From 1368b914e93a3af332f787d3d41c106d11bb90da Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 5 Jan 2021 22:09:57 -0500 Subject: sim: testsuite: flatten tree Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine. --- sim/testsuite/ChangeLog | 5 + sim/testsuite/Makefile.in | 1 - sim/testsuite/aarch64/ChangeLog | 83 + sim/testsuite/aarch64/adds.s | 98 + sim/testsuite/aarch64/addv.s | 50 + sim/testsuite/aarch64/allinsn.exp | 15 + sim/testsuite/aarch64/bit.s | 91 + sim/testsuite/aarch64/cmtst.s | 104 + sim/testsuite/aarch64/cnt.s | 33 + sim/testsuite/aarch64/fcmXX.s | 77 + sim/testsuite/aarch64/fcmp.s | 146 + sim/testsuite/aarch64/fcsel.s | 53 + sim/testsuite/aarch64/fcvtl.s | 59 + sim/testsuite/aarch64/fcvtz.s | 203 + sim/testsuite/aarch64/fminnm.s | 82 + sim/testsuite/aarch64/fstur.s | 137 + sim/testsuite/aarch64/ldn_multiple.s | 136 + sim/testsuite/aarch64/ldn_single.s | 102 + sim/testsuite/aarch64/ldnr.s | 178 + sim/testsuite/aarch64/mla.s | 105 + sim/testsuite/aarch64/mls.s | 105 + sim/testsuite/aarch64/mul.s | 99 + sim/testsuite/aarch64/pass.s | 7 + sim/testsuite/aarch64/stn_multiple.s | 171 + sim/testsuite/aarch64/stn_single.s | 124 + sim/testsuite/aarch64/sumov.s | 93 + sim/testsuite/aarch64/sumulh.s | 53 + sim/testsuite/aarch64/tbnz.s | 55 + sim/testsuite/aarch64/testutils.inc | 70 + sim/testsuite/aarch64/uzp.s | 216 + sim/testsuite/aarch64/xtl.s | 101 + sim/testsuite/aarch64/xtn.s | 79 + sim/testsuite/arm/ChangeLog | 122 + sim/testsuite/arm/adc.cgs | 43 + sim/testsuite/arm/add.cgs | 43 + sim/testsuite/arm/allinsn.exp | 28 + sim/testsuite/arm/and.cgs | 43 + sim/testsuite/arm/b.cgs | 261 + sim/testsuite/arm/bic.cgs | 43 + sim/testsuite/arm/bl.cgs | 21 + sim/testsuite/arm/bx.cgs | 12 + sim/testsuite/arm/cmn.cgs | 36 + sim/testsuite/arm/cmp.cgs | 36 + sim/testsuite/arm/eor.cgs | 36 + sim/testsuite/arm/hello.ms | 91 + sim/testsuite/arm/iwmmxt/iwmmxt.exp | 28 + sim/testsuite/arm/iwmmxt/tbcst.cgs | 65 + sim/testsuite/arm/iwmmxt/testutils.inc | 118 + sim/testsuite/arm/iwmmxt/textrm.cgs | 113 + sim/testsuite/arm/iwmmxt/tinsr.cgs | 65 + sim/testsuite/arm/iwmmxt/tmia.cgs | 35 + sim/testsuite/arm/iwmmxt/tmiaph.cgs | 35 + sim/testsuite/arm/iwmmxt/tmiaxy.cgs | 89 + sim/testsuite/arm/iwmmxt/tmovmsk.cgs | 65 + sim/testsuite/arm/iwmmxt/wacc.cgs | 77 + sim/testsuite/arm/iwmmxt/wadd.cgs | 251 + sim/testsuite/arm/iwmmxt/waligni.cgs | 43 + sim/testsuite/arm/iwmmxt/walignr.cgs | 137 + sim/testsuite/arm/iwmmxt/wand.cgs | 41 + sim/testsuite/arm/iwmmxt/wandn.cgs | 41 + sim/testsuite/arm/iwmmxt/wavg2.cgs | 121 + sim/testsuite/arm/iwmmxt/wcmpeq.cgs | 95 + sim/testsuite/arm/iwmmxt/wcmpgt.cgs | 173 + sim/testsuite/arm/iwmmxt/wmac.cgs | 121 + sim/testsuite/arm/iwmmxt/wmadd.cgs | 69 + sim/testsuite/arm/iwmmxt/wmax.cgs | 173 + sim/testsuite/arm/iwmmxt/wmin.cgs | 173 + sim/testsuite/arm/iwmmxt/wmov.cgs | 35 + sim/testsuite/arm/iwmmxt/wmul.cgs | 121 + sim/testsuite/arm/iwmmxt/wor.cgs | 41 + sim/testsuite/arm/iwmmxt/wpack.cgs | 173 + sim/testsuite/arm/iwmmxt/wror.cgs | 167 + sim/testsuite/arm/iwmmxt/wsad.cgs | 121 + sim/testsuite/arm/iwmmxt/wshufh.cgs | 35 + sim/testsuite/arm/iwmmxt/wsll.cgs | 167 + sim/testsuite/arm/iwmmxt/wsra.cgs | 167 + sim/testsuite/arm/iwmmxt/wsrl.cgs | 167 + sim/testsuite/arm/iwmmxt/wsub.cgs | 251 + sim/testsuite/arm/iwmmxt/wunpckeh.cgs | 137 + sim/testsuite/arm/iwmmxt/wunpckel.cgs | 137 + sim/testsuite/arm/iwmmxt/wunpckih.cgs | 95 + sim/testsuite/arm/iwmmxt/wunpckil.cgs | 95 + sim/testsuite/arm/iwmmxt/wxor.cgs | 41 + sim/testsuite/arm/iwmmxt/wzero.cgs | 29 + sim/testsuite/arm/ldm.cgs | 89 + sim/testsuite/arm/ldr.cgs | 192 + sim/testsuite/arm/ldrb.cgs | 192 + sim/testsuite/arm/ldrh.cgs | 132 + sim/testsuite/arm/ldrsb.cgs | 132 + sim/testsuite/arm/ldrsh.cgs | 132 + sim/testsuite/arm/misaligned1.ms | 61 + sim/testsuite/arm/misaligned2.ms | 60 + sim/testsuite/arm/misaligned3.ms | 62 + sim/testsuite/arm/misc.exp | 20 + sim/testsuite/arm/mla.cgs | 12 + sim/testsuite/arm/mov.cgs | 36 + sim/testsuite/arm/movw-movt.ms | 53 + sim/testsuite/arm/mrs.cgs | 24 + sim/testsuite/arm/msr.cgs | 24 + sim/testsuite/arm/mul.cgs | 12 + sim/testsuite/arm/mvn.cgs | 36 + sim/testsuite/arm/orr.cgs | 36 + sim/testsuite/arm/rsb.cgs | 36 + sim/testsuite/arm/rsc.cgs | 36 + sim/testsuite/arm/sbc.cgs | 36 + sim/testsuite/arm/smlal.cgs | 12 + sim/testsuite/arm/smull.cgs | 12 + sim/testsuite/arm/stm.cgs | 88 + sim/testsuite/arm/str.cgs | 192 + sim/testsuite/arm/strb.cgs | 192 + sim/testsuite/arm/strh.cgs | 132 + sim/testsuite/arm/sub.cgs | 36 + sim/testsuite/arm/swi.cgs | 12 + sim/testsuite/arm/swp.cgs | 12 + sim/testsuite/arm/swpb.cgs | 12 + sim/testsuite/arm/teq.cgs | 36 + sim/testsuite/arm/testutils.inc | 118 + sim/testsuite/arm/thumb/adc.cgs | 12 + sim/testsuite/arm/thumb/add-hd-hs.cgs | 12 + sim/testsuite/arm/thumb/add-hd-rs.cgs | 12 + sim/testsuite/arm/thumb/add-rd-hs.cgs | 12 + sim/testsuite/arm/thumb/add-sp.cgs | 12 + sim/testsuite/arm/thumb/add.cgs | 12 + sim/testsuite/arm/thumb/addi.cgs | 12 + sim/testsuite/arm/thumb/addi8.cgs | 12 + sim/testsuite/arm/thumb/allthumb.exp | 20 + sim/testsuite/arm/thumb/and.cgs | 12 + sim/testsuite/arm/thumb/asr.cgs | 14 + sim/testsuite/arm/thumb/b.cgs | 12 + sim/testsuite/arm/thumb/bcc.cgs | 12 + sim/testsuite/arm/thumb/bcs.cgs | 12 + sim/testsuite/arm/thumb/beq.cgs | 12 + sim/testsuite/arm/thumb/bge.cgs | 12 + sim/testsuite/arm/thumb/bgt.cgs | 12 + sim/testsuite/arm/thumb/bhi.cgs | 12 + sim/testsuite/arm/thumb/bic.cgs | 12 + sim/testsuite/arm/thumb/bl-hi.cgs | 12 + sim/testsuite/arm/thumb/bl-lo.cgs | 12 + sim/testsuite/arm/thumb/ble.cgs | 12 + sim/testsuite/arm/thumb/bls.cgs | 12 + sim/testsuite/arm/thumb/blt.cgs | 12 + sim/testsuite/arm/thumb/bmi.cgs | 12 + sim/testsuite/arm/thumb/bne.cgs | 12 + sim/testsuite/arm/thumb/bpl.cgs | 12 + sim/testsuite/arm/thumb/bvc.cgs | 12 + sim/testsuite/arm/thumb/bvs.cgs | 12 + sim/testsuite/arm/thumb/bx-hs.cgs | 12 + sim/testsuite/arm/thumb/bx-rs.cgs | 12 + sim/testsuite/arm/thumb/cmn.cgs | 12 + sim/testsuite/arm/thumb/cmp-hd-hs.cgs | 12 + sim/testsuite/arm/thumb/cmp-hd-rs.cgs | 12 + sim/testsuite/arm/thumb/cmp-rd-hs.cgs | 12 + sim/testsuite/arm/thumb/cmp.cgs | 14 + sim/testsuite/arm/thumb/eor.cgs | 12 + sim/testsuite/arm/thumb/lda-pc.cgs | 12 + sim/testsuite/arm/thumb/lda-sp.cgs | 12 + sim/testsuite/arm/thumb/ldmia.cgs | 12 + sim/testsuite/arm/thumb/ldr-imm.cgs | 12 + sim/testsuite/arm/thumb/ldr-pc.cgs | 12 + sim/testsuite/arm/thumb/ldr-sprel.cgs | 12 + sim/testsuite/arm/thumb/ldr.cgs | 12 + sim/testsuite/arm/thumb/ldrb-imm.cgs | 12 + sim/testsuite/arm/thumb/ldrb.cgs | 12 + sim/testsuite/arm/thumb/ldrh-imm.cgs | 12 + sim/testsuite/arm/thumb/ldrh.cgs | 12 + sim/testsuite/arm/thumb/ldsb.cgs | 12 + sim/testsuite/arm/thumb/ldsh.cgs | 12 + sim/testsuite/arm/thumb/lsl.cgs | 14 + sim/testsuite/arm/thumb/lsr.cgs | 14 + sim/testsuite/arm/thumb/mov-hd-hs.cgs | 12 + sim/testsuite/arm/thumb/mov-hd-rs.cgs | 12 + sim/testsuite/arm/thumb/mov-rd-hs.cgs | 12 + sim/testsuite/arm/thumb/mov.cgs | 12 + sim/testsuite/arm/thumb/mul.cgs | 12 + sim/testsuite/arm/thumb/mvn.cgs | 12 + sim/testsuite/arm/thumb/neg.cgs | 12 + sim/testsuite/arm/thumb/orr.cgs | 12 + sim/testsuite/arm/thumb/pop-pc.cgs | 12 + sim/testsuite/arm/thumb/pop.cgs | 12 + sim/testsuite/arm/thumb/push-lr.cgs | 12 + sim/testsuite/arm/thumb/push.cgs | 12 + sim/testsuite/arm/thumb/ror.cgs | 12 + sim/testsuite/arm/thumb/sbc.cgs | 12 + sim/testsuite/arm/thumb/stmia.cgs | 12 + sim/testsuite/arm/thumb/str-imm.cgs | 12 + sim/testsuite/arm/thumb/str-sprel.cgs | 12 + sim/testsuite/arm/thumb/str.cgs | 12 + sim/testsuite/arm/thumb/strb-imm.cgs | 12 + sim/testsuite/arm/thumb/strb.cgs | 12 + sim/testsuite/arm/thumb/strh-imm.cgs | 12 + sim/testsuite/arm/thumb/strh.cgs | 12 + sim/testsuite/arm/thumb/sub-sp.cgs | 12 + sim/testsuite/arm/thumb/sub.cgs | 12 + sim/testsuite/arm/thumb/subi.cgs | 12 + sim/testsuite/arm/thumb/subi8.cgs | 12 + sim/testsuite/arm/thumb/swi.cgs | 12 + sim/testsuite/arm/thumb/testutils.inc | 91 + sim/testsuite/arm/thumb/tst.cgs | 12 + sim/testsuite/arm/tst.cgs | 36 + sim/testsuite/arm/umlal.cgs | 12 + sim/testsuite/arm/umull.cgs | 12 + sim/testsuite/arm/xscale/blx.cgs | 31 + sim/testsuite/arm/xscale/mia.cgs | 35 + sim/testsuite/arm/xscale/miaph.cgs | 35 + sim/testsuite/arm/xscale/miaxy.cgs | 89 + sim/testsuite/arm/xscale/mra.cgs | 30 + sim/testsuite/arm/xscale/testutils.inc | 118 + sim/testsuite/arm/xscale/xscale.exp | 28 + sim/testsuite/avr/ChangeLog | 7 + sim/testsuite/avr/allinsn.exp | 15 + sim/testsuite/avr/pass.s | 7 + sim/testsuite/avr/testutils.inc | 42 + sim/testsuite/bfin/.gitignore | 1 + sim/testsuite/bfin/10272_small.s | 51 + sim/testsuite/bfin/10436.s | 39 + sim/testsuite/bfin/10622.s | 21 + sim/testsuite/bfin/10742.s | 17 + sim/testsuite/bfin/10799.s | 55 + sim/testsuite/bfin/11080.s | 40 + sim/testsuite/bfin/7641.s | 38 + sim/testsuite/bfin/ChangeLog | 370 + sim/testsuite/bfin/PN_generator.s | 78 + sim/testsuite/bfin/a0.s | 17 + sim/testsuite/bfin/a0shift.S | 169 + sim/testsuite/bfin/a1.s | 29 + sim/testsuite/bfin/a10.s | 176 + sim/testsuite/bfin/a11.S | 386 + sim/testsuite/bfin/a12.s | 40 + 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sim/testsuite/bfin/algnbug2.s | 69 + sim/testsuite/bfin/allinsn.exp | 43 + sim/testsuite/bfin/argc.c | 31 + sim/testsuite/bfin/ashift.s | 323 + sim/testsuite/bfin/ashift_flags.s | 84 + sim/testsuite/bfin/ashift_left.s | 17 + sim/testsuite/bfin/b0.S | 51 + sim/testsuite/bfin/b1.s | 12 + sim/testsuite/bfin/b2.S | 26 + sim/testsuite/bfin/brcc.s | 164 + sim/testsuite/bfin/brevadd.s | 20 + sim/testsuite/bfin/byteop16m.s | 76 + sim/testsuite/bfin/byteop16p.s | 74 + sim/testsuite/bfin/byteop1p.s | 75 + sim/testsuite/bfin/byteop2p.s | 58 + sim/testsuite/bfin/byteop3p.s | 119 + sim/testsuite/bfin/byteunpack.s | 45 + sim/testsuite/bfin/c_alu2op_arith_r_sft.s | 226 + sim/testsuite/bfin/c_alu2op_conv_b.s | 211 + sim/testsuite/bfin/c_alu2op_conv_h.s | 211 + sim/testsuite/bfin/c_alu2op_conv_mix.s | 186 + sim/testsuite/bfin/c_alu2op_conv_neg.s | 211 + sim/testsuite/bfin/c_alu2op_conv_toggle.s | 211 + sim/testsuite/bfin/c_alu2op_conv_xb.s | 211 + sim/testsuite/bfin/c_alu2op_conv_xh.s | 212 + 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sim/testsuite/bfin/c_brcc_kills_dmiss.s | 137 + sim/testsuite/bfin/c_cactrl_iflush_pr.s | 102 + sim/testsuite/bfin/c_cactrl_iflush_pr_pp.s | 100 + sim/testsuite/bfin/c_calla_ljump.s | 31 + sim/testsuite/bfin/c_calla_subr.s | 28 + sim/testsuite/bfin/c_cc2dreg.s | 56 + sim/testsuite/bfin/c_cc2stat_cc_ac.S | 240 + sim/testsuite/bfin/c_cc2stat_cc_an.s | 243 + sim/testsuite/bfin/c_cc2stat_cc_aq.s | 243 + sim/testsuite/bfin/c_cc2stat_cc_av0.S | 241 + sim/testsuite/bfin/c_cc2stat_cc_av1.S | 240 + sim/testsuite/bfin/c_cc2stat_cc_az.s | 243 + sim/testsuite/bfin/c_cc_flag_ccmv_depend.S | 80 + sim/testsuite/bfin/c_cc_flagdreg_mvbrsft.s | 87 + sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_s1.s | 99 + sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_sn.s | 118 + sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft.s | 83 + sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_s1.s | 98 + sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_sn.S | 127 + sim/testsuite/bfin/c_ccflag_a0a1.S | 143 + sim/testsuite/bfin/c_ccflag_dr_dr.s | 299 + sim/testsuite/bfin/c_ccflag_dr_dr_uu.s | 299 + sim/testsuite/bfin/c_ccflag_dr_imm3.s | 224 + sim/testsuite/bfin/c_ccflag_dr_imm3_uu.s | 221 + sim/testsuite/bfin/c_ccflag_pr_imm3.s | 539 + sim/testsuite/bfin/c_ccflag_pr_imm3_uu.s | 238 + sim/testsuite/bfin/c_ccflag_pr_pr.s | 262 + sim/testsuite/bfin/c_ccflag_pr_pr_uu.s | 212 + sim/testsuite/bfin/c_ccmv_cc_dr_dr.s | 124 + sim/testsuite/bfin/c_ccmv_cc_dr_pr.s | 61 + sim/testsuite/bfin/c_ccmv_cc_pr_pr.s | 111 + sim/testsuite/bfin/c_ccmv_ncc_dr_dr.s | 123 + sim/testsuite/bfin/c_ccmv_ncc_dr_pr.s | 60 + sim/testsuite/bfin/c_ccmv_ncc_pr_pr.s | 111 + sim/testsuite/bfin/c_comp3op_dr_and_dr.s | 412 + sim/testsuite/bfin/c_comp3op_dr_minus_dr.s | 412 + sim/testsuite/bfin/c_comp3op_dr_mix.s | 237 + sim/testsuite/bfin/c_comp3op_dr_or_dr.s | 412 + sim/testsuite/bfin/c_comp3op_dr_plus_dr.s | 412 + sim/testsuite/bfin/c_comp3op_dr_xor_dr.s | 412 + sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh1.s | 302 + sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh2.s | 302 + sim/testsuite/bfin/c_compi2opd_dr_add_i7_n.s | 164 + sim/testsuite/bfin/c_compi2opd_dr_add_i7_p.s | 147 + sim/testsuite/bfin/c_compi2opd_dr_eq_i7_n.s | 166 + sim/testsuite/bfin/c_compi2opd_dr_eq_i7_p.s | 147 + sim/testsuite/bfin/c_compi2opd_flags.S | 600 + sim/testsuite/bfin/c_compi2opd_flags_2.S | 600 + sim/testsuite/bfin/c_compi2opp_pr_add_i7_n.s | 149 + sim/testsuite/bfin/c_compi2opp_pr_add_i7_p.s | 116 + sim/testsuite/bfin/c_compi2opp_pr_eq_i7_n.s | 161 + sim/testsuite/bfin/c_compi2opp_pr_eq_i7_p.s | 131 + sim/testsuite/bfin/c_dagmodik_lnz_imgebl.s | 290 + sim/testsuite/bfin/c_dagmodik_lnz_imltbl.s | 289 + sim/testsuite/bfin/c_dagmodik_lz_inc_dec.s | 140 + sim/testsuite/bfin/c_dagmodim_lnz_imgebl.s | 108 + sim/testsuite/bfin/c_dagmodim_lnz_imltbl.s | 109 + sim/testsuite/bfin/c_dagmodim_lz_inc_dec.s | 98 + sim/testsuite/bfin/c_dsp32alu_a0_pm_a1.s | 39 + sim/testsuite/bfin/c_dsp32alu_a0a1s.s | 82 + sim/testsuite/bfin/c_dsp32alu_a_abs_a.s | 34 + sim/testsuite/bfin/c_dsp32alu_a_neg_a.s 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sim/testsuite/sim/bfin/c_dsp32alu_rpm.s | 264 - sim/testsuite/sim/bfin/c_dsp32alu_rpp.s | 266 - sim/testsuite/sim/bfin/c_dsp32alu_rr_lph_a1a0.s | 33 - sim/testsuite/sim/bfin/c_dsp32alu_rrpm.s | 265 - sim/testsuite/sim/bfin/c_dsp32alu_rrpm_aa.s | 70 - sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp.s | 263 - sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft.s | 262 - sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft_x.s | 261 - sim/testsuite/sim/bfin/c_dsp32alu_rrppmm.s | 263 - sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft.s | 261 - sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft_x.s | 261 - sim/testsuite/sim/bfin/c_dsp32alu_saa.s | 70 - sim/testsuite/sim/bfin/c_dsp32alu_sat_aa.S | 41 - sim/testsuite/sim/bfin/c_dsp32alu_search.s | 74 - sim/testsuite/sim/bfin/c_dsp32alu_sgn.s | 39 - sim/testsuite/sim/bfin/c_dsp32mac_a1a0.s | 255 - sim/testsuite/sim/bfin/c_dsp32mac_a1a0_iuw32.s | 1014 - sim/testsuite/sim/bfin/c_dsp32mac_a1a0_m.s | 340 - sim/testsuite/sim/bfin/c_dsp32mac_dr_a0.s | 124 - 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sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_is.s | 292 - sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_m.s | 152 - sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_s.s | 306 - sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_u.s | 292 - sim/testsuite/sim/bfin/c_dsp32mac_pair_mix.s | 69 - sim/testsuite/sim/bfin/c_dsp32mult_dr.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_i.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_ih.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_is.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_iu.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_m.s | 211 - sim/testsuite/sim/bfin/c_dsp32mult_dr_m_i.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_m_iutsh.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_m_s.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_m_t.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_m_u.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_mix.s | 196 - sim/testsuite/sim/bfin/c_dsp32mult_dr_s.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_t.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_tu.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_dr_u.s | 212 - sim/testsuite/sim/bfin/c_dsp32mult_pair.s | 179 - sim/testsuite/sim/bfin/c_dsp32mult_pair_i.s | 179 - sim/testsuite/sim/bfin/c_dsp32mult_pair_is.s | 179 - sim/testsuite/sim/bfin/c_dsp32mult_pair_m.s | 178 - sim/testsuite/sim/bfin/c_dsp32mult_pair_m_i.s | 178 - sim/testsuite/sim/bfin/c_dsp32mult_pair_m_is.s | 178 - sim/testsuite/sim/bfin/c_dsp32mult_pair_m_s.s | 178 - sim/testsuite/sim/bfin/c_dsp32mult_pair_m_u.s | 178 - sim/testsuite/sim/bfin/c_dsp32mult_pair_s.s | 180 - sim/testsuite/sim/bfin/c_dsp32mult_pair_u.s | 179 - sim/testsuite/sim/bfin/c_dsp32shift_a0alr.s | 211 - sim/testsuite/sim/bfin/c_dsp32shift_af.s | 186 - sim/testsuite/sim/bfin/c_dsp32shift_af_s.s | 186 - sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln.s | 423 - sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln_s.s | 423 - sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp.s | 423 - sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp_s.s | 423 - sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn.s | 423 - sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn_s.s | 424 - sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp.s | 423 - sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp_s.s | 423 - sim/testsuite/sim/bfin/c_dsp32shift_ahh.s | 430 - sim/testsuite/sim/bfin/c_dsp32shift_ahh_s.s | 430 - sim/testsuite/sim/bfin/c_dsp32shift_align16.s | 210 - sim/testsuite/sim/bfin/c_dsp32shift_align24.s | 210 - sim/testsuite/sim/bfin/c_dsp32shift_align8.s | 210 - sim/testsuite/sim/bfin/c_dsp32shift_amix.s | 142 - sim/testsuite/sim/bfin/c_dsp32shift_bitmux.s | 486 - sim/testsuite/sim/bfin/c_dsp32shift_bxor.s | 126 - sim/testsuite/sim/bfin/c_dsp32shift_expadj_h.s | 214 - sim/testsuite/sim/bfin/c_dsp32shift_expadj_l.s | 212 - sim/testsuite/sim/bfin/c_dsp32shift_expadj_r.s | 212 - sim/testsuite/sim/bfin/c_dsp32shift_expexp_r.s | 212 - sim/testsuite/sim/bfin/c_dsp32shift_fdepx.s | 210 - sim/testsuite/sim/bfin/c_dsp32shift_fextx.s | 210 - sim/testsuite/sim/bfin/c_dsp32shift_lf.s | 422 - sim/testsuite/sim/bfin/c_dsp32shift_lhalf_ln.s | 422 - sim/testsuite/sim/bfin/c_dsp32shift_lhalf_lp.s | 422 - sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rn.s | 425 - sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rp.s | 423 - sim/testsuite/sim/bfin/c_dsp32shift_lhh.s | 311 - sim/testsuite/sim/bfin/c_dsp32shift_lmix.s | 136 - sim/testsuite/sim/bfin/c_dsp32shift_ones.s | 214 - sim/testsuite/sim/bfin/c_dsp32shift_pack.s | 411 - sim/testsuite/sim/bfin/c_dsp32shift_rot.s | 427 - sim/testsuite/sim/bfin/c_dsp32shift_rot_mix.s | 437 - sim/testsuite/sim/bfin/c_dsp32shift_signbits_r.s | 214 - sim/testsuite/sim/bfin/c_dsp32shift_signbits_rh.s | 214 - sim/testsuite/sim/bfin/c_dsp32shift_signbits_rl.s | 210 - sim/testsuite/sim/bfin/c_dsp32shift_vmax.s | 113 - sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s | 113 - sim/testsuite/sim/bfin/c_dsp32shiftim_a0alr.s | 213 - sim/testsuite/sim/bfin/c_dsp32shiftim_af.s | 63 - sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s | 63 - sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln.s | 406 - sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln_s.s | 408 - sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp.s | 418 - sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp_s.s | 415 - sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn.s | 418 - sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn_s.s | 418 - sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp.s | 420 - sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp_s.s | 422 - sim/testsuite/sim/bfin/c_dsp32shiftim_ahh.s | 65 - sim/testsuite/sim/bfin/c_dsp32shiftim_ahh_s.s | 65 - sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s | 149 - sim/testsuite/sim/bfin/c_dsp32shiftim_lf.s | 63 - sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_ln.s | 401 - sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_lp.s | 418 - sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rn.s | 424 - sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rp.s | 421 - sim/testsuite/sim/bfin/c_dsp32shiftim_lhh.s | 65 - sim/testsuite/sim/bfin/c_dsp32shiftim_lmix.s | 138 - sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s | 62 - sim/testsuite/sim/bfin/c_dspldst_ld_dr_i.s | 168 - sim/testsuite/sim/bfin/c_dspldst_ld_dr_ipp.s | 348 - sim/testsuite/sim/bfin/c_dspldst_ld_dr_ippm.s | 328 - sim/testsuite/sim/bfin/c_dspldst_ld_drhi_i.s | 168 - sim/testsuite/sim/bfin/c_dspldst_ld_drhi_ipp.s | 364 - sim/testsuite/sim/bfin/c_dspldst_ld_drlo_i.s | 164 - sim/testsuite/sim/bfin/c_dspldst_ld_drlo_ipp.s | 355 - sim/testsuite/sim/bfin/c_dspldst_st_dr_i.s | 185 - sim/testsuite/sim/bfin/c_dspldst_st_dr_ipp.s | 326 - sim/testsuite/sim/bfin/c_dspldst_st_dr_ippm.s | 279 - sim/testsuite/sim/bfin/c_dspldst_st_drhi_i.s | 161 - sim/testsuite/sim/bfin/c_dspldst_st_drhi_ipp.s | 355 - sim/testsuite/sim/bfin/c_dspldst_st_drlo_i.s | 163 - sim/testsuite/sim/bfin/c_dspldst_st_drlo_ipp.s | 351 - sim/testsuite/sim/bfin/c_except_illopcode.S | 99 - sim/testsuite/sim/bfin/c_except_sys_sstep.S | 252 - sim/testsuite/sim/bfin/c_except_user_mode.S | 349 - sim/testsuite/sim/bfin/c_interr_disable.S | 323 - sim/testsuite/sim/bfin/c_interr_disable_enable.S | 344 - sim/testsuite/sim/bfin/c_interr_excpt.S | 290 - sim/testsuite/sim/bfin/c_interr_loopsetup_stld.S | 224 - sim/testsuite/sim/bfin/c_interr_nested.S | 289 - sim/testsuite/sim/bfin/c_interr_nmi.S | 318 - sim/testsuite/sim/bfin/c_interr_pending.S | 324 - sim/testsuite/sim/bfin/c_interr_pending_2.S | 268 - sim/testsuite/sim/bfin/c_interr_timer.S | 384 - sim/testsuite/sim/bfin/c_interr_timer_reload.S | 286 - sim/testsuite/sim/bfin/c_interr_timer_tcount.S | 242 - sim/testsuite/sim/bfin/c_interr_timer_tscale.S | 304 - sim/testsuite/sim/bfin/c_ldimmhalf_dreg.s | 60 - sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s | 85 - sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s | 89 - sim/testsuite/sim/bfin/c_ldimmhalf_h_dr.s | 82 - sim/testsuite/sim/bfin/c_ldimmhalf_h_ibml.s | 165 - sim/testsuite/sim/bfin/c_ldimmhalf_h_pr.s | 74 - sim/testsuite/sim/bfin/c_ldimmhalf_l_dr.s | 82 - sim/testsuite/sim/bfin/c_ldimmhalf_l_ibml.s | 165 - sim/testsuite/sim/bfin/c_ldimmhalf_l_pr.s | 76 - sim/testsuite/sim/bfin/c_ldimmhalf_lz_dr.s | 81 - sim/testsuite/sim/bfin/c_ldimmhalf_lz_ibml.s | 168 - sim/testsuite/sim/bfin/c_ldimmhalf_lz_pr.s | 72 - sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_dr.s | 113 - sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_ibml.s | 216 - sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_pr.s | 102 - sim/testsuite/sim/bfin/c_ldimmhalf_pibml.s | 212 - sim/testsuite/sim/bfin/c_ldst_ld_d_p.s | 372 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_b.s | 353 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_h.s | 351 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm.s | 417 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_b.s | 353 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_h.s | 330 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xb.s | 341 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xh.s | 355 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp.s | 371 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_b.s | 324 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_h.s | 350 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xb.s | 355 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xh.s | 333 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_ppmm_hbx.s | 656 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_xb.s | 326 - sim/testsuite/sim/bfin/c_ldst_ld_d_p_xh.s | 354 - sim/testsuite/sim/bfin/c_ldst_ld_p_p.s | 327 - sim/testsuite/sim/bfin/c_ldst_ld_p_p_mm.s | 406 - sim/testsuite/sim/bfin/c_ldst_ld_p_p_pp.s | 335 - sim/testsuite/sim/bfin/c_ldst_st_p_d.s | 299 - sim/testsuite/sim/bfin/c_ldst_st_p_d_b.s | 300 - sim/testsuite/sim/bfin/c_ldst_st_p_d_h.s | 280 - sim/testsuite/sim/bfin/c_ldst_st_p_d_mm.s | 601 - sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_b.s | 498 - sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_h.s | 554 - sim/testsuite/sim/bfin/c_ldst_st_p_d_pp.s | 804 - sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_b.s | 455 - sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_h.s | 457 - sim/testsuite/sim/bfin/c_ldst_st_p_p.s | 128 - sim/testsuite/sim/bfin/c_ldst_st_p_p_mm.s | 428 - sim/testsuite/sim/bfin/c_ldst_st_p_p_pp.s | 397 - sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_b.s | 554 - sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_h.s | 595 - sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xb.s | 594 - sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s | 595 - sim/testsuite/sim/bfin/c_ldstidxl_ld_dreg.s | 554 - sim/testsuite/sim/bfin/c_ldstidxl_ld_preg.s | 672 - sim/testsuite/sim/bfin/c_ldstidxl_st_dr_b.s | 612 - sim/testsuite/sim/bfin/c_ldstidxl_st_dr_h.s | 609 - sim/testsuite/sim/bfin/c_ldstidxl_st_dreg.s | 780 - sim/testsuite/sim/bfin/c_ldstidxl_st_preg.s | 709 - sim/testsuite/sim/bfin/c_ldstii_ld_dr_h.s | 541 - sim/testsuite/sim/bfin/c_ldstii_ld_dr_xh.s | 541 - sim/testsuite/sim/bfin/c_ldstii_ld_dreg.s | 540 - sim/testsuite/sim/bfin/c_ldstii_ld_preg.s | 564 - sim/testsuite/sim/bfin/c_ldstii_st_dr_h.s | 605 - sim/testsuite/sim/bfin/c_ldstii_st_dreg.s | 640 - sim/testsuite/sim/bfin/c_ldstii_st_preg.s | 603 - sim/testsuite/sim/bfin/c_ldstiifp_ld_dreg.s | 528 - sim/testsuite/sim/bfin/c_ldstiifp_ld_preg.s | 511 - sim/testsuite/sim/bfin/c_ldstiifp_st_dreg.s | 641 - sim/testsuite/sim/bfin/c_ldstiifp_st_preg.s | 618 - sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_hi.s | 411 - sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_lo.s | 410 - sim/testsuite/sim/bfin/c_ldstpmod_ld_dreg.s | 462 - sim/testsuite/sim/bfin/c_ldstpmod_ld_h_xh.s | 458 - sim/testsuite/sim/bfin/c_ldstpmod_ld_lohi.s | 462 - sim/testsuite/sim/bfin/c_ldstpmod_st_dr_hi.s | 400 - sim/testsuite/sim/bfin/c_ldstpmod_st_dr_lo.s | 401 - sim/testsuite/sim/bfin/c_ldstpmod_st_dreg.s | 623 - sim/testsuite/sim/bfin/c_ldstpmod_st_lohi.s | 625 - sim/testsuite/sim/bfin/c_linkage.s | 60 - sim/testsuite/sim/bfin/c_logi2op_alshft_mix.s | 143 - sim/testsuite/sim/bfin/c_logi2op_arith_shft.s | 223 - sim/testsuite/sim/bfin/c_logi2op_bitclr.s | 92 - sim/testsuite/sim/bfin/c_logi2op_bitset.s | 92 - sim/testsuite/sim/bfin/c_logi2op_bittgl.s | 165 - sim/testsuite/sim/bfin/c_logi2op_bittst.s | 583 - sim/testsuite/sim/bfin/c_logi2op_log_l_shft.s | 222 - .../sim/bfin/c_logi2op_log_l_shft_astat.S | 82 - sim/testsuite/sim/bfin/c_logi2op_log_r_shft.s | 222 - .../sim/bfin/c_logi2op_log_r_shft_astat.S | 82 - sim/testsuite/sim/bfin/c_logi2op_nbittst.s | 584 - sim/testsuite/sim/bfin/c_loopsetup_nested.s | 166 - sim/testsuite/sim/bfin/c_loopsetup_nested_bot.s | 165 - sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s | 184 - sim/testsuite/sim/bfin/c_loopsetup_nested_top.s | 166 - sim/testsuite/sim/bfin/c_loopsetup_overlap.s | 167 - sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc0.s | 95 - sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc1.s | 94 - sim/testsuite/sim/bfin/c_loopsetup_preg_lc0.s | 95 - sim/testsuite/sim/bfin/c_loopsetup_preg_lc1.s | 93 - sim/testsuite/sim/bfin/c_loopsetup_preg_stld.s | 194 - sim/testsuite/sim/bfin/c_loopsetup_prelc.s | 145 - sim/testsuite/sim/bfin/c_loopsetup_topbotcntr.s | 110 - sim/testsuite/sim/bfin/c_mmr_interr_ctl.s | 398 - sim/testsuite/sim/bfin/c_mmr_loop.S | 417 - sim/testsuite/sim/bfin/c_mmr_loop_user_except.S | 325 - sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S | 307 - sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S | 308 - sim/testsuite/sim/bfin/c_mmr_timer.S | 282 - sim/testsuite/sim/bfin/c_mode_supervisor.S | 287 - sim/testsuite/sim/bfin/c_mode_user.S | 338 - sim/testsuite/sim/bfin/c_mode_user_superivsor.S | 353 - sim/testsuite/sim/bfin/c_multi_issue_dsp_ld_ld.s | 197 - sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_1.s | 198 - sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_2.s | 198 - sim/testsuite/sim/bfin/c_progctrl_call_pcpr.s | 63 - sim/testsuite/sim/bfin/c_progctrl_call_pr.s | 32 - sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S | 330 - sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S | 280 - sim/testsuite/sim/bfin/c_progctrl_except_rtx.S | 96 - sim/testsuite/sim/bfin/c_progctrl_excpt.S | 261 - sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s | 58 - sim/testsuite/sim/bfin/c_progctrl_jump_pr.s | 56 - sim/testsuite/sim/bfin/c_progctrl_nop.s | 55 - sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S | 285 - sim/testsuite/sim/bfin/c_progctrl_rts.s | 36 - sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s | 163 - sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s | 162 - sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s | 167 - sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s | 213 - sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s | 203 - sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s | 173 - sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s | 83 - sim/testsuite/sim/bfin/c_regmv_acc_acc.s | 125 - sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s | 148 - sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s | 191 - sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s | 245 - sim/testsuite/sim/bfin/c_regmv_dr_dr.s | 209 - sim/testsuite/sim/bfin/c_regmv_dr_imlb.s | 539 - sim/testsuite/sim/bfin/c_regmv_dr_pr.s | 107 - sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s | 664 - sim/testsuite/sim/bfin/c_regmv_imlb_dep_stall.s | 335 - sim/testsuite/sim/bfin/c_regmv_imlb_dr.s | 313 - sim/testsuite/sim/bfin/c_regmv_imlb_imlb.s | 925 - sim/testsuite/sim/bfin/c_regmv_imlb_pr.s | 302 - sim/testsuite/sim/bfin/c_regmv_pr_dep_nostall.s | 280 - sim/testsuite/sim/bfin/c_regmv_pr_dep_stall.s | 237 - sim/testsuite/sim/bfin/c_regmv_pr_dr.s | 147 - sim/testsuite/sim/bfin/c_regmv_pr_imlb.s | 382 - sim/testsuite/sim/bfin/c_regmv_pr_pr.s | 95 - sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S | 342 - sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S | 359 - sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S | 359 - sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S | 341 - sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S | 377 - sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S | 393 - sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S | 375 - .../sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S | 377 - .../sim/bfin/c_seq_ex1_raise_call_mv_pop.S | 393 - sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S | 375 - sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S | 377 - sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S | 386 - sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S | 386 - sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S | 385 - .../sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S | 385 - sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S | 440 - sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S | 442 - sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S | 443 - .../sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S | 442 - sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S | 446 - .../sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S | 446 - sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S | 455 - sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S | 447 - sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S | 466 - sim/testsuite/sim/bfin/c_ujump.s | 52 - sim/testsuite/sim/bfin/cc-alu.S | 126 - sim/testsuite/sim/bfin/cc-astat-bits.s | 101 - sim/testsuite/sim/bfin/cc0.s | 30 - sim/testsuite/sim/bfin/cc1.s | 26 - sim/testsuite/sim/bfin/cc5.S | 90 - sim/testsuite/sim/bfin/cec-exact-exception.S | 54 - sim/testsuite/sim/bfin/cec-ifetch.S | 69 - sim/testsuite/sim/bfin/cec-multi-pending.S | 182 - sim/testsuite/sim/bfin/cec-no-snen-reti.S | 128 - sim/testsuite/sim/bfin/cec-non-operating-env.s | 37 - sim/testsuite/sim/bfin/cec-raise-reti.S | 111 - sim/testsuite/sim/bfin/cec-snen-reti.S | 122 - sim/testsuite/sim/bfin/cec-syscfg-ssstep.S | 72 - sim/testsuite/sim/bfin/cec-system-call.S | 64 - sim/testsuite/sim/bfin/cir.s | 20 - sim/testsuite/sim/bfin/cir1.s | 84 - sim/testsuite/sim/bfin/cli-sti.s | 25 - sim/testsuite/sim/bfin/cmpacc.s | 50 - sim/testsuite/sim/bfin/cmpdreg.S | 40 - sim/testsuite/sim/bfin/compare.s | 15 - sim/testsuite/sim/bfin/conv_enc_gen.s | 101 - sim/testsuite/sim/bfin/cycles.s | 41 - sim/testsuite/sim/bfin/d0.s | 31 - sim/testsuite/sim/bfin/d1.s | 17 - sim/testsuite/sim/bfin/d2.s | 56 - sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S | 545 - sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S | 544 - 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- sim/testsuite/sim/frv/cstd.cgs | 221 - sim/testsuite/sim/frv/cstdf.cgs | 222 - sim/testsuite/sim/frv/cstdfu.cgs | 248 - sim/testsuite/sim/frv/cstdu.cgs | 251 - sim/testsuite/sim/frv/cstf.cgs | 126 - sim/testsuite/sim/frv/cstfu.cgs | 158 - sim/testsuite/sim/frv/csth.cgs | 120 - sim/testsuite/sim/frv/csthf.cgs | 120 - sim/testsuite/sim/frv/csthfu.cgs | 150 - sim/testsuite/sim/frv/csthu.cgs | 150 - sim/testsuite/sim/frv/cstq.cgs | 355 - sim/testsuite/sim/frv/cstu.cgs | 152 - sim/testsuite/sim/frv/csub.cgs | 108 - sim/testsuite/sim/frv/csubcc.cgs | 156 - sim/testsuite/sim/frv/cswap.cgs | 212 - sim/testsuite/sim/frv/cudiv.cgs | 96 - sim/testsuite/sim/frv/cxor.cgs | 180 - sim/testsuite/sim/frv/cxorcc.cgs | 180 - sim/testsuite/sim/frv/dcef.cgs | 50 - sim/testsuite/sim/frv/dcei.cgs | 27 - sim/testsuite/sim/frv/dcf.cgs | 39 - sim/testsuite/sim/frv/dci.cgs | 22 - sim/testsuite/sim/frv/exit47.ms | 11 - sim/testsuite/sim/frv/fabsd.cgs | 26 - sim/testsuite/sim/frv/fabss.cgs | 25 - sim/testsuite/sim/frv/faddd.cgs | 93 - sim/testsuite/sim/frv/fadds.cgs | 92 - sim/testsuite/sim/frv/fbeq.cgs | 61 - sim/testsuite/sim/frv/fbeqlr.cgs | 84 - sim/testsuite/sim/frv/fbge.cgs | 69 - sim/testsuite/sim/frv/fbgelr.cgs | 88 - sim/testsuite/sim/frv/fbgt.cgs | 61 - sim/testsuite/sim/frv/fbgtlr.cgs | 84 - sim/testsuite/sim/frv/fble.cgs | 69 - sim/testsuite/sim/frv/fblelr.cgs | 89 - sim/testsuite/sim/frv/fblg.cgs | 69 - sim/testsuite/sim/frv/fblglr.cgs | 88 - sim/testsuite/sim/frv/fblt.cgs | 61 - sim/testsuite/sim/frv/fbltlr.cgs | 84 - sim/testsuite/sim/frv/fbne.cgs | 73 - sim/testsuite/sim/frv/fbnelr.cgs | 90 - sim/testsuite/sim/frv/fbno.cgs | 45 - sim/testsuite/sim/frv/fbnolr.cgs | 47 - sim/testsuite/sim/frv/fbo.cgs | 73 - sim/testsuite/sim/frv/fbolr.cgs | 90 - sim/testsuite/sim/frv/fbra.cgs | 75 - sim/testsuite/sim/frv/fbralr.cgs | 91 - sim/testsuite/sim/frv/fbu.cgs | 61 - sim/testsuite/sim/frv/fbue.cgs | 69 - sim/testsuite/sim/frv/fbuelr.cgs | 88 - sim/testsuite/sim/frv/fbug.cgs | 69 - sim/testsuite/sim/frv/fbuge.cgs | 73 - sim/testsuite/sim/frv/fbugelr.cgs | 90 - sim/testsuite/sim/frv/fbuglr.cgs | 88 - sim/testsuite/sim/frv/fbul.cgs | 69 - sim/testsuite/sim/frv/fbule.cgs | 73 - sim/testsuite/sim/frv/fbulelr.cgs | 90 - sim/testsuite/sim/frv/fbullr.cgs | 88 - sim/testsuite/sim/frv/fbulr.cgs | 84 - sim/testsuite/sim/frv/fcbeqlr.cgs | 262 - sim/testsuite/sim/frv/fcbgelr.cgs | 270 - sim/testsuite/sim/frv/fcbgtlr.cgs | 262 - sim/testsuite/sim/frv/fcblelr.cgs | 270 - sim/testsuite/sim/frv/fcblglr.cgs | 270 - sim/testsuite/sim/frv/fcbltlr.cgs | 262 - sim/testsuite/sim/frv/fcbnelr.cgs | 274 - sim/testsuite/sim/frv/fcbnolr.cgs | 185 - sim/testsuite/sim/frv/fcbolr.cgs | 274 - sim/testsuite/sim/frv/fcbralr.cgs | 276 - sim/testsuite/sim/frv/fcbuelr.cgs | 270 - sim/testsuite/sim/frv/fcbugelr.cgs | 274 - sim/testsuite/sim/frv/fcbuglr.cgs | 270 - sim/testsuite/sim/frv/fcbulelr.cgs | 274 - sim/testsuite/sim/frv/fcbullr.cgs | 270 - sim/testsuite/sim/frv/fcbulr.cgs | 262 - sim/testsuite/sim/frv/fckeq.cgs | 90 - sim/testsuite/sim/frv/fckge.cgs | 90 - sim/testsuite/sim/frv/fckgt.cgs | 90 - sim/testsuite/sim/frv/fckle.cgs | 90 - sim/testsuite/sim/frv/fcklg.cgs | 90 - sim/testsuite/sim/frv/fcklt.cgs | 90 - sim/testsuite/sim/frv/fckne.cgs | 90 - sim/testsuite/sim/frv/fckno.cgs | 90 - sim/testsuite/sim/frv/fcko.cgs | 90 - sim/testsuite/sim/frv/fckra.cgs | 90 - sim/testsuite/sim/frv/fcku.cgs | 90 - sim/testsuite/sim/frv/fckue.cgs | 90 - sim/testsuite/sim/frv/fckug.cgs | 90 - sim/testsuite/sim/frv/fckuge.cgs | 90 - sim/testsuite/sim/frv/fckul.cgs | 90 - sim/testsuite/sim/frv/fckule.cgs | 90 - sim/testsuite/sim/frv/fcmpd.cgs | 601 - sim/testsuite/sim/frv/fcmps.cgs | 600 - sim/testsuite/sim/frv/fdabss.cgs | 25 - sim/testsuite/sim/frv/fdadds.cgs | 134 - sim/testsuite/sim/frv/fdcmps.cgs | 985 - sim/testsuite/sim/frv/fddivs.cgs | 195 - sim/testsuite/sim/frv/fditos.cgs | 25 - sim/testsuite/sim/frv/fdivd.cgs | 128 - sim/testsuite/sim/frv/fdivs.cgs | 127 - sim/testsuite/sim/frv/fdmadds.cgs | 226 - sim/testsuite/sim/frv/fdmas.cgs | 265 - sim/testsuite/sim/frv/fdmovs.cgs | 45 - sim/testsuite/sim/frv/fdmss.cgs | 235 - sim/testsuite/sim/frv/fdmulcs.cgs | 201 - sim/testsuite/sim/frv/fdmuls.cgs | 193 - sim/testsuite/sim/frv/fdnegs.cgs | 25 - sim/testsuite/sim/frv/fdsads.cgs | 119 - sim/testsuite/sim/frv/fdsqrts.cgs | 17 - sim/testsuite/sim/frv/fdstoi.cgs | 23 - sim/testsuite/sim/frv/fdsubs.cgs | 117 - sim/testsuite/sim/frv/fdtoi.cgs | 32 - sim/testsuite/sim/frv/fitod.cgs | 26 - sim/testsuite/sim/frv/fitos.cgs | 25 - sim/testsuite/sim/frv/fmad.cgs | 161 - sim/testsuite/sim/frv/fmaddd.cgs | 143 - sim/testsuite/sim/frv/fmadds.cgs | 143 - sim/testsuite/sim/frv/fmas.cgs | 161 - sim/testsuite/sim/frv/fmovd.cgs | 48 - sim/testsuite/sim/frv/fmovs.cgs | 45 - sim/testsuite/sim/frv/fmsd.cgs | 146 - sim/testsuite/sim/frv/fmss.cgs | 146 - sim/testsuite/sim/frv/fmsubd.cgs | 144 - sim/testsuite/sim/frv/fmsubs.cgs | 144 - sim/testsuite/sim/frv/fmuld.cgs | 126 - sim/testsuite/sim/frv/fmuls.cgs | 125 - sim/testsuite/sim/frv/fnegd.cgs | 26 - sim/testsuite/sim/frv/fnegs.cgs | 25 - sim/testsuite/sim/frv/fnop.cgs | 12 - sim/testsuite/sim/frv/fr400/addss.cgs | 36 - sim/testsuite/sim/frv/fr400/allinsn.exp | 19 - sim/testsuite/sim/frv/fr400/csdiv.cgs | 187 - sim/testsuite/sim/frv/fr400/maddaccs.cgs | 131 - sim/testsuite/sim/frv/fr400/masaccs.cgs | 151 - sim/testsuite/sim/frv/fr400/maveh.cgs | 319 - sim/testsuite/sim/frv/fr400/mclracc.cgs | 79 - sim/testsuite/sim/frv/fr400/mhdseth.cgs | 22 - sim/testsuite/sim/frv/fr400/mhdsets.cgs | 20 - sim/testsuite/sim/frv/fr400/mhsethih.cgs | 22 - sim/testsuite/sim/frv/fr400/mhsethis.cgs | 25 - sim/testsuite/sim/frv/fr400/mhsetloh.cgs | 27 - sim/testsuite/sim/frv/fr400/mhsetlos.cgs | 25 - sim/testsuite/sim/frv/fr400/movgs.cgs | 50 - sim/testsuite/sim/frv/fr400/movsg.cgs | 65 - sim/testsuite/sim/frv/fr400/msubaccs.cgs | 131 - sim/testsuite/sim/frv/fr400/scutss.cgs | 664 - sim/testsuite/sim/frv/fr400/sdiv.cgs | 71 - sim/testsuite/sim/frv/fr400/sdivi.cgs | 70 - sim/testsuite/sim/frv/fr400/slass.cgs | 104 - sim/testsuite/sim/frv/fr400/smass.cgs | 359 - sim/testsuite/sim/frv/fr400/smsss.cgs | 354 - sim/testsuite/sim/frv/fr400/smu.cgs | 237 - sim/testsuite/sim/frv/fr400/subss.cgs | 43 - sim/testsuite/sim/frv/fr400/udiv.cgs | 46 - sim/testsuite/sim/frv/fr400/udivi.cgs | 47 - sim/testsuite/sim/frv/fr500/allinsn.exp | 19 - sim/testsuite/sim/frv/fr500/cmqaddhss.cgs | 444 - sim/testsuite/sim/frv/fr500/cmqaddhus.cgs | 360 - sim/testsuite/sim/frv/fr500/cmqsubhss.cgs | 448 - sim/testsuite/sim/frv/fr500/cmqsubhus.cgs | 370 - sim/testsuite/sim/frv/fr500/dcpl.cgs | 65 - sim/testsuite/sim/frv/fr500/dcul.cgs | 118 - sim/testsuite/sim/frv/fr500/mclracc.cgs | 79 - sim/testsuite/sim/frv/fr500/mqaddhss.cgs | 79 - sim/testsuite/sim/frv/fr500/mqaddhus.cgs | 65 - sim/testsuite/sim/frv/fr500/mqsubhss.cgs | 79 - sim/testsuite/sim/frv/fr500/mqsubhus.cgs | 66 - sim/testsuite/sim/frv/fr550/allinsn.exp | 19 - sim/testsuite/sim/frv/fr550/cmaddhss.cgs | 547 - sim/testsuite/sim/frv/fr550/cmaddhus.cgs | 481 - sim/testsuite/sim/frv/fr550/cmcpxiu.cgs | 492 - sim/testsuite/sim/frv/fr550/cmcpxru.cgs | 528 - sim/testsuite/sim/frv/fr550/cmmachs.cgs | 1545 - sim/testsuite/sim/frv/fr550/cmmachu.cgs | 858 - sim/testsuite/sim/frv/fr550/cmqaddhss.cgs | 429 - sim/testsuite/sim/frv/fr550/cmqaddhus.cgs | 345 - sim/testsuite/sim/frv/fr550/cmqmachs.cgs | 1262 - sim/testsuite/sim/frv/fr550/cmqmachu.cgs | 870 - sim/testsuite/sim/frv/fr550/cmqsubhss.cgs | 429 - sim/testsuite/sim/frv/fr550/cmqsubhus.cgs | 351 - sim/testsuite/sim/frv/fr550/cmsubhss.cgs | 547 - sim/testsuite/sim/frv/fr550/cmsubhus.cgs | 427 - sim/testsuite/sim/frv/fr550/dcpl.cgs | 65 - sim/testsuite/sim/frv/fr550/dcul.cgs | 118 - sim/testsuite/sim/frv/fr550/mabshs.cgs | 64 - sim/testsuite/sim/frv/fr550/maddaccs.cgs | 128 - sim/testsuite/sim/frv/fr550/maddhss.cgs | 97 - sim/testsuite/sim/frv/fr550/maddhus.cgs | 86 - sim/testsuite/sim/frv/fr550/masaccs.cgs | 148 - sim/testsuite/sim/frv/fr550/mdaddaccs.cgs | 102 - sim/testsuite/sim/frv/fr550/mdasaccs.cgs | 122 - sim/testsuite/sim/frv/fr550/mdsubaccs.cgs | 102 - sim/testsuite/sim/frv/fr550/mmachs.cgs | 259 - sim/testsuite/sim/frv/fr550/mmachu.cgs | 146 - sim/testsuite/sim/frv/fr550/mmrdhs.cgs | 263 - sim/testsuite/sim/frv/fr550/mmrdhu.cgs | 151 - sim/testsuite/sim/frv/fr550/mqaddhss.cgs | 76 - sim/testsuite/sim/frv/fr550/mqaddhus.cgs | 62 - sim/testsuite/sim/frv/fr550/mqmachs.cgs | 211 - sim/testsuite/sim/frv/fr550/mqmachu.cgs | 144 - sim/testsuite/sim/frv/fr550/mqmacxhs.cgs | 211 - sim/testsuite/sim/frv/fr550/mqsubhss.cgs | 76 - sim/testsuite/sim/frv/fr550/mqsubhus.cgs | 63 - sim/testsuite/sim/frv/fr550/mqxmachs.cgs | 211 - sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs | 211 - sim/testsuite/sim/frv/fr550/msubaccs.cgs | 128 - sim/testsuite/sim/frv/fr550/msubhss.cgs | 97 - sim/testsuite/sim/frv/fr550/msubhus.cgs | 77 - sim/testsuite/sim/frv/fr550/mtrap.cgs | 50 - sim/testsuite/sim/frv/fr550/udiv.cgs | 48 - sim/testsuite/sim/frv/fr550/udivi.cgs | 49 - sim/testsuite/sim/frv/fsqrtd.cgs | 22 - sim/testsuite/sim/frv/fsqrts.cgs | 19 - sim/testsuite/sim/frv/fstoi.cgs | 24 - sim/testsuite/sim/frv/fsubd.cgs | 83 - sim/testsuite/sim/frv/fsubs.cgs | 82 - sim/testsuite/sim/frv/fteq.cgs | 101 - sim/testsuite/sim/frv/ftge.cgs | 109 - sim/testsuite/sim/frv/ftgt.cgs | 101 - sim/testsuite/sim/frv/ftieq.cgs | 100 - sim/testsuite/sim/frv/ftige.cgs | 108 - sim/testsuite/sim/frv/ftigt.cgs | 100 - sim/testsuite/sim/frv/ftile.cgs | 108 - sim/testsuite/sim/frv/ftilg.cgs | 108 - sim/testsuite/sim/frv/ftilt.cgs | 100 - sim/testsuite/sim/frv/ftine.cgs | 112 - sim/testsuite/sim/frv/ftino.cgs | 53 - sim/testsuite/sim/frv/ftio.cgs | 112 - sim/testsuite/sim/frv/ftira.cgs | 114 - sim/testsuite/sim/frv/ftiu.cgs | 100 - sim/testsuite/sim/frv/ftiue.cgs | 108 - sim/testsuite/sim/frv/ftiug.cgs | 108 - sim/testsuite/sim/frv/ftiuge.cgs | 112 - sim/testsuite/sim/frv/ftiul.cgs | 108 - sim/testsuite/sim/frv/ftle.cgs | 109 - sim/testsuite/sim/frv/ftlg.cgs | 109 - sim/testsuite/sim/frv/ftlt.cgs | 101 - sim/testsuite/sim/frv/ftne.cgs | 113 - sim/testsuite/sim/frv/ftno.cgs | 54 - sim/testsuite/sim/frv/fto.cgs | 113 - sim/testsuite/sim/frv/ftra.cgs | 115 - sim/testsuite/sim/frv/ftu.cgs | 101 - sim/testsuite/sim/frv/ftue.cgs | 109 - sim/testsuite/sim/frv/ftug.cgs | 109 - sim/testsuite/sim/frv/ftuge.cgs | 113 - sim/testsuite/sim/frv/ftul.cgs | 109 - sim/testsuite/sim/frv/ftule.cgs | 113 - sim/testsuite/sim/frv/grloop.ms | 13 - sim/testsuite/sim/frv/hello.ms | 19 - sim/testsuite/sim/frv/icei.cgs | 15 - sim/testsuite/sim/frv/ici.cgs | 39 - sim/testsuite/sim/frv/icpl.cgs | 39 - sim/testsuite/sim/frv/icul.cgs | 53 - sim/testsuite/sim/frv/interrupts.exp | 19 - sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs | 35 - sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs | 35 - .../sim/frv/interrupts/badalign-fr550.cgs | 42 - sim/testsuite/sim/frv/interrupts/badalign.cgs | 73 - .../sim/frv/interrupts/compound-fr550.cgs | 54 - sim/testsuite/sim/frv/interrupts/compound.cgs | 66 - .../sim/frv/interrupts/data_store_error-fr550.cgs | 53 - .../sim/frv/interrupts/data_store_error.cgs | 53 - .../sim/frv/interrupts/fp_exception-fr550.cgs | 185 - sim/testsuite/sim/frv/interrupts/fp_exception.cgs | 209 - sim/testsuite/sim/frv/interrupts/illinsn.cgs | 38 - .../sim/frv/interrupts/insn_access_error-fr550.cgs | 44 - .../sim/frv/interrupts/insn_access_error.cgs | 56 - sim/testsuite/sim/frv/interrupts/mp_exception.cgs | 289 - .../sim/frv/interrupts/privileged_instruction.cgs | 54 - sim/testsuite/sim/frv/interrupts/regalign.cgs | 130 - sim/testsuite/sim/frv/interrupts/reset.cgs | 81 - sim/testsuite/sim/frv/interrupts/shadow_regs.cgs | 205 - sim/testsuite/sim/frv/interrupts/timer.cgs | 31 - sim/testsuite/sim/frv/jmpil.cgs | 17 - sim/testsuite/sim/frv/jmpl.cgs | 18 - sim/testsuite/sim/frv/jmpl.pcgs | 42 - sim/testsuite/sim/frv/ld.cgs | 29 - sim/testsuite/sim/frv/ldbf.cgs | 27 - sim/testsuite/sim/frv/ldbfi.cgs | 24 - sim/testsuite/sim/frv/ldbfu.cgs | 34 - sim/testsuite/sim/frv/ldc.cgs | 30 - sim/testsuite/sim/frv/ldcu.cgs | 34 - sim/testsuite/sim/frv/ldd.cgs | 43 - sim/testsuite/sim/frv/lddc.cgs | 45 - sim/testsuite/sim/frv/lddcu.cgs | 42 - sim/testsuite/sim/frv/lddf.cgs | 46 - sim/testsuite/sim/frv/lddfi.cgs | 34 - sim/testsuite/sim/frv/lddfu.cgs | 41 - sim/testsuite/sim/frv/lddi.cgs | 34 - sim/testsuite/sim/frv/lddu.cgs | 50 - sim/testsuite/sim/frv/ldf.cgs | 29 - sim/testsuite/sim/frv/ldfi.cgs | 26 - sim/testsuite/sim/frv/ldfu.cgs | 33 - sim/testsuite/sim/frv/ldhf.cgs | 27 - sim/testsuite/sim/frv/ldhfi.cgs | 24 - sim/testsuite/sim/frv/ldhfu.cgs | 33 - sim/testsuite/sim/frv/ldi.cgs | 26 - sim/testsuite/sim/frv/ldq.cgs | 64 - sim/testsuite/sim/frv/ldqc.cgs | 60 - sim/testsuite/sim/frv/ldqcu.cgs | 57 - sim/testsuite/sim/frv/ldqf.cgs | 61 - sim/testsuite/sim/frv/ldqfi.cgs | 51 - sim/testsuite/sim/frv/ldqfu.cgs | 58 - sim/testsuite/sim/frv/ldqi.cgs | 51 - sim/testsuite/sim/frv/ldqu.cgs | 71 - sim/testsuite/sim/frv/ldsb.cgs | 27 - sim/testsuite/sim/frv/ldsbi.cgs | 24 - sim/testsuite/sim/frv/ldsbu.cgs | 40 - sim/testsuite/sim/frv/ldsh.cgs | 27 - sim/testsuite/sim/frv/ldshi.cgs | 24 - sim/testsuite/sim/frv/ldshu.cgs | 39 - sim/testsuite/sim/frv/ldu.cgs | 39 - sim/testsuite/sim/frv/ldub.cgs | 27 - sim/testsuite/sim/frv/ldubi.cgs | 24 - sim/testsuite/sim/frv/ldubu.cgs | 39 - sim/testsuite/sim/frv/lduh.cgs | 27 - sim/testsuite/sim/frv/lduhi.cgs | 24 - sim/testsuite/sim/frv/lduhu.cgs | 39 - sim/testsuite/sim/frv/lrbranch.pcgs | 51 - sim/testsuite/sim/frv/mabshs.cgs | 67 - sim/testsuite/sim/frv/maddhss.cgs | 100 - sim/testsuite/sim/frv/maddhus.cgs | 89 - sim/testsuite/sim/frv/mand.cgs | 23 - sim/testsuite/sim/frv/maveh.cgs | 72 - sim/testsuite/sim/frv/mbtoh.cgs | 20 - sim/testsuite/sim/frv/mbtohe.cgs | 24 - sim/testsuite/sim/frv/mclracc.cgs | 79 - sim/testsuite/sim/frv/mcmpsh.cgs | 138 - sim/testsuite/sim/frv/mcmpuh.cgs | 138 - sim/testsuite/sim/frv/mcop1.cgs | 40 - sim/testsuite/sim/frv/mcop2.cgs | 40 - sim/testsuite/sim/frv/mcplhi.cgs | 53 - sim/testsuite/sim/frv/mcpli.cgs | 61 - sim/testsuite/sim/frv/mcpxis.cgs | 115 - sim/testsuite/sim/frv/mcpxiu.cgs | 76 - sim/testsuite/sim/frv/mcpxrs.cgs | 115 - sim/testsuite/sim/frv/mcpxru.cgs | 94 - sim/testsuite/sim/frv/mcut.cgs | 509 - sim/testsuite/sim/frv/mcuti.cgs | 381 - sim/testsuite/sim/frv/mcutss.cgs | 505 - sim/testsuite/sim/frv/mcutssi.cgs | 380 - sim/testsuite/sim/frv/mdaddaccs.cgs | 102 - sim/testsuite/sim/frv/mdasaccs.cgs | 122 - sim/testsuite/sim/frv/mdcutssi.cgs | 513 - sim/testsuite/sim/frv/mdpackh.cgs | 18 - sim/testsuite/sim/frv/mdrotli.cgs | 34 - sim/testsuite/sim/frv/mdsubaccs.cgs | 102 - sim/testsuite/sim/frv/mdunpackh.cgs | 26 - sim/testsuite/sim/frv/membar.cgs | 12 - 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sim/testsuite/v850/testutils.inc (limited to 'sim/testsuite') diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index fc5806e..4271705 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2021-01-15 Mike Frysinger + * Makefile.in (site.exp): Delete tool setting. + * sim/*/: Move subdirs up a directory. + +2021-01-15 Mike Frysinger + * configure, configure.ac: Delete. * Makefile.in (Makefile, config.status): Switch to ../config.status. diff --git a/sim/testsuite/Makefile.in b/sim/testsuite/Makefile.in index 1f75db6..1e4604c 100644 --- a/sim/testsuite/Makefile.in +++ b/sim/testsuite/Makefile.in @@ -127,7 +127,6 @@ site.exp: Makefile @echo '## these variables are automatically generated by make ##' > $@-t @echo '# Do not edit here. If you wish to override these values' >> $@-t @echo '# edit the last section' >> $@-t - @echo 'set tool sim' >> $@-t @echo 'set srcdir $(srcdir)' >> $@-t @echo 'set objdir' `pwd` >> $@-t @echo 'set arch $(arch)' >> $@-t diff --git a/sim/testsuite/aarch64/ChangeLog b/sim/testsuite/aarch64/ChangeLog new file mode 100644 index 0000000..f4671da --- /dev/null +++ b/sim/testsuite/aarch64/ChangeLog @@ -0,0 +1,83 @@ +2017-04-22 Jim Wilson + + * fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align + data. + * sumulh.s: Delete unnecessary data alignment. + * stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp + arguments to match change. + * ldn_multiple.s, stn_multiple.s: New. + +2017-04-08 Jim Wilson + + * fcvtl.s: New. + + * fcmXX.s: New. + +2017-03-25 Jim Wilson + + * adds.s: Add checks for values -2 and 1, where C is not set. + +2017-03-03 Jim Wilson + + * sumov.s: Correct compare test values. + * sumulh.s: New. + +2017-02-25 Jim Wilson + + * sumov.s: New. + + * cnt.s: New. + +2017-02-19 Jim Wilson + + * bit.s: Change cmp immediates to account for addv bug fix. + * cmtst.s, ldn_single.s, stn_single.s: Likewise. + * xtl.s: New. + +2017-02-14 Jim Wilson + + * mla.s: New. + + * bit.s: New. + + * ldn_single.s: New. + * ldnr.s: New. + * stn_single.s: New. + +2017-01-23 Jim Wilson + + * cmtst.s: New. + +2017-01-17 Jim Wilson + + * addv.s: New. + * xtn.s: New. + +2017-01-09 Jim Wilson + + * uzp.s: New. + +2017-01-04 Jim Wilson + + * fcsel.s: New. + * fcvtz.s: New. + * fminnm.s: New. + * mls.s: New. + * mul.s: New. + +2016-12-21 Jim Wilson + + * fcmp.s: New. + +2016-12-13 Jim Wilson + + * testutils.inc (pass): Move .Lpass to start. + (fail): Move .Lfail to start. Return 1 instead of 0. + (start): Moved .Lpass and .Lfail to here. + * adds.s: New. + * fstur.s: New. + * tbnz.s: New. + +2015-11-24 Nick Clifton + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/aarch64/adds.s b/sim/testsuite/aarch64/adds.s new file mode 100644 index 0000000..fdea5a7 --- /dev/null +++ b/sim/testsuite/aarch64/adds.s @@ -0,0 +1,98 @@ +# mach: aarch64 + +# Check the basic integer compare instructions: adds, adds64, subs, subs64. +# For add, check value pairs 1 and -1 (Z), -1 and -1 (N), 2 and -1 (C), +# and MIN_INT and -1 (V), +# Also check -2 and 1 (not C). +# For sub, negate the second value. + +.include "testutils.inc" + + start + mov w0, #1 + mov w1, #-1 + adds w2, w0, w1 + bne .Lfailure + mov w0, #-1 + mov w1, #-1 + adds w2, w0, w1 + bpl .Lfailure + mov w0, #2 + mov w1, #-1 + adds w2, w0, w1 + bcc .Lfailure + mov w0, #0x80000000 + mov w1, #-1 + adds w2, w0, w1 + bvc .Lfailure + mov w0, #-2 + mov w1, #1 + adds w2, w0, w1 + bcs .Lfailure + + mov x0, #1 + mov x1, #-1 + adds x2, x0, x1 + bne .Lfailure + mov x0, #-1 + mov x1, #-1 + adds x2, x0, x1 + bpl .Lfailure + mov x0, #2 + mov x1, #-1 + adds x2, x0, x1 + bcc .Lfailure + mov x0, #0x8000000000000000 + mov x1, #-1 + adds x2, x0, x1 + bvc .Lfailure + mov x0, #-2 + mov x1, #1 + adds x2, x0, x1 + bcs .Lfailure + + mov w0, #1 + mov w1, #1 + subs w2, w0, w1 + bne .Lfailure + mov w0, #-1 + mov w1, #1 + subs w2, w0, w1 + bpl .Lfailure + mov w0, #2 + mov w1, #1 + subs w2, w0, w1 + bcc .Lfailure + mov w0, #0x80000000 + mov w1, #1 + subs w2, w0, w1 + bvc .Lfailure + mov w0, #-2 + mov w1, #-1 + subs w2, w0, w1 + bcs .Lfailure + + mov x0, #1 + mov x1, #1 + subs x2, x0, x1 + bne .Lfailure + mov x0, #-1 + mov x1, #1 + subs x2, x0, x1 + bpl .Lfailure + mov x0, #2 + mov x1, #1 + subs x2, x0, x1 + bcc .Lfailure + mov x0, #0x8000000000000000 + mov x1, #1 + subs x2, x0, x1 + bvc .Lfailure + mov x0, #-2 + mov x1, #-1 + subs x2, x0, x1 + bcs .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/addv.s b/sim/testsuite/aarch64/addv.s new file mode 100644 index 0000000..4da8935 --- /dev/null +++ b/sim/testsuite/aarch64/addv.s @@ -0,0 +1,50 @@ +# mach: aarch64 + +# Check the add across vector instruction: addv. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + addv b1, v0.8b + mov x1, v1.d[0] + cmp x1, #36 + bne .Lfailure + + addv b1, v0.16b + mov x1, v1.d[0] + cmp x1, #136 + bne .Lfailure + + addv h1, v0.4h + mov x1, v1.d[0] + mov x2, #5136 + cmp x1, x2 + bne .Lfailure + + addv h1, v0.8h + mov x1, v1.d[0] + mov x2, #18496 + cmp x1, x2 + bne .Lfailure + + addv s1, v0.4s + mov x1, v1.d[0] + mov x2, 8220 + movk x2, 0x2824, lsl 16 + cmp x1, x2 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/allinsn.exp b/sim/testsuite/aarch64/allinsn.exp new file mode 100644 index 0000000..54d6478 --- /dev/null +++ b/sim/testsuite/aarch64/allinsn.exp @@ -0,0 +1,15 @@ +# AArch64 simulator testsuite + +if [istarget aarch64*-*] { + # all machines + set all_machs "aarch64" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/aarch64/bit.s b/sim/testsuite/aarch64/bit.s new file mode 100644 index 0000000..01a1d4e --- /dev/null +++ b/sim/testsuite/aarch64/bit.s @@ -0,0 +1,91 @@ +# mach: aarch64 + +# Check the bitwise vector instructions: bif, bit, bsl, eor. + +.include "testutils.inc" + + .data + .align 4 +inputa: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +inputb: + .word 0x40302010 + .word 0x80706050 + .word 0xc0b0a090 + .word 0x01f0e0d0 +mask: + .word 0xFF00FF00 + .word 0x00FF00FF + .word 0xF0F0F0F0 + .word 0x0F0F0F0F + + start + adrp x0, inputa + ldr q0, [x0, #:lo12:inputa] + adrp x0, inputb + ldr q1, [x0, #:lo12:inputb] + adrp x0, mask + ldr q2, [x0, #:lo12:mask] + + mov v3.8b, v0.8b + bif v3.8b, v1.8b, v2.8b + addv b4, v3.8b + mov x1, v4.d[0] + cmp x1, #50 + bne .Lfailure + + mov v3.16b, v0.16b + bif v3.16b, v1.16b, v2.16b + addv b4, v3.16b + mov x1, v4.d[0] + cmp x1, #252 + bne .Lfailure + + mov v3.8b, v0.8b + bit v3.8b, v1.8b, v2.8b + addv b4, v3.8b + mov x1, v4.d[0] + cmp x1, #50 + bne .Lfailure + + mov v3.16b, v0.16b + bit v3.16b, v1.16b, v2.16b + addv b4, v3.16b + mov x1, v4.d[0] + cmp x1, #13 + bne .Lfailure + + mov v3.8b, v2.8b + bsl v3.8b, v0.8b, v1.8b + addv b4, v3.8b + mov x1, v4.d[0] + cmp x1, #50 + bne .Lfailure + + mov v3.16b, v2.16b + bsl v3.16b, v0.16b, v1.16b + addv b4, v3.16b + mov x1, v4.d[0] + cmp x1, #252 + bne .Lfailure + + mov v3.8b, v0.8b + eor v3.8b, v1.8b, v2.8b + addv b4, v3.8b + mov x1, v4.d[0] + cmp x1, #252 + bne .Lfailure + + mov v3.16b, v0.16b + eor v3.16b, v1.16b, v2.16b + addv b4, v3.16b + mov x1, v4.d[0] + cmp x1, #247 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/cmtst.s b/sim/testsuite/aarch64/cmtst.s new file mode 100644 index 0000000..7e6a4c3 --- /dev/null +++ b/sim/testsuite/aarch64/cmtst.s @@ -0,0 +1,104 @@ +# mach: aarch64 + +# Check the vector compare bitwise test instruction: cmtst. + +.include "testutils.inc" + + .data + .align 4 +inputb: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +inputh: + .word 0x00020001 + .word 0x00040003 + .word 0x00060005 + .word 0x00800007 +inputs: + .word 0x00000001 + .word 0x00000002 + .word 0x00000003 + .word 0x00000004 +inputd: + .word 0x00000001 + .word 0x00000000 + .word 0x00000002 + .word 0x00000000 +inputd2: + .word 0x00000003 + .word 0x00000000 + .word 0x00000004 + .word 0x00000000 + + start + adrp x0, inputb + ldr q0, [x0, #:lo12:inputb] + rev64 v1.16b, v0.16b + + cmtst v2.8b, v0.8b, v1.8b + addv b3, v2.8b + mov x1, v3.d[0] + cmp x1, #0xfa + bne .Lfailure + + cmtst v2.16b, v0.16b, v1.16b + addv b3, v2.16b + mov x1, v3.d[0] + cmp x1, #0xf4 + bne .Lfailure + + adrp x0, inputh + ldr q0, [x0, #:lo12:inputh] + rev64 v1.8h, v0.8h + + cmtst v2.4h, v0.4h, v1.4h + addv h3, v2.4h + mov x1, v3.d[0] + mov x2, #0xfffe + cmp x1, x2 + bne .Lfailure + + cmtst v2.8h, v0.8h, v1.8h + addv h3, v2.8h + mov x1, v3.d[0] + mov x2, #0xfffc + cmp x1, x2 + bne .Lfailure + + adrp x0, inputs + ldr q0, [x0, #:lo12:inputs] + mov v1.d[0], v0.d[1] + mov v1.d[1], v0.d[0] + rev64 v1.4s, v1.4s + + cmtst v2.2s, v0.2s, v1.2s + mov x1, v2.d[0] + mov x2, #0xffffffff00000000 + cmp x1, x2 + bne .Lfailure + + cmtst v2.4s, v0.4s, v1.4s + addv s3, v2.4s + mov x1, v3.d[0] + mov x2, #0xfffffffe + cmp x1, x2 + bne .Lfailure + + adrp x0, inputd + ldr q0, [x0, #:lo12:inputd] + adrp x0, inputd2 + ldr q1, [x0, #:lo12:inputd2] + + cmtst v2.2d, v0.2d, v1.2d + mov x1, v2.d[0] + cmp x1, #-1 + bne .Lfailure + mov x2, v2.d[1] + cmp x2, #0 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/cnt.s b/sim/testsuite/aarch64/cnt.s new file mode 100644 index 0000000..b4be2e3 --- /dev/null +++ b/sim/testsuite/aarch64/cnt.s @@ -0,0 +1,33 @@ +# mach: aarch64 + +# Check the popcount instruction: cnt. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x0f070605 + .word 0x44332211 + .word 0xff776655 + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + cnt v1.8b, v0.8b + addv b2, v1.8b + mov x1, v2.d[0] + cmp x1, #16 + bne .Lfailure + + cnt v1.16b, v0.16b + addv b2, v1.16b + mov x1, v2.d[0] + cmp x1, #48 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/fcmXX.s b/sim/testsuite/aarch64/fcmXX.s new file mode 100644 index 0000000..cc1a2a9 --- /dev/null +++ b/sim/testsuite/aarch64/fcmXX.s @@ -0,0 +1,77 @@ +# mach: aarch64 + +# Check the FP scalar compare zero instructions: fcmeq, fcmle, fcmlt, fcmge, +# fcmgt. +# Check values -1, 0, and 1. + +.include "testutils.inc" + + start + fmov s0, wzr + fcmeq s1, s0, #0.0 + mov w0, v1.s[0] + cmp w0, #-1 + bne .Lfailure + fmov s0, #-1.0 + fcmeq s1, s0, #0.0 + mov w0, v1.s[0] + cmp w0, #0 + bne .Lfailure + fmov d0, xzr + fcmeq d1, d0, #0.0 + mov x0, v1.d[0] + cmp x0, #-1 + bne .Lfailure + fmov d0, #1.0 + fcmeq d1, d0, #0.0 + mov x0, v1.d[0] + cmp x0, #0 + bne .Lfailure + + fmov s0, #-1.0 + fcmle s1, s0, #0.0 + mov w0, v1.s[0] + cmp w0, #-1 + bne .Lfailure + fmov d0, #-1.0 + fcmle d1, d0, #0.0 + mov x0, v1.d[0] + cmp x0, #-1 + bne .Lfailure + + fmov s0, #-1.0 + fcmlt s1, s0, #0.0 + mov w0, v1.s[0] + cmp w0, #-1 + bne .Lfailure + fmov d0, #-1.0 + fcmlt d1, d0, #0.0 + mov x0, v1.d[0] + cmp x0, #-1 + bne .Lfailure + + fmov s0, #1.0 + fcmge s1, s0, #0.0 + mov w0, v1.s[0] + cmp w0, #-1 + bne .Lfailure + fmov d0, #1.0 + fcmge d1, d0, #0.0 + mov x0, v1.d[0] + cmp x0, #-1 + bne .Lfailure + + fmov s0, #1.0 + fcmgt s1, s0, #0.0 + mov w0, v1.s[0] + cmp w0, #-1 + bne .Lfailure + fmov d0, #1.0 + fcmgt d1, d0, #0.0 + mov x0, v1.d[0] + cmp x0, #-1 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/fcmp.s b/sim/testsuite/aarch64/fcmp.s new file mode 100644 index 0000000..fd826c4 --- /dev/null +++ b/sim/testsuite/aarch64/fcmp.s @@ -0,0 +1,146 @@ +# mach: aarch64 + +# Check the FP compare instructions: fcmps, fcmpzs, fcmpes, fcmpzes, fcmpd, +# fcmpzd, fcmped, fcmpzed. +# For 1 operand compares, check 0, 1, -1, +Inf, -Inf. +# For 2 operand compares, check 1/1, 1/-2, -1/2, +Inf/+Inf, +Inf/-Inf. +# FIXME: Check for qNaN and sNaN when exception raising support added. + +.include "testutils.inc" + + start + fmov s0, wzr + fcmp s0, #0.0 + bne .Lfailure + fcmpe s0, #0.0 + bne .Lfailure + fmov d0, xzr + fcmp d0, #0.0 + bne .Lfailure + fcmpe d0, #0.0 + bne .Lfailure + + fmov s0, #1.0 + fcmp s0, #0.0 + blo .Lfailure + fcmpe s0, #0.0 + blo .Lfailure + fmov d0, #1.0 + fcmp d0, #0.0 + blo .Lfailure + fcmpe d0, #0.0 + blo .Lfailure + + fmov s0, #-1.0 + fcmp s0, #0.0 + bpl .Lfailure + fcmpe s0, #0.0 + bpl .Lfailure + fmov d0, #-1.0 + fcmp d0, #0.0 + bpl .Lfailure + fcmpe d0, #0.0 + bpl .Lfailure + + fmov s0, #1.0 + fmov s1, wzr + fdiv s0, s0, s1 + fcmp s0, #0.0 + blo .Lfailure + fcmpe s0, #0.0 + blo .Lfailure + fmov d0, #1.0 + fmov d1, xzr + fdiv d0, d0, d1 + fcmp d0, #0.0 + blo .Lfailure + fcmpe d0, #0.0 + blo .Lfailure + + fmov s0, #-1.0 + fmov s1, wzr + fdiv s0, s0, s1 + fcmp s0, #0.0 + bpl .Lfailure + fcmpe s0, #0.0 + bpl .Lfailure + fmov d0, #-1.0 + fmov d1, xzr + fdiv d0, d0, d1 + fcmp d0, #0.0 + bpl .Lfailure + fcmpe d0, #0.0 + bpl .Lfailure + + fmov s0, #1.0 + fmov s1, #1.0 + fcmp s0, s1 + bne .Lfailure + fcmpe s0, s1 + bne .Lfailure + fmov d0, #1.0 + fmov d1, #1.0 + fcmp d0, d1 + bne .Lfailure + fcmpe d0, d1 + bne .Lfailure + + fmov s0, #1.0 + fmov s1, #-2.0 + fcmp s0, s1 + blo .Lfailure + fcmpe s0, s1 + blo .Lfailure + fmov d0, #1.0 + fmov d1, #-2.0 + fcmp d0, d1 + blo .Lfailure + fcmpe d0, d1 + blo .Lfailure + + fmov s0, #-1.0 + fmov s1, #2.0 + fcmp s0, s1 + bpl .Lfailure + fcmpe s0, s1 + bpl .Lfailure + fmov d0, #-1.0 + fmov d1, #2.0 + fcmp d0, d1 + bpl .Lfailure + fcmpe d0, d1 + bpl .Lfailure + + fmov s0, #1.0 + fmov s1, wzr + fdiv s0, s0, s1 + fcmp s0, s0 + bne .Lfailure + fcmpe s0, s0 + bne .Lfailure + fmov s1, #-1.0 + fmov s2, wzr + fdiv s1, s1, s2 + fcmp s0, s1 + blo .Lfailure + fcmpe s0, s1 + blo .Lfailure + + fmov d0, #1.0 + fmov d1, xzr + fdiv d0, d0, d1 + fcmp d0, d0 + bne .Lfailure + fcmpe d0, d0 + bne .Lfailure + fmov d1, #-1.0 + fmov d2, xzr + fdiv d1, d1, d2 + fcmp d0, d1 + blo .Lfailure + fcmpe d0, d1 + blo .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/fcsel.s b/sim/testsuite/aarch64/fcsel.s new file mode 100644 index 0000000..5b8443c --- /dev/null +++ b/sim/testsuite/aarch64/fcsel.s @@ -0,0 +1,53 @@ +# mach: aarch64 + +# Check the FP Conditional Select instruction: fcsel. +# Check 1/1 eq/neg, and 1/2 lt/gt. + +.include "testutils.inc" + + start + fmov s0, #1.0 + fmov s1, #1.0 + fmov s2, #-1.0 + fcmp s0, s1 + fcsel s3, s0, s2, eq + fcmp s3, s0 + bne .Lfailure + fcsel s3, s0, s2, ne + fcmp s3, s2 + bne .Lfailure + + fmov s0, #1.0 + fmov s1, #2.0 + fcmp s0, s1 + fcsel s3, s0, s2, lt + fcmp s3, s0 + bne .Lfailure + fcsel s3, s0, s2, gt + fcmp s3, s2 + bne .Lfailure + + fmov d0, #1.0 + fmov d1, #1.0 + fmov d2, #-1.0 + fcmp d0, d1 + fcsel d3, d0, d2, eq + fcmp d3, d0 + bne .Lfailure + fcsel d3, d0, d2, ne + fcmp d3, d2 + bne .Lfailure + + fmov d0, #1.0 + fmov d1, #2.0 + fcmp d0, d1 + fcsel d3, d0, d2, lt + fcmp d3, d0 + bne .Lfailure + fcsel d3, d0, d2, gt + fcmp d3, d2 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/fcvtl.s b/sim/testsuite/aarch64/fcvtl.s new file mode 100644 index 0000000..8febc08 --- /dev/null +++ b/sim/testsuite/aarch64/fcvtl.s @@ -0,0 +1,59 @@ +# mach: aarch64 + +# Check the FP convert to longer precision: fcvtl, fcvtl2. +# Test values 1.5, -1.5, INTMAX, and INT_MIN. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 1069547520 + .word 3217031168 + .word 1325400064 + .word 3472883712 +d1p5: + .word 0 + .word 1073217536 +dm1p5: + .word 0 + .word -1074266112 +dimax: + .word 0 + .word 1105199104 +dimin: + .word 0 + .word -1042284544 + + start + adrp x0, input + add x0, x0, #:lo12:input + ld1 {v0.4s}, [x0] + + fcvtl v1.2d, v0.2s + mov x1, v1.d[0] + adrp x2, d1p5 + ldr x3, [x2, #:lo12:d1p5] + cmp x1, x3 + bne .Lfailure + mov x1, v1.d[1] + adrp x2, dm1p5 + ldr x3, [x2, #:lo12:dm1p5] + cmp x1, x3 + bne .Lfailure + + fcvtl2 v2.2d, v0.4s + mov x1, v2.d[0] + adrp x2, dimax + ldr x3, [x2, #:lo12:dimax] + cmp x1, x3 + bne .Lfailure + mov x1, v2.d[1] + adrp x2, dimin + ldr x3, [x2, #:lo12:dimin] + cmp x1, x3 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/fcvtz.s b/sim/testsuite/aarch64/fcvtz.s new file mode 100644 index 0000000..311fc2e --- /dev/null +++ b/sim/testsuite/aarch64/fcvtz.s @@ -0,0 +1,203 @@ +# mach: aarch64 + +# Check the FP convert to int round toward zero instructions: fcvtszs32, +# fcvtszs, fcvtszd32, fcvtszd, fcvtzu. +# For 32-bit signed convert, test values -1.5, INT_MAX, and INT_MIN. +# For 64-bit signed convert, test values -1.5, LONG_MAX, and LONG_MIN. +# For 32-bit unsigned convert, test values 1.5, INT_MAX, and UINT_MAX. +# For 64-bit unsigned convert, test values 1.5, LONG_MAX, and ULONG_MAX. + + .data + .align 4 +fm1p5: + .word 3217031168 +fimax: + .word 1325400064 +fimin: + .word 3472883712 +flmax: + .word 1593835520 +flmin: + .word 3741319168 +f1p5: + .word 1069547520 +fuimax: + .word 1333788672 +fulmax: + .word 1602224128 + +dm1p5: + .word 0 + .word -1074266112 +dimax: + .word 4290772992 + .word 1105199103 +dimin: + .word 0 + .word -1042284544 +dlmax: + .word 0 + .word 1138753536 +dlmin: + .word 0 + .word -1008730112 +d1p5: + .word 0 + .word 1073217536 +duimax: + .word 4292870144 + .word 1106247679 +dulmax: + .word 0 + .word 1139802112 + +.include "testutils.inc" + + start + adrp x0, fm1p5 + ldr s0, [x0, #:lo12:fm1p5] + fcvtzs w1, s0 + cmp w1, #-1 + bne .Lfailure + adrp x0, fimax + ldr s0, [x0, #:lo12:fimax] + fcvtzs w1, s0 + mov w2, #0x7fffffff + cmp w1, w2 + bne .Lfailure + adrp x0, fimin + ldr s0, [x0, #:lo12:fimin] + fcvtzs w1, s0 + mov w2, #0x80000000 + cmp w1, w2 + bne .Lfailure + + adrp x0, fm1p5 + ldr s0, [x0, #:lo12:fm1p5] + fcvtzs x1, s0 + cmp x1, #-1 + bne .Lfailure + adrp x0, flmax + ldr s0, [x0, #:lo12:flmax] + fcvtzs x1, s0 + mov x2, #0x7fffffffffffffff + cmp x1, x2 + bne .Lfailure + adrp x0, flmin + ldr s0, [x0, #:lo12:flmin] + fcvtzs x1, s0 + mov x2, #0x8000000000000000 + cmp x1, x2 + bne .Lfailure + + adrp x0, dm1p5 + ldr d0, [x0, #:lo12:dm1p5] + fcvtzs w1, d0 + cmp w1, #-1 + bne .Lfailure + adrp x0, dimax + ldr d0, [x0, #:lo12:dimax] + fcvtzs w1, d0 + mov w2, #0x7fffffff + cmp w1, w2 + bne .Lfailure + adrp x0, dimin + ldr d0, [x0, #:lo12:dimin] + fcvtzs w1, d0 + mov w2, #0x80000000 + cmp w1, w2 + bne .Lfailure + + adrp x0, dm1p5 + ldr d0, [x0, #:lo12:dm1p5] + fcvtzs x1, d0 + cmp x1, #-1 + bne .Lfailure + adrp x0, dlmax + ldr d0, [x0, #:lo12:dlmax] + fcvtzs x1, d0 + mov x2, #0x7fffffffffffffff + cmp x1, x2 + bne .Lfailure + adrp x0, dlmin + ldr d0, [x0, #:lo12:dlmin] + fcvtzs x1, d0 + mov x2, #0x8000000000000000 + cmp x1, x2 + bne .Lfailure + + adrp x0, f1p5 + ldr s0, [x0, #:lo12:f1p5] + fcvtzu w1, s0 + cmp w1, #1 + bne .Lfailure + adrp x0, fimax + ldr s0, [x0, #:lo12:fimax] + fcvtzu w1, s0 + mov w2, #0x80000000 + cmp w1, w2 + bne .Lfailure + adrp x0, fuimax + ldr s0, [x0, #:lo12:fuimax] + fcvtzu w1, s0 + mov w2, #0xffffffff + cmp w1, w2 + bne .Lfailure + + adrp x0, f1p5 + ldr s0, [x0, #:lo12:f1p5] + fcvtzu x1, s0 + cmp x1, #1 + bne .Lfailure + adrp x0, flmax + ldr s0, [x0, #:lo12:flmax] + fcvtzu x1, s0 + mov x2, #0x8000000000000000 + cmp x1, x2 + bne .Lfailure + adrp x0, fulmax + ldr s0, [x0, #:lo12:fulmax] + fcvtzu x1, s0 + mov x2, #0xffffffffffffffff + cmp x1, x2 + bne .Lfailure + + adrp x0, d1p5 + ldr d0, [x0, #:lo12:d1p5] + fcvtzu w1, d0 + cmp w1, #1 + bne .Lfailure + adrp x0, dimax + ldr d0, [x0, #:lo12:dimax] + fcvtzu w1, d0 + mov w2, #0x7fffffff + cmp w1, w2 + bne .Lfailure + adrp x0, duimax + ldr d0, [x0, #:lo12:duimax] + fcvtzu w1, d0 + mov w2, #0xffffffff + cmp w1, w2 + bne .Lfailure + + adrp x0, d1p5 + ldr d0, [x0, #:lo12:d1p5] + fcvtzu x1, d0 + cmp x1, #1 + bne .Lfailure + adrp x0, dlmax + ldr d0, [x0, #:lo12:dlmax] + fcvtzu x1, d0 + mov x2, #0x8000000000000000 + cmp x1, x2 + bne .Lfailure + adrp x0, dulmax + ldr d0, [x0, #:lo12:dulmax] + fcvtzu x1, d0 + mov x2, #0xffffffffffffffff + cmp x1, x2 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/fminnm.s b/sim/testsuite/aarch64/fminnm.s new file mode 100644 index 0000000..43ccd7c --- /dev/null +++ b/sim/testsuite/aarch64/fminnm.s @@ -0,0 +1,82 @@ +# mach: aarch64 + +# Check the FP min/max number instructions: fminnm, fmaxnm, dminnm, dmaxnm. +# For min, check 2/1, 1/0, -1/-Inf. +# For max, check 1/2, -1/0, 1/+inf. + +.include "testutils.inc" + + start + fmov s0, #2.0 + fmov s1, #1.0 + fminnm s2, s0, s1 + fcmp s2, s1 + bne .Lfailure + fmov d0, #2.0 + fmov d1, #1.0 + fminnm d2, d0, d1 + fcmp d2, d1 + bne .Lfailure + + fmov s0, #1.0 + fmov s1, wzr + fminnm s2, s0, s1 + fcmp s2, s1 + bne .Lfailure + fmov d0, #1.0 + fmov d1, xzr + fminnm d2, d0, d1 + fcmp d2, d1 + bne .Lfailure + + fmov s0, #-1.0 + fmov s1, wzr + fdiv s1, s0, s1 + fminnm s2, s0, s1 + fcmp s2, s1 + bne .Lfailure + fmov d0, #-1.0 + fmov d1, xzr + fdiv d1, d0, d1 + fminnm d1, d0, d1 + fcmp d0, d0 + bne .Lfailure + + fmov s0, #1.0 + fmov s1, #2.0 + fmaxnm s2, s0, s1 + fcmp s2, s1 + bne .Lfailure + fmov d0, #1.0 + fmov d1, #2.0 + fmaxnm d2, d0, d1 + fcmp d2, d1 + bne .Lfailure + + fmov s0, #-1.0 + fmov s1, wzr + fmaxnm s2, s0, s1 + fcmp s2, s1 + bne .Lfailure + fmov d0, #-1.0 + fmov d1, xzr + fmaxnm d2, d0, d1 + fcmp d2, d1 + bne .Lfailure + + fmov s0, #1.0 + fmov s1, wzr + fdiv s1, s0, s1 + fmaxnm s2, s0, s1 + fcmp s2, s1 + bne .Lfailure + fmov d0, #1.0 + fmov d1, xzr + fdiv d1, d0, d1 + fmaxnm d1, d0, d1 + fcmp d0, d0 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/fstur.s b/sim/testsuite/aarch64/fstur.s new file mode 100644 index 0000000..80e5c67 --- /dev/null +++ b/sim/testsuite/aarch64/fstur.s @@ -0,0 +1,137 @@ +# mach: aarch64 + +# Check the FP store unscaled offset instructions: fsturs, fsturd, fsturq. +# Check the values -1, and XXX_MAX, which tests all bits. +# Check with offsets -256 and 255, which tests all bits. +# Also tests the FP load unscaled offset instructions: fldurs, fldurd, fldurq. + +.include "testutils.inc" + + .data + .align 4 +fm1: + .word 3212836864 +fmax: + .word 2139095039 +ftmp: + .word 0 + +dm1: + .word 0 + .word -1074790400 +dmax: + .word 4294967295 + .word 2146435071 +dtmp: + .word 0 + .word 0 + +ldm1: + .word 0 + .word 0 + .word 0 + .word -1073807360 +ldmax: + .word 4294967295 + .word 4294967295 + .word 4294967295 + .word 2147418111 +ldtmp: + .word 0 + .word 0 + .word 0 + .word 0 + + start + adrp x1, ftmp + add x1, x1, :lo12:ftmp + + adrp x0, fm1 + add x0, x0, :lo12:fm1 + sub x5, x0, #255 + sub x6, x1, #255 + movi d2, #0 + ldur s2, [x5, #255] + stur s2, [x6, #255] + ldr w3, [x0] + ldr w4, [x1] + cmp w3, w4 + bne .Lfailure + + adrp x0, fmax + add x0, x0, :lo12:fmax + add x5, x0, #256 + add x6, x1, #256 + movi d2, #0 + ldur s2, [x5, #-256] + stur s2, [x6, #-256] + ldr w3, [x0] + ldr w4, [x1] + cmp w3, w4 + bne .Lfailure + + adrp x1, dtmp + add x1, x1, :lo12:dtmp + + adrp x0, dm1 + add x0, x0, :lo12:dm1 + sub x5, x0, #255 + sub x6, x1, #255 + movi d2, #0 + ldur d2, [x5, #255] + stur d2, [x6, #255] + ldr x3, [x0] + ldr x4, [x1] + cmp x3, x4 + bne .Lfailure + + adrp x0, dmax + add x0, x0, :lo12:dmax + add x5, x0, #256 + add x6, x1, #256 + movi d2, #0 + ldur d2, [x5, #-256] + stur d2, [x6, #-256] + ldr x3, [x0] + ldr x4, [x1] + cmp x3, x4 + bne .Lfailure + + adrp x1, ldtmp + add x1, x1, :lo12:ldtmp + + adrp x0, ldm1 + add x0, x0, :lo12:ldm1 + sub x5, x0, #255 + sub x6, x1, #255 + movi v2.2d, #0 + ldur q2, [x5, #255] + stur q2, [x6, #255] + ldr x3, [x0] + ldr x4, [x1] + cmp x3, x4 + bne .Lfailure + ldr x3, [x0, 8] + ldr x4, [x1, 8] + cmp x3, x4 + bne .Lfailure + + adrp x0, ldmax + add x0, x0, :lo12:ldmax + add x5, x0, #256 + add x6, x1, #256 + movi v2.2d, #0 + ldur q2, [x5, #-256] + stur q2, [x6, #-256] + ldr x3, [x0] + ldr x4, [x1] + cmp x3, x4 + bne .Lfailure + ldr x3, [x0, 8] + ldr x4, [x1, 8] + cmp x3, x4 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/ldn_multiple.s b/sim/testsuite/aarch64/ldn_multiple.s new file mode 100644 index 0000000..285ef7e --- /dev/null +++ b/sim/testsuite/aarch64/ldn_multiple.s @@ -0,0 +1,136 @@ +# mach: aarch64 + +# Check the load multiple structure instructions: ld1, ld2, ld3, ld4. +# Check the addressing modes: no offset, post-index immediate offset, +# post-index register offset. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d + .word 0xfcfdfeff + .word 0xf8f9fafb + .word 0xf4f5f6f7 + .word 0xf0f1f2f3 + + start + adrp x0, input + add x0, x0, :lo12:input + + mov x2, x0 + mov x3, #16 + ld1 {v0.16b}, [x2], 16 + ld1 {v1.8h}, [x2], x3 + addv b4, v0.16b + addv b5, v1.16b + mov x4, v4.d[0] + cmp x4, #136 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #120 + bne .Lfailure + + mov x2, x0 + mov x3, #16 + ld2 {v0.8b, v1.8b}, [x2], x3 + ld2 {v2.4h, v3.4h}, [x2], 16 + addv b4, v0.8b + addv b5, v1.8b + addv b6, v2.8b + addv b7, v3.8b + mov x4, v4.d[0] + cmp x4, #64 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #72 + bne .Lfailure + mov x6, v6.d[0] + cmp x6, #196 + bne .Lfailure + mov x7, v7.d[0] + cmp x7, #180 + bne .Lfailure + + mov x2, x0 + ld3 {v0.2s, v1.2s, v2.2s}, [x2] + addv b4, v0.8b + addv b5, v1.8b + addv b6, v2.8b + mov x4, v4.d[0] + cmp x4, #68 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #16 + bne .Lfailure + mov x6, v6.d[0] + cmp x6, #16 + bne .Lfailure + + mov x2, x0 + ld4 {v0.4h, v1.4h, v2.4h, v3.4h}, [x2] + addv b4, v0.8b + addv b5, v1.8b + addv b6, v2.8b + addv b7, v3.8b + mov x4, v4.d[0] + cmp x4, #0 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #0 + bne .Lfailure + mov x6, v6.d[0] + cmp x6, #0 + bne .Lfailure + mov x7, v7.d[0] + cmp x7, #0 + bne .Lfailure + + mov x2, x0 + ld1 {v0.4s, v1.4s}, [x2] + addv b4, v0.16b + addv b5, v1.16b + mov x4, v4.d[0] + cmp x4, #136 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #120 + bne .Lfailure + + mov x2, x0 + ld1 {v0.1d, v1.1d, v2.1d}, [x2] + addv b4, v0.8b + addv b5, v1.8b + addv b6, v2.8b + mov x4, v4.d[0] + cmp x4, #36 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #100 + bne .Lfailure + mov x6, v6.d[0] + cmp x6, #220 + bne .Lfailure + + mov x2, x0 + ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x2] + addv b4, v0.8b + addv b5, v1.8b + addv b6, v2.8b + mov x4, v4.d[0] + cmp x4, #36 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #100 + bne .Lfailure + mov x6, v6.d[0] + cmp x6, #220 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/ldn_single.s b/sim/testsuite/aarch64/ldn_single.s new file mode 100644 index 0000000..9681520 --- /dev/null +++ b/sim/testsuite/aarch64/ldn_single.s @@ -0,0 +1,102 @@ +# mach: aarch64 + +# Check the load single 1-element structure to one lane instructions: +# ld1, ld2, ld3, ld4. +# Check the addressing modes: no offset, post-index immediate offset, +# post-index register offset. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d + .word 0x14131211 + .word 0x18171615 + .word 0x1c1b1a19 + .word 0x201f1e1d + + start + adrp x0, input + add x0, x0, :lo12:input + + mov x2, x0 + mov x3, #1 + mov x4, #4 + ld1 {v0.b}[0], [x2], 1 + ld1 {v0.b}[1], [x2], x3 + ld1 {v0.h}[1], [x2], 2 + ld1 {v0.s}[1], [x2], x4 + ld1 {v0.d}[1], [x2] + addv b1, v0.16b + mov x5, v1.d[0] + cmp x5, #136 + bne .Lfailure + + mov x2, x0 + mov x3, #16 + mov x4, #4 + ld2 {v0.d, v1.d}[0], [x2], x3 + ld2 {v0.s, v1.s}[2], [x2], 8 + ld2 {v0.h, v1.h}[6], [x2], x4 + ld2 {v0.b, v1.b}[14], [x2], 2 + ld2 {v0.b, v1.b}[15], [x2] + addv b2, v0.16b + addv b3, v1.16b + mov x5, v2.d[0] + mov x6, v3.d[0] + cmp x5, #221 + bne .Lfailure + cmp x6, #51 + bne .Lfailure + + mov x2, x0 + ld3 {v0.s, v1.s, v2.s}[0], [x2], 12 + ld3 {v0.s, v1.s, v2.s}[1], [x2] + mov x2, x0 + mov x3, #12 + ld3 {v0.s, v1.s, v2.s}[2], [x2], x3 + ld3 {v0.s, v1.s, v2.s}[3], [x2] + addv b3, v0.16b + addv b4, v1.16b + addv b5, v2.16b + mov x4, v3.d[0] + mov x5, v4.d[0] + mov x6, v5.d[0] + cmp x4, #136 + bne .Lfailure + cmp x5, #200 + bne .Lfailure + cmp x6, #8 + bne .Lfailure + + mov x2, x0 + ld4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16 + ld4 {v0.s, v1.s, v2.s, v3.s}[1], [x2] + mov x2, x0 + mov x3, #16 + ld4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], x3 + ld4 {v0.s, v1.s, v2.s, v3.s}[3], [x2] + addv b4, v0.16b + addv b5, v1.16b + addv b6, v2.16b + addv b7, v3.16b + mov x4, v4.d[0] + mov x5, v5.d[0] + mov x6, v6.d[0] + mov x7, v7.d[0] + cmp x4, #168 + bne .Lfailure + cmp x5, #232 + bne .Lfailure + cmp x6, #40 + bne .Lfailure + cmp x7, #104 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/ldnr.s b/sim/testsuite/aarch64/ldnr.s new file mode 100644 index 0000000..7126c46 --- /dev/null +++ b/sim/testsuite/aarch64/ldnr.s @@ -0,0 +1,178 @@ +# mach: aarch64 + +# Check the load single 1-element structure and replicate to all lanes insns: +# ld1r, ld2r, ld3r, ld4r. +# Check the addressing modes: no offset, post-index immediate offset, +# post-index register offset. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +input2: + .word 0x00000001 + .word 0x00000002 + .word 0x00000003 + .word 0x00000004 + .word 0x00000005 + .word 0x00000006 + .word 0x00000007 + .word 0x00000008 + .word 0x00000009 + .word 0x0000000a + .word 0x0000000b + .word 0x0000000c + + start + adrp x0, input + add x0, x0, :lo12:input + adrp x1, input2 + add x1, x1, :lo12:input2 + + mov x2, x0 + mov x3, #1 + ld1r {v0.8b}, [x2], 1 + ld1r {v1.16b}, [x2], x3 + ld1r {v2.4h}, [x2], 2 + ld1r {v3.8h}, [x2] + addv b0, v0.8b + addv b1, v1.16b + addv b2, v2.8b + addv b3, v3.16b + mov x2, v0.d[0] + mov x3, v1.d[0] + mov x4, v2.d[0] + mov x5, v3.d[0] + cmp x2, #8 + bne .Lfailure + cmp x3, #32 + bne .Lfailure + cmp x4, #28 + bne .Lfailure + cmp x5, #88 + bne .Lfailure + + mov x2, x1 + mov x3, #8 + ld2r {v0.2s, v1.2s}, [x2], 8 + ld2r {v2.4s, v3.4s}, [x2], x3 + ld2r {v4.1d, v5.1d}, [x2], 16 + ld2r {v6.2d, v7.2d}, [x2] + addp v0.2s, v0.2s, v1.2s + addv s2, v2.4s + addv s3, v3.4s + addp v4.2s, v4.2s, v5.2s + addv s6, v6.4s + addv s7, v7.4s + mov w2, v0.s[0] + mov w3, v0.s[1] + mov x4, v2.d[0] + mov x5, v3.d[0] + mov w6, v4.s[0] + mov w7, v4.s[1] + mov x8, v6.d[0] + mov x9, v7.d[0] + cmp w2, #2 + bne .Lfailure + cmp w3, #4 + bne .Lfailure + cmp x4, #12 + bne .Lfailure + cmp x5, #16 + bne .Lfailure + cmp w6, #11 + bne .Lfailure + cmp w7, #15 + bne .Lfailure + cmp x8, #38 + bne .Lfailure + cmp x9, #46 + bne .Lfailure + + mov x2, x0 + mov x3, #3 + ld3r {v0.8b, v1.8b, v2.8b}, [x2], 3 + ld3r {v3.8b, v4.8b, v5.8b}, [x2], x3 + ld3r {v6.8b, v7.8b, v8.8b}, [x2] + addv b0, v0.8b + addv b1, v1.8b + addv b2, v2.8b + addv b3, v3.8b + addv b4, v4.8b + addv b5, v5.8b + addv b6, v6.8b + addv b7, v7.8b + addv b8, v8.8b + addv b9, v9.8b + mov x2, v0.d[0] + mov x3, v1.d[0] + mov x4, v2.d[0] + mov x5, v3.d[0] + mov x6, v4.d[0] + mov x7, v5.d[0] + mov x8, v6.d[0] + mov x9, v7.d[0] + mov x10, v8.d[0] + cmp x2, #8 + bne .Lfailure + cmp x3, #16 + bne .Lfailure + cmp x4, #24 + bne .Lfailure + cmp x5, #32 + bne .Lfailure + cmp x6, #40 + bne .Lfailure + cmp x7, #48 + bne .Lfailure + cmp x8, #56 + bne .Lfailure + cmp x9, #64 + bne .Lfailure + cmp x10, #72 + bne .Lfailure + + mov x2, x1 + ld4r {v0.4s, v1.4s, v2.4s, v3.4s}, [x2], 16 + ld4r {v4.4s, v5.4s, v6.4s, v7.4s}, [x2] + addv s0, v0.4s + addv s1, v1.4s + addv s2, v2.4s + addv s3, v3.4s + addv s4, v4.4s + addv s5, v5.4s + addv s6, v6.4s + addv s7, v7.4s + mov x2, v0.d[0] + mov x3, v1.d[0] + mov x4, v2.d[0] + mov x5, v3.d[0] + mov x6, v4.d[0] + mov x7, v5.d[0] + mov x8, v6.d[0] + mov x9, v7.d[0] + cmp x2, #4 + bne .Lfailure + cmp x3, #8 + bne .Lfailure + cmp x4, #12 + bne .Lfailure + cmp x5, #16 + bne .Lfailure + cmp x6, #20 + bne .Lfailure + cmp x7, #24 + bne .Lfailure + cmp x8, #28 + bne .Lfailure + cmp x9, #32 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/mla.s b/sim/testsuite/aarch64/mla.s new file mode 100644 index 0000000..e3ea836 --- /dev/null +++ b/sim/testsuite/aarch64/mla.s @@ -0,0 +1,105 @@ +# mach: aarch64 + +# Check the vector multiply add instruction: mla. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +m8b: + .word 0x110a0502 + .word 0x4132251a +m16b: + .word 0x110a0502 + .word 0x4132251a + .word 0x917a6552 + .word 0x01e2c5aa +m4h: + .word 0x180a0402 + .word 0x70323c1a +m8h: + .word 0x180a0402 + .word 0x70323c1a + .word 0x087ab452 + .word 0xe0e26caa +m2s: + .word 0x140a0402 + .word 0xa46a3c1a +m4s: + .word 0x140a0402 + .word 0xa46a3c1a + .word 0xb52ab452 + .word 0x464b6caa + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + movi v1.8b, #1 + mla v1.8b, v0.8b, v0.8b + mov x1, v1.d[0] + adrp x3, m8b + ldr x4, [x3, #:lo12:m8b] + cmp x1, x4 + bne .Lfailure + + movi v1.16b, #1 + mla v1.16b, v0.16b, v0.16b + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m16b + ldr x4, [x3, #:lo12:m16b] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:m16b+8] + cmp x2, x5 + bne .Lfailure + + movi v1.4h, #1 + mla v1.4h, v0.4h, v0.4h + mov x1, v1.d[0] + adrp x3, m4h + ldr x4, [x3, #:lo12:m4h] + cmp x1, x4 + bne .Lfailure + + movi v1.8h, #1 + mla v1.8h, v0.8h, v0.8h + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m8h + ldr x4, [x3, #:lo12:m8h] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:m8h+8] + cmp x2, x5 + bne .Lfailure + + movi v1.2s, #1 + mla v1.2s, v0.2s, v0.2s + mov x1, v1.d[0] + adrp x3, m2s + ldr x4, [x3, #:lo12:m2s] + cmp x1, x4 + bne .Lfailure + + movi v1.4s, #1 + mla v1.4s, v0.4s, v0.4s + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m4s + ldr x4, [x3, #:lo12:m4s] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:m4s+8] + cmp x2, x5 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/mls.s b/sim/testsuite/aarch64/mls.s new file mode 100644 index 0000000..5c9e225 --- /dev/null +++ b/sim/testsuite/aarch64/mls.s @@ -0,0 +1,105 @@ +# mach: aarch64 + +# Check the vector multiply subtract instruction: mls. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +m8b: + .word 0xf1f8fd00 + .word 0xc1d0dde8 +m16b: + .word 0xf1f8fd00 + .word 0xc1d0dde8 + .word 0x71889db0 + .word 0x01203d58 +m4h: + .word 0xe7f8fc00 + .word 0x8fd0c3e8 +m8h: + .word 0xe7f8fc00 + .word 0x8fd0c3e8 + .word 0xf7884bb0 + .word 0x1f209358 +m2s: + .word 0xebf5fc00 + .word 0x5b95c3e8 +m4s: + .word 0xebf5fc00 + .word 0x5b95c3e8 + .word 0x4ad54bb0 + .word 0xb9b49358 + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + movi v1.8b, #1 + mls v1.8b, v0.8b, v0.8b + mov x1, v1.d[0] + adrp x3, m8b + ldr x4, [x3, #:lo12:m8b] + cmp x1, x4 + bne .Lfailure + + movi v1.16b, #1 + mls v1.16b, v0.16b, v0.16b + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m16b + ldr x4, [x3, #:lo12:m16b] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:m16b+8] + cmp x2, x5 + bne .Lfailure + + movi v1.4h, #1 + mls v1.4h, v0.4h, v0.4h + mov x1, v1.d[0] + adrp x3, m4h + ldr x4, [x3, #:lo12:m4h] + cmp x1, x4 + bne .Lfailure + + movi v1.8h, #1 + mls v1.8h, v0.8h, v0.8h + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m8h + ldr x4, [x3, #:lo12:m8h] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:m8h+8] + cmp x2, x5 + bne .Lfailure + + movi v1.2s, #1 + mls v1.2s, v0.2s, v0.2s + mov x1, v1.d[0] + adrp x3, m2s + ldr x4, [x3, #:lo12:m2s] + cmp x1, x4 + bne .Lfailure + + movi v1.4s, #1 + mls v1.4s, v0.4s, v0.4s + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m4s + ldr x4, [x3, #:lo12:m4s] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:m4s+8] + cmp x2, x5 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/mul.s b/sim/testsuite/aarch64/mul.s new file mode 100644 index 0000000..783dba7 --- /dev/null +++ b/sim/testsuite/aarch64/mul.s @@ -0,0 +1,99 @@ +# mach: aarch64 + +# Check the non-widening multiply vector instruction: mul. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +m8b: + .word 0x10090401 + .word 0x40312419 +m16b: + .word 0x10090401 + .word 0x40312419 + .word 0x90796451 + .word 0x00e1c4a9 +m4h: + .word 0x18090401 + .word 0x70313c19 +m8h: + .word 0x18090401 + .word 0x70313c19 + .word 0x0879b451 + .word 0xe0e16ca9 +m2s: + .word 0x140a0401 + .word 0xa46a3c19 +m4s: + .word 0x140a0401 + .word 0xa46a3c19 + .word 0xb52ab451 + .word 0x464b6ca9 + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + mul v1.8b, v0.8b, v0.8b + mov x1, v1.d[0] + adrp x3, m8b + ldr x4, [x0, #:lo12:m8b] + cmp x1, x4 + bne .Lfailure + + mul v1.16b, v0.16b, v0.16b + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m16b + ldr x4, [x0, #:lo12:m16b] + cmp x1, x4 + bne .Lfailure + ldr x5, [x0, #:lo12:m16b+8] + cmp x2, x5 + bne .Lfailure + + mul v1.4h, v0.4h, v0.4h + mov x1, v1.d[0] + adrp x3, m4h + ldr x4, [x0, #:lo12:m4h] + cmp x1, x4 + bne .Lfailure + + mul v1.8h, v0.8h, v0.8h + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m8h + ldr x4, [x0, #:lo12:m8h] + cmp x1, x4 + bne .Lfailure + ldr x5, [x0, #:lo12:m8h+8] + cmp x2, x5 + bne .Lfailure + + mul v1.2s, v0.2s, v0.2s + mov x1, v1.d[0] + adrp x3, m2s + ldr x4, [x0, #:lo12:m2s] + cmp x1, x4 + bne .Lfailure + + mul v1.4s, v0.4s, v0.4s + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m4s + ldr x4, [x0, #:lo12:m4s] + cmp x1, x4 + bne .Lfailure + ldr x5, [x0, #:lo12:m4s+8] + cmp x2, x5 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/pass.s b/sim/testsuite/aarch64/pass.s new file mode 100644 index 0000000..7ce7de5 --- /dev/null +++ b/sim/testsuite/aarch64/pass.s @@ -0,0 +1,7 @@ +# check that the sim doesn't die immediately. +# mach: aarch64 + +.include "testutils.inc" + + start + pass diff --git a/sim/testsuite/aarch64/stn_multiple.s b/sim/testsuite/aarch64/stn_multiple.s new file mode 100644 index 0000000..1a3f24d --- /dev/null +++ b/sim/testsuite/aarch64/stn_multiple.s @@ -0,0 +1,171 @@ +# mach: aarch64 + +# Check the store multiple structure instructions: st1, st2, st3, st4. +# Check the addressing modes: no offset, post-index immediate offset, +# post-index register offset. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d + .word 0xfcfdfeff + .word 0xf8f9fafb + .word 0xf4f5f6f7 + .word 0xf0f1f2f3 +output: + .zero 64 + + start + adrp x0, input + add x0, x0, :lo12:input + adrp x1, output + add x1, x1, :lo12:output + + mov x2, x0 + ldr q0, [x2], 16 + ldr q1, [x2] + mov x2, x0 + ldr q2, [x2], 16 + ldr q3, [x2] + + mov x2, x1 + mov x3, #16 + st1 {v0.16b}, [x2], 16 + st1 {v1.8h}, [x2], x3 + mov x2, x1 + ldr q4, [x2], 16 + ldr q5, [x2] + addv b4, v4.16b + addv b5, v5.16b + mov x4, v4.d[0] + cmp x4, #136 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #120 + bne .Lfailure + + mov x2, x1 + mov x3, #16 + st2 {v0.8b, v1.8b}, [x2], 16 + st2 {v2.4h, v3.4h}, [x2], x3 + mov x2, x1 + ldr q4, [x2], 16 + ldr q5, [x2] + addv b4, v4.16b + addv b5, v5.16b + mov x4, v4.d[0] + cmp x4, #0 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #0 + bne .Lfailure + + mov x2, x1 + st3 {v0.4s, v1.4s, v2.4s}, [x2] + ldr q4, [x2], 16 + ldr q5, [x2], 16 + ldr q6, [x2] + addv b4, v4.16b + addv b5, v5.16b + addv b6, v6.16b + mov x4, v4.d[0] + cmp x4, #36 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #0 + bne .Lfailure + mov x6, v6.d[0] + cmp x6, #100 + bne .Lfailure + + mov x2, x1 + st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x2] + ldr q4, [x2], 16 + ldr q5, [x2], 16 + ldr q6, [x2], 16 + ldr q7, [x2] + addv b4, v4.16b + addv b5, v5.16b + addv b6, v6.16b + addv b7, v7.16b + mov x4, v4.d[0] + cmp x4, #0 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #0 + bne .Lfailure + mov x6, v6.d[0] + cmp x6, #0 + bne .Lfailure + mov x7, v7.d[0] + cmp x7, #0 + bne .Lfailure + + pass + + mov x2, x1 + st1 {v0.2s, v1.2s}, [x2], 16 + st1 {v2.1d, v3.1d}, [x2] + mov x2, x1 + ldr q4, [x2], 16 + ldr q5, [x2] + addv b4, v4.16b + addv b5, v5.16b + mov x4, v4.d[0] + cmp x4, #0 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #0 + bne .Lfailure + + mov x2, x1 + st1 {v0.2d, v1.2d, v2.2d}, [x2] + mov x2, x1 + ldr q4, [x2], 16 + ldr q5, [x2], 16 + ldr q6, [x2] + addv b4, v4.16b + addv b5, v5.16b + addv b6, v6.16b + mov x4, v4.d[0] + cmp x4, #136 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #120 + bne .Lfailure + mov x6, v6.d[0] + cmp x6, #136 + bne .Lfailure + + mov x2, x1 + st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x2] + mov x2, x1 + ldr q4, [x2], 16 + ldr q5, [x2], 16 + ldr q6, [x2], 16 + ldr q7, [x2] + addv b4, v4.16b + addv b5, v5.16b + addv b6, v6.16b + addv b7, v7.16b + mov x4, v4.d[0] + cmp x4, #136 + bne .Lfailure + mov x5, v5.d[0] + cmp x5, #120 + bne .Lfailure + mov x6, v6.d[0] + cmp x6, #136 + bne .Lfailure + mov x7, v7.d[0] + cmp x7, #120 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/stn_single.s b/sim/testsuite/aarch64/stn_single.s new file mode 100644 index 0000000..a24b084 --- /dev/null +++ b/sim/testsuite/aarch64/stn_single.s @@ -0,0 +1,124 @@ +# mach: aarch64 + +# Check the store single 1-element structure to one lane instructions: +# st1, st2, st3, st4. +# Check the addressing modes: no offset, post-index immediate offset, +# post-index register offset. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d + .word 0x14131211 + .word 0x18171615 + .word 0x1c1b1a19 + .word 0x201f1e1d +output: + .zero 64 + + start + adrp x0, input + add x0, x0, :lo12:input + adrp x1, output + add x1, x1, :lo12:output + + mov x2, x0 + ldr q0, [x2], 16 + ldr q1, [x2] + mov x2, x0 + ldr q2, [x2], 16 + ldr q3, [x2] + + mov x2, x1 + mov x3, #1 + mov x4, #4 + st1 {v0.b}[0], [x2], 1 + st1 {v0.b}[1], [x2], x3 + st1 {v0.h}[1], [x2], 2 + st1 {v0.s}[1], [x2], x4 + st1 {v0.d}[1], [x2] + ldr q4, [x1] + addv b4, v4.16b + mov x5, v4.d[0] + cmp x5, #136 + bne .Lfailure + + mov x2, x1 + mov x3, #16 + mov x4, #4 + st2 {v0.d, v1.d}[0], [x2], x3 + st2 {v0.s, v1.s}[2], [x2], 8 + st2 {v0.h, v1.h}[6], [x2], x4 + st2 {v0.b, v1.b}[14], [x2], 2 + st2 {v0.b, v1.b}[15], [x2] + mov x2, x1 + ldr q4, [x2], 16 + ldr q5, [x2] + addv b4, v4.16b + addv b5, v5.16b + mov x5, v4.d[0] + mov x6, v5.d[0] + cmp x5, #200 + bne .Lfailure + cmp x6, #72 + bne .Lfailure + + mov x2, x1 + mov x3, #12 + st3 {v0.s, v1.s, v2.s}[0], [x2], 12 + st3 {v0.s, v1.s, v2.s}[1], [x2], x3 + st3 {v0.s, v1.s, v2.s}[2], [x2], 12 + st3 {v0.s, v1.s, v2.s}[3], [x2] + mov x2, x1 + ldr q4, [x2], 16 + ldr q5, [x2], 16 + ldr q6, [x2] + addv b4, v4.16b + addv b5, v5.16b + addv b6, v6.16b + mov x4, v4.d[0] + mov x5, v5.d[0] + mov x6, v6.d[0] + cmp x4, #120 + bne .Lfailure + cmp x5, #8 + bne .Lfailure + cmp x6, #24 + bne .Lfailure + + mov x2, x1 + mov x3, #16 + st4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16 + st4 {v0.s, v1.s, v2.s, v3.s}[1], [x2], x3 + st4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], 16 + st4 {v0.s, v1.s, v2.s, v3.s}[3], [x2] + mov x2, x1 + ldr q4, [x2], 16 + ldr q5, [x2], 16 + ldr q6, [x2], 16 + ldr q7, [x2] + addv b4, v4.16b + addv b5, v5.16b + addv b6, v6.16b + addv b7, v7.16b + mov x4, v4.d[0] + mov x5, v5.d[0] + mov x6, v6.d[0] + mov x7, v7.d[0] + cmp x4, #168 + bne .Lfailure + cmp x5, #232 + bne .Lfailure + cmp x6, #40 + bne .Lfailure + cmp x7, #104 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/sumov.s b/sim/testsuite/aarch64/sumov.s new file mode 100644 index 0000000..7180c6a --- /dev/null +++ b/sim/testsuite/aarch64/sumov.s @@ -0,0 +1,93 @@ +# mach: aarch64 + +# Check the mov from asimd to general reg instructions: smov, umov. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0xf4f3f2f1 + .word 0xf8f7f6f5 + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + smov w0, v0.b[0] + smov w3, v0.b[12] + cmp w0, #1 + bne .Lfailure + cmp w3, #-11 + bne .Lfailure + + smov x0, v0.b[1] + smov x3, v0.b[13] + cmp x0, #2 + bne .Lfailure + cmp x3, #-10 + bne .Lfailure + + smov w0, v0.h[0] + smov w1, v0.h[4] + cmp w0, #0x0201 + bne .Lfailure + cmp w1, #-3343 + bne .Lfailure + + smov x0, v0.h[1] + smov x1, v0.h[5] + cmp x0, #0x0403 + bne .Lfailure + cmp x1, #-2829 + bne .Lfailure + + smov x0, v0.s[1] + smov x1, v0.s[3] + mov x2, #0x0605 + movk x2, #0x0807, lsl #16 + cmp x0, x2 + bne .Lfailure + mov w3, #0xf6f5 + movk w3, #0xf8f7, lsl #16 + sxtw x3, w3 + cmp x1, x3 + bne .Lfailure + + umov w0, v0.b[0] + umov w3, v0.b[12] + cmp w0, #1 + bne .Lfailure + cmp w3, #0xf5 + bne .Lfailure + + umov w0, v0.h[0] + umov w1, v0.h[4] + cmp w0, #0x0201 + bne .Lfailure + mov w2, #0xf2f1 + cmp w1, w2 + bne .Lfailure + + umov w0, v0.s[0] + umov w1, v0.s[2] + mov w2, #0x0201 + movk w2, #0x0403, lsl #16 + cmp w0, w2 + bne .Lfailure + mov w3, #0xf2f1 + movk w3, #0xf4f3, lsl #16 + cmp w1, w3 + bne .Lfailure + + umov x0, v0.d[0] + adrp x1, input + ldr x2, [x1, #:lo12:input] + cmp x0, x2 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/sumulh.s b/sim/testsuite/aarch64/sumulh.s new file mode 100644 index 0000000..d75e0c6 --- /dev/null +++ b/sim/testsuite/aarch64/sumulh.s @@ -0,0 +1,53 @@ +# mach: aarch64 + +# Check the multiply highpart instructions: smulh, umulh. + +# Test -2*2, -1<<32*-1<<32, -2*-2, and 2*2. + +.include "testutils.inc" + + start + + mov x0, #-2 + mov x1, #2 + smulh x2, x0, x1 + cmp x2, #-1 + bne .Lfailure + umulh x3, x0, x1 + cmp x3, #1 + bne .Lfailure + + mov w0, #-1 + lsl x0, x0, #32 // 0xffffffff00000000 + mov x1, x0 + smulh x2, x0, x1 + cmp x2, #1 + bne .Lfailure + umulh x3, x0, x1 + mov w4, #-2 + lsl x4, x4, #32 + add x4, x4, #1 // 0xfffffffe00000001 + cmp x3, x4 + bne .Lfailure + + mov x0, #-2 + mov x1, #-2 + smulh x2, x0, x1 + cmp x2, #0 + bne .Lfailure + umulh x3, x0, x1 + cmp x3, #-4 + bne .Lfailure + + mov x0, #2 + mov x1, #2 + smulh x2, x0, x1 + cmp x2, #0 + bne .Lfailure + umulh x3, x0, x1 + cmp x3, #0 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/tbnz.s b/sim/testsuite/aarch64/tbnz.s new file mode 100644 index 0000000..2416101 --- /dev/null +++ b/sim/testsuite/aarch64/tbnz.s @@ -0,0 +1,55 @@ +# mach: aarch64 + +# Check the test-bit-and-branch instructions: tbnz, and tbz. +# We check the edge condition bit positions: 0, 1<<31, 1<<32, 1<<63. + +.include "testutils.inc" + + start + mov x0, #1 + tbnz x0, #0, .L1 + fail +.L1: + tbz x0, #0, .Lfailure + mov x0, #0xFFFFFFFFFFFFFFFE + tbnz x0, #0, .Lfailure + tbz x0, #0, .L2 + fail +.L2: + + mov x0, #0x80000000 + tbnz x0, #31, .L3 + fail +.L3: + tbz x0, #31, .Lfailure + mov x0, #0xFFFFFFFF7FFFFFFF + tbnz x0, #31, .Lfailure + tbz x0, #31, .L4 + fail +.L4: + + mov x0, #0x100000000 + tbnz x0, #32, .L5 + fail +.L5: + tbz x0, #32, .Lfailure + mov x0, #0xFFFFFFFEFFFFFFFF + tbnz x0, #32, .Lfailure + tbz x0, #32, .L6 + fail +.L6: + + mov x0, #0x8000000000000000 + tbnz x0, #63, .L7 + fail +.L7: + tbz x0, #63, .Lfailure + mov x0, #0x7FFFFFFFFFFFFFFF + tbnz x0, #63, .Lfailure + tbz x0, #63, .L8 + fail +.L8: + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/testutils.inc b/sim/testsuite/aarch64/testutils.inc new file mode 100644 index 0000000..1fc9bc8 --- /dev/null +++ b/sim/testsuite/aarch64/testutils.inc @@ -0,0 +1,70 @@ +# MACRO: exit +# Terminates execution. + .macro exit nr + + stp x29, x30, [sp,#-32]! + mov x4, #0x26 + mov x7, #\nr + mov x29, sp + movk x4, #0x2, lsl #16 + add x1, x29, #0x10 + str x4, [x29,#16] + str x7, [x29,#24] + mov w0, #0x18 + hlt #0xf000 + + .endm + +# MACRO: swiwrite +# Writes the string in X1 to stdout + .macro swiwrite len + + stp x29, x30, [sp,#-48]! + mov x0, #1 + mov x2, #\len + mov x29, sp + str x0, [x29,#24] + str x1, [x29,#32] + str x2, [x29,#40] + mov w0, #0x5 + add x1, x29, #0x18 + hlt #0xf000 + ldp x29, x30, [sp],#48 + ret + + .endm + +# MACRO: pass +# Write 'pass' to stdout and quit + .macro pass + + adrp x1, .Lpass + add x1, x1, :lo12:.Lpass + + swiwrite 5 + exit 0 + .endm + +# MACRO: fail +# Write 'fail' to stdout and quit + .macro fail + + adrp x1, .Lfail + add x1, x1, :lo12:.Lfail + swiwrite 5 + exit 1 + .endm + +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .data +.Lpass: + .asciz "pass\n" +.Lfail: + .asciz "fail\n" + + .text +.global _start +_start: + .endm diff --git a/sim/testsuite/aarch64/uzp.s b/sim/testsuite/aarch64/uzp.s new file mode 100644 index 0000000..851005e --- /dev/null +++ b/sim/testsuite/aarch64/uzp.s @@ -0,0 +1,216 @@ +# mach: aarch64 + +# Check the unzip instructions: uzp1, uzp2. + +.include "testutils.inc" + + .data + .align 4 +input1: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +input2: + .word 0x14131211 + .word 0x18171615 + .word 0x1c1b1a19 + .word 0x201f1e1d +zl8b: + .word 0x07050301 + .word 0x17151311 +zu8b: + .word 0x08060402 + .word 0x18161412 +zl16b: + .word 0x07050301 + .word 0x0f0d0b09 + .word 0x17151311 + .word 0x1f1d1b19 +zu16b: + .word 0x08060402 + .word 0x100e0c0a + .word 0x18161412 + .word 0x201e1c1a +zl4h: + .word 0x06050201 + .word 0x16151211 +zu4h: + .word 0x08070403 + .word 0x18171413 +zl8h: + .word 0x06050201 + .word 0x0e0d0a09 + .word 0x16151211 + .word 0x1e1d1a19 +zu8h: + .word 0x08070403 + .word 0x100f0c0b + .word 0x18171413 + .word 0x201f1c1b +zl2s: + .word 0x04030201 + .word 0x14131211 +zu2s: + .word 0x08070605 + .word 0x18171615 +zl4s: + .word 0x04030201 + .word 0x0c0b0a09 + .word 0x14131211 + .word 0x1c1b1a19 +zu4s: + .word 0x08070605 + .word 0x100f0e0d + .word 0x18171615 + .word 0x201f1e1d +zl2d: + .word 0x04030201 + .word 0x08070605 + .word 0x14131211 + .word 0x18171615 +zu2d: + .word 0x0c0b0a09 + .word 0x100f0e0d + .word 0x1c1b1a19 + .word 0x201f1e1d + + start + adrp x0, input1 + ldr q0, [x0, #:lo12:input1] + adrp x0, input2 + ldr q1, [x0, #:lo12:input2] + + uzp1 v2.8b, v0.8b, v1.8b + mov x1, v2.d[0] + adrp x3, zl8b + ldr x4, [x3, #:lo12:zl8b] + cmp x1, x4 + bne .Lfailure + + uzp2 v2.8b, v0.8b, v1.8b + mov x1, v2.d[0] + adrp x3, zu8b + ldr x4, [x3, #:lo12:zu8b] + cmp x1, x4 + bne .Lfailure + + uzp1 v2.16b, v0.16b, v1.16b + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, zl16b + ldr x4, [x3, #:lo12:zl16b] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:zl16b+8] + cmp x2, x5 + bne .Lfailure + + uzp2 v2.16b, v0.16b, v1.16b + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, zu16b + ldr x4, [x3, #:lo12:zu16b] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:zu16b+8] + cmp x2, x5 + bne .Lfailure + + uzp1 v2.4h, v0.4h, v1.4h + mov x1, v2.d[0] + adrp x3, zl4h + ldr x4, [x3, #:lo12:zl4h] + cmp x1, x4 + bne .Lfailure + + uzp2 v2.4h, v0.4h, v1.4h + mov x1, v2.d[0] + adrp x3, zu4h + ldr x4, [x3, #:lo12:zu4h] + cmp x1, x4 + bne .Lfailure + + uzp1 v2.8h, v0.8h, v1.8h + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, zl8h + ldr x4, [x3, #:lo12:zl8h] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:zl8h+8] + cmp x2, x5 + bne .Lfailure + + uzp2 v2.8h, v0.8h, v1.8h + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, zu8h + ldr x4, [x3, #:lo12:zu8h] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:zu8h+8] + cmp x2, x5 + bne .Lfailure + + uzp1 v2.2s, v0.2s, v1.2s + mov x1, v2.d[0] + adrp x3, zl2s + ldr x4, [x3, #:lo12:zl2s] + cmp x1, x4 + bne .Lfailure + + uzp2 v2.2s, v0.2s, v1.2s + mov x1, v2.d[0] + adrp x3, zu2s + ldr x4, [x3, #:lo12:zu2s] + cmp x1, x4 + bne .Lfailure + + uzp1 v2.4s, v0.4s, v1.4s + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, zl4s + ldr x4, [x3, #:lo12:zl4s] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:zl4s+8] + cmp x2, x5 + bne .Lfailure + + uzp2 v2.4s, v0.4s, v1.4s + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, zu4s + ldr x4, [x3, #:lo12:zu4s] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:zu4s+8] + cmp x2, x5 + bne .Lfailure + + uzp1 v2.2d, v0.2d, v1.2d + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, zl2d + ldr x4, [x3, #:lo12:zl2d] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:zl2d+8] + cmp x2, x5 + bne .Lfailure + + uzp2 v2.2d, v0.2d, v1.2d + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, zu2d + ldr x4, [x3, #:lo12:zu2d] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:zu2d+8] + cmp x2, x5 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/xtl.s b/sim/testsuite/aarch64/xtl.s new file mode 100644 index 0000000..16ef892 --- /dev/null +++ b/sim/testsuite/aarch64/xtl.s @@ -0,0 +1,101 @@ +#mach: aarch64 + +# Check the extend long instructions: sxtl, sxtl2, uxtl, uxtl2. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0xfcfdfeff + .word 0xf8f9fafb + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + uxtl v1.8h, v0.8b + uxtl2 v2.8h, v0.16b + addv h3, v1.8h + addv h4, v2.8h + mov x1, v3.d[0] + mov x2, v4.d[0] + cmp x1, #36 + bne .Lfailure + cmp x2, #2012 + bne .Lfailure + + uxtl v1.4s, v0.4h + uxtl2 v2.4s, v0.8h + addv s3, v1.4s + addv s4, v2.4s + mov x1, v3.d[0] + mov x2, v4.d[0] + mov x3, #5136 + cmp x1, x3 + bne .Lfailure + mov x4, #0xeff0 + movk x4, 0x3, lsl #16 + cmp x2, x4 + bne .Lfailure + + uxtl v1.2d, v0.2s + uxtl2 v2.2d, v0.4s + addv s3, v1.4s + addv s4, v2.4s + mov x1, v3.d[0] + mov x2, v4.d[0] + mov x3, #0x0806 + movk x3, #0x0c0a, lsl #16 + cmp x1, x3 + bne .Lfailure + mov x4, #0xf9fa + movk x4, #0xf5f7, lsl #16 + cmp x2, x4 + bne .Lfailure + + sxtl v1.8h, v0.8b + sxtl2 v2.8h, v0.16b + addv h3, v1.8h + addv h4, v2.8h + mov x1, v3.d[0] + mov x2, v4.d[0] + cmp x1, #36 + bne .Lfailure + mov x3, #0xffdc + cmp x2, x3 + bne .Lfailure + + sxtl v1.4s, v0.4h + sxtl2 v2.4s, v0.8h + addv s3, v1.4s + addv s4, v2.4s + mov x1, v3.d[0] + mov x2, v4.d[0] + mov x3, #5136 + cmp x1, x3 + bne .Lfailure + mov x4, #0xeff0 + movk x4, 0xffff, lsl #16 + bne .Lfailure + + sxtl v1.2d, v0.2s + sxtl2 v2.2d, v0.4s + addv s3, v1.4s + addv s4, v2.4s + mov x1, v3.d[0] + mov x2, v4.d[0] + mov x3, #0x0806 + movk x3, #0x0c0a, lsl #16 + cmp x1, x3 + bne .Lfailure + mov x4, #0xf9f8 + movk x4, #0xf5f7, lsl #16 + cmp x2, x4 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/aarch64/xtn.s b/sim/testsuite/aarch64/xtn.s new file mode 100644 index 0000000..de369f7 --- /dev/null +++ b/sim/testsuite/aarch64/xtn.s @@ -0,0 +1,79 @@ +# mach: aarch64 + +# Check the extract narrow instructions: xtn, xtn2. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +input2: + .word 0x14131211 + .word 0x18171615 + .word 0x1c1b1a19 + .word 0x201f1e1d +x16b: + .word 0x07050301 + .word 0x0f0d0b09 + .word 0x17151311 + .word 0x1f1d1b19 +x8h: + .word 0x06050201 + .word 0x0e0d0a09 + .word 0x16151211 + .word 0x1e1d1a19 +x4s: + .word 0x04030201 + .word 0x0c0b0a09 + .word 0x14131211 + .word 0x1c1b1a19 + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + adrp x0, input2 + ldr q1, [x0, #:lo12:input2] + + xtn v2.8b, v0.8h + xtn2 v2.16b, v1.8h + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, x16b + ldr x4, [x3, #:lo12:x16b] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:x16b+8] + cmp x2, x5 + bne .Lfailure + + xtn v2.4h, v0.4s + xtn2 v2.8h, v1.4s + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, x8h + ldr x4, [x3, #:lo12:x8h] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:x8h+8] + cmp x2, x5 + bne .Lfailure + + xtn v2.2s, v0.2d + xtn2 v2.4s, v1.2d + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, x4s + ldr x4, [x3, #:lo12:x4s] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:x4s+8] + cmp x2, x5 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/arm/ChangeLog b/sim/testsuite/arm/ChangeLog new file mode 100644 index 0000000..1237d81 --- /dev/null +++ b/sim/testsuite/arm/ChangeLog @@ -0,0 +1,122 @@ +2013-05-07 Jayant Sonar + Kaushik Phatak + + * movw-movt.ms: New file: Test movw & movt instructions. + +2011-07-01 Nick Clifton + + PR sim/12737 + * iwmmxt/wcmpgt.cgs: Remove expectation of failure. + * iwmmxt/wmac.cgs: Remove expectation of failure. + * iwmmxt/wsra.cgs: Remove expectation of failure. + * xscale/blx.cgs: Remove expectation of failure. + +2011-05-11 Joseph Myers + Hans-Peter Nilsson + + PR sim/12737 + * iwmmxt/wcmpgt.cgs, iwmmxt/wmac.cgs, + iwmmxt/wsra.cgs, xscale/blx.cgs: Kfail. + +2011-05-04 Joseph Myers + + * allinsn.exp (xscale*-*-*): Don't handle target. + * misc.exp (thumb*-*-*, xscale*-*-*): Don't handle + targets. + * iwmmxt/iwmmxt.exp: Test for arm*-*-* instead of + xscale*-*-*. + * thumb/allthumb.exp (thumb*-*-*): Don't handle target. + * xscale/xscale.exp: Test for arm*-*-* instead of + xscale*-*-*. + +2003-04-01 Nick Clifton + + * .: New directory: Tests for ARM simulator. + * allinsn.exp: New file: Test script. + * testutils.inc: New file: Test macros. + * adc.cgs, add.cgs, and.cgs, + b.cgs, bic.cgs, bl.cgs, bx.cgs, + cmn.cgs, cmp.cgs, eor.cgs, + hello.ms, ldm.cgs, ldr.cgs, + ldrb.cgs, ldrh.cgs, ldrsb.cgs, + ldrsh.cgs, misaligned1.ms, misaligned2.ms, + misaligned3.ms, misc.exp, mla.cgs, + mov.cgs, mrs.cgs, msr.cgs, + mul.cgs, mvn.cgs, orr.cgs, + rsb.cgs, rsc.cgs, sbc.cgs, + smlal.cgs, smull.cgs, stm.cgs, + str.cgs, strb.cgs, strh.cgs, + sub.cgs, swi.cgs, swp.cgs, + swpb.cgs, teq.cgs, tst.cgs, + umlal.cgs, umull.cgs: New files: ARM tests. + * iwmmxt: New Directory: Tests for iWMMXt. + * iwmmxt/iwmmxt.exp: New file: Test script. + * iwmmxt/testutils.inc: New file: Test macros. + * iwmmxt/tbcst.cgs, iwmmxt/textrm.cgs, + iwmmxt/tinsr.cgs, iwmmxt/tmia.cgs, + iwmmxt/tmiaph.cgs, iwmmxt/tmiaxy.cgs, + iwmmxt/tmovmsk.cgss, iwmmxt/wacc.cgs, + iwmmxt/wadd.cgs, iwmmxt/waligni.cgs, + iwmmxt/walignr.cgs, iwmmxt/wand.cgs, + iwmmxt/wandn.cgs, iwmmxt/wavg2.cgs, + iwmmxt/wcmpeq.cgs, iwmmxt/wcmpgt.cgs, + iwmmxt/wmac.cgs, iwmmxt/wmadd.cgs, + iwmmxt/wmax.cgs, iwmmxt/wmin.cgs, + iwmmxt/wmov.cgs, iwmmxt/wmul.cgs, + iwmmxt/wor.cgs, iwmmxt/wpack.cgs, + iwmmxt/wror.cgs, iwmmxt/wsad.cgs, + iwmmxt/wshufh.cgs, iwmmxt/wsll.cgs, + iwmmxt/wsra.cgs, iwmmxt/wsrl.cgs, + iwmmxt/wsub.cgs, iwmmxt/wunpckeh.cgs, + iwmmxt/wunpckel.cgs, iwmmxt/wunpckih.cgs, + iwmmxt/wunpckil.cgs, iwmmxt/wxor.cgs, + iwmmxt/wzero.cgs: New files: iWMMXt tests. + * thumb: New Directory: Thumb tests. + * thumb/allthumb.exp: New file: Test script. + * thumb/testutils.inc: New file: Test macros. + * thumb/adc.cgs, thumb/add-hd-hs.cgs, + thumb/add-hd-rs.cgs, thumb/add-rd-hs.cgs, + thumb/add-sp.cgs, thumb/add.cgs, + thumb/addi.cgs, thumb/addi8.cgs, + thumb/and.cgs, thumb/asr.cgs, thumb/b.cgs, + thumb/bcc.cgs, thumb/bcs.cgs, + thumb/beq.cgs, thumb/bge.cgs, + thumb/bgt.cgs, thumb/bhi.cgs, + thumb/bic.cgs, thumb/bl-hi.cgs, + thumb/bl-lo.cgs, thumb/ble.cgs, + thumb/bls.cgs, thumb/blt.cgs, + thumb/bmi.cgs, thumb/bne.cgs, + thumb/bpl.cgs, thumb/bvc.cgs, + thumb/bvs.cgs, thumb/bx-hs.cgs, + thumb/bx-rs.cgs, thumb/cmn.cgs, + thumb/cmp-hd-hs.cgs, thumb/cmp-hd-rs.cgs, + thumb/cmp-rd-hs.cgs, thumb/cmp.cgs, + thumb/eor.cgs, thumb/lda-pc.cgs, + thumb/lda-sp.cgs, thumb/ldmia.cgs, + thumb/ldr-imm.cgs, thumb/ldr-pc.cgs, + thumb/ldr-sprel.cgs, thumb/ldr.cgs, + thumb/ldrb-imm.cgs, thumb/ldrb.cgs, + thumb/ldrh-imm.cgs, thumb/ldrh.cgs, + thumb/ldsb.cgs, thumb/ldsh.cgs, + thumb/lsl.cgs, thumb/lsr.cgs, + thumb/mov-hd-hs.cgs, thumb/mov-hd-rs.cgs, + thumb/mov-rd-hs.cgs, thumb/mov.cgs, + thumb/mul.cgs, thumb/mvn.cgs, + thumb/neg.cgs, thumb/orr.cgs, + thumb/pop-pc.cgs, thumb/pop.cgs, + thumb/push-lr.cgs, thumb/push.cgs, + thumb/ror.cgs, thumb/sbc.cgs, + thumb/stmia.cgs, thumb/str-imm.cgs, + thumb/str-sprel.cgs, thumb/str.cgs, + thumb/strb-imm.cgs, thumb/strb.cgs, + thumb/strh-imm.cgs, thumb/strh.cgs, + thumb/sub-sp.cgs, thumb/sub.cgs, + thumb/subi.cgs, thumb/subi8.cgs, + thumb/swi.cgs, thumb/tst.cgs: New files: Thumb + tests. + * xscale: New directory. + * xscale/xscale.exp: New file: Test script. + * xscale/testutils.inc: New file: Test macros. + * xscale/blx.cgs, xscale/mia.cgs, + xscale/miaph.cgs, xscale/miaxy.cgs, + xscale/mra.cgs: New files: XScale tests. diff --git a/sim/testsuite/arm/adc.cgs b/sim/testsuite/arm/adc.cgs new file mode 100644 index 0000000..b6659a1 --- /dev/null +++ b/sim/testsuite/arm/adc.cgs @@ -0,0 +1,43 @@ +# arm testcase for adc +# mach: all + +# ??? Unfinished, more tests needed. + + .include "testutils.inc" + + start + +# adc$cond${set-cc?} $rd,$rn,$imm12 + + .global adc_imm +adc_imm: + mvi_h_gr r4,1 + mvi_h_cnvz 0,0,0,0 + adc r5,r4,#1 + test_h_cnvz 0,0,0,0 + test_h_gr r5,2 + +# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} + + .global adc_reg_imm_shift +adc_reg_imm_shift: + mvi_h_gr r4,1 + mvi_h_gr r5,1 + mvi_h_cnvz 0,0,0,0 + adc r6,r4,r5,lsl #2 + test_h_cnvz 0,0,0,0 + test_h_gr r6,5 + +# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} + + .global adc_reg_reg_shift +adc_reg_reg_shift: + mvi_h_gr r4,1 + mvi_h_gr r5,1 + mvi_h_gr r6,2 + mvi_h_cnvz 0,0,0,0 + adc r7,r4,r5,lsl r6 + test_h_cnvz 0,0,0,0 + test_h_gr r7,5 + + pass diff --git a/sim/testsuite/arm/add.cgs b/sim/testsuite/arm/add.cgs new file mode 100644 index 0000000..eba32e0 --- /dev/null +++ b/sim/testsuite/arm/add.cgs @@ -0,0 +1,43 @@ +# arm testcase for add +# mach: all + +# ??? Unfinished, more tests needed. + + .include "testutils.inc" + + start + +# add$cond${set-cc?} $rd,$rn,$imm12 + + .global add_imm +add_imm: + mvi_h_gr r4,1 + mvi_h_cnvz 0,0,0,0 + add r5,r4,#1 + test_h_cnvz 0,0,0,0 + test_h_gr r5,2 + +# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} + + .global add_reg_imm_shift +add_reg_imm_shift: + mvi_h_gr r4,1 + mvi_h_gr r5,1 + mvi_h_cnvz 0,0,0,0 + add r6,r4,r5,lsl #2 + test_h_cnvz 0,0,0,0 + test_h_gr r6,5 + +# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} + + .global add_reg_reg_shift +add_reg_reg_shift: + mvi_h_gr r4,1 + mvi_h_gr r5,1 + mvi_h_gr r6,2 + mvi_h_cnvz 0,0,0,0 + add r7,r4,r5,lsl r6 + test_h_cnvz 0,0,0,0 + test_h_gr r7,5 + + pass diff --git a/sim/testsuite/arm/allinsn.exp b/sim/testsuite/arm/allinsn.exp new file mode 100644 index 0000000..9752da6 --- /dev/null +++ b/sim/testsuite/arm/allinsn.exp @@ -0,0 +1,28 @@ +# ARM simulator testsuite. + +if { [istarget arm*-*-*] } { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "xscale" + + if [is_remote host] { + remote_download host $srcdir/$subdir/testutils.inc + } + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } + + if [is_remote host] { + remote_file host delete testutils.inc + } +} diff --git a/sim/testsuite/arm/and.cgs b/sim/testsuite/arm/and.cgs new file mode 100644 index 0000000..cd8f003 --- /dev/null +++ b/sim/testsuite/arm/and.cgs @@ -0,0 +1,43 @@ +# arm testcase for and +# mach: all + +# ??? Unfinished, more tests needed. + + .include "testutils.inc" + + start + +# and$cond${set-cc?} $rd,$rn,$imm12 + + .global and_imm +and_imm: + mvi_h_gr r4,1 + mvi_h_cnvz 0,0,0,0 + and r5,r4,#1 + test_h_cnvz 0,0,0,0 + test_h_gr r5,1 + +# and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} + + .global and_reg_imm_shift +and_reg_imm_shift: + mvi_h_gr r4,1 + mvi_h_gr r5,1 + mvi_h_cnvz 0,0,0,0 + and r6,r4,r5,lsl #1 + test_h_cnvz 0,0,0,0 + test_h_gr r6,0 + +# and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} + + .global and_reg_reg_shift +and_reg_reg_shift: + mvi_h_gr r4,1 + mvi_h_gr r5,1 + mvi_h_gr r6,1 + mvi_h_cnvz 0,0,0,0 + and r7,r4,r5,lsl r6 + test_h_cnvz 0,0,0,0 + test_h_gr r7,0 + + pass diff --git a/sim/testsuite/arm/b.cgs b/sim/testsuite/arm/b.cgs new file mode 100644 index 0000000..414b963 --- /dev/null +++ b/sim/testsuite/arm/b.cgs @@ -0,0 +1,261 @@ +# arm testcase for b$cond $offset24 +# mach: all + +# ??? Still need to test edge cases. + + .include "testutils.inc" + + start + + .global b +b: + +# b foo + + b balways1 + fail +balways1: + +# beq foo + + mvi_h_gr r4,4 + mvi_h_gr r5,4 + cmp r4,r5 + beq beq1 + fail +beq1: + mvi_h_gr r5,5 + cmp r4,r5 + beq beq2 + b beq3 +beq2: + fail +beq3: + +# bne foo + + mvi_h_gr r4,4 + mvi_h_gr r5,5 + cmp r4,r5 + bne bne1 + fail +bne1: + mvi_h_gr r5,4 + cmp r4,r5 + bne bne2 + b bne3 +bne2: + fail +bne3: + +# bcs foo + + mvi_h_cnvz 1,0,0,0 + bcs bcs1 + fail +bcs1: + mvi_h_cnvz 0,0,0,0 + bcs bcs2 + b bcs3 +bcs2: + fail +bcs3: + +# bcc foo + + mvi_h_cnvz 0,0,0,0 + bcc bcc1 + fail +bcc1: + mvi_h_cnvz 1,0,0,0 + bcc bcc2 + b bcc3 +bcc2: + fail +bcc3: + +# bmi foo + + mvi_h_cnvz 0,1,0,0 + bmi bmi1 + fail +bmi1: + mvi_h_cnvz 0,0,0,0 + bmi bmi2 + b bmi3 +bmi2: + fail +bmi3: + +# bpl foo + + mvi_h_cnvz 0,0,0,0 + bpl bpl1 + fail +bpl1: + mvi_h_cnvz 0,1,0,0 + bpl bpl2 + b bpl3 +bpl2: + fail +bpl3: + +# bvs foo + + mvi_h_cnvz 0,0,1,0 + bvs bvs1 + fail +bvs1: + mvi_h_cnvz 0,0,0,0 + bvs bvs2 + b bvs3 +bvs2: + fail +bvs3: + +# bvc foo + + mvi_h_cnvz 0,0,0,0 + bvc bvc1 + fail +bvc1: + mvi_h_cnvz 0,0,1,0 + bvc bvc2 + b bvc3 +bvc2: + fail +bvc3: + +# bhi foo + + mvi_h_gr r4,5 + mvi_h_gr r5,4 + cmp r4,r5 + bhi bhi1 + fail +bhi1: + mvi_h_gr r5,5 + cmp r4,r5 + bhi bhi2 + b bhi3 +bhi2: + fail +bhi3: + mvi_h_gr r5,6 + cmp r4,r5 + bhi bhi4 + b bhi5 +bhi4: + fail +bhi5: + +# bls foo + + mvi_h_gr r4,4 + mvi_h_gr r5,5 + cmp r4,r5 + bls bls1 + fail +bls1: + mvi_h_gr r5,4 + cmp r4,r5 + bls bls2 + fail +bls2: + mvi_h_gr r5,3 + cmp r4,r5 + bls bls3 + b bls4 +bls3: + fail +bls4: + +# bge foo + + mvi_h_gr r4,4 + mvi_h_gr r5,4 + cmp r4,r5 + bge bge1 + fail +bge1: + mvi_h_gr r5,3 + cmp r4,r5 + bge bge2 + fail +bge2: + mvi_h_gr r5,5 + cmp r4,r5 + bge bge3 + b bge4 +bge3: + fail +bge4: + +# blt foo + + mvi_h_gr r4,4 + mvi_h_gr r5,5 + cmp r4,r5 + blt blt1 + fail +blt1: + mvi_h_gr r5,4 + cmp r4,r5 + blt blt2 + b blt3 +blt2: + fail +blt3: + mvi_h_gr r5,3 + cmp r4,r5 + blt blt4 + b blt5 +blt4: + fail +blt5: + +# bgt foo + + mvi_h_gr r4,4 + mvi_h_gr r5,3 + cmp r4,r5 + bgt bgt1 + fail +bgt1: + mvi_h_gr r5,4 + cmp r4,r5 + bgt bgt2 + b bgt3 +bgt2: + fail +bgt3: + mvi_h_gr r5,5 + cmp r4,r5 + bgt bgt4 + b bgt5 +bgt4: + fail +bgt5: + +# ble foo + + mvi_h_gr r4,4 + mvi_h_gr r5,4 + cmp r4,r5 + ble ble1 + fail +ble1: + mvi_h_gr r5,5 + cmp r4,r5 + ble ble2 + fail +ble2: + mvi_h_gr r5,3 + cmp r4,r5 + ble ble3 + b ble4 +ble3: + fail +ble4: + + pass diff --git a/sim/testsuite/arm/bic.cgs b/sim/testsuite/arm/bic.cgs new file mode 100644 index 0000000..37a9b6c --- /dev/null +++ b/sim/testsuite/arm/bic.cgs @@ -0,0 +1,43 @@ +# arm testcase for bic +# mach: all + +# ??? Unfinished, more tests needed. + + .include "testutils.inc" + + start + +# bic$cond${set-cc?} $rd,$rn,$imm12 + + .global bic_imm +bic_imm: + mvi_h_gr r4,1 + mvi_h_cnvz 0,0,0,0 + bic r5,r4,#0 + test_h_cnvz 0,0,0,0 + test_h_gr r5,1 + +# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftimm} + + .global bic_reg_imm_shift +bic_reg_imm_shift: + mvi_h_gr r4,7 + mvi_h_gr r5,1 + mvi_h_cnvz 0,0,0,0 + bic r6,r4,r5,lsl #1 + test_h_cnvz 0,0,0,0 + test_h_gr r6,5 + +# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftreg} + + .global bic_reg_reg_shift +bic_reg_reg_shift: + mvi_h_gr r4,7 + mvi_h_gr r5,1 + mvi_h_gr r6,1 + mvi_h_cnvz 0,0,0,0 + bic r7,r4,r5,lsl r6 + test_h_cnvz 0,0,0,0 + test_h_gr r7,5 + + pass diff --git a/sim/testsuite/arm/bl.cgs b/sim/testsuite/arm/bl.cgs new file mode 100644 index 0000000..fbc7ef5 --- /dev/null +++ b/sim/testsuite/arm/bl.cgs @@ -0,0 +1,21 @@ +# arm testcase for bl$cond $offset24 +# mach: all + + .include "testutils.inc" + + start + + .global bl +bl: + mvi_h_gr r14,0 + bl bl2 +bl1: + fail +bl2: + mvaddr_h_gr r4,bl1 + cmp r14,r4 + beq bl3 + fail +bl3: + + pass diff --git a/sim/testsuite/arm/bx.cgs b/sim/testsuite/arm/bx.cgs new file mode 100644 index 0000000..4c18af4 --- /dev/null +++ b/sim/testsuite/arm/bx.cgs @@ -0,0 +1,12 @@ +# arm testcase for bx$cond $rn +# mach: unfinished + + .include "testutils.inc" + + start + + .global bx +bx: + bx0 pc + + pass diff --git a/sim/testsuite/arm/cmn.cgs b/sim/testsuite/arm/cmn.cgs new file mode 100644 index 0000000..1829fc7 --- /dev/null +++ b/sim/testsuite/arm/cmn.cgs @@ -0,0 +1,36 @@ +# arm testcase for cmn${cond}${set-cc?} $rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmn_imm +cmn_imm: + cmn00 pc,0 + + pass +# arm testcase for cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmn_reg_imm_shift +cmn_reg_imm_shift: + cmn00 pc,pc,pc,lsl 0 + + pass +# arm testcase for cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmn_reg_reg_shift +cmn_reg_reg_shift: + cmn00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/arm/cmp.cgs b/sim/testsuite/arm/cmp.cgs new file mode 100644 index 0000000..ab9dd59 --- /dev/null +++ b/sim/testsuite/arm/cmp.cgs @@ -0,0 +1,36 @@ +# arm testcase for cmp${cond}${set-cc?} $rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_imm +cmp_imm: + cmp00 pc,0 + + pass +# arm testcase for cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_reg_imm_shift +cmp_reg_imm_shift: + cmp00 pc,pc,pc,lsl 0 + + pass +# arm testcase for cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_reg_reg_shift +cmp_reg_reg_shift: + cmp00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/arm/eor.cgs b/sim/testsuite/arm/eor.cgs new file mode 100644 index 0000000..5bbb1c6 --- /dev/null +++ b/sim/testsuite/arm/eor.cgs @@ -0,0 +1,36 @@ +# arm testcase for eor$cond${set-cc?} $rd,$rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global eor_imm +eor_imm: + eor00 pc,pc,0 + + pass +# arm testcase for eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global eor_reg_imm_shift +eor_reg_imm_shift: + eor00 pc,pc,pc,lsl 0 + + pass +# arm testcase for eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global eor_reg_reg_shift +eor_reg_reg_shift: + eor00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/arm/hello.ms b/sim/testsuite/arm/hello.ms new file mode 100644 index 0000000..b063c29 --- /dev/null +++ b/sim/testsuite/arm/hello.ms @@ -0,0 +1,91 @@ +# output(): Hello, world.\n +# mach(): all + +# Emit hello world while switching back and forth between arm/thumb. +# ??? Unfinished + + .macro invalid +# This is "undefined" but it's not properly decoded yet. + .word 0x07ffffff +# This is stc which isn't recognized yet. + stc 0,cr0,[r0] + .endm + + .global _start +_start: +# Run some simple insns to confirm the engine is at least working. + nop + +# Skip over output text. + + bl skip_output + +hello_text: + .asciz "Hello, world.\n" + + .p2align 2 +skip_output: + +# Prime loop. + + mov r4, r14 + +output_next: + +# Switch arm->thumb to output next chacter. +# At this point r4 must point to the next character to output. + + adr r0, into_thumb + 1 + bx r0 + +into_thumb: + .thumb + +# Output a character. + + mov r0,#3 @ writec angel call + mov r1,r4 + swi 0xab @ ??? Confirm number. + +# Switch thumb->arm. + + adr r5, back_to_arm + bx r5 + + .p2align 2 +back_to_arm: + .arm + +# Load next character, see if done. + + add r4,r4,#1 + sub r3,r3,r3 + ldrb r5,[r4,r3] + teq r5,#0 + beq done + +# Output a character (in arm mode). + + mov r0,#3 + mov r1,r4 + swi #0x123456 + +# Load next character, see if done. + + add r4,r4,#1 + sub r3,r3,r3 + ldrb r5,[r4,r3] + teq r5,#0 + bne output_next + +done: + mov r0,#0x18 + ldr r1,exit_code + swi #0x123456 + +# If that fails, try to die with an invalid insn. + + invalid + +exit_code: + .word 0x20026 diff --git a/sim/testsuite/arm/iwmmxt/iwmmxt.exp b/sim/testsuite/arm/iwmmxt/iwmmxt.exp new file mode 100644 index 0000000..4def690 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/iwmmxt.exp @@ -0,0 +1,28 @@ +# Intel(r) Wireless MMX(tm) technology simulator testsuite. + +if { [istarget arm*-*-*] } { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "xscale" + + if [is_remote host] { + remote_download host $srcdir/$subdir/testutils.inc + } + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } + + if [is_remote host] { + remote_file host delete testutils.inc + } +} diff --git a/sim/testsuite/arm/iwmmxt/tbcst.cgs b/sim/testsuite/arm/iwmmxt/tbcst.cgs new file mode 100644 index 0000000..b7138df --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/tbcst.cgs @@ -0,0 +1,65 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TBCST +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global tbcst +tbcst: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte Wide Broadcast + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + tbcstb wr0, r2 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0xffffffff + test_h_gr r1, 0xffffffff + test_h_gr r2, 0x111111ff + + # Test Half Word Wide Broadcast + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + tbcsth wr0, r2 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x11ff11ff + test_h_gr r1, 0x11ff11ff + test_h_gr r2, 0x111111ff + + # Test Word Wide Broadcast + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + tbcstw wr0, r2 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x111111ff + test_h_gr r1, 0x111111ff + test_h_gr r2, 0x111111ff + + pass diff --git a/sim/testsuite/arm/iwmmxt/testutils.inc b/sim/testsuite/arm/iwmmxt/testutils.inc new file mode 100644 index 0000000..ae49db8 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/testutils.inc @@ -0,0 +1,118 @@ +# r0-r3 are used as tmps, consider them call clobbered by these macros. +# This uses the angel rom monitor calls. +# ??? How do we use the \@ facility of .macros ??? +# @ is the comment char! + + .macro mvi_h_gr reg, val + ldr \reg,[pc] + b . + 8 + .word \val + .endm + + .macro mvaddr_h_gr reg, addr + ldr \reg,[pc] + b . + 8 + .word \addr + .endm + + .macro start + .data +failmsg: + .asciz "fail\n" +passmsg: + .asciz "pass\n" + .text + +do_pass: + ldr r1, passmsg_addr + mov r0, #4 + swi #0x123456 + exit 0 +passmsg_addr: + .word passmsg + +do_fail: + ldr r1, failmsg_addr + mov r0, #4 + swi #0x123456 + exit 1 +failmsg_addr: + .word failmsg + + .global _start +_start: + .endm + +# *** Other macros know pass/fail are 4 bytes in size! Yuck. + + .macro pass + b do_pass + .endm + + .macro fail + b do_fail + .endm + + .macro exit rc + # ??? This works with the ARMulator but maybe not others. + #mov r0, #\rc + #swi #1 + # This seems to be portable (though it ignores rc). + mov r0,#0x18 + mvi_h_gr r1, 0x20026 + swi #0x123456 + # If that returns, punt with a sigill. + stc 0,cr0,[r0] + .endm + +# Other macros know this only clobbers r0. +# WARNING: It also clobbers the condition codes (FIXME). + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + cmp \reg, r0 + beq . + 8 + fail + .endm + + .macro mvi_h_cnvz c, n, v, z + mov r0, #0 + .if \c + orr r0, r0, #0x20000000 + .endif + .if \n + orr r0, r0, #0x80000000 + .endif + .if \v + orr r0, r0, #0x10000000 + .endif + .if \z + orr r0, r0, #0x40000000 + .endif + mrs r1, cpsr + bic r1, r1, #0xf0000000 + orr r1, r1, r0 + msr cpsr, r1 + # ??? nops needed + .endm + +# ??? Preserve condition codes? + .macro test_h_cnvz c, n, v, z + mov r0, #0 + .if \c + orr r0, r0, #0x20000000 + .endif + .if \n + orr r0, r0, #0x80000000 + .endif + .if \v + orr r0, r0, #0x10000000 + .endif + .if \z + orr r0, r0, #0x40000000 + .endif + mrs r1, cpsr + and r1, r1, #0xf0000000 + cmp r0, r1 + beq . + 8 + fail + .endm diff --git a/sim/testsuite/arm/iwmmxt/textrm.cgs b/sim/testsuite/arm/iwmmxt/textrm.cgs new file mode 100644 index 0000000..fb3dc94 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/textrm.cgs @@ -0,0 +1,113 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TEXTRM +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global textrm +textrm: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Wide Extraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + textrmub r2, wr0, #3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00000012 + + # Test Signed Byte Wide Extraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + textrmsb r2, wr0, #4 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0xfffffff0 + + # Test Unsigned Half Word Wide Extraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + textrmuh r2, wr0, #3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00009abc + + # Test Signed Half Word Wide Extraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + textrmsh r2, wr0, #1 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00001234 + + # Test Unsigned Word Wide Extraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + textrmuw r2, wr0, #0 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x12345678 + + # Test Signed Word Wide Extraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + textrmsw r2, wr0, #1 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x9abcdef0 + + pass diff --git a/sim/testsuite/arm/iwmmxt/tinsr.cgs b/sim/testsuite/arm/iwmmxt/tinsr.cgs new file mode 100644 index 0000000..f457b19 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/tinsr.cgs @@ -0,0 +1,65 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TINSR +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global tinsr +tinsr: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte Wide Insertion + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + tinsrb wr0, r2, #3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0xff345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x111111ff + + # Test Half Word Wide Insertion + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + tinsrh wr0, r2, #2 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abc11ff + test_h_gr r2, 0x111111ff + + # Test Word Wide Insertion + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + tinsrw wr0, r2, #1 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x111111ff + test_h_gr r2, 0x111111ff + + pass diff --git a/sim/testsuite/arm/iwmmxt/tmia.cgs b/sim/testsuite/arm/iwmmxt/tmia.cgs new file mode 100644 index 0000000..0b0da66 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/tmia.cgs @@ -0,0 +1,35 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TMIA +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global tmia +tmia: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + tmia wr0, r2, r3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x354f53c4 + test_h_gr r1, 0x4e330b5e + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/arm/iwmmxt/tmiaph.cgs b/sim/testsuite/arm/iwmmxt/tmiaph.cgs new file mode 100644 index 0000000..3778b0a --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/tmiaph.cgs @@ -0,0 +1,35 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TMIAPH +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global tmiaph +tmiaph: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + tmiaph wr0, r2, r3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0xfec3f9f4 + test_h_gr r1, 0x55667787 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/arm/iwmmxt/tmiaxy.cgs b/sim/testsuite/arm/iwmmxt/tmiaxy.cgs new file mode 100644 index 0000000..e7a7b73 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/tmiaxy.cgs @@ -0,0 +1,89 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TMIAxy +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global tmiaXY +tmiaXY: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Bottom Bottom Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + tmiaBB wr0, r2, r3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x05f753c4 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Bottom Top Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + tmiaBT wr0, r2, r3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0xeeede364 + test_h_gr r1, 0x55667787 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Top Bottom Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + tmiaTB wr0, r2, r3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x0ec85c04 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Top Top Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + tmiaTT wr0, r2, r3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x09eed974 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/arm/iwmmxt/tmovmsk.cgs b/sim/testsuite/arm/iwmmxt/tmovmsk.cgs new file mode 100644 index 0000000..cfea5b7 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/tmovmsk.cgs @@ -0,0 +1,65 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TMOVMSK +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global tmovmsk +tmovmsk: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte Wide Mask Transfer + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + + tmcrr wr0, r0, r1 + + tmovmskb r2, wr0 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x000000f0 + + # Test Half Word Wide Mask Transfer + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + + tmcrr wr0, r0, r1 + + tmovmskh r2, wr0 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x0000000c + + # Test Word Wide Mask Transfer + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + + tmcrr wr0, r0, r1 + + tmovmskw r2, wr0 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00000002 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wacc.cgs b/sim/testsuite/arm/iwmmxt/wacc.cgs new file mode 100644 index 0000000..b3ffea1 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wacc.cgs @@ -0,0 +1,77 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WACC +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wacc +wacc: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Wide Accumulation + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + waccb wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00000438 + test_h_gr r3, 0x00000000 + + # Test Unsigned Half Word Wide Accumulation + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wacch wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x0001e258 + test_h_gr r3, 0x00000000 + + # Test Unsigned Word Wide Accumulation + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + waccw wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0xacf13568 + test_h_gr r3, 0x00000000 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wadd.cgs b/sim/testsuite/arm/iwmmxt/wadd.cgs new file mode 100644 index 0000000..bb4d0ab --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wadd.cgs @@ -0,0 +1,251 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WADD +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wadd +wadd: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test UnSaturated Byte Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test Unsigned Saturated Byte Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddbus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test Signed Saturated Byte Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddbss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x2345677f + test_h_gr r5, 0xabcdef11 + + # Test UnSaturated Halfword Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test Unsigned Saturated Halfword Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddhus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test Signed Saturated Halfword Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddhss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test UnSaturated Word Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test Unsigned Saturated Word Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddwus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test Signed Saturated Word Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddwss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + pass diff --git a/sim/testsuite/arm/iwmmxt/waligni.cgs b/sim/testsuite/arm/iwmmxt/waligni.cgs new file mode 100644 index 0000000..dc99dae --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/waligni.cgs @@ -0,0 +1,43 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WALIGNI +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global waligni +waligni: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test 2 byte align + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waligni wr2, wr0, wr1, #2 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0xdef01234 + test_h_gr r5, 0x11119abc + + pass diff --git a/sim/testsuite/arm/iwmmxt/walignr.cgs b/sim/testsuite/arm/iwmmxt/walignr.cgs new file mode 100644 index 0000000..85df51e --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/walignr.cgs @@ -0,0 +1,137 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WALIGNR +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global walignr +walignr: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test 0 byte align + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + mvi_h_gr r6, 3 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + tmcr wcgr0, r6 + + walignr0 wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + tmrc r6, wcgr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0xbcdef012 + test_h_gr r5, 0x1111119a + test_h_gr r6, 3 + + # Test 1 byte align + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + mvi_h_gr r6, 4 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + tmcr wcgr1, r6 + + walignr1 wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + tmrc r6, wcgr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x9abcdef0 + test_h_gr r5, 0x11111111 + test_h_gr r6, 4 + + # Test 2 byte align + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + mvi_h_gr r6, 2 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + tmcr wcgr2, r6 + + walignr2 wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + tmrc r6, wcgr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0xdef01234 + test_h_gr r5, 0x11119abc + test_h_gr r6, 2 + + # Test 3 byte align + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + mvi_h_gr r6, 5 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + tmcr wcgr3, r6 + + walignr3 wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + tmrc r6, wcgr3 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x119abcde + test_h_gr r5, 0x00111111 + test_h_gr r6, 5 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wand.cgs b/sim/testsuite/arm/iwmmxt/wand.cgs new file mode 100644 index 0000000..018383f --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wand.cgs @@ -0,0 +1,41 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WAND +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wand +wand: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wand wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x10101010 + test_h_gr r5, 0x00000000 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wandn.cgs b/sim/testsuite/arm/iwmmxt/wandn.cgs new file mode 100644 index 0000000..f2c2305 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wandn.cgs @@ -0,0 +1,41 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WANDN +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wandn +wandn: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wandn wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x02244668 + test_h_gr r5, 0x9abcdef0 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wavg2.cgs b/sim/testsuite/arm/iwmmxt/wavg2.cgs new file mode 100644 index 0000000..cac2c1a --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wavg2.cgs @@ -0,0 +1,121 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WAVG2 +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wavg2 +wavg2: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte Wide Averaging + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wavg2b wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x11223344 + test_h_gr r5, 0x5e6f8089 + + # Test Byte Wide Averaging with Rounding + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wavg2br wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x12233445 + test_h_gr r5, 0x5e6f8089 + + # Test Half Word Wide Averaging + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wavg2h wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x11a233c4 + test_h_gr r5, 0x5e6f8089 + + # Test Half Word Wide Averaging with Rounding + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wavg2hr wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x11a333c5 + test_h_gr r5, 0x5e6f8089 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wcmpeq.cgs b/sim/testsuite/arm/iwmmxt/wcmpeq.cgs new file mode 100644 index 0000000..13ef3dc --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wcmpeq.cgs @@ -0,0 +1,95 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WCMPEQ +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wcmpeq +wcmpeq: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte Wide Compare Equal To + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x9abcde00 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpeqb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x9abcde00 + test_h_gr r4, 0x00000000 + test_h_gr r5, 0xffffffff + + # Test Half Word Wide Compare Equal To + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x9abcde00 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpeqh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x9abcde00 + test_h_gr r4, 0x00000000 + test_h_gr r5, 0xffffffff + + # Test Word Wide Compare Equal To + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x9abcde00 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpeqw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x9abcde00 + test_h_gr r4, 0x00000000 + test_h_gr r5, 0xffffffff + + pass diff --git a/sim/testsuite/arm/iwmmxt/wcmpgt.cgs b/sim/testsuite/arm/iwmmxt/wcmpgt.cgs new file mode 100644 index 0000000..33086c9 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wcmpgt.cgs @@ -0,0 +1,173 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WCMPGT +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wcmpgt +wcmpgt: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtub wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0xffffff00 + + # Test Signed Byte Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtsb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0x00000000 + + # Test Unsigned Half Word Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtuh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0xffffffff + + # Test Signed Half Word Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtsh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0x00000000 + + # Test Unsigned Word Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtuw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0xffffffff + + # Test Signed Word Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtsw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0x00000000 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wmac.cgs b/sim/testsuite/arm/iwmmxt/wmac.cgs new file mode 100644 index 0000000..0857ef9 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wmac.cgs @@ -0,0 +1,121 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WMAC +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wmac +wmac: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned, Multiply Accumulate, Non-zeroing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x33333333 + mvi_h_gr r5, 0x44444444 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmacu wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x6c889377 + test_h_gr r5, 0x44444444 + + # Test Unsigned, Multiply Accumulate, Zeroing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x33333333 + mvi_h_gr r5, 0x44444444 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmacuz wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x39556044 + test_h_gr r5, 0x00000000 + + # Test Signed, Multiply Accumulate, Non-zeroing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x33333333 + mvi_h_gr r5, 0x44444444 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmacs wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x28449377 + test_h_gr r5, 0x44444444 + + # Test Signed, Multiply Accumulate, Zeroing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x33333333 + mvi_h_gr r5, 0x44444444 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmacsz wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xf5116044 + test_h_gr r5, 0xffffffff + + pass diff --git a/sim/testsuite/arm/iwmmxt/wmadd.cgs b/sim/testsuite/arm/iwmmxt/wmadd.cgs new file mode 100644 index 0000000..564b3be --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wmadd.cgs @@ -0,0 +1,69 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WMADD +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wmadd +wmadd: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned, Multiply Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaddu wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x06fa5f6c + test_h_gr r5, 0x325b00d8 + + # Test Signed, Multiply Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmadds wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x06fa5f6c + test_h_gr r5, 0xee1700d8 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wmax.cgs b/sim/testsuite/arm/iwmmxt/wmax.cgs new file mode 100644 index 0000000..3a684ce --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wmax.cgs @@ -0,0 +1,173 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WMAX +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wmax +wmax: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Maximum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaxub wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x9abcde11 + + # Test Signed Byte Maximum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaxsb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x11111111 + + # Test Unsigned Halfword Maximum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaxuh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x9abcde00 + + # Test Signed Halfword Maximum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaxsh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x11111111 + + # Test Unsigned Word Maximum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaxuw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x9abcde00 + + # Test Signed Word Maximum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaxsw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x11111111 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wmin.cgs b/sim/testsuite/arm/iwmmxt/wmin.cgs new file mode 100644 index 0000000..3bc1c08 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wmin.cgs @@ -0,0 +1,173 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WMIN +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wmin +wmin: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Minimum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wminub wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x11111111 + test_h_gr r5, 0x11111100 + + # Test Signed Byte Minimum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wminsb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x11111111 + test_h_gr r5, 0x9abcde00 + + # Test Unsigned Halfword Minimum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wminuh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x11111111 + test_h_gr r5, 0x11111111 + + # Test Signed Halfword Minimum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wminsh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x11111111 + test_h_gr r5, 0x9abcde00 + + # Test Unsigned Word Minimum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wminuw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x11111111 + test_h_gr r5, 0x11111111 + + # Test Signed Word Minimum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wminsw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x11111111 + test_h_gr r5, 0x9abcde00 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wmov.cgs b/sim/testsuite/arm/iwmmxt/wmov.cgs new file mode 100644 index 0000000..e86fed6 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wmov.cgs @@ -0,0 +1,35 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WMOV +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wmov +wmov: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wmov wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wmul.cgs b/sim/testsuite/arm/iwmmxt/wmul.cgs new file mode 100644 index 0000000..0978b63 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wmul.cgs @@ -0,0 +1,121 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WMUL +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wmul +wmul: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned, Most Significant Multiply + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmulum wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x013605c3 + test_h_gr r5, 0x14a11db9 + + # Test Unsigned, Least Significant Multiply + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmulul wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xa974b5f8 + test_h_gr r5, 0x84f87be0 + + # Test Signed, Most Significant Multiply + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmulsm wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x013605c3 + test_h_gr r5, 0xf27ffb97 + + # Test Signed, Least Significant Multiply + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmulsl wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xa974b5f8 + test_h_gr r5, 0x84f87be0 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wor.cgs b/sim/testsuite/arm/iwmmxt/wor.cgs new file mode 100644 index 0000000..48d5f53 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wor.cgs @@ -0,0 +1,41 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WOR +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wor +wor: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wor wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x13355779 + test_h_gr r5, 0x9abcdef0 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wpack.cgs b/sim/testsuite/arm/iwmmxt/wpack.cgs new file mode 100644 index 0000000..0546bd4 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wpack.cgs @@ -0,0 +1,173 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WPACK +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wpack +wpack: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Halfword, Unsigned Saturation, Packing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wpackhus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x0000ffff + test_h_gr r5, 0x0000ffff + + # Test Halfword, Signed Saturation, Packing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wpackhss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x80807f7f + test_h_gr r5, 0x00007f7f + + # Test Word, Unsigned Saturation, Packing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wpackwus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x0000ffff + test_h_gr r5, 0x0000ffff + + # Test Word, Signed Saturation, Packing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wpackwss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x80007fff + test_h_gr r5, 0x00007fff + + # Test Double Word, Unsigned Saturation, Packing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wpackdus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x00000000 + test_h_gr r5, 0x11111111 + + # Test Double Word, Signed Saturation, Packing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wpackdss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x80000000 + test_h_gr r5, 0x11111111 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wror.cgs b/sim/testsuite/arm/iwmmxt/wror.cgs new file mode 100644 index 0000000..e329916 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wror.cgs @@ -0,0 +1,167 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WROR +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wror +wror: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Halfword wide rotate right by register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wrorh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x091a2b3c + test_h_gr r5, 0x4d5e6f78 + + # Test Halfword wide rotate right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr0, r2 + tmcrr wr1, r2, r3 + + wrorhg wr1, wr0, wcgr0 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr0 + tmrrc r3, r4, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x091a2b3c + test_h_gr r4, 0x4d5e6f78 + + # Test Word wide rotate right by register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wrorw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x2b3c091a + test_h_gr r5, 0x6f784d5e + + # Test Word wide rotate right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr0, r2 + tmcrr wr1, r2, r3 + + wrorwg wr1, wr0, wcgr0 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr0 + tmrrc r3, r4, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x2b3c091a + test_h_gr r4, 0x6f784d5e + + # Test Double Word wide rotate right by register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wrord wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x6f78091a + test_h_gr r5, 0x2b3c4d5e + + # Test Double Word wide rotate right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr0, r2 + tmcrr wr1, r2, r3 + + wrordg wr1, wr0, wcgr0 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr0 + tmrrc r3, r4, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x6f78091a + test_h_gr r4, 0x2b3c4d5e + + pass diff --git a/sim/testsuite/arm/iwmmxt/wsad.cgs b/sim/testsuite/arm/iwmmxt/wsad.cgs new file mode 100644 index 0000000..34a20cc --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wsad.cgs @@ -0,0 +1,121 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WSAD +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wsad +wsad: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte wide absolute accumulation + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x22222222 + mvi_h_gr r5, 0x22222222 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsadb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x2222258e + test_h_gr r5, 0x00000000 + + # Test Byte wide absolute accumulation with zeroing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x22222222 + mvi_h_gr r5, 0x22222222 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsadbz wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x0000036c + test_h_gr r5, 0x00000000 + + # Test Halfword wide absolute accumulation + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x22222222 + mvi_h_gr r5, 0x22222222 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsadh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x22239e14 + test_h_gr r5, 0x00000000 + + # Test Halfword wide absolute accumulation with zeroing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x22222222 + mvi_h_gr r5, 0x22222222 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsadhz wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x00017bf2 + test_h_gr r5, 0x00000000 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wshufh.cgs b/sim/testsuite/arm/iwmmxt/wshufh.cgs new file mode 100644 index 0000000..d5cff1e --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wshufh.cgs @@ -0,0 +1,35 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WSHUFH +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wshufh +wshufh: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wshufh wr1, wr0, #0x1b + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0xdef09abc + test_h_gr r3, 0x56781234 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wsll.cgs b/sim/testsuite/arm/iwmmxt/wsll.cgs new file mode 100644 index 0000000..17d7893 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wsll.cgs @@ -0,0 +1,167 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WSLL +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wsll +wsll: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Halfword Logical Shift Left + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsllh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23406780 + test_h_gr r5, 0xabc0ef00 + + # Test Halfword Aritc Shift Left by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr1, r2 + tmcrr wr1, r3, r4 + + wsllhg wr1, wr0, wcgr1 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr1 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x23406780 + test_h_gr r4, 0xabc0ef00 + + # Test Word Logical Shift Left + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsllw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456780 + test_h_gr r5, 0xabcdef00 + + # Test Word Logical Shift Left by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr2, r2 + tmcrr wr1, r3, r4 + + wsllwg wr1, wr0, wcgr2 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr2 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x23456780 + test_h_gr r4, 0xabcdef00 + + # Test Double Word Logical Shift Left + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdefc + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wslld wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdefc + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456780 + test_h_gr r5, 0xabcdefc1 + + # Test Double Word Logical Shift Left by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdefc + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr3, r2 + tmcrr wr1, r3, r4 + + wslldg wr1, wr0, wcgr3 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr3 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdefc + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x23456780 + test_h_gr r4, 0xabcdefc1 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wsra.cgs b/sim/testsuite/arm/iwmmxt/wsra.cgs new file mode 100644 index 0000000..db998bb --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wsra.cgs @@ -0,0 +1,167 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WSRA +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wsra +wsra: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Halfword Arithmetic Shift Right + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsrah wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01230567 + test_h_gr r5, 0xf9abfdef + + # Test Halfword Arithmetic Shift Right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr1, r2 + tmcrr wr1, r3, r4 + + wsrahg wr1, wr0, wcgr1 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr1 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x01230567 + test_h_gr r4, 0xf9abfdef + + # Test Word Arithmetic Shift Right + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsraw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0xf9abcdef + + # Test Word Arithmetic Shift Right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr2, r2 + tmcrr wr1, r3, r4 + + wsrawg wr1, wr0, wcgr2 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr2 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x01234567 + test_h_gr r4, 0xf9abcdef + + # Test Double Word Arithmetic Shift Right + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdefc + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsrad wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdefc + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0xc1234567 + test_h_gr r5, 0xf9abcdef + + # Test Double Word Arithmetic Shift Right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdefc + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr3, r2 + tmcrr wr1, r3, r4 + + wsradg wr1, wr0, wcgr3 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr3 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdefc + test_h_gr r2, 0x11111104 + test_h_gr r3, 0xc1234567 + test_h_gr r4, 0xf9abcdef + + pass diff --git a/sim/testsuite/arm/iwmmxt/wsrl.cgs b/sim/testsuite/arm/iwmmxt/wsrl.cgs new file mode 100644 index 0000000..416a464 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wsrl.cgs @@ -0,0 +1,167 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WSRL +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wsrl +wsrl: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Halfword Logical Shift Right + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsrlh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01230567 + test_h_gr r5, 0x09ab0def + + # Test Halfword Logical Shift Right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr1, r2 + tmcrr wr1, r3, r4 + + wsrlhg wr1, wr0, wcgr1 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr1 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x01230567 + test_h_gr r4, 0x09ab0def + + # Test Word Logical Shift Right + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsrlw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x09abcdef + + # Test Word Logical Shift Right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr2, r2 + tmcrr wr1, r3, r4 + + wsrlwg wr1, wr0, wcgr2 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr2 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x01234567 + test_h_gr r4, 0x09abcdef + + # Test Double Word Logical Shift Right + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdefc + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsrld wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdefc + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0xc1234567 + test_h_gr r5, 0x09abcdef + + # Test Double Word Logical Shift Right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdefc + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr3, r2 + tmcrr wr1, r3, r4 + + wsrldg wr1, wr0, wcgr3 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr3 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdefc + test_h_gr r2, 0x11111104 + test_h_gr r3, 0xc1234567 + test_h_gr r4, 0x09abcdef + + pass diff --git a/sim/testsuite/arm/iwmmxt/wsub.cgs b/sim/testsuite/arm/iwmmxt/wsub.cgs new file mode 100644 index 0000000..b0e77be --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wsub.cgs @@ -0,0 +1,251 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WSUB +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wsub +wsub: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsaturated Byte subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abcdef + + # Test Unsigned saturated Byte subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubbus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abcd00 + + # Test Signed saturated Byte subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubbss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abcdef + + # Test Unsaturated Halfword subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abccef + + # Test Unsigned saturated Halfword subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubhus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abccef + + # Test Signed saturated Halfword subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubhss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abccef + + # Test Unsaturated Word subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abccef + + # Test Unsigned saturated Word subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubwus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abccef + + # Test Signed saturated Word subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubwss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abccef + + pass diff --git a/sim/testsuite/arm/iwmmxt/wunpckeh.cgs b/sim/testsuite/arm/iwmmxt/wunpckeh.cgs new file mode 100644 index 0000000..32a70f4 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wunpckeh.cgs @@ -0,0 +1,137 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEH +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wunpckeh +wunpckeh: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Unpacking + + mvi_h_gr r0, 0x12345687 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckehub wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345687 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00de00f0 + test_h_gr r3, 0x009a00bc + + # Test Signed Byte Unpacking + + mvi_h_gr r0, 0x12345687 + mvi_h_gr r1, 0x7abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckehsb wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345687 + test_h_gr r1, 0x7abcdef0 + test_h_gr r2, 0xffdefff0 + test_h_gr r3, 0x007affbc + + # Test Unsigned Halfword Unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckehuh wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x0000def0 + test_h_gr r3, 0x00009abc + + # Test Signed Halfword Unpacking + + mvi_h_gr r0, 0x12348678 + mvi_h_gr r1, 0x7abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckehsh wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12348678 + test_h_gr r1, 0x7abcdef0 + test_h_gr r2, 0xffffdef0 + test_h_gr r3, 0x00007abc + + # Test Unsigned Word Unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckehuw wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x9abcdef0 + test_h_gr r3, 0x00000000 + + # Test Signed Word Unpacking + + mvi_h_gr r0, 0x82345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckehsw wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x82345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x9abcdef0 + test_h_gr r3, 0xffffffff + + pass diff --git a/sim/testsuite/arm/iwmmxt/wunpckel.cgs b/sim/testsuite/arm/iwmmxt/wunpckel.cgs new file mode 100644 index 0000000..a6ffb4f --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wunpckel.cgs @@ -0,0 +1,137 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEL +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wunpckel +wunpckel: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Unpacking + + mvi_h_gr r0, 0x12345687 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckelub wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345687 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00560087 + test_h_gr r3, 0x00120034 + + # Test Signed Byte Unpacking + + mvi_h_gr r0, 0x12345687 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckelsb wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345687 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x0056ff87 + test_h_gr r3, 0x00120034 + + # Test Unsigned Halfword Unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckeluh wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00005678 + test_h_gr r3, 0x00001234 + + # Test Signed Halfword Unpacking + + mvi_h_gr r0, 0x12348678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckelsh wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12348678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0xffff8678 + test_h_gr r3, 0x00001234 + + # Test Unsigned Word Unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckeluw wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x00000000 + + # Test Signed Word Unpacking + + mvi_h_gr r0, 0x82345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckelsw wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x82345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x82345678 + test_h_gr r3, 0xffffffff + + pass diff --git a/sim/testsuite/arm/iwmmxt/wunpckih.cgs b/sim/testsuite/arm/iwmmxt/wunpckih.cgs new file mode 100644 index 0000000..41fed0e --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wunpckih.cgs @@ -0,0 +1,95 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIH +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wunpckih +wunpckih: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wunpckihb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x00de00f0 + test_h_gr r5, 0x009a00bc + + # Test Halfword unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wunpckihh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x0000def0 + test_h_gr r5, 0x00009abc + + # Test Word unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wunpckihw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x9abcdef0 + test_h_gr r5, 0x00000000 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wunpckil.cgs b/sim/testsuite/arm/iwmmxt/wunpckil.cgs new file mode 100644 index 0000000..7bd7300 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wunpckil.cgs @@ -0,0 +1,95 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIL +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wunpckil +wunpckil: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wunpckilb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x11561178 + test_h_gr r5, 0x11121134 + + # Test Halfword unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wunpckilh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x11115678 + test_h_gr r5, 0x11111234 + + # Test Word unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wunpckilw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x11111111 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wxor.cgs b/sim/testsuite/arm/iwmmxt/wxor.cgs new file mode 100644 index 0000000..95e1fc8 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wxor.cgs @@ -0,0 +1,41 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WXOR +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wxor +wxor: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wxor wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x03254769 + test_h_gr r5, 0x9abcdef0 + + pass diff --git a/sim/testsuite/arm/iwmmxt/wzero.cgs b/sim/testsuite/arm/iwmmxt/wzero.cgs new file mode 100644 index 0000000..78fa7c5 --- /dev/null +++ b/sim/testsuite/arm/iwmmxt/wzero.cgs @@ -0,0 +1,29 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WZERO +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wzero +wzero: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + wzero wr0 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x00000000 + test_h_gr r1, 0x00000000 + + pass diff --git a/sim/testsuite/arm/ldm.cgs b/sim/testsuite/arm/ldm.cgs new file mode 100644 index 0000000..6831a83 --- /dev/null +++ b/sim/testsuite/arm/ldm.cgs @@ -0,0 +1,89 @@ +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmda_wb +ldmda_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmda +ldmda: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmdb_wb +ldmdb_wb: + + pass +# arm testcase for ldm$cond .. +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmdb +ldmdb: + ldm0 .. + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmia_wb +ldmia_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmia +ldmia: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmib_wb +ldmib_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmib +ldmib: + + pass diff --git a/sim/testsuite/arm/ldr.cgs b/sim/testsuite/arm/ldr.cgs new file mode 100644 index 0000000..437b68c --- /dev/null +++ b/sim/testsuite/arm/ldr.cgs @@ -0,0 +1,192 @@ +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_dec_imm_offset +ldr_post_dec_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_dec_nonpriv_imm_offset +ldr_post_dec_nonpriv_imm_offset: + ldr0t pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_dec_nonpriv_reg_offset +ldr_post_dec_nonpriv_reg_offset: + ldr0t pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_dec_reg_offset +ldr_post_dec_reg_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_inc_imm_offset +ldr_post_inc_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_inc_nonpriv_imm_offset +ldr_post_inc_nonpriv_imm_offset: + ldr0t pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_inc_nonpriv_reg_offset +ldr_post_inc_nonpriv_reg_offset: + ldr0t pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_inc_reg_offset +ldr_post_inc_reg_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_dec_imm_offset +ldr_pre_dec_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_dec_reg_offset +ldr_pre_dec_reg_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_dec_wb_imm_offset +ldr_pre_dec_wb_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_dec_wb_reg_offset +ldr_pre_dec_wb_reg_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_inc_imm_offset +ldr_pre_inc_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_inc_reg_offset +ldr_pre_inc_reg_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_inc_wb_imm_offset +ldr_pre_inc_wb_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_inc_wb_reg_offset +ldr_pre_inc_wb_reg_offset: + ldr0 pc,??? + + pass diff --git a/sim/testsuite/arm/ldrb.cgs b/sim/testsuite/arm/ldrb.cgs new file mode 100644 index 0000000..b09880c --- /dev/null +++ b/sim/testsuite/arm/ldrb.cgs @@ -0,0 +1,192 @@ +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_dec_imm_offset +ldrb_post_dec_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}bt $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_dec_nonpriv_imm_offset +ldrb_post_dec_nonpriv_imm_offset: + ldr0bt pc,??? + + pass +# arm testcase for ldr${cond}bt $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_dec_nonpriv_reg_offset +ldrb_post_dec_nonpriv_reg_offset: + ldr0bt pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_dec_reg_offset +ldrb_post_dec_reg_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_inc_imm_offset +ldrb_post_inc_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}bt $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_inc_nonpriv_imm_offset +ldrb_post_inc_nonpriv_imm_offset: + ldr0bt pc,??? + + pass +# arm testcase for ldr${cond}bt $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_inc_nonpriv_reg_offset +ldrb_post_inc_nonpriv_reg_offset: + ldr0bt pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_inc_reg_offset +ldrb_post_inc_reg_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_dec_imm_offset +ldrb_pre_dec_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_dec_reg_offset +ldrb_pre_dec_reg_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_dec_wb_imm_offset +ldrb_pre_dec_wb_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_dec_wb_reg_offset +ldrb_pre_dec_wb_reg_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_inc_imm_offset +ldrb_pre_inc_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_inc_reg_offset +ldrb_pre_inc_reg_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_inc_wb_imm_offset +ldrb_pre_inc_wb_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_inc_wb_reg_offset +ldrb_pre_inc_wb_reg_offset: + ldr0b pc,??? + + pass diff --git a/sim/testsuite/arm/ldrh.cgs b/sim/testsuite/arm/ldrh.cgs new file mode 100644 index 0000000..16a4323 --- /dev/null +++ b/sim/testsuite/arm/ldrh.cgs @@ -0,0 +1,132 @@ +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_post_dec_imm_offset +ldrh_post_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_post_dec_reg_offset +ldrh_post_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_post_inc_imm_offset +ldrh_post_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_post_inc_reg_offset +ldrh_post_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_dec_imm_offset +ldrh_pre_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_dec_reg_offset +ldrh_pre_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_dec_wb_imm_offset +ldrh_pre_dec_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_dec_wb_reg_offset +ldrh_pre_dec_wb_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_inc_imm_offset +ldrh_pre_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_inc_reg_offset +ldrh_pre_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_inc_wb_imm_offset +ldrh_pre_inc_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_inc_wb_reg_offset +ldrh_pre_inc_wb_reg_offset: + + pass diff --git a/sim/testsuite/arm/ldrsb.cgs b/sim/testsuite/arm/ldrsb.cgs new file mode 100644 index 0000000..4d08f4c --- /dev/null +++ b/sim/testsuite/arm/ldrsb.cgs @@ -0,0 +1,132 @@ +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_post_dec_imm_offset +ldrsb_post_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_post_dec_reg_offset +ldrsb_post_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_post_inc_imm_offset +ldrsb_post_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_post_inc_reg_offset +ldrsb_post_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_dec_imm_offset +ldrsb_pre_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_dec_reg_offset +ldrsb_pre_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_dec_wb_imm_offset +ldrsb_pre_dec_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_dec_wb_reg_offset +ldrsb_pre_dec_wb_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_inc_imm_offset +ldrsb_pre_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_inc_reg_offset +ldrsb_pre_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_inc_wb_imm_offset +ldrsb_pre_inc_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_inc_wb_reg_offset +ldrsb_pre_inc_wb_reg_offset: + + pass diff --git a/sim/testsuite/arm/ldrsh.cgs b/sim/testsuite/arm/ldrsh.cgs new file mode 100644 index 0000000..5a6e7c7 --- /dev/null +++ b/sim/testsuite/arm/ldrsh.cgs @@ -0,0 +1,132 @@ +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_post_dec_imm_offset +ldrsh_post_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_post_dec_reg_offset +ldrsh_post_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_post_inc_imm_offset +ldrsh_post_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_post_inc_reg_offset +ldrsh_post_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_dec_imm_offset +ldrsh_pre_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_dec_reg_offset +ldrsh_pre_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_dec_wb_imm_offset +ldrsh_pre_dec_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_dec_wb_reg_offset +ldrsh_pre_dec_wb_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_inc_imm_offset +ldrsh_pre_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_inc_reg_offset +ldrsh_pre_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_inc_wb_imm_offset +ldrsh_pre_inc_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_inc_wb_reg_offset +ldrsh_pre_inc_wb_reg_offset: + + pass diff --git a/sim/testsuite/arm/misaligned1.ms b/sim/testsuite/arm/misaligned1.ms new file mode 100644 index 0000000..69fda47 --- /dev/null +++ b/sim/testsuite/arm/misaligned1.ms @@ -0,0 +1,61 @@ +# Test LDR instructions with offsets misaligned by 1 byte. +# mach(): all + + .macro invalid +# This is "undefined" but it's not properly decoded yet. + .word 0x07ffffff +# This is stc which isn't recognized yet. + stc 0,cr0,[r0] + .endm + + .global _start +_start: +# Run some simple insns to confirm the engine is at least working. + nop + +# Skip over output text. + bl do_test + +pass: + .asciz "pass\n" + .p2align 2 + +do_test: + mov r4, r14 + bl continue +word1: + .word 0x5555 +continue: + ldr r6, [r14, #1] + ldr r7, word2 + cmp r6, r7 + # Failed. + bne done + +output_next: +# Output a character (in arm mode). + mov r0,#3 + mov r1,r4 + swi #0x123456 + +# Load next character, see if done. + add r4,r4,#1 + sub r3,r3,r3 + ldrb r5,[r4,r3] + teq r5,#0 + bne output_next + +done: + mov r0,#0x18 + ldr r1,exit_code + swi #0x123456 + +# If that fails, try to die with an invalid insn. + invalid + +exit_code: + .word 0x20026 + .word 0xFFFFFFFF +word2: + .word 0x55000055 + .word 0xFFFFFFFF diff --git a/sim/testsuite/arm/misaligned2.ms b/sim/testsuite/arm/misaligned2.ms new file mode 100644 index 0000000..3a03326 --- /dev/null +++ b/sim/testsuite/arm/misaligned2.ms @@ -0,0 +1,60 @@ +# Test LDR instructions with offsets misaligned by 2 bytes. +# mach(): all + + .macro invalid +# This is "undefined" but it's not properly decoded yet. + .word 0x07ffffff +# This is stc which isn't recognized yet. + stc 0,cr0,[r0] + .endm + + .global _start +_start: +# Run some simple insns to confirm the engine is at least working. + nop + +# Skip over output text. + bl do_test + +pass: + .asciz "pass\n" + .p2align 2 + +do_test: + mov r4, r14 + bl continue +word1: + .word 0x5555 +continue: + ldr r6, [r14, #2] + ldr r7, word2 + cmp r6, r7 + # Failed. + bne done + +output_next: +# Output a character (in arm mode). + mov r0,#3 + mov r1,r4 + swi #0x123456 + +# Load next character, see if done. + add r4,r4,#1 + sub r3,r3,r3 + ldrb r5,[r4,r3] + teq r5,#0 + bne output_next + +done: + mov r0,#0x18 + ldr r1,exit_code + swi #0x123456 + +# If that fails, try to die with an invalid insn. + invalid + +exit_code: + .word 0x20026 + +word2: + .word 0x55550000 diff --git a/sim/testsuite/arm/misaligned3.ms b/sim/testsuite/arm/misaligned3.ms new file mode 100644 index 0000000..bf2d9f1 --- /dev/null +++ b/sim/testsuite/arm/misaligned3.ms @@ -0,0 +1,62 @@ +# Test LDR instructions with offsets misaligned by 3 bytes. +# mach(): all + + .macro invalid +# This is "undefined" but it's not properly decoded yet. + .word 0x07ffffff +# This is stc which isn't recognized yet. + stc 0,cr0,[r0] + .endm + + .global _start +_start: +# Run some simple insns to confirm the engine is at least working. + nop + +# Skip over output text. + bl do_test + +pass: + .asciz "pass\n" + .p2align 2 + +do_test: + mov r4, r14 + bl continue +word1: + .word 0x5555 +continue: + ldr r6, [r14, #3] + ldr r7, word2 + cmp r6, r7 + # Failed. + bne done + +output_next: +# Output a character (in arm mode). + mov r0,#3 + mov r1,r4 + swi #0x123456 + +# Load next character, see if done. + add r4,r4,#1 + sub r3,r3,r3 + ldrb r5,[r4,r3] + teq r5,#0 + bne output_next + +done: + mov r0,#0x18 + ldr r1,exit_code + swi #0x123456 + +# If that fails, try to die with an invalid insn. + invalid + +exit_code: + .word 0x20026 + + .word 0xFFFFFFFF +word2: + .word 0x555500 + .word 0xFFFFFFFF diff --git a/sim/testsuite/arm/misc.exp b/sim/testsuite/arm/misc.exp new file mode 100644 index 0000000..bc36ca8 --- /dev/null +++ b/sim/testsuite/arm/misc.exp @@ -0,0 +1,20 @@ +# Miscellaneous ARM simulator testcases + +if { [istarget arm*-*-*] } { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "arm7tdmi" + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/arm/mla.cgs b/sim/testsuite/arm/mla.cgs new file mode 100644 index 0000000..c82dd0c --- /dev/null +++ b/sim/testsuite/arm/mla.cgs @@ -0,0 +1,12 @@ +# arm testcase for mla$cond${set-cc?} ${mul-rd},$rm,$rs,${mul-rn} +# mach: unfinished + + .include "testutils.inc" + + start + + .global mla +mla: + mla00 pc,pc,pc,pc + + pass diff --git a/sim/testsuite/arm/mov.cgs b/sim/testsuite/arm/mov.cgs new file mode 100644 index 0000000..d2a83d3 --- /dev/null +++ b/sim/testsuite/arm/mov.cgs @@ -0,0 +1,36 @@ +# arm testcase for mov$cond${set-cc?} $rd,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_imm +mov_imm: + mov00 pc,0 + + pass +# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_reg_imm_shift +mov_reg_imm_shift: + mov00 pc,pc,pc,lsl 0 + + pass +# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_reg_reg_shift +mov_reg_reg_shift: + mov00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/arm/movw-movt.ms b/sim/testsuite/arm/movw-movt.ms new file mode 100644 index 0000000..1be815d --- /dev/null +++ b/sim/testsuite/arm/movw-movt.ms @@ -0,0 +1,53 @@ +# output(): Hello, world.\n +# mach(): all + +# This is a test for movw & movt instructions. +# It emits hello world if movw & movt works appropriately. + + .macro invalid +# This is "undefined" but it's not properly decoded yet. + .word 0x07ffffff +# This is stc which isn't recognized yet. + stc 0,cr0,[r0] + .endm + + .global _start +_start: +# Run some simple insns to confirm the engine is at least working. + nop + +# Skip over output text. + + bl skip_output + +hello_text: + .asciz "Hello, world.\n" + + .p2align 2 +skip_output: + movw r4, #:lower16:hello_text + movt r4, #:upper16:hello_text + +output_next: +# Output a character + mov r0,#3 + mov r1,r4 + swi #0x123456 + +# Load next character, see if done. + add r4,r4,#1 + sub r3,r3,r3 + ldrb r5,[r4,r3] + teq r5,#0 + bne output_next + +done: + mov r0,#0x18 + ldr r1,exit_code + swi #0x123456 + +# If that fails, try to die with an invalid insn. + invalid + +exit_code: + .word 0x20026 diff --git a/sim/testsuite/arm/mrs.cgs b/sim/testsuite/arm/mrs.cgs new file mode 100644 index 0000000..22c5e95 --- /dev/null +++ b/sim/testsuite/arm/mrs.cgs @@ -0,0 +1,24 @@ +# arm testcase for mrs$cond $rd,cpsr +# mach: unfinished + + .include "testutils.inc" + + start + + .global mrs_c +mrs_c: + mrs0 pc,cpsr + + pass +# arm testcase for mrs$cond $rd,spsr +# mach: unfinished + + .include "testutils.inc" + + start + + .global mrs_s +mrs_s: + mrs0 pc,spsr + + pass diff --git a/sim/testsuite/arm/msr.cgs b/sim/testsuite/arm/msr.cgs new file mode 100644 index 0000000..c79f0bd --- /dev/null +++ b/sim/testsuite/arm/msr.cgs @@ -0,0 +1,24 @@ +# arm testcase for msr$cond cpsr,$rm +# mach: unfinished + + .include "testutils.inc" + + start + + .global msr_c +msr_c: + msr0 cpsr,pc + + pass +# arm testcase for msr$cond spsr,$rm +# mach: unfinished + + .include "testutils.inc" + + start + + .global msr_s +msr_s: + msr0 spsr,pc + + pass diff --git a/sim/testsuite/arm/mul.cgs b/sim/testsuite/arm/mul.cgs new file mode 100644 index 0000000..4f0a926 --- /dev/null +++ b/sim/testsuite/arm/mul.cgs @@ -0,0 +1,12 @@ +# arm testcase for mul$cond${set-cc?} ${mul-rd},$rm,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global mul +mul: + mul00 pc,pc,pc + + pass diff --git a/sim/testsuite/arm/mvn.cgs b/sim/testsuite/arm/mvn.cgs new file mode 100644 index 0000000..92fd3a4 --- /dev/null +++ b/sim/testsuite/arm/mvn.cgs @@ -0,0 +1,36 @@ +# arm testcase for mvn$cond${set-cc?} $rd,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global mvn_imm +mvn_imm: + mvn00 pc,0 + + pass +# arm testcase for mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global mvn_reg_imm_shift +mvn_reg_imm_shift: + mvn00 pc,pc,pc,lsl 0 + + pass +# arm testcase for mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global mvn_reg_reg_shift +mvn_reg_reg_shift: + mvn00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/arm/orr.cgs b/sim/testsuite/arm/orr.cgs new file mode 100644 index 0000000..3fc67ad --- /dev/null +++ b/sim/testsuite/arm/orr.cgs @@ -0,0 +1,36 @@ +# arm testcase for orr$cond${set-cc?} $rd,$rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global orr_imm +orr_imm: + orr00 pc,pc,0 + + pass +# arm testcase for orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global orr_reg_imm_shift +orr_reg_imm_shift: + orr00 pc,pc,pc,lsl 0 + + pass +# arm testcase for orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global orr_reg_reg_shift +orr_reg_reg_shift: + orr00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/arm/rsb.cgs b/sim/testsuite/arm/rsb.cgs new file mode 100644 index 0000000..14edc35 --- /dev/null +++ b/sim/testsuite/arm/rsb.cgs @@ -0,0 +1,36 @@ +# arm testcase for rsb$cond${set-cc?} $rd,$rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global rsb_imm +rsb_imm: + rsb00 pc,pc,0 + + pass +# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global rsb_reg_imm_shift +rsb_reg_imm_shift: + rsb00 pc,pc,pc,lsl 0 + + pass +# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global rsb_reg_reg_shift +rsb_reg_reg_shift: + rsb00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/arm/rsc.cgs b/sim/testsuite/arm/rsc.cgs new file mode 100644 index 0000000..078fbcc --- /dev/null +++ b/sim/testsuite/arm/rsc.cgs @@ -0,0 +1,36 @@ +# arm testcase for rsc$cond${set-cc?} $rd,$rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global rsc_imm +rsc_imm: + rsc00 pc,pc,0 + + pass +# arm testcase for rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global rsc_reg_imm_shift +rsc_reg_imm_shift: + rsc00 pc,pc,pc,lsl 0 + + pass +# arm testcase for rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global rsc_reg_reg_shift +rsc_reg_reg_shift: + rsc00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/arm/sbc.cgs b/sim/testsuite/arm/sbc.cgs new file mode 100644 index 0000000..9462702 --- /dev/null +++ b/sim/testsuite/arm/sbc.cgs @@ -0,0 +1,36 @@ +# arm testcase for sbc$cond${set-cc?} $rd,$rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global sbc_imm +sbc_imm: + sbc00 pc,pc,0 + + pass +# arm testcase for sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global sbc_reg_imm_shift +sbc_reg_imm_shift: + sbc00 pc,pc,pc,lsl 0 + + pass +# arm testcase for sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global sbc_reg_reg_shift +sbc_reg_reg_shift: + sbc00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/arm/smlal.cgs b/sim/testsuite/arm/smlal.cgs new file mode 100644 index 0000000..4ad1373 --- /dev/null +++ b/sim/testsuite/arm/smlal.cgs @@ -0,0 +1,12 @@ +# arm testcase for smlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global smlal +smlal: + smlal00 pc,pc,pc,pc + + pass diff --git a/sim/testsuite/arm/smull.cgs b/sim/testsuite/arm/smull.cgs new file mode 100644 index 0000000..22e3960 --- /dev/null +++ b/sim/testsuite/arm/smull.cgs @@ -0,0 +1,12 @@ +# arm testcase for smull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global smull +smull: + smull00 pc,pc,pc,pc + + pass diff --git a/sim/testsuite/arm/stm.cgs b/sim/testsuite/arm/stm.cgs new file mode 100644 index 0000000..c381216 --- /dev/null +++ b/sim/testsuite/arm/stm.cgs @@ -0,0 +1,88 @@ +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmda_wb +stmda_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmda +stmda: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmdb_wb +stmdb_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmdb +stmdb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmia_wb +stmia_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmia +stmia: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmib_wb +stmib_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmib +stmib: + + pass diff --git a/sim/testsuite/arm/str.cgs b/sim/testsuite/arm/str.cgs new file mode 100644 index 0000000..82c683b --- /dev/null +++ b/sim/testsuite/arm/str.cgs @@ -0,0 +1,192 @@ +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_dec_imm_offset +str_post_dec_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_dec_nonpriv_imm_offset +str_post_dec_nonpriv_imm_offset: + ldr0t pc,??? + + pass +# arm testcase for str${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_dec_nonpriv_reg_offset +str_post_dec_nonpriv_reg_offset: + str0t pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_dec_reg_offset +str_post_dec_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_inc_imm_offset +str_post_inc_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_inc_nonpriv_imm_offset +str_post_inc_nonpriv_imm_offset: + ldr0t pc,??? + + pass +# arm testcase for str${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_inc_nonpriv_reg_offset +str_post_inc_nonpriv_reg_offset: + str0t pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_inc_reg_offset +str_post_inc_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_dec_imm_offset +str_pre_dec_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_dec_reg_offset +str_pre_dec_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_dec_wb_imm_offset +str_pre_dec_wb_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_dec_wb_reg_offset +str_pre_dec_wb_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_inc_imm_offset +str_pre_inc_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_inc_reg_offset +str_pre_inc_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_inc_wb_imm_offset +str_pre_inc_wb_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_inc_wb_reg_offset +str_pre_inc_wb_reg_offset: + str0 pc,??? + + pass diff --git a/sim/testsuite/arm/strb.cgs b/sim/testsuite/arm/strb.cgs new file mode 100644 index 0000000..875a649 --- /dev/null +++ b/sim/testsuite/arm/strb.cgs @@ -0,0 +1,192 @@ +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_dec_imm_offset +strb_post_dec_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_dec_nonpriv_imm_offset +strb_post_dec_nonpriv_imm_offset: + ldr0t pc,??? + + pass +# arm testcase for str${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_dec_nonpriv_reg_offset +strb_post_dec_nonpriv_reg_offset: + str0t pc,??? + + pass +# arm testcase for str${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_dec_reg_offset +strb_post_dec_reg_offset: + str0b pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_inc_imm_offset +strb_post_inc_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_inc_nonpriv_imm_offset +strb_post_inc_nonpriv_imm_offset: + ldr0t pc,??? + + pass +# arm testcase for str${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_inc_nonpriv_reg_offset +strb_post_inc_nonpriv_reg_offset: + str0t pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_inc_reg_offset +strb_post_inc_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_dec_imm_offset +strb_pre_dec_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_dec_reg_offset +strb_pre_dec_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_dec_wb_imm_offset +strb_pre_dec_wb_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_dec_wb_reg_offset +strb_pre_dec_wb_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_inc_imm_offset +strb_pre_inc_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_inc_reg_offset +strb_pre_inc_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_inc_wb_imm_offset +strb_pre_inc_wb_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_inc_wb_reg_offset +strb_pre_inc_wb_reg_offset: + str0 pc,??? + + pass diff --git a/sim/testsuite/arm/strh.cgs b/sim/testsuite/arm/strh.cgs new file mode 100644 index 0000000..e111d48 --- /dev/null +++ b/sim/testsuite/arm/strh.cgs @@ -0,0 +1,132 @@ +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_post_dec_imm_offset +strh_post_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_post_dec_reg_offset +strh_post_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_post_inc_imm_offset +strh_post_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_post_inc_reg_offset +strh_post_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_dec_imm_offset +strh_pre_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_dec_reg_offset +strh_pre_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_dec_wb_imm_offset +strh_pre_dec_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_dec_wb_reg_offset +strh_pre_dec_wb_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_inc_imm_offset +strh_pre_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_inc_reg_offset +strh_pre_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_inc_wb_imm_offset +strh_pre_inc_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_inc_wb_reg_offset +strh_pre_inc_wb_reg_offset: + + pass diff --git a/sim/testsuite/arm/sub.cgs b/sim/testsuite/arm/sub.cgs new file mode 100644 index 0000000..50f222c --- /dev/null +++ b/sim/testsuite/arm/sub.cgs @@ -0,0 +1,36 @@ +# arm testcase for sub$cond${set-cc?} $rd,$rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global sub_imm +sub_imm: + sub00 pc,pc,0 + + pass +# arm testcase for sub$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global sub_reg_imm_shift +sub_reg_imm_shift: + sub00 pc,pc,pc,lsl 0 + + pass +# arm testcase for sub$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global sub_reg_reg_shift +sub_reg_reg_shift: + sub00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/arm/swi.cgs b/sim/testsuite/arm/swi.cgs new file mode 100644 index 0000000..0c23d43 --- /dev/null +++ b/sim/testsuite/arm/swi.cgs @@ -0,0 +1,12 @@ +# arm testcase for swi$cond ${swi-comment} +# mach: unfinished + + .include "testutils.inc" + + start + + .global swi +swi: + swi0 0 + + pass diff --git a/sim/testsuite/arm/swp.cgs b/sim/testsuite/arm/swp.cgs new file mode 100644 index 0000000..f965ef2 --- /dev/null +++ b/sim/testsuite/arm/swp.cgs @@ -0,0 +1,12 @@ +# arm testcase for swp$cond $rd,$rm,[$rn] +# mach: unfinished + + .include "testutils.inc" + + start + + .global swp +swp: + swp0 pc,pc,[pc] + + pass diff --git a/sim/testsuite/arm/swpb.cgs b/sim/testsuite/arm/swpb.cgs new file mode 100644 index 0000000..6f8a076 --- /dev/null +++ b/sim/testsuite/arm/swpb.cgs @@ -0,0 +1,12 @@ +# arm testcase for swpb${cond}b $rd,$rm,[$rn] +# mach: unfinished + + .include "testutils.inc" + + start + + .global swpb +swpb: + swpb0b pc,pc,[pc] + + pass diff --git a/sim/testsuite/arm/teq.cgs b/sim/testsuite/arm/teq.cgs new file mode 100644 index 0000000..6c69347 --- /dev/null +++ b/sim/testsuite/arm/teq.cgs @@ -0,0 +1,36 @@ +# arm testcase for teq${cond}${set-cc?} $rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global teq_imm +teq_imm: + teq00 pc,0 + + pass +# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global teq_reg_imm_shift +teq_reg_imm_shift: + teq00 pc,pc,pc,lsl 0 + + pass +# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global teq_reg_reg_shift +teq_reg_reg_shift: + teq00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/arm/testutils.inc b/sim/testsuite/arm/testutils.inc new file mode 100644 index 0000000..ae49db8 --- /dev/null +++ b/sim/testsuite/arm/testutils.inc @@ -0,0 +1,118 @@ +# r0-r3 are used as tmps, consider them call clobbered by these macros. +# This uses the angel rom monitor calls. +# ??? How do we use the \@ facility of .macros ??? +# @ is the comment char! + + .macro mvi_h_gr reg, val + ldr \reg,[pc] + b . + 8 + .word \val + .endm + + .macro mvaddr_h_gr reg, addr + ldr \reg,[pc] + b . + 8 + .word \addr + .endm + + .macro start + .data +failmsg: + .asciz "fail\n" +passmsg: + .asciz "pass\n" + .text + +do_pass: + ldr r1, passmsg_addr + mov r0, #4 + swi #0x123456 + exit 0 +passmsg_addr: + .word passmsg + +do_fail: + ldr r1, failmsg_addr + mov r0, #4 + swi #0x123456 + exit 1 +failmsg_addr: + .word failmsg + + .global _start +_start: + .endm + +# *** Other macros know pass/fail are 4 bytes in size! Yuck. + + .macro pass + b do_pass + .endm + + .macro fail + b do_fail + .endm + + .macro exit rc + # ??? This works with the ARMulator but maybe not others. + #mov r0, #\rc + #swi #1 + # This seems to be portable (though it ignores rc). + mov r0,#0x18 + mvi_h_gr r1, 0x20026 + swi #0x123456 + # If that returns, punt with a sigill. + stc 0,cr0,[r0] + .endm + +# Other macros know this only clobbers r0. +# WARNING: It also clobbers the condition codes (FIXME). + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + cmp \reg, r0 + beq . + 8 + fail + .endm + + .macro mvi_h_cnvz c, n, v, z + mov r0, #0 + .if \c + orr r0, r0, #0x20000000 + .endif + .if \n + orr r0, r0, #0x80000000 + .endif + .if \v + orr r0, r0, #0x10000000 + .endif + .if \z + orr r0, r0, #0x40000000 + .endif + mrs r1, cpsr + bic r1, r1, #0xf0000000 + orr r1, r1, r0 + msr cpsr, r1 + # ??? nops needed + .endm + +# ??? Preserve condition codes? + .macro test_h_cnvz c, n, v, z + mov r0, #0 + .if \c + orr r0, r0, #0x20000000 + .endif + .if \n + orr r0, r0, #0x80000000 + .endif + .if \v + orr r0, r0, #0x10000000 + .endif + .if \z + orr r0, r0, #0x40000000 + .endif + mrs r1, cpsr + and r1, r1, #0xf0000000 + cmp r0, r1 + beq . + 8 + fail + .endm diff --git a/sim/testsuite/arm/thumb/adc.cgs b/sim/testsuite/arm/thumb/adc.cgs new file mode 100644 index 0000000..58d74c1 --- /dev/null +++ b/sim/testsuite/arm/thumb/adc.cgs @@ -0,0 +1,12 @@ +# arm testcase for adc $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_adc +alu_adc: + adc r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/add-hd-hs.cgs b/sim/testsuite/arm/thumb/add-hd-hs.cgs new file mode 100644 index 0000000..0307acc --- /dev/null +++ b/sim/testsuite/arm/thumb/add-hd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $hd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global add_hd_hs +add_hd_hs: + add r8,r8 + + pass diff --git a/sim/testsuite/arm/thumb/add-hd-rs.cgs b/sim/testsuite/arm/thumb/add-hd-rs.cgs new file mode 100644 index 0000000..ca080f7 --- /dev/null +++ b/sim/testsuite/arm/thumb/add-hd-rs.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $hd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global add_hd_rs +add_hd_rs: + add r8,r0 + + pass diff --git a/sim/testsuite/arm/thumb/add-rd-hs.cgs b/sim/testsuite/arm/thumb/add-rd-hs.cgs new file mode 100644 index 0000000..46373a0 --- /dev/null +++ b/sim/testsuite/arm/thumb/add-rd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $rd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global add_rd_hs +add_rd_hs: + add r0,r8 + + pass diff --git a/sim/testsuite/arm/thumb/add-sp.cgs b/sim/testsuite/arm/thumb/add-sp.cgs new file mode 100644 index 0000000..54efa2a --- /dev/null +++ b/sim/testsuite/arm/thumb/add-sp.cgs @@ -0,0 +1,12 @@ +# arm testcase for add sp,#$sword7 +# mach: unfinished + + .include "testutils.inc" + + start + + .global add_sp +add_sp: + add sp,#0 + + pass diff --git a/sim/testsuite/arm/thumb/add.cgs b/sim/testsuite/arm/thumb/add.cgs new file mode 100644 index 0000000..63cc20c --- /dev/null +++ b/sim/testsuite/arm/thumb/add.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $rd,$rs,$rn +# mach: unfinished + + .include "testutils.inc" + + start + + .global add +add: + add r0,r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/addi.cgs b/sim/testsuite/arm/thumb/addi.cgs new file mode 100644 index 0000000..00ec76d --- /dev/null +++ b/sim/testsuite/arm/thumb/addi.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $rd,$rs,#$offset3 +# mach: unfinished + + .include "testutils.inc" + + start + + .global addi +addi: + add r0,r0,#0 + + pass diff --git a/sim/testsuite/arm/thumb/addi8.cgs b/sim/testsuite/arm/thumb/addi8.cgs new file mode 100644 index 0000000..d8e9f81 --- /dev/null +++ b/sim/testsuite/arm/thumb/addi8.cgs @@ -0,0 +1,12 @@ +# arm testcase for add ${bit10-rd},#$offset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global addi8 +addi8: + add r0,#0 + + pass diff --git a/sim/testsuite/arm/thumb/allthumb.exp b/sim/testsuite/arm/thumb/allthumb.exp new file mode 100644 index 0000000..4298663 --- /dev/null +++ b/sim/testsuite/arm/thumb/allthumb.exp @@ -0,0 +1,20 @@ +# ARM simulator testsuite. + +if { [istarget arm*-*-*] } { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "arm7tdmi" + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/arm/thumb/and.cgs b/sim/testsuite/arm/thumb/and.cgs new file mode 100644 index 0000000..d67adf4 --- /dev/null +++ b/sim/testsuite/arm/thumb/and.cgs @@ -0,0 +1,12 @@ +# arm testcase for and $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_and +alu_and: + and r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/asr.cgs b/sim/testsuite/arm/thumb/asr.cgs new file mode 100644 index 0000000..4d21dae --- /dev/null +++ b/sim/testsuite/arm/thumb/asr.cgs @@ -0,0 +1,14 @@ +# arm testcase for asr $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_asr +alu_asr: + asr r0,r0 + +# FIXME: Also asr $rd,$rs,#$offset5 + + pass diff --git a/sim/testsuite/arm/thumb/b.cgs b/sim/testsuite/arm/thumb/b.cgs new file mode 100644 index 0000000..ecae537 --- /dev/null +++ b/sim/testsuite/arm/thumb/b.cgs @@ -0,0 +1,12 @@ +# arm testcase for b $offset11 +# mach: unfinished + + .include "testutils.inc" + + start + + .global b +b: + b footext + + pass diff --git a/sim/testsuite/arm/thumb/bcc.cgs b/sim/testsuite/arm/thumb/bcc.cgs new file mode 100644 index 0000000..6c84458 --- /dev/null +++ b/sim/testsuite/arm/thumb/bcc.cgs @@ -0,0 +1,12 @@ +# arm testcase for bcc $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bcc +bcc: + bcc footext + + pass diff --git a/sim/testsuite/arm/thumb/bcs.cgs b/sim/testsuite/arm/thumb/bcs.cgs new file mode 100644 index 0000000..a29a8fb --- /dev/null +++ b/sim/testsuite/arm/thumb/bcs.cgs @@ -0,0 +1,12 @@ +# arm testcase for bcs $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bcs +bcs: + bcs footext + + pass diff --git a/sim/testsuite/arm/thumb/beq.cgs b/sim/testsuite/arm/thumb/beq.cgs new file mode 100644 index 0000000..33f3748 --- /dev/null +++ b/sim/testsuite/arm/thumb/beq.cgs @@ -0,0 +1,12 @@ +# arm testcase for beq $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global beq +beq: + beq footext + + pass diff --git a/sim/testsuite/arm/thumb/bge.cgs b/sim/testsuite/arm/thumb/bge.cgs new file mode 100644 index 0000000..4eb543d --- /dev/null +++ b/sim/testsuite/arm/thumb/bge.cgs @@ -0,0 +1,12 @@ +# arm testcase for bge $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bge +bge: + bge footext + + pass diff --git a/sim/testsuite/arm/thumb/bgt.cgs b/sim/testsuite/arm/thumb/bgt.cgs new file mode 100644 index 0000000..1ffe092 --- /dev/null +++ b/sim/testsuite/arm/thumb/bgt.cgs @@ -0,0 +1,12 @@ +# arm testcase for bgt $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bgt +bgt: + bgt footext + + pass diff --git a/sim/testsuite/arm/thumb/bhi.cgs b/sim/testsuite/arm/thumb/bhi.cgs new file mode 100644 index 0000000..c9811c6 --- /dev/null +++ b/sim/testsuite/arm/thumb/bhi.cgs @@ -0,0 +1,12 @@ +# arm testcase for bhi $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bhi +bhi: + bhi footext + + pass diff --git a/sim/testsuite/arm/thumb/bic.cgs b/sim/testsuite/arm/thumb/bic.cgs new file mode 100644 index 0000000..6dca1ef --- /dev/null +++ b/sim/testsuite/arm/thumb/bic.cgs @@ -0,0 +1,12 @@ +# arm testcase for bic $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_bic +alu_bic: + bic r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/bl-hi.cgs b/sim/testsuite/arm/thumb/bl-hi.cgs new file mode 100644 index 0000000..c7400c7 --- /dev/null +++ b/sim/testsuite/arm/thumb/bl-hi.cgs @@ -0,0 +1,12 @@ +# arm testcase for bl-hi ${lbwl-hi} +# mach: unfinished + + .include "testutils.inc" + + start + + .global bl_hi +bl_hi: + bl-hi 0 + + pass diff --git a/sim/testsuite/arm/thumb/bl-lo.cgs b/sim/testsuite/arm/thumb/bl-lo.cgs new file mode 100644 index 0000000..ed76613 --- /dev/null +++ b/sim/testsuite/arm/thumb/bl-lo.cgs @@ -0,0 +1,12 @@ +# arm testcase for bl-lo ${lbwl-lo} +# mach: unfinished + + .include "testutils.inc" + + start + + .global bl_lo +bl_lo: + bl-lo 0 + + pass diff --git a/sim/testsuite/arm/thumb/ble.cgs b/sim/testsuite/arm/thumb/ble.cgs new file mode 100644 index 0000000..e9c5a8f --- /dev/null +++ b/sim/testsuite/arm/thumb/ble.cgs @@ -0,0 +1,12 @@ +# arm testcase for ble $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global ble +ble: + ble footext + + pass diff --git a/sim/testsuite/arm/thumb/bls.cgs b/sim/testsuite/arm/thumb/bls.cgs new file mode 100644 index 0000000..483412b --- /dev/null +++ b/sim/testsuite/arm/thumb/bls.cgs @@ -0,0 +1,12 @@ +# arm testcase for bls $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bls +bls: + bls footext + + pass diff --git a/sim/testsuite/arm/thumb/blt.cgs b/sim/testsuite/arm/thumb/blt.cgs new file mode 100644 index 0000000..0fbcbe8 --- /dev/null +++ b/sim/testsuite/arm/thumb/blt.cgs @@ -0,0 +1,12 @@ +# arm testcase for blt $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global blt +blt: + blt footext + + pass diff --git a/sim/testsuite/arm/thumb/bmi.cgs b/sim/testsuite/arm/thumb/bmi.cgs new file mode 100644 index 0000000..8f7558a --- /dev/null +++ b/sim/testsuite/arm/thumb/bmi.cgs @@ -0,0 +1,12 @@ +# arm testcase for bmi $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bmi +bmi: + bmi footext + + pass diff --git a/sim/testsuite/arm/thumb/bne.cgs b/sim/testsuite/arm/thumb/bne.cgs new file mode 100644 index 0000000..a5ac348 --- /dev/null +++ b/sim/testsuite/arm/thumb/bne.cgs @@ -0,0 +1,12 @@ +# arm testcase for bne $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bne +bne: + bne footext + + pass diff --git a/sim/testsuite/arm/thumb/bpl.cgs b/sim/testsuite/arm/thumb/bpl.cgs new file mode 100644 index 0000000..8f64259 --- /dev/null +++ b/sim/testsuite/arm/thumb/bpl.cgs @@ -0,0 +1,12 @@ +# arm testcase for bpl $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bpl +bpl: + bpl footext + + pass diff --git a/sim/testsuite/arm/thumb/bvc.cgs b/sim/testsuite/arm/thumb/bvc.cgs new file mode 100644 index 0000000..bbd3af5 --- /dev/null +++ b/sim/testsuite/arm/thumb/bvc.cgs @@ -0,0 +1,12 @@ +# arm testcase for bvc $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bvc +bvc: + bvc footext + + pass diff --git a/sim/testsuite/arm/thumb/bvs.cgs b/sim/testsuite/arm/thumb/bvs.cgs new file mode 100644 index 0000000..8c9a551 --- /dev/null +++ b/sim/testsuite/arm/thumb/bvs.cgs @@ -0,0 +1,12 @@ +# arm testcase for bvs $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bvs +bvs: + bvs footext + + pass diff --git a/sim/testsuite/arm/thumb/bx-hs.cgs b/sim/testsuite/arm/thumb/bx-hs.cgs new file mode 100644 index 0000000..d963387 --- /dev/null +++ b/sim/testsuite/arm/thumb/bx-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for bx $hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global bx_hs +bx_hs: + bx r8 + + pass diff --git a/sim/testsuite/arm/thumb/bx-rs.cgs b/sim/testsuite/arm/thumb/bx-rs.cgs new file mode 100644 index 0000000..f6db8c8 --- /dev/null +++ b/sim/testsuite/arm/thumb/bx-rs.cgs @@ -0,0 +1,12 @@ +# arm testcase for bx $rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global bx_rs +bx_rs: + bx r0 + + pass diff --git a/sim/testsuite/arm/thumb/cmn.cgs b/sim/testsuite/arm/thumb/cmn.cgs new file mode 100644 index 0000000..96d53a1 --- /dev/null +++ b/sim/testsuite/arm/thumb/cmn.cgs @@ -0,0 +1,12 @@ +# arm testcase for cmn $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_cmn +alu_cmn: + cmn r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/cmp-hd-hs.cgs b/sim/testsuite/arm/thumb/cmp-hd-hs.cgs new file mode 100644 index 0000000..96a91a2 --- /dev/null +++ b/sim/testsuite/arm/thumb/cmp-hd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for cmp $hd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_hd_hs +cmp_hd_hs: + cmp r8,r8 + + pass diff --git a/sim/testsuite/arm/thumb/cmp-hd-rs.cgs b/sim/testsuite/arm/thumb/cmp-hd-rs.cgs new file mode 100644 index 0000000..9fc4875 --- /dev/null +++ b/sim/testsuite/arm/thumb/cmp-hd-rs.cgs @@ -0,0 +1,12 @@ +# arm testcase for cmp $hd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_hd_rs +cmp_hd_rs: + cmp r8,r0 + + pass diff --git a/sim/testsuite/arm/thumb/cmp-rd-hs.cgs b/sim/testsuite/arm/thumb/cmp-rd-hs.cgs new file mode 100644 index 0000000..e3f7a4a --- /dev/null +++ b/sim/testsuite/arm/thumb/cmp-rd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for cmp $rd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_rd_hs +cmp_rd_hs: + cmp r0,r8 + + pass diff --git a/sim/testsuite/arm/thumb/cmp.cgs b/sim/testsuite/arm/thumb/cmp.cgs new file mode 100644 index 0000000..7564099 --- /dev/null +++ b/sim/testsuite/arm/thumb/cmp.cgs @@ -0,0 +1,14 @@ +# arm testcase for cmp ${bit10-rd},#$offset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp +cmp: + cmp r0,#0 + +# FIXME: Also: cmp $rd,$rs + + pass diff --git a/sim/testsuite/arm/thumb/eor.cgs b/sim/testsuite/arm/thumb/eor.cgs new file mode 100644 index 0000000..cc6021c --- /dev/null +++ b/sim/testsuite/arm/thumb/eor.cgs @@ -0,0 +1,12 @@ +# arm testcase for eor $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_eor +alu_eor: + eor r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/lda-pc.cgs b/sim/testsuite/arm/thumb/lda-pc.cgs new file mode 100644 index 0000000..74407e2 --- /dev/null +++ b/sim/testsuite/arm/thumb/lda-pc.cgs @@ -0,0 +1,12 @@ +# arm testcase for add ${bit10-rd},pc,$word8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global lda_pc +lda_pc: + add r0,pc,0 + + pass diff --git a/sim/testsuite/arm/thumb/lda-sp.cgs b/sim/testsuite/arm/thumb/lda-sp.cgs new file mode 100644 index 0000000..ce2b62e --- /dev/null +++ b/sim/testsuite/arm/thumb/lda-sp.cgs @@ -0,0 +1,12 @@ +# arm testcase for add ${bit10-rd},sp,$word8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global lda_sp +lda_sp: + add r0,sp,0 + + pass diff --git a/sim/testsuite/arm/thumb/ldmia.cgs b/sim/testsuite/arm/thumb/ldmia.cgs new file mode 100644 index 0000000..550031e --- /dev/null +++ b/sim/testsuite/arm/thumb/ldmia.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldmia $rb!,{$rlist} +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmia +ldmia: + ldmia r0!,{0} + + pass diff --git a/sim/testsuite/arm/thumb/ldr-imm.cgs b/sim/testsuite/arm/thumb/ldr-imm.cgs new file mode 100644 index 0000000..a757f33 --- /dev/null +++ b/sim/testsuite/arm/thumb/ldr-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldr $rd,[$rb,#${offset5-7}] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_imm +ldr_imm: + ldr r0,[r0,#0] + + pass diff --git a/sim/testsuite/arm/thumb/ldr-pc.cgs b/sim/testsuite/arm/thumb/ldr-pc.cgs new file mode 100644 index 0000000..8227562 --- /dev/null +++ b/sim/testsuite/arm/thumb/ldr-pc.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldr ${bit10-rd},[pc,#$word8] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pc +ldr_pc: + ldr r0,[pc,#0] + + pass diff --git a/sim/testsuite/arm/thumb/ldr-sprel.cgs b/sim/testsuite/arm/thumb/ldr-sprel.cgs new file mode 100644 index 0000000..11eee26 --- /dev/null +++ b/sim/testsuite/arm/thumb/ldr-sprel.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldr ${bit10-rd},[sp,#$word8] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_sprel +ldr_sprel: + ldr r0,[sp,#0] + + pass diff --git a/sim/testsuite/arm/thumb/ldr.cgs b/sim/testsuite/arm/thumb/ldr.cgs new file mode 100644 index 0000000..03af925 --- /dev/null +++ b/sim/testsuite/arm/thumb/ldr.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldr $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr +ldr: + ldr r0,[r0,r0] + + pass diff --git a/sim/testsuite/arm/thumb/ldrb-imm.cgs b/sim/testsuite/arm/thumb/ldrb-imm.cgs new file mode 100644 index 0000000..c1eeafe --- /dev/null +++ b/sim/testsuite/arm/thumb/ldrb-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldrb $rd,[$rb,#$offset5] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_imm +ldrb_imm: + ldrb r0,[r0,#0] + + pass diff --git a/sim/testsuite/arm/thumb/ldrb.cgs b/sim/testsuite/arm/thumb/ldrb.cgs new file mode 100644 index 0000000..316a10f --- /dev/null +++ b/sim/testsuite/arm/thumb/ldrb.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldrb $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb +ldrb: + ldrb r0,[r0,r0] + + pass diff --git a/sim/testsuite/arm/thumb/ldrh-imm.cgs b/sim/testsuite/arm/thumb/ldrh-imm.cgs new file mode 100644 index 0000000..81ea1e0 --- /dev/null +++ b/sim/testsuite/arm/thumb/ldrh-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldrh $rd,[$rb,#${offset5-6}] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_imm +ldrh_imm: + ldrh r0,[r0,#0] + + pass diff --git a/sim/testsuite/arm/thumb/ldrh.cgs b/sim/testsuite/arm/thumb/ldrh.cgs new file mode 100644 index 0000000..3ff8f4e --- /dev/null +++ b/sim/testsuite/arm/thumb/ldrh.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldrh $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh +ldrh: + ldrh r0,[r0,r0] + + pass diff --git a/sim/testsuite/arm/thumb/ldsb.cgs b/sim/testsuite/arm/thumb/ldsb.cgs new file mode 100644 index 0000000..e1612c9 --- /dev/null +++ b/sim/testsuite/arm/thumb/ldsb.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldsb $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldsb +ldsb: + ldsb r0,[r0,r0] + + pass diff --git a/sim/testsuite/arm/thumb/ldsh.cgs b/sim/testsuite/arm/thumb/ldsh.cgs new file mode 100644 index 0000000..46d49ac --- /dev/null +++ b/sim/testsuite/arm/thumb/ldsh.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldsh $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldsh +ldsh: + ldsh r0,[r0,r0] + + pass diff --git a/sim/testsuite/arm/thumb/lsl.cgs b/sim/testsuite/arm/thumb/lsl.cgs new file mode 100644 index 0000000..05222e7 --- /dev/null +++ b/sim/testsuite/arm/thumb/lsl.cgs @@ -0,0 +1,14 @@ +# arm testcase for lsl $rd,$rs,#$offset5 +# mach: unfinished + + .include "testutils.inc" + + start + + .global lsl +lsl: + lsl r0,r0,#0 + +# FIXME: Also lsl $rd,$rs + + pass diff --git a/sim/testsuite/arm/thumb/lsr.cgs b/sim/testsuite/arm/thumb/lsr.cgs new file mode 100644 index 0000000..fe38fe0 --- /dev/null +++ b/sim/testsuite/arm/thumb/lsr.cgs @@ -0,0 +1,14 @@ +# arm testcase for lsr $rd,$rs,#$offset5 +# mach: unfinished + + .include "testutils.inc" + + start + + .global lsr +lsr: + lsr r0,r0,#0 + +# FIXME: Also lsr $rd,$rs + + pass diff --git a/sim/testsuite/arm/thumb/mov-hd-hs.cgs b/sim/testsuite/arm/thumb/mov-hd-hs.cgs new file mode 100644 index 0000000..2050908 --- /dev/null +++ b/sim/testsuite/arm/thumb/mov-hd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for mov $hd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_hd_hs +mov_hd_hs: + mov r8,r8 + + pass diff --git a/sim/testsuite/arm/thumb/mov-hd-rs.cgs b/sim/testsuite/arm/thumb/mov-hd-rs.cgs new file mode 100644 index 0000000..3d229c3 --- /dev/null +++ b/sim/testsuite/arm/thumb/mov-hd-rs.cgs @@ -0,0 +1,12 @@ +# arm testcase for mov $hd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_hd_rs +mov_hd_rs: + mov r8,r0 + + pass diff --git a/sim/testsuite/arm/thumb/mov-rd-hs.cgs b/sim/testsuite/arm/thumb/mov-rd-hs.cgs new file mode 100644 index 0000000..0661dfa --- /dev/null +++ b/sim/testsuite/arm/thumb/mov-rd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for mov $rd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_rd_hs +mov_rd_hs: + mov r0,r8 + + pass diff --git a/sim/testsuite/arm/thumb/mov.cgs b/sim/testsuite/arm/thumb/mov.cgs new file mode 100644 index 0000000..b497b0f --- /dev/null +++ b/sim/testsuite/arm/thumb/mov.cgs @@ -0,0 +1,12 @@ +# arm testcase for mov ${bit10-rd},#$offset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov +mov: + mov r0,#0 + + pass diff --git a/sim/testsuite/arm/thumb/mul.cgs b/sim/testsuite/arm/thumb/mul.cgs new file mode 100644 index 0000000..d160c56 --- /dev/null +++ b/sim/testsuite/arm/thumb/mul.cgs @@ -0,0 +1,12 @@ +# arm testcase for mul $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_mul +alu_mul: + mul r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/mvn.cgs b/sim/testsuite/arm/thumb/mvn.cgs new file mode 100644 index 0000000..606ce85 --- /dev/null +++ b/sim/testsuite/arm/thumb/mvn.cgs @@ -0,0 +1,12 @@ +# arm testcase for mvn $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_mvn +alu_mvn: + mvn r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/neg.cgs b/sim/testsuite/arm/thumb/neg.cgs new file mode 100644 index 0000000..09f0c81 --- /dev/null +++ b/sim/testsuite/arm/thumb/neg.cgs @@ -0,0 +1,12 @@ +# arm testcase for neg $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_neg +alu_neg: + neg r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/orr.cgs b/sim/testsuite/arm/thumb/orr.cgs new file mode 100644 index 0000000..de6f688 --- /dev/null +++ b/sim/testsuite/arm/thumb/orr.cgs @@ -0,0 +1,12 @@ +# arm testcase for orr $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_orr +alu_orr: + orr r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/pop-pc.cgs b/sim/testsuite/arm/thumb/pop-pc.cgs new file mode 100644 index 0000000..4579cad --- /dev/null +++ b/sim/testsuite/arm/thumb/pop-pc.cgs @@ -0,0 +1,12 @@ +# arm testcase for pop {${rlist-pc}} +# mach: unfinished + + .include "testutils.inc" + + start + + .global pop_pc +pop_pc: + pop {0} + + pass diff --git a/sim/testsuite/arm/thumb/pop.cgs b/sim/testsuite/arm/thumb/pop.cgs new file mode 100644 index 0000000..b156e1d --- /dev/null +++ b/sim/testsuite/arm/thumb/pop.cgs @@ -0,0 +1,12 @@ +# arm testcase for pop {$rlist} +# mach: unfinished + + .include "testutils.inc" + + start + + .global pop +pop: + pop {0} + + pass diff --git a/sim/testsuite/arm/thumb/push-lr.cgs b/sim/testsuite/arm/thumb/push-lr.cgs new file mode 100644 index 0000000..ee700a4 --- /dev/null +++ b/sim/testsuite/arm/thumb/push-lr.cgs @@ -0,0 +1,12 @@ +# arm testcase for push {${rlist-lr}} +# mach: unfinished + + .include "testutils.inc" + + start + + .global push_lr +push_lr: + push {0} + + pass diff --git a/sim/testsuite/arm/thumb/push.cgs b/sim/testsuite/arm/thumb/push.cgs new file mode 100644 index 0000000..ff94ca5 --- /dev/null +++ b/sim/testsuite/arm/thumb/push.cgs @@ -0,0 +1,12 @@ +# arm testcase for push {$rlist} +# mach: unfinished + + .include "testutils.inc" + + start + + .global push +push: + push {0} + + pass diff --git a/sim/testsuite/arm/thumb/ror.cgs b/sim/testsuite/arm/thumb/ror.cgs new file mode 100644 index 0000000..991fa66 --- /dev/null +++ b/sim/testsuite/arm/thumb/ror.cgs @@ -0,0 +1,12 @@ +# arm testcase for ror $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_ror +alu_ror: + ror r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/sbc.cgs b/sim/testsuite/arm/thumb/sbc.cgs new file mode 100644 index 0000000..078b061 --- /dev/null +++ b/sim/testsuite/arm/thumb/sbc.cgs @@ -0,0 +1,12 @@ +# arm testcase for sbc $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_sbc +alu_sbc: + sbc r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/stmia.cgs b/sim/testsuite/arm/thumb/stmia.cgs new file mode 100644 index 0000000..0e1c30c --- /dev/null +++ b/sim/testsuite/arm/thumb/stmia.cgs @@ -0,0 +1,12 @@ +# arm testcase for stmia $rb!,{$rlist} +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmia +stmia: + stmia r0!,{0} + + pass diff --git a/sim/testsuite/arm/thumb/str-imm.cgs b/sim/testsuite/arm/thumb/str-imm.cgs new file mode 100644 index 0000000..ce75941 --- /dev/null +++ b/sim/testsuite/arm/thumb/str-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for str $rd,[$rb,#${offset5-7}] +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_imm +str_imm: + str r0,[r0,#0] + + pass diff --git a/sim/testsuite/arm/thumb/str-sprel.cgs b/sim/testsuite/arm/thumb/str-sprel.cgs new file mode 100644 index 0000000..132edfb --- /dev/null +++ b/sim/testsuite/arm/thumb/str-sprel.cgs @@ -0,0 +1,12 @@ +# arm testcase for str ${bit10-rd},[sp,#$word8] +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_sprel +str_sprel: + str r0,[sp,#0] + + pass diff --git a/sim/testsuite/arm/thumb/str.cgs b/sim/testsuite/arm/thumb/str.cgs new file mode 100644 index 0000000..073e20b --- /dev/null +++ b/sim/testsuite/arm/thumb/str.cgs @@ -0,0 +1,12 @@ +# arm testcase for str $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global str +str: + str r0,[r0,r0] + + pass diff --git a/sim/testsuite/arm/thumb/strb-imm.cgs b/sim/testsuite/arm/thumb/strb-imm.cgs new file mode 100644 index 0000000..2b5bcf7 --- /dev/null +++ b/sim/testsuite/arm/thumb/strb-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for strb $rd,[$rb,#$offset5] +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_imm +strb_imm: + strb r0,[r0,#0] + + pass diff --git a/sim/testsuite/arm/thumb/strb.cgs b/sim/testsuite/arm/thumb/strb.cgs new file mode 100644 index 0000000..b7cb763 --- /dev/null +++ b/sim/testsuite/arm/thumb/strb.cgs @@ -0,0 +1,12 @@ +# arm testcase for strb $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb +strb: + strb r0,[r0,r0] + + pass diff --git a/sim/testsuite/arm/thumb/strh-imm.cgs b/sim/testsuite/arm/thumb/strh-imm.cgs new file mode 100644 index 0000000..9500288 --- /dev/null +++ b/sim/testsuite/arm/thumb/strh-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for strh $rd,[$rb,#${offset5-6}] +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_imm +strh_imm: + strh r0,[r0,#0] + + pass diff --git a/sim/testsuite/arm/thumb/strh.cgs b/sim/testsuite/arm/thumb/strh.cgs new file mode 100644 index 0000000..13f3a0d --- /dev/null +++ b/sim/testsuite/arm/thumb/strh.cgs @@ -0,0 +1,12 @@ +# arm testcase for strh $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh +strh: + strh r0,[r0,r0] + + pass diff --git a/sim/testsuite/arm/thumb/sub-sp.cgs b/sim/testsuite/arm/thumb/sub-sp.cgs new file mode 100644 index 0000000..e676f58 --- /dev/null +++ b/sim/testsuite/arm/thumb/sub-sp.cgs @@ -0,0 +1,12 @@ +# arm testcase for add sp,#-$sword7 +# mach: unfinished + + .include "testutils.inc" + + start + + .global sub_sp +sub_sp: + add sp,#-0 + + pass diff --git a/sim/testsuite/arm/thumb/sub.cgs b/sim/testsuite/arm/thumb/sub.cgs new file mode 100644 index 0000000..91cd7ab --- /dev/null +++ b/sim/testsuite/arm/thumb/sub.cgs @@ -0,0 +1,12 @@ +# arm testcase for sub $rd,$rs,$rn +# mach: unfinished + + .include "testutils.inc" + + start + + .global sub +sub: + sub r0,r0,r0 + + pass diff --git a/sim/testsuite/arm/thumb/subi.cgs b/sim/testsuite/arm/thumb/subi.cgs new file mode 100644 index 0000000..044efd0 --- /dev/null +++ b/sim/testsuite/arm/thumb/subi.cgs @@ -0,0 +1,12 @@ +# arm testcase for sub $rd,$rs,#$offset3 +# mach: unfinished + + .include "testutils.inc" + + start + + .global subi +subi: + sub r0,r0,#0 + + pass diff --git a/sim/testsuite/arm/thumb/subi8.cgs b/sim/testsuite/arm/thumb/subi8.cgs new file mode 100644 index 0000000..0c4d717 --- /dev/null +++ b/sim/testsuite/arm/thumb/subi8.cgs @@ -0,0 +1,12 @@ +# arm testcase for sub ${bit10-rd},#$offset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global subi8 +subi8: + sub r0,#0 + + pass diff --git a/sim/testsuite/arm/thumb/swi.cgs b/sim/testsuite/arm/thumb/swi.cgs new file mode 100644 index 0000000..1724c14 --- /dev/null +++ b/sim/testsuite/arm/thumb/swi.cgs @@ -0,0 +1,12 @@ +# arm testcase for swi $value8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global swi +swi: + swi 0 + + pass diff --git a/sim/testsuite/arm/thumb/testutils.inc b/sim/testsuite/arm/thumb/testutils.inc new file mode 100644 index 0000000..bdae29b --- /dev/null +++ b/sim/testsuite/arm/thumb/testutils.inc @@ -0,0 +1,91 @@ +# FIXME: wip, copied from ../testutils.inc +# r0-r3 are used as tmps, consider them call clobbered by these macros. +# This uses the angel rom monitor calls. +# ??? How do we use the \@ facility of .macros ??? +# @ is the comment char! + + .macro a_mvi_h_gr reg, val + ldr \reg,[pc] + b . + 8 + .word \val + .endm + + .macro mvaddr_h_gr reg, addr + ldr \reg,[pc] + b . + 8 + .word \val + .endm + + .macro start + .data +failmsg: + .asciz "fail\n" +passmsg: + .asciz "pass\n" + .text + +do_pass: + ldr r1, passmsg_addr + mov r0, #4 + swi #0x123456 + exit 0 +passmsg_addr: + .word passmsg + +do_fail: + ldr r1, failmsg_addr + mov r0, #4 + swi #0x123456 + exit 1 +failmsg_addr: + .word failmsg + + .global _start +_start: + .endm + +# *** Other macros know pass/fail are 4 bytes in size! Yuck. + + .macro pass + b do_pass + .endm + + .macro fail + b do_fail + .endm + + .macro exit rc + mov r1, #\rc + mov r0, #0x2a @ decimal 42 + swi #1 + # If that returns, punt with a sigill. + stc 0,cr0,[r0] + .endm + +# Other macros know this only clobbers r0. + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + cmp \reg, r0 + beq . + 8 + fail + .endm + + .macro mvi_h_cc c, n, v, z + ldi8 r0, 0 + ldi8 r1, 1 + .if xxx + cmp r0, r1 + .else + cmp r1, r0 + .endif + .endm + + .macro test_h_cc c, n, v, z + .if xxx + bc . + 8 + fail + .else + bnc . + 8 + fail + .endif + .endm diff --git a/sim/testsuite/arm/thumb/tst.cgs b/sim/testsuite/arm/thumb/tst.cgs new file mode 100644 index 0000000..068fccc --- /dev/null +++ b/sim/testsuite/arm/thumb/tst.cgs @@ -0,0 +1,12 @@ +# arm testcase for tst $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_tst +alu_tst: + tst r0,r0 + + pass diff --git a/sim/testsuite/arm/tst.cgs b/sim/testsuite/arm/tst.cgs new file mode 100644 index 0000000..f071707 --- /dev/null +++ b/sim/testsuite/arm/tst.cgs @@ -0,0 +1,36 @@ +# arm testcase for tst${cond}${set-cc?} $rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global tst_imm +tst_imm: + tst00 pc,0 + + pass +# arm testcase for tst$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global tst_reg_imm_shift +tst_reg_imm_shift: + tst00 pc,pc,pc,lsl 0 + + pass +# arm testcase for tst$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global tst_reg_reg_shift +tst_reg_reg_shift: + tst00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/arm/umlal.cgs b/sim/testsuite/arm/umlal.cgs new file mode 100644 index 0000000..1c17fb6 --- /dev/null +++ b/sim/testsuite/arm/umlal.cgs @@ -0,0 +1,12 @@ +# arm testcase for umlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global umlal +umlal: + umlal00 pc,pc,pc,pc + + pass diff --git a/sim/testsuite/arm/umull.cgs b/sim/testsuite/arm/umull.cgs new file mode 100644 index 0000000..a58541c --- /dev/null +++ b/sim/testsuite/arm/umull.cgs @@ -0,0 +1,12 @@ +# arm testcase for umull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global umull +umull: + umull00 pc,pc,pc,pc + + pass diff --git a/sim/testsuite/arm/xscale/blx.cgs b/sim/testsuite/arm/xscale/blx.cgs new file mode 100644 index 0000000..854647b --- /dev/null +++ b/sim/testsuite/arm/xscale/blx.cgs @@ -0,0 +1,31 @@ +# arm testcase for bl$cond $offset24 +# mach: all + + .include "testutils.inc" + + start + + .arm + blx thumb + + .thumb + .thumb_func +thumb: + nop + blx next + blx PASS + nop + nop + + .section text1, "ax" + .arm +next: + add r0, r1, r0 + bx lr + +FAIL: + fail +PASS: + pass + + diff --git a/sim/testsuite/arm/xscale/mia.cgs b/sim/testsuite/arm/xscale/mia.cgs new file mode 100644 index 0000000..a3f729e --- /dev/null +++ b/sim/testsuite/arm/xscale/mia.cgs @@ -0,0 +1,35 @@ +# XSCALE testcase for MIA +# mach: xscale +# as: -mcpu=xscale + + .include "testutils.inc" + + start + + .global mia +mia: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + mia acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0x354f53c4 + test_h_gr r1, 0x4e330b5e + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/arm/xscale/miaph.cgs b/sim/testsuite/arm/xscale/miaph.cgs new file mode 100644 index 0000000..53fb201 --- /dev/null +++ b/sim/testsuite/arm/xscale/miaph.cgs @@ -0,0 +1,35 @@ +# XSCALE testcase for MIAPH +# mach: xscale +# as: -mcpu=xscale + + .include "testutils.inc" + + start + + .global miaph +miaph: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaph acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0xfec3f9f4 + test_h_gr r1, 0x55667787 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/arm/xscale/miaxy.cgs b/sim/testsuite/arm/xscale/miaxy.cgs new file mode 100644 index 0000000..624564e --- /dev/null +++ b/sim/testsuite/arm/xscale/miaxy.cgs @@ -0,0 +1,89 @@ +# XSCALE testcase for MIAxy +# mach: xscale +# as: -mcpu=xscale + + .include "testutils.inc" + + start + + .global miaXY +miaXY: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Bottom Bottom Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaBB acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0x05f753c4 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Bottom Top Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaBT acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0xeeede364 + test_h_gr r1, 0x55667787 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Top Bottom Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaTB acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0x0ec85c04 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Top Top Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaTT acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0x09eed974 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/arm/xscale/mra.cgs b/sim/testsuite/arm/xscale/mra.cgs new file mode 100644 index 0000000..be4d9df --- /dev/null +++ b/sim/testsuite/arm/xscale/mra.cgs @@ -0,0 +1,30 @@ +# XScale testcase for MAR and MRA +# mach: xscale +# as: -mcpu=xscale + + .include "testutils.inc" + + start + + .global mar_mra +mar_mra: + mvi_h_gr r2,0 + mvi_h_gr r3,0 + mvi_h_gr r4,0x0000EFA0 + mvi_h_gr r5,0xA0A0A0A0 + + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mar acc0, r5, r4 + mra r2, r3, acc0 + + test_h_gr r2,0xA0A0A0A0 + test_h_gr r3,0x0000EFA0 + test_h_gr r4,0x0000EFA0 + test_h_gr r5,0xA0A0A0A0 + + pass diff --git a/sim/testsuite/arm/xscale/testutils.inc b/sim/testsuite/arm/xscale/testutils.inc new file mode 100644 index 0000000..ae49db8 --- /dev/null +++ b/sim/testsuite/arm/xscale/testutils.inc @@ -0,0 +1,118 @@ +# r0-r3 are used as tmps, consider them call clobbered by these macros. +# This uses the angel rom monitor calls. +# ??? How do we use the \@ facility of .macros ??? +# @ is the comment char! + + .macro mvi_h_gr reg, val + ldr \reg,[pc] + b . + 8 + .word \val + .endm + + .macro mvaddr_h_gr reg, addr + ldr \reg,[pc] + b . + 8 + .word \addr + .endm + + .macro start + .data +failmsg: + .asciz "fail\n" +passmsg: + .asciz "pass\n" + .text + +do_pass: + ldr r1, passmsg_addr + mov r0, #4 + swi #0x123456 + exit 0 +passmsg_addr: + .word passmsg + +do_fail: + ldr r1, failmsg_addr + mov r0, #4 + swi #0x123456 + exit 1 +failmsg_addr: + .word failmsg + + .global _start +_start: + .endm + +# *** Other macros know pass/fail are 4 bytes in size! Yuck. + + .macro pass + b do_pass + .endm + + .macro fail + b do_fail + .endm + + .macro exit rc + # ??? This works with the ARMulator but maybe not others. + #mov r0, #\rc + #swi #1 + # This seems to be portable (though it ignores rc). + mov r0,#0x18 + mvi_h_gr r1, 0x20026 + swi #0x123456 + # If that returns, punt with a sigill. + stc 0,cr0,[r0] + .endm + +# Other macros know this only clobbers r0. +# WARNING: It also clobbers the condition codes (FIXME). + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + cmp \reg, r0 + beq . + 8 + fail + .endm + + .macro mvi_h_cnvz c, n, v, z + mov r0, #0 + .if \c + orr r0, r0, #0x20000000 + .endif + .if \n + orr r0, r0, #0x80000000 + .endif + .if \v + orr r0, r0, #0x10000000 + .endif + .if \z + orr r0, r0, #0x40000000 + .endif + mrs r1, cpsr + bic r1, r1, #0xf0000000 + orr r1, r1, r0 + msr cpsr, r1 + # ??? nops needed + .endm + +# ??? Preserve condition codes? + .macro test_h_cnvz c, n, v, z + mov r0, #0 + .if \c + orr r0, r0, #0x20000000 + .endif + .if \n + orr r0, r0, #0x80000000 + .endif + .if \v + orr r0, r0, #0x10000000 + .endif + .if \z + orr r0, r0, #0x40000000 + .endif + mrs r1, cpsr + and r1, r1, #0xf0000000 + cmp r0, r1 + beq . + 8 + fail + .endm diff --git a/sim/testsuite/arm/xscale/xscale.exp b/sim/testsuite/arm/xscale/xscale.exp new file mode 100644 index 0000000..7c08f11 --- /dev/null +++ b/sim/testsuite/arm/xscale/xscale.exp @@ -0,0 +1,28 @@ +# XSCALE simulator testsuite. + +if { [istarget arm*-*-*] } { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "xscale" + + if [is_remote host] { + remote_download host $srcdir/$subdir/testutils.inc + } + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } + + if [is_remote host] { + remote_file host delete testutils.inc + } +} diff --git a/sim/testsuite/avr/ChangeLog b/sim/testsuite/avr/ChangeLog new file mode 100644 index 0000000..8c1bde2 --- /dev/null +++ b/sim/testsuite/avr/ChangeLog @@ -0,0 +1,7 @@ +2015-03-29 Mike Frysinger + + * testutils.inc (start): Change to _start and add global markings. + +2015-03-28 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/avr/allinsn.exp b/sim/testsuite/avr/allinsn.exp new file mode 100644 index 0000000..584a93d --- /dev/null +++ b/sim/testsuite/avr/allinsn.exp @@ -0,0 +1,15 @@ +# avr simulator testsuite + +if [istarget avr-*] { + # all machines + set all_machs "avr" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/avr/pass.s b/sim/testsuite/avr/pass.s new file mode 100644 index 0000000..fbcc485 --- /dev/null +++ b/sim/testsuite/avr/pass.s @@ -0,0 +1,7 @@ +# check that the sim doesn't die immediately. +# mach: avr + +.include "testutils.inc" + + start + pass diff --git a/sim/testsuite/avr/testutils.inc b/sim/testsuite/avr/testutils.inc new file mode 100644 index 0000000..baad45d --- /dev/null +++ b/sim/testsuite/avr/testutils.inc @@ -0,0 +1,42 @@ +# MACRO: outc +# Write byte to stdout + .macro outc ch + ldi r16, \ch + out 0x32, r16 + .endm + +# MACRO: exit + .macro exit nr + ldi r16, \nr + out 0x2f, r16 + .endm + +# MACRO: pass +# Write 'pass' to stdout and quit + .macro pass + outc 'p' + outc 'a' + outc 's' + outc 's' + outc '\n' + exit 0 + .endm + +# MACRO: fail +# Write 'fail' to stdout and quit + .macro fail + outc 'f' + outc 'a' + outc 'i' + outc 'l' + outc '\n' + exit 1 + .endm + +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .text +.global _start +_start: + .endm diff --git a/sim/testsuite/bfin/.gitignore b/sim/testsuite/bfin/.gitignore new file mode 100644 index 0000000..5164f03 --- /dev/null +++ b/sim/testsuite/bfin/.gitignore @@ -0,0 +1 @@ +*.[jxX] diff --git a/sim/testsuite/bfin/10272_small.s b/sim/testsuite/bfin/10272_small.s new file mode 100644 index 0000000..b260f9c --- /dev/null +++ b/sim/testsuite/bfin/10272_small.s @@ -0,0 +1,51 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym P5, tmp0; + + r6=0xFF (Z); + W[p5+0x6] = r6; + + r0.l=0x0808; + r0.h=0xffff; + + R1 = W[P5 + 0x6 ] (X); + R0 = DEPOSIT(R1, R0); + W[P5+0x6] = R0; + + R5=W[P5+0x6] (X); + DBGA(r5.l,0xffff); + + /* This instruction order fails to successfully write R0 back */ + r0.l=0x0808; + r0.h=0xffff; + + loadsym P5, tmp0; + + r6=0xFF (Z); + W[p5+0x6] = r6; + R1 = W[P5 + 0x6 ] (X); + R0 = DEPOSIT(R1, R0); + W[P5+0x6] = R0; + + R5=W[P5+0x6] (X); + DBGA(r5.l,0xffff); + + r4=1; + loadsym P5, tmp0; + r6=0xFF (Z); + W[p5+0x6] = r6; + R1 = W[P5 + 0x6 ] (X); + R0 = R1+R4; + W[P5+0x6] = R0; + + R5=W[P5+0x6] (X); + DBGA(r5.l,0x100); + + pass; + + .data +tmp0: + .space (0x10); diff --git a/sim/testsuite/bfin/10436.s b/sim/testsuite/bfin/10436.s new file mode 100644 index 0000000..9975436 --- /dev/null +++ b/sim/testsuite/bfin/10436.s @@ -0,0 +1,39 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym i0, tmp0; + + r1 = i0; + b0=i0; + r3=4; + l0=0; + m0=0; + + r5.l=0xdead; + r5.h=0xbeef; + + l0=r3; + [i0++] = r5; + l0 = 0; + r0 = i0; + + CC = R0 == R1; + if !CC JUMP _fail; + + l0=r3; + r3=[i0--]; + r0=i0; + + CC = R0 == R1; + if !CC JUMP _fail; + + pass + +_fail: + fail + + .data +tmp0: + .space (0x100); diff --git a/sim/testsuite/bfin/10622.s b/sim/testsuite/bfin/10622.s new file mode 100644 index 0000000..67076af --- /dev/null +++ b/sim/testsuite/bfin/10622.s @@ -0,0 +1,21 @@ +# mach: bfin + +.include "testutils.inc" + start + + r2.l = 0x1234; + r2.h = 0xff90; + + r4=8; + i2=r2; + m2 = 4; + a0 = 0; + r1.l = (a0 += r4.l *r4.l) (IS) || I2 += m2 || nop; + + r0 = i2; + + dbga(r0.l, 0x1238); + dbga(r0.h, 0xff90); + +_halt0: + pass; diff --git a/sim/testsuite/bfin/10742.s b/sim/testsuite/bfin/10742.s new file mode 100644 index 0000000..67cb6c9 --- /dev/null +++ b/sim/testsuite/bfin/10742.s @@ -0,0 +1,17 @@ +# mach: bfin + +.include "testutils.inc" + start + + + r5.h=0x1234; + r5.l=0x5678; + + p5 = r5; + p5.l = 0x1000; + + r0 = p5; + dbga(r0.h, 0x1234); + dbga(r0.l, 0x1000); + + pass diff --git a/sim/testsuite/bfin/10799.s b/sim/testsuite/bfin/10799.s new file mode 100644 index 0000000..76e1eb3 --- /dev/null +++ b/sim/testsuite/bfin/10799.s @@ -0,0 +1,55 @@ +# mach: bfin + +.include "testutils.inc" + start + + fp = sp; + + [--SP]=RETS; + + loadsym R1, _b; + loadsym R2, _a; + R0 = R2; + + SP += -12; + R2 = 4; + + CALL _dot; + R1 = R0; + + R0 = 30; + dbga( r1.l, 0x1e); + + + pass + +_dot: + P0 = R1; + CC = R2 <= 0; + R3 = R0; + R0 = 0; + IF CC JUMP ._P1L1 (bp); + R0 = 1; + I0 = R3; + R0 = MAX (R0,R2) || R2 = [P0++] || NOP; + P1 = R0; + R0 = 0; + R1 = [I0++]; + LSETUP (._P1L4 , ._P1L5) LC0=P1; + +._P1L4: + R1 *= R2; +._P1L5: + R0= R0 + R1 (NS) || R2 = [P0++] || R1 = [I0++]; + +._P1L1: + RTS; + +.data; +_a: + .db 0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00; + .db 0x04,0x00,0x00,0x00; + +_b: + .db 0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00; + .db 0x04,0x00,0x00,0x00; diff --git a/sim/testsuite/bfin/11080.s b/sim/testsuite/bfin/11080.s new file mode 100644 index 0000000..c5652cc --- /dev/null +++ b/sim/testsuite/bfin/11080.s @@ -0,0 +1,40 @@ +# Blackfin testcase for DISALGNEXCPT +# mach: bfin + +.include "testutils.inc" + start + + loadsym R0, foo; + R0 += 1; + I1 = R0; + + M0 = 4 (z); + + //dag0misalgn, dag1misalgn EXCAUSE value + R7 = 0x24 (z); + + // Get just the EXCAUSE field before + R5=SEQSTAT; + R5 = R5 << 26; + R5 = R5 >> 26; + + DISALGNEXCPT || R2 = [I1++M0]; // i1 = 0xff9004aa (misaligned) + + // Get just the EXCAUSE field after + R6=SEQSTAT; + R6 = R6 << 26; + R6 = R6 >> 26; + + // EXCAUSE of 0x24 == misaligned data memory access + CC = R6 == R7; + if CC jump _fail; + +_pass: + pass; + +_fail: + fail; + + .data +foo: + .space 0x10 diff --git a/sim/testsuite/bfin/7641.s b/sim/testsuite/bfin/7641.s new file mode 100644 index 0000000..864480c --- /dev/null +++ b/sim/testsuite/bfin/7641.s @@ -0,0 +1,38 @@ +# Blackfin testcase for playing with TESTSET +# mach: bfin + + .include "testutils.inc" + + start + + loadsym P0, element1 + + loadsym P1, element2 + + R0 = B [P0]; // R0 should get 00 + R1 = B [P1]; // R1 should get 02 + + TESTSET(P0); // should set CC and MSB of memory byte + R0 = CC; + TESTSET(P1); // should clear CC and not change MSB of memory + R1 = CC; + + R2 = B [P0]; // R2 should get 80 + R3 = B [P1]; // R3 should get 02 + + dbga(R0.l,0x0001); + dbga(R0.h,0x0000); + dbga(R1.l,0x0000); + dbga(R1.h,0x0000); + dbga(R2.l,0x0080); + dbga(R2.h,0x0000); + dbga(R3.l,0x0082); + dbga(R3.h,0x0000); + + pass + +.data +.align 4; +element1: .long 0x0 +element2: .long 0x2 +element3: .long 0x4 diff --git a/sim/testsuite/bfin/ChangeLog b/sim/testsuite/bfin/ChangeLog new file mode 100644 index 0000000..b8fdc04 --- /dev/null +++ b/sim/testsuite/bfin/ChangeLog @@ -0,0 +1,370 @@ +2021-01-04 Mike Frysinger + + * mdma-skel.h: Include stdlib.h. + +2015-10-11 Mike Frysinger + + PR sim/18407 + * ashift_left.s: New test. + +2013-12-07 Mike Frysinger + + * run-tests.sh: Add +x file mode. + +2013-06-23 Mike Frysinger + + * run-tests.sh (usage): Fix typo in exit. + +2013-06-23 Mike Frysinger + + * se_all32bitopcodes.S (se_all_next_insn): Skip debug insn opcodes. + +2013-06-23 Mike Frysinger + + * se_allopcodes.h (_match): Simplify register test to one less insn. + Omit the SSYNC insn when compiling for the sim. + +2013-06-23 Mike Frysinger + + * testutils.inc: Trim trailing whitespace. + +2013-06-17 Mike Frysinger + + * run-tests.sh: Add support for running in parallel. + +2013-06-17 Mike Frysinger + + * se_allopcodes.h: Add debugging related comments. + +2013-06-17 Mike Frysinger + + * se_allopcodes.h: Do not clear RETN/RETE/RETI. + +2012-04-09 Robin Getz + + * random_0017.S, random_0018.S, random_0025.S: New ASTAT shift tests. + +2012-04-09 Robin Getz + + * random_0036.S, random_0037.S: New astat tests. + +2012-04-09 Mike Frysinger + + * se_all64bitg1opcodes.S: Delete xfail line. + * se_all64bitg2opcodes.S: Likewise. + +2012-04-08 Mike Frysinger + + * se_all16bitopcodes.S (SE_ALL_BITS): Define to 16. + (SE_ALL_NEW_INSN_STUB): Define. + (se_all_load_table): Delete. + (se_all_new_insn_log): Likewise. + * se_all32bitopcodes.S: Add more details on slowness. + (SE_ALL_BITS): Define to 13. + (se_all_load_table): Delete. + (se_all_new_insn_stub, se_all_new_insn_log): Likewise. + * se_all64bitg0opcodes.S: Add more details on slowness. + (se_all_new_insn_stub): Delete. + * se_all64bitg1opcodes.S: See mach to bfin. + (se_all_new_insn_stub): Delete. + * se_all64bitg2opcodes.S: See mach to bfin. + (se_all_new_insn_stub): Delete. + * se_allopcodes.h (LOAD_PFX): Define based on SE_ALL_BITS. + (se_all_new_16bit_insn_log, se_all_new_32bit_insn_log): Unify + into new se_all_new_insn_log helper. + (se_all_load_table): New helper. + (se_all_new_insn_stub): Likewise. + +2012-03-25 Mike Frysinger + + * c_dsp32mac_dr_a1a0.s: Change 0x12efbc5569 to 0xefbc5569. + * c_dsp32mac_dr_a1a0_iutsh.s: Change 0x12efbc556 to 0x2efbc556. + * c_dsp32mac_dr_a1a0_m.s: Change 0x12efbc5569 to 0xefbc5569. + * c_dsp32shift_vmaxvmax.s: Change 0xa11002001 to 0x11002001. + * c_dsp32shiftim_af_s.s: Change 0x3a1230001 to 0xa1230001. + + * fact.s: Comment out test with too large a number (6227020800). + + * allinsn.exp: If preprocessing usp.S fails, set has_cpp to 0, + else set it to 1. If compiling argc.c fails, set has_cc to 0, + else set it to 1. When processing each src file, if has_ccp is + 0 and the file ends in .S, skip it; if it has_cc is 0 and the + file ends in .c, skip it. + +2012-03-19 Mike Frysinger + + * se_all64bitg0opcodes.S, se_all64bitg1opcodes.S, + se_all64bitg2opcodes.S: New exhaustive parallel insn tests. + +2012-03-19 Mike Frysinger + + * se_allopcodes.h: New framework for testing opcode regions. + * se_all16bitopcodes.S: Convert over to se_allopcodes.h. + * se_all32bitopcodes.S: Likewise. + +2012-03-19 Stuart Henderson + + * c_dsp32shiftim_amix.s: Check edge cases in shift behavior. + +2012-03-19 Robin Getz + + * random_0014.S, random_0015.S, random_0016.S: New tests for shifts. + +2012-03-18 Mike Frysinger + + * se_all16bitopcodes.S: Merge code from se_all32bitopcodes.S. + +2011-09-28 Mike Frysinger + + * vit_max2.s: New tests for parallel VIT_MAX insns. + +2011-06-18 Robin Getz + + * random_0019.S, random_0020.S, random_0021.S, random_0022.S, + random_0023.S, random_0024.S, random_0026.S, random_0027.S, + random_0028.S, random_0029.S, random_0030.S, random_0032.S, + random_0035.S: New tests for dsp insns. + +2011-06-04 Mike Frysinger + + * .gitignore, 10272_small.s, 10436.s, 10622.s, 10742.s, 10799.s, + 11080.s, 7641.s, a0.s, a0shift.S, a10.s, a11.S, a12.s, a1.s, a20.S, + a21.s, a22.s, a23.s, a24.s, a25.s, a26.s, a2.s, a30.s, a3.s, a4.s, + a5.s, a6.s, a7.s, a8.s, a9.s, abs-2.S, abs-3.S, abs-4.S, abs_acc.s, + abs.S, acc-rot.s, acp5_19.s, acp5_4.s, add_imm7.s, add_shift.S, + add_sub_acc.s, addsub_flags.S, algnbug1.s, algnbug2.s, allinsn.exp, + argc.c, ashift_flags.s, ashift.s, b0.S, b1.s, b2.S, brcc.s, brevadd.s, + byteop16m.s, byteop16p.s, byteop1p.s, byteop2p.s, byteop3p.s, + byteunpack.s, c_alu2op_arith_r_sft.s, c_alu2op_conv_b.s, + c_alu2op_conv_h.s, c_alu2op_conv_mix.s, c_alu2op_conv_neg.s, + c_alu2op_conv_toggle.s, c_alu2op_conv_xb.s, c_alu2op_conv_xh.s, + c_alu2op_divq.s, c_alu2op_divs.s, c_alu2op_log_l_sft.s, + c_alu2op_log_r_sft.s, c_alu2op_shadd_1.s, c_alu2op_shadd_2.s, + c_brcc_bp1.s, c_brcc_bp2.s, c_brcc_bp3.s, c_brcc_bp4.s, + c_brcc_brf_bp.s, c_brcc_brf_brt_bp.s, c_brcc_brf_brt_nbp.s, + c_brcc_brf_fbkwd.s, c_brcc_brf_nbp.s, c_brcc_brt_bp.s, + c_brcc_brt_nbp.s, c_brcc_kills_dhits.s, c_brcc_kills_dmiss.s, + c_br_preg_killed_ac.s, c_br_preg_killed_ex1.s, c_br_preg_stall_ac.s, + c_br_preg_stall_ex1.s, cc0.s, cc1.s, cc5.S, c_cactrl_iflush_pr_pp.s, + c_cactrl_iflush_pr.s, c_calla_ljump.s, c_calla_subr.s, cc-alu.S, + cc-astat-bits.s, c_cc2dreg.s, c_cc2stat_cc_ac.S, c_cc2stat_cc_an.s, + c_cc2stat_cc_aq.s, c_cc2stat_cc_av0.S, c_cc2stat_cc_av1.S, + c_cc2stat_cc_az.s, c_ccflag_a0a1.S, c_cc_flag_ccmv_depend.S, + c_ccflag_dr_dr.s, c_ccflag_dr_dr_uu.s, c_cc_flagdreg_mvbrsft.s, + c_cc_flagdreg_mvbrsft_s1.s, c_cc_flagdreg_mvbrsft_sn.s, + c_ccflag_dr_imm3.s, c_ccflag_dr_imm3_uu.s, c_ccflag_pr_imm3.s, + c_ccflag_pr_imm3_uu.s, c_ccflag_pr_pr.s, c_ccflag_pr_pr_uu.s, + c_ccmv_cc_dr_dr.s, c_ccmv_cc_dr_pr.s, c_ccmv_cc_pr_pr.s, + c_ccmv_ncc_dr_dr.s, c_ccmv_ncc_dr_pr.s, c_ccmv_ncc_pr_pr.s, + c_cc_regmvlogi_mvbrsft.s, c_cc_regmvlogi_mvbrsft_s1.s, + c_cc_regmvlogi_mvbrsft_sn.S, c_comp3op_dr_and_dr.s, + c_comp3op_dr_minus_dr.s, c_comp3op_dr_mix.s, c_comp3op_dr_or_dr.s, + c_comp3op_dr_plus_dr.s, c_comp3op_dr_xor_dr.s, + c_comp3op_pr_plus_pr_sh1.s, c_comp3op_pr_plus_pr_sh2.s, + c_compi2opd_dr_add_i7_n.s, c_compi2opd_dr_add_i7_p.s, + c_compi2opd_dr_eq_i7_n.s, c_compi2opd_dr_eq_i7_p.s, + c_compi2opd_flags_2.S, c_compi2opd_flags.S, c_compi2opp_pr_add_i7_n.s, + c_compi2opp_pr_add_i7_p.s, c_compi2opp_pr_eq_i7_n.s, + c_compi2opp_pr_eq_i7_p.s, c_dagmodik_lnz_imgebl.s, + c_dagmodik_lnz_imltbl.s, c_dagmodik_lz_inc_dec.s, + c_dagmodim_lnz_imgebl.s, c_dagmodim_lnz_imltbl.s, + c_dagmodim_lz_inc_dec.s, c_dsp32alu_a0a1s.s, c_dsp32alu_a0_pm_a1.s, + c_dsp32alu_aa_absabs.s, c_dsp32alu_a_abs_a.s, c_dsp32alu_aa_negneg.s, + c_dsp32alu_absabs.s, c_dsp32alu_abs.s, c_dsp32alu_alhwx.s, + c_dsp32alu_a_neg_a.s, c_dsp32alu_awx.s, c_dsp32alu_byteop1ew.s, + c_dsp32alu_byteop2.s, c_dsp32alu_byteop3.s, c_dsp32alu_bytepack.s, + c_dsp32alu_byteunpack.s, c_dsp32alu_disalnexcpt.s, c_dsp32alu_maxmax.s, + c_dsp32alu_max.s, c_dsp32alu_minmin.s, c_dsp32alu_min.s, + c_dsp32alu_mix.s, c_dsp32alu_rh_m.s, c_dsp32alu_rh_p.s, + c_dsp32alu_rh_rnd12_m.s, c_dsp32alu_rh_rnd12_p.s, + c_dsp32alu_rh_rnd20_m.s, c_dsp32alu_rh_rnd20_p.s, + c_dsp32alu_r_lh_a0pa1.s, c_dsp32alu_rlh_rnd.s, c_dsp32alu_rl_m.s, + c_dsp32alu_rl_p.s, c_dsp32alu_rl_rnd12_m.s, c_dsp32alu_rl_rnd12_p.s, + c_dsp32alu_rl_rnd20_m.s, c_dsp32alu_rl_rnd20_p.s, c_dsp32alu_rmm.s, + c_dsp32alu_rmp.s, c_dsp32alu_rm.s, c_dsp32alu_r_negneg.s, + c_dsp32alu_rpm.s, c_dsp32alu_rpp.s, c_dsp32alu_rp.s, + c_dsp32alu_rr_lph_a1a0.s, c_dsp32alu_rrpm_aa.s, c_dsp32alu_rrpmmp.s, + c_dsp32alu_rrpmmp_sft.s, c_dsp32alu_rrpmmp_sft_x.s, c_dsp32alu_rrpm.s, + c_dsp32alu_rrppmm.s, c_dsp32alu_rrppmm_sft.s, + c_dsp32alu_rrppmm_sft_x.s, c_dsp32alu_saa.s, c_dsp32alu_sat_aa.S, + c_dsp32alu_search.s, c_dsp32alu_sgn.s, c_dsp32mac_a1a0_iuw32.s, + c_dsp32mac_a1a0_m.s, c_dsp32mac_a1a0.s, c_dsp32mac_dr_a0_ih.s, + c_dsp32mac_dr_a0_i.s, c_dsp32mac_dr_a0_is.s, c_dsp32mac_dr_a0_iu.s, + c_dsp32mac_dr_a0_m.s, c_dsp32mac_dr_a0.s, c_dsp32mac_dr_a0_s.s, + c_dsp32mac_dr_a0_t.s, c_dsp32mac_dr_a0_tu.s, c_dsp32mac_dr_a0_u.s, + c_dsp32mac_dr_a1a0_iutsh.s, c_dsp32mac_dr_a1a0_m.s, + c_dsp32mac_dr_a1a0.s, c_dsp32mac_dr_a1_ih.s, c_dsp32mac_dr_a1_i.s, + c_dsp32mac_dr_a1_is.s, c_dsp32mac_dr_a1_iu.s, c_dsp32mac_dr_a1_m.s, + c_dsp32mac_dr_a1.s, c_dsp32mac_dr_a1_s.s, c_dsp32mac_dr_a1_t.s, + c_dsp32mac_dr_a1_tu.s, c_dsp32mac_dr_a1_u.s, c_dsp32mac_mix.s, + c_dsp32mac_pair_a0_i.s, c_dsp32mac_pair_a0_is.s, + c_dsp32mac_pair_a0_m.s, c_dsp32mac_pair_a0.s, c_dsp32mac_pair_a0_s.s, + c_dsp32mac_pair_a0_u.s, c_dsp32mac_pair_a1a0_i.s, + c_dsp32mac_pair_a1a0_is.s, c_dsp32mac_pair_a1a0_m.s, + c_dsp32mac_pair_a1a0.s, c_dsp32mac_pair_a1a0_s.s, + c_dsp32mac_pair_a1a0_u.s, c_dsp32mac_pair_a1_i.s, + c_dsp32mac_pair_a1_is.s, c_dsp32mac_pair_a1_m.s, c_dsp32mac_pair_a1.s, + c_dsp32mac_pair_a1_s.s, c_dsp32mac_pair_a1_u.s, c_dsp32mac_pair_mix.s, + c_dsp32mult_dr_ih.s, c_dsp32mult_dr_i.s, c_dsp32mult_dr_is.s, + c_dsp32mult_dr_iu.s, c_dsp32mult_dr_m_i.s, c_dsp32mult_dr_m_iutsh.s, + c_dsp32mult_dr_mix.s, c_dsp32mult_dr_m.s, c_dsp32mult_dr_m_s.s, + c_dsp32mult_dr_m_t.s, c_dsp32mult_dr_m_u.s, c_dsp32mult_dr.s, + c_dsp32mult_dr_s.s, c_dsp32mult_dr_t.s, c_dsp32mult_dr_tu.s, + c_dsp32mult_dr_u.s, c_dsp32mult_pair_i.s, c_dsp32mult_pair_is.s, + c_dsp32mult_pair_m_i.s, c_dsp32mult_pair_m_is.s, c_dsp32mult_pair_m.s, + c_dsp32mult_pair_m_s.s, c_dsp32mult_pair_m_u.s, c_dsp32mult_pair.s, + c_dsp32mult_pair_s.s, c_dsp32mult_pair_u.s, c_dsp32shift_a0alr.s, + c_dsp32shift_af.s, c_dsp32shift_af_s.s, c_dsp32shift_ahalf_ln.s, + c_dsp32shift_ahalf_ln_s.s, c_dsp32shift_ahalf_lp.s, + c_dsp32shift_ahalf_lp_s.s, c_dsp32shift_ahalf_rn.s, + c_dsp32shift_ahalf_rn_s.s, c_dsp32shift_ahalf_rp.s, + c_dsp32shift_ahalf_rp_s.s, c_dsp32shift_ahh.s, c_dsp32shift_ahh_s.s, + c_dsp32shift_align16.s, c_dsp32shift_align24.s, c_dsp32shift_align8.s, + c_dsp32shift_amix.s, c_dsp32shift_bitmux.s, c_dsp32shift_bxor.s, + c_dsp32shift_expadj_h.s, c_dsp32shift_expadj_l.s, + c_dsp32shift_expadj_r.s, c_dsp32shift_expexp_r.s, c_dsp32shift_fdepx.s, + c_dsp32shift_fextx.s, c_dsp32shiftim_a0alr.s, c_dsp32shiftim_af.s, + c_dsp32shiftim_af_s.s, c_dsp32shiftim_ahalf_ln.s, + c_dsp32shiftim_ahalf_ln_s.s, c_dsp32shiftim_ahalf_lp.s, + c_dsp32shiftim_ahalf_lp_s.s, c_dsp32shiftim_ahalf_rn.s, + c_dsp32shiftim_ahalf_rn_s.s, c_dsp32shiftim_ahalf_rp.s, + c_dsp32shiftim_ahalf_rp_s.s, c_dsp32shiftim_ahh.s, + c_dsp32shiftim_ahh_s.s, c_dsp32shiftim_amix.s, c_dsp32shiftim_lf.s, + c_dsp32shiftim_lhalf_ln.s, c_dsp32shiftim_lhalf_lp.s, + c_dsp32shiftim_lhalf_rn.s, c_dsp32shiftim_lhalf_rp.s, + c_dsp32shiftim_lhh.s, c_dsp32shiftim_lmix.s, c_dsp32shiftim_rot.s, + c_dsp32shift_lf.s, c_dsp32shift_lhalf_ln.s, c_dsp32shift_lhalf_lp.s, + c_dsp32shift_lhalf_rn.s, c_dsp32shift_lhalf_rp.s, c_dsp32shift_lhh.s, + c_dsp32shift_lmix.s, c_dsp32shift_ones.s, c_dsp32shift_pack.s, + c_dsp32shift_rot_mix.s, c_dsp32shift_rot.s, c_dsp32shift_signbits_rh.s, + c_dsp32shift_signbits_rl.s, c_dsp32shift_signbits_r.s, + c_dsp32shift_vmax.s, c_dsp32shift_vmaxvmax.s, c_dspldst_ld_drhi_ipp.s, + c_dspldst_ld_drhi_i.s, c_dspldst_ld_dr_ippm.s, c_dspldst_ld_dr_ipp.s, + c_dspldst_ld_dr_i.s, c_dspldst_ld_drlo_ipp.s, c_dspldst_ld_drlo_i.s, + c_dspldst_st_drhi_ipp.s, c_dspldst_st_drhi_i.s, c_dspldst_st_dr_ippm.s, + c_dspldst_st_dr_ipp.s, c_dspldst_st_dr_i.s, c_dspldst_st_drlo_ipp.s, + c_dspldst_st_drlo_i.s, cec-exact-exception.S, cec-ifetch.S, + cec-multi-pending.S, cec-non-operating-env.s, cec-no-snen-reti.S, + cec-raise-reti.S, cec-snen-reti.S, cec-syscfg-ssstep.S, + cec-system-call.S, c_except_illopcode.S, c_except_sys_sstep.S, + c_except_user_mode.S, c_interr_disable_enable.S, c_interr_disable.S, + c_interr_excpt.S, c_interr_loopsetup_stld.S, c_interr_nested.S, + c_interr_nmi.S, c_interr_pending_2.S, c_interr_pending.S, + c_interr_timer_reload.S, c_interr_timer.S, c_interr_timer_tcount.S, + c_interr_timer_tscale.S, cir1.s, cir.s, c_ldimmhalf_dreg.s, + c_ldimmhalf_drhi.s, c_ldimmhalf_drlo.s, c_ldimmhalf_h_dr.s, + c_ldimmhalf_h_ibml.s, c_ldimmhalf_h_pr.s, c_ldimmhalf_l_dr.s, + c_ldimmhalf_l_ibml.s, c_ldimmhalf_l_pr.s, c_ldimmhalf_lz_dr.s, + c_ldimmhalf_lzhi_dr.s, c_ldimmhalf_lzhi_ibml.s, c_ldimmhalf_lzhi_pr.s, + c_ldimmhalf_lz_ibml.s, c_ldimmhalf_lz_pr.s, c_ldimmhalf_pibml.s, + c_ldstidxl_ld_dr_b.s, c_ldstidxl_ld_dreg.s, c_ldstidxl_ld_dr_h.s, + c_ldstidxl_ld_dr_xb.s, c_ldstidxl_ld_dr_xh.s, c_ldstidxl_ld_preg.s, + c_ldstidxl_st_dr_b.s, c_ldstidxl_st_dreg.s, c_ldstidxl_st_dr_h.s, + c_ldstidxl_st_preg.s, c_ldstiifp_ld_dreg.s, c_ldstiifp_ld_preg.s, + c_ldstiifp_st_dreg.s, c_ldstiifp_st_preg.s, c_ldstii_ld_dreg.s, + c_ldstii_ld_dr_h.s, c_ldstii_ld_dr_xh.s, c_ldstii_ld_preg.s, + c_ldstii_st_dreg.s, c_ldstii_st_dr_h.s, c_ldstii_st_preg.s, + c_ldst_ld_d_p_b.s, c_ldst_ld_d_p_h.s, c_ldst_ld_d_p_mm_b.s, + c_ldst_ld_d_p_mm_h.s, c_ldst_ld_d_p_mm.s, c_ldst_ld_d_p_mm_xb.s, + c_ldst_ld_d_p_mm_xh.s, c_ldst_ld_d_p_pp_b.s, c_ldst_ld_d_p_pp_h.s, + c_ldst_ld_d_p_ppmm_hbx.s, c_ldst_ld_d_p_pp.s, c_ldst_ld_d_p_pp_xb.s, + c_ldst_ld_d_p_pp_xh.s, c_ldst_ld_d_p.s, c_ldst_ld_d_p_xb.s, + c_ldst_ld_d_p_xh.s, c_ldst_ld_p_p_mm.s, c_ldst_ld_p_p_pp.s, + c_ldst_ld_p_p.s, c_ldstpmod_ld_dreg.s, c_ldstpmod_ld_dr_hi.s, + c_ldstpmod_ld_dr_lo.s, c_ldstpmod_ld_h_xh.s, c_ldstpmod_ld_lohi.s, + c_ldstpmod_st_dreg.s, c_ldstpmod_st_dr_hi.s, c_ldstpmod_st_dr_lo.s, + c_ldstpmod_st_lohi.s, c_ldst_st_p_d_b.s, c_ldst_st_p_d_h.s, + c_ldst_st_p_d_mm_b.s, c_ldst_st_p_d_mm_h.s, c_ldst_st_p_d_mm.s, + c_ldst_st_p_d_pp_b.s, c_ldst_st_p_d_pp_h.s, c_ldst_st_p_d_pp.s, + c_ldst_st_p_d.s, c_ldst_st_p_p_mm.s, c_ldst_st_p_p_pp.s, + c_ldst_st_p_p.s, c_linkage.s, cli-sti.s, c_logi2op_alshft_mix.s, + c_logi2op_arith_shft.s, c_logi2op_bitclr.s, c_logi2op_bitset.s, + c_logi2op_bittgl.s, c_logi2op_bittst.s, c_logi2op_log_l_shft_astat.S, + c_logi2op_log_l_shft.s, c_logi2op_log_r_shft_astat.S, + c_logi2op_log_r_shft.s, c_logi2op_nbittst.s, c_loopsetup_nested_bot.s, + c_loopsetup_nested_prelc.s, c_loopsetup_nested.s, + c_loopsetup_nested_top.s, c_loopsetup_overlap.s, + c_loopsetup_preg_div2_lc0.s, c_loopsetup_preg_div2_lc1.s, + c_loopsetup_preg_lc0.s, c_loopsetup_preg_lc1.s, + c_loopsetup_preg_stld.s, c_loopsetup_prelc.s, c_loopsetup_topbotcntr.s, + c_mmr_interr_ctl.s, c_mmr_loop.S, c_mmr_loop_user_except.S, + c_mmr_ppop_illegal_adr.S, c_mmr_ppopm_illegal_adr.S, c_mmr_timer.S, + c_mode_supervisor.S, c_mode_user.S, c_mode_user_superivsor.S, cmpacc.s, + cmpdreg.S, c_multi_issue_dsp_ld_ld.s, c_multi_issue_dsp_ldst_1.s, + c_multi_issue_dsp_ldst_2.s, compare.s, conv_enc_gen.s, + c_progctrl_call_pcpr.s, c_progctrl_call_pr.s, + c_progctrl_clisti_interr.S, c_progctrl_csync_mmr.S, + c_progctrl_except_rtx.S, c_progctrl_excpt.S, c_progctrl_jump_pcpr.s, + c_progctrl_jump_pr.s, c_progctrl_nop.s, c_progctrl_raise_rt_i_n.S, + c_progctrl_rts.s, c_ptr2op_pr_neg_pr.s, c_ptr2op_pr_sft_2_1.s, + c_ptr2op_pr_shadd_1_2.s, c_pushpopmultiple_dp_pair.s, + c_pushpopmultiple_dp.s, c_pushpopmultiple_dreg.s, + c_pushpopmultiple_preg.s, c_regmv_acc_acc.s, c_regmv_dag_lz_dep.s, + c_regmv_dr_acc_acc.s, c_regmv_dr_dep_nostall.s, c_regmv_dr_dr.s, + c_regmv_dr_imlb.s, c_regmv_dr_pr.s, c_regmv_imlb_dep_nostall.s, + c_regmv_imlb_dep_stall.s, c_regmv_imlb_dr.s, c_regmv_imlb_imlb.s, + c_regmv_imlb_pr.s, c_regmv_pr_dep_nostall.s, c_regmv_pr_dep_stall.s, + c_regmv_pr_dr.s, c_regmv_pr_imlb.s, c_regmv_pr_pr.s, + c_seq_ac_raise_mv_ppop.S, c_seq_ac_raise_mv.S, + c_seq_ac_regmv_pushpop.S, c_seq_dec_raise_pushpop.S, + c_seq_ex1_brcc_mv_pop.S, c_seq_ex1_call_mv_pop.S, c_seq_ex1_j_mv_pop.S, + c_seq_ex1_raise_brcc_mv_pop.S, c_seq_ex1_raise_call_mv_pop.S, + c_seq_ex1_raise_j_mv_pop.S, c_seq_ex2_brcc_mp_mv_pop.S, + c_seq_ex2_mmrj_mvpop.S, c_seq_ex2_mmr_mvpop.S, + c_seq_ex2_raise_mmrj_mvpop.S, c_seq_ex2_raise_mmr_mvpop.S, + c_seq_ex3_ls_brcc_mvp.S, c_seq_ex3_ls_mmrj_mvp.S, + c_seq_ex3_ls_mmr_mvp.S, c_seq_ex3_raise_ls_mmrj_mvp.S, + c_seq_wb_cs_lsmmrj_mvp.S, c_seq_wb_raisecs_lsmmrj_mvp.S, + c_seq_wb_rti_lsmmrj_mvp.S, c_seq_wb_rtn_lsmmrj_mvp.S, + c_seq_wb_rtx_lsmmrj_mvp.S, c_ujump.s, cycles.s, d0.s, d1.s, d2.s, + dbg_brprd_ntkn_src_kill.S, dbg_brtkn_nprd_src_kill.S, + dbg_jmp_src_kill.S, dbg_tr_basic.S, dbg_tr_simplejp.S, dbg_tr_tbuf0.S, + dbg_tr_umode.S, disalnexcpt_implicit.S, div0.s, divq.s, dotproduct2.s, + dotproduct.s, double_prec_mult.s, dsp_a4.s, dsp_a7.s, dsp_a8.s, + dsp_d0.s, dsp_d1.s, dsp_neg.S, dsp_s1.s, e0.s, edn_snafu.s, + eu_dsp32mac_s.s, events.s, f221.s, fact.s, fir.s, fsm.s, greg2.s, + hwloop-bits.S, hwloop-branch-in.s, hwloop-branch-out.s, + hwloop-lt-bits.s, hwloop-nested.s, i0.s, iir.s, issue103.s, issue109.s, + issue112.s, issue113.s, issue117.s, issue118.s, issue119.s, issue121.s, + issue123.s, issue124.s, issue125.s, issue126.s, issue127.s, issue129.s, + issue139.S, issue140.S, issue142.s, issue144.s, issue146.S, issue175.s, + issue205.s, issue257.s, issue272.S, issue83.s, issue89.s, l0.s, + l0shift.s, l2_loop.s, link-2.s, link.s, lmu_cplb_multiple0.S, + lmu_cplb_multiple1.S, lmu_excpt_align.S, lmu_excpt_default.S, + lmu_excpt_illaddr.S, lmu_excpt_prot0.S, lmu_excpt_prot1.S, load.s, + logic.s, loop_snafu.s, loop_strncpy.s, lp0.s, lp1.s, lsetup.s, + m0boundary.s, m10.s, m11.s, m12.s, m13.s, m14.s, m15.s, m16.s, m17.s, + m1.S, m2.s, m3.s, m4.s, m5.s, m6.s, m7.s, m8.s, m9.s, mac2halfreg.S, + Makefile, math.s, max_min_flags.s, mc_s2.s, mdma-32bit-1d.c, + mdma-32bit-1d-neg-count.c, mdma-8bit-1d.c, mdma-8bit-1d-neg-count.c, + mdma-skel.h, mem3.s, mmr-exception.s, move.s, msa_acp_5_10.s, + msa_acp_5.10.S, msa_acp_5.12_1.S, msa_acp_5.12_2.S, mult.s, neg-2.S, + neg-3.S, neg.S, nshift.s, PN_generator.s, pr.s, push-pop-multiple.s, + pushpopreg_1.s, push-pop.s, quadaddsub.s, random_0001.s, random_0002.S, + random_0003.S, random_0004.S, random_0005.S, random_0006.S, + random_0007.S, random_0008.S, random_0009.S, random_0010.S, + random_0011.S, random_0012.S, random_0013.S, random_0031.S, + random_0033.S, random_0034.S, run-tests.sh, s0.s, s10.s, s11.s, s12.s, + s13.s, s14.s, s15.s, s16.s, s17.s, s18.s, s19.s, s1.s, s20.s, s21.s, + s2.s, s30.s, s3.s, s4.s, s5.s, s6.s, s7.s, s8.s, s9.s, saatest.s, + se_all16bitopcodes.S, se_all32bitopcodes.lds, se_all32bitopcodes.S, + se_brtarget_stall.S, se_bug_ui2.S, se_bug_ui3.S, se_bug_ui.S, + se_cc2stat_haz.S, se_cc_kill.S, se_cof.S, se_event_quad.S, + se_excpt_dagprotviol.S, se_excpt_ifprotviol.S, se_excpt_ssstep.S, + se_illegalcombination.S, se_kills2.S, se_kill_wbbr.S, + se_loop_disable.S, se_loop_kill_01.S, se_loop_kill_dcr_01.S, + se_loop_kill_dcr.S, se_loop_kill.S, se_loop_lr.S, + se_loop_mv2lb_stall.S, se_loop_mv2lc.S, se_loop_mv2lc_stall.S, + se_loop_mv2lt_stall.S, se_loop_nest_ppm_1.S, se_loop_nest_ppm_2.S, + se_loop_nest_ppm.S, se_loop_ppm_1.S, se_loop_ppm_int.S, se_loop_ppm.S, + se_lsetup_kill.S, se_misaligned_fetch.S, se_more_ret_haz.S, se_mv2lp.S, + se_oneins_zoff.S, se_popkill.S, seqstat.s, se_regmv_usp_sysreg.S, + se_rets_hazard.s, se_rts_rti.S, se_ssstep_dagprotviol.S, se_ssync.S, + se_stall_if2.S, se_undefinedinstruction1.S, se_undefinedinstruction2.S, + se_undefinedinstruction3.S, se_undefinedinstruction4.S, + se_usermode_protviol.S, sign.s, simple0.s, sri.s, stk2.s, stk3.s, + stk4.s, stk5.s, stk6.s, stk.s, syscfg.s, tar10622.s, test-dma.h, + test.h, testset2.s, testset.s, testutils.inc, unlink.S, up0.s, usp.S, + vec-abs-2.S, vec-abs-3.S, vec-abs.S, vecadd.s, vec-neg-2.S, + vec-neg-3.S, vec-neg.S, viterbi2.s, vit_max.s, wtf.s, x1.s, zcall.s, + zeroflagrnd.s: New files. diff --git a/sim/testsuite/bfin/PN_generator.s b/sim/testsuite/bfin/PN_generator.s new file mode 100644 index 0000000..7d92b85 --- /dev/null +++ b/sim/testsuite/bfin/PN_generator.s @@ -0,0 +1,78 @@ +# mach: bfin + +// GENERIC PN SEQUENCE GENERATOR +// Linear Feedback Shift Register +// ------------------------------- +// This solution implements an LFSR by applying an XOR reduction +// function to the 40 bit accumulator, XORing the contents of the +// CC bit, shifting by one the accumulator, and inserting the +// resulting bit on the open bit slot. +// CC --> ----- XOR-------------------------- +// | | | | | | +// | | | | | | +// +------------------------------+ v +// | b0 b1 b2 b3 b38 b39 | in <-- by one +// +------------------------------+ +// after: +// +------------------------------+ +// | b1 b2 b3 b38 b39 in | +// +------------------------------+ +// The program shown here is a PN sequence generator, and hence +// does not take any input other than the initial state. However, +// in order to accept an input, one simply needs to rotate the +// input sequence via CC prior to applying the XOR reduction. + +.include "testutils.inc" + start + + loadsym P1, output; + init_r_regs 0; + ASTAT = R0; + +// load Polynomial into A1 + A1 = A0 = 0; + R0.L = 0x1cd4; + R0.H = 0xab18; + A1.w = R0; + R0.L = 0x008d; + A1.x = R0.L; + +// load InitState into A0 + R0.L = 0x0001; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + + P4 = 4; + LSETUP ( l$0 , l$0end ) LC0 = P4; + l$0: // **** START l-LOOP ***** + + P4 = 32; + LSETUP ( m$1 , m$1 ) LC1 = P4; // **** START m-LOOP ***** + m$1: + A0 = BXORSHIFT( A0 , A1, CC ); + +// store 16 bits of outdata RL1 + R1 = A0.w; + l$0end: + [ P1 ++ ] = R1; + +// Check results + loadsym I2, output; + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5adf ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x2fc9 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0xbd91 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5520 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x80d5 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x7fef ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x34d1 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x915c ); + pass + + .data; +output: + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/bfin/a0.s b/sim/testsuite/bfin/a0.s new file mode 100644 index 0000000..3bc78d6 --- /dev/null +++ b/sim/testsuite/bfin/a0.s @@ -0,0 +1,17 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 1; + R0 <<= 1; + DBGA ( R0.L , 2 ); + R0 <<= 1; + DBGA ( R0.L , 4 ); + R0 <<= 3; + DBGA ( R0.L , 32 ); + R0 += 5; + DBGA ( R0.L , 37 ); + R0 += -7; + DBGA ( R0.L , 30 ); + pass diff --git a/sim/testsuite/bfin/a0shift.S b/sim/testsuite/bfin/a0shift.S new file mode 100644 index 0000000..18bfcbd --- /dev/null +++ b/sim/testsuite/bfin/a0shift.S @@ -0,0 +1,169 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + +// 0xfffffe371c + r0 = 0; + r1 = 0; + r2 = 0; + r3 = 0; + r4 = 0; + r5 = 0; + r6 = 0; + r7 = 0; + a1 = a0 =0; + astat = R0; + + R6.L = 0x8000; + R5.H = 0x8000; + +// load acc with values; + R0.L = 0xc062; + R0.H = 0xffee; + A0.w = R0; + R0.L = 0xc52c; + A0.x = R0; + R0.L = 0x8d10; + R0.H = 0x34c; + A1.w = R0; + R0.L = 0xe10c; + A1.x = R0; +// load regs with values; + R0.L = 0xe844; + R0.H = 0x4aba; + R1.L = 0xa294; + R1.H = 0x52ea; + R2.L = 0xafda; + R2.H = 0x5c32; +// end load regs and acc; + R0.H = (A1 = R5.L * R6.H), R0.L = (A0 += R5.L * R6.H) (FU); +P0 = ASTAT; +CHECKREG P0, (_VS|_V|_V_COPY); + + CHECKREG R0, 0xffff; +R0 = A1.w +CHECKREG R0, 0; +R0 = A1.x +CHECKREG R0, 0; +R0 = A0.w +CHECKREG R0, 0xffeec062; +R0 = A0.x +CHECKREG R0, 0x2c; + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY); + R4 = R6 +|- R5 , R3 = R6 -|+ R5; + CHECKREG R3, 0x80008000; + CHECKREG R4, 0x80008000; + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN); + A1 = R7.L * R2.L (M), A0 -= R7.L * R2.H (IS); + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN); + R7.H = R1.H * R3.L (TFU); + CHECKREG R7, 0x29750000; + P0 = ASTAT; + CHECKREG P0, (_VS|_AN); + R7.H = ( A1 -= R2.L * R5.H ), A0 = R2.L * R5.H; + CHECKREG R7, 0xafda0000; +R0 = A1.w +CHECKREG R0, 0xafda0000; +R0 = A1.x +CHECKREG R0, 0xffffffff; +R0 = A0.w +CHECKREG R0, 0x50260000; +R0 = A0.x +CHECKREG R0, 0x0; + P0 = ASTAT; + CHECKREG P0, (_VS|_AN); + R3 = R7.L * R6.H, R2 = R7.L * R6.H (IS); + CHECKREG R3, 0; + CHECKREG R2, 0; + P0 = ASTAT; + CHECKREG P0, (_VS|_AN); + R1.H = (A1 += R7.L * R4.H) (M), R1.L = (A0 = R7.H * R4.H) (FU); + CHECKREG R1, 0xafda57ed; + P0 = ASTAT; +R0 = A1.w +CHECKREG R0, 0xafda0000; +R0 = A1.x +CHECKREG R0, 0xffffffff; +R0 = A0.w +CHECKREG R0, 0x57ed0000; +R0 = A0.x +CHECKREG R0, 0x0; + CHECKREG P0, (_VS|_AN); + R3 = R6.H * R5.L (FU); + CHECKREG R3, 0; + P0 = ASTAT; + CHECKREG P0, (_VS|_AN); + R5.H = ( A1 += R3.L * R1.L ) (M), A0 -= R3.H * R1.H (ISS2); + CHECKREG R5, 0x80000000; +R0 = A1.w +CHECKREG R0, 0xafda0000; +R0 = A1.x +CHECKREG R0, 0xffffffff; +R0 = A0.w +CHECKREG R0, 0x57ed0000; +R0 = A0.x +CHECKREG R0, 0x0; + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN); + R3 = R3 +|- R5 , R6 = R3 -|+ R5 (CO); + CHECKREG R3, 0x80000000; + CHECKREG R6, 0x00008000; + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); + R7 = ( A1 += R4.L * R1.L ) (M), R6 = ( A0 += R4.L * R1.H ); +R0 = A1.w +CHECKREG R0, 0x83e38000; +R0 = A1.x +CHECKREG R0, 0xffffffff; +R0 = A0.w +CHECKREG R0, 0xa8130000; +R0 = A0.x +CHECKREG R0, 0x0; + CHECKREG R6, 0x7fffffff + CHECKREG R7, 0x83e38000 + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); + IF CC P2 = R1; + R2.H = (A1 = R7.L * R5.H) (M), R2.L = (A0 = R7.L * R5.H) (ISS2); + CHECKREG R2, 0x80007fff + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); + R3.H = R4.H * R2.H, R3.L = R4.L * R2.L (T); + CHECKREG R3, 0x7fff8001 + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); + R7 = ( A1 = R7.H * R1.H ) (M), A0 -= R7.H * R1.H (FU); + CHECKREG R7, 0xaabe7c4e + P0 = ASTAT; + CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ); + R0.H = R7.L * R4.H (M), R0.L = R7.L * R4.H (TFU); + CHECKREG R0, 0x3e273e27 + P0 = ASTAT; + CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ); + R5 = ( A1 = R7.L * R7.L ), R4 = ( A0 -= R7.H * R7.H ) (ISS2); + CHECKREG R5, 0x78b74f88 + CHECKREG R4, 0xc73635f8 +R0 = A1.w +CHECKREG R0, 0x3c5ba7c4; +R0 = A1.x +CHECKREG R0, 0x0; +R0 = A0.w +CHECKREG R0, 0xe39b1afc; +R0 = A0.x +CHECKREG R0, 0xffffffff; + R0 = ASTAT; + CHECKREG r0, (_VS|_AV0S|_AZ|_AN); + A0 = A0 >> 2; + R0 = ASTAT; + checkreg r0, (_VS|_AV0S); + R0 = A0.x; + DBGA (R0.L, 0x3f); + R0 = A0.w; + checkreg r0, 0xF8E6C6BF; + + pass diff --git a/sim/testsuite/bfin/a1.s b/sim/testsuite/bfin/a1.s new file mode 100644 index 0000000..40f9d40 --- /dev/null +++ b/sim/testsuite/bfin/a1.s @@ -0,0 +1,29 @@ +// check the imm7 bit constants bounds +# mach: bfin + +.include "testutils.inc" + start + + R0 = 63; + DBGA ( R0.L , 63 ); + R0 = -64; + DBGA ( R0.L , 0xffc0 ); + P0 = 63; + R0 = P0; DBGA ( R0.L , 63 ); + P0 = -64; + R0 = P0; DBGA ( R0.L , 0xffc0 ); + +// check loading imm16 into h/l halves + R0.L = 0x1111; + DBGA ( R0.L , 0x1111 ); + + R0.H = 0x1111; + DBGA ( R0.H , 0x1111 ); + + P0.L = 0x2222; + R0 = P0; DBGA ( R0.L , 0x2222 ); + + P0.H = 0x2222; + R0 = P0; DBGA ( R0.H , 0x2222 ); + + pass diff --git a/sim/testsuite/bfin/a10.s b/sim/testsuite/bfin/a10.s new file mode 100644 index 0000000..4117e60 --- /dev/null +++ b/sim/testsuite/bfin/a10.s @@ -0,0 +1,176 @@ +// ALU test program. +// Test dual 16 bit MAX, MIN, ABS instructions +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; +// MAX +// first operand is larger, so AN=0 + R0.L = 0x0001; + R0.H = 0x0002; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0002 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// second operand is larger + R0.L = 0x0000; + R0.H = 0x0000; + R1.L = 0x0001; + R1.H = 0x0022; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0022 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// one operand larger, one smaller. + R0.L = 0x000a; + R0.H = 0x0000; + R1.L = 0x0001; + R1.H = 0x0022; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x000a ); + DBGA ( R7.H , 0x0022 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x8001; + R0.H = 0xffff; + R1.L = 0x8000; + R1.H = 0x0022; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x8001 ); + DBGA ( R7.H , 0x0022 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x8000; + R0.H = 0xffff; + R1.L = 0x8000; + R1.H = 0x0022; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0022 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// MIN +// second operand is smaller + R0.L = 0x0001; + R0.H = 0x0004; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MIN ( R0 , R1 ) (V); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// first operand is smaller + R0.L = 0xffff; + R0.H = 0x8001; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MIN ( R0 , R1 ) (V); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x8001 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// one of each + R0.L = 0xffff; + R0.H = 0x0034; + R1.L = 0x0999; + R1.H = 0x0010; + R7 = MIN ( R0 , R1 ) (V); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x0010 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xffff; + R0.H = 0x0010; + R1.L = 0x0999; + R1.H = 0x0010; + R7 = MIN ( R0 , R1 ) (V); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x0010 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// ABS + R0.L = 0x0001; + R0.H = 0x8001; + R7 = ABS R0 (V); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x7fff ); + _DBG ASTAT; + R6 = ASTAT; + _DBG R6; + + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = VS; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0001; + R0.H = 0x8000; + R7 = ABS R0 (V); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0000; + R0.H = 0xffff; + R7 = ABS R0 (V); + _DBG R7; + _DBG ASTAT; + R6 = ASTAT; + _DBG R6; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0001 ); + CC = VS; R6 = CC; DBGA ( R6.L, 0x1 ); + CC = AZ; R6 = CC; DBGA ( R6.L, 0x1 ); + + pass diff --git a/sim/testsuite/bfin/a11.S b/sim/testsuite/bfin/a11.S new file mode 100644 index 0000000..bf3723a --- /dev/null +++ b/sim/testsuite/bfin/a11.S @@ -0,0 +1,386 @@ +// Test ALU RND RND12 RND20 +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + + R7 = 0; + ASTAT = R7; + +// 7ffffff0 +// + 00008000 +// -> 7fff0000 + R0 = 0xfff0 (Z); + R0.H = 0x7fff; + R7.L = R0 (RND); + R0 = ASTAT; + CHECKREG R7, 0x7fff; + CHECKREG R0, (_VS|_V|_V_COPY); + +// 7ffffff0 +// + 00008000 +// -> 7fff0000 + R0.L = 0xfff0; + R0.H = 0x7fff; + R7.H = R0 (RND); + R0 = ASTAT; + CHECKREG R7, 0x7fff7fff; + CHECKREG R0, (_VS|_V|_V_COPY); + +// 7ff0fff0 +// + 00008000 +// -> 7ff10000 + R0.L = 0xfff0; + R0.H = 0x7ff0; + R7.L = R0 (RND); + R0 = ASTAT; + CHECKREG R7, 0x7fff7ff1 + CHECKREG R0, (_VS); + +// 7ff0fff0 +// + 00008000 +// -> 7ff10000 +// 7ff0fff0 +// + 8000 +// -> 7ff1 + R0.L = 0xfff0; + R0.H = 0x7ff0; + R7.H = R0 (RND); + R0 = ASTAT; + CHECKREG R7, 0x7ff17ff1 + CHECKREG R0, (_VS); + +// fffffff0 +// + 00008000 +// -> 00000000 + R0.L = 0xfff0; + R0.H = 0xffff; + R7.L = R0 (RND); + R0 = ASTAT; + CHECKREG R7, 0x7ff10000; + CHECKREG R0, (_VS|_AZ); + +// fffffff0 +// + 00008000 +// -> 00000000 + R0.L = 0xfff0; + R0.H = 0xffff; + R7.H = R0 (RND); + R0 = ASTAT; + DBGA ( R7.H , 0 ); + CHECKREG R0, (_VS|_AZ); + +// 00fffff0 +// + 00008000 +// -> 0100 + R0.L = 0xfff0; + R0.H = 0x00ff; + R7.L = R0 (RND); + R0 = ASTAT; + DBGA ( R7.L , 0x0100 ); + CHECKREG R0, (_VS); + +// RND12 + +// 07ffe000 +// + 00000000 +// = 07ffe000 +// + 00000800 +// -> 7ffe + R0.L = 0xe000; + R0.H = 0x07ff; + R1 = 0x0000 (Z); + R1.H = 0x0000; + R7.L = R0 + R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x7ffe ); + CHECKREG R0, (_VS); + +// 07ffff00 +// + 00000000 +// = 07ffff00 +// + 00000800 +// -> 7fff + R0.L = 0xff00; + R0.H = 0x07ff; + R1.L = 0x0000; + R1.H = 0x0000; + R7.L = R0 + R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x7fff ); + CHECKREG R0, (_VS|_V|_V_COPY); + +// 07fffc00 +// + 00000f00 +// = 08000b00 +// + 00000800 +// -> 7fff + R0.L = 0xfc00; + R0.H = 0x07ff; + R1.L = 0x0f00; + R1.H = 0x0000; + R7.L = R0 + R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x7fff ); + CHECKREG R0, (_VS|_V|_V_COPY); + +// 07ff c000 +// + 0000 1000 +// = 07ff d000 +// + 0000 0800 +// -> 7ff d + R0.L = 0xc000; + R0.H = 0x07ff; + R1.L = 0x1000; + R1.H = 0x0000; + _DBG ASTAT; + R7.L = R0 + R1 (RND12); + _DBG ASTAT; + R0 = ASTAT; + _DBG R0; + DBGA ( R7.L , 0x7ffd ); + CHECKREG R0, (_VS); + +// ffff ffea +// + 07ff fe00 +// = 107ff fdea +// + 0000 0800 +// -> 7ff f + R0.L = 0xffea; + R0.H = 0xffff; + R1.L = 0xfe00; + R1.H = 0x07ff; + _DBG ASTAT; + R7.L = R0 + R1 (RND12); + _DBG ASTAT; + R0 = ASTAT; + _DBG R0; + DBGA ( R7.L , 0x7fff ); + CHECKREG R0, (_VS|_V|_V_COPY); + +// Small negative plus small negative should give zero +// ffff ffff +// + ffff ffff +// + 0000 0800 +// -> 000 0 + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0xffff; + R1.H = 0xffff; + _DBG ASTAT; + R7.L = R0 + R1 (RND12); + R0 = ASTAT; + _DBG R0; + DBGA ( R7.L , 0x0000 ); + CHECKREG R0, (_VS|_AZ); + +// Small negative minus small positive should give zero +// ffff ffff +// + 0000 0001 +// - 0000 0800 +// -> 000 0 + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x0001; + R1.H = 0x0000; + R7.L = R0 - R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x0000 ); + CHECKREG R0, (_VS|_AZ); + +// Large positive plus large positive should give maxpos +// 07ff ffff +// + 07ff ffff +// + 0000 0800 +// -> 7ff f + R0.L = 0xffff; + R0.H = 0x07ff; + R1.L = 0xffff; + R1.H = 0x07ff; + R7.L = R0 + R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x7fff ); + CHECKREG R0, (_VS|_V|_V_COPY); + +// Large negative plus large negative should give maxneg +// 0800 0000 +// + 0800 0000 +// + 0000 0800 +// -> 800 0 + R0.L = 0x0000; + R0.H = 0x0800; + R1.L = 0x0000; + R1.H = 0x0800; + R7.L = R0 + R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x7fff ); + CHECKREG R0, (_VS|_V|_V_COPY); + +// Large positive minus large negative should give maxpos +// 07ff ffff +// - 0800 0000 +// + 0000 0800 +// -> 800 0 + R0.L = 0xffff; + R0.H = 0x07ff; + R1.L = 0x0000; + R1.H = 0x0800; + R7.L = R0 - R1 (RND12); + R0 = ASTAT; + _DBG ASTAT; + DBGA ( R7.L , 0x0 ); + CHECKREG R0, (_VS|_AZ); + +// Large negative minus large positive should give maxneg +// 0800 0000 +// - 07ff ffff +// + 0000 0800 +// -> 800 0 + R0.L = 0x0000; + R0.H = 0x0800; + R1.L = 0xffff; + R1.H = 0x07ff; + R7.L = R0 - R1 (RND12); + R0 = ASTAT; + _DBG ASTAT; + DBGA ( R7.L , 0x0000 ); + CHECKREG R0, (_VS|_AZ); + +// cef4 3ed6 +// - 56f4 417a +// + 0000 0800 +// -> 800 0 + R0.L = 0x3ed6; + R0.H = 0xcef4; + R1.L = 0x417a; + R1.H = 0x56f4; + R7.L = R0 - R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x8000 ); + CHECKREG R0, (_VS|_V|_V_COPY|_AN); + +// RND20 + +// 00ff 0000 +// + 0000 0000 +// + 0008 0000 +// ->0010 + R0.L = 0x0000; + R0.H = 0x00ff; + R1.L = 0x0000; + R1.H = 0x0000; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x0010 ); + CHECKREG R0, (_VS); + +// 00f0 0000 +// + 000f 0000 +// + 0008 0000 +// ->0010 + R0.L = 0x0000; + R0.H = 0x00f0; + R1.L = 0x0000; + R1.H = 0x000f; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x0010 ); + CHECKREG R0, (_VS); + +// 7ff0 0000 +// + 0000 0000 +// + 0008 0000 +// ->07ff + R0.L = 0x0000; + R0.H = 0x7ff0; + R1.L = 0x0000; + R1.H = 0x0000; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x07ff ); + CHECKREG R0, (_VS); + +// 7fff 0000 +// + 0000 0000 +// + 0008 0000 +// ->0800 + R0.L = 0x0000; + R0.H = 0x7fff; + R1.L = 0x0000; + R1.H = 0x0000; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x0800 ); + CHECKREG R0, (_VS); + +// ffff 0000 +// + 0000 0000 +// + 0008 0000 +// ->0000 + R0.L = 0x0000; + R0.H = 0xffff; + R1.L = 0x0000; + R1.H = 0x0000; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x0000 ); + DBGA ( R0.H , 0x0200 ); + DBGA ( R0.L , 0x0001 ); + +// ff00 0000 +// + 0010 0000 +// + 0008 0000 +// ->fff1 + R0.L = 0x0000; + R0.H = 0xff00; + R1.L = 0x0000; + R1.H = 0x0010; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0xfff1 ); + CHECKREG R0, (_VS|_AN); + +// ff00 0000 +// + 0018 0000 +// + 0008 0000 +// ->fff2 + R0.L = 0x0000; + R0.H = 0xff00; + R1.L = 0x0000; + R1.H = 0x0018; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0xfff2 ); + CHECKREG R0, (_VS|_AN); + +// Small negative plus small negative should give zero +// ffff ffff +// + ffff ffff +// + 0008 0000 +// ->0000 + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0xffff; + R1.H = 0xffff; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x0000 ); + CHECKREG R0, (_VS|_AZ); + +// Small negative minus small positive should give zero +// ffff ffff +// + 0000 0010 +// + 0008 0000 +// ->0000 + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x0010; + R1.H = 0x0000; + R7.L = R0 - R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x0000 ); + CHECKREG R0, (_VS|_AZ); + + pass diff --git a/sim/testsuite/bfin/a12.s b/sim/testsuite/bfin/a12.s new file mode 100644 index 0000000..ddc436e --- /dev/null +++ b/sim/testsuite/bfin/a12.s @@ -0,0 +1,40 @@ +// Test SAA +# mach: bfin + +.include "testutils.inc" + start + + I0 = 0; + I1 = 0; + + imm32 R0, 0x04030201; + imm32 R2, 0x04030201; + A1 = A0 = 0; + saa(r1:0,r3:2); + R0 = A0.w; + R1 = A1.w; + CHECKREG R0, 0; + CHECKREG R1, 0; + + imm32 R0, 0x00000201; + imm32 R2, 0x00020102; + A1 = A0 = 0; + saa(r1:0,r3:2); + saa(r1:0,r3:2); + saa(r1:0,r3:2); + R0 = A0.w; + R1 = A1.w; + CHECKREG R0, 0x00030003; + CHECKREG R1, 0x00000006; + + imm32 R0, 0x000300ff; + imm32 R2, 0x0001ff00; + A1 = A0 = 0; + saa(r1:0,r3:2); + saa(r1:0,r3:2); + R0 = A0.w; + R1 = A1.w; + CHECKREG R0, 0x1fe01fe; + CHECKREG R1, 0x0000004; + + pass diff --git a/sim/testsuite/bfin/a2.s b/sim/testsuite/bfin/a2.s new file mode 100644 index 0000000..eb668dd --- /dev/null +++ b/sim/testsuite/bfin/a2.s @@ -0,0 +1,179 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym P0, middle; + + R0 = [ P0 + 0 ]; DBGA ( R0.L , 50 ); + R0 = [ P0 + 4 ]; DBGA ( R0.L , 51 ); + R0 = [ P0 + 8 ]; DBGA ( R0.L , 52 ); + R0 = [ P0 + 12 ]; DBGA ( R0.L , 53 ); + R0 = [ P0 + 16 ]; DBGA ( R0.L , 54 ); + R0 = [ P0 + 20 ]; DBGA ( R0.L , 55 ); + R0 = [ P0 + 24 ]; DBGA ( R0.L , 56 ); + R0 = [ P0 + 28 ]; DBGA ( R0.L , 57 ); + + R0 = [ P0 + -4 ]; DBGA ( R0.L , 49 ); + R0 = [ P0 + -8 ]; DBGA ( R0.L , 48 ); + R0 = [ P0 + -12 ]; DBGA ( R0.L , 47 ); + R0 = [ P0 + -16 ]; DBGA ( R0.L , 46 ); + R0 = [ P0 + -20 ]; DBGA ( R0.L , 45 ); + R0 = [ P0 + -24 ]; DBGA ( R0.L , 44 ); + R0 = [ P0 + -28 ]; DBGA ( R0.L , 43 ); + R0 = [ P0 + -32 ]; DBGA ( R0.L , 42 ); + + FP = P0; + + R0 = [ FP + 0 ]; DBGA ( R0.L , 50 ); + R0 = [ FP + 4 ]; DBGA ( R0.L , 51 ); + R0 = [ FP + 8 ]; DBGA ( R0.L , 52 ); + R0 = [ FP + 12 ]; DBGA ( R0.L , 53 ); + R0 = [ FP + 16 ]; DBGA ( R0.L , 54 ); + R0 = [ FP + 20 ]; DBGA ( R0.L , 55 ); + R0 = [ FP + 24 ]; DBGA ( R0.L , 56 ); + R0 = [ FP + 28 ]; DBGA ( R0.L , 57 ); + R0 = [ FP + 32 ]; DBGA ( R0.L , 58 ); + R0 = [ FP + 36 ]; DBGA ( R0.L , 59 ); + R0 = [ FP + 40 ]; DBGA ( R0.L , 60 ); + R0 = [ FP + 44 ]; DBGA ( R0.L , 61 ); + R0 = [ FP + 48 ]; DBGA ( R0.L , 62 ); + R0 = [ FP + 52 ]; DBGA ( R0.L , 63 ); + R0 = [ FP + 56 ]; DBGA ( R0.L , 64 ); + R0 = [ FP + 60 ]; DBGA ( R0.L , 65 ); + + R0 = [ FP + -4 ]; DBGA ( R0.L , 49 ); + R0 = [ FP + -8 ]; DBGA ( R0.L , 48 ); + R0 = [ FP + -12 ]; DBGA ( R0.L , 47 ); + R0 = [ FP + -16 ]; DBGA ( R0.L , 46 ); + R0 = [ FP + -20 ]; DBGA ( R0.L , 45 ); + R0 = [ FP + -24 ]; DBGA ( R0.L , 44 ); + R0 = [ FP + -28 ]; DBGA ( R0.L , 43 ); + R0 = [ FP + -32 ]; DBGA ( R0.L , 42 ); + R0 = [ FP + -36 ]; DBGA ( R0.L , 41 ); + R0 = [ FP + -40 ]; DBGA ( R0.L , 40 ); + R0 = [ FP + -44 ]; DBGA ( R0.L , 39 ); + R0 = [ FP + -48 ]; DBGA ( R0.L , 38 ); + R0 = [ FP + -52 ]; DBGA ( R0.L , 37 ); + R0 = [ FP + -56 ]; DBGA ( R0.L , 36 ); + R0 = [ FP + -60 ]; DBGA ( R0.L , 35 ); + R0 = [ FP + -64 ]; DBGA ( R0.L , 34 ); + R0 = [ FP + -68 ]; DBGA ( R0.L , 33 ); + R0 = [ FP + -72 ]; DBGA ( R0.L , 32 ); + R0 = [ FP + -76 ]; DBGA ( R0.L , 31 ); + R0 = [ FP + -80 ]; DBGA ( R0.L , 30 ); + R0 = [ FP + -84 ]; DBGA ( R0.L , 29 ); + R0 = [ FP + -88 ]; DBGA ( R0.L , 28 ); + R0 = [ FP + -92 ]; DBGA ( R0.L , 27 ); + R0 = [ FP + -96 ]; DBGA ( R0.L , 26 ); + R0 = [ FP + -100 ]; DBGA ( R0.L , 25 ); + R0 = [ FP + -104 ]; DBGA ( R0.L , 24 ); + R0 = [ FP + -108 ]; DBGA ( R0.L , 23 ); + R0 = [ FP + -112 ]; DBGA ( R0.L , 22 ); + R0 = [ FP + -116 ]; DBGA ( R0.L , 21 ); + + pass + + .data +base: + .dd 0 + .dd 1 + .dd 2 + .dd 3 + .dd 4 + .dd 5 + .dd 6 + .dd 7 + .dd 8 + .dd 9 + .dd 10 + .dd 11 + .dd 12 + .dd 13 + .dd 14 + .dd 15 + .dd 16 + .dd 17 + .dd 18 + .dd 19 + .dd 20 + .dd 21 + .dd 22 + .dd 23 + .dd 24 + .dd 25 + .dd 26 + .dd 27 + .dd 28 + .dd 29 + .dd 30 + .dd 31 + .dd 32 + .dd 33 + .dd 34 + .dd 35 + .dd 36 + .dd 37 + .dd 38 + .dd 39 + .dd 40 + .dd 41 + .dd 42 + .dd 43 + .dd 44 + .dd 45 + .dd 46 + .dd 47 + .dd 48 + .dd 49 +middle: + .dd 50 + .dd 51 + .dd 52 + .dd 53 + .dd 54 + .dd 55 + .dd 56 + .dd 57 + .dd 58 + .dd 59 + .dd 60 + .dd 61 + .dd 62 + .dd 63 + .dd 64 + .dd 65 + .dd 66 + .dd 67 + .dd 68 + .dd 69 + .dd 70 + .dd 71 + .dd 72 + .dd 73 + .dd 74 + .dd 75 + .dd 76 + .dd 77 + .dd 78 + .dd 79 + .dd 80 + .dd 81 + .dd 82 + .dd 83 + .dd 84 + .dd 85 + .dd 86 + .dd 87 + .dd 88 + .dd 89 + .dd 90 + .dd 91 + .dd 92 + .dd 93 + .dd 94 + .dd 95 + .dd 96 + .dd 97 + .dd 98 + .dd 99 diff --git a/sim/testsuite/bfin/a20.S b/sim/testsuite/bfin/a20.S new file mode 100644 index 0000000..6245994 --- /dev/null +++ b/sim/testsuite/bfin/a20.S @@ -0,0 +1,68 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R1 = 0; + ASTAT = R1; + + R1.H = -32768; + R2 = 0; + R2.H = -32768; + R3 = R1 +|+ R2; + _DBG ASTAT; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AC1|_AZ); + + R0.L = 32767; + R0.H = 32767; + R0 = R0 +|- R0; + _DBG ASTAT; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN|_AZ) + + R0 = 0; + ASTAT = R0; + _DBG ASTAT; + R7 = ASTAT; + CHECKREG R7, (_UNSET) + + R1.L = -1; + R1.H = 0x7fff; + R0 = ABS R1; + _DBG R0; + _DBG ASTAT; + R7 = ASTAT; + CHECKREG R7, (_UNSET) + + R1=0; + R1.H = 0x8000; + _DBG R1; + R0 = ABS R1; + _DBG R0; + _DBG ASTAT; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY) + + R0 = 0; + ASTAT = R0; + + R1.L = 32767; + R1.H = 32767; + R0 = R1 +|+ R1 (CO); + _DBG R0; + _DBG ASTAT; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AN) + + R0.L = -1; + R0.H = 32766; + R1.L = -1; + R1.H = -32768; + R0 = PACK( R0.H , R1.L ); + _DBG R0; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AN) + + pass diff --git a/sim/testsuite/bfin/a21.s b/sim/testsuite/bfin/a21.s new file mode 100644 index 0000000..c621921 --- /dev/null +++ b/sim/testsuite/bfin/a21.s @@ -0,0 +1,83 @@ +// Test ALU RND RND12 RND20 +# mach: bfin + +.include "testutils.inc" + start + + +// positive saturation + R0 = 0xffffffff; + A0.w = R0; + A1.w = R0; + R0 = 0x7f (X); + A0.x = R0; + A1.x = R0; + R3 = A1 + A0, R4 = A1 - A0 (S); + DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff ); + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 ); + +// neg saturation + R0 = 0; + A0.w = R0; + A1.w = R0; + R0 = 0x80 (X); + A0.x = R0; + A1.x = R0; + R3 = A1 + A0, R4 = A1 - A0 (S); + DBGA ( R3.H , 0x8000 ); DBGA ( R3.L , 0x0000 ); + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 ); + +// positive saturation + R0 = 0xfffffff0; + A0.w = R0; + A1.w = R0; + R0 = 0x01; + A0.x = R0; + A1.x = R0; + R3 = A1 + A0, R4 = A1 - A0 (S); + DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff ); + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 ); + +// no sat + R0 = 0xfffffff0; + A0.w = R0; + A1.w = R0; + R0 = 0x01; + A0.x = R0; + A1.x = R0; + R3 = A1 + A0, R4 = A1 - A0 (NS); + DBGA ( R3.H , 0xffff ); DBGA ( R3.L , 0xffe0 ); + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 ); + +// add and sub +1 -1 + R0 = 0x00000001; + A0.w = R0; + R0 = 0xffffffff; + A1.w = R0; + R0 = 0; + A0.x = R0; + R0 = 0xff (X); + A1.x = R0; + R3 = A1 + A0, R4 = A1 - A0 (NS); + DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); // 0 + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); // -2 + +// should get the same with saturation + R3 = A1 + A0, R4 = A1 - A0 (S); + DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); // 0 + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); // -2 + +// add and sub -1 +1 but with reverse order of A0 A1 + R0 = 0x00000001; + A0.w = R0; + R0 = 0xffffffff; + A1.w = R0; + R0 = 0; + A0.x = R0; + R0 = 0xff (X); + A1.x = R0; + R3 = A0 + A1, R4 = A0 - A1 (NS); + DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0002 ); + + pass diff --git a/sim/testsuite/bfin/a22.s b/sim/testsuite/bfin/a22.s new file mode 100644 index 0000000..1df76df --- /dev/null +++ b/sim/testsuite/bfin/a22.s @@ -0,0 +1,83 @@ +// Test ALU NEG accumulators +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0xffffffff; + A0.w = R0; + R0 = 0x7f (X); + A0.x = R0; + A0 = - A0; + _DBG A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff80 ); + + R0 = 0x1; + A0.w = R0; + R0 = 0x0; + A0.x = R0; + A0 = - A0; + R4 = A0.w; + R5 = A0.x; + _DBG A0; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); + + R0 = 0xffffffff; + A0.w = R0; + R0 = 0xff (X); + A0.x = R0; + A0 = - A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); + + R0 = 0x00000000; + A0.w = R0; + R0 = 0x80 (X); + A0.x = R0; + A0 = - A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + +// NEG NEG + R0 = 0x00000000; + A0.w = R0; + R0 = 0x80 (X); + A0.x = R0; + + R0 = 0xffffffff; + A1.w = R0; + R0 = 0x7f (X); + A1.x = R0; + + A1 = - A1, A0 = - A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + R4 = A1.w; + R5 = A1.x; + _DBG A1; + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff80 ); + +// NEG NEG register + R0.L = 0x0001; + R0.H = 0x8000; + + R3 = - R0 (V); + DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff ); + + _DBG ASTAT; + + pass diff --git a/sim/testsuite/bfin/a23.s b/sim/testsuite/bfin/a23.s new file mode 100644 index 0000000..d63fa0c --- /dev/null +++ b/sim/testsuite/bfin/a23.s @@ -0,0 +1,84 @@ +// Test ALU ABS accumulators +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0x00000000; + A0.w = R0; + R0 = 0x80 (X); + A0.x = R0; + + A0 = ABS A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + R0 = 0x00000001; + A0.w = R0; + R0 = 0x80 (X); + A0.x = R0; + + A0 = ABS A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + R0 = 0xffffffff; + A0.w = R0; + R0 = 0xff (X); + A0.x = R0; + + A0 = ABS A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); + + R0 = 0xfffffff0; + A0.w = R0; + R0 = 0x7f (X); + A0.x = R0; + + A0 = ABS A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfff0 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + R0 = 0x00000000; + A0.w = R0; + R0 = 0x80 (X); + A0.x = R0; + + A1 = ABS A0; + R4 = A1.w; + R5 = A1.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + R0 = 0x00000000; + A0.w = R0; + R0 = 0x80 (X); + A0.x = R0; + + R0 = 0x00000002; + A1.w = R0; + R0 = 0x80 (X); + A1.x = R0; + + A1 = ABS A1, A0 = ABS A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + R4 = A1.w; + R5 = A1.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + pass diff --git a/sim/testsuite/bfin/a24.s b/sim/testsuite/bfin/a24.s new file mode 100644 index 0000000..507350f --- /dev/null +++ b/sim/testsuite/bfin/a24.s @@ -0,0 +1,12 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0x1111 (X); + R0.H = 0x1111; + A0.x = R0; + R1 = A0.x; + DBGA ( R1.L , 0x11 ); + DBGA ( R1.H , 0x0 ); + pass diff --git a/sim/testsuite/bfin/a25.s b/sim/testsuite/bfin/a25.s new file mode 100644 index 0000000..b5d5d7b --- /dev/null +++ b/sim/testsuite/bfin/a25.s @@ -0,0 +1,28 @@ +# mach: bfin + +.include "testutils.inc" + start + + + A1 = A0 = 0; + R0.L = 0x01; + A0.x = R0; +//A0 = 0x0100000000 +//A1 = 0x0000000000 + + R4.L = 0x2d1a; + R4.H = 0x32e0; + + A1.x = R4; +//A1 = 0x1a00000000 + + A0.w = A1.x; + + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x001a ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0001 ); + + pass diff --git a/sim/testsuite/bfin/a26.s b/sim/testsuite/bfin/a26.s new file mode 100644 index 0000000..2e9a0b5 --- /dev/null +++ b/sim/testsuite/bfin/a26.s @@ -0,0 +1,72 @@ +// Test ALU SEARCH instruction +# mach: bfin + +.include "testutils.inc" + start + + + init_r_regs 0; + ASTAT = R0; + + R0 = 4; + R1 = 5; + A1 = A0 = 0; + + R2.L = 0x0001; + R2.H = 0xffff; + + loadsym P0, foo; + + ( R1 , R0 ) = SEARCH R2 (GT); + + // R0 should be the pointer + R7 = P0; + CC = R0 == R7; + if !CC JUMP _fail; + + _DBG R1; // does not change + DBGA ( R1.H , 0 ); DBGA ( R1.L , 0x5 ); + + _DBG A0; // changes + R0 = A0.w; + DBGA ( R0.H , 0 ); DBGA ( R0.L , 0x1 ); + + _DBG A1; // does not change + R0 = A1.w; + DBGA ( R0.H , 0 ); DBGA ( R0.L , 0 ); + + R0 = 4; + R1 = 5; + A1 = A0 = 0; + + R2.L = 0x0000; + R2.H = 0xffff; + + loadsym p0, foo; + + ( R1 , R0 ) = SEARCH R2 (LT); + + _DBG R0; // no change + DBGA ( R0.H , 0 ); DBGA ( R0.L , 4 ); + + _DBG R1; // change + R7 = P0; + CC = R1 == R7; + if !CC JUMP _fail; + + _DBG A0; + R0 = A0.w; + DBGA ( R0.H , 0 ); DBGA ( R0.L , 0 ); + + _DBG A1; + R0 = A1.w; + DBGA ( R0.H , 0xffff ); DBGA ( R0.L , 0xffff ); + + pass + +_fail: + fail; + + .data +foo: + .space (0x100) diff --git a/sim/testsuite/bfin/a3.s b/sim/testsuite/bfin/a3.s new file mode 100644 index 0000000..c53300b --- /dev/null +++ b/sim/testsuite/bfin/a3.s @@ -0,0 +1,313 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym P1, middle; + + R0 = W [ P1 + -2 ] (Z); DBGA ( R0.L , 49 ); + R0 = W [ P1 + -4 ] (Z); DBGA ( R0.L , 48 ); + R0 = W [ P1 + -6 ] (Z); DBGA ( R0.L , 47 ); + R0 = W [ P1 + -8 ] (Z); DBGA ( R0.L , 46 ); + R0 = W [ P1 + -10 ] (Z); DBGA ( R0.L , 45 ); + R0 = W [ P1 + -12 ] (Z); DBGA ( R0.L , 44 ); + R0 = W [ P1 + -14 ] (Z); DBGA ( R0.L , 43 ); + R0 = W [ P1 + -16 ] (Z); DBGA ( R0.L , 42 ); + R0 = W [ P1 + -18 ] (Z); DBGA ( R0.L , 41 ); + R0 = W [ P1 + -20 ] (Z); DBGA ( R0.L , 40 ); + R0 = W [ P1 + -22 ] (Z); DBGA ( R0.L , 39 ); + R0 = W [ P1 + -24 ] (Z); DBGA ( R0.L , 38 ); + R0 = W [ P1 + -26 ] (Z); DBGA ( R0.L , 37 ); + R0 = W [ P1 + -28 ] (Z); DBGA ( R0.L , 36 ); + R0 = W [ P1 + -30 ] (Z); DBGA ( R0.L , 35 ); + R0 = W [ P1 + -32 ] (Z); DBGA ( R0.L , 34 ); + R0 = W [ P1 + -34 ] (Z); DBGA ( R0.L , 33 ); + R0 = W [ P1 + -36 ] (Z); DBGA ( R0.L , 32 ); + R0 = W [ P1 + -38 ] (Z); DBGA ( R0.L , 31 ); + R0 = W [ P1 + -40 ] (Z); DBGA ( R0.L , 30 ); + R0 = W [ P1 + -42 ] (Z); DBGA ( R0.L , 29 ); + R0 = W [ P1 + -44 ] (Z); DBGA ( R0.L , 28 ); + R0 = W [ P1 + -46 ] (Z); DBGA ( R0.L , 27 ); + R0 = W [ P1 + -48 ] (Z); DBGA ( R0.L , 26 ); + R0 = W [ P1 + -50 ] (Z); DBGA ( R0.L , 25 ); + R0 = W [ P1 + -52 ] (Z); DBGA ( R0.L , 24 ); + R0 = W [ P1 + -54 ] (Z); DBGA ( R0.L , 23 ); + R0 = W [ P1 + -56 ] (Z); DBGA ( R0.L , 22 ); + R0 = W [ P1 + -58 ] (Z); DBGA ( R0.L , 21 ); + R0 = W [ P1 + -60 ] (Z); DBGA ( R0.L , 20 ); + R0 = W [ P1 + -62 ] (Z); DBGA ( R0.L , 19 ); + R0 = W [ P1 + -64 ] (Z); DBGA ( R0.L , 18 ); + R0 = W [ P1 + -66 ] (Z); DBGA ( R0.L , 17 ); + R0 = W [ P1 + -68 ] (Z); DBGA ( R0.L , 16 ); + R0 = W [ P1 + -70 ] (Z); DBGA ( R0.L , 15 ); + R0 = W [ P1 + -72 ] (Z); DBGA ( R0.L , 14 ); + R0 = W [ P1 + -74 ] (Z); DBGA ( R0.L , 13 ); + R0 = W [ P1 + -76 ] (Z); DBGA ( R0.L , 12 ); + R0 = W [ P1 + -78 ] (Z); DBGA ( R0.L , 11 ); + R0 = W [ P1 + -80 ] (Z); DBGA ( R0.L , 10 ); + R0 = W [ P1 + -82 ] (Z); DBGA ( R0.L , 9 ); + R0 = W [ P1 + -84 ] (Z); DBGA ( R0.L , 8 ); + R0 = W [ P1 + -86 ] (Z); DBGA ( R0.L , 7 ); + R0 = W [ P1 + -88 ] (Z); DBGA ( R0.L , 6 ); + R0 = W [ P1 + -90 ] (Z); DBGA ( R0.L , 5 ); + R0 = W [ P1 + -92 ] (Z); DBGA ( R0.L , 4 ); + R0 = W [ P1 + -94 ] (Z); DBGA ( R0.L , 3 ); + R0 = W [ P1 + -96 ] (Z); DBGA ( R0.L , 2 ); + R0 = W [ P1 + -98 ] (Z); DBGA ( R0.L , 1 ); + R0 = W [ P1 + 0 ] (Z); DBGA ( R0.L , 50 ); + R0 = W [ P1 + 2 ] (Z); DBGA ( R0.L , 51 ); + R0 = W [ P1 + 4 ] (Z); DBGA ( R0.L , 52 ); + R0 = W [ P1 + 6 ] (Z); DBGA ( R0.L , 53 ); + R0 = W [ P1 + 8 ] (Z); DBGA ( R0.L , 54 ); + R0 = W [ P1 + 10 ] (Z); DBGA ( R0.L , 55 ); + R0 = W [ P1 + 12 ] (Z); DBGA ( R0.L , 56 ); + R0 = W [ P1 + 14 ] (Z); DBGA ( R0.L , 57 ); + R0 = W [ P1 + 16 ] (Z); DBGA ( R0.L , 58 ); + R0 = W [ P1 + 18 ] (Z); DBGA ( R0.L , 59 ); + R0 = W [ P1 + 20 ] (Z); DBGA ( R0.L , 60 ); + R0 = W [ P1 + 22 ] (Z); DBGA ( R0.L , 61 ); + R0 = W [ P1 + 24 ] (Z); DBGA ( R0.L , 62 ); + R0 = W [ P1 + 26 ] (Z); DBGA ( R0.L , 63 ); + R0 = W [ P1 + 28 ] (Z); DBGA ( R0.L , 64 ); + R0 = W [ P1 + 30 ] (Z); DBGA ( R0.L , 65 ); + R0 = W [ P1 + 32 ] (Z); DBGA ( R0.L , 66 ); + R0 = W [ P1 + 34 ] (Z); DBGA ( R0.L , 67 ); + R0 = W [ P1 + 36 ] (Z); DBGA ( R0.L , 68 ); + R0 = W [ P1 + 38 ] (Z); DBGA ( R0.L , 69 ); + R0 = W [ P1 + 40 ] (Z); DBGA ( R0.L , 70 ); + R0 = W [ P1 + 42 ] (Z); DBGA ( R0.L , 71 ); + R0 = W [ P1 + 44 ] (Z); DBGA ( R0.L , 72 ); + R0 = W [ P1 + 46 ] (Z); DBGA ( R0.L , 73 ); + R0 = W [ P1 + 48 ] (Z); DBGA ( R0.L , 74 ); + R0 = W [ P1 + 50 ] (Z); DBGA ( R0.L , 75 ); + R0 = W [ P1 + 52 ] (Z); DBGA ( R0.L , 76 ); + R0 = W [ P1 + 54 ] (Z); DBGA ( R0.L , 77 ); + R0 = W [ P1 + 56 ] (Z); DBGA ( R0.L , 78 ); + R0 = W [ P1 + 58 ] (Z); DBGA ( R0.L , 79 ); + R0 = W [ P1 + 60 ] (Z); DBGA ( R0.L , 80 ); + R0 = W [ P1 + 62 ] (Z); DBGA ( R0.L , 81 ); + R0 = W [ P1 + 64 ] (Z); DBGA ( R0.L , 82 ); + R0 = W [ P1 + 66 ] (Z); DBGA ( R0.L , 83 ); + R0 = W [ P1 + 68 ] (Z); DBGA ( R0.L , 84 ); + R0 = W [ P1 + 70 ] (Z); DBGA ( R0.L , 85 ); + R0 = W [ P1 + 72 ] (Z); DBGA ( R0.L , 86 ); + R0 = W [ P1 + 74 ] (Z); DBGA ( R0.L , 87 ); + R0 = W [ P1 + 76 ] (Z); DBGA ( R0.L , 88 ); + R0 = W [ P1 + 78 ] (Z); DBGA ( R0.L , 89 ); + R0 = W [ P1 + 80 ] (Z); DBGA ( R0.L , 90 ); + R0 = W [ P1 + 82 ] (Z); DBGA ( R0.L , 91 ); + R0 = W [ P1 + 84 ] (Z); DBGA ( R0.L , 92 ); + R0 = W [ P1 + 86 ] (Z); DBGA ( R0.L , 93 ); + R0 = W [ P1 + 88 ] (Z); DBGA ( R0.L , 94 ); + R0 = W [ P1 + 90 ] (Z); DBGA ( R0.L , 95 ); + R0 = W [ P1 + 92 ] (Z); DBGA ( R0.L , 96 ); + R0 = W [ P1 + 94 ] (Z); DBGA ( R0.L , 97 ); + R0 = W [ P1 + 96 ] (Z); DBGA ( R0.L , 98 ); + R0 = W [ P1 + 98 ] (Z); DBGA ( R0.L , 99 ); + + FP = P1; + + R0 = W [ FP + -2 ] (Z); DBGA ( R0.L , 49 ); + R0 = W [ FP + -4 ] (Z); DBGA ( R0.L , 48 ); + R0 = W [ FP + -6 ] (Z); DBGA ( R0.L , 47 ); + R0 = W [ FP + -8 ] (Z); DBGA ( R0.L , 46 ); + R0 = W [ FP + -10 ] (Z); DBGA ( R0.L , 45 ); + R0 = W [ FP + -12 ] (Z); DBGA ( R0.L , 44 ); + R0 = W [ FP + -14 ] (Z); DBGA ( R0.L , 43 ); + R0 = W [ FP + -16 ] (Z); DBGA ( R0.L , 42 ); + R0 = W [ FP + -18 ] (Z); DBGA ( R0.L , 41 ); + R0 = W [ FP + -20 ] (Z); DBGA ( R0.L , 40 ); + R0 = W [ FP + -22 ] (Z); DBGA ( R0.L , 39 ); + R0 = W [ FP + -24 ] (Z); DBGA ( R0.L , 38 ); + R0 = W [ FP + -26 ] (Z); DBGA ( R0.L , 37 ); + R0 = W [ FP + -28 ] (Z); DBGA ( R0.L , 36 ); + R0 = W [ FP + -30 ] (Z); DBGA ( R0.L , 35 ); + R0 = W [ FP + -32 ] (Z); DBGA ( R0.L , 34 ); + R0 = W [ FP + -34 ] (Z); DBGA ( R0.L , 33 ); + R0 = W [ FP + -36 ] (Z); DBGA ( R0.L , 32 ); + R0 = W [ FP + -38 ] (Z); DBGA ( R0.L , 31 ); + R0 = W [ FP + -40 ] (Z); DBGA ( R0.L , 30 ); + R0 = W [ FP + -42 ] (Z); DBGA ( R0.L , 29 ); + R0 = W [ FP + -44 ] (Z); DBGA ( R0.L , 28 ); + R0 = W [ FP + -46 ] (Z); DBGA ( R0.L , 27 ); + R0 = W [ FP + -48 ] (Z); DBGA ( R0.L , 26 ); + R0 = W [ FP + -50 ] (Z); DBGA ( R0.L , 25 ); + R0 = W [ FP + -52 ] (Z); DBGA ( R0.L , 24 ); + R0 = W [ FP + -54 ] (Z); DBGA ( R0.L , 23 ); + R0 = W [ FP + -56 ] (Z); DBGA ( R0.L , 22 ); + R0 = W [ FP + -58 ] (Z); DBGA ( R0.L , 21 ); + R0 = W [ FP + -60 ] (Z); DBGA ( R0.L , 20 ); + R0 = W [ FP + -62 ] (Z); DBGA ( R0.L , 19 ); + R0 = W [ FP + -64 ] (Z); DBGA ( R0.L , 18 ); + R0 = W [ FP + -66 ] (Z); DBGA ( R0.L , 17 ); + R0 = W [ FP + -68 ] (Z); DBGA ( R0.L , 16 ); + R0 = W [ FP + -70 ] (Z); DBGA ( R0.L , 15 ); + R0 = W [ FP + -72 ] (Z); DBGA ( R0.L , 14 ); + R0 = W [ FP + -74 ] (Z); DBGA ( R0.L , 13 ); + R0 = W [ FP + -76 ] (Z); DBGA ( R0.L , 12 ); + R0 = W [ FP + -78 ] (Z); DBGA ( R0.L , 11 ); + R0 = W [ FP + -80 ] (Z); DBGA ( R0.L , 10 ); + R0 = W [ FP + -82 ] (Z); DBGA ( R0.L , 9 ); + R0 = W [ FP + -84 ] (Z); DBGA ( R0.L , 8 ); + R0 = W [ FP + -86 ] (Z); DBGA ( R0.L , 7 ); + R0 = W [ FP + -88 ] (Z); DBGA ( R0.L , 6 ); + R0 = W [ FP + -90 ] (Z); DBGA ( R0.L , 5 ); + R0 = W [ FP + -92 ] (Z); DBGA ( R0.L , 4 ); + R0 = W [ FP + -94 ] (Z); DBGA ( R0.L , 3 ); + R0 = W [ FP + -96 ] (Z); DBGA ( R0.L , 2 ); + R0 = W [ FP + -98 ] (Z); DBGA ( R0.L , 1 ); + R0 = W [ FP + 0 ] (Z); DBGA ( R0.L , 50 ); + R0 = W [ FP + 2 ] (Z); DBGA ( R0.L , 51 ); + R0 = W [ FP + 4 ] (Z); DBGA ( R0.L , 52 ); + R0 = W [ FP + 6 ] (Z); DBGA ( R0.L , 53 ); + R0 = W [ FP + 8 ] (Z); DBGA ( R0.L , 54 ); + R0 = W [ FP + 10 ] (Z); DBGA ( R0.L , 55 ); + R0 = W [ FP + 12 ] (Z); DBGA ( R0.L , 56 ); + R0 = W [ FP + 14 ] (Z); DBGA ( R0.L , 57 ); + R0 = W [ FP + 16 ] (Z); DBGA ( R0.L , 58 ); + R0 = W [ FP + 18 ] (Z); DBGA ( R0.L , 59 ); + R0 = W [ FP + 20 ] (Z); DBGA ( R0.L , 60 ); + R0 = W [ FP + 22 ] (Z); DBGA ( R0.L , 61 ); + R0 = W [ FP + 24 ] (Z); DBGA ( R0.L , 62 ); + R0 = W [ FP + 26 ] (Z); DBGA ( R0.L , 63 ); + R0 = W [ FP + 28 ] (Z); DBGA ( R0.L , 64 ); + R0 = W [ FP + 30 ] (Z); DBGA ( R0.L , 65 ); + R0 = W [ FP + 32 ] (Z); DBGA ( R0.L , 66 ); + R0 = W [ FP + 34 ] (Z); DBGA ( R0.L , 67 ); + R0 = W [ FP + 36 ] (Z); DBGA ( R0.L , 68 ); + R0 = W [ FP + 38 ] (Z); DBGA ( R0.L , 69 ); + R0 = W [ FP + 40 ] (Z); DBGA ( R0.L , 70 ); + R0 = W [ FP + 42 ] (Z); DBGA ( R0.L , 71 ); + R0 = W [ FP + 44 ] (Z); DBGA ( R0.L , 72 ); + R0 = W [ FP + 46 ] (Z); DBGA ( R0.L , 73 ); + R0 = W [ FP + 48 ] (Z); DBGA ( R0.L , 74 ); + R0 = W [ FP + 50 ] (Z); DBGA ( R0.L , 75 ); + R0 = W [ FP + 52 ] (Z); DBGA ( R0.L , 76 ); + R0 = W [ FP + 54 ] (Z); DBGA ( R0.L , 77 ); + R0 = W [ FP + 56 ] (Z); DBGA ( R0.L , 78 ); + R0 = W [ FP + 58 ] (Z); DBGA ( R0.L , 79 ); + R0 = W [ FP + 60 ] (Z); DBGA ( R0.L , 80 ); + R0 = W [ FP + 62 ] (Z); DBGA ( R0.L , 81 ); + R0 = W [ FP + 64 ] (Z); DBGA ( R0.L , 82 ); + R0 = W [ FP + 66 ] (Z); DBGA ( R0.L , 83 ); + R0 = W [ FP + 68 ] (Z); DBGA ( R0.L , 84 ); + R0 = W [ FP + 70 ] (Z); DBGA ( R0.L , 85 ); + R0 = W [ FP + 72 ] (Z); DBGA ( R0.L , 86 ); + R0 = W [ FP + 74 ] (Z); DBGA ( R0.L , 87 ); + R0 = W [ FP + 76 ] (Z); DBGA ( R0.L , 88 ); + R0 = W [ FP + 78 ] (Z); DBGA ( R0.L , 89 ); + R0 = W [ FP + 80 ] (Z); DBGA ( R0.L , 90 ); + R0 = W [ FP + 82 ] (Z); DBGA ( R0.L , 91 ); + R0 = W [ FP + 84 ] (Z); DBGA ( R0.L , 92 ); + R0 = W [ FP + 86 ] (Z); DBGA ( R0.L , 93 ); + R0 = W [ FP + 88 ] (Z); DBGA ( R0.L , 94 ); + R0 = W [ FP + 90 ] (Z); DBGA ( R0.L , 95 ); + R0 = W [ FP + 92 ] (Z); DBGA ( R0.L , 96 ); + R0 = W [ FP + 94 ] (Z); DBGA ( R0.L , 97 ); + R0 = W [ FP + 96 ] (Z); DBGA ( R0.L , 98 ); + R0 = W [ FP + 98 ] (Z); DBGA ( R0.L , 99 ); + pass + + .data + + .dw 0 + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 10 + .dw 11 + .dw 12 + .dw 13 + .dw 14 + .dw 15 + .dw 16 + .dw 17 + .dw 18 + .dw 19 + .dw 20 + .dw 21 + .dw 22 + .dw 23 + .dw 24 + .dw 25 + .dw 26 + .dw 27 + .dw 28 + .dw 29 + .dw 30 + .dw 31 + .dw 32 + .dw 33 + .dw 34 + .dw 35 + .dw 36 + .dw 37 + .dw 38 + .dw 39 + .dw 40 + .dw 41 + .dw 42 + .dw 43 + .dw 44 + .dw 45 + .dw 46 + .dw 47 + .dw 48 + .dw 49 +middle: + .dw 50 + .dw 51 + .dw 52 + .dw 53 + .dw 54 + .dw 55 + .dw 56 + .dw 57 + .dw 58 + .dw 59 + .dw 60 + .dw 61 + .dw 62 + .dw 63 + .dw 64 + .dw 65 + .dw 66 + .dw 67 + .dw 68 + .dw 69 + .dw 70 + .dw 71 + .dw 72 + .dw 73 + .dw 74 + .dw 75 + .dw 76 + .dw 77 + .dw 78 + .dw 79 + .dw 80 + .dw 81 + .dw 82 + .dw 83 + .dw 84 + .dw 85 + .dw 86 + .dw 87 + .dw 88 + .dw 89 + .dw 90 + .dw 91 + .dw 92 + .dw 93 + .dw 94 + .dw 95 + .dw 96 + .dw 97 + .dw 98 + .dw 99 diff --git a/sim/testsuite/bfin/a30.s b/sim/testsuite/bfin/a30.s new file mode 100644 index 0000000..38dd401 --- /dev/null +++ b/sim/testsuite/bfin/a30.s @@ -0,0 +1,55 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0.L = 0.5; + R0.H = 0.5; + R1.L = 0.5; + R1.H = 0.5; + + R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); + _DBGCMPLX R2; + _DBGCMPLX R3; + + DBGA ( R2.L , 0.5 ); + DBGA ( R2.H , 0.5 ); + DBGA ( R3.L , 0 ); + DBGA ( R3.H , 0 ); + + R1.L = 0.125; + R1.H = 0.125; + + R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); + _DBGCMPLX R2; + _DBGCMPLX R3; + DBGA ( R2.L , 0.3125 ); + DBGA ( R2.H , 0.3125 ); + DBGA ( R3.L , 0.1875 ); + DBGA ( R3.H , 0.1875 ); + + R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR); + _DBGCMPLX R0; + _DBGCMPLX R1; + DBGA ( R0.L , 0.25 ); + DBGA ( R0.H , 0.25 ); + DBGA ( R1.L , 0.0625 ); + DBGA ( R1.H , 0.0625 ); + + R0 = 1; + R0 <<= 15; + R1 = R0 << 16; + r0=r0 | r1; + R1 = R0; + + R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); + + _DBGCMPLX R2; + _DBGCMPLX R3; + DBGA ( R0.L , 0x8000 ); + DBGA ( R0.H , 0x8000 ); + DBGA ( R1.L , 0x8000 ); + DBGA ( R1.H , 0x8000 ); + + pass diff --git a/sim/testsuite/bfin/a4.s b/sim/testsuite/bfin/a4.s new file mode 100644 index 0000000..d0f5ef5 --- /dev/null +++ b/sim/testsuite/bfin/a4.s @@ -0,0 +1,36 @@ +# Blackfin testcase for signbits +# mach: bfin + + .include "testutils.inc" + + start + +xx: + R0 = 1; + CALL red; + JUMP.L aa; + + .align 16 +aa: + R0 = 2; + CALL red; + JUMP.S bb; + + .align 16 +bb: + R0 = 3; + CALL red; + JUMP.S ccd; + + .align 16 +red: + RTS; + + .align 16 +ccd: + R1 = 3 (Z); + CC = R0 == R1 + if CC jump 1f; + fail +1: + pass diff --git a/sim/testsuite/bfin/a5.s b/sim/testsuite/bfin/a5.s new file mode 100644 index 0000000..d0c0143 --- /dev/null +++ b/sim/testsuite/bfin/a5.s @@ -0,0 +1,140 @@ +// ALU test program. +// Test instructions +// rL4= L+L (r2,r3); +// rH4= L+H (r2,r3) S; +// rL4= L-L (r2,r3); +// rH4= L-H (r2,r3) S; +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + +// overflow positive + R0.L = 0x0000; + R0.H = 0x7fff; + R1.L = 0x7fff; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R3.L = R0.H + R1.L (NS); + DBGA ( R3.L , 0xfffe ); + DBGA ( R3.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// overflow negative + R0.L = 0xffff; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x8000; + R3 = 0; + R7 = 0; + ASTAT = R7; + R3.H = R0.L + R1.H (NS); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate positive + R0.L = 0x0000; + R0.H = 0x7fff; + R1.L = 0x7fff; + R1.H = 0x0000; + R3 = 0; + R7 = 0; + ASTAT = R7; + R3.L = R0.H + R1.L (S); + DBGA ( R3.L , 0x7fff ); + DBGA ( R3.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// saturate negative + R0.L = 0xffff; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x8000; + R3 = 0; + R7 = 0; + ASTAT = R7; + R3.L = R0.L + R1.H (S); + DBGA ( R3.L , 0x8000 ); + DBGA ( R3.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// overflow positive with subtraction + R0.L = 0x0000; + R0.H = 0x7fff; + R1.L = 0xffff; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R3.L = R0.H - R1.L (NS); + DBGA ( R3.L , 0x8000 ); + DBGA ( R3.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// overflow negative with subtraction + R0.L = 0x8000; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x0001; + R3 = 0; + R7 = 0; + ASTAT = R7; + R3.H = R0.L - R1.H (NS); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate positive with subtraction + R0.L = 0x0000; + R0.H = 0x7fff; + R1.L = 0xffff; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R3.H = R0.H - R1.L (S); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// saturate negative with subtraction + R0.L = 0x8000; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x0001; + R3 = 0; + R7 = 0; + ASTAT = R7; + R3.H = R0.L - R1.H (S); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + + pass diff --git a/sim/testsuite/bfin/a6.s b/sim/testsuite/bfin/a6.s new file mode 100644 index 0000000..27de5d2 --- /dev/null +++ b/sim/testsuite/bfin/a6.s @@ -0,0 +1,132 @@ +// ALU test program. +// Test instructions +// r7 = +/+ (r0,r1); +// r7 = +/+ (r0,r1) s; +// r7 = +/+ (r0,r1) sx; +# mach: bfin + +.include "testutils.inc" + start + + +// one result overflows positive + R0.L = 0x0001; + R0.H = 0x0010; + R1.L = 0x7fff; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1; + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// one result overflows negative + R0.L = 0xffff; + R0.H = 0x0010; + R1.L = 0x8000; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1; + DBGA ( R7.L , 0x7fff ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// one result zero + R0.L = 0x0001; + R0.H = 0xffff; + R1.L = 0x0001; + R1.H = 0x0001; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1; + DBGA ( R7.L , 0x0002 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R5 = CC; DBGA ( R5.L , 0x1 ); + CC = AN; R5 = CC; DBGA ( R5.L , 0x0 ); + CC = V; R5 = CC; DBGA ( R5.L , 0x0 ); + CC = AC0; R5 = CC; DBGA ( R5.L , 0x0 ); + +// one result saturates positive + R0.L = 0x0001; + R0.H = 0x0010; + R1.L = 0x7fff; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1 (S); + DBGA ( R7.L , 0x7fff ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// one result saturates negative + R0.L = 0xffff; + R0.H = 0x0010; + R1.L = 0x8000; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1 (S); + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// two results saturates negative + R0.L = 0xffff; + R0.H = 0xfff0; + R1.L = 0x8000; + R1.H = 0x8000; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1 (S); + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// one result overflows positive and cross + R0.L = 0x0001; + R0.H = 0x0010; + R1.L = 0x7fff; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1 (CO); + DBGA ( R7.L , 0x0020 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// one result saturates negative and cross + R0.L = 0xffff; + R0.H = 0x0010; + R1.L = 0x8000; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1 (SCO); + DBGA ( R7.L , 0x0020 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + + pass diff --git a/sim/testsuite/bfin/a7.s b/sim/testsuite/bfin/a7.s new file mode 100644 index 0000000..4fbc5f6 --- /dev/null +++ b/sim/testsuite/bfin/a7.s @@ -0,0 +1,179 @@ +# mach: bfin + +.include "testutils.inc" + start + + R1 = 0; + R0 = 0; + R0 = R1 ^ R0; + +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 1 ); + cc = az; + r7 = cc; + dbga( r7.l, 1); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + R0 = R1 | R0; +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 1 ); + cc = az; + r7 = cc; + dbga( r7.l, 1); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + R0 = 0; + R1 = 1; + CC = R0 == R1; + +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 2 ); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + CC = BITTST ( R1 , 1 ); + +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 2 ); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + CC = ! BITTST( R1 , 1 ); +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 0x22 ); + r7 = cc; + dbga( r7.l, 1); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + R0.L = 0; + R0.H = 0x8000; + R0 >>>= 1; + _DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 0x22 ); + cc = az; + r6 = cc; + dbga( r6.l, 0); + cc = an; + r6 = cc; + dbga( r6.l, 1); + cc = av0; + r6 = cc; + dbga( r6.l, 0); + cc = av0s; + r6 = cc; + dbga( r6.l, 0); + cc = av1; + r6 = cc; + dbga( r6.l, 0); + cc = av1s; + r6 = cc; + dbga( r6.l, 0); + + R0.L = 17767; R0.H = 291; + R1.L = 52719; R1.H = -30293; + R2.L = 39612; R2.H = 22136; + R3.L = 4660; R3.H = -8464; + R4.L = 26777; R4.H = 9029; + R5.L = 9029; R5.H = 30865; + R6.L = 21554; R6.H = -26506; + R7.L = 22136; R7.H = 4660; + R0 = R0 + R0; + R1 = R0 - R1; + R2 = R0 & R2; + R3 = R0 | R3; + R4 = R0 & R4; + R5 = R0 & R5; + R6 = R0 | R6; + R7 = R0 & R7; + DBGA ( R0.l , 35534 ); DBGA( R0.h , 582 ); + DBGA( R1.l , 48351 ); DBGA ( R1.h , 30874 ); + DBGA ( R2.l , 35468 ); DBGA ( R2.h , 576 ); + DBGA ( R3.l , 39678 ); DBGA ( R3.h , 0xdef6); + DBGA ( R4.l , 2184 ); DBGA ( R4.h , 580 ); + DBGA ( R5.l , 580 ); DBGA( R5.h , 0 ); + DBGA ( R6.l, 57086 ); DBGA ( R6.h , 0x9a76 ); + DBGA ( R7.l , 584 ); DBGA ( R7.h , 516 ); + pass diff --git a/sim/testsuite/bfin/a8.s b/sim/testsuite/bfin/a8.s new file mode 100644 index 0000000..23f3464 --- /dev/null +++ b/sim/testsuite/bfin/a8.s @@ -0,0 +1,41 @@ +# mach: bfin + +.include "testutils.inc" + start + +// xh, h, xb, b + R0.L = 32898; R0.H = 1; + R1.L = 49346; R1.H = 3; + R2.L = 6; R2.H = -1; + R3.L = 129; R3.H = 7; + R4.L = 4; R4.H = 0; + R5.L = 5; R5.H = 0; + R6.L = 6; R6.H = 0; + R7.L = 7; R7.H = 0; + R4 = R0.L (X); + +// _DBG ASTAT; R7 = ASTAT;DBGA ( R7.L , 2 ); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + R5 = R0.L; + R6 = R1.B (X); + R7 = R1.B; + DBGA ( R4.l , 32898 ); DBGA ( R4.h , 0xffff); + pass diff --git a/sim/testsuite/bfin/a9.s b/sim/testsuite/bfin/a9.s new file mode 100644 index 0000000..525b17f --- /dev/null +++ b/sim/testsuite/bfin/a9.s @@ -0,0 +1,219 @@ +// ALU test program. +// Test 32 bit MAX, MIN, ABS instructions +# mach: bfin + +.include "testutils.inc" + start + + +// MAX +// first operand is larger, so AN=0 + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// second operand is larger, so AN=1 + R0.L = 0x0000; + R0.H = 0x0000; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// first operand is larger, check correct output with overflow + R0.L = 0xffff; + R0.H = 0x7fff; + R1.L = 0xffff; + R1.H = 0xffff; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// second operand is larger, no overflow here + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0xffff; + R1.H = 0x7fff; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// second operand is larger, overflow + R0.L = 0xffff; + R0.H = 0x800f; + R1.L = 0xffff; + R1.H = 0x7fff; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0S; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1S; R7 = CC; DBGA ( R7.L , 0x0 ); + +// both operands equal + R0.L = 0x0080; + R0.H = 0x8000; + R1.L = 0x0080; + R1.H = 0x8000; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0x0080 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// MIN +// second operand is smaller + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MIN ( R0 , R1 ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// first operand is smaller + R0.L = 0x0001; + R0.H = 0x8000; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MIN ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// first operand is smaller, overflow + R0.L = 0x0001; + R0.H = 0x8000; + R1.L = 0x0000; + R1.H = 0x0ff0; + R7 = MIN ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// equal operands + R0.L = 0x0001; + R0.H = 0x8000; + R1.L = 0x0001; + R1.H = 0x8000; + R7 = MIN ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// ABS + R0.L = 0x0001; + R0.H = 0x8000; + R7 = ABS R0; + _DBG R7; + _DBG ASTAT; + R6 = ASTAT; + + _DBG R6; + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); +//CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); +//CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); +//CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); +//CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); +//CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); +//CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0001; + R0.H = 0x0000; + R7 = ABS R0; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0000; + R0.H = 0x8000; + R7 = ABS R0; + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R7 = ABS R0; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0000; + R0.H = 0x0000; + R7 = ABS R0; + _DBG R7; + _DBG ASTAT; + R6 = ASTAT; + _DBG R6; + + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = VS; R6 = CC; DBGA (R6.L, 0x1); + CC = AZ; R6 = CC; DBGA (R6.L, 0x1); + + pass diff --git a/sim/testsuite/bfin/abs-2.S b/sim/testsuite/bfin/abs-2.S new file mode 100644 index 0000000..1e768b0 --- /dev/null +++ b/sim/testsuite/bfin/abs-2.S @@ -0,0 +1,42 @@ +# Blackfin testcase for ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x8765; + R0.L = 0x4321; + R1 = ABS R0; + R7 = ASTAT; + R2.H = 0x789a; + R2.L = 0xbcdf; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AN V V_COPY */ + R3.H = HI(_AZ|_AN|_V|_V_COPY); + R3.L = LO(_AZ|_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: */ + R3.H = HI(0); + R3.L = LO(0); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/abs-3.S b/sim/testsuite/bfin/abs-3.S new file mode 100644 index 0000000..44ba765 --- /dev/null +++ b/sim/testsuite/bfin/abs-3.S @@ -0,0 +1,42 @@ +# Blackfin testcase for ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x0; + R0.L = 0x0; + R1 = ABS R0; + R7 = ASTAT; + R2.H = 0x0; + R2.L = 0x0; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN V V_COPY */ + R3.H = HI(_AN|_V|_V_COPY); + R3.L = LO(_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ */ + R3.H = HI(_AZ); + R3.L = LO(_AZ); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/abs-4.S b/sim/testsuite/bfin/abs-4.S new file mode 100644 index 0000000..0e691e0 --- /dev/null +++ b/sim/testsuite/bfin/abs-4.S @@ -0,0 +1,42 @@ +# Blackfin testcase for ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x8000; + R0.L = 0x0; + R1 = ABS R0; + R7 = ASTAT; + R2.H = 0x7fff; + R2.L = 0xffff; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AN V V_COPY */ + R3.H = HI(_AZ|_AN); + R3.L = LO(_AZ|_AN); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: V V_COPY VS */ + R3.H = HI(_V|_V_COPY|_VS); + R3.L = LO(_V|_V_COPY|_VS); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/abs.S b/sim/testsuite/bfin/abs.S new file mode 100644 index 0000000..1425d42 --- /dev/null +++ b/sim/testsuite/bfin/abs.S @@ -0,0 +1,42 @@ +# Blackfin testcase for ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x1234; + R0.L = 0x5678; + R1 = ABS R0; + R7 = ASTAT; + R2.H = 0x1234; + R2.L = 0x5678; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AN V V_COPY */ + R3.H = HI(_AZ|_AN|_V|_V_COPY); + R3.L = LO(_AZ|_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: */ + R3.H = HI(0); + R3.L = LO(0); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/abs_acc.s b/sim/testsuite/bfin/abs_acc.s new file mode 100644 index 0000000..99ed052 --- /dev/null +++ b/sim/testsuite/bfin/abs_acc.s @@ -0,0 +1,224 @@ +// ACP 5.7 ABS(A1) sets AV0 +# mach: bfin + +.include "testutils.inc" + start + + r1=0x80 (z); + A0=0; + A0.x=r1; + A0=abs A0; + _DBG astat; +//r7=astat; +//dbga (r7.h, 0x3); +//dbga (r7.l, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 1); + cc = av0s; + r7 = cc; + dbga( r7.l, 1); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + r6=A0.x; + dbga (r6.l, 0x7f); + + r1=0x80 (z); + A1=0; + A1.x=r1; + A1=abs A1; + _DBG astat; +//r7=astat; +//dbga (r7.h, 0xf); +//dbga (r7.l, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 1); + cc = av0s; + r7 = cc; + dbga( r7.l, 1); + cc = av1; + r7 = cc; + dbga( r7.l, 1); + cc = av1s; + r7 = cc; + dbga( r7.l, 1); + + r6=A1.x; + dbga (r6.l, 0x7f); + + r7=0; + astat=r7; + r1=0x80 (z); + A1=0; + A1.x=r1; + A0 = abs A1; + _DBG astat; +//r7=astat; +//dbga (r7.h, 0x3); +//dbga (r7.l, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 1); + cc = av0s; + r7 = cc; + dbga( r7.l, 1); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + r6=A0.x; + dbga (r6.l, 0x7f); + + r7=0; + astat=r7; + r1=0x80 (z); + A0=0; + A0.x=r1; + A1 = abs A0; + _DBG astat; +//r7=astat; +//dbga (r7.h, 0xc); +//dbga (r7.l, 0x0); + cc = az; + r3 = cc; + dbga( r3.l, 0); + cc = an; + r3 = cc; + dbga( r3.l, 0); + cc = av0; + r3 = cc; + dbga( r3.l, 0); + cc = av0s; + r3 = cc; + dbga( r3.l, 0); + cc = av1; + r3 = cc; + dbga( r3.l, 1); + cc = av1s; + r3 = cc; + dbga( r3.l, 1); + + r6=A1.x; + dbga (r6.l, 0x7f); + + r7=0; + astat=r7; + r1=0x80 (z); + A1=0; + A1.x=r1; + A0.x=r6; + _DBG A1; + _DBG A0; + A1=abs A1, A0=abs A0; + _DBG ASTAT; +//r7=astat; +//dbga (r7.h, 0xc); +//dbga (r7.l, 0x0); + cc = az; + r4 = cc; + dbga( r4.l, 0); + cc = an; + r4 = cc; + dbga( r4.l, 0); + cc = av0; + r4 = cc; + dbga( r4.l, 0); + cc = av0s; + r4 = cc; + dbga( r4.l, 0); + cc = av1; + r4 = cc; + dbga( r4.l, 1); + cc = av1s; + r4 = cc; + dbga( r4.l, 1); + + r7=0; + astat=r7; + r1=0x80 (z); + A1=0; + A1.x=r1; + A0 = A1; + A1=abs A1, A0=abs A0; + _DBG ASTAT; +//r7=astat; +//dbga (r7.h, 0xf); +//dbga (r7.l, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 1); + cc = av0s; + r7 = cc; + dbga( r7.l, 1); + cc = av1; + r7 = cc; + dbga( r7.l, 1); + cc = av1s; + r7 = cc; + dbga( r7.l, 1); + +// ACP 5.8 ABS sometimes sets AN + + r7=0; + astat=r7; + r0=1; + r1=abs r0; + _DBG r0; + _DBG r1; + _DBG astat; +//r7=astat; +//dbga (r7.h, 0x0); +//dbga (r7.l, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + pass; diff --git a/sim/testsuite/bfin/acc-rot.s b/sim/testsuite/bfin/acc-rot.s new file mode 100644 index 0000000..ccf307c --- /dev/null +++ b/sim/testsuite/bfin/acc-rot.s @@ -0,0 +1,129 @@ +# Blackfin testcase for Accumulator Rotates (ROT) +# mach: bfin + + .include "testutils.inc" + + .macro atest_setup acc:req, val_x:req, val_w:req, cc:req, shift:req + imm32 R0, \val_w + imm32 R1, \val_x + R2 = \cc; + R3 = \shift + \acc\().W = R0; + \acc\().X = R1; + CC = R2; + .endm + + .macro atest_check acc:req, exp_x:req, exp_w:req, expcc:req + R7 = CC; + CHECKREG R7, \expcc; + + R2 = \acc\().W; + CHECKREG R2, \exp_w; + + R6 = \acc\().X; + R6 = R6.B (z); + CHECKREG R6, \exp_x; + .endm + + .macro _atest acc:req, val_x:req, val_w:req, cc:req, shift:req, exp_x:req, exp_w:req, expcc:req + atest_setup \acc, \val_x, \val_w, \cc, \shift + _DBG \acc; + \acc = ROT \acc BY \shift; + atest_check \acc, \exp_x, \exp_w, \expcc + + atest_setup \acc, \val_x, \val_w, \cc, \shift + \acc = ROT \acc BY R3.L; + atest_check \acc, \exp_x, \exp_w, \expcc + .endm + + .macro atest val_x:req, val_w:req, cc:req, shift:req, exp_x:req, exp_w:req, expcc:req + _atest A0, \val_x, \val_w, \cc, \shift, \exp_x, \exp_w, \expcc + _atest A1, \val_x, \val_w, \cc, \shift, \exp_x, \exp_w, \expcc + .endm + + start + + atest 0x00, 0x00000000, 0, 0, 0x00, 0x00000000, 0 + atest 0xa5, 0xa5a5a5a5, 0, 0, 0xa5, 0xa5a5a5a5, 0 + atest 0x00, 0x00000000, 1, 0, 0x00, 0x00000000, 1 + atest 0xa5, 0xa5a5a5a5, 1, 0, 0xa5, 0xa5a5a5a5, 1 + atest 0x00, 0x00000000, 0, 10, 0x00, 0x00000000, 0 + + atest 0x00, 0x0000000f, 0, 4, 0x00, 0x000000f0, 0 + atest 0x00, 0x0000000f, 1, 4, 0x00, 0x000000f8, 0 + atest 0x00, 0x0000000f, 0, 20, 0x00, 0x00f00000, 0 + atest 0x00, 0x0000000f, 1, 20, 0x00, 0x00f80000, 0 + atest 0x00, 0x0000000f, 0, -5, 0xf0, 0x00000000, 0 + atest 0x00, 0x0000000f, 1, -5, 0xf8, 0x00000000, 0 + atest 0x00, 0x0000000f, 0, -1, 0x00, 0x00000007, 1 + atest 0x00, 0x0000000f, 1, -1, 0x80, 0x00000007, 1 + + atest 0xff, 0xffffffff, 1, 10, 0xff, 0xffffffff, 1 + atest 0x11, 0x11111110, 0, -5, 0x00, 0x88888888, 1 + + atest 0x1f, 0x2e3d4c5b, 1, 0, 0x1f, 0x2e3d4c5b, 1 + atest 0x1f, 0x2e3d4c5b, 1, 1, 0x3e, 0x5c7a98b7, 0 + atest 0x1f, 0x2e3d4c5b, 1, 2, 0x7c, 0xb8f5316e, 0 + atest 0x1f, 0x2e3d4c5b, 1, 3, 0xf9, 0x71ea62dc, 0 + atest 0x1f, 0x2e3d4c5b, 1, 4, 0xf2, 0xe3d4c5b8, 1 + atest 0x1f, 0x2e3d4c5b, 1, 5, 0xe5, 0xc7a98b71, 1 + atest 0x1f, 0x2e3d4c5b, 1, 6, 0xcb, 0x8f5316e3, 1 + atest 0x1f, 0x2e3d4c5b, 1, 7, 0x97, 0x1ea62dc7, 1 + atest 0x1f, 0x2e3d4c5b, 1, 8, 0x2e, 0x3d4c5b8f, 1 + atest 0x1f, 0x2e3d4c5b, 1, 9, 0x5c, 0x7a98b71f, 0 + atest 0x1f, 0x2e3d4c5b, 1, 10, 0xb8, 0xf5316e3e, 0 + atest 0x1f, 0x2e3d4c5b, 1, 11, 0x71, 0xea62dc7c, 1 + atest 0x1f, 0x2e3d4c5b, 1, 12, 0xe3, 0xd4c5b8f9, 0 + atest 0x1f, 0x2e3d4c5b, 1, 13, 0xc7, 0xa98b71f2, 1 + atest 0x1f, 0x2e3d4c5b, 1, 14, 0x8f, 0x5316e3e5, 1 + atest 0x1f, 0x2e3d4c5b, 1, 15, 0x1e, 0xa62dc7cb, 1 + atest 0x1f, 0x2e3d4c5b, 1, 16, 0x3d, 0x4c5b8f97, 0 + atest 0x1f, 0x2e3d4c5b, 1, 17, 0x7a, 0x98b71f2e, 0 + atest 0x1f, 0x2e3d4c5b, 1, 18, 0xf5, 0x316e3e5c, 0 + atest 0x1f, 0x2e3d4c5b, 1, 19, 0xea, 0x62dc7cb8, 1 + atest 0x1f, 0x2e3d4c5b, 1, 20, 0xd4, 0xc5b8f971, 1 + atest 0x1f, 0x2e3d4c5b, 1, 21, 0xa9, 0x8b71f2e3, 1 + atest 0x1f, 0x2e3d4c5b, 1, 22, 0x53, 0x16e3e5c7, 1 + atest 0x1f, 0x2e3d4c5b, 1, 23, 0xa6, 0x2dc7cb8f, 0 + atest 0x1f, 0x2e3d4c5b, 1, 24, 0x4c, 0x5b8f971e, 1 + atest 0x1f, 0x2e3d4c5b, 1, 25, 0x98, 0xb71f2e3d, 0 + atest 0x1f, 0x2e3d4c5b, 1, 26, 0x31, 0x6e3e5c7a, 1 + atest 0x1f, 0x2e3d4c5b, 1, 27, 0x62, 0xdc7cb8f5, 0 + atest 0x1f, 0x2e3d4c5b, 1, 28, 0xc5, 0xb8f971ea, 0 + atest 0x1f, 0x2e3d4c5b, 1, 29, 0x8b, 0x71f2e3d4, 1 + atest 0x1f, 0x2e3d4c5b, 1, 30, 0x16, 0xe3e5c7a9, 1 + atest 0x1f, 0x2e3d4c5b, 1, 31, 0x2d, 0xc7cb8f53, 0 + atest 0x1f, 0x2e3d4c5b, 1, -1, 0x8f, 0x971ea62d, 1 + atest 0x1f, 0x2e3d4c5b, 1, -2, 0xc7, 0xcb8f5316, 1 + atest 0x1f, 0x2e3d4c5b, 1, -3, 0xe3, 0xe5c7a98b, 0 + atest 0x1f, 0x2e3d4c5b, 1, -4, 0x71, 0xf2e3d4c5, 1 + atest 0x1f, 0x2e3d4c5b, 1, -5, 0xb8, 0xf971ea62, 1 + atest 0x1f, 0x2e3d4c5b, 1, -6, 0xdc, 0x7cb8f531, 0 + atest 0x1f, 0x2e3d4c5b, 1, -7, 0x6e, 0x3e5c7a98, 1 + atest 0x1f, 0x2e3d4c5b, 1, -8, 0xb7, 0x1f2e3d4c, 0 + atest 0x1f, 0x2e3d4c5b, 1, -9, 0x5b, 0x8f971ea6, 0 + atest 0x1f, 0x2e3d4c5b, 1, -10, 0x2d, 0xc7cb8f53, 0 + atest 0x1f, 0x2e3d4c5b, 1, -11, 0x16, 0xe3e5c7a9, 1 + atest 0x1f, 0x2e3d4c5b, 1, -12, 0x8b, 0x71f2e3d4, 1 + atest 0x1f, 0x2e3d4c5b, 1, -13, 0xc5, 0xb8f971ea, 0 + atest 0x1f, 0x2e3d4c5b, 1, -14, 0x62, 0xdc7cb8f5, 0 + atest 0x1f, 0x2e3d4c5b, 1, -15, 0x31, 0x6e3e5c7a, 1 + atest 0x1f, 0x2e3d4c5b, 1, -16, 0x98, 0xb71f2e3d, 0 + atest 0x1f, 0x2e3d4c5b, 1, -17, 0x4c, 0x5b8f971e, 1 + atest 0x1f, 0x2e3d4c5b, 1, -18, 0xa6, 0x2dc7cb8f, 0 + atest 0x1f, 0x2e3d4c5b, 1, -19, 0x53, 0x16e3e5c7, 1 + atest 0x1f, 0x2e3d4c5b, 1, -20, 0xa9, 0x8b71f2e3, 1 + atest 0x1f, 0x2e3d4c5b, 1, -21, 0xd4, 0xc5b8f971, 1 + atest 0x1f, 0x2e3d4c5b, 1, -22, 0xea, 0x62dc7cb8, 1 + atest 0x1f, 0x2e3d4c5b, 1, -23, 0xf5, 0x316e3e5c, 0 + atest 0x1f, 0x2e3d4c5b, 1, -24, 0x7a, 0x98b71f2e, 0 + atest 0x1f, 0x2e3d4c5b, 1, -25, 0x3d, 0x4c5b8f97, 0 + atest 0x1f, 0x2e3d4c5b, 1, -26, 0x1e, 0xa62dc7cb, 1 + atest 0x1f, 0x2e3d4c5b, 1, -27, 0x8f, 0x5316e3e5, 1 + atest 0x1f, 0x2e3d4c5b, 1, -28, 0xc7, 0xa98b71f2, 1 + atest 0x1f, 0x2e3d4c5b, 1, -29, 0xe3, 0xd4c5b8f9, 0 + atest 0x1f, 0x2e3d4c5b, 1, -30, 0x71, 0xea62dc7c, 1 + atest 0x1f, 0x2e3d4c5b, 1, -31, 0xb8, 0xf5316e3e, 0 + atest 0x1f, 0x2e3d4c5b, 1, -32, 0x5c, 0x7a98b71f, 0 + + pass diff --git a/sim/testsuite/bfin/acp5_19.s b/sim/testsuite/bfin/acp5_19.s new file mode 100644 index 0000000..74e7552 --- /dev/null +++ b/sim/testsuite/bfin/acp5_19.s @@ -0,0 +1,12 @@ +# mach: bfin + +.include "testutils.inc" + start + + r0.h=0xa5a5; + r0.l=0xffff; + a0 = 0; + r0=a0.x; + dbga(r0.h, 0x0000); + dbga(r0.l, 0x0000); + pass; diff --git a/sim/testsuite/bfin/acp5_4.s b/sim/testsuite/bfin/acp5_4.s new file mode 100644 index 0000000..993f7ba --- /dev/null +++ b/sim/testsuite/bfin/acp5_4.s @@ -0,0 +1,39 @@ +// test RND setting AZ +# mach: bfin + +.include "testutils.inc" + start + + +// result is zero with overflow ==> AZ, therefore, is not set + R0.L = 0x8000; + R0 = R0.L (X); + R1.L = R0 (RND); + CC = AZ; R7 = CC; + DBGA(R1.L, 0); + DBGA ( R7.L , 0x1 ); + +// No Overflow, result is zero, AZ is set + R0 = 1 (X); + R1.L = r0 (RND); + CC = AZ; R7 = CC; + DBGA(R1.L, 0); + DBGA ( R7.L , 0x1 ); + +// result should be 1 + R0.L = 0x8000; + R0.H = 0; + R1.L = R0 (RND); + CC = AZ; R7 = CC; + DBGA(R1.L, 1); + DBGA ( R7.L , 0x0 ); + +// Result should be non-zero + R0.H = 0x7ff0; + R0.L = 0x8000; + R1.L = R0 (RND); + CC = AZ; R7 = CC; + DBGA(R1.L, 0x7ff1); + DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/bfin/add_imm7.s b/sim/testsuite/bfin/add_imm7.s new file mode 100644 index 0000000..31f1538 --- /dev/null +++ b/sim/testsuite/bfin/add_imm7.s @@ -0,0 +1,38 @@ +# mach: bfin + +.include "testutils.inc" + start + + r0 = 0 + ASTAT = r0; + + r2=-7; + r2+=-63; + _dbg r2; + _dbg astat; + r7=astat; + dbga ( r7.h, 0x0); + dbga ( r7.l, 0x1006); + + r7=0; + astat=r7; + r2=64; + r2+=-64; + _dbg r2; + _dbg astat; + r7=astat; + dbga ( r7.h, 0x0); + dbga ( r7.l, 0x1005); + + r7=0; + astat=r7; + r2=0; + r2.h=0x8000; + r2+=-63; + _dbg astat; + _dbg r2; + r7=astat; + dbga ( r7.h, 0x0300); + dbga ( r7.l, 0x100c); + + pass diff --git a/sim/testsuite/bfin/add_shift.S b/sim/testsuite/bfin/add_shift.S new file mode 100644 index 0000000..8a8bf63 --- /dev/null +++ b/sim/testsuite/bfin/add_shift.S @@ -0,0 +1,53 @@ +// ACP 5.6 Flags for dreg=(dreg+dreg)<<1,2 +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + + r1=0; + ASTAT = R1; + r2=0; + r2.h=0x4000; + r2=(r2+r1)<<2; + dbga (r2.l,0x0); + dbga (r2.h,0x0); + _dbg ASTAT; + r7=ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AZ) + + r2=0; + r2.h=0x4000; + r2=(r2+r1)<<1; + dbga (r2.l,0x0); + dbga (r2.h,0x8000); + _dbg ASTAT; + r7=ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AN) + + r1=0; + r1.h=0xd300; + r2=0; + r2.h=0xb700; + r2=(r2+r1)<<1; + dbga (r2.l,0x0); + dbga (r2.h,0x1400); + _dbg ASTAT; + r7=ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY) + + r0 = 1; + r0 <<= 31; // r0 should be 0x80000000 + r7 = 0; + ASTAT = r7; + _dbg r0; + r1 = r0; + _dbg r1; + r1 = (r1 + r0) << 1; // add overflows to zero, no shift overflow + _dbg r1; + _dbg ASTAT; + r7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AZ); + + pass diff --git a/sim/testsuite/bfin/add_sub_acc.s b/sim/testsuite/bfin/add_sub_acc.s new file mode 100644 index 0000000..84416d0 --- /dev/null +++ b/sim/testsuite/bfin/add_sub_acc.s @@ -0,0 +1,123 @@ +// ACP 5.9 A0 -= A1 doesn't set flags +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + R0 = 0x0; + astat=r0; + A0.w = R0; + R0.L = 0x0080; + A0.x = R0; + R1 = 1; + + _DBG A0; + _DBG A1; + + A0 -= A1; + _dbg A0; + _dbg ASTAT; + r7=astat; + dbga (r7.h, 0x0); + dbga (r7.l, 0x1006); + + A1 = A0 = 0; + R0 = 0x1 (z); + astat=r0; + A0.w = R0; + R0.L = 0x0080; + A0.x = R0; + R1 = 1; + + _DBG A0; + _DBG A1; + + A0 -= A1; + _dbg A0; + _dbg ASTAT; + r7=astat; + dbga (r7.h, 0x0); + dbga (r7.l, 0x1006); + + A1 = A0 = 0; + R0 = 0x0; + astat=r0; + A0.w = R0; + R0.L = 0x0080; + A0.x = R0; + R1 = 1; + A1 = R1; + + _DBG A0; + _DBG A1; + + A0 -= A1; + _dbg A0; + _dbg ASTAT; + r7=astat; + dbga (r7.h, 0x3); + dbga (r7.l, 0x1006); + + A1 = A0 = 0; + R0 = 0x1 (z); + astat=r0; + A0.w = R0; + R0.L = 0x0080; + A0.x = R0; + R1 = 2 (z); + A1 = R1; + + _DBG A0; + _DBG A1; + + A0 -= A1; + _dbg A0; + _dbg ASTAT; + r7=astat; + dbga (r7.h, 0x3); + dbga (r7.l, 0x1006); + + # + + A1 = A0 = 0; + R0 = 0x0; + astat=r0; + R0.L=0xffff; + R0.H=0xffff; + A0.w = R0; + R1=0x7f; + A0.x = R1; + A1.x = R1; + A1.w = R0; + + _DBG A0; + _DBG A1; + + A0 += A1; + _dbg A0; + _dbg ASTAT; + r7=astat; + dbga (r7.h, 0x3); + dbga (r7.l, 0x0); + + A1 = A0 = 0; + R0 = 0x0; + astat=r0; + A0.w = R0; + R1=0x80; + A0.x = R1; + A1.x = R1; + A1.w = R0; + + _DBG A0; + _DBG A1; + + A0 += A1; + _dbg A0; + _dbg ASTAT; + r7=astat; + dbga (r7.h, 0x3); + dbga (r7.l, 0x1006); + + pass; diff --git a/sim/testsuite/bfin/addsub_flags.S b/sim/testsuite/bfin/addsub_flags.S new file mode 100644 index 0000000..78319c5 --- /dev/null +++ b/sim/testsuite/bfin/addsub_flags.S @@ -0,0 +1,107 @@ +// ACP 5.17 Dual ALU ops +// AZ, AN, AC0, AC1, V and VS are affected +// AV0, AV0S, AV1, AV1S are unaffected +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + A0 = A1 = 0; + + r0=0; + r0.h=0x7fff; + r2=0; + r2.h=0x7000; + r1=r0+r2,r3=r0-r2; + r7=astat; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); + + a1=r2; + a0=r0; + r1=a0+a1, r3=a0-a1; + r7=astat; + _dbg a0; + _dbg a1; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); + + a0=r2; + a1=r0; + r1=a1+a0, r3=a1-a0; + r7=astat; + _dbg a0; + _dbg a1; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); + + r0.h=0xafff; + r2.h=0xa000; + a1=r2; + a0=r0; + r1=a0+a1, r3=a0-a1; + r7=astat; + _dbg a0; + _dbg a1; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); + + r1=a0+a1, r3=a0-a1 (s); + r7=astat; + _dbg a0; + _dbg a1; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1|_AN); + + r0.h=0xafff; + r2.h=0xa000; + a0=r2; + a1=r0; + r1=a1+a0, r3=a1-a0; + r7=astat; + _dbg a0; + _dbg a1; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); + + r1=a1+a0, r3=a1-a0 (s); + r7=astat; + _dbg a0; + _dbg a1; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1|_AN); + + r2.h=0x8001; + r1=r0+r2,r3=r0-r2; + _dbg r1; + _dbg r3; + _dbg astat; + r7=astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); + + r2.h=0x8000; + r1=r0+r2,r3=r0-r2; + r7=astat; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); + + pass; diff --git a/sim/testsuite/bfin/algnbug1.s b/sim/testsuite/bfin/algnbug1.s new file mode 100644 index 0000000..be0363b --- /dev/null +++ b/sim/testsuite/bfin/algnbug1.s @@ -0,0 +1,38 @@ +# mach: bfin + +.include "testutils.inc" + start + + + loadsym P0, blocka; + I0 = P0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + I0 = P0; + M0 = 1 (X); + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + pass + + .data + .align 8 +blocka: + .dw 0xfeff + .dw 0xfcfd + .dw 0xfafb + .dw 0xf8f9 diff --git a/sim/testsuite/bfin/algnbug2.s b/sim/testsuite/bfin/algnbug2.s new file mode 100644 index 0000000..b06d5ad --- /dev/null +++ b/sim/testsuite/bfin/algnbug2.s @@ -0,0 +1,69 @@ +# mach: bfin + +.include "testutils.inc" + start + + + M0 = 1 (X); + loadsym I0, blocka; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + loadsym I0, blocka; + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + loadsym I0, blocka; + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + loadsym I0, blocka; + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + loadsym I0, blocka; + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + pass + + .data; + .align 8 +blocka: + .dw 0xfeff + .dw 0xfcfd + .dw 0xfafb + .dw 0xf8f9 diff --git a/sim/testsuite/bfin/allinsn.exp b/sim/testsuite/bfin/allinsn.exp new file mode 100644 index 0000000..aa304ea --- /dev/null +++ b/sim/testsuite/bfin/allinsn.exp @@ -0,0 +1,43 @@ +# Analog Devices Blackfin simulator testsuite + +if [istarget bfin-*-elf] { + # all machines + set all_machs "bfin" + + # See if we have a preprocessor available. + if { [target_compile $srcdir/$subdir/usp.S compilercheck.x "preprocess" \ + [list "incdir=$srcdir/$subdir"]] == "" } { + set has_cpp 1 + } { + verbose -log "Can't execute preprocessor" + set has_cpp 0 + } + + # See if we have a compiler available. + if { [target_compile $srcdir/$subdir/argc.c compilercheck.x "executable" \ + [list "incdir=$srcdir/$subdir" "additional_flags=-msim"]] == "" } { + set has_cc 1 + } { + verbose -log "Can't execute C compiler" + set has_cc 0 + } + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.\[csS\]]] { + # If we don't have a compiler available, skip tests :(. + if { $has_cpp == 0 && [string match "*.S" $src] } { + untested $src + continue + } + if { $has_cc == 0 && [string match "*.c" $src] } { + untested $src + continue + } + + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/bfin/argc.c b/sim/testsuite/bfin/argc.c new file mode 100644 index 0000000..21f1fef --- /dev/null +++ b/sim/testsuite/bfin/argc.c @@ -0,0 +1,31 @@ +/* Basic argc/argv tests. +# mach: bfin +# cc: -msim +# progopts: a bb ccc dddd +*/ + +int streq(const char *s1, const char *s2) +{ + int i = 0; + + while (s1[i] && s2[i] && s1[i] == s2[i]) + ++i; + + return s1[i] == '\0' && s2[i] == '\0'; +} + +int main(int argc, char *argv[]) +{ + if (argc != 5) + return 1; + if (!streq(argv[1], "a")) + return 2; + if (!streq(argv[2], "bb")) + return 2; + if (!streq(argv[3], "ccc")) + return 2; + if (!streq(argv[4], "dddd")) + return 2; + puts("pass"); + return 0; +} diff --git a/sim/testsuite/bfin/ashift.s b/sim/testsuite/bfin/ashift.s new file mode 100644 index 0000000..de0b36e --- /dev/null +++ b/sim/testsuite/bfin/ashift.s @@ -0,0 +1,323 @@ +# Blackfin testcase for ashift +# mach: bfin + + .include "testutils.inc" + + .macro ashift_test in:req, shift:req, out:req, opt + r0 = \in (Z); + r2.L = \shift; + r2.h = ASHIFT R0.L BY R2.L \opt; + DBGA (r2.h, \out); + .endm + + start + + /* + * 16-bit ashift and lshift uses a 6-bit signed magnitude, which + * gives a range from -32 to 31. In the case where the magnitude + * is -32, make sure the answer is correct. + */ + +ashift_test 0x8001, 33, 0xffff; +ashift_test 0x8001, 32, 0xffff; +ashift_test 0x8001, 31, 0x0000; +ashift_test 0x8001, 30, 0x0000; +ashift_test 0x8001, 29, 0x0000; +ashift_test 0x8001, 28, 0x0000; +ashift_test 0x8001, 27, 0x0000; +ashift_test 0x8001, 26, 0x0000; +ashift_test 0x8001, 25, 0x0000; +ashift_test 0x8001, 24, 0x0000; +ashift_test 0x8001, 23, 0x0000; +ashift_test 0x8001, 22, 0x0000; +ashift_test 0x8001, 21, 0x0000; +ashift_test 0x8001, 20, 0x0000; +ashift_test 0x8001, 19, 0x0000; +ashift_test 0x8001, 18, 0x0000; +ashift_test 0x8001, 17, 0x0000; +ashift_test 0x8001, 16, 0x0000; +ashift_test 0x8001, 15, 0x8000; +ashift_test 0x8001, 14, 0x4000; +ashift_test 0x8001, 13, 0x2000; +ashift_test 0x8001, 12, 0x1000; +ashift_test 0x8001, 11, 0x0800; +ashift_test 0x8001, 10, 0x0400; +ashift_test 0x8001, 9, 0x0200; +ashift_test 0x8001, 8, 0x0100; +ashift_test 0x8001, 7, 0x0080; +ashift_test 0x8001, 6, 0x0040; +ashift_test 0x8001, 5, 0x0020; +ashift_test 0x8001, 4, 0x0010; +ashift_test 0x8001, 3, 0x0008; +ashift_test 0x8001, 2, 0x0004; +ashift_test 0x8001, 1, 0x0002; +ashift_test 0x8001, 0, 0x8001; +ashift_test 0x8001, -1, 0xc000; +ashift_test 0x8001, -2, 0xe000; +ashift_test 0x8001, -3, 0xf000; +ashift_test 0x8001, -4, 0xf800; +ashift_test 0x8001, -5, 0xfc00; +ashift_test 0x8001, -6, 0xfe00; +ashift_test 0x8001, -7, 0xff00; +ashift_test 0x8001, -8, 0xff80; +ashift_test 0x8001, -9, 0xffc0; +ashift_test 0x8001, -10, 0xffe0; +ashift_test 0x8001, -11, 0xfff0; +ashift_test 0x8001, -12, 0xfff8; +ashift_test 0x8001, -13, 0xfffc; +ashift_test 0x8001, -14, 0xfffe; +ashift_test 0x8001, -15, 0xffff; +ashift_test 0x8001, -16, 0xffff; +ashift_test 0x8001, -17, 0xffff; +ashift_test 0x8001, -18, 0xffff; +ashift_test 0x8001, -19, 0xffff; +ashift_test 0x8001, -20, 0xffff; +ashift_test 0x8001, -21, 0xffff; +ashift_test 0x8001, -22, 0xffff; +ashift_test 0x8001, -23, 0xffff; +ashift_test 0x8001, -24, 0xffff; +ashift_test 0x8001, -25, 0xffff; +ashift_test 0x8001, -26, 0xffff; +ashift_test 0x8001, -27, 0xffff; +ashift_test 0x8001, -28, 0xffff; +ashift_test 0x8001, -29, 0xffff; +ashift_test 0x8001, -30, 0xffff; +ashift_test 0x8001, -31, 0xffff; +ashift_test 0x8001, -32, 0xffff; +ashift_test 0x8001, -33, 0x0; +ashift_test 0x8001, -34, 0x0; + +ashift_test 0x8001, 33, 0xffff, (S); +ashift_test 0x8001, 32, 0xffff, (S); +ashift_test 0x8001, 31, 0x8000, (S); +ashift_test 0x8001, 30, 0x8000, (S); +ashift_test 0x8001, 29, 0x8000, (S); +ashift_test 0x8001, 28, 0x8000, (S); +ashift_test 0x8001, 27, 0x8000, (S); +ashift_test 0x8001, 26, 0x8000, (S); +ashift_test 0x8001, 25, 0x8000, (S); +ashift_test 0x8001, 24, 0x8000, (S); +ashift_test 0x8001, 23, 0x8000, (S); +ashift_test 0x8001, 22, 0x8000, (S); +ashift_test 0x8001, 21, 0x8000, (S); +ashift_test 0x8001, 20, 0x8000, (S); +ashift_test 0x8001, 19, 0x8000, (S); +ashift_test 0x8001, 18, 0x8000, (S); +ashift_test 0x8001, 17, 0x8000, (S); +ashift_test 0x8001, 16, 0x8000, (S); +ashift_test 0x8001, 15, 0x8000, (S); +ashift_test 0x8001, 14, 0x8000, (S); +ashift_test 0x8001, 13, 0x8000, (S); +ashift_test 0x8001, 12, 0x8000, (S); +ashift_test 0x8001, 11, 0x8000, (S); +ashift_test 0x8001, 10, 0x8000, (S); +ashift_test 0x8001, 9, 0x8000, (S); +ashift_test 0x8001, 8, 0x8000, (S); +ashift_test 0x8001, 7, 0x8000, (S); +ashift_test 0x8001, 6, 0x8000, (S); +ashift_test 0x8001, 5, 0x8000, (S); +ashift_test 0x8001, 4, 0x8000, (S); +ashift_test 0x8001, 3, 0x8000, (S); +ashift_test 0x8001, 2, 0x8000, (S); +ashift_test 0x8001, 1, 0x8000, (S); +ashift_test 0x8001, 0, 0x8001, (S); +ashift_test 0x8001, -1, 0xc000, (S); +ashift_test 0x8001, -2, 0xe000, (S); +ashift_test 0x8001, -3, 0xf000, (S); +ashift_test 0x8001, -4, 0xf800, (S); +ashift_test 0x8001, -5, 0xfc00, (S); +ashift_test 0x8001, -6, 0xfe00, (S); +ashift_test 0x8001, -7, 0xff00, (S); +ashift_test 0x8001, -8, 0xff80, (S); +ashift_test 0x8001, -9, 0xffc0, (S); +ashift_test 0x8001, -10, 0xffe0, (S); +ashift_test 0x8001, -11, 0xfff0, (S); +ashift_test 0x8001, -12, 0xfff8, (S); +ashift_test 0x8001, -13, 0xfffc, (S); +ashift_test 0x8001, -14, 0xfffe, (S); +ashift_test 0x8001, -15, 0xffff, (S); +ashift_test 0x8001, -16, 0xffff, (S); +ashift_test 0x8001, -17, 0xffff, (S); +ashift_test 0x8001, -18, 0xffff, (S); +ashift_test 0x8001, -19, 0xffff, (S); +ashift_test 0x8001, -20, 0xffff, (S); +ashift_test 0x8001, -21, 0xffff, (S); +ashift_test 0x8001, -22, 0xffff, (S); +ashift_test 0x8001, -23, 0xffff, (S); +ashift_test 0x8001, -24, 0xffff, (S); +ashift_test 0x8001, -25, 0xffff, (S); +ashift_test 0x8001, -26, 0xffff, (S); +ashift_test 0x8001, -27, 0xffff, (S); +ashift_test 0x8001, -28, 0xffff, (S); +ashift_test 0x8001, -29, 0xffff, (S); +ashift_test 0x8001, -30, 0xffff, (S); +ashift_test 0x8001, -31, 0xffff, (S); +ashift_test 0x8001, -32, 0xffff, (S); +ashift_test 0x8001, -33, 0x8000, (S); +ashift_test 0x8001, -34, 0x8000, (S); + + +ashift_test 0x4002, 33, 0x0; +ashift_test 0x4002, 32, 0x0; +ashift_test 0x4002, 31, 0x0; +ashift_test 0x4002, 30, 0x0; +ashift_test 0x4002, 20, 0x0; +ashift_test 0x4002, 19, 0x0; +ashift_test 0x4002, 18, 0x0; +ashift_test 0x4002, 17, 0x0; +ashift_test 0x4002, 16, 0x0; +ashift_test 0x4002, 15, 0x0; +ashift_test 0x4002, 14, 0x8000; +ashift_test 0x4002, 13, 0x4000; +ashift_test 0x4002, 12, 0x2000; +ashift_test 0x4002, 11, 0x1000; +ashift_test 0x4002, 10, 0x0800; +ashift_test 0x4002, 9, 0x0400; +ashift_test 0x4002, 8, 0x0200; +ashift_test 0x4002, 7, 0x0100; +ashift_test 0x4002, 6, 0x0080; +ashift_test 0x4002, 5, 0x0040; +ashift_test 0x4002, 4, 0x0020; +ashift_test 0x4002, 3, 0x0010; +ashift_test 0x4002, 2, 0x0008; +ashift_test 0x4002, 1, 0x8004; +ashift_test 0x4002, 0, 0x4002; +ashift_test 0x4002, -1, 0x2001; +ashift_test 0x4002, -2, 0x1000; +ashift_test 0x4002, -3, 0x0800; +ashift_test 0x4002, -4, 0x0400; +ashift_test 0x4002, -5, 0x0200; +ashift_test 0x4002, -6, 0x0100; +ashift_test 0x4002, -7, 0x0080; +ashift_test 0x4002, -8, 0x0040; +ashift_test 0x4002, -9, 0x0020; +ashift_test 0x4002, -10, 0x0010; +ashift_test 0x4002, -11, 0x0008; +ashift_test 0x4002, -12, 0x0004; +ashift_test 0x4002, -13, 0x0002; +ashift_test 0x4002, -14, 0x0001; +ashift_test 0x4002, -15, 0x0; +ashift_test 0x4002, -16, 0x0; +ashift_test 0x4002, -17, 0x0; +ashift_test 0x4002, -31, 0x0; +ashift_test 0x4002, -32, 0x0; +ashift_test 0x4002, -33, 0x0; +ashift_test 0x4002, -34, 0x0; + +ashift_test 0x4002, 33, 0x0, (S); +ashift_test 0x4002, 32, 0x0, (S); +ashift_test 0x4002, 31, 0x7fff, (S); +ashift_test 0x4002, 30, 0x7fff, (S); +ashift_test 0x4002, 20, 0x7fff, (S); +ashift_test 0x4002, 19, 0x7fff, (S); +ashift_test 0x4002, 18, 0x7fff, (S); +ashift_test 0x4002, 17, 0x7fff, (S); +ashift_test 0x4002, 16, 0x7fff, (S); +ashift_test 0x4002, 15, 0x7fff, (S); +ashift_test 0x4002, 14, 0x7fff, (S); +ashift_test 0x4002, 13, 0x7fff, (S); +ashift_test 0x4002, 12, 0x7fff, (S); +ashift_test 0x4002, 11, 0x7fff, (S); +ashift_test 0x4002, 10, 0x7fff, (S); +ashift_test 0x4002, 9, 0x7fff, (S); +ashift_test 0x4002, 8, 0x7fff, (S); +ashift_test 0x4002, 7, 0x7fff, (S); +ashift_test 0x4002, 6, 0x7fff, (S); +ashift_test 0x4002, 5, 0x7fff, (S); +ashift_test 0x4002, 4, 0x7fff, (S); +ashift_test 0x4002, 3, 0x7fff, (S); +ashift_test 0x4002, 2, 0x7fff, (S); +ashift_test 0x4002, 1, 0x7fff, (S); +ashift_test 0x4002, 0, 0x4002, (S); +ashift_test 0x4002, -1, 0x2001, (S); +ashift_test 0x4002, -2, 0x1000, (S); +ashift_test 0x4002, -3, 0x0800, (S); +ashift_test 0x4002, -4, 0x0400, (S); +ashift_test 0x4002, -5, 0x0200, (S); +ashift_test 0x4002, -6, 0x0100, (S); +ashift_test 0x4002, -7, 0x0080, (S); +ashift_test 0x4002, -8, 0x0040, (S); +ashift_test 0x4002, -9, 0x0020, (S); +ashift_test 0x4002, -10, 0x0010, (S); +ashift_test 0x4002, -11, 0x0008, (S); +ashift_test 0x4002, -12, 0x0004, (S); +ashift_test 0x4002, -13, 0x0002, (S); +ashift_test 0x4002, -14, 0x0001, (S); +ashift_test 0x4002, -15, 0x0000, (S); +ashift_test 0x4002, -16, 0x0000, (S); +ashift_test 0x4002, -17, 0x0000, (S); +ashift_test 0x4002, -31, 0x0000, (S); +ashift_test 0x4002, -32, 0x0000, (S); +ashift_test 0x4002, -33, 0x7fff, (S); +ashift_test 0x4002, -34, 0x7fff, (S); + +ashift_test 0x0001, 33, 0x0000, (S); +ashift_test 0x0001, 32, 0x0000, (S); +ashift_test 0x0001, 31, 0x7fff, (S); +ashift_test 0x0001, 30, 0x7fff, (S); +ashift_test 0x0001, 29, 0x7fff, (S); +ashift_test 0x0001, 28, 0x7fff, (S); +ashift_test 0x0001, 27, 0x7fff, (S); +ashift_test 0x0001, 26, 0x7fff, (S); +ashift_test 0x0001, 25, 0x7fff, (S); +ashift_test 0x0001, 24, 0x7fff, (S); +ashift_test 0x0001, 23, 0x7fff, (S); +ashift_test 0x0001, 22, 0x7fff, (S); +ashift_test 0x0001, 21, 0x7fff, (S); +ashift_test 0x0001, 20, 0x7fff, (S); +ashift_test 0x0001, 19, 0x7fff, (S); +ashift_test 0x0001, 18, 0x7fff, (S); +ashift_test 0x0001, 17, 0x7fff, (S); +ashift_test 0x0001, 16, 0x7fff, (S); +ashift_test 0x0001, 15, 0x7fff, (S); +ashift_test 0x0001, 14, 0x4000, (S); +ashift_test 0x0001, 13, 0x2000, (S); +ashift_test 0x0001, 12, 0x1000, (S); +ashift_test 0x0001, 11, 0x0800, (S); +ashift_test 0x0001, 10, 0x0400, (S); +ashift_test 0x0001, 9, 0x0200, (S); +ashift_test 0x0001, 8, 0x0100, (S); +ashift_test 0x0001, 7, 0x0080, (S); +ashift_test 0x0001, 6, 0x0040, (S); +ashift_test 0x0001, 5, 0x0020, (S); +ashift_test 0x0001, 4, 0x0010, (S); +ashift_test 0x0001, 3, 0x0008, (S); +ashift_test 0x0001, 2, 0x0004, (S); +ashift_test 0x0001, 1, 0x0002, (S); +ashift_test 0x0001, 0, 0x0001, (S); +ashift_test 0x0001, -1, 0x0000, (S); +ashift_test 0x0001, -2, 0x0000, (S); +ashift_test 0x0001, -3, 0x0000, (S); +ashift_test 0x0001, -4, 0x0000, (S); +ashift_test 0x0001, -5, 0x0000, (S); +ashift_test 0x0001, -6, 0x0000, (S); +ashift_test 0x0001, -7, 0x0000, (S); +ashift_test 0x0001, -8, 0x0000, (S); +ashift_test 0x0001, -9, 0x0000, (S); +ashift_test 0x0001, -10, 0x0000, (S); +ashift_test 0x0001, -11, 0x0000, (S); +ashift_test 0x0001, -12, 0x0000, (S); +ashift_test 0x0001, -13, 0x0000, (S); +ashift_test 0x0001, -14, 0x0, (S); +ashift_test 0x0001, -15, 0x0, (S); +ashift_test 0x0001, -16, 0x0, (S); +ashift_test 0x0001, -17, 0x0, (S); +ashift_test 0x0001, -18, 0x0, (S); +ashift_test 0x0001, -19, 0x0, (S); +ashift_test 0x0001, -20, 0x0, (S); +ashift_test 0x0001, -21, 0x0, (S); +ashift_test 0x0001, -22, 0x0, (S); +ashift_test 0x0001, -23, 0x0, (S); +ashift_test 0x0001, -24, 0x0, (S); +ashift_test 0x0001, -25, 0x0, (S); +ashift_test 0x0001, -26, 0x0, (S); +ashift_test 0x0001, -27, 0x0, (S); +ashift_test 0x0001, -28, 0x0, (S); +ashift_test 0x0001, -29, 0x0, (S); +ashift_test 0x0001, -30, 0x0, (S); +ashift_test 0x0001, -31, 0x0, (S); +ashift_test 0x0001, -32, 0x0, (S); +ashift_test 0x0001, -33, 0x7fff, (S); +ashift_test 0x0001, -34, 0x7fff, (S); + + pass diff --git a/sim/testsuite/bfin/ashift_flags.s b/sim/testsuite/bfin/ashift_flags.s new file mode 100644 index 0000000..87f00be --- /dev/null +++ b/sim/testsuite/bfin/ashift_flags.s @@ -0,0 +1,84 @@ +# mach: bfin + +.include "testutils.inc" + start + +// load r1=0x7fffffff +// load r2=0x80000000 +// load r3=0x000000ff +// load r4=0x00000000 + loadsym p0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + + _dbg r0; + _dbg r1; + _dbg r2; + _dbg r3; + _dbg r4; + + R7 = 0; + ASTAT = R7; + r5 = r1 << 0x4 (s); + _DBG ASTAT; + r7=astat; + dbga (r5.h, 0x7fff); + dbga (r5.l, 0xffff); + dbga (r7.h, 0x0300); // V=1, VS=1 + dbga (r7.l, 0x8); + + R7 = 0; + ASTAT = R7; + r5.h = r1.h << 0x4 (s); + _DBG ASTAT; + r7=astat; + dbga (r5.h, 0x7fff); + dbga (r7.h, 0x0300); // V=1, VS=1 + dbga (r7.l, 0x8); + + A0 = 0; + A0.w = r1; + A0.x = r0.l; + r6 = 0x3; + _dbg r6; + _dbg A0; + R7 = 0; + ASTAT = R7; + A0 = ASHIFT A0 BY R6.L; + _DBG ASTAT; + _DBG A0; + r7 = astat; + dbga (r7.h, 0x0); // AV0=0, AV0S=0 + dbga (r7.l, 0x2); // AN = 1 + + A1 = 0; + A1 = r1; + A1.x = r0.l; + r6 = 0x3; + _dbg A1; + R7 = 0; + ASTAT = R7; + A1 = ASHIFT A1 BY R6.L; + _DBG ASTAT; + _DBG A1; + r7 = astat; + dbga (r7.h, 0x0); // AV1=0, AV1S=0 + dbga (r7.l, 0x2); // AN = 1 + + pass + + .data 0x1000; +data0: + .dw 0x1111 + .dw 0x1111 + .dw 0xffff + .dw 0x7fff + .dw 0x0000 + .dw 0x8000 + .dw 0x00ff + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/bfin/ashift_left.s b/sim/testsuite/bfin/ashift_left.s new file mode 100644 index 0000000..04cfa40 --- /dev/null +++ b/sim/testsuite/bfin/ashift_left.s @@ -0,0 +1,17 @@ +# Blackfin testcase for left ashift +# Dreg = Dreg << imm (S); +# mach: bfin + + .include "testutils.inc" + + .macro test in:req, shift:req, out:req, opt + imm32 r0, \in; + r1 = r0 >>> \shift \opt; + CHECKREG r1, \out; + .endm + + start + +test 2, 1, 1, (S); + + pass diff --git a/sim/testsuite/bfin/b0.S b/sim/testsuite/bfin/b0.S new file mode 100644 index 0000000..5a02092 --- /dev/null +++ b/sim/testsuite/bfin/b0.S @@ -0,0 +1,51 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + CC = R0 == R0; + + AZ = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AC0|_AC0_COPY|_CC|_AZ); + R0 = R0 + R0; + R0 = ASTAT; CHECKREG R0, (_CC); + + AN = CC; + R0 = ASTAT; CHECKREG R0, (_CC|_AN); + R0 = - R0; + R0 = ASTAT; CHECKREG R0, (_CC|_AN); + + AC0 = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AC0|_CC|_AN); + + AV0 = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_CC|_AN); + + AV1 = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_CC|_AN); + + AQ = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AQ|_CC|_AN); + + CC = R0 < R0; + _DBG ASTAT; + +// When AV0 is set, AV1 is unchanged + AQ = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AC0_COPY|_AZ); + + AV1 = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_AC0_COPY|_AZ); + + pass diff --git a/sim/testsuite/bfin/b1.s b/sim/testsuite/bfin/b1.s new file mode 100644 index 0000000..c9eaeca --- /dev/null +++ b/sim/testsuite/bfin/b1.s @@ -0,0 +1,12 @@ +# mach: bfin +.include "testutils.inc" + start + + R0 = 0; + CC = R0 == R0; + + IF CC JUMP 4; + JUMP.S LL1; + pass +LL1: + fail diff --git a/sim/testsuite/bfin/b2.S b/sim/testsuite/bfin/b2.S new file mode 100644 index 0000000..731f874 --- /dev/null +++ b/sim/testsuite/bfin/b2.S @@ -0,0 +1,26 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + CC = BITTST ( R0 , 0x0 ); + BITSET( R0 , 0x0 ); + CC = BITTST ( R0 , 0x0 ); + CC = ! BITTST( R0 , 0x0 ); + R1.L = 1; + R1.H = 0; + CC = R0 == R1; + CC = BITTST ( R0 , 0x1 ); + R5 = ASTAT; + CHECKREG R5, (_AC0|_AC0_COPY|_AZ) + + BITSET( R0 , 0x1 ); + R5 = ASTAT; + CHECKREG R5, 0 + CC = BITTST ( R0 , 0x1 ); + CC = ! BITTST( R0 , 0x1 ); + pass diff --git a/sim/testsuite/bfin/brcc.s b/sim/testsuite/bfin/brcc.s new file mode 100644 index 0000000..479bf50 --- /dev/null +++ b/sim/testsuite/bfin/brcc.s @@ -0,0 +1,164 @@ +# mach: bfin + +.include "testutils.inc" + start + + + /* Stall tests */ + + r0 = 0; + r1 = 1; + loadsym p0, foo; + p1 = p0; + +pass_1: + cc = r0; + nop; + nop; + + if cc jump _fail_1; + [p0++] = p0; + [p0++] = p0; + r7 = p0; + r5 = CC; + P1 += 8; + r6 = p1; + CC = R6 == R7; + if !CC jump _failure; + + cc = R5; + if !cc jump over; + +_fail_1: + [p0++] = p0; + [p0++] = p0; + +back: + if !cc jump skip(bp); + +_fail_2: + [p0++] = p0; + [p0++] = p0; + +over: + if cc jump _fail_3(bp); + [p0++] = p0; + [p0++] = p0; + r7=p0; + R5=cc; + P1 += 8; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + + CC = R5; + if !cc jump back(bp); + +_fail_3: + [p0++] = p0; + [p0++] = p0; + +skip: + [p0++] = p0; + [p0++] = p0; + [p0++] = p0; + r7=p0; + + P1 += 0xc; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + +next: + [p0++] = p0; + r7=p0; + P1 += 4; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + +pass_2: + cc = r1; + nop; + nop; + + if !cc jump _fail_4; + [p0++] = p0; + [p0++] = p0; + r7=p0; + R5 = cc; + P1 += 8; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + + cc = R5; + if cc jump over_2; + +_fail_4: + [p0++] = p0; + [p0++] = p0; + P1 += 8; + +back_2: + if cc jump skip_2 (bp); + +_fail_5: + [p0++] = p0; + [p0++] = p0; + P1 += 8; + +over_2: + if !cc jump _fail_6 (bp); + [p0++] = p0; + [p0++] = p0; + r7=p0; + R5 = cc; + P1 += 8; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + cc = R5; + + if cc jump back_2 (bp); + +_fail_6: + [p0++] = p0; + [p0++] = p0; + +skip_2: + [p0++] = p0; + [p0++] = p0; + [p0++] = p0; + r7=p0; + R5 = cc; + P1 += 0xc; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + cc = r5; + + if cc jump next_2 (bp); + +next_2: + [p0++] = p0; + [p0++] = p0; + P1 += 8; + r7=p0; + r6 = P1; + CC = R6 == R7; + if !CC jump _failure; + + cc = r0; +_halt: + pass; + +_fail_7: + [p0++] = p0; + +_failure: + fail; + + .data +foo: + .space (0x100) diff --git a/sim/testsuite/bfin/brevadd.s b/sim/testsuite/bfin/brevadd.s new file mode 100644 index 0000000..56e1122 --- /dev/null +++ b/sim/testsuite/bfin/brevadd.s @@ -0,0 +1,20 @@ +# Blackfin testcase for signbits +# mach: bfin + + .include "testutils.inc" + + start + + L2 = 0; + M2 = -4 (X); + I2.H = 0x9000; + I2.L = 0; + I2 += M2 (BREV); + R2 = I2; + imm32 r0, 0x10000002 + CC = R2 == R0 + if CC jump 1f; + + fail +1: + pass diff --git a/sim/testsuite/bfin/byteop16m.s b/sim/testsuite/bfin/byteop16m.s new file mode 100644 index 0000000..bd7478f --- /dev/null +++ b/sim/testsuite/bfin/byteop16m.s @@ -0,0 +1,76 @@ +# Blackfin testcase for BYTEOP16M +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_it resL:req, resH:req + imm32 R6, \resL + CC = R4 == R6; + IF !CC JUMP 1f; +#DBG R4 + imm32 R7, \resH + CC = R5 == R7; + IF !CC JUMP 1f; +#DBG R5 + .endm + .macro test_byteop16m i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req + dmm32 I0, \i0 + dmm32 I1, \i1 + + (R4, R5) = BYTEOP16M (R1:0, R3:2); + check_it \resL, \resH + (R4, R5) = BYTEOP16M (R1:0, R3:2) (R); + check_it \resLR, \resHR + + jump 2f; +1: fail +2: + .endm + + imm32 R0, 0x01020304 + imm32 R1, 0x10203040 + imm32 R2, 0x0a0b0c0d + imm32 R3, 0xa0b0c0d0 + + test_byteop16m 0, 0, 0xfff7fff7, 0xfff7fff7, 0xff70ff70, 0xff70ff70 + test_byteop16m 0, 1, 0xff31fff8, 0xfff8fff8, 0x0003ff80, 0xff80ff80 + test_byteop16m 0, 2, 0xff41ff32, 0xfff9fff9, 0x00040013, 0xff90ff90 + test_byteop16m 0, 3, 0xff51ff42, 0xff33fffa, 0x00050014, 0x0023ffa0 + test_byteop16m 1, 0, 0x0036fff6, 0xfff6fff6, 0xff64ff60, 0xff60ff60 + test_byteop16m 1, 1, 0xff70fff7, 0xfff7fff7, 0xfff7ff70, 0xff70ff70 + test_byteop16m 1, 2, 0xff80ff31, 0xfff8fff8, 0xfff80003, 0xff80ff80 + test_byteop16m 1, 3, 0xff90ff41, 0xff32fff9, 0xfff90004, 0x0013ff90 + test_byteop16m 2, 0, 0x00260035, 0xfff5fff5, 0xff63ff54, 0xff50ff50 + test_byteop16m 2, 1, 0xff600036, 0xfff6fff6, 0xfff6ff64, 0xff60ff60 + test_byteop16m 2, 2, 0xff70ff70, 0xfff7fff7, 0xfff7fff7, 0xff70ff70 + test_byteop16m 2, 3, 0xff80ff80, 0xff31fff8, 0xfff8fff8, 0x0003ff80 + test_byteop16m 3, 0, 0x00160025, 0x0034fff4, 0xff62ff53, 0xff44ff40 + test_byteop16m 3, 1, 0xff500026, 0x0035fff5, 0xfff5ff63, 0xff54ff50 + test_byteop16m 3, 2, 0xff60ff60, 0x0036fff6, 0xfff6fff6, 0xff64ff60 + test_byteop16m 3, 3, 0xff70ff70, 0xff70fff7, 0xfff7fff7, 0xfff7ff70 + + imm32 R0, ~0x01020304 + imm32 R1, ~0x10203040 + imm32 R2, ~0x0a0b0c0d + imm32 R3, ~0xa0b0c0d0 + + test_byteop16m 0, 0, 0x00090009, 0x00090009, 0x00900090, 0x00900090 + test_byteop16m 0, 1, 0x00cf0008, 0x00080008, 0xfffd0080, 0x00800080 + test_byteop16m 0, 2, 0x00bf00ce, 0x00070007, 0xfffcffed, 0x00700070 + test_byteop16m 0, 3, 0x00af00be, 0x00cd0006, 0xfffbffec, 0xffdd0060 + test_byteop16m 1, 0, 0xffca000a, 0x000a000a, 0x009c00a0, 0x00a000a0 + test_byteop16m 1, 1, 0x00900009, 0x00090009, 0x00090090, 0x00900090 + test_byteop16m 1, 2, 0x008000cf, 0x00080008, 0x0008fffd, 0x00800080 + test_byteop16m 1, 3, 0x007000bf, 0x00ce0007, 0x0007fffc, 0xffed0070 + test_byteop16m 2, 0, 0xffdaffcb, 0x000b000b, 0x009d00ac, 0x00b000b0 + test_byteop16m 2, 1, 0x00a0ffca, 0x000a000a, 0x000a009c, 0x00a000a0 + test_byteop16m 2, 2, 0x00900090, 0x00090009, 0x00090009, 0x00900090 + test_byteop16m 2, 3, 0x00800080, 0x00cf0008, 0x00080008, 0xfffd0080 + test_byteop16m 3, 0, 0xffeaffdb, 0xffcc000c, 0x009e00ad, 0x00bc00c0 + test_byteop16m 3, 1, 0x00b0ffda, 0xffcb000b, 0x000b009d, 0x00ac00b0 + test_byteop16m 3, 2, 0x00a000a0, 0xffca000a, 0x000a000a, 0x009c00a0 + test_byteop16m 3, 3, 0x00900090, 0x00900009, 0x00090009, 0x00090090 + + pass diff --git a/sim/testsuite/bfin/byteop16p.s b/sim/testsuite/bfin/byteop16p.s new file mode 100644 index 0000000..fdc5d66 --- /dev/null +++ b/sim/testsuite/bfin/byteop16p.s @@ -0,0 +1,74 @@ +# Blackfin testcase for BYTEOP16P +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_it resL:req, resH:req + imm32 R6, \resL + CC = R4 == R6; + IF !CC JUMP 1f; + imm32 R7, \resH + CC = R5 == R7; + IF !CC JUMP 1f; + .endm + .macro test_byteop16p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req + dmm32 I0, \i0 + dmm32 I1, \i1 + + (R4, R5) = BYTEOP16P (R1:0, R3:2); + check_it \resL, \resH + (R4, R5) = BYTEOP16P (R1:0, R3:2) (R); + check_it \resLR, \resHR + + jump 2f; +1: fail +2: + .endm + + imm32 R0, 0x01020304 + imm32 R1, 0x10203040 + imm32 R2, 0x0a0b0c0d + imm32 R3, 0xa0b0c0d0 + + test_byteop16p 0, 0, 0x000b000d, 0x000f0011, 0x00b000d0, 0x00f00110 + test_byteop16p 0, 1, 0x00d1000c, 0x000e0010, 0x001d00c0, 0x00e00100 + test_byteop16p 0, 2, 0x00c100d2, 0x000d000f, 0x001c002d, 0x00d000f0 + test_byteop16p 0, 3, 0x00b100c2, 0x00d3000e, 0x001b002c, 0x003d00e0 + test_byteop16p 1, 0, 0x004a000c, 0x000e0010, 0x00a400c0, 0x00e00100 + test_byteop16p 1, 1, 0x0110000b, 0x000d000f, 0x001100b0, 0x00d000f0 + test_byteop16p 1, 2, 0x010000d1, 0x000c000e, 0x0010001d, 0x00c000e0 + test_byteop16p 1, 3, 0x00f000c1, 0x00d2000d, 0x000f001c, 0x002d00d0 + test_byteop16p 2, 0, 0x003a004b, 0x000d000f, 0x00a300b4, 0x00d000f0 + test_byteop16p 2, 1, 0x0100004a, 0x000c000e, 0x001000a4, 0x00c000e0 + test_byteop16p 2, 2, 0x00f00110, 0x000b000d, 0x000f0011, 0x00b000d0 + test_byteop16p 2, 3, 0x00e00100, 0x00d1000c, 0x000e0010, 0x001d00c0 + test_byteop16p 3, 0, 0x002a003b, 0x004c000e, 0x00a200b3, 0x00c400e0 + test_byteop16p 3, 1, 0x00f0003a, 0x004b000d, 0x000f00a3, 0x00b400d0 + test_byteop16p 3, 2, 0x00e00100, 0x004a000c, 0x000e0010, 0x00a400c0 + test_byteop16p 3, 3, 0x00d000f0, 0x0110000b, 0x000d000f, 0x001100b0 + + imm32 R0, ~0x01020304 + imm32 R1, ~0x10203040 + imm32 R2, ~0x0a0b0c0d + imm32 R3, ~0xa0b0c0d0 + + test_byteop16p 0, 0, 0x01f301f1, 0x01ef01ed, 0x014e012e, 0x010e00ee + test_byteop16p 0, 1, 0x012d01f2, 0x01f001ee, 0x01e1013e, 0x011e00fe + test_byteop16p 0, 2, 0x013d012c, 0x01f101ef, 0x01e201d1, 0x012e010e + test_byteop16p 0, 3, 0x014d013c, 0x012b01f0, 0x01e301d2, 0x01c1011e + test_byteop16p 1, 0, 0x01b401f2, 0x01f001ee, 0x015a013e, 0x011e00fe + test_byteop16p 1, 1, 0x00ee01f3, 0x01f101ef, 0x01ed014e, 0x012e010e + test_byteop16p 1, 2, 0x00fe012d, 0x01f201f0, 0x01ee01e1, 0x013e011e + test_byteop16p 1, 3, 0x010e013d, 0x012c01f1, 0x01ef01e2, 0x01d1012e + test_byteop16p 2, 0, 0x01c401b3, 0x01f101ef, 0x015b014a, 0x012e010e + test_byteop16p 2, 1, 0x00fe01b4, 0x01f201f0, 0x01ee015a, 0x013e011e + test_byteop16p 2, 2, 0x010e00ee, 0x01f301f1, 0x01ef01ed, 0x014e012e + test_byteop16p 2, 3, 0x011e00fe, 0x012d01f2, 0x01f001ee, 0x01e1013e + test_byteop16p 3, 0, 0x01d401c3, 0x01b201f0, 0x015c014b, 0x013a011e + test_byteop16p 3, 1, 0x010e01c4, 0x01b301f1, 0x01ef015b, 0x014a012e + test_byteop16p 3, 2, 0x011e00fe, 0x01b401f2, 0x01f001ee, 0x015a013e + test_byteop16p 3, 3, 0x012e010e, 0x00ee01f3, 0x01f101ef, 0x01ed014e + + pass diff --git a/sim/testsuite/bfin/byteop1p.s b/sim/testsuite/bfin/byteop1p.s new file mode 100644 index 0000000..e90d790 --- /dev/null +++ b/sim/testsuite/bfin/byteop1p.s @@ -0,0 +1,75 @@ +# Blackfin testcase for BYTEOP1P +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_it res:req + imm32 R7, \res + CC = R6 == R7; + IF !CC JUMP 1f; + .endm + .macro test_byteop1p i0:req, i1:req, res:req, resT:req, resR:req, resTR:req + dmm32 I0, \i0 + dmm32 I1, \i1 + + R6 = BYTEOP1P (R1:0, R3:2); + check_it \res + R6 = BYTEOP1P (R1:0, R3:2) (T); + check_it \resT + R6 = BYTEOP1P (R1:0, R3:2) (R); + check_it \resR + R6 = BYTEOP1P (R1:0, R3:2) (T, R); + check_it \resTR + + jump 2f; +1: fail +2: + .endm + + imm32 R0, 0x01020304 + imm32 R1, 0x10203040 + imm32 R2, 0x0a0b0c0d + imm32 R3, 0xa0b0c0d0 + + test_byteop1p 0, 0, 0x06070809, 0x05060708, 0x58687888, 0x58687888 + test_byteop1p 0, 1, 0x69060708, 0x68060708, 0x0f607080, 0x0e607080 + test_byteop1p 0, 2, 0x61690708, 0x60690607, 0x0e176878, 0x0e166878 + test_byteop1p 0, 3, 0x59616a07, 0x58616907, 0x0e161f70, 0x0d161e70 + test_byteop1p 1, 0, 0x25060708, 0x25060708, 0x52607080, 0x52607080 + test_byteop1p 1, 1, 0x88060708, 0x88050607, 0x09586878, 0x08586878 + test_byteop1p 1, 2, 0x80690607, 0x80680607, 0x080f6070, 0x080e6070 + test_byteop1p 1, 3, 0x78616907, 0x78606906, 0x080e1768, 0x070e1668 + test_byteop1p 2, 0, 0x1d260708, 0x1d250607, 0x525a6878, 0x515a6878 + test_byteop1p 2, 1, 0x80250607, 0x80250607, 0x08526070, 0x08526070 + test_byteop1p 2, 2, 0x78880607, 0x78880506, 0x08095868, 0x07085868 + test_byteop1p 2, 3, 0x70806906, 0x70806806, 0x07080f60, 0x07080e60 + test_byteop1p 3, 0, 0x151e2607, 0x151d2607, 0x515a6270, 0x51596270 + test_byteop1p 3, 1, 0x781d2607, 0x781d2506, 0x08525a68, 0x07515a68 + test_byteop1p 3, 2, 0x70802506, 0x70802506, 0x07085260, 0x07085260 + test_byteop1p 3, 3, 0x68788806, 0x68788805, 0x07080958, 0x06070858 + + imm32 R0, ~0x01020304 + imm32 R1, ~0x10203040 + imm32 R2, ~0x0a0b0c0d + imm32 R3, ~0xa0b0c0d0 + + test_byteop1p 0, 0, 0xfaf9f8f7, 0xf9f8f7f6, 0xa7978777, 0xa7978777 + test_byteop1p 0, 1, 0x97f9f8f7, 0x96f9f8f7, 0xf19f8f7f, 0xf09f8f7f + test_byteop1p 0, 2, 0x9f96f9f8, 0x9e96f8f7, 0xf1e99787, 0xf1e89787 + test_byteop1p 0, 3, 0xa79e96f8, 0xa69e95f8, 0xf2e9e18f, 0xf1e9e08f + test_byteop1p 1, 0, 0xdaf9f8f7, 0xdaf9f8f7, 0xad9f8f7f, 0xad9f8f7f + test_byteop1p 1, 1, 0x77faf9f8, 0x77f9f8f7, 0xf7a79787, 0xf6a79787 + test_byteop1p 1, 2, 0x7f97f9f8, 0x7f96f9f8, 0xf7f19f8f, 0xf7f09f8f + test_byteop1p 1, 3, 0x879f96f9, 0x879e96f8, 0xf8f1e997, 0xf7f1e897 + test_byteop1p 2, 0, 0xe2daf9f8, 0xe2d9f8f7, 0xaea59787, 0xada59787 + test_byteop1p 2, 1, 0x7fdaf9f8, 0x7fdaf9f8, 0xf7ad9f8f, 0xf7ad9f8f + test_byteop1p 2, 2, 0x8777faf9, 0x8777f9f8, 0xf8f7a797, 0xf7f6a797 + test_byteop1p 2, 3, 0x8f7f97f9, 0x8f7f96f9, 0xf8f7f19f, 0xf8f7f09f + test_byteop1p 3, 0, 0xeae2d9f8, 0xeae1d9f8, 0xaea69d8f, 0xaea59d8f + test_byteop1p 3, 1, 0x87e2daf9, 0x87e2d9f8, 0xf8aea597, 0xf7ada597 + test_byteop1p 3, 2, 0x8f7fdaf9, 0x8f7fdaf9, 0xf8f7ad9f, 0xf8f7ad9f + test_byteop1p 3, 3, 0x978777fa, 0x978777f9, 0xf9f8f7a7, 0xf8f7f6a7 + + pass diff --git a/sim/testsuite/bfin/byteop2p.s b/sim/testsuite/bfin/byteop2p.s new file mode 100644 index 0000000..e11109a --- /dev/null +++ b/sim/testsuite/bfin/byteop2p.s @@ -0,0 +1,58 @@ +# Blackfin testcase for BYTEOP2P +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_it res:req + imm32 R7, \res + CC = R6 == R7; + IF !CC JUMP 1f; + .endm + .macro test_byteop2p i0:req, resRL:req, resRH:req, resTL:req, resTH:req, resRLr:req, resRHr:req, resTLr:req, resTHr:req + dmm32 I0, \i0 + + R6 = BYTEOP2P (R1:0, R3:2) (rndl); + check_it \resRL + R6 = BYTEOP2P (R1:0, R3:2) (rndh); + check_it \resRH + R6 = BYTEOP2P (R1:0, R3:2) (tl); + check_it \resTL + R6 = BYTEOP2P (R1:0, R3:2) (th); + check_it \resTH + R6 = BYTEOP2P (R1:0, R3:2) (rndl, r); + check_it \resRLr + R6 = BYTEOP2P (R1:0, R3:2) (rndh, r); + check_it \resRHr + R6 = BYTEOP2P (R1:0, R3:2) (tl, r); + check_it \resTLr + R6 = BYTEOP2P (R1:0, R3:2) (th, r); + check_it \resTHr + + jump 2f; +1: fail +2: + .endm + + imm32 R0, 0x01020304 + imm32 R1, 0x10203040 + imm32 R2, 0x0a0b0c0d + imm32 R3, 0xa0b0c0d0 + + test_byteop2p 0, 0x00060008, 0x06000800, 0x00060008, 0x06000800, 0x00600080, 0x60008000, 0x00600080, 0x60008000 + test_byteop2p 1, 0x00470007, 0x47000700, 0x00460007, 0x46000700, 0x00300070, 0x30007000, 0x00300070, 0x30007000 + test_byteop2p 2, 0x00800006, 0x80000600, 0x00800006, 0x80000600, 0x00080060, 0x08006000, 0x00080060, 0x08006000 + test_byteop2p 3, 0x00700047, 0x70004700, 0x00700046, 0x70004600, 0x00070030, 0x07003000, 0x00070030, 0x07003000 + + imm32 R0, ~0x01020304 + imm32 R1, ~0x10203040 + imm32 R2, ~0x0a0b0c0d + imm32 R3, ~0xa0b0c0d0 + + test_byteop2p 0, 0x00f900f7, 0xf900f700, 0x00f900f7, 0xf900f700, 0x009f007f, 0x9f007f00, 0x009f007f, 0x9f007f00 + test_byteop2p 1, 0x00b800f8, 0xb800f800, 0x00b800f8, 0xb800f800, 0x00cf008f, 0xcf008f00, 0x00ce008f, 0xce008f00 + test_byteop2p 2, 0x007f00f9, 0x7f00f900, 0x007f00f9, 0x7f00f900, 0x00f7009f, 0xf7009f00, 0x00f7009f, 0xf7009f00 + test_byteop2p 3, 0x008f00b8, 0x8f00b800, 0x008f00b8, 0x8f00b800, 0x00f800cf, 0xf800cf00, 0x00f800ce, 0xf800ce00 + + pass diff --git a/sim/testsuite/bfin/byteop3p.s b/sim/testsuite/bfin/byteop3p.s new file mode 100644 index 0000000..a5390f8 --- /dev/null +++ b/sim/testsuite/bfin/byteop3p.s @@ -0,0 +1,119 @@ +# Blackfin testcase for BYTEOP3P +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_it res:req + imm32 R7, \res + CC = R6 == R7; + IF !CC JUMP 1f; + .endm + .macro test_byteop3p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req + dmm32 I0, \i0 + dmm32 I1, \i1 + + R6 = BYTEOP3P (R1:0, R3:2) (LO); + check_it \resL + R6 = BYTEOP3P (R1:0, R3:2) (HI); + check_it \resH + R6 = BYTEOP3P (R1:0, R3:2) (LO, R); + check_it \resLR + R6 = BYTEOP3P (R1:0, R3:2) (HI, R); + check_it \resHR + + jump 2f; +1: fail +2: + .endm + + imm32 R0, 0x01020304 + imm32 R1, 0x10203040 + imm32 R2, 0x0a0b0c0d + imm32 R3, 0xa0b0c0d0 + + test_byteop3p 0, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 0, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 0, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 0, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + + imm32 R0, ~0x01020304 + imm32 R1, ~0x10203040 + imm32 R2, ~0x0a0b0c0d + imm32 R3, ~0xa0b0c0d0 + + test_byteop3p 0, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 0, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 0, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 0, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 1, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 1, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 1, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 1, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 2, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 2, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 2, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 2, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 3, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 3, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 3, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 3, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + + imm32 R0, 0x00010002 + imm32 R1, 0x00030004 + imm32 R2, 0x10203040 + imm32 R3, 0x50607080 + + test_byteop3p 0, 0, 0x00110032, 0x21004200, 0x00530074, 0x63008400 + test_byteop3p 0, 1, 0x00810022, 0x11003200, 0x00430064, 0x53007400 + test_byteop3p 0, 2, 0x00710012, 0x81002200, 0x00330054, 0x43006400 + test_byteop3p 0, 3, 0x00610082, 0x71001200, 0x00230044, 0x33005400 + test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 0, 0x00140031, 0x24004100, 0x00520073, 0x62008300 + test_byteop3p 2, 1, 0x00840021, 0x14003100, 0x00420063, 0x52007300 + test_byteop3p 2, 2, 0x00740011, 0x84002100, 0x00320053, 0x42006300 + test_byteop3p 2, 3, 0x00640081, 0x74001100, 0x00220043, 0x32005300 + test_byteop3p 3, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + + imm32 R0, 0x00100200 + imm32 R1, 0x30000040 + imm32 R2, 0x1a2b3c4d + imm32 R3, 0x5e6f7a8b + + test_byteop3p 0, 0, 0x002a00ff, 0x3b00ff00, 0x00ff00ba, 0xff00cb00 + test_byteop3p 0, 1, 0x009b00ff, 0x2a00ff00, 0x00ff00af, 0xff00ba00 + test_byteop3p 0, 2, 0x008a00ff, 0x9b00ff00, 0x00ff009e, 0xff00af00 + test_byteop3p 0, 3, 0x007f00ff, 0x8a00ff00, 0x00ff008d, 0xff009e00 + test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x008e007a, 0x9f008b00 + test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x007d006f, 0x8e007a00 + test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x006c005e, 0x7d006f00 + test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x005b004d, 0x6c005e00 + test_byteop3p 2, 0, 0x005a004c, 0x6b005d00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 1, 0x00cb003b, 0x5a004c00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 2, 0x00ba002a, 0xcb003b00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 3, 0x00af009b, 0xba002a00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 0, 0x001a00ff, 0x2b00ff00, 0x00ff00aa, 0xff00bb00 + test_byteop3p 3, 1, 0x008b00ff, 0x1a00ff00, 0x00ff009f, 0xff00aa00 + test_byteop3p 3, 2, 0x007a00ff, 0x8b00ff00, 0x00ff008e, 0xff009f00 + test_byteop3p 3, 3, 0x006f00ff, 0x7a00ff00, 0x00ff007d, 0xff008e00 + + pass diff --git a/sim/testsuite/bfin/byteunpack.s b/sim/testsuite/bfin/byteunpack.s new file mode 100644 index 0000000..883c071 --- /dev/null +++ b/sim/testsuite/bfin/byteunpack.s @@ -0,0 +1,45 @@ +# Blackfin testcase for playing with BYTEUNPACK +# mach: bfin + + .include "testutils.inc" + + start + + .macro _bu_pre_test i0:req, src0:req, src1:req + dmm32 I0, \i0 + imm32 R0, \src0 + imm32 R1, \src1 + .endm + .macro _bu_chk_test dst0:req, dst1:req + imm32 R2, \dst0 + imm32 R3, \dst1 + CC = R5 == R2; + IF !CC jump 1f; + CC = R6 == R3; + IF !CC jump 1f; + .endm + .macro bu_test i0:req, dst0:req, dst1:req, src0:req, src1:req + _bu_pre_test \i0, \src0, \src1 + (R6, R5) = BYTEUNPACK R1:0; + _bu_chk_test \dst0, \dst1 + .endm + .macro bu_r_test i0:req, dst0:req, dst1:req, src0:req, src1:req + _bu_pre_test \i0, \src0, \src1 + (R6, R5) = BYTEUNPACK R1:0 (R); + _bu_chk_test \dst0, \dst1 + .endm + + # Taken from PRM + bu_test 0, 0x00BA00DD, 0x00BE00EF, 0xBEEFBADD, 0xFEEDFACE + bu_test 1, 0x00EF00BA, 0x00CE00BE, 0xBEEFBADD, 0xFEEDFACE + bu_test 2, 0x00BE00EF, 0x00FA00CE, 0xBEEFBADD, 0xFEEDFACE + bu_test 3, 0x00CE00BE, 0x00ED00FA, 0xBEEFBADD, 0xFEEDFACE + + # Taken from PRM + bu_r_test 0, 0x00FA00CE, 0x00FE00ED, 0xBEEFBADD, 0xFEEDFACE + bu_r_test 1, 0x00ED00FA, 0x00DD00FE, 0xBEEFBADD, 0xFEEDFACE + bu_r_test 2, 0x00FE00ED, 0x00BA00DD, 0xBEEFBADD, 0xFEEDFACE + bu_r_test 3, 0x00DD00FE, 0x00EF00BA, 0xBEEFBADD, 0xFEEDFACE + + pass +1: fail diff --git a/sim/testsuite/bfin/c_alu2op_arith_r_sft.s b/sim/testsuite/bfin/c_alu2op_arith_r_sft.s new file mode 100644 index 0000000..7ce9d4e --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_arith_r_sft.s @@ -0,0 +1,226 @@ +//Original:/testcases/core/c_alu2op_arith_r_sft/c_alu2op_arith_r_sft.dsp +// Spec Reference: alu2op arith right +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R1.L = 1; +R1 >>>= R0; +R2 >>>= R0; +R3 >>>= R0; +R4 >>>= R0; +R5 >>>= R0; +R6 >>>= R0; +R7 >>>= R0; +R4 >>>= R0; +R0 >>>= R0; +CHECKREG r1, 0x12340001; +CHECKREG r2, 0x23456789; +CHECKREG r3, 0x3456789A; +CHECKREG r4, 0x856789AB; +CHECKREG r5, 0x96789ABC; +CHECKREG r6, 0xA789ABCD; +CHECKREG r7, 0xB89ABCDE; +CHECKREG r0, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R1.L = -1; +R0 >>>= R1; +R2 >>>= R1; +R3 >>>= R1; +R4 >>>= R1; +R5 >>>= R1; +R6 >>>= R1; +R7 >>>= R1; +R1 >>>= R1; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x00000000; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 31; +R0 >>>= R2; +R1 >>>= R2; +R3 >>>= R2; +R4 >>>= R2; +R5 >>>= R2; +R6 >>>= R2; +R7 >>>= R2; +R2 >>>= R2; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0x00000000; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R3.L = -31; +R0 >>>= R3; +R1 >>>= R3; +R2 >>>= R3; +R4 >>>= R3; +R5 >>>= R3; +R6 >>>= R3; +R7 >>>= R3; +R3 >>>= R3; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x00000001; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x00000000; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R4.L = 15; +R1 >>>= R4; +R2 >>>= R4; +R3 >>>= R4; +R0 >>>= R4; +R5 >>>= R4; +R6 >>>= R4; +R7 >>>= R4; +R4 >>>= R4; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00002468; +CHECKREG r2, 0x0000468A; +CHECKREG r3, 0x000068AC; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0xFFFF2CF1; +CHECKREG r6, 0xFFFF4F13; +CHECKREG r7, 0xFFFF7135; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0x00000000; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R5.L = -15; +R0 >>>= R5; +R1 >>>= R5; +R2 >>>= R5; +R3 >>>= R5; +R4 >>>= R5; +R6 >>>= R5; +R7 >>>= R5; +R5 >>>= R5; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0xb1256790; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x00000000; +imm32 r7, 0x789abcde; +R6.L = 24; +R0 >>>= R6; +R1 >>>= R6; +R2 >>>= R6; +R3 >>>= R6; +R4 >>>= R6; +R5 >>>= R6; +R7 >>>= R6; +R6 >>>= R6; +CHECKREG r0, 0x00000051; +CHECKREG r1, 0x00000012; +CHECKREG r2, 0xFFFFFFB1; +CHECKREG r3, 0x00000034; +CHECKREG r4, 0xFFFFFF95; +CHECKREG r5, 0xFFFFFF86; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000078; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0x00000000; +R7.L = -24; +R0 >>>= R7; +R1 >>>= R7; +R2 >>>= R7; +R3 >>>= R7; +R4 >>>= R7; +R5 >>>= R7; +R6 >>>= R7; +R7 >>>= R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0x00000000; + +// special case +R2.L = -1; +R2.H = 32767; +R0 = 0; +R2 >>>= R0; +CHECKREG r2, 0x7FFFFFFF; + +pass diff --git a/sim/testsuite/bfin/c_alu2op_conv_b.s b/sim/testsuite/bfin/c_alu2op_conv_b.s new file mode 100644 index 0000000..0de3b52 --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_conv_b.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_b/c_alu2op_conv_b.dsp +// Spec Reference: alu2op convert b +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.B (Z); +R1 = R0.B (Z); +R2 = R0.B (Z); +R3 = R0.B (Z); +R4 = R0.B (Z); +R5 = R0.B (Z); +R6 = R0.B (Z); +R7 = R0.B (Z); +CHECKREG r0, 0x000000BC; +CHECKREG r1, 0x000000BC; +CHECKREG r2, 0x000000BC; +CHECKREG r3, 0x000000BC; +CHECKREG r4, 0x000000BC; +CHECKREG r5, 0x000000BC; +CHECKREG r6, 0x000000BC; +CHECKREG r7, 0x000000BC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.B (Z); +R2 = R1.B (Z); +R3 = R1.B (Z); +R4 = R1.B (Z); +R5 = R1.B (Z); +R6 = R1.B (Z); +R7 = R1.B (Z); +R1 = R1.B (Z); +CHECKREG r0, 0x00000059; +CHECKREG r1, 0x00000059; +CHECKREG r2, 0x00000059; +CHECKREG r3, 0x00000059; +CHECKREG r4, 0x00000059; +CHECKREG r5, 0x00000059; +CHECKREG r6, 0x00000059; +CHECKREG r7, 0x00000059; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.B (Z); +R1 = R2.B (Z); +R3 = R2.B (Z); +R4 = R2.B (Z); +R5 = R2.B (Z); +R6 = R2.B (Z); +R7 = R2.B (Z); +R2 = R2.B (Z); +CHECKREG r0, 0x00000089; +CHECKREG r1, 0x00000089; +CHECKREG r2, 0x00000089; +CHECKREG r3, 0x00000089; +CHECKREG r4, 0x00000089; +CHECKREG r5, 0x00000089; +CHECKREG r6, 0x00000089; +CHECKREG r7, 0x00000089; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.B (Z); +R1 = R3.B (Z); +R2 = R3.B (Z); +R4 = R3.B (Z); +R5 = R3.B (Z); +R6 = R3.B (Z); +R7 = R3.B (Z); +R3 = R3.B (Z); +CHECKREG r0, 0x0000009A; +CHECKREG r1, 0x0000009A; +CHECKREG r2, 0x0000009A; +CHECKREG r3, 0x0000009A; +CHECKREG r4, 0x0000009A; +CHECKREG r5, 0x0000009A; +CHECKREG r6, 0x0000009A; +CHECKREG r7, 0x0000009A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.B (Z); +R1 = R4.B (Z); +R2 = R4.B (Z); +R3 = R4.B (Z); +R4 = R4.B (Z); +R5 = R4.B (Z); +R6 = R4.B (Z); +R7 = R4.B (Z); +CHECKREG r0, 0x000000AB; +CHECKREG r1, 0x000000AB; +CHECKREG r2, 0x000000AB; +CHECKREG r3, 0x000000AB; +CHECKREG r4, 0x000000AB; +CHECKREG r5, 0x000000AB; +CHECKREG r6, 0x000000AB; +CHECKREG r7, 0x000000AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.B (Z); +R1 = R5.B (Z); +R2 = R5.B (Z); +R3 = R5.B (Z); +R4 = R5.B (Z); +R6 = R5.B (Z); +R7 = R5.B (Z); +R5 = R5.B (Z); +CHECKREG r0, 0x000000BC; +CHECKREG r1, 0x000000BC; +CHECKREG r2, 0x000000BC; +CHECKREG r3, 0x000000BC; +CHECKREG r4, 0x000000BC; +CHECKREG r5, 0x000000BC; +CHECKREG r6, 0x000000BC; +CHECKREG r7, 0x000000BC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.B (Z); +R1 = R6.B (Z); +R2 = R6.B (Z); +R3 = R6.B (Z); +R4 = R6.B (Z); +R5 = R6.B (Z); +R7 = R6.B (Z); +R6 = R6.B (Z); +CHECKREG r0, 0x000000CD; +CHECKREG r1, 0x000000CD; +CHECKREG r2, 0x000000CD; +CHECKREG r3, 0x000000CD; +CHECKREG r4, 0x000000CD; +CHECKREG r5, 0x000000CD; +CHECKREG r6, 0x000000CD; +CHECKREG r7, 0x000000CD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.B (Z); +R1 = R7.B (Z); +R2 = R7.B (Z); +R3 = R7.B (Z); +R4 = R7.B (Z); +R5 = R7.B (Z); +R6 = R7.B (Z); +R7 = R7.B (Z); +CHECKREG r0, 0x00000088; +CHECKREG r1, 0x00000088; +CHECKREG r2, 0x00000088; +CHECKREG r3, 0x00000088; +CHECKREG r4, 0x00000088; +CHECKREG r5, 0x00000088; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x00000088; + + +pass diff --git a/sim/testsuite/bfin/c_alu2op_conv_h.s b/sim/testsuite/bfin/c_alu2op_conv_h.s new file mode 100644 index 0000000..70468a6 --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_conv_h.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_h/c_alu2op_conv_h.dsp +// Spec Reference: alu2op convert h +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.L (Z); +R1 = R0.L (Z); +R2 = R0.L (Z); +R3 = R0.L (Z); +R4 = R0.L (Z); +R5 = R0.L (Z); +R6 = R0.L (Z); +R7 = R0.L (Z); +CHECKREG r0, 0x00009ABC; +CHECKREG r1, 0x00009ABC; +CHECKREG r2, 0x00009ABC; +CHECKREG r3, 0x00009ABC; +CHECKREG r4, 0x00009ABC; +CHECKREG r5, 0x00009ABC; +CHECKREG r6, 0x00009ABC; +CHECKREG r7, 0x00009ABC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.L (Z); +R2 = R1.L (Z); +R3 = R1.L (Z); +R4 = R1.L (Z); +R5 = R1.L (Z); +R6 = R1.L (Z); +R7 = R1.L (Z); +R1 = R1.L (Z); +CHECKREG r0, 0x00004659; +CHECKREG r1, 0x00004659; +CHECKREG r2, 0x00004659; +CHECKREG r3, 0x00004659; +CHECKREG r4, 0x00004659; +CHECKREG r5, 0x00004659; +CHECKREG r6, 0x00004659; +CHECKREG r7, 0x00004659; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.L (Z); +R1 = R2.L (Z); +R3 = R2.L (Z); +R4 = R2.L (Z); +R5 = R2.L (Z); +R6 = R2.L (Z); +R7 = R2.L (Z); +R2 = R2.L (Z); +CHECKREG r0, 0x00006789; +CHECKREG r1, 0x00006789; +CHECKREG r2, 0x00006789; +CHECKREG r3, 0x00006789; +CHECKREG r4, 0x00006789; +CHECKREG r5, 0x00006789; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x00006789; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.L (Z); +R1 = R3.L (Z); +R2 = R3.L (Z); +R4 = R3.L (Z); +R5 = R3.L (Z); +R6 = R3.L (Z); +R7 = R3.L (Z); +R3 = R3.L (Z); +CHECKREG r0, 0x0000789A; +CHECKREG r1, 0x0000789A; +CHECKREG r2, 0x0000789A; +CHECKREG r3, 0x0000789A; +CHECKREG r4, 0x0000789A; +CHECKREG r5, 0x0000789A; +CHECKREG r6, 0x0000789A; +CHECKREG r7, 0x0000789A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.L (Z); +R1 = R4.L (Z); +R2 = R4.L (Z); +R3 = R4.L (Z); +R4 = R4.L (Z); +R5 = R4.L (Z); +R6 = R4.L (Z); +R7 = R4.L (Z); +CHECKREG r0, 0x0000A9AB; +CHECKREG r1, 0x0000A9AB; +CHECKREG r2, 0x0000A9AB; +CHECKREG r3, 0x0000A9AB; +CHECKREG r4, 0x0000A9AB; +CHECKREG r5, 0x0000A9AB; +CHECKREG r6, 0x0000A9AB; +CHECKREG r7, 0x0000A9AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.L (Z); +R1 = R5.L (Z); +R2 = R5.L (Z); +R3 = R5.L (Z); +R4 = R5.L (Z); +R6 = R5.L (Z); +R7 = R5.L (Z); +R5 = R5.L (Z); +CHECKREG r0, 0x00009FBC; +CHECKREG r1, 0x00009FBC; +CHECKREG r2, 0x00009FBC; +CHECKREG r3, 0x00009FBC; +CHECKREG r4, 0x00009FBC; +CHECKREG r5, 0x00009FBC; +CHECKREG r6, 0x00009FBC; +CHECKREG r7, 0x00009FBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.L (Z); +R1 = R6.L (Z); +R2 = R6.L (Z); +R3 = R6.L (Z); +R4 = R6.L (Z); +R5 = R6.L (Z); +R7 = R6.L (Z); +R6 = R6.L (Z); +CHECKREG r0, 0x0000AECD; +CHECKREG r1, 0x0000AECD; +CHECKREG r2, 0x0000AECD; +CHECKREG r3, 0x0000AECD; +CHECKREG r4, 0x0000AECD; +CHECKREG r5, 0x0000AECD; +CHECKREG r6, 0x0000AECD; +CHECKREG r7, 0x0000AECD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.L (Z); +R1 = R7.L (Z); +R2 = R7.L (Z); +R3 = R7.L (Z); +R4 = R7.L (Z); +R5 = R7.L (Z); +R6 = R7.L (Z); +R7 = R7.L (Z); +CHECKREG r0, 0x0000BC88; +CHECKREG r1, 0x0000BC88; +CHECKREG r2, 0x0000BC88; +CHECKREG r3, 0x0000BC88; +CHECKREG r4, 0x0000BC88; +CHECKREG r5, 0x0000BC88; +CHECKREG r6, 0x0000BC88; +CHECKREG r7, 0x0000BC88; + + +pass diff --git a/sim/testsuite/bfin/c_alu2op_conv_mix.s b/sim/testsuite/bfin/c_alu2op_conv_mix.s new file mode 100644 index 0000000..7c33c13 --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_conv_mix.s @@ -0,0 +1,186 @@ +//Original:/testcases/core/c_alu2op_conv_mix/c_alu2op_conv_mix.dsp +// Spec Reference: alu2op convert mix +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.B (X); +R1 = R1.L (X); +R2 = R2.L (Z); +R3 = R3.B (X); +R4 = R4.B (Z); +R5 = - R5; +R6 = ~ R6; +R7 = R7.L (X); +CHECKREG r0, 0xFFFFFFBC; +CHECKREG r1, 0x00005678; +CHECKREG r2, 0x00006789; +CHECKREG r3, 0xFFFFFF9A; +CHECKREG r4, 0x000000AB; +CHECKREG r5, 0x69876544; +CHECKREG r6, 0x58765432; +CHECKREG r7, 0xFFFFBCDE; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R6 = R0.B (X); +R7 = R1.L (X); +R0 = R2.L (Z); +R1 = R3.B (X); +R2 = R4.B (Z); +R3 = - R5; +R4 = ~ R6; +R5 = R7.L (X); +CHECKREG r0, 0x00006789; +CHECKREG r1, 0xFFFFFF9A; +CHECKREG r2, 0x000000AB; +CHECKREG r3, 0x39876544; +CHECKREG r4, 0xFFFFFFFD; +CHECKREG r5, 0x00004659; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0x00004659; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x91203450; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0x789abcde; +R5 = R0.B (X); +R6 = R1.L (X); +R7 = R2.L (Z); +R0 = R3.B (X); +R1 = R4.B (Z); +R2 = - R5; +R3 = ~ R6; +R4 = R7.L (X); +CHECKREG r0, 0xFFFFFF9A; +CHECKREG r1, 0x000000AB; +CHECKREG r2, 0xFFFFFFFE; +CHECKREG r3, 0xFFFFA987; +CHECKREG r4, 0x00003450; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00005678; +CHECKREG r7, 0x00003450; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0x00000000; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R4 = R0.B (X); +R5 = R1.L (X); +R6 = R2.L (Z); +R7 = R3.B (X); +R0 = R4.B (Z); +R1 = - R5; +R2 = ~ R6; +R3 = R7.L (X); +CHECKREG r0, 0x00000002; +CHECKREG r1, 0xFFFFA988; +CHECKREG r2, 0xFFFF9876; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00005678; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xadf00001; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x00000000; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R3 = R0.B (X); +R4 = R1.L (X); +R5 = R2.L (Z); +R6 = R3.B (X); +R7 = R4.B (Z); +R0 = - R5; +R1 = ~ R6; +R2 = R7.L (X); +CHECKREG r0, 0xFFFF9877; +CHECKREG r1, 0xFFFFFFFE; +CHECKREG r2, 0x00000078; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00005678; +CHECKREG r5, 0x00006789; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000078; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0x54238900; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R2 = R0.B (X); +R3 = R1.L (X); +R4 = R2.L (Z); +R5 = R3.B (X); +R6 = R4.B (Z); +R7 = - R5; +R0 = ~ R6; +R1 = R7.L (X); +CHECKREG r0, 0xFFFFFFFD; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x00000000; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x00000000; +imm32 r7, 0x789abcde; +R1 = R0.B (X); +R2 = R1.L (X); +R3 = R2.L (Z); +R4 = R3.B (X); +R5 = R4.B (Z); +R6 = - R5; +R0 = ~ R6; +R7 = R7.L (X); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000002; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0xFFFFFFFE; +CHECKREG r7, 0xFFFFBCDE; + + +pass diff --git a/sim/testsuite/bfin/c_alu2op_conv_neg.s b/sim/testsuite/bfin/c_alu2op_conv_neg.s new file mode 100644 index 0000000..85314a8 --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_conv_neg.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_neg/c_alu2op_conv_neg.dsp +// Spec Reference: alu2op (-) negative +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = - R0; +R1 = - R0; +R2 = - R0; +R3 = - R0; +R4 = - R0; +R5 = - R0; +R6 = - R0; +R7 = - R0; +CHECKREG r0, 0xFF876544; +CHECKREG r1, 0x00789ABC; +CHECKREG r2, 0x00789ABC; +CHECKREG r3, 0x00789ABC; +CHECKREG r4, 0x00789ABC; +CHECKREG r5, 0x00789ABC; +CHECKREG r6, 0x00789ABC; +CHECKREG r7, 0x00789ABC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = - R1; +R1 = - R1; +R2 = - R1; +R3 = - R1; +R4 = - R1; +R5 = - R1; +R6 = - R1; +R7 = - R1; +CHECKREG r0, 0xFFC8B9A7; +CHECKREG r1, 0xFFC8B9A7; +CHECKREG r2, 0x00374659; +CHECKREG r3, 0x00374659; +CHECKREG r4, 0x00374659; +CHECKREG r5, 0x00374659; +CHECKREG r6, 0x00374659; +CHECKREG r7, 0x00374659; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = - R2; +R1 = - R2; +R2 = - R2; +R3 = - R2; +R4 = - R2; +R5 = - R2; +R6 = - R2; +R7 = - R2; +CHECKREG r0, 0x6CEA9877; +CHECKREG r1, 0x6CEA9877; +CHECKREG r2, 0x6CEA9877; +CHECKREG r3, 0x93156789; +CHECKREG r4, 0x93156789; +CHECKREG r5, 0x93156789; +CHECKREG r6, 0x93156789; +CHECKREG r7, 0x93156789; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = - R3; +R1 = - R3; +R2 = - R3; +R3 = - R3; +R4 = - R3; +R5 = - R3; +R6 = - R3; +R7 = - R3; +CHECKREG r0, 0x56AD8766; +CHECKREG r1, 0x56AD8766; +CHECKREG r2, 0x56AD8766; +CHECKREG r3, 0x56AD8766; +CHECKREG r4, 0xA952789A; +CHECKREG r5, 0xA952789A; +CHECKREG r6, 0xA952789A; +CHECKREG r7, 0xA952789A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = - R4; +R1 = - R4; +R2 = - R4; +R3 = - R4; +R4 = - R4; +R5 = - R4; +R6 = - R4; +R7 = - R4; +CHECKREG r0, 0x79985655; +CHECKREG r1, 0x79985655; +CHECKREG r2, 0x79985655; +CHECKREG r3, 0x79985655; +CHECKREG r4, 0x79985655; +CHECKREG r5, 0x8667A9AB; +CHECKREG r6, 0x8667A9AB; +CHECKREG r7, 0x8667A9AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = - R5; +R1 = - R5; +R2 = - R5; +R3 = - R5; +R4 = - R5; +R5 = - R5; +R6 = - R5; +R7 = - R5; +CHECKREG r0, 0x39876044; +CHECKREG r1, 0x39876044; +CHECKREG r2, 0x39876044; +CHECKREG r3, 0x39876044; +CHECKREG r4, 0x39876044; +CHECKREG r5, 0x39876044; +CHECKREG r6, 0xC6789FBC; +CHECKREG r7, 0xC6789FBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = - R6; +R1 = - R6; +R2 = - R6; +R3 = - R6; +R4 = - R6; +R5 = - R6; +R6 = - R6; +R7 = - R6; +CHECKREG r0, 0x58765133; +CHECKREG r1, 0x58765133; +CHECKREG r2, 0x58765133; +CHECKREG r3, 0x58765133; +CHECKREG r4, 0x58765133; +CHECKREG r5, 0x58765133; +CHECKREG r6, 0x58765133; +CHECKREG r7, 0xA789AECD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = - R7; +R1 = - R7; +R2 = - R7; +R3 = - R7; +R4 = - R7; +R5 = - R7; +R7 = - R7; +R6 = - R7; +CHECKREG r0, 0xA7654378; +CHECKREG r1, 0xA7654378; +CHECKREG r2, 0xA7654378; +CHECKREG r3, 0xA7654378; +CHECKREG r4, 0xA7654378; +CHECKREG r5, 0xA7654378; +CHECKREG r6, 0x589ABC88; +CHECKREG r7, 0xA7654378; + + +pass diff --git a/sim/testsuite/bfin/c_alu2op_conv_toggle.s b/sim/testsuite/bfin/c_alu2op_conv_toggle.s new file mode 100644 index 0000000..791d7a9 --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_conv_toggle.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_toggle/c_alu2op_conv_toggle.dsp +// Spec Reference: alu2op (~) toggle +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = ~ R0; +R1 = ~ R0; +R2 = ~ R0; +R3 = ~ R0; +R4 = ~ R0; +R5 = ~ R0; +R6 = ~ R0; +R7 = ~ R0; +CHECKREG r0, 0xFF876543; +CHECKREG r1, 0x00789ABC; +CHECKREG r2, 0x00789ABC; +CHECKREG r3, 0x00789ABC; +CHECKREG r4, 0x00789ABC; +CHECKREG r5, 0x00789ABC; +CHECKREG r6, 0x00789ABC; +CHECKREG r7, 0x00789ABC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = ~ R1; +R1 = ~ R1; +R2 = ~ R1; +R3 = ~ R1; +R4 = ~ R1; +R5 = ~ R1; +R6 = ~ R1; +R7 = ~ R1; +CHECKREG r0, 0xFFC8B9A6; +CHECKREG r1, 0xFFC8B9A6; +CHECKREG r2, 0x00374659; +CHECKREG r3, 0x00374659; +CHECKREG r4, 0x00374659; +CHECKREG r5, 0x00374659; +CHECKREG r6, 0x00374659; +CHECKREG r7, 0x00374659; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = ~ R2; +R1 = ~ R2; +R2 = ~ R2; +R3 = ~ R2; +R4 = ~ R2; +R5 = ~ R2; +R6 = ~ R2; +R7 = ~ R2; +CHECKREG r0, 0x6CEA9876; +CHECKREG r1, 0x6CEA9876; +CHECKREG r2, 0x6CEA9876; +CHECKREG r3, 0x93156789; +CHECKREG r4, 0x93156789; +CHECKREG r5, 0x93156789; +CHECKREG r6, 0x93156789; +CHECKREG r7, 0x93156789; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = ~ R3; +R1 = ~ R3; +R2 = ~ R3; +R3 = ~ R3; +R4 = ~ R3; +R5 = ~ R3; +R6 = ~ R3; +R7 = ~ R3; +CHECKREG r0, 0x56AD8765; +CHECKREG r1, 0x56AD8765; +CHECKREG r2, 0x56AD8765; +CHECKREG r3, 0x56AD8765; +CHECKREG r4, 0xA952789A; +CHECKREG r5, 0xA952789A; +CHECKREG r6, 0xA952789A; +CHECKREG r7, 0xA952789A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = ~ R4; +R1 = ~ R4; +R2 = ~ R4; +R3 = ~ R4; +R4 = ~ R4; +R5 = ~ R4; +R6 = ~ R4; +R7 = ~ R4; +CHECKREG r0, 0x79985654; +CHECKREG r1, 0x79985654; +CHECKREG r2, 0x79985654; +CHECKREG r3, 0x79985654; +CHECKREG r4, 0x79985654; +CHECKREG r5, 0x8667A9AB; +CHECKREG r6, 0x8667A9AB; +CHECKREG r7, 0x8667A9AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = ~ R5; +R1 = ~ R5; +R2 = ~ R5; +R3 = ~ R5; +R4 = ~ R5; +R5 = ~ R5; +R6 = ~ R5; +R7 = ~ R5; +CHECKREG r0, 0x39876043; +CHECKREG r1, 0x39876043; +CHECKREG r2, 0x39876043; +CHECKREG r3, 0x39876043; +CHECKREG r4, 0x39876043; +CHECKREG r5, 0x39876043; +CHECKREG r6, 0xC6789FBC; +CHECKREG r7, 0xC6789FBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = ~ R6; +R1 = ~ R6; +R2 = ~ R6; +R3 = ~ R6; +R4 = ~ R6; +R5 = ~ R6; +R6 = ~ R6; +R7 = ~ R6; +CHECKREG r0, 0x58765132; +CHECKREG r1, 0x58765132; +CHECKREG r2, 0x58765132; +CHECKREG r3, 0x58765132; +CHECKREG r4, 0x58765132; +CHECKREG r5, 0x58765132; +CHECKREG r6, 0x58765132; +CHECKREG r7, 0xA789AECD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = ~ R7; +R1 = ~ R7; +R2 = ~ R7; +R3 = ~ R7; +R4 = ~ R7; +R5 = ~ R7; +R7 = ~ R7; +R6 = ~ R7; +CHECKREG r0, 0xA7654377; +CHECKREG r1, 0xA7654377; +CHECKREG r2, 0xA7654377; +CHECKREG r3, 0xA7654377; +CHECKREG r4, 0xA7654377; +CHECKREG r5, 0xA7654377; +CHECKREG r6, 0x589ABC88; +CHECKREG r7, 0xA7654377; + + +pass diff --git a/sim/testsuite/bfin/c_alu2op_conv_xb.s b/sim/testsuite/bfin/c_alu2op_conv_xb.s new file mode 100644 index 0000000..779a790 --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_conv_xb.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_xb/c_alu2op_conv_xb.dsp +// Spec Reference: alu2op convert xb +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.B (X); +R1 = R0.B (X); +R2 = R0.B (X); +R3 = R0.B (X); +R4 = R0.B (X); +R5 = R0.B (X); +R6 = R0.B (X); +R7 = R0.B (X); +CHECKREG r0, 0xFFFFFFBC; +CHECKREG r1, 0xFFFFFFBC; +CHECKREG r2, 0xFFFFFFBC; +CHECKREG r3, 0xFFFFFFBC; +CHECKREG r4, 0xFFFFFFBC; +CHECKREG r5, 0xFFFFFFBC; +CHECKREG r6, 0xFFFFFFBC; +CHECKREG r7, 0xFFFFFFBC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.B (X); +R2 = R1.B (X); +R3 = R1.B (X); +R4 = R1.B (X); +R5 = R1.B (X); +R6 = R1.B (X); +R7 = R1.B (X); +R1 = R1.B (X); +CHECKREG r0, 0x00000059; +CHECKREG r1, 0x00000059; +CHECKREG r2, 0x00000059; +CHECKREG r3, 0x00000059; +CHECKREG r4, 0x00000059; +CHECKREG r5, 0x00000059; +CHECKREG r6, 0x00000059; +CHECKREG r7, 0x00000059; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.B (X); +R1 = R2.B (X); +R3 = R2.B (X); +R4 = R2.B (X); +R5 = R2.B (X); +R6 = R2.B (X); +R7 = R2.B (X); +R2 = R2.B (X); +CHECKREG r0, 0xFFFFFF89; +CHECKREG r1, 0xFFFFFF89; +CHECKREG r2, 0xFFFFFF89; +CHECKREG r3, 0xFFFFFF89; +CHECKREG r4, 0xFFFFFF89; +CHECKREG r5, 0xFFFFFF89; +CHECKREG r6, 0xFFFFFF89; +CHECKREG r7, 0xFFFFFF89; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.B (X); +R1 = R3.B (X); +R2 = R3.B (X); +R4 = R3.B (X); +R5 = R3.B (X); +R6 = R3.B (X); +R7 = R3.B (X); +R3 = R3.B (X); +CHECKREG r0, 0xFFFFFF9A; +CHECKREG r1, 0xFFFFFF9A; +CHECKREG r2, 0xFFFFFF9A; +CHECKREG r3, 0xFFFFFF9A; +CHECKREG r4, 0xFFFFFF9A; +CHECKREG r5, 0xFFFFFF9A; +CHECKREG r6, 0xFFFFFF9A; +CHECKREG r7, 0xFFFFFF9A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.B (X); +R1 = R4.B (X); +R2 = R4.B (X); +R3 = R4.B (X); +R4 = R4.B (X); +R5 = R4.B (X); +R6 = R4.B (X); +R7 = R4.B (X); +CHECKREG r0, 0xFFFFFFAB; +CHECKREG r1, 0xFFFFFFAB; +CHECKREG r2, 0xFFFFFFAB; +CHECKREG r3, 0xFFFFFFAB; +CHECKREG r4, 0xFFFFFFAB; +CHECKREG r5, 0xFFFFFFAB; +CHECKREG r6, 0xFFFFFFAB; +CHECKREG r7, 0xFFFFFFAB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.B (X); +R1 = R5.B (X); +R2 = R5.B (X); +R3 = R5.B (X); +R4 = R5.B (X); +R6 = R5.B (X); +R7 = R5.B (X); +R5 = R5.B (X); +CHECKREG r0, 0xFFFFFFBC; +CHECKREG r1, 0xFFFFFFBC; +CHECKREG r2, 0xFFFFFFBC; +CHECKREG r3, 0xFFFFFFBC; +CHECKREG r4, 0xFFFFFFBC; +CHECKREG r5, 0xFFFFFFBC; +CHECKREG r6, 0xFFFFFFBC; +CHECKREG r7, 0xFFFFFFBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.B (X); +R1 = R6.B (X); +R2 = R6.B (X); +R3 = R6.B (X); +R4 = R6.B (X); +R5 = R6.B (X); +R7 = R6.B (X); +R6 = R6.B (X); +CHECKREG r0, 0xFFFFFFCD; +CHECKREG r1, 0xFFFFFFCD; +CHECKREG r2, 0xFFFFFFCD; +CHECKREG r3, 0xFFFFFFCD; +CHECKREG r4, 0xFFFFFFCD; +CHECKREG r5, 0xFFFFFFCD; +CHECKREG r6, 0xFFFFFFCD; +CHECKREG r7, 0xFFFFFFCD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.B (X); +R1 = R7.B (X); +R2 = R7.B (X); +R3 = R7.B (X); +R4 = R7.B (X); +R5 = R7.B (X); +R6 = R7.B (X); +R7 = R7.B (X); +CHECKREG r0, 0xFFFFFF88; +CHECKREG r1, 0xFFFFFF88; +CHECKREG r2, 0xFFFFFF88; +CHECKREG r3, 0xFFFFFF88; +CHECKREG r4, 0xFFFFFF88; +CHECKREG r5, 0xFFFFFF88; +CHECKREG r6, 0xFFFFFF88; +CHECKREG r7, 0xFFFFFF88; + + +pass diff --git a/sim/testsuite/bfin/c_alu2op_conv_xh.s b/sim/testsuite/bfin/c_alu2op_conv_xh.s new file mode 100644 index 0000000..75b06c0 --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_conv_xh.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_alu2op_conv_xh/c_alu2op_conv_xh.dsp +// Spec Reference: alu2op convert xh +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.L (X); +R1 = R0.L (X); +R2 = R0.L (X); +R3 = R0.L (X); +R4 = R0.L (X); +R5 = R0.L (X); +R6 = R0.L (X); +R7 = R0.L (X); +CHECKREG r0, 0xFFFF9ABC; +CHECKREG r1, 0xFFFF9ABC; +CHECKREG r2, 0xFFFF9ABC; +CHECKREG r3, 0xFFFF9ABC; +CHECKREG r4, 0xFFFF9ABC; +CHECKREG r5, 0xFFFF9ABC; +CHECKREG r6, 0xFFFF9ABC; +CHECKREG r7, 0xFFFF9ABC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.L (X); +R2 = R1.L (X); +R3 = R1.L (X); +R4 = R1.L (X); +R5 = R1.L (X); +R6 = R1.L (X); +R7 = R1.L (X); +R1 = R1.L (X); +CHECKREG r0, 0x00004659; +CHECKREG r1, 0x00004659; +CHECKREG r2, 0x00004659; +CHECKREG r3, 0x00004659; +CHECKREG r4, 0x00004659; +CHECKREG r5, 0x00004659; +CHECKREG r6, 0x00004659; +CHECKREG r7, 0x00004659; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.L (X); +R1 = R2.L (X); +R3 = R2.L (X); +R4 = R2.L (X); +R5 = R2.L (X); +R6 = R2.L (X); +R7 = R2.L (X); +R2 = R2.L (X); +CHECKREG r0, 0x00006789; +CHECKREG r1, 0x00006789; +CHECKREG r2, 0x00006789; +CHECKREG r3, 0x00006789; +CHECKREG r4, 0x00006789; +CHECKREG r5, 0x00006789; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x00006789; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.L (X); +R1 = R3.L (X); +R2 = R3.L (X); +R4 = R3.L (X); +R5 = R3.L (X); +R6 = R3.L (X); +R7 = R3.L (X); +R3 = R3.L (X); +CHECKREG r0, 0x0000789A; +CHECKREG r1, 0x0000789A; +CHECKREG r2, 0x0000789A; +CHECKREG r3, 0x0000789A; +CHECKREG r4, 0x0000789A; +CHECKREG r5, 0x0000789A; +CHECKREG r6, 0x0000789A; +CHECKREG r7, 0x0000789A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.L (X); +R1 = R4.L (X); +R2 = R4.L (X); +R3 = R4.L (X); +R4 = R4.L (X); +R5 = R4.L (X); +R6 = R4.L (X); +R7 = R4.L (X); +CHECKREG r0, 0xFFFFA9AB; +CHECKREG r1, 0xFFFFA9AB; +CHECKREG r2, 0xFFFFA9AB; +CHECKREG r3, 0xFFFFA9AB; +CHECKREG r4, 0xFFFFA9AB; +CHECKREG r5, 0xFFFFA9AB; +CHECKREG r6, 0xFFFFA9AB; +CHECKREG r7, 0xFFFFA9AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.L (X); +R1 = R5.L (X); +R2 = R5.L (X); +R3 = R5.L (X); +R4 = R5.L (X); +R6 = R5.L (X); +R7 = R5.L (X); +R5 = R5.L (X); +CHECKREG r0, 0xFFFF9FBC; +CHECKREG r1, 0xFFFF9FBC; +CHECKREG r2, 0xFFFF9FBC; +CHECKREG r3, 0xFFFF9FBC; +CHECKREG r4, 0xFFFF9FBC; +CHECKREG r5, 0xFFFF9FBC; +CHECKREG r6, 0xFFFF9FBC; +CHECKREG r7, 0xFFFF9FBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.L (X); +R1 = R6.L (X); +R2 = R6.L (X); +R3 = R6.L (X); +R4 = R6.L (X); +R5 = R6.L (X); +R7 = R6.L (X); +R6 = R6.L (X); +CHECKREG r0, 0xFFFFAECD; +CHECKREG r1, 0xFFFFAECD; +CHECKREG r2, 0xFFFFAECD; +CHECKREG r3, 0xFFFFAECD; +CHECKREG r4, 0xFFFFAECD; +CHECKREG r5, 0xFFFFAECD; +CHECKREG r6, 0xFFFFAECD; +CHECKREG r7, 0xFFFFAECD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.L (X); +R1 = R7.L (X); +R2 = R7.L (X); +R3 = R7.L (X); +R4 = R7.L (X); +R5 = R7.L (X); +R6 = R7.L (X); +R7 = R7.L (X); +CHECKREG r0, 0xFFFFBC88; +CHECKREG r1, 0xFFFFBC88; +CHECKREG r2, 0xFFFFBC88; +CHECKREG r3, 0xFFFFBC88; +CHECKREG r4, 0xFFFFBC88; +CHECKREG r5, 0xFFFFBC88; +CHECKREG r6, 0xFFFFBC88; +CHECKREG r7, 0xFFFFBC88; + + +pass diff --git a/sim/testsuite/bfin/c_alu2op_divq.s b/sim/testsuite/bfin/c_alu2op_divq.s new file mode 100644 index 0000000..2a03227 --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_divq.s @@ -0,0 +1,220 @@ +//Original:/testcases/core/c_alu2op_divq/c_alu2op_divq.dsp +// Spec Reference: alu2op divide q +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0.L = 1; +DIVQ ( R1 , R0 ); +DIVQ ( R2 , R0 ); +DIVQ ( R3 , R0 ); +DIVQ ( R4 , R0 ); +DIVQ ( R5 , R0 ); +DIVQ ( R6 , R0 ); +DIVQ ( R7 , R0 ); +DIVQ ( R4 , R0 ); +DIVQ ( R0 , R0 ); +CHECKREG r1, 0x2466ACF1; +CHECKREG r2, 0x4688CF13; +CHECKREG r3, 0x68AAF135; +CHECKREG r4, 0x159C26AD; +CHECKREG r5, 0x2CF33578; +CHECKREG r6, 0x4F15579A; +CHECKREG r7, 0x713779BC; +CHECKREG r0, 0xFFFE0002; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R1.L = -1; +DIVQ ( R0 , R1 ); +DIVQ ( R2 , R1 ); +DIVQ ( R3 , R1 ); +DIVQ ( R4 , R1 ); +DIVQ ( R5 , R1 ); +DIVQ ( R6 , R1 ); +DIVQ ( R7 , R1 ); +DIVQ ( R1 , R1 ); +CHECKREG r0, 0x02440004; +CHECKREG r1, 0x0003FFFE; +CHECKREG r2, 0x2688CF13; +CHECKREG r3, 0x48AEF135; +CHECKREG r4, 0x6AD11357; +CHECKREG r5, 0x8CF33579; +CHECKREG r6, 0xAF15579B; +CHECKREG r7, 0xD13779BD; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x00000000; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 31; +DIVQ ( R0 , R2 ); +DIVQ ( R1 , R2 ); +DIVQ ( R3 , R2 ); +DIVQ ( R4 , R2 ); +DIVQ ( R5 , R2 ); +DIVQ ( R6 , R2 ); +DIVQ ( R7 , R2 ); +DIVQ ( R2 , R2 ); +CHECKREG r0, 0xA2840005; +CHECKREG r1, 0x242AACF1; +CHECKREG r2, 0xFFC2003E; +CHECKREG r3, 0x686EF135; +CHECKREG r4, 0x2A911356; +CHECKREG r5, 0x0D2F3578; +CHECKREG r6, 0xCF51579B; +CHECKREG r7, 0xF0F779BD; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0x00000000; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R3.L = -31; +DIVQ ( R0 , R3 ); +DIVQ ( R1 , R3 ); +DIVQ ( R2 , R3 ); +DIVQ ( R4 , R3 ); +DIVQ ( R5 , R3 ); +DIVQ ( R6 , R3 ); +DIVQ ( R7 , R3 ); +DIVQ ( R3 , R3 ); +CHECKREG r0, 0x02080004; +CHECKREG r1, 0x042AACF1; +CHECKREG r2, 0x26C8CF13; +CHECKREG r3, 0x003FFFC2; +CHECKREG r4, 0x6B0D1357; +CHECKREG r5, 0x8D2F3579; +CHECKREG r6, 0xAF51579B; +CHECKREG r7, 0xD17379BD; + +imm32 r0, 0x00000001; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x00000000; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R4.L = 15; +DIVQ ( R1 , R4 ); +DIVQ ( R2 , R4 ); +DIVQ ( R3 , R4 ); +DIVQ ( R0 , R4 ); +DIVQ ( R5 , R4 ); +DIVQ ( R6 , R4 ); +DIVQ ( R7 , R4 ); +DIVQ ( R4 , R4 ); +CHECKREG r0, 0xFFE20002; +CHECKREG r1, 0x2486ACF1; +CHECKREG r2, 0x466CCF13; +CHECKREG r3, 0x688EF135; +CHECKREG r4, 0x001E001F; +CHECKREG r5, 0x2D0F3578; +CHECKREG r6, 0x4F31579A; +CHECKREG r7, 0x715379BC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0x00000000; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R5.L = -15; +DIVQ ( R0 , R5 ); +DIVQ ( R1 , R5 ); +DIVQ ( R2 , R5 ); +DIVQ ( R3 , R5 ); +DIVQ ( R4 , R5 ); +DIVQ ( R6 , R5 ); +DIVQ ( R7 , R5 ); +DIVQ ( R5 , R5 ); +CHECKREG r0, 0x02640004; +CHECKREG r1, 0xFFE20001; +CHECKREG r2, 0x26A8CF13; +CHECKREG r3, 0x48CAF135; +CHECKREG r4, 0x6AED1357; +CHECKREG r5, 0x001FFFE2; +CHECKREG r6, 0xAF31579B; +CHECKREG r7, 0xD15379BD; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0xb1256790; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x00000000; +imm32 r7, 0x789abcde; +R6.L = 24; +DIVQ ( R0 , R6 ); +DIVQ ( R1 , R6 ); +DIVQ ( R2 , R6 ); +DIVQ ( R3 , R6 ); +DIVQ ( R4 , R6 ); +DIVQ ( R5 , R6 ); +DIVQ ( R7 , R6 ); +DIVQ ( R6 , R6 ); +CHECKREG r0, 0xA2760005; +CHECKREG r1, 0x2438ACF1; +CHECKREG r2, 0x621ACF20; +CHECKREG r3, 0x68DCF135; +CHECKREG r4, 0x2A9F1356; +CHECKREG r5, 0x0D213578; +CHECKREG r6, 0xFFD00030; +CHECKREG r7, 0xF16579BD; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0x00000000; +R7.L = -24; +DIVQ ( R0 , R7 ); +DIVQ ( R1 , R7 ); +DIVQ ( R2 , R7 ); +DIVQ ( R3 , R7 ); +DIVQ ( R4 , R7 ); +DIVQ ( R5 , R7 ); +DIVQ ( R6 , R7 ); +DIVQ ( R7 , R7 ); +CHECKREG r0, 0x02160004; +CHECKREG r1, 0x0438ACF1; +CHECKREG r2, 0x26BACF13; +CHECKREG r3, 0x48DCF135; +CHECKREG r4, 0x6AFF1357; +CHECKREG r5, 0x8D213579; +CHECKREG r6, 0xAF43579B; +CHECKREG r7, 0x0031FFD0; + + +pass diff --git a/sim/testsuite/bfin/c_alu2op_divs.s b/sim/testsuite/bfin/c_alu2op_divs.s new file mode 100644 index 0000000..f0fc091 --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_divs.s @@ -0,0 +1,220 @@ +//Original:/testcases/core/c_alu2op_divs/c_alu2op_divs.dsp +// Spec Reference: alu2op divide s +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0.L = 1; +DIVS ( R1 , R0 ); +DIVS ( R2 , R0 ); +DIVS ( R3 , R0 ); +DIVS ( R4 , R0 ); +DIVS ( R5 , R0 ); +DIVS ( R6 , R0 ); +DIVS ( R7 , R0 ); +DIVS ( R4 , R0 ); +DIVS ( R0 , R0 ); +CHECKREG r1, 0x2468ACF0; +CHECKREG r2, 0x468ACF12; +CHECKREG r3, 0x68ACF134; +CHECKREG r4, 0x159E26AE; +CHECKREG r5, 0x2CF13579; +CHECKREG r6, 0x4F13579B; +CHECKREG r7, 0x713579BD; +CHECKREG r0, 0x00000002; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R1.L = -1; +DIVS ( R0 , R1 ); +DIVS ( R2 , R1 ); +DIVS ( R3 , R1 ); +DIVS ( R4 , R1 ); +DIVS ( R5 , R1 ); +DIVS ( R6 , R1 ); +DIVS ( R7 , R1 ); +DIVS ( R1 , R1 ); +CHECKREG r0, 0x02460005; +CHECKREG r1, 0x0001FFFF; +CHECKREG r2, 0x268ACF12; +CHECKREG r3, 0x48ACF134; +CHECKREG r4, 0x6ACF1356; +CHECKREG r5, 0x8CF13578; +CHECKREG r6, 0xAF13579A; +CHECKREG r7, 0xD13579BC; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x00000000; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 31; +DIVS ( R0 , R2 ); +DIVS ( R1 , R2 ); +DIVS ( R3 , R2 ); +DIVS ( R4 , R2 ); +DIVS ( R5 , R2 ); +DIVS ( R6 , R2 ); +DIVS ( R7 , R2 ); +DIVS ( R2 , R2 ); +CHECKREG r0, 0xA2460004; +CHECKREG r1, 0x2468ACF0; +CHECKREG r2, 0x0000003E; +CHECKREG r3, 0x68ACF134; +CHECKREG r4, 0x2ACF1357; +CHECKREG r5, 0x0CF13579; +CHECKREG r6, 0xCF13579A; +CHECKREG r7, 0xF13579BC; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0x00000000; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R3.L = -31; +DIVS ( R0 , R3 ); +DIVS ( R1 , R3 ); +DIVS ( R2 , R3 ); +DIVS ( R4 , R3 ); +DIVS ( R5 , R3 ); +DIVS ( R6 , R3 ); +DIVS ( R7 , R3 ); +DIVS ( R3 , R3 ); +CHECKREG r0, 0x02460005; +CHECKREG r1, 0x0468ACF0; +CHECKREG r2, 0x268ACF12; +CHECKREG r3, 0x0001FFC3; +CHECKREG r4, 0x6ACF1356; +CHECKREG r5, 0x8CF13578; +CHECKREG r6, 0xAF13579A; +CHECKREG r7, 0xD13579BC; + +imm32 r0, 0x00000001; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x00000000; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R4.L = 15; +DIVS ( R1 , R4 ); +DIVS ( R2 , R4 ); +DIVS ( R3 , R4 ); +DIVS ( R0 , R4 ); +DIVS ( R5 , R4 ); +DIVS ( R6 , R4 ); +DIVS ( R7 , R4 ); +DIVS ( R4 , R4 ); +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x2468ACF0; +CHECKREG r2, 0x468ACF12; +CHECKREG r3, 0x68ACF134; +CHECKREG r4, 0x0000001E; +CHECKREG r5, 0x2CF13579; +CHECKREG r6, 0x4F13579B; +CHECKREG r7, 0x713579BD; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0x00000000; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R5.L = -15; +DIVS ( R0 , R5 ); +DIVS ( R1 , R5 ); +DIVS ( R2 , R5 ); +DIVS ( R3 , R5 ); +DIVS ( R4 , R5 ); +DIVS ( R6 , R5 ); +DIVS ( R7 , R5 ); +DIVS ( R5 , R5 ); +CHECKREG r0, 0x02460005; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x268ACF12; +CHECKREG r3, 0x48ACF134; +CHECKREG r4, 0x6ACF1356; +CHECKREG r5, 0x0001FFE3; +CHECKREG r6, 0xAF13579A; +CHECKREG r7, 0xD13579BC; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0xb1256790; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x00000000; +imm32 r7, 0x789abcde; +R6.L = 24; +DIVS ( R0 , R6 ); +DIVS ( R1 , R6 ); +DIVS ( R2 , R6 ); +DIVS ( R3 , R6 ); +DIVS ( R4 , R6 ); +DIVS ( R5 , R6 ); +DIVS ( R7 , R6 ); +DIVS ( R6 , R6 ); +CHECKREG r0, 0xA2460004; +CHECKREG r1, 0x2468ACF0; +CHECKREG r2, 0x624ACF21; +CHECKREG r3, 0x68ACF134; +CHECKREG r4, 0x2ACF1357; +CHECKREG r5, 0x0CF13579; +CHECKREG r6, 0x00000030; +CHECKREG r7, 0xF13579BC; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0x00000000; +R7.L = -24; +DIVS ( R0 , R7 ); +DIVS ( R1 , R7 ); +DIVS ( R2 , R7 ); +DIVS ( R3 , R7 ); +DIVS ( R4 , R7 ); +DIVS ( R5 , R7 ); +DIVS ( R6 , R7 ); +DIVS ( R7 , R7 ); +CHECKREG r0, 0x02460005; +CHECKREG r1, 0x0468ACF0; +CHECKREG r2, 0x268ACF12; +CHECKREG r3, 0x48ACF134; +CHECKREG r4, 0x6ACF1356; +CHECKREG r5, 0x8CF13578; +CHECKREG r6, 0xAF13579A; +CHECKREG r7, 0x0001FFD1; + + +pass diff --git a/sim/testsuite/bfin/c_alu2op_log_l_sft.s b/sim/testsuite/bfin/c_alu2op_log_l_sft.s new file mode 100644 index 0000000..06489ef --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_log_l_sft.s @@ -0,0 +1,220 @@ +//Original:/proj/frio/dv/testcases/core/c_alu2op_log_l_sft/c_alu2op_log_l_sft.dsp +// Spec Reference: alu2op logical left +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x00000000; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x856789ab; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R0.L = 1; + R1 <<= R0; + R2 <<= R0; + R3 <<= R0; + R4 <<= R0; + R5 <<= R0; + R6 <<= R0; + R7 <<= R0; + R4 <<= R0; + R0 <<= R0; + CHECKREG r1, 0x2468ACF0; + CHECKREG r2, 0x468ACF12; + CHECKREG r3, 0x68ACF134; + CHECKREG r4, 0x159E26AC; + CHECKREG r5, 0x2CF13578; + CHECKREG r6, 0x4F13579A; + CHECKREG r7, 0x713579BC; + CHECKREG r0, 0x00000002; + + imm32 r0, 0x01230002; + imm32 r1, 0x00000000; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R1.L = -1; + R0 <<= R1; + R2 <<= R1; + R3 <<= R1; + R4 <<= R1; + R5 <<= R1; + R6 <<= R1; + R7 <<= R1; + R1 <<= R1; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x51230002; + imm32 r1, 0x12345678; + imm32 r2, 0x00000000; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x86789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2.L = 31; + R0 <<= R2; + R1 <<= R2; + R3 <<= R2; + R4 <<= R2; + R5 <<= R2; + R6 <<= R2; + R7 <<= R2; + R2 <<= R2; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x80000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x80000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x80000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0x00000000; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R3.L = -31; + R0 <<= R3; + R1 <<= R3; + R2 <<= R3; + R4 <<= R3; + R5 <<= R3; + R6 <<= R3; + R7 <<= R3; + R3 <<= R3; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x00000001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x00000000; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R4.L = 15; + R1 <<= R4; + R2 <<= R4; + R3 <<= R4; + R0 <<= R4; + R5 <<= R4; + R6 <<= R4; + R7 <<= R4; + R4 <<= R4; + CHECKREG r0, 0x00008000; + CHECKREG r1, 0x2B3C0000; + CHECKREG r2, 0xB3C48000; + CHECKREG r3, 0x3C4D0000; + CHECKREG r4, 0x00078000; + CHECKREG r5, 0x4D5E0000; + CHECKREG r6, 0xD5E68000; + CHECKREG r7, 0x5E6F0000; + + imm32 r0, 0x01230002; + imm32 r1, 0x00000000; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0x00000000; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R5.L = -15; + R0 <<= R5; + R1 <<= R5; + R2 <<= R5; + R3 <<= R5; + R4 <<= R5; + R6 <<= R5; + R7 <<= R5; + R5 <<= R5; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x51230002; + imm32 r1, 0x12345678; + imm32 r2, 0xb1256790; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x86789abc; + imm32 r6, 0x00000000; + imm32 r7, 0x789abcde; + R6.L = 24; + R0 <<= R6; + R1 <<= R6; + R2 <<= R6; + R3 <<= R6; + R4 <<= R6; + R5 <<= R6; + R7 <<= R6; + R6 <<= R6; + CHECKREG r0, 0x02000000; + CHECKREG r1, 0x78000000; + CHECKREG r2, 0x90000000; + CHECKREG r3, 0x9A000000; + CHECKREG r4, 0xAB000000; + CHECKREG r5, 0xBC000000; + CHECKREG r6, 0x18000000; + CHECKREG r7, 0xDE000000; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0x00000000; + R7.L = -24; + R0 <<= R7; + R1 <<= R7; + R2 <<= R7; + R3 <<= R7; + R4 <<= R7; + R5 <<= R7; + R6 <<= R7; + R7 <<= R7; + CHECKREG r0, 0x00; + CHECKREG r1, 0x00; + CHECKREG r2, 0x00; + CHECKREG r3, 0x00; + CHECKREG r4, 0x00; + CHECKREG r5, 0x00; + CHECKREG r6, 0x00; + CHECKREG r7, 0x00; + + pass diff --git a/sim/testsuite/bfin/c_alu2op_log_r_sft.s b/sim/testsuite/bfin/c_alu2op_log_r_sft.s new file mode 100644 index 0000000..fdb14fc --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_log_r_sft.s @@ -0,0 +1,217 @@ +//Original:/proj/frio/dv/testcases/core/c_alu2op_log_r_sft/c_alu2op_log_r_sft.dsp +// Spec Reference: alu2op logical right +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x856789ab; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R0.L = 1; + R1 >>= R0; + R2 >>= R0; + R3 >>= R0; + R4 >>= R0; + R5 >>= R0; + R6 >>= R0; + R7 >>= R0; + R4 >>= R0; + R0 >>= R0; + CHECKREG r1, 0x091A2B3C; + CHECKREG r2, 0x11A2B3C4; + CHECKREG r3, 0x1A2B3C4D; + CHECKREG r4, 0x2159E26A; + CHECKREG r5, 0x4B3C4D5E; + CHECKREG r6, 0x53C4D5E6; + CHECKREG r7, 0x5C4D5E6F; + CHECKREG r0, 0x00000000; + + imm32 r0, 0x01230002; + imm32 r1, 0x00000000; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R1.L = -1; + R0 >>= R1; + R2 >>= R1; + R3 >>= R1; + R4 >>= R1; + R5 >>= R1; + R6 >>= R1; + R7 >>= R1; + R1 >>= R1; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x51230002; + imm32 r1, 0x12345678; + imm32 r2, 0x00000000; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x86789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2.L = 31; + R0 >>= R2; + R1 >>= R2; + R3 >>= R2; + R4 >>= R2; + R5 >>= R2; + R6 >>= R2; + R7 >>= R2; + R2 >>= R2; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000001; + CHECKREG r5, 0x00000001; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0x00000000; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R3.L = -31; + R0 >>= R3; + R1 >>= R3; + R2 >>= R3; + R4 >>= R3; + R5 >>= R3; + R6 >>= R3; + R7 >>= R3; + R3 >>= R3; + CHECKREG r0, 0x00; + CHECKREG r1, 0x0; + CHECKREG r2, 0x0; + CHECKREG r3, 0x0; + CHECKREG r4, 0x0; + CHECKREG r5, 0x0; + CHECKREG r6, 0x0; + CHECKREG r7, 0x0; + + imm32 r0, 0x00000001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x00000000; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R4.L = 15; + R1 >>= R4; + R2 >>= R4; + R3 >>= R4; + R0 >>= R4; + R5 >>= R4; + R6 >>= R4; + R7 >>= R4; + R4 >>= R4; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00002468; + CHECKREG r2, 0x0000468A; + CHECKREG r3, 0x000068AC; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00012CF1; + CHECKREG r6, 0x00014F13; + CHECKREG r7, 0x00017135; + + imm32 r0, 0x01230002; + imm32 r1, 0x00000000; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0x00000000; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R5.L = -15; + R0 >>= R5; + R1 >>= R5; + R2 >>= R5; + R3 >>= R5; + R4 >>= R5; + R6 >>= R5; + R7 >>= R5; + R5 >>= R5; + CHECKREG r0, 0x000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x0000; + CHECKREG r3, 0x0000; + CHECKREG r4, 0x0000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x0000; + CHECKREG r7, 0x0000; + + imm32 r0, 0x51230002; + imm32 r1, 0x12345678; + imm32 r2, 0xb1256790; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x86789abc; + imm32 r6, 0x00000000; + imm32 r7, 0x789abcde; + R6.L = 24; + R0 >>= R6; + R1 >>= R6; + R2 >>= R6; + R3 >>= R6; + R4 >>= R6; + R5 >>= R6; + R7 >>= R6; + R6 >>= R6; + CHECKREG r0, 0x00000051; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x000000B1; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000095; + CHECKREG r5, 0x00000086; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000078; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0x00000000; + R7.L = -24; + R0 >>= R7; + R1 >>= R7; + R2 >>= R7; + R3 >>= R7; + R4 >>= R7; + R5 >>= R7; + R6 >>= R7; + R7 >>= R7; + CHECKREG r0, 0x00; + CHECKREG r1, 0x00; + CHECKREG r2, 0x00; + CHECKREG r3, 0x00; + CHECKREG r4, 0x00; + CHECKREG r5, 0x00; + CHECKREG r6, 0x00; + CHECKREG r7, 0x00; + + pass diff --git a/sim/testsuite/bfin/c_alu2op_shadd_1.s b/sim/testsuite/bfin/c_alu2op_shadd_1.s new file mode 100644 index 0000000..73e39ec --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_shadd_1.s @@ -0,0 +1,209 @@ +//Original:/testcases/core/c_alu2op_shadd_1/c_alu2op_shadd_1.dsp +// Spec Reference: alu2op shadd 1 +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x03417990; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R1 = ( R1 + R0 ) << 1; +R2 = ( R2 + R0 ) << 1; +R3 = ( R3 + R0 ) << 1; +R4 = ( R4 + R0 ) << 1; +R5 = ( R5 + R0 ) << 1; +R6 = ( R6 + R0 ) << 1; +R7 = ( R7 + R0 ) << 1; +R0 = ( R0 + R0 ) << 1; +CHECKREG r0, 0x0D05E640; +CHECKREG r1, 0x2AE5A010; +CHECKREG r2, 0x4D05C232; +CHECKREG r3, 0x6F25E454; +CHECKREG r4, 0x11460676; +CHECKREG r5, 0x33662898; +CHECKREG r6, 0x55864ABA; +CHECKREG r7, 0x77A66CDC; + +imm32 r0, 0x03457290; +imm32 r1, 0x12345278; +imm32 r2, 0x23456289; +imm32 r3, 0x3456729a; +imm32 r4, 0x856782ab; +imm32 r5, 0x967892bc; +imm32 r6, 0xa789a2cd; +imm32 r7, 0xb89ab2de; +R0 = ( R0 + R1 ) << 1; +R2 = ( R2 + R1 ) << 1; +R3 = ( R3 + R1 ) << 1; +R4 = ( R4 + R1 ) << 1; +R5 = ( R5 + R1 ) << 1; +R6 = ( R6 + R1 ) << 1; +R7 = ( R7 + R1 ) << 1; +R1 = ( R1 + R1 ) << 1; +CHECKREG r0, 0x2AF38A10; +CHECKREG r1, 0x48D149E0; +CHECKREG r2, 0x6AF36A02; +CHECKREG r3, 0x8D158A24; +CHECKREG r4, 0x2F37AA46; +CHECKREG r5, 0x5159CA68; +CHECKREG r6, 0x737BEA8A; +CHECKREG r7, 0x959E0AAC; + +imm32 r0, 0x03457930; +imm32 r1, 0x12345638; +imm32 r2, 0x23456739; +imm32 r3, 0x3456783a; +imm32 r4, 0x8567893b; +imm32 r5, 0x96789a3c; +imm32 r6, 0xa789ab3d; +imm32 r7, 0xb89abc3e; +R0 = ( R0 + R2 ) << 1; +R1 = ( R1 + R2 ) << 1; +R3 = ( R3 + R2 ) << 1; +R4 = ( R4 + R2 ) << 1; +R5 = ( R5 + R2 ) << 1; +R6 = ( R6 + R2 ) << 1; +R7 = ( R7 + R2 ) << 1; +R2 = ( R2 + R2 ) << 1; +CHECKREG r0, 0x4D15C0D2; +CHECKREG r1, 0x6AF37AE2; +CHECKREG r2, 0x8D159CE4; +CHECKREG r3, 0xAF37BEE6; +CHECKREG r4, 0x5159E0E8; +CHECKREG r5, 0x737C02EA; +CHECKREG r6, 0x959E24EC; +CHECKREG r7, 0xB7C046EE; + +imm32 r0, 0x04457990; +imm32 r1, 0x14345678; +imm32 r2, 0x24456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x846789ab; +imm32 r5, 0x94789abc; +imm32 r6, 0xa489abcd; +imm32 r7, 0xb49abcde; +R0 = ( R0 + R3 ) << 1; +R1 = ( R1 + R3 ) << 1; +R2 = ( R2 + R3 ) << 1; +R4 = ( R4 + R3 ) << 1; +R5 = ( R5 + R3 ) << 1; +R6 = ( R6 + R3 ) << 1; +R7 = ( R7 + R3 ) << 1; +R3 = ( R3 + R3 ) << 1; +CHECKREG r0, 0x7137E454; +CHECKREG r1, 0x91159E24; +CHECKREG r2, 0xB137C046; +CHECKREG r3, 0xD159E268; +CHECKREG r4, 0x717C048A; +CHECKREG r5, 0x919E26AC; +CHECKREG r6, 0xB1C048CE; +CHECKREG r7, 0xD1E26AF0; + +imm32 r0, 0x03417990; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R0 = ( R0 + R4 ) << 1; +R1 = ( R1 + R4 ) << 1; +R2 = ( R2 + R4 ) << 1; +R3 = ( R3 + R4 ) << 1; +R5 = ( R5 + R4 ) << 1; +R6 = ( R6 + R4 ) << 1; +R7 = ( R7 + R4 ) << 1; +R4 = ( R4 + R4 ) << 1; +CHECKREG r0, 0x11460676; +CHECKREG r1, 0x2F25C046; +CHECKREG r2, 0x5145E268; +CHECKREG r3, 0x7366048A; +CHECKREG r4, 0x158626AC; +CHECKREG r5, 0x37A648CE; +CHECKREG r6, 0x59C66AF0; +CHECKREG r7, 0x7BE68D12; + +imm32 r0, 0x03457290; +imm32 r1, 0x12345278; +imm32 r2, 0x23456289; +imm32 r3, 0x3456729a; +imm32 r4, 0x856782ab; +imm32 r5, 0x967892bc; +imm32 r6, 0xa789a2cd; +imm32 r7, 0xb89ab2de; +R0 = ( R0 + R5 ) << 1; +R1 = ( R1 + R5 ) << 1; +R2 = ( R2 + R5 ) << 1; +R3 = ( R3 + R5 ) << 1; +R4 = ( R4 + R5 ) << 1; +R6 = ( R6 + R5 ) << 1; +R7 = ( R7 + R5 ) << 1; +R5 = ( R5 + R5 ) << 1; +CHECKREG r0, 0x337C0A98; +CHECKREG r1, 0x5159CA68; +CHECKREG r2, 0x737BEA8A; +CHECKREG r3, 0x959E0AAC; +CHECKREG r4, 0x37C02ACE; +CHECKREG r5, 0x59E24AF0; +CHECKREG r6, 0x7C046B12; +CHECKREG r7, 0x9E268B34; + +imm32 r0, 0x03457930; +imm32 r1, 0x12345638; +imm32 r2, 0x23456739; +imm32 r3, 0x3456783a; +imm32 r4, 0x8567893b; +imm32 r5, 0x96789a3c; +imm32 r6, 0xa789ab3d; +imm32 r7, 0xb89abc3e; +R0 = ( R0 + R6 ) << 1; +R1 = ( R1 + R6 ) << 1; +R2 = ( R2 + R6 ) << 1; +R3 = ( R3 + R6 ) << 1; +R4 = ( R4 + R6 ) << 1; +R5 = ( R5 + R6 ) << 1; +R7 = ( R7 + R6 ) << 1; +R6 = ( R6 + R6 ) << 1; +CHECKREG r0, 0x559E48DA; +CHECKREG r1, 0x737C02EA; +CHECKREG r2, 0x959E24EC; +CHECKREG r3, 0xB7C046EE; +CHECKREG r4, 0x59E268F0; +CHECKREG r5, 0x7C048AF2; +CHECKREG r6, 0x9E26ACF4; +CHECKREG r7, 0xC048CEF6; + +imm32 r0, 0x04457990; +imm32 r1, 0x14345678; +imm32 r2, 0x24456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x846789ab; +imm32 r5, 0x94789abc; +imm32 r6, 0xa489abcd; +imm32 r7, 0xb49abcde; +R0 = ( R0 + R7 ) << 1; +R1 = ( R1 + R7 ) << 1; +R2 = ( R2 + R7 ) << 1; +R3 = ( R3 + R7 ) << 1; +R4 = ( R4 + R7 ) << 1; +R5 = ( R5 + R7 ) << 1; +R6 = ( R6 + R7 ) << 1; +R7 = ( R7 + R7 ) << 1; +CHECKREG r0, 0x71C06CDC; +CHECKREG r1, 0x919E26AC; +CHECKREG r2, 0xB1C048CE; +CHECKREG r3, 0xD1E26AF0; +CHECKREG r4, 0x72048D12; +CHECKREG r5, 0x9226AF34; +CHECKREG r6, 0xB248D156; +CHECKREG r7, 0xD26AF378; +pass diff --git a/sim/testsuite/bfin/c_alu2op_shadd_2.s b/sim/testsuite/bfin/c_alu2op_shadd_2.s new file mode 100644 index 0000000..b9812f4 --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_shadd_2.s @@ -0,0 +1,209 @@ +//Original:/testcases/core/c_alu2op_shadd_2/c_alu2op_shadd_2.dsp +// Spec Reference: alu2op shadd 2 +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x03417990; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R1 = ( R1 + R0 ) << 2; +R2 = ( R2 + R0 ) << 2; +R3 = ( R3 + R0 ) << 2; +R4 = ( R4 + R0 ) << 2; +R5 = ( R5 + R0 ) << 2; +R6 = ( R6 + R0 ) << 2; +R7 = ( R7 + R0 ) << 2; +R0 = ( R0 + R0 ) << 2; +CHECKREG r0, 0x1A0BCC80; +CHECKREG r1, 0x55CB4020; +CHECKREG r2, 0x9A0B8464; +CHECKREG r3, 0xDE4BC8A8; +CHECKREG r4, 0x228C0CEC; +CHECKREG r5, 0x66CC5130; +CHECKREG r6, 0xAB0C9574; +CHECKREG r7, 0xEF4CD9B8; + +imm32 r0, 0x03457290; +imm32 r1, 0x12345278; +imm32 r2, 0x23456289; +imm32 r3, 0x3456729a; +imm32 r4, 0x856782ab; +imm32 r5, 0x967892bc; +imm32 r6, 0xa789a2cd; +imm32 r7, 0xb89ab2de; +R0 = ( R0 + R1 ) << 2; +R2 = ( R2 + R1 ) << 2; +R3 = ( R3 + R1 ) << 2; +R4 = ( R4 + R1 ) << 2; +R5 = ( R5 + R1 ) << 2; +R6 = ( R6 + R1 ) << 2; +R7 = ( R7 + R1 ) << 2; +R1 = ( R1 + R1 ) << 2; +CHECKREG r0, 0x55E71420; +CHECKREG r1, 0x91A293C0; +CHECKREG r2, 0xD5E6D404; +CHECKREG r3, 0x1A2B1448; +CHECKREG r4, 0x5E6F548C; +CHECKREG r5, 0xA2B394D0; +CHECKREG r6, 0xE6F7D514; +CHECKREG r7, 0x2B3C1558; + +imm32 r0, 0x03457930; +imm32 r1, 0x12345638; +imm32 r2, 0x23456739; +imm32 r3, 0x3456783a; +imm32 r4, 0x8567893b; +imm32 r5, 0x96789a3c; +imm32 r6, 0xa789ab3d; +imm32 r7, 0xb89abc3e; +R0 = ( R0 + R2 ) << 2; +R1 = ( R1 + R2 ) << 2; +R3 = ( R3 + R2 ) << 2; +R4 = ( R4 + R2 ) << 2; +R5 = ( R5 + R2 ) << 2; +R6 = ( R6 + R2 ) << 2; +R7 = ( R7 + R2 ) << 2; +R2 = ( R2 + R2 ) << 2; +CHECKREG r0, 0x9A2B81A4; +CHECKREG r1, 0xD5E6F5C4; +CHECKREG r2, 0x1A2B39C8; +CHECKREG r3, 0x5E6F7DCC; +CHECKREG r4, 0xA2B3C1D0; +CHECKREG r5, 0xE6F805D4; +CHECKREG r6, 0x2B3C49D8; +CHECKREG r7, 0x6F808DDC; + +imm32 r0, 0x04457990; +imm32 r1, 0x14345678; +imm32 r2, 0x24456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x846789ab; +imm32 r5, 0x94789abc; +imm32 r6, 0xa489abcd; +imm32 r7, 0xb49abcde; +R0 = ( R0 + R3 ) << 2; +R1 = ( R1 + R3 ) << 2; +R2 = ( R2 + R3 ) << 2; +R4 = ( R4 + R3 ) << 2; +R5 = ( R5 + R3 ) << 2; +R6 = ( R6 + R3 ) << 2; +R7 = ( R7 + R3 ) << 2; +R3 = ( R3 + R3 ) << 2; +CHECKREG r0, 0xE26FC8A8; +CHECKREG r1, 0x222B3C48; +CHECKREG r2, 0x626F808C; +CHECKREG r3, 0xA2B3C4D0; +CHECKREG r4, 0xE2F80914; +CHECKREG r5, 0x233C4D58; +CHECKREG r6, 0x6380919C; +CHECKREG r7, 0xA3C4D5E0; + +imm32 r0, 0x03417990; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R0 = ( R0 + R4 ) << 2; +R1 = ( R1 + R4 ) << 2; +R2 = ( R2 + R4 ) << 2; +R3 = ( R3 + R4 ) << 2; +R5 = ( R5 + R4 ) << 2; +R6 = ( R6 + R4 ) << 2; +R7 = ( R7 + R4 ) << 2; +R4 = ( R4 + R4 ) << 2; +CHECKREG r0, 0x228C0CEC; +CHECKREG r1, 0x5E4B808C; +CHECKREG r2, 0xA28BC4D0; +CHECKREG r3, 0xE6CC0914; +CHECKREG r4, 0x2B0C4D58; +CHECKREG r5, 0x6F4C919C; +CHECKREG r6, 0xB38CD5E0; +CHECKREG r7, 0xF7CD1A24; + +imm32 r0, 0x03457290; +imm32 r1, 0x12345278; +imm32 r2, 0x23456289; +imm32 r3, 0x3456729a; +imm32 r4, 0x856782ab; +imm32 r5, 0x967892bc; +imm32 r6, 0xa789a2cd; +imm32 r7, 0xb89ab2de; +R0 = ( R0 + R5 ) << 2; +R1 = ( R1 + R5 ) << 2; +R2 = ( R2 + R5 ) << 2; +R3 = ( R3 + R5 ) << 2; +R4 = ( R4 + R5 ) << 2; +R6 = ( R6 + R5 ) << 2; +R7 = ( R7 + R5 ) << 2; +R5 = ( R5 + R5 ) << 2; +CHECKREG r0, 0x66F81530; +CHECKREG r1, 0xA2B394D0; +CHECKREG r2, 0xE6F7D514; +CHECKREG r3, 0x2B3C1558; +CHECKREG r4, 0x6F80559C; +CHECKREG r5, 0xB3C495E0; +CHECKREG r6, 0xF808D624; +CHECKREG r7, 0x3C4D1668; + +imm32 r0, 0x03457930; +imm32 r1, 0x12345638; +imm32 r2, 0x23456739; +imm32 r3, 0x3456783a; +imm32 r4, 0x8567893b; +imm32 r5, 0x96789a3c; +imm32 r6, 0xa789ab3d; +imm32 r7, 0xb89abc3e; +R0 = ( R0 + R6 ) << 2; +R1 = ( R1 + R6 ) << 2; +R2 = ( R2 + R6 ) << 2; +R3 = ( R3 + R6 ) << 2; +R4 = ( R4 + R6 ) << 2; +R5 = ( R5 + R6 ) << 2; +R7 = ( R7 + R6 ) << 2; +R6 = ( R6 + R6 ) << 2; +CHECKREG r0, 0xAB3C91B4; +CHECKREG r1, 0xE6F805D4; +CHECKREG r2, 0x2B3C49D8; +CHECKREG r3, 0x6F808DDC; +CHECKREG r4, 0xB3C4D1E0; +CHECKREG r5, 0xF80915E4; +CHECKREG r6, 0x3C4D59E8; +CHECKREG r7, 0x80919DEC; + +imm32 r0, 0x04457990; +imm32 r1, 0x14345678; +imm32 r2, 0x24456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x846789ab; +imm32 r5, 0x94789abc; +imm32 r6, 0xa489abcd; +imm32 r7, 0xb49abcde; +R0 = ( R0 + R7 ) << 2; +R1 = ( R1 + R7 ) << 2; +R2 = ( R2 + R7 ) << 2; +R3 = ( R3 + R7 ) << 2; +R4 = ( R4 + R7 ) << 2; +R5 = ( R5 + R7 ) << 2; +R6 = ( R6 + R7 ) << 2; +R7 = ( R7 + R7 ) << 2; +CHECKREG r0, 0xE380D9B8; +CHECKREG r1, 0x233C4D58; +CHECKREG r2, 0x6380919C; +CHECKREG r3, 0xA3C4D5E0; +CHECKREG r4, 0xE4091A24; +CHECKREG r5, 0x244D5E68; +CHECKREG r6, 0x6491A2AC; +CHECKREG r7, 0xA4D5E6F0; +pass diff --git a/sim/testsuite/bfin/c_br_preg_killed_ac.s b/sim/testsuite/bfin/c_br_preg_killed_ac.s new file mode 100644 index 0000000..67a5bdc --- /dev/null +++ b/sim/testsuite/bfin/c_br_preg_killed_ac.s @@ -0,0 +1,82 @@ +//Original:/testcases/seq/c_br_preg_killed_ac/c_br_preg_killed_ac.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; + + P4 = 4; + P2 = 2; + loadsym P5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + IF !CC JUMP LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + JUMP ( PC + P4 ); //brf LABEL2; // (bp); + CC = ! CC; +LABEL2: + JUMP ( PC + P4 ); //brf LABEL3; // (bp); + R2 = - R2; // ALU2op killed +LABEL3: + JUMP ( PC + P4 ); //brf LABEL4; + R3 <<= 2; // LOGI2op killed +LABEL4: + JUMP ( PC + P4 ); //brf LABEL5; + R0 = R1 + R2; // COMP3op killed +LABEL5: + JUMP ( PC + P4 ); //brf LABEL6; + R4 += 3; // COMPI2opD killed +LABEL6: + JUMP ( PC + P4 ); //brf LABEL7; // (bp); + R5 = 25; // LDIMMHALF killed +LABEL7: + JUMP ( PC + P4 ); //brf LABEL8; + R6 = CC; // CC2REG killed +LABEL8: + JUMP ( PC + P4 ); //brf LABEL9; + JUMP ( PC + P2 ); //BAD1; // UJUMP killed +LABEL9: + JUMP ( PC + P4 ); //brf LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/sim/testsuite/bfin/c_br_preg_killed_ex1.s b/sim/testsuite/bfin/c_br_preg_killed_ex1.s new file mode 100644 index 0000000..7a18f53 --- /dev/null +++ b/sim/testsuite/bfin/c_br_preg_killed_ex1.s @@ -0,0 +1,85 @@ +//Original:/testcases/seq/c_br_preg_killed_ex1/c_br_preg_killed_ex1.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + P2 = 4; + loadsym p5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + IF !CC JUMP LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + JUMP ( PC + P2 ); //brf LABEL2; // (bp); + CC = ! CC; +LABEL2: + IF !CC JUMP LABEL3; // (bp); + R2 = - R2; // ALU2op killed +LABEL3: + IF !CC JUMP LABEL4; + R3 <<= 2; // LOGI2op killed +LABEL4: + IF !CC JUMP LABEL5; + R0 = R1 + R2; // COMP3op killed +LABEL5: + IF !CC JUMP LABEL6; + R4 += 3; // COMPI2opD killed +LABEL6: + IF !CC JUMP LABEL7; // (bp); + R5 = 25; // LDIMMHALF killed +LABEL7: + IF !CC JUMP LABEL8; + R6 = CC; // CC2REG killed +LABEL8: + IF !CC JUMP LABEL9; + JUMP.S BAD1; // UJUMP killed +LABEL9: + IF !CC JUMP LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/sim/testsuite/bfin/c_br_preg_stall_ac.s b/sim/testsuite/bfin/c_br_preg_stall_ac.s new file mode 100644 index 0000000..7ac29e6 --- /dev/null +++ b/sim/testsuite/bfin/c_br_preg_stall_ac.s @@ -0,0 +1,75 @@ +//Original:/testcases/seq/c_br_preg_stall_ac/c_br_preg_stall_ac.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + /* This test likes to assume the current [SP] is valid */ + SP += -12; + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST; + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + P1 = 4; + P2 = 6; + loadsym P5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + R0 = CC; + IF CC R1 = R0; + [ SP ] = P2; + P2 = [ SP ]; + JUMP ( PC + P2 ); //brf LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1' + CC = ! CC; +LABEL2: + JUMP ( PC + P1 ); //brf LABEL3; + JUMP ( PC + P2 ); //BAD1; // UJUMP killed +LABEL3: + JUMP ( PC + P1 ); //brf LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/sim/testsuite/bfin/c_br_preg_stall_ex1.s b/sim/testsuite/bfin/c_br_preg_stall_ex1.s new file mode 100644 index 0000000..5310edf --- /dev/null +++ b/sim/testsuite/bfin/c_br_preg_stall_ex1.s @@ -0,0 +1,70 @@ +//Original:/testcases/seq/c_br_preg_stall_ex1/c_br_preg_stall_ex1.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + P1 = 4; + P2 = 6; + loadsym p5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + R0 = CC; + IF CC R1 = R0; + IF !CC JUMP LABEL1; + R0 = LC0; + R2 = R1 + R0; +LABEL1: + JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1' + CC = ! CC; +LABEL2: + JUMP ( PC + P1 ); //brf LABEL3; + JUMP ( PC + P2 ); //BAD1; // UJUMP killed +LABEL3: + JUMP ( PC + P1 ); //brf LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/sim/testsuite/bfin/c_brcc_bp1.s b/sim/testsuite/bfin/c_brcc_bp1.s new file mode 100644 index 0000000..012d1a5 --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_bp1.s @@ -0,0 +1,45 @@ +//Original:/testcases/core/c_brcc_bp1/c_brcc_bp1.dsp +// Spec Reference: brcc bp +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1; // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3; // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2; // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_brcc_bp2.s b/sim/testsuite/bfin/c_brcc_bp2.s new file mode 100644 index 0000000..1fc7278 --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_bp2.s @@ -0,0 +1,45 @@ +//Original:/testcases/core/c_brcc_bp2/c_brcc_bp2.dsp +// Spec Reference: brcc bp +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3; // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2; // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_brcc_bp3.s b/sim/testsuite/bfin/c_brcc_bp3.s new file mode 100644 index 0000000..0a21994 --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_bp3.s @@ -0,0 +1,47 @@ +//Original:/testcases/core/c_brcc_bp3/c_brcc_bp3.dsp +// Spec Reference: brcc bp +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3 (BP); // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2; // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_brcc_bp4.s b/sim/testsuite/bfin/c_brcc_bp4.s new file mode 100644 index 0000000..39f64b1 --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_bp4.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_bp4/c_brcc_bp4.dsp +// Spec Reference: brcc bp +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3 (BP); // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2 (BP); // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_brcc_brf_bp.s b/sim/testsuite/bfin/c_brcc_brf_bp.s new file mode 100644 index 0000000..7ca29c5 --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_brf_bp.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_brf_bp/c_brcc_brf_bp.dsp +// Spec Reference: brcc brf bp +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + IF !CC JUMP good1 (BP); // branch on false (should branch) + CC = ! CC; // set cc=1 + R1 = 1; // if go here, error +good1: IF !CC JUMP good2 (BP); // branch on false (should branch) +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // + IF !CC JUMP bad2 (BP); // branch on false (should not branch) + CC = ! CC; + IF !CC JUMP good3 (BP); // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF !CC JUMP end; // branch on true (should branch) +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_brcc_brf_brt_bp.s b/sim/testsuite/bfin/c_brcc_brf_brt_bp.s new file mode 100644 index 0000000..c9f2945 --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_brf_brt_bp.s @@ -0,0 +1,47 @@ +//Original:/testcases/core/c_brcc_brf_brt_bp/c_brcc_brf_brt_bp.dsp +// Spec Reference: brcc brfbrt +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000444; +imm32 r5, 0x00000555; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + CC = R4 < R5; + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) + CC = ! CC; + IF !CC JUMP good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF CC JUMP good3 (BP); // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF !CC JUMP bad2 (BP); // branch on true (should not branch) + IF CC JUMP end; // we're done +bad2: R0 = 8; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000444; +CHECKREG r5, 0x00000555; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_brcc_brf_brt_nbp.s b/sim/testsuite/bfin/c_brcc_brf_brt_nbp.s new file mode 100644 index 0000000..32b3bd0 --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_brf_brt_nbp.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_brf_brt_nbp/c_brcc_brf_brt_nbp.dsp +// Spec Reference: brcc brf brt no bp +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1; // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1; // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3; // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2; // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_brcc_brf_fbkwd.s b/sim/testsuite/bfin/c_brcc_brf_fbkwd.s new file mode 100644 index 0000000..371238c --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_brf_fbkwd.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_brf_fbkwd/c_brcc_brf_fbkwd.dsp +// Spec Reference: brcc brf forward/backward +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +ASTAT = R0; + +IF !CC JUMP SUBR; + R1.L = 0xeeee; + R2.L = 0x2222; + R3.L = 0x3333; +JBACK: + R4.L = 0x4444; + + + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00004444; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass + +//.code 0x448 +SUBR: + R1.L = 0x1111; +IF !CC JUMP JBACK; diff --git a/sim/testsuite/bfin/c_brcc_brf_nbp.s b/sim/testsuite/bfin/c_brcc_brf_nbp.s new file mode 100644 index 0000000..52eb0f3 --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_brf_nbp.s @@ -0,0 +1,45 @@ +//Original:/testcases/core/c_brcc_brf_nbp/c_brcc_brf_nbp.dsp +// Spec Reference: brcc brf no bp +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + IF !CC JUMP good1; // branch on false (should branch) + CC = ! CC; // set cc=1 + R1 = 1; // if go here, error +good1: IF !CC JUMP good2; // branch on false (should branch) +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // + IF !CC JUMP bad2; // branch on false (should not branch) + CC = ! CC; + IF !CC JUMP good3; // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF !CC JUMP end; // branch on true (should branch) +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_brcc_brt_bp.s b/sim/testsuite/bfin/c_brcc_brt_bp.s new file mode 100644 index 0000000..d3ad0fc --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_brt_bp.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_brt_bp/c_brcc_brt_bp.dsp +// Spec Reference: brcc brt bp +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // (should branch) + R1 = 1; // if go here, error +good1: IF CC JUMP good2 (BP); // (should branch) +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // + IF CC JUMP bad2 (BP); // (should not branch) + CC = ! CC; + IF CC JUMP good3 (BP); // (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP end (BP); // (should branch) +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_brcc_brt_nbp.s b/sim/testsuite/bfin/c_brcc_brt_nbp.s new file mode 100644 index 0000000..a1c5e6b --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_brt_nbp.s @@ -0,0 +1,45 @@ +//Original:/testcases/core/c_brcc_brt_nbp/c_brcc_brt_nbp.dsp +// Spec Reference: brcc brt no bp +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1; // (should branch) + R1 = 1; // if go here, error +good1: IF CC JUMP good2; // (should branch) +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // + IF CC JUMP bad2; // (should not branch) + CC = ! CC; + IF CC JUMP good3; // (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP end; // (should branch) +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_brcc_kills_dhits.s b/sim/testsuite/bfin/c_brcc_kills_dhits.s new file mode 100644 index 0000000..5224554 --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_kills_dhits.s @@ -0,0 +1,136 @@ +//Original:/testcases/core/c_brcc_kills_dhits/c_brcc_kills_dhits.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + loadsym P5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + IF !CC JUMP LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + IF !CC JUMP LABEL2; // (bp); + CC = ! CC; +LABEL2: + IF !CC JUMP LABEL3; // (bp); + R2 = - R2; // ALU2op killed +LABEL3: + IF !CC JUMP LABEL4; + R3 <<= 2; // LOGI2op killed +LABEL4: + IF !CC JUMP LABEL5; + R0 = R1 + R2; // COMP3op killed +LABEL5: + IF !CC JUMP LABEL6; + R4 += 3; // COMPI2opD killed +LABEL6: + IF !CC JUMP LABEL7; // (bp); + R5 = 25; // LDIMMHALF killed +LABEL7: + IF !CC JUMP LABEL8; + R6 = CC; // CC2REG killed +LABEL8: + IF !CC JUMP LABEL9; + JUMP.S BAD1; // UJUMP killed +LABEL9: + IF !CC JUMP LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + +LABEL10: + IF !CC JUMP LABEL11; + R1 = ( A1 += R4.L * R5.H ), A0 += R4.H * R5.L; +// DSP32MAC killed + +LABEL11: + IF !CC JUMP LABEL12; + R2 = R2 +|+ R3; // DSP32ALU killed + +LABEL12: + IF !CC JUMP LABEL13; + R3 = LSHIFT R2 BY R3.L (V); // dsp32shift killed + +LABEL13: + IF !CC JUMP LABEL14; + R4.H = R1.L << 6; // DSP32SHIFTIMM killed + +LABEL14: + IF !CC JUMP LABEL15; + P2 = P1; // REGMV PREG-PREG killed + +LABEL15: + IF !CC JUMP LABEL16; + R5 = P1; // REGMV Pr-to-Dr killed + +LABEL16: + IF !CC JUMP LABEL17; + ASTAT = R2; // REGMV Dr-to-sys killed + +LABEL17: + IF !CC JUMP LABEL18; + R6 = ASTAT; // REGMV sys-to-Dr killed + +LABEL18: + IF !CC JUMP LABEL19; + [ I0 ] = R2; // DSPLDST store killed + +LABEL19: + IF !CC JUMP end; + R7 = [ I0 ]; // DSPLDST load killed + +end: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/sim/testsuite/bfin/c_brcc_kills_dmiss.s b/sim/testsuite/bfin/c_brcc_kills_dmiss.s new file mode 100644 index 0000000..62bd7e1 --- /dev/null +++ b/sim/testsuite/bfin/c_brcc_kills_dmiss.s @@ -0,0 +1,137 @@ +//Original:/testcases/core/c_brcc_kills_dmiss/c_brcc_kills_dmiss.dsp +// Spec Reference: brcc kills data cache miss +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + loadsym P5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + IF !CC JUMP LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + IF !CC JUMP LABEL2; // (bp); + CC = ! CC; +LABEL2: + IF !CC JUMP LABEL3; // (bp); + R2 = - R2; // ALU2op killed +LABEL3: + IF !CC JUMP LABEL4; + R3 <<= 2; // LOGI2op killed +LABEL4: + IF !CC JUMP LABEL5; + R0 = R1 + R2; // COMP3op killed +LABEL5: + IF !CC JUMP LABEL6; + R4 += 3; // COMPI2opD killed +LABEL6: + IF !CC JUMP LABEL7; // (bp); + R5 = 25; // LDIMMHALF killed +LABEL7: + IF !CC JUMP LABEL8; + R6 = CC; // CC2REG killed +LABEL8: + IF !CC JUMP LABEL9; + JUMP.S BAD1; // UJUMP killed +LABEL9: + IF !CC JUMP LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + +LABEL10: + IF !CC JUMP LABEL11; + R1 = ( A1 += R4.L * R5.H ), A0 += R4.H * R5.L; +// DSP32MAC killed + +LABEL11: + IF !CC JUMP LABEL12; + R2 = R2 +|+ R3; // DSP32ALU killed + +LABEL12: + IF !CC JUMP LABEL13; + R3 = LSHIFT R2 BY R3.L (V); // dsp32shift killed + +LABEL13: + IF !CC JUMP LABEL14; + R4.H = R1.L << 6; // DSP32SHIFTIMM killed + +LABEL14: + IF !CC JUMP LABEL15; + P2 = P1; // REGMV PREG-PREG killed + +LABEL15: + IF !CC JUMP LABEL16; + R5 = P1; // REGMV Pr-to-Dr killed + +LABEL16: + IF !CC JUMP LABEL17; + ASTAT = R2; // REGMV Dr-to-sys killed + +LABEL17: + IF !CC JUMP LABEL18; + R6 = ASTAT; // REGMV sys-to-Dr killed + +LABEL18: + IF !CC JUMP LABEL19; + [ I0 ] = R2; // DSPLDST store killed + +LABEL19: + IF !CC JUMP end; + R7 = [ I0 ]; // DSPLDST load killed + +end: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + + .data +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/sim/testsuite/bfin/c_cactrl_iflush_pr.s b/sim/testsuite/bfin/c_cactrl_iflush_pr.s new file mode 100644 index 0000000..5d85792 --- /dev/null +++ b/sim/testsuite/bfin/c_cactrl_iflush_pr.s @@ -0,0 +1,102 @@ +//Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr/c_cactrl_iflush_pr.dsp +// Spec Reference: c_cactrl iflush_pr +# mach: bfin + +.include "testutils.inc" + start + +// initial values +//p1=0x448; +//imm32 p1, CODE_ADDR_1; + loadsym p1, SUBR1; +// set all regs + + imm32 r0, 0x13545abd; + imm32 r1, 0xadbcfec7; + imm32 r2, 0xa1245679; + imm32 r3, 0x00060007; + imm32 r4, 0xefbc4569; + imm32 r5, 0x1235000b; + imm32 r6, 0x000c000d; + imm32 r7, 0x678e000f; +// The result accumulated in A0 and A1, and stored to a reg half + R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; + R3.H = A1 , A0 = R7.H * R6.L (T); +// begin of iflush + IFLUSH [ P1 ]; // p1 = 0xf00 + R7 = 0; + ASTAT = R7; + IF !CC JUMP SUBR1; +JBACK: + R6 = 0; + +//r4 = (a1 = l*h) M, a0 = h*l (r3,r2); +//r5 a1 = l*h, = (a0 = h*l) (r1,r0) IS; + CHECKREG r2, 0xFFD15679; + CHECKREG r3, 0xFFD00007; + CHECKREG r4, 0x00074569; + CHECKREG r5, 0x12358000; + + pass + +//.code 0x448 +//.code CODE_ADDR_1 +SUBR1: + R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L; + A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2); + IF !CC JUMP JBACK; + NOP; NOP; NOP; NOP; NOP; + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F diff --git a/sim/testsuite/bfin/c_cactrl_iflush_pr_pp.s b/sim/testsuite/bfin/c_cactrl_iflush_pr_pp.s new file mode 100644 index 0000000..96fbdc9 --- /dev/null +++ b/sim/testsuite/bfin/c_cactrl_iflush_pr_pp.s @@ -0,0 +1,100 @@ +//Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr_pp/c_cactrl_iflush_pr_pp.dsp +// Spec Reference: c_cactrl iflush_pr [p++] +# mach: bfin + +.include "testutils.inc" + start + + loadsym p2, SUBR1; +// set all regs + + imm32 r0, 0x13545abd; + imm32 r1, 0xadbcfec7; + imm32 r2, 0xa1245679; + imm32 r3, 0x00060007; + imm32 r4, 0xefbc4569; + imm32 r5, 0x1235000b; + imm32 r6, 0x000c000d; + imm32 r7, 0x678e000f; +// The result accumulated in A0 and A1, and stored to a reg half + R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; + R3.H = A1 , A0 = R7.H * R6.L (T); +// begin of iflush + IFLUSH [ P2 ++ ]; // p2 = 0x448 + R7 = 0; + ASTAT = R7; + IF !CC JUMP SUBR1; +JBACK: + R6 = 0; + +//r4 = (a1 = l*h) M, a0 = h*l (r3,r2); +//r5 a1 = l*h, = (a0 = h*l) (r1,r0) IS; + CHECKREG r2, 0xFFD15679; + CHECKREG r3, 0xFFD00007; + CHECKREG r4, 0x00074569; + CHECKREG r5, 0x12358000; +//CHECKREG p2, 0x00000468; + + pass + +//.code 0x448 +//.code CODE_ADDR_1 +SUBR1: + R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L; + A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2); + IF !CC JUMP JBACK; + NOP; NOP; NOP; NOP; NOP; + +// Pre-load memory witb known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F diff --git a/sim/testsuite/bfin/c_calla_ljump.s b/sim/testsuite/bfin/c_calla_ljump.s new file mode 100644 index 0000000..be1e94f --- /dev/null +++ b/sim/testsuite/bfin/c_calla_ljump.s @@ -0,0 +1,31 @@ +//Original:/testcases/core/c_calla_ljump/c_calla_ljump.dsp +// Spec Reference: progctrl calla ljump +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +JUMP.L SUBR; + +JBACK: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass + +SUBR: // should jump here + R1.L = 0x1111; + JUMP.L JBACK; + R2.L = 0x2222; // should not go here + JUMP.L JBACK; +RTS; diff --git a/sim/testsuite/bfin/c_calla_subr.s b/sim/testsuite/bfin/c_calla_subr.s new file mode 100644 index 0000000..8c651da --- /dev/null +++ b/sim/testsuite/bfin/c_calla_subr.s @@ -0,0 +1,28 @@ +//Original:/testcases/core/c_calla_subr/c_calla_subr.dsp +// Spec Reference: progctrl calla subr +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +CALL SUBR; + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass + +SUBR: // should jump here + R1.L = 0x1111; + RTS; + R2.L = 0x2222; // should not go here + RTS; diff --git a/sim/testsuite/bfin/c_cc2dreg.s b/sim/testsuite/bfin/c_cc2dreg.s new file mode 100644 index 0000000..38aab85 --- /dev/null +++ b/sim/testsuite/bfin/c_cc2dreg.s @@ -0,0 +1,56 @@ +//Original:/testcases/core/c_cc2dreg/c_cc2dreg.dsp +// Spec Reference: cc2dreg +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00120000; +imm32 r2, 0x00000003; +imm32 r3, 0x00000004; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R0; + +CC = R1; +R1 = CC; +CC = R1; +CC = ! CC; +R2 = CC; +CC = R2; +CC = ! CC; +R3 = CC; +CC = R3; +CC = ! CC; +R4 = CC; +CC = R5; +R5 = CC; +CC = R6; +R6 = CC; +CC = ! CC; +R7 = CC; +R0 = CC; + + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + + + + +pass diff --git a/sim/testsuite/bfin/c_cc2stat_cc_ac.S b/sim/testsuite/bfin/c_cc2stat_cc_ac.S new file mode 100644 index 0000000..964f82a --- /dev/null +++ b/sim/testsuite/bfin/c_cc2stat_cc_ac.S @@ -0,0 +1,240 @@ +//Original:/testcases/core/c_cc2stat_cc_ac/c_cc2stat_cc_ac.dsp +// Spec Reference: cc2stat cc ac +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + imm32 r0, _UNSET; + imm32 r1, _UNSET; + imm32 r2, _UNSET; + imm32 r3, _UNSET; + imm32 r4, _UNSET; + imm32 r5, _UNSET; + imm32 r6, _UNSET; + imm32 r7, _UNSET; + +// test CC = AC 0-0, 0-1, 1-0, 1-1 + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + CC = AC0; // + R0 = CC; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + CC = AC0; // + R1 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + CC = AC0; // + R2 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + CC = AC0; // + R3 = CC; // + +// test cc |= AC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + CC |= AC0; // + R4 = CC; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + CC |= AC0; // + R5 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 0 + CC |= AC0; // + R6 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + CC |= AC0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _SET; + +// test CC &= AC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + CC &= AC0; // + R4 = CC; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + CC &= AC0; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + CC &= AC0; // + R6 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + CC &= AC0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _UNSET; + CHECKREG r7, _SET; + +// test CC ^= AC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + CC ^= AC0; // + R4 = CC; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + CC ^= AC0; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + CC ^= AC0; // + R6 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + CC ^= AC0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _UNSET; + +// test AC0 = CC 0-0, 0-1, 1-0, 1-1 + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + AC0 = CC; // + R0 = ASTAT; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + AC0 = CC; // + R1 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + AC0 = CC; // + R2 = ASTAT; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + AC0 = CC; // + R3 = ASTAT; // + +// test AC0 |= CC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + AC0 |= CC; // + R4 = ASTAT; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + AC0 |= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + AC0 |= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + AC0 |= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_AC0|_CC); + CHECKREG r3, (_CC|_AC0); + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0); + CHECKREG r6, (_AC0|_CC); + CHECKREG r7, (_CC|_AC0); + +// test AC0 &= CC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + AC0 &= CC; // + R4 = ASTAT; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + AC0 &= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + AC0 &= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + AC0 &= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AC0); + CHECKREG r3, (_CC|_AC0); + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _CC; + CHECKREG r7, (_CC|_AC0); + +// test AC0 ^= CC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + AC0 ^= CC; // + R4 = ASTAT; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + AC0 ^= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + AC0 ^= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + AC0 ^= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AC0); + CHECKREG r3, (_CC|_AC0); + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0); + CHECKREG r6, (_CC|_AC0); + CHECKREG r7, _CC; + + pass diff --git a/sim/testsuite/bfin/c_cc2stat_cc_an.s b/sim/testsuite/bfin/c_cc2stat_cc_an.s new file mode 100644 index 0000000..d93024f --- /dev/null +++ b/sim/testsuite/bfin/c_cc2stat_cc_an.s @@ -0,0 +1,243 @@ +//Original:/testcases/core/c_cc2stat_cc_an/c_cc2stat_cc_an.dsp +// Spec Reference: cc2stat cc an +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// test CC = AN 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +CC = AN; // +R0 = CC; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +CC = AN; // +R1 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +CC = AN; // +R2 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +CC = AN; // +R3 = CC; // + +// test cc |= AN (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +CC |= AN; // +R4 = CC; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +CC |= AN; // +R5 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 0 +CC |= AN; // +R6 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +CC |= AN; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +// test CC &= AN (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +CC &= AN; // +R4 = CC; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +CC &= AN; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +CC &= AN; // +R6 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +CC &= AN; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +// test CC ^= AN (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +CC ^= AN; // +R4 = CC; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +CC ^= AN; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +CC ^= AN; // +R6 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +CC ^= AN; // +R7 = CC; // + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +// test AN = CC 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +AN = CC; // +R0 = ASTAT; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +AN = CC; // +R1 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +AN = CC; // +R2 = ASTAT; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +AN = CC; // +R3 = ASTAT; // + +// test AN |= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +AN |= CC; // +R4 = ASTAT; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +AN |= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +AN |= CC; // +R6 = ASTAT; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +AN |= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// test AN &= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +AN &= CC; // +R4 = ASTAT; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +AN &= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +AN &= CC; // +R6 = ASTAT; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +AN &= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000022; + +// test AN ^= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +AN ^= CC; // +R4 = ASTAT; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +AN ^= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +AN ^= CC; // +R6 = ASTAT; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +AN ^= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000020; + + +pass diff --git a/sim/testsuite/bfin/c_cc2stat_cc_aq.s b/sim/testsuite/bfin/c_cc2stat_cc_aq.s new file mode 100644 index 0000000..e8b877e --- /dev/null +++ b/sim/testsuite/bfin/c_cc2stat_cc_aq.s @@ -0,0 +1,243 @@ +//Original:/testcases/core/c_cc2stat_cc_aq/c_cc2stat_cc_aq.dsp +// Spec Reference: cc2stat cc aq +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// test CC = AQ 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +CC = AQ; // +R0 = CC; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +CC = AQ; // +R1 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +CC = AQ; // +R2 = CC; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +CC = AQ; // +R3 = CC; // + +// test cc |= AQ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +CC |= AQ; // +R4 = CC; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +CC |= AQ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +CC |= AQ; // +R6 = CC; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +CC |= AQ; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +// test CC &= AQ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +CC &= AQ; // +R4 = CC; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +CC &= AQ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +CC &= AQ; // +R6 = CC; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +CC &= AQ; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +// test CC ^= AQ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +CC ^= AQ; // +R4 = CC; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +CC ^= AQ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +CC ^= AQ; // +R6 = CC; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +CC ^= AQ; // +R7 = CC; // + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +// test AQ = CC 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +AQ = CC; // +R0 = ASTAT; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +AQ = CC; // +R1 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +AQ = CC; // +R2 = ASTAT; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +AQ = CC; // +R3 = ASTAT; // + +// test AQ |= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +AQ |= CC; // +R4 = ASTAT; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +AQ |= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +AQ |= CC; // +R6 = ASTAT; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +AQ |= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000060; +CHECKREG r3, 0x00000060; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000040; +CHECKREG r6, 0x00000060; +CHECKREG r7, 0x00000060; + +// test AQ &= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +AQ &= CC; // +R4 = ASTAT; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +AQ &= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +AQ &= CC; // +R6 = ASTAT; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +AQ &= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000060; +CHECKREG r3, 0x00000060; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000060; + +// test AQ ^= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +AQ ^= CC; // +R4 = ASTAT; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +AQ ^= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +AQ ^= CC; // +R6 = ASTAT; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +AQ ^= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000060; +CHECKREG r3, 0x00000060; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000040; +CHECKREG r6, 0x00000060; +CHECKREG r7, 0x00000020; + + +pass diff --git a/sim/testsuite/bfin/c_cc2stat_cc_av0.S b/sim/testsuite/bfin/c_cc2stat_cc_av0.S new file mode 100644 index 0000000..c600902 --- /dev/null +++ b/sim/testsuite/bfin/c_cc2stat_cc_av0.S @@ -0,0 +1,241 @@ +//Original:/testcases/core/c_cc2stat_cc_av0/c_cc2stat_cc_av0.dsp +// Spec Reference: cc2stat cc av0 +# mach: bfin + +#include "test.h" + .include "testutils.inc" + + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000000; + imm32 r2, 0x00000000; + imm32 r3, 0x00000000; + imm32 r4, 0x00000000; + imm32 r5, 0x00000000; + imm32 r6, 0x00000000; + imm32 r7, 0x00000000; + +// test CC = AV0 0-0, 0-1, 1-0, 1-1 + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + CC = AV0; // + R0 = CC; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + CC = AV0; // + R1 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + CC = AV0; // + R2 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + CC = AV0; // + R3 = CC; // + +// test cc |= AV0 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + CC |= AV0; // + R4 = CC; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + CC |= AV0; // + R5 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 0 + CC |= AV0; // + R6 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + CC |= AV0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _SET; + +// test CC &= AV0 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + CC &= AV0; // + R4 = CC; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + CC &= AV0; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + CC &= AV0; // + R6 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + CC &= AV0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _UNSET; + CHECKREG r7, _SET; + +// test CC ^= AV0 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + CC ^= AV0; // + R4 = CC; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + CC ^= AV0; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + CC ^= AV0; // + R6 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + CC ^= AV0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _UNSET; + +// test AV0 = CC 0-0, 0-1, 1-0, 1-1 + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + AV0 = CC; // + R0 = ASTAT; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + AV0 = CC; // + R1 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + AV0 = CC; // + R2 = ASTAT; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + AV0 = CC; // + R3 = ASTAT; // + +// test AV0 |= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + AV0 |= CC; // + R4 = ASTAT; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + AV0 |= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + AV0 |= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + AV0 |= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV0); + CHECKREG r3, (_CC|_AV0); + CHECKREG r4, _UNSET; + CHECKREG r5, _AV0; + CHECKREG r6, (_CC|_AV0); + CHECKREG r7, (_CC|_AV0); + +// test AV0 &= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + AV0 &= CC; // + R4 = ASTAT; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + AV0 &= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + AV0 &= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + AV0 &= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV0); + CHECKREG r3, (_CC|_AV0); + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, (_CC); + CHECKREG r7, (_CC|_AV0); + +// test AV0 ^= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + AV0 ^= CC; // + R4 = ASTAT; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + AV0 ^= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + AV0 ^= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + AV0 ^= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV0); + CHECKREG r3, (_CC|_AV0); + CHECKREG r4, _UNSET; + CHECKREG r5, _AV0; + CHECKREG r6, (_CC|_AV0); + CHECKREG r7, _CC; + + pass diff --git a/sim/testsuite/bfin/c_cc2stat_cc_av1.S b/sim/testsuite/bfin/c_cc2stat_cc_av1.S new file mode 100644 index 0000000..2855085 --- /dev/null +++ b/sim/testsuite/bfin/c_cc2stat_cc_av1.S @@ -0,0 +1,240 @@ +//Original:/testcases/core/c_cc2stat_cc_av1/c_cc2stat_cc_av1.dsp +// Spec Reference: cc2stat cc av1 +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000000; + imm32 r2, 0x00000000; + imm32 r3, 0x00000000; + imm32 r4, 0x00000000; + imm32 r5, 0x00000000; + imm32 r6, 0x00000000; + imm32 r7, 0x00000000; + +// test CC = AV1 0-0, 0-1, 1-0, 1-1 + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + CC = AV1; // + R0 = CC; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + CC = AV1; // + R1 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + CC = AV1; // + R2 = CC; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + CC = AV1; // + R3 = CC; // + +// test cc |= AV1 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + CC |= AV1; // + R4 = CC; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + CC |= AV1; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + CC |= AV1; // + R6 = CC; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + CC |= AV1; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _SET; + +// test CC &= AV1 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + CC &= AV1; // + R4 = CC; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + CC &= AV1; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + CC &= AV1; // + R6 = CC; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + CC &= AV1; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _UNSET; + CHECKREG r7, _SET; + +// test CC ^= AV1 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + CC ^= AV1; // + R4 = CC; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + CC ^= AV1; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + CC ^= AV1; // + R6 = CC; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + CC ^= AV1; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _UNSET; + +// test AV1 = CC 0-0, 0-1, 1-0, 1-1 + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + AV1 = CC; // + R0 = ASTAT; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + AV1 = CC; // + R1 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + AV1 = CC; // + R2 = ASTAT; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + AV1 = CC; // + R3 = ASTAT; // + +// test AV1 |= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + AV1 |= CC; // + R4 = ASTAT; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + AV1 |= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + AV1 |= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + AV1 |= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV1); + CHECKREG r3, (_CC|_AV1); + CHECKREG r4, _UNSET; + CHECKREG r5, _AV1; + CHECKREG r6, (_CC|_AV1); + CHECKREG r7, (_CC|_AV1); + +// test AV1 &= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + AV1 &= CC; // + R4 = ASTAT; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + AV1 &= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + AV1 &= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + AV1 &= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV1); + CHECKREG r3, (_CC|_AV1); + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _CC; + CHECKREG r7, (_CC|_AV1); + +// test AV1 ^= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + AV1 ^= CC; // + R4 = ASTAT; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + AV1 ^= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + AV1 ^= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + AV1 ^= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV1); + CHECKREG r3, (_CC|_AV1); + CHECKREG r4, _UNSET; + CHECKREG r5, _AV1; + CHECKREG r6, (_CC|_AV1); + CHECKREG r7, _CC; + + pass diff --git a/sim/testsuite/bfin/c_cc2stat_cc_az.s b/sim/testsuite/bfin/c_cc2stat_cc_az.s new file mode 100644 index 0000000..0d8b05b --- /dev/null +++ b/sim/testsuite/bfin/c_cc2stat_cc_az.s @@ -0,0 +1,243 @@ +//Original:/testcases/core/c_cc2stat_cc_az/c_cc2stat_cc_az.dsp +// Spec Reference: cc2stat cc az +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// test CC = AZ 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +CC = AZ; // +R0 = CC; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +CC = AZ; // +R1 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +CC = AZ; // +R2 = CC; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +CC = AZ; // +R3 = CC; // + +// test cc |= AZ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +CC |= AZ; // +R4 = CC; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +CC |= AZ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +CC |= AZ; // +R6 = CC; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +CC |= AZ; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +// test CC &= AZ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +CC &= AZ; // +R4 = CC; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +CC &= AZ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +CC &= AZ; // +R6 = CC; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +CC &= AZ; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +// test CC ^= AZ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +CC ^= AZ; // +R4 = CC; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +CC ^= AZ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +CC ^= AZ; // +R6 = CC; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +CC ^= AZ; // +R7 = CC; // + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +// test AZ = CC 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +AZ = CC; // +R0 = ASTAT; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +AZ = CC; // +R1 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +AZ = CC; // +R2 = ASTAT; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +AZ = CC; // +R3 = ASTAT; // + +// test AZ |= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +AZ |= CC; // +R4 = ASTAT; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +AZ |= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +AZ |= CC; // +R6 = ASTAT; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +AZ |= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000021; +CHECKREG r3, 0x00000021; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000021; +CHECKREG r7, 0x00000021; + +// test AZ &= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +AZ &= CC; // +R4 = ASTAT; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +AZ &= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +AZ &= CC; // +R6 = ASTAT; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +AZ &= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000021; +CHECKREG r3, 0x00000021; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000021; + +// test AZ ^= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +AZ ^= CC; // +R4 = ASTAT; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +AZ ^= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +AZ ^= CC; // +R6 = ASTAT; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +AZ ^= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000021; +CHECKREG r3, 0x00000021; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000021; +CHECKREG r7, 0x00000020; + + +pass diff --git a/sim/testsuite/bfin/c_cc_flag_ccmv_depend.S b/sim/testsuite/bfin/c_cc_flag_ccmv_depend.S new file mode 100644 index 0000000..807a753 --- /dev/null +++ b/sim/testsuite/bfin/c_cc_flag_ccmv_depend.S @@ -0,0 +1,80 @@ +//Original:/proj/frio/dv/testcases/core/c_cc_flag_ccmv_depend/c_cc_flag_ccmv_depend.dsp +// Spec Reference: ccflag followed by ccmv (# stalls) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + imm32 r0, 0xa08d2311; + imm32 r1, 0x10120040; + imm32 r2, 0x62b61557; + imm32 r3, 0x07300007; + imm32 r4, 0x00740088; + imm32 r5, 0x609950aa; + imm32 r6, 0x20bb06cc; + imm32 r7, 0xd90e108f; + + imm32 p1, 0x1401101f; + imm32 p2, 0x3204108e; + imm32 fp, 0xd93f1084; + imm32 p4, 0xeb04106f; + imm32 p5, 0xa90e5089; + + CC = R7; // cc2dreg + IF CC R0 = R3; // ccmov + R6 = R0 + R4; + + CC = ! CC; // cc2dreg + IF CC R1 = P1; // ccmov + + CC = R5 < R1; // ccflag + R1 = ASTAT; + IF !CC R2 = R5; // ccmov + + CC = R2 == R3; // ccflag + IF CC P1 = R4; // ccmov + + CC = ! CC; + CC = R7 < R5; + IF CC P2 = P5; // ccmov + + CC = P5 == 3; + IF CC FP = R2; // ccmov + + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair + + CC = A0 == A1; + IF !CC R3 = R6; // ccmov + R7 = R3 + R2; + + A0 += A1 (W32); // dsp32alu a0 + a1 + CC = A0 < A1; + IF CC R4 = P4; // ccmov + R6 = R4; + + R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac + CC = A0 <= A1; + IF CC R5 = P5; // ccmov + + A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac + CC = A0 <= A1; + IF CC P5 = R6; // ccmov + + CHECKREG r0, 0x07300007; + CHECKREG r1, (_AC0|_AC0_COPY); + CHECKREG r2, 0x00766960; + CHECKREG r3, 0x07A4008F; + CHECKREG r4, 0xEB04106F; + CHECKREG r5, 0xA90E5089; + CHECKREG r6, 0xEB04106F; + CHECKREG r7, 0x075D69EF; + CHECKREG p1, 0x1401101F; + CHECKREG p2, 0xA90E5089; + CHECKREG fp, 0xD93F1084; + CHECKREG p4, 0xEB04106F; + CHECKREG p5, 0xA90E5089; + + pass diff --git a/sim/testsuite/bfin/c_cc_flagdreg_mvbrsft.s b/sim/testsuite/bfin/c_cc_flagdreg_mvbrsft.s new file mode 100644 index 0000000..a36f31a --- /dev/null +++ b/sim/testsuite/bfin/c_cc_flagdreg_mvbrsft.s @@ -0,0 +1,87 @@ +//Original:/testcases/core/c_cc_flagdreg_mvbrsft/c_cc_flagdreg_mvbrsft.dsp +// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xa08d2311; +imm32 r1, 0x10120040; +imm32 r2, 0x62b61557; +imm32 r3, 0x07300007; +imm32 r4, 0x00740088; +imm32 r5, 0x609950aa; +imm32 r6, 0x20bb06cc; +imm32 r7, 0xd90e108f; + + ASTAT = R0; + + CC = R1; // cc2dreg + IF CC R1 = R3; // ccmov + CC = ! CC; // cc2dreg + IF CC R3 = R2; // ccmov + CC = R0 < R1; // ccflag + IF CC R4 = R5; // ccmov + CC = R2 == R3; + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + IF !CC JUMP LABEL1; // branch on + CC = ! CC; + IF !CC JUMP LABEL2 (BP); // branch on +LABEL1: + R6 = R0 + R2; + JUMP.S END; +LABEL2: + R7 = R5 - R3; + CC = R0 < R1; // ccflag + IF CC JUMP END (BP); // branch on + R4 = R5 + R7; + +END: + +CHECKREG r0, 0xA08D2311; +CHECKREG r1, 0x07300007; +CHECKREG r2, 0x62B61557; +CHECKREG r3, 0x07300007; +CHECKREG r4, 0x609950AA; +CHECKREG r5, 0x609950AA; +CHECKREG r6, 0x20BB06CC; +CHECKREG r7, 0x596950A3; + +imm32 r0, 0x408d2711; +imm32 r1, 0x15124040; +imm32 r2, 0x62661557; +imm32 r3, 0x073b0007; +imm32 r4, 0x01f49088; +imm32 r5, 0x6e2959aa; +imm32 r6, 0xa0b506cc; +imm32 r7, 0x00000002; + + + CC = R1; // cc2dreg + R2 = ROT R2 BY 1; // dsp32shiftim_rot + CC = ! CC; // cc2dreg + R3 = ROT R0 BY -3; // dsp32shiftim_rot + CC = R0 < R1; // ccflag + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = R2 == R3; + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + R7 = ROT R6 BY R7.L; + +CHECKREG r0, 0x408D2711; +CHECKREG r1, 0x15124040; +CHECKREG r2, 0xC4CC2AAF; +CHECKREG r3, 0x6811A4E2; +CHECKREG r4, 0x01F49088; +CHECKREG r5, 0x6E2959AA; +CHECKREG r6, 0x3E921100; +CHECKREG r7, 0xFA484402; + + + + +pass diff --git a/sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_s1.s b/sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_s1.s new file mode 100644 index 0000000..24505c2 --- /dev/null +++ b/sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_s1.s @@ -0,0 +1,99 @@ +//Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_s1/c_cc_flagdreg_mvbrsft_s1.dsp +// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft) +# mach: bfin + +.include "testutils.inc" + start + + INIT_P_REGS 0; + + imm32 r0, 0xa08d2311; + imm32 r1, 0x10120040; + imm32 r2, 0x62b61557; + imm32 r3, 0x07300007; + imm32 r4, 0x00740088; + imm32 r5, 0x609950aa; + imm32 r6, 0x20bb06cc; + imm32 r7, 0xd90e108f; + + ASTAT = R0; + + CC = R1; // cc2dreg + R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac + IF CC R1 = R3; // ccmov + CC = ! CC; // cc2dreg + R4.H = R1.L + R0.L (S); // dsp32alu + IF CC R3 = R2; // ccmov + CC = R0 < R1; // ccflag + R4.L = R5.L << 1; // dsp32shiftimm + IF CC R4 = R5; // ccmov + CC = R2 == R3; // ccflag + R7 = R1.L * R4.L, R6 = R1.H * R4.H; // dsp32mult + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac + IF !CC JUMP LABEL1; // branch on + CC = ! CC; // cc2dreg + P1.L = 0x3000; // ldimmhalf + IF !CC JUMP LABEL2 (BP); // branch +LABEL1: + R6 = R6 + R2; + JUMP.S END; +LABEL2: + R7 = R5 - R7; + CC = R0 < R1; // ccflag + P2 = A0.w; + IF CC JUMP END (BP); // branch + P3 = A1.w; + R5 = R5 + R7; + +END: + + CHECKREG r0, 0xA08D2311; + CHECKREG r1, 0x07300007; + CHECKREG r2, 0x00011557; + CHECKREG r3, 0x07300007; + CHECKREG r4, 0x609950AA; + CHECKREG r5, 0x609950AA; + CHECKREG r6, 0x056C9760; + CHECKREG r7, 0x6094E75E; + CHECKREG p1, 0x00003000; + CHECKREG p2, 0x01382894; + CHECKREG p3, 0x00000000; + + imm32 r0, 0x408d2711; + imm32 r1, 0x15124040; + imm32 r2, 0x62661557; + imm32 r3, 0x073b0007; + imm32 r4, 0x01f49088; + imm32 r5, 0x6e2959aa; + imm32 r6, 0xa0b506cc; + imm32 r7, 0x00000002; + + CC = R1; // cc2dreg + + R2 = ROT R2 BY 1; // dsp32shiftim_rot + CC = ! CC; // cc2dreg + R3 >>= R7; // alu2op sft + R3 = ROT R0 BY -3; // dsp32shiftim_rot + CC = R0 < R1; // ccflag + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = R2 == R3; // ccflag + P1 = R1; // regmv + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft + R7 = ROT R6 BY R7.L; // dsp32shiftim_rot + + CHECKREG r0, 0x408D2711; + CHECKREG r1, 0x2ACFF368; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0xFFFC8440; + CHECKREG r4, 0x01F49088; + CHECKREG r5, 0x6E2959AA; + CHECKREG r6, 0x15BD33A8; + CHECKREG r7, 0x56F4CEA2; + CHECKREG p1, 0x15124040; + + pass diff --git a/sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_sn.s b/sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_sn.s new file mode 100644 index 0000000..8002cbd --- /dev/null +++ b/sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_sn.s @@ -0,0 +1,118 @@ +//Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_sn/c_cc_flagdreg_mvbrsft_sn.dsp +// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft) +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0xa08d2311; + imm32 r1, 0x10120040; + imm32 r2, 0x62b61557; + imm32 r3, 0x07300007; + imm32 r4, 0x00740088; + imm32 r5, 0x609950aa; + imm32 r6, 0x20bb06cc; + imm32 r7, 0xd90e108f; + + imm32 p1, 0x1401101f; + imm32 p2, 0x3204108e; + imm32 p3, 0xd93f1084; + imm32 p4, 0xeb04106f; + imm32 p5, 0xa90e5089; + + ASTAT = R0; + + CC = R1; // cc2dreg + R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac + I0 = P1; // regmv + IF CC R1 = R3; // ccmov + CC = ! CC; // cc2dreg + R4.H = R1.L + R0.L (S); // dsp32alu + M0 = P2; // regmv + IF CC R3 = R2; // ccmov + CC = R0 < R1; // ccflag + R4.L = R5.L << 1; // dsp32shiftimm + I0 += M0; // dagmodim + R2 = R0 + R2; // comp3op dr plus dr + IF CC R4 = R5; // ccmov + CC = R2 == R3; // ccflag + R7 = R1.L * R4.L, R6 = R1.H * R4.H; // dsp32mult + R5 = R0 + R2; // comp3op dr plus dr + BITCLR( R6 , 1 ); + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac + IF !CC JUMP LABEL1; // branch on + CC = ! CC; // cc2dreg + P1.L = 0x3000; // ldimmhalf + A0 += A1 (W32); // dsp32alu a0 + a1 + IF !CC JUMP LABEL2 (BP); // branch +LABEL1: + R6 = R6 + R2; + JUMP.S END; +LABEL2: + R7 = R5 - R7; + CC = R0 < R1; // ccflag + P2 = A0.w; + IF CC JUMP END (BP); // branch + P3 = A1.w; + R5 = R5 + R7; + +END: + + CHECKREG r0, 0xA08D2311; + CHECKREG r1, 0x07300007; + CHECKREG r2, 0xA08E3868; + CHECKREG r3, 0x07300007; + CHECKREG r4, 0x609950AA; + CHECKREG r5, 0x411B5B79; + CHECKREG r6, 0x056C9760; + CHECKREG r7, 0x4116F22D; + CHECKREG p1, 0x14013000; + CHECKREG p2, 0x033352A4; + CHECKREG p3, 0xD93F1084; + + imm32 r0, 0x408d2711; + imm32 r1, 0x15124040; + imm32 r2, 0x62661557; + imm32 r3, 0x073b0007; + imm32 r4, 0x01f49088; + imm32 r5, 0x6e2959aa; + imm32 r6, 0xa0b506cc; + imm32 r7, 0x00000002; + + CC = R1; // cc2dreg + P1 = -15; // compi2opp_pr_eq_i7 + R2 = ROT R2 BY 1; // dsp32shiftim_rot + CC = ! CC; // cc2dreg + R3 >>= R7; // alu2op sft + R4 = ROT R0 BY -3; // dsp32shiftim_rot + CC = R0 < R1; // ccflag + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair + R5 = R0 + R2; // comp3op dr plus dr + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = R2 == R3; // ccflag + P2 = R1; // regmv + R4.H = R1.L + R3.H (S); // dsp32alu + I0 = P1; // regmv + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft + I0 += 2; + P3 = I0; + R3.L = R5.L << 1; // dsp32shiftimm + R7 = ROT R6 BY R7.L; // dsp32shiftim_rot + + CHECKREG r0, 0x408D2711; + CHECKREG r1, 0x2ACFF368; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0xFFFD4E22; + CHECKREG r4, 0x403DA4E2; + CHECKREG r5, 0x408D2711; + CHECKREG r6, 0x15BD33A8; + CHECKREG r7, 0x56F4CEA2; + CHECKREG p1, 0xFFFFFFF1; + CHECKREG p2, 0x15124040; + CHECKREG p3, 0xFFFFFFF3; + + pass diff --git a/sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft.s b/sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft.s new file mode 100644 index 0000000..7ad1823 --- /dev/null +++ b/sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft.s @@ -0,0 +1,83 @@ +//Original:/testcases/core/c_cc_regmvlogi_mvbrsft/c_cc_regmvlogi_mvbrsft.dsp +// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000020; // cc=1 +imm32 r1, 0x00000000; // cc=0 +imm32 r2, 0x62b61557; +imm32 r3, 0x07300007; +imm32 r4, 0x00740088; +imm32 r5, 0x609950aa; +imm32 r6, 0x20bb06cc; +imm32 r7, 0xd90e108f; + + + ASTAT = R0; // cc=1 REGMV + IF CC R1 = R3; // ccmov + ASTAT = R1; // cc=0 REGMV + IF CC R3 = R2; // ccmv + CC = R0 < R1; // ccflag + IF CC R4 = R5; // ccmv + CC = ! BITTST( R0 , 4 ); // cc = 0 + IF CC R4 = R5; // ccmv + CC = BITTST ( R1 , 4 ); // cc = 0 + IF !CC JUMP LABEL1; // branch + CC = ! CC; + IF !CC JUMP LABEL2 (BP); // branch +LABEL1: + R6 = R0 + R2; + JUMP.S END; +LABEL2: + R7 = R5 - R3; + CC = R0 < R1; // ccflag + IF CC JUMP END (BP); // branch on + R4 = R5 + R7; + +END: + +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x07300007; +CHECKREG r2, 0x62B61557; +CHECKREG r3, 0x07300007; +CHECKREG r4, 0x609950AA; +CHECKREG r5, 0x609950AA; +CHECKREG r6, 0x62B61577; +CHECKREG r7, 0xD90E108F; + +imm32 r0, 0x00000020; +imm32 r1, 0x00000000; +imm32 r2, 0x62661557; +imm32 r3, 0x073b0007; +imm32 r4, 0x01f49088; +imm32 r5, 0x6e2959aa; +imm32 r6, 0xa0b506cc; +imm32 r7, 0x00000002; + + + ASTAT = R0; // cc=1 REGMV + R2 = ROT R2 BY 1; // dsp32shiftim_rot + ASTAT = R1; // cc=0 REGMV + R3 = ROT R3 BY 1; // dsp32shiftim_rot + CC = ! BITTST( R0 , 4 ); // cc = 0 + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = BITTST ( R1 , 4 ); // cc = 0 + IF CC R4 = R5; // ccmov + CC = BITTST ( R0 , 4 ); // cc = 1 + R7 = ROT R6 BY R7.L; + +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xC4CC2AAF; +CHECKREG r3, 0x0E76000E; +CHECKREG r4, 0x01F49088; +CHECKREG r5, 0x6E2959AA; +CHECKREG r6, 0x3E921110; +CHECKREG r7, 0xFA484440; + +pass diff --git a/sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_s1.s b/sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_s1.s new file mode 100644 index 0000000..f0306c9 --- /dev/null +++ b/sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_s1.s @@ -0,0 +1,98 @@ +//Original:/testcases/core/c_cc_regmvlogi_mvbrsft_s1/c_cc_regmvlogi_mvbrsft_s1.dsp +// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft) +# mach: bfin + +.include "testutils.inc" + start + + +A0 = 0; +A1 = 0; + +imm32 r0, 0x00000020; // cc=1 +imm32 r1, 0x00000000; // cc=0 +imm32 r2, 0x62b61557; +imm32 r3, 0x07300007; +imm32 r4, 0x00740088; +imm32 r5, 0x609950aa; +imm32 r6, 0x20bb06cc; +imm32 r7, 0x00000002; + + +ASTAT = R0; // cc=1 REGMV +R5 = R0 + R2; // comp3op dr plus dr +IF CC R1 = R3; // ccmov +ASTAT = R1; // cc=0 REGMV +R4 >>= R7; // alu2op sft +IF CC R3 = R2; // ccmv +CC = R0 < R1; // ccflag +R3.H = R1.L + R3.H (S); // dsp32alu +IF CC R4 = R5; // ccmv +CC = ! BITTST( R0 , 4 ); // cc = 0 +R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft +IF CC R4 = R5; // ccmv +CC = BITTST ( R1 , 4 ); // cc = 0 +R3.L = R5.L << 1; // dsp32shiftim +IF !CC JUMP LABEL1; // branch +CC = ! CC; +R1 = ( A1 = R7.L * R4.L ), R0 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair +IF !CC JUMP LABEL2 (BP); // branch +LABEL1: + R2 = R0 + R2; +JUMP.S END; +LABEL2: + R7 = R5 - R3; +CC = R0 < R1; // ccflag +R5 = R0 + R2; // comp3op dr plus dr +IF CC JUMP END (BP); // branch on +R4 = R5 + R7; + +END: + +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x0398000C; +CHECKREG r2, 0x62B61577; +CHECKREG r3, 0x07372AEE; +CHECKREG r4, 0x62B61577; +CHECKREG r5, 0x62B61577; +CHECKREG r6, 0xFC680013; +CHECKREG r7, 0x00000002; + +imm32 r0, 0x00000020; +imm32 r1, 0x00000000; +imm32 r2, 0x62661557; +imm32 r3, 0x073b0007; +imm32 r4, 0x01f49088; +imm32 r5, 0x6e2959aa; +imm32 r6, 0xa0b506cc; +imm32 r7, 0x00000002; + + + ASTAT = R0; // cc=1 REGMV + R4.H = R1.L + R0.L (S); // dsp32alu + R2 = ROT R2 BY 1; // dsp32shiftim_rot + ASTAT = R1; // cc=0 REGMV + A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac + R3 = ROT R3 BY 1; // dsp32shiftim_rot + CC = ! BITTST( R0 , 4 ); // cc = 0 + R4.L = R5.L << 1; // dsp32shiftimm + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = BITTST ( R1 , 4 ); // cc = 0 + R7 = R0 + R2; // comp3op dr plus dr + IF CC R4 = R5; // ccmov + A0 += A1 (W32); // dsp32alu a0 + a1 + CC = BITTST ( R0 , 4 ); // cc = 1 + R5 = ROT R6 BY R7.L; + R0 = A0.w; + R1 = A1.w; + +CHECKREG r0, 0x026B943C; +CHECKREG r1, 0x00025592; +CHECKREG r2, 0xC4CC2AAF; +CHECKREG r3, 0x0E76000E; +CHECKREG r4, 0x0020B354; +CHECKREG r5, 0x35480105; +CHECKREG r6, 0x04166A90; +CHECKREG r7, 0xC4CC2ACF; + +pass diff --git a/sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_sn.S b/sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_sn.S new file mode 100644 index 0000000..8b04188 --- /dev/null +++ b/sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_sn.S @@ -0,0 +1,127 @@ +//Original:/proj/frio/dv/testcases/core/c_cc_regmvlogi_mvbrsft_sn/c_cc_regmvlogi_mvbrsft_sn.dsp +// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + INIT_I_REGS 0; + INIT_M_REGS 0; + INIT_L_REGS 0; + INIT_B_REGS 0; + INIT_R_REGS 0; + INIT_P_REGS 0; + ASTAT = R0; + A0 = A1 = 0; + + imm32 r0, (_CC); // cc=1 + imm32 r1, 0x00000000; // cc=0 + imm32 r2, 0x62b61557; + imm32 r3, 0x07300007; + imm32 r4, 0x00740088; + imm32 r5, 0x609950aa; + imm32 r6, 0x20bb06cc; + imm32 r7, 0x00000002; + + A0 = R4; + A1 = R6; + + ASTAT = R0; // cc=1 REGMV + P2 = R2; + R2 = R0 + R2; // comp3op dr plus dr + M0 = P2; // regmv + IF CC R1 = R3; // ccmov + ASTAT = R1; // cc=0 REGMV + R3 >>= R7; // alu2op sft + R3 = R0 + R2; // comp3op dr plus dr + I0 = R5; + IF CC R3 = R2; // ccmv + CC = R0 < R1; // ccflag + R3.H = R1.L + R3.H (S); // dsp32alu + R5 = ( A1 = R7.L * R4.H ), R4 = ( A0 = R7.H * R4.L ); // dsp32mac pair + IF CC R4 = R5; // ccmv + CC = ! BITTST( R0 , 4 ); // cc = 0 + R0 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft + I0 += 2; // dagmodim + IF CC R4 = R5; // ccmv + CC = BITTST ( R1 , 4 ); // cc = 0 + R7.L = R5.L << 1; // dsp32shiftim + R1 = R0 +|- R1 , R5 = R0 -|+ R1 (ASR); // dsp32alu sft + P1 = A0.w; + IF !CC JUMP LABEL1; // branch + CC = ! CC; + R1 = ( A1 = R7.L * R4.L ), R0 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair + I0 += M0; // dagmodim + P2 = A1.w; + IF !CC JUMP LABEL2 (BP); // branch +LABEL1: + R2 = R0 + R2; + JUMP.S END; +LABEL2: + R7 = R5 - R3; + CC = R0 < R1; // ccflag + R6 = R0 + R2; // comp3op dr plus dr + P4 = I0; + IF CC JUMP END (BP); // branch on + R7 = R5 + R7; + +END: + + CHECKREG r0, 0x0398000C; + CHECKREG r1, 0x05640002; + CHECKREG r2, 0x664E1583; + CHECKREG r3, 0x62BD1597; + CHECKREG r4, 0x000001D0; + CHECKREG r5, 0xFE340009; + CHECKREG r6, 0xFC680013; + CHECKREG r7, 0x000003A0; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x62B61557; + CHECKREG p4, 0x00000000; + + imm32 r0, (_CC); + imm32 r1, 0x00000000; + imm32 r2, 0x62661557; + imm32 r3, 0x073b0007; + imm32 r4, 0x01f49088; + imm32 r5, 0x6e2959aa; + imm32 r6, 0xa0b506cc; + imm32 r7, 0xabd30002; + + A1 = A0 = 0; + ASTAT = R0; // cc=1 REGMV + R2.H = R3.L + R4.L (NS); // dsp32alu + R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac + R3 = ROT R2 BY 1; // dsp32shiftim_rot + ASTAT = R1; // cc=0 REGMV + A1 += R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac + R2.L = R5.L << 1; // dsp32shiftimm + R5 = ROT R3 BY 1; // dsp32shiftim_rot + CC = ! BITTST( R0 , 4 ); // cc = 0 + R4.L = R5.L << 1; // dsp32shiftimm + R0 >>= R7; // alu2op sft + A0 += A1; // dsp32alu a0 + a1 + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = BITTST ( R1 , 4 ); // cc = 0 + R0 = R0 + R2; // comp3op dr plus dr + R5 = R3.L * R4.H, R4 = R3.H * R4.L; // dsp32mult + P1 = A0.w; + IF CC R4 = R5; // ccmov + P1.L = 0x3000; // ldimmhalf + P2 = A1.w; // regmv + CC = BITTST ( R0 , 4 ); // cc = 1 + R7 = ROT R6 BY R7.L; + + CHECKREG r0, 0x0001B354; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x0001B354; + CHECKREG r3, 0x00022AAF; + CHECKREG r4, 0xFFFEAAF0; + CHECKREG r5, 0x00A6BB98; + CHECKREG r6, 0x3E955790; + CHECKREG r7, 0xFA555E42; + CHECKREG p1, 0x07193000; + CHECKREG p2, 0x071EE3B4; + + pass diff --git a/sim/testsuite/bfin/c_ccflag_a0a1.S b/sim/testsuite/bfin/c_ccflag_a0a1.S new file mode 100644 index 0000000..8163417 --- /dev/null +++ b/sim/testsuite/bfin/c_ccflag_a0a1.S @@ -0,0 +1,143 @@ +//Original:/testcases/core/c_ccflag_a0a1/c_ccflag_a0a1.dsp +// Spec Reference: ccflag a0-a1 (==, <, <=) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + imm32 r0, 0x12345778; + imm32 r1, 0x12345678; + imm32 r2, 0x056789ab; + imm32 r3, 0x80231345; + + imm32 r4, 0x00770088; + imm32 r5, 0x009900aa; + imm32 r6, 0x00bb00cc; + imm32 r7, _UNSET; + + ASTAT = R7; + R4 = ASTAT; + A0 = R0; + A1 = R0; + +// positive a0 EQUAL to a1 + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0|_CC|_AC0_COPY|_AZ); + CHECKREG r6, (_AC0|_AC0_COPY|_AZ); + CC = A0 <= A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r5, (_AC0|_CC|_AC0_COPY|_AZ); + CHECKREG r6, (_AC0|_AC0_COPY|_AZ); + CHECKREG r7, (_AC0|_CC|_AC0_COPY|_AZ); + +// positive a0 GREATER than to positive a1 + A1 = R1; + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r5, (_AC0|_AC0_COPY); // carry + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AC0|_AC0_COPY); + +// positive a0 LESS than to positive a1 + A1 = R2; + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AC0|_AC0_COPY); + +// positive a0 GREATER than to neg a1 + A1 = R3; + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r5, _UNSET; + CHECKREG r6, _UNSET; + CHECKREG r7, _UNSET; + +// negative a0 and positive a1 + imm32 r0, -1; + imm32 r1, 2; + imm32 r2, -3; + imm32 r3, -4; + A0 = R0; + A1 = R1; + + R7 = 0; + ASTAT = R7; + R4 = ASTAT; + + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0|_AC0_COPY|_AN); + CHECKREG r6, (_AC0|_AC0_COPY|_CC|_AN); + CHECKREG r7, (_AC0|_AC0_COPY|_CC|_AN); + +// negative a0 LESS than neg a1 + A0 = R3; + A1 = R4; + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0|_AC0_COPY|_AN); + CHECKREG r6, (_AC0|_AC0_COPY|_CC|_AN); + CHECKREG r7, (_AC0|_AC0_COPY|_CC|_AN); + +// negative a0 GREATER neg a1 + A0 = R0; + A1 = R3; + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AC0|_AC0_COPY); + +// negative a0 EQUAL neg imm3 + A0 = R3; + A1 = R3; + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0|_CC|_AC0_COPY|_AZ); + CHECKREG r6, (_AC0|_AC0_COPY|_AZ); + CHECKREG r7, (_AC0|_CC|_AC0_COPY|_AZ); + + pass diff --git a/sim/testsuite/bfin/c_ccflag_dr_dr.s b/sim/testsuite/bfin/c_ccflag_dr_dr.s new file mode 100644 index 0000000..a72cb0c --- /dev/null +++ b/sim/testsuite/bfin/c_ccflag_dr_dr.s @@ -0,0 +1,299 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr/c_ccflag_dr_dr.dsp +// Spec Reference: ccflags dr-dr +# mach: bfin + +.include "testutils.inc" + start + + +imm32 r0, 0x00110022; +imm32 r1, 0x00110022; +imm32 r2, 0x00330044; +imm32 r3, 0x00550066; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R7; +R4 = ASTAT; + +// positive dreg-1 EQUAL to positive dreg-2 +CC = R0 == R1; +R5 = ASTAT; +CC = R0 < R1; +R6 = ASTAT; +CC = R0 <= R1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CHECKREG r7, 0x00001025; +CC = R0 < R1; +R4 = ASTAT; +CC = R0 <= R1 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00001005; +CHECKREG r5, 0x00001025; + +// positive dreg-1 GREATER than positive dreg-2 +CC = R3 == R2; +R5 = ASTAT; +CC = R3 < R2; +R6 = ASTAT; +CC = R3 <= R2; +R7 = ASTAT; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; +CC = R3 < R2 (IU); +R4 = ASTAT; +CC = R3 <= R2 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001004; + + +// positive dreg-1 LESS than positive dreg-2 +CC = R2 == R3; +R5 = ASTAT; +CC = R2 < R3; +R6 = ASTAT; +CC = R2 <= R3; +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; +CC = R2 < R3; +R4 = ASTAT; +CC = R2 <= R3; +R5 = ASTAT; +CHECKREG r4, 0x00000022; +CHECKREG r5, 0x00000022; + +imm32 r0, 0x01230123; +imm32 r1, 0x81230123; +imm32 r2, 0x04560456; +imm32 r3, 0x87890789; +// operate on negative number +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +// positive dreg-1 GREATER than negative dreg-2 +CC = R0 == R1; +R5 = ASTAT; +CC = R0 < R1; +R6 = ASTAT; +CC = R0 <= R1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// negative dreg-1 LESS than POSITIVE dreg-2 small +CC = R3 == R2; +R5 = ASTAT; +CC = R3 < R2; +R6 = ASTAT; +CC = R3 <= R2; +R7 = ASTAT; +CHECKREG r5, 0x00001006; +CHECKREG r6, 0x00001026; +CHECKREG r7, 0x00001026; + +// negative dreg-1 GREATER than negative dreg-2 +CC = R1 == R3; +R5 = ASTAT; +CC = R1 < R3; +R6 = ASTAT; +CC = R1 <= R3; +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// negative dreg-1 LESS than negative dreg-2 +CC = R3 == R1; +R5 = ASTAT; +CC = R3 < R1; +R6 = ASTAT; +CC = R3 <= R1; +R7 = ASTAT; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + + +imm32 r0, 0x80230123; +imm32 r1, 0x00230123; +imm32 r2, 0x80560056; +imm32 r3, 0x00890089; +// operate on negative number +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +// negative dreg-1 LESS than POSITIVE dreg-2 +CC = R2 == R3; +R5 = ASTAT; +CC = R2 < R3; +R6 = ASTAT; +CC = R2 <= R3; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001006; // overflow and carry but not negative +CHECKREG r6, 0x00001026; // cc overflow, carry and negative +CHECKREG r7, 0x00001026; + + +imm32 r4, 0x44444444; +imm32 r5, 0x55555555; +imm32 r6, 0x66666666; +imm32 r7, 0x77777777; + +imm32 r0, 0x00000000; +imm32 r1, 0x11111111; +imm32 r2, 0x22222222; +imm32 r3, 0x33333333; + +ASTAT = R0; +R3 = ASTAT; +NOP; +CHECKREG r3, 0x00000000; + +// positive dreg-1 EQUAL to positive dreg-2 +CC = R4 == R5; +R0 = ASTAT; +CC = R4 < R5; +R1 = ASTAT; +CC = R4 <= R5; +R2 = ASTAT; +CC = R4 < R5; +R3 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CC = R4 <= R5; +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00000022; + +// positive dreg-1 GREATER than positive dreg-2 +CC = R7 == R6; +R0 = ASTAT; +CC = R7 < R6; +R1 = ASTAT; +CC = R7 <= R6; +R2 = ASTAT; +CC = R7 < R6; +R3 = ASTAT; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; +CC = R7 <= R6 (IU); +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00001004; + + +// positive dreg-1 LESS than positive dreg-2 +CC = R6 == R7; +R0 = ASTAT; +CC = R6 < R7; +R1 = ASTAT; +CC = R6 <= R7; +R2 = ASTAT; +CC = R6 < R7; +R3 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CC = R6 <= R7; +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00000022; + +imm32 r4, 0x01230123; +imm32 r5, 0x81230123; +imm32 r6, 0x04560456; +imm32 r7, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R3 = ASTAT; +CHECKREG r3, 0x00000000; + +// positive dreg-1 GREATER than negative dreg-2 +CC = R4 == R5; +R1 = ASTAT; +CC = R4 < R5; +R2 = ASTAT; +CC = R4 <= R5; +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + +// negative dreg-1 LESS than POSITIVE dreg-2 small +CC = R7 == R6; +R0 = ASTAT; +CC = R7 < R6; +R1 = ASTAT; +CC = R7 <= R6; +R2 = ASTAT; +CHECKREG r0, 0x00001006; +CHECKREG r1, 0x00001026; +CHECKREG r2, 0x00001026; + +// negative dreg-1 GREATER than negative dreg-2 +CC = R5 == R7; +R0 = ASTAT; +CC = R5 < R7; +R1 = ASTAT; +CC = R5 <= R7; +R2 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; + +// negative dreg-1 LESS than negative dreg-2 +CC = R7 == R5; +R1 = ASTAT; +CC = R7 < R5; +R2 = ASTAT; +CC = R7 <= R5; +R3 = ASTAT; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + + +imm32 r4, 0x80230123; +imm32 r5, 0x00230123; +imm32 r6, 0x80560056; +imm32 r7, 0x00890089; +// operate on negative number +R3 = 0; +ASTAT = R3; +R0 = ASTAT; + +// negative dreg-1 LESS than POSITIVE dreg-2 +CC = R6 == R7; +R1 = ASTAT; +CC = R6 < R7; +R2 = ASTAT; +CC = R6 <= R7; +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001006; // overflow and carry but not negative +CHECKREG r2, 0x00001026; // cc overflow, carry and negative +CHECKREG r3, 0x00001026; + + +pass; diff --git a/sim/testsuite/bfin/c_ccflag_dr_dr_uu.s b/sim/testsuite/bfin/c_ccflag_dr_dr_uu.s new file mode 100644 index 0000000..2709c89 --- /dev/null +++ b/sim/testsuite/bfin/c_ccflag_dr_dr_uu.s @@ -0,0 +1,299 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr_uu/c_ccflag_dr_dr_uu.dsp +// Spec Reference: ccflags dr-dr_uu +# mach: bfin + +.include "testutils.inc" + start + + +imm32 r0, 0x00110022; +imm32 r1, 0x00110022; +imm32 r2, 0x00330044; +imm32 r3, 0x00550066; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R7; +R4 = ASTAT; + +// positive dreg-1 EQUAL to positive dreg-2 +CC = R0 == R1; +R5 = ASTAT; +CC = R0 < R1 (IU); +R6 = ASTAT; +CC = R0 <= R1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CHECKREG r7, 0x00001025; +CC = R0 < R1 (IU); +R4 = ASTAT; +CC = R0 <= R1 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00001005; +CHECKREG r5, 0x00001025; + +// positive dreg-1 GREATER than positive dreg-2 +CC = R3 == R2; +R5 = ASTAT; +CC = R3 < R2 (IU); +R6 = ASTAT; +CC = R3 <= R2 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; +CC = R3 < R2 (IU); +R4 = ASTAT; +CC = R3 <= R2 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001004; + + +// positive dreg-1 LESS than positive dreg-2 +CC = R2 == R3; +R5 = ASTAT; +CC = R2 < R3 (IU); +R6 = ASTAT; +CC = R2 <= R3 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; +CC = R2 < R3 (IU); +R4 = ASTAT; +CC = R2 <= R3 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00000022; +CHECKREG r5, 0x00000022; + +imm32 r0, 0x01230123; +imm32 r1, 0x81230123; +imm32 r2, 0x04560456; +imm32 r3, 0x87890789; +// operate on negative number +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +// positive dreg-1 GREATER than negative dreg-2 +CC = R0 == R1; +R5 = ASTAT; +CC = R0 < R1 (IU); +R6 = ASTAT; +CC = R0 <= R1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// negative dreg-1 LESS than POSITIVE dreg-2 small +CC = R3 == R2; +R5 = ASTAT; +CC = R3 < R2 (IU); +R6 = ASTAT; +CC = R3 <= R2 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001006; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + +// negative dreg-1 GREATER than negative dreg-2 +CC = R1 == R3; +R5 = ASTAT; +CC = R1 < R3 (IU); +R6 = ASTAT; +CC = R1 <= R3 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// negative dreg-1 LESS than negative dreg-2 +CC = R3 == R1; +R5 = ASTAT; +CC = R3 < R1 (IU); +R6 = ASTAT; +CC = R3 <= R1 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + + +imm32 r0, 0x80230123; +imm32 r1, 0x00230123; +imm32 r2, 0x80560056; +imm32 r3, 0x00890089; +// operate on negative number +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +// negative dreg-1 LESS than POSITIVE dreg-2 +CC = R2 == R3; +R5 = ASTAT; +CC = R2 < R3 (IU); +R6 = ASTAT; +CC = R2 <= R3 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001006; // overflow and carry but not negative +CHECKREG r6, 0x00001004; // cc overflow, carry and negative +CHECKREG r7, 0x00001004; + + +imm32 r4, 0x44444444; +imm32 r5, 0x55555555; +imm32 r6, 0x66666666; +imm32 r7, 0x77777777; + +imm32 r0, 0x00000000; +imm32 r1, 0x11111111; +imm32 r2, 0x22222222; +imm32 r3, 0x33333333; + +ASTAT = R0; +R3 = ASTAT; +NOP; +CHECKREG r3, 0x00000000; + +// positive dreg-1 EQUAL to positive dreg-2 +CC = R4 == R5; +R0 = ASTAT; +CC = R4 < R5 (IU); +R1 = ASTAT; +CC = R4 <= R5 (IU); +R2 = ASTAT; +CC = R4 < R5 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CC = R4 <= R5 (IU); +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00000022; + +// positive dreg-1 GREATER than positive dreg-2 +CC = R7 == R6; +R0 = ASTAT; +CC = R7 < R6 (IU); +R1 = ASTAT; +CC = R7 <= R6 (IU); +R2 = ASTAT; +CC = R7 < R6 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; +CC = R7 <= R6 (IU); +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00001004; + + +// positive dreg-1 LESS than positive dreg-2 +CC = R6 == R7; +R0 = ASTAT; +CC = R6 < R7 (IU); +R1 = ASTAT; +CC = R6 <= R7 (IU); +R2 = ASTAT; +CC = R6 < R7 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CC = R6 <= R7 (IU); +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00000022; + +imm32 r4, 0x01230123; +imm32 r5, 0x81230123; +imm32 r6, 0x04560456; +imm32 r7, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R3 = ASTAT; +CHECKREG r3, 0x00000000; + +// positive dreg-1 GREATER than negative dreg-2 +CC = R4 == R5; +R1 = ASTAT; +CC = R4 < R5 (IU); +R2 = ASTAT; +CC = R4 <= R5 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; + +// negative dreg-1 LESS than POSITIVE dreg-2 small +CC = R7 == R6; +R0 = ASTAT; +CC = R7 < R6 (IU); +R1 = ASTAT; +CC = R7 <= R6 (IU); +R2 = ASTAT; +CHECKREG r0, 0x00001006; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; + +// negative dreg-1 GREATER than negative dreg-2 +CC = R5 == R7; +R0 = ASTAT; +CC = R5 < R7 (IU); +R1 = ASTAT; +CC = R5 <= R7 (IU); +R2 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; + +// negative dreg-1 LESS than negative dreg-2 +CC = R7 == R5; +R1 = ASTAT; +CC = R7 < R5 (IU); +R2 = ASTAT; +CC = R7 <= R5 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + + +imm32 r4, 0x80230123; +imm32 r5, 0x00230123; +imm32 r6, 0x80560056; +imm32 r7, 0x00890089; +// operate on negative number +R3 = 0; +ASTAT = R3; +R0 = ASTAT; + +// negative dreg-1 LESS than POSITIVE dreg-2 +CC = R6 == R7; +R1 = ASTAT; +CC = R6 < R7 (IU); +R2 = ASTAT; +CC = R6 <= R7 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001006; // overflow and carry but not negative +CHECKREG r2, 0x00001004; // cc overflow, carry and negative +CHECKREG r3, 0x00001004; + + +pass; diff --git a/sim/testsuite/bfin/c_ccflag_dr_imm3.s b/sim/testsuite/bfin/c_ccflag_dr_imm3.s new file mode 100644 index 0000000..e584b80 --- /dev/null +++ b/sim/testsuite/bfin/c_ccflag_dr_imm3.s @@ -0,0 +1,224 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3/c_ccflag_dr_imm3.dsp +// Spec Reference: ccflag dr-imm3 +# mach: bfin + +.include "testutils.inc" + start + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000002; +imm32 r2, 0x00000003; +imm32 r3, 0x00000004; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R7; +R4 = ASTAT; + +// positive dreg EQUAL to positive imm3 +CC = R0 == 1; +R5 = ASTAT; +CC = R0 < 1; +R6 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CC = R0 <= 1; +R5 = ASTAT; +CC = R0 < 1; +R6 = ASTAT; +CC = R0 <= 1; +R7 = ASTAT; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CHECKREG r7, 0x00001025; + +// positive dreg GREATER than to positive imm3 +CC = R1 == 1; +R5 = ASTAT; +CC = R1 < 1; +R6 = ASTAT; +CC = R1 <= 1; +R7 = ASTAT; +CHECKREG r5, 0x00001004; // carry +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + +// positive dreg LESS than to positive imm3 +CC = R0 == 2; +R5 = ASTAT; +CC = R0 < 2; +R6 = ASTAT; +CC = R0 <= 2; +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// positive dreg GREATER than to neg imm3 +CC = R2 == -4; +R5 = ASTAT; +CC = R2 < -4; +R6 = ASTAT; +CC = R2 <= -4; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, -1; +imm32 r1, -2; +imm32 r2, -3; +imm32 r3, -4; +// negative dreg and positive imm3 +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +CC = R3 == 1; +R5 = ASTAT; +CC = R3 < 1; +R6 = ASTAT; +CC = R3 <= 1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001006; +CHECKREG r6, 0x00001026; +CHECKREG r7, 0x00001026; + +// negative dreg LESS than neg imm3 +CC = R2 == -1; +R4 = ASTAT; +CC = R2 < -1; +R5 = ASTAT; +CC = R2 <= -1; +R6 = ASTAT; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000022; +CHECKREG r6, 0x00000022; + +// negative dreg GREATER neg imm3 +CC = R0 == -4; +R4 = ASTAT; +CC = R0 < -4; +R5 = ASTAT; +CC = R0 <= -4; +R6 = ASTAT; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; + +imm32 r4, 0x00000001; +imm32 r5, 0x00000002; +imm32 r6, 0x00000003; +imm32 r7, 0x00000004; + +ASTAT = R0; +R3 = ASTAT; + +// positive dreg EQUAL to positive imm3 +CC = R4 == 1; +R1 = ASTAT; +CC = R4 < 1; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001025; +CHECKREG r2, 0x00001005; +CC = R4 <= 1; +R1 = ASTAT; +CC = R4 < 1; +R2 = ASTAT; +CC = R4 <= 1; +R3 = ASTAT; +CHECKREG r1, 0x00001025; +CHECKREG r2, 0x00001005; +CHECKREG r3, 0x00001025; + +// positive dreg GREATER than to positive imm3 +CC = R5 == 1; +R1 = ASTAT; +CC = R5 < 1; +R2 = ASTAT; +CC = R5 <= 1; +R3 = ASTAT; +CHECKREG r1, 0x00001004; // carry +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// positive dreg LESS than to positive imm3 +CC = R6 == 2; +R1 = ASTAT; +CC = R6 < 2; +R2 = ASTAT; +CC = R6 <= 2; +R3 = ASTAT; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// positive dreg GREATER than to neg imm3 +CC = R6 == -4; +R1 = ASTAT; +CC = R6 < -4; +R2 = ASTAT; +CC = R6 <= -4; +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + +imm32 r4, -1; +imm32 r5, -2; +imm32 r6, -3; +imm32 r7, -4; +// negative dreg and positive imm3 +R3 = 0; +ASTAT = R3; +R0 = ASTAT; + +CC = R7 == 1; +R1 = ASTAT; +CC = R7 < 1; +R2 = ASTAT; +CC = R7 <= 1; +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001006; +CHECKREG r2, 0x00001026; +CHECKREG r3, 0x00001026; + +// negative dreg LESS than neg imm3 +CC = R6 == -1; +R0 = ASTAT; +CC = R6 < -1; +R1 = ASTAT; +CC = R6 <= -1; +R2 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; + +// negative dreg GREATER neg imm3 +CC = R4 == -4; +R0 = ASTAT; +CC = R4 < -4; +R1 = ASTAT; +CC = R4 <= -4; +R2 = ASTAT; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; + + + +pass; diff --git a/sim/testsuite/bfin/c_ccflag_dr_imm3_uu.s b/sim/testsuite/bfin/c_ccflag_dr_imm3_uu.s new file mode 100644 index 0000000..d4a6a48 --- /dev/null +++ b/sim/testsuite/bfin/c_ccflag_dr_imm3_uu.s @@ -0,0 +1,221 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3_uu/c_ccflag_dr_imm3_uu.dsp +// Spec Reference: ccflag dr-imm3 (uu) +# mach: bfin + +.include "testutils.inc" + start + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000002; +imm32 r2, 0x00000003; +imm32 r3, 0x00000004; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R7; +R4 = ASTAT; + +// positive dreg EQUAL to positive imm3 +CC = R0 == 1; +R5 = ASTAT; +CC = R0 < 1; +R6 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CC = R0 <= 1; +R5 = ASTAT; +CC = R0 < 1 (IU); +R6 = ASTAT; +CC = R0 <= 1 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CHECKREG r7, 0x00001025; + +// positive dreg GREATER than to positive imm3 +CC = R1 == 1; +R5 = ASTAT; +CC = R1 < 1 (IU); +R6 = ASTAT; +CC = R1 <= 1 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001004; // carry +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + +// positive dreg LESS than to positive imm3 +CC = R0 == 2; +R5 = ASTAT; +CC = R0 < 2 (IU); +R6 = ASTAT; +CC = R0 <= 2 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// positive dreg GREATER than to neg imm3 +CC = R2 == -4; +R5 = ASTAT; +CC = R2 < 4 (IU); +R6 = ASTAT; +CC = R2 <= 4 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +imm32 r0, -1; +imm32 r1, -2; +imm32 r2, -3; +imm32 r3, -4; +// negative dreg and positive imm3 +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +CC = R3 == 1; +R5 = ASTAT; +CC = R3 < 1 (IU); +R6 = ASTAT; +CC = R3 <= 1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001006; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + +// negative dreg LESS than neg imm3 +CC = R2 == -1; +R4 = ASTAT; +CC = R2 < 1 (IU); +R5 = ASTAT; +CC = R2 <= 1 (IU); +R6 = ASTAT; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; + +// negative dreg GREATER neg imm3 +CC = R0 == -2; +R4 = ASTAT; +CC = R0 < 4 (IU); +R5 = ASTAT; +CC = R0 <= 4 (IU); +R6 = ASTAT; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; + +imm32 r4, 0x00000001; +imm32 r5, 0x00000002; +imm32 r6, 0x00000003; +imm32 r7, 0x00000004; + +ASTAT = R0; +R3 = ASTAT; + +// positive dreg EQUAL to positive imm3 +CC = R4 == 1; +R1 = ASTAT; +CC = R4 < 1 (IU); +R2 = ASTAT; +CC = R4 <= 1 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001025; +CHECKREG r2, 0x00001005; +CHECKREG r3, 0x00001025; + +// positive dreg GREATER than to positive imm3 +CC = R5 == 1; +R1 = ASTAT; +CC = R5 < 1 (IU); +R2 = ASTAT; +CC = R5 <= 1 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00001004; // carry +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// positive dreg LESS than to positive imm3 +CC = R6 == 2; +R1 = ASTAT; +CC = R6 < 2 (IU); +R2 = ASTAT; +CC = R6 <= 2 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// positive dreg GREATER than to neg imm3 +CC = R6 == -4; +R1 = ASTAT; +CC = R6 < 4 (IU); +R2 = ASTAT; +CC = R6 <= 4 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; + +imm32 r4, -1; +imm32 r5, -2; +imm32 r6, -3; +imm32 r7, -4; +// negative dreg and positive imm3 +R3 = 0; +ASTAT = R3; +R0 = ASTAT; + +CC = R7 == 1; +R1 = ASTAT; +CC = R7 < 1 (IU); +R2 = ASTAT; +CC = R7 <= 1 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001006; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// negative dreg LESS than neg imm3 +CC = R6 == -1; +R0 = ASTAT; +CC = R6 < 1 (IU); +R1 = ASTAT; +CC = R6 <= 1 (IU); +R2 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; + +// negative dreg GREATER neg imm3 +CC = R4 == -4; +R0 = ASTAT; +CC = R4 < 4 (IU); +R1 = ASTAT; +CC = R4 <= 4 (IU); +R2 = ASTAT; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; + + + + + + +pass; diff --git a/sim/testsuite/bfin/c_ccflag_pr_imm3.s b/sim/testsuite/bfin/c_ccflag_pr_imm3.s new file mode 100644 index 0000000..aa6a0eb --- /dev/null +++ b/sim/testsuite/bfin/c_ccflag_pr_imm3.s @@ -0,0 +1,539 @@ +//Original:/testcases/core/c_ccflag_pr_imm3/c_ccflag_pr_imm3.dsp +// Spec Reference: ccflag pr-imm3 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +//imm32 p0, 0x00000001; +imm32 p1, 0x00000001; +imm32 p2, 0x00000002; +imm32 p3, 0x00000003; +imm32 p4, 0x00000001; +imm32 p5, 0x00000002; +imm32 sp, 0x00000003; +imm32 fp, 0x00000003; + +R0 = 0; +ASTAT = R0; +// positive dreg EQUAL to positive imm3 +CC = P1 == 1; +R0 = ASTAT; +CC = P1 < 1; +R1 = ASTAT; +CC = P1 <= 1; +R2 = ASTAT; +CC = P2 == 2; +R3 = ASTAT; +CC = P2 < 2; +R4 = ASTAT; +CC = P2 <= 2; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P3 == 3; +R0 = ASTAT; +CC = P3 < 3; +R1 = ASTAT; +CC = P3 <= 3; +R2 = ASTAT; +CC = P4 == 1; +R3 = ASTAT; +CC = P4 < 1; +R4 = ASTAT; +CC = P4 <= 1; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P5 == 2; +R0 = ASTAT; +CC = P5 < 2; +R1 = ASTAT; +CC = P5 <= 2; +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 3; +R4 = ASTAT; +CC = SP <= 3; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 3; +R6 = ASTAT; +CC = FP <= 3; +R7 = ASTAT; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000020; + +// positive dreg GREATER than positive imm3 +imm32 p1, 0x00000002; +imm32 p2, 0x00000002; +imm32 p3, 0x00000003; +imm32 p4, 0x00000002; +imm32 p5, 0x00000002; +imm32 sp, 0x00000003; +imm32 fp, 0x00000003; +CC = P1 == 0; +R0 = ASTAT; +CC = P1 < 0; +R1 = ASTAT; +CC = P1 <= 0; +R2 = ASTAT; +CC = P2 == 1; +R3 = ASTAT; +CC = P2 < 1; +R4 = ASTAT; +CC = P2 <= 1; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P3 == 2; +R0 = ASTAT; +CC = P3 < 2; +R1 = ASTAT; +CC = P3 <= 2; +R2 = ASTAT; +CC = P4 == 0; +R3 = ASTAT; +CC = P4 < 0; +R4 = ASTAT; +CC = P4 <= 0; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P5 == 1; +R0 = ASTAT; +CC = P5 < 1; +R1 = ASTAT; +CC = P5 <= 1; +R2 = ASTAT; +CC = SP == 2; +R3 = ASTAT; +CC = SP < 2; +R4 = ASTAT; +CC = SP <= 2; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = FP == 2; +R5 = ASTAT; +CC = FP < 2; +R6 = ASTAT; +CC = FP <= 2; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// positive dreg LESS than positive imm3 +imm32 p1, 0x00000001; +imm32 p2, 0x00000002; +imm32 p3, 0x00000002; +imm32 p4, 0x00000001; +imm32 p5, 0x00000001; +imm32 sp, 0x00000002; +imm32 fp, 0x00000002; +CC = P1 == 2; +R0 = ASTAT; +CC = P1 < 2; +R1 = ASTAT; +CC = P1 <= 2; +R2 = ASTAT; +CC = P2 == 3; +R3 = ASTAT; +CC = P2 < 3; +R4 = ASTAT; +CC = P2 <= 3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P3 == 3; +R0 = ASTAT; +CC = P3 < 3; +R1 = ASTAT; +CC = P3 <= 3; +R2 = ASTAT; +CC = P4 == 3; +R3 = ASTAT; +CC = P4 < 3; +R4 = ASTAT; +CC = P4 <= 3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P5 == 3; +R0 = ASTAT; +CC = P5 < 3; +R1 = ASTAT; +CC = P5 <= 3; +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 3; +R4 = ASTAT; +CC = SP <= 3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 3; +R6 = ASTAT; +CC = FP <= 3; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + + +// positive dreg GREATER than neg imm3 +CC = P1 == -1; +R0 = ASTAT; +CC = P1 < -1; +R1 = ASTAT; +CC = P1 <= -1; +R2 = ASTAT; +CC = P2 == -2; +R3 = ASTAT; +CC = P2 < -2; +R4 = ASTAT; +CC = P2 <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P3 == -3; +R0 = ASTAT; +CC = P3 < -3; +R1 = ASTAT; +CC = P3 <= -3; +R2 = ASTAT; +CC = P4 == -4; +R3 = ASTAT; +CC = P4 < -4; +R4 = ASTAT; +CC = P4 <= -4; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P5 == -1; +R0 = ASTAT; +CC = P5 < -1; +R1 = ASTAT; +CC = P5 <= -1; +R2 = ASTAT; +CC = SP == -2; +R3 = ASTAT; +CC = SP < -2; +R4 = ASTAT; +CC = SP <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = FP == -4; +R5 = ASTAT; +CC = FP < -4; +R6 = ASTAT; +CC = FP <= -4; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + + +imm32 p1, -1; +imm32 p2, -2; +imm32 p3, -3; +imm32 p4, -4; +imm32 p5, -1; +imm32 sp, -2; +imm32 fp, -3; +// negative dreg equal negative imm3 +CC = P1 == -1; +R0 = ASTAT; +CC = P1 < -1; +R1 = ASTAT; +CC = P1 <= -1; +R2 = ASTAT; +CC = P2 == -2; +R3 = ASTAT; +CC = P2 < -2; +R4 = ASTAT; +CC = P2 <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P3 == -3; +R0 = ASTAT; +CC = P3 < -3; +R1 = ASTAT; +CC = P3 <= -3; +R2 = ASTAT; +CC = P4 == -4; +R3 = ASTAT; +CC = P4 < -4; +R4 = ASTAT; +CC = P4 <= -4; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P5 == -1; +R0 = ASTAT; +CC = P5 < -1; +R1 = ASTAT; +CC = P5 <= -1; +R2 = ASTAT; +CC = SP == -2; +R3 = ASTAT; +CC = SP < -2; +R4 = ASTAT; +CC = SP <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = FP == -3; +R5 = ASTAT; +CC = FP < -3; +R6 = ASTAT; +CC = FP <= -3; +R7 = ASTAT; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000020; + + +// negative dreg GREATER neg imm3 +imm32 p1, -1; +imm32 p2, -1; +imm32 p3, -2; +imm32 p4, -3; +imm32 p5, -1; +imm32 sp, -2; +imm32 fp, -3; +CC = P1 == -2; +R0 = ASTAT; +CC = P1 < -2; +R1 = ASTAT; +CC = P1 <= -2; +R2 = ASTAT; +CC = P2 == -3; +R3 = ASTAT; +CC = P2 < -3; +R4 = ASTAT; +CC = P2 <= -3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P3 == -4; +R0 = ASTAT; +CC = P3 < -4; +R1 = ASTAT; +CC = P3 <= -4; +R2 = ASTAT; +CC = P4 == -4; +R3 = ASTAT; +CC = P4 < -4; +R4 = ASTAT; +CC = P4 <= -4; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P5 == -2; +R0 = ASTAT; +CC = P5 < -2; +R1 = ASTAT; +CC = P5 <= -2; +R2 = ASTAT; +CC = SP == -3; +R3 = ASTAT; +CC = SP < -3; +R4 = ASTAT; +CC = SP <= -3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = FP == -4; +R5 = ASTAT; +CC = FP < -4; +R6 = ASTAT; +CC = FP <= -4; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// negative dreg LESS than neg imm3 +imm32 p1, -2; +imm32 p2, -2; +imm32 p3, -3; +imm32 p4, -3; +imm32 p5, -4; +imm32 sp, -4; +imm32 fp, -4; +imm32 p4, -4; +CC = P1 == -1; +R0 = ASTAT; +CC = P1 < -1; +R1 = ASTAT; +CC = P1 <= -1; +R2 = ASTAT; +CC = P2 == -1; +R3 = ASTAT; +CC = P2 < -1; +R4 = ASTAT; +CC = P2 <= -1; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P3 == -2; +R0 = ASTAT; +CC = P3 < -2; +R1 = ASTAT; +CC = P3 <= -2; +R2 = ASTAT; +CC = P4 == -2; +R3 = ASTAT; +CC = P4 < -2; +R4 = ASTAT; +CC = P4 <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P5 == -3; +R0 = ASTAT; +CC = P5 < -3; +R1 = ASTAT; +CC = P5 <= -3; +R2 = ASTAT; +CC = SP == -3; +R3 = ASTAT; +CC = SP < -3; +R4 = ASTAT; +CC = SP <= -3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = FP == -3; +R5 = ASTAT; +CC = FP < -3; +R6 = ASTAT; +CC = FP <= -3; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + + +pass diff --git a/sim/testsuite/bfin/c_ccflag_pr_imm3_uu.s b/sim/testsuite/bfin/c_ccflag_pr_imm3_uu.s new file mode 100644 index 0000000..6b18702 --- /dev/null +++ b/sim/testsuite/bfin/c_ccflag_pr_imm3_uu.s @@ -0,0 +1,238 @@ +//Original:/testcases/core/c_ccflag_pr_imm3_uu/c_ccflag_pr_imm3_uu.dsp +// Spec Reference: ccflag pr-imm3 (uu) +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS 0; + + +//imm32 p0, 0x00000001; +imm32 p1, 0x00000001; +imm32 p2, 0x00000002; +imm32 p3, 0x00000003; +imm32 p4, 0x00000004; +imm32 p5, 0x00000005; +imm32 sp, 0x00000006; +imm32 fp, 0x00000007; + +R0 = 0; +ASTAT = R0; +// positive preg EQUAL to positive imm3 +CC = P1 == 1; +R0 = ASTAT; +CC = P1 < 1 (IU); +R1 = ASTAT; +CC = P1 <= 1 (IU); +R2 = ASTAT; +CC = P2 == 2; +R3 = ASTAT; +CC = P2 < 2 (IU); +R4 = ASTAT; +CC = P2 <= 2 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P3 == 3; +R0 = ASTAT; +CC = P3 < 3 (IU); +R1 = ASTAT; +CC = P3 <= 3 (IU); +R2 = ASTAT; +CC = P4 == 3; +R3 = ASTAT; +CC = P4 < 4 (IU); +R4 = ASTAT; +CC = P4 <= 4 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P5 == 3; +R0 = ASTAT; +CC = P5 < 5 (IU); +R1 = ASTAT; +CC = P5 <= 5 (IU); +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 6 (IU); +R4 = ASTAT; +CC = SP <= 6 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 7 (IU); +R6 = ASTAT; +CC = FP <= 7 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000020; + +// positive preg GREATER than positive imm3 +CC = P1 == 0; +R0 = ASTAT; +CC = P1 < 0 (IU); +R1 = ASTAT; +CC = P1 <= 0 (IU); +R2 = ASTAT; +CC = P2 == 1; +R3 = ASTAT; +CC = P2 < 1 (IU); +R4 = ASTAT; +CC = P2 <= 1 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P3 == 2; +R0 = ASTAT; +CC = P3 < 2 (IU); +R1 = ASTAT; +CC = P3 <= 2 (IU); +R2 = ASTAT; +CC = P4 == 3; +R3 = ASTAT; +CC = P4 < 3 (IU); +R4 = ASTAT; +CC = P4 <= 3 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P5 == 3; +R0 = ASTAT; +CC = P5 < 4 (IU); +R1 = ASTAT; +CC = P5 <= 4 (IU); +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 5 (IU); +R4 = ASTAT; +CC = SP <= 5 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 6 (IU); +R6 = ASTAT; +CC = FP <= 6 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// positive preg LESS than positive imm3 +imm32 p1, 0x00000000; +imm32 p2, 0x00000001; +imm32 p3, 0x00000002; +imm32 p4, 0x00000003; +imm32 p5, 0x00000004; +imm32 sp, 0x00000005; +imm32 fp, 0x00000006; +CC = P1 == 2; +R0 = ASTAT; +CC = P1 < 2 (IU); +R1 = ASTAT; +CC = P1 <= 2 (IU); +R2 = ASTAT; +CC = P2 == 3; +R3 = ASTAT; +CC = P2 < 3 (IU); +R4 = ASTAT; +CC = P2 <= 3 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P3 == 3; +R0 = ASTAT; +CC = P3 < 4 (IU); +R1 = ASTAT; +CC = P3 <= 4 (IU); +R2 = ASTAT; +CC = P4 == 3; +R3 = ASTAT; +CC = P4 < 5 (IU); +R4 = ASTAT; +CC = P4 <= 5 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P5 == 3; +R0 = ASTAT; +CC = P5 < 6 (IU); +R1 = ASTAT; +CC = P5 <= 6 (IU); +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 7 (IU); +R4 = ASTAT; +CC = SP <= 7 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 7 (IU); +R6 = ASTAT; +CC = FP <= 7 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + + + + +pass diff --git a/sim/testsuite/bfin/c_ccflag_pr_pr.s b/sim/testsuite/bfin/c_ccflag_pr_pr.s new file mode 100644 index 0000000..ef9db52 --- /dev/null +++ b/sim/testsuite/bfin/c_ccflag_pr_pr.s @@ -0,0 +1,262 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr/c_ccflag_pr_pr.dsp +// Spec Reference: ccflag pr-pr +# mach: bfin + +.include "testutils.inc" + start + +INIT_P_REGS 0; +INIT_R_REGS 0; + + +//imm32 p0, 0x00110022; +imm32 p1, 0x00110022; +imm32 p2, 0x00330044; +imm32 p3, 0x00550066; + +imm32 p4, 0x00770088; +imm32 p5, 0x009900aa; +imm32 fp, 0x00bb00cc; +imm32 sp, 0x00000000; + +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// positive preg-1 EQUAL to positive preg-2 +CC = P2 == P1; +R5 = ASTAT; +P5 = R5; +CC = P2 < P1; +R6 = ASTAT; +CC = P2 <= P1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// positive preg-1 GREATER than positive preg-2 +CC = P3 == P2; +R5 = ASTAT; +CC = P3 < P2; +R6 = ASTAT; +CC = P3 <= P2; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +// positive preg-1 LESS than positive preg-2 +CC = P2 == P3; +R5 = ASTAT; +CC = P2 < P3; +R6 = ASTAT; +CC = P2 <= P3; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +//imm32 p0, 0x01230123; +imm32 p1, 0x81230123; +imm32 p2, 0x04560456; +imm32 p3, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// positive preg-1 GREATER than negative preg-2 +CC = P2 == P1; +R5 = ASTAT; +CC = P2 < P1; +R6 = ASTAT; +CC = P2 <= P1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// negative preg-1 LESS than POSITIVE preg-2 small +CC = P3 == P2; +R5 = ASTAT; +CC = P3 < P2; +R6 = ASTAT; +CC = P3 <= P2; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +// negative preg-1 GREATER than negative preg-2 +CC = P1 == P3; +R5 = ASTAT; +CC = P1 < P3; +R6 = ASTAT; +CC = P1 <= P3; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +// negative preg-1 LESS than negative preg-2 +CC = P3 == P1; +R5 = ASTAT; +CC = P3 < P1; +R6 = ASTAT; +CC = P3 <= P1; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +//imm32 p0, 0x80230123; +imm32 p1, 0x00230123; +imm32 p2, 0x80560056; +imm32 p3, 0x00890089; +// operate on negative number +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// negative preg-1 LESS than POSITIVE preg-2 +CC = P2 == P3; +R5 = ASTAT; +CC = P2 < P3; +R6 = ASTAT; +CC = P2 <= P3; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; // overflow and carry but not negative +CHECKREG r6, 0x00000020; // cc overflow, carry and negative +CHECKREG r7, 0x00000020; + + +imm32 p4, 0x44444444; +imm32 p5, 0x55555555; +imm32 fp, 0x66666666; +imm32 sp, 0x77777777; + +//imm32 p0, 0x00000000; +imm32 p1, 0x11111111; +imm32 p2, 0x00000000; +imm32 p3, 0x33333333; + +ASTAT = R0; +R3 = ASTAT; +CHECKREG r3, 0x00000000; + +// positive preg-1 EQUAL to positive preg-2 +CC = P4 == P5; +R0 = ASTAT; +CC = P4 < P5; +R1 = ASTAT; +CC = P4 <= P5; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// positive preg-1 GREATER than positive preg-2 +CC = SP == FP; +R0 = ASTAT; +CC = SP < FP; +R1 = ASTAT; +CC = SP <= FP; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; + + +// positive preg-1 LESS than positive preg-2 +CC = FP == SP; +R0 = ASTAT; +CC = FP < SP; +R1 = ASTAT; +CC = FP <= SP; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +imm32 p4, 0x01230123; +imm32 p5, 0x81230123; +imm32 fp, 0x04560456; +imm32 sp, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R3 = ASTAT; // nop; +CHECKREG r3, 0x00000000; + +// positive preg-1 GREATER than negative preg-2 +CC = P4 == P5; +R1 = ASTAT; +CC = P4 < P5; +R2 = ASTAT; +CC = P4 <= P5; +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + +// negative preg-1 LESS than POSITIVE preg-2 small +CC = SP == FP; +R0 = ASTAT; +CC = SP < FP; +R1 = ASTAT; +CC = SP <= FP; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// negative preg-1 GREATER than negative preg-2 +CC = P5 == SP; +R0 = ASTAT; +CC = P5 < SP; +R1 = ASTAT; +CC = P5 <= SP; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// negative preg-1 LESS than negative preg-2 +CC = SP == P5; +R1 = ASTAT; +CC = SP < P5; +R2 = ASTAT; +CC = SP <= P5; +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + + +imm32 p4, 0x80230123; +imm32 p5, 0x00230123; +imm32 fp, 0x80560056; +imm32 sp, 0x00890089; +// operate on negative number +P3 = 0; +ASTAT = P3; +R0 = ASTAT; + +// negative preg-1 LESS than POSITIVE preg-2 +CC = R6 == R7; +R1 = ASTAT; +CC = R6 < R7; +R2 = ASTAT; +CC = R6 <= R7; +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001025; // overflow and carry but not negative +CHECKREG r2, 0x00001005; // cc overflow, carry and negative +CHECKREG r3, 0x00001025; + + +pass; diff --git a/sim/testsuite/bfin/c_ccflag_pr_pr_uu.s b/sim/testsuite/bfin/c_ccflag_pr_pr_uu.s new file mode 100644 index 0000000..0cde8c2 --- /dev/null +++ b/sim/testsuite/bfin/c_ccflag_pr_pr_uu.s @@ -0,0 +1,212 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr_uu/c_ccflag_pr_pr_uu.dsp +// Spec Reference: ccflag pr-pr (uu) +# mach: bfin + +.include "testutils.inc" + start + +INIT_R_REGS 0; + +//imm32 p0, 0x00110022; +imm32 p1, 0x00110022; +imm32 p2, 0x00330044; +imm32 p3, 0x00550066; + +imm32 p4, 0x00770088; +imm32 p5, 0x009900aa; +imm32 fp, 0x00bb00cc; +imm32 sp, 0x00000000; + +ASTAT = R0; +R4 = ASTAT; + +// positive preg-1 EQUAL to positive preg-2 +CC = P2 < P1 (IU); +R6 = ASTAT; +CC = P2 <= P1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// positive preg-1 GREATER than positive preg-2 +CC = P3 < P2 (IU); +R6 = ASTAT; +CC = P3 <= P2 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +// positive preg-1 LESS than positive preg-2 +CC = P2 < P3 (IU); +R6 = ASTAT; +CC = P2 <= P3 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +//imm32 p0, 0x01230123; +imm32 p1, 0x81230123; +imm32 p2, 0x04560456; +imm32 p3, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// positive preg-1 GREATER than negative preg-2 +CC = P2 < P1 (IU); +R6 = ASTAT; +CC = P2 <= P1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +// negative preg-1 LESS than POSITIVE preg-2 small +CC = P3 < P2 (IU); +R6 = ASTAT; +CC = P3 <= P2 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// negative preg-1 GREATER than negative preg-2 +CC = P1 < P3 (IU); +R6 = ASTAT; +CC = P1 <= P3 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +// negative preg-1 LESS than negative preg-2 +CC = P3 < P1 (IU); +R6 = ASTAT; +CC = P3 <= P1 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +//imm32 p0, 0x80230123; +imm32 p1, 0x00230123; +imm32 p2, 0x80560056; +imm32 p3, 0x00890089; +// operate on negative number +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// negative preg-1 LESS than POSITIVE preg-2 +CC = P2 < P3 (IU); +R6 = ASTAT; +CC = P2 <= P3 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; // overflow and carry but not negative +CHECKREG r6, 0x00000000; // cc overflow, carry and negative +CHECKREG r7, 0x00000000; + + +imm32 p4, 0x44444444; +imm32 p5, 0x55555555; +imm32 fp, 0x66666666; +imm32 sp, 0x77777777; + +//imm32 p0, 0x00000000; +imm32 p1, 0x11111111; +imm32 p2, 0x00000000; +imm32 p3, 0x33333333; + +ASTAT = R0; +R3 = ASTAT; +CHECKREG r3, 0x00000000; + +// positive preg-1 EQUAL to positive preg-2 +CC = P4 < P5; +R1 = ASTAT; +CC = P4 <= P5; +R2 = ASTAT; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// positive preg-1 GREATER than positive preg-2 +CC = SP < FP (IU); +R1 = ASTAT; +CC = SP <= FP (IU); +R2 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; + + +// positive preg-1 LESS than positive preg-2 +CC = FP < SP (IU); +R1 = ASTAT; +CC = FP <= SP (IU); +R2 = ASTAT; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +imm32 p4, 0x01230123; +imm32 p5, 0x81230123; +imm32 fp, 0x04560456; +imm32 sp, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R3 = ASTAT; // nop; +CHECKREG r3, 0x00000000; + +// positive preg-1 GREATER than negative preg-2 +CC = P4 < P5 (IU); +R2 = ASTAT; +CC = P4 <= P5 (IU); +R3 = ASTAT; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; + +// negative preg-1 LESS than POSITIVE preg-2 small +CC = SP < FP (IU); +R1 = ASTAT; +CC = SP <= FP (IU); +R2 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; + +// negative preg-1 GREATER than negative preg-2 +CC = P5 < SP (IU); +R1 = ASTAT; +CC = P5 <= SP (IU); +R2 = ASTAT; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// negative preg-1 LESS than negative preg-2 +CC = SP < P5 (IU); +R2 = ASTAT; +CC = SP <= P5 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + + +imm32 p4, 0x80230123; +imm32 p5, 0x00230123; +imm32 fp, 0x80560056; +imm32 sp, 0x00890089; +// operate on negative number +R0 = 0; +ASTAT = R0; +R0 = ASTAT; + +// negative preg-1 LESS than POSITIVE preg-2 +CC = R6 < R7 (IU); +R2 = ASTAT; +CC = R6 <= R7 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000000; // overflow and carry but not negative +CHECKREG r2, 0x00001005; // cc overflow, carry and negative +CHECKREG r3, 0x00001025; + + +pass; diff --git a/sim/testsuite/bfin/c_ccmv_cc_dr_dr.s b/sim/testsuite/bfin/c_ccmv_cc_dr_dr.s new file mode 100644 index 0000000..b9e4fa6 --- /dev/null +++ b/sim/testsuite/bfin/c_ccmv_cc_dr_dr.s @@ -0,0 +1,124 @@ +//Original:/testcases/core/c_ccmv_cc_dr_dr/c_ccmv_cc_dr_dr.dsp +// Spec Reference: ccmv cc dreg = dreg +# mach: bfin + +.include "testutils.inc" + start + +R0 = 0; +ASTAT = R0; + + +imm32 r0, 0xa08d2301; +imm32 r1, 0xd0021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x60b61507; +imm32 r4, 0x50487609; +imm32 r5, 0x3005900b; +imm32 r6, 0x2a0c660d; +imm32 r7, 0xd90e108f; +IF CC R0 = R0; +IF CC R1 = R3; +IF CC R2 = R5; +IF CC R3 = R2; +CC = ! CC; +IF CC R4 = R6; +IF CC R5 = R1; +IF CC R6 = R7; +CC = ! CC; +IF CC R7 = R4; +CHECKREG r0, 0xA08D2301; +CHECKREG r1, 0xD0021053; +CHECKREG r2, 0x2F041405; +CHECKREG r3, 0x60B61507; +CHECKREG r4, 0x2A0C660D; +CHECKREG r5, 0xD0021053; +CHECKREG r6, 0xD90E108F; +CHECKREG r7, 0xD90E108F; + + +imm32 r0, 0x308d2301; +imm32 r1, 0xd4023053; +imm32 r2, 0x2f041405; +imm32 r3, 0x60f61507; +imm32 r4, 0xd0487f09; +imm32 r5, 0x300b900b; +imm32 r6, 0x2a0cd60d; +imm32 r7, 0xd90e189f; +IF CC R4 = R3; +IF CC R5 = R7; +IF CC R6 = R1; +IF CC R7 = R2; +CC = ! CC; +IF CC R0 = R6; +IF CC R1 = R5; +IF CC R2 = R4; +CC = ! CC; +IF CC R3 = R0; +CHECKREG r0, 0x2A0CD60D; +CHECKREG r1, 0x300B900B; +CHECKREG r2, 0xD0487F09; +CHECKREG r3, 0x60F61507; +CHECKREG r4, 0xD0487F09; +CHECKREG r5, 0x300B900B; +CHECKREG r6, 0x2A0CD60D; +CHECKREG r7, 0xD90E189F; + + +imm32 r0, 0x708d2301; +imm32 r1, 0xd8021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x65b61507; +imm32 r4, 0x59487609; +imm32 r5, 0x3005900b; +imm32 r6, 0x2abc660d; +imm32 r7, 0xd90e108f; +IF CC R0 = R2; +IF CC R1 = R3; +CC = ! CC; +IF CC R2 = R5; +IF CC R3 = R7; +CC = ! CC; +IF CC R4 = R1; +IF CC R5 = R4; +IF CC R6 = R7; +IF CC R7 = R6; +CHECKREG r0, 0x708D2301; +CHECKREG r1, 0xD8021053; +CHECKREG r2, 0x3005900B; +CHECKREG r3, 0xD90E108F; +CHECKREG r4, 0x59487609; +CHECKREG r5, 0x3005900B; +CHECKREG r6, 0x2ABC660D; +CHECKREG r7, 0xD90E108F; + + +imm32 r0, 0xc08d2301; +imm32 r1, 0xdb021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x64b61507; +imm32 r4, 0x50487609; +imm32 r5, 0x30f5900b; +imm32 r6, 0x2a4c660d; +imm32 r7, 0x895e108f; +IF CC R4 = R3; +IF CC R5 = R7; +CC = ! CC; +IF CC R6 = R2; +IF CC R7 = R6; +CC = ! CC; +IF CC R0 = R1; +IF CC R1 = R2; +IF CC R2 = R0; +IF CC R3 = R4; +CHECKREG r0, 0xC08D2301; +CHECKREG r1, 0xDB021053; +CHECKREG r2, 0x2F041405; +CHECKREG r3, 0x64B61507; +CHECKREG r4, 0x50487609; +CHECKREG r5, 0x30F5900B; +CHECKREG r6, 0x2F041405; +CHECKREG r7, 0x2F041405; + + +pass diff --git a/sim/testsuite/bfin/c_ccmv_cc_dr_pr.s b/sim/testsuite/bfin/c_ccmv_cc_dr_pr.s new file mode 100644 index 0000000..186a199 --- /dev/null +++ b/sim/testsuite/bfin/c_ccmv_cc_dr_pr.s @@ -0,0 +1,61 @@ +//Original:/proj/frio/dv/testcases/core/c_ccmv_cc_dr_pr/c_ccmv_cc_dr_pr.dsp +// Spec Reference: ccmv cc dpreg = dpreg +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x138d2301; + imm32 r1, 0x20421053; + imm32 r2, 0x3f051405; + imm32 r3, 0x40b66507; + imm32 r4, 0x50487709; + imm32 r5, 0x6005908b; + imm32 r6, 0x7a0c6609; + imm32 r7, 0x890e108f; + imm32 p1, 0x9d021053; + imm32 p2, 0xafb41405; + imm32 p3, 0xb0bf1507; + imm32 p4, 0xd0483609; + imm32 p5, 0xe005d00b; + imm32 sp, 0xfa0c667d; + imm32 fp, 0xc90e108f; + IF CC R0 = P0; + IF CC P1 = R3; + IF CC R2 = P5; + IF CC P2 = R2; + CC = ! CC; + IF CC P3 = R6; + IF CC R5 = P1; + IF CC P4 = R7; + CC = ! CC; + IF CC R7 = P4; + IF CC P5 = R3; + IF CC R6 = SP; + IF CC R3 = P2; + CC = ! CC; + IF CC SP = R6; + IF CC R1 = P5; + IF CC FP = R4; + CC = ! CC; + IF CC R3 = P3; + CHECKREG r0, 0x138D2301; + CHECKREG r1, 0xE005D00B; + CHECKREG r2, 0x3F051405; + CHECKREG r3, 0x40B66507; + CHECKREG r4, 0x50487709; + CHECKREG r5, 0x9D021053; + CHECKREG r6, 0x7A0C6609; + CHECKREG r7, 0x890E108F; + CHECKREG p1, 0x9D021053; + CHECKREG p2, 0xAFB41405; + CHECKREG p3, 0x7A0C6609; + CHECKREG p4, 0x890E108F; + CHECKREG p5, 0xE005D00B; + CHECKREG sp, 0x7A0C6609; + CHECKREG fp, 0x50487709; + + pass diff --git a/sim/testsuite/bfin/c_ccmv_cc_pr_pr.s b/sim/testsuite/bfin/c_ccmv_cc_pr_pr.s new file mode 100644 index 0000000..df93ccb --- /dev/null +++ b/sim/testsuite/bfin/c_ccmv_cc_pr_pr.s @@ -0,0 +1,111 @@ +//Original:/proj/frio/dv/testcases/core/c_ccmv_cc_pr_pr/c_ccmv_cc_pr_pr.dsp +// Spec Reference: ccmv cc preg = preg +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 p1, 0xd0021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x60b61507; + imm32 p4, 0x50487609; + imm32 p5, 0x3005900b; + imm32 sp, 0x2a0c660d; + imm32 fp, 0xd90e108f; + IF CC P3 = P3; + IF CC P1 = P3; + IF CC P2 = P5; + IF CC P3 = P2; + CC = ! CC; + IF CC P4 = SP; + IF CC P5 = P1; + IF CC SP = FP; + CC = ! CC; + IF CC FP = P4; + CHECKREG p1, 0xD0021053; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x60B61507; + CHECKREG p4, 0x2A0C660D; + CHECKREG p5, 0xD0021053; + CHECKREG sp, 0xD90E108F; + CHECKREG fp, 0xD90E108F; + + imm32 p1, 0xd4023053; + imm32 p2, 0x2f041405; + imm32 p3, 0x60f61507; + imm32 p4, 0xd0487f09; + imm32 p5, 0x300b900b; + imm32 sp, 0x2a0cd60d; + imm32 fp, 0xd90e189f; + IF CC P4 = P3; + IF CC P5 = FP; + IF CC SP = P1; + IF CC FP = P2; + CC = ! CC; + IF CC P3 = SP; + IF CC P1 = P5; + IF CC P2 = P4; + CC = ! CC; + IF CC P3 = P2; + CHECKREG p1, 0x300B900B; + CHECKREG p2, 0xD0487F09; + CHECKREG p3, 0x2A0CD60D; + CHECKREG p4, 0xD0487F09; + CHECKREG p5, 0x300B900B; + CHECKREG sp, 0x2A0CD60D; + CHECKREG fp, 0xD90E189F; + + imm32 p1, 0xd8021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x65b61507; + imm32 p4, 0x59487609; + imm32 p5, 0x3005900b; + imm32 sp, 0x2abc660d; + imm32 fp, 0xd90e108f; + IF CC P3 = P2; + IF CC P1 = P3; + CC = ! CC; + IF CC P2 = P5; + IF CC P3 = FP; + CC = ! CC; + IF CC P4 = P1; + IF CC P5 = P4; + IF CC SP = FP; + IF CC FP = SP; + CHECKREG p1, 0xD8021053; + CHECKREG p2, 0x3005900B; + CHECKREG p3, 0xD90E108F; + CHECKREG p4, 0x59487609; + CHECKREG p5, 0x3005900B; + CHECKREG sp, 0x2ABC660D; + CHECKREG fp, 0xD90E108F; + + imm32 p1, 0xdb021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x64b61507; + imm32 p4, 0x50487609; + imm32 p5, 0x30f5900b; + imm32 sp, 0x2a4c660d; + imm32 fp, 0x895e108f; + IF CC P4 = P3; + IF CC P5 = FP; + CC = ! CC; + IF CC SP = P2; + IF CC FP = SP; + CC = ! CC; + IF CC P3 = P1; + IF CC P1 = P2; + IF CC P2 = P3; + IF CC P3 = P4; + CHECKREG p1, 0xDB021053; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x64B61507; + CHECKREG p4, 0x50487609; + CHECKREG p5, 0x30F5900B; + CHECKREG sp, 0x2F041405; + CHECKREG fp, 0x2F041405; + + pass diff --git a/sim/testsuite/bfin/c_ccmv_ncc_dr_dr.s b/sim/testsuite/bfin/c_ccmv_ncc_dr_dr.s new file mode 100644 index 0000000..94a6e32 --- /dev/null +++ b/sim/testsuite/bfin/c_ccmv_ncc_dr_dr.s @@ -0,0 +1,123 @@ +//Original:/testcases/core/c_ccmv_ncc_dr_dr/c_ccmv_ncc_dr_dr.dsp +// Spec Reference: ccmv !cc dreg = dreg +# mach: bfin + +.include "testutils.inc" + start +R0 = 0; +ASTAT = R0; + + +imm32 r0, 0x808d2301; +imm32 r1, 0x90021053; +imm32 r2, 0x21041405; +imm32 r3, 0x60261507; +imm32 r4, 0x50447609; +imm32 r5, 0xdfe5500b; +imm32 r6, 0x2a0c660d; +imm32 r7, 0xd90e1b8f; +IF !CC R0 = R0; +IF !CC R1 = R3; +IF !CC R2 = R5; +IF !CC R3 = R2; +CC = ! CC; +IF !CC R4 = R6; +IF !CC R5 = R1; +IF !CC R6 = R7; +CC = ! CC; +IF !CC R7 = R4; +CHECKREG r0, 0x808D2301; +CHECKREG r1, 0x60261507; +CHECKREG r2, 0xDFE5500B; +CHECKREG r3, 0xDFE5500B; +CHECKREG r4, 0x50447609; +CHECKREG r5, 0xDFE5500B; +CHECKREG r6, 0x2A0C660D; +CHECKREG r7, 0x50447609; + + +imm32 r0, 0x308d2301; +imm32 r1, 0xd4023053; +imm32 r2, 0x2f041405; +imm32 r3, 0x60f61507; +imm32 r4, 0xd0487f09; +imm32 r5, 0x300b900b; +imm32 r6, 0x2a0cd60d; +imm32 r7, 0xd90e189f; +IF !CC R4 = R3; +IF !CC R5 = R7; +IF !CC R6 = R1; +IF !CC R7 = R2; +CC = ! CC; +IF !CC R0 = R6; +IF !CC R1 = R5; +IF !CC R2 = R4; +CC = ! CC; +IF !CC R3 = R0; +CHECKREG r0, 0x308D2301; +CHECKREG r1, 0xD4023053; +CHECKREG r2, 0x2F041405; +CHECKREG r3, 0x308D2301; +CHECKREG r4, 0x60F61507; +CHECKREG r5, 0xD90E189F; +CHECKREG r6, 0xD4023053; +CHECKREG r7, 0x2F041405; + + +imm32 r0, 0x708d2301; +imm32 r1, 0xd8021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x65b61507; +imm32 r4, 0x59487609; +imm32 r5, 0x3005900b; +imm32 r6, 0x2abc660d; +imm32 r7, 0xd90e108f; +IF !CC R0 = R2; +IF !CC R1 = R3; +CC = ! CC; +IF !CC R2 = R5; +IF !CC R3 = R7; +CC = ! CC; +IF !CC R4 = R1; +IF !CC R5 = R4; +IF !CC R6 = R7; +IF !CC R7 = R6; +CHECKREG r0, 0x2F041405; +CHECKREG r1, 0x65B61507; +CHECKREG r2, 0x2F041405; +CHECKREG r3, 0x65B61507; +CHECKREG r4, 0x65B61507; +CHECKREG r5, 0x65B61507; +CHECKREG r6, 0xD90E108F; +CHECKREG r7, 0xD90E108F; + + +imm32 r0, 0xc08d2301; +imm32 r1, 0xdb021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x64b61507; +imm32 r4, 0x50487609; +imm32 r5, 0x30f5900b; +imm32 r6, 0x2a4c660d; +imm32 r7, 0x895e108f; +IF !CC R4 = R3; +IF !CC R5 = R7; +CC = ! CC; +IF !CC R6 = R2; +IF !CC R7 = R6; +CC = ! CC; +IF !CC R0 = R1; +IF !CC R1 = R2; +IF !CC R2 = R0; +IF !CC R3 = R4; +CHECKREG r0, 0xDB021053; +CHECKREG r1, 0x2F041405; +CHECKREG r2, 0xDB021053; +CHECKREG r3, 0x64B61507; +CHECKREG r4, 0x64B61507; +CHECKREG r5, 0x895E108F; +CHECKREG r6, 0x2A4C660D; +CHECKREG r7, 0x895E108F; + + +pass diff --git a/sim/testsuite/bfin/c_ccmv_ncc_dr_pr.s b/sim/testsuite/bfin/c_ccmv_ncc_dr_pr.s new file mode 100644 index 0000000..1b981ac --- /dev/null +++ b/sim/testsuite/bfin/c_ccmv_ncc_dr_pr.s @@ -0,0 +1,60 @@ +//Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_dr_pr/c_ccmv_ncc_dr_pr.dsp +// Spec Reference: ccmv !cc dpreg = dpreg +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x138d2301; + imm32 r1, 0x20421053; + imm32 r2, 0x3f051405; + imm32 r3, 0x40b66507; + imm32 r4, 0x50487709; + imm32 r5, 0x6005908b; + imm32 r6, 0x7a0c6609; + imm32 r7, 0x890e108f; + imm32 p1, 0x9d021053; + imm32 p2, 0xafb41405; + imm32 p3, 0xb0bf1507; + imm32 p4, 0xd0483609; + imm32 p5, 0xe005d00b; + imm32 sp, 0xfa0c667d; + imm32 fp, 0xc90e108f; + IF !CC R0 = P0; + CC = ! CC; + IF !CC P1 = R3; + IF !CC R2 = P5; + IF !CC P2 = R2; + IF !CC P3 = R6; + IF !CC R5 = P1; + CC = ! CC; + IF !CC P4 = R7; + IF !CC R7 = P4; + IF !CC P5 = R3; + IF !CC R6 = SP; + CC = ! CC; + IF !CC R3 = P2; + IF !CC SP = R6; + IF !CC R1 = P5; + CC = ! CC; + IF !CC FP = R4; + IF !CC R3 = P3; + CHECKREG r1, 0x20421053; + CHECKREG r2, 0x3F051405; + CHECKREG r3, 0xB0BF1507; + CHECKREG r4, 0x50487709; + CHECKREG r5, 0x6005908B; + CHECKREG r6, 0xFA0C667D; + CHECKREG r7, 0x890E108F; + CHECKREG p1, 0x9D021053; + CHECKREG p2, 0xAFB41405; + CHECKREG p3, 0xB0BF1507; + CHECKREG p4, 0x890E108F; + CHECKREG p5, 0x40B66507; + CHECKREG sp, 0xFA0C667D; + CHECKREG fp, 0x50487709; + + pass diff --git a/sim/testsuite/bfin/c_ccmv_ncc_pr_pr.s b/sim/testsuite/bfin/c_ccmv_ncc_pr_pr.s new file mode 100644 index 0000000..58c38ed --- /dev/null +++ b/sim/testsuite/bfin/c_ccmv_ncc_pr_pr.s @@ -0,0 +1,111 @@ +//Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_pr_pr/c_ccmv_ncc_pr_pr.dsp +// Spec Reference: ccmv !cc preg = preg +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 p1, 0xd0021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x60b61507; + imm32 p4, 0x50487609; + imm32 p5, 0x3005900b; + imm32 sp, 0x2a0c660d; + imm32 fp, 0xd90e108f; + IF !CC P3 = P3; + IF !CC P1 = P3; + CC = ! CC; + IF !CC P2 = P5; + IF !CC P3 = P2; + IF !CC P4 = SP; + IF !CC P5 = P1; + IF !CC SP = FP; + CC = ! CC; + IF !CC FP = P4; + CHECKREG p1, 0x60B61507; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x60B61507; + CHECKREG p4, 0x50487609; + CHECKREG p5, 0x3005900B; + CHECKREG sp, 0x2A0C660D; + CHECKREG fp, 0x50487609; + + imm32 p1, 0xd4023053; + imm32 p2, 0x2f041405; + imm32 p3, 0x60f61507; + imm32 p4, 0xd0487f09; + imm32 p5, 0x300b900b; + imm32 sp, 0x2a0cd60d; + imm32 fp, 0xd90e189f; + IF !CC P4 = P3; + IF !CC P5 = FP; + CC = ! CC; + IF !CC SP = P1; + IF !CC FP = P2; + IF !CC P3 = SP; + IF !CC P1 = P5; + IF !CC P2 = P4; + CC = ! CC; + IF !CC P3 = P2; + CHECKREG p1, 0xD4023053; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x2F041405; + CHECKREG p4, 0x60F61507; + CHECKREG p5, 0xD90E189F; + CHECKREG sp, 0x2A0CD60D; + CHECKREG fp, 0xD90E189F; + + imm32 p1, 0xd8021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x65b61507; + imm32 p4, 0x59487609; + imm32 p5, 0x3005900b; + imm32 sp, 0x2abc660d; + imm32 fp, 0xd90e108f; + IF !CC P3 = P2; + IF !CC P1 = P3; + CC = ! CC; + IF !CC P2 = P5; + IF !CC P3 = FP; + IF !CC P4 = P1; + IF !CC P5 = P4; + IF !CC SP = FP; + CC = ! CC; + IF !CC FP = SP; + CHECKREG p1, 0x2F041405; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x2F041405; + CHECKREG p4, 0x59487609; + CHECKREG p5, 0x3005900B; + CHECKREG sp, 0x2ABC660D; + CHECKREG fp, 0x2ABC660D; + + imm32 p1, 0xdb021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x64b61507; + imm32 p4, 0x50487609; + imm32 p5, 0x30f5900b; + imm32 sp, 0x2a4c660d; + imm32 fp, 0x895e108f; + IF !CC P4 = P3; + IF !CC P5 = FP; + IF !CC SP = P2; + IF !CC FP = SP; + CC = ! CC; + IF !CC P3 = P1; + IF !CC P1 = P2; + CC = ! CC; + IF !CC P2 = P3; + IF !CC P3 = P4; + CHECKREG p1, 0xDB021053; + CHECKREG p2, 0x64B61507; + CHECKREG p3, 0x64B61507; + CHECKREG p4, 0x64B61507; + CHECKREG p5, 0x895E108F; + CHECKREG sp, 0x2F041405; + CHECKREG fp, 0x2F041405; + + pass diff --git a/sim/testsuite/bfin/c_comp3op_dr_and_dr.s b/sim/testsuite/bfin/c_comp3op_dr_and_dr.s new file mode 100644 index 0000000..567187b --- /dev/null +++ b/sim/testsuite/bfin/c_comp3op_dr_and_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_and_dr/c_comp3op_dr_and_dr.dsp +// Spec Reference: comp3op dregs & dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 & R0; +R1 = R0 & R1; +R2 = R0 & R2; +R3 = R0 & R3; +R4 = R0 & R4; +R5 = R0 & R5; +R6 = R0 & R6; +R7 = R0 & R7; +CHECKREG r0, 0x01234567; +CHECKREG r1, 0x01234567; +CHECKREG r2, 0x00200024; +CHECKREG r3, 0x00200024; +CHECKREG r4, 0x01014001; +CHECKREG r5, 0x00010145; +CHECKREG r6, 0x00224422; +CHECKREG r7, 0x00204460; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 & R0; +R1 = R1 & R1; +R2 = R1 & R2; +R3 = R1 & R3; +R4 = R1 & R4; +R5 = R1 & R5; +R6 = R1 & R6; +R7 = R1 & R7; +CHECKREG r0, 0x01231567; +CHECKREG r1, 0x89AB1DEF; +CHECKREG r2, 0x002818AC; +CHECKREG r3, 0x88A01024; +CHECKREG r4, 0x01011889; +CHECKREG r5, 0x08811145; +CHECKREG r6, 0x88221422; +CHECKREG r7, 0x00201468; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 & R0; +R1 = R2 & R1; +R2 = R2 & R2; +R3 = R2 & R3; +R4 = R2 & R4; +R5 = R2 & R5; +R6 = R2 & R6; +R7 = R2 & R7; +CHECKREG r0, 0x00200024; +CHECKREG r1, 0x0028882C; +CHECKREG r2, 0x56789A2C; +CHECKREG r3, 0x56701224; +CHECKREG r4, 0x02400828; +CHECKREG r5, 0x50100224; +CHECKREG r6, 0x10701020; +CHECKREG r7, 0x12301228; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 & R0; +R1 = R3 & R1; +R2 = R3 & R2; +R3 = R3 & R3; +R4 = R3 & R4; +R5 = R3 & R5; +R6 = R3 & R6; +R7 = R3 & R7; +CHECKREG r0, 0x00200023; +CHECKREG r1, 0x88A00023; +CHECKREG r2, 0x56701233; +CHECKREG r3, 0xDEF01233; +CHECKREG r4, 0x02400013; +CHECKREG r5, 0x58900203; +CHECKREG r6, 0x98701033; +CHECKREG r7, 0x12301233; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 & R0; +R1 = R4 & R1; +R2 = R4 & R2; +R3 = R4 & R3; +R4 = R4 & R4; +R5 = R4 & R5; +R6 = R4 & R6; +R7 = R4 & R7; +CHECKREG r0, 0x41014001; +CHECKREG r1, 0x41014889; +CHECKREG r2, 0x42400898; +CHECKREG r3, 0x42400010; +CHECKREG r4, 0x43456899; +CHECKREG r5, 0x40012001; +CHECKREG r6, 0x40444010; +CHECKREG r7, 0x42044018; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 & R0; +R1 = R5 & R1; +R2 = R5 & R2; +R3 = R5 & R3; +R4 = R5 & R4; +R5 = R5 & R5; +R6 = R5 & R6; +R7 = R5 & R7; +CHECKREG r0, 0x05010145; +CHECKREG r1, 0x05810145; +CHECKREG r2, 0x55100204; +CHECKREG r3, 0x55900204; +CHECKREG r4, 0x25012001; +CHECKREG r5, 0x75912345; +CHECKREG r6, 0x15100000; +CHECKREG r7, 0x15100240; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 & R0; +R1 = R6 & R1; +R2 = R6 & R2; +R3 = R6 & R3; +R4 = R6 & R4; +R5 = R6 & R5; +R6 = R6 & R6; +R7 = R6 & R7; +CHECKREG r0, 0x00264422; +CHECKREG r1, 0x88264422; +CHECKREG r2, 0x10761030; +CHECKREG r3, 0x98761030; +CHECKREG r4, 0x00464010; +CHECKREG r5, 0x18160000; +CHECKREG r6, 0x98765432; +CHECKREG r7, 0x10365430; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 & R0; +R1 = R7 & R1; +R2 = R7 & R2; +R3 = R7 & R3; +R4 = R7 & R4; +R5 = R7 & R5; +R6 = R7 & R6; +R7 = R7 & R7; +CHECKREG r0, 0x00205460; +CHECKREG r1, 0x00205468; +CHECKREG r2, 0x12305238; +CHECKREG r3, 0x12305230; +CHECKREG r4, 0x02045018; +CHECKREG r5, 0x10105240; +CHECKREG r6, 0x10345430; +CHECKREG r7, 0x12345678; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 & R0; +R1 = R2 & R0; +R2 = R3 & R0; +R3 = R4 & R0; +R4 = R5 & R0; +R5 = R6 & R0; +R6 = R7 & R0; +R7 = R0 & R0; +CHECKREG r0, 0x01234567; +CHECKREG r1, 0x00000024; +CHECKREG r2, 0x00210024; +CHECKREG r3, 0x01010001; +CHECKREG r4, 0x00010145; +CHECKREG r5, 0x00224402; +CHECKREG r6, 0x00204461; +CHECKREG r7, 0x01234567; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 & R1; +R1 = R3 & R1; +R2 = R4 & R1; +R3 = R5 & R1; +R4 = R6 & R1; +R5 = R7 & R1; +R6 = R0 & R1; +R7 = R1 & R1; +CHECKREG r0, 0x002818AC; +CHECKREG r1, 0x08201024; +CHECKREG r2, 0x00001000; +CHECKREG r3, 0x08000004; +CHECKREG r4, 0x08201020; +CHECKREG r5, 0x00201020; +CHECKREG r6, 0x00201024; +CHECKREG r7, 0x08201024; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R4 & R2; +R1 = R5 & R2; +R2 = R6 & R2; +R3 = R7 & R2; +R4 = R0 & R2; +R5 = R1 & R2; +R6 = R2 & R2; +R7 = R3 & R2; +CHECKREG r0, 0x02410228; +CHECKREG r1, 0x50310224; +CHECKREG r2, 0x10731020; +CHECKREG r3, 0x10301020; +CHECKREG r4, 0x00410020; +CHECKREG r5, 0x10310020; +CHECKREG r6, 0x10731020; +CHECKREG r7, 0x10301020; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R5 & R3; +R1 = R6 & R3; +R2 = R7 & R3; +R3 = R0 & R3; +R4 = R1 & R3; +R5 = R2 & R3; +R6 = R3 & R3; +R7 = R4 & R3; +CHECKREG r0, 0x48400200; +CHECKREG r1, 0x08704030; +CHECKREG r2, 0x02304233; +CHECKREG r3, 0x48400200; +CHECKREG r4, 0x08400000; +CHECKREG r5, 0x00000200; +CHECKREG r6, 0x48400200; +CHECKREG r7, 0x08400000; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R6 & R4; +R1 = R7 & R4; +R2 = R0 & R4; +R3 = R1 & R4; +R4 = R2 & R4; +R5 = R3 & R4; +R6 = R4 & R4; +R7 = R5 & R4; +CHECKREG r0, 0x40444010; +CHECKREG r1, 0x42054018; +CHECKREG r2, 0x40444010; +CHECKREG r3, 0x42054018; +CHECKREG r4, 0x40444010; +CHECKREG r5, 0x40044010; +CHECKREG r6, 0x40444010; +CHECKREG r7, 0x40044010; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R7 & R5; +R1 = R0 & R5; +R2 = R1 & R5; +R3 = R2 & R5; +R4 = R3 & R5; +R5 = R4 & R5; +R6 = R5 & R5; +R7 = R6 & R5; +CHECKREG r0, 0x15140240; +CHECKREG r1, 0x15140240; +CHECKREG r2, 0x15140240; +CHECKREG r3, 0x15140240; +CHECKREG r4, 0x15140240; +CHECKREG r5, 0x15140240; +CHECKREG r6, 0x15140240; +CHECKREG r7, 0x15140240; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 & R6; +R1 = R0 & R6; +R2 = R1 & R6; +R3 = R2 & R6; +R4 = R3 & R6; +R5 = R4 & R6; +R6 = R5 & R6; +R7 = R6 & R6; +CHECKREG r0, 0x10365430; +CHECKREG r1, 0x10365430; +CHECKREG r2, 0x10365430; +CHECKREG r3, 0x10365430; +CHECKREG r4, 0x10365430; +CHECKREG r5, 0x10365430; +CHECKREG r6, 0x10365430; +CHECKREG r7, 0x10365430; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 & R7; +R1 = R2 & R7; +R2 = R3 & R7; +R3 = R4 & R7; +R4 = R5 & R7; +R5 = R6 & R7; +R6 = R7 & R7; +R7 = R0 & R7; +CHECKREG r0, 0x00200068; +CHECKREG r1, 0x12000208; +CHECKREG r2, 0x02300238; +CHECKREG r3, 0x00048018; +CHECKREG r4, 0x10000040; +CHECKREG r5, 0x10300400; +CHECKREG r6, 0x12348678; +CHECKREG r7, 0x00200068; + + +pass diff --git a/sim/testsuite/bfin/c_comp3op_dr_minus_dr.s b/sim/testsuite/bfin/c_comp3op_dr_minus_dr.s new file mode 100644 index 0000000..ebf2b0b --- /dev/null +++ b/sim/testsuite/bfin/c_comp3op_dr_minus_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_minus_dr/c_comp3op_dr_minus_dr.dsp +// Spec Reference: comp3op dregs - dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 - R0; +R1 = R0 - R1; +R2 = R0 - R2; +R3 = R0 - R3; +R4 = R0 - R4; +R5 = R0 - R5; +R6 = R0 - R6; +R7 = R0 - R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x76543211; +CHECKREG r2, 0xA9876544; +CHECKREG r3, 0x210FEDCC; +CHECKREG r4, 0xDCBA9767; +CHECKREG r5, 0x876EDCBB; +CHECKREG r6, 0x6789ABCE; +CHECKREG r7, 0xEDCBA988; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 - R0; +R1 = R1 - R1; +R2 = R1 - R2; +R3 = R1 - R3; +R4 = R1 - R4; +R5 = R1 - R5; +R6 = R1 - R6; +R7 = R1 - R7; +CHECKREG r0, 0x88880888; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xA987E544; +CHECKREG r3, 0x210FEDCC; +CHECKREG r4, 0xDCBAE767; +CHECKREG r5, 0x876EECBB; +CHECKREG r6, 0x6789EBCE; +CHECKREG r7, 0xEDCBE988; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 - R0; +R1 = R2 - R1; +R2 = R2 - R2; +R3 = R2 - R3; +R4 = R2 - R4; +R5 = R2 - R5; +R6 = R2 - R6; +R7 = R2 - R7; +CHECKREG r0, 0x55555505; +CHECKREG r1, 0xCCCCCCFD; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x210FEDDC; +CHECKREG r4, 0xDCBA97D7; +CHECKREG r5, 0x876EDCDB; +CHECKREG r6, 0x6789ABDE; +CHECKREG r7, 0xEDCBA9D8; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 - R0; +R1 = R3 - R1; +R2 = R3 - R2; +R3 = R3 - R3; +R4 = R3 - R4; +R5 = R3 - R5; +R6 = R3 - R6; +R7 = R3 - R7; +CHECKREG r0, 0xDDCCCCD0; +CHECKREG r1, 0x55444450; +CHECKREG r2, 0x88777780; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xDCBA976D; +CHECKREG r5, 0x876EDCBD; +CHECKREG r6, 0x6789ABCD; +CHECKREG r7, 0xEDCBA98D; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 - R0; +R1 = R4 - R1; +R2 = R4 - R2; +R3 = R4 - R3; +R4 = R4 - R4; +R5 = R4 - R5; +R6 = R4 - R6; +R7 = R4 - R7; +CHECKREG r0, 0x02222332; +CHECKREG r1, 0xF9999AAA; +CHECKREG r2, 0xFCCCCDDD; +CHECKREG r3, 0xF4555665; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0xB76EDCBB; +CHECKREG r6, 0xB789ABCE; +CHECKREG r7, 0xBDCBA988; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 - R0; +R1 = R5 - R1; +R2 = R5 - R2; +R3 = R5 - R3; +R4 = R5 - R4; +R5 = R5 - R5; +R6 = R5 - R6; +R7 = R5 - R7; +CHECKREG r0, 0x706DDDDE; +CHECKREG r1, 0xEFE55556; +CHECKREG r2, 0x20188889; +CHECKREG r3, 0x9FA11111; +CHECKREG r4, 0x504BBAAC; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x6A89ABCE; +CHECKREG r7, 0xEACBA988; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 - R0; +R1 = R6 - R1; +R2 = R6 - R2; +R3 = R6 - R3; +R4 = R6 - R4; +R5 = R6 - R5; +R6 = R6 - R6; +R7 = R6 - R7; +CHECKREG r0, 0x97500ECB; +CHECKREG r1, 0x0ECF8643; +CHECKREG r2, 0x41FFB976; +CHECKREG r3, 0xB98041FE; +CHECKREG r4, 0x752FEB99; +CHECKREG r5, 0x1FE030ED; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xEDC9A988; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 - R0; +R1 = R7 - R1; +R2 = R7 - R2; +R3 = R7 - R3; +R4 = R7 - R4; +R5 = R7 - R5; +R6 = R7 - R6; +R7 = R7 - R7; +CHECKREG r0, 0x1110E111; +CHECKREG r1, 0x8888D889; +CHECKREG r2, 0xBBBBDBBC; +CHECKREG r3, 0x3343E444; +CHECKREG r4, 0xEEEEDDDF; +CHECKREG r5, 0x99A2E333; +CHECKREG r6, 0x79BDE246; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 - R0; +R1 = R2 - R0; +R2 = R3 - R0; +R3 = R4 - R0; +R4 = R5 - R0; +R5 = R6 - R0; +R6 = R7 - R0; +R7 = R0 - R0; +CHECKREG r0, 0x70888888; +CHECKREG r1, 0xE5901234; +CHECKREG r2, 0x6E6889AC; +CHECKREG r3, 0xB2BC9011; +CHECKREG r4, 0x080898BD; +CHECKREG r5, 0x27EDCB8A; +CHECKREG r6, 0xA1ABCDE9; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 - R1; +R1 = R3 - R1; +R2 = R4 - R1; +R3 = R5 - R1; +R4 = R6 - R1; +R5 = R7 - R1; +R6 = R0 - R1; +R7 = R1 - R1; +CHECKREG r0, 0x28CCFCCD; +CHECKREG r1, 0xB474F445; +CHECKREG r2, 0x6ECD2454; +CHECKREG r3, 0xC41C2F00; +CHECKREG r4, 0xE4011DED; +CHECKREG r5, 0x5DBF21E3; +CHECKREG r6, 0x74580888; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R4 - R2; +R1 = R5 - R2; +R2 = R6 - R2; +R3 = R7 - R2; +R4 = R0 - R2; +R5 = R1 - R2; +R6 = R2 - R2; +R7 = R3 - R2; +CHECKREG r0, 0xCCD1C8FD; +CHECKREG r1, 0x21BD8909; +CHECKREG r2, 0x41FFB9F7; +CHECKREG r3, 0xD0347C31; +CHECKREG r4, 0x8AD20F06; +CHECKREG r5, 0xDFBDCF12; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x8E34C23A; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R5 - R3; +R1 = R6 - R3; +R2 = R7 - R3; +R3 = R0 - R3; +R4 = R1 - R3; +R5 = R2 - R3; +R6 = R3 - R3; +R7 = R4 - R3; +CHECKREG r0, 0x2950E111; +CHECKREG r1, 0x49841201; +CHECKREG r2, 0xC3440440; +CHECKREG r3, 0xDA609EDE; +CHECKREG r4, 0x6F237323; +CHECKREG r5, 0xE8E36562; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x94C2D445; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R6 - R4; +R1 = R7 - R4; +R2 = R0 - R4; +R3 = R1 - R4; +R4 = R2 - R4; +R5 = R3 - R4; +R6 = R4 - R4; +R7 = R5 - R4; +CHECKREG r0, 0xF510EB99; +CHECKREG r1, 0xEEEFEDDF; +CHECKREG r2, 0xA1CB8300; +CHECKREG r3, 0x9BAA8546; +CHECKREG r4, 0x4E861A67; +CHECKREG r5, 0x4D246ADF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFE9E5078; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R7 - R5; +R1 = R0 - R5; +R2 = R1 - R5; +R3 = R2 - R5; +R4 = R3 - R5; +R5 = R4 - R5; +R6 = R5 - R5; +R7 = R6 - R5; +CHECKREG r0, 0x9F9E3333; +CHECKREG r1, 0x2A080FEE; +CHECKREG r2, 0xB471ECA9; +CHECKREG r3, 0x3EDBC964; +CHECKREG r4, 0xC945A61F; +CHECKREG r5, 0x53AF82DA; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xAC507D26; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 - R6; +R1 = R0 - R6; +R2 = R1 - R6; +R3 = R2 - R6; +R4 = R3 - R6; +R5 = R4 - R6; +R6 = R5 - R6; +R7 = R6 - R6; +CHECKREG r0, 0x79C10246; +CHECKREG r1, 0xE14AAE14; +CHECKREG r2, 0x48D459E2; +CHECKREG r3, 0xB05E05B0; +CHECKREG r4, 0x17E7B17E; +CHECKREG r5, 0x7F715D4C; +CHECKREG r6, 0xE6FB091A; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 - R7; +R1 = R2 - R7; +R2 = R3 - R7; +R3 = R4 - R7; +R4 = R5 - R7; +R5 = R6 - R7; +R6 = R7 - R7; +R7 = R0 - R7; +CHECKREG r0, 0x7676F277; +CHECKREG r1, 0x4453F414; +CHECKREG r2, 0x7CC3EBC0; +CHECKREG r3, 0x16110221; +CHECKREG r4, 0x664CF1CD; +CHECKREG r5, 0x8643EE0A; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x64426BFF; + + +pass diff --git a/sim/testsuite/bfin/c_comp3op_dr_mix.s b/sim/testsuite/bfin/c_comp3op_dr_mix.s new file mode 100644 index 0000000..4920918 --- /dev/null +++ b/sim/testsuite/bfin/c_comp3op_dr_mix.s @@ -0,0 +1,237 @@ +//Original:/testcases/core/c_comp3op_dr_mix/c_comp3op_dr_mix.dsp +// Spec Reference: comp3op dregs mix +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 + R0; +R1 = R0 - R1; +R2 = R0 & R2; +R3 = R0 | R3; +R4 = R0 & R4; +R5 = R0 & R5; +R6 = R0 | R6; +R7 = R0 & R7; +CHECKREG r0, 0x02468ACE; +CHECKREG r1, 0x789ABCDF; +CHECKREG r2, 0x02408A8C; +CHECKREG r3, 0xDEF69AFE; +CHECKREG r4, 0x02440888; +CHECKREG r5, 0x00000244; +CHECKREG r6, 0x9A76DEFE; +CHECKREG r7, 0x02040248; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 + R0; +R1 = R1 - R1; +R2 = R1 & R2; +R3 = R1 | R3; +R4 = R1 & R4; +R5 = R1 & R5; +R6 = R1 | R6; +R7 = R1 & R7; +CHECKREG r0, 0x8ACE3356; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xDEF01234; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x98761432; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 + R0; +R1 = R2 - R1; +R2 = R2 & R2; +R3 = R2 | R3; +R4 = R2 & R4; +R5 = R2 & R5; +R6 = R2 | R6; +R7 = R2 & R7; +CHECKREG r0, 0x579BDF53; +CHECKREG r1, 0xCCCCCCFD; +CHECKREG r2, 0x56789A2C; +CHECKREG r3, 0xDEF89A2C; +CHECKREG r4, 0x02400828; +CHECKREG r5, 0x50100224; +CHECKREG r6, 0xDE7EDE2E; +CHECKREG r7, 0x12301228; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 + R0; +R1 = R3 - R1; +R2 = R3 & R2; +R3 = R3 | R3; +R4 = R3 & R4; +R5 = R3 - R5; +R6 = R3 | R6; +R7 = R3 & R7; +CHECKREG r0, 0xE0135796; +CHECKREG r1, 0x55444450; +CHECKREG r2, 0x56701233; +CHECKREG r3, 0xDEF01233; +CHECKREG r4, 0x02400013; +CHECKREG r5, 0x665EEEF0; +CHECKREG r6, 0xDEF65633; +CHECKREG r7, 0x12301233; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 + R0; +R1 = R4 - R1; +R2 = R4 & R2; +R3 = R4 | R3; +R4 = R4 & R4; +R5 = R4 & R5; +R6 = R4 | R6; +R7 = R4 & R7; +CHECKREG r0, 0x8468AE00; +CHECKREG r1, 0xF9999AAA; +CHECKREG r2, 0x42400898; +CHECKREG r3, 0x4FF57ABD; +CHECKREG r4, 0x43456899; +CHECKREG r5, 0x40012001; +CHECKREG r6, 0x4B777CBB; +CHECKREG r7, 0x42044018; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 + R0; +R1 = R5 - R1; +R2 = R5 & R2; +R3 = R5 | R3; +R4 = R5 & R4; +R5 = R5 & R5; +R6 = R5 | R6; +R7 = R5 & R7; +CHECKREG r0, 0x7AB468AC; +CHECKREG r1, 0xEFE55556; +CHECKREG r2, 0x55100204; +CHECKREG r3, 0xF5F13375; +CHECKREG r4, 0x25012001; +CHECKREG r5, 0x75912345; +CHECKREG r6, 0xF5F77777; +CHECKREG r7, 0x15100240; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 + R0; +R1 = R6 - R1; +R2 = R6 & R2; +R3 = R6 | R3; +R4 = R6 & R4; +R5 = R6 & R5; +R6 = R6 | R6; +R7 = R6 & R7; +CHECKREG r0, 0x999C9999; +CHECKREG r1, 0x0ECF8643; +CHECKREG r2, 0x10761030; +CHECKREG r3, 0xDEF65636; +CHECKREG r4, 0x00464010; +CHECKREG r5, 0x18160000; +CHECKREG r6, 0x98765432; +CHECKREG r7, 0x10365430; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 + R0; +R1 = R7 - R1; +R2 = R7 & R2; +R3 = R7 | R3; +R4 = R7 & R4; +R5 = R7 - R5; +R6 = R7 | R6; +R7 = R7 & R7; +CHECKREG r0, 0x1357CBDF; +CHECKREG r1, 0x8888D889; +CHECKREG r2, 0x12305238; +CHECKREG r3, 0xDEF4767C; +CHECKREG r4, 0x02045018; +CHECKREG r5, 0x99A2E333; +CHECKREG r6, 0x9A76767A; +CHECKREG r7, 0x12345678; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; + + +R0 = R1 + R2; +R1 = R3 - R2; +R2 = R4 & R3; +R3 = R5 | R4; +R4 = R6 & R7; +CHECKREG r0, 0x00060008; +CHECKREG r1, 0x00020002; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x000A000B; +CHECKREG r4, 0x000C000D; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000e000f; + + +pass diff --git a/sim/testsuite/bfin/c_comp3op_dr_or_dr.s b/sim/testsuite/bfin/c_comp3op_dr_or_dr.s new file mode 100644 index 0000000..36e6401 --- /dev/null +++ b/sim/testsuite/bfin/c_comp3op_dr_or_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_or_dr/c_comp3op_dr_or_dr.dsp +// Spec Reference: comp3op dregs | dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 | R0; +R1 = R0 | R1; +R2 = R0 | R2; +R3 = R0 | R3; +R4 = R0 | R4; +R5 = R0 | R5; +R6 = R0 | R6; +R7 = R0 | R7; +CHECKREG r0, 0x01234567; +CHECKREG r1, 0x89ABCDEF; +CHECKREG r2, 0x577BDFFF; +CHECKREG r3, 0xDFF35777; +CHECKREG r4, 0x23676DFF; +CHECKREG r5, 0x79B36767; +CHECKREG r6, 0x99775577; +CHECKREG r7, 0x1337577F; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 | R0; +R1 = R1 | R1; +R2 = R1 | R2; +R3 = R1 | R3; +R4 = R1 | R4; +R5 = R1 | R5; +R6 = R1 | R6; +R7 = R1 | R7; +CHECKREG r0, 0x89AB1DEF; +CHECKREG r1, 0x89AB1DEF; +CHECKREG r2, 0xDFFB1FFF; +CHECKREG r3, 0xDFFB1FFF; +CHECKREG r4, 0xABEF1DFF; +CHECKREG r5, 0xF9BB1FEF; +CHECKREG r6, 0x99FF1DFF; +CHECKREG r7, 0x9BBF1FFF; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 | R0; +R1 = R2 | R1; +R2 = R2 | R2; +R3 = R2 | R3; +R4 = R2 | R4; +R5 = R2 | R5; +R6 = R2 | R6; +R7 = R2 | R7; +CHECKREG r0, 0x577BDF2F; +CHECKREG r1, 0xDFFBDF2F; +CHECKREG r2, 0x56789A2C; +CHECKREG r3, 0xDEF89A2C; +CHECKREG r4, 0x777DFA2D; +CHECKREG r5, 0x7EF9BB2D; +CHECKREG r6, 0xDE7EDE2E; +CHECKREG r7, 0x567CDE2C; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 | R0; +R1 = R3 | R1; +R2 = R3 | R2; +R3 = R3 | R3; +R4 = R3 | R4; +R5 = R3 | R5; +R6 = R3 | R6; +R7 = R3 | R7; +CHECKREG r0, 0xDFF35773; +CHECKREG r1, 0xDFFBDFF3; +CHECKREG r2, 0xDEF89AB3; +CHECKREG r3, 0xDEF01233; +CHECKREG r4, 0xFFF57AB3; +CHECKREG r5, 0xFEF13373; +CHECKREG r6, 0xDEF65633; +CHECKREG r7, 0xDEF45673; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 | R0; +R1 = R4 | R1; +R2 = R4 | R2; +R3 = R4 | R3; +R4 = R4 | R4; +R5 = R4 | R5; +R6 = R4 | R6; +R7 = R4 | R7; +CHECKREG r0, 0x43676DFF; +CHECKREG r1, 0x4BEFEDFF; +CHECKREG r2, 0x477DFABD; +CHECKREG r3, 0x4FF57ABD; +CHECKREG r4, 0x43456899; +CHECKREG r5, 0x4BD56BDD; +CHECKREG r6, 0x4B777CBB; +CHECKREG r7, 0x43757EF9; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 | R0; +R1 = R5 | R1; +R2 = R5 | R2; +R3 = R5 | R3; +R4 = R5 | R4; +R5 = R5 | R5; +R6 = R5 | R6; +R7 = R5 | R7; +CHECKREG r0, 0x75B36767; +CHECKREG r1, 0xF5BBEFEF; +CHECKREG r2, 0x75F9BBFD; +CHECKREG r3, 0xF5F13375; +CHECKREG r4, 0x75D56BDD; +CHECKREG r5, 0x75912345; +CHECKREG r6, 0xF5F77777; +CHECKREG r7, 0x75B5777D; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 | R0; +R1 = R6 | R1; +R2 = R6 | R2; +R3 = R6 | R3; +R4 = R6 | R4; +R5 = R6 | R5; +R6 = R6 | R6; +R7 = R6 | R7; +CHECKREG r0, 0x99765577; +CHECKREG r1, 0x99F6DDFF; +CHECKREG r2, 0xDE76DEBE; +CHECKREG r3, 0xDEF65636; +CHECKREG r4, 0xBB767CBB; +CHECKREG r5, 0xF8F67777; +CHECKREG r6, 0x98765432; +CHECKREG r7, 0x9A76567A; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 | R0; +R1 = R7 | R1; +R2 = R7 | R2; +R3 = R7 | R3; +R4 = R7 | R4; +R5 = R7 | R5; +R6 = R7 | R6; +R7 = R7 | R7; +CHECKREG r0, 0x1337777F; +CHECKREG r1, 0x9BBF7FFF; +CHECKREG r2, 0x567C7EFC; +CHECKREG r3, 0xDEF4767C; +CHECKREG r4, 0x33757EF9; +CHECKREG r5, 0x7AB5777D; +CHECKREG r6, 0x9A76767A; +CHECKREG r7, 0x12345678; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 | R0; +R1 = R2 | R0; +R2 = R3 | R0; +R3 = R4 | R0; +R4 = R5 | R0; +R5 = R6 | R0; +R6 = R7 | R0; +R7 = R0 | R0; +CHECKREG r0, 0x91ABCDEF; +CHECKREG r1, 0xD7BBDFFF; +CHECKREG r2, 0xDFFBDFFF; +CHECKREG r3, 0xB3EFDDFF; +CHECKREG r4, 0xF9BBEDEF; +CHECKREG r5, 0x99FFDDFF; +CHECKREG r6, 0x93BFDFFF; +CHECKREG r7, 0x91ABCDEF; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 | R1; +R1 = R3 | R1; +R2 = R4 | R1; +R3 = R5 | R1; +R4 = R6 | R1; +R5 = R7 | R1; +R6 = R0 | R1; +R7 = R1 | R1; +CHECKREG r0, 0x7BFB1FFF; +CHECKREG r1, 0xFFAB1FFF; +CHECKREG r2, 0xFFEB1FFF; +CHECKREG r3, 0xFFBB3FFF; +CHECKREG r4, 0xFFFF1FFF; +CHECKREG r5, 0xFFBF1FFF; +CHECKREG r6, 0xFFFB1FFF; +CHECKREG r7, 0xFFAB1FFF; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R4 | R2; +R1 = R5 | R2; +R2 = R6 | R2; +R3 = R7 | R2; +R4 = R0 | R2; +R5 = R1 | R2; +R6 = R2 | R2; +R7 = R3 | R2; +CHECKREG r0, 0x7777FB2D; +CHECKREG r1, 0x7E73BB3D; +CHECKREG r2, 0xDE73DE2F; +CHECKREG r3, 0xDE77FE2F; +CHECKREG r4, 0xFF77FF2F; +CHECKREG r5, 0xFE73FF3F; +CHECKREG r6, 0xDE73DE2F; +CHECKREG r7, 0xDE77FE2F; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R5 | R3; +R1 = R6 | R3; +R2 = R7 | R3; +R3 = R0 | R3; +R4 = R1 | R3; +R5 = R2 | R3; +R6 = R3 | R3; +R7 = R4 | R3; +CHECKREG r0, 0x7EF16377; +CHECKREG r1, 0xDEF45637; +CHECKREG r2, 0x5EF44673; +CHECKREG r3, 0x7EF16377; +CHECKREG r4, 0xFEF57777; +CHECKREG r5, 0x7EF56777; +CHECKREG r6, 0x7EF16377; +CHECKREG r7, 0xFEF57777; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R6 | R4; +R1 = R7 | R4; +R2 = R0 | R4; +R3 = R1 | R4; +R4 = R2 | R4; +R5 = R3 | R4; +R6 = R4 | R4; +R7 = R5 | R4; +CHECKREG r0, 0x5B577CBB; +CHECKREG r1, 0x53757EF9; +CHECKREG r2, 0x5B577CBB; +CHECKREG r3, 0x53757EF9; +CHECKREG r4, 0x5B577CBB; +CHECKREG r5, 0x5B777EFB; +CHECKREG r6, 0x5B577CBB; +CHECKREG r7, 0x5B777EFB; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R7 | R5; +R1 = R0 | R5; +R2 = R1 | R5; +R3 = R2 | R5; +R4 = R3 | R5; +R5 = R4 | R5; +R6 = R5 | R5; +R7 = R6 | R5; +CHECKREG r0, 0x75B6777D; +CHECKREG r1, 0x75B6777D; +CHECKREG r2, 0x75B6777D; +CHECKREG r3, 0x75B6777D; +CHECKREG r4, 0x75B6777D; +CHECKREG r5, 0x75B6777D; +CHECKREG r6, 0x75B6777D; +CHECKREG r7, 0x75B6777D; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 | R6; +R1 = R0 | R6; +R2 = R1 | R6; +R3 = R2 | R6; +R4 = R3 | R6; +R5 = R4 | R6; +R6 = R5 | R6; +R7 = R6 | R6; +CHECKREG r0, 0x9A77567A; +CHECKREG r1, 0x9A77567A; +CHECKREG r2, 0x9A77567A; +CHECKREG r3, 0x9A77567A; +CHECKREG r4, 0x9A77567A; +CHECKREG r5, 0x9A77567A; +CHECKREG r6, 0x9A77567A; +CHECKREG r7, 0x9A77567A; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 | R7; +R1 = R2 | R7; +R2 = R3 | R7; +R3 = R4 | R7; +R4 = R5 | R7; +R5 = R6 | R7; +R6 = R7 | R7; +R7 = R0 | R7; +CHECKREG r0, 0x9ABFFEFF; +CHECKREG r1, 0x56BCFEFC; +CHECKREG r2, 0x9EFCF678; +CHECKREG r3, 0x3A758EF9; +CHECKREG r4, 0x7AB5FE7D; +CHECKREG r5, 0x9A7CF6FA; +CHECKREG r6, 0x12348678; +CHECKREG r7, 0x9ABFFEFF; + + +pass diff --git a/sim/testsuite/bfin/c_comp3op_dr_plus_dr.s b/sim/testsuite/bfin/c_comp3op_dr_plus_dr.s new file mode 100644 index 0000000..fff4cb7 --- /dev/null +++ b/sim/testsuite/bfin/c_comp3op_dr_plus_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_plus_dr/c_comp3op_dr_plus_dr.dsp +// Spec Reference: comp3op dregs + dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 + R0; +R1 = R0 + R1; +R2 = R0 + R2; +R3 = R0 + R3; +R4 = R0 + R4; +R5 = R0 + R5; +R6 = R0 + R6; +R7 = R0 + R7; +CHECKREG r0, 0x02468ACE; +CHECKREG r1, 0x8BF258BD; +CHECKREG r2, 0x58BF258A; +CHECKREG r3, 0xE1369D02; +CHECKREG r4, 0x258BF367; +CHECKREG r5, 0x7AD7AE13; +CHECKREG r6, 0x9ABCDF00; +CHECKREG r7, 0x147AE146; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 + R0; +R1 = R1 + R1; +R2 = R1 + R2; +R3 = R1 + R3; +R4 = R1 + R4; +R5 = R1 + R5; +R6 = R1 + R6; +R7 = R1 + R7; +CHECKREG r0, 0x8ACE3356; +CHECKREG r1, 0x13563BDE; +CHECKREG r2, 0x69CE569A; +CHECKREG r3, 0xF2464E12; +CHECKREG r4, 0x369B5477; +CHECKREG r5, 0x8BE74F23; +CHECKREG r6, 0xABCC5010; +CHECKREG r7, 0x258A5256; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 + R0; +R1 = R2 + R1; +R2 = R2 + R2; +R3 = R2 + R3; +R4 = R2 + R4; +R5 = R2 + R5; +R6 = R2 + R6; +R7 = R2 + R7; +CHECKREG r0, 0x579BDF53; +CHECKREG r1, 0xE024675B; +CHECKREG r2, 0xACF13458; +CHECKREG r3, 0x8BE1467C; +CHECKREG r4, 0xD0369C81; +CHECKREG r5, 0x2582577D; +CHECKREG r6, 0x4567887A; +CHECKREG r7, 0xBF258A80; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 + R0; +R1 = R3 + R1; +R2 = R3 + R2; +R3 = R3 + R3; +R4 = R3 + R4; +R5 = R3 + R5; +R6 = R3 + R6; +R7 = R3 + R7; +CHECKREG r0, 0xE0135796; +CHECKREG r1, 0x689BE016; +CHECKREG r2, 0x3568ACE6; +CHECKREG r3, 0xBDE02466; +CHECKREG r4, 0xE1258CF9; +CHECKREG r5, 0x367147A9; +CHECKREG r6, 0x56567899; +CHECKREG r7, 0xD0147AD9; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 + R0; +R1 = R4 + R1; +R2 = R4 + R2; +R3 = R4 + R3; +R4 = R4 + R4; +R5 = R4 + R5; +R6 = R4 + R6; +R7 = R4 + R7; +CHECKREG r0, 0x8468AE00; +CHECKREG r1, 0x8CF13688; +CHECKREG r2, 0x89BE0355; +CHECKREG r3, 0x92357ACD; +CHECKREG r4, 0x868AD132; +CHECKREG r5, 0xCF1BF477; +CHECKREG r6, 0xCF012564; +CHECKREG r7, 0xC8BF27AA; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 + R0; +R1 = R5 + R1; +R2 = R5 + R2; +R3 = R5 + R3; +R4 = R5 + R4; +R5 = R5 + R5; +R6 = R5 + R6; +R7 = R5 + R7; +CHECKREG r0, 0x7AB468AC; +CHECKREG r1, 0xFB3CF134; +CHECKREG r2, 0xCB09BE01; +CHECKREG r3, 0x4B813579; +CHECKREG r4, 0x9AD68BDE; +CHECKREG r5, 0xEB22468A; +CHECKREG r6, 0x80989ABC; +CHECKREG r7, 0x00569D02; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 + R0; +R1 = R6 + R1; +R2 = R6 + R2; +R3 = R6 + R3; +R4 = R6 + R4; +R5 = R6 + R5; +R6 = R6 + R6; +R7 = R6 + R7; +CHECKREG r0, 0x999C9999; +CHECKREG r1, 0x221D2221; +CHECKREG r2, 0xEEECEEEE; +CHECKREG r3, 0x776C6666; +CHECKREG r4, 0xBBBCBCCB; +CHECKREG r5, 0x110C7777; +CHECKREG r6, 0x30ECA864; +CHECKREG r7, 0x4322FEDC; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 + R0; +R1 = R7 + R1; +R2 = R7 + R2; +R3 = R7 + R3; +R4 = R7 + R4; +R5 = R7 + R5; +R6 = R7 + R6; +R7 = R7 + R7; +CHECKREG r0, 0x1357CBDF; +CHECKREG r1, 0x9BDFD467; +CHECKREG r2, 0x68ACD134; +CHECKREG r3, 0xF124C8AC; +CHECKREG r4, 0x3579CF11; +CHECKREG r5, 0x8AC5C9BD; +CHECKREG r6, 0xAAAACAAA; +CHECKREG r7, 0x2468ACF0; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 + R0; +R1 = R2 + R0; +R2 = R3 + R0; +R3 = R4 + R0; +R4 = R5 + R0; +R5 = R6 + R0; +R6 = R7 + R0; +R7 = R0 + R0; +CHECKREG r0, 0x92CF1356; +CHECKREG r1, 0xE8E7AE12; +CHECKREG r2, 0x71C0258A; +CHECKREG r3, 0xB6142BEF; +CHECKREG r4, 0x0B60349B; +CHECKREG r5, 0x2B456768; +CHECKREG r6, 0xA50369C7; +CHECKREG r7, 0x259E26AC; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 + R1; +R1 = R3 + R1; +R2 = R4 + R1; +R3 = R5 + R1; +R4 = R6 + R1; +R5 = R7 + R1; +R6 = R0 + R1; +R7 = R1 + R1; +CHECKREG r0, 0x7C2338AB; +CHECKREG r1, 0x07CB3023; +CHECKREG r2, 0x2B0D48BC; +CHECKREG r3, 0x805C5368; +CHECKREG r4, 0xA0414255; +CHECKREG r5, 0x19FF464B; +CHECKREG r6, 0x83EE68CE; +CHECKREG r7, 0x0F966046; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R3 + R2; +R1 = R4 + R2; +R2 = R5 + R2; +R3 = R6 + R2; +R4 = R7 + R2; +R5 = R0 + R2; +R6 = R1 + R2; +R7 = R2 + R2; +CHECKREG r0, 0x9563CC50; +CHECKREG r1, 0x79B8FD55; +CHECKREG r2, 0xCEA4BD61; +CHECKREG r3, 0x67181184; +CHECKREG r4, 0xE0D8F389; +CHECKREG r5, 0x640889B1; +CHECKREG r6, 0x485DBAB6; +CHECKREG r7, 0x9D497AC2; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R4 + R3; +R1 = R5 + R3; +R2 = R6 + R3; +R3 = R7 + R3; +R4 = R0 + R3; +R5 = R1 + R3; +R6 = R2 + R3; +R7 = R3 + R3; +CHECKREG r0, 0x7335A6C6; +CHECKREG r1, 0xC7316577; +CHECKREG r2, 0xE7649667; +CHECKREG r3, 0x612488A6; +CHECKREG r4, 0xD45A2F6C; +CHECKREG r5, 0x2855EE1D; +CHECKREG r6, 0x48891F0D; +CHECKREG r7, 0xC249114C; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R5 + R4; +R1 = R6 + R4; +R2 = R7 + R4; +R3 = R0 + R4; +R4 = R1 + R4; +R5 = R2 + R4; +R6 = R3 + R4; +R7 = R4 + R4; +CHECKREG r0, 0x98D68BDE; +CHECKREG r1, 0x9B9BBCCB; +CHECKREG r2, 0x957ABF11; +CHECKREG r3, 0xEC1BF477; +CHECKREG r4, 0xEEE12564; +CHECKREG r5, 0x845BE475; +CHECKREG r6, 0xDAFD19DB; +CHECKREG r7, 0xDDC24AC8; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R6 + R5; +R1 = R7 + R5; +R2 = R0 + R5; +R3 = R1 + R5; +R4 = R2 + R5; +R5 = R3 + R5; +R6 = R4 + R5; +R7 = R5 + R5; +CHECKREG r0, 0x0B0C8777; +CHECKREG r1, 0x8ACA79BD; +CHECKREG r2, 0x80A2AABC; +CHECKREG r3, 0x00609D02; +CHECKREG r4, 0xF638CE01; +CHECKREG r5, 0x75F6C047; +CHECKREG r6, 0x6C2F8E48; +CHECKREG r7, 0xEBED808E; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 + R6; +R1 = R0 + R6; +R2 = R1 + R6; +R3 = R2 + R6; +R4 = R3 + R6; +R5 = R4 + R6; +R6 = R5 + R6; +R7 = R6 + R6; +CHECKREG r0, 0xAAADAAAA; +CHECKREG r1, 0x4323FEDC; +CHECKREG r2, 0xDB9A530E; +CHECKREG r3, 0x7410A740; +CHECKREG r4, 0x0C86FB72; +CHECKREG r5, 0xA4FD4FA4; +CHECKREG r6, 0x3D73A3D6; +CHECKREG r7, 0x7AE747AC; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 + R7; +R1 = R2 + R7; +R2 = R3 + R7; +R3 = R4 + R7; +R4 = R5 + R7; +R5 = R6 + R7; +R6 = R7 + R7; +R7 = R0 + R7; +CHECKREG r0, 0x9ADFFF67; +CHECKREG r1, 0x68BD0104; +CHECKREG r2, 0xA12CF8B0; +CHECKREG r3, 0x3A7A0F11; +CHECKREG r4, 0x8AB5FEBD; +CHECKREG r5, 0xAAACFAFA; +CHECKREG r6, 0x24690CF0; +CHECKREG r7, 0xAD1485DF; + + +pass diff --git a/sim/testsuite/bfin/c_comp3op_dr_xor_dr.s b/sim/testsuite/bfin/c_comp3op_dr_xor_dr.s new file mode 100644 index 0000000..fa0db63 --- /dev/null +++ b/sim/testsuite/bfin/c_comp3op_dr_xor_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_xor_dr/c_comp3op_dr_xor_dr.dsp +// Spec Reference: comp3op dregs xor dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 ^ R0; +R1 = R0 ^ R1; +R2 = R0 ^ R2; +R3 = R0 ^ R3; +R4 = R0 ^ R4; +R5 = R0 ^ R5; +R6 = R0 ^ R6; +R7 = R0 ^ R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x89ABCDEF; +CHECKREG r2, 0x56789ABC; +CHECKREG r3, 0xDEF01234; +CHECKREG r4, 0x23456899; +CHECKREG r5, 0x78912345; +CHECKREG r6, 0x98765432; +CHECKREG r7, 0x12345678; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 ^ R0; +R1 = R1 ^ R1; +R2 = R1 ^ R2; +R3 = R1 ^ R3; +R4 = R1 ^ R4; +R5 = R1 ^ R5; +R6 = R1 ^ R6; +R7 = R1 ^ R7; +CHECKREG r0, 0x88880888; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x56781ABC; +CHECKREG r3, 0xDEF01234; +CHECKREG r4, 0x23451899; +CHECKREG r5, 0x78911345; +CHECKREG r6, 0x98761432; +CHECKREG r7, 0x12341678; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 ^ R0; +R1 = R2 ^ R1; +R2 = R2 ^ R2; +R3 = R2 ^ R3; +R4 = R2 ^ R4; +R5 = R2 ^ R5; +R6 = R2 ^ R6; +R7 = R2 ^ R7; +CHECKREG r0, 0x575BDF0B; +CHECKREG r1, 0xDFD35703; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xDEF01224; +CHECKREG r4, 0x23456829; +CHECKREG r5, 0x78912325; +CHECKREG r6, 0x98765422; +CHECKREG r7, 0x12345628; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 ^ R0; +R1 = R3 ^ R1; +R2 = R3 ^ R2; +R3 = R3 ^ R3; +R4 = R3 ^ R4; +R5 = R3 ^ R5; +R6 = R3 ^ R6; +R7 = R3 ^ R7; +CHECKREG r0, 0xDFD35750; +CHECKREG r1, 0x575BDFD0; +CHECKREG r2, 0x88888880; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x23456893; +CHECKREG r5, 0x78912343; +CHECKREG r6, 0x98765433; +CHECKREG r7, 0x12345673; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 ^ R0; +R1 = R4 ^ R1; +R2 = R4 ^ R2; +R3 = R4 ^ R3; +R4 = R4 ^ R4; +R5 = R4 ^ R5; +R6 = R4 ^ R6; +R7 = R4 ^ R7; +CHECKREG r0, 0x02662DFE; +CHECKREG r1, 0x0AEEA576; +CHECKREG r2, 0x053DF225; +CHECKREG r3, 0x0DB57AAD; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x48912345; +CHECKREG r6, 0x48765432; +CHECKREG r7, 0x42345678; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 ^ R0; +R1 = R5 ^ R1; +R2 = R5 ^ R2; +R3 = R5 ^ R3; +R4 = R5 ^ R4; +R5 = R5 ^ R5; +R6 = R5 ^ R6; +R7 = R5 ^ R7; +CHECKREG r0, 0x70B26622; +CHECKREG r1, 0xF03AEEAA; +CHECKREG r2, 0x20E9B9F9; +CHECKREG r3, 0xA0613171; +CHECKREG r4, 0x50D44BDC; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x95765432; +CHECKREG r7, 0x15345678; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 ^ R0; +R1 = R6 ^ R1; +R2 = R6 ^ R2; +R3 = R6 ^ R3; +R4 = R6 ^ R4; +R5 = R6 ^ R5; +R6 = R6 ^ R6; +R7 = R6 ^ R7; +CHECKREG r0, 0x99501155; +CHECKREG r1, 0x11D099DD; +CHECKREG r2, 0xCE00CE8E; +CHECKREG r3, 0x46804606; +CHECKREG r4, 0xBB303CAB; +CHECKREG r5, 0xE0E07777; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x12365678; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 ^ R0; +R1 = R7 ^ R1; +R2 = R7 ^ R2; +R3 = R7 ^ R3; +R4 = R7 ^ R4; +R5 = R7 ^ R5; +R6 = R7 ^ R6; +R7 = R7 ^ R7; +CHECKREG r0, 0x1317231F; +CHECKREG r1, 0x9B9F2B97; +CHECKREG r2, 0x444C2CC4; +CHECKREG r3, 0xCCC4244C; +CHECKREG r4, 0x31712EE1; +CHECKREG r5, 0x6AA5253D; +CHECKREG r6, 0x8A42224A; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 ^ R0; +R1 = R2 ^ R0; +R2 = R3 ^ R0; +R3 = R4 ^ R0; +R4 = R5 ^ R0; +R5 = R6 ^ R0; +R6 = R7 ^ R0; +R7 = R0 ^ R0; +CHECKREG r0, 0x90888888; +CHECKREG r1, 0xC6901234; +CHECKREG r2, 0x4E799ABC; +CHECKREG r3, 0xB3CD9011; +CHECKREG r4, 0xE819A9CD; +CHECKREG r5, 0x08FEDC9A; +CHECKREG r6, 0x82BCDEF9; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 ^ R1; +R1 = R3 ^ R1; +R2 = R4 ^ R1; +R3 = R5 ^ R1; +R4 = R6 ^ R1; +R5 = R7 ^ R1; +R6 = R0 ^ R1; +R7 = R1 ^ R1; +CHECKREG r0, 0x7BD30753; +CHECKREG r1, 0xF78B0FDB; +CHECKREG r2, 0xD4C91742; +CHECKREG r3, 0x8F1A2C9E; +CHECKREG r4, 0x6FFD1DE9; +CHECKREG r5, 0xE5BF19F3; +CHECKREG r6, 0x8C580888; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R4 ^ R2; +R1 = R5 ^ R2; +R2 = R6 ^ R2; +R3 = R7 ^ R2; +R4 = R0 ^ R2; +R5 = R1 ^ R2; +R6 = R2 ^ R2; +R7 = R3 ^ R2; +CHECKREG r0, 0x7536F905; +CHECKREG r1, 0x2E42B919; +CHECKREG r2, 0xCE00CE0F; +CHECKREG r3, 0xDC34F827; +CHECKREG r4, 0xBB36370A; +CHECKREG r5, 0xE0427716; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x12343628; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R5 ^ R3; +R1 = R6 ^ R3; +R2 = R7 ^ R3; +R3 = R0 ^ R3; +R4 = R1 ^ R3; +R5 = R2 ^ R3; +R6 = R3 ^ R3; +R7 = R4 ^ R3; +CHECKREG r0, 0x36B16177; +CHECKREG r1, 0xD6841607; +CHECKREG r2, 0x5CC40440; +CHECKREG r3, 0x78412344; +CHECKREG r4, 0xAEC53543; +CHECKREG r5, 0x24852704; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xD6841607; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R6 ^ R4; +R1 = R7 ^ R4; +R2 = R0 ^ R4; +R3 = R1 ^ R4; +R4 = R2 ^ R4; +R5 = R3 ^ R4; +R6 = R4 ^ R4; +R7 = R5 ^ R4; +CHECKREG r0, 0x1B133CAB; +CHECKREG r1, 0x11703EE1; +CHECKREG r2, 0x48565432; +CHECKREG r3, 0x42355678; +CHECKREG r4, 0x1B133CAB; +CHECKREG r5, 0x59266AD3; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x42355678; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R7 ^ R5; +R1 = R0 ^ R5; +R2 = R1 ^ R5; +R3 = R2 ^ R5; +R4 = R3 ^ R5; +R5 = R4 ^ R5; +R6 = R5 ^ R5; +R7 = R6 ^ R5; +CHECKREG r0, 0x60A2753D; +CHECKREG r1, 0x15345678; +CHECKREG r2, 0x60A2753D; +CHECKREG r3, 0x15345678; +CHECKREG r4, 0x60A2753D; +CHECKREG r5, 0x15345678; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x15345678; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 ^ R6; +R1 = R0 ^ R6; +R2 = R1 ^ R6; +R3 = R2 ^ R6; +R4 = R3 ^ R6; +R5 = R4 ^ R6; +R6 = R5 ^ R6; +R7 = R6 ^ R6; +CHECKREG r0, 0x8A41024A; +CHECKREG r1, 0x12375678; +CHECKREG r2, 0x8A41024A; +CHECKREG r3, 0x12375678; +CHECKREG r4, 0x8A41024A; +CHECKREG r5, 0x12375678; +CHECKREG r6, 0x8A41024A; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 ^ R7; +R1 = R2 ^ R7; +R2 = R3 ^ R7; +R3 = R4 ^ R7; +R4 = R5 ^ R7; +R5 = R6 ^ R7; +R6 = R7 ^ R7; +R7 = R0 ^ R7; +CHECKREG r0, 0x9A9FFE97; +CHECKREG r1, 0x44BCFCF4; +CHECKREG r2, 0x9CCCF440; +CHECKREG r3, 0x3A710EE1; +CHECKREG r4, 0x6AB5FE3D; +CHECKREG r5, 0x8A4CF2FA; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x88AB78EF; + + +pass diff --git a/sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh1.s b/sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh1.s new file mode 100644 index 0000000..f570a5f --- /dev/null +++ b/sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh1.s @@ -0,0 +1,302 @@ +//Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh1/c_comp3op_pr_plus_pr_sh1.dsp +// Spec Reference: comp3op pregs + pregs << 1 +# mach: bfin + +.include "testutils.inc" + start + + imm32 p1, 0x89ab1def; + imm32 p2, 0x56781abc; + imm32 p3, 0xdef01234; + imm32 p4, 0x23451899; + imm32 p5, 0x78911345; + imm32 sp, 0x98761432; + imm32 fp, 0x12341678; + P1 = P1 + ( P1 << 1 ); + P2 = P1 + ( P2 << 1 ); + P3 = P1 + ( P3 << 1 ); + P4 = P1 + ( P4 << 1 ); + P5 = P1 + ( P5 << 1 ); + SP = P1 + ( SP << 1 ); + FP = P1 + FP; + CHECKREG p1, 0x9D0159CD; + CHECKREG p2, 0x49F18F45; + CHECKREG p3, 0x5AE17E35; + CHECKREG p4, 0xE38B8AFF; + CHECKREG p5, 0x8E238057; + CHECKREG sp, 0xCDED8231; + CHECKREG fp, 0xAF357045; + + imm32 p1, 0x89abcd2f; + imm32 p2, 0x56789a2c; + imm32 p3, 0xdef01224; + imm32 p4, 0x23456829; + imm32 p5, 0x78912325; + imm32 sp, 0x98765422; + imm32 fp, 0x12345628; + P1 = P2 + ( P1 << 1 ); + P2 = P2 + ( P2 << 1 ); + P3 = P2 + ( P3 << 1 ); + P4 = P2 + ( P4 << 1 ); + P5 = P2 + ( P5 << 1 ); + SP = P2 + ( SP << 1 ); + FP = P2 + ( FP << 1 ); + CHECKREG p1, 0x69D0348A; + CHECKREG p2, 0x0369CE84; + CHECKREG p3, 0xC149F2CC; + CHECKREG p4, 0x49F49ED6; + CHECKREG p5, 0xF48C14CE; + CHECKREG sp, 0x345676C8; + CHECKREG fp, 0x27D27AD4; + + imm32 p1, 0x89abcde3; + imm32 p2, 0x56789ab3; + imm32 p3, 0xdef01233; + imm32 p4, 0x23456893; + imm32 p5, 0x78912343; + imm32 sp, 0x98765433; + imm32 fp, 0x12345673; + P1 = P3 + ( P1 << 1 ); + P2 = P3 + ( P2 << 1 ); + P3 = P3 + ( P3 << 1 ); + P4 = P3 + ( P4 << 1 ); + P5 = P3 + ( P5 << 1 ); + SP = P3 + ( SP << 1 ); + FP = P3 + ( FP << 1 ); + CHECKREG p1, 0xF247ADF9; + CHECKREG p2, 0x8BE14799; + CHECKREG p3, 0x9CD03699; + CHECKREG p4, 0xE35B07BF; + CHECKREG p5, 0x8DF27D1F; + CHECKREG sp, 0xCDBCDEFF; + CHECKREG fp, 0xC138E37F; + + imm32 p1, 0x49abcdef; + imm32 p2, 0x46789abc; + imm32 p3, 0x4ef01234; + imm32 p4, 0x43456899; + imm32 p5, 0x48912345; + imm32 sp, 0x48765432; + imm32 fp, 0x42345678; + P1 = P4 + ( P1 << 1 ); + P2 = P4 + ( P2 << 1 ); + P3 = P4 + ( P3 << 1 ); + P4 = P4 + ( P4 << 1 ); + P5 = P4 + ( P5 << 1 ); + SP = P4 + ( SP << 1 ); + FP = P4 + ( FP << 1 ); + CHECKREG p1, 0xD69D0477; + CHECKREG p2, 0xD0369E11; + CHECKREG p3, 0xE1258D01; + CHECKREG p4, 0xC9D039CB; + CHECKREG p5, 0x5AF28055; + CHECKREG sp, 0x5ABCE22F; + CHECKREG fp, 0x4E38E6BB; + + imm32 p1, 0x85abcdef; + imm32 p2, 0x55789abc; + imm32 p3, 0xd5f01234; + imm32 p4, 0x25456899; + imm32 p5, 0x75912345; + imm32 sp, 0x95765432; + imm32 fp, 0x15345678; + P1 = P5 + ( P1 << 1 ); + P2 = P5 + ( P2 << 1 ); + P3 = P5 + ( P3 << 1 ); + P4 = P5 + ( P4 << 1 ); + P5 = P5 + ( P5 << 1 ); + SP = P5 + ( SP << 1 ); + FP = P5 + ( FP << 1 ); + CHECKREG p1, 0x80E8BF23; + CHECKREG p2, 0x208258BD; + CHECKREG p3, 0x217147AD; + CHECKREG p4, 0xC01BF477; + CHECKREG p5, 0x60B369CF; + CHECKREG sp, 0x8BA01233; + CHECKREG fp, 0x8B1C16BF; + + imm32 p1, 0x89a6cdef; + imm32 p2, 0x56769abc; + imm32 p3, 0xdef61234; + imm32 p4, 0x23466899; + imm32 p5, 0x78962345; + imm32 sp, 0x98765432; + imm32 fp, 0x12365678; + P1 = SP + ( P1 << 1 ); + P2 = SP + ( P2 << 1 ); + P3 = SP + ( P3 << 1 ); + P4 = SP + ( P4 << 1 ); + P5 = SP + ( P5 << 1 ); + SP = SP + ( SP << 1 ); + FP = SP + ( FP << 1 ); + CHECKREG p1, 0xABC3F010; + CHECKREG p2, 0x456389AA; + CHECKREG p3, 0x5662789A; + CHECKREG p4, 0xDF032564; + CHECKREG p5, 0x89A29ABC; + CHECKREG sp, 0xC962FC96; + CHECKREG fp, 0xEDCFA986; + + imm32 p1, 0x89ab7def; + imm32 p2, 0x56787abc; + imm32 p3, 0xdef07234; + imm32 p4, 0x23457899; + imm32 p5, 0x78917345; + imm32 sp, 0x98767432; + imm32 fp, 0x12345678; + P1 = FP + ( P1 << 1 ); + P2 = FP + ( P2 << 1 ); + P3 = FP + ( P3 << 1 ); + P4 = FP + ( P4 << 1 ); + P5 = FP + ( P5 << 1 ); + SP = FP + ( SP << 1 ); + FP = FP + ( FP << 1 ); + CHECKREG p1, 0x258B5256; + CHECKREG p2, 0xBF254BF0; + CHECKREG p3, 0xD0153AE0; + CHECKREG p4, 0x58BF47AA; + CHECKREG p5, 0x03573D02; + CHECKREG sp, 0x43213EDC; + CHECKREG fp, 0x369D0368; + + imm32 p1, 0x29ab1def; + imm32 p2, 0x52781abc; + imm32 p3, 0xde201234; + imm32 p4, 0x23421899; + imm32 p5, 0x78912345; + imm32 sp, 0x98761232; + imm32 fp, 0x12341628; + P1 = P3 + ( P1 << 1 ); + P2 = P4 + ( P1 << 1 ); + P3 = P5 + ( P1 << 1 ); + P4 = SP + ( P1 << 1 ); + P5 = FP + ( P1 << 1 ); + FP = P1 + ( P1 << 1 ); + CHECKREG p1, 0x31764E12; + CHECKREG p2, 0x862EB4BD; + CHECKREG p3, 0xDB7DBF69; + CHECKREG p4, 0xFB62AE56; + CHECKREG p5, 0x7520B24C; + CHECKREG fp, 0x9462EA36; + + imm32 p1, 0x893bcd2f; + imm32 p2, 0x56739a2c; + imm32 p3, 0x3ef03224; + imm32 p4, 0x23456329; + imm32 p5, 0x78312335; + imm32 sp, 0x98735423; + imm32 fp, 0x12343628; + P1 = P4 + ( P2 << 1 ); + P2 = P5 + ( P2 << 1 ); + P3 = SP + ( P2 << 1 ); + P4 = FP + ( P2 << 1 ); + SP = P1 + ( P2 << 1 ); + FP = P2 + ( P2 << 1 ); + CHECKREG p1, 0xD02C9781; + CHECKREG p2, 0x2518578D; + CHECKREG p3, 0xE2A4033D; + CHECKREG p4, 0x5C64E542; + CHECKREG sp, 0x1A5D469B; + CHECKREG fp, 0x6F4906A7; + + imm32 p1, 0x894bcde3; + imm32 p2, 0x56749ab3; + imm32 p3, 0x4ef04233; + imm32 p4, 0x24456493; + imm32 p5, 0x78412344; + imm32 sp, 0x98745434; + imm32 fp, 0x12344673; + P1 = P5 + ( P3 << 1 ); + P2 = SP + ( P3 << 1 ); + P3 = FP + ( P3 << 1 ); + P5 = P1 + ( P3 << 1 ); + SP = P2 + ( P3 << 1 ); + FP = P3 + ( P3 << 1 ); + CHECKREG p1, 0x1621A7AA; + CHECKREG p2, 0x3654D89A; + CHECKREG p3, 0xB014CAD9; + CHECKREG p5, 0x764B3D5C; + CHECKREG sp, 0x967E6E4C; + CHECKREG fp, 0x103E608B; + + imm32 p1, 0x49abc5ef; + imm32 p2, 0x46789a5c; + imm32 p3, 0x4ef01235; + imm32 p4, 0x53456899; + imm32 p5, 0x45912345; + imm32 sp, 0x48565432; + imm32 fp, 0x42355678; + P1 = SP + ( P4 << 1 ); + P2 = FP + ( P4 << 1 ); + P4 = P1 + ( P4 << 1 ); + P5 = P2 + ( P4 << 1 ); + SP = P3 + ( P4 << 1 ); + FP = P4 + ( P4 << 1 ); + CHECKREG p1, 0xEEE12564; + CHECKREG p2, 0xE8C027AA; + CHECKREG p4, 0x956BF696; + CHECKREG p5, 0x139814D6; + CHECKREG sp, 0x79C7FF61; + CHECKREG fp, 0xC043E3C2; + + imm32 p1, 0x85ab6def; + imm32 p2, 0x657896bc; + imm32 p3, 0xd6f01264; + imm32 p4, 0x25656896; + imm32 p5, 0x75962345; + imm32 sp, 0x95766432; + imm32 fp, 0x15345678; + P1 = FP + ( P5 << 1 ); + P3 = P1 + ( P5 << 1 ); + P4 = P2 + ( P5 << 1 ); + P5 = P3 + ( P5 << 1 ); + SP = P4 + ( P5 << 1 ); + FP = P5 + ( P5 << 1 ); + CHECKREG p1, 0x00609D02; + CHECKREG p3, 0xEB8CE38C; + CHECKREG p4, 0x50A4DD46; + CHECKREG p5, 0xD6B92A16; + CHECKREG sp, 0xFE173172; + CHECKREG fp, 0x842B7E42; + + imm32 p1, 0x89a7cdef; + imm32 p2, 0x56767abc; + imm32 p3, 0xdef61734; + imm32 p4, 0x73466879; + imm32 p5, 0x77962347; + imm32 sp, 0x98765432; + imm32 fp, 0x12375678; + P2 = P1 + ( SP << 1 ); + P3 = P2 + ( SP << 1 ); + P4 = P3 + ( SP << 1 ); + P5 = P4 + ( SP << 1 ); + SP = P5 + ( SP << 1 ); + FP = SP + ( SP << 1 ); + CHECKREG p2, 0xBA947653; + CHECKREG p3, 0xEB811EB7; + CHECKREG p4, 0x1C6DC71B; + CHECKREG p5, 0x4D5A6F7F; + CHECKREG sp, 0x7E4717E3; + CHECKREG fp, 0x7AD547A9; + + imm32 p1, 0x88ab78ef; + imm32 p2, 0x56887a8c; + imm32 p3, 0x8ef87238; + imm32 p4, 0x28458899; + imm32 p5, 0x78817845; + imm32 sp, 0x98787482; + imm32 fp, 0x12348678; + P1 = P2 + ( FP << 1 ); + P2 = P3 + ( FP << 1 ); + P3 = P4 + ( FP << 1 ); + P4 = P5 + ( FP << 1 ); + P5 = SP + ( FP << 1 ); + SP = FP + ( FP << 1 ); + CHECKREG p1, 0x7AF1877C; + CHECKREG p2, 0xB3617F28; + CHECKREG p3, 0x4CAE9589; + CHECKREG p4, 0x9CEA8535; + CHECKREG p5, 0xBCE18172; + CHECKREG sp, 0x369D9368; + + pass diff --git a/sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh2.s b/sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh2.s new file mode 100644 index 0000000..dd86726 --- /dev/null +++ b/sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh2.s @@ -0,0 +1,302 @@ +//Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh2/c_comp3op_pr_plus_pr_sh2.dsp +// Spec Reference: comp3op pregs + pregs << 2 +# mach: bfin + +.include "testutils.inc" + start + + imm32 p1, 0x89ab1def; + imm32 p2, 0x56781abc; + imm32 p3, 0xdef01234; + imm32 p4, 0x23451899; + imm32 p5, 0x78911345; + imm32 sp, 0x98761432; + imm32 fp, 0x12341678; + P1 = P1 + ( P1 << 2 ); + P2 = P1 + ( P2 << 2 ); + P3 = P1 + ( P3 << 2 ); + P4 = P1 + ( P4 << 2 ); + P5 = P1 + ( P5 << 2 ); + SP = P1 + ( SP << 2 ); + FP = P1 + FP; + CHECKREG p1, 0xB05795AB; + CHECKREG p2, 0x0A38009B; + CHECKREG p3, 0x2C17DE7B; + CHECKREG p4, 0x3D6BF80F; + CHECKREG p5, 0x929BE2BF; + CHECKREG sp, 0x122FE673; + CHECKREG fp, 0xC28BAC23; + + imm32 p1, 0x89abcd2f; + imm32 p2, 0x56789a2c; + imm32 p3, 0xdef01224; + imm32 p4, 0x23456829; + imm32 p5, 0x78912325; + imm32 sp, 0x98765422; + imm32 fp, 0x12345628; + P1 = P2 + ( P1 << 2 ); + P2 = P2 + ( P2 << 2 ); + P3 = P2 + ( P3 << 2 ); + P4 = P2 + ( P4 << 2 ); + P5 = P2 + ( P5 << 2 ); + SP = P2 + ( SP << 2 ); + FP = P2 + ( FP << 2 ); + CHECKREG p1, 0x7D27CEE8; + CHECKREG p2, 0xB05B02DC; + CHECKREG p3, 0x2C1B4B6C; + CHECKREG p4, 0x3D70A380; + CHECKREG p5, 0x929F8F70; + CHECKREG sp, 0x12345364; + CHECKREG fp, 0xF92C5B7C; + + imm32 p1, 0x89abcde3; + imm32 p2, 0x56789ab3; + imm32 p3, 0xdef01233; + imm32 p4, 0x23456893; + imm32 p5, 0x78912343; + imm32 sp, 0x98765433; + imm32 fp, 0x12345673; + P1 = P3 + ( P1 << 2 ); + P2 = P3 + ( P2 << 2 ); + P3 = P3 + ( P3 << 2 ); + P4 = P3 + ( P4 << 2 ); + P5 = P3 + ( P5 << 2 ); + SP = P3 + ( SP << 2 ); + FP = P3 + ( FP << 2 ); + CHECKREG p1, 0x059F49BF; + CHECKREG p2, 0x38D27CFF; + CHECKREG p3, 0x5AB05AFF; + CHECKREG p4, 0xE7C5FD4B; + CHECKREG p5, 0x3CF4E80B; + CHECKREG sp, 0xBC89ABCB; + CHECKREG fp, 0xA381B4CB; + + imm32 p1, 0x49abcdef; + imm32 p2, 0x46789abc; + imm32 p3, 0x4ef01234; + imm32 p4, 0x43456899; + imm32 p5, 0x48912345; + imm32 sp, 0x48765432; + imm32 fp, 0x42345678; + P1 = P4 + ( P1 << 2 ); + P2 = P4 + ( P2 << 2 ); + P3 = P4 + ( P3 << 2 ); + P4 = P4 + ( P4 << 2 ); + P5 = P4 + ( P5 << 2 ); + SP = P4 + ( SP << 2 ); + FP = P4 + ( FP << 2 ); + CHECKREG p1, 0x69F4A055; + CHECKREG p2, 0x5D27D389; + CHECKREG p3, 0x7F05B169; + CHECKREG p4, 0x505B0AFD; + CHECKREG p5, 0x729F9811; + CHECKREG sp, 0x72345BC5; + CHECKREG fp, 0x592C64DD; + + imm32 p1, 0x85abcdef; + imm32 p2, 0x55789abc; + imm32 p3, 0xd5f01234; + imm32 p4, 0x25456899; + imm32 p5, 0x75912345; + imm32 sp, 0x95765432; + imm32 fp, 0x15345678; + P1 = P5 + ( P1 << 2 ); + P2 = P5 + ( P2 << 2 ); + P3 = P5 + ( P3 << 2 ); + P4 = P5 + ( P4 << 2 ); + P5 = P5 + ( P5 << 2 ); + SP = P5 + ( SP << 2 ); + FP = P5 + ( FP << 2 ); + CHECKREG p1, 0x8C405B01; + CHECKREG p2, 0xCB738E35; + CHECKREG p3, 0xCD516C15; + CHECKREG p4, 0x0AA6C5A9; + CHECKREG p5, 0x4BD5B059; + CHECKREG sp, 0xA1AF0121; + CHECKREG fp, 0xA0A70A39; + + imm32 p1, 0x89a6cdef; + imm32 p2, 0x56769abc; + imm32 p3, 0xdef61234; + imm32 p4, 0x23466899; + imm32 p5, 0x78962345; + imm32 sp, 0x98765432; + imm32 fp, 0x12365678; + P1 = SP + ( P1 << 2 ); + P2 = SP + ( P2 << 2 ); + P3 = SP + ( P3 << 2 ); + P4 = SP + ( P4 << 2 ); + P5 = SP + ( P5 << 2 ); + SP = SP + ( SP << 2 ); + FP = SP + ( FP << 2 ); + CHECKREG p1, 0xBF118BEE; + CHECKREG p2, 0xF250BF22; + CHECKREG p3, 0x144E9D02; + CHECKREG p4, 0x258FF696; + CHECKREG p5, 0x7ACEE146; + CHECKREG sp, 0xFA4FA4FA; + CHECKREG fp, 0x4328FEDA; + + imm32 p1, 0x89ab7def; + imm32 p2, 0x56787abc; + imm32 p3, 0xdef07234; + imm32 p4, 0x23457899; + imm32 p5, 0x78917345; + imm32 sp, 0x98767432; + imm32 fp, 0x12345678; + P1 = FP + ( P1 << 2 ); + P2 = FP + ( P2 << 2 ); + P3 = FP + ( P3 << 2 ); + P4 = FP + ( P4 << 2 ); + P5 = FP + ( P5 << 2 ); + SP = FP + ( SP << 2 ); + FP = FP + ( FP << 2 ); + CHECKREG p1, 0x38E24E34; + CHECKREG p2, 0x6C164168; + CHECKREG p3, 0x8DF61F48; + CHECKREG p4, 0x9F4A38DC; + CHECKREG p5, 0xF47A238C; + CHECKREG sp, 0x740E2740; + CHECKREG fp, 0x5B05B058; + + imm32 p1, 0x29ab1def; + imm32 p2, 0x52781abc; + imm32 p3, 0xde201234; + imm32 p4, 0x23421899; + imm32 p5, 0x78912345; + imm32 sp, 0x98761232; + imm32 fp, 0x12341628; + P1 = P3 + ( P1 << 2 ); + P2 = P4 + ( P1 << 2 ); + P3 = P5 + ( P1 << 2 ); + P4 = SP + ( P1 << 2 ); + P5 = FP + ( P1 << 2 ); + FP = P1 + ( P1 << 2 ); + CHECKREG p1, 0x84CC89F0; + CHECKREG p2, 0x36744059; + CHECKREG p3, 0x8BC34B05; + CHECKREG p4, 0xABA839F2; + CHECKREG p5, 0x25663DE8; + CHECKREG fp, 0x97FEB1B0; + + imm32 p1, 0x893bcd2f; + imm32 p2, 0x56739a2c; + imm32 p3, 0x3ef03224; + imm32 p4, 0x23456329; + imm32 p5, 0x78312335; + imm32 sp, 0x98735423; + imm32 fp, 0x12343628; + P1 = P4 + ( P2 << 2 ); + P2 = P5 + ( P2 << 2 ); + P3 = SP + ( P2 << 2 ); + P4 = FP + ( P2 << 2 ); + SP = P1 + ( P2 << 2 ); + FP = P2 + ( P2 << 2 ); + CHECKREG p1, 0x7D13CBD9; + CHECKREG p2, 0xD1FF8BE5; + CHECKREG p3, 0xE07183B7; + CHECKREG p4, 0x5A3265BC; + CHECKREG sp, 0xC511FB6D; + CHECKREG fp, 0x19FDBB79; + + imm32 p1, 0x894bcde3; + imm32 p2, 0x56749ab3; + imm32 p3, 0x4ef04233; + imm32 p4, 0x24456493; + imm32 p5, 0x78412344; + imm32 sp, 0x98745434; + imm32 fp, 0x12344673; + P1 = P5 + ( P3 << 2 ); + P2 = SP + ( P3 << 2 ); + P3 = FP + ( P3 << 2 ); + P5 = P1 + ( P3 << 2 ); + SP = P2 + ( P3 << 2 ); + FP = P3 + ( P3 << 2 ); + CHECKREG p1, 0xB4022C10; + CHECKREG p2, 0xD4355D00; + CHECKREG p3, 0x4DF54F3F; + CHECKREG p5, 0xEBD7690C; + CHECKREG sp, 0x0C0A99FC; + CHECKREG fp, 0x85CA8C3B; + + imm32 p1, 0x49abc5ef; + imm32 p2, 0x46789a5c; + imm32 p3, 0x4ef01235; + imm32 p4, 0x53456899; + imm32 p5, 0x45912345; + imm32 sp, 0x48565432; + imm32 fp, 0x42355678; + P1 = SP + ( P4 << 2 ); + P2 = FP + ( P4 << 2 ); + P4 = P1 + ( P4 << 2 ); + P5 = P2 + ( P4 << 2 ); + SP = P3 + ( P4 << 2 ); + FP = P4 + ( P4 << 2 ); + CHECKREG p1, 0x956BF696; + CHECKREG p2, 0x8F4AF8DC; + CHECKREG p4, 0xE28198FA; + CHECKREG p5, 0x19515CC4; + CHECKREG sp, 0xD8F6761D; + CHECKREG fp, 0x6C87FCE2; + + imm32 p1, 0x85ab6def; + imm32 p2, 0x657896bc; + imm32 p3, 0xd6f01264; + imm32 p4, 0x25656896; + imm32 p5, 0x75962345; + imm32 sp, 0x95766432; + imm32 fp, 0x15345678; + P1 = FP + ( P5 << 2 ); + P3 = P1 + ( P5 << 2 ); + P4 = P2 + ( P5 << 2 ); + P5 = P3 + ( P5 << 2 ); + SP = P4 + ( P5 << 2 ); + FP = P5 + ( P5 << 2 ); + CHECKREG p1, 0xEB8CE38C; + CHECKREG p3, 0xC1E570A0; + CHECKREG p4, 0x3BD123D0; + CHECKREG p5, 0x983DFDB4; + CHECKREG sp, 0x9CC91AA0; + CHECKREG fp, 0xF935F484; + + imm32 p1, 0x89a7cdef; + imm32 p2, 0x56767abc; + imm32 p3, 0xdef61734; + imm32 p4, 0x73466879; + imm32 p5, 0x77962347; + imm32 sp, 0x98765432; + imm32 fp, 0x12375678; + P2 = P1 + ( SP << 2 ); + P3 = P2 + ( SP << 2 ); + P4 = P3 + ( SP << 2 ); + P5 = P4 + ( SP << 2 ); + SP = P5 + ( SP << 2 ); + FP = SP + ( SP << 2 ); + CHECKREG p2, 0xEB811EB7; + CHECKREG p3, 0x4D5A6F7F; + CHECKREG p4, 0xAF33C047; + CHECKREG p5, 0x110D110F; + CHECKREG sp, 0x72E661D7; + CHECKREG fp, 0x3E7FE933; + + imm32 p1, 0x88ab78ef; + imm32 p2, 0x56887a8c; + imm32 p3, 0x8ef87238; + imm32 p4, 0x28458899; + imm32 p5, 0x78817845; + imm32 sp, 0x98787482; + imm32 fp, 0x12348678; + P1 = P2 + ( FP << 2 ); + P2 = P3 + ( FP << 2 ); + P3 = P4 + ( FP << 2 ); + P4 = P5 + ( FP << 2 ); + P5 = SP + ( FP << 2 ); + SP = FP + ( FP << 2 ); + CHECKREG p1, 0x9F5A946C; + CHECKREG p2, 0xD7CA8C18; + CHECKREG p3, 0x7117A279; + CHECKREG p4, 0xC1539225; + CHECKREG p5, 0xE14A8E62; + CHECKREG sp, 0x5B06A058; + + pass diff --git a/sim/testsuite/bfin/c_compi2opd_dr_add_i7_n.s b/sim/testsuite/bfin/c_compi2opd_dr_add_i7_n.s new file mode 100644 index 0000000..af3406b --- /dev/null +++ b/sim/testsuite/bfin/c_compi2opd_dr_add_i7_n.s @@ -0,0 +1,164 @@ +//Original:/testcases/core/c_compi2opd_dr_add_i7_n/c_compi2opd_dr_add_i7_n.dsp +// Spec Reference: compi2opd dregs += imm7 negative +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +R0 += 0; +R1 += -1; +R2 += -2; +R3 += -3; +R4 += -4; +R5 += -5; +R6 += -6; +R7 += -7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFE; +CHECKREG r3, 0xFFFFFFFD; +CHECKREG r4, 0xFFFFFFFC; +CHECKREG r5, 0xFFFFFFFB; +CHECKREG r6, 0xFFFFFFFA; +CHECKREG r7, 0xFFFFFFF9; + +R0 += -8; +R1 += -9; +R2 += -10; +R3 += -11; +R4 += -12; +R5 += -13; +R6 += -14; +R7 += -15; +CHECKREG r0, 0xFFFFFFF8; +CHECKREG r1, 0xFFFFFFF6; +CHECKREG r2, 0xFFFFFFF4; +CHECKREG r3, 0xFFFFFFF2; +CHECKREG r4, 0xFFFFFFF0; +CHECKREG r5, 0xFFFFFFEE; +CHECKREG r6, 0xFFFFFFEC; +CHECKREG r7, 0xFFFFFFEA; + +R0 += -16; +R1 += -17; +R2 += -18; +R3 += -19; +R4 += -20; +R5 += -21; +R6 += -22; +R7 += -23; +CHECKREG r0, 0xFFFFFFE8; +CHECKREG r1, 0xFFFFFFE5; +CHECKREG r2, 0xFFFFFFE2; +CHECKREG r3, 0xFFFFFFDF; +CHECKREG r4, 0xFFFFFFDC; +CHECKREG r5, 0xFFFFFFD9; +CHECKREG r6, 0xFFFFFFD6; +CHECKREG r7, 0xFFFFFFD3; + +R0 += -24; +R1 += -25; +R2 += -26; +R3 += -27; +R4 += -28; +R5 += -29; +R6 += -30; +R7 += -31; +CHECKREG r0, 0xFFFFFFD0; +CHECKREG r1, 0xFFFFFFCC; +CHECKREG r2, 0xFFFFFFC8; +CHECKREG r3, 0xFFFFFFC4; +CHECKREG r4, 0xFFFFFFC0; +CHECKREG r5, 0xFFFFFFBC; +CHECKREG r6, 0xFFFFFFB8; +CHECKREG r7, 0xFFFFFFB4; + +R0 += -32; +R1 += -33; +R2 += -34; +R3 += -35; +R4 += -36; +R5 += -37; +R6 += -38; +R7 += -39; +CHECKREG r0, 0xFFFFFFB0; +CHECKREG r1, 0xFFFFFFAB; +CHECKREG r2, 0xFFFFFFA6; +CHECKREG r3, 0xFFFFFFA1; +CHECKREG r4, 0xFFFFFF9C; +CHECKREG r5, 0xFFFFFF97; +CHECKREG r6, 0xFFFFFF92; +CHECKREG r7, 0xFFFFFF8D; + +R0 += -40; +R1 += -41; +R2 += -42; +R3 += -43; +R4 += -44; +R5 += -45; +R6 += -46; +R7 += -47; +CHECKREG r0, 0xFFFFFF88; +CHECKREG r1, 0xFFFFFF82; +CHECKREG r2, 0xFFFFFF7C; +CHECKREG r3, 0xFFFFFF76; +CHECKREG r4, 0xFFFFFF70; +CHECKREG r5, 0xFFFFFF6A; +CHECKREG r6, 0xFFFFFF64; +CHECKREG r7, 0xFFFFFF5E; + +R0 += -48; +R1 += -49; +R2 += -50; +R3 += -51; +R4 += -52; +R5 += -53; +R6 += -54; +R7 += -55; +CHECKREG r0, 0xFFFFFF58; +CHECKREG r1, 0xFFFFFF51; +CHECKREG r2, 0xFFFFFF4A; +CHECKREG r3, 0xFFFFFF43; +CHECKREG r4, 0xFFFFFF3C; +CHECKREG r5, 0xFFFFFF35; +CHECKREG r6, 0xFFFFFF2E; +CHECKREG r7, 0xFFFFFF27; + +R0 += -56; +R1 += -57; +R2 += -58; +R3 += -59; +R4 += -60; +R5 += -61; +R6 += -62; +R7 += -63; +CHECKREG r0, 0xFFFFFF20; +CHECKREG r1, 0xFFFFFF18; +CHECKREG r2, 0xFFFFFF10; +CHECKREG r3, 0xFFFFFF08; +CHECKREG r4, 0xFFFFFF00; +CHECKREG r5, 0xFFFFFEF8; +CHECKREG r6, 0xFFFFFEF0; +CHECKREG r7, 0xFFFFFEE8; + +R0 += -64; +R1 += -64; +R2 += -64; +R3 += -64; +R4 += -64; +R5 += -64; +R6 += -64; +R7 += -64; +CHECKREG r0, 0xFFFFFEE0; +CHECKREG r1, 0xFFFFFED8; +CHECKREG r2, 0xFFFFFED0; +CHECKREG r3, 0xFFFFFEC8; +CHECKREG r4, 0xFFFFFEC0; +CHECKREG r5, 0xFFFFFEB8; +CHECKREG r6, 0xFFFFFEB0; +CHECKREG r7, 0xFFFFFEA8; + +pass diff --git a/sim/testsuite/bfin/c_compi2opd_dr_add_i7_p.s b/sim/testsuite/bfin/c_compi2opd_dr_add_i7_p.s new file mode 100644 index 0000000..66b4537 --- /dev/null +++ b/sim/testsuite/bfin/c_compi2opd_dr_add_i7_p.s @@ -0,0 +1,147 @@ +//Original:/testcases/core/c_compi2opd_dr_add_i7_p/c_compi2opd_dr_add_i7_p.dsp +// Spec Reference: compi2opd dregs += imm7 positive +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +R0 += 0; +R1 += 1; +R2 += 2; +R3 += 3; +R4 += 4; +R5 += 5; +R6 += 6; +R7 += 7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +R0 += 8; +R1 += 9; +R2 += 10; +R3 += 11; +R4 += 12; +R5 += 13; +R6 += 14; +R7 += 15; +CHECKREG r0, 0x00000008; +CHECKREG r1, 0x0000000A; +CHECKREG r2, 0x0000000C; +CHECKREG r3, 0x0000000E; +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000012; +CHECKREG r6, 0x00000014; +CHECKREG r7, 0x00000016; + +R0 += 16; +R1 += 17; +R2 += 18; +R3 += 19; +R4 += 20; +R5 += 21; +R6 += 22; +R7 += 23; +CHECKREG r0, 0x00000018; +CHECKREG r1, 0x0000001B; +CHECKREG r2, 0x0000001E; +CHECKREG r3, 0x00000021; +CHECKREG r4, 0x00000024; +CHECKREG r5, 0x00000027; +CHECKREG r6, 0x0000002A; +CHECKREG r7, 0x0000002D; + +R0 += 24; +R1 += 25; +R2 += 26; +R3 += 27; +R4 += 28; +R5 += 29; +R6 += 30; +R7 += 31; +CHECKREG r0, 0x00000030; +CHECKREG r1, 0x00000034; +CHECKREG r2, 0x00000038; +CHECKREG r3, 0x0000003C; +CHECKREG r4, 0x00000040; +CHECKREG r5, 0x00000044; +CHECKREG r6, 0x00000048; +CHECKREG r7, 0x0000004C; + +R0 += 32; +R1 += 33; +R2 += 34; +R3 += 35; +R4 += 36; +R5 += 37; +R6 += 38; +R7 += 39; +CHECKREG r0, 0x00000050; +CHECKREG r1, 0x00000055; +CHECKREG r2, 0x0000005A; +CHECKREG r3, 0x0000005F; +CHECKREG r4, 0x00000064; +CHECKREG r5, 0x00000069; +CHECKREG r6, 0x0000006E; +CHECKREG r7, 0x00000073; + +R0 += 40; +R1 += 41; +R2 += 42; +R3 += 43; +R4 += 44; +R5 += 45; +R6 += 46; +R7 += 47; +CHECKREG r0, 0x00000078; +CHECKREG r1, 0x0000007E; +CHECKREG r2, 0x00000084; +CHECKREG r3, 0x0000008A; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0x00000096; +CHECKREG r6, 0x0000009C; +CHECKREG r7, 0x000000A2; + +R0 += 48; +R1 += 49; +R2 += 50; +R3 += 51; +R4 += 52; +R5 += 53; +R6 += 54; +R7 += 55; +CHECKREG r0, 0x000000A8; +CHECKREG r1, 0x000000AF; +CHECKREG r2, 0x000000B6; +CHECKREG r3, 0x000000BD; +CHECKREG r4, 0x000000C4; +CHECKREG r5, 0x000000CB; +CHECKREG r6, 0x000000D2; +CHECKREG r7, 0x000000D9; + +R0 += 56; +R1 += 57; +R2 += 58; +R3 += 59; +R4 += 60; +R5 += 61; +R6 += 62; +R7 += 63; +CHECKREG r0, 0x000000E0; +CHECKREG r1, 0x000000E8; +CHECKREG r2, 0x000000F0; +CHECKREG r3, 0x000000F8; +CHECKREG r4, 0x00000100; +CHECKREG r5, 0x00000108; +CHECKREG r6, 0x00000110; +CHECKREG r7, 0x00000118; + +pass diff --git a/sim/testsuite/bfin/c_compi2opd_dr_eq_i7_n.s b/sim/testsuite/bfin/c_compi2opd_dr_eq_i7_n.s new file mode 100644 index 0000000..509929d --- /dev/null +++ b/sim/testsuite/bfin/c_compi2opd_dr_eq_i7_n.s @@ -0,0 +1,166 @@ +//Original:/testcases/core/c_compi2opd_dr_eq_i7_n/c_compi2opd_dr_eq_i7_n.dsp +// Spec Reference: compi2opd dregs = imm7 negative +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + + +R0 = -0; +R1 = -1; +R2 = -2; +R3 = -3; +R4 = -4; +R5 = -5; +R6 = -6; +R7 = -7; +CHECKREG r0, -0; +CHECKREG r1, -1; +CHECKREG r2, -2; +CHECKREG r3, -3; +CHECKREG r4, -4; +CHECKREG r5, -5; +CHECKREG r6, -6; +CHECKREG r7, -7; + +R0 = -8; +R1 = -9; +R2 = -10; +R3 = -11; +R4 = -12; +R5 = -13; +R6 = -14; +R7 = -15; +CHECKREG r0, -8; +CHECKREG r1, -9; +CHECKREG r2, -10; +CHECKREG r3, -11; +CHECKREG r4, -12; +CHECKREG r5, -13; +CHECKREG r6, -14; +CHECKREG r7, -15; + +R0 = -16; +R1 = -17; +R2 = -18; +R3 = -19; +R4 = -20; +R5 = -21; +R6 = -22; +R7 = -23; +CHECKREG r0, -16; +CHECKREG r1, -17; +CHECKREG r2, -18; +CHECKREG r3, -19; +CHECKREG r4, -20; +CHECKREG r5, -21; +CHECKREG r6, -22; +CHECKREG r7, -23; + +R0 = -24; +R1 = -25; +R2 = -26; +R3 = -27; +R4 = -28; +R5 = -29; +R6 = -30; +R7 = -31; +CHECKREG r0, -24; +CHECKREG r1, -25; +CHECKREG r2, -26; +CHECKREG r3, -27; +CHECKREG r4, -28; +CHECKREG r5, -29; +CHECKREG r6, -30; +CHECKREG r7, -31; + +R0 = -32; +R1 = -33; +R2 = -34; +R3 = -35; +R4 = -36; +R5 = -37; +R6 = -38; +R7 = -39; +CHECKREG r0, -32; +CHECKREG r1, -33; +CHECKREG r2, -34; +CHECKREG r3, -35; +CHECKREG r4, -36; +CHECKREG r5, -37; +CHECKREG r6, -38; +CHECKREG r7, -39; + +R0 = -40; +R1 = -41; +R2 = -42; +R3 = -43; +R4 = -44; +R5 = -45; +R6 = -46; +R7 = -47; +CHECKREG r0, -40; +CHECKREG r1, -41; +CHECKREG r2, -42; +CHECKREG r3, -43; +CHECKREG r4, -44; +CHECKREG r5, -45; +CHECKREG r6, -46; +CHECKREG r7, -47; + +R0 = -48; +R1 = -49; +R2 = -50; +R3 = -51; +R4 = -52; +R5 = -53; +R6 = -54; +R7 = -55; +CHECKREG r0, -48; +CHECKREG r1, -49; +CHECKREG r2, -50; +CHECKREG r3, -51; +CHECKREG r4, -52; +CHECKREG r5, -53; +CHECKREG r6, -54; +CHECKREG r7, -55; + +R0 = -56; +R1 = -57; +R2 = -58; +R3 = -59; +R4 = -60; +R5 = -61; +R6 = -62; +R7 = -63; +CHECKREG r0, -56; +CHECKREG r1, -57; +CHECKREG r2, -58; +CHECKREG r3, -59; +CHECKREG r4, -60; +CHECKREG r5, -61; +CHECKREG r6, -62; +CHECKREG r7, -63; + +R0 = -64; +R1 = -64; +R2 = -64; +R3 = -64; +R4 = -64; +R5 = -64; +R6 = -64; +R7 = -64; +CHECKREG r0, -64; +CHECKREG r1, -64; +CHECKREG r2, -64; +CHECKREG r3, -64; +CHECKREG r4, -64; +CHECKREG r5, -64; +CHECKREG r6, -64; +CHECKREG r7, -64; + + +pass diff --git a/sim/testsuite/bfin/c_compi2opd_dr_eq_i7_p.s b/sim/testsuite/bfin/c_compi2opd_dr_eq_i7_p.s new file mode 100644 index 0000000..5e792cc --- /dev/null +++ b/sim/testsuite/bfin/c_compi2opd_dr_eq_i7_p.s @@ -0,0 +1,147 @@ +//Original:/testcases/core/c_compi2opd_dr_eq_i7_p/c_compi2opd_dr_eq_i7_p.dsp +// Spec Reference: compi2opd dregs = imm7 positive +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +R0 = 0; +R1 = 1; +R2 = 2; +R3 = 3; +R4 = 4; +R5 = 5; +R6 = 6; +R7 = 7; +CHECKREG r0, 0; +CHECKREG r1, 1; +CHECKREG r2, 2; +CHECKREG r3, 3; +CHECKREG r4, 4; +CHECKREG r5, 5; +CHECKREG r6, 6; +CHECKREG r7, 7; + +R0 = 8; +R1 = 9; +R2 = 10; +R3 = 11; +R4 = 12; +R5 = 13; +R6 = 14; +R7 = 15; +CHECKREG r0, 8; +CHECKREG r1, 9; +CHECKREG r2, 10; +CHECKREG r3, 11; +CHECKREG r4, 12; +CHECKREG r5, 13; +CHECKREG r6, 14; +CHECKREG r7, 15; + +R0 = 16; +R1 = 17; +R2 = 18; +R3 = 19; +R4 = 20; +R5 = 21; +R6 = 22; +R7 = 23; +CHECKREG r0, 16; +CHECKREG r1, 17; +CHECKREG r2, 18; +CHECKREG r3, 19; +CHECKREG r4, 20; +CHECKREG r5, 21; +CHECKREG r6, 22; +CHECKREG r7, 23; + +R0 = 24; +R1 = 25; +R2 = 26; +R3 = 27; +R4 = 28; +R5 = 29; +R6 = 30; +R7 = 31; +CHECKREG r0, 24; +CHECKREG r1, 25; +CHECKREG r2, 26; +CHECKREG r3, 27; +CHECKREG r4, 28; +CHECKREG r5, 29; +CHECKREG r6, 30; +CHECKREG r7, 31; + +R0 = 32; +R1 = 33; +R2 = 34; +R3 = 35; +R4 = 36; +R5 = 37; +R6 = 38; +R7 = 39; +CHECKREG r0, 32; +CHECKREG r1, 33; +CHECKREG r2, 34; +CHECKREG r3, 35; +CHECKREG r4, 36; +CHECKREG r5, 37; +CHECKREG r6, 38; +CHECKREG r7, 39; + +R0 = 40; +R1 = 41; +R2 = 42; +R3 = 43; +R4 = 44; +R5 = 45; +R6 = 46; +R7 = 47; +CHECKREG r0, 40; +CHECKREG r1, 41; +CHECKREG r2, 42; +CHECKREG r3, 43; +CHECKREG r4, 44; +CHECKREG r5, 45; +CHECKREG r6, 46; +CHECKREG r7, 47; + +R0 = 48; +R1 = 49; +R2 = 50; +R3 = 51; +R4 = 52; +R5 = 53; +R6 = 54; +R7 = 55; +CHECKREG r0, 48; +CHECKREG r1, 49; +CHECKREG r2, 50; +CHECKREG r3, 51; +CHECKREG r4, 52; +CHECKREG r5, 53; +CHECKREG r6, 54; +CHECKREG r7, 55; + +R0 = 56; +R1 = 57; +R2 = 58; +R3 = 59; +R4 = 60; +R5 = 61; +R6 = 62; +R7 = 63; +CHECKREG r0, 56; +CHECKREG r1, 57; +CHECKREG r2, 58; +CHECKREG r3, 59; +CHECKREG r4, 60; +CHECKREG r5, 61; +CHECKREG r6, 62; +CHECKREG r7, 63; + +pass diff --git a/sim/testsuite/bfin/c_compi2opd_flags.S b/sim/testsuite/bfin/c_compi2opd_flags.S new file mode 100644 index 0000000..5438e91 --- /dev/null +++ b/sim/testsuite/bfin/c_compi2opd_flags.S @@ -0,0 +1,600 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opd_flags/c_compi2opd_flags.dsp +// Spec Reference: compi2opd dregs += imm7 flags (az, an, ac, av0) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + INIT_R_REGS 0; + ASTAT = R0; // initialize astat + +// AZ for R0 + imm32 r0, 0x00000000; + R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R0 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R0 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R0; + R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R0 + imm32 r0, 0xffffffff; + R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R0; + R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0xFFFFFFFF; + CHECKREG r1, 0x00000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R0 + imm32 r0, 0x7fffffff; + R0 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R1 = R0; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R0; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFE; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); //C + CHECKREG r7, (_VS|_V|_V_COPY|_AN); // A + +// AZ, AN, AC, AV0 for R0 + R0 = 0; + ASTAT = R0; + imm32 r0, 0x80000000; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R1 = R0; + R0 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R0; + R0 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000001; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x80000000; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R0 + R1 = 0; + ASTAT = R1; + imm32 r1, 0x00000000; + R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R1 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R1 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R1; + R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R1 + imm32 r1, 0xffffffff; + R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R1; + R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R1 + imm32 r1, 0x7fffffff; + R1 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R1; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R1; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFE; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R1 + R1 = 0; + ASTAT = R1; + imm32 r1, 0x80000000; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R1; + R1 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R1; + R1 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000001; + CHECKREG r2, 0x80000000; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R2 + imm32 r2, 0x00000000; + ASTAT = R2; + R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R2 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R2 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R2; + R2 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R2 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R2 + imm32 r2, 0xffffffff; + R2 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R2; + R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R2 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r2, 0xFFFFFFFF; + CHECKREG r1, 0x00000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R2 + imm32 r2, 0x7fffffff; + R2 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R2; + R2 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R2; + R2 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x7FFFFFFE; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R2 + R2 = 0; + ASTAT = R2; + imm32 r2, 0x80000000; + R2 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R2; + R2 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R2; + R2 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x80000001; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R3 + imm32 r3, 0x00000000; + ASTAT = R3; + R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R3 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R3 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R3; + R3 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R3 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, 0x00000000; + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R3 + imm32 r3, 0xffffffff; + R3 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R3; + R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R3 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R3 + imm32 r3, 0x7fffffff; + R3 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R3; + R3 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R3; + R3 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r3, 0x7FFFFFFE; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R3 + R3 = 0; + ASTAT = R3; + imm32 r3, 0x80000000; + R3 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R3; + R3 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R3; + R3 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000000; + CHECKREG r3, 0x80000001; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R4 + imm32 r4, 0x00000000; + ASTAT = R4; + R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R4 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R4 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R4; + R4 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R3 = ASTAT; + R4 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, (_AN); + CHECKREG r4, 0x00000000; + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R4 + imm32 r4, 0xffffffff; + R4 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R4; + R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R4 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R4 + imm32 r4, 0x7fffffff; + R4 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R1 = R4; + R4 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R4; + R4 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r4, 0x7FFFFFFE; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R4 + R4 = 0; + ASTAT = R4; + imm32 r4, 0x80000000; + R4 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R1 = R4; + R4 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R4; + R4 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x80000000; + CHECKREG r4, 0x80000001; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R5 + imm32 r5, 0x00000000; + ASTAT = R5; + R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R5 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R5 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + R0 = R5; + R5 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R5 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R5 + imm32 r5, 0xffffffff; + R5 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R5; + R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R5 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r4, (_AN); + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R5 + imm32 r5, 0x7fffffff; + R5 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R5; + R5 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R5; + R5 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r4, (_VS|_AC0|_AC0_COPY); + CHECKREG r5, 0x7FFFFFFE; + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R5 + R5 = 0; + ASTAT = R5; + imm32 r5, 0x80000000; + R5 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R5; + R5 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R5; + R5 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r2, 0x80000000; + CHECKREG r4, (_VS|_AN); + CHECKREG r5, 0x80000001; + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R6 + imm32 r6, 0x00000000; + ASTAT = R6; + R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R6 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R0 = ASTAT; + R6 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R6; + R6 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R6 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R6 + imm32 r6, 0xffffffff; + R6 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R6; + R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R4 = ASTAT; + R6 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r4, (_AZ); + CHECKREG r5, (_AN); + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R6 + R6 = 0; + ASTAT = R6; + imm32 r6, 0x7fffffff; + R6 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R6; + R6 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R4 = ASTAT; + R1 = R6; + R6 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, 0x7FFFFFFE; + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R6 + R6 = 0; + ASTAT = R6; + imm32 r6, 0x80000000; + R6 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R6; + R6 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R4 = ASTAT; + R1 = R6; + R6 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000000; + CHECKREG r4, (_VS|_V|_V_COPY|_AN); + CHECKREG r5, (_VS|_AN); + CHECKREG r6, 0x80000001; + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R7 + imm32 r7, 0x00000000; + ASTAT = R7; + R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R1 = ASTAT; + R7 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R7 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R7; + R7 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R7 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, (_AZ); + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + +// AN, AC for R7 + imm32 r7, 0xffffffff; + R7 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R4 = ASTAT; + R0 = R7; + R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R7 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r4, (_AC0|_AC0_COPY|_AZ); + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, 0xFFFFFFFF; + +// AC, AV0 for R7 + R7 = 0; + ASTAT = R7; + imm32 r7, 0x7fffffff; + R7 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R4 = ASTAT; + R0 = R7; + R7 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R7; + R7 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r4, (_VS|_V|_V_COPY|_AN); + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, 0x7FFFFFFE; + +// AZ, AN, AC, AV0 for R7 + R7 = 0; + ASTAT = R7; + imm32 r7, 0x80000000; + R7 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R4 = ASTAT; + R0 = R7; + R7 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R7; + R7 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000000; + CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, 0x80000001; + + pass diff --git a/sim/testsuite/bfin/c_compi2opd_flags_2.S b/sim/testsuite/bfin/c_compi2opd_flags_2.S new file mode 100644 index 0000000..83bf1b0 --- /dev/null +++ b/sim/testsuite/bfin/c_compi2opd_flags_2.S @@ -0,0 +1,600 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opd_flags_2/c_compi2opd_flags_2.dsp +// Spec Reference: compi2opd dregs += imm7 flags_2 (az, an, ac, av0) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = R0; // initialize astat + +// AZ for R0 + imm32 r0, 0x00000000; + R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R0 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R0 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R0; + R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R0 + imm32 r0, 0xffffffff; + R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R0; + R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0xFFFFFFFF; + CHECKREG r1, 0x00000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R0 + imm32 r0, 0x7fffffff; + R0 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R1 = R0; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R0; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFE; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY|_V|_V_COPY|_VS); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R0 + R0 = 0; + ASTAT = R0; + imm32 r0, 0x80000000; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R1 = R0; + R0 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R0; + R0 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000001; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x80000000; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V_COPY|_V|_AN); + CHECKREG r7, (_VS|_V_COPY|_V|_AC0|_AC0_COPY); + +// AZ for R0 + imm32 r1, 0x00000000; + ASTAT = R1; + R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R1 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R1 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R1; + R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R1 + r1 = 0; + ASTAT = r1; + imm32 r1, 0xffffffff; + R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R1; + R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R1 + imm32 r1, 0x7fffffff; + R1 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R1; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R1; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFE; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R1 + R1 = 0; + ASTAT = R1; + imm32 r1, 0x80000000; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R1; + R1 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R1; + R1 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000001; + CHECKREG r2, 0x80000000; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R2 + imm32 r2, 0x00000000; + ASTAT = R2; + R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R2 += 2; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R2 += -2; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R2; + R2 += -2; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R2 += 2; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R2 + R2 = 0; + ASTAT = R2; + imm32 r2, 0xffffffff; + R2 += 2; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R2; + R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R2 += -2; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r2, 0xFFFFFFFF; + CHECKREG r1, (_AZ); + CHECKREG r5, (_AN); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R2 + imm32 r2, 0x7fffffff; + R2 += 2; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R2; + R2 += -2; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R2; + R2 += -2; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000001; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x7FFFFFFD; + CHECKREG r5, (_AC0|_AC0_COPY|_VS); + CHECKREG r6, (_AC0|_AC0_COPY|_VS|_V|_V_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R2 + R2 = 0; + ASTAT = R2; + imm32 r2, 0x80000000; + R2 += -2; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R2; + R2 += 2; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R2; + R2 += 2; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFE; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x80000002; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_AC0|_AC0_COPY|_VS|_V|_V_COPY); + +// AZ for R3 + imm32 r3, 0x00000000; + ASTAT = R3; + R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R3 += 3; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R3 += -3; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R3; + R3 += -3; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R3 += 3; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, 0x00000000; + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R3 + imm32 r3, 0xffffffff; + R3 += 3; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R3; + R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R3 += -3; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000002; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R3 + imm32 r3, 0x7fffffff; + R3 += 3; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R3; + R3 += -3; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R3; + R3 += -3; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000002; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r3, 0x7FFFFFFC; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY|_VS|_V|_V_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R3 + R3 = 0; + ASTAT = R3; + imm32 r3, 0x80000000; + R3 += -3; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R3; + R3 += 3; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R3; + R3 += 3; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFD; + CHECKREG r1, 0x80000000; + CHECKREG r3, 0x80000003; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R4 + imm32 r4, 0x00000000; + ASTAT = R4; + R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R4 += 4; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R4 += -4; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R4; + R4 += -4; // az = 0 an = 1 ac = 0 av0 = 0 + R3 = ASTAT; + R4 += 4; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, (_AN); + CHECKREG r4, 0x00000000; + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R4 + imm32 r4, 0xffffffff; + R4 += 4; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R4; + R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R4 += -4; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x00000003; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R4 + imm32 r4, 0x7fffffff; + R4 += 4; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R1 = R4; + R4 += -4; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R4; + R4 += -4; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x80000003; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r4, 0x7FFFFFFB; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R4 + R4 = 0; + ASTAT = R4; + imm32 r4, 0x80000000; + R4 += -4; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R1 = R4; + R4 += 4; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R4; + R4 += 4; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x7FFFFFFC; + CHECKREG r2, 0x80000000; + CHECKREG r4, 0x80000004; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R5 + imm32 r5, 0x00000000; + ASTAT = R5; + R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R5 += 5; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R5 += -5; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + R0 = R5; + R5 += -5; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R5 += 5; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R5 + imm32 r5, 0xffffffff; + R5 += 5; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R5; + R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R5 += -5; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x00000004; + CHECKREG r4, (_AN); + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R5 + imm32 r5, 0x7fffffff; + R5 += 5; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R5; + R5 += -5; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R5; + R5 += -5; // az = 0 an = 0 ac = 1 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x80000004; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r4, (_VS|_AC0|_AC0_COPY); + CHECKREG r5, 0x7FFFFFFA; + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R5 + R5 = 0; + ASTAT = R5; + imm32 r5, 0x80000000; + R5 += -5; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R5; + R5 += 5; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R5; + R5 += 5; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x7FFFFFFB; + CHECKREG r2, 0x80000000; + CHECKREG r4, (_VS|_AN); + CHECKREG r5, 0x80000005; + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R6 + imm32 r6, 0x00000000; + ASTAT = R6; + R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R6 += 6; // az = 0 an = 0 ac = 0 av0 = 0 + R0 = ASTAT; + R6 += -6; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R6; + R6 += -6; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R6 += 6; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R6 + imm32 r6, 0xffffffff; + R6 += 6; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R6; + R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R4 = ASTAT; + R6 += -6; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x00000005; + CHECKREG r4, 0x00000000; + CHECKREG r5, (_AN); + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R6 + imm32 r6, 0x7fffffff; + R6 += 6; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R6; + R6 += -6; // az = 0 an = 0 ac = 1 av0 = 1 + R4 = ASTAT; + R1 = R6; + R6 += -6; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000005; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, 0x7FFFFFF9; + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R6 + R6 = 0; + ASTAT = R6; + imm32 r6, 0x80000000; + R6 += -6; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R6; + R6 += 6; // az = 1 an = 1 ac = 0 av0 = 1 + R4 = ASTAT; + R1 = R6; + R6 += 6; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFA; + CHECKREG r1, 0x80000000; + CHECKREG r4, (_VS|_V|_V_COPY|_AN); + CHECKREG r5, (_VS|_AN); + CHECKREG r6, 0x80000006; + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R7 + imm32 r7, 0x00000000; + ASTAT = R7; + R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R1 = ASTAT; + R7 += 7; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R7 += -7; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R7; + R7 += -7; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R7 += 7; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, (_AZ); + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + +// AN, AC for R7 + imm32 r7, 0xffffffff; + R7 += 7; // az = 1 an = 0 ac = 1 av0 = 0 + R4 = ASTAT; + R0 = R7; + R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R7 += -7; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000006; + CHECKREG r4, (_AC0|_AC0_COPY); + CHECKREG r5, (_AN); + CHECKREG r6, 0x00000000; + CHECKREG r7, 0xFFFFFFFF; + +// AC, AV0 for R7 + imm32 r7, 0x7fffffff; + R7 += 7; // az = 0 an = 1 ac = 0 av0 = 1 + R4 = ASTAT; + R0 = R7; + R7 += -7; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R7; + R7 += -7; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000006; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r4, (_VS|_V|_V_COPY|_AN); + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, 0x7FFFFFF8; + +// AZ, AN, AC, AV0 for R7 + R7 = 0; + ASTAT = R7; + imm32 r7, 0x80000000; + R7 += -7; // az = 0 an = 0 ac = 1 av0 = 1 + R4 = ASTAT; + R0 = R7; + R7 += 7; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R7; + R7 += 7; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFF9; + CHECKREG r1, 0x80000000; + CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, 0x80000007; + + pass diff --git a/sim/testsuite/bfin/c_compi2opp_pr_add_i7_n.s b/sim/testsuite/bfin/c_compi2opp_pr_add_i7_n.s new file mode 100644 index 0000000..b63cb86 --- /dev/null +++ b/sim/testsuite/bfin/c_compi2opp_pr_add_i7_n.s @@ -0,0 +1,149 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_n/c_compi2opp_pr_add_i7_n.dsp +// Spec Reference: compi2opp pregs += imm7 negative +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + INIT_P_REGS 0; + + imm32 sp, 0x00000000; + imm32 fp, 0x00000000; + + P1 += -1; + P2 += -2; + P3 += -3; + P4 += -4; + P5 += -5; + SP += -6; + FP += -7; + CHECKREG p1, 0xFFFFFFFF; + CHECKREG p2, 0xFFFFFFFE; + CHECKREG p3, 0xFFFFFFFD; + CHECKREG p4, 0xFFFFFFFC; + CHECKREG p5, 0xFFFFFFFB; + CHECKREG sp, 0xFFFFFFFA; + CHECKREG fp, 0xFFFFFFF9; + + P1 += -9; + P2 += -10; + P3 += -11; + P4 += -12; + P5 += -13; + SP += -14; + FP += -15; + CHECKREG p1, 0xFFFFFFF6; + CHECKREG p2, 0xFFFFFFF4; + CHECKREG p3, 0xFFFFFFF2; + CHECKREG p4, 0xFFFFFFF0; + CHECKREG p5, 0xFFFFFFEE; + CHECKREG sp, 0xFFFFFFEC; + CHECKREG fp, 0xFFFFFFEA; + + P1 += -17; + P2 += -18; + P3 += -19; + P4 += -20; + P5 += -21; + SP += -22; + FP += -23; + CHECKREG p1, 0xFFFFFFE5; + CHECKREG p2, 0xFFFFFFE2; + CHECKREG p3, 0xFFFFFFDF; + CHECKREG p4, 0xFFFFFFDC; + CHECKREG p5, 0xFFFFFFD9; + CHECKREG sp, 0xFFFFFFD6; + CHECKREG fp, 0xFFFFFFD3; + + P1 += -25; + P2 += -26; + P3 += -27; + P4 += -28; + P5 += -29; + SP += -30; + FP += -31; + CHECKREG p1, 0xFFFFFFCC; + CHECKREG p2, 0xFFFFFFC8; + CHECKREG p3, 0xFFFFFFC4; + CHECKREG p4, 0xFFFFFFC0; + CHECKREG p5, 0xFFFFFFBC; + CHECKREG sp, 0xFFFFFFB8; + CHECKREG fp, 0xFFFFFFB4; + + P1 += -33; + P2 += -34; + P3 += -35; + P4 += -36; + P5 += -37; + SP += -38; + FP += -39; + CHECKREG p1, 0xFFFFFFAB; + CHECKREG p2, 0xFFFFFFA6; + CHECKREG p3, 0xFFFFFFA1; + CHECKREG p4, 0xFFFFFF9C; + CHECKREG p5, 0xFFFFFF97; + CHECKREG sp, 0xFFFFFF92; + CHECKREG fp, 0xFFFFFF8D; + + P1 += -41; + P2 += -42; + P3 += -43; + P4 += -44; + P5 += -45; + SP += -46; + FP += -47; + CHECKREG p1, 0xFFFFFF82; + CHECKREG p2, 0xFFFFFF7C; + CHECKREG p3, 0xFFFFFF76; + CHECKREG p4, 0xFFFFFF70; + CHECKREG p5, 0xFFFFFF6A; + CHECKREG sp, 0xFFFFFF64; + CHECKREG fp, 0xFFFFFF5E; + + P1 += -49; + P2 += -50; + P3 += -51; + P4 += -52; + P5 += -53; + SP += -54; + FP += -55; + CHECKREG p1, 0xFFFFFF51; + CHECKREG p2, 0xFFFFFF4A; + CHECKREG p3, 0xFFFFFF43; + CHECKREG p4, 0xFFFFFF3C; + CHECKREG p5, 0xFFFFFF35; + CHECKREG sp, 0xFFFFFF2E; + CHECKREG fp, 0xFFFFFF27; + + P1 += -57; + P2 += -58; + P3 += -59; + P4 += -60; + P5 += -61; + SP += -62; + FP += -63; + CHECKREG p1, 0xFFFFFF18; + CHECKREG p2, 0xFFFFFF10; + CHECKREG p3, 0xFFFFFF08; + CHECKREG p4, 0xFFFFFF00; + CHECKREG p5, 0xFFFFFEF8; + CHECKREG sp, 0xFFFFFEF0; + CHECKREG fp, 0xFFFFFEE8; + + P1 += -64; + P2 += -64; + P3 += -64; + P4 += -64; + P5 += -64; + SP += -64; + FP += -64; + CHECKREG p1, 0xFFFFFED8; + CHECKREG p2, 0xFFFFFED0; + CHECKREG p3, 0xFFFFFEC8; + CHECKREG p4, 0xFFFFFEC0; + CHECKREG p5, 0xFFFFFEB8; + CHECKREG sp, 0xFFFFFEB0; + CHECKREG fp, 0xFFFFFEA8; + + pass diff --git a/sim/testsuite/bfin/c_compi2opp_pr_add_i7_p.s b/sim/testsuite/bfin/c_compi2opp_pr_add_i7_p.s new file mode 100644 index 0000000..75336a8 --- /dev/null +++ b/sim/testsuite/bfin/c_compi2opp_pr_add_i7_p.s @@ -0,0 +1,116 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_p/c_compi2opp_pr_add_i7_p.dsp +// Spec Reference: compi2opp pregs += imm7 positive +# mach: bfin + +.include "testutils.inc" + start + + INIT_P_REGS 0; + + imm32 fp, 0x00000000; + + P1 += 1; + P2 += 2; + P3 += 3; + P4 += 4; + P5 += 5; + FP += 7; + CHECKREG p1, 0x00000001; + CHECKREG p2, 0x00000002; + CHECKREG p3, 0x00000003; + CHECKREG p4, 0x00000004; + CHECKREG p5, 0x00000005; + CHECKREG fp, 0x00000007; + + P1 += 9; + P2 += 10; + P3 += 11; + P4 += 12; + P5 += 13; + FP += 15; + CHECKREG p1, 0x0000000A; + CHECKREG p2, 0x0000000C; + CHECKREG p3, 0x0000000E; + CHECKREG p4, 0x00000010; + CHECKREG p5, 0x00000012; + CHECKREG fp, 0x00000016; + + P1 += 17; + P2 += 18; + P3 += 19; + P4 += 20; + P5 += 21; + FP += 23; + CHECKREG p1, 0x0000001B; + CHECKREG p2, 0x0000001E; + CHECKREG p3, 0x00000021; + CHECKREG p4, 0x00000024; + CHECKREG p5, 0x00000027; + CHECKREG fp, 0x0000002D; + + P1 += 25; + P2 += 26; + P3 += 27; + P4 += 28; + P5 += 29; + FP += 31; + CHECKREG p1, 0x00000034; + CHECKREG p2, 0x00000038; + CHECKREG p3, 0x0000003C; + CHECKREG p4, 0x00000040; + CHECKREG p5, 0x00000044; + CHECKREG fp, 0x0000004C; + + P1 += 33; + P2 += 34; + P3 += 35; + P4 += 36; + P5 += 37; + FP += 39; + CHECKREG p1, 0x00000055; + CHECKREG p2, 0x0000005A; + CHECKREG p3, 0x0000005F; + CHECKREG p4, 0x00000064; + CHECKREG p5, 0x00000069; + CHECKREG fp, 0x00000073; + + P1 += 41; + P2 += 42; + P3 += 43; + P4 += 44; + P5 += 45; + FP += 47; + CHECKREG p1, 0x0000007E; + CHECKREG p2, 0x00000084; + CHECKREG p3, 0x0000008A; + CHECKREG p4, 0x00000090; + CHECKREG p5, 0x00000096; + CHECKREG fp, 0x000000A2; + + P1 += 49; + P2 += 50; + P3 += 51; + P4 += 52; + P5 += 53; + FP += 55; + CHECKREG p1, 0x000000AF; + CHECKREG p2, 0x000000B6; + CHECKREG p3, 0x000000BD; + CHECKREG p4, 0x000000C4; + CHECKREG p5, 0x000000CB; + CHECKREG fp, 0x000000D9; + + P1 += 57; + P2 += 58; + P3 += 59; + P4 += 60; + P5 += 61; + FP += 63; + CHECKREG p1, 0x000000E8; + CHECKREG p2, 0x000000F0; + CHECKREG p3, 0x000000F8; + CHECKREG p4, 0x00000100; + CHECKREG p5, 0x00000108; + CHECKREG fp, 0x00000118; + + pass diff --git a/sim/testsuite/bfin/c_compi2opp_pr_eq_i7_n.s b/sim/testsuite/bfin/c_compi2opp_pr_eq_i7_n.s new file mode 100644 index 0000000..efeeb69 --- /dev/null +++ b/sim/testsuite/bfin/c_compi2opp_pr_eq_i7_n.s @@ -0,0 +1,161 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_n/c_compi2opp_pr_eq_i7_n.dsp +// Spec Reference: compi2opp pregs = imm7 negative +# mach: bfin + +.include "testutils.inc" + start + + R0 = -0; + P1 = -1; + P2 = -2; + P3 = -3; + P4 = -4; + P5 = -5; + SP = -6; + FP = -7; + CHECKREG r0, -0; + CHECKREG p1, -1; + CHECKREG p2, -2; + CHECKREG p3, -3; + CHECKREG p4, -4; + CHECKREG p5, -5; + CHECKREG sp, -6; + CHECKREG fp, -7; + + R0 = -8; + P1 = -9; + P2 = -10; + P3 = -11; + P4 = -12; + P5 = -13; + SP = -14; + FP = -15; + CHECKREG r0, -8; + CHECKREG p1, -9; + CHECKREG p2, -10; + CHECKREG p3, -11; + CHECKREG p4, -12; + CHECKREG p5, -13; + CHECKREG sp, -14; + CHECKREG fp, -15; + + R0 = -16; + P1 = -17; + P2 = -18; + P3 = -19; + P4 = -20; + P5 = -21; + SP = -22; + FP = -23; + CHECKREG r0, -16; + CHECKREG p1, -17; + CHECKREG p2, -18; + CHECKREG p3, -19; + CHECKREG p4, -20; + CHECKREG p5, -21; + CHECKREG sp, -22; + CHECKREG fp, -23; + + R0 = -24; + P1 = -25; + P2 = -26; + P3 = -27; + P4 = -28; + P5 = -29; + SP = -30; + FP = -31; + CHECKREG r0, -24; + CHECKREG p1, -25; + CHECKREG p2, -26; + CHECKREG p3, -27; + CHECKREG p4, -28; + CHECKREG p5, -29; + CHECKREG sp, -30; + CHECKREG fp, -31; + + R0 = -32; + P1 = -33; + P2 = -34; + P3 = -35; + P4 = -36; + P5 = -37; + SP = -38; + FP = -39; + CHECKREG r0, -32; + CHECKREG p1, -33; + CHECKREG p2, -34; + CHECKREG p3, -35; + CHECKREG p4, -36; + CHECKREG p5, -37; + CHECKREG sp, -38; + CHECKREG fp, -39; + + R0 = -40; + P1 = -41; + P2 = -42; + P3 = -43; + P4 = -44; + P5 = -45; + SP = -46; + FP = -47; + CHECKREG r0, -40; + CHECKREG p1, -41; + CHECKREG p2, -42; + CHECKREG p3, -43; + CHECKREG p4, -44; + CHECKREG p5, -45; + CHECKREG sp, -46; + CHECKREG fp, -47; + + R0 = -48; + P1 = -49; + P2 = -50; + P3 = -51; + P4 = -52; + P5 = -53; + SP = -54; + FP = -55; + CHECKREG r0, -48; + CHECKREG p1, -49; + CHECKREG p2, -50; + CHECKREG p3, -51; + CHECKREG p4, -52; + CHECKREG p5, -53; + CHECKREG sp, -54; + CHECKREG fp, -55; + + R0 = -56; + P1 = -57; + P2 = -58; + P3 = -59; + P4 = -60; + P5 = -61; + SP = -62; + FP = -63; + CHECKREG r0, -56; + CHECKREG p1, -57; + CHECKREG p2, -58; + CHECKREG p3, -59; + CHECKREG p4, -60; + CHECKREG p5, -61; + CHECKREG sp, -62; + CHECKREG fp, -63; + + R0 = -64; + P1 = -64; + P2 = -64; + P3 = -64; + P4 = -64; + P5 = -64; + SP = -64; + FP = -64; + CHECKREG r0, -64; + CHECKREG p1, -64; + CHECKREG p2, -64; + CHECKREG p3, -64; + CHECKREG p4, -64; + CHECKREG p5, -64; + CHECKREG sp, -64; + CHECKREG fp, -64; + + pass diff --git a/sim/testsuite/bfin/c_compi2opp_pr_eq_i7_p.s b/sim/testsuite/bfin/c_compi2opp_pr_eq_i7_p.s new file mode 100644 index 0000000..75433bc --- /dev/null +++ b/sim/testsuite/bfin/c_compi2opp_pr_eq_i7_p.s @@ -0,0 +1,131 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_p/c_compi2opp_pr_eq_i7_p.dsp +// Spec Reference: compi2opd pregs = imm7 positive +# mach: bfin + +.include "testutils.inc" + start + +//R0 = 0; + P1 = 1; + P2 = 2; + P3 = 3; + P4 = 4; + P5 = 5; + SP = 6; + FP = 7; + CHECKREG p1, 1; + CHECKREG p2, 2; + CHECKREG p3, 3; + CHECKREG p4, 4; + CHECKREG p5, 5; + CHECKREG sp, 6; + CHECKREG fp, 7; + + P1 = 9; + P2 = 10; + P3 = 11; + P4 = 12; + P5 = 13; + SP = 14; + FP = 15; + CHECKREG p1, 9; + CHECKREG p2, 10; + CHECKREG p3, 11; + CHECKREG p4, 12; + CHECKREG p5, 13; + CHECKREG sp, 14; + CHECKREG fp, 15; + + P1 = 17; + P2 = 18; + P3 = 19; + P4 = 20; + P5 = 21; + SP = 22; + FP = 23; + CHECKREG p1, 17; + CHECKREG p2, 18; + CHECKREG p3, 19; + CHECKREG p4, 20; + CHECKREG p5, 21; + CHECKREG sp, 22; + CHECKREG fp, 23; + + P1 = 25; + P2 = 26; + P3 = 27; + P4 = 28; + P5 = 29; + SP = 30; + FP = 31; + CHECKREG p1, 25; + CHECKREG p2, 26; + CHECKREG p3, 27; + CHECKREG p4, 28; + CHECKREG p5, 29; + CHECKREG sp, 30; + CHECKREG fp, 31; + + R0 = 32; + P1 = 33; + P2 = 34; + P3 = 35; + P4 = 36; + P5 = 37; + SP = 38; + FP = 39; + CHECKREG r0, 32; + CHECKREG p1, 33; + CHECKREG p2, 34; + CHECKREG p3, 35; + CHECKREG p4, 36; + CHECKREG p5, 37; + CHECKREG sp, 38; + CHECKREG fp, 39; + + P1 = 41; + P2 = 42; + P3 = 43; + P4 = 44; + P5 = 45; + SP = 46; + FP = 47; + CHECKREG p1, 41; + CHECKREG p2, 42; + CHECKREG p3, 43; + CHECKREG p4, 44; + CHECKREG p5, 45; + CHECKREG sp, 46; + CHECKREG fp, 47; + + P1 = 49; + P2 = 50; + P3 = 51; + P4 = 52; + P5 = 53; + SP = 54; + FP = 55; + CHECKREG p1, 49; + CHECKREG p2, 50; + CHECKREG p3, 51; + CHECKREG p4, 52; + CHECKREG p5, 53; + CHECKREG sp, 54; + CHECKREG fp, 55; + + P1 = 57; + P2 = 58; + P3 = 59; + P4 = 60; + P5 = 61; + SP = 62; + FP = 63; + CHECKREG p1, 57; + CHECKREG p2, 58; + CHECKREG p3, 59; + CHECKREG p4, 60; + CHECKREG p5, 61; + CHECKREG sp, 62; + CHECKREG fp, 63; + + pass diff --git a/sim/testsuite/bfin/c_dagmodik_lnz_imgebl.s b/sim/testsuite/bfin/c_dagmodik_lnz_imgebl.s new file mode 100644 index 0000000..cea97ad --- /dev/null +++ b/sim/testsuite/bfin/c_dagmodik_lnz_imgebl.s @@ -0,0 +1,290 @@ +//Original:/testcases/core/c_dagmodik_lnz_imgebl/c_dagmodik_lnz_imgebl.dsp +// Spec Reference: dagmodik l not zero & i+m >= b+l +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x00001000; +imm32 b1, 0x00001000; +imm32 b2, 0x00001000; +imm32 b3, 0x00001000; + +imm32 l0, 0x00000001; +imm32 l1, 0x00000002; +imm32 l2, 0x00000003; +imm32 l3, 0x00000004; + +imm32 m0, 0x00000015; +imm32 m1, 0x00000016; +imm32 m2, 0x00000017; +imm32 m3, 0x00000018; + + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x0000100F; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001002; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x0000100E; +CHECKREG r7, 0x00001001; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x000010FE; +CHECKREG r2, 0x0000100C; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00000FFF; +CHECKREG r5, 0x000010FC; +CHECKREG r6, 0x0000100A; +CHECKREG r7, 0x00001001; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x000010FE; +CHECKREG r2, 0x0000100B; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x00001005; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x0000100C; +CHECKREG r7, 0x00001001; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x00000FFE; +CHECKREG r1, 0x000010F8; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x00001005; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x0000100C; +CHECKREG r7, 0x00001001; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00000FFE; +CHECKREG r1, 0x000010F8; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x00000FF8; +CHECKREG r5, 0x000010F0; +CHECKREG r6, 0x00000FFF; +CHECKREG r7, 0x00001001; + +// i+m = b+l +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x00001000; +imm32 b1, 0x00001100; +imm32 b2, 0x00001010; +imm32 b3, 0x00001001; + +imm32 l0, 0x00000015; +imm32 l1, 0x00000016; +imm32 l2, 0x00000017; +imm32 l3, 0x00000018; + +imm32 m0, 0x00000015; +imm32 m1, 0x00000016; +imm32 m2, 0x00000017; +imm32 m3, 0x00000018; + + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001012; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001104; +CHECKREG r6, 0x00001014; +CHECKREG r7, 0x00001005; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001012; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x00001010; +CHECKREG r7, 0x00001001; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001104; +CHECKREG r2, 0x00001014; +CHECKREG r3, 0x00001005; +CHECKREG r4, 0x00001008; +CHECKREG r5, 0x00001108; +CHECKREG r6, 0x00001018; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x00001010; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x00001008; +CHECKREG r5, 0x00001108; +CHECKREG r6, 0x00001018; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x00001010; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x0000100D; +CHECKREG r5, 0x0000110E; +CHECKREG r6, 0x0000101F; +CHECKREG r7, 0x00001011; + + + +pass diff --git a/sim/testsuite/bfin/c_dagmodik_lnz_imltbl.s b/sim/testsuite/bfin/c_dagmodik_lnz_imltbl.s new file mode 100644 index 0000000..7142682 --- /dev/null +++ b/sim/testsuite/bfin/c_dagmodik_lnz_imltbl.s @@ -0,0 +1,289 @@ +//Original:/testcases/core/c_dagmodik_lnz_imltbl/c_dagmodik_lnz_imltbl.dsp +// Spec Reference: dagmodik l not zero & i+m < b +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x0000100e; +imm32 b1, 0x0000110c; +imm32 b2, 0x0000101a; +imm32 b3, 0x00001008; + +imm32 l0, 0x000000a1; +imm32 l1, 0x000000b2; +imm32 l2, 0x000000c3; +imm32 l3, 0x000000d4; + +imm32 m0, 0x00000005; +imm32 m1, 0x00000004; +imm32 m2, 0x00000003; +imm32 m3, 0x00000002; + + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001012; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001104; +CHECKREG r6, 0x00001014; +CHECKREG r7, 0x00001005; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x000010A3; +CHECKREG r1, 0x000011B4; +CHECKREG r2, 0x000010D5; +CHECKREG r3, 0x000010D7; +CHECKREG r4, 0x000010A1; +CHECKREG r5, 0x000011B2; +CHECKREG r6, 0x000010D3; +CHECKREG r7, 0x000010D5; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x000010A5; +CHECKREG r1, 0x000011B6; +CHECKREG r2, 0x000010D7; +CHECKREG r3, 0x000010D9; +CHECKREG r4, 0x000010A9; +CHECKREG r5, 0x000011BA; +CHECKREG r6, 0x000010DB; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x000010A1; +CHECKREG r1, 0x000011B2; +CHECKREG r2, 0x000010D3; +CHECKREG r3, 0x000010D5; +CHECKREG r4, 0x000010A9; +CHECKREG r5, 0x000011BA; +CHECKREG r6, 0x000010DB; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x000010A1; +CHECKREG r1, 0x000011B2; +CHECKREG r2, 0x000010D3; +CHECKREG r3, 0x000010D5; +CHECKREG r4, 0x00001099; +CHECKREG r5, 0x000011AA; +CHECKREG r6, 0x000010CB; +CHECKREG r7, 0x000010CD; + +// i+m = b+l +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x0000100e; +imm32 b1, 0x0000110c; +imm32 b2, 0x0000101a; +imm32 b3, 0x00001008; + +imm32 l0, 0x00000011; +imm32 l1, 0x00000012; +imm32 l2, 0x00000013; +imm32 l3, 0x00000014; + +imm32 m0, 0x00000002; +imm32 m1, 0x00000003; +imm32 m2, 0x00000004; +imm32 m3, 0x00000005; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001012; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001104; +CHECKREG r6, 0x00001014; +CHECKREG r7, 0x00001005; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001013; +CHECKREG r1, 0x00001114; +CHECKREG r2, 0x00001025; +CHECKREG r3, 0x00001017; +CHECKREG r4, 0x00001011; +CHECKREG r5, 0x00001112; +CHECKREG r6, 0x00001023; +CHECKREG r7, 0x00001015; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001015; +CHECKREG r1, 0x00001116; +CHECKREG r2, 0x00001027; +CHECKREG r3, 0x00001019; +CHECKREG r4, 0x00001019; +CHECKREG r5, 0x0000111A; +CHECKREG r6, 0x0000102B; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x00001011; +CHECKREG r1, 0x00001112; +CHECKREG r2, 0x00001023; +CHECKREG r3, 0x00001015; +CHECKREG r4, 0x00001019; +CHECKREG r5, 0x0000111A; +CHECKREG r6, 0x0000102B; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001011; +CHECKREG r1, 0x00001112; +CHECKREG r2, 0x00001023; +CHECKREG r3, 0x00001015; +CHECKREG r4, 0x0000101A; +CHECKREG r5, 0x0000111C; +CHECKREG r6, 0x0000101B; +CHECKREG r7, 0x0000100D; + + + +pass diff --git a/sim/testsuite/bfin/c_dagmodik_lz_inc_dec.s b/sim/testsuite/bfin/c_dagmodik_lz_inc_dec.s new file mode 100644 index 0000000..64ac946 --- /dev/null +++ b/sim/testsuite/bfin/c_dagmodik_lz_inc_dec.s @@ -0,0 +1,140 @@ +//Original:/testcases/core/c_dagmodik_lz_inc_dec/c_dagmodik_lz_inc_dec.dsp +// Spec Reference: dagmodik L=0, I incremented & decremented +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001200; +imm32 i3, 0x00001300; +imm32 m0, 0x00000000; +imm32 m1, 0x00000110; +imm32 m2, 0x00000210; +imm32 m3, 0x00000310; + + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001202; +CHECKREG r3, 0x00001302; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001104; +CHECKREG r6, 0x00001204; +CHECKREG r7, 0x00001304; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001202; +CHECKREG r3, 0x00001302; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x00001200; +CHECKREG r7, 0x00001300; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001104; +CHECKREG r2, 0x00001204; +CHECKREG r3, 0x00001304; +CHECKREG r4, 0x00001008; +CHECKREG r5, 0x00001108; +CHECKREG r6, 0x00001208; +CHECKREG r7, 0x00001308; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x00001200; +CHECKREG r3, 0x00001300; +CHECKREG r4, 0x00001008; +CHECKREG r5, 0x00001108; +CHECKREG r6, 0x00001208; +CHECKREG r7, 0x00001308; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x00001200; +CHECKREG r3, 0x00001300; +CHECKREG r4, 0x00000FF8; +CHECKREG r5, 0x000010F8; +CHECKREG r6, 0x000011F8; +CHECKREG r7, 0x000012F8; + + + +pass diff --git a/sim/testsuite/bfin/c_dagmodim_lnz_imgebl.s b/sim/testsuite/bfin/c_dagmodim_lnz_imgebl.s new file mode 100644 index 0000000..4189c05 --- /dev/null +++ b/sim/testsuite/bfin/c_dagmodim_lnz_imgebl.s @@ -0,0 +1,108 @@ +//Original:/testcases/core/c_dagmodim_lnz_imgebl/c_dagmodim_lnz_imgebl.dsp +// Spec Reference: dagmodim l not zero & i+m >= b+l +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x00001000; +imm32 b1, 0x00001000; +imm32 b2, 0x00001000; +imm32 b3, 0x00001000; + +imm32 l0, 0x00000001; +imm32 l1, 0x00000002; +imm32 l2, 0x00000003; +imm32 l3, 0x00000004; + +imm32 m0, 0x00000015; +imm32 m1, 0x00000016; +imm32 m2, 0x00000017; +imm32 m3, 0x00000018; + + I0 += M0; + I1 += M1; + I2 += M2; + I3 += M3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M1; + I1 += M2; + I2 += M3; + I3 += M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; + +CHECKREG r0, 0x00001014; +CHECKREG r1, 0x00001114; +CHECKREG r2, 0x00001024; +CHECKREG r3, 0x00001015; +CHECKREG r4, 0x00001029; +CHECKREG r5, 0x00001129; +CHECKREG r6, 0x00001039; +CHECKREG r7, 0x00001026; + + I0 -= M2; + I1 -= M3; + I2 -= M0; + I3 -= M1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= M3; + I1 -= M2; + I2 -= M1; + I3 -= M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001012; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00001024; +CHECKREG r3, 0x00001010; +CHECKREG r4, 0x00000FFB; +CHECKREG r5, 0x000010FA; +CHECKREG r6, 0x0000100E; +CHECKREG r7, 0x00000FFF; + + I0 += M3 (BREV); + I1 += M0 (BREV); + I2 += M1 (BREV); + I3 += M2 (BREV); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M2 (BREV); + I1 += M3 (BREV); + I2 += M0 (BREV); + I3 += M1 (BREV); +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00000FEF; +CHECKREG r1, 0x000010E0; +CHECKREG r2, 0x0000101B; +CHECKREG r3, 0x00000FE7; +CHECKREG r4, 0x00000FFB; +CHECKREG r5, 0x000010F8; +CHECKREG r6, 0x00001001; +CHECKREG r7, 0x00000FF2; + + +pass diff --git a/sim/testsuite/bfin/c_dagmodim_lnz_imltbl.s b/sim/testsuite/bfin/c_dagmodim_lnz_imltbl.s new file mode 100644 index 0000000..152c94b --- /dev/null +++ b/sim/testsuite/bfin/c_dagmodim_lnz_imltbl.s @@ -0,0 +1,109 @@ +//Original:/testcases/core/c_dagmodim_lnz_imltbl/c_dagmodim_lnz_imltbl.dsp +// Spec Reference: dagmodim l not zero & i+m < b +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x0000110e; +imm32 b1, 0x0000110c; +imm32 b2, 0x0000110a; +imm32 b3, 0x00001108; + +imm32 l0, 0x000000a1; +imm32 l1, 0x000000b2; +imm32 l2, 0x000000c3; +imm32 l3, 0x000000d4; + +imm32 m0, 0x00000005; +imm32 m1, 0x00000004; +imm32 m2, 0x00000003; +imm32 m3, 0x00000002; + + I0 += M0; + I1 += M1; + I2 += M2; + I3 += M3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M1; + I1 += M2; + I2 += M3; + I3 += M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001005; +CHECKREG r1, 0x00001104; +CHECKREG r2, 0x00001013; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001009; +CHECKREG r5, 0x00001107; +CHECKREG r6, 0x00001015; +CHECKREG r7, 0x00001008; + + + I0 -= M2; + I1 -= M3; + I2 -= M0; + I3 -= M1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= M3; + I1 -= M2; + I2 -= M1; + I3 -= M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x000010A7; +CHECKREG r1, 0x000011B7; +CHECKREG r2, 0x000010D3; +CHECKREG r3, 0x000010D8; +CHECKREG r4, 0x00001146; +CHECKREG r5, 0x000011B4; +CHECKREG r6, 0x00001192; +CHECKREG r7, 0x000011A7; + + I0 += M3 (BREV); + I1 += M0 (BREV); + I2 += M1 (BREV); + I3 += M2 (BREV); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M2 (BREV); + I1 += M3 (BREV); + I2 += M0 (BREV); + I3 += M1 (BREV); +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001145; +CHECKREG r1, 0x000011B3; +CHECKREG r2, 0x00001196; +CHECKREG r3, 0x000011A5; +CHECKREG r4, 0x00001146; +CHECKREG r5, 0x000011B0; +CHECKREG r6, 0x00001190; +CHECKREG r7, 0x000011A3; + + + +pass diff --git a/sim/testsuite/bfin/c_dagmodim_lz_inc_dec.s b/sim/testsuite/bfin/c_dagmodim_lz_inc_dec.s new file mode 100644 index 0000000..094a7d8 --- /dev/null +++ b/sim/testsuite/bfin/c_dagmodim_lz_inc_dec.s @@ -0,0 +1,98 @@ +//Original:/testcases/core/c_dagmodim_lz_inc_dec/c_dagmodim_lz_inc_dec.dsp +// Spec Reference: dagmodim L=0, I incremented & decremented (by M) +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x10001000; +imm32 i1, 0x02001100; +imm32 i2, 0x00301010; +imm32 i3, 0x00041001; + +imm32 m0, 0x00000005; +imm32 m1, 0x00000006; +imm32 m2, 0x00000007; +imm32 m3, 0x00000008; + + I0 += M0; + I1 += M1; + I2 += M2; + I3 += M3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M1; + I1 += M2; + I2 += M3; + I3 += M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; + +CHECKREG r0, 0x10001005; +CHECKREG r1, 0x02001106; +CHECKREG r2, 0x00301017; +CHECKREG r3, 0x00041009; +CHECKREG r4, 0x1000100B; +CHECKREG r5, 0x0200110D; +CHECKREG r6, 0x0030101F; +CHECKREG r7, 0x0004100E; + + I0 -= M2; + I1 -= M3; + I2 -= M0; + I3 -= M1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= M3; + I1 -= M2; + I2 -= M1; + I3 -= M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x10001004; +CHECKREG r1, 0x02001105; +CHECKREG r2, 0x0030101A; +CHECKREG r3, 0x00041008; +CHECKREG r4, 0x10000FFC; +CHECKREG r5, 0x020010FE; +CHECKREG r6, 0x00301014; +CHECKREG r7, 0x00041003; + + I0 += M3 (BREV); + I1 += M0 (BREV); + I2 += M1 (BREV); + I3 += M2 (BREV); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M2 (BREV); + I1 += M3 (BREV); + I2 += M0 (BREV); + I3 += M1 (BREV); +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x10000FF2; +CHECKREG r1, 0x020010F8; +CHECKREG r2, 0x00301011; +CHECKREG r3, 0x00041005; +CHECKREG r4, 0x10000FF4; +CHECKREG r5, 0x020010F4; +CHECKREG r6, 0x00301014; +CHECKREG r7, 0x00041000; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_a0_pm_a1.s b/sim/testsuite/bfin/c_dsp32alu_a0_pm_a1.s new file mode 100644 index 0000000..dda7ddd --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_a0_pm_a1.s @@ -0,0 +1,39 @@ +//Original:/testcases/core/c_dsp32alu_a0_pm_a1/c_dsp32alu_a0_pm_a1.dsp +// Spec Reference: dsp32alu a0 += a1 +# mach: bfin + +.include "testutils.inc" + start + + + +A1 = A0 = 0; + +imm32 r0, 0x25678911; +imm32 r1, 0x0029ab2d; +imm32 r2, 0x00145535; +imm32 r3, 0xf6567747; +imm32 r4, 0xe566895b; +imm32 r5, 0x67897b6d; +imm32 r6, 0xb4445875; +imm32 r7, 0x86667797; +A0 = R0; +A1 = R1; + +A0 += A1; +A0 += A1 (W32); +A0 += A1; +A0 += A1 (W32); +R5 = A0.w; + +A1 = R2; +A0 -= A1; +A0 -= A1 (W32); +A0 -= A1; +A0 -= A1 (W32); +R6 = A0.w; +CHECKREG r5, 0x260E35C5; +CHECKREG r6, 0x25BCE0F1; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_a0a1s.s b/sim/testsuite/bfin/c_dsp32alu_a0a1s.s new file mode 100644 index 0000000..ee20bb7 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_a0a1s.s @@ -0,0 +1,82 @@ +//Original:/testcases/core/c_dsp32alu_a0a1s/c_dsp32alu_a0a1s.dsp +// Spec Reference: dsp32alu a0a1s +# mach: bfin + +.include "testutils.inc" + start + + + +A1 = A0 = 0; + +imm32 r0, 0x15678911; +imm32 r1, 0xa789ab1d; +imm32 r2, 0xd4445515; +imm32 r3, 0xf6667717; +imm32 r4, 0xe567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0xb4445515; +imm32 r7, 0x86667777; +// A0 & A1 types +A0 = R0; +A1 = R1; + R6 = A0.w; + R7 = A1.w; +A0 = 0; +A1 = 0; + R0 = A0.w; + R1 = A1.w; +A0 = R2; +A1 = R3; +A0 = A0 (S); +A1 = A1 (S); + R4 = A0.w; + R5 = A1.w; +A0 = A1; + R2 = A0.w; +A0 = R3; +A1 = A0; + R3 = A1.w; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xF6667717; +CHECKREG r3, 0xF6667717; +CHECKREG r4, 0xD4445515; +CHECKREG r5, 0xF6667717; +CHECKREG r6, 0x15678911; +CHECKREG r7, 0xA789AB1D; + +A1 = A0 = 0; + R0 = A0.w; + R1 = A1.w; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; + +imm32 r0, 0xa1567891; +imm32 r1, 0xba789abd; +imm32 r2, 0xcd412355; +imm32 r3, 0xdf646777; +imm32 r4, 0xe567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0xb4445515; +imm32 r7, 0xf666aeb7; + +A0 = R4; +A1 = R5; + R0 = A0.w; + R1 = A1.w; +A0 = R6; +A1 = R7; + R2 = A0.w; + R3 = A1.w; +CHECKREG r0, 0xE567891B; +CHECKREG r1, 0x6789AB1D; +CHECKREG r2, 0xB4445515; +CHECKREG r3, 0xF666AEB7; +CHECKREG r4, 0xE567891B; +CHECKREG r5, 0x6789AB1D; +CHECKREG r6, 0xB4445515; +CHECKREG r7, 0xF666AEB7; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_a_abs_a.s b/sim/testsuite/bfin/c_dsp32alu_a_abs_a.s new file mode 100644 index 0000000..3a83972 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_a_abs_a.s @@ -0,0 +1,34 @@ +//Original:/testcases/core/c_dsp32alu_a_abs_a/c_dsp32alu_a_abs_a.dsp +// Spec Reference: dsp32alu a = abs a +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +A1 = A0 = 0; +A0 = R0; + +A0 = ABS A0; +A1 = ABS A0; +A1 = ABS A1; +A0 = ABS A1; +R1 = A0.w; +R2 = A1.w; +CHECKREG r0, 0xA5678911; +CHECKREG r1, 0x5A9876EF; +CHECKREG r2, 0x5A9876EF; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_a_neg_a.s b/sim/testsuite/bfin/c_dsp32alu_a_neg_a.s new file mode 100644 index 0000000..263e900 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_a_neg_a.s @@ -0,0 +1,34 @@ +//Original:/testcases/core/c_dsp32alu_a_neg_a/c_dsp32alu_a_neg_a.dsp +// Spec Reference: dsp32alu a = neg a +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +A1 = A0 = 0; +A0 = R0; + +A0 = - A0; +A1 = - A0; +A1 = - A1; +A0 = - A1; +R1 = A0.w; +R2 = A1.w; +CHECKREG r0, 0xA5678911; +CHECKREG r1, 0xA5678911; +CHECKREG r2, 0x5A9876EF; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_aa_absabs.s b/sim/testsuite/bfin/c_dsp32alu_aa_absabs.s new file mode 100644 index 0000000..fd505f0 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_aa_absabs.s @@ -0,0 +1,35 @@ +//Original:/testcases/core/c_dsp32alu_aa_absabs/c_dsp32alu_aa_absabs.dsp +// Spec Reference: dsp32alu a1, a0 = abs / abs a1, a0 +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +A0 = R0; +A1 = R1; + +A1 = ABS A1, A0 = ABS A0; +R2 = A0.w; +R3 = A1.w; +A1 = ABS A1, A0 = ABS A0; +R4 = A0.w; +R5 = A1.w; +CHECKREG r2, 0x5A9876EF; +CHECKREG r3, 0x2789AB1D; +CHECKREG r4, 0x5A9876EF; +CHECKREG r5, 0x2789AB1D; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_aa_negneg.s b/sim/testsuite/bfin/c_dsp32alu_aa_negneg.s new file mode 100644 index 0000000..4d6f4bf --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_aa_negneg.s @@ -0,0 +1,35 @@ +//Original:/testcases/core/c_dsp32alu_aa_negneg/c_dsp32alu_aa_negneg.dsp +// Spec Reference: dsp32alu a1, a0 = neg / neg a1, a0 +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +A0 = R0; +A1 = R1; + +A1 = - A1, A0 = - A0; +R2 = A0.w; +R3 = A1.w; +A1 = - A1, A0 = - A0; +R4 = A0.w; +R5 = A1.w; +CHECKREG r2, 0x5A9876EF; +CHECKREG r3, 0xD87654E3; +CHECKREG r4, 0xA5678911; +CHECKREG r5, 0x2789AB1D; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_abs.s b/sim/testsuite/bfin/c_dsp32alu_abs.s new file mode 100644 index 0000000..0504a7b --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_abs.s @@ -0,0 +1,62 @@ +//Original:/testcases/core/c_dsp32alu_abs/c_dsp32alu_abs.dsp +// Spec Reference: dsp32alu dregs = abs ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = ABS R0; +R1 = ABS R1; +R2 = ABS R2; +R3 = ABS R3; +R4 = ABS R4; +R5 = ABS R5; +R6 = ABS R6; +R7 = ABS R7; +CHECKREG r0, 0x15678911; +CHECKREG r1, 0x2789AB1D; +CHECKREG r2, 0x34445515; +CHECKREG r3, 0x46667717; +CHECKREG r4, 0x5567891B; +CHECKREG r5, 0x6789AB1D; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x79998889; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = ABS R7; +R1 = ABS R6; +R2 = ABS R5; +R3 = ABS R4; +R4 = ABS R3; +R5 = ABS R2; +R6 = ABS R1; +R7 = ABS R0; +CHECKREG r0, 0x0EEEFFFF; +CHECKREG r1, 0x033322D3; +CHECKREG r2, 0x155544D5; +CHECKREG r3, 0x277766D7; +CHECKREG r4, 0x277766D7; +CHECKREG r5, 0x155544D5; +CHECKREG r6, 0x033322D3; +CHECKREG r7, 0x0EEEFFFF; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_absabs.s b/sim/testsuite/bfin/c_dsp32alu_absabs.s new file mode 100644 index 0000000..bb1cafc --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_absabs.s @@ -0,0 +1,62 @@ +//Original:/testcases/core/c_dsp32alu_absabs/c_dsp32alu_absabs.dsp +// Spec Reference: dsp32alu dregs = abs / abs ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = ABS R0 (V); +R1 = ABS R1 (V); +R2 = ABS R2 (V); +R3 = ABS R3 (V); +R4 = ABS R4 (V); +R5 = ABS R5 (V); +R6 = ABS R6 (V); +R7 = ABS R7 (V); +CHECKREG r0, 0x156776EF; +CHECKREG r1, 0x278954E3; +CHECKREG r2, 0x34445515; +CHECKREG r3, 0x46667717; +CHECKREG r4, 0x556776E5; +CHECKREG r5, 0x678954E3; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x799A7777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = ABS R7 (V); +R1 = ABS R6 (V); +R2 = ABS R5 (V); +R3 = ABS R4 (V); +R4 = ABS R3 (V); +R5 = ABS R2 (V); +R6 = ABS R1 (V); +R7 = ABS R0 (V); +CHECKREG r0, 0x0EEE0001; +CHECKREG r1, 0x033422D3; +CHECKREG r2, 0x155644D5; +CHECKREG r3, 0x277866D7; +CHECKREG r4, 0x277866D7; +CHECKREG r5, 0x155644D5; +CHECKREG r6, 0x033422D3; +CHECKREG r7, 0x0EEE0001; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_alhwx.s b/sim/testsuite/bfin/c_dsp32alu_alhwx.s new file mode 100644 index 0000000..3ca87a7 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_alhwx.s @@ -0,0 +1,128 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_alhwx/c_dsp32alu_alhwx.dsp +// Spec Reference: dsp32alu alhwx +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + A1 = A0 = 0; + + imm32 r0, 0xa5678911; + imm32 r1, 0xaa89ab1d; + imm32 r2, 0xd4b45515; + imm32 r3, 0xf66e7717; + imm32 r4, 0xe567f91b; + imm32 r5, 0x6789ae1d; + imm32 r6, 0xb4445515; + imm32 r7, 0x8666a7d7; + A0.L = R0.L; + A0.H = R0.H; + A0.x = R1.L; + R7 = A0.w; + R6 = A0.x; + R5.L = A0.x; + A1.L = R4.L; + A1.H = R4.H; + A1.x = R3.L; + R0 = A1.w; + R1 = A1.x; + R2.L = A1.x; + CHECKREG r0, 0xE567F91B; + CHECKREG r1, 0x00000017; + CHECKREG r2, 0xD4B40017; + CHECKREG r3, 0xF66E7717; + CHECKREG r4, 0xE567F91B; + CHECKREG r5, 0x6789001D; + CHECKREG r6, 0x0000001D; + CHECKREG r7, 0xA5678911; + + imm32 r0, 0xe5678911; + imm32 r1, 0xaa89ab1d; + imm32 r2, 0xdfb45515; + imm32 r3, 0xf66e7717; + imm32 r4, 0xe5d7f91b; + imm32 r5, 0x67e9ae1d; + imm32 r6, 0xb4445515; + imm32 r7, 0x866aa7b7; + A0.L = R1.L; + A0.H = R1.H; + A0.x = R2.L; + R5 = A0.w; + R7 = A0.x; + R6.L = A0.x; + A1.L = R3.L; + A1.H = R3.H; + A1.x = R4.L; + R1 = A1.w; + R2 = A1.x; + R0.L = A1.x; + CHECKREG r0, 0xE567001B; + CHECKREG r1, 0xF66E7717; + CHECKREG r2, 0x0000001B; + CHECKREG r3, 0xF66E7717; + CHECKREG r4, 0xE5D7F91B; + CHECKREG r5, 0xAA89AB1D; + CHECKREG r6, 0xB4440015; + CHECKREG r7, 0x00000015; + + imm32 r0, 0x35678911; + imm32 r1, 0xa489ab1d; + imm32 r2, 0xd4545515; + imm32 r3, 0xf6667717; + imm32 r4, 0x9567f91b; + imm32 r5, 0x6a89ae1d; + imm32 r6, 0xb4445515; + imm32 r7, 0x8666a7d7; + A0.L = R3.L; + A0.H = R3.H; + A0.x = R4.L; + R0 = A0.w; + R1 = A0.x; + R2.L = A0.x; + A1.L = R5.L; + A1.H = R6.H; + A1.x = R7.L; + R7 = A1.w; + R5 = A1.x; + R5.L = A1.x; + CHECKREG r0, 0xF6667717; + CHECKREG r1, 0x0000001B; + CHECKREG r2, 0xD454001B; + CHECKREG r3, 0xF6667717; + CHECKREG r4, 0x9567F91B; + CHECKREG r5, 0xffffffD7; + CHECKREG r6, 0xB4445515; + CHECKREG r7, 0xB444AE1D; + + imm32 r0, 0xd5678911; + imm32 r1, 0x2a89ab1d; + imm32 r2, 0xd3b45515; + imm32 r3, 0xf66e7717; + imm32 r4, 0xe5d7f91b; + imm32 r5, 0x67e9ae1d; + imm32 r6, 0xb4445515; + imm32 r7, 0x889aa7b7; + A0.L = R4.L; + A0.H = R5.H; + A0.x = R6.L; + R1 = A0.w; + R2 = A0.x; + R3.L = A0.x; + A1.L = R0.L; + A1.H = R0.H; + A1.x = R7.L; + R4 = A1.w; + R5 = A1.x; + R6.L = A1.x; + CHECKREG r0, 0xD5678911; + CHECKREG r1, 0x67E9F91B; + CHECKREG r2, 0x00000015; + CHECKREG r3, 0xF66E0015; + CHECKREG r4, 0xD5678911; + CHECKREG r5, 0xffffffB7; + CHECKREG r6, 0xB444ffB7; + CHECKREG r7, 0x889AA7B7; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_awx.s b/sim/testsuite/bfin/c_dsp32alu_awx.s new file mode 100644 index 0000000..652264c --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_awx.s @@ -0,0 +1,61 @@ +//Original:/testcases/core/c_dsp32alu_awx/c_dsp32alu_awx.dsp +// Spec Reference: dsp32alu awx +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +// A0 & A1 types +A0 = 0; +A1 = 0; + +A0.L = R0.L; +A0.H = R0.H; +A0.x = R2.L; +R3 = A0.w; +R4 = A1.w; +R5.L = A0.x; +//rl6 = a1x; +CHECKREG r3, 0x15678911; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x67890015; +//CHECKREG r6, 0x74440000; + +R5 = ( A0 += A1 ); +R6.L = ( A0 += A1 ); +R7.H = ( A0 += A1 ); +CHECKREG r5, 0x7FFFFFFF; +CHECKREG r6, 0x74447FFF; +CHECKREG r7, 0x7FFF7777; + +A0 += A1; +R0 = A0.w; +CHECKREG r0, 0x15678911; + +A0 -= A1; +R1 = A0.w; +CHECKREG r1, 0x15678911; + +R2 = A1.L + A1.H, R3 = A0.L + A0.H; /* 0x */ +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xFFFF9E78; + +A0 = A1; +R4 = A0.w; +R5 = A1.w; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_byteop1ew.s b/sim/testsuite/bfin/c_dsp32alu_byteop1ew.s new file mode 100644 index 0000000..ff20a19 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_byteop1ew.s @@ -0,0 +1,136 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop1ew/c_dsp32alu_byteop1ew.dsp +// Spec Reference: dsp32alu byteop1ew +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86667777; + R4 = BYTEOP1P ( R1:0 , R3:2 ); + R5 = BYTEOP1P ( R1:0 , R3:2 ) (R); + R6 = BYTEOP1P ( R1:0 , R3:2 ) (T); + R7 = BYTEOP1P ( R1:0 , R3:2 ) (T , R); + R0 = BYTEOP1P ( R1:0 , R3:2 ) (T , R); + CHECKREG r4, 0x25566F13; + CHECKREG r5, 0x3778911A; + CHECKREG r6, 0x24556F13; + CHECKREG r7, 0x3677911A; + CHECKREG r0, 0x3677911A; + + imm32 r0, 0x1567892b; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445525; + imm32 r3, 0x46667727; + imm32 r4, 0x58889929; + imm32 r5, 0x6aaabb2b; + imm32 r6, 0x7cccdd2d; + imm32 r7, 0x8eeeffff; + R0 = BYTEOP1P ( R3:2 , R1:0 ); + R1 = BYTEOP1P ( R3:2 , R1:0 ) (R); + R2 = BYTEOP1P ( R3:2 , R1:0 ) (T); + R3 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); + R4 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); + R5 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); + R6 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); + R7 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); + CHECKREG r0, 0x25566F28; + CHECKREG r1, 0x3778912A; + CHECKREG r2, 0x2C4D6226; + CHECKREG r3, 0x3E6F8428; + CHECKREG r4, 0x3A738A29; + CHECKREG r5, 0x3A738A29; + CHECKREG r6, 0x3A738A29; + CHECKREG r7, 0x3A738A29; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r0, 0x456789ab; + imm32 r1, 0x6689abcd; + imm32 r2, 0x47445555; + imm32 r3, 0x68667777; + ( R1 , R2 ) = BYTEOP16P ( R1:0 , R3:2 ); + ( R0 , R3 ) = BYTEOP16P ( R1:0 , R3:2 ) (R); + ( R4 , R5 ) = BYTEOP16P ( R3:2 , R1:0 ); + ( R6 , R7 ) = BYTEOP16P ( R3:2 , R1:0 ); + CHECKREG r0, 0x006800F2; + CHECKREG r1, 0x008C00AB; + CHECKREG r2, 0x00DE0100; + CHECKREG r3, 0x00770122; + CHECKREG r4, 0x00000146; + CHECKREG r5, 0x000100F2; + CHECKREG r6, 0x00000146; + CHECKREG r7, 0x000100F2; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r0, 0x456789ab; + imm32 r1, 0x6689abcd; + imm32 r2, 0x47445555; + imm32 r3, 0x68667777; + ( R7 , R6 ) = BYTEOP16P ( R3:2 , R1:0 ); + ( R5 , R4 ) = BYTEOP16P ( R3:2 , R1:0 ) (R); + ( R2 , R3 ) = BYTEOP16P ( R3:2 , R1:0 ); + ( R1 , R0 ) = BYTEOP16P ( R3:2 , R1:0 ); + CHECKREG r0, 0x00890156; + CHECKREG r1, 0x004500F3; + CHECKREG r2, 0x008C00AB; + CHECKREG r3, 0x00DE0100; + CHECKREG r4, 0x01220144; + CHECKREG r5, 0x00CE00EF; + CHECKREG r6, 0x00DE0100; + CHECKREG r7, 0x008C00AB; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r0, 0x456789ab; + imm32 r1, 0x6689abcd; + imm32 r2, 0x47445555; + imm32 r3, 0x68667777; + ( R1 , R2 ) = BYTEOP16M ( R1:0 , R3:2 ); + ( R0 , R3 ) = BYTEOP16M ( R1:0 , R3:2 ) (R); + ( R4 , R5 ) = BYTEOP16M ( R3:2 , R1:0 ); + ( R6 , R7 ) = BYTEOP16M ( R3:2 , R1:0 ); + CHECKREG r0, 0x00970098; + CHECKREG r1, 0xFFFE0023; + CHECKREG r2, 0x00340056; + CHECKREG r3, 0xFF89FFAC; + CHECKREG r4, 0x0000FF9D; + CHECKREG r5, 0x0000FFBE; + CHECKREG r6, 0x0000FF9D; + CHECKREG r7, 0x0000FFBE; + + imm32 r0, 0x516789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x73445555; + imm32 r3, 0x84667777; + imm32 r0, 0x956789ab; + imm32 r1, 0xa689abcd; + imm32 r2, 0xb7445555; + imm32 r3, 0xc86def77; + ( R7 , R6 ) = BYTEOP16M ( R3:2 , R1:0 ); + ( R5 , R4 ) = BYTEOP16M ( R3:2 , R1:0 ) (R); + ( R2 , R3 ) = BYTEOP16M ( R3:2 , R1:0 ); + ( R1 , R0 ) = BYTEOP16M ( R3:2 , R1:0 ); + CHECKREG r0, 0x00760032; + CHECKREG r1, 0xFF6BFFBB; + CHECKREG r2, 0x0022FFDD; + CHECKREG r3, 0xFFCCFFAA; + CHECKREG r4, 0x0044FFAA; + CHECKREG r5, 0x0022FFE4; + CHECKREG r6, 0xFFCCFFAA; + CHECKREG r7, 0x0022FFDD; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_byteop2.s b/sim/testsuite/bfin/c_dsp32alu_byteop2.s new file mode 100644 index 0000000..544a5bd --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_byteop2.s @@ -0,0 +1,76 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop2/c_dsp32alu_byteop2.dsp +// Spec Reference: dsp32alu byteop2 +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86667777; + R4 = BYTEOP2P ( R1:0 , R3:2 ) (RNDL); + R5 = BYTEOP2P ( R1:0 , R3:2 ) (RNDL , R); + R6 = BYTEOP2P ( R1:0 , R3:2 ) (RNDH); + R7 = BYTEOP2P ( R1:0 , R3:2 ) (RNDH , R); + CHECKREG r4, 0x003D0041; + CHECKREG r5, 0x00570056; + CHECKREG r6, 0x3D004100; + CHECKREG r7, 0x57005600; + + imm32 r0, 0x1567892b; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445525; + imm32 r3, 0x46667727; + imm32 r4, 0x58889929; + imm32 r5, 0x6aaabb2b; + imm32 r6, 0x7cccdd2d; + imm32 r7, 0x8eeeffff; + R0 = BYTEOP2P ( R3:2 , R1:0 ) (RNDL); + R1 = BYTEOP2P ( R3:2 , R1:0 ) (RNDL , R); + R2 = BYTEOP2P ( R3:2 , R1:0 ) (RNDH); + R3 = BYTEOP2P ( R3:2 , R1:0 ) (RNDH , R); + CHECKREG r0, 0x003D004C; + CHECKREG r1, 0x0057005E; + CHECKREG r2, 0x2D003200; + CHECKREG r3, 0x41003F00; + + imm32 r0, 0x716789ab; + imm32 r1, 0x8289abcd; + imm32 r2, 0x93445555; + imm32 r3, 0xa4667777; + imm32 r4, 0xb56789ab; + imm32 r5, 0xd689abcd; + imm32 r6, 0xe7445555; + imm32 r7, 0x6f661235; + R4 = BYTEOP2P ( R1:0 , R3:2 ) (TL); + R5 = BYTEOP2P ( R1:0 , R3:2 ) (TL , R); + R6 = BYTEOP2P ( R1:0 , R3:2 ) (TH); + R7 = BYTEOP2P ( R1:0 , R3:2 ) (TH , R); + CHECKREG r4, 0x006B0077; + CHECKREG r5, 0x00850099; + CHECKREG r6, 0x6B007700; + CHECKREG r7, 0x85009900; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r4, 0x456789ab; + imm32 r5, 0x6689abcd; + imm32 r6, 0x47445555; + imm32 r7, 0x68667777; + R0 = BYTEOP2P ( R3:2 , R1:0 ) (TL); + R1 = BYTEOP2P ( R3:2 , R1:0 ) (TL , R); + R2 = BYTEOP2P ( R3:2 , R1:0 ) (TH); + R3 = BYTEOP2P ( R3:2 , R1:0 ) (TH , R); + CHECKREG r0, 0x004B0077; + CHECKREG r1, 0x006D0099; + CHECKREG r2, 0x34004800; + CHECKREG r3, 0x4D006100; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_byteop3.s b/sim/testsuite/bfin/c_dsp32alu_byteop3.s new file mode 100644 index 0000000..af32c06 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_byteop3.s @@ -0,0 +1,76 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop3/c_dsp32alu_byteop3.dsp +// Spec Reference: dsp32alu byteop3 +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86667777; + R4 = BYTEOP3P ( R1:0 , R3:2 ) (LO); + R5 = BYTEOP3P ( R1:0 , R3:2 ) (HI); + R6 = BYTEOP3P ( R1:0 , R3:2 ) (LO); + R7 = BYTEOP3P ( R1:0 , R3:2 ) (HI); + CHECKREG r4, 0x00FF0000; + CHECKREG r5, 0xFF000000; + CHECKREG r6, 0x00FF0000; + CHECKREG r7, 0xFF000000; + + imm32 r0, 0x1567892b; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445525; + imm32 r3, 0x46667727; + imm32 r4, 0x58889929; + imm32 r5, 0x6aaabb2b; + imm32 r6, 0x7cccdd2d; + imm32 r7, 0x8eeeffff; + R0 = BYTEOP3P ( R3:2 , R1:0 ) (LO); + R1 = BYTEOP3P ( R3:2 , R1:0 ) (LO); + R2 = BYTEOP3P ( R3:2 , R1:0 ) (HI); + R3 = BYTEOP3P ( R3:2 , R1:0 ) (HI); + CHECKREG r0, 0x00FF00FF; + CHECKREG r1, 0x00FF00FF; + CHECKREG r2, 0xFF00FF00; + CHECKREG r3, 0x00000000; + + imm32 r0, 0x716789ab; + imm32 r1, 0x8289abcd; + imm32 r2, 0x93445555; + imm32 r3, 0xa4667777; + imm32 r4, 0xb56789ab; + imm32 r5, 0xd689abcd; + imm32 r6, 0xe7445555; + imm32 r7, 0x6f661235; + R4 = BYTEOP3P ( R1:0 , R3:2 ) (LO); + R5 = BYTEOP3P ( R1:0 , R3:2 ) (LO); + R6 = BYTEOP3P ( R1:0 , R3:2 ) (HI); + R7 = BYTEOP3P ( R1:0 , R3:2 ) (HI); + CHECKREG r4, 0x00FF0000; + CHECKREG r5, 0x00FF0000; + CHECKREG r6, 0xFF000000; + CHECKREG r7, 0xFF000000; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r4, 0x456789ab; + imm32 r5, 0x6689abcd; + imm32 r6, 0x47445555; + imm32 r7, 0x68667777; + R0 = BYTEOP3P ( R3:2 , R1:0 ) (LO); + R1 = BYTEOP3P ( R3:2 , R1:0 ) (LO); + R2 = BYTEOP3P ( R3:2 , R1:0 ) (HI); + R3 = BYTEOP3P ( R3:2 , R1:0 ) (HI); + CHECKREG r0, 0x00FF00FF; + CHECKREG r1, 0x00FF00FF; + CHECKREG r2, 0xFF00FF00; + CHECKREG r3, 0x00000000; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_bytepack.s b/sim/testsuite/bfin/c_dsp32alu_bytepack.s new file mode 100644 index 0000000..731a692 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_bytepack.s @@ -0,0 +1,77 @@ +//Original:/testcases/core/c_dsp32alu_bytepack/c_dsp32alu_bytepack.dsp +// Spec Reference: dsp32alu bytepack +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R4 = BYTEPACK ( R0 , R0 ); +R5 = BYTEPACK ( R0 , R1 ); +R6 = BYTEPACK ( R0 , R2 ); +R7 = BYTEPACK ( R0 , R3 ); +CHECKREG r4, 0x67116711; +CHECKREG r5, 0x891D6711; +CHECKREG r6, 0x44156711; +CHECKREG r7, 0x66176711; + +imm32 r0, 0x1567892b; +imm32 r1, 0x2789ab2d; +imm32 r2, 0x34445525; +imm32 r3, 0x46667727; +imm32 r4, 0x58889929; +imm32 r5, 0x6aaabb2b; +imm32 r6, 0x7cccdd2d; +imm32 r7, 0x8eeeffff; +R4 = BYTEPACK ( R1 , R4 ); +R5 = BYTEPACK ( R1 , R5 ); +R6 = BYTEPACK ( R1 , R6 ); +R7 = BYTEPACK ( R1 , R7 ); +CHECKREG r4, 0x8829892D; +CHECKREG r5, 0xAA2B892D; +CHECKREG r6, 0xCC2D892D; +CHECKREG r7, 0xEEFF892D; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r0, 0x456789ab; +imm32 r1, 0x6689abcd; +imm32 r2, 0x47445555; +imm32 r3, 0x68667777; +R4 = BYTEPACK ( R2 , R0 ); +R5 = BYTEPACK ( R2 , R1 ); +R6 = BYTEPACK ( R2 , R2 ); +R7 = BYTEPACK ( R2 , R3 ); +CHECKREG r4, 0x67AB4455; +CHECKREG r5, 0x89CD4455; +CHECKREG r6, 0x44554455; +CHECKREG r7, 0x66774455; + +imm32 r0, 0x496789ab; +imm32 r1, 0x6489abcd; +imm32 r2, 0x4b445555; +imm32 r3, 0x6c647777; +imm32 r4, 0x8d889999; +imm32 r5, 0xaeaa4bbb; +imm32 r6, 0xcfccd44d; +imm32 r7, 0xe1eefff4; +R4 = BYTEPACK ( R3 , R4 ); +R5 = BYTEPACK ( R3 , R5 ); +R6 = BYTEPACK ( R3 , R6 ); +R7 = BYTEPACK ( R3 , R7 ); +CHECKREG r4, 0x88996477; +CHECKREG r5, 0xAABB6477; +CHECKREG r6, 0xCC4D6477; +CHECKREG r7, 0xEEF46477; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_byteunpack.s b/sim/testsuite/bfin/c_dsp32alu_byteunpack.s new file mode 100644 index 0000000..95fa30a --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_byteunpack.s @@ -0,0 +1,113 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteunpack/c_dsp32alu_byteunpack.dsp +// Spec Reference: dsp32alu byteunpack +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86667777; + ( R4 , R5 ) = BYTEUNPACK R1:0; + ( R1 , R3 ) = BYTEUNPACK R1:0; + ( R0 , R7 ) = BYTEUNPACK R1:0; + ( R6 , R2 ) = BYTEUNPACK R1:0; + CHECKREG r0, 0x00150067; + CHECKREG r1, 0x00150067; + CHECKREG r2, 0x00000067; + CHECKREG r3, 0x00890011; + CHECKREG r4, 0x00150067; + CHECKREG r5, 0x00890011; + CHECKREG r6, 0x00000015; + CHECKREG r7, 0x00890011; + + imm32 r0, 0x1567892b; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445525; + imm32 r3, 0x46667727; + imm32 r4, 0x58889929; + imm32 r5, 0x6aaabb2b; + imm32 r6, 0x7cccdd2d; + imm32 r7, 0x8eeeffff; + ( R1 , R0 ) = BYTEUNPACK R3:2; + ( R3 , R4 ) = BYTEUNPACK R3:2; + ( R5 , R2 ) = BYTEUNPACK R3:2; + ( R7 , R6 ) = BYTEUNPACK R3:2; + CHECKREG r0, 0x00550025; + CHECKREG r1, 0x00340044; + CHECKREG r2, 0x00550025; + CHECKREG r3, 0x00340044; + CHECKREG r4, 0x00550025; + CHECKREG r5, 0x00340044; + CHECKREG r6, 0x00000025; + CHECKREG r7, 0x00000055; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r0, 0x456789ab; + imm32 r1, 0x6689abcd; + imm32 r2, 0x47445555; + imm32 r3, 0x68667777; + ( R1 , R2 ) = BYTEUNPACK R1:0 (R); + ( R3 , R6 ) = BYTEUNPACK R1:0 (R); + ( R4 , R0 ) = BYTEUNPACK R1:0 (R); + ( R5 , R7 ) = BYTEUNPACK R1:0 (R); + CHECKREG r0, 0x00000089; + CHECKREG r1, 0x00660089; + CHECKREG r2, 0x00AB00CD; + CHECKREG r3, 0x00000066; + CHECKREG r4, 0x00000066; + CHECKREG r5, 0x00000066; + CHECKREG r6, 0x00000089; + CHECKREG r7, 0x00000089; + + imm32 r0, 0x496789ab; + imm32 r1, 0x6489abcd; + imm32 r2, 0x4b445555; + imm32 r3, 0x6c647777; + imm32 r4, 0x8d889999; + imm32 r5, 0xaeaa4bbb; + imm32 r6, 0xcfccd44d; + imm32 r7, 0xe1eefff4; + ( R0 , R1 ) = BYTEUNPACK R3:2 (R); + ( R2 , R3 ) = BYTEUNPACK R3:2 (R); + ( R4 , R5 ) = BYTEUNPACK R3:2 (R); + ( R6 , R7 ) = BYTEUNPACK R3:2 (R); + CHECKREG r0, 0x006C0064; + CHECKREG r1, 0x00770077; + CHECKREG r2, 0x006C0064; + CHECKREG r3, 0x00770077; + CHECKREG r4, 0x00000077; + CHECKREG r5, 0x00000077; + CHECKREG r6, 0x00000077; + CHECKREG r7, 0x00000077; + + imm32 r0, 0x4537891b; + imm32 r1, 0x6759ab2d; + imm32 r2, 0x44555535; + imm32 r3, 0x66665747; + imm32 r4, 0x88789565; + imm32 r5, 0xaa8abb5b; + imm32 r6, 0xcc9cdd85; + imm32 r7, 0xeeaeff9f; + ( R0 , R1 ) = BYTEUNPACK R1:0; + ( R2 , R3 ) = BYTEUNPACK R3:2 (R); + ( R4 , R5 ) = BYTEUNPACK R1:0 (R); + ( R6 , R7 ) = BYTEUNPACK R3:2; + CHECKREG r0, 0x00450037; + CHECKREG r1, 0x0089001B; + CHECKREG r2, 0x00660066; + CHECKREG r3, 0x00570047; + CHECKREG r4, 0x00000089; + CHECKREG r5, 0x0000001B; + CHECKREG r6, 0x00000066; + CHECKREG r7, 0x00000066; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_disalnexcpt.s b/sim/testsuite/bfin/c_dsp32alu_disalnexcpt.s new file mode 100644 index 0000000..ef5d916 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_disalnexcpt.s @@ -0,0 +1,255 @@ +//Original:/testcases/core/c_dsp32alu_disalnexcpt/c_dsp32alu_disalnexcpt.dsp +// Spec Reference: c_dsp32alu_disalgnexcpt +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym P0, DATA1; + P0 += 1; I0 = P0; + loadsym P0, DATA2; + P0 += 1; I1 = P0; + loadsym P0, DATA3; + P0 += 1; I2 = P0; + loadsym P0, DATA4; + P0 += 1; I3 = P0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I1 ++ ]; + DISALGNEXCPT || NOP || R2 = [ I2 ++ ]; + DISALGNEXCPT || NOP || R3 = [ I3 ++ ]; + DISALGNEXCPT || NOP || R4 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R5 = [ I1 ++ ]; + DISALGNEXCPT || NOP || R6 = [ I2 ++ ]; + DISALGNEXCPT || NOP || R7 = [ I3 ++ ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x04050607; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x44454647; + CHECKREG r7, 0x64656667; + +// reverse to minus mninus i-- + DISALGNEXCPT || NOP || R0 = [ I0 -- ]; + DISALGNEXCPT || NOP || R1 = [ I1 -- ]; + DISALGNEXCPT || NOP || R2 = [ I2 -- ]; + DISALGNEXCPT || NOP || R3 = [ I3 -- ]; + DISALGNEXCPT || NOP || R4 = [ I0 -- ]; + DISALGNEXCPT || NOP || R5 = [ I1 -- ]; + DISALGNEXCPT || NOP || R6 = [ I2 -- ]; + DISALGNEXCPT || NOP || R7 = [ I3 -- ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x28292A2B; + CHECKREG r2, 0x48494A4B; + CHECKREG r3, 0x68696A6B; + CHECKREG r4, 0x04050607; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x44454647; + CHECKREG r7, 0x64656667; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + +DATA2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + +DATA3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + +DATA4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + +DATA5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xBC0DBE26 + +DATA6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dsp32alu_max.s b/sim/testsuite/bfin/c_dsp32alu_max.s new file mode 100644 index 0000000..74d36f9 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_max.s @@ -0,0 +1,261 @@ +//Original:/testcases/core/c_dsp32alu_max/c_dsp32alu_max.dsp +// Spec Reference: dsp32alu dregs = max ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x85678911; +imm32 r1, 0x9789ab1d; +imm32 r2, 0xa4445b15; +imm32 r3, 0x46667717; +imm32 r4, 0xd567f91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = MAX ( R0 , R0 ); +R1 = MAX ( R0 , R1 ); +R2 = MAX ( R0 , R2 ); +R3 = MAX ( R0 , R3 ); +R4 = MAX ( R0 , R4 ); +R5 = MAX ( R0 , R5 ); +R6 = MAX ( R0 , R6 ); +R7 = MAX ( R0 , R7 ); +CHECKREG r0, 0x85678911; +CHECKREG r1, 0x9789AB1D; +CHECKREG r2, 0xA4445B15; +CHECKREG r3, 0x46667717; +CHECKREG r4, 0xD567F91B; +CHECKREG r5, 0x6789AB1D; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x86667777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = MAX ( R1 , R0 ); +R1 = MAX ( R1 , R1 ); +R2 = MAX ( R1 , R2 ); +R3 = MAX ( R1 , R3 ); +R4 = MAX ( R1 , R4 ); +R5 = MAX ( R1 , R5 ); +R6 = MAX ( R1 , R6 ); +R7 = MAX ( R1 , R7 ); +CHECKREG r0, 0xA789AB2D; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xB4445525; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0xD8889929; +CHECKREG r5, 0xEAAABB2B; +CHECKREG r6, 0xFCCCDD2D; +CHECKREG r7, 0x0EEEFFFF; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r4, 0x456789ab; +imm32 r5, 0x6689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = MAX ( R2 , R0 ); +R1 = MAX ( R2 , R1 ); +R2 = MAX ( R2 , R2 ); +R3 = MAX ( R2 , R3 ); +R4 = MAX ( R2 , R4 ); +R5 = MAX ( R2 , R5 ); +R6 = MAX ( R2 , R6 ); +R7 = MAX ( R2 , R7 ); +CHECKREG r0, 0x43445555; +CHECKREG r1, 0x6289ABCD; +CHECKREG r2, 0x43445555; +CHECKREG r3, 0x64667777; +CHECKREG r4, 0x456789AB; +CHECKREG r5, 0x6689ABCD; +CHECKREG r6, 0x47445555; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = MAX ( R3 , R0 ); +R1 = MAX ( R3 , R1 ); +R2 = MAX ( R3 , R2 ); +R3 = MAX ( R3 , R3 ); +R4 = MAX ( R3 , R4 ); +R5 = MAX ( R3 , R5 ); +R6 = MAX ( R3 , R6 ); +R7 = MAX ( R3 , R7 ); +CHECKREG r0, 0xC6667727; +CHECKREG r1, 0xC6667727; +CHECKREG r2, 0xC6667727; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0x456789AB; +CHECKREG r5, 0x6689ABCD; +CHECKREG r6, 0x47445555; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x5537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x74555535; +imm32 r3, 0x86665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = MAX ( R4 , R0 ); +R1 = MAX ( R4 , R1 ); +R2 = MAX ( R4 , R2 ); +R3 = MAX ( R4 , R3 ); +R4 = MAX ( R4 , R4 ); +R5 = MAX ( R4 , R5 ); +R6 = MAX ( R4 , R6 ); +R7 = MAX ( R4 , R7 ); +CHECKREG r0, 0x5537891B; +CHECKREG r1, 0x6759AB2D; +CHECKREG r2, 0x74555535; +CHECKREG r3, 0x88789565; +CHECKREG r4, 0x88789565; +CHECKREG r5, 0xAA8ABB5B; +CHECKREG r6, 0xCC9CDD85; +CHECKREG r7, 0xEEAEFF9F; + +imm32 r0, 0x556b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x79736564; +imm32 r3, 0x81278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = MAX ( R5 , R0 ); +R1 = MAX ( R5 , R1 ); +R2 = MAX ( R5 , R2 ); +R3 = MAX ( R5 , R3 ); +R4 = MAX ( R5 , R4 ); +R5 = MAX ( R5 , R5 ); +R6 = MAX ( R5 , R6 ); +R7 = MAX ( R5 , R7 ); +CHECKREG r0, 0x556B89AB; +CHECKREG r1, 0x69764BCD; +CHECKREG r2, 0x79736564; +CHECKREG r3, 0xAAAA0BBB; +CHECKREG r4, 0xAAAA0BBB; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0xCCCC1DDD; +CHECKREG r7, 0x12346FFF; + +imm32 r0, 0xe56739ab; +imm32 r1, 0xf7694bcd; +imm32 r2, 0xa3456755; +imm32 r3, 0x66666777; +imm32 r4, 0x42345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = MAX ( R6 , R0 ); +R1 = MAX ( R6 , R1 ); +R2 = MAX ( R6 , R2 ); +R3 = MAX ( R6 , R3 ); +R4 = MAX ( R6 , R4 ); +R5 = MAX ( R6 , R5 ); +R6 = MAX ( R6 , R6 ); +R7 = MAX ( R6 , R7 ); +CHECKREG r0, 0x043290D6; +CHECKREG r1, 0x043290D6; +CHECKREG r2, 0x043290D6; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x42345699; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x043290D6; +CHECKREG r7, 0x1234567F; + +imm32 r0, 0x576789ab; +imm32 r1, 0xd779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xf9ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = MAX ( R7 , R0 ); +R1 = MAX ( R7 , R1 ); +R2 = MAX ( R7 , R2 ); +R3 = MAX ( R7 , R3 ); +R4 = MAX ( R7 , R4 ); +R5 = MAX ( R7 , R5 ); +R6 = MAX ( R7 , R6 ); +R7 = MAX ( R7 , R7 ); +CHECKREG r0, 0x576789AB; +CHECKREG r1, 0xD779ABCD; +CHECKREG r2, 0x23456755; +CHECKREG r3, 0x56789007; +CHECKREG r4, 0x789AB799; +CHECKREG r5, 0xABCD2FF7; +CHECKREG r6, 0xF9AB1D7D; +CHECKREG r7, 0xABCD2FF7; +imm32 r0, 0xe56739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0xd3456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = MAX ( R4 , R7 ); +R5 = MAX ( R5 , R5 ); +R2 = MAX ( R6 , R3 ); +R6 = MAX ( R0 , R4 ); +R0 = MAX ( R1 , R6 ); +R2 = MAX ( R2 , R1 ); +R1 = MAX ( R3 , R0 ); +R7 = MAX ( R7 , R4 ); +CHECKREG r0, 0x67694BCD; +CHECKREG r1, 0x67694BCD; +CHECKREG r2, 0x67694BCD; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x12345699; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x12345699; +CHECKREG r7, 0x12345699; + +imm32 r0, 0xd76789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0xe3456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = MAX ( R4 , R0 ); +R5 = MAX ( R5 , R1 ); +R2 = MAX ( R2 , R2 ); +R7 = MAX ( R7 , R3 ); +R4 = MAX ( R3 , R4 ); +R0 = MAX ( R1 , R5 ); +R1 = MAX ( R0 , R6 ); +R6 = MAX ( R6 , R7 ); +CHECKREG r0, 0x6779ABCD; +CHECKREG r1, 0x6779ABCD; +CHECKREG r2, 0xE3456755; +CHECKREG r3, 0x789AB799; +CHECKREG r4, 0x789AB799; +CHECKREG r5, 0x6779ABCD; +CHECKREG r6, 0x789AB799; +CHECKREG r7, 0x789AB799; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_maxmax.s b/sim/testsuite/bfin/c_dsp32alu_maxmax.s new file mode 100644 index 0000000..8e39d22 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_maxmax.s @@ -0,0 +1,261 @@ +//Original:/testcases/core/c_dsp32alu_maxmax/c_dsp32alu_maxmax.dsp +// Spec Reference: dsp32alu dregs = max / max ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x25678911; +imm32 r1, 0x2389ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0xe6657717; +imm32 r4, 0x5a67891b; +imm32 r5, 0x67b9ab1d; +imm32 r6, 0x744d5515; +imm32 r7, 0x8666c777; +R0 = MAX ( R0 , R0 ) (V); +R1 = MAX ( R0 , R1 ) (V); +R2 = MAX ( R0 , R2 ) (V); +R3 = MAX ( R0 , R3 ) (V); +R4 = MAX ( R0 , R4 ) (V); +R5 = MAX ( R0 , R5 ) (V); +R6 = MAX ( R0 , R6 ) (V); +R7 = MAX ( R0 , R7 ) (V); +CHECKREG r0, 0x25678911; +CHECKREG r1, 0x2567AB1D; +CHECKREG r2, 0x34445515; +CHECKREG r3, 0x25677717; +CHECKREG r4, 0x5A67891B; +CHECKREG r5, 0x67B9AB1D; +CHECKREG r6, 0x744D5515; +CHECKREG r7, 0x2567C777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = MAX ( R1 , R0 ) (V); +R1 = MAX ( R1 , R1 ) (V); +R2 = MAX ( R1 , R2 ) (V); +R3 = MAX ( R1 , R3 ) (V); +R4 = MAX ( R1 , R4 ) (V); +R5 = MAX ( R1 , R5 ) (V); +R6 = MAX ( R1 , R6 ) (V); +R7 = MAX ( R1 , R7 ) (V); +CHECKREG r0, 0xA789AB2D; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xB4445525; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0xD888AB2D; +CHECKREG r5, 0xEAAABB2B; +CHECKREG r6, 0xFCCCDD2D; +CHECKREG r7, 0x0EEEFFFF; + +imm32 r0, 0x416789ab; +imm32 r1, 0x5289abcd; +imm32 r2, 0x63445555; +imm32 r3, 0xa7669777; +imm32 r4, 0x456789ab; +imm32 r5, 0xb689abcd; +imm32 r6, 0xd7445555; +imm32 r7, 0x68667777; +R0 = MAX ( R2 , R0 ) (V); +R1 = MAX ( R2 , R1 ) (V); +R2 = MAX ( R2 , R2 ) (V); +R3 = MAX ( R2 , R3 ) (V); +R4 = MAX ( R2 , R4 ) (V); +R5 = MAX ( R2 , R5 ) (V); +R6 = MAX ( R2 , R6 ) (V); +R7 = MAX ( R2 , R7 ) (V); +CHECKREG r0, 0x63445555; +CHECKREG r1, 0x63445555; +CHECKREG r2, 0x63445555; +CHECKREG r3, 0x63445555; +CHECKREG r4, 0x63445555; +CHECKREG r5, 0x63445555; +CHECKREG r6, 0x63445555; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = MAX ( R3 , R0 ) (V); +R1 = MAX ( R3 , R1 ) (V); +R2 = MAX ( R3 , R2 ) (V); +R3 = MAX ( R3 , R3 ) (V); +R4 = MAX ( R3 , R4 ) (V); +R5 = MAX ( R3 , R5 ) (V); +R6 = MAX ( R3 , R6 ) (V); +R7 = MAX ( R3 , R7 ) (V); +CHECKREG r0, 0xC6667727; +CHECKREG r1, 0xC6667727; +CHECKREG r2, 0xC6667727; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0x63447727; +CHECKREG r5, 0x63447727; +CHECKREG r6, 0x63447727; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x4537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x44555535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = MAX ( R4 , R0 ) (V); +R1 = MAX ( R4 , R1 ) (V); +R2 = MAX ( R4 , R2 ) (V); +R3 = MAX ( R4 , R3 ) (V); +R4 = MAX ( R4 , R4 ) (V); +R5 = MAX ( R4 , R5 ) (V); +R6 = MAX ( R4 , R6 ) (V); +R7 = MAX ( R4 , R7 ) (V); +CHECKREG r0, 0x45379565; +CHECKREG r1, 0x6759AB2D; +CHECKREG r2, 0x44555535; +CHECKREG r3, 0x66665747; +CHECKREG r4, 0x88789565; +CHECKREG r5, 0xAA8ABB5B; +CHECKREG r6, 0xCC9CDD85; +CHECKREG r7, 0xEEAEFF9F; + +imm32 r0, 0xa56b89ab; +imm32 r1, 0x659b4bcd; +imm32 r2, 0xd9736564; +imm32 r3, 0x61278394; +imm32 r4, 0xb8876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = MAX ( R5 , R0 ) (V); +R1 = MAX ( R5 , R1 ) (V); +R2 = MAX ( R5 , R2 ) (V); +R3 = MAX ( R5 , R3 ) (V); +R4 = MAX ( R5 , R4 ) (V); +R5 = MAX ( R5 , R5 ) (V); +R6 = MAX ( R5 , R6 ) (V); +R7 = MAX ( R5 , R7 ) (V); +CHECKREG r0, 0xAAAA0BBB; +CHECKREG r1, 0x659B4BCD; +CHECKREG r2, 0xD9736564; +CHECKREG r3, 0x61270BBB; +CHECKREG r4, 0xB8876439; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0xCCCC1DDD; +CHECKREG r7, 0x12346FFF; + +imm32 r0, 0x956739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0xd3456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = MAX ( R6 , R0 ) (V); +R1 = MAX ( R6 , R1 ) (V); +R2 = MAX ( R6 , R2 ) (V); +R3 = MAX ( R6 , R3 ) (V); +R4 = MAX ( R6 , R4 ) (V); +R5 = MAX ( R6 , R5 ) (V); +R6 = MAX ( R6 , R6 ) (V); +R7 = MAX ( R6 , R7 ) (V); +CHECKREG r0, 0x043239AB; +CHECKREG r1, 0x67694BCD; +CHECKREG r2, 0x04326755; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x12345699; +CHECKREG r5, 0x456790D6; +CHECKREG r6, 0x043290D6; +CHECKREG r7, 0x1234567F; + +imm32 r0, 0x876789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0xd3456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = MAX ( R7 , R0 ) (V); +R1 = MAX ( R7 , R1 ) (V); +R2 = MAX ( R7 , R2 ) (V); +R3 = MAX ( R7 , R3 ) (V); +R4 = MAX ( R7 , R4 ) (V); +R5 = MAX ( R7 , R5 ) (V); +R6 = MAX ( R7 , R6 ) (V); +R7 = MAX ( R7 , R7 ) (V); +CHECKREG r0, 0xABCD2FF7; +CHECKREG r1, 0x67792FF7; +CHECKREG r2, 0xD3456755; +CHECKREG r3, 0x56782FF7; +CHECKREG r4, 0x789A2FF7; +CHECKREG r5, 0xABCD2FF7; +CHECKREG r6, 0xABCD2FF7; +CHECKREG r7, 0xABCD2FF7; +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = MAX ( R4 , R7 ) (V); +R5 = MAX ( R5 , R5 ) (V); +R2 = MAX ( R6 , R3 ) (V); +R6 = MAX ( R0 , R4 ) (V); +R0 = MAX ( R1 , R6 ) (V); +R2 = MAX ( R2 , R1 ) (V); +R1 = MAX ( R3 , R0 ) (V); +R7 = MAX ( R7 , R4 ) (V); +CHECKREG r0, 0x67695699; +CHECKREG r1, 0x67696777; +CHECKREG r2, 0x67696777; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x12345699; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x45675699; +CHECKREG r7, 0x12345699; + +imm32 r0, 0x876789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x2345d755; +imm32 r3, 0x5678b007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = MAX ( R4 , R0 ) (V); +R5 = MAX ( R5 , R1 ) (V); +R2 = MAX ( R2 , R2 ) (V); +R7 = MAX ( R7 , R3 ) (V); +R4 = MAX ( R3 , R4 ) (V); +R0 = MAX ( R1 , R5 ) (V); +R1 = MAX ( R0 , R6 ) (V); +R6 = MAX ( R6 , R7 ) (V); +CHECKREG r0, 0x67790BBB; +CHECKREG r1, 0x67791D7D; +CHECKREG r2, 0x2345D755; +CHECKREG r3, 0x789AB799; +CHECKREG r4, 0x789AB799; +CHECKREG r5, 0x67790BBB; +CHECKREG r6, 0x789A2FF7; +CHECKREG r7, 0x789A2FF7; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_min.s b/sim/testsuite/bfin/c_dsp32alu_min.s new file mode 100644 index 0000000..b36eaac --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_min.s @@ -0,0 +1,261 @@ +//Original:/testcases/core/c_dsp32alu_min/c_dsp32alu_min.dsp +// Spec Reference: dsp32alu dregs = min ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x35678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0xf6667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = MIN ( R0 , R0 ); +R1 = MIN ( R0 , R1 ); +R2 = MIN ( R0 , R2 ); +R3 = MIN ( R0 , R3 ); +R4 = MIN ( R0 , R4 ); +R5 = MIN ( R0 , R5 ); +R6 = MIN ( R0 , R6 ); +R7 = MIN ( R0 , R7 ); +CHECKREG r0, 0x35678911; +CHECKREG r1, 0x2789AB1D; +CHECKREG r2, 0x35678911; +CHECKREG r3, 0xF6667717; +CHECKREG r4, 0x35678911; +CHECKREG r5, 0x35678911; +CHECKREG r6, 0x35678911; +CHECKREG r7, 0x86667777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = MIN ( R1 , R0 ); +R1 = MIN ( R1 , R1 ); +R2 = MIN ( R1 , R2 ); +R3 = MIN ( R1 , R3 ); +R4 = MIN ( R1 , R4 ); +R5 = MIN ( R1 , R5 ); +R6 = MIN ( R1 , R6 ); +R7 = MIN ( R1 , R7 ); +CHECKREG r0, 0x9567892B; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xA789AB2D; +CHECKREG r3, 0xA789AB2D; +CHECKREG r4, 0xA789AB2D; +CHECKREG r5, 0xA789AB2D; +CHECKREG r6, 0xA789AB2D; +CHECKREG r7, 0xA789AB2D; + +imm32 r0, 0x716789ab; +imm32 r1, 0x8289abcd; +imm32 r2, 0x93445555; +imm32 r3, 0xa4667777; +imm32 r4, 0x456789ab; +imm32 r5, 0xb689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = MIN ( R2 , R0 ); +R1 = MIN ( R2 , R1 ); +R2 = MIN ( R2 , R2 ); +R3 = MIN ( R2 , R3 ); +R4 = MIN ( R2 , R4 ); +R5 = MIN ( R2 , R5 ); +R6 = MIN ( R2 , R6 ); +R7 = MIN ( R2 , R7 ); +CHECKREG r0, 0x93445555; +CHECKREG r1, 0x8289ABCD; +CHECKREG r2, 0x93445555; +CHECKREG r3, 0x93445555; +CHECKREG r4, 0x93445555; +CHECKREG r5, 0x93445555; +CHECKREG r6, 0x93445555; +CHECKREG r7, 0x93445555; + +imm32 r0, 0x2567892b; +imm32 r1, 0x5789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = MIN ( R3 , R0 ); +R1 = MIN ( R3 , R1 ); +R2 = MIN ( R3 , R2 ); +R3 = MIN ( R3 , R3 ); +R4 = MIN ( R3 , R4 ); +R5 = MIN ( R3 , R5 ); +R6 = MIN ( R3 , R6 ); +R7 = MIN ( R3 , R7 ); +CHECKREG r0, 0x9567892B; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xB4445525; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0x93445555; +CHECKREG r5, 0x93445555; +CHECKREG r6, 0x93445555; +CHECKREG r7, 0x93445555; + +imm32 r0, 0xd537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0xf455b535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = MIN ( R4 , R0 ); +R1 = MIN ( R4 , R1 ); +R2 = MIN ( R4 , R2 ); +R3 = MIN ( R4 , R3 ); +R4 = MIN ( R4 , R4 ); +R5 = MIN ( R4 , R5 ); +R6 = MIN ( R4 , R6 ); +R7 = MIN ( R4 , R7 ); +CHECKREG r0, 0x88789565; +CHECKREG r1, 0x88789565; +CHECKREG r2, 0x88789565; +CHECKREG r3, 0x88789565; +CHECKREG r4, 0x88789565; +CHECKREG r5, 0x88789565; +CHECKREG r6, 0x88789565; +CHECKREG r7, 0x88789565; + +imm32 r0, 0xa56b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = MIN ( R5 , R0 ); +R1 = MIN ( R5 , R1 ); +R2 = MIN ( R5 , R2 ); +R3 = MIN ( R5 , R3 ); +R4 = MIN ( R5 , R4 ); +R5 = MIN ( R5 , R5 ); +R6 = MIN ( R5 , R6 ); +R7 = MIN ( R5 , R7 ); +CHECKREG r0, 0xA56B89AB; +CHECKREG r1, 0xAAAA0BBB; +CHECKREG r2, 0xAAAA0BBB; +CHECKREG r3, 0xAAAA0BBB; +CHECKREG r4, 0x98876439; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0xAAAA0BBB; +CHECKREG r7, 0xAAAA0BBB; + +imm32 r0, 0xe56739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0xd2345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = MIN ( R6 , R0 ); +R1 = MIN ( R6 , R1 ); +R2 = MIN ( R6 , R2 ); +R3 = MIN ( R6 , R3 ); +R4 = MIN ( R6 , R4 ); +R5 = MIN ( R6 , R5 ); +R6 = MIN ( R6 , R6 ); +R7 = MIN ( R6 , R7 ); +CHECKREG r0, 0xE56739AB; +CHECKREG r1, 0x043290D6; +CHECKREG r2, 0x03456755; +CHECKREG r3, 0x043290D6; +CHECKREG r4, 0xD2345699; +CHECKREG r5, 0x043290D6; +CHECKREG r6, 0x043290D6; +CHECKREG r7, 0x043290D6; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = MIN ( R7 , R0 ); +R1 = MIN ( R7 , R1 ); +R2 = MIN ( R7 , R2 ); +R3 = MIN ( R7 , R3 ); +R4 = MIN ( R7 , R4 ); +R5 = MIN ( R7 , R5 ); +R6 = MIN ( R7 , R6 ); +R7 = MIN ( R7 , R7 ); +CHECKREG r0, 0xABCD2FF7; +CHECKREG r1, 0xABCD2FF7; +CHECKREG r2, 0xABCD2FF7; +CHECKREG r3, 0xABCD2FF7; +CHECKREG r4, 0xABCD2FF7; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0x89AB1D7D; +CHECKREG r7, 0xABCD2FF7; +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0xd3456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0xb43290d6; +imm32 r7, 0x1234567f; +R4 = MIN ( R4 , R7 ); +R5 = MIN ( R5 , R5 ); +R2 = MIN ( R6 , R3 ); +R6 = MIN ( R0 , R4 ); +R0 = MIN ( R1 , R6 ); +R2 = MIN ( R2 , R1 ); +R1 = MIN ( R3 , R0 ); +R7 = MIN ( R7 , R4 ); +CHECKREG r0, 0x1234567F; +CHECKREG r1, 0x1234567F; +CHECKREG r2, 0xB43290D6; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x1234567F; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x1234567F; +CHECKREG r7, 0x1234567F; + +imm32 r0, 0xa76789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0xf3456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = MIN ( R4 , R0 ); +R5 = MIN ( R5 , R1 ); +R2 = MIN ( R2 , R2 ); +R7 = MIN ( R7 , R3 ); +R4 = MIN ( R3 , R4 ); +R0 = MIN ( R1 , R5 ); +R1 = MIN ( R0 , R6 ); +R6 = MIN ( R6 , R7 ); +CHECKREG r0, 0xAAAA0BBB; +CHECKREG r1, 0x89AB1D7D; +CHECKREG r2, 0xF3456755; +CHECKREG r3, 0xA76789AB; +CHECKREG r4, 0xA76789AB; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0x89AB1D7D; +CHECKREG r7, 0xA76789AB; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_minmin.s b/sim/testsuite/bfin/c_dsp32alu_minmin.s new file mode 100644 index 0000000..4106245 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_minmin.s @@ -0,0 +1,261 @@ +//Original:/testcases/core/c_dsp32alu_minmin/c_dsp32alu_minmin.dsp +// Spec Reference: dsp32alu dregs = min / min ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x25678911; +imm32 r1, 0x2389ab1d; +imm32 r2, 0x2a445345; +imm32 r3, 0x46657717; +imm32 r4, 0xd567e91b; +imm32 r5, 0x6789af1d; +imm32 r6, 0x74445d85; +imm32 r7, 0x8666a779; +R0 = MIN ( R0 , R0 ) (V); +R1 = MIN ( R0 , R1 ) (V); +R2 = MIN ( R0 , R2 ) (V); +R3 = MIN ( R0 , R3 ) (V); +R4 = MIN ( R0 , R4 ) (V); +R5 = MIN ( R0 , R5 ) (V); +R6 = MIN ( R0 , R6 ) (V); +R7 = MIN ( R0 , R7 ) (V); +CHECKREG r0, 0x25678911; +CHECKREG r1, 0x23898911; +CHECKREG r2, 0x25678911; +CHECKREG r3, 0x25678911; +CHECKREG r4, 0xD5678911; +CHECKREG r5, 0x25678911; +CHECKREG r6, 0x25678911; +CHECKREG r7, 0x86668911; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = MIN ( R1 , R0 ) (V); +R1 = MIN ( R1 , R1 ) (V); +R2 = MIN ( R1 , R2 ) (V); +R3 = MIN ( R1 , R3 ) (V); +R4 = MIN ( R1 , R4 ) (V); +R5 = MIN ( R1 , R5 ) (V); +R6 = MIN ( R1 , R6 ) (V); +R7 = MIN ( R1 , R7 ) (V); +CHECKREG r0, 0x9567892B; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xA789AB2D; +CHECKREG r3, 0xA789AB2D; +CHECKREG r4, 0xA7899929; +CHECKREG r5, 0xA789AB2D; +CHECKREG r6, 0xA789AB2D; +CHECKREG r7, 0xA789AB2D; + +imm32 r0, 0x416789ab; +imm32 r1, 0x5289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0xa466a777; +imm32 r4, 0x45678dab; +imm32 r5, 0xf689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = MIN ( R2 , R0 ) (V); +R1 = MIN ( R2 , R1 ) (V); +R2 = MIN ( R2 , R2 ) (V); +R3 = MIN ( R2 , R3 ) (V); +R4 = MIN ( R2 , R4 ) (V); +R5 = MIN ( R2 , R5 ) (V); +R6 = MIN ( R2 , R6 ) (V); +R7 = MIN ( R2 , R7 ) (V); +CHECKREG r0, 0x416789AB; +CHECKREG r1, 0x4344ABCD; +CHECKREG r2, 0x43445555; +CHECKREG r3, 0xA466A777; +CHECKREG r4, 0x43448DAB; +CHECKREG r5, 0xF689ABCD; +CHECKREG r6, 0x43445555; +CHECKREG r7, 0x43445555; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = MIN ( R3 , R0 ) (V); +R1 = MIN ( R3 , R1 ) (V); +R2 = MIN ( R3 , R2 ) (V); +R3 = MIN ( R3 , R3 ) (V); +R4 = MIN ( R3 , R4 ) (V); +R5 = MIN ( R3 , R5 ) (V); +R6 = MIN ( R3 , R6 ) (V); +R7 = MIN ( R3 , R7 ) (V); +CHECKREG r0, 0x9567892B; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xB4445525; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0xC6668DAB; +CHECKREG r5, 0xC666ABCD; +CHECKREG r6, 0xC6665555; +CHECKREG r7, 0xC6665555; + +imm32 r0, 0x5537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x74555535; +imm32 r3, 0x86665747; +imm32 r4, 0x98789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = MIN ( R4 , R0 ) (V); +R1 = MIN ( R4 , R1 ) (V); +R2 = MIN ( R4 , R2 ) (V); +R3 = MIN ( R4 , R3 ) (V); +R4 = MIN ( R4 , R4 ) (V); +R5 = MIN ( R4 , R5 ) (V); +R6 = MIN ( R4 , R6 ) (V); +R7 = MIN ( R4 , R7 ) (V); +CHECKREG r0, 0x9878891B; +CHECKREG r1, 0x98789565; +CHECKREG r2, 0x98789565; +CHECKREG r3, 0x86669565; +CHECKREG r4, 0x98789565; +CHECKREG r5, 0x98789565; +CHECKREG r6, 0x98789565; +CHECKREG r7, 0x98789565; + +imm32 r0, 0x256b89ab; +imm32 r1, 0x64764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x43346fff; +R0 = MIN ( R5 , R0 ) (V); +R1 = MIN ( R5 , R1 ) (V); +R2 = MIN ( R5 , R2 ) (V); +R3 = MIN ( R5 , R3 ) (V); +R4 = MIN ( R5 , R4 ) (V); +R5 = MIN ( R5 , R5 ) (V); +R6 = MIN ( R5 , R6 ) (V); +R7 = MIN ( R5 , R7 ) (V); +CHECKREG r0, 0xAAAA89AB; +CHECKREG r1, 0xAAAA0BBB; +CHECKREG r2, 0xAAAA0BBB; +CHECKREG r3, 0xAAAA8394; +CHECKREG r4, 0x98870BBB; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0xAAAA0BBB; +CHECKREG r7, 0xAAAA0BBB; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = MIN ( R6 , R0 ) (V); +R1 = MIN ( R6 , R1 ) (V); +R2 = MIN ( R6 , R2 ) (V); +R3 = MIN ( R6 , R3 ) (V); +R4 = MIN ( R6 , R4 ) (V); +R5 = MIN ( R6 , R5 ) (V); +R6 = MIN ( R6 , R6 ) (V); +R7 = MIN ( R6 , R7 ) (V); +CHECKREG r0, 0x043290D6; +CHECKREG r1, 0x043290D6; +CHECKREG r2, 0x034590D6; +CHECKREG r3, 0x043290D6; +CHECKREG r4, 0x043290D6; +CHECKREG r5, 0x04328B6B; +CHECKREG r6, 0x043290D6; +CHECKREG r7, 0x043290D6; + +imm32 r0, 0x976789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x8345a755; +imm32 r3, 0x5678b007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = MIN ( R7 , R0 ) (V); +R1 = MIN ( R7 , R1 ) (V); +R2 = MIN ( R7 , R2 ) (V); +R3 = MIN ( R7 , R3 ) (V); +R4 = MIN ( R7 , R4 ) (V); +R5 = MIN ( R7 , R5 ) (V); +R6 = MIN ( R7 , R6 ) (V); +R7 = MIN ( R7 , R7 ) (V); +CHECKREG r0, 0x976789AB; +CHECKREG r1, 0xABCDABCD; +CHECKREG r2, 0x8345A755; +CHECKREG r3, 0xABCDB007; +CHECKREG r4, 0xABCDB799; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0x89AB1D7D; +CHECKREG r7, 0xABCD2FF7; +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = MIN ( R4 , R7 ) (V); +R5 = MIN ( R5 , R5 ) (V); +R2 = MIN ( R6 , R3 ) (V); +R6 = MIN ( R0 , R4 ) (V); +R0 = MIN ( R1 , R6 ) (V); +R2 = MIN ( R2 , R1 ) (V); +R1 = MIN ( R3 , R0 ) (V); +R7 = MIN ( R7 , R4 ) (V); +CHECKREG r0, 0x123439AB; +CHECKREG r1, 0x123439AB; +CHECKREG r2, 0x043290D6; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x1234567F; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x123439AB; +CHECKREG r7, 0x1234567F; + +imm32 r0, 0xa76789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0xb3456755; +imm32 r3, 0x5678d007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = MIN ( R4 , R0 ) (V); +R5 = MIN ( R5 , R1 ) (V); +R2 = MIN ( R2 , R2 ) (V); +R7 = MIN ( R7 , R3 ) (V); +R4 = MIN ( R3 , R4 ) (V); +R0 = MIN ( R1 , R5 ) (V); +R1 = MIN ( R0 , R6 ) (V); +R6 = MIN ( R6 , R7 ) (V); +CHECKREG r0, 0xAAAAABCD; +CHECKREG r1, 0x89ABABCD; +CHECKREG r2, 0xB3456755; +CHECKREG r3, 0xA76789AB; +CHECKREG r4, 0xA76789AB; +CHECKREG r5, 0xAAAAABCD; +CHECKREG r6, 0x89AB89AB; +CHECKREG r7, 0xA76789AB; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_mix.s b/sim/testsuite/bfin/c_dsp32alu_mix.s new file mode 100644 index 0000000..e54523c --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_mix.s @@ -0,0 +1,137 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_mix/c_dsp32alu_mix.dsp +// Spec Reference: dsp32alu mix +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + +// ALU operations include parallel addition, subtraction, MAX, MIN, ABS on 16-bit +// and 32-bit data. If an operation use a single ALU only, it uses ALU0. + + imm32 r2, 0x44445555; + imm32 r3, 0x66667777; + imm32 r4, 0x88889999; + imm32 r5, 0xaaaabbbb; + imm32 r6, 0xccccdddd; + imm32 r7, 0xeeeeffff; + + imm32 r0, 0x456789ab; + imm32 r1, 0x6789abcd; +// Use only single ALU (ALU0 only), with saturation (S) + R2 = R1 + R0 (NS); /* 0xACF13578 */ + R3 = R2 + R0 (NS); /* 0xACF13578 */ + CHECKREG r2, 0xACF13578; + CHECKREG r3, 0xF258BF23; + R2 = R1 + R0 (S); /* 0x7FFFFFFF */ + R3 = R1 - R0 (NS); /* 0x22222222 */ + R4.L = R1.L + R0.L (NS); /* 0x88883578 */ + R5.L = R1.L + R0.H (NS); /* 0xAAAAF134 */ + R6.L = R1.H + R0.L (NS); /* 0xCCCCF134 */ + R7.L = R1.H + R0.H (NS); /* 0xEEEEACF0 */ + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r3, 0x22222222; + CHECKREG r4, 0x88883578; + CHECKREG r5, 0xAAAAF134; + CHECKREG r6, 0xCCCCF134; + CHECKREG r7, 0xEEEEACF0; + + R4.H = R1.L + R0.L (S); /* 0x80003578 */ + R5.H = R1.L + R0.H (S); /* 0xF134F134 */ + R6.H = R1.H + R0.L (S); /* 0xF134F134 */ + CHECKREG r4, 0x80003578; + CHECKREG r5, 0xF134F134; + CHECKREG r6, 0xF134F134; + + R4.H = R1.L + R0.L (S); /* 0x80003578 */ + R5.H = R1.L + R0.H (S); /* 0xF134F134 */ + R6.H = R1.H + R0.L (S); /* 0xF134F134 */ + CHECKREG r4, 0x80003578; /* 0x */ + CHECKREG r5, 0xF134F134; /* 0x */ + CHECKREG r6, 0xF134F134; /* 0x */ + + R4.H = R1.L + R0.L (S); /* 0x80003578 */ + R5.H = R1.L + R0.H (S); /* 0xF134F134 */ + R6.H = R1.H + R0.L (S); /* 0xF134F134 */ + R7.H = R1.H + R0.H (S); /* 0x7FFFACF0 */ + CHECKREG r4, 0x80003578; /* 0x */ + CHECKREG r5, 0xF134F134; /* 0x */ + CHECKREG r6, 0xF134F134; /* 0x */ + CHECKREG r7, 0x7FFFACF0; /* 0x */ + +// Dual + R2 = R0 +|+ R1 (SCO); /* 0x80007FFF */ + R3 = R0 +|- R1 (S); /* 0x7FFFDDDE */ + R4 = R0 -|+ R1 (SCO); /* 0x8000DDDE)*/ + R5 = R0 -|- R1 (SCO); /* 0xDDDEDDDE */ + CHECKREG r2, 0x80007FFF; + CHECKREG r3, 0x7FFFDDDE; + CHECKREG r4, 0x8000DDDE; + CHECKREG r5, 0xDDDEDDDE; + R2 = R0 +|+ R1, R3 = R0 -|- R1 (SCO); /* 0x */ +CHECKREG r2, 0x7FFF8000; + R4 = R0 +|- R1 , R5 = R0 -|+ R1 (CO); /* 0x */ + R6 = R0 + R1, R7 = R0 - R1 (S); /* 0x */ + CHECKREG r2, 0x7FFF8000; + CHECKREG r3, 0xDDDEDDDE; + CHECKREG r4, 0xACF0DDDE; + CHECKREG r5, 0x3578DDDE; + CHECKREG r6, 0x7FFFFFFF; + CHECKREG r7, 0xDDDDDDDE; + +// Max min abs types + R3 = MAX ( R0 , R1 ); /* 0x6789ABCD */ + R4 = MIN ( R0 , R1 ); /* 0x456789AB */ + R5 = ABS R0; /* 0x456789AB */ + CHECKREG r3, 0x6789ABCD; + CHECKREG r4, 0x456789AB; + CHECKREG r5, 0x456789AB; + R3 = MAX ( R0 , R1 ) (V); /* 0x6789ABCD */ + R4 = MIN ( R0 , R1 ) (V); /* 0x456789AB */ + R5 = ABS R0 (V); /* 0x45677655 */ + CHECKREG r3, 0x6789ABCD; + CHECKREG r4, 0x456789AB; + CHECKREG r5, 0x45677655; + +// RND types + R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L; + R3.L = R0 + R1 (RND12); /* 0x */ + R4.H = R0 - R1 (RND12); /* 0x */ + R5.L = R0 + R1 (RND20); /* 0x */ + R6.H = R0 - R1 (RND20); /* 0x */ + R7.H = R1 (RND); /* 0x */ + CHECKREG r2, 0xBBBCBBBC; + CHECKREG r3, 0x67897FFF; + CHECKREG r4, 0x800089AB; + CHECKREG r5, 0x45670ACF; + CHECKREG r6, 0xFDDEFFFF; + CHECKREG r7, 0x678ADDDE; + + R7 = - R0 (V); /* 0x */ + CHECKREG r7, 0xBA997655; +// A0 & A1 types + A0 = 0; + A1 = 0; + A0.L = R0.L; + A0.H = R0.H; + A0 = A1; + A0.x = R0.L; + A1.x = R0.L; + R2.L = A0.x; /* 0x */ + R3.L = A1.x; /* 0x */ + R4 = ( A0 += A1 ); /* 0x */ + R5.L = ( A0 += A1 ); /* 0x */ + R5.H = ( A0 += A1 ); /* 0x */ + CHECKREG r2, 0xBBBCffAB; /* 0x */ + CHECKREG r3, 0x6789ffAB; /* 0x */ + CHECKREG r4, 0x80000000; /* 0x */ + CHECKREG r5, 0x80008000; /* 0x */ + A0 += A1; + A0 -= A1; + R6 = A1.L + A1.H, R7 = A0.L + A0.H; /* 0x */ + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_r_lh_a0pa1.s b/sim/testsuite/bfin/c_dsp32alu_r_lh_a0pa1.s new file mode 100644 index 0000000..931662b --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_r_lh_a0pa1.s @@ -0,0 +1,75 @@ +//Original:/testcases/core/c_dsp32alu_r_lh_a0pa1/c_dsp32alu_r_lh_a0pa1.dsp +// Spec Reference: dsp32alu r(lh) = ( a0 += a1) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x15678911; +imm32 r1, 0x0125ab2d; +imm32 r2, 0x04445535; +imm32 r3, 0x00567747; +imm32 r4, 0x0566895b; +imm32 r5, 0x07897b6d; +imm32 r6, 0x04445875; +imm32 r7, 0x06667797; +A0 = R0; +A1 = R1; +R0 = ( A0 += A1 ); +R1 = ( A0 += A1 ); +R2 = ( A0 += A1 ); +R3 = ( A0 += A1 ); +R4 = ( A0 += A1 ); +R5 = ( A0 += A1 ); +R6 = ( A0 += A1 ); +R7 = ( A0 += A1 ); +CHECKREG r0, 0x168D343E; +CHECKREG r1, 0x17B2DF6B; +CHECKREG r2, 0x18D88A98; +CHECKREG r3, 0x19FE35C5; +CHECKREG r4, 0x1B23E0F2; +CHECKREG r5, 0x1C498C1F; +CHECKREG r6, 0x1D6F374C; +CHECKREG r7, 0x1E94E279; + +imm32 r0, 0x068D343E; +imm32 r1, 0x02B2DF6B; +imm32 r2, 0x48388A98; +imm32 r3, 0x59F435C5; +imm32 r4, 0x6B25E0F2; +imm32 r5, 0x7C496C1F; +imm32 r6, 0x886F374C; +imm32 r7, 0x9E94E279; +A0 = R0; +A1 = R1; +R0.L = ( A0 += A1 ); +R0.H = ( A0 += A1 ); +R1.L = ( A0 += A1 ); +R1.H = ( A0 += A1 ); +R2.L = ( A0 += A1 ); +R2.H = ( A0 += A1 ); +R3.L = ( A0 += A1 ); +R3.H = ( A0 += A1 ); +R4.L = ( A0 += A1 ); +R4.H = ( A0 += A1 ); +R5.L = ( A0 += A1 ); +R5.H = ( A0 += A1 ); +R6.L = ( A0 += A1 ); +R6.H = ( A0 += A1 ); +R7.L = ( A0 += A1 ); +R7.H = ( A0 += A1 ); +CHECKREG r0, 0x0BF30940; +CHECKREG r1, 0x11590EA6; +CHECKREG r2, 0x16BE140C; +CHECKREG r3, 0x1C241971; +CHECKREG r4, 0x218A1ED7; +CHECKREG r5, 0x26F0243D; +CHECKREG r6, 0x2C5529A3; +CHECKREG r7, 0x31BB2F08; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_r_negneg.s b/sim/testsuite/bfin/c_dsp32alu_r_negneg.s new file mode 100644 index 0000000..9c9d60c --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_r_negneg.s @@ -0,0 +1,88 @@ +//Original:/testcases/core/c_dsp32alu_r_negneg/c_dsp32alu_r_negneg.dsp +// Spec Reference: dsp32alu dregs = neg / neg dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = - R0 (V); +R1 = - R1 (V); +R2 = - R2 (V); +R3 = - R3 (V); +R4 = - R4 (V); +R5 = - R5 (V); +R6 = - R6 (V); +R7 = - R7 (V); +CHECKREG r0, 0x5A9976EF; +CHECKREG r1, 0xD87754E3; +CHECKREG r2, 0xC4BC4AEB; +CHECKREG r3, 0xB99A88E9; +CHECKREG r4, 0xAA9976E5; +CHECKREG r5, 0x987754E3; +CHECKREG r6, 0x8BBCAAEB; +CHECKREG r7, 0x799A8889; + +imm32 r0, 0xa567892b; +imm32 r1, 0x2789ab2d; +imm32 r2, 0x344d5525; +imm32 r3, 0xd6667727; +imm32 r4, 0x58889929; +imm32 r5, 0x6aaabb2b; +imm32 r6, 0x7ccfdd2d; +imm32 r7, 0x8eeeffff; +R1 = - R0 (V); +R2 = - R1 (V); +R3 = - R2 (V); +R4 = - R3 (V); +R5 = - R4 (V); +R6 = - R5 (V); +R7 = - R6 (V); +R0 = - R7 (V); +CHECKREG r0, 0xA567892B; +CHECKREG r1, 0x5A9976D5; +CHECKREG r2, 0xA567892B; +CHECKREG r3, 0x5A9976D5; +CHECKREG r4, 0xA567892B; +CHECKREG r5, 0x5A9976D5; +CHECKREG r6, 0xA567892B; +CHECKREG r7, 0x5A9976D5; + +imm32 r0, 0xb5678941; +imm32 r1, 0x2789ab5d; +imm32 r2, 0x34445565; +imm32 r3, 0xe6667777; +imm32 r4, 0x5567898b; +imm32 r5, 0x6789ab9d; +imm32 r6, 0xc4445505; +imm32 r7, 0x8666b777; +R2 = - R0 (V); +R3 = - R1 (V); +R4 = - R2 (V); +R5 = - R3 (V); +R6 = - R4 (V); +R7 = - R5 (V); +R0 = - R6 (V); +R1 = - R7 (V); +CHECKREG r0, 0xB5678941; +CHECKREG r1, 0x2789AB5D; +CHECKREG r2, 0x4A9976BF; +CHECKREG r3, 0xD87754A3; +CHECKREG r4, 0xB5678941; +CHECKREG r5, 0x2789AB5D; +CHECKREG r6, 0x4A9976BF; +CHECKREG r7, 0xD87754A3; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rh_m.s b/sim/testsuite/bfin/c_dsp32alu_rh_m.s new file mode 100644 index 0000000..ba4dfa3 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rh_m.s @@ -0,0 +1,263 @@ +//Original:/testcases/core/c_dsp32alu_rh_m/c_dsp32alu_rh_m.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x89678911; +imm32 r1, 0x2189ab1d; +imm32 r2, 0x34145515; +imm32 r3, 0x46617717; +imm32 r4, 0x5678191b; +imm32 r5, 0x6789a11d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667771; +R0.H = R0.L - R0.L (NS); +R1.H = R0.L - R1.H (NS); +R2.H = R0.H - R2.L (NS); +R3.H = R0.H - R3.H (NS); +R4.H = R0.L - R4.L (NS); +R5.H = R0.L - R5.H (NS); +R6.H = R0.H - R6.L (NS); +R7.H = R0.H - R7.H (NS); +CHECKREG r4, 0x6FF6191B; +CHECKREG r5, 0x2188A11D; +CHECKREG r6, 0xAAEB5515; +CHECKREG r7, 0x799A7771; +CHECKREG r4, 0x6FF6191B; +CHECKREG r5, 0x2188A11D; +CHECKREG r6, 0xAAEB5515; +CHECKREG r7, 0x799A7771; + +imm32 r0, 0x25678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x38445515; +imm32 r3, 0x468a7717; +imm32 r4, 0x5678e91b; +imm32 r5, 0x6789af1d; +imm32 r6, 0x744455f5; +imm32 r7, 0x8666777f; +R0.H = R1.L - R0.L (NS); +R1.H = R1.L - R1.H (NS); +R2.H = R1.H - R2.L (NS); +R3.H = R1.H - R3.H (NS); +R4.H = R1.L - R4.L (NS); +R5.H = R1.L - R5.H (NS); +R6.H = R1.H - R6.L (NS); +R7.H = R1.H - R7.H (NS); +CHECKREG r4, 0xC202E91B; +CHECKREG r5, 0x4394AF1D; +CHECKREG r6, 0x2D9F55F5; +CHECKREG r7, 0xFD2E777F; +CHECKREG r4, 0xC202E91B; +CHECKREG r5, 0x4394AF1D; +CHECKREG r6, 0x2D9F55F5; +CHECKREG r7, 0xFD2E777F; + +imm32 r0, 0x78678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34885515; +imm32 r3, 0x466aa717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789aa1d; +imm32 r6, 0x74445aa5; +imm32 r7, 0x866677a7; +R0.H = R2.L - R0.L (NS); +R1.H = R2.L - R1.H (NS); +R2.H = R2.H - R2.L (NS); +R3.H = R2.H - R3.H (NS); +R4.H = R2.L - R4.L (NS); +R5.H = R2.L - R5.H (NS); +R6.H = R2.H - R6.L (NS); +R7.H = R2.H - R7.H (NS); +CHECKREG r4, 0xCBFA891B; +CHECKREG r5, 0xED8CAA1D; +CHECKREG r6, 0x84CE5AA5; +CHECKREG r7, 0x590D77A7; +CHECKREG r4, 0xCBFA891B; +CHECKREG r5, 0xED8CAA1D; +CHECKREG r6, 0x84CE5AA5; +CHECKREG r7, 0x590D77A7; + +imm32 r0, 0xb5678911; +imm32 r1, 0xb789ab1d; +imm32 r2, 0x3b445515; +imm32 r3, 0x46b67717; +imm32 r4, 0x567b891b; +imm32 r5, 0x6789bb1d; +imm32 r6, 0x74445b15; +imm32 r7, 0x866677b7; +R0.H = R3.L - R0.L (NS); +R1.H = R3.L - R1.H (NS); +R2.H = R3.H - R2.L (NS); +R3.H = R3.H - R3.H (NS); +R4.H = R3.L - R4.L (NS); +R5.H = R3.L - R5.H (NS); +R6.H = R3.H - R6.L (NS); +R7.H = R3.H - R7.H (NS); +CHECKREG r4, 0xEDFC891B; +CHECKREG r5, 0x0F8EBB1D; +CHECKREG r6, 0xA4EB5B15; +CHECKREG r7, 0x799A77B7; +CHECKREG r4, 0xEDFC891B; +CHECKREG r5, 0x0F8EBB1D; +CHECKREG r6, 0xA4EB5B15; +CHECKREG r7, 0x799A77B7; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.H = R4.L - R0.L (NS); +R1.H = R4.L - R1.H (NS); +R2.H = R4.H - R2.L (NS); +R3.H = R4.H - R3.H (NS); +R4.H = R4.L - R4.L (NS); +R5.H = R4.L - R5.H (NS); +R6.H = R4.H - R6.L (NS); +R7.H = R4.H - R7.H (NS); +CHECKREG r4, 0x0000891B; +CHECKREG r5, 0x2192AB1D; +CHECKREG r6, 0xAAEB5515; +CHECKREG r7, 0x799A7777; +CHECKREG r4, 0x0000891B; +CHECKREG r5, 0x2192AB1D; +CHECKREG r6, 0xAAEB5515; +CHECKREG r7, 0x799A7777; + +imm32 r0, 0xcc678911; +imm32 r1, 0xc789ab1d; +imm32 r2, 0x3c445515; +imm32 r3, 0x46c67717; +imm32 r4, 0x567c891b; +imm32 r5, 0x6789cb1d; +imm32 r6, 0x74445c15; +imm32 r7, 0x866677c7; +R0.H = R5.L - R0.L (NS); +R1.H = R5.L - R1.H (NS); +R2.H = R5.H - R2.L (NS); +R3.H = R5.H - R3.H (NS); +R4.H = R5.L - R4.L (NS); +R5.H = R5.L - R5.H (NS); +R6.H = R5.H - R6.L (NS); +R7.H = R5.H - R7.H (NS); +CHECKREG r4, 0x4202891B; +CHECKREG r5, 0x6394CB1D; +CHECKREG r6, 0x077F5C15; +CHECKREG r7, 0xDD2E77C7; +CHECKREG r4, 0x4202891B; +CHECKREG r5, 0x6394CB1D; +CHECKREG r6, 0x077F5C15; +CHECKREG r7, 0xDD2E77C7; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.H = R6.L - R0.L (NS); +R1.H = R6.L - R1.H (NS); +R2.H = R6.H - R2.L (NS); +R3.H = R6.H - R3.H (NS); +R4.H = R6.L - R4.L (NS); +R5.H = R6.L - R5.H (NS); +R6.H = R6.H - R6.L (NS); +R7.H = R6.H - R7.H (NS); +CHECKREG r4, 0xCBFA891B; +CHECKREG r5, 0xED8CAB1D; +CHECKREG r6, 0x1F2F5515; +CHECKREG r7, 0x98C97777; +CHECKREG r4, 0xCBFA891B; +CHECKREG r5, 0xED8CAB1D; +CHECKREG r6, 0x1F2F5515; +CHECKREG r7, 0x98C97777; + +imm32 r0, 0xd5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667e17; +imm32 r4, 0x56e8891b; +imm32 r5, 0x678eab1d; +imm32 r6, 0x7444e515; +imm32 r7, 0x86667e77; +R0.H = R7.L - R0.L (NS); +R1.H = R7.L - R1.H (NS); +R2.H = R7.H - R2.L (NS); +R3.H = R7.H - R3.H (NS); +R4.H = R7.L - R4.L (NS); +R5.H = R7.L - R5.H (NS); +R6.H = R7.H - R6.L (NS); +R7.H = R7.H - R7.H (NS); +CHECKREG r4, 0xF55C891B; +CHECKREG r5, 0x16E9AB1D; +CHECKREG r6, 0xA151E515; +CHECKREG r7, 0x00007E77; +CHECKREG r4, 0xF55C891B; +CHECKREG r5, 0x16E9AB1D; +CHECKREG r6, 0xA151E515; +CHECKREG r7, 0x00007E77; + +imm32 r0, 0xff678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34ff5515; +imm32 r3, 0x4666f717; +imm32 r4, 0x567f891b; +imm32 r5, 0x6789fb1d; +imm32 r6, 0x74445f15; +imm32 r7, 0x866677f7; +R6.H = R2.L - R3.L (S); +R1.H = R4.L - R5.H (S); +R5.H = R7.H - R2.L (S); +R3.H = R0.H - R0.H (S); +R0.H = R3.L - R4.L (S); +R2.H = R5.L - R7.H (S); +R7.H = R6.H - R7.L (S); +R4.H = R1.H - R6.H (S); +CHECKREG r4, 0x8000891B; +CHECKREG r5, 0x8000FB1D; +CHECKREG r6, 0x5DFE5F15; +CHECKREG r7, 0xE60777F7; +CHECKREG r4, 0x8000891B; +CHECKREG r5, 0x8000FB1D; +CHECKREG r6, 0x5DFE5F15; +CHECKREG r7, 0xE60777F7; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3.H = R4.L - R0.L (S); +R1.H = R6.L - R3.H (S); +R4.H = R3.H - R2.L (S); +R6.H = R7.H - R1.H (S); +R2.H = R5.L - R4.L (S); +R7.H = R2.L - R7.H (S); +R0.H = R1.H - R6.L (S); +R5.H = R0.H - R5.H (S); +CHECKREG r4, 0xAAF5891B; +CHECKREG r5, 0x986DAB1D; +CHECKREG r6, 0x80005515; +CHECKREG r7, 0x7FFF7777; +CHECKREG r4, 0xAAF5891B; +CHECKREG r5, 0x986DAB1D; +CHECKREG r6, 0x80005515; +CHECKREG r7, 0x7FFF7777; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rh_p.s b/sim/testsuite/bfin/c_dsp32alu_rh_p.s new file mode 100644 index 0000000..fb7d3fa --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rh_p.s @@ -0,0 +1,263 @@ +//Original:/testcases/core/c_dsp32alu_rh_p/c_dsp32alu_rh_p.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x34678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34645515; +imm32 r3, 0x46667717; +imm32 r4, 0xd678891b; +imm32 r5, 0x6e89ab1d; +imm32 r6, 0x74b45515; +imm32 r7, 0x866cc777; +R0.H = R0.L + R0.L (NS); +R1.H = R0.L + R1.H (NS); +R2.H = R0.H + R2.L (NS); +R3.H = R0.H + R3.H (NS); +R4.H = R0.L + R4.L (NS); +R5.H = R0.L + R5.H (NS); +R6.H = R0.H + R6.L (NS); +R7.H = R0.H + R7.H (NS); +CHECKREG r4, 0x122C891B; +CHECKREG r5, 0xF79AAB1D; +CHECKREG r6, 0x67375515; +CHECKREG r7, 0x988EC777; +CHECKREG r4, 0x122C891B; +CHECKREG r5, 0xF79AAB1D; +CHECKREG r6, 0x67375515; +CHECKREG r7, 0x988EC777; + +imm32 r0, 0x12348911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34f45515; +imm32 r3, 0x46d67717; +imm32 r4, 0x567b891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444b515; +imm32 r7, 0x86667a77; +R0.H = R1.L + R0.L (NS); +R1.H = R1.L + R1.H (NS); +R2.H = R1.H + R2.L (NS); +R3.H = R1.H + R3.H (NS); +R4.H = R1.L + R4.L (NS); +R5.H = R1.L + R5.H (NS); +R6.H = R1.H + R6.L (NS); +R7.H = R1.H + R7.H (NS); +CHECKREG r4, 0x3438891B; +CHECKREG r5, 0x12A6AB1D; +CHECKREG r6, 0x8EBBB515; +CHECKREG r7, 0x600C7A77; +CHECKREG r4, 0x3438891B; +CHECKREG r5, 0x12A6AB1D; +CHECKREG r6, 0x8EBBB515; +CHECKREG r7, 0x600C7A77; + +imm32 r0, 0x85678911; +imm32 r1, 0x3989ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x5e78891b; +imm32 r5, 0x67d9ab1d; +imm32 r6, 0x744b5515; +imm32 r7, 0x86668777; +R0.H = R2.L + R0.L (NS); +R1.H = R2.L + R1.H (NS); +R2.H = R2.H + R2.L (NS); +R3.H = R2.H + R3.H (NS); +R4.H = R2.L + R4.L (NS); +R5.H = R2.L + R5.H (NS); +R6.H = R2.H + R6.L (NS); +R7.L = R2.H + R7.H (NS); +CHECKREG r4, 0xDE30891B; +CHECKREG r5, 0xBCEEAB1D; +CHECKREG r6, 0xDE6E5515; +CHECKREG r7, 0x86660FBF; +CHECKREG r4, 0xDE30891B; +CHECKREG r5, 0xBCEEAB1D; +CHECKREG r6, 0xDE6E5515; +CHECKREG r7, 0x86660FBF; + +imm32 r0, 0x25678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3e445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x567f891b; +imm32 r5, 0x6789bb1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667b77; +R0.H = R3.L + R0.L (NS); +R1.H = R3.L + R1.H (NS); +R2.H = R3.H + R2.L (NS); +R3.H = R3.H + R3.H (NS); +R4.H = R3.L + R4.L (NS); +R5.H = R3.L + R5.H (NS); +R6.H = R3.H + R6.L (NS); +R7.H = R3.H + R7.H (NS); +CHECKREG r4, 0x0032891B; +CHECKREG r5, 0xDEA0BB1D; +CHECKREG r6, 0xE2C15515; +CHECKREG r7, 0x14127B77; +CHECKREG r4, 0x0032891B; +CHECKREG r5, 0xDEA0BB1D; +CHECKREG r6, 0xE2C15515; +CHECKREG r7, 0x14127B77; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.H = R4.L + R0.L (NS); +R1.H = R4.L + R1.H (NS); +R2.H = R4.H + R2.L (NS); +R3.H = R4.H + R3.H (NS); +R4.H = R4.L + R4.L (NS); +R5.H = R4.L + R5.H (NS); +R6.H = R4.H + R6.L (NS); +R7.H = R4.H + R7.H (NS); +CHECKREG r4, 0x1236891B; +CHECKREG r5, 0xF0A4AB1D; +CHECKREG r6, 0x674B5515; +CHECKREG r7, 0x989C7777; +CHECKREG r4, 0x1236891B; +CHECKREG r5, 0xF0A4AB1D; +CHECKREG r6, 0x674B5515; +CHECKREG r7, 0x989C7777; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34d45515; +imm32 r3, 0x466b7717; +imm32 r4, 0x5678f91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444a515; +imm32 r7, 0x86667b77; +R0.H = R5.L + R0.L (NS); +R1.H = R5.L + R1.H (NS); +R2.H = R5.H + R2.L (NS); +R3.H = R5.H + R3.H (NS); +R4.H = R5.L + R4.L (NS); +R5.H = R5.L + R5.H (NS); +R6.H = R5.H + R6.L (NS); +R7.H = R5.H + R7.H (NS); +CHECKREG r4, 0xA438F91B; +CHECKREG r5, 0x12A6AB1D; +CHECKREG r6, 0xB7BBA515; +CHECKREG r7, 0x990C7B77; +CHECKREG r4, 0xA438F91B; +CHECKREG r5, 0x12A6AB1D; +CHECKREG r6, 0xB7BBA515; +CHECKREG r7, 0x990C7B77; + +imm32 r0, 0xf5678911; +imm32 r1, 0x2f89ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46f67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678fab1d; +imm32 r6, 0x7444f515; +imm32 r7, 0x86667f77; +R0.L = R6.L + R0.L (NS); +R1.H = R6.L + R1.H (NS); +R2.H = R6.H + R2.L (NS); +R3.H = R6.H + R3.H (NS); +R4.H = R6.L + R4.L (NS); +R5.H = R6.L + R5.H (NS); +R6.H = R6.H + R6.L (NS); +R7.H = R6.H + R7.H (NS); +CHECKREG r4, 0x7E30891B; +CHECKREG r5, 0x5CA4AB1D; +CHECKREG r6, 0x6959F515; +CHECKREG r7, 0xEFBF7F77; +CHECKREG r4, 0x7E30891B; +CHECKREG r5, 0x5CA4AB1D; +CHECKREG r6, 0x6959F515; +CHECKREG r7, 0xEFBF7F77; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.H = R7.L + R0.L (NS); +R1.H = R7.L + R1.H (NS); +R2.H = R7.H + R2.L (NS); +R3.H = R7.H + R3.H (NS); +R4.H = R7.L + R4.L (NS); +R5.H = R7.L + R5.H (NS); +R6.H = R7.H + R6.L (NS); +R7.H = R7.H + R7.H (NS); +CHECKREG r4, 0x0092891B; +CHECKREG r5, 0xDF00AB1D; +CHECKREG r6, 0xDB7B5515; +CHECKREG r7, 0x0CCC7777; +CHECKREG r4, 0x0092891B; +CHECKREG r5, 0xDF00AB1D; +CHECKREG r6, 0xDB7B5515; +CHECKREG r7, 0x0CCC7777; + +imm32 r0, 0x56678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34645515; +imm32 r3, 0x466a7717; +imm32 r4, 0x5678e91b; +imm32 r5, 0x6789af1d; +imm32 r6, 0x744455f5; +imm32 r7, 0x866677b7; +R6.H = R2.L + R3.L (S); +R1.H = R4.L + R5.H (S); +R5.H = R7.H + R2.L (S); +R3.H = R0.H + R0.H (S); +R0.H = R3.L + R4.L (S); +R2.H = R5.L + R7.H (S); +R7.H = R6.H + R7.L (S); +R4.H = R1.H + R6.H (S); +CHECKREG r4, 0x7FFFE91B; +CHECKREG r5, 0xDB7BAF1D; +CHECKREG r6, 0x7FFF55F5; +CHECKREG r7, 0x7FFF77B7; +CHECKREG r4, 0x7FFFE91B; +CHECKREG r5, 0xDB7BAF1D; +CHECKREG r6, 0x7FFF55F5; +CHECKREG r7, 0x7FFF77B7; + +imm32 r0, 0x95678911; +imm32 r1, 0x2989ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46967717; +imm32 r4, 0x5679891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74449515; +imm32 r7, 0x86667977; +R3.H = R4.L + R0.L (S); +R1.H = R6.L + R3.H (S); +R4.H = R3.H + R2.L (S); +R6.H = R7.H + R1.H (S); +R2.H = R5.L + R4.L (S); +R7.H = R2.L + R7.H (S); +R0.H = R1.H + R6.L (S); +R5.H = R0.H + R5.H (S); +CHECKREG r4, 0xD515891B; +CHECKREG r5, 0xE789AB1D; +CHECKREG r6, 0x80009515; +CHECKREG r7, 0xDB7B7977; +CHECKREG r4, 0xD515891B; +CHECKREG r5, 0xE789AB1D; +CHECKREG r6, 0x80009515; +CHECKREG r7, 0xDB7B7977; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rh_rnd12_m.s b/sim/testsuite/bfin/c_dsp32alu_rh_rnd12_m.s new file mode 100644 index 0000000..daf114a --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rh_rnd12_m.s @@ -0,0 +1,258 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_m/c_dsp32alu_rh_rnd12_m.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x45678ad1; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xf4445545; + imm32 r3, 0x46667767; + imm32 r4, 0xe678891b; + imm32 r5, 0x6f89ab1d; + imm32 r6, 0x7444d565; + imm32 r7, 0x8666b797; + R0.H = R0 - R0 (RND12); + R1.H = R0 - R1 (RND12); + R2.H = R0 - R2 (RND12); + R3.H = R0 - R3 (RND12); + R4.H = R0 - R4 (RND12); + R5.H = R0 - R5 (RND12); + R6.H = R0 - R6 (RND12); + R7.H = R0 - R7 (RND12); + CHECKREG r0, 0x00008AD1; + CHECKREG r1, 0x8000AB1D; + CHECKREG r2, 0x7fff5545; + CHECKREG r3, 0x80007767; + CHECKREG r4, 0x7fff891B; + CHECKREG r5, 0x8000AB1D; + CHECKREG r6, 0x8000D565; + CHECKREG r7, 0x7fffB797; + + imm32 r0, 0xd5678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xa4445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5b78891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74e45515; + imm32 r7, 0x86a6b777; + R0.H = R1 - R0 (RND12); + R1.H = R1 - R1 (RND12); + R2.H = R1 - R2 (RND12); + R3.H = R1 - R3 (RND12); + R4.H = R1 - R4 (RND12); + R5.H = R1 - R5 (RND12); + R6.H = R1 - R6 (RND12); + R7.H = R1 - R7 (RND12); + CHECKREG r0, 0x7fff8911; + CHECKREG r1, 0x0000AB1D; + CHECKREG r2, 0x7fff5515; + CHECKREG r3, 0x80007717; + CHECKREG r4, 0x8000891B; + CHECKREG r5, 0x8000AB1D; + CHECKREG r6, 0x80005515; + CHECKREG r7, 0x7fffB777; + + imm32 r0, 0xa5678091; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xb4445515; + imm32 r3, 0x46667717; + imm32 r4, 0xd678891b; + imm32 r5, 0x6e89ab4d; + imm32 r6, 0x74445567; + imm32 r7, 0x86967757; + R0.H = R2 - R0 (RND12); + R1.H = R2 - R1 (RND12); + R2.H = R2 - R2 (RND12); + R3.H = R2 - R3 (RND12); + R4.H = R2 - R4 (RND12); + R5.H = R2 - R5 (RND12); + R6.H = R2 - R6 (RND12); + R7.H = R2 - R7 (RND12); + CHECKREG r0, 0x7fff8091; + CHECKREG r1, 0x8000AB1D; + CHECKREG r2, 0x00005515; + CHECKREG r3, 0x80007717; + CHECKREG r4, 0x7fff891B; + CHECKREG r5, 0x8000AB4D; + CHECKREG r6, 0x80005567; + CHECKREG r7, 0x7fff7757; + + imm32 r0, 0x35678991; + imm32 r1, 0x2789ab8d; + imm32 r2, 0xd4445515; + imm32 r3, 0x46667737; + imm32 r4, 0x5678891b; + imm32 r5, 0xeab9ab4d; + imm32 r6, 0x744e5515; + imm32 r7, 0x866e747f; + R0.H = R3 - R0 (RND12); + R1.H = R3 - R1 (RND12); + R2.H = R3 - R2 (RND12); + R3.H = R3 - R3 (RND12); + R4.H = R3 - R4 (RND12); + R5.H = R3 - R5 (RND12); + R6.H = R3 - R6 (RND12); + R7.H = R3 - R7 (RND12); + CHECKREG r0, 0x7fff8991; + CHECKREG r1, 0x7fffAB8D; + CHECKREG r2, 0x7fff5515; + CHECKREG r3, 0x00007737; + CHECKREG r4, 0x8000891B; + CHECKREG r5, 0x7fffAB4D; + CHECKREG r6, 0x80005515; + CHECKREG r7, 0x7fff747F; + + imm32 r0, 0xe5678931; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34e45555; + imm32 r3, 0xd6667767; + imm32 r4, 0x5675891b; + imm32 r5, 0x6789abfd; + imm32 r6, 0xa4465515; + imm32 r7, 0x8b66e7b7; + R0.H = R4 - R0 (RND12); + R1.H = R4 - R1 (RND12); + R2.H = R4 - R2 (RND12); + R3.H = R4 - R3 (RND12); + R4.H = R4 - R4 (RND12); + R5.H = R4 - R5 (RND12); + R6.H = R4 - R6 (RND12); + R7.H = R4 - R7 (RND12); + CHECKREG r0, 0x7fff8931; + CHECKREG r1, 0x7fffAB1D; + CHECKREG r2, 0x7fff5555; + CHECKREG r3, 0x7fff7767; + CHECKREG r4, 0x0000891B; + CHECKREG r5, 0x8000ABFD; + CHECKREG r6, 0x7fff5515; + CHECKREG r7, 0x7fffE7B7; + + imm32 r0, 0x35678931; + imm32 r1, 0x2789ab4d; + imm32 r2, 0x3e445585; + imm32 r3, 0x46667717; + imm32 r4, 0xe6f8899b; + imm32 r5, 0x6789db1d; + imm32 r6, 0xf44a5515; + imm32 r7, 0x866b77b7; + R0.H = R5 - R0 (RND12); + R1.H = R5 - R1 (RND12); + R2.H = R5 - R2 (RND12); + R3.H = R5 - R3 (RND12); + R4.H = R5 - R4 (RND12); + R5.H = R5 - R5 (RND12); + R6.H = R5 - R6 (RND12); + R7.H = R5 - R7 (RND12); + CHECKREG r0, 0x7fff8931; + CHECKREG r1, 0x7fffAB4D; + CHECKREG r2, 0x7fff5585; + CHECKREG r3, 0x7fff7717; + CHECKREG r4, 0x7fff899B; + CHECKREG r5, 0x0000DB1D; + CHECKREG r6, 0x7fff5515; + CHECKREG r7, 0x7fff77B7; + + imm32 r0, 0xb5678911; + imm32 r1, 0xc789ab1d; + imm32 r2, 0x3ab45515; + imm32 r3, 0x466b7717; + imm32 r4, 0x4678e91b; + imm32 r5, 0x6789af1d; + imm32 r6, 0xf4445515; + imm32 r7, 0x86e6f777; + R0.H = R6 - R0 (RND12); + R1.H = R6 - R1 (RND12); + R2.H = R6 - R2 (RND12); + R3.H = R6 - R3 (RND12); + R4.H = R6 - R4 (RND12); + R5.H = R6 - R5 (RND12); + R6.H = R6 - R6 (RND12); + R7.H = R6 - R7 (RND12); + CHECKREG r0, 0x7fff8911; + CHECKREG r1, 0x7fffAB1D; + CHECKREG r2, 0x80005515; + CHECKREG r3, 0x80007717; + CHECKREG r4, 0x8000E91B; + CHECKREG r5, 0x8000AF1D; + CHECKREG r6, 0x00005515; + CHECKREG r7, 0x7fffF777; + + imm32 r0, 0xab678051; + imm32 r1, 0x2c89a26d; + imm32 r2, 0x34d455f5; + imm32 r3, 0x466e7717; + imm32 r4, 0x567f89bb; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x744e55a5; + imm32 r7, 0x8666ab77; + R0.H = R7 - R0 (RND12); + R1.H = R7 - R1 (RND12); + R2.H = R7 - R2 (RND12); + R3.H = R7 - R3 (RND12); + R4.H = R7 - R4 (RND12); + R5.H = R7 - R5 (RND12); + R6.H = R7 - R6 (RND12); + R7.H = R7 - R7 (RND12); + CHECKREG r0, 0x80008051; + CHECKREG r1, 0x8000A26D; + CHECKREG r2, 0x800055F5; + CHECKREG r3, 0x80007717; + CHECKREG r4, 0x800089BB; + CHECKREG r5, 0x8000AB1D; + CHECKREG r6, 0x800055A5; + CHECKREG r7, 0x0000AB77; + + imm32 r0, 0x15678901; + imm32 r1, 0x2789abad; + imm32 r2, 0x34445515; + imm32 r3, 0x466677d7; + imm32 r4, 0x5678891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445535; + imm32 r7, 0x86667747; + R6.H = R2 - R3 (RND12); + R1.H = R4 - R5 (RND12); + R5.H = R7 - R2 (RND12); + R3.H = R0 - R0 (RND12); + R0.H = R3 - R4 (RND12); + R2.H = R5 - R7 (RND12); + R7.H = R6 - R7 (RND12); + R4.H = R1 - R6 (RND12); + CHECKREG r0, 0x80008901; + CHECKREG r1, 0x8000ABAD; + CHECKREG r2, 0x99a35515; + CHECKREG r3, 0x000077D7; + CHECKREG r4, 0x0005891B; + CHECKREG r5, 0x8000AB1D; + CHECKREG r6, 0x80005535; + CHECKREG r7, 0x999e7747; + + imm32 r0, 0x15678121; + imm32 r1, 0x2789ab3d; + imm32 r2, 0x34445565; + imm32 r3, 0x4d667797; + imm32 r4, 0x567889ab; + imm32 r5, 0x67beabbd; + imm32 r6, 0x7b445515; + imm32 r7, 0x86d6e777; + R3.H = R4 - R0 (RND12); + R1.H = R6 - R3 (RND12); + R4.H = R3 - R2 (RND12); + R6.H = R7 - R1 (RND12); + R2.H = R5 - R4 (RND12); + R7.H = R2 - R7 (RND12); + R0.H = R1 - R6 (RND12); + R5.H = R0 - R5 (RND12); + CHECKREG r0, 0x7fff8121; + CHECKREG r1, 0xb44eAB3D; + CHECKREG r2, 0x80005565; + CHECKREG r3, 0x7fff7797; + CHECKREG r4, 0x7fff89AB; + CHECKREG r5, 0x7fffABBD; + CHECKREG r6, 0x80005515; + CHECKREG r7, 0x9297E777; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rh_rnd12_p.s b/sim/testsuite/bfin/c_dsp32alu_rh_rnd12_p.s new file mode 100644 index 0000000..fe54a86 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rh_rnd12_p.s @@ -0,0 +1,262 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_p/c_dsp32alu_rh_rnd12_p.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + + imm32 r0, 0x45678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xf4445515; + imm32 r3, 0x46667717; + imm32 r4, 0xe678891b; + imm32 r5, 0x6f89ab1d; + imm32 r6, 0x7444d515; + imm32 r7, 0x8666b777; + R0.H = R0 + R0 (RND12); + R1.H = R0 + R1 (RND12); + R2.H = R0 + R2 (RND12); + R3.H = R0 + R3 (RND12); + R4.H = R0 + R4 (RND12); + R5.H = R0 + R5 (RND12); + R6.H = R0 + R6 (RND12); + R7.H = R0 + R7 (RND12); + CHECKREG r0, 0x7FFF8911; + CHECKREG r1, 0x7fffAB1D; + CHECKREG r2, 0x7fff5515; + CHECKREG r3, 0x7fff7717; + CHECKREG r4, 0x7fff891B; + CHECKREG r5, 0x7fffAB1D; + CHECKREG r6, 0x7fffD515; + CHECKREG r7, 0x6664B777; + + imm32 r0, 0xd5678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xa4445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5b78891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74e45515; + imm32 r7, 0x86a6b777; + R0.H = R1 + R0 (RND12); + R1.H = R1 + R1 (RND12); + R2.H = R1 + R2 (RND12); + R3.H = R1 + R3 (RND12); + R4.H = R1 + R4 (RND12); + R5.H = R1 + R5 (RND12); + R6.H = R1 + R6 (RND12); + R7.H = R1 + R7 (RND12); + CHECKREG r0, 0xcf138911; + CHECKREG r1, 0x7FFFAB1D; + CHECKREG r2, 0x7fff5515; + CHECKREG r3, 0x7fff7717; + CHECKREG r4, 0x7fff891B; + CHECKREG r5, 0x7fffAB1D; + CHECKREG r6, 0x7fff5515; + CHECKREG r7, 0x6A66B777; + + imm32 r0, 0xa5678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xb4445515; + imm32 r3, 0x46667717; + imm32 r4, 0xd678891b; + imm32 r5, 0x6e89ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86967777; + R0.H = R2 + R0 (RND12); + R1.H = R2 + R1 (RND12); + R2.H = R2 + R2 (RND12); + R3.H = R2 + R3 (RND12); + R4.H = R2 + R4 (RND12); + R5.H = R2 + R5 (RND12); + R6.H = R2 + R6 (RND12); + R7.H = R2 + R7 (RND12); + CHECKREG r4, 0x8000891B; + CHECKREG r5, 0x8000AB1D; + CHECKREG r6, 0x80005515; + CHECKREG r7, 0x80007777; + CHECKREG r4, 0x8000891B; + CHECKREG r5, 0x8000AB1D; + CHECKREG r6, 0x80005515; + CHECKREG r7, 0x80007777; + + imm32 r0, 0x35678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xd4445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5678891b; + imm32 r5, 0xeab9ab1d; + imm32 r6, 0x744e5515; + imm32 r7, 0x866e777f; + R0.H = R3 + R0 (RND12); + R1.H = R3 + R1 (RND12); + R2.H = R3 + R2 (RND12); + R3.H = R3 + R3 (RND12); + R4.H = R3 + R4 (RND12); + R5.H = R3 + R5 (RND12); + R6.H = R3 + R6 (RND12); + R7.H = R3 + R7 (RND12); + CHECKREG r0, 0x7FFF8911; + CHECKREG r1, 0x7FFFAB1D; + CHECKREG r2, 0x7FFF5515; + CHECKREG r3, 0x7FFF7717; + CHECKREG r4, 0x7fff891B; + CHECKREG r5, 0x7fffAB1D; + CHECKREG r6, 0x7fff5515; + CHECKREG r7, 0x66df777F; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34e45515; + imm32 r3, 0xd6667717; + imm32 r4, 0x5675891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0xa4465515; + imm32 r7, 0x8b66e777; + R0.H = R4 + R0 (RND12); + R1.H = R4 + R1 (RND12); + R2.H = R4 + R2 (RND12); + R3.H = R4 + R3 (RND12); + R4.H = R4 + R4 (RND12); + R5.H = R4 + R5 (RND12); + R6.H = R4 + R6 (RND12); + R7.H = R4 + R7 (RND12); + CHECKREG r0, 0x7FFF8911; + CHECKREG r1, 0x7FFFAB1D; + CHECKREG r2, 0x7FFF5515; + CHECKREG r3, 0x7FFF7717; + CHECKREG r4, 0x7FFF891B; + CHECKREG r5, 0x7fffAB1D; + CHECKREG r6, 0x7fff5515; + CHECKREG r7, 0x7fffE777; + + imm32 r0, 0x35678111; + imm32 r1, 0x2789a21d; + imm32 r2, 0x3e445535; + imm32 r3, 0x46667757; + imm32 r4, 0xe6f8891b; + imm32 r5, 0x6789db7d; + imm32 r6, 0xf44a5595; + imm32 r7, 0x866b7770; + R0.H = R5 + R0 (RND12); + R1.H = R5 + R1 (RND12); + R2.H = R5 + R2 (RND12); + R3.H = R5 + R3 (RND12); + R4.H = R5 + R4 (RND12); + R5.H = R5 + R5 (RND12); + R6.H = R5 + R6 (RND12); + R7.H = R5 + R7 (RND12); + CHECKREG r0, 0x7FFF8111; + CHECKREG r1, 0x7FFFA21D; + CHECKREG r2, 0x7fff5535; + CHECKREG r3, 0x7FFF7757; + CHECKREG r4, 0x7FFF891B; + CHECKREG r5, 0x7FFFDB7D; + CHECKREG r6, 0x7fff5595; + CHECKREG r7, 0x66b57770; + + imm32 r0, 0xb5678911; + imm32 r1, 0xc789ab1d; + imm32 r2, 0x3ab45515; + imm32 r3, 0x466b7717; + imm32 r4, 0x4678e91b; + imm32 r5, 0x6789af1d; + imm32 r6, 0xf4445515; + imm32 r7, 0x86e6f777; + R0.H = R6 + R0 (RND12); + R1.H = R6 + R1 (RND12); + R2.H = R6 + R2 (RND12); + R3.H = R6 + R3 (RND12); + R4.H = R6 + R4 (RND12); + R5.H = R6 + R5 (RND12); + R6.H = R6 + R6 (RND12); + R7.H = R6 + R7 (RND12); + CHECKREG r0, 0x80008911; + CHECKREG r1, 0x8000AB1D; + CHECKREG r2, 0x7fff5515; + CHECKREG r3, 0x7FFF7717; + CHECKREG r4, 0x7FFFE91B; + CHECKREG r5, 0x7FFFAF1D; + CHECKREG r6, 0x80005515; + CHECKREG r7, 0x8000F777; + + imm32 r0, 0xab678021; + imm32 r1, 0x2c89a33d; + imm32 r2, 0x34d45575; + imm32 r3, 0x466e7797; + imm32 r4, 0x567f89fb; + imm32 r5, 0x6789abdd; + imm32 r6, 0x744e5515; + imm32 r7, 0x8666ab87; + R0.H = R7 + R0 (RND12); + R1.H = R7 + R1 (RND12); + R2.H = R7 + R2 (RND12); + R3.H = R7 + R3 (RND12); + R4.H = R7 + R4 (RND12); + R5.H = R7 + R5 (RND12); + R6.H = R7 + R6 (RND12); + R7.H = R7 + R7 (RND12); + CHECKREG r0, 0x80008021; + CHECKREG r1, 0x8000A33D; + CHECKREG r2, 0x80005575; + CHECKREG r3, 0x80007797; + CHECKREG r4, 0x800089FB; + CHECKREG r5, 0x8000ABDD; + CHECKREG r6, 0xab505515; + CHECKREG r7, 0x8000AB87; + + imm32 r0, 0x15678901; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445535; + imm32 r3, 0x46667747; + imm32 r4, 0x56788915; + imm32 r5, 0x6789ab6d; + imm32 r6, 0x74445518; + imm32 r7, 0x86667797; + R6.H = R2 + R3 (RND12); + R1.H = R4 + R5 (RND12); + R5.H = R7 + R2 (RND12); + R3.H = R0 + R0 (RND12); + R0.H = R3 + R4 (RND12); + R2.H = R5 + R7 (RND12); + R7.H = R6 + R7 (RND12); + R4.H = R1 + R6 (RND12); + CHECKREG r0, 0x7fff8901; + CHECKREG r1, 0x7FFFAB2D; + CHECKREG r2, 0x80005535; + CHECKREG r3, 0x7FFF7747; + CHECKREG r4, 0x7fff8915; + CHECKREG r5, 0x8000AB6D; + CHECKREG r6, 0x7FFF5518; + CHECKREG r7, 0x665D7797; + + imm32 r0, 0x35678911; + imm32 r1, 0x2489ab1d; + imm32 r2, 0x34545565; + imm32 r3, 0x4d6677b7; + imm32 r4, 0x567889db; + imm32 r5, 0x67beab1d; + imm32 r6, 0x7b445595; + imm32 r7, 0x86d6e707; + R3.H = R4 + R0 (RND12); + R1.H = R6 + R3 (RND12); + R4.H = R3 + R2 (RND12); + R6.H = R7 + R1 (RND12); + R2.H = R5 + R4 (RND12); + R7.H = R2 + R7 (RND12); + R0.H = R1 + R6 (RND12); + R5.H = R0 + R5 (RND12); + CHECKREG r0, 0x7fff8911; + CHECKREG r1, 0x7fffAB1D; + CHECKREG r2, 0x7FFF5565; + CHECKREG r3, 0x7FFF77B7; + CHECKREG r4, 0x7fff89DB; + CHECKREG r5, 0x7FFFAB1D; + CHECKREG r6, 0x6d695595; + CHECKREG r7, 0x6D64E707; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rh_rnd20_m.s b/sim/testsuite/bfin/c_dsp32alu_rh_rnd20_m.s new file mode 100644 index 0000000..8283394 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rh_rnd20_m.s @@ -0,0 +1,258 @@ +//Original:/testcases/core/c_dsp32alu_rh_rnd20_m/c_dsp32alu_rh_rnd20_m.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34a45515; +imm32 r3, 0x46a67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678aab1d; +imm32 r6, 0x7444a515; +imm32 r7, 0x86667a77; +R0.H = R0 - R0 (RND20); +R1.H = R0 - R1 (RND20); +R2.H = R0 - R2 (RND20); +R3.H = R0 - R3 (RND20); +R4.H = R0 - R4 (RND20); +R5.H = R0 - R5 (RND20); +R6.H = R0 - R6 (RND20); +R7.H = R0 - R7 (RND20); +CHECKREG r0, 0x00008911; +CHECKREG r1, 0xFD57AB1D; +CHECKREG r2, 0xFCB65515; +CHECKREG r3, 0xFB967717; +CHECKREG r4, 0xFA98891B; +CHECKREG r5, 0xF987AB1D; +CHECKREG r6, 0xF8BCA515; +CHECKREG r7, 0x079A7A77; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0xb4445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5b78891b; +imm32 r5, 0x67bbab1d; +imm32 r6, 0x7444b515; +imm32 r7, 0x86667b77; +R0.H = R1 - R0 (RND20); +R1.H = R1 - R1 (RND20); +R2.H = R1 - R2 (RND20); +R3.H = R1 - R3 (RND20); +R4.H = R1 - R4 (RND20); +R5.H = R1 - R5 (RND20); +R6.H = R1 - R6 (RND20); +R7.H = R1 - R7 (RND20); +CHECKREG r0, 0x08228911; +CHECKREG r1, 0x0000AB1D; +CHECKREG r2, 0x04BC5515; +CHECKREG r3, 0xFB9A7717; +CHECKREG r4, 0xFA49891B; +CHECKREG r5, 0xF984AB1D; +CHECKREG r6, 0xF8BCB515; +CHECKREG r7, 0x079A7B77; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x3a445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x567a891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445a15; +imm32 r7, 0x866677a7; +R0.H = R2 - R0 (RND20); +R1.H = R2 - R1 (RND20); +R2.H = R2 - R2 (RND20); +R3.H = R2 - R3 (RND20); +R4.H = R2 - R4 (RND20); +R5.H = R2 - R5 (RND20); +R6.H = R2 - R6 (RND20); +R7.H = R2 - R7 (RND20); +CHECKREG r0, 0x094E8911; +CHECKREG r1, 0x00FCAB1D; +CHECKREG r2, 0x00005515; +CHECKREG r3, 0xFB967717; +CHECKREG r4, 0xFA98891B; +CHECKREG r5, 0xF987AB1D; +CHECKREG r6, 0xF8BC5A15; +CHECKREG r7, 0x079A77A7; + +imm32 r0, 0xb5678911; +imm32 r1, 0xb789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678ddb1d; +imm32 r6, 0x74445d15; +imm32 r7, 0x866677d7; +R0.H = R3 - R0 (RND20); +R1.H = R3 - R1 (RND20); +R2.H = R3 - R2 (RND20); +R3.H = R3 - R3 (RND20); +R4.H = R3 - R4 (RND20); +R5.H = R3 - R5 (RND20); +R6.H = R3 - R6 (RND20); +R7.H = R3 - R7 (RND20); +CHECKREG r0, 0x09178911; +CHECKREG r1, 0x08F5AB1D; +CHECKREG r2, 0x00995515; +CHECKREG r3, 0x00007717; +CHECKREG r4, 0xFA98891B; +CHECKREG r5, 0xF987DB1D; +CHECKREG r6, 0xF8BC5D15; +CHECKREG r7, 0x079A77D7; + +imm32 r0, 0xd5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0xd4445515; +imm32 r3, 0xd6667717; +imm32 r4, 0x5d78891b; +imm32 r5, 0x67d9ab1d; +imm32 r6, 0x744d5515; +imm32 r7, 0x8666dd77; +R0.H = R4 - R0 (RND20); +R1.H = R4 - R1 (RND20); +R2.H = R4 - R2 (RND20); +R3.H = R4 - R3 (RND20); +R4.H = R4 - R4 (RND20); +R5.H = R4 - R5 (RND20); +R6.H = R4 - R6 (RND20); +R7.H = R4 - R7 (RND20); +CHECKREG r0, 0x08818911; +CHECKREG r1, 0x035FAB1D; +CHECKREG r2, 0x08935515; +CHECKREG r3, 0x08717717; +CHECKREG r4, 0x0000891B; +CHECKREG r5, 0xF982AB1D; +CHECKREG r6, 0xF8BB5515; +CHECKREG r7, 0x079ADD77; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34d45515; +imm32 r3, 0x46667717; +imm32 r4, 0x567d891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x74445d15; +imm32 r7, 0x866677d7; +R0.H = R5 - R0 (RND20); +R1.H = R5 - R1 (RND20); +R2.H = R5 - R2 (RND20); +R3.H = R5 - R3 (RND20); +R4.H = R5 - R4 (RND20); +R5.H = R5 - R5 (RND20); +R6.H = R5 - R6 (RND20); +R7.H = R5 - R7 (RND20); +CHECKREG r0, 0x08228911; +CHECKREG r1, 0x0390AB1D; +CHECKREG r2, 0x032B5515; +CHECKREG r3, 0x02127717; +CHECKREG r4, 0x0111891B; +CHECKREG r5, 0x0000DB1D; +CHECKREG r6, 0xF8BC5D15; +CHECKREG r7, 0x079A77D7; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34a45515; +imm32 r3, 0x46a67717; +imm32 r4, 0x56a8891b; +imm32 r5, 0x678aab1d; +imm32 r6, 0x7444a515; +imm32 r7, 0x86667a77; +R0.H = R6 - R0 (RND20); +R1.H = R6 - R1 (RND20); +R2.H = R6 - R2 (RND20); +R3.H = R6 - R3 (RND20); +R4.H = R6 - R4 (RND20); +R5.H = R6 - R5 (RND20); +R6.H = R6 - R6 (RND20); +R7.H = R6 - R7 (RND20); +CHECKREG r0, 0x0CEE8911; +CHECKREG r1, 0x049CAB1D; +CHECKREG r2, 0x03FA5515; +CHECKREG r3, 0x02DA7717; +CHECKREG r4, 0x01DA891B; +CHECKREG r5, 0x00CCAB1D; +CHECKREG r6, 0x0000A515; +CHECKREG r7, 0x079A7A77; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.H = R7 - R0 (RND20); +R1.H = R7 - R1 (RND20); +R2.H = R7 - R2 (RND20); +R3.H = R7 - R3 (RND20); +R4.H = R7 - R4 (RND20); +R5.H = R7 - R5 (RND20); +R6.H = R7 - R6 (RND20); +R7.H = R7 - R7 (RND20); +CHECKREG r0, 0xF7108911; +CHECKREG r1, 0xF5EEAB1D; +CHECKREG r2, 0xF5225515; +CHECKREG r3, 0xF4007717; +CHECKREG r4, 0xF2FF891B; +CHECKREG r5, 0xF1EEAB1D; +CHECKREG r6, 0xF1225515; +CHECKREG r7, 0x00007777; + +imm32 r0, 0xe5678911; +imm32 r1, 0xe789ab1d; +imm32 r2, 0xe4445515; +imm32 r3, 0x4ee67717; +imm32 r4, 0x567e891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444e515; +imm32 r7, 0x86667e77; +R6.H = R2 - R3 (RND20); +R1.H = R4 - R5 (RND20); +R5.H = R7 - R2 (RND20); +R3.H = R0 - R0 (RND20); +R0.H = R3 - R4 (RND20); +R2.H = R5 - R7 (RND20); +R7.H = R6 - R7 (RND20); +R4.H = R1 - R6 (RND20); +CHECKREG r0, 0xFA988911; +CHECKREG r1, 0xFEEFAB1D; +CHECKREG r2, 0x073C5515; +CHECKREG r3, 0x00007717; +CHECKREG r4, 0x005A891B; +CHECKREG r5, 0xFA22AB1D; +CHECKREG r6, 0xF956E515; +CHECKREG r7, 0x072F7E77; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x567d891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R3.H = R4 - R0 (RND20); +R1.H = R6 - R3 (RND20); +R4.H = R3 - R2 (RND20); +R6.H = R7 - R1 (RND20); +R2.H = R5 - R4 (RND20); +R7.H = R2 - R7 (RND20); +R0.H = R1 - R6 (RND20); +R5.H = R0 - R5 (RND20); +CHECKREG r0, 0x00EE8911; +CHECKREG r1, 0x06D3AB1D; +CHECKREG r2, 0x06AF5515; +CHECKREG r3, 0x07117717; +CHECKREG r4, 0xFC9D891B; +CHECKREG r5, 0xF996DB1D; +CHECKREG r6, 0xF7F9D515; +CHECKREG r7, 0x08057D77; + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rh_rnd20_p.s b/sim/testsuite/bfin/c_dsp32alu_rh_rnd20_p.s new file mode 100644 index 0000000..231db02 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rh_rnd20_p.s @@ -0,0 +1,258 @@ +//Original:/testcases/core/c_dsp32alu_rh_rnd20_p/c_dsp32alu_rh_rnd20_p.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34a45515; +imm32 r3, 0x46a67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678aab1d; +imm32 r6, 0x7444a515; +imm32 r7, 0x86667a77; +R0.H = R0 + R0 (RND20); +R1.H = R0 + R1 (RND20); +R2.H = R0 + R2 (RND20); +R3.H = R0 + R3 (RND20); +R4.H = R0 + R4 (RND20); +R5.H = R0 + R5 (RND20); +R6.H = R0 + R6 (RND20); +R7.H = R0 + R7 (RND20); +CHECKREG r0, 0xF4AD8911; +CHECKREG r1, 0x01F3AB1D; +CHECKREG r2, 0x02955515; +CHECKREG r3, 0x03B57717; +CHECKREG r4, 0x04B2891B; +CHECKREG r5, 0x05C4AB1D; +CHECKREG r6, 0x068FA515; +CHECKREG r7, 0xF7B17A77; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0xb4445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5b78891b; +imm32 r5, 0x67bbab1d; +imm32 r6, 0x7444b515; +imm32 r7, 0x86667b77; +R0.H = R1 + R0 (RND20); +R1.H = R1 + R1 (RND20); +R2.H = R1 + R2 (RND20); +R3.H = R1 + R3 (RND20); +R4.H = R1 + R4 (RND20); +R5.H = R1 + R5 (RND20); +R6.H = R1 + R6 (RND20); +R7.H = R1 + R7 (RND20); +CHECKREG r0, 0xFCCF8911; +CHECKREG r1, 0x04F1AB1D; +CHECKREG r2, 0xFB935515; +CHECKREG r3, 0x04B67717; +CHECKREG r4, 0x0607891B; +CHECKREG r5, 0x06CBAB1D; +CHECKREG r6, 0x0793B515; +CHECKREG r7, 0xF8B67B77; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x3a445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x567a891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445a15; +imm32 r7, 0x866677a7; +R0.H = R2 + R0 (RND20); +R1.H = R2 + R1 (RND20); +R2.H = R2 + R2 (RND20); +R3.H = R2 + R3 (RND20); +R4.H = R2 + R4 (RND20); +R5.H = R2 + R5 (RND20); +R6.H = R2 + R6 (RND20); +R7.H = R2 + R7 (RND20); +CHECKREG r0, 0xFDFB8911; +CHECKREG r1, 0x064DAB1D; +CHECKREG r2, 0x07495515; +CHECKREG r3, 0x04DF7717; +CHECKREG r4, 0x05DC891B; +CHECKREG r5, 0x06EDAB1D; +CHECKREG r6, 0x07B95A15; +CHECKREG r7, 0xF8DB77A7; + +imm32 r0, 0xb5678911; +imm32 r1, 0xb789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678ddb1d; +imm32 r6, 0x74445d15; +imm32 r7, 0x866677d7; +R0.H = R3 + R0 (RND20); +R1.H = R3 + R1 (RND20); +R2.H = R3 + R2 (RND20); +R3.H = R3 + R3 (RND20); +R4.H = R3 + R4 (RND20); +R5.H = R3 + R5 (RND20); +R6.H = R3 + R6 (RND20); +R7.H = R3 + R7 (RND20); +CHECKREG r0, 0xFFC48911; +CHECKREG r1, 0xFFE6AB1D; +CHECKREG r2, 0x08425515; +CHECKREG r3, 0x08DB7717; +CHECKREG r4, 0x05F5891B; +CHECKREG r5, 0x0707DB1D; +CHECKREG r6, 0x07D25D15; +CHECKREG r7, 0xF8F477D7; + +imm32 r0, 0xd5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0xd4445515; +imm32 r3, 0xd6667717; +imm32 r4, 0x5d78891b; +imm32 r5, 0x67d9ab1d; +imm32 r6, 0x744d5515; +imm32 r7, 0x8666dd77; +R0.H = R4 + R0 (RND20); +R1.H = R4 + R1 (RND20); +R2.H = R4 + R2 (RND20); +R3.H = R4 + R3 (RND20); +R4.H = R4 + R4 (RND20); +R5.H = R4 + R5 (RND20); +R6.H = R4 + R6 (RND20); +R7.H = R4 + R7 (RND20); +CHECKREG r0, 0x032E8911; +CHECKREG r1, 0x0850AB1D; +CHECKREG r2, 0x031C5515; +CHECKREG r3, 0x033E7717; +CHECKREG r4, 0x0BAF891B; +CHECKREG r5, 0x0739AB1D; +CHECKREG r6, 0x08005515; +CHECKREG r7, 0xF921DD77; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34d45515; +imm32 r3, 0x46667717; +imm32 r4, 0x567d891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x74445d15; +imm32 r7, 0x866677d7; +R0.H = R5 + R0 (RND20); +R1.H = R5 + R1 (RND20); +R2.H = R5 + R2 (RND20); +R3.H = R5 + R3 (RND20); +R4.H = R5 + R4 (RND20); +R5.H = R5 + R5 (RND20); +R6.H = R5 + R6 (RND20); +R7.H = R5 + R7 (RND20); +CHECKREG r0, 0x04CF8911; +CHECKREG r1, 0x0961AB1D; +CHECKREG r2, 0x09C65515; +CHECKREG r3, 0x0ADF7717; +CHECKREG r4, 0x0BE0891B; +CHECKREG r5, 0x0CF1DB1D; +CHECKREG r6, 0x08135D15; +CHECKREG r7, 0xF93677D7; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34a45515; +imm32 r3, 0x46a67717; +imm32 r4, 0x56a8891b; +imm32 r5, 0x678aab1d; +imm32 r6, 0x7444a515; +imm32 r7, 0x86667a77; +R0.H = R6 + R0 (RND20); +R1.H = R6 + R1 (RND20); +R2.H = R6 + R2 (RND20); +R3.H = R6 + R3 (RND20); +R4.H = R6 + R4 (RND20); +R5.H = R6 + R5 (RND20); +R6.H = R6 + R6 (RND20); +R7.H = R6 + R7 (RND20); +CHECKREG r0, 0x019B8911; +CHECKREG r1, 0x09EDAB1D; +CHECKREG r2, 0x0A8F5515; +CHECKREG r3, 0x0BAF7717; +CHECKREG r4, 0x0CAF891B; +CHECKREG r5, 0x0DBDAB1D; +CHECKREG r6, 0x0E89A515; +CHECKREG r7, 0xF94F7A77; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.H = R7 + R0 (RND20); +R1.H = R7 + R1 (RND20); +R2.H = R7 + R2 (RND20); +R3.H = R7 + R3 (RND20); +R4.H = R7 + R4 (RND20); +R5.H = R7 + R5 (RND20); +R6.H = R7 + R6 (RND20); +R7.H = R7 + R7 (RND20); +CHECKREG r0, 0xF9BD8911; +CHECKREG r1, 0xFADFAB1D; +CHECKREG r2, 0xFBAB5515; +CHECKREG r3, 0xFCCD7717; +CHECKREG r4, 0xFDCE891B; +CHECKREG r5, 0xFEDFAB1D; +CHECKREG r6, 0xFFAB5515; +CHECKREG r7, 0xF0CD7777; + +imm32 r0, 0xe5678911; +imm32 r1, 0xe789ab1d; +imm32 r2, 0xe4445515; +imm32 r3, 0x4ee67717; +imm32 r4, 0x567e891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444e515; +imm32 r7, 0x86667e77; +R6.H = R2 + R3 (RND20); +R1.H = R4 + R5 (RND20); +R5.H = R7 + R2 (RND20); +R3.H = R0 + R0 (RND20); +R0.H = R3 + R4 (RND20); +R2.H = R5 + R7 (RND20); +R7.H = R6 + R7 (RND20); +R4.H = R1 + R6 (RND20); +CHECKREG r0, 0x05338911; +CHECKREG r1, 0x0BE1AB1D; +CHECKREG r2, 0xF7D15515; +CHECKREG r3, 0xFCAD7717; +CHECKREG r4, 0x00F1891B; +CHECKREG r5, 0xF6ABAB1D; +CHECKREG r6, 0x0333E515; +CHECKREG r7, 0xF89A7E77; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x567d891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R3.H = R4 + R0 (RND20); +R1.H = R6 + R3 (RND20); +R4.H = R3 + R2 (RND20); +R6.H = R7 + R1 (RND20); +R2.H = R5 + R4 (RND20); +R7.H = R2 + R7 (RND20); +R0.H = R1 + R6 (RND20); +R5.H = R0 + R5 (RND20); +CHECKREG r0, 0x00068911; +CHECKREG r1, 0x0780AB1D; +CHECKREG r2, 0x06BA5515; +CHECKREG r3, 0x03BE7717; +CHECKREG r4, 0x0410891B; +CHECKREG r5, 0x0679DB1D; +CHECKREG r6, 0xF8DED515; +CHECKREG r7, 0xF8D27D77; + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rl_m.s b/sim/testsuite/bfin/c_dsp32alu_rl_m.s new file mode 100644 index 0000000..d942d91 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rl_m.s @@ -0,0 +1,263 @@ +//Original:/testcases/core/c_dsp32alu_rl_m/c_dsp32alu_rl_m.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x55678911; +imm32 r1, 0x2759ab1d; +imm32 r2, 0x34455515; +imm32 r3, 0x46665717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789a51d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R0.L - R0.L (NS); +R1.L = R0.L - R1.H (NS); +R2.L = R0.H - R2.L (NS); +R3.L = R0.H - R3.H (NS); +R4.L = R0.L - R4.L (NS); +R5.L = R0.L - R5.H (NS); +R6.L = R0.H - R6.L (NS); +R7.L = R0.H - R7.H (NS); +CHECKREG r4, 0x567876E5; +CHECKREG r5, 0x67899877; +CHECKREG r6, 0x74440052; +CHECKREG r7, 0x8666CF01; +CHECKREG r4, 0x567876E5; +CHECKREG r5, 0x67899877; +CHECKREG r6, 0x74440052; +CHECKREG r7, 0x8666CF01; + +imm32 r0, 0x44678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x344d5515; +imm32 r3, 0x4666d717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789cc1d; +imm32 r6, 0x74445c15; +imm32 r7, 0x86667c77; +R0.L = R1.L - R0.L (NS); +R1.L = R1.L - R1.H (NS); +R2.L = R1.H - R2.L (NS); +R3.L = R1.H - R3.H (NS); +R4.L = R1.L - R4.L (NS); +R5.L = R1.L - R5.H (NS); +R6.L = R1.H - R6.L (NS); +R7.L = R1.H - R7.H (NS); +CHECKREG r4, 0x5678FA79; +CHECKREG r5, 0x67891C0B; +CHECKREG r6, 0x7444CB74; +CHECKREG r7, 0x8666A123; +CHECKREG r4, 0x5678FA79; +CHECKREG r5, 0x67891C0B; +CHECKREG r6, 0x7444CB74; +CHECKREG r7, 0x8666A123; + +imm32 r0, 0xcc678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34c45515; +imm32 r3, 0x466c7717; +imm32 r4, 0x5678c91b; +imm32 r5, 0x6789ac1d; +imm32 r6, 0x74445515; +imm32 r7, 0x866677c7; +R0.L = R2.L - R0.L (NS); +R1.L = R2.L - R1.H (NS); +R2.L = R2.H - R2.L (NS); +R3.L = R2.H - R3.H (NS); +R4.L = R2.L - R4.L (NS); +R5.L = R2.L - R5.H (NS); +R6.L = R2.H - R6.L (NS); +R7.L = R2.H - R7.H (NS); +CHECKREG r4, 0x56781694; +CHECKREG r5, 0x67897826; +CHECKREG r6, 0x7444DFAF; +CHECKREG r7, 0x8666AE5E; +CHECKREG r4, 0x56781694; +CHECKREG r5, 0x67897826; +CHECKREG r6, 0x7444DFAF; +CHECKREG r7, 0x8666AE5E; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R3.L - R0.L (NS); +R1.L = R3.L - R1.H (NS); +R2.L = R3.H - R2.L (NS); +R3.L = R3.H - R3.H (NS); +R4.L = R3.L - R4.L (NS); +R5.L = R3.L - R5.H (NS); +R6.L = R3.H - R6.L (NS); +R7.L = R3.H - R7.H (NS); +CHECKREG r4, 0x567876E5; +CHECKREG r5, 0x67899877; +CHECKREG r6, 0x7444F151; +CHECKREG r7, 0x8666C000; +CHECKREG r4, 0x567876E5; +CHECKREG r5, 0x67899877; +CHECKREG r6, 0x7444F151; +CHECKREG r7, 0x8666C000; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34e45515; +imm32 r3, 0x466e7717; +imm32 r4, 0x5678e91b; +imm32 r5, 0x6789ae1d; +imm32 r6, 0x744455e5; +imm32 r7, 0x8666777e; +R0.L = R4.L - R0.L (NS); +R1.L = R4.L - R1.H (NS); +R2.L = R4.H - R2.L (NS); +R3.L = R4.H - R3.H (NS); +R4.L = R4.L - R4.L (NS); +R5.L = R4.L - R5.H (NS); +R6.L = R4.H - R6.L (NS); +R7.L = R4.H - R7.H (NS); +CHECKREG r4, 0x56780000; +CHECKREG r5, 0x67899877; +CHECKREG r6, 0x74440093; +CHECKREG r7, 0x8666D012; +CHECKREG r4, 0x56780000; +CHECKREG r5, 0x67899877; +CHECKREG r6, 0x74440093; +CHECKREG r7, 0x8666D012; + +imm32 r0, 0xdd678911; +imm32 r1, 0xd789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x567d891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x74445d15; +imm32 r7, 0x866677d7; +R0.L = R5.L - R0.L (NS); +R1.L = R5.L - R1.H (NS); +R2.L = R5.H - R2.L (NS); +R3.L = R5.H - R3.H (NS); +R4.L = R5.L - R4.L (NS); +R5.L = R5.L - R5.H (NS); +R6.L = R5.H - R6.L (NS); +R7.L = R5.H - R7.H (NS); +CHECKREG r4, 0x567D5202; +CHECKREG r5, 0x67897394; +CHECKREG r6, 0x74440A74; +CHECKREG r7, 0x8666E123; +CHECKREG r4, 0x567D5202; +CHECKREG r5, 0x67897394; +CHECKREG r6, 0x74440A74; +CHECKREG r7, 0x8666E123; + +imm32 r0, 0x85678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x38445515; +imm32 r3, 0x46667717; +imm32 r4, 0x568a891b; +imm32 r5, 0x67a9ab1d; +imm32 r6, 0x744a5515; +imm32 r7, 0x8666aa77; +R0.L = R6.L - R0.L (NS); +R1.L = R6.L - R1.H (NS); +R2.L = R6.H - R2.L (NS); +R3.L = R6.H - R3.H (NS); +R4.L = R6.L - R4.L (NS); +R5.L = R6.L - R5.H (NS); +R6.L = R6.H - R6.L (NS); +R7.L = R6.H - R7.H (NS); +CHECKREG r4, 0x568ACBFA; +CHECKREG r5, 0x67A9ED6C; +CHECKREG r6, 0x744A1F35; +CHECKREG r7, 0x8666EDE4; +CHECKREG r4, 0x568ACBFA; +CHECKREG r5, 0x67A9ED6C; +CHECKREG r6, 0x744A1F35; +CHECKREG r7, 0x8666EDE4; + +imm32 r0, 0x35678911; +imm32 r1, 0x2389ab1d; +imm32 r2, 0x34845515; +imm32 r3, 0x466a7717; +imm32 r4, 0x5678a91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445b15; +imm32 r7, 0x866677b7; +R0.L = R7.L - R0.L (NS); +R1.L = R7.L - R1.H (NS); +R2.L = R7.H - R2.L (NS); +R3.L = R7.H - R3.H (NS); +R4.L = R7.L - R4.L (NS); +R5.L = R7.L - R5.H (NS); +R6.L = R7.H - R6.L (NS); +R7.L = R7.H - R7.H (NS); +CHECKREG r4, 0x5678CE9C; +CHECKREG r5, 0x6789102E; +CHECKREG r6, 0x74442B51; +CHECKREG r7, 0x86660000; +CHECKREG r4, 0x5678CE9C; +CHECKREG r5, 0x6789102E; +CHECKREG r6, 0x74442B51; +CHECKREG r7, 0x86660000; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R6.L = R2.L - R3.L (S); +R1.L = R4.L - R5.H (S); +R5.L = R7.H - R2.L (S); +R3.L = R0.H - R0.H (S); +R0.L = R3.L - R4.L (S); +R2.L = R5.L - R7.H (S); +R7.L = R6.H - R7.L (S); +R4.L = R1.H - R6.H (S); +CHECKREG r4, 0x5678B345; +CHECKREG r5, 0x67898000; +CHECKREG r6, 0x7444DDFE; +CHECKREG r7, 0x8666FCCD; +CHECKREG r4, 0x5678B345; +CHECKREG r5, 0x67898000; +CHECKREG r6, 0x7444DDFE; +CHECKREG r7, 0x8666FCCD; + +imm32 r0, 0x1d678911; +imm32 r1, 0x27d9ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x466d7717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789dd1d; +imm32 r6, 0x74445515; +imm32 r7, 0x866677d7; +R3.L = R4.L - R0.L (S); +R1.L = R6.L - R3.H (S); +R4.L = R3.H - R2.L (S); +R6.L = R7.H - R1.H (S); +R2.L = R5.L - R4.L (S); +R7.L = R2.L - R7.H (S); +R0.L = R1.H - R6.L (S); +R5.L = R0.H - R5.H (S); +CHECKREG r4, 0x5678F158; +CHECKREG r5, 0x6789B5DE; +CHECKREG r6, 0x74448000; +CHECKREG r7, 0x8666655F; +CHECKREG r4, 0x5678F158; +CHECKREG r5, 0x6789B5DE; +CHECKREG r6, 0x74448000; +CHECKREG r7, 0x8666655F; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rl_p.s b/sim/testsuite/bfin/c_dsp32alu_rl_p.s new file mode 100644 index 0000000..3c037bd --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rl_p.s @@ -0,0 +1,263 @@ +//Original:/testcases/core/c_dsp32alu_rl_p/c_dsp32alu_rl_p.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x19678911; +imm32 r1, 0x2799ab1d; +imm32 r2, 0x34945515; +imm32 r3, 0x46967717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86669977; +R0.L = R0.L + R0.L (NS); +R1.L = R0.L + R1.H (NS); +R2.L = R0.H + R2.L (NS); +R3.L = R0.H + R3.H (NS); +R4.L = R0.L + R4.L (NS); +R5.L = R0.L + R5.H (NS); +R6.L = R0.H + R6.L (NS); +R7.L = R0.H + R7.H (NS); +CHECKREG r4, 0x56789B3D; +CHECKREG r5, 0x678979AB; +CHECKREG r6, 0x74446E7C; +CHECKREG r7, 0x86669FCD; +CHECKREG r4, 0x56789B3D; +CHECKREG r5, 0x678979AB; +CHECKREG r6, 0x74446E7C; +CHECKREG r7, 0x86669FCD; + +imm32 r0, 0x15678911; +imm32 r1, 0xaa89ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x567a891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445a15; +imm32 r7, 0x866677a7; +R0.L = R1.L + R0.L (NS); +R1.L = R1.L + R1.H (NS); +R2.L = R1.H + R2.L (NS); +R3.L = R1.H + R3.H (NS); +R4.L = R1.L + R4.L (NS); +R5.L = R1.L + R5.H (NS); +R6.L = R1.H + R6.L (NS); +R7.L = R1.H + R7.H (NS); +CHECKREG r4, 0x567ADEC1; +CHECKREG r5, 0x6789BD2F; +CHECKREG r6, 0x7444049E; +CHECKREG r7, 0x866630EF; +CHECKREG r4, 0x567ADEC1; +CHECKREG r5, 0x6789BD2F; +CHECKREG r6, 0x7444049E; +CHECKREG r7, 0x866630EF; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R2.L + R0.L (NS); +R1.L = R2.L + R1.H (NS); +R2.L = R2.H + R2.L (NS); +R3.L = R2.H + R3.H (NS); +R4.L = R2.L + R4.L (NS); +R5.L = R2.L + R5.H (NS); +R6.L = R2.H + R6.L (NS); +R7.L = R2.H + R7.H (NS); +CHECKREG r4, 0x56781274; +CHECKREG r5, 0x6789F0E2; +CHECKREG r6, 0x74448959; +CHECKREG r7, 0x8666BAAA; +CHECKREG r4, 0x56781274; +CHECKREG r5, 0x6789F0E2; +CHECKREG r6, 0x74448959; +CHECKREG r7, 0x8666BAAA; + +imm32 r0, 0xb5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3bb45515; +imm32 r3, 0x46667717; +imm32 r4, 0x567b891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444b515; +imm32 r7, 0x86667b77; +R0.L = R3.L + R0.L (NS); +R1.L = R3.L + R1.H (NS); +R2.L = R3.H + R2.L (NS); +R3.L = R3.H + R3.H (NS); +R4.L = R3.L + R4.L (NS); +R5.L = R3.L + R5.H (NS); +R6.L = R3.H + R6.L (NS); +R7.L = R3.H + R7.H (NS); +CHECKREG r4, 0x567B15E7; +CHECKREG r5, 0x6789F455; +CHECKREG r6, 0x7444FB7B; +CHECKREG r7, 0x8666CCCC; +CHECKREG r4, 0x567B15E7; +CHECKREG r5, 0x6789F455; +CHECKREG r6, 0x7444FB7B; +CHECKREG r7, 0x8666CCCC; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R4.L + R0.L (NS); +R1.L = R4.L + R1.H (NS); +R2.L = R4.H + R2.L (NS); +R3.L = R4.H + R3.H (NS); +R4.L = R4.L + R4.L (NS); +R5.L = R4.L + R5.H (NS); +R6.L = R4.H + R6.L (NS); +R7.L = R4.H + R7.H (NS); +CHECKREG r4, 0x56781236; +CHECKREG r5, 0x678979BF; +CHECKREG r6, 0x7444AB8D; +CHECKREG r7, 0x8666DCDE; +CHECKREG r4, 0x56781236; +CHECKREG r5, 0x678979BF; +CHECKREG r6, 0x7444AB8D; +CHECKREG r7, 0x8666DCDE; + +imm32 r0, 0xcc678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3c445515; +imm32 r3, 0x46c67717; +imm32 r4, 0x567c891b; +imm32 r5, 0x6789cb1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667c77; +R0.L = R5.L + R0.L (NS); +R1.L = R5.L + R1.H (NS); +R2.L = R5.H + R2.L (NS); +R3.L = R5.H + R3.H (NS); +R4.L = R5.L + R4.L (NS); +R5.L = R5.L + R5.H (NS); +R6.L = R5.H + R6.L (NS); +R7.L = R5.H + R7.H (NS); +CHECKREG r4, 0x567C5438; +CHECKREG r5, 0x678932A6; +CHECKREG r6, 0x7444BC9E; +CHECKREG r7, 0x8666EDEF; +CHECKREG r4, 0x567C5438; +CHECKREG r5, 0x678932A6; +CHECKREG r6, 0x7444BC9E; +CHECKREG r7, 0x8666EDEF; + +imm32 r0, 0xd5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R0.L = R6.L + R0.L (NS); +R1.L = R6.L + R1.H (NS); +R2.L = R6.H + R2.L (NS); +R3.L = R6.H + R3.H (NS); +R4.L = R6.L + R4.L (NS); +R5.L = R6.L + R5.H (NS); +R6.L = R6.H + R6.L (NS); +R7.L = R6.H + R7.H (NS); +CHECKREG r4, 0x56785E30; +CHECKREG r5, 0x678D3CA2; +CHECKREG r6, 0x74444959; +CHECKREG r7, 0x8666FAAA; +CHECKREG r4, 0x56785E30; +CHECKREG r5, 0x678D3CA2; +CHECKREG r6, 0x74444959; +CHECKREG r7, 0x8666FAAA; + +imm32 r0, 0xf5678911; +imm32 r1, 0x2f89ab1d; +imm32 r2, 0x34f45515; +imm32 r3, 0x466f7717; +imm32 r4, 0x5678f91b; +imm32 r5, 0x6789af1d; +imm32 r6, 0x744455f5; +imm32 r7, 0x8666777f; +R0.L = R7.L + R0.L (NS); +R1.L = R7.L + R1.H (NS); +R2.L = R7.H + R2.L (NS); +R3.L = R7.H + R3.H (NS); +R4.L = R7.L + R4.L (NS); +R5.L = R7.L + R5.H (NS); +R6.L = R7.H + R6.L (NS); +R7.L = R7.H + R7.H (NS); +CHECKREG r4, 0x5678709A; +CHECKREG r5, 0x6789DF08; +CHECKREG r6, 0x7444DC5B; +CHECKREG r7, 0x86660CCC; +CHECKREG r4, 0x5678709A; +CHECKREG r5, 0x6789DF08; +CHECKREG r6, 0x7444DC5B; +CHECKREG r7, 0x86660CCC; + +imm32 r0, 0x55678911; +imm32 r1, 0x2589ab1d; +imm32 r2, 0x35545515; +imm32 r3, 0x46d67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R6.L = R2.L + R3.L (S); +R1.L = R4.L + R5.H (S); +R5.L = R7.H + R2.L (S); +R3.L = R0.H + R0.H (S); +R0.L = R3.L + R4.L (S); +R2.L = R5.L + R7.H (S); +R7.L = R6.H + R7.L (S); +R4.L = R1.H + R6.H (S); +CHECKREG r4, 0x56787FFF; +CHECKREG r5, 0x678DDB7B; +CHECKREG r6, 0x74447FFF; +CHECKREG r7, 0x86667FFF; +CHECKREG r4, 0x56787FFF; +CHECKREG r5, 0x678DDB7B; +CHECKREG r6, 0x74447FFF; +CHECKREG r7, 0x86667FFF; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3.L = R4.L + R0.L (S); +R1.L = R6.L + R3.H (S); +R4.L = R3.H + R2.L (S); +R6.L = R7.H + R1.H (S); +R2.L = R5.L + R4.L (S); +R7.L = R2.L + R7.H (S); +R0.L = R1.H + R6.L (S); +R5.L = R0.H + R5.H (S); +CHECKREG r4, 0x56787FFF; +CHECKREG r5, 0x67897CF0; +CHECKREG r6, 0x7444ADEF; +CHECKREG r7, 0x8666B182; +CHECKREG r4, 0x56787FFF; +CHECKREG r5, 0x67897CF0; +CHECKREG r6, 0x7444ADEF; +CHECKREG r7, 0x8666B182; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rl_rnd12_m.s b/sim/testsuite/bfin/c_dsp32alu_rl_rnd12_m.s new file mode 100644 index 0000000..3beee88 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rl_rnd12_m.s @@ -0,0 +1,261 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_m/c_dsp32alu_rl_rnd12_m.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x85678911; + imm32 r1, 0x9189ab1d; + imm32 r2, 0xa4245515; + imm32 r3, 0xb6637717; + imm32 r4, 0xc678491b; + imm32 r5, 0x6789a51d; + imm32 r6, 0xe4445565; + imm32 r7, 0x86667777; + R0.L = R0 - R0 (RND12); + R1.L = R0 - R1 (RND12); + R2.L = R0 - R2 (RND12); + R3.L = R0 - R3 (RND12); + R4.L = R0 - R4 (RND12); + R5.L = R0 - R5 (RND12); + R6.L = R0 - R6 (RND12); + R7.L = R0 - R7 (RND12); + CHECKREG r0, 0x85670000; + CHECKREG r1, 0x91898000; + CHECKREG r2, 0xA4248000; + CHECKREG r3, 0xB6638000; + CHECKREG r4, 0xC6788000; + CHECKREG r5, 0x67898000; + CHECKREG r6, 0xE4448000; + CHECKREG r7, 0x8666F009; + + imm32 r0, 0x75678921; + imm32 r1, 0x2789ab14; + imm32 r2, 0xd4745515; + imm32 r3, 0x4d677767; + imm32 r4, 0x56d8791b; + imm32 r5, 0x678dab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86a6d777; + R0.L = R1 - R0 (RND12); + R1.L = R1 - R1 (RND12); + R2.L = R1 - R2 (RND12); + R3.L = R1 - R3 (RND12); + R4.L = R1 - R4 (RND12); + R5.L = R1 - R5 (RND12); + R6.L = R1 - R6 (RND12); + R7.L = R1 - R7 (RND12); + CHECKREG r0, 0x75678000; + CHECKREG r1, 0x27890000; + CHECKREG r2, 0xD4747FFF; + CHECKREG r3, 0x4D678000; + CHECKREG r4, 0x56D88000; + CHECKREG r5, 0x678D8000; + CHECKREG r6, 0x74448000; + CHECKREG r7, 0x86A67fff; + + imm32 r0, 0x55678911; + imm32 r1, 0x2689ab1d; + imm32 r2, 0x3d445515; + imm32 r3, 0x46967717; + imm32 r4, 0xa67a891b; + imm32 r5, 0x6789bb1d; + imm32 r6, 0x7444d515; + imm32 r7, 0x8666c777; + R0.L = R2 - R0 (RND12); + R1.L = R2 - R1 (RND12); + R2.L = R2 - R2 (RND12); + R3.L = R2 - R3 (RND12); + R4.L = R2 - R4 (RND12); + R5.L = R2 - R5 (RND12); + R6.L = R2 - R6 (RND12); + R7.L = R2 - R7 (RND12); + CHECKREG r0, 0x55678000; + CHECKREG r1, 0x26897fff; + CHECKREG r2, 0x3D440000; + CHECKREG r3, 0x46968000; + CHECKREG r4, 0xA67A7fff; + CHECKREG r5, 0x67898000; + CHECKREG r6, 0x74448000; + CHECKREG r7, 0x86667fff; + + imm32 r0, 0xf5678911; + imm32 r1, 0xd789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0xe6667717; + imm32 r4, 0x5678891b; + imm32 r5, 0x6d89ab1d; + imm32 r6, 0x7444d515; + imm32 r7, 0xe6667b77; + R0.L = R3 - R0 (RND12); + R1.L = R3 - R1 (RND12); + R2.L = R3 - R2 (RND12); + R3.L = R3 - R3 (RND12); + R4.L = R3 - R4 (RND12); + R5.L = R3 - R5 (RND12); + R6.L = R3 - R6 (RND12); + R7.L = R3 - R7 (RND12); + CHECKREG r0, 0xF5678000; + CHECKREG r1, 0xD7897fff; + CHECKREG r2, 0x34448000; + CHECKREG r3, 0xE6660000; + CHECKREG r4, 0x56788000; + CHECKREG r5, 0x6D898000; + CHECKREG r6, 0x74448000; + CHECKREG r7, 0xE666FFF8; + + imm32 r0, 0xa5678911; + imm32 r1, 0x2b89ab1d; + imm32 r2, 0x34c45515; + imm32 r3, 0x46d67717; + imm32 r4, 0x56e8891b; + imm32 r5, 0x67f9ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86687777; + R0.L = R4 - R0 (RND12); + R1.L = R4 - R1 (RND12); + R2.L = R4 - R2 (RND12); + R3.L = R4 - R3 (RND12); + R4.L = R4 - R4 (RND12); + R5.L = R4 - R5 (RND12); + R6.L = R4 - R6 (RND12); + R7.L = R4 - R7 (RND12); + CHECKREG r0, 0xa5677fff; + CHECKREG r1, 0x2b897fff; + CHECKREG r2, 0x34c47fff; + CHECKREG r3, 0x46d67fff; + CHECKREG r4, 0x56E80000; + CHECKREG r5, 0x67F98000; + CHECKREG r6, 0x74448000; + CHECKREG r7, 0x86687fff; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0xd6667717; + imm32 r4, 0x5ff8891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x744e5515; + imm32 r7, 0x8666a7b7; + R0.L = R5 - R0 (RND12); + R1.L = R5 - R1 (RND12); + R2.L = R5 - R2 (RND12); + R3.L = R5 - R3 (RND12); + R4.L = R5 - R4 (RND12); + R5.L = R5 - R5 (RND12); + R6.L = R5 - R6 (RND12); + R7.L = R5 - R7 (RND12); + CHECKREG r0, 0xE5677fff; + CHECKREG r1, 0x27897fff; + CHECKREG r2, 0x34447fff; + CHECKREG r3, 0xD6667fff; + CHECKREG r4, 0x5FF87912; + CHECKREG r5, 0x67890000; + CHECKREG r6, 0x744E8000; + CHECKREG r7, 0x86667fff; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ae1d; + imm32 r2, 0x344455e5; + imm32 r3, 0x4666771d; + imm32 r4, 0x5678891b; + imm32 r5, 0x6789abdd; + imm32 r6, 0x74a45515; + imm32 r7, 0x866c77b7; + R0.L = R6 - R0 (RND12); + R1.L = R6 - R1 (RND12); + R2.L = R6 - R2 (RND12); + R3.L = R6 - R3 (RND12); + R4.L = R6 - R4 (RND12); + R5.L = R6 - R5 (RND12); + R6.L = R6 - R6 (RND12); + R7.L = R6 - R7 (RND12); + CHECKREG r0, 0x15677fff; + CHECKREG r1, 0x27897fff; + CHECKREG r2, 0x34447fff; + CHECKREG r3, 0x46667fff; + CHECKREG r4, 0x56787fff; + CHECKREG r5, 0x67897fff; + CHECKREG r6, 0x74A40000; + CHECKREG r7, 0x866C7fff; + + imm32 r0, 0x25678911; + imm32 r1, 0x2389ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46567717; + imm32 r4, 0x5678891b; + imm32 r5, 0x678dab1d; + imm32 r6, 0x7444b515; + imm32 r7, 0xb666a777; + R0.L = R7 - R0 (RND12); + R1.L = R7 - R1 (RND12); + R2.L = R7 - R2 (RND12); + R3.L = R7 - R3 (RND12); + R4.L = R7 - R4 (RND12); + R5.L = R7 - R5 (RND12); + R6.L = R7 - R6 (RND12); + R7.L = R7 - R7 (RND12); + CHECKREG r0, 0x25678000; + CHECKREG r1, 0x23898000; + CHECKREG r2, 0x34448000; + CHECKREG r3, 0x46568000; + CHECKREG r4, 0x56788000; + CHECKREG r5, 0x678D8000; + CHECKREG r6, 0x74448000; + CHECKREG r7, 0xB6660000; + + imm32 r0, 0xaa678911; + imm32 r1, 0x27ddab1d; + imm32 r2, 0x344bb515; + imm32 r3, 0x46667717; + imm32 r4, 0x56dd891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x7444bb15; + imm32 r7, 0x86ff7777; + R6.L = R2 - R3 (RND12); + R1.L = R4 - R5 (RND12); + R5.L = R7 - R2 (RND12); + R3.L = R0 - R0 (RND12); + R0.L = R3 - R4 (RND12); + R2.L = R5 - R7 (RND12); + R7.L = R6 - R7 (RND12); + R4.L = R1 - R6 (RND12); + CHECKREG r0, 0xAA678000; + CHECKREG r1, 0x27DD8000; + CHECKREG r2, 0x344B7fff; + CHECKREG r3, 0x46660000; + CHECKREG r4, 0x56DD8000; + CHECKREG r5, 0x67898000; + CHECKREG r6, 0x74448000; + CHECKREG r7, 0x86FF7fff; + + imm32 r0, 0x95678911; + imm32 r1, 0x2d89ab1d; + imm32 r2, 0x34b45515; + imm32 r3, 0x46c67717; + imm32 r4, 0x567e891b; + imm32 r5, 0x678fab1d; + imm32 r6, 0x744e5515; + imm32 r7, 0x8b66a777; + R3.L = R4 - R0 (RND12); + R1.L = R6 - R3 (RND12); + R4.L = R3 - R2 (RND12); + R6.L = R7 - R1 (RND12); + R2.L = R5 - R4 (RND12); + R7.L = R2 - R7 (RND12); + R0.L = R1 - R6 (RND12); + R5.L = R0 - R5 (RND12); + CHECKREG r0, 0x95678000; + CHECKREG r1, 0x2D897fff; + CHECKREG r2, 0x34B47fff; + CHECKREG r3, 0x46C67fff; + CHECKREG r4, 0x567E7fff; + CHECKREG r5, 0x678F8000; + CHECKREG r6, 0x744E8000; + CHECKREG r7, 0x8B667FFF; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rl_rnd12_p.s b/sim/testsuite/bfin/c_dsp32alu_rl_rnd12_p.s new file mode 100644 index 0000000..bc159a2 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rl_rnd12_p.s @@ -0,0 +1,262 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_p/c_dsp32alu_rl_rnd12_p.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + + imm32 r0, 0x85678011; + imm32 r1, 0x9189a11d; + imm32 r2, 0xa4245235; + imm32 r3, 0xb6637747; + imm32 r4, 0xc67849db; + imm32 r5, 0x6789a5fd; + imm32 r6, 0xe4445565; + imm32 r7, 0x86667707; + R0.L = R0 + R0 (RND12); + R1.L = R0 + R1 (RND12); + R2.L = R0 + R2 (RND12); + R3.L = R0 + R3 (RND12); + R4.L = R0 + R4 (RND12); + R5.L = R0 + R5 (RND12); + R6.L = R0 + R6 (RND12); + R7.L = R0 + R7 (RND12); + CHECKREG r0, 0x85678000; + CHECKREG r1, 0x91898000; + CHECKREG r2, 0xA4248000; + CHECKREG r3, 0xB6638000; + CHECKREG r4, 0xC6788000; + CHECKREG r5, 0x67898000; + CHECKREG r6, 0xE4448000; + CHECKREG r7, 0x86668000; + + imm32 r0, 0x75678921; + imm32 r1, 0x2789ab14; + imm32 r2, 0xd4745515; + imm32 r3, 0x4d677767; + imm32 r4, 0x56d8791b; + imm32 r5, 0x678dab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86a6d777; + R0.L = R1 + R0 (RND12); + R1.L = R1 + R1 (RND12); + R2.L = R1 + R2 (RND12); + R3.L = R1 + R3 (RND12); + R4.L = R1 + R4 (RND12); + R5.L = R1 + R5 (RND12); + R6.L = R1 + R6 (RND12); + R7.L = R1 + R7 (RND12); + CHECKREG r0, 0x75677FFF; + CHECKREG r1, 0x27897FFF; + CHECKREG r2, 0xD474bfdd; + CHECKREG r3, 0x4D677fff; + CHECKREG r4, 0x56D87FFF; + CHECKREG r5, 0x678D7FFF; + CHECKREG r6, 0x74447FFF; + CHECKREG r7, 0x86A68000; + + imm32 r0, 0x55678911; + imm32 r1, 0x2689ab2d; + imm32 r2, 0x3d44551a; + imm32 r3, 0x469677cd; + imm32 r4, 0xa67a89bb; + imm32 r5, 0x6789bb1d; + imm32 r6, 0x7444d525; + imm32 r7, 0x8666c747; + R0.L = R2 + R0 (RND12); + R1.L = R2 + R1 (RND12); + R2.L = R2 + R2 (RND12); + R3.L = R2 + R3 (RND12); + R4.L = R2 + R4 (RND12); + R5.L = R2 + R5 (RND12); + R6.L = R2 + R6 (RND12); + R7.L = R2 + R7 (RND12); + CHECKREG r0, 0x55677fff; + CHECKREG r1, 0x26897fff; + CHECKREG r2, 0x3D447fff; + CHECKREG r3, 0x46967fff; + CHECKREG r4, 0xA67A8000; + CHECKREG r5, 0x67897fff; + CHECKREG r6, 0x74447fff; + CHECKREG r7, 0x86668000; + + imm32 r0, 0xf5678901; + imm32 r1, 0xd789ab7d; + imm32 r2, 0x34445565; + imm32 r3, 0xe6667757; + imm32 r4, 0x5678894b; + imm32 r5, 0x6d89ab3d; + imm32 r6, 0x7444d525; + imm32 r7, 0xe6667b77; + R0.L = R3 + R0 (RND12); + R1.L = R3 + R1 (RND12); + R2.L = R3 + R2 (RND12); + R3.L = R3 + R3 (RND12); + R4.L = R3 + R4 (RND12); + R5.L = R3 + R5 (RND12); + R6.L = R3 + R6 (RND12); + R7.L = R3 + R7 (RND12); + CHECKREG r0, 0xF5678000; + CHECKREG r1, 0xD7898000; + CHECKREG r2, 0x34447FFF; + CHECKREG r3, 0xE6668000; + CHECKREG r4, 0x56787FFF; + CHECKREG r5, 0x6D897FFF; + CHECKREG r6, 0x74447FFF; + CHECKREG r7, 0xE6668000; + + imm32 r0, 0xa5678911; + imm32 r1, 0x2b89ab1d; + imm32 r2, 0x34c45515; + imm32 r3, 0x46d67717; + imm32 r4, 0x56e8891b; + imm32 r5, 0x67f9ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86687777; + R0.L = R4 + R0 (RND12); + R1.L = R4 + R1 (RND12); + R2.L = R4 + R2 (RND12); + R3.L = R4 + R3 (RND12); + R4.L = R4 + R4 (RND12); + R5.L = R4 + R5 (RND12); + R6.L = R4 + R6 (RND12); + R7.L = R4 + R7 (RND12); + CHECKREG r0, 0xA567c501; + CHECKREG r1, 0x2B897fff; + CHECKREG r2, 0x34C47FFF; + CHECKREG r3, 0x46D67FFF; + CHECKREG r4, 0x56E87FFF; + CHECKREG r5, 0x67F97FFF; + CHECKREG r6, 0x74447FFF; + CHECKREG r7, 0x86688000; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445535; + imm32 r3, 0xd6667747; + imm32 r4, 0x5ff8895b; + imm32 r5, 0x6789ab8d; + imm32 r6, 0x744e5515; + imm32 r7, 0x8666a7b7; + R0.L = R5 + R0 (RND12); + R1.L = R5 + R1 (RND12); + R2.L = R5 + R2 (RND12); + R3.L = R5 + R3 (RND12); + R4.L = R5 + R4 (RND12); + R5.L = R5 + R5 (RND12); + R6.L = R5 + R6 (RND12); + R7.L = R5 + R7 (RND12); + CHECKREG r0, 0xE5677FFF; + CHECKREG r1, 0x27897FFF; + CHECKREG r2, 0x34447FFF; + CHECKREG r3, 0xD6667FFF; + CHECKREG r4, 0x5FF87fff; + CHECKREG r5, 0x67897FFF; + CHECKREG r6, 0x744E7FFF; + CHECKREG r7, 0x86668000; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ae1d; + imm32 r2, 0x344455e5; + imm32 r3, 0x4666771d; + imm32 r4, 0x5678891b; + imm32 r5, 0x6789abdd; + imm32 r6, 0x74a45515; + imm32 r7, 0x866c77b7; + R0.L = R6 + R0 (RND12); + R1.L = R6 + R1 (RND12); + R2.L = R6 + R2 (RND12); + R3.L = R6 + R3 (RND12); + R4.L = R6 + R4 (RND12); + R5.L = R6 + R5 (RND12); + R6.L = R6 + R6 (RND12); + R7.L = R6 + R7 (RND12); + CHECKREG r0, 0x15677FFF; + CHECKREG r1, 0x27897FFF; + CHECKREG r2, 0x34447FFF; + CHECKREG r3, 0x46667FFF; + CHECKREG r4, 0x56787FFF; + CHECKREG r5, 0x67897FFF; + CHECKREG r6, 0x74A47FFF; + CHECKREG r7, 0x866Cb10f; + + imm32 r0, 0x25678931; + imm32 r1, 0x2389ab14; + imm32 r2, 0x34445576; + imm32 r3, 0x46567787; + imm32 r4, 0x5678899b; + imm32 r5, 0x678dab1d; + imm32 r6, 0x7444b515; + imm32 r7, 0xb666a777; + R0.L = R7 + R0 (RND12); + R1.L = R7 + R1 (RND12); + R2.L = R7 + R2 (RND12); + R3.L = R7 + R3 (RND12); + R4.L = R7 + R4 (RND12); + R5.L = R7 + R5 (RND12); + R6.L = R7 + R6 (RND12); + R7.L = R7 + R7 (RND12); + CHECKREG r0, 0x25678000; + CHECKREG r1, 0x23898000; + CHECKREG r2, 0x34448000; + CHECKREG r3, 0x4656cbd2; + CHECKREG r4, 0x56787FFF; + CHECKREG r5, 0x678D7FFF; + CHECKREG r6, 0x74447FFF; + CHECKREG r7, 0xB6668000; + + imm32 r0, 0xaa678911; + imm32 r1, 0x27ddab1d; + imm32 r2, 0x344bb515; + imm32 r3, 0x46667717; + imm32 r4, 0x56dd891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x7444bb15; + imm32 r7, 0x86ff7777; + R6.L = R2 + R3 (RND12); + R1.L = R4 + R5 (RND12); + R5.L = R7 + R2 (RND12); + R3.L = R0 + R0 (RND12); + R0.L = R3 + R4 (RND12); + R2.L = R5 + R7 (RND12); + R7.L = R6 + R7 (RND12); + R4.L = R1 + R6 (RND12); + CHECKREG r0, 0xAA677FFF; + CHECKREG r1, 0x27DD7FFF; + CHECKREG r2, 0x344B8000; + CHECKREG r3, 0x46668000; + CHECKREG r4, 0x56DD7FFF; + CHECKREG r5, 0x67898000; + CHECKREG r6, 0x74447FFF; + CHECKREG r7, 0x86FFb43f; + + imm32 r0, 0x95678911; + imm32 r1, 0x2d89ab1d; + imm32 r2, 0x34b45515; + imm32 r3, 0x46c67717; + imm32 r4, 0x567e891b; + imm32 r5, 0x678fab1d; + imm32 r6, 0x744e5515; + imm32 r7, 0x8b66a777; + R3.L = R4 + R0 (RND12); + R1.L = R6 + R3 (RND12); + R4.L = R3 + R2 (RND12); + R6.L = R7 + R1 (RND12); + R2.L = R5 + R4 (RND12); + R7.L = R2 + R7 (RND12); + R0.L = R1 + R6 (RND12); + R5.L = R0 + R5 (RND12); + CHECKREG r0, 0x95677fff; + CHECKREG r1, 0x2D897FFF; + CHECKREG r2, 0x34B47FFF; + CHECKREG r3, 0x46C68000; + CHECKREG r4, 0x567E7FFF; + CHECKREG r5, 0x678Fcf73; + CHECKREG r6, 0x744E8000; + CHECKREG r7, 0x8B668000; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rl_rnd20_m.s b/sim/testsuite/bfin/c_dsp32alu_rl_rnd20_m.s new file mode 100644 index 0000000..4916fd0 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rl_rnd20_m.s @@ -0,0 +1,262 @@ +//Original:/testcases/core/c_dsp32alu_rl_rnd20_m/c_dsp32alu_rl_rnd20_m.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x75678911; +imm32 r1, 0xa789ab1d; +imm32 r2, 0x34745515; +imm32 r3, 0x4b677717; +imm32 r4, 0x5678791b; +imm32 r5, 0xc789a71d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R0 - R0 (RND20); +R1.L = R0 - R1 (RND20); +R2.L = R0 - R2 (RND20); +R3.L = R0 - R3 (RND20); +R4.L = R0 - R4 (RND20); +R5.L = R0 - R5 (RND20); +R6.L = R0 - R6 (RND20); +R7.L = R0 - R7 (RND20); +CHECKREG r0, 0x75670000; +CHECKREG r1, 0xA7890CDE; +CHECKREG r2, 0x3474040F; +CHECKREG r3, 0x4B6702A0; +CHECKREG r4, 0x567801EF; +CHECKREG r5, 0xC7890ADE; +CHECKREG r6, 0x74440012; +CHECKREG r7, 0x86660EF0; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3e445515; +imm32 r3, 0x46667717; +imm32 r4, 0x56e8891b; +imm32 r5, 0x678eab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86e67e77; +R0.L = R1 - R0 (RND20); +CHECKREG r0, 0xE5670422; +R1.L = R1 - R1 (RND20); +CHECKREG r1, 0x27890000; +R2.L = R1 - R2 (RND20); +CHECKREG r2, 0x3E44FE94; +R3.L = R1 - R3 (RND20); +CHECKREG r3, 0x4666FE12; +R4.L = R1 - R4 (RND20); +R5.L = R1 - R5 (RND20); +R6.L = R1 - R6 (RND20); +R7.L = R1 - R7 (RND20); +CHECKREG r0, 0xE5670422; +CHECKREG r1, 0x27890000; +CHECKREG r2, 0x3E44FE94; +CHECKREG r3, 0x4666FE12; +CHECKREG r4, 0x56E8FD0A; +CHECKREG r5, 0x678EFC00; +CHECKREG r6, 0x7444FB34; +CHECKREG r7, 0x86E60A0A; + +imm32 r0, 0xdd678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46667717; +imm32 r4, 0x56d8891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R0.L = R2 - R0 (RND20); +R1.L = R2 - R1 (RND20); +R2.L = R2 - R2 (RND20); +R3.L = R2 - R3 (RND20); +R4.L = R2 - R4 (RND20); +R5.L = R2 - R5 (RND20); +R6.L = R2 - R6 (RND20); +R7.L = R2 - R7 (RND20); +CHECKREG r0, 0xDD6705FE; +CHECKREG r1, 0x2789015C; +CHECKREG r2, 0x3D440000; +CHECKREG r3, 0x4666FF6E; +CHECKREG r4, 0x56D8FE67; +CHECKREG r5, 0x678DFD5B; +CHECKREG r6, 0x7444FC90; +CHECKREG r7, 0x86660B6E; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x567a891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444c515; +imm32 r7, 0x86667c77; +R0.L = R3 - R0 (RND20); +R1.L = R3 - R1 (RND20); +R2.L = R3 - R2 (RND20); +R3.L = R3 - R3 (RND20); +R4.L = R3 - R4 (RND20); +R5.L = R3 - R5 (RND20); +R6.L = R3 - R6 (RND20); +R7.L = R3 - R7 (RND20); +CHECKREG r0, 0xA5670A14; +CHECKREG r1, 0x2A8901C2; +CHECKREG r2, 0x34440126; +CHECKREG r3, 0x46A60000; +CHECKREG r4, 0x567AFF03; +CHECKREG r5, 0x6789FDF2; +CHECKREG r6, 0x7444FD26; +CHECKREG r7, 0x86660C04; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R4 - R0 (RND20); +R1.L = R4 - R1 (RND20); +R2.L = R4 - R2 (RND20); +R3.L = R4 - R3 (RND20); +R4.L = R4 - R4 (RND20); +R5.L = R4 - R5 (RND20); +R6.L = R4 - R6 (RND20); +R7.L = R4 - R7 (RND20); +CHECKREG r0, 0x15670411; +CHECKREG r1, 0x278902EF; +CHECKREG r2, 0x34440223; +CHECKREG r3, 0x46660101; +CHECKREG r4, 0x56780000; +CHECKREG r5, 0x6789FEEF; +CHECKREG r6, 0x7444FE23; +CHECKREG r7, 0x86660D01; + +imm32 r0, 0x95678911; +imm32 r1, 0x8789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0x4a667717; +imm32 r4, 0x56b8891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444e515; +imm32 r7, 0x86667d77; +R0.L = R5 - R0 (RND20); +R1.L = R5 - R1 (RND20); +R2.L = R5 - R2 (RND20); +R3.L = R5 - R3 (RND20); +R4.L = R5 - R4 (RND20); +R5.L = R5 - R5 (RND20); +R6.L = R5 - R6 (RND20); +R7.L = R5 - R7 (RND20); +CHECKREG r0, 0x95670D22; +CHECKREG r1, 0x87890E00; +CHECKREG r2, 0x7444FF35; +CHECKREG r3, 0x4A6601D2; +CHECKREG r4, 0x56B8010D; +CHECKREG r5, 0x678D0000; +CHECKREG r6, 0x7444FF35; +CHECKREG r7, 0x86660E12; + +imm32 r0, 0x35678911; +imm32 r1, 0x2459ab1d; +imm32 r2, 0x34465515; +imm32 r3, 0xe6667717; +imm32 r4, 0x5d78891b; +imm32 r5, 0x67b9ab1d; +imm32 r6, 0x744a5515; +imm32 r7, 0x8666c777; +R0.L = R6 - R0 (RND20); +R1.L = R6 - R1 (RND20); +R2.L = R6 - R2 (RND20); +R3.L = R6 - R3 (RND20); +R4.L = R6 - R4 (RND20); +R5.L = R6 - R5 (RND20); +R6.L = R6 - R6 (RND20); +R7.L = R6 - R7 (RND20); +CHECKREG r0, 0x356703EE; +CHECKREG r1, 0x245904FF; +CHECKREG r2, 0x34460400; +CHECKREG r3, 0xE66608DE; +CHECKREG r4, 0x5D78016D; +CHECKREG r5, 0x67B900C9; +CHECKREG r6, 0x744A0000; +CHECKREG r7, 0x86660EDE; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3a445515; +imm32 r3, 0x4c667717; +imm32 r4, 0x56b8891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x8666d777; +R0.L = R7 - R0 (RND20); +R1.L = R7 - R1 (RND20); +R2.L = R7 - R2 (RND20); +R3.L = R7 - R3 (RND20); +R4.L = R7 - R4 (RND20); +R5.L = R7 - R5 (RND20); +R6.L = R7 - R6 (RND20); +R7.L = R7 - R7 (RND20); +CHECKREG r0, 0xA567FE10; +CHECKREG r1, 0x2789F5EE; +CHECKREG r2, 0x3A44F4C2; +CHECKREG r3, 0x4C66F3A0; +CHECKREG r4, 0x56B8F2FB; +CHECKREG r5, 0x678DF1EE; +CHECKREG r6, 0x7444F122; +CHECKREG r7, 0x86660000; + +imm32 r0, 0xabd78911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0xd4445515; +imm32 r3, 0x4e667717; +imm32 r4, 0x56f8891b; +imm32 r5, 0x678aab1d; +imm32 r6, 0x7444b515; +imm32 r7, 0x86667d77; +R6.L = R2 - R3 (RND20); +R1.L = R4 - R5 (RND20); +R5.L = R7 - R2 (RND20); +R3.L = R0 - R0 (RND20); +R0.L = R3 - R4 (RND20); +R2.L = R5 - R7 (RND20); +R7.L = R6 - R7 (RND20); +R4.L = R1 - R6 (RND20); +CHECKREG r0, 0xABD7FF77; +CHECKREG r1, 0x2789FEF7; +CHECKREG r2, 0xD4440E12; +CHECKREG r3, 0x4E660000; +CHECKREG r4, 0x56F8FB34; +CHECKREG r5, 0x678AFB22; +CHECKREG r6, 0x7444F85E; +CHECKREG r7, 0x86660EDE; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3.L = R4 - R0 (RND20); +R1.L = R6 - R3 (RND20); +R4.L = R3 - R2 (RND20); +R6.L = R7 - R1 (RND20); +R2.L = R5 - R4 (RND20); +R7.L = R2 - R7 (RND20); +R0.L = R1 - R6 (RND20); +R5.L = R0 - R5 (RND20); +CHECKREG r0, 0x1567FB34; +CHECKREG r1, 0x278902DE; +CHECKREG r2, 0x34440111; +CHECKREG r3, 0x46660411; +CHECKREG r4, 0x56780122; +CHECKREG r5, 0x6789FADE; +CHECKREG r6, 0x7444F5EE; +CHECKREG r7, 0x86660ADE; + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rl_rnd20_p.s b/sim/testsuite/bfin/c_dsp32alu_rl_rnd20_p.s new file mode 100644 index 0000000..ced4fcc --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rl_rnd20_p.s @@ -0,0 +1,258 @@ +//Original:/testcases/core/c_dsp32alu_rl_rnd20_p/c_dsp32alu_rl_rnd20_p.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x75678911; +imm32 r1, 0xa789ab1d; +imm32 r2, 0x34745515; +imm32 r3, 0x4b677717; +imm32 r4, 0x5678791b; +imm32 r5, 0xc789a71d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R0 + R0 (RND20); +R1.L = R0 + R1 (RND20); +R2.L = R0 + R2 (RND20); +R3.L = R0 + R3 (RND20); +R4.L = R0 + R4 (RND20); +R5.L = R0 + R5 (RND20); +R6.L = R0 + R6 (RND20); +R7.L = R0 + R7 (RND20); +CHECKREG r0, 0x75670EAD; +CHECKREG r1, 0xA78901CF; +CHECKREG r2, 0x34740A9E; +CHECKREG r3, 0x4B670C0D; +CHECKREG r4, 0x56780CBE; +CHECKREG r5, 0xC78903CF; +CHECKREG r6, 0x74440E9B; +CHECKREG r7, 0x8666FFBD; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3e445515; +imm32 r3, 0x46667717; +imm32 r4, 0x56e8891b; +imm32 r5, 0x678eab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86e67e77; +R0.L = R1 + R0 (RND20); +R1.L = R1 + R1 (RND20); +R2.L = R1 + R2 (RND20); +R3.L = R1 + R3 (RND20); +R4.L = R1 + R4 (RND20); +R5.L = R1 + R5 (RND20); +R6.L = R1 + R6 (RND20); +R7.L = R1 + R7 (RND20); +CHECKREG r0, 0xE56700CF; +CHECKREG r1, 0x278904F1; +CHECKREG r2, 0x3E44065D; +CHECKREG r3, 0x466606DF; +CHECKREG r4, 0x56E807E7; +CHECKREG r5, 0x678E08F1; +CHECKREG r6, 0x744409BD; +CHECKREG r7, 0x86E6FAE7; + +imm32 r0, 0xdd678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46667717; +imm32 r4, 0x56d8891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R0.L = R2 + R0 (RND20); +R1.L = R2 + R1 (RND20); +R2.L = R2 + R2 (RND20); +R3.L = R2 + R3 (RND20); +R4.L = R2 + R4 (RND20); +R5.L = R2 + R5 (RND20); +R6.L = R2 + R6 (RND20); +R7.L = R2 + R7 (RND20); +CHECKREG r0, 0xDD6701AB; +CHECKREG r1, 0x2789064D; +CHECKREG r2, 0x3D4407A9; +CHECKREG r3, 0x4666083B; +CHECKREG r4, 0x56D80942; +CHECKREG r5, 0x678D0A4D; +CHECKREG r6, 0x74440B19; +CHECKREG r7, 0x8666FC3B; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x567a891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444c515; +imm32 r7, 0x86667c77; +R0.L = R3 + R0 (RND20); +R1.L = R3 + R1 (RND20); +R2.L = R3 + R2 (RND20); +R3.L = R3 + R3 (RND20); +R4.L = R3 + R4 (RND20); +R5.L = R3 + R5 (RND20); +R6.L = R3 + R6 (RND20); +R7.L = R3 + R7 (RND20); +CHECKREG r0, 0xA567FEC1; +CHECKREG r1, 0x2A890713; +CHECKREG r2, 0x344407AF; +CHECKREG r3, 0x46A608D5; +CHECKREG r4, 0x567A09D2; +CHECKREG r5, 0x67890AE3; +CHECKREG r6, 0x74440BAF; +CHECKREG r7, 0x8666FCD1; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R4 + R0 (RND20); +R1.L = R4 + R1 (RND20); +R2.L = R4 + R2 (RND20); +R3.L = R4 + R3 (RND20); +R4.L = R4 + R4 (RND20); +R5.L = R4 + R5 (RND20); +R6.L = R4 + R6 (RND20); +R7.L = R4 + R7 (RND20); +CHECKREG r0, 0x156706BE; +CHECKREG r1, 0x278907E0; +CHECKREG r2, 0x344408AC; +CHECKREG r3, 0x466609CE; +CHECKREG r4, 0x56780ACF; +CHECKREG r5, 0x67890BE0; +CHECKREG r6, 0x74440CAC; +CHECKREG r7, 0x8666FDCE; + +imm32 r0, 0x95678911; +imm32 r1, 0x8789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0x4a667717; +imm32 r4, 0x56b8891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444e515; +imm32 r7, 0x86667d77; +R0.L = R5 + R0 (RND20); +R1.L = R5 + R1 (RND20); +R2.L = R5 + R2 (RND20); +R3.L = R5 + R3 (RND20); +R4.L = R5 + R4 (RND20); +R5.L = R5 + R5 (RND20); +R6.L = R5 + R6 (RND20); +R7.L = R5 + R7 (RND20); +CHECKREG r0, 0x9567FFCF; +CHECKREG r1, 0x8789FEF1; +CHECKREG r2, 0x74440DBD; +CHECKREG r3, 0x4A660B1F; +CHECKREG r4, 0x56B80BE4; +CHECKREG r5, 0x678D0CF2; +CHECKREG r6, 0x74440DBD; +CHECKREG r7, 0x8666FEDF; + +imm32 r0, 0x35678911; +imm32 r1, 0x2459ab1d; +imm32 r2, 0x34465515; +imm32 r3, 0xe6667717; +imm32 r4, 0x5d78891b; +imm32 r5, 0x67b9ab1d; +imm32 r6, 0x744a5515; +imm32 r7, 0x8666c777; +R0.L = R6 + R0 (RND20); +R1.L = R6 + R1 (RND20); +R2.L = R6 + R2 (RND20); +R3.L = R6 + R3 (RND20); +R4.L = R6 + R4 (RND20); +R5.L = R6 + R5 (RND20); +R6.L = R6 + R6 (RND20); +R7.L = R6 + R7 (RND20); +CHECKREG r0, 0x35670A9B; +CHECKREG r1, 0x2459098A; +CHECKREG r2, 0x34460A89; +CHECKREG r3, 0xE66605AB; +CHECKREG r4, 0x5D780D1C; +CHECKREG r5, 0x67B90DC0; +CHECKREG r6, 0x744A0E89; +CHECKREG r7, 0x8666FFAB; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3a445515; +imm32 r3, 0x4c667717; +imm32 r4, 0x56b8891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x8666d777; +R0.L = R7 + R0 (RND20); +R1.L = R7 + R1 (RND20); +R2.L = R7 + R2 (RND20); +R3.L = R7 + R3 (RND20); +R4.L = R7 + R4 (RND20); +R5.L = R7 + R5 (RND20); +R6.L = R7 + R6 (RND20); +R7.L = R7 + R7 (RND20); +CHECKREG r0, 0xA567F2BD; +CHECKREG r1, 0x2789FADF; +CHECKREG r2, 0x3A44FC0B; +CHECKREG r3, 0x4C66FD2D; +CHECKREG r4, 0x56B8FDD2; +CHECKREG r5, 0x678DFEDF; +CHECKREG r6, 0x7444FFAB; +CHECKREG r7, 0x8666F0CD; + +imm32 r0, 0xabd78911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0xd4445515; +imm32 r3, 0x4e667717; +imm32 r4, 0x56f8891b; +imm32 r5, 0x678aab1d; +imm32 r6, 0x7444b515; +imm32 r7, 0x86667d77; +R6.L = R2 + R3 (RND20); +R1.L = R4 + R5 (RND20); +R5.L = R7 + R2 (RND20); +R3.L = R0 + R0 (RND20); +R0.L = R3 + R4 (RND20); +R2.L = R5 + R7 (RND20); +R7.L = R6 + R7 (RND20); +R4.L = R1 + R6 (RND20); +CHECKREG r0, 0xABD70A56; +CHECKREG r1, 0x27890BE8; +CHECKREG r2, 0xD444FEDF; +CHECKREG r3, 0x4E66F57B; +CHECKREG r4, 0x56F809BD; +CHECKREG r5, 0x678AF5AB; +CHECKREG r6, 0x7444022B; +CHECKREG r7, 0x8666FFAB; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3.L = R4 + R0 (RND20); +R1.L = R6 + R3 (RND20); +R4.L = R3 + R2 (RND20); +R6.L = R7 + R1 (RND20); +R2.L = R5 + R4 (RND20); +R7.L = R2 + R7 (RND20); +R0.L = R1 + R6 (RND20); +R5.L = R0 + R5 (RND20); +CHECKREG r0, 0x156709BD; +CHECKREG r1, 0x27890BAB; +CHECKREG r2, 0x34440BE0; +CHECKREG r3, 0x466606BE; +CHECKREG r4, 0x567807AB; +CHECKREG r5, 0x678907CF; +CHECKREG r6, 0x7444FADF; +CHECKREG r7, 0x8666FBAB; + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rlh_rnd.s b/sim/testsuite/bfin/c_dsp32alu_rlh_rnd.s new file mode 100644 index 0000000..b7f0c2a --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rlh_rnd.s @@ -0,0 +1,66 @@ +//Original:/testcases/core/c_dsp32alu_rlh_rnd/c_dsp32alu_rlh_rnd.dsp +// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x4537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x44555535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0.L = R1 (RND); +R0.H = R2 (RND); +R1.L = R3 (RND); +R1.H = R4 (RND); +R2.L = R5 (RND); +R2.H = R6 (RND); +CHECKREG r0, 0x4455675A; +CHECKREG r1, 0x88796666; +CHECKREG r2, 0xCC9DAA8B; + + +imm32 r0, 0xe537891b; +imm32 r1, 0xf759ab2d; +imm32 r2, 0x4ef55535; +imm32 r3, 0x666b5747; +imm32 r4, 0xc8789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0x8c9cdd85; +imm32 r7, 0x9eaeff9f; +R3.L = R0 (RND); +R3.H = R1 (RND); +R4.L = R2 (RND); +R4.H = R5 (RND); +R5.L = R6 (RND); +R5.H = R7 (RND); +CHECKREG r3, 0xF75AE538; +CHECKREG r4, 0xAA8B4EF5; +CHECKREG r5, 0x9EAF8C9D; + +imm32 r0, 0x5537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x8ef55535; +imm32 r3, 0x666b5747; +imm32 r4, 0xc8789565; +imm32 r5, 0xea8abb5b; +imm32 r6, 0xfc9cdd85; +imm32 r7, 0x9eaeff9f; +R6.L = R0 (RND); +R6.H = R1 (RND); +R7.L = R2 (RND); +R7.H = R3 (RND); +R5.L = R4 (RND); +R5.H = R5 (RND); +CHECKREG r5, 0xEA8BC879; +CHECKREG r6, 0x675A5538; +CHECKREG r7, 0x666B8EF5; + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rm.s b/sim/testsuite/bfin/c_dsp32alu_rm.s new file mode 100644 index 0000000..f8c1407 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rm.s @@ -0,0 +1,262 @@ +//Original:/testcases/core/c_dsp32alu_rm/c_dsp32alu_rm.dsp +// Spec Reference: dsp32alu +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x35678911; +imm32 r1, 0x2389ab1d; +imm32 r2, 0x34345515; +imm32 r3, 0x46637717; +imm32 r4, 0x5567391b; +imm32 r5, 0x6789a31d; +imm32 r6, 0x744455a5; +imm32 r7, 0x866677a7; +R0 = R0 - R0 (NS); +R1 = R0 - R1 (NS); +R2 = R0 - R2 (NS); +R3 = R0 - R3 (NS); +R4 = R0 - R4 (NS); +R5 = R0 - R5 (NS); +R6 = R0 - R6 (NS); +R7 = R0 - R7 (NS); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xDC7654E3; +CHECKREG r2, 0xCBCBAAEB; +CHECKREG r3, 0xB99C88E9; +CHECKREG r4, 0xAA98C6E5; +CHECKREG r5, 0x98765CE3; +CHECKREG r6, 0x8BBBAA5B; +CHECKREG r7, 0x79998859; + +imm32 r0, 0xa5678911; +imm32 r1, 0x4a89ab1d; +imm32 r2, 0x54a45515; +imm32 r3, 0x466a7717; +imm32 r4, 0x5567a91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445a15; +imm32 r7, 0x866677a7; +R0 = R1 - R0 (NS); +R1 = R1 - R1 (NS); +R2 = R1 - R2 (NS); +R3 = R1 - R3 (NS); +R4 = R1 - R4 (NS); +R5 = R1 - R5 (NS); +R6 = R1 - R6 (NS); +R7 = R1 - R7 (NS); +CHECKREG r0, 0xA522220C; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xAB5BAAEB; +CHECKREG r3, 0xB99588E9; +CHECKREG r4, 0xAA9856E5; +CHECKREG r5, 0x987654E3; +CHECKREG r6, 0x8BBBA5EB; +CHECKREG r7, 0x79998859; + +imm32 r0, 0xda678911; +imm32 r1, 0x27c9ab1d; +imm32 r2, 0x344c5515; +imm32 r3, 0x4666c717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x744455b5; +imm32 r7, 0x8666777b; +R0 = R2 - R0 (NS); +R1 = R2 - R1 (NS); +R2 = R2 - R2 (NS); +R3 = R2 - R3 (NS); +R4 = R2 - R4 (NS); +R5 = R2 - R5 (NS); +R6 = R2 - R6 (NS); +R7 = R2 - R7 (NS); +CHECKREG r0, 0x59E4CC04; +CHECKREG r1, 0x0C82A9F8; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xB99938E9; +CHECKREG r4, 0xAA9876E5; +CHECKREG r5, 0x987654E3; +CHECKREG r6, 0x8BBBAA4B; +CHECKREG r7, 0x79998885; + +imm32 r0, 0x65678911; +imm32 r1, 0x7289ab1d; +imm32 r2, 0x84345515; +imm32 r3, 0x96647717; +imm32 r4, 0x5567591b; +imm32 r5, 0x6789a61d; +imm32 r6, 0x744d5515; +imm32 r7, 0x8666b777; +R0 = R3 - R0 (NS); +R1 = R3 - R1 (NS); +R2 = R3 - R2 (NS); +R3 = R3 - R3 (NS); +R4 = R3 - R4 (NS); +R5 = R3 - R5 (NS); +R6 = R3 - R6 (NS); +R7 = R3 - R7 (NS); +CHECKREG r0, 0x30FCEE06; +CHECKREG r1, 0x23DACBFA; +CHECKREG r2, 0x12302202; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xAA98A6E5; +CHECKREG r5, 0x987659E3; +CHECKREG r6, 0x8BB2AAEB; +CHECKREG r7, 0x79994889; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R4 - R0 (NS); +R1 = R4 - R1 (NS); +R2 = R4 - R2 (NS); +R3 = R4 - R3 (NS); +R4 = R4 - R4 (NS); +R5 = R4 - R5 (NS); +R6 = R4 - R6 (NS); +R7 = R4 - R7 (NS); +CHECKREG r0, 0x4000000A; +CHECKREG r1, 0x2DDDDDFE; +CHECKREG r2, 0x21233406; +CHECKREG r3, 0x0F011204; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x987654E3; +CHECKREG r6, 0x8BBBAAEB; +CHECKREG r7, 0x79998889; + +imm32 r0, 0x95678911; +imm32 r1, 0x8789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0x36667717; +imm32 r4, 0x3567891b; +imm32 r5, 0x6e89ab1d; +imm32 r6, 0x74e45515; +imm32 r7, 0x866e7777; +R0 = R5 - R0 (NS); +R1 = R5 - R1 (NS); +R2 = R5 - R2 (NS); +R3 = R5 - R3 (NS); +R4 = R5 - R4 (NS); +R5 = R5 - R5 (NS); +R6 = R5 - R6 (NS); +R7 = R5 - R7 (NS); +CHECKREG r0, 0xD922220C; +CHECKREG r1, 0xE7000000; +CHECKREG r2, 0xFA455608; +CHECKREG r3, 0x38233406; +CHECKREG r4, 0x39222202; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x8B1BAAEB; +CHECKREG r7, 0x79918889; + +imm32 r0, 0x5a678911; +imm32 r1, 0x67c9ab1d; +imm32 r2, 0x744d5515; +imm32 r3, 0x8666b717; +imm32 r4, 0x9567891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x74445f15; +imm32 r7, 0x866677f7; +R0 = R6 - R0 (NS); +R1 = R6 - R1 (NS); +R2 = R6 - R2 (NS); +R3 = R6 - R3 (NS); +R4 = R6 - R4 (NS); +R5 = R6 - R5 (NS); +R6 = R6 - R6 (NS); +R7 = R6 - R7 (NS); +CHECKREG r0, 0x19DCD604; +CHECKREG r1, 0x0C7AB3F8; +CHECKREG r2, 0xFFF70A00; +CHECKREG r3, 0xEDDDA7FE; +CHECKREG r4, 0xDEDCD5FA; +CHECKREG r5, 0x0CBA83F8; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x79998809; + +imm32 r0, 0x25678911; +imm32 r1, 0x2389ab1d; +imm32 r2, 0x3a455515; +imm32 r3, 0x46d66717; +imm32 r4, 0x556b891b; +imm32 r5, 0x6789cb1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R7 - R0 (NS); +R1 = R7 - R1 (NS); +R2 = R7 - R2 (NS); +R3 = R7 - R3 (NS); +R4 = R7 - R4 (NS); +R5 = R7 - R5 (NS); +R6 = R7 - R6 (NS); +R7 = R7 - R7 (NS); +CHECKREG r0, 0x60FEEE66; +CHECKREG r1, 0x62DCCC5A; +CHECKREG r2, 0x4C212262; +CHECKREG r3, 0x3F901060; +CHECKREG r4, 0x30FAEE5C; +CHECKREG r5, 0x1EDCAC5A; +CHECKREG r6, 0x12222262; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xd5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34f45515; +imm32 r3, 0x466b7717; +imm32 r4, 0x5567c91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445115; +imm32 r7, 0x866a7d77; +R3 = R1 - R4 (S); +R7 = R4 - R6 (S); +R2 = R7 - R7 (S); +R4 = R5 - R0 (S); +R5 = R3 - R1 (S); +R6 = R2 - R3 (S); +R0 = R0 - R2 (S); +R1 = R6 - R5 (S); +CHECKREG r0, 0xD5678911; +CHECKREG r1, 0x7C45E719; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xD921E202; +CHECKREG r4, 0x7FFFFFFF; +CHECKREG r5, 0xAA9836E5; +CHECKREG r6, 0x26DE1DFE; +CHECKREG r7, 0xE1237806; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3 = R3 - R3 (S); +R1 = R7 - R6 (S); +R4 = R1 - R2 (S); +R7 = R4 - R0 (S); +R5 = R6 - R4 (S); +R2 = R5 - R5 (S); +R6 = R2 - R1 (S); +R0 = R0 - R7 (S); +CHECKREG r0, 0x7FFFFFFF; +CHECKREG r1, 0x80000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x7FFFFFFF; +CHECKREG r6, 0x7FFFFFFF; +CHECKREG r7, 0x80000000; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rmm.s b/sim/testsuite/bfin/c_dsp32alu_rmm.s new file mode 100644 index 0000000..85170a8 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rmm.s @@ -0,0 +1,264 @@ +//Original:/testcases/core/c_dsp32alu_rmm/c_dsp32alu_rmm.dsp +// Spec Reference: dsp32alu dreg = -/- ( dreg, dreg) +# mach: bfin + +.include "testutils.inc" + start + + + + +// ALU operations include parallel addition, subtraction +// and 32-bit data. If an operation use a single ALU only, it uses ALU0. + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R0 -|- R0; +R1 = R0 -|- R1; +R2 = R0 -|- R2; +R3 = R0 -|- R3; +R4 = R0 -|- R4; +R5 = R0 -|- R5; +R6 = R0 -|- R6; +R7 = R0 -|- R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xD87754E3; +CHECKREG r2, 0xCBBCAAEB; +CHECKREG r3, 0xB99A88E9; +CHECKREG r4, 0xAA9976E5; +CHECKREG r5, 0x987754E3; +CHECKREG r6, 0x8BBCAAEB; +CHECKREG r7, 0x799A8889; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = R1 -|- R0; +R1 = R1 -|- R1; +R2 = R1 -|- R2; +R3 = R1 -|- R3; +R4 = R1 -|- R4; +R5 = R1 -|- R5; +R6 = R1 -|- R6; +R7 = R1 -|- R7; +CHECKREG r0, 0x12222202; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x4BBCAADB; +CHECKREG r3, 0x399A88D9; +CHECKREG r4, 0x277866D7; +CHECKREG r5, 0x155644D5; +CHECKREG r6, 0x033422D3; +CHECKREG r7, 0xF1120001; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r4, 0x456789ab; +imm32 r5, 0x6689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = R2 -|- R0; +R1 = R2 -|- R1; +R2 = R2 -|- R2; +R3 = R2 -|- R3; +R4 = R2 -|- R4; +R5 = R2 -|- R5; +R6 = R2 -|- R6; +R7 = R2 -|- R7; +CHECKREG r0, 0x01DDCBAA; +CHECKREG r1, 0xE0BBA988; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x9B9A8889; +CHECKREG r4, 0xBA997655; +CHECKREG r5, 0x99775433; +CHECKREG r6, 0xB8BCAAAB; +CHECKREG r7, 0x979A8889; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = R3 -|- R0; +R1 = R3 -|- R1; +R2 = R3 -|- R2; +R3 = R3 -|- R3; +R4 = R3 -|- R4; +R5 = R3 -|- R5; +R6 = R3 -|- R6; +R7 = R3 -|- R7; +CHECKREG r0, 0x30FFEDFC; +CHECKREG r1, 0x1EDDCBFA; +CHECKREG r2, 0x12222202; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x456789AB; +CHECKREG r5, 0x6689ABCD; +CHECKREG r6, 0x47445555; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x4537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x44555535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = R4 -|- R0; +R1 = R4 -|- R1; +R2 = R4 -|- R2; +R3 = R4 -|- R3; +R4 = R4 -|- R4; +R5 = R4 -|- R5; +R6 = R4 -|- R6; +R7 = R4 -|- R7; +CHECKREG r0, 0x43410C4A; +CHECKREG r1, 0x211FEA38; +CHECKREG r2, 0x44234030; +CHECKREG r3, 0x22123E1E; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x557644A5; +CHECKREG r6, 0x3364227B; +CHECKREG r7, 0x11520061; + +imm32 r0, 0x456b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = R5 -|- R0; +R1 = R5 -|- R1; +R2 = R5 -|- R2; +R3 = R5 -|- R3; +R4 = R5 -|- R4; +R5 = R5 -|- R5; +R6 = R5 -|- R6; +R7 = R5 -|- R7; +CHECKREG r0, 0x653F8210; +CHECKREG r1, 0x4134BFEE; +CHECKREG r2, 0x6137A657; +CHECKREG r3, 0x49838827; +CHECKREG r4, 0x1223A782; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x3334E223; +CHECKREG r7, 0xEDCC9001; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = R6 -|- R0; +R1 = R6 -|- R1; +R2 = R6 -|- R2; +R3 = R6 -|- R3; +R4 = R6 -|- R4; +R5 = R6 -|- R5; +R6 = R6 -|- R6; +R7 = R6 -|- R7; +CHECKREG r0, 0xBECB572B; +CHECKREG r1, 0x9CC94509; +CHECKREG r2, 0x00ED2981; +CHECKREG r3, 0x9DCC295F; +CHECKREG r4, 0xF1FE3A3D; +CHECKREG r5, 0xBECB056B; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xEDCCA981; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = R7 -|- R0; +R1 = R7 -|- R1; +R2 = R7 -|- R2; +R3 = R7 -|- R3; +R4 = R7 -|- R4; +R5 = R7 -|- R5; +R6 = R7 -|- R6; +R7 = R7 -|- R7; +CHECKREG r0, 0x6466A64C; +CHECKREG r1, 0x4454842A; +CHECKREG r2, 0x8888C8A2; +CHECKREG r3, 0x55559FF0; +CHECKREG r4, 0x3333785E; +CHECKREG r5, 0x0123243C; +CHECKREG r6, 0x2222127A; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = R4 -|- R7 (S); +R5 = R5 -|- R5 (CO); +R2 = R6 -|- R3 (SCO); +R6 = R0 -|- R4 (S); +R0 = R1 -|- R6 (S); +R2 = R2 -|- R1 (CO); +R1 = R3 -|- R0 (CO); +R7 = R7 -|- R4 (SCO); +CHECKREG r0, 0x2202123C; +CHECKREG r1, 0x553B4464; +CHECKREG r2, 0x51FF1897; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x0000001A; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x45673991; +CHECKREG r7, 0x56651234; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = R4 -|- R0 (S); +R5 = R5 -|- R1 (SCO); +R2 = R2 -|- R2 (S); +R7 = R7 -|- R3 (CO); +R4 = R3 -|- R4 (CO); +R0 = R1 -|- R5 (S); +R1 = R0 -|- R6 (SCO); +R6 = R6 -|- R7 (SCO); +CHECKREG r0, 0x078B2BCD; +CHECKREG r1, 0x0E507DE0; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x31332DEE; +CHECKREG r4, 0x7655B899; +CHECKREG r5, 0x5FEE8000; +CHECKREG r6, 0xA2E387A2; +CHECKREG r7, 0x02097A9A; + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rmp.s b/sim/testsuite/bfin/c_dsp32alu_rmp.s new file mode 100644 index 0000000..b15397d --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rmp.s @@ -0,0 +1,264 @@ +//Original:/testcases/core/c_dsp32alu_rmp/c_dsp32alu_rmp.dsp +// Spec Reference: dsp32alu dreg = -/+ ( dreg, dreg) +# mach: bfin + +.include "testutils.inc" + start + + + + +// ALU operations include parallel addition, subtraction +// and 32-bit data. If an operation use a single ALU only, it uses ALU0. + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R0 -|+ R0; +R1 = R0 -|+ R1; +R2 = R0 -|+ R2; +R3 = R0 -|+ R3; +R4 = R0 -|+ R4; +R5 = R0 -|+ R5; +R6 = R0 -|+ R6; +R7 = R0 -|+ R7; +CHECKREG r0, 0x00001222; +CHECKREG r1, 0xD877BD3F; +CHECKREG r2, 0xCBBC6737; +CHECKREG r3, 0xB99A8939; +CHECKREG r4, 0xAA999B3D; +CHECKREG r5, 0x9877BD3F; +CHECKREG r6, 0x8BBC6737; +CHECKREG r7, 0x799A8999; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = R1 -|+ R0; +R1 = R1 -|+ R1; +R2 = R1 -|+ R2; +R3 = R1 -|+ R3; +R4 = R1 -|+ R4; +R5 = R1 -|+ R5; +R6 = R1 -|+ R6; +R7 = R1 -|+ R7; +CHECKREG r0, 0x12223458; +CHECKREG r1, 0x0000565A; +CHECKREG r2, 0x4BBCAB7F; +CHECKREG r3, 0x399ACD81; +CHECKREG r4, 0x2778EF83; +CHECKREG r5, 0x15561185; +CHECKREG r6, 0x03343387; +CHECKREG r7, 0xF1125659; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r4, 0x456789ab; +imm32 r5, 0x6689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = R2 -|+ R0; +R1 = R2 -|+ R1; +R2 = R2 -|+ R2; +R3 = R2 -|+ R3; +R4 = R2 -|+ R4; +R5 = R2 -|+ R5; +R6 = R2 -|+ R6; +R7 = R2 -|+ R7; +CHECKREG r0, 0x01DDDF00; +CHECKREG r1, 0xE0BB0122; +CHECKREG r2, 0x0000AAAA; +CHECKREG r3, 0x9B9A2221; +CHECKREG r4, 0xBA993455; +CHECKREG r5, 0x99775677; +CHECKREG r6, 0xB8BCFFFF; +CHECKREG r7, 0x979A2221; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = R3 -|+ R0; +R1 = R3 -|+ R1; +R2 = R3 -|+ R2; +R3 = R3 -|+ R3; +R4 = R3 -|+ R4; +R5 = R3 -|+ R5; +R6 = R3 -|+ R6; +R7 = R3 -|+ R7; +CHECKREG r4, 0x456722A3; +CHECKREG r5, 0x668944C5; +CHECKREG r6, 0x4744EE4D; +CHECKREG r7, 0x6866106F; +CHECKREG r4, 0x456722A3; +CHECKREG r5, 0x668944C5; +CHECKREG r6, 0x4744EE4D; +CHECKREG r7, 0x6866106F; + +imm32 r0, 0x4537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x44555535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = R4 -|+ R0; +R1 = R4 -|+ R1; +R2 = R4 -|+ R2; +R3 = R4 -|+ R3; +R4 = R4 -|+ R4; +R5 = R4 -|+ R5; +R6 = R4 -|+ R6; +R7 = R4 -|+ R7; +CHECKREG r0, 0x43411E80; +CHECKREG r1, 0x211F4092; +CHECKREG r2, 0x4423EA9A; +CHECKREG r3, 0x2212ECAC; +CHECKREG r4, 0x00002ACA; +CHECKREG r5, 0x5576E625; +CHECKREG r6, 0x3364084F; +CHECKREG r7, 0x11522A69; + +imm32 r0, 0x456b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = R5 -|+ R0; +R1 = R5 -|+ R1; +R2 = R5 -|+ R2; +R3 = R5 -|+ R3; +R4 = R5 -|+ R4; +R5 = R5 -|+ R5; +R6 = R5 -|+ R6; +R7 = R5 -|+ R7; +CHECKREG r0, 0x653F9566; +CHECKREG r1, 0x41345788; +CHECKREG r2, 0x6137711F; +CHECKREG r3, 0x49838F4F; +CHECKREG r4, 0x12236FF4; +CHECKREG r5, 0x00001776; +CHECKREG r6, 0x33343553; +CHECKREG r7, 0xEDCC8775; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = R6 -|+ R0; +R1 = R6 -|+ R1; +R2 = R6 -|+ R2; +R3 = R6 -|+ R3; +R4 = R6 -|+ R4; +R5 = R6 -|+ R5; +R6 = R6 -|+ R6; +R7 = R6 -|+ R7; +CHECKREG r0, 0xBECBCA81; +CHECKREG r1, 0x9CC9DCA3; +CHECKREG r2, 0x00EDF82B; +CHECKREG r3, 0x9DCCF84D; +CHECKREG r4, 0xF1FEE76F; +CHECKREG r5, 0xBECB1C41; +CHECKREG r6, 0x000021AC; +CHECKREG r7, 0xEDCC782B; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = R7 -|+ R0; +R1 = R7 -|+ R1; +R2 = R7 -|+ R2; +R3 = R7 -|+ R3; +R4 = R7 -|+ R4; +R5 = R7 -|+ R5; +R6 = R7 -|+ R6; +R7 = R7 -|+ R7; +CHECKREG r0, 0x6466B9A2; +CHECKREG r1, 0x4454DBC4; +CHECKREG r2, 0x8888974C; +CHECKREG r3, 0x5555BFFE; +CHECKREG r4, 0x3333E790; +CHECKREG r5, 0x01233BB2; +CHECKREG r6, 0x22224D74; +CHECKREG r7, 0x00005FEE; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = R4 -|+ R7 (S); +R5 = R5 -|+ R5 (CO); +R2 = R6 -|+ R3 (SCO); +R6 = R0 -|+ R4 (S); +R0 = R1 -|+ R6 (S); +R2 = R2 -|+ R1 (CO); +R1 = R3 -|+ R0 (CO); +R7 = R7 -|+ R4 (SCO); +CHECKREG r0, 0x22027FFF; +CHECKREG r1, 0xE7764464; +CHECKREG r2, 0xE99990E4; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x00007FFF; +CHECKREG r5, 0x16D60000; +CHECKREG r6, 0x45677FFF; +CHECKREG r7, 0x7FFF1234; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = R4 -|+ R0 (S); +R5 = R5 -|+ R1 (SCO); +R2 = R2 -|+ R2 (S); +R7 = R7 -|+ R3 (CO); +R4 = R3 -|+ R4 (CO); +R0 = R1 -|+ R5 (S); +R1 = R0 -|+ R6 (SCO); +R6 = R6 -|+ R7 (SCO); +CHECKREG r0, 0x7FFF8000; +CHECKREG r1, 0x9D7D7FFF; +CHECKREG r2, 0x00007FFF; +CHECKREG r3, 0x31338000; +CHECKREG r4, 0x3799B899; +CHECKREG r5, 0xB7888000; +CHECKREG r6, 0x7FFFD9B4; +CHECKREG r7, 0xAFF77A9A; + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rp.s b/sim/testsuite/bfin/c_dsp32alu_rp.s new file mode 100644 index 0000000..6984bc4 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rp.s @@ -0,0 +1,262 @@ +//Original:/testcases/core/c_dsp32alu_rp/c_dsp32alu_rp.dsp +// Spec Reference: dsp32alu +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34a45515; +imm32 r3, 0x466a7717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445a15; +imm32 r7, 0x866677a7; +R0 = R0 + R0 (NS); +R1 = R0 + R1 (NS); +R2 = R0 + R2 (NS); +R3 = R0 + R3 (NS); +R4 = R0 + R4 (NS); +R5 = R0 + R5 (NS); +R6 = R0 + R6 (NS); +R7 = R0 + R7 (NS); +CHECKREG r0, 0x4ACF1222; +CHECKREG r1, 0x7558BD3F; +CHECKREG r2, 0x7F736737; +CHECKREG r3, 0x91398939; +CHECKREG r4, 0xA0369B3D; +CHECKREG r5, 0xB258BD3F; +CHECKREG r6, 0xBF136C37; +CHECKREG r7, 0xD13589C9; + +imm32 r0, 0xabc78911; +imm32 r1, 0x27c9ab1d; +imm32 r2, 0x344c5515; +imm32 r3, 0x4666c717; +imm32 r4, 0x5567c91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445c15; +imm32 r7, 0x866677c7; +R0 = R1 + R0 (NS); +R1 = R1 + R1 (NS); +R2 = R1 + R2 (NS); +R3 = R1 + R3 (NS); +R4 = R1 + R4 (NS); +R5 = R1 + R5 (NS); +R6 = R1 + R6 (NS); +R7 = R1 + R7 (NS); +CHECKREG r0, 0xD391342E; +CHECKREG r1, 0x4F93563A; +CHECKREG r2, 0x83DFAB4F; +CHECKREG r3, 0x95FA1D51; +CHECKREG r4, 0xA4FB1F55; +CHECKREG r5, 0xB71D0157; +CHECKREG r6, 0xC3D7B24F; +CHECKREG r7, 0xD5F9CE01; + +imm32 r0, 0xdd678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x5567891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R0 = R2 + R0 (NS); +R1 = R2 + R1 (NS); +R2 = R2 + R2 (NS); +R3 = R2 + R3 (NS); +R4 = R2 + R4 (NS); +R5 = R2 + R5 (NS); +R6 = R2 + R6 (NS); +R7 = R2 + R7 (NS); +CHECKREG r0, 0x11ABDE26; +CHECKREG r1, 0x5BCE0032; +CHECKREG r2, 0x6888AA2A; +CHECKREG r3, 0xAF5F2141; +CHECKREG r4, 0xBDF03345; +CHECKREG r5, 0xD0165547; +CHECKREG r6, 0xDCCD7F3F; +CHECKREG r7, 0xEEEF27A1; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R3 + R0 (NS); +R1 = R3 + R1 (NS); +R2 = R3 + R2 (NS); +R3 = R3 + R3 (NS); +R4 = R3 + R4 (NS); +R5 = R3 + R5 (NS); +R6 = R3 + R6 (NS); +R7 = R3 + R7 (NS); +CHECKREG r0, 0x5BCE0028; +CHECKREG r1, 0x6DF02234; +CHECKREG r2, 0x7AAACC2C; +CHECKREG r3, 0x8CCCEE2E; +CHECKREG r4, 0xE2347749; +CHECKREG r5, 0xF456994B; +CHECKREG r6, 0x01114343; +CHECKREG r7, 0x133365A5; + +imm32 r0, 0xee678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34e45515; +imm32 r3, 0x46667717; +imm32 r4, 0x556e891b; +imm32 r5, 0x6789eb1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667e77; +R0 = R4 + R0 (NS); +R1 = R4 + R1 (NS); +R2 = R4 + R2 (NS); +R3 = R4 + R3 (NS); +R4 = R4 + R4 (NS); +R5 = R4 + R5 (NS); +R6 = R4 + R6 (NS); +R7 = R4 + R7 (NS); +CHECKREG r0, 0x43D6122C; +CHECKREG r1, 0x7CF83438; +CHECKREG r2, 0x8A52DE30; +CHECKREG r3, 0x9BD50032; +CHECKREG r4, 0xAADD1236; +CHECKREG r5, 0x1266FD53; +CHECKREG r6, 0x1F21674B; +CHECKREG r7, 0x314390AD; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R5 + R0 (NS); +R1 = R5 + R1 (NS); +R2 = R5 + R2 (NS); +R3 = R5 + R3 (NS); +R4 = R5 + R4 (NS); +R5 = R5 + R5 (NS); +R6 = R5 + R6 (NS); +R7 = R5 + R7 (NS); +CHECKREG r0, 0x7CF1342E; +CHECKREG r1, 0x8F13563A; +CHECKREG r2, 0x9BCE0032; +CHECKREG r3, 0xADF02234; +CHECKREG r4, 0xBCF13438; +CHECKREG r5, 0xCF13563A; +CHECKREG r6, 0x4357AB4F; +CHECKREG r7, 0x5579CDB1; + +imm32 r0, 0xff678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34f45515; +imm32 r3, 0x46667717; +imm32 r4, 0x556f891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444f515; +imm32 r7, 0x86667f77; +R0 = R6 + R0 (NS); +R1 = R6 + R1 (NS); +R2 = R6 + R2 (NS); +R3 = R6 + R3 (NS); +R4 = R6 + R4 (NS); +R5 = R6 + R5 (NS); +R6 = R6 + R6 (NS); +R7 = R6 + R7 (NS); +CHECKREG r0, 0x73AC7E26; +CHECKREG r1, 0x9BCEA032; +CHECKREG r2, 0xA9394A2A; +CHECKREG r3, 0xBAAB6C2C; +CHECKREG r4, 0xC9B47E30; +CHECKREG r5, 0xDBCEA032; +CHECKREG r6, 0xE889EA2A; +CHECKREG r7, 0x6EF069A1; + +imm32 r0, 0xed678911; +imm32 r1, 0x27d9ab1d; +imm32 r2, 0x344d5515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567c91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445c15; +imm32 r7, 0x866677c7; +R0 = R7 + R0 (NS); +R1 = R7 + R1 (NS); +R2 = R7 + R2 (NS); +R3 = R7 + R3 (NS); +R4 = R7 + R4 (NS); +R5 = R7 + R5 (NS); +R6 = R7 + R6 (NS); +R7 = R7 + R7 (NS); +CHECKREG r0, 0x73CE00D8; +CHECKREG r1, 0xAE4022E4; +CHECKREG r2, 0xBAB3CCDC; +CHECKREG r3, 0xCCCCEEDE; +CHECKREG r4, 0xDBCE40E2; +CHECKREG r5, 0xEDF022E4; +CHECKREG r6, 0xFAAAD3DC; +CHECKREG r7, 0x0CCCEF8E; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3 = R1 + R4 (S); +R7 = R4 + R6 (S); +R2 = R7 + R7 (S); +R4 = R5 + R0 (S); +R5 = R3 + R1 (S); +R6 = R2 + R3 (S); +R0 = R0 + R2 (S); +R1 = R6 + R5 (S); +CHECKREG r0, 0x7FFFFFFF; +CHECKREG r1, 0x7FFFFFFF; +CHECKREG r2, 0x7FFFFFFF; +CHECKREG r3, 0x7CF13438; +CHECKREG r4, 0x7CF1342E; +CHECKREG r5, 0x7FFFFFFF; +CHECKREG r6, 0x7FFFFFFF; +CHECKREG r7, 0x7FFFFFFF; + +imm32 r0, 0x55678911; +imm32 r1, 0x6a89ab1d; +imm32 r2, 0x74d45515; +imm32 r3, 0x866f7717; +imm32 r4, 0x5567c91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3 = R3 + R3 (S); +R1 = R7 + R6 (S); +R4 = R1 + R2 (S); +R7 = R4 + R0 (S); +R5 = R6 + R4 (S); +R2 = R5 + R5 (S); +R6 = R2 + R1 (S); +R0 = R0 + R7 (S); +CHECKREG r0, 0x7FFFFFFF; +CHECKREG r1, 0xFAAACC8C; +CHECKREG r2, 0x7FFFFFFF; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x6F7F21A1; +CHECKREG r5, 0x7FFFFFFF; +CHECKREG r6, 0x7AAACC8B; +CHECKREG r7, 0x7FFFFFFF; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rpm.s b/sim/testsuite/bfin/c_dsp32alu_rpm.s new file mode 100644 index 0000000..ebdec07 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rpm.s @@ -0,0 +1,264 @@ +//Original:/testcases/core/c_dsp32alu_rpm/c_dsp32alu_rpm.dsp +// Spec Reference: dsp32alu dreg = +/- ( dreg, dreg) +# mach: bfin + +.include "testutils.inc" + start + + + + +// ALU operations include parallel addition, subtraction +// and 32-bit data. If an operation use a single ALU only, it uses ALU0. + +imm32 r0, 0x65678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34845515; +imm32 r3, 0x46697717; +imm32 r4, 0x5567191b; +imm32 r5, 0x6789a31d; +imm32 r6, 0x74445545; +imm32 r7, 0x86667779; +R0 = R0 +|- R0; +R1 = R0 +|- R1; +R2 = R0 +|- R2; +R3 = R0 +|- R3; +R4 = R0 +|- R4; +R5 = R0 +|- R5; +R6 = R0 +|- R6; +R7 = R0 +|- R7; +CHECKREG r0, 0xCACE0000; +CHECKREG r1, 0xF25754E3; +CHECKREG r2, 0xFF52AAEB; +CHECKREG r3, 0x113788E9; +CHECKREG r4, 0x2035E6E5; +CHECKREG r5, 0x32575CE3; +CHECKREG r6, 0x3F12AABB; +CHECKREG r7, 0x51348887; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = R1 +|- R0; +R1 = R1 +|- R1; +R2 = R1 +|- R2; +R3 = R1 +|- R3; +R4 = R1 +|- R4; +R5 = R1 +|- R5; +R6 = R1 +|- R6; +R7 = R1 +|- R7; +CHECKREG r0, 0x3CF02202; +CHECKREG r1, 0x4F120000; +CHECKREG r2, 0x0356AADB; +CHECKREG r3, 0x157888D9; +CHECKREG r4, 0x279A66D7; +CHECKREG r5, 0x39BC44D5; +CHECKREG r6, 0x4BDE22D3; +CHECKREG r7, 0x5E000001; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r4, 0x456789ab; +imm32 r5, 0x6689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = R2 +|- R0; +R1 = R2 +|- R1; +R2 = R2 +|- R2; +R3 = R2 +|- R3; +R4 = R2 +|- R4; +R5 = R2 +|- R5; +R6 = R2 +|- R6; +R7 = R2 +|- R7; +CHECKREG r0, 0x84ABCBAA; +CHECKREG r1, 0xA5CDA988; +CHECKREG r2, 0x86880000; +CHECKREG r3, 0xEAEE8889; +CHECKREG r4, 0xCBEF7655; +CHECKREG r5, 0xED115433; +CHECKREG r6, 0xCDCCAAAB; +CHECKREG r7, 0xEEEE8889; + +imm32 r0, 0xa567892b; +imm32 r1, 0xaa89ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6a67727; +imm32 r0, 0x9a67892b; +imm32 r1, 0xa7a9ab2d; +imm32 r2, 0xb44a5525; +imm32 r3, 0xc666a727; +R0 = R3 +|- R0; +R1 = R3 +|- R1; +R2 = R3 +|- R2; +R3 = R3 +|- R3; +R4 = R3 +|- R4; +R5 = R3 +|- R5; +R6 = R3 +|- R6; +R7 = R3 +|- R7; +CHECKREG r0, 0x60CD1DFC; +CHECKREG r1, 0x6E0FFBFA; +CHECKREG r2, 0x7AB05202; +CHECKREG r3, 0x8CCC0000; +CHECKREG r4, 0x58BB89AB; +CHECKREG r5, 0x79DDABCD; +CHECKREG r6, 0x5A985555; +CHECKREG r7, 0x7BBA7777; + +imm32 r0, 0x4537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x44555535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = R4 +|- R0; +R1 = R4 +|- R1; +R2 = R4 +|- R2; +R3 = R4 +|- R3; +R4 = R4 +|- R4; +R5 = R4 +|- R5; +R6 = R4 +|- R6; +R7 = R4 +|- R7; +CHECKREG r0, 0xCDAF0C4A; +CHECKREG r1, 0xEFD1EA38; +CHECKREG r2, 0xCCCD4030; +CHECKREG r3, 0xEEDE3E1E; +CHECKREG r4, 0x10F00000; +CHECKREG r5, 0xBB7A44A5; +CHECKREG r6, 0xDD8C227B; +CHECKREG r7, 0xFF9E0061; + +imm32 r0, 0x456b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = R5 +|- R0; +R1 = R5 +|- R1; +R2 = R5 +|- R2; +R3 = R5 +|- R3; +R4 = R5 +|- R4; +R5 = R5 +|- R5; +R6 = R5 +|- R6; +R7 = R5 +|- R7; +CHECKREG r0, 0xF0158210; +CHECKREG r1, 0x1420BFEE; +CHECKREG r2, 0xF41DA657; +CHECKREG r3, 0x0BD18827; +CHECKREG r4, 0x4331A782; +CHECKREG r5, 0x55540000; +CHECKREG r6, 0x2220E223; +CHECKREG r7, 0x67889001; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = R6 +|- R0; +R1 = R6 +|- R1; +R2 = R6 +|- R2; +R3 = R6 +|- R3; +R4 = R6 +|- R4; +R5 = R6 +|- R5; +R6 = R6 +|- R6; +R7 = R6 +|- R7; +CHECKREG r0, 0x4999572B; +CHECKREG r1, 0x6B9B4509; +CHECKREG r2, 0x07772981; +CHECKREG r3, 0x6A98295F; +CHECKREG r4, 0x16663A3D; +CHECKREG r5, 0x4999056B; +CHECKREG r6, 0x08640000; +CHECKREG r7, 0x1A98A981; + +imm32 r0, 0xb76789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x2b456755; +imm32 r3, 0x56789007; +imm32 r4, 0x78bab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcdbff7; +R0 = R7 +|- R0; +R1 = R7 +|- R1; +R2 = R7 +|- R2; +R3 = R7 +|- R3; +R4 = R7 +|- R4; +R5 = R7 +|- R5; +R6 = R7 +|- R6; +R7 = R7 +|- R7; +CHECKREG r0, 0x6334364C; +CHECKREG r1, 0x1346142A; +CHECKREG r2, 0xD71258A2; +CHECKREG r3, 0x02452FF0; +CHECKREG r4, 0x2487085E; +CHECKREG r5, 0x5677B43C; +CHECKREG r6, 0x3578A27A; +CHECKREG r7, 0x579A0000; +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = R4 +|- R7 (S); +R5 = R5 +|- R5 (CO); +R2 = R6 +|- R3 (SCO); +R6 = R0 +|- R4 (S); +R0 = R1 +|- R6 (S); +R2 = R2 +|- R1 (CO); +R1 = R3 +|- R0 (CO); +R7 = R7 +|- R4 (SCO); +CHECKREG r0, 0x7FFF123C; +CHECKREG r1, 0x553BE665; +CHECKREG r2, 0x1ECBE769; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x2468001A; +CHECKREG r5, 0x00008ACE; +CHECKREG r6, 0x69CF3991; +CHECKREG r7, 0x5665369C; + +imm32 r0, 0xb76789ab; +imm32 r1, 0x6b79abcd; +imm32 r2, 0x2b456755; +imm32 r3, 0x56b89007; +imm32 r4, 0x78bab799; +imm32 r5, 0xaaab0bbb; +imm32 r6, 0x89abbd7d; +imm32 r7, 0xabcd2bf7; +R3 = R4 +|- R0 (S); +R5 = R5 +|- R1 (SCO); +R2 = R2 +|- R2 (S); +R7 = R7 +|- R3 (CO); +R4 = R3 +|- R4 (CO); +R0 = R1 +|- R5 (S); +R1 = R0 +|- R6 (SCO); +R6 = R6 +|- R7 (SCO); +CHECKREG r0, 0x7FFF95A9; +CHECKREG r1, 0xD82C09AA; +CHECKREG r2, 0x568A0000; +CHECKREG r3, 0x30212DEE; +CHECKREG r4, 0x7655A8DB; +CHECKREG r5, 0x5FEE1624; +CHECKREG r6, 0xE18F87B4; +CHECKREG r7, 0xFE09DBEE; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rpp.s b/sim/testsuite/bfin/c_dsp32alu_rpp.s new file mode 100644 index 0000000..5a69267 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rpp.s @@ -0,0 +1,266 @@ +//Original:/testcases/core/c_dsp32alu_rpp/c_dsp32alu_rpp.dsp +// Spec Reference: dsp32alu dreg = +/+ ( dreg, dreg) +# mach: bfin + +.include "testutils.inc" + start + + + + +// ALU operations include parallel addition, subtraction +// and 32-bit data. If an operation use a single ALU only, it uses ALU0. + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R0 +|+ R0; +R1 = R0 +|+ R1; +R2 = R0 +|+ R2; +R3 = R0 +|+ R3; +R4 = R0 +|+ R4; +R5 = R0 +|+ R5; +R6 = R0 +|+ R6; +R7 = R0 +|+ R7; +CHECKREG r0, 0x2ACE1222; +CHECKREG r1, 0x5257BD3F; +CHECKREG r2, 0x5F126737; +CHECKREG r3, 0x71348939; +CHECKREG r4, 0x80359B3D; +CHECKREG r5, 0x9257BD3F; +CHECKREG r6, 0x9F126737; +CHECKREG r7, 0xB1348999; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = R1 +|+ R0; +R1 = R1 +|+ R1; +R2 = R1 +|+ R2; +R3 = R1 +|+ R3; +R4 = R1 +|+ R4; +R5 = R1 +|+ R5; +R6 = R1 +|+ R6; +R7 = R1 +|+ R7; +CHECKREG r0, 0x3CF03458; +CHECKREG r1, 0x4F12565A; +CHECKREG r2, 0x0356AB7F; +CHECKREG r3, 0x1578CD81; +CHECKREG r4, 0x279AEF83; +CHECKREG r5, 0x39BC1185; +CHECKREG r6, 0x4BDE3387; +CHECKREG r7, 0x5E005659; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r4, 0x456789ab; +imm32 r5, 0x6689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = R2 +|+ R0; +R1 = R2 +|+ R1; +R2 = R2 +|+ R2; +R3 = R2 +|+ R3; +R4 = R2 +|+ R4; +R5 = R2 +|+ R5; +R6 = R2 +|+ R6; +R7 = R2 +|+ R7; +CHECKREG r0, 0x84ABDF00; +CHECKREG r1, 0xA5CD0122; +CHECKREG r2, 0x8688AAAA; +CHECKREG r3, 0xEAEE2221; +CHECKREG r4, 0xCBEF3455; +CHECKREG r5, 0xED115677; +CHECKREG r6, 0xCDCCFFFF; +CHECKREG r7, 0xEEEE2221; + +imm32 r0, 0xd567892b; +imm32 r1, 0xad89ab2d; +imm32 r2, 0xb4d45525; +imm32 r3, 0xc66d7727; +imm32 r0, 0x9567d92b; +imm32 r1, 0xa789ad2d; +imm32 r2, 0xb44455d5; +imm32 r3, 0xc666772d; +R0 = R3 +|+ R0; +R1 = R3 +|+ R1; +R2 = R3 +|+ R2; +R3 = R3 +|+ R3; +R4 = R3 +|+ R4; +R5 = R3 +|+ R5; +R6 = R3 +|+ R6; +R7 = R3 +|+ R7; +CHECKREG r0, 0x5BCD5058; +CHECKREG r1, 0x6DEF245A; +CHECKREG r2, 0x7AAACD02; +CHECKREG r3, 0x8CCCEE5A; +CHECKREG r4, 0x58BB22AF; +CHECKREG r5, 0x79DD44D1; +CHECKREG r6, 0x5A98EE59; +CHECKREG r7, 0x7BBA107B; + +imm32 r0, 0x4577891b; +imm32 r1, 0x6779ab2d; +imm32 r2, 0x44755535; +imm32 r3, 0x66765747; +imm32 r4, 0x88779565; +imm32 r5, 0xaa7abb5b; +imm32 r6, 0xcc97dd85; +imm32 r7, 0xeeae7f9f; +R0 = R4 +|+ R0; +R1 = R4 +|+ R1; +R2 = R4 +|+ R2; +R3 = R4 +|+ R3; +R4 = R4 +|+ R4; +R5 = R4 +|+ R5; +R6 = R4 +|+ R6; +R7 = R4 +|+ R7; +CHECKREG r0, 0xCDEE1E80; +CHECKREG r1, 0xEFF04092; +CHECKREG r2, 0xCCECEA9A; +CHECKREG r3, 0xEEEDECAC; +CHECKREG r4, 0x10EE2ACA; +CHECKREG r5, 0xBB68E625; +CHECKREG r6, 0xDD85084F; +CHECKREG r7, 0xFF9CAA69; + +imm32 r0, 0x456b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = R5 +|+ R0; +R1 = R5 +|+ R1; +R2 = R5 +|+ R2; +R3 = R5 +|+ R3; +R4 = R5 +|+ R4; +R5 = R5 +|+ R5; +R6 = R5 +|+ R6; +R7 = R5 +|+ R7; +CHECKREG r0, 0xF0159566; +CHECKREG r1, 0x14205788; +CHECKREG r2, 0xF41D711F; +CHECKREG r3, 0x0BD18F4F; +CHECKREG r4, 0x43316FF4; +CHECKREG r5, 0x55541776; +CHECKREG r6, 0x22203553; +CHECKREG r7, 0x67888775; + +imm32 r0, 0xaa6739ab; +imm32 r1, 0x67dd4bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x6b66bb77; +imm32 r4, 0x12345699; +imm32 r5, 0x45b78b6b; +imm32 r6, 0x043b90d6; +imm32 r7, 0x12b4bb7f; +R0 = R6 +|+ R0; +R1 = R6 +|+ R1; +R2 = R6 +|+ R2; +R3 = R6 +|+ R3; +R4 = R6 +|+ R4; +R5 = R6 +|+ R5; +R6 = R6 +|+ R6; +R7 = R6 +|+ R7; +CHECKREG r0, 0xAEA2CA81; +CHECKREG r1, 0x6C18DCA3; +CHECKREG r2, 0x0780F82B; +CHECKREG r3, 0x6FA14C4D; +CHECKREG r4, 0x166FE76F; +CHECKREG r5, 0x49F21C41; +CHECKREG r6, 0x087621AC; +CHECKREG r7, 0x1B2ADD2B; + +imm32 r0, 0x976789ab; +imm32 r1, 0x6979abcd; +imm32 r2, 0x23956755; +imm32 r3, 0x56799007; +imm32 r4, 0x789a9799; +imm32 r5, 0xaaaa09bb; +imm32 r6, 0x89ab1d9d; +imm32 r7, 0xabcd2ff9; +R0 = R7 +|+ R0; +R1 = R7 +|+ R1; +R2 = R7 +|+ R2; +R3 = R7 +|+ R3; +R4 = R7 +|+ R4; +R5 = R7 +|+ R5; +R6 = R7 +|+ R6; +R7 = R7 +|+ R7; +CHECKREG r0, 0x4334B9A4; +CHECKREG r1, 0x1546DBC6; +CHECKREG r2, 0xCF62974E; +CHECKREG r3, 0x0246C000; +CHECKREG r4, 0x2467C792; +CHECKREG r5, 0x567739B4; +CHECKREG r6, 0x35784D96; +CHECKREG r7, 0x579A5FF2; + +imm32 r0, 0x856739ab; +imm32 r1, 0x87694bcd; +imm32 r2, 0x08856755; +imm32 r3, 0x66686777; +imm32 r4, 0x12385699; +imm32 r5, 0x4567886b; +imm32 r6, 0x04329086; +imm32 r7, 0x12345678; +R4 = R4 +|+ R7 (S); +R5 = R5 +|+ R5 (CO); +R2 = R6 +|+ R3 (SCO); +R6 = R0 +|+ R4 (S); +R0 = R1 +|+ R6 (S); +R2 = R2 +|+ R1 (CO); +R1 = R3 +|+ R0 (CO); +R7 = R7 +|+ R4 (SCO); +CHECKREG r0, 0x80007FFF; +CHECKREG r1, 0xE776E668; +CHECKREG r2, 0xB6677F66; +CHECKREG r3, 0x66686777; +CHECKREG r4, 0x246C7FFF; +CHECKREG r5, 0x10D68ACE; +CHECKREG r6, 0xA9D37FFF; +CHECKREG r7, 0x7FFF36A0; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = R4 +|+ R0 (S); +R5 = R5 +|+ R1 (SCO); +R2 = R2 +|+ R2 (S); +R7 = R7 +|+ R3 (CO); +R4 = R3 +|+ R4 (CO); +R0 = R1 +|+ R5 (S); +R1 = R0 +|+ R6 (SCO); +R6 = R6 +|+ R7 (SCO); +CHECKREG r0, 0x1F01BDF0; +CHECKREG r1, 0xDB6DA8AC; +CHECKREG r2, 0x468A7FFF; +CHECKREG r3, 0x7FFF8000; +CHECKREG r4, 0x3799F899; +CHECKREG r5, 0xB7881223; +CHECKREG r6, 0x49498000; +CHECKREG r7, 0xAFF72BCC; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rr_lph_a1a0.s b/sim/testsuite/bfin/c_dsp32alu_rr_lph_a1a0.s new file mode 100644 index 0000000..5ce3598 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rr_lph_a1a0.s @@ -0,0 +1,33 @@ +//Original:/testcases/core/c_dsp32alu_rr_lph_a1a0/c_dsp32alu_rr_lph_a1a0.dsp +// Spec Reference: dsp32alu (dregs, dregs) = L + H, L + H (a1, a0) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x25678911; +imm32 r1, 0x0029ab2d; +imm32 r2, 0x00145535; +imm32 r3, 0xf6567747; +imm32 r4, 0xe566895b; +imm32 r5, 0x67897b6d; +imm32 r6, 0xb4445875; +imm32 r7, 0x86667797; +A1 = R1; +A0 = R0; + +R2 = A1.L + A1.H, R3 = A0.L + A0.H; +R4 = A1.L + A1.H, R5 = A0.L + A0.H; +R6 = A1.L + A1.H, R7 = A0.L + A0.H; +CHECKREG r2, 0xFFFFAB56; +CHECKREG r3, 0xFFFFAE78; +CHECKREG r4, 0xFFFFAB56; +CHECKREG r5, 0xFFFFAE78; +CHECKREG r6, 0xFFFFAB56; +CHECKREG r7, 0xFFFFAE78; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rrpm.s b/sim/testsuite/bfin/c_dsp32alu_rrpm.s new file mode 100644 index 0000000..2ced758 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rrpm.s @@ -0,0 +1,265 @@ +//Original:/testcases/core/c_dsp32alu_rrpm/c_dsp32alu_rrpm.dsp +// Spec Reference: dsp32alu (dreg, dreg) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x75678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34745515; +imm32 r3, 0x46677717; +imm32 r0, 0x5567a91b; +imm32 r1, 0x6789aa1d; +imm32 r2, 0x744455a5; +imm32 r3, 0x8666777a; +R0 = R0 + R0, R7 = R0 - R0 (NS); +R1 = R0 + R1, R6 = R0 - R1 (NS); +R2 = R0 + R2, R5 = R0 - R2 (NS); +R3 = R0 + R3, R4 = R0 - R3 (NS); +R4 = R0 + R4, R3 = R0 - R4 (NS); +R5 = R0 + R5, R2 = R0 - R5 (NS); +R6 = R0 + R6, R1 = R0 - R6 (NS); +R7 = R0 + R7, R0 = R0 - R7 (NS); +CHECKREG r0, 0xAACF5236; +CHECKREG r1, 0x6789AA1D; +CHECKREG r2, 0x744455A5; +CHECKREG r3, 0x8666777A; +CHECKREG r4, 0xCF382CF2; +CHECKREG r5, 0xE15A4EC7; +CHECKREG r6, 0xEE14FA4F; +CHECKREG r7, 0xAACF5236; + +imm32 r0, 0x4567892b; +imm32 r1, 0x4489ab2d; +imm32 r2, 0x54445525; +imm32 r3, 0x66645727; +imm32 r4, 0x78889629; +imm32 r5, 0x8aaabb6b; +imm32 r6, 0x9cccdd2d; +imm32 r7, 0x0eee3fff; +R0 = R1 + R0, R7 = R1 - R0 (NS); +R1 = R1 + R1, R6 = R1 - R1 (NS); +R2 = R1 + R2, R5 = R1 - R2 (NS); +R3 = R1 + R3, R4 = R1 - R3 (NS); +R4 = R1 + R4, R3 = R1 - R4 (NS); +R5 = R1 + R5, R2 = R1 - R5 (NS); +R6 = R1 + R6, R1 = R1 - R6 (NS); +R7 = R1 + R7, R0 = R1 - R7 (NS); +CHECKREG r0, 0x89F13458; +CHECKREG r1, 0x8913565A; +CHECKREG r2, 0x54445525; +CHECKREG r3, 0x66645727; +CHECKREG r4, 0xABC2558D; +CHECKREG r5, 0xBDE2578F; +CHECKREG r6, 0x8913565A; +CHECKREG r7, 0x8835785C; + + +imm32 r0, 0x496789ab; +imm32 r1, 0x6489abcd; +imm32 r2, 0x4b445555; +imm32 r3, 0x6c647777; +imm32 r4, 0x8d889999; +imm32 r5, 0x1eaa4bbb; +imm32 r6, 0x2fccd44d; +imm32 r7, 0x31eefff4; +R0 = R2 + R0, R7 = R2 - R0 (NS); +R1 = R2 + R1, R6 = R2 - R1 (NS); +R2 = R2 + R2, R5 = R2 - R2 (NS); +R3 = R2 + R3, R4 = R2 - R3 (NS); +R4 = R2 + R4, R3 = R2 - R4 (NS); +R5 = R2 + R5, R2 = R2 - R5 (NS); +R6 = R2 + R6, R1 = R2 - R6 (NS); +R7 = R2 + R7, R0 = R2 - R7 (NS); +CHECKREG r0, 0x94ABDF00; +CHECKREG r1, 0xAFCE0122; +CHECKREG r2, 0x9688AAAA; +CHECKREG r3, 0x6C647777; +CHECKREG r4, 0xC0ACDDDD; +CHECKREG r5, 0x9688AAAA; +CHECKREG r6, 0x7D435432; +CHECKREG r7, 0x98657654; + +imm32 r0, 0xa537891b; +imm32 r1, 0x6a59ab2d; +imm32 r2, 0x44a55535; +imm32 r3, 0x166a5747; +imm32 r4, 0x6878a565; +imm32 r5, 0x7a8aba5b; +imm32 r6, 0x8c9cdd85; +imm32 r7, 0x9eaeffaf; +R0 = R3 + R0, R7 = R3 - R0 (NS); +R1 = R3 + R1, R6 = R3 - R1 (NS); +R2 = R3 + R2, R5 = R3 - R2 (NS); +R3 = R3 + R3, R4 = R3 - R3 (NS); +R4 = R3 + R4, R3 = R3 - R4 (NS); +R5 = R3 + R5, R2 = R3 - R5 (NS); +R6 = R3 + R6, R1 = R3 - R6 (NS); +R7 = R3 + R7, R0 = R3 - R7 (NS); +CHECKREG r0, 0xBBA1E062; +CHECKREG r1, 0x80C40274; +CHECKREG r2, 0x5B0FAC7C; +CHECKREG r3, 0x2CD4AE8E; +CHECKREG r4, 0x2CD4AE8E; +CHECKREG r5, 0xFE99B0A0; +CHECKREG r6, 0xD8E55AA8; +CHECKREG r7, 0x9E077CBA; + +imm32 r0, 0x15678911; +imm32 r1, 0x9789ab1d; +imm32 r2, 0x94445515; +imm32 r3, 0x96667717; +imm32 r0, 0x5267891b; +imm32 r1, 0x67a9ab1d; +imm32 r2, 0x744c5515; +imm32 r3, 0x8666d777; +R0 = R4 + R0, R7 = R4 - R0 (NS); +R1 = R4 + R1, R6 = R4 - R1 (NS); +R2 = R4 + R2, R5 = R4 - R2 (NS); +R3 = R4 + R3, R4 = R4 - R3 (NS); +R4 = R4 + R4, R3 = R4 - R4 (NS); +R5 = R4 + R5, R2 = R4 - R5 (NS); +R6 = R4 + R6, R1 = R4 - R6 (NS); +R7 = R4 + R7, R0 = R4 - R7 (NS); +CHECKREG r0, 0x726E88BB; +CHECKREG r1, 0x87B0AABD; +CHECKREG r2, 0x945354B5; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x4CDBAE2E; +CHECKREG r5, 0x056407A7; +CHECKREG r6, 0x1206B19F; +CHECKREG r7, 0x2748D3A1; + +imm32 r0, 0xa567892b; +imm32 r1, 0x4a89ab2d; +imm32 r2, 0x54a45525; +imm32 r3, 0x666d7727; +imm32 r4, 0x7888d929; +imm32 r5, 0x8aaabe2b; +imm32 r6, 0x9cccdd2d; +imm32 r7, 0x0eeeffef; +R0 = R5 + R0, R7 = R5 - R0 (NS); +R1 = R5 + R1, R6 = R5 - R1 (NS); +R2 = R5 + R2, R5 = R5 - R2 (NS); +R3 = R5 + R3, R4 = R5 - R3 (NS); +R4 = R5 + R4, R3 = R5 - R4 (NS); +R5 = R5 + R5, R2 = R5 - R5 (NS); +R6 = R5 + R6, R1 = R5 - R6 (NS); +R7 = R5 + R7, R0 = R5 - R7 (NS); +CHECKREG r0, 0x86C99D0C; +CHECKREG r1, 0x2BEBBF0E; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x666D7727; +CHECKREG r4, 0x059F5AE5; +CHECKREG r5, 0x6C0CD20C; +CHECKREG r6, 0xAC2DE50A; +CHECKREG r7, 0x5150070C; + + +imm32 r0, 0x496789ab; +imm32 r1, 0x6489abcd; +imm32 r2, 0x4b445555; +imm32 r3, 0x6c647777; +imm32 r4, 0x8d889999; +imm32 r5, 0x1eaa4bbb; +imm32 r6, 0x2fccd44d; +imm32 r7, 0x31eefff4; +R0 = R6 + R0, R7 = R6 - R0 (NS); +R1 = R6 + R1, R6 = R6 - R1 (NS); +R2 = R6 + R2, R5 = R6 - R2 (NS); +R3 = R6 + R3, R4 = R6 - R3 (NS); +R4 = R6 + R4, R3 = R6 - R4 (NS); +R5 = R6 + R5, R2 = R6 - R5 (NS); +R6 = R6 + R6, R1 = R6 - R6 (NS); +R7 = R6 + R7, R0 = R6 - R7 (NS); +CHECKREG r0, 0xB021065E; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x4B445555; +CHECKREG r3, 0x6C647777; +CHECKREG r4, 0x2A21D989; +CHECKREG r5, 0x4B41FBAB; +CHECKREG r6, 0x96865100; +CHECKREG r7, 0x7CEB9BA2; + +imm32 r0, 0xe537891b; +imm32 r1, 0xe759ab2d; +imm32 r2, 0x4e555535; +imm32 r3, 0x16e65747; +imm32 r4, 0x687e9565; +imm32 r5, 0x7a8aeb5b; +imm32 r6, 0x8c9cdd85; +imm32 r7, 0x9eaefe9f; +R0 = R7 + R0, R7 = R7 - R0 (NS); +R1 = R7 + R1, R6 = R7 - R1 (NS); +R2 = R7 + R2, R5 = R7 - R2 (NS); +R3 = R7 + R3, R4 = R7 - R3 (NS); +R4 = R7 + R4, R3 = R7 - R4 (NS); +R5 = R7 + R5, R2 = R7 - R5 (NS); +R6 = R7 + R6, R1 = R7 - R6 (NS); +R7 = R7 + R7, R0 = R7 - R7 (NS); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xE759AB2D; +CHECKREG r2, 0x4E555535; +CHECKREG r3, 0x16E65747; +CHECKREG r4, 0x5C0893C1; +CHECKREG r5, 0x249995D3; +CHECKREG r6, 0x8B953FDB; +CHECKREG r7, 0x72EEEB08; + +imm32 r0, 0x496789ab; +imm32 r1, 0x6489abcd; +imm32 r2, 0x4b445555; +imm32 r3, 0x6c647777; +imm32 r4, 0x8d889999; +imm32 r5, 0x1eaa4bbb; +imm32 r6, 0x2fccd44d; +imm32 r7, 0x31eefff4; +R2 = R4 + R0, R7 = R4 - R0 (S); +R3 = R7 + R1, R6 = R7 - R1 (NS); +R4 = R0 + R2, R5 = R0 - R2 (S); +R5 = R4 + R3, R4 = R4 - R3 (NS); +R6 = R2 + R4, R3 = R2 - R4 (S); +R7 = R3 + R5, R2 = R3 - R5 (NS); +R0 = R1 + R6, R1 = R1 - R6 (S); +R1 = R5 + R7, R0 = R5 - R7 (S); +CHECKREG r0, 0x64DDDDDE; +CHECKREG r1, 0xA4E4D39A; +CHECKREG r2, 0x9640C966; +CHECKREG r3, 0x9B222222; +CHECKREG r4, 0x3BCE0122; +CHECKREG r5, 0x04E158BC; +CHECKREG r6, 0x12BE2466; +CHECKREG r7, 0xA0037ADE; + +imm32 r0, 0xa537891b; +imm32 r1, 0x6d59ab2d; +imm32 r2, 0x4f555535; +imm32 r3, 0x16c65747; +imm32 r4, 0x687c9565; +imm32 r5, 0x7a8acb5b; +imm32 r6, 0x8c9cdc85; +imm32 r7, 0x9eaefb9f; +R4 = R3 + R0, R1 = R3 - R0 (S); +R5 = R6 + R1, R2 = R6 - R1 (S); +R6 = R7 + R2, R3 = R7 - R2 (S); +R7 = R0 + R3, R4 = R0 - R3 (NS); +R0 = R2 + R4, R5 = R2 - R4 (S); +R1 = R1 + R5, R6 = R1 - R5 (S); +R2 = R5 + R6, R7 = R5 - R6 (NS); +R3 = R4 + R7, R0 = R4 - R7 (S); +CHECKREG r0, 0x052876A0; +CHECKREG r1, 0x6B0640B0; +CHECKREG r2, 0x718ECE2C; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x86888D7C; +CHECKREG r5, 0xF9777284; +CHECKREG r6, 0x78175BA8; +CHECKREG r7, 0x816016DC; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rrpm_aa.s b/sim/testsuite/bfin/c_dsp32alu_rrpm_aa.s new file mode 100644 index 0000000..7c1e3a3 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rrpm_aa.s @@ -0,0 +1,70 @@ +//Original:/testcases/core/c_dsp32alu_rrpm_aa/c_dsp32alu_rrpm_aa.dsp +// Spec Reference: dsp32alu (dregs, dregs) = +/- (a, a) amod1 +# mach: bfin + +.include "testutils.inc" + start + + + +A1 = A0 = 0; + +imm32 r0, 0x75678911; +imm32 r1, 0xa789ab2d; +imm32 r2, 0x34745515; +imm32 r3, 0x46677757; +imm32 r4, 0xb567a96b; +imm32 r5, 0x6789aa1d; +imm32 r6, 0x744455a5; +imm32 r7, 0x8666777a; +A0 = R0; +A1 = R1; + +R0 = A1 + A0, R7 = A1 - A0 (NS); +R1 = A0 + A1, R6 = A0 - A1 (NS); +R2 = A1 + A0, R5 = A1 - A0 (NS); +R3 = A0 + A1, R4 = A0 - A1 (NS); +R4 = A1 + A0, R0 = A1 - A0 (NS); +R5 = A0 + A1, R1 = A0 - A1 (NS); +R6 = A0 + A1, R2 = A0 - A1 (NS); +R7 = A1 + A0, R3 = A1 - A0 (NS); +CHECKREG r0, 0x3222221C; +CHECKREG r1, 0xCDDDDDE4; +CHECKREG r2, 0xCDDDDDE4; +CHECKREG r3, 0x3222221C; +CHECKREG r4, 0x1CF1343E; +CHECKREG r5, 0x1CF1343E; +CHECKREG r6, 0x1CF1343E; +CHECKREG r7, 0x1CF1343E; + +imm32 r0, 0x8537891b; +imm32 r1, 0x3759ab2d; +imm32 r2, 0x4e555535; +imm32 r3, 0x16e65747; +imm32 r4, 0x687e9565; +imm32 r5, 0x7a8aeb5b; +imm32 r6, 0x8c9cdd85; +imm32 r7, 0x9eaefe9f; +A0 = R0; +A1 = R1; +R3 = A1 + A0, R7 = A1 - A0 (S); +R4 = A0 + A1, R6 = A0 - A1 (S); +R5 = A1 + A0, R4 = A1 - A0 (S); +R6 = A0 + A1, R5 = A0 - A1 (S); +R7 = A1 + A0, R3 = A1 - A0 (S); +R0 = A0 + A1, R2 = A0 - A1 (S); +R1 = A0 + A1, R0 = A0 - A1 (S); +R2 = A1 + A0, R1 = A1 - A0 (S); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x7FFFFFFF; +CHECKREG r2, 0xBC913448; +CHECKREG r3, 0x7FFFFFFF; +CHECKREG r4, 0x7FFFFFFF; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0xBC913448; +CHECKREG r7, 0xBC913448; + + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rrpmmp.s b/sim/testsuite/bfin/c_dsp32alu_rrpmmp.s new file mode 100644 index 0000000..6951a9f --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rrpmmp.s @@ -0,0 +1,263 @@ +//Original:/testcases/core/c_dsp32alu_rrpmmp/c_dsp32alu_rrpmmp.dsp +// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) amod0 +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x35678911; +imm32 r1, 0x2489ab1d; +imm32 r2, 0x34545515; +imm32 r3, 0x46667717; +imm32 r0, 0x5567891b; +imm32 r1, 0x67889b1d; +imm32 r2, 0x74445915; +imm32 r3, 0x86667797; +R0 = R0 +|- R0 , R7 = R0 -|+ R0; +R1 = R0 +|- R1 , R6 = R0 -|+ R1; +R2 = R0 +|- R2 , R5 = R0 -|+ R2; +R3 = R0 +|- R3 , R4 = R0 -|+ R3; +R4 = R0 +|- R4 , R3 = R0 -|+ R4; +R5 = R0 +|- R5 , R2 = R0 -|+ R5; +R6 = R0 +|- R6 , R1 = R0 -|+ R6; +R7 = R0 +|- R7 , R0 = R0 -|+ R7; +CHECKREG r0, 0xAACE1236; +CHECKREG r1, 0x67889B1D; +CHECKREG r2, 0x74445915; +CHECKREG r3, 0x86667797; +CHECKREG r4, 0xCF368869; +CHECKREG r5, 0xE158A6EB; +CHECKREG r6, 0xEE1464E3; +CHECKREG r7, 0xAACEEDCA; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34e45515; +imm32 r3, 0x466e7717; +imm32 r0, 0x5567ee1b; +imm32 r1, 0x6789abed; +imm32 r2, 0x7444551e; +imm32 r3, 0x86e67777; +R0 = R1 +|- R0 , R7 = R1 -|+ R0; +R1 = R1 +|- R1 , R6 = R1 -|+ R1; +R2 = R1 +|- R2 , R5 = R1 -|+ R2; +R3 = R1 +|- R3 , R4 = R1 -|+ R3; +R4 = R1 +|- R4 , R3 = R1 -|+ R4; +R5 = R1 +|- R5 , R2 = R1 -|+ R5; +R6 = R1 +|- R6 , R1 = R1 -|+ R6; +R7 = R1 +|- R7 , R0 = R1 -|+ R7; +CHECKREG r0, 0xBCF0F1E2; +CHECKREG r1, 0xCF1257DA; +CHECKREG r2, 0x7444551E; +CHECKREG r3, 0x86E67777; +CHECKREG r4, 0x173E8889; +CHECKREG r5, 0x29E0AAE2; +CHECKREG r6, 0xCF12A826; +CHECKREG r7, 0xE134BDD2; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r0, 0x5567891b; +imm32 r1, 0x6789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0x86667777; +R0 = R2 +|- R0 , R7 = R2 -|+ R0; +R1 = R2 +|- R1 , R6 = R2 -|+ R1; +R2 = R2 +|- R2 , R5 = R2 -|+ R2; +R3 = R2 +|- R3 , R4 = R2 -|+ R3; +R4 = R2 +|- R4 , R3 = R2 -|+ R4; +R5 = R2 +|- R5 , R2 = R2 -|+ R5; +R6 = R2 +|- R6 , R1 = R2 -|+ R6; +R7 = R2 +|- R7 , R0 = R2 -|+ R7; +CHECKREG r0, 0xC9AB885A; +CHECKREG r1, 0xDBCDAA5C; +CHECKREG r2, 0xE888AA2A; +CHECKREG r3, 0x86667777; +CHECKREG r4, 0x4AAA8889; +CHECKREG r5, 0xE88855D6; +CHECKREG r6, 0xF543A9F8; +CHECKREG r7, 0x0765CBFA; + +imm32 r0, 0x85678911; +imm32 r1, 0x2889ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r0, 0x5587891b; +imm32 r1, 0x6788ab1d; +imm32 r2, 0x74448515; +imm32 r3, 0x86667877; +R0 = R3 +|- R0 , R7 = R3 -|+ R0; +R1 = R3 +|- R1 , R6 = R3 -|+ R1; +R2 = R3 +|- R2 , R5 = R3 -|+ R2; +R3 = R3 +|- R3 , R4 = R3 -|+ R3; +R4 = R3 +|- R4 , R3 = R3 -|+ R4; +R5 = R3 +|- R5 , R2 = R3 -|+ R5; +R6 = R3 +|- R6 , R1 = R3 -|+ R6; +R7 = R3 +|- R7 , R0 = R3 -|+ R7; +CHECKREG r0, 0xDBEDF280; +CHECKREG r1, 0xEDEE1482; +CHECKREG r2, 0xFAAAEE7A; +CHECKREG r3, 0x0CCCF0EE; +CHECKREG r4, 0x0CCC0F12; +CHECKREG r5, 0x1EEEF362; +CHECKREG r6, 0x2BAACD5A; +CHECKREG r7, 0x3DABEF5C; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r0, 0x5567891b; +imm32 r1, 0x6789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0x86667777; +R0 = R4 +|- R0 , R7 = R4 -|+ R0; +R1 = R4 +|- R1 , R6 = R4 -|+ R1; +R2 = R4 +|- R2 , R5 = R4 -|+ R2; +R3 = R4 +|- R3 , R4 = R4 -|+ R3; +R4 = R4 +|- R4 , R3 = R4 -|+ R4; +R5 = R4 +|- R5 , R2 = R4 -|+ R5; +R6 = R4 +|- R6 , R1 = R4 -|+ R6; +R7 = R4 +|- R7 , R0 = R4 -|+ R7; +CHECKREG r0, 0x5567982D; +CHECKREG r1, 0x6789BA2F; +CHECKREG r2, 0x74446427; +CHECKREG r3, 0x00000D12; +CHECKREG r4, 0x0CCC0000; +CHECKREG r5, 0xA5549BD9; +CHECKREG r6, 0xB20F45D1; +CHECKREG r7, 0xC43167D3; + +imm32 r0, 0x95678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x39445515; +imm32 r3, 0x46967717; +imm32 r0, 0x5567891b; +imm32 r1, 0x6789ab1d; +imm32 r2, 0x74495515; +imm32 r3, 0x86669777; +R0 = R5 +|- R0 , R7 = R5 -|+ R0; +R1 = R5 +|- R1 , R6 = R5 -|+ R1; +R2 = R5 +|- R2 , R5 = R5 -|+ R2; +R3 = R5 +|- R3 , R4 = R5 -|+ R3; +R4 = R5 +|- R4 , R3 = R5 -|+ R4; +R5 = R5 +|- R5 , R2 = R5 -|+ R5; +R6 = R5 +|- R6 , R1 = R5 -|+ R6; +R7 = R5 +|- R7 , R0 = R5 -|+ R7; +CHECKREG r0, 0x122924F4; +CHECKREG r1, 0x244B46F6; +CHECKREG r2, 0x0000E1DC; +CHECKREG r3, 0x86667953; +CHECKREG r4, 0xDBB06889; +CHECKREG r5, 0x62160000; +CHECKREG r6, 0x9FE1B90A; +CHECKREG r7, 0xB203DB0C; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r0, 0x5567891b; +imm32 r1, 0x6789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0x86667777; +R0 = R6 +|- R0 , R7 = R6 -|+ R0; +R1 = R6 +|- R1 , R6 = R6 -|+ R1; +R2 = R6 +|- R2 , R5 = R6 -|+ R2; +R3 = R6 +|- R3 , R4 = R6 -|+ R3; +R4 = R6 +|- R4 , R3 = R6 -|+ R4; +R5 = R6 +|- R5 , R2 = R6 -|+ R5; +R6 = R6 +|- R6 , R1 = R6 -|+ R6; +R7 = R6 +|- R7 , R0 = R6 -|+ R7; +CHECKREG r0, 0x26364225; +CHECKREG r1, 0x0000C84E; +CHECKREG r2, 0x74441D63; +CHECKREG r3, 0x86663FC5; +CHECKREG r4, 0xEA4A8889; +CHECKREG r5, 0xFC6CAAEB; +CHECKREG r6, 0x70B00000; +CHECKREG r7, 0xBB2ABDDB; + +imm32 r0, 0x67898911; +imm32 r1, 0xb789ab1d; +imm32 r2, 0x3b445515; +imm32 r3, 0x46b67717; +imm32 r0, 0x5567891b; +imm32 r1, 0x678bab1d; +imm32 r2, 0x7444b515; +imm32 r3, 0x86667b77; +R0 = R7 +|- R0 , R7 = R7 -|+ R0; +R1 = R7 +|- R1 , R6 = R7 -|+ R1; +R2 = R7 +|- R2 , R5 = R7 -|+ R2; +R3 = R7 +|- R3 , R4 = R7 -|+ R3; +R4 = R7 +|- R4 , R3 = R7 -|+ R4; +R5 = R7 +|- R5 , R2 = R7 -|+ R5; +R6 = R7 +|- R6 , R1 = R7 -|+ R6; +R7 = R7 +|- R7 , R0 = R7 -|+ R7; +CHECKREG r0, 0x00008DEC; +CHECKREG r1, 0x678B3909; +CHECKREG r2, 0x74444301; +CHECKREG r3, 0x86660963; +CHECKREG r4, 0x45208489; +CHECKREG r5, 0x57424AEB; +CHECKREG r6, 0x63FB54E3; +CHECKREG r7, 0xCB860000; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34ee5515; +imm32 r3, 0x4666e717; +imm32 r0, 0x5567891b; +imm32 r1, 0x6789ae1d; +imm32 r2, 0x744455e5; +imm32 r3, 0x8666777e; +R4 = R2 +|- R5 , R3 = R2 -|+ R5 (S); +R0 = R5 +|- R3 , R5 = R5 -|+ R3 (CO); +R2 = R6 +|- R2 , R0 = R6 -|+ R2 (SCO); +R3 = R4 +|- R0 , R2 = R4 -|+ R0 (S); +R7 = R7 +|- R6 , R6 = R7 -|+ R6 (CO); +R6 = R1 +|- R7 , R1 = R1 -|+ R7 (SCO); +R5 = R0 +|- R4 , R7 = R0 -|+ R4 (S); +R1 = R3 +|- R1 , R4 = R3 -|+ R1 (CO); +CHECKREG r0, 0x7FFFEFB7; +CHECKREG r1, 0xFFFFE33B; +CHECKREG r2, 0x0000FAB1; +CHECKREG r3, 0x7FFF1B43; +CHECKREG r4, 0x534BFFFF; +CHECKREG r5, 0x7FFFE4BD; +CHECKREG r6, 0x7FFF0300; +CHECKREG r7, 0x0000FAB1; + +imm32 r0, 0xff678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3f445515; +imm32 r3, 0x46f67717; +imm32 r0, 0x556f891b; +imm32 r1, 0x6789fb1d; +imm32 r2, 0x74445f15; +imm32 r3, 0x866677f7; +R4 = R3 +|- R3 , R5 = R3 -|+ R3 (SCO); +R1 = R6 +|- R1 , R6 = R6 -|+ R1 (SCO); +R6 = R1 +|- R4 , R4 = R1 -|+ R4 (S); +R7 = R4 +|- R2 , R0 = R4 -|+ R2 (S); +R2 = R2 +|- R6 , R1 = R2 -|+ R6 (CO); +R3 = R5 +|- R5 , R7 = R5 -|+ R5 (CO); +R5 = R7 +|- R7 , R3 = R7 -|+ R7 (SCO); +R0 = R0 +|- R0 , R2 = R0 -|+ R0 (SCO); +CHECKREG r0, 0x17760000; +CHECKREG r1, 0x66F87445; +CHECKREG r2, 0x7FFF0000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x7FFF07E3; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xFFFF07E3; +CHECKREG r7, 0x00000000; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rrpmmp_sft.s b/sim/testsuite/bfin/c_dsp32alu_rrpmmp_sft.s new file mode 100644 index 0000000..bd48482 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rrpmmp_sft.s @@ -0,0 +1,262 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft/c_dsp32alu_rrpmmp_sft.dsp +// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, << +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + + imm32 r0, 0x35678911; + imm32 r1, 0x2489ab1d; + imm32 r2, 0x34545515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x67889b1d; + imm32 r2, 0x74445915; + imm32 r3, 0x86667797; + R0 = R0 +|- R0 , R7 = R0 -|+ R0 (ASR); + R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); + R2 = R0 +|- R2 , R5 = R0 -|+ R2 (ASR); + R3 = R0 +|- R3 , R4 = R0 -|+ R3 (ASR); + R4 = R0 +|- R4 , R3 = R0 -|+ R4 (ASR); + R5 = R0 +|- R5 , R2 = R0 -|+ R5 (ASR); + R6 = R0 +|- R6 , R1 = R0 -|+ R6 (ASR); + R7 = R0 +|- R7 , R0 = R0 -|+ R7 (ASR); + CHECKREG r0, 0x2AB3c48D; + CHECKREG r1, 0x2F3CE6C7; + CHECKREG r2, 0x326B1645; + CHECKREG r3, 0xf6F31DE5; + CHECKREG r4, 0x5E73E21A; + CHECKREG r5, 0x22FCE9BB; + CHECKREG r6, 0x262B1939; + CHECKREG r7, 0x2AB33B72; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2e89ab1d; + imm32 r2, 0x34e45515; + imm32 r3, 0x466e7717; + imm32 r0, 0x5567ee1b; + imm32 r1, 0x6789abed; + imm32 r2, 0x7444551e; + imm32 r3, 0x86e67777; + R0 = R1 +|- R0 , R7 = R1 -|+ R0 (ASR); + R1 = R1 +|- R1 , R6 = R1 -|+ R1 (ASR); + R2 = R1 +|- R2 , R5 = R1 -|+ R2 (ASR); + R3 = R1 +|- R3 , R4 = R1 -|+ R3 (ASR); + R4 = R1 +|- R4 , R3 = R1 -|+ R4 (ASR); + R5 = R1 +|- R5 , R2 = R1 -|+ R5 (ASR); + R6 = R1 +|- R6 , R1 = R1 -|+ R6 (ASR); + R7 = R1 +|- R7 , R0 = R1 -|+ R7 (ASR); + CHECKREG r0, 0x1559d17D; + CHECKREG r1, 0x33C4d5F6; + CHECKREG r2, 0x36F31547; + CHECKREG r3, 0xfB9C1DDD; + CHECKREG r4, 0x6BEDE222; + CHECKREG r5, 0x3095eAB8; + CHECKREG r6, 0x33C42A09; + CHECKREG r7, 0x1E6A0479; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74445515; + imm32 r3, 0x86667777; + R0 = R2 +|- R0 , R7 = R2 -|+ R0 (ASR); + R1 = R2 +|- R1 , R6 = R2 -|+ R1 (ASR); + R2 = R2 +|- R2 , R5 = R2 -|+ R2 (ASR); + R3 = R2 +|- R3 , R4 = R2 -|+ R3 (ASR); + R4 = R2 +|- R4 , R3 = R2 -|+ R4 (ASR); + R5 = R2 +|- R5 , R2 = R2 -|+ R5 (ASR); + R6 = R2 +|- R6 , R1 = R2 -|+ R6 (ASR); + R7 = R2 +|- R7 , R0 = R2 -|+ R7 (ASR); + CHECKREG r0, 0x155A0CD1; + CHECKREG r1, 0x19E21551; + CHECKREG r2, 0x3A222A8A; + CHECKREG r3, 0xfEAA1DDD; + CHECKREG r4, 0x7599e222; + CHECKREG r5, 0x3A22d575; + CHECKREG r6, 0x203F1538; + CHECKREG r7, 0x24C81DB9; + + imm32 r0, 0x85678911; + imm32 r1, 0x2889ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5587891b; + imm32 r1, 0x6788ab1d; + imm32 r2, 0x74448515; + imm32 r3, 0x86667877; + R0 = R3 +|- R0 , R7 = R3 -|+ R0 (ASR); + R1 = R3 +|- R1 , R6 = R3 -|+ R1 (ASR); + R2 = R3 +|- R2 , R5 = R3 -|+ R2 (ASR); + R3 = R3 +|- R3 , R4 = R3 -|+ R3 (ASR); + R4 = R3 +|- R4 , R3 = R3 -|+ R4 (ASR); + R5 = R3 +|- R5 , R2 = R3 -|+ R5 (ASR); + R6 = R3 +|- R6 , R1 = R3 -|+ R6 (ASR); + R7 = R3 +|- R7 , R0 = R3 -|+ R7 (ASR); + CHECKREG r0, 0x15621E82; + CHECKREG r1, 0x19E22702; + CHECKREG r2, 0x1D111D80; + CHECKREG r3, 0xc3333C3B; + CHECKREG r4, 0xc333c3C4; + CHECKREG r5, 0xa6221EBA; + CHECKREG r6, 0xa9511538; + CHECKREG r7, 0xaDD11DB9; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74445515; + imm32 r3, 0x86667777; + R0 = R4 +|- R0 , R7 = R4 -|+ R0 (ASR); + R1 = R4 +|- R1 , R6 = R4 -|+ R1 (ASR); + R2 = R4 +|- R2 , R5 = R4 -|+ R2 (ASR); + R3 = R4 +|- R3 , R4 = R4 -|+ R3 (ASR); + R4 = R4 +|- R4 , R3 = R4 -|+ R4 (ASR); + R5 = R4 +|- R5 , R2 = R4 -|+ R5 (ASR); + R6 = R4 +|- R6 , R1 = R4 -|+ R6 (ASR); + R7 = R4 +|- R7 , R0 = R4 -|+ R7 (ASR); + CHECKREG r0, 0x33C0d337; + CHECKREG r1, 0x3848dBB8; + CHECKREG r2, 0x3B770636; + CHECKREG r3, 0x00001D9D; + CHECKREG r4, 0x1E660000; + CHECKREG r5, 0xe2EEf9CA; + CHECKREG r6, 0xe61D2448; + CHECKREG r7, 0xeAA62CC8; + + imm32 r0, 0x95678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x39445515; + imm32 r3, 0x46967717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74495515; + imm32 r3, 0x86669777; + R0 = R5 +|- R0 , R7 = R5 -|+ R0 (ASR); + R1 = R5 +|- R1 , R6 = R5 -|+ R1 (ASL); + R2 = R5 +|- R2 , R5 = R5 -|+ R2 (ASR); + R3 = R5 +|- R3 , R4 = R5 -|+ R3 (ASL); + R4 = R5 +|- R4 , R3 = R5 -|+ R4 (ASR); + R5 = R5 +|- R5 , R2 = R5 -|+ R5 (ASR); + R6 = R5 +|- R6 , R1 = R5 -|+ R6 (ASR); + R7 = R5 +|- R7 , R0 = R5 -|+ R7 (ASL); + CHECKREG r0, 0xE11E82E4; + CHECKREG r1, 0xe04424E7; + CHECKREG r2, 0x0000276F; + CHECKREG r3, 0xaaBD529D; + CHECKREG r4, 0x0c95D4D1; + CHECKREG r5, 0xb7520000; + CHECKREG r6, 0xd70EdB19; + CHECKREG r7, 0xfC2A7D1C; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74445515; + imm32 r3, 0x86667777; + R0 = R6 +|- R0 , R7 = R6 -|+ R0 (ASR); + R1 = R6 +|- R1 , R6 = R6 -|+ R1 (ASL); + R2 = R6 +|- R2 , R5 = R6 -|+ R2 (ASL); + R3 = R6 +|- R3 , R4 = R6 -|+ R3 (ASR); + R4 = R6 +|- R4 , R3 = R6 -|+ R4 (ASR); + R5 = R6 +|- R5 , R2 = R6 -|+ R5 (ASR); + R6 = R6 +|- R6 , R1 = R6 -|+ R6 (ASL); + R7 = R6 +|- R7 , R0 = R6 -|+ R7 (ASR); + CHECKREG r0, 0x5dAAd90D; + CHECKREG r1, 0x000031B0; + CHECKREG r2, 0x04BFe7B7; + CHECKREG r3, 0xd95C272E; + CHECKREG r4, 0x05AEe53D; + CHECKREG r5, 0xDa4B24B5; + CHECKREG r6, 0x7C280000; + CHECKREG r7, 0x1e7D26F3; + + imm32 r0, 0x67898911; + imm32 r1, 0xb789ab1d; + imm32 r2, 0x3b445515; + imm32 r3, 0x46b67717; + imm32 r0, 0x5567891b; + imm32 r1, 0x678bab1d; + imm32 r2, 0x7444b515; + imm32 r3, 0x86667b77; + R0 = R7 +|- R0 , R7 = R7 -|+ R0 (ASR); + R1 = R7 +|- R1 , R6 = R7 -|+ R1 (ASR); + R2 = R7 +|- R2 , R5 = R7 -|+ R2 (ASL); + R3 = R7 +|- R3 , R4 = R7 -|+ R3 (ASR); + R4 = R7 +|- R4 , R3 = R7 -|+ R4 (ASL); + R5 = R7 +|- R5 , R2 = R7 -|+ R5 (ASL); + R6 = R7 +|- R6 , R1 = R7 -|+ R6 (ASL); + R7 = R7 +|- R7 , R0 = R7 -|+ R7 (ASR); + CHECKREG r0, 0x0000d807; + CHECKREG r1, 0x4c163332; + CHECKREG r2, 0x07FAe47E; + CHECKREG r3, 0x6aF2038C; + CHECKREG r4, 0x273A5c90; + CHECKREG r5, 0x8a327b9E; + CHECKREG r6, 0x46162cEA; + CHECKREG r7, 0xe48B0000; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2e89ab1d; + imm32 r2, 0x34ee5515; + imm32 r3, 0x4666e717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ae1d; + imm32 r2, 0x744455e5; + imm32 r3, 0x8666777e; + R4 = R2 +|- R5 , R3 = R2 -|+ R5 (ASR); + R0 = R5 +|- R3 , R5 = R5 -|+ R3 (ASL); + R2 = R6 +|- R2 , R0 = R6 -|+ R2 (ASR); + R3 = R4 +|- R0 , R2 = R4 -|+ R0 (ASR); + R7 = R7 +|- R6 , R6 = R7 -|+ R6 (ASR); + R6 = R1 +|- R7 , R1 = R1 -|+ R7 (ASL); + R5 = R0 +|- R4 , R7 = R0 -|+ R4 (ASR); + R1 = R3 +|- R1 , R4 = R3 -|+ R1 (ASL); + CHECKREG r0, 0xE8e94167; + CHECKREG r1, 0x31084d1C; + CHECKREG r2, 0x0b291745; + CHECKREG r3, 0xF412d5de; + CHECKREG r4, 0x9f400a5C; + CHECKREG r5, 0xF4122a22; + CHECKREG r6, 0xf9B28924; + CHECKREG r7, 0xF4D71745; + + imm32 r0, 0xff678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x3f445515; + imm32 r3, 0x46f67717; + imm32 r0, 0x556f891b; + imm32 r1, 0x6789fb1d; + imm32 r2, 0x74445f15; + imm32 r3, 0x866677f7; + R4 = R3 +|- R3 , R5 = R3 -|+ R3 (ASR); + R1 = R6 +|- R1 , R6 = R6 -|+ R1 (ASL); + R6 = R1 +|- R4 , R4 = R1 -|+ R4 (ASR); + R7 = R4 +|- R2 , R0 = R4 -|+ R2 (ASL); + R2 = R2 +|- R6 , R1 = R2 -|+ R6 (ASR); + R3 = R5 +|- R5 , R7 = R5 -|+ R5 (ASL); + R5 = R7 +|- R7 , R3 = R7 -|+ R7 (ASR); + R0 = R0 +|- R0 , R2 = R0 -|+ R0 (ASR); + CHECKREG r0, 0x53880000; + CHECKREG r1, 0x67eb368e; + CHECKREG r2, 0x0000da38; + CHECKREG r3, 0x0000dfdc; + CHECKREG r4, 0x1e080e07; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0xa46e0e07; + CHECKREG r7, 0x0000dfdc; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rrpmmp_sft_x.s b/sim/testsuite/bfin/c_dsp32alu_rrpmmp_sft_x.s new file mode 100644 index 0000000..f8711a5 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rrpmmp_sft_x.s @@ -0,0 +1,261 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft_x/c_dsp32alu_rrpmmp_sft_x.dsp +// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, << +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x35678911; + imm32 r1, 0x2489ab1d; + imm32 r2, 0x34545515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x67889b1d; + imm32 r2, 0x74445915; + imm32 r3, 0x86667797; + R0 = R0 +|- R0 , R7 = R0 -|+ R0 (CO , ASR); + R1 = R0 +|- R1 , R6 = R0 -|+ R1 (CO , ASR); + R2 = R0 +|- R2 , R5 = R0 -|+ R2 (CO , ASR); + R3 = R0 +|- R3 , R4 = R0 -|+ R3 (CO , ASR); + R4 = R0 +|- R4 , R3 = R0 -|+ R4 (CO , ASR); + R5 = R0 +|- R5 , R2 = R0 -|+ R5 (CO , ASR); + R6 = R0 +|- R6 , R1 = R0 -|+ R6 (CO , ASR); + R7 = R0 +|- R7 , R0 = R0 -|+ R7 (CO , ASR); + CHECKREG r0, 0x00006626; + CHECKREG r1, 0xfb7743ec; + CHECKREG r2, 0xf848146e; + CHECKREG r3, 0x33c00cce; + CHECKREG r4, 0x4899cc40; + CHECKREG r5, 0x40f807b7; + CHECKREG r6, 0x117a0488; + CHECKREG r7, 0xef410000; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2e89ab1d; + imm32 r2, 0x34e45515; + imm32 r3, 0x466e7717; + imm32 r0, 0x5567ee1b; + imm32 r1, 0x6789abed; + imm32 r2, 0x7444551e; + imm32 r3, 0x86e67777; + R0 = R1 +|- R0 , R7 = R1 -|+ R0 (CO , ASR); + R1 = R1 +|- R1 , R6 = R1 -|+ R1 (CO , ASR); + R2 = R1 +|- R2 , R5 = R1 -|+ R2 (CO , ASR); + R3 = R1 +|- R3 , R4 = R1 -|+ R3 (CO , ASR); + R4 = R1 +|- R4 , R3 = R1 -|+ R4 (CO , ASR); + R5 = R1 +|- R5 , R2 = R1 -|+ R5 (CO , ASR); + R6 = R1 +|- R6 , R1 = R1 -|+ R6 (CO , ASR); + R7 = R1 +|- R7 , R0 = R1 -|+ R7 (CO , ASR); + CHECKREG r0, 0x336f197e; + CHECKREG r1, 0x00005dce; + CHECKREG r2, 0xfcd11e7d; + CHECKREG r3, 0x382815e7; + CHECKREG r4, 0x51a2c7d7; + CHECKREG r5, 0x490c032f; + CHECKREG r6, 0x09bb0000; + CHECKREG r7, 0xe6822a5e; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74445515; + imm32 r3, 0x86667777; + R0 = R2 +|- R0 , R7 = R2 -|+ R0 (CO , ASR); + R1 = R2 +|- R1 , R6 = R2 -|+ R1 (CO , ASR); + R2 = R2 +|- R2 , R5 = R2 -|+ R2 (CO , ASR); + R3 = R2 +|- R3 , R4 = R2 -|+ R3 (CO , ASR); + R4 = R2 +|- R4 , R3 = R2 -|+ R4 (CO , ASR); + R5 = R2 +|- R5 , R2 = R2 -|+ R5 (CO , ASR); + R6 = R2 +|- R6 , R1 = R2 -|+ R6 (CO , ASR); + R7 = R2 +|- R7 , R0 = R2 -|+ R7 (CO , ASR); + CHECKREG r0, 0x0f820874; + CHECKREG r1, 0x0afafff3; + CHECKREG r2, 0x00000f97; + CHECKREG r3, 0x3b771c44; + CHECKREG r4, 0x57ffc488; + CHECKREG r5, 0x64ac0000; + CHECKREG r6, 0x000c049d; + CHECKREG r7, 0xf78c0014; + + imm32 r0, 0x85678911; + imm32 r1, 0x2889ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5587891b; + imm32 r1, 0x6788ab1d; + imm32 r2, 0x74448515; + imm32 r3, 0x86667877; + R0 = R3 +|- R0 , R7 = R3 -|+ R0 (CO , ASR); + R1 = R3 +|- R1 , R6 = R3 -|+ R1 (CO , ASR); + R2 = R3 +|- R2 , R5 = R3 -|+ R2 (CO , ASR); + R3 = R3 +|- R3 , R4 = R3 -|+ R3 (CO , ASR); + R4 = R3 +|- R4 , R3 = R3 -|+ R4 (CO , ASR); + R5 = R3 +|- R5 , R2 = R3 -|+ R5 (CO , ASR); + R6 = R3 +|- R6 , R1 = R3 -|+ R6 (CO , ASR); + R7 = R3 +|- R7 , R0 = R3 -|+ R7 (CO , ASR); + CHECKREG r0, 0x8fb3ff9b; + CHECKREG r1, 0x8b33f71b; + CHECKREG r2, 0x8804009d; + CHECKREG r3, 0x000086f7; + CHECKREG r4, 0xff6e0000; + CHECKREG r5, 0xff63fef3; + CHECKREG r6, 0x08e5fbc4; + CHECKREG r7, 0x0064f744; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74445515; + imm32 r3, 0x86667777; + R0 = R4 +|- R0 , R7 = R4 -|+ R0 (CO , ASR); + R1 = R4 +|- R1 , R6 = R4 -|+ R1 (CO , ASR); + R2 = R4 +|- R2 , R5 = R4 -|+ R2 (CO , ASR); + R3 = R4 +|- R3 , R4 = R4 -|+ R3 (CO , ASR); + R4 = R4 +|- R4 , R3 = R4 -|+ R4 (CO , ASR); + R5 = R4 +|- R5 , R2 = R4 -|+ R5 (CO , ASR); + R6 = R4 +|- R6 , R1 = R4 -|+ R6 (CO , ASR); + R7 = R4 +|- R7 , R0 = R4 -|+ R7 (CO , ASR); + CHECKREG r0, 0xEA813B97; + CHECKREG r1, 0xE5F93316; + CHECKREG r2, 0xe2ca0898; + CHECKREG r3, 0x3C840000; + CHECKREG r4, 0x3BBB0000; + CHECKREG r5, 0x33221D35; + CHECKREG r6, 0x08A41A07; + CHECKREG r7, 0x0024157E; + + imm32 r0, 0x95678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x39445515; + imm32 r3, 0x46967717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74495515; + imm32 r3, 0x86669777; + R0 = R5 +|- R0 , R7 = R5 -|+ R0 (CO , ASR); + R1 = R5 +|- R1 , R6 = R5 -|+ R1 (CO , ASL); + R2 = R5 +|- R2 , R5 = R5 -|+ R2 (CO , ASR); + R3 = R5 +|- R3 , R4 = R5 -|+ R3 (CO , ASL); + R4 = R5 +|- R4 , R3 = R5 -|+ R4 (CO , ASR); + R5 = R5 +|- R5 , R2 = R5 -|+ R5 (CO , ASR); + R6 = R5 +|- R6 , R1 = R5 -|+ R6 (CO , ASR); + R7 = R5 +|- R7 , R0 = R5 -|+ R7 (CO , ASL); + CHECKREG r0, 0xDDBACBFA; + CHECKREG r1, 0xCB995440; + CHECKREG r2, 0xDF6C0000; + CHECKREG r3, 0x227525AF; + CHECKREG r4, 0x1375bCF7; + CHECKREG r5, 0x39250000; + CHECKREG r6, 0xE4E43467; + CHECKREG r7, 0x189A2246; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74445515; + imm32 r3, 0x86667777; + R0 = R6 +|- R0 , R7 = R6 -|+ R0 (CO , ASR); + R1 = R6 +|- R1 , R6 = R6 -|+ R1 (CO , ASL); + R2 = R6 +|- R2 , R5 = R6 -|+ R2 (CO , ASL); + R3 = R6 +|- R3 , R4 = R6 -|+ R3 (CO , ASR); + R4 = R6 +|- R4 , R3 = R6 -|+ R4 (CO , ASR); + R5 = R6 +|- R5 , R2 = R6 -|+ R5 (CO , ASR); + R6 = R6 +|- R6 , R1 = R6 -|+ R6 (CO , ASL); + R7 = R6 +|- R7 , R0 = R6 -|+ R7 (CO , ASR); + CHECKREG r0, 0xE3DF0EAF; + CHECKREG r1, 0xEAD80000; + CHECKREG r2, 0xC81F0FB9; + CHECKREG r3, 0x0B83C2F9; + CHECKREG r4, 0xFC0FEF32; + CHECKREG r5, 0xaF4F3297; + CHECKREG r6, 0xFC200000; + CHECKREG r7, 0xED701C21; + + imm32 r0, 0x67898911; + imm32 r1, 0xb789ab1d; + imm32 r2, 0x3b445515; + imm32 r3, 0x46b67717; + imm32 r0, 0x5567891b; + imm32 r1, 0x678bab1d; + imm32 r2, 0x7444b515; + imm32 r3, 0x86667b77; + R0 = R7 +|- R0 , R7 = R7 -|+ R0 (CO , ASR); + R1 = R7 +|- R1 , R6 = R7 -|+ R1 (CO , ASR); + R2 = R7 +|- R2 , R5 = R7 -|+ R2 (CO , ASL); + R3 = R7 +|- R3 , R4 = R7 -|+ R3 (CO , ASR); + R4 = R7 +|- R4 , R3 = R7 -|+ R4 (CO , ASL); + R5 = R7 +|- R5 , R2 = R7 -|+ R5 (CO , ASL); + R6 = R7 +|- R6 , R1 = R7 -|+ R6 (CO , ASL); + R7 = R7 +|- R7 , R0 = R7 -|+ R7 (CO , ASR); + CHECKREG r0, 0xCC040000; + CHECKREG r1, 0x031A2E1C; + CHECKREG r2, 0x1170A0D8; + CHECKREG r3, 0xE4405DC2; + CHECKREG r4, 0xECB64BD0; + CHECKREG r5, 0xA9A01EA0; + CHECKREG r6, 0x1C5C2CF6; + CHECKREG r7, 0xD29E0000; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2e89ab1d; + imm32 r2, 0x34ee5515; + imm32 r3, 0x4666e717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ae1d; + imm32 r2, 0x744455e5; + imm32 r3, 0x8666777e; + R4 = R2 +|- R5 , R3 = R2 -|+ R5 (CO , ASR); + R0 = R5 +|- R3 , R5 = R5 -|+ R3 (CO , ASL); + R2 = R6 +|- R2 , R0 = R6 -|+ R2 (CO , ASR); + R3 = R4 +|- R0 , R2 = R4 -|+ R0 (CO , ASR); + R7 = R7 +|- R6 , R6 = R7 -|+ R6 (CO , ASR); + R6 = R1 +|- R7 , R1 = R1 -|+ R7 (CO , ASL); + R5 = R0 +|- R4 , R7 = R0 -|+ R4 (CO , ASR); + R1 = R3 +|- R1 , R4 = R3 -|+ R1 (CO , ASL); + CHECKREG r0, 0x416dd40c; + CHECKREG r1, 0xaEE68766; + CHECKREG r2, 0xF7D7e6C2; + CHECKREG r3, 0x282F23CB; + CHECKREG r4, 0x07C6f1D6; + CHECKREG r5, 0x282FDC35; + CHECKREG r6, 0xBE0C8930; + CHECKREG r7, 0xF7D7193D; + + imm32 r0, 0xff678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x3f445515; + imm32 r3, 0x46f67717; + imm32 r0, 0x556f891b; + imm32 r1, 0x6789fb1d; + imm32 r2, 0x74445f15; + imm32 r3, 0x866677f7; + R4 = R3 +|- R3 , R5 = R3 -|+ R3 (CO , ASR); + R1 = R6 +|- R1 , R6 = R6 -|+ R1 (CO , ASL); + R6 = R1 +|- R4 , R4 = R1 -|+ R4 (CO , ASR); + R7 = R4 +|- R2 , R0 = R4 -|+ R2 (CO , ASL); + R2 = R2 +|- R6 , R1 = R2 -|+ R6 (CO , ASR); + R3 = R5 +|- R5 , R7 = R5 -|+ R5 (CO , ASL); + R5 = R7 +|- R7 , R3 = R7 -|+ R7 (CO , ASR); + R0 = R0 +|- R0 , R2 = R0 -|+ R0 (CO , ASR); + CHECKREG r0, 0x82EE0000; + CHECKREG r1, 0x369445BE; + CHECKREG r2, 0x339E0000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x0E136262; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0xe8C80E13; + CHECKREG r7, 0x00000000; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rrppmm.s b/sim/testsuite/bfin/c_dsp32alu_rrppmm.s new file mode 100644 index 0000000..3d62e56 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rrppmm.s @@ -0,0 +1,263 @@ +//Original:/testcases/core/c_dsp32alu_rrppmm/c_dsp32alu_rrppmm.dsp +// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) amod0 +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x95679911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34945515; +imm32 r3, 0x46967717; +imm32 r4, 0x5597891b; +imm32 r5, 0x6989ab1d; +imm32 r6, 0x94445515; +imm32 r7, 0x96667777; +R0 = R0 +|+ R0, R7 = R0 -|- R0; +R1 = R0 +|+ R1, R6 = R0 -|- R1; +R2 = R0 +|+ R2, R5 = R0 -|- R2; +R3 = R0 +|+ R3, R4 = R0 -|- R3; +R4 = R0 +|+ R4, R3 = R0 -|- R4; +R5 = R0 +|+ R5, R2 = R0 -|- R5; +R6 = R0 +|+ R6, R1 = R0 -|- R6; +R7 = R0 +|+ R7, R0 = R0 -|- R7; +CHECKREG r0, 0x2ACE3222; +CHECKREG r1, 0x2789AB1D; +CHECKREG r2, 0x34945515; +CHECKREG r3, 0x46967717; +CHECKREG r4, 0x0F06ED2D; +CHECKREG r5, 0x21080F2F; +CHECKREG r6, 0x2E13B927; +CHECKREG r7, 0x2ACE3222; + +imm32 r0, 0x11678911; +imm32 r1, 0xa719ab1d; +imm32 r2, 0x3a415515; +imm32 r3, 0x46a67717; +imm32 r4, 0x556a891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445a15; +imm32 r7, 0x866677a7; +R0 = R1 +|+ R0, R7 = R1 -|- R0; +R1 = R1 +|+ R1, R6 = R1 -|- R1; +R2 = R1 +|+ R2, R5 = R1 -|- R2; +R3 = R1 +|+ R3, R4 = R1 -|- R3; +R4 = R1 +|+ R4, R3 = R1 -|- R4; +R5 = R1 +|+ R5, R2 = R1 -|- R5; +R6 = R1 +|+ R6, R1 = R1 -|- R6; +R7 = R1 +|+ R7, R0 = R1 -|- R7; +CHECKREG r0, 0xB880342E; +CHECKREG r1, 0x4E32563A; +CHECKREG r2, 0x3A415515; +CHECKREG r3, 0x46A67717; +CHECKREG r4, 0x55BE355D; +CHECKREG r5, 0x6223575F; +CHECKREG r6, 0x4E32563A; +CHECKREG r7, 0xE3E47846; + +imm32 r0, 0xb567891b; +imm32 r1, 0x2b89abbd; +imm32 r2, 0x34b45b15; +imm32 r3, 0x466bb717; +imm32 r4, 0x556bb91b; +imm32 r5, 0x67b9ab1d; +imm32 r6, 0x7b4455b5; +imm32 r7, 0xb666777b; +R0 = R2 +|+ R0, R7 = R2 -|- R0; +R1 = R2 +|+ R1, R6 = R2 -|- R1; +R2 = R2 +|+ R2, R5 = R2 -|- R2; +R3 = R2 +|+ R3, R4 = R2 -|- R3; +R4 = R2 +|+ R4, R3 = R2 -|- R4; +R5 = R2 +|+ R5, R2 = R2 -|- R5; +R6 = R2 +|+ R6, R1 = R2 -|- R6; +R7 = R2 +|+ R7, R0 = R2 -|- R7; +CHECKREG r0, 0xEA1BE430; +CHECKREG r1, 0x603D06D2; +CHECKREG r2, 0x6968B62A; +CHECKREG r3, 0x466BB717; +CHECKREG r4, 0x8C65B53D; +CHECKREG r5, 0x6968B62A; +CHECKREG r6, 0x72936582; +CHECKREG r7, 0xE8B58824; + +imm32 r0, 0xbc678c11; +imm32 r1, 0x27c9cb1d; +imm32 r2, 0x344c5515; +imm32 r3, 0x46c6c717; +imm32 r4, 0x55678c1b; +imm32 r5, 0x6c89abcd; +imm32 r6, 0x7444551c; +imm32 r7, 0x8c667777; +R0 = R3 +|+ R0, R7 = R3 -|- R0; +R1 = R3 +|+ R1, R6 = R3 -|- R1; +R2 = R3 +|+ R2, R5 = R3 -|- R2; +R3 = R3 +|+ R3, R4 = R3 -|- R3; +R4 = R3 +|+ R4, R3 = R3 -|- R4; +R5 = R3 +|+ R5, R2 = R3 -|- R5; +R6 = R3 +|+ R6, R1 = R3 -|- R6; +R7 = R3 +|+ R7, R0 = R3 -|- R7; +CHECKREG r0, 0x032D5328; +CHECKREG r1, 0x6E8F9234; +CHECKREG r2, 0x7B121C2C; +CHECKREG r3, 0x8D8C8E2E; +CHECKREG r4, 0x8D8C8E2E; +CHECKREG r5, 0xA0060030; +CHECKREG r6, 0xAC898A28; +CHECKREG r7, 0x17EBC934; + +imm32 r0, 0xd56789d1; +imm32 r1, 0x2d89abdd; +imm32 r2, 0x34d455d5; +imm32 r3, 0x4d667717; +imm32 r4, 0x5dd7891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0xd44d5515; +imm32 r7, 0xd666d777; +R0 = R4 +|+ R0, R7 = R4 -|- R0; +R1 = R4 +|+ R1, R6 = R4 -|- R1; +R2 = R4 +|+ R2, R5 = R4 -|- R2; +R3 = R4 +|+ R3, R4 = R4 -|- R3; +R4 = R4 +|+ R4, R3 = R4 -|- R4; +R5 = R4 +|+ R5, R2 = R4 -|- R5; +R6 = R4 +|+ R6, R1 = R4 -|- R6; +R7 = R4 +|+ R7, R0 = R4 -|- R7; +CHECKREG r0, 0x987224BE; +CHECKREG r1, 0xF09446CA; +CHECKREG r2, 0xF7DFF0C2; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x20E22408; +CHECKREG r5, 0x49E5574E; +CHECKREG r6, 0x51300146; +CHECKREG r7, 0xA9522352; + +imm32 r0, 0xc567a911; +imm32 r1, 0x278aab1d; +imm32 r2, 0x3c445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x55c7891b; +imm32 r5, 0x6a8cab1d; +imm32 r6, 0x7444c515; +imm32 r7, 0xa6667c77; +R0 = R5 +|+ R0, R7 = R5 -|- R0; +R1 = R5 +|+ R1, R6 = R5 -|- R1; +R2 = R5 +|+ R2, R5 = R5 -|- R2; +R3 = R5 +|+ R3, R4 = R5 -|- R3; +R4 = R5 +|+ R4, R3 = R5 -|- R4; +R5 = R5 +|+ R5, R2 = R5 -|- R5; +R6 = R5 +|+ R6, R1 = R5 -|- R6; +R7 = R5 +|+ R7, R0 = R5 -|- R7; +CHECKREG r0, 0xB76BAA04; +CHECKREG r1, 0x198EAC10; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x46A67717; +CHECKREG r4, 0x15EA34F9; +CHECKREG r5, 0x5C90AC10; +CHECKREG r6, 0x9F92AC10; +CHECKREG r7, 0x01B5AE1C; + +imm32 r0, 0xd5678911; +imm32 r1, 0x2ddddd1d; +imm32 r2, 0x34ddd515; +imm32 r3, 0x46d67717; +imm32 r4, 0x5d6d891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x74445d15; +imm32 r7, 0xd66677d7; +R0 = R6 +|+ R0, R7 = R6 -|- R0; +R1 = R6 +|+ R1, R6 = R6 -|- R1; +R2 = R6 +|+ R2, R5 = R6 -|- R2; +R3 = R6 +|+ R3, R4 = R6 -|- R3; +R4 = R6 +|+ R4, R3 = R6 -|- R4; +R5 = R6 +|+ R5, R2 = R6 -|- R5; +R6 = R6 +|+ R6, R1 = R6 -|- R6; +R7 = R6 +|+ R7, R0 = R6 -|- R7; +CHECKREG r0, 0xEDF12BEC; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x34DDD515; +CHECKREG r3, 0x46D67717; +CHECKREG r4, 0x45F888D9; +CHECKREG r5, 0x57F12ADB; +CHECKREG r6, 0x8CCEFFF0; +CHECKREG r7, 0x2BABD3F4; + +imm32 r0, 0xf567a911; +imm32 r1, 0x2f8aab1d; +imm32 r2, 0x34a45515; +imm32 r3, 0x4a6f7717; +imm32 r4, 0x5567f91b; +imm32 r5, 0xa789af1d; +imm32 r6, 0x74445515; +imm32 r7, 0x866677f7; +R0 = R7 +|+ R0, R7 = R7 -|- R0; +R1 = R7 +|+ R1, R6 = R7 -|- R1; +R2 = R7 +|+ R2, R5 = R7 -|- R2; +R3 = R7 +|+ R3, R4 = R7 -|- R3; +R4 = R7 +|+ R4, R3 = R7 -|- R4; +R5 = R7 +|+ R5, R2 = R7 -|- R5; +R6 = R7 +|+ R6, R1 = R7 -|- R6; +R7 = R7 +|+ R7, R0 = R7 -|- R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x2F8AAB1D; +CHECKREG r2, 0x34A45515; +CHECKREG r3, 0x4A6F7717; +CHECKREG r4, 0xD78F26B5; +CHECKREG r5, 0xED5A48B7; +CHECKREG r6, 0xF274F2AF; +CHECKREG r7, 0x21FE9DCC; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34e45515; +imm32 r3, 0x46667717; +imm32 r4, 0x556e891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444e515; +imm32 r7, 0x86667e77; +R4 = R2 +|+ R5, R3 = R2 -|- R5 (S); +R0 = R5 +|+ R3, R5 = R5 -|- R3 (CO); +R2 = R6 +|+ R2, R0 = R6 -|- R2 (SCO); +R3 = R4 +|+ R0, R2 = R4 -|- R0 (S); +R7 = R7 +|+ R6, R6 = R7 -|- R6 (CO); +R6 = R1 +|+ R7, R1 = R1 -|- R7 (SCO); +R5 = R0 +|+ R4, R7 = R0 -|- R4 (S); +R1 = R3 +|+ R1, R4 = R3 -|- R1 (CO); +CHECKREG r0, 0x90003F60; +CHECKREG r1, 0x8FFF7371; +CHECKREG r2, 0x7FFFC0D2; +CHECKREG r3, 0x0FFF3F92; +CHECKREG r4, 0x0BB38FFF; +CHECKREG r5, 0x0FFF3F92; +CHECKREG r6, 0x29330EA9; +CHECKREG r7, 0x80003F2E; + +imm32 r0, 0xd5678911; +imm32 r1, 0xff89ab1d; +imm32 r2, 0x34f45515; +imm32 r3, 0x46667717; +imm32 r4, 0x556f891b; +imm32 r5, 0x6789fb1d; +imm32 r6, 0x74445f15; +imm32 r7, 0x866677f7; +R4 = R3 +|+ R3, R5 = R3 -|- R3 (SCO); +R1 = R6 +|+ R1, R6 = R6 -|- R1 (SCO); +R6 = R1 +|+ R4, R4 = R1 -|- R4 (S); +R7 = R4 +|+ R2, R0 = R4 -|- R2 (S); +R2 = R2 +|+ R6, R1 = R2 -|- R6 (CO); +R3 = R5 +|+ R5, R7 = R5 -|- R5 (CO); +R5 = R7 +|+ R7, R3 = R7 -|- R7 (SCO); +R0 = R0 +|+ R0, R2 = R0 -|- R0 (SCO); +CHECKREG r0, 0x80008000; +CHECKREG r1, 0xD516B4F5; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xF3CE8A33; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x00000000; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rrppmm_sft.s b/sim/testsuite/bfin/c_dsp32alu_rrppmm_sft.s new file mode 100644 index 0000000..027f516 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rrppmm_sft.s @@ -0,0 +1,261 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft/c_dsp32alu_rrppmm_sft.dsp +// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, << +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x95679911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34945515; + imm32 r3, 0x46967717; + imm32 r4, 0x5597891b; + imm32 r5, 0x6989ab1d; + imm32 r6, 0x94445515; + imm32 r7, 0x96667777; + R0 = R0 +|+ R0, R7 = R0 -|- R0 (ASR); + R1 = R0 +|+ R1, R6 = R0 -|- R1 (ASL); + R2 = R0 +|+ R2, R5 = R0 -|- R2 (ASR); + R3 = R0 +|+ R3, R4 = R0 -|- R3 (ASR); + R4 = R0 +|+ R4, R3 = R0 -|- R4 (ASL); + R5 = R0 +|+ R5, R2 = R0 -|- R5 (ASR); + R6 = R0 +|+ R6, R1 = R0 -|- R6 (ASL); + R7 = R0 +|+ R7, R0 = R0 -|- R7 (ASR); + CHECKREG r0, 0xcAB3cC88; + CHECKREG r1, 0x73567A52; + CHECKREG r2, 0xf27FfB89; + CHECKREG r3, 0xdBFE1028; + CHECKREG r4, 0x799E541C; + CHECKREG r5, 0xa2E89D87; + CHECKREG r6, 0xE246e9F2; + CHECKREG r7, 0xcAB3cC88; + + imm32 r0, 0x11678911; + imm32 r1, 0xa719ab1d; + imm32 r2, 0x3a415515; + imm32 r3, 0x46a67717; + imm32 r4, 0x556a891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445a15; + imm32 r7, 0x866677a7; + R0 = R1 +|+ R0, R7 = R1 -|- R0 (ASR); + R1 = R1 +|+ R1, R6 = R1 -|- R1 (ASR); + R2 = R1 +|+ R2, R5 = R1 -|- R2 (ASL); + R3 = R1 +|+ R3, R4 = R1 -|- R3 (ASR); + R4 = R1 +|+ R4, R3 = R1 -|- R4 (ASR); + R5 = R1 +|+ R5, R2 = R1 -|- R5 (ASR); + R6 = R1 +|+ R6, R1 = R1 -|- R6 (ASL); + R7 = R1 +|+ R7, R0 = R1 -|- R7 (ASR); + CHECKREG r0, 0x41AC229A; + CHECKREG r1, 0x4E32563A; + CHECKREG r2, 0xe6B4fF86; + CHECKREG r3, 0xfB70088D; + CHECKREG r4, 0xaBA9a290; + CHECKREG r5, 0xc064aB96; + CHECKREG r6, 0x4E32563A; + CHECKREG r7, 0x0C8533A0; + + imm32 r0, 0xb567891b; + imm32 r1, 0x2b89abbd; + imm32 r2, 0x34b45b15; + imm32 r3, 0x466bb717; + imm32 r4, 0x556bb91b; + imm32 r5, 0x67b9ab1d; + imm32 r6, 0x7b4455b5; + imm32 r7, 0xb666777b; + R0 = R2 +|+ R0, R7 = R2 -|- R0 (ASR); + R1 = R2 +|+ R1, R6 = R2 -|- R1 (ASR); + R2 = R2 +|+ R2, R5 = R2 -|- R2 (ASR); + R3 = R2 +|+ R3, R4 = R2 -|- R3 (ASL); + R4 = R2 +|+ R4, R3 = R2 -|- R4 (ASR); + R5 = R2 +|+ R5, R2 = R2 -|- R5 (ASR); + R6 = R2 +|+ R6, R1 = R2 -|- R6 (ASL); + R7 = R2 +|+ R7, R0 = R2 -|- R7 (ASR); + CHECKREG r0, 0xED5Ae246; + CHECKREG r1, 0x2B8AaBBC; + CHECKREG r2, 0x1A5A2D8A; + CHECKREG r3, 0x2C11098C; + CHECKREG r4, 0x08A35188; + CHECKREG r5, 0x1A5A2D8A; + CHECKREG r6, 0x3DDE0A6C; + CHECKREG r7, 0x2D004B43; + + imm32 r0, 0xbc678c11; + imm32 r1, 0x27c9cb1d; + imm32 r2, 0x344c5515; + imm32 r3, 0x46c6c717; + imm32 r4, 0x55678c1b; + imm32 r5, 0x6c89abcd; + imm32 r6, 0x7444551c; + imm32 r7, 0x8c667777; + R0 = R3 +|+ R0, R7 = R3 -|- R0 (ASL); + R1 = R3 +|+ R1, R6 = R3 -|- R1 (ASR); + R2 = R3 +|+ R2, R5 = R3 -|- R2 (ASR); + R3 = R3 +|+ R3, R4 = R3 -|- R3 (ASR); + R4 = R3 +|+ R4, R3 = R3 -|- R4 (ASL); + R5 = R3 +|+ R5, R2 = R3 -|- R5 (ASR); + R6 = R3 +|+ R6, R1 = R3 -|- R6 (ASR); + R7 = R3 +|+ R7, R0 = R3 -|- R7 (ASL); + CHECKREG r0, 0xF19C3044; + CHECKREG r1, 0xbF07C818; + CHECKREG r2, 0xC227eA96; + CHECKREG r3, 0x8D8C8E2E; + CHECKREG r4, 0x8D8C8E2E; + CHECKREG r5, 0xCB64a397; + CHECKREG r6, 0xCE85C615; + CHECKREG r7, 0x44940874; + + imm32 r0, 0xd56789d1; + imm32 r1, 0x2d89abdd; + imm32 r2, 0x34d455d5; + imm32 r3, 0x4d667717; + imm32 r4, 0x5dd7891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0xd44d5515; + imm32 r7, 0xd666d777; + R0 = R4 +|+ R0, R7 = R4 -|- R0 (ASR); + R1 = R4 +|+ R1, R6 = R4 -|- R1 (ASR); + R2 = R4 +|+ R2, R5 = R4 -|- R2 (ASR); + R3 = R4 +|+ R3, R4 = R4 -|- R3 (ASL); + R4 = R4 +|+ R4, R3 = R4 -|- R4 (ASR); + R5 = R4 +|+ R5, R2 = R4 -|- R5 (ASL); + R6 = R4 +|+ R6, R1 = R4 -|- R6 (ASR); + R7 = R4 +|+ R7, R0 = R4 -|- R7 (ASR); + CHECKREG r0, 0xeE551231; + CHECKREG r1, 0x045D1AB4; + CHECKREG r2, 0x18C214CA; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x20E22408; + CHECKREG r5, 0x6AC67B56; + CHECKREG r6, 0x1C840953; + CHECKREG r7, 0x328D11D6; + + imm32 r0, 0xc567a911; + imm32 r1, 0x278aab1d; + imm32 r2, 0x3c445515; + imm32 r3, 0x46a67717; + imm32 r4, 0x55c7891b; + imm32 r5, 0x6a8cab1d; + imm32 r6, 0x7444c515; + imm32 r7, 0xa6667c77; + R0 = R5 +|+ R0, R7 = R5 -|- R0 (ASR); + R1 = R5 +|+ R1, R6 = R5 -|- R1 (ASL); + R2 = R5 +|+ R2, R5 = R5 -|- R2 (ASR); + R3 = R5 +|+ R3, R4 = R5 -|- R3 (ASR); + R4 = R5 +|+ R4, R3 = R5 -|- R4 (ASR); + R5 = R5 +|+ R5, R2 = R5 -|- R5 (ASL); + R6 = R5 +|+ R6, R1 = R5 -|- R6 (ASR); + R7 = R5 +|+ R7, R0 = R5 -|- R7 (ASR); + CHECKREG r0, 0x04FFD585; + CHECKREG r1, 0x6B46D608; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x17720887; + CHECKREG r4, 0xFFB1a27D; + CHECKREG r5, 0x5C90AC10; + CHECKREG r6, 0xF14AD608; + CHECKREG r7, 0x5791D68B; + + imm32 r0, 0xd5678911; + imm32 r1, 0x2ddddd1d; + imm32 r2, 0x34ddd515; + imm32 r3, 0x46d67717; + imm32 r4, 0x5d6d891b; + imm32 r5, 0x6789db1d; + imm32 r6, 0x74445d15; + imm32 r7, 0xd66677d7; + R0 = R6 +|+ R0, R7 = R6 -|- R0 (ASR); + R1 = R6 +|+ R1, R6 = R6 -|- R1 (ASR); + R2 = R6 +|+ R2, R5 = R6 -|- R2 (ASR); + R3 = R6 +|+ R3, R4 = R6 -|- R3 (ASL); + R4 = R6 +|+ R4, R3 = R6 -|- R4 (ASR); + R5 = R6 +|+ R5, R2 = R6 -|- R5 (ASR); + R6 = R6 +|+ R6, R1 = R6 -|- R6 (ASL); + R7 = R6 +|+ R7, R0 = R6 -|- R7 (ASR); + CHECKREG r0, 0x9EAFcAF7; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x16040544; + CHECKREG r3, 0x353C5719; + CHECKREG r4, 0xEDF6E8E3; + CHECKREG r5, 0x0D2F3AB7; + CHECKREG r6, 0x8CCCFFF0; + CHECKREG r7, 0xeE1D34F9; + + imm32 r0, 0xf567a911; + imm32 r1, 0x2f8aab1d; + imm32 r2, 0x34a45515; + imm32 r3, 0x4a6f7717; + imm32 r4, 0x5567f91b; + imm32 r5, 0xa789af1d; + imm32 r6, 0x74445515; + imm32 r7, 0x866677f7; + R0 = R7 +|+ R0, R7 = R7 -|- R0 (ASR); + R1 = R7 +|+ R1, R6 = R7 -|- R1 (ASL); + R2 = R7 +|+ R2, R5 = R7 -|- R2 (ASR); + R3 = R7 +|+ R3, R4 = R7 -|- R3 (ASR); + R4 = R7 +|+ R4, R3 = R7 -|- R4 (ASL); + R5 = R7 +|+ R5, R2 = R7 -|- R5 (ASL); + R6 = R7 +|+ R6, R1 = R7 -|- R6 (ASR); + R7 = R7 +|+ R7, R0 = R7 -|- R7 (ASL); + CHECKREG r0, 0x00000000; + CHECKREG r1, 0xCB4Af763; + CHECKREG r2, 0xFD24bC88; + CHECKREG r3, 0x12EEdE8A; + CHECKREG r4, 0x0F0EbF42; + CHECKREG r5, 0x24D8e144; + CHECKREG r6, 0xFD34700F; + CHECKREG r7, 0x21FC9DCC; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2e89ab1d; + imm32 r2, 0x34e45515; + imm32 r3, 0x46667717; + imm32 r4, 0x556e891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x7444e515; + imm32 r7, 0x86667e77; + R4 = R2 +|+ R5, R3 = R2 -|- R5 (ASR); + R0 = R5 +|+ R3, R5 = R5 -|- R3 (ASL); + R2 = R6 +|+ R2, R0 = R6 -|- R2 (ASL); + R3 = R4 +|+ R0, R2 = R4 -|- R0 (ASR); + R7 = R7 +|+ R6, R6 = R7 -|- R6 (ASL); + R6 = R1 +|+ R7, R1 = R1 -|- R7 (ASL); + R5 = R0 +|+ R4, R7 = R0 -|- R4 (ASR); + R1 = R3 +|+ R1, R4 = R3 -|- R1 (ASR); + CHECKREG r0, 0x7EC02000; + CHECKREG r1, 0x6C72EC0B; + CHECKREG r2, 0xe7BBF00C; + CHECKREG r3, 0x667B100C; + CHECKREG r4, 0xfA082401; + CHECKREG r5, 0x667B100C; + CHECKREG r6, 0x47BAE46A; + CHECKREG r7, 0x18450FF3; + + imm32 r0, 0xd5678911; + imm32 r1, 0xff89ab1d; + imm32 r2, 0x34f45515; + imm32 r3, 0x46667717; + imm32 r4, 0x556f891b; + imm32 r5, 0x6789fb1d; + imm32 r6, 0x74445f15; + imm32 r7, 0x866677f7; + R4 = R3 +|+ R3, R5 = R3 -|- R3 (ASR); + R1 = R6 +|+ R1, R6 = R6 -|- R1 (ASL); + R6 = R1 +|+ R4, R4 = R1 -|- R4 (ASL); + R7 = R4 +|+ R2, R0 = R4 -|- R2 (ASR); + R2 = R2 +|+ R6, R1 = R2 -|- R6 (ASR); + R3 = R5 +|+ R5, R7 = R5 -|- R5 (ASL); + R5 = R7 +|+ R7, R3 = R7 -|- R7 (ASL); + R0 = R0 +|+ R0, R2 = R0 -|- R0 (ASR); + CHECKREG r0, 0x06BAF2C2; + CHECKREG r1, 0xEC7A1F0F; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x42683A9A; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x5C0016F6; + CHECKREG r7, 0x00000000; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_rrppmm_sft_x.s b/sim/testsuite/bfin/c_dsp32alu_rrppmm_sft_x.s new file mode 100644 index 0000000..32913f6 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_rrppmm_sft_x.s @@ -0,0 +1,261 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft_x/c_dsp32alu_rrppmm_sft_x.dsp +// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, << X +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x95679911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34945515; + imm32 r3, 0x46967717; + imm32 r4, 0x5597891b; + imm32 r5, 0x6989ab1d; + imm32 r6, 0x94445515; + imm32 r7, 0x96667777; + R0 = R0 +|+ R0, R7 = R0 -|- R0 (CO , ASR); + R1 = R0 +|+ R1, R6 = R0 -|- R1 (CO , ASL); + R2 = R0 +|+ R2, R5 = R0 -|- R2 (CO , ASR); + R3 = R0 +|+ R3, R4 = R0 -|- R3 (CO , ASR); + R4 = R0 +|+ R4, R3 = R0 -|- R4 (CO , ASL); + R5 = R0 +|+ R5, R2 = R0 -|- R5 (CO , ASR); + R6 = R0 +|+ R6, R1 = R0 -|- R6 (CO , ASL); + R7 = R0 +|+ R7, R0 = R0 -|- R7 (CO , ASR); + CHECKREG r0, 0xcC88cAB3; + CHECKREG r1, 0x7AAA72FE; + CHECKREG r2, 0xf454f9B4; + CHECKREG r3, 0xe35208D4; + CHECKREG r4, 0x4CC880F2; + CHECKREG r5, 0x9BB2a4BD; + CHECKREG r6, 0xE29EE99A; + CHECKREG r7, 0xcAB3cC88; + + imm32 r0, 0x11678911; + imm32 r1, 0xa719ab1d; + imm32 r2, 0x3a415515; + imm32 r3, 0x46a67717; + imm32 r4, 0x556a891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445a15; + imm32 r7, 0x866677a7; + R0 = R1 +|+ R0, R7 = R1 -|- R0 (CO , ASR); + R1 = R1 +|+ R1, R6 = R1 -|- R1 (CO , ASR); + R2 = R1 +|+ R2, R5 = R1 -|- R2 (CO , ASL); + R3 = R1 +|+ R3, R4 = R1 -|- R3 (CO , ASR); + R4 = R1 +|+ R4, R3 = R1 -|- R4 (CO , ASR); + R5 = R1 +|+ R5, R2 = R1 -|- R5 (CO , ASR); + R6 = R1 +|+ R6, R1 = R1 -|- R6 (CO , ASL); + R7 = R1 +|+ R7, R0 = R1 -|- R7 (CO , ASR); + CHECKREG r0, 0x41AC229A; + CHECKREG r1, 0x563A4E32; + CHECKREG r2, 0xe8B6fD84; + CHECKREG r3, 0xfD72068B; + CHECKREG r4, 0xa08EaDAB; + CHECKREG r5, 0xa994c266; + CHECKREG r6, 0x4E32563A; + CHECKREG r7, 0x33A00C85; + + imm32 r0, 0xb567891b; + imm32 r1, 0x2b89abbd; + imm32 r2, 0x34b45b15; + imm32 r3, 0x466bb717; + imm32 r4, 0x556bb91b; + imm32 r5, 0x67b9ab1d; + imm32 r6, 0x7b4455b5; + imm32 r7, 0xb666777b; + R0 = R2 +|+ R0, R7 = R2 -|- R0 (CO , ASR); + R1 = R2 +|+ R1, R6 = R2 -|- R1 (CO , ASR); + R2 = R2 +|+ R2, R5 = R2 -|- R2 (CO , ASR); + R3 = R2 +|+ R3, R4 = R2 -|- R3 (CO , ASL); + R4 = R2 +|+ R4, R3 = R2 -|- R4 (CO , ASR); + R5 = R2 +|+ R5, R2 = R2 -|- R5 (CO , ASR); + R6 = R2 +|+ R6, R1 = R2 -|- R6 (CO , ASL); + R7 = R2 +|+ R7, R0 = R2 -|- R7 (CO , ASR); + CHECKREG r0, 0xED5Ae246; + CHECKREG r1, 0x2B8AaBBC; + CHECKREG r2, 0x2D8A1A5A; + CHECKREG r3, 0x3F41F65C; + CHECKREG r4, 0x3E581BD3; + CHECKREG r5, 0x1A5A2D8A; + CHECKREG r6, 0x0A6C3DDE; + CHECKREG r7, 0x4B432D00; + + imm32 r0, 0xbc678c11; + imm32 r1, 0x27c9cb1d; + imm32 r2, 0x344c5515; + imm32 r3, 0x46c6c717; + imm32 r4, 0x55678c1b; + imm32 r5, 0x6c89abcd; + imm32 r6, 0x7444551c; + imm32 r7, 0x8c667777; + R0 = R3 +|+ R0, R7 = R3 -|- R0 (CO , ASL); + R1 = R3 +|+ R1, R6 = R3 -|- R1 (CO , ASR); + R2 = R3 +|+ R2, R5 = R3 -|- R2 (CO , ASR); + R3 = R3 +|+ R3, R4 = R3 -|- R3 (CO , ASR); + R4 = R3 +|+ R4, R3 = R3 -|- R4 (CO , ASL); + R5 = R3 +|+ R5, R2 = R3 -|- R5 (CO , ASR); + R6 = R3 +|+ R6, R1 = R3 -|- R6 (CO , ASR); + R7 = R3 +|+ R7, R0 = R3 -|- R7 (CO , ASL); + CHECKREG r0, 0xF19C3044; + CHECKREG r1, 0xbF07C818; + CHECKREG r2, 0xC227eA96; + CHECKREG r3, 0x8E2E8D8C; + CHECKREG r4, 0x8D8C8E2E; + CHECKREG r5, 0xa397CB64; + CHECKREG r6, 0xC615CE85; + CHECKREG r7, 0x08744494; + + imm32 r0, 0xd56789d1; + imm32 r1, 0x2d89abdd; + imm32 r2, 0x34d455d5; + imm32 r3, 0x4d667717; + imm32 r4, 0x5dd7891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0xd44d5515; + imm32 r7, 0xd666d777; + R0 = R4 +|+ R0, R7 = R4 -|- R0 (CO , ASR); + R1 = R4 +|+ R1, R6 = R4 -|- R1 (CO , ASR); + R2 = R4 +|+ R2, R5 = R4 -|- R2 (CO , ASR); + R3 = R4 +|+ R3, R4 = R4 -|- R3 (CO , ASL); + R4 = R4 +|+ R4, R3 = R4 -|- R4 (CO , ASR); + R5 = R4 +|+ R5, R2 = R4 -|- R5 (CO , ASL); + R6 = R4 +|+ R6, R1 = R4 -|- R6 (CO , ASR); + R7 = R4 +|+ R7, R0 = R4 -|- R7 (CO , ASR); + CHECKREG r0, 0xeE551231; + CHECKREG r1, 0x045D1AB4; + CHECKREG r2, 0x18C214CA; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x240820E2; + CHECKREG r5, 0x7B566AC6; + CHECKREG r6, 0x09531C84; + CHECKREG r7, 0x11D6328D; + + imm32 r0, 0xc567a911; + imm32 r1, 0x278aab1d; + imm32 r2, 0x3c445515; + imm32 r3, 0x46a67717; + imm32 r4, 0x55c7891b; + imm32 r5, 0x6a8cab1d; + imm32 r6, 0x7444c515; + imm32 r7, 0xa6667c77; + R0 = R5 +|+ R0, R7 = R5 -|- R0 (CO , ASR); + R1 = R5 +|+ R1, R6 = R5 -|- R1 (CO , ASL); + R2 = R5 +|+ R2, R5 = R5 -|- R2 (CO , ASR); + R3 = R5 +|+ R3, R4 = R5 -|- R3 (CO , ASR); + R4 = R5 +|+ R4, R3 = R5 -|- R4 (CO , ASR); + R5 = R5 +|+ R5, R2 = R5 -|- R5 (CO , ASL); + R6 = R5 +|+ R6, R1 = R5 -|- R6 (CO , ASR); + R7 = R5 +|+ R7, R0 = R5 -|- R7 (CO , ASR); + CHECKREG r0, 0x04FFD585; + CHECKREG r1, 0x6B46D608; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x327AeD7F; + CHECKREG r4, 0xbD85e4A9; + CHECKREG r5, 0xAC105C90; + CHECKREG r6, 0xD608F14A; + CHECKREG r7, 0xD68B5791; + + imm32 r0, 0xd5678911; + imm32 r1, 0x2ddddd1d; + imm32 r2, 0x34ddd515; + imm32 r3, 0x46d67717; + imm32 r4, 0x5d6d891b; + imm32 r5, 0x6789db1d; + imm32 r6, 0x74445d15; + imm32 r7, 0xd66677d7; + R0 = R6 +|+ R0, R7 = R6 -|- R0 (CO , ASR); + R1 = R6 +|+ R1, R6 = R6 -|- R1 (CO , ASR); + R2 = R6 +|+ R2, R5 = R6 -|- R2 (CO , ASR); + R3 = R6 +|+ R3, R4 = R6 -|- R3 (CO , ASL); + R4 = R6 +|+ R4, R3 = R6 -|- R4 (CO , ASR); + R5 = R6 +|+ R5, R2 = R6 -|- R5 (CO , ASR); + R6 = R6 +|+ R6, R1 = R6 -|- R6 (CO , ASL); + R7 = R6 +|+ R7, R0 = R6 -|- R7 (CO , ASR); + CHECKREG r0, 0x9EAFcAF7; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x0ED20C76; + CHECKREG r3, 0x1873F3E2; + CHECKREG r4, 0x4C1A0ABF; + CHECKREG r5, 0x33851461; + CHECKREG r6, 0xFFF08CCC; + CHECKREG r7, 0x34F9eE1D; + + imm32 r0, 0xf567a911; + imm32 r1, 0x2f8aab1d; + imm32 r2, 0x34a45515; + imm32 r3, 0x4a6f7717; + imm32 r4, 0x5567f91b; + imm32 r5, 0xa789af1d; + imm32 r6, 0x74445515; + imm32 r7, 0x866677f7; + R0 = R7 +|+ R0, R7 = R7 -|- R0 (CO , ASR); + R1 = R7 +|+ R1, R6 = R7 -|- R1 (CO , ASL); + R2 = R7 +|+ R2, R5 = R7 -|- R2 (CO , ASR); + R3 = R7 +|+ R3, R4 = R7 -|- R3 (CO , ASR); + R4 = R7 +|+ R4, R3 = R7 -|- R4 (CO , ASL); + R5 = R7 +|+ R5, R2 = R7 -|- R5 (CO , ASL); + R6 = R7 +|+ R6, R1 = R7 -|- R6 (CO , ASR); + R7 = R7 +|+ R7, R0 = R7 -|- R7 (CO , ASL); + CHECKREG r0, 0x00000000; + CHECKREG r1, 0xaC561657; + CHECKREG r2, 0x5E305B7C; + CHECKREG r3, 0x73FA7D7E; + CHECKREG r4, 0x204EaE02; + CHECKREG r5, 0x4250c3CC; + CHECKREG r6, 0x511B1C28; + CHECKREG r7, 0x9DCC21FC; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2e89ab1d; + imm32 r2, 0x34e45515; + imm32 r3, 0x46667717; + imm32 r4, 0x556e891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x7444e515; + imm32 r7, 0x86667e77; + R4 = R2 +|+ R5, R3 = R2 -|- R5 (CO , ASR); + R0 = R5 +|+ R3, R5 = R5 -|- R3 (CO , ASL); + R2 = R6 +|+ R2, R0 = R6 -|- R2 (CO , ASL); + R3 = R4 +|+ R0, R2 = R4 -|- R0 (CO , ASR); + R7 = R7 +|+ R6, R6 = R7 -|- R6 (CO , ASL); + R6 = R1 +|+ R7, R1 = R1 -|- R7 (CO , ASL); + R5 = R0 +|+ R4, R7 = R0 -|- R4 (CO , ASR); + R1 = R3 +|+ R1, R4 = R3 -|- R1 (CO , ASR); + CHECKREG r0, 0x20007EC0; + CHECKREG r1, 0xfF9258EB; + CHECKREG r2, 0xC0AC171B; + CHECKREG r3, 0x371B3F6C; + CHECKREG r4, 0xE6813788; + CHECKREG r5, 0x371B3F6C; + CHECKREG r6, 0x47BAE46A; + CHECKREG r7, 0x3F53e8E5; + + imm32 r0, 0xd5678911; + imm32 r1, 0xff89ab1d; + imm32 r2, 0x34f45515; + imm32 r3, 0x46667717; + imm32 r4, 0x556f891b; + imm32 r5, 0x6789fb1d; + imm32 r6, 0x74445f15; + imm32 r7, 0x866677f7; + R4 = R3 +|+ R3, R5 = R3 -|- R3 (CO , ASR); + R1 = R6 +|+ R1, R6 = R6 -|- R1 (CO , ASL); + R6 = R1 +|+ R4, R4 = R1 -|- R4 (CO , ASL); + R7 = R4 +|+ R2, R0 = R4 -|- R2 (CO , ASR); + R2 = R2 +|+ R6, R1 = R2 -|- R6 (CO , ASR); + R3 = R5 +|+ R5, R7 = R5 -|- R5 (CO , ASL); + R5 = R7 +|+ R7, R3 = R7 -|- R7 (CO , ASL); + R0 = R0 +|+ R0, R2 = R0 -|- R0 (CO , ASR); + CHECKREG r0, 0xF6A902D3; + CHECKREG r1, 0x1F0FEC7A; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x3A9A4268; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x5C0016F6; + CHECKREG r7, 0x00000000; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_saa.s b/sim/testsuite/bfin/c_dsp32alu_saa.s new file mode 100644 index 0000000..6cb577e --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_saa.s @@ -0,0 +1,70 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_saa/c_dsp32alu_saa.dsp +// Spec Reference: dsp32alu saa +# mach: bfin + +.include "testutils.inc" + start + + A1 = 0; + A0 = 0; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86667777; + A0 = 0; + A1 = 0; + SAA ( R1:0 , R3:2 ); + R4 = A0.w; + R5 = A1.w; + CHECKREG r4, 0x00340004; + CHECKREG r5, 0x001F0023; + SAA ( R3:2 , R1:0 ); + R6 = A0.w; + R7 = A1.w; + CHECKREG r6, 0x00680008; + CHECKREG r7, 0x003E0046; + + imm32 r0, 0x1567892b; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445525; + imm32 r3, 0x46667727; + imm32 r4, 0x00340004; + imm32 r5, 0x001F0023; + imm32 r6, 0x00680008; + imm32 r7, 0x003E0046; + SAA ( R1:0 , R3:2 ); + R0 = A0.w; + R1 = A1.w; + CHECKREG r0, 0x009C000E; + CHECKREG r1, 0x005D0069; + SAA ( R3:2 , R1:0 ); + R2 = A0.w; + R3 = A1.w; + CHECKREG r2, 0x00F10025; + CHECKREG r3, 0x009100C1; + + imm32 r0, 0x496789ab; + imm32 r1, 0x6489abcd; + imm32 r2, 0x4b445555; + imm32 r3, 0x6c647777; + imm32 r4, 0x8d889999; + imm32 r5, 0xaeaa4bbb; + imm32 r6, 0xcfccd44d; + imm32 r7, 0xe1eefff4; + SAA ( R3:2 , R1:0 ) (R); + R0 = A0.w; + R1 = A1.w; + CHECKREG r0, 0x0125007B; + CHECKREG r1, 0x009900E6; + SAA ( R1:0 , R3:2 ) (R); + R6 = A0.w; + R7 = A1.w; + CHECKREG r6, 0x019C00EA; + CHECKREG r7, 0x0105011B; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_sat_aa.S b/sim/testsuite/bfin/c_dsp32alu_sat_aa.S new file mode 100644 index 0000000..981de01 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_sat_aa.S @@ -0,0 +1,41 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_sat_aa/c_dsp32alu_sat_aa.dsp +// Spec Reference: dsp32alu sat ( a1, a0) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + A0 = A1 = 0; + + imm32 r0, 0xabefda8f; + imm32 r1, 0x789abced; + imm32 r2, 0x3b44b515; + imm32 r3, 0x96667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0xabcdef89; + imm32 r7, 0xefadbc8a; + A0 = R0; + A1 = R1; + A1 = A1 (S), A0 = A0 (S); + R0 = ASTAT; + R2 = A0.w; + R3 = A1.w; + + A0 = R6; + A1 = R7; + A1 = A1 (S), A0 = A0 (S); + R1 = ASTAT; + R4 = A0.w; + R5 = A1.w; + CHECKREG r0, _AN; + CHECKREG r1, _AN; + CHECKREG r2, 0xABEFDA8F; + CHECKREG r3, 0x789ABCED; + CHECKREG r4, 0xABCDEF89; + CHECKREG r5, 0xEFADBC8A; + + pass diff --git a/sim/testsuite/bfin/c_dsp32alu_search.s b/sim/testsuite/bfin/c_dsp32alu_search.s new file mode 100644 index 0000000..68b3d32 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_search.s @@ -0,0 +1,74 @@ +//Original:/testcases/core/c_dsp32alu_search/c_dsp32alu_search.dsp +// Spec Reference: dsp32alu search +# mach: bfin + +.include "testutils.inc" + start + +imm32 p0, 0x11234556; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +( R0 , R1 ) = SEARCH R2 (GE); +( R2 , R3 ) = SEARCH R4 (GT); +( R4 , R5 ) = SEARCH R0 (LE); +( R7 , R6 ) = SEARCH R1 (LT); +CHECKREG r0, 0x11234556; +CHECKREG r1, 0x11234556; +CHECKREG r2, 0x11234556; +CHECKREG r3, 0x46667717; +CHECKREG r4, 0x11234556; +CHECKREG r5, 0x11234556; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x86667777; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r0, 0x456789ab; +imm32 r1, 0x6689abcd; +imm32 r2, 0x47445555; +imm32 r3, 0x68667777; +( R2 , R1 ) = SEARCH R3 (LE); +( R6 , R3 ) = SEARCH R5 (GT); +( R4 , R7 ) = SEARCH R2 (GE); +( R0 , R5 ) = SEARCH R4 (LT); +CHECKREG r0, 0x11234556; +CHECKREG r1, 0x6689ABCD; +CHECKREG r2, 0x47445555; +CHECKREG r3, 0x68667777; +CHECKREG r4, 0x11234556; +CHECKREG r5, 0x11234556; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x11234556; + +imm32 r0, 0x516789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x73445555; +imm32 r3, 0x84667777; +imm32 r0, 0x956789ab; +imm32 r1, 0xa689abcd; +imm32 r2, 0xb7445555; +imm32 r3, 0xc86def77; +( R3 , R4 ) = SEARCH R5 (GT); +( R0 , R7 ) = SEARCH R6 (GE); +( R6 , R1 ) = SEARCH R2 (LT); +( R2 , R5 ) = SEARCH R4 (LE); +CHECKREG r0, 0x11234556; +CHECKREG r1, 0xA689ABCD; +CHECKREG r2, 0xB7445555; +CHECKREG r3, 0xC86DEF77; +CHECKREG r4, 0x11234556; +CHECKREG r5, 0x11234556; +CHECKREG r6, 0x11234556; +CHECKREG r7, 0x11234556; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32alu_sgn.s b/sim/testsuite/bfin/c_dsp32alu_sgn.s new file mode 100644 index 0000000..de36c20 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32alu_sgn.s @@ -0,0 +1,39 @@ +//Original:/testcases/core/c_dsp32alu_sgn/c_dsp32alu_sgn.dsp +// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x456789ab; +imm32 r1, 0x6689abcd; +imm32 r2, 0x47445555; +imm32 r3, 0x68667777; +R4.H = R4.L = SIGN(R2.H) * R0.H + SIGN(R2.L) * R0.L; +R5.H = R5.L = SIGN(R2.H) * R1.H + SIGN(R2.L) * R1.L; +R6.H = R6.L = SIGN(R2.H) * R2.H + SIGN(R2.L) * R2.L; +R7.H = R7.L = SIGN(R2.H) * R3.H + SIGN(R2.L) * R3.L; +CHECKREG r4, 0xCF12CF12; +CHECKREG r5, 0x12561256; +CHECKREG r6, 0x9C999C99; +CHECKREG r7, 0xDFDDDFDD; + +imm32 r0, 0x496789ab; +imm32 r1, 0x6489abcd; +imm32 r2, 0x4b445555; +imm32 r3, 0x6c647777; +imm32 r4, 0x8d889999; +imm32 r5, 0xaeaa4bbb; +imm32 r6, 0xcfccd44d; +imm32 r7, 0xe1eefff4; +R0.H = R0.L = SIGN(R3.H) * R4.H + SIGN(R3.L) * R4.L; +R1.H = R1.L = SIGN(R3.H) * R5.H + SIGN(R3.L) * R5.L; +R2.H = R2.L = SIGN(R3.H) * R6.H + SIGN(R3.L) * R6.L; +R3.H = R3.L = SIGN(R3.H) * R7.H + SIGN(R3.L) * R7.L; +CHECKREG r0, 0x27212721; +CHECKREG r1, 0xFA65FA65; +CHECKREG r2, 0xA419A419; +CHECKREG r3, 0xE1E2E1E2; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_a1a0.s b/sim/testsuite/bfin/c_dsp32mac_a1a0.s new file mode 100644 index 0000000..25c2a2d --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_a1a0.s @@ -0,0 +1,255 @@ +//Original:/testcases/core/c_dsp32mac_a1a0/c_dsp32mac_a1a0.dsp +// Spec Reference: dsp32mac a1 a0 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 r0, 0x00000000; +A0 = 0; +A1 = 0; +ASTAT = r0; + + +// test the default (signed fraction : left ) +imm32 r0, 0x12345678; +imm32 r1, 0x33456789; +imm32 r2, 0x5556789a; +imm32 r3, 0x75678912; +imm32 r4, 0x86789123; +imm32 r5, 0xa7891234; +imm32 r6, 0xc1234567; +imm32 r7, 0xf1234567; +A1 = R0.L * R1.L, A0 = R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 = R2.L * R3.L, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 += R4.L * R5.L, A0 = R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.L * R7.L, A0 += R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x45F11C70; +CHECKREG r1, 0x45F11C70; +CHECKREG r2, 0xB48EEC5C; +CHECKREG r3, 0x8FF1C9A8; +CHECKREG r4, 0xEEB780C0; +CHECKREG r5, 0x802DABE0; +CHECKREG r6, 0xF6043652; +CHECKREG r7, 0xA5CF0AC2; + +imm32 r0, 0x12245618; +imm32 r1, 0x23256719; +imm32 r2, 0x3426781a; +imm32 r3, 0x45278912; +imm32 r4, 0x56289113; +imm32 r5, 0x67291214; +imm32 r6, 0xa1234517; +imm32 r7, 0xc1234517; +A1 = R0.L * R1.H, A0 += R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 = R2.L * R3.H, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 = R4.L * R5.H, A0 += R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 = R6.L * R7.H, A0 += R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x3B5C5702; +CHECKREG r1, 0x17A372F0; +CHECKREG r2, 0x7C3EF2EE; +CHECKREG r3, 0x40E29BEC; +CHECKREG r4, 0x886A092E; +CHECKREG r5, 0xA699C216; +CHECKREG r6, 0xB700DEC0; +CHECKREG r7, 0xDE11924A; + +imm32 r0, 0x15245648; +imm32 r1, 0x25256749; +imm32 r2, 0x3526784a; +imm32 r3, 0x45278942; +imm32 r4, 0x55389143; +imm32 r5, 0x65391244; +imm32 r6, 0xa5334547; +imm32 r7, 0xc5334547; +A1 += R0.H * R1.H, A0 = R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 += R2.H * R3.H, A0 = R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 += R4.H * R5.H, A0 = R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.H * R7.H, A0 = R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x459F2510; +CHECKREG r1, 0xE43416B2; +CHECKREG r2, 0x40FC8A8C; +CHECKREG r3, 0x00EAC446; +CHECKREG r4, 0x0C2925C0; +CHECKREG r5, 0x444EE736; +CHECKREG r6, 0x29B65052; +CHECKREG r7, 0x6E053788; + + +imm32 r0, 0x13245628; +imm32 r1, 0x23256729; +imm32 r2, 0x3326782a; +imm32 r3, 0x43278922; +imm32 r4, 0x56389123; +imm32 r5, 0x67391224; +imm32 r6, 0xa1334527; +imm32 r7, 0xc1334527; +A1 += R0.H * R1.L, A0 += R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 = R2.H * R3.L, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 = R4.H * R5.L, A0 += R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 = R6.H * R7.L, A0 += R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x6F261922; +CHECKREG r1, 0x7D725110; +CHECKREG r2, 0xAE30B1EE; +CHECKREG r3, 0xD0804218; +CHECKREG r4, 0xBA68D1AE; +CHECKREG r5, 0x0C381FC0; +CHECKREG r6, 0xE8EBF200; +CHECKREG r7, 0xCCC89B8A; + + +imm32 r0, 0x01340678; +imm32 r1, 0x02450789; +imm32 r2, 0x0356089a; +imm32 r3, 0x04670912; +imm32 r4, 0x05780123; +imm32 r5, 0x06890234; +imm32 r6, 0x07230567; +imm32 r7, 0x00230567; +A1 -= R0.L * R1.L, A0 = R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 = R2.L * R3.L, A0 -= R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 -= R4.L * R5.L, A0 -= R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 -= R6.L * R7.L, A0 += R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x00617C70; +CHECKREG r1, 0xCC671F1A; +CHECKREG r2, 0x0015C084; +CHECKREG r3, 0x009C09A8; +CHECKREG r4, 0xFFFDA7C4; +CHECKREG r5, 0x00970770; +CHECKREG r6, 0xFFFF9B56; +CHECKREG r7, 0x005CA88E; + +imm32 r0, 0x00245618; +imm32 r1, 0x01256719; +imm32 r2, 0x0226781a; +imm32 r3, 0x03278912; +imm32 r4, 0x06489113; +imm32 r5, 0x05291214; +imm32 r6, 0x01634517; +imm32 r7, 0x02234517; +A1 += R0.L * R1.H, A0 -= R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 -= R2.L * R3.H, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 -= R4.L * R5.H, A0 -= R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.L * R7.H, A0 -= R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0xBAA77AA6; +CHECKREG r1, 0x0121BB7E; +CHECKREG r2, 0xBD9CAE92; +CHECKREG r3, 0xFE2C8792; +CHECKREG r4, 0xBCB99352; +CHECKREG r5, 0x02A5517C; +CHECKREG r6, 0xBCB3A640; +CHECKREG r7, 0x03CC91C6; + +imm32 r0, 0x10240648; +imm32 r1, 0x25156749; +imm32 r2, 0x3526084a; +imm32 r3, 0x45238942; +imm32 r4, 0x51381143; +imm32 r5, 0x62392244; +imm32 r6, 0xa3333547; +imm32 r7, 0xc4334547; +A1 += R0.H * R1.H, A0 -= R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 -= R2.H * R3.H, A0 -= R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 -= R4.H * R5.H, A0 += R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.H * R7.H, A0 -= R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0xB7A22130; +CHECKREG r1, 0x08799FAE; +CHECKREG r2, 0xB327F8F4; +CHECKREG r3, 0xEBC49B4A; +CHECKREG r4, 0xC8E5FEB4; +CHECKREG r5, 0xAD71905A; +CHECKREG r6, 0x9D8AE062; +CHECKREG r7, 0xD8CCAEAC; + + +imm32 r0, 0x10245628; +imm32 r1, 0x23056729; +imm32 r2, 0x3320782a; +imm32 r3, 0x43270922; +imm32 r4, 0x56389023; +imm32 r5, 0x67391024; +imm32 r6, 0x21334507; +imm32 r7, 0x11334520; +A1 += R0.H * R1.L, A0 -= R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 -= R2.H * R3.L, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 -= R4.H * R5.L, A0 -= R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.H * R7.L, A0 -= R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x581B1792; +CHECKREG r1, 0xE5CED234; +CHECKREG r2, 0x9725B05E; +CHECKREG r3, 0xE228FDB4; +CHECKREG r4, 0x8C46709E; +CHECKREG r5, 0xD749BDF4; +CHECKREG r6, 0x87D0704C; +CHECKREG r7, 0xE93788B4; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_a1a0_iuw32.s b/sim/testsuite/bfin/c_dsp32mac_a1a0_iuw32.s new file mode 100644 index 0000000..16910ff --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_a1a0_iuw32.s @@ -0,0 +1,1014 @@ +//Original:/testcases/core/c_dsp32mac_a1a0_iuw32/c_dsp32mac_a1a0_iuw32.dsp +// Spec Reference: dsp32mac a1 a0 iuw32 MNOP +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 r0, 0x00000000; +A0 = 0; +A1 = 0; +ASTAT = r0; + + +// test the (signed integer: no ) I=1 +imm32 r0, 0x22345628; +imm32 r1, 0x23456729; +imm32 r2, 0x3456782a; +imm32 r3, 0x45678922; +imm32 r4, 0x56789123; +imm32 r5, 0x67891224; +imm32 r6, 0xa1234527; +imm32 r7, 0xc1234567; +A1 = R0.L * R7.L, A0 = R0.L * R7.L (IS); +R0 = A0.w; +R7 = A1.w; +A1 = R6.L * R1.L, A0 += R6.L * R1.H (IS); +R6 = A0.w; +R1 = A1.w; +A1 += R2.L * R3.L, A0 = R2.H * R3.L (IS); +R2 = A0.w; +R3 = A1.w; +A1 += R5.L * R4.L, A0 += R5.H * R4.H (IS); +R5 = A0.w; +R4 = A1.w; +CHECKREG r0, 0x175B7218; +CHECKREG r1, 0x1BDDC43F; +CHECKREG r2, 0xE7B2F96C; +CHECKREG r3, 0xE41233D3; +CHECKREG r4, 0xDC3712BF; +CHECKREG r5, 0x0AAB87A4; +CHECKREG r6, 0x20E26A9B; +CHECKREG r7, 0x175B7218; + +imm32 r0, 0x13335678; +imm32 r1, 0x23436789; +imm32 r2, 0x3353789a; +imm32 r3, 0xa3638912; +imm32 r4, 0x53739123; +imm32 r5, 0x63831234; +imm32 r6, 0xa1234567; +imm32 r7, 0xc1234567; +A1 = R2.L * R7.H, A0 += R2.L * R7.L (IS); +R2 = A0.w; +R7 = A1.w; +A1 = R6.L * R1.H, A0 += R6.L * R1.H (IS); +R6 = A0.w; +R1 = A1.w; +A1 += R0.L * R5.H, A0 = R0.H * R5.L (IS); +R0 = A0.w; +R5 = A1.w; +A1 += R4.L * R3.H, A0 = R4.H * R3.H (IS); +R4 = A0.w; +R3 = A1.w; +CHECKREG r0, 0x015D7C5C; +CHECKREG r1, 0x098F3EF5; +CHECKREG r2, 0x2B5D8F9A; +CHECKREG r3, 0x53474FE6; +CHECKREG r4, 0xE1CF7E79; +CHECKREG r5, 0x2B2BE65D; +CHECKREG r6, 0x34ECCE8F; +CHECKREG r7, 0xE262970E; + +imm32 r0, 0x14345678; +imm32 r1, 0x24456789; +imm32 r2, 0x3456789a; +imm32 r3, 0x44678912; +imm32 r4, 0x54789123; +imm32 r5, 0x67891244; +imm32 r6, 0xa1234547; +imm32 r7, 0xc1234547; +A1 += R4.H * R0.L, A0 = R4.L * R0.L (IS); +R4 = A0.w; +R0 = A1.w; +A1 = R3.H * R1.L, A0 += R3.L * R1.H (IS); +R3 = A0.w; +R1 = A1.w; +A1 = R2.H * R6.L, A0 = R2.H * R6.L (IS); +R2 = A0.w; +R6 = A1.w; +A1 += R7.H * R5.L, A0 += R7.H * R5.H (IS); +R7 = A0.w; +R5 = A1.w; +CHECKREG r0, 0x6FCF3826; +CHECKREG r1, 0x1BAA0C1F; +CHECKREG r2, 0x0E29B1DA; +CHECKREG r3, 0xC9B44442; +CHECKREG r4, 0xDA8DCA68; +CHECKREG r5, 0x09AD7526; +CHECKREG r6, 0x0E29B1DA; +CHECKREG r7, 0xF4BD2295; + +imm32 r0, 0x15345678; +imm32 r1, 0x23556789; +imm32 r2, 0x3455789a; +imm32 r3, 0x45675912; +imm32 r4, 0x56789523; +imm32 r5, 0x67891234; +imm32 r6, 0xa1234557; +imm32 r7, 0xc1234565; +A1 += R0.H * R1.H, A0 = R0.L * R1.L (IS); +R0 = A0.w; +R1 = A1.w; +A1 = R5.H * R6.H, A0 = R5.L * R6.H (IS); +R5 = A0.w; +R6 = A1.w; +A1 = R4.H * R3.H, A0 += R4.H * R3.L (IS); +R4 = A0.w; +R3 = A1.w; +A1 = R2.H * R7.H, A0 = R2.H * R7.H (IS); +R2 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x22F88E38; +CHECKREG r1, 0x0C9A9B6A; +CHECKREG r2, 0xF3263C9F; +CHECKREG r3, 0x17712248; +CHECKREG r4, 0x1756FD8C; +CHECKREG r5, 0xF941311C; +CHECKREG r6, 0xD9A250BB; +CHECKREG r7, 0xF3263C9F; + +// test the (unsigned or integer :no ) U=1 +imm32 r0, 0x62345678; +imm32 r1, 0x26456789; +imm32 r2, 0x3466789a; +imm32 r3, 0x45668912; +imm32 r4, 0x56786123; +imm32 r5, 0x67891634; +imm32 r6, 0xa1234567; +imm32 r7, 0xc1234566; +A1 = R0.L * R2.L, A0 = R0.L * R2.L (FU); +R0 = A0.w; +R2 = A1.w; +A1 = R1.L * R3.L, A0 += R1.L * R3.H (FU); +R1 = A0.w; +R3 = A1.w; +A1 += R4.L * R6.L, A0 = R4.H * R6.L (FU); +R4 = A0.w; +R6 = A1.w; +A1 += R5.L * R7.L, A0 += R5.H * R7.H (FU); +R5 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x28BC4430; +CHECKREG r1, 0x44CD71C6; +CHECKREG r2, 0x28BC4430; +CHECKREG r3, 0x376F98A2; +CHECKREG r4, 0x17712248; +CHECKREG r5, 0x658D9303; +CHECKREG r6, 0x51C51CB7; +CHECKREG r7, 0x57C9F96F; + +imm32 r0, 0x12345678; +imm32 r1, 0x73456789; +imm32 r2, 0x8456789a; +imm32 r3, 0x49998912; +imm32 r4, 0x56782123; +imm32 r5, 0x67891234; +imm32 r6, 0xa1234577; +imm32 r7, 0xc1234567; +A1 = R2.L * R3.H, A0 = R2.L * R3.L (FU); +R2 = A0.w; +R3 = A1.w; +A1 = R0.L * R1.H, A0 = R0.L * R1.H (FU); +R0 = A0.w; +R1 = A1.w; +A1 += R4.L * R5.H, A0 = R4.H * R5.L (FU); +R4 = A0.w; +R5 = A1.w; +A1 = R7.L * R6.H, A0 += R7.H * R6.H (FU); +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x26EF3658; +CHECKREG r1, 0x26EF3658; +CHECKREG r2, 0x4092E4D4; +CHECKREG r3, 0x22ABFE0A; +CHECKREG r4, 0x06260060; +CHECKREG r5, 0x34560713; +CHECKREG r6, 0x7FB76B29; +CHECKREG r7, 0x2BAF4415; + +imm32 r0, 0x1234567a; +imm32 r1, 0x2345678a; +imm32 r2, 0x3456a89a; +imm32 r3, 0x4a678912; +imm32 r4, 0xa6789123; +imm32 r5, 0xc7891234; +imm32 r6, 0xa1234567; +imm32 r7, 0xc1234567; +A1 = R5.H * R4.L, A0 = R5.L * R4.L (FU); +R4 = A0.w; +R5 = A1.w; +A1 = R3.H * R2.L, A0 = R3.L * R2.H (FU); +R2 = A0.w; +R3 = A1.w; +A1 = R1.H * R0.L, A0 = R1.H * R0.L (FU); +R0 = A0.w; +R1 = A1.w; +A1 = R7.H * R6.L, A0 = R7.H * R6.H (FU); +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x0BE9FCE2; +CHECKREG r1, 0x0BE9FCE2; +CHECKREG r2, 0x1C05B40C; +CHECKREG r3, 0x310059F6; +CHECKREG r4, 0x0A51F11C; +CHECKREG r5, 0x711FE0BB; +CHECKREG r6, 0x79916AC9; +CHECKREG r7, 0x345C2415; + +imm32 r0, 0xb2345678; +imm32 r1, 0x2b456789; +imm32 r2, 0x34b6789a; +imm32 r3, 0xc56b8912; +imm32 r4, 0x5c78b123; +imm32 r5, 0x67c91b34; +imm32 r6, 0xa12345b7; +imm32 r7, 0xc123456b; +A1 = R6.H * R7.H, A0 = R6.L * R7.L (FU); +R6 = A0.w; +R7 = A1.w; +A1 = R5.H * R4.H, A0 = R5.L * R4.H (FU); +R4 = A0.w; +R5 = A1.w; +A1 = R2.H * R3.H, A0 = R2.H * R3.L (FU); +R2 = A0.w; +R3 = A1.w; +A1 = R0.H * R1.H, A0 = R0.H * R1.H (FU); +R0 = A0.w; +R1 = A1.w; +CHECKREG r0, 0x1E1EC404; +CHECKREG r1, 0x1E1EC404; +CHECKREG r2, 0x1C391ACC; +CHECKREG r3, 0x28A61612; +CHECKREG r4, 0x09D37060; +CHECKREG r5, 0x257CE238; +CHECKREG r6, 0x12E7767D; +CHECKREG r7, 0x79916AC9; + +// Test w32 +imm32 r0, 0x123df178; +imm32 r1, 0x2245e189; +imm32 r2, 0x3256719a; +imm32 r3, 0x42678112; +imm32 r4, 0xa2789123; +imm32 r5, 0x62891134; +imm32 r6, 0xa2b34167; +imm32 r7, 0xc22d4167; +A1 = R0.L * R4.L, A0 += R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.L * R5.L, A0 += R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 = R2.L * R6.L, A0 += R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.L * R4.L, A0 += R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0x2AB4BAD4; +CHECKREG r1, 0x13410376; +CHECKREG r2, 0x2CF930AA; +CHECKREG r3, 0x33802490; +CHECKREG r4, 0x091C5540; +CHECKREG r5, 0xFBE7D1A8; +CHECKREG r6, 0x3A0B9DEC; +CHECKREG r7, 0xC22D4167; + +imm32 r0, 0x553df344; +imm32 r1, 0x2525e349; +imm32 r2, 0x3252734a; +imm32 r3, 0x42658342; +imm32 r4, 0xa5789343; +imm32 r5, 0x63591344; +imm32 r6, 0xa3b54347; +imm32 r7, 0xc32d4347; +A1 += R0.L * R4.H, A0 = R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 += R1.L * R5.H, A0 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.L * R6.H, A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 += R3.L * R4.H, A0 = R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0x0AD16D98; +CHECKREG r1, 0xE9B67EC2; +CHECKREG r2, 0x1A72D57C; +CHECKREG r3, 0x0965C3AC; +CHECKREG r4, 0x970BD9DE; +CHECKREG r5, 0xFBD48BC2; +CHECKREG r6, 0xA8B3CE66; +CHECKREG r7, 0xC32D4347; + +imm32 r0, 0x163df678; +imm32 r1, 0x2625e689; +imm32 r2, 0x3652769a; +imm32 r3, 0x46628612; +imm32 r4, 0xa6789623; +imm32 r5, 0x63691634; +imm32 r6, 0xa3634367; +imm32 r7, 0xc3264667; +A1 += R0.H * R4.L, A0 = R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.H * R5.L, A0 += R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.L, A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 += R3.H * R4.L, A0 += R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0x07E204D0; +CHECKREG r1, 0xF41B1732; +CHECKREG r2, 0x1C9AA1FC; +CHECKREG r3, 0xD8C785D8; +CHECKREG r4, 0x5DCEA034; +CHECKREG r5, 0x069DDB08; +CHECKREG r6, 0x23387D04; +CHECKREG r7, 0xC3264667; + +imm32 r0, 0x123df378; +imm32 r1, 0x2225e389; +imm32 r2, 0x3252739a; +imm32 r3, 0x42628312; +imm32 r4, 0xa3789323; +imm32 r5, 0x63891334; +imm32 r6, 0xa3b34367; +imm32 r7, 0xc32d4367; +A1 += R0.H * R4.H, A0 = R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.H * R5.H, A0 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.H, A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.H * R4.H, A0 = R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0x0AA862D0; +CHECKREG r1, 0xE9DD7EA2; +CHECKREG r2, 0x1A7F69FC; +CHECKREG r3, 0x29CFB5BC; +CHECKREG r4, 0x29CFB5BC; +CHECKREG r5, 0x1A8D299A; +CHECKREG r6, 0xF643F446; +CHECKREG r7, 0xC32D4367; + +imm32 r0, 0x123df678; +imm32 r1, 0x2345e789; +imm32 r2, 0x34567b9a; +imm32 r3, 0x45678c12; +imm32 r4, 0xa6789123; +imm32 r5, 0x6c891234; +imm32 r6, 0xa1b34567; +imm32 r7, 0xc12d4567; +A1 = R0.H * R4.L, A0 = R0.H * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.H * R5.L, A0 = R1.H * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 = R2.H * R6.H, A0 = R2.L * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.H * R4.H, A0 = R3.L * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xF03416AE; +CHECKREG r1, 0x1DE7F7DA; +CHECKREG r2, 0x430479EC; +CHECKREG r3, 0x0E4EA750; +CHECKREG r4, 0xF76F51D8; +CHECKREG r5, 0x05040808; +CHECKREG r6, 0xD9715C44; +CHECKREG r7, 0xC12D4567; + +// MNOP & w32 +imm32 r0, 0x623df17a; +imm32 r1, 0x7245e18b; +imm32 r2, 0x8256719a; +imm32 r3, 0x92678112; +imm32 r4, 0xa2789123; +imm32 r5, 0xb2891134; +imm32 r6, 0xc2b34167; +imm32 r7, 0xd22d4167; +A0 += R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A0 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A0 += R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A0 = R3.H * R7.H (W32); +R3 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x1AE2E2AC; +CHECKREG r1, 0x126EB2C6; +CHECKREG r2, 0xD2393FFA; +CHECKREG r3, 0x273C7436; +CHECKREG r4, 0xF76F51D8; +CHECKREG r5, 0xF76F51D8; +CHECKREG r6, 0xF76F51D8; +CHECKREG r7, 0xF76F51D8; + +imm32 r0, 0xa23df17a; +imm32 r1, 0x7b45e18b; +imm32 r2, 0x82c6719a; +imm32 r3, 0x126d8112; +imm32 r4, 0xc278e123; +imm32 r5, 0xb2491f34; +imm32 r6, 0x89b54167; +imm32 r7, 0xd25d6767; +A1 += R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.H * R7.H (W32); +R3 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x273C7436; +CHECKREG r1, 0x273C7436; +CHECKREG r2, 0x273C7436; +CHECKREG r3, 0x273C7436; +CHECKREG r4, 0xFAEFCD34; +CHECKREG r5, 0x127DED46; +CHECKREG r6, 0xD281B49A; +CHECKREG r7, 0xF96E3732; + +// test MM=1(Mix mode), MAC1 executes a mixed mode multiplication: (one input is +// signed, the other input is unsigned +imm32 r0, 0x22345628; +imm32 r1, 0x23456729; +imm32 r2, 0x3456782a; +imm32 r3, 0x45678922; +imm32 r4, 0x56789123; +imm32 r5, 0x67891224; +imm32 r6, 0xa1234527; +imm32 r7, 0xc1234567; +A1 += R0.L * R7.L (M), A0 = R0.L * R7.L (IS); +R0 = A0.w; +R7 = A1.w; +A1 = R6.L * R1.L (M), A0 += R6.L * R1.H (IS); +R6 = A0.w; +R1 = A1.w; +A1 = R2.L * R3.L (M), A0 = R2.H * R3.L (IS); +R2 = A0.w; +R3 = A1.w; +A1 += R5.L * R4.L (M), A0 += R5.H * R4.H (IS); +R5 = A0.w; +R4 = A1.w; +CHECKREG r0, 0x175B7218; +CHECKREG r1, 0x1BDDC43F; +CHECKREG r2, 0xE7B2F96C; +CHECKREG r3, 0x405E6F94; +CHECKREG r4, 0x4AA74E80; +CHECKREG r5, 0x0AAB87A4; +CHECKREG r6, 0x20E26A9B; +CHECKREG r7, 0x10C9A94A; + +imm32 r0, 0x13335678; +imm32 r1, 0x23436789; +imm32 r2, 0x3353789a; +imm32 r3, 0xa3638912; +imm32 r4, 0x53739123; +imm32 r5, 0x63831234; +imm32 r6, 0xa1234567; +imm32 r7, 0xc1234567; +A1 += R2.L * R7.H (M), A0 = R2.L * R7.L (IS); +R2 = A0.w; +R7 = A1.w; +A1 = R6.L * R1.H (M), A0 = R6.L * R1.H (IS); +R6 = A0.w; +R1 = A1.w; +A1 += R0.L * R5.H (M), A0 = R0.H * R5.L (IS); +R0 = A0.w; +R5 = A1.w; +A1 = R4.L * R3.H (M), A0 += R4.H * R3.H (IS); +R4 = A0.w; +R3 = A1.w; +CHECKREG r0, 0x015D7C5C; +CHECKREG r1, 0x098F3EF5; +CHECKREG r2, 0x20B207F6; +CHECKREG r3, 0xB93E6989; +CHECKREG r4, 0xE32CFAD5; +CHECKREG r5, 0x2B2BE65D; +CHECKREG r6, 0x098F3EF5; +CHECKREG r7, 0xA5A3E58E; + +imm32 r0, 0x14345678; +imm32 r1, 0x24456789; +imm32 r2, 0x3456789a; +imm32 r3, 0x44678912; +imm32 r4, 0x54789123; +imm32 r5, 0x67891244; +imm32 r6, 0xa1234547; +imm32 r7, 0xc1234547; +A1 = R4.H * R0.L (M), A0 = R4.L * R0.L (IS); +R4 = A0.w; +R0 = A1.w; +A1 = R3.H * R1.L (M), A0 = R3.L * R1.H (IS); +R3 = A0.w; +R1 = A1.w; +A1 = R2.H * R6.L (M), A0 = R2.H * R6.L (IS); +R2 = A0.w; +R6 = A1.w; +A1 = R7.H * R5.L (M), A0 = R7.H * R5.H (IS); +R7 = A0.w; +R5 = A1.w; +CHECKREG r0, 0x1C87E840; +CHECKREG r1, 0x1BAA0C1F; +CHECKREG r2, 0x0E29B1DA; +CHECKREG r3, 0xEF2679DA; +CHECKREG r4, 0xDA8DCA68; +CHECKREG r5, 0xFB83C34C; +CHECKREG r6, 0x0E29B1DA; +CHECKREG r7, 0xE69370BB; + +imm32 r0, 0x15345678; +imm32 r1, 0x23556789; +imm32 r2, 0x3455789a; +imm32 r3, 0x45675912; +imm32 r4, 0x56789523; +imm32 r5, 0x67891234; +imm32 r6, 0xa1234557; +imm32 r7, 0xc1234565; +A1 = R0.H * R1.H (M), A0 = R0.L * R1.L (IS); +R0 = A0.w; +R1 = A1.w; +A1 = R5.H * R6.H (M), A0 = R5.L * R6.H (IS); +R5 = A0.w; +R6 = A1.w; +A1 += R4.H * R3.H (M), A0 = R4.H * R3.L (IS); +R4 = A0.w; +R3 = A1.w; +A1 += R2.H * R7.H (M), A0 = R2.H * R7.H (IS); +R2 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x22F88E38; +CHECKREG r1, 0x02ED2644; +CHECKREG r2, 0xF3263C9F; +CHECKREG r3, 0x589C7303; +CHECKREG r4, 0x1E15CC70; +CHECKREG r5, 0xF941311C; +CHECKREG r6, 0x412B50BB; +CHECKREG r7, 0x8017AFA2; + +// test the (unsigned or integer :no ) U=1 +imm32 r0, 0x62345678; +imm32 r1, 0x26456789; +imm32 r2, 0x3466789a; +imm32 r3, 0x45668912; +imm32 r4, 0x56786123; +imm32 r5, 0x67891634; +imm32 r6, 0xa1234567; +imm32 r7, 0xc1234566; +A1 = R0.L * R2.L (M), A0 = R0.L * R2.L (FU); +R0 = A0.w; +R2 = A1.w; +A1 += R1.L * R3.L (M), A0 = R1.L * R3.H (FU); +R1 = A0.w; +R3 = A1.w; +A1 = R4.L * R6.L (M), A0 = R4.H * R6.L (FU); +R4 = A0.w; +R6 = A1.w; +A1 += R5.L * R7.L (M), A0 = R5.H * R7.H (FU); +R5 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x28BC4430; +CHECKREG r1, 0x1C112D96; +CHECKREG r2, 0x28BC4430; +CHECKREG r3, 0x602BDCD2; +CHECKREG r4, 0x17712248; +CHECKREG r5, 0x4E1C70BB; +CHECKREG r6, 0x1A558415; +CHECKREG r7, 0x205A60CD; + +imm32 r0, 0x12345678; +imm32 r1, 0x73456789; +imm32 r2, 0x8456789a; +imm32 r3, 0x49998912; +imm32 r4, 0x56782123; +imm32 r5, 0x67891234; +imm32 r6, 0xa1234577; +imm32 r7, 0xc1234567; +A1 = R2.L * R3.H (M), A0 = R2.L * R3.L (FU); +R2 = A0.w; +R3 = A1.w; +A1 = R0.L * R1.H (M), A0 = R0.L * R1.H (FU); +R0 = A0.w; +R1 = A1.w; +A1 = R4.L * R5.H (M), A0 = R4.H * R5.L (FU); +R4 = A0.w; +R5 = A1.w; +A1 = R7.L * R6.H (M), A0 = R7.H * R6.H (FU); +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x26EF3658; +CHECKREG r1, 0x26EF3658; +CHECKREG r2, 0x4092E4D4; +CHECKREG r3, 0x22ABFE0A; +CHECKREG r4, 0x06260060; +CHECKREG r5, 0x0D66D0BB; +CHECKREG r6, 0x79916AC9; +CHECKREG r7, 0x2BAF4415; + +imm32 r0, 0x1234567a; +imm32 r1, 0x2345678a; +imm32 r2, 0x3456a89a; +imm32 r3, 0x4a678912; +imm32 r4, 0xa6789123; +imm32 r5, 0xc7891234; +imm32 r6, 0xa1234567; +imm32 r7, 0xc1234567; +A1 = R5.H * R4.L (M), A0 += R5.L * R4.L (FU); +R4 = A0.w; +R5 = A1.w; +A1 = R3.H * R2.L (M), A0 = R3.L * R2.H (FU); +R2 = A0.w; +R3 = A1.w; +A1 = R1.H * R0.L (M), A0 += R1.H * R0.L (FU); +R0 = A0.w; +R1 = A1.w; +A1 = R7.H * R6.L (M), A0 = R7.H * R6.H (FU); +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x27EFB0EE; +CHECKREG r1, 0x0BE9FCE2; +CHECKREG r2, 0x1C05B40C; +CHECKREG r3, 0x310059F6; +CHECKREG r4, 0x83E35BE5; +CHECKREG r5, 0xDFFCE0BB; +CHECKREG r6, 0x79916AC9; +CHECKREG r7, 0xEEF52415; + +imm32 r0, 0xb2345678; +imm32 r1, 0x2b456789; +imm32 r2, 0x34b6789a; +imm32 r3, 0xc56b8912; +imm32 r4, 0x5c78b123; +imm32 r5, 0x67c91b34; +imm32 r6, 0xa12345b7; +imm32 r7, 0xc123456b; +A1 += R6.H * R7.H (M), A0 = R6.L * R7.L (FU); +R6 = A0.w; +R7 = A1.w; +A1 += R5.H * R4.H (M), A0 = R5.L * R4.H (FU); +R4 = A0.w; +R5 = A1.w; +A1 = R2.H * R3.H (M), A0 += R2.H * R3.L (FU); +R2 = A0.w; +R3 = A1.w; +A1 = R0.H * R1.H (M), A0 += R0.H * R1.H (FU); +R0 = A0.w; +R1 = A1.w; +CHECKREG r0, 0x442B4F30; +CHECKREG r1, 0xF2D9C404; +CHECKREG r2, 0x260C8B2C; +CHECKREG r3, 0x28A61612; +CHECKREG r4, 0x09D37060; +CHECKREG r5, 0xCCE07116; +CHECKREG r6, 0x12E7767D; +CHECKREG r7, 0xA7638EDE; + +// Test w32 +imm32 r0, 0x123df178; +imm32 r1, 0x2245e189; +imm32 r2, 0x3256719a; +imm32 r3, 0x42678112; +imm32 r4, 0xa2789123; +imm32 r5, 0x62891134; +imm32 r6, 0xa2b34167; +imm32 r7, 0xc22d4167; +A1 = R0.L * R7.L (M), A0 = R0.L * R7.L (W32); +R0 = A0.w; +R7 = A1.w; +A1 += R1.L * R5.L (M), A0 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 = R2.L * R6.L (M), A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 += R3.L * R4.L (M), A0 = R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xF8933E90; +CHECKREG r1, 0xE88C48A2; +CHECKREG r2, 0x19B82D34; +CHECKREG r3, 0xCF7A9C90; +CHECKREG r4, 0xD50FA66C; +CHECKREG r5, 0xFA3D881C; +CHECKREG r6, 0x1D05CEF6; +CHECKREG r7, 0xFC499F48; + +imm32 r0, 0x553df344; +imm32 r1, 0x2525e349; +imm32 r2, 0x3252734a; +imm32 r3, 0x42658342; +imm32 r4, 0xa5789343; +imm32 r5, 0x63591344; +imm32 r6, 0xa3b54347; +imm32 r7, 0xc32d4347; +A1 = R0.L * R7.H (M), A0 = R0.L * R7.L (W32); +R0 = A0.w; +R7 = A1.w; +A1 = R1.L * R5.H (M), A0 += R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 = R2.L * R6.H (M), A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.L * R4.H (M), A0 += R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xF94E87B8; +CHECKREG r1, 0xE305067A; +CHECKREG r2, 0x1A72D57C; +CHECKREG r3, 0xEB7D462C; +CHECKREG r4, 0xAF5F10F0; +CHECKREG r5, 0xF4DB3F61; +CHECKREG r6, 0x49B9A152; +CHECKREG r7, 0xF64A8EF4; + +imm32 r0, 0x163df678; +imm32 r1, 0x2625e689; +imm32 r2, 0x3652769a; +imm32 r3, 0x46628612; +imm32 r4, 0xa6789623; +imm32 r5, 0x63691634; +imm32 r6, 0xa3634367; +imm32 r7, 0xc3264667; +A1 = R0.H * R7.L (M), A0 = R0.L * R7.L (W32); +R0 = A0.w; +R7 = A1.w; +A1 = R1.H * R5.L (M), A0 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.L (M), A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.H * R4.L (M), A0 = R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xFAC1F490; +CHECKREG r1, 0xEC391262; +CHECKREG r2, 0x1C9AA1FC; +CHECKREG r3, 0xCEC513E0; +CHECKREG r4, 0x29470B66; +CHECKREG r5, 0x034EED84; +CHECKREG r6, 0x119C3E82; +CHECKREG r7, 0x061DA08B; + +imm32 r0, 0x123df378; +imm32 r1, 0x2225e389; +imm32 r2, 0x3252739a; +imm32 r3, 0x42628312; +imm32 r4, 0xa3789323; +imm32 r5, 0x63891334; +imm32 r6, 0xa3b34367; +imm32 r7, 0xc32d4367; +A1 = R0.H * R7.H (M), A0 = R0.L * R7.L (W32); +R0 = A0.w; +R7 = A1.w; +A1 = R1.H * R5.H (M), A0 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.H (M), A0 += R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 += R3.H * R4.H (M), A0 += R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xF966BA90; +CHECKREG r1, 0xE9DD7EA2; +CHECKREG r2, 0x045CE89E; +CHECKREG r3, 0xD45FF07E; +CHECKREG r4, 0x57D77E13; +CHECKREG r5, 0x0D4694CD; +CHECKREG r6, 0x2D73FA23; +CHECKREG r7, 0x0DE7ABB9; + +imm32 r0, 0x123df678; +imm32 r1, 0x2345e789; +imm32 r2, 0x34567b9a; +imm32 r3, 0x45678c12; +imm32 r4, 0xa6789123; +imm32 r5, 0x6c891234; +imm32 r6, 0xa1b34567; +imm32 r7, 0xc12d4567; +A1 = R0.H * R4.L (M), A0 = R0.H * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.H * R5.L (M), A0 = R1.H * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 = R2.H * R6.H (M), A0 = R2.L * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.H * R4.H (M), A0 = R3.L * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xF03416AE; +CHECKREG r1, 0x1DE7F7DA; +CHECKREG r2, 0x430479EC; +CHECKREG r3, 0xF6A29C3C; +CHECKREG r4, 0x02CD9C01; +CHECKREG r5, 0x02820404; +CHECKREG r6, 0x210EAE22; +CHECKREG r7, 0xC12D4567; + +// MNOP & w32 +imm32 r0, 0x623df17a; +imm32 r1, 0x7245e18b; +imm32 r2, 0x8256719a; +imm32 r3, 0x92678112; +imm32 r4, 0xa2789123; +imm32 r5, 0xb2891134; +imm32 r6, 0xc2b34167; +imm32 r7, 0xd22d4167; +A0 = R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A0 += R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A0 += R3.H * R7.H (W32); +R3 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x0C943B5C; +CHECKREG r1, 0x1F02EE22; +CHECKREG r2, 0xBFCA8D34; +CHECKREG r3, 0xE707016A; +CHECKREG r4, 0x02CD9C01; +CHECKREG r5, 0x02CD9C01; +CHECKREG r6, 0x02CD9C01; +CHECKREG r7, 0x02CD9C01; + +imm32 r0, 0xa23df17a; +imm32 r1, 0x7b45e18b; +imm32 r2, 0x82c6719a; +imm32 r3, 0x126d8112; +imm32 r4, 0xc278e123; +imm32 r5, 0xb2491f34; +imm32 r6, 0x89b54167; +imm32 r7, 0xd25d6767; +A1 += R0.L * R4.L (M,W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.L * R5.H (M,W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.L (M,W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.H * R7.H (M,W32); +R3 = A0.w; +R7 = A1.w; +CHECKREG r0, 0xE707016A; +CHECKREG r1, 0xE707016A; +CHECKREG r2, 0xE707016A; +CHECKREG r3, 0xE707016A; +CHECKREG r4, 0xF607D9AF; +CHECKREG r5, 0xEAC9F6A3; +CHECKREG r6, 0xCACBDA4D; +CHECKREG r7, 0x0F241B99; + +imm32 r0, 0x123df678; +imm32 r1, 0x2345e789; +imm32 r2, 0x34567b9a; +imm32 r3, 0x45678c12; +imm32 r4, 0xa6789123; +imm32 r5, 0x6c891234; +imm32 r6, 0xa1b34567; +imm32 r7, 0xc12d4567; +A1 -= R0.H * R4.L (M), A0 += R0.H * R4.L (IS); +R0 = A0.w; +R4 = A1.w; +A1 -= R1.H * R5.L (M), A0 -= R1.H * R5.H (FU); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.H (M), A0 -= R2.L * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 -= R3.H * R4.H (M), A0 -= R3.L * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xDF210CC1; +CHECKREG r1, 0xD02D10D4; +CHECKREG r2, 0x8D2896E8; +CHECKREG r3, 0x9181B214; +CHECKREG r4, 0x220C8AE5; +CHECKREG r5, 0x024B0C3E; +CHECKREG r6, 0x2359BA60; +CHECKREG r7, 0xC12D4567; + +imm32 r0, 0x123df678; +imm32 r1, 0x2345e789; +imm32 r2, 0x34567b9a; +imm32 r3, 0x45678c12; +imm32 r4, 0xa6789123; +imm32 r5, 0x6c891234; +imm32 r6, 0xa1b34567; +imm32 r7, 0xc12d4567; +A1 -= R0.H * R4.L (M), A0 = R0.H * R4.L (IS); +R0 = A0.w; +R4 = A1.w; +A1 -= R1.H * R5.L (M), A0 = R1.H * R5.H (FU); +R1 = A0.w; +R5 = A1.w; +A1 -= R2.H * R6.H (M), A0 = R2.L * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 -= R3.H * R4.H (M), A0 = R3.L * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xF81A0B57; +CHECKREG r1, 0x0EF3FBED; +CHECKREG r2, 0x430479EC; +CHECKREG r3, 0xEA874D74; +CHECKREG r4, 0xEDB77A95; +CHECKREG r5, 0x15337B8A; +CHECKREG r6, 0xF424CD68; +CHECKREG r7, 0xC12D4567; + +// MNOP & w32 +imm32 r0, 0x623df17a; +imm32 r1, 0x7245e18b; +imm32 r2, 0x8256719a; +imm32 r3, 0x92678112; +imm32 r4, 0xa2789123; +imm32 r5, 0xb2891134; +imm32 r6, 0xc2b34167; +imm32 r7, 0xd22d4167; +A0 -= R0.L * R4.L (IS); +R0 = A0.w; +R4 = A1.w; +A0 -= R1.L * R5.H (FU); +R1 = A0.w; +R5 = A1.w; +A0 -= R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A0 -= R3.H * R7.H (W32); +R3 = A0.w; +R7 = A1.w; +CHECKREG r0, 0xE43D2FC6; +CHECKREG r1, 0x46F1D663; +CHECKREG r2, 0x8727492F; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0xEDB77A95; +CHECKREG r5, 0xEDB77A95; +CHECKREG r6, 0xEDB77A95; +CHECKREG r7, 0xEDB77A95; + +imm32 r0, 0xa23df17a; +imm32 r1, 0x7b45e18b; +imm32 r2, 0x82c6719a; +imm32 r3, 0x126d8112; +imm32 r4, 0xc278e123; +imm32 r5, 0xb2491f34; +imm32 r6, 0x89b54167; +imm32 r7, 0xd25d6767; +A1 -= R0.L * R4.L (M,IS); +R0 = A0.w; +R4 = A1.w; +A1 -= R1.L * R5.H (M,FU); +R1 = A0.w; +R5 = A1.w; +A1 -= R2.H * R6.L (M,W32); +R2 = A0.w; +R6 = A1.w; +A1 -= R3.H * R7.H (M,FU); +R3 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x80000000; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0xFA7D3CE7; +CHECKREG r5, 0x0FB34644; +CHECKREG r6, 0x2FB1629A; +CHECKREG r7, 0x208D4701; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_a1a0_m.s b/sim/testsuite/bfin/c_dsp32mac_a1a0_m.s new file mode 100644 index 0000000..69d54d3 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_a1a0_m.s @@ -0,0 +1,340 @@ +//Original:/testcases/core/c_dsp32mac_a1a0_m/c_dsp32mac_a1a0_m.dsp +// Spec Reference: dsp32mac a1 a0 m MNOP +# mach: bfin + +.include "testutils.inc" + start + + + INIT_R_REGS 0; + + + imm32 r0, 0x00000000; + A0 = 0; + A1 = 0; + ASTAT = r0; + +// test the MNOP default (signed fraction : left ) rounding U=0 I=0 T=0 w32=1 + imm32 r0, 0x123c5678; + imm32 r1, 0x2345c789; + imm32 r2, 0x34567c9a; + imm32 r3, 0x456789c2; + imm32 r4, 0xc678912c; + imm32 r5, 0x6c891234; + imm32 r6, 0xa1c34567; + imm32 r7, 0xc12c4567; + + A0 = 0; + A1 = 0; + + A1 = R0.L * R1.L (M); + R0 = A0.w; + R1 = A1.w; + A0 += R2.H * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 += R4.L * R5.H; + R4 = A0.w; + R5 = A1.w; + A0 += R6.L * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x43658E38; + CHECKREG r2, 0x1C607934; + CHECKREG r3, 0x43658E38; + CHECKREG r4, 0x1C607934; + CHECKREG r5, 0xE56C0F50; + CHECKREG r6, 0xFA4FA29C; + CHECKREG r7, 0xE56C0F50; + + imm32 r0, 0xd2345678; + imm32 r1, 0x2d456789; + imm32 r2, 0x34d6789a; + imm32 r3, 0x456d8912; + imm32 r4, 0x5678d123; + imm32 r5, 0x67891d34; + imm32 r6, 0xa12345d7; + imm32 r7, 0xc123456d; + A0 += R6.H * R7.L; + R6 = A0.w; + R7 = A1.w; + A1 += R4.L * R5.H; + R4 = A0.w; + R5 = A1.w; + A0 += R2.L * R3.L; + R2 = A0.w; + R3 = A1.w; + A1 += R0.H * R1.L; + R0 = A0.w; + R1 = A1.w; + CHECKREG r0, 0x56CD8212; + CHECKREG r1, 0x9A78E46E; + CHECKREG r2, 0x56CD8212; + CHECKREG r3, 0xBF8410C6; + CHECKREG r4, 0xC6DBB86A; + CHECKREG r5, 0xBF8410C6; + CHECKREG r6, 0xC6DBB86A; + CHECKREG r7, 0xE56C0F50; + +// test MM=1(Mix mode), MAC1 executes a mixed mode multiplication: (one input is +// signed, the other input is unsigned + imm32 r0, 0x12345678; + imm32 r1, 0x33456789; + imm32 r2, 0x5556789a; + imm32 r3, 0x75678912; + imm32 r4, 0x86789123; + imm32 r5, 0xa7891234; + imm32 r6, 0xc1234567; + imm32 r7, 0xf1234567; + A1 += R0.L * R1.L (M), A0 = R0.L * R1.L; + R0 = A0.w; + R1 = A1.w; + A1 = R2.L * R3.L (M), A0 += R2.L * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 += R4.L * R5.L (M), A0 = R4.H * R5.L; + R4 = A0.w; + R5 = A1.w; + A1 = R6.L * R7.L (M), A0 = R6.H * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x45F11C70; + CHECKREG r1, 0xBD7172A6; + CHECKREG r2, 0xB48EEC5C; + CHECKREG r3, 0x4092E4D4; + CHECKREG r4, 0xEEB780C0; + CHECKREG r5, 0x38B0D5F0; + CHECKREG r6, 0x074CB592; + CHECKREG r7, 0x12D0AF71; + + imm32 r0, 0x12245618; + imm32 r1, 0x23256719; + imm32 r2, 0x3426781a; + imm32 r3, 0x45278912; + imm32 r4, 0x56289113; + imm32 r5, 0x67291214; + imm32 r6, 0xa1234517; + imm32 r7, 0xc1234517; + A1 += R0.L * R1.H (M), A0 = R0.L * R1.L; + R0 = A0.w; + R1 = A1.w; + A1 += R2.L * R3.H (M), A0 = R2.L * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 += R4.L * R5.H (M), A0 = R4.H * R5.L; + R4 = A0.w; + R5 = A1.w; + A1 += R6.L * R7.H (M), A0 += R6.H * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x455820B0; + CHECKREG r1, 0x1EA268E9; + CHECKREG r2, 0x40E29BEC; + CHECKREG r3, 0x3F13B6DF; + CHECKREG r4, 0x0C2B1640; + CHECKREG r5, 0x126097EA; + CHECKREG r6, 0x3AC1EBD2; + CHECKREG r7, 0x4680610F; + + imm32 r0, 0x15245648; + imm32 r1, 0x25256749; + imm32 r2, 0x3526784a; + imm32 r3, 0x45278942; + imm32 r4, 0x55389143; + imm32 r5, 0x65391244; + imm32 r6, 0xa5334547; + imm32 r7, 0xc5334547; + A1 = R0.H * R1.H (M), A0 = R0.L * R1.L; + R0 = A0.w; + R1 = A1.w; + A1 += R2.H * R3.H (M), A0 += R2.L * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 = R4.H * R5.H (M), A0 = R4.H * R5.L; + R4 = A0.w; + R5 = A1.w; + A1 = R6.H * R7.H (M), A0 = R6.H * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x459F2510; + CHECKREG r1, 0x03114234; + CHECKREG r2, 0x869BAF9C; + CHECKREG r3, 0x116C98FE; + CHECKREG r4, 0x0C2925C0; + CHECKREG r5, 0x21B21178; + CHECKREG r6, 0x29B65052; + CHECKREG r7, 0xBA0E2829; + + imm32 r0, 0x13245628; + imm32 r1, 0x23256729; + imm32 r2, 0x3326782a; + imm32 r3, 0x43278922; + imm32 r4, 0x56389123; + imm32 r5, 0x67391224; + imm32 r6, 0xa1334527; + imm32 r7, 0xc1334527; + A1 = R0.H * R1.L (M), A0 = R0.L * R1.L; + R0 = A0.w; + R1 = A1.w; + A1 += R2.H * R3.L (M), A0 = R2.L * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 = R4.H * R5.L (M), A0 = R4.H * R5.L; + R4 = A0.w; + R5 = A1.w; + A1 += R6.H * R7.L (M), A0 = R6.H * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x456FC8D0; + CHECKREG r1, 0x07B68CC4; + CHECKREG r2, 0x3F0A98CC; + CHECKREG r3, 0x231CADD0; + CHECKREG r4, 0x0C381FC0; + CHECKREG r5, 0x061C0FE0; + CHECKREG r6, 0x2E832052; + CHECKREG r7, 0xEC805DA5; + +// test the MNOP default (signed fraction : left ) rounding U=0 I=0 T=0 w32=1 + imm32 r0, 0x123c5678; + imm32 r1, 0x2345c789; + imm32 r2, 0x34567c9a; + imm32 r3, 0x456789c2; + imm32 r4, 0xc678912c; + imm32 r5, 0x6c891234; + imm32 r6, 0xa1c34567; + imm32 r7, 0xc12c4567; + + A0 = 0; + A1 = 0; + + A1 += R0.L * R1.L (M); + R0 = A0.w; + R1 = A1.w; + A0 += R2.H * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 = R4.L * R5.H (M); + R4 = A0.w; + R5 = A1.w; + A0 += R6.L * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x43658E38; + CHECKREG r2, 0x1C607934; + CHECKREG r3, 0x43658E38; + CHECKREG r4, 0x1C607934; + CHECKREG r5, 0xD103408C; + CHECKREG r6, 0xFA4FA29C; + CHECKREG r7, 0xD103408C; + + imm32 r0, 0xd2345678; + imm32 r1, 0x2d456789; + imm32 r2, 0x34d6789a; + imm32 r3, 0x456d8912; + imm32 r4, 0x5678d123; + imm32 r5, 0x67891d34; + imm32 r6, 0xa12345d7; + imm32 r7, 0xc123456d; + A0 = R6.H * R7.L; + R6 = A0.w; + R7 = A1.w; + A1 = R4.L * R5.H (M); + R4 = A0.w; + R5 = A1.w; + A0 = R2.L * R3.L; + R2 = A0.w; + R3 = A1.w; + A1 += R0.H * R1.L (M); + R0 = A0.w; + R1 = A1.w; + CHECKREG r0, 0x8FF1C9A8; + CHECKREG r1, 0xDA866A8F; + CHECKREG r2, 0x8FF1C9A8; + CHECKREG r3, 0xED0C00BB; + CHECKREG r4, 0xCC8C15CE; + CHECKREG r5, 0xED0C00BB; + CHECKREG r6, 0xCC8C15CE; + CHECKREG r7, 0xD103408C; + + imm32 r0, 0x123c5678; + imm32 r1, 0x2345c789; + imm32 r2, 0x34567c9a; + imm32 r3, 0x456789c2; + imm32 r4, 0xc678912c; + imm32 r5, 0x6c891234; + imm32 r6, 0xa1c34567; + imm32 r7, 0xc12c4567; + + A0 = 0; + A1 = 0; + + A1 -= R0.L * R1.L (M); + R0 = A0.w; + R1 = A1.w; + A0 -= R2.H * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 -= R4.L * R5.H (M); + R4 = A0.w; + R5 = A1.w; + A0 -= R6.L * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0xBC9A71C8; + CHECKREG r2, 0xE39F86CC; + CHECKREG r3, 0xBC9A71C8; + CHECKREG r4, 0xE39F86CC; + CHECKREG r5, 0xEB97313C; + CHECKREG r6, 0x05B05D64; + CHECKREG r7, 0xEB97313C; + + imm32 r0, 0xd2345678; + imm32 r1, 0x2d456789; + imm32 r2, 0x34d6789a; + imm32 r3, 0x456d8912; + imm32 r4, 0x5678d123; + imm32 r5, 0x67891d34; + imm32 r6, 0xa12345d7; + imm32 r7, 0xc123456d; + A0 -= R6.H * R7.L; + R6 = A0.w; + R7 = A1.w; + A1 -= R4.L * R5.H (M); + R4 = A0.w; + R5 = A1.w; + A0 -= R2.L * R3.L; + R2 = A0.w; + R3 = A1.w; + A1 -= R0.H * R1.L (M); + R0 = A0.w; + R1 = A1.w; + CHECKREG r0, 0xA9327DEE; + CHECKREG r1, 0x1110C6AD; + CHECKREG r2, 0xA9327DEE; + CHECKREG r3, 0xFE8B3081; + CHECKREG r4, 0x39244796; + CHECKREG r5, 0xFE8B3081; + CHECKREG r6, 0x39244796; + CHECKREG r7, 0xEB97313C; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + .dd 0x000f0005 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 + .dd 0x00b00104 + .dd 0x00a00105 diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a0.s b/sim/testsuite/bfin/c_dsp32mac_dr_a0.s new file mode 100644 index 0000000..71bd916 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a0.s @@ -0,0 +1,124 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0/c_dsp32mac_dr_a0.dsp +// Spec Reference: dsp32mac dr_a0 +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xab235675; +imm32 r1, 0xcaba5127; +imm32 r2, 0x13a46705; +imm32 r3, 0x000a0007; +imm32 r4, 0x90abad09; +imm32 r5, 0x10aceadb; +imm32 r6, 0x000c00ad; +imm32 r7, 0x1246700a; + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0xb3545abd; +imm32 r1, 0xabbcfec7; +imm32 r2, 0xa1b45679; +imm32 r3, 0x000b0007; +imm32 r4, 0xefbcb569; +imm32 r5, 0x12350b0b; +imm32 r6, 0x000c00bd; +imm32 r7, 0x678e000b; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +A1 -= R2.L * R3.L, R2.L = ( A0 = R2.H * R3.L ); +R3 = A0.w; +A1 = R4.L * R5.L, R4.L = ( A0 += R4.H * R5.H ); +R5 = A0.w; +A1 = R6.L * R7.L, R6.L = ( A0 = R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0xB354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xA1B4FFFB; +CHECKREG r3, 0xFFFAD7D8; +CHECKREG r4, 0xEFBCFDAB; +CHECKREG r5, 0xFDAA8BB0; +CHECKREG r6, 0x000C0099; +CHECKREG r7, 0x0098E7AC; + +imm32 r0, 0xc3545abd; +imm32 r1, 0xacbcfec7; +imm32 r2, 0xa1c45679; +imm32 r3, 0x000c0007; +imm32 r4, 0xefbcc569; +imm32 r5, 0x12350c0b; +imm32 r6, 0x000c00cd; +imm32 r7, 0x678e000c; +A1 = R1.L * R0.H, R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +A1 -= R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ); +R3 = A0.w; +A1 = R4.H * R5.H, R4.L = ( A0 += R4.H * R5.H ); +R5 = A0.w; +A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0xC354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xA1C4FF27; +CHECKREG r3, 0xFF27451E; +CHECKREG r4, 0xEFBCFCD7; +CHECKREG r5, 0xFCD6F8F6; +CHECKREG r6, 0x000CFD7D; +CHECKREG r7, 0xFD7CD262; + +imm32 r0, 0xd3545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1d45679; +imm32 r3, 0x000d0007; +imm32 r4, 0xefbcd569; +imm32 r5, 0x12350d0b; +imm32 r6, 0x000c00dd; +imm32 r7, 0x678e000d; +A1 += R1.H * R0.L, R0.L = ( A0 -= R1.L * R0.L ); +R1 = A0.w; +A1 = R2.H * R3.H, R2.L = ( A0 -= R2.H * R3.L ); +R3 = A0.w; +A1 -= R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ); +R5 = A0.w; +A1 += R6.H * R7.L, R6.L = ( A0 = R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0xD354FE5B; +CHECKREG r1, 0xFE5AB48C; +CHECKREG r2, 0xA1D4FE60; +CHECKREG r3, 0xFE5FDAF4; +CHECKREG r4, 0xEFBC00B0; +CHECKREG r5, 0x00B0271C; +CHECKREG r6, 0x000C00B3; +CHECKREG r7, 0x00B2CB2C; + +imm32 r0, 0xe3545abd; +imm32 r1, 0xaebcfec7; +imm32 r2, 0xa1e45679; +imm32 r3, 0x000e0007; +imm32 r4, 0xefbce569; +imm32 r5, 0x12350e0b; +imm32 r6, 0x000c00ed; +imm32 r7, 0x678e000e; +A1 = R1.H * R0.H, R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +A1 += R2.H * R3.H, R2.L = ( A0 += R2.H * R3.L ); +R3 = A0.w; +A1 = R4.H * R5.H, R4.L = ( A0 = R4.H * R5.H ); +R5 = A0.w; +A1 = R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0xE354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xA1E4FF1D; +CHECKREG r3, 0xFF1CF84E; +CHECKREG r4, 0xEFBCFDB0; +CHECKREG r5, 0xFDAFB3D8; +CHECKREG r6, 0x000CFCF0; +CHECKREG r7, 0xFCEFF6EC; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a0_i.s b/sim/testsuite/bfin/c_dsp32mac_dr_a0_i.s new file mode 100644 index 0000000..4696075 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a0_i.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_i/c_dsp32mac_dr_a0_i.dsp +// Spec Reference: dsp32mac dr a0 i (signed int) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0x9dbcfec7; +imm32 r2, 0xc9248679; +imm32 r3, 0xd0969007; +imm32 r4, 0xefb94569; +imm32 r5, 0xcd35900b; +imm32 r6, 0xe00c890d; +imm32 r7, 0xf78e909f; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (IS); +R1 = A0.w; +A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IS); +R3 = A0.w; +A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IS); +R5 = A0.w; +A1 += R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H ) (IS); +R7 = A0.w; +CHECKREG r0, 0xA3548000; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0xC9247FFF; +CHECKREG r3, 0x17FEBFFC; +CHECKREG r4, 0xEFB97FFF; +CHECKREG r5, 0x1B398649; +CHECKREG r6, 0xE00C7FFF; +CHECKREG r7, 0x174CF613; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x68548abd; +imm32 r1, 0x7d8cfec7; +imm32 r2, 0xa1285679; +imm32 r3, 0xb0068007; +imm32 r4, 0xcfbc4869; +imm32 r5, 0xd235c08b; +imm32 r6, 0xe00ca008; +imm32 r7, 0x678e700f; +R0.L = ( A0 -= R1.L * R0.L ) (IS); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (IS); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.L ) (IS); +R5 = A0.w; +R6.L = ( A0 -= R6.H * R7.H ) (IS); +R7 = A0.w; +CHECKREG r0, 0x68547FFF; +CHECKREG r1, 0x16BD9728; +CHECKREG r2, 0xA1288000; +CHECKREG r3, 0xFBB9CDFE; +CHECKREG r4, 0xCFBC7FFF; +CHECKREG r5, 0x0BF6CB14; +CHECKREG r6, 0xE00C7FFF; +CHECKREG r7, 0x18E3B06C; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x7b54babd; +imm32 r1, 0xb7bcdec7; +imm32 r2, 0x7b7be679; +imm32 r3, 0x80b77007; +imm32 r4, 0x9fbb7569; +imm32 r5, 0xa235b70b; +imm32 r6, 0xb00c3b7d; +imm32 r7, 0xc78ea0b7; +R0.L = ( A0 = R1.L * R0.L ) (IS); +R1 = A0.w; +R2.L = ( A0 -= R2.H * R3.L ) (IS); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.H ) (IS); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (IS); +R7 = A0.w; +CHECKREG r0, 0x7B547FFF; +CHECKREG r1, 0x08FD0EEB; +CHECKREG r2, 0x7B7B8000; +CHECKREG r3, 0xD2F3DE8E; +CHECKREG r4, 0x9FBB7FFF; +CHECKREG r5, 0x234567B7; +CHECKREG r6, 0xB00C7FFF; +CHECKREG r7, 0x1627920D; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xe3545abd; +imm32 r1, 0x5ebcfec7; +imm32 r2, 0x71e45679; +imm32 r3, 0x900e0007; +imm32 r4, 0xafbce569; +imm32 r5, 0xd2359e0b; +imm32 r6, 0xc00ca0ed; +imm32 r7, 0x678ed00e; +A1 -= R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (IS); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ) (IS); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (IS); +R5 = A0.w; +A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (IS); +R1 = A0.w; +CHECKREG r0, 0xE3547FFF; +CHECKREG r1, 0x2E5AD9ED; +CHECKREG r2, 0x71E47FFF; +CHECKREG r3, 0x15B8A0F8; +CHECKREG r4, 0xAFBC7FFF; +CHECKREG r5, 0x0E5B99EC; +CHECKREG r6, 0xC00C7FFF; +CHECKREG r7, 0x3FFFCC18; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a0_ih.s b/sim/testsuite/bfin/c_dsp32mac_dr_a0_ih.s new file mode 100644 index 0000000..3735995 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a0_ih.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_ih/c_dsp32mac_dr_a0_ih.dsp +// Spec Reference: dsp32mac dr a0 ih (integer mutiplication with high word extraction) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xf3545abd; +imm32 r1, 0x7fbcfec7; +imm32 r2, 0xc7fff679; +imm32 r3, 0xd0799007; +imm32 r4, 0xefb79f69; +imm32 r5, 0xcd35700b; +imm32 r6, 0xe00c87fd; +imm32 r7, 0xf78e909f; +A1 = R1.L * R0.L, R0.L = ( A0 -= R1.L * R0.L ) (IH); +R1 = A0.w; +A1 = R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IH); +R3 = A0.w; +A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IH); +R5 = A0.w; +A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (IH); +R7 = A0.w; +CHECKREG r0, 0xF354006F; +CHECKREG r1, 0x006EF115; +CHECKREG r2, 0xC7FF187F; +CHECKREG r3, 0x187EE7F9; +CHECKREG r4, 0xEFB71BBA; +CHECKREG r5, 0x1BBA13DC; +CHECKREG r6, 0xE00C1FB0; +CHECKREG r7, 0x1FAF9D32; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0xc5548abd; +imm32 r1, 0x9b5cfec7; +imm32 r2, 0xa9b55679; +imm32 r3, 0xb09b5007; +imm32 r4, 0xcfb9b5c9; +imm32 r5, 0x52359b5c; +imm32 r6, 0xe50c5098; +imm32 r7, 0x675e7509; +R0.L = ( A0 = R1.L * R0.L ) (IH); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (IH); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.L ) (IH); +R5 = A0.w; +R6.L = ( A0 -= R6.H * R7.H ) (IH); +R7 = A0.w; +CHECKREG r0, 0xC554008F; +CHECKREG r1, 0x008F5EEB; +CHECKREG r2, 0xA9B5E5BE; +CHECKREG r3, 0xE5BDEA2E; +CHECKREG r4, 0xCFB912FB; +CHECKREG r5, 0x12FAA97C; +CHECKREG r6, 0xE50C1DDD; +CHECKREG r7, 0x1DDCBB14; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x4b54babd; +imm32 r1, 0x12346ec7; +imm32 r2, 0xa4bbe679; +imm32 r3, 0x8abdb707; +imm32 r4, 0x9f4b7b69; +imm32 r5, 0xa234877b; +imm32 r6, 0xb00c4887; +imm32 r7, 0xc78ea4b8; +R0.L = ( A0 = R1.L * R0.L ) (IH); +R1 = A0.w; +R2.L = ( A0 -= R2.H * R3.L ) (IH); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.H ) (IH); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (IH); +R7 = A0.w; +CHECKREG r0, 0x4B54E207; +CHECKREG r1, 0xE2075EEB; +CHECKREG r2, 0xA4BBC803; +CHECKREG r3, 0xC80330CE; +CHECKREG r4, 0x9F4B236F; +CHECKREG r5, 0x236ED13C; +CHECKREG r6, 0xB00C1371; +CHECKREG r7, 0x1370FD1E; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x1a545abd; +imm32 r1, 0x42fcfec7; +imm32 r2, 0xc53f5679; +imm32 r3, 0x9c64f007; +imm32 r4, 0xafc7ec69; +imm32 r5, 0xd23c891b; +imm32 r6, 0xc00cc602; +imm32 r7, 0x678edc7e; +A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (IH); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (IH); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (IH); +R5 = A0.w; +A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (IH); +R1 = A0.w; +CHECKREG r0, 0x1A54EEED; +CHECKREG r1, 0xEEED15DF; +CHECKREG r2, 0xC53F1302; +CHECKREG r3, 0x13020C09; +CHECKREG r4, 0xAFC7EEE5; +CHECKREG r5, 0xEEE57293; +CHECKREG r6, 0xC00CFD3D; +CHECKREG r7, 0xFD3CE337; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a0_is.s b/sim/testsuite/bfin/c_dsp32mac_dr_a0_is.s new file mode 100644 index 0000000..9c10949 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a0_is.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_is/c_dsp32mac_dr_a0_is.dsp +// Spec Reference: dsp32mac dr a0 is (scale by 2.0 signed fraction with round) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xf3545abd; +imm32 r1, 0x7fbcfec7; +imm32 r2, 0xc7fff679; +imm32 r3, 0xd0799007; +imm32 r4, 0xefb79f69; +imm32 r5, 0xcd35700b; +imm32 r6, 0xe00c87fd; +imm32 r7, 0xf78e909f; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (ISS2); +R1 = A0.w; +A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (ISS2); +R3 = A0.w; +A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (ISS2); +R5 = A0.w; +A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (ISS2); +R7 = A0.w; +CHECKREG r0, 0xF3548000; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0xC7FF8000; +CHECKREG r3, 0xE71226F2; +CHECKREG r4, 0xEFB78000; +CHECKREG r5, 0xEA4D52D5; +CHECKREG r6, 0xE00C8000; +CHECKREG r7, 0xEE42DC2B; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0xc5548abd; +imm32 r1, 0x9b5cfec7; +imm32 r2, 0xa9b55679; +imm32 r3, 0xb09b5007; +imm32 r4, 0xcfb9b5c9; +imm32 r5, 0x52359b5c; +imm32 r6, 0xe50c5098; +imm32 r7, 0x675e7509; +R0.L = ( A0 -= R1.L * R0.L ) (ISS2); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (ISS2); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.L ) (ISS2); +R5 = A0.w; +R6.L = ( A0 -= R6.H * R7.H ) (ISS2); +R7 = A0.w; +CHECKREG r0, 0xC5548000; +CHECKREG r1, 0xEDB37D40; +CHECKREG r2, 0xA9B58000; +CHECKREG r3, 0xD2E20883; +CHECKREG r4, 0xCFB97FFF; +CHECKREG r5, 0x12FAA97C; +CHECKREG r6, 0xE50C7FFF; +CHECKREG r7, 0x1DDCBB14; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x4b54babd; +imm32 r1, 0x12346ec7; +imm32 r2, 0xa4bbe679; +imm32 r3, 0x8abdb707; +imm32 r4, 0x9f4b7b69; +imm32 r5, 0xa234877b; +imm32 r6, 0xb00c4887; +imm32 r7, 0xc78ea4b8; +R0.L = ( A0 = R1.L * R0.L ) (ISS2); +R1 = A0.w; +R2.L = ( A0 -= R2.H * R3.L ) (ISS2); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.H ) (ISS2); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (ISS2); +R7 = A0.w; +CHECKREG r0, 0x4B548000; +CHECKREG r1, 0xE2075EEB; +CHECKREG r2, 0xA4BB8000; +CHECKREG r3, 0xC80330CE; +CHECKREG r4, 0x9F4B7FFF; +CHECKREG r5, 0x236ED13C; +CHECKREG r6, 0xB00C7FFF; +CHECKREG r7, 0x1370FD1E; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x1a545abd; +imm32 r1, 0x42fcfec7; +imm32 r2, 0xc53f5679; +imm32 r3, 0x9c64f007; +imm32 r4, 0xafc7ec69; +imm32 r5, 0xd23c891b; +imm32 r6, 0xc00cc602; +imm32 r7, 0x678edc7e; +A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (ISS2); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (ISS2); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (ISS2); +R5 = A0.w; +A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (ISS2); +R1 = A0.w; +CHECKREG r0, 0x1A548000; +CHECKREG r1, 0xF0477293; +CHECKREG r2, 0xC53F7FFF; +CHECKREG r3, 0x13020C09; +CHECKREG r4, 0xAFC78000; +CHECKREG r5, 0xEEE57293; +CHECKREG r6, 0xC00C8000; +CHECKREG r7, 0xFD3CE337; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a0_iu.s b/sim/testsuite/bfin/c_dsp32mac_dr_a0_iu.s new file mode 100644 index 0000000..2017459 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a0_iu.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_iu/c_dsp32mac_dr_a0_iu.dsp +// Spec Reference: dsp32mac dr a0 iu (unsigned int) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x83545abd; +imm32 r1, 0x78bcfec7; +imm32 r2, 0xc7948679; +imm32 r3, 0xd0799007; +imm32 r4, 0xefb79569; +imm32 r5, 0xcd35700b; +imm32 r6, 0xe00c877d; +imm32 r7, 0xf78e9097; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ); +R3 = A0.w; +A1 = R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ); +R5 = A0.w; +A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0x8354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xC794315B; +CHECKREG r3, 0x315B6A18; +CHECKREG r4, 0xEFB72AE5; +CHECKREG r5, 0x2AE51252; +CHECKREG r6, 0xE00C32D9; +CHECKREG r7, 0x32D896FE; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0xc5548abd; +imm32 r1, 0x7b5cfec7; +imm32 r2, 0xa1b55679; +imm32 r3, 0xb00b5007; +imm32 r4, 0xcfbcb5c9; +imm32 r5, 0x5235cb5c; +imm32 r6, 0xe50c50b8; +imm32 r7, 0x675e750b; +R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ); +R3 = A0.w; +R4.L = ( A0 -= R4.H * R5.L ); +R5 = A0.w; +R6.L = ( A0 = R6.H * R7.H ); +R7 = A0.w; +CHECKREG r0, 0xC554011F; +CHECKREG r1, 0x011EBDD6; +CHECKREG r2, 0xA1B5CB1B; +CHECKREG r3, 0xCB1A8C3C; +CHECKREG r4, 0xCFBCB741; +CHECKREG r5, 0xB741151C; +CHECKREG r6, 0xE50CEA3C; +CHECKREG r7, 0xEA3BDCD0; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x4b54babd; +imm32 r1, 0xbabcdec7; +imm32 r2, 0xa4bbe679; +imm32 r3, 0x8abdb007; +imm32 r4, 0x9f4b7b69; +imm32 r5, 0xa23487bb; +imm32 r6, 0xb00c488b; +imm32 r7, 0xc78ea4b8; +R0.L = ( A0 -= R1.L * R0.L ); +R1 = A0.w; +R2.L = ( A0 = R2.H * R3.L ); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.H ); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0x4B54D842; +CHECKREG r1, 0xD841BEFA; +CHECKREG r2, 0xA4BB3906; +CHECKREG r3, 0x3906223A; +CHECKREG r4, 0x9F4B46DE; +CHECKREG r5, 0x46DDA278; +CHECKREG r6, 0xB00C26E0; +CHECKREG r7, 0x26E036AC; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x1a545abd; +imm32 r1, 0x52fcfec7; +imm32 r2, 0xc13f5679; +imm32 r3, 0x9c04f007; +imm32 r4, 0xafccec69; +imm32 r5, 0xd23c5e1b; +imm32 r6, 0xc00cc6e2; +imm32 r7, 0x678edc7e; +A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ); +R5 = A0.w; +A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ); +R1 = A0.w; +CHECKREG r0, 0x1A544DFA; +CHECKREG r1, 0x4DFA5880; +CHECKREG r2, 0xC13F2602; +CHECKREG r3, 0x26025482; +CHECKREG r4, 0xAFCC1CAD; +CHECKREG r5, 0x1CAD17A0; +CHECKREG r6, 0xC00C4F71; +CHECKREG r7, 0x4F70B886; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a0_m.s b/sim/testsuite/bfin/c_dsp32mac_dr_a0_m.s new file mode 100644 index 0000000..dcdbae0 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a0_m.s @@ -0,0 +1,127 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_m/c_dsp32mac_dr_a0_m.dsp +// Spec Reference: dsp32mac dr_a0 m +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xab235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246700f; + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +A1 -= R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ); +R3 = A0.w; +A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ); +R5 = A0.w; +A1 = R6.H * R7.H, R6.L = ( A0 = R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0x1354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xA124FF27; +CHECKREG r3, 0xFF274DDE; +CHECKREG r4, 0xEFBCFCD7; +CHECKREG r5, 0xFCD701B6; +CHECKREG r6, 0x000C000B; +CHECKREG r7, 0x000A846C; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R0.L = ( A0 += R6.L * R7.L ); +R1 = A0.w; +R2.L = ( A0 -= R2.L * R3.H ); +R3 = A0.w; +R4.L = ( A0 += R4.H * R5.L ); +R5 = A0.w; +R6.L = ( A0 = R0.H * R1.H ); +R7 = A0.w; +CHECKREG r0, 0x1354000B; +CHECKREG r1, 0x000A85F2; +CHECKREG r2, 0xA1240006; +CHECKREG r3, 0x00067846; +CHECKREG r4, 0xEFBC0005; +CHECKREG r5, 0x0005126E; +CHECKREG r6, 0x000C0002; +CHECKREG r7, 0x00018290; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +R2.L = ( A0 += R2.H * R3.L ); +R3 = A0.w; +R4.L = ( A0 += R4.H * R5.H ); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0x1354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xA124FF1D; +CHECKREG r3, 0xFF1CEDCE; +CHECKREG r4, 0xEFBCFCCD; +CHECKREG r5, 0xFCCCA1A6; +CHECKREG r6, 0x000CFCD7; +CHECKREG r7, 0xFCD72612; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +A1 = R1.L * R0.L (M), R6.L = ( A0 -= R1.L * R0.L ); +R7 = A0.w; +A1 -= R2.L * R3.H (M), R2.L = ( A0 += R2.H * R3.L ); +R3 = A0.w; +A1 = R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ); +R5 = A0.w; +A1 -= R6.H * R7.H (M), R0.L = ( A0 = R6.L * R7.H ); +R1 = A0.w; +CHECKREG r0, 0x1354000B; +CHECKREG r1, 0x000A83F2; +CHECKREG r2, 0xA124FDB0; +CHECKREG r3, 0xFDAFD834; +CHECKREG r4, 0xEFBCFDB0; +CHECKREG r5, 0xFDAFB3D8; +CHECKREG r6, 0x000CFDB5; +CHECKREG r7, 0xFDB5083C; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a0_s.s b/sim/testsuite/bfin/c_dsp32mac_dr_a0_s.s new file mode 100644 index 0000000..2288130 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a0_s.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_s/c_dsp32mac_dr_a0_s.dsp +// Spec Reference: dsp32mac dr a0 s (scale by 2.0 signed fraction with round) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x83545abd; +imm32 r1, 0x98bcfec7; +imm32 r2, 0xc9948679; +imm32 r3, 0xd0999007; +imm32 r4, 0xefb99569; +imm32 r5, 0xcd35900b; +imm32 r6, 0xe00c89ad; +imm32 r7, 0xf78e909a; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (S2RND); +R1 = A0.w; +A1 = R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (S2RND); +R3 = A0.w; +A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (S2RND); +R5 = A0.w; +A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (S2RND); +R7 = A0.w; +CHECKREG r0, 0x8354FE44; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xC9945F37; +CHECKREG r3, 0x2F9B8618; +CHECKREG r4, 0xEFB96C22; +CHECKREG r5, 0x361112B2; +CHECKREG r6, 0xE00C7BBF; +CHECKREG r7, 0x3DDFA49E; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0xc8548abd; +imm32 r1, 0x7bccfec7; +imm32 r2, 0xa1bc5679; +imm32 r3, 0xb00bc007; +imm32 r4, 0xcfbcb8c9; +imm32 r5, 0x5235cb8c; +imm32 r6, 0xe50ca0b8; +imm32 r7, 0x675e700b; +R0.L = ( A0 = R1.L * R0.L ) (S2RND); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (S2RND); +R3 = A0.w; +R4.L = ( A0 -= R4.H * R5.L ) (S2RND); +R5 = A0.w; +R6.L = ( A0 = R6.H * R7.H ) (S2RND); +R7 = A0.w; +CHECKREG r0, 0xC854023D; +CHECKREG r1, 0x011EBDD6; +CHECKREG r2, 0xA1BC9635; +CHECKREG r3, 0xCB1A8C3C; +CHECKREG r4, 0xCFBC8000; +CHECKREG r5, 0xB7532E9C; +CHECKREG r6, 0xE50CD478; +CHECKREG r7, 0xEA3BDCD0; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x7b54babd; +imm32 r1, 0xbabcdec7; +imm32 r2, 0xabbbe679; +imm32 r3, 0x8abdb007; +imm32 r4, 0x9fab7b69; +imm32 r5, 0xa23a87bb; +imm32 r6, 0xb00ca88b; +imm32 r7, 0xc78eaab8; +R0.L = ( A0 = R1.L * R0.L ) (S2RND); +R1 = A0.w; +R2.L = ( A0 -= R2.H * R3.L ) (S2RND); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.H ) (S2RND); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (S2RND); +R7 = A0.w; +CHECKREG r0, 0x7B5423F4; +CHECKREG r1, 0x11FA1DD6; +CHECKREG r2, 0xABBBBAA7; +CHECKREG r3, 0xDD53999C; +CHECKREG r4, 0x9FAB7FFF; +CHECKREG r5, 0x4692C57C; +CHECKREG r6, 0xB00C7FFF; +CHECKREG r7, 0x6D23D9B0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xfa545abd; +imm32 r1, 0x5ffcfec7; +imm32 r2, 0xc1ef5679; +imm32 r3, 0x9c0ef007; +imm32 r4, 0xafccec69; +imm32 r5, 0xd23c9e1b; +imm32 r6, 0xc00cc0e2; +imm32 r7, 0x678edc0e; +A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (S2RND); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (S2RND); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (S2RND); +R5 = A0.w; +A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (S2RND); +R1 = A0.w; +CHECKREG r0, 0xFA54CF65; +CHECKREG r1, 0xE7B2ACD4; +CHECKREG r2, 0xC1EF7FFF; +CHECKREG r3, 0x6C45F786; +CHECKREG r4, 0xAFCCCEDE; +CHECKREG r5, 0xE76F2094; +CHECKREG r6, 0xC00C0838; +CHECKREG r7, 0x041C3834; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a0_t.s b/sim/testsuite/bfin/c_dsp32mac_dr_a0_t.s new file mode 100644 index 0000000..f72f8cc --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a0_t.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_t/c_dsp32mac_dr_a0_t.dsp +// Spec Reference: dsp32mac dr a0 t (truncation) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbdbcfec7; +imm32 r2, 0xc1248679; +imm32 r3, 0xd0069007; +imm32 r4, 0xefbc4569; +imm32 r5, 0xcd35500b; +imm32 r6, 0xe00c800d; +imm32 r7, 0xf78e900f; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (T); +R1 = A0.w; +A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (T); +R3 = A0.w; +A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (T); +R5 = A0.w; +A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (T); +R7 = A0.w; +CHECKREG r0, 0xA354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xC12436FD; +CHECKREG r3, 0x36FD0FF8; +CHECKREG r4, 0xEFBC3D71; +CHECKREG r5, 0x3D716BD0; +CHECKREG r6, 0xE00C45E2; +CHECKREG r7, 0x45E2903C; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x63548abd; +imm32 r1, 0x7dbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0xb0069007; +imm32 r4, 0xcfbc4569; +imm32 r5, 0xd235c00b; +imm32 r6, 0xe00ca00d; +imm32 r7, 0x678e700f; +R0.L = ( A0 = R1.L * R0.L ) (T); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (T); +R3 = A0.w; +R4.L = ( A0 -= R4.H * R5.L ) (T); +R5 = A0.w; +R6.L = ( A0 = R6.H * R7.H ) (T); +R7 = A0.w; +CHECKREG r0, 0x6354011E; +CHECKREG r1, 0x011EBDD6; +CHECKREG r2, 0xA124CB17; +CHECKREG r3, 0xCB172B82; +CHECKREG r4, 0xCFBCB2F9; +CHECKREG r5, 0xB2F9515A; +CHECKREG r6, 0xE00CE626; +CHECKREG r7, 0xE6263550; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x6dbcdec7; +imm32 r2, 0x7124e679; +imm32 r3, 0x80067007; +imm32 r4, 0x9fbc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb00c300d; +imm32 r7, 0xc78ea00f; +R0.L = ( A0 -= R1.L * R0.L ) (T); +R1 = A0.w; +R2.L = ( A0 = R2.H * R3.L ) (T); +R3 = A0.w; +R4.L = ( A0 -= R4.H * R5.H ) (T); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (T); +R7 = A0.w; +CHECKREG r0, 0x5354D42C; +CHECKREG r1, 0xD42C177A; +CHECKREG r2, 0x71246305; +CHECKREG r3, 0x6305AFF8; +CHECKREG r4, 0x9FBC1C7B; +CHECKREG r5, 0x1C7B9C20; +CHECKREG r6, 0xB00C074B; +CHECKREG r7, 0x074B208C; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +A1 = R1.L * R0.L (M), R0.L = ( A0 += R1.L * R0.L ) (T); +R1 = A0.w; +A1 += R2.L * R3.H (M), R2.L = ( A0 -= R2.H * R3.L ) (T); +R3 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (T); +R5 = A0.w; +A1 -= R6.H * R7.H (M), R6.L = ( A0 += R6.L * R7.H ) (T); +R7 = A0.w; +CHECKREG r0, 0x3354066D; +CHECKREG r1, 0x066D3E62; +CHECKREG r2, 0x71240667; +CHECKREG r3, 0x06670E6A; +CHECKREG r4, 0xAFBC1CB7; +CHECKREG r5, 0x1CB733D8; +CHECKREG r6, 0xC00CCF17; +CHECKREG r7, 0xCF173844; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a0_tu.s b/sim/testsuite/bfin/c_dsp32mac_dr_a0_tu.s new file mode 100644 index 0000000..61c4670 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a0_tu.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_tu/c_dsp32mac_dr_a0_tu.dsp +// Spec Reference: dsp32mac dr a0 tu (truncate unsigned fraction) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xf3545abd; +imm32 r1, 0x7fbcfec7; +imm32 r2, 0xc7fff679; +imm32 r3, 0xd0799007; +imm32 r4, 0xefb79f69; +imm32 r5, 0xcd35700b; +imm32 r6, 0xe00c87fd; +imm32 r7, 0xf78e909f; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (TFU); +R1 = A0.w; +A1 -= R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (TFU); +R3 = A0.w; +A1 += R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ) (TFU); +R5 = A0.w; +A1 += R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (TFU); +R7 = A0.w; +CHECKREG r0, 0xF3545A4E; +CHECKREG r1, 0x5A4E0EEB; +CHECKREG r2, 0xC7FF0000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xEFB70000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xE00C8380; +CHECKREG r7, 0x83808956; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0xc5548abd; +imm32 r1, 0x9b5cfec7; +imm32 r2, 0xa9b55679; +imm32 r3, 0xb09b5007; +imm32 r4, 0xcfb9b5c9; +imm32 r5, 0x52359b5c; +imm32 r6, 0xe50c5098; +imm32 r7, 0x675e7509; +R0.L = ( A0 = R1.L * R0.L ) (TFU); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (TFU); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.L ) (TFU); +R5 = A0.w; +R6.L = ( A0 -= R6.H * R7.H ) (TFU); +R7 = A0.w; +CHECKREG r0, 0xC5548A13; +CHECKREG r1, 0x8A135EEB; +CHECKREG r2, 0xA9B5C5BA; +CHECKREG r3, 0xC5BAEA2E; +CHECKREG r4, 0xCFB97E0F; +CHECKREG r5, 0x7E0FA97C; +CHECKREG r6, 0xE50C2193; +CHECKREG r7, 0x2193BB14; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x4b54babd; +imm32 r1, 0x12346ec7; +imm32 r2, 0xa4bbe679; +imm32 r3, 0x8abdb707; +imm32 r4, 0x9f4b7b69; +imm32 r5, 0xa234877b; +imm32 r6, 0xb00c4887; +imm32 r7, 0xc78ea4b8; +R0.L = ( A0 -= R1.L * R0.L ) (TFU); +R1 = A0.w; +R2.L = ( A0 = R2.H * R3.L ) (TFU); +R3 = A0.w; +R4.L = ( A0 -= R4.H * R5.H ) (TFU); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (TFU); +R7 = A0.w; +CHECKREG r0, 0x4B540000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xA4BB75C6; +CHECKREG r3, 0x75C62E1D; +CHECKREG r4, 0x9F4B10D8; +CHECKREG r5, 0x10D85CE1; +CHECKREG r6, 0xB00C4961; +CHECKREG r7, 0x496188C3; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x1a545abd; +imm32 r1, 0x42fcfec7; +imm32 r2, 0xc53f5679; +imm32 r3, 0x9c64f007; +imm32 r4, 0xafc7ec69; +imm32 r5, 0xd23c891b; +imm32 r6, 0xc00cc602; +imm32 r7, 0x678edc7e; +A1 -= R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (TFU); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ) (TFU); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (TFU); +R5 = A0.w; +A1 -= R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (TFU); +R1 = A0.w; +CHECKREG r0, 0x1A5498EA; +CHECKREG r1, 0x98EA3745; +CHECKREG r2, 0xC53FA3AF; +CHECKREG r3, 0xA3AF97AE; +CHECKREG r4, 0xAFC7905A; +CHECKREG r5, 0x905A70A4; +CHECKREG r6, 0xC00C2ED1; +CHECKREG r7, 0x2ED15DDC; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a0_u.s b/sim/testsuite/bfin/c_dsp32mac_dr_a0_u.s new file mode 100644 index 0000000..5ca5cac --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a0_u.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_u/c_dsp32mac_dr_a0_u.dsp +// Spec Reference: dsp32mac dr a0 u (unsigned fraction and unsigned int) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0x9abcfec7; +imm32 r2, 0xc9a48679; +imm32 r3, 0xd09a9007; +imm32 r4, 0xefb9a569; +imm32 r5, 0xcd359a0b; +imm32 r6, 0xe00c89ad; +imm32 r7, 0xf78e909a; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (FU); +R1 = A0.w; +A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (FU); +R3 = A0.w; +A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (FU); +R5 = A0.w; +A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (FU); +R7 = A0.w; +CHECKREG r0, 0xA3545A4E; +CHECKREG r1, 0x5A4E0EEB; +CHECKREG r2, 0xC9A40000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xEFB9C029; +CHECKREG r5, 0xC028C64D; +CHECKREG r6, 0xE00CFFFF; +CHECKREG r7, 0x454B0F43; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0xb8548abd; +imm32 r1, 0x7b8cfec7; +imm32 r2, 0xa1b85679; +imm32 r3, 0xb00b8007; +imm32 r4, 0xcfbcb869; +imm32 r5, 0xd235cb8b; +imm32 r6, 0xe00ca0b8; +imm32 r7, 0x678e700b; +R0.L = ( A0 = R1.L * R0.L ) (FU); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (FU); +R3 = A0.w; +R4.L = ( A0 -= R4.H * R5.L ) (FU); +R5 = A0.w; +R6.L = ( A0 = R6.H * R7.H ) (FU); +R7 = A0.w; +CHECKREG r0, 0xB8548A13; +CHECKREG r1, 0x8A135EEB; +CHECKREG r2, 0xA1B8C58A; +CHECKREG r3, 0xC58A461E; +CHECKREG r4, 0xCFBC205F; +CHECKREG r5, 0x205F670A; +CHECKREG r6, 0xE00C5AA1; +CHECKREG r7, 0x5AA11AA8; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x7b54babd; +imm32 r1, 0xb7bcdec7; +imm32 r2, 0xab7be679; +imm32 r3, 0x8ab7b007; +imm32 r4, 0x9fab7b69; +imm32 r5, 0xa23ab7bb; +imm32 r6, 0xb00cab7b; +imm32 r7, 0xc78eaab7; +R0.L = ( A0 = R1.L * R0.L ) (FU); +R1 = A0.w; +R2.L = ( A0 -= R2.H * R3.L ) (FU); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.H ) (FU); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (FU); +R7 = A0.w; +CHECKREG r0, 0x7B54A281; +CHECKREG r1, 0xA2810EEB; +CHECKREG r2, 0xAB7B2C98; +CHECKREG r3, 0x2C97CE8E; +CHECKREG r4, 0x9FAB652E; +CHECKREG r5, 0x652E62BE; +CHECKREG r6, 0xB00CEADA; +CHECKREG r7, 0xEADA1DF8; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xea545abd; +imm32 r1, 0x5eacfec7; +imm32 r2, 0xc1ea5679; +imm32 r3, 0x9c0ea007; +imm32 r4, 0xafccea69; +imm32 r5, 0xd23c9eab; +imm32 r6, 0xc00cc0ea; +imm32 r7, 0x678edc0e; +A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (FU); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (FU); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (FU); +R5 = A0.w; +A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (FU); +R1 = A0.w; +CHECKREG r0, 0xEA540484; +CHECKREG r1, 0x04840000; +CHECKREG r2, 0xC1EAFFFF; +CHECKREG r3, 0x45282CE3; +CHECKREG r4, 0xAFCC0000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xC00C2200; +CHECKREG r7, 0x22002A7E; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1.s new file mode 100644 index 0000000..33c5981 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1.s @@ -0,0 +1,213 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1/c_dsp32mac_dr_a1.dsp +// Spec Reference: dsp32mac dr_a1 +# mach: bfin + +.include "testutils.inc" + start + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R0.H = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L; +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; +R3 = A1.w; +R4.H = ( A1 = R4.L * R5.L ), A0 += R4.H * R5.H; +R5 = A1.w; +R6.H = ( A1 += R6.L * R7.L ), A0 += R6.L * R7.H; +R7 = A1.w; +CHECKREG r0, 0xFF225ABD; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0x00055679; +CHECKREG r3, 0x0004BA9E; +CHECKREG r4, 0x00064569; +CHECKREG r5, 0x0005F706; +CHECKREG r6, 0x0006000D; +CHECKREG r7, 0x0005F88C; + +imm32 r0, 0x13545abd; +imm32 r1, 0xa1bcfec7; +imm32 r2, 0xa1145679; +imm32 r3, 0x00010007; +imm32 r4, 0xefbc1569; +imm32 r5, 0x1235010b; +imm32 r6, 0x000c001d; +imm32 r7, 0x678e0001; +R4.H = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L; +R5 = A1.w; +R0.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L; +R1 = A1.w; +R2.H = ( A1 = R4.L * R5.H ), A0 += R4.H * R5.H; +R3 = A1.w; +R6.H = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H; +R7 = A1.w; +CHECKREG r0, 0x00015ABD; +CHECKREG r1, 0x0000ACF2; +CHECKREG r2, 0xFFF95679; +CHECKREG r3, 0xFFF8F98C; +CHECKREG r4, 0xFFD71569; +CHECKREG r5, 0xFFD6B524; +CHECKREG r6, 0x0010001D; +CHECKREG r7, 0x00106FB8; + +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xa1845679; +imm32 r3, 0x00080007; +imm32 r4, 0xefbc8569; +imm32 r5, 0x1235080b; +imm32 r6, 0x000c008d; +imm32 r7, 0x678e0008; +R6.H = ( A1 += R1.H * R0.L ), A0 = R1.L * R0.L; +R7 = A1.w; +R2.H = ( A1 = R2.H * R3.L ), A0 = R2.H * R3.L; +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H; +R5 = A1.w; +R0.H = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H; +R1 = A1.w; +CHECKREG r0, 0x1B505ABD; +CHECKREG r1, 0x1B4FC2A8; +CHECKREG r2, 0xFFFB5679; +CHECKREG r3, 0xFFFAD538; +CHECKREG r4, 0xFEFA8569; +CHECKREG r5, 0xFEFA5A28; +CHECKREG r6, 0xC234008D; +CHECKREG r7, 0xC233C550; + +imm32 r0, 0xc3545abd; +imm32 r1, 0xacbcfec7; +imm32 r2, 0xa1c45679; +imm32 r3, 0x000c0007; +imm32 r4, 0xefbcc569; +imm32 r5, 0x12350c0b; +imm32 r6, 0x000c00cd; +imm32 r7, 0x678e000c; +R6.H = ( A1 += R1.H * R0.H ), A0 = R1.L * R0.L; +R7 = A1.w; +R0.H = ( A1 = R2.H * R3.H ), A0 = R2.H * R3.L; +R1 = A1.w; +R4.H = ( A1 = R4.H * R5.H ), A0 += R4.H * R5.H; +R5 = A1.w; +R2.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H; +R3 = A1.w; +CHECKREG r0, 0xFFF75ABD; +CHECKREG r1, 0xFFF72A60; +CHECKREG r2, 0x20875679; +CHECKREG r3, 0x2086A6C8; +CHECKREG r4, 0xFDB0C569; +CHECKREG r5, 0xFDAFB3D8; +CHECKREG r6, 0x42C800CD; +CHECKREG r7, 0x42C78608; + +imm32 r0, 0x01542abd; +imm32 r1, 0x02bc4ec7; +imm32 r2, 0x03240679; +imm32 r3, 0x04061007; +imm32 r4, 0x05bc2569; +imm32 r5, 0x0635300b; +imm32 r6, 0x070c200d; +imm32 r7, 0x088e100f; +R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L; +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.L ), A0 -= R2.H * R3.L; +R3 = A1.w; +R4.H = ( A1 -= R4.L * R5.L ), A0 += R4.H * R5.H; +R5 = A1.w; +R6.H = ( A1 += R6.L * R7.L ), A0 -= R6.L * R7.H; +R7 = A1.w; +CHECKREG r0, 0x06392ABD; +CHECKREG r1, 0x063908F2; +CHECKREG r2, 0x056A0679; +CHECKREG r3, 0x05698E54; +CHECKREG r4, 0xF75F2569; +CHECKREG r5, 0xF75EF74E; +CHECKREG r6, 0xFB64200D; +CHECKREG r7, 0xFB6458D4; + +imm32 r0, 0x03545abd; +imm32 r1, 0x31bcfec7; +imm32 r2, 0x11145679; +imm32 r3, 0x00010007; +imm32 r4, 0xefbc1569; +imm32 r5, 0x1235010b; +imm32 r6, 0x000c001d; +imm32 r7, 0x678e0001; +R4.H = ( A1 += R1.L * R0.H ), A0 -= R1.L * R0.L; +R5 = A1.w; +R0.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L; +R1 = A1.w; +R2.H = ( A1 -= R4.L * R5.H ), A0 += R4.H * R5.H; +R3 = A1.w; +R6.H = ( A1 += R6.L * R7.H ), A0 -= R6.L * R7.H; +R7 = A1.w; +CHECKREG r0, 0xFB5C5ABD; +CHECKREG r1, 0xFB5B887A; +CHECKREG r2, 0xFC225679; +CHECKREG r3, 0xFC223F02; +CHECKREG r4, 0xFB5C1569; +CHECKREG r5, 0xFB5C356C; +CHECKREG r6, 0xFC3A001D; +CHECKREG r7, 0xFC39B52E; + +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xa1845679; +imm32 r3, 0x00080007; +imm32 r4, 0xefbc8569; +imm32 r5, 0x1235080b; +imm32 r6, 0x000c008d; +imm32 r7, 0x678e0008; +R6.H = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L; +R7 = A1.w; +R2.H = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L; +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ), A0 -= R4.H * R5.H; +R5 = A1.w; +R0.H = ( A1 += R6.H * R7.L ), A0 -= R6.L * R7.H; +R1 = A1.w; +CHECKREG r0, 0xF9745ABD; +CHECKREG r1, 0xF9741604; +CHECKREG r2, 0xBE625679; +CHECKREG r3, 0xBE62358E; +CHECKREG r4, 0xFEFA8569; +CHECKREG r5, 0xFEFA5A28; +CHECKREG r6, 0xBE5D008D; +CHECKREG r7, 0xBE5D0AC6; + +imm32 r0, 0xc3545abd; +imm32 r1, 0xacbcfec7; +imm32 r2, 0xa1c45679; +imm32 r3, 0x000c0007; +imm32 r4, 0xefbcc569; +imm32 r5, 0x12350c0b; +imm32 r6, 0x000c00cd; +imm32 r7, 0x678e000c; +R6.H = ( A1 += R1.H * R0.H ), A0 -= R1.L * R0.L; +R7 = A1.w; +R0.H = ( A1 = R2.H * R3.H ), A0 -= R2.H * R3.L; +R1 = A1.w; +R4.H = ( A1 -= R4.H * R5.H ), A0 += R4.H * R5.H; +R5 = A1.w; +R2.H = ( A1 -= R6.H * R7.H ), A0 += R6.L * R7.H; +R3 = A1.w; +CHECKREG r0, 0xFFF75ABD; +CHECKREG r1, 0xFFF72A60; +CHECKREG r2, 0xF9D05679; +CHECKREG r3, 0xF9D00540; +CHECKREG r4, 0x0247C569; +CHECKREG r5, 0x02477688; +CHECKREG r6, 0x20EC00CD; +CHECKREG r7, 0x20EBD964; + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1_i.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1_i.s new file mode 100644 index 0000000..de42387 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1_i.s @@ -0,0 +1,273 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_i/c_dsp32mac_dr_a1_i.dsp +// Spec Reference: dsp32mac dr a1 i (signed int) +# mach: bfin + +.include "testutils.inc" + start + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbdbcfec7; +imm32 r2, 0xc1248679; +imm32 r3, 0xd0069007; +imm32 r4, 0xefbc4569; +imm32 r5, 0xcd35500b; +imm32 r6, 0xe00c800d; +imm32 r7, 0xf78e900f; +R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (IS); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (IS); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (IS); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x7FFF8679; +CHECKREG r3, 0x16C676D6; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0xFAEA0D14; +CHECKREG r6, 0x7FFF800D; +CHECKREG r7, 0x010DDAA8; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x63548abd; +imm32 r1, 0x7dbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0xb0069007; +imm32 r4, 0xcfbc4569; +imm32 r5, 0xFFFF8000; +imm32 r6, 0x7FFF800D; +imm32 r7, 0x00007FFF; +R0.H = ( A1 = R1.L * R0.L ) (IS); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (IS); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (IS); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (IS); +R7 = A1.w; +CHECKREG r0, 0x7FFF8ABD; +CHECKREG r1, 0x008F5EEB; +CHECKREG r2, 0x80005679; +CHECKREG r3, 0xE58B95C1; +CHECKREG r4, 0x7FFF4569; +CHECKREG r5, 0x18220000; +CHECKREG r6, 0x0000800D; +CHECKREG r7, 0x00000000; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x6dbcdec7; +imm32 r2, 0x7124e679; +imm32 r3, 0x80067007; +imm32 r4, 0x9fbc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb00c300d; +imm32 r7, 0xc78ea00f; + R0.H = A1 , A0 = R1.L * R0.L (IS); +R1 = A1.w; + R2.H = A1 , A0 = R2.H * R3.L (IS); +R3 = A1.w; + R4.H = A1 , A0 = R4.H * R5.H (IS); +R5 = A1.w; + R6.H = A1 , A0 += R6.L * R7.H (IS); +R7 = A1.w; +CHECKREG r0, 0x0000BABD; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x0000E679; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00004569; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x0000300D; +CHECKREG r7, 0x00000000; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (IS); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M), A0 = R2.H * R3.L (IS); +R3 = A0.w; +R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (IS); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H (IS); +R7 = A0.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x7FFF5679; +CHECKREG r3, 0x000317FC; +CHECKREG r4, 0x7FFF4569; +CHECKREG r5, 0x030D72D5; +CHECKREG r6, 0x8000A00D; +CHECKREG r7, 0xE78B9C22; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xc1845679; +imm32 r3, 0x1c080007; +imm32 r4, 0xe1cc8569; +imm32 r5, 0x921c080b; +imm32 r6, 0x7901908d; +imm32 r7, 0x679e9008; +R0.H = ( A1 += R1.L * R0.L ) (M,IS); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ) (M,IS); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ) (M,IS); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M,IS); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xE5B26993; +CHECKREG r2, 0x7FFF5679; +CHECKREG r3, 0x0977EFC8; +CHECKREG r4, 0x7FFF8569; +CHECKREG r5, 0x0885038C; +CHECKREG r6, 0x7FFF908D; +CHECKREG r7, 0x30FA159E; + +imm32 r0, 0x03545abd; +imm32 r1, 0x1dbcfec7; +imm32 r2, 0x21248679; +imm32 r3, 0x30069007; +imm32 r4, 0x4fbc4569; +imm32 r5, 0x5d35500b; +imm32 r6, 0x600c800d; +imm32 r7, 0x778e900f; +R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L (IS); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L (IS); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IS); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ), A0 -= R6.L * R7.H (IS); +R7 = A1.w; +CHECKREG r0, 0x7FFF5ABD; +CHECKREG r1, 0x316906B3; +CHECKREG r2, 0x80008679; +CHECKREG r3, 0xE933D6D6; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0xD045A9C2; +CHECKREG r6, 0x8000800D; +CHECKREG r7, 0xA36ACF1A; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x63540abd; +imm32 r1, 0x7dbc1ec7; +imm32 r2, 0xa1242679; +imm32 r3, 0x40063007; +imm32 r4, 0x1fbc4569; +imm32 r5, 0x2FFF4000; +imm32 r6, 0x7FFF800D; +imm32 r7, 0x10007FFF; +R0.H = ( A1 -= R1.L * R0.L ) (IS); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (IS); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (IS); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (IS); +R7 = A1.w; +CHECKREG r0, 0x80000ABD; +CHECKREG r1, 0xA220502F; +CHECKREG r2, 0x80002679; +CHECKREG r3, 0x98812959; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0x90922959; +CHECKREG r6, 0x8000800D; +CHECKREG r7, 0x88923959; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x2354babd; +imm32 r1, 0x3dbcdec7; +imm32 r2, 0x7424e679; +imm32 r3, 0x80067007; +imm32 r4, 0x95bc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb06c300d; +imm32 r7, 0xc787a00f; + R0.H = A1 , A0 -= R1.L * R0.L (IS); +R1 = A1.w; + R2.H = A1 , A0 -= R2.H * R3.L (IS); +R3 = A1.w; + R4.H = A1 , A0 -= R4.H * R5.H (IS); +R5 = A1.w; + R6.H = A1 , A0 -= R6.L * R7.H (IS); +R7 = A1.w; +CHECKREG r0, 0x8000BABD; +CHECKREG r1, 0x88923959; +CHECKREG r2, 0x8000E679; +CHECKREG r3, 0x88923959; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0x88923959; +CHECKREG r6, 0x8000300D; +CHECKREG r7, 0x88923959; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +R0.H = ( A1 -= R1.L * R0.L ) (M), A0 += R1.L * R0.L (IS); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (IS); +R3 = A0.w; +R4.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H (IS); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (M), A0 += R6.L * R7.H (IS); +R7 = A0.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0x89012A6E; +CHECKREG r2, 0x80005679; +CHECKREG r3, 0x000317FC; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0x2B3160AC; +CHECKREG r6, 0x8000A00D; +CHECKREG r7, 0xCAD78046; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xc1845679; +imm32 r3, 0x1c080007; +imm32 r4, 0xe1cc8569; +imm32 r5, 0x921c080b; +imm32 r6, 0x7901908d; +imm32 r7, 0x679e9008; +R0.H = ( A1 -= R1.L * R0.L ) (M,IS); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M,IS); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (M,IS); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (M,IS); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0x457EF719; +CHECKREG r2, 0x80005679; +CHECKREG r3, 0x3C070751; +CHECKREG r4, 0x80008569; +CHECKREG r5, 0x3CF9F38D; +CHECKREG r6, 0x8000908D; +CHECKREG r7, 0x0BFFDDEF; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1_ih.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1_ih.s new file mode 100644 index 0000000..ae20990 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1_ih.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_ih/c_dsp32mac_dr_a1_ih.dsp +// Spec Reference: dsp32mac dr_a1 ih (int multiplication with word extraction) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x93545abd; +imm32 r1, 0x1dbcfec7; +imm32 r2, 0x52248679; +imm32 r3, 0xd6069007; +imm32 r4, 0xef7c4569; +imm32 r5, 0xcd38500b; +imm32 r6, 0xe00c900d; +imm32 r7, 0xf78e990f; +R0.H = ( A1 = R1.L * R0.L ), A0 -= R1.L * R0.L (IH); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ), A0 -= R2.H * R3.L (IH); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IH); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ), A0 = R6.L * R7.H (IH); +R7 = A1.w; +CHECKREG r0, 0xFF915ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x137E8679; +CHECKREG r3, 0x137E5BC1; +CHECKREG r4, 0x18A84569; +CHECKREG r5, 0x18A8516D; +CHECKREG r6, 0x010E900D; +CHECKREG r7, 0x010DDAA8; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0x83548abd; +imm32 r1, 0x76bcfec7; +imm32 r2, 0xa1745679; +imm32 r3, 0xb0269007; +imm32 r4, 0xcfb34569; +imm32 r5, 0xd235600b; +imm32 r6, 0xe00ca70d; +imm32 r7, 0x678e708f; +R0.H = ( A1 -= R1.L * R0.L ) (IH); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (IH); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (IH); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (IH); +R7 = A1.w; +CHECKREG r0, 0x007E8ABD; +CHECKREG r1, 0x007E7BBD; +CHECKREG r2, 0xE5865679; +CHECKREG r3, 0xE58581B3; +CHECKREG r4, 0xEDE14569; +CHECKREG r5, 0xEDE10CB1; +CHECKREG r6, 0xFACEA70D; +CHECKREG r7, 0xFACDF209; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x9dbcdec7; +imm32 r2, 0x7724e679; +imm32 r3, 0x80567007; +imm32 r4, 0x9fb34569; +imm32 r5, 0xa235200b; +imm32 r6, 0xb00c100d; +imm32 r7, 0x9876a10f; + R0.H = A1 , A0 = R1.L * R0.L (IH); +R1 = A1.w; + R2.H = A1 , A0 += R2.H * R3.L (IH); +R3 = A1.w; + R4.H = A1 , A0 -= R4.H * R5.H (IH); +R5 = A1.w; + R6.H = A1 , A0 += R6.L * R7.H (IH); +R7 = A1.w; +CHECKREG r0, 0xFACEBABD; +CHECKREG r1, 0xFACDF209; +CHECKREG r2, 0xFACEE679; +CHECKREG r3, 0xFACDF209; +CHECKREG r4, 0xFACE4569; +CHECKREG r5, 0xFACDF209; +CHECKREG r6, 0xFACE100D; +CHECKREG r7, 0xFACDF209; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x9dbcfec7; +imm32 r2, 0x81245679; +imm32 r3, 0x97060007; +imm32 r4, 0xaf6c4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00c400d; +imm32 r7, 0x678ed30f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 -= R1.L * R0.L (IH); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M), A0 += R2.H * R3.L (IH); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (M), A0 += R4.H * R5.H (IH); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M), A0 -= R6.L * R7.H (IH); +R7 = A1.w; +CHECKREG r0, 0xFF915ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x32945679; +CHECKREG r3, 0x329474C1; +CHECKREG r4, 0xD2A94569; +CHECKREG r5, 0xD2A949A4; +CHECKREG r6, 0xE621400D; +CHECKREG r7, 0xE6215AA8; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x92005ABD; +imm32 r1, 0x09300000; +imm32 r2, 0x56749679; +imm32 r3, 0x30A95000; +imm32 r4, 0xa0009669; +imm32 r5, 0x01000970; +imm32 r6, 0xdf45609D; +imm32 r7, 0x12345679; +R0.H = ( A1 -= R1.L * R0.L ) (M,IH); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M,IH); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (M,IH); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ) (M,IH); +R7 = A1.w; +CHECKREG r0, 0xE6215ABD; +CHECKREG r1, 0xE6215AA8; +CHECKREG r2, 0xD2129679; +CHECKREG r3, 0xD2126089; +CHECKREG r4, 0xFC769669; +CHECKREG r5, 0xFC760000; +CHECKREG r6, 0xFA22609D; +CHECKREG r7, 0xFA223404; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1_is.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1_is.s new file mode 100644 index 0000000..2d97468 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1_is.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_is/c_dsp32mac_dr_a1_is.dsp +// Spec Reference: dsp32mac dr_a1 is ((scale by 2 signed int) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbdbcfec7; +imm32 r2, 0xc1248679; +imm32 r3, 0xd0069007; +imm32 r4, 0xefbc4569; +imm32 r5, 0xcd35500b; +imm32 r6, 0xe00c800d; +imm32 r7, 0xf78e900f; +R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (ISS2); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (ISS2); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (ISS2); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (ISS2); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x80008679; +CHECKREG r3, 0xE8CA9815; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0xE3B4A529; +CHECKREG r6, 0x8000800D; +CHECKREG r7, 0xE4C27FD1; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0x63548abd; +imm32 r1, 0x7dbcfec7; +imm32 r2, 0xC5885679; +imm32 r3, 0xC5880000; +imm32 r4, 0xcfbc4569; +imm32 r5, 0xd235c00b; +imm32 r6, 0xe00ca00d; +imm32 r7, 0x678e700f; +R0.H = ( A1 = R1.L * R0.L ) (ISS2); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (ISS2); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (ISS2); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (ISS2); +R7 = A1.w; +CHECKREG r0, 0x7FFF8ABD; +CHECKREG r1, 0x008F5EEB; +CHECKREG r2, 0x80005679; +CHECKREG r3, 0xECCF6C33; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0xE0C07F1F; +CHECKREG r6, 0x8000A00D; +CHECKREG r7, 0xEDAD6477; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x6dbcdec7; +imm32 r2, 0x7124e679; +imm32 r3, 0x80067007; +imm32 r4, 0x9fbc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb00c300d; +imm32 r7, 0xc78ea00f; + R0.H = A1 , A0 -= R1.L * R0.L (ISS2); +R1 = A1.w; + R2.H = A1 , A0 += R2.H * R3.L (ISS2); +R3 = A1.w; + R4.H = A1 , A0 -= R4.H * R5.H (ISS2); +R5 = A1.w; + R6.H = A1 , A0 = R6.L * R7.H (ISS2); +R7 = A1.w; +CHECKREG r0, 0x8000BABD; +CHECKREG r1, 0xEDAD6477; +CHECKREG r2, 0x8000E679; +CHECKREG r3, 0xEDAD6477; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0xEDAD6477; +CHECKREG r6, 0x8000300D; +CHECKREG r7, 0xEDAD6477; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (ISS2); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (ISS2); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (ISS2); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (ISS2); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x7FFF5679; +CHECKREG r3, 0x303725C1; +CHECKREG r4, 0x7FFF4569; +CHECKREG r5, 0x5D60D8AD; +CHECKREG r6, 0x7FFFA00D; +CHECKREG r7, 0x43823355; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x92005ABD; +imm32 r1, 0x09300000; +imm32 r2, 0x56749679; +imm32 r3, 0x30A95000; +imm32 r4, 0xa0009669; +imm32 r5, 0x01000970; +imm32 r6, 0xdf45609D; +imm32 r7, 0x12345679; +R0.H = ( A1 += R1.L * R0.L ) (M,ISS2); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M,ISS2); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (M,ISS2); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M,ISS2); +R7 = A1.w; +CHECKREG r0, 0x7FFF5ABD; +CHECKREG r1, 0x43823355; +CHECKREG r2, 0x7FFF9679; +CHECKREG r3, 0x57912D74; +CHECKREG r4, 0x7FFF9669; +CHECKREG r5, 0x5B1B2D74; +CHECKREG r6, 0x8000609D; +CHECKREG r7, 0xFDAC3404; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1_iu.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1_iu.s new file mode 100644 index 0000000..8f36ac3 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1_iu.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_iu/c_dsp32mac_dr_a1_iu.dsp +// Spec Reference: dsp32mac dr_a1 iu (unsigned integer) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x93545abd; +imm32 r1, 0x7890afc7; +imm32 r2, 0x52248679; +imm32 r3, 0xd5069007; +imm32 r4, 0xef5c4569; +imm32 r5, 0xcd35500b; +imm32 r6, 0xe00c500d; +imm32 r7, 0xf78e950f; +R0.H = ( A1 = R1.L * R0.L ), A0 += R1.L * R0.L (IU); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ), A0 = R2.H * R3.L (IU); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ), A0 += R4.H * R5.H (IU); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ), A0 -= R6.L * R7.H (IU); +R7 = A1.w; +CHECKREG r0, 0xFFFF5ABD; +CHECKREG r1, 0x3E4DBBEB; +CHECKREG r2, 0xFFFF8679; +CHECKREG r3, 0xAE338FC1; +CHECKREG r4, 0xFFFF4569; +CHECKREG r5, 0xF90A98B5; +CHECKREG r6, 0xFFFF500D; +CHECKREG r7, 0x2062BE0D; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0xd3548abd; +imm32 r1, 0x9dbcfec7; +imm32 r2, 0xa9d45679; +imm32 r3, 0xb09d9007; +imm32 r4, 0xcfb9d569; +imm32 r5, 0xd2359d0b; +imm32 r6, 0xe00ca90d; +imm32 r7, 0x678e709f; +R0.H = ( A1 += R1.L * R0.L ) (IU); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (IU); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (IU); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (IU); +R7 = A1.w; +CHECKREG r0, 0xFFFF8ABD; +CHECKREG r1, 0xAA761CF8; +CHECKREG r2, 0xFFFF5679; +CHECKREG r3, 0x6ECDE4C3; +CHECKREG r4, 0xFFFFD569; +CHECKREG r5, 0x7F6D61F3; +CHECKREG r6, 0xFFFFA90D; +CHECKREG r7, 0x24CC474B; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0xa354babd; +imm32 r1, 0x9abcdec7; +imm32 r2, 0x77a4e679; +imm32 r3, 0x805a7007; +imm32 r4, 0x9fb3a569; +imm32 r5, 0xa2352a0b; +imm32 r6, 0xb00c10ad; +imm32 r7, 0x9876a10a; + R0.H = A1 , A0 -= R1.L * R0.L (IU); +R1 = A1.w; + R2.H = A1 , A0 += R2.H * R3.L (IU); +R3 = A1.w; + R4.H = A1 , A0 = R4.H * R5.H (IU); +R5 = A1.w; + R6.H = A1 , A0 -= R6.L * R7.H (IU); +R7 = A1.w; +CHECKREG r0, 0xFFFFBABD; +CHECKREG r1, 0x24CC474B; +CHECKREG r2, 0xFFFFE679; +CHECKREG r3, 0x24CC474B; +CHECKREG r4, 0xFFFFA569; +CHECKREG r5, 0x24CC474B; +CHECKREG r6, 0xFFFF10AD; +CHECKREG r7, 0x24CC474B; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x9dbcfec7; +imm32 r2, 0x81245679; +imm32 r3, 0x97060007; +imm32 r4, 0xaf6c4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00c400d; +imm32 r7, 0x678ed30f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (IU); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (IU); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (M), A0 -= R4.H * R5.H (IU); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (IU); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x80005679; +CHECKREG r3, 0xCC8DA915; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0xD2A949A4; +CHECKREG r6, 0x8000400D; +CHECKREG r7, 0xB8CAA44C; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0xe2005ABD; +imm32 r1, 0x0e300000; +imm32 r2, 0x56e49679; +imm32 r3, 0x30Ae5000; +imm32 r4, 0xa000e669; +imm32 r5, 0x01000e70; +imm32 r6, 0xdf4560eD; +imm32 r7, 0x1234567e; +R0.H = ( A1 -= R1.L * R0.L ) (M,IU); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M,IU); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (M,IU); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (M,IU); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xB8CAA44C; +CHECKREG r2, 0x80009679; +CHECKREG r3, 0xA4B99A8A; +CHECKREG r4, 0x8000E669; +CHECKREG r5, 0xAA239A8A; +CHECKREG r6, 0x800060ED; +CHECKREG r7, 0xAC776686; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1_m.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1_m.s new file mode 100644 index 0000000..b44d5e6 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1_m.s @@ -0,0 +1,206 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_m/c_dsp32mac_dr_a1_m.dsp +// Spec Reference: dsp32mac dr a1 m +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xab235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246700f; + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R0.H = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L; +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L; +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H; +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H; +R7 = A1.w; +CHECKREG r0, 0xFF225ABD; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0x00045679; +CHECKREG r3, 0x00040DAC; +CHECKREG r4, 0xFFFF4569; +CHECKREG r5, 0xFFFE9A28; +CHECKREG r6, 0x0008000D; +CHECKREG r7, 0x00084F78; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R0.H = ( A1 += R1.L * R0.L ); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ); +R7 = A1.w; +CHECKREG r0, 0xFF2A5ABD; +CHECKREG r1, 0xFF2A6D4E; +CHECKREG r2, 0x00045679; +CHECKREG r3, 0x00040DAC; +CHECKREG r4, 0x00034569; +CHECKREG r5, 0x0002A7D4; +CHECKREG r6, 0x000A000D; +CHECKREG r7, 0x0009B550; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; + R0.H = A1 , A0 += R1.L * R0.L; +R1 = A1.w; + R2.H = A1 , A0 = R2.H * R3.L; +R3 = A1.w; + R4.H = A1 , A0 = R4.H * R5.H; +R5 = A1.w; + R6.H = A1 , A0 += R6.L * R7.H; +R7 = A1.w; +CHECKREG r0, 0x000A5ABD; +CHECKREG r1, 0x0009B550; +CHECKREG r2, 0x000A5679; +CHECKREG r3, 0x0009B550; +CHECKREG r4, 0x000A4569; +CHECKREG r5, 0x0009B550; +CHECKREG r6, 0x000A000D; +CHECKREG r7, 0x0009B550; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R4.H = ( A1 += R1.L * R0.L ) (M), A0 = R1.L * R0.L; +R5 = A1.w; +R6.H = ( A1 = R2.L * R3.H ) (M), A0 += R2.H * R3.L; +R7 = A1.w; +R0.H = ( A1 = R4.H * R5.L ) (M), A0 = R4.H * R5.H; +R1 = A1.w; +R2.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H; +R3 = A1.w; +CHECKREG r0, 0xFFB35ABD; +CHECKREG r1, 0xFFB294B9; +CHECKREG r2, 0x00005679; +CHECKREG r3, 0x00000004; +CHECKREG r4, 0xFF9B4569; +CHECKREG r5, 0xFF9AC43B; +CHECKREG r6, 0x0002000D; + +CHECKREG r7, 0x000206D6; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xc1845679; +imm32 r3, 0x1c080007; +imm32 r4, 0xe1cc8569; +imm32 r5, 0x121c080b; +imm32 r6, 0x7001008d; +imm32 r7, 0x678e1008; +R6.H = ( A1 += R1.L * R0.L ) (M); +R7 = A1.w; +R2.H = ( A1 = R2.L * R3.H ) (M); +R3 = A1.w; +R0.H = ( A1 += R4.H * R5.L ) (M); +R1 = A1.w; +R4.H = ( A1 = R6.H * R7.H ) (M); +R5 = A1.w; +CHECKREG r0, 0x08855ABD; +CHECKREG r1, 0x0885038C; +CHECKREG r2, 0x09785679; +CHECKREG r3, 0x0977EFC8; +CHECKREG r4, 0xFF918569; +CHECKREG r5, 0xFF913021; +CHECKREG r6, 0xFF91008D; +CHECKREG r7, 0xFF910EEF; + +imm32 r0, 0x03545abd; +imm32 r1, 0xa0bcfec7; +imm32 r2, 0xa1045679; +imm32 r3, 0x00000007; +imm32 r4, 0xefbc0569; +imm32 r5, 0x1235100b; +imm32 r6, 0x000c020d; +imm32 r7, 0x678e003f; +R4.H = ( A1 -= R1.L * R0.L ) (M), A0 -= R1.L * R0.L; +R5 = A1.w; +R6.H = ( A1 -= R2.L * R3.H ) (M), A0 += R2.H * R3.L; +R7 = A1.w; +R0.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H; +R1 = A1.w; +R2.H = ( A1 -= R6.H * R7.H ) (M), A0 -= R6.L * R7.H; +R3 = A1.w; +CHECKREG r0, 0x00005ABD; +CHECKREG r1, 0x00002136; +CHECKREG r2, 0x00005679; +CHECKREG r3, 0x00002136; +CHECKREG r4, 0x00000569; +CHECKREG r5, 0x00002136; +CHECKREG r6, 0x0000020D; +CHECKREG r7, 0x00002136; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xc1845679; +imm32 r3, 0x1c080007; +imm32 r4, 0xe1cc8569; +imm32 r5, 0x121c080b; +imm32 r6, 0x7001008d; +imm32 r7, 0x678e1008; +R6.H = ( A1 -= R1.L * R0.L ) (M); +R7 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M); +R3 = A1.w; +R0.H = ( A1 -= R4.H * R5.L ) (M); +R1 = A1.w; +R4.H = ( A1 -= R6.H * R7.H ) (M); +R5 = A1.w; +CHECKREG r0, 0xF7EA5ABD; +CHECKREG r1, 0xF7EA0EBF; +CHECKREG r2, 0xF6F75679; +CHECKREG r3, 0xF6F72283; +CHECKREG r4, 0xF7EA8569; +CHECKREG r5, 0xF7E9DE9E; +CHECKREG r6, 0x006F008D; +CHECKREG r7, 0x006F124B; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1_s.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1_s.s new file mode 100644 index 0000000..1059673 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1_s.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_s/c_dsp32mac_dr_a1_s.dsp +// Spec Reference: dsp32mac dr_a1 s (scale by 2 signed fraction with round) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbabcfec7; +imm32 r2, 0xc1a48679; +imm32 r3, 0xd00a9007; +imm32 r4, 0xefbca569; +imm32 r5, 0xcd355a0b; +imm32 r6, 0xe00c80ad; +imm32 r7, 0xf78e900a; +R0.H = ( A1 -= R1.L * R0.L ), A0 += R1.L * R0.L (S2RND); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ), A0 -= R2.H * R3.L (S2RND); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ), A0 = R4.H * R5.H (S2RND); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ), A0 -= R6.L * R7.H (S2RND); +R7 = A1.w; +CHECKREG r0, 0x01BC5ABD; +CHECKREG r1, 0x00DDE22A; +CHECKREG r2, 0x5CCE8679; +CHECKREG r3, 0x2E67039E; +CHECKREG r4, 0xE91EA569; +CHECKREG r5, 0xF48ECA28; +CHECKREG r6, 0xED5580AD; +CHECKREG r7, 0xF6AA7F78; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0x63bb8abd; +imm32 r1, 0xbdbcfec7; +imm32 r2, 0xab245679; +imm32 r3, 0xb0b69007; +imm32 r4, 0xcfbb4569; +imm32 r5, 0xd235b00b; +imm32 r6, 0xe00cab0d; +imm32 r7, 0x678e70bf; +R0.H = ( A1 += R1.L * R0.L ) (S2RND); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (S2RND); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ) (S2RND); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (S2RND); +R7 = A1.w; +CHECKREG r0, 0xEF928ABD; +CHECKREG r1, 0xF7C93D4E; +CHECKREG r2, 0x5AB45679; +CHECKREG r3, 0x2D59E942; +CHECKREG r4, 0x7FFF4569; +CHECKREG r5, 0x4B80E354; +CHECKREG r6, 0xCC4CAB0D; +CHECKREG r7, 0xE6263550; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0x5c54babd; +imm32 r1, 0x6dccdec7; +imm32 r2, 0xc12ce679; +imm32 r3, 0x8c06c007; +imm32 r4, 0x9fcc4c69; +imm32 r5, 0xa23c90cb; +imm32 r6, 0xb00cc00c; +imm32 r7, 0xc78eac0f; + R0.H = A1 , A0 -= R1.L * R0.L (S2RND); +R1 = A1.w; + R2.H = A1 , A0 += R2.H * R3.L (S2RND); +R3 = A1.w; + R4.H = A1 , A0 = R4.H * R5.H (S2RND); +R5 = A1.w; + R6.H = A1 , A0 += R6.L * R7.H (S2RND); +R7 = A1.w; +CHECKREG r0, 0xCC4CBABD; +CHECKREG r1, 0xE6263550; +CHECKREG r2, 0xCC4CE679; +CHECKREG r3, 0xE6263550; +CHECKREG r4, 0xCC4C4C69; +CHECKREG r5, 0xE6263550; +CHECKREG r6, 0xCC4CC00C; +CHECKREG r7, 0xE6263550; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x3d545abd; +imm32 r1, 0x5ddcfec7; +imm32 r2, 0x712d5679; +imm32 r3, 0x9006d007; +imm32 r4, 0xafbc4d69; +imm32 r5, 0xd23590db; +imm32 r6, 0xd00ca00d; +imm32 r7, 0x6d8ed00f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (S2RND); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ) (M), A0 -= R2.H * R3.L (S2RND); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (S2RND); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (S2RND); +R7 = A1.w; +CHECKREG r0, 0xFF225ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x614C5679; +CHECKREG r3, 0x30A616D6; +CHECKREG r4, 0x06764D69; +CHECKREG r5, 0x033B2CAA; +CHECKREG r6, 0xDD6BA00D; +CHECKREG r7, 0xEEB5AF52; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83e45abd; +imm32 r1, 0xe8befec7; +imm32 r2, 0xce84e679; +imm32 r3, 0x1ce80e07; +imm32 r4, 0xe1ce85e9; +imm32 r5, 0x921ce80e; +imm32 r6, 0x79019e8d; +imm32 r7, 0x679e90e8; +R0.H = ( A1 += R1.L * R0.L ) (M,S2RND); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ) (M,S2RND); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ) (M,S2RND); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (M,S2RND); +R7 = A1.w; +CHECKREG r0, 0xDC8D5ABD; +CHECKREG r1, 0xEE46BE3D; +CHECKREG r2, 0xFA3CE679; +CHECKREG r3, 0xFD1E19A8; +CHECKREG r4, 0xC37E85E9; +CHECKREG r5, 0xE1BF22EC; +CHECKREG r6, 0x80009E8D; +CHECKREG r7, 0xB0C50D4E; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1_t.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1_t.s new file mode 100644 index 0000000..7dc3925 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1_t.s @@ -0,0 +1,274 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_t/c_dsp32mac_dr_a1_t.dsp +// Spec Reference: dsp32mac dr a1 t (truncation) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbdbcfec7; +imm32 r2, 0xc1248679; +imm32 r3, 0xd0069007; +imm32 r4, 0xefbc4569; +imm32 r5, 0xcd35500b; +imm32 r6, 0xe00c800d; +imm32 r7, 0xf78e900f; +R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (T); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (T); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (T); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (T); +R7 = A1.w; +CHECKREG r0, 0xFF225ABD; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0x2D8C8679; +CHECKREG r3, 0x2D8CEDAC; +CHECKREG r4, 0xF5D44569; +CHECKREG r5, 0xF5D41A28; +CHECKREG r6, 0x021B800D; +CHECKREG r7, 0x021BB550; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x63548abd; +imm32 r1, 0x7dbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0xb0069007; +imm32 r4, 0xcfbc4569; +imm32 r5, 0xd235c00b; +imm32 r6, 0xe00ca00d; +imm32 r7, 0x678e700f; +R0.H = ( A1 = R1.L * R0.L ) (T); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (T); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (T); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (T); +R7 = A1.w; +CHECKREG r0, 0x011E8ABD; +CHECKREG r1, 0x011EBDD6; +CHECKREG r2, 0xCB175679; +CHECKREG r3, 0xCB172B82; +CHECKREG r4, 0x181D4569; +CHECKREG r5, 0x181DDA28; +CHECKREG r6, 0xE626A00D; +CHECKREG r7, 0xE6263550; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x6dbcdec7; +imm32 r2, 0x7124e679; +imm32 r3, 0x80067007; +imm32 r4, 0x9fbc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb00c300d; +imm32 r7, 0xc78ea00f; + R0.H = A1 , A0 = R1.L * R0.L (T); +R1 = A1.w; + R2.H = A1 , A0 = R2.H * R3.L (T); +R3 = A1.w; + R4.H = A1 , A0 = R4.H * R5.H (T); +R5 = A1.w; + R6.H = A1 , A0 += R6.L * R7.H (T); +R7 = A1.w; +CHECKREG r0, 0xE626BABD; +CHECKREG r1, 0xE6263550; +CHECKREG r2, 0xE626E679; +CHECKREG r3, 0xE6263550; +CHECKREG r4, 0xE6264569; +CHECKREG r5, 0xE6263550; +CHECKREG r6, 0xE626300D; +CHECKREG r7, 0xE6263550; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (T); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M), A0 = R2.H * R3.L (T); +R3 = A0.w; +R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (T); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H (T); +R7 = A0.w; +CHECKREG r0, 0xFF915ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x30375679; +CHECKREG r3, 0x00062FF8; +CHECKREG r4, 0x030D4569; +CHECKREG r5, 0x030D72D5; +CHECKREG r6, 0xE621A00D; +CHECKREG r7, 0xCF173844; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xc1845679; +imm32 r3, 0x1c080007; +imm32 r4, 0xe1cc8569; +imm32 r5, 0x921c080b; +imm32 r6, 0x7901908d; +imm32 r7, 0x679e9008; +R0.H = ( A1 += R1.L * R0.L ) (M,T); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ) (M,T); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ) (M,T); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M,T); +R7 = A1.w; +CHECKREG r0, 0xE5B25ABD; +CHECKREG r1, 0xE5B26993; +CHECKREG r2, 0x09775679; +CHECKREG r3, 0x0977EFC8; +CHECKREG r4, 0x08858569; +CHECKREG r5, 0x0885038C; +CHECKREG r6, 0x30FA908D; +CHECKREG r7, 0x30FA159E; + +imm32 r0, 0x03545abd; +imm32 r1, 0xb0bcfec7; +imm32 r2, 0xc1048679; +imm32 r3, 0xd0009007; +imm32 r4, 0xefbc0569; +imm32 r5, 0xcd35510b; +imm32 r6, 0xe00c802d; +imm32 r7, 0xf78e9003; +R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L (T); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L (T); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (T); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ), A0 -= R6.L * R7.H (T); +R7 = A1.w; +CHECKREG r0, 0x31D75ABD; +CHECKREG r1, 0x31D7F7C8; +CHECKREG r2, 0x2D928679; +CHECKREG r3, 0x2D92A000; +CHECKREG r4, 0x37DF0569; +CHECKREG r5, 0x37DF0DD8; +CHECKREG r6, 0x39FA802D; +CHECKREG r7, 0x39FAC328; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x63548abd; +imm32 r1, 0x7dbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0xb0069007; +imm32 r4, 0xcfbc4569; +imm32 r5, 0xd235c00b; +imm32 r6, 0xe00ca00d; +imm32 r7, 0x678e700f; +R0.H = ( A1 -= R1.L * R0.L ) (T); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (T); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (T); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (T); +R7 = A1.w; +CHECKREG r0, 0x38DC8ABD; +CHECKREG r1, 0x38DC0552; +CHECKREG r2, 0x6EE35679; +CHECKREG r3, 0x6EE397A6; +CHECKREG r4, 0x56C54569; +CHECKREG r5, 0x56C5BD7E; +CHECKREG r6, 0x709FA00D; +CHECKREG r7, 0x709F882E; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x6dbcdec7; +imm32 r2, 0x7124e679; +imm32 r3, 0x80067007; +imm32 r4, 0x9fbc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb00c300d; +imm32 r7, 0xc78ea00f; + R0.H = A1 , A0 -= R1.L * R0.L (T); +R1 = A1.w; + R2.H = A1 , A0 -= R2.H * R3.L (T); +R3 = A1.w; + R4.H = A1 , A0 -= R4.H * R5.H (T); +R5 = A1.w; + R6.H = A1 , A0 -= R6.L * R7.H (T); +R7 = A1.w; +CHECKREG r0, 0x709FBABD; +CHECKREG r1, 0x709F882E; +CHECKREG r2, 0x709FE679; +CHECKREG r3, 0x709F882E; +CHECKREG r4, 0x709F4569; +CHECKREG r5, 0x709F882E; +CHECKREG r6, 0x709F300D; +CHECKREG r7, 0x709F882E; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +R0.H = ( A1 -= R1.L * R0.L ) (M), A0 += R1.L * R0.L (T); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M), A0 -= R2.H * R3.L (T); +R3 = A0.w; +R4.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H (T); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (T); +R7 = A0.w; +CHECKREG r0, 0x710E5ABD; +CHECKREG r1, 0x710E7943; +CHECKREG r2, 0x40685679; +CHECKREG r3, 0x1ED0EB56; +CHECKREG r4, 0x133E4569; +CHECKREG r5, 0x133EAF81; +CHECKREG r6, 0xF960A00D; +CHECKREG r7, 0x4FB9B312; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xc1845679; +imm32 r3, 0x1c080007; +imm32 r4, 0xe1cc8569; +imm32 r5, 0x921c080b; +imm32 r6, 0x7901908d; +imm32 r7, 0x679e9008; +R0.H = ( A1 -= R1.L * R0.L ) (M,T); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M,T); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (M,T); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (M,T); +R7 = A1.w; +CHECKREG r0, 0xF9CE5ABD; +CHECKREG r1, 0xF9CEFB3E; +CHECKREG r2, 0xF0575679; +CHECKREG r3, 0xF0570B76; +CHECKREG r4, 0xF1498569; +CHECKREG r5, 0xF149F7B2; +CHECKREG r6, 0xC04F908D; +CHECKREG r7, 0xC04FE214; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1_tu.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1_tu.s new file mode 100644 index 0000000..259def7 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1_tu.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_tu/c_dsp32mac_dr_a1_tu.dsp +// Spec Reference: dsp32mac dr_a1 tu (truncate signed fraction) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbdbcfec7; +imm32 r2, 0xc1248679; +imm32 r3, 0xd0069007; +imm32 r4, 0xefbc4569; +imm32 r5, 0xcd35500b; +imm32 r6, 0xe00c800d; +imm32 r7, 0xf78e900f; +R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (TFU); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (TFU); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (TFU); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (TFU); +R7 = A1.w; +CHECKREG r0, 0x5A4E5ABD; +CHECKREG r1, 0x5A4E0EEB; +CHECKREG r2, 0x00008679; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x4AF54569; +CHECKREG r5, 0x4AF50D14; +CHECKREG r6, 0xFFFF800D; +CHECKREG r7, 0x239CE7BC; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0x63548abd; +imm32 r1, 0x7dbcfec7; +imm32 r2, 0xC5885679; +imm32 r3, 0xC5880000; +imm32 r4, 0xcfbc4569; +imm32 r5, 0xd235c00b; +imm32 r6, 0xe00ca00d; +imm32 r7, 0x678e700f; +R0.H = ( A1 = R1.L * R0.L ) (TFU); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (TFU); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (TFU); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (TFU); +R7 = A1.w; +CHECKREG r0, 0x8A138ABD; +CHECKREG r1, 0x8A135EEB; +CHECKREG r2, 0xCCCC5679; +CHECKREG r3, 0xCCCC6C33; +CHECKREG r4, 0x30F64569; +CHECKREG r5, 0x30F67F1F; +CHECKREG r6, 0x5AA1A00D; +CHECKREG r7, 0x5AA11AA8; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x6dbcdec7; +imm32 r2, 0x7124e679; +imm32 r3, 0x80067007; +imm32 r4, 0x9fbc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb00c300d; +imm32 r7, 0xc78ea00f; + R0.H = A1 , A0 -= R1.L * R0.L (TFU); +R1 = A1.w; + R2.H = A1 , A0 += R2.H * R3.L (TFU); +R3 = A1.w; + R4.H = A1 , A0 -= R4.H * R5.H (TFU); +R5 = A1.w; + R6.H = A1 , A0 = R6.L * R7.H (TFU); +R7 = A1.w; +CHECKREG r0, 0x5AA1BABD; +CHECKREG r1, 0x5AA11AA8; +CHECKREG r2, 0x5AA1E679; +CHECKREG r3, 0x5AA11AA8; +CHECKREG r4, 0x5AA14569; +CHECKREG r5, 0x5AA11AA8; +CHECKREG r6, 0x5AA1300D; +CHECKREG r7, 0x5AA11AA8; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 -= R1.L * R0.L (TFU); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (TFU); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (TFU); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (TFU); +R7 = A1.w; +CHECKREG r0, 0xFF915ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x30375679; +CHECKREG r3, 0x303725C1; +CHECKREG r4, 0x5D604569; +CHECKREG r5, 0x5D60D8AD; +CHECKREG r6, 0x4382A00D; +CHECKREG r7, 0x43823355; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x92005ABD; +imm32 r1, 0x09300000; +imm32 r2, 0x56749679; +imm32 r3, 0x30A95000; +imm32 r4, 0xa0009669; +imm32 r5, 0x01000970; +imm32 r6, 0xdf45609D; +imm32 r7, 0x12345679; +R0.H = ( A1 += R1.L * R0.L ) (M,TFU); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M,TFU); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (M,TFU); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (M,TFU); +R7 = A1.w; +CHECKREG r0, 0x43825ABD; +CHECKREG r1, 0x43823355; +CHECKREG r2, 0x57919679; +CHECKREG r3, 0x57912D74; +CHECKREG r4, 0xFC769669; +CHECKREG r5, 0xFC760000; +CHECKREG r6, 0xFEC9609D; +CHECKREG r7, 0xFEC9CBFC; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1_u.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1_u.s new file mode 100644 index 0000000..1f78e34 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1_u.s @@ -0,0 +1,170 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_u/c_dsp32mac_dr_a1_u.dsp +// Spec Reference: dsp32mac dr_a1 u (unsigned fraction & unsigned int) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbabcfec7; +imm32 r2, 0xc1a48679; +imm32 r3, 0xd00a9007; +imm32 r4, 0xefbca569; +imm32 r5, 0xcd355a0b; +imm32 r6, 0xe00c80ad; +imm32 r7, 0xf78e900a; +R0.H = ( A1 = R6.L * R7.L ), A0 += R6.L * R7.L (FU); +R1 = A1.w; +R2.H = ( A1 = R3.L * R4.H ), A0 = R3.H * R4.L (FU); +R3 = A1.w; +R4.H = ( A1 += R2.H * R5.L ), A0 = R2.H * R5.H (FU); +R5 = A1.w; +R6.H = ( A1 += R0.H * R1.H ), A0 += R0.L * R1.H (FU); +R7 = A1.w; +CHECKREG r0, 0x48665ABD; +CHECKREG r1, 0x486656C2; +CHECKREG r2, 0x86E08679; +CHECKREG r3, 0x86E04E24; +CHECKREG r4, 0xB651A569; +CHECKREG r5, 0xB650D9C4; +CHECKREG r6, 0xCACA80AD; +CHECKREG r7, 0xCACA6268; + +imm32 r0, 0x03545abd; +imm32 r1, 0x1abcfec7; +imm32 r2, 0xc2a48679; +imm32 r3, 0x300a9007; +imm32 r4, 0x54bca569; +imm32 r5, 0x6d355a0b; +imm32 r6, 0x700c80ad; +imm32 r7, 0x878e900a; +R0.H = ( A1 -= R6.L * R7.L ), A0 += R6.L * R7.L (FU); +R1 = A1.w; +R2.H = ( A1 -= R3.L * R4.H ), A0 = R3.H * R4.L (FU); +R3 = A1.w; +R4.H = ( A1 += R2.H * R5.L ), A0 -= R2.H * R5.H (FU); +R5 = A1.w; +R6.H = ( A1 -= R0.H * R1.H ), A0 += R0.L * R1.H (FU); +R7 = A1.w; +CHECKREG r0, 0x82645ABD; +CHECKREG r1, 0x82640BA6; +CHECKREG r2, 0x52B88679; +CHECKREG r3, 0x52B7FA82; +CHECKREG r4, 0x6FD0A569; +CHECKREG r5, 0x6FD0386A; +CHECKREG r6, 0x2D6780AD; +CHECKREG r7, 0x2D66815A; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0xb3548abd; +imm32 r1, 0x7bbcfec7; +imm32 r2, 0xa1b45679; +imm32 r3, 0xb00b9007; +imm32 r4, 0xcfbcb569; +imm32 r5, 0xd235c00b; +imm32 r6, 0xe00cabbd; +imm32 r7, 0x678e700b; +R0.H = ( A1 = R1.L * R0.L ) (FU); +R1 = A1.w; +R2.H = ( A1 = R2.L * R6.H ) (FU); +R3 = A1.w; +R4.H = ( A1 += R3.H * R5.L ) (FU); +R5 = A1.w; +R6.H = ( A1 = R4.H * R7.H ) (FU); +R7 = A1.w; +CHECKREG r0, 0x8A138ABD; +CHECKREG r1, 0x8A135EEB; +CHECKREG r2, 0x4BAE5679; +CHECKREG r3, 0x4BADEDAC; +CHECKREG r4, 0x8473B569; +CHECKREG r5, 0x8472EE1B; +CHECKREG r6, 0x3594ABBD; +CHECKREG r7, 0x3593BCCA; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0xc354babd; +imm32 r1, 0x6cbcdec7; +imm32 r2, 0x71c4e679; +imm32 r3, 0x800c7007; +imm32 r4, 0x9fbcc569; +imm32 r5, 0xa2359c0b; +imm32 r6, 0xb00c30cd; +imm32 r7, 0xc78ea00c; + R0.H = A1 , A0 = R1.L * R0.L (FU); +R1 = A1.w; + R2.H = A1 , A0 = R2.H * R3.L (FU); +R3 = A1.w; + R4.H = A1 , A0 = R4.H * R5.H (FU); +R5 = A1.w; + R6.H = A1 , A0 = R6.L * R7.H (FU); +R7 = A1.w; +CHECKREG r0, 0x3594BABD; +CHECKREG r1, 0x3593BCCA; +CHECKREG r2, 0x3594E679; +CHECKREG r3, 0x3593BCCA; +CHECKREG r4, 0x3594C569; +CHECKREG r5, 0x3593BCCA; +CHECKREG r6, 0x359430CD; +CHECKREG r7, 0x3593BCCA; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0xd3545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71d45679; +imm32 r3, 0x900d0007; +imm32 r4, 0xafbcd569; +imm32 r5, 0xd2359d0b; +imm32 r6, 0xc00ca0dd; +imm32 r7, 0x678ed00d; +R0.H = ( A1 = R1.L * R2.L ) (M), A0 += R1.L * R2.L (FU); +R1 = A1.w; +R2.H = ( A1 = R3.L * R4.H ) (M), A0 = R3.H * R4.L (FU); +R3 = A1.w; +R4.H = ( A1 = R5.H * R6.L ) (M), A0 += R5.H * R6.H (FU); +R5 = A1.w; +R6.H = ( A1 += R7.H * R0.H ) (M), A0 += R7.L * R0.H (FU); +R7 = A1.w; +CHECKREG r0, 0xFF965ABD; +CHECKREG r1, 0xFF96460F; +CHECKREG r2, 0x00055679; +CHECKREG r3, 0x0004CE24; +CHECKREG r4, 0xE33AD569; +CHECKREG r5, 0xE33997C1; +CHECKREG r6, 0x4A9DA0DD; +CHECKREG r7, 0x4A9CB6F5; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0xe3545abd; +imm32 r1, 0xaebcfec7; +imm32 r2, 0xc1e45679; +imm32 r3, 0x1c0e0007; +imm32 r4, 0xe1cce569; +imm32 r5, 0x921c0e0b; +imm32 r6, 0x790190ed; +imm32 r7, 0x679e900e; +R0.H = ( A1 = R1.L * R0.L ) (M,FU); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M,FU); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ) (M,FU); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M,FU); +R7 = A1.w; +CHECKREG r0, 0xFF915ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x090B5679; +CHECKREG r3, 0x090B0589; +CHECKREG r4, 0x0763E569; +CHECKREG r5, 0x0762E14D; +CHECKREG r6, 0x30FA90ED; +CHECKREG r7, 0x30FA159E; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1a0.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1a0.s new file mode 100644 index 0000000..e84f3d5 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1a0.s @@ -0,0 +1,157 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0/c_dsp32mac_dr_a1a0.dsp +// Spec Reference: dsp32mac dr_a1a0 +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + R0 = 0; + ASTAT = R0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x13545abd; + imm32 r1, 0xb2bcfec7; + imm32 r2, 0xc1348679; + imm32 r3, 0xd0049007; + imm32 r4, 0xefbc5569; + imm32 r5, 0xcd35560b; + imm32 r6, 0xe00c807d; + imm32 r7, 0xf78e9008; + A1 = A0 = 0; + R6.H = (A1 += R0.L * R0.L), R6.L = (A0 = R0.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 += R2.L * R3.L), R1.L = (A0 -= R2.H * R3.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 -= R4.L * R5.L), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R0.L * R7.L), R3.L = (A0 += R0.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0x13545ABD; + CHECKREG r1, 0x7FFF0964; + CHECKREG r2, 0x71380FD8; + CHECKREG r3, 0x21D909DC; + CHECKREG r4, 0x21D8C27A; + CHECKREG r5, 0x09DB89BE; + CHECKREG r6, 0x40534053; + CHECKREG r7, 0xF78E9008; + CHECKREG p1, 0x4052DF12; + CHECKREG p2, 0x4052DF12; + CHECKREG p3, 0xAAA259B0; + CHECKREG p4, 0x0963CE3A; + CHECKREG p5, 0x713876AA; + CHECKREG fp, 0x0FD82A12; + + imm32 r0, 0x13545abd; + imm32 r1, 0x22bcfec7; + imm32 r2, 0x43348679; + imm32 r3, 0x50049007; + imm32 r4, 0x6fbc5569; + imm32 r5, 0x7d35560b; + imm32 r6, 0x800c807d; + imm32 r7, 0xf98e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.L * R0.H), R0.L = (A0 = R1.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R6.H = (A1 += R2.L * R2.H), R6.L = (A0 -= R2.H * R2.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 -= R4.L * R5.H), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R3.L * R7.H), R3.L = (A0 -= R3.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0xFFD1FF22; + CHECKREG r1, 0x22BCFEC7; + CHECKREG r2, 0x80007FFF; + CHECKREG r3, 0x80007FFF; + CHECKREG r4, 0x721A320A; + CHECKREG r5, 0xA6989CC2; + CHECKREG r6, 0xC0033EF0; + CHECKREG r7, 0xF98E9008; + CHECKREG p1, 0xFFD0BC98; + CHECKREG p2, 0xFF221DD6; + CHECKREG p3, 0xC002B3C0; + CHECKREG p4, 0x3EF026AE; + CHECKREG p5, 0x6C76CC46; + CHECKREG fp, 0xAC3C0286; + + imm32 r0, 0x13545abd; + imm32 r1, 0x42bcfec7; + imm32 r2, 0x51348679; + imm32 r3, 0x60049007; + imm32 r4, 0x7fbc5569; + imm32 r5, 0x8d35560b; + imm32 r6, 0x900c807d; + imm32 r7, 0xa78e9008; + A1 = A0 = 0; + R0.H = (A1 -= R1.H * R0.L), R0.L = (A0 = R1.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 += R2.H * R3.L), R1.L = (A0 -= R2.H * R3.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 = R4.H * R5.L), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 -= R6.H * R7.L), R3.L = (A0 += R6.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0xD0B1FF22; + CHECKREG r1, 0x89A8462B; + CHECKREG r2, 0x55DDD39D; + CHECKREG r3, 0xF3EF2BB9; + CHECKREG r4, 0xF3EEC968; + CHECKREG r5, 0x2BB8C982; + CHECKREG r6, 0x900C807D; + CHECKREG r7, 0xA78E9008; + CHECKREG p1, 0xD0B14668; + CHECKREG p2, 0xFF221DD6; + CHECKREG p3, 0x89A83740; + CHECKREG p4, 0x462B2CFE; + CHECKREG p5, 0x55DD4A28; + CHECKREG fp, 0xD39D28D6; + + imm32 r0, 0x03545abd; + imm32 r1, 0xb3bcfec7; + imm32 r2, 0x24348679; + imm32 r3, 0x60049007; + imm32 r4, 0x7fbc5569; + imm32 r5, 0x9d35560b; + imm32 r6, 0xa00c807d; + imm32 r7, 0x078e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.H * R0.H), R0.L = (A0 -= R1.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 -= R2.H * R3.H), R1.L = (A0 = R2.H * R3.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 = R4.H * R5.H), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R6.H * R7.H), R3.L = (A0 -= R6.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0xFE0400DE; + CHECKREG r1, 0xE2DCE054; + CHECKREG r2, 0x9D698000; + CHECKREG r3, 0x97C08545; + CHECKREG r4, 0x97BFB128; + CHECKREG r5, 0x85449604; + CHECKREG r6, 0xA00C807D; + CHECKREG r7, 0x078E9008; + CHECKREG p1, 0xFE045B60; + CHECKREG p2, 0x00DDE22A; + CHECKREG p3, 0xE2DC39C0; + CHECKREG p4, 0xE0547AD8; + CHECKREG p5, 0x9D697BD8; + CHECKREG fp, 0x7DBDF6B0; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1a0_iutsh.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1a0_iutsh.s new file mode 100644 index 0000000..8f9e70c --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1a0_iutsh.s @@ -0,0 +1,157 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_iutsh/c_dsp32mac_dr_a1a0_iutsh.dsp +// Spec Reference: dsp32mac dr_a1a0 iutsh +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + R0 = 0; + ASTAT = R0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x13545abd; + imm32 r1, 0xb2bcfec7; + imm32 r2, 0xc1348679; + imm32 r3, 0xd0049007; + imm32 r4, 0x2efbc556; + imm32 r5, 0xcd35560b; + imm32 r6, 0xe00c807d; + imm32 r7, 0xf78e9008; + A1 = A0 = 0; + R6.H = (A1 += R0.L * R0.L), R6.L = (A0 = R0.L * R0.L) (IS); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 += R2.L * R3.L), R1.L = (A0 -= R2.H * R3.L) (FU); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 = R4.L * R5.L) (M), R2.L = (A0 += R4.H * R5.H) (T); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R0.L * R7.L), R3.L = (A0 += R0.L * R7.H) (S2RND); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0x13545ABD; + CHECKREG r1, 0x6BD10000; + CHECKREG r2, 0xEC48ED5B; + CHECKREG r3, 0x8000CEBE; + CHECKREG r4, 0x9CE8AA82; + CHECKREG r5, 0xE75ED19A; + CHECKREG r6, 0x7FFF7FFF; + CHECKREG r7, 0xF78E9008; + CHECKREG p1, 0x20296F89; + CHECKREG p2, 0x20296F89; + CHECKREG p3, 0x6BD12CD8; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0xEC485EB2; + CHECKREG fp, 0xED5B71EE; + + imm32 r0, 0x13545abd; + imm32 r1, 0x22bcfec7; + imm32 r2, 0x43348679; + imm32 r3, 0x50049007; + imm32 r4, 0x6fbc5569; + imm32 r5, 0x7d35560b; + imm32 r6, 0x800c807d; + imm32 r7, 0xf98e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.L * R0.H), R0.L = (A0 = R1.L * R0.L) (IU); + P1 = A1.w; + P2 = A0.w; + R6.H = (A1 += R2.L * R2.H), R6.L = (A0 = R2.H * R2.L) (TFU); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 -= R4.L * R5.H), R2.L = (A0 += R4.H * R5.H) (ISS2); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R3.L * R7.H), R3.L = (A0 -= R3.L * R7.H) (IH); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0xFFFFFFFF; + CHECKREG r1, 0x22BCFEC7; + CHECKREG r2, 0x7FFF7FFF; + CHECKREG r3, 0x0F955721; + CHECKREG r4, 0x0F951905; + CHECKREG r5, 0x5721369E; + CHECKREG r6, 0x3689234C; + CHECKREG r7, 0xF98E9008; + CHECKREG p1, 0x133C5E4C; + CHECKREG p2, 0x5A4E0EEB; + CHECKREG p3, 0x368959E0; + CHECKREG p4, 0x234CFB94; + CHECKREG p5, 0x0CC36623; + CHECKREG fp, 0x59F2E980; + + imm32 r0, 0x13545abd; + imm32 r1, 0x42bcfec7; + imm32 r2, 0x51348679; + imm32 r3, 0x60049007; + imm32 r4, 0x7fbc5569; + imm32 r5, 0x8d35560b; + imm32 r6, 0x900c807d; + imm32 r7, 0xa78e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.H * R0.L), R0.L = (A0 = R1.L * R0.L) (IS); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 += R2.H * R3.L) (M), R1.L = (A0 -= R2.H * R3.L) (IU); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 = R4.H * R5.L), R2.L = (A0 += R4.H * R5.H) (ISS2); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 -= R6.H * R7.L) (M), R3.L = (A0 += R6.L * R7.H) (IH); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0x7FFF8000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x7FFF8000; + CHECKREG r3, 0x69EBC4A8; + CHECKREG r4, 0x69EB64B4; + CHECKREG r5, 0xC4A864C1; + CHECKREG r6, 0x900C807D; + CHECKREG r7, 0xA78E9008; + CHECKREG p1, 0x17A75CCC; + CHECKREG p2, 0xFF910EEB; + CHECKREG p3, 0x4556D538; + CHECKREG p4, 0xD1E1967F; + CHECKREG p5, 0x2AEEA514; + CHECKREG fp, 0x989A946B; + + imm32 r0, 0x03545abd; + imm32 r1, 0xb3bcfec7; + imm32 r2, 0x24348679; + imm32 r3, 0x60049007; + imm32 r4, 0x7fbc5569; + imm32 r5, 0x9d35560b; + imm32 r6, 0xa00c807d; + imm32 r7, 0x078e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.H * R0.H), R0.L = (A0 -= R1.L * R0.L) (FU); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 += R2.H * R3.H), R1.L = (A0 = R2.H * R3.L) (TFU); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 = R4.H * R5.H), R2.L = (A0 += R4.H * R5.H) (IU); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 -= R6.H * R7.H) (M), R3.L = (A0 += R6.L * R7.H) (S2RND); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0x02560000; + CHECKREG r1, 0x0FEA145E; + CHECKREG r2, 0xFFFFFFFF; + CHECKREG r3, 0x7FFF7FFF; + CHECKREG r4, 0x5145A344; + CHECKREG r5, 0x5B485C04; + CHECKREG r6, 0xA00C807D; + CHECKREG r7, 0x078E9008; + CHECKREG p1, 0x02562DB0; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x0FEA3E80; + CHECKREG p4, 0x145E3D6C; + CHECKREG p5, 0x4E70BDEC; + CHECKREG fp, 0x62CEFB58; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_dr_a1a0_m.s b/sim/testsuite/bfin/c_dsp32mac_dr_a1a0_m.s new file mode 100644 index 0000000..2b6f741 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_dr_a1a0_m.s @@ -0,0 +1,157 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_m/c_dsp32mac_dr_a1a0_m.dsp +// Spec Reference: dsp32mac dr_a1a0 m +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + R0 = 0; + ASTAT = R0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x13545abd; + imm32 r1, 0xb2bcfec7; + imm32 r2, 0xc1348679; + imm32 r3, 0xd0049007; + imm32 r4, 0xefbc5569; + imm32 r5, 0xcd35560b; + imm32 r6, 0xe00c807d; + imm32 r7, 0xf78e9008; + A1 = A0 = 0; + R6.H = (A1 += R0.L * R0.L) (M), R6.L = (A0 = R0.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 += R2.L * R3.L) (M), R1.L = (A0 -= R2.H * R3.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 -= R4.L * R5.L) (M), R2.L = (A0 -= R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R0.L * R7.L) (M), R3.L = (A0 += R0.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0x13545ABD; + CHECKREG r1, 0xDBCA0964; + CHECKREG r2, 0xBF1502EF; + CHECKREG r3, 0xF222FCF3; + CHECKREG r4, 0xF222613D; + CHECKREG r5, 0xFCF2D20E; + CHECKREG r6, 0x20294053; + CHECKREG r7, 0xF78E9008; + CHECKREG p1, 0x20296F89; + CHECKREG p2, 0x4052DF12; + CHECKREG p3, 0xDBCA2CD8; + CHECKREG p4, 0x0963CE3A; + CHECKREG p5, 0xBF153B55; + CHECKREG fp, 0x02EF7262; + + imm32 r0, 0x13545abd; + imm32 r1, 0x22bcfec7; + imm32 r2, 0x43348679; + imm32 r3, 0x50049007; + imm32 r4, 0x6fbc5569; + imm32 r5, 0x7d35560b; + imm32 r6, 0x800c807d; + imm32 r7, 0xf98e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.L * R0.H) (M), R0.L = (A0 -= R1.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R6.H = (A1 += R2.L * R2.H) (M), R6.L = (A0 = R2.H * R2.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 -= R4.L * R5.H) (M), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R3.L * R7.H) (M), R3.L = (A0 -= R3.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0xFFE800DE; + CHECKREG r1, 0x22BCFEC7; + CHECKREG r2, 0xB63B2D7E; + CHECKREG r3, 0x800027DA; + CHECKREG r4, 0x49141905; + CHECKREG r5, 0x27DA6D3C; + CHECKREG r6, 0xE001C032; + CHECKREG r7, 0xF98E9008; + CHECKREG p1, 0xFFE85E4C; + CHECKREG p2, 0x00DDE22A; + CHECKREG p3, 0xE00159E0; + CHECKREG p4, 0xC031F728; + CHECKREG p5, 0xB63B6623; + CHECKREG fp, 0x2D7DD300; + + imm32 r0, 0x13545abd; + imm32 r1, 0x42bcfec7; + imm32 r2, 0x51348679; + imm32 r3, 0x60049007; + imm32 r4, 0x7fbc5569; + imm32 r5, 0x8d35560b; + imm32 r6, 0x900c807d; + imm32 r7, 0xa78e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.H * R0.L) (M), R0.L = (A0 = R1.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 -= R2.H * R3.L) (M), R1.L = (A0 -= R2.H * R3.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 -= R4.H * R5.L) (M), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R6.H * R7.L) (M), R3.L = (A0 += R6.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0x17A7FF22; + CHECKREG r1, 0xE9F8462B; + CHECKREG r2, 0xBF09D39D; + CHECKREG r3, 0x800C2BB9; + CHECKREG r4, 0x800C7FAC; + CHECKREG r5, 0x2BB8C982; + CHECKREG r6, 0x900C807D; + CHECKREG r7, 0xA78E9008; + CHECKREG p1, 0x17A75CCC; + CHECKREG p2, 0xFF221DD6; + CHECKREG p3, 0xE9F7E460; + CHECKREG p4, 0x462B2CFE; + CHECKREG p5, 0xBF093F4C; + CHECKREG fp, 0xD39D28D6; + + imm32 r0, 0x03545abd; + imm32 r1, 0xb3bcfec7; + imm32 r2, 0x24348679; + imm32 r3, 0x60049007; + imm32 r4, 0x7fbc5569; + imm32 r5, 0x9d35560b; + imm32 r6, 0xa00c807d; + imm32 r7, 0x078e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.H * R0.H) (M), R0.L = (A0 -= R1.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 -= R2.H * R3.H) (M), R1.L = (A0 = R2.H * R3.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 = R4.H * R5.H) (M), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R6.H * R7.H) (M), R3.L = (A0 += R6.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0xFF0200DE; + CHECKREG r1, 0xF16EE054; + CHECKREG r2, 0x4E718000; + CHECKREG r3, 0x4B9C8000; + CHECKREG r4, 0x4B9BD894; + CHECKREG r5, 0x7637575C; + CHECKREG r6, 0xA00C807D; + CHECKREG r7, 0x078E9008; + CHECKREG p1, 0xFF022DB0; + CHECKREG p2, 0x00DDE22A; + CHECKREG p3, 0xF16E1CE0; + CHECKREG p4, 0xE0547AD8; + CHECKREG p5, 0x4E70BDEC; + CHECKREG fp, 0x7DBDF6B0; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_mix.s b/sim/testsuite/bfin/c_dsp32mac_mix.s new file mode 100644 index 0000000..a5a28c7 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_mix.s @@ -0,0 +1,114 @@ +//Original:/testcases/core/c_dsp32mac_mix/c_dsp32mac_mix.dsp +// Spec Reference: dsp32mac mix +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xab235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246700f; + +A1 = A0 = 0; +A0.L = R0.L; +A0.H = R0.H; + +// test the ROUNDING only on signed fraction T=1 +R0.H = (A1 = R4.L * R5.L), R0.L = (A0 = R4.L * R5.H) (T); +R1.H = (A1 = R4.H * R5.L), R1.L = (A0 = R4.H * R5.H) (T); +R2.H = (A1 = R6.L * R7.L), R2.L = (A0 = R6.H * R7.H) (T); +R3.H = (A1 = R6.L * R7.H), R3.L = (A0 = R6.L * R7.L) (T); +CHECKREG r0, 0x066DF95C; +CHECKREG r1, 0x0E0AF17F; +CHECKREG r2, 0x000B0001; +CHECKREG r3, 0x0001000B; + +// When two results are stored to a single register, they must be rounded +// or truncated and stored to the 2 halves of a single destination reg dst + +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; + +// The result accumulated in A0 and A1, and stored to a reg half +R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; +R3.H = A1 , A0 = R7.H * R6.L (T); +R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L; +A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2); + +CHECKREG r2, 0xFFD15679; +CHECKREG r3, 0xFFD00007; +CHECKREG r4, 0x00074569; +CHECKREG r5, 0x12358000; + +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +// The result accumulated in A0 and A1, and stored to a reg +R5.H = (A1 = R1.L * R0.H), R5.L = (A0 = R1.H * R0.L) (TFU); +R6.H = (A1 = R3.L * R2.H) (M), R6.L = (A0 = R3.H * R2.L) (TFU); +R7.H = (A1 = R1.L * R0.H) (M), R7.L = (A0 = R1.H * R0.L) (IH); // hi-word extraction +CHECKREG r5, 0x133C3D94; +CHECKREG r6, 0x00040002; +CHECKREG r7, 0xFFE8E2D7; + + +// The result accumulated in A0 and A1, and stored to a reg pair +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; + +R3 = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; +R5 = ( A1 = R1.L * R0.H ); +R7 = ( A1 += R1.L * R0.H ) (M), A0 -= R1.H * R0.L; +CHECKREG r2, 0xA1245679; +CHECKREG r3, 0xFFD0BC98; +CHECKREG r4, 0xEFBC4569; +CHECKREG r5, 0xFFD0BC98; +CHECKREG r6, 0x000C000D; +CHECKREG r7, 0xFFB91AE4; +A1 = R1.L * R0.H, R2 = ( A0 = R1.H * R0.L ); +A1 = R1.L * R0.H (M), R6 = ( A0 -= R1.H * R0.L ); +CHECKREG r2, 0xC5AEB798; +CHECKREG r3, 0xFFD0BC98; +CHECKREG r4, 0xEFBC4569; +CHECKREG r5, 0xFFD0BC98; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFFB91AE4; + +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R3 = ( A1 -= R5.L * R4.H ), R2 = ( A0 -= R5.H * R4.L ) (S2RND); +R3 = ( A1 -= R1.L * R0.H ) (M), R2 = ( A0 += R1.H * R0.L ) (S2RND); +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x0002CBB0; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a0.s b/sim/testsuite/bfin/c_dsp32mac_pair_a0.s new file mode 100644 index 0000000..e47600e --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a0.s @@ -0,0 +1,129 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0/c_dsp32mac_pair_a0.dsp +// Spec Reference: dsp32mac pair a0 +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L, R6 = ( A0 = R1.L * R0.L ); + P1 = A1.w; + P5 = A0.w; + A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ); + P2 = A1.w; + A1 -= R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ); + P3 = A0.w; + A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ); + P4 = A0.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF2CF3598; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF70DA834; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xFF221DD6; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0x0004BA9E; + CHECKREG p3, 0xF2CF3598; + CHECKREG p4, 0xF70DA834; + CHECKREG p5, 0xFF221DD6; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A1 += R1.L * R0.H, R4 = ( A0 -= R1.L * R0.L ); + P1 = A0.w; + A1 = R2.L * R3.H, R0 = ( A0 = R2.H * R3.L ); + P2 = A0.w; + A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ); + P3 = A0.w; + A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ); + P4 = A0.w; + CHECKREG r0, 0xFFBC8F22; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFFA518F6; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xFD9B2E5E; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFD9B2E5E; + CHECKREG p2, 0xFFFC4AC8; + CHECKREG p3, 0xFFA518F6; + CHECKREG p4, 0xFFBC8F22; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ); + P1 = A0.w; + A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ); + P2 = A0.w; + A1 -= R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ); + P3 = A0.w; + A1 += R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ); + P4 = A0.w; + CHECKREG r0, 0xF8876658; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x1EA0F4F8; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x00062F18; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xCB200616; + CHECKREG p2, 0x00062F18; + CHECKREG p3, 0xF8876658; + CHECKREG p4, 0x1EA0F4F8; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ); + P1 = A0.w; + A1 -= R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ); + P2 = A0.w; + A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ); + P3 = A0.w; + A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ); + P4 = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0xFF256182; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0xFF1FB35E; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0xF750102E; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFF9EE9A; + CHECKREG p2, 0xFF256182; + CHECKREG p3, 0xFF1FB35E; + CHECKREG p4, 0xF750102E; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a0_i.s b/sim/testsuite/bfin/c_dsp32mac_pair_a0_i.s new file mode 100644 index 0000000..75782f8 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a0_i.s @@ -0,0 +1,247 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_i/c_dsp32mac_pair_a0_i.dsp +// Spec Reference: dsp32mac pair a0 I +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (IS); + P1 = A0.w; + A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (IS); + P5 = A1.w; + P2 = A0.w; + A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (IS); + P3 = A0.w; + A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFFD9ABC; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF9679ACC; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF857FE25; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0x006EF115; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0x006EF115; + CHECKREG p2, 0xFFFD9ABC; + CHECKREG p3, 0xF9679ACC; + CHECKREG p4, 0xF857FE25; + CHECKREG p5, 0x00025D4F; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A0.w; + A1 -= R2.L * R3.H, R0 = ( A0 -= R2.H * R3.L ) (IS); + P2 = A0.w; + A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (IS); + P3 = A0.w; + A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFC8B26EA; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFC7F6BD4; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xFCB93CEB; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFCB93CEB; + CHECKREG p2, 0xFCBB1787; + CHECKREG p3, 0xFC7F6BD4; + CHECKREG p4, 0xFC8B26EA; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L, R4 = ( A0 -= R1.L * R0.L ) (IS); + P1 = A0.w; + A1 -= R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (IS); + P2 = A0.w; + A1 = R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (IS); + P3 = A0.w; + A1 -= R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0x01A40FD3; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x0B2A737B; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0x16FB23DF; + CHECKREG p2, 0x0003178C; + CHECKREG p3, 0x01A40FD3; + CHECKREG p4, 0x0B2A737B; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (IS); + P1 = A0.w; + A1 = R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ) (IS); + P2 = A0.w; + A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (IS); + P3 = A0.w; + A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFFCF74D; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0xFF92B0C1; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0xFF911149; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0x007295B5; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFFCF74D; + CHECKREG p2, 0xFF92B0C1; + CHECKREG p3, 0xFF911149; + CHECKREG p4, 0x007295B5; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (IS); + P5 = A1.w; + P1 = A0.w; + A1 -= R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (IS); + P2 = A0.w; + A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (IS); + P3 = A0.w; + A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFFD9ABC; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF9679ACC; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xFA773773; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xFF910EEB; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF910EEB; + CHECKREG p2, 0xFFFD9ABC; + CHECKREG p3, 0xF9679ACC; + CHECKREG p4, 0xFA773773; + CHECKREG p5, 0xFF89C73F; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R4 = ( A0 -= R1.L * R0.L ) (IS); + P1 = A0.w; + R0 = ( A0 = R2.H * R3.L ) (IS); + P2 = A0.w; + R2 = ( A0 += R4.H * R5.H ) (IS); + P3 = A0.w; + R0 = ( A0 += R6.L * R7.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFE0B29B; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFFD4F785; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xFDBDFA88; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFDBDFA88; + CHECKREG p2, 0xFFFE2564; + CHECKREG p3, 0xFFD4F785; + CHECKREG p4, 0xFFE0B29B; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A0.w; + R6 = ( A0 -= R2.H * R3.L ) (IS); + P2 = A0.w; + A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (IS); + P3 = A0.w; + R4 = ( A0 += R6.L * R7.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xE3AD394F; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xDB61F2C1; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0xE58CEB7F; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xE590030B; + CHECKREG p2, 0xE58CEB7F; + CHECKREG p3, 0xE3AD394F; + CHECKREG p4, 0xDB61F2C1; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R0 = ( A0 = R5.L * R3.L ) (IS); + P1 = A0.w; + A1 -= R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (IS); + P2 = A0.w; + A1 = R7.H * R0.H (M), R4 = ( A0 += R7.H * R0.H ) (IS); + P3 = A0.w; + R6 = ( A0 += R4.L * R6.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFFCF74D; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0x006A468C; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0x0068A714; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0xFBE08004; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFFCF74D; + CHECKREG p2, 0x006A468C; + CHECKREG p3, 0x0068A714; + CHECKREG p4, 0xFBE08004; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a0_is.s b/sim/testsuite/bfin/c_dsp32mac_pair_a0_is.s new file mode 100644 index 0000000..55f6c05 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a0_is.s @@ -0,0 +1,245 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_is/c_dsp32mac_pair_a0_is.dsp +// Spec Reference: dsp32mac pair a0 IS +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (ISS2); + P1 = A1.w; + A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (ISS2); + P2 = A1.w; + A1 -= R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (ISS2); + P3 = A1.w; + A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (ISS2); + P4 = A1.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF2CF3598; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xEE90C2FC; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0x00DDE22A; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF910EEB; + CHECKREG p2, 0x00025D4F; + CHECKREG p3, 0xFFCD4859; + CHECKREG p4, 0x0E03FC27; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A0.w; + A1 -= R2.L * R3.H, R0 = ( A0 -= R2.H * R3.L ) (ISS2); + P2 = A0.w; + A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (ISS2); + P3 = A0.w; + A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xF89EF66E; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xF8878042; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xF97279D6; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFCB93CEB; + CHECKREG p2, 0xFCBB1787; + CHECKREG p3, 0xFC43C021; + CHECKREG p4, 0xFC4F7B37; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A0.w; + A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (ISS2); + P2 = A0.w; + A1 -= R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (ISS2); + P3 = A0.w; + A1 += R6.H * R7.L, R4 = ( A0 -= R6.L * R7.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xF8876658; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xD26DD7B8; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x00062F18; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xE590030B; + CHECKREG p2, 0x0003178C; + CHECKREG p3, 0xFC43B32C; + CHECKREG p4, 0xE936EBDC; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (ISS2); + P1 = A0.w; + A1 -= R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ) (ISS2); + P2 = A0.w; + A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (ISS2); + P3 = A0.w; + A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0xFF256182; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0xFF1FB35E; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0xF750102E; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFFCF74D; + CHECKREG p2, 0xFF92B0C1; + CHECKREG p3, 0xFF8FD9AF; + CHECKREG p4, 0xFBA80817; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L (M), R6 = ( A0 -= R1.L * R0.L ) (ISS2); + P5 = A1.w; + P1 = A0.w; + A1 = R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (ISS2); + P2 = A0.w; + A1 -= R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (ISS2); + P3 = A0.w; + A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF2CF3598; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF0DDEE08; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xF82DF258; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFC16F92C; + CHECKREG p2, 0xFFFD9ABC; + CHECKREG p3, 0xF9679ACC; + CHECKREG p4, 0xF86EF704; + CHECKREG p5, 0xFF82C04D; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A0.w; + R0 = ( A0 -= R2.H * R3.L ) (ISS2); + P2 = A0.w; + R2 = ( A0 += R4.H * R5.H ) (ISS2); + P3 = A0.w; + R0 = ( A0 += R6.L * R7.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xF89EF66E; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xF8878042; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xF97279D6; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFCB93CEB; + CHECKREG p2, 0xFCBB1787; + CHECKREG p3, 0xFC43C021; + CHECKREG p4, 0xFC4F7B37; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A0.w; + R6 = ( A0 = R2.H * R3.L ) (ISS2); + P2 = A0.w; + A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (ISS2); + P3 = A0.w; + R4 = ( A0 += R6.L * R7.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xF8876658; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x1EA0F4F8; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x00062F18; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xE590030B; + CHECKREG p2, 0x0003178C; + CHECKREG p3, 0xFC43B32C; + CHECKREG p4, 0x0F507A7C; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R0 = ( A0 = R5.L * R3.L ) (ISS2); + P1 = A0.w; + A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (ISS2); + P2 = A0.w; + A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (ISS2); + P3 = A0.w; + R6 = ( A0 += R4.L * R6.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0x00D48D18; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0x00DA3B3C; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0x06E3E0DC; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFFCF74D; + CHECKREG p2, 0x006A468C; + CHECKREG p3, 0x006D1D9E; + CHECKREG p4, 0x0371F06E; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a0_m.s b/sim/testsuite/bfin/c_dsp32mac_pair_a0_m.s new file mode 100644 index 0000000..075704f --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a0_m.s @@ -0,0 +1,129 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_m/c_dsp32mac_pair_a0_m.dsp +// Spec Reference: dsp32mac pair a0 m (M, MNOP) +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ); + P5 = A1.w; + P1 = A0.w; + A1 = R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ); + P2 = A0.w; + A1 -= R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ); + P3 = A0.w; + A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ); + P4 = A0.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF2CF3598; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF70DA834; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xFF221DD6; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0xFFFB3578; + CHECKREG p3, 0xF2CF3598; + CHECKREG p4, 0xF70DA834; + CHECKREG p5, 0xFF910EEB; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R4 = ( A0 -= R1.L * R0.L ); + P1 = A0.w; + R0 = ( A0 = R2.H * R3.L ); + P2 = A0.w; + R2 = ( A0 += R4.H * R5.H ); + P3 = A0.w; + R0 = ( A0 += R6.L * R7.H ); + P4 = A0.w; + CHECKREG r0, 0xFFBC8F22; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFFA518F6; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xFD9B2E5E; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFD9B2E5E; + CHECKREG p2, 0xFFFC4AC8; + CHECKREG p3, 0xFFA518F6; + CHECKREG p4, 0xFFBC8F22; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ); + P1 = A0.w; + R6 = ( A0 -= R2.H * R3.L ); + P2 = A0.w; + A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ); + P3 = A0.w; + R4 = ( A0 += R6.L * R7.H ); + P4 = A0.w; + CHECKREG r0, 0xC39B0E3E; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xA26DF406; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0xCB19D6FE; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xCB200616; + CHECKREG p2, 0xCB19D6FE; + CHECKREG p3, 0xC39B0E3E; + CHECKREG p4, 0xA26DF406; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R0 = ( A0 = R5.L * R3.L ); + P1 = A0.w; + A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ); + P2 = A0.w; + A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ); + P3 = A0.w; + R6 = ( A0 += R4.L * R6.H ); + P4 = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0x00D48D18; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0x00DA3B3C; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0x06E3E0DC; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFF9EE9A; + CHECKREG p2, 0x00D48D18; + CHECKREG p3, 0x00DA3B3C; + CHECKREG p4, 0x06E3E0DC; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a0_s.s b/sim/testsuite/bfin/c_dsp32mac_pair_a0_s.s new file mode 100644 index 0000000..77e36d8 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a0_s.s @@ -0,0 +1,245 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_s/c_dsp32mac_pair_a0_s.dsp +// Spec Reference: dsp32mac pair a0 S +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (S2RND); + P1 = A0.w; + A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (S2RND); + P3 = A0.w; + A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0xFFF66AF0; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xE59E6B30; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xD4A4A0C0; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0x01BBC454; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0x00DDE22A; + CHECKREG p2, 0xFFFB3578; + CHECKREG p3, 0xF2CF3598; + CHECKREG p4, 0xEA525060; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A0.w; + A1 = R2.L * R3.H, R0 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (S2RND); + P3 = A0.w; + A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0xFC6CC6B8; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFC3DDA60; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xF2E4F3AC; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xF97279D6; + CHECKREG p2, 0xFFFC4AC8; + CHECKREG p3, 0xFE1EED30; + CHECKREG p4, 0xFE36635C; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L, R4 = ( A0 -= R1.L * R0.L ) (S2RND); + P1 = A0.w; + A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + A1 = R4.H * R5.L, R0 = ( A0 -= R4.H * R5.H ) (S2RND); + P3 = A0.w; + A1 += R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0xE314ECC0; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x7B7B2740; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x000C5E30; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0x33165D46; + CHECKREG p2, 0x00062F18; + CHECKREG p3, 0xF18A7660; + CHECKREG p4, 0x3DBD93A0; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (S2RND); + P1 = A0.w; + A1 -= R2.H * R1.H, R2 = ( A0 = R2.H * R1.L ) (S2RND); + P2 = A0.w; + A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (S2RND); + P3 = A0.w; + A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0xFFF3DD34; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0x01A91A30; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0x01940118; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0x01CD1598; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFF9EE9A; + CHECKREG p2, 0x00D48D18; + CHECKREG p3, 0x00CA008C; + CHECKREG p4, 0x00E68ACC; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (S2RND); + P5 = A1.w; + P1 = A0.w; + A1 -= R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (S2RND); + P3 = A0.w; + A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0xFFF66AF0; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xE59E6B30; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF69835A0; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xFE443BAC; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0xFFFB3578; + CHECKREG p3, 0xF2CF3598; + CHECKREG p4, 0xFB4C1AD0; + CHECKREG p5, 0xFFAFB03F; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R4 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A0.w; + R0 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + R2 = ( A0 -= R4.H * R5.H ) (S2RND); + P3 = A0.w; + R0 = ( A0 += R6.L * R7.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0x03E23D18; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0x03B350C0; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xF2E4F3AC; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xF97279D6; + CHECKREG p2, 0xFFFC4AC8; + CHECKREG p3, 0x01D9A860; + CHECKREG p4, 0x01F11E8C; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A0.w; + R6 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (S2RND); + P3 = A0.w; + R4 = ( A0 += R6.L * R7.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0xE2113B30; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x7A7775B0; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x000C5E30; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xCB200616; + CHECKREG p2, 0x00062F18; + CHECKREG p3, 0xF1089D98; + CHECKREG p4, 0x3D3BBAD8; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R0 = ( A0 -= R5.L * R3.L ) (S2RND); + P1 = A0.w; + A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (S2RND); + P2 = A0.w; + A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (S2RND); + P3 = A0.w; + R6 = ( A0 += R4.L * R6.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0x7A83987C; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0x01A91A30; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0x80000000; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0x80000000; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0x3D41CC3E; + CHECKREG p2, 0x00D48D18; + CHECKREG p3, 0x9D6AA7E4; + CHECKREG p4, 0x9D6AA7E4; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a0_u.s b/sim/testsuite/bfin/c_dsp32mac_pair_a0_u.s new file mode 100644 index 0000000..000fe6b --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a0_u.s @@ -0,0 +1,245 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_u/c_dsp32mac_pair_a0_u.dsp +// Spec Reference: dsp32mac pair a0 U +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (FU); + P1 = A0.w; + A1 -= R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (FU); + P2 = A0.w; + A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (FU); + P3 = A0.w; + A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x00049ABC; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0x60FC9ACC; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0x60FC9ACC; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00049ABC; + CHECKREG p3, 0x60FC9ACC; + CHECKREG p4, 0x60FC9ACC; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (FU); + P1 = A0.w; + A1 -= R2.L * R3.H, R0 = ( A0 = R2.H * R3.L ) (FU); + P2 = A0.w; + A1 = R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (FU); + P3 = A0.w; + A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x0523F7E8; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0x05183CD2; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0x47763CEB; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x47763CEB; + CHECKREG p2, 0x00032564; + CHECKREG p3, 0x05183CD2; + CHECKREG p4, 0x0523F7E8; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ) (FU); + P1 = A0.w; + A1 -= R2.H * R3.L, R6 = ( A0 -= R2.H * R3.L ) (FU); + P2 = A0.w; + A1 = R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (FU); + P3 = A0.w; + A1 += R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x2E395300; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x8D7C0C72; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x2B29EB7F; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0x2B2D030B; + CHECKREG p2, 0x2B29EB7F; + CHECKREG p3, 0x2E395300; + CHECKREG p4, 0x8D7C0C72; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (FU); + P1 = A0.w; + A1 = R2.H * R1.H, R2 = ( A0 = R2.H * R1.L ) (FU); + P2 = A0.w; + A1 -= R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (FU); + P3 = A0.w; + A1 -= R4.H * R6.H, R6 = ( A0 -= R4.L * R6.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x0003F74D; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0xA845468C; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0xA8467E26; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0xA1D8A65E; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0x0003F74D; + CHECKREG p2, 0xA845468C; + CHECKREG p3, 0xA8467E26; + CHECKREG p4, 0xA1D8A65E; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (FU); + P5 = A1.w; + P1 = A0.w; + A1 = R2.L * R3.L (M), R0 = ( A0 -= R2.H * R3.L ) (FU); + P2 = A0.w; + A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (FU); + P3 = A0.w; + A1 -= R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x5A49742F; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xBB41743F; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xBC5110E6; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0x5A4E0EEB; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0x5A4E0EEB; + CHECKREG p2, 0x5A49742F; + CHECKREG p3, 0xBB41743F; + CHECKREG p4, 0xBC5110E6; + CHECKREG p5, 0x573CE4B9; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R4 = ( A0 -= R1.L * R0.L ) (FU); + P1 = A0.w; + R0 = ( A0 = R2.H * R3.L ) (FU); + P2 = A0.w; + R2 = ( A0 += R4.H * R5.H ) (FU); + P3 = A0.w; + R0 = ( A0 -= R6.L * R7.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x0846EF70; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0x0852AA86; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0x74DAD3FB; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x74DAD3FB; + CHECKREG p2, 0x00032564; + CHECKREG p3, 0x0852AA86; + CHECKREG p4, 0x0846EF70; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (FU); + P1 = A0.w; + R6 = ( A0 = R2.H * R3.L ) (FU); + P2 = A0.w; + A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (FU); + P3 = A0.w; + R4 = ( A0 += R6.L * R7.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x03127F0D; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x0C98E2B5; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0x2B2D030B; + CHECKREG p2, 0x0003178C; + CHECKREG p3, 0x03127F0D; + CHECKREG p4, 0x0C98E2B5; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R0 = ( A0 = R5.L * R3.L ) (FU); + P1 = A0.w; + A1 -= R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (FU); + P2 = A0.w; + A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (FU); + P3 = A0.w; + R6 = ( A0 += R4.L * R6.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x0003F74D; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0xA845468C; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0xA8440EF2; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0xA9070C4A; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0x0003F74D; + CHECKREG p2, 0xA845468C; + CHECKREG p3, 0xA8440EF2; + CHECKREG p4, 0xA9070C4A; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a1.s b/sim/testsuite/bfin/c_dsp32mac_pair_a1.s new file mode 100644 index 0000000..36d8e2a --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a1.s @@ -0,0 +1,127 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1/c_dsp32mac_pair_a1.dsp +// Spec Reference: dsp32mac pair a1 +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L; + P1 = A1.w; + R1 = ( A1 = R2.L * R3.L ), A0 += R2.H * R3.L; + P2 = A1.w; + R3 = ( A1 -= R7.L * R4.L ), A0 += R7.H * R4.H; + P3 = A1.w; + R5 = ( A1 -= R6.L * R5.L ), A0 -= R6.L * R5.H; + P4 = A1.w; + CHECKREG r0, 0x63545ABD; + CHECKREG r1, 0x0004BA9E; + CHECKREG r2, 0xA8645679; + CHECKREG r3, 0xE8616512; + CHECKREG r4, 0xEFB86569; + CHECKREG r5, 0xF0688FB4; + CHECKREG r6, 0x000C086D; + CHECKREG r7, 0xFF221DD6; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0x0004BA9E; + CHECKREG p3, 0xE8616512; + CHECKREG p4, 0xF0688FB4; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = ( A1 += R1.L * R0.H ), A0 -= R1.L * R0.L; + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L; + P2 = A1.w; + R3 = ( A1 -= R4.L * R5.H ), A0 += R4.H * R5.H; + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H; + P4 = A1.w; + CHECKREG r0, 0x98764ABD; + CHECKREG r1, 0x012F2306; + CHECKREG r2, 0xA1145649; + CHECKREG r3, 0x0117ACDA; + CHECKREG r4, 0xEFBC1569; + CHECKREG r5, 0xF97C8728; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xF97C8728; + CHECKREG p2, 0x0000AC92; + CHECKREG p3, 0x0117ACDA; + CHECKREG p4, 0x012F2306; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ), A0 = R1.L * R0.L; + P1 = A1.w; + R7 = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L; + P2 = A1.w; + R1 = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H; + P3 = A1.w; + R5 = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H; + P4 = A1.w; + CHECKREG r0, 0x7136459D; + CHECKREG r1, 0xCABE16DA; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xEF9C1569; + CHECKREG r5, 0xCABE9156; + CHECKREG r6, 0x0003401D; + CHECKREG r7, 0xD363146A; + CHECKREG p1, 0xD3694382; + CHECKREG p2, 0xD363146A; + CHECKREG p3, 0xCABE16DA; + CHECKREG p4, 0xCABE9156; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L; + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ), A0 -= R2.H * R1.L; + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H; + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H; + P4 = A1.w; + CHECKREG r0, 0x123489BD; + CHECKREG r1, 0xDBB6D160; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0x18A4A070; + CHECKREG r4, 0xEDB91569; + CHECKREG r5, 0x09DF3640; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0x08024998; + CHECKREG p1, 0xDBB6D160; + CHECKREG p2, 0x18A4A070; + CHECKREG p3, 0x09DF3640; + CHECKREG p4, 0x08024998; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a1_i.s b/sim/testsuite/bfin/c_dsp32mac_pair_a1_i.s new file mode 100644 index 0000000..8ac571d --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a1_i.s @@ -0,0 +1,243 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_i/c_dsp32mac_pair_a1_i.dsp +// Spec Reference: dsp32mac pair a1 I +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x93545abd; + imm32 r1, 0x89bcfec7; + imm32 r2, 0xa8945679; + imm32 r3, 0x00890007; + imm32 r4, 0xefb89569; + imm32 r5, 0x1235890b; + imm32 r6, 0x000c089d; + imm32 r7, 0x678e0089; + R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L (IS); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.L ), A0 -= R2.H * R3.L (IS); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.L ), A0 += R7.H * R4.H (IS); + P3 = A1.w; + R5 = ( A1 += R6.L * R5.L ), A0 += R6.L * R5.H (IS); + P4 = A1.w; + CHECKREG r0, 0x93545ABD; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0xA8945679; + CHECKREG r3, 0xF9C9E563; + CHECKREG r4, 0xEFB89569; + CHECKREG r5, 0xF5C94922; + CHECKREG r6, 0x000C089D; + CHECKREG r7, 0xFF910EEB; + CHECKREG p1, 0xFF910EEB; + CHECKREG p2, 0x00025D4F; + CHECKREG p3, 0xF9C9E563; + CHECKREG p4, 0xF5C94922; + + imm32 r0, 0x98464abd; + imm32 r1, 0xa1b5f4c7; + imm32 r2, 0xa1146649; + imm32 r3, 0x00010805; + imm32 r4, 0xefbc1599; + imm32 r5, 0x12350100; + imm32 r6, 0x200c001d; + imm32 r7, 0x628e0001; + R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (IS); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS); + P2 = A1.w; + R3 = ( A1 = R4.L * R5.H ), A0 -= R4.H * R5.H (IS); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (IS); + P4 = A1.w; + CHECKREG r0, 0x98464ABD; + CHECKREG r1, 0xFF90BFE3; + CHECKREG r2, 0xA1146649; + CHECKREG r3, 0xFF8595CD; + CHECKREG r4, 0xEFBC1599; + CHECKREG r5, 0xFA555F8C; + CHECKREG r6, 0x200C001D; + CHECKREG r7, 0x628E0001; + CHECKREG p1, 0xFA555F8C; + CHECKREG p2, 0x00006649; + CHECKREG p3, 0xFF8595CD; + CHECKREG p4, 0xFF90BFE3; + + imm32 r0, 0x713a459d; + imm32 r1, 0xabd6aec7; + imm32 r2, 0x7a145a79; + imm32 r3, 0x08a100a7; + imm32 r4, 0xef9a156a; + imm32 r5, 0x1225a10b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0a61; + R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (IS); + P1 = A1.w; + R7 = ( A1 -= R2.H * R3.L ), A0 = R2.H * R3.L (IS); + P2 = A1.w; + R1 = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IS); + P3 = A1.w; + R5 = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H (IS); + P4 = A1.w; + CHECKREG r0, 0x713A459D; + CHECKREG r1, 0xE54D2A3B; + CHECKREG r2, 0x7A145A79; + CHECKREG r3, 0x08A100A7; + CHECKREG r4, 0xEF9A156A; + CHECKREG r5, 0xE54DB17A; + CHECKREG r6, 0x0003401D; + CHECKREG r7, 0xE85E2D15; + CHECKREG p1, 0xE8ADD021; + CHECKREG p2, 0xE85E2D15; + CHECKREG p3, 0xE54D2A3B; + CHECKREG p4, 0xE54DB17A; + + imm32 r0, 0x773489bd; + imm32 r1, 0x917cfec7; + imm32 r2, 0xa9177679; + imm32 r3, 0xd0910777; + imm32 r4, 0xedb91579; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d077999; + imm32 r7, 0x677e0709; + R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (IS); + P1 = A1.w; + R3 = ( A1 -= R2.H * R1.H ), A0 = R2.H * R1.L (IS); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H (IS); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ), A0 -= R4.L * R6.H (IS); + P4 = A1.w; + CHECKREG r0, 0x773489BD; + CHECKREG r1, 0xEDC9D17F; + CHECKREG r2, 0xA9177679; + CHECKREG r3, 0xE79AC370; + CHECKREG r4, 0xEDB91579; + CHECKREG r5, 0xB76A2BD8; + CHECKREG r6, 0x0D077999; + CHECKREG r7, 0xB67C10E7; + CHECKREG p1, 0xEDC9D17F; + CHECKREG p2, 0xE79AC370; + CHECKREG p3, 0xB76A2BD8; + CHECKREG p4, 0xB67C10E7; + + imm32 r0, 0x83547abd; + imm32 r1, 0x88bc8ec7; + imm32 r2, 0xa8895679; + imm32 r3, 0x00080007; + imm32 r4, 0xe6b86569; + imm32 r5, 0x1A35860b; + imm32 r6, 0x000c896d; + imm32 r7, 0x67Be0096; + R7 = ( A1 += R1.L * R0.L ) (IS); + P1 = A1.w; + R1 = ( A1 = R2.H * R3.L ) (IS); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.H ) (IS); + P3 = A1.w; + R5 = ( A1 += R6.H * R5.H ) (IS); + P4 = A1.w; + CHECKREG r0, 0x83547ABD; + CHECKREG r1, 0xFFFD9BBF; + CHECKREG r2, 0xA8895679; + CHECKREG r3, 0xF81E0AF0; + CHECKREG r4, 0xE6B86569; + CHECKREG r5, 0xF81F456C; + CHECKREG r6, 0x000C896D; + CHECKREG r7, 0x80334FD2; + CHECKREG p1, 0x80334FD2; + CHECKREG p2, 0xFFFD9BBF; + CHECKREG p3, 0xF81E0AF0; + CHECKREG p4, 0xF81F456C; + + imm32 r0, 0x9aa64abd; + imm32 r1, 0xa1baf4c7; + imm32 r2, 0xb114a649; + imm32 r3, 0x0b010005; + imm32 r4, 0xefbcdb69; + imm32 r5, 0x123501bb; + imm32 r6, 0x000c0d1b; + imm32 r7, 0x678e0d01; + R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (IS); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ) (M), A0 -= R2.H * R3.L (IS); + P2 = A1.w; + R3 = ( A1 -= R4.L * R5.H ) (M), A0 += R4.H * R5.H (IS); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (IS); + P4 = A1.w; + CHECKREG r0, 0x9AA64ABD; + CHECKREG r1, 0x23F08194; + CHECKREG r2, 0xB114A649; + CHECKREG r3, 0x1EA35F9A; + CHECKREG r4, 0xEFBCDB69; + CHECKREG r5, 0xF157B476; + CHECKREG r6, 0x000C0D1B; + CHECKREG r7, 0x678E0D01; + CHECKREG p1, 0xF157B476; + CHECKREG p2, 0xFC24C949; + CHECKREG p3, 0x1EA35F9A; + CHECKREG p4, 0x23F08194; + + imm32 r0, 0xd136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0xdd010007; + imm32 r4, 0xeddc1569; + imm32 r5, 0x122d010b; + imm32 r6, 0x00e3d01d; + imm32 r7, 0x678e0d61; + R5 = A1 , A0 -= R1.L * R0.L (IS); + P1 = A1.w; + R7 = A1 , A0 = R2.H * R3.L (IS); + P2 = A1.w; + R1 = A1 , A0 += R4.H * R5.H (IS); + P3 = A1.w; + R5 = A1 , A0 += R6.L * R7.H (IS); + P4 = A1.w; + CHECKREG r0, 0xD136459D; + CHECKREG r1, 0x23F08194; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0xDD010007; + CHECKREG r4, 0xEDDC1569; + CHECKREG r5, 0x23F08194; + CHECKREG r6, 0x00E3D01D; + CHECKREG r7, 0x23F08194; + CHECKREG p1, 0x23F08194; + CHECKREG p2, 0x23F08194; + CHECKREG p3, 0x23F08194; + CHECKREG p4, 0x23F08194; + + imm32 r0, 0x125489bd; + imm32 r1, 0x91b5fec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910507; + imm32 r4, 0x34567859; + imm32 r5, 0xd2359105; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ) (M,IS); + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ) (M,IS); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ) (M,IS); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ) (M,IS); + P4 = A1.w; + CHECKREG r0, 0x125489BD; + CHECKREG r1, 0xFEA1A199; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0xA98B2D94; + CHECKREG r4, 0x34567859; + CHECKREG r5, 0xA21B7CBC; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0xA4C64EC4; + CHECKREG p1, 0xFEA1A199; + CHECKREG p2, 0xA98B2D94; + CHECKREG p3, 0xA21B7CBC; + CHECKREG p4, 0xA4C64EC4; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a1_is.s b/sim/testsuite/bfin/c_dsp32mac_pair_a1_is.s new file mode 100644 index 0000000..58d9735 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a1_is.s @@ -0,0 +1,243 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_is/c_dsp32mac_pair_a1_is.dsp +// Spec Reference: dsp32mac pair a1 IS +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x93545abd; + imm32 r1, 0x89bcfec7; + imm32 r2, 0xa8945679; + imm32 r3, 0x00890007; + imm32 r4, 0xefb89569; + imm32 r5, 0x1235890b; + imm32 r6, 0x000c089d; + imm32 r7, 0x678e0089; + R7 = ( A1 += R5.L * R0.L ), A0 = R5.L * R0.L (ISS2); + P1 = A1.w; + R1 = ( A1 = R4.L * R3.L ), A0 = R4.H * R3.L (ISS2); + P2 = A1.w; + R3 = ( A1 = R7.L * R2.L ), A0 += R7.H * R2.H (ISS2); + P3 = A1.w; + R5 = ( A1 += R6.L * R1.L ), A0 += R6.L * R1.H (ISS2); + P4 = A1.w; + CHECKREG r0, 0x93545ABD; + CHECKREG r1, 0xFFFA2BBE; + CHECKREG r2, 0xA8945679; + CHECKREG r3, 0x0F06AE9C; + CHECKREG r4, 0xEFB89569; + CHECKREG r5, 0x11F835A8; + CHECKREG r6, 0x000C089D; + CHECKREG r7, 0xABAC163E; + CHECKREG p1, 0xD5D60B1F; + CHECKREG p2, 0xFFFD15DF; + CHECKREG p3, 0x0783574E; + CHECKREG p4, 0x08FC1AD4; + + imm32 r0, 0x98464abd; + imm32 r1, 0xa1b5f4c7; + imm32 r2, 0xa1146649; + imm32 r3, 0x00010805; + imm32 r4, 0xefbc1599; + imm32 r5, 0x12350100; + imm32 r6, 0x200c001d; + imm32 r7, 0x628e0001; + R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (ISS2); + P1 = A1.w; + R1 = ( A1 -= R5.L * R3.H ), A0 = R5.H * R3.L (ISS2); + P2 = A1.w; + R3 = ( A1 -= R4.L * R2.H ), A0 += R4.H * R2.H (ISS2); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (ISS2); + P4 = A1.w; + CHECKREG r0, 0x98464ABD; + CHECKREG r1, 0x2B2A1FC8; + CHECKREG r2, 0xA1146649; + CHECKREG r3, 0x2B13CB9C; + CHECKREG r4, 0xEFBC1599; + CHECKREG r5, 0x1B10627C; + CHECKREG r6, 0x200C001D; + CHECKREG r7, 0x628E0001; + CHECKREG p1, 0x0D88313E; + CHECKREG p2, 0x0D87CEC2; + CHECKREG p3, 0x1589E5CE; + CHECKREG p4, 0x15950FE4; + + imm32 r0, 0x713a459d; + imm32 r1, 0xabd6aec7; + imm32 r2, 0x7a145a79; + imm32 r3, 0x08a100a7; + imm32 r4, 0xef9a156a; + imm32 r5, 0x1225a10b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0a61; + R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (ISS2); + P1 = A1.w; + R7 = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L (ISS2); + P2 = A1.w; + R1 = ( A1 = R7.H * R5.L ), A0 += R7.H * R5.H (ISS2); + P3 = A1.w; + R5 = ( A1 += R6.H * R4.L ), A0 += R6.L * R4.H (ISS2); + P4 = A1.w; + CHECKREG r0, 0x713A459D; + CHECKREG r1, 0xFE604820; + CHECKREG r2, 0x7A145A79; + CHECKREG r3, 0x08A100A7; + CHECKREG r4, 0xEF9A156A; + CHECKREG r5, 0xFE60C89C; + CHECKREG r6, 0x0003401D; + CHECKREG r7, 0xFCC4FA2C; + CHECKREG p1, 0xFEB22022; + CHECKREG p2, 0xFE627D16; + CHECKREG p3, 0xFF302410; + CHECKREG p4, 0xFF30644E; + + imm32 r0, 0x773489bd; + imm32 r1, 0x917cfec7; + imm32 r2, 0xa9177679; + imm32 r3, 0xd0910777; + imm32 r4, 0xedb91579; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d077999; + imm32 r7, 0x677e0709; + R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (ISS2); + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ), A0 = R2.H * R1.L (ISS2); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H (ISS2); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (ISS2); + P4 = A1.w; + CHECKREG r0, 0x773489BD; + CHECKREG r1, 0x0F5908A6; + CHECKREG r2, 0xA9177679; + CHECKREG r3, 0xF59443FE; + CHECKREG r4, 0xEDB91579; + CHECKREG r5, 0x953314CE; + CHECKREG r6, 0x0D077999; + CHECKREG r7, 0x9356DEEC; + CHECKREG p1, 0x07AC8453; + CHECKREG p2, 0xFACA21FF; + CHECKREG p3, 0xCA998A67; + CHECKREG p4, 0xC9AB6F76; + + imm32 r0, 0x83547abd; + imm32 r1, 0x88bc8ec7; + imm32 r2, 0xa8895679; + imm32 r3, 0x00080007; + imm32 r4, 0xe6b86569; + imm32 r5, 0x1A35860b; + imm32 r6, 0x000c896d; + imm32 r7, 0x67Be0096; + R7 = ( A1 += R1.L * R0.L ) (ISS2); + P1 = A1.w; + R1 = ( A1 = R2.H * R3.L ) (ISS2); + P2 = A1.w; + R3 = ( A1 -= R7.L * R4.H ) (ISS2); + P3 = A1.w; + R5 = ( A1 += R6.H * R5.H ) (ISS2); + P4 = A1.w; + CHECKREG r0, 0x83547ABD; + CHECKREG r1, 0xFFFB377E; + CHECKREG r2, 0xA8895679; + CHECKREG r3, 0xFFFB377E; + CHECKREG r4, 0xE6B86569; + CHECKREG r5, 0xFFFDAC76; + CHECKREG r6, 0x000C896D; + CHECKREG r7, 0x80000000; + CHECKREG p1, 0x9362AE61; + CHECKREG p2, 0xFFFD9BBF; + CHECKREG p3, 0xFFFD9BBF; + CHECKREG p4, 0xFFFED63B; + + imm32 r0, 0x9aa64abd; + imm32 r1, 0xa1baf4c7; + imm32 r2, 0xb114a649; + imm32 r3, 0x0b010005; + imm32 r4, 0xefbcdb69; + imm32 r5, 0x123501bb; + imm32 r6, 0x000c0d1b; + imm32 r7, 0x678e0d01; + R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (ISS2); + P1 = A1.w; + R1 = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (ISS2); + P2 = A1.w; + R3 = ( A1 = R4.L * R5.H ) (M), A0 += R4.H * R5.H (ISS2); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (ISS2); + P4 = A1.w; + CHECKREG r0, 0x9AA64ABD; + CHECKREG r1, 0xC54D5630; + CHECKREG r2, 0xB114A649; + CHECKREG r3, 0xBAB3123C; + CHECKREG r4, 0xEFBCDB69; + CHECKREG r5, 0xF26E8A8A; + CHECKREG r6, 0x000C0D1B; + CHECKREG r7, 0x678E0D01; + CHECKREG p1, 0xF9374545; + CHECKREG p2, 0xFD127BFC; + CHECKREG p3, 0xDD59891E; + CHECKREG p4, 0xE2A6AB18; + + imm32 r0, 0xd136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0xdd010007; + imm32 r4, 0xeddc1569; + imm32 r5, 0x122d010b; + imm32 r6, 0x00e3d01d; + imm32 r7, 0x678e0d61; + R5 = A1 , A0 -= R1.L * R0.L (ISS2); + P1 = A1.w; + R7 = A1 , A0 = R2.H * R3.L (ISS2); + P2 = A1.w; + R1 = A1 , A0 += R4.H * R5.H (ISS2); + P3 = A1.w; + R5 = A1 , A0 += R6.L * R7.H (ISS2); + P4 = A1.w; + CHECKREG r0, 0xD136459D; + CHECKREG r1, 0xC54D5630; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0xDD010007; + CHECKREG r4, 0xEDDC1569; + CHECKREG r5, 0xC54D5630; + CHECKREG r6, 0x00E3D01D; + CHECKREG r7, 0xC54D5630; + CHECKREG p1, 0xE2A6AB18; + CHECKREG p2, 0xE2A6AB18; + CHECKREG p3, 0xE2A6AB18; + CHECKREG p4, 0xE2A6AB18; + + imm32 r0, 0x125489bd; + imm32 r1, 0x91b5fec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910507; + imm32 r4, 0x34567859; + imm32 r5, 0xd2359105; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ) (M,ISS2); + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ) (M,ISS2); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ) (M,ISS2); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ) (M,ISS2); + P4 = A1.w; + CHECKREG r0, 0x125489BD; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0xA9140000; + CHECKREG r4, 0x34567859; + CHECKREG r5, 0x9A349E50; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0x9F8A4260; + CHECKREG p1, 0xBD57CB1D; + CHECKREG p2, 0xD48A0000; + CHECKREG p3, 0xCD1A4F28; + CHECKREG p4, 0xCFC52130; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a1_m.s b/sim/testsuite/bfin/c_dsp32mac_pair_a1_m.s new file mode 100644 index 0000000..f93e7a5 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a1_m.s @@ -0,0 +1,127 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_m/c_dsp32mac_pair_a1_m.dsp +// Spec Reference: dsp32mac pair a1 M MNOP +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x63547abd; + imm32 r1, 0x86bc8ec7; + imm32 r2, 0xa8695679; + imm32 r3, 0x00060007; + imm32 r4, 0xe6b86569; + imm32 r5, 0x1A35860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x67Be0086; + R7 = ( A1 += R1.L * R0.L ); + P1 = A1.w; + R1 = ( A1 -= R2.H * R3.L ); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.H ); + P3 = A1.w; + R5 = ( A1 += R6.H * R5.H ); + P4 = A1.w; + CHECKREG r0, 0x63547ABD; + CHECKREG r1, 0x93734818; + CHECKREG r2, 0xA8695679; + CHECKREG r3, 0xE7256BA0; + CHECKREG r4, 0xE6B86569; + CHECKREG r5, 0xE727E098; + CHECKREG r6, 0x000C086D; + CHECKREG r7, 0x936E7DD6; + CHECKREG p1, 0x936E7DD6; + CHECKREG p2, 0x93734818; + CHECKREG p3, 0xE7256BA0; + CHECKREG p4, 0xE727E098; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xb1145649; + imm32 r3, 0x0b010005; + imm32 r4, 0xefbcbb69; + imm32 r5, 0x123501bb; + imm32 r6, 0x000c001b; + imm32 r7, 0x678e0001; + R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L; + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ) (M), A0 = R2.H * R3.L; + P2 = A1.w; + R3 = ( A1 -= R4.L * R5.H ) (M), A0 += R4.H * R5.H; + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H; + P4 = A1.w; + CHECKREG r0, 0x98764ABD; + CHECKREG r1, 0x3FE4AC0B; + CHECKREG r2, 0xB1145649; + CHECKREG r3, 0x3FD9C011; + CHECKREG r4, 0xEFBCBB69; + CHECKREG r5, 0xE078DC52; + CHECKREG r6, 0x000C001B; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xE078DC52; + CHECKREG p2, 0x03B57949; + CHECKREG p3, 0x3FD9C011; + CHECKREG p4, 0x3FE4AC0B; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0xd8010007; + imm32 r4, 0xeddc1569; + imm32 r5, 0x122d010b; + imm32 r6, 0x0003d01d; + imm32 r7, 0x678e0d61; + R5 = A1 , A0 = R1.L * R0.L; + P1 = A1.w; + R7 = A1 , A0 -= R2.H * R3.L; + P2 = A1.w; + R1 = A1 , A0 += R4.H * R5.H; + P3 = A1.w; + R5 = A1 , A0 += R6.L * R7.H; + P4 = A1.w; + CHECKREG r0, 0x7136459D; + CHECKREG r1, 0x3FE4AC0B; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0xD8010007; + CHECKREG r4, 0xEDDC1569; + CHECKREG r5, 0x3FE4AC0B; + CHECKREG r6, 0x0003D01D; + CHECKREG r7, 0x3FE4AC0B; + CHECKREG p1, 0x3FE4AC0B; + CHECKREG p2, 0x3FE4AC0B; + CHECKREG p3, 0x3FE4AC0B; + CHECKREG p4, 0x3FE4AC0B; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0x34567899; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ) (M); + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ) (M); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ) (M); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ) (M); + P4 = A1.w; + CHECKREG r0, 0x123489BD; + CHECKREG r1, 0x1A95CC10; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0xF6F970A4; + CHECKREG r4, 0x34567899; + CHECKREG r5, 0xEF96BB8C; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0xF2418D94; + CHECKREG p1, 0x1A95CC10; + CHECKREG p2, 0xF6F970A4; + CHECKREG p3, 0xEF96BB8C; + CHECKREG p4, 0xF2418D94; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a1_s.s b/sim/testsuite/bfin/c_dsp32mac_pair_a1_s.s new file mode 100644 index 0000000..2cc1ec6 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a1_s.s @@ -0,0 +1,243 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_s/c_dsp32mac_pair_a1_s.dsp +// Spec Reference: dsp32mac pair a1 S +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x93545abd; + imm32 r1, 0x89bcfec7; + imm32 r2, 0xa8945679; + imm32 r3, 0x00890007; + imm32 r4, 0xefb89569; + imm32 r5, 0x1235890b; + imm32 r6, 0x000c089d; + imm32 r7, 0x678e0089; + R7 = ( A1 += R5.L * R0.L ), A0 = R5.L * R0.L (S2RND); + P1 = A1.w; + R1 = ( A1 -= R4.L * R3.L ), A0 = R4.H * R3.L (S2RND); + P2 = A1.w; + R3 = ( A1 -= R7.L * R2.L ), A0 += R7.H * R2.H (S2RND); + P3 = A1.w; + R5 = ( A1 += R6.L * R1.L ), A0 += R6.L * R1.H (S2RND); + P4 = A1.w; + CHECKREG r0, 0x93545ABD; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0xA8945679; + CHECKREG r3, 0x80000000; + CHECKREG r4, 0xEFB89569; + CHECKREG r5, 0x80000000; + CHECKREG r6, 0x000C089D; + CHECKREG r7, 0x80000000; + CHECKREG p1, 0xABAC163E; + CHECKREG p2, 0xABB1EA80; + CHECKREG p3, 0xABB1EA80; + CHECKREG p4, 0xABB1EA80; + + imm32 r0, 0x98464abd; + imm32 r1, 0xa1b5f4c7; + imm32 r2, 0xa1146649; + imm32 r3, 0x00010805; + imm32 r4, 0xefbc1599; + imm32 r5, 0x12350100; + imm32 r6, 0x200c001d; + imm32 r7, 0x628e0001; + R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (S2RND); + P1 = A1.w; + R1 = ( A1 = R5.L * R3.H ), A0 -= R5.H * R3.L (S2RND); + P2 = A1.w; + R3 = ( A1 = R4.L * R2.H ), A0 += R4.H * R2.H (S2RND); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (S2RND); + P4 = A1.w; + CHECKREG r0, 0x98464ABD; + CHECKREG r1, 0xE0244C28; + CHECKREG r2, 0xA1146649; + CHECKREG r3, 0xDFF7A3D0; + CHECKREG r4, 0xEFBC1599; + CHECKREG r5, 0x80000000; + CHECKREG r6, 0x200C001D; + CHECKREG r7, 0x628E0001; + CHECKREG p1, 0xB4CA1754; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0xEFFBD1E8; + CHECKREG p4, 0xF0122614; + + imm32 r0, 0x713a459d; + imm32 r1, 0xabd6aec7; + imm32 r2, 0x7a145a79; + imm32 r3, 0x08a100a7; + imm32 r4, 0xef9a156a; + imm32 r5, 0x1225a10b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0a61; + R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (S2RND); + P1 = A1.w; + R7 = ( A1 = R2.H * R3.L ), A0 -= R2.H * R3.L (S2RND); + P2 = A1.w; + R1 = ( A1 = R7.H * R5.L ), A0 += R7.H * R5.H (S2RND); + P3 = A1.w; + R5 = ( A1 += R6.H * R4.L ), A0 += R6.L * R4.H (S2RND); + P4 = A1.w; + CHECKREG r0, 0x713A459D; + CHECKREG r1, 0xFDC53700; + CHECKREG r2, 0x7A145A79; + CHECKREG r3, 0x08A100A7; + CHECKREG r4, 0xEF9A156A; + CHECKREG r5, 0xFDC637F8; + CHECKREG r6, 0x0003401D; + CHECKREG r7, 0x013E8C30; + CHECKREG p1, 0xC24C4690; + CHECKREG p2, 0x009F4618; + CHECKREG p3, 0xFEE29B80; + CHECKREG p4, 0xFEE31BFC; + + imm32 r0, 0x773489bd; + imm32 r1, 0x917cfec7; + imm32 r2, 0xa9177679; + imm32 r3, 0xd0910777; + imm32 r4, 0xedb91579; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d077999; + imm32 r7, 0x677e0709; + R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (S2RND); + P1 = A1.w; + R3 = ( A1 -= R2.H * R1.H ), A0 = R2.H * R1.L (S2RND); + P2 = A1.w; + R5 = ( A1 = R7.H * R0.H ), A0 += R7.H * R0.H (S2RND); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (S2RND); + P4 = A1.w; + CHECKREG r0, 0x773489BD; + CHECKREG r1, 0x1FB6B80C; + CHECKREG r2, 0xA9177679; + CHECKREG r3, 0x4AC6BAA4; + CHECKREG r4, 0xEDB91579; + CHECKREG r5, 0x7FFFFFFF; + CHECKREG r6, 0x0D077999; + CHECKREG r7, 0x7FFFFFFF; + CHECKREG p1, 0x0FDB5C06; + CHECKREG p2, 0x25635D52; + CHECKREG p3, 0x60612F30; + CHECKREG p4, 0x5E84F94E; + + imm32 r0, 0x83547abd; + imm32 r1, 0x88bc8ec7; + imm32 r2, 0xa8895679; + imm32 r3, 0x00080007; + imm32 r4, 0xe6b86569; + imm32 r5, 0x1A35860b; + imm32 r6, 0x000c896d; + imm32 r7, 0x67Be0096; + R7 = ( A1 += R1.L * R0.L ) (S2RND); + P1 = A1.w; + R1 = ( A1 -= R2.H * R3.L ) (S2RND); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.H ) (S2RND); + P3 = A1.w; + R5 = ( A1 += R6.H * R5.H ) (S2RND); + P4 = A1.w; + CHECKREG r0, 0x83547ABD; + CHECKREG r1, 0xE3F07F4C; + CHECKREG r2, 0xA8895679; + CHECKREG r3, 0x06FFCF00; + CHECKREG r4, 0xE6B86569; + CHECKREG r5, 0x0704B8F0; + CHECKREG r6, 0x000C896D; + CHECKREG r7, 0xE3E6EE48; + CHECKREG p1, 0xF1F37724; + CHECKREG p2, 0xF1F83FA6; + CHECKREG p3, 0x037FE780; + CHECKREG p4, 0x03825C78; + + imm32 r0, 0x9aa64abd; + imm32 r1, 0xa1baf4c7; + imm32 r2, 0xb114a649; + imm32 r3, 0x0b010005; + imm32 r4, 0xefbcdb69; + imm32 r5, 0x123501bb; + imm32 r6, 0x000c0d1b; + imm32 r7, 0x678e0d01; + R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (S2RND); + P1 = A1.w; + R1 = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (S2RND); + P2 = A1.w; + R3 = ( A1 -= R4.L * R5.H ) (M), A0 -= R4.H * R5.H (S2RND); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (S2RND); + P4 = A1.w; + CHECKREG r0, 0x9AA64ABD; + CHECKREG r1, 0x5315786C; + CHECKREG r2, 0xB114A649; + CHECKREG r3, 0x487B3478; + CHECKREG r4, 0xEFBCDB69; + CHECKREG r5, 0xF9759704; + CHECKREG r6, 0x000C0D1B; + CHECKREG r7, 0x678E0D01; + CHECKREG p1, 0xFCBACB82; + CHECKREG p2, 0x00960239; + CHECKREG p3, 0x243D9A3C; + CHECKREG p4, 0x298ABC36; + + imm32 r0, 0xd136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0xdd010007; + imm32 r4, 0xeddc1569; + imm32 r5, 0x122d010b; + imm32 r6, 0x00e3d01d; + imm32 r7, 0x678e0d61; + R5 = A1 , A0 -= R1.L * R0.L (S2RND); + P1 = A1.w; + R7 = A1 , A0 = R2.H * R3.L (S2RND); + P2 = A1.w; + R1 = A1 , A0 -= R4.H * R5.H (S2RND); + P3 = A1.w; + R5 = A1 , A0 += R6.L * R7.H (S2RND); + P4 = A1.w; + CHECKREG r0, 0xD136459D; + CHECKREG r1, 0x5315786C; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0xDD010007; + CHECKREG r4, 0xEDDC1569; + CHECKREG r5, 0x5315786C; + CHECKREG r6, 0x00E3D01D; + CHECKREG r7, 0x5315786C; + CHECKREG p1, 0x298ABC36; + CHECKREG p2, 0x298ABC36; + CHECKREG p3, 0x298ABC36; + CHECKREG p4, 0x298ABC36; + + imm32 r0, 0x125489bd; + imm32 r1, 0x91b5fec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910507; + imm32 r4, 0x34567859; + imm32 r5, 0xd2359105; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ) (M,S2RND); + P1 = A1.w; + R3 = ( A1 -= R2.H * R1.H ) (M,S2RND); + P2 = A1.w; + R5 = ( A1 = R7.H * R0.H ) (M,S2RND); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ) (M,S2RND); + P4 = A1.w; + CHECKREG r0, 0x125489BD; + CHECKREG r1, 0x0877B876; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0x0E3747DE; + CHECKREG r4, 0x34567859; + CHECKREG r5, 0x0EDF61B0; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0x143505C0; + CHECKREG p1, 0x043BDC3B; + CHECKREG p2, 0x071BA3EF; + CHECKREG p3, 0x076FB0D8; + CHECKREG p4, 0x0A1A82E0; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a1_u.s b/sim/testsuite/bfin/c_dsp32mac_pair_a1_u.s new file mode 100644 index 0000000..26cfbd5 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a1_u.s @@ -0,0 +1,243 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_u/c_dsp32mac_pair_a1_u.dsp +// Spec Reference: dsp32mac pair a1 U +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x93545abd; + imm32 r1, 0x89bcfec7; + imm32 r2, 0xa8945679; + imm32 r3, 0x00890007; + imm32 r4, 0xefb89569; + imm32 r5, 0x1235890b; + imm32 r6, 0x000c089d; + imm32 r7, 0x678e0089; + R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L (FU); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L (FU); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.L ), A0 += R7.H * R4.H (FU); + P3 = A1.w; + R5 = ( A1 += R6.L * R5.L ), A0 += R6.L * R5.H (FU); + P4 = A1.w; + CHECKREG r0, 0x93545ABD; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0xA8945679; + CHECKREG r3, 0x08B4E563; + CHECKREG r4, 0xEFB89569; + CHECKREG r5, 0x0D514922; + CHECKREG r6, 0x000C089D; + CHECKREG r7, 0x5A4E0EEB; + CHECKREG p1, 0x5A4E0EEB; + CHECKREG p2, 0x00025D4F; + CHECKREG p3, 0x08B4E563; + CHECKREG p4, 0x0D514922; + + imm32 r0, 0x98464abd; + imm32 r1, 0xa1b5f4c7; + imm32 r2, 0xa1146649; + imm32 r3, 0x00010805; + imm32 r4, 0xefbc1599; + imm32 r5, 0x12350100; + imm32 r6, 0x200c001d; + imm32 r7, 0x628e0001; + R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (FU); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (FU); + P2 = A1.w; + R3 = ( A1 = R4.L * R5.H ), A0 += R4.H * R5.H (FU); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (FU); + P4 = A1.w; + CHECKREG r0, 0x98464ABD; + CHECKREG r1, 0x0D7355F0; + CHECKREG r2, 0xA1146649; + CHECKREG r3, 0x0D682BDA; + CHECKREG r4, 0xEFBC1599; + CHECKREG r5, 0x9EEA5F8C; + CHECKREG r6, 0x200C001D; + CHECKREG r7, 0x628E0001; + CHECKREG p1, 0x9EEA5F8C; + CHECKREG p2, 0x00006649; + CHECKREG p3, 0x0D682BDA; + CHECKREG p4, 0x0D7355F0; + + imm32 r0, 0x713a459d; + imm32 r1, 0xabd6aec7; + imm32 r2, 0x7a145a79; + imm32 r3, 0x08a100a7; + imm32 r4, 0xef9a156a; + imm32 r5, 0x1225a10b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0a61; + R5 = ( A1 += R7.H * R3.L ), A0 = R7.L * R3.L (FU); + P1 = A1.w; + R7 = ( A1 = R2.H * R4.L ), A0 -= R2.H * R4.L (FU); + P2 = A1.w; + R1 = ( A1 -= R0.H * R5.L ), A0 += R0.H * R5.H (FU); + P3 = A1.w; + R5 = ( A1 += R6.H * R1.L ), A0 += R6.L * R1.H (FU); + P4 = A1.w; + CHECKREG r0, 0x713A459D; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x7A145A79; + CHECKREG r3, 0x08A100A7; + CHECKREG r4, 0xEF9A156A; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x0003401D; + CHECKREG r7, 0x0A363048; + CHECKREG p1, 0x0DB6E392; + CHECKREG p2, 0x0A363048; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x00000000; + + imm32 r0, 0x773489bd; + imm32 r1, 0x917cfec7; + imm32 r2, 0xa9177679; + imm32 r3, 0xd0910777; + imm32 r4, 0xedb91579; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d077999; + imm32 r7, 0x677e0709; + R1 = ( A1 += R5.H * R3.H ), A0 -= R5.L * R3.L (FU); + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ), A0 -= R2.H * R1.L (FU); + P2 = A1.w; + R5 = ( A1 = R7.H * R0.H ), A0 += R7.H * R0.H (FU); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (FU); + P4 = A1.w; + CHECKREG r0, 0x773489BD; + CHECKREG r1, 0xAB422005; + CHECKREG r2, 0xA9177679; + CHECKREG r3, 0x711DF4EE; + CHECKREG r4, 0xEDB91579; + CHECKREG r5, 0x30309798; + CHECKREG r6, 0x0D077999; + CHECKREG r7, 0x3C497CA7; + CHECKREG p1, 0xAB422005; + CHECKREG p2, 0x711DF4EE; + CHECKREG p3, 0x30309798; + CHECKREG p4, 0x3C497CA7; + + imm32 r0, 0x83547abd; + imm32 r1, 0x88bc8ec7; + imm32 r2, 0xa8895679; + imm32 r3, 0x00080007; + imm32 r4, 0xe6b86569; + imm32 r5, 0x1A35860b; + imm32 r6, 0x000c896d; + imm32 r7, 0x67Be0096; + R7 = ( A1 += R1.L * R0.L ) (FU); + P1 = A1.w; + R1 = ( A1 = R2.H * R3.L ) (FU); + P2 = A1.w; + R3 = ( A1 -= R7.L * R4.H ) (FU); + P3 = A1.w; + R5 = ( A1 += R6.H * R5.H ) (FU); + P4 = A1.w; + CHECKREG r0, 0x83547ABD; + CHECKREG r1, 0x00049BBF; + CHECKREG r2, 0xA8895679; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0xE6B86569; + CHECKREG r5, 0x00013A7C; + CHECKREG r6, 0x000C896D; + CHECKREG r7, 0x80BDBB92; + CHECKREG p1, 0x80BDBB92; + CHECKREG p2, 0x00049BBF; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x00013A7C; + + imm32 r0, 0x9aa64abd; + imm32 r1, 0xa1baf4c7; + imm32 r2, 0xb114a649; + imm32 r3, 0x0b010005; + imm32 r4, 0xefbcdb69; + imm32 r5, 0x123501bb; + imm32 r6, 0x000c0d1b; + imm32 r7, 0x678e0d01; + R5 = ( A1 += R5.L * R0.H ) (M), A0 = R5.L * R0.L (FU); + P1 = A1.w; + R1 = ( A1 = R1.L * R3.H ) (M), A0 = R1.H * R3.L (FU); + P2 = A1.w; + R3 = ( A1 -= R2.L * R6.H ) (M), A0 += R2.H * R6.H (FU); + P3 = A1.w; + R1 = ( A1 += R4.L * R7.H ) (M), A0 += R4.L * R7.H (FU); + P4 = A1.w; + CHECKREG r0, 0x9AA64ABD; + CHECKREG r1, 0xF0BBA999; + CHECKREG r2, 0xB114A649; + CHECKREG r3, 0xFF88B65B; + CHECKREG r4, 0xEFBCDB69; + CHECKREG r5, 0x010CD7BE; + CHECKREG r6, 0x000C0D1B; + CHECKREG r7, 0x678E0D01; + CHECKREG p1, 0x010CD7BE; + CHECKREG p2, 0xFF8481C7; + CHECKREG p3, 0xFF88B65B; + CHECKREG p4, 0xF0BBA999; + + imm32 r0, 0xd136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0xdd010007; + imm32 r4, 0xeddc1569; + imm32 r5, 0x122d010b; + imm32 r6, 0x00e3d01d; + imm32 r7, 0x678e0d61; + R5 = A1 , A0 = R1.L * R0.L (FU); + P1 = A1.w; + R7 = A1 , A0 = R2.H * R3.L (FU); + P2 = A1.w; + R1 = A1 , A0 += R4.H * R5.H (FU); + P3 = A1.w; + R5 = A1 , A0 += R6.L * R7.H (FU); + P4 = A1.w; + CHECKREG r0, 0xD136459D; + CHECKREG r1, 0xFFFFFFFF; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0xDD010007; + CHECKREG r4, 0xEDDC1569; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0x00E3D01D; + CHECKREG r7, 0xFFFFFFFF; + CHECKREG p1, 0xF0BBA999; + CHECKREG p2, 0xF0BBA999; + CHECKREG p3, 0xF0BBA999; + CHECKREG p4, 0xF0BBA999; + + imm32 r0, 0x125489bd; + imm32 r1, 0x91b5fec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910507; + imm32 r4, 0x34567859; + imm32 r5, 0xd2359105; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ) (M,FU); + P1 = A1.w; + R3 = ( A1 -= R2.H * R1.H ) (M,FU); + P2 = A1.w; + R5 = ( A1 = R7.H * R0.H ) (M,FU); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ) (M,FU); + P4 = A1.w; + CHECKREG r0, 0x125489BD; + CHECKREG r1, 0xCB6CC99E; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0x107E992E; + CHECKREG r4, 0x34567859; + CHECKREG r5, 0x076FB0D8; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0x0A1A82E0; + CHECKREG p1, 0xCB6CC99E; + CHECKREG p2, 0x107E992E; + CHECKREG p3, 0x076FB0D8; + CHECKREG p4, 0x0A1A82E0; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a1a0.s b/sim/testsuite/bfin/c_dsp32mac_pair_a1a0.s new file mode 100644 index 0000000..d7bd4b4 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a1a0.s @@ -0,0 +1,152 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0/c_dsp32mac_pair_a1a0.dsp +// Spec Reference: dsp32mac pair a1a0 +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ); + FP = A1.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x0004BA9E; + CHECKREG r2, 0x00177258; + CHECKREG r3, 0x17A3558C; + CHECKREG r4, 0x0455E4F4; + CHECKREG r5, 0xFB35EDF0; + CHECKREG r6, 0xFF221DD6; + CHECKREG r7, 0xFF221DD6; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0xFF221DD6; + CHECKREG p3, 0x0004BA9E; + CHECKREG p4, 0xFFFB3578; + CHECKREG p5, 0x17A3558C; + CHECKREG sp, 0x00177258; + CHECKREG fp, 0xFB35EDF0; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 -= R2.H * R3.L ); + P2 = A0.w; + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ); + P5 = A1.w; + SP = A0.w; + R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ); + FP = A0.w; + CHECKREG r0, 0xF955783E; + CHECKREG r1, 0xFC03F6B2; + CHECKREG r2, 0xF93E0212; + CHECKREG r3, 0xFBEC8086; + CHECKREG r4, 0xF97279D6; + CHECKREG r5, 0x0449E564; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x0449E564; + CHECKREG p2, 0xF9762F0E; + CHECKREG p3, 0x0000AC92; + CHECKREG p4, 0xF9762F0E; + CHECKREG p5, 0xFBEC8086; + CHECKREG sp, 0xF93E0212; + CHECKREG fp, 0xF955783E; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ); + P1 = A1.w; + P2 = A0.w; + R7 = ( A1 -= R2.H * R3.L ), R6 = ( A0 -= R2.H * R3.L ); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H ); + FP = A0.w; + CHECKREG r0, 0xDFA7BA7E; + CHECKREG r1, 0xF66CBF80; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xEF9AE3A2; + CHECKREG r5, 0x004EF7CC; + CHECKREG r6, 0xCB19D6FE; + CHECKREG r7, 0xCE37E816; + CHECKREG p1, 0xCE3E172E; + CHECKREG p2, 0xCB200616; + CHECKREG p3, 0xCE37E816; + CHECKREG p5, 0xF66CBF80; + CHECKREG p4, 0xCB19D6FE; + CHECKREG sp, 0xDFA7BA7E; + CHECKREG fp, 0xEF9AE3A2; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 -= R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ); + P5 = A1.w; + SP = A0.w; + R7 = ( A1 -= R4.H * R6.H ), R6 = ( A0 -= R4.L * R6.H ); + FP = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0x114737D6; + CHECKREG r2, 0xDA154570; + CHECKREG r3, 0xF4447118; + CHECKREG r4, 0xDA0F974C; + CHECKREG r5, 0xF44A1F3C; + CHECKREG r6, 0xE4BBB02C; + CHECKREG r7, 0xF82827D4; + CHECKREG p1, 0x114737D6; + CHECKREG p2, 0xFFF9EE9A; + CHECKREG p3, 0xF4447118; + CHECKREG p4, 0xDA154570; + CHECKREG p5, 0xF44A1F3C; + CHECKREG sp, 0xDA0F974C; + CHECKREG fp, 0xE4BBB02C; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_i.s b/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_i.s new file mode 100644 index 0000000..24d66fb --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_i.s @@ -0,0 +1,292 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_i/c_dsp32mac_pair_a1a0_i.dsp +// Spec Reference: dsp32mac pair a1a0 I +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (IS); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (IS); + FP = A1.w; + CHECKREG r0, 0xFFFD9ABC; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0x0004A9F4; + CHECKREG r3, 0x05E8D563; + CHECKREG r4, 0x0114469B; + CHECKREG r5, 0xFECD7B7C; + CHECKREG r6, 0xFF910EEB; + CHECKREG r7, 0xFF910EEB; + CHECKREG p1, 0xFF910EEB; + CHECKREG p2, 0xFF910EEB; + CHECKREG p3, 0x00025D4F; + CHECKREG p4, 0xFFFD9ABC; + CHECKREG p5, 0x05E8D563; + CHECKREG sp, 0x0004A9F4; + CHECKREG fp, 0xFECD7B7C; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 -= R2.H * R3.L ) (IS); + P2 = A0.w; + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (IS); + P5 = A1.w; + SP = A0.w; + R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (IS); + FP = A0.w; + CHECKREG r0, 0xFCBBE07C; + CHECKREG r1, 0xFF409C82; + CHECKREG r2, 0xFCB02566; + CHECKREG r3, 0xFF34E16C; + CHECKREG r4, 0xFCB93CEB; + CHECKREG r5, 0x03577736; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x03577736; + CHECKREG p2, 0xFCBB1787; + CHECKREG p3, 0x00005649; + CHECKREG p4, 0xFCBB1787; + CHECKREG p5, 0xFF34E16C; + CHECKREG sp, 0xFCB02566; + CHECKREG fp, 0xFCBBE07C; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R7 = ( A1 = R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 -= R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (IS); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H ) (IS); + FP = A0.w; + CHECKREG r0, 0x0273FCDC; + CHECKREG r1, 0xF76A2B8C; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x02744380; + CHECKREG r5, 0xF76A7230; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x0003178C; + CHECKREG p1, 0xE85DACC0; + CHECKREG p2, 0xE590030B; + CHECKREG p3, 0x0003178C; + CHECKREG p5, 0xF76A2B8C; + CHECKREG p4, 0x0003178C; + CHECKREG sp, 0x0273FCDC; + CHECKREG fp, 0x02744380; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 -= R2.H * R1.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (IS); + P5 = A1.w; + SP = A0.w; + R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (IS); + FP = A0.w; + CHECKREG r0, 0xFFFCF74D; + CHECKREG r1, 0xFFE69235; + CHECKREG r2, 0xDAB58E29; + CHECKREG r3, 0x0008D3F8; + CHECKREG r4, 0xDAB3EEB1; + CHECKREG r5, 0xFFFE6088; + CHECKREG r6, 0xD9D21BFD; + CHECKREG r7, 0xFE17B7EC; + CHECKREG p1, 0xFFE69235; + CHECKREG p2, 0xFFFCF74D; + CHECKREG p3, 0x0008D3F8; + CHECKREG p4, 0xDAB58E29; + CHECKREG p5, 0xFFFE6088; + CHECKREG sp, 0xDAB3EEB1; + CHECKREG fp, 0xD9D21BFD; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 -= R7.H * R4.H ) (IS); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (IS); + FP = A0.w; + CHECKREG r0, 0xFFFD9ABC; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0xFFD771FC; + CHECKREG r3, 0x16A6FC20; + CHECKREG r4, 0x00E70EA3; + CHECKREG r5, 0x1E76A239; + CHECKREG r6, 0xFF910EEB; + CHECKREG r7, 0xFDA8C6D7; + CHECKREG p1, 0xFDA8C6D7; + CHECKREG p2, 0xFF910EEB; + CHECKREG p3, 0x00025D4F; + CHECKREG p4, 0xFFFD9ABC; + CHECKREG p5, 0x16A6FC20; + CHECKREG sp, 0xFFD771FC; + CHECKREG fp, 0x00E70EA3; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = A1, R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R1 = A1, R0 = ( A0 = R2.H * R3.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R3 = A1, R2 = ( A0 -= R4.H * R5.H ) (IS); + P5 = A1.w; + SP = A0.w; + R1 = A1, R0 = ( A0 += R6.L * R7.H ) (IS); + FP = A1.w; + CHECKREG r0, 0x006DB534; + CHECKREG r1, 0x1E76A239; + CHECKREG r2, 0x0061FA1E; + CHECKREG r3, 0x1E76A239; + CHECKREG r4, 0xFCB93CEB; + CHECKREG r5, 0x1E76A239; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x1E76A239; + CHECKREG p2, 0xFCB93CEB; + CHECKREG p3, 0x1E76A239; + CHECKREG p4, 0xFFFE2564; + CHECKREG p5, 0x1E76A239; + CHECKREG sp, 0x0061FA1E; + CHECKREG fp, 0x1E76A239; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R7 = A1, R6 = ( A0 = R2.H * R3.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 += R4.H * R5.H ) (IS); + P5 = A1.w; + SP = A0.w; + R5 = A1, R4 = ( A0 -= R6.L * R7.H ) (IS); + FP = A1.w; + CHECKREG r0, 0xFF3AD93C; + CHECKREG r1, 0xED91D5F0; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xFE887FD8; + CHECKREG r5, 0xED91D5F0; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x0793B277; + CHECKREG p1, 0x0793B277; + CHECKREG p2, 0xE590030B; + CHECKREG p3, 0x0793B277; + CHECKREG p4, 0x0003178C; + CHECKREG p5, 0xED91D5F0; + CHECKREG sp, 0xFF3AD93C; + CHECKREG fp, 0xED91D5F0; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = A1, R0 = ( A0 = R5.L * R3.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (IS); + P5 = A0.w; + SP = A1.w; + R7 = A1, R6 = ( A0 += R4.L * R6.H ) (IS); + FP = A0.w; + CHECKREG r0, 0xFFFCF74D; + CHECKREG r1, 0xED91D5F0; + CHECKREG r2, 0x0E4826C0; + CHECKREG r3, 0xAF564854; + CHECKREG r4, 0x0E468748; + CHECKREG r5, 0x67DC6088; + CHECKREG r6, 0x081F86A8; + CHECKREG r7, 0x67DC6088; + CHECKREG p1, 0xED91D5F0; + CHECKREG p2, 0xFFFCF74D; + CHECKREG p3, 0xAF564854; + CHECKREG p4, 0x0E4826C0; + CHECKREG p5, 0x0E468748; + CHECKREG sp, 0x67DC6088; + CHECKREG fp, 0x081F86A8; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_is.s b/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_is.s new file mode 100644 index 0000000..b719318 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_is.s @@ -0,0 +1,292 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_is/c_dsp32mac_pair_a1a0_is.dsp +// Spec Reference: dsp32mac pair a1a0 IS +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R4.L * R0.L ), R6 = ( A0 = R4.L * R0.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R3.L * R1.L ), R0 = ( A0 = R3.H * R1.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R7.L * R2.L ), R2 = ( A0 += R7.H * R2.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R5.L * R6.L ), R4 = ( A0 += R5.L * R6.H ) (ISS2); + FP = A1.w; + CHECKREG r0, 0xFFFEB854; + CHECKREG r1, 0xFFFFEEE2; + CHECKREG r2, 0xCECAD1AC; + CHECKREG r3, 0xB509D374; + CHECKREG r4, 0x8A4CA32E; + CHECKREG r5, 0x1EC2C250; + CHECKREG r6, 0x47E3910A; + CHECKREG r7, 0x47E3910A; + CHECKREG p1, 0x23F1C885; + CHECKREG p2, 0x23F1C885; + CHECKREG p3, 0xFFFFF771; + CHECKREG p4, 0xFFFF5C2A; + CHECKREG p5, 0xDA84E9BA; + CHECKREG sp, 0xE76568D6; + CHECKREG fp, 0x0F616128; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = ( A1 += R4.L * R0.H ), R4 = ( A0 = R4.L * R0.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (ISS2); + P2 = A0.w; + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R7.L * R5.H ), R2 = ( A0 += R7.H * R5.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R1 = ( A1 += R6.L * R1.H ), R0 = ( A0 += R6.L * R1.H ) (ISS2); + FP = A0.w; + CHECKREG r0, 0x0ADC2224; + CHECKREG r1, 0x00001AE2; + CHECKREG r2, 0x0ADC2224; + CHECKREG r3, 0x00001AE2; + CHECKREG r4, 0x0C80510A; + CHECKREG r5, 0x0D712F1C; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x06B8978E; + CHECKREG p2, 0xFFFE2564; + CHECKREG p3, 0x00005649; + CHECKREG p4, 0xFFFE2564; + CHECKREG p5, 0x00000D71; + CHECKREG sp, 0x056E1112; + CHECKREG fp, 0x056E1112; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R7 = ( A1 = R6.H * R3.L ), R6 = ( A0 = R6.H * R3.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R2.H * R7.L ), R4 = ( A0 += R2.L * R7.H ) (ISS2); + FP = A0.w; + CHECKREG r0, 0x12E88AAA; + CHECKREG r1, 0xE779EB80; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x12E88AAA; + CHECKREG r5, 0xE79F0610; + CHECKREG r6, 0x0000002A; + CHECKREG r7, 0x0000002A; + CHECKREG p1, 0xE91D1DAF; + CHECKREG p2, 0xE590030B; + CHECKREG p3, 0x00000015; + CHECKREG p5, 0xF3BCF5C0; + CHECKREG p4, 0x00000015; + CHECKREG sp, 0x09744555; + CHECKREG fp, 0x09744555; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (ISS2); + FP = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0xF897461A; + CHECKREG r2, 0xD0654810; + CHECKREG r3, 0x05083598; + CHECKREG r4, 0xD05F99EC; + CHECKREG r5, 0xFFFA51DC; + CHECKREG r6, 0xC5F8000C; + CHECKREG r7, 0xFB1F80C4; + CHECKREG p1, 0xFC4BA30D; + CHECKREG p2, 0xFFFCF74D; + CHECKREG p3, 0x02841ACC; + CHECKREG p4, 0xE832A408; + CHECKREG p5, 0xFFFD28EE; + CHECKREG sp, 0xE82FCCF6; + CHECKREG fp, 0xE2FC0006; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (ISS2); + FP = A0.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x0004BA9E; + CHECKREG r2, 0x00B650E8; + CHECKREG r3, 0xB2D59E54; + CHECKREG r4, 0x04F4C384; + CHECKREG r5, 0xD21436B8; + CHECKREG r6, 0xFF221DD6; + CHECKREG r7, 0xFA419E9A; + CHECKREG p1, 0xFD20CF4D; + CHECKREG p2, 0xFF910EEB; + CHECKREG p3, 0x00025D4F; + CHECKREG p4, 0xFFFD9ABC; + CHECKREG p5, 0xD96ACF2A; + CHECKREG sp, 0x005B2874; + CHECKREG fp, 0x027A61C2; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = A1, R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R1 = A1, R0 = ( A0 = R4.H * R3.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R3 = A1, R2 = ( A0 += R2.H * R5.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R1 = A1, R0 = ( A0 += R6.L * R7.H ) (ISS2); + FP = A1.w; + CHECKREG r0, 0x22252FC0; + CHECKREG r1, 0xD21436B8; + CHECKREG r2, 0x220DB994; + CHECKREG r3, 0xD21436B8; + CHECKREG r4, 0xF97279D6; + CHECKREG r5, 0xD21436B8; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xE90A1B5C; + CHECKREG p2, 0xFCB93CEB; + CHECKREG p3, 0xE90A1B5C; + CHECKREG p4, 0xFFFFDF3A; + CHECKREG p5, 0xE90A1B5C; + CHECKREG sp, 0x1106DCCA; + CHECKREG fp, 0xE90A1B5C; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R7 = A1, R6 = ( A0 = R2.H * R3.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 += R4.H * R5.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R5 = A1, R4 = ( A0 += R6.L * R7.H ) (ISS2); + FP = A1.w; + CHECKREG r0, 0x25E6F698; + CHECKREG r1, 0xDBFA4500; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x042A6938; + CHECKREG r5, 0xDBFA4500; + CHECKREG r6, 0x00062F18; + CHECKREG r7, 0xA44E5734; + CHECKREG p1, 0xD2272B9A; + CHECKREG p2, 0xE590030B; + CHECKREG p3, 0xD2272B9A; + CHECKREG p4, 0x0003178C; + CHECKREG p5, 0xEDFD2280; + CHECKREG sp, 0x12F37B4C; + CHECKREG fp, 0xEDFD2280; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = A1, R0 = ( A0 = R5.L * R3.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (ISS2); + P5 = A0.w; + SP = A1.w; + R7 = A1, R6 = ( A0 += R4.L * R6.H ) (ISS2); + FP = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0xDBFA4500; + CHECKREG r2, 0xD124C800; + CHECKREG r3, 0x80000000; + CHECKREG r4, 0xD11F19DC; + CHECKREG r5, 0x7FFFFFFF; + CHECKREG r6, 0xD3C1DE7C; + CHECKREG r7, 0x7FFFFFFF; + CHECKREG p1, 0xEDFD2280; + CHECKREG p2, 0xFFFCF74D; + CHECKREG p3, 0xB54F3988; + CHECKREG p4, 0xE8926400; + CHECKREG p5, 0xE88F8CEE; + CHECKREG sp, 0x67DB28EE; + CHECKREG fp, 0xE9E0EF3E; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_m.s b/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_m.s new file mode 100644 index 0000000..2725fa9 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_m.s @@ -0,0 +1,152 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_m/c_dsp32mac_pair_a1a0_m.dsp +// Spec Reference: dsp32mac pair a1a0 M MNOP +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R0.L * R1.L ) (M), R6 = ( A0 = R0.L * R1.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R3.L * R2.L ) (M), R0 = ( A0 = R3.H * R2.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R7.L * R6.L ) (M), R2 = ( A0 += R7.H * R6.H ) (IS); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R5.L * R4.L ) (M), R4 = ( A0 += R5.L * R4.H ) (IS); + FP = A0.w; + CHECKREG r0, 0x002D4356; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0x00061B84; + CHECKREG r3, 0xFF23D196; + CHECKREG r4, 0x07C7B86C; + CHECKREG r5, 0xCED42319; + CHECKREG r6, 0xFF910EEB; + CHECKREG r7, 0x5A4E0EEB; + CHECKREG p1, 0x5A4E0EEB; + CHECKREG p2, 0xFF910EEB; + CHECKREG p3, 0x00025D4F; + CHECKREG p4, 0x002D4356; + CHECKREG p5, 0xFF23D196; + CHECKREG sp, 0x00061B84; + CHECKREG fp, 0x07C7B86C; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = A1, R4 = ( A0 = R3.L * R1.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R1 = A1, R0 = ( A0 -= R0.H * R5.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R3 = A1, R2 = ( A0 += R2.H * R7.H ) (IS); + P5 = A1.w; + SP = A0.w; + R1 = A1, R0 = ( A0 -= R4.L * R6.H ) (IS); + FP = A1.w; + CHECKREG r0, 0xE7CEC8D1; + CHECKREG r1, 0xCED42319; + CHECKREG r2, 0xE7CC2775; + CHECKREG r3, 0xCED42319; + CHECKREG r4, 0xFFFFC7E3; + CHECKREG r5, 0xCED42319; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xCED42319; + CHECKREG p2, 0xFFFFC7E3; + CHECKREG p3, 0xCED42319; + CHECKREG p4, 0x0E31C25D; + CHECKREG p5, 0xCED42319; + CHECKREG sp, 0xE7CC2775; + CHECKREG fp, 0xCED42319; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R4.H * R3.L ) (M), R4 = ( A0 = R4.L * R3.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R7 = A1, R6 = ( A0 = R5.H * R0.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R2.H * R6.L ) (M), R0 = ( A0 += R2.H * R6.H ) (IS); + P5 = A1.w; + SP = A0.w; + R5 = A1, R4 = ( A0 += R7.L * R1.H ) (IS); + FP = A1.w; + CHECKREG r0, 0xECB84AE7; + CHECKREG r1, 0x5091B70C; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xD3A83F94; + CHECKREG r5, 0x5091B70C; + CHECKREG r6, 0xF2A0B667; + CHECKREG r7, 0xCED3B05D; + CHECKREG p1, 0xCED3B05D; + CHECKREG p2, 0x000095DF; + CHECKREG p3, 0xCED3B05D; + CHECKREG p4, 0xF2A0B667; + CHECKREG p5, 0x5091B70C; + CHECKREG sp, 0xECB84AE7; + CHECKREG fp, 0x5091B70C; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = A1, R0 = ( A0 = R5.L * R2.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R3.H * R1.H ) (M), R2 = ( A0 -= R3.H * R1.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (IS); + P5 = A0.w; + SP = A1.w; + R7 = A1, R6 = ( A0 += R4.L * R6.H ) (IS); + FP = A0.w; + CHECKREG r0, 0xDA854033; + CHECKREG r1, 0x5091B70C; + CHECKREG r2, 0xCD00D267; + CHECKREG r3, 0xF1127221; + CHECKREG r4, 0xBDCBD4BD; + CHECKREG r5, 0x58A90256; + CHECKREG r6, 0xBB976699; + CHECKREG r7, 0x58A90256; + CHECKREG p1, 0x5091B70C; + CHECKREG p2, 0xDA854033; + CHECKREG p3, 0xF1127221; + CHECKREG p4, 0xCD00D267; + CHECKREG p5, 0xBDCBD4BD; + CHECKREG sp, 0x58A90256; + CHECKREG fp, 0xBB976699; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_s.s b/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_s.s new file mode 100644 index 0000000..ce66ae0 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_s.s @@ -0,0 +1,306 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_s/c_dsp32mac_pair_a1a0_s.dsp +// Spec Reference: dsp32mac pair a1a0 S +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (S2RND); + FP = A1.w; + CHECKREG r0, 0xFFF66AF0; + CHECKREG r1, 0x0009753C; + CHECKREG r2, 0x00675E70; + CHECKREG r3, 0x5E8D5630; + CHECKREG r4, 0x116128E0; + CHECKREG r5, 0xECD7B7C0; + CHECKREG r6, 0xFE443BAC; + CHECKREG r7, 0xFE443BAC; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0xFF221DD6; + CHECKREG p3, 0x0004BA9E; + CHECKREG p4, 0xFFFB3578; + CHECKREG p5, 0x2F46AB18; + CHECKREG sp, 0x0033AF38; + CHECKREG fp, 0xF66BDBE0; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A0 = R2; + A1 = R3; + R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (S2RND); + FP = A0.w; + CHECKREG r0, 0xFC6F3BF8; + CHECKREG r1, 0xFCAF6688; + CHECKREG r2, 0xFC404FA0; + CHECKREG r3, 0xFC807A30; + CHECKREG r4, 0xF2E4F3AC; + CHECKREG r5, 0x1229EEF2; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x0914F779; + CHECKREG p2, 0xFFFC4AC8; + CHECKREG p3, 0x0000AC92; + CHECKREG p4, 0xFFFC4AC8; + CHECKREG p5, 0xFE403D18; + CHECKREG sp, 0xFE2027D0; + CHECKREG fp, 0xFE379DFC; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A0 = R0; + A1 = R1; + R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R7 = ( A1 = R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H ) (S2RND); + FP = A0.w; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x7FFFFFFF; + CHECKREG r5, 0x0011A900; + CHECKREG r6, 0x000C5E30; + CHECKREG r7, 0x000C5E30; + CHECKREG p1, 0x7E10BF43; + CHECKREG p2, 0xCB200616; + CHECKREG p3, 0x00062F18; + CHECKREG p5, 0x00000000; + CHECKREG p4, 0x00062F18; + CHECKREG sp, 0x69C62F18; + CHECKREG fp, 0x69CF0398; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A0 = R0; + A1 = R1; + R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (S2RND); + FP = A0.w; + CHECKREG r0, 0xFFF3DD34; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x7FFFFFFF; + CHECKREG r4, 0xFFEAE6E8; + CHECKREG r5, 0xFFEAE6E8; + CHECKREG r6, 0xFACD5268; + CHECKREG r7, 0xFFE66AC8; + CHECKREG p1, 0xA2B53ED1; + CHECKREG p2, 0xFFF9EE9A; + CHECKREG p3, 0x56EC0000; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0xFFF57374; + CHECKREG sp, 0xFFF57374; + CHECKREG fp, 0xFD66A934; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A0 = R0; + A1 = R1; + R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 -= R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (S2RND); + FP = A0.w; + CHECKREG r0, 0xFFF66AF0; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x20866AF0; + CHECKREG r3, 0x80000000; + CHECKREG r4, 0x31803560; + CHECKREG r5, 0x80000000; + CHECKREG r6, 0xFE443BAC; + CHECKREG r7, 0x80000000; + CHECKREG p1, 0x864E0DB2; + CHECKREG p2, 0xFF221DD6; + CHECKREG p3, 0x864BB063; + CHECKREG p4, 0xFFFB3578; + CHECKREG p5, 0x864BB063; + CHECKREG sp, 0x10433578; + CHECKREG fp, 0x18C01AB0; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A0 = R0; + A1 = R1; + R5 = A1, R4 = ( A0 = R3.L * R0.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R1 = A1, R0 = ( A0 = R2.H * R1.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R3 = A1, R2 = ( A0 += R7.H * R5.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R1 = A1, R0 = ( A0 += R4.L * R6.H ) (S2RND); + FP = A1.w; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x80000000; + CHECKREG r3, 0x80000000; + CHECKREG r4, 0x0005D6C4; + CHECKREG r5, 0x80000000; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xA1BCF4C7; + CHECKREG p2, 0x0002EB62; + CHECKREG p3, 0xA1BCF4C7; + CHECKREG p4, 0x08528D18; + CHECKREG p5, 0xA1BCF4C7; + CHECKREG sp, 0xA0C48D18; + CHECKREG fp, 0xA1BCF4C7; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A0 = R0; + A1 = R1; + R5 = ( A1 += R1.H * R6.L ) (M), R4 = ( A0 = R1.L * R6.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R7 = A1, R6 = ( A0 -= R4.H * R3.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R2.H * R5.L ) (M), R0 = ( A0 += R2.H * R5.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R5 = A1, R4 = ( A0 += R0.L * R7.H ) (S2RND); + FP = A1.w; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x80000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x9EA59954; + CHECKREG r7, 0x80000000; + CHECKREG p1, 0x96C29605; + CHECKREG p2, 0xCF4D7916; + CHECKREG p3, 0x96C29605; + CHECKREG p4, 0xCF52CCAA; + CHECKREG p5, 0x00000000; + CHECKREG sp, 0x5E3ECCAA; + CHECKREG fp, 0x00000000; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A0 = R0; + A1 = R1; + R1 = A1, R0 = ( A0 -= R5.L * R3.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 -= R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 -= R7.H * R0.H ) (S2RND); + P5 = A0.w; + SP = A1.w; + R7 = A1, R6 = ( A0 += R4.L * R6.H ) (S2RND); + FP = A0.w; + CHECKREG r0, 0x24753646; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x80000000; + CHECKREG r4, 0xC4D53E28; + CHECKREG r5, 0x1D9560EC; + CHECKREG r6, 0xD18105A8; + CHECKREG r7, 0x1D9560EC; + CHECKREG p1, 0x91BCFEC7; + CHECKREG p2, 0x123A9B23; + CHECKREG p3, 0xBD32FEC7; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0xE26A9F14; + CHECKREG sp, 0x0ECAB076; + CHECKREG fp, 0xE8C082D4; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_u.s b/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_u.s new file mode 100644 index 0000000..1b2707e --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_a1a0_u.s @@ -0,0 +1,292 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_u/c_dsp32mac_pair_a1a0_u.dsp +// Spec Reference: dsp32mac pair a1a0 U +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (FU); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (FU); + FP = A1.w; + CHECKREG r0, 0x00049ABC; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0x549454CC; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x55A3F173; + CHECKREG r5, 0x07CFA619; + CHECKREG r6, 0x5A4E0EEB; + CHECKREG r7, 0x5A4E0EEB; + CHECKREG p1, 0x5A4E0EEB; + CHECKREG p2, 0x5A4E0EEB; + CHECKREG p3, 0x00025D4F; + CHECKREG p4, 0x00049ABC; + CHECKREG p5, 0x00000000; + CHECKREG sp, 0x549454CC; + CHECKREG fp, 0x07CFA619; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 -= R1.L * R0.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 -= R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (FU); + P2 = A0.w; + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (FU); + P5 = A1.w; + SP = A0.w; + R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (FU); + FP = A0.w; + CHECKREG r0, 0x089013D8; + CHECKREG r1, 0x6C5ACAC6; + CHECKREG r2, 0x088458C2; + CHECKREG r3, 0x6C4F0FB0; + CHECKREG r4, 0x0E2DB488; + CHECKREG r5, 0x9996A1D3; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x9996A1D3; + CHECKREG p2, 0x00032564; + CHECKREG p3, 0x99964B8A; + CHECKREG p4, 0x00032564; + CHECKREG p5, 0x6C4F0FB0; + CHECKREG sp, 0x088458C2; + CHECKREG fp, 0x089013D8; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R7 = ( A1 -= R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (FU); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 -= R6.L * R7.H ) (FU); + FP = A0.w; + CHECKREG r0, 0x1A2AB610; + CHECKREG r1, 0x24F02BB4; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x0BE761C4; + CHECKREG r5, 0x24F2761C; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x9B11C378; + CHECKREG p1, 0x9B14DB04; + CHECKREG p2, 0x2B2D030B; + CHECKREG p3, 0x9B11C378; + CHECKREG p5, 0x24F02BB4; + CHECKREG p4, 0x0003178C; + CHECKREG sp, 0x1A2AB610; + CHECKREG fp, 0x0BE761C4; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 -= R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 -= R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (FU); + P5 = A1.w; + SP = A0.w; + R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (FU); + FP = A0.w; + CHECKREG r0, 0x0003F74D; + CHECKREG r1, 0xD0349621; + CHECKREG r2, 0x63278394; + CHECKREG r3, 0x46B1FE11; + CHECKREG r4, 0x6328BB2E; + CHECKREG r5, 0x46B0C677; + CHECKREG r6, 0x6CB2D756; + CHECKREG r7, 0x4BBE7457; + CHECKREG p1, 0xD0349621; + CHECKREG p2, 0x0003F74D; + CHECKREG p3, 0x46B1FE11; + CHECKREG p4, 0x63278394; + CHECKREG p5, 0x46B0C677; + CHECKREG sp, 0x6328BB2E; + CHECKREG fp, 0x6CB2D756; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (FU); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 -= R6.L * R5.L ) (M), R4 = ( A0 -= R6.L * R5.H ) (FU); + FP = A0.w; + CHECKREG r0, 0x00049ABC; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0x46897C84; + CHECKREG r3, 0x316C7D3D; + CHECKREG r4, 0x4579DFDD; + CHECKREG r5, 0x299CD724; + CHECKREG r6, 0x5A4E0EEB; + CHECKREG r7, 0x4B4F8342; + CHECKREG p1, 0x4B4F8342; + CHECKREG p2, 0x5A4E0EEB; + CHECKREG p3, 0x00025D4F; + CHECKREG p4, 0x00049ABC; + CHECKREG p5, 0x316C7D3D; + CHECKREG sp, 0x46897C84; + CHECKREG fp, 0x4579DFDD; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = A1, R4 = ( A0 = R1.L * R0.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R1 = A1, R0 = ( A0 -= R2.H * R3.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R3 = A1, R2 = ( A0 += R4.H * R5.H ) (FU); + P5 = A1.w; + SP = A0.w; + R1 = A1, R0 = ( A0 -= R6.L * R7.H ) (FU); + FP = A1.w; + CHECKREG r0, 0x5304CE59; + CHECKREG r1, 0x299CD724; + CHECKREG r2, 0x5310896F; + CHECKREG r3, 0x299CD724; + CHECKREG r4, 0x47763CEB; + CHECKREG r5, 0x299CD724; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x299CD724; + CHECKREG p2, 0x47763CEB; + CHECKREG p3, 0x299CD724; + CHECKREG p4, 0x47731787; + CHECKREG p5, 0x299CD724; + CHECKREG sp, 0x5310896F; + CHECKREG fp, 0x299CD724; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R7 = A1, R6 = ( A0 = R2.H * R3.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 -= R4.H * R5.H ) (FU); + P5 = A1.w; + SP = A0.w; + R5 = A1, R4 = ( A0 += R6.L * R7.H ) (FU); + FP = A1.w; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x2706223A; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x01B8DC2C; + CHECKREG r5, 0x2706223A; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x12B9E762; + CHECKREG p1, 0x12B9E762; + CHECKREG p2, 0x2B2D030B; + CHECKREG p3, 0x12B9E762; + CHECKREG p4, 0x0003178C; + CHECKREG p5, 0x2706223A; + CHECKREG sp, 0x00000000; + CHECKREG fp, 0x2706223A; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = A1, R0 = ( A0 -= R5.L * R3.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (FU); + P5 = A0.w; + SP = A1.w; + R7 = A1, R6 = ( A0 += R4.L * R6.H ) (FU); + FP = A0.w; + CHECKREG r0, 0x01B4E4DF; + CHECKREG r1, 0x2706223A; + CHECKREG r2, 0x169AF688; + CHECKREG r3, 0xF2C00278; + CHECKREG r4, 0x174BDCA0; + CHECKREG r5, 0x00B0E618; + CHECKREG r6, 0x228A5420; + CHECKREG r7, 0x00B0E618; + CHECKREG p1, 0x2706223A; + CHECKREG p2, 0x01B4E4DF; + CHECKREG p3, 0xF2C00278; + CHECKREG p4, 0x169AF688; + CHECKREG p5, 0x174BDCA0; + CHECKREG sp, 0x00B0E618; + CHECKREG fp, 0x228A5420; + + pass diff --git a/sim/testsuite/bfin/c_dsp32mac_pair_mix.s b/sim/testsuite/bfin/c_dsp32mac_pair_mix.s new file mode 100644 index 0000000..714fedd --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mac_pair_mix.s @@ -0,0 +1,69 @@ +//Original:/testcases/core/c_dsp32mac_pair_mix/c_dsp32mac_pair_mix.dsp +// Spec Reference: dsp32mac pair mix +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00060007; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; + +A0 = 0; +ASTAT = R0; +// The result accumulated in A0 and A1, and stored to a reg pair +imm32 r0, 0x00120034; +imm32 r1, 0x00050006; + +R3 = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; +R5 = ( A1 = R1.L * R0.H ); +R7 = ( A1 = R1.L * R0.H ) (M), A0 = R1.H * R0.L; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x000000d8; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x000000d8; +CHECKREG r6, 0x000C000D; +CHECKREG r7, 0x0000006c; +A1 = R1.L * R0.H, R2 = ( A0 += R1.H * R0.L ); +A1 = R1.L * R0.H (M), R6 = ( A0 -= R1.H * R0.L ); +CHECKREG r2, 0x00000410; +CHECKREG r3, 0x000000d8; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x000000d8; +CHECKREG r6, 0x00000208; +CHECKREG r7, 0x0000006c; +R3 = ( A1 = R1.L * R0.H ), R2 = ( A0 += R1.H * R0.L ) (S2RND); +R5 = ( A1 = R1.L * R0.H ) (M), R4 = ( A0 -= R1.H * R0.L ) (S2RND); +CHECKREG r2, 0x00000820; +CHECKREG r3, 0x000001B0; +CHECKREG r4, 0x00000410; +CHECKREG r5, 0x000000D8; + +imm32 r0, 0x12345678; +imm32 r1, 0x34567897; +imm32 r2, 0x0acb1234; +imm32 r3, 0x456acb07; +imm32 r4, 0x421dbc09; +imm32 r5, 0x89acbd0b; +imm32 r6, 0x5adbcd0d; +imm32 r7, 0x9abc230f; +A1 += R7.L * R5.H, R2 = ( A0 = R7.H * R5.L ); +A1 -= R1.H * R2.L (M), R6 = ( A0 += R1.L * R2.H ) (S2RND); +CHECKREG r0, 0x12345678; +CHECKREG r1, 0x34567897; +CHECKREG r2, 0x34F8E428; +CHECKREG r3, 0x456ACB07; +CHECKREG r4, 0x421DBC09; +CHECKREG r5, 0x89ACBD0B; +CHECKREG r6, 0x7FFFFFFF; +CHECKREG r7, 0x9ABC230F; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr.s b/sim/testsuite/bfin/c_dsp32mult_dr.s new file mode 100644 index 0000000..5ae44cb --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr/c_dsp32mult_dr.dsp +// Spec Reference: dsp32mult single dr +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x93ba5127; +imm32 r2, 0xa3446725; +imm32 r3, 0x00050027; +imm32 r4, 0xb0ab6d29; +imm32 r5, 0x10ace72b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467029; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L; +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H; +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L; +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H; +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L; +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H; +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L; +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H; +CHECKREG r0, 0x39FA39FA; +CHECKREG r1, 0x24C2CEF5; +CHECKREG r2, 0xE9C910A6; +CHECKREG r3, 0x12CA0A8E; +CHECKREG r4, 0x39FA39FA; +CHECKREG r5, 0x369EB722; +CHECKREG r6, 0x369EB722; +CHECKREG r7, 0x33735B96; + +imm32 r0, 0x5b33a635; +imm32 r1, 0x6fbe5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x9006d037; +imm32 r4, 0x80abcb39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c00dd; +imm32 r7, 0x12469003; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L; +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H; +R6.H = R3.L * R2.H, R6.L = R3.L * R2.L; +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H; +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L; +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H; +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L; +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H; +CHECKREG r0, 0xFF31FF31; +CHECKREG r1, 0x00B500B5; +CHECKREG r2, 0xF51DF51D; +CHECKREG r3, 0x09860986; +CHECKREG r4, 0xF51DF51D; +CHECKREG r5, 0x3FAEEF41; +CHECKREG r6, 0xF8DB1B2D; +CHECKREG r7, 0x29CE29CE; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L; +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H; +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L; +R3.H = R5.H * R5.L, R3.L = R5.H * R5.H; +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L; +R5.H = R4.H * R5.L, R5.L = R4.L * R5.H; +R6.H = R5.H * R4.L, R6.L = R5.H * R4.L; +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H; +CHECKREG r0, 0x33491B2A; +CHECKREG r1, 0x0E7AF852; +CHECKREG r2, 0xF852F852; +CHECKREG r3, 0xFDD5022C; +CHECKREG r4, 0x33491B2A; +CHECKREG r5, 0xF955038A; +CHECKREG r6, 0xFE96FE96; +CHECKREG r7, 0xFFD10059; + +imm32 r0, 0xab235666; +imm32 r1, 0xeaba5166; +imm32 r2, 0x13d48766; +imm32 r3, 0xf00b0066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10ac5f6b; +imm32 r6, 0x800cb66d; +imm32 r7, 0x1246707f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L; +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H; +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L; +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H; +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L; +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H; +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L; +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H; +CHECKREG r0, 0x7FE82A4A; +CHECKREG r1, 0xEDBCF57F; +CHECKREG r2, 0xEDBCF57F; +CHECKREG r3, 0x029C029C; +CHECKREG r4, 0x12400609; +CHECKREG r5, 0x029B029B; +CHECKREG r6, 0x7FE82A4A; +CHECKREG r7, 0x1243060A; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0.H = R0.L * R7.H (M), R0.L = R0.H * R7.L; +R1.H = R1.H * R6.H, R1.L = R1.H * R6.H; +R2.H = R2.H * R5.L, R2.L = R2.L * R5.L; +R3.H = R3.H * R4.L (M), R3.L = R3.H * R4.L; +R4.H = R4.L * R3.L, R4.L = R4.L * R3.H; +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L; +R6.H = R6.L * R1.H, R6.L = R6.L * R1.L; +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H; +CHECKREG r0, 0xF99C0A92; +CHECKREG r1, 0xFFFBFFFB; +CHECKREG r2, 0xFB31E621; +CHECKREG r3, 0x0005FFFE; +CHECKREG r4, 0x0001FFFE; +CHECKREG r5, 0xFCA1FCA1; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x0182FF16; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946905; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d9d; +imm32 r7, 0x12467009; +R0.H = R7.H * R0.H, R0.L = R7.L * R0.L; +R1.H = R6.H * R1.L (M), R1.L = R6.H * R1.L; +R2.H = R5.H * R2.H, R2.L = R5.L * R2.L; +R3.H = R4.L * R3.H, R3.L = R4.H * R3.L; +R4.H = R3.H * R4.H, R4.L = R3.L * R4.L; +R5.H = R2.H * R5.L (M), R5.L = R2.H * R5.L; +R6.H = R1.L * R6.L, R6.L = R1.L * R6.H; +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H; +CHECKREG r0, 0xF19A4F2D; +CHECKREG r1, 0x00040008; +CHECKREG r2, 0x028DEDD5; +CHECKREG r3, 0xFFF9FFFA; +CHECKREG r4, 0x00060005; +CHECKREG r5, 0x0255FF8F; +CHECKREG r6, 0x00010000; +CHECKREG r7, 0x0B4EFDF2; + +imm32 r0, 0x8b235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0x00080007; +imm32 r4, 0x90ab8d09; +imm32 r5, 0x10ace8db; +imm32 r6, 0x000c008d; +imm32 r7, 0x12467008; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H; +R3.H = R1.H * R7.H (M), R3.L = R1.L * R7.L; +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H; +R1.H = R3.H * R1.L, R1.L = R3.L * R1.H; +R4.H = R4.L * R2.L, R4.L = R4.L * R2.H; +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L; +R6.H = R6.H * R4.L (M), R6.L = R6.L * R4.H; +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H; +CHECKREG r0, 0x0005FFA9; +CHECKREG r1, 0xFD80E154; +CHECKREG r2, 0x005F0008; +CHECKREG r3, 0xFC0E4707; +CHECKREG r4, 0xFFF9FFAB; +CHECKREG r5, 0x00B70940; +CHECKREG r6, 0x000C0000; +CHECKREG r7, 0x0819001A; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H; +R6.H = R6.H * R3.L (M), R6.L = R6.L * R3.H; +R0.H = R7.L * R4.H, R0.L = R7.H * R4.H; +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L; +R2.H = R1.H * R6.L (M), R2.L = R1.L * R6.H; +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L; +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H; +R7.H = R4.L * R1.L, R7.L = R4.L * R1.H; +CHECKREG r0, 0xF3ECFE08; +CHECKREG r1, 0xFFBE0044; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x0000FFFF; +CHECKREG r4, 0xF234FD56; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFFFF0001; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_i.s b/sim/testsuite/bfin/c_dsp32mult_dr_i.s new file mode 100644 index 0000000..b0b34d5 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_i.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_i/c_dsp32mult_dr_i.dsp +// Spec Reference: dsp32mult single dr i +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IS); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IS); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IS); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IS); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IS); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IS); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IS); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IS); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF8000; +CHECKREG r2, 0x80007FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0x8923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1824b735; +imm32 r3, 0x99860037; +imm32 r4, 0x8098cd39; +imm32 r5, 0xb0a98f3b; +imm32 r6, 0xa00c083d; +imm32 r7, 0x12467083; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IS); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IS); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IS); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IS); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IS); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IS); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IS); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IS); +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x80007FFF; +CHECKREG r7, 0x80008000; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IS); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IS); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IS); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IS); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IS); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IS); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IS); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IS); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF8000; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x80008000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xe0060066; +imm32 r4, 0x9eab9d69; +imm32 r5, 0x10ecef6b; +imm32 r6, 0x800ee06d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IS); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IS); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IS); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IS); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IS); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IS); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IS); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IS); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x80008000; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x7FFF7FFF; + +// mix order +imm32 r0, 0xac23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13c46705; +imm32 r3, 0xf0060007; +imm32 r4, 0x9faccd09; +imm32 r5, 0x10fcdfdb; +imm32 r6, 0x000fc00d; +imm32 r7, 0x1246ff0f; +R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (IS); +R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IS); +R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IS); +R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IS); +R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IS); +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IS); +R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IS); +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IS); +CHECKREG r0, 0x7FFF8000; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x80008000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x80007FFF; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R5.H * R0.H, R0.L = R5.H * R0.L (IS); +R1.H = R6.H * R1.L, R1.L = R6.L * R1.L (IS); +R2.H = R7.H * R2.H, R2.L = R7.H * R2.H (IS); +R3.H = R0.L * R3.H, R3.L = R0.H * R3.L (IS); +R4.H = R1.H * R4.H, R4.L = R1.L * R4.L (IS); +R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (IS); +R6.H = R3.H * R6.H, R6.L = R3.L * R6.L (IS); +R7.H = R4.L * R7.H, R7.L = R4.H * R7.H (IS); +CHECKREG r0, 0x80007FFF; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x80007FFF; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x80008000; + +imm32 r0, 0xfb235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13f46705; +imm32 r3, 0x000f0007; +imm32 r4, 0x90abfd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IS); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IS); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IS); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IS); +R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IS); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IS); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IS); +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IS); +CHECKREG r0, 0x7FFF8000; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x80007FFF; + +imm32 r0, 0xab2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13246d05; +imm32 r3, 0x000600d7; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c500d; +imm32 r7, 0x1246760f; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (IS); +R6.H = R6.H * R3.L, R6.L = R6.H * R3.H (IS); +R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (IS); +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (IS); +R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (IS); +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (IS); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (IS); +R7.H = R4.H * R1.L, R7.L = R4.H * R1.H (IS); +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x0A140048; +CHECKREG r7, 0x80007FFF; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_ih.s b/sim/testsuite/bfin/c_dsp32mult_dr_ih.s new file mode 100644 index 0000000..5236375 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_ih.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_ih/c_dsp32mult_dr_ih.dsp +// Spec Reference: dsp32mult single dr ih +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IH); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IH); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IH); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IH); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IH); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IH); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IH); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IH); +CHECKREG r0, 0x1CFD1CFD; +CHECKREG r1, 0x0930F44E; +CHECKREG r2, 0xFEAD010A; +CHECKREG r3, 0x00890054; +CHECKREG r4, 0x1CFD1CFD; +CHECKREG r5, 0x1B4FDD40; +CHECKREG r6, 0x1B4FDD40; +CHECKREG r7, 0x19BA29A9; + +imm32 r0, 0x9923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1324b735; +imm32 r3, 0x99060037; +imm32 r4, 0x809bcd39; +imm32 r5, 0xb0a99f3b; +imm32 r6, 0xa00c093d; +imm32 r7, 0x12467093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IH); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IH); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IH); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IH); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IH); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IH); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IH); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IH); +CHECKREG r0, 0xFFF4FFF4; +CHECKREG r1, 0x00050005; +CHECKREG r2, 0xFA8FFA8F; +CHECKREG r3, 0x02300230; +CHECKREG r4, 0xFA8FFA8F; +CHECKREG r5, 0x1D48F84D; +CHECKREG r6, 0xFFF00004; +CHECKREG r7, 0xFFEAFFEA; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IH); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IH); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IH); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IH); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IH); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IH); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IH); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IH); +CHECKREG r0, 0x19A50D95; +CHECKREG r1, 0x073DFC29; +CHECKREG r2, 0xFC29FC29; +CHECKREG r3, 0x01150116; +CHECKREG r4, 0x19A50D95; +CHECKREG r5, 0xFE55FF1E; +CHECKREG r6, 0xFFF4FFE9; +CHECKREG r7, 0x00010003; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xe0060066; +imm32 r4, 0x9eab9d69; +imm32 r5, 0x10ecef6b; +imm32 r6, 0x800ee06d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IH); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IH); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IH); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IH); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IH); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IH); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IH); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IH); +CHECKREG r0, 0x3FF203E5; +CHECKREG r1, 0xF6DEFDBF; +CHECKREG r2, 0xF6DEFDBF; +CHECKREG r3, 0x014E014E; +CHECKREG r4, 0x01240012; +CHECKREG r5, 0x00150015; +CHECKREG r6, 0x3FF203E5; +CHECKREG r7, 0x04910047; + +// mix order +imm32 r0, 0xac23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13c46705; +imm32 r3, 0x00060007; +imm32 r4, 0x90accd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000cc00d; +imm32 r7, 0x1246fc0f; +R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (IH); +R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IH); +R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IH); +R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IH); +R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IH); +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IH); +R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IH); +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IH); +CHECKREG r0, 0x0161FA04; +CHECKREG r1, 0xEBBA0004; +CHECKREG r2, 0xFD85FD85; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0xFFD7FFD7; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFF930019; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (IH); +R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (IH); +R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (IH); +R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (IH); +R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (IH); +R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (IH); +R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (IH); +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (IH); +CHECKREG r0, 0xF9F10675; +CHECKREG r1, 0xFFFE0423; +CHECKREG r2, 0xFDBB06D7; +CHECKREG r3, 0xFFA314DD; +CHECKREG r4, 0x00280013; +CHECKREG r5, 0xFFDA0029; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x0076FF91; + +imm32 r0, 0xfb235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13f46705; +imm32 r3, 0x000f0007; +imm32 r4, 0x90abfd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IH); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IH); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IH); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IH); +R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IH); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IH); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IH); +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IH); +CHECKREG r0, 0x0001FFFE; +CHECKREG r1, 0xF94D00A6; +CHECKREG r2, 0x00550004; +CHECKREG r3, 0xFC8EEADF; +CHECKREG r4, 0x0000FFDB; +CHECKREG r5, 0x0038FEA0; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFF660004; + +imm32 r0, 0xab2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13246d05; +imm32 r3, 0x000600d7; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c500d; +imm32 r7, 0x1246760f; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (IH); +R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (IH); +R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (IH); +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (IH); +R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (IH); +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (IH); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (IH); +R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (IH); +CHECKREG r0, 0xFF71FCD4; +CHECKREG r1, 0xFFCB0033; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xFFFD0000; +CHECKREG r4, 0xF920FECB; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0xFFFF0000; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_is.s b/sim/testsuite/bfin/c_dsp32mult_dr_is.s new file mode 100644 index 0000000..f0813428 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_is.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_is/c_dsp32mult_dr_is.dsp +// Spec Reference: dsp32mult single dr is +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (ISS2); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (ISS2); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (ISS2); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (ISS2); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (ISS2); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (ISS2); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (ISS2); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (ISS2); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF8000; +CHECKREG r2, 0x80007FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0x9923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1324b735; +imm32 r3, 0x99060037; +imm32 r4, 0x809bcd39; +imm32 r5, 0xb0a99f3b; +imm32 r6, 0xa00c093d; +imm32 r7, 0x12467093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (ISS2); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (ISS2); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (ISS2); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (ISS2); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (ISS2); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (ISS2); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (ISS2); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (ISS2); +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x80007FFF; +CHECKREG r7, 0x80008000; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (ISS2); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (ISS2); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (ISS2); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (ISS2); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (ISS2); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (ISS2); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (ISS2); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (ISS2); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF8000; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x80008000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xe0060066; +imm32 r4, 0x9eab9d69; +imm32 r5, 0x10ecef6b; +imm32 r6, 0x800ee06d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (ISS2); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (ISS2); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (ISS2); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (ISS2); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (ISS2); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (ISS2); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (ISS2); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (ISS2); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x80008000; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x7FFF7FFF; + +// mix order +imm32 r0, 0xac23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13c46705; +imm32 r3, 0x00060007; +imm32 r4, 0x90accd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000cc00d; +imm32 r7, 0x1246fc0f; +R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (ISS2); +R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (ISS2); +R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (ISS2); +R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (ISS2); +R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (ISS2); +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (ISS2); +R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (ISS2); +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (ISS2); +CHECKREG r0, 0x7FFF8000; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x80008000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x80007FFF; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (ISS2); +R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (ISS2); +R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (ISS2); +R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (ISS2); +R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (ISS2); +R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (ISS2); +R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (ISS2); +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (ISS2); +CHECKREG r0, 0x80007FFF; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x80007FFF; +CHECKREG r3, 0x80007FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x80007FFF; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x7FFF8000; + +imm32 r0, 0xfb235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13f46705; +imm32 r3, 0x000f0007; +imm32 r4, 0x90abfd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (ISS2); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (ISS2); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (ISS2); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (ISS2); +R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (ISS2); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (ISS2); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (ISS2); +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (ISS2); +CHECKREG r0, 0x7FFF8000; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x80007FFF; + +imm32 r0, 0xab2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13246d05; +imm32 r3, 0x000600d7; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c500d; +imm32 r7, 0x1246760f; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (ISS2); +R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (ISS2); +R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (ISS2); +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (ISS2); +R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (ISS2); +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (ISS2); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (ISS2); +R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (ISS2); +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x14287FFF; +CHECKREG r7, 0x80007FFF; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_iu.s b/sim/testsuite/bfin/c_dsp32mult_dr_iu.s new file mode 100644 index 0000000..83b1bc0 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_iu.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_iu/c_dsp32mult_dr_iu.dsp +// Spec Reference: dsp32mult single dr iu +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00010002; +imm32 r1, 0x00023004; +imm32 r2, 0x03843725; +imm32 r3, 0x00084027; +imm32 r4, 0x00ab5d29; +imm32 r5, 0x00ac682b; +imm32 r6, 0x000c708d; +imm32 r7, 0x02462028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IU); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IU); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IU); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IU); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IU); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IU); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IU); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IU); +CHECKREG r0, 0x00040004; +CHECKREG r1, 0xC0100008; +CHECKREG r2, 0x0020FFFF; +CHECKREG r3, 0x0040FFFF; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x60080004; +CHECKREG r6, 0x60080004; +CHECKREG r7, 0xFFFF0004; + +imm32 r0, 0x00230635; +imm32 r1, 0x00995137; +imm32 r2, 0x00240735; +imm32 r3, 0x00060037; +imm32 r4, 0x009b0239; +imm32 r5, 0x00a9933b; +imm32 r6, 0x000c093d; +imm32 r7, 0x12407093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IU); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IU); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IU); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IU); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IU); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IU); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IU); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IU); +CHECKREG r0, 0xFFFFFFFF; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0x2B3E00D8; +CHECKREG r6, 0xFFFF07BC; +CHECKREG r7, 0x014A014A; + +imm32 r0, 0x09235655; +imm32 r1, 0x09ba5157; +imm32 r2, 0x03246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x00ab6509; +imm32 r5, 0x00ac7f5b; +imm32 r6, 0x000a005d; +imm32 r7, 0x0246405f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IU); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IU); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IU); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IU); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IU); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IU); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IU); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IU); +CHECKREG r0, 0xFFFFFFFF; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFF7390; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x00230666; +imm32 r1, 0x00ba0166; +imm32 r2, 0x00240766; +imm32 r3, 0x00060066; +imm32 r4, 0x03ab0d69; +imm32 r5, 0x10ec3f6b; +imm32 r6, 0x000e206d; +imm32 r7, 0x00460e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IU); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IU); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IU); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IU); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IU); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IU); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IU); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IU); +CHECKREG r0, 0x00C4FFFF; +CHECKREG r1, 0x03D4FFFF; +CHECKREG r2, 0x03D4FFFF; +CHECKREG r3, 0x13241324; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x00C4FFFF; +CHECKREG r7, 0x3598FFFF; + +// mix order +imm32 r0, 0x0023a675; +imm32 r1, 0x00ba5127; +imm32 r2, 0x00c46705; +imm32 r3, 0x00060007; +imm32 r4, 0x00accd09; +imm32 r5, 0x00acdfdb; +imm32 r6, 0x000cc00d; +imm32 r7, 0x0246fc0f; +R0.H = R0.L * R7.H, R0.L = R0.H * R7.H (IU); +R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IU); +R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IU); +R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IU); +R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IU); +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IU); +R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IU); +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IU); +CHECKREG r0, 0xFFFF4F92; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x00230a75; +imm32 r1, 0x00ba0127; +imm32 r2, 0x00240905; +imm32 r3, 0x00d60007; +imm32 r4, 0x00ab0d09; +imm32 r5, 0x00ac0ddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x0046000f; +R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (IU); +R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (IU); +R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (IU); +R3.H = R4.L * R3.H, R3.L = R4.H * R3.H (IU); +R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (IU); +R5.H = R2.H * R5.L, R5.L = R2.L * R5.H (IU); +R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (IU); +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (IU); +CHECKREG r0, 0x0992FFFF; +CHECKREG r1, 0x08B8FFFF; +CHECKREG r2, 0x1830FFFF; +CHECKREG r3, 0xFFFF8EF2; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x68A0FFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x0b230675; +imm32 r1, 0x00ba0127; +imm32 r2, 0x03f40705; +imm32 r3, 0x000f0007; +imm32 r4, 0x00ab0d09; +imm32 r5, 0x10ac0fdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246000f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IU); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IU); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IU); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IU); +R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IU); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IU); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IU); +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IU); +CHECKREG r0, 0xFFFFFFFF; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFF4D7C; +CHECKREG r3, 0xFFFF0AE6; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x002d0675; +imm32 r1, 0x001a0027; +imm32 r2, 0x00240005; +imm32 r3, 0x000600d7; +imm32 r4, 0x008b0d09; +imm32 r5, 0x00a0000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x0006060f; +R3.H = R0.L * R2.L, R3.L = R0.L * R2.H (IU); +R4.H = R1.H * R3.L, R4.L = R1.H * R3.H (IU); +R5.H = R2.L * R4.L, R5.L = R2.L * R4.H (IU); +R6.H = R3.L * R5.H, R6.L = R3.L * R5.L (IU); +R0.H = R4.H * R6.L, R0.L = R4.H * R6.L (IU); +R1.H = R5.L * R7.H, R1.L = R5.H * R7.L (IU); +R2.H = R6.L * R0.L, R2.L = R6.L * R0.H (IU); +R7.H = R7.H * R1.L, R7.L = R7.L * R1.H (IU); +CHECKREG r0, 0xFFFFFFFF; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0x2049E874; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_m.s b/sim/testsuite/bfin/c_dsp32mult_dr_m.s new file mode 100644 index 0000000..3e42cae --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_m.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_dsp32mult_dr_m/c_dsp32mult_dr_m.dsp +// Spec Reference: dsp32mult single dr (mix) MUNOP +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R4.L = R0.L * R0.L; +R5.L = R0.L * R1.H; +R6.L = R1.H * R0.L; +R7.L = R1.H * R1.H; +R0.L = R0.L * R0.L; +R1.L = R0.L * R1.H; +R2.L = R1.H * R0.L; +R3.L = R1.H * R1.H; +CHECKREG r0, 0x342339FA; +CHECKREG r1, 0x9F7AD448; +CHECKREG r2, 0xA328D448; +CHECKREG r3, 0x000648CA; +CHECKREG r4, 0xB0AB39FA; +CHECKREG r5, 0x10ACBF0A; +CHECKREG r6, 0xC00CBF0A; +CHECKREG r7, 0xD24648CA; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R4.L = R2.H * R2.L; +R5.L = R2.H * R3.H; +R6.L = R3.L * R2.L; +R7.L = R3.L * R3.H; +R0.L = R2.H * R2.L; +R1.L = R2.H * R3.H; +R2.L = R3.L * R2.L; +R3.L = R3.L * R3.H; +CHECKREG r0, 0x5B23F51D; +CHECKREG r1, 0x6FBAEF41; +CHECKREG r2, 0x1324FFE1; +CHECKREG r3, 0x9006FFD0; +CHECKREG r4, 0x80ABF51D; +CHECKREG r5, 0xB0ACEF41; +CHECKREG r6, 0xA00CFFE1; +CHECKREG r7, 0x1246FFD0; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0.L = R4.L * R4.L; +R1.L = R4.L * R5.H; +R2.L = R5.H * R4.L; +R3.L = R5.H * R5.H; +R4.L = R4.L * R4.L; +R5.L = R4.L * R5.H; +R6.L = R5.H * R4.L; +R7.L = R5.H * R5.H; +CHECKREG r0, 0x1B231B2A; +CHECKREG r1, 0xC4BAF854; +CHECKREG r2, 0x4324F854; +CHECKREG r3, 0x0506022B; +CHECKREG r4, 0x906B1B2A; +CHECKREG r5, 0x10A70389; +CHECKREG r6, 0xB00C0389; +CHECKREG r7, 0x1246022B; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +// test the unsigned U=1 +R0.L = R6.L * R6.L; +R1.L = R6.L * R7.H; +R2.L = R7.H * R6.L; +R3.L = R7.H * R7.H; +R4.L = R6.L * R6.L; +R5.L = R6.L * R7.H; +R6.L = R7.H * R6.L; +R7.L = R7.H * R7.H; +CHECKREG r0, 0xBB233178; +CHECKREG r1, 0xEFBAF4A4; +CHECKREG r2, 0x1324F4A4; +CHECKREG r3, 0xF006029C; +CHECKREG r4, 0x90AB3178; +CHECKREG r5, 0x10ACF4A4; +CHECKREG r6, 0x800CF4A4; +CHECKREG r7, 0x1246029C; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0.L = R0.H * R7.L; +R1.L = R1.H * R6.H; +R2.L = R2.L * R5.L; +R3.L = R3.H * R4.H; +R4.L = R4.L * R3.H; +R5.L = R5.H * R2.L; +R6.L = R6.L * R1.L; +R7.L = R7.H * R0.L; +CHECKREG r0, 0xAB230A92; +CHECKREG r1, 0xCFBAFFFB; +CHECKREG r2, 0x1324E621; +CHECKREG r3, 0x0006FFFB; +CHECKREG r4, 0x90ABFFFE; +CHECKREG r5, 0x10ACFCA1; +CHECKREG r6, 0x000C0000; +CHECKREG r7, 0x12460182; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R7.H * R0.H; +R1.H = R6.H * R1.H; +R2.H = R5.H * R2.L; +R3.H = R4.H * R3.H; +R4.H = R3.L * R4.H; +R5.H = R2.H * R5.L; +R6.H = R1.H * R6.H; +R7.H = R0.L * R7.H; +CHECKREG r0, 0xF3E35A75; +CHECKREG r1, 0xFFFB5127; +CHECKREG r2, 0x0DAE6905; +CHECKREG r3, 0xFFFB0007; +CHECKREG r4, 0xFFFACD09; +CHECKREG r5, 0xFDA2E9DB; +CHECKREG r6, 0x00000D0D; +CHECKREG r7, 0x0CEA700F; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R2.H = R0.L * R6.L; +R3.H = R1.H * R7.L; +R0.H = R2.L * R0.L; +R1.H = R3.L * R1.H; +R4.H = R4.H * R2.H; +R5.H = R5.L * R3.H; +R6.H = R6.H * R4.L; +R7.H = R7.L * R5.H; +CHECKREG r0, 0x45965675; +CHECKREG r1, 0xFFFD5127; +CHECKREG r2, 0x006A6705; +CHECKREG r3, 0xD07F0007; +CHECKREG r4, 0xFFA49D09; +CHECKREG r5, 0x0838E9DB; +CHECKREG r6, 0xFFF7009D; +CHECKREG r7, 0x07327009; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R4.H = R5.L * R2.L; +R6.H = R6.H * R3.H; +R0.H = R7.H * R4.L; +R1.H = R0.H * R5.L; +R2.H = R1.H * R6.H; +R5.H = R2.H * R7.L; +R3.H = R3.H * R0.L; +R7.H = R4.L * R1.H; +CHECKREG r0, 0xFD4B5675; +CHECKREG r1, 0x005D5127; +CHECKREG r2, 0x00006705; +CHECKREG r3, 0x00090007; +CHECKREG r4, 0xF234ED09; +CHECKREG r5, 0x0000EEDB; +CHECKREG r6, 0x000000ED; +CHECKREG r7, 0xFFF2700E; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_m_i.s b/sim/testsuite/bfin/c_dsp32mult_dr_m_i.s new file mode 100644 index 0000000..6860a13 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_m_i.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_m_i/c_dsp32mult_dr_m_i.dsp +// Spec Reference: dsp32mult single dr munop i +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xfb235625; +imm32 r1, 0x9fba5127; +imm32 r2, 0xa3ff6725; +imm32 r3, 0x0006f027; +imm32 r4, 0xb0abcd29; +imm32 r5, 0x1facef2b; +imm32 r6, 0xc0fc002d; +imm32 r7, 0xd24f702f; +R4.L = R0.H * R0.L (IS); +R5.H = R0.L * R1.L (IS); +R6.L = R1.L * R0.H (IS); +R7.L = R1.L * R1.L (IS); +R0.H = R0.L * R0.L (IS); +R1.L = R0.L * R1.L (IS); +R2.L = R1.H * R0.L (IS); +R3.H = R1.L * R1.L (IS); +CHECKREG r0, 0x7FFF5625; +CHECKREG r1, 0x9FBA7FFF; +CHECKREG r2, 0xA3FF8000; +CHECKREG r3, 0x7FFFF027; +CHECKREG r4, 0xB0AB8000; +CHECKREG r5, 0x7FFFEF2B; +CHECKREG r6, 0xC0FC8000; +CHECKREG r7, 0xD24F7FFF; + +imm32 r0, 0xeb23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b7e5; +imm32 r3, 0x9e060037; +imm32 r4, 0x80ebcd39; +imm32 r5, 0xb0aeef3b; +imm32 r6, 0xa00ce03d; +imm32 r7, 0x12467e03; +R5.H = R2.L * R2.L (IS); +R6.L = R2.L * R3.H (IS); +R7.L = R3.H * R2.L (IS); +R0.H = R3.L * R3.L (IS); +R1.H = R2.L * R2.H (IS); +R2.L = R2.H * R3.H (IS); +R3.H = R3.L * R2.L (IS); +R4.L = R3.L * R3.L (IS); +CHECKREG r0, 0x0BD1A635; +CHECKREG r1, 0x80005137; +CHECKREG r2, 0x13248000; +CHECKREG r3, 0x80000037; +CHECKREG r4, 0x80EB0BD1; +CHECKREG r5, 0x7FFFEF3B; +CHECKREG r6, 0xA00C7FFF; +CHECKREG r7, 0x12467FFF; + +imm32 r0, 0xdd235655; +imm32 r1, 0xc4dd5157; +imm32 r2, 0x6324d755; +imm32 r3, 0x00060055; +imm32 r4, 0x90dbc509; +imm32 r5, 0x10adef5b; +imm32 r6, 0xb00cd05d; +imm32 r7, 0x12467d5f; +R0.L = R4.L * R4.H (IS); +R1.H = R4.H * R5.L (IS); +R2.L = R5.H * R4.L (IS); +R3.L = R5.L * R5.L (IS); +R4.H = R4.L * R4.H (IS); +R5.L = R4.L * R5.H (IS); +R6.H = R5.H * R4.H (IS); +R7.L = R5.H * R5.H (IS); +CHECKREG r0, 0xDD237FFF; +CHECKREG r1, 0x7FFF5157; +CHECKREG r2, 0x63248000; +CHECKREG r3, 0x00067FFF; +CHECKREG r4, 0x7FFFC509; +CHECKREG r5, 0x10AD8000; +CHECKREG r6, 0x7FFFD05D; +CHECKREG r7, 0x12467FFF; + +imm32 r0, 0xcb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x1c248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90cb9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cc06d; +imm32 r7, 0x12467c6f; +// test the unsigned U=1 +R0.L = R6.L * R6.L (IS); +R1.H = R6.H * R7.L (IS); +R2.L = R7.L * R6.L (IS); +R3.L = R7.L * R7.L (IS); +R6.H = R6.H * R6.H (IS); +R7.L = R6.L * R7.L (IS); +R4.H = R7.H * R6.H (IS); +R5.L = R7.L * R7.L (IS); +CHECKREG r0, 0xCB237FFF; +CHECKREG r1, 0x80005166; +CHECKREG r2, 0x1C248000; +CHECKREG r3, 0xF0067FFF; +CHECKREG r4, 0x7FFF9D69; +CHECKREG r5, 0x10AC7FFF; +CHECKREG r6, 0x7FFFC06D; +CHECKREG r7, 0x12468000; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0xe0060007; +imm32 r4, 0x9eabcd09; +imm32 r5, 0x10ecdfdb; +imm32 r6, 0x000e000d; +imm32 r7, 0x1246e00f; +R0.H = R0.L * R7.H (IS); +R1.L = R1.H * R6.H (IS); +R2.L = R2.L * R5.L (IS); +R3.H = R3.H * R4.H (IS); +R4.L = R4.L * R3.H (IS); +R5.L = R5.H * R2.H (IS); +R6.H = R6.H * R1.L (IS); +R7.L = R7.L * R0.H (IS); +CHECKREG r0, 0x8000A675; +CHECKREG r1, 0xCFBA8000; +CHECKREG r2, 0x13248000; +CHECKREG r3, 0x7FFF0007; +CHECKREG r4, 0x9EAB8000; +CHECKREG r5, 0x10EC7FFF; +CHECKREG r6, 0x8000000D; +CHECKREG r7, 0x12467FFF; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x93246905; +imm32 r3, 0x09060007; +imm32 r4, 0x909bcd09; +imm32 r5, 0x10a9e9db; +imm32 r6, 0x000c9d0d; +imm32 r7, 0x1246790f; +R0.L = R7.L * R0.H (IS); +R1.L = R6.L * R1.L (IS); +R2.H = R5.L * R2.L (IS); +R3.L = R4.H * R3.L (IS); +R4.L = R3.H * R4.H (IS); +R5.H = R2.H * R5.L (IS); +R6.L = R1.H * R6.L (IS); +R7.L = R0.L * R7.L (IS); +CHECKREG r0, 0x9B238000; +CHECKREG r1, 0xCFBA8000; +CHECKREG r2, 0x80006905; +CHECKREG r3, 0x09068000; +CHECKREG r4, 0x909B8000; +CHECKREG r5, 0x7FFFE9DB; +CHECKREG r6, 0x000C7FFF; +CHECKREG r7, 0x12468000; + +imm32 r0, 0xa9235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x08060007; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a88fdb; +imm32 r6, 0x000c080d; +imm32 r7, 0x1246708f; +R2.L = R0.L * R6.L (IS); +R3.L = R1.H * R7.L (IS); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IS); +R1.H = R3.L * R1.L (IS); +R4.L = R4.H * R2.L (IS); +R5.L = R5.L * R3.L (IS); +R6.L = R6.L * R4.L (IS); +R7.H = R7.H * R5.L (IS); +CHECKREG r0, 0x7FFF8000; +CHECKREG r1, 0x80005127; +CHECKREG r2, 0x13247FFF; +CHECKREG r3, 0x08068000; +CHECKREG r4, 0x908B8000; +CHECKREG r5, 0x10A87FFF; +CHECKREG r6, 0x000C8000; +CHECKREG r7, 0x7FFF708F; + +imm32 r0, 0x7b235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x17246705; +imm32 r3, 0x00760007; +imm32 r4, 0x907bcd09; +imm32 r5, 0x10a7efdb; +imm32 r6, 0x000c700d; +imm32 r7, 0x1246770f; +R4.L = R5.L * R2.L (IS); +R6.L = R6.L * R3.H (IS); +R0.H = R7.L * R4.H (IS); +R1.L = R0.H * R5.L (IS); +R2.L = R1.L * R6.L (IS); +R5.L = R2.L * R7.H (IS); +R3.H = R3.H * R0.L (IS); +R7.L = R4.H * R1.H (IS); +CHECKREG r0, 0x80005675; +CHECKREG r1, 0xCFBA7FFF; +CHECKREG r2, 0x17247FFF; +CHECKREG r3, 0x7FFF0007; +CHECKREG r4, 0x907B8000; +CHECKREG r5, 0x10A77FFF; +CHECKREG r6, 0x000C7FFF; +CHECKREG r7, 0x12467FFF; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_m_iutsh.s b/sim/testsuite/bfin/c_dsp32mult_dr_m_iutsh.s new file mode 100644 index 0000000..4f38460 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_m_iutsh.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_m_iutsh/c_dsp32mult_dr_m_iutsh.dsp +// Spec Reference: dsp32mult single dr munop iu tu is ih +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xfb235625; +imm32 r1, 0x9fba5127; +imm32 r2, 0xa3ff6725; +imm32 r3, 0x0006f027; +imm32 r4, 0xb0abcd29; +imm32 r5, 0x1facef2b; +imm32 r6, 0xc0fc002d; +imm32 r7, 0xd24f702f; +R4.L = R0.H * R0.L (TFU); +R5.H = R0.L * R1.L (IU); +R6.L = R1.L * R0.H (TFU); +R7.L = R1.L * R1.L (TFU); +R0.H = R0.L * R0.L (IU); +R1.L = R0.L * R1.L (TFU); +R2.L = R1.H * R0.L (IU); +R3.H = R1.L * R1.L (TFU); +CHECKREG r0, 0xFFFF5625; +CHECKREG r1, 0x9FBA1B4E; +CHECKREG r2, 0xA3FFFFFF; +CHECKREG r3, 0x02E9F027; +CHECKREG r4, 0xB0AB5482; +CHECKREG r5, 0xFFFFEF2B; +CHECKREG r6, 0xC0FC4F9C; +CHECKREG r7, 0xD24F19B9; + +imm32 r0, 0xeb23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b7e5; +imm32 r3, 0x9e060037; +imm32 r4, 0x80ebcd39; +imm32 r5, 0xb0aeef3b; +imm32 r6, 0xa00ce03d; +imm32 r7, 0x12467e03; +R4.H = R2.L * R2.L (ISS2); +R5.L = R2.L * R3.H (IH); +R6.L = R3.H * R2.L (ISS2); +R7.H = R3.L * R3.L (ISS2); +R2.H = R2.L * R2.H (IH); +R3.L = R2.H * R3.H (ISS2); +R0.H = R3.L * R2.L (IH); +R1.L = R3.L * R3.L (ISS2); +CHECKREG r0, 0xDBF3A635; +CHECKREG r1, 0x6FBA7FFF; +CHECKREG r2, 0xFA9CB7E5; +CHECKREG r3, 0x9E067FFF; +CHECKREG r4, 0x7FFFCD39; +CHECKREG r5, 0xB0AE1B99; +CHECKREG r6, 0xA00C7FFF; +CHECKREG r7, 0x17A27E03; + +imm32 r0, 0xdd235655; +imm32 r1, 0xc4dd5157; +imm32 r2, 0x6324d755; +imm32 r3, 0x00060055; +imm32 r4, 0x90dbc509; +imm32 r5, 0x10adef5b; +imm32 r6, 0xb00cd05d; +imm32 r7, 0x12467d5f; +R0.L = R4.L * R4.H (IU); +R1.H = R4.H * R5.L (TFU); +R2.L = R5.H * R4.L (ISS2); +R3.L = R5.L * R5.L (IH); +R4.H = R4.L * R4.H (ISS2); +R5.L = R4.L * R5.H (TFU); +R6.H = R5.H * R4.H (IU); +R7.L = R5.H * R5.H (ISS2); +CHECKREG r0, 0xDD23FFFF; +CHECKREG r1, 0x876F5157; +CHECKREG r2, 0x63248000; +CHECKREG r3, 0x00060115; +CHECKREG r4, 0x7FFFC509; +CHECKREG r5, 0x10AD0CD5; +CHECKREG r6, 0xFFFFD05D; +CHECKREG r7, 0x12467FFF; + +imm32 r0, 0xcb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x1c248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90cb9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cc06d; +imm32 r7, 0x12467c6f; +// test the unsigned U=1 +R0.L = R6.L * R6.L (TFU); +R1.H = R6.H * R7.L (IH); +R2.L = R7.L * R6.L (ISS2); +R3.L = R7.L * R7.L (IH); +R6.L = R6.L * R6.L (TFU); +R7.L = R6.L * R7.L (IH); +R4.L = R7.L * R6.L (TFU); +R5.L = R7.L * R7.L (ISS2); +CHECKREG r0, 0xCB2390A3; +CHECKREG r1, 0xC1CE5166; +CHECKREG r2, 0x1C248000; +CHECKREG r3, 0xF0063C7C; +CHECKREG r4, 0x90CB720D; +CHECKREG r5, 0x10AC7FFF; +CHECKREG r6, 0x800C90A3; +CHECKREG r7, 0x1246C9DF; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0xe0060007; +imm32 r4, 0x9eabcd09; +imm32 r5, 0x10ecdfdb; +imm32 r6, 0x000e000d; +imm32 r7, 0x1246e00f; +R0.H = R0.L * R7.H (IU); +R1.L = R1.H * R6.H (ISS2); +R2.L = R2.L * R5.L (IU); +R3.H = R3.H * R4.H (ISS2); +R4.L = R4.L * R3.H (IU); +R5.L = R5.H * R2.H (ISS2); +R6.H = R6.H * R1.L (IH); +R7.L = R7.L * R0.H (IU); +CHECKREG r0, 0xFFFFA675; +CHECKREG r1, 0xCFBA8000; +CHECKREG r2, 0x1324FFFF; +CHECKREG r3, 0x7FFF0007; +CHECKREG r4, 0x9EABFFFF; +CHECKREG r5, 0x10EC7FFF; +CHECKREG r6, 0xFFF9000D; +CHECKREG r7, 0x1246FFFF; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x93246905; +imm32 r3, 0x09060007; +imm32 r4, 0x909bcd09; +imm32 r5, 0x10a9e9db; +imm32 r6, 0x000c9d0d; +imm32 r7, 0x1246790f; +R0.L = R7.L * R0.H (TFU); +R1.L = R6.L * R1.L (TFU); +R2.H = R5.L * R2.L (TFU); +R3.L = R4.H * R3.L (TFU); +R4.L = R3.H * R4.H (TFU); +R5.H = R2.H * R5.L (TFU); +R6.L = R1.H * R6.L (TFU); +R7.L = R0.L * R7.L (TFU); +CHECKREG r0, 0x9B23495C; +CHECKREG r1, 0xCFBA31C9; +CHECKREG r2, 0x5FEF6905; +CHECKREG r3, 0x09060003; +CHECKREG r4, 0x909B0518; +CHECKREG r5, 0x57A2E9DB; +CHECKREG r6, 0x000C7F6F; +CHECKREG r7, 0x124622B0; + +imm32 r0, 0xa9235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x08060007; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a88fdb; +imm32 r6, 0x000c080d; +imm32 r7, 0x1246708f; +R2.L = R0.L * R6.L (IU); +R3.L = R1.H * R7.L (IH); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IU); +R1.H = R3.L * R1.L (IH); +R4.L = R4.H * R2.L (IU); +R5.L = R5.L * R3.L (ISS2); +R6.L = R6.L * R4.L (IH); +R7.H = R7.H * R5.L (IU); +CHECKREG r0, 0xFFFFFFFF; +CHECKREG r1, 0xF84C5127; +CHECKREG r2, 0x1324FFFF; +CHECKREG r3, 0x0806E7B2; +CHECKREG r4, 0x908BFFFF; +CHECKREG r5, 0x10A87FFF; +CHECKREG r6, 0x000C0000; +CHECKREG r7, 0xFFFF708F; + +imm32 r0, 0x7b235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x17246705; +imm32 r3, 0x00760007; +imm32 r4, 0x907bcd09; +imm32 r5, 0x10a7efdb; +imm32 r6, 0x000c700d; +imm32 r7, 0x1246770f; +R4.L = R5.L * R2.L (TFU); +R6.L = R6.L * R3.H (ISS2); +R0.H = R7.L * R4.H (ISS2); +R1.L = R0.H * R5.L (ISS2); +R2.L = R1.L * R6.L (IH); +R5.L = R2.L * R7.H (TFU); +R3.H = R3.H * R0.L (IH); +R7.L = R4.H * R1.H (IU); +CHECKREG r0, 0x80005675; +CHECKREG r1, 0xCFBA7FFF; +CHECKREG r2, 0x17243FFF; +CHECKREG r3, 0x00280007; +CHECKREG r4, 0x907B6085; +CHECKREG r5, 0x10A70491; +CHECKREG r6, 0x000C7FFF; +CHECKREG r7, 0x1246FFFF; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_m_s.s b/sim/testsuite/bfin/c_dsp32mult_dr_m_s.s new file mode 100644 index 0000000..670d9d3 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_m_s.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_m_s/c_dsp32mult_dr_m_s.dsp +// Spec Reference: dsp32mult single dr munop s +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xfb235625; +imm32 r1, 0x9fba5127; +imm32 r2, 0xa3ff6725; +imm32 r3, 0x0006f027; +imm32 r4, 0xb0abcd29; +imm32 r5, 0x1facef2b; +imm32 r6, 0xc0fc002d; +imm32 r7, 0xd24f702f; +R4.L = R0.H * R0.L (S2RND); +R5.H = R0.L * R1.L (S2RND); +R6.L = R1.L * R0.H (S2RND); +R7.L = R1.L * R1.L (S2RND); +R0.H = R0.L * R0.L (S2RND); +R1.L = R0.L * R1.L (S2RND); +R2.L = R1.H * R0.L (S2RND); +R3.H = R1.L * R1.L (S2RND); +CHECKREG r0, 0x73F45625; +CHECKREG r1, 0x9FBA6D3B; +CHECKREG r2, 0xA3FF8000; +CHECKREG r3, 0x7FFFF027; +CHECKREG r4, 0xB0ABF974; +CHECKREG r5, 0x6D3BEF2B; +CHECKREG r6, 0xC0FCF9D5; +CHECKREG r7, 0xD24F66E7; + +imm32 r0, 0xeb23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b7e5; +imm32 r3, 0x9e060037; +imm32 r4, 0x80ebcd39; +imm32 r5, 0xb0aeef3b; +imm32 r6, 0xa00ce03d; +imm32 r7, 0x12467e03; +R4.H = R2.L * R2.L (S2RND); +R5.L = R2.L * R3.H (S2RND); +R6.L = R3.H * R2.L (S2RND); +R7.H = R3.L * R3.L (S2RND); +R2.H = R2.L * R2.H (S2RND); +R3.L = R2.H * R3.H (S2RND); +R0.H = R3.L * R2.L (S2RND); +R1.L = R3.L * R3.L (S2RND); +CHECKREG r0, 0xDACEA635; +CHECKREG r1, 0x6FBA1108; +CHECKREG r2, 0xEA6FB7E5; +CHECKREG r3, 0x9E062104; +CHECKREG r4, 0x513DCD39; +CHECKREG r5, 0xB0AE6E63; +CHECKREG r6, 0xA00C6E63; +CHECKREG r7, 0x00007E03; + +imm32 r0, 0xdd235655; +imm32 r1, 0xc4dd5157; +imm32 r2, 0x6324d755; +imm32 r3, 0x00060055; +imm32 r4, 0x90dbc509; +imm32 r5, 0x10adef5b; +imm32 r6, 0xb00cd05d; +imm32 r7, 0x12467d5f; +R0.L = R4.L * R4.H (S2RND); +R1.H = R4.H * R5.L (S2RND); +R2.L = R5.H * R4.L (S2RND); +R3.L = R5.L * R5.L (S2RND); +R4.H = R4.L * R4.H (S2RND); +R5.L = R4.L * R5.H (S2RND); +R6.H = R5.H * R4.H (S2RND); +R7.L = R5.H * R5.H (S2RND); +CHECKREG r0, 0xDD236666; +CHECKREG r1, 0x1CE85157; +CHECKREG r2, 0x6324F0A3; +CHECKREG r3, 0x00060454; +CHECKREG r4, 0x6666C509; +CHECKREG r5, 0x10ADF0A3; +CHECKREG r6, 0x1AAED05D; +CHECKREG r7, 0x12460458; + +imm32 r0, 0xcb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x1c248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90cb9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cc06d; +imm32 r7, 0x12467c6f; +// test the unsigned U=1 +R0.L = R6.L * R6.L (S2RND); +R1.H = R6.H * R7.L (S2RND); +R2.L = R7.L * R6.L (S2RND); +R3.L = R7.L * R7.L (S2RND); +R6.L = R6.L * R6.L (S2RND); +R7.L = R6.L * R7.L (S2RND); +R4.L = R7.L * R6.L (S2RND); +R5.L = R7.L * R7.L (S2RND); +CHECKREG r0, 0xCB233F27; +CHECKREG r1, 0x80005166; +CHECKREG r2, 0x1C248465; +CHECKREG r3, 0xF0067FFF; +CHECKREG r4, 0x90CB7929; +CHECKREG r5, 0x10AC7FFF; +CHECKREG r6, 0x800C3F27; +CHECKREG r7, 0x12467AC9; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0xe0060007; +imm32 r4, 0x9eabcd09; +imm32 r5, 0x10ecdfdb; +imm32 r6, 0x000e000d; +imm32 r7, 0x1246e00f; +R0.H = R0.L * R7.H (S2RND); +R1.L = R1.H * R6.H (S2RND); +R2.L = R2.L * R5.L (S2RND); +R3.H = R3.H * R4.H (S2RND); +R4.L = R4.L * R3.H (S2RND); +R5.L = R5.H * R2.H (S2RND); +R6.H = R6.H * R1.L (S2RND); +R7.L = R7.L * R0.H (S2RND); +CHECKREG r0, 0xE66FA675; +CHECKREG r1, 0xCFBAFFF5; +CHECKREG r2, 0x1324CC42; +CHECKREG r3, 0x30A10007; +CHECKREG r4, 0x9EABD947; +CHECKREG r5, 0x10EC0510; +CHECKREG r6, 0x0000000D; +CHECKREG r7, 0x12460CC3; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x93246905; +imm32 r3, 0x09060007; +imm32 r4, 0x909bcd09; +imm32 r5, 0x10a9e9db; +imm32 r6, 0x000c9d0d; +imm32 r7, 0x1246790f; +R0.L = R7.L * R0.H (S2RND); +R1.L = R6.L * R1.L (S2RND); +R2.H = R5.L * R2.L (S2RND); +R3.L = R4.H * R3.L (S2RND); +R4.L = R3.H * R4.H (S2RND); +R5.H = R2.H * R5.L (S2RND); +R6.L = R1.H * R6.L (S2RND); +R7.L = R0.L * R7.L (S2RND); +CHECKREG r0, 0x9B238000; +CHECKREG r1, 0xCFBA8288; +CHECKREG r2, 0xDBAA6905; +CHECKREG r3, 0x0906FFF4; +CHECKREG r4, 0x909BF04B; +CHECKREG r5, 0x0C93E9DB; +CHECKREG r6, 0x000C4AA2; +CHECKREG r7, 0x12468000; + +imm32 r0, 0xa9235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x08060007; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a88fdb; +imm32 r6, 0x000c080d; +imm32 r7, 0x1246708f; +R2.L = R4.L * R6.L (S2RND); +R3.L = R2.H * R2.L (S2RND); +R0.H = R2.L * R3.L, R0.L = R2.H * R3.H (S2RND); +R1.H = R3.L * R1.L (S2RND); +R4.L = R4.H * R0.L (S2RND); +R5.L = R5.L * R5.L (S2RND); +R6.L = R6.L * R5.H (S2RND); +R7.H = R6.H * R7.L (S2RND); +CHECKREG r0, 0x00310266; +CHECKREG r1, 0xFD915127; +CHECKREG r2, 0x1324F997; +CHECKREG r3, 0x0806FE15; +CHECKREG r4, 0x908BFBD3; +CHECKREG r5, 0x10A87FFF; +CHECKREG r6, 0x000C0218; +CHECKREG r7, 0x0015708F; + +imm32 r0, 0x7b235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x17246705; +imm32 r3, 0x00760007; +imm32 r4, 0x907bcd09; +imm32 r5, 0x10a7efdb; +imm32 r6, 0x000c700d; +imm32 r7, 0x1246770f; +R4.L = R5.L * R2.L (S2RND); +R6.L = R6.L * R3.H (S2RND); +R0.H = R7.L * R4.H (S2RND); +R1.L = R0.H * R5.L (S2RND); +R2.L = R1.L * R6.L (S2RND); +R5.L = R2.L * R7.H (S2RND); +R3.H = R3.H * R0.L (S2RND); +R7.L = R4.H * R1.H (S2RND); +CHECKREG r0, 0x80005675; +CHECKREG r1, 0xCFBA204A; +CHECKREG r2, 0x17240068; +CHECKREG r3, 0x009F0007; +CHECKREG r4, 0x907BE603; +CHECKREG r5, 0x10A7001E; +CHECKREG r6, 0x000C00CF; +CHECKREG r7, 0x1246541E; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_m_t.s b/sim/testsuite/bfin/c_dsp32mult_dr_m_t.s new file mode 100644 index 0000000..4dc42e8 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_m_t.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_m_t/c_dsp32mult_dr_m_t.dsp +// Spec Reference: dsp32mult single dr munop t +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xfb235625; +imm32 r1, 0x9fba5127; +imm32 r2, 0xa3ff6725; +imm32 r3, 0x0006f027; +imm32 r4, 0xb0abcd29; +imm32 r5, 0x1facef2b; +imm32 r6, 0xc0fc002d; +imm32 r7, 0xd24f702f; +R4.L = R0.H * R0.L (T); +R5.H = R0.L * R1.L (T); +R6.L = R1.L * R0.H (T); +R7.L = R1.L * R1.L (T); +R0.H = R0.L * R0.L (T); +R1.L = R0.L * R1.L (T); +R2.L = R1.H * R0.L (T); +R3.H = R1.L * R1.L (T); +CHECKREG r0, 0x39F95625; +CHECKREG r1, 0x9FBA369D; +CHECKREG r2, 0xA3FFBF35; +CHECKREG r3, 0x174DF027; +CHECKREG r4, 0xB0ABFCBA; +CHECKREG r5, 0x369DEF2B; +CHECKREG r6, 0xC0FCFCEA; +CHECKREG r7, 0xD24F3373; + +imm32 r0, 0xeb23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b7e5; +imm32 r3, 0x9e060037; +imm32 r4, 0x80ebcd39; +imm32 r5, 0xb0aeef3b; +imm32 r6, 0xa00ce03d; +imm32 r7, 0x12467e03; +R4.H = R2.L * R2.L (T); +R5.L = R2.L * R3.H (T); +R6.L = R3.H * R2.L (T); +R7.H = R3.L * R3.L (T); +R2.H = R2.L * R2.H (T); +R3.L = R2.H * R3.H (T); +R0.H = R3.L * R2.L (T); +R1.L = R3.L * R3.L (T); +CHECKREG r0, 0xFB59A635; +CHECKREG r1, 0x6FBA0088; +CHECKREG r2, 0xF537B7E5; +CHECKREG r3, 0x9E060841; +CHECKREG r4, 0x289ECD39; +CHECKREG r5, 0xB0AE3731; +CHECKREG r6, 0xA00C3731; +CHECKREG r7, 0x00007E03; + +imm32 r0, 0xdd235655; +imm32 r1, 0xc4dd5157; +imm32 r2, 0x6324d755; +imm32 r3, 0x00060055; +imm32 r4, 0x90dbc509; +imm32 r5, 0x10adef5b; +imm32 r6, 0xb00cd05d; +imm32 r7, 0x12467d5f; +R0.L = R4.L * R4.H (T); +R1.H = R4.H * R5.L (T); +R2.L = R5.H * R4.L (T); +R3.L = R5.L * R5.L (T); +R4.H = R4.L * R4.H (T); +R5.L = R4.L * R5.H (T); +R6.H = R5.H * R4.H (T); +R7.L = R5.H * R5.H (T); +CHECKREG r0, 0xDD233333; +CHECKREG r1, 0x0E735157; +CHECKREG r2, 0x6324F851; +CHECKREG r3, 0x0006022A; +CHECKREG r4, 0x3333C509; +CHECKREG r5, 0x10ADF851; +CHECKREG r6, 0x06ABD05D; +CHECKREG r7, 0x1246022C; + +imm32 r0, 0xcb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x1c248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90cb9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cc06d; +imm32 r7, 0x12467c6f; +// test the unsigned U=1 +R0.L = R6.L * R6.L (T); +R1.H = R6.H * R7.L (T); +R2.L = R7.L * R6.L (T); +R3.L = R7.L * R7.L (T); +R6.L = R6.L * R6.L (T); +R7.L = R6.L * R7.L (T); +R4.L = R7.L * R6.L (T); +R5.L = R7.L * R7.L (T); +CHECKREG r0, 0xCB231F93; +CHECKREG r1, 0x839C5166; +CHECKREG r2, 0x1C24C232; +CHECKREG r3, 0xF00678F7; +CHECKREG r4, 0x90CB0792; +CHECKREG r5, 0x10AC075B; +CHECKREG r6, 0x800C1F93; +CHECKREG r7, 0x12461EB1; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0xe0060007; +imm32 r4, 0x9eabcd09; +imm32 r5, 0x10ecdfdb; +imm32 r6, 0x000e000d; +imm32 r7, 0x1246e00f; +R0.H = R0.L * R7.H (T); +R1.L = R1.H * R6.H (T); +R2.L = R2.L * R5.L (T); +R3.H = R3.H * R4.H (T); +R4.L = R4.L * R3.H (T); +R5.L = R5.H * R2.H (T); +R6.H = R6.H * R1.L (T); +R7.L = R7.L * R0.H (T); +CHECKREG r0, 0xF337A675; +CHECKREG r1, 0xCFBAFFFA; +CHECKREG r2, 0x1324E620; +CHECKREG r3, 0x18500007; +CHECKREG r4, 0x9EABF651; +CHECKREG r5, 0x10EC0287; +CHECKREG r6, 0xFFFF000D; +CHECKREG r7, 0x12460330; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x93246905; +imm32 r3, 0x09060007; +imm32 r4, 0x909bcd09; +imm32 r5, 0x10a9e9db; +imm32 r6, 0x000c9d0d; +imm32 r7, 0x1246790f; +R0.L = R7.L * R0.H (T); +R1.L = R6.L * R1.L (T); +R2.H = R5.L * R2.L (T); +R3.L = R4.H * R3.L (T); +R4.L = R3.H * R4.H (T); +R5.H = R2.H * R5.L (T); +R6.L = R1.H * R6.L (T); +R7.L = R0.L * R7.L (T); +CHECKREG r0, 0x9B23A09B; +CHECKREG r1, 0xCFBAC144; +CHECKREG r2, 0xEDD46905; +CHECKREG r3, 0x0906FFF9; +CHECKREG r4, 0x909BF825; +CHECKREG r5, 0x0324E9DB; +CHECKREG r6, 0x000C2551; +CHECKREG r7, 0x1246A5C7; + +imm32 r0, 0xa9235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x08060007; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a88fdb; +imm32 r6, 0x000c080d; +imm32 r7, 0x1246708f; +R2.L = R3.L * R6.L (T); +R3.L = R4.H * R7.L (T); +R0.H = R7.L * R0.L, R0.L = R7.H * R0.H (T); +R1.H = R6.L * R1.L (T); +R4.L = R5.H * R2.L (T); +R5.L = R2.L * R3.L (T); +R6.L = R0.L * R4.L (T); +R7.H = R1.H * R5.L (T); +CHECKREG r0, 0x4C06F399; +CHECKREG r1, 0x051A5127; +CHECKREG r2, 0x13240000; +CHECKREG r3, 0x08069DFD; +CHECKREG r4, 0x908B0000; +CHECKREG r5, 0x10A80000; +CHECKREG r6, 0x000C0000; +CHECKREG r7, 0x0000708F; + +imm32 r0, 0x7b235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x17246705; +imm32 r3, 0x00760007; +imm32 r4, 0x907bcd09; +imm32 r5, 0x10a7efdb; +imm32 r6, 0x000c700d; +imm32 r7, 0x1246770f; +R4.L = R5.L * R3.L (T); +R6.L = R6.L * R4.H (T); +R0.H = R7.L * R5.H (T); +R1.L = R0.L * R6.L (T); +R2.L = R1.L * R7.H (T); +R5.L = R2.L * R2.H (T); +R3.H = R3.H * R0.L (T); +R7.L = R4.H * R1.H (T); +CHECKREG r0, 0x0F7D5675; +CHECKREG r1, 0xCFBABE0F; +CHECKREG r2, 0x1724F696; +CHECKREG r3, 0x004F0007; +CHECKREG r4, 0x907BFFFF; +CHECKREG r5, 0x10A7FE4C; +CHECKREG r6, 0x000C9E60; +CHECKREG r7, 0x12462A0E; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_m_u.s b/sim/testsuite/bfin/c_dsp32mult_dr_m_u.s new file mode 100644 index 0000000..c07b136 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_m_u.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_m_u/c_dsp32mult_dr_m_u.dsp +// Spec Reference: dsp32mult single dr munop u +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xfb235625; +imm32 r1, 0x9fba5127; +imm32 r2, 0xa3ff6725; +imm32 r3, 0x0006f027; +imm32 r4, 0xb0abcd29; +imm32 r5, 0x1facef2b; +imm32 r6, 0xc0fc002d; +imm32 r7, 0xd24f702f; +R4.L = R0.H * R0.L (FU); +R5.H = R0.L * R1.L (FU); +R6.L = R1.L * R0.H (FU); +R7.L = R1.L * R1.L (FU); +R0.H = R0.L * R0.L (FU); +R1.L = R0.L * R1.L (FU); +R2.L = R1.H * R0.L (FU); +R3.H = R1.L * R1.L (FU); +CHECKREG r0, 0x1CFD5625; +CHECKREG r1, 0x9FBA1B4F; +CHECKREG r2, 0xA3FF35C0; +CHECKREG r3, 0x02EAF027; +CHECKREG r4, 0xB0AB5482; +CHECKREG r5, 0x1B4FEF2B; +CHECKREG r6, 0xC0FC4F9C; +CHECKREG r7, 0xD24F19BA; + +imm32 r0, 0xbb23a635; +imm32 r1, 0x6bba5137; +imm32 r2, 0x13b4b7e5; +imm32 r3, 0x9e0b0037; +imm32 r4, 0x80ebbd39; +imm32 r5, 0xb0aeef3b; +imm32 r6, 0xa00ceb3d; +imm32 r7, 0x12467eb3; +R4.H = R2.L * R2.L (FU); +R5.L = R2.L * R3.H (FU); +R6.L = R3.H * R2.L (FU); +R7.H = R3.L * R3.L (FU); +R2.H = R2.L * R2.H (FU); +R3.L = R2.H * R3.H (FU); +R0.H = R3.L * R2.L (FU); +R1.L = R3.L * R3.L (FU); +CHECKREG r0, 0x0647A635; +CHECKREG r1, 0x6BBA004C; +CHECKREG r2, 0x0E27B7E5; +CHECKREG r3, 0x9E0B08BD; +CHECKREG r4, 0x8419BD39; +CHECKREG r5, 0xB0AE7187; +CHECKREG r6, 0xA00C7187; +CHECKREG r7, 0x00007EB3; + +imm32 r0, 0xbd235655; +imm32 r1, 0xc4dd5157; +imm32 r2, 0x6b24d755; +imm32 r3, 0x00b60055; +imm32 r4, 0x90dbc509; +imm32 r5, 0x10adbf5b; +imm32 r6, 0xb00cdb5d; +imm32 r7, 0x12467dbf; +R0.L = R4.L * R4.H (FU); +R1.H = R4.H * R5.L (FU); +R2.L = R5.H * R4.L (FU); +R3.L = R5.L * R5.L (FU); +R4.H = R4.L * R4.H (FU); +R5.L = R4.L * R5.H (FU); +R6.H = R5.H * R4.H (FU); +R7.L = R5.H * R5.H (FU); +CHECKREG r0, 0xBD236F7E; +CHECKREG r1, 0x6C475157; +CHECKREG r2, 0x6B240CD6; +CHECKREG r3, 0x00B68F09; +CHECKREG r4, 0x6F7EC509; +CHECKREG r5, 0x10AD0CD6; +CHECKREG r6, 0x0743DB5D; +CHECKREG r7, 0x12460116; + +imm32 r0, 0xcb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x1c248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90cb9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cc06d; +imm32 r7, 0x12467c6f; +// test the unsigned U=1 +R0.L = R6.L * R6.L (FU); +R1.H = R6.H * R7.L (FU); +R2.L = R7.L * R6.L (FU); +R3.L = R7.L * R7.L (FU); +R6.L = R6.L * R6.L (FU); +R7.L = R6.L * R7.L (FU); +R4.L = R7.L * R6.L (FU); +R5.L = R7.L * R7.L (FU); +CHECKREG r0, 0xCB2390A4; +CHECKREG r1, 0x3E3D5166; +CHECKREG r2, 0x1C245D88; +CHECKREG r3, 0xF0063C7C; +CHECKREG r4, 0x90CB27B9; +CHECKREG r5, 0x10AC134F; +CHECKREG r6, 0x800C90A4; +CHECKREG r7, 0x1246464E; + +// mix order +imm32 r0, 0x8b23a675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0xe0088807; +imm32 r4, 0x9eabcd09; +imm32 r5, 0x10ecdfdb; +imm32 r6, 0x000e008d; +imm32 r7, 0x1246e008; +R0.H = R0.L * R7.H (FU); +R1.L = R1.H * R6.H (FU); +R2.L = R2.L * R5.L (FU); +R3.H = R3.H * R4.H (FU); +R4.L = R4.L * R3.H (FU); +R5.L = R5.H * R2.H (FU); +R6.H = R6.H * R1.L (FU); +R7.L = R7.L * R0.H (FU); +CHECKREG r0, 0x0BE2A675; +CHECKREG r1, 0xC8BA000B; +CHECKREG r2, 0x13845A15; +CHECKREG r3, 0x8ADB8807; +CHECKREG r4, 0x9EAB6F36; +CHECKREG r5, 0x10EC014A; +CHECKREG r6, 0x0000008D; +CHECKREG r7, 0x12460A66; + +imm32 r0, 0x9b235a75; +imm32 r1, 0x7fba5127; +imm32 r2, 0x97246905; +imm32 r3, 0x09777007; +imm32 r4, 0x909bc779; +imm32 r5, 0x10a9e9d7; +imm32 r6, 0x000c9d0d; +imm32 r7, 0x1246790f; +R0.L = R7.L * R0.H (FU); +R1.L = R6.L * R1.L (FU); +R2.H = R5.L * R2.L (FU); +R3.L = R4.H * R3.L (FU); +R4.L = R3.H * R4.H (FU); +R5.H = R2.H * R5.L (FU); +R6.L = R1.H * R6.L (FU); +R7.L = R0.L * R7.L (FU); +CHECKREG r0, 0x9B23495D; +CHECKREG r1, 0x7FBA31C9; +CHECKREG r2, 0x5FEE6905; +CHECKREG r3, 0x09773F48; +CHECKREG r4, 0x909B0559; +CHECKREG r5, 0x57A0E9D7; +CHECKREG r6, 0x000C4E5C; +CHECKREG r7, 0x124622B1; + +imm32 r0, 0xa9235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x08060007; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a88fdb; +imm32 r6, 0x000c080d; +imm32 r7, 0x1246708f; +R2.L = R0.L * R6.L (FU); +R3.L = R1.H * R7.H (FU); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.L (FU); +R1.H = R3.L * R4.L (FU); +R4.L = R1.H * R2.L (FU); +R5.L = R5.L * R3.L (FU); +R6.L = R6.L * R4.L (FU); +R7.H = R7.H * R5.L (FU); +CHECKREG r0, 0x00EB0677; +CHECKREG r1, 0x0B7A5127; +CHECKREG r2, 0x132402B8; +CHECKREG r3, 0x08060E54; +CHECKREG r4, 0x908B001F; +CHECKREG r5, 0x10A8080D; +CHECKREG r6, 0x000C0001; +CHECKREG r7, 0x0093708F; + +imm32 r0, 0x7b235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x17246705; +imm32 r3, 0x00760007; +imm32 r4, 0x907bcd09; +imm32 r5, 0x10a7efdb; +imm32 r6, 0x000c700d; +imm32 r7, 0x1246770f; +R4.L = R5.L * R2.L (FU); +R6.L = R6.L * R3.H (FU); +R0.H = R7.L * R4.H (FU); +R1.L = R0.H * R5.L (FU); +R2.L = R1.L * R6.L (FU); +R5.L = R2.L * R7.H (FU); +R3.H = R3.H * R0.L (FU); +R7.L = R4.H * R1.H (FU); +CHECKREG r0, 0x43325675; +CHECKREG r1, 0xCFBA3EF5; +CHECKREG r2, 0x1724000D; +CHECKREG r3, 0x00280007; +CHECKREG r4, 0x907B6086; +CHECKREG r5, 0x10A70001; +CHECKREG r6, 0x000C0034; +CHECKREG r7, 0x1246753C; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_mix.s b/sim/testsuite/bfin/c_dsp32mult_dr_mix.s new file mode 100644 index 0000000..794cbfc --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_mix.s @@ -0,0 +1,196 @@ +//Original:/testcases/core/c_dsp32mult_dr_mix/c_dsp32mult_dr_mix.dsp +// Spec Reference: dsp32mult single dr (mix) u i t is tu ih +# mach: bfin + +.include "testutils.inc" + start + +// test the default (signed fraction) rounding U=0 I=0 T=0 +imm32 r0, 0xab235615; +imm32 r1, 0xcfba5117; +imm32 r2, 0x13246715; +imm32 r3, 0x00060017; +imm32 r4, 0x90abcd19; +imm32 r5, 0x10acef1b; +imm32 r6, 0x000c001d; +imm32 r7, 0x1246701f; +R2.H = R1.L * R0.L, R2.L = R1.L * R0.L; +R3.L = R1.L * R0.H (ISS2); +R4.H = R1.H * R0.L; +R5.H = R1.L * R0.H (M), R5.L = R1.H * R0.H; +R6.H = R1.H * R0.L, R6.L = R1.L * R0.L; +R7.H = R1.H * R0.H (M), R7.L = R1.H * R0.H; +CHECKREG r2, 0x36893689; +CHECKREG r3, 0x00068000; +CHECKREG r4, 0xDF89CD19; +CHECKREG r5, 0x36352001; +CHECKREG r6, 0xDF893689; +CHECKREG r7, 0xDFBB2001; + +// test the signed integer U=0 I=1 +imm32 r0, 0x8b235625; +imm32 r1, 0x9fba5127; +imm32 r2, 0xa3246725; +imm32 r3, 0x00060027; +imm32 r4, 0xb0abcd29; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c002d; +imm32 r7, 0xd246702f; +R2.H = R1.L * R0.L, R2.L = R1.L * R0.L (TFU); +R3.H = R1.L * R0.L, R3.L = R1.L * R0.H (IS); +R4.H = R1.L * R0.L, R4.L = R1.H * R0.L (ISS2); +R5.H = R1.L * R0.L, R5.L = R1.H * R0.H (IS); +R6.H = R1.L * R0.H, R6.L = R1.L * R0.L (IS); +R7.H = R1.L * R0.H, R7.L = R1.L * R0.H (IH); +CHECKREG r0, 0x8B235625; +CHECKREG r1, 0x9FBA5127; +CHECKREG r2, 0x1B4E1B4E; +CHECKREG r3, 0x7FFF8000; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x80007FFF; +CHECKREG r7, 0xDAF4DAF4; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0.H = R3.L * R2.H, R0.L = R3.H * R2.L (IS); +R1.H = R3.L * R2.H, R1.L = R3.H * R2.H (ISS2); +R4.H = R3.H * R2.L, R4.L = R3.L * R2.L (IS); +R5.H = R3.H * R2.L, R5.L = R3.L * R2.H (IS); +R6.H = R3.H * R2.L, R6.L = R3.H * R2.L (IH); +R7.H = R3.H * R2.L, R7.L = R3.H * R2.H (IS); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF8000; +CHECKREG r2, 0x1324B735; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x1FD71FD7; +CHECKREG r7, 0x7FFF8000; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R0.H = R5.H * R4.H, R0.L = R5.L * R4.L (IS); +R1.H = R5.H * R4.H, R1.L = R5.L * R4.H (ISS2); +R2.H = R5.H * R4.H, R2.L = R5.H * R4.L (IS); +R3.H = R5.H * R4.H, R3.L = R5.H * R4.H (IS); +R4.H = R6.H * R7.L, R4.L = R6.H * R7.L (IH); +R5.H = R6.L * R7.H, R5.L = R6.H * R7.H (IS); +CHECKREG r0, 0x80007FFF; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0xDCE8DCE8; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0xB00C005D; +CHECKREG r7, 0x1246705F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +// test the unsigned U=1 +R2.H = R1.L * R0.L, R2.L = R1.L * R0.L (FU); +R3.H = R1.L * R0.L, R3.L = R1.L * R0.H (ISS2); +R4.H = R7.L * R6.L, R4.L = R7.H * R6.L (FU); +R5.H = R3.L * R2.L (M), R5.L = R3.H * R2.H (FU); +R6.H = R5.L * R4.H, R6.L = R5.L * R4.L (TFU); +R7.H = R5.L * R4.H, R7.L = R5.L * R4.H (FU); +CHECKREG r0, 0xBB235666; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0x1B791B79; +CHECKREG r3, 0x7FFF8000; +CHECKREG r4, 0x4D7C0C98; +CHECKREG r5, 0xF2440DBC; +CHECKREG r6, 0x042800AC; +CHECKREG r7, 0x04280428; + +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0.H = R5.L * R4.H, R0.L = R5.H * R4.L (FU); +R1.H = R3.L * R2.H, R1.L = R3.H * R2.H (IU); +R2.H = R7.H * R6.L, R2.L = R7.L * R6.L (TFU); +R3.H = R5.H * R4.L, R3.L = R5.L * R4.H (FU); +R6.H = R1.H * R0.L, R6.L = R1.H * R0.L (IH); +R7.H = R3.H * R2.L, R7.L = R3.H * R2.H (FU); +CHECKREG r0, 0x7E810D5A; +CHECKREG r1, 0x85FC72D8; +CHECKREG r2, 0x0000000C; +CHECKREG r3, 0x0D5A7E81; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0xF9A3F9A3; +CHECKREG r7, 0x00010000; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R2.H = R1.H * R0.H, R2.L = R1.L * R0.L (TFU); +R3.H = R1.H * R0.L, R3.L = R1.L * R0.H (FU); +R4.H = R6.H * R7.H, R4.L = R6.H * R7.L (ISS2); +R5.H = R6.L * R7.H, R5.L = R6.H * R7.H (FU); +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x8ADD1CAC; +CHECKREG r3, 0x49663640; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x00EE0001; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x1246700F; + +// test the ROUNDING only on signed fraction T=1 +imm32 r0, 0xab235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246700f; +R2.H = R1.L * R0.L (M), R2.L = R1.L * R0.H (IS); +R3.H = R1.H * R0.L (M), R3.L = R1.H * R0.H (FU); +R0.H = R3.L * R2.L (M), R0.L = R3.H * R2.H (T); +R1.H = R5.L * R4.H (M), R1.L = R5.L * R4.L (S2RND); +R4.H = R7.H * R6.H (M), R4.L = R7.L * R6.L (IU); +R5.H = R7.L * R6.H (M), R5.L = R7.H * R6.L (TFU); +R6.H = R5.H * R4.L (M), R6.L = R5.L * R4.H (ISS2); +R7.H = R3.L * R2.H (M), R7.L = R3.L * R2.L (IH); +CHECKREG r0, 0xC56FEFB2; +CHECKREG r1, 0xEDC10CDB; +CHECKREG r2, 0x7FFF8000; +CHECKREG r3, 0xEFB28ADE; +CHECKREG r4, 0x7FFFFFFF; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x7FFF0000; +CHECKREG r7, 0xC56F3A91; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_s.s b/sim/testsuite/bfin/c_dsp32mult_dr_s.s new file mode 100644 index 0000000..1f3f967 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_s.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_s/c_dsp32mult_dr_s.dsp +// Spec Reference: dsp32mult single dr s +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (S2RND); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (S2RND); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (S2RND); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (S2RND); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (S2RND); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (S2RND); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (S2RND); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (S2RND); +CHECKREG r0, 0x73F473F4; +CHECKREG r1, 0x7FFF8000; +CHECKREG r2, 0x80007FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x73F473F4; +CHECKREG r5, 0x6D3B8000; +CHECKREG r6, 0x6D3B8000; +CHECKREG r7, 0x66E77FFF; + +imm32 r0, 0x9923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1324b735; +imm32 r3, 0x99060037; +imm32 r4, 0x809bcd39; +imm32 r5, 0xb0a99f3b; +imm32 r6, 0xa00c093d; +imm32 r7, 0x12467093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (S2RND); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (S2RND); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (S2RND); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (S2RND); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (S2RND); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (S2RND); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (S2RND); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (S2RND); +CHECKREG r0, 0xF416F416; +CHECKREG r1, 0x132C132C; +CHECKREG r2, 0xEA3BEA3B; +CHECKREG r3, 0x23072307; +CHECKREG r4, 0xEA3BEA3B; +CHECKREG r5, 0x7520E134; +CHECKREG r6, 0xFFC10010; +CHECKREG r7, 0xFFA8FFA8; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (S2RND); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (S2RND); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (S2RND); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (S2RND); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (S2RND); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (S2RND); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (S2RND); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (S2RND); +CHECKREG r0, 0x66933653; +CHECKREG r1, 0x1CF4F0A4; +CHECKREG r2, 0xF0A4F0A4; +CHECKREG r3, 0x04540458; +CHECKREG r4, 0x66933653; +CHECKREG r5, 0xE553F1DF; +CHECKREG r6, 0xF402E95B; +CHECKREG r7, 0x05E40B1E; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xe0060066; +imm32 r4, 0x9eab9d69; +imm32 r5, 0x10ecef6b; +imm32 r6, 0x800ee06d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (S2RND); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (S2RND); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (S2RND); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (S2RND); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (S2RND); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (S2RND); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (S2RND); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (S2RND); +CHECKREG r0, 0x7FFF0F94; +CHECKREG r1, 0xDB78F6FC; +CHECKREG r2, 0xDB78F6FC; +CHECKREG r3, 0x05380538; +CHECKREG r4, 0x491708E5; +CHECKREG r5, 0x14DF14DF; +CHECKREG r6, 0x7FFF0F94; +CHECKREG r7, 0x248C0473; + +// mix order +imm32 r0, 0xac23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13c46705; +imm32 r3, 0x00060007; +imm32 r4, 0x90accd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000cc00d; +imm32 r7, 0x1246fc0f; +R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (S2RND); +R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (S2RND); +R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (S2RND); +R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (S2RND); +R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (S2RND); +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (S2RND); +R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (S2RND); +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (S2RND); +CHECKREG r0, 0x0584E80E; +CHECKREG r1, 0xAEE9000F; +CHECKREG r2, 0xF613F613; +CHECKREG r3, 0xFFFAFFFA; +CHECKREG r4, 0x00050005; +CHECKREG r5, 0xFD6AFD6A; +CHECKREG r6, 0xFFF1FFF1; +CHECKREG r7, 0xF92A0193; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (S2RND); +R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (S2RND); +R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (S2RND); +R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (S2RND); +R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (S2RND); +R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (S2RND); +R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (S2RND); +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (S2RND); +CHECKREG r0, 0xE7C519D4; +CHECKREG r1, 0xFFF7108C; +CHECKREG r2, 0xF6EB1B5B; +CHECKREG r3, 0xFE8C5374; +CHECKREG r4, 0x02870128; +CHECKREG r5, 0xFDA20293; +CHECKREG r6, 0x0000FFFE; +CHECKREG r7, 0x0760F915; + +imm32 r0, 0xfb235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13f46705; +imm32 r3, 0x000f0007; +imm32 r4, 0x90abfd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (S2RND); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (S2RND); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (S2RND); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (S2RND); +R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (S2RND); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (S2RND); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (S2RND); +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (S2RND); +CHECKREG r0, 0x0016FFE6; +CHECKREG r1, 0x94D30A65; +CHECKREG r2, 0x01560010; +CHECKREG r3, 0xF238AB7A; +CHECKREG r4, 0xFFFFFDAD; +CHECKREG r5, 0x037AE9FB; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xD97200FE; + +imm32 r0, 0xab2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13246d05; +imm32 r3, 0x000600d7; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c500d; +imm32 r7, 0x1246760f; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (S2RND); +R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (S2RND); +R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (S2RND); +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (S2RND); +R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (S2RND); +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (S2RND); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (S2RND); +R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (S2RND); +CHECKREG r0, 0xF718CD46; +CHECKREG r1, 0xF2CC0CCC; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0xFF56FFE2; +CHECKREG r4, 0xE480FB2C; +CHECKREG r5, 0x00000004; +CHECKREG r6, 0x00000008; +CHECKREG r7, 0xFA8000FF; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_t.s b/sim/testsuite/bfin/c_dsp32mult_dr_t.s new file mode 100644 index 0000000..fd2fe02 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_t.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_t/c_dsp32mult_dr_t.dsp +// Spec Reference: dsp32mult single dr t +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (T); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (T); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (T); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (T); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (T); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (T); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (T); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (T); +CHECKREG r0, 0x39F939F9; +CHECKREG r1, 0x24C1D139; +CHECKREG r2, 0xEAD010A5; +CHECKREG r3, 0x11180A8D; +CHECKREG r4, 0x39F939F9; +CHECKREG r5, 0x369DBA7F; +CHECKREG r6, 0x369DBA7F; +CHECKREG r7, 0x33735352; + +imm32 r0, 0x9923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1324b735; +imm32 r3, 0x99060037; +imm32 r4, 0x809bcd39; +imm32 r5, 0xb0a99f3b; +imm32 r6, 0xa00c093d; +imm32 r7, 0x12467093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (T); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (T); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (T); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (T); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (T); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (T); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (T); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (T); +CHECKREG r0, 0xFF41FF41; +CHECKREG r1, 0x00990099; +CHECKREG r2, 0xF51DF51D; +CHECKREG r3, 0x08C208C2; +CHECKREG r4, 0xF51DF51D; +CHECKREG r5, 0x3A8FF099; +CHECKREG r6, 0xFFE00008; +CHECKREG r7, 0xFFD3FFD3; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (T); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (T); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (T); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (T); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (T); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (T); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (T); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (T); +CHECKREG r0, 0x33491B29; +CHECKREG r1, 0x0E7AF851; +CHECKREG r2, 0xF851F851; +CHECKREG r3, 0x022A022B; +CHECKREG r4, 0x33491B29; +CHECKREG r5, 0xF954FC77; +CHECKREG r6, 0xFF3FFE95; +CHECKREG r7, 0x002F0059; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xe0060066; +imm32 r4, 0x9eab9d69; +imm32 r5, 0x10ecef6b; +imm32 r6, 0x800ee06d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (T); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (T); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (T); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (T); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (T); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (T); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (T); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (T); +CHECKREG r0, 0x7FE407C9; +CHECKREG r1, 0xEDBBFB7E; +CHECKREG r2, 0xEDBBFB7E; +CHECKREG r3, 0x029B029B; +CHECKREG r4, 0x123E011C; +CHECKREG r5, 0x029A029A; +CHECKREG r6, 0x7FE407C9; +CHECKREG r7, 0x1242011C; + +// mix order +imm32 r0, 0xac23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13c46705; +imm32 r3, 0x00060007; +imm32 r4, 0x90accd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000cc00d; +imm32 r7, 0x1246fc0f; +R0.H = R5.L * R7.L, R0.L = R5.H * R7.H (T); +R1.H = R7.L * R6.L, R1.L = R7.L * R6.H (T); +R2.H = R6.H * R5.H, R2.L = R6.H * R5.L (T); +R3.H = R0.L * R4.L, R3.L = R0.L * R4.L (T); +R4.H = R1.L * R5.H, R4.L = R1.L * R5.L (T); +R5.H = R3.H * R4.L, R5.L = R3.H * R4.L (T); +R6.H = R2.L * R5.L, R6.L = R2.L * R5.L (T); +R7.H = R4.H * R0.L, R7.L = R4.H * R0.H (T); +CHECKREG r0, 0x00FD0261; +CHECKREG r1, 0x01F8FFFF; +CHECKREG r2, 0x0001FFFC; +CHECKREG r3, 0xFF0DFF0D; +CHECKREG r4, 0xFFFF0000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R4.H = R7.H * R0.H, R4.L = R7.H * R0.L (T); +R5.H = R6.H * R1.H, R5.L = R6.L * R1.L (T); +R6.H = R5.H * R2.H, R6.L = R5.H * R2.L (T); +R7.H = R4.H * R3.H, R7.L = R4.H * R3.L (T); +R0.H = R3.H * R4.H, R0.L = R3.H * R4.L (T); +R2.H = R2.H * R5.H, R2.L = R2.H * R5.L (T); +R1.H = R1.H * R6.H, R1.L = R1.H * R6.L (T); +R3.H = R0.L * R7.H, R3.L = R0.H * R7.H (T); +CHECKREG r0, 0xFFEB0015; +CHECKREG r1, 0xFFFF0001; +CHECKREG r2, 0x0001FDBF; +CHECKREG r3, 0xFFFF0000; +CHECKREG r4, 0xF3E20CE9; +CHECKREG r5, 0xFFFB0846; +CHECKREG r6, 0x0001FFFB; +CHECKREG r7, 0xFFEB048A; + +imm32 r0, 0xfb235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13f46705; +imm32 r3, 0x000f0007; +imm32 r4, 0x90abfd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (T); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (T); +R0.H = R2.L * R0.L, R0.L = R2.L * R0.H (T); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (T); +R4.H = R4.L * R2.L, R4.L = R4.L * R2.H (T); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (T); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (T); +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (T); +CHECKREG r0, 0x0005FFFF; +CHECKREG r1, 0xE5340299; +CHECKREG r2, 0x00AA0008; +CHECKREG r3, 0xF91BD5BD; +CHECKREG r4, 0xFFFFFFFC; +CHECKREG r5, 0x00DEFA7E; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFB2D001F; + +imm32 r0, 0xab2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13246d05; +imm32 r3, 0x000600d7; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c500d; +imm32 r7, 0x1246760f; +R5.H = R5.L * R2.L, R5.L = R5.L * R2.H (T); +R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (T); +R1.H = R7.L * R4.L, R1.L = R7.L * R4.H (T); +R0.H = R1.L * R5.H, R0.L = R1.L * R5.L (T); +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (T); +R4.H = R2.L * R7.H, R4.L = R2.H * R7.L (T); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (T); +R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (T); +CHECKREG r0, 0x0B0B01F1; +CHECKREG r1, 0xD0FE9933; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00030012; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0xF23FFD95; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000000; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_tu.s b/sim/testsuite/bfin/c_dsp32mult_dr_tu.s new file mode 100644 index 0000000..81ad933 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_tu.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_tu/c_dsp32mult_dr_tu.dsp +// Spec Reference: dsp32mult single dr tu +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (TFU); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (TFU); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (TFU); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (TFU); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (TFU); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (TFU); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (TFU); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (TFU); +CHECKREG r0, 0x1CFC1CFC; +CHECKREG r1, 0x0930114A; +CHECKREG r2, 0x01F5010A; +CHECKREG r3, 0x012A0054; +CHECKREG r4, 0x1CFC1CFC; +CHECKREG r5, 0x1B4E3364; +CHECKREG r6, 0x1B4E3364; +CHECKREG r7, 0x19B95B1D; + +imm32 r0, 0x9923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1324b735; +imm32 r3, 0x99060037; +imm32 r4, 0x809bcd39; +imm32 r5, 0xb0a99f3b; +imm32 r6, 0xa00c093d; +imm32 r7, 0x12467093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (TFU); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (TFU); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (TFU); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (TFU); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (TFU); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (TFU); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (TFU); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (TFU); +CHECKREG r0, 0x00700070; +CHECKREG r1, 0x00420042; +CHECKREG r2, 0x0DB20DB2; +CHECKREG r3, 0x082F082F; +CHECKREG r4, 0x0DB20DB2; +CHECKREG r5, 0x6D820B70; +CHECKREG r6, 0x00270004; +CHECKREG r7, 0x00200020; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (TFU); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (TFU); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (TFU); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (TFU); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (TFU); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (TFU); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (TFU); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (TFU); +CHECKREG r0, 0x6F5897A6; +CHECKREG r1, 0x87430CD4; +CHECKREG r2, 0x0CD40CD4; +CHECKREG r3, 0xDFCB0115; +CHECKREG r4, 0x6F5897A6; +CHECKREG r5, 0x681A8DC9; +CHECKREG r6, 0x53FD3DAA; +CHECKREG r7, 0x39A82A55; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xe0060066; +imm32 r4, 0x9eab9d69; +imm32 r5, 0x10ecef6b; +imm32 r6, 0x800ee06d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (TFU); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (TFU); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (TFU); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (TFU); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (TFU); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (TFU); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (TFU); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (TFU); +CHECKREG r0, 0x400EC4BE; +CHECKREG r1, 0x09231005; +CHECKREG r2, 0x09231005; +CHECKREG r3, 0x014D014D; +CHECKREG r4, 0x01240383; +CHECKREG r5, 0x00140014; +CHECKREG r6, 0x400EC4BE; +CHECKREG r7, 0x04920E0B; + +// mix order +imm32 r0, 0xac23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13c46705; +imm32 r3, 0x00060007; +imm32 r4, 0x90accd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000cc00d; +imm32 r7, 0x1246fc0f; +R2.H = R0.L * R7.L, R2.L = R0.H * R7.H (TFU); +R5.H = R1.L * R6.L, R5.L = R1.L * R6.H (TFU); +R6.H = R2.H * R5.L, R6.L = R2.H * R5.L (TFU); +R7.H = R3.L * R4.L, R7.L = R3.L * R4.L (TFU); +R0.H = R4.L * R3.L, R0.L = R4.L * R3.L (TFU); +R1.H = R5.H * R2.L, R1.L = R5.H * R2.L (TFU); +R3.H = R6.L * R1.L, R3.L = R6.L * R1.L (TFU); +R4.H = R7.H * R0.L, R4.L = R7.H * R0.H (TFU); +CHECKREG r0, 0x00050005; +CHECKREG r1, 0x02EB02EB; +CHECKREG r2, 0xA3E40C49; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x3CE10003; +CHECKREG r6, 0x00010001; +CHECKREG r7, 0x00050005; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (TFU); +R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (TFU); +R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (TFU); +R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (TFU); +R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (TFU); +R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (TFU); +R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (TFU); +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (TFU); +CHECKREG r0, 0x0C370674; +CHECKREG r1, 0x00090423; +CHECKREG r2, 0x0E6606D6; +CHECKREG r3, 0x0078758E; +CHECKREG r4, 0x00430060; +CHECKREG r5, 0x00F00D60; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x007500DF; + +imm32 r0, 0xfb235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13f46705; +imm32 r3, 0x000f0007; +imm32 r4, 0x90abfd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (TFU); +R3.H = R2.H * R7.H, R3.L = R2.H * R7.L (TFU); +R0.H = R1.L * R0.L, R0.L = R1.H * R0.H (TFU); +R1.H = R3.L * R0.L, R1.L = R3.H * R0.H (TFU); +R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (TFU); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (TFU); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (TFU); +R7.H = R7.L * R6.L, R7.L = R7.H * R6.H (TFU); +CHECKREG r0, 0x1B68CBC7; +CHECKREG r1, 0x001D0000; +CHECKREG r2, 0x00550004; +CHECKREG r3, 0x00060025; +CHECKREG r4, 0x00030030; +CHECKREG r5, 0x00050002; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xab2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13246d05; +imm32 r3, 0x000600d7; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c500d; +imm32 r7, 0x1246760f; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (TFU); +R6.H = R6.H * R3.L, R6.L = R6.H * R3.L (TFU); +R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (TFU); +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (TFU); +R2.H = R1.L * R6.L, R2.L = R1.H * R6.H (TFU); +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (TFU); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.L (TFU); +R7.H = R4.H * R1.L, R7.L = R4.H * R1.L (TFU); +CHECKREG r0, 0x08442F1A; +CHECKREG r1, 0x03102C21; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00270027; +CHECKREG r4, 0x662411EE; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x119B119B; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_dr_u.s b/sim/testsuite/bfin/c_dsp32mult_dr_u.s new file mode 100644 index 0000000..47ae1b9 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_dr_u.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_u/c_dsp32mult_dr_u.dsp +// Spec Reference: dsp32mult single dr u +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (FU); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (FU); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (FU); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (FU); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (FU); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (FU); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (FU); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (FU); +CHECKREG r0, 0x1CFD1CFD; +CHECKREG r1, 0x0930114B; +CHECKREG r2, 0x01F5010A; +CHECKREG r3, 0x012B0054; +CHECKREG r4, 0x1CFD1CFD; +CHECKREG r5, 0x1B4F3365; +CHECKREG r6, 0x1B4F3365; +CHECKREG r7, 0x19BA5B1D; + +imm32 r0, 0x9923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1324b735; +imm32 r3, 0x99060037; +imm32 r4, 0x809bcd39; +imm32 r5, 0xb0a99f3b; +imm32 r6, 0xa00c093d; +imm32 r7, 0x12467093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (FU); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (FU); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (FU); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (FU); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (FU); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (FU); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (FU); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (FU); +CHECKREG r0, 0x00700070; +CHECKREG r1, 0x00430043; +CHECKREG r2, 0x0DB30DB3; +CHECKREG r3, 0x08300830; +CHECKREG r4, 0x0DB30DB3; +CHECKREG r5, 0x6D830B71; +CHECKREG r6, 0x00270004; +CHECKREG r7, 0x00210021; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (FU); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (FU); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (FU); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (FU); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (FU); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (FU); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (FU); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (FU); +CHECKREG r0, 0x6F5997A7; +CHECKREG r1, 0x87430CD5; +CHECKREG r2, 0x0CD50CD5; +CHECKREG r3, 0xDFCB0116; +CHECKREG r4, 0x6F5997A7; +CHECKREG r5, 0x681C8DCB; +CHECKREG r6, 0x53FF3DAC; +CHECKREG r7, 0x39AA2A57; + +imm32 r0, 0xb9235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x19248766; +imm32 r3, 0xe0960066; +imm32 r4, 0x9ea99d69; +imm32 r5, 0x10ec9f6b; +imm32 r6, 0x800e906d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (FU); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (FU); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (FU); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (FU); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (FU); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (FU); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (FU); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (FU); +CHECKREG r0, 0x400E517B; +CHECKREG r1, 0x09240A4F; +CHECKREG r2, 0x09240A4F; +CHECKREG r3, 0x014E014E; +CHECKREG r4, 0x01250174; +CHECKREG r5, 0x00150015; +CHECKREG r6, 0x400E517B; +CHECKREG r7, 0x049205D1; + +// mix order +imm32 r0, 0x9923a675; +imm32 r1, 0xcf995127; +imm32 r2, 0x13c49705; +imm32 r3, 0x05069007; +imm32 r4, 0x90accd09; +imm32 r5, 0x10ac9fdb; +imm32 r6, 0x000cc90d; +imm32 r7, 0x1246fc9f; +R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (FU); +R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (FU); +R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (FU); +R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (FU); +R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (FU); +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (FU); +R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (FU); +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (FU); +CHECKREG r0, 0xA4430AEE; +CHECKREG r1, 0x3FBC0004; +CHECKREG r2, 0x0C580C58; +CHECKREG r3, 0x735B735B; +CHECKREG r4, 0x5C645C64; +CHECKREG r5, 0x00CE00CE; +CHECKREG r6, 0x00030003; +CHECKREG r7, 0x00C80BBA; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (FU); +R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (FU); +R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (FU); +R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (FU); +R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (FU); +R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (FU); +R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (FU); +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (FU); +CHECKREG r0, 0x0C370675; +CHECKREG r1, 0x000A0423; +CHECKREG r2, 0x0E6706D7; +CHECKREG r3, 0x0079758F; +CHECKREG r4, 0x00440061; +CHECKREG r5, 0x00F00D62; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x007600DF; + +imm32 r0, 0xee235675; +imm32 r1, 0xcfea5127; +imm32 r2, 0x13fe6705; +imm32 r3, 0x000fe007; +imm32 r4, 0x90abfe09; +imm32 r5, 0x10acefeb; +imm32 r6, 0x000c00fe; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (FU); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (FU); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (FU); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (FU); +R4.H = R4.L * R2.L, R4.L = R4.L * R2.H (FU); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (FU); +R6.H = R6.H * R5.L, R6.L = R6.L * R5.H (FU); +R7.H = R7.L * R4.L, R7.L = R7.H * R4.H (FU); +CHECKREG r0, 0x00010050; +CHECKREG r1, 0x1CDA0C0D; +CHECKREG r2, 0x00560004; +CHECKREG r3, 0x0ED75B03; +CHECKREG r4, 0x00040055; +CHECKREG r5, 0x0DE805ED; +CHECKREG r6, 0x0000000E; +CHECKREG r7, 0x00250000; + +imm32 r0, 0xfb2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13f46d05; +imm32 r3, 0x000f00d7; +imm32 r4, 0x908bfd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c5f0d; +imm32 r7, 0x124676ff; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (FU); +R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (FU); +R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (FU); +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (FU); +R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (FU); +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (FU); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (FU); +R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (FU); +CHECKREG r0, 0x08B12F7B; +CHECKREG r1, 0x03172C7C; +CHECKREG r2, 0x00010000; +CHECKREG r3, 0x00280007; +CHECKREG r4, 0x662512B2; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x11C0003A; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_pair.s b/sim/testsuite/bfin/c_dsp32mult_pair.s new file mode 100644 index 0000000..99d3504 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_pair.s @@ -0,0 +1,179 @@ +//Original:/testcases/core/c_dsp32mult_pair/c_dsp32mult_pair.dsp +// Spec Reference: dsp32mult pair +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x93ba5127; +imm32 r2, 0xa3446725; +imm32 r3, 0x00050027; +imm32 r4, 0xb0ab6d29; +imm32 r5, 0x10ace72b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467029; +R1 = R0.L * R0.L, R0 = R0.L * R0.L; +R3 = R0.L * R1.L, R2 = R0.L * R1.H; +R5 = R1.L * R0.L, R4 = R1.H * R0.L; +R7 = R1.L * R1.L, R6 = R1.H * R1.H; +CHECKREG r0, 0x39F9C2B2; +CHECKREG r1, 0x39F9C2B2; +CHECKREG r2, 0xE43C0244; +CHECKREG r3, 0x1D5C8788; +CHECKREG r4, 0xE43C0244; +CHECKREG r5, 0x1D5C8788; +CHECKREG r6, 0x1A41A862; +CHECKREG r7, 0x1D5C8788; + +imm32 r0, 0x5b33a635; +imm32 r1, 0x6fbe5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x9006d037; +imm32 r4, 0x80abcb39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c00dd; +imm32 r7, 0x12469003; +R1 = R2.L * R2.L, R0 = R2.L * R2.L; +R3 = R2.L * R3.L, R2 = R2.L * R3.H; +R5 = R3.L * R2.L, R4 = R3.H * R2.L; +R7 = R3.L * R3.L, R6 = R3.H * R3.H; +CHECKREG r0, 0x2965A1F2; +CHECKREG r1, 0x2965A1F2; +CHECKREG r2, 0x3FAE367C; +CHECKREG r3, 0x1B2CD8C6; +CHECKREG r4, 0x0B90E2A0; +CHECKREG r5, 0xEF4D87D0; +CHECKREG r6, 0x05C49F20; +CHECKREG r7, 0x0C057248; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R1 = R4.L * R4.L, R0 = R4.L * R4.L; +R3 = R4.L * R5.L, R2 = R4.L * R5.H; +R5 = R5.L * R4.L, R4 = R5.H * R4.L; +R7 = R5.L * R5.L, R6 = R5.H * R5.H; +CHECKREG r0, 0x1B29B4A2; +CHECKREG r1, 0x1B29B4A2; +CHECKREG r2, 0xF851E418; +CHECKREG r3, 0x07AAE266; +CHECKREG r4, 0xF851E418; +CHECKREG r5, 0x07AAE266; +CHECKREG r6, 0x007579C8; +CHECKREG r7, 0x06D88148; + +imm32 r0, 0xab235666; +imm32 r1, 0xeaba5166; +imm32 r2, 0x13d48766; +imm32 r3, 0xf00b0066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10ac5f6b; +imm32 r6, 0x800cb66d; +imm32 r7, 0x1246707f; +R1 = R6.L * R6.L, R0 = R6.L * R6.L; +R3 = R6.L * R7.L, R2 = R6.L * R7.H; +R5 = R7.L * R6.L, R4 = R7.H * R6.L; +R7 = R7.L * R7.L, R6 = R7.H * R7.H; +CHECKREG r0, 0x2A4A54D2; +CHECKREG r1, 0x2A4A54D2; +CHECKREG r2, 0xF57F179C; +CHECKREG r3, 0xBF566026; +CHECKREG r4, 0xF57F179C; +CHECKREG r5, 0xBF566026; +CHECKREG r6, 0x029BD648; +CHECKREG r7, 0x62DEBE02; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R1 = R3.L * R2.L (M), R0 = R3.L * R2.H; +R3 = R1.L * R0.H, R2 = R1.H * R0.L; +R5 = R7.H * R4.L, R4 = R7.H * R4.L; +R7 = R5.L * R6.L (M), R6 = R5.H * R6.L; +CHECKREG r0, 0x00010BF8; +CHECKREG r1, 0x0002D123; +CHECKREG r2, 0x00002FE0; +CHECKREG r3, 0xFFFFA246; +CHECKREG r4, 0xF8B964EC; +CHECKREG r5, 0xF8B964EC; +CHECKREG r6, 0xFFFF42CA; +CHECKREG r7, 0x00051FFC; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946905; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d9d; +imm32 r7, 0x12467009; +R3 = R6.L * R5.L, R2 = R6.L * R5.H; +R1 = R3.L * R0.H (M), R0 = R3.H * R0.L; +R5 = R1.L * R4.L (M), R4 = R1.H * R4.L; +R7 = R2.H * R7.L, R6 = R2.H * R7.L; +CHECKREG r0, 0xFE55DCD2; +CHECKREG r1, 0x0C7E7B9A; +CHECKREG r2, 0x01C5EAF8; +CHECKREG r3, 0xFDA5149E; +CHECKREG r4, 0xF6576CDC; +CHECKREG r5, 0x4BD1CA6A; +CHECKREG r6, 0x018C7FDA; +CHECKREG r7, 0x018C7FDA; + +imm32 r0, 0x8b235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0x00080007; +imm32 r4, 0x90ab8d09; +imm32 r5, 0x10ace8db; +imm32 r6, 0x000c008d; +imm32 r7, 0x12467008; +R3 = R6.H * R5.L, R2 = R6.L * R5.H; +R7 = R2.L * R0.H (M), R6 = R2.H * R0.L; +R5 = R1.L * R3.L (M), R4 = R1.H * R3.L; +R1 = R2.H * R7.L, R0 = R2.L * R7.H; +CHECKREG r0, 0x2517D740; +CHECKREG r1, 0xFFFDAAA0; +CHECKREG r2, 0x00125D78; +CHECKREG r3, 0xFFFDD488; +CHECKREG r4, 0x12C555A0; +CHECKREG r5, 0x435F68B8; +CHECKREG r6, 0x000C2874; +CHECKREG r7, 0x32CCEF68; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R1.H * R4.L, R0 = R1.H * R4.L; +R3 = R2.L * R5.L, R2 = R2.L * R5.H; +R5 = R3.H * R6.L, R4 = R3.L * R6.L; +R7 = R4.L * R0.H, R6 = R4.H * R0.L; +CHECKREG r0, 0x074CED14; +CHECKREG r1, 0x074CED14; +CHECKREG r2, 0x0D6B0EB8; +CHECKREG r3, 0xF2338E8E; +CHECKREG r4, 0xFF2DF2EC; +CHECKREG r5, 0xFFE6726E; +CHECKREG r6, 0x001F3108; +CHECKREG r7, 0xFF412420; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_pair_i.s b/sim/testsuite/bfin/c_dsp32mult_pair_i.s new file mode 100644 index 0000000..2d0d320 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_pair_i.s @@ -0,0 +1,179 @@ +//Original:/testcases/core/c_dsp32mult_pair_i/c_dsp32mult_pair_i.dsp +// Spec Reference: dsp32mult pair i +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x93ba5127; +imm32 r2, 0xa3446725; +imm32 r3, 0x00050027; +imm32 r4, 0xb0ab6d29; +imm32 r5, 0x10ace72b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467029; +R1 = R0.L * R0.L, R0 = R0.L * R0.L (IS); +R3 = R0.L * R1.L, R2 = R0.L * R1.H (IS); +R5 = R1.L * R0.L, R4 = R1.H * R0.L (IS); +R7 = R1.L * R1.L, R6 = R1.H * R1.H (IS); +CHECKREG r0, 0x1CFCE159; +CHECKREG r1, 0x1CFCE159; +CHECKREG r2, 0xFC878F9C; +CHECKREG r3, 0x03AB90F1; +CHECKREG r4, 0xFC878F9C; +CHECKREG r5, 0x03AB90F1; +CHECKREG r6, 0x03481810; +CHECKREG r7, 0x03AB90F1; + +imm32 r0, 0x5b33a635; +imm32 r1, 0x6fbe5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x9006d037; +imm32 r4, 0x80abcb39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c00dd; +imm32 r7, 0x12469003; +R1 = R2.L * R2.L, R0 = R2.L * R2.L (IS); +R3 = R2.L * R3.L, R2 = R2.L * R3.H (IS); +R5 = R3.L * R2.L, R4 = R3.H * R2.L (IS); +R7 = R3.L * R3.L, R6 = R3.H * R3.H (IS); +CHECKREG r0, 0x14B2D0F9; +CHECKREG r1, 0x14B2D0F9; +CHECKREG r2, 0x1FD71B3E; +CHECKREG r3, 0x0D966C63; +CHECKREG r4, 0x01721C54; +CHECKREG r5, 0x0B88B0FA; +CHECKREG r6, 0x00B893E4; +CHECKREG r7, 0x2DE3AE49; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R1 = R4.L * R4.L, R0 = R4.L * R4.L (IS); +R3 = R4.L * R5.L, R2 = R4.L * R5.H (IS); +R5 = R5.L * R4.L, R4 = R5.H * R4.L (IS); +R7 = R5.L * R5.L, R6 = R5.H * R5.H (IS); +CHECKREG r0, 0x0D94DA51; +CHECKREG r1, 0x0D94DA51; +CHECKREG r2, 0xFC28F20C; +CHECKREG r3, 0x03D57133; +CHECKREG r4, 0xFC28F20C; +CHECKREG r5, 0x03D57133; +CHECKREG r6, 0x000EAF39; +CHECKREG r7, 0x320E1029; + +imm32 r0, 0xab235666; +imm32 r1, 0xeaba5166; +imm32 r2, 0x13d48766; +imm32 r3, 0xf00b0066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10ac5f6b; +imm32 r6, 0x800cb66d; +imm32 r7, 0x1246707f; +R1 = R6.L * R6.L, R0 = R6.L * R6.L (IS); +R3 = R6.L * R7.L, R2 = R6.L * R7.H (IS); +R5 = R7.L * R6.L, R4 = R7.H * R6.L (IS); +R7 = R7.L * R7.L, R6 = R7.H * R7.H (IS); +CHECKREG r0, 0x15252A69; +CHECKREG r1, 0x15252A69; +CHECKREG r2, 0xFABF8BCE; +CHECKREG r3, 0xDFAB3013; +CHECKREG r4, 0xFABF8BCE; +CHECKREG r5, 0xDFAB3013; +CHECKREG r6, 0x014DEB24; +CHECKREG r7, 0x316F5F01; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (IS); +R3 = R1.L * R0.H, R2 = R1.H * R0.L (IS); +R5 = R7.H * R4.L, R4 = R7.H * R4.L (IS); +R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (IS); +CHECKREG r0, 0x000085FC; +CHECKREG r1, 0x0002D123; +CHECKREG r2, 0xFFFF0BF8; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xFC5CB276; +CHECKREG r5, 0xFC5CB276; +CHECKREG r6, 0xFFFFD0AC; +CHECKREG r7, 0xFFFC0FFE; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946905; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d9d; +imm32 r7, 0x12467009; +R3 = R6.L * R5.L, R2 = R6.L * R5.H (IS); +R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (IS); +R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (IS); +R7 = R2.H * R7.L, R6 = R2.H * R7.L (IS); +CHECKREG r0, 0xFF9549FA; +CHECKREG r1, 0xB8ADBDCD; +CHECKREG r2, 0x00E2F57C; +CHECKREG r3, 0xFED28A4F; +CHECKREG r4, 0x1B929715; +CHECKREG r5, 0xD7646535; +CHECKREG r6, 0x0062E7F2; +CHECKREG r7, 0x0062E7F2; + +imm32 r0, 0x8b235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0x00080007; +imm32 r4, 0x90ab8d09; +imm32 r5, 0x10ace8db; +imm32 r6, 0x000c008d; +imm32 r7, 0x12467008; +R3 = R6.H * R5.L, R2 = R6.L * R5.H (IS); +R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (IS); +R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (IS); +R1 = R2.H * R7.L, R0 = R2.L * R7.H (IS); +CHECKREG r0, 0x04A2FAE8; +CHECKREG r1, 0x00043554; +CHECKREG r2, 0x00092EBC; +CHECKREG r3, 0xFFFEEA44; +CHECKREG r4, 0x04B15568; +CHECKREG r5, 0x4A43345C; +CHECKREG r6, 0x00030A1D; +CHECKREG r7, 0x196677B4; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R1.H * R4.L, R0 = R1.H * R4.L (IS); +R3 = R2.L * R5.L, R2 = R2.L * R5.H (IS); +R5 = R3.H * R6.L, R4 = R3.L * R6.L (IS); +R7 = R4.L * R0.H, R6 = R4.H * R0.L (IS); +CHECKREG r0, 0x03A6768A; +CHECKREG r1, 0x03A6768A; +CHECKREG r2, 0x06B5875C; +CHECKREG r3, 0xF919C747; +CHECKREG r4, 0xFFCB7CBB; +CHECKREG r5, 0xFFF99C25; +CHECKREG r6, 0xFFE7756E; +CHECKREG r7, 0x01C71242; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_pair_is.s b/sim/testsuite/bfin/c_dsp32mult_pair_is.s new file mode 100644 index 0000000..d4a7d88 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_pair_is.s @@ -0,0 +1,179 @@ +//Original:/testcases/core/c_dsp32mult_pair_is/c_dsp32mult_pair_is.dsp +// Spec Reference: dsp32mult pair is +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x93ba5127; +imm32 r2, 0xa3446725; +imm32 r3, 0x00050027; +imm32 r4, 0xb0ab6d29; +imm32 r5, 0x10ace72b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467029; +R1 = R0.L * R0.L, R0 = R0.L * R0.L (ISS2); +R3 = R0.L * R1.L, R2 = R0.L * R1.H (ISS2); +R5 = R1.L * R0.L, R4 = R1.H * R0.L (ISS2); +R7 = R1.L * R1.L, R6 = R1.H * R1.H (ISS2); +CHECKREG r0, 0x39F9C2B2; +CHECKREG r1, 0x39F9C2B2; +CHECKREG r2, 0xE43C0244; +CHECKREG r3, 0x1D5C8788; +CHECKREG r4, 0xE43C0244; +CHECKREG r5, 0x1D5C8788; +CHECKREG r6, 0x1A41A862; +CHECKREG r7, 0x1D5C8788; + +imm32 r0, 0x5b33a635; +imm32 r1, 0x6fbe5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x9006d037; +imm32 r4, 0x80abcb39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c00dd; +imm32 r7, 0x12469003; +R1 = R2.L * R2.L, R0 = R2.L * R2.L (ISS2); +R3 = R2.L * R3.L, R2 = R2.L * R3.H (ISS2); +R5 = R3.L * R2.L, R4 = R3.H * R2.L (ISS2); +R7 = R3.L * R3.L, R6 = R3.H * R3.H (ISS2); +CHECKREG r0, 0x2965A1F2; +CHECKREG r1, 0x2965A1F2; +CHECKREG r2, 0x3FAE367C; +CHECKREG r3, 0x1B2CD8C6; +CHECKREG r4, 0x0B90E2A0; +CHECKREG r5, 0xEF4D87D0; +CHECKREG r6, 0x05C49F20; +CHECKREG r7, 0x0C057248; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R1 = R4.L * R4.L, R0 = R4.L * R4.L (ISS2); +R3 = R4.L * R5.L, R2 = R4.L * R5.H (ISS2); +R5 = R5.L * R4.L, R4 = R5.H * R4.L (ISS2); +R7 = R5.L * R5.L, R6 = R5.H * R5.H (ISS2); +CHECKREG r0, 0x1B29B4A2; +CHECKREG r1, 0x1B29B4A2; +CHECKREG r2, 0xF851E418; +CHECKREG r3, 0x07AAE266; +CHECKREG r4, 0xF851E418; +CHECKREG r5, 0x07AAE266; +CHECKREG r6, 0x007579C8; +CHECKREG r7, 0x06D88148; + +imm32 r0, 0xab235666; +imm32 r1, 0xeaba5166; +imm32 r2, 0x13d48766; +imm32 r3, 0xf00b0066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10ac5f6b; +imm32 r6, 0x800cb66d; +imm32 r7, 0x1246707f; +R1 = R6.L * R6.L, R0 = R6.L * R6.L (ISS2); +R3 = R6.L * R7.L, R2 = R6.L * R7.H (ISS2); +R5 = R7.L * R6.L, R4 = R7.H * R6.L (ISS2); +R7 = R7.L * R7.L, R6 = R7.H * R7.H (ISS2); +CHECKREG r0, 0x2A4A54D2; +CHECKREG r1, 0x2A4A54D2; +CHECKREG r2, 0xF57F179C; +CHECKREG r3, 0xBF566026; +CHECKREG r4, 0xF57F179C; +CHECKREG r5, 0xBF566026; +CHECKREG r6, 0x029BD648; +CHECKREG r7, 0x62DEBE02; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (ISS2); +R3 = R1.L * R0.H, R2 = R1.H * R0.L (ISS2); +R5 = R7.H * R4.L, R4 = R7.H * R4.L (ISS2); +R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (ISS2); +CHECKREG r0, 0x00010BF8; +CHECKREG r1, 0x0005A246; +CHECKREG r2, 0x000077B0; +CHECKREG r3, 0xFFFF448C; +CHECKREG r4, 0xF8B964EC; +CHECKREG r5, 0xF8B964EC; +CHECKREG r6, 0xFFFF42CA; +CHECKREG r7, 0x000A3FF8; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946905; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d9d; +imm32 r7, 0x12467009; +R3 = R6.L * R5.L, R2 = R6.L * R5.H (ISS2); +R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (ISS2); +R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (ISS2); +R7 = R2.H * R7.L, R6 = R2.H * R7.L (ISS2); +CHECKREG r0, 0xFE55DCD2; +CHECKREG r1, 0x18FCF734; +CHECKREG r2, 0x01C5EAF8; +CHECKREG r3, 0xFDA5149E; +CHECKREG r4, 0xECAED9B8; +CHECKREG r5, 0xF53529A8; +CHECKREG r6, 0x018C7FDA; +CHECKREG r7, 0x018C7FDA; + +imm32 r0, 0x8b235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0x00080007; +imm32 r4, 0x90ab8d09; +imm32 r5, 0x10ace8db; +imm32 r6, 0x000c008d; +imm32 r7, 0x12467008; +R3 = R6.H * R5.L, R2 = R6.L * R5.H (ISS2); +R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (ISS2); +R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (ISS2); +R1 = R2.H * R7.L, R0 = R2.L * R7.H (ISS2); +CHECKREG r0, 0x4A306970; +CHECKREG r1, 0xFFFB5540; +CHECKREG r2, 0x00125D78; +CHECKREG r3, 0xFFFDD488; +CHECKREG r4, 0x12C555A0; +CHECKREG r5, 0x7FFFFFFF; +CHECKREG r6, 0x000C2874; +CHECKREG r7, 0x6599DED0; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R1.H * R4.L, R0 = R1.H * R4.L (ISS2); +R3 = R2.L * R5.L, R2 = R2.L * R5.H (ISS2); +R5 = R3.H * R6.L, R4 = R3.L * R6.L (ISS2); +R7 = R4.L * R0.H, R6 = R4.H * R0.L (ISS2); +CHECKREG r0, 0x074CED14; +CHECKREG r1, 0x074CED14; +CHECKREG r2, 0x0D6B0EB8; +CHECKREG r3, 0xF2338E8E; +CHECKREG r4, 0xFF2DF2EC; +CHECKREG r5, 0xFFE6726E; +CHECKREG r6, 0x001F3108; +CHECKREG r7, 0xFF412420; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_pair_m.s b/sim/testsuite/bfin/c_dsp32mult_pair_m.s new file mode 100644 index 0000000..73ab875 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_pair_m.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m/c_dsp32mult_pair_m.dsp +// Spec Reference: dsp32mult pair MUNOP +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L; +R2 = R0.L * R1.H; +R4 = R1.H * R1.H; +R6 = R0.L * R0.L; +CHECKREG r0, 0x39F9C2B2; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x2E3AADA8; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x48C98C48; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0x1D5C8788; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L; +R2 = R2.L * R3.H; +R4 = R3.H * R2.H; +R6 = R2.L * R3.L; +CHECKREG r0, 0x2965A1F2; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x3FAE367C; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0xC84ABC28; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x00176948; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L; +R2 = R4.L * R5.H; +R4 = R5.H * R5.H; +R6 = R4.L * R5.L; +CHECKREG r0, 0x1B29B4A2; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0xF85431BE; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x022A99E2; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0x0D4762AC; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L; +R2 = R6.L * R7.H; +R4 = R7.H * R7.H; +R6 = R6.L * R7.L; +CHECKREG r0, 0x31781CD2; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0xF4A3CF9C; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x029BD648; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0xBA1A5E86; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L; +R2 = R1.L * R6.H; +R4 = R3.H * R4.H; +R6 = R4.L * R3.L; +CHECKREG r0, 0x0B26E1B6; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x00079BA8; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0xFFFAC804; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0xFFFCF038; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H; +R3 = R6.H * R1.H; +R5 = R5.H * R2.L; +R7 = R4.L * R3.H; +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0xF3E28324; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0xFFFEDD30; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x0DADBEB8; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x0000CBDC; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L; +R3 = R5.L * R3.H; +R5 = R3.H * R1.L; +R7 = R1.H * R2.H; +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0xFFF6B8D8; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0xFFFE7166; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0x00011CA0; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0xFFFE7870; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H; +R3 = R6.H * R1.H; +R5 = R1.L * R2.L; +R7 = R4.H * R2.L; +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0x03175676; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x00004A28; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0x4596549C; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0xA66540AE; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_pair_m_i.s b/sim/testsuite/bfin/c_dsp32mult_pair_m_i.s new file mode 100644 index 0000000..b865be0 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_pair_m_i.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m_i/c_dsp32mult_pair_m_i.dsp +// Spec Reference: dsp32mult pair MUNOP i +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L (IS); +R2 = R0.L * R1.H (IS); +R4 = R1.H * R1.H (IS); +R6 = R0.L * R0.L (IS); +CHECKREG r0, 0x1CFCE159; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x0B8EAB6A; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x2464C624; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0x03AB90F1; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L (IS); +R2 = R2.L * R3.H (IS); +R4 = R3.H * R2.H (IS); +R6 = R2.L * R3.L (IS); +CHECKREG r0, 0x14B2D0F9; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x1FD71B3E; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0xF212AF0A; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x0005DA52; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L (IS); +R2 = R4.L * R5.H (IS); +R4 = R5.H * R5.H (IS); +R6 = R4.L * R5.L (IS); +CHECKREG r0, 0x0D94DA51; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0xFC2A18DF; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x01154CF1; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0xFAFF58AB; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L (IS); +R2 = R6.L * R7.H (IS); +R4 = R7.H * R7.H (IS); +R6 = R6.L * R7.L (IS); +CHECKREG r0, 0x18BC0E69; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0xFA51E7CE; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x014DEB24; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0xDD0D2F43; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L (IS); +R2 = R1.L * R6.H (IS); +R4 = R3.H * R4.H (IS); +R6 = R4.L * R3.L (IS); +CHECKREG r0, 0x059370DB; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x0003CDD4; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0xFFFD6402; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0x0002BC0E; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H (IS); +R3 = R6.H * R1.H (IS); +R5 = R5.H * R2.L (IS); +R7 = R4.L * R3.H (IS); +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0xF9F14192; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0xFFFFB74C; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x06D6DF5C; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x000032F7; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L (IS); +R3 = R5.L * R3.H (IS); +R5 = R3.H * R1.L (IS); +R7 = R1.H * R2.H (IS); +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0xFFFB5C6C; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0xFFFF38B3; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0xFFFFA394; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0xFFFF9E1C; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H (IS); +R3 = R6.H * R1.H (IS); +R5 = R1.L * R2.L (IS); +R7 = R4.H * R2.L (IS); +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0x018BAB3B; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x00001284; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0xDDE31527; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0xD332A057; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_pair_m_is.s b/sim/testsuite/bfin/c_dsp32mult_pair_m_is.s new file mode 100644 index 0000000..073b7f3 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_pair_m_is.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m_is/c_dsp32mult_pair_m_is.dsp +// Spec Reference: dsp32mult pair MUNOP is +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L (ISS2); +R2 = R0.L * R1.H (ISS2); +R4 = R1.H * R1.H (ISS2); +R6 = R0.L * R0.L (ISS2); +CHECKREG r0, 0x39F9C2B2; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x2E3AADA8; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x48C98C48; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0x1D5C8788; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L (ISS2); +R2 = R2.L * R3.H (ISS2); +R4 = R3.H * R2.H (ISS2); +R6 = R2.L * R3.L (ISS2); +CHECKREG r0, 0x2965A1F2; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x3FAE367C; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0xC84ABC28; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x00176948; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L (ISS2); +R2 = R4.L * R5.H (ISS2); +R4 = R5.H * R5.H (ISS2); +R6 = R4.L * R5.L (ISS2); +CHECKREG r0, 0x1B29B4A2; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0xF85431BE; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x022A99E2; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0x0D4762AC; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L (ISS2); +R2 = R6.L * R7.H (ISS2); +R4 = R7.H * R7.H (ISS2); +R6 = R6.L * R7.L (ISS2); +CHECKREG r0, 0x31781CD2; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0xF4A3CF9C; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x029BD648; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0xBA1A5E86; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L (ISS2); +R2 = R1.L * R6.H (ISS2); +R4 = R3.H * R4.H (ISS2); +R6 = R4.L * R3.L (ISS2); +CHECKREG r0, 0x0B26E1B6; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x00079BA8; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0xFFFAC804; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0xFFFCF038; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H (ISS2); +R3 = R6.H * R1.H (ISS2); +R5 = R5.H * R2.L (ISS2); +R7 = R4.L * R3.H (ISS2); +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0xF3E28324; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0xFFFEDD30; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x0DADBEB8; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x0000CBDC; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L (ISS2); +R3 = R5.L * R3.H (ISS2); +R5 = R3.H * R1.L (ISS2); +R7 = R1.H * R2.H (ISS2); +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0xFFF6B8D8; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0xFFFE7166; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0x00011CA0; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0xFFFE7870; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H (ISS2); +R3 = R6.H * R1.H (ISS2); +R5 = R1.L * R2.L (ISS2); +R7 = R4.H * R2.L (ISS2); +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0x03175676; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x00004A28; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0x4596549C; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0xA66540AE; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_pair_m_s.s b/sim/testsuite/bfin/c_dsp32mult_pair_m_s.s new file mode 100644 index 0000000..71b95eb --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_pair_m_s.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m_s/c_dsp32mult_pair_m_s.dsp +// Spec Reference: dsp32mult pair MUNOP s +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L (S2RND); +R2 = R0.L * R1.H (S2RND); +R4 = R1.H * R1.H (S2RND); +R6 = R0.L * R0.L (S2RND); +CHECKREG r0, 0x73F38564; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x7FFFFFFF; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x7FFFFFFF; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0x7FFFFFFF; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L (S2RND); +R2 = R2.L * R3.H (S2RND); +R4 = R3.H * R2.H (S2RND); +R6 = R2.L * R3.L (S2RND); +CHECKREG r0, 0x52CB43E4; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x7F5C6CF8; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x005DA520; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L (S2RND); +R2 = R4.L * R5.H (S2RND); +R4 = R5.H * R5.H (S2RND); +R6 = R4.L * R5.L (S2RND); +CHECKREG r0, 0x36536944; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0xF0A8637C; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x045533C4; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0xF2898AB0; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L (S2RND); +R2 = R6.L * R7.H (S2RND); +R4 = R7.H * R7.H (S2RND); +R6 = R6.L * R7.L (S2RND); +CHECKREG r0, 0x62F039A4; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0xE9479F38; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x0537AC90; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L (S2RND); +R2 = R1.L * R6.H (S2RND); +R4 = R3.H * R4.H (S2RND); +R6 = R4.L * R3.L (S2RND); +CHECKREG r0, 0x164DC36C; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x000F3750; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0xFFF59008; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0xFFF3C0E0; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H (S2RND); +R3 = R6.H * R1.H (S2RND); +R5 = R5.H * R2.L (S2RND); +R7 = R4.L * R3.H (S2RND); +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0xE7C50648; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0xFFFB74F0; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x1B5B7D70; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x0003FB4C; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L (S2RND); +R3 = R5.L * R3.H (S2RND); +R5 = R3.H * R1.L (S2RND); +R7 = R1.H * R2.H (S2RND); +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0xFFED71B0; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0xFFFCE2CC; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0xFFF8E500; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0xFFFA3010; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H (S2RND); +R3 = R6.H * R1.H (S2RND); +R5 = R1.L * R2.L (S2RND); +R7 = R4.H * R2.L (S2RND); +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0x062EACEC; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x000128A0; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0x80000000; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_pair_m_u.s b/sim/testsuite/bfin/c_dsp32mult_pair_m_u.s new file mode 100644 index 0000000..d7f6633 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_pair_m_u.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m_u/c_dsp32mult_pair_m_u.dsp +// Spec Reference: dsp32mult pair MUNOP u +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L (FU); +R2 = R0.L * R1.H (FU); +R4 = R1.H * R1.H (FU); +R6 = R0.L * R0.L (FU); +CHECKREG r0, 0x1CFCE159; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x8C61AB6A; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x6358C624; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0xC65D90F1; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L (FU); +R2 = R2.L * R3.H (FU); +R4 = R3.H * R2.H (FU); +R6 = R2.L * R3.L (FU); +CHECKREG r0, 0x831CD0F9; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x67121B3E; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0x39FC8A6C; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x0005DA52; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L (FU); +R2 = R4.L * R5.H (FU); +R4 = R5.H * R5.H (FU); +R6 = R4.L * R5.L (FU); +CHECKREG r0, 0x97A6DA51; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0x0CD118DF; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x01154CF1; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0x47F058AB; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L (FU); +R2 = R6.L * R7.H (FU); +R4 = R7.H * R7.H (FU); +R6 = R6.L * R7.L (FU); +CHECKREG r0, 0x79960E69; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0x0C97E7CE; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x014DEB24; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0x4D7C2F43; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L (FU); +R2 = R1.L * R6.H (FU); +R4 = R3.H * R4.H (FU); +R6 = R4.L * R3.L (FU); +CHECKREG r0, 0x9C1770DB; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x0003CDD4; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00036402; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0x0002BC0E; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H (FU); +R3 = R6.H * R1.H (FU); +R5 = R5.H * R2.L (FU); +R7 = R4.L * R3.H (FU); +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0x0C374192; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0x00009294; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x06D6DF5C; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L (FU); +R3 = R5.L * R3.H (FU); +R5 = R3.H * R1.L (FU); +R7 = R1.H * R2.H (FU); +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0x00075C6C; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0x000838B3; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0x0002E360; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0x0000890C; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H (FU); +R3 = R6.H * R1.H (FU); +R5 = R1.L * R2.L (FU); +R7 = R4.H * R2.L (FU); +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0xD9B7AB3B; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x000A3494; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0x44E81527; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0x3A37A057; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_pair_s.s b/sim/testsuite/bfin/c_dsp32mult_pair_s.s new file mode 100644 index 0000000..dae1552 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_pair_s.s @@ -0,0 +1,180 @@ +//Original:/testcases/core/c_dsp32mult_pair_s/c_dsp32mult_pair_s.dsp +// Spec Reference: dsp32mult pair s +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x93ba5127; +imm32 r2, 0xa3446725; +imm32 r3, 0x00050027; +imm32 r4, 0xb0ab6d29; +imm32 r5, 0x10ace72b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467029; +R1 = R0.L * R0.L, R0 = R0.L * R0.L (S2RND); +R3 = R0.L * R1.L, R2 = R0.L * R1.H (S2RND); +R5 = R1.L * R0.L, R4 = R1.H * R0.L (S2RND); +R7 = R1.L * R1.L, R6 = R1.H * R1.H (S2RND); +CHECKREG r0, 0x73F38564; +CHECKREG r1, 0x73F38564; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x7FFFFFFF; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x7FFFFFFF; +CHECKREG r6, 0x7FFFFFFF; +CHECKREG r7, 0x7FFFFFFF; + +imm32 r0, 0x5b33a635; +imm32 r1, 0x6fbe5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x9006d037; +imm32 r4, 0x80abcb39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c00dd; +imm32 r7, 0x12469003; +R1 = R2.L * R2.L, R0 = R2.L * R2.L (S2RND); +R3 = R2.L * R3.L, R2 = R2.L * R3.H (S2RND); +R5 = R3.L * R2.L, R4 = R3.H * R2.L (S2RND); +R7 = R3.L * R3.L, R6 = R3.H * R3.H (S2RND); +CHECKREG r0, 0x52CB43E4; +CHECKREG r1, 0x52CB43E4; +CHECKREG r2, 0x7F5C6CF8; +CHECKREG r3, 0x3659B18C; +CHECKREG r4, 0x5C88C8E0; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x2E26ABC4; +CHECKREG r7, 0x602B9240; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R1 = R4.L * R4.L, R0 = R4.L * R4.L (S2RND); +R3 = R4.L * R5.L, R2 = R4.L * R5.H (S2RND); +R5 = R5.L * R4.L, R4 = R5.H * R4.L (S2RND); +R7 = R5.L * R5.L, R6 = R5.H * R5.H (S2RND); +CHECKREG r0, 0x36536944; +CHECKREG r1, 0x36536944; +CHECKREG r2, 0xF0A3C830; +CHECKREG r3, 0x0F55C4CC; +CHECKREG r4, 0xF0A3C830; +CHECKREG r5, 0x0F55C4CC; +CHECKREG r6, 0x03AC48E4; +CHECKREG r7, 0x36C40A40; + +imm32 r0, 0xab235666; +imm32 r1, 0xeaba5166; +imm32 r2, 0x13d48766; +imm32 r3, 0xf00b0066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10ac5f6b; +imm32 r6, 0x800cb66d; +imm32 r7, 0x1246707f; +R1 = R6.L * R6.L, R0 = R6.L * R6.L (S2RND); +R3 = R6.L * R7.L, R2 = R6.L * R7.H (S2RND); +R5 = R7.L * R6.L, R4 = R7.H * R6.L (S2RND); +R7 = R7.L * R7.L, R6 = R7.H * R7.H (S2RND); +CHECKREG r0, 0x5494A9A4; +CHECKREG r1, 0x5494A9A4; +CHECKREG r2, 0xEAFE2F38; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0xEAFE2F38; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x0537AC90; +CHECKREG r7, 0x7FFFFFFF; + + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (S2RND); +R3 = R1.L * R0.H, R2 = R1.H * R0.L (S2RND); +R5 = R7.H * R4.L, R4 = R7.H * R4.L (S2RND); +R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (S2RND); +CHECKREG r0, 0x000217F0; +CHECKREG r1, 0x0005A246; +CHECKREG r2, 0x0001DEC0; +CHECKREG r3, 0xFFFD1230; +CHECKREG r4, 0xF172C9D8; +CHECKREG r5, 0xF172C9D8; +CHECKREG r6, 0xFFFD0B28; +CHECKREG r7, 0xFFFA7FF0; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946905; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d9d; +imm32 r7, 0x12467009; +R3 = R6.L * R5.L, R2 = R6.L * R5.H (S2RND); +R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (S2RND); +R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (S2RND); +R7 = R2.H * R7.L, R6 = R2.H * R7.L (S2RND); +CHECKREG r0, 0xF9577348; +CHECKREG r1, 0x31F9EE68; +CHECKREG r2, 0x038BD5F0; +CHECKREG r3, 0xFB4A293C; +CHECKREG r4, 0xB2B9DB04; +CHECKREG r5, 0xEA6A5350; +CHECKREG r6, 0x0633BF8C; +CHECKREG r7, 0x0633BF8C; + +imm32 r0, 0x8b235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0x00080007; +imm32 r4, 0x90ab8d09; +imm32 r5, 0x10ace8db; +imm32 r6, 0x000c008d; +imm32 r7, 0x12467008; +R3 = R6.H * R5.L, R2 = R6.L * R5.H (S2RND); +R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (S2RND); +R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (S2RND); +R1 = R2.H * R7.L, R0 = R2.L * R7.H (S2RND); +CHECKREG r0, 0x510340C0; +CHECKREG r1, 0xFFDAAA00; +CHECKREG r2, 0x0024BAF0; +CHECKREG r3, 0xFFFBA910; +CHECKREG r4, 0x4B155680; +CHECKREG r5, 0x6B2FA2E0; +CHECKREG r6, 0x0030A1D0; +CHECKREG r7, 0xB4EDBDA0; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R1.H * R4.L, R0 = R1.H * R4.L (S2RND); +R3 = R2.L * R5.L, R2 = R2.L * R5.H (S2RND); +R5 = R3.H * R6.L, R4 = R3.L * R6.L (S2RND); +R7 = R4.L * R0.H, R6 = R4.H * R0.L (S2RND); +CHECKREG r0, 0x0E99DA28; +CHECKREG r1, 0x0E99DA28; +CHECKREG r2, 0x1AD61D70; +CHECKREG r3, 0xE4671D1C; +CHECKREG r4, 0x006BCBB0; +CHECKREG r5, 0xFF99CD6C; +CHECKREG r6, 0xFFC0BAE0; +CHECKREG r7, 0xF41170C0; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32mult_pair_u.s b/sim/testsuite/bfin/c_dsp32mult_pair_u.s new file mode 100644 index 0000000..0c570b2 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32mult_pair_u.s @@ -0,0 +1,179 @@ +//Original:/testcases/core/c_dsp32mult_pair_u/c_dsp32mult_pair_u.dsp +// Spec Reference: dsp32mult pair u +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x93ba5127; +imm32 r2, 0xa3446725; +imm32 r3, 0x00050027; +imm32 r4, 0xb0ab6d29; +imm32 r5, 0x10ace72b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467029; +R1 = R0.L * R0.L, R0 = R0.L * R0.L (FU); +R3 = R0.L * R1.L, R2 = R0.L * R1.H (FU); +R5 = R1.L * R0.L, R4 = R1.H * R0.L (FU); +R7 = R1.L * R1.L, R6 = R1.H * R1.H (FU); +CHECKREG r0, 0x1CFCE159; +CHECKREG r1, 0x1CFCE159; +CHECKREG r2, 0x19838F9C; +CHECKREG r3, 0xC65D90F1; +CHECKREG r4, 0x19838F9C; +CHECKREG r5, 0xC65D90F1; +CHECKREG r6, 0x03481810; +CHECKREG r7, 0xC65D90F1; + +imm32 r0, 0x5b33a635; +imm32 r1, 0x6fbe5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x9006d037; +imm32 r4, 0x80abcb39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c00dd; +imm32 r7, 0x12469003; +R1 = R2.L * R2.L, R0 = R2.L * R2.L (FU); +R3 = R2.L * R3.L, R2 = R2.L * R3.H (FU); +R5 = R3.L * R2.L, R4 = R3.H * R2.L (FU); +R7 = R3.L * R3.L, R6 = R3.H * R3.H (FU); +CHECKREG r0, 0x831CD0F9; +CHECKREG r1, 0x831CD0F9; +CHECKREG r2, 0x67121B3E; +CHECKREG r3, 0x95026C63; +CHECKREG r4, 0x0FDB4C7C; +CHECKREG r5, 0x0B88B0FA; +CHECKREG r6, 0x56BB5404; +CHECKREG r7, 0x2DE3AE49; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R1 = R4.L * R4.L, R0 = R4.L * R4.L (FU); +R3 = R4.L * R5.L, R2 = R4.L * R5.H (FU); +R5 = R5.L * R4.L, R4 = R5.H * R4.L (FU); +R7 = R5.L * R5.L, R6 = R5.H * R5.H (FU); +CHECKREG r0, 0x97A6DA51; +CHECKREG r1, 0x97A6DA51; +CHECKREG r2, 0x0CD4F20C; +CHECKREG r3, 0xB8397133; +CHECKREG r4, 0x0CD4F20C; +CHECKREG r5, 0xB8397133; +CHECKREG r6, 0x8491FCB1; +CHECKREG r7, 0x320E1029; + +imm32 r0, 0xab235666; +imm32 r1, 0xeaba5166; +imm32 r2, 0x13d48766; +imm32 r3, 0xf00b0066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10ac5f6b; +imm32 r6, 0x800cb66d; +imm32 r7, 0x1246707f; +R1 = R6.L * R6.L, R0 = R6.L * R6.L (FU); +R3 = R6.L * R7.L, R2 = R6.L * R7.H (FU); +R5 = R7.L * R6.L, R4 = R7.H * R6.L (FU); +R7 = R7.L * R7.L, R6 = R7.H * R7.H (FU); +CHECKREG r0, 0x81FF2A69; +CHECKREG r1, 0x81FF2A69; +CHECKREG r2, 0x0D058BCE; +CHECKREG r3, 0x502A3013; +CHECKREG r4, 0x0D058BCE; +CHECKREG r5, 0x502A3013; +CHECKREG r6, 0x014DEB24; +CHECKREG r7, 0x316F5F01; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (FU); +R3 = R1.L * R0.H, R2 = R1.H * R0.L (FU); +R5 = R7.H * R4.L, R4 = R7.H * R4.L (FU); +R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (FU); +CHECKREG r0, 0x000085FC; +CHECKREG r1, 0x0002D123; +CHECKREG r2, 0x00010BF8; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0EA2B276; +CHECKREG r5, 0x0EA2B276; +CHECKREG r6, 0x0000BE3A; +CHECKREG r7, 0xFFFC0FFE; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946905; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d9d; +imm32 r7, 0x12467009; +R3 = R6.L * R5.L, R2 = R6.L * R5.H (FU); +R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (FU); +R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (FU); +R7 = R2.H * R7.L, R6 = R2.H * R7.L (FU); +CHECKREG r0, 0x0464B4BB; +CHECKREG r1, 0xB8ADBDCD; +CHECKREG r2, 0x00E2F57C; +CHECKREG r3, 0x0C6F8A4F; +CHECKREG r4, 0x71489715; +CHECKREG r5, 0xD7646535; +CHECKREG r6, 0x0062E7F2; +CHECKREG r7, 0x0062E7F2; + +imm32 r0, 0x8b235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0x00080007; +imm32 r4, 0x90ab8d09; +imm32 r5, 0x10ace8db; +imm32 r6, 0x000c008d; +imm32 r7, 0x12467008; +R3 = R6.H * R5.L, R2 = R6.L * R5.H (FU); +R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (FU); +R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (FU); +R1 = R2.H * R7.L, R0 = R2.L * R7.H (FU); +CHECKREG r0, 0x04A2FAE8; +CHECKREG r1, 0x00043554; +CHECKREG r2, 0x00092EBC; +CHECKREG r3, 0x000AEA44; +CHECKREG r4, 0xB7AF5568; +CHECKREG r5, 0x4A43345C; +CHECKREG r6, 0x00030A1D; +CHECKREG r7, 0x196677B4; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R1.H * R4.L, R0 = R1.H * R4.L (FU); +R3 = R2.L * R5.L, R2 = R2.L * R5.H (FU); +R5 = R3.H * R6.L, R4 = R3.L * R6.L (FU); +R7 = R4.L * R0.H, R6 = R4.H * R0.L (FU); +CHECKREG r0, 0xBF69768A; +CHECKREG r1, 0xBF69768A; +CHECKREG r2, 0x06B5875C; +CHECKREG r3, 0x601EC747; +CHECKREG r4, 0x00B87CBB; +CHECKREG r5, 0x0058FBC6; +CHECKREG r6, 0x00553330; +CHECKREG r7, 0x5D42ADB3; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_a0alr.s b/sim/testsuite/bfin/c_dsp32shift_a0alr.s new file mode 100644 index 0000000..4b625aa --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_a0alr.s @@ -0,0 +1,211 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_a0alr/c_dsp32shift_a0alr.dsp +// Spec Reference: dsp32shift a0 ashift, lshift, rot +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x11140000; + imm32 r1, 0x012C003E; + imm32 r2, 0x81359E24; + imm32 r3, 0x81459E24; + imm32 r4, 0xD159E268; + imm32 r5, 0x51626AF2; + imm32 r6, 0x9176AF36; + imm32 r7, 0xE18BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = ASHIFT A0 BY R0.L; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x012C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0x0258007C; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = ASHIFT A0 BY R2.L; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x003E0000; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = ASHIFT A0 BY R3.L; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x00000000; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = ASHIFT A0 BY R4.L; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x00000000; + + R5.L = -16; + A0 = 0; + A0.L = R6.L; + A0.H = R6.H; + A0 = ASHIFT A0 BY R5.L; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x00000000; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = ASHIFT A0 BY R6.L; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x00000000; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + A0 = ASHIFT A0 BY R7.L; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x00000000; + + imm32 r0, 0x12340000; + imm32 r1, 0x028C003E; + imm32 r2, 0x82159E24; + imm32 r3, 0x82159E24; + imm32 r4, 0xD259E268; + imm32 r5, 0x52E26AF2; + imm32 r6, 0x9226AF36; + imm32 r7, 0xE26BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = LSHIFT A0 BY R0.L; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x028C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0x0518007C; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = LSHIFT A0 BY R2.L; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x003E0000; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = LSHIFT A0 BY R3.L; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x00000000; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = LSHIFT A0 BY R4.L; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x00000000; + + R5.L = -16; + A0 = 0; + A0.L = R6.L; + A0.H = R6.H; + A0 = LSHIFT A0 BY R5.L; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x00000000; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = LSHIFT A0 BY R6.L; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x00000000; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + A0 = LSHIFT A0 BY R7.L; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x00000000; + + imm32 r0, 0x13340000; + imm32 r1, 0x038C003E; + imm32 r2, 0x83159E24; + imm32 r3, 0x83159E24; + imm32 r4, 0xD359E268; + imm32 r5, 0x53E26AF2; + imm32 r6, 0x9326AF36; + imm32 r7, 0xE36BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = ROT A0 BY R0.L; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x038C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = ROT A0 BY R1.L; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0x0718007C; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = ROT A0 BY R2.L; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x003E0001; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = ROT A0 BY R3.L; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0xE3000F80; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = ROT A0 BY R4.L; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x718007C0; + + R5.L = -16; + A0.L = R6.L; + A0.H = R6.H; + A0 = ROT A0 BY R5.L; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x80007180; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = ROT A0 BY R6.L; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x01C6001F; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + A0 = ROT A0 BY R7.L; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x8C003E00; + + pass diff --git a/sim/testsuite/bfin/c_dsp32shift_af.s b/sim/testsuite/bfin/c_dsp32shift_af.s new file mode 100644 index 0000000..c93587b --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_af.s @@ -0,0 +1,186 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_af/c_dsp32shift_af.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + +// ashift : mix data, count (+)= (half reg) +// d_reg = ashift (d BY d_lo) +// Rx by RLx + imm32 r0, 0x01230001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x856789ab; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R4 = ASHIFT R0 BY R0.L; + R5 = ASHIFT R1 BY R0.L; + R6 = ASHIFT R2 BY R0.L; + R7 = ASHIFT R3 BY R0.L; + CHECKREG r4, 0x02460002; + CHECKREG r5, 0x2468ACF0; + CHECKREG r6, 0x468ACF12; + CHECKREG r7, 0x68ACF134; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0xa6789abc; + imm32 r6, 0xb789abcd; + imm32 r7, 0xc89abcde; + R1.L = 5; + R5 = ASHIFT R0 BY R1.L; + R6 = ASHIFT R1 BY R1.L; + R7 = ASHIFT R2 BY R1.L; + R4 = ASHIFT R3 BY R1.L; + CHECKREG r4, 0x8ACF1340; + CHECKREG r5, 0x24600040; + CHECKREG r6, 0x468000A0; + CHECKREG r7, 0x68ACF120; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2 = 15; + R6 = ASHIFT R0 BY R2.L; + R7 = ASHIFT R1 BY R2.L; + R4 = ASHIFT R2 BY R2.L; + R5 = ASHIFT R3 BY R2.L; + CHECKREG r4, 0x00078000; + CHECKREG r5, 0x3C4D0000; + CHECKREG r6, 0x80010000; + CHECKREG r7, 0x2B3C0000; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0xa56789ab; + imm32 r5, 0xb6789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0xd89abcde; + R3.L = 16; + R7 = ASHIFT R0 BY R3.L; + R6 = ASHIFT R1 BY R3.L; + R5 = ASHIFT R2 BY R3.L; + R4 = ASHIFT R3 BY R3.L; + CHECKREG r4, 0x00100000; + CHECKREG r5, 0x67890000; + CHECKREG r6, 0x56780000; + CHECKREG r7, 0x00020000; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -1; + R7 = ASHIFT R0 BY R4.L; + R0 = ASHIFT R1 BY R4.L; + R1 = ASHIFT R2 BY R4.L; + R2 = ASHIFT R3 BY R4.L; + R3 = ASHIFT R4 BY R4.L; + R4 = ASHIFT R5 BY R4.L; + R5 = ASHIFT R6 BY R4.L; + R6 = ASHIFT R7 BY R4.L; + CHECKREG r0, 0x091A2B3C; + CHECKREG r1, 0x11A2B3C4; + CHECKREG r2, 0x1A2B3C4D; + CHECKREG r3, 0x22B3FFFF; + CHECKREG r4, 0x2B3C4D5E; + CHECKREG r5, 0x40000000; + CHECKREG r6, 0x40000000; + CHECKREG r7, 0x00918001; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R5.L = -6; + R6 = ASHIFT R0 BY R5.L; + R7 = ASHIFT R1 BY R5.L; + R0 = ASHIFT R2 BY R5.L; + R1 = ASHIFT R3 BY R5.L; + R2 = ASHIFT R4 BY R5.L; + R3 = ASHIFT R5 BY R5.L; + R4 = ASHIFT R6 BY R5.L; + R5 = ASHIFT R7 BY R5.L; + CHECKREG r0, 0xFE4D159E; + CHECKREG r1, 0xFE9159E2; + CHECKREG r2, 0xFED59E26; + CHECKREG r3, 0xFF19E3FF; + CHECKREG r4, 0x00001230; + CHECKREG r5, 0xFFF82345; + CHECKREG r6, 0x00048C00; + CHECKREG r7, 0xFE08D159; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -15; + R5 = ASHIFT R0 BY R6.L; + R0 = ASHIFT R1 BY R6.L; + R7 = ASHIFT R2 BY R6.L; + R0 = ASHIFT R3 BY R6.L; + R1 = ASHIFT R4 BY R6.L; + R2 = ASHIFT R5 BY R6.L; + R3 = ASHIFT R6 BY R6.L; + R6 = ASHIFT R7 BY R6.L; + CHECKREG r0, 0x000068AC; + CHECKREG r1, 0x00008ACF; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x0000CF13; + CHECKREG r4, 0x456789AB; + CHECKREG r5, 0x00000246; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x0000468A; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R7.L = -14; + R0 = ASHIFT R0 BY R7.L; + R1 = ASHIFT R1 BY R7.L; + R2 = ASHIFT R2 BY R7.L; + R3 = ASHIFT R3 BY R7.L; + R4 = ASHIFT R4 BY R7.L; + R5 = ASHIFT R5 BY R7.L; + R6 = ASHIFT R6 BY R7.L; + R7 = ASHIFT R7 BY R7.L; + CHECKREG r0, 0x0000048C; + CHECKREG r1, 0xFFFE08D1; + CHECKREG r2, 0xFFFE4D15; + CHECKREG r3, 0xFFFE9159; + CHECKREG r4, 0xFFFED59E; + CHECKREG r5, 0xFFFF19E2; + CHECKREG r6, 0xFFFF5E26; + CHECKREG r7, 0xFFFFA26B; + + pass diff --git a/sim/testsuite/bfin/c_dsp32shift_af_s.s b/sim/testsuite/bfin/c_dsp32shift_af_s.s new file mode 100644 index 0000000..e94f7cb --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_af_s.s @@ -0,0 +1,186 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_af_s/c_dsp32shift_af_s.dsp +// Spec Reference: dsp32shift ashift s +# mach: bfin + +.include "testutils.inc" + start + +// ashift : mix data, count (+)= (half reg) +// d_reg = ashift (d BY d_lo) +// Rx by RLx + imm32 r0, 0x01230001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x856789ab; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R4 = ASHIFT R0 BY R0.L (S); + R5 = ASHIFT R1 BY R0.L (S); + R6 = ASHIFT R2 BY R0.L (S); + R7 = ASHIFT R3 BY R0.L (S); + CHECKREG r4, 0x02460002; + CHECKREG r5, 0x2468ACF0; + CHECKREG r6, 0x468ACF12; + CHECKREG r7, 0x68ACF134; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0xa6789abc; + imm32 r6, 0xb789abcd; + imm32 r7, 0xc89abcde; + R1.L = 5; + R5 = ASHIFT R0 BY R1.L (S); + R6 = ASHIFT R1 BY R1.L (S); + R7 = ASHIFT R2 BY R1.L (S); + R4 = ASHIFT R3 BY R1.L (S); + CHECKREG r4, 0x7FFFFFFF; + CHECKREG r5, 0x24600040; + CHECKREG r6, 0x7FFFFFFF; + CHECKREG r7, 0x7FFFFFFF; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2 = 14; + R6 = ASHIFT R0 BY R2.L (S); + R7 = ASHIFT R1 BY R2.L (S); + R4 = ASHIFT R2 BY R2.L (S); + R5 = ASHIFT R3 BY R2.L (S); + CHECKREG r4, 0x00038000; + CHECKREG r5, 0x7FFFFFFF; + CHECKREG r6, 0x7FFFFFFF; + CHECKREG r7, 0x7FFFFFFF; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0xa56789ab; + imm32 r5, 0xb6789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0xd89abcde; + R3.L = 15; + R7 = ASHIFT R0 BY R3.L (S); + R6 = ASHIFT R1 BY R3.L (S); + R5 = ASHIFT R2 BY R3.L (S); + R4 = ASHIFT R3 BY R3.L (S); + CHECKREG r4, 0x7FFFFFFF; + CHECKREG r5, 0x7FFFFFFF; + CHECKREG r6, 0x7FFFFFFF; + CHECKREG r7, 0x7FFFFFFF; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -1; + R7 = ASHIFT R0 BY R4.L; + R0 = ASHIFT R1 BY R4.L; + R1 = ASHIFT R2 BY R4.L; + R2 = ASHIFT R3 BY R4.L; + R3 = ASHIFT R4 BY R4.L; + R4 = ASHIFT R5 BY R4.L; + R5 = ASHIFT R6 BY R4.L; + R6 = ASHIFT R7 BY R4.L; + CHECKREG r0, 0x091A2B3C; + CHECKREG r1, 0x11A2B3C4; + CHECKREG r2, 0x1A2B3C4D; + CHECKREG r3, 0x22B3FFFF; + CHECKREG r4, 0x2B3C4D5E; + CHECKREG r5, 0x40000000; + CHECKREG r6, 0x40000000; + CHECKREG r7, 0x00918001; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R5.L = -6; + R6 = ASHIFT R0 BY R5.L (S); + R7 = ASHIFT R1 BY R5.L (S); + R0 = ASHIFT R2 BY R5.L (S); + R1 = ASHIFT R3 BY R5.L (S); + R2 = ASHIFT R4 BY R5.L (S); + R3 = ASHIFT R5 BY R5.L (S); + R4 = ASHIFT R6 BY R5.L (S); + R5 = ASHIFT R7 BY R5.L (S); + CHECKREG r0, 0xFE4D159E; + CHECKREG r1, 0xFE9159E2; + CHECKREG r2, 0xFED59E26; + CHECKREG r3, 0xFF19E3FF; + CHECKREG r4, 0x00001230; + CHECKREG r5, 0xFFF82345; + CHECKREG r6, 0x00048C00; + CHECKREG r7, 0xFE08D159; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -15; + R5 = ASHIFT R0 BY R6.L (S); + R0 = ASHIFT R1 BY R6.L (S); + R7 = ASHIFT R2 BY R6.L (S); + R0 = ASHIFT R3 BY R6.L (S); + R1 = ASHIFT R4 BY R6.L (S); + R2 = ASHIFT R5 BY R6.L (S); + R3 = ASHIFT R6 BY R6.L (S); + R6 = ASHIFT R7 BY R6.L (S); + CHECKREG r0, 0x000068AC; + CHECKREG r1, 0x00008ACF; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x0000CF13; + CHECKREG r4, 0x456789AB; + CHECKREG r5, 0x00000246; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x0000468A; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R7.L = -14; + R0 = ASHIFT R0 BY R7.L (S); + R1 = ASHIFT R1 BY R7.L (S); + R2 = ASHIFT R2 BY R7.L (S); + R3 = ASHIFT R3 BY R7.L (S); + R4 = ASHIFT R4 BY R7.L (S); + R5 = ASHIFT R5 BY R7.L (S); + R6 = ASHIFT R6 BY R7.L (S); + R7 = ASHIFT R7 BY R7.L (S); + CHECKREG r0, 0x0000048C; + CHECKREG r1, 0xFFFE08D1; + CHECKREG r2, 0xFFFE4D15; + CHECKREG r3, 0xFFFE9159; + CHECKREG r4, 0xFFFED59E; + CHECKREG r5, 0xFFFF19E2; + CHECKREG r6, 0xFFFF5E26; + CHECKREG r7, 0xFFFFA26B; + + pass diff --git a/sim/testsuite/bfin/c_dsp32shift_ahalf_ln.s b/sim/testsuite/bfin/c_dsp32shift_ahalf_ln.s new file mode 100644 index 0000000..9a37aef --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_ahalf_ln.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_ln/c_dsp32shift_ahalf_ln.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + + +// Ashift : neg data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R0.L = ASHIFT R0.L BY R0.L; +R1.L = ASHIFT R1.L BY R0.L; +R2.L = ASHIFT R2.L BY R0.L; +R3.L = ASHIFT R3.L BY R0.L; +R4.L = ASHIFT R4.L BY R0.L; +R5.L = ASHIFT R5.L BY R0.L; +R6.L = ASHIFT R6.L BY R0.L; +R7.L = ASHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c001; +CHECKREG r2, 0x0000c002; +CHECKREG r3, 0x0000c003; +CHECKREG r4, 0x0000c004; +CHECKREG r5, 0x0000c005; +CHECKREG r6, 0x0000c006; +CHECKREG r7, 0x0000c007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R0.L = ASHIFT R0.L BY R1.L; +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L; +R3.L = ASHIFT R3.L BY R1.L; +R4.L = ASHIFT R4.L BY R1.L; +R5.L = ASHIFT R5.L BY R1.L; +R6.L = ASHIFT R6.L BY R1.L; +R7.L = ASHIFT R7.L BY R1.L; +//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */ +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000a004; +CHECKREG r3, 0x0000c006; +CHECKREG r4, 0x0000e008; +CHECKREG r5, 0x0000800a; +CHECKREG r6, 0x0000a00c; +CHECKREG r7, 0x0000c00e; + + +imm32 r0, 0x0000c001; +imm32 r1, 0x0000d001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = ASHIFT R0.L BY R2.L; +R1.L = ASHIFT R1.L BY R2.L; +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L; +R4.L = ASHIFT R4.L BY R2.L; +R5.L = ASHIFT R5.L BY R2.L; +R6.L = ASHIFT R6.L BY R2.L; +R7.L = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00009001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000b002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000f007; +R0.L = ASHIFT R0.L BY R3.L; +R1.L = ASHIFT R1.L BY R3.L; +R2.L = ASHIFT R2.L BY R3.L; +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L; +R5.L = ASHIFT R5.L BY R3.L; +R6.L = ASHIFT R6.L BY R3.L; +R7.L = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L; +R1.L = ASHIFT R1.H BY R0.L; +R2.L = ASHIFT R2.H BY R0.L; +R3.L = ASHIFT R3.H BY R0.L; +R4.L = ASHIFT R4.H BY R0.L; +R5.L = ASHIFT R5.H BY R0.L; +R6.L = ASHIFT R6.H BY R0.L; +R7.L = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R0.L = ASHIFT R0.H BY R1.L; +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L; +R3.L = ASHIFT R3.H BY R1.L; +R4.L = ASHIFT R4.H BY R1.L; +R5.L = ASHIFT R5.H BY R1.L; +R6.L = ASHIFT R6.H BY R1.L; +R7.L = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x90012002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x90022004; +CHECKREG r3, 0x90032006; +CHECKREG r4, 0x90042008; +CHECKREG r5, 0x9005200a; +CHECKREG r6, 0x9006200c; +CHECKREG r7, 0x9007200e; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0xa0018000; +CHECKREG r1, 0xa0018000; +CHECKREG r2, 0xa002000f; +CHECKREG r3, 0xa0038000; +CHECKREG r4, 0xa0040000; +CHECKREG r5, 0xa0058000; +CHECKREG r6, 0xa0060000; +CHECKREG r7, 0xa0078000; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc0070007; +R0.L = ASHIFT R0.H BY R3.L; +R1.L = ASHIFT R1.H BY R3.L; +R2.L = ASHIFT R2.H BY R3.L; +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L; +R5.L = ASHIFT R5.H BY R3.L; +R6.L = ASHIFT R6.H BY R3.L; +R7.L = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0xc0010000; +CHECKREG r1, 0xc0010000; +CHECKREG r2, 0xc0020000; +CHECKREG r3, 0xc0030010; +CHECKREG r4, 0xc0040000; +CHECKREG r5, 0xc0050000; +CHECKREG r6, 0xc0060000; +CHECKREG r7, 0xc0070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R0.L; +R1.H = ASHIFT R1.L BY R0.L; +R2.H = ASHIFT R2.L BY R0.L; +R3.H = ASHIFT R3.L BY R0.L; +R4.H = ASHIFT R4.L BY R0.L; +R5.H = ASHIFT R5.L BY R0.L; +R6.H = ASHIFT R6.L BY R0.L; +R7.H = ASHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R0.H = ASHIFT R0.L BY R1.L; +R1.H = ASHIFT R1.L BY R1.L; +R2.H = ASHIFT R2.L BY R1.L; +R3.H = ASHIFT R3.L BY R1.L; +R4.H = ASHIFT R4.L BY R1.L; +R5.H = ASHIFT R5.L BY R1.L; +R6.H = ASHIFT R6.L BY R1.L; +R7.H = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0xa002d001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0xa004d002; +CHECKREG r3, 0xa006d003; +CHECKREG r4, 0xa008d004; +CHECKREG r5, 0xa00ad005; +CHECKREG r6, 0xa00cd006; +CHECKREG r7, 0xa00ed007; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = ASHIFT R0.L BY R2.L; +R1.H = ASHIFT R1.L BY R2.L; +//rh2 = ashift (rl2 by rl2); +R3.H = ASHIFT R3.L BY R2.L; +R4.H = ASHIFT R4.L BY R2.L; +R5.H = ASHIFT R5.L BY R2.L; +R6.H = ASHIFT R6.L BY R2.L; +R7.H = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x8000e001; +CHECKREG r1, 0x8000e001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x8000e003; +CHECKREG r4, 0x0000e004; +CHECKREG r5, 0x8000e005; +CHECKREG r6, 0x0000e006; +CHECKREG r7, 0x8000e007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.H = ASHIFT R0.L BY R3.L; +R1.H = ASHIFT R1.L BY R3.L; +R2.H = ASHIFT R2.L BY R3.L; +R3.H = ASHIFT R3.L BY R3.L; +R4.H = ASHIFT R4.L BY R3.L; +R5.H = ASHIFT R5.L BY R3.L; +R6.H = ASHIFT R6.L BY R3.L; +R7.H = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x0000f001; +CHECKREG r1, 0x0000f001; +CHECKREG r2, 0x0000f002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000f004; +CHECKREG r5, 0x0000f005; +CHECKREG r6, 0x0000f006; +CHECKREG r7, 0x0000f007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R0.L; +R1.H = ASHIFT R1.H BY R0.L; +R2.H = ASHIFT R2.H BY R0.L; +R3.H = ASHIFT R3.H BY R0.L; +R4.H = ASHIFT R4.H BY R0.L; +R5.H = ASHIFT R5.H BY R0.L; +R6.H = ASHIFT R6.H BY R0.L; +R7.H = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.H = ASHIFT R0.H BY R1.L; +R1.H = ASHIFT R1.H BY R1.L; +R2.H = ASHIFT R2.H BY R1.L; +R3.H = ASHIFT R3.H BY R1.L; +R4.H = ASHIFT R4.H BY R1.L; +R5.H = ASHIFT R5.H BY R1.L; +R6.H = ASHIFT R6.H BY R1.L; +R7.H = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x40020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x40040000; +CHECKREG r3, 0x40060000; +CHECKREG r4, 0x40080000; +CHECKREG r5, 0x400a0000; +CHECKREG r6, 0x400c0000; +CHECKREG r7, 0x400e0000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0xb0018000; +CHECKREG r1, 0xb0018000; +CHECKREG r2, 0xb002000f; +CHECKREG r3, 0xb0038000; +CHECKREG r4, 0xb0040000; +CHECKREG r5, 0xb0058000; +CHECKREG r6, 0xb0060000; +CHECKREG r7, 0xb0078000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R0.H = ASHIFT R0.H BY R3.L; +R1.H = ASHIFT R1.H BY R3.L; +R2.H = ASHIFT R2.H BY R3.L; +R3.H = ASHIFT R3.H BY R3.L; +R4.H = ASHIFT R4.H BY R3.L; +R5.H = ASHIFT R5.H BY R3.L; +R6.H = ASHIFT R6.H BY R3.L; +R7.H = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_ahalf_ln_s.s b/sim/testsuite/bfin/c_dsp32shift_ahalf_ln_s.s new file mode 100644 index 0000000..dd6b8d4 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_ahalf_ln_s.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_ln_s/c_dsp32shift_ahalf_ln_s.dsp +// Spec Reference: +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : neg data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R0.L = ASHIFT R0.L BY R0.L (S); +R1.L = ASHIFT R1.L BY R0.L (S); +R2.L = ASHIFT R2.L BY R0.L (S); +R3.L = ASHIFT R3.L BY R0.L (S); +R4.L = ASHIFT R4.L BY R0.L (S); +R5.L = ASHIFT R5.L BY R0.L (S); +R6.L = ASHIFT R6.L BY R0.L (S); +R7.L = ASHIFT R7.L BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c001; +CHECKREG r2, 0x0000c002; +CHECKREG r3, 0x0000c003; +CHECKREG r4, 0x0000c004; +CHECKREG r5, 0x0000c005; +CHECKREG r6, 0x0000c006; +CHECKREG r7, 0x0000c007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R0.L = ASHIFT R0.L BY R1.L (S); +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L (S); +R3.L = ASHIFT R3.L BY R1.L (S); +R4.L = ASHIFT R4.L BY R1.L (S); +R5.L = ASHIFT R5.L BY R1.L (S); +R6.L = ASHIFT R6.L BY R1.L (S); +R7.L = ASHIFT R7.L BY R1.L (S); +//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */ +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000a004; +CHECKREG r3, 0x0000c006; +CHECKREG r4, 0x0000e008; +CHECKREG r5, 0x0000800a; +CHECKREG r6, 0x0000a00c; +CHECKREG r7, 0x0000c00e; + + +imm32 r0, 0x0000c001; +imm32 r1, 0x0000d001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = ASHIFT R0.L BY R2.L (S); +R1.L = ASHIFT R1.L BY R2.L (S); +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L (S); +R4.L = ASHIFT R4.L BY R2.L (S); +R5.L = ASHIFT R5.L BY R2.L (S); +R6.L = ASHIFT R6.L BY R2.L (S); +R7.L = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00008000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00008000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00009001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000b002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000f007; +R0.L = ASHIFT R0.L BY R3.L (S); +R1.L = ASHIFT R1.L BY R3.L (S); +R2.L = ASHIFT R2.L BY R3.L (S); +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L (S); +R5.L = ASHIFT R5.L BY R3.L (S); +R6.L = ASHIFT R6.L BY R3.L (S); +R7.L = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x00008000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00008000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00008000; +CHECKREG r7, 0x00008000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L (S); +R1.L = ASHIFT R1.H BY R0.L (S); +R2.L = ASHIFT R2.H BY R0.L (S); +R3.L = ASHIFT R3.H BY R0.L (S); +R4.L = ASHIFT R4.H BY R0.L (S); +R5.L = ASHIFT R5.H BY R0.L (S); +R6.L = ASHIFT R6.H BY R0.L (S); +R7.L = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R0.L = ASHIFT R0.H BY R1.L (S); +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L (S); +R3.L = ASHIFT R3.H BY R1.L (S); +R4.L = ASHIFT R4.H BY R1.L (S); +R5.L = ASHIFT R5.H BY R1.L (S); +R6.L = ASHIFT R6.H BY R1.L (S); +R7.L = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x90018000; +//CHECKREG r1, 0x00018000; +CHECKREG r2, 0x90028000; +CHECKREG r3, 0x90038000; +CHECKREG r4, 0x90048000; +CHECKREG r5, 0x90058000; +CHECKREG r6, 0x90068000; +CHECKREG r7, 0x90078000; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0xa0018000; +CHECKREG r1, 0xa0018000; +//CHECKREG r2, 0xa002000f; +CHECKREG r3, 0xa0038000; +CHECKREG r4, 0xa0048000; +CHECKREG r5, 0xa0058000; +CHECKREG r6, 0xa0068000; +CHECKREG r7, 0xa0078000; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc0070007; +R0.L = ASHIFT R0.H BY R3.L (S); +R1.L = ASHIFT R1.H BY R3.L (S); +R2.L = ASHIFT R2.H BY R3.L (S); +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L (S); +R5.L = ASHIFT R5.H BY R3.L (S); +R6.L = ASHIFT R6.H BY R3.L (S); +R7.L = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0xc0018000; +CHECKREG r1, 0xc0018000; +CHECKREG r2, 0xc0028000; +CHECKREG r3, 0xc0030010; +CHECKREG r4, 0xc0048000; +CHECKREG r5, 0xc0058000; +CHECKREG r6, 0xc0068000; +CHECKREG r7, 0xc0078000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R0.L (S); +R1.H = ASHIFT R1.L BY R0.L (S); +R2.H = ASHIFT R2.L BY R0.L (S); +R3.H = ASHIFT R3.L BY R0.L (S); +R4.H = ASHIFT R4.L BY R0.L (S); +R5.H = ASHIFT R5.L BY R0.L (S); +R6.H = ASHIFT R6.L BY R0.L (S); +R7.H = ASHIFT R7.L BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R0.H = ASHIFT R0.L BY R1.L (S); +R1.H = ASHIFT R1.L BY R1.L (S); +R2.H = ASHIFT R2.L BY R1.L (S); +R3.H = ASHIFT R3.L BY R1.L (S); +R4.H = ASHIFT R4.L BY R1.L (S); +R5.H = ASHIFT R5.L BY R1.L (S); +R6.H = ASHIFT R6.L BY R1.L (S); +R7.H = ASHIFT R7.L BY R1.L (S); +CHECKREG r0, 0xa002d001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0xa004d002; +CHECKREG r3, 0xa006d003; +CHECKREG r4, 0xa008d004; +CHECKREG r5, 0xa00ad005; +CHECKREG r6, 0xa00cd006; +CHECKREG r7, 0xa00ed007; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = ASHIFT R0.L BY R2.L (S); +R1.H = ASHIFT R1.L BY R2.L (S); +//rh2 = ashift (rl2 by rl2); +R3.H = ASHIFT R3.L BY R2.L (S); +R4.H = ASHIFT R4.L BY R2.L (S); +R5.H = ASHIFT R5.L BY R2.L (S); +R6.H = ASHIFT R6.L BY R2.L (S); +R7.H = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x8000e001; +CHECKREG r1, 0x8000e001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x8000e003; +CHECKREG r4, 0x8000e004; +CHECKREG r5, 0x8000e005; +CHECKREG r6, 0x8000e006; +CHECKREG r7, 0x8000e007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.H = ASHIFT R0.L BY R3.L (S); +R1.H = ASHIFT R1.L BY R3.L (S); +R2.H = ASHIFT R2.L BY R3.L (S); +//rh3 = ashift (rl3 by rl3) s; +R4.H = ASHIFT R4.L BY R3.L (S); +R5.H = ASHIFT R5.L BY R3.L (S); +R6.H = ASHIFT R6.L BY R3.L (S); +R7.H = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x8000f001; +CHECKREG r1, 0x8000f001; +CHECKREG r2, 0x8000f002; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x8000f004; +CHECKREG r5, 0x8000f005; +CHECKREG r6, 0x8000f006; +CHECKREG r7, 0x8000f007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R0.L (S); +R1.H = ASHIFT R1.H BY R0.L (S); +R2.H = ASHIFT R2.H BY R0.L (S); +R3.H = ASHIFT R3.H BY R0.L (S); +R4.H = ASHIFT R4.H BY R0.L (S); +R5.H = ASHIFT R5.H BY R0.L (S); +R6.H = ASHIFT R6.H BY R0.L (S); +R7.H = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.H = ASHIFT R0.H BY R1.L (S); +R1.H = ASHIFT R1.H BY R1.L (S); +R2.H = ASHIFT R2.H BY R1.L (S); +R3.H = ASHIFT R3.H BY R1.L (S); +R4.H = ASHIFT R4.H BY R1.L (S); +R5.H = ASHIFT R5.H BY R1.L (S); +R6.H = ASHIFT R6.H BY R1.L (S); +R7.H = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x80000000; +//CHECKREG r1, 0x80000000; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0xb0018000; +CHECKREG r1, 0xb0018000; +//CHECKREG r2, 0xb002000f; +CHECKREG r3, 0xb0038000; +CHECKREG r4, 0xb0048000; +CHECKREG r5, 0xb0058000; +CHECKREG r6, 0xb0068000; +CHECKREG r7, 0xb0078000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R0.H = ASHIFT R0.H BY R3.L (S); +R1.H = ASHIFT R1.H BY R3.L (S); +R2.H = ASHIFT R2.H BY R3.L (S); +R3.H = ASHIFT R3.H BY R3.L (S); +R4.H = ASHIFT R4.H BY R3.L (S); +R5.H = ASHIFT R5.H BY R3.L (S); +R6.H = ASHIFT R6.H BY R3.L (S); +R7.H = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x80000000; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x80000010; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_ahalf_lp.s b/sim/testsuite/bfin/c_dsp32shift_ahalf_lp.s new file mode 100644 index 0000000..ecfa5f6 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_ahalf_lp.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_lp/c_dsp32shift_ahalf_lp.dsp +// Spec Reference: dsp32shift ashift half reg left positive +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R0.L; +R1.L = ASHIFT R1.L BY R0.L; +R2.L = ASHIFT R2.L BY R0.L; +R3.L = ASHIFT R3.L BY R0.L; +R4.L = ASHIFT R4.L BY R0.L; +R5.L = ASHIFT R5.L BY R0.L; +R6.L = ASHIFT R6.L BY R0.L; +R7.L = ASHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R1.L; +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L; +R3.L = ASHIFT R3.L BY R1.L; +R4.L = ASHIFT R4.L BY R1.L; +R5.L = ASHIFT R5.L BY R1.L; +R6.L = ASHIFT R6.L BY R1.L; +R7.L = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000006; +CHECKREG r4, 0x00000008; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x0000000c; +CHECKREG r7, 0x0000000e; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R2.L; +R1.L = ASHIFT R1.L BY R2.L; +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L; +R4.L = ASHIFT R4.L BY R2.L; +R5.L = ASHIFT R5.L BY R2.L; +R6.L = ASHIFT R6.L BY R2.L; +R7.L = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R3.L; +R1.L = ASHIFT R1.L BY R3.L; +R2.L = ASHIFT R2.L BY R3.L; +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L; +R5.L = ASHIFT R5.L BY R3.L; +R6.L = ASHIFT R6.L BY R3.L; +R7.L = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L; +R1.L = ASHIFT R1.H BY R0.L; +R2.L = ASHIFT R2.H BY R0.L; +R3.L = ASHIFT R3.H BY R0.L; +R4.L = ASHIFT R4.H BY R0.L; +R5.L = ASHIFT R5.H BY R0.L; +R6.L = ASHIFT R6.H BY R0.L; +R7.L = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R1.L; +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L; +R3.L = ASHIFT R3.H BY R1.L; +R4.L = ASHIFT R4.H BY R1.L; +R5.L = ASHIFT R5.H BY R1.L; +R6.L = ASHIFT R6.H BY R1.L; +R7.L = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x00010002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020004; +CHECKREG r3, 0x00030006; +CHECKREG r4, 0x00040008; +CHECKREG r5, 0x0005000a; +CHECKREG r6, 0x0006000c; +CHECKREG r7, 0x0007000e; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0x00018000; +CHECKREG r1, 0x00018000; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00038000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00058000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x00010001; +imm32 r1, 0x00010001; +imm32 r2, 0x00020002; +imm32 r3, 0x00030010; +imm32 r4, 0x00040004; +imm32 r5, 0x00050005; +imm32 r6, 0x00060006; +imm32 r7, 0x00070007; +R0.L = ASHIFT R0.H BY R3.L; +R1.L = ASHIFT R1.H BY R3.L; +R2.L = ASHIFT R2.H BY R3.L; +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L; +R5.L = ASHIFT R5.H BY R3.L; +R6.L = ASHIFT R6.H BY R3.L; +R7.L = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030010; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R0.L; +R1.H = ASHIFT R1.L BY R0.L; +R2.H = ASHIFT R2.L BY R0.L; +R3.H = ASHIFT R3.L BY R0.L; +R4.H = ASHIFT R4.L BY R0.L; +R5.H = ASHIFT R5.L BY R0.L; +R6.H = ASHIFT R6.L BY R0.L; +R7.H = ASHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R1.L; +R1.H = ASHIFT R1.L BY R1.L; +R2.H = ASHIFT R2.L BY R1.L; +R3.H = ASHIFT R3.L BY R1.L; +R4.H = ASHIFT R4.L BY R1.L; +R5.H = ASHIFT R5.L BY R1.L; +R6.H = ASHIFT R6.L BY R1.L; +R7.H = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0x00020001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040002; +CHECKREG r3, 0x00060003; +CHECKREG r4, 0x00080004; +CHECKREG r5, 0x000a0005; +CHECKREG r6, 0x000c0006; +CHECKREG r7, 0x000e0007; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R2.L; +R1.H = ASHIFT R1.L BY R2.L; +//rh2 = ashift (rl2 by rl2); +R3.H = ASHIFT R3.L BY R2.L; +R4.H = ASHIFT R4.L BY R2.L; +R5.H = ASHIFT R5.L BY R2.L; +R6.H = ASHIFT R6.L BY R2.L; +R7.H = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x80000001; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x80000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x80000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x80000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R3.L; +R1.H = ASHIFT R1.L BY R3.L; +R2.H = ASHIFT R2.L BY R3.L; +R3.H = ASHIFT R3.L BY R3.L; +R4.H = ASHIFT R4.L BY R3.L; +R5.H = ASHIFT R5.L BY R3.L; +R6.H = ASHIFT R6.L BY R3.L; +R7.H = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R0.L; +R1.H = ASHIFT R1.H BY R0.L; +R2.H = ASHIFT R2.H BY R0.L; +R3.H = ASHIFT R3.H BY R0.L; +R4.H = ASHIFT R4.H BY R0.L; +R5.H = ASHIFT R5.H BY R0.L; +R6.H = ASHIFT R6.H BY R0.L; +R7.H = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R1.L; +R1.H = ASHIFT R1.H BY R1.L; +R2.H = ASHIFT R2.H BY R1.L; +R3.H = ASHIFT R3.H BY R1.L; +R4.H = ASHIFT R4.H BY R1.L; +R5.H = ASHIFT R5.H BY R1.L; +R6.H = ASHIFT R6.H BY R1.L; +R7.H = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x00020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040000; +CHECKREG r3, 0x00060000; +CHECKREG r4, 0x00080000; +CHECKREG r5, 0x000a0000; +CHECKREG r6, 0x000c0000; +CHECKREG r7, 0x000e0000; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0x00018000; +CHECKREG r1, 0x00018000; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00038000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00058000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030010; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R3.L; +R1.H = ASHIFT R1.H BY R3.L; +R2.H = ASHIFT R2.H BY R3.L; +R3.H = ASHIFT R3.H BY R3.L; +R4.H = ASHIFT R4.H BY R3.L; +R5.H = ASHIFT R5.H BY R3.L; +R6.H = ASHIFT R6.H BY R3.L; +R7.H = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_ahalf_lp_s.s b/sim/testsuite/bfin/c_dsp32shift_ahalf_lp_s.s new file mode 100644 index 0000000..b07eed8 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_ahalf_lp_s.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_lp_s/c_dsp32shift_ahalf_lp_s.dsp +// Spec Reference: dsp32shift ashift s +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R0.L (S); +R1.L = ASHIFT R1.L BY R0.L (S); +R2.L = ASHIFT R2.L BY R0.L (S); +R3.L = ASHIFT R3.L BY R0.L (S); +R4.L = ASHIFT R4.L BY R0.L (S); +R5.L = ASHIFT R5.L BY R0.L (S); +R6.L = ASHIFT R6.L BY R0.L (S); +R7.L = ASHIFT R7.L BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R1.L (S); +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L (S); +R3.L = ASHIFT R3.L BY R1.L (S); +R4.L = ASHIFT R4.L BY R1.L (S); +R5.L = ASHIFT R5.L BY R1.L (S); +R6.L = ASHIFT R6.L BY R1.L (S); +R7.L = ASHIFT R7.L BY R1.L (S); +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000006; +CHECKREG r4, 0x00000008; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x0000000c; +CHECKREG r7, 0x0000000e; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R2.L (S); +R1.L = ASHIFT R1.L BY R2.L (S); +//rl2 = ashift (rl2 by rl2) s; +R3.L = ASHIFT R3.L BY R2.L (S); +R4.L = ASHIFT R4.L BY R2.L (S); +R5.L = ASHIFT R5.L BY R2.L (S); +R6.L = ASHIFT R6.L BY R2.L (S); +R7.L = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x00007fff; +CHECKREG r1, 0x00007fff; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00007fff; +CHECKREG r4, 0x00007fff; +CHECKREG r5, 0x00007fff; +CHECKREG r6, 0x00007fff; +CHECKREG r7, 0x00007fff; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R3.L (S); +R1.L = ASHIFT R1.L BY R3.L (S); +R2.L = ASHIFT R2.L BY R3.L (S); +//rl3 = ashift (rl3 by rl3) s; +R4.L = ASHIFT R4.L BY R3.L (S); +R5.L = ASHIFT R5.L BY R3.L (S); +R6.L = ASHIFT R6.L BY R3.L (S); +R7.L = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x00007fff; +CHECKREG r1, 0x00007fff; +CHECKREG r2, 0x00007fff; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00007fff; +CHECKREG r5, 0x00007fff; +CHECKREG r6, 0x00007fff; +CHECKREG r7, 0x00007fff; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L (S); +R1.L = ASHIFT R1.H BY R0.L (S); +R2.L = ASHIFT R2.H BY R0.L (S); +R3.L = ASHIFT R3.H BY R0.L (S); +R4.L = ASHIFT R4.H BY R0.L (S); +R5.L = ASHIFT R5.H BY R0.L (S); +R6.L = ASHIFT R6.H BY R0.L (S); +R7.L = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R1.L (S); +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L (S); +R3.L = ASHIFT R3.H BY R1.L (S); +R4.L = ASHIFT R4.H BY R1.L (S); +R5.L = ASHIFT R5.H BY R1.L (S); +R6.L = ASHIFT R6.H BY R1.L (S); +R7.L = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x00010002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020004; +CHECKREG r3, 0x00030006; +CHECKREG r4, 0x00040008; +CHECKREG r5, 0x0005000a; +CHECKREG r6, 0x0006000c; +CHECKREG r7, 0x0007000e; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0x00017fff; +CHECKREG r1, 0x00017fff; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00037fff; +CHECKREG r4, 0x00047fff; +CHECKREG r5, 0x00057fff; +CHECKREG r6, 0x00067fff; +CHECKREG r7, 0x00077fff; + +imm32 r0, 0x00010001; +imm32 r1, 0x00010001; +imm32 r2, 0x00020002; +imm32 r3, 0x00030010; +imm32 r4, 0x00040004; +imm32 r5, 0x00050005; +imm32 r6, 0x00060006; +imm32 r7, 0x00070007; +R0.L = ASHIFT R0.H BY R3.L (S); +R1.L = ASHIFT R1.H BY R3.L (S); +R2.L = ASHIFT R2.H BY R3.L (S); +//rl3 = ashift (rh3 by rl3) s; +R4.L = ASHIFT R4.H BY R3.L (S); +R5.L = ASHIFT R5.H BY R3.L (S); +R6.L = ASHIFT R6.H BY R3.L (S); +R7.L = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0x00017fff; +CHECKREG r1, 0x00017fff; +CHECKREG r2, 0x00027fff; +CHECKREG r3, 0x00030010; +CHECKREG r4, 0x00047fff; +CHECKREG r5, 0x00057fff; +CHECKREG r6, 0x00067fff; +CHECKREG r7, 0x00077fff; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R0.L (S); +R1.H = ASHIFT R1.L BY R0.L (S); +R2.H = ASHIFT R2.L BY R0.L (S); +R3.H = ASHIFT R3.L BY R0.L (S); +R4.H = ASHIFT R4.L BY R0.L (S); +R5.H = ASHIFT R5.L BY R0.L (S); +R6.H = ASHIFT R6.L BY R0.L (S); +R7.H = ASHIFT R7.L BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R1.L (S); +R1.H = ASHIFT R1.L BY R1.L (S); +R2.H = ASHIFT R2.L BY R1.L (S); +R3.H = ASHIFT R3.L BY R1.L (S); +R4.H = ASHIFT R4.L BY R1.L (S); +R5.H = ASHIFT R5.L BY R1.L (S); +R6.H = ASHIFT R6.L BY R1.L (S); +R7.H = ASHIFT R7.L BY R1.L (S); +CHECKREG r0, 0x00020001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040002; +CHECKREG r3, 0x00060003; +CHECKREG r4, 0x00080004; +CHECKREG r5, 0x000a0005; +CHECKREG r6, 0x000c0006; +CHECKREG r7, 0x000e0007; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R2.L (S); +R1.H = ASHIFT R1.L BY R2.L (S); +//rh2 = ashift (rl2 by rl2) s; +R3.H = ASHIFT R3.L BY R2.L (S); +R4.H = ASHIFT R4.L BY R2.L (S); +R5.H = ASHIFT R5.L BY R2.L (S); +R6.H = ASHIFT R6.L BY R2.L (S); +R7.H = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x7fff0001; +CHECKREG r1, 0x7fff0001; +//ECKREG(r2, 0x7fff000f); +CHECKREG r3, 0x7fff0003; +CHECKREG r4, 0x7fff0004; +CHECKREG r5, 0x7fff0005; +CHECKREG r6, 0x7fff0006; +CHECKREG r7, 0x7fff0007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R3.L (S); +R1.H = ASHIFT R1.L BY R3.L (S); +R2.H = ASHIFT R2.L BY R3.L (S); +R3.H = ASHIFT R3.L BY R3.L (S); +R4.H = ASHIFT R4.L BY R3.L (S); +R5.H = ASHIFT R5.L BY R3.L (S); +R6.H = ASHIFT R6.L BY R3.L (S); +R7.H = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x7fff0001; +CHECKREG r1, 0x7fff0001; +CHECKREG r2, 0x7fff0002; +CHECKREG r3, 0x7fff0010; +CHECKREG r4, 0x7fff0004; +CHECKREG r5, 0x7fff0005; +CHECKREG r6, 0x7fff0006; +CHECKREG r7, 0x7fff0007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R0.L (S); +R1.H = ASHIFT R1.H BY R0.L (S); +R2.H = ASHIFT R2.H BY R0.L (S); +R3.H = ASHIFT R3.H BY R0.L (S); +R4.H = ASHIFT R4.H BY R0.L (S); +R5.H = ASHIFT R5.H BY R0.L (S); +R6.H = ASHIFT R6.H BY R0.L (S); +R7.H = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R1.L (S); +R1.H = ASHIFT R1.H BY R1.L (S); +R2.H = ASHIFT R2.H BY R1.L (S); +R3.H = ASHIFT R3.H BY R1.L (S); +R4.H = ASHIFT R4.H BY R1.L (S); +R5.H = ASHIFT R5.H BY R1.L (S); +R6.H = ASHIFT R6.H BY R1.L (S); +R7.H = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x00020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040000; +CHECKREG r3, 0x00060000; +CHECKREG r4, 0x00080000; +CHECKREG r5, 0x000a0000; +CHECKREG r6, 0x000c0000; +CHECKREG r7, 0x000e0000; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0x00017fff; +CHECKREG r1, 0x00017fff; +//CHECKREG r2, 0x00027fff; +CHECKREG r3, 0x00037fff; +CHECKREG r4, 0x00047fff; +CHECKREG r5, 0x00057fff; +CHECKREG r6, 0x00067fff; +CHECKREG r7, 0x00077fff; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030010; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R3.L (S); +R1.H = ASHIFT R1.H BY R3.L (S); +R2.H = ASHIFT R2.H BY R3.L (S); +R3.H = ASHIFT R3.H BY R3.L (S); +R4.H = ASHIFT R4.H BY R3.L (S); +R5.H = ASHIFT R5.H BY R3.L (S); +R6.H = ASHIFT R6.H BY R3.L (S); +R7.H = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0x7fff0000; +CHECKREG r1, 0x7fff0000; +CHECKREG r2, 0x7fff0000; +CHECKREG r3, 0x7fff0010; +CHECKREG r4, 0x7fff0000; +CHECKREG r5, 0x7fff0000; +CHECKREG r6, 0x7fff0000; +CHECKREG r7, 0x7fff0000; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_ahalf_rn.s b/sim/testsuite/bfin/c_dsp32shift_ahalf_rn.s new file mode 100644 index 0000000..aaa282c --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_ahalf_rn.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_rn/c_dsp32shift_ahalf_rn.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=right (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +//rl0 = ashift (rl0 by rl0); +R1.L = ASHIFT R1.L BY R0.L; +R2.L = ASHIFT R2.L BY R0.L; +R3.L = ASHIFT R3.L BY R0.L; +R4.L = ASHIFT R4.L BY R0.L; +R5.L = ASHIFT R5.L BY R0.L; +R6.L = ASHIFT R6.L BY R0.L; +R7.L = ASHIFT R7.L BY R0.L; +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c000; +CHECKREG r2, 0x0000c001; +CHECKREG r3, 0x0000c001; +CHECKREG r4, 0x0000c002; +CHECKREG r5, 0x0000c002; +CHECKREG r6, 0x0000c003; +CHECKREG r7, 0x0000c003; + +imm32 r0, 0x00008001; +R1.L = -1; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R1.L; +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L; +R3.L = ASHIFT R3.L BY R1.L; +R4.L = ASHIFT R4.L BY R1.L; +R5.L = ASHIFT R5.L BY R1.L; +R6.L = ASHIFT R6.L BY R1.L; +R7.L = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0x0000c000; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000c001; +CHECKREG r3, 0x0000c001; +CHECKREG r4, 0x0000c002; +CHECKREG r5, 0x0000c002; +CHECKREG r6, 0x0000c003; +CHECKREG r7, 0x0000c003; + + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +R2.L = -15; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R2.L; +R1.L = ASHIFT R1.L BY R2.L; +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L; +R4.L = ASHIFT R4.L BY R2.L; +R5.L = ASHIFT R5.L BY R2.L; +R6.L = ASHIFT R6.L BY R2.L; +R7.L = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0000ffff; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x0000ffff; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +R3.L = -16; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R3.L; +R1.L = ASHIFT R1.L BY R3.L; +R2.L = ASHIFT R2.L BY R3.L; +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L; +R5.L = ASHIFT R5.L BY R3.L; +R6.L = ASHIFT R6.L BY R3.L; +R7.L = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0000ffff; +CHECKREG r2, 0x0000ffff; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = ASHIFT R0.H BY R0.L; +R1.L = ASHIFT R1.H BY R0.L; +R2.L = ASHIFT R2.H BY R0.L; +R3.L = ASHIFT R3.H BY R0.L; +R4.L = ASHIFT R4.H BY R0.L; +R5.L = ASHIFT R5.H BY R0.L; +R6.L = ASHIFT R6.H BY R0.L; +R7.L = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x80018001; +CHECKREG r2, 0x80028002; +CHECKREG r3, 0x80038003; +CHECKREG r4, 0x80048004; +CHECKREG r5, 0x80058005; +CHECKREG r6, 0x80068006; +CHECKREG r7, 0x80078007; + +imm32 r0, 0x80010000; +R1.L = -1; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = ASHIFT R0.H BY R1.L; +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L; +R3.L = ASHIFT R3.H BY R1.L; +R4.L = ASHIFT R4.H BY R1.L; +R5.L = ASHIFT R5.H BY R1.L; +R6.L = ASHIFT R6.H BY R1.L; +R7.L = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x8001c000; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x8002c001; +CHECKREG r3, 0x8003c001; +CHECKREG r4, 0x8004c002; +CHECKREG r5, 0x8005c002; +CHECKREG r6, 0x8006c003; +CHECKREG r7, 0x8007c003; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +R2.L = -15; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0xa001ffff; +CHECKREG r1, 0xa001ffff; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0xa003ffff; +CHECKREG r4, 0xa004ffff; +CHECKREG r5, 0xa005ffff; +CHECKREG r6, 0xa006ffff; +CHECKREG r7, 0xa007ffff; + +imm32 r0, 0xb0010001; +imm32 r1, 0xb0010001; +imm32 r2, 0xb0020002; +R3.L = -16; +imm32 r4, 0xb0040004; +imm32 r5, 0xb0050005; +imm32 r6, 0xb0060006; +imm32 r7, 0xb0070007; +R0.L = ASHIFT R0.H BY R3.L; +R1.L = ASHIFT R1.H BY R3.L; +R2.L = ASHIFT R2.H BY R3.L; +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L; +R5.L = ASHIFT R5.H BY R3.L; +R6.L = ASHIFT R6.H BY R3.L; +R7.L = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0xb001ffff; +CHECKREG r1, 0xb001ffff; +CHECKREG r2, 0xb002ffff; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0xb004ffff; +CHECKREG r5, 0xb005ffff; +CHECKREG r6, 0xb006ffff; +CHECKREG r7, 0xb007ffff; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R4.L; +R1.H = ASHIFT R1.L BY R4.L; +R2.H = ASHIFT R2.L BY R4.L; +R3.H = ASHIFT R3.L BY R4.L; +//rh4 = ashift (rl4 by rl4); +R5.H = ASHIFT R5.L BY R4.L; +R6.H = ASHIFT R6.L BY R4.L; +R7.H = ASHIFT R7.L BY R4.L; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +R5.L = -1; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = ASHIFT R0.L BY R5.L; +R1.H = ASHIFT R1.L BY R5.L; +R2.H = ASHIFT R2.L BY R5.L; +R3.H = ASHIFT R3.L BY R5.L; +R4.H = ASHIFT R4.L BY R5.L; +//rh5 = ashift (rl5 by rl5); +R6.H = ASHIFT R6.L BY R5.L; +R7.H = ASHIFT R7.L BY R5.L; +CHECKREG r0, 0xc0008001; +CHECKREG r1, 0xc0008001; +CHECKREG r2, 0xc0018002; +CHECKREG r3, 0xc0018003; +CHECKREG r4, 0xc0028004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0xc0038006; +CHECKREG r7, 0xc0038007; + + +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009004; +imm32 r5, 0x00009005; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = ASHIFT R0.L BY R6.L; +R1.H = ASHIFT R1.L BY R6.L; +R2.H = ASHIFT R2.L BY R6.L; +R3.H = ASHIFT R3.L BY R6.L; +R4.H = ASHIFT R4.L BY R6.L; +R5.H = ASHIFT R5.L BY R6.L; +//rh6 = ashift (rl6 by rl6); +R7.H = ASHIFT R7.L BY R6.L; +CHECKREG r0, 0xffff9001; +CHECKREG r1, 0xffff9001; +CHECKREG r2, 0xffff9002; +CHECKREG r3, 0xffff9003; +CHECKREG r4, 0xffff9004; +CHECKREG r5, 0xffff9005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0xffff9007; + +imm32 r0, 0x0000a001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000a002; +imm32 r3, 0x0000a003; +imm32 r4, 0x0000a004; +imm32 r5, 0x0000a005; +imm32 r6, 0x0000a006; +R7.L = -16; +R0.H = ASHIFT R0.L BY R7.L; +R1.H = ASHIFT R1.L BY R7.L; +R2.H = ASHIFT R2.L BY R7.L; +R3.H = ASHIFT R3.L BY R7.L; +R4.H = ASHIFT R4.L BY R7.L; +R5.H = ASHIFT R5.L BY R7.L; +R6.H = ASHIFT R6.L BY R7.L; +R7.H = ASHIFT R7.L BY R7.L; +CHECKREG r0, 0xffffa001; +CHECKREG r1, 0xffffa001; +CHECKREG r2, 0xffffa002; +CHECKREG r3, 0xffffa003; +CHECKREG r4, 0xffffa004; +CHECKREG r5, 0xffffa005; +CHECKREG r6, 0xffffa006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +R4.L = -1; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = ASHIFT R0.H BY R4.L; +R1.H = ASHIFT R1.H BY R4.L; +R2.H = ASHIFT R2.H BY R4.L; +R3.H = ASHIFT R3.H BY R4.L; +//rh4 = ashift (rh4 by rl4); +R5.H = ASHIFT R5.H BY R4.L; +R6.H = ASHIFT R6.H BY R4.L; +R7.H = ASHIFT R7.H BY R4.L; +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xc0010000; +CHECKREG r3, 0xc0010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0xc0020000; +CHECKREG r6, 0xc0030000; +CHECKREG r7, 0xc0030000; + +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +R5.L = -1; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = ASHIFT R0.H BY R5.L; +R1.H = ASHIFT R1.H BY R5.L; +R2.H = ASHIFT R2.H BY R5.L; +R3.H = ASHIFT R3.H BY R5.L; +R4.H = ASHIFT R4.H BY R5.L; +//rh5 = ashift (rh5 by rl5); +R6.H = ASHIFT R6.H BY R5.L; +R7.H = ASHIFT R7.H BY R5.L; +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xc0010000; +CHECKREG r3, 0xc0010000; +CHECKREG r4, 0xc0020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0xc0030000; +CHECKREG r7, 0xc0030000; + + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030000; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = ASHIFT R0.H BY R6.L; +R1.L = ASHIFT R1.H BY R6.L; +R2.L = ASHIFT R2.H BY R6.L; +R3.L = ASHIFT R3.H BY R6.L; +R4.L = ASHIFT R4.H BY R6.L; +R5.L = ASHIFT R5.H BY R6.L; +//rl6 = ashift (rh6 by rl6); +R7.L = ASHIFT R7.H BY R6.L; +CHECKREG r0, 0xd001ffff; +CHECKREG r1, 0xd001ffff; +CHECKREG r2, 0xd002ffff; +CHECKREG r3, 0xd003ffff; +CHECKREG r4, 0xd004ffff; +CHECKREG r5, 0xd005ffff; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0xd007ffff; + +imm32 r0, 0xe0010000; +imm32 r1, 0xe0010000; +imm32 r2, 0xe0020000; +imm32 r3, 0xe0030000; +imm32 r4, 0xe0040000; +imm32 r5, 0xe0050000; +imm32 r6, 0xe0060000; +R7.L = -16; +R0.H = ASHIFT R0.H BY R7.L; +R1.H = ASHIFT R1.H BY R7.L; +R2.H = ASHIFT R2.H BY R7.L; +R3.H = ASHIFT R3.H BY R7.L; +R4.H = ASHIFT R4.H BY R7.L; +R5.H = ASHIFT R5.H BY R7.L; +R6.H = ASHIFT R6.H BY R7.L; +//rh7 = ashift (rh7 by rl7); +CHECKREG r0, 0xffff0000; +CHECKREG r1, 0xffff0000; +CHECKREG r2, 0xffff0000; +CHECKREG r3, 0xffff0000; +CHECKREG r4, 0xffff0000; +CHECKREG r5, 0xffff0000; +CHECKREG r6, 0xffff0000; +//CHECKREG r7, -16; +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_ahalf_rn_s.s b/sim/testsuite/bfin/c_dsp32shift_ahalf_rn_s.s new file mode 100644 index 0000000..503671e --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_ahalf_rn_s.s @@ -0,0 +1,424 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_rn_s/c_dsp32shift_ahalf_rn_s.dsp +// Spec Reference: dsp32shift ashift s +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +//rl0 = ashift (rl0 by rl0); +R1.L = ASHIFT R1.L BY R0.L (S); +R2.L = ASHIFT R2.L BY R0.L (S); +R3.L = ASHIFT R3.L BY R0.L (S); +R4.L = ASHIFT R4.L BY R0.L (S); +R5.L = ASHIFT R5.L BY R0.L (S); +R6.L = ASHIFT R6.L BY R0.L (S); +R7.L = ASHIFT R7.L BY R0.L (S); +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c000; +CHECKREG r2, 0x0000c001; +CHECKREG r3, 0x0000c001; +CHECKREG r4, 0x0000c002; +CHECKREG r5, 0x0000c002; +CHECKREG r6, 0x0000c003; +CHECKREG r7, 0x0000c003; + +imm32 r0, 0x00008001; +R1.L = -1; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R1.L (S); +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L (S); +R3.L = ASHIFT R3.L BY R1.L (S); +R4.L = ASHIFT R4.L BY R1.L (S); +R5.L = ASHIFT R5.L BY R1.L (S); +R6.L = ASHIFT R6.L BY R1.L (S); +R7.L = ASHIFT R7.L BY R1.L (S); +CHECKREG r0, 0x0000c000; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000c001; +CHECKREG r3, 0x0000c001; +CHECKREG r4, 0x0000c002; +CHECKREG r5, 0x0000c002; +CHECKREG r6, 0x0000c003; +CHECKREG r7, 0x0000c003; + + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +R2.L = -15; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R2.L (S); +R1.L = ASHIFT R1.L BY R2.L (S); +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L (S); +R4.L = ASHIFT R4.L BY R2.L (S); +R5.L = ASHIFT R5.L BY R2.L (S); +R6.L = ASHIFT R6.L BY R2.L (S); +R7.L = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0000ffff; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x0000ffff; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +R3.L = -16; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R3.L (S); +R1.L = ASHIFT R1.L BY R3.L (S); +R2.L = ASHIFT R2.L BY R3.L (S); +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L (S); +R5.L = ASHIFT R5.L BY R3.L (S); +R6.L = ASHIFT R6.L BY R3.L (S); +R7.L = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0000ffff; +CHECKREG r2, 0x0000ffff; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = ASHIFT R0.H BY R0.L (S); +R1.L = ASHIFT R1.H BY R0.L (S); +R2.L = ASHIFT R2.H BY R0.L (S); +R3.L = ASHIFT R3.H BY R0.L (S); +R4.L = ASHIFT R4.H BY R0.L (S); +R5.L = ASHIFT R5.H BY R0.L (S); +R6.L = ASHIFT R6.H BY R0.L (S); +R7.L = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x80018001; +CHECKREG r2, 0x80028002; +CHECKREG r3, 0x80038003; +CHECKREG r4, 0x80048004; +CHECKREG r5, 0x80058005; +CHECKREG r6, 0x80068006; +CHECKREG r7, 0x80078007; + +imm32 r0, 0x80010000; +R1.L = -1; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = ASHIFT R0.H BY R1.L (S); +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L (S); +R3.L = ASHIFT R3.H BY R1.L (S); +R4.L = ASHIFT R4.H BY R1.L (S); +R5.L = ASHIFT R5.H BY R1.L (S); +R6.L = ASHIFT R6.H BY R1.L (S); +R7.L = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x8001c000; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x8002c001; +CHECKREG r3, 0x8003c001; +CHECKREG r4, 0x8004c002; +CHECKREG r5, 0x8005c002; +CHECKREG r6, 0x8006c003; +CHECKREG r7, 0x8007c003; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +R2.L = -15; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0xa001ffff; +CHECKREG r1, 0xa001ffff; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0xa003ffff; +CHECKREG r4, 0xa004ffff; +CHECKREG r5, 0xa005ffff; +CHECKREG r6, 0xa006ffff; +CHECKREG r7, 0xa007ffff; + +imm32 r0, 0xb0010001; +imm32 r1, 0xb0010001; +imm32 r2, 0xb0020002; +R3.L = -16; +imm32 r4, 0xb0040004; +imm32 r5, 0xb0050005; +imm32 r6, 0xb0060006; +imm32 r7, 0xb0070007; +R0.L = ASHIFT R0.H BY R3.L (S); +R1.L = ASHIFT R1.H BY R3.L (S); +R2.L = ASHIFT R2.H BY R3.L (S); +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L (S); +R5.L = ASHIFT R5.H BY R3.L (S); +R6.L = ASHIFT R6.H BY R3.L (S); +R7.L = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0xb001ffff; +CHECKREG r1, 0xb001ffff; +CHECKREG r2, 0xb002ffff; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0xb004ffff; +CHECKREG r5, 0xb005ffff; +CHECKREG r6, 0xb006ffff; +CHECKREG r7, 0xb007ffff; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R4.L (S); +R1.H = ASHIFT R1.L BY R4.L (S); +R2.H = ASHIFT R2.L BY R4.L (S); +R3.H = ASHIFT R3.L BY R4.L (S); +//rh4 = ashift (rl4 by rl4); +R5.H = ASHIFT R5.L BY R4.L (S); +R6.H = ASHIFT R6.L BY R4.L (S); +R7.H = ASHIFT R7.L BY R4.L (S); +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +R5.L = -1; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = ASHIFT R0.L BY R5.L (S); +R1.H = ASHIFT R1.L BY R5.L (S); +R2.H = ASHIFT R2.L BY R5.L (S); +R3.H = ASHIFT R3.L BY R5.L (S); +R4.H = ASHIFT R4.L BY R5.L (S); +//rh5 = ashift (rl5 by rl5); +R6.H = ASHIFT R6.L BY R5.L (S); +R7.H = ASHIFT R7.L BY R5.L (S); +CHECKREG r0, 0xc0008001; +CHECKREG r1, 0xc0008001; +CHECKREG r2, 0xc0018002; +CHECKREG r3, 0xc0018003; +CHECKREG r4, 0xc0028004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0xc0038006; +CHECKREG r7, 0xc0038007; + + +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009004; +imm32 r5, 0x00009005; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = ASHIFT R0.L BY R6.L (S); +R1.H = ASHIFT R1.L BY R6.L (S); +R2.H = ASHIFT R2.L BY R6.L (S); +R3.H = ASHIFT R3.L BY R6.L (S); +R4.H = ASHIFT R4.L BY R6.L (S); +R5.H = ASHIFT R5.L BY R6.L (S); +//rh6 = ashift (rl6 by rl6); +R7.H = ASHIFT R7.L BY R6.L; +CHECKREG r0, 0xffff9001; +CHECKREG r1, 0xffff9001; +CHECKREG r2, 0xffff9002; +CHECKREG r3, 0xffff9003; +CHECKREG r4, 0xffff9004; +CHECKREG r5, 0xffff9005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0xffff9007; + +imm32 r0, 0x0000a001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000a002; +imm32 r3, 0x0000a003; +imm32 r4, 0x0000a004; +imm32 r5, 0x0000a005; +imm32 r6, 0x0000a006; +R7.L = -16; +R0.H = ASHIFT R0.L BY R7.L (S); +R1.H = ASHIFT R1.L BY R7.L (S); +R2.H = ASHIFT R2.L BY R7.L (S); +R3.H = ASHIFT R3.L BY R7.L (S); +R4.H = ASHIFT R4.L BY R7.L (S); +R5.H = ASHIFT R5.L BY R7.L (S); +R6.H = ASHIFT R6.L BY R7.L (S); +R7.H = ASHIFT R7.L BY R7.L (S); +CHECKREG r0, 0xffffa001; +CHECKREG r1, 0xffffa001; +CHECKREG r2, 0xffffa002; +CHECKREG r3, 0xffffa003; +CHECKREG r4, 0xffffa004; +CHECKREG r5, 0xffffa005; +CHECKREG r6, 0xffffa006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +R4.L = -1; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = ASHIFT R0.H BY R4.L (S); +R1.H = ASHIFT R1.H BY R4.L (S); +R2.H = ASHIFT R2.H BY R4.L (S); +R3.H = ASHIFT R3.H BY R4.L (S); +//rh4 = ashift (rh4 by rl4); +R5.H = ASHIFT R5.H BY R4.L (S); +R6.H = ASHIFT R6.H BY R4.L (S); +R7.H = ASHIFT R7.H BY R4.L (S); +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xc0010000; +CHECKREG r3, 0xc0010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0xc0020000; +CHECKREG r6, 0xc0030000; +CHECKREG r7, 0xc0030000; + +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +R5.L = -1; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = ASHIFT R0.H BY R5.L (S); +R1.H = ASHIFT R1.H BY R5.L (S); +R2.H = ASHIFT R2.H BY R5.L (S); +R3.H = ASHIFT R3.H BY R5.L (S); +R4.H = ASHIFT R4.H BY R5.L (S); +//rh5 = ashift (rh5 by rl5); +R6.H = ASHIFT R6.H BY R5.L (S); +R7.H = ASHIFT R7.H BY R5.L (S); +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xc0010000; +CHECKREG r3, 0xc0010000; +CHECKREG r4, 0xc0020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0xc0030000; +CHECKREG r7, 0xc0030000; + + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030000; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = ASHIFT R0.H BY R6.L (S); +R1.L = ASHIFT R1.H BY R6.L (S); +R2.L = ASHIFT R2.H BY R6.L (S); +R3.L = ASHIFT R3.H BY R6.L (S); +R4.L = ASHIFT R4.H BY R6.L (S); +R5.L = ASHIFT R5.H BY R6.L (S); +//rl6 = ashift (rh6 by rl6); +R7.L = ASHIFT R7.H BY R6.L; +CHECKREG r0, 0xd001ffff; +CHECKREG r1, 0xd001ffff; +CHECKREG r2, 0xd002ffff; +CHECKREG r3, 0xd003ffff; +CHECKREG r4, 0xd004ffff; +CHECKREG r5, 0xd005ffff; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0xd007ffff; + +imm32 r0, 0xe0010000; +imm32 r1, 0xe0010000; +imm32 r2, 0xe0020000; +imm32 r3, 0xe0030000; +imm32 r4, 0xe0040000; +imm32 r5, 0xe0050000; +imm32 r6, 0xe0060000; +R7.L = -16; +R0.H = ASHIFT R0.H BY R7.L (S); +R1.H = ASHIFT R1.H BY R7.L (S); +R2.H = ASHIFT R2.H BY R7.L (S); +R3.H = ASHIFT R3.H BY R7.L (S); +R4.H = ASHIFT R4.H BY R7.L (S); +R5.H = ASHIFT R5.H BY R7.L (S); +R6.H = ASHIFT R6.H BY R7.L (S); +//rh7 = ashift (rh7 by rl7); +CHECKREG r0, 0xffff0000; +CHECKREG r1, 0xffff0000; +CHECKREG r2, 0xffff0000; +CHECKREG r3, 0xffff0000; +CHECKREG r4, 0xffff0000; +CHECKREG r5, 0xffff0000; +CHECKREG r6, 0xffff0000; +//CHECKREG r7, -16; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_ahalf_rp.s b/sim/testsuite/bfin/c_dsp32shift_ahalf_rp.s new file mode 100644 index 0000000..e3480d5 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_ahalf_rp.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_rp/c_dsp32shift_ahalf_rp.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=right (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +//rl0 = ashift (rl0 by rl0); +R1.L = ASHIFT R1.L BY R0.L; +R2.L = ASHIFT R2.L BY R0.L; +R3.L = ASHIFT R3.L BY R0.L; +R4.L = ASHIFT R4.L BY R0.L; +R5.L = ASHIFT R5.L BY R0.L; +R6.L = ASHIFT R6.L BY R0.L; +R7.L = ASHIFT R7.L BY R0.L; +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x00001001; +R1.L = -1; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R1.L; +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L; +R3.L = ASHIFT R3.L BY R1.L; +R4.L = ASHIFT R4.L BY R1.L; +R5.L = ASHIFT R5.L BY R1.L; +R6.L = ASHIFT R6.L BY R1.L; +R7.L = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0x00000800; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00001001; +CHECKREG r3, 0x00001801; +CHECKREG r4, 0x00002002; +CHECKREG r5, 0x00002802; +CHECKREG r6, 0x00003003; +CHECKREG r7, 0x00003803; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +R2.L = -15; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R2.L; +R1.L = ASHIFT R1.L BY R2.L; +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L; +R4.L = ASHIFT R4.L BY R2.L; +R5.L = ASHIFT R5.L BY R2.L; +R6.L = ASHIFT R6.L BY R2.L; +R7.L = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r2, 0x00002002; +R3.L = -16; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R3.L; +R1.L = ASHIFT R1.L BY R3.L; +R2.L = ASHIFT R2.L BY R3.L; +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L; +R5.L = ASHIFT R5.L BY R3.L; +R6.L = ASHIFT R6.L BY R3.L; +R7.L = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L; +R1.L = ASHIFT R1.H BY R0.L; +R2.L = ASHIFT R2.H BY R0.L; +R3.L = ASHIFT R3.H BY R0.L; +R4.L = ASHIFT R4.H BY R0.L; +R5.L = ASHIFT R5.H BY R0.L; +R6.L = ASHIFT R6.H BY R0.L; +R7.L = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x10010000; +R1.L = -1; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R1.L; +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L; +R3.L = ASHIFT R3.H BY R1.L; +R4.L = ASHIFT R4.H BY R1.L; +R5.L = ASHIFT R5.H BY R1.L; +R6.L = ASHIFT R6.H BY R1.L; +R7.L = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x10010800; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x20021001; +CHECKREG r3, 0x30031801; +CHECKREG r4, 0x40042002; +CHECKREG r5, 0x50052802; +CHECKREG r6, 0x60063003; +CHECKREG r7, 0x70073803; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +R2.L = -15; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010001; +imm32 r1, 0x10010001; +imm32 r2, 0x20020002; +R3.L = -16; +imm32 r4, 0x40040004; +imm32 r5, 0x50050005; +imm32 r6, 0x60060006; +imm32 r7, 0x70070007; +R0.L = ASHIFT R0.H BY R3.L; +R1.L = ASHIFT R1.H BY R3.L; +R2.L = ASHIFT R2.H BY R3.L; +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L; +R5.L = ASHIFT R5.H BY R3.L; +R6.L = ASHIFT R6.H BY R3.L; +R7.L = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R4.L; +R1.H = ASHIFT R1.L BY R4.L; +R2.H = ASHIFT R2.L BY R4.L; +R3.H = ASHIFT R3.L BY R4.L; +//rh4 = ashift (rl4 by rl4); +R5.H = ASHIFT R5.L BY R4.L; +R6.H = ASHIFT R6.L BY R4.L; +R7.H = ASHIFT R7.L BY R4.L; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +R5.L = -1; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R5.L; +R1.H = ASHIFT R1.L BY R5.L; +R2.H = ASHIFT R2.L BY R5.L; +R3.H = ASHIFT R3.L BY R5.L; +R4.H = ASHIFT R4.L BY R5.L; +//rh5 = ashift (rl5 by rl5); +R6.H = ASHIFT R6.L BY R5.L; +R7.H = ASHIFT R7.L BY R5.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00010002; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0x00030006; +CHECKREG r7, 0x00030007; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r1, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +R6.L = -15; +imm32 r7, 0x00007007; +R0.H = ASHIFT R0.L BY R6.L; +R1.H = ASHIFT R1.L BY R6.L; +R2.H = ASHIFT R2.L BY R6.L; +R3.H = ASHIFT R3.L BY R6.L; +R4.H = ASHIFT R4.L BY R6.L; +R5.H = ASHIFT R5.L BY R6.L; +//rh6 = ashift (rl6 by rl6); +R7.H = ASHIFT R7.L BY R6.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00007007; + +imm32 r0, 0x00001001; +imm32 r1, 0x00002001; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +R7.L = -16; +R0.H = ASHIFT R0.L BY R7.L; +R1.H = ASHIFT R1.L BY R7.L; +R2.H = ASHIFT R2.L BY R7.L; +R3.H = ASHIFT R3.L BY R7.L; +R4.H = ASHIFT R4.L BY R7.L; +R5.H = ASHIFT R5.L BY R7.L; +R6.H = ASHIFT R6.L BY R7.L; +R7.H = ASHIFT R7.L BY R7.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002001; +CHECKREG r2, 0x00002002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +CHECKREG r6, 0x00006006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +R4.L = -1; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R4.L; +R1.H = ASHIFT R1.H BY R4.L; +R2.H = ASHIFT R2.H BY R4.L; +R3.H = ASHIFT R3.H BY R4.L; +//rh4 = ashift (rh4 by rl4); +R5.H = ASHIFT R5.H BY R4.L; +R6.H = ASHIFT R6.H BY R4.L; +R7.H = ASHIFT R7.H BY R4.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00010000; +CHECKREG r3, 0x00010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0x00020000; +CHECKREG r6, 0x00030000; +CHECKREG r7, 0x00030000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +R5.L = -1; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.H = ASHIFT R0.H BY R5.L; +R1.H = ASHIFT R1.H BY R5.L; +R2.H = ASHIFT R2.H BY R5.L; +R3.H = ASHIFT R3.H BY R5.L; +R4.H = ASHIFT R4.H BY R5.L; +//rh5 = ashift (rh5 by rl5); +R6.H = ASHIFT R6.H BY R5.L; +R7.H = ASHIFT R7.H BY R5.L; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x08000000; +CHECKREG r2, 0x10010000; +CHECKREG r3, 0x18010000; +CHECKREG r4, 0x20020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0x30030000; +CHECKREG r7, 0x38030000; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +R6.L = -15; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R6.L; +R1.L = ASHIFT R1.H BY R6.L; +R2.L = ASHIFT R2.H BY R6.L; +R3.L = ASHIFT R3.H BY R6.L; +R4.L = ASHIFT R4.H BY R6.L; +R5.L = ASHIFT R5.H BY R6.L; +//rl6 = ashift (rh6 by rl6); +R7.L = ASHIFT R7.H BY R6.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r2, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +R7.L = -16; +R0.H = ASHIFT R0.H BY R7.L; +R1.H = ASHIFT R1.H BY R7.L; +R2.H = ASHIFT R2.H BY R7.L; +R3.H = ASHIFT R3.H BY R7.L; +R4.H = ASHIFT R4.H BY R7.L; +R5.H = ASHIFT R5.H BY R7.L; +R6.H = ASHIFT R6.H BY R7.L; +//rh7 = ashift (rh7 by rl7); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +//CHECKREG r7, -16; +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_ahalf_rp_s.s b/sim/testsuite/bfin/c_dsp32shift_ahalf_rp_s.s new file mode 100644 index 0000000..3e467f2 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_ahalf_rp_s.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_rp_s/c_dsp32shift_ahalf_rp_s.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +//rl0 = ashift (rl0 by rl0); +R1.L = ASHIFT R1.L BY R0.L (S); +R2.L = ASHIFT R2.L BY R0.L (S); +R3.L = ASHIFT R3.L BY R0.L (S); +R4.L = ASHIFT R4.L BY R0.L (S); +R5.L = ASHIFT R5.L BY R0.L (S); +R6.L = ASHIFT R6.L BY R0.L (S); +R7.L = ASHIFT R7.L BY R0.L (S); +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x00001001; +R1.L = -1; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R1.L (S); +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L (S); +R3.L = ASHIFT R3.L BY R1.L (S); +R4.L = ASHIFT R4.L BY R1.L (S); +R5.L = ASHIFT R5.L BY R1.L (S); +R6.L = ASHIFT R6.L BY R1.L (S); +R7.L = ASHIFT R7.L BY R1.L (S); +CHECKREG r0, 0x00000800; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00001001; +CHECKREG r3, 0x00001801; +CHECKREG r4, 0x00002002; +CHECKREG r5, 0x00002802; +CHECKREG r6, 0x00003003; +CHECKREG r7, 0x00003803; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +R2.L = -15; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R2.L (S); +R1.L = ASHIFT R1.L BY R2.L (S); +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L (S); +R4.L = ASHIFT R4.L BY R2.L (S); +R5.L = ASHIFT R5.L BY R2.L (S); +R6.L = ASHIFT R6.L BY R2.L (S); +R7.L = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r2, 0x00002002; +R3.L = -16; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R3.L (S); +R1.L = ASHIFT R1.L BY R3.L (S); +R2.L = ASHIFT R2.L BY R3.L (S); +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L (S); +R5.L = ASHIFT R5.L BY R3.L (S); +R6.L = ASHIFT R6.L BY R3.L (S); +R7.L = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L (S); +R1.L = ASHIFT R1.H BY R0.L (S); +R2.L = ASHIFT R2.H BY R0.L (S); +R3.L = ASHIFT R3.H BY R0.L (S); +R4.L = ASHIFT R4.H BY R0.L (S); +R5.L = ASHIFT R5.H BY R0.L (S); +R6.L = ASHIFT R6.H BY R0.L (S); +R7.L = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x10010000; +R1.L = -1; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R1.L (S); +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L (S); +R3.L = ASHIFT R3.H BY R1.L (S); +R4.L = ASHIFT R4.H BY R1.L (S); +R5.L = ASHIFT R5.H BY R1.L (S); +R6.L = ASHIFT R6.H BY R1.L (S); +R7.L = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x10010800; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x20021001; +CHECKREG r3, 0x30031801; +CHECKREG r4, 0x40042002; +CHECKREG r5, 0x50052802; +CHECKREG r6, 0x60063003; +CHECKREG r7, 0x70073803; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +R2.L = -15; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010001; +imm32 r1, 0x10010001; +imm32 r2, 0x20020002; +R3.L = -16; +imm32 r4, 0x40040004; +imm32 r5, 0x50050005; +imm32 r6, 0x60060006; +imm32 r7, 0x70070007; +R0.L = ASHIFT R0.H BY R3.L (S); +R1.L = ASHIFT R1.H BY R3.L (S); +R2.L = ASHIFT R2.H BY R3.L (S); +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L (S); +R5.L = ASHIFT R5.H BY R3.L (S); +R6.L = ASHIFT R6.H BY R3.L (S); +R7.L = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +// d_hi = ashift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R4.L (S); +R1.H = ASHIFT R1.L BY R4.L (S); +R2.H = ASHIFT R2.L BY R4.L (S); +R3.H = ASHIFT R3.L BY R4.L (S); +//rh4 = ashift (rl4 by rl4); +R5.H = ASHIFT R5.L BY R4.L (S); +R6.H = ASHIFT R6.L BY R4.L (S); +R7.H = ASHIFT R7.L BY R4.L (S); +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +R5.L = -1; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R5.L (S); +R1.H = ASHIFT R1.L BY R5.L (S); +R2.H = ASHIFT R2.L BY R5.L (S); +R3.H = ASHIFT R3.L BY R5.L (S); +R4.H = ASHIFT R4.L BY R5.L (S); +//rh5 = ashift (rl5 by rl5); +R6.H = ASHIFT R6.L BY R5.L (S); +R7.H = ASHIFT R7.L BY R5.L (S); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00010002; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0x00030006; +CHECKREG r7, 0x00030007; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r1, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +R6.L = -15; +imm32 r7, 0x00007007; +R0.H = ASHIFT R0.L BY R6.L (S); +R1.H = ASHIFT R1.L BY R6.L (S); +R2.H = ASHIFT R2.L BY R6.L (S); +R3.H = ASHIFT R3.L BY R6.L (S); +R4.H = ASHIFT R4.L BY R6.L (S); +R5.H = ASHIFT R5.L BY R6.L (S); +//rh6 = ashift (rl6 by rl6); +R7.H = ASHIFT R7.L BY R6.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00007007; + +imm32 r0, 0x00001001; +imm32 r1, 0x00002001; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +R7.L = -16; +R0.H = ASHIFT R0.L BY R7.L (S); +R1.H = ASHIFT R1.L BY R7.L (S); +R2.H = ASHIFT R2.L BY R7.L (S); +R3.H = ASHIFT R3.L BY R7.L (S); +R4.H = ASHIFT R4.L BY R7.L (S); +R5.H = ASHIFT R5.L BY R7.L (S); +R6.H = ASHIFT R6.L BY R7.L (S); +R7.H = ASHIFT R7.L BY R7.L (S); +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002001; +CHECKREG r2, 0x00002002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +CHECKREG r6, 0x00006006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +R4.L = -1; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R4.L (S); +R1.H = ASHIFT R1.H BY R4.L (S); +R2.H = ASHIFT R2.H BY R4.L (S); +R3.H = ASHIFT R3.H BY R4.L (S); +//rh4 = ashift (rh4 by rl4); +R5.H = ASHIFT R5.H BY R4.L (S); +R6.H = ASHIFT R6.H BY R4.L (S); +R7.H = ASHIFT R7.H BY R4.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00010000; +CHECKREG r3, 0x00010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0x00020000; +CHECKREG r6, 0x00030000; +CHECKREG r7, 0x00030000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +R5.L = -1; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.H = ASHIFT R0.H BY R5.L (S); +R1.H = ASHIFT R1.H BY R5.L (S); +R2.H = ASHIFT R2.H BY R5.L (S); +R3.H = ASHIFT R3.H BY R5.L (S); +R4.H = ASHIFT R4.H BY R5.L (S); +//rh5 = ashift (rh5 by rl5); +R6.H = ASHIFT R6.H BY R5.L (S); +R7.H = ASHIFT R7.H BY R5.L (S); +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x08000000; +CHECKREG r2, 0x10010000; +CHECKREG r3, 0x18010000; +CHECKREG r4, 0x20020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0x30030000; +CHECKREG r7, 0x38030000; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +R6.L = -15; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R6.L (S); +R1.L = ASHIFT R1.H BY R6.L (S); +R2.L = ASHIFT R2.H BY R6.L (S); +R3.L = ASHIFT R3.H BY R6.L (S); +R4.L = ASHIFT R4.H BY R6.L (S); +R5.L = ASHIFT R5.H BY R6.L (S); +//rl6 = ashift (rh6 by rl6); +R7.L = ASHIFT R7.H BY R6.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r2, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +R7.L = -16; +R0.H = ASHIFT R0.H BY R7.L (S); +R1.H = ASHIFT R1.H BY R7.L (S); +R2.H = ASHIFT R2.H BY R7.L (S); +R3.H = ASHIFT R3.H BY R7.L (S); +R4.H = ASHIFT R4.H BY R7.L (S); +R5.H = ASHIFT R5.H BY R7.L (S); +R6.H = ASHIFT R6.H BY R7.L (S); +//rh7 = ashift (rh7 by rl7); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +//CHECKREG r7, -16; +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_ahh.s b/sim/testsuite/bfin/c_dsp32shift_ahh.s new file mode 100644 index 0000000..2051cf9 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_ahh.s @@ -0,0 +1,430 @@ +//Original:/testcases/core/c_dsp32shift_ahh/c_dsp32shift_ahh.dsp +// Spec Reference: dsp32shift ashift/ashift +# mach: bfin + +.include "testutils.inc" + start + + + +// ashift/ashift : positive data, count (+)=left (half reg) +// d_reg = ashift/ashift (d BY d_lo) +// Rx by RLx +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5 = ASHIFT R0 BY R0.L (V); +R0 = ASHIFT R1 BY R0.L (V); +R1 = ASHIFT R2 BY R0.L (V); +R2 = ASHIFT R3 BY R0.L (V); +R3 = ASHIFT R4 BY R0.L (V); +R4 = ASHIFT R5 BY R0.L (V); +R7 = ASHIFT R6 BY R0.L (V); +R6 = ASHIFT R7 BY R0.L (V); +CHECKREG r0, 0x12345678; +CHECKREG r1, 0x00230067; +CHECKREG r2, 0x00340078; +CHECKREG r3, 0x0045FF89; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x01230000; +CHECKREG r6, 0x0000FFFF; +CHECKREG r7, 0x0067FFAB; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1.L = 5; +R2 = ASHIFT R0 BY R1.L (V); +R3 = ASHIFT R1 BY R1.L (V); +R4 = ASHIFT R2 BY R1.L (V); +R5 = ASHIFT R3 BY R1.L (V); +R6 = ASHIFT R4 BY R1.L (V); +R7 = ASHIFT R5 BY R1.L (V); +R0 = ASHIFT R6 BY R1.L (V); +R1 = ASHIFT R7 BY R1.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x24600040; +CHECKREG r3, 0x468000A0; +CHECKREG r4, 0x8C000800; +CHECKREG r5, 0xD0001400; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2 = 15; +R3 = ASHIFT R0 BY R2.L (V); +R4 = ASHIFT R1 BY R2.L (V); +R5 = ASHIFT R2 BY R2.L (V); +R6 = ASHIFT R3 BY R2.L (V); +R7 = ASHIFT R4 BY R2.L (V); +R0 = ASHIFT R5 BY R2.L (V); +R1 = ASHIFT R6 BY R2.L (V); +R2 = ASHIFT R7 BY R2.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R3.L = 16; +R4 = ASHIFT R0 BY R3.L (V); +R5 = ASHIFT R1 BY R3.L (V); +R6 = ASHIFT R2 BY R3.L (V); +R7 = ASHIFT R3 BY R3.L (V); +R0 = ASHIFT R4 BY R3.L (V); +R1 = ASHIFT R5 BY R3.L (V); +R2 = ASHIFT R6 BY R3.L (V); +R3 = ASHIFT R7 BY R3.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R4.L = -1; +R0 = ASHIFT R0 BY R4.L (V); +R1 = ASHIFT R1 BY R4.L (V); +R2 = ASHIFT R2 BY R4.L (V); +R3 = ASHIFT R3 BY R4.L (V); +R4 = ASHIFT R4 BY R4.L (V); +R5 = ASHIFT R5 BY R4.L (V); +R6 = ASHIFT R6 BY R4.L (V); +R7 = ASHIFT R7 BY R4.L (V); +CHECKREG r0, 0x00910001; +CHECKREG r1, 0x091A2B3C; +CHECKREG r2, 0x11A233C4; +CHECKREG r3, 0x1A2B3C4D; +CHECKREG r4, 0x22B3FFFF; +CHECKREG r5, 0x2B3CCD5E; +CHECKREG r6, 0x33C4D5E6; +CHECKREG r7, 0x3C4DDE6F; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5.L = -6; +R6 = ASHIFT R0 BY R5.L (V); +R7 = ASHIFT R1 BY R5.L (V); +R0 = ASHIFT R2 BY R5.L (V); +R1 = ASHIFT R3 BY R5.L (V); +R2 = ASHIFT R4 BY R5.L (V); +R3 = ASHIFT R5 BY R5.L (V); +R4 = ASHIFT R6 BY R5.L (V); +R5 = ASHIFT R7 BY R5.L (V); +CHECKREG r0, 0x008D019E; +CHECKREG r1, 0x00D101E2; +CHECKREG r2, 0x0115FE26; +CHECKREG r3, 0x0159FFFF; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00010005; +CHECKREG r6, 0x00040000; +CHECKREG r7, 0x00480159; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R6.L = -15; +R7 = ASHIFT R0 BY R6.L (V); +R0 = ASHIFT R1 BY R6.L (V); +R1 = ASHIFT R2 BY R6.L (V); +R2 = ASHIFT R3 BY R6.L (V); +R3 = ASHIFT R4 BY R6.L (V); +R4 = ASHIFT R5 BY R6.L (V); +R5 = ASHIFT R6 BY R6.L (V); +R6 = ASHIFT R7 BY R6.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x0000FFFF; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7.L = -16; +R0 = ASHIFT R0 BY R7.L (V); +R1 = ASHIFT R1 BY R7.L (V); +R2 = ASHIFT R2 BY R7.L (V); +R3 = ASHIFT R3 BY R7.L (V); +R4 = ASHIFT R4 BY R7.L (V); +R5 = ASHIFT R5 BY R7.L (V); +R6 = ASHIFT R6 BY R7.L (V); +R7 = ASHIFT R7 BY R7.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x0000FFFF; +CHECKREG r7, 0x0000FFFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0.L = 4; +//r0 = ashift/ashift (r0 by rl0); +R1 = ASHIFT R1 BY R0.L (V); +R2 = ASHIFT R2 BY R0.L (V); +R3 = ASHIFT R3 BY R0.L (V); +R4 = ASHIFT R4 BY R0.L (V); +R5 = ASHIFT R5 BY R0.L (V); +R6 = ASHIFT R6 BY R0.L (V); +R7 = ASHIFT R7 BY R0.L (V); +CHECKREG r0, 0x01230004; +CHECKREG r1, 0x23406780; +CHECKREG r2, 0x34507890; +CHECKREG r3, 0x456089A0; +CHECKREG r4, 0x56709AB0; +CHECKREG r5, 0x6780ABC0; +CHECKREG r6, 0x7890BCD0; +CHECKREG r7, 0x89A0CDE0; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1.L = 6; +R0 = ASHIFT R0 BY R1.L (V); +//r1 = ashift/ashift (r1 by rl1); +R2 = ASHIFT R2 BY R1.L (V); +R3 = ASHIFT R3 BY R1.L (V); +R4 = ASHIFT R4 BY R1.L (V); +R5 = ASHIFT R5 BY R1.L (V); +R6 = ASHIFT R6 BY R1.L (V); +R7 = ASHIFT R7 BY R1.L (V); +CHECKREG r0, 0x48C00080; +CHECKREG r1, 0x12340006; +CHECKREG r2, 0xD140E240; +CHECKREG r3, 0x15802680; +CHECKREG r4, 0x59C06AC0; +CHECKREG r5, 0x9E00AF00; +CHECKREG r6, 0xE240F340; +CHECKREG r7, 0x26803780; + + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 15; +R0 = ASHIFT R0 BY R2.L (V); +R1 = ASHIFT R1 BY R2.L (V); +//r2 = ashift/ashift (r2 by rl2); +R3 = ASHIFT R3 BY R2.L (V); +R4 = ASHIFT R4 BY R2.L (V); +R5 = ASHIFT R5 BY R2.L (V); +R6 = ASHIFT R6 BY R2.L (V); +R7 = ASHIFT R7 BY R2.L (V); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x2345000F; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R3.L = 16; +R0 = ASHIFT R0 BY R3.L (V); +R1 = ASHIFT R1 BY R3.L (V); +R2 = ASHIFT R2 BY R3.L (V); +//r3 = ashift/ashift (r3 by rl3); +R4 = ASHIFT R4 BY R3.L (V); +R5 = ASHIFT R5 BY R3.L (V); +R6 = ASHIFT R6 BY R3.L (V); +R7 = ASHIFT R7 BY R3.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x34560010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R4.L = -9; +R0 = ASHIFT R0 BY R4.L (V); +R1 = ASHIFT R1 BY R4.L (V); +R2 = ASHIFT R2 BY R4.L (V); +R3 = ASHIFT R3 BY R4.L (V); +//r4 = ashift/ashift (r4 by rl4); +R5 = ASHIFT R5 BY R4.L (V); +R6 = ASHIFT R6 BY R4.L (V); +R7 = ASHIFT R7 BY R4.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0009002B; +CHECKREG r2, 0x00110033; +CHECKREG r3, 0x001A003C; +CHECKREG r4, 0x4567FFF7; +CHECKREG r5, 0x002BFFCD; +CHECKREG r6, 0x0033FFD5; +CHECKREG r7, 0x003CFFDE; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5.L = -14; +R0 = ASHIFT R0 BY R5.L (V); +R1 = ASHIFT R1 BY R5.L (V); +R2 = ASHIFT R2 BY R5.L (V); +R3 = ASHIFT R3 BY R5.L (V); +R4 = ASHIFT R4 BY R5.L (V); +//r5 = ashift/ashift (r5 by rl5); +R6 = ASHIFT R6 BY R5.L (V); +R7 = ASHIFT R7 BY R5.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x0001FFFE; +CHECKREG r5, 0x5678FFF2; +CHECKREG r6, 0x0001FFFE; +CHECKREG r7, 0x0001FFFE; + + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R6.L = -15; +R0 = ASHIFT R0 BY R6.L (V); +R1 = ASHIFT R1 BY R6.L (V); +R2 = ASHIFT R2 BY R6.L (V); +R3 = ASHIFT R3 BY R6.L (V); +R4 = ASHIFT R4 BY R6.L (V); +R5 = ASHIFT R5 BY R6.L (V); +//r6 = ashift/ashift (r6 by rl6); +R7 = ASHIFT R7 BY R6.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x6789FFF1; +CHECKREG r7, 0x0000FFFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7.L = -16; +R0 = ASHIFT R0 BY R7.L (V); +R1 = ASHIFT R1 BY R7.L (V); +R2 = ASHIFT R2 BY R7.L (V); +R3 = ASHIFT R3 BY R7.L (V); +R4 = ASHIFT R4 BY R7.L (V); +R5 = ASHIFT R5 BY R7.L (V); +R6 = ASHIFT R6 BY R7.L (V); +R7 = ASHIFT R7 BY R7.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_ahh_s.s b/sim/testsuite/bfin/c_dsp32shift_ahh_s.s new file mode 100644 index 0000000..b948e90 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_ahh_s.s @@ -0,0 +1,430 @@ +//Original:/testcases/core/c_dsp32shift_ahh_s/c_dsp32shift_ahh_s.dsp +// Spec Reference: dsp32shift ashift/ashift s +# mach: bfin + +.include "testutils.inc" + start + + + +// ashift/ashift s : positive data, count (+)=left (half reg) +// d_reg = ashift/ashift (d BY d_lo) saturation +// Rx by RLx +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5 = ASHIFT R0 BY R0.L (V , S); +R0 = ASHIFT R1 BY R0.L (V , S); +R1 = ASHIFT R2 BY R0.L (V , S); +R2 = ASHIFT R3 BY R0.L (V , S); +R3 = ASHIFT R4 BY R0.L (V , S); +R4 = ASHIFT R5 BY R0.L (V , S); +R7 = ASHIFT R6 BY R0.L (V , S); +R6 = ASHIFT R7 BY R0.L (V , S); +CHECKREG r0, 0x12345678; +CHECKREG r1, 0x00230067; +CHECKREG r2, 0x00340078; +CHECKREG r3, 0x0045FF89; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x01230000; +CHECKREG r6, 0x0000FFFF; +CHECKREG r7, 0x0067FFAB; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1.L = 5; +R2 = ASHIFT R0 BY R1.L (V , S); +R3 = ASHIFT R1 BY R1.L (V , S); +R4 = ASHIFT R2 BY R1.L (V , S); +R5 = ASHIFT R3 BY R1.L (V , S); +R6 = ASHIFT R4 BY R1.L (V , S); +R7 = ASHIFT R5 BY R1.L (V , S); +R0 = ASHIFT R6 BY R1.L (V , S); +R1 = ASHIFT R7 BY R1.L (V , S); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x24600040; +CHECKREG r3, 0x7FFF00A0; +CHECKREG r4, 0x7FFF0800; +CHECKREG r5, 0x7FFF1400; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2 = 15; +R3 = ASHIFT R0 BY R2.L (V , S); +R4 = ASHIFT R1 BY R2.L (V , S); +R5 = ASHIFT R2 BY R2.L (V , S); +R6 = ASHIFT R3 BY R2.L (V , S); +R7 = ASHIFT R4 BY R2.L (V , S); +R0 = ASHIFT R5 BY R2.L (V , S); +R1 = ASHIFT R6 BY R2.L (V , S); +R2 = ASHIFT R7 BY R2.L (V , S); +CHECKREG r0, 0x00007FFF; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x00007FFF; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R3.L = 16; +R4 = ASHIFT R0 BY R3.L (V , S); +R5 = ASHIFT R1 BY R3.L (V , S); +R6 = ASHIFT R2 BY R3.L (V , S); +R7 = ASHIFT R3 BY R3.L (V , S); +R0 = ASHIFT R4 BY R3.L (V , S); +R1 = ASHIFT R5 BY R3.L (V , S); +R2 = ASHIFT R6 BY R3.L (V , S); +R3 = ASHIFT R7 BY R3.L (V , S); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R4.L = -1; +R0 = ASHIFT R0 BY R4.L (V , S); +R1 = ASHIFT R1 BY R4.L (V , S); +R2 = ASHIFT R2 BY R4.L (V , S); +R3 = ASHIFT R3 BY R4.L (V , S); +R4 = ASHIFT R4 BY R4.L (V , S); +R5 = ASHIFT R5 BY R4.L (V , S); +R6 = ASHIFT R6 BY R4.L (V , S); +R7 = ASHIFT R7 BY R4.L (V , S); +CHECKREG r0, 0x00910001; +CHECKREG r1, 0x091A2B3C; +CHECKREG r2, 0x11A233C4; +CHECKREG r3, 0x1A2B3C4D; +CHECKREG r4, 0x22B3FFFF; +CHECKREG r5, 0x2B3CCD5E; +CHECKREG r6, 0x33C4D5E6; +CHECKREG r7, 0x3C4DDE6F; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5.L = -6; +R6 = ASHIFT R0 BY R5.L (V , S); +R7 = ASHIFT R1 BY R5.L (V , S); +R0 = ASHIFT R2 BY R5.L (V , S); +R1 = ASHIFT R3 BY R5.L (V , S); +R2 = ASHIFT R4 BY R5.L (V , S); +R3 = ASHIFT R5 BY R5.L (V , S); +R4 = ASHIFT R6 BY R5.L (V , S); +R5 = ASHIFT R7 BY R5.L (V , S); +CHECKREG r0, 0x008D019E; +CHECKREG r1, 0x00D101E2; +CHECKREG r2, 0x0115FE26; +CHECKREG r3, 0x0159FFFF; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00010005; +CHECKREG r6, 0x00040000; +CHECKREG r7, 0x00480159; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R6.L = -15; +R7 = ASHIFT R0 BY R6.L (V , S); +R0 = ASHIFT R1 BY R6.L (V , S); +R1 = ASHIFT R2 BY R6.L (V , S); +R2 = ASHIFT R3 BY R6.L (V , S); +R3 = ASHIFT R4 BY R6.L (V , S); +R4 = ASHIFT R5 BY R6.L (V , S); +R5 = ASHIFT R6 BY R6.L (V , S); +R6 = ASHIFT R7 BY R6.L (V , S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x0000FFFF; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7.L = -16; +R0 = ASHIFT R0 BY R7.L (V , S); +R1 = ASHIFT R1 BY R7.L (V , S); +R2 = ASHIFT R2 BY R7.L (V , S); +R3 = ASHIFT R3 BY R7.L (V , S); +R4 = ASHIFT R4 BY R7.L (V , S); +R5 = ASHIFT R5 BY R7.L (V , S); +R6 = ASHIFT R6 BY R7.L (V , S); +R7 = ASHIFT R7 BY R7.L (V , S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x0000FFFF; +CHECKREG r7, 0x0000FFFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0.L = 4; +//r0 = ashift/ashift (r0 by rl0); +R1 = ASHIFT R1 BY R0.L (V , S); +R2 = ASHIFT R2 BY R0.L (V , S); +R3 = ASHIFT R3 BY R0.L (V , S); +R4 = ASHIFT R4 BY R0.L (V , S); +R5 = ASHIFT R5 BY R0.L (V , S); +R6 = ASHIFT R6 BY R0.L (V , S); +R7 = ASHIFT R7 BY R0.L (V , S); +CHECKREG r0, 0x01230004; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF8000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1.L = 6; +R0 = ASHIFT R0 BY R1.L (V , S); +//r1 = ashift/ashift (r1 by rl1); +R2 = ASHIFT R2 BY R1.L (V , S); +R3 = ASHIFT R3 BY R1.L (V , S); +R4 = ASHIFT R4 BY R1.L (V , S); +R5 = ASHIFT R5 BY R1.L (V , S); +R6 = ASHIFT R6 BY R1.L (V , S); +R7 = ASHIFT R7 BY R1.L (V , S); +CHECKREG r0, 0x48C00080; +CHECKREG r1, 0x12340006; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF8000; + + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 15; +R0 = ASHIFT R0 BY R2.L (V , S); +R1 = ASHIFT R1 BY R2.L (V , S); +//r2 = ashift/ashift (r2 by rl2) s; +R3 = ASHIFT R3 BY R2.L (V , S); +R4 = ASHIFT R4 BY R2.L (V , S); +R5 = ASHIFT R5 BY R2.L (V , S); +R6 = ASHIFT R6 BY R2.L (V , S); +R7 = ASHIFT R7 BY R2.L (V , S); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x2345000F; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF8000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R3.L = 16; +R0 = ASHIFT R0 BY R3.L (V , S); +R1 = ASHIFT R1 BY R3.L (V , S); +R2 = ASHIFT R2 BY R3.L (V , S); +//r3 = ashift/ashift (r3 by rl3) s; +R4 = ASHIFT R4 BY R3.L (V , S); +R5 = ASHIFT R5 BY R3.L (V , S); +R6 = ASHIFT R6 BY R3.L (V , S); +R7 = ASHIFT R7 BY R3.L (V , S); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x34560010; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF8000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R4.L = -9; +R0 = ASHIFT R0 BY R4.L (V , S); +R1 = ASHIFT R1 BY R4.L (V , S); +R2 = ASHIFT R2 BY R4.L (V , S); +R3 = ASHIFT R3 BY R4.L (V , S); +//r4 = ashift/ashift (r4 by rl4) s; +R5 = ASHIFT R5 BY R4.L (V , S); +R6 = ASHIFT R6 BY R4.L (V , S); +R7 = ASHIFT R7 BY R4.L (V , S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0009002B; +CHECKREG r2, 0x00110033; +CHECKREG r3, 0x001A003C; +CHECKREG r4, 0x4567FFF7; +CHECKREG r5, 0x002BFFCD; +CHECKREG r6, 0x0033FFD5; +CHECKREG r7, 0x003CFFDE; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5.L = -14; +R0 = ASHIFT R0 BY R5.L (V , S); +R1 = ASHIFT R1 BY R5.L (V , S); +R2 = ASHIFT R2 BY R5.L (V , S); +R3 = ASHIFT R3 BY R5.L (V , S); +R4 = ASHIFT R4 BY R5.L (V , S); +//r5 = ashift/ashift (r5 by rl5) s; +R6 = ASHIFT R6 BY R5.L (V , S); +R7 = ASHIFT R7 BY R5.L (V , S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x0001FFFE; +CHECKREG r5, 0x5678FFF2; +CHECKREG r6, 0x0001FFFE; +CHECKREG r7, 0x0001FFFE; + + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R6.L = -15; +R0 = ASHIFT R0 BY R6.L (V , S); +R1 = ASHIFT R1 BY R6.L (V , S); +R2 = ASHIFT R2 BY R6.L (V , S); +R3 = ASHIFT R3 BY R6.L (V , S); +R4 = ASHIFT R4 BY R6.L (V , S); +R5 = ASHIFT R5 BY R6.L (V , S); +//r6 = ashift/ashift (r6 by rl6) s; +R7 = ASHIFT R7 BY R6.L (V , S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x6789FFF1; +CHECKREG r7, 0x0000FFFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7.L = -16; +R0 = ASHIFT R0 BY R7.L (V , S); +R1 = ASHIFT R1 BY R7.L (V , S); +R2 = ASHIFT R2 BY R7.L (V , S); +R3 = ASHIFT R3 BY R7.L (V , S); +R4 = ASHIFT R4 BY R7.L (V , S); +R5 = ASHIFT R5 BY R7.L (V , S); +R6 = ASHIFT R6 BY R7.L (V , S); +R7 = ASHIFT R7 BY R7.L (V , S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_align16.s b/sim/testsuite/bfin/c_dsp32shift_align16.s new file mode 100644 index 0000000..a6fd284 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_align16.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_align16/c_dsp32shift_align16.dsp +// Spec Reference: dsp32shift align16 +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = ALIGN16 ( R1 , R0 ); +R2 = ALIGN16 ( R2 , R0 ); +R3 = ALIGN16 ( R3 , R0 ); +R4 = ALIGN16 ( R4 , R0 ); +R5 = ALIGN16 ( R5 , R0 ); +R6 = ALIGN16 ( R6 , R0 ); +R7 = ALIGN16 ( R7 , R0 ); +R0 = ALIGN16 ( R0 , R0 ); +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x08010000; +CHECKREG r2, 0x08020000; +CHECKREG r3, 0x08030000; +CHECKREG r4, 0x48040000; +CHECKREG r5, 0x05050000; +CHECKREG r6, 0x08660000; +CHECKREG r7, 0x08070000; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09400002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = ALIGN16 ( R0 , R1 ); +R2 = ALIGN16 ( R2 , R1 ); +R3 = ALIGN16 ( R3 , R1 ); +R4 = ALIGN16 ( R4 , R1 ); +R5 = ALIGN16 ( R5 , R1 ); +R6 = ALIGN16 ( R6 , R1 ); +R7 = ALIGN16 ( R7 , R1 ); +R1 = ALIGN16 ( R1 , R1 ); +CHECKREG r0, 0xD0010900; +CHECKREG r1, 0x00020900; +CHECKREG r2, 0x00020900; +CHECKREG r3, 0x00030900; +CHECKREG r4, 0x00040900; +CHECKREG r5, 0x30050900; +CHECKREG r6, 0x04060900; +CHECKREG r7, 0x00570900; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a400010; +imm32 r4, 0x0a05e004; +imm32 r5, 0x0a006005; +imm32 r6, 0x0a00e706; +imm32 r7, 0x0a00e087; +R0 = ALIGN16 ( R0 , R2 ); +R1 = ALIGN16 ( R1 , R2 ); +R3 = ALIGN16 ( R3 , R2 ); +R4 = ALIGN16 ( R4 , R2 ); +R5 = ALIGN16 ( R5 , R2 ); +R6 = ALIGN16 ( R6 , R2 ); +R7 = ALIGN16 ( R7 , R2 ); +R2 = ALIGN16 ( R2 , R2 ); +CHECKREG r0, 0xE0010A00; +CHECKREG r1, 0xE0010A00; +CHECKREG r2, 0x000F0A00; +CHECKREG r3, 0x00100A00; +CHECKREG r4, 0xE0040A00; +CHECKREG r5, 0x60050A00; +CHECKREG r6, 0xE7060A00; +CHECKREG r7, 0xE0870A00; + +imm32 r0, 0x2b00f001; +imm32 r1, 0x0300f001; +imm32 r2, 0x0b40f002; +imm32 r3, 0x0b050010; +imm32 r4, 0x0b006004; +imm32 r5, 0x0b00f705; +imm32 r6, 0x0b00f086; +imm32 r7, 0x0b00f009; +R0 = ALIGN16 ( R0 , R3 ); +R1 = ALIGN16 ( R1 , R3 ); +R2 = ALIGN16 ( R2 , R3 ); +R4 = ALIGN16 ( R4 , R3 ); +R5 = ALIGN16 ( R5 , R3 ); +R6 = ALIGN16 ( R6 , R3 ); +R7 = ALIGN16 ( R7 , R3 ); +R3 = ALIGN16 ( R3 , R3 ); +CHECKREG r0, 0xF0010B05; +CHECKREG r1, 0xF0010B05; +CHECKREG r2, 0xF0020B05; +CHECKREG r3, 0x00100B05; +CHECKREG r4, 0x60040B05; +CHECKREG r5, 0xF7050B05; +CHECKREG r6, 0xF0860B05; +CHECKREG r7, 0xF0090B05; + +imm32 r0, 0x4c0000c0; +imm32 r1, 0x050100c0; +imm32 r2, 0x0c6200c0; +imm32 r3, 0x0c0700c0; +imm32 r4, 0x0c04800c; +imm32 r5, 0x0c0509c0; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c0700ca; +R0 = ALIGN16 ( R0 , R4 ); +R1 = ALIGN16 ( R1 , R4 ); +R2 = ALIGN16 ( R2 , R4 ); +R3 = ALIGN16 ( R3 , R4 ); +R5 = ALIGN16 ( R5 , R4 ); +R6 = ALIGN16 ( R6 , R4 ); +R7 = ALIGN16 ( R7 , R4 ); +R4 = ALIGN16 ( R4 , R4 ); +CHECKREG r0, 0x00C00C04; +CHECKREG r1, 0x00C00C04; +CHECKREG r2, 0x00C00C04; +CHECKREG r3, 0x00C00C04; +CHECKREG r4, 0x800C0C04; +CHECKREG r5, 0x09C00C04; +CHECKREG r6, 0x00000C04; +CHECKREG r7, 0x00CA0C04; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = ALIGN16 ( R0 , R5 ); +R1 = ALIGN16 ( R1 , R5 ); +R2 = ALIGN16 ( R2 , R5 ); +R3 = ALIGN16 ( R3 , R5 ); +R4 = ALIGN16 ( R4 , R5 ); +R6 = ALIGN16 ( R6 , R5 ); +R7 = ALIGN16 ( R7 , R5 ); +R5 = ALIGN16 ( R5 , R5 ); +CHECKREG r0, 0x00D0A005; +CHECKREG r1, 0x00D1A005; +CHECKREG r2, 0x00D0A005; +CHECKREG r3, 0x00D0A005; +CHECKREG r4, 0x00D0A005; +CHECKREG r5, 0x0007A005; +CHECKREG r6, 0x00D0A005; +CHECKREG r7, 0x00D0A005; + +imm32 r0, 0xb2010000; +imm32 r1, 0xb0310000; +imm32 r2, 0xb042000f; +imm32 r3, 0xbf030000; +imm32 r4, 0xba040000; +imm32 r5, 0xbb050000; +imm32 r6, 0xbc060009; +imm32 r7, 0xb0e70000; +R0 = ALIGN16 ( R0 , R6 ); +R1 = ALIGN16 ( R1 , R6 ); +R2 = ALIGN16 ( R2 , R6 ); +R3 = ALIGN16 ( R3 , R6 ); +R4 = ALIGN16 ( R4 , R6 ); +R5 = ALIGN16 ( R5 , R6 ); +R6 = ALIGN16 ( R6 , R6 ); +R7 = ALIGN16 ( R7 , R6 ); +CHECKREG r0, 0x0000BC06; +CHECKREG r1, 0x0000BC06; +CHECKREG r2, 0x000FBC06; +CHECKREG r3, 0x0000BC06; +CHECKREG r4, 0x0000BC06; +CHECKREG r5, 0x0000BC06; +CHECKREG r6, 0x0009BC06; +CHECKREG r7, 0x00000009; + +imm32 r0, 0xd23100e0; +imm32 r1, 0xd04500e0; +imm32 r2, 0xde32f0e0; +imm32 r3, 0xd90300e0; +imm32 r4, 0xd07400e0; +imm32 r5, 0xdef500e0; +imm32 r6, 0xd06600e0; +imm32 r7, 0xd0080023; +R1 = ALIGN16 ( R0 , R7 ); +R2 = ALIGN16 ( R1 , R7 ); +R3 = ALIGN16 ( R2 , R7 ); +R4 = ALIGN16 ( R3 , R7 ); +R5 = ALIGN16 ( R4 , R7 ); +R6 = ALIGN16 ( R5 , R7 ); +R7 = ALIGN16 ( R6 , R7 ); +R0 = ALIGN16 ( R7 , R7 ); +CHECKREG r0, 0xD008D008; +CHECKREG r1, 0x00E0D008; +CHECKREG r2, 0xD008D008; +CHECKREG r3, 0xD008D008; +CHECKREG r4, 0xD008D008; +CHECKREG r5, 0xD008D008; +CHECKREG r6, 0xD008D008; +CHECKREG r7, 0xD008D008; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_align24.s b/sim/testsuite/bfin/c_dsp32shift_align24.s new file mode 100644 index 0000000..bc33c58 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_align24.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_align24/c_dsp32shift_align24.dsp +// Spec Reference: dsp32shift align24 +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = ALIGN24 ( R1 , R0 ); +R2 = ALIGN24 ( R2 , R0 ); +R3 = ALIGN24 ( R3 , R0 ); +R4 = ALIGN24 ( R4 , R0 ); +R5 = ALIGN24 ( R5 , R0 ); +R6 = ALIGN24 ( R6 , R0 ); +R7 = ALIGN24 ( R7 , R0 ); +R0 = ALIGN24 ( R0 , R0 ); +CHECKREG r0, 0x00000100; +CHECKREG r1, 0x00080100; +CHECKREG r2, 0x20080200; +CHECKREG r3, 0x03080300; +CHECKREG r4, 0x00480400; +CHECKREG r5, 0x00050500; +CHECKREG r6, 0x00086600; +CHECKREG r7, 0x00080700; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09400002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = ALIGN24 ( R0 , R1 ); +R2 = ALIGN24 ( R2 , R1 ); +R3 = ALIGN24 ( R3 , R1 ); +R4 = ALIGN24 ( R4 , R1 ); +R5 = ALIGN24 ( R5 , R1 ); +R6 = ALIGN24 ( R6 , R1 ); +R7 = ALIGN24 ( R7 , R1 ); +R1 = ALIGN24 ( R1 , R1 ); +CHECKREG r0, 0x00D00109; +CHECKREG r1, 0x00000209; +CHECKREG r2, 0x40000209; +CHECKREG r3, 0x10000309; +CHECKREG r4, 0x02000409; +CHECKREG r5, 0x00300509; +CHECKREG r6, 0x00040609; +CHECKREG r7, 0x00005709; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a400010; +imm32 r4, 0x0a05e004; +imm32 r5, 0x0a006005; +imm32 r6, 0x0a00e706; +imm32 r7, 0x0a00e087; +R0 = ALIGN24 ( R0 , R2 ); +R1 = ALIGN24 ( R1 , R2 ); +R3 = ALIGN24 ( R3 , R2 ); +R4 = ALIGN24 ( R4 , R2 ); +R5 = ALIGN24 ( R5 , R2 ); +R6 = ALIGN24 ( R6 , R2 ); +R7 = ALIGN24 ( R7 , R2 ); +R2 = ALIGN24 ( R2 , R2 ); +CHECKREG r0, 0x00E0010A; +CHECKREG r1, 0x00E0010A; +CHECKREG r2, 0x00000F0A; +CHECKREG r3, 0x4000100A; +CHECKREG r4, 0x05E0040A; +CHECKREG r5, 0x0060050A; +CHECKREG r6, 0x00E7060A; +CHECKREG r7, 0x00E0870A; + +imm32 r0, 0x2b00f001; +imm32 r1, 0x0300f001; +imm32 r2, 0x0b40f002; +imm32 r3, 0x0b050010; +imm32 r4, 0x0b006004; +imm32 r5, 0x0b00f705; +imm32 r6, 0x0b00f086; +imm32 r7, 0x0b00f009; +R0 = ALIGN24 ( R0 , R3 ); +R1 = ALIGN24 ( R1 , R3 ); +R2 = ALIGN24 ( R2 , R3 ); +R4 = ALIGN24 ( R4 , R3 ); +R5 = ALIGN24 ( R5 , R3 ); +R6 = ALIGN24 ( R6 , R3 ); +R7 = ALIGN24 ( R7 , R3 ); +R3 = ALIGN24 ( R3 , R3 ); +CHECKREG r0, 0x00F0010B; +CHECKREG r1, 0x00F0010B; +CHECKREG r2, 0x40F0020B; +CHECKREG r3, 0x0500100B; +CHECKREG r4, 0x0060040B; +CHECKREG r5, 0x00F7050B; +CHECKREG r6, 0x00F0860B; +CHECKREG r7, 0x00F0090B; + +imm32 r0, 0x4c0000c0; +imm32 r1, 0x050100c0; +imm32 r2, 0x0c6200c0; +imm32 r3, 0x0c0700c0; +imm32 r4, 0x0c04800c; +imm32 r5, 0x0c0509c0; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c0700ca; +R0 = ALIGN24 ( R0 , R4 ); +R1 = ALIGN24 ( R1 , R4 ); +R2 = ALIGN24 ( R2 , R4 ); +R3 = ALIGN24 ( R3 , R4 ); +R5 = ALIGN24 ( R5 , R4 ); +R6 = ALIGN24 ( R6 , R4 ); +R7 = ALIGN24 ( R7 , R4 ); +R4 = ALIGN24 ( R4 , R4 ); +CHECKREG r0, 0x0000C00C; +CHECKREG r1, 0x0100C00C; +CHECKREG r2, 0x6200C00C; +CHECKREG r3, 0x0700C00C; +CHECKREG r4, 0x04800C0C; +CHECKREG r5, 0x0509C00C; +CHECKREG r6, 0x0600000C; +CHECKREG r7, 0x0700CA0C; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = ALIGN24 ( R0 , R5 ); +R1 = ALIGN24 ( R1 , R5 ); +R2 = ALIGN24 ( R2 , R5 ); +R3 = ALIGN24 ( R3 , R5 ); +R4 = ALIGN24 ( R4 , R5 ); +R6 = ALIGN24 ( R6 , R5 ); +R7 = ALIGN24 ( R7 , R5 ); +R5 = ALIGN24 ( R5 , R5 ); +CHECKREG r0, 0x0100D0A0; +CHECKREG r1, 0x0100D1A0; +CHECKREG r2, 0x0200D0A0; +CHECKREG r3, 0x0300D0A0; +CHECKREG r4, 0x0400D0A0; +CHECKREG r5, 0x050007A0; +CHECKREG r6, 0x0600D0A0; +CHECKREG r7, 0x0700D0A0; + +imm32 r0, 0xb2010000; +imm32 r1, 0xb0310000; +imm32 r2, 0xb042000f; +imm32 r3, 0xbf030000; +imm32 r4, 0xba040000; +imm32 r5, 0xbb050000; +imm32 r6, 0xbc060009; +imm32 r7, 0xb0e70000; +R0 = ALIGN24 ( R0 , R6 ); +R1 = ALIGN24 ( R1 , R6 ); +R2 = ALIGN24 ( R2 , R6 ); +R3 = ALIGN24 ( R3 , R6 ); +R4 = ALIGN24 ( R4 , R6 ); +R5 = ALIGN24 ( R5 , R6 ); +R6 = ALIGN24 ( R6 , R6 ); +R7 = ALIGN24 ( R7 , R6 ); +CHECKREG r0, 0x010000BC; +CHECKREG r1, 0x310000BC; +CHECKREG r2, 0x42000FBC; +CHECKREG r3, 0x030000BC; +CHECKREG r4, 0x040000BC; +CHECKREG r5, 0x050000BC; +CHECKREG r6, 0x060009BC; +CHECKREG r7, 0xE7000006; + +imm32 r0, 0xd23100e0; +imm32 r1, 0xd04500e0; +imm32 r2, 0xde32f0e0; +imm32 r3, 0xd90300e0; +imm32 r4, 0xd07400e0; +imm32 r5, 0xdef500e0; +imm32 r6, 0xd06600e0; +imm32 r7, 0xd0080023; +R1 = ALIGN24 ( R0 , R7 ); +R2 = ALIGN24 ( R1 , R7 ); +R3 = ALIGN24 ( R2 , R7 ); +R4 = ALIGN24 ( R3 , R7 ); +R5 = ALIGN24 ( R4 , R7 ); +R6 = ALIGN24 ( R5 , R7 ); +R7 = ALIGN24 ( R6 , R7 ); +R0 = ALIGN24 ( R7 , R7 ); +CHECKREG r0, 0xD0D0D0D0; +CHECKREG r1, 0x3100E0D0; +CHECKREG r2, 0x00E0D0D0; +CHECKREG r3, 0xE0D0D0D0; +CHECKREG r4, 0xD0D0D0D0; +CHECKREG r5, 0xD0D0D0D0; +CHECKREG r6, 0xD0D0D0D0; +CHECKREG r7, 0xD0D0D0D0; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_align8.s b/sim/testsuite/bfin/c_dsp32shift_align8.s new file mode 100644 index 0000000..ce1f82b --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_align8.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_align8/c_dsp32shift_align8.dsp +// Spec Reference: dsp32shift align8 +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = ALIGN8 ( R1 , R0 ); +R2 = ALIGN8 ( R2 , R0 ); +R3 = ALIGN8 ( R3 , R0 ); +R4 = ALIGN8 ( R4 , R0 ); +R5 = ALIGN8 ( R5 , R0 ); +R6 = ALIGN8 ( R6 , R0 ); +R7 = ALIGN8 ( R7 , R0 ); +R0 = ALIGN8 ( R0 , R0 ); +CHECKREG r0, 0x01000000; +CHECKREG r1, 0x01000000; +CHECKREG r2, 0x02000000; +CHECKREG r3, 0x03000000; +CHECKREG r4, 0x04000000; +CHECKREG r5, 0x05000000; +CHECKREG r6, 0x66000000; +CHECKREG r7, 0x07000000; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09400002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = ALIGN8 ( R0 , R1 ); +R2 = ALIGN8 ( R2 , R1 ); +R3 = ALIGN8 ( R3 , R1 ); +R4 = ALIGN8 ( R4 , R1 ); +R5 = ALIGN8 ( R5 , R1 ); +R6 = ALIGN8 ( R6 , R1 ); +R7 = ALIGN8 ( R7 , R1 ); +R1 = ALIGN8 ( R1 , R1 ); +CHECKREG r0, 0x01090000; +CHECKREG r1, 0x02090000; +CHECKREG r2, 0x02090000; +CHECKREG r3, 0x03090000; +CHECKREG r4, 0x04090000; +CHECKREG r5, 0x05090000; +CHECKREG r6, 0x06090000; +CHECKREG r7, 0x57090000; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a400010; +imm32 r4, 0x0a05e004; +imm32 r5, 0x0a006005; +imm32 r6, 0x0a00e706; +imm32 r7, 0x0a00e087; +R0 = ALIGN8 ( R0 , R2 ); +R1 = ALIGN8 ( R1 , R2 ); +R3 = ALIGN8 ( R3 , R2 ); +R4 = ALIGN8 ( R4 , R2 ); +R5 = ALIGN8 ( R5 , R2 ); +R6 = ALIGN8 ( R6 , R2 ); +R7 = ALIGN8 ( R7 , R2 ); +R2 = ALIGN8 ( R2 , R2 ); +CHECKREG r0, 0x010A0000; +CHECKREG r1, 0x010A0000; +CHECKREG r2, 0x0F0A0000; +CHECKREG r3, 0x100A0000; +CHECKREG r4, 0x040A0000; +CHECKREG r5, 0x050A0000; +CHECKREG r6, 0x060A0000; +CHECKREG r7, 0x870A0000; + +imm32 r0, 0x2b00f001; +imm32 r1, 0x0300f001; +imm32 r2, 0x0b40f002; +imm32 r3, 0x0b050010; +imm32 r4, 0x0b006004; +imm32 r5, 0x0b00f705; +imm32 r6, 0x0b00f086; +imm32 r7, 0x0b00f009; +R0 = ALIGN8 ( R0 , R3 ); +R1 = ALIGN8 ( R1 , R3 ); +R2 = ALIGN8 ( R2 , R3 ); +R4 = ALIGN8 ( R4 , R3 ); +R5 = ALIGN8 ( R5 , R3 ); +R6 = ALIGN8 ( R6 , R3 ); +R7 = ALIGN8 ( R7 , R3 ); +R3 = ALIGN8 ( R3 , R3 ); +CHECKREG r0, 0x010B0500; +CHECKREG r1, 0x010B0500; +CHECKREG r2, 0x020B0500; +CHECKREG r3, 0x100B0500; +CHECKREG r4, 0x040B0500; +CHECKREG r5, 0x050B0500; +CHECKREG r6, 0x860B0500; +CHECKREG r7, 0x090B0500; + +imm32 r0, 0x4c0000c0; +imm32 r1, 0x050100c0; +imm32 r2, 0x0c6200c0; +imm32 r3, 0x0c0700c0; +imm32 r4, 0x0c04800c; +imm32 r5, 0x0c0509c0; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c0700ca; +R0 = ALIGN8 ( R0 , R4 ); +R1 = ALIGN8 ( R1 , R4 ); +R2 = ALIGN8 ( R2 , R4 ); +R3 = ALIGN8 ( R3 , R4 ); +R5 = ALIGN8 ( R5 , R4 ); +R6 = ALIGN8 ( R6 , R4 ); +R7 = ALIGN8 ( R7 , R4 ); +R4 = ALIGN8 ( R4 , R4 ); +CHECKREG r0, 0xC00C0480; +CHECKREG r1, 0xC00C0480; +CHECKREG r2, 0xC00C0480; +CHECKREG r3, 0xC00C0480; +CHECKREG r4, 0x0C0C0480; +CHECKREG r5, 0xC00C0480; +CHECKREG r6, 0x000C0480; +CHECKREG r7, 0xCA0C0480; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = ALIGN8 ( R0 , R5 ); +R1 = ALIGN8 ( R1 , R5 ); +R2 = ALIGN8 ( R2 , R5 ); +R3 = ALIGN8 ( R3 , R5 ); +R4 = ALIGN8 ( R4 , R5 ); +R6 = ALIGN8 ( R6 , R5 ); +R7 = ALIGN8 ( R7 , R5 ); +R5 = ALIGN8 ( R5 , R5 ); +CHECKREG r0, 0xD0A00500; +CHECKREG r1, 0xD1A00500; +CHECKREG r2, 0xD0A00500; +CHECKREG r3, 0xD0A00500; +CHECKREG r4, 0xD0A00500; +CHECKREG r5, 0x07A00500; +CHECKREG r6, 0xD0A00500; +CHECKREG r7, 0xD0A00500; + +imm32 r0, 0xb2010000; +imm32 r1, 0xb0310000; +imm32 r2, 0xb042000f; +imm32 r3, 0xbf030000; +imm32 r4, 0xba040000; +imm32 r5, 0xbb050000; +imm32 r6, 0xbc060009; +imm32 r7, 0xb0e70000; +R0 = ALIGN8 ( R0 , R6 ); +R1 = ALIGN8 ( R1 , R6 ); +R2 = ALIGN8 ( R2 , R6 ); +R3 = ALIGN8 ( R3 , R6 ); +R4 = ALIGN8 ( R4 , R6 ); +R5 = ALIGN8 ( R5 , R6 ); +R6 = ALIGN8 ( R6 , R6 ); +R7 = ALIGN8 ( R7 , R6 ); +CHECKREG r0, 0x00BC0600; +CHECKREG r1, 0x00BC0600; +CHECKREG r2, 0x0FBC0600; +CHECKREG r3, 0x00BC0600; +CHECKREG r4, 0x00BC0600; +CHECKREG r5, 0x00BC0600; +CHECKREG r6, 0x09BC0600; +CHECKREG r7, 0x0009BC06; + +imm32 r0, 0xd23100e0; +imm32 r1, 0xd04500e0; +imm32 r2, 0xde32f0e0; +imm32 r3, 0xd90300e0; +imm32 r4, 0xd07400e0; +imm32 r5, 0xdef500e0; +imm32 r6, 0xd06600e0; +imm32 r7, 0xd0080023; +R1 = ALIGN8 ( R0 , R7 ); +R2 = ALIGN8 ( R1 , R7 ); +R3 = ALIGN8 ( R2 , R7 ); +R4 = ALIGN8 ( R3 , R7 ); +R5 = ALIGN8 ( R4 , R7 ); +R6 = ALIGN8 ( R5 , R7 ); +R7 = ALIGN8 ( R6 , R7 ); +R0 = ALIGN8 ( R7 , R7 ); +CHECKREG r0, 0x0000D008; +CHECKREG r1, 0xE0D00800; +CHECKREG r2, 0x00D00800; +CHECKREG r3, 0x00D00800; +CHECKREG r4, 0x00D00800; +CHECKREG r5, 0x00D00800; +CHECKREG r6, 0x00D00800; +CHECKREG r7, 0x00D00800; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_amix.s b/sim/testsuite/bfin/c_dsp32shift_amix.s new file mode 100644 index 0000000..af59e3f --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_amix.s @@ -0,0 +1,142 @@ +//Original:/testcases/core/c_dsp32shift_amix/c_dsp32shift_amix.dsp +// Spec Reference: dsp32shift ashift mix +# mach: bfin + +.include "testutils.inc" + start + +// Ashift (Arithmetic ) retain the sign bit (0-->0, 1-->1) + +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// Ashift : positive data, count (+)=left (half reg) +imm32 r0, 0x00010001; +imm32 r1, 1; +imm32 r2, 0x00020002; +imm32 r3, 2; +R4.H = ASHIFT R0.H BY R1.L; +R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x00020002 */ +R5.H = ASHIFT R2.H BY R3.L; +R5.L = ASHIFT R2.L BY R3.L; /* r5 = 0x00080008 */ +R6 = ASHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */ +R7 = ASHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */ +CHECKREG r4, 0x00020002; +CHECKREG r5, 0x00080008; +CHECKREG r6, 0x00020002; +CHECKREG r7, 0x00080008; + +// Ashift : (full reg) +imm32 r1, 3; +imm32 r3, 4; +R6 = ASHIFT R0 BY R1.L; /* r6 = 0x00080010 */ +R7 = ASHIFT R2 BY R3.L; +CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ +CHECKREG r7, 0x00200020; + +A0 = 0; +A0.L = R0.L; +A0.H = R0.H; +A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00080008 */ +R5 = A0.w; /* r5 = 0x00080008 */ + +CHECKREG r5, 0x00080008; +imm32 r4, 0x30000003; +imm32 r1, 1; +R5 = ASHIFT R4 BY R1.L; /* r5 = 0x60000006 */ +CHECKREG r5, 0x60000006; +imm32 r1, 2; +R5 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */ +CHECKREG r5, 0xc000000c; + + +// Ashift : count (-)=right (half reg) +imm32 r0, 0x10001000; +imm32 r1, -1; +imm32 r2, 0x10001000; +imm32 r3, -2; +R4.H = ASHIFT R0.H BY R1.L; +R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x08000800 */ +R5.H = ASHIFT R2.H BY R3.L; +R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0x04000400 */ +R6 = ASHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */ +R7 = ASHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */ +CHECKREG r4, 0x08000800; +CHECKREG r5, 0x04000400; +CHECKREG r6, 0x08000800; +CHECKREG r7, 0x04000400; + +// Ashift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = ASHIFT R0 BY R1.L; /* r6 = 0x02000200 */ +R7 = ASHIFT R2 BY R3.L; /* r7 = 0x01000100 */ +CHECKREG r6, 0x02000200; +CHECKREG r7, 0x01000100; + +// NEGATIVE +// Ashift : NEGATIVE data, count (+)=left (half reg) +imm32 r0, 0xc00f800f; +imm32 r1, 1; +imm32 r2, 0xe00fe00f; +imm32 r3, 2; +R4.H = ASHIFT R0.H BY R1.L; +R4.L = ASHIFT R0.L BY R1.L (S); /* r4 = 0x801e801e */ +R5.H = ASHIFT R2.H BY R3.L; +R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0x803c803c */ +CHECKREG r4, 0x801e8000; +CHECKREG r5, 0x803c803c; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +imm32 r1, 4; +imm32 r3, 5; +R6 = ASHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */ +R7 = ASHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xf80fe00f; +imm32 r2, 0xfc0fe00f; +R6 = ASHIFT R0 BY R1.L (S); /* r6 = 0x80fe00f0 */ +R7 = ASHIFT R2 BY R3.L (S); /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +R6 = ASHIFT R0 BY R1.L (S); /* r6 = 0x80000000 zero bubble tru MSB */ +R7 = ASHIFT R2 BY R3.L (S); /* r7 = 0x80000000 */ +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + + +// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok +imm32 r0, 0x80f080f0; +imm32 r1, -1; +imm32 r2, 0x80f080f0; +imm32 r3, -2; +R4.H = ASHIFT R0.H BY R1.L; +R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0xc078c078 */ +R5.H = ASHIFT R2.H BY R3.L; +R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0xe03ce03c */ +CHECKREG r4, 0xc078c078; +CHECKREG r5, 0xe03ce03c; +R6 = ASHIFT R0 BY R1.L (V); /* r6 = 0xc078c078 */ +R7 = ASHIFT R2 BY R3.L (V); /* r7 = 0xe03ce03c */ +CHECKREG r6, 0xc078c078; +CHECKREG r7, 0xe03ce03c; + +// Ashift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = ASHIFT R0 BY R1.L; /* r6 = 0xf01e101e */ +R7 = ASHIFT R2 BY R3.L; /* r7 = 0xf80f080f */ +CHECKREG r6, 0xf01e101e; +CHECKREG r7, 0xf80f080f; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_bitmux.s b/sim/testsuite/bfin/c_dsp32shift_bitmux.s new file mode 100644 index 0000000..d962b27 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_bitmux.s @@ -0,0 +1,486 @@ +//Original:/testcases/core/c_dsp32shift_bitmux/c_dsp32shift_bitmux.dsp +// Spec Reference: dsp32shift bitmux +# mach: bfin + + .include "testutils.inc" + + start + + A0 = 0; + imm32 r0, 0x01230000; + imm32 r1, 0x12340678; + imm32 r2, 0x23450089; + imm32 r3, 0x3456089a; + imm32 r4, 0x456709ab; + imm32 r5, 0x56780abc; + imm32 r6, 0x67890bcd; + imm32 r7, 0x789a0cde; +//r0, r0, a0 >>= bitmux; invalid now + BITMUX( R0 , R1, A0) (ASR); + BITMUX( R0 , R2, A0) (ASR); + BITMUX( R0 , R3, A0) (ASR); + BITMUX( R0 , R4, A0) (ASR); + BITMUX( R0 , R5, A0) (ASR); + BITMUX( R0 , R6, A0) (ASR); + BITMUX( R0 , R7, A0) (ASR); + CHECKREG r1, 0x091A033C; + CHECKREG r0, 0x00024600; + CHECKREG r2, 0x11A28044; + CHECKREG r3, 0x1A2B044D; + CHECKREG r4, 0x22B384D5; + CHECKREG r5, 0x2B3C055E; + CHECKREG r6, 0x33C485E6; + CHECKREG r7, 0x3C4D066F; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x20000000; + CHECKREG r1, 0x00000022; + + imm32 r0, 0x01231001; + imm32 r1, 0x12341678; + imm32 r2, 0x13451789; + imm32 r3, 0x1456189a; + imm32 r4, 0x156711ab; + imm32 r5, 0x16781abc; + imm32 r6, 0x17891bcd; + imm32 r7, 0x189a1cde; + BITMUX( R1 , R0, A0) (ASR); +//r1, r1, a0 >>= bitmux; + BITMUX( R1 , R2, A0) (ASR); + BITMUX( R1 , R3, A0) (ASR); + BITMUX( R1 , R4, A0) (ASR); + BITMUX( R1 , R5, A0) (ASR); + BITMUX( R1 , R6, A0) (ASR); + BITMUX( R1 , R7, A0) (ASR); + CHECKREG r0, 0x00918800; + CHECKREG r1, 0x0024682C; + CHECKREG r2, 0x09A28BC4; + CHECKREG r3, 0x0A2B0C4D; + CHECKREG r4, 0x0AB388D5; + CHECKREG r5, 0x0B3C0D5E; + CHECKREG r6, 0x0BC48DE6; + CHECKREG r7, 0x0C4D0E6F; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x28888000; + CHECKREG r1, 0x00000077; + + imm32 r0, 0x31232002; + imm32 r1, 0x22342678; + imm32 r2, 0x23452789; + imm32 r3, 0x2456289a; + imm32 r4, 0x256729ab; + imm32 r5, 0x26782abc; + imm32 r6, 0x27892bcd; + imm32 r7, 0x289a2cde; + BITMUX( R2 , R0, A0) (ASR); + BITMUX( R2 , R1, A0) (ASR); +//r2, r2, a0 >>= bitmux; + BITMUX( R2 , R3, A0) (ASR); + BITMUX( R2 , R4, A0) (ASR); + BITMUX( R2 , R5, A0) (ASR); + BITMUX( R2 , R6, A0) (ASR); + BITMUX( R2 , R7, A0) (ASR); + CHECKREG r0, 0x18919001; + CHECKREG r1, 0x111A133C; + CHECKREG r2, 0x00468A4F; + CHECKREG r3, 0x122B144D; + CHECKREG r4, 0x12B394D5; + CHECKREG r5, 0x133C155E; + CHECKREG r6, 0x13C495E6; + CHECKREG r7, 0x144D166F; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x05DCA222; + CHECKREG r1, 0x00000023; + + imm32 r0, 0x31230003; + imm32 r1, 0x32345378; + imm32 r2, 0x33456389; + imm32 r3, 0x3456739a; + imm32 r4, 0x356783ab; + imm32 r5, 0x367893bc; + imm32 r6, 0x3789a3cd; + imm32 r7, 0x389ab3de; + BITMUX( R3 , R0, A0) (ASR); + BITMUX( R3 , R1, A0) (ASR); + BITMUX( R3 , R2, A0) (ASR); +//r3, r3, a0 >>= bitmux; + BITMUX( R3 , R4, A0) (ASR); + BITMUX( R3 , R5, A0) (ASR); + BITMUX( R3 , R6, A0) (ASR); + BITMUX( R3 , R7, A0) (ASR); + CHECKREG r0, 0x18918001; + CHECKREG r1, 0x191A29BC; + CHECKREG r2, 0x19A2B1C4; + CHECKREG r3, 0x0068ACE7; + CHECKREG r4, 0x1AB3C1D5; + CHECKREG r5, 0x1B3C49DE; + CHECKREG r6, 0x1BC4D1E6; + CHECKREG r7, 0x1C4D59EF; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x988C1772; + CHECKREG r1, 0x00000027; + + imm32 r0, 0x41230044; + imm32 r1, 0x42345648; + imm32 r2, 0x43456749; + imm32 r3, 0x4456784a; + imm32 r4, 0x4567894b; + imm32 r5, 0x46789a4c; + imm32 r6, 0x4789ab4d; + imm32 r7, 0x489abc44; + BITMUX( R4 , R0, A0) (ASR); + BITMUX( R4 , R1, A0) (ASR); + BITMUX( R4 , R2, A0) (ASR); + BITMUX( R4 , R3, A0) (ASR); +//r4, r4, a0 >>= bitmux; + BITMUX( R4 , R5, A0) (ASR); + BITMUX( R4 , R6, A0) (ASR); + BITMUX( R4 , R7, A0) (ASR); + CHECKREG r0, 0x20918022; + CHECKREG r1, 0x211A2B24; + CHECKREG r2, 0x21A2B3A4; + CHECKREG r3, 0x222B3C25; + CHECKREG r4, 0x008ACF12; + CHECKREG r5, 0x233C4D26; + CHECKREG r6, 0x23C4D5A6; + CHECKREG r7, 0x244D5E22; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x949E6230; + CHECKREG r1, 0x00000061; + + imm32 r0, 0x51235005; + imm32 r1, 0x52345678; + imm32 r2, 0x53455789; + imm32 r3, 0x5456589a; + imm32 r4, 0x556759ab; + imm32 r5, 0x56785abc; + imm32 r6, 0x57895bcd; + imm32 r7, 0x589a5cde; + BITMUX( R5 , R0, A0) (ASR); + BITMUX( R5 , R1, A0) (ASR); + BITMUX( R5 , R2, A0) (ASR); + BITMUX( R5 , R3, A0) (ASR); + BITMUX( R5 , R4, A0) (ASR); +//r5, r5, a0 >>= bitmux; + BITMUX( R5 , R6, A0) (ASR); + BITMUX( R5 , R7, A0) (ASR); + CHECKREG r0, 0x2891A802; + CHECKREG r1, 0x291A2B3C; + CHECKREG r2, 0x29A2ABC4; + CHECKREG r3, 0x2A2B2C4D; + CHECKREG r4, 0x2AB3ACD5; + CHECKREG r5, 0x00ACF0B5; + CHECKREG r6, 0x2BC4ADE6; + CHECKREG r7, 0x2C4D2E6F; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0xC9865279; + CHECKREG r1, 0x0000003D; + + imm32 r0, 0x61260006; + imm32 r1, 0x62365678; + imm32 r2, 0x63466789; + imm32 r3, 0x6456789a; + imm32 r4, 0x656689ab; + imm32 r5, 0x66786abc; + imm32 r6, 0x6786abcd; + imm32 r7, 0x6896bcde; + BITMUX( R6 , R0, A0) (ASR); + BITMUX( R6 , R1, A0) (ASR); + BITMUX( R6 , R2, A0) (ASR); + BITMUX( R6 , R3, A0) (ASR); + BITMUX( R6 , R4, A0) (ASR); + BITMUX( R6 , R5, A0) (ASR); +//r6, r6, a0 >>= bitmux; + BITMUX( R6 , R7, A0) (ASR); + CHECKREG r0, 0x30930003; + CHECKREG r1, 0x311B2B3C; + CHECKREG r2, 0x31A333C4; + CHECKREG r3, 0x322B3C4D; + CHECKREG r4, 0x32B344D5; + CHECKREG r5, 0x333C355E; + CHECKREG r6, 0x00CF0D57; + CHECKREG r7, 0x344B5E6F; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0xC4F72619; + CHECKREG r1, 0x00000049; + + imm32 r0, 0x71730007; + imm32 r1, 0x72745678; + imm32 r2, 0x73756789; + imm32 r3, 0x7476789a; + imm32 r4, 0x757789ab; + imm32 r5, 0x76789abc; + imm32 r6, 0x7779abcd; + imm32 r7, 0x777abcde; + BITMUX( R7 , R0, A0) (ASR); + BITMUX( R7 , R1, A0) (ASR); + BITMUX( R7 , R2, A0) (ASR); + BITMUX( R7 , R3, A0) (ASR); + BITMUX( R7 , R4, A0) (ASR); + BITMUX( R7 , R5, A0) (ASR); + BITMUX( R7 , R6, A0) (ASR); +//r7, r7, a0 >>= bitmux; + CHECKREG r0, 0x38B98003; + CHECKREG r1, 0x393A2B3C; + CHECKREG r2, 0x39BAB3C4; + CHECKREG r3, 0x3A3B3C4D; + CHECKREG r4, 0x3ABBC4D5; + CHECKREG r5, 0x3B3C4D5E; + CHECKREG r6, 0x3BBCD5E6; + CHECKREG r7, 0x00EEF579; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0xD92713DC; + CHECKREG r1, 0xFFFFFFCD; + + imm32 r0, 0x08230080; + imm32 r1, 0x18345688; + imm32 r2, 0x28456789; + imm32 r3, 0x3856788a; + imm32 r4, 0x4867898b; + imm32 r5, 0x58789a8c; + imm32 r6, 0x6889ab8d; + imm32 r7, 0x789abc8e; +//r0, r0, a0 <<= bitmux; + BITMUX( R0 , R1, A0) (ASL); + BITMUX( R0 , R2, A0) (ASL); + BITMUX( R0 , R3, A0) (ASL); + BITMUX( R0 , R4, A0) (ASL); + BITMUX( R0 , R5, A0) (ASL); + BITMUX( R0 , R6, A0) (ASL); + BITMUX( R0 , R7, A0) (ASL); + CHECKREG r1, 0x3068AD10; + CHECKREG r0, 0x11804000; + CHECKREG r2, 0x508ACF12; + CHECKREG r3, 0x70ACF114; + CHECKREG r4, 0x90CF1316; + CHECKREG r5, 0xB0F13518; + CHECKREG r6, 0xD113571A; + CHECKREG r7, 0xF135791C; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0xC4F70010; + CHECKREG r1, 0x00000049; + + imm32 r0, 0x09230009; + imm32 r1, 0x19345679; + imm32 r2, 0x29456789; + imm32 r3, 0x39567899; + imm32 r4, 0x496789a9; + imm32 r5, 0x59789ab9; + imm32 r6, 0x6989abc9; + imm32 r7, 0x799abcd9; + BITMUX( R1 , R0, A0) (ASL); +//r1, r1, a0 <<= bitmux; + BITMUX( R1 , R2, A0) (ASL); + BITMUX( R1 , R3, A0) (ASL); + BITMUX( R1 , R4, A0) (ASL); + BITMUX( R1 , R5, A0) (ASL); + BITMUX( R1 , R6, A0) (ASL); + BITMUX( R1 , R7, A0) (ASL); + CHECKREG r0, 0x12460012; + CHECKREG r1, 0x9A2B3C80; + CHECKREG r2, 0x528ACF12; + CHECKREG r3, 0x72ACF132; + CHECKREG r4, 0x92CF1352; + CHECKREG r5, 0xB2F13572; + CHECKREG r6, 0xD3135792; + CHECKREG r7, 0xF33579B2; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0xC0040050; + CHECKREG r1, 0x0000003D; + + imm32 r0, 0x0a23000a; + imm32 r1, 0x1a34567a; + imm32 r2, 0x2a45678a; + imm32 r3, 0x3a56789a; + imm32 r4, 0x4a6789aa; + imm32 r5, 0x5aa89aba; + imm32 r6, 0x6a89abca; + imm32 r7, 0x7a9abcda; + BITMUX( R2 , R0, A0) (ASL); + BITMUX( R2 , R1, A0) (ASL); +//r2, r2, a0 <<= bitmux; + BITMUX( R2 , R3, A0) (ASL); + BITMUX( R2 , R4, A0) (ASL); + BITMUX( R2 , R5, A0) (ASL); + BITMUX( R2 , R6, A0) (ASL); + BITMUX( R2 , R7, A0) (ASL); + CHECKREG r0, 0x14460014; + CHECKREG r1, 0x3468ACF4; + CHECKREG r2, 0x22B3C500; + CHECKREG r3, 0x74ACF134; + CHECKREG r4, 0x94CF1354; + CHECKREG r5, 0xB5513574; + CHECKREG r6, 0xD5135794; + CHECKREG r7, 0xF53579B4; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x00140111; + CHECKREG r1, 0x00000001; + + imm32 r0, 0x01b300b3; + imm32 r1, 0x12b456b8; + imm32 r2, 0x23b567b9; + imm32 r3, 0x34b678ba; + imm32 r4, 0x45b789bb; + imm32 r5, 0x56b89abc; + imm32 r6, 0x67b9abbd; + imm32 r7, 0x78babcbe; + BITMUX( R3 , R0, A0) (ASL); + BITMUX( R3 , R1, A0) (ASL); + BITMUX( R3 , R2, A0) (ASL); +//r3, r3, a0 <<= bitmux; + BITMUX( R3 , R4, A0) (ASL); + BITMUX( R3 , R5, A0) (ASL); + BITMUX( R3 , R6, A0) (ASL); + BITMUX( R3 , R7, A0) (ASL); + CHECKREG r0, 0x03660166; + CHECKREG r1, 0x2568AD70; + CHECKREG r2, 0x476ACF72; + CHECKREG r3, 0x5B3C5D00; + CHECKREG r4, 0x8B6F1376; + CHECKREG r5, 0xAD713578; + CHECKREG r6, 0xCF73577A; + CHECKREG r7, 0xF175797C; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x00444144; + CHECKREG r1, 0x00000005; + + imm32 r0, 0x012300c4; + imm32 r1, 0x123456c8; + imm32 r2, 0x234567c9; + imm32 r3, 0x345678ca; + imm32 r4, 0x456789cb; + imm32 r5, 0x56789acc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcce; + BITMUX( R4 , R0, A0) (ASL); + BITMUX( R4 , R1, A0) (ASL); + BITMUX( R4 , R2, A0) (ASL); + BITMUX( R4 , R3, A0) (ASL); +//r4, r4, a0 <<= bitmux; + BITMUX( R4 , R5, A0) (ASL); + BITMUX( R4 , R6, A0) (ASL); + BITMUX( R4 , R7, A0) (ASL); + CHECKREG r0, 0x02460188; + CHECKREG r1, 0x2468AD90; + CHECKREG r2, 0x468ACF92; + CHECKREG r3, 0x68ACF194; + CHECKREG r4, 0xB3C4E580; + CHECKREG r5, 0xACF13598; + CHECKREG r6, 0xCF13579A; + CHECKREG r7, 0xF135799C; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x10510404; + CHECKREG r1, 0x00000011; + + imm32 r0, 0x0c230d05; + imm32 r1, 0x1c345d78; + imm32 r2, 0x2c456d89; + imm32 r3, 0x3c567d9a; + imm32 r4, 0x4c678dab; + imm32 r5, 0x5c789dbc; + imm32 r6, 0x6c89adcd; + imm32 r7, 0x7c9abdde; + BITMUX( R5 , R0, A0) (ASL); + BITMUX( R5 , R1, A0) (ASL); + BITMUX( R5 , R2, A0) (ASL); + BITMUX( R5 , R3, A0) (ASL); + BITMUX( R5 , R4, A0) (ASL); +//r5, r5, a0 <<= bitmux; + BITMUX( R5 , R6, A0) (ASL); + BITMUX( R5 , R7, A0) (ASL); + CHECKREG r0, 0x18461A0A; + CHECKREG r1, 0x3868BAF0; + CHECKREG r2, 0x588ADB12; + CHECKREG r3, 0x78ACFB34; + CHECKREG r4, 0x98CF1B56; + CHECKREG r5, 0x3C4EDE00; + CHECKREG r6, 0xD9135B9A; + CHECKREG r7, 0xF9357BBC; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x41010454; + CHECKREG r1, 0x00000014; + + imm32 r0, 0x0d230e06; + imm32 r1, 0x1d345e78; + imm32 r2, 0x2d456e89; + imm32 r3, 0x3d567e9a; + imm32 r4, 0x4d678eab; + imm32 r5, 0x5d789ebc; + imm32 r6, 0x6d89aecd; + imm32 r7, 0x7d9abede; + BITMUX( R6 , R0, A0) (ASL); + BITMUX( R6 , R1, A0) (ASL); + BITMUX( R6 , R2, A0) (ASL); + BITMUX( R6 , R3, A0) (ASL); + BITMUX( R6 , R4, A0) (ASL); + BITMUX( R6 , R5, A0) (ASL); +//r6, r6, a0 <<= bitmux; + BITMUX( R6 , R7, A0) (ASL); + CHECKREG r0, 0x1A461C0C; + CHECKREG r1, 0x3A68BCF0; + CHECKREG r2, 0x5A8ADD12; + CHECKREG r3, 0x7AACFD34; + CHECKREG r4, 0x9ACF1D56; + CHECKREG r5, 0xBAF13D78; + CHECKREG r6, 0xC4D76680; + CHECKREG r7, 0xFB357DBC; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x41150514; + CHECKREG r1, 0x00000040; + + imm32 r0, 0x01230007; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + BITMUX( R7 , R0, A0) (ASL); + BITMUX( R7 , R1, A0) (ASL); + BITMUX( R7 , R2, A0) (ASL); + BITMUX( R7 , R3, A0) (ASL); + BITMUX( R7 , R4, A0) (ASL); + BITMUX( R7 , R5, A0) (ASL); + BITMUX( R7 , R6, A0) (ASL); +//r7, r7, a0 <<= bitmux; + + CHECKREG r0, 0x0246000E; + CHECKREG r1, 0x2468ACF0; + CHECKREG r2, 0x468ACF12; + CHECKREG r3, 0x68ACF134; + CHECKREG r4, 0x8ACF1356; + CHECKREG r5, 0xACF13578; + CHECKREG r6, 0xCF13579A; + CHECKREG r7, 0x4D5E6F00; + + pass diff --git a/sim/testsuite/bfin/c_dsp32shift_bxor.s b/sim/testsuite/bfin/c_dsp32shift_bxor.s new file mode 100644 index 0000000..18b148b --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_bxor.s @@ -0,0 +1,126 @@ +//Original:/testcases/core/c_dsp32shift_bxor/c_dsp32shift_bxor.dsp +// Spec Reference: dsp32shift bxor +# mach: bfin + +.include "testutils.inc" + start + +R0 = 0; +R1 = 58; +A0 = R1; +ASTAT = R0; + + +imm32 r0, 0x12345678; +imm32 r1, 0x22334455; +imm32 r2, 0x66778890; +imm32 r3, 0xaabbccdd; +imm32 r4, 0x34567890; +imm32 r5, 0xa2d3d5f6; +imm32 r6, 0x456bda06; +imm32 r7, 0x56789abc; +R0.L = CC = BXORSHIFT( A0 , R0 ); +R1.L = CC = BXORSHIFT( A0 , R1 ); +R2.L = CC = BXORSHIFT( A0 , R2 ); +R3.L = CC = BXORSHIFT( A0 , R3 ); +R4.L = CC = BXORSHIFT( A0 , R4 ); +R5.L = CC = BXORSHIFT( A0 , R5 ); +R6.L = CC = BXORSHIFT( A0 , R6 ); +R7.L = CC = BXORSHIFT( A0 , R7 ); +CHECKREG r0, 0x12340001; +CHECKREG r1, 0x22330001; +CHECKREG r2, 0x66770000; +CHECKREG r3, 0xAABB0001; +CHECKREG r4, 0x34560000; +CHECKREG r5, 0xA2D30000; +CHECKREG r6, 0x456B0000; +CHECKREG r7, 0x56780001; + +imm32 r0, 0xa1001001; +imm32 r1, 0x1b001001; +imm32 r2, 0x11c01002; +imm32 r3, 0x110d1003; +imm32 r4, 0x1100e004; +imm32 r5, 0x11001f05; +imm32 r6, 0x11001006; +imm32 r7, 0x11001001; +R5.L = CC = BXORSHIFT( A0 , R0 ); +R4.L = CC = BXORSHIFT( A0 , R1 ); +R2.L = CC = BXORSHIFT( A0 , R2 ); +R7.L = CC = BXORSHIFT( A0 , R3 ); +R0.L = CC = BXORSHIFT( A0 , R4 ); +R1.L = CC = BXORSHIFT( A0 , R5 ); +R3.L = CC = BXORSHIFT( A0 , R6 ); +R6.L = CC = BXORSHIFT( A0 , R7 ); +CHECKREG r0, 0xA1000000; +CHECKREG r1, 0x1B000000; +CHECKREG r2, 0x11C00001; +CHECKREG r3, 0x110D0000; +CHECKREG r4, 0x11000000; +CHECKREG r5, 0x11000001; +CHECKREG r6, 0x11000000; +CHECKREG r7, 0x11000001; + +imm32 r0, 0xa2001001; +imm32 r1, 0x1b341001; +imm32 r2, 0x71c01002; +imm32 r3, 0x810d1003; +imm32 r4, 0x1600e004; +imm32 r5, 0x41001405; +imm32 r6, 0x31003006; +imm32 r7, 0x21004671; +R2.L = CC = BXOR( A0 , R0 ); +R3.L = CC = BXOR( A0 , R1 ); +R5.L = CC = BXOR( A0 , R2 ); +R6.L = CC = BXOR( A0 , R3 ); +R0.L = CC = BXOR( A0 , R4 ); +R1.L = CC = BXOR( A0 , R5 ); +R7.L = CC = BXOR( A0 , R6 ); +R4.L = CC = BXOR( A0 , R7 ); +CHECKREG r0, 0xA2000000; +CHECKREG r1, 0x1B340000; +CHECKREG r2, 0x71C00000; +CHECKREG r3, 0x810D0000; +CHECKREG r4, 0x16000000; +CHECKREG r5, 0x41000000; +CHECKREG r6, 0x31000001; +CHECKREG r7, 0x21000000; + +imm32 r0, 0x4a502001; +imm32 r1, 0x6b343001; +imm32 r2, 0x71c04002; +imm32 r3, 0x810d5003; +imm32 r4, 0x5600e004; +imm32 r5, 0x47001405; +imm32 r6, 0x91003006; +imm32 r7, 0xa1004671; +A1 = R3; +R0.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R1.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R2.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R3.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R4.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R5.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R6.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R7.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +CHECKREG r0, 0x4A500001; +CHECKREG r1, 0x6B340000; +CHECKREG r2, 0x71C00000; +CHECKREG r3, 0x810D0000; +CHECKREG r4, 0x56000001; +CHECKREG r5, 0x47000000; +CHECKREG r6, 0x91000001; +CHECKREG r7, 0xA1000001; + + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_expadj_h.s b/sim/testsuite/bfin/c_dsp32shift_expadj_h.s new file mode 100644 index 0000000..30ecd61 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_expadj_h.s @@ -0,0 +1,214 @@ +//Original:/testcases/core/c_dsp32shift_expadj_h/c_dsp32shift_expadj_h.dsp +// Spec Reference: dsp32shift expadj rh +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x80000008; +imm32 r1, 0x80010008; +imm32 r2, 0x80020008; +imm32 r3, 0x80030008; +imm32 r4, 0x80040008; +imm32 r5, 0x80050008; +imm32 r6, 0x80060008; +imm32 r7, 0x80070008; +R1.L = EXPADJ( R1.H , R0.L ); +R2.L = EXPADJ( R2.H , R0.L ); +R3.L = EXPADJ( R3.H , R0.L ); +R4.L = EXPADJ( R4.H , R0.L ); +R5.L = EXPADJ( R5.H , R0.L ); +R6.L = EXPADJ( R6.H , R0.L ); +R7.L = EXPADJ( R7.H , R0.L ); +R0.L = EXPADJ( R0.H , R0.L ); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x80010000; +CHECKREG r2, 0x80020000; +CHECKREG r3, 0x80030000; +CHECKREG r4, 0x80040000; +CHECKREG r5, 0x80050000; +CHECKREG r6, 0x80060000; +CHECKREG r7, 0x80070000; + +imm32 r0, 0x90010009; +imm32 r1, 0x00010009; +imm32 r2, 0x90020009; +imm32 r3, 0x90030009; +imm32 r4, 0x90040009; +imm32 r5, 0x90050009; +imm32 r6, 0x90060009; +imm32 r7, 0x90070009; +R0.L = EXPADJ( R0.H , R1.L ); +R2.L = EXPADJ( R2.H , R1.L ); +R3.L = EXPADJ( R3.H , R1.L ); +R4.L = EXPADJ( R4.H , R1.L ); +R5.L = EXPADJ( R5.H , R1.L ); +R6.L = EXPADJ( R6.H , R1.L ); +R7.L = EXPADJ( R7.H , R1.L ); +R1.L = EXPADJ( R1.H , R1.L ); +CHECKREG r0, 0x90010000; +CHECKREG r1, 0x00010009; +CHECKREG r2, 0x90020000; +CHECKREG r3, 0x90030000; +CHECKREG r4, 0x90040000; +CHECKREG r5, 0x90050000; +CHECKREG r6, 0x90060000; +CHECKREG r7, 0x90070000; + + +imm32 r0, 0xa001000a; +imm32 r1, 0xa001000a; +imm32 r2, 0xa002000a; +imm32 r3, 0xa003000a; +imm32 r4, 0xa004000a; +imm32 r5, 0xa005000a; +imm32 r6, 0xa006000a; +imm32 r7, 0xa007000a; +R0.L = EXPADJ( R0.H , R2.L ); +R1.L = EXPADJ( R1.H , R2.L ); +R3.L = EXPADJ( R3.H , R2.L ); +R4.L = EXPADJ( R4.H , R2.L ); +R5.L = EXPADJ( R5.H , R2.L ); +R6.L = EXPADJ( R6.H , R2.L ); +R7.L = EXPADJ( R7.H , R2.L ); +R2.L = EXPADJ( R2.H , R2.L ); +CHECKREG r0, 0xA0010000; +CHECKREG r1, 0xA0010000; +CHECKREG r2, 0xA0020000; +CHECKREG r3, 0xA0030000; +CHECKREG r4, 0xA0040000; +CHECKREG r5, 0xA0050000; +CHECKREG r6, 0xA0060000; +CHECKREG r7, 0xA0070000; + +imm32 r0, 0xc001000c; +imm32 r1, 0xc001000c; +imm32 r2, 0xc002000c; +imm32 r3, 0xc003001c; +imm32 r4, 0xc004000c; +imm32 r5, 0xc005000c; +imm32 r6, 0xc006000c; +imm32 r7, 0xc007000c; +R0.L = EXPADJ( R0.H , R3.L ); +R1.L = EXPADJ( R1.H , R3.L ); +R2.L = EXPADJ( R2.H , R3.L ); +R4.L = EXPADJ( R4.H , R3.L ); +R5.L = EXPADJ( R5.H , R3.L ); +R6.L = EXPADJ( R6.H , R3.L ); +R7.L = EXPADJ( R7.H , R3.L ); +R3.L = EXPADJ( R3.H , R3.L ); +CHECKREG r0, 0xC0010001; +CHECKREG r1, 0xC0010001; +CHECKREG r2, 0xC0020001; +CHECKREG r3, 0xC0030001; +CHECKREG r4, 0xC0040001; +CHECKREG r5, 0xC0050001; +CHECKREG r6, 0xC0060001; +CHECKREG r7, 0xC0070001; + +imm32 r0, 0xb0000008; +imm32 r1, 0xb0010008; +imm32 r2, 0xb0020008; +imm32 r3, 0xb0030008; +imm32 r4, 0xb0040008; +imm32 r5, 0xb0050008; +imm32 r6, 0xb0060008; +imm32 r7, 0xb0070008; +R0.L = EXPADJ( R1.H , R4.L ); +R1.L = EXPADJ( R2.H , R4.L ); +R2.L = EXPADJ( R3.H , R4.L ); +R3.L = EXPADJ( R4.H , R4.L ); +R5.L = EXPADJ( R5.H , R4.L ); +R6.L = EXPADJ( R6.H , R4.L ); +R7.L = EXPADJ( R7.H , R4.L ); +R4.L = EXPADJ( R0.H , R4.L ); +CHECKREG r0, 0xB0000000; +CHECKREG r1, 0xB0010000; +CHECKREG r2, 0xB0020000; +CHECKREG r3, 0xB0030000; +CHECKREG r4, 0xB0040000; +CHECKREG r5, 0xB0050000; +CHECKREG r6, 0xB0060000; +CHECKREG r7, 0xB0070000; + +imm32 r0, 0xc0010009; +imm32 r1, 0xc0010009; +imm32 r2, 0xc0020009; +imm32 r3, 0xc0030009; +imm32 r4, 0xc0040009; +imm32 r5, 0xc0050009; +imm32 r6, 0xc0060009; +imm32 r7, 0xc0070009; +R0.L = EXPADJ( R0.H , R5.L ); +R1.L = EXPADJ( R2.H , R5.L ); +R2.L = EXPADJ( R3.H , R5.L ); +R3.L = EXPADJ( R4.H , R5.L ); +R4.L = EXPADJ( R5.H , R5.L ); +R6.L = EXPADJ( R6.H , R5.L ); +R7.L = EXPADJ( R7.H , R5.L ); +R5.L = EXPADJ( R1.H , R5.L ); +CHECKREG r0, 0xC0010001; +CHECKREG r1, 0xC0010001; +CHECKREG r2, 0xC0020001; +CHECKREG r3, 0xC0030001; +CHECKREG r4, 0xC0040001; +CHECKREG r5, 0xC0050001; +CHECKREG r6, 0xC0060001; +CHECKREG r7, 0xC0070001; + + +imm32 r0, 0xe001000a; +imm32 r1, 0xe001000a; +imm32 r2, 0xe002000a; +imm32 r3, 0xe003000a; +imm32 r4, 0xe004000a; +imm32 r5, 0xe005000a; +imm32 r6, 0xe006000a; +imm32 r7, 0xe007000a; +R0.L = EXPADJ( R0.H , R6.L ); +R1.L = EXPADJ( R1.H , R6.L ); +R2.L = EXPADJ( R3.H , R6.L ); +R3.L = EXPADJ( R4.H , R6.L ); +R4.L = EXPADJ( R5.H , R6.L ); +R5.L = EXPADJ( R6.H , R6.L ); +R6.L = EXPADJ( R7.H , R6.L ); +R7.L = EXPADJ( R2.H , R6.L ); +CHECKREG r0, 0xE0010002; +CHECKREG r1, 0xE0010002; +CHECKREG r2, 0xE0020002; +CHECKREG r3, 0xE0030002; +CHECKREG r4, 0xE0040002; +CHECKREG r5, 0xE0050002; +CHECKREG r6, 0xE0060002; +CHECKREG r7, 0xE0070002; + +imm32 r0, 0xd001000c; +imm32 r1, 0xd001000c; +imm32 r2, 0xd002000c; +imm32 r3, 0xd003001c; +imm32 r4, 0xd004000c; +imm32 r5, 0xd005000c; +imm32 r6, 0xd006000c; +imm32 r7, 0xd007000c; +R0.L = EXPADJ( R0.H , R7.L ); +R1.L = EXPADJ( R1.H , R7.L ); +R2.L = EXPADJ( R2.H , R7.L ); +R3.L = EXPADJ( R4.H , R7.L ); +R4.L = EXPADJ( R5.H , R7.L ); +R5.L = EXPADJ( R6.H , R7.L ); +R6.L = EXPADJ( R7.H , R7.L ); +R7.L = EXPADJ( R3.H , R7.L ); +CHECKREG r0, 0xD0010001; +CHECKREG r1, 0xD0010001; +CHECKREG r2, 0xD0020001; +CHECKREG r3, 0xD0030001; +CHECKREG r4, 0xD0040001; +CHECKREG r5, 0xD0050001; +CHECKREG r6, 0xD0060001; +CHECKREG r7, 0xD0070001; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_expadj_l.s b/sim/testsuite/bfin/c_dsp32shift_expadj_l.s new file mode 100644 index 0000000..237850b --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_expadj_l.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32shift_expadj_l/c_dsp32shift_expadj_l.dsp +// Spec Reference: dsp32shift expadj rl +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R1.L = EXPADJ( R1.L , R0.L ); +R2.L = EXPADJ( R2.L , R0.L ); +R3.L = EXPADJ( R3.L , R0.L ); +R4.L = EXPADJ( R4.L , R0.L ); +R5.L = EXPADJ( R5.L , R0.L ); +R6.L = EXPADJ( R6.L , R0.L ); +R7.L = EXPADJ( R7.L , R0.L ); +R0.L = EXPADJ( R0.L , R0.L ); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x11001001; +imm32 r1, 0x11001001; +imm32 r2, 0x11001002; +imm32 r3, 0x11001003; +imm32 r4, 0x11001004; +imm32 r5, 0x11001005; +imm32 r6, 0x11001006; +imm32 r7, 0x11001007; +R0.L = EXPADJ( R0.L , R1.L ); +R2.L = EXPADJ( R2.L , R1.L ); +R3.L = EXPADJ( R3.L , R1.L ); +R4.L = EXPADJ( R4.L , R1.L ); +R5.L = EXPADJ( R5.L , R1.L ); +R6.L = EXPADJ( R6.L , R1.L ); +R7.L = EXPADJ( R7.L , R1.L ); +R1.L = EXPADJ( R1.L , R1.L ); +CHECKREG r0, 0x11001001; +CHECKREG r1, 0x11001001; +CHECKREG r2, 0x11001001; +CHECKREG r3, 0x11001001; +CHECKREG r4, 0x11001001; +CHECKREG r5, 0x11001001; +CHECKREG r6, 0x11001001; +CHECKREG r7, 0x11001001; + +imm32 r0, 0x2000c001; +imm32 r1, 0x2000d001; +imm32 r2, 0x2000000f; +imm32 r3, 0x2000e003; +imm32 r4, 0x2000f004; +imm32 r5, 0x2000f005; +imm32 r6, 0x2000f006; +imm32 r7, 0x2000f007; +R0.L = EXPADJ( R0.L , R2.L ); +R1.L = EXPADJ( R1.L , R2.L ); +R3.L = EXPADJ( R3.L , R2.L ); +R4.L = EXPADJ( R4.L , R2.L ); +R5.L = EXPADJ( R5.L , R2.L ); +R6.L = EXPADJ( R6.L , R2.L ); +R7.L = EXPADJ( R7.L , R2.L ); +R2.L = EXPADJ( R2.L , R2.L ); +CHECKREG r0, 0x20000001; +CHECKREG r1, 0x20000001; +CHECKREG r2, 0x2000000B; +CHECKREG r3, 0x20000002; +CHECKREG r4, 0x20000003; +CHECKREG r5, 0x20000003; +CHECKREG r6, 0x20000003; +CHECKREG r7, 0x20000003; + +imm32 r0, 0x30009001; +imm32 r1, 0x3000a001; +imm32 r2, 0x3000b002; +imm32 r3, 0x30000010; +imm32 r4, 0x3000c004; +imm32 r5, 0x3000d005; +imm32 r6, 0x3000e006; +imm32 r7, 0x3000f007; +R0.L = EXPADJ( R0.L , R3.L ); +R1.L = EXPADJ( R1.L , R3.L ); +R2.L = EXPADJ( R2.L , R3.L ); +R4.L = EXPADJ( R4.L , R3.L ); +R5.L = EXPADJ( R5.L , R3.L ); +R6.L = EXPADJ( R6.L , R3.L ); +R7.L = EXPADJ( R7.L , R3.L ); +R3.L = EXPADJ( R3.L , R3.L ); +CHECKREG r0, 0x30000010; +CHECKREG r1, 0x30000010; +CHECKREG r2, 0x30000010; +CHECKREG r3, 0x30000010; +CHECKREG r4, 0x30000010; +CHECKREG r5, 0x30000010; +CHECKREG r6, 0x30000010; +CHECKREG r7, 0x30000010; + +imm32 r0, 0x40000000; +imm32 r1, 0x4000c001; +imm32 r2, 0x4000c002; +imm32 r3, 0x4000c003; +imm32 r4, 0x4000c004; +imm32 r5, 0x4000c005; +imm32 r6, 0x4000c006; +imm32 r7, 0x4000c007; +R0.L = EXPADJ( R1.L , R4.L ); +R1.L = EXPADJ( R2.L , R4.L ); +R2.L = EXPADJ( R3.L , R4.L ); +R3.L = EXPADJ( R4.L , R4.L ); +R5.L = EXPADJ( R5.L , R4.L ); +R6.L = EXPADJ( R6.L , R4.L ); +R7.L = EXPADJ( R7.L , R4.L ); +R4.L = EXPADJ( R0.L , R4.L ); +CHECKREG r0, 0x40000001; +CHECKREG r1, 0x40000001; +CHECKREG r2, 0x40000001; +CHECKREG r3, 0x40000001; +CHECKREG r4, 0x4000C004; +CHECKREG r5, 0x40000001; +CHECKREG r6, 0x40000001; +CHECKREG r7, 0x40000001; + +imm32 r0, 0x51001001; +imm32 r1, 0x51001001; +imm32 r2, 0x51001002; +imm32 r3, 0x51001003; +imm32 r4, 0x51001004; +imm32 r5, 0x51001005; +imm32 r6, 0x51001006; +imm32 r7, 0x51001007; +R0.L = EXPADJ( R0.L , R5.L ); +R1.L = EXPADJ( R2.L , R5.L ); +R2.L = EXPADJ( R3.L , R5.L ); +R3.L = EXPADJ( R4.L , R5.L ); +R4.L = EXPADJ( R5.L , R5.L ); +R6.L = EXPADJ( R6.L , R5.L ); +R7.L = EXPADJ( R7.L , R5.L ); +R5.L = EXPADJ( R1.L , R5.L ); +CHECKREG r0, 0x51000002; +CHECKREG r1, 0x51000002; +CHECKREG r2, 0x51000002; +CHECKREG r3, 0x51000002; +CHECKREG r4, 0x51000002; +CHECKREG r5, 0x51001005; +CHECKREG r6, 0x51000002; +CHECKREG r7, 0x51000002; + +imm32 r0, 0x6000c001; +imm32 r1, 0x6000d001; +imm32 r2, 0x6000000f; +imm32 r3, 0x6000e003; +imm32 r4, 0x6000f004; +imm32 r5, 0x6000f005; +imm32 r6, 0x6000f006; +imm32 r7, 0x6000f007; +R0.L = EXPADJ( R0.L , R6.L ); +R1.L = EXPADJ( R1.L , R6.L ); +R2.L = EXPADJ( R3.L , R6.L ); +R3.L = EXPADJ( R4.L , R6.L ); +R4.L = EXPADJ( R5.L , R6.L ); +R5.L = EXPADJ( R6.L , R6.L ); +R7.L = EXPADJ( R7.L , R6.L ); +R6.L = EXPADJ( R2.L , R6.L ); +CHECKREG r0, 0x60000001; +CHECKREG r1, 0x60000001; +CHECKREG r2, 0x60000002; +CHECKREG r3, 0x60000003; +CHECKREG r4, 0x60000003; +CHECKREG r5, 0x60000003; +CHECKREG r6, 0x6000F006; +CHECKREG r7, 0x60000003; + +imm32 r0, 0x70009001; +imm32 r1, 0x7000a001; +imm32 r2, 0x7000b002; +imm32 r3, 0x70000010; +imm32 r4, 0x7000c004; +imm32 r5, 0x7000d005; +imm32 r6, 0x7000e006; +imm32 r7, 0x7000f007; +R0.L = EXPADJ( R0.L , R7.L ); +R1.L = EXPADJ( R1.L , R7.L ); +R2.L = EXPADJ( R2.L , R7.L ); +R3.L = EXPADJ( R4.L , R7.L ); +R4.L = EXPADJ( R5.L , R7.L ); +R5.L = EXPADJ( R6.L , R7.L ); +R6.L = EXPADJ( R7.L , R7.L ); +R7.L = EXPADJ( R3.L , R7.L ); +CHECKREG r0, 0x70000000; +CHECKREG r1, 0x70000000; +CHECKREG r2, 0x70000000; +CHECKREG r3, 0x70000001; +CHECKREG r4, 0x70000001; +CHECKREG r5, 0x70000002; +CHECKREG r6, 0x70000003; +CHECKREG r7, 0x7000F007; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_expadj_r.s b/sim/testsuite/bfin/c_dsp32shift_expadj_r.s new file mode 100644 index 0000000..c557cbf --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_expadj_r.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32shift_expadj_r/c_dsp32shift_expadj_r.dsp +// Spec Reference: dsp32shift expadj r +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x08000800; +imm32 r1, 0x08000801; +imm32 r2, 0x08000802; +imm32 r3, 0x08000803; +imm32 r4, 0x08000804; +imm32 r5, 0x08000805; +imm32 r6, 0x08000806; +imm32 r7, 0x08000807; +//rl0 = expadj r0 by rl0; +R1.L = EXPADJ( R1 , R0.L ); +R2.L = EXPADJ( R2 , R0.L ); +R3.L = EXPADJ( R3 , R0.L ); +R4.L = EXPADJ( R4 , R0.L ); +R5.L = EXPADJ( R5 , R0.L ); +R6.L = EXPADJ( R6 , R0.L ); +R7.L = EXPADJ( R7 , R0.L ); +CHECKREG r0, 0x08000800; +CHECKREG r1, 0x08000800; +CHECKREG r2, 0x08000800; +CHECKREG r3, 0x08000800; +CHECKREG r4, 0x08000800; +CHECKREG r5, 0x08000800; +CHECKREG r6, 0x08000800; +CHECKREG r7, 0x08000800; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000001; +imm32 r2, 0x0900d002; +imm32 r3, 0x0900d003; +imm32 r4, 0x0900d004; +imm32 r5, 0x0900d005; +imm32 r6, 0x0900d006; +imm32 r7, 0x0900d007; +R0.L = EXPADJ( R0 , R1.L ); +R1.L = EXPADJ( R1 , R1.L ); +R2.L = EXPADJ( R2 , R1.L ); +R3.L = EXPADJ( R3 , R1.L ); +R4.L = EXPADJ( R4 , R1.L ); +R5.L = EXPADJ( R5 , R1.L ); +R6.L = EXPADJ( R6 , R1.L ); +R7.L = EXPADJ( R7 , R1.L ); +CHECKREG r0, 0x09000001; +CHECKREG r1, 0x09000001; +CHECKREG r2, 0x09000001; +CHECKREG r3, 0x09000001; +CHECKREG r4, 0x09000001; +CHECKREG r5, 0x09000001; +CHECKREG r6, 0x09000001; +CHECKREG r7, 0x09000001; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a00e003; +imm32 r4, 0x0a00e004; +imm32 r5, 0x0a00e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0a00e007; +R0.L = EXPADJ( R0 , R2.L ); +R1.L = EXPADJ( R1 , R2.L ); +//rl2 = expadj r2 by rl2; +R3.L = EXPADJ( R3 , R2.L ); +R4.L = EXPADJ( R4 , R2.L ); +R5.L = EXPADJ( R5 , R2.L ); +R6.L = EXPADJ( R6 , R2.L ); +R7.L = EXPADJ( R7 , R2.L ); +CHECKREG r0, 0x0A000003; +CHECKREG r1, 0x0A000003; +CHECKREG r2, 0x0A00000F; +CHECKREG r3, 0x0A000003; +CHECKREG r4, 0x0A000003; +CHECKREG r5, 0x0A000003; +CHECKREG r6, 0x0A000003; +CHECKREG r7, 0x0A000003; + +imm32 r0, 0x0b00f001; +imm32 r1, 0x0b00f001; +imm32 r2, 0x0b00f002; +imm32 r3, 0x0b000010; +imm32 r4, 0x0b00f004; +imm32 r5, 0x0b00f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x0b00f007; +R0.L = EXPADJ( R0 , R3.L ); +R1.L = EXPADJ( R1 , R3.L ); +R2.L = EXPADJ( R2 , R3.L ); +R3.L = EXPADJ( R3 , R3.L ); +R4.L = EXPADJ( R4 , R3.L ); +R5.L = EXPADJ( R5 , R3.L ); +R6.L = EXPADJ( R6 , R3.L ); +R7.L = EXPADJ( R7 , R3.L ); +CHECKREG r0, 0x0B000003; +CHECKREG r1, 0x0B000003; +CHECKREG r2, 0x0B000003; +CHECKREG r3, 0x0B000003; +CHECKREG r4, 0x0B000003; +CHECKREG r5, 0x0B000003; +CHECKREG r6, 0x0B000003; +CHECKREG r7, 0x0B000003; + +imm32 r0, 0x0c0000c0; +imm32 r1, 0x0c0100c0; +imm32 r2, 0x0c0200c0; +imm32 r3, 0x0c0300c0; +imm32 r4, 0x0c0400c0; +imm32 r5, 0x0c0500c0; +imm32 r6, 0x0c0600c0; +imm32 r7, 0x0c0700c0; +R0.L = EXPADJ( R0 , R4.L ); +R1.L = EXPADJ( R1 , R4.L ); +R2.L = EXPADJ( R2 , R4.L ); +R3.L = EXPADJ( R3 , R4.L ); +R4.L = EXPADJ( R4 , R4.L ); +R5.L = EXPADJ( R5 , R4.L ); +R6.L = EXPADJ( R6 , R4.L ); +R7.L = EXPADJ( R7 , R4.L ); +CHECKREG r0, 0x0C0000C0; +CHECKREG r1, 0x0C0100C0; +CHECKREG r2, 0x0C0200C0; +CHECKREG r3, 0x0C0300C0; +CHECKREG r4, 0x0C0400C0; +CHECKREG r5, 0x0C0500C0; +CHECKREG r6, 0x0C0600C0; +CHECKREG r7, 0x0C0700C0; + +imm32 r0, 0xa00100d0; +imm32 r1, 0x000100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa00500d0; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0.L = EXPADJ( R0 , R5.L ); +R1.L = EXPADJ( R1 , R5.L ); +R2.L = EXPADJ( R2 , R5.L ); +R3.L = EXPADJ( R3 , R5.L ); +R4.L = EXPADJ( R4 , R5.L ); +R5.L = EXPADJ( R5 , R5.L ); +R6.L = EXPADJ( R6 , R5.L ); +R7.L = EXPADJ( R7 , R5.L ); +CHECKREG r0, 0xA0010000; +CHECKREG r1, 0x0001000E; +CHECKREG r2, 0xA0020000; +CHECKREG r3, 0xA0030000; +CHECKREG r4, 0xA0040000; +CHECKREG r5, 0xA0050000; +CHECKREG r6, 0xA0060000; +CHECKREG r7, 0xA0070000; + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R0.L = EXPADJ( R0 , R6.L ); +R1.L = EXPADJ( R1 , R6.L ); +R2.L = EXPADJ( R2 , R6.L ); +R3.L = EXPADJ( R3 , R6.L ); +R4.L = EXPADJ( R4 , R6.L ); +R5.L = EXPADJ( R5 , R6.L ); +R6.L = EXPADJ( R6 , R6.L ); +R7.L = EXPADJ( R7 , R6.L ); +CHECKREG r0, 0xB0010000; +CHECKREG r1, 0xB0010000; +CHECKREG r2, 0xB0020000; +CHECKREG r3, 0xB0030000; +CHECKREG r4, 0xB0040000; +CHECKREG r5, 0xB0050000; +CHECKREG r6, 0xB0060000; +CHECKREG r7, 0xB0070000; + +imm32 r0, 0xd00100e0; +imm32 r1, 0xd00100e0; +imm32 r2, 0xd00200e0; +imm32 r3, 0xd00300e0; +imm32 r4, 0xd00400e0; +imm32 r5, 0xd00500e0; +imm32 r6, 0xd00600e0; +imm32 r7, 0xd00700e0; +R0.L = EXPADJ( R0 , R7.L ); +R1.L = EXPADJ( R1 , R7.L ); +R2.L = EXPADJ( R2 , R7.L ); +R3.L = EXPADJ( R3 , R7.L ); +R4.L = EXPADJ( R4 , R7.L ); +R5.L = EXPADJ( R5 , R7.L ); +R6.L = EXPADJ( R6 , R7.L ); +R7.L = EXPADJ( R7 , R7.L ); +CHECKREG r0, 0xD00100E0; +CHECKREG r1, 0xD00100E0; +CHECKREG r2, 0xD00200E0; +CHECKREG r3, 0xD00300E0; +CHECKREG r4, 0xD00400E0; +CHECKREG r5, 0xD00500E0; +CHECKREG r6, 0xD00600E0; +CHECKREG r7, 0xD00700E0; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_expexp_r.s b/sim/testsuite/bfin/c_dsp32shift_expexp_r.s new file mode 100644 index 0000000..4e9186b --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_expexp_r.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32shift_expexp_r/c_dsp32shift_expexp_r.dsp +// Spec Reference: dsp32shift expadj / expadj r +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x0800d001; +imm32 r1, 0x08000001; +imm32 r2, 0x0800d002; +imm32 r3, 0x0800d003; +imm32 r4, 0x0800d004; +imm32 r5, 0x0800d005; +imm32 r6, 0x0800d006; +imm32 r7, 0x0800d007; +R1.L = EXPADJ( R1 , R0.L ) (V); +R2.L = EXPADJ( R2 , R0.L ) (V); +R3.L = EXPADJ( R3 , R0.L ) (V); +R4.L = EXPADJ( R4 , R0.L ) (V); +R5.L = EXPADJ( R5 , R0.L ) (V); +R6.L = EXPADJ( R6 , R0.L ) (V); +R7.L = EXPADJ( R7 , R0.L ) (V); +R0.L = EXPADJ( R0 , R0.L ) (V); +CHECKREG r0, 0x0800D001; +CHECKREG r1, 0x0800D001; +CHECKREG r2, 0x0800D001; +CHECKREG r3, 0x0800D001; +CHECKREG r4, 0x0800D001; +CHECKREG r5, 0x0800D001; +CHECKREG r6, 0x0800D001; +CHECKREG r7, 0x0800D001; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000001; +imm32 r2, 0x0900d002; +imm32 r3, 0x0900d003; +imm32 r4, 0x0900d004; +imm32 r5, 0x0900d005; +imm32 r6, 0x0900d006; +imm32 r7, 0x0900d007; +R0.L = EXPADJ( R0 , R1.L ) (V); +R1.L = EXPADJ( R1 , R1.L ) (V); +R2.L = EXPADJ( R2 , R1.L ) (V); +R3.L = EXPADJ( R3 , R1.L ) (V); +R4.L = EXPADJ( R4 , R1.L ) (V); +R5.L = EXPADJ( R5 , R1.L ) (V); +R6.L = EXPADJ( R6 , R1.L ) (V); +R7.L = EXPADJ( R7 , R1.L ) (V); +CHECKREG r0, 0x09000001; +CHECKREG r1, 0x09000001; +CHECKREG r2, 0x09000001; +CHECKREG r3, 0x09000001; +CHECKREG r4, 0x09000001; +CHECKREG r5, 0x09000001; +CHECKREG r6, 0x09000001; +CHECKREG r7, 0x09000001; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a00e003; +imm32 r4, 0x0a00e004; +imm32 r5, 0x0a00e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0a00e007; +R0.L = EXPADJ( R0 , R2.L ) (V); +R1.L = EXPADJ( R1 , R2.L ) (V); +R3.L = EXPADJ( R3 , R2.L ) (V); +R4.L = EXPADJ( R4 , R2.L ) (V); +R5.L = EXPADJ( R5 , R2.L ) (V); +R6.L = EXPADJ( R6 , R2.L ) (V); +R7.L = EXPADJ( R7 , R2.L ) (V); +R2.L = EXPADJ( R2 , R2.L ) (V); +CHECKREG r0, 0x0A000002; +CHECKREG r1, 0x0A000002; +CHECKREG r2, 0x0A000003; +CHECKREG r3, 0x0A000002; +CHECKREG r4, 0x0A000002; +CHECKREG r5, 0x0A000002; +CHECKREG r6, 0x0A000002; +CHECKREG r7, 0x0A000002; + +imm32 r0, 0x0b00f001; +imm32 r1, 0x0b00f001; +imm32 r2, 0x0b00f002; +imm32 r3, 0x0b000010; +imm32 r4, 0x0b00f004; +imm32 r5, 0x0b00f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x0b00f007; +R0.L = EXPADJ( R0 , R3.L ) (V); +R1.L = EXPADJ( R1 , R3.L ) (V); +R2.L = EXPADJ( R2 , R3.L ) (V); +R3.L = EXPADJ( R3 , R3.L ) (V); +R4.L = EXPADJ( R4 , R3.L ) (V); +R5.L = EXPADJ( R5 , R3.L ) (V); +R6.L = EXPADJ( R6 , R3.L ) (V); +R7.L = EXPADJ( R7 , R3.L ) (V); +CHECKREG r0, 0x0B000010; +CHECKREG r1, 0x0B000010; +CHECKREG r2, 0x0B000010; +CHECKREG r3, 0x0B000010; +CHECKREG r4, 0x0B000010; +CHECKREG r5, 0x0B000010; +CHECKREG r6, 0x0B000010; +CHECKREG r7, 0x0B000010; + +imm32 r0, 0x0c0000c0; +imm32 r1, 0x0c0100c0; +imm32 r2, 0x0c0200c0; +imm32 r3, 0x0c0300c0; +imm32 r4, 0x0c0400c0; +imm32 r5, 0x0c0500c0; +imm32 r6, 0x0c0600c0; +imm32 r7, 0x0c0700c0; +R0.L = EXPADJ( R0 , R4.L ) (V); +R1.L = EXPADJ( R1 , R4.L ) (V); +R2.L = EXPADJ( R2 , R4.L ) (V); +R3.L = EXPADJ( R3 , R4.L ) (V); +R4.L = EXPADJ( R4 , R4.L ) (V); +R5.L = EXPADJ( R5 , R4.L ) (V); +R6.L = EXPADJ( R6 , R4.L ) (V); +R7.L = EXPADJ( R7 , R4.L ) (V); +CHECKREG r0, 0x0C0000C0; +CHECKREG r1, 0x0C0100C0; +CHECKREG r2, 0x0C0200C0; +CHECKREG r3, 0x0C0300C0; +CHECKREG r4, 0x0C0400C0; +CHECKREG r5, 0x0C0500C0; +CHECKREG r6, 0x0C0600C0; +CHECKREG r7, 0x0C0700C0; + +imm32 r0, 0xa00100d0; +imm32 r1, 0x000100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa00500d0; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0.L = EXPADJ( R0 , R5.L ) (V); +R1.L = EXPADJ( R1 , R5.L ) (V); +R2.L = EXPADJ( R2 , R5.L ) (V); +R3.L = EXPADJ( R3 , R5.L ) (V); +R4.L = EXPADJ( R4 , R5.L ) (V); +R5.L = EXPADJ( R5 , R5.L ) (V); +R6.L = EXPADJ( R6 , R5.L ) (V); +R7.L = EXPADJ( R7 , R5.L ) (V); +CHECKREG r0, 0xA00100D0; +CHECKREG r1, 0x000100D0; +CHECKREG r2, 0xA00200D0; +CHECKREG r3, 0xA00300D0; +CHECKREG r4, 0xA00400D0; +CHECKREG r5, 0xA00500D0; +CHECKREG r6, 0xA00600D0; +CHECKREG r7, 0xA00700D0; + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R0.L = EXPADJ( R0 , R6.L ) (V); +R1.L = EXPADJ( R1 , R6.L ) (V); +R2.L = EXPADJ( R2 , R6.L ) (V); +R3.L = EXPADJ( R3 , R6.L ) (V); +R4.L = EXPADJ( R4 , R6.L ) (V); +R5.L = EXPADJ( R5 , R6.L ) (V); +R6.L = EXPADJ( R6 , R6.L ) (V); +R7.L = EXPADJ( R7 , R6.L ) (V); +CHECKREG r0, 0xB0010000; +CHECKREG r1, 0xB0010000; +CHECKREG r2, 0xB0020000; +CHECKREG r3, 0xB0030000; +CHECKREG r4, 0xB0040000; +CHECKREG r5, 0xB0050000; +CHECKREG r6, 0xB0060000; +CHECKREG r7, 0xB0070000; + +imm32 r0, 0xd00102e7; +imm32 r1, 0xd00104e7; +imm32 r2, 0xd00206e7; +imm32 r3, 0xd00308e7; +imm32 r4, 0xd0040ae7; +imm32 r5, 0xd0050ce7; +imm32 r6, 0xd0060ee7; +imm32 r7, 0xd00707e7; +R0.L = EXPADJ( R0 , R7.L ) (V); +R1.L = EXPADJ( R1 , R7.L ) (V); +R2.L = EXPADJ( R2 , R7.L ) (V); +R3.L = EXPADJ( R3 , R7.L ) (V); +R4.L = EXPADJ( R4 , R7.L ) (V); +R5.L = EXPADJ( R5 , R7.L ) (V); +R6.L = EXPADJ( R6 , R7.L ) (V); +R7.L = EXPADJ( R7 , R7.L ) (V); +CHECKREG r0, 0xD0010001; +CHECKREG r1, 0xD0010001; +CHECKREG r2, 0xD0020001; +CHECKREG r3, 0xD0030001; +CHECKREG r4, 0xD0040001; +CHECKREG r5, 0xD0050001; +CHECKREG r6, 0xD0060001; +CHECKREG r7, 0xD0070001; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_fdepx.s b/sim/testsuite/bfin/c_dsp32shift_fdepx.s new file mode 100644 index 0000000..5e843fe --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_fdepx.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_fdepx/c_dsp32shift_fdepx.dsp +// Spec Reference: dsp32shift fdep x +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = DEPOSIT( R1, R0 ); +R2 = DEPOSIT( R2, R0 ); +R3 = DEPOSIT( R3, R0 ); +R4 = DEPOSIT( R4, R0 ) (X); +R5 = DEPOSIT( R5, R0 ); +R6 = DEPOSIT( R6, R0 ); +R7 = DEPOSIT( R7, R0 ) (X); +R0 = DEPOSIT( R0, R0 ); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x01000800; +CHECKREG r2, 0x08200802; +CHECKREG r3, 0x08030802; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x08000504; +CHECKREG r6, 0x08000866; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09000002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = DEPOSIT( R0, R1 ); +R2 = DEPOSIT( R2, R1 ); +R3 = DEPOSIT( R3, R1 ); +R4 = DEPOSIT( R4, R1 ); +R5 = DEPOSIT( R5, R1 ) (X); +R6 = DEPOSIT( R6, R1 ); +R7 = DEPOSIT( R7, R1 ) (X); +R1 = DEPOSIT( R1, R1 ); +CHECKREG r0, 0x0900D000; +CHECKREG r1, 0x09000000; +CHECKREG r2, 0x09000000; +CHECKREG r3, 0x09100000; +CHECKREG r4, 0x09020004; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x09000404; +CHECKREG r7, 0x00000000; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a000010; +imm32 r4, 0x0a00e004; +imm32 r5, 0x0a00e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0a00e007; +R0 = DEPOSIT( R0, R2 ); +R1 = DEPOSIT( R1, R2 ); +R3 = DEPOSIT( R3, R2 ); +R4 = DEPOSIT( R4, R2 ); +R5 = DEPOSIT( R5, R2 ); +R6 = DEPOSIT( R6, R2 ); +R7 = DEPOSIT( R7, R2 ); +R2 = DEPOSIT( R2, R2 ); +CHECKREG r0, 0x0A008A00; +CHECKREG r1, 0x0A008A00; +CHECKREG r2, 0x0A000A00; +CHECKREG r3, 0x0A000A00; +CHECKREG r4, 0x0A008A00; +CHECKREG r5, 0x0A008A00; +CHECKREG r6, 0x0A008A00; +CHECKREG r7, 0x0A008A00; + +imm32 r0, 0x4b00f001; +imm32 r1, 0x5b00f001; +imm32 r2, 0x6b00f002; +imm32 r3, 0x9f000010; +imm32 r4, 0x8b00f004; +imm32 r5, 0x0900f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x0b0af007; +R0 = DEPOSIT( R0, R3 ); +R1 = DEPOSIT( R1, R3 ); +R2 = DEPOSIT( R2, R3 ) (X); +R4 = DEPOSIT( R4, R3 ); +R5 = DEPOSIT( R5, R3 ); +R6 = DEPOSIT( R6, R3 ) (X); +R7 = DEPOSIT( R7, R3 ); +R3 = DEPOSIT( R3, R3 ); +CHECKREG r0, 0x4B009F00; +CHECKREG r1, 0x5B009F00; +CHECKREG r2, 0xFFFF9F00; +CHECKREG r3, 0x9F009F00; +CHECKREG r4, 0x8B009F00; +CHECKREG r5, 0x09009F00; +CHECKREG r6, 0xFFFF9F00; +CHECKREG r7, 0x0B0A9F00; + +imm32 r0, 0x0c0000c0; +imm32 r1, 0x0c0100c0; +imm32 r2, 0x0c0200c0; +imm32 r3, 0x0c0300c0; +imm32 r4, 0x0c04000c; +imm32 r5, 0x0c0500c0; +imm32 r6, 0x0c0600c0; +imm32 r7, 0x0c0700c0; +R0 = DEPOSIT( R0, R4 ); +R1 = DEPOSIT( R1, R4 ); +R2 = DEPOSIT( R2, R4 ); +R3 = DEPOSIT( R3, R4 ); +R5 = DEPOSIT( R5, R4 ) (X); +R6 = DEPOSIT( R6, R4 ); +R7 = DEPOSIT( R7, R4 ); +R4 = DEPOSIT( R4, R4 ); +CHECKREG r0, 0x0C000C04; +CHECKREG r1, 0x0C010C04; +CHECKREG r2, 0x0C020C04; +CHECKREG r3, 0x0C030C04; +CHECKREG r4, 0x0C040C04; +CHECKREG r5, 0xFFFFFC04; +CHECKREG r6, 0x0C060C04; +CHECKREG r7, 0x0C070C04; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R5 = DEPOSIT( R0, R5 ); +R6 = DEPOSIT( R1, R5 ) (X); +R7 = DEPOSIT( R2, R5 ); +R0 = DEPOSIT( R3, R5 ); +R1 = DEPOSIT( R4, R5 ) (X); +R2 = DEPOSIT( R6, R5 ); +R3 = DEPOSIT( R7, R5 ); +R4 = DEPOSIT( R5, R5 ); +CHECKREG r0, 0xA00300C1; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0xA00200C1; +CHECKREG r4, 0xA0010081; +CHECKREG r5, 0xA0010085; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0xA00200C1; + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0x00237809; +imm32 r7, 0xb0070000; +R0 = DEPOSIT( R0, R6 ); +R1 = DEPOSIT( R1, R6 ); +R2 = DEPOSIT( R2, R6 ); +R3 = DEPOSIT( R3, R6 ) (X); +R4 = DEPOSIT( R4, R6 ); +R5 = DEPOSIT( R5, R6 ); +R6 = DEPOSIT( R6, R6 ); +R7 = DEPOSIT( R7, R6 ); +CHECKREG r0, 0x23010000; +CHECKREG r1, 0x23010000; +CHECKREG r2, 0x2302000F; +CHECKREG r3, 0x23030000; +CHECKREG r4, 0x23040000; +CHECKREG r5, 0x23050000; +CHECKREG r6, 0x23237809; +CHECKREG r7, 0x23070000; + +imm32 r0, 0xd00100e0; +imm32 r1, 0xd00100e0; +imm32 r2, 0xd00200e0; +imm32 r3, 0xd00300e0; +imm32 r4, 0xd00400e0; +imm32 r5, 0xd00500e0; +imm32 r6, 0xd00600e0; +imm32 r7, 0x00012345; +R1 = DEPOSIT( R0, R7 ); +R2 = DEPOSIT( R1, R7 ); +R3 = DEPOSIT( R2, R7 ); +R4 = DEPOSIT( R3, R7 ); +R5 = DEPOSIT( R4, R7 ) (X); +R6 = DEPOSIT( R5, R7 ); +R7 = DEPOSIT( R6, R7 ) (X); +R0 = DEPOSIT( R7, R7 ); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xD0010008; +CHECKREG r2, 0xD0010008; +CHECKREG r3, 0xD0010008; +CHECKREG r4, 0xD0010008; +CHECKREG r5, 0x00000008; +CHECKREG r6, 0x00000008; +CHECKREG r7, 0x00000008; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_fextx.s b/sim/testsuite/bfin/c_dsp32shift_fextx.s new file mode 100644 index 0000000..13ba90c --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_fextx.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_fextx/c_dsp32shift_fextx.dsp +// Spec Reference: dsp32shift fext x +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = EXTRACT( R1, R0.L ) (Z); +R2 = EXTRACT( R2, R0.L ) (Z); +R3 = EXTRACT( R3, R0.L ) (Z); +R4 = EXTRACT( R4, R0.L ) (X); +R5 = EXTRACT( R5, R0.L ) (Z); +R6 = EXTRACT( R6, R0.L ) (Z); +R7 = EXTRACT( R7, R0.L ) (X); +R0 = EXTRACT( R0, R0.L ) (Z); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09000002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = EXTRACT( R0, R1.L ) (Z); +R2 = EXTRACT( R2, R1.L ) (Z); +R3 = EXTRACT( R3, R1.L ) (Z); +R4 = EXTRACT( R4, R1.L ) (Z); +R5 = EXTRACT( R5, R1.L ) (X); +R6 = EXTRACT( R6, R1.L ) (Z); +R7 = EXTRACT( R7, R1.L ) (X); +R1 = EXTRACT( R1, R1.L ) (Z); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0xFFFFFFFF; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a000010; +imm32 r4, 0x0a00e004; +imm32 r5, 0x0a00e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0a00e007; +R0 = EXTRACT( R0, R2.L ) (Z); +R1 = EXTRACT( R1, R2.L ) (Z); +R3 = EXTRACT( R3, R2.L ) (Z); +R4 = EXTRACT( R4, R2.L ) (Z); +R5 = EXTRACT( R5, R2.L ) (Z); +R6 = EXTRACT( R6, R2.L ) (Z); +R7 = EXTRACT( R7, R2.L ) (Z); +R2 = EXTRACT( R2, R2.L ) (Z); +CHECKREG r0, 0x00006001; +CHECKREG r1, 0x00006001; +CHECKREG r2, 0x0000000F; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00006004; +CHECKREG r5, 0x00006005; +CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00006007; + +imm32 r0, 0x0b00f001; +imm32 r1, 0x0b00f001; +imm32 r2, 0x0b00f002; +imm32 r3, 0x0b000010; +imm32 r4, 0x0b00f004; +imm32 r5, 0x0b00f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x0b00f007; +R0 = EXTRACT( R0, R3.L ) (Z); +R1 = EXTRACT( R1, R3.L ) (Z); +R2 = EXTRACT( R2, R3.L ) (X); +R4 = EXTRACT( R4, R3.L ) (Z); +R5 = EXTRACT( R5, R3.L ) (Z); +R6 = EXTRACT( R6, R3.L ) (X); +R7 = EXTRACT( R7, R3.L ) (Z); +R3 = EXTRACT( R3, R3.L ) (Z); +CHECKREG r0, 0x0000F001; +CHECKREG r1, 0x0000F001; +CHECKREG r2, 0xFFFFF002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000F004; +CHECKREG r5, 0x0000F005; +CHECKREG r6, 0xFFFFF006; +CHECKREG r7, 0x0000F007; + +imm32 r0, 0x0c0000c0; +imm32 r1, 0x0c0100c0; +imm32 r2, 0x0c0200c0; +imm32 r3, 0x0c0300c0; +imm32 r4, 0x0c04000c; +imm32 r5, 0x0c0500c0; +imm32 r6, 0x0c0600c0; +imm32 r7, 0x0c0700c0; +R0 = EXTRACT( R0, R4.L ) (Z); +R1 = EXTRACT( R1, R4.L ) (Z); +R2 = EXTRACT( R2, R4.L ) (Z); +R3 = EXTRACT( R3, R4.L ) (Z); +R5 = EXTRACT( R5, R4.L ) (X); +R6 = EXTRACT( R6, R4.L ) (Z); +R7 = EXTRACT( R7, R4.L ) (Z); +R4 = EXTRACT( R4, R4.L ) (Z); +CHECKREG r0, 0x000000C0; +CHECKREG r1, 0x000000C0; +CHECKREG r2, 0x000000C0; +CHECKREG r3, 0x000000C0; +CHECKREG r4, 0x0000000C; +CHECKREG r5, 0x000000C0; +CHECKREG r6, 0x000000C0; +CHECKREG r7, 0x000000C0; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = EXTRACT( R0, R5.L ) (Z); +R1 = EXTRACT( R1, R5.L ) (X); +R2 = EXTRACT( R2, R5.L ) (Z); +R3 = EXTRACT( R3, R5.L ) (Z); +R4 = EXTRACT( R4, R5.L ) (X); +R6 = EXTRACT( R6, R5.L ) (Z); +R7 = EXTRACT( R7, R5.L ) (Z); +R5 = EXTRACT( R5, R5.L ) (Z); +CHECKREG r0, 0x00000050; +CHECKREG r1, 0xFFFFFFD1; +CHECKREG r2, 0x00000050; +CHECKREG r3, 0x00000050; +CHECKREG r4, 0xFFFFFFD0; +CHECKREG r5, 0x00000007; +CHECKREG r6, 0x00000050; +CHECKREG r7, 0x00000050; + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060009; +imm32 r7, 0xb0070000; +R0 = EXTRACT( R0, R6.L ) (Z); +R1 = EXTRACT( R1, R6.L ) (Z); +R2 = EXTRACT( R2, R6.L ) (Z); +R3 = EXTRACT( R3, R6.L ) (X); +R4 = EXTRACT( R4, R6.L ) (Z); +R5 = EXTRACT( R5, R6.L ) (Z); +R6 = EXTRACT( R6, R6.L ) (Z); +R7 = EXTRACT( R7, R6.L ) (Z); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x0000000F; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000009; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xd00100e0; +imm32 r1, 0xd00100e0; +imm32 r2, 0xd00200e0; +imm32 r3, 0xd00300e0; +imm32 r4, 0xd00400e0; +imm32 r5, 0xd00500e0; +imm32 r6, 0xd00600e0; +imm32 r7, 0xd0070023; +R1 = EXTRACT( R0, R7.L ) (Z); +R2 = EXTRACT( R1, R7.L ) (Z); +R3 = EXTRACT( R2, R7.L ) (Z); +R4 = EXTRACT( R3, R7.L ) (Z); +R5 = EXTRACT( R4, R7.L ) (X); +R6 = EXTRACT( R5, R7.L ) (Z); +R7 = EXTRACT( R6, R7.L ) (X); +R0 = EXTRACT( R7, R7.L ) (Z); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_lf.s b/sim/testsuite/bfin/c_dsp32shift_lf.s new file mode 100644 index 0000000..88ee774 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_lf.s @@ -0,0 +1,422 @@ +//Original:/testcases/core/c_dsp32shift_lf/c_dsp32shift_lf.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : mix data, count (+)= (half reg) +// d_reg = lshift (d BY d_lo) +// Rx by RLx +imm32 r0, 0x01210001; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R7 = LSHIFT R0 BY R0.L; +R6 = LSHIFT R1 BY R0.L; +R0 = LSHIFT R2 BY R0.L; +R1 = LSHIFT R3 BY R0.L; +R2 = LSHIFT R4 BY R0.L; +R3 = LSHIFT R5 BY R0.L; +R4 = LSHIFT R6 BY R0.L; +R5 = LSHIFT R7 BY R0.L; +CHECKREG r0, 0x4682CF12; +CHECKREG r1, 0xE2680000; +CHECKREG r2, 0x26AC0000; +CHECKREG r3, 0x6AF00000; +CHECKREG r4, 0xB3C00000; +CHECKREG r5, 0x00080000; +CHECKREG r6, 0x2462ACF0; +CHECKREG r7, 0x02420002; + +imm32 r0, 0x01220002; +imm32 r1, 0x12325678; +imm32 r2, 0x23426789; +imm32 r3, 0x3452789a; +imm32 r4, 0x956289ab; +imm32 r5, 0xa6729abc; +imm32 r6, 0xb782abcd; +imm32 r7, 0xc892bcde; +R1.L = 2; +R3 = LSHIFT R0 BY R1.L; +R4 = LSHIFT R1 BY R1.L; +R5 = LSHIFT R2 BY R1.L; +R6 = LSHIFT R3 BY R1.L; +R7 = LSHIFT R4 BY R1.L; +R0 = LSHIFT R5 BY R1.L; +R1 = LSHIFT R6 BY R1.L; +R2 = LSHIFT R7 BY R1.L; +CHECKREG r0, 0x34267890; +CHECKREG r1, 0x48800080; +CHECKREG r2, 0x23200020; +CHECKREG r3, 0x04880008; +CHECKREG r4, 0x48C80008; +CHECKREG r5, 0x8D099E24; +CHECKREG r6, 0x12200020; +CHECKREG r7, 0x23200020; + +imm32 r0, 0x01230002; +imm32 r1, 0x12335678; +imm32 r2, 0x23436789; +imm32 r3, 0x3453789a; +imm32 r4, 0x456389ab; +imm32 r5, 0x56739abc; +imm32 r6, 0x6783abcd; +imm32 r7, 0x789abcde; +R2 = 14; +R0 = LSHIFT R4 BY R2.L; +R1 = LSHIFT R5 BY R2.L; +R2 = LSHIFT R6 BY R2.L; +R3 = LSHIFT R7 BY R2.L; +CHECKREG r0, 0xE26AC000; +CHECKREG r1, 0xE6AF0000; +CHECKREG r2, 0xEAF34000; +CHECKREG r3, 0x789ABCDE; + +imm32 r0, 0x01240002; +imm32 r1, 0x12345678; +imm32 r2, 0x23446789; +imm32 r3, 0x3454789a; +imm32 r4, 0xa56489ab; +imm32 r5, 0xb6749abc; +imm32 r6, 0xc784abcd; +imm32 r7, 0xd894bcde; +R3.L = 15; +R4 = LSHIFT R0 BY R3.L; +R5 = LSHIFT R1 BY R3.L; +R6 = LSHIFT R2 BY R3.L; +R7 = LSHIFT R3 BY R3.L; +R0 = LSHIFT R4 BY R3.L; +R1 = LSHIFT R5 BY R3.L; +R2 = LSHIFT R6 BY R3.L; +R3 = LSHIFT R7 BY R3.L; +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0xC0000000; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x2B3C0000; +CHECKREG r6, 0x33C48000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x01250002; +imm32 r1, 0x12355678; +imm32 r2, 0x23456789; +imm32 r3, 0x3455789a; +imm32 r4, 0x456589ab; +imm32 r5, 0x56759abc; +imm32 r6, 0x6785abcd; +imm32 r7, 0x7895bcde; +R4.L = -1; +R7 = LSHIFT R0 BY R4.L; +R6 = LSHIFT R1 BY R4.L; +R5 = LSHIFT R2 BY R4.L; +R3 = LSHIFT R4 BY R4.L; +R2 = LSHIFT R5 BY R4.L; +R1 = LSHIFT R6 BY R4.L; +R0 = LSHIFT R7 BY R4.L; +R4 = LSHIFT R3 BY R4.L; +CHECKREG r0, 0x00494000; +CHECKREG r1, 0x048D559E; +CHECKREG r2, 0x08D159E2; +CHECKREG r3, 0x22B2FFFF; +CHECKREG r4, 0x11597FFF; +CHECKREG r5, 0x11A2B3C4; +CHECKREG r6, 0x091AAB3C; +CHECKREG r7, 0x00928001; + +imm32 r0, 0x01260002; +imm32 r1, 0x82365678; +imm32 r2, 0x93466789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56689ab; +imm32 r5, 0xc6769abc; +imm32 r6, 0xd786abcd; +imm32 r7, 0xe896bcde; +R5.L = -8; +R6 = LSHIFT R0 BY R5.L; +R7 = LSHIFT R1 BY R5.L; +R0 = LSHIFT R2 BY R5.L; +R1 = LSHIFT R3 BY R5.L; +R2 = LSHIFT R4 BY R5.L; +R3 = LSHIFT R5 BY R5.L; +R4 = LSHIFT R6 BY R5.L; +R5 = LSHIFT R7 BY R5.L; +CHECKREG r0, 0x00934667; +CHECKREG r1, 0x00A45678; +CHECKREG r2, 0x00B56689; +CHECKREG r3, 0x00C676FF; +CHECKREG r4, 0x00000126; +CHECKREG r5, 0x00008236; +CHECKREG r6, 0x00012600; +CHECKREG r7, 0x00823656; + +imm32 r0, 0x01270002; +imm32 r1, 0x12375678; +imm32 r2, 0x23476789; +imm32 r3, 0x3457789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56779abc; +imm32 r6, 0x6787abcd; +imm32 r7, 0x7897bcde; +R6.L = -15; +R7 = LSHIFT R0 BY R6.L; +R0 = LSHIFT R1 BY R6.L; +R1 = LSHIFT R2 BY R6.L; +R2 = LSHIFT R3 BY R6.L; +R3 = LSHIFT R4 BY R6.L; +R4 = LSHIFT R5 BY R6.L; +R5 = LSHIFT R6 BY R6.L; +R6 = LSHIFT R7 BY R6.L; +CHECKREG r0, 0x0000246E; +CHECKREG r1, 0x0000468E; +CHECKREG r2, 0x000068AE; +CHECKREG r3, 0x00008ACF; +CHECKREG r4, 0x0000ACEF; +CHECKREG r5, 0x0000CF0F; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x0000024E; + +imm32 r0, 0x01280002; +imm32 r1, 0x82385678; +imm32 r2, 0x93486789; +imm32 r3, 0xa458789a; +imm32 r4, 0xb56889ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd788abcd; +imm32 r7, 0xe898bcde; +R7.L = -16; +R0 = LSHIFT R0 BY R7.L; +R1 = LSHIFT R1 BY R7.L; +R2 = LSHIFT R2 BY R7.L; +R3 = LSHIFT R3 BY R7.L; +R4 = LSHIFT R4 BY R7.L; +R5 = LSHIFT R5 BY R7.L; +R6 = LSHIFT R6 BY R7.L; +R7 = LSHIFT R7 BY R7.L; +CHECKREG r0, 0x00000128; +CHECKREG r1, 0x00008238; +CHECKREG r2, 0x00009348; +CHECKREG r3, 0x0000A458; +CHECKREG r4, 0x0000B568; +CHECKREG r5, 0x0000C678; +CHECKREG r6, 0x0000D788; +CHECKREG r7, 0x0000E898; + +imm32 r0, 0x81290002; +imm32 r1, 0x92395678; +imm32 r2, 0xa3496789; +imm32 r3, 0xb459789a; +imm32 r4, 0xc56989ab; +imm32 r5, 0xd6799abc; +imm32 r6, 0xe789abcd; +imm32 r7, 0xf899bcde; +R0.L = 4; +//r0 = lshift (r0 by rl0); +R1 = LSHIFT R1 BY R0.L; +R2 = LSHIFT R2 BY R0.L; +R3 = LSHIFT R3 BY R0.L; +R4 = LSHIFT R4 BY R0.L; +R5 = LSHIFT R5 BY R0.L; +R6 = LSHIFT R6 BY R0.L; +R7 = LSHIFT R7 BY R0.L; +CHECKREG r1, 0x23956780; +CHECKREG r2, 0x34967890; +CHECKREG r3, 0x459789A0; +CHECKREG r4, 0x56989AB0; +CHECKREG r5, 0x6799ABC0; +CHECKREG r6, 0x789ABCD0; +CHECKREG r7, 0x899BCDE0; + +imm32 r0, 0x012a0002; +imm32 r1, 0x123a5678; +imm32 r2, 0x234a6789; +imm32 r3, 0x345a789a; +imm32 r4, 0x456a89ab; +imm32 r5, 0x567a9abc; +imm32 r6, 0x678aabcd; +imm32 r7, 0xf89abcde; +R1.L = 2; +R7 = LSHIFT R0 BY R1.L; +R6 = LSHIFT R1 BY R1.L; +R5 = LSHIFT R2 BY R1.L; +R4 = LSHIFT R3 BY R1.L; +R3 = LSHIFT R4 BY R1.L; +R2 = LSHIFT R5 BY R1.L; +R0 = LSHIFT R6 BY R1.L; +R1 = LSHIFT R7 BY R1.L; +CHECKREG r0, 0x23A00020; +CHECKREG r1, 0x12A00020; +CHECKREG r2, 0x34A67890; +CHECKREG r3, 0x45A789A0; +CHECKREG r4, 0xD169E268; +CHECKREG r5, 0x8D299E24; +CHECKREG r6, 0x48E80008; +CHECKREG r7, 0x04A80008; + + +imm32 r0, 0x012b0002; +imm32 r1, 0x123b5678; +imm32 r2, 0x234b6789; +imm32 r3, 0x345b789a; +imm32 r4, 0x456b89ab; +imm32 r5, 0x567b9abc; +imm32 r6, 0x678babcd; +imm32 r7, 0x789bbcde; +R2.L = 15; +R0 = LSHIFT R0 BY R2.L; +R1 = LSHIFT R1 BY R2.L; +R3 = LSHIFT R3 BY R2.L; +R4 = LSHIFT R4 BY R2.L; +R5 = LSHIFT R5 BY R2.L; +R6 = LSHIFT R6 BY R2.L; +R7 = LSHIFT R7 BY R2.L; +R2 = LSHIFT R2 BY R2.L; +CHECKREG r0, 0x80010000; +CHECKREG r1, 0xAB3C0000; +CHECKREG r2, 0x80078000; +CHECKREG r3, 0xBC4D0000; +CHECKREG r4, 0xC4D58000; +CHECKREG r5, 0xCD5E0000; +CHECKREG r6, 0xD5E68000; +CHECKREG r7, 0xDE6F0000; + +imm32 r0, 0x012c0002; +imm32 r1, 0x123c5678; +imm32 r2, 0x234c6789; +imm32 r3, 0x345c789a; +imm32 r4, 0x456c89ab; +imm32 r5, 0x567c9abc; +imm32 r6, 0x678cabcd; +imm32 r7, 0x789cbcde; +R3.L = 16; +R0 = LSHIFT R0 BY R3.L; +R1 = LSHIFT R1 BY R3.L; +R2 = LSHIFT R2 BY R3.L; +R4 = LSHIFT R4 BY R3.L; +R5 = LSHIFT R5 BY R3.L; +R6 = LSHIFT R6 BY R3.L; +R7 = LSHIFT R7 BY R3.L; +R3 = LSHIFT R3 BY R3.L; +CHECKREG r0, 0x00020000; +CHECKREG r1, 0x56780000; +CHECKREG r2, 0x67890000; +CHECKREG r3, 0x00100000; +CHECKREG r4, 0x89AB0000; +CHECKREG r5, 0x9ABC0000; +CHECKREG r6, 0xABCD0000; +CHECKREG r7, 0xBCDE0000; + +imm32 r0, 0x012d0002; +imm32 r1, 0x123d5678; +imm32 r2, 0x234d6789; +imm32 r3, 0x345d789a; +imm32 r4, 0x456d89ab; +imm32 r5, 0x567d9abc; +imm32 r6, 0x678dabcd; +imm32 r7, 0x789dbcde; +R4.L = -9; +R7 = LSHIFT R0 BY R4.L; +R0 = LSHIFT R1 BY R4.L; +R1 = LSHIFT R2 BY R4.L; +R2 = LSHIFT R3 BY R4.L; +//r4 = lshift (r4 by rl4); +R3 = LSHIFT R5 BY R4.L; +R5 = LSHIFT R6 BY R4.L; +R6 = LSHIFT R7 BY R4.L; +CHECKREG r0, 0x00091EAB; +CHECKREG r1, 0x0011A6B3; +CHECKREG r2, 0x001A2EBC; +CHECKREG r3, 0x002B3ECD; +CHECKREG r4, 0x456DFFF7; +CHECKREG r5, 0x0033C6D5; +CHECKREG r6, 0x0000004B; +CHECKREG r7, 0x00009680; + +imm32 r0, 0x012e0002; +imm32 r1, 0x123e5678; +imm32 r2, 0x234e6789; +imm32 r3, 0x345e789a; +imm32 r4, 0x456e89ab; +imm32 r5, 0x567e9abc; +imm32 r6, 0x678eabcd; +imm32 r7, 0x789ebcde; +R5.L = -14; +R0 = LSHIFT R0 BY R5.L; +R1 = LSHIFT R1 BY R5.L; +R2 = LSHIFT R2 BY R5.L; +R3 = LSHIFT R3 BY R5.L; +R4 = LSHIFT R4 BY R5.L; +//r5 = lshift (r5 by rl5); +R6 = LSHIFT R6 BY R5.L; +R7 = LSHIFT R7 BY R5.L; +CHECKREG r0, 0x000004B8; +CHECKREG r1, 0x000048F9; +CHECKREG r2, 0x00008D39; +CHECKREG r3, 0x0000D179; +CHECKREG r4, 0x000115BA; +CHECKREG r5, 0x567EFFF2; +CHECKREG r6, 0x00019E3A; +CHECKREG r7, 0x0001E27A; + + +imm32 r0, 0x012f0002; +imm32 r1, 0x623f5678; +imm32 r2, 0x734f6789; +imm32 r3, 0x845f789a; +imm32 r4, 0x956f89ab; +imm32 r5, 0xa67f9abc; +imm32 r6, 0xc78fabcd; +imm32 r7, 0xd89fbcde; +R6.L = -15; +R0 = LSHIFT R0 BY R6.L; +R1 = LSHIFT R1 BY R6.L; +R2 = LSHIFT R2 BY R6.L; +R3 = LSHIFT R3 BY R6.L; +R4 = LSHIFT R4 BY R6.L; +R5 = LSHIFT R5 BY R6.L; +//r6 = lshift (r6 by rl6); +R7 = LSHIFT R7 BY R6.L; +CHECKREG r0, 0x0000025E; +CHECKREG r1, 0x0000C47E; +CHECKREG r2, 0x0000E69E; +CHECKREG r3, 0x000108BE; +CHECKREG r4, 0x00012ADF; +CHECKREG r5, 0x00014CFF; +CHECKREG r6, 0xC78FFFF1; +CHECKREG r7, 0x0001B13F; + +imm32 r0, 0x71230072; +imm32 r1, 0x82345678; +imm32 r2, 0x93456779; +imm32 r3, 0xa456787a; +imm32 r4, 0xb567897b; +imm32 r5, 0xc6789a7c; +imm32 r6, 0x6789ab7d; +imm32 r7, 0x789abc7e; +R7.L = -16; +R0 = LSHIFT R0 BY R7.L; +R1 = LSHIFT R1 BY R7.L; +R2 = LSHIFT R2 BY R7.L; +R3 = LSHIFT R3 BY R7.L; +R4 = LSHIFT R4 BY R7.L; +R5 = LSHIFT R5 BY R7.L; +R6 = LSHIFT R6 BY R7.L; +R7 = LSHIFT R7 BY R7.L; +CHECKREG r0, 0x00007123; +CHECKREG r1, 0x00008234; +CHECKREG r2, 0x00009345; +CHECKREG r3, 0x0000A456; +CHECKREG r4, 0x0000B567; +CHECKREG r5, 0x0000C678; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x0000789A; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_lhalf_ln.s b/sim/testsuite/bfin/c_dsp32shift_lhalf_ln.s new file mode 100644 index 0000000..df47e33 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_lhalf_ln.s @@ -0,0 +1,422 @@ +//Original:/testcases/core/c_dsp32shift_lhalf_ln/c_dsp32shift_lhalf_ln.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : neg data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R0.L = LSHIFT R0.L BY R0.L; +R1.L = LSHIFT R1.L BY R0.L; +R2.L = LSHIFT R2.L BY R0.L; +R3.L = LSHIFT R3.L BY R0.L; +R4.L = LSHIFT R4.L BY R0.L; +R5.L = LSHIFT R5.L BY R0.L; +R6.L = LSHIFT R6.L BY R0.L; +R7.L = LSHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c001; +CHECKREG r2, 0x0000c002; +CHECKREG r3, 0x0000c003; +CHECKREG r4, 0x0000c004; +CHECKREG r5, 0x0000c005; +CHECKREG r6, 0x0000c006; +CHECKREG r7, 0x0000c007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R0.L = LSHIFT R0.L BY R1.L; +//rl1 = lshift (rl1 by rl1); +R2.L = LSHIFT R2.L BY R1.L; +R3.L = LSHIFT R3.L BY R1.L; +R4.L = LSHIFT R4.L BY R1.L; +R5.L = LSHIFT R5.L BY R1.L; +R6.L = LSHIFT R6.L BY R1.L; +R7.L = LSHIFT R7.L BY R1.L; +//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */ +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000a004; +CHECKREG r3, 0x0000c006; +CHECKREG r4, 0x0000e008; +CHECKREG r5, 0x0000800a; +CHECKREG r6, 0x0000a00c; +CHECKREG r7, 0x0000c00e; + + +imm32 r0, 0x0000c001; +imm32 r1, 0x0000d001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = LSHIFT R0.L BY R2.L; +R1.L = LSHIFT R1.L BY R2.L; +//rl2 = lshift (rl2 by rl2); +R3.L = LSHIFT R3.L BY R2.L; +R4.L = LSHIFT R4.L BY R2.L; +R5.L = LSHIFT R5.L BY R2.L; +R6.L = LSHIFT R6.L BY R2.L; +R7.L = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00009001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000b002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000f007; +R0.L = LSHIFT R0.L BY R3.L; +R1.L = LSHIFT R1.L BY R3.L; +R2.L = LSHIFT R2.L BY R3.L; +//rl3 = lshift (rl3 by rl3); +R4.L = LSHIFT R4.L BY R3.L; +R5.L = LSHIFT R5.L BY R3.L; +R6.L = LSHIFT R6.L BY R3.L; +R7.L = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = lshft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R0.L; +R1.L = LSHIFT R1.H BY R0.L; +R2.L = LSHIFT R2.H BY R0.L; +R3.L = LSHIFT R3.H BY R0.L; +R4.L = LSHIFT R4.H BY R0.L; +R5.L = LSHIFT R5.H BY R0.L; +R6.L = LSHIFT R6.H BY R0.L; +R7.L = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R0.L = LSHIFT R0.H BY R1.L; +//rl1 = lshift (rh1 by rl1); +R2.L = LSHIFT R2.H BY R1.L; +R3.L = LSHIFT R3.H BY R1.L; +R4.L = LSHIFT R4.H BY R1.L; +R5.L = LSHIFT R5.H BY R1.L; +R6.L = LSHIFT R6.H BY R1.L; +R7.L = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x90012002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x90022004; +CHECKREG r3, 0x90032006; +CHECKREG r4, 0x90042008; +CHECKREG r5, 0x9005200a; +CHECKREG r6, 0x9006200c; +CHECKREG r7, 0x9007200e; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0xa0018000; +CHECKREG r1, 0xa0018000; +CHECKREG r2, 0xa002000f; +CHECKREG r3, 0xa0038000; +CHECKREG r4, 0xa0040000; +CHECKREG r5, 0xa0058000; +CHECKREG r6, 0xa0060000; +CHECKREG r7, 0xa0078000; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc0070007; +R0.L = LSHIFT R0.H BY R3.L; +R1.L = LSHIFT R1.H BY R3.L; +R2.L = LSHIFT R2.H BY R3.L; +//rl3 = lshift (rh3 by rl3); +R4.L = LSHIFT R4.H BY R3.L; +R5.L = LSHIFT R5.H BY R3.L; +R6.L = LSHIFT R6.H BY R3.L; +R7.L = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0xc0010000; +CHECKREG r1, 0xc0010000; +CHECKREG r2, 0xc0020000; +CHECKREG r3, 0xc0030010; +CHECKREG r4, 0xc0040000; +CHECKREG r5, 0xc0050000; +CHECKREG r6, 0xc0060000; +CHECKREG r7, 0xc0070000; + +// d_hi = lshft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R0.L; +R1.H = LSHIFT R1.L BY R0.L; +R2.H = LSHIFT R2.L BY R0.L; +R3.H = LSHIFT R3.L BY R0.L; +R4.H = LSHIFT R4.L BY R0.L; +R5.H = LSHIFT R5.L BY R0.L; +R6.H = LSHIFT R6.L BY R0.L; +R7.H = LSHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R0.H = LSHIFT R0.L BY R1.L; +R1.H = LSHIFT R1.L BY R1.L; +R2.H = LSHIFT R2.L BY R1.L; +R3.H = LSHIFT R3.L BY R1.L; +R4.H = LSHIFT R4.L BY R1.L; +R5.H = LSHIFT R5.L BY R1.L; +R6.H = LSHIFT R6.L BY R1.L; +R7.H = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0xa002d001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0xa004d002; +CHECKREG r3, 0xa006d003; +CHECKREG r4, 0xa008d004; +CHECKREG r5, 0xa00ad005; +CHECKREG r6, 0xa00cd006; +CHECKREG r7, 0xa00ed007; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = LSHIFT R0.L BY R2.L; +R1.H = LSHIFT R1.L BY R2.L; +//rh2 = lshift (rl2 by rl2); +R3.H = LSHIFT R3.L BY R2.L; +R4.H = LSHIFT R4.L BY R2.L; +R5.H = LSHIFT R5.L BY R2.L; +R6.H = LSHIFT R6.L BY R2.L; +R7.H = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x8000e001; +CHECKREG r1, 0x8000e001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x8000e003; +CHECKREG r4, 0x0000e004; +CHECKREG r5, 0x8000e005; +CHECKREG r6, 0x0000e006; +CHECKREG r7, 0x8000e007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.H = LSHIFT R0.L BY R3.L; +R1.H = LSHIFT R1.L BY R3.L; +R2.H = LSHIFT R2.L BY R3.L; +R3.H = LSHIFT R3.L BY R3.L; +R4.H = LSHIFT R4.L BY R3.L; +R5.H = LSHIFT R5.L BY R3.L; +R6.H = LSHIFT R6.L BY R3.L; +R7.H = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x0000f001; +CHECKREG r1, 0x0000f001; +CHECKREG r2, 0x0000f002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000f004; +CHECKREG r5, 0x0000f005; +CHECKREG r6, 0x0000f006; +CHECKREG r7, 0x0000f007; + +// d_lo = lshft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R0.L; +R1.H = LSHIFT R1.H BY R0.L; +R2.H = LSHIFT R2.H BY R0.L; +R3.H = LSHIFT R3.H BY R0.L; +R4.H = LSHIFT R4.H BY R0.L; +R5.H = LSHIFT R5.H BY R0.L; +R6.H = LSHIFT R6.H BY R0.L; +R7.H = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.H = LSHIFT R0.H BY R1.L; +R1.H = LSHIFT R1.H BY R1.L; +R2.H = LSHIFT R2.H BY R1.L; +R3.H = LSHIFT R3.H BY R1.L; +R4.H = LSHIFT R4.H BY R1.L; +R5.H = LSHIFT R5.H BY R1.L; +R6.H = LSHIFT R6.H BY R1.L; +R7.H = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x40020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x40040000; +CHECKREG r3, 0x40060000; +CHECKREG r4, 0x40080000; +CHECKREG r5, 0x400a0000; +CHECKREG r6, 0x400c0000; +CHECKREG r7, 0x400e0000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0xb0018000; +CHECKREG r1, 0xb0018000; +CHECKREG r2, 0xb002000f; +CHECKREG r3, 0xb0038000; +CHECKREG r4, 0xb0040000; +CHECKREG r5, 0xb0058000; +CHECKREG r6, 0xb0060000; +CHECKREG r7, 0xb0078000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R0.H = LSHIFT R0.H BY R3.L; +R1.H = LSHIFT R1.H BY R3.L; +R2.H = LSHIFT R2.H BY R3.L; +R3.H = LSHIFT R3.H BY R3.L; +R4.H = LSHIFT R4.H BY R3.L; +R5.H = LSHIFT R5.H BY R3.L; +R6.H = LSHIFT R6.H BY R3.L; +R7.H = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_lhalf_lp.s b/sim/testsuite/bfin/c_dsp32shift_lhalf_lp.s new file mode 100644 index 0000000..6000715 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_lhalf_lp.s @@ -0,0 +1,422 @@ +//Original:/testcases/core/c_dsp32shift_lhalf_lp/c_dsp32shift_lhalf_lp.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = LSHIFT R0.L BY R0.L; +R1.L = LSHIFT R1.L BY R0.L; +R2.L = LSHIFT R2.L BY R0.L; +R3.L = LSHIFT R3.L BY R0.L; +R4.L = LSHIFT R4.L BY R0.L; +R5.L = LSHIFT R5.L BY R0.L; +R6.L = LSHIFT R6.L BY R0.L; +R7.L = LSHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = LSHIFT R0.L BY R1.L; +//rl1 = lshift (rl1 by rl1); +R2.L = LSHIFT R2.L BY R1.L; +R3.L = LSHIFT R3.L BY R1.L; +R4.L = LSHIFT R4.L BY R1.L; +R5.L = LSHIFT R5.L BY R1.L; +R6.L = LSHIFT R6.L BY R1.L; +R7.L = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000006; +CHECKREG r4, 0x00000008; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x0000000c; +CHECKREG r7, 0x0000000e; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = LSHIFT R0.L BY R2.L; +R1.L = LSHIFT R1.L BY R2.L; +//rl2 = lshift (rl2 by rl2); +R3.L = LSHIFT R3.L BY R2.L; +R4.L = LSHIFT R4.L BY R2.L; +R5.L = LSHIFT R5.L BY R2.L; +R6.L = LSHIFT R6.L BY R2.L; +R7.L = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = LSHIFT R0.L BY R3.L; +R1.L = LSHIFT R1.L BY R3.L; +R2.L = LSHIFT R2.L BY R3.L; +//rl3 = lshift (rl3 by rl3); +R4.L = LSHIFT R4.L BY R3.L; +R5.L = LSHIFT R5.L BY R3.L; +R6.L = LSHIFT R6.L BY R3.L; +R7.L = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R0.L; +R1.L = LSHIFT R1.H BY R0.L; +R2.L = LSHIFT R2.H BY R0.L; +R3.L = LSHIFT R3.H BY R0.L; +R4.L = LSHIFT R4.H BY R0.L; +R5.L = LSHIFT R5.H BY R0.L; +R6.L = LSHIFT R6.H BY R0.L; +R7.L = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R1.L; +//rl1 = lshift (rh1 by rl1); +R2.L = LSHIFT R2.H BY R1.L; +R3.L = LSHIFT R3.H BY R1.L; +R4.L = LSHIFT R4.H BY R1.L; +R5.L = LSHIFT R5.H BY R1.L; +R6.L = LSHIFT R6.H BY R1.L; +R7.L = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x00010002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020004; +CHECKREG r3, 0x00030006; +CHECKREG r4, 0x00040008; +CHECKREG r5, 0x0005000a; +CHECKREG r6, 0x0006000c; +CHECKREG r7, 0x0007000e; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0x00018000; +CHECKREG r1, 0x00018000; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00038000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00058000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x00010001; +imm32 r1, 0x00010001; +imm32 r2, 0x00020002; +imm32 r3, 0x00030010; +imm32 r4, 0x00040004; +imm32 r5, 0x00050005; +imm32 r6, 0x00060006; +imm32 r7, 0x00070007; +R0.L = LSHIFT R0.H BY R3.L; +R1.L = LSHIFT R1.H BY R3.L; +R2.L = LSHIFT R2.H BY R3.L; +//rl3 = lshift (rh3 by rl3); +R4.L = LSHIFT R4.H BY R3.L; +R5.L = LSHIFT R5.H BY R3.L; +R6.L = LSHIFT R6.H BY R3.L; +R7.L = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030010; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R0.L; +R1.H = LSHIFT R1.L BY R0.L; +R2.H = LSHIFT R2.L BY R0.L; +R3.H = LSHIFT R3.L BY R0.L; +R4.H = LSHIFT R4.L BY R0.L; +R5.H = LSHIFT R5.L BY R0.L; +R6.H = LSHIFT R6.L BY R0.L; +R7.H = LSHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R1.L; +R1.H = LSHIFT R1.L BY R1.L; +R2.H = LSHIFT R2.L BY R1.L; +R3.H = LSHIFT R3.L BY R1.L; +R4.H = LSHIFT R4.L BY R1.L; +R5.H = LSHIFT R5.L BY R1.L; +R6.H = LSHIFT R6.L BY R1.L; +R7.H = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0x00020001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040002; +CHECKREG r3, 0x00060003; +CHECKREG r4, 0x00080004; +CHECKREG r5, 0x000a0005; +CHECKREG r6, 0x000c0006; +CHECKREG r7, 0x000e0007; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R2.L; +R1.H = LSHIFT R1.L BY R2.L; +//rh2 = lshift (rl2 by rl2); +R3.H = LSHIFT R3.L BY R2.L; +R4.H = LSHIFT R4.L BY R2.L; +R5.H = LSHIFT R5.L BY R2.L; +R6.H = LSHIFT R6.L BY R2.L; +R7.H = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x80000001; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x80000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x80000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x80000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R3.L; +R1.H = LSHIFT R1.L BY R3.L; +R2.H = LSHIFT R2.L BY R3.L; +R3.H = LSHIFT R3.L BY R3.L; +R4.H = LSHIFT R4.L BY R3.L; +R5.H = LSHIFT R5.L BY R3.L; +R6.H = LSHIFT R6.L BY R3.L; +R7.H = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R0.L; +R1.H = LSHIFT R1.H BY R0.L; +R2.H = LSHIFT R2.H BY R0.L; +R3.H = LSHIFT R3.H BY R0.L; +R4.H = LSHIFT R4.H BY R0.L; +R5.H = LSHIFT R5.H BY R0.L; +R6.H = LSHIFT R6.H BY R0.L; +R7.H = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R1.L; +R1.H = LSHIFT R1.H BY R1.L; +R2.H = LSHIFT R2.H BY R1.L; +R3.H = LSHIFT R3.H BY R1.L; +R4.H = LSHIFT R4.H BY R1.L; +R5.H = LSHIFT R5.H BY R1.L; +R6.H = LSHIFT R6.H BY R1.L; +R7.H = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x00020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040000; +CHECKREG r3, 0x00060000; +CHECKREG r4, 0x00080000; +CHECKREG r5, 0x000a0000; +CHECKREG r6, 0x000c0000; +CHECKREG r7, 0x000e0000; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0x00018000; +CHECKREG r1, 0x00018000; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00038000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00058000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030010; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R3.L; +R1.H = LSHIFT R1.H BY R3.L; +R2.H = LSHIFT R2.H BY R3.L; +R3.H = LSHIFT R3.H BY R3.L; +R4.H = LSHIFT R4.H BY R3.L; +R5.H = LSHIFT R5.H BY R3.L; +R6.H = LSHIFT R6.H BY R3.L; +R7.H = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_lhalf_rn.s b/sim/testsuite/bfin/c_dsp32shift_lhalf_rn.s new file mode 100644 index 0000000..a5b6563 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_lhalf_rn.s @@ -0,0 +1,425 @@ +//Original:/testcases/core/c_dsp32shift_lhalf_rn/c_dsp32shift_lhalf_rn.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +//rl0 = lshift (rl0 by rl0); +R1.L = LSHIFT R1.L BY R0.L; +R2.L = LSHIFT R2.L BY R0.L; +R3.L = LSHIFT R3.L BY R0.L; +R4.L = LSHIFT R4.L BY R0.L; +R5.L = LSHIFT R5.L BY R0.L; +R6.L = LSHIFT R6.L BY R0.L; +R7.L = LSHIFT R7.L BY R0.L; +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00004000; +CHECKREG r2, 0x00004001; +CHECKREG r3, 0x00004001; +CHECKREG r4, 0x00004002; +CHECKREG r5, 0x00004002; +CHECKREG r6, 0x00004003; +CHECKREG r7, 0x00004003; + +imm32 r0, 0x00008001; +R1.L = -1; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = LSHIFT R0.L BY R1.L; +//rl1 = lshift (rl1 by rl1); +R2.L = LSHIFT R2.L BY R1.L; +R3.L = LSHIFT R3.L BY R1.L; +R4.L = LSHIFT R4.L BY R1.L; +R5.L = LSHIFT R5.L BY R1.L; +R6.L = LSHIFT R6.L BY R1.L; +R7.L = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0x00004000; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00004001; +CHECKREG r3, 0x00004001; +CHECKREG r4, 0x00004002; +CHECKREG r5, 0x00004002; +CHECKREG r6, 0x00004003; +CHECKREG r7, 0x00004003; + + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +R2.L = -15; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = LSHIFT R0.L BY R2.L; +R1.L = LSHIFT R1.L BY R2.L; +//rl2 = lshift (rl2 by rl2); +R3.L = LSHIFT R3.L BY R2.L; +R4.L = LSHIFT R4.L BY R2.L; +R5.L = LSHIFT R5.L BY R2.L; +R6.L = LSHIFT R6.L BY R2.L; +R7.L = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +R3.L = -16; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = LSHIFT R0.L BY R3.L; +R1.L = LSHIFT R1.L BY R3.L; +R2.L = LSHIFT R2.L BY R3.L; +//rl3 = lshift (rl3 by rl3); +R4.L = LSHIFT R4.L BY R3.L; +R5.L = LSHIFT R5.L BY R3.L; +R6.L = LSHIFT R6.L BY R3.L; +R7.L = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = LSHIFT R0.H BY R0.L; +R1.L = LSHIFT R1.H BY R0.L; +R2.L = LSHIFT R2.H BY R0.L; +R3.L = LSHIFT R3.H BY R0.L; +R4.L = LSHIFT R4.H BY R0.L; +R5.L = LSHIFT R5.H BY R0.L; +R6.L = LSHIFT R6.H BY R0.L; +R7.L = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x80018001; +CHECKREG r2, 0x80028002; +CHECKREG r3, 0x80038003; +CHECKREG r4, 0x80048004; +CHECKREG r5, 0x80058005; +CHECKREG r6, 0x80068006; +CHECKREG r7, 0x80078007; + +imm32 r0, 0x80010000; +R1.L = -1; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = LSHIFT R0.H BY R1.L; +//rl1 = lshift (rh1 by rl1); +R2.L = LSHIFT R2.H BY R1.L; +R3.L = LSHIFT R3.H BY R1.L; +R4.L = LSHIFT R4.H BY R1.L; +R5.L = LSHIFT R5.H BY R1.L; +R6.L = LSHIFT R6.H BY R1.L; +R7.L = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x80014000; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x80024001; +CHECKREG r3, 0x80034001; +CHECKREG r4, 0x80044002; +CHECKREG r5, 0x80054002; +CHECKREG r6, 0x80064003; +CHECKREG r7, 0x80074003; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +R2.L = -15; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0xa0010001; +CHECKREG r1, 0xa0010001; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0xa0030001; +CHECKREG r4, 0xa0040001; +CHECKREG r5, 0xa0050001; +CHECKREG r6, 0xa0060001; +CHECKREG r7, 0xa0070001; + +imm32 r0, 0xb0010001; +imm32 r1, 0xb0010001; +imm32 r2, 0xb0020002; +R3.L = -16; +imm32 r4, 0xb0040004; +imm32 r5, 0xb0050005; +imm32 r6, 0xb0060006; +imm32 r7, 0xb0070007; +R0.L = LSHIFT R0.H BY R3.L; +R1.L = LSHIFT R1.H BY R3.L; +R2.L = LSHIFT R2.H BY R3.L; +//rl3 = lshift (rh3 by rl3); +R4.L = LSHIFT R4.H BY R3.L; +R5.L = LSHIFT R5.H BY R3.L; +R6.L = LSHIFT R6.H BY R3.L; +R7.L = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0xb0010000; +CHECKREG r1, 0xb0010000; +CHECKREG r2, 0xb0020000; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0xb0040000; +CHECKREG r5, 0xb0050000; +CHECKREG r6, 0xb0060000; +CHECKREG r7, 0xb0070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R4.L; +R1.H = LSHIFT R1.L BY R4.L; +R2.H = LSHIFT R2.L BY R4.L; +R3.H = LSHIFT R3.L BY R4.L; +//rh4 = lshift (rl4 by rl4); +R5.H = LSHIFT R5.L BY R4.L; +R6.H = LSHIFT R6.L BY R4.L; +R7.H = LSHIFT R7.L BY R4.L; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +R5.L = -1; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = LSHIFT R0.L BY R5.L; +R1.H = LSHIFT R1.L BY R5.L; +R2.H = LSHIFT R2.L BY R5.L; +R3.H = LSHIFT R3.L BY R5.L; +R4.H = LSHIFT R4.L BY R5.L; +//rh5 = lshift (rl5 by rl5); +R6.H = LSHIFT R6.L BY R5.L; +R7.H = LSHIFT R7.L BY R5.L; +CHECKREG r0, 0x40008001; +CHECKREG r1, 0x40008001; +CHECKREG r2, 0x40018002; +CHECKREG r3, 0x40018003; +CHECKREG r4, 0x40028004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0x40038006; +CHECKREG r7, 0x40038007; + + +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009004; +imm32 r5, 0x00009005; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = LSHIFT R0.L BY R6.L; +R1.H = LSHIFT R1.L BY R6.L; +R2.H = LSHIFT R2.L BY R6.L; +R3.H = LSHIFT R3.L BY R6.L; +R4.H = LSHIFT R4.L BY R6.L; +R5.H = LSHIFT R5.L BY R6.L; +//rh6 = lshift (rl6 by rl6); +R7.H = LSHIFT R7.L BY R6.L; +CHECKREG r0, 0x00019001; +CHECKREG r1, 0x00019001; +CHECKREG r2, 0x00019002; +CHECKREG r3, 0x00019003; +CHECKREG r4, 0x00019004; +CHECKREG r5, 0x00019005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00019007; + +imm32 r0, 0x0000a001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000a002; +imm32 r3, 0x0000a003; +imm32 r4, 0x0000a004; +imm32 r5, 0x0000a005; +imm32 r6, 0x0000a006; +R7.L = -16; +R0.H = LSHIFT R0.L BY R7.L; +R1.H = LSHIFT R1.L BY R7.L; +R2.H = LSHIFT R2.L BY R7.L; +R3.H = LSHIFT R3.L BY R7.L; +R4.H = LSHIFT R4.L BY R7.L; +R5.H = LSHIFT R5.L BY R7.L; +R6.H = LSHIFT R6.L BY R7.L; +R7.H = LSHIFT R7.L BY R7.L; +CHECKREG r0, 0x0000a001; +CHECKREG r1, 0x0000a001; +CHECKREG r2, 0x0000a002; +CHECKREG r3, 0x0000a003; +CHECKREG r4, 0x0000a004; +CHECKREG r5, 0x0000a005; +CHECKREG r6, 0x0000a006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +R4.L = -1; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = LSHIFT R0.H BY R4.L; +R1.H = LSHIFT R1.H BY R4.L; +R2.H = LSHIFT R2.H BY R4.L; +R3.H = LSHIFT R3.H BY R4.L; +//rh4 = lshift (rh4 by rl4); +R5.H = LSHIFT R5.H BY R4.L; +R6.H = LSHIFT R6.H BY R4.L; +R7.H = LSHIFT R7.H BY R4.L; +CHECKREG r0, 0x40000000; +CHECKREG r1, 0x40000000; +CHECKREG r2, 0x40010000; +CHECKREG r3, 0x40010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0x40020000; +CHECKREG r6, 0x40030000; +CHECKREG r7, 0x40030000; + +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +R5.L = -1; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = LSHIFT R0.H BY R5.L; +R1.H = LSHIFT R1.H BY R5.L; +R2.H = LSHIFT R2.H BY R5.L; +R3.H = LSHIFT R3.H BY R5.L; +R4.H = LSHIFT R4.H BY R5.L; +//rh5 = lshift (rh5 by rl5); +R6.H = LSHIFT R6.H BY R5.L; +R7.H = LSHIFT R7.H BY R5.L; +CHECKREG r0, 0x40000000; +CHECKREG r1, 0x40000000; +CHECKREG r2, 0x40010000; +CHECKREG r3, 0x40010000; +CHECKREG r4, 0x40020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0x40030000; +CHECKREG r7, 0x40030000; + + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030000; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = LSHIFT R0.H BY R6.L; +R1.L = LSHIFT R1.H BY R6.L; +R2.L = LSHIFT R2.H BY R6.L; +R3.L = LSHIFT R3.H BY R6.L; +R4.L = LSHIFT R4.H BY R6.L; +R5.L = LSHIFT R5.H BY R6.L; +//rl6 = lshift (rh6 by rl6); +R7.L = LSHIFT R7.H BY R6.L; +CHECKREG r0, 0xd0010001; +CHECKREG r1, 0xd0010001; +CHECKREG r2, 0xd0020001; +CHECKREG r3, 0xd0030001; +CHECKREG r4, 0xd0040001; +CHECKREG r5, 0xd0050001; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0xd0070001; + +imm32 r0, 0xe0010000; +imm32 r1, 0xe0010000; +imm32 r2, 0xe0020000; +imm32 r3, 0xe0030000; +imm32 r4, 0xe0040000; +imm32 r5, 0xe0050000; +imm32 r6, 0xe0060000; +R7.L = -16; +R0.H = LSHIFT R0.H BY R7.L; +R1.H = LSHIFT R1.H BY R7.L; +R2.H = LSHIFT R2.H BY R7.L; +R3.H = LSHIFT R3.H BY R7.L; +R4.H = LSHIFT R4.H BY R7.L; +R5.H = LSHIFT R5.H BY R7.L; +R6.H = LSHIFT R6.H BY R7.L; +//rh7 = lshift (rh7 by rl7); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +//CHECKREG r7, -16; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_lhalf_rp.s b/sim/testsuite/bfin/c_dsp32shift_lhalf_rp.s new file mode 100644 index 0000000..45fa6a0 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_lhalf_rp.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_lhalf_rp/c_dsp32shift_lhalf_rp.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +//rl0 = lshift (rl0 by rl0); +R1.L = LSHIFT R1.L BY R0.L; +R2.L = LSHIFT R2.L BY R0.L; +R3.L = LSHIFT R3.L BY R0.L; +R4.L = LSHIFT R4.L BY R0.L; +R5.L = LSHIFT R5.L BY R0.L; +R6.L = LSHIFT R6.L BY R0.L; +R7.L = LSHIFT R7.L BY R0.L; +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x00001001; +R1.L = -1; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = LSHIFT R0.L BY R1.L; +//rl1 = lshift (rl1 by rl1); +R2.L = LSHIFT R2.L BY R1.L; +R3.L = LSHIFT R3.L BY R1.L; +R4.L = LSHIFT R4.L BY R1.L; +R5.L = LSHIFT R5.L BY R1.L; +R6.L = LSHIFT R6.L BY R1.L; +R7.L = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0x00000800; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00001001; +CHECKREG r3, 0x00001801; +CHECKREG r4, 0x00002002; +CHECKREG r5, 0x00002802; +CHECKREG r6, 0x00003003; +CHECKREG r7, 0x00003803; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +R2.L = -15; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = LSHIFT R0.L BY R2.L; +R1.L = LSHIFT R1.L BY R2.L; +//rl2 = lshift (rl2 by rl2); +R3.L = LSHIFT R3.L BY R2.L; +R4.L = LSHIFT R4.L BY R2.L; +R5.L = LSHIFT R5.L BY R2.L; +R6.L = LSHIFT R6.L BY R2.L; +R7.L = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r2, 0x00002002; +R3.L = -16; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = LSHIFT R0.L BY R3.L; +R1.L = LSHIFT R1.L BY R3.L; +R2.L = LSHIFT R2.L BY R3.L; +//rl3 = lshift (rl3 by rl3); +R4.L = LSHIFT R4.L BY R3.L; +R5.L = LSHIFT R5.L BY R3.L; +R6.L = LSHIFT R6.L BY R3.L; +R7.L = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R0.L; +R1.L = LSHIFT R1.H BY R0.L; +R2.L = LSHIFT R2.H BY R0.L; +R3.L = LSHIFT R3.H BY R0.L; +R4.L = LSHIFT R4.H BY R0.L; +R5.L = LSHIFT R5.H BY R0.L; +R6.L = LSHIFT R6.H BY R0.L; +R7.L = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x10010000; +R1.L = -1; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = LSHIFT R0.H BY R1.L; +//rl1 = lshift (rh1 by rl1); +R2.L = LSHIFT R2.H BY R1.L; +R3.L = LSHIFT R3.H BY R1.L; +R4.L = LSHIFT R4.H BY R1.L; +R5.L = LSHIFT R5.H BY R1.L; +R6.L = LSHIFT R6.H BY R1.L; +R7.L = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x10010800; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x20021001; +CHECKREG r3, 0x30031801; +CHECKREG r4, 0x40042002; +CHECKREG r5, 0x50052802; +CHECKREG r6, 0x60063003; +CHECKREG r7, 0x70073803; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +R2.L = -15; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010001; +imm32 r1, 0x10010001; +imm32 r2, 0x20020002; +R3.L = -16; +imm32 r4, 0x40040004; +imm32 r5, 0x50050005; +imm32 r6, 0x60060006; +imm32 r7, 0x70070007; +R0.L = LSHIFT R0.H BY R3.L; +R1.L = LSHIFT R1.H BY R3.L; +R2.L = LSHIFT R2.H BY R3.L; +//rl3 = lshift (rh3 by rl3); +R4.L = LSHIFT R4.H BY R3.L; +R5.L = LSHIFT R5.H BY R3.L; +R6.L = LSHIFT R6.H BY R3.L; +R7.L = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R4.L; +R1.H = LSHIFT R1.L BY R4.L; +R2.H = LSHIFT R2.L BY R4.L; +R3.H = LSHIFT R3.L BY R4.L; +//rh4 = lshift (rl4 by rl4); +R5.H = LSHIFT R5.L BY R4.L; +R6.H = LSHIFT R6.L BY R4.L; +R7.H = LSHIFT R7.L BY R4.L; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +R5.L = -1; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R5.L; +R1.H = LSHIFT R1.L BY R5.L; +R2.H = LSHIFT R2.L BY R5.L; +R3.H = LSHIFT R3.L BY R5.L; +R4.H = LSHIFT R4.L BY R5.L; +//rh5 = lshift (rl5 by rl5); +R6.H = LSHIFT R6.L BY R5.L; +R7.H = LSHIFT R7.L BY R5.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00010002; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0x00030006; +CHECKREG r7, 0x00030007; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r1, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +R6.L = -15; +imm32 r7, 0x00007007; +R0.H = LSHIFT R0.L BY R6.L; +R1.H = LSHIFT R1.L BY R6.L; +R2.H = LSHIFT R2.L BY R6.L; +R3.H = LSHIFT R3.L BY R6.L; +R4.H = LSHIFT R4.L BY R6.L; +R5.H = LSHIFT R5.L BY R6.L; +//rh6 = lshift (rl6 by rl6); +R7.H = LSHIFT R7.L BY R6.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00007007; + +imm32 r0, 0x00001001; +imm32 r1, 0x00002001; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +R7.L = -16; +R0.H = LSHIFT R0.L BY R7.L; +R1.H = LSHIFT R1.L BY R7.L; +R2.H = LSHIFT R2.L BY R7.L; +R3.H = LSHIFT R3.L BY R7.L; +R4.H = LSHIFT R4.L BY R7.L; +R5.H = LSHIFT R5.L BY R7.L; +R6.H = LSHIFT R6.L BY R7.L; +R7.H = LSHIFT R7.L BY R7.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002001; +CHECKREG r2, 0x00002002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +CHECKREG r6, 0x00006006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +R4.L = -1; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R4.L; +R1.H = LSHIFT R1.H BY R4.L; +R2.H = LSHIFT R2.H BY R4.L; +R3.H = LSHIFT R3.H BY R4.L; +//rh4 = lshift (rh4 by rl4); +R5.H = LSHIFT R5.H BY R4.L; +R6.H = LSHIFT R6.H BY R4.L; +R7.H = LSHIFT R7.H BY R4.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00010000; +CHECKREG r3, 0x00010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0x00020000; +CHECKREG r6, 0x00030000; +CHECKREG r7, 0x00030000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +R5.L = -1; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.H = LSHIFT R0.H BY R5.L; +R1.H = LSHIFT R1.H BY R5.L; +R2.H = LSHIFT R2.H BY R5.L; +R3.H = LSHIFT R3.H BY R5.L; +R4.H = LSHIFT R4.H BY R5.L; +//rh5 = lshift (rh5 by rl5); +R6.H = LSHIFT R6.H BY R5.L; +R7.H = LSHIFT R7.H BY R5.L; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x08000000; +CHECKREG r2, 0x10010000; +CHECKREG r3, 0x18010000; +CHECKREG r4, 0x20020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0x30030000; +CHECKREG r7, 0x38030000; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +R6.L = -15; +imm32 r7, 0x70070000; +R0.L = LSHIFT R0.H BY R6.L; +R1.L = LSHIFT R1.H BY R6.L; +R2.L = LSHIFT R2.H BY R6.L; +R3.L = LSHIFT R3.H BY R6.L; +R4.L = LSHIFT R4.H BY R6.L; +R5.L = LSHIFT R5.H BY R6.L; +//rl6 = lshift (rh6 by rl6); +R7.L = LSHIFT R7.H BY R6.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r2, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +R7.L = -16; +R0.H = LSHIFT R0.H BY R7.L; +R1.H = LSHIFT R1.H BY R7.L; +R2.H = LSHIFT R2.H BY R7.L; +R3.H = LSHIFT R3.H BY R7.L; +R4.H = LSHIFT R4.H BY R7.L; +R5.H = LSHIFT R5.H BY R7.L; +R6.H = LSHIFT R6.H BY R7.L; +//rh7 = lshift (rh7 by rl7); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +//CHECKREG r7, -16; +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_lhh.s b/sim/testsuite/bfin/c_dsp32shift_lhh.s new file mode 100644 index 0000000..4722987 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_lhh.s @@ -0,0 +1,311 @@ +//Original:/testcases/core/c_dsp32shift_lhh/c_dsp32shift_lhh.dsp +// Spec Reference: dsp32shift lshift/lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift/lshift : = (half reg) +// d_reg = lshift/lshift (d BY d_lo) +// Rx by RLx +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1 = LSHIFT R0 BY R0.L (V); +R2 = LSHIFT R1 BY R0.L (V); +R3 = LSHIFT R2 BY R0.L (V); +R4 = LSHIFT R3 BY R0.L (V); +R5 = LSHIFT R4 BY R0.L (V); +R6 = LSHIFT R5 BY R0.L (V); +R7 = LSHIFT R6 BY R0.L (V); +R0 = LSHIFT R7 BY R0.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1.L = 5; +R2 = LSHIFT R0 BY R1.L (V); +R3 = LSHIFT R1 BY R1.L (V); +R4 = LSHIFT R2 BY R1.L (V); +R5 = LSHIFT R3 BY R1.L (V); +R6 = LSHIFT R4 BY R1.L (V); +R7 = LSHIFT R5 BY R1.L (V); +R0 = LSHIFT R6 BY R1.L (V); +R1 = LSHIFT R7 BY R1.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2 = 15; +R3 = LSHIFT R0 BY R2.L (V); +R4 = LSHIFT R1 BY R2.L (V); +R5 = LSHIFT R2 BY R2.L (V); +R6 = LSHIFT R3 BY R2.L (V); +R7 = LSHIFT R4 BY R2.L (V); +R0 = LSHIFT R5 BY R2.L (V); +R1 = LSHIFT R6 BY R2.L (V); +R2 = LSHIFT R7 BY R2.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R3.L = 16; +R4 = LSHIFT R0 BY R3.L (V); +R5 = LSHIFT R1 BY R3.L (V); +R6 = LSHIFT R2 BY R3.L (V); +R7 = LSHIFT R3 BY R3.L (V); +R0 = LSHIFT R4 BY R3.L (V); +R1 = LSHIFT R5 BY R3.L (V); +R2 = LSHIFT R6 BY R3.L (V); +R3 = LSHIFT R7 BY R3.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R4.L = -1; +R0 = LSHIFT R0 BY R4.L (V); +R1 = LSHIFT R1 BY R4.L (V); +R2 = LSHIFT R2 BY R4.L (V); +R3 = LSHIFT R3 BY R4.L (V); +R4 = LSHIFT R4 BY R4.L (V); +R5 = LSHIFT R5 BY R4.L (V); +R6 = LSHIFT R6 BY R4.L (V); +R7 = LSHIFT R7 BY R4.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5.L = -6; +R6 = LSHIFT R0 BY R5.L (V); +R7 = LSHIFT R1 BY R5.L (V); +R0 = LSHIFT R2 BY R5.L (V); +R1 = LSHIFT R3 BY R5.L (V); +R2 = LSHIFT R4 BY R5.L (V); +R3 = LSHIFT R5 BY R5.L (V); +R4 = LSHIFT R6 BY R5.L (V); +R5 = LSHIFT R7 BY R5.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R6.L = -15; +R7 = LSHIFT R0 BY R6.L (V); +R0 = LSHIFT R1 BY R6.L (V); +R1 = LSHIFT R2 BY R6.L (V); +R2 = LSHIFT R3 BY R6.L (V); +R3 = LSHIFT R4 BY R6.L (V); +R4 = LSHIFT R5 BY R6.L (V); +R5 = LSHIFT R6 BY R6.L (V); +R6 = LSHIFT R7 BY R6.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7.L = -16; +R0 = LSHIFT R0 BY R7.L (V); +R1 = LSHIFT R1 BY R7.L (V); +R2 = LSHIFT R2 BY R7.L (V); +R3 = LSHIFT R3 BY R7.L (V); +R4 = LSHIFT R4 BY R7.L (V); +R5 = LSHIFT R5 BY R7.L (V); +R6 = LSHIFT R6 BY R7.L (V); +R7 = LSHIFT R7 BY R7.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0.L = 4; +//r0 = lshift/lshift (r0 by rl0); +R1 = LSHIFT R1 BY R0.L (V); +R2 = LSHIFT R2 BY R0.L (V); +R3 = LSHIFT R3 BY R0.L (V); +R4 = LSHIFT R4 BY R0.L (V); +R5 = LSHIFT R5 BY R0.L (V); +R6 = LSHIFT R6 BY R0.L (V); +R7 = LSHIFT R7 BY R0.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1.L = 6; +R0 = LSHIFT R0 BY R1.L (V); +//r1 = lshift/lshift (r1 by rl1); +R2 = LSHIFT R2 BY R1.L (V); +R3 = LSHIFT R3 BY R1.L (V); +R4 = LSHIFT R4 BY R1.L (V); +R5 = LSHIFT R5 BY R1.L (V); +R6 = LSHIFT R6 BY R1.L (V); +R7 = LSHIFT R7 BY R1.L (V); + + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 15; +R0 = LSHIFT R0 BY R2.L (V); +R1 = LSHIFT R1 BY R2.L (V); +//r2 = lshift/lshift (r2 by rl2); +R3 = LSHIFT R3 BY R2.L (V); +R4 = LSHIFT R4 BY R2.L (V); +R5 = LSHIFT R5 BY R2.L (V); +R6 = LSHIFT R6 BY R2.L (V); +R7 = LSHIFT R7 BY R2.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R3.L = 16; +R0 = LSHIFT R0 BY R3.L (V); +R1 = LSHIFT R1 BY R3.L (V); +R2 = LSHIFT R2 BY R3.L (V); +//r3 = lshift/lshift (r3 by rl3); +R4 = LSHIFT R4 BY R3.L (V); +R5 = LSHIFT R5 BY R3.L (V); +R6 = LSHIFT R6 BY R3.L (V); +R7 = LSHIFT R7 BY R3.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R4.L = -9; +R0 = LSHIFT R0 BY R4.L (V); +R1 = LSHIFT R1 BY R4.L (V); +R2 = LSHIFT R2 BY R4.L (V); +R3 = LSHIFT R3 BY R4.L (V); +//r4 = lshift/lshift (r4 by rl4); +R5 = LSHIFT R5 BY R4.L (V); +R6 = LSHIFT R6 BY R4.L (V); +R7 = LSHIFT R7 BY R4.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5.L = -14; +R0 = LSHIFT R0 BY R5.L (V); +R1 = LSHIFT R1 BY R5.L (V); +R2 = LSHIFT R2 BY R5.L (V); +R3 = LSHIFT R3 BY R5.L (V); +R4 = LSHIFT R4 BY R5.L (V); +//r5 = lshift/lshift (r5 by rl5); +R6 = LSHIFT R6 BY R5.L (V); +R7 = LSHIFT R7 BY R5.L (V); + + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R6.L = -15; +R0 = LSHIFT R0 BY R6.L (V); +R1 = LSHIFT R1 BY R6.L (V); +R2 = LSHIFT R2 BY R6.L (V); +R3 = LSHIFT R3 BY R6.L (V); +R4 = LSHIFT R4 BY R6.L (V); +R5 = LSHIFT R5 BY R6.L (V); +//r6 = lshift/lshift (r6 by rl6); +R7 = LSHIFT R7 BY R6.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7.L = -16; +R0 = LSHIFT R0 BY R7.L (V); +R1 = LSHIFT R1 BY R7.L (V); +R2 = LSHIFT R2 BY R7.L (V); +R3 = LSHIFT R3 BY R7.L (V); +R4 = LSHIFT R4 BY R7.L (V); +R5 = LSHIFT R5 BY R7.L (V); +R6 = LSHIFT R6 BY R7.L (V); +R7 = LSHIFT R7 BY R7.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_lmix.s b/sim/testsuite/bfin/c_dsp32shift_lmix.s new file mode 100644 index 0000000..2a3c360 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_lmix.s @@ -0,0 +1,136 @@ +//Original:/testcases/core/c_dsp32shift_lmix/c_dsp32shift_lmix.dsp +// Spec Reference: dsp32shift lshift: mix +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// lshift : positive data, count (+)=left (half reg) +imm32 r0, 0x00010001; +imm32 r1, 1; +imm32 r2, 0x00020002; +imm32 r3, 2; +R4.H = LSHIFT R0.H BY R1.L; +R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x00020002 */ +R5.H = LSHIFT R2.H BY R3.L; +R5.L = LSHIFT R2.L BY R3.L; /* r5 = 0x00080008 */ +R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */ +R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */ +CHECKREG r4, 0x00020002; +CHECKREG r5, 0x00080008; +CHECKREG r6, 0x00020002; +CHECKREG r7, 0x00080008; + +// lshift : (full reg) +imm32 r1, 3; +imm32 r3, 4; +R6 = LSHIFT R0 BY R1.L; /* r6 = 0x00080010 */ +R7 = LSHIFT R2 BY R3.L; +CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ +CHECKREG r7, 0x00200020; + +A0 = 0; +A0.L = R0.L; +A0.H = R0.H; +A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00080008 */ +R5 = A0.w; /* r5 = 0x00080008 */ +CHECKREG r5, 0x00080008; + +imm32 r4, 0x30000003; +imm32 r1, 1; +R6 = LSHIFT R4 BY R1.L; /* r5 = 0x60000006 */ +imm32 r1, 2; +R7 = LSHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */ +CHECKREG r6, 0x60000006; +CHECKREG r7, 0xc000000c; + + +// lshift : count (-)=right (half reg) +imm32 r0, 0x10001000; +imm32 r1, -1; +imm32 r2, 0x10001000; +imm32 r3, -2; +R4.H = LSHIFT R0.H BY R1.L; +R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x08000800 */ +R5.H = LSHIFT R2.H BY R3.L; +R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x04000400 */ +R6 = LSHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */ +R7 = LSHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */ +CHECKREG r4, 0x08000800; +CHECKREG r5, 0x04000400; +CHECKREG r6, 0x08000800; +CHECKREG r7, 0x04000400; + +// lshift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = LSHIFT R0 BY R1.L; /* r6 = 0x02000200 */ +R7 = LSHIFT R2 BY R3.L; /* r7 = 0x01000100 */ +CHECKREG r6, 0x02000200; +CHECKREG r7, 0x01000100; + +// NEGATIVE +// lshift : NEGATIVE data, count (+)=left (half reg) +imm32 r0, 0xc00f800f; +imm32 r1, 1; +imm32 r2, 0xe00fe00f; +imm32 r3, 2; +R4.H = LSHIFT R0.H BY R1.L; +R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x801e001e */ +R5.H = LSHIFT R2.H BY R3.L; +R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x803c803c */ +CHECKREG r4, 0x801e001e; +CHECKREG r5, 0x803c803c; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +imm32 r1, 4; +imm32 r3, 5; +R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */ +R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xf80fe00f; +imm32 r2, 0xfc0fe00f; +R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */ +R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + + + +// lshift : NEGATIVE data, count (-)=right (half reg) Working ok +imm32 r0, 0x80f080f0; +imm32 r1, -1; +imm32 r2, 0x80f080f0; +imm32 r3, -2; +R4.H = LSHIFT R0.H BY R1.L; +R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x40784078 */ +R5.H = LSHIFT R2.H BY R3.L; +R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x203c203c */ +CHECKREG r4, 0x40784078; +CHECKREG r5, 0x203c203c; +R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x40784078 */ +R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x203c203c */ +CHECKREG r6, 0x40784078; +CHECKREG r7, 0x203c203c; + +// lshift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = LSHIFT R0 BY R1.L; /* r6 = 0x101e101e */ +R7 = LSHIFT R2 BY R3.L; /* r7 = 0x080f080f */ +CHECKREG r6, 0x101e101e; +CHECKREG r7, 0x080f080f; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_ones.s b/sim/testsuite/bfin/c_dsp32shift_ones.s new file mode 100644 index 0000000..4097777 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_ones.s @@ -0,0 +1,214 @@ +//Original:/testcases/core/c_dsp32shift_ones/c_dsp32shift_ones.dsp +// Spec Reference: dsp32shift ones +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x88880000; +imm32 r1, 0x34560001; +imm32 r2, 0x08000002; +imm32 r3, 0x08000003; +imm32 r4, 0x08000004; +imm32 r5, 0x08000005; +imm32 r6, 0x08000006; +imm32 r7, 0x08000007; +R7.L = ONES R0; +R1.L = ONES R0; +R2.L = ONES R0; +R3.L = ONES R0; +R4.L = ONES R0; +R5.L = ONES R0; +R6.L = ONES R0; +R0.L = ONES R0; +CHECKREG r1, 0x34560004; +CHECKREG r0, 0x88880004; +CHECKREG r2, 0x08000004; +CHECKREG r3, 0x08000004; +CHECKREG r4, 0x08000004; +CHECKREG r5, 0x08000004; +CHECKREG r6, 0x08000004; +CHECKREG r7, 0x08000004; + +imm32 r0, 0x9999d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R0.L = ONES R1; +R7.L = ONES R1; +R2.L = ONES R1; +R3.L = ONES R1; +R4.L = ONES R1; +R5.L = ONES R1; +R6.L = ONES R1; +R1.L = ONES R1; +CHECKREG r0, 0x99990001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + + +imm32 r0, 0xaaaae001; +imm32 r1, 0x0000e001; +imm32 r2, 0xaaaa000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.L = ONES R2; +R1.L = ONES R2; +R7.L = ONES R2; +R3.L = ONES R2; +R4.L = ONES R2; +R5.L = ONES R2; +R6.L = ONES R2; +R2.L = ONES R2; +CHECKREG r0, 0xAAAA000C; +CHECKREG r1, 0x0000000C; +CHECKREG r2, 0xAAAA000C; +CHECKREG r3, 0x0000000C; +CHECKREG r4, 0x0000000C; +CHECKREG r5, 0x0000000C; +CHECKREG r6, 0x0000000C; +CHECKREG r7, 0x0000000C; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0xbbbb0010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = ONES R3; +R1.L = ONES R3; +R2.L = ONES R3; +R7.L = ONES R3; +R4.L = ONES R3; +R5.L = ONES R3; +R6.L = ONES R3; +R3.L = ONES R3; +CHECKREG r0, 0x0000000D; +CHECKREG r1, 0x0000000D; +CHECKREG r2, 0x0000000D; +CHECKREG r3, 0xBBBB000D; +CHECKREG r4, 0x0000000D; +CHECKREG r5, 0x0000000D; +CHECKREG r6, 0x0000000D; +CHECKREG r7, 0x0000000D; + +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0xcccc0000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ONES R4; +R1.L = ONES R4; +R2.L = ONES R4; +R3.L = ONES R4; +R7.L = ONES R4; +R5.L = ONES R4; +R6.L = ONES R4; +R4.L = ONES R4; +CHECKREG r0, 0x00000008; +CHECKREG r1, 0x00010008; +CHECKREG r2, 0x00020008; +CHECKREG r3, 0x00030008; +CHECKREG r4, 0xCCCC0008; +CHECKREG r5, 0x00050008; +CHECKREG r6, 0x00060008; +CHECKREG r7, 0x00070008; + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xaddd0000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ONES R5; +R1.L = ONES R5; +R2.L = ONES R5; +R3.L = ONES R5; +R4.L = ONES R5; +R7.L = ONES R5; +R6.L = ONES R5; +R5.L = ONES R5; +CHECKREG r0, 0xA001000B; +CHECKREG r1, 0xA001000B; +CHECKREG r2, 0xA002000B; +CHECKREG r3, 0xA003000B; +CHECKREG r4, 0xA004000B; +CHECKREG r5, 0xADDD000B; +CHECKREG r6, 0xA006000B; +CHECKREG r7, 0xA007000B; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xeeee0000; +imm32 r7, 0xb0070000; +R0.L = ONES R6; +R1.L = ONES R6; +R2.L = ONES R6; +R3.L = ONES R6; +R4.L = ONES R6; +R5.L = ONES R6; +R7.L = ONES R6; +R6.L = ONES R6; +CHECKREG r0, 0xB001000C; +CHECKREG r1, 0xB001000C; +CHECKREG r2, 0xB002000C; +CHECKREG r3, 0xB003000C; +CHECKREG r4, 0xB004000C; +CHECKREG r5, 0xB005000C; +CHECKREG r6, 0xEEEE000C; +CHECKREG r7, 0xB007000C; + +imm32 r0, 0xd0010001; +imm32 r1, 0xd0010002; +imm32 r2, 0xd0020003; +imm32 r3, 0xd0030014; +imm32 r4, 0xd0040005; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060007; +imm32 r7, 0xffff0000; +R0.L = ONES R7; +R1.L = ONES R7; +R2.L = ONES R7; +R3.L = ONES R7; +R4.L = ONES R7; +R5.L = ONES R7; +R6.L = ONES R7; +R7.L = ONES R7; + +CHECKREG r0, 0xD0010010; +CHECKREG r1, 0xD0010010; +CHECKREG r2, 0xD0020010; +CHECKREG r3, 0xD0030010; +CHECKREG r4, 0xD0040010; +CHECKREG r5, 0xD0050010; +CHECKREG r6, 0xD0060010; +CHECKREG r7, 0xFFFF0010; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_pack.s b/sim/testsuite/bfin/c_dsp32shift_pack.s new file mode 100644 index 0000000..5647309 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_pack.s @@ -0,0 +1,411 @@ +//Original:/testcases/core/c_dsp32shift_pack/c_dsp32shift_pack.dsp +// Spec Reference: dsp32shift pack +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x01230000; +imm32 r1, 0x02345678; +imm32 r2, 0x03456789; +imm32 r3, 0x0456789a; +imm32 r4, 0x056789ab; +imm32 r5, 0x06789abc; +imm32 r6, 0x0789abcd; +imm32 r7, 0x089abcde; +R1 = PACK( R0.L , R0.L ); +R2 = PACK( R1.L , R0.H ); +R3 = PACK( R2.H , R0.L ); +R4 = PACK( R3.H , R0.H ); +R5 = PACK( R4.L , R0.L ); +R6 = PACK( R5.L , R0.H ); +R7 = PACK( R6.H , R0.L ); +R0 = PACK( R7.H , R0.H ); +CHECKREG r1, 0x00000000; +CHECKREG r0, 0x00000123; +CHECKREG r2, 0x00000123; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000123; +CHECKREG r5, 0x01230000; +CHECKREG r6, 0x00000123; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x11230001; +imm32 r1, 0x12345678; +imm32 r2, 0x1bcdef12; +imm32 r3, 0x1456789a; +imm32 r4, 0x1cdef012; +imm32 r5, 0x1456789a; +imm32 r6, 0x1789abcd; +imm32 r7, 0x189abcde; +R2 = PACK( R0.L , R1.L ); +R3 = PACK( R1.L , R1.H ); +R4 = PACK( R2.H , R1.L ); +R5 = PACK( R3.H , R1.H ); +R6 = PACK( R4.L , R1.L ); +R7 = PACK( R5.L , R1.H ); +R0 = PACK( R6.H , R1.L ); +R1 = PACK( R7.H , R1.H ); +CHECKREG r0, 0x56785678; +CHECKREG r1, 0x12341234; +CHECKREG r2, 0x00015678; +CHECKREG r3, 0x56781234; +CHECKREG r4, 0x00015678; +CHECKREG r5, 0x56781234; +CHECKREG r6, 0x56785678; +CHECKREG r7, 0x12341234; + +imm32 r0, 0x20230002; +imm32 r1, 0x21345678; +imm32 r2, 0x22456789; +imm32 r3, 0x2356789a; +imm32 r4, 0x246789ab; +imm32 r5, 0x25789abc; +imm32 r6, 0x2689abcd; +imm32 r7, 0x279abcde; +R3 = PACK( R0.L , R2.L ); +R4 = PACK( R1.L , R2.H ); +R5 = PACK( R2.H , R2.L ); +R6 = PACK( R3.H , R2.H ); +R7 = PACK( R4.L , R2.L ); +R0 = PACK( R5.L , R2.H ); +R1 = PACK( R6.H , R2.L ); +R2 = PACK( R7.H , R2.H ); +CHECKREG r0, 0x67892245; +CHECKREG r1, 0x00026789; +CHECKREG r2, 0x22452245; +CHECKREG r3, 0x00026789; +CHECKREG r4, 0x56782245; +CHECKREG r5, 0x22456789; +CHECKREG r6, 0x00022245; +CHECKREG r7, 0x22456789; + +imm32 r0, 0x31230003; +imm32 r1, 0x31345678; +imm32 r2, 0x31456789; +imm32 r3, 0x3156789a; +imm32 r4, 0x316789ab; +imm32 r5, 0x31789abc; +imm32 r6, 0x3189abcd; +imm32 r7, 0x311abcde; +R4 = PACK( R0.L , R3.L ); +R5 = PACK( R1.L , R3.H ); +R6 = PACK( R2.H , R3.L ); +R7 = PACK( R3.H , R3.H ); +R0 = PACK( R4.L , R3.L ); +R1 = PACK( R5.L , R3.H ); +R2 = PACK( R6.H , R3.L ); +R3 = PACK( R7.H , R3.H ); +CHECKREG r0, 0x789A789A; +CHECKREG r1, 0x31563156; +CHECKREG r2, 0x3145789A; +CHECKREG r3, 0x31563156; +CHECKREG r4, 0x0003789A; +CHECKREG r5, 0x56783156; +CHECKREG r6, 0x3145789A; +CHECKREG r7, 0x31563156; + +imm32 r0, 0x41230004; +imm32 r1, 0x42345678; +imm32 r2, 0x43456789; +imm32 r3, 0x4456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x46789abc; +imm32 r6, 0x4789abcd; +imm32 r7, 0x489abcde; +R0 = PACK( R0.L , R4.L ); +R1 = PACK( R1.L , R4.H ); +R2 = PACK( R2.H , R4.L ); +R3 = PACK( R3.H , R4.H ); +R4 = PACK( R4.L , R4.L ); +R5 = PACK( R5.L , R4.H ); +R6 = PACK( R6.H , R4.L ); +R7 = PACK( R7.H , R4.H ); +CHECKREG r0, 0x000489AB; +CHECKREG r1, 0x56784567; +CHECKREG r2, 0x434589AB; +CHECKREG r3, 0x44564567; +CHECKREG r4, 0x89AB89AB; +CHECKREG r5, 0x9ABC89AB; +CHECKREG r6, 0x478989AB; +CHECKREG r7, 0x489A89AB; + +imm32 r0, 0x51230005; +imm32 r1, 0x52345678; +imm32 r2, 0x53456789; +imm32 r3, 0x5456789a; +imm32 r4, 0x556789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x5789abcd; +imm32 r7, 0x589abcde; +R6 = PACK( R0.L , R5.L ); +R7 = PACK( R1.L , R5.H ); +R0 = PACK( R2.H , R5.L ); +R1 = PACK( R3.H , R5.H ); +R2 = PACK( R4.L , R5.L ); +R3 = PACK( R5.L , R5.H ); +R4 = PACK( R6.H , R5.L ); +R5 = PACK( R7.H , R5.H ); +CHECKREG r0, 0x53459ABC; +CHECKREG r1, 0x54565678; +CHECKREG r2, 0x89AB9ABC; +CHECKREG r3, 0x9ABC5678; +CHECKREG r4, 0x00059ABC; +CHECKREG r5, 0x56785678; +CHECKREG r6, 0x00059ABC; +CHECKREG r7, 0x56785678; + +imm32 r0, 0x61230006; +imm32 r1, 0x62345678; +imm32 r2, 0x63456789; +imm32 r3, 0x6456789a; +imm32 r4, 0x656789ab; +imm32 r5, 0x66789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x689abcde; +R7 = PACK( R0.L , R6.L ); +R0 = PACK( R1.L , R6.H ); +R1 = PACK( R2.H , R6.L ); +R2 = PACK( R3.H , R6.H ); +R3 = PACK( R4.L , R6.L ); +R4 = PACK( R5.L , R6.H ); +R5 = PACK( R6.H , R6.L ); +R6 = PACK( R7.H , R6.H ); +CHECKREG r0, 0x56786789; +CHECKREG r1, 0x6345ABCD; +CHECKREG r2, 0x64566789; +CHECKREG r3, 0x89ABABCD; +CHECKREG r4, 0x9ABC6789; +CHECKREG r5, 0x6789ABCD; +CHECKREG r6, 0x00066789; +CHECKREG r7, 0x0006ABCD; + +imm32 r0, 0x71230007; +imm32 r1, 0x72345678; +imm32 r2, 0x73456789; +imm32 r3, 0x7456789a; +imm32 r4, 0x756789ab; +imm32 r5, 0x76789abc; +imm32 r6, 0x7789abcd; +imm32 r7, 0x789abcde; +R0 = PACK( R0.L , R7.L ); +R1 = PACK( R1.L , R7.H ); +R2 = PACK( R2.H , R7.L ); +R3 = PACK( R3.H , R7.H ); +R4 = PACK( R4.L , R7.L ); +R5 = PACK( R5.L , R7.H ); +R6 = PACK( R6.H , R7.L ); +R7 = PACK( R7.H , R7.H ); +CHECKREG r0, 0x0007BCDE; +CHECKREG r1, 0x5678789A; +CHECKREG r2, 0x7345BCDE; +CHECKREG r3, 0x7456789A; +CHECKREG r4, 0x89ABBCDE; +CHECKREG r5, 0x9ABC789A; +CHECKREG r6, 0x7789BCDE; +CHECKREG r7, 0x789A789A; + +imm32 r0, 0x81230008; +imm32 r1, 0x82345678; +imm32 r2, 0x83456789; +imm32 r3, 0x8456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x8789abcd; +imm32 r7, 0x889abcde; +R0 = PACK( R0.L , R0.L ); +R1 = PACK( R1.L , R0.H ); +R2 = PACK( R2.H , R0.L ); +R3 = PACK( R3.H , R0.H ); +R4 = PACK( R4.L , R0.L ); +R5 = PACK( R5.L , R0.H ); +R6 = PACK( R6.H , R0.L ); +R7 = PACK( R7.H , R0.H ); +CHECKREG r0, 0x00080008; +CHECKREG r1, 0x56780008; +CHECKREG r2, 0x83450008; +CHECKREG r3, 0x84560008; +CHECKREG r4, 0x89AB0008; +CHECKREG r5, 0x9ABC0008; +CHECKREG r6, 0x87890008; +CHECKREG r7, 0x889A0008; + +imm32 r0, 0x91230009; +imm32 r1, 0x92345678; +imm32 r2, 0x93456789; +imm32 r3, 0x9456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0x9789abcd; +imm32 r7, 0x989abcde; +R0 = PACK( R0.L , R1.L ); +R1 = PACK( R1.L , R1.H ); +R2 = PACK( R2.H , R1.L ); +R3 = PACK( R3.H , R1.H ); +R4 = PACK( R4.L , R1.L ); +R5 = PACK( R5.L , R1.H ); +R6 = PACK( R6.H , R1.L ); +R7 = PACK( R7.H , R1.H ); +CHECKREG r0, 0x00095678; +CHECKREG r1, 0x56789234; +CHECKREG r2, 0x93459234; +CHECKREG r3, 0x94565678; +CHECKREG r4, 0x89AB9234; +CHECKREG r5, 0x9ABC5678; +CHECKREG r6, 0x97899234; +CHECKREG r7, 0x989A5678; + + +imm32 r0, 0xa123000a; +imm32 r1, 0xa2345678; +imm32 r2, 0xa3456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xa56789ab; +imm32 r5, 0xa6789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xa89abcde; +R0 = PACK( R0.L , R2.L ); +R1 = PACK( R1.L , R2.H ); +R2 = PACK( R2.H , R2.L ); +R3 = PACK( R3.H , R2.H ); +R4 = PACK( R4.L , R2.L ); +R5 = PACK( R5.L , R2.H ); +R6 = PACK( R6.H , R2.L ); +R7 = PACK( R7.H , R2.H ); +CHECKREG r0, 0x000A6789; +CHECKREG r1, 0x5678A345; +CHECKREG r2, 0xA3456789; +CHECKREG r3, 0xA456A345; +CHECKREG r4, 0x89AB6789; +CHECKREG r5, 0x9ABCA345; +CHECKREG r6, 0xA7896789; +CHECKREG r7, 0xA89AA345; + +imm32 r0, 0xb123000b; +imm32 r1, 0xb2345678; +imm32 r2, 0xb3456789; +imm32 r3, 0xb456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xb6789abc; +imm32 r6, 0xb789abcd; +imm32 r7, 0xb89abcde; +R0 = PACK( R0.L , R3.L ); +R1 = PACK( R1.L , R3.H ); +R2 = PACK( R2.H , R3.L ); +R3 = PACK( R3.H , R3.H ); +R4 = PACK( R4.L , R3.L ); +R5 = PACK( R5.L , R3.H ); +R6 = PACK( R6.H , R3.L ); +R7 = PACK( R7.H , R3.H ); +CHECKREG r0, 0x000B789A; +CHECKREG r1, 0x5678B456; +CHECKREG r2, 0xB345789A; +CHECKREG r3, 0xB456B456; +CHECKREG r4, 0x89ABB456; +CHECKREG r5, 0x9ABCB456; +CHECKREG r6, 0xB789B456; +CHECKREG r7, 0xB89AB456; + +imm32 r0, 0xc123000c; +imm32 r1, 0xc2345678; +imm32 r2, 0xc3456789; +imm32 r3, 0xc456789a; +imm32 r4, 0xc56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xc789abcd; +imm32 r7, 0xc89abcde; +R0 = PACK( R0.L , R4.L ); +R1 = PACK( R1.L , R4.H ); +R2 = PACK( R2.H , R4.L ); +R3 = PACK( R3.H , R4.H ); +R4 = PACK( R4.L , R4.L ); +R5 = PACK( R5.L , R4.H ); +R6 = PACK( R6.H , R4.L ); +R7 = PACK( R7.H , R4.H ); +CHECKREG r0, 0x000C89AB; +CHECKREG r1, 0x5678C567; +CHECKREG r2, 0xC34589AB; +CHECKREG r3, 0xC456C567; +CHECKREG r4, 0x89AB89AB; +CHECKREG r5, 0x9ABC89AB; +CHECKREG r6, 0xC78989AB; +CHECKREG r7, 0xC89A89AB; + +imm32 r0, 0xd123000d; +imm32 r1, 0xd2345678; +imm32 r2, 0xd3456789; +imm32 r3, 0xd456789a; +imm32 r4, 0xd56789ab; +imm32 r5, 0xd6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xd89abcde; +R0 = PACK( R0.L , R5.L ); +R1 = PACK( R1.L , R5.H ); +R2 = PACK( R2.H , R5.L ); +R3 = PACK( R3.H , R5.H ); +R4 = PACK( R4.L , R5.L ); +R5 = PACK( R5.L , R5.H ); +R6 = PACK( R6.H , R5.L ); +R7 = PACK( R7.H , R5.H ); +CHECKREG r0, 0x000D9ABC; +CHECKREG r1, 0x5678D678; +CHECKREG r2, 0xD3459ABC; +CHECKREG r3, 0xD456D678; +CHECKREG r4, 0x89AB9ABC; +CHECKREG r5, 0x9ABCD678; +CHECKREG r6, 0xD789D678; +CHECKREG r7, 0xD89A9ABC; + + +imm32 r0, 0xe123000e; +imm32 r1, 0xe2345678; +imm32 r2, 0xe3456789; +imm32 r3, 0xe456789a; +imm32 r4, 0xe56789ab; +imm32 r5, 0xe6789abc; +imm32 r6, 0xe789abcd; +imm32 r7, 0xe89abcde; +R0 = PACK( R0.L , R6.L ); +R1 = PACK( R1.L , R6.H ); +R2 = PACK( R2.H , R6.L ); +R3 = PACK( R3.H , R6.H ); +R4 = PACK( R4.L , R6.L ); +R5 = PACK( R5.L , R6.H ); +R6 = PACK( R6.H , R6.L ); +R7 = PACK( R7.H , R6.H ); +CHECKREG r0, 0x000EABCD; +CHECKREG r1, 0x5678E789; +CHECKREG r2, 0xE345ABCD; +CHECKREG r3, 0xE456E789; +CHECKREG r4, 0x89ABABCD; +CHECKREG r5, 0x9ABCE789; +CHECKREG r6, 0xE789ABCD; +CHECKREG r7, 0xE89AE789; + +imm32 r0, 0xf123000f; +imm32 r1, 0xf2345678; +imm32 r2, 0xf3456789; +imm32 r3, 0xf456789a; +imm32 r4, 0xf56789ab; +imm32 r5, 0xf6789abc; +imm32 r6, 0xf789abcd; +imm32 r7, 0xf89abcde; +R0 = PACK( R0.L , R7.L ); +R1 = PACK( R1.L , R7.H ); +R2 = PACK( R2.H , R7.L ); +R3 = PACK( R3.H , R7.H ); +R4 = PACK( R4.L , R7.L ); +R5 = PACK( R5.L , R7.H ); +R6 = PACK( R6.H , R7.L ); +R7 = PACK( R7.H , R7.H ); +CHECKREG r0, 0x000FBCDE; +CHECKREG r1, 0x5678F89A; +CHECKREG r2, 0xF345BCDE; +CHECKREG r3, 0xF456F89A; +CHECKREG r4, 0x89ABBCDE; +CHECKREG r5, 0x9ABCF89A; +CHECKREG r6, 0xF789BCDE; +CHECKREG r7, 0xF89AF89A; +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_rot.s b/sim/testsuite/bfin/c_dsp32shift_rot.s new file mode 100644 index 0000000..d4b2ff2 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_rot.s @@ -0,0 +1,427 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot/c_dsp32shift_rot.dsp +// Spec Reference: dsp32shift rot +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x01230001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R1 = ROT R0 BY R0.L; + R2 = ROT R1 BY R0.L; + R3 = ROT R2 BY R0.L; + R4 = ROT R3 BY R0.L; + R5 = ROT R4 BY R0.L; + R6 = ROT R5 BY R0.L; + R7 = ROT R6 BY R0.L; + R0 = ROT R7 BY R0.L; + CHECKREG r1, 0x02460002; + CHECKREG r0, 0x23000100; + CHECKREG r2, 0x048C0004; + CHECKREG r3, 0x09180008; + CHECKREG r4, 0x12300010; + CHECKREG r5, 0x24600020; + CHECKREG r6, 0x48C00040; + CHECKREG r7, 0x91800080; + + imm32 r0, 0x01230001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R1.L = 15; + R2 = ROT R0 BY R1.L; + R3 = ROT R1 BY R1.L; + R4 = ROT R2 BY R1.L; + R5 = ROT R3 BY R1.L; + R6 = ROT R4 BY R1.L; + R7 = ROT R5 BY R1.L; + R0 = ROT R6 BY R1.L; + R1 = ROT R7 BY R1.L; + CHECKREG r0, 0x2C04C400; + CHECKREG r1, 0x5C489000; + CHECKREG r2, 0x8000C048; + CHECKREG r3, 0x0007C48D; + CHECKREG r4, 0x60242000; + CHECKREG r5, 0xE2468001; + CHECKREG r6, 0x10005809; + CHECKREG r7, 0x4000B891; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2 = 16; + R3 = ROT R0 BY R2.L; + R4 = ROT R1 BY R2.L; + R5 = ROT R2 BY R2.L; + R6 = ROT R3 BY R2.L; + R7 = ROT R4 BY R2.L; + R0 = ROT R5 BY R2.L; + R1 = ROT R6 BY R2.L; + R2 = ROT R7 BY R2.L; + CHECKREG r0, 0x00000008; + CHECKREG r1, 0x00010048; + CHECKREG r2, 0x2B3CC48D; + CHECKREG r3, 0x00020091; + CHECKREG r4, 0x5678891A; + CHECKREG r5, 0x00100000; + CHECKREG r6, 0x00910001; + CHECKREG r7, 0x891A2B3C; + + imm32 r0, 0x01230003; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R3.L = 31; + R4 = ROT R0 BY R3.L; + R5 = ROT R1 BY R3.L; + R6 = ROT R2 BY R3.L; + R7 = ROT R3 BY R3.L; + R0 = ROT R4 BY R3.L; + R1 = ROT R5 BY R3.L; + R2 = ROT R6 BY R3.L; + R3 = ROT R7 BY R3.L; + CHECKREG r0, 0x60123000; + CHECKREG r1, 0x11234567; + CHECKREG r2, 0x62345678; + CHECKREG r3, 0xE3456001; + CHECKREG r4, 0x8048C000; + CHECKREG r5, 0x448D159E; + CHECKREG r6, 0x88D159E2; + CHECKREG r7, 0x8D158007; + + imm32 r0, 0x01230004; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -1; + R0 = ROT R0 BY R4.L; + R1 = ROT R1 BY R4.L; + R2 = ROT R2 BY R4.L; + R3 = ROT R3 BY R4.L; + R4 = ROT R4 BY R4.L; + R5 = ROT R5 BY R4.L; + R6 = ROT R6 BY R4.L; + R7 = ROT R7 BY R4.L; + CHECKREG r0, 0x80918002; + CHECKREG r1, 0x091A2B3C; + CHECKREG r2, 0x11A2B3C4; + CHECKREG r3, 0x9A2B3C4D; + CHECKREG r4, 0x22B3FFFF; + CHECKREG r5, 0xAB3C4D5E; + CHECKREG r6, 0x33C4D5E6; + CHECKREG r7, 0xBC4D5E6F; + + imm32 r0, 0x01230005; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R5.L = -15; + R6 = ROT R0 BY R5.L; + R7 = ROT R1 BY R5.L; + R0 = ROT R2 BY R5.L; + R1 = ROT R3 BY R5.L; + R2 = ROT R4 BY R5.L; + R3 = ROT R5 BY R5.L; + R4 = ROT R6 BY R5.L; + R5 = ROT R7 BY R5.L; + CHECKREG r0, 0x9E26468A; + CHECKREG r1, 0xE26A68AC; + CHECKREG r2, 0x26AE8ACF; + CHECKREG r3, 0xFFC4ACF1; + CHECKREG r4, 0x091A0028; + CHECKREG r5, 0x91A0B3C0; + CHECKREG r6, 0x00140246; + CHECKREG r7, 0x59E02468; + + imm32 r0, 0x01230006; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -16; + R7 = ROT R0 BY R6.L; + R0 = ROT R1 BY R6.L; + R1 = ROT R2 BY R6.L; + R2 = ROT R3 BY R6.L; + R3 = ROT R4 BY R6.L; + R4 = ROT R5 BY R6.L; + R5 = ROT R6 BY R6.L; + R6 = ROT R7 BY R6.L; + CHECKREG r0, 0xACF01234; + CHECKREG r1, 0xCF122345; + CHECKREG r2, 0xF1343456; + CHECKREG r3, 0x13564567; + CHECKREG r4, 0x35795678; + CHECKREG r5, 0xFFE16789; + CHECKREG r6, 0x0247000C; + CHECKREG r7, 0x000C0123; + + imm32 r0, 0x01230007; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R7.L = -27; + R0 = ROT R0 BY R7.L; + R1 = ROT R1 BY R7.L; + R2 = ROT R2 BY R7.L; + R3 = ROT R3 BY R7.L; + R4 = ROT R4 BY R7.L; + R5 = ROT R5 BY R7.L; + R6 = ROT R6 BY R7.L; + R7 = ROT R7 BY R7.L; + CHECKREG r0, 0x48C001C0; + CHECKREG r1, 0x8D159E02; + CHECKREG r2, 0xD159E244; + CHECKREG r3, 0x159E2686; + CHECKREG r4, 0x59E26AE8; + CHECKREG r5, 0x9E26AF2A; + CHECKREG r6, 0xE26AF36C; + CHECKREG r7, 0x26BFF96F; + + imm32 r0, 0x01230008; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R0.L = 7; +//r0 = rot (r0 by rl0); + R1 = ROT R1 BY R0.L; + R2 = ROT R2 BY R0.L; + R3 = ROT R3 BY R0.L; + R4 = ROT R4 BY R0.L; + R5 = ROT R5 BY R0.L; + R6 = ROT R6 BY R0.L; + R7 = ROT R7 BY R0.L; + CHECKREG r0, 0x01230007; + CHECKREG r1, 0x1A2B3C04; + CHECKREG r2, 0xA2B3C4C8; + CHECKREG r3, 0x2B3C4D4D; + CHECKREG r4, 0xB3C4D591; + CHECKREG r5, 0x3C4D5E15; + CHECKREG r6, 0xC4D5E6D9; + CHECKREG r7, 0x4D5E6F5E; + + imm32 r0, 0x01230009; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R1.L = 16; + R0 = ROT R0 BY R1.L; +//r1 = rot (r1 by rl1); + R2 = ROT R2 BY R1.L; + R3 = ROT R3 BY R1.L; + R4 = ROT R4 BY R1.L; + R5 = ROT R5 BY R1.L; + R6 = ROT R6 BY R1.L; + R7 = ROT R7 BY R1.L; + CHECKREG r0, 0x00090091; + CHECKREG r1, 0x12340010; + CHECKREG r2, 0x678991A2; + CHECKREG r3, 0x789A9A2B; + CHECKREG r4, 0x89AB22B3; + CHECKREG r5, 0x9ABCAB3C; + CHECKREG r6, 0xABCD33C4; + CHECKREG r7, 0xBCDEBC4D; + + imm32 r0, 0x0123000a; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2.L = 30; + R0 = ROT R0 BY R2.L; + R1 = ROT R1 BY R2.L; +//r2 = rot (r2 by rl2); + R3 = ROT R3 BY R2.L; + R4 = ROT R4 BY R2.L; + R5 = ROT R5 BY R2.L; + R6 = ROT R6 BY R2.L; + R7 = ROT R7 BY R2.L; + CHECKREG r0, 0x80246001; + CHECKREG r1, 0x02468ACF; + CHECKREG r2, 0x2345001E; + CHECKREG r3, 0x868ACF13; + CHECKREG r4, 0xC8ACF135; + CHECKREG r5, 0x0ACF1357; + CHECKREG r6, 0x6CF13579; + CHECKREG r7, 0xAF13579B; + + imm32 r0, 0x0123000b; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R3.L = 31; + R0 = ROT R0 BY R3.L; + R1 = ROT R1 BY R3.L; + R2 = ROT R2 BY R3.L; +//r3 = rot (r3 by rl3); + R4 = ROT R4 BY R3.L; + R5 = ROT R5 BY R3.L; + R6 = ROT R6 BY R3.L; + R7 = ROT R7 BY R3.L; + CHECKREG r0, 0xC048C002; + CHECKREG r1, 0x448D159E; + CHECKREG r2, 0x88D159E2; + CHECKREG r3, 0x3456001F; + CHECKREG r4, 0x9159E26A; + CHECKREG r5, 0x559E26AF; + CHECKREG r6, 0x99E26AF3; + CHECKREG r7, 0x1E26AF37; + + imm32 r0, 0x0123000c; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -2; + R0 = ROT R0 BY R4.L; + R1 = ROT R1 BY R4.L; + R2 = ROT R2 BY R4.L; + R3 = ROT R3 BY R4.L; +//r4 = rot (r4 by rl4); + R5 = ROT R5 BY R4.L; + R6 = ROT R6 BY R4.L; + R7 = ROT R7 BY R4.L; + CHECKREG r0, 0x4048C003; + CHECKREG r1, 0x048D159E; + CHECKREG r2, 0x88D159E2; + CHECKREG r3, 0x0D159E26; + CHECKREG r4, 0x4567FFFE; + CHECKREG r5, 0x559E26AF; + CHECKREG r6, 0x99E26AF3; + CHECKREG r7, 0x1E26AF37; + + imm32 r0, 0x0123000d; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R5.L = -17; + R0 = ROT R0 BY R5.L; + R1 = ROT R1 BY R5.L; + R2 = ROT R2 BY R5.L; + R3 = ROT R3 BY R5.L; + R4 = ROT R4 BY R5.L; +//r5 = rot (r5 by rl5); + R6 = ROT R6 BY R5.L; + R7 = ROT R7 BY R5.L; + CHECKREG r0, 0x000D8091; + CHECKREG r1, 0x5678891A; + CHECKREG r2, 0x678911A2; + CHECKREG r3, 0x789A9A2B; + CHECKREG r4, 0x89AB22B3; + CHECKREG r5, 0x5678FFEF; + CHECKREG r6, 0xABCDB3C4; + CHECKREG r7, 0xBCDEBC4D; + + imm32 r0, 0x0123000e; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -30; + R0 = ROT R0 BY R6.L; + R1 = ROT R1 BY R6.L; + R2 = ROT R2 BY R6.L; + R3 = ROT R3 BY R6.L; + R4 = ROT R4 BY R6.L; + R5 = ROT R5 BY R6.L; +//r6 = rot (r6 by rl6); + R7 = ROT R7 BY R6.L; + CHECKREG r0, 0x09180070; + CHECKREG r1, 0x91A2B3C0; + CHECKREG r2, 0x1A2B3C48; + CHECKREG r3, 0xA2B3C4D4; + CHECKREG r4, 0x2B3C4D5D; + CHECKREG r5, 0xB3C4D5E1; + CHECKREG r6, 0x6789FFE2; + CHECKREG r7, 0xC4D5E6F1; + + imm32 r0, 0x0123000f; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R7.L = -31; + R0 = ROT R0 BY R7.L; + R1 = ROT R1 BY R7.L; + R2 = ROT R2 BY R7.L; + R3 = ROT R3 BY R7.L; + R4 = ROT R4 BY R7.L; + R5 = ROT R5 BY R7.L; + R6 = ROT R6 BY R7.L; + R7 = ROT R7 BY R7.L; + CHECKREG r0, 0x048C003E; + CHECKREG r1, 0x48D159E0; + CHECKREG r2, 0x8D159E24; + CHECKREG r3, 0xD159E268; + CHECKREG r4, 0x159E26AC; + CHECKREG r5, 0x59E26AF2; + CHECKREG r6, 0x9E26AF36; + CHECKREG r7, 0xE26BFF86; + + pass diff --git a/sim/testsuite/bfin/c_dsp32shift_rot_mix.s b/sim/testsuite/bfin/c_dsp32shift_rot_mix.s new file mode 100644 index 0000000..7639b99 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_rot_mix.s @@ -0,0 +1,437 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot_mix/c_dsp32shift_rot_mix.dsp +// Spec Reference: dsp32shift rot +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + + imm32 r0, 0x01230000; + imm32 r1, 0x12345678; + imm32 r2, 0x83456789; + imm32 r3, 0x9456789a; + imm32 r4, 0xa56789ab; + imm32 r5, 0xb6789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0xd89abcde; + R1 = ROT R0 BY R0.L; + R2 = ROT R1 BY R0.L; + R3 = ROT R2 BY R0.L; + R4 = ROT R3 BY R0.L; + R5 = ROT R4 BY R0.L; + R6 = ROT R5 BY R0.L; + R7 = ROT R6 BY R0.L; + R0 = ROT R7 BY R0.L; + CHECKREG r0, 0x01230000; + CHECKREG r1, 0x01230000; + CHECKREG r2, 0x01230000; + CHECKREG r3, 0x01230000; + CHECKREG r4, 0x01230000; + CHECKREG r5, 0x01230000; + CHECKREG r6, 0x01230000; + CHECKREG r7, 0x01230000; + + A0 = 0; + A0.L = R0.L; + A0.H = R0.H; + A0 = ROT A0 BY R1.L; + R6 = A0.w; + imm32 r4, 0x30003000; + imm32 r1, 5; + R7 = ROT R4 BY R1.L; + CHECKREG r6, 0x01230000; + CHECKREG r7, 0x00060003; + + imm32 r0, 0x11230001; + imm32 r1, 0xc2345678; + imm32 r2, 0xd3456789; + imm32 r3, 0xb456789a; + imm32 r4, 0x056789ab; + imm32 r5, 0x36789abc; + imm32 r6, 0x1789abcd; + imm32 r7, 0x189abcde; + R1.L = 5; + R2 = ROT R0 BY R1.L; + R3 = ROT R1 BY R1.L; + R4 = ROT R2 BY R1.L; + R5 = ROT R3 BY R1.L; + R6 = ROT R4 BY R1.L; + R7 = ROT R5 BY R1.L; + R0 = ROT R6 BY R1.L; + R1 = ROT R7 BY R1.L; + CHECKREG r0, 0x00108908; + CHECKREG r1, 0x005613A0; + CHECKREG r2, 0x24600021; + CHECKREG r3, 0x468000AC; + CHECKREG r4, 0x8C000422; + CHECKREG r5, 0xD0001584; + CHECKREG r6, 0x80008448; + CHECKREG r7, 0x0002B09D; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x8456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0x789abcde; + R2 = 15; + R3 = ROT R0 BY R2.L; + R4 = ROT R1 BY R2.L; + R5 = ROT R2 BY R2.L; + R6 = ROT R3 BY R2.L; + R7 = ROT R4 BY R2.L; + R0 = ROT R5 BY R2.L; + R1 = ROT R6 BY R2.L; + R2 = ROT R7 BY R2.L; + CHECKREG r0, 0xC0000001; + CHECKREG r1, 0x10006009; + CHECKREG r2, 0x45678891; + CHECKREG r3, 0x80010048; + CHECKREG r4, 0x2B3C448D; + CHECKREG r5, 0x00078000; + CHECKREG r6, 0x80242000; + CHECKREG r7, 0x22468ACF; + + imm32 r0, 0x21230003; + imm32 r1, 0x22345678; + imm32 r2, 0x23456789; + imm32 r3, 0x2456789a; + imm32 r4, 0x256789ab; + imm32 r5, 0x26789abc; + imm32 r6, 0x2789abcd; + imm32 r7, 0x289abcde; + R3.L = 24; + R4 = ROT R0 BY R3.L; + R5 = ROT R1 BY R3.L; + R6 = ROT R2 BY R3.L; + R7 = ROT R3 BY R3.L; + R0 = ROT R4 BY R3.L; + R1 = ROT R5 BY R3.L; + R2 = ROT R6 BY R3.L; + R3 = ROT R7 BY R3.L; + CHECKREG r0, 0x8001C848; + CHECKREG r1, 0x2BBC088D; + CHECKREG r2, 0xB34488D1; + CHECKREG r3, 0x000C4915; + CHECKREG r4, 0x03909180; + CHECKREG r5, 0x78111A2B; + CHECKREG r6, 0x8911A2B3; + CHECKREG r7, 0x18922B00; + + imm32 r0, 0x01230004; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -1; + R0 = ROT R0 BY R4.L; + R1 = ROT R1 BY R4.L; + R2 = ROT R2 BY R4.L; + R3 = ROT R3 BY R4.L; + R4 = ROT R4 BY R4.L; + R5 = ROT R5 BY R4.L; + R6 = ROT R6 BY R4.L; + R7 = ROT R7 BY R4.L; + CHECKREG r0, 0x80918002; + CHECKREG r1, 0x091A2B3C; + CHECKREG r2, 0x11A2B3C4; + CHECKREG r3, 0x9A2B3C4D; + CHECKREG r4, 0x22B3FFFF; + CHECKREG r5, 0xAB3C4D5E; + CHECKREG r6, 0x33C4D5E6; + CHECKREG r7, 0xBC4D5E6F; + + imm32 r0, 0x01230005; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R5.L = -6; + R6 = ROT R0 BY R5.L; + R7 = ROT R1 BY R5.L; + R0 = ROT R2 BY R5.L; + R1 = ROT R3 BY R5.L; + R2 = ROT R4 BY R5.L; + R3 = ROT R5 BY R5.L; + R4 = ROT R6 BY R5.L; + R5 = ROT R7 BY R5.L; + CHECKREG r0, 0x4C8D159E; + CHECKREG r1, 0xD0D159E2; + CHECKREG r2, 0x59159E26; + CHECKREG r3, 0xD559E3FF; + CHECKREG r4, 0x04A01230; + CHECKREG r5, 0xCB012345; + CHECKREG r6, 0x28048C00; + CHECKREG r7, 0xC048D159; + + imm32 r0, 0x01230006; + imm32 r1, 0x82345678; + imm32 r2, 0x73456789; + imm32 r3, 0x3456789a; + imm32 r4, 0xd56789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0x789abcde; + R6.L = -15; + R7 = ROT R0 BY R6.L; + R0 = ROT R1 BY R6.L; + R1 = ROT R2 BY R6.L; + R2 = ROT R3 BY R6.L; + R3 = ROT R4 BY R6.L; + R4 = ROT R5 BY R6.L; + R5 = ROT R6 BY R6.L; + R6 = ROT R7 BY R6.L; + CHECKREG r0, 0x59E10468; + CHECKREG r1, 0x9E26E68A; + CHECKREG r2, 0xE26A68AC; + CHECKREG r3, 0x26AFAACF; + CHECKREG r4, 0x6AF0ACF1; + CHECKREG r5, 0xFFC58F13; + CHECKREG r6, 0x091A0030; + CHECKREG r7, 0x00180246; + + imm32 r0, 0x01230007; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R7.L = -27; + R0 = ROT R0 BY R7.L; + R1 = ROT R1 BY R7.L; + R2 = ROT R2 BY R7.L; + R3 = ROT R3 BY R7.L; + R4 = ROT R4 BY R7.L; + R5 = ROT R5 BY R7.L; + R6 = ROT R6 BY R7.L; + R7 = ROT R7 BY R7.L; + CHECKREG r0, 0x48C001C0; + CHECKREG r1, 0x8D159E02; + CHECKREG r2, 0xD159E244; + CHECKREG r3, 0x159E2686; + CHECKREG r4, 0x59E26AE8; + CHECKREG r5, 0x9E26AF2A; + CHECKREG r6, 0xE26AF36C; + CHECKREG r7, 0x26BFF96F; + + imm32 r0, 0x01230008; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R0.L = 7; +//r0 = rot (r0 by rl0); + R1 = ROT R1 BY R0.L; + R2 = ROT R2 BY R0.L; + R3 = ROT R3 BY R0.L; + R4 = ROT R4 BY R0.L; + R5 = ROT R5 BY R0.L; + R6 = ROT R6 BY R0.L; + R7 = ROT R7 BY R0.L; + CHECKREG r0, 0x01230007; + CHECKREG r1, 0x1A2B3C04; + CHECKREG r2, 0xA2B3C4C8; + CHECKREG r3, 0x2B3C4D4D; + CHECKREG r4, 0xB3C4D591; + CHECKREG r5, 0x3C4D5E15; + CHECKREG r6, 0xC4D5E6D9; + CHECKREG r7, 0x4D5E6F5E; + + imm32 r0, 0x01230009; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R1.L = 16; + R0 = ROT R0 BY R1.L; +//r1 = rot (r1 by rl1); + R2 = ROT R2 BY R1.L; + R3 = ROT R3 BY R1.L; + R4 = ROT R4 BY R1.L; + R5 = ROT R5 BY R1.L; + R6 = ROT R6 BY R1.L; + R7 = ROT R7 BY R1.L; + CHECKREG r0, 0x00090091; + CHECKREG r1, 0x12340010; + CHECKREG r2, 0x678991A2; + CHECKREG r3, 0x789A9A2B; + CHECKREG r4, 0x89AB22B3; + CHECKREG r5, 0x9ABCAB3C; + CHECKREG r6, 0xABCD33C4; + CHECKREG r7, 0xBCDEBC4D; + + imm32 r0, 0x0123000a; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2.L = 31; + R0 = ROT R0 BY R2.L; + R1 = ROT R1 BY R2.L; +//r2 = rot (r2 by rl2); + R3 = ROT R3 BY R2.L; + R4 = ROT R4 BY R2.L; + R5 = ROT R5 BY R2.L; + R6 = ROT R6 BY R2.L; + R7 = ROT R7 BY R2.L; + CHECKREG r0, 0x0048C002; + CHECKREG r1, 0x448D159E; + CHECKREG r2, 0x2345001F; + CHECKREG r3, 0x0D159E26; + CHECKREG r4, 0xD159E26A; + CHECKREG r5, 0x559E26AF; + CHECKREG r6, 0x99E26AF3; + CHECKREG r7, 0x1E26AF37; + + imm32 r0, 0x0123000b; + imm32 r1, 0x92345678; + imm32 r2, 0x93456789; + imm32 r3, 0xc456789a; + imm32 r4, 0xa56789ab; + imm32 r5, 0xb6789abc; + imm32 r6, 0xe789abcd; + imm32 r7, 0xf89abcde; + R3.L = 33; + R0 = ROT R0 BY R3.L; + R1 = ROT R1 BY R3.L; + R2 = ROT R2 BY R3.L; +//r3 = rot (r3 by rl3); + R4 = ROT R4 BY R3.L; + R5 = ROT R5 BY R3.L; + R6 = ROT R6 BY R3.L; + R7 = ROT R7 BY R3.L; + CHECKREG r0, 0x048C002E; + CHECKREG r1, 0x48D159E1; + CHECKREG r2, 0x4D159E25; + CHECKREG r3, 0xC4560021; + CHECKREG r4, 0x959E26AD; + CHECKREG r5, 0xD9E26AF1; + CHECKREG r6, 0x9E26AF35; + CHECKREG r7, 0xE26AF37B; + + imm32 r0, 0x0123000c; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -2; + R0 = ROT R0 BY R4.L; + R1 = ROT R1 BY R4.L; + R2 = ROT R2 BY R4.L; + R3 = ROT R3 BY R4.L; +//r4 = rot (r4 by rl4); + R5 = ROT R5 BY R4.L; + R6 = ROT R6 BY R4.L; + R7 = ROT R7 BY R4.L; + CHECKREG r0, 0x4048C003; + CHECKREG r1, 0x048D159E; + CHECKREG r2, 0x88D159E2; + CHECKREG r3, 0x0D159E26; + CHECKREG r4, 0x4567FFFE; + CHECKREG r5, 0x559E26AF; + CHECKREG r6, 0x99E26AF3; + CHECKREG r7, 0x1E26AF37; + + imm32 r0, 0x0123000d; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R5.L = -14; + R0 = ROT R0 BY R5.L; + R1 = ROT R1 BY R5.L; + R2 = ROT R2 BY R5.L; + R3 = ROT R3 BY R5.L; + R4 = ROT R4 BY R5.L; +//r5 = rot (r5 by rl5); + R6 = ROT R6 BY R5.L; + R7 = ROT R7 BY R5.L; + CHECKREG r0, 0x006C048C; + CHECKREG r1, 0xB3C048D1; + CHECKREG r2, 0x3C488D15; + CHECKREG r3, 0xC4D4D159; + CHECKREG r4, 0x4D5D159E; + CHECKREG r5, 0x5678FFF2; + CHECKREG r6, 0x5E699E26; + CHECKREG r7, 0xE6F5E26A; + + imm32 r0, 0x0123000e; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -16; + R0 = ROT R0 BY R6.L; + R1 = ROT R1 BY R6.L; + R2 = ROT R2 BY R6.L; + R3 = ROT R3 BY R6.L; + R4 = ROT R4 BY R6.L; + R5 = ROT R5 BY R6.L; +//r6 = rot (r6 by rl6); + R7 = ROT R7 BY R6.L; + CHECKREG r0, 0x001D0123; + CHECKREG r1, 0xACF01234; + CHECKREG r2, 0xCF122345; + CHECKREG r3, 0xF1343456; + CHECKREG r4, 0x13564567; + CHECKREG r5, 0x35795678; + CHECKREG r6, 0x6789FFF0; + CHECKREG r7, 0x79BD789A; + + imm32 r0, 0x0123000f; + imm32 r1, 0x12345678; + imm32 r2, 0x83456789; + imm32 r3, 0x3456789a; + imm32 r4, 0xd56789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x9789abcd; + imm32 r7, 0x789abcde; + R7.L = -32; + R0 = ROT R0 BY R7.L; + R1 = ROT R1 BY R7.L; + R2 = ROT R2 BY R7.L; + R3 = ROT R3 BY R7.L; + R4 = ROT R4 BY R7.L; + R5 = ROT R5 BY R7.L; + R6 = ROT R6 BY R7.L; + R7 = ROT R7 BY R7.L; + CHECKREG r0, 0x0246001f; + CHECKREG r1, 0x2468ACF0; + CHECKREG r2, 0x068ACF12; + CHECKREG r3, 0x68ACF135; + CHECKREG r4, 0xAACF1356; + CHECKREG r5, 0xACF13579; + CHECKREG r6, 0x2F13579A; + CHECKREG r7, 0xF135FFC1; + pass diff --git a/sim/testsuite/bfin/c_dsp32shift_signbits_r.s b/sim/testsuite/bfin/c_dsp32shift_signbits_r.s new file mode 100644 index 0000000..6bdb7a0 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_signbits_r.s @@ -0,0 +1,214 @@ +//Original:/testcases/core/c_dsp32shift_signbits_r/c_dsp32shift_signbits_r.dsp +// Spec Reference: dsp32shift signbits dregs +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0x88880000; +imm32 r1, 0x34560001; +imm32 r2, 0x08000002; +imm32 r3, 0x08000003; +imm32 r4, 0x08000004; +imm32 r5, 0x08000005; +imm32 r6, 0x08000006; +imm32 r7, 0x08000007; +R7.L = SIGNBITS R0; +R1.L = SIGNBITS R0; +R2.L = SIGNBITS R0; +R3.L = SIGNBITS R0; +R4.L = SIGNBITS R0; +R5.L = SIGNBITS R0; +R6.L = SIGNBITS R0; +R0.L = SIGNBITS R0; +CHECKREG r0, 0x88880000; +CHECKREG r1, 0x34560000; +CHECKREG r2, 0x08000000; +CHECKREG r3, 0x08000000; +CHECKREG r4, 0x08000000; +CHECKREG r5, 0x08000000; +CHECKREG r6, 0x08000000; +CHECKREG r7, 0x08000000; + +imm32 r0, 0x9999001E; +imm32 r1, 0x0000001E; +imm32 r2, 0x0000001E; +imm32 r3, 0x0000001E; +imm32 r4, 0x0000001E; +imm32 r5, 0x0000001E; +imm32 r6, 0x0000001E; +imm32 r7, 0x0000001E; +R0.L = SIGNBITS R1; +R7.L = SIGNBITS R1; +R2.L = SIGNBITS R1; +R3.L = SIGNBITS R1; +R4.L = SIGNBITS R1; +R5.L = SIGNBITS R1; +R6.L = SIGNBITS R1; +R1.L = SIGNBITS R1; +CHECKREG r0, 0x9999001A; +CHECKREG r1, 0x0000001A; +CHECKREG r2, 0x0000001A; +CHECKREG r3, 0x0000001A; +CHECKREG r4, 0x0000001A; +CHECKREG r5, 0x0000001A; +CHECKREG r6, 0x0000001A; +CHECKREG r7, 0x0000001A; + + +imm32 r0, 0x0aaae001; +imm32 r1, 0x0000e001; +imm32 r2, 0xaaaa000f; +imm32 r3, 0x0a00e003; +imm32 r4, 0x00a0e004; +imm32 r5, 0x00a0e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0b00e007; +R0.L = SIGNBITS R2; +R1.L = SIGNBITS R2; +R7.L = SIGNBITS R2; +R3.L = SIGNBITS R2; +R4.L = SIGNBITS R2; +R5.L = SIGNBITS R2; +R6.L = SIGNBITS R2; +R2.L = SIGNBITS R2; +CHECKREG r0, 0x0AAA0000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xAAAA0000; +CHECKREG r3, 0x0A000000; +CHECKREG r4, 0x00A00000; +CHECKREG r5, 0x00A00000; +CHECKREG r6, 0x0A000000; +CHECKREG r7, 0x0B000000; + +imm32 r0, 0x0b00f001; +imm32 r1, 0x0a00f001; +imm32 r2, 0x0b00f002; +imm32 r3, 0xbbbb0010; +imm32 r4, 0x0b00f004; +imm32 r5, 0x0b00f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x00b0f007; +R0.L = SIGNBITS R3; +R1.L = SIGNBITS R3; +R2.L = SIGNBITS R3; +R7.L = SIGNBITS R3; +R4.L = SIGNBITS R3; +R5.L = SIGNBITS R3; +R6.L = SIGNBITS R3; +R3.L = SIGNBITS R3; +CHECKREG r0, 0x0B000000; +CHECKREG r1, 0x0A000000; +CHECKREG r2, 0x0B000000; +CHECKREG r3, 0xBBBB0000; +CHECKREG r4, 0x0B000000; +CHECKREG r5, 0x0B000000; +CHECKREG r6, 0x0B000000; +CHECKREG r7, 0x00B00000; + +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0xcccc0000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = SIGNBITS R4; +R1.L = SIGNBITS R4; +R2.L = SIGNBITS R4; +R3.L = SIGNBITS R4; +R7.L = SIGNBITS R4; +R5.L = SIGNBITS R4; +R6.L = SIGNBITS R4; +R4.L = SIGNBITS R4; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020001; +CHECKREG r3, 0x00030001; +CHECKREG r4, 0xCCCC0001; +CHECKREG r5, 0x00050001; +CHECKREG r6, 0x00060001; +CHECKREG r7, 0x00070001; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xdddd0000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = SIGNBITS R5; +R1.L = SIGNBITS R5; +R2.L = SIGNBITS R5; +R3.L = SIGNBITS R5; +R4.L = SIGNBITS R5; +R7.L = SIGNBITS R5; +R6.L = SIGNBITS R5; +R5.L = SIGNBITS R5; +CHECKREG r0, 0xA0010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0xA0020001; +CHECKREG r3, 0xA0030001; +CHECKREG r4, 0xA0040001; +CHECKREG r5, 0xDDDD0001; +CHECKREG r6, 0xA0060001; +CHECKREG r7, 0xA0070001; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xeeee0000; +imm32 r7, 0xb0070000; +R0.L = SIGNBITS R6; +R1.L = SIGNBITS R6; +R2.L = SIGNBITS R6; +R3.L = SIGNBITS R6; +R4.L = SIGNBITS R6; +R5.L = SIGNBITS R6; +R7.L = SIGNBITS R6; +R6.L = SIGNBITS R6; +CHECKREG r0, 0xB0010002; +CHECKREG r1, 0xB0010002; +CHECKREG r2, 0xB0020002; +CHECKREG r3, 0xB0030002; +CHECKREG r4, 0xB0040002; +CHECKREG r5, 0xB0050002; +CHECKREG r6, 0xEEEE0002; +CHECKREG r7, 0xB0070002; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xffff0000; +R0.L = SIGNBITS R7; +R1.L = SIGNBITS R7; +R2.L = SIGNBITS R7; +R3.L = SIGNBITS R7; +R4.L = SIGNBITS R7; +R5.L = SIGNBITS R7; +R6.L = SIGNBITS R7; +R7.L = SIGNBITS R7; + +CHECKREG r0, 0xD001000F; +CHECKREG r1, 0xD001000F; +CHECKREG r2, 0xD002000F; +CHECKREG r3, 0xD003000F; +CHECKREG r4, 0xD004000F; +CHECKREG r5, 0xD005000F; +CHECKREG r6, 0xD006000F; +CHECKREG r7, 0xFFFF000F; +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_signbits_rh.s b/sim/testsuite/bfin/c_dsp32shift_signbits_rh.s new file mode 100644 index 0000000..8ae46ae --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_signbits_rh.s @@ -0,0 +1,214 @@ +//Original:/testcases/core/c_dsp32shift_signbits_rh/c_dsp32shift_signbits_rh.dsp +// Spec Reference: dsp32shift signbits dregs_hi +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xd1000000; +imm32 r1, 0xd2000001; +imm32 r2, 0xd3000002; +imm32 r3, 0xd4000003; +imm32 r4, 0xd5000004; +imm32 r5, 0xd6000005; +imm32 r6, 0xd7000006; +imm32 r7, 0xd8000007; +R0.L = SIGNBITS R0.H; +R1.L = SIGNBITS R0.H; +R2.L = SIGNBITS R0.H; +R3.L = SIGNBITS R0.H; +R4.L = SIGNBITS R0.H; +R5.L = SIGNBITS R0.H; +R6.L = SIGNBITS R0.H; +R7.L = SIGNBITS R0.H; +CHECKREG r0, 0xD1000001; +CHECKREG r1, 0xD2000001; +CHECKREG r2, 0xD3000001; +CHECKREG r3, 0xD4000001; +CHECKREG r4, 0xD5000001; +CHECKREG r5, 0xD6000001; +CHECKREG r6, 0xD7000001; +CHECKREG r7, 0xD8000001; + +imm32 r0, 0xe200d001; +imm32 r1, 0xe2000001; +imm32 r2, 0xe200d002; +imm32 r3, 0xe200d003; +imm32 r4, 0xe200d004; +imm32 r5, 0xe200d005; +imm32 r6, 0xe200d006; +imm32 r7, 0xe200d007; +R0.L = SIGNBITS R1.H; +R1.L = SIGNBITS R1.H; +R2.L = SIGNBITS R1.H; +R3.L = SIGNBITS R1.H; +R4.L = SIGNBITS R1.H; +R5.L = SIGNBITS R1.H; +R6.L = SIGNBITS R1.H; +R7.L = SIGNBITS R1.H; +CHECKREG r0, 0xE2000002; +CHECKREG r1, 0xE2000002; +CHECKREG r2, 0xE2000002; +CHECKREG r3, 0xE2000002; +CHECKREG r4, 0xE2000002; +CHECKREG r5, 0xE2000002; +CHECKREG r6, 0xE2000002; +CHECKREG r7, 0xE2000002; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0xf000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.L = SIGNBITS R2.H; +R1.L = SIGNBITS R2.H; +R2.L = SIGNBITS R2.H; +R3.L = SIGNBITS R2.H; +R4.L = SIGNBITS R2.H; +R5.L = SIGNBITS R2.H; +R6.L = SIGNBITS R2.H; +R7.L = SIGNBITS R2.H; +CHECKREG r0, 0x00000003; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0xF0000003; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000003; +CHECKREG r5, 0x00000003; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x0100f001; +imm32 r1, 0x0100f001; +imm32 r2, 0x0100f002; +imm32 r3, 0x01000010; +imm32 r4, 0x0100f004; +imm32 r5, 0x0100f005; +imm32 r6, 0x0100f006; +imm32 r7, 0x0100f007; +R0.L = SIGNBITS R3.H; +R1.L = SIGNBITS R3.H; +R2.L = SIGNBITS R3.H; +R3.L = SIGNBITS R3.H; +R4.L = SIGNBITS R3.H; +R5.L = SIGNBITS R3.H; +R6.L = SIGNBITS R3.H; +R7.L = SIGNBITS R3.H; +CHECKREG r0, 0x01000006; +CHECKREG r1, 0x01000006; +CHECKREG r2, 0x01000006; +CHECKREG r3, 0x01000006; +CHECKREG r4, 0x01000006; +CHECKREG r5, 0x01000006; +CHECKREG r6, 0x01000006; +CHECKREG r7, 0x01000006; + +imm32 r0, 0x04000000; +imm32 r1, 0x04010000; +imm32 r2, 0x04020000; +imm32 r3, 0x04030000; +imm32 r4, 0x04040000; +imm32 r5, 0x04050000; +imm32 r6, 0x04060000; +imm32 r7, 0x04070000; +R0.L = SIGNBITS R4.H; +R1.L = SIGNBITS R4.H; +R2.L = SIGNBITS R4.H; +R3.L = SIGNBITS R4.H; +R4.L = SIGNBITS R4.H; +R5.L = SIGNBITS R4.H; +R6.L = SIGNBITS R4.H; +R7.L = SIGNBITS R4.H; +CHECKREG r0, 0x04000004; +CHECKREG r1, 0x04010004; +CHECKREG r2, 0x04020004; +CHECKREG r3, 0x04030004; +CHECKREG r4, 0x04040004; +CHECKREG r5, 0x04050004; +CHECKREG r6, 0x04060004; +CHECKREG r7, 0x04070004; + +imm32 r0, 0xa5010000; +imm32 r1, 0xa5010001; +imm32 r2, 0xa5020000; +imm32 r3, 0xa5030000; +imm32 r4, 0xa5540000; +imm32 r5, 0xa5550000; +imm32 r6, 0xa5060000; +imm32 r7, 0xa5070000; +R0.L = SIGNBITS R5.H; +R1.L = SIGNBITS R5.H; +R2.L = SIGNBITS R5.H; +R3.L = SIGNBITS R5.H; +R4.L = SIGNBITS R5.H; +R5.L = SIGNBITS R5.H; +R6.L = SIGNBITS R5.H; +R7.L = SIGNBITS R5.H; +CHECKREG r0, 0xA5010000; +CHECKREG r1, 0xA5010000; +CHECKREG r2, 0xA5020000; +CHECKREG r3, 0xA5030000; +CHECKREG r4, 0xA5540000; +CHECKREG r5, 0xA5550000; +CHECKREG r6, 0xA5060000; +CHECKREG r7, 0xA5070000; + + +imm32 r0, 0xb6010000; +imm32 r1, 0xb6010000; +imm32 r2, 0xb602000f; +imm32 r3, 0xb6030000; +imm32 r4, 0xb6040000; +imm32 r5, 0xb6050000; +imm32 r6, 0xb6060000; +imm32 r7, 0xb6670000; +R0.L = SIGNBITS R6.H; +R1.L = SIGNBITS R6.H; +R2.L = SIGNBITS R6.H; +R3.L = SIGNBITS R6.H; +R4.L = SIGNBITS R6.H; +R5.L = SIGNBITS R6.H; +R6.L = SIGNBITS R6.H; +R7.L = SIGNBITS R6.H; +CHECKREG r0, 0xB6010000; +CHECKREG r1, 0xB6010000; +CHECKREG r2, 0xB6020000; +CHECKREG r3, 0xB6030000; +CHECKREG r4, 0xB6040000; +CHECKREG r5, 0xB6050000; +CHECKREG r6, 0xB6060000; +CHECKREG r7, 0xB6670000; + +imm32 r0, 0xd7010000; +imm32 r1, 0xd7010000; +imm32 r2, 0xd7020000; +imm32 r3, 0xd7030010; +imm32 r4, 0xd7040000; +imm32 r5, 0xd7050000; +imm32 r6, 0xd7060000; +imm32 r7, 0xd7070000; +R0.L = SIGNBITS R7.H; +R1.L = SIGNBITS R7.H; +R2.L = SIGNBITS R7.H; +R3.L = SIGNBITS R7.H; +R4.L = SIGNBITS R7.H; +R5.L = SIGNBITS R7.H; +R6.L = SIGNBITS R7.H; +R7.L = SIGNBITS R7.H; +CHECKREG r0, 0xD7010001; +CHECKREG r1, 0xD7010001; +CHECKREG r2, 0xD7020001; +CHECKREG r3, 0xD7030001; +CHECKREG r4, 0xD7040001; +CHECKREG r5, 0xD7050001; +CHECKREG r6, 0xD7060001; +CHECKREG r7, 0xD7070001; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_signbits_rl.s b/sim/testsuite/bfin/c_dsp32shift_signbits_rl.s new file mode 100644 index 0000000..3f3ccfd --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_signbits_rl.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_signbits_rl/c_dsp32shift_signbits_rl.dsp +// Spec Reference: dsp32shift signbits dregs_lo +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R7.L = SIGNBITS R0.L; +R1.L = SIGNBITS R0.L; +R2.L = SIGNBITS R0.L; +R3.L = SIGNBITS R0.L; +R4.L = SIGNBITS R0.L; +R5.L = SIGNBITS R0.L; +R6.L = SIGNBITS R0.L; +R0.L = SIGNBITS R0.L; +CHECKREG r1, 0x0000000F; +CHECKREG r0, 0x0000000F; +CHECKREG r2, 0x0000000F; +CHECKREG r3, 0x0000000F; +CHECKREG r4, 0x0000000F; +CHECKREG r5, 0x0000000F; +CHECKREG r6, 0x0000000F; +CHECKREG r7, 0x0000000F; + +imm32 r0, 0x00000001; +imm32 r1, 0x00008001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R0.L = SIGNBITS R1.L; +R7.L = SIGNBITS R1.L; +R2.L = SIGNBITS R1.L; +R3.L = SIGNBITS R1.L; +R4.L = SIGNBITS R1.L; +R5.L = SIGNBITS R1.L; +R6.L = SIGNBITS R1.L; +R1.L = SIGNBITS R1.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +imm32 r0, 0x0000c001; +imm32 r1, 0x0000d001; +imm32 r2, 0x0000c00f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = SIGNBITS R2.L; +R1.L = SIGNBITS R2.L; +R7.L = SIGNBITS R2.L; +R3.L = SIGNBITS R2.L; +R4.L = SIGNBITS R2.L; +R5.L = SIGNBITS R2.L; +R6.L = SIGNBITS R2.L; +R2.L = SIGNBITS R2.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00009001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000b002; +imm32 r3, 0x00000e10; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000f007; +R0.L = SIGNBITS R3.L; +R1.L = SIGNBITS R3.L; +R2.L = SIGNBITS R3.L; +R7.L = SIGNBITS R3.L; +R4.L = SIGNBITS R3.L; +R5.L = SIGNBITS R3.L; +R6.L = SIGNBITS R3.L; +R3.L = SIGNBITS R3.L; +CHECKREG r0, 0x00000003; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0x00000003; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000003; +CHECKREG r5, 0x00000003; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x0000f000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = SIGNBITS R4.L; +R1.L = SIGNBITS R4.L; +R2.L = SIGNBITS R4.L; +R3.L = SIGNBITS R4.L; +R7.L = SIGNBITS R4.L; +R5.L = SIGNBITS R4.L; +R6.L = SIGNBITS R4.L; +R4.L = SIGNBITS R4.L; +CHECKREG r0, 0x00000003; +CHECKREG r1, 0x00010003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00000003; +CHECKREG r5, 0x00050003; +CHECKREG r6, 0x00060003; +CHECKREG r7, 0x00070003; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x9008f000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R0.L = SIGNBITS R5.L; +R1.L = SIGNBITS R5.L; +R2.L = SIGNBITS R5.L; +R3.L = SIGNBITS R5.L; +R4.L = SIGNBITS R5.L; +R7.L = SIGNBITS R5.L; +R6.L = SIGNBITS R5.L; +R5.L = SIGNBITS R5.L; +CHECKREG r0, 0x90010003; +CHECKREG r1, 0x00010003; +CHECKREG r2, 0x90020003; +CHECKREG r3, 0x90030003; +CHECKREG r4, 0x90040003; +CHECKREG r5, 0x90080003; +CHECKREG r6, 0x90060003; +CHECKREG r7, 0x90070003; + +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa000fc00; +imm32 r7, 0xa0070000; +R0.L = SIGNBITS R6.L; +R1.L = SIGNBITS R6.L; +R2.L = SIGNBITS R6.L; +R3.L = SIGNBITS R6.L; +R4.L = SIGNBITS R6.L; +R5.L = SIGNBITS R6.L; +R7.L = SIGNBITS R6.L; +R6.L = SIGNBITS R6.L; +CHECKREG r0, 0x90010005; +CHECKREG r1, 0xA0010005; +CHECKREG r2, 0xA0020005; +CHECKREG r3, 0xA0030005; +CHECKREG r4, 0xA0040005; +CHECKREG r5, 0xA0050005; +CHECKREG r6, 0xA0000005; +CHECKREG r7, 0xA0070005; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc007e007; +R0.L = SIGNBITS R7.L; +R1.L = SIGNBITS R7.L; +R2.L = SIGNBITS R7.L; +R3.L = SIGNBITS R7.L; +R4.L = SIGNBITS R7.L; +R5.L = SIGNBITS R7.L; +R6.L = SIGNBITS R7.L; +R7.L = SIGNBITS R7.L; +CHECKREG r0, 0xC0010002; +CHECKREG r1, 0xC0010002; +CHECKREG r2, 0xC0020002; +CHECKREG r3, 0xC0030002; +CHECKREG r4, 0xC0040002; +CHECKREG r5, 0xC0050002; +CHECKREG r6, 0xC0060002; +CHECKREG r7, 0xC0070002; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_vmax.s b/sim/testsuite/bfin/c_dsp32shift_vmax.s new file mode 100644 index 0000000..4f3ccd1 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_vmax.s @@ -0,0 +1,113 @@ +//Original:/testcases/core/c_dsp32shift_vmax/c_dsp32shift_vmax.dsp +// Spec Reference: dsp32shift vmax +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x11001001; +imm32 r1, 0x11001001; +imm32 r2, 0x12345678; +imm32 r3, 0x11001003; +imm32 r4, 0x11001004; +imm32 r5, 0x11001005; +imm32 r6, 0x11001006; +imm32 r7, 0x11001007; +A0 = R2; +R0.L = VIT_MAX( R0 ) (ASL); +R1.L = VIT_MAX( R1 ) (ASL); +R2.L = VIT_MAX( R2 ) (ASL); +R3.L = VIT_MAX( R3 ) (ASL); +R4.L = VIT_MAX( R4 ) (ASL); +R5.L = VIT_MAX( R5 ) (ASL); +R6.L = VIT_MAX( R6 ) (ASL); +R7.L = VIT_MAX( R7 ) (ASL); +CHECKREG r0, 0x11001100; +CHECKREG r1, 0x11001100; +CHECKREG r2, 0x12345678; +CHECKREG r3, 0x11001100; +CHECKREG r4, 0x11001100; +CHECKREG r5, 0x11001100; +CHECKREG r6, 0x11001100; +CHECKREG r7, 0x11001100; + +imm32 r0, 0xa1001001; +imm32 r1, 0x1b001001; +imm32 r2, 0x11c01002; +imm32 r3, 0x110d1003; +imm32 r4, 0x1100e004; +imm32 r5, 0x11001f05; +imm32 r6, 0x11001006; +imm32 r7, 0x11001001; +R1.L = VIT_MAX( R0 ) (ASL); +R2.L = VIT_MAX( R1 ) (ASL); +R3.L = VIT_MAX( R2 ) (ASL); +R4.L = VIT_MAX( R3 ) (ASL); +R5.L = VIT_MAX( R4 ) (ASL); +R6.L = VIT_MAX( R5 ) (ASL); +R7.L = VIT_MAX( R6 ) (ASL); +R0.L = VIT_MAX( R7 ) (ASL); +CHECKREG r0, 0xA1001B00; +CHECKREG r1, 0x1B001001; +CHECKREG r2, 0x11C01B00; +CHECKREG r3, 0x110D1B00; +CHECKREG r4, 0x11001B00; +CHECKREG r5, 0x11001B00; +CHECKREG r6, 0x11001B00; +CHECKREG r7, 0x11001B00; + + +imm32 r0, 0x20000000; +imm32 r1, 0x4300c001; +imm32 r2, 0x4040c002; +imm32 r3, 0x40056003; +imm32 r4, 0x4000c704; +imm32 r5, 0x4000c085; +imm32 r6, 0x4000c096; +imm32 r7, 0x4000c000; +R0.L = VIT_MAX( R0 ) (ASR); +R1.L = VIT_MAX( R1 ) (ASR); +R2.L = VIT_MAX( R2 ) (ASR); +R3.L = VIT_MAX( R3 ) (ASR); +R4.L = VIT_MAX( R4 ) (ASR); +R5.L = VIT_MAX( R5 ) (ASR); +R6.L = VIT_MAX( R6 ) (ASR); +R7.L = VIT_MAX( R7 ) (ASR); +CHECKREG r0, 0x20002000; +CHECKREG r1, 0x4300C001; +CHECKREG r2, 0x4040C002; +CHECKREG r3, 0x40056003; +CHECKREG r4, 0x40004000; +CHECKREG r5, 0x40004000; +CHECKREG r6, 0x40004000; +CHECKREG r7, 0x4000C000; + +imm32 r0, 0x10000000; +imm32 r1, 0x4200c001; +imm32 r2, 0x4030c002; +imm32 r3, 0x4004c003; +imm32 r4, 0x40005004; +imm32 r5, 0x4000c605; +imm32 r6, 0x4000c076; +imm32 r7, 0x4000c008; +R2.L = VIT_MAX( R0 ) (ASR); +R3.L = VIT_MAX( R1 ) (ASR); +R4.L = VIT_MAX( R2 ) (ASR); +R5.L = VIT_MAX( R3 ) (ASR); +R6.L = VIT_MAX( R4 ) (ASR); +R7.L = VIT_MAX( R5 ) (ASR); +R0.L = VIT_MAX( R6 ) (ASR); +R1.L = VIT_MAX( R7 ) (ASR); +CHECKREG r0, 0x10004030; +CHECKREG r1, 0x42004000; +CHECKREG r2, 0x40301000; +CHECKREG r3, 0x4004C001; +CHECKREG r4, 0x40004030; +CHECKREG r5, 0x4000C001; +CHECKREG r6, 0x40004030; +CHECKREG r7, 0x40004000; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shift_vmaxvmax.s b/sim/testsuite/bfin/c_dsp32shift_vmaxvmax.s new file mode 100644 index 0000000..0d4722a --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_vmaxvmax.s @@ -0,0 +1,113 @@ +//Original:/testcases/core/c_dsp32shift_vmaxvmax/c_dsp32shift_vmaxvmax.dsp +// Spec Reference: dsp32shift vmax / vmax +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x11002001; +imm32 r1, 0x12001001; +imm32 r2, 0x11301302; +imm32 r3, 0x43001003; +imm32 r4, 0x11601604; +imm32 r5, 0x71001705; +imm32 r6, 0x81008006; +imm32 r7, 0x1900b007; +A0 = R3; +R1 = VIT_MAX( R1 , R0 ) (ASL); +R2 = VIT_MAX( R2 , R1 ) (ASL); +R3 = VIT_MAX( R3 , R2 ) (ASL); +R4 = VIT_MAX( R4 , R3 ) (ASL); +R5 = VIT_MAX( R5 , R4 ) (ASL); +R6 = VIT_MAX( R6 , R5 ) (ASL); +R7 = VIT_MAX( R7 , R6 ) (ASL); +R0 = VIT_MAX( R0 , R7 ) (ASL); +CHECKREG r0, 0x20018100; +CHECKREG r1, 0x12002001; +CHECKREG r2, 0x13022001; +CHECKREG r3, 0x43002001; +CHECKREG r4, 0x16044300; +CHECKREG r5, 0x71004300; +CHECKREG r6, 0x81007100; +CHECKREG r7, 0x19008100; + +imm32 r0, 0x11002001; +imm32 r1, 0xd2001001; +imm32 r2, 0x14301302; +imm32 r3, 0x43001003; +imm32 r4, 0x11f01604; +imm32 r5, 0xb1001705; +imm32 r6, 0xd1008006; +imm32 r7, 0x39056707; +R1 = VIT_MAX( R1 , R3 ) (ASL); +R2 = VIT_MAX( R2 , R4 ) (ASL); +R3 = VIT_MAX( R3 , R6 ) (ASL); +R4 = VIT_MAX( R4 , R5 ) (ASL); +R5 = VIT_MAX( R5 , R7 ) (ASL); +R6 = VIT_MAX( R6 , R0 ) (ASL); +R7 = VIT_MAX( R7 , R1 ) (ASL); +R0 = VIT_MAX( R0 , R2 ) (ASL); +CHECKREG r0, 0x20011604; +CHECKREG r1, 0x10014300; +CHECKREG r2, 0x14301604; +CHECKREG r3, 0x4300D100; +CHECKREG r4, 0x16041705; +CHECKREG r5, 0x17056707; +CHECKREG r6, 0xD1002001; +CHECKREG r7, 0x67074300; + +imm32 r0, 0xa1011001; +imm32 r1, 0x1b002001; +imm32 r2, 0x81c01302; +imm32 r3, 0x910d1403; +imm32 r4, 0x2100e504; +imm32 r5, 0x31007f65; +imm32 r6, 0x41007006; +imm32 r7, 0x15001801; +R1 = VIT_MAX( R1 , R0 ) (ASR); +R2 = VIT_MAX( R2 , R1 ) (ASR); +R3 = VIT_MAX( R3 , R2 ) (ASR); +R4 = VIT_MAX( R4 , R3 ) (ASR); +R5 = VIT_MAX( R5 , R4 ) (ASR); +R6 = VIT_MAX( R6 , R5 ) (ASR); +R7 = VIT_MAX( R7 , R6 ) (ASR); +R0 = VIT_MAX( R0 , R7 ) (ASR); +CHECKREG r0, 0x1001910D; +CHECKREG r1, 0x20011001; +CHECKREG r2, 0x81C02001; +CHECKREG r3, 0x910D81C0; +CHECKREG r4, 0x2100910D; +CHECKREG r5, 0x7F65910D; +CHECKREG r6, 0x7006910D; +CHECKREG r7, 0x1801910D; + +imm32 r0, 0xe1011001; +imm32 r1, 0x4b002001; +imm32 r2, 0x8fc01302; +imm32 r3, 0x910d1403; +imm32 r4, 0xb100e504; +imm32 r5, 0x41007f65; +imm32 r6, 0xaf007006; +imm32 r7, 0x16001801; +R0 = VIT_MAX( R4 , R0 ) (ASR); +R1 = VIT_MAX( R5 , R1 ) (ASR); +R2 = VIT_MAX( R6 , R2 ) (ASR); +R3 = VIT_MAX( R7 , R3 ) (ASR); +R4 = VIT_MAX( R0 , R4 ) (ASR); +R5 = VIT_MAX( R1 , R5 ) (ASR); +R6 = VIT_MAX( R2 , R6 ) (ASR); +R7 = VIT_MAX( R3 , R7 ) (ASR); +CHECKREG r0, 0xE5041001; +CHECKREG r1, 0x7F654B00; +CHECKREG r2, 0xAF008FC0; +CHECKREG r3, 0x1801910D; +CHECKREG r4, 0x1001E504; +CHECKREG r5, 0x7F657F65; +CHECKREG r6, 0xAF00AF00; +CHECKREG r7, 0x910D1801; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_a0alr.s b/sim/testsuite/bfin/c_dsp32shiftim_a0alr.s new file mode 100644 index 0000000..13bd532 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_a0alr.s @@ -0,0 +1,213 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_a0alr/c_dsp32shiftim_a0alr.dsp +// Spec Reference: dsp32shift a0 ashift, lshift, rot +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x11140000; + imm32 r1, 0x012C003E; + imm32 r2, 0x81359E24; + imm32 r3, 0x81459E24; + imm32 r4, 0xD159E268; + imm32 r5, 0x51626AF2; + imm32 r6, 0x9176AF36; + imm32 r7, 0xE18BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = A0 << 0; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x012C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = A0 << 1; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x026B3C48; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = A0 << 15; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0xCF120000; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = A0 << 31; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x00000000; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = A0 >>> 1; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x28B13579; + + R5.L = -16; + A0 = 0; + A0.L = R6.L; + A0.H = R6.H; + A0 = A0 >>> 16; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x00009176; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = A0 >>> 31; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x00000001; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + .dw 0xC683 // .dw 0xC683 // A0 = A0 >>> 32; + .dw 0x0100 + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x00000000; + + imm32 r0, 0x12340000; + imm32 r1, 0x028C003E; + imm32 r2, 0x82159E24; + imm32 r3, 0x82159E24; + imm32 r4, 0xD259E268; + imm32 r5, 0x52E26AF2; + imm32 r6, 0x9226AF36; + imm32 r7, 0xE26BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = A0 << 0; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x028C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = A0 << 3; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x10ACF120; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = A0 << 15; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0xCF120000; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = A0 << 31; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x00000000; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = A0 >> 1; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x29713579; + + R5.L = -16; + A0 = 0; + A0.L = R6.L; + A0.H = R6.H; + A0 = A0 >> 16; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x00009226; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = A0 >> 31; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x00000001; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + .dw 0xC683 + .dw 0x4100 // A0 = A0 >> 32; + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x00000000; + + imm32 r0, 0x13340000; + imm32 r1, 0x038C003E; + imm32 r2, 0x83159E24; + imm32 r3, 0x83159E24; + imm32 r4, 0xD359E268; + imm32 r5, 0x53E26AF2; + imm32 r6, 0x9326AF36; + imm32 r7, 0xE36BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = ROT A0 BY 0; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x038C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = ROT A0 BY 1; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x062B3C48; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = ROT A0 BY 15; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0xCF120060; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = ROT A0 BY 31; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x62B4D678; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = ROT A0 BY -1; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x29F13579; + + R5.L = -16; + A0.L = R6.L; + A0.H = R6.H; + A0 = ROT A0 BY -16; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x6C9A9326; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = ROT A0 BY -31; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0xAFFE1ABD; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + A0 = ROT A0 BY -32; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x6800018D; + + pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_af.s b/sim/testsuite/bfin/c_dsp32shiftim_af.s new file mode 100644 index 0000000..1c994f4 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_af.s @@ -0,0 +1,63 @@ +//Original:/testcases/core/c_dsp32shiftim_af/c_dsp32shiftim_af.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: ashift + + +imm32 r0, 0xa1230001; +imm32 r1, 0x1b345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x34d6789a; +imm32 r4, 0x85a789ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb8912cde; +R0 = R0 << 0; +R1 = R1 << 3; +R2 = R2 << 7; +R3 = R3 << 8; +R4 = R4 << 15; +R5 = R5 << 24; +R6 = R6 << 31; +R7 = R7 << 20; +CHECKREG r0, 0xA1230001; +CHECKREG r1, 0xD9A2B3C0; +CHECKREG r2, 0xE2B3C480; +CHECKREG r3, 0xD6789A00; +CHECKREG r4, 0xC4D58000; +CHECKREG r5, 0xBC000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0xCDE00000; + +imm32 r0, 0xa1230001; +imm32 r1, 0x1b345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x34d6789a; +imm32 r4, 0x85a789ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb8912cde; +R6 = R0 >>> 1; +R7 = R1 >>> 3; +R0 = R2 >>> 7; +R1 = R3 >>> 8; +R2 = R4 >>> 15; +R3 = R5 >>> 24; +R4 = R6 >>> 31; +R5 = R7 >>> 20; +CHECKREG r0, 0x00478ACF; +CHECKREG r1, 0x0034D678; +CHECKREG r2, 0xFFFF0B4F; +CHECKREG r3, 0xFFFFFF96; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0x00000036; +CHECKREG r6, 0xD0918000; +CHECKREG r7, 0x03668ACF; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_af_s.s b/sim/testsuite/bfin/c_dsp32shiftim_af_s.s new file mode 100644 index 0000000..5fdf02a --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_af_s.s @@ -0,0 +1,63 @@ +//Original:/testcases/core/c_dsp32shiftim_af_s/c_dsp32shiftim_af_s.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: ashift saturated + + +imm32 r0, 0x81230001; +imm32 r1, 0x19345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x3ed6789a; +imm32 r4, 0x85d789ab; +imm32 r5, 0x967f9abc; +imm32 r6, 0xa789bbcd; +imm32 r7, 0xb891acde; +R0 = R0 << 0 (S); +R1 = R1 << 3 (S); +R2 = R2 << 7 (S); +R3 = R3 << 8 (S); +R4 = R4 << 15 (S); +R5 = R5 << 24 (S); +R6 = R6 << 31 (S); +R7 = R7 << 20 (S); +CHECKREG r0, 0x81230001; +CHECKREG r1, 0x7FFFFFFF; +CHECKREG r2, 0x7FFFFFFF; +CHECKREG r3, 0x7FFFFFFF; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + +imm32 r0, 0xa1230001; +imm32 r1, 0x1e345678; +imm32 r2, 0x23f56789; +imm32 r3, 0x34db789a; +imm32 r4, 0x85a7a9ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa78dabcd; +imm32 r7, 0xb8914cde; +R6 = R0 >>> 1; +R7 = R1 >>> 3; +R0 = R2 >>> 7; +R1 = R3 >>> 8; +R2 = R4 >>> 15; +R3 = R5 >>> 24; +R4 = R6 >>> 31; +R5 = R7 >>> 20; +CHECKREG r0, 0x0047EACF; +CHECKREG r1, 0x0034DB78; +CHECKREG r2, 0xFFFF0B4F; +CHECKREG r3, 0xFFFFFF96; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0x0000003C; +CHECKREG r6, 0xD0918000; +CHECKREG r7, 0x03C68ACF; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln.s b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln.s new file mode 100644 index 0000000..e911d3a --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln.s @@ -0,0 +1,406 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_ln/c_dsp32shiftim_ahalf_ln.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + +// Ashift : neg data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x1000c000; +imm32 r1, 0x1000c001; +imm32 r2, 0x1000c002; +imm32 r3, 0x1000c003; +imm32 r4, 0x1000c004; +imm32 r5, 0x1000c005; +imm32 r6, 0x1000c006; +imm32 r7, 0x1000c007; +R0.L = R0.L << 1; +R1.L = R1.L << 1; +R2.L = R2.L << 1; +R3.L = R3.L << 1; +R4.L = R4.L << 1; +R5.L = R5.L << 1; +R6.L = R6.L << 1; +R7.L = R7.L << 1; +CHECKREG r0, 0x10008000; +CHECKREG r1, 0x10008002; +CHECKREG r2, 0x10008004; +CHECKREG r3, 0x10008006; +CHECKREG r4, 0x10008008; +CHECKREG r5, 0x1000800A; +CHECKREG r6, 0x1000800C; +CHECKREG r7, 0x1000800E; + +imm32 r0, 0x20008001; +imm32 r1, 0x20000001; +imm32 r2, 0x2000d002; +imm32 r3, 0x2000e003; +imm32 r4, 0x2000f004; +imm32 r5, 0x2000c005; +imm32 r6, 0x2000d006; +imm32 r7, 0x2000e007; +R7.L = R0.L << 1; +R6.L = R1.L << 1; +R5.L = R2.L << 1; +R4.L = R3.L << 1; +R3.L = R4.L << 1; +R2.L = R5.L << 1; +R1.L = R6.L << 1; +R0.L = R7.L << 1; + +imm32 r0, 0x3000c001; +imm32 r1, 0x3000d001; +imm32 r2, 0x3000000f; +imm32 r3, 0x3000e003; +imm32 r4, 0x3000f004; +imm32 r5, 0x3000f005; +imm32 r6, 0x3000f006; +imm32 r7, 0x3000f007; +R6.L = R0.L << 12; +R7.L = R1.L << 12; +R5.L = R2.L << 12; +R4.L = R3.L << 12; +R3.L = R4.L << 12; +R2.L = R5.L << 12; +R1.L = R6.L << 12; +R0.L = R7.L << 12; +CHECKREG r1, 0x30000000; +CHECKREG r0, 0x30000000; +CHECKREG r2, 0x30000000; +CHECKREG r3, 0x30000000; +CHECKREG r4, 0x30003000; +CHECKREG r5, 0x3000F000; +CHECKREG r6, 0x30001000; +CHECKREG r7, 0x30001000; + +imm32 r0, 0x40009001; +imm32 r1, 0x4000a001; +imm32 r2, 0x4000b002; +imm32 r3, 0x40000010; +imm32 r4, 0x4000c004; +imm32 r5, 0x4000d005; +imm32 r6, 0x4000e006; +imm32 r7, 0x4000f007; +R5.L = R0.L << 13; +R6.L = R1.L << 13; +R7.L = R2.L << 13; +R0.L = R3.L << 13; +R1.L = R4.L << 13; +R2.L = R5.L << 13; +R3.L = R6.L << 13; +R4.L = R7.L << 13; +CHECKREG r0, 0x40000000; +CHECKREG r1, 0x40008000; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0x40000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x40002000; +CHECKREG r6, 0x40002000; +CHECKREG r7, 0x40004000; + +imm32 r0, 0x00005000; +imm32 r1, 0x00015000; +imm32 r2, 0x00025000; +imm32 r3, 0x00035000; +imm32 r4, 0x00045000; +imm32 r5, 0x00055000; +imm32 r6, 0x00065000; +imm32 r7, 0x00075500; +R0.L = R0.H << 10; +R1.L = R1.H << 10; +R2.L = R2.H << 10; +R3.L = R3.H << 10; +R4.L = R4.H << 10; +R5.L = R5.H << 10; +R6.L = R6.H << 10; +R7.L = R7.H << 10; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010400; +CHECKREG r2, 0x00020800; +CHECKREG r3, 0x00030C00; +CHECKREG r4, 0x00041000; +CHECKREG r5, 0x00051400; +CHECKREG r6, 0x00061800; +CHECKREG r7, 0x00071C00; + +imm32 r0, 0x90010000; +imm32 r1, 0x90010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R2.L = R0.H << 11; +R3.L = R1.H << 11; +R4.L = R2.H << 11; +R5.L = R3.H << 11; +R6.L = R4.H << 11; +R7.L = R5.H << 11; +R0.L = R6.H << 11; +R1.L = R7.H << 11; +CHECKREG r0, 0x90013000; +CHECKREG r1, 0x90013800; +CHECKREG r2, 0x90020800; +CHECKREG r3, 0x90030800; +CHECKREG r4, 0x90041000; +CHECKREG r5, 0x90051800; +CHECKREG r6, 0x90062000; +CHECKREG r7, 0x90072800; + + +imm32 r0, 0xa0010600; +imm32 r1, 0xa0010600; +imm32 r2, 0xa002060f; +imm32 r3, 0xa0030600; +imm32 r4, 0xa0040600; +imm32 r5, 0xa0050600; +imm32 r6, 0xa0060600; +imm32 r7, 0xa0070600; +R0.L = R0.H << 12; +R1.L = R1.H << 12; +R2.L = R2.H << 12; +R3.L = R3.H << 12; +R4.L = R4.H << 12; +R5.L = R5.H << 12; +R6.L = R6.H << 12; +R7.L = R7.H << 12; +CHECKREG r0, 0xA0011000; +CHECKREG r1, 0xA0011000; +CHECKREG r2, 0xA0022000; +CHECKREG r3, 0xA0033000; +CHECKREG r4, 0xA0044000; +CHECKREG r5, 0xA0055000; +CHECKREG r6, 0xA0066000; +CHECKREG r7, 0xA0077000; + +imm32 r0, 0xc0010701; +imm32 r1, 0xc0010701; +imm32 r2, 0xc0020702; +imm32 r3, 0xc0030710; +imm32 r4, 0xc0040704; +imm32 r5, 0xc0050705; +imm32 r6, 0xc0060706; +imm32 r7, 0xc0070707; +R0.L = R0.H << 13; +R1.L = R1.H << 13; +R2.L = R2.H << 13; +R3.L = R3.H << 13; +R4.L = R4.H << 13; +R5.L = R5.H << 13; +R6.L = R6.H << 13; +R7.L = R7.H << 13; +CHECKREG r0, 0xC0012000; +CHECKREG r1, 0xC0012000; +CHECKREG r2, 0xC0024000; +CHECKREG r3, 0xC0036000; +CHECKREG r4, 0xC0048000; +CHECKREG r5, 0xC005A000; +CHECKREG r6, 0xC006C000; +CHECKREG r7, 0xC007E000; + +imm32 r0, 0x00008000; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = R0.L << 0; +R1.H = R1.L << 1; +R2.H = R2.L << 2; +R3.H = R3.L << 3; +R4.H = R4.L << 4; +R5.H = R5.L << 5; +R6.H = R6.L << 6; +R7.H = R7.L << 7; +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x00028001; +CHECKREG r2, 0x00088002; +CHECKREG r3, 0x00188003; +CHECKREG r4, 0x00408004; +CHECKREG r5, 0x00A08005; +CHECKREG r6, 0x01808006; +CHECKREG r7, 0x03808007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R2.H = R0.L << 8; +R3.H = R1.L << 9; +R4.H = R2.L << 10; +R5.H = R3.L << 11; +R6.H = R4.L << 12; +R7.H = R5.L << 13; +R0.H = R6.L << 14; +R1.H = R7.L << 15; +CHECKREG r0, 0x8000D001; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x0100D002; +CHECKREG r3, 0x0200D003; +CHECKREG r4, 0x0800D004; +CHECKREG r5, 0x1800D005; +CHECKREG r6, 0x4000D006; +CHECKREG r7, 0xA000D007; + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = R0.L << 12; +R1.H = R1.L << 12; +R2.H = R2.L << 12; +R3.H = R3.L << 12; +R4.H = R4.L << 12; +R5.H = R5.L << 12; +R6.H = R6.L << 12; +R7.H = R7.L << 12; +CHECKREG r0, 0x1000E001; +CHECKREG r1, 0x1000E001; +CHECKREG r2, 0xF000000F; +CHECKREG r3, 0x3000E003; +CHECKREG r4, 0x4000E004; +CHECKREG r5, 0x5000E005; +CHECKREG r6, 0x6000E006; +CHECKREG r7, 0x7000E007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R5.H = R0.L << 13; +R6.H = R1.L << 13; +R7.H = R2.L << 13; +R0.H = R3.L << 13; +R1.H = R4.L << 13; +R2.H = R5.L << 13; +R3.H = R6.L << 13; +R4.H = R7.L << 13; +CHECKREG r0, 0x0000F001; +CHECKREG r1, 0x8000F001; +CHECKREG r2, 0xA000F002; +CHECKREG r3, 0xC0000010; +CHECKREG r4, 0xE000F004; +CHECKREG r5, 0x2000F005; +CHECKREG r6, 0x2000F006; +CHECKREG r7, 0x4000F007; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x90000000; +imm32 r1, 0x90010000; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R4.H = R0.H << 10; +R5.H = R1.H << 10; +R6.H = R2.H << 10; +R7.H = R3.H << 10; +R0.H = R4.H << 10; +R1.H = R5.H << 10; +R2.H = R6.H << 10; +R3.H = R7.H << 10; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x04000000; +CHECKREG r6, 0x08000000; +CHECKREG r7, 0x0C000000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R7.H = R0.H << 11; +R0.H = R1.H << 11; +R1.H = R2.H << 11; +R2.H = R3.H << 11; +R3.H = R4.H << 11; +R4.H = R5.H << 11; +R5.H = R6.H << 11; +R6.H = R7.H << 11; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x10000001; +CHECKREG r2, 0x18000000; +CHECKREG r3, 0x20000000; +CHECKREG r4, 0x28000000; +CHECKREG r5, 0x30000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x08000000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R6.H = R0.H << 12; +R7.H = R1.H << 12; +R0.H = R2.H << 12; +R1.H = R3.H << 12; +R2.H = R4.H << 12; +R3.H = R5.H << 12; +R4.H = R6.H << 12; +R5.H = R7.H << 12; +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x30000000; +CHECKREG r2, 0x4000000F; +CHECKREG r3, 0x50000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x10000000; +CHECKREG r7, 0x10000000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R5.H = R0.H << 3; +R6.H = R1.H << 3; +R7.H = R2.H << 3; +R0.H = R3.H << 3; +R1.H = R4.H << 3; +R2.H = R5.H << 3; +R3.H = R6.H << 3; +R4.H = R7.H << 3; +CHECKREG r0, 0x80180000; +CHECKREG r1, 0x80200000; +CHECKREG r2, 0x00400000; +CHECKREG r3, 0x00400010; +CHECKREG r4, 0x00800000; +CHECKREG r5, 0x80080000; +CHECKREG r6, 0x80080000; +CHECKREG r7, 0x80100000; +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln_s.s b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln_s.s new file mode 100644 index 0000000..aa28f3f --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln_s.s @@ -0,0 +1,408 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_ln_s/c_dsp32shiftim_ahalf_ln_s.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : neg data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x1000c000; +imm32 r1, 0x1000c001; +imm32 r2, 0x1000c002; +imm32 r3, 0x1000c003; +imm32 r4, 0x1000c004; +imm32 r5, 0x1000c005; +imm32 r6, 0x1000c006; +imm32 r7, 0x1000c007; +R0.L = R0.L << 1 (S); +R1.L = R1.L << 1 (S); +R2.L = R2.L << 1 (S); +R3.L = R3.L << 1 (S); +R4.L = R4.L << 1 (S); +R5.L = R5.L << 1 (S); +R6.L = R6.L << 1 (S); +R7.L = R7.L << 1 (S); +CHECKREG r0, 0x10008000; +CHECKREG r1, 0x10008002; +CHECKREG r2, 0x10008004; +CHECKREG r3, 0x10008006; +CHECKREG r4, 0x10008008; +CHECKREG r5, 0x1000800A; +CHECKREG r6, 0x1000800C; +CHECKREG r7, 0x1000800E; + +imm32 r0, 0x20008001; +imm32 r1, 0x20000001; +imm32 r2, 0x2000d002; +imm32 r3, 0x2000e003; +imm32 r4, 0x2000f004; +imm32 r5, 0x2000c005; +imm32 r6, 0x2000d006; +imm32 r7, 0x2000e007; +R7.L = R0.L << 1 (S); +R6.L = R1.L << 1 (S); +R5.L = R2.L << 1 (S); +R4.L = R3.L << 1 (S); +R3.L = R4.L << 1 (S); +R2.L = R5.L << 1 (S); +R1.L = R6.L << 1 (S); +R0.L = R7.L << 1 (S); + +imm32 r0, 0x3000c001; +imm32 r1, 0x3000d001; +imm32 r2, 0x3000000f; +imm32 r3, 0x3000e003; +imm32 r4, 0x3000f004; +imm32 r5, 0x3000f005; +imm32 r6, 0x3000f006; +imm32 r7, 0x3000f007; +R6.L = R0.L << 12 (S); +R7.L = R1.L << 12 (S); +R5.L = R2.L << 12 (S); +R4.L = R3.L << 12 (S); +R3.L = R4.L << 12 (S); +R2.L = R5.L << 12 (S); +R1.L = R6.L << 12 (S); +R0.L = R7.L << 12 (S); +CHECKREG r1, 0x30008000; +CHECKREG r0, 0x30008000; +CHECKREG r2, 0x30007FFF; +CHECKREG r3, 0x30008000; +CHECKREG r4, 0x30008000; +CHECKREG r5, 0x30007FFF; +CHECKREG r6, 0x30008000; +CHECKREG r7, 0x30008000; + +imm32 r0, 0x40009001; +imm32 r1, 0x4000a001; +imm32 r2, 0x4000b002; +imm32 r3, 0x40000010; +imm32 r4, 0x4000c004; +imm32 r5, 0x4000d005; +imm32 r6, 0x4000e006; +imm32 r7, 0x4000f007; +R5.L = R0.L << 13 (S); +R6.L = R1.L << 13 (S); +R7.L = R2.L << 13 (S); +R0.L = R3.L << 13 (S); +R1.L = R4.L << 13 (S); +R2.L = R5.L << 13 (S); +R3.L = R6.L << 13 (S); +R4.L = R7.L << 13 (S); +CHECKREG r0, 0x40007FFF; +CHECKREG r1, 0x40008000; +CHECKREG r2, 0x40008000; +CHECKREG r3, 0x40008000; +CHECKREG r4, 0x40008000; +CHECKREG r5, 0x40008000; +CHECKREG r6, 0x40008000; +CHECKREG r7, 0x40008000; + +imm32 r0, 0x00005000; +imm32 r1, 0x00015000; +imm32 r2, 0x00025000; +imm32 r3, 0x00035000; +imm32 r4, 0x00045000; +imm32 r5, 0x00055000; +imm32 r6, 0x00065000; +imm32 r7, 0x00075500; +R0.L = R0.H << 10 (S); +R1.L = R1.H << 10 (S); +R2.L = R2.H << 10 (S); +R3.L = R3.H << 10 (S); +R4.L = R4.H << 10 (S); +R5.L = R5.H << 10 (S); +R6.L = R6.H << 10 (S); +R7.L = R7.H << 10 (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010400; +CHECKREG r2, 0x00020800; +CHECKREG r3, 0x00030C00; +CHECKREG r4, 0x00041000; +CHECKREG r5, 0x00051400; +CHECKREG r6, 0x00061800; +CHECKREG r7, 0x00071C00; + +imm32 r0, 0x90010000; +imm32 r1, 0x90010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R2.L = R0.H << 11 (S); +R3.L = R1.H << 11 (S); +R4.L = R2.H << 11 (S); +R5.L = R3.H << 11 (S); +R6.L = R4.H << 11 (S); +R7.L = R5.H << 11 (S); +R0.L = R6.H << 11 (S); +R1.L = R7.H << 11 (S); +CHECKREG r0, 0x90018000; +CHECKREG r1, 0x90018000; +CHECKREG r2, 0x90028000; +CHECKREG r3, 0x90038000; +CHECKREG r4, 0x90048000; +CHECKREG r5, 0x90058000; +CHECKREG r6, 0x90068000; +CHECKREG r7, 0x90078000; + + +imm32 r0, 0xa0010600; +imm32 r1, 0xa0010600; +imm32 r2, 0xa002060f; +imm32 r3, 0xa0030600; +imm32 r4, 0xa0040600; +imm32 r5, 0xa0050600; +imm32 r6, 0xa0060600; +imm32 r7, 0xa0070600; +R0.L = R0.H << 12 (S); +R1.L = R1.H << 12 (S); +R2.L = R2.H << 12 (S); +R3.L = R3.H << 12 (S); +R4.L = R4.H << 12 (S); +R5.L = R5.H << 12 (S); +R6.L = R6.H << 12 (S); +R7.L = R7.H << 12 (S); +CHECKREG r0, 0xA0018000; +CHECKREG r1, 0xA0018000; +CHECKREG r2, 0xA0028000; +CHECKREG r3, 0xA0038000; +CHECKREG r4, 0xA0048000; +CHECKREG r5, 0xA0058000; +CHECKREG r6, 0xA0068000; +CHECKREG r7, 0xA0078000; + +imm32 r0, 0xc0010701; +imm32 r1, 0xc0010701; +imm32 r2, 0xc0020702; +imm32 r3, 0xc0030710; +imm32 r4, 0xc0040704; +imm32 r5, 0xc0050705; +imm32 r6, 0xc0060706; +imm32 r7, 0xc0070707; +R0.L = R0.H << 13 (S); +R1.L = R1.H << 13 (S); +R2.L = R2.H << 13 (S); +R3.L = R3.H << 13 (S); +R4.L = R4.H << 13 (S); +R5.L = R5.H << 13 (S); +R6.L = R6.H << 13 (S); +R7.L = R7.H << 13 (S); +CHECKREG r0, 0xC0018000; +CHECKREG r1, 0xC0018000; +CHECKREG r2, 0xC0028000; +CHECKREG r3, 0xC0038000; +CHECKREG r4, 0xC0048000; +CHECKREG r5, 0xC0058000; +CHECKREG r6, 0xC0068000; +CHECKREG r7, 0xC0078000; + +imm32 r0, 0x00008000; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = R0.L << 0 (S); +R1.H = R1.L << 1 (S); +R2.H = R2.L << 2 (S); +R3.H = R3.L << 3 (S); +R4.H = R4.L << 4 (S); +R5.H = R5.L << 5 (S); +R6.H = R6.L << 6 (S); +R7.H = R7.L << 7 (S); +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x80008001; +CHECKREG r2, 0x80008002; +CHECKREG r3, 0x80008003; +CHECKREG r4, 0x80008004; +CHECKREG r5, 0x80008005; +CHECKREG r6, 0x80008006; +CHECKREG r7, 0x80008007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R2.H = R0.L << 8 (S); +R3.H = R1.L << 9 (S); +R4.H = R2.L << 10 (S); +R5.H = R3.L << 11 (S); +R6.H = R4.L << 12 (S); +R7.H = R5.L << 13 (S); +R0.H = R6.L << 14 (S); +R1.H = R7.L << 15 (S); +CHECKREG r0, 0x8000D001; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x8000D002; +CHECKREG r3, 0x0200D003; +CHECKREG r4, 0x8000D004; +CHECKREG r5, 0x8000D005; +CHECKREG r6, 0x8000D006; +CHECKREG r7, 0x8000D007; + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = R0.L << 12 (S); +R1.H = R1.L << 12 (S); +R2.H = R2.L << 12 (S); +R3.H = R3.L << 12 (S); +R4.H = R4.L << 12 (S); +R5.H = R5.L << 12 (S); +R6.H = R6.L << 12 (S); +R7.H = R7.L << 12 (S); +CHECKREG r0, 0x8000E001; +CHECKREG r1, 0x8000E001; +CHECKREG r2, 0x7FFF000F; +CHECKREG r3, 0x8000E003; +CHECKREG r4, 0x8000E004; +CHECKREG r5, 0x8000E005; +CHECKREG r6, 0x8000E006; +CHECKREG r7, 0x8000E007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R5.H = R0.L << 13 (S); +R6.H = R1.L << 13 (S); +R7.H = R2.L << 13 (S); +R0.H = R3.L << 13 (S); +R1.H = R4.L << 13 (S); +R2.H = R5.L << 13 (S); +R3.H = R6.L << 13 (S); +R4.H = R7.L << 13 (S); +CHECKREG r0, 0x7FFFF001; +CHECKREG r1, 0x8000F001; +CHECKREG r2, 0x8000F002; +CHECKREG r3, 0x80000010; +CHECKREG r4, 0x8000F004; +CHECKREG r5, 0x8000F005; +CHECKREG r6, 0x8000F006; +CHECKREG r7, 0x8000F007; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x90000000; +imm32 r1, 0x90010000; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R4.H = R0.H << 10 (S); +R5.H = R1.H << 10 (S); +R6.H = R2.H << 10 (S); +R7.H = R3.H << 10 (S); +R0.H = R4.H << 10 (S); +R1.H = R5.H << 10 (S); +R2.H = R6.H << 10 (S); +R3.H = R7.H << 10 (S); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x80000000; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R7.H = R0.H << 11 (S); +R0.H = R1.H << 11 (S); +R1.H = R2.H << 11 (S); +R2.H = R3.H << 11 (S); +R3.H = R4.H << 11 (S); +R4.H = R5.H << 11 (S); +R5.H = R6.H << 11 (S); +R6.H = R7.H << 11 (S); +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R6.H = R0.H << 12 (S); +R7.H = R1.H << 12 (S); +R0.H = R2.H << 12 (S); +R1.H = R3.H << 12 (S); +R2.H = R4.H << 12 (S); +R3.H = R5.H << 12 (S); +R4.H = R6.H << 12 (S); +R5.H = R7.H << 12 (S); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x80000000; +CHECKREG r2, 0x8000000F; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R5.H = R0.H << 3 (S); +R6.H = R1.H << 3 (S); +R7.H = R2.H << 3 (S); +R0.H = R3.H << 3 (S); +R1.H = R4.H << 3 (S); +R2.H = R5.H << 3 (S); +R3.H = R6.H << 3 (S); +R4.H = R7.H << 3 (S); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x80000000; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x80000010; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_ahalf_lp.s b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_lp.s new file mode 100644 index 0000000..44e8882 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_lp.s @@ -0,0 +1,418 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_lp/c_dsp32shiftim_ahalf_lp.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x01010100; +imm32 r1, 0x01020101; +imm32 r2, 0x01030102; +imm32 r3, 0x01040103; +imm32 r4, 0x01050104; +imm32 r5, 0x01060105; +imm32 r6, 0x01070106; +imm32 r7, 0x01080107; +R0.L = R0.L << 0; +R1.L = R1.L << 1; +R2.L = R2.L << 2; +R3.L = R3.L << 3; +R4.L = R4.L << 4; +R5.L = R5.L << 5; +R6.L = R6.L << 6; +R7.L = R7.L << 7; +CHECKREG r0, 0x01010100; +CHECKREG r1, 0x01020202; +CHECKREG r2, 0x01030408; +CHECKREG r3, 0x01040818; +CHECKREG r4, 0x01051040; +CHECKREG r5, 0x010620A0; +CHECKREG r6, 0x01074180; +CHECKREG r7, 0x01088380; + +imm32 r0, 0x00090201; +imm32 r1, 0x00100201; +imm32 r2, 0x00110202; +imm32 r3, 0x00120203; +imm32 r4, 0x00130204; +imm32 r5, 0x00140205; +imm32 r6, 0x00150206; +imm32 r7, 0x00160207; +R7.L = R0.L << 8; +R6.L = R1.L << 9; +R5.L = R2.L << 10; +R4.L = R3.L << 11; +R3.L = R4.L << 12; +R2.L = R5.L << 13; +R1.L = R6.L << 14; +R0.L = R7.L << 15; +CHECKREG r1, 0x00100000; +CHECKREG r0, 0x00090000; +CHECKREG r2, 0x00110000; +CHECKREG r3, 0x00120000; +CHECKREG r4, 0x00131800; +CHECKREG r5, 0x00140800; +CHECKREG r6, 0x00150200; +CHECKREG r7, 0x00160100; + + +imm32 r0, 0x00170401; +imm32 r1, 0x00180401; +imm32 r2, 0x0019040f; +imm32 r3, 0x00200403; +imm32 r4, 0x00210404; +imm32 r5, 0x00220405; +imm32 r6, 0x00230406; +imm32 r7, 0x00244407; +R6.L = R0.L << 15; +R5.L = R1.L << 15; +R4.L = R2.L << 15; +R3.L = R3.L << 15; +R2.L = R4.L << 15; +R1.L = R5.L << 15; +R0.L = R6.L << 15; +R7.L = R7.L << 15; +CHECKREG r0, 0x00170000; +CHECKREG r1, 0x00180000; +CHECKREG r2, 0x00190000; +CHECKREG r3, 0x00208000; +CHECKREG r4, 0x00218000; +CHECKREG r5, 0x00228000; +CHECKREG r6, 0x00238000; +CHECKREG r7, 0x00248000; + +imm32 r0, 0x00005001; +imm32 r1, 0x00005001; +imm32 r2, 0x00005002; +imm32 r3, 0x00005010; +imm32 r4, 0x00005004; +imm32 r5, 0x00005005; +imm32 r6, 0x00000506; +imm32 r7, 0x00000507; +R5.L = R0.L << 13; +R6.L = R1.L << 13; +R7.L = R2.L << 13; +R0.L = R3.L << 13; +R1.L = R4.L << 13; +R2.L = R5.L << 13; +R3.L = R6.L << 13; +R4.L = R7.L << 13; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00002000; +CHECKREG r6, 0x00002000; +CHECKREG r7, 0x00004000; + +// RHx by RLx +imm32 r0, 0x00006010; +imm32 r1, 0x00016020; +imm32 r2, 0x00026030; +imm32 r3, 0x00036040; +imm32 r4, 0x00046050; +imm32 r5, 0x00056060; +imm32 r6, 0x00066070; +imm32 r7, 0x00076080; +R0.L = R0.H << 10; +R1.L = R1.H << 10; +R2.L = R2.H << 10; +R3.L = R3.H << 10; +R4.L = R4.H << 10; +R5.L = R5.H << 10; +R6.L = R6.H << 10; +R7.L = R7.H << 10; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010400; +CHECKREG r2, 0x00020800; +CHECKREG r3, 0x00030C00; +CHECKREG r4, 0x00041000; +CHECKREG r5, 0x00051400; +CHECKREG r6, 0x00061800; +CHECKREG r7, 0x00071C00; + +imm32 r0, 0x00010090; +imm32 r1, 0x00010111; +imm32 r2, 0x00020120; +imm32 r3, 0x00030130; +imm32 r4, 0x00040140; +imm32 r5, 0x00050150; +imm32 r6, 0x00060160; +imm32 r7, 0x00070170; +R1.L = R0.H << 1; +R2.L = R1.H << 1; +R3.L = R2.H << 1; +R4.L = R3.H << 1; +R5.L = R4.H << 1; +R6.L = R5.H << 1; +R7.L = R6.H << 1; +R0.L = R7.H << 1; +CHECKREG r1, 0x00010002; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030004; +CHECKREG r4, 0x00040006; +CHECKREG r5, 0x00050008; +CHECKREG r6, 0x0006000A; +CHECKREG r7, 0x0007000C; +CHECKREG r0, 0x0001000E; + + +imm32 r0, 0x0a010000; +imm32 r1, 0x0b010000; +imm32 r2, 0x0c02000f; +imm32 r3, 0x0d030000; +imm32 r4, 0x0e040000; +imm32 r5, 0x0f050000; +imm32 r6, 0x01060000; +imm32 r7, 0x02070000; +R2.L = R0.H << 12; +R3.L = R1.H << 12; +R4.L = R2.H << 12; +R5.L = R3.H << 12; +R6.L = R4.H << 12; +R7.L = R5.H << 12; +R0.L = R6.H << 12; +R1.L = R7.H << 12; +CHECKREG r0, 0x0A016000; +CHECKREG r1, 0x0B017000; +CHECKREG r2, 0x0C021000; +CHECKREG r3, 0x0D031000; +CHECKREG r4, 0x0E042000; +CHECKREG r5, 0x0F053000; +CHECKREG r6, 0x01064000; +CHECKREG r7, 0x02075000; + +imm32 r0, 0x01010001; +imm32 r1, 0x02010001; +imm32 r2, 0x03020002; +imm32 r3, 0x04030010; +imm32 r4, 0x05040004; +imm32 r5, 0x06050005; +imm32 r6, 0x07060006; +imm32 r7, 0x08070007; +R3.L = R0.H << 13; +R4.L = R1.H << 13; +R5.L = R2.H << 13; +R6.L = R3.H << 13; +R7.L = R4.H << 13; +R0.L = R5.H << 13; +R1.L = R6.H << 13; +R2.L = R7.H << 13; +CHECKREG r0, 0x0101A000; +CHECKREG r1, 0x0201C000; +CHECKREG r2, 0x0302E000; +CHECKREG r3, 0x04032000; +CHECKREG r4, 0x05042000; +CHECKREG r5, 0x06054000; +CHECKREG r6, 0x07066000; +CHECKREG r7, 0x08078000; + +// RLx by RLx +imm32 r0, 0xa0000400; +imm32 r1, 0xbb000401; +imm32 r2, 0xc0000402; +imm32 r3, 0xd0000403; +imm32 r4, 0xe0000404; +imm32 r5, 0xf0000405; +imm32 r6, 0x10000406; +imm32 r7, 0x20000407; +R0.H = R0.L << 14; +R1.H = R1.L << 14; +R2.H = R2.L << 14; +R3.H = R3.L << 14; +R4.H = R4.L << 14; +R5.H = R5.L << 14; +R6.H = R6.L << 14; +R7.H = R7.L << 14; +CHECKREG r0, 0x00000400; +CHECKREG r1, 0x40000401; +CHECKREG r2, 0x80000402; +CHECKREG r3, 0xC0000403; +CHECKREG r4, 0x00000404; +CHECKREG r5, 0x40000405; +CHECKREG r6, 0x80000406; +CHECKREG r7, 0xC0000407; + +imm32 r0, 0x0a000001; +imm32 r1, 0x0b000001; +imm32 r2, 0x0cd00002; +imm32 r3, 0x0d000003; +imm32 r4, 0x0e000004; +imm32 r5, 0x0f000005; +imm32 r6, 0x03000006; +imm32 r7, 0x04000007; +R1.H = R0.L << 15; +R2.H = R1.L << 15; +R3.H = R2.L << 15; +R4.H = R3.L << 15; +R5.H = R4.L << 15; +R6.H = R5.L << 15; +R7.H = R6.L << 15; +R0.H = R7.L << 15; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x80000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x80000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x80000006; +CHECKREG r7, 0x00000007; +CHECKREG r0, 0x80000001; + + +imm32 r0, 0x10000001; +imm32 r1, 0x02000001; +imm32 r2, 0x0300000f; +imm32 r3, 0x04000003; +imm32 r4, 0x05000004; +imm32 r5, 0x06000005; +imm32 r6, 0x07000006; +imm32 r7, 0x00800007; +R2.H = R0.L << 2; +R3.H = R1.L << 2; +R4.H = R2.L << 2; +R5.H = R3.L << 2; +R6.H = R4.L << 2; +R7.H = R5.L << 2; +R0.H = R6.L << 2; +R1.H = R7.L << 2; +CHECKREG r0, 0x00180001; +CHECKREG r1, 0x001C0001; +CHECKREG r2, 0x0004000F; +CHECKREG r3, 0x00040003; +CHECKREG r4, 0x003C0004; +CHECKREG r5, 0x000C0005; +CHECKREG r6, 0x00100006; +CHECKREG r7, 0x00140007; + +imm32 r0, 0x00000801; +imm32 r1, 0x00000801; +imm32 r2, 0x00000802; +imm32 r3, 0x00000810; +imm32 r4, 0x00000804; +imm32 r5, 0x00000805; +imm32 r6, 0x00000806; +imm32 r7, 0x00000807; +R3.H = R0.L << 3; +R4.H = R1.L << 3; +R5.H = R2.L << 3; +R6.H = R3.L << 3; +R7.H = R4.L << 3; +R0.H = R5.L << 3; +R1.H = R6.L << 3; +R2.H = R7.L << 3; +CHECKREG r0, 0x40280801; +CHECKREG r1, 0x40300801; +CHECKREG r2, 0x40380802; +CHECKREG r3, 0x40080810; +CHECKREG r4, 0x40080804; +CHECKREG r5, 0x40100805; +CHECKREG r6, 0x40800806; +CHECKREG r7, 0x40200807; + +// RHx by RLx +imm32 r0, 0x00000400; +imm32 r1, 0x00010500; +imm32 r2, 0x00020060; +imm32 r3, 0x00030070; +imm32 r4, 0x00040800; +imm32 r5, 0x00050090; +imm32 r6, 0x00060d00; +imm32 r7, 0x00070a00; +R7.H = R0.H << 10; +R6.H = R1.H << 10; +R5.H = R2.H << 10; +R4.H = R3.H << 10; +R3.H = R4.H << 10; +R2.H = R5.H << 10; +R1.H = R6.H << 10; +R0.H = R7.H << 10; +CHECKREG r1, 0x00000500; +CHECKREG r2, 0x00000060; +CHECKREG r3, 0x00000070; +CHECKREG r4, 0x0C000800; +CHECKREG r5, 0x08000090; +CHECKREG r6, 0x04000D00; +CHECKREG r7, 0x00000A00; +CHECKREG r0, 0x00000400; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020001; +imm32 r3, 0x00030002; +imm32 r4, 0x00040003; +imm32 r5, 0x00050004; +imm32 r6, 0x00060005; +imm32 r7, 0x00070006; +R6.H = R0.H << 11; +R5.H = R1.H << 11; +R4.H = R2.H << 11; +R3.H = R3.H << 11; +R2.H = R4.H << 11; +R1.H = R5.H << 11; +R7.H = R6.H << 11; +R0.H = R7.H << 11; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x18000002; +CHECKREG r4, 0x10000003; +CHECKREG r5, 0x08000004; +CHECKREG r6, 0x08000005; +CHECKREG r7, 0x00000006; +CHECKREG r0, 0x00000000; + + +imm32 r0, 0x00010060; +imm32 r1, 0x00010060; +imm32 r2, 0x0002006f; +imm32 r3, 0x00030060; +imm32 r4, 0x00040060; +imm32 r5, 0x00050060; +imm32 r6, 0x00060060; +imm32 r7, 0x00070060; +R4.H = R0.H << 12; +R5.H = R1.H << 12; +R6.H = R2.H << 12; +R7.H = R3.H << 12; +R0.H = R4.H << 12; +R1.H = R5.H << 12; +R2.H = R6.H << 12; +R3.H = R7.H << 12; +CHECKREG r0, 0x00000060; +CHECKREG r1, 0x00000060; +CHECKREG r2, 0x0000006F; +CHECKREG r3, 0x00000060; +CHECKREG r4, 0x10000060; +CHECKREG r5, 0x10000060; +CHECKREG r6, 0x20000060; +CHECKREG r7, 0x30000060; + +imm32 r0, 0x12010070; +imm32 r1, 0x23010070; +imm32 r2, 0x34020070; +imm32 r3, 0x45030070; +imm32 r4, 0x56040070; +imm32 r5, 0x67050070; +imm32 r6, 0x78060070; +imm32 r7, 0x09070070; +R4.H = R0.H << 3; +R5.H = R1.H << 3; +R6.H = R2.H << 3; +R7.H = R3.H << 3; +R0.H = R4.H << 3; +R1.H = R5.H << 3; +R2.H = R6.H << 3; +R3.H = R7.H << 3; +CHECKREG r0, 0x80400070; +CHECKREG r1, 0xC0400070; +CHECKREG r2, 0x00800070; +CHECKREG r3, 0x40C00070; +CHECKREG r4, 0x90080070; +CHECKREG r5, 0x18080070; +CHECKREG r6, 0xA0100070; +CHECKREG r7, 0x28180070; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_ahalf_lp_s.s b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_lp_s.s new file mode 100644 index 0000000..45b2a7e --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_lp_s.s @@ -0,0 +1,415 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_lp_s/c_dsp32shiftim_ahalf_lp_s.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00100a00; +imm32 r1, 0x00100a01; +imm32 r2, 0x00100a02; +imm32 r3, 0x00100a03; +imm32 r4, 0x00100a04; +imm32 r5, 0x00100a05; +imm32 r6, 0x00100a06; +imm32 r7, 0x00100a07; +R7.L = R0.L << 0 (S); +R0.L = R1.L << 1 (S); +R1.L = R2.L << 2 (S); +R2.L = R3.L << 3 (S); +R3.L = R4.L << 4 (S); +R4.L = R5.L << 5 (S); +R5.L = R6.L << 6 (S); +R6.L = R7.L << 7 (S); +CHECKREG r1, 0x00102808; +CHECKREG r0, 0x00101402; +CHECKREG r2, 0x00105018; +CHECKREG r3, 0x00107FFF; +CHECKREG r4, 0x00107FFF; +CHECKREG r5, 0x00107FFF; +CHECKREG r6, 0x00107FFF; +CHECKREG r7, 0x00100A00; + +imm32 r0, 0x00200018; +imm32 r1, 0x00200019; +imm32 r2, 0x0020001a; +imm32 r3, 0x0020001b; +imm32 r4, 0x0020001c; +imm32 r5, 0x0020001d; +imm32 r6, 0x0020001e; +imm32 r7, 0x0020001f; +R2.L = R0.L << 8 (S); +R3.L = R1.L << 9 (S); +R4.L = R2.L << 10 (S); +R5.L = R3.L << 11 (S); +R6.L = R4.L << 12 (S); +R7.L = R5.L << 13 (S); +R0.L = R6.L << 14 (S); +R1.L = R7.L << 15 (S); +CHECKREG r0, 0x00207FFF; +CHECKREG r1, 0x00207FFF; +CHECKREG r2, 0x00201800; +CHECKREG r3, 0x00203200; +CHECKREG r4, 0x00207FFF; +CHECKREG r5, 0x00207FFF; +CHECKREG r6, 0x00207FFF; +CHECKREG r7, 0x00207FFF; + +imm32 r0, 0x05002001; +imm32 r1, 0x05002001; +imm32 r2, 0x0500000f; +imm32 r3, 0x05002003; +imm32 r4, 0x05002004; +imm32 r5, 0x05002005; +imm32 r6, 0x05002006; +imm32 r7, 0x05002007; +R3.L = R0.L << 0 (S); +R4.L = R1.L << 1 (S); +R5.L = R2.L << 2 (S); +R6.L = R3.L << 3 (S); +R7.L = R4.L << 4 (S); +R0.L = R5.L << 5 (S); +R1.L = R6.L << 6 (S); +R2.L = R7.L << 7 (S); +CHECKREG r0, 0x05000780; +CHECKREG r1, 0x05007FFF; +CHECKREG r2, 0x05007FFF; +CHECKREG r3, 0x05002001; +CHECKREG r4, 0x05004002; +CHECKREG r5, 0x0500003C; +CHECKREG r6, 0x05007FFF; +CHECKREG r7, 0x05007FFF; + +imm32 r0, 0x03000031; +imm32 r1, 0x03000031; +imm32 r2, 0x03000032; +imm32 r3, 0x03000030; +imm32 r4, 0x03000034; +imm32 r5, 0x03000035; +imm32 r6, 0x03000036; +imm32 r7, 0x03000037; +R4.L = R0.L << 8 (S); +R5.L = R1.L << 9 (S); +R6.L = R2.L << 10 (S); +R7.L = R3.L << 11 (S); +R0.L = R4.L << 12 (S); +R1.L = R5.L << 13 (S); +R2.L = R6.L << 14 (S); +R3.L = R7.L << 15 (S); +CHECKREG r0, 0x03007FFF; +CHECKREG r1, 0x03007FFF; +CHECKREG r2, 0x03007FFF; +CHECKREG r3, 0x03007FFF; +CHECKREG r4, 0x03003100; +CHECKREG r5, 0x03006200; +CHECKREG r6, 0x03007FFF; +CHECKREG r7, 0x03007FFF; +// RHx by RLx +imm32 r0, 0x03000000; +imm32 r1, 0x03000000; +imm32 r2, 0x03000000; +imm32 r3, 0x03000000; +imm32 r4, 0x03003100; +imm32 r5, 0x03006200; +imm32 r6, 0x0300C800; +imm32 r7, 0x03008000; +R5.L = R0.H << 0 (S); +R6.L = R1.H << 1 (S); +R7.L = R2.H << 2 (S); +R0.L = R3.H << 3 (S); +R1.L = R4.H << 4 (S); +R2.L = R5.H << 5 (S); +R3.L = R6.H << 6 (S); +R4.L = R7.H << 7 (S); +CHECKREG r0, 0x03001800; +CHECKREG r1, 0x03003000; +CHECKREG r2, 0x03006000; +CHECKREG r3, 0x03007FFF; +CHECKREG r4, 0x03007FFF; +CHECKREG r5, 0x03000300; +CHECKREG r6, 0x03000600; +CHECKREG r7, 0x03000C00; + +imm32 r0, 0x05018000; +imm32 r1, 0x05018001; +imm32 r2, 0x05028000; +imm32 r3, 0x05038000; +imm32 r4, 0x05048000; +imm32 r5, 0x05058000; +imm32 r6, 0x05068000; +imm32 r7, 0x05078000; +R6.L = R0.H << 8 (S); +R7.L = R1.H << 9 (S); +R0.L = R2.H << 10 (S); +R1.L = R3.H << 11 (S); +R2.L = R4.H << 12 (S); +R3.L = R5.H << 13 (S); +R4.L = R6.H << 14 (S); +R5.L = R7.H << 15 (S); +CHECKREG r0, 0x05017FFF; +CHECKREG r1, 0x05017FFF; +CHECKREG r2, 0x05027FFF; +CHECKREG r3, 0x05037FFF; +CHECKREG r4, 0x05047FFF; +CHECKREG r5, 0x05057FFF; +CHECKREG r6, 0x05067FFF; +CHECKREG r7, 0x05077FFF; + + +imm32 r0, 0x60019000; +imm32 r1, 0x60019000; +imm32 r2, 0x6002900f; +imm32 r3, 0x60039000; +imm32 r4, 0x60049000; +imm32 r5, 0x60059000; +imm32 r6, 0x60069000; +imm32 r7, 0x60079000; +R7.L = R0.H << 0 (S); +R0.L = R1.H << 1 (S); +R1.L = R2.H << 2 (S); +R2.L = R3.H << 3 (S); +R3.L = R4.H << 4 (S); +R4.L = R5.H << 5 (S); +R5.L = R6.H << 6 (S); +R6.L = R7.H << 7 (S); +CHECKREG r0, 0x60017FFF; +CHECKREG r1, 0x60017FFF; +CHECKREG r2, 0x60027FFF; +CHECKREG r3, 0x60037FFF; +CHECKREG r4, 0x60047FFF; +CHECKREG r5, 0x60057FFF; +CHECKREG r6, 0x60067FFF; +CHECKREG r7, 0x60076001; + +imm32 r0, 0x70010001; +imm32 r1, 0x70010001; +imm32 r2, 0x70020002; +imm32 r3, 0x77030010; +imm32 r4, 0x70040004; +imm32 r5, 0x70050005; +imm32 r6, 0x70060006; +imm32 r7, 0x70070007; +R0.L = R0.H << 8 (S); +R1.L = R1.H << 9 (S); +R2.L = R2.H << 10 (S); +R3.L = R3.H << 11 (S); +R4.L = R4.H << 12 (S); +R5.L = R5.H << 13 (S); +R6.L = R6.H << 14 (S); +R7.L = R7.H << 15 (S); +CHECKREG r0, 0x70017FFF; +CHECKREG r1, 0x70017FFF; +CHECKREG r2, 0x70027FFF; +CHECKREG r3, 0x77037FFF; +CHECKREG r4, 0x70047FFF; +CHECKREG r5, 0x70057FFF; +CHECKREG r6, 0x70067FFF; +CHECKREG r7, 0x70077FFF; + +// d_hi = lshft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0xa8000000; +imm32 r1, 0xa8000001; +imm32 r2, 0xa8000002; +imm32 r3, 0xa8000003; +imm32 r4, 0xa8000004; +imm32 r5, 0xa8000005; +imm32 r6, 0xa8000006; +imm32 r7, 0xa8000007; +R0.H = R0.L << 0 (S); +R1.H = R1.L << 1 (S); +R2.H = R2.L << 2 (S); +R3.H = R3.L << 3 (S); +R4.H = R4.L << 4 (S); +R5.H = R5.L << 5 (S); +R6.H = R6.L << 6 (S); +R7.H = R7.L << 7 (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00080002; +CHECKREG r3, 0x00180003; +CHECKREG r4, 0x00400004; +CHECKREG r5, 0x00A00005; +CHECKREG r6, 0x01800006; +CHECKREG r7, 0x03800007; + +imm32 r0, 0xf0090001; +imm32 r1, 0xf0090001; +imm32 r2, 0xf0090002; +imm32 r3, 0xf0090003; +imm32 r4, 0xf0090004; +imm32 r5, 0xf0090005; +imm32 r6, 0xf0000006; +imm32 r7, 0xf0000007; +R1.H = R0.L << 8 (S); +R2.H = R1.L << 9 (S); +R3.H = R2.L << 10 (S); +R4.H = R3.L << 11 (S); +R5.H = R4.L << 12 (S); +R6.H = R5.L << 13 (S); +R7.H = R6.L << 14 (S); +R0.H = R7.L << 15 (S); +CHECKREG r1, 0x01000001; +CHECKREG r2, 0x02000002; +CHECKREG r3, 0x08000003; +CHECKREG r4, 0x18000004; +CHECKREG r5, 0x40000005; +CHECKREG r6, 0x7FFF0006; +CHECKREG r7, 0x7FFF0007; +CHECKREG r0, 0x7FFF0001; + + +imm32 r0, 0x07000001; +imm32 r1, 0x07000001; +imm32 r2, 0x0700000f; +imm32 r3, 0x07000003; +imm32 r4, 0x07000004; +imm32 r5, 0x07000005; +imm32 r6, 0x07000006; +imm32 r7, 0x07000007; +R3.H = R0.L << 0 (S); +R4.H = R1.L << 1 (S); +R5.H = R2.L << 2 (S); +R6.H = R3.L << 3 (S); +R7.H = R4.L << 4 (S); +R0.H = R5.L << 5 (S); +R1.H = R6.L << 6 (S); +R2.H = R7.L << 7 (S); +CHECKREG r0, 0x00A00001; +CHECKREG r1, 0x01800001; +CHECKREG r2, 0x0380000F; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +CHECKREG r5, 0x003C0005; +CHECKREG r6, 0x00180006; +CHECKREG r7, 0x00400007; + +imm32 r0, 0x00000501; +imm32 r1, 0x00000501; +imm32 r2, 0x00000502; +imm32 r3, 0x00000510; +imm32 r4, 0x00000504; +imm32 r5, 0x00000505; +imm32 r6, 0x00000506; +imm32 r7, 0x00000507; +R4.H = R0.L << 8 (S); +R5.H = R1.L << 9 (S); +R6.H = R2.L << 10 (S); +R7.H = R3.L << 11 (S); +R0.H = R4.L << 12 (S); +R1.H = R5.L << 13 (S); +R2.H = R6.L << 14 (S); +R3.H = R7.L << 15 (S); +CHECKREG r0, 0x7FFF0501; +CHECKREG r1, 0x7FFF0501; +CHECKREG r2, 0x7FFF0502; +CHECKREG r3, 0x7FFF0510; +CHECKREG r4, 0x7FFF0504; +CHECKREG r5, 0x7FFF0505; +CHECKREG r6, 0x7FFF0506; +CHECKREG r7, 0x7FFF0507; + +imm32 r0, 0x00a00800; +imm32 r1, 0x00a10800; +imm32 r2, 0x00a20800; +imm32 r3, 0x00a30800; +imm32 r4, 0x00a40800; +imm32 r5, 0x00a50800; +imm32 r6, 0x00a60800; +imm32 r7, 0x00a70800; +R5.H = R0.H << 0 (S); +R6.H = R1.H << 1 (S); +R7.H = R2.H << 2 (S); +R0.H = R3.H << 3 (S); +R1.H = R4.H << 4 (S); +R2.H = R5.H << 5 (S); +R3.H = R6.H << 6 (S); +R4.H = R7.H << 7 (S); +CHECKREG r0, 0x05180800; +CHECKREG r1, 0x0A400800; +CHECKREG r2, 0x14000800; +CHECKREG r3, 0x50800800; +CHECKREG r4, 0x7FFF0800; +CHECKREG r5, 0x00A00800; +CHECKREG r6, 0x01420800; +CHECKREG r7, 0x02880800; + +imm32 r0, 0x0c010000; +imm32 r1, 0x0c010001; +imm32 r2, 0x0c020000; +imm32 r3, 0x0c030000; +imm32 r4, 0x0c040000; +imm32 r5, 0x0c050000; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c070000; +R6.H = R0.H << 8 (S); +R7.H = R1.H << 9 (S); +R0.H = R2.H << 10 (S); +R1.H = R3.H << 11 (S); +R2.H = R4.H << 12 (S); +R3.H = R5.H << 13 (S); +R4.H = R6.H << 14 (S); +R5.H = R7.H << 15 (S); +CHECKREG r0, 0x7FFF0000; +CHECKREG r1, 0x7FFF0001; +CHECKREG r2, 0x7FFF0000; +CHECKREG r3, 0x7FFF0000; +CHECKREG r4, 0x7FFF0000; +CHECKREG r5, 0x7FFF0000; +CHECKREG r6, 0x7FFF0000; +CHECKREG r7, 0x7FFF0000; + + +imm32 r0, 0x00b10000; +imm32 r1, 0x00b10000; +imm32 r2, 0x00b2000f; +imm32 r3, 0x00b30000; +imm32 r4, 0x00b40000; +imm32 r5, 0x00b50000; +imm32 r6, 0x00b60000; +imm32 r7, 0x00b70000; +R7.L = R0.H << 0 (S); +R0.L = R1.H << 1 (S); +R1.L = R2.H << 2 (S); +R2.L = R3.H << 3 (S); +R3.L = R4.H << 4 (S); +R4.L = R5.H << 5 (S); +R5.L = R6.H << 6 (S); +R6.L = R7.H << 7 (S); +CHECKREG r0, 0x00B10162; +CHECKREG r1, 0x00B102C8; +CHECKREG r2, 0x00B20598; +CHECKREG r3, 0x00B30B40; +CHECKREG r4, 0x00B416A0; +CHECKREG r5, 0x00B52D80; +CHECKREG r6, 0x00B65B80; +CHECKREG r7, 0x00B700B1; + +imm32 r0, 0x0a010700; +imm32 r1, 0x0a010700; +imm32 r2, 0x0a020700; +imm32 r3, 0x0a030710; +imm32 r4, 0x0a040700; +imm32 r5, 0x0a050700; +imm32 r6, 0x0a060700; +imm32 r7, 0x0a070700; +R0.H = R0.H << 8 (S); +R1.H = R1.H << 9 (S); +R2.H = R2.H << 10 (S); +R3.H = R3.H << 11 (S); +R4.H = R4.H << 12 (S); +R5.H = R5.H << 13 (S); +R6.H = R6.H << 14 (S); +R7.H = R7.H << 15 (S); +CHECKREG r0, 0x7FFF0700; +CHECKREG r1, 0x7FFF0700; +CHECKREG r2, 0x7FFF0700; +CHECKREG r3, 0x7FFF0710; +CHECKREG r4, 0x7FFF0700; +CHECKREG r5, 0x7FFF0700; +CHECKREG r6, 0x7FFF0700; +CHECKREG r7, 0x7FFF0700; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn.s b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn.s new file mode 100644 index 0000000..30d84f2 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn.s @@ -0,0 +1,418 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_rn/c_dsp32shiftim_ahalf_rn.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = R0.L >>> 10; +R1.L = R1.L >>> 10; +R2.L = R2.L >>> 10; +R3.L = R3.L >>> 10; +R4.L = R4.L >>> 10; +R5.L = R5.L >>> 10; +R6.L = R6.L >>> 10; +R7.L = R7.L >>> 10; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x0000FFE0; +CHECKREG r2, 0x0000FFE0; +CHECKREG r3, 0x0000FFE0; +CHECKREG r4, 0x0000FFE0; +CHECKREG r5, 0x0000FFE0; +CHECKREG r6, 0x0000FFE0; +CHECKREG r7, 0x0000FFE0; + +imm32 r0, 0x02008020; +imm32 r0, 0x02008021; +imm32 r2, 0x02008022; +imm32 r3, 0x02008023; +imm32 r4, 0x02008024; +imm32 r5, 0x02008025; +imm32 r6, 0x02008026; +imm32 r7, 0x02008027; +R0.L = R0.L >>> 11; +R1.L = R1.L >>> 11; +R2.L = R2.L >>> 11; +R3.L = R3.L >>> 11; +R4.L = R4.L >>> 11; +R5.L = R5.L >>> 11; +R6.L = R6.L >>> 11; +R7.L = R7.L >>> 11; +CHECKREG r0, 0x0200FFF0; +CHECKREG r1, 0x0000FFFF; +CHECKREG r2, 0x0200FFF0; +CHECKREG r3, 0x0200FFF0; +CHECKREG r4, 0x0200FFF0; +CHECKREG r5, 0x0200FFF0; +CHECKREG r6, 0x0200FFF0; +CHECKREG r7, 0x0200FFF0; + + +imm32 r0, 0x00308001; +imm32 r1, 0x00308001; +R2.L = -15; +imm32 r3, 0x00308003; +imm32 r4, 0x00308004; +imm32 r5, 0x00308005; +imm32 r6, 0x00308006; +imm32 r7, 0x00308007; +R0.L = R0.L >>> 12; +R1.L = R1.L >>> 12; +R2.L = R2.L >>> 12; +R3.L = R3.L >>> 12; +R4.L = R4.L >>> 12; +R5.L = R5.L >>> 12; +R6.L = R6.L >>> 12; +R7.L = R7.L >>> 12; +CHECKREG r0, 0x0030FFF8; +CHECKREG r1, 0x0030FFF8; +CHECKREG r2, 0x0200FFFF; +CHECKREG r3, 0x0030FFF8; +CHECKREG r4, 0x0030FFF8; +CHECKREG r5, 0x0030FFF8; +CHECKREG r6, 0x0030FFF8; +CHECKREG r7, 0x0030FFF8; + +imm32 r0, 0x00008401; +imm32 r1, 0x00008401; +imm32 r2, 0x00008402; +R3.L = -16; +imm32 r4, 0x00008404; +imm32 r5, 0x00008405; +imm32 r6, 0x00008406; +imm32 r7, 0x00008407; +R0.L = R0.L >>> 3; +R1.L = R1.L >>> 3; +R2.L = R2.L >>> 3; +R3.L = R3.L >>> 3; +R4.L = R4.L >>> 3; +R5.L = R5.L >>> 3; +R6.L = R6.L >>> 3; +R7.L = R7.L >>> 3; +CHECKREG r0, 0x0000F080; +CHECKREG r1, 0x0000F080; +CHECKREG r2, 0x0000F080; +CHECKREG r3, 0x0030FFFE; +CHECKREG r4, 0x0000F080; +CHECKREG r5, 0x0000F080; +CHECKREG r6, 0x0000F080; +CHECKREG r7, 0x0000F080; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x05000500; +imm32 r1, 0x85010500; +imm32 r2, 0x85020500; +imm32 r3, 0x85030500; +imm32 r4, 0x85040500; +imm32 r5, 0x85050500; +imm32 r6, 0x85060500; +imm32 r7, 0x85070500; +R0.L = R0.H >>> 10; +R1.L = R1.H >>> 10; +R2.L = R2.H >>> 10; +R3.L = R3.H >>> 10; +R4.L = R4.H >>> 10; +R5.L = R5.H >>> 10; +R6.L = R6.H >>> 10; +R7.L = R7.H >>> 10; +CHECKREG r0, 0x05000001; +CHECKREG r1, 0x8501FFE1; +CHECKREG r2, 0x8502FFE1; +CHECKREG r3, 0x8503FFE1; +CHECKREG r4, 0x8504FFE1; +CHECKREG r5, 0x8505FFE1; +CHECKREG r6, 0x8506FFE1; +CHECKREG r7, 0x8507FFE1; + +imm32 r0, 0x80610000; +R1.L = -1; +imm32 r2, 0x80620000; +imm32 r3, 0x80630000; +imm32 r4, 0x80640000; +imm32 r5, 0x80650000; +imm32 r6, 0x80660000; +imm32 r7, 0x80670000; +R0.L = R0.H >>> 11; +R1.L = R1.H >>> 11; +R2.L = R2.H >>> 11; +R3.L = R3.H >>> 11; +R4.L = R4.H >>> 11; +R5.L = R5.H >>> 11; +R6.L = R6.H >>> 11; +R7.L = R7.H >>> 11; +CHECKREG r0, 0x8061FFF0; +CHECKREG r1, 0x8501FFF0; +CHECKREG r2, 0x8062FFF0; +CHECKREG r3, 0x8063FFF0; +CHECKREG r4, 0x8064FFF0; +CHECKREG r5, 0x8065FFF0; +CHECKREG r6, 0x8066FFF0; +CHECKREG r7, 0x8067FFF0; + + +imm32 r0, 0xa0010070; +imm32 r1, 0xa0010070; +R2.L = -15; +imm32 r3, 0xa0030070; +imm32 r4, 0xa0040070; +imm32 r5, 0xa0050070; +imm32 r6, 0xa0060070; +imm32 r7, 0xa0070070; +R0.L = R0.H >>> 12; +R1.L = R1.H >>> 12; +R2.L = R2.H >>> 12; +R3.L = R3.H >>> 12; +R4.L = R4.H >>> 12; +R5.L = R5.H >>> 12; +R6.L = R6.H >>> 12; +R7.L = R7.H >>> 12; +CHECKREG r0, 0xA001FFFA; +CHECKREG r1, 0xA001FFFA; +CHECKREG r2, 0x8062FFF8; +CHECKREG r3, 0xA003FFFA; +CHECKREG r4, 0xA004FFFA; +CHECKREG r5, 0xA005FFFA; +CHECKREG r6, 0xA006FFFA; +CHECKREG r7, 0xA007FFFA; + +imm32 r0, 0xb8010001; +imm32 r1, 0xb8010001; +imm32 r2, 0xb8020002; +R3.L = -16; +imm32 r4, 0xb8040004; +imm32 r5, 0xb8050005; +imm32 r6, 0xb8060006; +imm32 r7, 0xb8070007; +R0.L = R0.H >>> 13; +R1.L = R1.H >>> 13; +R2.L = R2.H >>> 13; +R3.L = R3.H >>> 13; +R4.L = R4.H >>> 13; +R5.L = R5.H >>> 13; +R6.L = R6.H >>> 13; +R7.L = R7.H >>> 13; +CHECKREG r0, 0xB801FFFD; +CHECKREG r1, 0xB801FFFD; +CHECKREG r2, 0xB802FFFD; +CHECKREG r3, 0xA003FFFD; +CHECKREG r4, 0xB804FFFD; +CHECKREG r5, 0xB805FFFD; +CHECKREG r6, 0xB806FFFD; +CHECKREG r7, 0xB807FFFD; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009000; +imm32 r5, 0x00009005; +imm32 r6, 0x00009006; +imm32 r7, 0x00009007; +R0.H = R0.L >>> 14; +R1.H = R1.L >>> 14; +R2.H = R2.L >>> 14; +R3.H = R3.L >>> 14; +R4.H = R4.L >>> 14; +R5.H = R5.L >>> 14; +R6.H = R6.L >>> 14; +R7.H = R7.L >>> 14; +CHECKREG r0, 0xFFFE9001; +CHECKREG r1, 0xFFFE9001; +CHECKREG r2, 0xFFFE9002; +CHECKREG r3, 0xFFFE9003; +CHECKREG r4, 0xFFFE9000; +CHECKREG r5, 0xFFFE9005; +CHECKREG r6, 0xFFFE9006; +CHECKREG r7, 0xFFFE9007; + +imm32 r0, 0xa0008001; +imm32 r1, 0xa0008001; +imm32 r2, 0xa0008002; +imm32 r3, 0xa0008003; +imm32 r4, 0xa0008004; +R5.L = -1; +imm32 r6, 0xa0008006; +imm32 r7, 0xa0008007; +R0.H = R0.L >>> 5; +R1.H = R1.L >>> 5; +R2.H = R2.L >>> 5; +R3.H = R3.L >>> 5; +R4.H = R4.L >>> 5; +R5.H = R5.L >>> 5; +R6.H = R6.L >>> 5; +R7.H = R7.L >>> 5; +CHECKREG r0, 0xFC008001; +CHECKREG r1, 0xFC008001; +CHECKREG r2, 0xFC008002; +CHECKREG r3, 0xFC008003; +CHECKREG r4, 0xFC008004; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFC008006; +CHECKREG r7, 0xFC008007; + + +imm32 r0, 0x00009b01; +imm32 r1, 0x00009b01; +imm32 r2, 0x00009b02; +imm32 r3, 0x00009b03; +imm32 r4, 0x00009b04; +imm32 r5, 0x00009b05; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = R0.L >>> 6; +R1.H = R1.L >>> 6; +R2.H = R2.L >>> 6; +R3.H = R3.L >>> 6; +R4.H = R4.L >>> 6; +R5.H = R5.L >>> 6; +R6.H = R6.L >>> 6; +R7.H = R7.L >>> 6; +CHECKREG r0, 0xFE6C9B01; +CHECKREG r1, 0xFE6C9B01; +CHECKREG r2, 0xFE6C9B02; +CHECKREG r3, 0xFE6C9B03; +CHECKREG r4, 0xFE6C9B04; +CHECKREG r5, 0xFE6C9B05; +CHECKREG r6, 0xFFFFFFF1; +CHECKREG r7, 0xFE409007; + +imm32 r0, 0x0000a0c1; +imm32 r1, 0x0000a0c1; +imm32 r2, 0x0000a0c2; +imm32 r3, 0x0000a0c3; +imm32 r4, 0x0000a0c4; +imm32 r5, 0x0000a0c5; +imm32 r6, 0x0000a0c6; +R7.L = -16; +R0.H = R0.L >>> 7; +R1.H = R1.L >>> 7; +R2.H = R2.L >>> 7; +R3.H = R3.L >>> 7; +R4.H = R4.L >>> 7; +R5.H = R5.L >>> 7; +R6.H = R6.L >>> 7; +R7.H = R7.L >>> 7; +CHECKREG r0, 0xFF41A0C1; +CHECKREG r1, 0xFF41A0C1; +CHECKREG r2, 0xFF41A0C2; +CHECKREG r3, 0xFF41A0C3; +CHECKREG r4, 0xFF41A0C4; +CHECKREG r5, 0xFF41A0C5; +CHECKREG r6, 0xFF41A0C6; +CHECKREG r7, 0xFFFFFFF0; + +imm32 r0, 0x80010d00; +imm32 r1, 0x80010d00; +imm32 r2, 0x80020d00; +imm32 r3, 0x80030d00; +R4.L = -1; +imm32 r5, 0x80050d00; +imm32 r6, 0x80060d00; +imm32 r7, 0x80070d00; +R0.H = R0.H >>> 14; +R1.H = R1.H >>> 14; +R2.H = R2.H >>> 14; +R3.H = R3.H >>> 14; +R4.H = R4.H >>> 14; +R5.H = R5.H >>> 14; +R6.H = R6.H >>> 14; +R7.H = R7.H >>> 14; +CHECKREG r0, 0xFFFE0D00; +CHECKREG r1, 0xFFFE0D00; +CHECKREG r2, 0xFFFE0D00; +CHECKREG r3, 0xFFFE0D00; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFE0D00; +CHECKREG r6, 0xFFFE0D00; +CHECKREG r7, 0xFFFE0D00; + +imm32 r0, 0x8d010000; +imm32 r1, 0x8d010000; +imm32 r2, 0x8d020000; +imm32 r3, 0x8d030000; +imm32 r4, 0x8d040000; +R5.L = -1; +imm32 r6, 0x8d060000; +imm32 r7, 0x8d070000; +R0.H = R0.H >>> 15; +R1.H = R1.H >>> 15; +R2.H = R2.H >>> 15; +R3.H = R3.H >>> 15; +R4.H = R4.H >>> 15; +R5.H = R5.H >>> 15; +R6.H = R6.H >>> 15; +R7.H = R7.H >>> 15; +CHECKREG r0, 0xFFFF0000; +CHECKREG r1, 0xFFFF0000; +CHECKREG r2, 0xFFFF0000; +CHECKREG r3, 0xFFFF0000; +CHECKREG r4, 0xFFFF0000; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFF0000; +CHECKREG r7, 0xFFFF0000; + + +imm32 r0, 0xde010000; +imm32 r1, 0xde010000; +imm32 r2, 0xde020000; +imm32 r3, 0xde030000; +imm32 r4, 0xde040000; +imm32 r5, 0xde050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = R0.H >>> 10; +R1.L = R1.H >>> 10; +R2.L = R2.H >>> 10; +R3.L = R3.H >>> 10; +R4.L = R4.H >>> 10; +R5.L = R5.H >>> 10; +R6.L = R6.H >>> 10; +R7.L = R7.H >>> 10; +CHECKREG r0, 0xDE01FFF7; +CHECKREG r1, 0xDE01FFF7; +CHECKREG r2, 0xDE02FFF7; +CHECKREG r3, 0xDE03FFF7; +CHECKREG r4, 0xDE04FFF7; +CHECKREG r5, 0xDE05FFF7; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xD007FFF4; + +imm32 r0, 0x9f010c00; +imm32 r1, 0xaf010c00; +imm32 r2, 0xbf020c00; +imm32 r3, 0xcf030c00; +imm32 r4, 0xdf040c00; +imm32 r5, 0xef050c00; +imm32 r6, 0xff060c00; +R7.L = -16; +R0.H = R0.H >>> 5; +R1.H = R1.H >>> 5; +R2.H = R2.H >>> 5; +R3.H = R3.H >>> 5; +R4.H = R4.H >>> 5; +R5.H = R5.H >>> 5; +R6.H = R6.H >>> 5; +R7.H = R7.H >>> 5; +CHECKREG r0, 0xFCF80C00; +CHECKREG r1, 0xFD780C00; +CHECKREG r2, 0xFDF80C00; +CHECKREG r3, 0xFE780C00; +CHECKREG r4, 0xFEF80C00; +CHECKREG r5, 0xFF780C00; +CHECKREG r6, 0xFFF80C00; +CHECKREG r7, 0xFE80FFF0; +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn_s.s b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn_s.s new file mode 100644 index 0000000..20770d5 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn_s.s @@ -0,0 +1,418 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_rn_s/c_dsp32shiftim_ahalf_rn_s.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = R0.L >>> 10; +R1.L = R1.L >>> 10; +R2.L = R2.L >>> 10; +R3.L = R3.L >>> 10; +R4.L = R4.L >>> 10; +R5.L = R5.L >>> 10; +R6.L = R6.L >>> 10; +R7.L = R7.L >>> 10; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x0000FFE0; +CHECKREG r2, 0x0000FFE0; +CHECKREG r3, 0x0000FFE0; +CHECKREG r4, 0x0000FFE0; +CHECKREG r5, 0x0000FFE0; +CHECKREG r6, 0x0000FFE0; +CHECKREG r7, 0x0000FFE0; + +imm32 r0, 0x02008020; +imm32 r0, 0x02008021; +imm32 r2, 0x02008022; +imm32 r3, 0x02008023; +imm32 r4, 0x02008024; +imm32 r5, 0x02008025; +imm32 r6, 0x02008026; +imm32 r7, 0x02008027; +R0.L = R0.L >>> 11; +R1.L = R1.L >>> 11; +R2.L = R2.L >>> 11; +R3.L = R3.L >>> 11; +R4.L = R4.L >>> 11; +R5.L = R5.L >>> 11; +R6.L = R6.L >>> 11; +R7.L = R7.L >>> 11; +CHECKREG r0, 0x0200FFF0; +CHECKREG r1, 0x0000FFFF; +CHECKREG r2, 0x0200FFF0; +CHECKREG r3, 0x0200FFF0; +CHECKREG r4, 0x0200FFF0; +CHECKREG r5, 0x0200FFF0; +CHECKREG r6, 0x0200FFF0; +CHECKREG r7, 0x0200FFF0; + + +imm32 r0, 0x00308001; +imm32 r1, 0x00308001; +R2.L = -15; +imm32 r3, 0x00308003; +imm32 r4, 0x00308004; +imm32 r5, 0x00308005; +imm32 r6, 0x00308006; +imm32 r7, 0x00308007; +R0.L = R0.L >>> 12; +R1.L = R1.L >>> 12; +R2.L = R2.L >>> 12; +R3.L = R3.L >>> 12; +R4.L = R4.L >>> 12; +R5.L = R5.L >>> 12; +R6.L = R6.L >>> 12; +R7.L = R7.L >>> 12; +CHECKREG r0, 0x0030FFF8; +CHECKREG r1, 0x0030FFF8; +CHECKREG r2, 0x0200FFFF; +CHECKREG r3, 0x0030FFF8; +CHECKREG r4, 0x0030FFF8; +CHECKREG r5, 0x0030FFF8; +CHECKREG r6, 0x0030FFF8; +CHECKREG r7, 0x0030FFF8; + +imm32 r0, 0x00008401; +imm32 r1, 0x00008401; +imm32 r2, 0x00008402; +R3.L = -16; +imm32 r4, 0x00008404; +imm32 r5, 0x00008405; +imm32 r6, 0x00008406; +imm32 r7, 0x00008407; +R0.L = R0.L >>> 3; +R1.L = R1.L >>> 3; +R2.L = R2.L >>> 3; +R3.L = R3.L >>> 3; +R4.L = R4.L >>> 3; +R5.L = R5.L >>> 3; +R6.L = R6.L >>> 3; +R7.L = R7.L >>> 3; +CHECKREG r0, 0x0000F080; +CHECKREG r1, 0x0000F080; +CHECKREG r2, 0x0000F080; +CHECKREG r3, 0x0030FFFE; +CHECKREG r4, 0x0000F080; +CHECKREG r5, 0x0000F080; +CHECKREG r6, 0x0000F080; +CHECKREG r7, 0x0000F080; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x05000500; +imm32 r1, 0x85010500; +imm32 r2, 0x85020500; +imm32 r3, 0x85030500; +imm32 r4, 0x85040500; +imm32 r5, 0x85050500; +imm32 r6, 0x85060500; +imm32 r7, 0x85070500; +R0.L = R0.H >>> 10; +R1.L = R1.H >>> 10; +R2.L = R2.H >>> 10; +R3.L = R3.H >>> 10; +R4.L = R4.H >>> 10; +R5.L = R5.H >>> 10; +R6.L = R6.H >>> 10; +R7.L = R7.H >>> 10; +CHECKREG r0, 0x05000001; +CHECKREG r1, 0x8501FFE1; +CHECKREG r2, 0x8502FFE1; +CHECKREG r3, 0x8503FFE1; +CHECKREG r4, 0x8504FFE1; +CHECKREG r5, 0x8505FFE1; +CHECKREG r6, 0x8506FFE1; +CHECKREG r7, 0x8507FFE1; + +imm32 r0, 0x80610000; +R1.L = -1; +imm32 r2, 0x80620000; +imm32 r3, 0x80630000; +imm32 r4, 0x80640000; +imm32 r5, 0x80650000; +imm32 r6, 0x80660000; +imm32 r7, 0x80670000; +R0.L = R0.H >>> 11; +R1.L = R1.H >>> 11; +R2.L = R2.H >>> 11; +R3.L = R3.H >>> 11; +R4.L = R4.H >>> 11; +R5.L = R5.H >>> 11; +R6.L = R6.H >>> 11; +R7.L = R7.H >>> 11; +CHECKREG r0, 0x8061FFF0; +CHECKREG r1, 0x8501FFF0; +CHECKREG r2, 0x8062FFF0; +CHECKREG r3, 0x8063FFF0; +CHECKREG r4, 0x8064FFF0; +CHECKREG r5, 0x8065FFF0; +CHECKREG r6, 0x8066FFF0; +CHECKREG r7, 0x8067FFF0; + + +imm32 r0, 0xa0010070; +imm32 r1, 0xa0010070; +R2.L = -15; +imm32 r3, 0xa0030070; +imm32 r4, 0xa0040070; +imm32 r5, 0xa0050070; +imm32 r6, 0xa0060070; +imm32 r7, 0xa0070070; +R0.L = R0.H >>> 12; +R1.L = R1.H >>> 12; +R2.L = R2.H >>> 12; +R3.L = R3.H >>> 12; +R4.L = R4.H >>> 12; +R5.L = R5.H >>> 12; +R6.L = R6.H >>> 12; +R7.L = R7.H >>> 12; +CHECKREG r0, 0xA001FFFA; +CHECKREG r1, 0xA001FFFA; +CHECKREG r2, 0x8062FFF8; +CHECKREG r3, 0xA003FFFA; +CHECKREG r4, 0xA004FFFA; +CHECKREG r5, 0xA005FFFA; +CHECKREG r6, 0xA006FFFA; +CHECKREG r7, 0xA007FFFA; + +imm32 r0, 0xb8010001; +imm32 r1, 0xb8010001; +imm32 r2, 0xb8020002; +R3.L = -16; +imm32 r4, 0xb8040004; +imm32 r5, 0xb8050005; +imm32 r6, 0xb8060006; +imm32 r7, 0xb8070007; +R0.L = R0.H >>> 13; +R1.L = R1.H >>> 13; +R2.L = R2.H >>> 13; +R3.L = R3.H >>> 13; +R4.L = R4.H >>> 13; +R5.L = R5.H >>> 13; +R6.L = R6.H >>> 13; +R7.L = R7.H >>> 13; +CHECKREG r0, 0xB801FFFD; +CHECKREG r1, 0xB801FFFD; +CHECKREG r2, 0xB802FFFD; +CHECKREG r3, 0xA003FFFD; +CHECKREG r4, 0xB804FFFD; +CHECKREG r5, 0xB805FFFD; +CHECKREG r6, 0xB806FFFD; +CHECKREG r7, 0xB807FFFD; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009000; +imm32 r5, 0x00009005; +imm32 r6, 0x00009006; +imm32 r7, 0x00009007; +R0.H = R0.L >>> 14; +R1.H = R1.L >>> 14; +R2.H = R2.L >>> 14; +R3.H = R3.L >>> 14; +R4.H = R4.L >>> 14; +R5.H = R5.L >>> 14; +R6.H = R6.L >>> 14; +R7.H = R7.L >>> 14; +CHECKREG r0, 0xFFFE9001; +CHECKREG r1, 0xFFFE9001; +CHECKREG r2, 0xFFFE9002; +CHECKREG r3, 0xFFFE9003; +CHECKREG r4, 0xFFFE9000; +CHECKREG r5, 0xFFFE9005; +CHECKREG r6, 0xFFFE9006; +CHECKREG r7, 0xFFFE9007; + +imm32 r0, 0xa0008001; +imm32 r1, 0xa0008001; +imm32 r2, 0xa0008002; +imm32 r3, 0xa0008003; +imm32 r4, 0xa0008004; +R5.L = -1; +imm32 r6, 0xa0008006; +imm32 r7, 0xa0008007; +R0.H = R0.L >>> 5; +R1.H = R1.L >>> 5; +R2.H = R2.L >>> 5; +R3.H = R3.L >>> 5; +R4.H = R4.L >>> 5; +R5.H = R5.L >>> 5; +R6.H = R6.L >>> 5; +R7.H = R7.L >>> 5; +CHECKREG r0, 0xFC008001; +CHECKREG r1, 0xFC008001; +CHECKREG r2, 0xFC008002; +CHECKREG r3, 0xFC008003; +CHECKREG r4, 0xFC008004; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFC008006; +CHECKREG r7, 0xFC008007; + + +imm32 r0, 0x00009b01; +imm32 r1, 0x00009b01; +imm32 r2, 0x00009b02; +imm32 r3, 0x00009b03; +imm32 r4, 0x00009b04; +imm32 r5, 0x00009b05; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = R0.L >>> 6; +R1.H = R1.L >>> 6; +R2.H = R2.L >>> 6; +R3.H = R3.L >>> 6; +R4.H = R4.L >>> 6; +R5.H = R5.L >>> 6; +R6.H = R6.L >>> 6; +R7.H = R7.L >>> 6; +CHECKREG r0, 0xFE6C9B01; +CHECKREG r1, 0xFE6C9B01; +CHECKREG r2, 0xFE6C9B02; +CHECKREG r3, 0xFE6C9B03; +CHECKREG r4, 0xFE6C9B04; +CHECKREG r5, 0xFE6C9B05; +CHECKREG r6, 0xFFFFFFF1; +CHECKREG r7, 0xFE409007; + +imm32 r0, 0x0000a0c1; +imm32 r1, 0x0000a0c1; +imm32 r2, 0x0000a0c2; +imm32 r3, 0x0000a0c3; +imm32 r4, 0x0000a0c4; +imm32 r5, 0x0000a0c5; +imm32 r6, 0x0000a0c6; +R7.L = -16; +R0.H = R0.L >>> 7; +R1.H = R1.L >>> 7; +R2.H = R2.L >>> 7; +R3.H = R3.L >>> 7; +R4.H = R4.L >>> 7; +R5.H = R5.L >>> 7; +R6.H = R6.L >>> 7; +R7.H = R7.L >>> 7; +CHECKREG r0, 0xFF41A0C1; +CHECKREG r1, 0xFF41A0C1; +CHECKREG r2, 0xFF41A0C2; +CHECKREG r3, 0xFF41A0C3; +CHECKREG r4, 0xFF41A0C4; +CHECKREG r5, 0xFF41A0C5; +CHECKREG r6, 0xFF41A0C6; +CHECKREG r7, 0xFFFFFFF0; + +imm32 r0, 0x80010d00; +imm32 r1, 0x80010d00; +imm32 r2, 0x80020d00; +imm32 r3, 0x80030d00; +R4.L = -1; +imm32 r5, 0x80050d00; +imm32 r6, 0x80060d00; +imm32 r7, 0x80070d00; +R0.H = R0.H >>> 14; +R1.H = R1.H >>> 14; +R2.H = R2.H >>> 14; +R3.H = R3.H >>> 14; +R4.H = R4.H >>> 14; +R5.H = R5.H >>> 14; +R6.H = R6.H >>> 14; +R7.H = R7.H >>> 14; +CHECKREG r0, 0xFFFE0D00; +CHECKREG r1, 0xFFFE0D00; +CHECKREG r2, 0xFFFE0D00; +CHECKREG r3, 0xFFFE0D00; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFE0D00; +CHECKREG r6, 0xFFFE0D00; +CHECKREG r7, 0xFFFE0D00; + +imm32 r0, 0x8d010000; +imm32 r1, 0x8d010000; +imm32 r2, 0x8d020000; +imm32 r3, 0x8d030000; +imm32 r4, 0x8d040000; +R5.L = -1; +imm32 r6, 0x8d060000; +imm32 r7, 0x8d070000; +R0.H = R0.H >>> 15; +R1.H = R1.H >>> 15; +R2.H = R2.H >>> 15; +R3.H = R3.H >>> 15; +R4.H = R4.H >>> 15; +R5.H = R5.H >>> 15; +R6.H = R6.H >>> 15; +R7.H = R7.H >>> 15; +CHECKREG r0, 0xFFFF0000; +CHECKREG r1, 0xFFFF0000; +CHECKREG r2, 0xFFFF0000; +CHECKREG r3, 0xFFFF0000; +CHECKREG r4, 0xFFFF0000; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFF0000; +CHECKREG r7, 0xFFFF0000; + + +imm32 r0, 0xde010000; +imm32 r1, 0xde010000; +imm32 r2, 0xde020000; +imm32 r3, 0xde030000; +imm32 r4, 0xde040000; +imm32 r5, 0xde050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = R0.H >>> 10; +R1.L = R1.H >>> 10; +R2.L = R2.H >>> 10; +R3.L = R3.H >>> 10; +R4.L = R4.H >>> 10; +R5.L = R5.H >>> 10; +R6.L = R6.H >>> 10; +R7.L = R7.H >>> 10; +CHECKREG r0, 0xDE01FFF7; +CHECKREG r1, 0xDE01FFF7; +CHECKREG r2, 0xDE02FFF7; +CHECKREG r3, 0xDE03FFF7; +CHECKREG r4, 0xDE04FFF7; +CHECKREG r5, 0xDE05FFF7; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xD007FFF4; + +imm32 r0, 0x9f010c00; +imm32 r1, 0xaf010c00; +imm32 r2, 0xbf020c00; +imm32 r3, 0xcf030c00; +imm32 r4, 0xdf040c00; +imm32 r5, 0xef050c00; +imm32 r6, 0xff060c00; +R7.L = -16; +R0.H = R0.H >>> 5; +R1.H = R1.H >>> 5; +R2.H = R2.H >>> 5; +R3.H = R3.H >>> 5; +R4.H = R4.H >>> 5; +R5.H = R5.H >>> 5; +R6.H = R6.H >>> 5; +R7.H = R7.H >>> 5; +CHECKREG r0, 0xFCF80C00; +CHECKREG r1, 0xFD780C00; +CHECKREG r2, 0xFDF80C00; +CHECKREG r3, 0xFE780C00; +CHECKREG r4, 0xFEF80C00; +CHECKREG r5, 0xFF780C00; +CHECKREG r6, 0xFFF80C00; +CHECKREG r7, 0xFE80FFF0; +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_ahalf_rp.s b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_rp.s new file mode 100644 index 0000000..471795e --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_rp.s @@ -0,0 +1,420 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_rp/c_dsp32shiftim_ahalf_rp.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + +// Ashift : positive data, count (+)=right (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00010001; +imm32 r2, 0x00010002; +imm32 r3, 0x00010003; +imm32 r4, 0x00010004; +imm32 r5, 0x00010005; +imm32 r6, 0x00010006; +imm32 r7, 0x00010007; +R0.L = R0.L >>> 1; +R1.L = R1.L >>> 1; +R2.L = R2.L >>> 1; +R3.L = R3.L >>> 1; +R4.L = R4.L >>> 1; +R5.L = R5.L >>> 1; +R6.L = R6.L >>> 1; +R7.L = R7.L >>> 1; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00010001; +CHECKREG r3, 0x00010001; +CHECKREG r4, 0x00010002; +CHECKREG r5, 0x00010002; +CHECKREG r6, 0x00010003; +CHECKREG r7, 0x00010003; + +imm32 r0, 0x00201001; +R1.L = -1; +imm32 r2, 0x00202002; +imm32 r3, 0x00203003; +imm32 r4, 0x00204004; +imm32 r5, 0x00205005; +imm32 r6, 0x00206006; +imm32 r7, 0x00207007; +R7.L = R0.L >>> 5; +R0.L = R1.L >>> 5; +R1.L = R2.L >>> 5; +R2.L = R3.L >>> 5; +R3.L = R4.L >>> 5; +R4.L = R5.L >>> 5; +R5.L = R6.L >>> 5; +R6.L = R7.L >>> 5; +CHECKREG r0, 0x0020FFFF; +CHECKREG r1, 0x00010100; +CHECKREG r2, 0x00200180; +CHECKREG r3, 0x00200200; +CHECKREG r4, 0x00200280; +CHECKREG r5, 0x00200300; +CHECKREG r6, 0x00200004; +CHECKREG r7, 0x00200080; + + +imm32 r0, 0x03001001; +imm32 r1, 0x03001001; +R2.L = -15; +imm32 r3, 0x03003003; +imm32 r4, 0x03004004; +imm32 r5, 0x03005005; +imm32 r6, 0x03006006; +imm32 r7, 0x03007007; +R6.L = R0.L >>> 2; +R7.L = R1.L >>> 2; +R0.L = R2.L >>> 2; +R1.L = R3.L >>> 2; +R2.L = R4.L >>> 2; +R3.L = R5.L >>> 2; +R4.L = R6.L >>> 2; +R5.L = R7.L >>> 2; +CHECKREG r0, 0x0300FFFC; +CHECKREG r1, 0x03000C00; +CHECKREG r2, 0x00201001; +CHECKREG r3, 0x03001401; +CHECKREG r4, 0x03000100; +CHECKREG r5, 0x03000100; +CHECKREG r6, 0x03000400; +CHECKREG r7, 0x03000400; + +imm32 r0, 0x40001001; +imm32 r1, 0x40001001; +imm32 r2, 0x40002002; +R3.L = -16; +imm32 r4, 0x40004004; +imm32 r5, 0x40005005; +imm32 r6, 0x40006006; +imm32 r7, 0x40007007; +R5.L = R0.L >>> 13; +R6.L = R1.L >>> 13; +R7.L = R2.L >>> 13; +R0.L = R3.L >>> 13; +R1.L = R4.L >>> 13; +R2.L = R5.L >>> 13; +R3.L = R6.L >>> 13; +R4.L = R7.L >>> 13; +CHECKREG r0, 0x4000FFFF; +CHECKREG r1, 0x40000002; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0x03000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x40000000; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x40000001; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x50000000; +imm32 r1, 0x50010000; +imm32 r2, 0x50020000; +imm32 r3, 0x50030000; +imm32 r4, 0x50040000; +imm32 r5, 0x50050000; +imm32 r6, 0x50060000; +imm32 r7, 0x50070000; +R3.L = R0.H >>> 10; +R4.L = R1.H >>> 10; +R5.L = R2.H >>> 10; +R6.L = R3.H >>> 10; +R7.L = R4.H >>> 10; +R0.L = R5.H >>> 10; +R1.L = R6.H >>> 10; +R2.L = R7.H >>> 10; +CHECKREG r0, 0x50000014; +CHECKREG r1, 0x50010014; +CHECKREG r2, 0x50020014; +CHECKREG r3, 0x50030014; +CHECKREG r4, 0x50040014; +CHECKREG r5, 0x50050014; +CHECKREG r6, 0x50060014; +CHECKREG r7, 0x50070014; + +imm32 r0, 0x10016000; +R1.L = -1; +imm32 r2, 0x20026000; +imm32 r3, 0x30036000; +imm32 r4, 0x40046000; +imm32 r5, 0x50056000; +imm32 r6, 0x60060000; +imm32 r7, 0x70076000; +R0.L = R0.H >>> 11; +R1.L = R1.H >>> 11; +R2.L = R2.H >>> 11; +R3.L = R3.H >>> 11; +R4.L = R4.H >>> 11; +R5.L = R5.H >>> 11; +R6.L = R6.H >>> 11; +R7.L = R7.H >>> 11; +CHECKREG r0, 0x10010002; +CHECKREG r1, 0x5001000A; +CHECKREG r2, 0x20020004; +CHECKREG r3, 0x30030006; +CHECKREG r4, 0x40040008; +CHECKREG r5, 0x5005000A; +CHECKREG r6, 0x6006000C; +CHECKREG r7, 0x7007000E; + + +imm32 r0, 0x10010700; +imm32 r1, 0x10010700; +R2.L = -15; +imm32 r3, 0x30030700; +imm32 r4, 0x40040000; +imm32 r5, 0x50050700; +imm32 r6, 0x60060000; +imm32 r7, 0x70070700; +R0.L = R0.H >>> 15; +R1.L = R1.H >>> 15; +R2.L = R2.H >>> 15; +R3.L = R3.H >>> 15; +R4.L = R4.H >>> 15; +R5.L = R5.H >>> 15; +R6.L = R6.H >>> 15; +R7.L = R7.H >>> 15; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x18010001; +imm32 r1, 0x18010001; +imm32 r2, 0x28020002; +R3.L = -16; +imm32 r4, 0x48040004; +imm32 r5, 0x58050005; +imm32 r6, 0x68060006; +imm32 r7, 0x78070007; +R0.L = R0.H >>> 13; +R1.L = R1.H >>> 13; +R2.L = R2.H >>> 13; +R3.L = R3.H >>> 13; +R4.L = R4.H >>> 13; +R5.L = R5.H >>> 13; +R6.L = R6.H >>> 13; +R7.L = R7.H >>> 13; +CHECKREG r0, 0x18010000; +CHECKREG r1, 0x18010000; +CHECKREG r2, 0x28020001; +CHECKREG r3, 0x30030001; +CHECKREG r4, 0x48040002; +CHECKREG r5, 0x58050002; +CHECKREG r6, 0x68060003; +CHECKREG r7, 0x78070003; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x09000091; +imm32 r1, 0x09000091; +imm32 r2, 0x09000092; +imm32 r3, 0x09000093; +imm32 r4, 0x09000090; +imm32 r5, 0x09000095; +imm32 r6, 0x09000096; +imm32 r7, 0x09000097; +R0.H = R0.L >>> 14; +R1.H = R1.L >>> 14; +R2.H = R2.L >>> 14; +R3.H = R3.L >>> 14; +R4.H = R4.L >>> 14; +R5.H = R5.L >>> 14; +R6.H = R6.L >>> 14; +R7.H = R7.L >>> 14; +CHECKREG r0, 0x00000091; +CHECKREG r1, 0x00000091; +CHECKREG r2, 0x00000092; +CHECKREG r3, 0x00000093; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0x00000095; +CHECKREG r6, 0x00000096; +CHECKREG r7, 0x00000097; + +imm32 r0, 0xa0000001; +imm32 r1, 0xa0000001; +imm32 r2, 0xa0000002; +imm32 r3, 0xa0000003; +imm32 r4, 0xa0000004; +R5.L = -1; +imm32 r6, 0xa0000006; +imm32 r7, 0xa0000007; +R0.H = R0.L >>> 15; +R1.H = R1.L >>> 15; +R2.H = R2.L >>> 15; +R3.H = R3.L >>> 15; +R4.H = R4.L >>> 15; +R5.H = R5.L >>> 15; +R6.H = R6.L >>> 15; +R7.H = R7.L >>> 15; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + + +imm32 r0, 0xb0001001; +imm32 r1, 0xb0001001; +imm32 r1, 0xb0002002; +imm32 r3, 0xb0003003; +imm32 r4, 0xb0004004; +imm32 r5, 0xb0005005; +R6.L = -15; +imm32 r7, 0xb0007007; +R0.H = R0.L >>> 6; +R1.H = R1.L >>> 6; +R2.H = R2.L >>> 6; +R3.H = R3.L >>> 6; +R4.H = R4.L >>> 6; +R5.H = R5.L >>> 6; +R6.H = R6.L >>> 6; +R7.H = R7.L >>> 6; +CHECKREG r0, 0x00401001; +CHECKREG r1, 0x00802002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00C03003; +CHECKREG r4, 0x01004004; +CHECKREG r5, 0x01405005; +CHECKREG r6, 0xFFFFFFF1; +CHECKREG r7, 0x01C07007; + +imm32 r0, 0x0c001c01; +imm32 r1, 0x0c002c01; +imm32 r2, 0x0c002c02; +imm32 r3, 0x0c003c03; +imm32 r4, 0x0c004c04; +imm32 r5, 0x0c005c05; +imm32 r6, 0x0c006c06; +R7.L = -16; +R0.H = R0.L >>> 7; +R1.H = R1.L >>> 7; +R2.H = R2.L >>> 7; +R3.H = R3.L >>> 7; +R4.H = R4.L >>> 7; +R5.H = R5.L >>> 7; +R6.H = R6.L >>> 7; +R7.H = R7.L >>> 7; +CHECKREG r0, 0x00381C01; +CHECKREG r1, 0x00582C01; +CHECKREG r2, 0x00582C02; +CHECKREG r3, 0x00783C03; +CHECKREG r4, 0x00984C04; +CHECKREG r5, 0x00B85C05; +CHECKREG r6, 0x00D86C06; +CHECKREG r7, 0xFFFFFFF0; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x0d01d000; +imm32 r1, 0x0d01d000; +imm32 r2, 0x0d02d000; +imm32 r3, 0x0d03d000; +R4.L = -1; +imm32 r5, 0x0d05d000; +imm32 r6, 0x0d06d000; +imm32 r7, 0x0d07d000; +R0.H = R0.H >>> 4; +R1.H = R1.H >>> 4; +R2.H = R2.H >>> 4; +R3.H = R3.H >>> 4; +R4.H = R4.H >>> 4; +R5.H = R5.H >>> 4; +R6.H = R6.H >>> 4; +R7.H = R6.H >>> 4; +CHECKREG r0, 0x00D0D000; +CHECKREG r1, 0x00D0D000; +CHECKREG r2, 0x00D0D000; +CHECKREG r3, 0x00D0D000; +CHECKREG r4, 0x0009FFFF; +CHECKREG r5, 0x00D0D000; +CHECKREG r6, 0x00D0D000; +CHECKREG r7, 0x000DD000; + +imm32 r0, 0x1e010000; +imm32 r1, 0x1e010000; +imm32 r2, 0x2e020000; +imm32 r3, 0x3e030000; +imm32 r4, 0x4e040000; +R5.L = -1; +imm32 r6, 0x6e060000; +imm32 r7, 0x7e070000; +R7.H = R0.H >>> 15; +R6.H = R1.H >>> 15; +R0.H = R2.H >>> 15; +R1.H = R3.H >>> 15; +R2.H = R4.H >>> 15; +R3.H = R5.H >>> 15; +R4.H = R6.H >>> 15; +R5.H = R7.H >>> 15; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x1f010000; +imm32 r1, 0x1f010000; +imm32 r2, 0x2f020000; +imm32 r3, 0x3f030000; +imm32 r4, 0x4f040000; +imm32 r5, 0x5f050000; +R6.L = -15; +imm32 r7, 0x70070000; +R6.H = R0.H >>> 6; +R7.H = R1.H >>> 6; +R5.H = R2.H >>> 6; +R0.H = R3.H >>> 6; +R1.H = R4.H >>> 6; +R2.H = R5.H >>> 6; +R3.H = R6.H >>> 6; +R4.H = R7.H >>> 6; +CHECKREG r0, 0x00FC0000; +CHECKREG r1, 0x013C0000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00010000; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x00BC0000; +CHECKREG r6, 0x007CFFF1; +CHECKREG r7, 0x007C0000; + +imm32 r0, 0x11010a00; +imm32 r1, 0x11010b00; +imm32 r2, 0x21020d00; +imm32 r2, 0x31030c00; +imm32 r4, 0x41040d00; +imm32 r5, 0x51050e00; +imm32 r6, 0x610600f0; +R7.L = -16; +R5.H = R0.H >>> 7; +R6.H = R1.H >>> 7; +R7.H = R2.H >>> 7; +R2.H = R3.H >>> 7; +R3.H = R4.H >>> 7; +R4.H = R5.H >>> 7; +R0.H = R6.H >>> 7; +R1.H = R7.H >>> 7; +CHECKREG r0, 0x00000A00; +CHECKREG r1, 0x00000B00; +CHECKREG r2, 0x00000C00; +CHECKREG r3, 0x00820000; +CHECKREG r4, 0x00000D00; +CHECKREG r5, 0x00220E00; +CHECKREG r6, 0x002200F0; +CHECKREG r7, 0x0062FFF0; +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_ahalf_rp_s.s b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_rp_s.s new file mode 100644 index 0000000..6429fb1 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_ahalf_rp_s.s @@ -0,0 +1,422 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_rp_s/c_dsp32shiftim_ahalf_rp_s.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=right (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00010001; +imm32 r2, 0x00010002; +imm32 r3, 0x00010003; +imm32 r4, 0x00010004; +imm32 r5, 0x00010005; +imm32 r6, 0x00010006; +imm32 r7, 0x00010007; +R0.L = R0.L >>> 1; +R1.L = R1.L >>> 1; +R2.L = R2.L >>> 1; +R3.L = R3.L >>> 1; +R4.L = R4.L >>> 1; +R5.L = R5.L >>> 1; +R6.L = R6.L >>> 1; +R7.L = R7.L >>> 1; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00010001; +CHECKREG r3, 0x00010001; +CHECKREG r4, 0x00010002; +CHECKREG r5, 0x00010002; +CHECKREG r6, 0x00010003; +CHECKREG r7, 0x00010003; + +imm32 r0, 0x00201001; +R1.L = -1; +imm32 r2, 0x00202002; +imm32 r3, 0x00203003; +imm32 r4, 0x00204004; +imm32 r5, 0x00205005; +imm32 r6, 0x00206006; +imm32 r7, 0x00207007; +R7.L = R0.L >>> 5; +R0.L = R1.L >>> 5; +R1.L = R2.L >>> 5; +R2.L = R3.L >>> 5; +R3.L = R4.L >>> 5; +R4.L = R5.L >>> 5; +R5.L = R6.L >>> 5; +R6.L = R7.L >>> 5; +CHECKREG r0, 0x0020FFFF; +CHECKREG r1, 0x00010100; +CHECKREG r2, 0x00200180; +CHECKREG r3, 0x00200200; +CHECKREG r4, 0x00200280; +CHECKREG r5, 0x00200300; +CHECKREG r6, 0x00200004; +CHECKREG r7, 0x00200080; + + +imm32 r0, 0x03001001; +imm32 r1, 0x03001001; +R2.L = -15; +imm32 r3, 0x03003003; +imm32 r4, 0x03004004; +imm32 r5, 0x03005005; +imm32 r6, 0x03006006; +imm32 r7, 0x03007007; +R6.L = R0.L >>> 2; +R7.L = R1.L >>> 2; +R0.L = R2.L >>> 2; +R1.L = R3.L >>> 2; +R2.L = R4.L >>> 2; +R3.L = R5.L >>> 2; +R4.L = R6.L >>> 2; +R5.L = R7.L >>> 2; +CHECKREG r0, 0x0300FFFC; +CHECKREG r1, 0x03000C00; +CHECKREG r2, 0x00201001; +CHECKREG r3, 0x03001401; +CHECKREG r4, 0x03000100; +CHECKREG r5, 0x03000100; +CHECKREG r6, 0x03000400; +CHECKREG r7, 0x03000400; + +imm32 r0, 0x40001001; +imm32 r1, 0x40001001; +imm32 r2, 0x40002002; +R3.L = -16; +imm32 r4, 0x40004004; +imm32 r5, 0x40005005; +imm32 r6, 0x40006006; +imm32 r7, 0x40007007; +R5.L = R0.L >>> 13; +R6.L = R1.L >>> 13; +R7.L = R2.L >>> 13; +R0.L = R3.L >>> 13; +R1.L = R4.L >>> 13; +R2.L = R5.L >>> 13; +R3.L = R6.L >>> 13; +R4.L = R7.L >>> 13; +CHECKREG r0, 0x4000FFFF; +CHECKREG r1, 0x40000002; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0x03000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x40000000; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x40000001; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x50000000; +imm32 r1, 0x50010000; +imm32 r2, 0x50020000; +imm32 r3, 0x50030000; +imm32 r4, 0x50040000; +imm32 r5, 0x50050000; +imm32 r6, 0x50060000; +imm32 r7, 0x50070000; +R3.L = R0.H >>> 10; +R4.L = R1.H >>> 10; +R5.L = R2.H >>> 10; +R6.L = R3.H >>> 10; +R7.L = R4.H >>> 10; +R0.L = R5.H >>> 10; +R1.L = R6.H >>> 10; +R2.L = R7.H >>> 10; +CHECKREG r0, 0x50000014; +CHECKREG r1, 0x50010014; +CHECKREG r2, 0x50020014; +CHECKREG r3, 0x50030014; +CHECKREG r4, 0x50040014; +CHECKREG r5, 0x50050014; +CHECKREG r6, 0x50060014; +CHECKREG r7, 0x50070014; + +imm32 r0, 0x10016000; +R1.L = -1; +imm32 r2, 0x20026000; +imm32 r3, 0x30036000; +imm32 r4, 0x40046000; +imm32 r5, 0x50056000; +imm32 r6, 0x60060000; +imm32 r7, 0x70076000; +R0.L = R0.H >>> 11; +R1.L = R1.H >>> 11; +R2.L = R2.H >>> 11; +R3.L = R3.H >>> 11; +R4.L = R4.H >>> 11; +R5.L = R5.H >>> 11; +R6.L = R6.H >>> 11; +R7.L = R7.H >>> 11; +CHECKREG r0, 0x10010002; +CHECKREG r1, 0x5001000A; +CHECKREG r2, 0x20020004; +CHECKREG r3, 0x30030006; +CHECKREG r4, 0x40040008; +CHECKREG r5, 0x5005000A; +CHECKREG r6, 0x6006000C; +CHECKREG r7, 0x7007000E; + + +imm32 r0, 0x10010700; +imm32 r1, 0x10010700; +R2.L = -15; +imm32 r3, 0x30030700; +imm32 r4, 0x40040000; +imm32 r5, 0x50050700; +imm32 r6, 0x60060000; +imm32 r7, 0x70070700; +R0.L = R0.H >>> 15; +R1.L = R1.H >>> 15; +R2.L = R2.H >>> 15; +R3.L = R3.H >>> 15; +R4.L = R4.H >>> 15; +R5.L = R5.H >>> 15; +R6.L = R6.H >>> 15; +R7.L = R7.H >>> 15; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x18010001; +imm32 r1, 0x18010001; +imm32 r2, 0x28020002; +R3.L = -16; +imm32 r4, 0x48040004; +imm32 r5, 0x58050005; +imm32 r6, 0x68060006; +imm32 r7, 0x78070007; +R0.L = R0.H >>> 13; +R1.L = R1.H >>> 13; +R2.L = R2.H >>> 13; +R3.L = R3.H >>> 13; +R4.L = R4.H >>> 13; +R5.L = R5.H >>> 13; +R6.L = R6.H >>> 13; +R7.L = R7.H >>> 13; +CHECKREG r0, 0x18010000; +CHECKREG r1, 0x18010000; +CHECKREG r2, 0x28020001; +CHECKREG r3, 0x30030001; +CHECKREG r4, 0x48040002; +CHECKREG r5, 0x58050002; +CHECKREG r6, 0x68060003; +CHECKREG r7, 0x78070003; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x09000091; +imm32 r1, 0x09000091; +imm32 r2, 0x09000092; +imm32 r3, 0x09000093; +imm32 r4, 0x09000090; +imm32 r5, 0x09000095; +imm32 r6, 0x09000096; +imm32 r7, 0x09000097; +R0.H = R0.L >>> 14; +R1.H = R1.L >>> 14; +R2.H = R2.L >>> 14; +R3.H = R3.L >>> 14; +R4.H = R4.L >>> 14; +R5.H = R5.L >>> 14; +R6.H = R6.L >>> 14; +R7.H = R7.L >>> 14; +CHECKREG r0, 0x00000091; +CHECKREG r1, 0x00000091; +CHECKREG r2, 0x00000092; +CHECKREG r3, 0x00000093; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0x00000095; +CHECKREG r6, 0x00000096; +CHECKREG r7, 0x00000097; + +imm32 r0, 0xa0000001; +imm32 r1, 0xa0000001; +imm32 r2, 0xa0000002; +imm32 r3, 0xa0000003; +imm32 r4, 0xa0000004; +R5.L = -1; +imm32 r6, 0xa0000006; +imm32 r7, 0xa0000007; +R0.H = R0.L >>> 15; +R1.H = R1.L >>> 15; +R2.H = R2.L >>> 15; +R3.H = R3.L >>> 15; +R4.H = R4.L >>> 15; +R5.H = R5.L >>> 15; +R6.H = R6.L >>> 15; +R7.H = R7.L >>> 15; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + + +imm32 r0, 0xb0001001; +imm32 r1, 0xb0001001; +imm32 r1, 0xb0002002; +imm32 r3, 0xb0003003; +imm32 r4, 0xb0004004; +imm32 r5, 0xb0005005; +R6.L = -15; +imm32 r7, 0xb0007007; +R0.H = R0.L >>> 6; +R1.H = R1.L >>> 6; +R2.H = R2.L >>> 6; +R3.H = R3.L >>> 6; +R4.H = R4.L >>> 6; +R5.H = R5.L >>> 6; +R6.H = R6.L >>> 6; +R7.H = R7.L >>> 6; +CHECKREG r0, 0x00401001; +CHECKREG r1, 0x00802002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00C03003; +CHECKREG r4, 0x01004004; +CHECKREG r5, 0x01405005; +CHECKREG r6, 0xFFFFFFF1; +CHECKREG r7, 0x01C07007; + +imm32 r0, 0x0c001c01; +imm32 r1, 0x0c002c01; +imm32 r2, 0x0c002c02; +imm32 r3, 0x0c003c03; +imm32 r4, 0x0c004c04; +imm32 r5, 0x0c005c05; +imm32 r6, 0x0c006c06; +R7.L = -16; +R0.H = R0.L >>> 7; +R1.H = R1.L >>> 7; +R2.H = R2.L >>> 7; +R3.H = R3.L >>> 7; +R4.H = R4.L >>> 7; +R5.H = R5.L >>> 7; +R6.H = R6.L >>> 7; +R7.H = R7.L >>> 7; +CHECKREG r0, 0x00381C01; +CHECKREG r1, 0x00582C01; +CHECKREG r2, 0x00582C02; +CHECKREG r3, 0x00783C03; +CHECKREG r4, 0x00984C04; +CHECKREG r5, 0x00B85C05; +CHECKREG r6, 0x00D86C06; +CHECKREG r7, 0xFFFFFFF0; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x0d01d000; +imm32 r1, 0x0d01d000; +imm32 r2, 0x0d02d000; +imm32 r3, 0x0d03d000; +R4.L = -1; +imm32 r5, 0x0d05d000; +imm32 r6, 0x0d06d000; +imm32 r7, 0x0d07d000; +R0.H = R0.H >>> 4; +R1.H = R1.H >>> 4; +R2.H = R2.H >>> 4; +R3.H = R3.H >>> 4; +R4.H = R4.H >>> 4; +R5.H = R5.H >>> 4; +R6.H = R6.H >>> 4; +R7.H = R6.H >>> 4; +CHECKREG r0, 0x00D0D000; +CHECKREG r1, 0x00D0D000; +CHECKREG r2, 0x00D0D000; +CHECKREG r3, 0x00D0D000; +CHECKREG r4, 0x0009FFFF; +CHECKREG r5, 0x00D0D000; +CHECKREG r6, 0x00D0D000; +CHECKREG r7, 0x000DD000; + +imm32 r0, 0x1e010000; +imm32 r1, 0x1e010000; +imm32 r2, 0x2e020000; +imm32 r3, 0x3e030000; +imm32 r4, 0x4e040000; +R5.L = -1; +imm32 r6, 0x6e060000; +imm32 r7, 0x7e070000; +R7.H = R0.H >>> 15; +R6.H = R1.H >>> 15; +R0.H = R2.H >>> 15; +R1.H = R3.H >>> 15; +R2.H = R4.H >>> 15; +R3.H = R5.H >>> 15; +R4.H = R6.H >>> 15; +R5.H = R7.H >>> 15; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x1f010000; +imm32 r1, 0x1f010000; +imm32 r2, 0x2f020000; +imm32 r3, 0x3f030000; +imm32 r4, 0x4f040000; +imm32 r5, 0x5f050000; +R6.L = -15; +imm32 r7, 0x70070000; +R6.H = R0.H >>> 6; +R7.H = R1.H >>> 6; +R5.H = R2.H >>> 6; +R0.H = R3.H >>> 6; +R1.H = R4.H >>> 6; +R2.H = R5.H >>> 6; +R3.H = R6.H >>> 6; +R4.H = R7.H >>> 6; +CHECKREG r0, 0x00FC0000; +CHECKREG r1, 0x013C0000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00010000; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x00BC0000; +CHECKREG r6, 0x007CFFF1; +CHECKREG r7, 0x007C0000; + +imm32 r0, 0x11010a00; +imm32 r1, 0x11010b00; +imm32 r2, 0x21020d00; +imm32 r2, 0x31030c00; +imm32 r4, 0x41040d00; +imm32 r5, 0x51050e00; +imm32 r6, 0x610600f0; +R7.L = -16; +R5.H = R0.H >>> 7; +R6.H = R1.H >>> 7; +R7.H = R2.H >>> 7; +R2.H = R3.H >>> 7; +R3.H = R4.H >>> 7; +R4.H = R5.H >>> 7; +R0.H = R6.H >>> 7; +R1.H = R7.H >>> 7; +CHECKREG r0, 0x00000A00; +CHECKREG r1, 0x00000B00; +CHECKREG r2, 0x00000C00; +CHECKREG r3, 0x00820000; +CHECKREG r4, 0x00000D00; +CHECKREG r5, 0x00220E00; +CHECKREG r6, 0x002200F0; +CHECKREG r7, 0x0062FFF0; +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_ahh.s b/sim/testsuite/bfin/c_dsp32shiftim_ahh.s new file mode 100644 index 0000000..79d1924 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_ahh.s @@ -0,0 +1,65 @@ +//Original:/testcases/core/c_dsp32shiftim_ahh/c_dsp32shiftim_ahh.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: ashift / ashift + + + +imm32 r0, 0x01230abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0 = R0 << 0 (V); +R1 = R1 << 3 (V); +R2 = R2 << 5 (V); +R3 = R3 << 8 (V); +R4 = R4 << 9 (V); +R5 = R5 << 15 (V); +R6 = R6 << 7 (V); +R7 = R7 << 13 (V); +CHECKREG r0, 0x01230ABC; +CHECKREG r1, 0x91A0B3C0; +CHECKREG r2, 0x68A0F120; +CHECKREG r3, 0x56009A00; +CHECKREG r4, 0xCE005600; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xC480E680; +CHECKREG r7, 0x4000C000; + +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7 = R0 >>> 1 (V); +R0 = R1 >>> 8 (V); +R1 = R2 >>> 14 (V); +R2 = R3 >>> 15 (V); +R3 = R4 >>> 11 (V); +R4 = R5 >>> 4 (V); +R5 = R6 >>> 9 (V); +R6 = R7 >>> 6 (V); +CHECKREG r0, 0x00120056; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x0008FFF1; +CHECKREG r4, 0x0567F9AB; +CHECKREG r5, 0x0033FFD5; +CHECKREG r6, 0x00020000; +CHECKREG r7, 0x00910000; + + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_ahh_s.s b/sim/testsuite/bfin/c_dsp32shiftim_ahh_s.s new file mode 100644 index 0000000..9e69f2a --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_ahh_s.s @@ -0,0 +1,65 @@ +//Original:/testcases/core/c_dsp32shiftim_ahh_s/c_dsp32shiftim_ahh_s.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: ashift / ashift saturated + + + +imm32 r0, 0x01230abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0 = R0 << 0 (V , S); +R1 = R1 << 3 (V , S); +R2 = R2 << 5 (V , S); +R3 = R3 << 8 (V , S); +R4 = R4 << 9 (V , S); +R5 = R5 << 15 (V , S); +R6 = R6 << 7 (V , S); +R7 = R7 << 13 (V , S); +CHECKREG r0, 0x01230ABC; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF8000; + +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7 = R0 >>> 1 (V, S); +R0 = R1 >>> 8 (V, S); +R1 = R2 >>> 14 (V, S); +R2 = R3 >>> 15 (V, S); +R3 = R4 >>> 11 (V, S); +R4 = R5 >>> 4 (V, S); +R5 = R6 >>> 9 (V, S); +R6 = R7 >>> 6 (V, S); +CHECKREG r0, 0x00120056; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x0008FFF1; +CHECKREG r4, 0x0567F9AB; +CHECKREG r5, 0x0033FFD5; +CHECKREG r6, 0x00020000; +CHECKREG r7, 0x00910000; + + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_amix.s b/sim/testsuite/bfin/c_dsp32shiftim_amix.s new file mode 100644 index 0000000..d1c0c20 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_amix.s @@ -0,0 +1,149 @@ +//Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: mix + + + +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// Ashift : positive data, count (+)=left (half reg) +imm32 r0, 0x00010001; +imm32 r1, 1; +imm32 r2, 0x00020002; +imm32 r3, 2; +R4.H = R0.H << 1; +R4.L = R0.L << 1; /* r4 = 0x00020002 */ +R5.H = R2.H << 2; +R5.L = R2.L << 2; /* r5 = 0x00080008 */ +R6 = R0 << 1 (V); /* r6 = 0x00020002 */ +R7 = R2 << 2 (V); /* r7 = 0x00080008 */ +CHECKREG r4, 0x00020002; +CHECKREG r5, 0x00080008; +CHECKREG r6, 0x00020002; +CHECKREG r7, 0x00080008; + +imm32 r1, 3; +imm32 r3, 4; +R6 = R0 << 3; /* r6 = 0x00080010 */ +R7 = R2 << 4; +CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ +CHECKREG r7, 0x00200020; + +A0 = 0; +A0.L = R0.L; +A0.H = R0.H; +A0 = A0 << 3; /* a0 = 0x00080008 */ +R5 = A0.w; /* r5 = 0x00080008 */ +CHECKREG r5, 0x00080008; + +imm32 r4, 0x30000003; +imm32 r1, 1; +R5 = R4 << 1; /* r5 = 0x60000006 */ + +imm32 r1, 2; +R6 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */ +CHECKREG r5, 0x60000006; +CHECKREG r6, 0xc000000c; + + +// Ashift : count (-)=right (half reg) +imm32 r0, 0x10001000; +imm32 r1, -1; +imm32 r2, 0x10001000; +imm32 r3, -2; +R4.H = R0.H >>> 1; +R4.L = R0.L >>> 1; /* r4 = 0x08000800 */ +R5.H = R2.H >>> 2; +R5.L = R2.L >>> 2; /* r4 = 0x04000400 */ +R6 = R0 >>> 1 (V); /* r4 = 0x08000800 */ +R7 = R2 >>> 2 (V); /* r4 = 0x04000400 */ +CHECKREG r4, 0x08000800; +CHECKREG r5, 0x04000400; +CHECKREG r6, 0x08000800; +CHECKREG r7, 0x04000400; + +// Ashift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = R0 >>> 3; /* r6 = 0x02000200 */ +R7 = R2 >>> 4; /* r7 = 0x01000100 */ +CHECKREG r6, 0x02000200; +CHECKREG r7, 0x01000100; + +// NEGATIVE +// Ashift : NEGATIVE data, count (+)=left (half reg) +imm32 r0, 0xc00f800f; +imm32 r1, 1; +imm32 r2, 0xe00fe00f; +imm32 r3, 2; +R4.H = R0.H << 1; +R4.L = R0.L << 1 (S); /* r4 = 0x801e801e */ +R5.H = R2.H << 2; +R5.L = R2.L << 2; /* r4 = 0x803c803c */ +CHECKREG r4, 0x801e8000; +CHECKREG r5, 0x803c803c; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +imm32 r1, 4; +imm32 r3, 5; +R6 = R0 << 4; /* r6 = 0x80fe00f0 */ +R7 = R2 << 5; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xf80fe00f; +imm32 r2, 0xfc0fe00f; +R6 = R0 << 4 (S); /* r6 = 0x80fe00f0 */ +R7 = R2 << 5 (S); /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +R6 = R0 << 4 (S); /* r6 = 0x80000000 zero bubble tru MSB */ +R7 = R2 << 5 (S); /* r7 = 0x80000000 */ +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + +imm32 r0, 0xFFFFFFF4; +imm32 r2, 0xFFF00001; +R6 = R0 << 31 (S); /* r6 = 0x80000000 */ +R7 = R2 << 31 (S); /* r7 = 0x80000000 */ +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + + +// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok +imm32 r0, 0x80f080f0; +imm32 r1, -1; +imm32 r2, 0x80f080f0; +imm32 r3, -2; +R4.H = R0.H >>> 1; +R4.L = R0.L >>> 1; /* r4 = 0xc078c078 */ +R5.H = R2.H >>> 2; +R5.L = R2.L >>> 2; /* r4 = 0xe03ce03c */ +CHECKREG r4, 0xc078c078; +CHECKREG r5, 0xe03ce03c; +R6 = R0 >>> 1 (V); /* r6 = 0xc078c078 */ +R7 = R2 >>> 2 (V); /* r7 = 0xe03ce03c */ +CHECKREG r6, 0xc078c078; +CHECKREG r7, 0xe03ce03c; + +imm32 r1, -3; +imm32 r3, -4; +R6 = R0 >>> 3; /* r6 = 0xf01e101e */ +R7 = R2 >>> 4; /* r7 = 0xf80f080f */ +CHECKREG r6, 0xf01e101e; +CHECKREG r7, 0xf80f080f; + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_lf.s b/sim/testsuite/bfin/c_dsp32shiftim_lf.s new file mode 100644 index 0000000..3083173 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_lf.s @@ -0,0 +1,63 @@ +//Original:/testcases/core/c_dsp32shiftim_lf/c_dsp32shiftim_lf.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm lshift: lshift + + +imm32 r0, 0xa1230001; +imm32 r1, 0x1b345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x34d6789a; +imm32 r4, 0x85a789ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb8912cde; +R0 = R0 << 0; +R1 = R1 << 3; +R2 = R2 << 7; +R3 = R3 << 8; +R4 = R4 << 15; +R5 = R5 << 24; +R6 = R6 << 31; +R7 = R7 << 20; +CHECKREG r0, 0xA1230001; +CHECKREG r1, 0xD9A2B3C0; +CHECKREG r2, 0xE2B3C480; +CHECKREG r3, 0xD6789A00; +CHECKREG r4, 0xC4D58000; +CHECKREG r5, 0xBC000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0xCDE00000; + +imm32 r0, 0xa1230001; +imm32 r1, 0x1b345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x34d6789a; +imm32 r4, 0x85a789ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb8912cde; +R6 = R0 >> 1; +R7 = R1 >> 3; +R0 = R2 >> 7; +R1 = R3 >> 8; +R2 = R4 >> 15; +R3 = R5 >> 24; +R4 = R6 >> 31; +R5 = R7 >> 20; +CHECKREG r0, 0x00478ACF; +CHECKREG r1, 0x0034D678; +CHECKREG r2, 0x00010B4F; +CHECKREG r3, 0x00000096; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000036; +CHECKREG r6, 0x50918000; +CHECKREG r7, 0x03668ACF; + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_lhalf_ln.s b/sim/testsuite/bfin/c_dsp32shiftim_lhalf_ln.s new file mode 100644 index 0000000..36004fd --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_lhalf_ln.s @@ -0,0 +1,401 @@ +//Original:/testcases/core/c_dsp32shiftim_lhalf_ln/c_dsp32shiftim_lhalf_ln.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : neg data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R0.L = R0.L << 1; +R1.L = R1.L << 0; +R2.L = R2.L << 0; +R3.L = R3.L << 0; +R4.L = R4.L << 0; +R5.L = R5.L << 0; +R6.L = R6.L << 0; +R7.L = R7.L << 0; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000C001; +CHECKREG r2, 0x0000C002; +CHECKREG r3, 0x0000C003; +CHECKREG r4, 0x0000C004; +CHECKREG r5, 0x0000C005; +CHECKREG r6, 0x0000C006; +CHECKREG r7, 0x0000C007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R1.L = R0.L << 1; +R2.L = R1.L << 2; +R3.L = R2.L << 3; +R4.L = R3.L << 4; +R5.L = R4.L << 5; +R6.L = R5.L << 6; +R7.L = R6.L << 7; +R0.L = R7.L << 8; +imm32 r1, 0x2000d001; +imm32 r2, 0x2000000f; +imm32 r3, 0x2000e003; +imm32 r4, 0x2000f004; +imm32 r5, 0x2200f005; +imm32 r6, 0x2000f006; +imm32 r7, 0x2000f007; +imm32 r0, 0x2000c001; + +R2.L = R0.L << 10; +R3.L = R1.L << 12; +R4.L = R2.L << 13; +R5.L = R3.L << 14; +R6.L = R4.L << 15; +R7.L = R5.L << 15; +R0.L = R6.L << 2; +R1.L = R7.L << 3; +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x20000000; +CHECKREG r2, 0x20000400; +CHECKREG r3, 0x20001000; +CHECKREG r4, 0x20000000; +CHECKREG r5, 0x22000000; +CHECKREG r6, 0x20000000; +CHECKREG r7, 0x20000000; + +imm32 r0, 0x30009001; +imm32 r1, 0x3000a001; +imm32 r2, 0x3000b002; +imm32 r3, 0x30000010; +imm32 r4, 0x3000c004; +imm32 r5, 0x3000d005; +imm32 r6, 0x3000e006; +imm32 r7, 0x3000f007; +R3.L = R0.L << 12; +R4.L = R1.L << 13; +R5.L = R2.L << 14; +R6.L = R3.L << 15; +R7.L = R4.L << 11; +R0.L = R5.L << 12; +R1.L = R6.L << 13; +R2.L = R7.L << 15; +CHECKREG r0, 0x30000000; +CHECKREG r1, 0x30000000; +CHECKREG r2, 0x30000000; +CHECKREG r3, 0x30001000; +CHECKREG r4, 0x30002000; +CHECKREG r5, 0x30008000; +CHECKREG r6, 0x30000000; +CHECKREG r7, 0x30000000; +// RHx by RLx +imm32 r0, 0x00000040; +imm32 r1, 0x00010040; +imm32 r2, 0x00020040; +imm32 r3, 0x00030040; +imm32 r4, 0x00040040; +imm32 r5, 0x00050040; +imm32 r6, 0x00060040; +imm32 r7, 0x00070040; +R0.L = R0.H << 0; +R1.L = R1.H << 1; +R2.L = R2.H << 2; +R3.L = R3.H << 3; +R4.L = R4.H << 4; +R5.L = R5.H << 5; +R6.L = R6.H << 6; +R7.L = R7.H << 7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010002; +CHECKREG r2, 0x00020008; +CHECKREG r3, 0x00030018; +CHECKREG r4, 0x00040040; +CHECKREG r5, 0x000500A0; +CHECKREG r6, 0x00060180; +CHECKREG r7, 0x00070380; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R1.L = R0.H << 1; +R2.L = R1.H << 2; +R3.L = R2.H << 3; +R4.L = R3.H << 4; +R5.L = R4.H << 5; +R6.L = R5.H << 6; +R7.L = R6.H << 7; +R0.L = R7.H << 8; +CHECKREG r1, 0x00012002; +CHECKREG r2, 0x90020004; +CHECKREG r3, 0x90038010; +CHECKREG r4, 0x90040030; +CHECKREG r5, 0x90050080; +CHECKREG r6, 0x90060140; +CHECKREG r7, 0x90070300; +CHECKREG r0, 0x90010700; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R2.L = R0.H << 15; +R3.L = R1.H << 15; +R4.L = R2.H << 15; +R5.L = R3.H << 15; +R6.L = R4.H << 15; +R7.L = R5.H << 15; +R0.L = R6.H << 15; +R1.L = R7.H << 15; +CHECKREG r0, 0xA0010000; +CHECKREG r1, 0xA0018000; +CHECKREG r2, 0xA0028000; +CHECKREG r3, 0xA0038000; +CHECKREG r4, 0xA0040000; +CHECKREG r5, 0xA0058000; +CHECKREG r6, 0xA0060000; +CHECKREG r7, 0xA0078000; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc0070007; +R3.L = R0.H << 14; +R4.L = R1.H << 14; +R5.L = R2.H << 14; +R6.L = R3.H << 14; +R7.L = R4.H << 14; +R0.L = R5.H << 14; +R1.L = R6.H << 14; +R2.L = R7.H << 14; +CHECKREG r0, 0xC0014000; +CHECKREG r1, 0xC0018000; +CHECKREG r2, 0xC002C000; +CHECKREG r3, 0xC0034000; +CHECKREG r4, 0xC0044000; +CHECKREG r5, 0xC0058000; +CHECKREG r6, 0xC006C000; +CHECKREG r7, 0xC0070000; + +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = R0.L << 12; +R1.H = R1.L << 12; +R2.H = R2.L << 13; +R3.H = R3.L << 14; +R4.H = R4.L << 15; +R5.H = R5.L << 14; +R6.H = R6.L << 7; +R7.H = R7.L << 8; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x10000001; +CHECKREG r2, 0x40000002; +CHECKREG r3, 0xC0000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x40000005; +CHECKREG r6, 0x03000006; +CHECKREG r7, 0x07000007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R1.H = R0.L << 3; +R2.H = R1.L << 4; +R3.H = R2.L << 5; +R4.H = R3.L << 6; +R5.H = R4.L << 7; +R6.H = R5.L << 8; +R7.H = R6.L << 9; +R0.H = R7.L << 8; +CHECKREG r1, 0x80080001; +CHECKREG r2, 0x0010D002; +CHECKREG r3, 0x0040D003; +CHECKREG r4, 0x00C0D004; +CHECKREG r5, 0x0200D005; +CHECKREG r6, 0x0500D006; +CHECKREG r7, 0x0C00D007; +CHECKREG r0, 0x0700D001; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R2.H = R0.L << 15; +R3.H = R1.L << 15; +R4.H = R2.L << 15; +R5.H = R3.L << 15; +R6.H = R4.L << 15; +R7.H = R5.L << 15; +R0.H = R6.L << 15; +R1.H = R7.L << 15; +CHECKREG r0, 0x0000E001; +CHECKREG r1, 0x8000E001; +CHECKREG r2, 0x8000000F; +CHECKREG r3, 0x8000E003; +CHECKREG r4, 0x8000E004; +CHECKREG r5, 0x8000E005; +CHECKREG r6, 0x0000E006; +CHECKREG r7, 0x8000E007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R3.H = R0.L << 13; +R4.H = R1.L << 13; +R5.H = R2.L << 13; +R6.H = R3.L << 13; +R7.H = R4.L << 13; +R0.H = R5.L << 13; +R1.H = R6.L << 13; +R2.H = R7.L << 13; +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = R0.H << 0; +R1.H = R1.H << 0; +R2.H = R2.H << 0; +R3.H = R3.H << 0; +R4.H = R4.H << 0; +R5.H = R5.H << 0; +R6.H = R6.H << 0; +R7.H = R7.H << 0; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R1.H = R0.H << 1; +R2.H = R1.H << 1; +R3.H = R2.H << 1; +R4.H = R3.H << 1; +R5.H = R4.H << 1; +R6.H = R5.H << 1; +R7.H = R6.H << 1; +R0.H = R7.H << 1; +CHECKREG r1, 0x40020001; +CHECKREG r2, 0x80040000; +CHECKREG r3, 0x00080000; +CHECKREG r4, 0x00100000; +CHECKREG r5, 0x00200000; +CHECKREG r6, 0x00400000; +CHECKREG r7, 0x00800000; +CHECKREG r0, 0x01000000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R2.H = R0.H << 15; +R3.H = R1.H << 15; +R4.H = R2.H << 15; +R5.H = R3.H << 15; +R6.H = R4.H << 15; +R7.H = R5.H << 15; +R0.H = R6.H << 15; +R1.H = R7.H << 15; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x8000000F; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R6.H = R0.H << 12; +R7.H = R1.H << 12; +R0.H = R2.H << 12; +R1.H = R3.H << 12; +R2.H = R4.H << 12; +R3.H = R5.H << 12; +R4.H = R6.H << 12; +R5.H = R7.H << 12; +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x30000000; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0x50000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x10000000; +CHECKREG r7, 0x10000000; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_lhalf_lp.s b/sim/testsuite/bfin/c_dsp32shiftim_lhalf_lp.s new file mode 100644 index 0000000..53e53f2 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_lhalf_lp.s @@ -0,0 +1,418 @@ +//Original:/testcases/core/c_dsp32shiftim_lhalf_lp/c_dsp32shiftim_lhalf_lp.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY imm5) +// RLx by imm5 +imm32 r0, 0x00100a00; +imm32 r1, 0x00100a01; +imm32 r2, 0x00100a02; +imm32 r3, 0x00100a03; +imm32 r4, 0x00100a04; +imm32 r5, 0x00100a05; +imm32 r6, 0x00100a06; +imm32 r7, 0x00100a07; +R7.L = R0.L << 0; +R0.L = R1.L << 1; +R1.L = R2.L << 2; +R2.L = R3.L << 3; +R3.L = R4.L << 4; +R4.L = R5.L << 5; +R5.L = R6.L << 6; +R6.L = R7.L << 7; +CHECKREG r1, 0x00102808; +CHECKREG r0, 0x00101402; +CHECKREG r2, 0x00105018; +CHECKREG r3, 0x0010A040; +CHECKREG r4, 0x001040A0; +CHECKREG r5, 0x00108180; +CHECKREG r6, 0x00100000; +CHECKREG r7, 0x00100A00; + +imm32 r0, 0x00200018; +imm32 r1, 0x00200019; +imm32 r2, 0x0020001a; +imm32 r3, 0x0020001b; +imm32 r4, 0x0020001c; +imm32 r5, 0x0020001d; +imm32 r6, 0x0020001e; +imm32 r7, 0x0020001f; +R2.L = R0.L << 8; +R3.L = R1.L << 9; +R4.L = R2.L << 10; +R5.L = R3.L << 11; +R6.L = R4.L << 12; +R7.L = R5.L << 13; +R0.L = R6.L << 14; +R1.L = R7.L << 15; +CHECKREG r0, 0x00200000; +CHECKREG r1, 0x00200000; +CHECKREG r2, 0x00201800; +CHECKREG r3, 0x00203200; +CHECKREG r4, 0x00200000; +CHECKREG r5, 0x00200000; +CHECKREG r6, 0x00200000; +CHECKREG r7, 0x00200000; + +imm32 r0, 0x05002001; +imm32 r1, 0x05002001; +imm32 r2, 0x0500000f; +imm32 r3, 0x05002003; +imm32 r4, 0x05002004; +imm32 r5, 0x05002005; +imm32 r6, 0x05002006; +imm32 r7, 0x05002007; +R3.L = R0.L << 0; +R4.L = R1.L << 1; +R5.L = R2.L << 2; +R6.L = R3.L << 3; +R7.L = R4.L << 4; +R0.L = R5.L << 5; +R1.L = R6.L << 6; +R2.L = R7.L << 7; +CHECKREG r0, 0x05000780; +CHECKREG r1, 0x05000200; +CHECKREG r2, 0x05001000; +CHECKREG r3, 0x05002001; +CHECKREG r4, 0x05004002; +CHECKREG r5, 0x0500003C; +CHECKREG r6, 0x05000008; +CHECKREG r7, 0x05000020; + +imm32 r0, 0x03000031; +imm32 r1, 0x03000031; +imm32 r2, 0x03000032; +imm32 r3, 0x03000030; +imm32 r4, 0x03000034; +imm32 r5, 0x03000035; +imm32 r6, 0x03000036; +imm32 r7, 0x03000037; +R4.L = R0.L << 8; +R5.L = R1.L << 9; +R6.L = R2.L << 10; +R7.L = R3.L << 11; +R0.L = R4.L << 12; +R1.L = R5.L << 13; +R2.L = R6.L << 14; +R3.L = R7.L << 15; +CHECKREG r0, 0x03000000; +CHECKREG r1, 0x03000000; +CHECKREG r2, 0x03000000; +CHECKREG r3, 0x03000000; +CHECKREG r4, 0x03003100; +CHECKREG r5, 0x03006200; +CHECKREG r6, 0x0300C800; +CHECKREG r7, 0x03008000; +// RHx by RLx +imm32 r0, 0x03000000; +imm32 r1, 0x03000000; +imm32 r2, 0x03000000; +imm32 r3, 0x03000000; +imm32 r4, 0x03003100; +imm32 r5, 0x03006200; +imm32 r6, 0x0300C800; +imm32 r7, 0x03008000; +R5.L = R0.H << 0; +R6.L = R1.H << 1; +R7.L = R2.H << 2; +R0.L = R3.H << 3; +R1.L = R4.H << 4; +R2.L = R5.H << 5; +R3.L = R6.H << 6; +R4.L = R7.H << 7; +CHECKREG r0, 0x03001800; +CHECKREG r1, 0x03003000; +CHECKREG r2, 0x03006000; +CHECKREG r3, 0x0300C000; +CHECKREG r4, 0x03008000; +CHECKREG r5, 0x03000300; +CHECKREG r6, 0x03000600; +CHECKREG r7, 0x03000C00; + +imm32 r0, 0x05018000; +imm32 r1, 0x05018001; +imm32 r2, 0x05028000; +imm32 r3, 0x05038000; +imm32 r4, 0x05048000; +imm32 r5, 0x05058000; +imm32 r6, 0x05068000; +imm32 r7, 0x05078000; +R6.L = R0.H << 8; +R7.L = R1.H << 9; +R0.L = R2.H << 10; +R1.L = R3.H << 11; +R2.L = R4.H << 12; +R3.L = R5.H << 13; +R4.L = R6.H << 14; +R5.L = R7.H << 15; +CHECKREG r0, 0x05010800; +CHECKREG r1, 0x05011800; +CHECKREG r2, 0x05024000; +CHECKREG r3, 0x0503A000; +CHECKREG r4, 0x05048000; +CHECKREG r5, 0x05058000; +CHECKREG r6, 0x05060100; +CHECKREG r7, 0x05070200; + + +imm32 r0, 0x60019000; +imm32 r1, 0x60019000; +imm32 r2, 0x6002900f; +imm32 r3, 0x60039000; +imm32 r4, 0x60049000; +imm32 r5, 0x60059000; +imm32 r6, 0x60069000; +imm32 r7, 0x60079000; +R7.L = R0.H << 0; +R0.L = R1.H << 1; +R1.L = R2.H << 2; +R2.L = R3.H << 3; +R3.L = R4.H << 4; +R4.L = R5.H << 5; +R5.L = R6.H << 6; +R6.L = R7.H << 7; +CHECKREG r0, 0x6001C002; +CHECKREG r1, 0x60018008; +CHECKREG r2, 0x60020018; +CHECKREG r3, 0x60030040; +CHECKREG r4, 0x600400A0; +CHECKREG r5, 0x60050180; +CHECKREG r6, 0x60060380; +CHECKREG r7, 0x60076001; + +imm32 r0, 0x70010001; +imm32 r1, 0x70010001; +imm32 r2, 0x70020002; +imm32 r3, 0x77030010; +imm32 r4, 0x70040004; +imm32 r5, 0x70050005; +imm32 r6, 0x70060006; +imm32 r7, 0x70070007; +R0.L = R0.H << 8; +R1.L = R1.H << 9; +R2.L = R2.H << 10; +R3.L = R3.H << 11; +R4.L = R4.H << 12; +R5.L = R5.H << 13; +R6.L = R6.H << 14; +R7.L = R7.H << 15; +CHECKREG r0, 0x70010100; +CHECKREG r1, 0x70010200; +CHECKREG r2, 0x70020800; +CHECKREG r3, 0x77031800; +CHECKREG r4, 0x70044000; +CHECKREG r5, 0x7005A000; +CHECKREG r6, 0x70068000; +CHECKREG r7, 0x70078000; + +// d_hi = lshft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0xa8000000; +imm32 r1, 0xa8000001; +imm32 r2, 0xa8000002; +imm32 r3, 0xa8000003; +imm32 r4, 0xa8000004; +imm32 r5, 0xa8000005; +imm32 r6, 0xa8000006; +imm32 r7, 0xa8000007; +R0.H = R0.L << 0; +R1.H = R1.L << 1; +R2.H = R2.L << 2; +R3.H = R3.L << 3; +R4.H = R4.L << 4; +R5.H = R5.L << 5; +R6.H = R6.L << 6; +R7.H = R7.L << 7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00080002; +CHECKREG r3, 0x00180003; +CHECKREG r4, 0x00400004; +CHECKREG r5, 0x00A00005; +CHECKREG r6, 0x01800006; +CHECKREG r7, 0x03800007; + +imm32 r0, 0xf0090001; +imm32 r1, 0xf0090001; +imm32 r2, 0xf0090002; +imm32 r3, 0xf0090003; +imm32 r4, 0xf0090004; +imm32 r5, 0xf0090005; +imm32 r6, 0xf0000006; +imm32 r7, 0xf0000007; +R1.H = R0.L << 8; +R2.H = R1.L << 9; +R3.H = R2.L << 10; +R4.H = R3.L << 11; +R5.H = R4.L << 12; +R6.H = R5.L << 13; +R7.H = R6.L << 14; +R0.H = R7.L << 15; +CHECKREG r1, 0x01000001; +CHECKREG r2, 0x02000002; +CHECKREG r3, 0x08000003; +CHECKREG r4, 0x18000004; +CHECKREG r5, 0x40000005; +CHECKREG r6, 0xA0000006; +CHECKREG r7, 0x80000007; +CHECKREG r0, 0x80000001; + + +imm32 r0, 0x07000001; +imm32 r1, 0x07000001; +imm32 r2, 0x0700000f; +imm32 r3, 0x07000003; +imm32 r4, 0x07000004; +imm32 r5, 0x07000005; +imm32 r6, 0x07000006; +imm32 r7, 0x07000007; +R3.H = R0.L << 0; +R4.H = R1.L << 1; +R5.H = R2.L << 2; +R6.H = R3.L << 3; +R7.H = R4.L << 4; +R0.H = R5.L << 5; +R1.H = R6.L << 6; +R2.H = R7.L << 7; +CHECKREG r0, 0x00A00001; +CHECKREG r1, 0x01800001; +CHECKREG r2, 0x0380000F; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +CHECKREG r5, 0x003C0005; +CHECKREG r6, 0x00180006; +CHECKREG r7, 0x00400007; + +imm32 r0, 0x00000501; +imm32 r1, 0x00000501; +imm32 r2, 0x00000502; +imm32 r3, 0x00000510; +imm32 r4, 0x00000504; +imm32 r5, 0x00000505; +imm32 r6, 0x00000506; +imm32 r7, 0x00000507; +R4.H = R0.L << 8; +R5.H = R1.L << 9; +R6.H = R2.L << 10; +R7.H = R3.L << 11; +R0.H = R4.L << 12; +R1.H = R5.L << 13; +R2.H = R6.L << 14; +R3.H = R7.L << 15; +CHECKREG r0, 0x40000501; +CHECKREG r1, 0xA0000501; +CHECKREG r2, 0x80000502; +CHECKREG r3, 0x80000510; +CHECKREG r4, 0x01000504; +CHECKREG r5, 0x02000505; +CHECKREG r6, 0x08000506; +CHECKREG r7, 0x80000507; + +imm32 r0, 0x00a00800; +imm32 r1, 0x00a10800; +imm32 r2, 0x00a20800; +imm32 r3, 0x00a30800; +imm32 r4, 0x00a40800; +imm32 r5, 0x00a50800; +imm32 r6, 0x00a60800; +imm32 r7, 0x00a70800; +R5.H = R0.H << 0; +R6.H = R1.H << 1; +R7.H = R2.H << 2; +R0.H = R3.H << 3; +R1.H = R4.H << 4; +R2.H = R5.H << 5; +R3.H = R6.H << 6; +R4.H = R7.H << 7; +CHECKREG r0, 0x05180800; +CHECKREG r1, 0x0A400800; +CHECKREG r2, 0x14000800; +CHECKREG r3, 0x50800800; +CHECKREG r4, 0x44000800; +CHECKREG r5, 0x00A00800; +CHECKREG r6, 0x01420800; +CHECKREG r7, 0x02880800; + +imm32 r0, 0x0c010000; +imm32 r1, 0x0c010001; +imm32 r2, 0x0c020000; +imm32 r3, 0x0c030000; +imm32 r4, 0x0c040000; +imm32 r5, 0x0c050000; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c070000; +R6.H = R0.H << 8; +R7.H = R1.H << 9; +R0.H = R2.H << 10; +R1.H = R3.H << 11; +R2.H = R4.H << 12; +R3.H = R5.H << 13; +R4.H = R6.H << 14; +R5.H = R7.H << 15; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x18000001; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0xA0000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x01000000; +CHECKREG r7, 0x02000000; + + +imm32 r0, 0x00b10000; +imm32 r1, 0x00b10000; +imm32 r2, 0x00b2000f; +imm32 r3, 0x00b30000; +imm32 r4, 0x00b40000; +imm32 r5, 0x00b50000; +imm32 r6, 0x00b60000; +imm32 r7, 0x00b70000; +R7.L = R0.H << 0; +R0.L = R1.H << 1; +R1.L = R2.H << 2; +R2.L = R3.H << 3; +R3.L = R4.H << 4; +R4.L = R5.H << 5; +R5.L = R6.H << 6; +R6.L = R7.H << 7; +CHECKREG r0, 0x00B10162; +CHECKREG r1, 0x00B102C8; +CHECKREG r2, 0x00B20598; +CHECKREG r3, 0x00B30B40; +CHECKREG r4, 0x00B416A0; +CHECKREG r5, 0x00B52D80; +CHECKREG r6, 0x00B65B80; +CHECKREG r7, 0x00B700B1; + +imm32 r0, 0x0a010700; +imm32 r1, 0x0a010700; +imm32 r2, 0x0a020700; +imm32 r3, 0x0a030710; +imm32 r4, 0x0a040700; +imm32 r5, 0x0a050700; +imm32 r6, 0x0a060700; +imm32 r7, 0x0a070700; +R0.H = R0.H << 8; +R1.H = R1.H << 9; +R2.H = R2.H << 10; +R3.H = R3.H << 11; +R4.H = R4.H << 12; +R5.H = R5.H << 13; +R6.H = R6.H << 14; +R7.H = R7.H << 15; +CHECKREG r0, 0x01000700; +CHECKREG r1, 0x02000700; +CHECKREG r2, 0x08000700; +CHECKREG r3, 0x18000710; +CHECKREG r4, 0x40000700; +CHECKREG r5, 0xA0000700; +CHECKREG r6, 0x80000700; +CHECKREG r7, 0x80000700; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_lhalf_rn.s b/sim/testsuite/bfin/c_dsp32shiftim_lhalf_rn.s new file mode 100644 index 0000000..a14a4c3 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_lhalf_rn.s @@ -0,0 +1,424 @@ +//Original:/testcases/core/c_dsp32shiftim_lhalf_rn/c_dsp32shiftim_lhalf_rn.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : neg data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = R0.L >> 1; +R1.L = R1.L >> 2; +R2.L = R2.L >> 3; +R3.L = R3.L >> 4; +R4.L = R4.L >> 5; +R5.L = R5.L >> 6; +R6.L = R6.L >> 7; +R7.L = R7.L >> 8; +CHECKREG r0, 0x00007FFF; +CHECKREG r1, 0x00002000; +CHECKREG r2, 0x00001000; +CHECKREG r3, 0x00000800; +CHECKREG r4, 0x00000400; +CHECKREG r5, 0x00000200; +CHECKREG r6, 0x00000100; +CHECKREG r7, 0x00000080; + +imm32 r0, 0x00008001; +R1.L = -1; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = R0.L >> 9; +R1.L = R1.L >> 10; +R2.L = R2.L >> 11; +R3.L = R3.L >> 12; +R4.L = R4.L >> 13; +R5.L = R5.L >> 14; +R6.L = R6.L >> 15; +R7.L = R7.L >> 10; +CHECKREG r0, 0x00000040; +CHECKREG r1, 0x0000003F; +CHECKREG r2, 0x00000010; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000020; + + +imm32 r0, 0x30008001; +imm32 r1, 0x30008001; +R2.L = -15; +imm32 r3, 0x30008003; +imm32 r4, 0x30008004; +imm32 r5, 0x30008005; +imm32 r6, 0x30008006; +imm32 r7, 0x30008007; +R7.L = R0.L >> 1; +R6.L = R1.L >> 2; +R5.L = R2.L >> 3; +R4.L = R3.L >> 4; +R3.L = R4.L >> 5; +R2.L = R5.L >> 6; +R0.L = R7.L >> 8; +R1.L = R6.L >> 7; +CHECKREG r0, 0x30000040; +CHECKREG r1, 0x30000040; +CHECKREG r2, 0x0000007F; +CHECKREG r3, 0x30000040; +CHECKREG r4, 0x30000800; +CHECKREG r5, 0x30001FFE; +CHECKREG r6, 0x30002000; +CHECKREG r7, 0x30004000; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +R3.L = -16; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R6.L = R0.L >> 13; +R5.L = R1.L >> 13; +R4.L = R2.L >> 13; +R3.L = R3.L >> 13; +R2.L = R4.L >> 13; +R1.L = R5.L >> 13; +R0.L = R6.L >> 13; +R7.L = R7.L >> 13; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x30000007; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000004; +CHECKREG r6, 0x00000004; +CHECKREG r7, 0x00000004; + +// d_lo = lshift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = R0.H >> 1; +R1.L = R1.H >> 1; +R2.L = R2.H >> 1; +R3.L = R3.H >> 1; +R4.L = R4.H >> 1; +R5.L = R5.H >> 1; +R6.L = R6.H >> 1; +R7.L = R7.H >> 1; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x80014000; +CHECKREG r2, 0x80024001; +CHECKREG r3, 0x80034001; +CHECKREG r4, 0x80044002; +CHECKREG r5, 0x80054002; +CHECKREG r6, 0x80064003; +CHECKREG r7, 0x80074003; + +imm32 r0, 0x80010000; +R1.L = -1; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R1.L = R0.H >> 10; +R2.L = R1.H >> 11; +R3.L = R2.H >> 12; +R4.L = R3.H >> 13; +R5.L = R4.H >> 14; +R6.L = R5.H >> 15; +R0.L = R7.H >> 15; +R7.L = R6.H >> 15; +CHECKREG r0, 0x80010001; +CHECKREG r1, 0x80010020; +CHECKREG r2, 0x80020010; +CHECKREG r3, 0x80030008; +CHECKREG r4, 0x80040004; +CHECKREG r5, 0x80050002; +CHECKREG r6, 0x80060001; +CHECKREG r7, 0x80070001; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +R2.L = -15; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R2.L = R0.H >> 2; +R3.L = R1.H >> 2; +R4.L = R2.H >> 2; +R5.L = R3.H >> 2; +R6.L = R4.H >> 2; +R7.L = R5.H >> 2; +R0.L = R6.H >> 2; +R1.L = R7.H >> 2; +CHECKREG r0, 0xA0012801; +CHECKREG r1, 0xA0012801; +CHECKREG r2, 0x80022800; +CHECKREG r3, 0xA0032800; +CHECKREG r4, 0xA0042000; +CHECKREG r5, 0xA0052800; +CHECKREG r6, 0xA0062801; +CHECKREG r7, 0xA0072801; + +imm32 r0, 0xb0010001; +imm32 r1, 0xb0010001; +imm32 r2, 0xb0020002; +R3.L = -16; +imm32 r4, 0xb0040004; +imm32 r5, 0xb0050005; +imm32 r6, 0xb0060006; +imm32 r7, 0xb0070007; +R3.L = R0.H >> 13; +R4.L = R1.H >> 13; +R5.L = R2.H >> 13; +R6.L = R3.H >> 13; +R7.L = R4.H >> 13; +R0.L = R5.H >> 13; +R1.L = R6.H >> 13; +R2.L = R7.H >> 13; +CHECKREG r0, 0xB0010005; +CHECKREG r1, 0xB0010005; +CHECKREG r2, 0xB0020005; +CHECKREG r3, 0xA0030005; +CHECKREG r4, 0xB0040005; +CHECKREG r5, 0xB0050005; +CHECKREG r6, 0xB0060005; +CHECKREG r7, 0xB0070005; + +// d_hi = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = R0.L >> 14; +R1.H = R1.L >> 14; +R2.H = R2.L >> 14; +R3.H = R3.L >> 14; +R4.H = R4.L >> 14; +R5.H = R5.L >> 14; +R6.H = R6.L >> 14; +R7.H = R7.L >> 14; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +R5.L = -1; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R1.H = R0.L >> 5; +R0.H = R7.L >> 5; +R2.H = R1.L >> 5; +R3.H = R2.L >> 5; +R4.H = R3.L >> 5; +R5.H = R4.L >> 5; +R6.H = R5.L >> 5; +R7.H = R6.L >> 5; +CHECKREG r0, 0x04008001; +CHECKREG r1, 0x04008001; +CHECKREG r2, 0x04008002; +CHECKREG r3, 0x04008003; +CHECKREG r4, 0x04008004; +CHECKREG r5, 0x0400FFFF; +CHECKREG r6, 0x07FF8006; +CHECKREG r7, 0x04008007; + + +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009004; +imm32 r5, 0x00009005; +R6.L = -15; +imm32 r7, 0x00009007; +R3.H = R0.L >> 14; +R4.H = R1.L >> 14; +R5.H = R2.L >> 14; +R6.H = R3.L >> 14; +R7.H = R4.L >> 14; +R0.H = R5.L >> 14; +R1.H = R6.L >> 14; +R2.H = R7.L >> 14; +CHECKREG r0, 0x00029001; +CHECKREG r1, 0x00039001; +CHECKREG r2, 0x00029002; +CHECKREG r3, 0x00029003; +CHECKREG r4, 0x00029004; +CHECKREG r5, 0x00029005; +CHECKREG r6, 0x0002FFF1; +CHECKREG r7, 0x00029007; + +imm32 r0, 0x0000a001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000a002; +imm32 r3, 0x0000a003; +imm32 r4, 0x0000a004; +imm32 r5, 0x0000a005; +imm32 r6, 0x0000a006; +R7.L = -16; +R4.H = R0.L >> 15; +R5.H = R1.L >> 15; +R6.H = R2.L >> 15; +R7.H = R3.L >> 15; +R0.H = R4.L >> 15; +R1.H = R5.L >> 15; +R2.H = R6.L >> 15; +R3.H = R7.L >> 15; +CHECKREG r0, 0x0001A001; +CHECKREG r1, 0x0001A001; +CHECKREG r2, 0x0001A002; +CHECKREG r3, 0x0001A003; +CHECKREG r4, 0x0001A004; +CHECKREG r5, 0x0001A005; +CHECKREG r6, 0x0001A006; +CHECKREG r7, 0x0001FFF0; + +// d_lo = lshft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +R4.L = -1; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = R0.H >> 4; +R1.H = R1.H >> 4; +R2.H = R2.H >> 4; +R3.H = R3.H >> 4; +R4.H = R4.H >> 4; +R5.H = R5.H >> 4; +R6.H = R6.H >> 4; +R7.H = R7.H >> 4; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x08000000; +CHECKREG r2, 0x08000000; +CHECKREG r3, 0x08000000; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x08000000; +CHECKREG r6, 0x08000000; +CHECKREG r7, 0x08000000; + +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +R5.L = -1; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R1.H = R0.H >> 15; +R2.H = R1.H >> 15; +R3.H = R2.H >> 15; +R4.H = R3.H >> 15; +R5.H = R4.H >> 15; +R6.H = R5.H >> 15; +R0.H = R7.H >> 15; +R7.H = R6.H >> 15; +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030000; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R3.H = R0.H >> 6; +R4.H = R1.H >> 6; +R5.H = R2.H >> 6; +R6.H = R3.H >> 6; +R7.H = R4.H >> 6; +R0.H = R5.H >> 6; +R1.H = R6.H >> 6; +R2.H = R7.H >> 6; +CHECKREG r0, 0x000D0000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x03400000; +CHECKREG r4, 0x03400000; +CHECKREG r5, 0x03400000; +CHECKREG r6, 0x000DFFF1; +CHECKREG r7, 0x000D0000; + +imm32 r0, 0xe0010000; +imm32 r1, 0xe0010000; +imm32 r2, 0xe0020000; +imm32 r3, 0xe0030000; +imm32 r4, 0xe0040000; +imm32 r5, 0xe0050000; +imm32 r6, 0xe0060000; +R7.L = -16; +R4.H = R0.H >> 7; +R5.H = R1.H >> 7; +R6.H = R2.H >> 7; +R7.H = R3.H >> 7; +R0.H = R4.H >> 7; +R1.H = R5.H >> 7; +R2.H = R6.H >> 7; +R3.H = R7.H >> 7; +CHECKREG r0, 0x00030000; +CHECKREG r1, 0x00030000; +CHECKREG r2, 0x00030000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x01C00000; +CHECKREG r5, 0x01C00000; +CHECKREG r6, 0x01C00000; +CHECKREG r7, 0x01C0FFF0; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_lhalf_rp.s b/sim/testsuite/bfin/c_dsp32shiftim_lhalf_rp.s new file mode 100644 index 0000000..a26a3eb --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_lhalf_rp.s @@ -0,0 +1,421 @@ +//Original:/testcases/core/c_dsp32shiftim_lhalf_rp/c_dsp32shiftim_lhalf_rp.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x90000001; +imm32 r2, 0x90000002; +imm32 r3, 0x90000003; +imm32 r4, 0x90000004; +imm32 r5, 0x90000005; +imm32 r6, 0x90000006; +imm32 r7, 0x90000007; +R0.L = R0.L << 0; +R1.L = R1.L >> 1; +R2.L = R2.L >> 2; +R3.L = R3.L >> 3; +R4.L = R4.L >> 4; +R5.L = R5.L >> 5; +R6.L = R6.L >> 6; +R7.L = R7.L >> 7; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x90000000; +CHECKREG r2, 0x90000000; +CHECKREG r3, 0x90000000; +CHECKREG r4, 0x90000000; +CHECKREG r5, 0x90000000; +CHECKREG r6, 0x90000000; +CHECKREG r7, 0x90000000; + +imm32 r0, 0x00001001; +R1.L = -1; +imm32 r2, 0xa0002002; +imm32 r3, 0xa0003003; +imm32 r4, 0xa0004004; +imm32 r5, 0xa0005005; +imm32 r6, 0xa0006006; +imm32 r7, 0xa0007007; +R0.L = R0.L >> 1; +R1.L = R1.L >> 1; +R2.L = R2.L >> 1; +R3.L = R3.L >> 1; +R4.L = R4.L >> 1; +R5.L = R5.L >> 1; +R6.L = R6.L >> 1; +R7.L = R7.L >> 1; +CHECKREG r0, 0x00000800; +CHECKREG r1, 0x90007FFF; +CHECKREG r2, 0xA0001001; +CHECKREG r3, 0xA0001801; +CHECKREG r4, 0xA0002002; +CHECKREG r5, 0xA0002802; +CHECKREG r6, 0xA0003003; +CHECKREG r7, 0xA0003803; + + +imm32 r0, 0xb0001001; +imm32 r1, 0xb0001001; +R2.L = -15; +imm32 r3, 0xb0003003; +imm32 r4, 0xb0004004; +imm32 r5, 0xb0005005; +imm32 r6, 0xb0006006; +imm32 r7, 0xb0007007; +R0.L = R0.L >> 15; +R1.L = R1.L >> 15; +R2.L = LSHIFT R2.L BY R2.L; +R3.L = R3.L >> 15; +R4.L = R4.L >> 15; +R5.L = R5.L >> 15; +R6.L = R6.L >> 15; +R7.L = R7.L >> 15; +CHECKREG r0, 0xb0000000; +CHECKREG r1, 0xb0000000; +CHECKREG r2, 0xA0000001; +CHECKREG r3, 0xB0000000; +CHECKREG r4, 0xb0000000; +CHECKREG r5, 0xb0000000; +CHECKREG r6, 0xb0000000; +CHECKREG r7, 0xB0000000; + +imm32 r0, 0xc0001001; +imm32 r1, 0xc0001001; +imm32 r2, 0xc0002002; +R3.L = -16; +imm32 r4, 0xc0004004; +imm32 r5, 0xc0005005; +imm32 r6, 0xc0006006; +imm32 r7, 0xc0007007; +R0.L = R0.L >> 13; +R1.L = R1.L >> 13; +R2.L = R2.L >> 13; +R3.L = R3.L >> 13; +R4.L = R4.L >> 13; +R5.L = R5.L >> 13; +R6.L = R6.L >> 13; +R7.L = R7.L >> 13; +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xC0000001; +CHECKREG r3, 0xB0000007; +CHECKREG r4, 0xC0000002; +CHECKREG r5, 0xC0000002; +CHECKREG r6, 0xC0000003; +CHECKREG r7, 0xC0000003; + +// RHx by RLx +imm32 r0, 0x0000c000; +imm32 r1, 0x0001c000; +imm32 r2, 0x0002c000; +imm32 r3, 0x0003c000; +imm32 r4, 0x0004c000; +imm32 r5, 0x0005c000; +imm32 r6, 0x0006c000; +imm32 r7, 0x0007c000; +R0.L = R0.H << 0; +R1.L = R1.H << 0; +R2.L = R2.H << 0; +R3.L = R3.H << 0; +R4.L = R4.H << 0; +R5.L = R5.H << 0; +R6.L = R6.H << 0; +R7.L = R7.H << 0; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x10010000; +R1.L = -1; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = R0.H >> 1; +R1.L = R1.H >> 1; +R2.L = R2.H >> 1; +R3.L = R3.H >> 1; +R4.L = R4.H >> 1; +R5.L = R5.H >> 1; +R6.L = R6.H >> 1; +R7.L = R7.H >> 1; +CHECKREG r0, 0x10010800; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x20021001; +CHECKREG r3, 0x30031801; +CHECKREG r4, 0x40042002; +CHECKREG r5, 0x50052802; +CHECKREG r6, 0x60063003; +CHECKREG r7, 0x70073803; + + +imm32 r0, 0x1001e000; +imm32 r1, 0x1001e000; +R2.L = -15; +imm32 r3, 0x3003e000; +imm32 r4, 0x4004e000; +imm32 r5, 0x5005e000; +imm32 r6, 0x6006e000; +imm32 r7, 0x7007e000; +R0.L = R0.H >> 15; +R1.L = R1.H >> 15; +R2.L = R2.H >> 15; +R3.L = R3.H >> 15; +R4.L = R4.H >> 15; +R5.L = R5.H >> 15; +R6.L = R6.H >> 15; +R7.L = R7.H >> 15; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x1001f001; +imm32 r1, 0x1001f001; +imm32 r2, 0x2002f002; +R3.L = -16; +imm32 r4, 0x4004f004; +imm32 r5, 0x5005f005; +imm32 r6, 0x6006f006; +imm32 r7, 0x7007f007; +R0.L = R0.H >> 13; +R1.L = R1.H >> 13; +R2.L = R2.H >> 13; +R3.L = R3.H >> 13; +R4.L = R4.H >> 13; +R5.L = R5.H >> 13; +R6.L = R6.H >> 13; +R7.L = R7.H >> 13; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020001; +CHECKREG r3, 0x30030001; +CHECKREG r4, 0x40040002; +CHECKREG r5, 0x50050002; +CHECKREG r6, 0x60060003; +CHECKREG r7, 0x70070003; + +// RLx by RLx +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r2, 0x00001002; +imm32 r3, 0x00001003; +imm32 r4, 0x00001000; +imm32 r5, 0x00001005; +imm32 r6, 0x00001006; +imm32 r7, 0x00001007; +R0.H = R0.L >> 14; +R1.H = R1.L >> 14; +R2.H = R2.L >> 14; +R3.H = R3.L >> 14; +R4.H = R4.L >> 14; +R5.H = R5.L >> 14; +R6.H = R6.L >> 14; +R7.H = R7.L >> 14; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00001001; +CHECKREG r2, 0x00001002; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00001005; +CHECKREG r6, 0x00001006; +CHECKREG r7, 0x00001007; + +imm32 r0, 0x00002001; +imm32 r1, 0x00002001; +imm32 r2, 0x00002002; +imm32 r3, 0x00002003; +imm32 r4, 0x00002004; +R5.L = -1; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = R0.L >> 5; +R1.H = R1.L >> 5; +R2.H = R2.L >> 5; +R3.H = R3.L >> 5; +R4.H = R4.L >> 5; +R5.H = R5.L >> 5; +R6.H = R6.L >> 5; +R7.H = R7.L >> 5; +CHECKREG r0, 0x01002001; +CHECKREG r1, 0x01002001; +CHECKREG r2, 0x01002002; +CHECKREG r3, 0x01002003; +CHECKREG r4, 0x01002004; +CHECKREG r5, 0x07FFFFFF; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + + +imm32 r0, 0x30001001; +imm32 r1, 0x30001001; +imm32 r1, 0x30002002; +imm32 r3, 0x30003003; +imm32 r4, 0x30004004; +imm32 r5, 0x30005005; +R6.L = -15; +imm32 r7, 0x00007007; +R0.H = R0.L >> 15; +R1.H = R1.L >> 15; +R2.H = R2.L >> 15; +R3.H = R3.L >> 15; +R4.H = R4.L >> 15; +R5.H = R5.L >> 15; +R6.H = R6.L >> 15; +R7.H = R7.L >> 15; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002002; +CHECKREG r2, 0x00002002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +CHECKREG r6, 0x0001FFF1; +CHECKREG r7, 0x00007007; + +imm32 r0, 0x40001001; +imm32 r1, 0x40002001; +imm32 r2, 0x40002002; +imm32 r3, 0x40003003; +imm32 r4, 0x40004004; +imm32 r5, 0x40005005; +imm32 r6, 0x40006006; +R7.L = -16; +R0.H = R0.L >> 7; +R1.H = R1.L >> 7; +R2.H = R2.L >> 7; +R3.H = R3.L >> 7; +R4.H = R4.L >> 7; +R5.H = R5.L >> 7; +R6.H = R6.L >> 7; +R7.H = R7.L >> 7; +CHECKREG r0, 0x00201001; +CHECKREG r1, 0x00402001; +CHECKREG r2, 0x00402002; +CHECKREG r3, 0x00603003; +CHECKREG r4, 0x00804004; +CHECKREG r5, 0x00A05005; +CHECKREG r6, 0x00C06006; +CHECKREG r7, 0x01FFFFF0; + +// RHx by RLx +imm32 r0, 0x50010000; +imm32 r1, 0x50010000; +imm32 r2, 0x50020000; +imm32 r3, 0x50030000; +R4.L = -1; +imm32 r5, 0x50050000; +imm32 r6, 0x50060000; +imm32 r7, 0x50070000; +R0.H = R0.H >> 1; +R1.H = R1.H >> 1; +R2.H = R2.H >> 1; +R3.H = R3.H >> 1; +R4.H = R4.H >> 1; +R5.H = R5.H >> 1; +R6.H = R6.H >> 1; +R7.H = R7.H >> 1; +CHECKREG r0, 0x28000000; +CHECKREG r1, 0x28000000; +CHECKREG r2, 0x28010000; +CHECKREG r3, 0x28010000; +CHECKREG r4, 0x0040FFFF; +CHECKREG r5, 0x28020000; +CHECKREG r6, 0x28030000; +CHECKREG r7, 0x28030000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +R5.L = -1; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.H = R0.H >> 5; +R1.H = R1.H >> 5; +R2.H = R2.H >> 5; +R3.H = R3.H >> 5; +R4.H = R4.H >> 5; +R5.H = R5.H >> 5; +R6.H = R6.H >> 5; +R7.H = R7.H >> 5; +CHECKREG r0, 0x00800000; +CHECKREG r1, 0x00800000; +CHECKREG r2, 0x01000000; +CHECKREG r3, 0x01800000; +CHECKREG r4, 0x02000000; +CHECKREG r5, 0x0140FFFF; +CHECKREG r6, 0x03000000; +CHECKREG r7, 0x03800000; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +R6.L = -15; +imm32 r7, 0x70070000; +R0.L = R0.H >> 6; +R1.L = R1.H >> 6; +R2.L = R2.H >> 6; +R3.L = R3.H >> 6; +R4.L = R4.H >> 6; +R5.L = R5.H >> 6; +R6.L = R6.H >> 6; +R7.L = R7.H >> 6; +CHECKREG r0, 0x10010040; +CHECKREG r1, 0x10010040; +CHECKREG r2, 0x20020080; +CHECKREG r3, 0x300300C0; +CHECKREG r4, 0x40040100; +CHECKREG r5, 0x50050140; +CHECKREG r6, 0x0300000C; +CHECKREG r7, 0x700701C0; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r2, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +R7.L = -16; +R0.H = R0.H >> 15; +R1.H = R1.H >> 15; +R2.H = R2.H >> 15; +R3.H = R3.H >> 15; +R4.H = R4.H >> 15; +R5.H = R5.H >> 15; +R6.H = R6.H >> 15; +R7.H = R7.H >> 15; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x000000C0; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x0000FFF0; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_lhh.s b/sim/testsuite/bfin/c_dsp32shiftim_lhh.s new file mode 100644 index 0000000..e129dca --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_lhh.s @@ -0,0 +1,65 @@ +//Original:/testcases/core/c_dsp32shiftim_lhh/c_dsp32shiftim_lhh.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm lshift: lshift / lshift + + + +imm32 r0, 0x01230abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0 = R0 << 0 (V); +R1 = R1 << 3 (V); +R2 = R2 << 5 (V); +R3 = R3 << 8 (V); +R4 = R4 << 9 (V); +R5 = R5 << 15 (V); +R6 = R6 << 7 (V); +R7 = R7 << 13 (V); +CHECKREG r0, 0x01230ABC; +CHECKREG r1, 0x91A0B3C0; +CHECKREG r2, 0x68A0F120; +CHECKREG r3, 0x56009A00; +CHECKREG r4, 0xCE005600; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xC480E680; +CHECKREG r7, 0x4000C000; + +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7 = R0 >> 11 (V); +R0 = R1 >> 8 (V); +R1 = R2 >> 14 (V); +R2 = R3 >> 15 (V); +R3 = R4 >> 10 (V); +R4 = R5 >> 2 (V); +R5 = R6 >> 9 (V); +R6 = R7 >> 6 (V); +CHECKREG r0, 0x00120056; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00110022; +CHECKREG r4, 0x159E26AF; +CHECKREG r5, 0x00330055; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + + + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_lmix.s b/sim/testsuite/bfin/c_dsp32shiftim_lmix.s new file mode 100644 index 0000000..82845ff --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_lmix.s @@ -0,0 +1,138 @@ +//Original:/testcases/core/c_dsp32shiftim_lmix/c_dsp32shiftim_lmix.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm lshift: mix + + + + +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + + +// Lshift (Logical ) +// Lshift : positive data, count (+)=left (half reg) +imm32 r0, 0x00010001; +imm32 r1, 1; +imm32 r2, 0x00020002; +imm32 r3, 2; +R4.H = R0.H << 1; +R4.L = R0.L << 1; /* r4 = 0x00020002 */ +R5.H = R2.H << 2; +R5.L = R2.L << 2; /* r5 = 0x00080008 */ +R6 = R0 << 1 (V); /* r6 = 0x00020002 */ +R7 = R2 << 2 (V); /* r7 = 0x00080008 */ +CHECKREG r4, 0x00020002; +CHECKREG r5, 0x00080008; +CHECKREG r6, 0x00020002; +CHECKREG r7, 0x00080008; + +// Lshift : (full reg) +imm32 r1, 3; +imm32 r3, 4; +R6 = R0 << 3; /* r6 = 0x00080010 */ +R7 = R2 << 4; +CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ +CHECKREG r7, 0x00200020; + +A0 = 0; +A0.L = R0.L; +A0.H = R0.H; +A0 = A0 << 3; /* a0 = 0x00080008 */ +R5 = A0.w; /* r5 = 0x00080008 */ +CHECKREG r5, 0x00080008; + +imm32 r4, 0x30000003; +imm32 r1, 1; +R5 = R4 << 1; /* r5 = 0x60000006 */ +imm32 r1, 2; +R6 = R4 << 2; /* r6 = 0xc000000c like LSHIFT */ +CHECKREG r5, 0x60000006; +CHECKREG r6, 0xc000000c; + + +// lshift : count (-)=right (half reg) +imm32 r0, 0x10001000; +imm32 r1, -1; +imm32 r2, 0x10001000; +imm32 r3, -2; +R4.H = R0.H >> 1; +R4.L = R0.L >> 1; /* r4 = 0x08000800 */ +R5.H = R2.H >> 2; +R5.L = R2.L >> 2; /* r4 = 0x04000400 */ +R6 = R0 >> 1 (V); /* r4 = 0x08000800 */ +R7 = R2 >> 2 (V); /* r4 = 0x04000400 */ +CHECKREG r4, 0x08000800; +CHECKREG r5, 0x04000400; +CHECKREG r6, 0x08000800; +CHECKREG r7, 0x04000400; + +// lshift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = R0 >> 3; /* r6 = 0x02000200 */ +R7 = R2 >> 4; /* r7 = 0x01000100 */ +CHECKREG r6, 0x02000200; +CHECKREG r7, 0x01000100; + +// NEGATIVE +// lshift : NEGATIVE data, count (+)=left (half reg) +imm32 r0, 0xc00f800f; +imm32 r1, 1; +imm32 r2, 0xe00fe00f; +imm32 r3, 2; +R4.H = R0.H << 1; +R4.L = R0.L << 1; /* r4 = 0x801e001e */ +R5.H = R2.H << 2; +R5.L = R2.L << 2; /* r4 = 0x803c803c */ +CHECKREG r4, 0x801e001e; +CHECKREG r5, 0x803c803c; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +imm32 r1, 4; +imm32 r3, 5; +R6 = R0 << 4; /* r6 = 0x80fe00f0 */ +R7 = R2 << 5; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xf80fe00f; +imm32 r2, 0xfc0fe00f; +R6 = R0 << 4; /* r6 = 0x80fe00f0 */ +R7 = R2 << 5; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + + + +// lshift : NEGATIVE data, count (-)=right (half reg) Working ok +imm32 r0, 0x80f080f0; +imm32 r1, -1; +imm32 r2, 0x80f080f0; +imm32 r3, -2; +R4.H = R0.H >> 1; +R4.L = R0.L >> 1; /* r4 = 0x40784078 */ +R5.H = R2.H >> 2; +R5.L = R2.L >> 2; /* r4 = 0x203c203c */ +CHECKREG r4, 0x40784078; +CHECKREG r5, 0x203c203c; +R6 = R0 >> 1 (V); /* r6 = 0x40784078 */ +R7 = R2 >> 2 (V); /* r7 = 0x203c203c */ +CHECKREG r6, 0x40784078; +CHECKREG r7, 0x203c203c; + +imm32 r1, -3; +imm32 r3, -4; +R6 = R0 >> 3; /* r6 = 0x101e101e */ +R7 = R2 >> 4; /* r7 = 0x080f080f */ +CHECKREG r6, 0x101e101e; +CHECKREG r7, 0x080f080f; + +pass diff --git a/sim/testsuite/bfin/c_dsp32shiftim_rot.s b/sim/testsuite/bfin/c_dsp32shiftim_rot.s new file mode 100644 index 0000000..0b47eda --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shiftim_rot.s @@ -0,0 +1,62 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_rot/c_dsp32shiftim_rot.dsp +// Spec Reference: dsp32shiftimm rot: +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + + imm32 r0, 0xa1230001; + imm32 r1, 0x1b345678; + imm32 r2, 0x23c56789; + imm32 r3, 0x34d6789a; + imm32 r4, 0x85a789ab; + imm32 r5, 0x967c9abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb8912cde; + R0 = ROT R0 BY 1; + R1 = ROT R1 BY 5; + R2 = ROT R2 BY 9; + R3 = ROT R3 BY 8; + R4 = ROT R4 BY 24; + R5 = ROT R5 BY 31; + R6 = ROT R6 BY 14; + R7 = ROT R7 BY 25; + CHECKREG r0, 0x42460002; + CHECKREG r1, 0x668ACF11; + CHECKREG r2, 0x8ACF1323; + CHECKREG r3, 0xD6789A9A; + CHECKREG r4, 0xAB42D3C4; + CHECKREG r5, 0x659F26AF; + CHECKREG r6, 0x6AF354F1; + CHECKREG r7, 0xBCB8912C; + + imm32 r0, 0xa1230001; + imm32 r1, 0x1b345678; + imm32 r2, 0x23c56789; + imm32 r3, 0x34d6789a; + imm32 r4, 0x85a789ab; + imm32 r5, 0x967c9abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb8912cde; + R6 = ROT R0 BY -3; + R7 = ROT R1 BY -9; + R0 = ROT R2 BY -8; + R1 = ROT R3 BY -7; + R2 = ROT R4 BY -15; + R3 = ROT R5 BY -24; + R4 = ROT R6 BY -31; + R5 = ROT R7 BY -22; + CHECKREG r0, 0x1223C567; + CHECKREG r1, 0x6A69ACF1; + CHECKREG r2, 0x26AD0B4F; + CHECKREG r3, 0xF9357896; + CHECKREG r4, 0xD0918000; + CHECKREG r5, 0x6CD15DE0; + CHECKREG r6, 0x74246000; + CHECKREG r7, 0x780D9A2B; + + pass diff --git a/sim/testsuite/bfin/c_dspldst_ld_dr_i.s b/sim/testsuite/bfin/c_dspldst_ld_dr_i.s new file mode 100644 index 0000000..02743cc --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_ld_dr_i.s @@ -0,0 +1,168 @@ +//Original:/testcases/core/c_dspldst_ld_dr_i/c_dspldst_ld_dr_i.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: c_dspldst ld_dr_i + + +// set all regs + + INIT_R_REGS 0; + +// initial values + loadsym I0, DATA1 + loadsym I1, DATA2 + loadsym I2, DATA3 + loadsym I3, DATA4 + + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x00010203; + CHECKREG r5, 0x20212223; + CHECKREG r6, 0x40414243; + CHECKREG r7, 0x60616263; + R1 = [ I0 ]; + R2 = [ I1 ]; + R3 = [ I2 ]; + R4 = [ I3 ]; + R5 = [ I0 ]; + R6 = [ I1 ]; + R7 = [ I2 ]; + R0 = [ I3 ]; + CHECKREG r0, 0x60616263; + CHECKREG r1, 0x00010203; + CHECKREG r2, 0x20212223; + CHECKREG r3, 0x40414243; + CHECKREG r4, 0x60616263; + CHECKREG r5, 0x00010203; + CHECKREG r6, 0x20212223; + CHECKREG r7, 0x40414243; + R2 = [ I0 ]; + R3 = [ I1 ]; + R4 = [ I2 ]; + R5 = [ I3 ]; + R6 = [ I0 ]; + R7 = [ I1 ]; + R0 = [ I2 ]; + R1 = [ I3 ]; + CHECKREG r0, 0x40414243; + CHECKREG r1, 0x60616263; + CHECKREG r2, 0x00010203; + CHECKREG r3, 0x20212223; + CHECKREG r4, 0x40414243; + CHECKREG r5, 0x60616263; + CHECKREG r6, 0x00010203; + CHECKREG r7, 0x20212223; + + R3 = [ I0 ]; + R4 = [ I1 ]; + R5 = [ I2 ]; + R6 = [ I3 ]; + R7 = [ I0 ]; + R0 = [ I1 ]; + R1 = [ I2 ]; + R2 = [ I3 ]; + CHECKREG r0, 0x20212223; + CHECKREG r1, 0x40414243; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x00010203; + CHECKREG r4, 0x20212223; + CHECKREG r5, 0x40414243; + CHECKREG r6, 0x60616263; + CHECKREG r7, 0x00010203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_ld_dr_ipp.s b/sim/testsuite/bfin/c_dspldst_ld_dr_ipp.s new file mode 100644 index 0000000..d94dfc2 --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_ld_dr_ipp.s @@ -0,0 +1,348 @@ +//Original:/testcases/core/c_dspldst_ld_dr_ipp/c_dspldst_ld_dr_ipp.dsp +// Spec Reference: c_dspldst ld_dr_i++/-- +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x04050607; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x44454647; + CHECKREG r7, 0x64656667; + R1 = [ I0 ++ ]; + R2 = [ I1 ++ ]; + R3 = [ I2 ++ ]; + R4 = [ I3 ++ ]; + R5 = [ I0 ++ ]; + R6 = [ I1 ++ ]; + R7 = [ I2 ++ ]; + R0 = [ I3 ++ ]; + CHECKREG r0, 0x6C6D6E6F; + CHECKREG r1, 0x08090A0B; + CHECKREG r2, 0x28292A2B; + CHECKREG r3, 0x48494A4B; + CHECKREG r4, 0x68696A6B; + CHECKREG r5, 0x0C0D0E0F; + CHECKREG r6, 0x2C2D2E2F; + CHECKREG r7, 0x4C4D4E4F; + R2 = [ I0 ++ ]; + R3 = [ I1 ++ ]; + R4 = [ I2 ++ ]; + R5 = [ I3 ++ ]; + R6 = [ I0 ++ ]; + R7 = [ I1 ++ ]; + R0 = [ I2 ++ ]; + R1 = [ I3 ++ ]; + CHECKREG r0, 0x54555657; + CHECKREG r1, 0x74757677; + CHECKREG r2, 0x10111213; + CHECKREG r3, 0x30313233; + CHECKREG r4, 0x50515253; + CHECKREG r5, 0x70717273; + CHECKREG r6, 0x14151617; + CHECKREG r7, 0x34353637; + + R3 = [ I0 ++ ]; + R4 = [ I1 ++ ]; + R5 = [ I2 ++ ]; + R6 = [ I3 ++ ]; + R7 = [ I0 ++ ]; + R0 = [ I1 ++ ]; + R1 = [ I2 ++ ]; + R2 = [ I3 ++ ]; + CHECKREG r0, 0x3C3D3E3F; + CHECKREG r1, 0xC5C6C7C8; + CHECKREG r2, 0x7C7D7E7F; + CHECKREG r3, 0x18191A1B; + CHECKREG r4, 0x38393A3B; + CHECKREG r5, 0x58595A5B; + CHECKREG r6, 0x78797A7B; + CHECKREG r7, 0x1C1D1E1F; + +// reverse to minus mninus i-- + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0x11223344; + CHECKREG r1, 0x91929394; + CHECKREG r2, 0xC9CACBCD; + CHECKREG r3, 0xEBECEDEE; + CHECKREG r4, 0x1C1D1E1F; + CHECKREG r5, 0x3C3D3E3F; + CHECKREG r6, 0xC5C6C7C8; + CHECKREG r7, 0x7C7D7E7F; + R1 = [ I0 -- ]; + R2 = [ I1 -- ]; + R3 = [ I2 -- ]; + R4 = [ I3 -- ]; + R5 = [ I0 -- ]; + R6 = [ I1 -- ]; + R7 = [ I2 -- ]; + R0 = [ I3 -- ]; + CHECKREG r0, 0x74757677; + CHECKREG r1, 0x18191A1B; + CHECKREG r2, 0x38393A3B; + CHECKREG r3, 0x58595A5B; + CHECKREG r4, 0x78797A7B; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x34353637; + CHECKREG r7, 0x54555657; + R2 = [ I0 -- ]; + R3 = [ I1 -- ]; + R4 = [ I2 -- ]; + R5 = [ I3 -- ]; + R6 = [ I0 -- ]; + R7 = [ I1 -- ]; + R0 = [ I2 -- ]; + R1 = [ I3 -- ]; + CHECKREG r0, 0x4C4D4E4F; + CHECKREG r1, 0x6C6D6E6F; + CHECKREG r2, 0x10111213; + CHECKREG r3, 0x30313233; + CHECKREG r4, 0x50515253; + CHECKREG r5, 0x70717273; + CHECKREG r6, 0x0C0D0E0F; + CHECKREG r7, 0x2C2D2E2F; + + R3 = [ I0 -- ]; + R4 = [ I1 -- ]; + R5 = [ I2 -- ]; + R6 = [ I3 -- ]; + R7 = [ I0 -- ]; + R0 = [ I1 -- ]; + R1 = [ I2 -- ]; + R2 = [ I3 -- ]; + CHECKREG r0, 0x24252627; + CHECKREG r1, 0x44454647; + CHECKREG r2, 0x64656667; + CHECKREG r3, 0x08090A0B; + CHECKREG r4, 0x28292A2B; + CHECKREG r5, 0x48494A4B; + CHECKREG r6, 0x68696A6B; + CHECKREG r7, 0x04050607; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xBC0DBE26 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_ld_dr_ippm.s b/sim/testsuite/bfin/c_dspldst_ld_dr_ippm.s new file mode 100644 index 0000000..abdc823 --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_ld_dr_ippm.s @@ -0,0 +1,328 @@ +//Original:/testcases/core/c_dspldst_ld_dr_ippm/c_dspldst_ld_dr_ippm.dsp +// Spec Reference: c_dspldst ld_dr_i++m +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + M0 = 0 (X); + M1 = 0x4 (X); + M2 = 0x0 (X); + M3 = 0x4 (X); + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + R0 = [ I0 ++ M0 ]; + R1 = [ I1 ++ M1 ]; + R2 = [ I2 ++ M2 ]; + R3 = [ I3 ++ M3 ]; + R4 = [ I0 ++ M1 ]; + R5 = [ I1 ++ M2 ]; + R6 = [ I2 ++ M3 ]; + R7 = [ I3 ++ M0 ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x00010203; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x40414243; + CHECKREG r7, 0x64656667; + R1 = [ I0 ++ M2 ]; + R2 = [ I1 ++ M3 ]; + R3 = [ I2 ++ M0 ]; + R4 = [ I3 ++ M1 ]; + R5 = [ I0 ++ M3 ]; + R6 = [ I1 ++ M0 ]; + R7 = [ I2 ++ M1 ]; + R0 = [ I3 ++ M2 ]; + CHECKREG r0, 0x68696A6B; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x24252627; + CHECKREG r3, 0x44454647; + CHECKREG r4, 0x64656667; + CHECKREG r5, 0x04050607; + CHECKREG r6, 0x28292A2B; + CHECKREG r7, 0x44454647; + + M0 = 4 (X); + M1 = 0x0 (X); + M2 = 0x4 (X); + M3 = 0x0 (X); + R2 = [ I0 ++ M0 ]; + R3 = [ I1 ++ M1 ]; + R4 = [ I2 ++ M2 ]; + R5 = [ I3 ++ M3 ]; + R6 = [ I0 ++ M1 ]; + R7 = [ I1 ++ M2 ]; + R0 = [ I2 ++ M3 ]; + R1 = [ I3 ++ M0 ]; + CHECKREG r0, 0x4C4D4E4F; + CHECKREG r1, 0x68696A6B; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x28292A2B; + CHECKREG r4, 0x48494A4B; + CHECKREG r5, 0x68696A6B; + CHECKREG r6, 0x0C0D0E0F; + CHECKREG r7, 0x28292A2B; + + R3 = [ I0 ++ M2 ]; + R4 = [ I1 ++ M3 ]; + R5 = [ I2 ++ M0 ]; + R6 = [ I3 ++ M1 ]; + R7 = [ I0 ++ M3 ]; + R0 = [ I1 ++ M0 ]; + R1 = [ I2 ++ M1 ]; + R2 = [ I3 ++ M2 ]; + CHECKREG r0, 0x2C2D2E2F; + CHECKREG r1, 0x50515253; + CHECKREG r2, 0x6C6D6E6F; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x2C2D2E2F; + CHECKREG r5, 0x4C4D4E4F; + CHECKREG r6, 0x6C6D6E6F; + CHECKREG r7, 0x10111213; + + R5 = [ I0 ++ M2 ]; + R6 = [ I1 ++ M3 ]; + R7 = [ I2 ++ M0 ]; + R0 = [ I3 ++ M1 ]; + R1 = [ I0 ++ M3 ]; + R2 = [ I1 ++ M0 ]; + R3 = [ I2 ++ M1 ]; + R4 = [ I3 ++ M2 ]; + CHECKREG r0, 0x70717273; + CHECKREG r1, 0x14151617; + CHECKREG r2, 0x30313233; + CHECKREG r3, 0x54555657; + CHECKREG r4, 0x70717273; + CHECKREG r5, 0x10111213; + CHECKREG r6, 0x30313233; + CHECKREG r7, 0x50515253; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_ld_drhi_i.s b/sim/testsuite/bfin/c_dspldst_ld_drhi_i.s new file mode 100644 index 0000000..3ada175 --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_ld_drhi_i.s @@ -0,0 +1,168 @@ +//Original:/testcases/core/c_dspldst_ld_drhi_i/c_dspldst_ld_drhi_i.dsp +// Spec Reference: c_dspldst ld_drhi_i +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + + INIT_R_REGS 0; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + +// Load upper half of Dregs + R0.H = W [ I0 ]; + R1.H = W [ I1 ]; + R2.H = W [ I2 ]; + R3.H = W [ I3 ]; + R4.H = W [ I0 ]; + R5.H = W [ I1 ]; + R6.H = W [ I2 ]; + R7.H = W [ I3 ]; + CHECKREG r0, 0x02030000; + CHECKREG r1, 0x22230000; + CHECKREG r2, 0x42430000; + CHECKREG r3, 0x62630000; + CHECKREG r4, 0x02030000; + CHECKREG r5, 0x22230000; + CHECKREG r6, 0x42430000; + CHECKREG r7, 0x62630000; + + R1.H = W [ I0 ]; + R2.H = W [ I1 ]; + R3.H = W [ I2 ]; + R4.H = W [ I3 ]; + R5.H = W [ I0 ]; + R6.H = W [ I1 ]; + R7.H = W [ I2 ]; + R0.H = W [ I3 ]; + CHECKREG r0, 0x62630000; + CHECKREG r1, 0x02030000; + CHECKREG r2, 0x22230000; + CHECKREG r3, 0x42430000; + CHECKREG r4, 0x62630000; + CHECKREG r5, 0x02030000; + CHECKREG r6, 0x22230000; + CHECKREG r7, 0x42430000; + + R2.H = W [ I0 ]; + R3.H = W [ I1 ]; + R4.H = W [ I2 ]; + R5.H = W [ I3 ]; + R6.H = W [ I0 ]; + R7.H = W [ I1 ]; + R0.H = W [ I2 ]; + R1.H = W [ I3 ]; + CHECKREG r0, 0x42430000; + CHECKREG r1, 0x62630000; + CHECKREG r2, 0x02030000; + CHECKREG r3, 0x22230000; + CHECKREG r4, 0x42430000; + CHECKREG r5, 0x62630000; + CHECKREG r6, 0x02030000; + CHECKREG r7, 0x22230000; + + R3.H = W [ I0 ]; + R4.H = W [ I1 ]; + R5.H = W [ I2 ]; + R6.H = W [ I3 ]; + R7.H = W [ I0 ]; + R0.H = W [ I1 ]; + R1.H = W [ I2 ]; + R2.H = W [ I3 ]; + + CHECKREG r0, 0x22230000; + CHECKREG r1, 0x42430000; + CHECKREG r2, 0x62630000; + CHECKREG r3, 0x02030000; + CHECKREG r4, 0x22230000; + CHECKREG r5, 0x42430000; + CHECKREG r6, 0x62630000; + CHECKREG r7, 0x02030000; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_ld_drhi_ipp.s b/sim/testsuite/bfin/c_dspldst_ld_drhi_ipp.s new file mode 100644 index 0000000..e4531af --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_ld_drhi_ipp.s @@ -0,0 +1,364 @@ +//Original:/testcases/core/c_dspldst_ld_drhi_ipp/c_dspldst_ld_drhi_ipp.dsp +// Spec Reference: c_dspldst ld_drhi_i++/-- +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + + INIT_R_REGS 0; + +// initial values +//i0=0x3000; +//i1=0x4000; +//i2=0x5000; +//i3=0x6000; + loadsym I0, DATA_ADDR_3; + loadsym I1, DATA_ADDR_4; + loadsym I2, DATA_ADDR_5; + loadsym I3, DATA_ADDR_6; + +// Load Upper half of Dregs + R0.H = W [ I0 ++ ]; + R1.H = W [ I1 ++ ]; + R2.H = W [ I2 ++ ]; + R3.H = W [ I3 ++ ]; + R4.H = W [ I0 ++ ]; + R5.H = W [ I1 ++ ]; + R6.H = W [ I2 ++ ]; + R7.H = W [ I3 ++ ]; + CHECKREG r0, 0x02030000; + CHECKREG r1, 0x22230000; + CHECKREG r2, 0x42430000; + CHECKREG r3, 0x62630000; + CHECKREG r4, 0x00010000; + CHECKREG r5, 0x20210000; + CHECKREG r6, 0x40410000; + CHECKREG r7, 0x60610000; + + R1.H = W [ I0 ++ ]; + R2.H = W [ I1 ++ ]; + R3.H = W [ I2 ++ ]; + R4.H = W [ I3 ++ ]; + R5.H = W [ I0 ++ ]; + R6.H = W [ I1 ++ ]; + R7.H = W [ I2 ++ ]; + R0.H = W [ I3 ++ ]; + CHECKREG r0, 0x64650000; + CHECKREG r1, 0x06070000; + CHECKREG r2, 0x26270000; + CHECKREG r3, 0x46470000; + CHECKREG r4, 0x66670000; + CHECKREG r5, 0x04050000; + CHECKREG r6, 0x24250000; + CHECKREG r7, 0x44450000; + + R2.H = W [ I0 ++ ]; + R3.H = W [ I1 ++ ]; + R4.H = W [ I2 ++ ]; + R5.H = W [ I3 ++ ]; + R6.H = W [ I0 ++ ]; + R7.H = W [ I1 ++ ]; + R0.H = W [ I2 ++ ]; + R1.H = W [ I3 ++ ]; + CHECKREG r0, 0x48490000; + CHECKREG r1, 0x68690000; + CHECKREG r2, 0x0A0B0000; + CHECKREG r3, 0x2A2B0000; + CHECKREG r4, 0x4A4B0000; + CHECKREG r5, 0x6A6B0000; + CHECKREG r6, 0x08090000; + CHECKREG r7, 0x28290000; + + R3.H = W [ I0 ++ ]; + R4.H = W [ I1 ++ ]; + R5.H = W [ I2 ++ ]; + R6.H = W [ I3 ++ ]; + R7.H = W [ I0 ++ ]; + R0.H = W [ I1 ++ ]; + R1.H = W [ I2 ++ ]; + R2.H = W [ I3 ++ ]; + + CHECKREG r0, 0x2C2D0000; + CHECKREG r1, 0x4C4D0000; + CHECKREG r2, 0x6C6D0000; + CHECKREG r3, 0x0E0F0000; + CHECKREG r4, 0x2E2F0000; + CHECKREG r5, 0x4E4F0000; + CHECKREG r6, 0x6E6F0000; + CHECKREG r7, 0x0C0D0000; + +// reverse to minus mninus i-- +// Load Upper half of Dregs + R0.H = W [ I0 -- ]; + R1.H = W [ I1 -- ]; + R2.H = W [ I2 -- ]; + R3.H = W [ I3 -- ]; + R4.H = W [ I0 -- ]; + R5.H = W [ I1 -- ]; + R6.H = W [ I2 -- ]; + R7.H = W [ I3 -- ]; + CHECKREG r0, 0x12130000; + CHECKREG r1, 0x32330000; + CHECKREG r2, 0x52530000; + CHECKREG r3, 0x72730000; + CHECKREG r4, 0x0C0D0000; + CHECKREG r5, 0x2C2D0000; + CHECKREG r6, 0x4C4D0000; + CHECKREG r7, 0x6C6D0000; + + R1.H = W [ I0 -- ]; + R2.H = W [ I1 -- ]; + R3.H = W [ I2 -- ]; + R4.H = W [ I3 -- ]; + R5.H = W [ I0 -- ]; + R6.H = W [ I1 -- ]; + R7.H = W [ I2 -- ]; + R0.H = W [ I3 -- ]; + CHECKREG r0, 0x68690000; + CHECKREG r1, 0x0E0F0000; + CHECKREG r2, 0x2E2F0000; + CHECKREG r3, 0x4E4F0000; + CHECKREG r4, 0x6E6F0000; + CHECKREG r5, 0x08090000; + CHECKREG r6, 0x28290000; + CHECKREG r7, 0x48490000; + + R2.H = W [ I0 -- ]; + R3.H = W [ I1 -- ]; + R4.H = W [ I2 -- ]; + R5.H = W [ I3 -- ]; + R6.H = W [ I0 -- ]; + R7.H = W [ I1 -- ]; + R0.H = W [ I2 -- ]; + R1.H = W [ I3 -- ]; + CHECKREG r0, 0x44450000; + CHECKREG r1, 0x64650000; + CHECKREG r2, 0x0A0B0000; + CHECKREG r3, 0x2A2B0000; + CHECKREG r4, 0x4A4B0000; + CHECKREG r5, 0x6A6B0000; + CHECKREG r6, 0x04050000; + CHECKREG r7, 0x24250000; + + R3.H = W [ I0 -- ]; + R4.H = W [ I1 -- ]; + R5.H = W [ I2 -- ]; + R6.H = W [ I3 -- ]; + R7.H = W [ I0 -- ]; + R0.H = W [ I1 -- ]; + R1.H = W [ I2 -- ]; + R2.H = W [ I3 -- ]; + + CHECKREG r0, 0x20210000; + CHECKREG r1, 0x40410000; + CHECKREG r2, 0x60610000; + CHECKREG r3, 0x06070000; + CHECKREG r4, 0x26270000; + CHECKREG r5, 0x46470000; + CHECKREG r6, 0x66670000; + CHECKREG r7, 0x00010000; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xBC0DBE26 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_ld_drlo_i.s b/sim/testsuite/bfin/c_dspldst_ld_drlo_i.s new file mode 100644 index 0000000..aec575c --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_ld_drlo_i.s @@ -0,0 +1,164 @@ +//Original:/testcases/core/c_dspldst_ld_drlo_i/c_dspldst_ld_drlo_i.dsp +// Spec Reference: c_dspldst ld_drlo_i +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + +// Load Lower half of Dregs + R0.L = W [ I0 ]; + R1.L = W [ I1 ]; + R2.L = W [ I2 ]; + R3.L = W [ I3 ]; + R4.L = W [ I0 ]; + R5.L = W [ I1 ]; + R6.L = W [ I2 ]; + R7.L = W [ I3 ]; + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00000203; + CHECKREG r5, 0x00002223; + CHECKREG r6, 0x00004243; + CHECKREG r7, 0x00006263; + + R1.L = W [ I0 ]; + R2.L = W [ I1 ]; + R3.L = W [ I2 ]; + R4.L = W [ I3 ]; + R5.L = W [ I0 ]; + R6.L = W [ I1 ]; + R7.L = W [ I2 ]; + R0.L = W [ I3 ]; + CHECKREG r0, 0x00006263; + CHECKREG r1, 0x00000203; + CHECKREG r2, 0x00002223; + CHECKREG r3, 0x00004243; + CHECKREG r4, 0x00006263; + CHECKREG r5, 0x00000203; + CHECKREG r6, 0x00002223; + CHECKREG r7, 0x00004243; + + R2.L = W [ I0 ]; + R3.L = W [ I1 ]; + R4.L = W [ I2 ]; + R5.L = W [ I3 ]; + R6.L = W [ I0 ]; + R7.L = W [ I1 ]; + R0.L = W [ I2 ]; + R1.L = W [ I3 ]; + CHECKREG r0, 0x00004243; + CHECKREG r1, 0x00006263; + CHECKREG r2, 0x00000203; + CHECKREG r3, 0x00002223; + CHECKREG r4, 0x00004243; + CHECKREG r5, 0x00006263; + CHECKREG r6, 0x00000203; + CHECKREG r7, 0x00002223; + + R3.L = W [ I0 ]; + R4.L = W [ I1 ]; + R5.L = W [ I2 ]; + R6.L = W [ I3 ]; + R7.L = W [ I0 ]; + R0.L = W [ I1 ]; + R1.L = W [ I2 ]; + R2.L = W [ I3 ]; + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0x00000203; + CHECKREG r4, 0x00002223; + CHECKREG r5, 0x00004243; + CHECKREG r6, 0x00006263; + CHECKREG r7, 0x00000203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_ld_drlo_ipp.s b/sim/testsuite/bfin/c_dspldst_ld_drlo_ipp.s new file mode 100644 index 0000000..d47b6b8 --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_ld_drlo_ipp.s @@ -0,0 +1,355 @@ +//Original:/testcases/core/c_dspldst_ld_drlo_ipp/c_dspldst_ld_drlo_ipp.dsp +// Spec Reference: c_dspldst ld_drlo_i++/-- +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + +// Load Lower half of Dregs + R0.L = W [ I0 ++ ]; + R1.L = W [ I1 ++ ]; + R2.L = W [ I2 ++ ]; + R3.L = W [ I3 ++ ]; + R4.L = W [ I0 ++ ]; + R5.L = W [ I1 ++ ]; + R6.L = W [ I2 ++ ]; + R7.L = W [ I3 ++ ]; + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00000001; + CHECKREG r5, 0x00002021; + CHECKREG r6, 0x00004041; + CHECKREG r7, 0x00006061; + + R1.L = W [ I0 ++ ]; + R2.L = W [ I1 ++ ]; + R3.L = W [ I2 ++ ]; + R4.L = W [ I3 ++ ]; + R5.L = W [ I0 ++ ]; + R6.L = W [ I1 ++ ]; + R7.L = W [ I2 ++ ]; + R0.L = W [ I3 ++ ]; + CHECKREG r0, 0x00006465; + CHECKREG r1, 0x00000607; + CHECKREG r2, 0x00002627; + CHECKREG r3, 0x00004647; + CHECKREG r4, 0x00006667; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00004445; + + R2.L = W [ I0 ++ ]; + R3.L = W [ I1 ++ ]; + R4.L = W [ I2 ++ ]; + R5.L = W [ I3 ++ ]; + R6.L = W [ I0 ++ ]; + R7.L = W [ I1 ++ ]; + R0.L = W [ I2 ++ ]; + R1.L = W [ I3 ++ ]; + CHECKREG r0, 0x00004849; + CHECKREG r1, 0x00006869; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00002A2B; + CHECKREG r4, 0x00004A4B; + CHECKREG r5, 0x00006A6B; + CHECKREG r6, 0x00000809; + CHECKREG r7, 0x00002829; + + R3.L = W [ I0 ++ ]; + R4.L = W [ I1 ++ ]; + R5.L = W [ I2 ++ ]; + R6.L = W [ I3 ++ ]; + R7.L = W [ I0 ++ ]; + R0.L = W [ I1 ++ ]; + R1.L = W [ I2 ++ ]; + R2.L = W [ I3 ++ ]; + CHECKREG r0, 0x00002C2D; + CHECKREG r1, 0x00004C4D; + CHECKREG r2, 0x00006C6D; + CHECKREG r3, 0x00000E0F; + CHECKREG r4, 0x00002E2F; + CHECKREG r5, 0x00004E4F; + CHECKREG r6, 0x00006E6F; + CHECKREG r7, 0x00000C0D; + +// reverse to minus mninus i-- + +// Load Lower half of Dregs + R0.L = W [ I0 -- ]; + R1.L = W [ I1 -- ]; + R2.L = W [ I2 -- ]; + R3.L = W [ I3 -- ]; + R4.L = W [ I0 -- ]; + R5.L = W [ I1 -- ]; + R6.L = W [ I2 -- ]; + R7.L = W [ I3 -- ]; + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00003233; + CHECKREG r2, 0x00005253; + CHECKREG r3, 0x00007273; + CHECKREG r4, 0x00000C0D; + CHECKREG r5, 0x00002C2D; + CHECKREG r6, 0x00004C4D; + CHECKREG r7, 0x00006C6D; + + R1.L = W [ I0 -- ]; + R2.L = W [ I1 -- ]; + R3.L = W [ I2 -- ]; + R4.L = W [ I3 -- ]; + R5.L = W [ I0 -- ]; + R6.L = W [ I1 -- ]; + R7.L = W [ I2 -- ]; + R0.L = W [ I3 -- ]; + CHECKREG r0, 0x00006869; + CHECKREG r1, 0x00000E0F; + CHECKREG r2, 0x00002E2F; + CHECKREG r3, 0x00004E4F; + CHECKREG r4, 0x00006E6F; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00002829; + CHECKREG r7, 0x00004849; + + R2.L = W [ I0 -- ]; + R3.L = W [ I1 -- ]; + R4.L = W [ I2 -- ]; + R5.L = W [ I3 -- ]; + R6.L = W [ I0 -- ]; + R7.L = W [ I1 -- ]; + R0.L = W [ I2 -- ]; + R1.L = W [ I3 -- ]; + CHECKREG r0, 0x00004445; + CHECKREG r1, 0x00006465; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00002A2B; + CHECKREG r4, 0x00004A4B; + CHECKREG r5, 0x00006A6B; + CHECKREG r6, 0x00000405; + CHECKREG r7, 0x00002425; + + R3.L = W [ I0 -- ]; + R4.L = W [ I1 -- ]; + R5.L = W [ I2 -- ]; + R6.L = W [ I3 -- ]; + R7.L = W [ I0 -- ]; + R0.L = W [ I1 -- ]; + R1.L = W [ I2 -- ]; + R2.L = W [ I3 -- ]; + CHECKREG r0, 0x00002021; + CHECKREG r1, 0x00004041; + CHECKREG r2, 0x00006061; + CHECKREG r3, 0x00000607; + CHECKREG r4, 0x00002627; + CHECKREG r5, 0x00004647; + CHECKREG r6, 0x00006667; + CHECKREG r7, 0x00000001; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xBC0DBE26 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_st_dr_i.s b/sim/testsuite/bfin/c_dspldst_st_dr_i.s new file mode 100644 index 0000000..7434607 --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_st_dr_i.s @@ -0,0 +1,185 @@ +//Original:/testcases/core/c_dspldst_st_dr_i/c_dspldst_st_dr_i.dsp +// Spec Reference: c_dspldst st_dr_i +# mach: bfin + +.include "testutils.inc" + start + + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + [ I0 ] = R0; + [ I1 ] = R1; + [ I2 ] = R2; + [ I3 ] = R3; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x0a234507; + CHECKREG r5, 0x1b345618; + CHECKREG r6, 0x2c456729; + CHECKREG r7, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + [ I0 ] = R1; + [ I1 ] = R2; + [ I2 ] = R3; + [ I3 ] = R4; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x1b345618; + CHECKREG r5, 0x2c456729; + CHECKREG r6, 0x3d56783a; + CHECKREG r7, 0x4e67894b; + + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + [ I0 ] = R2; + [ I1 ] = R3; + [ I2 ] = R4; + [ I3 ] = R5; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x2c456729; + CHECKREG r5, 0x3d56783a; + CHECKREG r6, 0x4e67894b; + CHECKREG r7, 0x5f789a5c; + + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + [ I0 ] = R3; + [ I1 ] = R4; + [ I2 ] = R5; + [ I3 ] = R6; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x3d56783a; + CHECKREG r5, 0x4e67894b; + CHECKREG r6, 0x5f789a5c; + CHECKREG r7, 0x6089ab6d; + + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + [ I0 ] = R4; + [ I1 ] = R5; + [ I2 ] = R6; + [ I3 ] = R7; + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + CHECKREG r0, 0x4e67894b; + CHECKREG r1, 0x5f789a5c; + CHECKREG r2, 0x6089ab6d; + CHECKREG r3, 0x719abc7e; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_st_dr_ipp.s b/sim/testsuite/bfin/c_dspldst_st_dr_ipp.s new file mode 100644 index 0000000..87404a1 --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_st_dr_ipp.s @@ -0,0 +1,326 @@ +//Original:testcases/core/c_dspldst_st_dr_ipp/c_dspldst_st_dr_ipp.dsp +// Spec Reference: c_dspldst st_dr_ipp +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +//INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + +// initial values + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + [ I0 ++ ] = R0; + [ I1 ++ ] = R1; + [ I2 ++ ] = R2; + [ I3 ++ ] = R3; + + [ I0 ++ ] = R1; + [ I1 ++ ] = R2; + [ I2 ++ ] = R3; + [ I3 ++ ] = R4; + + [ I0 ++ ] = R3; + [ I1 ++ ] = R4; + [ I2 ++ ] = R5; + [ I3 ++ ] = R6; + + [ I0 ++ ] = R4; + [ I1 ++ ] = R5; + [ I2 ++ ] = R6; + [ I3 ++ ] = R7; + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x0a234507; + CHECKREG r1, 0x1b345618; + CHECKREG r2, 0x2c456729; + CHECKREG r3, 0x3d56783a; + CHECKREG r4, 0x1B345618; + CHECKREG r5, 0x2C456729; + CHECKREG r6, 0x3D56783A; + CHECKREG r7, 0x4E67894B; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x3D56783A; + CHECKREG r1, 0x4E67894B; + CHECKREG r2, 0x5F789A5C; + CHECKREG r3, 0x6089AB6D; + CHECKREG r4, 0x4E67894B; + CHECKREG r5, 0x5F789A5C; + CHECKREG r6, 0x6089AB6D; + CHECKREG r7, 0x719ABC7E; + +// initial values + + imm32 r0, 0xa0b2c3d4; + imm32 r1, 0x1b245618; + imm32 r2, 0x22b36729; + imm32 r3, 0xbd3c483a; + imm32 r4, 0xde64d54b; + imm32 r5, 0x5f785e6c; + imm32 r6, 0x30896bf7; + imm32 r7, 0x719ab770; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + + [ I0 -- ] = R0; + [ I1 -- ] = R1; + [ I2 -- ] = R2; + [ I3 -- ] = R3; + [ I0 -- ] = R4; + [ I1 -- ] = R5; + [ I2 -- ] = R6; + [ I3 -- ] = R7; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0xA0B2C3D4; + CHECKREG r1, 0x1B245618; + CHECKREG r2, 0x22B36729; + CHECKREG r3, 0xBD3C483A; + CHECKREG r4, 0xDE64D54B; + CHECKREG r5, 0x5F785E6C; + CHECKREG r6, 0x30896BF7; + CHECKREG r7, 0x719AB770; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_st_dr_ippm.s b/sim/testsuite/bfin/c_dspldst_st_dr_ippm.s new file mode 100644 index 0000000..9b08838 --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_st_dr_ippm.s @@ -0,0 +1,279 @@ +//Original:/testcases/core/c_dspldst_st_dr_ippm/c_dspldst_st_dr_ippm.dsp +// Spec Reference: c_dspldst st_dr_ippm +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + M0 = 4 (X); + M1 = 0x4 (X); + M2 = 0x4 (X); + M3 = 0x4 (X); + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + [ I0 ++ M0 ] = R0; + [ I1 ++ M1 ] = R1; + [ I2 ++ M2 ] = R2; + [ I3 ++ M3 ] = R3; + [ I0 ++ M1 ] = R1; + [ I1 ++ M2 ] = R2; + [ I2 ++ M3 ] = R3; + [ I3 ++ M0 ] = R4; + + [ I0 ++ M2 ] = R3; + [ I1 ++ M3 ] = R4; + [ I2 ++ M0 ] = R5; + [ I3 ++ M1 ] = R6; + [ I0 ++ M3 ] = R4; + [ I1 ++ M0 ] = R5; + [ I2 ++ M1 ] = R6; + [ I3 ++ M2 ] = R7; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + R0 = [ I0 ++ M0 ]; + R1 = [ I1 ++ M1 ]; + R2 = [ I2 ++ M2 ]; + R3 = [ I3 ++ M3 ]; + R4 = [ I0 ++ M1 ]; + R5 = [ I1 ++ M2 ]; + R6 = [ I2 ++ M3 ]; + R7 = [ I3 ++ M0 ]; + CHECKREG r0, 0x0A234507; + CHECKREG r1, 0x1B345618; + CHECKREG r2, 0x2C456729; + CHECKREG r3, 0x3D56783A; + CHECKREG r4, 0x1B345618; + CHECKREG r5, 0x2C456729; + CHECKREG r6, 0x3D56783A; + CHECKREG r7, 0x4E67894B; + R0 = [ I0 ++ M2 ]; + R1 = [ I1 ++ M3 ]; + R2 = [ I2 ++ M0 ]; + R3 = [ I3 ++ M1 ]; + R4 = [ I0 ++ M3 ]; + R5 = [ I1 ++ M0 ]; + R6 = [ I2 ++ M1 ]; + R7 = [ I3 ++ M2 ]; + CHECKREG r0, 0x3D56783A; + CHECKREG r1, 0x4E67894B; + CHECKREG r2, 0x5F789A5C; + CHECKREG r3, 0x6089AB6D; + CHECKREG r4, 0x4E67894B; + CHECKREG r5, 0x5F789A5C; + CHECKREG r6, 0x6089AB6D; + CHECKREG r7, 0x719ABC7E; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_st_drhi_i.s b/sim/testsuite/bfin/c_dspldst_st_drhi_i.s new file mode 100644 index 0000000..a5aefc8 --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_st_drhi_i.s @@ -0,0 +1,161 @@ +//Original:/testcases/core/c_dspldst_st_drhi_i/c_dspldst_st_drhi_i.dsp +// Spec Reference: c_dspldst st_drhi_i +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + W [ I0 ] = R0.H; + W [ I1 ] = R1.H; + W [ I2 ] = R2.H; + W [ I3 ] = R3.H; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x00010A23; + CHECKREG r5, 0x20211B34; + CHECKREG r6, 0x40412C45; + CHECKREG r7, 0x60613D56; + W [ I0 ] = R1.H; + W [ I1 ] = R2.H; + W [ I2 ] = R3.H; + W [ I3 ] = R4.H; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x00011B34; + CHECKREG r5, 0x20212C45; + CHECKREG r6, 0x40413D56; + CHECKREG r7, 0x60610001; + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + W [ I0 ] = R2.H; + W [ I1 ] = R3.H; + W [ I2 ] = R4.H; + W [ I3 ] = R5.H; + R0 = [ I0 ]; + R1 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r0, 0x00012C45; + CHECKREG r1, 0x20213D56; + CHECKREG r6, 0x40414E67; + CHECKREG r7, 0x60615F78; + + W [ I0 ] = R4.H; + W [ I1 ] = R5.H; + W [ I2 ] = R6.H; + W [ I3 ] = R7.H; + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + CHECKREG r0, 0x00014E67; + CHECKREG r1, 0x20215F78; + CHECKREG r6, 0x40414E67; + CHECKREG r7, 0x60615F78; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_st_drhi_ipp.s b/sim/testsuite/bfin/c_dspldst_st_drhi_ipp.s new file mode 100644 index 0000000..4e25d9d --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_st_drhi_ipp.s @@ -0,0 +1,355 @@ +//Original:testcases/core/c_dspldst_st_drhi_ipp/c_dspldst_st_drhi_ipp.dsp +// Spec Reference: c_dspldst st_drhi_ipp +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + +// Half reg 16 bit mem store + + imm32 r0, 0x0a123456; + imm32 r1, 0x11b12345; + imm32 r2, 0x222c1234; + imm32 r3, 0x3344d012; + imm32 r4, 0x5566e012; + imm32 r5, 0x789abf01; + imm32 r6, 0xabcd0123; + imm32 r7, 0x01234567; + +// initial values + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + W [ I0 ++ ] = R0.H; + W [ I1 ++ ] = R1.H; + W [ I2 ++ ] = R2.H; + W [ I3 ++ ] = R3.H; + W [ I0 ++ ] = R1.H; + W [ I1 ++ ] = R2.H; + W [ I2 ++ ] = R3.H; + W [ I3 ++ ] = R4.H; + + W [ I0 ++ ] = R3.H; + W [ I1 ++ ] = R4.H; + W [ I2 ++ ] = R5.H; + W [ I3 ++ ] = R6.H; + + W [ I0 ++ ] = R4.H; + W [ I1 ++ ] = R5.H; + W [ I2 ++ ] = R6.H; + W [ I3 ++ ] = R7.H; + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x11B10A12; + CHECKREG r1, 0x222C11B1; + CHECKREG r2, 0x3344222C; + CHECKREG r3, 0x55663344; + CHECKREG r4, 0x55663344; + CHECKREG r5, 0x789A5566; + CHECKREG r6, 0xABCD789A; + CHECKREG r7, 0x0123ABCD; + + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x28292A2B; + CHECKREG r2, 0x48494A4B; + CHECKREG r3, 0x68696A6B; + CHECKREG r4, 0x0C0D0E0F; + CHECKREG r5, 0x2C2D2E2F; + CHECKREG r6, 0x4C4D4E4F; + CHECKREG r7, 0x6C6D6E6F; + +// initial values + + imm32 r0, 0x01b2c3d4; + imm32 r1, 0x10145618; + imm32 r2, 0xa2016729; + imm32 r3, 0xbb30183a; + imm32 r4, 0xdec4014b; + imm32 r5, 0x5f7d501c; + imm32 r6, 0x3089eb01; + imm32 r7, 0x719abf70; + + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + + W [ I0 -- ] = R0.H; + W [ I1 -- ] = R1.H; + W [ I2 -- ] = R2.H; + W [ I3 -- ] = R3.H; + W [ I0 -- ] = R1.H; + W [ I1 -- ] = R2.H; + W [ I2 -- ] = R3.H; + W [ I3 -- ] = R4.H; + + W [ I0 -- ] = R3.H; + W [ I1 -- ] = R4.H; + W [ I2 -- ] = R5.H; + W [ I3 -- ] = R6.H; + W [ I0 -- ] = R4.H; + W [ I1 -- ] = R5.H; + W [ I2 -- ] = R6.H; + W [ I3 -- ] = R7.H; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0x000001B2; + CHECKREG r1, 0x00001014; + CHECKREG r2, 0x0000A201; + CHECKREG r3, 0x0000BB30; + CHECKREG r4, 0x1014BB30; + CHECKREG r5, 0xA201DEC4; + CHECKREG r6, 0xBB305F7D; + CHECKREG r7, 0xDEC43089; + + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0xDEC41A1B; + CHECKREG r1, 0x5F7D3A3B; + CHECKREG r2, 0x30895A5B; + CHECKREG r3, 0x719A7A7B; + CHECKREG r4, 0x14151617; + CHECKREG r5, 0x34353637; + CHECKREG r6, 0x54555657; + CHECKREG r7, 0x74757677; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_st_drlo_i.s b/sim/testsuite/bfin/c_dspldst_st_drlo_i.s new file mode 100644 index 0000000..7b36691 --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_st_drlo_i.s @@ -0,0 +1,163 @@ +//Original:/testcases/core/c_dspldst_st_drlo_i/c_dspldst_st_drlo_i.dsp +// Spec Reference: c_dspldst st_drlo_i +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + W [ I0 ] = R0.L; + W [ I1 ] = R1.L; + W [ I2 ] = R2.L; + W [ I3 ] = R3.L; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x00014507; + CHECKREG r5, 0x20215618; + CHECKREG r6, 0x40416729; + CHECKREG r7, 0x6061783A; + W [ I0 ] = R3.L; + W [ I1 ] = R2.L; + W [ I2 ] = R1.L; + W [ I3 ] = R0.L; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x0001783A; + CHECKREG r5, 0x20216729; + CHECKREG r6, 0x40415618; + CHECKREG r7, 0x60614507; + + imm32 r0, 0x1a334507; + imm32 r1, 0x12345618; + imm32 r2, 0x2c3e6729; + imm32 r3, 0x3d54f83a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f789c5c; + imm32 r6, 0x6089ad7d; + imm32 r7, 0x739abc88; + + W [ I0 ] = R4.L; + W [ I1 ] = R5.L; + W [ I2 ] = R6.L; + W [ I3 ] = R7.L; + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + CHECKREG r0, 0x0001594B; + CHECKREG r1, 0x20219C5C; + CHECKREG r2, 0x4041AD7D; + CHECKREG r3, 0x6061BC88; + + W [ I0 ] = R7.L; + W [ I1 ] = R6.L; + W [ I2 ] = R5.L; + W [ I3 ] = R4.L; + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + CHECKREG r0, 0x0001BC88; + CHECKREG r1, 0x2021AD7D; + CHECKREG r2, 0x40419C5C; + CHECKREG r3, 0x6061594B; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_dspldst_st_drlo_ipp.s b/sim/testsuite/bfin/c_dspldst_st_drlo_ipp.s new file mode 100644 index 0000000..08483e3 --- /dev/null +++ b/sim/testsuite/bfin/c_dspldst_st_drlo_ipp.s @@ -0,0 +1,351 @@ +//Original:testcases/core/c_dspldst_st_drlo_ipp/c_dspldst_st_drlo_ipp.dsp +// Spec Reference: c_dspldst st_drlo_ipp +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + +// Half reg 16 bit mem store + + imm32 r0, 0x0a123456; + imm32 r1, 0x11b12345; + imm32 r2, 0x222c1234; + imm32 r3, 0x3344d012; + imm32 r4, 0x5566e012; + imm32 r5, 0x789abf01; + imm32 r6, 0xabcd0123; + imm32 r7, 0x01234567; + +// initial values + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + W [ I0 ++ ] = R0.L; + W [ I1 ++ ] = R1.L; + W [ I2 ++ ] = R2.L; + W [ I3 ++ ] = R3.L; + W [ I0 ++ ] = R1.L; + W [ I1 ++ ] = R2.L; + W [ I2 ++ ] = R3.L; + W [ I3 ++ ] = R4.L; + + W [ I0 ++ ] = R3.L; + W [ I1 ++ ] = R4.L; + W [ I2 ++ ] = R5.L; + W [ I3 ++ ] = R6.L; + W [ I0 ++ ] = R4.L; + W [ I1 ++ ] = R5.L; + W [ I2 ++ ] = R6.L; + W [ I3 ++ ] = R7.L; + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x23453456; + CHECKREG r1, 0x12342345; + CHECKREG r2, 0xD0121234; + CHECKREG r3, 0xE012D012; + CHECKREG r4, 0xE012D012; + CHECKREG r5, 0xBF01E012; + CHECKREG r6, 0x0123BF01; + CHECKREG r7, 0x45670123; + + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x28292A2B; + CHECKREG r2, 0x48494A4B; + CHECKREG r3, 0x68696A6B; + CHECKREG r4, 0x0C0D0E0F; + CHECKREG r5, 0x2C2D2E2F; + CHECKREG r6, 0x4C4D4E4F; + CHECKREG r7, 0x6C6D6E6F; + +// initial values + + imm32 r0, 0x01b2c3d4; + imm32 r1, 0x10145618; + imm32 r2, 0xa2016729; + imm32 r3, 0xbb30183a; + imm32 r4, 0xdec4014b; + imm32 r5, 0x5f7d501c; + imm32 r6, 0x3089eb01; + imm32 r7, 0x719abf70; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + + W [ I0 -- ] = R0.L; + W [ I1 -- ] = R1.L; + W [ I2 -- ] = R2.L; + W [ I3 -- ] = R3.L; + W [ I0 -- ] = R1.L; + W [ I1 -- ] = R2.L; + W [ I2 -- ] = R3.L; + W [ I3 -- ] = R4.L; + + W [ I0 -- ] = R3.L; + W [ I1 -- ] = R4.L; + W [ I2 -- ] = R5.L; + W [ I3 -- ] = R6.L; + W [ I0 -- ] = R4.L; + W [ I1 -- ] = R5.L; + W [ I2 -- ] = R6.L; + W [ I3 -- ] = R7.L; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0x0000C3D4; + CHECKREG r1, 0x00005618; + CHECKREG r2, 0x00006729; + CHECKREG r3, 0x0000183A; + CHECKREG r4, 0x5618183A; + CHECKREG r5, 0x6729014B; + CHECKREG r6, 0x183A501C; + CHECKREG r7, 0x014BEB01; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0x014B1A1B; + CHECKREG r1, 0x501C3A3B; + CHECKREG r2, 0xEB015A5B; + CHECKREG r3, 0xBF707A7B; + CHECKREG r4, 0x14151617; + CHECKREG r5, 0x34353637; + CHECKREG r6, 0x54555657; + CHECKREG r7, 0x74757677; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_except_illopcode.S b/sim/testsuite/bfin/c_except_illopcode.S new file mode 100644 index 0000000..bf6c66d --- /dev/null +++ b/sim/testsuite/bfin/c_except_illopcode.S @@ -0,0 +1,99 @@ +//Original:/proj/frio/dv/testcases/core/c_except_illopcode/c_except_illopcode.dsp +// Spec Reference: c_exception illegal opcode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +// load address of exception handler + +P0 = 0x200C (Z); // 0xFFE0200C EVT3 EXCEPTION +P0.H = 0xFFE0; +R0 = exception_handler (Z); // wr address of exception handler to MMR EVT3 +R0.H = exception_handler; +[ P0 ] = R0; + +// Jump to User mode and enable exceptions + +R0 = MidUserCode (Z); +R0.H = MidUserCode; +RETI = R0; +RTI; // cause it to go to Midusercode, .dd cause exception + +BeginUserCode: +P1 = 1; +P2 = 2; +P3 = 3; +P4 = 4; + +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000001); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000003); +// CHECKREG(r4, 0x00000098); +CHECKREG(r5, 0x00000005); +CHECKREG(r6, 0x00000006); +CHECKREG(r7, 0x00000007); +CHECKREG(p1, 0x00000001); +CHECKREG(p2, 0x00000002); +CHECKREG(p3, 0x00000003); +CHECKREG(p4, 0x00000004); + +dbg_pass; +//jump 2; +//jump -2; +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF + +//dbg_pass; + +MidUserCode: +.dd 0xFFFFFFFF +R0 = 0; +R1 = 1; +R2 = 2; +R3 = 3; +CC = R0; +IF !CC JUMP BeginUserCode; + +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF + +//.code 0x800 + +exception_handler: +R4 = RETX; // error handler: RETX has the address of the same Illegal instr +R5 = 5; +R6 = 6; +R7 = 7; +R4 += 4; // we have to add 4 to point to next instr after return +RETX = R4; + +RTX; // return from exception + //nop; + +.section MEM_DATA_ADDR_1,"aw" +.dd 0xDEADBEEF +.dd 0xBAD00BAD diff --git a/sim/testsuite/bfin/c_except_sys_sstep.S b/sim/testsuite/bfin/c_except_sys_sstep.S new file mode 100644 index 0000000..c719555 --- /dev/null +++ b/sim/testsuite/bfin/c_except_sys_sstep.S @@ -0,0 +1,252 @@ +//Original:/proj/frio/dv/testcases/core/c_except_sys_sstep/c_except_sys_sstep.dsp +// Spec Reference: Single Step Supervisor Exception Test (NO REGTRACE!) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +// CHECK_INIT(p2, 0x2000); +include(symtable.inc) +CHECK_INIT_DEF(p2); + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + R0 = 1; +SYSCFG = r0; // Enable Supervisor Single Step + R4 = 0; + +LD32_LABEL(r0, START); +RETI = r0; // We need to load the return address + +RTI; + + +START: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + R0 = 0; + R1 = 1; + R2 = 2; + R3 = 3; + R5 = 5; + R6 = 6; + R7 = 7; + +EXCPT 3; // turn off single step via handler + +CHECKREG(r4, 0x0b); // 11 instrs are executed before single step = disabled +CHECKREG(r0, 0x00); +CHECKREG(r1, 0x03); +CHECKREG(r2, 0x10); +CHECKREG(r3, 0x04); +CHECKREG(r5, 0x09); +CHECKREG(r6, 0x06); +CHECKREG(r7, 0x07); + + + // PUT YOUR TEST HERE! + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + [ -- SP ] = ASTAT; // save ASTAT + R1 = SEQSTAT; + R1 <<= 26; + R1 >>= 26; // only want EXCAUSE + R2 = 0x10; // EXCAUSE 0x10 means Single Step (exception) +CC = r1 == r2; +IF CC JUMP SSCOUNT; // Go to Single Step Handler + +SYSCFG = r0; // otherwise must be an EXCPT, so turn off singlestep + R3 += 1; + +JUMP.S EXIT; + +SSCOUNT: + R4 += 1; // R4 counts single step events + +EXIT: +ASTAT = [sp++]; + R5 += 1; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_except_user_mode.S b/sim/testsuite/bfin/c_except_user_mode.S new file mode 100644 index 0000000..8c71bd7f --- /dev/null +++ b/sim/testsuite/bfin/c_except_user_mode.S @@ -0,0 +1,349 @@ +//Original:/proj/frio/dv/testcases/core/c_except_user_mode/c_except_user_mode.dsp +// Spec Reference: except_mode_user +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; // execute this instr put us in USER mode + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // USER MODE & go to different RAISE in USER mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +RAISE 2; // RTN // exception because we execute this in USER mode +RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; + + +CHECKREG(r0, 0x00000018); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x00000000); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = RETN; + R0 += 2; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +RETN = r0; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = RETX; + I0 += 2; + R1 += 2; // for return address +RETX = r1; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = RETI; + R2 += 2; + I0 += 2; + I1 += 2; +RETI = r2; +RTI; + +THANDLE: // Timer Handler 6 + R3 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + R3 += 2; +RETI = r3; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = RETI; + I0 += 2; + I1 += 2; + I3 += 2; + R4 += 2; +RETI = r4; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R5 += 2; +RETI = r5; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R6 += 2; +RETI = r6; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R7 += 2; +RETI = r7; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = RETI; + R0 += 2; + M0 = I0; + M1 = I1; + M2 = I2; + M3 = I3; +RETI = r0; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R1 += 2; +RETI = r1; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R2 += 2; +RETI = r2; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R3 += 2; +RETI = r3; +RTI; + +I15HANDLE: // IVG 15 Handler + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +RTI; + +// nop;nop;nop;nop;nop;nop;nop; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: +// .space (STACKSIZE); // adding this may solve the problem diff --git a/sim/testsuite/bfin/c_interr_disable.S b/sim/testsuite/bfin/c_interr_disable.S new file mode 100644 index 0000000..5a64623 --- /dev/null +++ b/sim/testsuite/bfin/c_interr_disable.S @@ -0,0 +1,323 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_disable/c_interr_disable.dsp +// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0x00BFFFFC); + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +//.code 0x200 + START : + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +CLI R1; // stop interrupt +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000050, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000000, p0, r0); +CSYNC; + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000050); + +// RD_MMR(TCOUNT, p0, r3); +// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + +RD_MMR(TPERIOD, p0, r4); +CHECKREG(r4, 0x00000050); + +// RD_MMR(TCNTL, p0, r5); +// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000015, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000002, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) +CSYNC; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label4; + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label5: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label6; + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +label4: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +JUMP.S label5; + R5.L = 0x2222; // Will be killed + R5.H = 0x2222; // Will be killed +NOP; +NOP; +NOP; +NOP; +label6: R3.H = 0x7999; + R3.L = 0x7aaa; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + // With auto reload + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000015); + +// RD_MMR(TCNTL , p0, r3); +// CHECKREG(r3, 0x0000000F); +CHECKREG(r7, 0x00000000); // no interrupt being serviced +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +STI R1; +NOP; +CHECKREG(r7, 0x00000001); // interrupt being serviced +// WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +// csync; +NOP; + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_DATA_ADDR_1,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/bfin/c_interr_disable_enable.S b/sim/testsuite/bfin/c_interr_disable_enable.S new file mode 100644 index 0000000..ac28cdb --- /dev/null +++ b/sim/testsuite/bfin/c_interr_disable_enable.S @@ -0,0 +1,344 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_disable_enable/c_interr_disable_enable.dsp +// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0x00BFFFFC); + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + // LD32(sp, 0x000FF200); +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +//.code 0x200 + START : + P1 = 0; + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +CLI R1; // stop interrupt +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000050, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000000, p0, r0); +CSYNC; + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000050); + +// RD_MMR(TCOUNT, p0, r3); +// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + +RD_MMR(TPERIOD, p0, r4); +CHECKREG(r4, 0x00000050); + +// RD_MMR(TCNTL, p0, r5); +// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000015, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000002, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) +CSYNC; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label4; + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label5: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label6; + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +label4: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +JUMP.S label5; + R5.L = 0x2222; // Will be killed + R5.H = 0x2222; // Will be killed +NOP; +NOP; +NOP; +NOP; +label6: R3.H = 0x7999; + R3.L = 0x7aaa; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + // With auto reload + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000015); + +// RD_MMR(TCNTL , p0, r3); +// CHECKREG(r3, 0x0000000F); +CHECKREG(r7, 0x00000000); // no interrupt being serviced +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +STI R1; +NOP; +CHECKREG(r7, 0x00000001); // interrupt being serviced +WR_MMR(TCOUNT, 0x00000005, p0, r0); +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +CHECKREG(r7, 0x00000002); // interrupt being serviced +RAISE 7; +NOP; NOP; +CHECKREG(p1, 0x00000001); // interrupt being serviced + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// +//.code ITABLE + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler + P1 += 1; +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.data + +.space (STACKSIZE); +KSTACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/bfin/c_interr_excpt.S b/sim/testsuite/bfin/c_interr_excpt.S new file mode 100644 index 0000000..911a78e --- /dev/null +++ b/sim/testsuite/bfin/c_interr_excpt.S @@ -0,0 +1,290 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_excpt/c_interr_excpt.dsp +// Spec Reference: interr excpt +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = 4; + + +EXCPT 1; // RTX +EXCPT 2; // RTX +EXCPT 3; // RTX +EXCPT 4; // RTX +EXCPT 5; // RTX +EXCPT 5; // RTX +EXCPT 6; // RTX +EXCPT 7; // RTX +EXCPT 8; // RTX +EXCPT 9; // RTX +EXCPT 10; // RTX +EXCPT 11; // RTX +EXCPT 12; // RTX +EXCPT 13; // RTX +EXCPT 14; // RTX +EXCPT 15; // RTX + +CHECKREG(r0, 0x33333333); +CHECKREG(r1, 0xCCCCCCCD); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x33333333); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x00000000); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + R0 = R1 + R2; + R1 = R2 + R3; + R2 = R0 + R1; + R3 = R0 + R2; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +//.data 0xF0000000 +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_interr_loopsetup_stld.S b/sim/testsuite/bfin/c_interr_loopsetup_stld.S new file mode 100644 index 0000000..824b53e --- /dev/null +++ b/sim/testsuite/bfin/c_interr_loopsetup_stld.S @@ -0,0 +1,224 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_loopsetup_stld/c_interr_loopsetup_stld.dsp +// Spec Reference: interrupt loopsetup_ldst +# mach: bfin + +#include "test.h" +.include "testutils.inc" +start + + A0 = 0; // reset accumulators + A1 = 0; + +P1 = 3; +P2 = 4; + +LD32(r0, 0x00200005); +LD32(r1, 0x00300010); +LD32(r2, 0x00500012); +LD32(r3, 0x00600024); +LD32(r4, 0x00700016); +LD32(r5, 0x00900028); +LD32(r6, 0x0a000030); +LD32(r7, 0x00b00044); + +loadsym I0, DATA0; +loadsym I1, DATA1; +R0 = [ I0 ++ ]; +R1 = [ I1 ++ ]; +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += 2; + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; // dsp32mac dual + // a1 += h*h, a0 += l*l (r0,r1) ; r0 = [i0++]; r1 = [i1++]; // dsp32mac + R2 = ( R2 + R5 ) << 1; // alu2op +DIVQ ( R5 , R3 ); + R1 <<= R5; + R1 >>>= R1; + R6 = ~ R0; + //MY_GEN_INT(10, 1) +DIVQ ( R5 , R2 ); + R0 = R3.B (X); +DIVS ( R7 , R0 ); +end1: R2 += 3; + R3 = ( A0 += A1 ); +CHECKREG(r0, 0x00000024); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x0670098D); +CHECKREG(r3, 0x000015EC); +CHECKREG(r4, 0x00700016); +CHECKREG(r5, 0x0B240A39); +CHECKREG(r6, 0xFFF2FFFC); +CHECKREG(r7, 0x05800220); + +A0 = 0; +A1 = 0; +LSETUP ( start2 , end2 ) LC0 = P2; +start2: R4 += 4; + //a1 += h*h, a0 += l*l (r0,r1), r0 = [i0--], r1 = [i1--]; + A1 += R0.H * R1.H, A0 += R0.L * R1.L; R0 = [ I0 -- ]; R1 = [ I1 -- ]; + R1 <<= R5; + R6 = R7.B (Z); + R2 = - R6; + R3 = R4.L (Z); +DIVS ( R1 , R1 ); + R6 = - R0; + R0 >>= R0; +DIVS ( R4 , R7 ); + //MY_GEN_INT(13, 1) + R1 = R2.L (Z); +end2: R5 += -5; + R6 = ( A0 += A1 ); +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x0000FFE0); +CHECKREG(r2, 0xFFFFFFE0); +CHECKREG(r3, 0x000000EC); +CHECKREG(r4, 0x070001D8); +CHECKREG(r5, 0x0B240A25); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x05800220); +LD32(r0, 0x01200805); +LD32(r1, 0x02300710); +LD32(r2, 0x03500612); +LD32(r3, 0x04600524); +LD32(r4, 0x05700416); +LD32(r5, 0x06900328); +LD32(r6, 0x0a700230); +LD32(r7, 0x08b00044); + +loadsym I2, DATA0; +loadsym I3, DATA1; +[ I2 ++ ] = R0; +[ I3 ++ ] = R1; +LSETUP ( start3 , end3 ) LC0 = P1; +start3: + [ I2 ++ ] = R2; + [ I3 ++ ] = R3; + R2 += 1; +end3: + R3 += 1; + +A0 = 0; +A1 = 0; +LSETUP ( start4 , end4 ) LC0 = P2; +R0 = [ I0 -- ]; +R1 = [ I1 -- ]; +start4: + // a1 += h*h, a0 += l*l (r0,r1), r0 = [i2--], r1 = [i3--]; + A1 += R0.H * R1.H, A0 += R0.L * R1.L; R0 = [ I2 -- ]; R1 = [ I3 -- ]; + R4 = R4 + R0; // comp3op + R5 = R7.L (Z); + R4 >>>= R5; + R0 = R7.B (X); +DIVQ ( R6 , R6 ); + //MY_GEN_INT(7, 1) +end4: R5 = R5 + R1; + R6 = ( A0 += A1 ); + R7 = ( A0 += A1 ); +CHECKREG(r0, 0x00000044); +CHECKREG(r1, 0x04600524); +CHECKREG(r2, 0x03500615); +CHECKREG(r3, 0x04600527); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x04600568); +CHECKREG(r6, 0x007C3498); +CHECKREG(r7, 0x00812098); + + +pass; // End the test + +// +// Data Segment +// + + + +.data + +DATA0: +.dd 0x000a0000 +.dd 0x000b0001 +.dd 0x000c0002 +.dd 0x000d0003 +.dd 0x000e0004 +.dd 0x000f0005 +.dd 0x00100006 +.dd 0x00200007 +.dd 0x00300008 +.dd 0x00400009 +.dd 0x0050000a +.dd 0x0060000b +.dd 0x0070000c +.dd 0x0080000d +.dd 0x0090000e +.dd 0x0100000f +.dd 0x02000010 +.dd 0x03000011 +.dd 0x04000012 +.dd 0x05000013 +.dd 0x06000014 +.dd 0x001a0000 +.dd 0x001b0001 +.dd 0x001c0002 +.dd 0x001d0003 +.dd 0x00010004 +.dd 0x00010005 +.dd 0x02100006 +.dd 0x02200007 +.dd 0x02300008 +.dd 0x02200009 +.dd 0x0250000a +.dd 0x0260000b +.dd 0x0270000c +.dd 0x0280000d +.dd 0x0290000e +.dd 0x2100000f +.dd 0x22000010 +.dd 0x22000011 +.dd 0x24000012 +.dd 0x25000013 +.dd 0x26000014 + +DATA1: +.dd 0x00f00100 +.dd 0x00e00101 +.dd 0x00d00102 +.dd 0x00c00103 +.dd 0x00b00104 +.dd 0x00a00105 +.dd 0x00900106 +.dd 0x00800107 +.dd 0x00100108 +.dd 0x00200109 +.dd 0x0030010a +.dd 0x0040010b +.dd 0x0050011c +.dd 0x0060010d +.dd 0x0070010e +.dd 0x0080010f +.dd 0x00900110 +.dd 0x01000111 +.dd 0x02000112 +.dd 0x03000113 +.dd 0x04000114 +.dd 0x05000115 +.dd 0x03f00100 +.dd 0x03e00101 +.dd 0x03d00102 +.dd 0x03c00103 +.dd 0x03b00104 +.dd 0x03a00105 +.dd 0x03900106 +.dd 0x03800107 +.dd 0x03100108 +.dd 0x03200109 +.dd 0x0330010a +.dd 0x0330010b +.dd 0x0350011c +.dd 0x0360010d +.dd 0x0370010e +.dd 0x0380010f +.dd 0x03900110 +.dd 0x31000111 +.dd 0x32000112 +.dd 0x33000113 +.dd 0x34000114 diff --git a/sim/testsuite/bfin/c_interr_nested.S b/sim/testsuite/bfin/c_interr_nested.S new file mode 100644 index 0000000..55af970 --- /dev/null +++ b/sim/testsuite/bfin/c_interr_nested.S @@ -0,0 +1,289 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_nested/c_interr_nested.dsp +// Spec Reference: interrupt nested using raises +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +RAISE 2; // RTN +// RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +// RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +// RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI +RAISE 15; // RTI + +CHECKREG(r0, 0x0000000B); +CHECKREG(r1, 0x0000000C); +CHECKREG(r2, 0x0000000D); +CHECKREG(r3, 0x0000000E); +CHECKREG(r4, 0x00000007); +CHECKREG(r5, 0x00000008); +CHECKREG(r6, 0x00000009); +CHECKREG(r7, 0x0000000A); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +CHECKREG(r0, 0x00000002); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000005); +CHECKREG(r3, 0x00000006); +CHECKREG(r4, 0x00000007); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RAISE 5; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RAISE 8; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RAISE 12; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_interr_nmi.S b/sim/testsuite/bfin/c_interr_nmi.S new file mode 100644 index 0000000..5124494 --- /dev/null +++ b/sim/testsuite/bfin/c_interr_nmi.S @@ -0,0 +1,318 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_nmi/c_interr_nmi.dsp +// Spec Reference: progctrl raise rti rtn +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +R0 = 0; +R1 = 0; +R2 = 0; +R3 = 0; +R4 = 0; +R5 = 0; +R6 = 0; +R7 = 0; + +RAISE 2; // RTN +RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI +RAISE 15; // RTI + +CHECKREG(r0, 0x0000000B); +CHECKREG(r1, 0x0000001A); +CHECKREG(r2, 0x00000024); +CHECKREG(r3, 0x00000028); +CHECKREG(r4, 0x0000000E); +CHECKREG(r5, 0x00000010); +CHECKREG(r6, 0x00000012); +CHECKREG(r7, 0x00000014); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +CHECKREG(r0, 0x0000000B); +CHECKREG(r1, 0x0000000E); +CHECKREG(r2, 0x00000017); +CHECKREG(r3, 0x0000001A); +CHECKREG(r4, 0x0000000E); + +( R7:0 ) = [ SP ++ ]; // pop + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x00000000); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x00000000); +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 += 1; + R1 += 2; +RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI +RAISE 15; // RTI + [ -- SP ] = ( R7:0 ); // push +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 += 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 += 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 += 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 += 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 += 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 += 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 += 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 += 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 += 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 += 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_interr_pending.S b/sim/testsuite/bfin/c_interr_pending.S new file mode 100644 index 0000000..96b5a96 --- /dev/null +++ b/sim/testsuite/bfin/c_interr_pending.S @@ -0,0 +1,324 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_pending/c_interr_pending.dsp +// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0x00BFFFFC); + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +//.code 0x200 + START : + P1 = 0x0; + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +CLI R1; // stop interrupt +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000050, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000000, p0, r0); +CSYNC; + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000050); + +// RD_MMR(TCOUNT, p0, r3); +// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + +RD_MMR(TPERIOD, p0, r4); +CHECKREG(r4, 0x00000050); + +// RD_MMR(TCNTL, p0, r5); +// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000015, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000002, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) +CSYNC; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label4; + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label5: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label6; + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +label4: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +JUMP.S label5; + R5.L = 0x2222; // Will be killed + R5.H = 0x2222; // Will be killed +NOP; +NOP; +NOP; +NOP; +label6: R3.H = 0x7999; + R3.L = 0x7aaa; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + // With auto reload + // Read the contents of the Timer +RAISE 7; +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000015); + +CHECKREG(p1, 0x00000000); // no interrupt being serviced +CHECKREG(r7, 0x00000000); // no interrupt being serviced +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +STI R1; +NOP; NOP; NOP; +CHECKREG(r7, 0x00000001); // interrupt being serviced +CHECKREG(p1, 0x00000001); // interrupt being serviced +NOP; + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// +//.code ITABLE + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler + P1 += 1; + +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_DATA_ADDR_1,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/bfin/c_interr_pending_2.S b/sim/testsuite/bfin/c_interr_pending_2.S new file mode 100644 index 0000000..2f1cf6c --- /dev/null +++ b/sim/testsuite/bfin/c_interr_pending_2.S @@ -0,0 +1,268 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_pending_2/c_interr_pending_2.dsp +// Spec Reference: interr pending (raise) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +// + +////MY_GEN_INT_INIT(0x000f0000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + //CHECK_INIT(p5, 0x00002000); +include(symtable.inc) +CHECK_INIT_DEF(p0); + + +LD32(r0, 0x8b235625); +LD32(r1, 0x93ba5127); +LD32(r2, 0xa3446725); +LD32(r3, 0x00050027); +LD32(r4, 0xb0ab6d29); +LD32(r5, 0x10ace72b); +LD32(r6, 0xc00c008d); +LD32(r7, 0xd2467029); +R4.H = R0.L * R1.L, R4.L = R0.L * R1.L; +CLI R0; +R5.H = R2.H * R3.L, R5.L = R2.L * R3.H; +RAISE 8; +RAISE 9; +CHECKREG(r4, 0x369E369E); +CHECKREG(r5, 0xFFE40004); +SSYNC; +STI R0; +R6.H = R1.L * R2.L, R6.L = R1.H * R2.L; +R7.H = R1.L * R3.H, R7.L = R1.H * R3.H; + +CHECKREG(r4, 0x369E369F); +CHECKREG(r5, 0xFFE40005); +CHECKREG(r6, 0x4165A8C0); +CHECKREG(r7, 0x0003FFFC); + + + +END: +dbg_pass; // End the test + +//********************************************************************* +// +// Handlers for Events +// +//.code 0x000f0000 + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler + R4 += 1; +RTI; + +I9HANDLE: // IVG 9 Handler + R5 += 1; +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" + +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_interr_timer.S b/sim/testsuite/bfin/c_interr_timer.S new file mode 100644 index 0000000..181213e --- /dev/null +++ b/sim/testsuite/bfin/c_interr_timer.S @@ -0,0 +1,384 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_timer/c_interr_timer.dsp +// Spec Reference: interrupt on HW TIMER +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +//.code 0x200 + START : + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR(0) (active state) +WR_MMR(TPERIOD, 0x00000050, p0, r0); + // WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TCOUNT, 0x00000000, p0, r0); +WR_MMR(TSCALE, 0x00000000, p0, r0); +CSYNC; + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000050); + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR(0), TMREN(1)) +CSYNC; // TIMER interrupt + +RD_MMR(TCOUNT, p0, r3); +CSYNC; +CHECKREG(r3, 0x00000000); +CHECKREG(r7, 0x00000001); +WR_MMR(TCNTL, 0x00000001, p0, r0); // enable Timer (TMPWR(0), TMREN(1)=0) +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR(0), TMREN(1)) +CSYNC; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +RD_MMR(TCOUNT, p0, r4); +CHECKREG(r4, 0x00000000); + +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000B); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Power, EN -> interr +CSYNC; +CHECKREG(r7, 0x00000003); // 3 interr already happened + R7 = 0; // reset r7 +WR_MMR(TPERIOD, 0x00000040, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000002, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auto load +CSYNC; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label4; + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label5: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label6; + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +label4: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +JUMP.S label5; + R5.L = 0x2222; // Will be killed + R5.H = 0x2222; // Will be killed +NOP; +NOP; +NOP; +NOP; +label6: R3.H = 0x7999; + R3.L = 0x7aaa; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + // With auto reload + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000040); + +// CHECKREG(r7, 0x00000002); +CC = R7 == 0; +IF !CC JUMP LABEL1; +WR_MMR(TPERIOD, 0x00000030, p0, r0); // SHOULD NOT EXECUTE + +LABEL1: + +NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; + + +RD_MMR(TCNTL , p0, r3); +CHECKREG(r3, 0x0000000F); + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer +CSYNC; +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000040); + + +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +RD_MMR(TCOUNT, p0, r4); +CHECKREG(r4, 0x00000000); + +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000B); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; NOP; NOP; + +WR_MMR(TPERIOD, 0x00000060, p0, r0); +CSYNC; +NOP; +RD_MMR(TPERIOD, p0, r6); +CHECKREG(r6, 0x00000060); + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_DATA_ADDR_1,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/bfin/c_interr_timer_reload.S b/sim/testsuite/bfin/c_interr_timer_reload.S new file mode 100644 index 0000000..d84e5f5 --- /dev/null +++ b/sim/testsuite/bfin/c_interr_timer_reload.S @@ -0,0 +1,286 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_timer_reload/c_interr_timer_reload.dsp +// Spec Reference: interrupt on HW TIMER auto-reload +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0x00BFFFFC); + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; + +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; + +//.code 0x200 + START : + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000020, p0, r0); +WR_MMR(TCOUNT, 0x00000002, p0, r0); +WR_MMR(TSCALE, 0x00000005, p0, r0); +CSYNC; + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000020); + +RD_MMR(TCOUNT, p0, r3); +CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + + + +NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; + +RD_MMR(TCOUNT, p0, r4); +CHECKREG(r4, 0x00000000); + +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000B); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +CHECKREG(r7, 0x00000001); + R7 = 0; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000020, p0, r0); +WR_MMR(TCOUNT, 0x00000003, p0, r0); +WR_MMR(TSCALE, 0x00000002, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auo-reload +CSYNC; +NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; + // With auto reload + // Read the contents of the Timer + +// CHECKREG(r7, 0x00000002); +CC = R7 == 0; +IF !CC JUMP LABEL1; +WR_MMR(TPERIOD, 0x00000030, p0, r0); // SHOULD NOT EXECUTE + +LABEL1: + + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000020); + +RD_MMR(TCNTL , p0, r3); +CHECKREG(r3, 0x0000000F); + +WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer but not auto-reload +CSYNC; + +NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; +RD_MMR(TCOUNT, p0, r4); +CHECKREG(r4, 0x00000000); + +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000B); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; NOP; NOP; + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_DATA_ADDR_1,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/bfin/c_interr_timer_tcount.S b/sim/testsuite/bfin/c_interr_timer_tcount.S new file mode 100644 index 0000000..cc8fddc --- /dev/null +++ b/sim/testsuite/bfin/c_interr_timer_tcount.S @@ -0,0 +1,242 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_timer_tcount/c_interr_timer_tcount.dsp +// Spec Reference: interrupt on HW TIMER tcount +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0x00BFFFFC); + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; + +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; + +//.code 0x200 + START : + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000010, p0, r0); +WR_MMR(TCOUNT, 0x00000002, p0, r0); +WR_MMR(TSCALE, 0x00000001, p0, r0); +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + + +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000B); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +CHECKREG(r7, 0x00000001); + R7 = 0; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000010, p0, r0); +WR_MMR(TCOUNT, 0x00000002, p0, r0); +WR_MMR(TSCALE, 0x00000003, p0, r0); +WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer +CSYNC; +NOP; +NOP; + // Read the contents of the Timer + + +RD_MMR(TCNTL , p0, r3); +CHECKREG(r3, 0x0000000B); + +CHECKREG(r7, 0x00000001); + + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; NOP; NOP; + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_DATA_ADDR_1,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/bfin/c_interr_timer_tscale.S b/sim/testsuite/bfin/c_interr_timer_tscale.S new file mode 100644 index 0000000..f8a87ac --- /dev/null +++ b/sim/testsuite/bfin/c_interr_timer_tscale.S @@ -0,0 +1,304 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_timer_tscale/c_interr_timer_tscale.dsp +// Spec Reference: interrupt on HW TIMER tscale +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0x00BFFFFC); + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; + +//.code 0x200 + START : + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000010, p0, r0); +WR_MMR(TCOUNT, 0x00000002, p0, r0); +WR_MMR(TSCALE, 0x00000001, p0, r0); +CSYNC; + // Read the contents of the Timer +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000010); + +RD_MMR(TCOUNT, p0, r3); +CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace -seed 8b8db910 + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + +RD_MMR(TCOUNT, p0, r4); +CHECKREG(r4, 0x00000000); + +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000B); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +CHECKREG(r7, 0x00000001); + R7 = 0; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000010, p0, r0); +WR_MMR(TCOUNT, 0x00000003, p0, r0); +WR_MMR(TSCALE, 0x00000128, p0, r0); +WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer +CSYNC; +NOP; +NOP; +label5: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label6; + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +label4: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +JUMP.S label5; + R5.L = 0x2222; // Will be killed + R5.H = 0x2222; // Will be killed +NOP; +label6: R3.H = 0x7999; + R3.L = 0x7aaa; +NOP; + // With auto reload + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000010); + +RD_MMR(TCNTL , p0, r3); +CHECKREG(r3, 0x0000000b); + +CHECKREG(r7, 0x00000001); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn ON Timer auto-reload +WR_MMR(TPERIOD, 0x00000020, p0, r0); +WR_MMR(TSCALE, 0x00000003, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auto-reload + +NOP; NOP; + R7 = 0; +CSYNC; + +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; + R1 = 1; + R2 = 1; + R3 = 2; +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000F); +CC = R1 < R7; +IF CC R2 = R3; + +CHECKREG(r2, 0x00000002); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; NOP; NOP; + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_DATA_ADDR_1,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/bfin/c_ldimmhalf_dreg.s b/sim/testsuite/bfin/c_ldimmhalf_dreg.s new file mode 100644 index 0000000..b39e4e1 --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_dreg.s @@ -0,0 +1,60 @@ +//Original:/testcases/core/c_ldimmhalf_dreg/c_ldimmhalf_dreg.dsp +// Spec Reference: ldimmhalf dreg imm16 +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + +// test Dreg +R0 = 0x0123 (X); +R1 = 0x1234 (X); +R2 = 0x2345 (X); +R3 = 0x3456 (X); +R4 = 0x4567 (X); +R5 = 0x5678 (X); +R6 = 0x6789 (X); +R7 = 0x789a (X); +CHECKREG r0, 0x00000123; +CHECKREG r1, 0x00001234; +CHECKREG r2, 0x00002345; +CHECKREG r3, 0x00003456; +CHECKREG r4, 0x00004567; +CHECKREG r5, 0x00005678; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x0000789A; + +R0 = -32768 (X); +R1 = -1111 (X); +R2 = -2222 (X); +R3 = -3333 (X); +R4 = -4444 (X); +R5 = -5555 (X); +R6 = -6666 (X); +R7 = -7777 (X); +CHECKREG r0, 0xFFFF8000; +CHECKREG r1, 0xFFFFFBA9; +CHECKREG r2, 0xFFFFF752; +CHECKREG r3, 0xFFFFF2FB; +CHECKREG r4, 0xFFFFEEA4; +CHECKREG r5, 0xFFFFEA4D; +CHECKREG r6, 0xFFFFE5F6; +CHECKREG r7, 0xFFFFE19F; + +R0 = 0x7fff (X); +R1 = 0x7ffe (X); +R2 = 32767 (X); +R3 = 32766 (X); +R4 = -32768 (X); +R5 = -32767 (X); +CHECKREG r0, 0x00007fff; +CHECKREG r1, 0x00007ffe; +CHECKREG r2, 0x00007fff; +CHECKREG r3, 0x00007ffe; +CHECKREG r4, 0xFFFF8000; +CHECKREG r5, 0xFFFF8001; + +pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_drhi.s b/sim/testsuite/bfin/c_ldimmhalf_drhi.s new file mode 100644 index 0000000..3b7194a --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_drhi.s @@ -0,0 +1,85 @@ +//Original:/testcases/core/c_ldimmhalf_drhi/c_ldimmhalf_drhi.dsp +// Spec Reference: ldimmhalf dreg hi +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + +// test Dreg +R0.H = 0x0001; +R1.H = 0x0003; +R2.H = 0x0005; +R3.H = 0x0007; +R4.H = 0x0009; +R5.H = 0x000b; +R6.H = 0x000d; +R7.H = 0x000f; +CHECKREG r0, 0x0001FFFF; +CHECKREG r1, 0x0003FFFF; +CHECKREG r2, 0x0005FFFF; +CHECKREG r3, 0x0007FFFF; +CHECKREG r4, 0x0009FFFF; +CHECKREG r5, 0x000bFFFF; +CHECKREG r6, 0x000dFFFF; +CHECKREG r7, 0x000fFFFF; + +R0.H = 0x0020; +R1.H = 0x0040; +R2.H = 0x0060; +R3.H = 0x0080; +R4.H = 0x00a0; +R5.H = 0x00b0; +R6.H = 0x00c0; +R7.H = 0x00d0; +CHECKREG r0, 0x0020FFFF; +CHECKREG r1, 0x0040FFFF; +CHECKREG r2, 0x0060FFFF; +CHECKREG r3, 0x0080FFFF; +CHECKREG r4, 0x00a0FFFF; +CHECKREG r5, 0x00b0FFFF; +CHECKREG r6, 0x00c0FFFF; +CHECKREG r7, 0x00d0FFFF; + +R0.H = 0x0100; +R1.H = 0x0200; +R2.H = 0x0300; +R3.H = 0x0400; +R4.H = 0x0500; +R5.H = 0x0600; +R6.H = 0x0700; +R7.H = 0x0800; +CHECKREG r0, 0x0100FFFF; +CHECKREG r1, 0x0200FFFF; +CHECKREG r2, 0x0300FFFF; +CHECKREG r3, 0x0400FFFF; +CHECKREG r4, 0x0500FFFF; +CHECKREG r5, 0x0600FFFF; +CHECKREG r6, 0x0700FFFF; +CHECKREG r7, 0x0800FFFF; + +R0 = 0; +R1 = 0; +R2 = 0; +R3 = 0; +R4 = 0; +R5 = 0; +R6 = 0; +R7 = 0; +R0.H = 0x7fff; +R1.H = 0x7ffe; +R2.H = 32767; +R3.H = 32766; +R4.H = -32768; +R5.H = -32767; +CHECKREG r0, 0x7fff0000; +CHECKREG r1, 0x7ffe0000; +CHECKREG r2, 0x7fff0000; +CHECKREG r3, 0x7ffe0000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80010000; + +pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_drlo.s b/sim/testsuite/bfin/c_ldimmhalf_drlo.s new file mode 100644 index 0000000..0a33d4a --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_drlo.s @@ -0,0 +1,89 @@ +//Original:/testcases/core/c_ldimmhalf_drlo/c_ldimmhalf_drlo.dsp +// Spec Reference: ldimmhalf dreg lo +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + +// test Dreg +R0.L = 0x0001; +R1.L = 0x0003; +R2.L = 0x0005; +R3.L = 0x0007; +R4.L = 0x0009; +R5.L = 0x000b; +R6.L = 0x000d; +R7.L = 0x000f; +CHECKREG r0, 0xFFFF0001; +CHECKREG r1, 0xFFFF0003; +CHECKREG r2, 0xFFFF0005; +CHECKREG r3, 0xFFFF0007; +CHECKREG r4, 0xFFFF0009; +CHECKREG r5, 0xFFFF000b; +CHECKREG r6, 0xFFFF000D; +CHECKREG r7, 0xFFFF000F; + +R0.L = 0x0020; +R1.L = 0x0040; +R2.L = 0x0060; +R3.L = 0x0080; +R4.L = 0x00a0; +R5.L = 0x00b0; +R6.L = 0x00c0; +R7.L = 0x00d0; +CHECKREG r0, 0xFFFF0020; +CHECKREG r1, 0xFFFF0040; +CHECKREG r2, 0xFFFF0060; +CHECKREG r3, 0xFFFF0080; +CHECKREG r4, 0xFFFF00a0; +CHECKREG r5, 0xFFFF00b0; +CHECKREG r6, 0xFFFF00c0; +CHECKREG r7, 0xFFFF00d0; + +R0.L = 0x0100; +R1.L = 0x0200; +R2.L = 0x0300; +R3.L = 0x0400; +R4.L = 0x0500; +R5.L = 0x0600; +R6.L = 0x0700; +R7.L = 0x0800; +CHECKREG r0, 0xFFFF0100; +CHECKREG r1, 0xFFFF0200; +CHECKREG r2, 0xFFFF0300; +CHECKREG r3, 0xFFFF0400; +CHECKREG r4, 0xFFFF0500; +CHECKREG r5, 0xFFFF0600; +CHECKREG r6, 0xFFFF0700; +CHECKREG r7, 0xFFFF0800; + +R0 = 0; +R1 = 0; +R2 = 0; +R3 = 0; +R4 = 0; +R5 = 0; +R6 = 0; +R7 = 0; +R0.L = 0x7fff; +R1.L = 0x7ffe; +R2.L = -32768; +R3.L = -32767; +R4.L = 32767; +R5.L = 32766; +R6.L = 32765; +R7.L = 32764; +CHECKREG r0, 0x00007fff; +CHECKREG r1, 0x00007ffe; +CHECKREG r2, 0x00008000; +CHECKREG r3, 0x00008001; +CHECKREG r4, 0x00007FFF; +CHECKREG r5, 0x00007FFE; +CHECKREG r6, 0x00007FFD; +CHECKREG r7, 0x00007FFC; + +pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_h_dr.s b/sim/testsuite/bfin/c_ldimmhalf_h_dr.s new file mode 100644 index 0000000..83e60db --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_h_dr.s @@ -0,0 +1,82 @@ +//Original:/testcases/core/c_ldimmhalf_h_dr/c_ldimmhalf_h_dr.dsp +// Spec Reference: ldimmhalf h dreg +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + + +// test Dreg +R0.H = 0x0000; +R1.H = 0x0002; +R2.H = 0x0004; +R3.H = 0x0006; +R4.H = 0x0008; +R5.H = 0x000a; +R6.H = 0x000c; +R7.H = 0x000e; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0002ffff; +CHECKREG r2, 0x0004ffff; +CHECKREG r3, 0x0006ffff; +CHECKREG r4, 0x0008ffff; +CHECKREG r5, 0x000affff; +CHECKREG r6, 0x000cffff; +CHECKREG r7, 0x000effff; + +R0.H = 0x0000; +R1.H = 0x0020; +R2.H = 0x0040; +R3.H = 0x0060; +R4.H = 0x0080; +R5.H = 0x00a0; +R6.H = 0x00c0; +R7.H = 0x00e0; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0020ffff; +CHECKREG r2, 0x0040ffff; +CHECKREG r3, 0x0060ffff; +CHECKREG r4, 0x0080ffff; +CHECKREG r5, 0x00a0ffff; +CHECKREG r6, 0x00c0ffff; +CHECKREG r7, 0x00e0ffff; + +R0.H = 0x0000; +R1.H = 0x0200; +R2.H = 0x0400; +R3.H = 0x0600; +R4.H = 0x0800; +R5.H = 0x0a00; +R6.H = 0x0c00; +R7.H = 0x0e00; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0200ffff; +CHECKREG r2, 0x0400ffff; +CHECKREG r3, 0x0600ffff; +CHECKREG r4, 0x0800ffff; +CHECKREG r5, 0x0a00ffff; +CHECKREG r6, 0x0c00ffff; +CHECKREG r7, 0x0e00ffff; + +R0.H = 0x0000; +R1.H = 0x2000; +R2.H = 0x4000; +R3.H = 0x6000; +R4.H = 0x8000; +R5.H = 0xa000; +R6.H = 0xc000; +R7.H = 0xe000; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x2000ffff; +CHECKREG r2, 0x4000ffff; +CHECKREG r3, 0x6000ffff; +CHECKREG r4, 0x8000ffff; +CHECKREG r5, 0xa000ffff; +CHECKREG r6, 0xc000ffff; +CHECKREG r7, 0xe000ffff; + +pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_h_ibml.s b/sim/testsuite/bfin/c_ldimmhalf_h_ibml.s new file mode 100644 index 0000000..8aedc09 --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_h_ibml.s @@ -0,0 +1,165 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_ibml/c_ldimmhalf_h_ibml.dsp +// Spec Reference: ldimmhalf h ibml +# mach: bfin + +.include "testutils.inc" + start + + INIT_I_REGS -1; + INIT_L_REGS -1; + INIT_B_REGS -1; + INIT_M_REGS -1; + + I0.H = 0x2000; + I1.H = 0x2002; + I2.H = 0x2004; + I3.H = 0x2006; + L0.H = 0x2008; + L1.H = 0x200a; + L2.H = 0x200c; + L3.H = 0x200e; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x2000ffff; + CHECKREG r1, 0x2002ffff; + CHECKREG r2, 0x2004ffff; + CHECKREG r3, 0x2006ffff; + CHECKREG r4, 0x2008ffff; + CHECKREG r5, 0x200affff; + CHECKREG r6, 0x200cffff; + CHECKREG r7, 0x200effff; + + I0.H = 0x0111; + I1.H = 0x1111; + I2.H = 0x2222; + I3.H = 0x3333; + L0.H = 0x4444; + L1.H = 0x5555; + L2.H = 0x6666; + L3.H = 0x7777; + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x0111ffff; + CHECKREG r1, 0x1111ffff; + CHECKREG r2, 0x2222ffff; + CHECKREG r3, 0x3333ffff; + CHECKREG r4, 0x4444ffff; + CHECKREG r5, 0x5555ffff; + CHECKREG r6, 0x6666ffff; + CHECKREG r7, 0x7777ffff; + + I0.H = 0x8888; + I1.H = 0x9aaa; + I2.H = 0xabbb; + I3.H = 0xbccc; + L0.H = 0xcddd; + L1.H = 0xdeee; + L2.H = 0xefff; + L3.H = 0xf111; + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x8888ffff; + CHECKREG r1, 0x9aaaffff; + CHECKREG r2, 0xabbbffff; + CHECKREG r3, 0xbcccffff; + CHECKREG r4, 0xcdddffff; + CHECKREG r5, 0xdeeeffff; + CHECKREG r6, 0xefffffff; + CHECKREG r7, 0xf111ffff; + + B0.H = 0x3000; + B1.H = 0x3002; + B2.H = 0x3004; + B3.H = 0x3006; + M0.H = 0x3008; + M1.H = 0x300a; + M2.H = 0x300c; + M3.H = 0x300e; + + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0x3000ffff; + CHECKREG r1, 0x3002ffff; + CHECKREG r2, 0x3004ffff; + CHECKREG r3, 0x3006ffff; + CHECKREG r4, 0x3008ffff; + CHECKREG r5, 0x300Affff; + CHECKREG r6, 0x300cffff; + CHECKREG r7, 0x300effff; + + B0.H = 0x0110; + B1.H = 0x1110; + B2.H = 0x2220; + B3.H = 0x3330; + M0.H = 0x4440; + M1.H = 0x5550; + M2.H = 0x6660; + M3.H = 0x7770; + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0x0110FFFF; + CHECKREG r1, 0x1110FFFF; + CHECKREG r2, 0x2220FFFF; + CHECKREG r3, 0x3330FFFF; + CHECKREG r4, 0x4440FFFF; + CHECKREG r5, 0x5550FFFF; + CHECKREG r6, 0x6660FFFF; + CHECKREG r7, 0x7770FFFF; + + B0.H = 0xf880; + B1.H = 0xfaa0; + B2.H = 0xfbb0; + B3.H = 0xfcc0; + M0.H = 0xfdd0; + M1.H = 0xfee0; + M2.H = 0xfff0; + M3.H = 0xf110; + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xf880ffff; + CHECKREG r1, 0xfaa0ffff; + CHECKREG r2, 0xfbb0ffff; + CHECKREG r3, 0xfcc0ffff; + CHECKREG r4, 0xfdd0ffff; + CHECKREG r5, 0xfee0ffff; + CHECKREG r6, 0xfff0ffff; + CHECKREG r7, 0xf110ffff; + + pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_h_pr.s b/sim/testsuite/bfin/c_ldimmhalf_h_pr.s new file mode 100644 index 0000000..cf7fb41 --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_h_pr.s @@ -0,0 +1,74 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_pr/c_ldimmhalf_h_pr.dsp +// Spec Reference: ldimmhalf h preg +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS -1; + INIT_P_REGS -1; + imm32 sp, 0xffffffff; + imm32 fp, 0xffffffff; + +// test Preg + P1.H = 0x0002; + P2.H = 0x0004; + P3.H = 0x0006; + P4.H = 0x0008; + P5.H = 0x000a; + FP.H = 0x000c; + SP.H = 0x000e; + CHECKREG p1, 0x0002ffff; + CHECKREG p2, 0x0004ffff; + CHECKREG p3, 0x0006ffff; + CHECKREG p4, 0x0008ffff; + CHECKREG p5, 0x000affff; + CHECKREG fp, 0x000cffff; + CHECKREG sp, 0x000effff; + + P1.H = 0x0020; + P2.H = 0x0040; + P3.H = 0x0060; + P4.H = 0x0080; + P5.H = 0x00a0; + FP.H = 0x00c0; + SP.H = 0x00e0; + CHECKREG p1, 0x0020ffff; + CHECKREG p2, 0x0040ffff; + CHECKREG p3, 0x0060ffff; + CHECKREG p4, 0x0080ffff; + CHECKREG p5, 0x00a0ffff; + CHECKREG fp, 0x00c0ffff; + CHECKREG sp, 0x00e0ffff; + + P1.H = 0x0200; + P2.H = 0x0400; + P3.H = 0x0600; + P4.H = 0x0800; + P5.H = 0x0a00; + FP.H = 0x0c00; + SP.H = 0x0e00; + CHECKREG p1, 0x0200ffff; + CHECKREG p2, 0x0400ffff; + CHECKREG p3, 0x0600ffff; + CHECKREG p4, 0x0800ffff; + CHECKREG p5, 0x0a00ffff; + CHECKREG fp, 0x0c00ffff; + CHECKREG sp, 0x0e00ffff; + + P1.H = 0x2000; + P2.H = 0x4000; + P3.H = 0x6000; + P4.H = 0x8000; + P5.H = 0xa000; + FP.H = 0xc000; + SP.H = 0xe000; + CHECKREG p1, 0x2000ffff; + CHECKREG p2, 0x4000ffff; + CHECKREG p3, 0x6000ffff; + CHECKREG p4, 0x8000ffff; + CHECKREG p5, 0xa000ffff; + CHECKREG fp, 0xc000ffff; + CHECKREG sp, 0xe000ffff; + + pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_l_dr.s b/sim/testsuite/bfin/c_ldimmhalf_l_dr.s new file mode 100644 index 0000000..b47284d --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_l_dr.s @@ -0,0 +1,82 @@ +//Original:/testcases/core/c_ldimmhalf_l_dr/c_ldimmhalf_l_dr.dsp +// Spec Reference: ldimmhalf l dreg +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + + +// test Dreg +R0.L = 0x0001; +R1.L = 0x0003; +R2.L = 0x0005; +R3.L = 0x0007; +R4.L = 0x0009; +R5.L = 0x000b; +R6.L = 0x000d; +R7.L = 0x000f; +CHECKREG r0, 0xffff0001; +CHECKREG r1, 0xffff0003; +CHECKREG r2, 0xffff0005; +CHECKREG r3, 0xffff0007; +CHECKREG r4, 0xffff0009; +CHECKREG r5, 0xffff000b; +CHECKREG r6, 0xffff000d; +CHECKREG r7, 0xffff000f; + +R0.L = 0x0010; +R1.L = 0x0030; +R2.L = 0x0050; +R3.L = 0x0070; +R4.L = 0x0090; +R5.L = 0x00b0; +R6.L = 0x00d0; +R7.L = 0x00f0; +CHECKREG r0, 0xffff0010; +CHECKREG r1, 0xffff0030; +CHECKREG r2, 0xffff0050; +CHECKREG r3, 0xffff0070; +CHECKREG r4, 0xffff0090; +CHECKREG r5, 0xffff00b0; +CHECKREG r6, 0xffff00d0; +CHECKREG r7, 0xffff00f0; + +R0.L = 0x0100; +R1.L = 0x0300; +R2.L = 0x0500; +R3.L = 0x0700; +R4.L = 0x0900; +R5.L = 0x0b00; +R6.L = 0x0d00; +R7.L = 0x0f00; +CHECKREG r0, 0xffff0100; +CHECKREG r1, 0xffff0300; +CHECKREG r2, 0xffff0500; +CHECKREG r3, 0xffff0700; +CHECKREG r4, 0xffff0900; +CHECKREG r5, 0xffff0b00; +CHECKREG r6, 0xffff0d00; +CHECKREG r7, 0xffff0f00; + +R0.L = 0x1000; +R1.L = 0x3000; +R2.L = 0x5000; +R3.L = 0x7000; +R4.L = 0x9000; +R5.L = 0xb000; +R6.L = 0xd000; +R7.L = 0xf000; +CHECKREG r0, 0xffff1000; +CHECKREG r1, 0xffff3000; +CHECKREG r2, 0xffff5000; +CHECKREG r3, 0xffff7000; +CHECKREG r4, 0xffff9000; +CHECKREG r5, 0xffffb000; +CHECKREG r6, 0xffffd000; +CHECKREG r7, 0xfffff000; + +pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_l_ibml.s b/sim/testsuite/bfin/c_ldimmhalf_l_ibml.s new file mode 100644 index 0000000..66f83b0 --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_l_ibml.s @@ -0,0 +1,165 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_ibml/c_ldimmhalf_l_ibml.dsp +// Spec Reference: ldimmhalf l ibml +# mach: bfin + +.include "testutils.inc" + start + + INIT_I_REGS -1; + INIT_L_REGS -1; + INIT_M_REGS -1; + INIT_B_REGS -1; + + I0.L = 0x2001; + I1.L = 0x2003; + I2.L = 0x2005; + I3.L = 0x2007; + L0.L = 0x2009; + L1.L = 0x200b; + L2.L = 0x200d; + L3.L = 0x200f; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0xffff2001; + CHECKREG r1, 0xffff2003; + CHECKREG r2, 0xffff2005; + CHECKREG r3, 0xffff2007; + CHECKREG r4, 0xffff2009; + CHECKREG r5, 0xffff200b; + CHECKREG r6, 0xffff200d; + CHECKREG r7, 0xffff200f; + + I0.L = 0x0111; + I1.L = 0x1111; + I2.L = 0x2222; + I3.L = 0x3333; + L0.L = 0x4444; + L1.L = 0x5555; + L2.L = 0x6666; + L3.L = 0x7777; + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0xffff0111; + CHECKREG r1, 0xffff1111; + CHECKREG r2, 0xffff2222; + CHECKREG r3, 0xffff3333; + CHECKREG r4, 0xffff4444; + CHECKREG r5, 0xffff5555; + CHECKREG r6, 0xffff6666; + CHECKREG r7, 0xffff7777; + + I0.L = 0x8888; + I1.L = 0x9aaa; + I2.L = 0xabbb; + I3.L = 0xbccc; + L0.L = 0xcddd; + L1.L = 0xdeee; + L2.L = 0xefff; + L3.L = 0xf111; + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0xffff8888; + CHECKREG r1, 0xffff9aaa; + CHECKREG r2, 0xffffabbb; + CHECKREG r3, 0xffffbccc; + CHECKREG r4, 0xffffcddd; + CHECKREG r5, 0xffffdeee; + CHECKREG r6, 0xffffefff; + CHECKREG r7, 0xfffff111; + + B0.L = 0x3001; + B1.L = 0x3003; + B2.L = 0x3005; + B3.L = 0x3007; + M0.L = 0x3009; + M1.L = 0x300b; + M2.L = 0x300d; + M3.L = 0x300f; + + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xffff3001; + CHECKREG r1, 0xffff3003; + CHECKREG r2, 0xffff3005; + CHECKREG r3, 0xffff3007; + CHECKREG r4, 0xffff3009; + CHECKREG r5, 0xffff300B; + CHECKREG r6, 0xffff300d; + CHECKREG r7, 0xffff300f; + + B0.L = 0x0110; + B1.L = 0x1110; + B2.L = 0x2220; + B3.L = 0x3330; + M0.L = 0x4440; + M1.L = 0x5550; + M2.L = 0x6660; + M3.L = 0x7770; + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xffff0110; + CHECKREG r1, 0xffff1110; + CHECKREG r2, 0xffff2220; + CHECKREG r3, 0xffff3330; + CHECKREG r4, 0xffff4440; + CHECKREG r5, 0xffff5550; + CHECKREG r6, 0xffff6660; + CHECKREG r7, 0xffff7770; + + B0.L = 0xf880; + B1.L = 0xfaa0; + B2.L = 0xfbb0; + B3.L = 0xfcc0; + M0.L = 0xfdd0; + M1.L = 0xfee0; + M2.L = 0xfff0; + M3.L = 0xf110; + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xfffff880; + CHECKREG r1, 0xfffffaa0; + CHECKREG r2, 0xfffffbb0; + CHECKREG r3, 0xfffffcc0; + CHECKREG r4, 0xfffffdd0; + CHECKREG r5, 0xfffffee0; + CHECKREG r6, 0xfffffff0; + CHECKREG r7, 0xfffff110; + + pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_l_pr.s b/sim/testsuite/bfin/c_ldimmhalf_l_pr.s new file mode 100644 index 0000000..c067862 --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_l_pr.s @@ -0,0 +1,76 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_pr/c_ldimmhalf_l_pr.dsp +// Spec Reference: ldimmhalf l preg +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS -1; + INIT_P_REGS -1; + + imm32 sp, 0xffffffff; + imm32 fp, 0xffffffff; + +// test Preg + P1.L = 0x0003; + P2.L = 0x0005; + P3.L = 0x0007; + P4.L = 0x0009; + P5.L = 0x000b; + FP.L = 0x000d; + SP.L = 0x000f; + CHECKREG p1, 0xffff0003; + CHECKREG p2, 0xffff0005; + CHECKREG p3, 0xffff0007; + CHECKREG p4, 0xffff0009; + CHECKREG p5, 0xffff000b; + CHECKREG fp, 0xffff000d; + CHECKREG sp, 0xffff000f; + + P1.L = 0x0030; + P2.L = 0x0050; + P3.L = 0x0070; + P4.L = 0x0090; + P5.L = 0x00b0; + FP.L = 0x00d0; + SP.L = 0x00f0; +//CHECKREG p0, 0x00000010; + CHECKREG p1, 0xffff0030; + CHECKREG p2, 0xffff0050; + CHECKREG p3, 0xffff0070; + CHECKREG p4, 0xffff0090; + CHECKREG p5, 0xffff00b0; + CHECKREG fp, 0xffff00d0; + CHECKREG sp, 0xffff00f0; + + P1.L = 0x0300; + P2.L = 0x0500; + P3.L = 0x0700; + P4.L = 0x0900; + P5.L = 0x0b00; + FP.L = 0x0d00; + SP.L = 0x0f00; + CHECKREG p1, 0xffff0300; + CHECKREG p2, 0xffff0500; + CHECKREG p3, 0xffff0700; + CHECKREG p4, 0xffff0900; + CHECKREG p5, 0xffff0b00; + CHECKREG fp, 0xffff0d00; + CHECKREG sp, 0xffff0f00; + + P1.L = 0x3000; + P2.L = 0x5000; + P3.L = 0x7000; + P4.L = 0x9000; + P5.L = 0xb000; + FP.L = 0xd000; + SP.L = 0xf000; + CHECKREG p1, 0xffff3000; + CHECKREG p2, 0xffff5000; + CHECKREG p3, 0xffff7000; + CHECKREG p4, 0xffff9000; + CHECKREG p5, 0xffffb000; + CHECKREG fp, 0xffffd000; + CHECKREG sp, 0xfffff000; + + pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_lz_dr.s b/sim/testsuite/bfin/c_ldimmhalf_lz_dr.s new file mode 100644 index 0000000..a2ae95f --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_lz_dr.s @@ -0,0 +1,81 @@ +//Original:/testcases/core/c_ldimmhalf_lz_dr/c_ldimmhalf_lz_dr.dsp +// Spec Reference: ldimmhalf lz dreg +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS -1; + + +// test Dreg +R0 = 0x0001 (Z); +R1 = 0x0003 (Z); +R2 = 0x0005 (Z); +R3 = 0x0007 (Z); +R4 = 0x0009 (Z); +R5 = 0x000b (Z); +R6 = 0x000d (Z); +R7 = 0x000f (Z); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0x00000005; +CHECKREG r3, 0x00000007; +CHECKREG r4, 0x00000009; +CHECKREG r5, 0x0000000b; +CHECKREG r6, 0x0000000d; +CHECKREG r7, 0x0000000f; + +R0 = 0x0010 (Z); +R1 = 0x0030 (Z); +R2 = 0x0050 (Z); +R3 = 0x0070 (Z); +R4 = 0x0090 (Z); +R5 = 0x00b0 (Z); +R6 = 0x00d0 (Z); +R7 = 0x00f0 (Z); +CHECKREG r0, 0x00000010; +CHECKREG r1, 0x00000030; +CHECKREG r2, 0x00000050; +CHECKREG r3, 0x00000070; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0x000000b0; +CHECKREG r6, 0x000000d0; +CHECKREG r7, 0x000000f0; + +R0 = 0x0100 (Z); +R1 = 0x0300 (Z); +R2 = 0x0500 (Z); +R3 = 0x0700 (Z); +R4 = 0x0900 (Z); +R5 = 0x0b00 (Z); +R6 = 0x0d00 (Z); +R7 = 0x0f00 (Z); +CHECKREG r0, 0x00000100; +CHECKREG r1, 0x00000300; +CHECKREG r2, 0x00000500; +CHECKREG r3, 0x00000700; +CHECKREG r4, 0x00000900; +CHECKREG r5, 0x00000b00; +CHECKREG r6, 0x00000d00; +CHECKREG r7, 0x00000f00; + +R0 = 0x1000 (Z); +R1 = 0x3000 (Z); +R2 = 0x5000 (Z); +R3 = 0x7000 (Z); +R4 = 0x9000 (Z); +R5 = 0xb000 (Z); +R6 = 0xd000 (Z); +R7 = 0xf000 (Z); +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00003000; +CHECKREG r2, 0x00005000; +CHECKREG r3, 0x00007000; +CHECKREG r4, 0x00009000; +CHECKREG r5, 0x0000b000; +CHECKREG r6, 0x0000d000; +CHECKREG r7, 0x0000f000; + +pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_lz_ibml.s b/sim/testsuite/bfin/c_ldimmhalf_lz_ibml.s new file mode 100644 index 0000000..efe77ae --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_lz_ibml.s @@ -0,0 +1,168 @@ +//Original:/testcases/core/c_ldimmhalf_lz_ibml/c_ldimmhalf_lz_ibml.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: ldimmhalf lz ibml + + + + +I0 = 0x2001 (Z); +I1 = 0x2003 (Z); +I2 = 0x2005 (Z); +I3 = 0x2007 (Z); +L0 = 0x2009 (Z); +L1 = 0x200b (Z); +L2 = 0x200d (Z); +L3 = 0x200f (Z); + + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x00002001; +CHECKREG r1, 0x00002003; +CHECKREG r2, 0x00002005; +CHECKREG r3, 0x00002007; +CHECKREG r4, 0x00002009; +CHECKREG r5, 0x0000200b; +CHECKREG r6, 0x0000200d; +CHECKREG r7, 0x0000200f; + +I0 = 0x0111 (Z); +I1 = 0x1111 (Z); +I2 = 0x2222 (Z); +I3 = 0x3333 (Z); +L0 = 0x4444 (Z); +L1 = 0x5555 (Z); +L2 = 0x6666 (Z); +L3 = 0x7777 (Z); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x00000111; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00002222; +CHECKREG r3, 0x00003333; +CHECKREG r4, 0x00004444; +CHECKREG r5, 0x00005555; +CHECKREG r6, 0x00006666; +CHECKREG r7, 0x00007777; + +I0 = 0x8888 (Z); +I1 = 0x9aaa (Z); +I2 = 0xabbb (Z); +I3 = 0xbccc (Z); +L0 = 0xcddd (Z); +L1 = 0xdeee (Z); +L2 = 0xefff (Z); +L3 = 0xf111 (Z); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x00008888; +CHECKREG r1, 0x00009aaa; +CHECKREG r2, 0x0000abbb; +CHECKREG r3, 0x0000bccc; +CHECKREG r4, 0x0000cddd; +CHECKREG r5, 0x0000deee; +CHECKREG r6, 0x0000efff; +CHECKREG r7, 0x0000f111; + +B0 = 0x3001 (Z); +B1 = 0x3003 (Z); +B2 = 0x3005 (Z); +B3 = 0x3007 (Z); +M0 = 0x3009 (Z); +M1 = 0x300b (Z); +M2 = 0x300d (Z); +M3 = 0x300f (Z); + +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00003001; +CHECKREG r1, 0x00003003; +CHECKREG r2, 0x00003005; +CHECKREG r3, 0x00003007; +CHECKREG r4, 0x00003009; +CHECKREG r5, 0x0000300B; +CHECKREG r6, 0x0000300d; +CHECKREG r7, 0x0000300f; + + +B0 = 0x0110 (Z); +B1 = 0x1110 (Z); +B2 = 0x2220 (Z); +B3 = 0x3330 (Z); +M0 = 0x4440 (Z); +M1 = 0x5550 (Z); +M2 = 0x6660 (Z); +M3 = 0x7770 (Z); +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00000110; +CHECKREG r1, 0x00001110; +CHECKREG r2, 0x00002220; +CHECKREG r3, 0x00003330; +CHECKREG r4, 0x00004440; +CHECKREG r5, 0x00005550; +CHECKREG r6, 0x00006660; +CHECKREG r7, 0x00007770; + +B0 = 0xf880 (Z); +B1 = 0xfaa0 (Z); +B2 = 0xfbb0 (Z); +B3 = 0xfcc0 (Z); +M0 = 0xfdd0 (Z); +M1 = 0xfee0 (Z); +M2 = 0xfff0 (Z); +M3 = 0xf110 (Z); +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x0000f880; +CHECKREG r1, 0x0000faa0; +CHECKREG r2, 0x0000fbb0; +CHECKREG r3, 0x0000fcc0; +CHECKREG r4, 0x0000fdd0; +CHECKREG r5, 0x0000fee0; +CHECKREG r6, 0x0000fff0; +CHECKREG r7, 0x0000f110; + + +pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_lz_pr.s b/sim/testsuite/bfin/c_ldimmhalf_lz_pr.s new file mode 100644 index 0000000..23d3191 --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_lz_pr.s @@ -0,0 +1,72 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lz_pr/c_ldimmhalf_lz_pr.dsp +// Spec Reference: ldimmhalf lz preg +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS -1; + +// test Preg + P1 = 0x0003 (Z); + P2 = 0x0005 (Z); + P3 = 0x0007 (Z); + P4 = 0x0009 (Z); + P5 = 0x000b (Z); + FP = 0x000d (Z); + SP = 0x000f (Z); + CHECKREG p1, 0x00000003; + CHECKREG p2, 0x00000005; + CHECKREG p3, 0x00000007; + CHECKREG p4, 0x00000009; + CHECKREG p5, 0x0000000b; + CHECKREG fp, 0x0000000d; + CHECKREG sp, 0x0000000f; + + P1 = 0x0030 (Z); + P2 = 0x0050 (Z); + P3 = 0x0070 (Z); + P4 = 0x0090 (Z); + P5 = 0x00b0 (Z); + FP = 0x00d0 (Z); + SP = 0x00f0 (Z); +//CHECKREG p0, 0x00000010; + CHECKREG p1, 0x00000030; + CHECKREG p2, 0x00000050; + CHECKREG p3, 0x00000070; + CHECKREG p4, 0x00000090; + CHECKREG p5, 0x000000b0; + CHECKREG fp, 0x000000d0; + CHECKREG sp, 0x000000f0; + + P1 = 0x0300 (Z); + P2 = 0x0500 (Z); + P3 = 0x0700 (Z); + P4 = 0x0900 (Z); + P5 = 0x0b00 (Z); + FP = 0x0d00 (Z); + SP = 0x0f00 (Z); + CHECKREG p1, 0x00000300; + CHECKREG p2, 0x00000500; + CHECKREG p3, 0x00000700; + CHECKREG p4, 0x00000900; + CHECKREG p5, 0x00000b00; + CHECKREG fp, 0x00000d00; + CHECKREG sp, 0x00000f00; + + P1 = 0x3000 (Z); + P2 = 0x5000 (Z); + P3 = 0x7000 (Z); + P4 = 0x9000 (Z); + P5 = 0xb000 (Z); + FP = 0xd000 (Z); + SP = 0xf000 (Z); + CHECKREG p1, 0x00003000; + CHECKREG p2, 0x00005000; + CHECKREG p3, 0x00007000; + CHECKREG p4, 0x00009000; + CHECKREG p5, 0x0000b000; + CHECKREG fp, 0x0000d000; + CHECKREG sp, 0x0000f000; + + pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_lzhi_dr.s b/sim/testsuite/bfin/c_ldimmhalf_lzhi_dr.s new file mode 100644 index 0000000..67e652a --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_lzhi_dr.s @@ -0,0 +1,113 @@ +//Original:/testcases/core/c_ldimmhalf_lzhi_dr/c_ldimmhalf_lzhi_dr.dsp +// Spec Reference: ldimmhalf lz & hi dreg +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS -1; + + +// test Dreg +R0 = 0x0001 (Z); +R0.H = 0x0000; +R1 = 0x0003 (Z); +R1.H = 0x0002; +R2 = 0x0005 (Z); +R2.H = 0x0004; +R3 = 0x0007 (Z); +R3.H = 0x0006; +R4 = 0x0009 (Z); +R4.H = 0x0008; +R5 = 0x000b (Z); +R5.H = 0x000a; +R6 = 0x000d (Z); +R6.H = 0x000c; +R7 = 0x000f (Z); +R7.H = 0x000e; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000e000f; + +R0 = 0x0010 (Z); +R0.H = 0x0000; +R1 = 0x0030 (Z); +R1.H = 0x0020; +R2 = 0x0050 (Z); +R2.H = 0x0040; +R3 = 0x0070 (Z); +R3.H = 0x0060; +R4 = 0x0090 (Z); +R4.H = 0x0080; +R5 = 0x00b0 (Z); +R5.H = 0x00a0; +R6 = 0x00d0 (Z); +R6.H = 0x00c0; +R7 = 0x00f0 (Z); +R7.H = 0x00e0; +CHECKREG r0, 0x00000010; +CHECKREG r1, 0x00200030; +CHECKREG r2, 0x00400050; +CHECKREG r3, 0x00600070; +CHECKREG r4, 0x00800090; +CHECKREG r5, 0x00a000b0; +CHECKREG r6, 0x00c000d0; +CHECKREG r7, 0x00e000f0; + +R0 = 0x0100 (Z); +R0.H = 0x0000; +R1 = 0x0300 (Z); +R1.H = 0x0200; +R2 = 0x0500 (Z); +R2.H = 0x0400; +R3 = 0x0700 (Z); +R3.H = 0x0600; +R4 = 0x0900 (Z); +R4.H = 0x0800; +R5 = 0x0b00 (Z); +R5.H = 0x0a00; +R6 = 0x0d00 (Z); +R6.H = 0x0c00; +R7 = 0x0f00 (Z); +R7.H = 0x0e00; +CHECKREG r0, 0x00000100; +CHECKREG r1, 0x02000300; +CHECKREG r2, 0x04000500; +CHECKREG r3, 0x06000700; +CHECKREG r4, 0x08000900; +CHECKREG r5, 0x0a000b00; +CHECKREG r6, 0x0c000d00; +CHECKREG r7, 0x0e000f00; + +R0 = 0x1000 (Z); +R0.H = 0x0000; +R1 = 0x3000 (Z); +R1.H = 0x2000; +R2 = 0x5000 (Z); +R2.H = 0x4000; +R3 = 0x7000 (Z); +R3.H = 0x6000; +R4 = 0x9000 (Z); +R4.H = 0x8000; +R5 = 0xb000 (Z); +R5.H = 0xa000; +R6 = 0xd000 (Z); +R6.H = 0xc000; +R7 = 0xf000 (Z); +R7.H = 0xe000; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x20003000; +CHECKREG r2, 0x40005000; +CHECKREG r3, 0x60007000; +CHECKREG r4, 0x80009000; +CHECKREG r5, 0xa000b000; +CHECKREG r6, 0xc000d000; +CHECKREG r7, 0xe000f000; + +pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_lzhi_ibml.s b/sim/testsuite/bfin/c_ldimmhalf_lzhi_ibml.s new file mode 100644 index 0000000..6f5720b --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_lzhi_ibml.s @@ -0,0 +1,216 @@ +//Original:/testcases/core/c_ldimmhalf_lzhi_ibml/c_ldimmhalf_lzhi_ibml.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: ldimmhalf lzhi ibml + + + + +I0 = 0x2001 (Z); +I0.H = 0x2000; +I1 = 0x2003 (Z); +I1.H = 0x2002; +I2 = 0x2005 (Z); +I2.H = 0x2004; +I3 = 0x2007 (Z); +I3.H = 0x2006; +L0 = 0x2009 (Z); +L0.H = 0x2008; +L1 = 0x200b (Z); +L1.H = 0x200a; +L2 = 0x200d (Z); +L2.H = 0x200c; +L3 = 0x200f (Z); +L3.H = 0x200e; + + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x20002001; +CHECKREG r1, 0x20022003; +CHECKREG r2, 0x20042005; +CHECKREG r3, 0x20062007; +CHECKREG r4, 0x20082009; +CHECKREG r5, 0x200a200b; +CHECKREG r6, 0x200c200d; +CHECKREG r7, 0x200e200f; + +I0 = 0x0111 (Z); +I0.H = 0x1000; +I1 = 0x1111 (Z); +I1.H = 0x1000; +I2 = 0x2222 (Z); +I2.H = 0x2000; +I3 = 0x3333 (Z); +I3.H = 0x3000; +L0 = 0x4444 (Z); +L0.H = 0x4000; +L1 = 0x5555 (Z); +L1.H = 0x5000; +L2 = 0x6666 (Z); +L2.H = 0x6000; +L3 = 0x7777 (Z); +L3.H = 0x7000; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x10000111; +CHECKREG r1, 0x10001111; +CHECKREG r2, 0x20002222; +CHECKREG r3, 0x30003333; +CHECKREG r4, 0x40004444; +CHECKREG r5, 0x50005555; +CHECKREG r6, 0x60006666; +CHECKREG r7, 0x70007777; + +I0 = 0x8888 (Z); +I0.H = 0x8000; +I1 = 0x9aaa (Z); +I1.H = 0x9000; +I2 = 0xabbb (Z); +I2.H = 0xa000; +I3 = 0xbccc (Z); +I3.H = 0xb000; +L0 = 0xcddd (Z); +L0.H = 0xc000; +L1 = 0xdeee (Z); +L1.H = 0xd000; +L2 = 0xefff (Z); +L2.H = 0xe000; +L3 = 0xf111 (Z); +L3.H = 0xf000; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x80008888; +CHECKREG r1, 0x90009aaa; +CHECKREG r2, 0xa000abbb; +CHECKREG r3, 0xb000bccc; +CHECKREG r4, 0xc000cddd; +CHECKREG r5, 0xd000deee; +CHECKREG r6, 0xe000efff; +CHECKREG r7, 0xf000f111; + +B0 = 0x3001 (Z); +B0.H = 0x3000; +B1 = 0x3003 (Z); +B1.H = 0x3002; +B2 = 0x3005 (Z); +B2.H = 0x3004; +B3 = 0x3007 (Z); +B3.H = 0x3006; +M0 = 0x3009 (Z); +M0.H = 0x3008; +M1 = 0x300b (Z); +M1.H = 0x300a; +M2 = 0x300d (Z); +M2.H = 0x300c; +M3 = 0x300f (Z); +M3.H = 0x300e; + +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x30003001; +CHECKREG r1, 0x30023003; +CHECKREG r2, 0x30043005; +CHECKREG r3, 0x30063007; +CHECKREG r4, 0x30083009; +CHECKREG r5, 0x300A300B; +CHECKREG r6, 0x300c300d; +CHECKREG r7, 0x300e300f; + + +B0 = 0x0110 (Z); +B0.H = 0x1000; +B1 = 0x1110 (Z); +B1.H = 0x1000; +B2 = 0x2220 (Z); +B2.H = 0x2000; +B3 = 0x3330 (Z); +B3.H = 0x3000; +M0 = 0x4440 (Z); +M0.H = 0x4000; +M1 = 0x5550 (Z); +M1.H = 0x5000; +M2 = 0x6660 (Z); +M2.H = 0x6000; +M3 = 0x7770 (Z); +M3.H = 0x7000; +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x10000110; +CHECKREG r1, 0x10001110; +CHECKREG r2, 0x20002220; +CHECKREG r3, 0x30003330; +CHECKREG r4, 0x40004440; +CHECKREG r5, 0x50005550; +CHECKREG r6, 0x60006660; +CHECKREG r7, 0x70007770; + +B0 = 0xf880 (Z); +B0.H = 0x8000; +B1 = 0xfaa0 (Z); +B1.H = 0xa000; +B2 = 0xfbb0 (Z); +B2.H = 0xb000; +B3 = 0xfcc0 (Z); +B3.H = 0xc000; +M0 = 0xfdd0 (Z); +M0.H = 0xd000; +M1 = 0xfee0 (Z); +M1.H = 0xe000; +M2 = 0xfff0 (Z); +M2.H = 0xf000; +M3 = 0xf110 (Z); +M3.H = 0x1000; +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x8000f880; +CHECKREG r1, 0xa000faa0; +CHECKREG r2, 0xb000fbb0; +CHECKREG r3, 0xc000fcc0; +CHECKREG r4, 0xd000fdd0; +CHECKREG r5, 0xe000fee0; +CHECKREG r6, 0xf000fff0; +CHECKREG r7, 0x1000f110; + + +pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_lzhi_pr.s b/sim/testsuite/bfin/c_ldimmhalf_lzhi_pr.s new file mode 100644 index 0000000..9276d36 --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_lzhi_pr.s @@ -0,0 +1,102 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lzhi_pr/c_ldimmhalf_lzhi_pr.dsp +// Spec Reference: ldimmhalf lzhi preg +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS -1; + +// test Preg +//lz(p0)=0x0001; +//h(p0) =0x0000; + P1 = 0x0003 (Z); + P1.H = 0x0002; + P2 = 0x0005 (Z); + P2.H = 0x0004; + P3 = 0x0007 (Z); + P3.H = 0x0006; + P4 = 0x0009 (Z); + P4.H = 0x0008; + P5 = 0x000b (Z); + P5.H = 0x000a; + FP = 0x000d (Z); + FP.H = 0x000c; + SP = 0x000f (Z); + SP.H = 0x000e; + CHECKREG p1, 0x00020003; + CHECKREG p2, 0x00040005; + CHECKREG p3, 0x00060007; + CHECKREG p4, 0x00080009; + CHECKREG p5, 0x000a000b; + CHECKREG fp, 0x000c000d; + CHECKREG sp, 0x000e000f; + + P1 = 0x0030 (Z); + P1.H = 0x0020; + P2 = 0x0050 (Z); + P2.H = 0x0040; + P3 = 0x0070 (Z); + P3.H = 0x0060; + P4 = 0x0090 (Z); + P4.H = 0x0080; + P5 = 0x00b0 (Z); + P5.H = 0x00a0; + FP = 0x00d0 (Z); + FP.H = 0x00c0; + SP = 0x00f0 (Z); + SP.H = 0x00e0; +//CHECKREG p0, 0x00000010; + CHECKREG p1, 0x00200030; + CHECKREG p2, 0x00400050; + CHECKREG p3, 0x00600070; + CHECKREG p4, 0x00800090; + CHECKREG p5, 0x00a000b0; + CHECKREG fp, 0x00c000d0; + CHECKREG sp, 0x00e000f0; + + P1 = 0x0300 (Z); + P1.H = 0x0200; + P2 = 0x0500 (Z); + P2.H = 0x0400; + P3 = 0x0700 (Z); + P3.H = 0x0600; + P4 = 0x0900 (Z); + P4.H = 0x0800; + P5 = 0x0b00 (Z); + P5.H = 0x0a00; + FP = 0x0d00 (Z); + FP.H = 0x0c00; + SP = 0x0f00 (Z); + SP.H = 0x0e00; + CHECKREG p1, 0x02000300; + CHECKREG p2, 0x04000500; + CHECKREG p3, 0x06000700; + CHECKREG p4, 0x08000900; + CHECKREG p5, 0x0a000b00; + CHECKREG fp, 0x0c000d00; + CHECKREG sp, 0x0e000f00; + + P1 = 0x3000 (Z); + P1.H = 0x2000; + P2 = 0x5000 (Z); + P2.H = 0x4000; + P3 = 0x7000 (Z); + P3.H = 0x6000; + P4 = 0x9000 (Z); + P4.H = 0x8000; + P5 = 0xb000 (Z); + P5.H = 0xa000; + FP = 0xd000 (Z); + FP.H = 0xc000; + SP = 0xf000 (Z); + SP.H = 0xe000; + CHECKREG p1, 0x20003000; + CHECKREG p2, 0x40005000; + CHECKREG p3, 0x60007000; + CHECKREG p4, 0x80009000; + CHECKREG p5, 0xa000b000; + CHECKREG fp, 0xc000d000; + CHECKREG sp, 0xe000f000; + + pass diff --git a/sim/testsuite/bfin/c_ldimmhalf_pibml.s b/sim/testsuite/bfin/c_ldimmhalf_pibml.s new file mode 100644 index 0000000..a7e8f8b --- /dev/null +++ b/sim/testsuite/bfin/c_ldimmhalf_pibml.s @@ -0,0 +1,212 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_pibml/c_ldimmhalf_pibml.dsp +// Spec Reference: ldimmhalf p i b m l +# mach: bfin + +.include "testutils.inc" + start + +// set all reg=-1 + + +//p0 =0x0123; + P1 = 0x1234 (X); + P2 = 0x2345 (X); + P3 = 0x3456 (X); + P4 = 0x4567 (X); + P5 = 0x5678 (X); + FP = 0x6789 (X); + SP = 0x789a (X); +//CHECKREG p0, 0x00000123; + CHECKREG p1, 0x00001234; + CHECKREG p2, 0x00002345; + CHECKREG p3, 0x00003456; + CHECKREG p4, 0x00004567; + CHECKREG p5, 0x00005678; + CHECKREG fp, 0x00006789; + CHECKREG sp, 0x0000789A; + +//p0 = -32768; + P1 = -32768 (X); + P2 = -2222 (X); + P3 = -3333 (X); + P4 = -4444 (X); + P5 = -5555 (X); + FP = -6666 (X); + SP = -7777 (X); +//CHECKREG r0, 0xFFFF8000; + CHECKREG p1, 0xFFFF8000; + CHECKREG p2, 0xFFFFF752; + CHECKREG p3, 0xFFFFF2FB; + CHECKREG p4, 0xFFFFEEA4; + CHECKREG p5, 0xFFFFEA4D; + CHECKREG fp, 0xFFFFE5F6; + CHECKREG sp, 0xFFFFE19F; + +//p0 =0x0123; + P1 = 0x7abc (X); + P2 = 0x6def (X); + P3 = 0x5f56 (X); + P4 = 0x7dd7 (X); + P5 = 0x4abd (X); + FP = 0x7fff (X); + SP = 0x7ffa (X); +//CHECKREG p0, 0x00000123; + CHECKREG p1, 0x00007abc; + CHECKREG p2, 0x00006def; + CHECKREG p3, 0x00005f56; + CHECKREG p4, 0x00007dd7; + CHECKREG p5, 0x00004abd; + CHECKREG fp, 0x00007fff; + CHECKREG sp, 0x00007ffa; + + I0 = 0x0123 (X); + I1 = 0x1234 (X); + I2 = 0x2345 (X); + I3 = 0x3456 (X); + B0 = 0x0567 (X); + B1 = 0x1678 (X); + B2 = 0x2789 (X); + B3 = 0x389a (X); + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0x00000123; + CHECKREG r1, 0x00001234; + CHECKREG r2, 0x00002345; + CHECKREG r3, 0x00003456; + CHECKREG r4, 0x00000567; + CHECKREG r5, 0x00001678; + CHECKREG r6, 0x00002789; + CHECKREG r7, 0x0000389A; + + I0 = -32768 (X); + I1 = -12345 (X); + I2 = -23456 (X); + I3 = -3456 (X); + B0 = -4567 (X); + B1 = -5678 (X); + B2 = -6678 (X); + B3 = -7012 (X); + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0xFFFF8000; + CHECKREG r1, 0xFFFFCFC7; + CHECKREG r2, 0xFFFFA460; + CHECKREG r3, 0xFFFFF280; + CHECKREG r4, 0xFFFFEE29; + CHECKREG r5, 0xFFFFE9D2; + CHECKREG r6, 0xFFFFE5EA; + CHECKREG r7, 0xFFFFE49C; + + I0 = 0x7abd (X); + I1 = 0x7bf4 (X); + I2 = 0x6c45 (X); + I3 = 0x7d56 (X); + B0 = 0x7e67 (X); + B1 = 0x7f78 (X); + B2 = 0x7ff9 (X); + B3 = 0x7fff (X); + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0x00007abd; + CHECKREG r1, 0x00007bf4; + CHECKREG r2, 0x00006c45; + CHECKREG r3, 0x00007d56; + CHECKREG r4, 0x00007e67; + CHECKREG r5, 0x00007f78; + CHECKREG r6, 0x00007ff9; + CHECKREG r7, 0x00007fff; + + M0 = 0x7123 (X); + M1 = 0x7234 (X); + M2 = 0x7345 (X); + M3 = 0x7456 (X); + L0 = 0x7567 (X); + L1 = 0x7678 (X); + L2 = 0x7789 (X); + L3 = 0x789a (X); + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x00007123; + CHECKREG r1, 0x00007234; + CHECKREG r2, 0x00007345; + CHECKREG r3, 0x00007456; + CHECKREG r4, 0x00007567; + CHECKREG r5, 0x00007678; + CHECKREG r6, 0x00007789; + CHECKREG r7, 0x0000789A; + + M0 = -32768 (X); + M1 = -123 (X); + M2 = -234 (X); + M3 = -345 (X); + L0 = -456 (X); + L1 = -567 (X); + L2 = -667 (X); + L3 = -701 (X); + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0xFFFF8000; + CHECKREG r1, 0xFFFFFF85; + CHECKREG r2, 0xFFFFFF16; + CHECKREG r3, 0xFFFFFEA7; + CHECKREG r4, 0xFFFFFE38; + CHECKREG r5, 0xFFFFFDC9; + CHECKREG r6, 0xFFFFFD65; + CHECKREG r7, 0xFFFFFD43; + + M0 = 0x7aaa (X); + M1 = 0x7bbb (X); + M2 = 0x7ccc (X); + M3 = 0x7ddd (X); + L0 = 0x7eee (X); + L1 = 0x7fa8 (X); + L2 = 0x7fb9 (X); + L3 = 0x7fcc (X); + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x00007aaa; + CHECKREG r1, 0x00007bbb; + CHECKREG r2, 0x00007ccc; + CHECKREG r3, 0x00007ddd; + CHECKREG r4, 0x00007eee; + CHECKREG r5, 0x00007fa8; + CHECKREG r6, 0x00007fb9; + CHECKREG r7, 0x00007fcc; + + pass diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p.s b/sim/testsuite/bfin/c_ldst_ld_d_p.s new file mode 100644 index 0000000..1183e44 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p.s @@ -0,0 +1,372 @@ +//Original:/testcases/core/c_ldst_ld_d_p/c_ldst_ld_d_p.dsp +// Spec Reference: c_ldst ld d [p] +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ P5 ]; + R6 = [ FP ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x80818283; + CHECKREG r6, 0x00010203; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + R7 = [ P1 ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + R7 = [ P1 ]; + R0 = [ P2 ]; + CHECKREG r0, 0x20212223; + CHECKREG r1, 0x20212223; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + R7 = [ P1 ]; + R0 = [ P2 ]; + CHECKREG r0, 0x20212223; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R4 = [ P5 ]; + R5 = [ FP ]; + R7 = [ P1 ]; + R0 = [ P2 ]; + R2 = [ P4 ]; + CHECKREG r0, 0x20212223; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R5 = [ FP ]; + R7 = [ P1 ]; + R0 = [ P2 ]; + R2 = [ P4 ]; + R3 = [ P5 ]; + CHECKREG r0, 0x20212223; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x80818283; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R7 = [ P1 ]; + R0 = [ P2 ]; + R2 = [ P4 ]; + R3 = [ P5 ]; + R4 = [ FP ]; + CHECKREG r0, 0x20212223; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x80818283; + CHECKREG r4, 0x00010203; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R7 = [ P1 ]; + R0 = [ P2 ]; + R2 = [ P4 ]; + R3 = [ P5 ]; + R4 = [ FP ]; + CHECKREG r0, 0x20212223; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x80818283; + CHECKREG r4, 0x00010203; + CHECKREG r6, 0x00010203; + CHECKREG r7, 0x00010203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_b.s b/sim/testsuite/bfin/c_ldst_ld_d_p_b.s new file mode 100644 index 0000000..369bb6d --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_b.s @@ -0,0 +1,353 @@ +//Original:/testcases/core/c_ldst_ld_d_p_b/c_ldst_ld_d_p_b.dsp +// Spec Reference: c_ldst ld d [p] b +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// load 8 bits from memory, and zero extend into 32-bit reg + R0 = B [ P1 ] (Z); + R1 = B [ P2 ] (Z); +.ifndef BFIN_HOST + R2 = B [ P3 ] (Z); +.else + R2 = 0x43 (Z); +.endif + R3 = B [ P4 ] (Z); + R4 = B [ P5 ] (Z); + R5 = B [ P5 ] (Z); + R6 = B [ FP ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000063; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000083; + CHECKREG r6, 0x00000003; + R1 = B [ P2 ] (Z); +.ifndef BFIN_HOST + R2 = B [ P3 ] (Z); +.else + R2 = 0x43 (Z); +.endif + R3 = B [ P4 ] (Z); + R4 = B [ P5 ] (Z); + R5 = B [ FP ] (Z); + R7 = B [ P1 ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000063; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; +.ifndef BFIN_HOST + R2 = B [ P3 ] (Z); +.else + R2 = 0x43 (Z); +.endif + R3 = B [ P4 ] (Z); + R4 = B [ P5 ] (Z); + R5 = B [ FP ] (Z); + R7 = B [ P1 ] (Z); + R0 = B [ P2 ] (Z); + CHECKREG r0, 0x00000023; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000063; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + R3 = B [ P4 ] (Z); + R4 = B [ P5 ] (Z); + R5 = B [ FP ] (Z); + R7 = B [ P1 ] (Z); + R0 = B [ P2 ] (Z); +.ifndef BFIN_HOST + R1 = B [ P3 ] (Z); +.else + R1 = 0x43; +.endif + CHECKREG r0, 0x00000023; + CHECKREG r1, 0x00000043; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000063; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_h.s b/sim/testsuite/bfin/c_ldst_ld_d_p_h.s new file mode 100644 index 0000000..fb68de5 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_h.s @@ -0,0 +1,351 @@ +//Original:/testcases/core/c_ldst_ld_d_p_h/c_ldst_ld_d_p_h.dsp +// Spec Reference: c_ldst ld d [p] h +# mach: bfin + +.include "testutils.inc" + start + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// load 16 bits from memory and zero extend into 32-bit reg + R0 = W [ P1 ] (Z); + R1 = W [ P2 ] (Z); +.ifndef BFIN_HOST + R2 = W [ P3 ] (Z); +.else + R2 = 0x4243(Z); +.endif + R3 = W [ P4 ] (Z); + R4 = W [ P5 ] (Z); + R5 = W [ P5 ] (Z); + R6 = W [ FP ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00008283; + CHECKREG r6, 0x00000203; + R1 = W [ P2 ] (Z); +.ifndef BFIN_HOST + R2 = W [ P3 ] (Z); +.else + R2 = 0x4243 (Z); +.endif + R3 = W [ P4 ] (Z); + R4 = W [ P5 ] (Z); + R5 = W [ FP ] (Z); + R7 = W [ P1 ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; +.ifndef BFIN_HOST + R2 = W [ P3 ] (Z); +.else + R2 = 0x4243 (Z); +.endif + R3 = W [ P4 ] (Z); + R4 = W [ P5 ] (Z); + R5 = W [ FP ] (Z); + R7 = W [ P1 ] (Z); + R0 = W [ P2 ] (Z); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + R3 = W [ P4 ] (Z); + R4 = W [ P5 ] (Z); + R5 = W [ FP ] (Z); + R7 = W [ P1 ] (Z); + R0 = W [ P2 ] (Z); +.ifndef BFIN_HOST + R1 = W [ P3 ] (Z); +.else + R1 = 0x4243 (Z); +.endif + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_mm.s b/sim/testsuite/bfin/c_ldst_ld_d_p_mm.s new file mode 100644 index 0000000..56e49a4 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_mm.s @@ -0,0 +1,417 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm/c_ldst_ld_d_p_mm.dsp +// Spec Reference: c_ldst ld d [p--] +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P5 -- ]; + R1 = [ P1 -- ]; + R2 = [ P2 -- ]; + R3 = [ P3 -- ]; + R4 = [ P4 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r0, 0x11223344; + CHECKREG r1, 0x91929394; + CHECKREG r2, 0xC9CACBCD; + CHECKREG r3, 0xEBECEDEE; + CHECKREG r4, 0x0F101213; + CHECKREG r5, 0x20212223; + CHECKREG r6, 0xA0A1A2A3; + R1 = [ P5 -- ]; + R2 = [ P1 -- ]; + R3 = [ P2 -- ]; + R4 = [ P3 -- ]; + R5 = [ P4 -- ]; + R6 = [ FP -- ]; + R7 = [ SP -- ]; + CHECKREG r0, 0x11223344; + CHECKREG r1, 0x1C1D1E1F; + CHECKREG r2, 0x3C3D3E3F; + CHECKREG r3, 0xC5C6C7C8; + CHECKREG r4, 0x7C7D7E7F; + CHECKREG r5, 0x9C9D9E9F; + CHECKREG r6, 0x1C1D1E1F; + CHECKREG r7, 0x9C9D9E9F; + R2 = [ P5 -- ]; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ FP -- ]; + R0 = [ SP -- ]; + CHECKREG r0, 0x98999A9B; + CHECKREG r1, 0x1C1D1E1F; + CHECKREG r2, 0x18191A1B; + CHECKREG r3, 0x38393A3B; + CHECKREG r4, 0x58595A5B; + CHECKREG r5, 0x78797A7B; + CHECKREG r6, 0x98999A9B; + CHECKREG r7, 0x18191A1B; + + R3 = [ P5 -- ]; + R4 = [ P1 -- ]; + R5 = [ P2 -- ]; + R6 = [ P3 -- ]; + R7 = [ P4 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r0, 0x14151617; + CHECKREG r1, 0x94959697; + CHECKREG r2, 0x18191A1B; + CHECKREG r3, 0x14151617; + CHECKREG r4, 0x34353637; + CHECKREG r5, 0x54555657; + CHECKREG r6, 0x74757677; + CHECKREG r7, 0x94959697; + + R4 = [ P5 -- ]; + R5 = [ P1 -- ]; + R6 = [ P2 -- ]; + R7 = [ P3 -- ]; + R0 = [ P4 -- ]; + R1 = [ FP -- ]; + R2 = [ SP -- ]; + CHECKREG r0, 0x90919293; + CHECKREG r1, 0x10111213; + CHECKREG r2, 0x90919293; + CHECKREG r3, 0x14151617; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x30313233; + CHECKREG r6, 0x50515253; + CHECKREG r7, 0x70717273; + + R5 = [ P5 -- ]; + R6 = [ P1 -- ]; + R7 = [ P2 -- ]; + R0 = [ P3 -- ]; + R1 = [ P4 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + CHECKREG r0, 0x6C6D6E6F; + CHECKREG r1, 0x8C8D8E8F; + CHECKREG r2, 0x0C0D0E0F; + CHECKREG r3, 0x8C8D8E8F; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x0C0D0E0F; + CHECKREG r6, 0x2C2D2E2F; + CHECKREG r7, 0x4C4D4E4F; + + R6 = [ P5 -- ]; + R7 = [ P1 -- ]; + R0 = [ P2 -- ]; + R1 = [ P3 -- ]; + R2 = [ P4 -- ]; + R3 = [ FP -- ]; + R4 = [ SP -- ]; + CHECKREG r0, 0x48494A4B; + CHECKREG r1, 0x68696A6B; + CHECKREG r2, 0x88898A8B; + CHECKREG r3, 0x08090A0B; + CHECKREG r4, 0x88898A8B; + CHECKREG r5, 0x0C0D0E0F; + CHECKREG r6, 0x08090A0B; + CHECKREG r7, 0x28292A2B; + + R7 = [ P5 -- ]; + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ FP -- ]; + R5 = [ SP -- ]; + CHECKREG r0, 0x24252627; + CHECKREG r1, 0x44454647; + CHECKREG r2, 0x64656667; + CHECKREG r3, 0x84858687; + CHECKREG r4, 0x04050607; + CHECKREG r5, 0x84858687; + CHECKREG r6, 0x08090A0B; + CHECKREG r7, 0x04050607; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_mm_b.s b/sim/testsuite/bfin/c_ldst_ld_d_p_mm_b.s new file mode 100644 index 0000000..f571553 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_mm_b.s @@ -0,0 +1,353 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm_b/c_ldst_ld_d_p_mm_b.dsp +// Spec Reference: c_ldst ld d [p--] b +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x14; + loadsym p1, DATA_ADDR_2, 0x14; + loadsym p2, DATA_ADDR_3, 0x14; + loadsym i1, DATA_ADDR_4, 0x14; + loadsym p4, DATA_ADDR_5, 0x14; + loadsym fp, DATA_ADDR_6, 0x14; + loadsym i3, DATA_ADDR_7, 0x14; + P3 = I1; SP = I3; + + R0 = B [ P5 -- ] (Z); + R1 = B [ P1 -- ] (Z); + R2 = B [ P2 -- ] (Z); + R3 = B [ P3 -- ] (Z); + R4 = B [ P4 -- ] (Z); + R5 = B [ FP -- ] (Z); + R6 = B [ SP -- ] (Z); + CHECKREG r0, 0x00000017; + CHECKREG r1, 0x00000037; + CHECKREG r2, 0x00000057; + CHECKREG r3, 0x00000077; + CHECKREG r4, 0x00000097; + CHECKREG r5, 0x00000017; + CHECKREG r6, 0x00000097; + R1 = B [ P5 -- ] (Z); + R2 = B [ P1 -- ] (Z); + R3 = B [ P2 -- ] (Z); + R4 = B [ P3 -- ] (Z); + R5 = B [ P4 -- ] (Z); + R6 = B [ FP -- ] (Z); + R7 = B [ SP -- ] (Z); + CHECKREG r0, 0x00000017; + CHECKREG r1, 0x00000010; + CHECKREG r2, 0x00000030; + CHECKREG r3, 0x00000050; + CHECKREG r4, 0x00000070; + CHECKREG r5, 0x00000090; + CHECKREG r6, 0x00000010; + CHECKREG r7, 0x00000090; + R2 = B [ P5 -- ] (Z); + R3 = B [ P1 -- ] (Z); + R4 = B [ P2 -- ] (Z); + R5 = B [ P3 -- ] (Z); + R6 = B [ P4 -- ] (Z); + R7 = B [ FP -- ] (Z); + R0 = B [ SP -- ] (Z); + CHECKREG r0, 0x00000091; + CHECKREG r1, 0x00000010; + CHECKREG r2, 0x00000011; + CHECKREG r3, 0x00000031; + CHECKREG r4, 0x00000051; + CHECKREG r5, 0x00000071; + CHECKREG r6, 0x00000091; + CHECKREG r7, 0x00000011; + + R3 = B [ P5 -- ] (Z); + R4 = B [ P1 -- ] (Z); + R5 = B [ P2 -- ] (Z); + R6 = B [ P3 -- ] (Z); + R7 = B [ P4 -- ] (Z); + R0 = B [ FP -- ] (Z); + R1 = B [ SP -- ] (Z); + CHECKREG r0, 0x00000012; + CHECKREG r1, 0x00000092; + CHECKREG r2, 0x00000011; + CHECKREG r3, 0x00000012; + CHECKREG r4, 0x00000032; + CHECKREG r5, 0x00000052; + CHECKREG r6, 0x00000072; + CHECKREG r7, 0x00000092; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_mm_h.s b/sim/testsuite/bfin/c_ldst_ld_d_p_mm_h.s new file mode 100644 index 0000000..207f93a --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_mm_h.s @@ -0,0 +1,330 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm_h/c_ldst_ld_d_p_mm_h.dsp +// Spec Reference: c_ldst ld d [p--] h +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + +// initial values + loadsym p5, DATA_ADDR_1, 0x10; + loadsym p1, DATA_ADDR_2, 0x10; + loadsym p2, DATA_ADDR_3, 0x10; + loadsym p4, DATA_ADDR_5, 0x10; + loadsym fp, DATA_ADDR_6, 0x10; + + R0 = W [ P5 -- ] (Z); + R1 = W [ P1 -- ] (Z); + R2 = W [ P2 -- ] (Z); + R4 = W [ P4 -- ] (Z); + R5 = W [ FP -- ] (Z); + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00003233; + CHECKREG r2, 0x00005253; + CHECKREG r4, 0x00009293; + CHECKREG r5, 0x00001213; + R1 = W [ P5 -- ] (Z); + R2 = W [ P1 -- ] (Z); + R3 = W [ P2 -- ] (Z); + R5 = W [ P4 -- ] (Z); + R6 = W [ FP -- ] (Z); + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00000C0D; + CHECKREG r2, 0x00002C2D; + CHECKREG r3, 0x00004C4D; + CHECKREG r5, 0x00008C8D; + CHECKREG r6, 0x00000C0D; + R2 = W [ P5 -- ] (Z); + R3 = W [ P1 -- ] (Z); + R4 = W [ P2 -- ] (Z); + R6 = W [ P4 -- ] (Z); + R7 = W [ FP -- ] (Z); + CHECKREG r1, 0x00000C0D; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00002E2F; + CHECKREG r4, 0x00004E4F; + CHECKREG r6, 0x00008E8F; + CHECKREG r7, 0x00000E0F; + + R3 = W [ P5 -- ] (Z); + R4 = W [ P1 -- ] (Z); + R5 = W [ P2 -- ] (Z); + R7 = W [ P4 -- ] (Z); + R0 = W [ FP -- ] (Z); + CHECKREG r0, 0x00000809; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00002829; + CHECKREG r5, 0x00004849; + CHECKREG r7, 0x00008889; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_mm_xb.s b/sim/testsuite/bfin/c_ldst_ld_d_p_mm_xb.s new file mode 100644 index 0000000..e545ca8 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_mm_xb.s @@ -0,0 +1,341 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm_xb/c_ldst_ld_d_p_mm_xb.dsp +// Spec Reference: c_ldst ld d [p--] xb + +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R5 = B [ P5 -- ] (X); + R6 = B [ P1 -- ] (X); + R7 = B [ P2 -- ] (X); + R0 = B [ P3 -- ] (X); + R1 = B [ P4 -- ] (X); + R2 = B [ FP -- ] (X); + R3 = B [ SP -- ] (X); + CHECKREG r0, 0xFFFFFFEE; + CHECKREG r1, 0x00000013; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0xFFFFFFA3; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000044; + CHECKREG r6, 0xFFFFFF94; + CHECKREG r7, 0xFFFFFFCD; + + R6 = B [ P5 -- ] (X); + R7 = B [ P1 -- ] (X); + R0 = B [ P2 -- ] (X); + R1 = B [ P3 -- ] (X); + R2 = B [ P4 -- ] (X); + R3 = B [ FP -- ] (X); + R4 = B [ SP -- ] (X); + CHECKREG r0, 0xFFFFFFC5; + CHECKREG r1, 0x0000007C; + CHECKREG r2, 0xFFFFFF9C; + CHECKREG r3, 0x0000001C; + CHECKREG r4, 0xFFFFFF9C; + CHECKREG r5, 0x00000044; + CHECKREG r6, 0x0000001C; + CHECKREG r7, 0x0000003C; + + R7 = B [ P5 -- ] (X); + R0 = B [ P1 -- ] (X); + R1 = B [ P2 -- ] (X); + R2 = B [ P3 -- ] (X); + R3 = B [ P4 -- ] (X); + R4 = B [ FP -- ] (X); + R5 = B [ SP -- ] (X); + CHECKREG r0, 0x0000003D; + CHECKREG r1, 0xFFFFFFC6; + CHECKREG r2, 0x0000007D; + CHECKREG r3, 0xFFFFFF9D; + CHECKREG r4, 0x0000001D; + CHECKREG r5, 0xFFFFFF9D; + CHECKREG r6, 0x0000001C; + CHECKREG r7, 0x0000001D; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_mm_xh.s b/sim/testsuite/bfin/c_ldst_ld_d_p_mm_xh.s new file mode 100644 index 0000000..16676a5 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_mm_xh.s @@ -0,0 +1,355 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm_xh/c_ldst_ld_d_p_mm_xh.dsp +// Spec Reference: c_ldst ld d [p++/--] h b xh xb +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x08; + loadsym p1, DATA_ADDR_2, 0x08; + loadsym p2, DATA_ADDR_3, 0x08; + loadsym i1, DATA_ADDR_4, 0x08; + loadsym p4, DATA_ADDR_5, 0x08; + loadsym fp, DATA_ADDR_6, 0x08; + loadsym i3, DATA_ADDR_7, 0x08; + P3 = I1; SP = I3; + + R4 = W [ P5 -- ] (X); + R5 = W [ P1 -- ] (X); + R6 = W [ P2 -- ] (X); + R7 = W [ P3 -- ] (X); + R0 = W [ P4 -- ] (X); + R1 = W [ FP -- ] (X); + R2 = W [ SP -- ] (X); + CHECKREG r0, 0xFFFF8A8B; + CHECKREG r1, 0x00000A0B; + CHECKREG r2, 0xFFFF8A8B; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0x00004A4B; + CHECKREG r7, 0x00006A6B; + + R5 = W [ P5 -- ] (X); + R6 = W [ P1 -- ] (X); + R7 = W [ P2 -- ] (X); + R0 = W [ P3 -- ] (X); + R1 = W [ P4 -- ] (X); + R2 = W [ FP -- ] (X); + R3 = W [ SP -- ] (X); + CHECKREG r0, 0x00006465; + CHECKREG r1, 0xFFFF8485; + CHECKREG r2, 0x00000405; + CHECKREG r3, 0xFFFF8485; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00004445; + + R6 = W [ P5 -- ] (X); + R7 = W [ P1 -- ] (X); + R0 = W [ P2 -- ] (X); + R1 = W [ P3 -- ] (X); + R2 = W [ P4 -- ] (X); + R3 = W [ FP -- ] (X); + R4 = W [ SP -- ] (X); + CHECKREG r0, 0x00004647; + CHECKREG r1, 0x00006667; + CHECKREG r2, 0xFFFF8687; + CHECKREG r3, 0x00000607; + CHECKREG r4, 0xFFFF8687; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00000607; + CHECKREG r7, 0x00002627; + + R7 = W [ P5 -- ] (X); + R0 = W [ P1 -- ] (X); + R1 = W [ P2 -- ] (X); + R2 = W [ P3 -- ] (X); + R3 = W [ P4 -- ] (X); + R4 = W [ FP -- ] (X); + R5 = W [ SP -- ] (X); + CHECKREG r0, 0x00002021; + CHECKREG r1, 0x00004041; + CHECKREG r2, 0x00006061; + CHECKREG r3, 0xFFFF8081; + CHECKREG r4, 0x00000001; + CHECKREG r5, 0xFFFF8081; + CHECKREG r6, 0x00000607; + CHECKREG r7, 0x00000001; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_pp.s b/sim/testsuite/bfin/c_ldst_ld_d_p_pp.s new file mode 100644 index 0000000..c03ed68 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_pp.s @@ -0,0 +1,371 @@ +//Original:/testcases/core/c_ldst_ld_d_p_pp/c_ldst_ld_d_p_pp.dsp +// Spec Reference: c_ldst ld d [p++] +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = [ P5 ++ ]; + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + R1 = [ P5 ++ ]; + R2 = [ P1 ++ ]; + R3 = [ P2 ++ ]; + R5 = [ P4 ++ ]; + R6 = [ FP ++ ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x24252627; + CHECKREG r3, 0x44454647; + CHECKREG r5, 0x84858687; + CHECKREG r6, 0x04050607; + R2 = [ P5 ++ ]; + R3 = [ P1 ++ ]; + R4 = [ P2 ++ ]; + R6 = [ P4 ++ ]; + R7 = [ FP ++ ]; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x28292A2B; + CHECKREG r4, 0x48494A4B; + CHECKREG r6, 0x88898A8B; + CHECKREG r7, 0x08090A0B; + + R3 = [ P5 ++ ]; + R4 = [ P1 ++ ]; + R5 = [ P2 ++ ]; + R7 = [ P4 ++ ]; + R0 = [ FP ++ ]; + CHECKREG r0, 0x0C0D0E0F; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x2C2D2E2F; + CHECKREG r5, 0x4C4D4E4F; + CHECKREG r7, 0x8C8D8E8F; + + R4 = [ P5 ++ ]; + R5 = [ P1 ++ ]; + R6 = [ P2 ++ ]; + R0 = [ P4 ++ ]; + R1 = [ FP ++ ]; + CHECKREG r0, 0x90919293; + CHECKREG r1, 0x10111213; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x30313233; + CHECKREG r6, 0x50515253; + + R5 = [ P5 ++ ]; + R6 = [ P1 ++ ]; + R7 = [ P2 ++ ]; + R1 = [ P4 ++ ]; + R2 = [ FP ++ ]; + CHECKREG r1, 0x94959697; + CHECKREG r2, 0x14151617; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x34353637; + CHECKREG r7, 0x54555657; + + R6 = [ P5 ++ ]; + R7 = [ P1 ++ ]; + R0 = [ P2 ++ ]; + R2 = [ P4 ++ ]; + R3 = [ FP ++ ]; + CHECKREG r0, 0x58595A5B; + CHECKREG r2, 0x98999A9B; + CHECKREG r3, 0x18191A1B; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x18191A1B; + CHECKREG r7, 0x38393A3B; + + R7 = [ P5 ++ ]; + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ FP ++ ]; + CHECKREG r0, 0x3C3D3E3F; + CHECKREG r1, 0xC5C6C7C8; + CHECKREG r3, 0x9C9D9E9F; + CHECKREG r4, 0x1C1D1E1F; + CHECKREG r6, 0x18191A1B; + CHECKREG r7, 0x1C1D1E1F; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_pp_b.s b/sim/testsuite/bfin/c_ldst_ld_d_p_pp_b.s new file mode 100644 index 0000000..492ef3c --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_pp_b.s @@ -0,0 +1,324 @@ +//Original:/testcases/core/c_ldst_ld_d_p_pp_b/c_ldst_ld_d_p_pp_b.dsp +// Spec Reference: c_ldst ld d [p++] b +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = B [ P5 ++ ] (Z); + R1 = B [ P1 ++ ] (Z); + R2 = B [ P2 ++ ] (Z); + R4 = B [ P4 ++ ] (Z); + R5 = B [ FP ++ ] (Z); + + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + R1 = B [ P5 ++ ] (Z); + R2 = B [ P1 ++ ] (Z); + R3 = B [ P2 ++ ] (Z); + R5 = B [ P4 ++ ] (Z); + R6 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000022; + CHECKREG r3, 0x00000042; + CHECKREG r5, 0x00000082; + CHECKREG r6, 0x00000002; + R2 = B [ P5 ++ ] (Z); + R3 = B [ P1 ++ ] (Z); + R4 = B [ P2 ++ ] (Z); + R6 = B [ P4 ++ ] (Z); + R7 = B [ FP ++ ] (Z); + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000021; + CHECKREG r4, 0x00000041; + CHECKREG r6, 0x00000081; + CHECKREG r7, 0x00000001; + + R3 = B [ P5 ++ ] (Z); + R4 = B [ P1 ++ ] (Z); + R5 = B [ P2 ++ ] (Z); + R7 = B [ P4 ++ ] (Z); + R0 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000000; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000020; + CHECKREG r5, 0x00000040; + CHECKREG r7, 0x00000080; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_pp_h.s b/sim/testsuite/bfin/c_ldst_ld_d_p_pp_h.s new file mode 100644 index 0000000..b5bd84f --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_pp_h.s @@ -0,0 +1,350 @@ +//Original:/testcases/core/c_ldst_ld_d_p_pp_h/c_ldst_ld_d_p_pp_h.dsp +// Spec Reference: c_ldst ld d [p++] h +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_4; +.endif + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = W [ P5 ++ ] (Z); + R1 = W [ P1 ++ ] (Z); + R2 = W [ P2 ++ ] (Z); +.ifndef BFIN_HOST + R3 = W [ P3 ++ ] (Z); +.endif + R4 = W [ P4 ++ ] (Z); + R5 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; +.ifndef BFIN_HOST + CHECKREG r3, 0x00006263; +.endif + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + R1 = W [ P5 ++ ] (Z); + R2 = W [ P1 ++ ] (Z); + R3 = W [ P2 ++ ] (Z); +.ifndef BFIN_HOST + R4 = W [ P3 ++ ] (Z); +.endif + R5 = W [ P4 ++ ] (Z); + R6 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00002021; + CHECKREG r3, 0x00004041; +.ifndef BFIN_HOST + CHECKREG r4, 0x00006061; +.endif + CHECKREG r5, 0x00008081; + CHECKREG r6, 0x00000001; + R2 = W [ P5 ++ ] (Z); + R3 = W [ P1 ++ ] (Z); + R4 = W [ P2 ++ ] (Z); +.ifndef BFIN_HOST + R5 = W [ P3 ++ ] (Z); +.endif + R6 = W [ P4 ++ ] (Z); + R7 = W [ FP ++ ] (Z); + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00004647; +.ifndef BFIN_HOST + CHECKREG r5, 0x00006667; +.endif + CHECKREG r6, 0x00008687; + CHECKREG r7, 0x00000607; + + R3 = W [ P5 ++ ] (Z); + R4 = W [ P1 ++ ] (Z); + R5 = W [ P2 ++ ] (Z); +.ifndef BFIN_HOST + R6 = W [ P3 ++ ] (Z); +.endif + R7 = W [ P4 ++ ] (Z); + R0 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000405; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00000405; + CHECKREG r4, 0x00002425; +.ifndef BFIN_HOST + CHECKREG r5, 0x00004445; + CHECKREG r6, 0x00006465; +.endif + CHECKREG r7, 0x00008485; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_pp_xb.s b/sim/testsuite/bfin/c_ldst_ld_d_p_pp_xb.s new file mode 100644 index 0000000..834508b --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_pp_xb.s @@ -0,0 +1,355 @@ +//Original:testcases/core/c_ldst_ld_d_p_pp_xb/c_ldst_ld_d_p_pp_xb.dsp +// Spec Reference: c_ldst ld d [p++] xb +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x04; + loadsym p1, DATA_ADDR_2, 0x04; + loadsym p2, DATA_ADDR_3, 0x04; + loadsym i1, DATA_ADDR_4, 0x04; + loadsym p4, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x04; + loadsym i3, DATA_ADDR_7, 0x04; + P3 = I1; SP = I3; + + R4 = B [ P5 ++ ] (X); + R5 = B [ P1 ++ ] (X); + R6 = B [ P2 ++ ] (X); + R7 = B [ P3 ++ ] (X); + R0 = B [ P4 ++ ] (X); + R1 = B [ FP ++ ] (X); + R2 = B [ SP ++ ] (X); + CHECKREG r0, 0xFFFFFF87; + CHECKREG r1, 0x00000007; + CHECKREG r2, 0xFFFFFF87; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000027; + CHECKREG r6, 0x00000047; + CHECKREG r7, 0x00000067; + + R5 = B [ P5 ++ ] (X); + R6 = B [ P1 ++ ] (X); + R7 = B [ P2 ++ ] (X); + R0 = B [ P3 ++ ] (X); + R1 = B [ P4 ++ ] (X); + R2 = B [ FP ++ ] (X); + R3 = B [ SP ++ ] (X); + CHECKREG r0, 0x00000066; + CHECKREG r1, 0xFFFFFF86; + CHECKREG r2, 0x00000006; + CHECKREG r3, 0xFFFFFF86; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000026; + CHECKREG r7, 0x00000046; + + R6 = B [ P5 ++ ] (X); + R7 = B [ P1 ++ ] (X); + R0 = B [ P2 ++ ] (X); + R1 = B [ P3 ++ ] (X); + R2 = B [ P4 ++ ] (X); + R3 = B [ FP ++ ] (X); + R4 = B [ SP ++ ] (X); + CHECKREG r0, 0x00000045; + CHECKREG r1, 0x00000065; + CHECKREG r2, 0xFFFFFF85; + CHECKREG r3, 0x00000005; + CHECKREG r4, 0xFFFFFF85; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000005; + CHECKREG r7, 0x00000025; + + R7 = B [ P5 ++ ] (X); + R0 = B [ P1 ++ ] (X); + R1 = B [ P2 ++ ] (X); + R2 = B [ P3 ++ ] (X); + R3 = B [ P4 ++ ] (X); + R4 = B [ FP ++ ] (X); + R5 = B [ SP ++ ] (X); + CHECKREG r0, 0x00000024; + CHECKREG r1, 0x00000044; + CHECKREG r2, 0x00000064; + CHECKREG r3, 0xFFFFFF84; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0xFFFFFF84; + CHECKREG r6, 0x00000005; + CHECKREG r7, 0x00000004; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_pp_xh.s b/sim/testsuite/bfin/c_ldst_ld_d_p_pp_xh.s new file mode 100644 index 0000000..bab5d78 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_pp_xh.s @@ -0,0 +1,333 @@ +//Original:testcases/core/c_ldst_ld_d_p_pp_xh/c_ldst_ld_d_p_pp_xh.dsp +// Spec Reference: c_ldst ld d [p++] xh +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + +// initial values + loadsym p5, DATA_ADDR_1, 0x08; + loadsym p1, DATA_ADDR_2, 0x08; + loadsym p2, DATA_ADDR_3, 0x08; + loadsym p4, DATA_ADDR_5, 0x08; + loadsym fp, DATA_ADDR_6, 0x08; + + R4 = W [ P5 ++ ] (X); + R5 = W [ P1 ++ ] (X); + R6 = W [ P2 ++ ] (X); + R0 = W [ P4 ++ ] (X); + R1 = W [ FP ++ ] (X); + CHECKREG r0, 0xFFFF8A8B; + CHECKREG r1, 0x00000A0B; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0x00004A4B; + + R5 = W [ P5 ++ ] (X); + R6 = W [ P1 ++ ] (X); + R7 = W [ P2 ++ ] (X); + R1 = W [ P4 ++ ] (X); + R2 = W [ FP ++ ] (X); + CHECKREG r1, 0xFFFF8889; + CHECKREG r2, 0x00000809; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00002829; + CHECKREG r7, 0x00004849; + + R6 = W [ P5 ++ ] (X); + R7 = W [ P1 ++ ] (X); + R0 = W [ P2 ++ ] (X); + R2 = W [ P4 ++ ] (X); + R3 = W [ FP ++ ] (X); + CHECKREG r0, 0x00004E4F; + CHECKREG r2, 0xFFFF8E8F; + CHECKREG r3, 0x00000E0F; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00000E0F; + CHECKREG r7, 0x00002E2F; + + R7 = W [ P5 ++ ] (X); + R0 = W [ P1 ++ ] (X); + R1 = W [ P2 ++ ] (X); + R3 = W [ P4 ++ ] (X); + R4 = W [ FP ++ ] (X); + CHECKREG r0, 0x00002C2D; + CHECKREG r1, 0x00004C4D; + CHECKREG r3, 0xFFFF8C8D; + CHECKREG r4, 0x00000C0D; + CHECKREG r6, 0x00000E0F; + CHECKREG r7, 0x00000C0D; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_ppmm_hbx.s b/sim/testsuite/bfin/c_ldst_ld_d_p_ppmm_hbx.s new file mode 100644 index 0000000..f782e83 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_ppmm_hbx.s @@ -0,0 +1,656 @@ +//Original:/testcases/core/c_ldst_ld_d_p_ppmm_hbx/c_ldst_ld_d_p_ppmm_hbx.dsp +// Spec Reference: c_ldst ld d [p++/--] h b xh xb +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = W [ P5 ++ ] (Z); + R1 = W [ P1 ++ ] (Z); + R2 = W [ P2 ++ ] (Z); + R4 = W [ P4 ++ ] (Z); + R5 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + R1 = W [ P5 ++ ] (Z); + R2 = W [ P1 ++ ] (Z); + R3 = W [ P2 ++ ] (Z); + R5 = W [ P4 ++ ] (Z); + R6 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00002021; + CHECKREG r3, 0x00004041; + CHECKREG r5, 0x00008081; + CHECKREG r6, 0x00000001; + R2 = W [ P5 ++ ] (Z); + R3 = W [ P1 ++ ] (Z); + R4 = W [ P2 ++ ] (Z); + R6 = W [ P4 ++ ] (Z); + R7 = W [ FP ++ ] (Z); + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00004647; + CHECKREG r6, 0x00008687; + CHECKREG r7, 0x00000607; + + R3 = W [ P5 ++ ] (Z); + R4 = W [ P1 ++ ] (Z); + R5 = W [ P2 ++ ] (Z); + R7 = W [ P4 ++ ] (Z); + R0 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000405; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00000405; + CHECKREG r4, 0x00002425; + CHECKREG r5, 0x00004445; + CHECKREG r7, 0x00008485; + + R4 = W [ P5 ++ ] (X); + R5 = W [ P1 ++ ] (X); + R6 = W [ P2 ++ ] (X); + R0 = W [ P4 ++ ] (X); + R1 = W [ FP ++ ] (X); + CHECKREG r0, 0xFFFF8A8B; + CHECKREG r1, 0x00000A0B; + CHECKREG r3, 0x00000405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0x00004A4B; + + R5 = W [ P5 ++ ] (X); + R6 = W [ P1 ++ ] (X); + R7 = W [ P2 ++ ] (X); + R1 = W [ P4 ++ ] (X); + R2 = W [ FP ++ ] (X); + CHECKREG r1, 0xFFFF8889; + CHECKREG r2, 0x00000809; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00002829; + CHECKREG r7, 0x00004849; + + R6 = W [ P5 ++ ] (X); + R7 = W [ P1 ++ ] (X); + R0 = W [ P2 ++ ] (X); + R2 = W [ P4 ++ ] (X); + R3 = W [ FP ++ ] (X); + CHECKREG r0, 0x00004E4F; + CHECKREG r2, 0xFFFF8E8F; + CHECKREG r3, 0x00000E0F; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00000E0F; + CHECKREG r7, 0x00002E2F; + + R7 = W [ P5 ++ ] (X); + R0 = W [ P1 ++ ] (X); + R1 = W [ P2 ++ ] (X); + R3 = W [ P4 ++ ] (X); + R4 = W [ FP ++ ] (X); + CHECKREG r0, 0x00002C2D; + CHECKREG r1, 0x00004C4D; + CHECKREG r3, 0xFFFF8C8D; + CHECKREG r4, 0x00000C0D; + CHECKREG r6, 0x00000E0F; + CHECKREG r7, 0x00000C0D; + + R0 = W [ P5 -- ] (Z); + R1 = W [ P1 -- ] (Z); + R2 = W [ P2 -- ] (Z); + R4 = W [ P4 -- ] (Z); + R5 = W [ FP -- ] (Z); + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00003233; + CHECKREG r2, 0x00005253; + CHECKREG r4, 0x00009293; + CHECKREG r5, 0x00001213; + R1 = W [ P5 -- ] (Z); + R2 = W [ P1 -- ] (Z); + R3 = W [ P2 -- ] (Z); + R5 = W [ P4 -- ] (Z); + R6 = W [ FP -- ] (Z); + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00000C0D; + CHECKREG r2, 0x00002C2D; + CHECKREG r3, 0x00004C4D; + CHECKREG r5, 0x00008C8D; + CHECKREG r6, 0x00000C0D; + R2 = W [ P5 -- ] (Z); + R3 = W [ P1 -- ] (Z); + R4 = W [ P2 -- ] (Z); + R6 = W [ P4 -- ] (Z); + R7 = W [ FP -- ] (Z); + CHECKREG r1, 0x00000C0D; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00002E2F; + CHECKREG r4, 0x00004E4F; + CHECKREG r6, 0x00008E8F; + CHECKREG r7, 0x00000E0F; + + R3 = W [ P5 -- ] (Z); + R4 = W [ P1 -- ] (Z); + R5 = W [ P2 -- ] (Z); + R7 = W [ P4 -- ] (Z); + R0 = W [ FP -- ] (Z); + CHECKREG r0, 0x00000809; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00002829; + CHECKREG r5, 0x00004849; + CHECKREG r7, 0x00008889; + + R4 = W [ P5 -- ] (X); + R5 = W [ P1 -- ] (X); + R6 = W [ P2 -- ] (X); + R0 = W [ P4 -- ] (X); + R1 = W [ FP -- ] (X); + CHECKREG r0, 0xFFFF8A8B; + CHECKREG r1, 0x00000A0B; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0x00004A4B; + + R5 = W [ P5 -- ] (X); + R6 = W [ P1 -- ] (X); + R7 = W [ P2 -- ] (X); + R1 = W [ P4 -- ] (X); + R2 = W [ FP -- ] (X); + CHECKREG r1, 0xFFFF8485; + CHECKREG r2, 0x00000405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00004445; + + R6 = W [ P5 -- ] (X); + R7 = W [ P1 -- ] (X); + R0 = W [ P2 -- ] (X); + R2 = W [ P4 -- ] (X); + R3 = W [ FP -- ] (X); + CHECKREG r0, 0x00004647; + CHECKREG r2, 0xFFFF8687; + CHECKREG r3, 0x00000607; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00000607; + CHECKREG r7, 0x00002627; + + R7 = W [ P5 -- ] (X); + R0 = W [ P1 -- ] (X); + R1 = W [ P2 -- ] (X); + R3 = W [ P4 -- ] (X); + R4 = W [ FP -- ] (X); + CHECKREG r0, 0x00002021; + CHECKREG r1, 0x00004041; + CHECKREG r3, 0xFFFF8081; + CHECKREG r4, 0x00000001; + CHECKREG r6, 0x00000607; + CHECKREG r7, 0x00000001; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = B [ P5 ++ ] (Z); + R1 = B [ P1 ++ ] (Z); + R2 = B [ P2 ++ ] (Z); + R4 = B [ P4 ++ ] (Z); + R5 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + R1 = B [ P5 ++ ] (Z); + R2 = B [ P1 ++ ] (Z); + R3 = B [ P2 ++ ] (Z); + R5 = B [ P4 ++ ] (Z); + R6 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000022; + CHECKREG r3, 0x00000042; + CHECKREG r5, 0x00000082; + CHECKREG r6, 0x00000002; + R2 = B [ P5 ++ ] (Z); + R3 = B [ P1 ++ ] (Z); + R4 = B [ P2 ++ ] (Z); + R6 = B [ P4 ++ ] (Z); + R7 = B [ FP ++ ] (Z); + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000021; + CHECKREG r4, 0x00000041; + CHECKREG r6, 0x00000081; + CHECKREG r7, 0x00000001; + + R3 = B [ P5 ++ ] (Z); + R4 = B [ P1 ++ ] (Z); + R5 = B [ P2 ++ ] (Z); + R7 = B [ P4 ++ ] (Z); + R0 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000000; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000020; + CHECKREG r5, 0x00000040; + CHECKREG r7, 0x00000080; + + R4 = B [ P5 ++ ] (X); + R5 = B [ P1 ++ ] (X); + R6 = B [ P2 ++ ] (X); + R0 = B [ P4 ++ ] (X); + R1 = B [ FP ++ ] (X); + CHECKREG r0, 0xFFFFFF87; + CHECKREG r1, 0x00000007; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000027; + CHECKREG r6, 0x00000047; + + R5 = B [ P5 ++ ] (X); + R6 = B [ P1 ++ ] (X); + R7 = B [ P2 ++ ] (X); + R1 = B [ P4 ++ ] (X); + R2 = B [ FP ++ ] (X); + CHECKREG r1, 0xFFFFFF86; + CHECKREG r2, 0x00000006; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000026; + CHECKREG r7, 0x00000046; + + R6 = B [ P5 ++ ] (X); + R7 = B [ P1 ++ ] (X); + R0 = B [ P2 ++ ] (X); + R2 = B [ P4 ++ ] (X); + R3 = B [ FP ++ ] (X); + CHECKREG r0, 0x00000045; + CHECKREG r2, 0xFFFFFF85; + CHECKREG r3, 0x00000005; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000005; + CHECKREG r7, 0x00000025; + + R7 = B [ P5 ++ ] (X); + R0 = B [ P1 ++ ] (X); + R1 = B [ P2 ++ ] (X); + R3 = B [ P4 ++ ] (X); + R4 = B [ FP ++ ] (X); + CHECKREG r0, 0x00000024; + CHECKREG r1, 0x00000044; + CHECKREG r3, 0xFFFFFF84; + CHECKREG r4, 0x00000004; + CHECKREG r6, 0x00000005; + CHECKREG r7, 0x00000004; + + R0 = B [ P5 -- ] (Z); + R1 = B [ P1 -- ] (Z); + R2 = B [ P2 -- ] (Z); + R4 = B [ P4 -- ] (Z); + R5 = B [ FP -- ] (Z); + CHECKREG r0, 0x0000000B; + CHECKREG r1, 0x0000002B; + CHECKREG r2, 0x0000004B; + CHECKREG r4, 0x0000008B; + CHECKREG r5, 0x0000000B; + R1 = B [ P5 -- ] (Z); + R2 = B [ P1 -- ] (Z); + R3 = B [ P2 -- ] (Z); + R5 = B [ P4 -- ] (Z); + R6 = B [ FP -- ] (Z); + CHECKREG r0, 0x0000000B; + CHECKREG r1, 0x00000004; + CHECKREG r2, 0x00000024; + CHECKREG r3, 0x00000044; + CHECKREG r5, 0x00000084; + CHECKREG r6, 0x00000004; + R2 = B [ P5 -- ] (Z); + R3 = B [ P1 -- ] (Z); + R4 = B [ P2 -- ] (Z); + R6 = B [ P4 -- ] (Z); + R7 = B [ FP -- ] (Z); + CHECKREG r1, 0x00000004; + CHECKREG r2, 0x00000005; + CHECKREG r3, 0x00000025; + CHECKREG r4, 0x00000045; + CHECKREG r6, 0x00000085; + CHECKREG r7, 0x00000005; + + R3 = B [ P5 -- ] (Z); + R4 = B [ P1 -- ] (Z); + R5 = B [ P2 -- ] (Z); + R7 = B [ P4 -- ] (Z); + R0 = B [ FP -- ] (Z); + CHECKREG r0, 0x00000006; + CHECKREG r2, 0x00000005; + CHECKREG r3, 0x00000006; + CHECKREG r4, 0x00000026; + CHECKREG r5, 0x00000046; + CHECKREG r7, 0x00000086; + + R4 = B [ P5 -- ] (X); + R5 = B [ P1 -- ] (X); + R6 = B [ P2 -- ] (X); + R0 = B [ P4 -- ] (X); + R1 = B [ FP -- ] (X); + CHECKREG r0, 0xFFFFFF87; + CHECKREG r1, 0x00000007; + CHECKREG r3, 0x00000006; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000027; + CHECKREG r6, 0x00000047; + + R5 = B [ P5 -- ] (X); + R6 = B [ P1 -- ] (X); + R7 = B [ P2 -- ] (X); + R1 = B [ P4 -- ] (X); + R2 = B [ FP -- ] (X); + CHECKREG r1, 0xFFFFFF80; + CHECKREG r2, 0x00000000; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000020; + CHECKREG r7, 0x00000040; + + R6 = B [ P5 -- ] (X); + R7 = B [ P1 -- ] (X); + R0 = B [ P2 -- ] (X); + R2 = B [ P4 -- ] (X); + R3 = B [ FP -- ] (X); + CHECKREG r0, 0x00000041; + CHECKREG r2, 0xFFFFFF81; + CHECKREG r3, 0x00000001; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000001; + CHECKREG r7, 0x00000021; + + R7 = B [ P5 -- ] (X); + R0 = B [ P1 -- ] (X); + R1 = B [ P2 -- ] (X); + R3 = B [ P4 -- ] (X); + R4 = B [ FP -- ] (X); + CHECKREG r0, 0x00000022; + CHECKREG r1, 0x00000042; + CHECKREG r3, 0xFFFFFF82; + CHECKREG r4, 0x00000002; + CHECKREG r6, 0x00000001; + CHECKREG r7, 0x00000002; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_xb.s b/sim/testsuite/bfin/c_ldst_ld_d_p_xb.s new file mode 100644 index 0000000..2337a7a --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_xb.s @@ -0,0 +1,326 @@ +//Original:/testcases/core/c_ldst_ld_d_p_xb/c_ldst_ld_d_p_xb.dsp +// Spec Reference: c_ldst ld d [p] xb +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// load 8 bits from memory & sign extend into 32-bit reg + R4 = B [ P5 ] (X); + R5 = B [ FP ] (X); + R7 = B [ P1 ] (X); + R0 = B [ P2 ] (X); + R2 = B [ P4 ] (X); + CHECKREG r0, 0x00000023; + CHECKREG r2, 0x00000063; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0xFFFFFF83; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + R5 = B [ FP ] (X); + R7 = B [ P1 ] (X); + R0 = B [ P2 ] (X); + R2 = B [ P4 ] (X); + R3 = B [ P5 ] (X); + CHECKREG r0, 0x00000023; + CHECKREG r2, 0x00000063; + CHECKREG r3, 0xFFFFFF83; + CHECKREG r4, 0xFFFFFF83; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + R7 = B [ P1 ] (X); + R0 = B [ P2 ] (X); + R2 = B [ P4 ] (X); + R3 = B [ P5 ] (X); + R4 = B [ FP ] (X); + CHECKREG r0, 0x00000023; + CHECKREG r2, 0x00000063; + CHECKREG r3, 0xFFFFFF83; + CHECKREG r4, 0x00000003; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + R7 = B [ P1 ] (X); + R0 = B [ P2 ] (X); + R2 = B [ P4 ] (X); + R3 = B [ P5 ] (X); + R4 = B [ FP ] (X); + CHECKREG r0, 0x00000023; + CHECKREG r2, 0x00000063; + CHECKREG r3, 0xFFFFFF83; + CHECKREG r4, 0x00000003; + CHECKREG r7, 0x00000003; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_d_p_xh.s b/sim/testsuite/bfin/c_ldst_ld_d_p_xh.s new file mode 100644 index 0000000..480a98d --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_d_p_xh.s @@ -0,0 +1,354 @@ +//Original:/testcases/core/c_ldst_ld_d_p_xh/c_ldst_ld_d_p_xh.dsp +// Spec Reference: c_ldst ld d [p] xh +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// load 16 bits from memory and sign extend into 32-bit reg + R4 = W [ P5 ] (X); + R5 = W [ FP ] (X); + R7 = W [ P1 ] (X); + R0 = W [ P2 ] (X); +.ifndef BFIN_HOST + R1 = W [ P3 ] (X); +.else + imm32 r1, 0x00004243; +.endif + R2 = W [ P4 ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0xFFFF8283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + R5 = W [ FP ] (X); + R7 = W [ P1 ] (X); + R0 = W [ P2 ] (X); +.ifndef BFIN_HOST + R1 = W [ P3 ] (X); +.else + imm32 R1, 0x00004243; +.endif + R2 = W [ P4 ] (X); + R3 = W [ P5 ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0xFFFF8283; + CHECKREG r4, 0xFFFF8283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + R7 = W [ P1 ] (X); + R0 = W [ P2 ] (X); +.ifndef BFIN_HOST + R1 = W [ P3 ] (X); +.else + imm32 R1, 0x00004243; +.endif + R2 = W [ P4 ] (X); + R3 = W [ P5 ] (X); + R4 = W [ FP ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0xFFFF8283; + CHECKREG r4, 0x00000203; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + R7 = W [ P1 ] (X); + R0 = W [ P2 ] (X); +.ifndef BFIN_HOST + R1 = W [ P3 ] (X); +.else + imm32 R1, 0x00004243; +.endif + R2 = W [ P4 ] (X); + R3 = W [ P5 ] (X); + R4 = W [ FP ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0xFFFF8283; + CHECKREG r4, 0x00000203; + CHECKREG r7, 0x00000203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_p_p.s b/sim/testsuite/bfin/c_ldst_ld_p_p.s new file mode 100644 index 0000000..96658b5 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_p_p.s @@ -0,0 +1,327 @@ +//Original:/testcases/core/c_ldst_ld_p_p/c_ldst_ld_p_p.dsp +// Spec Reference: c_ldst ld p [p] +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + P2 = [ P1 ]; + P4 = [ P1 ]; + P5 = [ P1 ]; + FP = [ P1 ]; + CHECKREG p2, 0x78910213; + CHECKREG p4, 0x78910213; + CHECKREG p5, 0x78910213; + CHECKREG fp, 0x78910213; + + loadsym p2, DATA_ADDR_2; + P1 = [ P2 ]; + P4 = [ P2 ]; + P5 = [ P2 ]; + FP = [ P2 ]; + CHECKREG p1, 0x20212223; + CHECKREG p4, 0x20212223; + CHECKREG p5, 0x20212223; + CHECKREG fp, 0x20212223; + + loadsym p4, DATA_ADDR_4; + P1 = [ P4 ]; + P2 = [ P4 ]; + P5 = [ P4 ]; + FP = [ P4 ]; + CHECKREG p1, 0x60616263; + CHECKREG p2, 0x60616263; + CHECKREG p5, 0x60616263; + CHECKREG fp, 0x60616263; + + loadsym p5, DATA_ADDR_5; + P1 = [ P5 ]; + P2 = [ P5 ]; + P4 = [ P5 ]; + FP = [ P5 ]; + CHECKREG p1, 0x8A8B8C8D; + CHECKREG p2, 0x8A8B8C8D; + CHECKREG p4, 0x8A8B8C8D; + CHECKREG fp, 0x8A8B8C8D; + + loadsym fp, DATA_ADDR_7; + P1 = [ FP ]; + P2 = [ FP ]; + P4 = [ FP ]; + P5 = [ FP ]; + CHECKREG p1, 0x80818283; + CHECKREG p2, 0x80818283; + CHECKREG p4, 0x80818283; + CHECKREG p5, 0x80818283; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x78910213 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x8A8B8C8D + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_p_p_mm.s b/sim/testsuite/bfin/c_ldst_ld_p_p_mm.s new file mode 100644 index 0000000..75471c8 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_p_p_mm.s @@ -0,0 +1,406 @@ +//Original:testcases/core/c_ldst_ld_p_p_mm/c_ldst_ld_p_p_mm.dsp +// Spec Reference: c_ldst ld p [p--] +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x18; + loadsym p2, DATA_ADDR_2, 0x18; + loadsym i1, DATA_ADDR_3, 0x18; + loadsym p4, DATA_ADDR_4, 0x18; + loadsym p5, DATA_ADDR_5, 0x18; + loadsym fp, DATA_ADDR_6, 0x18; + loadsym i3, DATA_ADDR_7, 0x18; + P3 = I1; SP = I3; + + P2 = [ P1 -- ]; + P3 = [ P1 -- ]; + P4 = [ P1 -- ]; + P5 = [ P1 -- ]; + SP = [ P1 -- ]; + FP = [ P1 -- ]; + CHECKREG p2, 0x18191A1B; + CHECKREG p3, 0x14151617; + CHECKREG p4, 0x10111213; + CHECKREG p5, 0x0C0D0E0F; + CHECKREG sp, 0x08090A0B; + CHECKREG fp, 0x04050607; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x18; + P3 = I1; SP = I3; + + P1 = [ P2 -- ]; + P3 = [ P2 -- ]; + P4 = [ P2 -- ]; + P5 = [ P2 -- ]; + SP = [ P2 -- ]; + FP = [ P2 -- ]; + CHECKREG p1, 0x38393A3B; + CHECKREG p3, 0x34353637; + CHECKREG p4, 0x30313233; + CHECKREG p5, 0x2C2D2E2F; + CHECKREG sp, 0x28292A2B; + CHECKREG fp, 0x24252627; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x18; + P3 = I1; SP = I3; + + P1 = [ P3 -- ]; + P2 = [ P3 -- ]; + P4 = [ P3 -- ]; + P5 = [ P3 -- ]; + SP = [ P3 -- ]; + FP = [ P3 -- ]; + CHECKREG p1, 0x58595A5B; + CHECKREG p2, 0x54555657; + CHECKREG p4, 0x50515253; + CHECKREG p5, 0x4C4D4E4F; + CHECKREG sp, 0x48494A4B; + CHECKREG fp, 0x44454647; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x18; + P3 = I1; SP = I3; + + P1 = [ P4 -- ]; + P2 = [ P4 -- ]; + P3 = [ P4 -- ]; + P5 = [ P4 -- ]; + SP = [ P4 -- ]; + FP = [ P4 -- ]; + CHECKREG p1, 0x78797A7B; + CHECKREG p2, 0x74757677; + CHECKREG p3, 0x70717273; + CHECKREG p5, 0x6C6D6E6F; + CHECKREG sp, 0x68696A6B; + CHECKREG fp, 0x64656667; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x18; + P3 = I1; SP = I3; + + P1 = [ P5 -- ]; + P2 = [ P5 -- ]; + P3 = [ P5 -- ]; + P4 = [ P5 -- ]; + SP = [ P5 -- ]; + FP = [ P5 -- ]; + CHECKREG p1, 0x98999A9B; + CHECKREG p2, 0x94959697; + CHECKREG p3, 0x90919293; + CHECKREG p4, 0x8C8D8E8F; + CHECKREG sp, 0x88898A8B; + CHECKREG fp, 0x84858687; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x18; + P3 = I1; SP = I3; + + P1 = [ SP -- ]; + P2 = [ SP -- ]; + P3 = [ SP -- ]; + P4 = [ SP -- ]; + P5 = [ SP -- ]; + FP = [ SP -- ]; + CHECKREG p1, 0x18191A1B; + CHECKREG p2, 0x14151617; + CHECKREG p3, 0x10111213; + CHECKREG p4, 0x0C0D0E0F; + CHECKREG p5, 0x08090A0B; + CHECKREG fp, 0x04050607; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x18; + P3 = I1; SP = I3; + + P1 = [ FP -- ]; + P2 = [ FP -- ]; + P3 = [ FP -- ]; + P4 = [ FP -- ]; + P5 = [ FP -- ]; + SP = [ FP -- ]; + CHECKREG p1, 0x98999A9B; + CHECKREG p2, 0x94959697; + CHECKREG p3, 0x90919293; + CHECKREG p4, 0x8C8D8E8F; + CHECKREG p5, 0x88898A8B; + CHECKREG sp, 0x84858687; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x78910213 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x8A8B8C8D + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_ld_p_p_pp.s b/sim/testsuite/bfin/c_ldst_ld_p_p_pp.s new file mode 100644 index 0000000..c66440a --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_ld_p_p_pp.s @@ -0,0 +1,335 @@ +//Original:/testcases/core/c_ldst_ld_p_p_pp/c_ldst_ld_p_p_pp.dsp +// Spec Reference: c_ldst ld p [p++] +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + P2 = [ P1 ++ ]; + P1 += 4; + P4 = [ P1 ++ ]; + P5 = [ P1 ++ ]; + P1 += 4; + FP = [ P1 ++ ]; + CHECKREG p2, 0x78910213; + CHECKREG p4, 0x08090A0B; + CHECKREG p5, 0x0C0D0E0F; + CHECKREG fp, 0x14151617; + + loadsym p2, DATA_ADDR_2; + P1 = [ P2 ++ ]; + P2 += 4; + P4 = [ P2 ++ ]; + P5 = [ P2 ++ ]; + P2 += 4; + FP = [ P2 ++ ]; + CHECKREG p1, 0x20212223; + CHECKREG p4, 0x28292A2B; + CHECKREG p5, 0x2C2D2E2F; + CHECKREG fp, 0x34353637; + + loadsym p4, DATA_ADDR_4; + P1 = [ P4 ++ ]; + P2 = [ P4 ++ ]; + P4 += 4; + P5 = [ P4 ++ ]; + P4 += 4; + FP = [ P4 ++ ]; + CHECKREG p1, 0x60616263; + CHECKREG p2, 0x64656667; + CHECKREG p5, 0x6C6D6E6F; + CHECKREG fp, 0x74757677; + + loadsym p5, DATA_ADDR_5; + P1 = [ P5 ++ ]; + P2 = [ P5 ++ ]; + P5 += 4; + P4 = [ P5 ++ ]; + P5 += 4; + FP = [ P5 ++ ]; + CHECKREG p1, 0x8A8B8C8D; + CHECKREG p2, 0x84858687; + CHECKREG p4, 0x8C8D8E8F; + CHECKREG fp, 0x94959697; + + loadsym fp, DATA_ADDR_7; + P1 = [ FP ++ ]; + P2 = [ FP ++ ]; + FP += 4; + P4 = [ FP ++ ]; + P5 = [ FP ++ ]; + CHECKREG p1, 0x80818283; + CHECKREG p2, 0x84858687; + CHECKREG p4, 0x8C8D8E8F; + CHECKREG p5, 0x90919293; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data +DATA_ADDR_1: + .dd 0x78910213 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x8A8B8C8D + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_st_p_d.s b/sim/testsuite/bfin/c_ldst_st_p_d.s new file mode 100644 index 0000000..504b027 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_st_p_d.s @@ -0,0 +1,299 @@ +//Original:/testcases/core/c_ldst_st_p_d/c_ldst_st_p_d.dsp +// Spec Reference: c_ldst st_p_d +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + [ P5 ] = R0; + [ P1 ] = R1; + [ P2 ] = R2; + [ P4 ] = R4; + [ FP ] = R5; + + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x0A231507; + CHECKREG r5, 0x5F786A5C; + CHECKREG r7, 0x719A8C7E; + + imm32 r0, 0x1a231507; + imm32 r1, 0x12342618; + imm32 r2, 0x2c353729; + imm32 r3, 0x3d54483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f78665c; + imm32 r6, 0x60897b7d; + imm32 r7, 0x719a8c78; + [ P5 ] = R1; + [ P1 ] = R2; + [ P2 ] = R3; + [ P4 ] = R5; + [ FP ] = R6; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2C353729; + CHECKREG r1, 0x3D54483A; + CHECKREG r3, 0x5F78665C; + CHECKREG r4, 0x12342618; + CHECKREG r5, 0x60897B7D; + CHECKREG r7, 0x719A8C78; + + imm32 r0, 0x2a231507; + imm32 r1, 0x12342618; + imm32 r2, 0x2c253729; + imm32 r3, 0x3d52483a; + imm32 r4, 0x4e67294b; + imm32 r5, 0x5f78625c; + imm32 r6, 0x60897b2d; + imm32 r7, 0x719a8c72; + [ P5 ] = R2; + [ P1 ] = R3; + [ P2 ] = R4; + [ P4 ] = R6; + [ FP ] = R7; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x3D52483A; + CHECKREG r1, 0x4E67294B; + CHECKREG r3, 0x60897B2D; + CHECKREG r4, 0x2C253729; + CHECKREG r5, 0x719A8C72; + CHECKREG r7, 0x719A8C72; + + imm32 r0, 0x3a231507; + imm32 r1, 0x13342618; + imm32 r2, 0x2c353729; + imm32 r3, 0x3d53483a; + imm32 r4, 0x4e67394b; + imm32 r5, 0x5f78635c; + imm32 r6, 0x60897b3d; + imm32 r7, 0x719a8c73; + [ P5 ] = R3; + [ P1 ] = R4; + [ P2 ] = R5; + [ P4 ] = R7; + [ FP ] = R0; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x4E67394B; + CHECKREG r1, 0x5F78635C; + CHECKREG r3, 0x719A8C73; + CHECKREG r4, 0x3D53483A; + CHECKREG r5, 0x3A231507; + CHECKREG r7, 0x719A8C73; + + imm32 r0, 0x4a231507; + imm32 r1, 0x14342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d54483a; + imm32 r4, 0x4e67494b; + imm32 r5, 0x5f78645c; + imm32 r6, 0x60897b4d; + imm32 r7, 0x719a8c74; + [ P5 ] = R4; + [ P1 ] = R5; + [ P2 ] = R6; + [ P4 ] = R0; + [ FP ] = R1; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x5F78645C; + CHECKREG r1, 0x60897B4D; + CHECKREG r3, 0x4A231507; + CHECKREG r4, 0x4E67494B; + CHECKREG r5, 0x14342618; + CHECKREG r7, 0x719A8C74; + + imm32 r0, 0x5a231507; + imm32 r1, 0x15342618; + imm32 r2, 0x2c553729; + imm32 r3, 0x3d55483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f78655c; + imm32 r6, 0x60897b5d; + imm32 r7, 0x719a8c75; + [ P5 ] = R5; + [ P1 ] = R6; + [ P2 ] = R7; + [ P4 ] = R1; + [ FP ] = R2; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x60897B5D; + CHECKREG r1, 0x719A8C75; + CHECKREG r3, 0x15342618; + CHECKREG r4, 0x5F78655C; + CHECKREG r5, 0x2C553729; + CHECKREG r7, 0x719A8C75; + + imm32 r0, 0x6a231507; + imm32 r1, 0x16342618; + imm32 r2, 0x2c653729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67694b; + imm32 r5, 0x5f78665c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c76; + [ P5 ] = R6; + [ P1 ] = R7; + [ P2 ] = R0; + [ P4 ] = R2; + [ FP ] = R3; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x719A8C76; + CHECKREG r1, 0x6A231507; + CHECKREG r3, 0x2C653729; + CHECKREG r4, 0x60897B6D; + CHECKREG r5, 0x3D56483A; + CHECKREG r7, 0x719A8C76; + + imm32 r0, 0x7a231507; + imm32 r1, 0x17342618; + imm32 r2, 0x2c753729; + imm32 r3, 0x3d57483a; + imm32 r4, 0x4e67794b; + imm32 r5, 0x5f78675c; + imm32 r6, 0x60897b7d; + imm32 r7, 0x719a8c77; + [ P5 ] = R7; + [ P1 ] = R0; + [ P2 ] = R1; + [ P4 ] = R3; + [ FP ] = R4; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x7A231507; + CHECKREG r1, 0x17342618; + CHECKREG r3, 0x3D57483A; + CHECKREG r4, 0x719A8C77; + CHECKREG r5, 0x4E67794B; + CHECKREG r7, 0x719A8C77; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_st_p_d_b.s b/sim/testsuite/bfin/c_ldst_st_p_d_b.s new file mode 100644 index 0000000..1575c00 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_st_p_d_b.s @@ -0,0 +1,300 @@ +//Original:/testcases/core/c_ldst_st_p_d_b/c_ldst_st_p_d_b.dsp +// Spec Reference: c_ldst st_p d b +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + B [ P5 ] = R0; + B [ P1 ] = R1; + B [ P2 ] = R2; + B [ P4 ] = R4; + B [ FP ] = R5; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212218; + CHECKREG r1, 0x40414229; + CHECKREG r3, 0x8081824B; + CHECKREG r4, 0x00010207; + CHECKREG r5, 0xA0A1A25C; + CHECKREG r7, 0x719A8C7E; + + imm32 r0, 0x1a231507; + imm32 r1, 0x11342618; + imm32 r2, 0x2c153729; + imm32 r3, 0x3d51483a; + imm32 r4, 0x4e67194b; + imm32 r5, 0x5f78615c; + imm32 r6, 0x60897b1d; + imm32 r7, 0x719a8c71; + B [ P5 ] = R1; + B [ P1 ] = R2; + B [ P2 ] = R3; + B [ P4 ] = R5; + B [ FP ] = R6; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212229; + CHECKREG r1, 0x4041423A; + CHECKREG r3, 0x8081825C; + CHECKREG r4, 0x00010218; + CHECKREG r5, 0xA0A1A21D; + CHECKREG r7, 0x719A8C71; + + imm32 r0, 0x2a231507; + imm32 r1, 0x12342618; + imm32 r2, 0x2c253729; + imm32 r3, 0x3d52483a; + imm32 r4, 0x4e67294b; + imm32 r5, 0x5f78625c; + imm32 r6, 0x60897b2d; + imm32 r7, 0x719a8c72; + B [ P5 ] = R2; + B [ P1 ] = R3; + B [ P2 ] = R4; + B [ P4 ] = R6; + B [ FP ] = R7; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021223A; + CHECKREG r1, 0x4041424B; + CHECKREG r2, 0x2c253729; + CHECKREG r3, 0x8081822D; + CHECKREG r4, 0x00010229; + CHECKREG r5, 0xA0A1A272; + CHECKREG r7, 0x719A8C72; + + imm32 r0, 0x3a231507; + imm32 r1, 0x13342618; + imm32 r3, 0x3d53483a; + imm32 r4, 0x4e67394b; + imm32 r5, 0x5f78635c; + imm32 r6, 0x60897b3d; + imm32 r7, 0x719a8c73; + B [ P5 ] = R3; + B [ P1 ] = R4; + B [ P2 ] = R5; + B [ P4 ] = R7; + B [ FP ] = R0; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021224B; + CHECKREG r1, 0x4041425C; + CHECKREG r3, 0x80818273; + CHECKREG r4, 0x0001023A; + CHECKREG r5, 0xA0A1A207; + CHECKREG r7, 0x719A8C73; + + imm32 r0, 0x4a231507; + imm32 r1, 0x14342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d54483a; + imm32 r4, 0x4e67494b; + imm32 r5, 0x5f78645c; + imm32 r6, 0x60897b4d; + imm32 r7, 0x719a8c74; + B [ P5 ] = R4; + B [ P1 ] = R5; + B [ P2 ] = R6; + B [ P4 ] = R0; + B [ FP ] = R1; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021225C; + CHECKREG r1, 0x4041424D; + CHECKREG r3, 0x80818207; + CHECKREG r4, 0x0001024B; + CHECKREG r5, 0xA0A1A218; + CHECKREG r7, 0x719A8C74; + + imm32 r0, 0x5a231507; + imm32 r1, 0x15342618; + imm32 r2, 0x2c553729; + imm32 r3, 0x3d55483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f78655c; + imm32 r6, 0x60897b5d; + imm32 r7, 0x719a8c75; + B [ P5 ] = R5; + B [ P1 ] = R6; + B [ P2 ] = R7; + B [ P4 ] = R1; + B [ FP ] = R2; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021225D; + CHECKREG r1, 0x40414275; + CHECKREG r3, 0x80818218; + CHECKREG r4, 0x0001025C; + CHECKREG r5, 0xA0A1A229; + CHECKREG r7, 0x719A8C75; + + imm32 r0, 0x6a231507; + imm32 r1, 0x16342618; + imm32 r2, 0x2c653729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67694b; + imm32 r5, 0x5f78665c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c76; + B [ P5 ] = R6; + B [ P1 ] = R7; + B [ P2 ] = R0; + B [ P4 ] = R2; + B [ FP ] = R3; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212276; + CHECKREG r1, 0x40414207; + CHECKREG r3, 0x80818229; + CHECKREG r4, 0x0001026D; + CHECKREG r5, 0xA0A1A23A; + CHECKREG r7, 0x719A8C76; + + imm32 r0, 0x7a231507; + imm32 r1, 0x17342618; + imm32 r2, 0x2c753729; + imm32 r3, 0x3d57483a; + imm32 r4, 0x4e67794b; + imm32 r5, 0x5f78675c; + imm32 r6, 0x60897b7d; + imm32 r7, 0x719a8c77; + B [ P5 ] = R7; + B [ P1 ] = R0; + B [ P2 ] = R1; + B [ P4 ] = R3; + B [ FP ] = R4; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212207; + CHECKREG r1, 0x40414218; + CHECKREG r3, 0x8081823A; + CHECKREG r4, 0x00010277; + CHECKREG r5, 0xA0A1A24B; + CHECKREG r7, 0x719A8C77; + + pass + +// Pre-load memory witb known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_st_p_d_h.s b/sim/testsuite/bfin/c_ldst_st_p_d_h.s new file mode 100644 index 0000000..dc0906c --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_st_p_d_h.s @@ -0,0 +1,280 @@ +//Original:/testcases/core/c_ldst_st_p_d_h/c_ldst_st_p_d_h.dsp +// Spec Reference: c_ldst st_p d h +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + W [ P5 ] = R0; + W [ P1 ] = R1; + W [ P2 ] = R2; + W [ P4 ] = R4; + W [ FP ] = R5; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212618; + CHECKREG r1, 0x40413729; + CHECKREG r3, 0x8081594B; + CHECKREG r4, 0x00011507; + CHECKREG r5, 0xA0A16A5C; + CHECKREG r7, 0x719A8C7E; + + imm32 r0, 0x1a231507; + imm32 r1, 0x11342618; + imm32 r2, 0x2c153729; + imm32 r3, 0x3d51483a; + imm32 r4, 0x4e67194b; + imm32 r5, 0x5f78615c; + imm32 r6, 0x60897b1d; + imm32 r7, 0x719a8c71; + W [ P5 ] = R1; + W [ P1 ] = R2; + W [ P2 ] = R3; + W [ P4 ] = R5; + W [ FP ] = R6; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20213729; + CHECKREG r1, 0x4041483A; + CHECKREG r3, 0x8081615C; + CHECKREG r4, 0x00012618; + CHECKREG r5, 0xA0A17B1D; + CHECKREG r6, 0x60897b1d; + + imm32 r0, 0x2a231507; + imm32 r1, 0x12342618; + imm32 r2, 0x2c253729; + imm32 r3, 0x3d52483a; + imm32 r4, 0x4e67294b; + imm32 r5, 0x5f78625c; + imm32 r6, 0x60897b2d; + imm32 r7, 0x719a8c72; + W [ P5 ] = R2; + W [ P1 ] = R3; + W [ P2 ] = R4; + W [ P4 ] = R6; + W [ FP ] = R7; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021483A; + CHECKREG r1, 0x4041294B; + CHECKREG r3, 0x80817B2D; + CHECKREG r4, 0x00013729; + CHECKREG r5, 0xA0A18C72; + CHECKREG r7, 0x719A8C72; + + imm32 r0, 0x3a231507; + imm32 r1, 0x13342618; + imm32 r2, 0x2c353729; + imm32 r3, 0x3d53483a; + imm32 r4, 0x4e67394b; + imm32 r5, 0x5f78635c; + imm32 r6, 0x60897b3d; + imm32 r7, 0x719a8c73; + W [ P5 ] = R3; + W [ P1 ] = R4; + W [ P2 ] = R5; + W [ P4 ] = R7; + W [ FP ] = R0; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021394B; + CHECKREG r1, 0x4041635C; + CHECKREG r3, 0x80818C73; + CHECKREG r4, 0x0001483A; + CHECKREG r5, 0xA0A11507; + CHECKREG r7, 0x719A8C73; + + imm32 r0, 0x4a231507; + imm32 r1, 0x14342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d54483a; + imm32 r4, 0x4e67494b; + imm32 r5, 0x5f78645c; + imm32 r6, 0x60897b4d; + imm32 r7, 0x719a8c74; + W [ P5 ] = R4; + W [ P1 ] = R5; + W [ P2 ] = R6; + W [ P4 ] = R0; + W [ FP ] = R1; + + W [ P5 ] = R5; + W [ P1 ] = R6; + W [ P2 ] = R7; + W [ P4 ] = R1; + W [ FP ] = R2; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20217B4D; + CHECKREG r1, 0x40418C74; + CHECKREG r3, 0x80812618; + CHECKREG r4, 0x0001645C; + CHECKREG r5, 0xA0A13729; + CHECKREG r7, 0x719A8C74; + + imm32 r0, 0x5a231507; + imm32 r1, 0x15342618; + imm32 r2, 0x2c553729; + imm32 r3, 0x3d55483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f78655c; + imm32 r6, 0x60897b5d; + imm32 r7, 0x719a8c75; + W [ P5 ] = R6; + W [ P1 ] = R7; + W [ P2 ] = R0; + W [ P4 ] = R2; + W [ FP ] = R3; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20218C75; + CHECKREG r1, 0x40411507; + CHECKREG r3, 0x80813729; + CHECKREG r4, 0x00017B5D; + CHECKREG r5, 0xA0A1483A; + CHECKREG r7, 0x719A8C75; + + imm32 r0, 0x6a231507; + imm32 r1, 0x16342618; + imm32 r2, 0x2c653729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67694b; + imm32 r5, 0x5f78665c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c76; + W [ P5 ] = R7; + W [ P1 ] = R0; + W [ P2 ] = R1; + W [ P4 ] = R3; + W [ FP ] = R4; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20211507; + CHECKREG r1, 0x40412618; + CHECKREG r3, 0x8081483A; + CHECKREG r4, 0x00018C76; + CHECKREG r5, 0xA0A1694B; + CHECKREG r7, 0x719A8C76; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_st_p_d_mm.s b/sim/testsuite/bfin/c_ldst_st_p_d_mm.s new file mode 100644 index 0000000..54d7faa --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_st_p_d_mm.s @@ -0,0 +1,601 @@ +//Original:testcases/core/c_ldst_st_p_d_mm/c_ldst_st_p_d_mm.dsp +// Spec Reference: c_ldst st_p++/p-- +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + loadsym i3, DATA_ADDR_7; + P3 = I1; SP = I3; + + [ P5 ++ ] = R0; + [ P1 ++ ] = R1; + [ P2 ++ ] = R2; + [ P3 ++ ] = R3; + [ P4 ++ ] = R4; + [ FP ++ ] = R5; + [ SP ++ ] = R6; + + [ P5 ++ ] = R2; + [ P1 ++ ] = R3; + [ P2 ++ ] = R4; + [ P3 ++ ] = R5; + [ P4 ++ ] = R6; + [ FP ++ ] = R7; + [ SP ++ ] = R0; + + [ P5 ++ ] = R5; + [ P1 ++ ] = R6; + [ P2 ++ ] = R7; + [ P3 ++ ] = R0; + [ P4 ++ ] = R1; + [ FP ++ ] = R2; + [ SP ++ ] = R3; + + [ P5 ++ ] = R7; + [ P1 ++ ] = R0; + [ P2 ++ ] = R1; + [ P3 ++ ] = R2; + [ P4 ++ ] = R3; + [ FP ++ ] = R4; + [ SP ++ ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + loadsym i3, DATA_ADDR_7; + P3 = I1; SP = I3; + + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R2 = [ P3 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + R6 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x0A231507; + CHECKREG r5, 0x5F786A5C; + CHECKREG r6, 0x60897B6D; + CHECKREG r7, 0x719A8C7E; + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R2 = [ P3 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + R6 = [ SP ++ ]; + CHECKREG r0, 0x3D56483A; + CHECKREG r1, 0x4E67594B; + CHECKREG r2, 0x5F786A5C; + CHECKREG r3, 0x60897B6D; + CHECKREG r4, 0x2C453729; + CHECKREG r5, 0x719A8C7E; + CHECKREG r6, 0x0A231507; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R3 = [ P3 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ P5 ++ ]; + R6 = [ FP ++ ]; + R7 = [ SP ++ ]; + CHECKREG r0, 0x3D56483A; + CHECKREG r1, 0x60897B6D; + CHECKREG r2, 0x719A8C7E; + CHECKREG r3, 0x0A231507; + CHECKREG r4, 0x1B342618; + CHECKREG r5, 0x5F786A5C; + CHECKREG r6, 0x2C453729; + CHECKREG r7, 0x3D56483A; + R3 = [ P1 ++ ]; + R4 = [ P2 ++ ]; + R5 = [ P3 ++ ]; + R6 = [ P4 ++ ]; + R7 = [ P5 ++ ]; + R0 = [ FP ++ ]; + R1 = [ SP ++ ]; + CHECKREG r0, 0x4E67594B; + CHECKREG r1, 0x5F786A5C; + CHECKREG r2, 0x719A8C7E; + CHECKREG r3, 0x0A231507; + CHECKREG r4, 0x1B342618; + CHECKREG r5, 0x2C453729; + CHECKREG r6, 0x3D56483A; + CHECKREG r7, 0x719A8C7E; + +// reset values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + [ P5 -- ] = R0; + [ P1 -- ] = R1; + [ P2 -- ] = R2; + [ P3 -- ] = R3; + [ P4 -- ] = R4; + [ FP -- ] = R5; + [ SP -- ] = R6; + + [ P5 -- ] = R2; + [ P1 -- ] = R3; + [ P2 -- ] = R4; + [ P3 -- ] = R5; + [ P4 -- ] = R6; + [ FP -- ] = R7; + [ SP -- ] = R0; + + [ P5 -- ] = R5; + [ P1 -- ] = R6; + [ P2 -- ] = R7; + [ P3 -- ] = R0; + [ P4 -- ] = R1; + [ FP -- ] = R2; + [ SP -- ] = R3; + + [ P5 -- ] = R6; + [ P1 -- ] = R7; + [ P2 -- ] = R0; + [ P3 -- ] = R1; + [ P4 -- ] = R2; + [ FP -- ] = R3; + [ SP -- ] = R4; + [ P1 -- ] = R0; + [ P2 -- ] = R1; + [ P3 -- ] = R2; + [ P4 -- ] = R3; + [ FP -- ] = R4; + [ SP -- ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ P5 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r0, 0x5F786A5C; + CHECKREG r1, 0x719A8C7E; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x1B342618; + CHECKREG r4, 0x4E67594B; + CHECKREG r5, 0x2C453729; + CHECKREG r6, 0x3D56483A; + CHECKREG r7, 0x719A8C7E; + R2 = [ P1 -- ]; + R3 = [ P2 -- ]; + R4 = [ P3 -- ]; + R5 = [ P4 -- ]; + R6 = [ P5 -- ]; + R7 = [ FP -- ]; + R0 = [ SP -- ]; + CHECKREG r0, 0x4E67594B; + CHECKREG r1, 0x719A8C7E; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x1B342618; + CHECKREG r4, 0x2C453729; + CHECKREG r5, 0x3D56483A; + CHECKREG r6, 0x719A8C7E; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r0, 0x719A8C7E; + CHECKREG r1, 0x0A231507; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x3D56483A; + CHECKREG r4, 0x719A8C7E; + CHECKREG r5, 0x4E67594B; + CHECKREG r6, 0x5F786A5C; + CHECKREG r7, 0x2C453729; + R5 = [ P1 -- ]; + R6 = [ P2 -- ]; + R7 = [ P3 -- ]; + R0 = [ P4 -- ]; + R1 = [ P5 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + CHECKREG r0, 0x719A8C7E; + CHECKREG r1, 0x3D56483A; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x1B342618; + CHECKREG r4, 0x719A8C7E; + CHECKREG r5, 0x719A8C7E; + CHECKREG r6, 0x4E67594B; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/bfin/c_ldst_st_p_d_mm_b.s b/sim/testsuite/bfin/c_ldst_st_p_d_mm_b.s new file mode 100644 index 0000000..1a2c3a9 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_st_p_d_mm_b.s @@ -0,0 +1,498 @@ +//Original:testcases/core/c_ldst_st_p_d_mm_b/c_ldst_st_p_d_mm_b.dsp +// Spec Reference: c_ldst st_p-- b byte +# mach: bfin + +.include "testutils.inc" + start + + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// reset values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + B [ P5 -- ] = R0; + B [ P1 -- ] = R1; + B [ P2 -- ] = R2; + B [ P3 -- ] = R3; + B [ P4 -- ] = R4; + B [ FP -- ] = R5; + B [ SP -- ] = R6; + + B [ P5 -- ] = R1; + B [ P1 -- ] = R2; + B [ P2 -- ] = R3; + B [ P3 -- ] = R4; + B [ P4 -- ] = R5; + B [ FP -- ] = R6; + B [ SP -- ] = R7; + + B [ P5 -- ] = R2; + B [ P1 -- ] = R3; + B [ P2 -- ] = R4; + B [ P3 -- ] = R5; + B [ P4 -- ] = R6; + B [ FP -- ] = R7; + B [ SP -- ] = R0; + + B [ P5 -- ] = R3; + B [ P1 -- ] = R4; + B [ P2 -- ] = R5; + B [ P3 -- ] = R6; + B [ P4 -- ] = R7; + B [ FP -- ] = R0; + B [ SP -- ] = R1; + + B [ P5 -- ] = R4; + B [ P1 -- ] = R5; + B [ P2 -- ] = R6; + B [ P3 -- ] = R7; + B [ P4 -- ] = R0; + B [ FP -- ] = R1; + B [ SP -- ] = R2; + + B [ P5 -- ] = R5; + B [ P1 -- ] = R6; + B [ P2 -- ] = R7; + B [ P3 -- ] = R0; + B [ P4 -- ] = R1; + B [ FP -- ] = R2; + B [ SP -- ] = R3; + + B [ P5 -- ] = R6; + B [ P1 -- ] = R7; + B [ P2 -- ] = R0; + B [ P3 -- ] = R1; + B [ P4 -- ] = R2; + B [ FP -- ] = R3; + B [ SP -- ] = R4; + + B [ P5 -- ] = R7; + B [ P1 -- ] = R0; + B [ P2 -- ] = R1; + B [ P3 -- ] = R2; + B [ P4 -- ] = R3; + B [ FP -- ] = R4; + B [ SP -- ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ P5 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r1, 0x00000029; + CHECKREG r2, 0x0000003A; + CHECKREG r3, 0x0000004B; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x0000005C; + CHECKREG r6, 0xE0E1E26D; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 -- ]; + R2 = [ P2 -- ]; + R3 = [ P3 -- ]; + R4 = [ P4 -- ]; + R5 = [ P5 -- ]; + R6 = [ FP -- ]; + R7 = [ SP -- ]; + CHECKREG r1, 0x293A4B5C; + CHECKREG r2, 0x3A4B5C6D; + CHECKREG r3, 0x4B5C6D7E; + CHECKREG r4, 0x5C6D7E07; + CHECKREG r5, 0x18293A4B; + CHECKREG r6, 0x6D7E0718; + CHECKREG r7, 0x7E071829; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r1, 0x3A4B5CDB; + CHECKREG r2, 0x3A4B5C6D; + CHECKREG r3, 0x6D7E073B; + CHECKREG r4, 0x7E07185B; + CHECKREG r5, 0x0718297B; + CHECKREG r6, 0x18293A9B; + CHECKREG r7, 0x5C6D7E1B; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/bfin/c_ldst_st_p_d_mm_h.s b/sim/testsuite/bfin/c_ldst_st_p_d_mm_h.s new file mode 100644 index 0000000..883bf35 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_st_p_d_mm_h.s @@ -0,0 +1,554 @@ +//Original:testcases/core/c_ldst_st_p_d_mm_h/c_ldst_st_p_d_mm_h.dsp +// Spec Reference: c_ldst st_p-- h half +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// reset values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + W [ P5 -- ] = R0; + W [ P1 -- ] = R1; + W [ P2 -- ] = R2; + W [ P3 -- ] = R3; + W [ P4 -- ] = R4; + W [ FP -- ] = R5; + W [ SP -- ] = R6; + + W [ P5 -- ] = R1; + W [ P1 -- ] = R2; + W [ P2 -- ] = R3; + W [ P3 -- ] = R4; + W [ P4 -- ] = R5; + W [ FP -- ] = R6; + W [ SP -- ] = R7; + + W [ P5 -- ] = R2; + W [ P1 -- ] = R3; + W [ P2 -- ] = R4; + W [ P3 -- ] = R5; + W [ P4 -- ] = R6; + W [ FP -- ] = R7; + W [ SP -- ] = R0; + + W [ P5 -- ] = R3; + W [ P1 -- ] = R4; + W [ P2 -- ] = R5; + W [ P3 -- ] = R6; + W [ P4 -- ] = R7; + W [ FP -- ] = R0; + W [ SP -- ] = R1; + + W [ P5 -- ] = R4; + W [ P1 -- ] = R5; + W [ P2 -- ] = R6; + W [ P3 -- ] = R7; + W [ P4 -- ] = R0; + W [ FP -- ] = R1; + W [ SP -- ] = R2; + + W [ P5 -- ] = R5; + W [ P1 -- ] = R6; + W [ P2 -- ] = R7; + W [ P3 -- ] = R0; + W [ P4 -- ] = R1; + W [ FP -- ] = R2; + W [ SP -- ] = R3; + + W [ P5 -- ] = R6; + W [ P1 -- ] = R7; + W [ P2 -- ] = R0; + W [ P3 -- ] = R1; + W [ P4 -- ] = R2; + W [ FP -- ] = R3; + W [ SP -- ] = R4; + + W [ P5 -- ] = R7; + W [ P1 -- ] = R0; + W [ P2 -- ] = R1; + W [ P3 -- ] = R2; + W [ P4 -- ] = R3; + W [ FP -- ] = R4; + W [ SP -- ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ P5 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r1, 0x00003729; + CHECKREG r2, 0x0000483A; + CHECKREG r3, 0x0000594B; + CHECKREG r4, 0x00001507; + CHECKREG r5, 0x00006A5C; + CHECKREG r6, 0xE0E17B6D; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 -- ]; + R2 = [ P2 -- ]; + R3 = [ P3 -- ]; + R4 = [ P4 -- ]; + R5 = [ P5 -- ]; + R6 = [ FP -- ]; + R7 = [ SP -- ]; + CHECKREG r1, 0x3729483A; + CHECKREG r2, 0x483A594B; + CHECKREG r3, 0x594B6A5C; + CHECKREG r4, 0x6A5C7B6D; + CHECKREG r5, 0x26183729; + CHECKREG r6, 0x7B6D8C7E; + CHECKREG r7, 0x8C7E1507; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r1, 0x26183729; + CHECKREG r2, 0x483A594B; + CHECKREG r3, 0x594B6A5C; + CHECKREG r4, 0x6A5C7B6D; + CHECKREG r5, 0x7B6D8C7E; + CHECKREG r6, 0x8C7E1507; + CHECKREG r7, 0x483A594B; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r1, 0x483A594B; + CHECKREG r2, 0x483A594B; + CHECKREG r3, 0x7B6D8C7E; + CHECKREG r4, 0x8C7E1507; + CHECKREG r5, 0x15072618; + CHECKREG r6, 0x26183729; + CHECKREG r7, 0x6A5C7B6D; + R4 = [ P1 -- ]; + R5 = [ P2 -- ]; + R6 = [ P3 -- ]; + R7 = [ P4 -- ]; + R0 = [ P5 -- ]; + R1 = [ FP -- ]; + R2 = [ SP -- ]; + CHECKREG r1, 0x594BB2B3; + CHECKREG r2, 0x6A5CD2D3; + CHECKREG r3, 0x7B6D8C7E; + CHECKREG r4, 0x15073233; + CHECKREG r5, 0x26185253; + CHECKREG r6, 0x37297273; + CHECKREG r7, 0x483A9293; + R5 = [ P1 -- ]; + R6 = [ P2 -- ]; + R7 = [ P3 -- ]; + R0 = [ P4 -- ]; + R1 = [ P5 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + CHECKREG r1, 0x0C0D0E0F; + CHECKREG r2, 0xACADAEAF; + CHECKREG r3, 0xCCCDCECF; + CHECKREG r4, 0x15073233; + CHECKREG r5, 0x2C2D2E2F; + CHECKREG r6, 0x4C4D4E4F; + CHECKREG r7, 0x6C6D6E6F; + R6 = [ P1 -- ]; + R7 = [ P2 -- ]; + R0 = [ P3 -- ]; + R1 = [ P4 -- ]; + R2 = [ P5 -- ]; + R3 = [ FP -- ]; + R0 = [ SP -- ]; + CHECKREG r1, 0x88898A8B; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0xA8A9AAAB; + CHECKREG r4, 0x15073233; + CHECKREG r5, 0x2C2D2E2F; + CHECKREG r6, 0x28292A2B; + CHECKREG r7, 0x48494A4B; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/bfin/c_ldst_st_p_d_pp.s b/sim/testsuite/bfin/c_ldst_st_p_d_pp.s new file mode 100644 index 0000000..05e96bc --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_st_p_d_pp.s @@ -0,0 +1,804 @@ +//Original:testcases/core/c_ldst_st_p_d_pp/c_ldst_st_p_d_pp.dsp +// Spec Reference: c_ldst st_p++ d +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + loadsym i3, DATA_ADDR_7; + P3 = I1; SP = I3; + + [ P5 ++ ] = R0; + [ P1 ++ ] = R1; + [ P2 ++ ] = R2; + [ P3 ++ ] = R3; + [ P4 ++ ] = R4; + [ FP ++ ] = R5; + [ SP ++ ] = R6; + + [ P5 ++ ] = R1; + [ P1 ++ ] = R2; + [ P2 ++ ] = R3; + [ P3 ++ ] = R4; + [ P4 ++ ] = R5; + [ FP ++ ] = R6; + [ SP ++ ] = R7; + + [ P5 ++ ] = R2; + [ P1 ++ ] = R3; + [ P2 ++ ] = R4; + [ P3 ++ ] = R5; + [ P4 ++ ] = R6; + [ FP ++ ] = R7; + [ SP ++ ] = R0; + + [ P5 ++ ] = R3; + [ P1 ++ ] = R4; + [ P2 ++ ] = R5; + [ P3 ++ ] = R6; + [ P4 ++ ] = R7; + [ FP ++ ] = R0; + [ SP ++ ] = R1; + + [ P5 ++ ] = R4; + [ P1 ++ ] = R5; + [ P2 ++ ] = R6; + [ P3 ++ ] = R7; + [ P4 ++ ] = R0; + [ FP ++ ] = R1; + [ SP ++ ] = R2; + + [ P5 ++ ] = R5; + [ P1 ++ ] = R6; + [ P2 ++ ] = R7; + [ P3 ++ ] = R0; + [ P4 ++ ] = R1; + [ FP ++ ] = R2; + [ SP ++ ] = R3; + + [ P5 ++ ] = R6; + [ P1 ++ ] = R7; + [ P2 ++ ] = R0; + [ P3 ++ ] = R1; + [ P4 ++ ] = R2; + [ FP ++ ] = R3; + [ SP ++ ] = R4; + + [ P5 ++ ] = R7; + [ P1 ++ ] = R0; + [ P2 ++ ] = R1; + [ P3 ++ ] = R2; + [ P4 ++ ] = R3; + [ FP ++ ] = R4; + [ SP ++ ] = R5; + +// Read back and check + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + loadsym i3, DATA_ADDR_7; + P3 = I1; SP = I3; + + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R2 = [ P3 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + R6 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x0A231507; + CHECKREG r5, 0x5F786A5C; + CHECKREG r6, 0x60897B6D; + CHECKREG r7, 0x719A8C7E; + + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R3 = [ P3 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ P5 ++ ]; + R6 = [ FP ++ ]; + R7 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x1B342618; + CHECKREG r6, 0x60897B6D; + CHECKREG r7, 0x719A8C7E; + + R2 = [ P1 ++ ]; + R3 = [ P2 ++ ]; + R4 = [ P3 ++ ]; + R5 = [ P4 ++ ]; + R6 = [ P5 ++ ]; + R7 = [ FP ++ ]; + R0 = [ SP ++ ]; + CHECKREG r0, 0x0A231507; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x2C453729; + CHECKREG r7, 0x719A8C7E; + + R3 = [ P1 ++ ]; + R4 = [ P2 ++ ]; + R5 = [ P3 ++ ]; + R6 = [ P4 ++ ]; + R7 = [ P5 ++ ]; + R0 = [ FP ++ ]; + R1 = [ SP ++ ]; + CHECKREG r0, 0x0A231507; + CHECKREG r1, 0x1B342618; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x3D56483A; + + R4 = [ P1 ++ ]; + R5 = [ P2 ++ ]; + R6 = [ P3 ++ ]; + R7 = [ P4 ++ ]; + R0 = [ P5 ++ ]; + R1 = [ FP ++ ]; + R2 = [ SP ++ ]; + CHECKREG r0, 0x4E67594B; + CHECKREG r1, 0x1B342618; + CHECKREG r2, 0x2C453729; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x0A231507; + + R5 = [ P1 ++ ]; + R6 = [ P2 ++ ]; + R7 = [ P3 ++ ]; + R0 = [ P4 ++ ]; + R1 = [ P5 ++ ]; + R2 = [ FP ++ ]; + R3 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x5F786A5C; + CHECKREG r2, 0x2C453729; + CHECKREG r3, 0x3D56483A; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x0A231507; + + R6 = [ P1 ++ ]; + R7 = [ P2 ++ ]; + R0 = [ P3 ++ ]; + R1 = [ P4 ++ ]; + R2 = [ P5 ++ ]; + R3 = [ FP ++ ]; + R4 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x60897B6D; + CHECKREG r3, 0x3D56483A; + CHECKREG r4, 0x4E67594B; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x0A231507; + + R7 = [ P1 ++ ]; + R0 = [ P2 ++ ]; + R1 = [ P3 ++ ]; + R2 = [ P4 ++ ]; + R3 = [ P5 ++ ]; + R4 = [ FP ++ ]; + R5 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x719A8C7E; + CHECKREG r4, 0x4E67594B; + CHECKREG r5, 0x5F786A5C; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x0A231507; + +// reset values + imm32 r0, 0x1a235507; + imm32 r1, 0x12342518; + imm32 r2, 0x23353729; + imm32 r3, 0x3f54483a; + imm32 r4, 0x4467694b; + imm32 r5, 0x5ff86a5c; + imm32 r6, 0x608b7b1d; + imm32 r7, 0x719a8c71; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + [ P5 -- ] = R0; + [ P1 -- ] = R1; + [ P2 -- ] = R2; + [ P3 -- ] = R3; + [ P4 -- ] = R4; + [ FP -- ] = R5; + [ SP -- ] = R6; + + [ P5 -- ] = R1; + [ P1 -- ] = R2; + [ P2 -- ] = R3; + [ P3 -- ] = R4; + [ P4 -- ] = R5; + [ FP -- ] = R6; + [ SP -- ] = R7; + + [ P5 -- ] = R2; + [ P1 -- ] = R3; + [ P2 -- ] = R4; + [ P3 -- ] = R5; + [ P4 -- ] = R6; + [ FP -- ] = R7; + [ SP -- ] = R0; + + [ P5 -- ] = R3; + [ P1 -- ] = R4; + [ P2 -- ] = R5; + [ P3 -- ] = R6; + [ P4 -- ] = R7; + [ FP -- ] = R0; + [ SP -- ] = R1; + + [ P5 -- ] = R4; + [ P1 -- ] = R5; + [ P2 -- ] = R6; + [ P3 -- ] = R7; + [ P4 -- ] = R0; + [ FP -- ] = R1; + [ SP -- ] = R2; + + [ P5 -- ] = R5; + [ P1 -- ] = R6; + [ P2 -- ] = R7; + [ P3 -- ] = R0; + [ P4 -- ] = R1; + [ FP -- ] = R2; + [ SP -- ] = R3; + + [ P5 -- ] = R6; + [ P1 -- ] = R7; + [ P2 -- ] = R0; + [ P3 -- ] = R1; + [ P4 -- ] = R2; + [ FP -- ] = R3; + [ SP -- ] = R4; + + [ P5 -- ] = R7; + [ P1 -- ] = R0; + [ P2 -- ] = R1; + [ P3 -- ] = R2; + [ P4 -- ] = R3; + [ FP -- ] = R4; + [ SP -- ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ P5 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x1A235507; + CHECKREG r5, 0x5FF86A5C; + CHECKREG r6, 0x608B7B1D; + CHECKREG r7, 0x719A8C71; + + R1 = [ P1 -- ]; + R2 = [ P2 -- ]; + R3 = [ P3 -- ]; + R4 = [ P4 -- ]; + R5 = [ P5 -- ]; + R6 = [ FP -- ]; + R7 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x12342518; + CHECKREG r6, 0x608B7B1D; + CHECKREG r7, 0x719A8C71; + + R2 = [ P1 -- ]; + R3 = [ P2 -- ]; + R4 = [ P3 -- ]; + R5 = [ P4 -- ]; + R6 = [ P5 -- ]; + R7 = [ FP -- ]; + R0 = [ SP -- ]; + CHECKREG r0, 0x1A235507; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x23353729; + CHECKREG r7, 0x719A8C71; + + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r0, 0x1A235507; + CHECKREG r1, 0x12342518; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x3F54483A; + + R4 = [ P1 -- ]; + R5 = [ P2 -- ]; + R6 = [ P3 -- ]; + R7 = [ P4 -- ]; + R0 = [ P5 -- ]; + R1 = [ FP -- ]; + R2 = [ SP -- ]; + CHECKREG r0, 0x4467694B; + CHECKREG r1, 0x12342518; + CHECKREG r2, 0x23353729; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x1A235507; + + R5 = [ P1 -- ]; + R6 = [ P2 -- ]; + R7 = [ P3 -- ]; + R0 = [ P4 -- ]; + R1 = [ P5 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x5FF86A5C; + CHECKREG r2, 0x23353729; + CHECKREG r3, 0x3F54483A; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x1A235507; + + R6 = [ P1 -- ]; + R7 = [ P2 -- ]; + R0 = [ P3 -- ]; + R1 = [ P4 -- ]; + R2 = [ P5 -- ]; + R3 = [ FP -- ]; + R4 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x608B7B1D; + CHECKREG r3, 0x3F54483A; + CHECKREG r4, 0x4467694B; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x1A235507; + + R7 = [ P1 -- ]; + R0 = [ P2 -- ]; + R1 = [ P3 -- ]; + R2 = [ P4 -- ]; + R3 = [ P5 -- ]; + R4 = [ FP -- ]; + R5 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x719A8C71; + CHECKREG r4, 0x4467694B; + CHECKREG r5, 0x5FF86A5C; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x1A235507; + + P3 = I1; SP = I3; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/bfin/c_ldst_st_p_d_pp_b.s b/sim/testsuite/bfin/c_ldst_st_p_d_pp_b.s new file mode 100644 index 0000000..823aa9b --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_st_p_d_pp_b.s @@ -0,0 +1,455 @@ +//Original:/testcases/core/c_ldst_st_p_d_pp_b/c_ldst_st_p_d_pp_b.dsp +// Spec Reference: c_ldst st_p++ b byte +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// store incremented by 1 loc + B [ P5 ++ ] = R0; + B [ P1 ++ ] = R1; + B [ P2 ++ ] = R2; + B [ P4 ++ ] = R4; + B [ FP ++ ] = R5; + + B [ P5 ++ ] = R1; + B [ P1 ++ ] = R2; + B [ P2 ++ ] = R3; + B [ P4 ++ ] = R5; + B [ FP ++ ] = R6; + + B [ P5 ++ ] = R2; + B [ P1 ++ ] = R3; + B [ P2 ++ ] = R4; + B [ P4 ++ ] = R6; + B [ FP ++ ] = R7; + + B [ P5 ++ ] = R3; + B [ P1 ++ ] = R4; + B [ P2 ++ ] = R5; + B [ P4 ++ ] = R7; + B [ FP ++ ] = R0; + + B [ P5 ++ ] = R4; + B [ P1 ++ ] = R5; + B [ P2 ++ ] = R6; + B [ P4 ++ ] = R0; + B [ FP ++ ] = R1; + + B [ P5 ++ ] = R5; + B [ P1 ++ ] = R6; + B [ P2 ++ ] = R7; + B [ P4 ++ ] = R1; + B [ FP ++ ] = R2; + + B [ P5 ++ ] = R6; + B [ P1 ++ ] = R7; + B [ P2 ++ ] = R0; + B [ P4 ++ ] = R2; + B [ FP ++ ] = R3; + + B [ P5 ++ ] = R7; + B [ P1 ++ ] = R0; + B [ P2 ++ ] = R1; + B [ P4 ++ ] = R3; + B [ FP ++ ] = R4; + +// Read back and check + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r0, 0x4B3A2918; + CHECKREG r1, 0x5C4B3A29; + CHECKREG r3, 0x7E6D5C4B; + CHECKREG r4, 0x3A291807; + CHECKREG r5, 0x077E6D5C; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ P5 ++ ]; + R6 = [ FP ++ ]; + CHECKREG r0, 0x4B3A2918; + CHECKREG r1, 0x077E6D5C; + CHECKREG r2, 0x18077E6D; + CHECKREG r4, 0x3A291807; + CHECKREG r5, 0x7E6D5C4B; + CHECKREG r6, 0x4B3A2918; + R2 = [ P1 ++ ]; + R3 = [ P2 ++ ]; + R5 = [ P4 ++ ]; + R6 = [ P5 ++ ]; + R7 = [ FP ++ ]; + CHECKREG r1, 0x077E6D5C; + CHECKREG r2, 0x28292A2B; + CHECKREG r3, 0x48494A4B; + CHECKREG r5, 0x88898A8B; + CHECKREG r6, 0x08090A0B; + CHECKREG r7, 0xA8A9AAAB; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/bfin/c_ldst_st_p_d_pp_h.s b/sim/testsuite/bfin/c_ldst_st_p_d_pp_h.s new file mode 100644 index 0000000..c8b453a --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_st_p_d_pp_h.s @@ -0,0 +1,457 @@ +//Original:/testcases/core/c_ldst_st_p_d_pp_h/c_ldst_st_p_d_pp_h.dsp +// Spec Reference: c_ldst st_p++/p-- h half +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// half word 16-bit store incremented by 2 + W [ P5 ++ ] = R0; + W [ P1 ++ ] = R1; + W [ P2 ++ ] = R2; + W [ P4 ++ ] = R4; + W [ FP ++ ] = R5; + + W [ P5 ++ ] = R1; + W [ P1 ++ ] = R2; + W [ P2 ++ ] = R3; + W [ P4 ++ ] = R5; + W [ FP ++ ] = R6; + + W [ P5 ++ ] = R2; + W [ P1 ++ ] = R3; + W [ P2 ++ ] = R4; + W [ P4 ++ ] = R6; + W [ FP ++ ] = R7; + + W [ P5 ++ ] = R3; + W [ P1 ++ ] = R4; + W [ P2 ++ ] = R5; + W [ P4 ++ ] = R7; + W [ FP ++ ] = R0; + + W [ P5 ++ ] = R4; + W [ P1 ++ ] = R5; + W [ P2 ++ ] = R6; + W [ P4 ++ ] = R0; + W [ FP ++ ] = R1; + + W [ P5 ++ ] = R5; + W [ P1 ++ ] = R6; + W [ P2 ++ ] = R7; + W [ P4 ++ ] = R1; + W [ FP ++ ] = R2; + + W [ P5 ++ ] = R6; + W [ P1 ++ ] = R7; + W [ P2 ++ ] = R0; + W [ P4 ++ ] = R2; + W [ FP ++ ] = R3; + + W [ P5 ++ ] = R7; + W [ P1 ++ ] = R0; + W [ P2 ++ ] = R1; + W [ P4 ++ ] = R3; + W [ FP ++ ] = R4; + +// Read back and check + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r0, 0x37292618; + CHECKREG r1, 0x483A3729; + CHECKREG r3, 0x6A5C594B; + CHECKREG r4, 0x26181507; + CHECKREG r5, 0x7B6D6A5C; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ P5 ++ ]; + R6 = [ FP ++ ]; + CHECKREG r0, 0x37292618; + CHECKREG r1, 0x594B483A; + CHECKREG r2, 0x6A5C594B; + CHECKREG r4, 0x8C7E7B6D; + CHECKREG r5, 0x483A3729; + CHECKREG r6, 0x15078C7E; + R2 = [ P1 ++ ]; + R3 = [ P2 ++ ]; + R5 = [ P4 ++ ]; + R6 = [ P5 ++ ]; + R7 = [ FP ++ ]; + CHECKREG r1, 0x594B483A; + CHECKREG r2, 0x7B6D6A5C; + CHECKREG r3, 0x8C7E7B6D; + CHECKREG r5, 0x26181507; + CHECKREG r6, 0x6A5C594B; + CHECKREG r7, 0x37292618; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/bfin/c_ldst_st_p_p.s b/sim/testsuite/bfin/c_ldst_st_p_p.s new file mode 100644 index 0000000..1cc87a1 --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_st_p_p.s @@ -0,0 +1,128 @@ +//Original:/testcases/core/c_ldst_st_p_p/c_ldst_st_p_p.dsp +// Spec Reference: c_ldst st_p_p +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values p-p + imm32 p5, 0x0a231507; + imm32 p1, 0x1b342618; + imm32 p2, 0x2c453729; + + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + [ P4 ] = P1; + [ FP ] = P2; + R5 = [ P4 ]; + R6 = [ FP ]; + CHECKREG r5, 0x1B342618; + CHECKREG r6, 0x2C453729; + + [ P4 ] = P2; + [ FP ] = R3; + R5 = [ P4 ]; + R6 = [ FP ]; + CHECKREG r5, 0x2C453729; + CHECKREG r6, 0x3D56483A; + + [ P4 ] = R3; + [ FP ] = P5; + R5 = [ P4 ]; + R6 = [ FP ]; + CHECKREG r5, 0x3D56483A; + CHECKREG r6, 0x0A231507; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldst_st_p_p_mm.s b/sim/testsuite/bfin/c_ldst_st_p_p_mm.s new file mode 100644 index 0000000..e7dd3cd --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_st_p_p_mm.s @@ -0,0 +1,428 @@ +//Original:testcases/core/c_ldst_st_p_p_mm/c_ldst_st_p_p_mm.dsp +// Spec Reference: c_ldst st p-- p +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values p-p + imm32 p5, 0x0a231507; + imm32 p1, 0x1b342618; + imm32 p2, 0x2c453729; + imm32 p3, 0x4356789a; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_5, 0x18; + loadsym fp, DATA_ADDR_6, 0x18; + loadsym i3, DATA_ADDR_7, 0x18; + P3 = I1; SP = I3; + + [ P4 -- ] = P1; + [ FP -- ] = P2; + [ SP -- ] = R3; + + [ P4 -- ] = P2; + [ FP -- ] = P3; + [ SP -- ] = P5; + + [ P4 -- ] = P3; + [ FP -- ] = P5; + [ SP -- ] = P1; + + [ P4 -- ] = P5; + [ FP -- ] = P1; + [ SP -- ] = P2; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_5, 0x18; + loadsym fp, DATA_ADDR_6, 0x18; + loadsym i3, DATA_ADDR_7, 0x18; + P3 = I1; SP = I3; + + R1 = [ P4 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + R4 = [ P4 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r1, 0x1B342618; + CHECKREG r2, 0x2C453729; + CHECKREG r3, 0x3D56483A; + CHECKREG r4, 0x2C453729; + CHECKREG r5, 0x4356789A; + CHECKREG r6, 0x0A231507; + R1 = [ P4 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + R4 = [ P4 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r1, 0x4356789A; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x1B342618; + CHECKREG r4, 0x0A231507; + CHECKREG r5, 0x1B342618; + CHECKREG r6, 0x2C453729; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x10000080 + .dd 0x02000800 + .dd 0x00207000 + .dd 0x000d0000 + .dd 0x0006b000 + .dd 0x00500a00 + .dd 0x0d0000f0 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x10006000 + .dd 0xa2050800 + .dd 0x0c30db00 + .dd 0x00b40000 + .dd 0xa0045000 + .dd 0x0000f600 + .dd 0x00d00070 + .dd 0x00000008 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x10000000 + .dd 0x0d000000 + .dd 0x00400000 + .dd 0x000b0000 + .dd 0x000d0b00 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/bfin/c_ldst_st_p_p_pp.s b/sim/testsuite/bfin/c_ldst_st_p_p_pp.s new file mode 100644 index 0000000..c8068de --- /dev/null +++ b/sim/testsuite/bfin/c_ldst_st_p_p_pp.s @@ -0,0 +1,397 @@ +//Original:/testcases/core/c_ldst_st_p_p_pp/c_ldst_st_p_p_pp.dsp +// Spec Reference: c_ldst st p++ p +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values p-p + imm32 p5, 0x0a231507; + imm32 p1, 0x1b342618; + imm32 p2, 0x2c453729; + imm32 p0, 0x125afbd3; + + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + [ P4 ++ ] = P1; + [ FP ++ ] = P2; + + [ P4 ++ ] = P2; + [ FP ++ ] = P0; + + [ P4 ++ ] = P0; + [ FP ++ ] = P5; + + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + R1 = [ P4 ++ ]; + R2 = [ FP ++ ]; + R4 = [ P4 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r1, 0x1B342618; + CHECKREG r2, 0x2C453729; + CHECKREG r4, 0x2C453729; + CHECKREG r5, 0x125AFBD3; + R1 = [ P4 ++ ]; + R2 = [ FP ++ ]; + R4 = [ P4 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r1, 0x125AFBD3; + CHECKREG r2, 0x0A231507; + CHECKREG r4, 0x8C8D8E8F; + CHECKREG r5, 0xACADAEAF; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/bfin/c_ldstidxl_ld_dr_b.s b/sim/testsuite/bfin/c_ldstidxl_ld_dr_b.s new file mode 100644 index 0000000..74b4222 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstidxl_ld_dr_b.s @@ -0,0 +1,554 @@ +//Original:testcases/core/c_ldstidxl_ld_dr_b/c_ldstidxl_ld_dr_b.dsp +// Spec Reference: c_ldstidxl load dreg B (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; + +// initial values + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + + R0 = B [ P1 + 151 ] (Z); + R1 = B [ P1 + 83 ] (Z); + R2 = B [ P1 + 45 ] (Z); + R3 = B [ P1 + 17 ] (Z); + R4 = B [ P1 + 39 ] (Z); + R5 = B [ P1 + 21 ] (Z); + R6 = B [ P1 + 123 ] (Z); + R7 = B [ P1 + 155 ] (Z); + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000018; + CHECKREG r2, 0x00000076; + CHECKREG r3, 0x00000012; + CHECKREG r4, 0x00000055; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000058; + CHECKREG r7, 0x00000004; + + R0 = B [ P2 + -121 ] (Z); + R1 = B [ P2 + -113 ] (Z); + R2 = B [ P2 + -35 ] (Z); + R3 = B [ P2 + -27 ] (Z); + R4 = B [ P2 + -49 ] (Z); + R5 = B [ P2 + -5 ] (Z); + R6 = B [ P2 + -51 ] (Z); + R7 = B [ P2 + -147 ] (Z); + CHECKREG r0, 0x000000CF; + CHECKREG r1, 0x000000D7; + CHECKREG r2, 0x00000056; + CHECKREG r3, 0x00000064; + CHECKREG r4, 0x00000094; + CHECKREG r5, 0x0000004C; + CHECKREG r6, 0x00000099; + CHECKREG r7, 0x0000004E; + + R0 = B [ P4 + 47 ] (Z); + R1 = B [ P4 + -41 ] (Z); + R2 = B [ P4 + 38 ] (Z); + R3 = B [ P4 + -31 ] (Z); + R4 = B [ P4 + 28 ] (Z); + R5 = B [ P4 + 26 ] (Z); + R6 = B [ P4 + -22 ] (Z); + R7 = B [ P4 + 105 ] (Z); + CHECKREG r0, 0x00000050; + CHECKREG r1, 0x00000093; + CHECKREG r2, 0x00000049; + CHECKREG r3, 0x00000099; + CHECKREG r4, 0x00000043; + CHECKREG r5, 0x00000067; + CHECKREG r6, 0x000000E8; + CHECKREG r7, 0x00000099; + + R0 = B [ P5 + -14 ] (Z); + R1 = B [ P5 + 12 ] (Z); + R2 = B [ P5 + -6 ] (Z); + R3 = B [ P5 + 4 ] (Z); + R4 = B [ P5 + 0 ] (Z); + R5 = B [ P5 + -2 ] (Z); + R6 = B [ P5 + 8 ] (Z); + R7 = B [ P5 + -107 ] (Z); + CHECKREG r0, 0x00000035; + CHECKREG r1, 0x00000065; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000057; + CHECKREG r4, 0x00000053; + CHECKREG r5, 0x00000047; + CHECKREG r6, 0x00000061; + CHECKREG r7, 0x00000006; + + R0 = B [ FP + 99 ] (Z); + R1 = B [ FP + -15 ] (Z); + R2 = B [ FP + 41 ] (Z); + R3 = B [ FP + -65 ] (Z); + R4 = B [ FP + 25 ] (Z); + R5 = B [ FP + -34 ] (Z); + R6 = B [ FP + 37 ] (Z); + R7 = B [ FP + -97 ] (Z); + CHECKREG r0, 0x00000093; + CHECKREG r1, 0x00000099; + CHECKREG r2, 0x0000004E; + CHECKREG r3, 0x000000D7; + CHECKREG r4, 0x00000068; + CHECKREG r5, 0x000000E8; + CHECKREG r6, 0x0000004A; + CHECKREG r7, 0x0000004C; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstidxl_ld_dr_h.s b/sim/testsuite/bfin/c_ldstidxl_ld_dr_h.s new file mode 100644 index 0000000..334ad17 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstidxl_ld_dr_h.s @@ -0,0 +1,595 @@ +//Original:testcases/core/c_ldstidxl_ld_dr_h/c_ldstidxl_ld_dr_h.dsp +// Spec Reference: c_ldstidxl load dreg H (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym i1, DATA_ADDR_1, 0x70; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + loadsym i3, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + R0 = W [ P1 + 154 ] (Z); + R1 = W [ P1 + 84 ] (Z); + R2 = W [ P1 + 48 ] (Z); + R3 = W [ P1 + 10 ] (Z); + R4 = W [ P1 + 34 ] (Z); + R5 = W [ P1 + 20 ] (Z); + R6 = W [ P1 + 126 ] (Z); + R7 = W [ P1 + 154 ] (Z); + CHECKREG r0, 0x00000405; + CHECKREG r1, 0x00002425; + CHECKREG r2, 0x00008485; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00001122; + CHECKREG r5, 0x00001617; + CHECKREG r6, 0x00006263; + CHECKREG r7, 0x00000405; + + R0 = W [ P2 + -120 ] (Z); + R1 = W [ P2 + -114 ] (Z); + R2 = W [ P2 + -36 ] (Z); + R3 = W [ P2 + -22 ] (Z); + R4 = W [ P2 + -44 ] (Z); + R5 = W [ P2 + -6 ] (Z); + R6 = W [ P2 + -52 ] (Z); + R7 = W [ P2 + -146 ] (Z); + CHECKREG r0, 0x0000D5D6; + CHECKREG r1, 0x0000D7D8; + CHECKREG r2, 0x0000565A; + CHECKREG r3, 0x0000A667; + CHECKREG r4, 0x000099EA; + CHECKREG r5, 0x00004C4D; + CHECKREG r6, 0x000099EA; + CHECKREG r7, 0x00004C4D; + + R0 = W [ P3 + 56 ] (Z); + R1 = W [ P3 + 62 ] (Z); + R2 = W [ P3 + -64 ] (Z); + R3 = W [ P3 + 60 ] (Z); + R4 = W [ P3 + -56 ] (Z); + R5 = W [ P3 + 10 ] (Z); + R6 = W [ P3 + -28 ] (Z); + R7 = W [ P3 + -110 ] (Z); + CHECKREG r0, 0x00001617; + CHECKREG r1, 0x00001819; + CHECKREG r2, 0x00008485; + CHECKREG r3, 0x00001A1B; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00005859; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00000001; + + R0 = W [ P4 + 42 ] (Z); + R1 = W [ P4 + -40 ] (Z); + R2 = W [ P4 + 38 ] (Z); + R3 = W [ P4 + -32 ] (Z); + R4 = W [ P4 + 28 ] (Z); + R5 = W [ P4 + 26 ] (Z); + R6 = W [ P4 + -22 ] (Z); + R7 = W [ P4 + 106 ] (Z); + CHECKREG r0, 0x00004C4D; + CHECKREG r1, 0x000099EA; + CHECKREG r2, 0x00004849; + CHECKREG r3, 0x000099EA; + CHECKREG r4, 0x00004243; + CHECKREG r5, 0x0000A667; + CHECKREG r6, 0x000098E8; + CHECKREG r7, 0x000095E8; + + R0 = W [ P5 + -14 ] (Z); + R1 = W [ P5 + 12 ] (Z); + R2 = W [ P5 + -6 ] (Z); + R3 = W [ P5 + 4 ] (Z); + R4 = W [ P5 + 0 ] (Z); + R5 = W [ P5 + -2 ] (Z); + R6 = W [ P5 + 8 ] (Z); + R7 = W [ P5 + -108 ] (Z); + CHECKREG r0, 0x00003435; + CHECKREG r1, 0x00006465; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00005657; + CHECKREG r4, 0x00005253; + CHECKREG r5, 0x00004647; + CHECKREG r6, 0x00006061; + CHECKREG r7, 0x00000607; + + R0 = W [ FP + 90 ] (Z); + R1 = W [ FP + -14 ] (Z); + R2 = W [ FP + 42 ] (Z); + R3 = W [ FP + -66 ] (Z); + R4 = W [ FP + 26 ] (Z); + R5 = W [ FP + -34 ] (Z); + R6 = W [ FP + 38 ] (Z); + R7 = W [ FP + -98 ] (Z); + CHECKREG r0, 0x000091E8; + CHECKREG r1, 0x000091E8; + CHECKREG r2, 0x00004C4D; + CHECKREG r3, 0x0000D7D8; + CHECKREG r4, 0x0000A667; + CHECKREG r5, 0x000095E8; + CHECKREG r6, 0x00004849; + CHECKREG r7, 0x00004C4D; + + R0 = W [ SP + 46 ] (Z); + R1 = W [ SP + -42 ] (Z); + R2 = W [ SP + 48 ] (Z); + R3 = W [ SP + 50 ] (Z); + R4 = W [ SP + -102 ] (Z); + R5 = W [ SP + 82 ] (Z); + R6 = W [ SP + 62 ] (Z); + R7 = W [ SP + 46 ] (Z); + CHECKREG r0, 0x00000809; + CHECKREG r1, 0x00000506; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00000C0D; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0x00007475; + CHECKREG r6, 0x00001819; + CHECKREG r7, 0x00000809; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstidxl_ld_dr_xb.s b/sim/testsuite/bfin/c_ldstidxl_ld_dr_xb.s new file mode 100644 index 0000000..e5a3515 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstidxl_ld_dr_xb.s @@ -0,0 +1,594 @@ +//Original:testcases/core/c_ldstidxl_ld_dr_xb/c_ldstidxl_ld_dr_xb.dsp +// Spec Reference: c_ldstidxl load dreg XB (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym i1, DATA_ADDR_1, 0x70; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + loadsym i3, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + R0 = B [ P1 + 151 ] (X); + R1 = B [ P1 + 83 ] (X); + R2 = B [ P1 + 45 ] (X); + R3 = B [ P1 + 17 ] (X); + R4 = B [ P1 + 39 ] (X); + R5 = B [ P1 + 21 ] (X); + R6 = B [ P1 + 123 ] (X); + R7 = B [ P1 + 155 ] (X); + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000018; + CHECKREG r2, 0x00000076; + CHECKREG r3, 0x00000012; + CHECKREG r4, 0x00000055; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000058; + CHECKREG r7, 0x00000004; + + R0 = B [ P2 + -121 ] (X); + R1 = B [ P2 + -113 ] (X); + R2 = B [ P2 + -35 ] (X); + R3 = B [ P2 + -27 ] (X); + R4 = B [ P2 + -49 ] (X); + R5 = B [ P2 + -5 ] (X); + R6 = B [ P2 + -51 ] (X); + R7 = B [ P2 + -147 ] (X); + CHECKREG r0, 0xFFFFFFCF; + CHECKREG r1, 0xFFFFFFD7; + CHECKREG r2, 0x00000056; + CHECKREG r3, 0x00000064; + CHECKREG r4, 0xFFFFFF94; + CHECKREG r5, 0x0000004C; + CHECKREG r6, 0xFFFFFF99; + CHECKREG r7, 0x0000004E; + + R0 = B [ P3 + 56 ] (X); + R1 = B [ P3 + 62 ] (X); + R2 = B [ P3 + -63 ] (X); + R3 = B [ P3 + 61 ] (X); + R4 = B [ P3 + -59 ] (X); + R5 = B [ P3 + 11 ] (X); + R6 = B [ P3 + -23 ] (X); + R7 = B [ P3 + -111 ] (X); + CHECKREG r0, 0x00000017; + CHECKREG r1, 0x00000019; + CHECKREG r2, 0xFFFFFF84; + CHECKREG r3, 0x0000001A; + CHECKREG r4, 0xFFFFFF88; + CHECKREG r5, 0x00000058; + CHECKREG r6, 0x00000028; + CHECKREG r7, 0x00000002; + + R0 = B [ P4 + 47 ] (X); + R1 = B [ P4 + -41 ] (X); + R2 = B [ P4 + 38 ] (X); + R3 = B [ P4 + -31 ] (X); + R4 = B [ P4 + 28 ] (X); + R5 = B [ P4 + 26 ] (X); + R6 = B [ P4 + -22 ] (X); + R7 = B [ P4 + 105 ] (X); + CHECKREG r0, 0x00000050; + CHECKREG r1, 0xFFFFFF93; + CHECKREG r2, 0x00000049; + CHECKREG r3, 0xFFFFFF99; + CHECKREG r4, 0x00000043; + CHECKREG r5, 0x00000067; + CHECKREG r6, 0xFFFFFFE8; + CHECKREG r7, 0xFFFFFF99; + + R0 = B [ P5 + -14 ] (X); + R1 = B [ P5 + 12 ] (X); + R2 = B [ P5 + -6 ] (X); + R3 = B [ P5 + 4 ] (X); + R4 = B [ P5 + 0 ] (X); + R5 = B [ P5 + -2 ] (X); + R6 = B [ P5 + 8 ] (X); + R7 = B [ P5 + -107 ] (X); + CHECKREG r0, 0x00000035; + CHECKREG r1, 0x00000065; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000057; + CHECKREG r4, 0x00000053; + CHECKREG r5, 0x00000047; + CHECKREG r6, 0x00000061; + CHECKREG r7, 0x00000006; + + R0 = B [ FP + 99 ] (X); + R1 = B [ FP + -15 ] (X); + R2 = B [ FP + 41 ] (X); + R3 = B [ FP + -65 ] (X); + R4 = B [ FP + 25 ] (X); + R5 = B [ FP + -34 ] (X); + R6 = B [ FP + 37 ] (X); + R7 = B [ FP + -97 ] (X); + CHECKREG r0, 0xFFFFFF93; + CHECKREG r1, 0xFFFFFF99; + CHECKREG r2, 0x0000004E; + CHECKREG r3, 0xFFFFFFD7; + CHECKREG r4, 0x00000068; + CHECKREG r5, 0xFFFFFFE8; + CHECKREG r6, 0x0000004A; + CHECKREG r7, 0x0000004C; + + R0 = B [ SP + 46 ] (X); + R1 = B [ SP + -41 ] (X); + R2 = B [ SP + 48 ] (X); + R3 = B [ SP + 51 ] (X); + R4 = B [ SP + -102 ] (X); + R5 = B [ SP + 89 ] (X); + R6 = B [ SP + 62 ] (X); + R7 = B [ SP + 43 ] (X); + CHECKREG r0, 0x00000009; + CHECKREG r1, 0x00000005; + CHECKREG r2, 0x0000000F; + CHECKREG r3, 0x0000000C; + CHECKREG r4, 0x00000009; + CHECKREG r5, 0xFFFFFF88; + CHECKREG r6, 0x00000019; + CHECKREG r7, 0x00000004; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstidxl_ld_dr_xh.s b/sim/testsuite/bfin/c_ldstidxl_ld_dr_xh.s new file mode 100644 index 0000000..7d1dda1 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstidxl_ld_dr_xh.s @@ -0,0 +1,595 @@ +//Original:testcases/core/c_ldstidxl_ld_dr_xh/c_ldstidxl_ld_dr_xh.dsp +// Spec Reference: c_ldstidxl load dreg XH (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym i1, DATA_ADDR_1, 0x70; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + loadsym i3, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + R0 = W [ P1 + 154 ] (X); + R1 = W [ P1 + 84 ] (X); + R2 = W [ P1 + 48 ] (X); + R3 = W [ P1 + 10 ] (X); + R4 = W [ P1 + 34 ] (X); + R5 = W [ P1 + 20 ] (X); + R6 = W [ P1 + 126 ] (X); + R7 = W [ P1 + 154 ] (X); + CHECKREG r0, 0x00000405; + CHECKREG r1, 0x00002425; + CHECKREG r2, 0xFFFF8485; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00001122; + CHECKREG r5, 0x00001617; + CHECKREG r6, 0x00006263; + CHECKREG r7, 0x00000405; + + R0 = W [ P2 + -120 ] (X); + R1 = W [ P2 + -114 ] (X); + R2 = W [ P2 + -36 ] (X); + R3 = W [ P2 + -22 ] (X); + R4 = W [ P2 + -44 ] (X); + R5 = W [ P2 + -6 ] (X); + R6 = W [ P2 + -52 ] (X); + R7 = W [ P2 + -146 ] (X); + CHECKREG r0, 0xFFFFD5D6; + CHECKREG r1, 0xFFFFD7D8; + CHECKREG r2, 0x0000565A; + CHECKREG r3, 0xFFFFA667; + CHECKREG r4, 0xFFFF99EA; + CHECKREG r5, 0x00004C4D; + CHECKREG r6, 0xFFFF99EA; + CHECKREG r7, 0x00004C4D; + + R0 = W [ P3 + 56 ] (X); + R1 = W [ P3 + 62 ] (X); + R2 = W [ P3 + -64 ] (X); + R3 = W [ P3 + 60 ] (X); + R4 = W [ P3 + -56 ] (X); + R5 = W [ P3 + 10 ] (X); + R6 = W [ P3 + -28 ] (X); + R7 = W [ P3 + -110 ] (X); + CHECKREG r0, 0x00001617; + CHECKREG r1, 0x00001819; + CHECKREG r2, 0xFFFF8485; + CHECKREG r3, 0x00001A1B; + CHECKREG r4, 0xFFFF8283; + CHECKREG r5, 0x00005859; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00000001; + + R0 = W [ P4 + 42 ] (X); + R1 = W [ P4 + -40 ] (X); + R2 = W [ P4 + 38 ] (X); + R3 = W [ P4 + -32 ] (X); + R4 = W [ P4 + 28 ] (X); + R5 = W [ P4 + 26 ] (X); + R6 = W [ P4 + -22 ] (X); + R7 = W [ P4 + 106 ] (X); + CHECKREG r0, 0x00004C4D; + CHECKREG r1, 0xFFFF99EA; + CHECKREG r2, 0x00004849; + CHECKREG r3, 0xFFFF99EA; + CHECKREG r4, 0x00004243; + CHECKREG r5, 0xFFFFA667; + CHECKREG r6, 0xFFFF98E8; + CHECKREG r7, 0xFFFF95E8; + + R0 = W [ P5 + -14 ] (X); + R1 = W [ P5 + 12 ] (X); + R2 = W [ P5 + -6 ] (X); + R3 = W [ P5 + 4 ] (X); + R4 = W [ P5 + 0 ] (X); + R5 = W [ P5 + -2 ] (X); + R6 = W [ P5 + 8 ] (X); + R7 = W [ P5 + -108 ] (X); + CHECKREG r0, 0x00003435; + CHECKREG r1, 0x00006465; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00005657; + CHECKREG r4, 0x00005253; + CHECKREG r5, 0x00004647; + CHECKREG r6, 0x00006061; + CHECKREG r7, 0x00000607; + + R0 = W [ FP + 90 ] (X); + R1 = W [ FP + -14 ] (X); + R2 = W [ FP + 42 ] (X); + R3 = W [ FP + -66 ] (X); + R4 = W [ FP + 26 ] (X); + R5 = W [ FP + -34 ] (X); + R6 = W [ FP + 38 ] (X); + R7 = W [ FP + -98 ] (X); + CHECKREG r0, 0xFFFF91E8; + CHECKREG r1, 0xFFFF91E8; + CHECKREG r2, 0x00004C4D; + CHECKREG r3, 0xFFFFD7D8; + CHECKREG r4, 0xFFFFA667; + CHECKREG r5, 0xFFFF95E8; + CHECKREG r6, 0x00004849; + CHECKREG r7, 0x00004C4D; + + R0 = W [ SP + 46 ] (X); + R1 = W [ SP + -42 ] (X); + R2 = W [ SP + 48 ] (X); + R3 = W [ SP + 50 ] (X); + R4 = W [ SP + -102 ] (X); + R5 = W [ SP + 82 ] (X); + R6 = W [ SP + 62 ] (X); + R7 = W [ SP + 46 ] (X); + CHECKREG r0, 0x00000809; + CHECKREG r1, 0x00000506; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00000C0D; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0x00007475; + CHECKREG r6, 0x00001819; + CHECKREG r7, 0x00000809; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstidxl_ld_dreg.s b/sim/testsuite/bfin/c_ldstidxl_ld_dreg.s new file mode 100644 index 0000000..4c25099 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstidxl_ld_dreg.s @@ -0,0 +1,554 @@ +//Original:testcases/core/c_ldstidxl_ld_dreg/c_ldstidxl_ld_dreg.dsp +// Spec Reference: c_ldstidxl load dreg (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; + +// initial values + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + + R0 = [ P1 + 156 ]; + R1 = [ P1 + 84 ]; + R2 = [ P1 + 48 ]; + R3 = [ P1 + 12 ]; + R4 = [ P1 + 36 ]; + R5 = [ P1 + 20 ]; + R6 = [ P1 + 128 ]; + R7 = [ P1 + 156 ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x22232425; + CHECKREG r2, 0x82838485; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x55667788; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x66676869; + CHECKREG r7, 0x08090A0B; + + R0 = [ P2 + -120 ]; + R1 = [ P2 + -112 ]; + R2 = [ P2 + -36 ]; + R3 = [ P2 + -24 ]; + R4 = [ P2 + -44 ]; + R5 = [ P2 + -8 ]; + R6 = [ P2 + -52 ]; + R7 = [ P2 + -148 ]; + CHECKREG r0, 0xD3D4D5D6; + CHECKREG r1, 0xDBDCDDDE; + CHECKREG r2, 0xA455565A; + CHECKREG r3, 0xA667686A; + CHECKREG r4, 0x96E899EA; + CHECKREG r5, 0x4C4D4E4F; + CHECKREG r6, 0x94E899EA; + CHECKREG r7, 0x4C4D4E4F; + + R0 = [ P4 + 44 ]; + R1 = [ P4 + -40 ]; + R2 = [ P4 + 36 ]; + R3 = [ P4 + -32 ]; + R4 = [ P4 + 28 ]; + R5 = [ P4 + 24 ]; + R6 = [ P4 + -20 ]; + R7 = [ P4 + 108 ]; + CHECKREG r0, 0x50515253; + CHECKREG r1, 0x94E899EA; + CHECKREG r2, 0x48494A4B; + CHECKREG r3, 0x96E899EA; + CHECKREG r4, 0x40414243; + CHECKREG r5, 0xA667686A; + CHECKREG r6, 0x99E899EA; + CHECKREG r7, 0x96E899EA; + + R0 = [ P5 + -16 ]; + R1 = [ P5 + 12 ]; + R2 = [ P5 + -8 ]; + R3 = [ P5 + 4 ]; + R4 = [ P5 + 0 ]; + R5 = [ P5 + -4 ]; + R6 = [ P5 + 8 ]; + R7 = [ P5 + -108 ]; + CHECKREG r0, 0x34353637; + CHECKREG r1, 0x62636465; + CHECKREG r2, 0x42434445; + CHECKREG r3, 0x54555657; + CHECKREG r4, 0x50515253; + CHECKREG r5, 0x46474849; + CHECKREG r6, 0x58596061; + CHECKREG r7, 0x04050607; + + R0 = [ FP + 92 ]; + R1 = [ FP + -16 ]; + R2 = [ FP + 40 ]; + R3 = [ FP + -64 ]; + R4 = [ FP + 28 ]; + R5 = [ FP + -32 ]; + R6 = [ FP + 36 ]; + R7 = [ FP + -96 ]; + CHECKREG r0, 0x92E899EA; + CHECKREG r1, 0x91E899EA; + CHECKREG r2, 0x4C4D4E4F; + CHECKREG r3, 0xDBDCDDDE; + CHECKREG r4, 0x40414243; + CHECKREG r5, 0x96E899EA; + CHECKREG r6, 0x48494A4B; + CHECKREG r7, 0x50515253; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstidxl_ld_preg.s b/sim/testsuite/bfin/c_ldstidxl_ld_preg.s new file mode 100644 index 0000000..503c24e --- /dev/null +++ b/sim/testsuite/bfin/c_ldstidxl_ld_preg.s @@ -0,0 +1,672 @@ +//Original:testcases/core/c_ldstidxl_ld_preg/c_ldstidxl_ld_preg.dsp +// Spec Reference: c_ldstidxl load dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym i1, DATA_ADDR_1, 0x70; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + loadsym i3, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + P2 = [ P1 + 12 ]; + P3 = [ P1 + 44 ]; + P4 = [ P1 + 8 ]; + P5 = [ P1 + 156 ]; + SP = [ P1 + 16 ]; + FP = [ P1 + 120 ]; + P1 = [ P1 + 24 ]; + CHECKREG p1, 0x18191A1B; + CHECKREG p2, 0x0C0D0E0F; + CHECKREG p3, 0x74757677; + CHECKREG p4, 0x08090A0B; + CHECKREG p5, 0x08090A0B; + CHECKREG sp, 0x10111213; + CHECKREG fp, 0x58596061; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0xA0; + P3 = I1; SP = I3; + + P1 = [ P2 + -128 ]; + P3 = [ P2 + -36 ]; + P4 = [ P2 + -40 ]; + P5 = [ P2 + -144 ]; + SP = [ P2 + -48 ]; + FP = [ P2 + 52 ]; + P2 = [ P2 + -132 ]; + CHECKREG p1, 0xEBECEDEE; + CHECKREG p2, 0x7C7D7E7F; + CHECKREG p3, 0xA60CAD7E; + CHECKREG p4, 0xA50CAD6E; + CHECKREG p5, 0x70717273; + CHECKREG sp, 0xA30CAD4E; + CHECKREG fp, 0x64656667; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + P1 = [ P3 + 56 ]; + P2 = [ P3 + -104 ]; + P4 = [ P3 + 80 ]; + P5 = [ P3 + -56 ]; + SP = [ P3 + 52 ]; + FP = [ P3 + -48 ]; + P3 = [ P3 + 84 ]; + CHECKREG p1, 0x14151617; + CHECKREG p2, 0x08090A0B; + CHECKREG p3, 0x82838485; + CHECKREG p4, 0x74757677; + CHECKREG p5, 0x80818283; + CHECKREG sp, 0x10111213; + CHECKREG fp, 0x01020304; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_2, 0x70; + P3 = I1; SP = I3; + P1 = [ P4 + 44 ]; + P2 = [ P4 + -40 ]; + P3 = [ P4 + -96 ]; + P5 = [ P4 + -68 ]; + SP = [ P4 + 84 ]; + FP = [ P4 + 108 ]; + P4 = [ P4 + -32 ]; + CHECKREG p1, 0x6C6D6E6F; + CHECKREG p2, 0xAB0CAD03; + CHECKREG p3, 0x70717273; + CHECKREG p4, 0xAB0CAD05; + CHECKREG p5, 0xFBFCFDFE; + CHECKREG sp, 0x03040506; + CHECKREG fp, 0x6C6D6E6F; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + P1 = [ P5 + 16 ]; + P2 = [ P5 + 12 ]; + P3 = [ P5 + 96 ]; + P4 = [ P5 + 0 ]; + SP = [ P5 + -44 ]; + FP = [ P5 + 28 ]; + P5 = [ P5 + -84 ]; + CHECKREG p1, 0x66676869; + CHECKREG p2, 0x62636465; + CHECKREG p3, 0x84858687; + CHECKREG p4, 0x50515253; + CHECKREG p5, 0x1C1D1E1F; + CHECKREG sp, 0x05060708; + CHECKREG fp, 0x72636467; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_2, 0x70; + P3 = I1; SP = I3; + + P1 = [ SP + -72 ]; + P2 = [ SP + 16 ]; + P3 = [ SP + -80 ]; + P4 = [ SP + 92 ]; + P5 = [ SP + -28 ]; + FP = [ SP + 32 ]; + SP = [ SP + -36 ]; + CHECKREG p1, 0xF7F8F9FA; + CHECKREG p2, 0xB455565B; + CHECKREG p3, 0xEBECEDEE; + CHECKREG p4, 0x0B0CAD0E; + CHECKREG p5, 0xAB0CAD06; + CHECKREG sp, 0xAB0CAD04; + CHECKREG fp, 0x60616263; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_2, 0x70; + P3 = I1; SP = I3; + + P1 = [ FP + 40 ]; + P2 = [ FP + 44 ]; + P3 = [ FP + 96 ]; + P4 = [ FP + 52 ]; + P5 = [ FP + 104 ]; + SP = [ FP + 60 ]; + FP = [ FP + 64 ]; + CHECKREG p1, 0x68696A6B; + CHECKREG p2, 0x6C6D6E6F; + CHECKREG p3, 0x60616263; + CHECKREG p4, 0x74757677; + CHECKREG p5, 0x68696A6B; + CHECKREG sp, 0x7C7D7E7F; + CHECKREG fp, 0xEBECEDEE; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xa667686a + +DATA_ADDR_2: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstidxl_st_dr_b.s b/sim/testsuite/bfin/c_ldstidxl_st_dr_b.s new file mode 100644 index 0000000..5ed1a11 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstidxl_st_dr_b.s @@ -0,0 +1,612 @@ +//Original:testcases/core/c_ldstidxl_st_dr_b/c_ldstidxl_st_dr_b.dsp +// Spec Reference: c_ldstidxl store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f5080; + imm32 r1, 0x204e6091; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80b3; + imm32 r4, 0x501b90c4; + imm32 r5, 0x600aa0d5; + imm32 r6, 0x7019b0e6; + imm32 r7, 0xd028c0f7; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xc8; + loadsym i1, DATA_ADDR_1, 0x10; + loadsym p4, DATA_ADDR_2, 0xc8; + loadsym p5, DATA_ADDR_1, 0x00; + loadsym fp, DATA_ADDR_2, 0xc8; + loadsym i3, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + B [ P1 + 0x1101 ] = R0; + B [ P1 + 0x1013 ] = R1; + B [ P1 + 0x1015 ] = R2; + B [ P1 + 0x1007 ] = R3; + B [ P2 + -0x1019 ] = R4; + B [ P2 + -0x1011 ] = R5; + B [ P2 + -0x1013 ] = R6; + B [ P2 + -0x1015 ] = R7; + R6 = B [ P1 + 0x1101 ] (Z); + R5 = B [ P1 + 0x1013 ] (Z); + R4 = B [ P1 + 0x1015 ] (Z); + R3 = B [ P1 + 0x1007 ] (Z); + R2 = B [ P2 + -0x1019 ] (Z); + R7 = B [ P2 + -0x1011 ] (Z); + R0 = B [ P2 + -0x1013 ] (Z); + R1 = B [ P2 + -0x1015 ] (Z); + CHECKREG r0, 0x000000E6; + CHECKREG r1, 0x000000F7; + CHECKREG r2, 0x000000C4; + CHECKREG r3, 0x000000B3; + CHECKREG r4, 0x000000A2; + CHECKREG r5, 0x00000091; + CHECKREG r6, 0x00000080; + CHECKREG r7, 0x000000D5; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + B [ P3 + 0x1011 ] = R0; + B [ P3 + 0x1023 ] = R1; + B [ P3 + 0x1025 ] = R2; + B [ P3 + 0x1027 ] = R3; + B [ P4 + -0x1029 ] = R4; + B [ P4 + -0x1021 ] = R5; + B [ P4 + -0x1033 ] = R6; + B [ P4 + -0x1035 ] = R7; + R3 = B [ P3 + 0x1011 ] (Z); + R4 = B [ P3 + 0x1023 ] (Z); + R0 = B [ P3 + 0x1025 ] (Z); + R1 = B [ P3 + 0x1027 ] (Z); + R2 = B [ P4 + -0x1029 ] (Z); + R5 = B [ P4 + -0x1021 ] (Z); + R6 = B [ P4 + -0x1033 ] (Z); + R7 = B [ P4 + -0x1035 ] (Z); + CHECKREG r0, 0x000000B2; + CHECKREG r1, 0x000000B3; + CHECKREG r2, 0x000000B4; + CHECKREG r3, 0x000000B0; + CHECKREG r4, 0x000000B1; + CHECKREG r5, 0x000000B5; + CHECKREG r6, 0x000000B6; + CHECKREG r7, 0x000000B7; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + B [ P5 + 0x1031 ] = R0; + B [ P5 + 0x1033 ] = R1; + B [ P5 + 0x1035 ] = R2; + B [ P5 + 0x1047 ] = R3; + B [ SP + -0x1049 ] = R4; + B [ SP + -0x1041 ] = R5; + B [ SP + -0x1043 ] = R6; + B [ SP + -0x1045 ] = R7; + R6 = B [ P5 + 0x1031 ] (Z); + R5 = B [ P5 + 0x1033 ] (Z); + R4 = B [ P5 + 0x1035 ] (Z); + R3 = B [ P5 + 0x1047 ] (Z); + R2 = B [ SP + -0x1049 ] (Z); + R0 = B [ SP + -0x1041 ] (Z); + R7 = B [ SP + -0x1043 ] (Z); + R1 = B [ SP + -0x1045 ] (Z); + CHECKREG r0, 0x000000C5; + CHECKREG r1, 0x000000C7; + CHECKREG r2, 0x000000C4; + CHECKREG r3, 0x000000C3; + CHECKREG r4, 0x000000C2; + CHECKREG r5, 0x000000C1; + CHECKREG r6, 0x000000C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + B [ FP + 0x1051 ] = R0; + B [ FP + 0x1053 ] = R1; + B [ FP + 0x1055 ] = R2; + B [ FP + 0x1057 ] = R3; + B [ FP + 0x1059 ] = R4; + B [ FP + 0x1061 ] = R5; + B [ FP + 0x1063 ] = R6; + B [ FP + 0x1065 ] = R7; + R3 = B [ FP + 0x1051 ] (Z); + R4 = B [ FP + 0x1053 ] (Z); + R0 = B [ FP + 0x1055 ] (Z); + R1 = B [ FP + 0x1057 ] (Z); + R2 = B [ FP + 0x1059 ] (Z); + R5 = B [ FP + 0x1061 ] (Z); + R6 = B [ FP + 0x1063 ] (Z); + R7 = B [ FP + 0x1065 ] (Z); + CHECKREG r0, 0x000000D2; + CHECKREG r1, 0x000000D3; + CHECKREG r2, 0x000000D4; + CHECKREG r3, 0x000000D0; + CHECKREG r4, 0x000000D1; + CHECKREG r5, 0x000000D5; + CHECKREG r6, 0x000000D6; + CHECKREG r7, 0x000000D7; + + P3 = I0; SP = I2; + pass + +// Pre-load memory witb known data +// More data is defined than will actually be used + + .data +// Make sure there is space between the text and data sections + .space (0x2000); + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + +// Make sure there is space for us to scribble + .space (0x2000); diff --git a/sim/testsuite/bfin/c_ldstidxl_st_dr_h.s b/sim/testsuite/bfin/c_ldstidxl_st_dr_h.s new file mode 100644 index 0000000..114d192 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstidxl_st_dr_h.s @@ -0,0 +1,609 @@ +//Original:testcases/core/c_ldstidxl_st_dr_h/c_ldstidxl_st_dr_h.dsp +// Spec Reference: c_ldstidxl store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xc8; + loadsym i1, DATA_ADDR_1, 0x10; + loadsym p4, DATA_ADDR_2, 0xc8; + loadsym p5, DATA_ADDR_1, 0x00; + loadsym fp, DATA_ADDR_2, 0xc8; + loadsym i3, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + W [ P1 + 0x1002 ] = R0; + W [ P1 + 0x1004 ] = R1; + W [ P1 + 0x1006 ] = R2; + W [ P1 + 0x1008 ] = R3; + W [ P2 + -0x1010 ] = R4; + W [ P2 + -0x1022 ] = R5; + W [ P2 + -0x1034 ] = R6; + W [ P2 + -0x1046 ] = R7; + R6 = W [ P1 + 0x1002 ] (Z); + R5 = W [ P1 + 0x1004 ] (Z); + R4 = W [ P1 + 0x1006 ] (Z); + R3 = W [ P1 + 0x1008 ] (Z); + R2 = W [ P2 + -0x1010 ] (Z); + R7 = W [ P2 + -0x1022 ] (Z); + R0 = W [ P2 + -0x1034 ] (Z); + R1 = W [ P2 + -0x1046 ] (Z); + CHECKREG r0, 0x0000B0A6; + CHECKREG r1, 0x0000C0A7; + CHECKREG r2, 0x000090A4; + CHECKREG r3, 0x000080A3; + CHECKREG r4, 0x000070A2; + CHECKREG r5, 0x000060A1; + CHECKREG r6, 0x000050A0; + CHECKREG r7, 0x0000A0A5; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + W [ P3 + 0x1018 ] = R0; + W [ P3 + 0x1020 ] = R1; + W [ P3 + 0x1022 ] = R2; + W [ P3 + 0x1024 ] = R3; + W [ P4 + -0x1026 ] = R4; + W [ P4 + -0x1028 ] = R5; + W [ P4 + -0x1030 ] = R6; + W [ P4 + -0x1052 ] = R7; + R3 = W [ P3 + 0x1018 ] (Z); + R4 = W [ P3 + 0x1020 ] (Z); + R0 = W [ P3 + 0x1022 ] (Z); + R1 = W [ P3 + 0x1024 ] (Z); + R2 = W [ P4 + -0x1026 ] (Z); + R5 = W [ P4 + -0x1028 ] (Z); + R6 = W [ P4 + -0x1030 ] (Z); + R7 = W [ P4 + -0x1052 ] (Z); + CHECKREG r0, 0x000070B2; + CHECKREG r1, 0x000080B3; + CHECKREG r2, 0x000090B4; + CHECKREG r3, 0x000050B0; + CHECKREG r4, 0x000060B1; + CHECKREG r5, 0x0000A0B5; + CHECKREG r6, 0x0000B0B6; + CHECKREG r7, 0x0000C0B7; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + W [ P5 + 0x1034 ] = R0; + W [ P5 + 0x1036 ] = R1; + W [ P5 + 0x1038 ] = R2; + W [ P5 + 0x1040 ] = R3; + W [ SP + -0x1042 ] = R4; + W [ SP + -0x1054 ] = R5; + W [ SP + -0x1066 ] = R6; + W [ SP + -0x1078 ] = R7; + R6 = W [ P5 + 0x1034 ] (Z); + R5 = W [ P5 + 0x1036 ] (Z); + R4 = W [ P5 + 0x1038 ] (Z); + R3 = W [ P5 + 0x1040 ] (Z); + R2 = W [ SP + -0x1042 ] (Z); + R0 = W [ SP + -0x1054 ] (Z); + R7 = W [ SP + -0x1066 ] (Z); + R1 = W [ SP + -0x1078 ] (Z); + CHECKREG r0, 0x0000A0C5; + CHECKREG r1, 0x0000C0C7; + CHECKREG r2, 0x000090C4; + CHECKREG r3, 0x000080C3; + CHECKREG r4, 0x000070C2; + CHECKREG r5, 0x000060C1; + CHECKREG r6, 0x000050C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + W [ FP + 0x1050 ] = R0; + W [ FP + 0x1052 ] = R1; + W [ FP + 0x1054 ] = R2; + W [ FP + 0x1056 ] = R3; + W [ FP + 0x1058 ] = R4; + W [ FP + 0x1060 ] = R5; + W [ FP + 0x1062 ] = R6; + W [ FP + 0x1064 ] = R7; + R3 = W [ FP + 0x1050 ] (Z); + R4 = W [ FP + 0x1052 ] (Z); + R0 = W [ FP + 0x1054 ] (Z); + R1 = W [ FP + 0x1056 ] (Z); + R2 = W [ FP + 0x1058 ] (Z); + R5 = W [ FP + 0x1060 ] (Z); + R6 = W [ FP + 0x1062 ] (Z); + R7 = W [ FP + 0x1064 ] (Z); + CHECKREG r0, 0x000070D2; + CHECKREG r1, 0x000080D3; + CHECKREG r2, 0x000090D4; + CHECKREG r3, 0x000050D0; + CHECKREG r4, 0x000060D1; + CHECKREG r5, 0x0000A0D5; + CHECKREG r6, 0x0000B0D6; + CHECKREG r7, 0x0000C0D7; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + .space (0x2000); +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + +// Make sure there is space for us to scribble + .space (0x2000); diff --git a/sim/testsuite/bfin/c_ldstidxl_st_dreg.s b/sim/testsuite/bfin/c_ldstidxl_st_dreg.s new file mode 100644 index 0000000..ac1f028 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstidxl_st_dreg.s @@ -0,0 +1,780 @@ +//Original:testcases/core/c_ldstidxl_st_dreg/c_ldstidxl_st_dreg.dsp +// Spec Reference: c_ldstidxl store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xc8; + loadsym i1, DATA_ADDR_1, 0x10; + loadsym p4, DATA_ADDR_2, 0xc8; + loadsym p5, DATA_ADDR_1, 0x00; + loadsym fp, DATA_ADDR_2, 0xc8; + loadsym i3, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + [ P1 + 0x1004 ] = R0; + [ P1 + 0x1008 ] = R1; + [ P1 + 0x1010 ] = R2; + [ P1 + 0x1014 ] = R3; + [ P2 + -0x1020 ] = R4; + [ P2 + -0x1024 ] = R5; + [ P2 + -0x1028 ] = R6; + [ P2 + -0x1030 ] = R7; + R6 = [ P1 + 0x1004 ]; + R5 = [ P1 + 0x1008 ]; + R4 = [ P1 + 0x1010 ]; + R3 = [ P1 + 0x1014 ]; + R2 = [ P2 + -0x1020 ]; + R7 = [ P2 + -0x1024 ]; + R0 = [ P2 + -0x1028 ]; + R1 = [ P2 + -0x1030 ]; + CHECKREG r0, 0x7019B0A6; + CHECKREG r1, 0xD028C0A7; + CHECKREG r2, 0x501B90A4; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300370A2; + CHECKREG r5, 0x204E60A1; + CHECKREG r6, 0x105F50A0; + CHECKREG r7, 0x600AA0A5; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + [ P3 + 0x1034 ] = R0; + [ P3 + 0x1040 ] = R1; + [ P3 + 0x1044 ] = R2; + [ P3 + 0x1048 ] = R3; + [ P4 + -0x1050 ] = R4; + [ P4 + -0x1054 ] = R5; + [ P4 + -0x1060 ] = R6; + [ P4 + -0x1064 ] = R7; + R3 = [ P3 + 0x1034 ]; + R4 = [ P3 + 0x1040 ]; + R0 = [ P3 + 0x1044 ]; + R1 = [ P3 + 0x1048 ]; + R2 = [ P4 + -0x1050 ]; + R5 = [ P4 + -0x1054 ]; + R6 = [ P4 + -0x1060 ]; + R7 = [ P4 + -0x1064 ]; + CHECKREG r0, 0x30BD70B2; + CHECKREG r1, 0x40BC80B3; + CHECKREG r2, 0x55BB90B4; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x20BE60B1; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B9B0B6; + CHECKREG r7, 0x80B8C0B7; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + [ P5 + 1004 ] = R0; + [ P5 + 1008 ] = R1; + [ P5 + 1012 ] = R2; + [ P5 + 1016 ] = R3; + [ SP + -0x1020 ] = R4; + [ SP + -0x1024 ] = R5; + [ SP + -0x1028 ] = R6; + [ SP + -0x1030 ] = R7; + R6 = [ P5 + 1004 ]; + R4 = [ P5 + 1008 ]; + R5 = [ P5 + 1012 ]; + R3 = [ P5 + 1016 ]; + R2 = [ SP + -0x1020 ]; + R0 = [ SP + -0x1024 ]; + R7 = [ SP + -0x1028 ]; + R1 = [ SP + -0x1030 ]; + CHECKREG r0, 0x60CAA0C5; + CHECKREG r1, 0xD0C8C0C7; + CHECKREG r2, 0x50CB90C4; + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x20CE60C1; + CHECKREG r5, 0x30C370C2; + CHECKREG r6, 0x10CF50C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + [ FP + 0x1034 ] = R0; + [ FP + 0x1040 ] = R1; + [ FP + 0x1044 ] = R2; + [ FP + 0x1048 ] = R3; + [ FP + 0x1050 ] = R4; + [ FP + 0x1054 ] = R5; + [ FP + 0x1060 ] = R6; + [ FP + 0x1064 ] = R7; + + R3 = [ FP + 0x1034 ]; + R4 = [ FP + 0x1040 ]; + R0 = [ FP + 0x1044 ]; + R1 = [ FP + 0x1048 ]; + R2 = [ FP + 0x1050 ]; + R5 = [ FP + 0x1054 ]; + R6 = [ FP + 0x1060 ]; + R7 = [ FP + 0x1064 ]; + CHECKREG r0, 0x80DD70D2; + CHECKREG r1, 0x90DC80D3; + CHECKREG r2, 0xA0DB90D4; + CHECKREG r3, 0x60DF50D0; + CHECKREG r4, 0x70DE60D1; + CHECKREG r5, 0xB0DAA0D5; + CHECKREG r6, 0xC0D9B0D6; + CHECKREG r7, 0xD0D8C0D7; + + P3 = I0; SP = I2; + pass + + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +// Make sure there is space between the text section, and the data section + .space (0x2000); + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_2: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xa263646a + .dd 0xa667686a + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + +// Make sure there is space for us to scribble + .space (0x2000); diff --git a/sim/testsuite/bfin/c_ldstidxl_st_preg.s b/sim/testsuite/bfin/c_ldstidxl_st_preg.s new file mode 100644 index 0000000..6520f82 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstidxl_st_preg.s @@ -0,0 +1,709 @@ +//Original:testcases/core/c_ldstidxl_st_preg/c_ldstidxl_st_preg.dsp +// Spec Reference: c_ldstidxl store preg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + P3 = 0x0123 (X); + P4 = 0x4567 (X); + P5 = 0x79ab (X); + FP = 0x6def (X); + SP = 0x1ace (X); + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x0000; + loadsym p2, DATA_ADDR_2, 0x00c8; + P3 = I1; SP = I3; + + [ P1 + 0x1004 ] = P5; + [ P1 + 0x1008 ] = P3; + [ P1 + 0x1014 ] = P4; + [ P1 + 0x1018 ] = P3; + [ P2 + -0x1020 ] = P4; + [ P2 + -0x1024 ] = P5; + [ P2 + -0x1028 ] = SP; + [ P2 + -0x1034 ] = FP; + R6 = [ P1 + 0x1004 ]; + R5 = [ P1 + 0x1008 ]; + R4 = [ P1 + 0x1014 ]; + R3 = [ P1 + 0x1018 ]; + R2 = [ P2 + -0x1020 ]; + R7 = [ P2 + -0x1024 ]; + R0 = [ P2 + -0x1028 ]; + R1 = [ P2 + -0x1034 ]; + CHECKREG r0, 0x00001ACE; + CHECKREG r1, 0x00006DEF; + CHECKREG r2, 0x00004567; + CHECKREG r3, 0x00000123; + CHECKREG r4, 0x00004567; + CHECKREG r5, 0x00000123; + CHECKREG r6, 0x000079AB; + CHECKREG r7, 0x000079AB; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + P1 = 0x3456 (X); + P2 = 0x1234 (X); + P5 = 0x5e23 (X); + FP = 0x2ac5 (X); + SP = 0x6378 (X); + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_1, 0x0000; + loadsym p4, DATA_ADDR_2, 0x00c8; + P3 = I1; SP = I3; + + [ P3 + 0x1034 ] = P2; + [ P3 + 0x1040 ] = P1; + [ P3 + 0x1044 ] = P2; + [ P3 + 0x1048 ] = P1; + [ P4 + -0x1054 ] = P2; + [ P4 + -0x1058 ] = P5; + [ P4 + -0x1060 ] = SP; + [ P4 + -0x1064 ] = FP; + R3 = [ P3 + 0x1034 ]; + R4 = [ P3 + 0x1040 ]; + R0 = [ P3 + 0x1044 ]; + R1 = [ P3 + 0x1048 ]; + R2 = [ P4 + -0x1054 ]; + R5 = [ P4 + -0x1058 ]; + R6 = [ P4 + -0x1060 ]; + R7 = [ P4 + -0x1064 ]; + CHECKREG r0, 0x00001234; + CHECKREG r1, 0x00003456; + CHECKREG r2, 0x00001234; + CHECKREG r3, 0x00001234; + CHECKREG r4, 0x00003456; + CHECKREG r5, 0x00005E23; + CHECKREG r6, 0x00006378; + CHECKREG r7, 0x00002AC5; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + P1 = 0x2125 (X); + P2 = 0x7345 (X); + P3 = 0x3230 (X); + P4 = 0x5789 (X); + FP = 0x5bcd (X); + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x0000; + loadsym i3, DATA_ADDR_2, 0x00c8; + P3 = I1; SP = I3; + + [ P5 + 0x1004 ] = P2; + [ P5 + 0x1008 ] = P1; + [ P5 + 0x1014 ] = P2; + [ P5 + 0x1018 ] = P3; + [ SP + -0x1020 ] = P4; + [ SP + -0x1024 ] = P2; + [ SP + -0x1028 ] = P3; + [ SP + -0x1034 ] = FP; + R6 = [ P5 + 0x1004 ]; + R5 = [ P5 + 0x1008 ]; + R4 = [ P5 + 0x1014 ]; + R3 = [ P5 + 0x1018 ]; + R2 = [ SP + -0x1020 ]; + R0 = [ SP + -0x1024 ]; + R7 = [ SP + -0x1028 ]; + R1 = [ SP + -0x1034 ]; + CHECKREG r0, 0x00007345; + CHECKREG r1, 0x00005BCD; + CHECKREG r2, 0x00005789; + CHECKREG r3, 0x00003230; + CHECKREG r4, 0x00007345; + CHECKREG r5, 0x00002125; + CHECKREG r6, 0x00007345; + CHECKREG r7, 0x00003230; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + P1 = 0x5bcd (X); + P2 = 0x1122 (X); + P3 = 0x3455 (X); + P4 = 0x6677 (X); + P5 = 0x58ab (X); + SP = 0x1ace (X); + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0x0010; + P3 = I1; SP = I3; + [ FP + 0x1034 ] = P1; + [ FP + 0x2040 ] = P1; + [ FP + 0x1144 ] = P2; + [ FP + 0x2048 ] = P3; + [ FP + 0x1050 ] = P4; + [ FP + 0x2058 ] = P5; + [ FP + 0x1160 ] = P2; + [ FP + 0x2064 ] = SP; + R3 = [ FP + 0x1034 ]; + R4 = [ FP + 0x2040 ]; + R0 = [ FP + 0x1144 ]; + R1 = [ FP + 0x2048 ]; + R2 = [ FP + 0x1050 ]; + R5 = [ FP + 0x2058 ]; + R6 = [ FP + 0x1160 ]; + R7 = [ FP + 0x2064 ]; + CHECKREG r0, 0x00001122; + CHECKREG r1, 0x00003455; + CHECKREG r2, 0x00006677; + CHECKREG r3, 0x00005BCD; + CHECKREG r4, 0x00005BCD; + CHECKREG r5, 0x000058AB; + CHECKREG r6, 0x00001122; + CHECKREG r7, 0x00001ace; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +// Make sure there is space between the text and data sections + .space (0x2000); + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_2: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + +// Make sure there is space for us to scribble + .space (0x2000); diff --git a/sim/testsuite/bfin/c_ldstii_ld_dr_h.s b/sim/testsuite/bfin/c_ldstii_ld_dr_h.s new file mode 100644 index 0000000..a2daecd --- /dev/null +++ b/sim/testsuite/bfin/c_ldstii_ld_dr_h.s @@ -0,0 +1,541 @@ +//Original:testcases/core/c_ldstii_ld_dr_h/c_ldstii_ld_dr_h.dsp +// Spec Reference: c_ldstii load dreg h +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x04; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_1, 0x00; + loadsym p5, DATA_ADDR_2, 0x00; + loadsym fp, DATA_ADDR_3, 0x00; + loadsym i3, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + R0 = W [ P1 + 0 ] (Z); + R1 = W [ P1 + 4 ] (Z); + R2 = W [ P1 + 8 ] (Z); + R3 = W [ P1 + 12 ] (Z); + R4 = W [ P1 + 16 ] (Z); + R5 = W [ P1 + 20 ] (Z); + R6 = W [ P1 + 24 ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000607; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000E0F; + CHECKREG r4, 0x00001213; + CHECKREG r5, 0x00001617; + CHECKREG r6, 0x00001A1B; + + R0 = W [ P2 + 28 ] (Z); + R1 = W [ P2 + 32 ] (Z); + R2 = W [ P2 + 36 ] (Z); + R3 = W [ P2 + 40 ] (Z); + R4 = W [ P2 + 44 ] (Z); + R5 = W [ P2 + 48 ] (Z); + R6 = W [ P2 + 52 ] (Z); + CHECKREG r0, 0x00009394; + CHECKREG r1, 0x00009798; + CHECKREG r2, 0x0000A2A3; + CHECKREG r3, 0x0000A7A8; + CHECKREG r4, 0x0000B1B2; + CHECKREG r5, 0x0000B5B6; + CHECKREG r6, 0x0000B9C0; + + R0 = W [ P3 + 56 ] (Z); + R1 = W [ P3 + 60 ] (Z); + R2 = W [ P3 + 64 ] (Z); + R3 = W [ P3 + 60 ] (Z); + R4 = W [ P3 + 56 ] (Z); + R5 = W [ P3 + 52 ] (Z); + R6 = W [ P3 + 48 ] (Z); + CHECKREG r0, 0x000099EA; + CHECKREG r1, 0x000099EA; + CHECKREG r2, 0x000099EA; + CHECKREG r3, 0x000099EA; + CHECKREG r4, 0x000099EA; + CHECKREG r5, 0x0000E5E6; + CHECKREG r6, 0x0000E1E2; + + R0 = W [ P4 + 44 ] (Z); + R1 = W [ P4 + 40 ] (Z); + R2 = W [ P4 + 36 ] (Z); + R3 = W [ P4 + 32 ] (Z); + R4 = W [ P4 + 28 ] (Z); + R5 = W [ P4 + 24 ] (Z); + R6 = W [ P4 + 20 ] (Z); + CHECKREG r0, 0x00007677; + CHECKREG r1, 0x00007273; + CHECKREG r2, 0x00007788; + CHECKREG r3, 0x00003344; + CHECKREG r4, 0x00001E1F; + CHECKREG r5, 0x00001A1B; + CHECKREG r6, 0x00001617; + + R0 = W [ P5 + 16 ] (Z); + R1 = W [ P5 + 12 ] (Z); + R2 = W [ P5 + 8 ] (Z); + R3 = W [ P5 + 4 ] (Z); + R4 = W [ P5 + 0 ] (Z); + R5 = W [ P5 + 4 ] (Z); + R6 = W [ P5 + 8 ] (Z); + CHECKREG r0, 0x00003233; + CHECKREG r1, 0x00002E2F; + CHECKREG r2, 0x00002A2B; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00002223; + CHECKREG r5, 0x00002627; + CHECKREG r6, 0x00002A2B; + + R0 = W [ FP + 12 ] (Z); + R1 = W [ FP + 16 ] (Z); + R2 = W [ FP + 20 ] (Z); + R3 = W [ FP + 24 ] (Z); + R4 = W [ FP + 28 ] (Z); + R5 = W [ FP + 32 ] (Z); + R6 = W [ FP + 36 ] (Z); + CHECKREG r0, 0x00004E4F; + CHECKREG r1, 0x00005253; + CHECKREG r2, 0x00005657; + CHECKREG r3, 0x00005A5B; + CHECKREG r4, 0x0000C7C8; + CHECKREG r5, 0x0000CBCD; + CHECKREG r6, 0x0000D1D2; + + R0 = W [ SP + 40 ] (Z); + R1 = W [ SP + 44 ] (Z); + R2 = W [ SP + 48 ] (Z); + R3 = W [ SP + 52 ] (Z); + R4 = W [ SP + 56 ] (Z); + R5 = W [ SP + 60 ] (Z); + R6 = W [ SP + 64 ] (Z); + CHECKREG r0, 0x0000F9FA; + CHECKREG r1, 0x0000FDFE; + CHECKREG r2, 0x00000102; + CHECKREG r3, 0x00000506; + CHECKREG r4, 0x0000090A; + CHECKREG r5, 0x0000AD0E; + CHECKREG r6, 0x0000AD01; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstii_ld_dr_xh.s b/sim/testsuite/bfin/c_ldstii_ld_dr_xh.s new file mode 100644 index 0000000..07b097f --- /dev/null +++ b/sim/testsuite/bfin/c_ldstii_ld_dr_xh.s @@ -0,0 +1,541 @@ +//Original:testcases/core/c_ldstii_ld_dr_xh/c_ldstii_ld_dr_xh.dsp +// Spec Reference: c_ldstii load dreg xh +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x04; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_1, 0x00; + loadsym p5, DATA_ADDR_2, 0x00; + loadsym fp, DATA_ADDR_3, 0x00; + loadsym i3, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + R0 = W [ P1 + 0 ] (X); + R1 = W [ P1 + 4 ] (X); + R2 = W [ P1 + 8 ] (X); + R3 = W [ P1 + 12 ] (X); + R4 = W [ P1 + 16 ] (X); + R5 = W [ P1 + 20 ] (X); + R6 = W [ P1 + 24 ] (X); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000607; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000E0F; + CHECKREG r4, 0x00001213; + CHECKREG r5, 0x00001617; + CHECKREG r6, 0x00001A1B; + + R0 = W [ P2 + 28 ] (X); + R1 = W [ P2 + 32 ] (X); + R2 = W [ P2 + 36 ] (X); + R3 = W [ P2 + 40 ] (X); + R4 = W [ P2 + 44 ] (X); + R5 = W [ P2 + 48 ] (X); + R6 = W [ P2 + 52 ] (X); + CHECKREG r0, 0xFFFF9394; + CHECKREG r1, 0xFFFF9798; + CHECKREG r2, 0xFFFFA2A3; + CHECKREG r3, 0xFFFFA7A8; + CHECKREG r4, 0xFFFFB1B2; + CHECKREG r5, 0xFFFFB5B6; + CHECKREG r6, 0xFFFFB9C0; + + R0 = W [ P3 + 56 ] (X); + R1 = W [ P3 + 60 ] (X); + R2 = W [ P3 + 64 ] (X); + R3 = W [ P3 + 60 ] (X); + R4 = W [ P3 + 56 ] (X); + R5 = W [ P3 + 52 ] (X); + R6 = W [ P3 + 48 ] (X); + CHECKREG r0, 0xFFFF99EA; + CHECKREG r1, 0xFFFF99EA; + CHECKREG r2, 0xFFFF99EA; + CHECKREG r3, 0xFFFF99EA; + CHECKREG r4, 0xFFFF99EA; + CHECKREG r5, 0xFFFFE5E6; + CHECKREG r6, 0xFFFFE1E2; + + R0 = W [ P4 + 44 ] (X); + R1 = W [ P4 + 40 ] (X); + R2 = W [ P4 + 36 ] (X); + R3 = W [ P4 + 32 ] (X); + R4 = W [ P4 + 28 ] (X); + R5 = W [ P4 + 24 ] (X); + R6 = W [ P4 + 20 ] (X); + CHECKREG r0, 0x00007677; + CHECKREG r1, 0x00007273; + CHECKREG r2, 0x00007788; + CHECKREG r3, 0x00003344; + CHECKREG r4, 0x00001E1F; + CHECKREG r5, 0x00001A1B; + CHECKREG r6, 0x00001617; + + R0 = W [ P5 + 16 ] (X); + R1 = W [ P5 + 12 ] (X); + R2 = W [ P5 + 8 ] (X); + R3 = W [ P5 + 4 ] (X); + R4 = W [ P5 + 0 ] (X); + R5 = W [ P5 + 4 ] (X); + R6 = W [ P5 + 8 ] (X); + CHECKREG r0, 0x00003233; + CHECKREG r1, 0x00002E2F; + CHECKREG r2, 0x00002A2B; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00002223; + CHECKREG r5, 0x00002627; + CHECKREG r6, 0x00002A2B; + + R0 = W [ FP + 12 ] (X); + R1 = W [ FP + 16 ] (X); + R2 = W [ FP + 20 ] (X); + R3 = W [ FP + 24 ] (X); + R4 = W [ FP + 28 ] (X); + R5 = W [ FP + 32 ] (X); + R6 = W [ FP + 36 ] (X); + CHECKREG r0, 0x00004E4F; + CHECKREG r1, 0x00005253; + CHECKREG r2, 0x00005657; + CHECKREG r3, 0x00005A5B; + CHECKREG r4, 0xFFFFC7C8; + CHECKREG r5, 0xFFFFCBCD; + CHECKREG r6, 0xFFFFD1D2; + + R0 = W [ SP + 40 ] (X); + R1 = W [ SP + 44 ] (X); + R2 = W [ SP + 48 ] (X); + R3 = W [ SP + 52 ] (X); + R4 = W [ SP + 56 ] (X); + R5 = W [ SP + 60 ] (X); + R6 = W [ SP + 64 ] (X); + CHECKREG r0, 0xFFFFF9FA; + CHECKREG r1, 0xFFFFFDFE; + CHECKREG r2, 0x00000102; + CHECKREG r3, 0x00000506; + CHECKREG r4, 0x0000090A; + CHECKREG r5, 0xFFFFAD0E; + CHECKREG r6, 0xFFFFAD01; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstii_ld_dreg.s b/sim/testsuite/bfin/c_ldstii_ld_dreg.s new file mode 100644 index 0000000..00757f3 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstii_ld_dreg.s @@ -0,0 +1,540 @@ +//Original:testcases/core/c_ldstii_ld_dreg/c_ldstii_ld_dreg.dsp +// Spec Reference: c_ldstii load dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x04; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_1, 0x00; + loadsym p5, DATA_ADDR_2, 0x00; + loadsym fp, DATA_ADDR_3, 0x00; + loadsym i3, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + R0 = [ P1 + 0 ]; + R1 = [ P1 + 4 ]; + R2 = [ P1 + 8 ]; + R3 = [ P1 + 12 ]; + R4 = [ P1 + 16 ]; + R5 = [ P1 + 20 ]; + R6 = [ P1 + 24 ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x18191A1B; + + R0 = [ P2 + 28 ]; + R1 = [ P2 + 32 ]; + R2 = [ P2 + 36 ]; + R3 = [ P2 + 40 ]; + R4 = [ P2 + 44 ]; + R5 = [ P2 + 48 ]; + R6 = [ P2 + 52 ]; + CHECKREG r0, 0x91929394; + CHECKREG r1, 0x95969798; + CHECKREG r2, 0x99A1A2A3; + CHECKREG r3, 0xA5A6A7A8; + CHECKREG r4, 0xA9B0B1B2; + CHECKREG r5, 0xB3B4B5B6; + CHECKREG r6, 0xB7B8B9C0; + + R0 = [ P3 + 56 ]; + R1 = [ P3 + 60 ]; + R2 = [ P3 + 64 ]; + R3 = [ P3 + 60 ]; + R4 = [ P3 + 56 ]; + R5 = [ P3 + 52 ]; + R6 = [ P3 + 48 ]; + CHECKREG r0, 0x91E899EA; + CHECKREG r1, 0x92E899EA; + CHECKREG r2, 0x93E899EA; + CHECKREG r3, 0x92E899EA; + CHECKREG r4, 0x91E899EA; + CHECKREG r5, 0xE3E4E5E6; + CHECKREG r6, 0xDFE0E1E2; + + R0 = [ P4 + 44 ]; + R1 = [ P4 + 40 ]; + R2 = [ P4 + 36 ]; + R3 = [ P4 + 32 ]; + R4 = [ P4 + 28 ]; + R5 = [ P4 + 24 ]; + R6 = [ P4 + 20 ]; + CHECKREG r0, 0x74757677; + CHECKREG r1, 0x99717273; + CHECKREG r2, 0x55667788; + CHECKREG r3, 0x11223344; + CHECKREG r4, 0x1C1D1E1F; + CHECKREG r5, 0x18191A1B; + CHECKREG r6, 0x14151617; + + R0 = [ P5 + 16 ]; + R1 = [ P5 + 12 ]; + R2 = [ P5 + 8 ]; + R3 = [ P5 + 4 ]; + R4 = [ P5 + 0 ]; + R5 = [ P5 + 4 ]; + R6 = [ P5 + 8 ]; + CHECKREG r0, 0x30313233; + CHECKREG r1, 0x2C2D2E2F; + CHECKREG r2, 0x28292A2B; + CHECKREG r3, 0x24252627; + CHECKREG r4, 0x20212223; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x28292A2B; + + R0 = [ FP + 12 ]; + R1 = [ FP + 16 ]; + R2 = [ FP + 20 ]; + R3 = [ FP + 24 ]; + R4 = [ FP + 28 ]; + R5 = [ FP + 32 ]; + R6 = [ FP + 36 ]; + CHECKREG r0, 0x4C4D4E4F; + CHECKREG r1, 0x50515253; + CHECKREG r2, 0x54555657; + CHECKREG r3, 0x58595A5B; + CHECKREG r4, 0xC5C6C7C8; + CHECKREG r5, 0xC9CACBCD; + CHECKREG r6, 0xCFD0D1D2; + + R0 = [ SP + 40 ]; + R1 = [ SP + 44 ]; + R2 = [ SP + 48 ]; + R3 = [ SP + 52 ]; + R4 = [ SP + 56 ]; + R5 = [ SP + 60 ]; + R6 = [ SP + 64 ]; + CHECKREG r0, 0xF7F8F9FA; + CHECKREG r1, 0xFBFCFDFE; + CHECKREG r2, 0xFF000102; + CHECKREG r3, 0x03040506; + CHECKREG r4, 0x0708090A; + CHECKREG r5, 0x0B0CAD0E; + CHECKREG r6, 0xAB0CAD01; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstii_ld_preg.s b/sim/testsuite/bfin/c_ldstii_ld_preg.s new file mode 100644 index 0000000..961b7d3 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstii_ld_preg.s @@ -0,0 +1,564 @@ +//Original:testcases/core/c_ldstii_ld_preg/c_ldstii_ld_preg.dsp +// Spec Reference: c_ldstii load preg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x04; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_1, 0x00; + loadsym p5, DATA_ADDR_2, 0x00; + loadsym fp, DATA_ADDR_3, 0x00; + loadsym i3, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + P2 = [ P1 + 0 ]; + P3 = [ P1 + 4 ]; + P4 = [ P1 + 8 ]; + P5 = [ P1 + 12 ]; + SP = [ P1 + 16 ]; + FP = [ P1 + 20 ]; + P1 = [ P1 + 24 ]; + CHECKREG p1, 0x18191A1B; + CHECKREG p2, 0x00010203; + CHECKREG p3, 0x04050607; + CHECKREG p4, 0x08090A0B; + CHECKREG p5, 0x0C0D0E0F; + CHECKREG sp, 0x10111213; + CHECKREG fp, 0x14151617; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x04; + P3 = I1; SP = I3; + + P1 = [ P2 + 28 ]; + P3 = [ P2 + 36 ]; + P4 = [ P2 + 40 ]; + P5 = [ P2 + 44 ]; + SP = [ P2 + 48 ]; + FP = [ P2 + 52 ]; + P2 = [ P2 + 32 ]; + CHECKREG p1, 0x91929394; + CHECKREG p2, 0x95969798; + CHECKREG p3, 0x99A1A2A3; + CHECKREG p4, 0xA5A6A7A8; + CHECKREG p5, 0xA9B0B1B2; + CHECKREG sp, 0xB3B4B5B6; + CHECKREG fp, 0xB7B8B9C0; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + + P1 = [ P3 + 56 ]; + P2 = [ P3 + 60 ]; + P4 = [ P3 + 60 ]; + P5 = [ P3 + 56 ]; + SP = [ P3 + 52 ]; + FP = [ P3 + 48 ]; + P3 = [ P3 + 64 ]; + CHECKREG p1, 0xE3E4E5E6; + CHECKREG p2, 0x91E899EA; + CHECKREG p3, 0x92E899EA; + CHECKREG p4, 0x91E899EA; + CHECKREG p5, 0xE3E4E5E6; + CHECKREG sp, 0xDFE0E1E2; + CHECKREG fp, 0xDBDCDDDE; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + P1 = [ P4 + 44 ]; + P2 = [ P4 + 40 ]; + P3 = [ P4 + 36 ]; + P5 = [ P4 + 28 ]; + SP = [ P4 + 24 ]; + FP = [ P4 + 20 ]; + P4 = [ P4 + 32 ]; + CHECKREG p1, 0xFBFCFDFE; + CHECKREG p2, 0xF7F8F9FA; + CHECKREG p3, 0xF3F4F5F6; + CHECKREG p4, 0xEBECEDEE; + CHECKREG p5, 0x7C7D7E7F; + CHECKREG sp, 0x78797A7B; + CHECKREG fp, 0x74757677; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + P1 = [ P5 + 16 ]; + P2 = [ P5 + 12 ]; + P3 = [ P5 + 8 ]; + P4 = [ P5 + 0 ]; + SP = [ P5 + 4 ]; + FP = [ P5 + 8 ]; + P5 = [ P5 + 4 ]; + CHECKREG p1, 0x10111213; + CHECKREG p2, 0x0C0D0E0F; + CHECKREG p3, 0x08090A0B; + CHECKREG p4, 0x00010203; + CHECKREG p5, 0x04050607; + CHECKREG sp, 0x04050607; + CHECKREG fp, 0x08090A0B; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + + P1 = [ SP + 12 ]; + P2 = [ SP + 16 ]; + P3 = [ SP + 20 ]; + P4 = [ SP + 24 ]; + P5 = [ SP + 28 ]; + FP = [ SP + 32 ]; + SP = [ SP + 36 ]; + CHECKREG p1, 0x2C2D2E2F; + CHECKREG p2, 0x30313233; + CHECKREG p3, 0x34353637; + CHECKREG p4, 0x38393A3B; + CHECKREG p5, 0x3C3D3E3F; + CHECKREG sp, 0x95969798; + CHECKREG fp, 0x91929394; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + + P1 = [ FP + 40 ]; + P2 = [ FP + 44 ]; + P3 = [ FP + 48 ]; + P4 = [ FP + 52 ]; + P5 = [ FP + 56 ]; + SP = [ FP + 60 ]; + FP = [ FP + 64 ]; + CHECKREG p1, 0xD3D4D5D6; + CHECKREG p2, 0xD7D8D9DA; + CHECKREG p3, 0xDBDCDDDE; + CHECKREG p4, 0xDFE0E1E2; + CHECKREG p5, 0xE3E4E5E6; + CHECKREG sp, 0x91E899EA; + CHECKREG fp, 0x92E899EA; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstii_st_dr_h.s b/sim/testsuite/bfin/c_ldstii_st_dr_h.s new file mode 100644 index 0000000..2f85534 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstii_st_dr_h.s @@ -0,0 +1,605 @@ +//Original:/testcases/core/c_ldstii_st_dr_h/c_ldstii_st_dr_h.dsp +// Spec Reference: c_ldstii store dreg +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_1; + loadsym fp, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym sp, DATA_ADDR_3; +.endif + + W [ P1 + 2 ] = R0; + W [ P1 + 4 ] = R1; + W [ P1 + 6 ] = R2; + W [ P1 + 8 ] = R3; + W [ P2 + 10 ] = R4; + W [ P2 + 12 ] = R5; + W [ P2 + 14 ] = R6; + W [ P2 + 16 ] = R7; + R6 = W [ P1 + 2 ] (Z); + R5 = W [ P1 + 4 ] (Z); + R4 = W [ P1 + 6 ] (Z); + R3 = W [ P1 + 8 ] (Z); + R2 = W [ P2 + 10 ] (Z); + R7 = W [ P2 + 12 ] (Z); + R0 = W [ P2 + 14 ] (Z); + R1 = W [ P2 + 16 ] (Z); + CHECKREG r0, 0x0000B0A6; + CHECKREG r1, 0x0000C0A7; + CHECKREG r2, 0x000090A4; + CHECKREG r3, 0x000080A3; + CHECKREG r4, 0x000070A2; + CHECKREG r5, 0x000060A1; + CHECKREG r6, 0x000050A0; + CHECKREG r7, 0x0000A0A5; + +.ifndef BFIN_HOST + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + W [ P3 + 18 ] = R0; + W [ P3 + 20 ] = R1; + W [ P3 + 22 ] = R2; + W [ P3 + 24 ] = R3; + W [ P4 + 26 ] = R4; + W [ P4 + 28 ] = R5; + W [ P4 + 30 ] = R6; + W [ P4 + 32 ] = R7; + R3 = W [ P3 + 18 ] (Z); + R4 = W [ P3 + 20 ] (Z); + R0 = W [ P3 + 22 ] (Z); + R1 = W [ P3 + 24 ] (Z); + R2 = W [ P4 + 26 ] (Z); + R5 = W [ P4 + 28 ] (Z); + R6 = W [ P4 + 30 ] (Z); + R7 = W [ P4 + 32 ] (Z); + CHECKREG r0, 0x000070B2; + CHECKREG r1, 0x000080B3; + CHECKREG r2, 0x000090B4; + CHECKREG r3, 0x000050B0; + CHECKREG r4, 0x000060B1; + CHECKREG r5, 0x0000A0B5; + CHECKREG r6, 0x0000B0B6; + CHECKREG r7, 0x0000C0B7; +.endif + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + W [ P5 + 34 ] = R0; + W [ P5 + 36 ] = R1; + W [ P5 + 38 ] = R2; + W [ P5 + 40 ] = R3; +.ifndef BFIN_HOST + W [ SP + 42 ] = R4; + W [ SP + 44 ] = R5; + W [ SP + 46 ] = R6; + W [ SP + 48 ] = R7; +.endif + R6 = W [ P5 + 34 ] (Z); + R5 = W [ P5 + 36 ] (Z); + R4 = W [ P5 + 38 ] (Z); + R3 = W [ P5 + 40 ] (Z); +.ifndef BFIN_HOST + R2 = W [ SP + 42 ] (Z); + R0 = W [ SP + 44 ] (Z); + R7 = W [ SP + 46 ] (Z); + R1 = W [ SP + 48 ] (Z); + + CHECKREG r0, 0x0000A0C5; + CHECKREG r1, 0x0000C0C7; + CHECKREG r2, 0x000090C4; +.endif + CHECKREG r3, 0x000080C3; + CHECKREG r4, 0x000070C2; + CHECKREG r5, 0x000060C1; + CHECKREG r6, 0x000050C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + W [ FP + 50 ] = R0; + W [ FP + 52 ] = R1; + W [ FP + 54 ] = R2; + W [ FP + 56 ] = R3; + W [ FP + 58 ] = R4; + W [ FP + 60 ] = R5; + W [ FP + 62 ] = R6; + W [ FP + 64 ] = R7; + R3 = W [ FP + 50 ] (Z); + R4 = W [ FP + 52 ] (Z); + R0 = W [ FP + 54 ] (Z); + R1 = W [ FP + 56 ] (Z); + R2 = W [ FP + 58 ] (Z); + R5 = W [ FP + 60 ] (Z); + R6 = W [ FP + 62 ] (Z); + R7 = W [ FP + 64 ] (Z); + CHECKREG r0, 0x000070D2; + CHECKREG r1, 0x000080D3; + CHECKREG r2, 0x000090D4; + CHECKREG r3, 0x000050D0; + CHECKREG r4, 0x000060D1; + CHECKREG r5, 0x0000A0D5; + CHECKREG r6, 0x0000B0D6; + CHECKREG r7, 0x0000C0D7; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstii_st_dreg.s b/sim/testsuite/bfin/c_ldstii_st_dreg.s new file mode 100644 index 0000000..af04cd5 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstii_st_dreg.s @@ -0,0 +1,640 @@ +//Original:/testcases/core/c_ldstii_st_dreg/c_ldstii_st_dreg.dsp +// Spec Reference: c_ldstii store dreg +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_1; + loadsym fp, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym sp, DATA_ADDR_3; +.endif + + [ P1 + 4 ] = R0; + [ P1 + 8 ] = R1; + [ P1 + 12 ] = R2; + [ P1 + 16 ] = R3; + [ P2 + 20 ] = R4; + [ P2 + 24 ] = R5; + [ P2 + 28 ] = R6; + [ P2 + 32 ] = R7; + R6 = [ P1 + 4 ]; + R5 = [ P1 + 8 ]; + R4 = [ P1 + 12 ]; + R3 = [ P1 + 16 ]; + R2 = [ P2 + 20 ]; + R7 = [ P2 + 24 ]; + R0 = [ P2 + 28 ]; + R1 = [ P2 + 32 ]; + CHECKREG r0, 0x7019B0A6; + CHECKREG r1, 0xD028C0A7; + CHECKREG r2, 0x501B90A4; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300370A2; + CHECKREG r5, 0x204E60A1; + CHECKREG r6, 0x105F50A0; + CHECKREG r7, 0x600AA0A5; + +.ifndef BFIN_HOST + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + [ P3 + 36 ] = R0; + [ P3 + 40 ] = R1; + [ P3 + 44 ] = R2; + [ P3 + 48 ] = R3; + [ P4 + 52 ] = R4; + [ P4 + 56 ] = R5; + [ P4 + 60 ] = R6; + [ P4 + 64 ] = R7; + R3 = [ P3 + 36 ]; + R4 = [ P3 + 40 ]; + R0 = [ P3 + 44 ]; + R1 = [ P3 + 48 ]; + R2 = [ P4 + 52 ]; + R5 = [ P4 + 56 ]; + R6 = [ P4 + 60 ]; + R7 = [ P4 + 64 ]; + CHECKREG r0, 0x30BD70B2; + CHECKREG r1, 0x40BC80B3; + CHECKREG r2, 0x55BB90B4; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x20BE60B1; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B9B0B6; + CHECKREG r7, 0x80B8C0B7; +.endif + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + [ P5 + 4 ] = R0; + [ P5 + 8 ] = R1; + [ P5 + 12 ] = R2; + [ P5 + 16 ] = R3; +.ifndef BFIN_HOST + [ SP + 20 ] = R4; + [ SP + 24 ] = R5; + [ SP + 28 ] = R6; + [ SP + 32 ] = R7; +.endif + R6 = [ P5 + 4 ]; + R5 = [ P5 + 8 ]; + R4 = [ P5 + 12 ]; + R3 = [ P5 + 16 ]; +.ifndef BFIN_HOST + R2 = [ SP + 20 ]; + R0 = [ SP + 24 ]; + R7 = [ SP + 28 ]; + R1 = [ SP + 32 ]; + CHECKREG r0, 0x60CAA0C5; + CHECKREG r1, 0xD0C8C0C7; + CHECKREG r2, 0x50CB90C4; +.endif + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x30C370C2; + CHECKREG r5, 0x20CE60C1; + CHECKREG r6, 0x10CF50C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + [ FP + 36 ] = R0; + [ FP + 40 ] = R1; + [ FP + 44 ] = R2; + [ FP + 48 ] = R3; + [ FP + 52 ] = R4; + [ FP + 56 ] = R5; + [ FP + 60 ] = R6; + [ FP + 64 ] = R7; + R3 = [ FP + 36 ]; + R4 = [ FP + 40 ]; + R0 = [ FP + 44 ]; + R1 = [ FP + 48 ]; + R2 = [ FP + 52 ]; + R5 = [ FP + 56 ]; + R6 = [ FP + 60 ]; + R7 = [ FP + 64 ]; + CHECKREG r0, 0x80DD70D2; + CHECKREG r1, 0x90DC80D3; + CHECKREG r2, 0xA0DB90D4; + CHECKREG r3, 0x60DF50D0; + CHECKREG r4, 0x70DE60D1; + CHECKREG r5, 0xB0DAA0D5; + CHECKREG r6, 0xC0D9B0D6; + CHECKREG r7, 0xD0D8C0D7; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstii_st_preg.s b/sim/testsuite/bfin/c_ldstii_st_preg.s new file mode 100644 index 0000000..126bd4d --- /dev/null +++ b/sim/testsuite/bfin/c_ldstii_st_preg.s @@ -0,0 +1,603 @@ +//Original:/testcases/core/c_ldstii_st_preg/c_ldstii_st_preg.dsp +// Spec Reference: c_ldstii store preg +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + P4 = 0x4567 (X); + P5 = 0x79ab (X); + FP = 0x6def (X); + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + + [ P1 + 8 ] = P4; + [ P1 + 12 ] = P5; + [ P2 + 20 ] = P4; + [ P2 + 24 ] = P5; + [ P2 + 32 ] = FP; + R5 = [ P1 + 8 ]; + R4 = [ P1 + 12 ]; + R2 = [ P2 + 20 ]; + R7 = [ P2 + 24 ]; + R1 = [ P2 + 32 ]; + CHECKREG r1, 0x00006DEF; + CHECKREG r2, 0x00004567; + CHECKREG r4, 0x000079AB; + CHECKREG r5, 0x00004567; + CHECKREG r7, 0x000079AB; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + P1 = 0x3456 (X); + P2 = 0x1234 (X); + P5 = 0x5e23 (X); + FP = 0x2ac5 (X); + loadsym p4, DATA_ADDR_4; + + [ P4 + 52 ] = P2; + [ P4 + 56 ] = P5; + [ P4 + 64 ] = FP; + R2 = [ P4 + 52 ]; + R5 = [ P4 + 56 ]; + R7 = [ P4 + 64 ]; + CHECKREG r2, 0x00001234; + CHECKREG r5, 0x00005E23; + CHECKREG r7, 0x00002AC5; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + P1 = 0x2125 (X); + P2 = 0x7345 (X); + P4 = 0x5789 (X); + FP = 0x5bcd (X); + loadsym p5, DATA_ADDR_1; + + [ P5 + 4 ] = P2; + [ P5 + 8 ] = P1; + [ P5 + 12 ] = P2; + R6 = [ P5 + 4 ]; + R5 = [ P5 + 8 ]; + R4 = [ P5 + 12 ]; + CHECKREG r4, 0x00007345; + CHECKREG r5, 0x00002125; + CHECKREG r6, 0x00007345; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + P1 = 0x5bcd (X); + P2 = 0x1122 (X); + P4 = 0x6677 (X); + P5 = 0x58ab (X); + loadsym fp, DATA_ADDR_2; + [ FP + 36 ] = P4; + [ FP + 40 ] = P1; + [ FP + 44 ] = P2; + [ FP + 52 ] = P4; + [ FP + 56 ] = P5; + [ FP + 64 ] = P2; + R3 = [ FP + 36 ]; + R4 = [ FP + 40 ]; + R0 = [ FP + 44 ]; + R2 = [ FP + 52 ]; + R5 = [ FP + 56 ]; + R7 = [ FP + 64 ]; + CHECKREG r0, 0x00001122; + CHECKREG r2, 0x00006677; + CHECKREG r3, 0x00006677; + CHECKREG r4, 0x00005BCD; + CHECKREG r5, 0x000058AB; + CHECKREG r7, 0x00001122; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstiifp_ld_dreg.s b/sim/testsuite/bfin/c_ldstiifp_ld_dreg.s new file mode 100644 index 0000000..ad5cb82 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstiifp_ld_dreg.s @@ -0,0 +1,528 @@ +//Original:testcases/core/c_ldstiifp_ld_dreg/c_ldstiifp_ld_dreg.dsp +// Spec Reference: c_ldstiifp load dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + P1 = 0x0000; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0000; + P5 = 0x0000; + SP = 0x0000; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + r0 = [ fp + 0 ]; + R1 = [ FP + 4 ]; + R2 = [ FP + 8 ]; + R3 = [ FP + 12 ]; + R4 = [ FP + 16 ]; + R5 = [ FP + 20 ]; + R6 = [ FP + 24 ]; + R7 = [ FP + 28 ]; + CHECKREG r0, 0x86878889; + CHECKREG r1, 0x80818283; + CHECKREG r2, 0x84858687; + CHECKREG r3, 0x01020304; + CHECKREG r4, 0x05060708; + CHECKREG r5, 0x09101112; + CHECKREG r6, 0x14151617; + + R0 = [ FP + 32 ]; + R1 = [ FP + 36 ]; + R2 = [ FP + 40 ]; + R3 = [ FP + 44 ]; + R4 = [ FP + 48 ]; + R5 = [ FP + 52 ]; + R7 = [ FP + 56 ]; + CHECKREG r0, 0x22232425; + CHECKREG r1, 0x26272829; + CHECKREG r2, 0x30313233; + CHECKREG r3, 0x34353637; + CHECKREG r4, 0x38394041; + CHECKREG r5, 0x42434445; + CHECKREG r6, 0x14151617; + + R0 = [ FP + 56 ]; + R1 = [ FP + 60 ]; + R2 = [ FP + 64 ]; + R3 = [ FP + 68 ]; + R4 = [ FP + 72 ]; + R5 = [ FP + 76 ]; + R6 = [ FP + 80 ]; + CHECKREG r0, 0x46474849; + CHECKREG r1, 0x50515253; + CHECKREG r2, 0x54555657; + CHECKREG r3, 0x58596061; + CHECKREG r4, 0x62636465; + CHECKREG r5, 0x66676869; + CHECKREG r6, 0x74555657; + + R0 = [ FP + 84 ]; + R1 = [ FP + 88 ]; + R2 = [ FP + 92 ]; + R3 = [ FP + 96 ]; + R4 = [ FP + 100 ]; + R5 = [ FP + 104 ]; + R6 = [ FP + 108 ]; + CHECKREG r0, 0x78596067; + CHECKREG r1, 0x72636467; + CHECKREG r2, 0x76676867; + CHECKREG r3, 0x20212223; + CHECKREG r4, 0x24252627; + CHECKREG r5, 0x28292A2B; + CHECKREG r6, 0x2C2D2E2F; + + R0 = [ FP + 112 ]; + R1 = [ FP + 116 ]; + R2 = [ FP + 120 ]; + R3 = [ FP + 124 ]; + R4 = [ FP + 128 ]; + R5 = [ FP + -4 ]; + R6 = [ FP + -8 ]; + CHECKREG r0, 0x30313233; + CHECKREG r1, 0x34353637; + CHECKREG r2, 0x38393A3B; + CHECKREG r3, 0x3C3D3E3F; + CHECKREG r4, 0x91929394; + CHECKREG r5, 0x82838485; + CHECKREG r6, 0x74757677; + + R0 = [ FP + -12 ]; + R1 = [ FP + -16 ]; + R2 = [ FP + -20 ]; + R3 = [ FP + -24 ]; + R4 = [ FP + -28 ]; + R5 = [ FP + -32 ]; + R6 = [ FP + -36 ]; + CHECKREG r0, 0x99717273; + CHECKREG r1, 0x55667788; + CHECKREG r2, 0x11223344; + CHECKREG r3, 0x1C1D1E1F; + CHECKREG r4, 0x18191A1B; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x10111213; + + R0 = [ FP + -40 ]; + R1 = [ FP + -44 ]; + R2 = [ FP + -48 ]; + R3 = [ FP + -64 ]; + R4 = [ FP + -88 ]; + R5 = [ FP + -96 ]; + R6 = [ FP + -128 ]; + CHECKREG r0, 0x0C0D0E0F; + CHECKREG r1, 0x08090A0B; + CHECKREG r2, 0x04050607; + CHECKREG r3, 0x78596067; + CHECKREG r4, 0x50515253; + CHECKREG r5, 0x42434445; + CHECKREG r6, 0x09101112; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstiifp_ld_preg.s b/sim/testsuite/bfin/c_ldstiifp_ld_preg.s new file mode 100644 index 0000000..7945d30 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstiifp_ld_preg.s @@ -0,0 +1,511 @@ +//Original:testcases/core/c_ldstiifp_ld_preg/c_ldstiifp_ld_preg.dsp +// Spec Reference: c_ldstiifp load preg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P3 = I1; SP = I3; + p1 = [ fp + 0 ]; + P2 = [ FP + -4 ]; + P3 = [ FP + -8 ]; + P4 = [ FP + -12 ]; + P5 = [ FP + -16 ]; + SP = [ FP + -20 ]; + FP = [ FP + -24 ]; + CHECKREG p1, 0x86878889; + CHECKREG p2, 0x82838485; + CHECKREG p3, 0x74757677; + CHECKREG p4, 0x99717273; + CHECKREG p5, 0x55667788; + CHECKREG sp, 0x11223344; + CHECKREG fp, 0x1C1D1E1F; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P1 = [ FP + -28 ]; + P2 = [ FP + -32 ]; + P3 = [ FP + -36 ]; + P4 = [ FP + -40 ]; + P5 = [ FP + -44 ]; + SP = [ FP + -48 ]; + FP = [ FP + -52 ]; + CHECKREG p1, 0x18191A1B; + CHECKREG p2, 0x14151617; + CHECKREG p3, 0x10111213; + CHECKREG p4, 0x0C0D0E0F; + CHECKREG p5, 0x08090A0B; + CHECKREG sp, 0x04050607; + CHECKREG fp, 0x00010203; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P1 = [ FP + -56 ]; + P2 = [ FP + -60 ]; + P3 = [ FP + -64 ]; + P4 = [ FP + -68 ]; + P5 = [ FP + -72 ]; + SP = [ FP + -76 ]; + FP = [ FP + -80 ]; + CHECKREG p1, 0x76676867; + CHECKREG p2, 0x72636467; + CHECKREG p3, 0x78596067; + CHECKREG p4, 0x74555657; + CHECKREG p5, 0x66676869; + CHECKREG sp, 0x62636465; + CHECKREG fp, 0x58596061; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P1 = [ FP + -84 ]; + P2 = [ FP + -88 ]; + P3 = [ FP + -92 ]; + P4 = [ FP + -96 ]; + P5 = [ FP + -100 ]; + SP = [ FP + -104 ]; + FP = [ FP + -108 ]; + CHECKREG p1, 0x54555657; + CHECKREG p2, 0x50515253; + CHECKREG p3, 0x46474849; + CHECKREG p4, 0x42434445; + CHECKREG p5, 0x38394041; + CHECKREG sp, 0x34353637; + CHECKREG fp, 0x30313233; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P1 = [ FP + -112 ]; + P2 = [ FP + -116 ]; + P3 = [ FP + -120 ]; + P4 = [ FP + -124 ]; + P5 = [ FP + -128 ]; + SP = [ FP + -4 ]; + FP = [ FP + -8 ]; + CHECKREG p1, 0x26272829; + CHECKREG p2, 0x22232425; + CHECKREG p3, 0x18192021; + CHECKREG p4, 0x14151617; + CHECKREG p5, 0x09101112; + CHECKREG sp, 0x82838485; + CHECKREG fp, 0x74757677; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstiifp_st_dreg.s b/sim/testsuite/bfin/c_ldstiifp_st_dreg.s new file mode 100644 index 0000000..4d1a363 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstiifp_st_dreg.s @@ -0,0 +1,641 @@ +//Original:testcases/core/c_ldstiifp_st_dreg/c_ldstiifp_st_dreg.dsp +// Spec Reference: c_ldstiifp store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x00; + loadsym i1, DATA_ADDR_3, 0x00; + loadsym p4, DATA_ADDR_4, 0x00; + loadsym p5, DATA_ADDR_1, 0x00; + loadsym i3, DATA_ADDR_3, 0x00; + loadsym fp, DATA_ADDR_1, 0xC8; + P3 = I1; SP = I3; + + [ FP + -4 ] = R0; + [ FP + -8 ] = R1; + [ FP + -12 ] = R2; + [ FP + -16 ] = R3; + [ FP + -20 ] = R4; + [ FP + -24 ] = R5; + [ FP + -28 ] = R6; + [ FP + -32 ] = R7; + R6 = [ FP + -4 ]; + R5 = [ FP + -8 ]; + R4 = [ FP + -12 ]; + R3 = [ FP + -16 ]; + R2 = [ FP + -20 ]; + R7 = [ FP + -24 ]; + R0 = [ FP + -28 ]; + R1 = [ FP + -32 ]; + CHECKREG r0, 0x7019B0A6; + CHECKREG r1, 0xD028C0A7; + CHECKREG r2, 0x501B90A4; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300370A2; + CHECKREG r5, 0x204E60A1; + CHECKREG r6, 0x105F50A0; + CHECKREG r7, 0x600AA0A5; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + [ FP + -36 ] = R0; + [ FP + -40 ] = R1; + [ FP + -44 ] = R2; + [ FP + -48 ] = R3; + [ FP + -52 ] = R4; + [ FP + -56 ] = R5; + [ FP + -60 ] = R6; + [ FP + -64 ] = R7; + R3 = [ FP + -36 ]; + R4 = [ FP + -40 ]; + R0 = [ FP + -44 ]; + R1 = [ FP + -48 ]; + R2 = [ FP + -52 ]; + R5 = [ FP + -56 ]; + R6 = [ FP + -60 ]; + R7 = [ FP + -64 ]; + CHECKREG r0, 0x30BD70B2; + CHECKREG r1, 0x40BC80B3; + CHECKREG r2, 0x55BB90B4; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x20BE60B1; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B9B0B6; + CHECKREG r7, 0x80B8C0B7; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + [ FP + -68 ] = R0; + [ FP + -72 ] = R1; + [ FP + -76 ] = R2; + [ FP + -80 ] = R3; + [ FP + -84 ] = R4; + [ FP + -88 ] = R5; + [ FP + -92 ] = R6; + [ FP + -96 ] = R7; + R6 = [ FP + -68 ]; + R5 = [ FP + -72 ]; + R4 = [ FP + -76 ]; + R3 = [ FP + -80 ]; + R2 = [ FP + -84 ]; + R0 = [ FP + -88 ]; + R7 = [ FP + -92 ]; + R1 = [ FP + -96 ]; + CHECKREG r0, 0x60CAA0C5; + CHECKREG r1, 0xD0C8C0C7; + CHECKREG r2, 0x50CB90C4; + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x30C370C2; + CHECKREG r5, 0x20CE60C1; + CHECKREG r6, 0x10CF50C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + [ FP + -100 ] = R0; + [ FP + -104 ] = R1; + [ FP + -108 ] = R2; + [ FP + -112 ] = R3; + [ FP + -116 ] = R4; + [ FP + -120 ] = R5; + [ FP + -124 ] = R6; + [ FP + -128 ] = R7; + R3 = [ FP + -100 ]; + R4 = [ FP + -104 ]; + R0 = [ FP + -108 ]; + R1 = [ FP + -112 ]; + R2 = [ FP + -116 ]; + R5 = [ FP + -120 ]; + R6 = [ FP + -124 ]; + R7 = [ FP + -128 ]; + CHECKREG r0, 0x80DD70D2; + CHECKREG r1, 0x90DC80D3; + CHECKREG r2, 0xA0DB90D4; + CHECKREG r3, 0x60DF50D0; + CHECKREG r4, 0x70DE60D1; + CHECKREG r5, 0xB0DAA0D5; + CHECKREG r6, 0xC0D9B0D6; + CHECKREG r7, 0xD0D8C0D7; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstiifp_st_preg.s b/sim/testsuite/bfin/c_ldstiifp_st_preg.s new file mode 100644 index 0000000..3a132dc --- /dev/null +++ b/sim/testsuite/bfin/c_ldstiifp_st_preg.s @@ -0,0 +1,618 @@ +//Original:testcases/core/c_ldstiifp_st_preg/c_ldstiifp_st_preg.dsp +// Spec Reference: c_ldstiifp store preg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + imm32 p1, 0x12345678; + imm32 p2, 0x6789abcd; + imm32 p4, 0x24680123; + imm32 p5, 0x57913597; + + loadsym fp, DATA_ADDR_1, 0xC8; + [ FP + -4 ] = P2; + [ FP + -8 ] = P1; + [ FP + -12 ] = P2; + [ FP + -20 ] = P4; + [ FP + -24 ] = P5; + [ FP + -32 ] = P5; + R6 = [ FP + -4 ]; + R5 = [ FP + -8 ]; + R4 = [ FP + -12 ]; + R2 = [ FP + -20 ]; + R7 = [ FP + -24 ]; + R1 = [ FP + -32 ]; + CHECKREG r1, 0x57913597; + CHECKREG r2, 0x24680123; + CHECKREG r4, 0x6789ABCD; + CHECKREG r5, 0x12345678; + CHECKREG r6, 0x6789ABCD; + CHECKREG r7, 0x57913597; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + imm32 p1, 0x11223344; + imm32 p2, 0x2349abcd; + imm32 p4, 0x44556623; + imm32 p5, 0x57913597; + [ FP + -36 ] = P4; + [ FP + -40 ] = P1; + [ FP + -44 ] = P2; + [ FP + -52 ] = P4; + [ FP + -56 ] = P5; + [ FP + -64 ] = P1; + R3 = [ FP + -36 ]; + R4 = [ FP + -40 ]; + R0 = [ FP + -44 ]; + R2 = [ FP + -52 ]; + R5 = [ FP + -56 ]; + R7 = [ FP + -64 ]; + CHECKREG r0, 0x2349ABCD; + CHECKREG r2, 0x44556623; + CHECKREG r3, 0x44556623; + CHECKREG r4, 0x11223344; + CHECKREG r5, 0x57913597; + CHECKREG r7, 0x11223344; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + imm32 p1, 0x19012345; + imm32 p2, 0x2146abcd; + imm32 p4, 0x24680123; + imm32 p5, 0x57913597; + [ FP + -68 ] = P2; + [ FP + -72 ] = P1; + [ FP + -76 ] = P2; + [ FP + -84 ] = P4; + [ FP + -88 ] = P5; + [ FP + -96 ] = P2; + R6 = [ FP + -68 ]; + R5 = [ FP + -72 ]; + R4 = [ FP + -76 ]; + R2 = [ FP + -84 ]; + R0 = [ FP + -88 ]; + R1 = [ FP + -96 ]; + CHECKREG r0, 0x57913597; + CHECKREG r1, 0x2146ABCD; + CHECKREG r2, 0x24680123; + CHECKREG r4, 0x2146ABCD; + CHECKREG r5, 0x19012345; + CHECKREG r6, 0x2146ABCD; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + imm32 p1, 0x13579678; + imm32 p2, 0x2468abcd; + imm32 p4, 0x45678123; + imm32 p5, 0x57913597; + [ FP + -104 ] = P1; + [ FP + -108 ] = P2; + [ FP + -116 ] = P4; + [ FP + -120 ] = P5; + R4 = [ FP + -104 ]; + R0 = [ FP + -108 ]; + R2 = [ FP + -116 ]; + R5 = [ FP + -120 ]; + CHECKREG r0, 0x2468ABCD; + CHECKREG r2, 0x45678123; + CHECKREG r4, 0x13579678; + CHECKREG r5, 0x57913597; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstpmod_ld_dr_hi.s b/sim/testsuite/bfin/c_ldstpmod_ld_dr_hi.s new file mode 100644 index 0000000..982444e --- /dev/null +++ b/sim/testsuite/bfin/c_ldstpmod_ld_dr_hi.s @@ -0,0 +1,411 @@ +//Original:testcases/core/c_ldstpmod_ld_dr_hi/c_ldstpmod_ld_dr_hi.dsp +// Spec Reference: c_ldstpmod load dr hi +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_2, 0x04; + loadsym p2, DATA_ADDR_3, 0x04; + loadsym i1, DATA_ADDR_4, 0x04; + loadsym p4, DATA_ADDR_5, 0x08; + loadsym p5, DATA_ADDR_1, 0x08; + loadsym fp, DATA_ADDR_6, 0x08; + loadsym i3, DATA_ADDR_7, 0x0c; + P3 = I1; SP = I3; + + R0.H = W [ P1 ]; + R1.H = W [ P1 ]; + R2.H = W [ P1 ]; + R3.H = W [ P1 ]; + R4.H = W [ P1 ]; + R5.H = W [ P1 ]; + R6.H = W [ P1 ]; + R7.H = W [ P1 ]; + CHECKREG r0, 0x26270000; + CHECKREG r1, 0x26270000; + CHECKREG r2, 0x26270000; + CHECKREG r3, 0x26270000; + CHECKREG r4, 0x26270000; + CHECKREG r5, 0x26270000; + CHECKREG r6, 0x26270000; + CHECKREG r7, 0x26270000; + + R0.H = W [ P2 ]; + R1.H = W [ P2 ]; + R2.H = W [ P2 ]; + R3.H = W [ P2 ]; + R4.H = W [ P2 ]; + R5.H = W [ P2 ]; + R6.H = W [ P2 ]; + R7.H = W [ P2 ]; + CHECKREG r0, 0x46470000; + CHECKREG r1, 0x46470000; + CHECKREG r2, 0x46470000; + CHECKREG r3, 0x46470000; + CHECKREG r4, 0x46470000; + CHECKREG r5, 0x46470000; + CHECKREG r6, 0x46470000; + CHECKREG r7, 0x46470000; + + R0.H = W [ P3 ]; + R1.H = W [ P3 ]; + R2.H = W [ P3 ]; + R3.H = W [ P3 ]; + R4.H = W [ P3 ]; + R5.H = W [ P3 ]; + R6.H = W [ P3 ]; + R7.H = W [ P3 ]; + CHECKREG r0, 0x66670000; + CHECKREG r1, 0x66670000; + CHECKREG r2, 0x66670000; + CHECKREG r3, 0x66670000; + CHECKREG r4, 0x66670000; + CHECKREG r5, 0x66670000; + CHECKREG r6, 0x66670000; + CHECKREG r7, 0x66670000; + + R0.H = W [ P4 ]; + R1.H = W [ P4 ]; + R2.H = W [ P4 ]; + R3.H = W [ P4 ]; + R4.H = W [ P4 ]; + R5.H = W [ P4 ]; + R6.H = W [ P4 ]; + R7.H = W [ P4 ]; + CHECKREG r0, 0x8A8B0000; + CHECKREG r1, 0x8A8B0000; + CHECKREG r2, 0x8A8B0000; + CHECKREG r3, 0x8A8B0000; + CHECKREG r4, 0x8A8B0000; + CHECKREG r5, 0x8A8B0000; + CHECKREG r6, 0x8A8B0000; + CHECKREG r7, 0x8A8B0000; + + R0.H = W [ P5 ]; + R1.H = W [ P5 ]; + R2.H = W [ P5 ]; + R3.H = W [ P5 ]; + R4.H = W [ P5 ]; + R5.H = W [ P5 ]; + R6.H = W [ P5 ]; + R7.H = W [ P5 ]; + CHECKREG r0, 0x0A0B0000; + CHECKREG r1, 0x0A0B0000; + CHECKREG r2, 0x0A0B0000; + CHECKREG r3, 0x0A0B0000; + CHECKREG r4, 0x0A0B0000; + CHECKREG r5, 0x0A0B0000; + CHECKREG r6, 0x0A0B0000; + CHECKREG r7, 0x0A0B0000; + + R0.H = W [ SP ]; + R1.H = W [ SP ]; + R2.H = W [ SP ]; + R3.H = W [ SP ]; + R4.H = W [ SP ]; + R5.H = W [ SP ]; + R6.H = W [ SP ]; + R7.H = W [ SP ]; + CHECKREG r0, 0x8E8F0000; + CHECKREG r1, 0x8E8F0000; + CHECKREG r2, 0x8E8F0000; + CHECKREG r3, 0x8E8F0000; + CHECKREG r4, 0x8E8F0000; + CHECKREG r5, 0x8E8F0000; + CHECKREG r6, 0x8E8F0000; + CHECKREG r7, 0x8E8F0000; + + R0.H = W [ FP ]; + R1.H = W [ FP ]; + R2.H = W [ FP ]; + R3.H = W [ FP ]; + R4.H = W [ FP ]; + R5.H = W [ FP ]; + R6.H = W [ FP ]; + R7.H = W [ FP ]; + CHECKREG r0, 0x0A0B0000; + CHECKREG r1, 0x0A0B0000; + CHECKREG r2, 0x0A0B0000; + CHECKREG r3, 0x0A0B0000; + CHECKREG r4, 0x0A0B0000; + CHECKREG r5, 0x0A0B0000; + CHECKREG r6, 0x0A0B0000; + CHECKREG r7, 0x0A0B0000; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstpmod_ld_dr_lo.s b/sim/testsuite/bfin/c_ldstpmod_ld_dr_lo.s new file mode 100644 index 0000000..e399a24 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstpmod_ld_dr_lo.s @@ -0,0 +1,410 @@ +//Original:testcases/core/c_ldstpmod_ld_dr_lo/c_ldstpmod_ld_dr_lo.dsp +// Spec Reference: c_ldstpmod load dr lo +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS(0); +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_2, 0x04; + loadsym p2, DATA_ADDR_3, 0x04; + loadsym i1, DATA_ADDR_4, 0x04; + loadsym p4, DATA_ADDR_5, 0x08; + loadsym p5, DATA_ADDR_1, 0x08; + loadsym fp, DATA_ADDR_6, 0x08; + loadsym i3, DATA_ADDR_7, 0x0c; + P3 = I1; SP = I3; + + R0.L = W [ P1 ]; + R1.L = W [ P1 ]; + R2.L = W [ P1 ]; + R3.L = W [ P1 ]; + R4.L = W [ P1 ]; + R5.L = W [ P1 ]; + R6.L = W [ P1 ]; + R7.L = W [ P1 ]; + CHECKREG r0, 0x00002627; + CHECKREG r1, 0x00002627; + CHECKREG r2, 0x00002627; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00002627; + CHECKREG r5, 0x00002627; + CHECKREG r6, 0x00002627; + CHECKREG r7, 0x00002627; + + R0.L = W [ P2 ]; + R1.L = W [ P2 ]; + R2.L = W [ P2 ]; + R3.L = W [ P2 ]; + R4.L = W [ P2 ]; + R5.L = W [ P2 ]; + R6.L = W [ P2 ]; + R7.L = W [ P2 ]; + CHECKREG r0, 0x00004647; + CHECKREG r1, 0x00004647; + CHECKREG r2, 0x00004647; + CHECKREG r3, 0x00004647; + CHECKREG r4, 0x00004647; + CHECKREG r5, 0x00004647; + CHECKREG r6, 0x00004647; + CHECKREG r7, 0x00004647; + + R0.L = W [ P3 ]; + R1.L = W [ P3 ]; + R2.L = W [ P3 ]; + R3.L = W [ P3 ]; + R4.L = W [ P3 ]; + R5.L = W [ P3 ]; + R6.L = W [ P3 ]; + R7.L = W [ P3 ]; + CHECKREG r0, 0x00006667; + CHECKREG r1, 0x00006667; + CHECKREG r2, 0x00006667; + CHECKREG r3, 0x00006667; + CHECKREG r4, 0x00006667; + CHECKREG r5, 0x00006667; + CHECKREG r6, 0x00006667; + CHECKREG r7, 0x00006667; + + R0.L = W [ P4 ]; + R1.L = W [ P4 ]; + R2.L = W [ P4 ]; + R3.L = W [ P4 ]; + R4.L = W [ P4 ]; + R5.L = W [ P4 ]; + R6.L = W [ P4 ]; + R7.L = W [ P4 ]; + CHECKREG r0, 0x00008A8B; + CHECKREG r1, 0x00008A8B; + CHECKREG r2, 0x00008A8B; + CHECKREG r3, 0x00008A8B; + CHECKREG r4, 0x00008A8B; + CHECKREG r5, 0x00008A8B; + CHECKREG r6, 0x00008A8B; + CHECKREG r7, 0x00008A8B; + + R0.L = W [ P5 ]; + R1.L = W [ P5 ]; + R2.L = W [ P5 ]; + R3.L = W [ P5 ]; + R4.L = W [ P5 ]; + R5.L = W [ P5 ]; + R6.L = W [ P5 ]; + R7.L = W [ P5 ]; + CHECKREG r0, 0x00000A0B; + CHECKREG r1, 0x00000A0B; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000A0B; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000A0B; + CHECKREG r6, 0x00000A0B; + CHECKREG r7, 0x00000A0B; + + R0.L = W [ SP ]; + R1.L = W [ SP ]; + R2.L = W [ SP ]; + R3.L = W [ SP ]; + R4.L = W [ SP ]; + R5.L = W [ SP ]; + R6.L = W [ SP ]; + R7.L = W [ SP ]; + CHECKREG r0, 0x00008E8F; + CHECKREG r1, 0x00008E8F; + CHECKREG r2, 0x00008E8F; + CHECKREG r3, 0x00008E8F; + CHECKREG r4, 0x00008E8F; + CHECKREG r5, 0x00008E8F; + CHECKREG r6, 0x00008E8F; + CHECKREG r7, 0x00008E8F; + + R0.L = W [ FP ]; + R1.L = W [ FP ]; + R2.L = W [ FP ]; + R3.L = W [ FP ]; + R4.L = W [ FP ]; + R5.L = W [ FP ]; + R6.L = W [ FP ]; + R7.L = W [ FP ]; + CHECKREG r0, 0x00000A0B; + CHECKREG r1, 0x00000A0B; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000A0B; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000A0B; + CHECKREG r6, 0x00000A0B; + CHECKREG r7, 0x00000A0B; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstpmod_ld_dreg.s b/sim/testsuite/bfin/c_ldstpmod_ld_dreg.s new file mode 100644 index 0000000..cfcdf1d --- /dev/null +++ b/sim/testsuite/bfin/c_ldstpmod_ld_dreg.s @@ -0,0 +1,462 @@ +//Original:testcases/core/c_ldstpmod_ld_dreg/c_ldstpmod_ld_dreg.dsp +// Spec Reference: c_ldstpmod load dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0008; + FP = 0x0008; + SP = 0x000c; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + R0 = [ P5 ++ P3 ]; + R1 = [ P5 ++ P1 ]; + R2 = [ P5 ++ P2 ]; + R3 = [ P5 ++ P3 ]; + R4 = [ P5 ++ P4 ]; + R5 = [ P5 ++ SP ]; + R6 = [ P5 ++ FP ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x18191A1B; + CHECKREG r6, 0x55667788; + +// initial values + P5 = 0x0000; + P2 = 0x0004; + P3 = 0x0008; + P4 = 0x0008; + FP = 0x000c; + SP = 0x000c; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x04; + P3 = I1; SP = I3; + + R0 = [ P1 ++ P5 ]; + R1 = [ P1 ++ P3 ]; + R2 = [ P1 ++ P2 ]; + R3 = [ P1 ++ P3 ]; + R4 = [ P1 ++ P4 ]; + R5 = [ P1 ++ SP ]; + R6 = [ P1 ++ FP ]; + CHECKREG r0, 0x04050607; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x0C0D0E0F; + CHECKREG r3, 0x10111213; + CHECKREG r4, 0x18191A1B; + CHECKREG r5, 0x11223344; + CHECKREG r6, 0x74757677; + +// initial values + P5 = 0x0000; + P1 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0008; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + + R0 = [ P2 ++ P5 ]; + R1 = [ P2 ++ P1 ]; + R2 = [ P2 ++ P4 ]; + R3 = [ P2 ++ P3 ]; + R4 = [ P2 ++ P4 ]; + R5 = [ P2 ++ SP ]; + R6 = [ P2 ++ FP ]; + CHECKREG r0, 0x40414243; + CHECKREG r1, 0x40414243; + CHECKREG r2, 0x44454647; + CHECKREG r3, 0x48494A4B; + CHECKREG r4, 0x4C4D4E4F; + CHECKREG r5, 0x50515253; + CHECKREG r6, 0x54555657; + +// initial values + P5 = 0x0010; + P1 = 0x0004; + P2 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_1, 0x04; + P3 = I1; SP = I3; + + R0 = [ P3 ++ P5 ]; + R1 = [ P3 ++ P1 ]; + R2 = [ P3 ++ P2 ]; + R3 = [ P3 ++ P1 ]; + R4 = [ P3 ++ P4 ]; + R5 = [ P3 ++ SP ]; + R6 = [ P3 ++ FP ]; + CHECKREG r0, 0x04050607; + CHECKREG r1, 0x14151617; + CHECKREG r2, 0x18191A1B; + CHECKREG r3, 0x1C1D1E1F; + CHECKREG r4, 0x11223344; + CHECKREG r5, 0x55667788; + CHECKREG r6, 0x99717273; + +// initial values + P5 = 0x0004; + P1 = 0x0008; + P2 = 0x000C; + P3 = 0x0004; + FP = 0x0008; + SP = 0x0008; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_2, 0x04; + P3 = I1; SP = I3; + + R0 = [ P4 ++ P5 ]; + R1 = [ P4 ++ P1 ]; + R2 = [ P4 ++ P2 ]; + R3 = [ P4 ++ P3 ]; + R4 = [ P4 ++ P2 ]; + R5 = [ P4 ++ SP ]; + R6 = [ P4 ++ FP ]; + CHECKREG r0, 0x24252627; + CHECKREG r1, 0x28292A2B; + CHECKREG r2, 0x30313233; + CHECKREG r3, 0x3C3D3E3F; + CHECKREG r4, 0x91929394; + CHECKREG r5, 0xA5A6A7A8; + CHECKREG r6, 0xB3B4B5B6; + +// initial values + P5 = 0x0000; + P1 = 0x0010; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + SP = 0x0008; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0x04; + P3 = I1; SP = I3; + + R0 = [ FP ++ P5 ]; + R1 = [ FP ++ P1 ]; + R2 = [ FP ++ P2 ]; + R3 = [ FP ++ P3 ]; + R4 = [ FP ++ P4 ]; + R5 = [ FP ++ SP ]; + R6 = [ FP ++ SP ]; + CHECKREG r0, 0x04050607; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x14151617; + CHECKREG r3, 0x18191A1B; + CHECKREG r4, 0x1C1D1E1F; + CHECKREG r5, 0x11223344; + CHECKREG r6, 0x99717273; + +// initial values + P5 = 0x0000; + P1 = 0x0004; + P2 = 0x0008; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_1, 0x08; + P3 = I1; SP = I3; + + R0 = [ SP ++ P5 ]; + R1 = [ SP ++ P1 ]; + R2 = [ SP ++ P2 ]; + R3 = [ SP ++ P3 ]; + R4 = [ SP ++ P4 ]; + R5 = [ SP ++ FP ]; + R6 = [ SP ++ FP ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x08090A0B; + CHECKREG r2, 0x0C0D0E0F; + CHECKREG r3, 0x14151617; + CHECKREG r4, 0x18191A1B; + CHECKREG r5, 0x1C1D1E1F; + CHECKREG r6, 0x11223344; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstpmod_ld_h_xh.s b/sim/testsuite/bfin/c_ldstpmod_ld_h_xh.s new file mode 100644 index 0000000..c3c4eda --- /dev/null +++ b/sim/testsuite/bfin/c_ldstpmod_ld_h_xh.s @@ -0,0 +1,458 @@ +//Original:testcases/core/c_ldstpmod_ld_h_xh/c_ldstpmod_ld_h_xh.dsp +// Spec Reference: c_ldstpmod load dreg h & xh +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + R0 = W [ P5 ++ P1 ] (Z); + R1 = W [ P5 ++ P1 ] (Z); + R2 = W [ P5 ++ P2 ] (Z); + R3 = W [ P5 ++ P3 ] (Z); + R4 = W [ P5 ++ P4 ] (Z); + R5 = W [ P5 ++ SP ] (Z); + R6 = W [ P5 ++ FP ] (Z); + CHECKREG r0, 0x0000A203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x0000B607; + CHECKREG r3, 0x00009405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x0000CE0F; + +// initial values + P5 = 0x0002; + P2 = 0x0002; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + R0 = W [ P1 ++ P5 ] (X); + R1 = W [ P1 ++ P2 ] (X); + R2 = W [ P1 ++ P2 ] (X); + R3 = W [ P1 ++ P3 ] (X); + R4 = W [ P1 ++ P4 ] (X); + R5 = W [ P1 ++ SP ] (X); + R6 = W [ P1 ++ FP ] (X); + CHECKREG r0, 0xFFFFA203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0xFFFFB607; + CHECKREG r3, 0xFFFF9405; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0xFFFFAC0D; + CHECKREG r6, 0x00001011; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P3 = 0x0002; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_3, 0x06; + P3 = I1; SP = I3; + R0 = W [ P2 ++ P5 ] (Z); + R1 = W [ P2 ++ P1 ] (Z); + R2 = W [ P2 ++ P2 ] (Z); + R3 = W [ P2 ++ P3 ] (Z); + R4 = W [ P2 ++ P4 ] (Z); + R5 = W [ P2 ++ SP ] (Z); + R6 = W [ P2 ++ FP ] (Z); + CHECKREG r0, 0x00008445; + CHECKREG r1, 0x00004A4B; + CHECKREG r2, 0x00004849; + CHECKREG r3, 0x00004849; + CHECKREG r4, 0x00004E4F; + CHECKREG r5, 0x00005253; + CHECKREG r6, 0x00005051; + +// initial values + P5 = 0x0004; + P1 = 0x0002; + P2 = 0x0002; + P4 = 0x0004; + FP = 0x1002 (X); + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_1, 0x02; + P3 = I1; SP = I3; + R0 = W [ P3 ++ P5 ] (X); + R1 = W [ P3 ++ P1 ] (X); + R2 = W [ P3 ++ P2 ] (X); + R3 = W [ P3 ++ P3 ] (X); + R4 = W [ P3 ++ P4 ] (X); + R5 = W [ P3 ++ SP ] (X); + R6 = W [ P3 ++ FP ] (X); + CHECKREG r0, 0x00000001; + CHECKREG r1, 0xFFFF9405; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0xFFFFAC0D; + CHECKREG r6, 0x00001213; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + R0 = W [ P4 ++ P5 ] (Z); + R1 = W [ P4 ++ P1 ] (X); + R2 = W [ P4 ++ P2 ] (X); + R3 = W [ P4 ++ P3 ] (Z); + R4 = W [ P4 ++ P4 ] (Z); + R5 = W [ P4 ++ SP ] (X); + R6 = W [ P4 ++ FP ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00002021; + CHECKREG r2, 0x00002627; + CHECKREG r3, 0x0000A425; + CHECKREG r4, 0x00002A2B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0xFFFF8829; + +// initial values + P5 = 0x0000; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0x02; + P3 = I1; SP = I3; + R0 = W [ FP ++ P5 ] (X); + R1 = W [ FP ++ P1 ] (X); + R2 = W [ FP ++ P2 ] (X); + R3 = W [ FP ++ P3 ] (X); + R4 = W [ FP ++ P4 ] (Z); + R5 = W [ FP ++ SP ] (Z); + R6 = W [ FP ++ FP ] (X); + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0xFFFFB607; + CHECKREG r3, 0xFFFF9405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0xFFFFAC0D; + +// initial values + P5 = 0x0000; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_1, 0x04; + P3 = I1; SP = I3; + + R0 = W [ SP ++ P5 ] (Z); + R1 = W [ SP ++ P1 ] (X); + R2 = W [ SP ++ P2 ] (Z); + R3 = W [ SP ++ P3 ] (X); + R4 = W [ SP ++ P4 ] (Z); + R5 = W [ SP ++ P1 ] (X); + R6 = W [ SP ++ FP ] (Z); + CHECKREG r0, 0x0000B607; + CHECKREG r1, 0xFFFFB607; + CHECKREG r2, 0x00009405; + CHECKREG r3, 0x00000A0B; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0xFFFFCE0F; + CHECKREG r6, 0x0000AC0D; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + .space (0x2000); + +DATA_ADDR_1: + .dd 0x0001a203 + .dd 0x9405b607 + .dd 0x08090A0B + .dd 0xaC0DcE0F + .dd 0x10111213 + .dd 0xb415c617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0xa5060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0xc8192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0xb0313233 + .dd 0x34353637 + .dd 0xd8394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0xf0515253 + .dd 0x54555657 + .dd 0xe8596061 + .dd 0x62636465 + .dd 0xf6676869 + .dd 0x74555657 + .dd 0xa8596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0xa4252627 + .dd 0x88292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x84454647 + .dd 0x48494A4B + .dd 0x9C4D4E4F + .dd 0x50515253 + .dd 0xa4555657 + .dd 0xb8595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x90616263 + .dd 0x64656667 + .dd 0xa8696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0xd4757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x08898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x54959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0xa4050607 + .dd 0x08090A0B + .dd 0xfC0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x98191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x74252627 + .dd 0x28292A2B + .dd 0x8C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x98393A3B + .dd 0x3C3D3E3F + .dd 0xb0414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0xdC4D4E4F + .dd 0x50515253 + .dd 0x94555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0xf0616263 + .dd 0xf4656667 + .dd 0xf8696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x10919293 + .dd 0x24959697 + .dd 0x38999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0x54A5A6A7 + .dd 0x68A9AAAB + .dd 0x7CADAEAF + .dd 0xB0B1B2B3 + .dd 0x84B5B6B7 + .dd 0xB8B9BABB + .dd 0x4CBDBEBF + .dd 0xC0C1C2C3 + .dd 0x34C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0x20D1D2D3 + .dd 0xD4D5D6D7 + .dd 0x18D9DADB + .dd 0xDCDDDEDF + .dd 0x00E1E2E3 + .dd 0xE4E5E6E7 + .dd 0x18E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstpmod_ld_lohi.s b/sim/testsuite/bfin/c_ldstpmod_ld_lohi.s new file mode 100644 index 0000000..4223e59 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstpmod_ld_lohi.s @@ -0,0 +1,462 @@ +//Original:testcases/core/c_ldstpmod_ld_lohi/c_ldstpmod_ld_lohi.dsp +// Spec Reference: c_ldstpmod load dreg lo & hi +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + R0.L = W [ P5 ++ P1 ]; + R1.L = W [ P5 ++ P1 ]; + R2.L = W [ P5 ++ P2 ]; + R3.L = W [ P5 ++ P3 ]; + R4.L = W [ P5 ++ P4 ]; + R5.L = W [ P5 ++ SP ]; + R6.L = W [ P5 ++ FP ]; + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00000405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00000E0F; + +// initial values + P5 = 0x0000; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + + R0.H = W [ P1 ++ P5 ]; + R1.H = W [ P1 ++ P2 ]; + R2.H = W [ P1 ++ P2 ]; + R3.H = W [ P1 ++ P3 ]; + R4.H = W [ P1 ++ P4 ]; + R5.H = W [ P1 ++ SP ]; + R6.H = W [ P1 ++ FP ]; + CHECKREG r0, 0x22230203; + CHECKREG r1, 0x22230001; + CHECKREG r2, 0x20210607; + CHECKREG r3, 0x26270405; + CHECKREG r4, 0x24250A0B; + CHECKREG r5, 0x2A2B0809; + CHECKREG r6, 0x28290E0F; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x02; + P3 = I1; SP = I3; + + R0.L = W [ P2 ++ P5 ]; + R0.H = W [ P2 ++ P1 ]; + R1.L = W [ P2 ++ P1 ]; + R1.H = W [ P2 ++ P3 ]; + R2.H = W [ P2 ++ P4 ]; + R2.L = W [ P2 ++ SP ]; + R3.L = W [ P2 ++ FP ]; + CHECKREG r0, 0x26272021; + CHECKREG r1, 0x2A2B2425; + CHECKREG r2, 0x28292E2F; + CHECKREG r3, 0x26272C2D; + CHECKREG r4, 0x24250A0B; + CHECKREG r5, 0x2A2B0809; + CHECKREG r6, 0x28290E0F; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + + R3.L = W [ P3 ++ P5 ]; + R3.H = W [ P3 ++ P1 ]; + R4.L = W [ P3 ++ P2 ]; + R5.H = W [ P3 ++ P1 ]; + R5.L = W [ P3 ++ P4 ]; + R6.H = W [ P3 ++ SP ]; + R6.L = W [ P3 ++ FP ]; + CHECKREG r0, 0x26272021; + CHECKREG r1, 0x2A2B2425; + CHECKREG r2, 0x28292E2F; + CHECKREG r3, 0x40414243; + CHECKREG r4, 0x24254647; + CHECKREG r5, 0x44454A4B; + CHECKREG r6, 0x48494E4F; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + R0.H = W [ P4 ++ P5 ]; + R0.L = W [ P4 ++ P1 ]; + R1.L = W [ P4 ++ P2 ]; + R1.H = W [ P4 ++ P3 ]; + R2.H = W [ P4 ++ P4 ]; + R3.L = W [ P4 ++ SP ]; + R3.H = W [ P4 ++ FP ]; + CHECKREG r0, 0x62636061; + CHECKREG r1, 0x64656667; + CHECKREG r2, 0x6A6B2E2F; + CHECKREG r3, 0x68696A6B; + CHECKREG r4, 0x24254647; + CHECKREG r5, 0x44454A4B; + CHECKREG r6, 0x48494E4F; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + + R0.H = W [ FP ++ P5 ]; + R1.L = W [ FP ++ P1 ]; + R2.H = W [ FP ++ P2 ]; + R3.H = W [ FP ++ P3 ]; + R4.L = W [ FP ++ P4 ]; + R5.H = W [ FP ++ SP ]; + R6.L = W [ FP ++ P1 ]; + CHECKREG r0, 0x82836061; + CHECKREG r1, 0x64658081; + CHECKREG r2, 0x86872E2F; + CHECKREG r3, 0x84856A6B; + CHECKREG r4, 0x24258A8B; + CHECKREG r5, 0x88894A4B; + CHECKREG r6, 0x48498E8F; + +// initial values + P5 = 0x0000; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x00; + P3 = I1; SP = I3; + + R0.L = W [ SP ++ P5 ]; + R1.H = W [ SP ++ P1 ]; + R2.H = W [ SP ++ P2 ]; + R3.L = W [ SP ++ P3 ]; + R4.H = W [ SP ++ P4 ]; + R5.L = W [ SP ++ P5 ]; + R6.H = W [ SP ++ FP ]; + CHECKREG r0, 0x82830203; + CHECKREG r1, 0x02038081; + CHECKREG r2, 0x00012E2F; + CHECKREG r3, 0x84850607; + CHECKREG r4, 0x04058A8B; + CHECKREG r5, 0x88890A0B; + CHECKREG r6, 0x0A0B8E8F; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstpmod_st_dr_hi.s b/sim/testsuite/bfin/c_ldstpmod_st_dr_hi.s new file mode 100644 index 0000000..4e19e60 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstpmod_st_dr_hi.s @@ -0,0 +1,400 @@ +//Original:testcases/core/c_ldstpmod_st_dr_hi/c_ldstpmod_st_dr_hi.dsp +// Spec Reference: c_ldstpmod store dreg hi +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x600f5000; + imm32 r1, 0x700e6001; + imm32 r2, 0x800d7002; + imm32 r3, 0x900c8003; + imm32 r4, 0xa00b9004; + imm32 r5, 0xb00aa005; + imm32 r6, 0xc009b006; + imm32 r7, 0xd008c007; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x02; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_4, 0x06; + loadsym p5, DATA_ADDR_5, 0x08; + loadsym fp, DATA_ADDR_6, 0x0a; + loadsym i3, DATA_ADDR_7, 0x0c; + P3 = I1; SP = I3; + W [ P1 ] = R1.H; + W [ P2 ] = R2.H; + W [ P3 ] = R3.H; + W [ P4 ] = R4.H; + W [ P5 ] = R5.H; + W [ SP ] = R6.H; + W [ FP ] = R0.H; + R6.H = W [ P1 ]; + R5.H = W [ P2 ]; + R4.H = W [ P3 ]; + R3.H = W [ P4 ]; + R2.H = W [ P5 ]; + R0.H = W [ SP ]; + R1.H = W [ FP ]; + CHECKREG r0, 0xC0095000; + CHECKREG r1, 0x600F6001; + CHECKREG r2, 0xB00A7002; + CHECKREG r3, 0xA00B8003; + CHECKREG r4, 0x900C9004; + CHECKREG r5, 0x800DA005; + CHECKREG r6, 0x700EB006; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x0c; + loadsym p2, DATA_ADDR_2, 0x0a; + loadsym i1, DATA_ADDR_3, 0x08; + loadsym p4, DATA_ADDR_4, 0x06; + loadsym p5, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x02; + loadsym i3, DATA_ADDR_7, 0x00; + P3 = I1; SP = I3; + W [ P1 ] = R2.H; + W [ P2 ] = R3.H; + W [ P3 ] = R4.H; + W [ P4 ] = R5.H; + W [ P5 ] = R6.H; + W [ SP ] = R7.H; + W [ FP ] = R1.H; + R1.L = W [ P1 ]; + R2.L = W [ P2 ]; + R3.L = W [ P3 ]; + R4.L = W [ P4 ]; + R5.L = W [ P5 ]; + R6.L = W [ SP ]; + R0.L = W [ FP ]; + CHECKREG r0, 0x105F204E; + CHECKREG r1, 0x204E3003; + CHECKREG r2, 0x3003402C; + CHECKREG r3, 0x402C501B; + CHECKREG r4, 0x501B600A; + CHECKREG r5, 0x600A7019; + CHECKREG r6, 0x7019D028; + +// initial values + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x12345675; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x10; + loadsym p2, DATA_ADDR_2, 0x02; + loadsym i1, DATA_ADDR_3, 0x00; + loadsym p4, DATA_ADDR_4, 0x08; + loadsym p5, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x06; + loadsym i3, DATA_ADDR_7, 0x02; + P3 = I1; SP = I3; + W [ P1 ] = R5.H; + W [ P2 ] = R6.H; + W [ P3 ] = R7.H; + W [ P4 ] = R0.H; + W [ P5 ] = R1.H; + W [ SP ] = R2.H; + W [ FP ] = R3.H; + R5.H = W [ P1 ]; + R4.H = W [ P2 ]; + R3.H = W [ P3 ]; + R2.H = W [ P4 ]; + R1.H = W [ P5 ]; + R0.H = W [ SP ]; + R6.H = W [ FP ]; + CHECKREG r0, 0x30BD50B0; + CHECKREG r1, 0x20BE60B1; + CHECKREG r2, 0x10BF70B2; + CHECKREG r3, 0x80B880B3; + CHECKREG r4, 0x70B990B4; + CHECKREG r5, 0x12345675; + CHECKREG r6, 0x40BCB0B6; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstpmod_st_dr_lo.s b/sim/testsuite/bfin/c_ldstpmod_st_dr_lo.s new file mode 100644 index 0000000..b005545 --- /dev/null +++ b/sim/testsuite/bfin/c_ldstpmod_st_dr_lo.s @@ -0,0 +1,401 @@ +//Original:testcases/core/c_ldstpmod_st_dr_lo/c_ldstpmod_st_dr_lo.dsp +// Spec Reference: c_ldstpmod store dreg lo +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x600f5000; + imm32 r1, 0x700e6001; + imm32 r2, 0x800d7002; + imm32 r3, 0x900c8003; + imm32 r4, 0xa00b9004; + imm32 r5, 0xb00aa005; + imm32 r6, 0xc009b006; + imm32 r7, 0xd008c007; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x02; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_4, 0x06; + loadsym p5, DATA_ADDR_5, 0x08; + loadsym fp, DATA_ADDR_6, 0x0a; + loadsym i3, DATA_ADDR_7, 0x0c; + P3 = I1; SP = I3; + + W [ P1 ] = R1.L; + W [ P2 ] = R2.L; + W [ P3 ] = R3.L; + W [ P4 ] = R4.L; + W [ P5 ] = R5.L; + W [ SP ] = R6.L; + W [ FP ] = R0.L; + R6.L = W [ P1 ]; + R5.L = W [ P2 ]; + R4.L = W [ P3 ]; + R3.L = W [ P4 ]; + R2.L = W [ P5 ]; + R0.L = W [ SP ]; + R1.L = W [ FP ]; + CHECKREG r0, 0x600FB006; + CHECKREG r1, 0x700E5000; + CHECKREG r2, 0x800DA005; + CHECKREG r3, 0x900C9004; + CHECKREG r4, 0xA00B8003; + CHECKREG r5, 0xB00A7002; + CHECKREG r6, 0xC0096001; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x0c; + loadsym p2, DATA_ADDR_2, 0x0a; + loadsym i1, DATA_ADDR_3, 0x08; + loadsym p4, DATA_ADDR_4, 0x06; + loadsym p5, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x02; + loadsym i3, DATA_ADDR_7, 0x00; + P3 = I1; SP = I3; + W [ P1 ] = R2.L; + W [ P2 ] = R3.L; + W [ P3 ] = R4.L; + W [ P4 ] = R5.L; + W [ P5 ] = R6.L; + W [ SP ] = R7.L; + W [ FP ] = R1.L; + R1.L = W [ P1 ]; + R2.L = W [ P2 ]; + R3.L = W [ P3 ]; + R4.L = W [ P4 ]; + R5.L = W [ P5 ]; + R6.L = W [ SP ]; + R0.L = W [ FP ]; + CHECKREG r0, 0x105F60A1; + CHECKREG r1, 0x204E70A2; + CHECKREG r2, 0x300380A3; + CHECKREG r3, 0x402C90A4; + CHECKREG r4, 0x501BA0A5; + CHECKREG r5, 0x600AB0A6; + CHECKREG r6, 0x7019C0A7; + +// initial values + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x10; + loadsym p2, DATA_ADDR_2, 0x02; + loadsym i1, DATA_ADDR_3, 0x00; + loadsym p4, DATA_ADDR_4, 0x08; + loadsym p5, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x06; + loadsym i3, DATA_ADDR_7, 0x02; + P3 = I1; SP = I3; + W [ P1 ] = R5.L; + W [ P2 ] = R6.L; + W [ P3 ] = R7.L; + W [ P4 ] = R0.L; + W [ P5 ] = R1.L; + W [ SP ] = R2.L; + W [ FP ] = R3.L; + R5.L = W [ P1 ]; + R4.L = W [ P2 ]; + R3.L = W [ P3 ]; + R2.L = W [ P4 ]; + R1.L = W [ P5 ]; + R0.L = W [ SP ]; + R6.L = W [ FP ]; + CHECKREG r0, 0x10BF70B2; + CHECKREG r1, 0x20BE60B1; + CHECKREG r2, 0x30BD50B0; + CHECKREG r3, 0x40BCC0B7; + CHECKREG r4, 0x55BBB0B6; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B980B3; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstpmod_st_dreg.s b/sim/testsuite/bfin/c_ldstpmod_st_dreg.s new file mode 100644 index 0000000..e1ec36f --- /dev/null +++ b/sim/testsuite/bfin/c_ldstpmod_st_dreg.s @@ -0,0 +1,623 @@ +//Original:testcases/core/c_ldstpmod_st_dreg/c_ldstpmod_st_dreg.dsp +// Spec Reference: c_ldstpmod store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x600f5000; + imm32 r1, 0x700e6001; + imm32 r2, 0x800d7002; + imm32 r3, 0x900c8003; + imm32 r4, 0xa00b9004; + imm32 r5, 0xb00aa005; + imm32 r6, 0xc009b006; + imm32 r7, 0xd008c007; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0008; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + [ P5 ++ P1 ] = R0; + [ P5 ++ P1 ] = R1; + [ P5 ++ P2 ] = R2; + [ P5 ++ P3 ] = R3; + [ P5 ++ P4 ] = R4; + [ P5 ++ SP ] = R5; + [ P5 ++ FP ] = R6; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0008; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + R6 = [ P5 ++ P1 ]; + R5 = [ P5 ++ P1 ]; + R4 = [ P5 ++ P2 ]; + R3 = [ P5 ++ P3 ]; + R2 = [ P5 ++ P4 ]; + R0 = [ P5 ++ SP ]; + R1 = [ P5 ++ FP ]; + CHECKREG r0, 0xB00AA005; + CHECKREG r1, 0xC009B006; + CHECKREG r2, 0xA00B9004; + CHECKREG r3, 0x900C8003; + CHECKREG r4, 0x800D7002; + CHECKREG r5, 0x700E6001; + CHECKREG r6, 0x600F5000; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + P5 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0008; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + [ P1 ++ P5 ] = R0; + [ P1 ++ P5 ] = R1; + [ P1 ++ P2 ] = R2; + [ P1 ++ P3 ] = R3; + [ P1 ++ P4 ] = R4; + [ P1 ++ SP ] = R5; + [ P1 ++ FP ] = R6; + P5 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0008; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + R6 = [ P1 ++ P5 ]; + R5 = [ P1 ++ P5 ]; + R4 = [ P1 ++ P2 ]; + R3 = [ P1 ++ P3 ]; + R2 = [ P1 ++ P4 ]; + R0 = [ P1 ++ SP ]; + R1 = [ P1 ++ FP ]; + CHECKREG r0, 0x600AA0A5; + CHECKREG r1, 0x7019B0A6; + CHECKREG r2, 0x501B90A4; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300370A2; + CHECKREG r5, 0x204E60A1; + CHECKREG r6, 0x105F50A0; + +// initial values + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + P5 = 0x0004; + P1 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + [ P2 ++ P5 ] = R0; + [ P2 ++ P1 ] = R1; + [ P2 ++ P1 ] = R2; + [ P2 ++ P3 ] = R3; + [ P2 ++ P4 ] = R4; + [ P2 ++ SP ] = R5; + [ P2 ++ FP ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + R3 = [ P2 ++ P5 ]; + R4 = [ P2 ++ P1 ]; + R0 = [ P2 ++ P1 ]; + R1 = [ P2 ++ P3 ]; + R2 = [ P2 ++ P4 ]; + R5 = [ P2 ++ SP ]; + R6 = [ P2 ++ FP ]; + CHECKREG r0, 0x30BD70B2; + CHECKREG r1, 0x40BC80B3; + CHECKREG r2, 0x55BB90B4; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x20BE60B1; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B9B0B6; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + [ P3 ++ P5 ] = R0; + [ P3 ++ P1 ] = R1; + [ P3 ++ P2 ] = R2; + [ P3 ++ P1 ] = R3; + [ P3 ++ P4 ] = R4; + [ P3 ++ SP ] = R5; + [ P3 ++ FP ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + R6 = [ P3 ++ P5 ]; + R5 = [ P3 ++ P1 ]; + R4 = [ P3 ++ P2 ]; + R3 = [ P3 ++ P1 ]; + R2 = [ P3 ++ P4 ]; + R0 = [ P3 ++ SP ]; + R1 = [ P3 ++ FP ]; + CHECKREG r0, 0x60CAA0C5; + CHECKREG r1, 0x70C9B0C6; + CHECKREG r2, 0x50CB90C4; + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x30C370C2; + CHECKREG r5, 0x20CE60C1; + CHECKREG r6, 0x10CF50C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + [ P4 ++ P5 ] = R0; + [ P4 ++ P1 ] = R1; + [ P4 ++ P2 ] = R2; + [ P4 ++ P3 ] = R3; + [ P4 ++ P1 ] = R4; + [ P4 ++ SP ] = R5; + [ P4 ++ FP ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + R5 = [ P4 ++ P5 ]; + R6 = [ P4 ++ P1 ]; + R0 = [ P4 ++ P2 ]; + R1 = [ P4 ++ P3 ]; + R2 = [ P4 ++ P1 ]; + R3 = [ P4 ++ SP ]; + R4 = [ P4 ++ FP ]; + CHECKREG r0, 0x80DD70D2; + CHECKREG r1, 0x90DC80D3; + CHECKREG r2, 0xA0DB90D4; + CHECKREG r3, 0xB0DAA0D5; + CHECKREG r4, 0xC0D9B0D6; + CHECKREG r5, 0x60DF50D0; + CHECKREG r6, 0x70DE60D1; + +// initial values + imm32 r0, 0x1e5f50e0; + imm32 r1, 0x2e4e60e1; + imm32 r2, 0x3e0370e2; + imm32 r3, 0x4e2c80e3; + imm32 r4, 0x5e1b90e4; + imm32 r5, 0x6e0aa0e5; + imm32 r6, 0x7e19b0e6; + imm32 r7, 0xde28c0e7; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x00; + P3 = I1; SP = I3; + [ SP ++ P5 ] = R0; + [ SP ++ P1 ] = R1; + [ SP ++ P2 ] = R2; + [ SP ++ P3 ] = R3; + [ SP ++ P4 ] = R4; + [ SP ++ P1 ] = R5; + [ SP ++ FP ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x00; + P3 = I1; SP = I3; + R6 = [ SP ++ P5 ]; + R5 = [ SP ++ P1 ]; + R4 = [ SP ++ P2 ]; + R3 = [ SP ++ P3 ]; + R2 = [ SP ++ P4 ]; + R0 = [ SP ++ P1 ]; + R1 = [ SP ++ FP ]; + CHECKREG r0, 0x6E0AA0E5; + CHECKREG r1, 0x7E19B0E6; + CHECKREG r2, 0x5E1B90E4; + CHECKREG r3, 0x4E2C80E3; + CHECKREG r4, 0x3E0370E2; + CHECKREG r5, 0x2E4E60E1; + CHECKREG r6, 0x1E5F50E0; + +// initial values + imm32 r0, 0x10ff50f0; + imm32 r1, 0x20fe60f1; + imm32 r2, 0x30fd70f2; + imm32 r3, 0x40fc80f3; + imm32 r4, 0x55fb90f4; + imm32 r5, 0x60faa0f5; + imm32 r6, 0x70f9b0f6; + imm32 r7, 0x80f8c0f7; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x1004 (X); + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x00; + P3 = I1; SP = I3; + [ FP ++ P5 ] = R0; + [ FP ++ P1 ] = R1; + [ FP ++ P2 ] = R2; + [ FP ++ P3 ] = R3; + [ FP ++ P4 ] = R4; + [ FP ++ SP ] = R5; + [ FP ++ P1 ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x00; + P3 = I1; SP = I3; + R3 = [ FP ++ P5 ]; + R4 = [ FP ++ P1 ]; + R0 = [ FP ++ P2 ]; + R1 = [ FP ++ P3 ]; + R2 = [ FP ++ P4 ]; + R5 = [ FP ++ SP ]; + R6 = [ FP ++ P1 ]; + CHECKREG r0, 0x30FD70F2; + CHECKREG r1, 0x40FC80F3; + CHECKREG r2, 0x55FB90F4; + CHECKREG r3, 0x10FF50F0; + CHECKREG r4, 0x20FE60F1; + CHECKREG r5, 0x60FAA0F5; + CHECKREG r6, 0x70F9B0F6; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_ldstpmod_st_lohi.s b/sim/testsuite/bfin/c_ldstpmod_st_lohi.s new file mode 100644 index 0000000..58990ad --- /dev/null +++ b/sim/testsuite/bfin/c_ldstpmod_st_lohi.s @@ -0,0 +1,625 @@ +//Original:testcases/core/c_ldstpmod_st_lohi/c_ldstpmod_st_lohi.dsp +// Spec Reference: c_ldstpmod store dreg lo & hi +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x600f5000; + imm32 r1, 0x700e6001; + imm32 r2, 0x800d7002; + imm32 r3, 0x900c8003; + imm32 r4, 0xa00b9004; + imm32 r5, 0xb00aa005; + imm32 r6, 0xc009b006; + imm32 r7, 0xd008c007; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0006; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + + W [ P5 ++ P1 ] = R0.L; + W [ P5 ++ P1 ] = R1.L; + W [ P5 ++ P2 ] = R2.L; + W [ P5 ++ P3 ] = R3.L; + W [ P5 ++ P4 ] = R4.L; + W [ P5 ++ SP ] = R5.L; + W [ P5 ++ FP ] = R6.L; + + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0006; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + + R6.L = W [ P5 ++ P1 ]; + R5.L = W [ P5 ++ P1 ]; + R4.L = W [ P5 ++ P2 ]; + R3.L = W [ P5 ++ P3 ]; + R2.L = W [ P5 ++ P4 ]; + R0.L = W [ P5 ++ SP ]; + R1.L = W [ P5 ++ FP ]; + CHECKREG r0, 0x600FA005; + CHECKREG r1, 0x700EB006; + CHECKREG r2, 0x800D9004; + CHECKREG r3, 0x900C8003; + CHECKREG r4, 0xA00B7002; + CHECKREG r5, 0xB00A6001; + CHECKREG r6, 0xC0095000; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x204EA0A5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + P5 = 0x0002; + P2 = 0x0002; + P3 = 0x0004; + P4 = 0x0002; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + W [ P1 ++ P5 ] = R0.H; + W [ P1 ++ P2 ] = R1.H; + W [ P1 ++ P2 ] = R2.H; + W [ P1 ++ P3 ] = R3.H; + W [ P1 ++ P4 ] = R4.H; + W [ P1 ++ SP ] = R5.H; + W [ P1 ++ FP ] = R6.H; + P5 = 0x0002; + P2 = 0x0002; + P3 = 0x0004; + P4 = 0x0002; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + R6.H = W [ P1 ++ P5 ]; + R5.H = W [ P1 ++ P2 ]; + R4.H = W [ P1 ++ P2 ]; + R3.H = W [ P1 ++ P3 ]; + R2.H = W [ P1 ++ P4 ]; + R0.H = W [ P1 ++ SP ]; + R1.H = W [ P1 ++ FP ]; + CHECKREG r0, 0x204E50A0; + CHECKREG r1, 0x701960A1; + CHECKREG r2, 0x501B70A2; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300390A4; + CHECKREG r5, 0x204EA0A5; + CHECKREG r6, 0x105FB0A6; + +// initial values + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + P5 = 0x0002; + P1 = 0x0002; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x02; + P3 = I1; SP = I3; + W [ P2 ++ P5 ] = R0.L; + W [ P2 ++ P1 ] = R0.H; + W [ P2 ++ P2 ] = R2.H; + W [ P2 ++ P3 ] = R2.H; + W [ P2 ++ P4 ] = R4.L; + W [ P2 ++ SP ] = R4.H; + W [ P2 ++ FP ] = R6.L; + P5 = 0x0002; + P1 = 0x0002; + P3 = 0x0002; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x02; + P3 = I1; SP = I3; + R3.L = W [ P2 ++ P5 ]; + R3.H = W [ P2 ++ P1 ]; + R0.L = W [ P2 ++ P2 ]; + R0.H = W [ P2 ++ P3 ]; + R2.L = W [ P2 ++ P4 ]; + R2.H = W [ P2 ++ SP ]; + R6.L = W [ P2 ++ FP ]; + CHECKREG r0, 0x30BD30BD; + CHECKREG r1, 0x20BE60B1; + CHECKREG r2, 0x2E2F2A2B; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x55BB90B4; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B955BB; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x02; + P3 = I1; SP = I3; + W [ P3 ++ P5 ] = R1.H; + W [ P3 ++ P1 ] = R1.L; + W [ P3 ++ P2 ] = R3.L; + W [ P3 ++ P2 ] = R3.H; + W [ P3 ++ P4 ] = R5.H; + W [ P3 ++ SP ] = R6.H; + W [ P3 ++ FP ] = R6.L; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x02; + P3 = I1; SP = I3; + R6.L = W [ P3 ++ P5 ]; + R6.H = W [ P3 ++ P1 ]; + R4.H = W [ P3 ++ P2 ]; + R4.L = W [ P3 ++ P2 ]; + R5.L = W [ P3 ++ P4 ]; + R5.H = W [ P3 ++ SP ]; + R1.L = W [ P3 ++ FP ]; + CHECKREG r0, 0x10CF50C0; + CHECKREG r1, 0x20CEB0C6; + CHECKREG r2, 0x30C370C2; + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x80C340CC; + CHECKREG r5, 0x70C960CA; + CHECKREG r6, 0x60C120CE; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x02; + P3 = I1; SP = I3; + W [ P4 ++ P5 ] = R0.L; + W [ P4 ++ P1 ] = R1.H; + W [ P4 ++ P2 ] = R2.L; + W [ P4 ++ P3 ] = R3.H; + W [ P4 ++ P3 ] = R4.H; + W [ P4 ++ SP ] = R5.L; + W [ P4 ++ FP ] = R6.H; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x02; + P3 = I1; SP = I3; + R5.L = W [ P4 ++ P5 ]; + R6.L = W [ P4 ++ P1 ]; + R0.H = W [ P4 ++ P2 ]; + R1.L = W [ P4 ++ P3 ]; + R2.L = W [ P4 ++ P3 ]; + R3.H = W [ P4 ++ SP ]; + R4.H = W [ P4 ++ FP ]; + CHECKREG r0, 0x70D250D0; + CHECKREG r1, 0x70DE90DC; + CHECKREG r2, 0x80DDA0DB; + CHECKREG r3, 0xA0D580D3; + CHECKREG r4, 0xC0D990D4; + CHECKREG r5, 0xB0DA50D0; + CHECKREG r6, 0xC0D970DE; + +// initial values + imm32 r0, 0x1e5f50e0; + imm32 r1, 0x2e4e60e1; + imm32 r2, 0x3e0370e2; + imm32 r3, 0x4e2c80e3; + imm32 r4, 0x5e1b90e4; + imm32 r5, 0x6e0aa0e5; + imm32 r6, 0x7e19b0e6; + imm32 r7, 0xde28c0e7; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0002; + FP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x02; + P3 = I1; SP = I3; + W [ SP ++ P5 ] = R0.H; + W [ SP ++ P1 ] = R1.H; + W [ SP ++ P2 ] = R2.L; + W [ SP ++ P3 ] = R3.L; + W [ SP ++ P4 ] = R4.H; + W [ SP ++ FP ] = R5.H; + W [ SP ++ FP ] = R6.L; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x02; + P3 = I1; SP = I3; + R6.H = W [ SP ++ P5 ]; + R5.H = W [ SP ++ P1 ]; + R4.H = W [ SP ++ P2 ]; + R3.H = W [ SP ++ P3 ]; + R3.L = W [ SP ++ P4 ]; + R0.L = W [ SP ++ FP ]; + R1.L = W [ SP ++ FP ]; + CHECKREG r0, 0x1E5FB0E6; + CHECKREG r1, 0x2E4E1617; + CHECKREG r2, 0x3E0370E2; + CHECKREG r3, 0x80E35E1B; + CHECKREG r4, 0x70E290E4; + CHECKREG r5, 0x2E4EA0E5; + CHECKREG r6, 0x1E5FB0E6; + +// initial values + imm32 r0, 0x10ff50f0; + imm32 r1, 0x20fe60f1; + imm32 r2, 0x30fd70f2; + imm32 r3, 0x40fc80f3; + imm32 r4, 0x55fb90f4; + imm32 r5, 0x60faa0f5; + imm32 r6, 0x70f9b0f6; + imm32 r7, 0x80f8c0f7; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0004; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x02; + P3 = I1; SP = I3; + W [ FP ++ P5 ] = R0.L; + W [ FP ++ P1 ] = R1.H; + W [ FP ++ P2 ] = R2.H; + W [ FP ++ P3 ] = R3.H; + W [ FP ++ P4 ] = R4.L; + W [ FP ++ SP ] = R5.L; + W [ FP ++ SP ] = R6.L; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x02; + P3 = I1; SP = I3; + R3.L = W [ FP ++ P5 ]; + R4.L = W [ FP ++ P1 ]; + R0.H = W [ FP ++ P2 ]; + R1.H = W [ FP ++ P3 ]; + R2.L = W [ FP ++ P4 ]; + R5.H = W [ FP ++ SP ]; + R6.H = W [ FP ++ SP ]; + CHECKREG r0, 0x30FD50F0; + CHECKREG r1, 0x40FC60F1; + CHECKREG r2, 0x30FD90F4; + CHECKREG r3, 0x40FC50F0; + CHECKREG r4, 0x55FB20FE; + CHECKREG r5, 0xA0F5A0F5; + CHECKREG r6, 0x9091B0F6; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/bfin/c_linkage.s b/sim/testsuite/bfin/c_linkage.s new file mode 100644 index 0000000..d7d673e --- /dev/null +++ b/sim/testsuite/bfin/c_linkage.s @@ -0,0 +1,60 @@ +//Original:testcases/core/c_linkage/c_linkage.dsp +// Spec Reference: linkage (link & unlnk) +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS(0); + + loadsym sp, DATA_ADDR_1, 0x24; + p0 = sp; + + FP = 0x0064 (X); + R0 = 5; + RETS = R0; + + LINK 4; // push rets, push fp, fp=sp, sp=sp-framesize (4) + + R1 = 3; + RETS = R1; // initialize rets by a different value + + loadsym p1, SUBR + CALL ( P1 ); + + SP = 0x3333 (X); + + UNLINK; // sp = fp, fp = pop (old fp), rets = pop(old rets), + + R2 = RETS; // for checking + + CHECKREG r0, 0x00000005; + CHECKREG r1, 0x00000003; + CHECKREG r2, 0x00000005; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00001111; + CHECKREG r7, 0x00000000; + CHECKREG fp, 0x00000064; + CC = SP == P0; + if CC JUMP 1f; + fail; +1: + pass + +SUBR: // should jump here + R6.L = 0x1111; + RTS; + R7.L = 0x2222; // should not go here + RTS; + + .data +DATA_ADDR_1: +DATA: + .space (0x0100); + +// Stack Segments + + .space (0x100); +KSTACK: diff --git a/sim/testsuite/bfin/c_logi2op_alshft_mix.s b/sim/testsuite/bfin/c_logi2op_alshft_mix.s new file mode 100644 index 0000000..7e42664 --- /dev/null +++ b/sim/testsuite/bfin/c_logi2op_alshft_mix.s @@ -0,0 +1,143 @@ +//Original:/testcases/core/c_logi2op_alshft_mix/c_logi2op_alshft_mix.dsp +// Spec Reference: Logi2op >>>=, >>=, <<= +# mach: bfin + +.include "testutils.inc" + start + +// Arithmetic >>>= : positive data +imm32 r0, 0x40000000; +imm32 r1, 0x01111111; +imm32 r2, 0x22222222; +imm32 r3, 0x33333333; +imm32 r4, 0x44444444; +imm32 r5, 0x55555555; +imm32 r6, 0x66666666; +imm32 r7, 0x77777777; +R0 >>>= 1; /* r0 = 0x20000000 */ +R1 >>>= 1; /* r1 = 0x00888888 */ +R2 >>>= 2; /* r2 = 0x08888888 */ +R3 >>>= 8; /* r3 = 0x00333333 */ +R4 >>>= 1; /* r4 = 0x22222222 */ +R5 >>>= 27; /* r5 = 0x0000000a */ +R6 >>>= 30; /* r5 = 0x00000001 */ +R7 >>>= 31; /* r5 = 0x00000000 */ +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x00888888; +CHECKREG r2, 0x08888888; +CHECKREG r3, 0x00333333; +CHECKREG r4, 0x22222222; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + + + +// Arithmetic >>>= : negative data , +imm32 r0, 0x80000000; +imm32 r1, 0x81111111; +imm32 r2, 0xa2222222; +imm32 r3, 0xb3333333; +imm32 r4, 0xc4444444; +imm32 r5, 0xd5555555; +imm32 r6, 0xe6666666; +imm32 r7, 0xf7777777; +R0 >>>= 1; /* r0 = 0xc0000000 */ +R1 >>>= 1; /* r1 = 0xc0888888 */ +R2 >>>= 2; /* r2 = 0xe8888888 */ +R3 >>>= 8; /* r3 = 0x00333333 */ +R4 >>>= 1; /* r4 = 0x22222222 */ +R5 >>>= 27; /* r5 = 0x0000000a */ +R6 >>>= 30; /* r5 = 0x00000001 */ +R7 >>>= 31; /* r5 = 0x00000000 */ +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0888888; +CHECKREG r2, 0xe8888888; +CHECKREG r3, 0xffb33333; +CHECKREG r4, 0xe2222222; +CHECKREG r5, 0xfffffffa; +CHECKREG r6, 0xffffffff; +CHECKREG r7, 0xffffffff; + + +// Logical >>>= : positive data +imm32 r0, 0x40000000; +imm32 r1, 0x01111111; +imm32 r2, 0x22222222; +imm32 r3, 0x33333333; +imm32 r4, 0x44444444; +imm32 r5, 0x55555555; +imm32 r6, 0x66666666; +imm32 r7, 0x77777777; +R0 >>= 1; /* r0 = 0x20000000 */ +R1 >>= 1; /* r1 = 0x00888888 */ +R2 >>= 2; /* r2 = 0x08888888 */ +R3 >>= 8; /* r3 = 0x00333333 */ +R4 >>= 1; /* r4 = 0x22222222 */ +R5 >>= 27; /* r5 = 0x0000000a */ +R6 >>= 30; /* r5 = 0x00000001 */ +R7 >>= 31; /* r5 = 0x00000000 */ +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x00888888; +CHECKREG r2, 0x08888888; +CHECKREG r3, 0x00333333; +CHECKREG r4, 0x22222222; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +// Logical >>= : negative data , +imm32 r0, 0x80000000; +imm32 r1, 0x81111111; +imm32 r2, 0xa2222222; +imm32 r3, 0xb3333333; +imm32 r4, 0xc4444444; +imm32 r5, 0xd5555555; +imm32 r6, 0xe6666666; +imm32 r7, 0xf7777777; +R0 >>= 1; /* r0 = 0x40000000 */ +R1 >>= 1; /* r1 = 0x40888888 */ +R2 >>= 2; /* r2 = 0x48888888 */ +R3 >>= 8; /* r3 = 0x40333333 */ +R4 >>= 1; /* r4 = 0xa2222222 */ +R5 >>= 27; /* r5 = 0x0000000a */ +R6 >>= 30; /* r5 = 0x00000001 */ +R7 >>= 31; /* r5 = 0x00000000 */ +CHECKREG r0, 0x40000000; +CHECKREG r1, 0x40888888; +CHECKREG r2, 0x28888888; +CHECKREG r3, 0x00b33333; +CHECKREG r4, 0x62222222; +CHECKREG r5, 0x0000001a; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000001; + + +// Logical <<= : negative data , +imm32 r0, 0x80000000; +imm32 r1, 0x81111111; +imm32 r2, 0xa2222222; +imm32 r3, 0xb3333333; +imm32 r4, 0xc4444444; +imm32 r5, 0xd5555555; +imm32 r6, 0xe6666666; +imm32 r7, 0xf7777777; +R0 <<= 1; /* r0 = 0x00000000 */ +R1 <<= 1; /* r1 = 0x40888888 */ +R2 <<= 2; /* r2 = 0x88888888 */ +R3 <<= 8; /* r3 = 0x33333300 */ +R4 <<= 1; /* r4 = 0x88888888 */ +R5 <<= 27; /* r5 = 0xa8000000 */ +R6 <<= 30; /* r5 = 0x80000000 */ +R7 <<= 31; /* r5 = 0x80000000 */ +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x02222222; +CHECKREG r2, 0x88888888; +CHECKREG r3, 0x33333300; +CHECKREG r4, 0x88888888; +CHECKREG r5, 0xa8000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + // hlt; + +pass diff --git a/sim/testsuite/bfin/c_logi2op_arith_shft.s b/sim/testsuite/bfin/c_logi2op_arith_shft.s new file mode 100644 index 0000000..110feee --- /dev/null +++ b/sim/testsuite/bfin/c_logi2op_arith_shft.s @@ -0,0 +1,223 @@ +//Original:/testcases/core/c_logi2op_arith_shft/c_logi2op_arith_shft.dsp +// Spec Reference: Logi2op >>>= +# mach: bfin + +.include "testutils.inc" + start + + + + + +// Arithmetic >>>= : negative data +// bit 0-7 +imm32 r0, 0x81111111; +imm32 r1, 0x81111111; +imm32 r2, 0x81111111; +imm32 r3, 0x81111111; +imm32 r4, 0x81111111; +imm32 r5, 0x81111111; +imm32 r6, 0x81111111; +imm32 r7, 0x81111111; +R0 >>>= 0; /* r0 = 0x81111111 */ +R1 >>>= 1; /* r1 = 0xC0888888 */ +R2 >>>= 2; /* r2 = 0xE0444444 */ +R3 >>>= 3; /* r3 = 0xF0222222 */ +R4 >>>= 4; /* r4 = 0xF8111111 */ +R5 >>>= 5; /* r5 = 0xFC088888 */ +R6 >>>= 6; /* r6 = 0xFE044444 */ +R7 >>>= 7; /* r7 = 0xFF022222 */ +CHECKREG r0, 0x81111111; +CHECKREG r1, 0xC0888888; +CHECKREG r2, 0xE0444444; +CHECKREG r3, 0xF0222222; +CHECKREG r4, 0xF8111111; +CHECKREG r5, 0xFC088888; +CHECKREG r6, 0xFE044444; +CHECKREG r7, 0xFF022222; + +// bit 8-15 +imm32 r0, 0x82222222; +imm32 r1, 0x82222222; +imm32 r2, 0x82222222; +imm32 r3, 0x82222222; +imm32 r4, 0x82222222; +imm32 r5, 0x82222222; +imm32 r6, 0x82222222; +imm32 r7, 0x82222222; +R0 >>>= 8; /* r0 = 0xFF822222 */ +R1 >>>= 9; /* r1 = 0xFFC11111 */ +R2 >>>= 10; /* r2 = 0xFFE08888 */ +R3 >>>= 11; /* r3 = 0xFFF04444 */ +R4 >>>= 12; /* r4 = 0xFFF82222 */ +R5 >>>= 13; /* r5 = 0xFFFC1111 */ +R6 >>>= 14; /* r6 = 0xFFFE0888 */ +R7 >>>= 15; /* r7 = 0xFFFF0444 */ +CHECKREG r0, 0xFF822222; +CHECKREG r1, 0xFFC11111; +CHECKREG r2, 0xFFE08888; +CHECKREG r3, 0xFFF04444; +CHECKREG r4, 0xFFF82222; +CHECKREG r5, 0xFFFC1111; +CHECKREG r6, 0xFFFE0888; +CHECKREG r7, 0xFFFF0444; + +// bit 16-23 +imm32 r0, 0x83333333; +imm32 r1, 0x83333333; +imm32 r2, 0x83333333; +imm32 r3, 0x83333333; +imm32 r4, 0x83333333; +imm32 r5, 0x83333333; +imm32 r6, 0x83333333; +imm32 r7, 0x83333333; +R0 >>>= 16; /* r0 = 0xFFFF8333 */ +R1 >>>= 17; /* r1 = 0xFFFFC199 */ +R2 >>>= 18; /* r2 = 0xFFFFE0CC */ +R3 >>>= 19; /* r3 = 0xFFFFF066 */ +R4 >>>= 20; /* r4 = 0xFFFFF833 */ +R5 >>>= 21; /* r5 = 0xFFFFFC19 */ +R6 >>>= 22; /* r6 = 0xFFFFFE0C */ +R7 >>>= 23; /* r7 = 0xFFFFFF06 */ +CHECKREG r0, 0xFFFF8333; +CHECKREG r1, 0xFFFFC199; +CHECKREG r2, 0xFFFFE0CC; +CHECKREG r3, 0xFFFFF066; +CHECKREG r4, 0xFFFFF833; +CHECKREG r5, 0xFFFFFC19; +CHECKREG r6, 0xFFFFFE0C; +CHECKREG r7, 0xFFFFFF06; + +// bit 24-31 +imm32 r0, 0x84444444; +imm32 r1, 0x84444444; +imm32 r2, 0x84444444; +imm32 r3, 0x84444444; +imm32 r4, 0x84444444; +imm32 r5, 0x84444444; +imm32 r6, 0x84444444; +imm32 r7, 0x84444444; +R0 >>>= 24; /* r0 = 0xFFFFFF84 */ +R1 >>>= 25; /* r1 = 0xFFFFFFC2 */ +R2 >>>= 26; /* r2 = 0xFFFFFFE1 */ +R3 >>>= 27; /* r3 = 0xFFFFFFF0 */ +R4 >>>= 28; /* r4 = 0xFFFFFFF8 */ +R5 >>>= 29; /* r5 = 0xFFFFFFFC */ +R6 >>>= 30; /* r6 = 0xFFFFFFFE */ +R7 >>>= 31; /* r7 = 0xFFFFFFFF */ +CHECKREG r0, 0xFFFFFF84; +CHECKREG r1, 0xFFFFFFC2; +CHECKREG r2, 0xFFFFFFE1; +CHECKREG r3, 0xFFFFFFF0; +CHECKREG r4, 0xFFFFFFF8; +CHECKREG r5, 0xFFFFFFFC; +CHECKREG r6, 0xFFFFFFFE; +CHECKREG r7, 0xFFFFFFFF; + +// Arithmetic >>>= : positive data +// bit 0-7 +imm32 r0, 0x41111111; +imm32 r1, 0x41111111; +imm32 r2, 0x41111111; +imm32 r3, 0x41111111; +imm32 r4, 0x41111111; +imm32 r5, 0x41111111; +imm32 r6, 0x41111111; +imm32 r7, 0x41111111; +R0 >>>= 0; /* r0 = 0x41111111 */ +R1 >>>= 1; /* r1 = 0x20888888 */ +R2 >>>= 2; /* r2 = 0x10444444 */ +R3 >>>= 3; /* r3 = 0x08222222 */ +R4 >>>= 4; /* r4 = 0x04111111 */ +R5 >>>= 5; /* r5 = 0x02088888 */ +R6 >>>= 6; /* r6 = 0x01044444 */ +R7 >>>= 7; /* r7 = 0x00822222 */ +CHECKREG r0, 0x41111111; +CHECKREG r1, 0x20888888; +CHECKREG r2, 0x10444444; +CHECKREG r3, 0x08222222; +CHECKREG r4, 0x04111111; +CHECKREG r5, 0x02088888; +CHECKREG r6, 0x01044444; +CHECKREG r7, 0x00822222; + +// bit 8-15 +imm32 r0, 0x42222222; +imm32 r1, 0x42222222; +imm32 r2, 0x42222222; +imm32 r3, 0x42222222; +imm32 r4, 0x42222222; +imm32 r5, 0x42222222; +imm32 r6, 0x42222222; +imm32 r7, 0x42222222; +R0 >>>= 8; /* r0 = 0x00422222 */ +R1 >>>= 9; /* r1 = 0x00211111 */ +R2 >>>= 10; /* r2 = 0x00108888 */ +R3 >>>= 11; /* r3 = 0x00084444 */ +R4 >>>= 12; /* r4 = 0x00042222 */ +R5 >>>= 13; /* r5 = 0x00021111 */ +R6 >>>= 14; /* r6 = 0x00010888 */ +R7 >>>= 15; /* r7 = 0x00008444 */ +CHECKREG r0, 0x00422222; +CHECKREG r1, 0x00211111; +CHECKREG r2, 0x00108888; +CHECKREG r3, 0x00084444; +CHECKREG r4, 0x00042222; +CHECKREG r5, 0x00021111; +CHECKREG r6, 0x00010888; +CHECKREG r7, 0x00008444; + +// bit 16-23 +imm32 r0, 0x43333333; +imm32 r1, 0x43333333; +imm32 r2, 0x43333333; +imm32 r3, 0x43333333; +imm32 r4, 0x43333333; +imm32 r5, 0x43333333; +imm32 r6, 0x43333333; +imm32 r7, 0x43333333; +R0 >>>= 16; /* r0 = 0x00004333 */ +R1 >>>= 17; /* r1 = 0x00002199 */ +R2 >>>= 18; /* r2 = 0x000010CC */ +R3 >>>= 19; /* r3 = 0x00000866 */ +R4 >>>= 20; /* r4 = 0x00000433 */ +R5 >>>= 21; /* r5 = 0x00000219 */ +R6 >>>= 22; /* r6 = 0x0000010C */ +R7 >>>= 23; /* r7 = 0x00000086 */ +CHECKREG r0, 0x00004333; +CHECKREG r1, 0x00002199; +CHECKREG r2, 0x000010CC; +CHECKREG r3, 0x00000866; +CHECKREG r4, 0x00000433; +CHECKREG r5, 0x00000219; +CHECKREG r6, 0x0000010C; +CHECKREG r7, 0x00000086; + +// bit 24-31 +imm32 r0, 0x44444444; +imm32 r1, 0x44444444; +imm32 r2, 0x44444444; +imm32 r3, 0x44444444; +imm32 r4, 0x44444444; +imm32 r5, 0x44444444; +imm32 r6, 0x44444444; +imm32 r7, 0x44444444; +R0 >>>= 24; /* r0 = 0x00000044 */ +R1 >>>= 25; /* r1 = 0x00000022 */ +R2 >>>= 26; /* r2 = 0x00000011 */ +R3 >>>= 27; /* r3 = 0x00000008 */ +R4 >>>= 28; /* r4 = 0x00000004 */ +R5 >>>= 29; /* r5 = 0x00000002 */ +R6 >>>= 30; /* r6 = 0x00000001 */ +R7 >>>= 31; /* r7 = 0x00000000 */ +CHECKREG r0, 0x00000044; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000011; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + + +pass diff --git a/sim/testsuite/bfin/c_logi2op_bitclr.s b/sim/testsuite/bfin/c_logi2op_bitclr.s new file mode 100644 index 0000000..b5ca481 --- /dev/null +++ b/sim/testsuite/bfin/c_logi2op_bitclr.s @@ -0,0 +1,92 @@ +//Original:/testcases/core/c_logi2op_bitclr/c_logi2op_bitclr.dsp +// Spec Reference: Logi2op functions: bitclr +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0xffffffff; +imm32 r1, 0xffffffff; +imm32 r2, 0xffffffff; +imm32 r3, 0xffffffff; +imm32 r4, 0xffffffff; +imm32 r5, 0xffffffff; +imm32 r6, 0xffffffff; +imm32 r7, 0xffffffff; + +// bit clr +BITCLR( R0 , 0 ); /* r0 = 0x00000001 */ +BITCLR( R1 , 1 ); /* r1 = 0x00000002 */ +BITCLR( R2 , 2 ); /* r2 = 0x00000004 */ +BITCLR( R3 , 3 ); /* r3 = 0x00000008 */ +BITCLR( R4 , 4 ); /* r4 = 0x00000010 */ +BITCLR( R5 , 5 ); /* r5 = 0x00000020 */ +BITCLR( R6 , 6 ); /* r6 = 0x00000040 */ +BITCLR( R7 , 7 ); /* r7 = 0x00000080 */ +CHECKREG r0, 0xfffffffe; +CHECKREG r1, 0xfffffffd; +CHECKREG r2, 0xfffffffb; +CHECKREG r3, 0xfffffff7; +CHECKREG r4, 0xffffffef; +CHECKREG r5, 0xffffffdf; +CHECKREG r6, 0xffffffbf; +CHECKREG r7, 0xffffff7f; + +// bit clr +BITCLR( R0 , 8 ); /* r0 = 0x00000100 */ +BITCLR( R1 , 9 ); /* r1 = 0x00000200 */ +BITCLR( R2 , 10 ); /* r2 = 0x00000400 */ +BITCLR( R3 , 11 ); /* r3 = 0x00000800 */ +BITCLR( R4 , 12 ); /* r4 = 0x00001000 */ +BITCLR( R5 , 13 ); /* r5 = 0x00002000 */ +BITCLR( R6 , 14 ); /* r6 = 0x00004000 */ +BITCLR( R7 , 15 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0xfffffefe; +CHECKREG r1, 0xfffffdfd; +CHECKREG r2, 0xfffffbfb; +CHECKREG r3, 0xfffff7f7; +CHECKREG r4, 0xffffefef; +CHECKREG r5, 0xffffdfdf; +CHECKREG r6, 0xffffbfbf; +CHECKREG r7, 0xffff7f7f; + +// bit clr +BITCLR( R0 , 16 ); /* r0 = 0x00000100 */ +BITCLR( R1 , 17 ); /* r1 = 0x00000200 */ +BITCLR( R2 , 18 ); /* r2 = 0x00000400 */ +BITCLR( R3 , 19 ); /* r3 = 0x00000800 */ +BITCLR( R4 , 20 ); /* r4 = 0x00001000 */ +BITCLR( R5 , 21 ); /* r5 = 0x00002000 */ +BITCLR( R6 , 22 ); /* r6 = 0x00004000 */ +BITCLR( R7 , 23 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0xfffefefe; +CHECKREG r1, 0xfffdfdfd; +CHECKREG r2, 0xfffbfbfb; +CHECKREG r3, 0xfff7f7f7; +CHECKREG r4, 0xffefefef; +CHECKREG r5, 0xffdfdfdf; +CHECKREG r6, 0xffbfbfbf; +CHECKREG r7, 0xff7f7f7f; + +// bit clr +BITCLR( R0 , 24 ); /* r0 = 0x00000100 */ +BITCLR( R1 , 25 ); /* r1 = 0x00000200 */ +BITCLR( R2 , 26 ); /* r2 = 0x00000400 */ +BITCLR( R3 , 27 ); /* r3 = 0x00000800 */ +BITCLR( R4 , 28 ); /* r4 = 0x00001000 */ +BITCLR( R5 , 29 ); /* r5 = 0x00002000 */ +BITCLR( R6 , 30 ); /* r6 = 0x00004000 */ +BITCLR( R7 , 31 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0xfefefefe; +CHECKREG r1, 0xfdfdfdfd; +CHECKREG r2, 0xfbfbfbfb; +CHECKREG r3, 0xf7f7f7f7; +CHECKREG r4, 0xefefefef; +CHECKREG r5, 0xdfdfdfdf; +CHECKREG r6, 0xbfbfbfbf; +CHECKREG r7, 0x7f7f7f7f; + + +pass diff --git a/sim/testsuite/bfin/c_logi2op_bitset.s b/sim/testsuite/bfin/c_logi2op_bitset.s new file mode 100644 index 0000000..ce86d67 --- /dev/null +++ b/sim/testsuite/bfin/c_logi2op_bitset.s @@ -0,0 +1,92 @@ +//Original:/testcases/core/c_logi2op_bitset/c_logi2op_bitset.dsp +// Spec Reference: Logi2op +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// bit set +BITSET( R0 , 0 ); /* r0 = 0x00000001 */ +BITSET( R1 , 1 ); /* r1 = 0x00000002 */ +BITSET( R2 , 2 ); /* r2 = 0x00000004 */ +BITSET( R3 , 3 ); /* r3 = 0x00000008 */ +BITSET( R4 , 4 ); /* r4 = 0x00000010 */ +BITSET( R5 , 5 ); /* r5 = 0x00000020 */ +BITSET( R6 , 6 ); /* r6 = 0x00000040 */ +BITSET( R7 , 7 ); /* r7 = 0x00000080 */ +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000040; +CHECKREG r7, 0x00000080; + +// bit set +BITSET( R0 , 8 ); /* r0 = 0x00000100 */ +BITSET( R1 , 9 ); /* r1 = 0x00000200 */ +BITSET( R2 , 10 ); /* r2 = 0x00000400 */ +BITSET( R3 , 11 ); /* r3 = 0x00000800 */ +BITSET( R4 , 12 ); /* r4 = 0x00001000 */ +BITSET( R5 , 13 ); /* r5 = 0x00002000 */ +BITSET( R6 , 14 ); /* r6 = 0x00004000 */ +BITSET( R7 , 15 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00000101; +CHECKREG r1, 0x00000202; +CHECKREG r2, 0x00000404; +CHECKREG r3, 0x00000808; +CHECKREG r4, 0x00001010; +CHECKREG r5, 0x00002020; +CHECKREG r6, 0x00004040; +CHECKREG r7, 0x00008080; + +// bit set +BITSET( R0 , 16 ); /* r0 = 0x00000100 */ +BITSET( R1 , 17 ); /* r1 = 0x00000200 */ +BITSET( R2 , 18 ); /* r2 = 0x00000400 */ +BITSET( R3 , 19 ); /* r3 = 0x00000800 */ +BITSET( R4 , 20 ); /* r4 = 0x00001000 */ +BITSET( R5 , 21 ); /* r5 = 0x00002000 */ +BITSET( R6 , 22 ); /* r6 = 0x00004000 */ +BITSET( R7 , 23 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00010101; +CHECKREG r1, 0x00020202; +CHECKREG r2, 0x00040404; +CHECKREG r3, 0x00080808; +CHECKREG r4, 0x00101010; +CHECKREG r5, 0x00202020; +CHECKREG r6, 0x00404040; +CHECKREG r7, 0x00808080; + +// bit set +BITSET( R0 , 24 ); /* r0 = 0x00000100 */ +BITSET( R1 , 25 ); /* r1 = 0x00000200 */ +BITSET( R2 , 26 ); /* r2 = 0x00000400 */ +BITSET( R3 , 27 ); /* r3 = 0x00000800 */ +BITSET( R4 , 28 ); /* r4 = 0x00001000 */ +BITSET( R5 , 29 ); /* r5 = 0x00002000 */ +BITSET( R6 , 30 ); /* r6 = 0x00004000 */ +BITSET( R7 , 31 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x01010101; +CHECKREG r1, 0x02020202; +CHECKREG r2, 0x04040404; +CHECKREG r3, 0x08080808; +CHECKREG r4, 0x10101010; +CHECKREG r5, 0x20202020; +CHECKREG r6, 0x40404040; +CHECKREG r7, 0x80808080; + + +pass diff --git a/sim/testsuite/bfin/c_logi2op_bittgl.s b/sim/testsuite/bfin/c_logi2op_bittgl.s new file mode 100644 index 0000000..ca9fe41 --- /dev/null +++ b/sim/testsuite/bfin/c_logi2op_bittgl.s @@ -0,0 +1,165 @@ +//Original:/testcases/core/c_logi2op_bittgl/c_logi2op_bittgl.dsp +// Spec Reference: Logi2op functions: bittgl +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// bit 0-7 +BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ +BITTGL( R1 , 1 ); /* r1 = 0x00000002 */ +BITTGL( R2 , 2 ); /* r2 = 0x00000004 */ +BITTGL( R3 , 3 ); /* r3 = 0x00000008 */ +BITTGL( R4 , 4 ); /* r4 = 0x00000010 */ +BITTGL( R5 , 5 ); /* r5 = 0x00000020 */ +BITTGL( R6 , 6 ); /* r6 = 0x00000040 */ +BITTGL( R7 , 7 ); /* r7 = 0x00000080 */ +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000040; +CHECKREG r7, 0x00000080; + +// bit 8-15 +BITTGL( R0 , 8 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 9 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 10 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 11 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 12 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 13 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 14 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 15 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00000101; +CHECKREG r1, 0x00000202; +CHECKREG r2, 0x00000404; +CHECKREG r3, 0x00000808; +CHECKREG r4, 0x00001010; +CHECKREG r5, 0x00002020; +CHECKREG r6, 0x00004040; +CHECKREG r7, 0x00008080; + +// bit 16-23 +BITTGL( R0 , 16 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 17 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 18 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 19 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 20 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 21 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 22 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 23 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00010101; +CHECKREG r1, 0x00020202; +CHECKREG r2, 0x00040404; +CHECKREG r3, 0x00080808; +CHECKREG r4, 0x00101010; +CHECKREG r5, 0x00202020; +CHECKREG r6, 0x00404040; +CHECKREG r7, 0x00808080; + +// bit 24-31 +BITTGL( R0 , 24 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 25 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 26 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 27 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 28 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 29 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 30 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 31 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x01010101; +CHECKREG r1, 0x02020202; +CHECKREG r2, 0x04040404; +CHECKREG r3, 0x08080808; +CHECKREG r4, 0x10101010; +CHECKREG r5, 0x20202020; +CHECKREG r6, 0x40404040; +CHECKREG r7, 0x80808080; + +// bit 0-7 +BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ +BITTGL( R1 , 1 ); /* r1 = 0x00000002 */ +BITTGL( R2 , 2 ); /* r2 = 0x00000004 */ +BITTGL( R3 , 3 ); /* r3 = 0x00000008 */ +BITTGL( R4 , 4 ); /* r4 = 0x00000010 */ +BITTGL( R5 , 5 ); /* r5 = 0x00000020 */ +BITTGL( R6 , 6 ); /* r6 = 0x00000040 */ +BITTGL( R7 , 7 ); /* r7 = 0x00000080 */ +CHECKREG r0, 0x01010100; +CHECKREG r1, 0x02020200; +CHECKREG r2, 0x04040400; +CHECKREG r3, 0x08080800; +CHECKREG r4, 0x10101000; +CHECKREG r5, 0x20202000; +CHECKREG r6, 0x40404000; +CHECKREG r7, 0x80808000; + +// bit 8-15 +BITTGL( R0 , 8 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 9 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 10 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 11 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 12 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 13 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 14 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 15 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x01010000; +CHECKREG r1, 0x02020000; +CHECKREG r2, 0x04040000; +CHECKREG r3, 0x08080000; +CHECKREG r4, 0x10100000; +CHECKREG r5, 0x20200000; +CHECKREG r6, 0x40400000; +CHECKREG r7, 0x80800000; + +// bit 16-23 +BITTGL( R0 , 16 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 17 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 18 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 19 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 20 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 21 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 22 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 23 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x01000000; +CHECKREG r1, 0x02000000; +CHECKREG r2, 0x04000000; +CHECKREG r3, 0x08000000; +CHECKREG r4, 0x10000000; +CHECKREG r5, 0x20000000; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x80000000; + +// bit 24-31 +BITTGL( R0 , 24 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 25 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 26 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 27 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 28 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 29 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 30 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 31 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + + +pass diff --git a/sim/testsuite/bfin/c_logi2op_bittst.s b/sim/testsuite/bfin/c_logi2op_bittst.s new file mode 100644 index 0000000..cce9df5 --- /dev/null +++ b/sim/testsuite/bfin/c_logi2op_bittst.s @@ -0,0 +1,583 @@ +//Original:/testcases/core/c_logi2op_bittst/c_logi2op_bittst.dsp +// Spec Reference: Logi2op functions: bittst +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// bit(0-7) tst set clr toggle +CC = BITTST ( R0 , 0 ); /* cc = 0 */ +BITSET( R0 , 0 ); /* r0 = 0x00000001 */ +R1 = CC; +CC = BITTST ( R0 , 0 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 0 ); /* r0 = 0x00000000 */ +CC = BITTST ( R0 , 0 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ +CC = BITTST ( R0 , 0 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; + +CC = BITTST ( R1 , 1 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 1 ); /* r1 = 0x00000002 */ +CC = BITTST ( R1 , 1 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 1 ); /* r1 = 0x00000000 */ +CC = BITTST ( R1 , 1 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 1 ); /* r1 = 0x00000002 */ +CC = BITTST ( R1 , 1 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; + +CC = BITTST ( R2 , 2 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 2 ); /* r2 = 0x00000004 */ +CC = BITTST ( R2 , 2 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 2 ); /* r2 = 0x00000000 */ +CC = BITTST ( R2 , 2 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 2 ); /* r2 = 0x00000004 */ +CC = BITTST ( R2 , 2 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; + +CC = BITTST ( R3 , 3 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 3 ); /* r3 = 0x00000008 */ +CC = BITTST ( R3 , 3 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 3 ); /* r3 = 0x00000000 */ +CC = BITTST ( R3 , 3 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 3 ); /* r3 = 0x00000008 */ +CC = BITTST ( R3 , 3 ); /* cc = 1 */ +R7 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +CC = BITTST ( R4 , 4 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 4 ); /* r4 = 0x00000010 */ +CC = BITTST ( R4 , 4 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 4 ); /* r4 = 0x00000000 */ +CC = BITTST ( R4 , 4 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 4 ); /* r4 = 0x00000010 */ +CC = BITTST ( R4 , 4 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; + +CC = BITTST ( R5 , 5 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 5 ); /* r5 = 0x00000020 */ +CC = BITTST ( R5 , 5 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 5 ); /* r5 = 0x00000000 */ +CC = BITTST ( R5 , 5 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 5 ); /* r5 = 0x00000020 */ +CC = BITTST ( R5 , 5 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; + +CC = BITTST ( R6 , 6 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 6 ); /* r6 = 0x00000040 */ +CC = BITTST ( R6 , 6 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 6 ); /* r6 = 0x00000000 */ +CC = BITTST ( R6 , 6 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 6 ); /* r6 = 0x00000040 */ +CC = BITTST ( R6 , 6 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00000040; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; + +CC = BITTST ( R7 , 7 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 7 ); /* r7 = 0x00000080 */ +CC = BITTST ( R7 , 7 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 7 ); /* r7 = 0x00000000 */ +CC = BITTST ( R7 , 7 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 7 ); /* r7 = 0x00000080 */ +CC = BITTST ( R7 , 7 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; + +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000040; +CHECKREG r7, 0x00000080; + +// bit(8-15) tst set clr toggle +CC = BITTST ( R0 , 8 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 8 ); /* r0 = 0x00000101 */ +CC = BITTST ( R0 , 8 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 8 ); /* r0 = 0x00000000 */ +CC = BITTST ( R0 , 8 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 8 ); /* r0 = 0x00000101 */ +CC = BITTST ( R0 , 8 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00000100; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; + +CC = BITTST ( R1 , 9 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 9 ); /* r1 = 0x00000200 */ +CC = BITTST ( R1 , 9 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 9 ); /* r1 = 0x00000000 */ +CC = BITTST ( R1 , 9 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 9 ); /* r1 = 0x00000200 */ +CC = BITTST ( R1 , 9 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00000200; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; + +CC = BITTST ( R2 , 10 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 10 ); /* r2 = 0x00000400 */ +CC = BITTST ( R2 , 10 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 10 ); /* r2 = 0x00000000 */ +CC = BITTST ( R2 , 10 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 10 ); /* r2 = 0x00000400 */ +CC = BITTST ( R2 , 10 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x00000400; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; + +CC = BITTST ( R3 , 11 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 11 ); /* r3 = 0x00000800 */ +CC = BITTST ( R3 , 11 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 11 ); /* r3 = 0x00000000 */ +CC = BITTST ( R3 , 11 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 11 ); /* r3 = 0x00000800 */ +CC = BITTST ( R3 , 11 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x00000800; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +CC = BITTST ( R4 , 12 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 12 ); /* r4 = 0x00001000 */ +CC = BITTST ( R4 , 12 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 12 ); /* r4 = 0x00000000 */ +CC = BITTST ( R4 , 12 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 12 ); /* r4 = 0x00001000 */ +CC = BITTST ( R4 , 12 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; + +CC = BITTST ( R5 , 13 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 13 ); /* r5 = 0x00002000 */ +CC = BITTST ( R5 , 13 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 13 ); /* r5 = 0x00000000 */ +CC = BITTST ( R5 , 13 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 13 ); /* r5 = 0x00002000 */ +CC = BITTST ( R5 , 13 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00002000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; + +CC = BITTST ( R6 , 14 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 14 ); /* r6 = 0x00004000 */ +CC = BITTST ( R6 , 14 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 14 ); /* r6 = 0x00000000 */ +CC = BITTST ( R6 , 14 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 14 ); /* r6 = 0x00004000 */ +CC = BITTST ( R6 , 14 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00004000; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; + +CC = BITTST ( R7 , 15 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 15 ); /* r7 = 0x00008000 */ +CC = BITTST ( R7 , 15 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 15 ); /* r7 = 0x00000000 */ +CC = BITTST ( R7 , 15 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 15 ); /* r7 = 0x00008000 */ +CC = BITTST ( R7 , 15 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00002000; +CHECKREG r6, 0x00004000; +CHECKREG r7, 0x00008000; + +// bit(16-23) tst set clr toggle +CC = BITTST ( R0 , 16 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 16 ); /* r0 = 0x00010000 */ +CC = BITTST ( R0 , 16 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 16 ); /* r0 = 0x00000000 */ +CC = BITTST ( R0 , 16 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 16 ); /* r0 = 0x00010000 */ +CC = BITTST ( R0 , 16 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; + +CC = BITTST ( R1 , 17 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 17 ); /* r1 = 0x00020000 */ +CC = BITTST ( R1 , 17 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 17 ); /* r1 = 0x00000000 */ +CC = BITTST ( R1 , 17 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 17 ); /* r1 = 0x00020000 */ +CC = BITTST ( R1 , 17 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00020000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; + +CC = BITTST ( R2 , 18 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 18 ); /* r2 = 0x00020000 */ +CC = BITTST ( R2 , 18 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 18 ); /* r2 = 0x00000000 */ +CC = BITTST ( R2 , 18 ); /* cc = 1 */ +R4 = CC; +BITTGL( R2 , 18 ); /* r2 = 0x00020000 */ +CC = BITTST ( R2 , 18 ); /* cc = 1 */ +R5 = CC; +CHECKREG r2, 0x00040000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00004000; + +CC = BITTST ( R3 , 19 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 19 ); /* r3 = 0x00080000 */ +CC = BITTST ( R3 , 19 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 19 ); /* r3 = 0x00000000 */ +CC = BITTST ( R3 , 19 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 19 ); /* r3 = 0x00080000 */ +CC = BITTST ( R3 , 19 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x00080000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +CC = BITTST ( R4 , 20 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 20 ); /* r4 = 0x00100000 */ +CC = BITTST ( R4 , 20 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 20 ); /* r4 = 0x00000000 */ +CC = BITTST ( R4 , 20 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 20 ); /* r4 = 0x00100000 */ +CC = BITTST ( R4 , 20 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00100000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; + +CC = BITTST ( R5 , 21 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 21 ); /* r5 = 0x00200000 */ +CC = BITTST ( R5 , 21 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 21 ); /* r5 = 0x00000000 */ +CC = BITTST ( R5 , 21 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 21 ); /* r5 = 0x00200000 */ +CC = BITTST ( R5 , 21 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00200000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; + +CC = BITTST ( R6 , 22 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 22 ); /* r6 = 0x00400000 */ +CC = BITTST ( R6 , 22 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 22 ); /* r6 = 0x00000000 */ +CC = BITTST ( R6 , 22 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 22 ); /* r6 = 0x00400000 */ +CC = BITTST ( R6 , 22 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00400000; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; + +CC = BITTST ( R7 , 23 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 23 ); /* r7 = 0x00800000 */ +CC = BITTST ( R7 , 23 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 23 ); /* r7 = 0x00000000 */ +CC = BITTST ( R7 , 23 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 23 ); /* r7 = 0x00800000 */ +CC = BITTST ( R7 , 23 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00100000; +CHECKREG r5, 0x00200000; +CHECKREG r6, 0x00400000; +CHECKREG r7, 0x00800000; + +// bit(24-31) tst set clr toggle +CC = BITTST ( R0 , 24 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 24 ); /* r0 = 0x00000101 */ +CC = BITTST ( R0 , 24 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 24 ); /* r0 = 0x01000000 */ +CC = BITTST ( R0 , 24 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 24 ); /* r0 = 0x01000000 */ +CC = BITTST ( R0 , 24 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x01000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; + +CC = BITTST ( R1 , 25 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 25 ); /* r1 = 0x02000000 */ +CC = BITTST ( R1 , 25 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 25 ); /* r1 = 0x00000000 */ +CC = BITTST ( R1 , 25 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 25 ); /* r1 = 0x02000000 */ +CC = BITTST ( R1 , 25 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x02000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; + +CC = BITTST ( R2 , 26 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 26 ); /* r2 = 0x04000000 */ +CC = BITTST ( R2 , 26 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 26 ); /* r2 = 0x00000000 */ +CC = BITTST ( R2 , 26 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 26 ); /* r2 = 0x04000000 */ +CC = BITTST ( R2 , 26 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x04000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; + +CC = BITTST ( R3 , 27 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 27 ); /* r3 = 0x08000000 */ +CC = BITTST ( R3 , 27 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 27 ); /* r3 = 0x00000000 */ +CC = BITTST ( R3 , 27 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 27 ); /* r3 = 0x08000000 */ +CC = BITTST ( R3 , 27 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x08000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +CC = BITTST ( R4 , 28 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 28 ); /* r4 = 0x10000000 */ +CC = BITTST ( R4 , 28 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 28 ); /* r4 = 0x00000000 */ +CC = BITTST ( R4 , 28 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 28 ); /* r4 = 0x10000000 */ +CC = BITTST ( R4 , 28 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x10000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; + +CC = BITTST ( R5 , 29 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 29 ); /* r5 = 0x20000000 */ +CC = BITTST ( R5 , 29 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 29 ); /* r5 = 0x00000000 */ +CC = BITTST ( R5 , 29 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 29 ); /* r5 = 0x20000000 */ +CC = BITTST ( R5 , 29 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x20000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; + +CC = BITTST ( R6 , 30 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 30 ); /* r6 = 0x40000000 */ +CC = BITTST ( R6 , 30 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 30 ); /* r6 = 0x00000000 */ +CC = BITTST ( R6 , 30 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 30 ); /* r6 = 0x40000000 */ +CC = BITTST ( R6 , 30 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; + +CC = BITTST ( R7 , 31 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 31 ); /* r7 = 0x80000000 */ +CC = BITTST ( R7 , 31 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 31 ); /* r7 = 0x00000000 */ +CC = BITTST ( R7 , 31 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 31 ); /* r7 = 0x80000000 */ +CC = BITTST ( R7 , 31 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x10000000; +CHECKREG r5, 0x20000000; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x80000000; + +pass diff --git a/sim/testsuite/bfin/c_logi2op_log_l_shft.s b/sim/testsuite/bfin/c_logi2op_log_l_shft.s new file mode 100644 index 0000000..46a457a --- /dev/null +++ b/sim/testsuite/bfin/c_logi2op_log_l_shft.s @@ -0,0 +1,222 @@ +//Original:/testcases/core/c_logi2op_log_l_shft/c_logi2op_log_l_shft.dsp +// Spec Reference: Logi2op <<= +# mach: bfin + +.include "testutils.inc" + start + + + + +// Logical <<= : negative data +// bit 0-7 +imm32 r0, 0x81111111; +imm32 r1, 0x81111111; +imm32 r2, 0x81111111; +imm32 r3, 0x81111111; +imm32 r4, 0x81111111; +imm32 r5, 0x81111111; +imm32 r6, 0x81111111; +imm32 r7, 0x81111111; +R0 <<= 0; /* r0 = 0x81111111 */ +R1 <<= 1; /* r1 = 0x40888888 */ +R2 <<= 2; /* r2 = 0x20444444 */ +R3 <<= 3; /* r3 = 0x10222222 */ +R4 <<= 4; /* r4 = 0x08111111 */ +R5 <<= 5; /* r5 = 0x04088888 */ +R6 <<= 6; /* r6 = 0x02044444 */ +R7 <<= 7; /* r7 = 0x01022222 */ +CHECKREG r0, 0x81111111; +CHECKREG r1, 0x02222222; +CHECKREG r2, 0x04444444; +CHECKREG r3, 0x08888888; +CHECKREG r4, 0x11111110; +CHECKREG r5, 0x22222220; +CHECKREG r6, 0x44444440; +CHECKREG r7, 0x88888880; + +// bit 8-15 +imm32 r0, 0x82222222; +imm32 r1, 0x82222222; +imm32 r2, 0x82222222; +imm32 r3, 0x82222222; +imm32 r4, 0x82222222; +imm32 r5, 0x82222222; +imm32 r6, 0x82222222; +imm32 r7, 0x82222222; +R0 <<= 8; +R1 <<= 9; +R2 <<= 10; +R3 <<= 11; +R4 <<= 12; +R5 <<= 13; +R6 <<= 14; +R7 <<= 15; +CHECKREG r0, 0x22222200; +CHECKREG r1, 0x44444400; +CHECKREG r2, 0x88888800; +CHECKREG r3, 0x11111000; +CHECKREG r4, 0x22222000; +CHECKREG r5, 0x44444000; +CHECKREG r6, 0x88888000; +CHECKREG r7, 0x11110000; + +// bit 16-23 +imm32 r0, 0x83333333; +imm32 r1, 0x83333333; +imm32 r2, 0x83333333; +imm32 r3, 0x83333333; +imm32 r4, 0x83333333; +imm32 r5, 0x83333333; +imm32 r6, 0x83333333; +imm32 r7, 0x83333333; +R0 <<= 16; +R1 <<= 17; +R2 <<= 18; +R3 <<= 19; +R4 <<= 20; +R5 <<= 21; +R6 <<= 22; +R7 <<= 23; +CHECKREG r0, 0x33330000; +CHECKREG r1, 0x66660000; +CHECKREG r2, 0xCCCC0000; +CHECKREG r3, 0x99980000; +CHECKREG r4, 0x33300000; +CHECKREG r5, 0x66600000; +CHECKREG r6, 0xCCC00000; +CHECKREG r7, 0x99800000; + +// bit 24-31 +imm32 r0, 0x84444444; +imm32 r1, 0x84444444; +imm32 r2, 0x84444444; +imm32 r3, 0x84444444; +imm32 r4, 0x84444444; +imm32 r5, 0x84444444; +imm32 r6, 0x84444444; +imm32 r7, 0x84444444; +R0 <<= 24; +R1 <<= 25; +R2 <<= 26; +R3 <<= 27; +R4 <<= 28; +R5 <<= 29; +R6 <<= 30; +R7 <<= 31; +CHECKREG r0, 0x44000000; +CHECKREG r1, 0x88000000; +CHECKREG r2, 0x10000000; +CHECKREG r3, 0x20000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// Arithmetic <<= : positive data +// bit 0-7 +imm32 r0, 0x41111111; +imm32 r1, 0x41111111; +imm32 r2, 0x41111111; +imm32 r3, 0x41111111; +imm32 r4, 0x41111111; +imm32 r5, 0x41111111; +imm32 r6, 0x41111111; +imm32 r7, 0x41111111; +R0 <<= 0; +R1 <<= 1; +R2 <<= 2; +R3 <<= 3; +R4 <<= 4; +R5 <<= 5; +R6 <<= 6; +R7 <<= 7; +CHECKREG r0, 0x41111111; +CHECKREG r1, 0x82222222; +CHECKREG r2, 0x04444444; +CHECKREG r3, 0x08888888; +CHECKREG r4, 0x11111110; +CHECKREG r5, 0x22222220; +CHECKREG r6, 0x44444440; +CHECKREG r7, 0x88888880; + +// bit 8-15 +imm32 r0, 0x42222222; +imm32 r1, 0x42222222; +imm32 r2, 0x42222222; +imm32 r3, 0x42222222; +imm32 r4, 0x42222222; +imm32 r5, 0x42222222; +imm32 r6, 0x42222222; +imm32 r7, 0x42222222; +R0 <<= 8; +R1 <<= 9; +R2 <<= 10; +R3 <<= 11; +R4 <<= 12; +R5 <<= 13; +R6 <<= 14; +R7 <<= 15; +CHECKREG r0, 0x22222200; +CHECKREG r1, 0x44444400; +CHECKREG r2, 0x88888800; +CHECKREG r3, 0x11111000; +CHECKREG r4, 0x22222000; +CHECKREG r5, 0x44444000; +CHECKREG r6, 0x88888000; +CHECKREG r7, 0x11110000; + +// bit 16-23 +imm32 r0, 0x43333333; +imm32 r1, 0x43333333; +imm32 r2, 0x43333333; +imm32 r3, 0x43333333; +imm32 r4, 0x43333333; +imm32 r5, 0x43333333; +imm32 r6, 0x43333333; +imm32 r7, 0x43333333; +R0 <<= 16; +R1 <<= 17; +R2 <<= 18; +R3 <<= 19; +R4 <<= 20; +R5 <<= 21; +R6 <<= 22; +R7 <<= 23; +CHECKREG r0, 0x33330000; +CHECKREG r1, 0x66660000; +CHECKREG r2, 0xCCCC0000; +CHECKREG r3, 0x99980000; +CHECKREG r4, 0x33300000; +CHECKREG r5, 0x66600000; +CHECKREG r6, 0xCCC00000; +CHECKREG r7, 0x99800000; + +// bit 24-31 +imm32 r0, 0x44444444; +imm32 r1, 0x44444444; +imm32 r2, 0x44444444; +imm32 r3, 0x44444444; +imm32 r4, 0x44444444; +imm32 r5, 0x44444444; +imm32 r6, 0x44444444; +imm32 r7, 0x44444444; +R0 <<= 24; +R1 <<= 25; +R2 <<= 26; +R3 <<= 27; +R4 <<= 28; +R5 <<= 29; +R6 <<= 30; +R7 <<= 31; +CHECKREG r0, 0x44000000; +CHECKREG r1, 0x88000000; +CHECKREG r2, 0x10000000; +CHECKREG r3, 0x20000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +pass diff --git a/sim/testsuite/bfin/c_logi2op_log_l_shft_astat.S b/sim/testsuite/bfin/c_logi2op_log_l_shft_astat.S new file mode 100644 index 0000000..6b3e8ca --- /dev/null +++ b/sim/testsuite/bfin/c_logi2op_log_l_shft_astat.S @@ -0,0 +1,82 @@ +# Test ASTAT bits with logical left shift (<<=) +# mach: bfin + +.include "testutils.inc" +#include "test.h" +start + +.macro __do val:req, shift:req, exp:req + # First test when ASTAT starts with all bits cleared + imm32 R2, \val; + ASTAT = R0; + R2 <<= \shift; + R3 = ASTAT; + CHECKREG R2, (\val << \shift); + CHECKREG R3, \exp; + + # Then test when ASTAT starts with all bits set + imm32 R2, \val; + ASTAT = R1; + R2 <<= \shift; + R3 = ASTAT; + CHECKREG R3, (\exp) | ~(_AZ|_AN|_V|_V_COPY); +.endm + +.macro _do shift:req, val:req + # Automatically test all shifted values + .if ((\val << \shift) & 0xffffffff) == 0 + __do \val, \shift, _AZ + .else + .if (\val << \shift) == 0x80000000 + __do \val, \shift, _AN + .else + __do \val, \shift, 0 + .endif + .endif + .if (\val << 1) & 0xffffffff + _do \shift, (\val << 1) + .endif +.endm + +.macro do shift:req +_l_shft_\shift: + _do \shift, 1 +.endm + +R0 = 0; +R1 = -1; + +do 0 +do 1 +do 2 +do 3 +do 4 +do 5 +do 6 +do 7 +do 8 +do 9 +do 10 +do 11 +do 12 +do 13 +do 14 +do 15 +do 16 +do 17 +do 18 +do 19 +do 20 +do 21 +do 22 +do 23 +do 24 +do 25 +do 26 +do 27 +do 28 +do 29 +do 30 +do 31 + +pass diff --git a/sim/testsuite/bfin/c_logi2op_log_r_shft.s b/sim/testsuite/bfin/c_logi2op_log_r_shft.s new file mode 100644 index 0000000..af4eb73 --- /dev/null +++ b/sim/testsuite/bfin/c_logi2op_log_r_shft.s @@ -0,0 +1,222 @@ +//Original:/testcases/core/c_logi2op_log_r_shft/c_logi2op_log_r_shft.dsp +// Spec Reference: Logi2op >>= +# mach: bfin + +.include "testutils.inc" + start + + + + +// Logical >>= : negative data +// bit 0-7 +imm32 r0, 0x81111111; +imm32 r1, 0x81111111; +imm32 r2, 0x81111111; +imm32 r3, 0x81111111; +imm32 r4, 0x81111111; +imm32 r5, 0x81111111; +imm32 r6, 0x81111111; +imm32 r7, 0x81111111; +R0 >>= 0; /* r0 = 0x81111111 */ +R1 >>= 1; /* r1 = 0x40888888 */ +R2 >>= 2; /* r2 = 0x20444444 */ +R3 >>= 3; /* r3 = 0x10222222 */ +R4 >>= 4; /* r4 = 0x08111111 */ +R5 >>= 5; /* r5 = 0x04088888 */ +R6 >>= 6; /* r6 = 0x02044444 */ +R7 >>= 7; /* r7 = 0x01022222 */ +CHECKREG r0, 0x81111111; +CHECKREG r1, 0x40888888; +CHECKREG r2, 0x20444444; +CHECKREG r3, 0x10222222; +CHECKREG r4, 0x08111111; +CHECKREG r5, 0x04088888; +CHECKREG r6, 0x02044444; +CHECKREG r7, 0x01022222; + +// bit 8-15 +imm32 r0, 0x82222222; +imm32 r1, 0x82222222; +imm32 r2, 0x82222222; +imm32 r3, 0x82222222; +imm32 r4, 0x82222222; +imm32 r5, 0x82222222; +imm32 r6, 0x82222222; +imm32 r7, 0x82222222; +R0 >>= 8; /* r0 = 0x00822222 */ +R1 >>= 9; /* r1 = 0x00411111 */ +R2 >>= 10; /* r2 = 0x00208888 */ +R3 >>= 11; /* r3 = 0x00104444 */ +R4 >>= 12; /* r4 = 0x00082222 */ +R5 >>= 13; /* r5 = 0x00041111 */ +R6 >>= 14; /* r6 = 0x00020888 */ +R7 >>= 15; /* r7 = 0x00010444 */ +CHECKREG r0, 0x00822222; +CHECKREG r1, 0x00411111; +CHECKREG r2, 0x00208888; +CHECKREG r3, 0x00104444; +CHECKREG r4, 0x00082222; +CHECKREG r5, 0x00041111; +CHECKREG r6, 0x00020888; +CHECKREG r7, 0x00010444; + +// bit 16-23 +imm32 r0, 0x83333333; +imm32 r1, 0x83333333; +imm32 r2, 0x83333333; +imm32 r3, 0x83333333; +imm32 r4, 0x83333333; +imm32 r5, 0x83333333; +imm32 r6, 0x83333333; +imm32 r7, 0x83333333; +R0 >>= 16; /* r0 = 0x00008333 */ +R1 >>= 17; /* r1 = 0x00004199 */ +R2 >>= 18; /* r2 = 0x000020CC */ +R3 >>= 19; /* r3 = 0x00001066 */ +R4 >>= 20; /* r4 = 0x00000833 */ +R5 >>= 21; /* r5 = 0x00000419 */ +R6 >>= 22; /* r6 = 0x0000020C */ +R7 >>= 23; /* r7 = 0x00000106 */ +CHECKREG r0, 0x00008333; +CHECKREG r1, 0x00004199; +CHECKREG r2, 0x000020CC; +CHECKREG r3, 0x00001066; +CHECKREG r4, 0x00000833; +CHECKREG r5, 0x00000419; +CHECKREG r6, 0x0000020C; +CHECKREG r7, 0x00000106; + +// bit 24-31 +imm32 r0, 0x84444444; +imm32 r1, 0x84444444; +imm32 r2, 0x84444444; +imm32 r3, 0x84444444; +imm32 r4, 0x84444444; +imm32 r5, 0x84444444; +imm32 r6, 0x84444444; +imm32 r7, 0x84444444; +R0 >>= 24; /* r0 = 0x00000084 */ +R1 >>= 25; /* r1 = 0x00000042 */ +R2 >>= 26; /* r2 = 0x00000021 */ +R3 >>= 27; /* r3 = 0x00000010 */ +R4 >>= 28; /* r4 = 0x00000008 */ +R5 >>= 29; /* r5 = 0x00000004 */ +R6 >>= 30; /* r6 = 0x00000002 */ +R7 >>= 31; /* r7 = 0x00000001 */ +CHECKREG r0, 0x00000084; +CHECKREG r1, 0x00000042; +CHECKREG r2, 0x00000021; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000008; +CHECKREG r5, 0x00000004; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0x00000001; + +// Arithmetic >>= : positive data +// bit 0-7 +imm32 r0, 0x41111111; +imm32 r1, 0x41111111; +imm32 r2, 0x41111111; +imm32 r3, 0x41111111; +imm32 r4, 0x41111111; +imm32 r5, 0x41111111; +imm32 r6, 0x41111111; +imm32 r7, 0x41111111; +R0 >>= 0; /* r0 = 0x41111111 */ +R1 >>= 1; /* r1 = 0x20888888 */ +R2 >>= 2; /* r2 = 0x10444444 */ +R3 >>= 3; /* r3 = 0x08222222 */ +R4 >>= 4; /* r4 = 0x04111111 */ +R5 >>= 5; /* r5 = 0x02088888 */ +R6 >>= 6; /* r6 = 0x01044444 */ +R7 >>= 7; /* r7 = 0x00822222 */ +CHECKREG r0, 0x41111111; +CHECKREG r1, 0x20888888; +CHECKREG r2, 0x10444444; +CHECKREG r3, 0x08222222; +CHECKREG r4, 0x04111111; +CHECKREG r5, 0x02088888; +CHECKREG r6, 0x01044444; +CHECKREG r7, 0x00822222; + +// bit 8-15 +imm32 r0, 0x42222222; +imm32 r1, 0x42222222; +imm32 r2, 0x42222222; +imm32 r3, 0x42222222; +imm32 r4, 0x42222222; +imm32 r5, 0x42222222; +imm32 r6, 0x42222222; +imm32 r7, 0x42222222; +R0 >>= 8; /* r0 = 0x00422222 */ +R1 >>= 9; /* r1 = 0x00211111 */ +R2 >>= 10; /* r2 = 0x00108888 */ +R3 >>= 11; /* r3 = 0x00084444 */ +R4 >>= 12; /* r4 = 0x00042222 */ +R5 >>= 13; /* r5 = 0x00021111 */ +R6 >>= 14; /* r6 = 0x00010888 */ +R7 >>= 15; /* r7 = 0x00008444 */ +CHECKREG r0, 0x00422222; +CHECKREG r1, 0x00211111; +CHECKREG r2, 0x00108888; +CHECKREG r3, 0x00084444; +CHECKREG r4, 0x00042222; +CHECKREG r5, 0x00021111; +CHECKREG r6, 0x00010888; +CHECKREG r7, 0x00008444; + +// bit 16-23 +imm32 r0, 0x43333333; +imm32 r1, 0x43333333; +imm32 r2, 0x43333333; +imm32 r3, 0x43333333; +imm32 r4, 0x43333333; +imm32 r5, 0x43333333; +imm32 r6, 0x43333333; +imm32 r7, 0x43333333; +R0 >>= 16; /* r0 = 0x00004333 */ +R1 >>= 17; /* r1 = 0x00002199 */ +R2 >>= 18; /* r2 = 0x000010CC */ +R3 >>= 19; /* r3 = 0x00000866 */ +R4 >>= 20; /* r4 = 0x00000433 */ +R5 >>= 21; /* r5 = 0x00000219 */ +R6 >>= 22; /* r6 = 0x0000010C */ +R7 >>= 23; /* r7 = 0x00000086 */ +CHECKREG r0, 0x00004333; +CHECKREG r1, 0x00002199; +CHECKREG r2, 0x000010CC; +CHECKREG r3, 0x00000866; +CHECKREG r4, 0x00000433; +CHECKREG r5, 0x00000219; +CHECKREG r6, 0x0000010C; +CHECKREG r7, 0x00000086; + +// bit 24-31 +imm32 r0, 0x44444444; +imm32 r1, 0x44444444; +imm32 r2, 0x44444444; +imm32 r3, 0x44444444; +imm32 r4, 0x44444444; +imm32 r5, 0x44444444; +imm32 r6, 0x44444444; +imm32 r7, 0x44444444; +R0 >>= 24; /* r0 = 0x00000044 */ +R1 >>= 25; /* r1 = 0x00000022 */ +R2 >>= 26; /* r2 = 0x00000011 */ +R3 >>= 27; /* r3 = 0x00000008 */ +R4 >>= 28; /* r4 = 0x00000004 */ +R5 >>= 29; /* r5 = 0x00000002 */ +R6 >>= 30; /* r6 = 0x00000001 */ +R7 >>= 31; /* r7 = 0x00000000 */ +CHECKREG r0, 0x00000044; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000011; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + + +pass diff --git a/sim/testsuite/bfin/c_logi2op_log_r_shft_astat.S b/sim/testsuite/bfin/c_logi2op_log_r_shft_astat.S new file mode 100644 index 0000000..4f2a22b --- /dev/null +++ b/sim/testsuite/bfin/c_logi2op_log_r_shft_astat.S @@ -0,0 +1,82 @@ +# Test ASTAT bits with logical right shift (>>=) +# mach: bfin + +.include "testutils.inc" +#include "test.h" +start + +.macro __do val:req, shift:req, exp:req + # First test when ASTAT starts with all bits cleared + imm32 R2, \val; + ASTAT = R0; + R2 >>= \shift; + R3 = ASTAT; + CHECKREG R2, (\val >> \shift); + CHECKREG R3, \exp; + + # Then test when ASTAT starts with all bits set + imm32 R2, \val; + ASTAT = R1; + R2 >>= \shift; + R3 = ASTAT; + CHECKREG R3, (\exp) | ~(_AZ|_AN|_V|_V_COPY); +.endm + +.macro _do shift:req, val:req + # Automatically test all shifted values + .if ((\val >> \shift) & 0xffffffff) == 0 + __do \val, \shift, _AZ + .else + .if (\val >> \shift) == 0x80000000 + __do \val, \shift, _AN + .else + __do \val, \shift, 0 + .endif + .endif + .if (\val >> 1) & 0xffffffff + _do \shift, (\val >> 1) + .endif +.endm + +.macro do shift:req +_l_shft_\shift: + _do \shift, 0x80000000 +.endm + +R0 = 0; +R1 = -1; + +do 0 +do 1 +do 2 +do 3 +do 4 +do 5 +do 6 +do 7 +do 8 +do 9 +do 10 +do 11 +do 12 +do 13 +do 14 +do 15 +do 16 +do 17 +do 18 +do 19 +do 20 +do 21 +do 22 +do 23 +do 24 +do 25 +do 26 +do 27 +do 28 +do 29 +do 30 +do 31 + +pass diff --git a/sim/testsuite/bfin/c_logi2op_nbittst.s b/sim/testsuite/bfin/c_logi2op_nbittst.s new file mode 100644 index 0000000..b881c2b --- /dev/null +++ b/sim/testsuite/bfin/c_logi2op_nbittst.s @@ -0,0 +1,584 @@ +//Original:/testcases/core/c_logi2op_nbittst/c_logi2op_nbittst.dsp +// Spec Reference: Logi2op !bittst +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// bit(0-7) tst set clr toggle +CC = ! BITTST( R0 , 0 ); /* cc = 0 */ +BITSET( R0 , 0 ); /* r0 = 0x00000001 */ +R1 = CC; +CC = ! BITTST( R0 , 0 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 0 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R0 , 0 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ +CC = ! BITTST( R0 , 0 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; + +CC = ! BITTST( R1 , 1 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 1 ); /* r0 = 0x00000002 */ +CC = ! BITTST( R1 , 1 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 1 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R1 , 1 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 1 ); /* r0 = 0x00000002 */ +CC = ! BITTST( R1 , 1 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; + +CC = ! BITTST( R2 , 2 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 2 ); /* r0 = 0x00000004 */ +CC = ! BITTST( R2 , 2 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 2 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R2 , 2 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 2 ); /* r0 = 0x00000004 */ +CC = ! BITTST( R2 , 2 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x00000005; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; + +CC = ! BITTST( R3 , 3 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 3 ); /* r0 = 0x00000008 */ +CC = ! BITTST( R3 , 3 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 3 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R3 , 3 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 3 ); /* r0 = 0x00000008 */ +CC = ! BITTST( R3 , 3 ); /* cc = 1 */ +R7 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0x00000005; +CHECKREG r3, 0x00000009; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +CC = ! BITTST( R4 , 4 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 4 ); /* r0 = 0x00000010 */ +CC = ! BITTST( R4 , 4 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 4 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R4 , 4 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 4 ); /* r0 = 0x00000010 */ +CC = ! BITTST( R4 , 4 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00000011; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; + +CC = ! BITTST( R5 , 5 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 5 ); /* r0 = 0x00000020 */ +CC = ! BITTST( R5 , 5 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 5 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R5 , 5 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 5 ); /* r0 = 0x00000020 */ +CC = ! BITTST( R5 , 5 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00000021; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; + +CC = ! BITTST( R6 , 6 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 6 ); /* r0 = 0x00000040 */ +CC = ! BITTST( R6 , 6 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 6 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R6 , 6 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 6 ); /* r0 = 0x00000040 */ +CC = ! BITTST( R6 , 6 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00000041; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; + +CC = ! BITTST( R7 , 7 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 7 ); /* r0 = 0x00000080 */ +CC = ! BITTST( R7 , 7 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 7 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R7 , 7 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 7 ); /* r0 = 0x00000080 */ +CC = ! BITTST( R7 , 7 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; + +CHECKREG r4, 0x00000011; +CHECKREG r5, 0x00000021; +CHECKREG r6, 0x00000041; +CHECKREG r7, 0x00000081; + +// bit(8-15) tst set clr toggle +CC = ! BITTST( R0 , 8 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 8 ); /* r0 = 0x00000101 */ +CC = ! BITTST( R0 , 8 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 8 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R0 , 8 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 8 ); /* r0 = 0x00000101 */ +CC = ! BITTST( R0 , 8 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00000101; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; + +CC = ! BITTST( R1 , 9 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 9 ); /* r0 = 0x00000202 */ +CC = ! BITTST( R1 , 9 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 9 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R1 , 9 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 9 ); /* r0 = 0x00000202 */ +CC = ! BITTST( R1 , 9 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00000201; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; + +CC = ! BITTST( R2 , 10 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 10 ); /* r0 = 0x00000404 */ +CC = ! BITTST( R2 , 10 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 10 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R2 , 10 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 10 ); /* r0 = 0x00000404 */ +CC = ! BITTST( R2 , 10 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x00000401; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; + +CC = ! BITTST( R3 , 11 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 11 ); /* r0 = 0x00000808 */ +CC = ! BITTST( R3 , 11 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 11 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R3 , 11 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 11 ); /* r0 = 0x00000808 */ +CC = ! BITTST( R3 , 11 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x00000801; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +CC = ! BITTST( R4 , 12 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 12 ); /* r0 = 0x00001010 */ +CC = ! BITTST( R4 , 12 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 12 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R4 , 12 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 12 ); /* r0 = 0x00001010 */ +CC = ! BITTST( R4 , 12 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00001001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; + +CC = ! BITTST( R5 , 13 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 13 ); /* r0 = 0x00002020 */ +CC = ! BITTST( R5 , 13 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 13 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R5 , 13 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 13 ); /* r0 = 0x00002020 */ +CC = ! BITTST( R5 , 13 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00002001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; + +CC = ! BITTST( R6 , 14 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 14 ); /* r0 = 0x00004040 */ +CC = ! BITTST( R6 , 14 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 14 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R6 , 14 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 14 ); /* r0 = 0x00004040 */ +CC = ! BITTST( R6 , 14 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00004001; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; + +CC = ! BITTST( R7 , 15 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 15 ); /* r0 = 0x00008080 */ +CC = ! BITTST( R7 , 15 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 15 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R7 , 15 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 15 ); /* r0 = 0x00008080 */ +CC = ! BITTST( R7 , 15 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00001001; +CHECKREG r5, 0x00002001; +CHECKREG r6, 0x00004001; +CHECKREG r7, 0x00008001; + +// bit(16-23) tst set clr toggle +CC = ! BITTST( R0 , 16 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 16 ); /* r0 = 0x00000001 */ +CC = ! BITTST( R0 , 16 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 16 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R0 , 16 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 16 ); /* r0 = 0x00000001 */ +CC = ! BITTST( R0 , 16 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; + +CC = ! BITTST( R1 , 17 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 17 ); /* r0 = 0x00000002 */ +CC = ! BITTST( R1 , 17 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 17 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R1 , 17 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 17 ); /* r0 = 0x00000002 */ +CC = ! BITTST( R1 , 17 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; + +CC = ! BITTST( R2 , 18 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 18 ); /* r0 = 0x00000004 */ +CC = ! BITTST( R2 , 18 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 18 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R2 , 18 ); /* cc = 1 */ +R4 = CC; +BITTGL( R2 , 18 ); /* r0 = 0x00000004 */ +CC = ! BITTST( R2 , 18 ); /* cc = 1 */ +R5 = CC; +CHECKREG r2, 0x00040001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00004001; + +CC = ! BITTST( R3 , 19 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 19 ); /* r0 = 0x00000008 */ +CC = ! BITTST( R3 , 19 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 19 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R3 , 19 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 19 ); /* r0 = 0x00000008 */ +CC = ! BITTST( R3 , 19 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x00080001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +CC = ! BITTST( R4 , 20 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 20 ); /* r0 = 0x00000010 */ +CC = ! BITTST( R4 , 20 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 20 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R4 , 20 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 20 ); /* r0 = 0x00000010 */ +CC = ! BITTST( R4 , 20 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00100001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; + +CC = ! BITTST( R5 , 21 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 21 ); /* r0 = 0x00000020 */ +CC = ! BITTST( R5 , 21 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 21 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R5 , 21 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 21 ); /* r0 = 0x00000020 */ +CC = ! BITTST( R5 , 21 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00200001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; + +CC = ! BITTST( R6 , 22 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 22 ); /* r0 = 0x00000040 */ +CC = ! BITTST( R6 , 22 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 22 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R6 , 22 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 22 ); /* r0 = 0x00000040 */ +CC = ! BITTST( R6 , 22 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00400001; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; + +CC = ! BITTST( R7 , 23 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 23 ); /* r0 = 0x00000080 */ +CC = ! BITTST( R7 , 23 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 23 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R7 , 23 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 23 ); /* r0 = 0x00000080 */ +CC = ! BITTST( R7 , 23 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00100001; +CHECKREG r5, 0x00200001; +CHECKREG r6, 0x00400001; +CHECKREG r7, 0x00800001; + +// bit(24-31) tst set clr toggle +CC = ! BITTST( R0 , 24 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 24 ); /* r0 = 0x00000101 */ +CC = ! BITTST( R0 , 24 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 24 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R0 , 24 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 24 ); /* r0 = 0x00000101 */ +CC = ! BITTST( R0 , 24 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x01000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; + +CC = ! BITTST( R1 , 25 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 25 ); /* r0 = 0x00000202 */ +CC = ! BITTST( R1 , 25 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 25 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R1 , 25 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 25 ); /* r0 = 0x00000202 */ +CC = ! BITTST( R1 , 25 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x02000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; + +CC = ! BITTST( R2 , 26 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 26 ); /* r0 = 0x00000404 */ +CC = ! BITTST( R2 , 26 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 26 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R2 , 26 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 26 ); /* r0 = 0x00000404 */ +CC = ! BITTST( R2 , 26 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x04000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; + +CC = ! BITTST( R3 , 27 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 27 ); /* r0 = 0x00000808 */ +CC = ! BITTST( R3 , 27 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 27 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R3 , 27 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 27 ); /* r0 = 0x00000808 */ +CC = ! BITTST( R3 , 27 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x08000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +CC = ! BITTST( R4 , 28 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 28 ); /* r0 = 0x00001010 */ +CC = ! BITTST( R4 , 28 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 28 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R4 , 28 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 28 ); /* r0 = 0x00001010 */ +CC = ! BITTST( R4 , 28 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x10000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; + +CC = ! BITTST( R5 , 29 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 29 ); /* r0 = 0x00002020 */ +CC = ! BITTST( R5 , 29 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 29 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R5 , 29 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 29 ); /* r0 = 0x00002020 */ +CC = ! BITTST( R5 , 29 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x20000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; + +CC = ! BITTST( R6 , 30 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 30 ); /* r0 = 0x00004040 */ +CC = ! BITTST( R6 , 30 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 30 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R6 , 30 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 30 ); /* r0 = 0x00004040 */ +CC = ! BITTST( R6 , 30 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x40000001; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; + +CC = ! BITTST( R7 , 31 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 31 ); /* r0 = 0x00008080 */ +CC = ! BITTST( R7 , 31 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 31 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R7 , 31 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 31 ); /* r0 = 0x80808080 */ +CC = ! BITTST( R7 , 31 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x10000001; +CHECKREG r5, 0x20000001; +CHECKREG r6, 0x40000001; +CHECKREG r7, 0x80000001; + +pass diff --git a/sim/testsuite/bfin/c_loopsetup_nested.s b/sim/testsuite/bfin/c_loopsetup_nested.s new file mode 100644 index 0000000..b351bc5 --- /dev/null +++ b/sim/testsuite/bfin/c_loopsetup_nested.s @@ -0,0 +1,166 @@ +//Original:/testcases/core/c_loopsetup_nested/c_loopsetup_nested.dsp +// Spec Reference: loopsetup nested inside +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; +LSETUP ( start3 , end3 ) LC1 = P3; +start3: R6 += 6; +LSETUP ( start4 , end4 ) LC0 = P4 >> 1; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000017; +CHECKREG r1, 0xFFFFFFEC; +CHECKREG r2, 0x00000056; +CHECKREG r3, 0x0000004C; +CHECKREG r4, 0x00000070; +CHECKREG r5, 0x00000014; +CHECKREG r6, 0x0000007E; +CHECKREG r7, 0x0000004D; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start5 , end5 ) LC0 = P5; +start5: R4 += 1; +LSETUP ( start6 , end6 ) LC1 = SP >> 1; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +end5: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x0000005D; +CHECKREG r4, 0x00000047; +CHECKREG r5, 0x00000042; +CHECKREG r6, 0x000000D0; +CHECKREG r7, 0xFFFFFFE4; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000063; +CHECKREG r4, 0x0000006B; +CHECKREG r5, 0x00000015; +CHECKREG r6, 0x000000D0; +CHECKREG r7, 0xFFFFFFE4; + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 20; +SP = 22; +FP = 24; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1; +start11: R0 += 1; + R1 += -1; +LSETUP ( start15 , end15 ) LC0 = P5; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start13 , end13 ) LC1 = P3; +start13: R6 += 1; +LSETUP ( start12 , end12 ) LC0 = P2; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000011; +CHECKREG r1, 0x00000004; +CHECKREG r2, 0x0000002C; +CHECKREG r3, 0x0000004E; +CHECKREG r4, 0x00000210; +CHECKREG r5, 0xFFFFFE80; +CHECKREG r6, 0x00000070; +CHECKREG r7, 0x00000060; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start14 , end14 ) LC0 = P4; +start14: R0 += 1; + R1 += -1; +LSETUP ( start16 , end16 ) LC1 = SP; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +end14: R2 += 1; + R3 += 1; +CHECKREG r0, 0x00000017; +CHECKREG r1, 0xFFFFFFFE; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x00000055; +CHECKREG r4, 0x00000118; +CHECKREG r5, 0xFFFFFF78; +CHECKREG r6, 0x000001EC; +CHECKREG r7, 0xFFFFFEE4; + +pass diff --git a/sim/testsuite/bfin/c_loopsetup_nested_bot.s b/sim/testsuite/bfin/c_loopsetup_nested_bot.s new file mode 100644 index 0000000..118b6d2 --- /dev/null +++ b/sim/testsuite/bfin/c_loopsetup_nested_bot.s @@ -0,0 +1,165 @@ +//Original:/testcases/core/c_loopsetup_nested_bot/c_loopsetup_nested_bot.dsp +// Spec Reference: loopsetup nested same bottom +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; +ASTAT = r0; + +//p0 = 2; +P1 = 2; +P2 = 4; +P3 = 6; +P4 = 8; +P5 = 10; +SP = 12; +FP = 14; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x32; +R4 = 0x46 (X); +R5 = 0x50 (X); +R6 = 0x68 (X); +R7 = 0x72 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; +LSETUP ( start3 , end3 ) LC1 = P3; +start3: R6 += 6; +LSETUP ( start4 , end3 ) LC0 = P4 >> 1; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000010; +CHECKREG r1, 0xFFFFFFFA; +CHECKREG r2, 0x00000041; +CHECKREG r3, 0x0000005D; +CHECKREG r4, 0x00000066; +CHECKREG r5, 0x00000028; +CHECKREG r6, 0x0000008C; +CHECKREG r7, 0x00000033; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x14; +R3 = 0x18; +R4 = 0x20; +R5 = 0x12; +R6 = 0x24; +R7 = 0x16; +LSETUP ( start5 , end5 ) LC0 = P5; +start5: R4 += 1; +LSETUP ( start6 , end5 ) LC1 = SP >> 1; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +end5: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000014; +CHECKREG r3, 0x00000183; +CHECKREG r4, 0x0000002A; +CHECKREG r5, 0xFFFFFF9A; +CHECKREG r6, 0x00000114; +CHECKREG r7, 0xFFFFFEEA; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000014; +CHECKREG r3, 0x00000189; +CHECKREG r4, 0x00000062; +CHECKREG r5, 0xFFFFFF54; +CHECKREG r6, 0x00000114; +CHECKREG r7, 0xFFFFFEEA; + +P1 = 04; +P2 = 08; +P3 = 10; +P4 = 12; +P5 = 14; +SP = 16; +FP = 18; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x12; +R3 = 0x20; +R4 = 0x18; +R5 = 0x14; +R6 = 0x16; +R7 = 0x28; +LSETUP ( start11 , end11 ) LC0 = P5; +start11: R0 += 1; + R1 += -1; +LSETUP ( start15 , end15 ) LC1 = P1; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start13 , end12 ) LC0 = P2; +start13: R6 += 1; +LSETUP ( start12 , end12 ) LC1 = P3; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000013; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000031; +CHECKREG r4, 0x0000005A; +CHECKREG r5, 0xFFFFFFD2; +CHECKREG r6, 0x00000017; +CHECKREG r7, 0x00000027; + +R0 = 0x05; +R1 = 0x08; +R2 = 0x12; +R3 = 0x24; +R4 = 0x18; +R5 = 0x20; +R6 = 0x32; +R7 = 0x46 (X); +LSETUP ( start14 , end14 ) LC0 = P4; +start14: R0 += 1; + R1 += -1; +LSETUP ( start16 , end16 ) LC1 = SP; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +LSETUP ( start17 , end14 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +end14: R2 += 1; + R3 += 1; +CHECKREG r0, 0x00000011; +CHECKREG r1, 0xFFFFFFFC; +CHECKREG r2, 0x0000007E; +CHECKREG r3, 0x0000009D; +CHECKREG r4, 0x00000084; +CHECKREG r5, 0xFFFFFFB4; +CHECKREG r6, 0x000000F2; +CHECKREG r7, 0xFFFFFF86; + +pass diff --git a/sim/testsuite/bfin/c_loopsetup_nested_prelc.s b/sim/testsuite/bfin/c_loopsetup_nested_prelc.s new file mode 100644 index 0000000..f7de63c --- /dev/null +++ b/sim/testsuite/bfin/c_loopsetup_nested_prelc.s @@ -0,0 +1,184 @@ +//Original:/testcases/core/c_loopsetup_nested_prelc/c_loopsetup_nested_prelc.dsp +// Spec Reference: loopsetup nested preload lc0 lc1 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x12; +R3 = 0x14; +R4 = 0x18; +R5 = 0x16; +R6 = 0x16; +R7 = 0x18; + +LC0 = R0; +LC1 = R1; +LSETUP ( start1 , end1 ) LC0; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; +LC0 = R7; +LC1 = R6; +LSETUP ( start3 , end3 ) LC0; +start3: R6 += 6; +LSETUP ( start4 , end4 ) LC1; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000037; +CHECKREG r1, 0xFFFFFFAC; +CHECKREG r2, 0x000000A8; +CHECKREG r3, 0x0000007E; +CHECKREG r4, 0x00000068; +CHECKREG r5, 0xFFFFFFB2; +CHECKREG r6, 0x000000A6; +CHECKREG r7, 0xFFFFFF70; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x08; +R3 = 0x0C; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); + +LC0 = R2; +LC1 = R3; +LSETUP ( start5 , end5 ) LC0; +start5: R4 += 1; +LSETUP ( start6 , end6 ) LC1; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +end5: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000008; +CHECKREG r3, 0x0000003F; +CHECKREG r4, 0x00000048; +CHECKREG r5, 0x00000040; +CHECKREG r6, 0x000000AC; +CHECKREG r7, 0x00000011; +LSETUP ( start7 , end7 ) LC0; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000008; +CHECKREG r3, 0x00000045; +CHECKREG r4, 0x0000004C; +CHECKREG r5, 0x0000003B; +CHECKREG r6, 0x000000AC; +CHECKREG r7, 0x00000011; + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 12; +SP = 14; +FP = 16; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x14; +R3 = 0x18; +R4 = 0x16; +R5 = 0x04; +R6 = 0x30; +R7 = 0x30; + +LC0 = R5; +LC1 = R4; +LSETUP ( start11 , end11 ) LC0; +start11: R0 += 1; + R1 += -1; +LSETUP ( start15 , end15 ) LC1; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +end11: R2 += 1; + R3 += 1; + + +LSETUP ( start13 , end13 ) LC0 = P5; +start13: R6 += 1; +LSETUP ( start12 , end12 ) LC1 = P2; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000009; +CHECKREG r1, 0x0000000C; +CHECKREG r2, 0x00000018; +CHECKREG r3, 0x0000002A; +CHECKREG r4, 0x000000D7; +CHECKREG r5, 0xFFFFFF43; +CHECKREG r6, 0x0000003C; +CHECKREG r7, 0x00000024; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x14; +R7 = 0x08; +P4 = 6; +FP = 8; + +LC0 = R6; +LC1 = R7; +LSETUP ( start14 , end14 ) LC0 = P4; +start14: R0 += 1; + R1 += -1; +LSETUP ( start16 , end16 ) LC1; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +end14: R2 += 1; + R3 += 1; +CHECKREG r0, 0x0000000B; +CHECKREG r1, 0x0000000A; +CHECKREG r2, 0x00000026; +CHECKREG r3, 0x0000003D; +CHECKREG r4, 0x00000058; +CHECKREG r5, 0x00000038; +CHECKREG r6, 0x00000021; +CHECKREG r7, 0xFFFFFFFB; + +pass diff --git a/sim/testsuite/bfin/c_loopsetup_nested_top.s b/sim/testsuite/bfin/c_loopsetup_nested_top.s new file mode 100644 index 0000000..54146a3 --- /dev/null +++ b/sim/testsuite/bfin/c_loopsetup_nested_top.s @@ -0,0 +1,166 @@ +//Original:/testcases/core/c_loopsetup_nested_top/c_loopsetup_nested_top.dsp +// Spec Reference: loopsetup nested top +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; +LSETUP ( start3 , end3 ) LC1 = P3; +LSETUP ( start3 , end4 ) LC0 = P4; +start3: R6 += 6; + R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000012; +CHECKREG r1, 0xFFFFFFF6; +CHECKREG r2, 0x00000047; +CHECKREG r3, 0x0000004C; +CHECKREG r4, 0x00000070; +CHECKREG r5, 0x00000014; +CHECKREG r6, 0x0000009C; +CHECKREG r7, 0x0000004D; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start5 , end5 ) LC0 = P5; +LSETUP ( start5 , end6 ) LC1 = SP >> 1; +start5: R4 += 1; + R6 += 4; +end6: R7 += -5; + R3 += 6; +end5: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x0000005D; +CHECKREG r4, 0x0000004A; +CHECKREG r5, 0x00000042; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x0000003E; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000063; +CHECKREG r4, 0x0000006E; +CHECKREG r5, 0x00000015; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x0000003E; + +P1 = 8; +P2 = 10; +P3 = 12; +P4 = 14; +P5 = 16; +SP = 18; +FP = 20; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1 >> 1; +LSETUP ( start11 , end15 ) LC0 = P5; +start11: R0 += 1; + R1 += -1; + R4 += 1; +end15: R5 += -1; + R3 += 1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start12 , end12 ) LC1 = P3 >> 1; +LSETUP ( start12 , end13 ) LC0 = P2 >> 1; +start12: R6 += 1; + R4 += 1; +end13: R5 += -1; + R3 += 1; +end12: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000018; +CHECKREG r1, 0xFFFFFFFD; +CHECKREG r2, 0x00000024; +CHECKREG r3, 0x0000003C; +CHECKREG r4, 0x0000005D; +CHECKREG r5, 0x00000033; +CHECKREG r6, 0x0000006A; +CHECKREG r7, 0x0000006A; + +R0 = 0x04; +R1 = 0x06; +R2 = 0x08; +R3 = 0x10; +R4 = 0x12; +R5 = 0x14; +R6 = 0x16; +R7 = 0x18; +LSETUP ( start14 , end14 ) LC0 = P4; +LSETUP ( start14 , end16 ) LC1 = SP >> 1; +start14: R0 += 1; + R1 += -1; + R6 += 1; +end16: R7 += -1; + R3 += 1; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +end14: R2 += 1; + R3 += 1; +CHECKREG r0, 0x0000001A; +CHECKREG r1, 0xFFFFFFF0; +CHECKREG r2, 0x00000016; +CHECKREG r3, 0x0000002D; +CHECKREG r4, 0x0000009E; +CHECKREG r5, 0xFFFFFF88; +CHECKREG r6, 0x0000002C; +CHECKREG r7, 0x00000002; + +pass diff --git a/sim/testsuite/bfin/c_loopsetup_overlap.s b/sim/testsuite/bfin/c_loopsetup_overlap.s new file mode 100644 index 0000000..ff3b343 --- /dev/null +++ b/sim/testsuite/bfin/c_loopsetup_overlap.s @@ -0,0 +1,167 @@ +//Original:/testcases/core/c_loopsetup_overlap/c_loopsetup_overlap.dsp +// Spec Reference: loopsetup overlap +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; + +LSETUP ( start3 , end3 ) LC1 = P3; +start3: R6 += 6; +LSETUP ( start4 , end4 ) LC0 = P4 >> 1; +start4: R0 += 1; + R1 += -2; +end3: R2 += 3; + R3 += 4; +end4: R7 += -7; + R3 += 1; +CHECKREG r0, 0x0000000F; +CHECKREG r1, 0xFFFFFFFC; +CHECKREG r2, 0x0000003E; +CHECKREG r3, 0x00000044; +CHECKREG r4, 0x00000070; +CHECKREG r5, 0x00000014; +CHECKREG r6, 0x0000007E; +CHECKREG r7, 0x0000005B; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start5 , end5 ) LC0 = P5; +start5: R4 += 1; +LSETUP ( start6 , end6 ) LC1 = SP >> 1; +start6: R6 += 4; +end5: R7 += -5; + R3 += 6; +end6: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x0000004B; +CHECKREG r4, 0x00000047; +CHECKREG r5, 0x00000048; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x0000003E; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000051; +CHECKREG r4, 0x0000006B; +CHECKREG r5, 0x0000001B; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x0000003E; + +P1 = 8; +P2 = 10; +P3 = 12; +P4 = 14; +P5 = 16; +SP = 18; +FP = 20; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1; +start11: R0 += 1; + R1 += -1; +LSETUP ( start15 , end15 ) LC0 = P5; +start15: R4 += 5; +end11: R5 += -14; + R3 += 1; +end15: R2 += 17; + R3 += 12; +LSETUP ( start13 , end13 ) LC1 = P3; +start13: R6 += 1; +LSETUP ( start12 , end12 ) LC0 = P2; +start12: R4 += 22; +end13: R5 += -11; + R3 += 13; +end12: R7 += -1; + R3 += 14; +CHECKREG r0, 0x0000000D; +CHECKREG r1, 0x00000008; +CHECKREG r2, 0x00000130; +CHECKREG r3, 0x000000DC; +CHECKREG r4, 0x00000281; +CHECKREG r5, 0xFFFFFE27; +CHECKREG r6, 0x0000006C; +CHECKREG r7, 0x00000066; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start14 , end14 ) LC0 = P4; +start14: R0 += 21; + R1 += -11; +LSETUP ( start16 , end16 ) LC1 = SP; +start16: R6 += 10; +end16: R7 += -12; + R3 += 1; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 31; +end14: R5 += -1; + R3 += 11; +end17: R2 += 41; + R3 += 1; +CHECKREG r0, 0x0000012B; +CHECKREG r1, 0xFFFFFF76; +CHECKREG r2, 0x000001BA; +CHECKREG r3, 0x000000AD; +CHECKREG r4, 0x00000309; +CHECKREG r5, 0x00000039; +CHECKREG r6, 0x00000A38; +CHECKREG r7, 0xFFFFF4A0; + +pass diff --git a/sim/testsuite/bfin/c_loopsetup_preg_div2_lc0.s b/sim/testsuite/bfin/c_loopsetup_preg_div2_lc0.s new file mode 100644 index 0000000..b147659 --- /dev/null +++ b/sim/testsuite/bfin/c_loopsetup_preg_div2_lc0.s @@ -0,0 +1,95 @@ +//Original:/testcases/core/c_loopsetup_preg_div2_lc0/c_loopsetup_preg_div2_lc0.dsp +// Spec Reference: loopsetup preg lc0 / 2 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +P5 = 20; +P1 = 30; +P2 = 40; +P3 = 50; +P4 = 60; +//p5 = 7; +SP = 80 (X); +FP = 90 (X); + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1 >> 1; +start1: R0 += 1; + R1 += -2; +end1: R2 += 3; + R3 += 4; +LSETUP ( start2 , end2 ) LC0 = P2 >> 1; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +LSETUP ( start3 , end3 ) LC0 = P3 >> 1; +start3: R6 += 6; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000014; +CHECKREG r1, 0xFFFFFFF2; +CHECKREG r2, 0x0000004D; +CHECKREG r3, 0x00000036; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0xFFFFFFEC; +CHECKREG r6, 0x000000F6; +CHECKREG r7, 0xFFFFFFC1; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start4 , end4 ) LC0 = P4 >> 1; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +LSETUP ( start5 , end5 ) LC0 = P5 >> 1; +start5: R4 += 1; +end5: R5 += -2; + R3 += 3; +LSETUP ( start6 , end6 ) LC0 = SP >> 1; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +CHECKREG r0, 0x00000023; +CHECKREG r1, 0xFFFFFFD4; +CHECKREG r2, 0x0000007A; +CHECKREG r3, 0x0000003D; +CHECKREG r4, 0x0000004A; +CHECKREG r5, 0x0000003C; +CHECKREG r6, 0x00000100; +CHECKREG r7, 0xFFFFFFA8; +LSETUP ( start7 , end7 ) LC0 = FP >> 1; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000023; +CHECKREG r1, 0xFFFFFFD4; +CHECKREG r2, 0x0000007A; +CHECKREG r3, 0x00000043; +CHECKREG r4, 0x000000FE; +CHECKREG r5, 0xFFFFFF5B; +CHECKREG r6, 0x00000100; +CHECKREG r7, 0xFFFFFFA8; + + +pass diff --git a/sim/testsuite/bfin/c_loopsetup_preg_div2_lc1.s b/sim/testsuite/bfin/c_loopsetup_preg_div2_lc1.s new file mode 100644 index 0000000..73c7aa0 --- /dev/null +++ b/sim/testsuite/bfin/c_loopsetup_preg_div2_lc1.s @@ -0,0 +1,94 @@ +//Original:/testcases/core/c_loopsetup_preg_div2_lc1/c_loopsetup_preg_div2_lc1.dsp +// Spec Reference: loopsetup preg lc1 / 2 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 20; +SP = 22; +FP = 24; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1 >> 1; +start11: R0 += 1; + R1 += -1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start12 , end12 ) LC1 = P2 >> 1; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +LSETUP ( start13 , end13 ) LC1 = P3 >> 1; +start13: R6 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x0000000B; +CHECKREG r1, 0x0000000A; +CHECKREG r2, 0x00000026; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x00000047; +CHECKREG r5, 0x00000049; +CHECKREG r6, 0x00000068; +CHECKREG r7, 0x00000068; + +R0 = 0x06; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start14 , end14 ) LC1 = P4 >> 1; +start14: R0 += 1; + R1 += -1; +end14: R2 += 1; + R3 += 1; +LSETUP ( start15 , end15 ) LC1 = P5 >> 1; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +LSETUP ( start16 , end16 ) LC1 = SP >> 1; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +CHECKREG r0, 0x0000000F; +CHECKREG r1, 0x00000007; +CHECKREG r2, 0x00000029; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x0000004A; +CHECKREG r5, 0x00000046; +CHECKREG r6, 0x0000006B; +CHECKREG r7, 0x00000065; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +CHECKREG r0, 0x0000000F; +CHECKREG r1, 0x00000007; +CHECKREG r2, 0x00000029; +CHECKREG r3, 0x00000034; +CHECKREG r4, 0x00000056; +CHECKREG r5, 0x0000003A; +CHECKREG r6, 0x0000006B; +CHECKREG r7, 0x00000065; + +pass diff --git a/sim/testsuite/bfin/c_loopsetup_preg_lc0.s b/sim/testsuite/bfin/c_loopsetup_preg_lc0.s new file mode 100644 index 0000000..4429b1e --- /dev/null +++ b/sim/testsuite/bfin/c_loopsetup_preg_lc0.s @@ -0,0 +1,95 @@ +//Original:/testcases/core/c_loopsetup_preg_lc0/c_loopsetup_preg_lc0.dsp +// Spec Reference: loopsetup preg lc0 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +end1: R2 += 3; + R3 += 4; +LSETUP ( start2 , end2 ) LC0 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +LSETUP ( start3 , end3 ) LC0 = P3; +start3: R6 += 6; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000008; +CHECKREG r1, 0x0000000A; +CHECKREG r2, 0x00000029; +CHECKREG r3, 0x00000036; +CHECKREG r4, 0x00000050; +CHECKREG r5, 0x0000003C; +CHECKREG r6, 0x0000007E; +CHECKREG r7, 0x0000004D; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start4 , end4 ) LC0 = P4; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +LSETUP ( start5 , end5 ) LC0 = P5; +start5: R4 += 1; +end5: R5 += -2; + R3 += 3; +LSETUP ( start6 , end6 ) LC0 = SP; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +CHECKREG r0, 0x0000000B; +CHECKREG r1, 0x00000004; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x0000003D; +CHECKREG r4, 0x00000047; +CHECKREG r5, 0x00000042; +CHECKREG r6, 0x00000080; +CHECKREG r7, 0x00000048; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x0000000B; +CHECKREG r1, 0x00000004; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x00000043; +CHECKREG r4, 0x0000006B; +CHECKREG r5, 0x00000015; +CHECKREG r6, 0x00000080; +CHECKREG r7, 0x00000048; + + +pass diff --git a/sim/testsuite/bfin/c_loopsetup_preg_lc1.s b/sim/testsuite/bfin/c_loopsetup_preg_lc1.s new file mode 100644 index 0000000..8970f40 --- /dev/null +++ b/sim/testsuite/bfin/c_loopsetup_preg_lc1.s @@ -0,0 +1,93 @@ +//Original:/testcases/core/c_loopsetup_preg_lc1/c_loopsetup_preg_lc1.dsp +// Spec Reference: loopsetup preg lc1 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 20; +SP = 22; +FP = 24; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1; +start11: R0 += 1; + R1 += -1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start12 , end12 ) LC1 = P2; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +LSETUP ( start13 , end13 ) LC1 = P3; +start13: R6 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000011; +CHECKREG r1, 0x00000004; +CHECKREG r2, 0x0000002C; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x0000004E; +CHECKREG r5, 0x00000042; +CHECKREG r6, 0x00000070; +CHECKREG r7, 0x00000060; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start14 , end14 ) LC1 = P4; +start14: R0 += 1; + R1 += -1; +end14: R2 += 1; + R3 += 1; +LSETUP ( start15 , end15 ) LC1 = P5; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +LSETUP ( start16 , end16 ) LC1 = SP; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000017; +CHECKREG r1, 0xFFFFFFFE; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x00000054; +CHECKREG r5, 0x0000003c; +CHECKREG r6, 0x00000076; +CHECKREG r7, 0x0000005A; +LSETUP ( start17 , end17 ) LC1 = FP; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +CHECKREG r0, 0x00000017; +CHECKREG r1, 0xFFFFFFFE; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x00000034; +CHECKREG r4, 0x0000006c; +CHECKREG r5, 0x00000024; +CHECKREG r6, 0x00000076; +CHECKREG r7, 0x0000005A; + +pass diff --git a/sim/testsuite/bfin/c_loopsetup_preg_stld.s b/sim/testsuite/bfin/c_loopsetup_preg_stld.s new file mode 100644 index 0000000..ab549a6 --- /dev/null +++ b/sim/testsuite/bfin/c_loopsetup_preg_stld.s @@ -0,0 +1,194 @@ +//Original:/testcases/core/c_loopsetup_preg_stld/c_loopsetup_preg_stld.dsp +// Spec Reference: loopsetup preg st & ld +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + A0 = 0; + A1 = 0; + ASTAT = r0; + + P1 = 9; + P2 = 8; + P0 = 7; + P4 = 6; + P5 = 5; + FP = 3; + + imm32 r0, 0x00200005; + imm32 r1, 0x00300010; + imm32 r2, 0x00500012; + imm32 r3, 0x00600024; + imm32 r4, 0x00700016; + imm32 r5, 0x00900028; + imm32 r6, 0x0a000030; + imm32 r7, 0x00b00044; + + loadsym I0, DATA0; + loadsym I1, DATA1; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + LSETUP ( start1 , end1 ) LC0 = P1; +start1: + R0 += 1; + R1 += 2; + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; +end1: + R2 += 3; + + R3 = ( A0 += A1 ); + + A0 = 0; + A1 = 0; + LSETUP ( start2 , end2 ) LC0 = P2; +start2: + R4 += 4; + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 -- ] || R1 = [ I1 -- ]; +end2: + R5 += -5; + R6 = ( A0 += A1 ); + CHECKREG r0, 0x000D0003; + CHECKREG r1, 0x00C00103; + CHECKREG r2, 0x0050002D; + CHECKREG r3, 0x00010794; + CHECKREG r4, 0x00700036; + CHECKREG r5, 0x00900000; + CHECKREG r6, 0x00011388; + CHECKREG r7, 0x00B00044; + + imm32 r0, 0x01200805; + imm32 r1, 0x02300710; + imm32 r2, 0x03500612; + imm32 r3, 0x04600524; + imm32 r4, 0x05700416; + imm32 r5, 0x06900328; + imm32 r6, 0x0a700230; + imm32 r7, 0x08b00044; + + loadsym I2, DATA0; + loadsym I3, DATA1; + [ I2 ++ ] = R0; + [ I3 ++ ] = R1; + LSETUP ( start3 , end3 ) LC0 = P1; +start3: + [ I2 ++ ] = R2; + [ I3 ++ ] = R3; + R2 += 1; +end3: + R3 += 1; + + A0 = 0; + A1 = 0; + LSETUP ( start4 , end4 ) LC0 = P2; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; +start4: + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I2 -- ] || R1 = [ I3 -- ]; + R4 = R4 + R0; // comp3op +end4: + R5 = R5 + R1; + + R6 = ( A0 += A1 ); + CHECKREG r0, 0x03500614; + CHECKREG r1, 0x04600526; + CHECKREG r2, 0x0350061B; + CHECKREG r3, 0x0460052D; + CHECKREG r4, 0x1CF02EC1; + CHECKREG r5, 0x25602851; + CHECKREG r6, 0x0282F220; + CHECKREG r7, 0x08B00044; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + .dd 0x000f0005 + .dd 0x00100006 + .dd 0x00200007 + .dd 0x00300008 + .dd 0x00400009 + .dd 0x0050000a + .dd 0x0060000b + .dd 0x0070000c + .dd 0x0080000d + .dd 0x0090000e + .dd 0x0100000f + .dd 0x02000010 + .dd 0x03000011 + .dd 0x04000012 + .dd 0x05000013 + .dd 0x06000014 + .dd 0x001a0000 + .dd 0x001b0001 + .dd 0x001c0002 + .dd 0x001d0003 + .dd 0x00010004 + .dd 0x00010005 + .dd 0x02100006 + .dd 0x02200007 + .dd 0x02300008 + .dd 0x02200009 + .dd 0x0250000a + .dd 0x0260000b + .dd 0x0270000c + .dd 0x0280000d + .dd 0x0290000e + .dd 0x2100000f + .dd 0x22000010 + .dd 0x22000011 + .dd 0x24000012 + .dd 0x25000013 + .dd 0x26000014 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 + .dd 0x00b00104 + .dd 0x00a00105 + .dd 0x00900106 + .dd 0x00800107 + .dd 0x00100108 + .dd 0x00200109 + .dd 0x0030010a + .dd 0x0040010b + .dd 0x0050011c + .dd 0x0060010d + .dd 0x0070010e + .dd 0x0080010f + .dd 0x00900110 + .dd 0x01000111 + .dd 0x02000112 + .dd 0x03000113 + .dd 0x04000114 + .dd 0x05000115 + .dd 0x03f00100 + .dd 0x03e00101 + .dd 0x03d00102 + .dd 0x03c00103 + .dd 0x03b00104 + .dd 0x03a00105 + .dd 0x03900106 + .dd 0x03800107 + .dd 0x03100108 + .dd 0x03200109 + .dd 0x0330010a + .dd 0x0330010b + .dd 0x0350011c + .dd 0x0360010d + .dd 0x0370010e + .dd 0x0380010f + .dd 0x03900110 + .dd 0x31000111 + .dd 0x32000112 + .dd 0x33000113 + .dd 0x34000114 diff --git a/sim/testsuite/bfin/c_loopsetup_prelc.s b/sim/testsuite/bfin/c_loopsetup_prelc.s new file mode 100644 index 0000000..527988a --- /dev/null +++ b/sim/testsuite/bfin/c_loopsetup_prelc.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_loopsetup_prelc/c_loopsetup_prelc.dsp +// Spec Reference: loopsetup preload lc0 lc1 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); + +LC0 = R0; +LC1 = R1; + +LSETUP ( start1 , end1 ) LC0; +start1: R0 += 1; + R1 += -2; +end1: R2 += 3; + R3 += 4; +LSETUP ( start2 , end2 ) LC1; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +LSETUP ( start3 , end3 ) LC0 = P3; +start3: R6 += 6; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x0000000a; +CHECKREG r1, 0x00000006; +CHECKREG r2, 0x0000002f; +CHECKREG r3, 0x00000036; +CHECKREG r4, 0x00000080; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x0000007E; +CHECKREG r7, 0x0000004D; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); + +LC0 = R2; +LC1 = R3; + +LSETUP ( start4 , end4 ) LC0; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +LSETUP ( start5 , end5 ) LC1; +start5: R4 += 1; +end5: R5 += -2; + R3 += 3; + +LSETUP ( start6 , end6 ) LC0 = P2; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +CHECKREG r0, 0x00000025; +CHECKREG r1, 0xFFFFFFD0; +CHECKREG r2, 0x00000080; +CHECKREG r3, 0x0000003D; +CHECKREG r4, 0x00000070; +CHECKREG r5, 0xFFFFFFF0; +CHECKREG r6, 0x00000070; +CHECKREG r7, 0x0000005C; +LSETUP ( start7 , end7 ) LC1; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000025; +CHECKREG r1, 0xFFFFFFD0; +CHECKREG r2, 0x00000080; +CHECKREG r3, 0x00000043; +CHECKREG r4, 0x00000074; +CHECKREG r5, 0xFFFFFFEB; +CHECKREG r6, 0x00000070; +CHECKREG r7, 0x0000005C; + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 20; +SP = 22; +FP = 24; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x25; +R7 = 0x32; + +LC0 = R6; +LC1 = R7; +LSETUP ( start11 , end11 ) LC0; +start11: R0 += 1; + R1 += -1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start12 , end12 ) LC1; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +LSETUP ( start13 , end13 ) LC1 = P4; +start13: R6 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x0000002A; +CHECKREG r1, 0xFFFFFFEB; +CHECKREG r2, 0x00000045; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x00000072; +CHECKREG r5, 0x0000001E; +CHECKREG r6, 0x00000037; +CHECKREG r7, 0x00000020; + + +pass diff --git a/sim/testsuite/bfin/c_loopsetup_topbotcntr.s b/sim/testsuite/bfin/c_loopsetup_topbotcntr.s new file mode 100644 index 0000000..dc19b7d --- /dev/null +++ b/sim/testsuite/bfin/c_loopsetup_topbotcntr.s @@ -0,0 +1,110 @@ +//Original:/proj/frio/dv/testcases/core/c_loopsetup_topbotcntr/c_loopsetup_topbotcntr.dsp +// Spec Reference: loopsetup top bot counter +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + + ASTAT = r0; + + R1 = 0x10; + R2 = 0x20; + R3 = 0x30; + R4 = 0x40 (X); + R5 = 0x08; + + loadsym R6, start1; + loadsym R7, end1; + + LT0 = R6; + LB0 = R7; + LC0 = R5; +//start immmediately +start1: R0 += 1; + R1 += -2; +end1: R2 += 3; + R3 += 4; + + CHECKREG r0, 0x00000008; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000038; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000040; + CHECKREG r5, 0x00000008; +//CHECKREG r6, 0x00000090; +//CHECKREG r7, 0x00000094; + + R0 = 0x05; + R1 = 0x10; + R2 = 0x10; + R3 = 0x10; + R4 = 0x20; + R5 = 0x20; + R6 = 0x30; + R7 = 0x30; + + loadsym R1, start2; + R0 = R1; + loadsym R1, end2; + LT1 = R0; + LB1 = R1; + LC1 = R2; + +start2: R4 += 1; + R5 += 2; +end2: R6 += -3; + R7 += 4; + CHECKREG r3, 0x00000010; + CHECKREG r4, 0x00000030; + CHECKREG r5, 0x00000040; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000034; + + R0 = 0x05; + R1 = 0x10; + R2 = 0x20; + R3 = 0x30; + R4 = 0x40 (X); + R5 = 0x50 (X); + R6 = 0x60 (X); + R7 = 0x70 (X); + + loadsym R1, start3 + r0 = r1; + loadsym r1, end3; + LT0 = R0; + LB0 = R1; + LC0 = R2; + loadsym r3, start4; + loadsym r4, end4; + LT1 = R3; + LB1 = R4; + LC1 = R5; + + R0 = 0x10; + R1 = 0x15; + R2 = 0x20; + R3 = 0x26; + R4 = 0x30; + R5 = 0x40 (X); + +start3: R0 += 1; + R1 += -2; +start4: R2 += 3; + R3 += 4; +end4: R6 += 5; +end3: R7 += -6; + + CHECKREG r0, 0x00000030; + CHECKREG r1, 0xFFFFFFD5; + CHECKREG r2, 0x0000016D; + CHECKREG r3, 0x000001E2; + CHECKREG r4, 0x00000030; + CHECKREG r5, 0x00000040; + CHECKREG r6, 0x0000028B; + CHECKREG r7, 0xFFFFFFB0; + + pass diff --git a/sim/testsuite/bfin/c_mmr_interr_ctl.s b/sim/testsuite/bfin/c_mmr_interr_ctl.s new file mode 100644 index 0000000..ad4d88b --- /dev/null +++ b/sim/testsuite/bfin/c_mmr_interr_ctl.s @@ -0,0 +1,398 @@ +# Blackfin testcase for the CEC +# mach: bfin +# sim: --environment operating + + .include "testutils.inc" + + start + + INIT_R_REGS 0; + INIT_P_REGS 0; + INIT_I_REGS 0; + INIT_M_REGS 0; + INIT_L_REGS 0; + INIT_B_REGS 0; + + CLI R1; // inhibit events during MMR writes + + loadsym sp, USTACK; // setup the user stack pointer + usp = sp; // and frame pointer + + loadsym sp, KSTACK; // setup the stack pointer + fp = sp; // and frame pointer + + imm32 p0, 0xFFE02000; + loadsym r0, EHANDLE; // Emulation Handler (Int0) + [p0++] = r0; + + loadsym r0, RHANDLE; // Reset Handler (Int1) + [p0++] = r0; + + loadsym r0, NHANDLE; // NMI Handler (Int2) + [p0++] = r0; + + loadsym r0, XHANDLE; // Exception Handler (Int3) + [p0++] = r0; + + [p0++] = r0; // EVT4 not used global Interr Enable (INT4) + + loadsym r0, HWHANDLE; // HW Error Handler (Int5) + [p0++] = r0; + + loadsym r0, THANDLE; // Timer Handler (Int6) + [p0++] = r0; + + loadsym r0, I7HANDLE; // IVG7 Handler + [p0++] = r0; + + loadsym r0, I8HANDLE; // IVG8 Handler + [p0++] = r0; + + loadsym r0, I9HANDLE; // IVG9 Handler + [p0++] = r0; + + loadsym r0, I10HANDLE;// IVG10 Handler + [p0++] = r0; + + loadsym r0, I11HANDLE;// IVG11 Handler + [p0++] = r0; + + loadsym r0, I12HANDLE;// IVG12 Handler + [p0++] = r0; + + loadsym r0, I13HANDLE;// IVG13 Handler + [p0++] = r0; + + loadsym r0, I14HANDLE;// IVG14 Handler + [p0++] = r0; + + loadsym r0, I15HANDLE;// IVG15 Handler + [p0++] = r0; + + imm32 p0, 0xFFE02100 // EVT_OVERRIDE + r0 = 0; + [p0++] = r0; + + r1 = -1; // Change this to mask interrupts (*) + csync; // wait for MMR writes to finish + sti r1; // sync and reenable events (implicit write to IMASK) + + imm32 p0, 0xFFE02104; + r0 = [p0]; + // ckeck that sti allows the lower 5 bits of imask to be written + CHECKREG r0, 0xffff; + +DUMMY: + + r0 = 0 (z); + + LT0 = r0; // set loop counters to something deterministic + LB0 = r0; + LC0 = r0; + LT1 = r0; + LB1 = r0; + LC1 = r0; + + ASTAT = r0; // reset other internal regs + SYSCFG = r0; + RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + + loadsym r0, STARTUSER;// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) + RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + + JUMP STARTSUP; // jump to code start for SUPERVISOR mode + + RTI; + +STARTSUP: + loadsym p1, BEGIN; + + imm32 p0, (0xFFE02000 + 4 * 15); + + CLI R1; // inhibit events during write to MMR + [p0] = p1; // IVG15 (General) handler (Int 15) load with start + csync; // wait for it + sti r1; // reenable events with proper imask + + RAISE 15; // after we RTI, INT 15 should be taken + + RTI; + +// +// The Main Program +// +STARTUSER: + LINK 0; // change for how much stack frame space you need. + + JUMP BEGIN; + +// ********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [--sp] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** +// EVTx + // wrt-rd EVT0: 0 bits, rw=0 = 0xFFE02000 + imm32 p0, 0xFFE02000; + imm32 r0, 0x00000000 + [p0] = r0; + + // wrt-rd EVT1: 32 bits, rw=0 = 0xFFE02004 + imm32 p0, 0xFFE02004; + imm32 r0, 0x00000000 + [p0] = r0; + + // wrt-rd EVT2 = 0xFFE02008 + imm32 p0, 0xFFE02008 + imm32 r0, 0xE1DE5D1C + [p0] = r0; + + // wrt-rd EVT3 = 0xFFE0200C + imm32 p0, 0xFFE0200C + imm32 r0, 0x9CC20332 + [p0] = r0; + + // wrt-rd EVT4 = 0xFFE02010 + imm32 p0, 0xFFE02010 + imm32 r0, 0x00000000 + [p0] = r0; + + // wrt-rd EVT5 = 0xFFE02014 + imm32 p0, 0xFFE02014 + imm32 r0, 0x55552345 + [p0] = r0; + + // wrt-rd EVT6 = 0xFFE02018 + imm32 p0, 0xFFE02018 + imm32 r0, 0x66663456 + [p0] = r0; + + // wrt-rd EVT7 = 0xFFE0201C + imm32 p0, 0xFFE0201C + imm32 r0, 0x77774567 + [p0] = r0; + + // wrt-rd EVT8 = 0xFFE02020 + imm32 p0, 0xFFE02020 + imm32 r0, 0x88885678 + [p0] = r0; + + // wrt-rd EVT9 = 0xFFE02024 + imm32 p0, 0xFFE02024 + imm32 r0, 0x99996789 + [p0] = r0; + + // wrt-rd EVT10 = 0xFFE02028 + imm32 p0, 0xFFE02028 + imm32 r0, 0xaaaa1234 + [p0] = r0; + + // wrt-rd EVT11 = 0xFFE0202C + imm32 p0, 0xFFE0202C + imm32 r0, 0xBBBBABC6 + [p0] = r0; + + // wrt-rd EVT12 = 0xFFE02030 + imm32 p0, 0xFFE02030 + imm32 r0, 0xCCCCABC6 + [p0] = r0; + + // wrt-rd EVT13 = 0xFFE02034 + imm32 p0, 0xFFE02034 + imm32 r0, 0xDDDDABC6 + [p0] = r0; + + // wrt-rd EVT14 = 0xFFE02038 + imm32 p0, 0xFFE02038 + imm32 r0, 0xEEEEABC6 + [p0] = r0; + + // wrt-rd EVT15 = 0xFFE0203C + imm32 p0, 0xFFE0203C + imm32 r0, 0xFFFFABC6 + [p0] = r0; + + // wrt-rd EVT_OVERRIDE:9 bits = 0xFFE02100 + imm32 p0, 0xFFE02100 + imm32 r0, 0x000001ff + [p0] = r0; + + // wrt-rd IMASK: 16 bits = 0xFFE02104 + imm32 p0, 0xFFE02104 + imm32 r0, 0x00000fff + [p0] = r0; + + // wrt-rd IPEND: 16 bits, rw=0 = 0xFFE02108 + imm32 p0, 0xFFE02108 + imm32 r0, 0x00000000 + //[p0] = r0; + raise 12; + raise 13; + + // wrt-rd ILAT: 16 bits, rw=0 = 0xFFE0210C + imm32 p0, 0xFFE0210C + imm32 r0, 0x00000000 + //[p0] = r0; + csync; + + // *** read ops + imm32 p0, 0xFFE02000 + r0 = [p0]; + CHECKREG r0, 0; + + imm32 p0, 0xFFE02004 + r1 = [p0]; + CHECKREG r1, 0; + + imm32 p0, 0xFFE02008 + r2 = [p0]; + CHECKREG r2, 0xE1DE5D1C; + + imm32 p0, 0xFFE0200C + r3 = [p0]; + CHECKREG r3, 0x9CC20332; + + imm32 p0, 0xFFE02014 + r4 = [p0]; + imm32 p0, 0xFFE02018 + r5 = [p0]; + imm32 p0, 0xFFE0201C + r6 = [p0]; + imm32 p0, 0xFFE02020 /* EVT8 */ + r7 = [p0]; +CHECKREG r0, 0x00000000; +//CHECKREG(r1, 0x00000000); /// mismatch = 00 +CHECKREG r2, 0xE1DE5D1C; +CHECKREG r3, 0x9CC20332; +CHECKREG r4, 0x55552345; +CHECKREG r5, 0x66663456; +CHECKREG r6, 0x77774567; +CHECKREG r7, 0x88885678; + + imm32 p0, 0xFFE02024 /* EVT9 */ + r0 = [p0]; + imm32 p0, 0xFFE02028 /* EVT10 */ + r1 = [p0]; + imm32 p0, 0xFFE0202C /* EVT11 */ + r2 = [p0]; + imm32 p0, 0xFFE02030 /* EVT12 */ + r3 = [p0]; + imm32 p0, 0xFFE02034 /* EVT13 */ + r4 = [p0]; + imm32 p0, 0xFFE02038 /* EVT14 */ + r5 = [p0]; + imm32 p0, 0xFFE0203C /* EVT15 */ + r6 = [p0]; +CHECKREG r0, 0x99996789; +CHECKREG r1, 0xaaaa1234; +CHECKREG r2, 0xBBBBABC6; +CHECKREG r3, 0xCCCCABC6; +CHECKREG r4, 0xDDDDABC6; +CHECKREG r5, 0xEEEEABC6; +CHECKREG r6, 0xFFFFABC6; + + imm32 p0, 0xFFE02100 /* EVT_OVERRIDE */ + r0 = [p0]; + imm32 p0, 0xFFE02104 /* IMASK */ + r1 = [p0]; + imm32 p0, 0xFFE02108 /* IPEND */ + r2 = [p0]; + imm32 p0, 0xFFE0210C /* ILAT */ + r3 = [p0]; +CHECKREG r0, 0x000001ff; +CHECKREG r1, 0x00000fff; /* XXX: original had 0xfe0 ?? */ +CHECKREG r2, 0x00008000; +CHECKREG r3, 0x00003000; + + dbg_pass; + +// ********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 + RTE; + +RHANDLE: // Reset Handler 1 + RTI; + +NHANDLE: // NMI Handler 2 + r0 = 2; + RTN; + +XHANDLE: // Exception Handler 3 + + RTX; + +HWHANDLE: // HW Error Handler 5 + r2 = 5; + RTI; + +THANDLE: // Timer Handler 6 + r3 = 6; + RTI; + +I7HANDLE: // IVG 7 Handler + r4 = 7; + RTI; + +I8HANDLE: // IVG 8 Handler + r5 = 8; + RTI; + +I9HANDLE: // IVG 9 Handler + r6 = 9; + RTI; + +I10HANDLE: // IVG 10 Handler + r7 = 10; + RTI; + +I11HANDLE: // IVG 11 Handler + r0 = 11; + RTI; + +I12HANDLE: // IVG 12 Handler + r1 = 12; + RTI; + +I13HANDLE: // IVG 13 Handler + r2 = 13; + RTI; + +I14HANDLE: // IVG 14 Handler + r3 = 14; + RTI; + +I15HANDLE: // IVG 15 Handler + r4 = 15; + RTI; + + nop;nop;nop;nop;nop;nop;nop; // needed for icache bug + +// +// Data Segment +// + +.data +// Stack Segments (Both Kernel and User) + +.rep 0x10 +.byte 0 +.endr +KSTACK: + +.rep 0x10 +.byte 0 +.endr +USTACK: diff --git a/sim/testsuite/bfin/c_mmr_loop.S b/sim/testsuite/bfin/c_mmr_loop.S new file mode 100644 index 0000000..b0fa404 --- /dev/null +++ b/sim/testsuite/bfin/c_mmr_loop.S @@ -0,0 +1,417 @@ +//Original:/proj/frio/dv/testcases/core/c_mmr_loop/c_mmr_loop.dsp +// Spec Reference: mmr loop (interr control) no exception +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we set the processor operating modes, initialize registers +// etc.) +// + +BOOT: + +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + //CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; // and frame pointer + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// +STARTUSER: +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + + + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** +// EVTx + // wrt-rd EVT0: 0 bits, rw=0 = 0xFFE02000 +LD32(p0, 0xFFE02000); +LD32(r0, 0x00000000); + [ P0 ] = R0; + + // wrt-rd EVT1: 32 bits, rw=0 = 0xFFE02004 +LD32(p0, 0xFFE02004); +LD32(r0, 0x00000000); + [ P0 ] = R0; + + // wrt-rd EVT2 = 0xFFE02008 +LD32(p0, 0xFFE02008); +LD32(r0, 0xE1DE5D1C); + [ P0 ] = R0; + + // wrt-rd EVT3 = 0xFFE0200C +LD32(p0, 0xFFE0200C); +LD32(r0, 0x9CC20332); + [ P0 ] = R0; + + // wrt-rd EVT4 = 0xFFE02010 +LD32(p0, 0xFFE02010); +LD32(r0, 0x00000000); // not implemented + [ P0 ] = R0; + + // wrt-rd EVT5 = 0xFFE02014 +LD32(p0, 0xFFE02014); +LD32(r0, 0x55552345); + [ P0 ] = R0; + + // wrt-rd EVT6 = 0xFFE02018 +LD32(p0, 0xFFE02018); +LD32(r0, 0x66663456); + [ P0 ] = R0; + + // wrt-rd EVT7 = 0xFFE0201C +LD32(p0, 0xFFE0201C); +LD32(r0, 0x77774567); + [ P0 ] = R0; + + // wrt-rd EVT8 = 0xFFE02020 +LD32(p0, 0xFFE02020); +LD32(r0, 0x88885678); + [ P0 ] = R0; + + // wrt-rd EVT9 = 0xFFE02024 +LD32(p0, 0xFFE02024); +LD32(r0, 0x99996789); + [ P0 ] = R0; + + // wrt-rd EVT10 = 0xFFE02028 +LD32(p0, 0xFFE02028); +LD32(r0, 0xaaaa1234); + [ P0 ] = R0; + + // wrt-rd EVT11 = 0xFFE0202C +LD32(p0, 0xFFE0202C); +LD32(r0, 0xBBBBABC6); + [ P0 ] = R0; + + // wrt-rd EVT12 = 0xFFE02030 +LD32(p0, 0xFFE02030); +LD32(r0, 0xCCCCABC6); + [ P0 ] = R0; + + // wrt-rd EVT13 = 0xFFE02034 +LD32(p0, 0xFFE02034); +LD32(r0, 0xDDDDABC6); + [ P0 ] = R0; + + // wrt-rd EVT14 = 0xFFE02038 +LD32(p0, 0xFFE02038); +LD32(r0, 0xEEEEABC6); + [ P0 ] = R0; + + // wrt-rd EVT15 = 0xFFE0203C +LD32(p0, 0xFFE0203C); +LD32(r0, 0xFFFFABC6); + [ P0 ] = R0; + + // wrt-rd EVT_OVERRIDE:9 bits = 0xFFE02100 +LD32(p0, 0xFFE02100); +LD32(r0, 0x000001ff); + [ P0 ] = R0; + + // wrt-rd IMASK: 16 bits = 0xFFE02104 +LD32(p0, 0xFFE02104); +LD32(r0, 0x00000fe0); + [ P0 ] = R0; + + + // wrt-rd IPEND: 16 bits, rw=0 = 0xFFE02108 +LD32(p0, 0xFFE02108); +LD32(r0, 0x00000000); + //[p0] = r0; +RAISE 12; +RAISE 13; + + // wrt-rd ILAT: 16 bits, rw=0 = 0xFFE0210C +LD32(p0, 0xFFE0210C); +LD32(r0, 0x00000000); + //[p0] = r0; +CSYNC; +//*** read ops +P1.L = DATA0; +P1.H = DATA0; + +LD32(p0, 0xFFE02000); + P2 = 16; +LSETUP ( start1 , end1 ) LC0 = P2; +start1: + R0 = [ P0 ++ ]; +end1: [ P1 ++ ] = R0; +//nop; +P1.L = DATA0; +P1.H = DATA0; + R0 = [ P1 ++ ]; + R1 = [ P1 ++ ]; + R2 = [ P1 ++ ]; + R3 = [ P1 ++ ]; + R4 = [ P1 ++ ]; + R5 = [ P1 ++ ]; + R6 = [ P1 ++ ]; + R7 = [ P1 ++ ]; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0xE1DE5D1C); +CHECKREG(r3, 0x9CC20332); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x55552345); +CHECKREG(r6, 0x66663456); +CHECKREG(r7, 0x77774567); + R0 = [ P1 ++ ]; + R1 = [ P1 ++ ]; + R2 = [ P1 ++ ]; + R3 = [ P1 ++ ]; + R4 = [ P1 ++ ]; + R5 = [ P1 ++ ]; + R6 = [ P1 ++ ]; + R7 = [ P1 ++ ]; +CHECKREG(r0, 0x88885678); +CHECKREG(r1, 0x99996789); +CHECKREG(r2, 0xAAAA1234); +CHECKREG(r3, 0xBBBBABC6); +CHECKREG(r4, 0xCCCCABC6); +CHECKREG(r5, 0xDDDDABC6); +CHECKREG(r6, 0xEEEEABC6); +CHECKREG(r7, 0xFFFFABC6); + +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + R7 = 0x00006789 (X); +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA0: +.dd 0x000a0000 +.dd 0x000b0001 +.dd 0x000c0002 +.dd 0x000d0003 +.dd 0x000e0004 +.dd 0x000f0005 +.dd 0x00100006 +.dd 0x00200007 +.dd 0x00300008 +.dd 0x00400009 +.dd 0x0050000a +.dd 0x0060000b +.dd 0x0070000c +.dd 0x0080000d +.dd 0x0090000e +.dd 0x0100000f +.dd 0x02000010 +.dd 0x03000011 +.dd 0x04000012 +.dd 0x05000013 +.dd 0x06000014 +.dd 0x001a0000 +.dd 0x001b0001 +.dd 0x001c0002 +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_mmr_loop_user_except.S b/sim/testsuite/bfin/c_mmr_loop_user_except.S new file mode 100644 index 0000000..7e0bc40 --- /dev/null +++ b/sim/testsuite/bfin/c_mmr_loop_user_except.S @@ -0,0 +1,325 @@ +//Original:/proj/frio/dv/testcases/core/c_mmr_loop_user_except/c_mmr_loop_user_except.dsp +// Spec Reference: c_mmr_loop_user_except +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we set the processor operating modes, initialize registers +// etc.) +// + +BOOT: + +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + //CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; // and frame pointer + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) + + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +// LD32_LABEL(r0, I13HANDLE);// IVG13 Handler +// [p0++] = r0; + +// LD32_LABEL(r0, I14HANDLE);// IVG14 Handler +// [p0++] = r0; + +//***************** + // wrt-rd EVT13 = 0xFFE02034 +LD32(p0, 0xFFE02034); +LD32(r0, 0xDDDDABC6); + [ P0 ] = R0; + + // wrt-rd EVT14 = 0xFFE02038 +LD32(p0, 0xFFE02038); +LD32(r0, 0xEEEEABC6); + [ P0 ] = R0; +//***************** +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; // execute this instr put us in USER mode + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // USER MODE & go to different RAISE in USER mode + // until the end of the test. + +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +// LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +// RAISE 2; // RTN // exception because we execute this in USER mode + R0 = 0; +LD32(p0, 0xFFE02034); + P2 = 2; +LSETUP ( start1 , end1 ) LC0 = P2; +start1: + R0 = [ P0 ++ ]; // 16 bit instr +end1: R1 = R0; + +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +//CHECKREG(r3, 0x00000030); +CHECKREG(r4, 0x0000000F); +CHECKREG(r5, 0x00000012); +CHECKREG(r6, 0x00000015); +CHECKREG(r7, 0x00000018); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = RETN; + R0 += 2; +RETN = r0; +RTN; + +XHANDLE: // Exception Handler 3 + R3 = RETX; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; + R3 += 2; // for resturn address +RETX = r3; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = RETI; + R2 += 2; +RETI = r2; +RTI; + +THANDLE: // Timer Handler 6 + R3 = RETI; + R3 += 2; +RETI = r3; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = RETI; + R4 += 2; +RETI = r4; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = RETI; + R5 += 2; +RETI = r5; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = RETI; + R6 += 2; +RETI = r6; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = RETI; + R7 += 2; +RETI = r7; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = RETI; + R0 += 2; +RETI = r0; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = RETI; + R1 += 2; +RETI = r1; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = RETI; + R2 += 2; +RETI = r2; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = RETI; + R3 += 2; +RETI = r3; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: +// .space (STACKSIZE); // adding this may solve the problem diff --git a/sim/testsuite/bfin/c_mmr_ppop_illegal_adr.S b/sim/testsuite/bfin/c_mmr_ppop_illegal_adr.S new file mode 100644 index 0000000..82bb45d --- /dev/null +++ b/sim/testsuite/bfin/c_mmr_ppop_illegal_adr.S @@ -0,0 +1,307 @@ +//Original:/proj/frio/dv/testcases/core/c_mmr_ppop_illegal_adr/c_mmr_ppop_illegal_adr.dsp +// Spec Reference: mmr ppop illegal address +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we set the processor operating modes, initialize registers +// etc.) +// + +BOOT: + +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + //CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; // and frame pointer + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// +STARTUSER: +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + + + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + +LD32(r0, 0206037020); +LD32(r1, 0x10070030); +LD32(r2, 0xe2000043); +LD32(r3, 0x30305050); +LD32(r4, 0x0f040860); +LD32(r5, 0x0a0050d0); +LD32(r6, 0x00000000); +LD32(r7, 0x0f060071); +// LD32(sp, 0xFFE02104); +// [--sp] = (r7-r6); + [ -- SP ] = R7; + [ -- SP ] = R6; +.dd 0xffff + R1 += 2; + +CHECKREG(r1, 0x10070034); +CHECKREG(r2, 0xE2000046); +CHECKREG(r3, 0x30305054); +CHECKREG(r4, 0x0f040865); +CHECKREG(r5, 0x0a0050d6); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x0f060079); + R7 = [ SP ++ ]; +CHECKREG(r7, 0x00000000); + +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 +R0 = RETX; // error handler:RETX has the address of the same Illegal instr + R1 += 2; + R2 += 3; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; +R0 += 2; // we have to add 2 to point to next instr after return (16-bit illegal instr) +RETX = R0; +NOP; NOP; NOP; NOP; + + +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA0: +.dd 0x000a0000 +.dd 0x000b0001 +.dd 0x000c0002 +.dd 0x000d0003 +.dd 0x000e0004 +.dd 0x000f0005 +.dd 0x00100006 +.dd 0x00200007 +.dd 0x00300008 +.dd 0x00400009 +.dd 0x0050000a +.dd 0x0060000b +.dd 0x0070000c +.dd 0x0080000d +.dd 0x0090000e +.dd 0x0100000f +.dd 0x02000010 +.dd 0x03000011 +.dd 0x04000012 +.dd 0x05000013 +.dd 0x06000014 +.dd 0x001a0000 +.dd 0x001b0001 +.dd 0x001c0002 +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_mmr_ppopm_illegal_adr.S b/sim/testsuite/bfin/c_mmr_ppopm_illegal_adr.S new file mode 100644 index 0000000..0b78d5e --- /dev/null +++ b/sim/testsuite/bfin/c_mmr_ppopm_illegal_adr.S @@ -0,0 +1,308 @@ +//Original:/proj/frio/dv/testcases/core/c_mmr_ppopm_illegal_adr/c_mmr_ppopm_illegal_adr.dsp +// Spec Reference: mmr ppopm illegal address +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we set the processor operating modes, initialize registers +// etc.) +// + +BOOT: + +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + //CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; // and frame pointer + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// +STARTUSER: +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + + + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + +LD32(r0, 0206037020); +LD32(r1, 0x10070030); +LD32(r2, 0xe2000043); +LD32(r3, 0x30305050); +LD32(r4, 0x0f040860); +LD32(r5, 0x0a0050d0); +LD32(r6, 0x00000000); +LD32(r7, 0x0f060071); + [ -- SP ] = ( R7:7 ); +LD32(r7, 0x123456af); + [ -- SP ] = ( R7:6 ); +// [--sp] = r7; +// [--sp] = r6; +.dd 0xffff + R1 += 2; + +CHECKREG(r1, 0x10070034); +CHECKREG(r2, 0xE2000046); +CHECKREG(r3, 0x30305054); +CHECKREG(r4, 0x0f040865); +CHECKREG(r5, 0x0a0050d6); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x123456b7); + R7 = [ SP ++ ]; +CHECKREG(r7, 0x123456af); + +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 +R0 = RETX; // error handler:RETX has the address of the same Illegal instr + R1 += 2; + R2 += 3; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; +R0 += 2; // we have to add 2 to point to next instr after return (16-bit illegal instr) +RETX = R0; +NOP; NOP; NOP; NOP; + + +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA0: +.dd 0x000a0000 +.dd 0x000b0001 +.dd 0x000c0002 +.dd 0x000d0003 +.dd 0x000e0004 +.dd 0x000f0005 +.dd 0x00100006 +.dd 0x00200007 +.dd 0x00300008 +.dd 0x00400009 +.dd 0x0050000a +.dd 0x0060000b +.dd 0x0070000c +.dd 0x0080000d +.dd 0x0090000e +.dd 0x0100000f +.dd 0x02000010 +.dd 0x03000011 +.dd 0x04000012 +.dd 0x05000013 +.dd 0x06000014 +.dd 0x001a0000 +.dd 0x001b0001 +.dd 0x001c0002 +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_mmr_timer.S b/sim/testsuite/bfin/c_mmr_timer.S new file mode 100644 index 0000000..ac34e17 --- /dev/null +++ b/sim/testsuite/bfin/c_mmr_timer.S @@ -0,0 +1,282 @@ +//Original:/proj/frio/dv/testcases/core/c_mmr_timer/c_mmr_timer.dsp +// Spec Reference: mmr timer +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we set the processor operating modes, initialize registers +// etc.) +// + +BOOT: + +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + //CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; // and frame pointer + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// +STARTUSER: +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // TCNTL: 4 bits, rw=1 = 0xFFE03000 +LD32(p0, 0xFFE03000); +LD32(r0, 0x0000000D); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R1 = [ P0 ]; + + // TPERIOD: 32 bits, rw=1 = 0xFFE03004 +LD32(p0, 0xFFE03004); +LD32(r0, 0x11112222); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R2 = [ P0 ]; + + // TSCALE: 8 bits, rw=1 = 0xFFE03008 +LD32(p0, 0xFFE03008); +LD32(r0, 0x00000050); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R3 = [ P0 ]; + + + // TCOUNT: 32 bits, rw=1 = 0xFFE0300C +LD32(p0, 0xFFE0300C); +LD32(r0, 0x00000100); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R4 = [ P0 ]; + + +CHECKREG(r1, 0x0000000D); +CHECKREG(r2, 0x11112222); +CHECKREG(r3, 0x00000050); +CHECKREG(r4, 0x00000100); + +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +//.data 0xFFE03000 +//.dd 0x00000000 diff --git a/sim/testsuite/bfin/c_mode_supervisor.S b/sim/testsuite/bfin/c_mode_supervisor.S new file mode 100644 index 0000000..4ea0d6c --- /dev/null +++ b/sim/testsuite/bfin/c_mode_supervisor.S @@ -0,0 +1,287 @@ +//Original:/proj/frio/dv/testcases/core/c_mode_supervisor/c_mode_supervisor.dsp +// Spec Reference: mode_supervisor +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +RAISE 2; // RTN +RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI +RAISE 15; // RTI + +CHECKREG(r0, 0x0000000B); +CHECKREG(r1, 0x0000000C); +CHECKREG(r2, 0x0000000D); +CHECKREG(r3, 0x0000000E); +CHECKREG(r4, 0x00000007); +CHECKREG(r5, 0x00000008); +CHECKREG(r6, 0x00000009); +CHECKREG(r7, 0x0000000A); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +CHECKREG(r0, 0x00000002); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000005); +CHECKREG(r3, 0x00000006); +CHECKREG(r4, 0x00000007); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_mode_user.S b/sim/testsuite/bfin/c_mode_user.S new file mode 100644 index 0000000..1b72035 --- /dev/null +++ b/sim/testsuite/bfin/c_mode_user.S @@ -0,0 +1,338 @@ +//Original:/proj/frio/dv/testcases/core/c_mode_user/c_mode_user.dsp +// Spec Reference: mode_user +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + A0 = 0; // reset accumulators + A1 = 0; + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; // execute this instr put us in USER mode + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // USER MODE & go to different RAISE in USER mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +A1 = A0 = 0; +ASTAT = R0; + + +// R-reg to P-reg to R reg: stall +LD32(r0, 0x1357bdad); +LD32(r1, 0x02dfe804); +LD32(r2, 0x12345679); +LD32(r3, 0x34751975); +LD32(r4, 0x08810990); +LD32(r5, 0x01a1b0b0); +LD32(r6, 0x01c1dd00); +LD32(r7, 0x01e1fff0); +R5 = R3.L * R1.L, R4 = R3.L * R1.L; // dsp32mult_pair +P4 = R5; +R6 = P4; +R1 = ( A1 += R5.L * R6.H ), A0 = R5.H * R6.L; // dsp32mac_pair +P3 = A0.w; +P4 = A1.w; +A1 = A1 (S), A0 = A0 (S); // dsp32alu_sat_aa +R6 = A0.w; +R7 = A1.w; +R0 = R7; +R2 = R0; // regmv +R2 >>>= R3; // c_alu2op_arith_r_sft.dsp +R4 = R2 - R1; +R5.L = ASHIFT R4.L BY R3.L; +R6 += -3; //c_compi2opd_dr_add_i7_n.dsp +I2 = R6; +I2 += 2; +I2 += M1; +R7 = I2; + + +CHECKREG(r0, 0x015AF820); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x34751975); +CHECKREG(r4, 0xFEA507E0); +CHECKREG(r5, 0xFB3A0000); +CHECKREG(r6, 0x015AF81D); +CHECKREG(r7, 0x015AF81F); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x015AF81F); +CHECKREG(r3, 0x00000000); +CHECKREG(r4, 0xFEA507E0); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = RETN; + R0 += 2; +RETN = r0; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = RETX; + R0 += 1; + R1 += 2; + R2 += 1; + R3 += 1; + R4 += 1; + R5 += 1; + R6 += 1; + R7 += 1; +RETX = r1; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = RETI; + R2 += 2; +RETI = r2; +RTI; + +THANDLE: // Timer Handler 6 + R3 = RETI; + R3 += 2; +RETI = r3; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = RETI; + R4 += 2; +RETI = r4; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = RETI; + R5 += 2; +RETI = r5; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = RETI; + R6 += 2; +RETI = r6; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = RETI; + R7 += 2; +RETI = r7; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = RETI; + R0 += 2; +RETI = r0; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = RETI; + R1 += 2; +RETI = r1; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = RETI; + R2 += 2; +RETI = r2; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = RETI; + R3 += 2; +RETI = r3; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: +// .space (STACKSIZE); // adding this may solve the problem diff --git a/sim/testsuite/bfin/c_mode_user_superivsor.S b/sim/testsuite/bfin/c_mode_user_superivsor.S new file mode 100644 index 0000000..ef8a2b4 --- /dev/null +++ b/sim/testsuite/bfin/c_mode_user_superivsor.S @@ -0,0 +1,353 @@ +//Original:/proj/frio/dv/testcases/core/c_mode_user_superivsor/c_mode_user_superivsor.dsp +// Spec Reference: mode_user_supervisor +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; // execute this instr put us in USER mode + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // USER MODE & go to different RAISE in USER mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 +RAISE 2; // RTN +RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; + +CHECKREG(r0, 0x00000018); +CHECKREG(r1, 0x00000018); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000018); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x00000000); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = RETN; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETN = r0; +RTN; + +XHANDLE: // Exception Handler 3 + R0 = RETX; + I0 += 2; + I1 += 2; + I3 += 2; + R0 += 2; +RETX = r0; +RTX; + +HWHANDLE: // HW Error Handler 5 + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + R0 += 2; +RETI = r0; +RTI; + +THANDLE: // Timer Handler 6 + R0 = RETI; + R0 += 2; +RETI = r0; +RTI; + +I7HANDLE: // IVG 7 Handler + R0 = RETI; + I0 += 2; + I1 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I8HANDLE: // IVG 8 Handler + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + M0 = I0; + M1 = I1; + M2 = I2; + M3 = I3; + R0 += 2; +RETI = r0; +RTI; + +I9HANDLE: // IVG 9 Handler + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I10HANDLE: // IVG 10 Handler + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + M0 = R4; + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I12HANDLE: // IVG 12 Handler + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I13HANDLE: // IVG 13 Handler + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I14HANDLE: // IVG 14 Handler + R0 = RETI; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; + I1 += 2; + I2 += 2; +RTI; + +// nop;nop;nop;nop;nop;nop;nop; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: +// .space (STACKSIZE); // adding this may solve the problem diff --git a/sim/testsuite/bfin/c_multi_issue_dsp_ld_ld.s b/sim/testsuite/bfin/c_multi_issue_dsp_ld_ld.s new file mode 100644 index 0000000..1af87dc --- /dev/null +++ b/sim/testsuite/bfin/c_multi_issue_dsp_ld_ld.s @@ -0,0 +1,197 @@ +//Original:/testcases/core/c_multi_issue_dsp_ld_ld/c_multi_issue_dsp_ld_ld.dsp +// Spec Reference: dsp32mac and 2 loads +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + imm32 r0, 0x00000000; + A0 = 0; + A1 = 0; + ASTAT = r0; + + loadsym I0, DATA0 + loadsym I1, DATA1 + + loadsym P1, DATA0 + loadsym P2, DATA1 + +// test the default (signed fraction : left ) + imm32 r0, 0x12345678; + imm32 r1, 0x33456789; + imm32 r2, 0x5556789a; + imm32 r3, 0x75678912; + imm32 r4, 0x86789123; + imm32 r5, 0xa7891234; + imm32 r6, 0xc1234567; + imm32 r7, 0xf1234567; + A1 = R0.L * R1.L, A0 = R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; + A1 += R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ I0 ++ ] || R3 = [ I1 ++ ]; + A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = [ P1 ++ ] || R5 = [ I1 ++ ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x000A0000; + CHECKREG r1, 0x00F00100; + CHECKREG r2, 0x000B0001; + CHECKREG r3, 0x00E00101; + CHECKREG r4, 0x000A0000; + CHECKREG r5, 0x00D00102; + CHECKREG r6, 0x92793486; + CHECKREG r7, 0xDD2F9BAA; + + imm32 r0, 0x12245618; + imm32 r1, 0x23256719; + imm32 r2, 0x3426781a; + imm32 r3, 0x45278912; + imm32 r4, 0x56289113; + imm32 r5, 0x67291214; + imm32 r6, 0xa1234517; + imm32 r7, 0xc1234517; + A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = [ P1 ++ ] || R6 = [ I0 ++ ]; + A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ P2 ++ ] || R3 = [ I1 ++ ]; + A1 += R4.H * R6.H, A0 -= R4.H * R6.L || [ P2 ++ ] = R5 || R7 = [ I1 ++ ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x12245618; + CHECKREG r1, 0x23256719; + CHECKREG r2, 0x00F00100; + CHECKREG r3, 0x00C00103; + CHECKREG r4, 0x000B0001; + CHECKREG r5, 0x67291214; + CHECKREG r6, 0x863ABC70; + CHECKREG r7, 0xB4EF6A10; + + imm32 r0, 0x15245648; + imm32 r1, 0x25256749; + imm32 r2, 0x3526784a; + imm32 r3, 0x45278942; + imm32 r4, 0x55389143; + imm32 r5, 0x65391244; + imm32 r6, 0xa5334547; + imm32 r7, 0xc5334547; + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = [ P1 ++ ] || R0 = [ I1 -- ]; + A1 += R2.H * R3.H, A0 += R2.L * R3.H || NOP || R4 = [ I0 ++ ]; + A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = [ P2 -- ] || R5 = [ I0 -- ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x00A00105; + CHECKREG r1, 0x25256749; + CHECKREG r2, 0x000C0002; + CHECKREG r3, 0x00D00102; + CHECKREG r4, 0x000D0003; + CHECKREG r5, 0x000E0004; + CHECKREG r6, 0xCBDCD104; + CHECKREG r7, 0x0001DAE8; + + imm32 r1, 0x02450789; + imm32 r2, 0x0356089a; + imm32 r3, 0x04670912; + imm32 r4, 0x05780123; + imm32 r5, 0x06890234; + imm32 r6, 0x07230567; + imm32 r7, 0x00230567; + R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R1 = [ I1 ++ ] || R0 = [ I0 -- ]; + R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = [ P1 ] || R3 = [ I0 -- ]; + R5 = R4 +|+ R2, R0 = R4 -|- R2 (CO) || NOP || R4 = [ I0 ++ ]; + CHECKREG r0, 0xFA99FFDD; + CHECKREG r1, 0x0B8A0E79; + CHECKREG r2, 0x00610336; + CHECKREG r3, 0x000C0002; + CHECKREG r4, 0x000B0001; + CHECKREG r5, 0x009F0105; + CHECKREG r6, 0x000D0003; + CHECKREG r7, 0x00230567; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + .dd 0x000f0005 + .dd 0x00100006 + .dd 0x00200007 + .dd 0x00300008 + .dd 0x00400009 + .dd 0x0050000a + .dd 0x0060000b + .dd 0x0070000c + .dd 0x0080000d + .dd 0x0090000e + .dd 0x0100000f + .dd 0x02000010 + .dd 0x03000011 + .dd 0x04000012 + .dd 0x05000013 + .dd 0x06000014 + .dd 0x001a0000 + .dd 0x001b0001 + .dd 0x001c0002 + .dd 0x001d0003 + .dd 0x00010004 + .dd 0x00010005 + .dd 0x02100006 + .dd 0x02200007 + .dd 0x02300008 + .dd 0x02200009 + .dd 0x0250000a + .dd 0x0260000b + .dd 0x0270000c + .dd 0x0280000d + .dd 0x0290000e + .dd 0x2100000f + .dd 0x22000010 + .dd 0x22000011 + .dd 0x24000012 + .dd 0x25000013 + .dd 0x26000014 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 + .dd 0x00b00104 + .dd 0x00a00105 + .dd 0x00900106 + .dd 0x00800107 + .dd 0x00100108 + .dd 0x00200109 + .dd 0x0030010a + .dd 0x0040010b + .dd 0x0050011c + .dd 0x0060010d + .dd 0x0070010e + .dd 0x0080010f + .dd 0x00900110 + .dd 0x01000111 + .dd 0x02000112 + .dd 0x03000113 + .dd 0x04000114 + .dd 0x05000115 + .dd 0x03f00100 + .dd 0x03e00101 + .dd 0x03d00102 + .dd 0x03c00103 + .dd 0x03b00104 + .dd 0x03a00105 + .dd 0x03900106 + .dd 0x03800107 + .dd 0x03100108 + .dd 0x03200109 + .dd 0x0330010a + .dd 0x0330010b + .dd 0x0350011c + .dd 0x0360010d + .dd 0x0370010e + .dd 0x0380010f + .dd 0x03900110 + .dd 0x31000111 + .dd 0x32000112 + .dd 0x33000113 + .dd 0x34000114 diff --git a/sim/testsuite/bfin/c_multi_issue_dsp_ldst_1.s b/sim/testsuite/bfin/c_multi_issue_dsp_ldst_1.s new file mode 100644 index 0000000..8dc8373 --- /dev/null +++ b/sim/testsuite/bfin/c_multi_issue_dsp_ldst_1.s @@ -0,0 +1,198 @@ +//Original:/testcases/core/c_multi_issue_dsp_ldst_1/c_multi_issue_dsp_ldst_1.dsp +// Spec Reference: dsp32mac and 2 load/store +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + + imm32 r0, 0x00000000; + A0 = 0; + A1 = 0; + ASTAT = r0; + + loadsym I0, DATA0; + loadsym I1, DATA1; + + loadsym P1, DATA0; + loadsym P2, DATA1; + +// test the default (signed fraction : left ) + imm32 r0, 0x12345678; + imm32 r1, 0x33456789; + imm32 r2, 0x5556789a; + imm32 r3, 0x75678912; + imm32 r4, 0x86789123; + imm32 r5, 0xa7891234; + imm32 r6, 0xc1234567; + imm32 r7, 0xf1234567; + A1 = R0.L * R1.L, A0 = R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; + A1 += R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ I0 ++ ] || R3 = [ I1 ++ ]; + A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = [ P1 ++ ] || [ I1 ++ ] = R5; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x000A0000; + CHECKREG r1, 0x00F00100; + CHECKREG r2, 0x000B0001; + CHECKREG r3, 0x00E00101; + CHECKREG r4, 0x000A0000; + CHECKREG r5, 0xA7891234; + CHECKREG r6, 0x92793486; + CHECKREG r7, 0xDD2F9BAA; + + imm32 r0, 0x12245618; + imm32 r1, 0x23256719; + imm32 r2, 0x3426781a; + imm32 r3, 0x45278912; + imm32 r4, 0x56289113; + imm32 r5, 0x67291214; + imm32 r6, 0xa1234517; + imm32 r7, 0xc1234517; + A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = [ P1 ++ ] || [ I0 ++ ] = R6; + A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ P2 ++ ] || [ I1 ++ ] = R3; + A1 += R4.H * R6.H, A0 -= R4.H * R6.L || [ P2 ++ ] = R5 || R7 = [ I1 ++ ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x12245618; + CHECKREG r1, 0x23256719; + CHECKREG r2, 0x00F00100; + CHECKREG r3, 0x45278912; + CHECKREG r4, 0x000B0001; + CHECKREG r5, 0x67291214; + CHECKREG r6, 0x8634CCA2; + CHECKREG r7, 0xB4E7420A; + + imm32 r0, 0x15245648; + imm32 r1, 0x25256749; + imm32 r2, 0x3526784a; + imm32 r3, 0x45278942; + imm32 r4, 0x55389143; + imm32 r5, 0x65391244; + imm32 r6, 0xa5334547; + imm32 r7, 0xc5334547; + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = [ P1 ++ ] || [ I1 -- ] = R3; + A1 += R2.H * R3.H, A0 += R2.L * R3.H || NOP || [ I0 ++ ] = R2; + A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = [ P2 -- ] || R6 = [ I0 -- ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x15245648; + CHECKREG r1, 0x25256749; + CHECKREG r2, 0xA1234517; + CHECKREG r3, 0xA7891234; + CHECKREG r4, 0x55389143; + CHECKREG r5, 0x65391244; + CHECKREG r6, 0xFD508A74; + CHECKREG r7, 0x0C2925C0; + + imm32 r1, 0x02450789; + imm32 r2, 0x0356089a; + imm32 r3, 0x04670912; + imm32 r4, 0x05780123; + imm32 r5, 0x06890234; + imm32 r6, 0x07230567; + imm32 r7, 0x00230567; + R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R0 = [ I1 ++ ] || [ I0 -- ] = R2; + R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = [ P1 ] || [ I0 -- ] = R3; + R5 = R4 +|+ R2, R0 = R4 -|- R2 (CO) || NOP || [ I0 ++ ] = R5; + CHECKREG r0, 0xFA99FFDD; + CHECKREG r1, 0x0B8A0E79; + CHECKREG r2, 0x0AA32DD7; + CHECKREG r3, 0x04670912; + CHECKREG r4, 0x0A802870; + CHECKREG r5, 0x15235647; + CHECKREG r6, 0x0356089A; + CHECKREG r7, 0x00230567; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + .dd 0x000f0005 + .dd 0x00100006 + .dd 0x00200007 + .dd 0x00300008 + .dd 0x00400009 + .dd 0x0050000a + .dd 0x0060000b + .dd 0x0070000c + .dd 0x0080000d + .dd 0x0090000e + .dd 0x0100000f + .dd 0x02000010 + .dd 0x03000011 + .dd 0x04000012 + .dd 0x05000013 + .dd 0x06000014 + .dd 0x001a0000 + .dd 0x001b0001 + .dd 0x001c0002 + .dd 0x001d0003 + .dd 0x00010004 + .dd 0x00010005 + .dd 0x02100006 + .dd 0x02200007 + .dd 0x02300008 + .dd 0x02200009 + .dd 0x0250000a + .dd 0x0260000b + .dd 0x0270000c + .dd 0x0280000d + .dd 0x0290000e + .dd 0x2100000f + .dd 0x22000010 + .dd 0x22000011 + .dd 0x24000012 + .dd 0x25000013 + .dd 0x26000014 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 + .dd 0x00b00104 + .dd 0x00a00105 + .dd 0x00900106 + .dd 0x00800107 + .dd 0x00100108 + .dd 0x00200109 + .dd 0x0030010a + .dd 0x0040010b + .dd 0x0050011c + .dd 0x0060010d + .dd 0x0070010e + .dd 0x0080010f + .dd 0x00900110 + .dd 0x01000111 + .dd 0x02000112 + .dd 0x03000113 + .dd 0x04000114 + .dd 0x05000115 + .dd 0x03f00100 + .dd 0x03e00101 + .dd 0x03d00102 + .dd 0x03c00103 + .dd 0x03b00104 + .dd 0x03a00105 + .dd 0x03900106 + .dd 0x03800107 + .dd 0x03100108 + .dd 0x03200109 + .dd 0x0330010a + .dd 0x0330010b + .dd 0x0350011c + .dd 0x0360010d + .dd 0x0370010e + .dd 0x0380010f + .dd 0x03900110 + .dd 0x31000111 + .dd 0x32000112 + .dd 0x33000113 + .dd 0x34000114 diff --git a/sim/testsuite/bfin/c_multi_issue_dsp_ldst_2.s b/sim/testsuite/bfin/c_multi_issue_dsp_ldst_2.s new file mode 100644 index 0000000..16fd3e5 --- /dev/null +++ b/sim/testsuite/bfin/c_multi_issue_dsp_ldst_2.s @@ -0,0 +1,198 @@ +//Original:/testcases/core/c_multi_issue_dsp_ldst_2/c_multi_issue_dsp_ldst_2.dsp +// Spec Reference: dsp32mac and 2 load/store +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + INIT_R_REGS 0; + + imm32 r0, 0x00000000; + A0 = 0; + A1 = 0; + ASTAT = r0; + + loadsym I0, DATA0; + loadsym I1, DATA1; + + loadsym P1, DATA0; + loadsym P2, DATA1; + +// test the default (signed fraction : left ) + imm32 r0, 0x12345678; + imm32 r1, 0x33456789; + imm32 r2, 0x5556789a; + imm32 r3, 0x75678912; + imm32 r4, 0x86789123; + imm32 r5, 0xa7891234; + imm32 r6, 0xc1234567; + imm32 r7, 0xf1234567; + A1 = R0.L * R1.L, A0 = R0.L * R1.L || R2 = B [ P1 ++ ] (X) || R3 = [ I1 ++ ]; + A1 += R2.L * R3.L, A0 += R2.L * R3.H || R0 = B [ P1 ++ ] (X) || R1 = [ I1 ++ ]; + A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = B [ P2 ++ ] (X) || [ I1 ++ ] = R5; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00E00101; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00F00100; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0xA7891234; + CHECKREG r6, 0x23DB649A; + CHECKREG r7, 0x4D3DD202; + + imm32 r0, 0x12245618; + imm32 r1, 0x23256719; + imm32 r2, 0x3426781a; + imm32 r3, 0x45278912; + imm32 r4, 0x56289113; + imm32 r5, 0x67291214; + imm32 r6, 0xa1234517; + imm32 r7, 0xc1234517; + A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = B [ P1 ++ ] (X) || [ I0 ++ ] = R6; + A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = B [ P2 ++ ] (X) || [ I1 ++ ] = R3; + A1 += R4.H * R6.H, A0 -= R4.H * R6.L || R5 = B [ P2 ++ ] (X) || R7 = [ I1 ++ ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x12245618; + CHECKREG r1, 0x23256719; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x45278912; + CHECKREG r4, 0x0000000A; + CHECKREG r5, 0xFFFFFFF0; + CHECKREG r6, 0x863ABC9C; + CHECKREG r7, 0xB4EF6908; + + imm32 r0, 0x15245648; + imm32 r1, 0x25256749; + imm32 r2, 0x3526784a; + imm32 r3, 0x45278942; + imm32 r4, 0x55389143; + imm32 r5, 0x65391244; + imm32 r6, 0xa5334547; + imm32 r7, 0xc5334547; + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = B [ P1 ++ ] (X) || [ I1 -- ] = R3; + A1 += R2.H * R3.H, A0 += R2.L * R3.H || R0 = B [ P2 -- ] (X) || [ I0 ++ ] = R2; + A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = B [ P2 ++ ] (X) || R1 = [ I0 -- ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x000C0002; + CHECKREG r2, 0xFFFFFFA1; + CHECKREG r3, 0xFFFFFFF0; + CHECKREG r4, 0x55389143; + CHECKREG r5, 0x65391244; + CHECKREG r6, 0xD7CFB47A; + CHECKREG r7, 0x0C2925C0; + + imm32 r1, 0x02450789; + imm32 r2, 0x0356089a; + imm32 r3, 0x04670912; + imm32 r4, 0x05780123; + imm32 r5, 0x06890234; + imm32 r6, 0x07230567; + imm32 r7, 0x00230567; + R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R0 = B [ P1 ++ ] (X) || [ I0 -- ] = R2; + R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = B [ P1 ] (X) || [ I0 -- ] = R3; + R5 = R4 +|+ R2, R0 = R4 -|- R2 || R3 = B [ P2 ++ ] (X) || R7 = [ I1 ++ ]; + CHECKREG r0, 0xFFDDFA99; + CHECKREG r1, 0x0B8A0E79; + CHECKREG r2, 0x001102B3; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0xFFEEFD4C; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0x00000008; + CHECKREG r7, 0x00B00104; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + .dd 0x000f0005 + .dd 0x00100006 + .dd 0x00200007 + .dd 0x00300008 + .dd 0x00400009 + .dd 0x0050000a + .dd 0x0060000b + .dd 0x0070000c + .dd 0x0080000d + .dd 0x0090000e + .dd 0x0100000f + .dd 0x02000010 + .dd 0x03000011 + .dd 0x04000012 + .dd 0x05000013 + .dd 0x06000014 + .dd 0x001a0000 + .dd 0x001b0001 + .dd 0x001c0002 + .dd 0x001d0003 + .dd 0x00010004 + .dd 0x00010005 + .dd 0x02100006 + .dd 0x02200007 + .dd 0x02300008 + .dd 0x02200009 + .dd 0x0250000a + .dd 0x0260000b + .dd 0x0270000c + .dd 0x0280000d + .dd 0x0290000e + .dd 0x2100000f + .dd 0x22000010 + .dd 0x22000011 + .dd 0x24000012 + .dd 0x25000013 + .dd 0x26000014 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 + .dd 0x00b00104 + .dd 0x00a00105 + .dd 0x00900106 + .dd 0x00800107 + .dd 0x00100108 + .dd 0x00200109 + .dd 0x0030010a + .dd 0x0040010b + .dd 0x0050011c + .dd 0x0060010d + .dd 0x0070010e + .dd 0x0080010f + .dd 0x00900110 + .dd 0x01000111 + .dd 0x02000112 + .dd 0x03000113 + .dd 0x04000114 + .dd 0x05000115 + .dd 0x03f00100 + .dd 0x03e00101 + .dd 0x03d00102 + .dd 0x03c00103 + .dd 0x03b00104 + .dd 0x03a00105 + .dd 0x03900106 + .dd 0x03800107 + .dd 0x03100108 + .dd 0x03200109 + .dd 0x0330010a + .dd 0x0330010b + .dd 0x0350011c + .dd 0x0360010d + .dd 0x0370010e + .dd 0x0380010f + .dd 0x03900110 + .dd 0x31000111 + .dd 0x32000112 + .dd 0x33000113 + .dd 0x34000114 diff --git a/sim/testsuite/bfin/c_progctrl_call_pcpr.s b/sim/testsuite/bfin/c_progctrl_call_pcpr.s new file mode 100644 index 0000000..4cc5b29 --- /dev/null +++ b/sim/testsuite/bfin/c_progctrl_call_pcpr.s @@ -0,0 +1,63 @@ +//Original:/testcases/core/c_progctrl_call_pcpr/c_progctrl_call_pcpr.dsp +// Spec Reference: progctrl call (pc+pr) +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = r0; + + FP = SP; + + P2 = 0x0006; + +JMP: + CALL ( PC + P2 ); + JUMP.S JMP; + +STOP: + JUMP.S END; + +LAB1: + P2 = 0x000e; + R1 = 0x1111 (X); + RTS; + +LAB2: + P2 = 0x0016; + R2 = 0x2222 (X); + RTS; + +LAB3: + P2 = 0x001e; + R3 = 0x3333 (X); + RTS; + +LAB4: + P2 = 0x0026; + R4 = 0x4444 (X); + RTS; + +LAB5: + P2 = 0x0004; + R5 = 0x5555 (X); + RTS; + +END: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00001111; + CHECKREG r2, 0x00002222; + CHECKREG r3, 0x00003333; + CHECKREG r4, 0x00004444; + CHECKREG r5, 0x00005555; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass + + .data +DATA: + .space (0x0100); diff --git a/sim/testsuite/bfin/c_progctrl_call_pr.s b/sim/testsuite/bfin/c_progctrl_call_pr.s new file mode 100644 index 0000000..be8278e --- /dev/null +++ b/sim/testsuite/bfin/c_progctrl_call_pr.s @@ -0,0 +1,32 @@ +//Original:/testcases/core/c_progctrl_call_pr/c_progctrl_call_pr.dsp +// Spec Reference: progctrl call (pr) +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = r0; + + FP = SP; + + loadsym P1, SUBR; + CALL ( P1 ); + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00001111; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass + +SUBR: // should jump here + R1.L = 0x1111; + RTS; + R2.L = 0x2222; // should not go here + RTS; diff --git a/sim/testsuite/bfin/c_progctrl_clisti_interr.S b/sim/testsuite/bfin/c_progctrl_clisti_interr.S new file mode 100644 index 0000000..78d6e67 --- /dev/null +++ b/sim/testsuite/bfin/c_progctrl_clisti_interr.S @@ -0,0 +1,330 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_clisti_interr/c_progctrl_clisti_interr.dsp +// Spec Reference: CLI STI interrupt on HW TIMER +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + //CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + BOOT : + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + + START : + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +CLI R1; // stop interrupt +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000050, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000000, p0, r0); +CSYNC; + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000050); + +// RD_MMR(TCOUNT, p0, r3); +// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +RD_MMR(TPERIOD, p0, r4); +CHECKREG(r4, 0x00000050); + +// RD_MMR(TCNTL, p0, r5); +// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000015, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000002, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) +CSYNC; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label4; + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label5: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label6; + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +label4: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +JUMP.S label5; + R5.L = 0x2222; // Will be killed + R5.H = 0x2222; // Will be killed +NOP; +NOP; +NOP; +NOP; +label6: R3.H = 0x7999; + R3.L = 0x7aaa; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + // With auto reload + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000015); + +// RD_MMR(TCNTL , p0, r3); +// CHECKREG(r3, 0x0000000F); +NOP; +CHECKREG(r7, 0x00000000); // no interrupt being serviced +NOP; +STI R1; + +NOP; NOP; NOP; +NOP; NOP; NOP; +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; NOP; NOP; + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_PROGRAM_STACK,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/bfin/c_progctrl_csync_mmr.S b/sim/testsuite/bfin/c_progctrl_csync_mmr.S new file mode 100644 index 0000000..0aeccde --- /dev/null +++ b/sim/testsuite/bfin/c_progctrl_csync_mmr.S @@ -0,0 +1,280 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_csync_mmr/c_progctrl_csync_mmr.dsp +// Spec Reference: csync mmr timer +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +INIT_R_REGS(-1); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // TCNTL: 4 bits, rw=1 = 0xFFE03000 +LD32(p0, 0xFFE03000); +LD32(r0, 0x00000001); + [ P0 ] = R0; +LD32(r0, 0x0000000D); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R1 = [ P0 ]; + + // TPERIOD: 32 bits, rw=1 = 0xFFE03004 +LD32(p0, 0xFFE03004); +LD32(r0, 0x11112222); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R2 = [ P0 ]; + + // TSCALE: 8 bits, rw=1 = 0xFFE03008 +LD32(p0, 0xFFE03008); +LD32(r0, 0x00000050); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R3 = [ P0 ]; + + + // TCOUNT: 32 bits, rw=1 = 0xFFE0300C +LD32(p0, 0xFFE0300C); +LD32(r0, 0x00000100); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R4 = [ P0 ]; + + +CHECKREG(r1, 0x0000000D); +CHECKREG(r2, 0x11112222); +CHECKREG(r3, 0x00000050); +CHECKREG(r4, 0x00000100); + +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_progctrl_except_rtx.S b/sim/testsuite/bfin/c_progctrl_except_rtx.S new file mode 100644 index 0000000..9cacc28 --- /dev/null +++ b/sim/testsuite/bfin/c_progctrl_except_rtx.S @@ -0,0 +1,96 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_except_rtx/c_progctrl_except_rtx.dsp +// Spec Reference: c_progctrl_except_rtx +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); +// load address of exception handler + +P0 = 0x200C (Z); // 0xFFE0200C EVT3 EXCEPTION +P0.H = 0xFFE0; +R0 = exception_handler (Z); // wr address of exception handler to MMR EVT3 +R0.H = exception_handler; +[ P0 ] = R0; + +// Jump to User mode and enable exceptions + +R0 = MidUserCode (Z); +R0.H = MidUserCode; +RETI = R0; +RTI; // cause it to go to Midusercode, .dd cause exception + +BeginUserCode: +P1 = 1; +P2 = 2; +P3 = 3; +P4 = 4; + +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000001); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000003); +CHECKREG(r5, 0x00000000); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x00000000); +CHECKREG(p1, 0x00000001); +CHECKREG(p2, 0x00000002); +CHECKREG(p3, 0x00000003); +CHECKREG(p4, 0x00000004); + +dbg_pass; +//jump 2; +//jump -2; +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF + +//dbg_pass; + +MidUserCode: +.dd 0xFFFFFFFF +R0 = 0; +R1 = 1; +R2 = 2; +R3 = 3; +CC = R0; +IF !CC JUMP BeginUserCode; + +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF + + +exception_handler: +R4 = RETX; // error handler: RETX has the address of the same Illegal instr +R1 += 1; +R2 += 2; +R3 += 3; +R1 += 1; +R4 += 4; // we have to add 4 to point to next instr after return +RETX = R4; + +RTX; // return from exception + +.section MEM_DATA_ADDR_1,"aw" +.dd 0xDEADBEEF +.dd 0xBAD00BAD diff --git a/sim/testsuite/bfin/c_progctrl_excpt.S b/sim/testsuite/bfin/c_progctrl_excpt.S new file mode 100644 index 0000000..625a5c0 --- /dev/null +++ b/sim/testsuite/bfin/c_progctrl_excpt.S @@ -0,0 +1,261 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_excpt/c_progctrl_excpt.dsp +// Spec Reference: progctrl excpt uimm4 +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +EXCPT 2; // RETX RTX + +CHECKREG(r0, 0x0000000A); +CHECKREG(r1, 0x0000000B); +CHECKREG(r2, 0x0000000C); +CHECKREG(r3, 0x0000000D); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x00000000); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + R0 = 10; + R1 = 11; + R2 = 12; + R3 = 13; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_progctrl_jump_pcpr.s b/sim/testsuite/bfin/c_progctrl_jump_pcpr.s new file mode 100644 index 0000000..727025c --- /dev/null +++ b/sim/testsuite/bfin/c_progctrl_jump_pcpr.s @@ -0,0 +1,58 @@ +//Original:/testcases/core/c_progctrl_jump_pcpr/c_progctrl_jump_pcpr.dsp +// Spec Reference: progctrl jump pc+pr +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + + P2 = 0x0004; + +JMP: + JUMP ( PC + P2 ); +// jump JMP; + +STOP: +JUMP.S END; + +LAB1: + P2 = 0x000c; + R1 = 0x1111 (X); +JUMP.S JMP; + +LAB2: + P2 = 0x0014; + R2 = 0x2222 (X); +JUMP.S JMP; + +LAB3: + P2 = 0x001c; + R3 = 0x3333 (X); +JUMP.S JMP; + +LAB4: + P2 = 0x0024; + R4 = 0x4444 (X); +JUMP.S JMP; + +LAB5: + P2 = 0x0002; + R5 = 0x5555 (X); +JUMP.S JMP; + +END: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00002222; +CHECKREG r3, 0x00003333; +CHECKREG r4, 0x00004444; +CHECKREG r5, 0x00005555; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/c_progctrl_jump_pr.s b/sim/testsuite/bfin/c_progctrl_jump_pr.s new file mode 100644 index 0000000..8b77c31 --- /dev/null +++ b/sim/testsuite/bfin/c_progctrl_jump_pr.s @@ -0,0 +1,56 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_jump_pr/c_progctrl_jump_pr.dsp +// Spec Reference: progctrl jump(p) +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = r0; + + loadsym p1, LAB1; + loadsym p2, LAB2; + loadsym fp, LAB3; + loadsym p4, LAB4; + loadsym p5, LAB5; + + JUMP ( P1 ); + +STOP: + JUMP.S END; + +LAB1: + R1 = 0x1111 (X); + JUMP ( P5 ); + R6 = 0x6666 (X); + +LAB2: + R2 = 0x2222 (X); + JUMP.S STOP; + +LAB3: + R3 = 0x3333 (X); + JUMP ( P2 ); + R7 = 0x7777 (X); + +LAB4: + R4 = 0x4444 (X); + JUMP ( FP ); + +LAB5: + R5 = 0x5555 (X); + JUMP ( P4 ); + +END: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00001111; + CHECKREG r2, 0x00002222; + CHECKREG r3, 0x00003333; + CHECKREG r4, 0x00004444; + CHECKREG r5, 0x00005555; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass diff --git a/sim/testsuite/bfin/c_progctrl_nop.s b/sim/testsuite/bfin/c_progctrl_nop.s new file mode 100644 index 0000000..77f744b --- /dev/null +++ b/sim/testsuite/bfin/c_progctrl_nop.s @@ -0,0 +1,55 @@ +//Original:/testcases/core/c_progctrl_nop/c_progctrl_nop.dsp +// Spec Reference: progctrl nop +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + + +I0 = 0x1122 (Z); +NOP; +R0 = I0; + +I1 = 0x3344 (Z); +NOP; +R1 = I1; + +I2 = 0x5566 (Z); +NOP; +R2 = I2; + +I3 = 0x7788 (Z); +NOP; +R3 = I3; + + +P2 = 0x99aa (Z); +NOP; NOP; +R4 = P2; + +P3 = 0xbbcc (Z); +NOP; NOP; +R5 = P3; + +P4 = 0xddee (Z); +NOP; NOP; +R6 = P4; + +P5 = 0x1234 (Z); +NOP; NOP; +R7 = P5; + +CHECKREG r0, 0x00001122; +CHECKREG r1, 0x00003344; +CHECKREG r2, 0x00005566; +CHECKREG r3, 0x00007788; +CHECKREG r4, 0x000099AA; +CHECKREG r5, 0x0000BBCC; +CHECKREG r6, 0x0000DDEE; +CHECKREG r7, 0x00001234; + + +pass diff --git a/sim/testsuite/bfin/c_progctrl_raise_rt_i_n.S b/sim/testsuite/bfin/c_progctrl_raise_rt_i_n.S new file mode 100644 index 0000000..9444f5d --- /dev/null +++ b/sim/testsuite/bfin/c_progctrl_raise_rt_i_n.S @@ -0,0 +1,285 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_raise_rt_i_n/c_progctrl_raise_rt_i_n.dsp +// Spec Reference: progctrl raise rti rtn +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +CHECK_INIT(p5, 0xe0000000); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +RAISE 2; // RTN +RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI +RAISE 15; // RTI + +CHECKREG(r0, 0x0000000B); +CHECKREG(r1, 0x0000000C); +CHECKREG(r2, 0x0000000D); +CHECKREG(r3, 0x0000000E); +CHECKREG(r4, 0x00000007); +CHECKREG(r5, 0x00000008); +CHECKREG(r6, 0x00000009); +CHECKREG(r7, 0x0000000A); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +CHECKREG(r0, 0x00000002); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000005); +CHECKREG(r3, 0x00000006); +CHECKREG(r4, 0x00000007); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_progctrl_rts.s b/sim/testsuite/bfin/c_progctrl_rts.s new file mode 100644 index 0000000..3aa3bed --- /dev/null +++ b/sim/testsuite/bfin/c_progctrl_rts.s @@ -0,0 +1,36 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_rts/c_progctrl_rts.dsp +// Spec Reference: progctrl rts +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = r0; + + loadsym R2, SUBR; + RETS = R2; + RTS; + +STOP: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r4, 0x00004444; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass + +SUBR: // should jump here + loadsym R3, STOP; + RETS = R3; + R4.L = 0x4444; + RTS; + RETS = R3; + R5.L = 0x5555; // should not go here + RTS; + + fail diff --git a/sim/testsuite/bfin/c_ptr2op_pr_neg_pr.s b/sim/testsuite/bfin/c_ptr2op_pr_neg_pr.s new file mode 100644 index 0000000..2d27849 --- /dev/null +++ b/sim/testsuite/bfin/c_ptr2op_pr_neg_pr.s @@ -0,0 +1,163 @@ +//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_neg_pr/c_ptr2op_pr_neg_pr.dsp +// Spec Reference: ptr2op preg -= preg +# mach: bfin + +.include "testutils.inc" + start + +// check p-reg to p-reg move + imm32 p1, 0xf0021003; + imm32 p2, 0x2e041005; + imm32 p3, 0x20d61007; + imm32 p4, 0x200a1009; + imm32 p5, 0x200a300b; + imm32 sp, 0x200c180d; + imm32 fp, 0x200e109f; + P1 -= P1; + P2 -= P1; + P3 -= P1; + P4 -= P1; + P5 -= P1; + SP -= P1; + FP -= P1; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x2E041005; + CHECKREG p3, 0x20D61007; + CHECKREG p4, 0x200A1009; + CHECKREG p5, 0x200A300B; + CHECKREG sp, 0x200C180D; + CHECKREG fp, 0x200E109F; + + imm32 p1, 0x50021003; + imm32 p2, 0x26041005; + imm32 p3, 0x20761007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a900b; + imm32 sp, 0x200c1a0d; + imm32 fp, 0x200e10bf; + P1 -= P2; + P2 -= P2; + P3 -= P2; + P4 -= P2; + P5 -= P2; + SP -= P2; + FP -= P2; + CHECKREG p1, 0x29FDFFFE; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x20761007; + CHECKREG p4, 0x20081009; + CHECKREG p5, 0x200A900B; + CHECKREG sp, 0x200C1A0D; + CHECKREG fp, 0x200E10BF; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p3, 0x20061007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 sp, 0x200c100d; + imm32 fp, 0x200e100f; + P1 -= P3; + P2 -= P3; + P3 -= P3; + P4 -= P3; + P5 -= P3; + SP -= P3; + FP -= P3; + CHECKREG p1, 0xFFFBFFFC; + CHECKREG p2, 0xFFFDFFFE; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x20081009; + CHECKREG p5, 0x200A100B; + CHECKREG sp, 0x200C100D; + CHECKREG fp, 0x200E100F; + + imm32 p1, 0xa0021003; + imm32 p2, 0x2c041005; + imm32 p3, 0x20b61007; + imm32 p4, 0x200d1009; + imm32 p5, 0x200ae00b; + imm32 sp, 0x200c110d; + imm32 fp, 0x200e104f; + P1 -= P4; + P2 -= P4; + P3 -= P4; + P4 -= P4; + P5 -= P4; + SP -= P4; + FP -= P4; + CHECKREG p1, 0x7FF4FFFA; + CHECKREG p2, 0x0BF6FFFC; + CHECKREG p3, 0x00A8FFFE; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0x200AE00B; + CHECKREG sp, 0x200C110D; + CHECKREG fp, 0x200E104F; + + imm32 p1, 0x10021003; + imm32 p2, 0x22041005; + imm32 p3, 0x20361007; + imm32 p4, 0x20041009; + imm32 p5, 0x200aa00b; + imm32 sp, 0x200c1b0d; + imm32 fp, 0x200e10cf; + P1 -= P5; + P2 -= P5; + P3 -= P5; + P4 -= P5; + P5 -= P5; + SP -= P5; + FP -= P5; + CHECKREG p1, 0xEFF76FF8; + CHECKREG p2, 0x01F96FFA; + CHECKREG p3, 0x002B6FFC; + CHECKREG p4, 0xFFF96FFE; + CHECKREG p5, 0x00000000; + CHECKREG sp, 0x200C1B0D; + CHECKREG fp, 0x200E10CF; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p3, 0x20061007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 sp, 0x200c100d; + imm32 fp, 0x200e100f; + P1 -= SP; + P2 -= SP; + P3 -= SP; + P4 -= SP; + P5 -= SP; + SP -= SP; + FP -= SP; + CHECKREG p1, 0xFFF5FFF6; + CHECKREG p2, 0xFFF7FFF8; + CHECKREG p3, 0xFFF9FFFA; + CHECKREG p4, 0xFFFBFFFC; + CHECKREG p5, 0xFFFDFFFE; + CHECKREG sp, 0x00000000; + CHECKREG fp, 0x200E100F; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p3, 0x20061007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 sp, 0x200c100d; + imm32 fp, 0x200e100f; + P1 -= FP; + P2 -= FP; + P3 -= FP; + P4 -= FP; + P5 -= FP; + SP -= FP; + FP -= FP; + CHECKREG p1, 0xFFF3FFF4; + CHECKREG p2, 0xFFF5FFF6; + CHECKREG p3, 0xFFF7FFF8; + CHECKREG p4, 0xFFF9FFFA; + CHECKREG p5, 0xFFFBFFFC; + CHECKREG sp, 0xFFFDFFFE; + CHECKREG fp, 0x00000000; + + pass diff --git a/sim/testsuite/bfin/c_ptr2op_pr_sft_2_1.s b/sim/testsuite/bfin/c_ptr2op_pr_sft_2_1.s new file mode 100644 index 0000000..dabd216 --- /dev/null +++ b/sim/testsuite/bfin/c_ptr2op_pr_sft_2_1.s @@ -0,0 +1,162 @@ +//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_sft_2_1/c_ptr2op_pr_sft_2_1.dsp +// Spec Reference: ptr2op preg = preg << 2 (>>2, >> 1) +# mach: bfin + +.include "testutils.inc" + start +// check p-reg to p-reg move + imm32 p1, 0xf0921203; + imm32 p2, 0xbe041305; + imm32 p3, 0xd0d61407; + imm32 p4, 0xa00a1089; + imm32 p5, 0x400a300b; + imm32 sp, 0xe07c180d; + imm32 fp, 0x206e109f; + P1 = P1 << 2; + P2 = P1 >> 2; + P3 = P1 << 2; + P4 = P1 >> 1; + P5 = P1 >> 2; + SP = P1 << 2; + FP = P1 >> 1; + CHECKREG p1, 0xC248480C; + CHECKREG p2, 0x30921203; + CHECKREG p3, 0x09212030; + CHECKREG p4, 0x61242406; + CHECKREG p5, 0x30921203; + CHECKREG sp, 0x09212030; + CHECKREG fp, 0x61242406; + + imm32 p1, 0x50021003; + imm32 p2, 0x26041005; + imm32 p3, 0x60761007; + imm32 p4, 0x20081009; + imm32 p5, 0xf00a900b; + imm32 sp, 0xb00c1a0d; + imm32 fp, 0x200e10bf; + P1 = P2; + P2 = P2; + P3 = P2; + P4 = P2; + P5 = P2; + SP = P2; + FP = P2; + CHECKREG p1, 0x26041005; + CHECKREG p2, 0x26041005; + CHECKREG p3, 0x26041005; + CHECKREG p4, 0x26041005; + CHECKREG p5, 0x26041005; + CHECKREG sp, 0x26041005; + CHECKREG fp, 0x26041005; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p3, 0x20061007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 sp, 0x200c100d; + imm32 fp, 0x200e100f; + P1 = P3 << 2; + P2 = P3 >> 1; + P3 = P3 >> 2; + P4 = P3 << 2; + P5 = P3 << 2; + SP = P3 >> 1; + FP = P3 << 2; + CHECKREG p1, 0x8018401C; + CHECKREG p2, 0x10030803; + CHECKREG p3, 0x08018401; + CHECKREG p4, 0x20061004; + CHECKREG p5, 0x20061004; + CHECKREG sp, 0x0400C200; + CHECKREG fp, 0x20061004; + + imm32 p1, 0xa0021003; + imm32 p2, 0x2c041005; + imm32 p3, 0x40b61007; + imm32 p4, 0x250d1009; + imm32 p5, 0x260ae00b; + imm32 sp, 0x700c110d; + imm32 fp, 0x900e104f; + P1 = P4 >> 1; + P2 = P4 << 2; + P3 = P4 << 2; + P4 = P4 >> 2; + P5 = P4 << 2; + SP = P4 >> 2; + FP = P4 << 2; + CHECKREG p1, 0x12868804; + CHECKREG p2, 0x94344024; + CHECKREG p3, 0x94344024; + CHECKREG p4, 0x09434402; + CHECKREG p5, 0x250D1008; + CHECKREG sp, 0x0250D100; + CHECKREG fp, 0x250D1008; + + imm32 p1, 0x10021003; + imm32 p2, 0x22041005; + imm32 p3, 0x20361007; + imm32 p4, 0x20041009; + imm32 p5, 0x200aa00b; + imm32 sp, 0x200c1b0d; + imm32 fp, 0x200e10cf; + P1 = P5 << 2; + P2 = P5 >> 2; + P3 = P5 << 2; + P4 = P5 << 2; + P5 = P5 >> 1; + SP = P5 >> 2; + FP = P5 << 2; + CHECKREG p1, 0x802A802C; + CHECKREG p2, 0x0802A802; + CHECKREG p3, 0x802A802C; + CHECKREG p4, 0x802A802C; + CHECKREG p5, 0x10055005; + CHECKREG sp, 0x04015401; + CHECKREG fp, 0x40154014; + + imm32 p1, 0x50021003; + imm32 p2, 0x62041005; + imm32 p3, 0x70e61007; + imm32 p4, 0x290f1009; + imm32 p5, 0x700ab00b; + imm32 sp, 0x2a0c1d0d; + imm32 fp, 0xb00e1e0f; + P1 = SP << 2; + P2 = SP << 2; + P3 = SP >> 2; + P4 = SP << 2; + P5 = SP >> 2; + SP = SP >> 1; + FP = SP >> 2; + CHECKREG p1, 0xA8307434; + CHECKREG p2, 0xA8307434; + CHECKREG p3, 0x0A830743; + CHECKREG p4, 0xA8307434; + CHECKREG p5, 0x0A830743; + CHECKREG sp, 0x15060E86; + CHECKREG fp, 0x054183A1; + + imm32 p1, 0x32002003; + imm32 p2, 0x24004005; + imm32 p3, 0x20506007; + imm32 p4, 0x20068009; + imm32 p5, 0x200ae00b; + imm32 sp, 0x200c1f0d; + imm32 fp, 0x200e10bf; + P1 = FP >> 2; + P2 = FP >> 1; + P3 = FP << 2; + P4 = FP >> 2; + P5 = FP << 2; + SP = FP >> 2; + FP = FP << 2; + CHECKREG p1, 0x0803842F; + CHECKREG p2, 0x1007085F; + CHECKREG p3, 0x803842FC; + CHECKREG p4, 0x0803842F; + CHECKREG p5, 0x803842FC; + CHECKREG sp, 0x0803842F; + CHECKREG fp, 0x803842FC; + + pass diff --git a/sim/testsuite/bfin/c_ptr2op_pr_shadd_1_2.s b/sim/testsuite/bfin/c_ptr2op_pr_shadd_1_2.s new file mode 100644 index 0000000..dc6e2e8 --- /dev/null +++ b/sim/testsuite/bfin/c_ptr2op_pr_shadd_1_2.s @@ -0,0 +1,167 @@ +//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_shadd_1_2/c_ptr2op_pr_shadd_1_2.dsp +// Spec Reference: ptr2op shadd preg, pregs, 1 (2) +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + +// check p-reg to p-reg move + + imm32 p1, 0xf0921203; + imm32 p2, 0xbe041305; + imm32 p3, 0xd0d61407; + imm32 p4, 0xa00a1089; + imm32 p5, 0x400a300b; + imm32 sp, 0xe07c180d; + imm32 fp, 0x206e109f; + P1 = ( P1 + P1 ) << 2; + P2 = ( P2 + P1 ) << 2; + P3 = ( P3 + P1 ) << 2; + P4 = ( P4 + P1 ) << 1; + P5 = ( P5 + P1 ) << 2; + SP = ( SP + P1 ) << 2; + FP = ( FP + P1 ) << 1; + CHECKREG p1, 0x84909018; + CHECKREG p2, 0x0A528C74; + CHECKREG p3, 0x559A907C; + CHECKREG p4, 0x49354142; + CHECKREG p5, 0x126B008C; + CHECKREG sp, 0x9432A094; + CHECKREG fp, 0x49FD416E; + + imm32 p1, 0x50021003; + imm32 p2, 0x26041005; + imm32 p3, 0x60761007; + imm32 p4, 0x20081009; + imm32 p5, 0xf00a900b; + imm32 sp, 0xb00c1a0d; + imm32 fp, 0x200e10bf; + P1 = ( P1 + P2 ) << 1; + P2 = ( P2 + P2 ) << 2; + P3 = ( P3 + P2 ) << 1; + P4 = ( P4 + P2 ) << 2; + P5 = ( P5 + P2 ) << 2; + SP = ( SP + P2 ) << 1; + FP = ( FP + P2 ) << 2; + CHECKREG p1, 0xEC0C4010; + CHECKREG p2, 0x30208028; + CHECKREG p3, 0x212D205E; + CHECKREG p4, 0x40A240C4; + CHECKREG p5, 0x80AC40CC; + CHECKREG sp, 0xC059346A; + CHECKREG fp, 0x40BA439C; + + imm32 p1, 0x30026003; + imm32 p2, 0x40051005; + imm32 p3, 0x20e65057; + imm32 p4, 0x2d081089; + imm32 p5, 0xf00ab07b; + imm32 sp, 0x200c1b0d; + imm32 fp, 0x200e100f; + P1 = ( P1 + P3 ) << 2; + P2 = ( P2 + P3 ) << 1; + P3 = ( P3 + P3 ) << 2; + P4 = ( P4 + P3 ) << 2; + P5 = ( P5 + P3 ) << 2; + SP = ( SP + P3 ) << 1; + FP = ( FP + P3 ) << 2; + CHECKREG p1, 0x43A2C168; + CHECKREG p2, 0xC1D6C0B8; + CHECKREG p3, 0x073282B8; + CHECKREG p4, 0xD0EA4D04; + CHECKREG p5, 0xDCF4CCCC; + CHECKREG sp, 0x4E7D3B8A; + CHECKREG fp, 0x9D024B1C; + + imm32 p1, 0xa0021003; + imm32 p2, 0x2c041005; + imm32 p3, 0x40b61007; + imm32 p4, 0x250d1009; + imm32 p5, 0x260ae00b; + imm32 sp, 0x700c110d; + imm32 fp, 0x900e104f; + P1 = ( P1 + P4 ) << 1; + P2 = ( P2 + P4 ) << 2; + P3 = ( P3 + P4 ) << 2; + P4 = ( P4 + P4 ) << 2; + P5 = ( P5 + P4 ) << 1; + SP = ( SP + P4 ) << 2; + FP = ( FP + P4 ) << 2; + CHECKREG p1, 0x8A1E4018; + CHECKREG p2, 0x44448038; + CHECKREG p3, 0x970C8040; + CHECKREG p4, 0x28688048; + CHECKREG p5, 0x9CE6C0A6; + CHECKREG sp, 0x61D24554; + CHECKREG fp, 0xE1DA425C; + + imm32 p1, 0xae021003; + imm32 p2, 0x22041705; + imm32 p3, 0x20361487; + imm32 p4, 0x90743009; + imm32 p5, 0xa60aa00b; + imm32 sp, 0xb00c1b0d; + imm32 fp, 0x200e10cf; + P1 = ( P1 + P5 ) << 2; + P2 = ( P2 + P5 ) << 2; + P3 = ( P3 + P5 ) << 2; + P4 = ( P4 + P5 ) << 2; + P5 = ( P5 + P5 ) << 1; + SP = ( SP + P5 ) << 2; + FP = ( FP + P5 ) << 2; + CHECKREG p1, 0x5032C038; + CHECKREG p2, 0x203ADC40; + CHECKREG p3, 0x1902D248; + CHECKREG p4, 0xD9FB4050; + CHECKREG p5, 0x982A802C; + CHECKREG sp, 0x20DA6CE4; + CHECKREG fp, 0xE0E243EC; + + imm32 p1, 0x50021003; + imm32 p2, 0x62041005; + imm32 p3, 0x70e61007; + imm32 p4, 0x290f1009; + imm32 p5, 0x700ab00b; + imm32 sp, 0x2a0c1d0d; + imm32 fp, 0xb00e1e0f; + P1 = ( P1 + SP ) << 2; + P2 = ( P2 + SP ) << 1; + P3 = ( P3 + SP ) << 2; + P4 = ( P4 + SP ) << 2; + P5 = ( P5 + SP ) << 2; + SP = ( SP + SP ) << 1; + FP = ( FP + SP ) << 2; + CHECKREG p1, 0xE838B440; + CHECKREG p2, 0x18205A24; + CHECKREG p3, 0x6BC8B450; + CHECKREG p4, 0x4C6CB458; + CHECKREG p5, 0x685B3460; + CHECKREG sp, 0xA8307434; + CHECKREG fp, 0x60FA490C; + + imm32 p1, 0x32002003; + imm32 p2, 0x24004005; + imm32 p3, 0xe0506007; + imm32 p4, 0xd0068009; + imm32 p5, 0x230ae00b; + imm32 sp, 0x205c1f0d; + imm32 fp, 0x200e10bf; + P1 = ( P1 + FP ) << 2; + P2 = ( P2 + FP ) << 1; + P3 = ( P3 + FP ) << 2; + P4 = ( P4 + FP ) << 2; + P5 = ( P5 + FP ) << 2; + SP = ( SP + FP ) << 2; + FP = ( FP + FP ) << 2; + CHECKREG p1, 0x4838C308; + CHECKREG p2, 0x881CA188; + CHECKREG p3, 0x0179C318; + CHECKREG p4, 0xC0524320; + CHECKREG p5, 0x0C63C328; + CHECKREG sp, 0x01A8BF30; + CHECKREG fp, 0x007085F8; + + pass diff --git a/sim/testsuite/bfin/c_pushpopmultiple_dp.s b/sim/testsuite/bfin/c_pushpopmultiple_dp.s new file mode 100644 index 0000000..5d7de57 --- /dev/null +++ b/sim/testsuite/bfin/c_pushpopmultiple_dp.s @@ -0,0 +1,213 @@ +//Original:/testcases/core/c_pushpopmultiple_dp/c_pushpopmultiple_dp.dsp +// Spec Reference: pushpopmultiple dreg preg single group +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + + imm32 r0, 0x00000000; + ASTAT = r0; + + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + P1 = 0xa1 (X); + P2 = 0xa2 (X); + P3 = 0xa3 (X); + P4 = 0xa4 (X); + P5 = 0xa5 (X); + [ -- SP ] = ( R7:0 ); + [ -- SP ] = ( P5:1 ); + + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + + P2 = 0xb2 (X); + P3 = 0xb3 (X); + P4 = 0xb4 (X); + P5 = 0xb5 (X); + [ -- SP ] = ( R7:1 ); + [ -- SP ] = ( P5:2 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + + P3 = 0xc3 (X); + P4 = 0xc4 (X); + P5 = 0xc5 (X); + [ -- SP ] = ( R7:2 ); + [ -- SP ] = ( P5:3 ); + + R3 = 0x34; + R4 = 0x35; + R5 = 0x36; + R6 = 0x37; + R7 = 0x38; + + P4 = 0xd4 (X); + P5 = 0xd5 (X); + [ -- SP ] = ( R7:3 ); + [ -- SP ] = ( P5:4 ); + + R4 = 0x45 (X); + R5 = 0x46 (X); + R6 = 0x47 (X); + R7 = 0x48 (X); + P5 = 0xe5 (X); + [ -- SP ] = ( R7:4 ); + [ -- SP ] = ( P5:5 ); + + R5 = 0x56 (X); + R6 = 0x57 (X); + R7 = 0x58 (X); + [ -- SP ] = ( R7:5 ); + R6 = 0x67 (X); + R7 = 0x68 (X); + [ -- SP ] = ( R7:6 ); + R7 = 0x78 (X); + [ -- SP ] = ( R7:7 ); + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + P1 = 0; + P2 = 0; + P3 = 0; + P4 = 0; + P5 = 0; + ( R7:7 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000078; + + ( R7:6 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000067; + CHECKREG r7, 0x00000068; + + ( R7:5 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000057; + CHECKREG r7, 0x00000058; + + ( P5:5 ) = [ SP ++ ]; + ( R7:4 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0x000000e5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000046; + CHECKREG r6, 0x00000047; + CHECKREG r7, 0x00000048; + + ( P5:4 ) = [ SP ++ ]; + ( R7:3 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x000000d4; + CHECKREG p5, 0x000000d5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000035; + CHECKREG r5, 0x00000036; + CHECKREG r6, 0x00000037; + CHECKREG r7, 0x00000038; + + ( P5:3 ) = [ SP ++ ]; + ( R7:2 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000c4; + CHECKREG p5, 0x000000c5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000024; + CHECKREG r4, 0x00000025; + CHECKREG r5, 0x00000026; + CHECKREG r6, 0x00000027; + CHECKREG r7, 0x00000028; + + ( P5:2 ) = [ SP ++ ]; + ( R7:1 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000b3; + CHECKREG p4, 0x000000b4; + CHECKREG p5, 0x000000b5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000013; + CHECKREG r3, 0x00000014; + CHECKREG r4, 0x00000015; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000017; + CHECKREG r7, 0x00000018; + + ( P5:1 ) = [ SP ++ ]; + ( R7:0 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000a2; + CHECKREG p3, 0x000000a3; + CHECKREG p4, 0x000000a4; + CHECKREG p5, 0x000000a5; + + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000003; + CHECKREG r3, 0x00000004; + CHECKREG r4, 0x00000005; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000007; + CHECKREG r7, 0x00000008; + pass diff --git a/sim/testsuite/bfin/c_pushpopmultiple_dp_pair.s b/sim/testsuite/bfin/c_pushpopmultiple_dp_pair.s new file mode 100644 index 0000000..78dae01 --- /dev/null +++ b/sim/testsuite/bfin/c_pushpopmultiple_dp_pair.s @@ -0,0 +1,203 @@ +//Original:/testcases/core/c_pushpopmultiple_dp_pair/c_pushpopmultiple_dp_pair.dsp +// Spec Reference: pushpopmultiple dreg preg in group pair +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + + imm32 r0, 0x00000000; + ASTAT = r0; + + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + P1 = 0xa1 (X); + P2 = 0xa2 (X); + P3 = 0xa3 (X); + P4 = 0xa4 (X); + P5 = 0xa5 (X); + [ -- SP ] = ( R7:0, P5:1 ); + + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + + P2 = 0xb2 (X); + P3 = 0xb3 (X); + P4 = 0xb4 (X); + P5 = 0xb5 (X); + [ -- SP ] = ( R7:1, P5:2 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + + P3 = 0xc3 (X); + P4 = 0xc4 (X); + P5 = 0xc5 (X); + [ -- SP ] = ( R7:2, P5:3 ); + + R3 = 0x34; + R4 = 0x35; + R5 = 0x36; + R6 = 0x37; + R7 = 0x38; + + P4 = 0xd4 (X); + P5 = 0xd5 (X); + [ -- SP ] = ( R7:3, P5:4 ); + + R4 = 0x45 (X); + R5 = 0x46 (X); + R6 = 0x47 (X); + R7 = 0x48 (X); + P5 = 0xe5 (X); + [ -- SP ] = ( R7:4, P5:5 ); + + R5 = 0x56 (X); + R6 = 0x57 (X); + R7 = 0x58 (X); + [ -- SP ] = ( R7:5 ); + R6 = 0x67 (X); + R7 = 0x68 (X); + [ -- SP ] = ( R7:6 ); + R7 = 0x78 (X); + [ -- SP ] = ( R7:7 ); + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + P1 = 0; + P2 = 0; + P3 = 0; + P4 = 0; + P5 = 0; + ( R7:7 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000078; + + ( R7:6 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000067; + CHECKREG r7, 0x00000068; + + ( R7:5 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000057; + CHECKREG r7, 0x00000058; + + ( R7:4, P5:5 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0x000000e5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000046; + CHECKREG r6, 0x00000047; + CHECKREG r7, 0x00000048; + + ( R7:3, P5:4 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x000000d4; + CHECKREG p5, 0x000000d5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000035; + CHECKREG r5, 0x00000036; + CHECKREG r6, 0x00000037; + CHECKREG r7, 0x00000038; + + ( R7:2, P5:3 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000c4; + CHECKREG p5, 0x000000c5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000024; + CHECKREG r4, 0x00000025; + CHECKREG r5, 0x00000026; + CHECKREG r6, 0x00000027; + CHECKREG r7, 0x00000028; + + ( R7:1, P5:2 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000b3; + CHECKREG p4, 0x000000b4; + CHECKREG p5, 0x000000b5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000013; + CHECKREG r3, 0x00000014; + CHECKREG r4, 0x00000015; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000017; + CHECKREG r7, 0x00000018; + + ( R7:0, P5:1 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000a2; + CHECKREG p3, 0x000000a3; + CHECKREG p4, 0x000000a4; + CHECKREG p5, 0x000000a5; + + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000003; + CHECKREG r3, 0x00000004; + CHECKREG r4, 0x00000005; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000007; + CHECKREG r7, 0x00000008; + pass diff --git a/sim/testsuite/bfin/c_pushpopmultiple_dreg.s b/sim/testsuite/bfin/c_pushpopmultiple_dreg.s new file mode 100644 index 0000000..ca1ebf1 --- /dev/null +++ b/sim/testsuite/bfin/c_pushpopmultiple_dreg.s @@ -0,0 +1,173 @@ +//Original:/testcases/core/c_pushpopmultiple_dreg/c_pushpopmultiple_dreg.dsp +// Spec Reference: pushpopmultiple dreg +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + + imm32 r0, 0x00000000; + ASTAT = r0; + + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:0 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000003; + CHECKREG r3, 0x00000004; + CHECKREG r4, 0x00000005; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000007; + CHECKREG r7, 0x00000008; + + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + [ -- SP ] = ( R7:1 ); + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:1 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000013; + CHECKREG r3, 0x00000014; + CHECKREG r4, 0x00000015; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000017; + CHECKREG r7, 0x00000018; + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + [ -- SP ] = ( R7:2 ); + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:2 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000024; + CHECKREG r4, 0x00000025; + CHECKREG r5, 0x00000026; + CHECKREG r6, 0x00000027; + CHECKREG r7, 0x00000028; + + R3 = 0x34; + R4 = 0x35; + R5 = 0x36; + R6 = 0x37; + R7 = 0x38; + [ -- SP ] = ( R7:3 ); + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:3 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000035; + CHECKREG r5, 0x00000036; + CHECKREG r6, 0x00000037; + CHECKREG r7, 0x00000038; + + R4 = 0x45 (X); + R5 = 0x46 (X); + R6 = 0x47 (X); + R7 = 0x48 (X); + [ -- SP ] = ( R7:4 ); + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:4 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000046; + CHECKREG r6, 0x00000047; + CHECKREG r7, 0x00000048; + + R5 = 0x56 (X); + R6 = 0x57 (X); + R7 = 0x58 (X); + [ -- SP ] = ( R7:5 ); + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:5 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000057; + CHECKREG r7, 0x00000058; + + R6 = 0x67 (X); + R7 = 0x68 (X); + [ -- SP ] = ( R7:6 ); + R6 = 0; + R7 = 0; + ( R7:6 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000067; + CHECKREG r7, 0x00000068; + + R7 = 0x78 (X); + [ -- SP ] = ( R7:7 ); + R7 = 0; + ( R7:7 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000067; + CHECKREG r7, 0x00000078; + + pass diff --git a/sim/testsuite/bfin/c_pushpopmultiple_preg.s b/sim/testsuite/bfin/c_pushpopmultiple_preg.s new file mode 100644 index 0000000..15c1937 --- /dev/null +++ b/sim/testsuite/bfin/c_pushpopmultiple_preg.s @@ -0,0 +1,83 @@ +//Original:/testcases/core/c_pushpopmultiple_preg/c_pushpopmultiple_preg.dsp +// Spec Reference: pushpopmultiple preg +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + + imm32 r0, 0x00000000; + ASTAT = r0; + + P1 = 0xa1 (X); + P2 = 0xa2 (X); + P3 = 0xa3 (X); + P4 = 0xa4 (X); + P5 = 0xa5 (X); + [ -- SP ] = ( P5:1 ); + P1 = 0; + P2 = 0; + P3 = 0; + P4 = 0; + P5 = 0; + ( P5:1 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000a2; + CHECKREG p3, 0x000000a3; + CHECKREG p4, 0x000000a4; + CHECKREG p5, 0x000000a5; + + P2 = 0xb2 (X); + P3 = 0xb3 (X); + P4 = 0xb4 (X); + P5 = 0xb5 (X); + [ -- SP ] = ( P5:2 ); + P2 = 0; + P3 = 0; + P4 = 0; + P5 = 0; + ( P5:2 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000b3; + CHECKREG p4, 0x000000b4; + CHECKREG p5, 0x000000b5; + + P3 = 0xc3 (X); + P4 = 0xc4 (X); + P5 = 0xc5 (X); + [ -- SP ] = ( P5:3 ); + P3 = 0; + P4 = 0; + P5 = 0; + ( P5:3 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000c4; + CHECKREG p5, 0x000000c5; + + P4 = 0xd4 (X); + P5 = 0xd5 (X); + [ -- SP ] = ( P5:4 ); + P4 = 0; + P5 = 0; + ( P5:4 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000d4; + CHECKREG p5, 0x000000d5; + + P5 = 0xe5 (X); + [ -- SP ] = ( P5:5 ); + P5 = 0; + ( P5:5 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000d4; + CHECKREG p5, 0x000000e5; + + pass diff --git a/sim/testsuite/bfin/c_regmv_acc_acc.s b/sim/testsuite/bfin/c_regmv_acc_acc.s new file mode 100644 index 0000000..08e4414 --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_acc_acc.s @@ -0,0 +1,125 @@ +//Original:/testcases/core/c_regmv_acc_acc/c_regmv_acc_acc.dsp +// Spec Reference: regmv acc-acc +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0xa9627911; + imm32 r1, 0xd0158978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0x0004000d; + imm32 r7, 0x000e500f; + A0 = R0; + + A1 = A0; + R2 = A1.w; + R3 = A1.x; + + A1.x = A0.w; + A1.w = A0.w; + A0.x = A0.w; + A0.w = A0.w; + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + + CHECKREG r0, 0xA9627911; + CHECKREG r1, 0xD0158978; + CHECKREG r2, 0xA9627911; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r4, 0xA9627911; + CHECKREG r5, 0x00000011; + CHECKREG r6, 0xA9627911; + CHECKREG r7, 0x00000011; + + imm32 r0, 0x90ba7911; + imm32 r1, 0xe3458978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x56080009; + imm32 r5, 0x783a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x489e534f; + A1 = R0; + + A0 = A1; + R2 = A0.w; + R3 = A0.x; + + A0.x = A1.w; + A0.w = A1.w; + A1.x = A1.w; + A1.w = A1.w; + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + CHECKREG r0, 0x90BA7911; + CHECKREG r1, 0xE3458978; + CHECKREG r2, 0x90BA7911; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r4, 0x90BA7911; + CHECKREG r5, 0x00000011; + CHECKREG r6, 0x90BA7911; + CHECKREG r7, 0x00000011; + + imm32 r0, 0xf9627911; + imm32 r1, 0xd0158978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x789e534f; + A0 = R0; + + A0.x = A0.x; + A0.w = A0.x; + A1.w = A0.x; + A1.x = A0.x; + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + CHECKREG r0, 0xF9627911; + CHECKREG r1, 0xD0158978; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x10060007; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0xFFFFFFFF; + + imm32 r0, 0x90ba7911; + imm32 r1, 0xe3458978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x56080009; + imm32 r5, 0x783a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x489e534f; + A1 = R0; + + A0.x = A1.x; + A0.w = A1.x; + A1.w = A1.x; + A1.x = A1.x; + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + CHECKREG r0, 0x90BA7911; + CHECKREG r1, 0xE3458978; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x10060007; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0xFFFFFFFF; + + pass diff --git a/sim/testsuite/bfin/c_regmv_dag_lz_dep.s b/sim/testsuite/bfin/c_regmv_dag_lz_dep.s new file mode 100644 index 0000000..fb95a73 --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_dag_lz_dep.s @@ -0,0 +1,148 @@ +//Original:/testcases/core/c_regmv_dag_lz_dep/c_regmv_dag_lz_dep.dsp +// Spec Reference: regmv dag lz dep forward +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 r0, 0x11111111; +imm32 r1, 0x22223331; +imm32 r2, 0x44445551; +imm32 r3, 0x66667771; +imm32 r4, 0x88889991; +imm32 r5, 0xaaaabbb1; +imm32 r6, 0xccccddd1; +imm32 r7, 0xeeeefff1; + +I0 = R0; +I0 = 0x1122 (Z); +R0 = I0; + +I1 = R1; +I1 = 0x3344 (Z); +R1 = I1; + +I2 = R2; +I2 = 0x5566 (Z); +R2 = I2; + +I3 = R3; +I3 = 0x7788 (Z); +R3 = I3; + + +B0 = R4; +B0 = 0x99aa (Z); +R4 = B0; + +B1 = R5; +B1 = 0xbbcc (Z); +R5 = B1; + +B2 = R6; +B2 = 0xddee (Z); +R6 = B2; + +B3 = R7; +B3 = 0xff01 (Z); +R7 = B3; + +CHECKREG r0, 0x00001122; +CHECKREG r1, 0x00003344; +CHECKREG r2, 0x00005566; +CHECKREG r3, 0x00007788; +CHECKREG r4, 0x000099AA; +CHECKREG r5, 0x0000BBCC; +CHECKREG r6, 0x0000DDEE; +CHECKREG r7, 0x0000FF01; + +imm32 r0, 0x11111112; +imm32 r1, 0x22223332; +imm32 r2, 0x44445552; +imm32 r3, 0x66667772; +imm32 r4, 0x88889992; +imm32 r5, 0xaaaabbb2; +imm32 r6, 0xccccddd2; +imm32 r7, 0xeeeefff2; +M0 = R0; +M0 = 0xa1a2 (Z); +R0 = M0; + +M1 = R1; +M1 = 0xb1b2 (Z); +R1 = M1; + +M2 = R2; +M2 = 0xc1c2 (Z); +R2 = M2; + +M3 = R3; +M3 = 0xd1d2 (Z); +R3 = M3; + + +L0 = R4; +L0 = 0xe1e2 (Z); +R4 = L0; + +L1 = R5; +L1 = 0xf1f2 (Z); +R5 = L1; + +L2 = R6; +L2 = 0x1112 (Z); +R6 = L2; + +L3 = R7; +L3 = 0x2122 (Z); +R7 = L3; + +CHECKREG r0, 0x0000A1A2; +CHECKREG r1, 0x0000B1B2; +CHECKREG r2, 0x0000C1C2; +CHECKREG r3, 0x0000D1D2; +CHECKREG r4, 0x0000E1E2; +CHECKREG r5, 0x0000F1F2; +CHECKREG r6, 0x00001112; +CHECKREG r7, 0x00002122; + +imm32 r0, 0x11111113; +imm32 r1, 0x22223333; +imm32 r2, 0x44445553; +imm32 r3, 0x66667773; +imm32 r4, 0x88889993; +imm32 r5, 0xaaaabbb3; +imm32 r6, 0xccccddd3; +imm32 r7, 0xeeeefff3; + +P1 = R1; +P1 = 0x3A3B (Z); +R1 = P1; + + +P2 = R2; +P2 = 0x4A4B (Z); +R2 = P2; + +P3 = R3; +P3 = 0x5A5B (Z); +R3 = P3; + +P4 = R4; +P4 = 0x6A6B (Z); +R4 = P4; + +P5 = R5; +P5 = 0x7A7B (Z); +R5 = P5; + +CHECKREG r1, 0x00003A3B; +CHECKREG r2, 0x00004A4B; +CHECKREG r3, 0x00005A5B; +CHECKREG r4, 0x00006A6B; +CHECKREG r5, 0x00007A7B; + +pass diff --git a/sim/testsuite/bfin/c_regmv_dr_acc_acc.s b/sim/testsuite/bfin/c_regmv_dr_acc_acc.s new file mode 100644 index 0000000..6af3d04 --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_dr_acc_acc.s @@ -0,0 +1,191 @@ +//Original:/testcases/core/c_regmv_dr_acc_acc/c_regmv_dr_acc_acc.dsp +// Spec Reference: regmv dreg-acc-acc +# mach: bfin + +.include "testutils.inc" + start + + + +// check R-reg to ACC + imm32 r0, 0x00000000; + imm32 r1, 0x12345678; + imm32 r2, 0x91234567; + imm32 r3, 0x00060007; + imm32 r4, 0x00080009; + imm32 r5, 0x000a000b; + imm32 r6, 0x000c000d; + imm32 r7, 0x000e000f; + A0 = R0; + A1 = R0; + A0 = R1; + A1 = R2; + + R3 = A0.w; + R4 = A0.x; + R5 = A1.w; + R6 = A1.x; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x12345678; + CHECKREG r2, 0x91234567; + CHECKREG r3, 0x12345678; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x91234567; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0x000E000F; + + A1 = A0 = 0; + R3 = A0.w; + R4 = A0.x; + R5 = A1.w; + R6 = A1.x; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + + imm32 r0, 0xa5678901; + imm32 r1, 0xb0158978; + imm32 r2, 0x91234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0x0004000d; + imm32 r7, 0x000e500f; + A0 = R0; + A1 = R1; + + R3 = A0.w; + R4 = A0.x; + R5 = A1.w; + R6 = A1.x; + CHECKREG r0, 0xA5678901; + CHECKREG r1, 0xB0158978; + CHECKREG r2, 0x91234567; + CHECKREG r3, 0xA5678901; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, 0xB0158978; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0x000E500F; + + imm32 r0, 0xe9627911; + imm32 r1, 0xd0158978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0x0004000d; + imm32 r7, 0x000e500f; + A0 = R0; + A1 = A0; + + imm32 r0, 0x90ba7911; + imm32 r1, 0xe3458978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x56080009; + imm32 r5, 0x783a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x489e534f; + A0.w = R0; + A0.x = R1; + A1.w = R2; + A1.x = R3; + + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + + CHECKREG r0, 0x90BA7911; + CHECKREG r1, 0xE3458978; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x10060007; + CHECKREG r4, 0x90BA7911; + CHECKREG r5, 0x00000078; + CHECKREG r6, 0xC1234567; + CHECKREG r7, 0x00000007; + + R3 = A0.w; + R4 = A0.x; + R5 = A1.w; + R6 = A1.x; + CHECKREG r0, 0x90BA7911; + CHECKREG r1, 0xE3458978; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x90BA7911; + CHECKREG r4, 0x00000078; + CHECKREG r5, 0xC1234567; + CHECKREG r6, 0x00000007; + CHECKREG r7, 0x00000007; + + imm32 r0, 0xf9627911; + imm32 r1, 0xd0158978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x789e534f; + A0 = R6; + A1.w = A0.w; + A1.x = A0.x; + + R0 = A0.w; + R1 = A0.x; + R2 = A1.w; + R3 = A1.x; + + A1 = R7; + A0.w = A1.w; + A0.x = A1.x; + + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + + CHECKREG r0, 0xF247890D; + CHECKREG r1, 0xFFFFFFFF; + CHECKREG r2, 0xF247890D; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r4, 0x789E534F; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x789E534F; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x90ba7911; + imm32 r1, 0xe3458978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x56080009; + imm32 r5, 0x783a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x489e534f; + A0.w = A1.x; + A0.x = A1.x; + R4 = A0.w; + R5 = A0.x; + + A0 = R2; + A1.w = A0.x; + A1.x = A0.x; + + R6 = A1.w; + R7 = A1.x; + + A0.x = A1.w; + A1.x = A0.w; + R0 = A0.x; + R1 = A1.x; + + CHECKREG r0, 0xFFFFFFFF; + CHECKREG r1, 0x00000067; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x10060007; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0xFFFFFFFF; + + pass diff --git a/sim/testsuite/bfin/c_regmv_dr_dep_nostall.s b/sim/testsuite/bfin/c_regmv_dr_dep_nostall.s new file mode 100644 index 0000000..118274d --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_dr_dep_nostall.s @@ -0,0 +1,245 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_dr_dep_nostall/c_regmv_dr_dep_nostall.dsp +// Spec Reference: regmv dr-dep no stall +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000001; + imm32 r1, 0x00110001; + imm32 r2, 0x00220002; + imm32 r3, 0x00330003; + imm32 r4, 0x00440004; + imm32 r5, 0x00550005; + imm32 r6, 0x00660006; + imm32 r7, 0x00770007; +// R-reg to R-reg: no stall + R0 = R0; + R1 = R0; + R2 = R1; + R3 = R2; + R4 = R3; + R5 = R4; + R6 = R5; + R7 = R6; + R0 = R7; + + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000001; + CHECKREG r4, 0x00000001; + CHECKREG r5, 0x00000001; + CHECKREG r6, 0x00000001; + CHECKREG r7, 0x00000001; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22223333; + imm32 p2, 0x44445555; + imm32 p3, 0x66667777; + imm32 p4, 0x88889999; + imm32 p5, 0xaaaabbbb; + imm32 fp, 0xccccdddd; + imm32 sp, 0xeeeeffff; + +// P-reg to R-reg to I,M reg: no stall + R0 = P0; + I0 = R0; + R1 = P1; + I1 = R1; + R2 = P2; + I2 = R2; + R3 = P3; + I3 = R3; + R4 = P4; + M0 = R4; + R5 = P5; + M1 = R5; + R6 = FP; + M2 = R6; + R7 = SP; + M3 = R7; + + CHECKREG r1, 0x22223333; + CHECKREG r2, 0x44445555; + CHECKREG r3, 0x66667777; + CHECKREG r4, 0x88889999; + CHECKREG r5, 0xAAAABBBB; + CHECKREG r6, 0xCCCCDDDD; + CHECKREG r7, 0xEEEEFFFF; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0xEEEEFFFF; + CHECKREG r1, 0xCCCCDDDD; + CHECKREG r2, 0xAAAABBBB; + CHECKREG r3, 0x88889999; + CHECKREG r4, 0x66667777; + CHECKREG r5, 0x44445555; + CHECKREG r6, 0x22223333; + + imm32 i0, 0x00001111; + imm32 i1, 0x22223333; + imm32 i2, 0x44445555; + imm32 i3, 0x66667777; + imm32 m0, 0x88889999; + imm32 m0, 0xaaaabbbb; + imm32 m0, 0xccccdddd; + imm32 m0, 0xeeeeffff; + +// I,M-reg to R-reg to P-reg: no stall + R0 = I0; + P1 = R0; + R1 = I1; + P1 = R1; + R2 = I2; + P2 = R2; + R3 = I3; + P3 = R3; + R4 = M0; + P4 = R4; + R5 = M1; + P5 = R5; + R6 = M2; + SP = R6; + R7 = M3; + FP = R7; + + CHECKREG p1, 0x22223333; + CHECKREG p2, 0x44445555; + CHECKREG p3, 0x66667777; + CHECKREG p4, 0xEEEEFFFF; + CHECKREG p5, 0xAAAABBBB; + CHECKREG sp, 0xCCCCDDDD; + CHECKREG fp, 0xEEEEFFFF; + + imm32 i0, 0x10001111; + imm32 i1, 0x12221333; + imm32 i2, 0x14441555; + imm32 i3, 0x16661777; + imm32 m0, 0x18881999; + imm32 m1, 0x1aaa1bbb; + imm32 m2, 0x1ccc1ddd; + imm32 m3, 0x1eee1fff; + +// I,M-reg to R-reg to L,B reg: no stall + R0 = I0; + L0 = R0; + R1 = I1; + L1 = R1; + R2 = I2; + L2 = R2; + R3 = I3; + L3 = R3; + R4 = M0; + B0 = R4; + R5 = M1; + B1 = R5; + R6 = M2; + B2 = R6; + R7 = M3; + B3 = R7; + + CHECKREG r0, 0x10001111; + CHECKREG r1, 0x12221333; + CHECKREG r2, 0x14441555; + CHECKREG r3, 0x16661777; + CHECKREG r4, 0x18881999; + CHECKREG r5, 0x1AAA1BBB; + CHECKREG r6, 0x1CCC1DDD; + CHECKREG r7, 0x1EEE1FFF; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x16661777; + CHECKREG r1, 0x14441555; + CHECKREG r2, 0x12221333; + CHECKREG r3, 0x10001111; + CHECKREG r4, 0x1EEE1FFF; + CHECKREG r5, 0x1CCC1DDD; + CHECKREG r6, 0x1AAA1BBB; + CHECKREG r7, 0x18881999; + + imm32 l0, 0x20003111; + imm32 l1, 0x22223333; + imm32 l2, 0x24443555; + imm32 l3, 0x26663777; + imm32 b0, 0x28883999; + imm32 b0, 0x2aaa3bbb; + imm32 b0, 0x2ccc3ddd; + imm32 b0, 0x2eee3fff; + +// L,B-reg to R-reg to I,M reg: no stall + R0 = L0; + I0 = R0; + R1 = L1; + I1 = R1; + R2 = L2; + I2 = R2; + R3 = L3; + I3 = R3; + R4 = B0; + M0 = R4; + R5 = B1; + M1 = R5; + R6 = B2; + M2 = R6; + R7 = B3; + M3 = R7; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x1EEE1FFF; + CHECKREG r1, 0x1CCC1DDD; + CHECKREG r2, 0x1AAA1BBB; + CHECKREG r3, 0x2EEE3FFF; + CHECKREG r4, 0x26663777; + CHECKREG r5, 0x24443555; + CHECKREG r6, 0x22223333; + CHECKREG r7, 0x20003111; + + imm32 r0, 0x00000030; + imm32 r1, 0x00000031; + imm32 r2, 0x00000003; + imm32 r3, 0x00330003; + imm32 r4, 0x00440004; + imm32 r5, 0x00550005; + imm32 r6, 0x00660006; + imm32 r7, 0x00770007; + +// R-reg to R-reg to sysreg to Reg: no stall + R3 = R0; + ASTAT = R3; + R6 = ASTAT; + R4 = R1; + RETS = R4; + R7 = RETS; + + CHECKREG r0, 0x00000030; + CHECKREG r1, 0x00000031; + CHECKREG r2, 0x00000003; + CHECKREG r3, 0x00000030; + CHECKREG r4, 0x00000031; + CHECKREG r5, 0x00550005; + CHECKREG r6, 0x00000030; + CHECKREG r7, 0x00000031; + + pass diff --git a/sim/testsuite/bfin/c_regmv_dr_dr.s b/sim/testsuite/bfin/c_regmv_dr_dr.s new file mode 100644 index 0000000..e1fb658 --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_dr_dr.s @@ -0,0 +1,209 @@ +//Original:/testcases/core/c_regmv_dr_dr/c_regmv_dr_dr.dsp +// Spec Reference: regmv dreg-to-dreg +# mach: bfin + +.include "testutils.inc" + start + +// check R-reg to R-reg move +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R0; +R1 = R0; +R2 = R0; +R3 = R0; +R4 = R0; +R5 = R0; +R6 = R0; +R7 = R0; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R1; +R1 = R1; +R2 = R1; +R3 = R1; +R4 = R1; +R5 = R1; +R6 = R1; +R7 = R1; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R2; +R1 = R2; +R2 = R2; +R3 = R2; +R4 = R2; +R5 = R2; +R6 = R2; +R7 = R2; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R3; +R1 = R3; +R2 = R3; +R3 = R3; +R4 = R3; +R5 = R3; +R6 = R3; +R7 = R3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R4; +R1 = R4; +R2 = R4; +R3 = R4; +R4 = R4; +R5 = R4; +R6 = R4; +R7 = R4; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R5; +R1 = R5; +R2 = R5; +R3 = R5; +R4 = R5; +R5 = R5; +R6 = R5; +R7 = R5; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R6; +R1 = R6; +R2 = R6; +R3 = R6; +R4 = R6; +R5 = R6; +R6 = R6; +R7 = R6; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R7; +R1 = R7; +R2 = R7; +R3 = R7; +R4 = R7; +R5 = R7; +R6 = R7; +R7 = R7; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + +pass diff --git a/sim/testsuite/bfin/c_regmv_dr_imlb.s b/sim/testsuite/bfin/c_regmv_dr_imlb.s new file mode 100644 index 0000000..01650b0 --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_dr_imlb.s @@ -0,0 +1,539 @@ +//Original:/testcases/core/c_regmv_dr_imlb/c_regmv_dr_imlb.dsp +// Spec Reference: regmv dreg-to-imlb +# mach: bfin + +.include "testutils.inc" + start + +// check DR-reg to imlb-reg move +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R0; +I1 = R0; +I2 = R0; +I3 = R0; +M0 = R0; +M1 = R0; +M2 = R0; +M3 = R0; + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R1; +I1 = R1; +I2 = R1; +I3 = R1; +M0 = R1; +M1 = R1; +M2 = R1; +M3 = R1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R2; +I1 = R2; +I2 = R2; +I3 = R2; +M0 = R2; +M1 = R2; +M2 = R2; +M3 = R2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R3; +I1 = R3; +I2 = R3; +I3 = R3; +M0 = R3; +M1 = R3; +M2 = R3; +M3 = R3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R4; +I1 = R4; +I2 = R4; +I3 = R4; +M0 = R4; +M1 = R4; +M2 = R4; +M3 = R4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R5; +I1 = R5; +I2 = R5; +I3 = R5; +M0 = R5; +M1 = R5; +M2 = R5; +M3 = R5; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R6; +I1 = R6; +I2 = R6; +I3 = R6; +M0 = R6; +M1 = R6; +M2 = R6; +M3 = R6; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R7; +I1 = R7; +I2 = R7; +I3 = R7; +M0 = R7; +M1 = R7; +M2 = R7; +M3 = R7; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R0; +L1 = R0; +L2 = R0; +L3 = R0; +B0 = R0; +B1 = R0; +B2 = R0; +B3 = R0; + +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R1; +L1 = R1; +L2 = R1; +L3 = R1; +B0 = R1; +B1 = R1; +B2 = R1; +B3 = R1; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R2; +L1 = R2; +L2 = R2; +L3 = R2; +B0 = R2; +B1 = R2; +B2 = R2; +B3 = R2; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R3; +L1 = R3; +L2 = R3; +L3 = R3; +B0 = R3; +B1 = R3; +B2 = R3; +B3 = R3; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R4; +L1 = R4; +L2 = R4; +L3 = R4; +B0 = R4; +B1 = R4; +B2 = R4; +B3 = R4; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R5; +L1 = R5; +L2 = R5; +L3 = R5; +B0 = R5; +B1 = R5; +B2 = R5; +B3 = R5; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R6; +L1 = R6; +L2 = R6; +L3 = R6; +B0 = R6; +B1 = R6; +B2 = R6; +B3 = R6; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R7; +L1 = R7; +L2 = R7; +L3 = R7; +B0 = R7; +B1 = R7; +B2 = R7; +B3 = R7; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + +pass diff --git a/sim/testsuite/bfin/c_regmv_dr_pr.s b/sim/testsuite/bfin/c_regmv_dr_pr.s new file mode 100644 index 0000000..fd8967c --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_dr_pr.s @@ -0,0 +1,107 @@ +//Original:/testcases/core/c_regmv_dr_pr/c_regmv_dr_pr.dsp +// Spec Reference: regmv dreg-to-preg +# mach: bfin + +.include "testutils.inc" + start + +// check R-reg to R-reg move + imm32 r0, 0x20001001; + imm32 r1, 0x20021003; + imm32 r2, 0x20041005; + imm32 r3, 0x20061007; + imm32 r4, 0x20081009; + imm32 r5, 0x200a100b; + imm32 r6, 0x200c100d; + imm32 r7, 0x200e100f; + + P1 = R0; + P2 = R0; + P4 = R0; + P5 = R0; + FP = R0; + CHECKREG p1, 0x20001001; + CHECKREG p2, 0x20001001; + CHECKREG p4, 0x20001001; + CHECKREG p5, 0x20001001; + CHECKREG fp, 0x20001001; + + P1 = R1; + P2 = R1; + P4 = R1; + P5 = R1; + FP = R1; + CHECKREG p1, 0x20021003; + CHECKREG p2, 0x20021003; + CHECKREG p4, 0x20021003; + CHECKREG p5, 0x20021003; + CHECKREG fp, 0x20021003; + + P1 = R2; + P2 = R2; + P4 = R2; + P5 = R2; + FP = R2; + CHECKREG p1, 0x20041005; + CHECKREG p2, 0x20041005; + CHECKREG p4, 0x20041005; + CHECKREG p5, 0x20041005; + CHECKREG fp, 0x20041005; + + P1 = R3; + P2 = R3; + P4 = R3; + P5 = R3; + FP = R3; + CHECKREG p1, 0x20061007; + CHECKREG p2, 0x20061007; + CHECKREG p4, 0x20061007; + CHECKREG p5, 0x20061007; + CHECKREG fp, 0x20061007; + + P1 = R4; + P2 = R4; + P4 = R4; + P5 = R4; + FP = R4; + CHECKREG p1, 0x20081009; + CHECKREG p2, 0x20081009; + CHECKREG p4, 0x20081009; + CHECKREG p5, 0x20081009; + CHECKREG fp, 0x20081009; + + P1 = R5; + P2 = R5; + P4 = R5; + P5 = R5; + FP = R5; + CHECKREG p1, 0x200a100b; + CHECKREG p2, 0x200a100b; + CHECKREG p4, 0x200a100b; + CHECKREG p5, 0x200a100b; + CHECKREG fp, 0x200a100b; + + P1 = R6; + P2 = R6; + P4 = R6; + P5 = R6; + FP = R6; + CHECKREG p1, 0x200c100d; + CHECKREG p2, 0x200c100d; + CHECKREG p4, 0x200c100d; + CHECKREG p5, 0x200c100d; + CHECKREG fp, 0x200c100d; + + P1 = R7; + P2 = R7; + P4 = R7; + P5 = R7; + FP = R7; + CHECKREG p1, 0x200e100f; + CHECKREG p2, 0x200e100f; + CHECKREG p4, 0x200e100f; + CHECKREG p5, 0x200e100f; + CHECKREG fp, 0x200e100f; + +End: + pass diff --git a/sim/testsuite/bfin/c_regmv_imlb_dep_nostall.s b/sim/testsuite/bfin/c_regmv_imlb_dep_nostall.s new file mode 100644 index 0000000..cda1fb1 --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_imlb_dep_nostall.s @@ -0,0 +1,664 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_nostall/c_regmv_imlb_dep_nostall.dsp +// Spec Reference: regmv imlb-dep no stall +# mach: bfin + +.include "testutils.inc" + start + +// P-reg to I,M-reg to R-reg: no stall +//imm32 p0, 0x00001111; + imm32 p1, 0x12213330; + imm32 p2, 0x14415550; + imm32 p3, 0x16617770; + imm32 p4, 0x18819990; + imm32 p5, 0x1aa1bbb0; + imm32 fp, 0x1cc1ddd0; + imm32 sp, 0x1ee1fff0; + I0 = P0; + R0 = I0; + I1 = P1; + R1 = I1; + I2 = P2; + R2 = I2; + I3 = P3; + R3 = I3; + M0 = P4; + R4 = M0; + M1 = P5; + R5 = M1; + M2 = SP; + R6 = M2; + M3 = FP; + R7 = M3; + + CHECKREG r1, 0x12213330; + CHECKREG r2, 0x14415550; + CHECKREG r3, 0x16617770; + CHECKREG r4, 0x18819990; + CHECKREG r5, 0x1aa1bbb0; + CHECKREG r6, 0x1EE1FFF0; + CHECKREG r7, 0x1CC1DDD0; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x1CC1DDD0; + CHECKREG r1, 0x1EE1FFF0; + CHECKREG r2, 0x1AA1BBB0; + CHECKREG r3, 0x18819990; + CHECKREG r4, 0x16617770; + CHECKREG r5, 0x14415550; + CHECKREG r6, 0x12213330; + +// P-reg to L,B-reg to R-reg: no stall +//imm32 p0, 0x00001111; + imm32 p1, 0x21213331; + imm32 p2, 0x21415551; + imm32 p3, 0x21617771; + imm32 p4, 0x21819991; + imm32 p5, 0x21a1bbb1; + imm32 fp, 0x21c1ddd1; + imm32 sp, 0x21e1fff1; + L0 = P0; + R0 = L0; + L1 = P1; + R1 = L1; + L2 = P2; + R2 = L2; + L3 = P3; + R3 = L3; + B0 = P4; + R4 = B0; + B1 = P5; + R5 = B1; + B2 = SP; + R6 = B2; + B3 = FP; + R7 = B3; + + CHECKREG r1, 0x21213331; + CHECKREG r2, 0x21415551; + CHECKREG r3, 0x21617771; + CHECKREG r4, 0x21819991; + CHECKREG r5, 0x21a1bbb1; + CHECKREG r6, 0x21E1FFF1; + CHECKREG r7, 0x21C1DDD1; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x21617771; + CHECKREG r1, 0x21415551; + CHECKREG r2, 0x21213331; + CHECKREG r4, 0x21C1DDD1; + CHECKREG r5, 0x21E1FFF1; + CHECKREG r6, 0x21A1BBB1; + CHECKREG r7, 0x21819991; + +// P-reg to I,M-reg to L,B-reg: no stall +//imm32 p0, 0x00001111; + imm32 p1, 0x72213337; + imm32 p2, 0x74415557; + imm32 p3, 0x76617777; + imm32 p4, 0x78819997; + imm32 p5, 0x7aa1bbb7; + imm32 fp, 0x7cc1ddd7; + imm32 sp, 0x77e1fff7; + I0 = P0; + L0 = I0; + I1 = P1; + L1 = I1; + I2 = P2; + L2 = I2; + I3 = P3; + L3 = I3; + M0 = P4; + B0 = M0; + M1 = P5; + B1 = M1; + M2 = SP; + B2 = M2; + M3 = FP; + B3 = M3; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x76617777; + CHECKREG r1, 0x74415557; + CHECKREG r2, 0x72213337; + CHECKREG r4, 0x7CC1DDD7; + CHECKREG r5, 0x77E1FFF7; + CHECKREG r6, 0x7AA1BBB7; + CHECKREG r7, 0x78819997; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x7CC1DDD7; + CHECKREG r1, 0x77E1FFF7; + CHECKREG r2, 0x7AA1BBB7; + CHECKREG r3, 0x78819997; + CHECKREG r4, 0x76617777; + CHECKREG r5, 0x74415557; + CHECKREG r6, 0x72213337; + +// P-reg to L,B-reg to I,Mreg: no stall +//imm32 p0, 0x00001111; + imm32 p1, 0x81213338; + imm32 p2, 0x81415558; + imm32 p3, 0x81617778; + imm32 p4, 0x81819998; + imm32 p5, 0x81a1bbb8; + imm32 fp, 0x81c1ddd8; + imm32 sp, 0x81e1fff8; + L0 = P0; + I0 = L0; + L1 = P1; + I1 = L1; + L2 = P2; + I2 = L2; + L3 = P3; + I3 = L3; + B0 = P4; + M0 = B0; + B1 = P5; + M1 = B1; + B2 = SP; + M2 = B2; + B3 = FP; + M3 = B3; + + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x81819998; + CHECKREG r1, 0x81A1BBB8; + CHECKREG r2, 0x81E1FFF8; + CHECKREG r3, 0x81C1DDD8; + CHECKREG r5, 0x81213338; + CHECKREG r6, 0x81415558; + CHECKREG r7, 0x81617778; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x81617778; + CHECKREG r1, 0x81415558; + CHECKREG r2, 0x81213338; + CHECKREG r4, 0x81C1DDD8; + CHECKREG r5, 0x81E1FFF8; + CHECKREG r6, 0x81A1BBB8; + CHECKREG r7, 0x81819998; + +// I-to-M, I-to-I and to R-reg: no stall + imm32 i0, 0x30001111; + imm32 i1, 0x23213332; + imm32 i2, 0x14315552; + imm32 i3, 0x01637772; + imm32 m0, 0x80113992; + imm32 m1, 0xaa01b3b2; + imm32 m2, 0xccc01d32; + imm32 m3, 0xeee101f3; + M0 = I0; + R4 = M0; + M1 = I1; + R5 = M1; + M2 = I2; + R6 = M2; + M3 = I3; + R7 = M3; + I0 = I3; + R0 = I0; + I1 = I2; + R1 = I1; + I3 = I0; + R2 = I3; + I2 = I1; + R3 = I2; + + CHECKREG r0, 0x01637772; + CHECKREG r1, 0x14315552; + CHECKREG r2, 0x01637772; + CHECKREG r3, 0x14315552; + CHECKREG r4, 0x30001111; + CHECKREG r5, 0x23213332; + CHECKREG r6, 0x14315552; + CHECKREG r7, 0x01637772; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x30001111; + CHECKREG r1, 0x23213332; + CHECKREG r2, 0x14315552; + CHECKREG r3, 0x01637772; + CHECKREG r4, 0x01637772; + CHECKREG r5, 0x14315552; + CHECKREG r6, 0x14315552; + CHECKREG r7, 0x01637772; + +// I-to-M, I-to-I and to P-reg: no stall + imm32 i0, 0x00001111; + imm32 i1, 0x42213342; + imm32 i2, 0x44415542; + imm32 i3, 0x46617742; + imm32 m0, 0x48819942; + imm32 m1, 0x4aa1bb42; + imm32 m2, 0x4cc1dd42; + imm32 m3, 0x4ee1ff42; + M0 = I0; + R0 = M0; + M1 = I1; + P1 = M1; + M2 = I2; + P2 = M2; + M3 = I3; + P3 = M3; + I0 = I3; + P4 = I0; + I1 = I2; + P5 = I1; + I2 = I0; + SP = I2; + I3 = I1; + FP = I3; + + CHECKREG r0, 0x00001111; + CHECKREG p1, 0x42213342; + CHECKREG p2, 0x44415542; + CHECKREG p3, 0x46617742; + CHECKREG p4, 0x46617742; + CHECKREG p5, 0x44415542; + CHECKREG sp, 0x46617742; + CHECKREG fp, 0x44415542; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x00001111; + CHECKREG r1, 0x42213342; + CHECKREG r2, 0x44415542; + CHECKREG r3, 0x46617742; + CHECKREG r4, 0x46617742; + CHECKREG r5, 0x44415542; + CHECKREG r6, 0x46617742; + CHECKREG r7, 0x44415542; + +// L-to-B, L-to-L and to R-reg: no stall + imm32 l0, 0x40001114; + imm32 l1, 0x24213334; + imm32 l2, 0x54415554; + imm32 l3, 0x05647774; + imm32 b0, 0x60514994; + imm32 b1, 0xa605b4b4; + imm32 b2, 0xcc605d44; + imm32 b3, 0xeee605f4; + B0 = L0; + R4 = B0; + B1 = L1; + R5 = B1; + B2 = L2; + R6 = B2; + B3 = L3; + R7 = B3; + L0 = L3; + R0 = L0; + L1 = L2; + R1 = L1; + L3 = L0; + R2 = L3; + L2 = L1; + R3 = L2; + + CHECKREG r0, 0x05647774; + CHECKREG r1, 0x54415554; + CHECKREG r2, 0x05647774; + CHECKREG r3, 0x54415554; + CHECKREG r4, 0x40001114; + CHECKREG r5, 0x24213334; + CHECKREG r6, 0x54415554; + CHECKREG r7, 0x05647774; + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0x05647774; + CHECKREG r1, 0x54415554; + CHECKREG r2, 0x54415554; + CHECKREG r3, 0x05647774; + CHECKREG r4, 0x40001114; + CHECKREG r5, 0x24213334; + CHECKREG r6, 0x54415554; + CHECKREG r7, 0x05647774; + +// L-to-B, L-to-L and to P-reg: no stall + imm32 l0, 0x60001116; + imm32 l1, 0x46213346; + imm32 l2, 0x74615546; + imm32 l3, 0x47667746; + imm32 b0, 0x48716946; + imm32 b1, 0x8aa7b646; + imm32 b2, 0x48c17d66; + imm32 b3, 0x4e81f746; + M0 = I0; + R0 = M0; + M1 = I1; + P1 = M1; + M2 = I2; + P2 = M2; + M3 = I3; + P3 = M3; + I0 = I3; + P4 = I0; + I1 = I2; + P5 = I1; + I2 = I0; + SP = I2; + I3 = I1; + FP = I3; + + CHECKREG r0, 0x46617742; + CHECKREG p1, 0x44415542; + CHECKREG p2, 0x46617742; + CHECKREG p3, 0x44415542; + CHECKREG p4, 0x44415542; + CHECKREG p5, 0x46617742; + CHECKREG sp, 0x44415542; + CHECKREG fp, 0x46617742; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x46617742; + CHECKREG r1, 0x44415542; + CHECKREG r2, 0x46617742; + CHECKREG r3, 0x44415542; + CHECKREG r4, 0x44415542; + CHECKREG r5, 0x46617742; + CHECKREG r6, 0x44415542; + CHECKREG r7, 0x46617742; + +// I-to-M-to-L, I-to-I-to-B -reg: no stall + imm32 i0, 0x90001119; + imm32 i1, 0x93213339; + imm32 i2, 0x94315559; + imm32 i3, 0x91637779; + imm32 m0, 0x90113999; + imm32 m1, 0x9a01b3b9; + imm32 m2, 0x9cc01d39; + imm32 m3, 0x9ee101f9; + M0 = I0; + L0 = M0; + M1 = I1; + L1 = M1; + M2 = I2; + L2 = M2; + M3 = I3; + L3 = M3; + I0 = I3; + B0 = I0; + I1 = I2; + B1 = I1; + I3 = I0; + B2 = I3; + I2 = I1; + B3 = I2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0x90001119; + CHECKREG r1, 0x93213339; + CHECKREG r2, 0x94315559; + CHECKREG r3, 0x91637779; + CHECKREG r4, 0x91637779; + CHECKREG r5, 0x94315559; + CHECKREG r6, 0x91637779; + CHECKREG r7, 0x94315559; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x90001119; + CHECKREG r1, 0x93213339; + CHECKREG r2, 0x94315559; + CHECKREG r3, 0x91637779; + CHECKREG r4, 0x91637779; + CHECKREG r5, 0x94315559; + CHECKREG r6, 0x94315559; + CHECKREG r7, 0x91637779; + +// I-to-M-B, I-to-I-L reg: no stall + imm32 i0, 0xa000111a; + imm32 i1, 0xaa21334a; + imm32 i2, 0xa4a1554a; + imm32 i3, 0xa66a774a; + imm32 m0, 0xa881a94a; + imm32 m1, 0xaaa1ba4a; + imm32 m2, 0xacc1ddaa; + imm32 m3, 0xaee1ff4a; + M0 = I0; + B3 = M0; + M1 = I1; + B2 = M1; + M2 = I2; + B1 = M2; + M3 = I3; + B0 = M3; + I0 = I3; + L1 = I0; + I1 = I2; + L2 = I1; + I2 = I0; + L3 = I2; + I3 = I1; + L0 = I3; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0xA4A1554A; + CHECKREG r1, 0xA66A774A; + CHECKREG r2, 0xA4A1554A; + CHECKREG r3, 0xA66A774A; + CHECKREG r4, 0xA66A774A; + CHECKREG r5, 0xA4A1554A; + CHECKREG r6, 0xAA21334A; + CHECKREG r7, 0xA000111A; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0xA000111A; + CHECKREG r1, 0xAA21334A; + CHECKREG r2, 0xA4A1554A; + CHECKREG r3, 0xA66A774A; + CHECKREG r4, 0xA66A774A; + CHECKREG r5, 0xA4A1554A; + CHECKREG r6, 0xA66A774A; + CHECKREG r7, 0xA4A1554A; + +// L-to-B-to-I, L-to-L-to-M reg: no stall + imm32 l0, 0xb000111b; + imm32 l1, 0xb421333b; + imm32 l2, 0xb441555b; + imm32 l3, 0xb564777b; + imm32 b0, 0xb051499b; + imm32 b1, 0xb605b4bb; + imm32 b2, 0xbc605d4b; + imm32 b3, 0xbee605fb; + B0 = L0; + I2 = B0; + B1 = L1; + I3 = B1; + B2 = L2; + I0 = B2; + B3 = L3; + I1 = B3; + L0 = L3; + M0 = L0; + L1 = L2; + M1 = L1; + L3 = L0; + M2 = L3; + L2 = L1; + M3 = L2; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xB441555B; + CHECKREG r1, 0xB564777B; + CHECKREG r2, 0xB000111B; + CHECKREG r3, 0xB421333B; + CHECKREG r4, 0xB564777B; + CHECKREG r5, 0xB441555B; + CHECKREG r6, 0xB564777B; + CHECKREG r7, 0xB441555B; + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0xB564777B; + CHECKREG r1, 0xB441555B; + CHECKREG r2, 0xB441555B; + CHECKREG r3, 0xB564777B; + CHECKREG r4, 0xB000111B; + CHECKREG r5, 0xB421333B; + CHECKREG r6, 0xB441555B; + CHECKREG r7, 0xB564777B; + +// B-to-L-to-M, B-to-B-to-I reg: no stall + imm32 l0, 0xc000111c; + imm32 l1, 0xc621334c; + imm32 l2, 0xc461554c; + imm32 l3, 0xc766774c; + imm32 b0, 0xc871694c; + imm32 b1, 0xcaa7b64c; + imm32 b2, 0xc8c17d6c; + imm32 b3, 0xce81f74c; + L0 = B0; + M1 = L0; + L1 = B1; + M2 = L1; + L2 = B2; + M3 = L2; + L3 = B3; + M0 = L3; + B3 = B0; + I0 = B3; + B0 = B1; + I1 = B0; + B1 = B2; + I2 = B1; + B2 = B3; + I3 = B2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0xC871694C; + CHECKREG r1, 0xCAA7B64C; + CHECKREG r2, 0xC8C17D6C; + CHECKREG r3, 0xCE81F74C; + CHECKREG r4, 0xCAA7B64C; + CHECKREG r5, 0xC8C17D6C; + CHECKREG r6, 0xC871694C; + CHECKREG r7, 0xC871694C; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0xCE81F74C; + CHECKREG r1, 0xC871694C; + CHECKREG r2, 0xCAA7B64C; + CHECKREG r3, 0xC8C17D6C; + CHECKREG r4, 0xC871694C; + CHECKREG r5, 0xCAA7B64C; + CHECKREG r6, 0xC8C17D6C; + CHECKREG r7, 0xC871694C; + + pass diff --git a/sim/testsuite/bfin/c_regmv_imlb_dep_stall.s b/sim/testsuite/bfin/c_regmv_imlb_dep_stall.s new file mode 100644 index 0000000..8fd2235 --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_imlb_dep_stall.s @@ -0,0 +1,335 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_stall/c_regmv_imlb_dep_stall.dsp +// Spec Reference: regmv imlb-depepency stall +# mach: bfin + +.include "testutils.inc" + start + +// R-reg to I,M-reg to R-reg: stall + imm32 r0, 0x00001110; + imm32 r1, 0x00213330; + imm32 r2, 0x04015550; + imm32 r3, 0x06607770; + imm32 r4, 0x08010990; + imm32 r5, 0x0a01b0b0; + imm32 r6, 0x0c01dd00; + imm32 r7, 0x0e01f0f0; + I0 = R0; + R7 = I0; + I1 = R1; + R0 = I1; + I2 = R2; + R1 = I2; + I3 = R3; + R2 = I3; + M0 = R4; + R3 = M0; + M1 = R5; + R4 = M1; + M2 = R6; + R5 = M2; + M3 = R7; + R6 = M3; + + CHECKREG r0, 0x00213330; + CHECKREG r1, 0x04015550; + CHECKREG r2, 0x06607770; + CHECKREG r3, 0x08010990; + CHECKREG r4, 0x0A01B0B0; + CHECKREG r5, 0x0C01DD00; + CHECKREG r6, 0x00001110; + CHECKREG r7, 0x00001110; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x00001110; + CHECKREG r1, 0x0C01DD00; + CHECKREG r2, 0x0A01B0B0; + CHECKREG r3, 0x08010990; + CHECKREG r4, 0x06607770; + CHECKREG r5, 0x04015550; + CHECKREG r6, 0x00213330; + CHECKREG r7, 0x00001110; + +// R-to-M,I and to P-reg: stall + imm32 i0, 0x00001111; + imm32 i1, 0x12213341; + imm32 i2, 0x14415541; + imm32 i3, 0x16617741; + imm32 m0, 0x18819941; + imm32 m1, 0x1aa1bb41; + imm32 m2, 0x1cc1dd41; + imm32 m3, 0x1ee1ff41; + M0 = R0; + R0 = M0; + M1 = R1; + P1 = M1; + M2 = R2; + P2 = M2; + M3 = R3; + P3 = M3; + I0 = R4; + P4 = I0; + I1 = R5; + P5 = I1; + I2 = R6; + SP = I2; + I3 = R7; + FP = I3; + + CHECKREG r0, 0x00001110; + CHECKREG p1, 0x0C01DD00; + CHECKREG p2, 0x0A01B0B0; + CHECKREG p3, 0x08010990; + CHECKREG p4, 0x06607770; + CHECKREG p5, 0x04015550; + CHECKREG sp, 0x00213330; + CHECKREG fp, 0x00001110; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x00001110; + CHECKREG r1, 0x0C01DD00; + CHECKREG r2, 0x0A01B0B0; + CHECKREG r3, 0x08010990; + CHECKREG r4, 0x06607770; + CHECKREG r5, 0x04015550; + CHECKREG r6, 0x00213330; + CHECKREG r7, 0x00001110; + +// R-reg to L,B-reg to R-reg: stall + imm32 r0, 0x20001112; + imm32 r1, 0x22213332; + imm32 r2, 0x21215552; + imm32 r3, 0x21627772; + imm32 r4, 0x21812992; + imm32 r5, 0x21a1b2b2; + imm32 r6, 0x21c1d222; + imm32 r7, 0x21e1ff22; + L0 = R1; + R0 = L0; + L1 = R2; + R1 = L1; + L2 = R3; + R2 = L2; + L3 = R4; + R3 = L3; + B0 = R5; + R4 = B0; + B1 = R6; + R5 = B1; + B2 = R7; + R6 = B2; + B3 = R0; + R7 = B3; + + CHECKREG r0, 0x22213332; + CHECKREG r1, 0x21215552; + CHECKREG r2, 0x21627772; + CHECKREG r3, 0x21812992; + CHECKREG r4, 0x21A1B2B2; + CHECKREG r5, 0x21C1D222; + CHECKREG r6, 0x21E1FF22; + CHECKREG r7, 0x22213332; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x21812992; + CHECKREG r1, 0x21627772; + CHECKREG r2, 0x21215552; + CHECKREG r3, 0x22213332; + CHECKREG r4, 0x22213332; + CHECKREG r5, 0x21E1FF22; + CHECKREG r6, 0x21C1D222; + CHECKREG r7, 0x21A1B2B2; + +// R-reg to L,B-reg to P-reg: stall + imm32 r0, 0x50001115; + imm32 r1, 0x51213335; + imm32 r2, 0x51415555; + imm32 r3, 0x51617775; + imm32 r4, 0x51819995; + imm32 r5, 0x51a1bbb5; + imm32 r6, 0x51c1ddd5; + imm32 r7, 0x51e1fff5; + L0 = R1; + R0 = L0; + L1 = R2; + SP = L1; + L2 = R3; + FP = L2; + L3 = R4; + P1 = L3; + B0 = R5; + P2 = B0; + B1 = R6; + P3 = B1; + B2 = R7; + P4 = B2; + B3 = R0; + P5 = B3; + + CHECKREG r0, 0x51213335; + CHECKREG p1, 0x51819995; + CHECKREG p2, 0x51A1BBB5; + CHECKREG p3, 0x51C1DDD5; + CHECKREG p4, 0x51E1FFF5; + CHECKREG p5, 0x51213335; + CHECKREG sp, 0x51415555; + CHECKREG fp, 0x51617775; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x51819995; + CHECKREG r1, 0x51617775; + CHECKREG r2, 0x51415555; + CHECKREG r3, 0x51213335; + CHECKREG r4, 0x51213335; + CHECKREG r5, 0x51E1FFF5; + CHECKREG r6, 0x51C1DDD5; + CHECKREG r7, 0x51A1BBB5; + +// R-reg to I,M-reg to L,B-reg: stall + imm32 r0, 0x00001111; + imm32 r1, 0x72213337; + imm32 r2, 0x74415557; + imm32 r3, 0x76617777; + imm32 r4, 0x78819997; + imm32 r5, 0x7aa1bbb7; + imm32 r6, 0x7cc1ddd7; + imm32 r7, 0x77e1fff7; + I0 = R0; + L0 = I0; + I1 = R1; + L1 = I1; + I2 = R2; + L2 = I2; + I3 = R3; + L3 = I3; + M0 = R4; + B0 = M0; + M1 = R5; + B1 = M1; + M2 = R6; + B2 = M2; + M3 = R7; + B3 = M3; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x76617777; + CHECKREG r1, 0x74415557; + CHECKREG r2, 0x72213337; + CHECKREG r3, 0x00001111; + CHECKREG r4, 0x77E1FFF7; + CHECKREG r5, 0x7CC1DDD7; + CHECKREG r6, 0x7AA1BBB7; + CHECKREG r7, 0x78819997; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x77E1FFF7; + CHECKREG r1, 0x7CC1DDD7; + CHECKREG r2, 0x7AA1BBB7; + CHECKREG r3, 0x78819997; + CHECKREG r4, 0x76617777; + CHECKREG r5, 0x74415557; + CHECKREG r6, 0x72213337; + CHECKREG r7, 0x00001111; + +// R-reg to L,B-reg to I,M reg: stall + imm32 r0, 0x00001111; + imm32 r1, 0x81213338; + imm32 r2, 0x81415558; + imm32 r3, 0x81617778; + imm32 r4, 0x81819998; + imm32 r5, 0x81a1bbb8; + imm32 r6, 0x81c1ddd8; + imm32 r7, 0x81e1fff8; + L0 = R0; + I0 = L0; + L1 = R1; + I1 = L1; + L2 = R2; + I2 = L2; + L3 = R3; + I3 = L3; + B0 = R4; + M0 = B0; + B1 = R5; + M1 = B1; + B2 = R6; + M2 = B2; + B3 = R7; + M3 = B3; + + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x81819998; + CHECKREG r1, 0x81A1BBB8; + CHECKREG r2, 0x81C1DDD8; + CHECKREG r3, 0x81E1FFF8; + CHECKREG r4, 0x00001111; + CHECKREG r5, 0x81213338; + CHECKREG r6, 0x81415558; + CHECKREG r7, 0x81617778; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x81617778; + CHECKREG r1, 0x81415558; + CHECKREG r2, 0x81213338; + CHECKREG r3, 0x00001111; + CHECKREG r4, 0x81E1FFF8; + CHECKREG r5, 0x81C1DDD8; + CHECKREG r6, 0x81A1BBB8; + CHECKREG r7, 0x81819998; + + pass diff --git a/sim/testsuite/bfin/c_regmv_imlb_dr.s b/sim/testsuite/bfin/c_regmv_imlb_dr.s new file mode 100644 index 0000000..ec15df0 --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_imlb_dr.s @@ -0,0 +1,313 @@ +//Original:/testcases/core/c_regmv_imlb_dr/c_regmv_imlb_dr.dsp +// Spec Reference: regmv imlb to dr +# mach: bfin + +.include "testutils.inc" + start + + + + + + +// initialize source regs +imm32 i0, 0x11111111; +imm32 i1, 0x22222222; +imm32 i2, 0x33333333; +imm32 i3, 0x44444444; + + +// i to dreg +R0 = I0; +R1 = I0; +R2 = I0; +R3 = I0; +R4 = I1; +R5 = I1; +R6 = I1; +R7 = I1; +CHECKREG r0, 0x11111111; +CHECKREG r1, 0x11111111; +CHECKREG r2, 0x11111111; +CHECKREG r3, 0x11111111; +CHECKREG r4, 0x22222222; +CHECKREG r5, 0x22222222; +CHECKREG r6, 0x22222222; +CHECKREG r7, 0x22222222; + +R0 = I1; +R1 = I1; +R2 = I1; +R3 = I1; +R4 = I0; +R5 = I0; +R6 = I0; +R7 = I0; +CHECKREG r0, 0x22222222; +CHECKREG r1, 0x22222222; +CHECKREG r2, 0x22222222; +CHECKREG r3, 0x22222222; +CHECKREG r4, 0x11111111; +CHECKREG r5, 0x11111111; +CHECKREG r6, 0x11111111; +CHECKREG r7, 0x11111111; + + +// i to dreg +R0 = I2; +R1 = I2; +R2 = I2; +R3 = I2; +R4 = I3; +R5 = I3; +R6 = I3; +R7 = I3; +CHECKREG r0, 0x33333333; +CHECKREG r1, 0x33333333; +CHECKREG r2, 0x33333333; +CHECKREG r3, 0x33333333; +CHECKREG r4, 0x44444444; +CHECKREG r5, 0x44444444; +CHECKREG r6, 0x44444444; +CHECKREG r7, 0x44444444; + +R0 = I3; +R1 = I3; +R2 = I3; +R3 = I3; +R4 = I2; +R5 = I2; +R6 = I2; +R7 = I2; +CHECKREG r0, 0x44444444; +CHECKREG r1, 0x44444444; +CHECKREG r2, 0x44444444; +CHECKREG r3, 0x44444444; +CHECKREG r4, 0x33333333; +CHECKREG r5, 0x33333333; +CHECKREG r6, 0x33333333; +CHECKREG r7, 0x33333333; + + +imm32 m0, 0x55555555; +imm32 m1, 0x66666666; +imm32 m2, 0x77777777; +imm32 m3, 0x88888888; +// m to dreg +R0 = M0; +R1 = M0; +R2 = M0; +R3 = M0; +R4 = M1; +R5 = M1; +R6 = M1; +R7 = M1; +CHECKREG r0, 0x55555555; +CHECKREG r1, 0x55555555; +CHECKREG r2, 0x55555555; +CHECKREG r3, 0x55555555; +CHECKREG r4, 0x66666666; +CHECKREG r5, 0x66666666; +CHECKREG r6, 0x66666666; +CHECKREG r7, 0x66666666; + +R0 = M1; +R1 = M1; +R2 = M1; +R3 = M1; +R4 = M0; +R5 = M0; +R6 = M0; +R7 = M0; +CHECKREG r0, 0x66666666; +CHECKREG r1, 0x66666666; +CHECKREG r2, 0x66666666; +CHECKREG r3, 0x66666666; +CHECKREG r4, 0x55555555; +CHECKREG r5, 0x55555555; +CHECKREG r6, 0x55555555; +CHECKREG r7, 0x55555555; + +R0 = M2; +R1 = M2; +R2 = M2; +R3 = M2; +R4 = M3; +R5 = M3; +R6 = M3; +R7 = M3; +CHECKREG r0, 0x77777777; +CHECKREG r1, 0x77777777; +CHECKREG r2, 0x77777777; +CHECKREG r3, 0x77777777; +CHECKREG r4, 0x88888888; +CHECKREG r5, 0x88888888; +CHECKREG r6, 0x88888888; +CHECKREG r7, 0x88888888; + +R0 = M3; +R1 = M3; +R2 = M3; +R3 = M3; +R4 = M2; +R5 = M2; +R6 = M2; +R7 = M2; +CHECKREG r0, 0x88888888; +CHECKREG r1, 0x88888888; +CHECKREG r2, 0x88888888; +CHECKREG r3, 0x88888888; +CHECKREG r4, 0x77777777; +CHECKREG r5, 0x77777777; +CHECKREG r6, 0x77777777; +CHECKREG r7, 0x77777777; + +imm32 l0, 0x99999999; +imm32 l1, 0xaaaaaaaa; +imm32 l2, 0xbbbbbbbb; +imm32 l3, 0xcccccccc; +// l to dreg +R0 = L0; +R1 = L0; +R2 = L0; +R3 = L0; +R4 = L1; +R5 = L1; +R6 = L1; +R7 = L1; +CHECKREG r0, 0x99999999; +CHECKREG r1, 0x99999999; +CHECKREG r2, 0x99999999; +CHECKREG r3, 0x99999999; +CHECKREG r4, 0xaaaaaaaa; +CHECKREG r5, 0xaaaaaaaa; +CHECKREG r6, 0xaaaaaaaa; +CHECKREG r7, 0xaaaaaaaa; + +R0 = L1; +R1 = L1; +R2 = L1; +R3 = L1; +R4 = L0; +R5 = L0; +R6 = L0; +R7 = L0; +CHECKREG r0, 0xaaaaaaaa; +CHECKREG r1, 0xaaaaaaaa; +CHECKREG r2, 0xaaaaaaaa; +CHECKREG r3, 0xaaaaaaaa; +CHECKREG r4, 0x99999999; +CHECKREG r5, 0x99999999; +CHECKREG r6, 0x99999999; +CHECKREG r7, 0x99999999; + + +R0 = L2; +R1 = L2; +R2 = L2; +R3 = L2; +R4 = L3; +R5 = L3; +R6 = L3; +R7 = L3; +CHECKREG r0, 0xbbbbbbbb; +CHECKREG r1, 0xbbbbbbbb; +CHECKREG r2, 0xbbbbbbbb; +CHECKREG r3, 0xbbbbbbbb; +CHECKREG r4, 0xcccccccc; +CHECKREG r5, 0xcccccccc; +CHECKREG r6, 0xcccccccc; +CHECKREG r7, 0xcccccccc; + +R0 = L3; +R1 = L3; +R2 = L3; +R3 = L3; +R4 = L2; +R5 = L2; +R6 = L2; +R7 = L2; +CHECKREG r0, 0xcccccccc; +CHECKREG r1, 0xcccccccc; +CHECKREG r2, 0xcccccccc; +CHECKREG r3, 0xcccccccc; +CHECKREG r4, 0xbbbbbbbb; +CHECKREG r5, 0xbbbbbbbb; +CHECKREG r6, 0xbbbbbbbb; +CHECKREG r7, 0xbbbbbbbb; + + +imm32 b0, 0xdddddddd; +imm32 b1, 0xeeeeeeee; +imm32 b2, 0xffffffff; +imm32 b3, 0x12345678; +// b to dreg +R0 = B0; +R1 = B0; +R2 = B0; +R3 = B0; +R4 = B1; +R5 = B1; +R6 = B1; +R7 = B1; +CHECKREG r0, 0xdddddddd; +CHECKREG r1, 0xdddddddd; +CHECKREG r2, 0xdddddddd; +CHECKREG r3, 0xdddddddd; +CHECKREG r4, 0xeeeeeeee; +CHECKREG r5, 0xeeeeeeee; +CHECKREG r6, 0xeeeeeeee; +CHECKREG r7, 0xeeeeeeee; + +R0 = B1; +R1 = B1; +R2 = B1; +R3 = B1; +R4 = B0; +R5 = B0; +R6 = B0; +R7 = B0; +CHECKREG r0, 0xeeeeeeee; +CHECKREG r1, 0xeeeeeeee; +CHECKREG r2, 0xeeeeeeee; +CHECKREG r3, 0xeeeeeeee; +CHECKREG r4, 0xdddddddd; +CHECKREG r5, 0xdddddddd; +CHECKREG r6, 0xdddddddd; +CHECKREG r7, 0xdddddddd; + +R0 = B2; +R1 = B2; +R2 = B2; +R3 = B2; +R4 = B3; +R5 = B3; +R6 = B3; +R7 = B3; +CHECKREG r0, 0xffffffff; +CHECKREG r1, 0xffffffff; +CHECKREG r2, 0xffffffff; +CHECKREG r3, 0xffffffff; +CHECKREG r4, 0x12345678; +CHECKREG r5, 0x12345678; +CHECKREG r6, 0x12345678; +CHECKREG r7, 0x12345678; + +R0 = B3; +R1 = B3; +R2 = B3; +R3 = B3; +R4 = B2; +R5 = B2; +R6 = B2; +R7 = B2; +CHECKREG r0, 0x12345678; +CHECKREG r1, 0x12345678; +CHECKREG r2, 0x12345678; +CHECKREG r3, 0x12345678; +CHECKREG r4, 0xffffffff; +CHECKREG r5, 0xffffffff; +CHECKREG r6, 0xffffffff; +CHECKREG r7, 0xffffffff; + +pass diff --git a/sim/testsuite/bfin/c_regmv_imlb_imlb.s b/sim/testsuite/bfin/c_regmv_imlb_imlb.s new file mode 100644 index 0000000..35146ec --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_imlb_imlb.s @@ -0,0 +1,925 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_imlb/c_regmv_imlb_imlb.dsp +// Spec Reference: regmv imlb-imlb +# mach: bfin + +.include "testutils.inc" + start + +// initialize source regs + imm32 i0, 0x11111111; + imm32 i1, 0x22222222; + imm32 i2, 0x33333333; + imm32 i3, 0x44444444; + imm32 m0, 0x55555555; + imm32 m1, 0x66666666; + imm32 m2, 0x77777777; + imm32 m3, 0x88888888; + imm32 l0, 0x99999999; + imm32 l1, 0xAAAAAAAA; + imm32 l2, 0xBBBBBBBB; + imm32 l3, 0xCCCCCCCC; + imm32 b0, 0xDDDDDDDD; + imm32 b1, 0xEEEEEEEE; + imm32 b2, 0xFFFFFFFF; + imm32 b3, 0x12345667; + +//*******************i-i & m-m, i-m & m-i, l-l & b-b, l-b & b-l +// i to i & m to m + I0 = I0; + I1 = I1; + I2 = I2; + I3 = I3; + M0 = M0; + M1 = M1; + M2 = M2; + M3 = M3; + + I0 = I1; + I1 = I2; + I2 = I3; + I3 = I0; + M0 = M1; + M1 = M2; + M2 = M3; + M3 = M0; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x22222222; + CHECKREG r1, 0x33333333; + CHECKREG r2, 0x44444444; + CHECKREG r3, 0x22222222; + CHECKREG r4, 0x66666666; + CHECKREG r5, 0x77777777; + CHECKREG r6, 0x88888888; + CHECKREG r7, 0x66666666; + + I0 = I2; + I1 = I3; + I2 = I0; + I3 = I1; + M0 = M2; + M1 = M3; + M2 = M0; + M3 = M1; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x44444444; + CHECKREG r1, 0x22222222; + CHECKREG r2, 0x44444444; + CHECKREG r3, 0x22222222; + CHECKREG r4, 0x88888888; + CHECKREG r5, 0x66666666; + CHECKREG r6, 0x88888888; + CHECKREG r7, 0x66666666; + + I0 = I3; + I1 = I0; + I2 = I1; + I3 = I2; + M0 = M3; + M1 = M0; + M2 = M1; + M3 = M2; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x22222222; + CHECKREG r1, 0x22222222; + CHECKREG r2, 0x22222222; + CHECKREG r3, 0x22222222; + CHECKREG r4, 0x66666666; + CHECKREG r5, 0x66666666; + CHECKREG r6, 0x66666666; + CHECKREG r7, 0x66666666; + + imm32 i0, 0xa1111110; + imm32 i1, 0xb2222220; + imm32 i2, 0xc3333330; + imm32 i3, 0xd4444440; + imm32 m0, 0xe5555550; + imm32 m1, 0xf6666660; + imm32 m2, 0x17777770; + imm32 m3, 0x28888888; + +// m to i & i to m + I0 = M0; + I1 = M1; + I2 = M2; + I3 = M3; + M0 = I0; + M1 = I1; + M2 = I2; + M3 = I3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xE5555550; + CHECKREG r1, 0xF6666660; + CHECKREG r2, 0x17777770; + CHECKREG r3, 0x28888888; + CHECKREG r4, 0xE5555550; + CHECKREG r5, 0xF6666660; + CHECKREG r6, 0x17777770; + CHECKREG r7, 0x28888888; + + I0 = M1; + I1 = M2; + I2 = M3; + I3 = M0; + M0 = I1; + M1 = I2; + M2 = I3; + M3 = I0; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xF6666660; + CHECKREG r1, 0x17777770; + CHECKREG r2, 0x28888888; + CHECKREG r3, 0xE5555550; + CHECKREG r4, 0x17777770; + CHECKREG r5, 0x28888888; + CHECKREG r6, 0xE5555550; + CHECKREG r7, 0xF6666660; + + I0 = M2; + I1 = M3; + I2 = M0; + I3 = M1; + M0 = I2; + M1 = I3; + M2 = I0; + M3 = I1; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xE5555550; + CHECKREG r1, 0xF6666660; + CHECKREG r2, 0x17777770; + CHECKREG r3, 0x28888888; + CHECKREG r4, 0x17777770; + CHECKREG r5, 0x28888888; + CHECKREG r6, 0xE5555550; + CHECKREG r7, 0xF6666660; + + I0 = M3; + I1 = M0; + I2 = M1; + I3 = M2; + M0 = I3; + M1 = I0; + M2 = I1; + M3 = I2; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xF6666660; + CHECKREG r1, 0x17777770; + CHECKREG r2, 0x28888888; + CHECKREG r3, 0xE5555550; + CHECKREG r4, 0xE5555550; + CHECKREG r5, 0xF6666660; + CHECKREG r6, 0x17777770; + CHECKREG r7, 0x28888888; + +// l to l & b to b + L0 = L0; + L1 = L1; + L2 = L2; + L3 = L3; + B0 = B0; + B1 = B1; + B2 = B2; + B3 = B3; + + L0 = L1; + L1 = L2; + L2 = L3; + L3 = L0; + B0 = B1; + B1 = B2; + B2 = B3; + B3 = B0; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0xAAAAAAAA; + CHECKREG r1, 0xBBBBBBBB; + CHECKREG r2, 0xCCCCCCCC; + CHECKREG r3, 0xAAAAAAAA; + CHECKREG r4, 0xEEEEEEEE; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0x12345667; + CHECKREG r7, 0xEEEEEEEE; + + L0 = L2; + L1 = L3; + L2 = L0; + L3 = L1; + B0 = B2; + B1 = B3; + B2 = B0; + B3 = B1; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0xCCCCCCCC; + CHECKREG r1, 0xAAAAAAAA; + CHECKREG r2, 0xCCCCCCCC; + CHECKREG r3, 0xAAAAAAAA; + CHECKREG r4, 0x12345667; + CHECKREG r5, 0xEEEEEEEE; + CHECKREG r6, 0x12345667; + CHECKREG r7, 0xEEEEEEEE; + + imm32 l0, 0x09499091; + imm32 l1, 0x0A55A0A2; + imm32 l2, 0x0B6BB0B3; + imm32 l3, 0x0C7CC0C4; + imm32 b0, 0x0D8DD0D5; + imm32 b1, 0x0E9EE0E6; + imm32 b2, 0x0F0FF0F7; + imm32 b3, 0x12145068; + + L0 = L3; + L1 = L0; + L2 = L1; + L3 = L2; + B0 = B3; + B1 = B0; + B2 = B1; + B3 = B2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x0C7CC0C4; + CHECKREG r1, 0x0C7CC0C4; + CHECKREG r2, 0x0C7CC0C4; + CHECKREG r3, 0x0C7CC0C4; + CHECKREG r4, 0x12145068; + CHECKREG r5, 0x12145068; + CHECKREG r6, 0x12145068; + CHECKREG r7, 0x12145068; + +// b to l & l to b + L0 = B0; + L1 = B1; + L2 = B2; + L3 = B3; + B0 = L0; + B1 = L1; + B2 = L2; + B3 = L3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xF6666660; + CHECKREG r1, 0x17777770; + CHECKREG r2, 0x28888888; + CHECKREG r3, 0xE5555550; + CHECKREG r4, 0xE5555550; + CHECKREG r5, 0xF6666660; + CHECKREG r6, 0x17777770; + CHECKREG r7, 0x28888888; + + imm32 l0, 0x01909910; + imm32 l1, 0x12A11220; + imm32 l2, 0x23B25530; + imm32 l3, 0x34C36640; + imm32 b0, 0x45D47750; + imm32 b1, 0x56E58860; + imm32 b2, 0x67F66676; + imm32 b3, 0x78375680; + + L0 = B1; + L1 = B2; + L2 = B3; + L3 = B0; + B0 = L1; + B1 = L2; + B2 = L3; + B3 = L0; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x56E58860; + CHECKREG r1, 0x67F66676; + CHECKREG r2, 0x78375680; + CHECKREG r3, 0x45D47750; + CHECKREG r4, 0x67F66676; + CHECKREG r5, 0x78375680; + CHECKREG r6, 0x45D47750; + CHECKREG r7, 0x56E58860; + + imm32 l0, 0x09909990; + imm32 l1, 0x1AA11230; + imm32 l2, 0x2BB25550; + imm32 l3, 0x3CC36660; + imm32 b0, 0x4DD47770; + imm32 b1, 0x5EE58880; + imm32 b2, 0x6FF66666; + imm32 b3, 0x72375660; + + L0 = B2; + L1 = B3; + L2 = B0; + L3 = B1; + B0 = L2; + B1 = L3; + B2 = L0; + B3 = L1; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x6FF66666; + CHECKREG r1, 0x72375660; + CHECKREG r2, 0x4DD47770; + CHECKREG r3, 0x5EE58880; + CHECKREG r4, 0x4DD47770; + CHECKREG r5, 0x5EE58880; + CHECKREG r6, 0x6FF66666; + CHECKREG r7, 0x72375660; + + L0 = B3; + L1 = B0; + L2 = B1; + L3 = B2; + B0 = L3; + B1 = L0; + B2 = L1; + B3 = L2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x72375660; + CHECKREG r1, 0x4DD47770; + CHECKREG r2, 0x5EE58880; + CHECKREG r3, 0x6FF66666; + CHECKREG r4, 0x6FF66666; + CHECKREG r5, 0x72375660; + CHECKREG r6, 0x4DD47770; + CHECKREG r7, 0x5EE58880; + + imm32 l0, 0x09999990; + imm32 l1, 0x1AAAAAA0; + imm32 l2, 0x2BBBBBB0; + imm32 l3, 0x3CCCCCC0; + imm32 b0, 0x4DDDDDD0; + imm32 b1, 0x5EEEEEE0; + imm32 b2, 0x6FFFFFF0; + imm32 b3, 0x72345660; + +//*******************l-i & l-m, b-i & b-m, i-l & i-b, m-l & m-b +// l to i & l to m + I0 = L0; + I1 = L1; + I2 = L2; + I3 = L3; + M0 = L0; + M1 = L1; + M2 = L2; + M3 = L3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x09999990; + CHECKREG r1, 0x1AAAAAA0; + CHECKREG r2, 0x2BBBBBB0; + CHECKREG r3, 0x3CCCCCC0; + CHECKREG r4, 0x09999990; + CHECKREG r5, 0x1AAAAAA0; + CHECKREG r6, 0x2BBBBBB0; + CHECKREG r7, 0x3CCCCCC0; + + I0 = L1; + I1 = L2; + I2 = L3; + I3 = L0; + M0 = L1; + M1 = L2; + M2 = L3; + M3 = L0; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x1AAAAAA0; + CHECKREG r1, 0x2BBBBBB0; + CHECKREG r2, 0x3CCCCCC0; + CHECKREG r3, 0x09999990; + CHECKREG r4, 0x1AAAAAA0; + CHECKREG r5, 0x2BBBBBB0; + CHECKREG r6, 0x3CCCCCC0; + CHECKREG r7, 0x09999990; + + I0 = L2; + I1 = L3; + I2 = L0; + I3 = L1; + M0 = L2; + M1 = L3; + M2 = L0; + M3 = L1; + + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x1AAAAAA0; + CHECKREG r1, 0x2BBBBBB0; + CHECKREG r2, 0x3CCCCCC0; + CHECKREG r3, 0x09999990; + CHECKREG r4, 0x2BBBBBB0; + CHECKREG r5, 0x3CCCCCC0; + CHECKREG r6, 0x09999990; + CHECKREG r7, 0x1AAAAAA0; + + I0 = L3; + I1 = L0; + I2 = L1; + I3 = L2; + M0 = L3; + M1 = L0; + M2 = L1; + M3 = L2; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x3CCCCCC0; + CHECKREG r1, 0x09999990; + CHECKREG r2, 0x1AAAAAA0; + CHECKREG r3, 0x2BBBBBB0; + CHECKREG r4, 0x3CCCCCC0; + CHECKREG r5, 0x09999990; + CHECKREG r6, 0x1AAAAAA0; + CHECKREG r7, 0x2BBBBBB0; + +// b to i & b to m + I0 = B0; + I1 = B1; + I2 = B2; + I3 = B3; + M0 = B0; + M1 = B1; + M2 = B2; + M3 = B3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x4DDDDDD0; + CHECKREG r1, 0x5EEEEEE0; + CHECKREG r2, 0x6FFFFFF0; + CHECKREG r3, 0x72345660; + CHECKREG r4, 0x4DDDDDD0; + CHECKREG r5, 0x5EEEEEE0; + CHECKREG r6, 0x6FFFFFF0; + CHECKREG r7, 0x72345660; + + I0 = B1; + I1 = B2; + I2 = B3; + I3 = B0; + M0 = B1; + M1 = B2; + M2 = B3; + M3 = B0; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x5EEEEEE0; + CHECKREG r1, 0x6FFFFFF0; + CHECKREG r2, 0x72345660; + CHECKREG r3, 0x4DDDDDD0; + CHECKREG r4, 0x5EEEEEE0; + CHECKREG r5, 0x6FFFFFF0; + CHECKREG r6, 0x72345660; + CHECKREG r7, 0x4DDDDDD0; + + I0 = B2; + I1 = B3; + I2 = B0; + I3 = B1; + M0 = B2; + M1 = B3; + M2 = B0; + M3 = B1; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x6FFFFFF0; + CHECKREG r1, 0x72345660; + CHECKREG r2, 0x4DDDDDD0; + CHECKREG r3, 0x5EEEEEE0; + CHECKREG r4, 0x6FFFFFF0; + CHECKREG r5, 0x72345660; + CHECKREG r6, 0x4DDDDDD0; + CHECKREG r7, 0x5EEEEEE0; + + I0 = B3; + I1 = B0; + I2 = B1; + I3 = B2; + M0 = B3; + M1 = B0; + M2 = B1; + M3 = B2; + + P1 = I1; + P2 = I2; + P3 = I3; + P4 = M0; + P5 = M1; + FP = M2; + SP = M3; + + CHECKREG p1, 0x4DDDDDD0; + CHECKREG p2, 0x5EEEEEE0; + CHECKREG p3, 0x6FFFFFF0; + CHECKREG p4, 0x72345660; + CHECKREG p5, 0x4DDDDDD0; + CHECKREG fp, 0x5EEEEEE0; + CHECKREG sp, 0x6FFFFFF0; + +// i to l & i to b + imm32 i0, 0x09999990; + imm32 i1, 0x1AAAAAA0; + imm32 i2, 0x2BBBBBB0; + imm32 i3, 0x3CCCCCC0; + + L0 = I0; + L1 = I1; + L2 = I2; + L3 = I3; + B0 = I0; + B1 = I1; + B2 = I2; + B3 = I3; + + L0 = I1; + L1 = I2; + L2 = I3; + L3 = I0; + B0 = I1; + B1 = I2; + B2 = I3; + B3 = I0; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x1AAAAAA0; + CHECKREG r1, 0x2BBBBBB0; + CHECKREG r2, 0x3CCCCCC0; + CHECKREG r3, 0x09999990; + CHECKREG r4, 0x1AAAAAA0; + CHECKREG r5, 0x2BBBBBB0; + CHECKREG r6, 0x3CCCCCC0; + CHECKREG r7, 0x09999990; + + L0 = I2; + L1 = I3; + L2 = I0; + L3 = I1; + B0 = I2; + B1 = I3; + B2 = I0; + B3 = I1; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x2BBBBBB0; + CHECKREG r1, 0x3CCCCCC0; + CHECKREG r2, 0x09999990; + CHECKREG r3, 0x1AAAAAA0; + CHECKREG r4, 0x2BBBBBB0; + CHECKREG r5, 0x3CCCCCC0; + CHECKREG r6, 0x09999990; + CHECKREG r7, 0x1AAAAAA0; + + imm32 l0, 0x09499091; + imm32 l1, 0x0A55A0A2; + imm32 l2, 0x0B6BB0B3; + imm32 l3, 0x0C7CC0C4; + imm32 b0, 0x0D8DD0D5; + imm32 b1, 0x0E9EE0E6; + imm32 b2, 0x0F0FF0F7; + imm32 b3, 0x12145068; + + L0 = I3; + L1 = I0; + L2 = I1; + L3 = I2; + B0 = I3; + B1 = I0; + B2 = I1; + B3 = I2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x3CCCCCC0; + CHECKREG r1, 0x09999990; + CHECKREG r2, 0x1AAAAAA0; + CHECKREG r3, 0x2BBBBBB0; + CHECKREG r4, 0x3CCCCCC0; + CHECKREG r5, 0x09999990; + CHECKREG r6, 0x1AAAAAA0; + CHECKREG r7, 0x2BBBBBB0; + +// m to l & m to b + imm32 m0, 0x4DDDDDD0; + imm32 m1, 0x5EEEEEE0; + imm32 m2, 0x6FFFFFF0; + imm32 m3, 0x72345660; + L0 = M0; + L1 = M1; + L2 = M2; + L3 = M3; + B0 = M0; + B1 = M1; + B2 = M2; + B3 = M3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x09999990; + CHECKREG r1, 0x1AAAAAA0; + CHECKREG r2, 0x2BBBBBB0; + CHECKREG r3, 0x3CCCCCC0; + CHECKREG r4, 0x4DDDDDD0; + CHECKREG r5, 0x5EEEEEE0; + CHECKREG r6, 0x6FFFFFF0; + CHECKREG r7, 0x72345660; + + imm32 l0, 0x01909910; + imm32 l1, 0x12A11220; + imm32 l2, 0x23B25530; + imm32 l3, 0x34C36640; + imm32 b0, 0x45D47750; + imm32 b1, 0x56E58860; + imm32 b2, 0x67F66676; + imm32 b3, 0x78375680; + + L0 = M1; + L1 = M2; + L2 = M3; + L3 = M0; + B0 = M1; + B1 = M2; + B2 = M3; + B3 = M0; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x5EEEEEE0; + CHECKREG r1, 0x6FFFFFF0; + CHECKREG r2, 0x72345660; + CHECKREG r3, 0x4DDDDDD0; + CHECKREG r4, 0x5EEEEEE0; + CHECKREG r5, 0x6FFFFFF0; + CHECKREG r6, 0x72345660; + CHECKREG r7, 0x4DDDDDD0; + + imm32 l0, 0x09909990; + imm32 l1, 0x1AA11230; + imm32 l2, 0x2BB25550; + imm32 l3, 0x3CC36660; + imm32 b0, 0x4DD47770; + imm32 b1, 0x5EE58880; + imm32 b2, 0x6FF66666; + imm32 b3, 0x72375660; + + L0 = M2; + L1 = M3; + L2 = M0; + L3 = M1; + B0 = M2; + B1 = M3; + B2 = M0; + B3 = M1; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x6FFFFFF0; + CHECKREG r1, 0x72345660; + CHECKREG r2, 0x4DDDDDD0; + CHECKREG r3, 0x5EEEEEE0; + CHECKREG r4, 0x6FFFFFF0; + CHECKREG r5, 0x72345660; + CHECKREG r6, 0x4DDDDDD0; + CHECKREG r7, 0x5EEEEEE0; + + L0 = M3; + L1 = M0; + L2 = M1; + L3 = M2; + B0 = M3; + B1 = M0; + B2 = M1; + B3 = M2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x72345660; + CHECKREG r1, 0x4DDDDDD0; + CHECKREG r2, 0x5EEEEEE0; + CHECKREG r3, 0x6FFFFFF0; + CHECKREG r4, 0x72345660; + CHECKREG r5, 0x4DDDDDD0; + CHECKREG r6, 0x5EEEEEE0; + CHECKREG r7, 0x6FFFFFF0; + + pass diff --git a/sim/testsuite/bfin/c_regmv_imlb_pr.s b/sim/testsuite/bfin/c_regmv_imlb_pr.s new file mode 100644 index 0000000..7e32a29 --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_imlb_pr.s @@ -0,0 +1,302 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_pr/c_regmv_imlb_pr.dsp +// Spec Reference: regmv imlb to dr +# mach: bfin + +.include "testutils.inc" + start + +// initialize source regs + imm32 i0, 0x11111111; + imm32 i1, 0x22222222; + imm32 i2, 0x33333333; + imm32 i3, 0x44444444; + +// i to preg + R0 = I0; + P1 = I0; + P2 = I0; + P3 = I0; + P4 = I1; + P5 = I1; + SP = I1; + FP = I1; + CHECKREG r0, 0x11111111; + CHECKREG p1, 0x11111111; + CHECKREG p2, 0x11111111; + CHECKREG p3, 0x11111111; + CHECKREG p4, 0x22222222; + CHECKREG p5, 0x22222222; + CHECKREG sp, 0x22222222; + CHECKREG fp, 0x22222222; + + R0 = I1; + P1 = I1; + P2 = I1; + P3 = I1; + P4 = I0; + P5 = I0; + SP = I0; + FP = I0; + CHECKREG r0, 0x22222222; + CHECKREG p1, 0x22222222; + CHECKREG p2, 0x22222222; + CHECKREG p3, 0x22222222; + CHECKREG p4, 0x11111111; + CHECKREG p5, 0x11111111; + CHECKREG sp, 0x11111111; + CHECKREG fp, 0x11111111; + + R0 = I2; + P1 = I2; + P2 = I2; + P3 = I2; + P4 = I3; + P5 = I3; + SP = I3; + FP = I3; + CHECKREG r0, 0x33333333; + CHECKREG p1, 0x33333333; + CHECKREG p2, 0x33333333; + CHECKREG p3, 0x33333333; + CHECKREG p4, 0x44444444; + CHECKREG p5, 0x44444444; + CHECKREG sp, 0x44444444; + CHECKREG fp, 0x44444444; + + R0 = I3; + P1 = I3; + P2 = I3; + P3 = I3; + P4 = I2; + P5 = I2; + SP = I2; + FP = I2; + CHECKREG r0, 0x44444444; + CHECKREG p1, 0x44444444; + CHECKREG p2, 0x44444444; + CHECKREG p3, 0x44444444; + CHECKREG p4, 0x33333333; + CHECKREG p5, 0x33333333; + CHECKREG sp, 0x33333333; + CHECKREG fp, 0x33333333; + + imm32 m0, 0x55555555; + imm32 m1, 0x66666666; + imm32 m2, 0x77777777; + imm32 m3, 0x88888888; +// m to preg + R0 = M0; + P1 = M0; + P2 = M0; + P3 = M0; + P4 = M1; + P5 = M1; + SP = M1; + FP = M1; + CHECKREG r0, 0x55555555; + CHECKREG p1, 0x55555555; + CHECKREG p2, 0x55555555; + CHECKREG p3, 0x55555555; + CHECKREG p4, 0x66666666; + CHECKREG p5, 0x66666666; + CHECKREG sp, 0x66666666; + CHECKREG fp, 0x66666666; + + R0 = M1; + P1 = M1; + P2 = M1; + P3 = M1; + P4 = M0; + P5 = M0; + SP = M0; + FP = M0; + CHECKREG r0, 0x66666666; + CHECKREG p1, 0x66666666; + CHECKREG p2, 0x66666666; + CHECKREG p3, 0x66666666; + CHECKREG p4, 0x55555555; + CHECKREG p5, 0x55555555; + CHECKREG sp, 0x55555555; + CHECKREG fp, 0x55555555; + + R0 = M2; + P1 = M2; + P2 = M2; + P3 = M2; + P4 = M3; + P5 = M3; + SP = M3; + FP = M3; + CHECKREG r0, 0x77777777; + CHECKREG p1, 0x77777777; + CHECKREG p2, 0x77777777; + CHECKREG p3, 0x77777777; + CHECKREG p4, 0x88888888; + CHECKREG p5, 0x88888888; + CHECKREG sp, 0x88888888; + CHECKREG fp, 0x88888888; + + R0 = M3; + P1 = M3; + P2 = M3; + P3 = M3; + P4 = M2; + P5 = M2; + SP = M2; + FP = M2; + CHECKREG r0, 0x88888888; + CHECKREG p1, 0x88888888; + CHECKREG p2, 0x88888888; + CHECKREG p3, 0x88888888; + CHECKREG p4, 0x77777777; + CHECKREG p5, 0x77777777; + CHECKREG sp, 0x77777777; + CHECKREG fp, 0x77777777; + + imm32 l0, 0x99999999; + imm32 l1, 0xaaaaaaaa; + imm32 l2, 0xbbbbbbbb; + imm32 l3, 0xcccccccc; +// l to preg + R0 = L0; + P1 = L0; + P2 = L0; + P3 = L0; + P4 = L1; + P5 = L1; + SP = L1; + FP = L1; + CHECKREG r0, 0x99999999; + CHECKREG p1, 0x99999999; + CHECKREG p2, 0x99999999; + CHECKREG p3, 0x99999999; + CHECKREG p4, 0xaaaaaaaa; + CHECKREG p5, 0xaaaaaaaa; + CHECKREG sp, 0xaaaaaaaa; + CHECKREG fp, 0xaaaaaaaa; + + R0 = L1; + P1 = L1; + P2 = L1; + P3 = L1; + P4 = L0; + P5 = L0; + SP = L0; + FP = L0; + CHECKREG r0, 0xaaaaaaaa; + CHECKREG p1, 0xaaaaaaaa; + CHECKREG p2, 0xaaaaaaaa; + CHECKREG p3, 0xaaaaaaaa; + CHECKREG p4, 0x99999999; + CHECKREG p5, 0x99999999; + CHECKREG sp, 0x99999999; + CHECKREG fp, 0x99999999; + + R0 = L2; + P1 = L2; + P2 = L2; + P3 = L2; + P4 = L3; + P5 = L3; + SP = L3; + FP = L3; + CHECKREG r0, 0xbbbbbbbb; + CHECKREG p1, 0xbbbbbbbb; + CHECKREG p2, 0xbbbbbbbb; + CHECKREG p3, 0xbbbbbbbb; + CHECKREG p4, 0xcccccccc; + CHECKREG p5, 0xcccccccc; + CHECKREG sp, 0xcccccccc; + CHECKREG fp, 0xcccccccc; + + R0 = L3; + P1 = L3; + P2 = L3; + P3 = L3; + P4 = L2; + P5 = L2; + SP = L2; + FP = L2; + CHECKREG r0, 0xcccccccc; + CHECKREG p1, 0xcccccccc; + CHECKREG p2, 0xcccccccc; + CHECKREG p3, 0xcccccccc; + CHECKREG p4, 0xbbbbbbbb; + CHECKREG p5, 0xbbbbbbbb; + CHECKREG sp, 0xbbbbbbbb; + CHECKREG fp, 0xbbbbbbbb; + + imm32 b0, 0xdddddddd; + imm32 b1, 0xeeeeeeee; + imm32 b2, 0xffffffff; + imm32 b3, 0x12345678; +// b to preg + R0 = B0; + P1 = B0; + P2 = B0; + P3 = B0; + P4 = B1; + P5 = B1; + SP = B1; + FP = B1; + CHECKREG r0, 0xdddddddd; + CHECKREG p1, 0xdddddddd; + CHECKREG p2, 0xdddddddd; + CHECKREG p3, 0xdddddddd; + CHECKREG p4, 0xeeeeeeee; + CHECKREG p5, 0xeeeeeeee; + CHECKREG sp, 0xeeeeeeee; + CHECKREG fp, 0xeeeeeeee; + + R0 = B1; + P1 = B1; + P2 = B1; + P3 = B1; + P4 = B0; + P5 = B0; + SP = B0; + FP = B0; + CHECKREG r0, 0xeeeeeeee; + CHECKREG p1, 0xeeeeeeee; + CHECKREG p2, 0xeeeeeeee; + CHECKREG p3, 0xeeeeeeee; + CHECKREG p4, 0xdddddddd; + CHECKREG p5, 0xdddddddd; + CHECKREG sp, 0xdddddddd; + CHECKREG fp, 0xdddddddd; + + R0 = B2; + P1 = B2; + P2 = B2; + P3 = B2; + P4 = B3; + P5 = B3; + SP = B3; + FP = B3; + CHECKREG r0, 0xffffffff; + CHECKREG p1, 0xffffffff; + CHECKREG p2, 0xffffffff; + CHECKREG p3, 0xffffffff; + CHECKREG p4, 0x12345678; + CHECKREG p5, 0x12345678; + CHECKREG sp, 0x12345678; + CHECKREG fp, 0x12345678; + + R0 = B3; + P1 = B3; + P2 = B3; + P3 = B3; + P4 = B2; + P5 = B2; + SP = B2; + FP = B2; + CHECKREG r0, 0x12345678; + CHECKREG p1, 0x12345678; + CHECKREG p2, 0x12345678; + CHECKREG p3, 0x12345678; + CHECKREG p4, 0xffffffff; + CHECKREG p5, 0xffffffff; + CHECKREG sp, 0xffffffff; + CHECKREG fp, 0xffffffff; + + pass diff --git a/sim/testsuite/bfin/c_regmv_pr_dep_nostall.s b/sim/testsuite/bfin/c_regmv_pr_dep_nostall.s new file mode 100644 index 0000000..5525bea --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_pr_dep_nostall.s @@ -0,0 +1,280 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_nostall/c_regmv_pr_dep_nostall.dsp +// Spec Reference: regmv pr-dep no stall +# mach: bfin + +.include "testutils.inc" + start + +//imm32 p0, 0x00001111; + imm32 p1, 0x32213330; + imm32 p2, 0x34415550; + imm32 p3, 0x36617770; + imm32 p4, 0x38819990; + imm32 p5, 0x3aa1bbb0; + imm32 fp, 0x3cc1ddd0; + imm32 sp, 0x3ee1fff0; +// P-reg to P-reg to R-reg: no stall + P4 = P1; + R1 = P4; + SP = P5; + R2 = SP; + P1 = FP; + R3 = P1; + CHECKREG r1, 0x32213330; + CHECKREG r2, 0x3AA1BBB0; + CHECKREG r3, 0x3CC1DDD0; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22213332; + imm32 p2, 0x44415552; + imm32 p3, 0x66617772; + imm32 p4, 0x88819992; + imm32 p5, 0xaaa1bbb2; + imm32 fp, 0xccc1ddd2; + imm32 sp, 0xeee1fff2; + +// P-reg to P-reg to I reg: no stall + P1 = P2; + I0 = P1; + P3 = P2; + I1 = P3; + P5 = P4; + I2 = P5; + FP = SP; + I3 = FP; + + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r4, 0xEEE1FFF2; + CHECKREG r5, 0x88819992; + CHECKREG r6, 0x44415552; + CHECKREG r7, 0x44415552; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22213332; + imm32 p2, 0x44415552; + imm32 p3, 0x66617772; + imm32 p4, 0x88819992; + imm32 p5, 0xaaa1bbb2; + imm32 fp, 0xccc1ddd2; + imm32 sp, 0xe111fff2; + +// P-reg to P-reg to M reg: no stall + P1 = P4; + M0 = P1; + P3 = P2; + M1 = P3; + P5 = P4; + M2 = P5; + FP = SP; + M3 = FP; + + R4 = M3; + R5 = M2; + R6 = M1; + R7 = M0; + CHECKREG r4, 0xE111FFF2; + CHECKREG r5, 0x88819992; + CHECKREG r6, 0x44415552; + CHECKREG r7, 0x88819992; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22213332; + imm32 p2, 0x44215552; + imm32 p3, 0x66217772; + imm32 p4, 0x88219992; + imm32 p5, 0xaa21bbb2; + imm32 fp, 0xcc21ddd2; + imm32 sp, 0xee21fff2; + +// P-reg to P-reg to L reg: no stall + P1 = P0; + L0 = P1; + P3 = P2; + L1 = P3; + P5 = P4; + L2 = P5; + FP = SP; + L3 = FP; + + R4 = L3; + R5 = L2; + R6 = L1; + R7 = L0; + CHECKREG r4, 0xEE21FFF2; + CHECKREG r5, 0x88219992; + CHECKREG r6, 0x44215552; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22213332; + imm32 p2, 0x44415532; + imm32 p3, 0x66617732; + imm32 p4, 0x88819932; + imm32 p5, 0xaaa1bb32; + imm32 fp, 0xccc1dd32; + imm32 sp, 0xeee1ff32; + +// P-reg to P-reg to B reg: no stall + P1 = FP; + B0 = P1; + P3 = P2; + B1 = P3; + P5 = P4; + B2 = P5; + FP = SP; + B3 = FP; + + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r4, 0xEEE1FF32; + CHECKREG r5, 0x88819932; + CHECKREG r6, 0x44415532; + CHECKREG r7, 0xccc1dd32; + + imm32 i0, 0x03001131; + imm32 i1, 0x23223333; + imm32 i2, 0x43445535; + imm32 i3, 0x63667737; + imm32 m0, 0x83889939; + imm32 m1, 0xa3aabb3b; + imm32 m2, 0xc3ccdd3d; + imm32 m3, 0xe3eeff3f; + +// I,M-reg to P-reg to R-reg: no stall + P1 = I0; + R0 = P1; + P2 = I1; + R1 = P2; + P3 = I2; + R2 = P3; + P4 = I3; + R3 = P4; + P5 = M0; + R4 = P5; + SP = M1; + R5 = SP; + FP = M2; + R6 = FP; + FP = M3; + R7 = FP; + + CHECKREG r0, 0x03001131; + CHECKREG r1, 0x23223333; + CHECKREG r2, 0x43445535; + CHECKREG r3, 0x63667737; + CHECKREG r4, 0x83889939; + CHECKREG r5, 0xA3AABB3B; + CHECKREG r6, 0xC3CCDD3D; + CHECKREG r7, 0xE3EEFF3F; + + imm32 i0, 0x12001111; + imm32 i1, 0x12221333; + imm32 i2, 0x12441555; + imm32 i3, 0x12661777; + imm32 m0, 0x12881999; + imm32 m1, 0x12aa1bbb; + imm32 m2, 0x12cc1ddd; + imm32 m3, 0x12ee1fff; + +// I,M-reg to P-reg to L,B reg: no stall + P1 = I0; + L0 = P1; + P1 = I1; + L1 = P1; + P2 = I2; + L2 = P2; + P3 = I3; + L3 = P3; + P4 = M0; + B0 = P4; + P5 = M1; + B1 = P5; + SP = M2; + B2 = SP; + FP = M3; + B3 = FP; + +//CHECKREG r0, 0x12001111; + CHECKREG p1, 0x12221333; + CHECKREG p2, 0x12441555; + CHECKREG p3, 0x12661777; + CHECKREG p4, 0x12881999; + CHECKREG p5, 0x12AA1BBB; + CHECKREG sp, 0x12CC1DDD; + CHECKREG fp, 0x12EE1FFF; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x12661777; + CHECKREG r1, 0x12441555; + CHECKREG r2, 0x12221333; + CHECKREG r3, 0x12001111; + CHECKREG r4, 0x12EE1FFF; + CHECKREG r5, 0x12CC1DDD; + CHECKREG r6, 0x12AA1BBB; + CHECKREG r7, 0x12881999; + + imm32 l0, 0x23003111; + imm32 l1, 0x23223333; + imm32 l2, 0x23443555; + imm32 l3, 0x23663777; + imm32 b0, 0x23883999; + imm32 b0, 0x23aa3bbb; + imm32 b0, 0x23cc3ddd; + imm32 b0, 0x23ee3fff; + +// L,B-reg to P-reg to I,M reg: no stall + P1 = L0; + I0 = P1; + P1 = L1; + I1 = P1; + P2 = L2; + I2 = P2; + P3 = L3; + I3 = P3; + P4 = B0; + M0 = P4; + P5 = B1; + M1 = P5; + SP = B2; + M2 = SP; + FP = B3; + M3 = FP; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; +//CHECKREG r0, 0x1EEE1FFF; + CHECKREG p1, 0x23223333; + CHECKREG p2, 0x23443555; + CHECKREG p3, 0x23663777; + CHECKREG p4, 0x23EE3FFF; + CHECKREG p5, 0x12AA1BBB; + CHECKREG sp, 0x12CC1DDD; + CHECKREG fp, 0x12EE1FFF; + + CHECKREG r0, 0x12EE1FFF; + CHECKREG r1, 0x12CC1DDD; + CHECKREG r2, 0x12AA1BBB; + CHECKREG r3, 0x23EE3FFF; + CHECKREG r4, 0x23663777; + CHECKREG r5, 0x23443555; + CHECKREG r6, 0x23223333; + CHECKREG r7, 0x23003111; + + pass diff --git a/sim/testsuite/bfin/c_regmv_pr_dep_stall.s b/sim/testsuite/bfin/c_regmv_pr_dep_stall.s new file mode 100644 index 0000000..91dd0f8 --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_pr_dep_stall.s @@ -0,0 +1,237 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_stall/c_regmv_pr_dep_stall.dsp +// Spec Reference: regmv pr-dependency stall +# mach: bfin + +.include "testutils.inc" + start + + INIT_M_REGS 0; + +// R-reg to P-reg to R reg: stall + imm32 r0, 0x00001110; + imm32 r1, 0x00213330; + imm32 r2, 0x04015550; + imm32 r3, 0x06607770; + imm32 r4, 0x08810990; + imm32 r5, 0x01a1b0b0; + imm32 r6, 0x01c1dd00; + imm32 r7, 0x01e1fff0; + P1 = R1; + R0 = P1; + P2 = R2; + R1 = P2; + P3 = R3; + R2 = P3; + P4 = R4; + R3 = P4; + P5 = R5; + R4 = P5; + SP = R6; + R5 = P2; + FP = R7; + R6 = P3; + + CHECKREG r0, 0x00213330; + CHECKREG r1, 0x04015550; + CHECKREG r2, 0x06607770; + CHECKREG r3, 0x08810990; + CHECKREG r4, 0x01A1B0B0; + CHECKREG r5, 0x04015550; + CHECKREG r6, 0x06607770; + CHECKREG r7, 0x01E1FFF0; + +// R-reg to P-reg to I,M reg: stall + imm32 r0, 0x10001111; + imm32 r1, 0x11213331; + imm32 r2, 0x14115551; + imm32 r3, 0x16617771; + imm32 r4, 0x18811991; + imm32 r5, 0x11a1b1b1; + imm32 r6, 0x11c1dd11; + imm32 r7, 0x11e1fff1; + P1 = R0; + I0 = P1; + P2 = R1; + I1 = P2; + P3 = R2; + I2 = P3; + P4 = R3; + I3 = P4; + P5 = R4; + M0 = P5; + SP = R5; + M1 = SP; + FP = R6; + M2 = FP; + + R0 = I3; + R1 = I2; + R2 = I1; + R3 = I0; + R4 = M3; + R5 = M2; + R6 = M1; + R7 = M0; + CHECKREG r0, 0x16617771; + CHECKREG r1, 0x14115551; + CHECKREG r2, 0x11213331; + CHECKREG r3, 0x10001111; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x11C1DD11; + CHECKREG r6, 0x11A1B1B1; + CHECKREG r7, 0x18811991; + + CHECKREG p1, 0x10001111; + CHECKREG p2, 0x11213331; + CHECKREG p3, 0x14115551; + CHECKREG p4, 0x16617771; + CHECKREG p5, 0x18811991; + CHECKREG sp, 0x11A1B1B1; + CHECKREG fp, 0x11C1DD11; + + imm32 r0, 0x20001112; + imm32 r1, 0x21213332; + imm32 r2, 0x24115552; + imm32 r3, 0x26617772; + imm32 r4, 0x28811992; + imm32 r5, 0x21a1b1b2; + imm32 r6, 0x21c1dd12; + imm32 r7, 0x21e1fff2; + P1 = R3; + I3 = P1; + P2 = R4; + I0 = P2; + P3 = R5; + I1 = P3; + P4 = R6; + I2 = P4; + P5 = R7; + M1 = P5; + SP = R0; + M2 = SP; + FP = R1; + M3 = FP; + + R0 = I3; + R1 = I2; + R2 = I1; + R3 = I0; + R4 = M3; + R5 = M2; + R6 = M1; + R7 = M0; + CHECKREG r0, 0x26617772; + CHECKREG r1, 0x21C1DD12; + CHECKREG r2, 0x21A1B1B2; + CHECKREG r3, 0x28811992; + CHECKREG r4, 0x21213332; + CHECKREG r5, 0x20001112; + CHECKREG r6, 0x21E1FFF2; + CHECKREG r7, 0x18811991; + + CHECKREG p1, 0x26617772; + CHECKREG p2, 0x28811992; + CHECKREG p3, 0x21A1B1B2; + CHECKREG p4, 0x21C1DD12; + CHECKREG p5, 0x21E1FFF2; + CHECKREG sp, 0x20001112; + CHECKREG fp, 0x21213332; + +// R-reg to P-reg to L,B reg: stall + imm32 r0, 0x30001113; + imm32 r1, 0x31213333; + imm32 r2, 0x34115553; + imm32 r3, 0x36617773; + imm32 r4, 0x38811993; + imm32 r5, 0x31a1b1b3; + imm32 r6, 0x31c1dd13; + imm32 r7, 0x31e1fff3; + P1 = R4; + L0 = P1; + P2 = R5; + L1 = P2; + P3 = R6; + L2 = P3; + P4 = R7; + L3 = P4; + P5 = R0; + B0 = P5; + SP = R1; + B1 = SP; + FP = R2; + B2 = FP; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x31E1FFF3; + CHECKREG r1, 0x31C1DD13; + CHECKREG r2, 0x31A1B1B3; + CHECKREG r3, 0x38811993; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x34115553; + CHECKREG r6, 0x31213333; + CHECKREG r7, 0x30001113; + + CHECKREG p1, 0x38811993; + CHECKREG p2, 0x31A1B1B3; + CHECKREG p3, 0x31C1DD13; + CHECKREG p4, 0x31E1FFF3; + CHECKREG p5, 0x30001113; + CHECKREG sp, 0x31213333; + CHECKREG fp, 0x34115553; + + imm32 r0, 0x40001114; + imm32 r1, 0x44213334; + imm32 r2, 0x44415554; + imm32 r3, 0x46647774; + imm32 r4, 0x48814994; + imm32 r5, 0x41a1b4b4; + imm32 r6, 0x41c1dd44; + imm32 r7, 0x41e1fff4; + P1 = R5; + L2 = P1; + P2 = R6; + L3 = P2; + P3 = R7; + L0 = P3; + P4 = R0; + L1 = P4; + P5 = R1; + B2 = P5; + SP = R2; + B3 = SP; + FP = R3; + B0 = FP; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x41C1DD44; + CHECKREG r1, 0x41A1B4B4; + CHECKREG r2, 0x40001114; + CHECKREG r3, 0x41E1FFF4; + CHECKREG r4, 0x44415554; + CHECKREG r5, 0x44213334; + CHECKREG r6, 0x31213333; + CHECKREG r7, 0x46647774; + + CHECKREG p1, 0x41A1B4B4; + CHECKREG p2, 0x41C1DD44; + CHECKREG p3, 0x41E1FFF4; + CHECKREG p4, 0x40001114; + CHECKREG p5, 0x44213334; + CHECKREG sp, 0x44415554; + CHECKREG fp, 0x46647774; + + pass diff --git a/sim/testsuite/bfin/c_regmv_pr_dr.s b/sim/testsuite/bfin/c_regmv_pr_dr.s new file mode 100644 index 0000000..fe1826f --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_pr_dr.s @@ -0,0 +1,147 @@ +//Original:/testcases/core/c_regmv_pr_dr/c_regmv_pr_dr.dsp +// Spec Reference: regmv preg to dreg +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; + +//imm32 p0, 0x00000001; +imm32 p1, 0x10082001; +imm32 p2, 0x10092002; +imm32 p3, 0x100a2003; +imm32 p4, 0x100b2004; +imm32 p5, 0x100c2005; +imm32 sp, 0x100d2006; +imm32 fp, 0x100e2007; + +//--------- Preg to dreg : Rx <= Px ------ + + +R0 = P1; +R1 = P1; +R2 = P1; +R3 = P1; +R4 = P1; +R5 = P1; +R6 = P1; +R7 = P1; +CHECKREG r1, 0x10082001; +CHECKREG r2, 0x10082001; +CHECKREG r3, 0x10082001; +CHECKREG r4, 0x10082001; +CHECKREG r5, 0x10082001; +CHECKREG r6, 0x10082001; +CHECKREG r7, 0x10082001; + +R0 = P2; +R1 = P2; +R2 = P2; +R3 = P2; +R4 = P2; +R5 = P2; +R6 = P2; +R7 = P2; +CHECKREG r0, 0x10092002; +CHECKREG r1, 0x10092002; +CHECKREG r2, 0x10092002; +CHECKREG r3, 0x10092002; +CHECKREG r4, 0x10092002; +CHECKREG r5, 0x10092002; +CHECKREG r6, 0x10092002; +CHECKREG r7, 0x10092002; + +R0 = P3; +R1 = P3; +R2 = P3; +R3 = P3; +R4 = P3; +R5 = P3; +R6 = P3; +R7 = P3; +CHECKREG r1, 0x100a2003; +CHECKREG r2, 0x100a2003; +CHECKREG r3, 0x100a2003; +CHECKREG r4, 0x100a2003; +CHECKREG r5, 0x100a2003; +CHECKREG r6, 0x100a2003; +CHECKREG r7, 0x100a2003; + +R0 = P4; +R1 = P4; +R2 = P4; +R3 = P4; +R4 = P4; +R5 = P4; +R6 = P4; +R7 = P4; +CHECKREG r0, 0x100b2004; +CHECKREG r1, 0x100b2004; +CHECKREG r2, 0x100b2004; +CHECKREG r3, 0x100b2004; +CHECKREG r4, 0x100b2004; +CHECKREG r5, 0x100b2004; +CHECKREG r6, 0x100b2004; +CHECKREG r7, 0x100b2004; + +R1 = P5; +R2 = P5; +R3 = P5; +R4 = P5; +R5 = P5; +R6 = P5; +R7 = P5; +CHECKREG r1, 0x100c2005; +CHECKREG r2, 0x100c2005; +CHECKREG r3, 0x100c2005; +CHECKREG r4, 0x100c2005; +CHECKREG r5, 0x100c2005; +CHECKREG r6, 0x100c2005; +CHECKREG r7, 0x100c2005; + +R0 = SP; +R1 = SP; +R2 = SP; +R3 = SP; +R4 = SP; +R5 = SP; +R6 = SP; +R7 = SP; +CHECKREG r0, 0x100d2006; +CHECKREG r1, 0x100d2006; +CHECKREG r2, 0x100d2006; +CHECKREG r3, 0x100d2006; +CHECKREG r4, 0x100d2006; +CHECKREG r5, 0x100d2006; +CHECKREG r6, 0x100d2006; +CHECKREG r7, 0x100d2006; + +R0 = FP; +R1 = FP; +R2 = FP; +R3 = FP; +R4 = FP; +R5 = FP; +R6 = FP; +R7 = FP; +CHECKREG r1, 0x100e2007; +CHECKREG r2, 0x100e2007; +CHECKREG r3, 0x100e2007; +CHECKREG r4, 0x100e2007; +CHECKREG r5, 0x100e2007; +CHECKREG r6, 0x100e2007; +CHECKREG r7, 0x100e2007; + +pass diff --git a/sim/testsuite/bfin/c_regmv_pr_imlb.s b/sim/testsuite/bfin/c_regmv_pr_imlb.s new file mode 100644 index 0000000..31ff3e9 --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_pr_imlb.s @@ -0,0 +1,382 @@ +//Original:/testcases/core/c_regmv_pr_imlb/c_regmv_pr_imlb.dsp +// Spec Reference: regmv preg-to-imlb reg +# mach: bfin + +.include "testutils.inc" + start + +// check R-reg to imlb-reg move + +imm32 r0, 0x00000001; +imm32 p1, 0x00020003; +imm32 p2, 0x00040005; +imm32 p3, 0x00060007; +imm32 p4, 0x00080009; +imm32 p5, 0x000a000b; +imm32 sp, 0x000c000d; +imm32 fp, 0x000e000f; +I0 = P1; +I1 = P1; +I2 = P1; +I3 = P1; +M0 = P1; +M1 = P1; +M2 = P1; +M3 = P1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 p2, 0x00040005; +I0 = P2; +I1 = P2; +I2 = P2; +I3 = P2; +M0 = P2; +M1 = P2; +M2 = P2; +M3 = P2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 p3, 0x00060007; +I0 = P3; +I1 = P3; +I2 = P3; +I3 = P3; +M0 = P3; +M1 = P3; +M2 = P3; +M3 = P3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 p4, 0x00080009; +I0 = P4; +I1 = P4; +I2 = P4; +I3 = P4; +M0 = P4; +M1 = P4; +M2 = P4; +M3 = P4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 p5, 0x000a000b; +I0 = P5; +I1 = P5; +I2 = P5; +I3 = P5; +M0 = P5; +M1 = P5; +M2 = P5; +M3 = P5; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 sp, 0x000c000d; +I0 = SP; +I1 = SP; +I2 = SP; +I3 = SP; +M0 = SP; +M1 = SP; +M2 = SP; +M3 = SP; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 fp, 0x000e000f; +I0 = FP; +I1 = FP; +I2 = FP; +I3 = FP; +M0 = FP; +M1 = FP; +M2 = FP; +M3 = FP; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + + +imm32 p1, 0x00020003; +L0 = P1; +L1 = P1; +L2 = P1; +L3 = P1; +B0 = P1; +B1 = P1; +B2 = P1; +B3 = P1; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 p2, 0x00040005; +L0 = P2; +L1 = P2; +L2 = P2; +L3 = P2; +B0 = P2; +B1 = P2; +B2 = P2; +B3 = P2; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 p3, 0x00060007; +L0 = P3; +L1 = P3; +L2 = P3; +L3 = P3; +B0 = P3; +B1 = P3; +B2 = P3; +B3 = P3; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 p4, 0x00080009; +L0 = P4; +L1 = P4; +L2 = P4; +L3 = P4; +B0 = P4; +B1 = P4; +B2 = P4; +B3 = P4; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 p5, 0x000a000b; +L0 = P5; +L1 = P5; +L2 = P5; +L3 = P5; +B0 = P5; +B1 = P5; +B2 = P5; +B3 = P5; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 sp, 0x000c000d; +L0 = SP; +L1 = SP; +L2 = SP; +L3 = SP; +B0 = SP; +B1 = SP; +B2 = SP; +B3 = SP; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 fp, 0x000e000f; +L0 = FP; +L1 = FP; +L2 = FP; +L3 = FP; +B0 = FP; +B1 = FP; +B2 = FP; +B3 = FP; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + +pass diff --git a/sim/testsuite/bfin/c_regmv_pr_pr.s b/sim/testsuite/bfin/c_regmv_pr_pr.s new file mode 100644 index 0000000..9fb83f6 --- /dev/null +++ b/sim/testsuite/bfin/c_regmv_pr_pr.s @@ -0,0 +1,95 @@ +//Original:/testcases/core/c_regmv_pr_pr/c_regmv_pr_pr.dsp +// Spec Reference: regmv preg-to-preg +# mach: bfin + +.include "testutils.inc" + start + +// check p-reg to p-reg move + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = P1; + P2 = P1; + P4 = P1; + P5 = P1; + FP = P1; + CHECKREG p1, 0x20021003; + CHECKREG p2, 0x20021003; + CHECKREG p4, 0x20021003; + CHECKREG p5, 0x20021003; + CHECKREG fp, 0x20021003; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = P2; + P2 = P2; + P4 = P2; + P5 = P2; + FP = P2; + CHECKREG p1, 0x20041005; + CHECKREG p2, 0x20041005; + CHECKREG p4, 0x20041005; + CHECKREG p5, 0x20041005; + CHECKREG fp, 0x20041005; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = P4; + P2 = P4; + P4 = P4; + P5 = P4; + FP = P4; + CHECKREG p1, 0x20081009; + CHECKREG p2, 0x20081009; + CHECKREG p4, 0x20081009; + CHECKREG p5, 0x20081009; + CHECKREG fp, 0x20081009; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = P5; + P2 = P5; + P4 = P5; + P5 = P5; + FP = P5; + CHECKREG p1, 0x200a100b; + CHECKREG p2, 0x200a100b; + CHECKREG p4, 0x200a100b; + CHECKREG p5, 0x200a100b; + CHECKREG fp, 0x200a100b; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = FP; + P2 = FP; + P4 = FP; + P5 = FP; + FP = FP; + CHECKREG p1, 0x200e100f; + CHECKREG p2, 0x200e100f; + CHECKREG p4, 0x200e100f; + CHECKREG p5, 0x200e100f; + CHECKREG fp, 0x200e100f; + + pass diff --git a/sim/testsuite/bfin/c_seq_ac_raise_mv.S b/sim/testsuite/bfin/c_seq_ac_raise_mv.S new file mode 100644 index 0000000..fb231d3 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ac_raise_mv.S @@ -0,0 +1,342 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv/c_seq_ac_raise_mv.dsp +// Spec Reference: sequencer stage AC (raise + regmv) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0xa01 (X); + R1 = 0xb02 (X); + R2 = 0xc03 (X); + R3 = 0xd04 (X); + R4 = 0xe05 (X); + R5 = 0xf06 (X); + R6 = 0x107 (X); + R7 = 0x208 (X); +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + +RAISE 2; // RTN + P1 = R7; + R0 = P1; +// [--sp] = (r7-r0); + +RAISE 5; // RTI + P2 = R6; + R1 = P2; + +// [--sp] = (r7-r1); + + +RAISE 6; // RTI + P3 = R5; + R2 = P3; + [ -- SP ] = ( R7:2 ); +// POP + +RAISE 7; // RTI + P4 = R4; + R3 = P4; +// (r7-r2) = [sp++]; + + + +CHECKREG(r0, 0x00000208); +CHECKREG(r1, 0x00000107); +CHECKREG(r2, 0x00000F06); +CHECKREG(r3, 0x00000E05); +CHECKREG(r4, 0x00000E05); +CHECKREG(r5, 0x00000F06); +CHECKREG(r6, 0x00000107); +CHECKREG(r7, 0x00000208); + + R0 = 0xa41 (X); + R1 = 0xb52 (X); + R2 = 0xc63 (X); + R3 = 0xd74 (X); + R4 = 0xe85 (X); + R5 = 0xf96 (X); + R6 = 0x1a7 (X); + R7 = 0x2b8 (X); +RAISE 8; // RTI + P1 = R0; + R6 = P1; +// (r7-r1) = [sp++]; +CHECKREG(r0, 0x00000A41); +CHECKREG(r1, 0x00000B52); +CHECKREG(r2, 0x00000C63); +CHECKREG(r3, 0x00000D74); +CHECKREG(r4, 0x00000E85); +CHECKREG(r5, 0x00000F96); +CHECKREG(r6, 0x00000A41); +CHECKREG(r7, 0x000002B8); + +RAISE 9; // RTI + P2 = R1; + R7 = P2; +// (r7-r0) = [sp++]; + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); +CHECKREG(r4, 0x00000E85); +CHECKREG(r5, 0x00000F96); +CHECKREG(r6, 0x00000A41); +CHECKREG(r7, 0x00000B52); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I0 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I1 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I2 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I3 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ac_raise_mv_ppop.S b/sim/testsuite/bfin/c_seq_ac_raise_mv_ppop.S new file mode 100644 index 0000000..f5fdd4a --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ac_raise_mv_ppop.S @@ -0,0 +1,359 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv_ppop/c_seq_ac_raise_mv_ppop.dsp +// Spec Reference: sequencer stage AC (raise + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + +RAISE 2; // RTN + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:1 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +RAISE 6; // RTI + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:2 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:2 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000024); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); + +RAISE 8; // RTI + P1 = R1; + R5 = P1; + ( R7:1 ) = [ SP ++ ]; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + +RAISE 9; // RTI + P2 = R2; + R5 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ac_regmv_pushpop.S b/sim/testsuite/bfin/c_seq_ac_regmv_pushpop.S new file mode 100644 index 0000000..163b2ed --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ac_regmv_pushpop.S @@ -0,0 +1,359 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ac_regmv_pushpop/c_seq_ac_regmv_pushpop.dsp +// Spec Reference: sequencer stage AC (regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + //RAISE 2; // RTN + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + + //RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:1 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + + //RAISE 6; // RTI + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:2 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + + //RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:2 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000024); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); + + //RAISE 8; // RTI + P1 = R1; + R5 = P1; + ( R7:1 ) = [ SP ++ ]; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + + //RAISE 9; // RTI + P2 = R2; + R5 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_dec_raise_pushpop.S b/sim/testsuite/bfin/c_seq_dec_raise_pushpop.S new file mode 100644 index 0000000..6ac5d60 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_dec_raise_pushpop.S @@ -0,0 +1,341 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_dec_raise_pushpop/c_seq_dec_raise_pushpop.dsp +// Spec Reference: sequencer stage DEC (raise + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + +RAISE 2; // RTN + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +RAISE 5; // RTI + [ -- SP ] = ( R7:1 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +RAISE 6; // RTI + [ -- SP ] = ( R7:2 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +RAISE 7; // RTI + ( R7:2 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000025); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); + +RAISE 8; // RTI + ( R7:1 ) = [ SP ++ ]; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000014); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + +RAISE 9; // RTI + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ex1_brcc_mv_pop.S b/sim/testsuite/bfin/c_seq_ex1_brcc_mv_pop.S new file mode 100644 index 0000000..be9be51 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex1_brcc_mv_pop.S @@ -0,0 +1,377 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex1_brcc_mv_pop/c_seq_ex1_brcc_mv_pop.dsp +// Spec Reference: sequencer stage ex1 ( brcc + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +R0 = 0; +ASTAT = R0; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN +IF !CC JUMP LABEL1 (BP); + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// RAISE 6; // RTI +IF !CC JUMP LABEL2 (BP); + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +// RAISE 7; // RTI +IF CC JUMP LABEL4; // SHOULD NOT EXECUTE + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + +LABEL4: + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000003); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); + +// RAISE 8; // RTI +IF !CC JUMP LABEL3 (BP); + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +// RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ex1_call_mv_pop.S b/sim/testsuite/bfin/c_seq_ex1_call_mv_pop.S new file mode 100644 index 0000000..d55d61d --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex1_call_mv_pop.S @@ -0,0 +1,393 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex1_call_mv_pop/c_seq_ex1_call_mv_pop.dsp +// Spec Reference: sequencer stage ex1 ( call + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + +LD32_LABEL(p1, SUBR1); + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN +CALL (p1); + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// RAISE 6; // RTI +CALL SUBR2; + P1 = R3; + R4 = P1; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +// RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000024); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); + +// RAISE 8; // RTI +CALL SUBR3; + P3 = R5; + R6 = P3; + ( R7:0 ) = [ SP ++ ]; +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +// RAISE 9; // RTI + P4 = R6; + R7 = P4; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000002); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + + +SUBR1: // should jump here + I0 += 2; + RTS; + I3 += 2; // should not go here + RTS; + +SUBR2: // should jump here + I1 += 2; + RTS; + I3 += 2; // should not go here + RTS; + +SUBR3: // should jump here + I2 += 2; + RTS; + I3 += 2; // should not go here + RTS; + + + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ex1_j_mv_pop.S b/sim/testsuite/bfin/c_seq_ex1_j_mv_pop.S new file mode 100644 index 0000000..089c300 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex1_j_mv_pop.S @@ -0,0 +1,375 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex1_j_mv_pop/c_seq_ex1_j_mv_pop.dsp +// Spec Reference: sequencer stage ex1 (jump + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN +JUMP.S LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// RAISE 6; // RTI +JUMP.S LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +// RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000003); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); + +// RAISE 8; // RTI +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +// RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ex1_raise_brcc_mv_pop.S b/sim/testsuite/bfin/c_seq_ex1_raise_brcc_mv_pop.S new file mode 100644 index 0000000..059a61b --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex1_raise_brcc_mv_pop.S @@ -0,0 +1,377 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_brcc_mv_pop/c_seq_ex1_raise_brcc_mv_pop.dsp +// Spec Reference: sequencer stage ex1 (raise+ brcc + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +R0 = 0; +ASTAT = R0; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN +IF !CC JUMP LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +RAISE 6; // RTI +IF !CC JUMP LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +RAISE 7; // RTI +IF CC JUMP LABEL4; // SHOULD NOT EXECUTE + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + +LABEL4: + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000003); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); + +RAISE 8; // RTI +IF !CC JUMP LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ex1_raise_call_mv_pop.S b/sim/testsuite/bfin/c_seq_ex1_raise_call_mv_pop.S new file mode 100644 index 0000000..1b70686 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex1_raise_call_mv_pop.S @@ -0,0 +1,393 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_call_mv_pop/c_seq_ex1_raise_call_mv_pop.dsp +// Spec Reference: sequencer stage ex1 (raise+ call + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + +LD32_LABEL(p1, SUBR1); + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN +CALL (p1); + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +RAISE 6; // RTI +CALL SUBR2; + P1 = R3; + R4 = P1; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000024); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); + +RAISE 8; // RTI +CALL SUBR3; + P3 = R5; + R6 = P3; + ( R7:0 ) = [ SP ++ ]; +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +RAISE 9; // RTI + P4 = R6; + R7 = P4; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000008); +CHECKREG(r1, 0x00000004); +CHECKREG(r2, 0x00000004); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + + +SUBR1: // should jump here + I0 += 2; + RTS; + I3 += 2; // should not go here + RTS; + +SUBR2: // should jump here + I1 += 2; + RTS; + I3 += 2; // should not go here + RTS; + +SUBR3: // should jump here + I2 += 2; + RTS; + I3 += 2; // should not go here + RTS; + + + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ex1_raise_j_mv_pop.S b/sim/testsuite/bfin/c_seq_ex1_raise_j_mv_pop.S new file mode 100644 index 0000000..2d88bb4 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex1_raise_j_mv_pop.S @@ -0,0 +1,375 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_j_mv_pop/c_seq_ex1_raise_j_mv_pop.dsp +// Spec Reference: sequencer stage ex1 (raise+ jump + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN +JUMP.S LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +RAISE 6; // RTI +JUMP.S LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000003); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); + +RAISE 8; // RTI +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ex2_brcc_mp_mv_pop.S b/sim/testsuite/bfin/c_seq_ex2_brcc_mp_mv_pop.S new file mode 100644 index 0000000..c32d062 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex2_brcc_mp_mv_pop.S @@ -0,0 +1,377 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex2_brcc_mp_mv_pop/c_seq_ex2_brcc_mp_mv_pop.dsp +// Spec Reference: sequencer stage ex2 ( brcc (mis-pred)+ regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +R0 = 0; +ASTAT = R0; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN +IF CC JUMP LABEL1 (BP); + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// RAISE 6; // RTI +IF !CC JUMP LABEL2 (BP); + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +// RAISE 7; // RTI +IF CC JUMP LABEL4 (BP); // SHOULD NOT EXECUTE + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + +LABEL4: + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + +// RAISE 8; // RTI +IF !CC JUMP LABEL3 (BP); + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +// RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ex2_mmr_mvpop.S b/sim/testsuite/bfin/c_seq_ex2_mmr_mvpop.S new file mode 100644 index 0000000..6e156d7 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex2_mmr_mvpop.S @@ -0,0 +1,386 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmr_mvpop/c_seq_ex2_mmr_mvpop.dsp +// Spec Reference: sequencer stage ex2 (mmr + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + +// [--sp] = (r7-r0); +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +LD32(r0, 0x55552345); +// RAISE 2; // RTN + [ P1 ] = R0; +// jump LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; +CSYNC; +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +// RAISE 6; // RTI + R0 = [ P1 ]; +// jump LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +//CHECKREG(r0, 0x55552345); +// RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x55552345); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000024); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +// RAISE 8; // RTI + R0 = [ P1 ]; +// jump LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +CSYNC; +CHECKREG(r0, 0x55552345); // CHECKREG can not be skipped +CHECKREG(r1, 0x00000012); // so they cannot appear here +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +//CHECKREG(r0, 0x55552345); +// RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x55552345); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ex2_mmrj_mvpop.S b/sim/testsuite/bfin/c_seq_ex2_mmrj_mvpop.S new file mode 100644 index 0000000..11eba1a --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex2_mmrj_mvpop.S @@ -0,0 +1,386 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmrj_mvpop/c_seq_ex2_mmrj_mvpop.dsp +// Spec Reference: sequencer stage ex2 ( mmr + jump + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +LD32(p2, DATA_ADDR_1); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; +CSYNC; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN + [ P1 ] = R0; +JUMP.S LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +// RAISE 6; // RTI + R0 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CHECKREG(r0, 0x00000001); +// RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000003); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +// RAISE 8; // RTI + R0 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CHECKREG(r0, 0x00000001); +// RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ex2_raise_mmr_mvpop.S b/sim/testsuite/bfin/c_seq_ex2_raise_mmr_mvpop.S new file mode 100644 index 0000000..5f86570 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex2_raise_mmr_mvpop.S @@ -0,0 +1,385 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmr_mvpop/c_seq_ex2_raise_mmr_mvpop.dsp +// Spec Reference: sequencer stage ex2 (raise+ mmr + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + +// [--sp] = (r7-r0); +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +LD32(r0, 0x55552345); +RAISE 2; // RTN + [ P1 ] = R0; +// jump LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; +CSYNC; +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R0 = [ P1 ]; +// jump LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x55552345); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000024); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI + R0 = [ P1 ]; +// jump LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +CSYNC; +CHECKREG(r0, 0x55552345); // CHECKREG can not be skipped +CHECKREG(r1, 0x00000012); // so they cannot appear here +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +//CHECKREG(r0, 0x55552345); +RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x55552345); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ex2_raise_mmrj_mvpop.S b/sim/testsuite/bfin/c_seq_ex2_raise_mmrj_mvpop.S new file mode 100644 index 0000000..f32ec69 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex2_raise_mmrj_mvpop.S @@ -0,0 +1,385 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmrj_mvpop/c_seq_ex2_raise_mmrj_mvpop.dsp +// Spec Reference: sequencer stage ex2 (raise+ mmr + jump+ regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +LD32(r0, 0x55552345); +RAISE 2; // RTN + [ P1 ] = R0; +JUMP.S LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; +CSYNC; +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R0 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CHECKREG(r0, 0x55552345); +RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x55552345); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000003); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI + R0 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CHECKREG(r0, 0x55552345); +RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/c_seq_ex3_ls_brcc_mvp.S b/sim/testsuite/bfin/c_seq_ex3_ls_brcc_mvp.S new file mode 100644 index 0000000..d64de59 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex3_ls_brcc_mvp.S @@ -0,0 +1,440 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_brcc_mvp/c_seq_ex3_ls_brcc_mvp.dsp +// Spec Reference: sequencer stage ex3 (ldst + brcc + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** +R0 = 0; +ASTAT = R0; + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym p2, DATA; +LD32(r0, 0x55552345); +// RAISE 2; // RTN +// r0 = [p2++]; + R1 = [ P1 ]; +IF !CC JUMP LABEL1 (BP); + + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI +// r2 = [p2++]; + R3 = [ P1 ]; +IF CC JUMP LABEL2 (BP); // not taken + + P4 = R6; + R4 = P4; + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +// RAISE 6; // RTI +// r4 = [p2++]; + R5 = [ P1 ]; +IF !CC JUMP LABEL2 (BP); + P3 = R3; + R6 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x55552345); +//CHECKREG(r1, 0x000002B8); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000025); +//CHECKREG(r5, 0x000002B8); +// RAISE 7; // RTI +// r0 = [p2++]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x55552345); +//CHECKREG(r1, 0x000002B8); +CHECKREG(r2, 0x00000003); +//CHECKREG(r3, 0x000002B8); +CHECKREG(r4, 0x00000007); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +// RAISE 8; // RTI +// r0 = [p2++]; + R1 = [ P1 ]; +IF !CC JUMP LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x55552345); +//CHECKREG(r1, 0x000002B8); +// RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/bfin/c_seq_ex3_ls_mmr_mvp.S b/sim/testsuite/bfin/c_seq_ex3_ls_mmr_mvp.S new file mode 100644 index 0000000..1b0d7b5 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex3_ls_mmr_mvp.S @@ -0,0 +1,442 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmr_mvp/c_seq_ex3_ls_mmr_mvp.dsp +// Spec Reference: sequencer stage ex3 (ldst + mmr regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** +R0 = 0; +ASTAT = R0; + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym p2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; + + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +// brf LABEL1 (bp); + + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + R2 = [ P2 ++ ]; + R3 = [ P1 ]; +// brt LABEL2 (bp); // not taken + + P4 = R6; + R4 = P4; + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +// RAISE 6; // RTI + R4 = [ P2 ++ ]; + R5 = [ P1 ]; +// brf LABEL2 (bp) ; + P3 = R3; + R6 = P3; + [ -- SP ] = ( R7:0 ); +// POP +// r0 = 0x00; +// r1 = 0x00; +// r2 = 0x00; +// r3 = 0x00; +// r4 = 0x00; +// r5 = 0x00; +// r6 = 0x00; +// r7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000016); +CHECKREG(r5, 0x14789232); +// RAISE 7; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000016); +CHECKREG(r5, 0x14789232); +CHECKREG(r6, 0x00000024); +CHECKREG(r7, 0x00000028); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +// RAISE 8; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +// brf LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +CHECKREG(r0, 0x00010203); // CHECKREG can not be skipped +CHECKREG(r1, 0x00000012); // so they cannot appear here +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x14789232); +CHECKREG(r4, 0x00000017); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x0000000C); +CHECKREG(r1, 0x0000000D); +// RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000008); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/bfin/c_seq_ex3_ls_mmrj_mvp.S b/sim/testsuite/bfin/c_seq_ex3_ls_mmrj_mvp.S new file mode 100644 index 0000000..96543f4 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex3_ls_mmrj_mvp.S @@ -0,0 +1,443 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmrj_mvp/c_seq_ex3_ls_mmrj_mvp.dsp +// Spec Reference: sequencer stage ex3 (ldst + mmr + jump+ regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym p2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; +CSYNC; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R4 = [ P2 ++ ]; + R5 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R6 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x14789232); +CHECKREG(r6, 0x00000027); +// RAISE 7; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000007); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +// RAISE 8; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +// RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S b/sim/testsuite/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S new file mode 100644 index 0000000..35abb66 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S @@ -0,0 +1,442 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex3_raise_ls_mmrj_mvp/c_seq_ex3_raise_ls_mmrj_mvp.dsp +// Spec Reference: sequencer stage ex3 (raise+ ldst + mmr + jump+ regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym p2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; +CSYNC; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R4 = [ P2 ++ ]; + R5 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R6 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x14789232); +CHECKREG(r6, 0x00000027); +RAISE 7; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000007); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/bfin/c_seq_wb_cs_lsmmrj_mvp.S b/sim/testsuite/bfin/c_seq_wb_cs_lsmmrj_mvp.S new file mode 100644 index 0000000..bf2a33f --- /dev/null +++ b/sim/testsuite/bfin/c_seq_wb_cs_lsmmrj_mvp.S @@ -0,0 +1,446 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_wb_cs_lsmmrj_mvp/c_seq_wb_cs_lsmmrj_mvp.dsp +// Spec Reference: sequencer:wb ( csync ldst mmr jump regmv pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym P2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN +CSYNC; + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI +CSYNC; + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +// RAISE 6; // RTI +CSYNC; + R4 = [ P2 ++ ]; + R6 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R5 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x14789232); +// RAISE 7; // RTI +CSYNC; + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000007); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +// RAISE 8; // RTI +CSYNC; + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +// RAISE 9; // RTI +CSYNC; + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S b/sim/testsuite/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S new file mode 100644 index 0000000..cbcf9ed --- /dev/null +++ b/sim/testsuite/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S @@ -0,0 +1,446 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_wb_raisecs_lsmmrj_mvp/c_seq_wb_raisecs_lsmmrj_mvp.dsp +// Spec Reference: sequencer:wb (raise csync ldst mmr jump regmv pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym P2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN +CSYNC; + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI +CSYNC; + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI +CSYNC; + R4 = [ P2 ++ ]; + R6 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R5 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x14789232); +RAISE 7; // RTI +CSYNC; + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000007); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI +CSYNC; + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +RAISE 9; // RTI +CSYNC; + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/bfin/c_seq_wb_rti_lsmmrj_mvp.S b/sim/testsuite/bfin/c_seq_wb_rti_lsmmrj_mvp.S new file mode 100644 index 0000000..4b97bee --- /dev/null +++ b/sim/testsuite/bfin/c_seq_wb_rti_lsmmrj_mvp.S @@ -0,0 +1,455 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_wb_rti_lsmmrj_mvp/c_seq_wb_rti_lsmmrj_mvp.dsp +// Spec Reference: sequencer:wb ( rti ldst mmr jump regmv pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym P2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R4 = [ P2 ++ ]; + R6 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R5 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x14789232); +RAISE 7; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000007); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + // *********** + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; + // *********** +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + // *********** + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; + // *********** + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/bfin/c_seq_wb_rtn_lsmmrj_mvp.S b/sim/testsuite/bfin/c_seq_wb_rtn_lsmmrj_mvp.S new file mode 100644 index 0000000..b18a52f --- /dev/null +++ b/sim/testsuite/bfin/c_seq_wb_rtn_lsmmrj_mvp.S @@ -0,0 +1,447 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_wb_rtn_lsmmrj_mvp/c_seq_wb_rtn_lsmmrj_mvp.dsp +// Spec Reference: sequencer:wb ( rtn ldst mmr jump regmv pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym P2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R4 = [ P2 ++ ]; + R6 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R5 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x14789232); +RAISE 7; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000007); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + // *********** + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; + // *********** + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/bfin/c_seq_wb_rtx_lsmmrj_mvp.S b/sim/testsuite/bfin/c_seq_wb_rtx_lsmmrj_mvp.S new file mode 100644 index 0000000..52eb6c8 --- /dev/null +++ b/sim/testsuite/bfin/c_seq_wb_rtx_lsmmrj_mvp.S @@ -0,0 +1,466 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_wb_rtx_lsmmrj_mvp/c_seq_wb_rtx_lsmmrj_mvp.dsp +// Spec Reference: sequencer:wb ( rtx ldst mmr jump regmv pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym P2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R4 = [ P2 ++ ]; + R6 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R5 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789234); +CHECKREG(r2, 0x00000024); +CHECKREG(r3, 0x00000025); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x00000027); +CHECKREG(r6, 0x14789232); +RAISE 7; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789233); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000008); +//CHECKREG(r4, 0x000002CC); +CHECKREG(r5, 0x00000007); +CHECKREG(r6, 0x00000008); +CHECKREG(r7, 0x00000009); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050608); +CHECKREG(r3, 0x00000009); +//CHECKREG(r4, 0x000002E4); +CHECKREG(r5, 0x00000008); +CHECKREG(r6, 0x00000009); +CHECKREG(r7, 0x0000000A); +RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 +R4 = RETX; // error handler: RETX has the address of the same Illegal instr + R1 += 1; + R2 += 1; + R3 += 1; + R5 += 1; + R6 += 1; + R7 += 1; +R4 += 4; // we have to add 4 to point to next instr after return +RETX = R4; +RTX; + // *********** + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; + // *********** + +HWHANDLE: // HW Error Handler 5 +.dd 0xFFFFFFFF + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 +.dd 0xFFFFFFFF + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler +.dd 0xFFFFFFFF + I3 += 2; +RTI; +I8HANDLE: // IVG 8 Handler +.dd 0xFFFFFFFF + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler +.dd 0xFFFFFFFF + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/bfin/c_ujump.s b/sim/testsuite/bfin/c_ujump.s new file mode 100644 index 0000000..65dcf5e --- /dev/null +++ b/sim/testsuite/bfin/c_ujump.s @@ -0,0 +1,52 @@ +//Original:/testcases/core/c_ujump/c_ujump.dsp +// Spec Reference: ujump +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +JUMP.S LAB1; + + +STOP: +JUMP.S END; + +LAB1: + R1 = 0x1111 (X); +JUMP.S LAB5; + R6 = 0x6666 (X); + +LAB2: + R2 = 0x2222 (X); +JUMP.S STOP; + +LAB3: + R3 = 0x3333 (X); +JUMP.S LAB2; + R7 = 0x7777 (X); + +LAB4: + R4 = 0x4444 (X); +JUMP.S LAB3; + +LAB5: + R5 = 0x5555 (X); +JUMP.S LAB4; + +END: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00002222; +CHECKREG r3, 0x00003333; +CHECKREG r4, 0x00004444; +CHECKREG r5, 0x00005555; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/bfin/cc-alu.S b/sim/testsuite/bfin/cc-alu.S new file mode 100644 index 0000000..089fbe7 --- /dev/null +++ b/sim/testsuite/bfin/cc-alu.S @@ -0,0 +1,126 @@ +# Blackfin testcase for CC/A0/A1 compares +# mach: bfin + +#include "test.h" + .include "testutils.inc" + + start + +/* Clear ASTAT before test */ +#define CHECK_ASTAT(op, exp) ASTAT = R2; CC = A0 op A1; check_astat exp + .macro check_astat exp:req + R5 = ASTAT; + R6 = \exp; + CC = R5 == R6; + IF !CC JUMP 1f; + .endm + + .macro _acc_test exp_eq:req, exp_le:req, exp_lt:req + CHECK_ASTAT(==, \exp_eq) + CHECK_ASTAT(<=, \exp_le) + CHECK_ASTAT(<, \exp_lt) + + jump 2f; +1: fail +2: + .endm + + .macro acc_test acc0:req, acc1:req, eq:req, le:req, lt:req + dmm32 A0, \acc0 + dmm32 A1, \acc1 + _acc_test \eq, \le, \lt + .endm + + .macro acc_ex_test a0x:req, a0w:req, a1x:req, a1w:req, eq:req, le:req, lt:req + imm32 R0, \a0w + A0.W = R0; + R0 = \a0x; + A0.X = R0; + imm32 R1, \a1w + A1.W = R1; + R1 = \a1x; + A1.X = R1; + _acc_test \eq, \le, \lt + .endm + + # Keep R2 with a value of 0 + imm32 R2, 0 + +#define _EQ _AC0|_CC|_AC0_COPY|_AZ, _AC0|_CC|_AC0_COPY|_AZ, _AC0| _AC0_COPY|_AZ +#define _POS_GT _AN, _CC| _AN, _CC| _AN +#define _POS_LT _AC0| _AC0_COPY , _AC0| _AC0_COPY , _AC0| _AC0_COPY +#define _NEG_GT _AC0| _AC0_COPY|_AN, _AC0|_CC|_AC0_COPY|_AN, _AC0|_CC|_AC0_COPY|_AN +#define _NEG_LT 0, 0, 0 + + # Simple tests around zero + acc_test 0, 0, _EQ + acc_test 0, 1, _POS_GT + acc_test 0, 10000, _POS_GT + acc_test 1, 0, _POS_LT + acc_test 10000, 0, _POS_LT + acc_test 0, -1, _NEG_LT + acc_test 0, -10000, _NEG_LT + acc_test -1, 0, _NEG_GT + acc_test -10000, 0, _NEG_GT + + # Simple positive-only tests + acc_test 1, 1, _EQ + acc_test 10000, 10000, _EQ + acc_test 1, 2, _POS_GT + acc_test 1, 20000, _POS_GT + acc_test 2, 1, _POS_LT + acc_test 20000, 1, _POS_LT + + # Simple negative-only tests + acc_test -1, -1, _EQ + acc_test -10000, -10000, _EQ + acc_test -1, -2, _POS_LT + acc_test -1, -20000, _POS_LT + acc_test -2, -1, _POS_GT + acc_test -20000, -1, _POS_GT + + # Simple postitive/negative tests + acc_test 1, -1, _NEG_LT + acc_test -1, 1, _NEG_GT + acc_test 1, -10000, _NEG_LT + acc_test -10000, 1, _NEG_GT + acc_test -1, 10000, _NEG_GT + acc_test 10000, -1, _NEG_LT + acc_test -10000, 10000, _NEG_GT + acc_test 10000, -10000, _NEG_LT + + # Max boundary limits +#define MAX_POS 0x7f, 0xffffffff +#define MAX_NEG 0x80, 0x00000000 + acc_ex_test 0, 0, MAX_POS, _POS_GT + acc_ex_test MAX_POS, 0, 0, _POS_LT + acc_ex_test 0, 1, MAX_POS, _POS_GT + acc_ex_test MAX_POS, 0, 1, _POS_LT + acc_ex_test -1, -1, MAX_POS, _NEG_GT + acc_ex_test MAX_POS, -1, -1, _NEG_LT + acc_ex_test MAX_POS, MAX_POS, _EQ + acc_ex_test 0, 0, MAX_POS, _POS_GT + acc_ex_test MAX_POS, 0, 0, _POS_LT + acc_ex_test 0, 1, MAX_POS, _POS_GT + acc_ex_test MAX_POS, 0, 1, _POS_LT + acc_ex_test -1, -1, MAX_POS, _NEG_GT + acc_ex_test MAX_POS, -1, -1, _NEG_LT + + acc_ex_test 0, 0, MAX_NEG, _NEG_LT + acc_ex_test MAX_NEG, 0, 0, _NEG_GT + acc_ex_test 0, 1, MAX_NEG, _NEG_LT + acc_ex_test MAX_NEG, 0, 1, _NEG_GT + acc_ex_test -1, -1, MAX_NEG, _POS_LT + acc_ex_test MAX_NEG, -1, -1, _POS_GT + acc_ex_test MAX_NEG, MAX_NEG, _EQ + acc_ex_test 0, 0, MAX_NEG, _NEG_LT + acc_ex_test MAX_NEG, 0, 0, _NEG_GT + acc_ex_test 0, 1, MAX_NEG, _NEG_LT + acc_ex_test MAX_NEG, 0, 1, _NEG_GT + acc_ex_test -1, -1, MAX_NEG, _POS_LT + acc_ex_test MAX_NEG, -1, -1, _POS_GT + + acc_ex_test MAX_POS, MAX_NEG, _NEG_LT + acc_ex_test MAX_NEG, MAX_POS, _NEG_GT + + pass diff --git a/sim/testsuite/bfin/cc-astat-bits.s b/sim/testsuite/bfin/cc-astat-bits.s new file mode 100644 index 0000000..1c7d485 --- /dev/null +++ b/sim/testsuite/bfin/cc-astat-bits.s @@ -0,0 +1,101 @@ +# Blackfin testcase for setting all ASTAT bits via CC +# mach: bfin + +# We encode the opcodes directly since we test reserved bits +# which lack an insn in the ISA for it. It's a 16bit insn; +# the low 8 bits are always 0x03 while the encoding for the +# high 8 bits are: +# bit 7 - direction +# 0: CC=...; +# 1: ...=CC; +# bit 6/5 - operation +# 0: = assignment +# 1: | bit or +# 2: & bit and +# 3: ^ bit xor +# bit 4-0 - the bit in ASTAT to access + + .include "testutils.inc" + + .macro _do dir:req, op:req, bit:req, bit_in:req, cc_in:req, bg_val:req, bit_out:req, cc_out:req + /* CC = CC; is invalid, so skip it */ + .if \bit != 5 + + /* Calculate the before and after ASTAT values */ + imm32 R1, (\bg_val & ~((1 << \bit) | (1 << 5))) | (\bit_in << \bit) | (\cc_in << 5); + imm32 R3, (\bg_val & ~((1 << \bit) | (1 << 5))) | (\bit_out << \bit) | (\cc_out << 5); + + /* Test the actual opcode */ + ASTAT = R1; + .byte (\dir << 7) | (\op << 5) | \bit + .byte 0x03 + R2 = ASTAT; + + /* Make sure things line up */ + CC = R3 == R2; + IF !CC JUMP 1f; + JUMP 2f; +1: fail +2: + .endif + + /* Recurse through all the bits */ + .if \bit > 0 + _do \dir, \op, \bit - 1, \bit_in, \cc_in, \bg_val, \bit_out, \cc_out + .endif + .endm + + /* Test different background fields on ASTAT */ + .macro do dir:req, op:req, bit_in:req, cc_in:req, bit_out:req, cc_out:req + _do \dir, \op, 31, \bit_in, \cc_in, 0, \bit_out, \cc_out + _do \dir, \op, 31, \bit_in, \cc_in, -1, \bit_out, \cc_out + .endm + + start + nop; + +_cc_eq_bit: /* CC = bit */ + do 0, 0, 0, 0, 0, 0 + do 0, 0, 0, 1, 0, 0 + do 0, 0, 1, 0, 1, 1 + do 0, 0, 1, 1, 1, 1 +_bit_eq_cc: /* bit = CC */ + do 1, 0, 0, 0, 0, 0 + do 1, 0, 0, 1, 1, 1 + do 1, 0, 1, 0, 0, 0 + do 1, 0, 1, 1, 1, 1 + +_cc_or_bit: /* CC |= bit */ + do 0, 1, 0, 0, 0, 0 + do 0, 1, 0, 1, 0, 1 + do 0, 1, 1, 0, 1, 1 + do 0, 1, 1, 1, 1, 1 +_bit_or_cc: /* bit |= CC */ + do 1, 1, 0, 0, 0, 0 + do 1, 1, 0, 1, 1, 1 + do 1, 1, 1, 0, 1, 0 + do 1, 1, 1, 1, 1, 1 + +_cc_and_bit: /* CC &= bit */ + do 0, 2, 0, 0, 0, 0 + do 0, 2, 0, 1, 0, 0 + do 0, 2, 1, 0, 1, 0 + do 0, 2, 1, 1, 1, 1 +_bit_and_cc: /* bit &= CC */ + do 1, 2, 0, 0, 0, 0 + do 1, 2, 0, 1, 0, 1 + do 1, 2, 1, 0, 0, 0 + do 1, 2, 1, 1, 1, 1 + +_cc_xor_bit: /* CC ^= bit */ + do 0, 3, 0, 0, 0, 0 + do 0, 3, 0, 1, 0, 1 + do 0, 3, 1, 0, 1, 1 + do 0, 3, 1, 1, 1, 0 +_bit_xor_cc: /* bit ^= CC */ + do 1, 3, 0, 0, 0, 0 + do 1, 3, 0, 1, 1, 1 + do 1, 3, 1, 0, 1, 0 + do 1, 3, 1, 1, 0, 1 + + pass diff --git a/sim/testsuite/bfin/cc0.s b/sim/testsuite/bfin/cc0.s new file mode 100644 index 0000000..3fee01e --- /dev/null +++ b/sim/testsuite/bfin/cc0.s @@ -0,0 +1,30 @@ +# Blackfin testcase for overflow +# mach: bfin + + .include "testutils.inc" + + start + + # add 0x80000000 + 0x80000000 + R1 = 1; + R1 <<= 31; + R0 = R1; + R0 = R0 + R1; + CC = V; // check to see if av0 and ac get set + CC &= AC0; + IF !CC JUMP art; + R1 = 0; + R1 += 0; + CC = AZ; + IF !CC JUMP art; + pass + +art: + R0 = CC; + R1 = 1 (Z); + + CC = R1 == R0 + if CC jump 1f; + fail +1: + pass diff --git a/sim/testsuite/bfin/cc1.s b/sim/testsuite/bfin/cc1.s new file mode 100644 index 0000000..d5d86d8 --- /dev/null +++ b/sim/testsuite/bfin/cc1.s @@ -0,0 +1,26 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0x1234 (X); + CC = BITTST ( R0 , 2 ); + IF !CC JUMP s$0; + R0 += 1; +s$0: + nop; + DBGA ( R0.L , 0x1235 ); + CC = BITTST ( R0 , 1 ); + IF !CC JUMP s$1; + R0 += 1; +s$1: + nop; + DBGA ( R0.L , 0x1235 ); + CC = BITTST ( R0 , 12 ); + IF !CC JUMP s$3; + R0 = - R0; +s$3: + nop; + DBGA ( R0.L , 0xedcb ); + pass diff --git a/sim/testsuite/bfin/cc5.S b/sim/testsuite/bfin/cc5.S new file mode 100644 index 0000000..593b3bd --- /dev/null +++ b/sim/testsuite/bfin/cc5.S @@ -0,0 +1,90 @@ +// ALU test program. +// Test instructions reg = (A0+=A1) + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + loadsym P0, data0; + + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// add accums and transfer result + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R6 = ( A0 += A1 ); + CHECKREG R6, 0x22222222; + R6 = A0.w; + CHECKREG R6, 0x22222222; + R7 = A0.x; + CHECKREG R7, 0; + R6 = A1.w; + CHECKREG R6, 0x11111111; + R7 = A1.x; + CHECKREG R7, 0; + +// add accums and transfer result (saturate positive) + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R6 = ( A0 += A1 ); + CHECKREG R6, 0x7fffffff; + R6 = A0.w; + CHECKREG R6, 0xfffffffe; + R7 = A0.x; + CHECKREG R7, 0; + R6 = A1.w; + CHECKREG R6, 0x7fffffff; + _DBG ASTAT; + R7 = A1.x; + _DBG ASTAT; + CHECKREG R7, 0; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY); + +// add accums and transfer result (saturate negative) + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + A1.x = R3.L; + A0.x = R3.L; + R6 = ( A0 += A1 ); + CHECKREG R6, 0x80000000; + R6 = A0.w; + CHECKREG R6, 0x00000000; + R7 = A0.x; + CHECKREG R6, 0; + R6 = A1.w; + CHECKREG R6, 0x80000000; + R7 = A1.x; + CHECKREG R7, 0xffffffff; + R7 = ASTAT; + _DBG ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); + + pass + + .data +data0: + .dw 0x1111 + .dw 0x1111 + .dw 0xffff + .dw 0x7fff + .dw 0x0000 + .dw 0x8000 + .dw 0x00ff + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/bfin/cec-exact-exception.S b/sim/testsuite/bfin/cec-exact-exception.S new file mode 100644 index 0000000..fd22f94 --- /dev/null +++ b/sim/testsuite/bfin/cec-exact-exception.S @@ -0,0 +1,54 @@ +# Blackfin testcase for aborting an excepting insn immediately +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + # This test keeps P5 as the base of the EVT table + + .macro set_evt lvl:req, sym:req + loadsym R1, \sym; + [P5 + 4 * \lvl\()] = R1; + .endm + + start + + # Set up exception handler + imm32 P4, EVT3; + loadsym R1, _evx; + [P4] = R1; + + # Lower ourselves to userspace + loadsym R1, _user; + RETI = R1; + RTI; + +_user: + imm32 R0, 0x12345678; + R1 = R0; + imm32 P0, 0xffffffff; + P1 = P0; +_user_fail: + # Sometimes this even causes immediate double faults when + # exceptions are not exact since this may trigger multiple + R0 = [P0++]; + + JUMP fail_lvl; + +_evx: + # RETX should be pointing to the right place + loadsym R6, _user_fail; + R7 = RETX; + CC = R6 == R7; + IF !CC JUMP fail_lvl; + + # R0 and P0 should be unchanged + CC = R1 == R0; + IF !CC JUMP fail_lvl; + CC = P1 == P0; + IF !CC JUMP fail_lvl; + + dbg_pass +fail_lvl: + dbg_fail diff --git a/sim/testsuite/bfin/cec-ifetch.S b/sim/testsuite/bfin/cec-ifetch.S new file mode 100644 index 0000000..5ed54b5 --- /dev/null +++ b/sim/testsuite/bfin/cec-ifetch.S @@ -0,0 +1,69 @@ +# Blackfin testcase for making sure RETX is the excepting insn +# and not the target of the insn (like indirect jumps) +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + # Set our handler + imm32 P5, EVT3; + loadsym R1, _evtx; + [P5] = R1; + + # Lower ourselves below EVT3 + loadsym R4, _i_rts; + RETI = R4; + RAISE 12; + RTI; + +_i_rts: + # Check unaligned RETS + loadsym R6, 1f; + loadsym R5, 2f; + R0 = 1; + RETS = R0; +1: RTS; +2: + +_i_jump: + # Check unaligned indirect jump + loadsym R6, 1f; + loadsym R5, 2f; + P0 = 1; +1: JUMP (P0); +2: + +_i_jump_off: + # Check unaligned indirect jump (pc-relative) + loadsym R6, 1f; + loadsym R5, 2f; + P0 = 1; +1: JUMP (PC + P0); +2: + +_i_call: + # Check unaligned indirect call + loadsym R6, 1f; + loadsym R5, 2f; + P0 = 1; +1: CALL (P0); +2: + +_pass_lvl: + dbg_pass + +_evtx: + # Make sure R6 matches RETX + R7 = RETX; + CC = R6 == R7; + if !CC jump _fail_lvl; + + # Move on to next test + RETX = R5; + RTX; + +_fail_lvl: + dbg_fail diff --git a/sim/testsuite/bfin/cec-multi-pending.S b/sim/testsuite/bfin/cec-multi-pending.S new file mode 100644 index 0000000..63f3780 --- /dev/null +++ b/sim/testsuite/bfin/cec-multi-pending.S @@ -0,0 +1,182 @@ +# Blackfin testcase for multiple pending IVGs vs masked state +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + # This test keeps P5 as the base of the EVT table + + .macro set_evt lvl:req, sym:req + loadsym R1, \sym; + [P5 + 4 * \lvl\()] = R1; + .endm + + .macro check_cec mmr:req, valid:req + imm32 P3, \mmr; + R0 = [P3]; + R1 = ~0x1f; + R0 = R0 & R1; + imm32 R1, \valid; + CC = R1 == R0; + IF CC JUMP 1f; + dbg_fail +1: + .endm + + .macro delay cnt:req + imm32 P2, \cnt + LSETUP (1f, 1f) LC1 = P2; +1: mnop; + .endm + + start + + # First mark all EVTs as fails (they shouldn't be activated) + imm32 P5, EVT0; + P1 = P5; + loadsym R1, fail_lvl + imm32 P2, 16 + LSETUP (1f, 1f) LC0 = P2; +1: [P1++] = R1; + + # Lower ourselves to EVT15 + set_evt 15, evt15; + R7 = 0 (x); + BITSET (R7, 15); + sti R7; + loadsym R1, wait; + RETI = R1; + RAISE 15; + RTI; + +wait: + jump wait; + +evt15: + # We shouldn't come back here + set_evt 15, fail_lvl; + + # Activate interrupt nesting early + [--SP] = RETI; + + # Raise some higher levels, but they should be masked and so + # they should never be activated ... + RAISE 6; + RAISE 5; + RAISE 9; + RAISE 12; + + # Only IVG15 should be pending + check_cec IPEND, (1<<15); + + # But all should be latched + check_cec ILAT, (1<<5) | (1<<6) | (1<<9) | (1<<12); + + # Delay a little in case a higher level wrongly activates + delay 30 + + # If we're still here, things are still good. So let's + # transition up *slightly*, but not to the highest latched. + set_evt 12, evt12; + cli R7; + BITSET (R7, 12); + sti R7; + + # Let CEC raise us to IVG12 + delay 30 + # CEC should have been faster than this ... + dbg_fail + +evt12: + # We shouldn't come back here + set_evt 12, fail_lvl; + + # Raise some higher levels, but they should be masked and so + # they should never be activated ... + RAISE 11; + + # Both IVG15 and IVG12 should be pending + check_cec IPEND, (1<<15) | (1<<12); + + # But all should be latched + check_cec ILAT, (1<<5) | (1<<6) | (1<<9) | (1<<11); + + # Activate interrupt nesting a little later + [--SP] = RETI; + + # Still here, so unmask a higher IVG again to move up + set_evt 9, evt9; + cli R7; + BITSET (R7, 9); + sti R7; + delay 30 + + # CEC should have been faster than this ... + dbg_fail + +evt9: + # We shouldn't come back here + set_evt 9, fail_lvl; + + # IVG9 should also be pending now + check_cec IPEND, (1<<15) | (1<<12) | (1<<9); + + # But all should be latched + check_cec ILAT, (1<<5) | (1<<6) | (1<<11); + + # Unmask the next level, but IPEND[4] is set, so we should stay here + set_evt 6, evt6; + cli R7; + BITSET (R7, 6); + sti R7; + + # Delay a little in case a higher level wrongly activates + delay 30 + + # Good, now unmask things globally + [--SP] = RETI; + delay 30 + + # CEC should have been faster than this ... + dbg_fail + +evt6: + # We shouldn't come back here + set_evt 6, fail_lvl; + + # IVG6 should also be pending now + check_cec IPEND, (1<<15) | (1<<12) | (1<<9) | (1<<6); + + # But all should be latched + check_cec ILAT, (1<<5) | (1<<11); + + # Activate interrupt nesting a little later + [--SP] = RETI; + + # Unmask the next level, but do it via IMASK + set_evt 5, evt5; + imm32 P2, IMASK; + R7 = [P2]; + BITSET (R7, 5); + [P2] = R7; + delay 30 + + # CEC should have been faster than this ... + dbg_fail + +evt5: + # We shouldn't come back here + set_evt 5, fail_lvl; + + # IVG5 should also be pending now + check_cec IPEND, (1<<15) | (1<<12) | (1<<9) | (1<<6) | (1<<5); + + # But all should be latched + check_cec ILAT, (1<<11); + + # All good! + dbg_pass; + +fail_lvl: + dbg_fail; diff --git a/sim/testsuite/bfin/cec-no-snen-reti.S b/sim/testsuite/bfin/cec-no-snen-reti.S new file mode 100644 index 0000000..bb9557d --- /dev/null +++ b/sim/testsuite/bfin/cec-no-snen-reti.S @@ -0,0 +1,128 @@ +# Blackfin testcase for having RETI LSB set correctly when not self nested +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + # Set our handler + imm32 P5, EVT11; + loadsym R1, _ivg11; + [P5] = R1; + loadsym R1, _fail_lvl; + [P5 + 4] = R1; /* IVG12 */ + [P5 + 12] = R1; /* IVG14 */ + loadsym R1, _ivg13; + [P5 + 8] = R1; + + # Disable self nesting + R2 = SYSCFG; + BITCLR (R2, 2); + SYSCFG = R2; + CSYNC; + + # Enable IVG11/IVG13/IVG14 but not IVG12 + cli R3; + BITSET (R3, 11); + BITCLR (R3, 12); + BITSET (R3, 13); + BITSET (R3, 14); + sti R3; + + # Counters to keep track of nesting depth + R7 = 0; + R5 = 0; + + # Lower ourselves to IVG11 + loadsym R4, _fail_lvl; + RETI = R4; + RAISE 11; + RAISE 12; + RAISE 13; + RAISE 14; + RTI; + +# This IVG makes sure we don't re-enter when self RAISE is pending +_ivg11: + R0 = RETI; + + # Make sure we are indeed at IVG11 + imm32 P0, IPEND; + R1 = [P0]; + CC = BITTST (R1, 11); + IF !CC JUMP _fail_lvl; + + # Should not be re-entering + CC = R5 == 0; + IF !CC JUMP _fail_lvl; + + # Make sure LSB of RETI is not set + CC = BITTST (R0, 0); + IF CC JUMP _fail_lvl; + + # Try to avoid nesting a few times + R5 += 1; + R6 = 3; + CC = R7 < R6; + IF !CC JUMP 1f; + [--sp] = RETI; + R7 += 1; + RAISE 11; + MNOP;NOP;MNOP;NOP; + R5 = 0; + RTI; + + # Move down to IVG13 for next test +1: loadsym R4, _fail_lvl; + RETI = R4; + RTI; + +# This IVG makes sure RETI LSB is ignored on transition out (RTI) +_ivg13: + R0 = RETI; + + # Make sure we are indeed at IVG13 + imm32 P0, IPEND; + R1 = [P0]; + CC = BITTST (R1, 13); + IF !CC JUMP _fail_lvl; + + # RETI LSB should not be set when entering IVG13 + CC = BITTST (R0, 0); + IF CC JUMP _fail_lvl; + + # Should get here only after a few IVG11 tests + CC = R7 == R6; + IF !CC JUMP _fail_lvl; + + # Make sure IVG13 isn't pending + imm32 P0, ILAT; + R1 = [P0]; + CC = BITTST (R1, 13); + IF CC JUMP _fail_lvl; + + # Manually set RETI to with LSB set so we should stay at IVG13 + # even though SNEN is disabled + loadsym R1, 1f; + BITSET (R1, 0); + RETI = R1; + R7 += 1; + RTI; + +1: # Make sure we get here in right number of tests + R6 = 4; + CC = R7 == R6; + IF !CC JUMP _fail_lvl; + + # Make sure we are still at IVG13 + imm32 P0, IPEND; + R1 = [P0]; + CC = BITTST (R1, 13); + IF !CC JUMP _fail_lvl; + + dbg_pass + +_fail_lvl: + dbg_fail; diff --git a/sim/testsuite/bfin/cec-non-operating-env.s b/sim/testsuite/bfin/cec-non-operating-env.s new file mode 100644 index 0000000..a35344c --- /dev/null +++ b/sim/testsuite/bfin/cec-non-operating-env.s @@ -0,0 +1,37 @@ +# Make sure the sim doesn't segfault when doing things that don't +# make much sense in a non-operating environment +# mach: bfin + + .include "testutils.inc" + + start + + csync; + ssync; + idle; + raise 12; + cli r0; + sti r0; + + loadsym r0, .Lreti; + reti = r0; + rti; + fail; +.Lreti: + + loadsym r0, .Lretx; + retx = r0; + rtx; + fail; +.Lretx: + + loadsym r0, .Lretn; + retn = r0; + rtn; + fail; +.Lretn: + + usp = p0; + p0 = usp; + + pass; diff --git a/sim/testsuite/bfin/cec-raise-reti.S b/sim/testsuite/bfin/cec-raise-reti.S new file mode 100644 index 0000000..1735ab8 --- /dev/null +++ b/sim/testsuite/bfin/cec-raise-reti.S @@ -0,0 +1,111 @@ +# Blackfin testcase for having RETI set correctly +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + # This test keeps P5 as the base of the EVT table + + .macro set_evt lvl:req, sym:req + loadsym R1, \sym; + [P5 + 4 * \lvl\()] = R1; + .endm + + start + + # First mark all EVTs as fails (they shouldn't be activated) + imm32 P5, EVT0; + P1 = P5; + loadsym R1, fail_lvl + imm32 P2, 16 + LSETUP (1f, 1f) LC0 = P2; +1: [P1++] = R1; + + # We'll bounce up a few + set_evt 6, evt6; + set_evt 7, evt7; + set_evt 8, evt8; + set_evt 9, evt9; + + # Lower ourselves down so we can RAISE up + set_evt 14, evt14; + loadsym R1, wait; + RETI = R1; + RAISE 14; + R7 = -1; + sti R7; + RTI; + +wait: + jump wait; + +evt14: + # Activate interrupt nesting early + [--SP] = RETI; + + # We activate the interrupt here ... + loadsym R1, 1f; + RAISE 9; + # ... but we should RETI here +1: JUMP fail_lvl; + +evt9: + R2 = RETI; + CC = R1 == R2; + IF !CC JUMP fail_lvl; + + # We activate the interrupt here ... + loadsym R1, 1f; + RAISE 8; + [--SP] = RETI; + # ... but we should RETI here +1: JUMP fail_lvl; + +evt8: + R2 = RETI; + CC = R1 == R2; + IF !CC JUMP fail_lvl; + + # Activate interrupt nesting early + [--SP] = RETI; + + # We activate the interrupt here ... + loadsym R1, 1f; + cli R7; + RAISE 7; + sti R7; + # ... but we should RETI here +1: JUMP fail_lvl; + +evt7: + R2 = RETI; + CC = R1 == R2; + IF !CC JUMP fail_lvl; + + # Activate interrupt nesting early + [--SP] = RETI; + + # We activate the interrupt here ... + imm32 P0, IMASK + R7 = [P0]; + R6 = 0; + [P0] = R6; + loadsym R1, 1f; + RAISE 6; + [P0] = R7; + # ... but we should RETI here + # don't jump to fail_lvl as the pipeline might advance + # the PC to the fail_lvl point before the ivg actually + # gets a chance to fire +1: JUMP 1b; + +evt6: + R2 = RETI; + CC = R1 == R2; + IF !CC JUMP fail_lvl; + + dbg_pass + +fail_lvl: + dbg_fail; diff --git a/sim/testsuite/bfin/cec-snen-reti.S b/sim/testsuite/bfin/cec-snen-reti.S new file mode 100644 index 0000000..306d99b --- /dev/null +++ b/sim/testsuite/bfin/cec-snen-reti.S @@ -0,0 +1,122 @@ +# Blackfin testcase for having RETI LSB set correctly when self nested +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + # Set our handler + imm32 P5, EVT11; + loadsym R1, _ivg11; + [P5] = R1; + loadsym R1, _fail_lvl; + [P5 + 4] = R1; /* IVG12 */ + [P5 + 12] = R1; /* IVG14 */ + loadsym R1, _ivg13; + [P5 + 8] = R1; + + # Enable self nesting + R2 = SYSCFG; + BITSET (R2, 2); + SYSCFG = R2; + CSYNC; + + # Enable IVG11/IVG13/IVG14 but not IVG12 + cli R3; + BITSET (R3, 11); + BITCLR (R3, 12); + BITSET (R3, 13); + BITSET (R3, 14); + sti R3; + + # Counter to keep track of nesting depth + R7 = 0; + + # Lower ourselves to IVG11 + loadsym R4, _fail_lvl; + RETI = R4; + RAISE 11; + RAISE 12; + RAISE 13; + RAISE 14; + RTI; + +# This IVG makes sure RETI LSB is set correctly on transition in (RAISE) +_ivg11: + R0 = RETI; + + # Make sure we are indeed at IVG11 + imm32 P0, IPEND; + R1 = [P0]; + CC = BITTST (R1, 11); + IF !CC JUMP _fail_lvl; + + # Make sure LSB of RETI is set only on first pass + CC = ! BITTST (R0, 0); + R1 = CC; + CC = R7 == 0; + R2 = CC; + CC = R1 == R2; + IF !CC JUMP _fail_lvl; + + # Nest ourselves a few times + R6 = 3; + CC = R7 < R6; + IF !CC JUMP 1f; + [--sp] = RETI; + R7 += 1; + RAISE 11; + MNOP; + JUMP _fail_lvl; + + # Move down to IVG13 for next test +1: loadsym R4, _fail_lvl; + RETI = R4; + RTI; + +# This IVG makes sure RETI LSB is respected on transition out (RTI) +_ivg13: + R0 = RETI; + + # Make sure we are indeed at IVG13 + imm32 P0, IPEND; + R1 = [P0]; + CC = BITTST (R1, 13); + IF !CC JUMP _fail_lvl; + + # RETI LSB should be set when re-entering IVG13 + CC = ! BITTST (R0, 0); + R1 = CC; + CC = R7 == R6; + R2 = CC; + CC = R1 == R2; + IF !CC JUMP _fail_lvl; + + # Should get here only after a few IVG11 tests + CC = R7 < R6; + IF CC JUMP _fail_lvl; + + # Make sure IVG13 isn't pending + imm32 P0, ILAT; + R1 = [P0]; + CC = BITTST (R1, 13); + IF CC JUMP _fail_lvl; + + # Manually set RETI to with LSB set so we return there + R5 = R6; + R5 += 3; + CC = R7 < R5; + IF !CC JUMP 1f; + loadsym R1, _ivg13; + BITSET (R1, 0); + RETI = R1; + R7 += 1; + RTI; + + # All done! +1: dbg_pass + +_fail_lvl: + dbg_fail; diff --git a/sim/testsuite/bfin/cec-syscfg-ssstep.S b/sim/testsuite/bfin/cec-syscfg-ssstep.S new file mode 100644 index 0000000..169a605 --- /dev/null +++ b/sim/testsuite/bfin/cec-syscfg-ssstep.S @@ -0,0 +1,72 @@ +# Blackfin testcase for hardware single stepping +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + # Set up exception handler + imm32 P4, EVT3; + loadsym R1, _evx; + [P4] = R1; + + # Enable single stepping + R0 = 1; + SYSCFG = R0; + + # Lower to the code we want to single step through + R1 = 1; + imm32 R5, 0xffff + R6 = 0; + R7 = 0; + loadsym R1, _usr; + RETI = R1; + RTI; + +_usr: + # Single step and set a new bit every time + BITSET (R7, 0); + BITSET (R7, 1); + BITSET (R7, 2); + BITSET (R7, 3); + BITSET (R7, 4); + BITSET (R7, 5); + BITSET (R7, 6); + BITSET (R7, 7); + BITSET (R7, 8); + BITSET (R7, 9); + BITSET (R7, 10); + BITSET (R7, 11); + BITSET (R7, 12); + BITSET (R7, 13); + BITSET (R7, 14); + BITSET (R7, 15); + JUMP fail_lvl; + +_evx: + # Make sure exception reason is single step + R3 = SEQSTAT; + R4 = 0x3f; + R3 = R3 & R4; + R4 = 0x10; + CC = R3 == R4; + IF !CC JUMP fail_lvl; + + # Set a new bit in R6 every single step to match R7 + CC = R1; + R6 = ROT R6 BY 1; + CC = R6 == R7; + IF !CC JUMP fail_lvl; + + # Do it through each bit + CC = R5 == R6; + IF CC JUMP pass_lvl; + + RTX; + +pass_lvl: + dbg_pass; +fail_lvl: + dbg_fail; diff --git a/sim/testsuite/bfin/cec-system-call.S b/sim/testsuite/bfin/cec-system-call.S new file mode 100644 index 0000000..6aaf3ca --- /dev/null +++ b/sim/testsuite/bfin/cec-system-call.S @@ -0,0 +1,64 @@ +# Blackfin testcase for returning to the right place while bouncing between +# multiple CEC levels (like in a Linux system call) +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + # This test keeps P5 as the base of the EVT table + + .macro set_evt lvl:req, sym:req + loadsym R1, \sym; + [P5 + 4 * \lvl\()] = R1; + .endm + + start + + # First mark all EVTs as fails (they shouldn't be activated) + imm32 P5, EVT0; + P1 = P5; + loadsym R1, fail_lvl + imm32 P2, 16 + LSETUP (1f, 1f) LC0 = P2; +1: [P1++] = R1; + + # The OS exception handler + set_evt 3, _evx; + # The OS system call handler + set_evt 15, _evt15; + + # Lower ourselves to userspace + loadsym R1, _user; + loadsym R2, _next_user; + RETI = R1; + R7 = -1; + sti R7; + RTI; + +_user: + EXCPT 0; +_next_user: + dbg_pass + +_evx: + # RETX should be pointing to the right place + R1 = RETX; + CC = R1 == R2; + IF !CC JUMP fail_lvl; + + # Lower ourselves to the system call handler + RAISE 15; + RTX; + +_evt15: + # RETI should be pointing to the right place + R1 = RETI; + CC = R1 == R2; + IF !CC JUMP fail_lvl; + + # Return to userspace now + RTI; + +fail_lvl: + dbg_fail diff --git a/sim/testsuite/bfin/cir.s b/sim/testsuite/bfin/cir.s new file mode 100644 index 0000000..efbb9d4 --- /dev/null +++ b/sim/testsuite/bfin/cir.s @@ -0,0 +1,20 @@ +# Blackfin testcase for circular buffer limits +# mach: bfin + + .include "testutils.inc" + + start + + B0 = 0 (X); + I0 = 0x1100 (X); + L0 = 0x10c0 (X); + M0 = 0 (X); + I0 += M0; + R0 = I0; + + R1 = 0x40 (Z); + CC = R1 == R0 + if CC jump 1f; + fail +1: + pass diff --git a/sim/testsuite/bfin/cir1.s b/sim/testsuite/bfin/cir1.s new file mode 100644 index 0000000..78381ac --- /dev/null +++ b/sim/testsuite/bfin/cir1.s @@ -0,0 +1,84 @@ +# Blackfin testcase for circular buffers +# mach: bfin + + .include "testutils.inc" + + .macro daginit i:req, b:req, l:req, m:req + imm32 I0, \i + imm32 B0, \b + imm32 L0, \l + imm32 M0, \m + .endm + .macro dagcheck newi:req + DBGA ( I0.L, \newi & 0xFFFF ); + DBGA ( I0.H, \newi >> 16 ); + .endm + + .macro dagadd i:req, b:req, l:req, m:req, newi:req + daginit \i, \b, \l, \m + I0 += M0; + dagcheck \newi + .endm + + .macro dagsub i:req, b:req, l:req, m:req, newi:req + daginit \i, \b, \l, \m + I0 -= M0; + dagcheck \newi + .endm + + .macro dag i:req, b:req, l:req, m:req, addi:req, subi:req + daginit \i, \b, \l, \m + I0 += M0; + dagcheck \addi + imm32 I0, \i + I0 -= M0; + dagcheck \subi + .endm + + start + + init_l_regs 0 + init_i_regs 0 + init_b_regs 0 + init_m_regs 0 + +_zero_len: + dag 0, 0, 0, 0, 0, 0 + dag 100, 0, 0, 0, 100, 100 + dag 100, 0, 0, 11, 111, 89 + dag 100, 0xaa00ff00, 0, 0, 100, 100 + dag 100, 0xaa00ff00, 0, 11, 111, 89 + +_zero_base: + dag 0, 0, 100, 10, 10, 90 + dag 50, 0, 100, 10, 60, 40 + dag 99, 0, 100, 10, 9, 89 + dag 50, 0, 100, 50, 0, 0 + dag 50, 0, 100, 100, 50, 50 + dag 50, 0, 100, 200, 150, -50 + dag 50, 0, 100, 2100, 2050, -1950 + dag 1000, 0, 100, 0, 900, 1000 + dag 1000, 0, 1000, 0, 0, 1000 + + dag 0xffff1000, 0, 0x1000, 0, 0xffff0000, 0xffff1000 + dag 0xaaaa1000, 0, 0xaaa1000, 0, 0xa0000000, 0xaaaa1000 + dag 0xaaaa1000, 0, 0xaaa1000, 0x1000, 0xa0001000, 0xaaaa0000 + dag 0xffff1000, 0, 0xffff0000, 0xffffff, 0x1000fff, 0xfeff1001 + +_positive_base: + dag 0, 100, 100, 10, 10, 90 + dag 90, 100, 100, 10, 100, 180 + dag 90, 100, 100, 2100, 2090, -1910 + dag 100, 100, 100, 100, 100, 100 + dag 0xfffff000, 0xffffff00, 0x10, 0xffff, 0xefef, 0xfffef011 + +_large_base_len: + dag 0, 0xffffff00, 0xffffff00, 0x00000100, 0x00000200, 0xfffffe00 + dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0x88888887, 0x77777779 + dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0x4ccccccc, 0x91111111, 0x6eeeeeef + dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0x00000000, 0x44444445, 0xbbbbbbbb + dag 0, 0xdddddddd, 0x7bbbbbbb, 0xcccccccc, 0xcccccccc, 0xb7777779 + dag 0, 0xbbbbbbbb, 0x7bbbbbbb, 0x4ccccccc, 0x4ccccccc, 0xb3333334 + dag 0, 0xbbbbbbbb, 0x7bbbbbbb, 0x00000000, 0x84444445, 0x7bbbbbbb + + pass diff --git a/sim/testsuite/bfin/cli-sti.s b/sim/testsuite/bfin/cli-sti.s new file mode 100644 index 0000000..9e775cb --- /dev/null +++ b/sim/testsuite/bfin/cli-sti.s @@ -0,0 +1,25 @@ +# Blackfin testcase for cli/sti instructions +# mach: bfin +# sim: --environment operating + + .include "testutils.inc" + + start + + # Make sure we can't mask <=EVT4 + R0 = 0; + sti R0; + cli R1; + R2 = 0x1f; + CC = R1 == R2; + IF !CC JUMP 1f; + + # Make sure we can mask >=EVT5 + R0 = 0xff; + sti R0; + cli R1; + CC = R0 == R1; + IF !CC JUMP 1f; + + dbg_pass +1: dbg_fail diff --git a/sim/testsuite/bfin/cmpacc.s b/sim/testsuite/bfin/cmpacc.s new file mode 100644 index 0000000..ed31f62 --- /dev/null +++ b/sim/testsuite/bfin/cmpacc.s @@ -0,0 +1,50 @@ +# Blackfin testcase for the accumulator and compares +# mach: bfin + + .include "testutils.inc" + + start + +r7=0; +astat=r7; +r7.l=0x80; +A1.x=r7.l; +r0 = 0; +A1.w=r0; +r1.l = 0xffff; +r1.h =0xffff; +A0.w=r1; +r7.l=0x7f; +A0.x=r7.l; +#dbg A0; +#dbg A1; +#dbg astat; +cc = A0==A1; +#dbg astat; +r7=astat; +dbga (r7.h, 0x0); +dbga (r7.l, 0x0); +astat=r0; +#dbg astat; +r7.l=0x80; +A0.x=r7.l; +r0 = 0; +A0.w=r0; +r1.l = 0xffff; +r1.h =0xffff; +A1.w=r1; +r7.l=0x7f; +A1.x=r7.l; +cc = A0 G0 +// | | | | +// +------------------------------+ +// | b0 b1 b2 b3 b14 b15 | <- in +// +------------------------------+ +// | | | | | +// ----- XOR------------> G1 +// Instruction BXOR computes the bit G0 or G1 and stores it into CC +// and also into a destination reg half. Here, we take CC and rotate it +// into an output register. +// However, one can also store the output bit directly by storing +// the register half where this bit is placed. This would result +// in an output structure similar to the one in the original function +// Convolutional_Encode(), where an entire half word holds a bit. +// The resulting execution speed would be roughly twice as fast, +// since there is no need to rotate output bit via CC. + +.include "testutils.inc" + start + + loadsym P0, input; + loadsym P1, output; + + R1 = 0; R2 = 0;R3 = 0; + + R2.L = 0; + R2.H = 0xa01d; // polynom 0 + R3.L = 0; + R3.H = 0x12f4; // polynom 1 + + // load and CurrentState to upper half of A0 + A1 = A0 = 0; + R0 = 0x0000; + A0.w = R0; + A0 = A0 << 16; + + // l-loop counter is in P4 + P4 = 2(Z); + // **** START l-LOOP ***** +l$0: + + // insert 16 bits of input into lower half of A0 + // and advance input pointer + R0 = W [ P0 ++ ] (Z); + A0.L = R0.L; + + P5 = 2 (Z); + LSETUP ( m$0 , m$0end ) LC0 = P5; // **** BEGIN m-LOOP ***** +m$0: + + P5 = 8 (Z); + LSETUP ( i$1 , i$1end ) LC1 = P5; // **** BEGIN i-LOOP ***** +i$1: + R4.L = CC = BXORSHIFT( A0 , R2 ); // polynom0 -> CC + R1 = ROT R1 BY 1; // CC -> R1 + R4.L = CC = BXOR( A0 , R3 ); // polynom1 -> CC +i$1end: + R1 = ROT R1 BY 1; // CC -> R1 + + // store 16 bits of outdata RL1 +m$0end: + W [ P1 ++ ] = R1; + + P4 += -1; + CC = P4 == 0; + IF !CC JUMP l$0; // **** END l-LOOP ***** + + // Check results + loadsym I2, output; + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x8c62 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x262e ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5b4d ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x834f ); + pass + + .data +input: + .dw 0x999f + .dw 0x1999 + +output: + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/bfin/cycles.s b/sim/testsuite/bfin/cycles.s new file mode 100644 index 0000000..bdea7eb --- /dev/null +++ b/sim/testsuite/bfin/cycles.s @@ -0,0 +1,41 @@ +# Blackfin testcase for playing with CYCLES +# mach: bfin + + .include "testutils.inc" + + start + + R0 = 0; + R1 = 1; + CYCLES = R0; + CYCLES2 = R1; + + /* CYCLES should be "small" while CYCLES2 should be R1 still */ + R2 = CYCLES; + CC = R2 <= 3; + if ! CC jump 1f; + + R3 = CYCLES2; + CC = R3 == 1; + if ! CC jump 1f; + + nop; + mnop; + nop; + mnop; + + /* Test the "shadowed" CYCLES2 -- only a read of CYCLES reloads it */ + imm32 R1, 0x12345678 + CYCLES2 = R1; + R2 = CYCLES2; + CC = R2 == R3; + if ! CC jump 1f; + + R2 = CYCLES; + R2 = CYCLES2; + CC = R2 == R1; + if ! CC jump 1f; + + pass +1: + fail diff --git a/sim/testsuite/bfin/d0.s b/sim/testsuite/bfin/d0.s new file mode 100644 index 0000000..5e13959 --- /dev/null +++ b/sim/testsuite/bfin/d0.s @@ -0,0 +1,31 @@ +# mach: bfin + +.include "testutils.inc" + start + + I1 = 0x4 (X); + B1 = 0x0 (X); + L1 = 0x10 (X); + M0 = 8 (X); + I1 -= M0; + R0 = I1; + DBGA ( R0.L , 0xc ); + + I1 = 0xf0 (X); + B1 = 0x100 (X); + L1 = 0x10 (X); + M0 = 2 (X); + I1 += M0; + R0 = I1; + DBGA ( R0.L , 0xf2 ); + + I2 = 0x1000 (X); + B2.L = 0; + B2.H = 0x9000; + L2 = 0x10 (X); + M2 = 0 (X); + I2 += M2; + R0 = I2; + DBGA ( R0.L , 0x1000 ); + + pass diff --git a/sim/testsuite/bfin/d1.s b/sim/testsuite/bfin/d1.s new file mode 100644 index 0000000..ea56330 --- /dev/null +++ b/sim/testsuite/bfin/d1.s @@ -0,0 +1,17 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + I0 = 0x1100 (X); + L0 = 0x10c0 (X); + M0 = 0 (X); + B0 = 0 (X); + I0 += M0; + R0 = I0; + DBGA ( R0.L , 0x40 ); + + pass diff --git a/sim/testsuite/bfin/d2.s b/sim/testsuite/bfin/d2.s new file mode 100644 index 0000000..2634f4b --- /dev/null +++ b/sim/testsuite/bfin/d2.s @@ -0,0 +1,56 @@ +# Blackfin testcase for circular buffers and BREV +# mach: bfin + + .include "testutils.inc" + + start + + I0 = 0 (X); + M0 = 0x8 (X); + P0 = 16; + loadsym R1, vals; + +aaa: + I0 += M0 (BREV); + P0 += -1; + + R2 = I0; + R0 = R1 + R2 + P1 = R0; + R0 = B[P1] (Z); + + R3 = P0; + + CC = R0 == R3; + if !CC JUMP _fail; + + CC = P0 == 0; + IF !CC JUMP aaa (BP); + R0 = I0; + + DBGA(R0.L, 0x0000); + DBGA(R0.H, 0x0000); + + pass + +_fail: + fail + + .data +vals: +.db 0x0 /* 0 */ +.db 0x8 +.db 0xc +.db 0x4 /* 4 */ +.db 0xe +.db 0x6 +.db 0xa +.db 0x2 /* 8 */ +.db 0xf +.db 0x7 +.db 0xB +.db 0x3 /* c */ +.db 0xD +.db 0x5 +.db 0x9 /* f */ +.db 0x1 diff --git a/sim/testsuite/bfin/dbg_brprd_ntkn_src_kill.S b/sim/testsuite/bfin/dbg_brprd_ntkn_src_kill.S new file mode 100644 index 0000000..a86ecdc --- /dev/null +++ b/sim/testsuite/bfin/dbg_brprd_ntkn_src_kill.S @@ -0,0 +1,545 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_brprd_ntkn_src_kill/dbg_brprd_ntkn_src_kill.dsp +// Description: This test checks that the trace buffer keeps track of a +// branch source instruction that is predicted but not taken getting killed +// at each stage in the pipe. The test consists of 8 instances of an EXCPT +// instruction followed by 0 to 7 NOPs and a BRF instruction (and bp), with +// the trace buffer enabled. +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000020 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + + // Save all the registers used in the ISR + [ -- SP ] = R0; + [ -- SP ] = R1; + [ -- SP ] = P0; + [ -- SP ] = P1; + [ -- SP ] = LC0; + [ -- SP ] = LB0; + [ -- SP ] = LT0; + [ -- SP ] = ASTAT; + + // Get EXCAUSE bits out of SEQSTAT + R0 = SEQSTAT; + R0 = R0 << 26; + R0 = R0 >> 26; + + // Check for Trace Exception + // Load r1 with EXCAUSE for Trace Exception + R1 = 0x0011 (Z); + // Check for Trace Exception +CC = R0 == R1; + // Branch to OUT if the EXCAUSE is not TRACE. +IF !CC JUMP OUT; + + // Read out the Trace Buffer. +LD32(p0, TBUFSTAT); + // Read TBUFSTAT MMR + P1 = [ P0 ]; + + // if p1 is zero skip the loop. +CC = P1 == 0; +IF CC JUMP OUT; + + // Read out the Entire Trace Buffer. +LD32(p0, TBUF); +LSETUP ( l0s , l0e ) LC0 = P1; +l0s:R0 = [ P0 ]; +l0e:R0 = [ P0 ]; + +OUT: + // Check for other exception, if any. + + // Restore all saved registers. +ASTAT = [ SP ++ ]; +LT0 = [ SP ++ ]; +LB0 = [ SP ++ ]; +LC0 = [ SP ++ ]; + P1 = [ SP ++ ]; + P0 = [ SP ++ ]; + R1 = [ SP ++ ]; + R0 = [ SP ++ ]; + + // Return +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +WR_MMR(TBUFCTL, 0x7, p0, r0); // Enable trace buffer & overflow + +CSYNC; // Wait for MMR write to complete + +CC = R7 == R6; // Set CC +EXCPT 1; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in WB stage +NOP; +NOP; + +EXCPT 2; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in EX3 stage +NOP; +NOP; + +EXCPT 3; +NOP; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in EX2 stage +NOP; +NOP; + +EXCPT 4; +NOP; +NOP; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in EX1 stage +NOP; +NOP; + +EXCPT 5; +NOP; +NOP; +NOP; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in AC stage +NOP; +NOP; + +EXCPT 6; +NOP; +NOP; +NOP; +NOP; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in DEC stage +NOP; +NOP; + +EXCPT 7; NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in IF2 stage +NOP; +NOP; + +EXCPT 8; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in IF1 stage +NOP; +NOP; + + // Read out the Rest of the Trace Buffer. +LD32(p0, TBUFSTAT); + // Read TBUFSTAT MMR + P1 = [ P0 ]; + + // if p1 is zero skip the loop. +CC = P1 == 0; +IF CC JUMP OUT1; + + // Read out the Entire Trace Buffer. +LD32(p0, TBUF); +LSETUP ( l1s , l1e ) LC0 = P1; +l1s:R0 = [ P0 ]; +l1e:R0 = [ P0 ]; + + // Don't RTI if you never wish to go to User Mode + // use END_TEST instead. + +OUT1: +dbg_pass; + +// rti; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + + // YOUR USER CODE GOES HERE. + +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_DATA_ADDR_2 //.data 0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/dbg_brtkn_nprd_src_kill.S b/sim/testsuite/bfin/dbg_brtkn_nprd_src_kill.S new file mode 100644 index 0000000..812c8c7 --- /dev/null +++ b/sim/testsuite/bfin/dbg_brtkn_nprd_src_kill.S @@ -0,0 +1,544 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_brtkn_nprd_src_kill/dbg_brtkn_nprd_src_kill.dsp +// Description: This test checks that the trace buffer keeps track of a +// branch source instruction that is taken but not predicted getting killed +// at each stage in the pipe. The test consists of 8 instances of an EXCPT +// instruction followed by 0 to 7 NOPs and a BRT instruction (no bp), with +// the trace buffer enabled. +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000020 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + + // Save all the registers used in the ISR + [ -- SP ] = R0; + [ -- SP ] = R1; + [ -- SP ] = P0; + [ -- SP ] = P1; + [ -- SP ] = LC0; + [ -- SP ] = LB0; + [ -- SP ] = LT0; + [ -- SP ] = ASTAT; + + // Get EXCAUSE bits out of SEQSTAT + R0 = SEQSTAT; + R0 = R0 << 26; + R0 = R0 >> 26; + + // Check for Trace Exception + // Load r1 with EXCAUSE for Trace Exception + R1 = 0x0011 (Z); + // Check for Trace Exception +CC = R0 == R1; + // Branch to OUT if the EXCAUSE is not TRACE. +IF !CC JUMP OUT; + + // Read out the Trace Buffer. +LD32(p0, TBUFSTAT); + // Read TBUFSTAT MMR + P1 = [ P0 ]; + + // if p1 is zero skip the loop. +CC = P1 == 0; +IF CC JUMP OUT; + + // Read out the Entire Trace Buffer. +LD32(p0, TBUF); +LSETUP ( l0s , l0e ) LC0 = P1; +l0s:R0 = [ P0 ]; +l0e:R0 = [ P0 ]; + +OUT: + // Check for other exception, if any. + + // Restore all saved registers. +ASTAT = [ SP ++ ]; +LT0 = [ SP ++ ]; +LB0 = [ SP ++ ]; +LC0 = [ SP ++ ]; + P1 = [ SP ++ ]; + P0 = [ SP ++ ]; + R1 = [ SP ++ ]; + R0 = [ SP ++ ]; + + // Return +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +WR_MMR(TBUFCTL, 0x7, p0, r0); // Enable trace buffer & overflow + +CSYNC; // Wait for MMR write to complete + +CC = R7 == R6; // Set CC +EXCPT 1; +IF CC JUMP 4; // Mispredicted branch gets killed in WB stage +NOP; +NOP; + +EXCPT 2; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in EX3 stage +NOP; +NOP; + +EXCPT 3; +NOP; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in EX2 stage +NOP; +NOP; + +EXCPT 4; +NOP; +NOP; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in EX1 stage +NOP; +NOP; + +EXCPT 5; +NOP; +NOP; +NOP; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in AC stage +NOP; +NOP; + +EXCPT 6; +NOP; +NOP; +NOP; +NOP; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in DEC stage +NOP; +NOP; + +EXCPT 7; NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in IF2 stage +NOP; +NOP; + +EXCPT 8; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in IF1 stage +NOP; +NOP; + + // Read out the Rest of the Trace Buffer. +LD32(p0, TBUFSTAT); + // Read TBUFSTAT MMR + P1 = [ P0 ]; + + // if p1 is zero skip the loop. +CC = P1 == 0; +IF CC JUMP OUT1; + + // Read out the Entire Trace Buffer. +LD32(p0, TBUF); +LSETUP ( l1s , l1e ) LC0 = P1; +l1s:R0 = [ P0 ]; +l1e:R0 = [ P0 ]; + + // Don't RTI if you never wish to go to User Mode + // use END_TEST instead. + +OUT1: +dbg_pass; + +// rti; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + + // YOUR USER CODE GOES HERE. + +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_DATA_ADDR_2 //.data 0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/dbg_jmp_src_kill.S b/sim/testsuite/bfin/dbg_jmp_src_kill.S new file mode 100644 index 0000000..c0caf5b --- /dev/null +++ b/sim/testsuite/bfin/dbg_jmp_src_kill.S @@ -0,0 +1,543 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_jmp_src_kill/dbg_jmp_src_kill.dsp +// Description: This test checks that the trace buffer keeps track of a JUMP +// source instruction getting killed at each stage in the pipe. The test +// consists of 8 instances of an EXCPT instruction followed by 0 to 7 NOPs +// and a JUMP, with the trace buffer enabled. +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000020 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + + // Save all the registers used in the ISR + [ -- SP ] = R0; + [ -- SP ] = R1; + [ -- SP ] = P0; + [ -- SP ] = P1; + [ -- SP ] = LC0; + [ -- SP ] = LB0; + [ -- SP ] = LT0; + [ -- SP ] = ASTAT; + + // Get EXCAUSE bits out of SEQSTAT + R0 = SEQSTAT; + R0 = R0 << 26; + R0 = R0 >> 26; + + // Check for Trace Exception + // Load r1 with EXCAUSE for Trace Exception + R1 = 0x0011 (Z); + // Check for Trace Exception +CC = R0 == R1; + // Branch to OUT if the EXCAUSE is not TRACE. +IF !CC JUMP OUT; + + // Read out the Trace Buffer. +LD32(p0, TBUFSTAT); + // Read TBUFSTAT MMR + P1 = [ P0 ]; + + // if p1 is zero skip the loop. +CC = P1 == 0; +IF CC JUMP OUT; + + // Read out the Entire Trace Buffer. +LD32(p0, TBUF); +LSETUP ( l0s , l0e ) LC0 = P1; +l0s:R0 = [ P0 ]; +l0e:R0 = [ P0 ]; + +OUT: + // Check for other exception, if any. + + // Restore all saved registers. +ASTAT = [ SP ++ ]; +LT0 = [ SP ++ ]; +LB0 = [ SP ++ ]; +LC0 = [ SP ++ ]; + P1 = [ SP ++ ]; + P0 = [ SP ++ ]; + R1 = [ SP ++ ]; + R0 = [ SP ++ ]; + + // Return +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +WR_MMR(TBUFCTL, 0x7, p0, r0); // Enable trace buffer & overflow + +CSYNC; // Wait for MMR write to complete + +EXCPT 1; +JUMP 4; // Jump gets killed in WB stage +NOP; +NOP; + +EXCPT 2; +NOP; +JUMP 4; // Jump gets killed in EX3 stage +NOP; +NOP; + +EXCPT 3; +NOP; +NOP; +JUMP 4; // Jump gets killed in EX2 stage +NOP; +NOP; + +EXCPT 4; +NOP; +NOP; +NOP; +JUMP 4; // Jump gets killed in EX1 stage +NOP; +NOP; + +EXCPT 5; +NOP; +NOP; +NOP; +NOP; +JUMP 4; // Jump gets killed in AC stage +NOP; +NOP; + +EXCPT 6; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP 4; // Jump gets killed in DEC stage +NOP; +NOP; + +EXCPT 7; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP 4; // Jump gets killed in IF2 stage +NOP; +NOP; + +EXCPT 8; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP 4; // Jump gets killed in IF1 stage +NOP; +NOP; + + // Read out the Rest of the Trace Buffer. +LD32(p0, TBUFSTAT); + // Read TBUFSTAT MMR + P1 = [ P0 ]; + + // if p1 is zero skip the loop. +CC = P1 == 0; +IF CC JUMP OUT1; + + // Read out the Entire Trace Buffer. +LD32(p0, TBUF); +LSETUP ( l1s , l1e ) LC0 = P1; +l1s:R0 = [ P0 ]; +l1e:R0 = [ P0 ]; + + // Don't RTI if you never wish to go to User Mode + // use END_TEST instead. + +OUT1: +dbg_pass; + +// rti; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + + // YOUR USER CODE GOES HERE. + +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_DATA_ADDR_2 //.data 0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/dbg_tr_basic.S b/sim/testsuite/bfin/dbg_tr_basic.S new file mode 100644 index 0000000..b7fa5b6 --- /dev/null +++ b/sim/testsuite/bfin/dbg_tr_basic.S @@ -0,0 +1,272 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_tr_basic/dbg_tr_basic.dsp +// Description: Verify the basic functionality of TBUFPWR and TBUFEN in +// Supervisor mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(mmrs.inc) +include(selfcheck.inc) + +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +// This test embeds .text offsets, so pad our test so it lines up. +.space 0x70 + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + +CHECK_INIT(p5, 0x00BFFFFC); + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +LD32_LABEL(r7, DUMMY); +RETI = r7; +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; + + + + START : +WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn ON trace Buffer + // TBUFPWR = 0 + // TBUFEN = 0 + // TBUFOVF = 0 + // CMPLP = 0 +NOP; +NOP; +NOP; +NOP; +NOP; + NOP; +NOP; +JUMP.S label1; // + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label2: R5.H = 0x7777; // + R5.L = 0x7888; +JUMP.S label3; // + R6.L = 0x1111; // Will be killed + R6.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +label1: R4.H = 0x5555; // + R4.L = 0x6666; +NOP; +WR_MMR(TBUFCTL, 0x00000002, p0, r0); // + // TBUFPWR = 0 + // TBUFEN = 1 + // TBUFOVF = 0 + // CMPLP = 0 +NOP; +NOP; +NOP; +NOP; +JUMP.S label2; // + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +label3: R6.H = 0x7999; // + R6.L = 0x7aaa; +NOP; +NOP; +WR_MMR(TBUFCTL, 0x00000001, p0, r0); + NOP; + NOP; + NOP; +WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer + // TBUFPWR = 1 + // TBUFEN = 1 + // TBUFOVF = 0 + // CMPLP = 0 +NOP; +NOP; +NOP; +NOP; +JUMP.S label4; // + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; + +label4: R6.H = 0x1aaa; // + R6.L = 0x2222; +NOP; +NOP; +NOP; +NOP; + +WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn OFF trace Buffer + +NOP; +NOP; +NOP; +NOP; + // Read the contents of the Trace Buffer + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000001); + + // Read 3rd Entry of the Trace Buffer +RD_MMR(TBUF, p0, r0); +CHECKREG(r0, 0x000002d2); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000001); + +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x000002c0); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000000); + + +WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn OFF trace Buffer Power + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; diff --git a/sim/testsuite/bfin/dbg_tr_simplejp.S b/sim/testsuite/bfin/dbg_tr_simplejp.S new file mode 100644 index 0000000..8fe5f20 --- /dev/null +++ b/sim/testsuite/bfin/dbg_tr_simplejp.S @@ -0,0 +1,267 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_tr_simplejp/dbg_tr_simplejp.dsp +// Description: This test performs simple jumps and verifies the trace buffer +// recording for simple jumps. +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(mmrs.inc) +include(selfcheck.inc) +include(symtable.inc) + +#ifndef ITABLE +#define ITABLE CODE_ADDR_1 // +#endif + +// This test embeds .text offsets, so pad our test so it lines up. +.space 0x5e + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + +CHECK_INIT_DEF(p5); // CHECK_INIT(p5, 0x00BFFFFC); + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +LD32_LABEL(r7, DUMMY); +RETI = r7; +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; + + + + START : +WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer + // TBUFPWR = 1 + // TBUFEN = 1 + // TBUFOVF = 0 + // CMPLP = 0 +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label1; // 0x0224 + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label2: R5.H = 0x7777; // 0x0234 + R5.L = 0x7888; +JUMP.S label3; //0x023c + R6.L = 0x1111; // Will be killed + R6.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +label1: R4.H = 0x5555; // 0x0250 + R4.L = 0x6666; +NOP; +JUMP.S label2; // 0x0258 + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +label3: R6.H = 0x7999; //0x026c + R6.L = 0x7aaa; +NOP; +NOP; +NOP; +NOP; + +WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn OFF trace Buffer + +NOP; +NOP; +NOP; +NOP; +NOP; + // Read the contents of the Trace Buffer + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000003); + + // Read 3rd Entry of the Trace Buffer +RD_MMR(TBUF, p0, r0); +CHECKREG(r0, 0x0000026c); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000003); + +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x0000023c); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000002); + + // Read 2nd Entry of the Trace Buffer +RD_MMR(TBUF, p0, r0); +CHECKREG(r0, 0x00000234); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000002); + +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x0000025a); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000001); + + // Read ist Entry of the Trace Buffer +RD_MMR(TBUF, p0, r0); +CHECKREG(r0, 0x00000250); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000001); + +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x00000224); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000000); + +WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn OFF trace Buffer Power + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; diff --git a/sim/testsuite/bfin/dbg_tr_tbuf0.S b/sim/testsuite/bfin/dbg_tr_tbuf0.S new file mode 100644 index 0000000..82ca6ce --- /dev/null +++ b/sim/testsuite/bfin/dbg_tr_tbuf0.S @@ -0,0 +1,262 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_tr_tbuf0/dbg_tr_tbuf0.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(mmrs.inc) +include(selfcheck.inc) + +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +// This test embeds .text offsets, so pad our test so it lines up. +.space 0x64 + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + +CHECK_INIT(p5, 0x00BFFFFC); + + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +LD32_LABEL(r7, DUMMY); +RETI = r7; +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; + + + + START : + +WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn ON trace Buffer +WR_MMR(TBUFCTL, 0x0000000b, p0, r0); // Turn ON trace Buffer + // TBUFPWR = 1 + // TBUFEN = 1 + // TBUFOVF = 0 + // CMPLP = 01 +NOP; +NOP; +NOP; + NOP; + NOP; + R6 = 0; + R7 = 10; + +JMP: + JUMP.S LABEL0; + NOP; + NOP; + +LABEL0: + P1 = 0x0006; + JUMP (PC+P1); + +LABEL1: + LD32(R3, 0xBADD); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + +LABEL2: + CC = R7 == R6; + IF CC JUMP END; + R6 += 1; + JUMP LABEL2; + +LABEL3: + NOP; + +LABEL4: + LD32(R4, 0xBADD); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + + + + +END: + R0 = 1; + NOP; + NOP; + NOP; + +CHECKREG(r3, 0x00000000); +CHECKREG(r4, 0x00000000); + // Read the contents of the Trace Buffer + +RD_MMR(TBUFSTAT, p0, r0); +CHECKREG(r0, 0x00000004); + + // Read last entry of the Trace Buffer +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x00000256); + +RD_MMR(TBUF, p0, r2); +CHECKREG(r2, 0x00000246); + +RD_MMR(TBUFSTAT, p0, r0); +CHECKREG(r0, 0x00000003); + + // Read last entry of the Trace Buffer +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x00000245); + +RD_MMR(TBUF, p0, r2); +CHECKREG(r2, 0x0000024a); + +RD_MMR(TBUFSTAT, p0, r0); +CHECKREG(r0, 0x00000002); + + // Read last entry of the Trace Buffer +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x00000240); + +RD_MMR(TBUF, p0, r2); +CHECKREG(r2, 0x0000023a); + +RD_MMR(TBUFSTAT, p0, r0); +CHECKREG(r0, 0x00000001); + + // Read last entry of the Trace Buffer +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x00000238); + +RD_MMR(TBUF, p0, r2); +CHECKREG(r2, 0x00000232); + + + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + +RTX; + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; diff --git a/sim/testsuite/bfin/dbg_tr_umode.S b/sim/testsuite/bfin/dbg_tr_umode.S new file mode 100644 index 0000000..83c3f74 --- /dev/null +++ b/sim/testsuite/bfin/dbg_tr_umode.S @@ -0,0 +1,314 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_tr_umode/dbg_tr_umode.dsp +// Description: Verify the basic functionality of TBUFPWR and TBUFEN in +// Supervisor mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(mmrs.inc) +include(selfcheck.inc) + +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x20 +#endif + +// This test embeds .text offsets, so pad our test so it lines up. +.space 0x64 + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + +CHECK_INIT(p5, 0x00BFFFFC); + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +LD32_LABEL(r7, DUMMY); +RETI = r7; +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; + +// .code 0x200 +START: +WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn ON trace Buffer +WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer + // TBUFPWR = 1 + // TBUFEN = 1 + // TBUFOVF = 0 + // CMPLP = 0 +NOP; +NOP; +NOP; +NOP; + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +RTI; + +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + +NOP; + NOP; +NOP; +JUMP.S label1; + R4.L = 0x1111; + R4.H = 0x1111; +NOP; +NOP; +NOP; +label2: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label3; + R6.L = 0x1111; + R6.H = 0x1111; +NOP; +NOP; +NOP; +NOP; +NOP; +label1: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label2; + R5.L = 0x1111; + R5.H = 0x1111; +NOP; +NOP; +NOP; +NOP; +label3: + NOP; +NOP; +NOP; + NOP; + NOP; + NOP; +NOP; +NOP; + // Checks the contents of the Trace Buffer + + EXCPT 0; + NOP; NOP; NOP; NOP; +CHECKREG(r2, 0x00000006); +CHECKREG(r1, 0x00000416); +CHECKREG(r0, 0x000002aa); +CHECKREG(r3, 0x0000029a); +CHECKREG(r4, 0x00000262); +CHECKREG(r5, 0x00000004); +CHECKREG(r6, 0x0000025a); +CHECKREG(r7, 0x00000288); + NOP; NOP; NOP; NOP; + NOP; NOP; NOP; NOP; + + EXCPT 1; + NOP; NOP; NOP; NOP; + CHECKREG(r2, 0x00000005); +CHECKREG(r1, 0x00000416); +CHECKREG(r0, 0x00000304); +CHECKREG(r3, 0x000002ac); +CHECKREG(r4, 0x00000470); +CHECKREG(r5, 0x00000003); +CHECKREG(r6, 0x00000276); +CHECKREG(r7, 0x0000024a); + NOP; NOP; NOP; NOP; + NOP; NOP; NOP; NOP; + + EXCPT 2; + NOP; NOP; NOP; NOP; + CHECKREG(r2, 0x00000004); +CHECKREG(r1, 0x00000416); +CHECKREG(r0, 0x0000035e); +CHECKREG(r3, 0x00000306); +CHECKREG(r4, 0x00000470); +CHECKREG(r5, 0x00000002); +CHECKREG(r6, 0x00000244); +CHECKREG(r7, 0x00000242); + NOP; NOP; NOP; NOP; + + EXCPT 3; + NOP; NOP; NOP; NOP; + CHECKREG(r2, 0x00000003); +CHECKREG(r1, 0x00000416); +CHECKREG(r0, 0x000003b0); +CHECKREG(r3, 0x00000360); +CHECKREG(r4, 0x00000470); +CHECKREG(r5, 0x00000001); +CHECKREG(r6, 0x00000238); +CHECKREG(r7, 0x00000236); + + + +NOP; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + R7 = SEQSTAT; + +RD_MMR(TBUFSTAT, p0, r2); +RD_MMR(TBUF, p0, r1); +RD_MMR(TBUF, p0, r0); +RD_MMR(TBUF, p0, r3); +RD_MMR(TBUF, p0, r4); +RD_MMR(TBUFSTAT, p0, r5); +RD_MMR(TBUF, p0, r6); +RD_MMR(TBUF, p0, r7); + + NOP; NOP; NOP; NOP; + +RTX; + + NOP; NOP; NOP; NOP; + NOP; NOP; NOP; NOP; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/disalnexcpt_implicit.S b/sim/testsuite/bfin/disalnexcpt_implicit.S new file mode 100644 index 0000000..9f6c83c --- /dev/null +++ b/sim/testsuite/bfin/disalnexcpt_implicit.S @@ -0,0 +1,122 @@ +# Blackfin testcase for insns that implicitly have DISALGNEXCPT behavior +# when used in parallel insns +# mach: bfin + +#include "test.h" + .include "testutils.inc" + + start + + LINK 0x100; + + # Set up I0/I1/I2/I3 to be unaligned by 0/1/2/3 bytes + init_l_regs 0 + init_m_regs 0 + R0 = SP; + BITCLR (R0, 0); + BITCLR (R0, 1); + I0 = R0; + B0 = R0; + R1 = 1; + R1 = R0 + R1; + I1 = R1; + B1 = R1; + R2 = 2; + R2 = R0 + R2; + I2 = R2; + B2 = R2; + R3 = 3; + R3 = R0 + R3; + I3 = R3; + B3 = R3; + +#define EXP_VAL 0x12345678 +#define EXP(r, n) CHECKREG (r, EXP_VAL); r = 0; I##n = B##n + imm32 R5, EXP_VAL; + imm32 R6, 0x9abcdef0; + imm32 R7, 0x0a1b2c3e; + [SP] = R5; + [SP - 4] = R6; + [SP + 4] = R7; + +#define BYTEPACK(n) \ + R7 = BYTEPACK (R0, R1) || R4 = [I##n]; EXP (R4, n); \ + R6 = BYTEPACK (R0, R1) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + R5 = BYTEPACK (R0, R1) || R6 = [I##n++]; EXP (R6, n); \ + R4 = BYTEPACK (R0, R1) || R7 = [I##n--]; EXP (R7, n); + BYTEPACK(0) + BYTEPACK(1) + BYTEPACK(2) + BYTEPACK(3) + +#define BYTEUNPACK(n) \ + (R7, R5) = BYTEUNPACK R1:0 || R4 = [I##n]; EXP (R4, n); \ + (R6, R7) = BYTEUNPACK R3:2 || R5 = [I##n ++ M##n]; EXP (R5, n); \ + (R5, R4) = BYTEUNPACK R1:0 || R6 = [I##n++]; EXP (R6, n); \ + (R4, R6) = BYTEUNPACK R3:2 || R7 = [I##n--]; EXP (R7, n); + BYTEUNPACK(0) + BYTEUNPACK(1) + BYTEUNPACK(2) + BYTEUNPACK(3) + +#define SAA(n) \ + SAA (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \ + SAA (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + SAA (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \ + SAA (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n); + SAA(0) + SAA(1) + SAA(2) + SAA(3) + +#define BYTEOP1P(n) \ + R7 = BYTEOP1P (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \ + R6 = BYTEOP1P (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + R5 = BYTEOP1P (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \ + R4 = BYTEOP1P (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n); + BYTEOP1P(0) + BYTEOP1P(1) + BYTEOP1P(2) + BYTEOP1P(3) + +#define BYTEOP2P(n) \ + R7 = BYTEOP2P (R1:0, R3:2) (TL) || R4 = [I##n]; EXP (R4, n); \ + R6 = BYTEOP2P (R1:0, R3:2) (TH) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + R5 = BYTEOP2P (R1:0, R3:2) (RNDL) || R6 = [I##n++]; EXP (R6, n); \ + R4 = BYTEOP2P (R1:0, R3:2) (RNDH) || R7 = [I##n--]; EXP (R7, n); + BYTEOP2P(0) + BYTEOP2P(1) + BYTEOP2P(2) + BYTEOP2P(3) + +#define BYTEOP3P(n) \ + R7 = BYTEOP3P (R1:0, R3:2) (LO) || R4 = [I##n]; EXP (R4, n); \ + R6 = BYTEOP3P (R1:0, R3:2) (HI) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + R5 = BYTEOP3P (R1:0, R3:2) (LO) || R6 = [I##n++]; EXP (R6, n); \ + R4 = BYTEOP3P (R1:0, R3:2) (HI) || R7 = [I##n--]; EXP (R7, n); + BYTEOP3P(0) + BYTEOP3P(1) + BYTEOP3P(2) + BYTEOP3P(3) + +#define BYTEOP16P(n) \ + (R7, R6) = BYTEOP16P (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \ + (R6, R4) = BYTEOP16P (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + (R5, R7) = BYTEOP16P (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \ + (R4, R6) = BYTEOP16P (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n); + BYTEOP16P(0) + BYTEOP16P(1) + BYTEOP16P(2) + BYTEOP16P(3) + +#define BYTEOP16M(n) \ + (R7, R5) = BYTEOP16M (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \ + (R6, R7) = BYTEOP16M (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + (R5, R4) = BYTEOP16M (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \ + (R4, R5) = BYTEOP16M (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n); + BYTEOP16M(0) + BYTEOP16M(1) + BYTEOP16M(2) + BYTEOP16M(3) + + pass diff --git a/sim/testsuite/bfin/div0.s b/sim/testsuite/bfin/div0.s new file mode 100644 index 0000000..e52fe45 --- /dev/null +++ b/sim/testsuite/bfin/div0.s @@ -0,0 +1,37 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 70 (X); + R1 = 5; + + P2 = 16; + DIVS ( R0 , R1 ); + LSETUP ( s0 , s0 ) LC0 = P2; +s0: + DIVQ ( R0 , R1 ); + + DBGA ( R0.L , 14 ); + + R0 = 3272 (X); + R1 = 55; + + DIVS ( R0 , R1 ); + LSETUP ( s1 , s1 ) LC0 = P2; +s1: + DIVQ ( R0 , R1 ); + + DBGA ( R0.L , 59 ); + + R0 = 32767 (X); + R1 = 55; + DIVS ( R0 , R1 ); + + LSETUP ( s2 , s2 ) LC0 = P2; +s2: + DIVQ ( R0 , R1 ); + + DBGA ( R0.L , 595 ); + + pass diff --git a/sim/testsuite/bfin/divq.s b/sim/testsuite/bfin/divq.s new file mode 100644 index 0000000..6cb881b --- /dev/null +++ b/sim/testsuite/bfin/divq.s @@ -0,0 +1,1322 @@ +# Blackfin testcase for divide instructions +# mach: bfin + + + .include "testutils.inc" + + start + + /* + * Evaluate given a signed integer dividend and signed interger divisor + * input is: + * r0 = dividend, or numerator + * r1 = divisor, or denominator + * output is: + * r0 = quotient (16-bits) + */ + .macro divide num:req, den:req + imm32 r0 \num + r1 = \den (Z); + + r0 <<= 1; /* Left shift dividend by 1 needed for integer division */ + p0 = 15; /* Evaluate the quotient to 16 bits. */ + + /* Initialize AQ status bit and dividend for the DIVQ loop. */ + divs (r0, r1); + + /* Evaluate DIVQ p0=15 times. */ + lsetup (1f, 1f) lc0=p0; +1: + divq (r0, r1); + + /* Sign extend the 16-bit quotient to 32bits. */ + r0 = r0.l (x); + + imm32 r1, (\num / \den); + CC = r0 == r1 + if CC jump 2f; + fail +2: + .endm + + /* test a bunch of values, making sure not to : + * - exceed a signed 16-bit divisor + * - exceed a signed 16-bit answer + */ + divide 0x00000001, 0x0001 /* expect 0x0001 */ + divide 0x00000001, 0x0002 /* expect 0x0000 */ + divide 0x00000001, 0x0003 /* expect 0x0000 */ + divide 0x00000001, 0x0004 /* expect 0x0000 */ + divide 0x00000001, 0x0007 /* expect 0x0000 */ + divide 0x00000001, 0x0008 /* expect 0x0000 */ + divide 0x00000001, 0x000f /* expect 0x0000 */ + divide 0x00000001, 0x0010 /* expect 0x0000 */ + divide 0x00000001, 0x001f /* expect 0x0000 */ + divide 0x00000001, 0x0020 /* expect 0x0000 */ + divide 0x00000001, 0x003f /* expect 0x0000 */ + divide 0x00000001, 0x0040 /* expect 0x0000 */ + divide 0x00000001, 0x007f /* expect 0x0000 */ + divide 0x00000001, 0x0080 /* expect 0x0000 */ + divide 0x00000001, 0x00ff /* expect 0x0000 */ + divide 0x00000001, 0x0100 /* expect 0x0000 */ + divide 0x00000001, 0x01ff /* expect 0x0000 */ + divide 0x00000001, 0x0200 /* expect 0x0000 */ + divide 0x00000001, 0x03ff /* expect 0x0000 */ + divide 0x00000001, 0x0400 /* expect 0x0000 */ + divide 0x00000001, 0x07ff /* expect 0x0000 */ + divide 0x00000001, 0x0800 /* expect 0x0000 */ + divide 0x00000001, 0x0fff /* expect 0x0000 */ + divide 0x00000001, 0x1000 /* expect 0x0000 */ + divide 0x00000001, 0x1fff /* expect 0x0000 */ + divide 0x00000001, 0x2000 /* expect 0x0000 */ + divide 0x00000001, 0x3fff /* expect 0x0000 */ + divide 0x00000001, 0x4000 /* expect 0x0000 */ + divide 0x00000001, 0x7fff /* expect 0x0000 */ + divide 0x00000002, 0x0001 /* expect 0x0002 */ + divide 0x00000002, 0x0002 /* expect 0x0001 */ + divide 0x00000002, 0x0003 /* expect 0x0000 */ + divide 0x00000002, 0x0004 /* expect 0x0000 */ + divide 0x00000002, 0x0007 /* expect 0x0000 */ + divide 0x00000002, 0x0008 /* expect 0x0000 */ + divide 0x00000002, 0x000f /* expect 0x0000 */ + divide 0x00000002, 0x0010 /* expect 0x0000 */ + divide 0x00000002, 0x001f /* expect 0x0000 */ + divide 0x00000002, 0x0020 /* expect 0x0000 */ + divide 0x00000002, 0x003f /* expect 0x0000 */ + divide 0x00000002, 0x0040 /* expect 0x0000 */ + divide 0x00000002, 0x007f /* expect 0x0000 */ + divide 0x00000002, 0x0080 /* expect 0x0000 */ + divide 0x00000002, 0x00ff /* expect 0x0000 */ + divide 0x00000002, 0x0100 /* expect 0x0000 */ + divide 0x00000002, 0x01ff /* expect 0x0000 */ + divide 0x00000002, 0x0200 /* expect 0x0000 */ + divide 0x00000002, 0x03ff /* expect 0x0000 */ + divide 0x00000002, 0x0400 /* expect 0x0000 */ + divide 0x00000002, 0x07ff /* expect 0x0000 */ + divide 0x00000002, 0x0800 /* expect 0x0000 */ + divide 0x00000002, 0x0fff /* expect 0x0000 */ + divide 0x00000002, 0x1000 /* expect 0x0000 */ + divide 0x00000002, 0x1fff /* expect 0x0000 */ + divide 0x00000002, 0x2000 /* expect 0x0000 */ + divide 0x00000002, 0x3fff /* expect 0x0000 */ + divide 0x00000002, 0x4000 /* expect 0x0000 */ + divide 0x00000002, 0x7fff /* expect 0x0000 */ + divide 0x00000003, 0x0001 /* expect 0x0003 */ + divide 0x00000003, 0x0002 /* expect 0x0001 */ + divide 0x00000003, 0x0003 /* expect 0x0001 */ + divide 0x00000003, 0x0004 /* expect 0x0000 */ + divide 0x00000003, 0x0007 /* expect 0x0000 */ + divide 0x00000003, 0x0008 /* expect 0x0000 */ + divide 0x00000003, 0x000f /* expect 0x0000 */ + divide 0x00000003, 0x0010 /* expect 0x0000 */ + divide 0x00000003, 0x001f /* expect 0x0000 */ + divide 0x00000003, 0x0020 /* expect 0x0000 */ + divide 0x00000003, 0x003f /* expect 0x0000 */ + divide 0x00000003, 0x0040 /* expect 0x0000 */ + divide 0x00000003, 0x007f /* expect 0x0000 */ + divide 0x00000003, 0x0080 /* expect 0x0000 */ + divide 0x00000003, 0x00ff /* expect 0x0000 */ + divide 0x00000003, 0x0100 /* expect 0x0000 */ + divide 0x00000003, 0x01ff /* expect 0x0000 */ + divide 0x00000003, 0x0200 /* expect 0x0000 */ + divide 0x00000003, 0x03ff /* expect 0x0000 */ + divide 0x00000003, 0x0400 /* expect 0x0000 */ + divide 0x00000003, 0x07ff /* expect 0x0000 */ + divide 0x00000003, 0x0800 /* expect 0x0000 */ + divide 0x00000003, 0x0fff /* expect 0x0000 */ + divide 0x00000003, 0x1000 /* expect 0x0000 */ + divide 0x00000003, 0x1fff /* expect 0x0000 */ + divide 0x00000003, 0x2000 /* expect 0x0000 */ + divide 0x00000003, 0x3fff /* expect 0x0000 */ + divide 0x00000003, 0x4000 /* expect 0x0000 */ + divide 0x00000003, 0x7fff /* expect 0x0000 */ + divide 0x00000004, 0x0001 /* expect 0x0004 */ + divide 0x00000004, 0x0002 /* expect 0x0002 */ + divide 0x00000004, 0x0003 /* expect 0x0001 */ + divide 0x00000004, 0x0004 /* expect 0x0001 */ + divide 0x00000004, 0x0007 /* expect 0x0000 */ + divide 0x00000004, 0x0008 /* expect 0x0000 */ + divide 0x00000004, 0x000f /* expect 0x0000 */ + divide 0x00000004, 0x0010 /* expect 0x0000 */ + divide 0x00000004, 0x001f /* expect 0x0000 */ + divide 0x00000004, 0x0020 /* expect 0x0000 */ + divide 0x00000004, 0x003f /* expect 0x0000 */ + divide 0x00000004, 0x0040 /* expect 0x0000 */ + divide 0x00000004, 0x007f /* expect 0x0000 */ + divide 0x00000004, 0x0080 /* expect 0x0000 */ + divide 0x00000004, 0x00ff /* expect 0x0000 */ + divide 0x00000004, 0x0100 /* expect 0x0000 */ + divide 0x00000004, 0x01ff /* expect 0x0000 */ + divide 0x00000004, 0x0200 /* expect 0x0000 */ + divide 0x00000004, 0x03ff /* expect 0x0000 */ + divide 0x00000004, 0x0400 /* expect 0x0000 */ + divide 0x00000004, 0x07ff /* expect 0x0000 */ + divide 0x00000004, 0x0800 /* expect 0x0000 */ + divide 0x00000004, 0x0fff /* expect 0x0000 */ + divide 0x00000004, 0x1000 /* expect 0x0000 */ + divide 0x00000004, 0x1fff /* expect 0x0000 */ + divide 0x00000004, 0x2000 /* expect 0x0000 */ + divide 0x00000004, 0x3fff /* expect 0x0000 */ + divide 0x00000004, 0x4000 /* expect 0x0000 */ + divide 0x00000004, 0x7fff /* expect 0x0000 */ + divide 0x00000007, 0x0001 /* expect 0x0007 */ + divide 0x00000007, 0x0002 /* expect 0x0003 */ + divide 0x00000007, 0x0003 /* expect 0x0002 */ + divide 0x00000007, 0x0004 /* expect 0x0001 */ + divide 0x00000007, 0x0007 /* expect 0x0001 */ + divide 0x00000007, 0x0008 /* expect 0x0000 */ + divide 0x00000007, 0x000f /* expect 0x0000 */ + divide 0x00000007, 0x0010 /* expect 0x0000 */ + divide 0x00000007, 0x001f /* expect 0x0000 */ + divide 0x00000007, 0x0020 /* expect 0x0000 */ + divide 0x00000007, 0x003f /* expect 0x0000 */ + divide 0x00000007, 0x0040 /* expect 0x0000 */ + divide 0x00000007, 0x007f /* expect 0x0000 */ + divide 0x00000007, 0x0080 /* expect 0x0000 */ + divide 0x00000007, 0x00ff /* expect 0x0000 */ + divide 0x00000007, 0x0100 /* expect 0x0000 */ + divide 0x00000007, 0x01ff /* expect 0x0000 */ + divide 0x00000007, 0x0200 /* expect 0x0000 */ + divide 0x00000007, 0x03ff /* expect 0x0000 */ + divide 0x00000007, 0x0400 /* expect 0x0000 */ + divide 0x00000007, 0x07ff /* expect 0x0000 */ + divide 0x00000007, 0x0800 /* expect 0x0000 */ + divide 0x00000007, 0x0fff /* expect 0x0000 */ + divide 0x00000007, 0x1000 /* expect 0x0000 */ + divide 0x00000007, 0x1fff /* expect 0x0000 */ + divide 0x00000007, 0x2000 /* expect 0x0000 */ + divide 0x00000007, 0x3fff /* expect 0x0000 */ + divide 0x00000007, 0x4000 /* expect 0x0000 */ + divide 0x00000007, 0x7fff /* expect 0x0000 */ + divide 0x00000008, 0x0001 /* expect 0x0008 */ + divide 0x00000008, 0x0002 /* expect 0x0004 */ + divide 0x00000008, 0x0003 /* expect 0x0002 */ + divide 0x00000008, 0x0004 /* expect 0x0002 */ + divide 0x00000008, 0x0007 /* expect 0x0001 */ + divide 0x00000008, 0x0008 /* expect 0x0001 */ + divide 0x00000008, 0x000f /* expect 0x0000 */ + divide 0x00000008, 0x0010 /* expect 0x0000 */ + divide 0x00000008, 0x001f /* expect 0x0000 */ + divide 0x00000008, 0x0020 /* expect 0x0000 */ + divide 0x00000008, 0x003f /* expect 0x0000 */ + divide 0x00000008, 0x0040 /* expect 0x0000 */ + divide 0x00000008, 0x007f /* expect 0x0000 */ + divide 0x00000008, 0x0080 /* expect 0x0000 */ + divide 0x00000008, 0x00ff /* expect 0x0000 */ + divide 0x00000008, 0x0100 /* expect 0x0000 */ + divide 0x00000008, 0x01ff /* expect 0x0000 */ + divide 0x00000008, 0x0200 /* expect 0x0000 */ + divide 0x00000008, 0x03ff /* expect 0x0000 */ + divide 0x00000008, 0x0400 /* expect 0x0000 */ + divide 0x00000008, 0x07ff /* expect 0x0000 */ + divide 0x00000008, 0x0800 /* expect 0x0000 */ + divide 0x00000008, 0x0fff /* expect 0x0000 */ + divide 0x00000008, 0x1000 /* expect 0x0000 */ + divide 0x00000008, 0x1fff /* expect 0x0000 */ + divide 0x00000008, 0x2000 /* expect 0x0000 */ + divide 0x00000008, 0x3fff /* expect 0x0000 */ + divide 0x00000008, 0x4000 /* expect 0x0000 */ + divide 0x00000008, 0x7fff /* expect 0x0000 */ + divide 0x0000000f, 0x0001 /* expect 0x000f */ + divide 0x0000000f, 0x0002 /* expect 0x0007 */ + divide 0x0000000f, 0x0003 /* expect 0x0005 */ + divide 0x0000000f, 0x0004 /* expect 0x0003 */ + divide 0x0000000f, 0x0007 /* expect 0x0002 */ + divide 0x0000000f, 0x0008 /* expect 0x0001 */ + divide 0x0000000f, 0x000f /* expect 0x0001 */ + divide 0x0000000f, 0x0010 /* expect 0x0000 */ + divide 0x0000000f, 0x001f /* expect 0x0000 */ + divide 0x0000000f, 0x0020 /* expect 0x0000 */ + divide 0x0000000f, 0x003f /* expect 0x0000 */ + divide 0x0000000f, 0x0040 /* expect 0x0000 */ + divide 0x0000000f, 0x007f /* expect 0x0000 */ + divide 0x0000000f, 0x0080 /* expect 0x0000 */ + divide 0x0000000f, 0x00ff /* expect 0x0000 */ + divide 0x0000000f, 0x0100 /* expect 0x0000 */ + divide 0x0000000f, 0x01ff /* expect 0x0000 */ + divide 0x0000000f, 0x0200 /* expect 0x0000 */ + divide 0x0000000f, 0x03ff /* expect 0x0000 */ + divide 0x0000000f, 0x0400 /* expect 0x0000 */ + divide 0x0000000f, 0x07ff /* expect 0x0000 */ + divide 0x0000000f, 0x0800 /* expect 0x0000 */ + divide 0x0000000f, 0x0fff /* expect 0x0000 */ + divide 0x0000000f, 0x1000 /* expect 0x0000 */ + divide 0x0000000f, 0x1fff /* expect 0x0000 */ + divide 0x0000000f, 0x2000 /* expect 0x0000 */ + divide 0x0000000f, 0x3fff /* expect 0x0000 */ + divide 0x0000000f, 0x4000 /* expect 0x0000 */ + divide 0x0000000f, 0x7fff /* expect 0x0000 */ + divide 0x00000010, 0x0001 /* expect 0x0010 */ + divide 0x00000010, 0x0002 /* expect 0x0008 */ + divide 0x00000010, 0x0003 /* expect 0x0005 */ + divide 0x00000010, 0x0004 /* expect 0x0004 */ + divide 0x00000010, 0x0007 /* expect 0x0002 */ + divide 0x00000010, 0x0008 /* expect 0x0002 */ + divide 0x00000010, 0x000f /* expect 0x0001 */ + divide 0x00000010, 0x0010 /* expect 0x0001 */ + divide 0x00000010, 0x001f /* expect 0x0000 */ + divide 0x00000010, 0x0020 /* expect 0x0000 */ + divide 0x00000010, 0x003f /* expect 0x0000 */ + divide 0x00000010, 0x0040 /* expect 0x0000 */ + divide 0x00000010, 0x007f /* expect 0x0000 */ + divide 0x00000010, 0x0080 /* expect 0x0000 */ + divide 0x00000010, 0x00ff /* expect 0x0000 */ + divide 0x00000010, 0x0100 /* expect 0x0000 */ + divide 0x00000010, 0x01ff /* expect 0x0000 */ + divide 0x00000010, 0x0200 /* expect 0x0000 */ + divide 0x00000010, 0x03ff /* expect 0x0000 */ + divide 0x00000010, 0x0400 /* expect 0x0000 */ + divide 0x00000010, 0x07ff /* expect 0x0000 */ + divide 0x00000010, 0x0800 /* expect 0x0000 */ + divide 0x00000010, 0x0fff /* expect 0x0000 */ + divide 0x00000010, 0x1000 /* expect 0x0000 */ + divide 0x00000010, 0x1fff /* expect 0x0000 */ + divide 0x00000010, 0x2000 /* expect 0x0000 */ + divide 0x00000010, 0x3fff /* expect 0x0000 */ + divide 0x00000010, 0x4000 /* expect 0x0000 */ + divide 0x00000010, 0x7fff /* expect 0x0000 */ + divide 0x0000001f, 0x0001 /* expect 0x001f */ + divide 0x0000001f, 0x0002 /* expect 0x000f */ + divide 0x0000001f, 0x0003 /* expect 0x000a */ + divide 0x0000001f, 0x0004 /* expect 0x0007 */ + divide 0x0000001f, 0x0007 /* expect 0x0004 */ + divide 0x0000001f, 0x0008 /* expect 0x0003 */ + divide 0x0000001f, 0x000f /* expect 0x0002 */ + divide 0x0000001f, 0x0010 /* expect 0x0001 */ + divide 0x0000001f, 0x001f /* expect 0x0001 */ + divide 0x0000001f, 0x0020 /* expect 0x0000 */ + divide 0x0000001f, 0x003f /* expect 0x0000 */ + divide 0x0000001f, 0x0040 /* expect 0x0000 */ + divide 0x0000001f, 0x007f /* expect 0x0000 */ + divide 0x0000001f, 0x0080 /* expect 0x0000 */ + divide 0x0000001f, 0x00ff /* expect 0x0000 */ + divide 0x0000001f, 0x0100 /* expect 0x0000 */ + divide 0x0000001f, 0x01ff /* expect 0x0000 */ + divide 0x0000001f, 0x0200 /* expect 0x0000 */ + divide 0x0000001f, 0x03ff /* expect 0x0000 */ + divide 0x0000001f, 0x0400 /* expect 0x0000 */ + divide 0x0000001f, 0x07ff /* expect 0x0000 */ + divide 0x0000001f, 0x0800 /* expect 0x0000 */ + divide 0x0000001f, 0x0fff /* expect 0x0000 */ + divide 0x0000001f, 0x1000 /* expect 0x0000 */ + divide 0x0000001f, 0x1fff /* expect 0x0000 */ + divide 0x0000001f, 0x2000 /* expect 0x0000 */ + divide 0x0000001f, 0x3fff /* expect 0x0000 */ + divide 0x0000001f, 0x4000 /* expect 0x0000 */ + divide 0x0000001f, 0x7fff /* expect 0x0000 */ + divide 0x00000020, 0x0001 /* expect 0x0020 */ + divide 0x00000020, 0x0002 /* expect 0x0010 */ + divide 0x00000020, 0x0003 /* expect 0x000a */ + divide 0x00000020, 0x0004 /* expect 0x0008 */ + divide 0x00000020, 0x0007 /* expect 0x0004 */ + divide 0x00000020, 0x0008 /* expect 0x0004 */ + divide 0x00000020, 0x000f /* expect 0x0002 */ + divide 0x00000020, 0x0010 /* expect 0x0002 */ + divide 0x00000020, 0x001f /* expect 0x0001 */ + divide 0x00000020, 0x0020 /* expect 0x0001 */ + divide 0x00000020, 0x003f /* expect 0x0000 */ + divide 0x00000020, 0x0040 /* expect 0x0000 */ + divide 0x00000020, 0x007f /* expect 0x0000 */ + divide 0x00000020, 0x0080 /* expect 0x0000 */ + divide 0x00000020, 0x00ff /* expect 0x0000 */ + divide 0x00000020, 0x0100 /* expect 0x0000 */ + divide 0x00000020, 0x01ff /* expect 0x0000 */ + divide 0x00000020, 0x0200 /* expect 0x0000 */ + divide 0x00000020, 0x03ff /* expect 0x0000 */ + divide 0x00000020, 0x0400 /* expect 0x0000 */ + divide 0x00000020, 0x07ff /* expect 0x0000 */ + divide 0x00000020, 0x0800 /* expect 0x0000 */ + divide 0x00000020, 0x0fff /* expect 0x0000 */ + divide 0x00000020, 0x1000 /* expect 0x0000 */ + divide 0x00000020, 0x1fff /* expect 0x0000 */ + divide 0x00000020, 0x2000 /* expect 0x0000 */ + divide 0x00000020, 0x3fff /* expect 0x0000 */ + divide 0x00000020, 0x4000 /* expect 0x0000 */ + divide 0x00000020, 0x7fff /* expect 0x0000 */ + divide 0x0000003f, 0x0001 /* expect 0x003f */ + divide 0x0000003f, 0x0002 /* expect 0x001f */ + divide 0x0000003f, 0x0003 /* expect 0x0015 */ + divide 0x0000003f, 0x0004 /* expect 0x000f */ + divide 0x0000003f, 0x0007 /* expect 0x0009 */ + divide 0x0000003f, 0x0008 /* expect 0x0007 */ + divide 0x0000003f, 0x000f /* expect 0x0004 */ + divide 0x0000003f, 0x0010 /* expect 0x0003 */ + divide 0x0000003f, 0x001f /* expect 0x0002 */ + divide 0x0000003f, 0x0020 /* expect 0x0001 */ + divide 0x0000003f, 0x003f /* expect 0x0001 */ + divide 0x0000003f, 0x0040 /* expect 0x0000 */ + divide 0x0000003f, 0x007f /* expect 0x0000 */ + divide 0x0000003f, 0x0080 /* expect 0x0000 */ + divide 0x0000003f, 0x00ff /* expect 0x0000 */ + divide 0x0000003f, 0x0100 /* expect 0x0000 */ + divide 0x0000003f, 0x01ff /* expect 0x0000 */ + divide 0x0000003f, 0x0200 /* expect 0x0000 */ + divide 0x0000003f, 0x03ff /* expect 0x0000 */ + divide 0x0000003f, 0x0400 /* expect 0x0000 */ + divide 0x0000003f, 0x07ff /* expect 0x0000 */ + divide 0x0000003f, 0x0800 /* expect 0x0000 */ + divide 0x0000003f, 0x0fff /* expect 0x0000 */ + divide 0x0000003f, 0x1000 /* expect 0x0000 */ + divide 0x0000003f, 0x1fff /* expect 0x0000 */ + divide 0x0000003f, 0x2000 /* expect 0x0000 */ + divide 0x0000003f, 0x3fff /* expect 0x0000 */ + divide 0x0000003f, 0x4000 /* expect 0x0000 */ + divide 0x0000003f, 0x7fff /* expect 0x0000 */ + divide 0x00000040, 0x0001 /* expect 0x0040 */ + divide 0x00000040, 0x0002 /* expect 0x0020 */ + divide 0x00000040, 0x0003 /* expect 0x0015 */ + divide 0x00000040, 0x0004 /* expect 0x0010 */ + divide 0x00000040, 0x0007 /* expect 0x0009 */ + divide 0x00000040, 0x0008 /* expect 0x0008 */ + divide 0x00000040, 0x000f /* expect 0x0004 */ + divide 0x00000040, 0x0010 /* expect 0x0004 */ + divide 0x00000040, 0x001f /* expect 0x0002 */ + divide 0x00000040, 0x0020 /* expect 0x0002 */ + divide 0x00000040, 0x003f /* expect 0x0001 */ + divide 0x00000040, 0x0040 /* expect 0x0001 */ + divide 0x00000040, 0x007f /* expect 0x0000 */ + divide 0x00000040, 0x0080 /* expect 0x0000 */ + divide 0x00000040, 0x00ff /* expect 0x0000 */ + divide 0x00000040, 0x0100 /* expect 0x0000 */ + divide 0x00000040, 0x01ff /* expect 0x0000 */ + divide 0x00000040, 0x0200 /* expect 0x0000 */ + divide 0x00000040, 0x03ff /* expect 0x0000 */ + divide 0x00000040, 0x0400 /* expect 0x0000 */ + divide 0x00000040, 0x07ff /* expect 0x0000 */ + divide 0x00000040, 0x0800 /* expect 0x0000 */ + divide 0x00000040, 0x0fff /* expect 0x0000 */ + divide 0x00000040, 0x1000 /* expect 0x0000 */ + divide 0x00000040, 0x1fff /* expect 0x0000 */ + divide 0x00000040, 0x2000 /* expect 0x0000 */ + divide 0x00000040, 0x3fff /* expect 0x0000 */ + divide 0x00000040, 0x4000 /* expect 0x0000 */ + divide 0x00000040, 0x7fff /* expect 0x0000 */ + divide 0x0000007f, 0x0001 /* expect 0x007f */ + divide 0x0000007f, 0x0002 /* expect 0x003f */ + divide 0x0000007f, 0x0003 /* expect 0x002a */ + divide 0x0000007f, 0x0004 /* expect 0x001f */ + divide 0x0000007f, 0x0007 /* expect 0x0012 */ + divide 0x0000007f, 0x0008 /* expect 0x000f */ + divide 0x0000007f, 0x000f /* expect 0x0008 */ + divide 0x0000007f, 0x0010 /* expect 0x0007 */ + divide 0x0000007f, 0x001f /* expect 0x0004 */ + divide 0x0000007f, 0x0020 /* expect 0x0003 */ + divide 0x0000007f, 0x003f /* expect 0x0002 */ + divide 0x0000007f, 0x0040 /* expect 0x0001 */ + divide 0x0000007f, 0x007f /* expect 0x0001 */ + divide 0x0000007f, 0x0080 /* expect 0x0000 */ + divide 0x0000007f, 0x00ff /* expect 0x0000 */ + divide 0x0000007f, 0x0100 /* expect 0x0000 */ + divide 0x0000007f, 0x01ff /* expect 0x0000 */ + divide 0x0000007f, 0x0200 /* expect 0x0000 */ + divide 0x0000007f, 0x03ff /* expect 0x0000 */ + divide 0x0000007f, 0x0400 /* expect 0x0000 */ + divide 0x0000007f, 0x07ff /* expect 0x0000 */ + divide 0x0000007f, 0x0800 /* expect 0x0000 */ + divide 0x0000007f, 0x0fff /* expect 0x0000 */ + divide 0x0000007f, 0x1000 /* expect 0x0000 */ + divide 0x0000007f, 0x1fff /* expect 0x0000 */ + divide 0x0000007f, 0x2000 /* expect 0x0000 */ + divide 0x0000007f, 0x3fff /* expect 0x0000 */ + divide 0x0000007f, 0x4000 /* expect 0x0000 */ + divide 0x0000007f, 0x7fff /* expect 0x0000 */ + divide 0x00000080, 0x0001 /* expect 0x0080 */ + divide 0x00000080, 0x0002 /* expect 0x0040 */ + divide 0x00000080, 0x0003 /* expect 0x002a */ + divide 0x00000080, 0x0004 /* expect 0x0020 */ + divide 0x00000080, 0x0007 /* expect 0x0012 */ + divide 0x00000080, 0x0008 /* expect 0x0010 */ + divide 0x00000080, 0x000f /* expect 0x0008 */ + divide 0x00000080, 0x0010 /* expect 0x0008 */ + divide 0x00000080, 0x001f /* expect 0x0004 */ + divide 0x00000080, 0x0020 /* expect 0x0004 */ + divide 0x00000080, 0x003f /* expect 0x0002 */ + divide 0x00000080, 0x0040 /* expect 0x0002 */ + divide 0x00000080, 0x007f /* expect 0x0001 */ + divide 0x00000080, 0x0080 /* expect 0x0001 */ + divide 0x00000080, 0x00ff /* expect 0x0000 */ + divide 0x00000080, 0x0100 /* expect 0x0000 */ + divide 0x00000080, 0x01ff /* expect 0x0000 */ + divide 0x00000080, 0x0200 /* expect 0x0000 */ + divide 0x00000080, 0x03ff /* expect 0x0000 */ + divide 0x00000080, 0x0400 /* expect 0x0000 */ + divide 0x00000080, 0x07ff /* expect 0x0000 */ + divide 0x00000080, 0x0800 /* expect 0x0000 */ + divide 0x00000080, 0x0fff /* expect 0x0000 */ + divide 0x00000080, 0x1000 /* expect 0x0000 */ + divide 0x00000080, 0x1fff /* expect 0x0000 */ + divide 0x00000080, 0x2000 /* expect 0x0000 */ + divide 0x00000080, 0x3fff /* expect 0x0000 */ + divide 0x00000080, 0x4000 /* expect 0x0000 */ + divide 0x00000080, 0x7fff /* expect 0x0000 */ + divide 0x000000ff, 0x0001 /* expect 0x00ff */ + divide 0x000000ff, 0x0002 /* expect 0x007f */ + divide 0x000000ff, 0x0003 /* expect 0x0055 */ + divide 0x000000ff, 0x0004 /* expect 0x003f */ + divide 0x000000ff, 0x0007 /* expect 0x0024 */ + divide 0x000000ff, 0x0008 /* expect 0x001f */ + divide 0x000000ff, 0x000f /* expect 0x0011 */ + divide 0x000000ff, 0x0010 /* expect 0x000f */ + divide 0x000000ff, 0x001f /* expect 0x0008 */ + divide 0x000000ff, 0x0020 /* expect 0x0007 */ + divide 0x000000ff, 0x003f /* expect 0x0004 */ + divide 0x000000ff, 0x0040 /* expect 0x0003 */ + divide 0x000000ff, 0x007f /* expect 0x0002 */ + divide 0x000000ff, 0x0080 /* expect 0x0001 */ + divide 0x000000ff, 0x00ff /* expect 0x0001 */ + divide 0x000000ff, 0x0100 /* expect 0x0000 */ + divide 0x000000ff, 0x01ff /* expect 0x0000 */ + divide 0x000000ff, 0x0200 /* expect 0x0000 */ + divide 0x000000ff, 0x03ff /* expect 0x0000 */ + divide 0x000000ff, 0x0400 /* expect 0x0000 */ + divide 0x000000ff, 0x07ff /* expect 0x0000 */ + divide 0x000000ff, 0x0800 /* expect 0x0000 */ + divide 0x000000ff, 0x0fff /* expect 0x0000 */ + divide 0x000000ff, 0x1000 /* expect 0x0000 */ + divide 0x000000ff, 0x1fff /* expect 0x0000 */ + divide 0x000000ff, 0x2000 /* expect 0x0000 */ + divide 0x000000ff, 0x3fff /* expect 0x0000 */ + divide 0x000000ff, 0x4000 /* expect 0x0000 */ + divide 0x000000ff, 0x7fff /* expect 0x0000 */ + divide 0x00000100, 0x0001 /* expect 0x0100 */ + divide 0x00000100, 0x0002 /* expect 0x0080 */ + divide 0x00000100, 0x0003 /* expect 0x0055 */ + divide 0x00000100, 0x0004 /* expect 0x0040 */ + divide 0x00000100, 0x0007 /* expect 0x0024 */ + divide 0x00000100, 0x0008 /* expect 0x0020 */ + divide 0x00000100, 0x000f /* expect 0x0011 */ + divide 0x00000100, 0x0010 /* expect 0x0010 */ + divide 0x00000100, 0x001f /* expect 0x0008 */ + divide 0x00000100, 0x0020 /* expect 0x0008 */ + divide 0x00000100, 0x003f /* expect 0x0004 */ + divide 0x00000100, 0x0040 /* expect 0x0004 */ + divide 0x00000100, 0x007f /* expect 0x0002 */ + divide 0x00000100, 0x0080 /* expect 0x0002 */ + divide 0x00000100, 0x00ff /* expect 0x0001 */ + divide 0x00000100, 0x0100 /* expect 0x0001 */ + divide 0x00000100, 0x01ff /* expect 0x0000 */ + divide 0x00000100, 0x0200 /* expect 0x0000 */ + divide 0x00000100, 0x03ff /* expect 0x0000 */ + divide 0x00000100, 0x0400 /* expect 0x0000 */ + divide 0x00000100, 0x07ff /* expect 0x0000 */ + divide 0x00000100, 0x0800 /* expect 0x0000 */ + divide 0x00000100, 0x0fff /* expect 0x0000 */ + divide 0x00000100, 0x1000 /* expect 0x0000 */ + divide 0x00000100, 0x1fff /* expect 0x0000 */ + divide 0x00000100, 0x2000 /* expect 0x0000 */ + divide 0x00000100, 0x3fff /* expect 0x0000 */ + divide 0x00000100, 0x4000 /* expect 0x0000 */ + divide 0x00000100, 0x7fff /* expect 0x0000 */ + divide 0x000001ff, 0x0001 /* expect 0x01ff */ + divide 0x000001ff, 0x0002 /* expect 0x00ff */ + divide 0x000001ff, 0x0003 /* expect 0x00aa */ + divide 0x000001ff, 0x0004 /* expect 0x007f */ + divide 0x000001ff, 0x0007 /* expect 0x0049 */ + divide 0x000001ff, 0x0008 /* expect 0x003f */ + divide 0x000001ff, 0x000f /* expect 0x0022 */ + divide 0x000001ff, 0x0010 /* expect 0x001f */ + divide 0x000001ff, 0x001f /* expect 0x0010 */ + divide 0x000001ff, 0x0020 /* expect 0x000f */ + divide 0x000001ff, 0x003f /* expect 0x0008 */ + divide 0x000001ff, 0x0040 /* expect 0x0007 */ + divide 0x000001ff, 0x007f /* expect 0x0004 */ + divide 0x000001ff, 0x0080 /* expect 0x0003 */ + divide 0x000001ff, 0x00ff /* expect 0x0002 */ + divide 0x000001ff, 0x0100 /* expect 0x0001 */ + divide 0x000001ff, 0x01ff /* expect 0x0001 */ + divide 0x000001ff, 0x0200 /* expect 0x0000 */ + divide 0x000001ff, 0x03ff /* expect 0x0000 */ + divide 0x000001ff, 0x0400 /* expect 0x0000 */ + divide 0x000001ff, 0x07ff /* expect 0x0000 */ + divide 0x000001ff, 0x0800 /* expect 0x0000 */ + divide 0x000001ff, 0x0fff /* expect 0x0000 */ + divide 0x000001ff, 0x1000 /* expect 0x0000 */ + divide 0x000001ff, 0x1fff /* expect 0x0000 */ + divide 0x000001ff, 0x2000 /* expect 0x0000 */ + divide 0x000001ff, 0x3fff /* expect 0x0000 */ + divide 0x000001ff, 0x4000 /* expect 0x0000 */ + divide 0x000001ff, 0x7fff /* expect 0x0000 */ + divide 0x00000200, 0x0001 /* expect 0x0200 */ + divide 0x00000200, 0x0002 /* expect 0x0100 */ + divide 0x00000200, 0x0003 /* expect 0x00aa */ + divide 0x00000200, 0x0004 /* expect 0x0080 */ + divide 0x00000200, 0x0007 /* expect 0x0049 */ + divide 0x00000200, 0x0008 /* expect 0x0040 */ + divide 0x00000200, 0x000f /* expect 0x0022 */ + divide 0x00000200, 0x0010 /* expect 0x0020 */ + divide 0x00000200, 0x001f /* expect 0x0010 */ + divide 0x00000200, 0x0020 /* expect 0x0010 */ + divide 0x00000200, 0x003f /* expect 0x0008 */ + divide 0x00000200, 0x0040 /* expect 0x0008 */ + divide 0x00000200, 0x007f /* expect 0x0004 */ + divide 0x00000200, 0x0080 /* expect 0x0004 */ + divide 0x00000200, 0x00ff /* expect 0x0002 */ + divide 0x00000200, 0x0100 /* expect 0x0002 */ + divide 0x00000200, 0x01ff /* expect 0x0001 */ + divide 0x00000200, 0x0200 /* expect 0x0001 */ + divide 0x00000200, 0x03ff /* expect 0x0000 */ + divide 0x00000200, 0x0400 /* expect 0x0000 */ + divide 0x00000200, 0x07ff /* expect 0x0000 */ + divide 0x00000200, 0x0800 /* expect 0x0000 */ + divide 0x00000200, 0x0fff /* expect 0x0000 */ + divide 0x00000200, 0x1000 /* expect 0x0000 */ + divide 0x00000200, 0x1fff /* expect 0x0000 */ + divide 0x00000200, 0x2000 /* expect 0x0000 */ + divide 0x00000200, 0x3fff /* expect 0x0000 */ + divide 0x00000200, 0x4000 /* expect 0x0000 */ + divide 0x00000200, 0x7fff /* expect 0x0000 */ + divide 0x000003ff, 0x0001 /* expect 0x03ff */ + divide 0x000003ff, 0x0002 /* expect 0x01ff */ + divide 0x000003ff, 0x0003 /* expect 0x0155 */ + divide 0x000003ff, 0x0004 /* expect 0x00ff */ + divide 0x000003ff, 0x0007 /* expect 0x0092 */ + divide 0x000003ff, 0x0008 /* expect 0x007f */ + divide 0x000003ff, 0x000f /* expect 0x0044 */ + divide 0x000003ff, 0x0010 /* expect 0x003f */ + divide 0x000003ff, 0x001f /* expect 0x0021 */ + divide 0x000003ff, 0x0020 /* expect 0x001f */ + divide 0x000003ff, 0x003f /* expect 0x0010 */ + divide 0x000003ff, 0x0040 /* expect 0x000f */ + divide 0x000003ff, 0x007f /* expect 0x0008 */ + divide 0x000003ff, 0x0080 /* expect 0x0007 */ + divide 0x000003ff, 0x00ff /* expect 0x0004 */ + divide 0x000003ff, 0x0100 /* expect 0x0003 */ + divide 0x000003ff, 0x01ff /* expect 0x0002 */ + divide 0x000003ff, 0x0200 /* expect 0x0001 */ + divide 0x000003ff, 0x03ff /* expect 0x0001 */ + divide 0x000003ff, 0x0400 /* expect 0x0000 */ + divide 0x000003ff, 0x07ff /* expect 0x0000 */ + divide 0x000003ff, 0x0800 /* expect 0x0000 */ + divide 0x000003ff, 0x0fff /* expect 0x0000 */ + divide 0x000003ff, 0x1000 /* expect 0x0000 */ + divide 0x000003ff, 0x1fff /* expect 0x0000 */ + divide 0x000003ff, 0x2000 /* expect 0x0000 */ + divide 0x000003ff, 0x3fff /* expect 0x0000 */ + divide 0x000003ff, 0x4000 /* expect 0x0000 */ + divide 0x000003ff, 0x7fff /* expect 0x0000 */ + divide 0x00000400, 0x0001 /* expect 0x0400 */ + divide 0x00000400, 0x0002 /* expect 0x0200 */ + divide 0x00000400, 0x0003 /* expect 0x0155 */ + divide 0x00000400, 0x0004 /* expect 0x0100 */ + divide 0x00000400, 0x0007 /* expect 0x0092 */ + divide 0x00000400, 0x0008 /* expect 0x0080 */ + divide 0x00000400, 0x000f /* expect 0x0044 */ + divide 0x00000400, 0x0010 /* expect 0x0040 */ + divide 0x00000400, 0x001f /* expect 0x0021 */ + divide 0x00000400, 0x0020 /* expect 0x0020 */ + divide 0x00000400, 0x003f /* expect 0x0010 */ + divide 0x00000400, 0x0040 /* expect 0x0010 */ + divide 0x00000400, 0x007f /* expect 0x0008 */ + divide 0x00000400, 0x0080 /* expect 0x0008 */ + divide 0x00000400, 0x00ff /* expect 0x0004 */ + divide 0x00000400, 0x0100 /* expect 0x0004 */ + divide 0x00000400, 0x01ff /* expect 0x0002 */ + divide 0x00000400, 0x0200 /* expect 0x0002 */ + divide 0x00000400, 0x03ff /* expect 0x0001 */ + divide 0x00000400, 0x0400 /* expect 0x0001 */ + divide 0x00000400, 0x07ff /* expect 0x0000 */ + divide 0x00000400, 0x0800 /* expect 0x0000 */ + divide 0x00000400, 0x0fff /* expect 0x0000 */ + divide 0x00000400, 0x1000 /* expect 0x0000 */ + divide 0x00000400, 0x1fff /* expect 0x0000 */ + divide 0x00000400, 0x2000 /* expect 0x0000 */ + divide 0x00000400, 0x3fff /* expect 0x0000 */ + divide 0x00000400, 0x4000 /* expect 0x0000 */ + divide 0x00000400, 0x7fff /* expect 0x0000 */ + divide 0x000007ff, 0x0001 /* expect 0x07ff */ + divide 0x000007ff, 0x0002 /* expect 0x03ff */ + divide 0x000007ff, 0x0003 /* expect 0x02aa */ + divide 0x000007ff, 0x0004 /* expect 0x01ff */ + divide 0x000007ff, 0x0007 /* expect 0x0124 */ + divide 0x000007ff, 0x0008 /* expect 0x00ff */ + divide 0x000007ff, 0x000f /* expect 0x0088 */ + divide 0x000007ff, 0x0010 /* expect 0x007f */ + divide 0x000007ff, 0x001f /* expect 0x0042 */ + divide 0x000007ff, 0x0020 /* expect 0x003f */ + divide 0x000007ff, 0x003f /* expect 0x0020 */ + divide 0x000007ff, 0x0040 /* expect 0x001f */ + divide 0x000007ff, 0x007f /* expect 0x0010 */ + divide 0x000007ff, 0x0080 /* expect 0x000f */ + divide 0x000007ff, 0x00ff /* expect 0x0008 */ + divide 0x000007ff, 0x0100 /* expect 0x0007 */ + divide 0x000007ff, 0x01ff /* expect 0x0004 */ + divide 0x000007ff, 0x0200 /* expect 0x0003 */ + divide 0x000007ff, 0x03ff /* expect 0x0002 */ + divide 0x000007ff, 0x0400 /* expect 0x0001 */ + divide 0x000007ff, 0x07ff /* expect 0x0001 */ + divide 0x000007ff, 0x0800 /* expect 0x0000 */ + divide 0x000007ff, 0x0fff /* expect 0x0000 */ + divide 0x000007ff, 0x1000 /* expect 0x0000 */ + divide 0x000007ff, 0x1fff /* expect 0x0000 */ + divide 0x000007ff, 0x2000 /* expect 0x0000 */ + divide 0x000007ff, 0x3fff /* expect 0x0000 */ + divide 0x000007ff, 0x4000 /* expect 0x0000 */ + divide 0x000007ff, 0x7fff /* expect 0x0000 */ + divide 0x00000800, 0x0001 /* expect 0x0800 */ + divide 0x00000800, 0x0002 /* expect 0x0400 */ + divide 0x00000800, 0x0003 /* expect 0x02aa */ + divide 0x00000800, 0x0004 /* expect 0x0200 */ + divide 0x00000800, 0x0007 /* expect 0x0124 */ + divide 0x00000800, 0x0008 /* expect 0x0100 */ + divide 0x00000800, 0x000f /* expect 0x0088 */ + divide 0x00000800, 0x0010 /* expect 0x0080 */ + divide 0x00000800, 0x001f /* expect 0x0042 */ + divide 0x00000800, 0x0020 /* expect 0x0040 */ + divide 0x00000800, 0x003f /* expect 0x0020 */ + divide 0x00000800, 0x0040 /* expect 0x0020 */ + divide 0x00000800, 0x007f /* expect 0x0010 */ + divide 0x00000800, 0x0080 /* expect 0x0010 */ + divide 0x00000800, 0x00ff /* expect 0x0008 */ + divide 0x00000800, 0x0100 /* expect 0x0008 */ + divide 0x00000800, 0x01ff /* expect 0x0004 */ + divide 0x00000800, 0x0200 /* expect 0x0004 */ + divide 0x00000800, 0x03ff /* expect 0x0002 */ + divide 0x00000800, 0x0400 /* expect 0x0002 */ + divide 0x00000800, 0x07ff /* expect 0x0001 */ + divide 0x00000800, 0x0800 /* expect 0x0001 */ + divide 0x00000800, 0x0fff /* expect 0x0000 */ + divide 0x00000800, 0x1000 /* expect 0x0000 */ + divide 0x00000800, 0x1fff /* expect 0x0000 */ + divide 0x00000800, 0x2000 /* expect 0x0000 */ + divide 0x00000800, 0x3fff /* expect 0x0000 */ + divide 0x00000800, 0x4000 /* expect 0x0000 */ + divide 0x00000800, 0x7fff /* expect 0x0000 */ + divide 0x00000fff, 0x0001 /* expect 0x0fff */ + divide 0x00000fff, 0x0002 /* expect 0x07ff */ + divide 0x00000fff, 0x0003 /* expect 0x0555 */ + divide 0x00000fff, 0x0004 /* expect 0x03ff */ + divide 0x00000fff, 0x0007 /* expect 0x0249 */ + divide 0x00000fff, 0x0008 /* expect 0x01ff */ + divide 0x00000fff, 0x000f /* expect 0x0111 */ + divide 0x00000fff, 0x0010 /* expect 0x00ff */ + divide 0x00000fff, 0x001f /* expect 0x0084 */ + divide 0x00000fff, 0x0020 /* expect 0x007f */ + divide 0x00000fff, 0x003f /* expect 0x0041 */ + divide 0x00000fff, 0x0040 /* expect 0x003f */ + divide 0x00000fff, 0x007f /* expect 0x0020 */ + divide 0x00000fff, 0x0080 /* expect 0x001f */ + divide 0x00000fff, 0x00ff /* expect 0x0010 */ + divide 0x00000fff, 0x0100 /* expect 0x000f */ + divide 0x00000fff, 0x01ff /* expect 0x0008 */ + divide 0x00000fff, 0x0200 /* expect 0x0007 */ + divide 0x00000fff, 0x03ff /* expect 0x0004 */ + divide 0x00000fff, 0x0400 /* expect 0x0003 */ + divide 0x00000fff, 0x07ff /* expect 0x0002 */ + divide 0x00000fff, 0x0800 /* expect 0x0001 */ + divide 0x00000fff, 0x0fff /* expect 0x0001 */ + divide 0x00000fff, 0x1000 /* expect 0x0000 */ + divide 0x00000fff, 0x1fff /* expect 0x0000 */ + divide 0x00000fff, 0x2000 /* expect 0x0000 */ + divide 0x00000fff, 0x3fff /* expect 0x0000 */ + divide 0x00000fff, 0x4000 /* expect 0x0000 */ + divide 0x00000fff, 0x7fff /* expect 0x0000 */ + divide 0x00001000, 0x0001 /* expect 0x1000 */ + divide 0x00001000, 0x0002 /* expect 0x0800 */ + divide 0x00001000, 0x0003 /* expect 0x0555 */ + divide 0x00001000, 0x0004 /* expect 0x0400 */ + divide 0x00001000, 0x0007 /* expect 0x0249 */ + divide 0x00001000, 0x0008 /* expect 0x0200 */ + divide 0x00001000, 0x000f /* expect 0x0111 */ + divide 0x00001000, 0x0010 /* expect 0x0100 */ + divide 0x00001000, 0x001f /* expect 0x0084 */ + divide 0x00001000, 0x0020 /* expect 0x0080 */ + divide 0x00001000, 0x003f /* expect 0x0041 */ + divide 0x00001000, 0x0040 /* expect 0x0040 */ + divide 0x00001000, 0x007f /* expect 0x0020 */ + divide 0x00001000, 0x0080 /* expect 0x0020 */ + divide 0x00001000, 0x00ff /* expect 0x0010 */ + divide 0x00001000, 0x0100 /* expect 0x0010 */ + divide 0x00001000, 0x01ff /* expect 0x0008 */ + divide 0x00001000, 0x0200 /* expect 0x0008 */ + divide 0x00001000, 0x03ff /* expect 0x0004 */ + divide 0x00001000, 0x0400 /* expect 0x0004 */ + divide 0x00001000, 0x07ff /* expect 0x0002 */ + divide 0x00001000, 0x0800 /* expect 0x0002 */ + divide 0x00001000, 0x0fff /* expect 0x0001 */ + divide 0x00001000, 0x1000 /* expect 0x0001 */ + divide 0x00001000, 0x1fff /* expect 0x0000 */ + divide 0x00001000, 0x2000 /* expect 0x0000 */ + divide 0x00001000, 0x3fff /* expect 0x0000 */ + divide 0x00001000, 0x4000 /* expect 0x0000 */ + divide 0x00001000, 0x7fff /* expect 0x0000 */ + divide 0x00001fff, 0x0001 /* expect 0x1fff */ + divide 0x00001fff, 0x0002 /* expect 0x0fff */ + divide 0x00001fff, 0x0003 /* expect 0x0aaa */ + divide 0x00001fff, 0x0004 /* expect 0x07ff */ + divide 0x00001fff, 0x0007 /* expect 0x0492 */ + divide 0x00001fff, 0x0008 /* expect 0x03ff */ + divide 0x00001fff, 0x000f /* expect 0x0222 */ + divide 0x00001fff, 0x0010 /* expect 0x01ff */ + divide 0x00001fff, 0x001f /* expect 0x0108 */ + divide 0x00001fff, 0x0020 /* expect 0x00ff */ + divide 0x00001fff, 0x003f /* expect 0x0082 */ + divide 0x00001fff, 0x0040 /* expect 0x007f */ + divide 0x00001fff, 0x007f /* expect 0x0040 */ + divide 0x00001fff, 0x0080 /* expect 0x003f */ + divide 0x00001fff, 0x00ff /* expect 0x0020 */ + divide 0x00001fff, 0x0100 /* expect 0x001f */ + divide 0x00001fff, 0x01ff /* expect 0x0010 */ + divide 0x00001fff, 0x0200 /* expect 0x000f */ + divide 0x00001fff, 0x03ff /* expect 0x0008 */ + divide 0x00001fff, 0x0400 /* expect 0x0007 */ + divide 0x00001fff, 0x07ff /* expect 0x0004 */ + divide 0x00001fff, 0x0800 /* expect 0x0003 */ + divide 0x00001fff, 0x0fff /* expect 0x0002 */ + divide 0x00001fff, 0x1000 /* expect 0x0001 */ + divide 0x00001fff, 0x1fff /* expect 0x0001 */ + divide 0x00001fff, 0x2000 /* expect 0x0000 */ + divide 0x00001fff, 0x3fff /* expect 0x0000 */ + divide 0x00001fff, 0x4000 /* expect 0x0000 */ + divide 0x00001fff, 0x7fff /* expect 0x0000 */ + divide 0x00002000, 0x0001 /* expect 0x2000 */ + divide 0x00002000, 0x0002 /* expect 0x1000 */ + divide 0x00002000, 0x0003 /* expect 0x0aaa */ + divide 0x00002000, 0x0004 /* expect 0x0800 */ + divide 0x00002000, 0x0007 /* expect 0x0492 */ + divide 0x00002000, 0x0008 /* expect 0x0400 */ + divide 0x00002000, 0x000f /* expect 0x0222 */ + divide 0x00002000, 0x0010 /* expect 0x0200 */ + divide 0x00002000, 0x001f /* expect 0x0108 */ + divide 0x00002000, 0x0020 /* expect 0x0100 */ + divide 0x00002000, 0x003f /* expect 0x0082 */ + divide 0x00002000, 0x0040 /* expect 0x0080 */ + divide 0x00002000, 0x007f /* expect 0x0040 */ + divide 0x00002000, 0x0080 /* expect 0x0040 */ + divide 0x00002000, 0x00ff /* expect 0x0020 */ + divide 0x00002000, 0x0100 /* expect 0x0020 */ + divide 0x00002000, 0x01ff /* expect 0x0010 */ + divide 0x00002000, 0x0200 /* expect 0x0010 */ + divide 0x00002000, 0x03ff /* expect 0x0008 */ + divide 0x00002000, 0x0400 /* expect 0x0008 */ + divide 0x00002000, 0x07ff /* expect 0x0004 */ + divide 0x00002000, 0x0800 /* expect 0x0004 */ + divide 0x00002000, 0x0fff /* expect 0x0002 */ + divide 0x00002000, 0x1000 /* expect 0x0002 */ + divide 0x00002000, 0x1fff /* expect 0x0001 */ + divide 0x00002000, 0x2000 /* expect 0x0001 */ + divide 0x00002000, 0x3fff /* expect 0x0000 */ + divide 0x00002000, 0x4000 /* expect 0x0000 */ + divide 0x00002000, 0x7fff /* expect 0x0000 */ + divide 0x00003fff, 0x0001 /* expect 0x3fff */ + divide 0x00003fff, 0x0002 /* expect 0x1fff */ + divide 0x00003fff, 0x0003 /* expect 0x1555 */ + divide 0x00003fff, 0x0004 /* expect 0x0fff */ + divide 0x00003fff, 0x0007 /* expect 0x0924 */ + divide 0x00003fff, 0x0008 /* expect 0x07ff */ + divide 0x00003fff, 0x000f /* expect 0x0444 */ + divide 0x00003fff, 0x0010 /* expect 0x03ff */ + divide 0x00003fff, 0x001f /* expect 0x0210 */ + divide 0x00003fff, 0x0020 /* expect 0x01ff */ + divide 0x00003fff, 0x003f /* expect 0x0104 */ + divide 0x00003fff, 0x0040 /* expect 0x00ff */ + divide 0x00003fff, 0x007f /* expect 0x0081 */ + divide 0x00003fff, 0x0080 /* expect 0x007f */ + divide 0x00003fff, 0x00ff /* expect 0x0040 */ + divide 0x00003fff, 0x0100 /* expect 0x003f */ + divide 0x00003fff, 0x01ff /* expect 0x0020 */ + divide 0x00003fff, 0x0200 /* expect 0x001f */ + divide 0x00003fff, 0x03ff /* expect 0x0010 */ + divide 0x00003fff, 0x0400 /* expect 0x000f */ + divide 0x00003fff, 0x07ff /* expect 0x0008 */ + divide 0x00003fff, 0x0800 /* expect 0x0007 */ + divide 0x00003fff, 0x0fff /* expect 0x0004 */ + divide 0x00003fff, 0x1000 /* expect 0x0003 */ + divide 0x00003fff, 0x1fff /* expect 0x0002 */ + divide 0x00003fff, 0x2000 /* expect 0x0001 */ + divide 0x00003fff, 0x3fff /* expect 0x0001 */ + divide 0x00003fff, 0x4000 /* expect 0x0000 */ + divide 0x00003fff, 0x7fff /* expect 0x0000 */ + divide 0x00004000, 0x0001 /* expect 0x4000 */ + divide 0x00004000, 0x0002 /* expect 0x2000 */ + divide 0x00004000, 0x0003 /* expect 0x1555 */ + divide 0x00004000, 0x0004 /* expect 0x1000 */ + divide 0x00004000, 0x0007 /* expect 0x0924 */ + divide 0x00004000, 0x0008 /* expect 0x0800 */ + divide 0x00004000, 0x000f /* expect 0x0444 */ + divide 0x00004000, 0x0010 /* expect 0x0400 */ + divide 0x00004000, 0x001f /* expect 0x0210 */ + divide 0x00004000, 0x0020 /* expect 0x0200 */ + divide 0x00004000, 0x003f /* expect 0x0104 */ + divide 0x00004000, 0x0040 /* expect 0x0100 */ + divide 0x00004000, 0x007f /* expect 0x0081 */ + divide 0x00004000, 0x0080 /* expect 0x0080 */ + divide 0x00004000, 0x00ff /* expect 0x0040 */ + divide 0x00004000, 0x0100 /* expect 0x0040 */ + divide 0x00004000, 0x01ff /* expect 0x0020 */ + divide 0x00004000, 0x0200 /* expect 0x0020 */ + divide 0x00004000, 0x03ff /* expect 0x0010 */ + divide 0x00004000, 0x0400 /* expect 0x0010 */ + divide 0x00004000, 0x07ff /* expect 0x0008 */ + divide 0x00004000, 0x0800 /* expect 0x0008 */ + divide 0x00004000, 0x0fff /* expect 0x0004 */ + divide 0x00004000, 0x1000 /* expect 0x0004 */ + divide 0x00004000, 0x1fff /* expect 0x0002 */ + divide 0x00004000, 0x2000 /* expect 0x0002 */ + divide 0x00004000, 0x3fff /* expect 0x0001 */ + divide 0x00004000, 0x4000 /* expect 0x0001 */ + divide 0x00004000, 0x7fff /* expect 0x0000 */ + divide 0x00007fff, 0x0001 /* expect 0x7fff */ + divide 0x00007fff, 0x0002 /* expect 0x3fff */ + divide 0x00007fff, 0x0003 /* expect 0x2aaa */ + divide 0x00007fff, 0x0004 /* expect 0x1fff */ + divide 0x00007fff, 0x0007 /* expect 0x1249 */ + divide 0x00007fff, 0x0008 /* expect 0x0fff */ + divide 0x00007fff, 0x000f /* expect 0x0888 */ + divide 0x00007fff, 0x0010 /* expect 0x07ff */ + divide 0x00007fff, 0x001f /* expect 0x0421 */ + divide 0x00007fff, 0x0020 /* expect 0x03ff */ + divide 0x00007fff, 0x003f /* expect 0x0208 */ + divide 0x00007fff, 0x0040 /* expect 0x01ff */ + divide 0x00007fff, 0x007f /* expect 0x0102 */ + divide 0x00007fff, 0x0080 /* expect 0x00ff */ + divide 0x00007fff, 0x00ff /* expect 0x0080 */ + divide 0x00007fff, 0x0100 /* expect 0x007f */ + divide 0x00007fff, 0x01ff /* expect 0x0040 */ + divide 0x00007fff, 0x0200 /* expect 0x003f */ + divide 0x00007fff, 0x03ff /* expect 0x0020 */ + divide 0x00007fff, 0x0400 /* expect 0x001f */ + divide 0x00007fff, 0x07ff /* expect 0x0010 */ + divide 0x00007fff, 0x0800 /* expect 0x000f */ + divide 0x00007fff, 0x0fff /* expect 0x0008 */ + divide 0x00007fff, 0x1000 /* expect 0x0007 */ + divide 0x00007fff, 0x1fff /* expect 0x0004 */ + divide 0x00007fff, 0x2000 /* expect 0x0003 */ + divide 0x00007fff, 0x3fff /* expect 0x0002 */ + divide 0x00007fff, 0x4000 /* expect 0x0001 */ + divide 0x00007fff, 0x7fff /* expect 0x0001 */ + divide 0x00008000, 0x0002 /* expect 0x4000 */ + divide 0x00008000, 0x0003 /* expect 0x2aaa */ + divide 0x00008000, 0x0004 /* expect 0x2000 */ + divide 0x00008000, 0x0007 /* expect 0x1249 */ + divide 0x00008000, 0x0008 /* expect 0x1000 */ + divide 0x00008000, 0x000f /* expect 0x0888 */ + divide 0x00008000, 0x0010 /* expect 0x0800 */ + divide 0x00008000, 0x001f /* expect 0x0421 */ + divide 0x00008000, 0x0020 /* expect 0x0400 */ + divide 0x00008000, 0x003f /* expect 0x0208 */ + divide 0x00008000, 0x0040 /* expect 0x0200 */ + divide 0x00008000, 0x007f /* expect 0x0102 */ + divide 0x00008000, 0x0080 /* expect 0x0100 */ + divide 0x00008000, 0x00ff /* expect 0x0080 */ + divide 0x00008000, 0x0100 /* expect 0x0080 */ + divide 0x00008000, 0x01ff /* expect 0x0040 */ + divide 0x00008000, 0x0200 /* expect 0x0040 */ + divide 0x00008000, 0x03ff /* expect 0x0020 */ + divide 0x00008000, 0x0400 /* expect 0x0020 */ + divide 0x00008000, 0x07ff /* expect 0x0010 */ + divide 0x00008000, 0x0800 /* expect 0x0010 */ + divide 0x00008000, 0x0fff /* expect 0x0008 */ + divide 0x00008000, 0x1000 /* expect 0x0008 */ + divide 0x00008000, 0x1fff /* expect 0x0004 */ + divide 0x00008000, 0x2000 /* expect 0x0004 */ + divide 0x00008000, 0x3fff /* expect 0x0002 */ + divide 0x00008000, 0x4000 /* expect 0x0002 */ + divide 0x00008000, 0x7fff /* expect 0x0001 */ + divide 0x0000ffff, 0x0002 /* expect 0x7fff */ + divide 0x0000ffff, 0x0003 /* expect 0x5555 */ + divide 0x0000ffff, 0x0004 /* expect 0x3fff */ + divide 0x0000ffff, 0x0007 /* expect 0x2492 */ + divide 0x0000ffff, 0x0008 /* expect 0x1fff */ + divide 0x0000ffff, 0x000f /* expect 0x1111 */ + divide 0x0000ffff, 0x0010 /* expect 0x0fff */ + divide 0x0000ffff, 0x001f /* expect 0x0842 */ + divide 0x0000ffff, 0x0020 /* expect 0x07ff */ + divide 0x0000ffff, 0x003f /* expect 0x0410 */ + divide 0x0000ffff, 0x0040 /* expect 0x03ff */ + divide 0x0000ffff, 0x007f /* expect 0x0204 */ + divide 0x0000ffff, 0x0080 /* expect 0x01ff */ + divide 0x0000ffff, 0x00ff /* expect 0x0101 */ + divide 0x0000ffff, 0x0100 /* expect 0x00ff */ + divide 0x0000ffff, 0x01ff /* expect 0x0080 */ + divide 0x0000ffff, 0x0200 /* expect 0x007f */ + divide 0x0000ffff, 0x03ff /* expect 0x0040 */ + divide 0x0000ffff, 0x0400 /* expect 0x003f */ + divide 0x0000ffff, 0x07ff /* expect 0x0020 */ + divide 0x0000ffff, 0x0800 /* expect 0x001f */ + divide 0x0000ffff, 0x0fff /* expect 0x0010 */ + divide 0x0000ffff, 0x1000 /* expect 0x000f */ + divide 0x0000ffff, 0x1fff /* expect 0x0008 */ + divide 0x0000ffff, 0x2000 /* expect 0x0007 */ + divide 0x0000ffff, 0x3fff /* expect 0x0004 */ + divide 0x0000ffff, 0x4000 /* expect 0x0003 */ + divide 0x0000ffff, 0x7fff /* expect 0x0002 */ + divide 0x00010000, 0x0003 /* expect 0x5555 */ + divide 0x00010000, 0x0004 /* expect 0x4000 */ + divide 0x00010000, 0x0007 /* expect 0x2492 */ + divide 0x00010000, 0x0008 /* expect 0x2000 */ + divide 0x00010000, 0x000f /* expect 0x1111 */ + divide 0x00010000, 0x0010 /* expect 0x1000 */ + divide 0x00010000, 0x001f /* expect 0x0842 */ + divide 0x00010000, 0x0020 /* expect 0x0800 */ + divide 0x00010000, 0x003f /* expect 0x0410 */ + divide 0x00010000, 0x0040 /* expect 0x0400 */ + divide 0x00010000, 0x007f /* expect 0x0204 */ + divide 0x00010000, 0x0080 /* expect 0x0200 */ + divide 0x00010000, 0x00ff /* expect 0x0101 */ + divide 0x00010000, 0x0100 /* expect 0x0100 */ + divide 0x00010000, 0x01ff /* expect 0x0080 */ + divide 0x00010000, 0x0200 /* expect 0x0080 */ + divide 0x00010000, 0x03ff /* expect 0x0040 */ + divide 0x00010000, 0x0400 /* expect 0x0040 */ + divide 0x00010000, 0x07ff /* expect 0x0020 */ + divide 0x00010000, 0x0800 /* expect 0x0020 */ + divide 0x00010000, 0x0fff /* expect 0x0010 */ + divide 0x00010000, 0x1000 /* expect 0x0010 */ + divide 0x00010000, 0x1fff /* expect 0x0008 */ + divide 0x00010000, 0x2000 /* expect 0x0008 */ + divide 0x00010000, 0x3fff /* expect 0x0004 */ + divide 0x00010000, 0x4000 /* expect 0x0004 */ + divide 0x00010000, 0x7fff /* expect 0x0002 */ + divide 0x0001ffff, 0x0004 /* expect 0x7fff */ + divide 0x0001ffff, 0x0007 /* expect 0x4924 */ + divide 0x0001ffff, 0x0008 /* expect 0x3fff */ + divide 0x0001ffff, 0x000f /* expect 0x2222 */ + divide 0x0001ffff, 0x0010 /* expect 0x1fff */ + divide 0x0001ffff, 0x001f /* expect 0x1084 */ + divide 0x0001ffff, 0x0020 /* expect 0x0fff */ + divide 0x0001ffff, 0x003f /* expect 0x0820 */ + divide 0x0001ffff, 0x0040 /* expect 0x07ff */ + divide 0x0001ffff, 0x007f /* expect 0x0408 */ + divide 0x0001ffff, 0x0080 /* expect 0x03ff */ + divide 0x0001ffff, 0x00ff /* expect 0x0202 */ + divide 0x0001ffff, 0x0100 /* expect 0x01ff */ + divide 0x0001ffff, 0x01ff /* expect 0x0100 */ + divide 0x0001ffff, 0x0200 /* expect 0x00ff */ + divide 0x0001ffff, 0x03ff /* expect 0x0080 */ + divide 0x0001ffff, 0x0400 /* expect 0x007f */ + divide 0x0001ffff, 0x07ff /* expect 0x0040 */ + divide 0x0001ffff, 0x0800 /* expect 0x003f */ + divide 0x0001ffff, 0x0fff /* expect 0x0020 */ + divide 0x0001ffff, 0x1000 /* expect 0x001f */ + divide 0x0001ffff, 0x1fff /* expect 0x0010 */ + divide 0x0001ffff, 0x2000 /* expect 0x000f */ + divide 0x0001ffff, 0x3fff /* expect 0x0008 */ + divide 0x0001ffff, 0x4000 /* expect 0x0007 */ + divide 0x0001ffff, 0x7fff /* expect 0x0004 */ + divide 0x00020000, 0x0007 /* expect 0x4924 */ + divide 0x00020000, 0x0008 /* expect 0x4000 */ + divide 0x00020000, 0x000f /* expect 0x2222 */ + divide 0x00020000, 0x0010 /* expect 0x2000 */ + divide 0x00020000, 0x001f /* expect 0x1084 */ + divide 0x00020000, 0x0020 /* expect 0x1000 */ + divide 0x00020000, 0x003f /* expect 0x0820 */ + divide 0x00020000, 0x0040 /* expect 0x0800 */ + divide 0x00020000, 0x007f /* expect 0x0408 */ + divide 0x00020000, 0x0080 /* expect 0x0400 */ + divide 0x00020000, 0x00ff /* expect 0x0202 */ + divide 0x00020000, 0x0100 /* expect 0x0200 */ + divide 0x00020000, 0x01ff /* expect 0x0100 */ + divide 0x00020000, 0x0200 /* expect 0x0100 */ + divide 0x00020000, 0x03ff /* expect 0x0080 */ + divide 0x00020000, 0x0400 /* expect 0x0080 */ + divide 0x00020000, 0x07ff /* expect 0x0040 */ + divide 0x00020000, 0x0800 /* expect 0x0040 */ + divide 0x00020000, 0x0fff /* expect 0x0020 */ + divide 0x00020000, 0x1000 /* expect 0x0020 */ + divide 0x00020000, 0x1fff /* expect 0x0010 */ + divide 0x00020000, 0x2000 /* expect 0x0010 */ + divide 0x00020000, 0x3fff /* expect 0x0008 */ + divide 0x00020000, 0x4000 /* expect 0x0008 */ + divide 0x00020000, 0x7fff /* expect 0x0004 */ + divide 0x0003ffff, 0x0008 /* expect 0x7fff */ + divide 0x0003ffff, 0x000f /* expect 0x4444 */ + divide 0x0003ffff, 0x0010 /* expect 0x3fff */ + divide 0x0003ffff, 0x001f /* expect 0x2108 */ + divide 0x0003ffff, 0x0020 /* expect 0x1fff */ + divide 0x0003ffff, 0x003f /* expect 0x1041 */ + divide 0x0003ffff, 0x0040 /* expect 0x0fff */ + divide 0x0003ffff, 0x007f /* expect 0x0810 */ + divide 0x0003ffff, 0x0080 /* expect 0x07ff */ + divide 0x0003ffff, 0x00ff /* expect 0x0404 */ + divide 0x0003ffff, 0x0100 /* expect 0x03ff */ + divide 0x0003ffff, 0x01ff /* expect 0x0201 */ + divide 0x0003ffff, 0x0200 /* expect 0x01ff */ + divide 0x0003ffff, 0x03ff /* expect 0x0100 */ + divide 0x0003ffff, 0x0400 /* expect 0x00ff */ + divide 0x0003ffff, 0x07ff /* expect 0x0080 */ + divide 0x0003ffff, 0x0800 /* expect 0x007f */ + divide 0x0003ffff, 0x0fff /* expect 0x0040 */ + divide 0x0003ffff, 0x1000 /* expect 0x003f */ + divide 0x0003ffff, 0x1fff /* expect 0x0020 */ + divide 0x0003ffff, 0x2000 /* expect 0x001f */ + divide 0x0003ffff, 0x3fff /* expect 0x0010 */ + divide 0x0003ffff, 0x4000 /* expect 0x000f */ + divide 0x0003ffff, 0x7fff /* expect 0x0008 */ + divide 0x00040000, 0x000f /* expect 0x4444 */ + divide 0x00040000, 0x0010 /* expect 0x4000 */ + divide 0x00040000, 0x001f /* expect 0x2108 */ + divide 0x00040000, 0x0020 /* expect 0x2000 */ + divide 0x00040000, 0x003f /* expect 0x1041 */ + divide 0x00040000, 0x0040 /* expect 0x1000 */ + divide 0x00040000, 0x007f /* expect 0x0810 */ + divide 0x00040000, 0x0080 /* expect 0x0800 */ + divide 0x00040000, 0x00ff /* expect 0x0404 */ + divide 0x00040000, 0x0100 /* expect 0x0400 */ + divide 0x00040000, 0x01ff /* expect 0x0201 */ + divide 0x00040000, 0x0200 /* expect 0x0200 */ + divide 0x00040000, 0x03ff /* expect 0x0100 */ + divide 0x00040000, 0x0400 /* expect 0x0100 */ + divide 0x00040000, 0x07ff /* expect 0x0080 */ + divide 0x00040000, 0x0800 /* expect 0x0080 */ + divide 0x00040000, 0x0fff /* expect 0x0040 */ + divide 0x00040000, 0x1000 /* expect 0x0040 */ + divide 0x00040000, 0x1fff /* expect 0x0020 */ + divide 0x00040000, 0x2000 /* expect 0x0020 */ + divide 0x00040000, 0x3fff /* expect 0x0010 */ + divide 0x00040000, 0x4000 /* expect 0x0010 */ + divide 0x00040000, 0x7fff /* expect 0x0008 */ + divide 0x0007ffff, 0x0010 /* expect 0x7fff */ + divide 0x0007ffff, 0x001f /* expect 0x4210 */ + divide 0x0007ffff, 0x0020 /* expect 0x3fff */ + divide 0x0007ffff, 0x003f /* expect 0x2082 */ + divide 0x0007ffff, 0x0040 /* expect 0x1fff */ + divide 0x0007ffff, 0x007f /* expect 0x1020 */ + divide 0x0007ffff, 0x0080 /* expect 0x0fff */ + divide 0x0007ffff, 0x00ff /* expect 0x0808 */ + divide 0x0007ffff, 0x0100 /* expect 0x07ff */ + divide 0x0007ffff, 0x01ff /* expect 0x0402 */ + divide 0x0007ffff, 0x0200 /* expect 0x03ff */ + divide 0x0007ffff, 0x03ff /* expect 0x0200 */ + divide 0x0007ffff, 0x0400 /* expect 0x01ff */ + divide 0x0007ffff, 0x07ff /* expect 0x0100 */ + divide 0x0007ffff, 0x0800 /* expect 0x00ff */ + divide 0x0007ffff, 0x0fff /* expect 0x0080 */ + divide 0x0007ffff, 0x1000 /* expect 0x007f */ + divide 0x0007ffff, 0x1fff /* expect 0x0040 */ + divide 0x0007ffff, 0x2000 /* expect 0x003f */ + divide 0x0007ffff, 0x3fff /* expect 0x0020 */ + divide 0x0007ffff, 0x4000 /* expect 0x001f */ + divide 0x0007ffff, 0x7fff /* expect 0x0010 */ + divide 0x00080000, 0x001f /* expect 0x4210 */ + divide 0x00080000, 0x0020 /* expect 0x4000 */ + divide 0x00080000, 0x003f /* expect 0x2082 */ + divide 0x00080000, 0x0040 /* expect 0x2000 */ + divide 0x00080000, 0x007f /* expect 0x1020 */ + divide 0x00080000, 0x0080 /* expect 0x1000 */ + divide 0x00080000, 0x00ff /* expect 0x0808 */ + divide 0x00080000, 0x0100 /* expect 0x0800 */ + divide 0x00080000, 0x01ff /* expect 0x0402 */ + divide 0x00080000, 0x0200 /* expect 0x0400 */ + divide 0x00080000, 0x03ff /* expect 0x0200 */ + divide 0x00080000, 0x0400 /* expect 0x0200 */ + divide 0x00080000, 0x07ff /* expect 0x0100 */ + divide 0x00080000, 0x0800 /* expect 0x0100 */ + divide 0x00080000, 0x0fff /* expect 0x0080 */ + divide 0x00080000, 0x1000 /* expect 0x0080 */ + divide 0x00080000, 0x1fff /* expect 0x0040 */ + divide 0x00080000, 0x2000 /* expect 0x0040 */ + divide 0x00080000, 0x3fff /* expect 0x0020 */ + divide 0x00080000, 0x4000 /* expect 0x0020 */ + divide 0x00080000, 0x7fff /* expect 0x0010 */ + divide 0x000fffff, 0x0020 /* expect 0x7fff */ + divide 0x000fffff, 0x003f /* expect 0x4104 */ + divide 0x000fffff, 0x0040 /* expect 0x3fff */ + divide 0x000fffff, 0x007f /* expect 0x2040 */ + divide 0x000fffff, 0x0080 /* expect 0x1fff */ + divide 0x000fffff, 0x00ff /* expect 0x1010 */ + divide 0x000fffff, 0x0100 /* expect 0x0fff */ + divide 0x000fffff, 0x01ff /* expect 0x0804 */ + divide 0x000fffff, 0x0200 /* expect 0x07ff */ + divide 0x000fffff, 0x03ff /* expect 0x0401 */ + divide 0x000fffff, 0x0400 /* expect 0x03ff */ + divide 0x000fffff, 0x07ff /* expect 0x0200 */ + divide 0x000fffff, 0x0800 /* expect 0x01ff */ + divide 0x000fffff, 0x0fff /* expect 0x0100 */ + divide 0x000fffff, 0x1000 /* expect 0x00ff */ + divide 0x000fffff, 0x1fff /* expect 0x0080 */ + divide 0x000fffff, 0x2000 /* expect 0x007f */ + divide 0x000fffff, 0x3fff /* expect 0x0040 */ + divide 0x000fffff, 0x4000 /* expect 0x003f */ + divide 0x000fffff, 0x7fff /* expect 0x0020 */ + divide 0x00100000, 0x003f /* expect 0x4104 */ + divide 0x00100000, 0x0040 /* expect 0x4000 */ + divide 0x00100000, 0x007f /* expect 0x2040 */ + divide 0x00100000, 0x0080 /* expect 0x2000 */ + divide 0x00100000, 0x00ff /* expect 0x1010 */ + divide 0x00100000, 0x0100 /* expect 0x1000 */ + divide 0x00100000, 0x01ff /* expect 0x0804 */ + divide 0x00100000, 0x0200 /* expect 0x0800 */ + divide 0x00100000, 0x03ff /* expect 0x0401 */ + divide 0x00100000, 0x0400 /* expect 0x0400 */ + divide 0x00100000, 0x07ff /* expect 0x0200 */ + divide 0x00100000, 0x0800 /* expect 0x0200 */ + divide 0x00100000, 0x0fff /* expect 0x0100 */ + divide 0x00100000, 0x1000 /* expect 0x0100 */ + divide 0x00100000, 0x1fff /* expect 0x0080 */ + divide 0x00100000, 0x2000 /* expect 0x0080 */ + divide 0x00100000, 0x3fff /* expect 0x0040 */ + divide 0x00100000, 0x4000 /* expect 0x0040 */ + divide 0x00100000, 0x7fff /* expect 0x0020 */ + divide 0x001fffff, 0x0040 /* expect 0x7fff */ + divide 0x001fffff, 0x007f /* expect 0x4081 */ + divide 0x001fffff, 0x0080 /* expect 0x3fff */ + divide 0x001fffff, 0x00ff /* expect 0x2020 */ + divide 0x001fffff, 0x0100 /* expect 0x1fff */ + divide 0x001fffff, 0x01ff /* expect 0x1008 */ + divide 0x001fffff, 0x0200 /* expect 0x0fff */ + divide 0x001fffff, 0x03ff /* expect 0x0802 */ + divide 0x001fffff, 0x0400 /* expect 0x07ff */ + divide 0x001fffff, 0x07ff /* expect 0x0400 */ + divide 0x001fffff, 0x0800 /* expect 0x03ff */ + divide 0x001fffff, 0x0fff /* expect 0x0200 */ + divide 0x001fffff, 0x1000 /* expect 0x01ff */ + divide 0x001fffff, 0x1fff /* expect 0x0100 */ + divide 0x001fffff, 0x2000 /* expect 0x00ff */ + divide 0x001fffff, 0x3fff /* expect 0x0080 */ + divide 0x001fffff, 0x4000 /* expect 0x007f */ + divide 0x001fffff, 0x7fff /* expect 0x0040 */ + divide 0x00200000, 0x007f /* expect 0x4081 */ + divide 0x00200000, 0x0080 /* expect 0x4000 */ + divide 0x00200000, 0x00ff /* expect 0x2020 */ + divide 0x00200000, 0x0100 /* expect 0x2000 */ + divide 0x00200000, 0x01ff /* expect 0x1008 */ + divide 0x00200000, 0x0200 /* expect 0x1000 */ + divide 0x00200000, 0x03ff /* expect 0x0802 */ + divide 0x00200000, 0x0400 /* expect 0x0800 */ + divide 0x00200000, 0x07ff /* expect 0x0400 */ + divide 0x00200000, 0x0800 /* expect 0x0400 */ + divide 0x00200000, 0x0fff /* expect 0x0200 */ + divide 0x00200000, 0x1000 /* expect 0x0200 */ + divide 0x00200000, 0x1fff /* expect 0x0100 */ + divide 0x00200000, 0x2000 /* expect 0x0100 */ + divide 0x00200000, 0x3fff /* expect 0x0080 */ + divide 0x00200000, 0x4000 /* expect 0x0080 */ + divide 0x00200000, 0x7fff /* expect 0x0040 */ + divide 0x003fffff, 0x0080 /* expect 0x7fff */ + divide 0x003fffff, 0x00ff /* expect 0x4040 */ + divide 0x003fffff, 0x0100 /* expect 0x3fff */ + divide 0x003fffff, 0x01ff /* expect 0x2010 */ + divide 0x003fffff, 0x0200 /* expect 0x1fff */ + divide 0x003fffff, 0x03ff /* expect 0x1004 */ + divide 0x003fffff, 0x0400 /* expect 0x0fff */ + divide 0x003fffff, 0x07ff /* expect 0x0801 */ + divide 0x003fffff, 0x0800 /* expect 0x07ff */ + divide 0x003fffff, 0x0fff /* expect 0x0400 */ + divide 0x003fffff, 0x1000 /* expect 0x03ff */ + divide 0x003fffff, 0x1fff /* expect 0x0200 */ + divide 0x003fffff, 0x2000 /* expect 0x01ff */ + divide 0x003fffff, 0x3fff /* expect 0x0100 */ + divide 0x003fffff, 0x4000 /* expect 0x00ff */ + divide 0x003fffff, 0x7fff /* expect 0x0080 */ + divide 0x00400000, 0x00ff /* expect 0x4040 */ + divide 0x00400000, 0x0100 /* expect 0x4000 */ + divide 0x00400000, 0x01ff /* expect 0x2010 */ + divide 0x00400000, 0x0200 /* expect 0x2000 */ + divide 0x00400000, 0x03ff /* expect 0x1004 */ + divide 0x00400000, 0x0400 /* expect 0x1000 */ + divide 0x00400000, 0x07ff /* expect 0x0801 */ + divide 0x00400000, 0x0800 /* expect 0x0800 */ + divide 0x00400000, 0x0fff /* expect 0x0400 */ + divide 0x00400000, 0x1000 /* expect 0x0400 */ + divide 0x00400000, 0x1fff /* expect 0x0200 */ + divide 0x00400000, 0x2000 /* expect 0x0200 */ + divide 0x00400000, 0x3fff /* expect 0x0100 */ + divide 0x00400000, 0x4000 /* expect 0x0100 */ + divide 0x00400000, 0x7fff /* expect 0x0080 */ + divide 0x007fffff, 0x0100 /* expect 0x7fff */ + divide 0x007fffff, 0x01ff /* expect 0x4020 */ + divide 0x007fffff, 0x0200 /* expect 0x3fff */ + divide 0x007fffff, 0x03ff /* expect 0x2008 */ + divide 0x007fffff, 0x0400 /* expect 0x1fff */ + divide 0x007fffff, 0x07ff /* expect 0x1002 */ + divide 0x007fffff, 0x0800 /* expect 0x0fff */ + divide 0x007fffff, 0x0fff /* expect 0x0800 */ + divide 0x007fffff, 0x1000 /* expect 0x07ff */ + divide 0x007fffff, 0x1fff /* expect 0x0400 */ + divide 0x007fffff, 0x2000 /* expect 0x03ff */ + divide 0x007fffff, 0x3fff /* expect 0x0200 */ + divide 0x007fffff, 0x4000 /* expect 0x01ff */ + divide 0x007fffff, 0x7fff /* expect 0x0100 */ + divide 0x00800000, 0x01ff /* expect 0x4020 */ + divide 0x00800000, 0x0200 /* expect 0x4000 */ + divide 0x00800000, 0x03ff /* expect 0x2008 */ + divide 0x00800000, 0x0400 /* expect 0x2000 */ + divide 0x00800000, 0x07ff /* expect 0x1002 */ + divide 0x00800000, 0x0800 /* expect 0x1000 */ + divide 0x00800000, 0x0fff /* expect 0x0800 */ + divide 0x00800000, 0x1000 /* expect 0x0800 */ + divide 0x00800000, 0x1fff /* expect 0x0400 */ + divide 0x00800000, 0x2000 /* expect 0x0400 */ + divide 0x00800000, 0x3fff /* expect 0x0200 */ + divide 0x00800000, 0x4000 /* expect 0x0200 */ + divide 0x00800000, 0x7fff /* expect 0x0100 */ + divide 0x00ffffff, 0x0200 /* expect 0x7fff */ + divide 0x00ffffff, 0x03ff /* expect 0x4010 */ + divide 0x00ffffff, 0x0400 /* expect 0x3fff */ + divide 0x00ffffff, 0x07ff /* expect 0x2004 */ + divide 0x00ffffff, 0x0800 /* expect 0x1fff */ + divide 0x00ffffff, 0x0fff /* expect 0x1001 */ + divide 0x00ffffff, 0x1000 /* expect 0x0fff */ + divide 0x00ffffff, 0x1fff /* expect 0x0800 */ + divide 0x00ffffff, 0x2000 /* expect 0x07ff */ + divide 0x00ffffff, 0x3fff /* expect 0x0400 */ + divide 0x00ffffff, 0x4000 /* expect 0x03ff */ + divide 0x00ffffff, 0x7fff /* expect 0x0200 */ + divide 0x01000000, 0x03ff /* expect 0x4010 */ + divide 0x01000000, 0x0400 /* expect 0x4000 */ + divide 0x01000000, 0x07ff /* expect 0x2004 */ + divide 0x01000000, 0x0800 /* expect 0x2000 */ + divide 0x01000000, 0x0fff /* expect 0x1001 */ + divide 0x01000000, 0x1000 /* expect 0x1000 */ + divide 0x01000000, 0x1fff /* expect 0x0800 */ + divide 0x01000000, 0x2000 /* expect 0x0800 */ + divide 0x01000000, 0x3fff /* expect 0x0400 */ + divide 0x01000000, 0x4000 /* expect 0x0400 */ + divide 0x01000000, 0x7fff /* expect 0x0200 */ + divide 0x01ffffff, 0x0400 /* expect 0x7fff */ + divide 0x01ffffff, 0x07ff /* expect 0x4008 */ + divide 0x01ffffff, 0x0800 /* expect 0x3fff */ + divide 0x01ffffff, 0x0fff /* expect 0x2002 */ + divide 0x01ffffff, 0x1000 /* expect 0x1fff */ + divide 0x01ffffff, 0x1fff /* expect 0x1000 */ + divide 0x01ffffff, 0x2000 /* expect 0x0fff */ + divide 0x01ffffff, 0x3fff /* expect 0x0800 */ + divide 0x01ffffff, 0x4000 /* expect 0x07ff */ + divide 0x01ffffff, 0x7fff /* expect 0x0400 */ + divide 0x02000000, 0x07ff /* expect 0x4008 */ + divide 0x02000000, 0x0800 /* expect 0x4000 */ + divide 0x02000000, 0x0fff /* expect 0x2002 */ + divide 0x02000000, 0x1000 /* expect 0x2000 */ + divide 0x02000000, 0x1fff /* expect 0x1000 */ + divide 0x02000000, 0x2000 /* expect 0x1000 */ + divide 0x02000000, 0x3fff /* expect 0x0800 */ + divide 0x02000000, 0x4000 /* expect 0x0800 */ + divide 0x02000000, 0x7fff /* expect 0x0400 */ + divide 0x03ffffff, 0x0800 /* expect 0x7fff */ + divide 0x03ffffff, 0x0fff /* expect 0x4004 */ + divide 0x03ffffff, 0x1000 /* expect 0x3fff */ + divide 0x03ffffff, 0x1fff /* expect 0x2001 */ + divide 0x03ffffff, 0x2000 /* expect 0x1fff */ + divide 0x03ffffff, 0x3fff /* expect 0x1000 */ + divide 0x03ffffff, 0x4000 /* expect 0x0fff */ + divide 0x03ffffff, 0x7fff /* expect 0x0800 */ + divide 0x04000000, 0x0fff /* expect 0x4004 */ + divide 0x04000000, 0x1000 /* expect 0x4000 */ + divide 0x04000000, 0x1fff /* expect 0x2001 */ + divide 0x04000000, 0x2000 /* expect 0x2000 */ + divide 0x04000000, 0x3fff /* expect 0x1000 */ + divide 0x04000000, 0x4000 /* expect 0x1000 */ + divide 0x04000000, 0x7fff /* expect 0x0800 */ + divide 0x07ffffff, 0x1000 /* expect 0x7fff */ + divide 0x07ffffff, 0x1fff /* expect 0x4002 */ + divide 0x07ffffff, 0x2000 /* expect 0x3fff */ + divide 0x07ffffff, 0x3fff /* expect 0x2000 */ + divide 0x07ffffff, 0x4000 /* expect 0x1fff */ + divide 0x07ffffff, 0x7fff /* expect 0x1000 */ + divide 0x08000000, 0x1fff /* expect 0x4002 */ + divide 0x08000000, 0x2000 /* expect 0x4000 */ + divide 0x08000000, 0x3fff /* expect 0x2000 */ + divide 0x08000000, 0x4000 /* expect 0x2000 */ + divide 0x08000000, 0x7fff /* expect 0x1000 */ + divide 0x0fffffff, 0x2000 /* expect 0x7fff */ + divide 0x0fffffff, 0x3fff /* expect 0x4001 */ + divide 0x0fffffff, 0x4000 /* expect 0x3fff */ + divide 0x0fffffff, 0x7fff /* expect 0x2000 */ + divide 0x10000000, 0x3fff /* expect 0x4001 */ + divide 0x10000000, 0x4000 /* expect 0x4000 */ + divide 0x10000000, 0x7fff /* expect 0x2000 */ + divide 0x1fffffff, 0x4000 /* expect 0x7fff */ + divide 0x1fffffff, 0x7fff /* expect 0x4000 */ + divide 0x20000000, 0x7fff /* expect 0x4000 */ + + pass diff --git a/sim/testsuite/bfin/dotproduct.s b/sim/testsuite/bfin/dotproduct.s new file mode 100644 index 0000000..bfae545 --- /dev/null +++ b/sim/testsuite/bfin/dotproduct.s @@ -0,0 +1,304 @@ +# Blackfin testcase for a simple vector dot product using hard +# wired input buffers of 128 samples each. These values are in +# 1.15 signed . + +# mach: bfin + + .include "testutils.inc" + + start + + loadsym P0, _buf0 + loadsym P1, _buf1 + + /* loop control + * number of loop iterations is 2^N with r4|=1< 32 + + A1 = R0.H * R1.L (M), A0 = R0.L * R1.L (FU); + A1 += R1.H * R0.L (M,IS); + A0 = A0 >>> 16; + A0 += A1; + A0 = A0 >>> 16; + A0 += R0.H * R1.H (IS); + R7 = A0.w; + +loop1end: + [ P2 ++ ] = R7; // store 32 bit output + + // test results + loadsym P1, output; + R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xab6b ); + R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xa627 ); + R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xa0e3 ); + R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0x9b9f ); + pass + + .data +input_a: + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .align 4; +input_b: + .dw 0x1000 + .dw 0x4010 + .dw 0x1000 + .dw 0x4011 + .dw 0x1000 + .dw 0x4012 + .dw 0x1000 + .dw 0x4013 + .dw 0x1000 + .dw 0x4014 + .dw 0x1000 + .dw 0x4015 + .dw 0x1000 + .dw 0x4016 + .dw 0x1000 + .dw 0x4017 + .dw 0x1000 + .dw 0x4018 + .dw 0x1000 + .dw 0x4019 + .align 4; +output: + .space (40); diff --git a/sim/testsuite/bfin/dsp_a4.s b/sim/testsuite/bfin/dsp_a4.s new file mode 100644 index 0000000..fdafcdf --- /dev/null +++ b/sim/testsuite/bfin/dsp_a4.s @@ -0,0 +1,113 @@ +/* ALU test program. + * Test instructions + * r3= + (r0,r0); + * r3= + (r0,r0) s; + * r3= - (r0,r0); + * r3= - (r0,r0) s; + */ +# mach: bfin + +.include "testutils.inc" + start + + +// overflow positive + R0.L = 0xffff; + R0.H = 0x7fff; + R7 = 0; + ASTAT = R7; + R3 = R0 + R0 (NS); + DBGA ( R3.L , 0xfffe ); + DBGA ( R3.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// overflow negative + R0.L = 0x0000; + R0.H = 0x8000; + R7 = 0; + ASTAT = R7; + R3 = R0 + R0 (NS); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// zero + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R3 = R1 + R0 (NS); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate positive + R0.L = 0; + R0.H = 0x7fff; + R7 = 0; + ASTAT = R7; + R3 = R0 + R0 (S); + DBGA ( R3.L , 0xffff ); + DBGA ( R3.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// saturate negative + R0.L = 0; + R0.H = 0x8000; + R7 = 0; + ASTAT = R7; + R3 = R0 + R0 (S); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x8000 ); + + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate positive with subtraction + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0xffff; + R1.H = 0x7fff; + R7 = 0; + ASTAT = R7; + R3 = R1 - R0 (S); + DBGA ( R3.L , 0xffff ); + DBGA ( R3.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// saturate negative with subtraction + R0.L = 0x1; + R0.H = 0x0; + R1.L = 0x0000; + R1.H = 0x8000; + R7 = 0; + ASTAT = R7; + R3 = R1 - R0 (S); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + + pass diff --git a/sim/testsuite/bfin/dsp_a7.s b/sim/testsuite/bfin/dsp_a7.s new file mode 100644 index 0000000..075fbc7 --- /dev/null +++ b/sim/testsuite/bfin/dsp_a7.s @@ -0,0 +1,103 @@ +/* ALU test program. + * Test instructions + * r7 = +/- (r0,r1); + * r7 = -/+ (r0,r1); + * r7 = -/- (r0,r1); + */ + +# mach: bfin + +.include "testutils.inc" + start + +// test subtraction + R0.L = 0x000f; + R0.H = 0x0010; + R1.L = 0x000f; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|- R1; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test overflow negative on subtraction + R0.L = 0x8000; + R0.H = 0x0010; + R1.L = 0x0001; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|- R1; + DBGA ( R7.L , 0x7fff ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test saturate negative on subtraction +/- + R0.L = 0x8000; + R0.H = 0x0010; + R1.L = 0x0001; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|- R1 (S); + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test saturate negative on subtraction -/+ + R0.L = 0x8000; + R0.H = 0x8000; + R1.L = 0x0001; + R1.H = 0x0001; + R7 = 0; + ASTAT = R7; + R7 = R0 -|+ R1 (S); + DBGA ( R7.L , 0x8001 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R5 = CC; DBGA ( R5.L , 0x0 ); + CC = AN; R5 = CC; DBGA ( R5.L , 0x1 ); + CC = V; R5 = CC; DBGA ( R5.L , 0x1 ); + CC = AC0; R5 = CC; DBGA ( R5.L , 0x0 ); + +// test saturate negative on subtraction -/- + R0.L = 0x8000; + R0.H = 0x8000; + R1.L = 0x0001; + R1.H = 0x0001; + R7 = 0; + ASTAT = R7; + R7 = R0 -|- R1 (S); + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test saturate positive on subtraction -/+ + R0.L = 0x7fff; + R0.H = 0x7fff; + R1.L = 0xffff; + R1.H = 0xffff; + R7 = 0; + ASTAT = R7; + R7 = R0 -|+ R1 (S); + DBGA ( R7.L , 0x7ffe ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + + pass diff --git a/sim/testsuite/bfin/dsp_a8.s b/sim/testsuite/bfin/dsp_a8.s new file mode 100644 index 0000000..0383e20 --- /dev/null +++ b/sim/testsuite/bfin/dsp_a8.s @@ -0,0 +1,80 @@ +/* ALU test program. + * Test instructions + * (r7,r6) = +/- (r0,r1); + * (r7,r6) = +/- (r0,r1)s; + */ +# mach: bfin + +.include "testutils.inc" + start + + +// test positive overflow + R0.L = 0xffff; + R0.H = 0x7fff; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R6 = R0 + R1, R7 = R0 - R1 (NS); + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test positive overflow + R0.L = 0xffff; + R0.H = 0x7fff; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R7 = R0 + R1, R6 = R0 - R1 (NS); + DBGA ( R6.L , 0xfffe ); + DBGA ( R6.H , 0x7fff ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test positive sat + R0.L = 0xffff; + R0.H = 0x7fff; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R6 = R0 + R1, R7 = R0 - R1 (S); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x7fff ); + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test positive sat + R0.L = 0xffff; + R0.H = 0x7fff; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R7 = R0 + R1, R6 = R0 - R1 (S); + DBGA ( R6.L , 0xfffe ); + DBGA ( R6.H , 0x7fff ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + + pass diff --git a/sim/testsuite/bfin/dsp_d0.s b/sim/testsuite/bfin/dsp_d0.s new file mode 100644 index 0000000..ff7aaf0 --- /dev/null +++ b/sim/testsuite/bfin/dsp_d0.s @@ -0,0 +1,31 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym I0, vec; + + R0 = [ I0 ++ ]; + DBGA ( R0.L , 1 ); DBGA ( R0.H , 2 ); + R0 = [ I0 ++ ]; + DBGA ( R0.L , 2 ); DBGA ( R0.H , 3 ); + + loadsym I3, vec; + R0 = 4; + M1 = R0; + + _DBG I3; + R0 = [ I3 ++ M1 ]; + DBGA ( R0.L , 1 ); DBGA ( R0.H , 2 ); + _DBG I3; + R0 = [ I3 ++ M1 ]; + DBGA ( R0.L , 2 ); DBGA ( R0.H , 3 ); + + pass + + .data +vec: + .dw 1 + .dw 2 + .dw 2 + .dw 3 diff --git a/sim/testsuite/bfin/dsp_d1.s b/sim/testsuite/bfin/dsp_d1.s new file mode 100644 index 0000000..c045ba5 --- /dev/null +++ b/sim/testsuite/bfin/dsp_d1.s @@ -0,0 +1,117 @@ +/* DAG test program. + * Test circular buffers + */ +# mach: bfin + +.include "testutils.inc" + start + + loadsym I0, foo; + loadsym B0, foo; + loadsym R2, foo; + L0 = 0x10 (X); + M1 = 8 (X); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2 + DBGA ( R1.L , 0x0008 ); + R0 = [ I0 ++ M1 ]; + R7 = I0; + + R1 = R7 - R2; + DBGA ( R1.L , 0x0000 ); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2 + DBGA ( R1.L , 0x0008 ); + + loadsym I0, foo; + loadsym B0, foo; + loadsym R2, foo; + L0 = 0x10 (X); + M1 = -4 (X); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2 + DBGA ( R1.L , 0x000c ); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2 + DBGA ( R1.L , 0x0008 ); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0004 ); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0000 ); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x000c ); + + loadsym I0, foo; + loadsym B0, foo; + loadsym R2, foo; + L0 = 0x8 (X); + R0 = [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0004 ); + R0 = [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0000 ); + R0 = [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0004 ); + + loadsym I0, foo; + loadsym B0, foo; + loadsym R2, foo; + L0 = 0x8 (X); + R0.L = W [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0002 ); + R0.L = W [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0004 ); + R0.L = W [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0006 ); + R0.L = W [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0000 ); + R0.L = W [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0002 ); + + loadsym I0, foo; + loadsym B0, foo; + loadsym R2, foo; + L0 = 0x8 (X); + R0 = [ I0 -- ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0004 ); + R0 = [ I0 -- ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0000 ); + R0 = [ I0 -- ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0004 ); + + pass + + .data +foo: + .space (0x10); diff --git a/sim/testsuite/bfin/dsp_neg.S b/sim/testsuite/bfin/dsp_neg.S new file mode 100644 index 0000000..a6ec10a --- /dev/null +++ b/sim/testsuite/bfin/dsp_neg.S @@ -0,0 +1,36 @@ +// ALU test program. +// Test instructions: +// dreg = -dreg (ns); +// dreg = -dreg (s); +// dspalu32 negate instruction +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + +// CHECK MULTI ISSUE + r1=0x5; + loadsym i0, data0; + r2 = -r1 (ns) || r3=[i0++]; + checkreg r2, 0xfffffffb; + r3 = astat + checkreg r3, (_AN); + + r1.h = 0x8000; + r1.l = 0x0; + r2 = -r1 (s); + checkreg r2, 0x7fffffff; + + r3 = astat; + _dbg astat; + checkreg r3, (_VS|_V|_V_COPY); + + pass + + .data +data0: + .space (0x10); diff --git a/sim/testsuite/bfin/dsp_s1.s b/sim/testsuite/bfin/dsp_s1.s new file mode 100644 index 0000000..70d8a5d --- /dev/null +++ b/sim/testsuite/bfin/dsp_s1.s @@ -0,0 +1,85 @@ +/* SHIFT test program. + * Test r0, r1, A0 >>= BITMUX; + */ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = r0; + +// load r0=0x80000009 +// load r1=0x10000009 +// load r2=0x0000000f +// load r3=0x00000000 +// load r4=0x80000008 +// load r5=0x00000000 + loadsym P0, data0; + loadsym P1, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + +// insert two bits, both equal to 1 +// A0: 00 0000 000f -> c0 0000 0003 +// r0: 8000 0009 -> 4000 0004 +// r1: 1000 0009 -> 0800 0004 + R0 = [ P1 + 0 ]; + R1 = [ P1 + 4 ]; + A0.w = R2; + A0.x = R3.L; + BITMUX( R0 , R1, A0) (ASR); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0003 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xffc0 ); + DBGA ( R0.L , 0x0004 ); + DBGA ( R0.H , 0x4000 ); + DBGA ( R1.L , 0x0004 ); + DBGA ( R1.H , 0x0800 ); + +// insert two bits, one equal to 1, other to 0 +// A0: 00 0000 000f -> 40 0000 0003 +// r0: 8000 0009 -> 4000 0004 +// r4: 8000 0008 -> 4000 0004 + R0 = [ P1 + 0 ]; + R4 = [ P1 + 16 ]; + A0.w = R2; + A0.x = R3.L; + BITMUX( R0 , R4, A0) (ASR); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0003 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0040 ); + DBGA ( R0.L , 0x0004 ); + DBGA ( R0.H , 0x4000 ); + DBGA ( R4.L , 0x0004 ); + DBGA ( R4.H , 0x4000 ); + + pass + + .data +data0: + .dw 0x0009 + .dw 0x8000 + + .dw 0x0009 + .dw 0x1000 + + .dw 0x000f + .dw 0x0000 + + .dw 0x0000 + .dw 0x0000 + + .dw 0x0008 + .dw 0x8000 + + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/bfin/e0.s b/sim/testsuite/bfin/e0.s new file mode 100644 index 0000000..bdcd71b --- /dev/null +++ b/sim/testsuite/bfin/e0.s @@ -0,0 +1,51 @@ +// assert that we can issue a software exception +// and that the expt number is passed correctly through +// SEQSTAT. +# mach: bfin +# sim: --environment operating + + .include "testutils.inc" + + start +.ifndef BFIN_HOST + imm32 p0, 0xFFE02000; /* EVT0 */ + P1 = re (Z); // load a pointer to ihandler interrupt 1 + P1.H = re; + [ P0 + (4*3) ] = P1; + + R0 = -1; /* unmask all interrupts */ + imm32 p1, 0xFFE02104; + [P1] = R0; + + R0 = start_uspace (Z); + R0.H = start_uspace; + RETI = R0; + RTI; +start_uspace: + EXCPT 10; + + DBGA ( R1.L , 0x1238 ); + + dbg_pass; + + // ihandler +re: + R0 = SEQSTAT; + R0 <<= (32-6); + R0 >>= (32-6); + R2 = 0x20; + CC = R0 < R2; + IF !CC JUMP _error; + DBGA ( R0.L , 0xa ); + R1 = 0x1234 (X); + R1 += 1; + R1 += 1; + R1 += 1; + R1 += 1; + RTX; + +_error: + DBGA ( R0.L , EXCPT_PROTVIOL ); + dbg_fail; + +.endif diff --git a/sim/testsuite/bfin/edn_snafu.s b/sim/testsuite/bfin/edn_snafu.s new file mode 100644 index 0000000..b97d7e8 --- /dev/null +++ b/sim/testsuite/bfin/edn_snafu.s @@ -0,0 +1,45 @@ +# mach: bfin + +.include "testutils.inc" + start + + + + loadsym r7, foo; + + p0 = r7; + + r0.h=0x2a2a; + r0.l=0x2a2a; + + [p0++]=r0; + [p0++]=r0; + r0=0; + [p0++]=r0; + + p0 = r7; + p1=-1; + + lsetup(lstart, lend) lc0=p1; + +lstart: + _dbg p0; + r1=b[p0++] (z); + cc = r1 == 0; + if cc jump ldone; +lend: + nop; + +ldone: + + r1=b[p0++](z); + r1=p0; + r6 = r1 - r7; + + DBGA (R6.L, 0xA); + + pass; + + .data +foo: + .space (0x100) diff --git a/sim/testsuite/bfin/eu_dsp32mac_s.s b/sim/testsuite/bfin/eu_dsp32mac_s.s new file mode 100644 index 0000000..6935aa6 --- /dev/null +++ b/sim/testsuite/bfin/eu_dsp32mac_s.s @@ -0,0 +1,38 @@ +// Check MAC with scaling +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0; + R1 = 0; + R2 = 0; + A1 = A0 = 0; +// The result accumulated in A1, and stored to a reg half + R0.L = 23229; + R0.H = -23724; + R1.L = -313; + R1.H = -17732; + R2.H = ( A1 = R1.L * R0.L ), A0 += R1.L * R0.L (S2RND); + _DBG R2; + DBGA ( R2.H , 0xfe44 ); + + R0 = 0; + ASTAT = R0; // clear all flags + A0 = 0; + A1 = 0; + R0.H = 0x8000; + R0.L = 0x7fff; + R1.H = 0x7fff; + R1.L = 0x8000; + A1 = R0.H * R1.H (M), R0.L = ( A0 -= R0.H * R1.H ) (ISS2); + _DBG R0; + DBGA ( R0.L , 0x7fff ); + + R0 += 0; // clear flags + NOP; + NOP; + NOP; + NOP; + pass diff --git a/sim/testsuite/bfin/events.s b/sim/testsuite/bfin/events.s new file mode 100644 index 0000000..689f47b --- /dev/null +++ b/sim/testsuite/bfin/events.s @@ -0,0 +1,44 @@ +# Blackfin testcase for event processing +# mach: bfin + + .include "testutils.inc" + + start + + # Run enough instructions to trigger event processing + # and thus cpu stopping/restarting + + R0 = 0; + imm32 R1, 100000 + +3: + R0 += 1; # 1 + R0 += 1; + R0 += 1; # 3 + R0 += 1; + R0 += 1; # 5 + R0 += 1; + R0 += 1; # 7 + R0 += 1; + R0 += 1; # 9 + R0 += 1; + R0 += 1; # 11 + R0 += 1; + R0 += 1; # 13 + R0 += 1; + R0 += 1; # 15 + R0 += 1; + R0 += 1; # 17 + R0 += 1; + R0 += 1; # 19 + R0 += 1; + + CC = R0 < R1; + IF CC JUMP 3b; + + CC = R0 == R1; + IF !CC JUMP 1f; + + pass +1: + fail diff --git a/sim/testsuite/bfin/f221.s b/sim/testsuite/bfin/f221.s new file mode 100644 index 0000000..7968843 --- /dev/null +++ b/sim/testsuite/bfin/f221.s @@ -0,0 +1,56 @@ +# Blackfin testcase for the CEC (handling exceptions from usermode) +# mach: bfin +# sim: --environment operating + + .include "testutils.inc" + + start +.ifndef BFIN_HOST + // load address of exception handler + imm32 p0, 0xFFE02000; /* EVT0 */ + R0 = exception_handler (Z); + R0.H = exception_handler; + [ P0 + (4*3) ] = R0; + // Jump to User mode and enable exceptions + R0 = UserCode (Z); + R0.H = UserCode; + RETI = R0; + RTI; + +UserCode: + R4 = 0xec39 (Z); + R0 = 0xcafe (Z); + L3 = 0xf41f (Z); + L3.H = 0x1ce9; + I3 = 0xfe10 (Z); + I3.H = 0x20a9; + B3 = 0x4552 (Z); + B3.H = 0x15f0; + + // should except - r4 dep + // R4 = R4 >> 25 || W [ I3 ++ ] = R0.H || R4 = [ I3 ]; +.Lskip_start: + .rep 8 + .byte 0xff + .endr + dbg_fail; +.Lskip_end: + NOP; + NOP; + NOP; + NOP; + NOP; + dbg_pass; + +exception_handler: + // just skip over excepting instructions + R0 = RETX; + R1.L = .Lskip_start; + R1.H = .Lskip_start; + R2.L = .Lskip_end; + R2.H = .Lskip_end; + R2 = R2 - R1; + R0 = R0 + R2; + RETX = R0; + RTX; +.endif diff --git a/sim/testsuite/bfin/fact.s b/sim/testsuite/bfin/fact.s new file mode 100644 index 0000000..aed8153 --- /dev/null +++ b/sim/testsuite/bfin/fact.s @@ -0,0 +1,51 @@ +# Blackfin testcase for factorial +# mach: bfin + + .include "testutils.inc" + + start + + .macro factorial num:req answer:req + R0 = \num (Z); + CALL _fact; + imm32 r1, \answer; + CC = R1 == R0; + if CC JUMP 1f; + fail +1: + .endm + +_test: + factorial 1 1 + factorial 2 2 + factorial 3 6 + factorial 4 24 + factorial 5 120 + factorial 6 720 + factorial 7 5040 + factorial 8 40320 + factorial 9 362880 + factorial 10 3628800 + factorial 11 39916800 + factorial 12 479001600 +# This is the real answer, but it overflows 32bits. Since gas itself +# likes to choke on 64bit values when compiled for 32bit systems, just +# specify the truncated 32bit value since that's what the Blackfin will +# come up with too. +# factorial 13 6227020800 + factorial 13 1932053504 + pass + +_fact: + LINK 0; + [ -- SP ] = R7; + CC = R0 < 2; + IF CC JUMP 1f; + R7 = R0; + R0 += -1; + CALL _fact; + R0 *= R7; +1: + R7 = [ SP ++ ]; + UNLINK; + RTS; diff --git a/sim/testsuite/bfin/fir.s b/sim/testsuite/bfin/fir.s new file mode 100644 index 0000000..0ba4d2f --- /dev/null +++ b/sim/testsuite/bfin/fir.s @@ -0,0 +1,201 @@ +# mach: bfin + +// FIR FILTER COMPTUED DIRECTLY ON INPUT WITH NO +// INTERNAL STATE +// TWO OUTPUTS PER ITERATION +// This program computes a FIR filter without maintaining a buffer of internal +// state. +// This example computes two output samples per inner loop. The following +// diagram shows the alignment required for signal x and coefficients c: +// x0 x1 x2 x3 x4 x5 +// c0 c1 c2 c3 c4 -> output z(0)=x0*c0 + x1*c1 + ... +// c0 c1 c2 c3 c4 -> z(1)=x1*c0 + x2*c1 + ... +// L-1 +// --- +// Z(k) = \ c(n) * x(n+k) +// / +// --- +// n=0 +// Naive, first stab at spliting this for dual MACS. +// L/2-1 L/2-1 +// --- --- +// R(k) = \ (x(2n) * y(2n+k)) + \ (x(2n-1) * y(2n-1+k)) +// / / +// --- --- +// n=0 n=0 +// Alternate, better partitioning for the machine. +// L-1 +// --- +// R(0) = \ x(n) * y(n) +// / +// --- +// n=0 +// L-1 +// --- +// R(1) = \ x(n) * y(n+1) +// / +// --- +// n=0 +// L-1 +// --- +// R(2) = \ x(n) * y(n+2) +// / +// --- +// n=0 +// L-1 +// --- +// R(3) = \ x(n) * y(n+3) +// / +// --- +// n=0 +// . +// . +// . +// . +// Okay in this verion the inner loop will compute R(2k) and R(2k+1) in parallel +// L-1 +// --- +// R(2k) = \ x(n) * y(n+2k) +// / +// --- +// n=0 +// L-1 +// --- +// R(2k+1) = \ x(n) * y(n+2k+1) +// / +// --- +// n=0 +// Implementation +// -------------- +// Sample pair x1 x0 is loaded into register R0, and coefficients c1 c0 +// is loaded into register R1: +// +-------+ R0 +// | x1 x0 | +// +-------+ +// +-------+ R1 +// | c1 c0 | compute two MACs: z(0)+=x0*c0, and z(1)+=x1*c0 +// +-------+ +// Now load x2 into lo half of R0, and compute the next two MACs: +// +-------+ R0 +// | x1 x2 | +// +-------+ +// +-------+ R1 +// | c1 c0 | compute z(0)+=x1*c1 and z(1)+=x2*c1 (c0 not used) +// +-------+ +// Meanwhile, load coefficient pair c3 c2 into R2, and x3 into hi half of R0: +// +-------+ R0 +// | x3 x2 | +// +-------+ +// +-------+ R2 +// | c3 c2 | compute z(0)+=x2*c2 and z(1)+=x3*c2 (c3 not used) +// +-------+ +// Load x4 into low half of R0: +// +-------+ R0 +// | x3 x4 | +// +-------+ +// +-------+ R1 +// | c3 c2 | compute z(0)+=x3*c3 and z(1)+=x4*c3 (c2 not used) +// +-------+ +// //This is a reference FIR function used to test: */ +//void firf (float input[], float output[], float coeffs[], +// long input_size, long coeffs_size) +//{ +// long i, k; +// for(i=0; i< input_size; i++){ +// output[i] = 0; +// for(k=0; k < coeffs_size; k++) +// output[i] += input[k+i] * coeffs[k]; +// } +//} + +.include "testutils.inc" + start + + + R0 = 0; R1 = 0; R2 = 0; + P1 = 128 (X); // Load loop bounds in R5, R6, and divide by 2 + P2 = 64 (X); + + // P0 holds pointer to input data in one memory + // bank. Increments by 2 after each inner-loop iter + loadsym P0, input; + + // Pointer to coeffs in alternate memory bank. + loadsym I1, coef; + + // Pointer to outputs in any memory bank. + loadsym I2, output; + + // Setup outer do-loop for M/2 iterations + // (2 outputs are computed per pass) + + LSETUP ( L$0 , L$0end ) LC0 = P1 >> 1; + +L$0: + loadsym I1, coef; + I0 = P0; + // Set-up inner do-loop for L/2 iterations + // (2 MACs are computed per pass) + + LSETUP ( L$1 , L$1end ) LC1 = P2 >> 1; + + // Load first two data elements in r0, + // and two coeffs into r1: + + R0.L = W [ I0 ++ ]; + A1 = A0 = 0 || R0.H = W [ I0 ++ ] || R1 = [ I1 ++ ]; + +L$1: + A1 += R0.H * R1.L, A0 += R0.L * R1.L || R0.L = W [ I0 ++ ] || NOP; +L$1end: + A1 += R0.L * R1.H, A0 += R0.H * R1.H || R0.H = W [ I0 ++ ] || R1 = [ I1 ++ ]; + + // Line 1: do 2 MACs and load next data element into RL0. + // Line 2: do 2 MACs, load next data element into RH0, + // and load next 2 coeffs + + R0.H = A1, R0.L = A0; + + // advance data pointer by 2 16b elements + P0 += 4; + +L$0end: + [ I2 ++ ] = R0; // store 2 outputs + + // Check results + loadsym I2, output; + + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0800 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1000 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x2000 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1000 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0800 ); + pass + + .data +input: + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x4000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .space ((128-10)*2); // must pad with zeros or uninitialized values. + + .data +coef: + .dw 0x1000 + .dw 0x2000 + .dw 0x4000 + .dw 0x2000 + .dw 0x1000 + .dw 0x0000 + .space ((64-6)*2); // must pad with zeros or uninitialized values. + + .data +output: + .space (128*4) diff --git a/sim/testsuite/bfin/fsm.s b/sim/testsuite/bfin/fsm.s new file mode 100644 index 0000000..a15ffa0 --- /dev/null +++ b/sim/testsuite/bfin/fsm.s @@ -0,0 +1,57 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R1 = 0; + R0 = R1; + R7 = 7; +L$10: + CC = R0 == 1; + IF CC JUMP L$14; + CC = R0 <= 1; + IF !CC JUMP L$30; + CC = R0 == 0; + IF CC JUMP L$12; + JUMP.S L$25; +L$30: + CC = R0 == R7; + IF CC JUMP L$16; + R5 = 17; + CC = R0 == R5; + IF CC JUMP L$23; + JUMP.S L$25; +L$12: + R1 += 5; + R0 = 1; + JUMP.S L$8; +L$14: + R1 <<= 4; + R0 = 4; + JUMP.S L$8; +L$16: + CC = BITTST ( R1 , 3 ); + IF CC JUMP L$17; + BITSET( R1 , 3 ); + R0 = 4; + JUMP.S L$20; +L$17: + BITSET( R1 , 5 ); + R0 = 14; +L$20: + JUMP.S L$8; +L$23: + R5 = 13; + R1 = R1 ^ R5; + R0 = 20; + JUMP.S L$8; +L$25: + R1 += 1; + R0 += 1; +L$8: + R5 = 19; + CC = R0 <= R5; + IF CC JUMP L$10 (BP); + DBGA ( R0.L , 20 ); DBGA ( R1.L , 140 ); + pass diff --git a/sim/testsuite/bfin/greg2.s b/sim/testsuite/bfin/greg2.s new file mode 100644 index 0000000..7135130 --- /dev/null +++ b/sim/testsuite/bfin/greg2.s @@ -0,0 +1,18 @@ +# mach: bfin + +.include "testutils.inc" + start + + r3.l=0x5678; + r3.h=0x1234; + + p5=8; + + p5=r3; + p5.l =4; + + r5=p5; + dbga( r5.h, 0x1234); + +_halt: + pass; diff --git a/sim/testsuite/bfin/hwloop-bits.S b/sim/testsuite/bfin/hwloop-bits.S new file mode 100644 index 0000000..76d9003 --- /dev/null +++ b/sim/testsuite/bfin/hwloop-bits.S @@ -0,0 +1,104 @@ +# Blackfin testcase for HW Loops and user->super transitions +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + .macro check_hwloop_regs lc:req, lt:req, lb:req + R0 = LC0; + CC = R0 == \lc; + IF !CC JUMP fail; + + R0 = LT0; + CC = R0 == \lt; + IF !CC JUMP fail; + + R0 = LB0; + CC = R0 == \lb; + IF !CC JUMP fail; + + R0 = LC1; + CC = R0 == \lc; + IF !CC JUMP fail; + + R0 = LT1; + CC = R0 == \lt; + IF !CC JUMP fail; + + R0 = LB1; + CC = R0 == \lb; + IF !CC JUMP fail; + .endm + + start + + imm32 P0, EVT3; + loadsym R0, exception; + [P0] = R0; + + imm32 P0, EVT2; + loadsym R0, nmi; + [P0] = R0; + + loadsym R0, usermode; + RETI = R0; + + # Set the LC/LB/LT up with LSB set + # - Hardware clears LT LSB, but LB remains until we lower + imm32 R6, 0xaaaa5555 + R4 = R6; + BITCLR (R4, 0); + imm32 R7, 0xaa55aa55 + R5 = R7; + BITCLR (R5, 0); + + LC0 = R6; + LT0 = R6; + LB0 = R7; + LC1 = R6; + LT1 = R6; + LB1 = R7; + + # Sanity check + check_hwloop_regs R6, R4, R7 + + RTI; + +usermode: + # Make sure LSB has been cleared in LB + check_hwloop_regs R6, R4, R5 + + # Clear LSB in all LC/LT/LB + LC0 = R4; + LT0 = R4; + LB0 = R5; + LC1 = R4; + LT1 = R4; + LB1 = R5; + + # Now move back up to supervisor + EXCPT 4; + +exception: + # Make sure LSB is set in LB + check_hwloop_regs R4, R4, R7 + + # Clear the LSB and move up another supervisor level + LC0 = R4; + LT0 = R4; + LB0 = R5; + LC1 = R4; + LT1 = R4; + LB1 = R5; + + RAISE 2; + +nmi: + # Make sure LSB stayed clear + check_hwloop_regs R4, R4, R5 + + dbg_pass + +fail: + dbg_fail diff --git a/sim/testsuite/bfin/hwloop-branch-in.s b/sim/testsuite/bfin/hwloop-branch-in.s new file mode 100644 index 0000000..c477c94 --- /dev/null +++ b/sim/testsuite/bfin/hwloop-branch-in.s @@ -0,0 +1,99 @@ +# Blackfin testcase for branching into the middle of a hardware loop +# mach: bfin + + .include "testutils.inc" + + .macro test_prep lc:req + loadsym P5, 1f; + dmm32 LC0, \lc + R5 = 0; + R6 = 0; + R7 = 0; + .endm + + .macro test_check exp5:req, exp6:req, exp7:req, expLC:req +1: + imm32 R4, \exp5; + CC = R4 == R5; + IF !CC JUMP 2f; + imm32 R4, \exp6; + CC = R4 == R6; + IF !CC JUMP 2f; + imm32 R4, \exp7; + CC = R4 == R7; + IF !CC JUMP 2f; + R3 = LC0; + imm32 R4, \expLC; + CC = R4 == R3; + IF !CC JUMP 2f; + JUMP 3f; +2: fail +3: + .endm + + .macro test_rts entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req + loadsym R1, \entry; + RETS = R1; + test_prep \lc + RTS; + test_check \exp5, \exp6, \exp7, \expLC + .endm + + .macro test_jump entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req + loadsym P1, \entry; + test_prep \lc + JUMP (P1); + test_check \exp5, \exp6, \exp7, \expLC + .endm + + start + + loadsym R1, hws; + LT0 = R1; + loadsym R1, hwe; + LB0 = R1; + + test_rts hws, 0, 1, 1, 1, 0 + test_rts hws, 1, 1, 1, 1, 0 + test_rts hws, 2, 2, 2, 2, 0 + test_rts hws, 20, 20, 20, 20, 0 + + test_rts hwm, 0, 0, 1, 1, 0 + test_rts hwm, 1, 0, 1, 1, 0 + test_rts hwm, 2, 1, 2, 2, 0 + test_rts hwm, 20, 19, 20, 20, 0 + + test_rts hwe, 0, 0, 0, 1, 0 + test_rts hwe, 1, 0, 0, 1, 0 + test_rts hwe, 2, 1, 1, 2, 0 + test_rts hwe, 20, 19, 19, 20, 0 + + test_rts hwp, 0, 0, 0, 0, 0 + test_rts hwp, 1, 0, 0, 0, 1 + test_rts hwp, 2, 0, 0, 0, 2 + + test_jump hws, 0, 1, 1, 1, 0 + test_jump hws, 1, 1, 1, 1, 0 + test_jump hws, 2, 2, 2, 2, 0 + test_jump hws, 20, 20, 20, 20, 0 + + test_jump hwm, 0, 0, 1, 1, 0 + test_jump hwm, 1, 0, 1, 1, 0 + test_jump hwm, 2, 1, 2, 2, 0 + test_jump hwm, 20, 19, 20, 20, 0 + + test_jump hwe, 0, 0, 0, 1, 0 + test_jump hwe, 1, 0, 0, 1, 0 + test_jump hwe, 2, 1, 1, 2, 0 + test_jump hwe, 20, 19, 19, 20, 0 + + test_jump hwp, 0, 0, 0, 0, 0 + test_jump hwp, 1, 0, 0, 0, 1 + test_jump hwp, 2, 0, 0, 0, 2 + + pass + +hws: R5 += 1; +hwm: R6 += 1; +hwe: R7 += 1; +hwp: JUMP (P5); diff --git a/sim/testsuite/bfin/hwloop-branch-out.s b/sim/testsuite/bfin/hwloop-branch-out.s new file mode 100644 index 0000000..54f712b --- /dev/null +++ b/sim/testsuite/bfin/hwloop-branch-out.s @@ -0,0 +1,129 @@ +# Blackfin testcase for branching out of the middle of a hardware loop +# mach: bfin + + .include "testutils.inc" + + .macro test_prep lc:req, sym:req + imm32 P0, \lc + loadsym P1, \sym + R5 = 0; + R6 = 0; + R7 = 0; + LSETUP (1f, 2f) LC0 = P0; + .endm + + .macro test_check exp5:req, exp6:req, exp7:req, expLC + imm32 R4, \exp5; + CC = R4 == R5; + IF !CC JUMP 2f; + imm32 R4, \exp6; + CC = R4 == R6; + IF !CC JUMP 2f; + imm32 R4, \exp7; + CC = R4 == R7; + IF !CC JUMP 2f; + R3 = LC0; + imm32 R4, \expLC; + CC = R4 == R3; + IF !CC JUMP 2f; + JUMP 3f; +2: fail +3: + .endm + + start + mnop; + +test_jump_s: + .macro test_jump_s lc:req + test_prep \lc, 3f +1: JUMP (P1); + R5 += 1; +2: R6 += 1; + fail +3: R7 += 1; + test_check 0, 0, 1, \lc + .endm + test_jump_s 0 + test_jump_s 1 + test_jump_s 2 + test_jump_s 10 + +test_jump_m: + .macro test_jump_m lc:req + test_prep \lc, 3f +1: R5 += 1; + JUMP (P1); +2: R6 += 1; + fail +3: R7 += 1; + test_check 1, 0, 1, \lc + .endm + test_jump_m 0 + test_jump_m 1 + test_jump_m 2 + test_jump_m 10 + +test_jump_e: + .macro test_jump_e lc:req, lcend:req + test_prep \lc, 3f +1: R5 += 1; + R6 += 1; +2: JUMP (P1); + fail +3: R7 += 1; + test_check 1, 1, 1, \lcend + .endm + test_jump_e 0, 0 + test_jump_e 1, 0 + test_jump_e 2, 1 + test_jump_e 10, 9 + +test_call_s: + .macro test_call_s lc:req, exp5:req, exp6:req, exp7:req + test_prep \lc, __ret +1: CALL (P1); + R5 += 1; +2: R6 += 1; +3: R7 += 1; + test_check \exp5, \exp6, \exp7, 0 + .endm + test_call_s 0, 1, 1, 2 + test_call_s 1, 1, 1, 2 + test_call_s 2, 2, 2, 3 + test_call_s 10, 10, 10, 11 + +test_call_m: + .macro test_call_m lc:req, exp5:req, exp6:req, exp7:req + test_prep \lc, __ret +1: R5 += 1; + CALL (P1); +2: R6 += 1; +3: R7 += 1; + test_check \exp5, \exp6, \exp7, 0 + .endm + test_call_m 0, 1, 1, 2 + test_call_m 1, 1, 1, 2 + test_call_m 2, 2, 2, 3 + test_call_m 10, 10, 10, 11 + +test_call_e: + .macro test_call_e lc:req, exp5:req, exp6:req, exp7:req + test_prep \lc, __ret +1: R5 += 1; + R6 += 1; +2: CALL (P1); +3: R7 += 1; + test_check \exp5, \exp6, \exp7, 0 + .endm + test_call_e 0, 1, 1, 2 + test_call_e 1, 1, 1, 2 + test_call_e 2, 2, 2, 3 + test_call_e 10, 10, 10, 11 + + pass + +__ret: + nop;nop;nop; + R7 += 1; + rts; diff --git a/sim/testsuite/bfin/hwloop-lt-bits.s b/sim/testsuite/bfin/hwloop-lt-bits.s new file mode 100644 index 0000000..dd21c8a --- /dev/null +++ b/sim/testsuite/bfin/hwloop-lt-bits.s @@ -0,0 +1,25 @@ +# Blackfin testcase for HW Loops (LT) LSB behavior +# mach: bfin + + .include "testutils.inc" + + start + + # Loading LT should always clear LSB + imm32 R6, 0xaaaa5555 + R4 = R6; + BITCLR (R4, 0); + + LT0 = R6; + LT1 = R6; + + R0 = LT0; + CC = R0 == R4; + IF ! CC JUMP 1f; + + R0 = LT1; + CC = R0 == R4; + IF ! CC JUMP 1f; + + pass +1: fail diff --git a/sim/testsuite/bfin/hwloop-nested.s b/sim/testsuite/bfin/hwloop-nested.s new file mode 100644 index 0000000..9d1b71c --- /dev/null +++ b/sim/testsuite/bfin/hwloop-nested.s @@ -0,0 +1,33 @@ +# Blackfin testcase for overlapping nested hwloops (LB) +# mach: bfin + + .include "testutils.inc" + + start + + R0 = 0; + R1 = 0; + P0 = 2; + P1 = 2; + LSETUP (1f, 3f) LC0 = P0; +1: R0 += 1; + + LSETUP (2f, 3f) LC1 = P1; +2: R1 += 1; + + CC = R1 == 2; + IF !CC JUMP 3f; + CC = R0 == 1; + IF !CC JUMP fail; + R3 = LC0; + CC = R3 == 2; + IF !CC JUMP fail; + R3 = LC1; + CC = R3 == 1; + IF !CC JUMP fail; + pass + +3: nop; + +fail: + fail diff --git a/sim/testsuite/bfin/i0.s b/sim/testsuite/bfin/i0.s new file mode 100644 index 0000000..89c7fd5 --- /dev/null +++ b/sim/testsuite/bfin/i0.s @@ -0,0 +1,57 @@ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + R0.L = 0x1234; + R0.H = 0x7765; + DBGA ( R0.L , 0x1234 ); + DBGA ( R0.H , 0x7765 ); + R0.L = -1; + DBGA ( R0.H , 0x7765 ); + DBGA ( R0.L , 0xffff ); + + R0.L = 0x5555; + R0.H = 0xAAAA; + DBGA ( R0.H , 0xAAAA ); + DBGA ( R0.L , 0x5555 ); + + I0.L = 0x1234; + I0.H = 0x256; + R0 = I0; + DBGA ( R0.L , 0x1234 ); + DBGA ( R0.H , 0x256 ); + + R0 = -50; + R1 = -77 (X); + R2 = -99 (X); + R3 = 32767 (X); + R4 = -32768 (X); + R5 = 256 (X); + R6 = 128 (X); + R7 = 1023 (X); + DBGA ( R0.L , 0xffce ); + DBGA ( R1.L , 0xffb3 ); + DBGA ( R2.L , 0xff9d ); + DBGA ( R3.L , 0x7fff ); + DBGA ( R4.L , 0x8000 ); + DBGA ( R5.L , 256 ); + DBGA ( R6.L , 128 ); + DBGA ( R7.L , 1023 ); + + R6 = -1; + DBGA ( R6.L , 0xffff ); + + R0.L = 0x5555; + R1.L = 0xaaaa; + + DBGA ( R0.L , 0x5555 ); + DBGA ( R1.L , 0xaaaa ); + + R0 = R0 + R1; + DBGA ( R0.H , 0xfffe ); + + pass diff --git a/sim/testsuite/bfin/iir.s b/sim/testsuite/bfin/iir.s new file mode 100644 index 0000000..b1cb420 --- /dev/null +++ b/sim/testsuite/bfin/iir.s @@ -0,0 +1,207 @@ +# mach: bfin + +// GENERIC BIQUAD: +// --------------- +// x ---------+---------|---------+-------y +// | |t1 | +// | D | +// | a1 | b1 | +// +---<-----|---->----+ +// | | | +// | D | D's are delays +// | a2 | b2 | ">" represent multiplications +// +---<-----|---->----+ +// To test this routine, use a biquad with a pole pair at z = (0.7 +- 0.1j), +// and a double zero at z = -1.0, which is a low-pass. The transfer function is: +// 1 + 2z^-1 + z^-2 +// H(z) = ---------------------- +// 1 - 1.4z^-1 + 0.5z^-2 +// a1 = 1.4 +// a2 = -0.5 +// b1 = 2 +// b2 = 1 +// This filter conforms to the biquad test in BDT, since it has coefficients +// larger than 1.0 in magnitude, and b0=1. (Note that the a's have a negative +// sign.) +// This filter can be simulated in matlab. To simulate one biquad, use +// A = [1.0, -1.4, 0.5] +// B = [1, 2, 1] +// Y=filter(B,A,X) +// To simulate two cascaded biquads, use +// Y=filter(B,A,filter(B,A,X)) +// SCALED COEFFICIENTS: +// -------------------- +// In order to conform to 1.15 representation, must scale coeffs by 0.5. +// This requires an additional internal re-scale. The equations for the Type II +// filter are: +// t1 = x + a1*t1*z^-1 + a2*t1*z^-2 +// y = b0*t1 + b1*t1*z^-1 + b2*t1*z^-2 +// (Note inclusion of term b0, which in the example is b0 = 1.) +// If all coeffs are replaced by +// ai --> ai' = 0.5*a1 +// then the two equations become +// t1 = x + 2*a1'*t1*z^-1 + 2*a2'*t1*z^-2 +// 0.5*y = b0'*t1 + b1'*t1*z^-1 + b2'*t1*z^-2 +// which can be implemented as: +// 2.0 b0'=0.5 +// x ---------+--->-----|---->----+-------y +// | |t1 | +// | D | +// | a1' | b1' | +// +---<-----|---->----+ +// | | | +// | D | +// | a2' | b2' | +// +---<-----|---->----+ +// But, b0' can be eliminated by: +// x ---------+---------|---------+-------y +// | | | +// | V 2.0 | +// | | | +// | |t1 | +// | D | +// | a1' | b1' | +// +---<-----|---->----+ +// | | | +// | D | +// | a2' | b2' | +// +---<-----|---->----+ +// Function biquadf() computes this implementation on float data. +// CASCADED BIQUADS +// ---------------- +// Cascaded biquads are simulated by simply cascading copies of the +// filter defined above. However, one must be careful with the resulting +// filter, as it is not very stable numerically (double poles in the +// vecinity of +1). It would of course be better to cascade different +// filters, as that would result in more stable structures. +// The functions biquadf() and biquadR() have been tested with up to 3 +// stages using this technique, with inputs having small signal amplitude +// (less than 0.001) and under 300 samples. +// +// In order to pipeline, need to maintain two pointers into the state +// array: one to load (I0) and one to store (I2). This is required since +// the load of iteration i+1 is hoisted above the store of iteration i. + +.include "testutils.inc" + start + + + // I3 points to input buffer + loadsym I3, input; + + // P1 points to output buffer + loadsym P1, output; + + R0 = 0; R7 = 0; + + P2 = 10; + LSETUP ( L$0 , L$0end ) LC0 = P2; +L$0: + + // I0 and I2 are pointers to state + loadsym I0, state; + I2 = I0; + + // pointer to coeffs + loadsym I1, Coeff; + + R0.H = W [ I3 ++ ]; // load input value into RH0 + A0.w = R0; // A0 holds x + + P2 = 2; + LSETUP ( L$1 , L$1end ) LC1 = P2; + + // load 2 coeffs into R1 and R2 + // load state into R3 + R1 = [ I1 ++ ]; + MNOP || R2 = [ I1 ++ ] || R3 = [ I0 ++ ]; + +L$1: + + // A1=b1*s0 A0=a1*s0+x + A1 = R1.L * R3.L, A0 += R1.H * R3.L || R1 = [ I1 ++ ] || NOP; + + // A1+=b2*s1 A0+=a2*s1 + // and move scaled value in A0 (t1) into RL4 + A1 += R2.L * R3.H, R4.L = ( A0 += R2.H * R3.H ) (S2RND) || R2 = [ I1 ++ ] || NOP; + + // Advance state. before: + // R4 = uuuu t1 + // R3 = stat[1] stat[0] + // after PACKLL: + // R3 = stat[0] t1 + R5 = PACK( R3.L , R4.L ) || R3 = [ I0 ++ ] || NOP; + + // collect output into A0, and move to RL0. + // Keep output value in A0, since it is also + // the accumulator used to store the input to + // the next stage. Also, store updated state +L$1end: + R0.L = ( A0 += A1 ) || [ I2 ++ ] = R5 || NOP; + + // store output +L$0end: + W [ P1 ++ ] = R0; + + // Check results + loadsym I2, output; + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0028 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0110 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0373 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x075b ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0c00 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1064 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x13d3 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x15f2 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x16b9 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1650 ); + + pass + + .data +state: + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + + .data +Coeff: + .dw 0x7fff + .dw 0x5999 + .dw 0x4000 + .dw 0xe000 + .dw 0x7fff + .dw 0x5999 + .dw 0x4000 + .dw 0xe000 +input: + .dw 0x0028 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 +output: + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/bfin/issue103.s b/sim/testsuite/bfin/issue103.s new file mode 100644 index 0000000..6244a7f --- /dev/null +++ b/sim/testsuite/bfin/issue103.s @@ -0,0 +1,34 @@ +# mach: bfin + +.include "testutils.inc" + start + + A0 = 0; + A1 = 0; + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R2.H = 0xf12e; + R2.L = 0xbeaa; + R3.L = 0x00ff; + A1.w = R2; + A1.x = R3; + R0.H = 0xd136; + R0.L = 0x459d; + R1.H = 0xabd6; + R1.L = 0x9ec7; + + _DBG A1; + R5 = A1 , A0 = R1.L * R0.L (FU); + + DBGA ( R5.H , 0xffff ); + DBGA ( R5.L , 0xffff ); + + NOP; + NOP; + NOP; + NOP; + pass diff --git a/sim/testsuite/bfin/issue109.s b/sim/testsuite/bfin/issue109.s new file mode 100644 index 0000000..65b78b7 --- /dev/null +++ b/sim/testsuite/bfin/issue109.s @@ -0,0 +1,16 @@ +//Statement of problem... +//16-bit ashift and lshift uses a 6-bit signed magnitude, which gives a +//range from -32 to 31. test the boundary. +# mach: bfin + +.include "testutils.inc" + start + + + R1.L = 0x8000; + R0.L = -32; + R2.L = ASHIFT R1.L BY R0.L; + + DBGA ( R2.L , 0xffff ); + + pass diff --git a/sim/testsuite/bfin/issue112.s b/sim/testsuite/bfin/issue112.s new file mode 100644 index 0000000..e116936 --- /dev/null +++ b/sim/testsuite/bfin/issue112.s @@ -0,0 +1,38 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + A0 = 0; + A1 = 0; + R2.H = 0xfafa; + R2.L = 0xf5f6; + R3.L = 0x00ff; + A0.w = R2; + A0.x = R3; + R2.H = 0x7ebc; + R2.L = 0xd051; + R3 = 0; + A1.w = R2; + A1.x = R3; + R1.H = 0x7fff; + R1.L = 0x8000; + R0.H = 0x8000; + R0.L = 0x7fff; + A1 += R0.L * R1.L (M), R0.L = ( A0 = R0.H * R1.H ) (IH); + + _DBG A1; + R0 = A1.w; + R1 = A1.x; + DBGA ( R0.L , 0xffff ); + DBGA ( R0.H , 0x7fff ); + DBGA ( R1.L , 0 ); + + NOP; + NOP; + pass diff --git a/sim/testsuite/bfin/issue113.s b/sim/testsuite/bfin/issue113.s new file mode 100644 index 0000000..4bebaea --- /dev/null +++ b/sim/testsuite/bfin/issue113.s @@ -0,0 +1,18 @@ +# mach: bfin + +.include "testutils.inc" + start + + A0 = 0; + R0.L = 0x10; + A0.x = R0; + + R0.L = 0x0038; + R0.H = 0x0006; + + R0.L = SIGNBITS A0; + + DBGA ( R0.L , 0xfffa ); + DBGA ( R0.H , 0x0006 ); + + pass diff --git a/sim/testsuite/bfin/issue117.s b/sim/testsuite/bfin/issue117.s new file mode 100644 index 0000000..00e92b7 --- /dev/null +++ b/sim/testsuite/bfin/issue117.s @@ -0,0 +1,19 @@ +# mach: bfin + +.include "testutils.inc" + start + +// issue 117 + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + A0 = 0; + A1 = 0; + R0.L = 0x0400; + R1.L = 0x0010; + R2.L = ( A0 = R0.L * R1.L ) (S2RND); + + DBGA ( R2.L , 0x1 ); + pass diff --git a/sim/testsuite/bfin/issue118.s b/sim/testsuite/bfin/issue118.s new file mode 100644 index 0000000..bc455b3 --- /dev/null +++ b/sim/testsuite/bfin/issue118.s @@ -0,0 +1,41 @@ +# mach: bfin + +.include "testutils.inc" + start + + +// issue 118 + + R0 = 1; + R1 = 0; + A0.x = R1; + A0.w = R0; + + A0 = - A0; + + _DBG A0; + _DBG ASTAT; + +//R0 = ASTAT; +//DBGA ( R0.L , 0x2 ); + + cc = az; + r0 = cc; + dbga( r0.l, 0); + cc = an; + r0 = cc; + dbga( r0.l, 1); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + pass diff --git a/sim/testsuite/bfin/issue119.s b/sim/testsuite/bfin/issue119.s new file mode 100644 index 0000000..ade8818 --- /dev/null +++ b/sim/testsuite/bfin/issue119.s @@ -0,0 +1,26 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R0.L = -32768; + R0.H = 32767; + R1.L = 32767; + R1.H = -32768; + R2.H = (A1 = R0.L * R1.H) (M), R2.L = (A0 = R0.L * R1.L) (TFU); + + _DBG R2; + DBGA ( R2.L , 0x3fff ); + DBGA ( R2.H , 0xc000 ); + + R3 = ( A1 = R0.L * R1.H ) (M), R2 = ( A0 = R0.L * R1.L ) (FU); + + _DBG R3; + DBGA ( R3.L , 0 ); + DBGA ( R3.H , 0xc000 ); + + pass diff --git a/sim/testsuite/bfin/issue121.s b/sim/testsuite/bfin/issue121.s new file mode 100644 index 0000000..7e609cd --- /dev/null +++ b/sim/testsuite/bfin/issue121.s @@ -0,0 +1,40 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + R0.L = 32767; + R0.H = 32767; + R1.L = -32768; + R1.H = -32768; + R0.L = R0 + R1 (RND12); + + _DBG R0; + _DBG ASTAT; +//R1 = ASTAT; +//_DBG R1; + +//DBGA ( R1.H , 0x0 ); +//DBGA ( R1.L , 0x0001 ); + cc = az; + r0 = cc; + dbga( r0.l, 1); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + pass diff --git a/sim/testsuite/bfin/issue123.s b/sim/testsuite/bfin/issue123.s new file mode 100644 index 0000000..9f40c3f --- /dev/null +++ b/sim/testsuite/bfin/issue123.s @@ -0,0 +1,20 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0.L = 0x7bb8; + R0.H = 0x8d5e; + R4.L = 0x7e1c; + R4.H = 0x9e22; +// end load regs and acc; + R6.H = R4.H * R0.L (M), R6.L = R4.L * R0.H (ISS2); + + _DBG R6; + + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x8000 ); + +//------------- + + pass diff --git a/sim/testsuite/bfin/issue124.s b/sim/testsuite/bfin/issue124.s new file mode 100644 index 0000000..b28f141 --- /dev/null +++ b/sim/testsuite/bfin/issue124.s @@ -0,0 +1,26 @@ +# mach: bfin + +.include "testutils.inc" + start + +// issue 124 + + R0 = 0; + R1.L = 0x80; + + A0.w = R0; + A0.x = R1; + + A1.w = R0; + A1.x = R1; + + _DBG A0; + _DBG A1; + + R5 = ( A0 += A1 ); + + _DBG A0; + R7 = A0.w; DBGA ( R7.H , 0 ); DBGA ( R7.L , 0 ); + R7 = A0.x; DBGA ( R7.L , 0xff80 ); + + pass diff --git a/sim/testsuite/bfin/issue125.s b/sim/testsuite/bfin/issue125.s new file mode 100644 index 0000000..826bf7f --- /dev/null +++ b/sim/testsuite/bfin/issue125.s @@ -0,0 +1,75 @@ +# mach: bfin + +.include "testutils.inc" + start + + A0 = 0; + A1 = 0; + R0 = -1; + R1 = 0; + R1.L = 0x007f; + A0.w = R0; + A0.x = R1; + A1.w = R0; + A1.x = R1; + _DBG A0; + _DBG A1; + _DBG astat; + A0 += A1; + + _DBG A0; +// _DBG ASTAT; +// R0 = ASTAT; +// _DBG R0; +// DBGA ( R0.L , 0x0 ); +// DBGA ( R0.H , 0x3 ); + cc = az; + r0 = cc; + dbga( r0.l, 0); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 1); + cc = av0s; + r0 = cc; + dbga( r0.l, 1); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + A1 = 0; + _DBG A0; + A0 += A1; + + _DBG A0; +// _DBG ASTAT; +// R0 = ASTAT; +// _DBG R0; + +// DBGA ( R0.L , 0 ); +// DBGA ( R0.H , 2 ); + cc = az; + r0 = cc; + dbga( r0.l, 0); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 1); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + pass diff --git a/sim/testsuite/bfin/issue126.s b/sim/testsuite/bfin/issue126.s new file mode 100644 index 0000000..ff15bac --- /dev/null +++ b/sim/testsuite/bfin/issue126.s @@ -0,0 +1,19 @@ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + P1 = R0; + P2 = R0; + + R0 = R0; + P1 = ( P1 + P0 ) << 2; + P2 = ( P2 + P0 ) << 1; + + _DBG ASTAT; + R5 = ASTAT; + DBGA ( R5.H , 0 ); DBGA ( R5.L , 0 ); + + pass diff --git a/sim/testsuite/bfin/issue127.s b/sim/testsuite/bfin/issue127.s new file mode 100644 index 0000000..811bc37 --- /dev/null +++ b/sim/testsuite/bfin/issue127.s @@ -0,0 +1,35 @@ +# mach: bfin + +.include "testutils.inc" + start + +// load acc with values; + R0.L = 0x5d8c; + R0.H = 0x90c4; + A0.w = R0; + R0.L = 0x8308; + A0.x = R0; + R0.L = 0x32da; + R0.H = 0xa6ec; + A1.w = R0; + R0.L = 0x1772; + A1.x = R0; +// load regs with values; + R0.L = 0x83de; + R0.H = 0x7070; + R1.L = 0x8b86; + R1.H = 0x85ac; + R2.L = 0x2398; + R2.H = 0x3adc; + R3.L = 0x1480; + R3.H = 0x7f90; +// end load regs and acc; + SAA ( R1:0 , R3:2 ) (R); + + _DBG A0; + _DBG A1; + + R0 = A0.x; DBGA ( R0.L , 0 ); + R0 = A1.x; DBGA ( R0.L , 0 ); + + pass diff --git a/sim/testsuite/bfin/issue129.s b/sim/testsuite/bfin/issue129.s new file mode 100644 index 0000000..f9653a8 --- /dev/null +++ b/sim/testsuite/bfin/issue129.s @@ -0,0 +1,36 @@ +# Blackfin testcase for PREGS and BREV +# mach: bfin + + .include "testutils.inc" + + start + +// issue 129 + + P0.L = 0x0000; + P0.H = 0x8000; + + P4.L = 0x0000; + P4.H = 0x8000; + + P4 += P0 (BREV); + + R0 = P4; + DBGA ( R0.H , 0x4000 ); + DBGA ( R0.L , 0 ); + +//-------------- + + P0.L = 0x0000; + P0.H = 0xE000; + + P4.L = 0x1f09; + P4.H = 0x9008; + + P4 += P0 (BREV); + + R0 = P4; + DBGA ( R0.H , 0x0808 ); + DBGA ( R0.L , 0x1f09 ); + + pass diff --git a/sim/testsuite/bfin/issue139.S b/sim/testsuite/bfin/issue139.S new file mode 100644 index 0000000..8df28ba --- /dev/null +++ b/sim/testsuite/bfin/issue139.S @@ -0,0 +1,108 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ASTAT = R0; + R0.L = 0x33; + R0.H = 0x55; + R1.L = 0x66; + R1.H = 0x77; + R7 = R1 +|+ R0, R6 = R1 -|- R0 (SCO , ASR); + + _DBG R7; + CHECKREG R7, 0x0066004c; + CHECKREG R6, 0x00190011; + R7 = ASTAT + CHECKREG R7, 0; + +//----------------------- + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + R0.L = 0x33; + R0.H = 0x55; + R1.L = 0x66; + R1.H = 0x77; + R3 = R1 +|+ R0, R2 = R1 -|- R0 (ASR); + + R7 = ASTAT; + CHECKREG R7, 0; + +//----------------------- + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + R0.L = 0x33; + R0.H = 0x55; + R1.L = 0x66; + R1.H = 0x77; + R5 = R1 +|+ R0, R4 = R1 -|- R0 (CO , ASR); + + R7 = ASTAT; + CHECKREG R7, 0; + +//----------------------- + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + R0.L = 0x33; + R0.H = 0x55; + R1.L = 0x66; + R1.H = 0x77; + R3 = R1 +|+ R0, R2 = R1 -|- R0 (ASL); + CHECKREG R3, 0x01980132; + CHECKREG R2, 0x00440066; + + R7 = ASTAT; + CHECKREG R7, 0; + +//----------------------- + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + R0.L = 0x33; + R0.H = 0x55; + R1.L = 0x7fff; + R1.H = 0x77; + R3 = R1 +|+ R0, R2 = R1 -|- R0 (S , ASL); + CHECKREG R3, 0x01987fff; + CHECKREG R2, 0x00447fff; + + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY); + + pass diff --git a/sim/testsuite/bfin/issue140.S b/sim/testsuite/bfin/issue140.S new file mode 100644 index 0000000..df27517 --- /dev/null +++ b/sim/testsuite/bfin/issue140.S @@ -0,0 +1,22 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + R6.L = -32768; + R6.H = -32768; + R1.L = -32768; + R1.H = -32768; + + R4 = R6.L * R1.H; + + _DBG ASTAT; + + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY); + + pass diff --git a/sim/testsuite/bfin/issue142.s b/sim/testsuite/bfin/issue142.s new file mode 100644 index 0000000..be290b5 --- /dev/null +++ b/sim/testsuite/bfin/issue142.s @@ -0,0 +1,34 @@ +# mach: bfin + +.include "testutils.inc" + start + +// load acc with values; + imm32 R0, 0x7d647b42; + A0.w = R0; + R0 = 0x0000 (Z); + A0.x = R0; + + imm32 R0, 0x7be27f50; + A1.w = R0; + R0 = 0x0000 (Z); + A1.x = R0; + +// load regs with values; + I1 = 0 (X); + I0 = 1 (X); + imm32 R2, 0xefef1212; + imm32 R3, 0xf23c0189; + + SAA ( R3:2 , R3:2 ) (R); + + R0 = A0.w + CHECKREG R0, 0x7d9f7bca; + R0 = A0.x + CHECKREG R0, 0; + R1 = A1.w; + CHECKREG R1, 0x7cc28006; + R1 = A1.x; + CHECKREG R1, 0; + + pass diff --git a/sim/testsuite/bfin/issue144.s b/sim/testsuite/bfin/issue144.s new file mode 100644 index 0000000..3c029a3 --- /dev/null +++ b/sim/testsuite/bfin/issue144.s @@ -0,0 +1,31 @@ +# mach: bfin + +.include "testutils.inc" + start + + a0=0; + R0.L = 1; + R0.H = 0; + R0 *= R0; + _DBG R0; + _DBG A0; + + R7 = A0.w; + DBGA ( R7.H , 0 ); DBGA ( R7.L , 0 ); + + R0.L = -1; + R0.H = 32767; + + _DBG R0; + + a0=0; + R0 *= R0; + + _DBG R0; + _DBG A0; + R7 = A0.w; + DBGA ( R7.H , 0 ); DBGA ( R7.L , 0 ); + R7 = A0.x; + DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/bfin/issue146.S b/sim/testsuite/bfin/issue146.S new file mode 100644 index 0000000..b14e78c --- /dev/null +++ b/sim/testsuite/bfin/issue146.S @@ -0,0 +1,32 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + +// razor issue 146 + + A0 = 0; + A1 = 0; + R0 = 0; + ASTAT = R0; + R1 = 0; + R0.L = 0x891b; + R0.H = 0x8537; + R1.L = 0xab2d; + R1.H = 0x3759; + A0 = R0; + A1 = R1; + + _DBG A0; + _DBG A1; + + R3 = A1 + A0, R7 = A1 - A0 (S); + _DBG R3; + _DBG R7; + + _DBG ASTAT; + R0 = ASTAT; + CHECKREG R0, (_VS|_V|_V_COPY|_AN); + + pass diff --git a/sim/testsuite/bfin/issue175.s b/sim/testsuite/bfin/issue175.s new file mode 100644 index 0000000..3073823 --- /dev/null +++ b/sim/testsuite/bfin/issue175.s @@ -0,0 +1,34 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + imm32 R1, 0x80007fff; + imm32 R0, 0x00010001; + R0 = R1 +|+ R0, R2 = R1 -|- R0 (S , ASL); + _DBG R0; + _DBG R2; + CHECKREG R0, 0x80007fff; + CHECKREG R2, 0x80007fff; + + R0 = ASTAT; + _dbg r0; + DBGA ( R0.L , 0x000a ); + DBGA ( R0.H , 0x0300 ); + + R0 = 0; + R1 = 0; + R4 = 0; + ASTAT = R0; + R4 = R1 +|+ R0, R0 = R1 -|- R0 (S , ASL); + _DBG R4; + _DBG R0; + R7 = ASTAT; + _DBG R7; + _DBG ASTAT; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + + pass diff --git a/sim/testsuite/bfin/issue205.s b/sim/testsuite/bfin/issue205.s new file mode 100644 index 0000000..44cb1e0 --- /dev/null +++ b/sim/testsuite/bfin/issue205.s @@ -0,0 +1,66 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0; R1 = 0; R2 = 0; R3 = 0; R4 = 0; R5 = 0; R6 = 0; R7 = 0; + P0 = 0; P1 = 0; P2 = 0; P4 = 0; P5 = 0; + I0 = 0 (X); I1 = 0 (X); I2 = 0 (X); I3 = 0 (X); + M0 = 0 (X); M1 = 0 (X); M2 = 0 (X); M3 = 0 (X); + L0 = 0 (X); L1 = 0 (X); L2 = 0 (X); L3 = 0 (X); + B0 = 0 (X); B1 = 0 (X); B2 = 0 (X); B3 = 0 (X); + + R0 = -1; + R1 = 0x1234 (X); + R2 = -2000 (X); + R3 = 2000 (X); + R4 = 0; + R5 = 1; + R6 = 5555 (X); + R7 = -1000 (X); + + loadsym P1, tmp0; + loadsym P2, tmp1; + loadsym P4, tmp2; + + I1 = P1; + I2 = P2; + I3 = P4; + + + R0.L = 0x0017; + R0.H = 0xffff; + R0.L = EXPADJ( R2 , R1.L ) || [ P2 ] = R0 || NOP; + R6 = [ P2 ]; + DBGA ( R6.L , 0x17 ); + DBGA ( R6.H , 0xffff ); + + DBGA ( R0.L , 0x1234 ); + DBGA ( R0.H , 0xffff ); + + pass + + .data +tmp0: + .dd 0x12345678 // 0x1000 + .dd 0x10101010 // 0x1004 + .dd 0x55555555 // 0x1008 + .dd 0xaaaaaaaa // 0x100c + .dd 0xffffffff // 0x1010 + + .data +tmp1: + .dd 0xabcdefef // 0x2000 + .dd 0x12121212 // 0x2004 + .dd 0x45454545 // 0x2008 + .dd 0xabababab // 0x200c + .dd 0x0f0f0f0f // 0x2010 + + .data +tmp2: + .dd 0xff00ff00 // 0x3000 + .dd 0x02020202 // 0x3004 + .dd 0x4f4f4f45 // 0x3008 + .dd 0xafafafaf // 0x300c + .dd 0x1f1f1f1f // 0x3010 diff --git a/sim/testsuite/bfin/issue257.s b/sim/testsuite/bfin/issue257.s new file mode 100644 index 0000000..01f0396 --- /dev/null +++ b/sim/testsuite/bfin/issue257.s @@ -0,0 +1,28 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0; + R1 = 0; + R2 = 0; + R0.H = 0xfffe; + R0.L = 0x9be8; + R1.L = 0xeb53; + R2.H = R0 - R1 (RND20); + + _DBG R2; + _DBG ASTAT; + DBGA ( R2.H , 0 ); + + R0 = ASTAT; +//DBGA ( R0.L , 1 ); + cc = az; + r0 = cc; + dbga( r0.l, 1); + cc = an; + r0 = cc; + dbga( r0.l, 0); + + pass diff --git a/sim/testsuite/bfin/issue272.S b/sim/testsuite/bfin/issue272.S new file mode 100644 index 0000000..ee8ec38 --- /dev/null +++ b/sim/testsuite/bfin/issue272.S @@ -0,0 +1,23 @@ +// When the RND12 instruction produces large negative results, the AV0 flag is +// should not be set. +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + R0.H = 0xcef4; + R0.L = 0x3ed6; + R1.H = 0x56f4; + R1.L = 0x417a; + R2.H = R0 - R1 (RND12); + + _DBG ASTAT; + R0 = ASTAT; + CHECKREG R0, (_VS|_V|_V_COPY|_AN); + CHECKREG R2, 0x80000000; + + pass diff --git a/sim/testsuite/bfin/issue83.s b/sim/testsuite/bfin/issue83.s new file mode 100644 index 0000000..2474d4b --- /dev/null +++ b/sim/testsuite/bfin/issue83.s @@ -0,0 +1,93 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0.H = -32768; + R0.L = 0; + R0 >>= 0x1; + + _DBG R0; + R7 = ASTAT; + _DBG R7; + +//DBGA ( R7.H , 0x0000 ); +//DBGA ( R7.L , 0x0000 ); + cc = az; + r0 = cc; + dbga( r0.l, 0); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + R0.H = 0; + R0.L = 1; + R0 <<= 0x1f; + + _DBG R0; + R7 = ASTAT; + _DBG R7; +//DBGA ( R7.H , 0x0000 ); +//DBGA ( R7.L , 0x0002 ); + cc = az; + r0 = cc; + dbga( r0.l, 0); + cc = an; + r0 = cc; + dbga( r0.l, 1); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + R1.L = -1; + R1.H = 32767; + R0 = 31; + R1 >>= R0; + + _DBG R1; + R7 = ASTAT; + _DBG R7; +//DBGA ( R7.H , 0x0000 ); +//DBGA ( R7.L , 0x0001 ); + cc = az; + r0 = cc; + dbga( r0.l, 1); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + pass diff --git a/sim/testsuite/bfin/issue89.s b/sim/testsuite/bfin/issue89.s new file mode 100644 index 0000000..24d0517 --- /dev/null +++ b/sim/testsuite/bfin/issue89.s @@ -0,0 +1,30 @@ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + R2.L = 0x000f; + R2.H = 0x038c; + _DBG R2; + + R7.L = 0x007c; + R7.H = 0x0718; + A0 = 0; + A0.w = R7; + _DBG A0; + + A0 = ROT A0 BY R2.L; + + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x003e ); + DBGA ( R4.L , 0x0001 ); + DBGA ( R5.H , 0xffff ); + DBGA ( R5.L , 0xff8c ); + + pass diff --git a/sim/testsuite/bfin/l0.s b/sim/testsuite/bfin/l0.s new file mode 100644 index 0000000..88fcb59 --- /dev/null +++ b/sim/testsuite/bfin/l0.s @@ -0,0 +1,137 @@ +// simple test to ensure that we can load data from memory. +# mach: bfin + +.include "testutils.inc" + start + + loadsym P0, tab; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + R6 = [ P0 ++ ]; + R7 = [ P0 ++ ]; + + DBGA ( R0.H , 0x1111 ); + DBGA ( R1.H , 0x2222 ); + DBGA ( R2.H , 0x3333 ); + DBGA ( R3.H , 0x4444 ); + DBGA ( R4.H , 0x5555 ); + DBGA ( R5.H , 0x6666 ); + DBGA ( R6.H , 0x7777 ); + DBGA ( R7.H , 0x8888 ); + + loadsym P0, tab2; + + R0 = W [ P0 ++ ] (Z); + DBGA ( R0.L , 0x1111 ); + + R1 = W [ P0 ++ ] (Z); + DBGA ( R1.L , 0x8888 ); + + R2 = W [ P0 ++ ] (Z); + DBGA ( R2.L , 0x2222 ); + + R3 = W [ P0 ++ ] (Z); + DBGA ( R3.L , 0x7777 ); + + R4 = W [ P0 ++ ] (Z); + DBGA ( R4.L , 0x3333 ); + + R5 = W [ P0 ++ ] (Z); + DBGA ( R5.L , 0x6666 ); + + R0 = B [ P0 ++ ] (Z); + DBGA ( R0.L , 0x44 ); + R1 = B [ P0 ++ ] (Z); + DBGA ( R1.L , 0x44 ); + R2 = B [ P0 ++ ] (Z); + DBGA ( R2.L , 0x55 ); + R3 = B [ P0 ++ ] (Z); + DBGA ( R3.L , 0x55 ); + + R0 = B [ P0 ++ ] (X); + DBGA ( R0.L , 0x55 ); + + R1 = B [ P0 ++ ] (X); + DBGA ( R1.L , 0x55 ); + + R0 = W [ P0 ++ ] (X); + DBGA ( R0.L , 0x4444 ); + + R1 = [ P0 ++ ]; + DBGA ( R1.L , 0x6666 ); + DBGA ( R1.H , 0x3333 ); + + P1 = [ P0 ++ ]; + R0 = P1; + DBGA ( R0.L , 0x7777 ); + DBGA ( R0.H , 0x2222 ); + + P1 = [ P0 ++ ]; + R0 = P1; + DBGA ( R0.L , 0x8888 ); + DBGA ( R0.H , 0x1111 ); + + loadsym P5, tab3; + + R0 = B [ P5 ++ ] (X); + DBGA ( R0.H , 0 ); + DBGA ( R0.L , 0 ); + + R0 = B [ P5 ++ ] (X); + DBGA ( R0.H , 0xffff ); + DBGA ( R0.L , 0xffff ); + + R1 = W [ P5 ++ ] (X); + DBGA ( R1.H , 0xffff ); + DBGA ( R1.L , 0xffff ); + + pass + + .data +tab: + .dw 0 + .dw 0x1111 + .dw 0 + .dw 0x2222 + .dw 0 + .dw 0x3333 + .dw 0 + .dw 0x4444 + .dw 0 + .dw 0x5555 + .dw 0 + .dw 0x6666 + .dw 0 + .dw 0x7777 + .dw 0 + .dw 0x8888 + .dw 0 + .dw 0 + .dw 0 + .dw 0 + +tab2: + .dw 0x1111 + .dw 0x8888 + .dw 0x2222 + .dw 0x7777 + .dw 0x3333 + .dw 0x6666 + .dw 0x4444 + .dw 0x5555 + .dw 0x5555 + .dw 0x4444 + .dw 0x6666 + .dw 0x3333 + .dw 0x7777 + .dw 0x2222 + .dw 0x8888 + .dw 0x1111 + +tab3: + .dw 0xff00 + .dw 0xffff diff --git a/sim/testsuite/bfin/l0shift.s b/sim/testsuite/bfin/l0shift.s new file mode 100644 index 0000000..3f5dc2c --- /dev/null +++ b/sim/testsuite/bfin/l0shift.s @@ -0,0 +1,13 @@ +# mach: bfin + +.include "testutils.inc" + start + + + r5 = 0; + r2.L = 0xadbd; + r2.h = 0xfedc; + r5 = r2 >> 0; + dbga (r5.l, 0xadbd); + dbga (r5.h, 0xfedc); + pass diff --git a/sim/testsuite/bfin/l2_loop.s b/sim/testsuite/bfin/l2_loop.s new file mode 100644 index 0000000..a6cde54 --- /dev/null +++ b/sim/testsuite/bfin/l2_loop.s @@ -0,0 +1,28 @@ +# mach: bfin + +.include "testutils.inc" + start + + p0=10; + loadsym i0, foo; + + R2 = i0; + r0.l = 0x5678; + r0.h = 0x1234; + + lsetup(lstart, lend) lc0=p0; + +lstart: + [i0++] = r0; +lend: + [i0++] = r0; + + r0=i0; + R0 = R0 - R2; + dbga(r0.l, 0x0050); + + pass + + .data +foo: + .space (0x100) diff --git a/sim/testsuite/bfin/link-2.s b/sim/testsuite/bfin/link-2.s new file mode 100644 index 0000000..ac711c6 --- /dev/null +++ b/sim/testsuite/bfin/link-2.s @@ -0,0 +1,24 @@ +# Blackfin testcase for link/unlink instructions +# mach: bfin + + .include "testutils.inc" + + start + + /* Make sure size arg to LINK works */ + R0 = SP; + LINK 0x20; + R1 = SP; + R1 += 0x8 + 0x20; + CC = R1 == R0; + IF !CC JUMP 1f; + + /* Make sure UNLINK restores old SP */ + UNLINK + R1 = SP; + CC = R1 == R0; + IF !CC JUMP 1f; + + pass +1: + fail diff --git a/sim/testsuite/bfin/link.s b/sim/testsuite/bfin/link.s new file mode 100644 index 0000000..c92ae1b --- /dev/null +++ b/sim/testsuite/bfin/link.s @@ -0,0 +1,67 @@ +# Blackfin testcase for link/unlink instructions +# mach: bfin + + .include "testutils.inc" + + start + + /* give FP/RETS known/different values */ + R7.H = 0xdead; + R7.L = 0x1234; + RETS = R7; + R6 = R7; + R6 += 0x23; + FP = R6; + + /* SP should have moved by -8 bytes (to push FP/RETS) */ + R0 = SP; + LINK 0; + R1 = SP; + R1 += 8; + CC = R0 == R1; + IF !CC JUMP 1f; + + /* FP should now have the same value as SP */ + R1 = SP; + R2 = FP; + CC = R1 == R2; + IF !CC JUMP 1f; + + /* make sure FP/RETS on the stack have our known values */ + R1 = [SP]; + CC = R1 == R6; + IF !CC JUMP 1f; + + R1 = [SP + 4]; + CC = R1 == R7; + IF !CC JUMP 1f; + + /* UNLINK should: + * assign SP to current FP + * adjust SP by -8 bytes + * restore RETS/FP from the stack + */ + R4 = 0; + RETS = R4; + R0 = SP; + UNLINK; + + /* Check new SP */ + R1 = SP; + R1 += -0x8; + CC = R1 == R0; + IF !CC JUMP 1f; + + /* Check restored RETS */ + R1 = RETS; + CC = R1 == R7; + IF !CC JUMP 1f; + + /* Check restored FP */ + R1 = FP; + CC = R1 == R6; + IF !CC JUMP 1f; + + pass +1: + fail diff --git a/sim/testsuite/bfin/lmu_cplb_multiple0.S b/sim/testsuite/bfin/lmu_cplb_multiple0.S new file mode 100644 index 0000000..9399c43 --- /dev/null +++ b/sim/testsuite/bfin/lmu_cplb_multiple0.S @@ -0,0 +1,2678 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple0/lmu_cplb_multiple0.dsp +// Description: Multiple CPLB Hit exceptions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +//------------------------------------- + +// Test LMU/CPLB exceptions + +// Basic outline: +// Set exception handler +// program CPLB Entries +// Enable CPLB in DMEM_CNTL +// perform access +// verify exception occurred + +CHECK_INIT(p5, 0xEFFFFFFC); + +//------------------------- +// Zero the CPLB Address and Data regs. + + LD32(p0, DCPLB_ADDR0); + R0 = 0; + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + LD32(p0, DCPLB_DATA0); + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + // Now set the CPLB entries we will need + + + + + // Data area for the desired error + WR_MMR(DCPLB_ADDR0, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR1, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR2, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR3, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR4, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR5, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR6, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR7, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR8, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR9, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR10, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR11, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR12, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR13, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR14, 0x10000000, p0, r0); + + // MMR space + WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); + WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + WR_MMR_LABEL(EVT15, int_15, p0, r1); + WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); + WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); + CSYNC; + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + + // But first raise interrupt 15 so we can do one test + // in supervisor mode. + RAISE 15; + NOP; + + RTI; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + +handler: + // generic protection exception handler + // Inputs: + // p2: addr of CPLB entry to be modified ( current test) + // + // Outputs: + // r4: SEQSTAT + // r5: DCPLB_FAULT_ADDR + // r6: DCPLB_STATUS + // r7: RETX (instruction addr where exception occurred) + + + R4 = SEQSTAT; // Get exception cause + R4 <<= 24; // Clear HWERRCAUSE + SFTRESET + R4 >>= 24; + + // read data addr which caused exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r5); + + RD_MMR(DCPLB_STATUS, p0, r6); + + R7 = RETX; // get address of excepting instruction + + // disable the offending CPLB entries + R2 = 0; + [ P2 ] = R2; + + CSYNC; + + // return from exception and re-execute offending instruction + RTX; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +int_15: + // Interrupt 15 handler - test will run in supervisor mode + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x41C6 (Z); + LD32(p2, DCPLB_DATA1); + +X0_1: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB1)); + CHECKREG_SYM(r7, X0_1, r0); // RETX should be value of X0_1 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x167E (Z); + LD32(p2, DCPLB_DATA2); + +X0_2: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB2)); + CHECKREG_SYM(r7, X0_2, r0); // RETX should be value of X0_2 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2781 (Z); + LD32(p2, DCPLB_DATA3); + +X0_3: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB3)); + CHECKREG_SYM(r7, X0_3, r0); // RETX should be value of X0_3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x446B (Z); + LD32(p2, DCPLB_DATA4); + +X0_4: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB4)); + CHECKREG_SYM(r7, X0_4, r0); // RETX should be value of X0_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x794B (Z); + LD32(p2, DCPLB_DATA5); + +X0_5: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB5)); + CHECKREG_SYM(r7, X0_5, r0); // RETX should be value of X0_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x15FB (Z); + LD32(p2, DCPLB_DATA6); + +X0_6: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB6)); + CHECKREG_SYM(r7, X0_6, r0); // RETX should be value of X0_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x59E2 (Z); + LD32(p2, DCPLB_DATA7); + +X0_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB7)); + CHECKREG_SYM(r7, X0_7, r0); // RETX should be value of X0_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1CFB (Z); + LD32(p2, DCPLB_DATA8); + +X0_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB8)); + CHECKREG_SYM(r7, X0_8, r0); // RETX should be value of X0_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3F54 (Z); + LD32(p2, DCPLB_DATA9); + +X0_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB9)); + CHECKREG_SYM(r7, X0_9, r0); // RETX should be value of X0_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0FF6 (Z); + LD32(p2, DCPLB_DATA10); + +X0_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB10)); + CHECKREG_SYM(r7, X0_10, r0); // RETX should be value of X0_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0ABD (Z); + LD32(p2, DCPLB_DATA11); + +X0_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB11)); + CHECKREG_SYM(r7, X0_11, r0); // RETX should be value of X0_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x31DF (Z); + LD32(p2, DCPLB_DATA12); + +X0_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB12)); + CHECKREG_SYM(r7, X0_12, r0); // RETX should be value of X0_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x237C (Z); + LD32(p2, DCPLB_DATA13); + +X0_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB13)); + CHECKREG_SYM(r7, X0_13, r0); // RETX should be value of X0_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2F1C (Z); + LD32(p2, DCPLB_DATA14); + +X0_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB14)); + CHECKREG_SYM(r7, X0_14, r0); // RETX should be value of X0_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7DE1 (Z); + LD32(p2, DCPLB_DATA2); + +X1_2: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB2)); + CHECKREG_SYM(r7, X1_2, r0); // RETX should be value of X1_2 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4487 (Z); + LD32(p2, DCPLB_DATA3); + +X1_3: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB3)); + CHECKREG_SYM(r7, X1_3, r0); // RETX should be value of X1_3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6201 (Z); + LD32(p2, DCPLB_DATA4); + +X1_4: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB4)); + CHECKREG_SYM(r7, X1_4, r0); // RETX should be value of X1_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x52BF (Z); + LD32(p2, DCPLB_DATA5); + +X1_5: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB5)); + CHECKREG_SYM(r7, X1_5, r0); // RETX should be value of X1_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6231 (Z); + LD32(p2, DCPLB_DATA6); + +X1_6: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB6)); + CHECKREG_SYM(r7, X1_6, r0); // RETX should be value of X1_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x63DE (Z); + LD32(p2, DCPLB_DATA7); + +X1_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB7)); + CHECKREG_SYM(r7, X1_7, r0); // RETX should be value of X1_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6956 (Z); + LD32(p2, DCPLB_DATA8); + +X1_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB8)); + CHECKREG_SYM(r7, X1_8, r0); // RETX should be value of X1_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1372 (Z); + LD32(p2, DCPLB_DATA9); + +X1_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB9)); + CHECKREG_SYM(r7, X1_9, r0); // RETX should be value of X1_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x500F (Z); + LD32(p2, DCPLB_DATA10); + +X1_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB10)); + CHECKREG_SYM(r7, X1_10, r0); // RETX should be value of X1_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2847 (Z); + LD32(p2, DCPLB_DATA11); + +X1_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB11)); + CHECKREG_SYM(r7, X1_11, r0); // RETX should be value of X1_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2C67 (Z); + LD32(p2, DCPLB_DATA12); + +X1_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB12)); + CHECKREG_SYM(r7, X1_12, r0); // RETX should be value of X1_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7566 (Z); + LD32(p2, DCPLB_DATA13); + +X1_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB13)); + CHECKREG_SYM(r7, X1_13, r0); // RETX should be value of X1_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4287 (Z); + LD32(p2, DCPLB_DATA14); + +X1_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB14)); + CHECKREG_SYM(r7, X1_14, r0); // RETX should be value of X1_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3359 (Z); + LD32(p2, DCPLB_DATA3); + +X2_3: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB3)); + CHECKREG_SYM(r7, X2_3, r0); // RETX should be value of X2_3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4DAA (Z); + LD32(p2, DCPLB_DATA4); + +X2_4: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB4)); + CHECKREG_SYM(r7, X2_4, r0); // RETX should be value of X2_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6488 (Z); + LD32(p2, DCPLB_DATA5); + +X2_5: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB5)); + CHECKREG_SYM(r7, X2_5, r0); // RETX should be value of X2_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x773C (Z); + LD32(p2, DCPLB_DATA6); + +X2_6: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB6)); + CHECKREG_SYM(r7, X2_6, r0); // RETX should be value of X2_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6F59 (Z); + LD32(p2, DCPLB_DATA7); + +X2_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB7)); + CHECKREG_SYM(r7, X2_7, r0); // RETX should be value of X2_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6EEA (Z); + LD32(p2, DCPLB_DATA8); + +X2_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB8)); + CHECKREG_SYM(r7, X2_8, r0); // RETX should be value of X2_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5656 (Z); + LD32(p2, DCPLB_DATA9); + +X2_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB9)); + CHECKREG_SYM(r7, X2_9, r0); // RETX should be value of X2_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6113 (Z); + LD32(p2, DCPLB_DATA10); + +X2_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB10)); + CHECKREG_SYM(r7, X2_10, r0); // RETX should be value of X2_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4A7B (Z); + LD32(p2, DCPLB_DATA11); + +X2_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB11)); + CHECKREG_SYM(r7, X2_11, r0); // RETX should be value of X2_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x31D2 (Z); + LD32(p2, DCPLB_DATA12); + +X2_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB12)); + CHECKREG_SYM(r7, X2_12, r0); // RETX should be value of X2_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2D85 (Z); + LD32(p2, DCPLB_DATA13); + +X2_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB13)); + CHECKREG_SYM(r7, X2_13, r0); // RETX should be value of X2_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x19A1 (Z); + LD32(p2, DCPLB_DATA14); + +X2_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB14)); + CHECKREG_SYM(r7, X2_14, r0); // RETX should be value of X2_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x69D8 (Z); + LD32(p2, DCPLB_DATA4); + +X3_4: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB4)); + CHECKREG_SYM(r7, X3_4, r0); // RETX should be value of X3_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x353C (Z); + LD32(p2, DCPLB_DATA5); + +X3_5: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB5)); + CHECKREG_SYM(r7, X3_5, r0); // RETX should be value of X3_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3B54 (Z); + LD32(p2, DCPLB_DATA6); + +X3_6: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB6)); + CHECKREG_SYM(r7, X3_6, r0); // RETX should be value of X3_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7D55 (Z); + LD32(p2, DCPLB_DATA7); + +X3_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB7)); + CHECKREG_SYM(r7, X3_7, r0); // RETX should be value of X3_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x102F (Z); + LD32(p2, DCPLB_DATA8); + +X3_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB8)); + CHECKREG_SYM(r7, X3_8, r0); // RETX should be value of X3_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1B37 (Z); + LD32(p2, DCPLB_DATA9); + +X3_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB9)); + CHECKREG_SYM(r7, X3_9, r0); // RETX should be value of X3_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7AAE (Z); + LD32(p2, DCPLB_DATA10); + +X3_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB10)); + CHECKREG_SYM(r7, X3_10, r0); // RETX should be value of X3_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5E65 (Z); + LD32(p2, DCPLB_DATA11); + +X3_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB11)); + CHECKREG_SYM(r7, X3_11, r0); // RETX should be value of X3_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x345B (Z); + LD32(p2, DCPLB_DATA12); + +X3_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB12)); + CHECKREG_SYM(r7, X3_12, r0); // RETX should be value of X3_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x63DA (Z); + LD32(p2, DCPLB_DATA13); + +X3_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB13)); + CHECKREG_SYM(r7, X3_13, r0); // RETX should be value of X3_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6102 (Z); + LD32(p2, DCPLB_DATA14); + +X3_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB14)); + CHECKREG_SYM(r7, X3_14, r0); // RETX should be value of X3_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7A79 (Z); + LD32(p2, DCPLB_DATA5); + +X4_5: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB5)); + CHECKREG_SYM(r7, X4_5, r0); // RETX should be value of X4_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0398 (Z); + LD32(p2, DCPLB_DATA6); + +X4_6: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB6)); + CHECKREG_SYM(r7, X4_6, r0); // RETX should be value of X4_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x28CC (Z); + LD32(p2, DCPLB_DATA7); + +X4_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB7)); + CHECKREG_SYM(r7, X4_7, r0); // RETX should be value of X4_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x60E3 (Z); + LD32(p2, DCPLB_DATA8); + +X4_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB8)); + CHECKREG_SYM(r7, X4_8, r0); // RETX should be value of X4_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1F1A (Z); + LD32(p2, DCPLB_DATA9); + +X4_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB9)); + CHECKREG_SYM(r7, X4_9, r0); // RETX should be value of X4_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4B76 (Z); + LD32(p2, DCPLB_DATA10); + +X4_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB10)); + CHECKREG_SYM(r7, X4_10, r0); // RETX should be value of X4_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x058E (Z); + LD32(p2, DCPLB_DATA11); + +X4_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB11)); + CHECKREG_SYM(r7, X4_11, r0); // RETX should be value of X4_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7A5F (Z); + LD32(p2, DCPLB_DATA12); + +X4_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB12)); + CHECKREG_SYM(r7, X4_12, r0); // RETX should be value of X4_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x28D9 (Z); + LD32(p2, DCPLB_DATA13); + +X4_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB13)); + CHECKREG_SYM(r7, X4_13, r0); // RETX should be value of X4_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0799 (Z); + LD32(p2, DCPLB_DATA14); + +X4_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB14)); + CHECKREG_SYM(r7, X4_14, r0); // RETX should be value of X4_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x388F (Z); + LD32(p2, DCPLB_DATA6); + +X5_6: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB6)); + CHECKREG_SYM(r7, X5_6, r0); // RETX should be value of X5_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x751F (Z); + LD32(p2, DCPLB_DATA7); + +X5_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB7)); + CHECKREG_SYM(r7, X5_7, r0); // RETX should be value of X5_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x493F (Z); + LD32(p2, DCPLB_DATA8); + +X5_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB8)); + CHECKREG_SYM(r7, X5_8, r0); // RETX should be value of X5_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0F36 (Z); + LD32(p2, DCPLB_DATA9); + +X5_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB9)); + CHECKREG_SYM(r7, X5_9, r0); // RETX should be value of X5_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x48EE (Z); + LD32(p2, DCPLB_DATA10); + +X5_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB10)); + CHECKREG_SYM(r7, X5_10, r0); // RETX should be value of X5_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2043 (Z); + LD32(p2, DCPLB_DATA11); + +X5_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB11)); + CHECKREG_SYM(r7, X5_11, r0); // RETX should be value of X5_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3F78 (Z); + LD32(p2, DCPLB_DATA12); + +X5_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB12)); + CHECKREG_SYM(r7, X5_12, r0); // RETX should be value of X5_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1E4D (Z); + LD32(p2, DCPLB_DATA13); + +X5_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB13)); + CHECKREG_SYM(r7, X5_13, r0); // RETX should be value of X5_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3D0D (Z); + LD32(p2, DCPLB_DATA14); + +X5_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB14)); + CHECKREG_SYM(r7, X5_14, r0); // RETX should be value of X5_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x33FA (Z); + LD32(p2, DCPLB_DATA7); + +X6_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB7)); + CHECKREG_SYM(r7, X6_7, r0); // RETX should be value of X6_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6FBE (Z); + LD32(p2, DCPLB_DATA8); + +X6_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB8)); + CHECKREG_SYM(r7, X6_8, r0); // RETX should be value of X6_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x36A6 (Z); + LD32(p2, DCPLB_DATA9); + +X6_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB9)); + CHECKREG_SYM(r7, X6_9, r0); // RETX should be value of X6_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2DDA (Z); + LD32(p2, DCPLB_DATA10); + +X6_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB10)); + CHECKREG_SYM(r7, X6_10, r0); // RETX should be value of X6_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x30E4 (Z); + LD32(p2, DCPLB_DATA11); + +X6_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB11)); + CHECKREG_SYM(r7, X6_11, r0); // RETX should be value of X6_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0586 (Z); + LD32(p2, DCPLB_DATA12); + +X6_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB12)); + CHECKREG_SYM(r7, X6_12, r0); // RETX should be value of X6_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x148E (Z); + LD32(p2, DCPLB_DATA13); + +X6_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB13)); + CHECKREG_SYM(r7, X6_13, r0); // RETX should be value of X6_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x42DC (Z); + LD32(p2, DCPLB_DATA14); + +X6_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB14)); + CHECKREG_SYM(r7, X6_14, r0); // RETX should be value of X6_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5929 (Z); + LD32(p2, DCPLB_DATA8); + +X7_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB8)); + CHECKREG_SYM(r7, X7_8, r0); // RETX should be value of X7_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0C6D (Z); + LD32(p2, DCPLB_DATA9); + +X7_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB9)); + CHECKREG_SYM(r7, X7_9, r0); // RETX should be value of X7_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x334E (Z); + LD32(p2, DCPLB_DATA10); + +X7_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB10)); + CHECKREG_SYM(r7, X7_10, r0); // RETX should be value of X7_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x62FF (Z); + LD32(p2, DCPLB_DATA11); + +X7_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB11)); + CHECKREG_SYM(r7, X7_11, r0); // RETX should be value of X7_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1F56 (Z); + LD32(p2, DCPLB_DATA12); + +X7_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB12)); + CHECKREG_SYM(r7, X7_12, r0); // RETX should be value of X7_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2BE1 (Z); + LD32(p2, DCPLB_DATA13); + +X7_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB13)); + CHECKREG_SYM(r7, X7_13, r0); // RETX should be value of X7_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1D70 (Z); + LD32(p2, DCPLB_DATA14); + +X7_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB14)); + CHECKREG_SYM(r7, X7_14, r0); // RETX should be value of X7_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2620 (Z); + LD32(p2, DCPLB_DATA9); + +X8_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB9)); + CHECKREG_SYM(r7, X8_9, r0); // RETX should be value of X8_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x26FB (Z); + LD32(p2, DCPLB_DATA10); + +X8_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB10)); + CHECKREG_SYM(r7, X8_10, r0); // RETX should be value of X8_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x718F (Z); + LD32(p2, DCPLB_DATA11); + +X8_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB11)); + CHECKREG_SYM(r7, X8_11, r0); // RETX should be value of X8_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x04B1 (Z); + LD32(p2, DCPLB_DATA12); + +X8_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB12)); + CHECKREG_SYM(r7, X8_12, r0); // RETX should be value of X8_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5358 (Z); + LD32(p2, DCPLB_DATA13); + +X8_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB13)); + CHECKREG_SYM(r7, X8_13, r0); // RETX should be value of X8_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3305 (Z); + LD32(p2, DCPLB_DATA14); + +X8_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB14)); + CHECKREG_SYM(r7, X8_14, r0); // RETX should be value of X8_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5690 (Z); + LD32(p2, DCPLB_DATA10); + +X9_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB10)); + CHECKREG_SYM(r7, X9_10, r0); // RETX should be value of X9_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5DC5 (Z); + LD32(p2, DCPLB_DATA11); + +X9_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB11)); + CHECKREG_SYM(r7, X9_11, r0); // RETX should be value of X9_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7809 (Z); + LD32(p2, DCPLB_DATA12); + +X9_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB12)); + CHECKREG_SYM(r7, X9_12, r0); // RETX should be value of X9_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1DDC (Z); + LD32(p2, DCPLB_DATA13); + +X9_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB13)); + CHECKREG_SYM(r7, X9_13, r0); // RETX should be value of X9_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6B53 (Z); + LD32(p2, DCPLB_DATA14); + +X9_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB14)); + CHECKREG_SYM(r7, X9_14, r0); // RETX should be value of X9_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7BCD (Z); + LD32(p2, DCPLB_DATA11); + +X10_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB11)); + CHECKREG_SYM(r7, X10_11, r0); // RETX should be value of X10_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x63AA (Z); + LD32(p2, DCPLB_DATA12); + +X10_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB12)); + CHECKREG_SYM(r7, X10_12, r0); // RETX should be value of X10_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x373B (Z); + LD32(p2, DCPLB_DATA13); + +X10_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB13)); + CHECKREG_SYM(r7, X10_13, r0); // RETX should be value of X10_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5648 (Z); + LD32(p2, DCPLB_DATA14); + +X10_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB14)); + CHECKREG_SYM(r7, X10_14, r0); // RETX should be value of X10_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6799 (Z); + LD32(p2, DCPLB_DATA12); + +X11_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA11, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB12)); + CHECKREG_SYM(r7, X11_12, r0); // RETX should be value of X11_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1452 (Z); + LD32(p2, DCPLB_DATA13); + +X11_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA11, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB13)); + CHECKREG_SYM(r7, X11_13, r0); // RETX should be value of X11_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x23D3 (Z); + LD32(p2, DCPLB_DATA14); + +X11_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA11, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB14)); + CHECKREG_SYM(r7, X11_14, r0); // RETX should be value of X11_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1152 (Z); + LD32(p2, DCPLB_DATA13); + +X12_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA12, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB13)); + CHECKREG_SYM(r7, X12_13, r0); // RETX should be value of X12_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6E9D (Z); + LD32(p2, DCPLB_DATA14); + +X12_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA12, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB14)); + CHECKREG_SYM(r7, X12_14, r0); // RETX should be value of X12_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6006 (Z); + LD32(p2, DCPLB_DATA14); + +X13_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA13, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB13|FAULT_CPLB14)); + CHECKREG_SYM(r7, X13_14, r0); // RETX should be value of X13_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- +User: + NOP; + dbg_pass; diff --git a/sim/testsuite/bfin/lmu_cplb_multiple1.S b/sim/testsuite/bfin/lmu_cplb_multiple1.S new file mode 100644 index 0000000..cf8cdf4 --- /dev/null +++ b/sim/testsuite/bfin/lmu_cplb_multiple1.S @@ -0,0 +1,2680 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple1/lmu_cplb_multiple1.dsp +// Description: Multiple CPLB Hit exceptions (DAG1) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +//------------------------------------- + +// Test LMU/CPLB exceptions + +// Basic outline: +// Set exception handler +// program CPLB Entries +// Enable CPLB in DMEM_CNTL +// perform access +// verify exception occurred + +CHECK_INIT(p5, 0xEFFFFFFC); + +//------------------------- +// Zero the CPLB Address and Data regs. + + LD32(p0, DCPLB_ADDR0); + R0 = 0; + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + LD32(p0, DCPLB_DATA0); + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + // Now set the CPLB entries we will need + + + + + // Data area for the desired error + WR_MMR(DCPLB_ADDR0, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR1, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR2, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR3, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR4, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR5, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR6, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR7, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR8, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR9, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR10, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR11, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR12, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR13, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR14, 0x10000000, p0, r0); + + // MMR space + WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); + WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + WR_MMR_LABEL(EVT15, int_15, p0, r1); + WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); + WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); + CSYNC; + + A0 = 0; + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + + // But first raise interrupt 15 so we can do one test + // in supervisor mode. + RAISE 15; + NOP; + + RTI; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + +handler: + // generic protection exception handler + // Inputs: + // p2: addr of CPLB entry to be modified ( current test) + // + // Outputs: + // r4: SEQSTAT + // r5: DCPLB_FAULT_ADDR + // r6: DCPLB_STATUS + // r7: RETX (instruction addr where exception occurred) + + + R4 = SEQSTAT; // Get exception cause + R4 <<= 24; // Clear HWERRCAUSE + SFTRESET + R4 >>= 24; + + // read data addr which caused exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r5); + + RD_MMR(DCPLB_STATUS, p0, r6); + + R7 = RETX; // get address of excepting instruction + + // disable the offending CPLB entries + R2 = 0; + [ P2 ] = R2; + + CSYNC; + + // return from exception and re-execute offending instruction + RTX; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +int_15: + // Interrupt 15 handler - test will run in supervisor mode + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x41C6 (Z); + LD32(p2, DCPLB_DATA1); + +X0_1: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB1)); + CHECKREG_SYM(r7, X0_1, r0); // RETX should be value of X0_1 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x167E (Z); + LD32(p2, DCPLB_DATA2); + +X0_2: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB2)); + CHECKREG_SYM(r7, X0_2, r0); // RETX should be value of X0_2 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2781 (Z); + LD32(p2, DCPLB_DATA3); + +X0_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB3)); + CHECKREG_SYM(r7, X0_3, r0); // RETX should be value of X0_3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x446B (Z); + LD32(p2, DCPLB_DATA4); + +X0_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB4)); + CHECKREG_SYM(r7, X0_4, r0); // RETX should be value of X0_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x794B (Z); + LD32(p2, DCPLB_DATA5); + +X0_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB5)); + CHECKREG_SYM(r7, X0_5, r0); // RETX should be value of X0_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x15FB (Z); + LD32(p2, DCPLB_DATA6); + +X0_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB6)); + CHECKREG_SYM(r7, X0_6, r0); // RETX should be value of X0_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x59E2 (Z); + LD32(p2, DCPLB_DATA7); + +X0_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB7)); + CHECKREG_SYM(r7, X0_7, r0); // RETX should be value of X0_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1CFB (Z); + LD32(p2, DCPLB_DATA8); + +X0_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB8)); + CHECKREG_SYM(r7, X0_8, r0); // RETX should be value of X0_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3F54 (Z); + LD32(p2, DCPLB_DATA9); + +X0_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB9)); + CHECKREG_SYM(r7, X0_9, r0); // RETX should be value of X0_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0FF6 (Z); + LD32(p2, DCPLB_DATA10); + +X0_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB10)); + CHECKREG_SYM(r7, X0_10, r0); // RETX should be value of X0_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0ABD (Z); + LD32(p2, DCPLB_DATA11); + +X0_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB11)); + CHECKREG_SYM(r7, X0_11, r0); // RETX should be value of X0_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x31DF (Z); + LD32(p2, DCPLB_DATA12); + +X0_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB12)); + CHECKREG_SYM(r7, X0_12, r0); // RETX should be value of X0_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x237C (Z); + LD32(p2, DCPLB_DATA13); + +X0_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB13)); + CHECKREG_SYM(r7, X0_13, r0); // RETX should be value of X0_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2F1C (Z); + LD32(p2, DCPLB_DATA14); + +X0_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB14)); + CHECKREG_SYM(r7, X0_14, r0); // RETX should be value of X0_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7DE1 (Z); + LD32(p2, DCPLB_DATA2); + +X1_2: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB2)); + CHECKREG_SYM(r7, X1_2, r0); // RETX should be value of X1_2 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4487 (Z); + LD32(p2, DCPLB_DATA3); + +X1_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB3)); + CHECKREG_SYM(r7, X1_3, r0); // RETX should be value of X1_3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6201 (Z); + LD32(p2, DCPLB_DATA4); + +X1_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB4)); + CHECKREG_SYM(r7, X1_4, r0); // RETX should be value of X1_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x52BF (Z); + LD32(p2, DCPLB_DATA5); + +X1_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB5)); + CHECKREG_SYM(r7, X1_5, r0); // RETX should be value of X1_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6231 (Z); + LD32(p2, DCPLB_DATA6); + +X1_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB6)); + CHECKREG_SYM(r7, X1_6, r0); // RETX should be value of X1_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x63DE (Z); + LD32(p2, DCPLB_DATA7); + +X1_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB7)); + CHECKREG_SYM(r7, X1_7, r0); // RETX should be value of X1_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6956 (Z); + LD32(p2, DCPLB_DATA8); + +X1_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB8)); + CHECKREG_SYM(r7, X1_8, r0); // RETX should be value of X1_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1372 (Z); + LD32(p2, DCPLB_DATA9); + +X1_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB9)); + CHECKREG_SYM(r7, X1_9, r0); // RETX should be value of X1_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x500F (Z); + LD32(p2, DCPLB_DATA10); + +X1_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB10)); + CHECKREG_SYM(r7, X1_10, r0); // RETX should be value of X1_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2847 (Z); + LD32(p2, DCPLB_DATA11); + +X1_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB11)); + CHECKREG_SYM(r7, X1_11, r0); // RETX should be value of X1_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2C67 (Z); + LD32(p2, DCPLB_DATA12); + +X1_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB12)); + CHECKREG_SYM(r7, X1_12, r0); // RETX should be value of X1_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7566 (Z); + LD32(p2, DCPLB_DATA13); + +X1_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB13)); + CHECKREG_SYM(r7, X1_13, r0); // RETX should be value of X1_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4287 (Z); + LD32(p2, DCPLB_DATA14); + +X1_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB14)); + CHECKREG_SYM(r7, X1_14, r0); // RETX should be value of X1_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3359 (Z); + LD32(p2, DCPLB_DATA3); + +X2_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB3)); + CHECKREG_SYM(r7, X2_3, r0); // RETX should be value of X2_3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4DAA (Z); + LD32(p2, DCPLB_DATA4); + +X2_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB4)); + CHECKREG_SYM(r7, X2_4, r0); // RETX should be value of X2_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6488 (Z); + LD32(p2, DCPLB_DATA5); + +X2_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB5)); + CHECKREG_SYM(r7, X2_5, r0); // RETX should be value of X2_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x773C (Z); + LD32(p2, DCPLB_DATA6); + +X2_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB6)); + CHECKREG_SYM(r7, X2_6, r0); // RETX should be value of X2_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6F59 (Z); + LD32(p2, DCPLB_DATA7); + +X2_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB7)); + CHECKREG_SYM(r7, X2_7, r0); // RETX should be value of X2_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6EEA (Z); + LD32(p2, DCPLB_DATA8); + +X2_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB8)); + CHECKREG_SYM(r7, X2_8, r0); // RETX should be value of X2_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5656 (Z); + LD32(p2, DCPLB_DATA9); + +X2_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB9)); + CHECKREG_SYM(r7, X2_9, r0); // RETX should be value of X2_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6113 (Z); + LD32(p2, DCPLB_DATA10); + +X2_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB10)); + CHECKREG_SYM(r7, X2_10, r0); // RETX should be value of X2_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4A7B (Z); + LD32(p2, DCPLB_DATA11); + +X2_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB11)); + CHECKREG_SYM(r7, X2_11, r0); // RETX should be value of X2_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x31D2 (Z); + LD32(p2, DCPLB_DATA12); + +X2_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB12)); + CHECKREG_SYM(r7, X2_12, r0); // RETX should be value of X2_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2D85 (Z); + LD32(p2, DCPLB_DATA13); + +X2_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB13)); + CHECKREG_SYM(r7, X2_13, r0); // RETX should be value of X2_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x19A1 (Z); + LD32(p2, DCPLB_DATA14); + +X2_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB14)); + CHECKREG_SYM(r7, X2_14, r0); // RETX should be value of X2_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x69D8 (Z); + LD32(p2, DCPLB_DATA4); + +X3_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB4)); + CHECKREG_SYM(r7, X3_4, r0); // RETX should be value of X3_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x353C (Z); + LD32(p2, DCPLB_DATA5); + +X3_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB5)); + CHECKREG_SYM(r7, X3_5, r0); // RETX should be value of X3_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3B54 (Z); + LD32(p2, DCPLB_DATA6); + +X3_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB6)); + CHECKREG_SYM(r7, X3_6, r0); // RETX should be value of X3_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7D55 (Z); + LD32(p2, DCPLB_DATA7); + +X3_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB7)); + CHECKREG_SYM(r7, X3_7, r0); // RETX should be value of X3_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x102F (Z); + LD32(p2, DCPLB_DATA8); + +X3_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB8)); + CHECKREG_SYM(r7, X3_8, r0); // RETX should be value of X3_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1B37 (Z); + LD32(p2, DCPLB_DATA9); + +X3_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB9)); + CHECKREG_SYM(r7, X3_9, r0); // RETX should be value of X3_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7AAE (Z); + LD32(p2, DCPLB_DATA10); + +X3_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB10)); + CHECKREG_SYM(r7, X3_10, r0); // RETX should be value of X3_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5E65 (Z); + LD32(p2, DCPLB_DATA11); + +X3_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB11)); + CHECKREG_SYM(r7, X3_11, r0); // RETX should be value of X3_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x345B (Z); + LD32(p2, DCPLB_DATA12); + +X3_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB12)); + CHECKREG_SYM(r7, X3_12, r0); // RETX should be value of X3_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x63DA (Z); + LD32(p2, DCPLB_DATA13); + +X3_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB13)); + CHECKREG_SYM(r7, X3_13, r0); // RETX should be value of X3_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6102 (Z); + LD32(p2, DCPLB_DATA14); + +X3_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB14)); + CHECKREG_SYM(r7, X3_14, r0); // RETX should be value of X3_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7A79 (Z); + LD32(p2, DCPLB_DATA5); + +X4_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB5)); + CHECKREG_SYM(r7, X4_5, r0); // RETX should be value of X4_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0398 (Z); + LD32(p2, DCPLB_DATA6); + +X4_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB6)); + CHECKREG_SYM(r7, X4_6, r0); // RETX should be value of X4_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x28CC (Z); + LD32(p2, DCPLB_DATA7); + +X4_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB7)); + CHECKREG_SYM(r7, X4_7, r0); // RETX should be value of X4_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x60E3 (Z); + LD32(p2, DCPLB_DATA8); + +X4_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB8)); + CHECKREG_SYM(r7, X4_8, r0); // RETX should be value of X4_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1F1A (Z); + LD32(p2, DCPLB_DATA9); + +X4_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB9)); + CHECKREG_SYM(r7, X4_9, r0); // RETX should be value of X4_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4B76 (Z); + LD32(p2, DCPLB_DATA10); + +X4_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB10)); + CHECKREG_SYM(r7, X4_10, r0); // RETX should be value of X4_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x058E (Z); + LD32(p2, DCPLB_DATA11); + +X4_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB11)); + CHECKREG_SYM(r7, X4_11, r0); // RETX should be value of X4_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7A5F (Z); + LD32(p2, DCPLB_DATA12); + +X4_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB12)); + CHECKREG_SYM(r7, X4_12, r0); // RETX should be value of X4_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x28D9 (Z); + LD32(p2, DCPLB_DATA13); + +X4_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB13)); + CHECKREG_SYM(r7, X4_13, r0); // RETX should be value of X4_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0799 (Z); + LD32(p2, DCPLB_DATA14); + +X4_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB14)); + CHECKREG_SYM(r7, X4_14, r0); // RETX should be value of X4_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x388F (Z); + LD32(p2, DCPLB_DATA6); + +X5_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB6)); + CHECKREG_SYM(r7, X5_6, r0); // RETX should be value of X5_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x751F (Z); + LD32(p2, DCPLB_DATA7); + +X5_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB7)); + CHECKREG_SYM(r7, X5_7, r0); // RETX should be value of X5_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x493F (Z); + LD32(p2, DCPLB_DATA8); + +X5_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB8)); + CHECKREG_SYM(r7, X5_8, r0); // RETX should be value of X5_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0F36 (Z); + LD32(p2, DCPLB_DATA9); + +X5_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB9)); + CHECKREG_SYM(r7, X5_9, r0); // RETX should be value of X5_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x48EE (Z); + LD32(p2, DCPLB_DATA10); + +X5_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB10)); + CHECKREG_SYM(r7, X5_10, r0); // RETX should be value of X5_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2043 (Z); + LD32(p2, DCPLB_DATA11); + +X5_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB11)); + CHECKREG_SYM(r7, X5_11, r0); // RETX should be value of X5_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3F78 (Z); + LD32(p2, DCPLB_DATA12); + +X5_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB12)); + CHECKREG_SYM(r7, X5_12, r0); // RETX should be value of X5_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1E4D (Z); + LD32(p2, DCPLB_DATA13); + +X5_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB13)); + CHECKREG_SYM(r7, X5_13, r0); // RETX should be value of X5_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3D0D (Z); + LD32(p2, DCPLB_DATA14); + +X5_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB14)); + CHECKREG_SYM(r7, X5_14, r0); // RETX should be value of X5_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x33FA (Z); + LD32(p2, DCPLB_DATA7); + +X6_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB7)); + CHECKREG_SYM(r7, X6_7, r0); // RETX should be value of X6_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6FBE (Z); + LD32(p2, DCPLB_DATA8); + +X6_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB8)); + CHECKREG_SYM(r7, X6_8, r0); // RETX should be value of X6_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x36A6 (Z); + LD32(p2, DCPLB_DATA9); + +X6_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB9)); + CHECKREG_SYM(r7, X6_9, r0); // RETX should be value of X6_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2DDA (Z); + LD32(p2, DCPLB_DATA10); + +X6_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB10)); + CHECKREG_SYM(r7, X6_10, r0); // RETX should be value of X6_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x30E4 (Z); + LD32(p2, DCPLB_DATA11); + +X6_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB11)); + CHECKREG_SYM(r7, X6_11, r0); // RETX should be value of X6_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0586 (Z); + LD32(p2, DCPLB_DATA12); + +X6_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB12)); + CHECKREG_SYM(r7, X6_12, r0); // RETX should be value of X6_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x148E (Z); + LD32(p2, DCPLB_DATA13); + +X6_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB13)); + CHECKREG_SYM(r7, X6_13, r0); // RETX should be value of X6_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x42DC (Z); + LD32(p2, DCPLB_DATA14); + +X6_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB14)); + CHECKREG_SYM(r7, X6_14, r0); // RETX should be value of X6_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5929 (Z); + LD32(p2, DCPLB_DATA8); + +X7_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB8)); + CHECKREG_SYM(r7, X7_8, r0); // RETX should be value of X7_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0C6D (Z); + LD32(p2, DCPLB_DATA9); + +X7_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB9)); + CHECKREG_SYM(r7, X7_9, r0); // RETX should be value of X7_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x334E (Z); + LD32(p2, DCPLB_DATA10); + +X7_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB10)); + CHECKREG_SYM(r7, X7_10, r0); // RETX should be value of X7_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x62FF (Z); + LD32(p2, DCPLB_DATA11); + +X7_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB11)); + CHECKREG_SYM(r7, X7_11, r0); // RETX should be value of X7_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1F56 (Z); + LD32(p2, DCPLB_DATA12); + +X7_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB12)); + CHECKREG_SYM(r7, X7_12, r0); // RETX should be value of X7_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2BE1 (Z); + LD32(p2, DCPLB_DATA13); + +X7_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB13)); + CHECKREG_SYM(r7, X7_13, r0); // RETX should be value of X7_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1D70 (Z); + LD32(p2, DCPLB_DATA14); + +X7_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB14)); + CHECKREG_SYM(r7, X7_14, r0); // RETX should be value of X7_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2620 (Z); + LD32(p2, DCPLB_DATA9); + +X8_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB9)); + CHECKREG_SYM(r7, X8_9, r0); // RETX should be value of X8_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x26FB (Z); + LD32(p2, DCPLB_DATA10); + +X8_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB10)); + CHECKREG_SYM(r7, X8_10, r0); // RETX should be value of X8_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x718F (Z); + LD32(p2, DCPLB_DATA11); + +X8_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB11)); + CHECKREG_SYM(r7, X8_11, r0); // RETX should be value of X8_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x04B1 (Z); + LD32(p2, DCPLB_DATA12); + +X8_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB12)); + CHECKREG_SYM(r7, X8_12, r0); // RETX should be value of X8_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5358 (Z); + LD32(p2, DCPLB_DATA13); + +X8_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB13)); + CHECKREG_SYM(r7, X8_13, r0); // RETX should be value of X8_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3305 (Z); + LD32(p2, DCPLB_DATA14); + +X8_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB14)); + CHECKREG_SYM(r7, X8_14, r0); // RETX should be value of X8_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5690 (Z); + LD32(p2, DCPLB_DATA10); + +X9_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB10)); + CHECKREG_SYM(r7, X9_10, r0); // RETX should be value of X9_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5DC5 (Z); + LD32(p2, DCPLB_DATA11); + +X9_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB11)); + CHECKREG_SYM(r7, X9_11, r0); // RETX should be value of X9_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7809 (Z); + LD32(p2, DCPLB_DATA12); + +X9_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB12)); + CHECKREG_SYM(r7, X9_12, r0); // RETX should be value of X9_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1DDC (Z); + LD32(p2, DCPLB_DATA13); + +X9_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB13)); + CHECKREG_SYM(r7, X9_13, r0); // RETX should be value of X9_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6B53 (Z); + LD32(p2, DCPLB_DATA14); + +X9_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB14)); + CHECKREG_SYM(r7, X9_14, r0); // RETX should be value of X9_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7BCD (Z); + LD32(p2, DCPLB_DATA11); + +X10_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB11)); + CHECKREG_SYM(r7, X10_11, r0); // RETX should be value of X10_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x63AA (Z); + LD32(p2, DCPLB_DATA12); + +X10_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB12)); + CHECKREG_SYM(r7, X10_12, r0); // RETX should be value of X10_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x373B (Z); + LD32(p2, DCPLB_DATA13); + +X10_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB13)); + CHECKREG_SYM(r7, X10_13, r0); // RETX should be value of X10_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5648 (Z); + LD32(p2, DCPLB_DATA14); + +X10_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB14)); + CHECKREG_SYM(r7, X10_14, r0); // RETX should be value of X10_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6799 (Z); + LD32(p2, DCPLB_DATA12); + +X11_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA11, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB12)); + CHECKREG_SYM(r7, X11_12, r0); // RETX should be value of X11_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1452 (Z); + LD32(p2, DCPLB_DATA13); + +X11_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA11, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB13)); + CHECKREG_SYM(r7, X11_13, r0); // RETX should be value of X11_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x23D3 (Z); + LD32(p2, DCPLB_DATA14); + +X11_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA11, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB14)); + CHECKREG_SYM(r7, X11_14, r0); // RETX should be value of X11_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1152 (Z); + LD32(p2, DCPLB_DATA13); + +X12_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA12, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB13)); + CHECKREG_SYM(r7, X12_13, r0); // RETX should be value of X12_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6E9D (Z); + LD32(p2, DCPLB_DATA14); + +X12_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA12, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB14)); + CHECKREG_SYM(r7, X12_14, r0); // RETX should be value of X12_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6006 (Z); + LD32(p2, DCPLB_DATA14); + +X13_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA13, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB13|FAULT_CPLB14)); + CHECKREG_SYM(r7, X13_14, r0); // RETX should be value of X13_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- +User: + NOP; + dbg_pass; diff --git a/sim/testsuite/bfin/lmu_excpt_align.S b/sim/testsuite/bfin/lmu_excpt_align.S new file mode 100644 index 0000000..b978155 --- /dev/null +++ b/sim/testsuite/bfin/lmu_excpt_align.S @@ -0,0 +1,345 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_align/lmu_excpt_align.dsp +// Description: LMU data alignment exceptions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +CHECK_INIT(p5, 0xE0000000); + + // test address for DAG0 + // test address for DAG1 + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + + // Write fault addr MMR to known state + WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6); + + //nop;nop;nop;nop;nop; // in lieu of CSYNC + CSYNC; + + A0 = 0; + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + RTI; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +User: + NOP;NOP;NOP;NOP;NOP; + + //------------------------------------------------------- + // First do stores + //------------------------------------------------------- + // 16-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X01: W [ I1 ] = R1.L; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X02: [ I1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 2))); + LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X03: [ I1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 3))); + LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X04: [ I1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 16-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X05: A0 = 0 || NOP || W [ I1 ] = R1.L; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X05, r0); // RETX should be value of X05 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X06: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X06, r0); // RETX should be value of X06 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 2))); + LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X07: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X07, r0); // RETX should be value of X07 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 3))); + LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X08: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X08, r0); // RETX should be value of X08 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // Now repeat for Loads + //------------------------------------------------------- + // 16-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X11: R1.L = W [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X11, r0); // RETX should be value of X11 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X12: R1 = [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X12, r0); // RETX should be value of X12 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 2))); + LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X13: R1 = [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X13, r0); // RETX should be value of X13 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 3))); + LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X14: R1 = [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X14, r0); // RETX should be value of X14 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 16-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X15: A0 = 0 || NOP || R1.L = W [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X15, r0); // RETX should be value of X15 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X16, r0); // RETX should be value of X16 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 2))); + LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X17: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X17, r0); // RETX should be value of X17 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 3))); + LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X18: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X18, r0); // RETX should be value of X18 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + dbg_pass; + + +handler: + R5 = SEQSTAT; // Get exception cause + + // read and check fail addr (addr_which_causes_exception) + // should not be set for alignment exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r6); + + R7 = RETX; // get address of excepting instruction + + // align the offending address + I1 = P2; + + RTX; + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +.section MEM_0x1000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/bfin/lmu_excpt_default.S b/sim/testsuite/bfin/lmu_excpt_default.S new file mode 100644 index 0000000..9b8a14f --- /dev/null +++ b/sim/testsuite/bfin/lmu_excpt_default.S @@ -0,0 +1,307 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_default/lmu_excpt_default.dsp +// Description: Default protection checks (CPLB disabled) +// - MMR access in User mode +// - DAG1 Access MMRs (supv/user mode, read/write) +// - DAG1 Access Scratch SRAM (user or supervisor mode, read/write) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#define EXCPT_PROTVIOL 0x23 +#define OMODE_SUPV 0 // not used in the hardware + + + + CHECK_INIT(p5, 0xE0000000); + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + WR_MMR_LABEL(EVT15, Supv, p0, r1); + WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); + WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); + CSYNC; + + A0 = 0; + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + + // But first raise interrupt 15 so we can run in supervisor mode. + RAISE 15; + + RTI; + +Supv: + + //------------------------------------------------------- + // DAG1 MMR Write access + + + + LD32(i1, (DCPLB_ADDR0)); + LD32_LABEL(p2, Y01); // Exception handler will return to this address + LD32(r0, 0xdeadbeef); + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X01: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here +Y01: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS + CHECKREG_SYM(r7, X01, r0); // RETX X01: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG1 MMR Read access + + + + LD32(i1, (DCPLB_ADDR1)); + LD32_LABEL(p2, Y02); // Exception handler will return to this address + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X02: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here +Y02: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS + CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS + CHECKREG_SYM(r7, X02, r0); // RETX X02: (HARDCODED ADDR!!) + +#if 0 + //------------------------------------------------------- + // DAG1 Scratch SRAM Write access + + + + LD32(i1, (( 0xFF800000 + 0x300000))); + LD32_LABEL(p2, Y03); // Exception handler will return to this address + LD32(r1, 0xdeadbeef); + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X03: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here +Y03: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS + CHECKREG_SYM(r7, X03, r0); // RETX X03: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG1 Scratch SRAM Read access + + + + LD32(i1, ((( 0xFF800000 + 0x300000) + 4))); + LD32_LABEL(p2, Y04); // Exception handler will return to this address + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X04: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here +Y04: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS + CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS + CHECKREG_SYM(r7, X04, r0); // RETX X04: (HARDCODED ADDR!!) +#endif + + //------------------------------------------------------- + + // Now, go to User mode + LD32_LABEL(r0, User); + RETI = R0; + RTI; + + +User: + + //------------------------------------------------------- + // DAG0 MMR Write access (multi-issue) + + + + LD32(i1, (DCPLB_ADDR0)); + LD32_LABEL(p2, Y11); // Exception handler will return to this address + LD32(r0, 0xdeadbeef); + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X11: A0 = 0 || [ I1 ] = R1 || NOP; // Exception should occur here +Y11: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X11, r0); // RETX X11: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG0 MMR Read access (multi-issue) + + + + LD32(i1, (DCPLB_ADDR1)); + LD32_LABEL(p2, Y12); // Exception handler will return to this address + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X12: A0 = 0 || R1 = [ I1 ] || NOP; // Exception should occur here +Y12: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS + CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X12, r0); // RETX X12: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG1 MMR Write access + + + + LD32(i1, (DCPLB_ADDR0)); + LD32_LABEL(p2, Y13); // Exception handler will return to this address + LD32(r0, 0xdeadbeef); + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here +Y13: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X13, r0); // RETX X13: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG1 MMR Read access + + + + LD32(i1, (DCPLB_ADDR1)); + LD32_LABEL(p2, Y14); // Exception handler will return to this address + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X14: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here +Y14: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS + CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X14, r0); // RETX X14: (HARDCODED ADDR!!) + +#if 0 + //------------------------------------------------------- + // DAG1 Scratch SRAM Write access + + + + LD32(i1, (( 0xFF800000 + 0x300000))); + LD32_LABEL(p2, Y15); // Exception handler will return to this address + LD32(r1, 0xdeadbeef); + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X15: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here +Y15: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X15, r0); // RETX X15: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG1 Scratch SRAM Read access + + + + LD32(i1, ((( 0xFF800000 + 0x300000) + 4))); + LD32_LABEL(p2, Y16); // Exception handler will return to this address + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here +Y16: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS + CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X16, r0); // RETX X16: (HARDCODED ADDR!!) +#endif + + //------------------------------------------------------- + // DAG0 MMR Write access (single-issue) + + + + LD32(i1, (DCPLB_ADDR0)); + LD32_LABEL(p2, Y17); // Exception handler will return to this address + LD32(r0, 0xdeadbeef); + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X17: [ I1 ] = R1; // Exception should occur here +Y17: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X17, r0); // RETX X17: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG0 MMR Read access (single-issue) + + + + LD32(i1, (DCPLB_ADDR1)); + LD32_LABEL(p2, Y18); // Exception handler will return to this address + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X18: R1 = [ I1 ]; // Exception should occur here +Y18: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS + CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X18, r0); // RETX X18: (HARDCODED ADDR!!) + + //------------------------------------------------------- + dbg_pass; + + +handler: + R4 = SEQSTAT; // Get exception cause + + // read and check fail addr (addr_which_causes_exception) + // should not be set for alignment exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r5); + RD_MMR(DCPLB_STATUS, p0, r6); + R7 = RETX; // get address of excepting instruction + + RETX = P2; + + RTX; diff --git a/sim/testsuite/bfin/lmu_excpt_illaddr.S b/sim/testsuite/bfin/lmu_excpt_illaddr.S new file mode 100644 index 0000000..7c84b64 --- /dev/null +++ b/sim/testsuite/bfin/lmu_excpt_illaddr.S @@ -0,0 +1,337 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_illaddr/lmu_excpt_illaddr.dsp +// Description: LMU illegal address exceptions +// Illegal core MMR: addr[19:16] != 0 +// Illegal core MMR: Illegal peripheral +// Illegal core MMR: Illegal addr in peripheral +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#ifndef SR_BASE +#define SR_BASE 0xFF800000 // must match value used for sram_baddr inputs +#endif +#ifndef A_SRAM_BASE +#define A_SRAM_BASE SR_BASE +#endif +#ifndef B_SRAM_BASE +#define B_SRAM_BASE SR_BASE + 0x100000 +#endif +#ifndef I_SRAM_BASE +#define I_SRAM_BASE SR_BASE + 0x200000 +#endif +#ifndef SCRATCH_SRAM_BASE +#define SCRATCH_SRAM_BASE SR_BASE + 0x300000 +#endif + +#ifndef A_SRAM_SIZE +#define A_SRAM_SIZE 0x4000 +#endif +#ifndef B_SRAM_SIZE +#define B_SRAM_SIZE 0x4000 +#endif +#ifndef I_SRAM_SIZE +#define I_SRAM_SIZE 0x4000 +#endif +#ifndef SCRATCH_SRAM_SIZE +#define SCRATCH_SRAM_SIZE 0x1000 +#endif + +CHECK_INIT(p5, 0xE0000000); + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + WR_MMR_LABEL(EVT15, int15, p0, r1); + WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); + WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); + + // Set up CPLB + + WR_MMR(DCPLB_ADDR1, SR_BASE, p0, r0); // SRAM segment: Non-cacheable + WR_MMR(DCPLB_DATA1, ( CPLB_VALID | CPLB_L1SRAM | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0); + + WR_MMR(DCPLB_ADDR2, 0xE0000000, p0, r0); // CHECKREG segment: Non-cacheable + WR_MMR(DCPLB_DATA2, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0); + + WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); // MMRs: Non-cacheable + WR_MMR(DCPLB_DATA15, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0); + + WR_MMR(DMEM_CONTROL, (DMC_AB_SRAM | ENDCPLB | ENDM), p0, r0); + + CSYNC; + + // Write fault addr MMR to known state + WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6); + NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + + // But first raise interrupt 15 so we will run in supervisor mode. + RAISE 15; + NOP; + RTI; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + +int15: + NOP;NOP;NOP;NOP;NOP; + + //------------------------------------------------------- + // First do stores + //------------------------------------------------------- + // + + // illegal core MMR: addr[19] !=0 + + + LD32(p1, 0xFFE80000); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X01: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE80000); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: addr[18] !=0 + + + LD32(p1, 0xFFE40000); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X02: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE40000); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: addr[17] !=0 + + + LD32(p1, 0xFFE20000); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X03: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE20000); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: addr[16] !=0 + + + LD32(p1, 0xFFE10000); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X04: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE10000); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal periperal (addr[15:12] > 8) + + + LD32(p1, 0xFFE09000); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X10: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE09000); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X10, r0); // RETX should be value of X10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 00 + + + LD32(p1, 0xFFE00408); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X20: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE00408); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X20, r0); // RETX should be value of X20 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 01 + + + LD32(p1, 0xFFE01408); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X21: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE01408); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X21, r0); // RETX should be value of X21 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 02 + + + LD32(p1, 0xFFE02114); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X22: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE02114); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X22, r0); // RETX should be value of X22 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 03 + + + LD32(p1, 0xFFE03010); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X23: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE03010); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X23, r0); // RETX should be value of X23 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 04 + + + LD32(p1, 0xFFE04008); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X24: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE04008); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X24, r0); // RETX should be value of X24 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 05 + + + LD32(p1, 0xFFE05010); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X25: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE05010); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X25, r0); // RETX should be value of X25 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 06 + + + LD32(p1, 0xFFE06104); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X26: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE06104); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X26, r0); // RETX should be value of X26 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 07 + + + LD32(p1, 0xFFE07204); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X27: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE07204); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X27, r0); // RETX should be value of X27 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 08 + + + LD32(p1, 0xFFE08108); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X28: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE08108); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X28, r0); // RETX should be value of X28 (HARDCODED ADDR!!) + + //------------------------------------------------------- +User: + dbg_pass; + + + //------------------------------------------------------- +handler: + R5 = SEQSTAT; // Get exception cause + + // read and check fail addr (addr_which_causes_exception) + // should not be set for alignment exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r6); + + R7 = RETX; // get address of excepting instruction + + // align the offending address + P1 = P2; + + RTX; + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; diff --git a/sim/testsuite/bfin/lmu_excpt_prot0.S b/sim/testsuite/bfin/lmu_excpt_prot0.S new file mode 100644 index 0000000..279cc02 --- /dev/null +++ b/sim/testsuite/bfin/lmu_excpt_prot0.S @@ -0,0 +1,392 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot0/lmu_excpt_prot0.dsp +// Description: LMU protection exceptions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +//------------------------------------- + +// Test LMU/CPLB exceptions + +// Basic outline: +// Set exception handler +// program CPLB Entries +// Enable CPLB in DMEM_CNTL +// perform access +// verify exception occurred + +CHECK_INIT(p5, 0xEFFFFFFC); + +//------------------------- +// Zero the CPLB Address and Data regs. + + LD32(p0, DCPLB_ADDR0); + R0 = 0; + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + LD32(p0, DCPLB_DATA0); + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + // Now set the CPLB entries we will need + + + + + + + + + + + + + + + + + + + + + + + + + + // Data area for the desired error + WR_MMR(DCPLB_ADDR0, 0x800, p0, r0); + WR_MMR(DCPLB_ADDR1, 0x1000, p0, r0); + WR_MMR(DCPLB_DATA0, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW, p0, r0); + WR_MMR(DCPLB_ADDR2, 0x2000, p0, r0); + WR_MMR(DCPLB_ADDR3, 0x3000, p0, r0); + WR_MMR(DCPLB_ADDR4, 0x4000, p0, r0); + WR_MMR(DCPLB_ADDR5, 0x5000, p0, r0); + WR_MMR(DCPLB_ADDR6, 0x6000, p0, r0); + WR_MMR(DCPLB_ADDR7, 0x7000, p0, r0); + + // CHECKREG segment + WR_MMR(DCPLB_ADDR14, 0xEFFFFC00, p0, r0); + WR_MMR(DCPLB_DATA14, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_WT|CPLB_L1_CACHABLE|CPLB_SUPV_WR|CPLB_USER_RW, p0, r0); + + // MMR space + WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); + WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + WR_MMR_LABEL(EVT15, int_15, p0, r1); + WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); + WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); + + // enable CPLB + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + + // But first raise interrupt 15 so we can do one test + // in supervisor mode. + RAISE 15; + NOP; + + RTI; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +int_15: + // Interrupt 15 handler - needed to try supervisor access with exceptions enabled + //------------------------------------------------------- + // Protection violation - Illegal Supervisor Write Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(p1, 0x800); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA0); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA1); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); + + +X0: [ P1 ] = R1; // Exception should occur here + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x800); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0)); + CHECKREG_SYM(r7, X0, r0); // RETX should be value of X0 (HARDCODED ADDR!!) + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RTI; + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +User: + NOP;NOP;NOP;NOP;NOP; + + //------------------------------------------------------- + // Protection violation - Illegal User Write Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(p1, 0x1000); + LD32(r1, 0xDEADBEEF); + + + // values to fix up current test + LD32(p2, DCPLB_DATA1); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + // values for next test + LD32(p3, DCPLB_DATA2); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE); + +X1: [ P1 ] = R1; // Exception should occur here + + // Now check that handler read correct values + + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x1000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER | FAULT_CPLB1)); + CHECKREG_SYM(r7, X1, r0); // RETX should be value of X1 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // Protection violation - Illegal User Read Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(p1, 0x2000); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA2); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RO|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA3); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + +X2: //[p1] = r1; // Exception should occur here + R0 = [ P1 ]; + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x2000); + CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER | FAULT_CPLB2)); + CHECKREG_SYM(r7, X2, r0); // RETX should be value of X2 (HARDCODED ADDR!!) + + //------------------------------------------------------- + // Protection violation - Illegal Dirty Page Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(p1, 0x3000); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA3); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA4); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DA0ACC|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + +X3: [ P1 ] = R1; // Exception should occur here + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x3000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER | FAULT_CPLB3)); + CHECKREG_SYM(r7, X3, r0); // RETX should be value of X3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + // Protection violation - Illegal DAG1 Access + // Since this test uses DAG0, there shouldn't be any exception + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(p1, 0x4000); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA4); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA5); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + +X4: [ P1 ] = R1; // Exception should NOT occur here + + + // Now check that handler read correct values + // Handler shouldn't have been invoked, so registers should + // remain unchanged. + CHECKREG(r4,0); // supv and EXCPT_PROT + CHECKREG(r5, 0); + CHECKREG(r6, 0); + CHECKREG(r7, 0); // RETX should NOT be value of X4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + // L1Miss not implemented yet - skip for now.... + +// //------------------------------------------------------- +// // Protection violation - L1 Miss +// r0=0;r1=0;r2=0;r3=0;r4=0;r5=0;r6=0;r7=0; +// +// LD32(p1, 0x5000); +// LD32(r1, 0xDEADBEEF); +// +// LD32(p2, DCPLB_DATA5); +// LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); +// +// LD32(p3, DCPLB_DATA6); +// LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_USER_RW|CPLB_SUPV_WR); +// +// +//X5: //[p1] = r1; // Exception should occur here +// r0 = [p1]; +// +// +// // Now check that handler read correct values +// CHECKREG(r4,0x23); // supv and EXCPT_PROT +// CHECKREG(r5, 0x5000); +// // CHECKREG(r6, FAULT_DATA | FAULT_CPLB5); +// CHECKREG_SYM(r7, X5, r0); // RETX should be value of X5 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + dbg_pass; + + +handler: + // generic protection exception handler + // Inputs: + // p2: addr of CPLB entry to be modified ( current test) + // r2: new data for CPLB entry + // + // p3: addr of CPLB entry to be modified ( next test) + // r3: new data for CPLB entry + // + // Outputs: + // r4: SEQSTAT + // r5: DCPLB_FAULT_ADDR + // r6: DCPLB_STATUS + // r7: RETX (instruction addr where exception occurred) + + + R4 = SEQSTAT; // Get exception cause + + // read data addr which caused exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r5); + + RD_MMR(DCPLB_STATUS, p0, r6); + + R7 = RETX; // get address of excepting instruction + + + // modify CPLB to allow access. Main pgm passes in addr and data + [ P2 ] = R2; + + // Set up for next test + [ P3 ] = R3; + + NOP;NOP;NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC; + + // return from exception and re-execute offending instruction + RTX; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +.section MEM_0x800,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x1000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x2000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x3000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x4000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x5000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +// Need illegal SRAM addr to test CPLB_L1SRAM +//.data 0x6000 +// .dd 0x00000000 +// .dd 0x00000000 +// .dd 0x00000000 +// .dd 0x00000000 + +.section MEM_0x7000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/bfin/lmu_excpt_prot1.S b/sim/testsuite/bfin/lmu_excpt_prot1.S new file mode 100644 index 0000000..5ffa680 --- /dev/null +++ b/sim/testsuite/bfin/lmu_excpt_prot1.S @@ -0,0 +1,401 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot1/lmu_excpt_prot1.dsp +// Description: LMU protection exceptions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +//------------------------------------- + +// Test LMU/CPLB exceptions + +// Basic outline: +// Set exception handler +// program CPLB Entries +// Enable CPLB in DMEM_CNTL +// perform access +// verify exception occurred + +CHECK_INIT(p5, 0xEFFFFFFC); + + A0 = 0; + +//------------------------- +// Zero the CPLB Address and Data regs. + + LD32(p0, DCPLB_ADDR0); + R0 = 0; + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + LD32(p0, DCPLB_DATA0); + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + // Now set the CPLB entries we will need + + + + + + + + + + + + + + + + + + + + + + + + + + // Data area for the desired error + WR_MMR(DCPLB_ADDR0, 0x800, p0, r0); + WR_MMR(DCPLB_ADDR1, 0x1000, p0, r0); + WR_MMR(DCPLB_DATA0, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE, p0, r0); + WR_MMR(DCPLB_ADDR2, 0x2000, p0, r0); + WR_MMR(DCPLB_ADDR3, 0x3000, p0, r0); + WR_MMR(DCPLB_ADDR4, 0x4000, p0, r0); + WR_MMR(DCPLB_ADDR5, 0x5000, p0, r0); + WR_MMR(DCPLB_ADDR6, 0x6000, p0, r0); + WR_MMR(DCPLB_ADDR7, 0x7000, p0, r0); + + // CHECKREG segment + WR_MMR(DCPLB_ADDR14, 0xEFFFFC00, p0, r0); + WR_MMR(DCPLB_DATA14, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_WT|CPLB_L1_CACHABLE|CPLB_SUPV_WR|CPLB_USER_RW, p0, r0); + + // MMR space + WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); + WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + WR_MMR_LABEL(EVT15, int_15, p0, r1); + WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); + WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); + + // enable CPLB + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC + + // Address for slot 0 accesses + // LD32(p4, 0xEFFFFFF8); + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + + // But first raise interrupt 15 so we can do one test + // in supervisor mode. + RAISE 15; + NOP; + + RTI; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +int_15: + // Interrupt 15 handler - needed to try supervisor access with exceptions enabled + //------------------------------------------------------- + // Protection violation - Illegal Supervisor Write Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(i1, 0x800); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA0); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA1); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); + + +X0: //[p1] = r1; // Exception should occur here + A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1 + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x800); + CHECKREG(r6, (FAULT_SUPV|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB0)); + CHECKREG_SYM(r7, X0, r0); // RETX should be value of X0 (HARDCODED ADDR!!) + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RTI; + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +User: + NOP;NOP;NOP;NOP;NOP; + + //------------------------------------------------------- + // Protection violation - Illegal User Write Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(i1, 0x1000); + LD32(r1, 0xDEADBEEF); + + + // values to fix up current test + LD32(p2, DCPLB_DATA1); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + // values for next test + LD32(p3, DCPLB_DATA2); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE); + +X1: //[p1] = r1; // Exception should occur here + A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1 + + // Now check that handler read correct values + + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x1000); + CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB1)); + CHECKREG_SYM(r7, X1, r0); // RETX should be value of X1 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // Protection violation - Illegal User Read Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(i1, 0x2000); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA2); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RO|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA3); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + +X2: //[p1] = r1; // Exception should occur here + A0 = 0 || NOP || R0 = [ I1 ]; // test access with DAG1 + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x2000); + CHECKREG(r6, (FAULT_USER|FAULT_READ|FAULT_DAG1 | FAULT_CPLB2)); + CHECKREG_SYM(r7, X2, r0); // RETX should be value of X2 (HARDCODED ADDR!!) + + //------------------------------------------------------- + // Protection violation - Illegal Dirty Page Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(i1, 0x3000); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA3); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA4); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DA0ACC|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); + + +X3: //[p1] = r1; // Exception should occur here + A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1 + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x3000); + CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB3)); + CHECKREG_SYM(r7, X3, r0); // RETX should be value of X3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + // Protection violation - Illegal DAG1 Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(i1, 0x4000); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA4); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA5); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + +X4: //[p1] = r1; // Exception should occur here + A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1 + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x4000); + CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB4)); + CHECKREG_SYM(r7, X4, r0); // RETX should be value of X4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + // L1Miss not implemented yet - skip for now.... + +// //------------------------------------------------------- +// // Protection violation - L1 Miss +// r0=0;r1=0;r2=0;r3=0;r4=0;r5=0;r6=0;r7=0; +// +// LD32(p1, 0x6000); +// LD32(r1, 0xDEADBEEF); +// +// LD32(p2, DCPLB_DATA6); +// LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); +// +// LD32(p3, DCPLB_DATA7); +// LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_USER_RW|CPLB_SUPV_WR); +// +// +//X6: //[p1] = r1; // Exception should occur here +// r0 = [p1]; +// +// +// // Now check that handler read correct values +// CHECKREG(r4,0x23); // supv and EXCPT_PROT +// CHECKREG(r5, 0x6000); +// // CHECKREG(r6, FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB6); +// CHECKREG_SYM(r7, X6, r0); // RETX should be value of X6 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + dbg_pass; + + +handler: + // generic protection exception handler + // Inputs: + // p2: addr of CPLB entry to be modified ( current test) + // r2: new data for CPLB entry + // + // p3: addr of CPLB entry to be modified ( next test) + // r3: new data for CPLB entry + // + // Outputs: + // r4: SEQSTAT + // r5: DCPLB_FAULT_ADDR + // r6: DCPLB_STATUS + // r7: RETX (instruction addr where exception occurred) + + + R4 = SEQSTAT; // Get exception cause + + // read data addr which caused exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r5); + RD_MMR(DCPLB_STATUS, p0, r6); + + // Reset status regs + WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r0); + WR_MMR(DCPLB_STATUS, 0, p0, r0); + + R7 = RETX; // get address of excepting instruction + + + // modify CPLB to allow access. Main pgm passes in addr and data + [ P2 ] = R2; + + // Set up for next test + [ P3 ] = R3; + + NOP;NOP;NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC; + + // return from exception and re-execute offending instruction + RTX; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +.section MEM_0x800,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x1000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x2000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x3000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x4000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x5000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +// Need a cache miss to test CPLB_L1REF +//.data 0x6000 +// .dd 0x00000000 +// .dd 0x00000000 +// .dd 0x00000000 +// .dd 0x00000000 + +.section MEM_0x7000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/bfin/load.s b/sim/testsuite/bfin/load.s new file mode 100644 index 0000000..2fca3de --- /dev/null +++ b/sim/testsuite/bfin/load.s @@ -0,0 +1,239 @@ +# Blackfin testcase for register load instructions +# mach: bfin + + + .include "testutils.inc" + + start + + .macro load32 num:req, reg0:req, reg1:req + imm32 \reg0 \num + imm32 \reg1 \num + CC = \reg0 == \reg1 + if CC jump 2f; + fail +2: + .endm + + .macro load32p num:req preg:req + imm32 r0 \num + imm32 \preg \num + r1 = \preg + cc = r0 == r1 + if CC jump 3f; + fail +3: + imm32 \preg 0 + .endm + + .macro load16z num:req reg0:req reg1:req + \reg0 = \num (Z); + imm32 \reg1 \num + CC = \reg0 == \reg1 + if CC jump 4f; + fail +4: + .endm + + .macro load16zp num:req reg:req + \reg = \num (Z); + imm32 r1 \num; + r0 = \reg; + cc = r0 == r1 + if CC jump 5f; + fail +5: + .endm + + .macro load16x num:req reg0:req reg1:req + \reg0 = \num (X); + imm32 \reg1, \num + CC = \reg0 == \reg1 + if CC jump 6f; + fail +6: + .endm + + /* Clobbers R0 */ + .macro loadinc preg0:req, preg1:req, dreg:req + loadsym \preg0, _buf + \preg1 = \preg0; + \dreg = \preg0; + [\preg0\()++] = \preg0; + \dreg += 4; + R0 = \preg0; + CC = \dreg == R0; + if CC jump 7f; + fail +7: + R0 = [ \preg1\() ]; + \dreg += -4; + CC = \dreg == R0; + if CC jump 8f; + fail +8: + .endm + + /* test a bunch of values */ + + /* load_immediate (Half-Word Load) + * register = constant + * reg_lo = uimm16; + * reg_hi = uimm16; + */ + + load32 0 R0 R1 + load32 0xFFFFFFFF R0 R1 + load32 0x55aaaa55 r0 r1 + load32 0x12345678 r0 r1 + load32 0x12345678 R0 R2 + load32 0x23456789 R0 R3 + load32 0x3456789a R0 R4 + load32 0x456789ab R0 R5 + load32 0x56789abc R0 R6 + load32 0x6789abcd R0 R7 + load32 0x789abcde R0 R0 + load32 0x89abcdef R1 R0 + load32 0x9abcdef0 R2 R0 + load32 0xabcdef01 R3 R0 + load32 0xbcdef012 R4 R0 + load32 0xcdef0123 R5 R0 + load32 0xdef01234 R6 R0 + load32 0xef012345 R7 R0 + + load32p 0xf0123456 P0 + load32p 0x01234567 P1 + load32p 0x12345678 P2 +.ifndef BFIN_HOST + load32p 0x23456789 P3 +.endif + load32p 0x3456789a P4 + load32p 0x456789ab P5 + load32p 0x56789abc SP + load32p 0x6789abcd FP + + load32p 0x789abcde I0 + load32p 0x89abcdef I1 + load32p 0x9abcdef0 I2 + load32p 0xabcdef01 I3 + load32p 0xbcdef012 M0 + load32p 0xcdef0123 M1 + load32p 0xdef01234 M2 + load32p 0xef012345 M3 + + load32p 0xf0123456 B0 + load32p 0x01234567 B1 + load32p 0x12345678 B2 + load32p 0x23456789 B3 + load32p 0x3456789a L0 + load32p 0x456789ab L1 + load32p 0x56789abc L2 + load32p 0x6789abcd L3 + + /* Zero Extended */ + load16z 0x1234 R0 R1 + load16z 0x2345 R0 R1 + load16z 0x3456 R0 R2 + load16z 0x4567 R0 R3 + load16z 0x5678 R0 R4 + load16z 0x6789 R0 R5 + load16z 0x789a R0 R6 + load16z 0x89ab R0 R7 + load16z 0x9abc R1 R0 + load16z 0xabcd R2 R0 + load16z 0xbcde R3 R0 + load16z 0xcdef R4 R0 + load16z 0xdef0 R5 R0 + load16z 0xef01 R6 R0 + load16z 0xf012 R7 R0 + + load16zp 0x0123 P0 + load16zp 0x1234 P1 + load16zp 0x1234 p2 +.ifndef BFIN_HOST + load16zp 0x2345 p3 +.endif + load16zp 0x3456 p4 + load16zp 0x4567 p5 + load16zp 0x5678 sp + load16zp 0x6789 fp + load16zp 0x789a i0 + load16zp 0x89ab i1 + load16zp 0x9abc i2 + load16zp 0xabcd i3 + load16zp 0xbcde m0 + load16zp 0xcdef m1 + load16zp 0xdef0 m2 + load16zp 0xef01 m3 + load16zp 0xf012 b0 + load16zp 0x0123 b1 + load16zp 0x1234 b2 + load16zp 0x2345 b3 + load16zp 0x3456 l0 + load16zp 0x4567 l1 + load16zp 0x5678 l2 + load16zp 0x6789 l3 + + /* Sign Extended */ + load16x 0x20 R0 R1 + load16x 0x3F R0 R1 + load16x -0x20 R0 R1 + load16x -0x3F R0 R1 + load16x 0x1234 R0 R1 + load16x 0x2345 R0 R1 + load16x 0x3456 R0 R2 + load16x 0x4567 R0 R3 + load16x 0x5678 R0 R4 + load16x 0x6789 R0 R5 + load16x 0x789a R0 R6 + load16x 0x09ab R0 R7 + load16x -0x1abc R1 R0 + load16x -0x2bcd R2 R0 + load16x -0x3cde R3 R0 + load16x -0x4def R4 R0 + load16x -0x5ef0 R5 R0 + load16x -0x6f01 R6 R0 + load16x -0x7012 R7 R0 + + loadinc P0, P1, R1 + loadinc P1, P2, R1 + loadinc P2, P1, R2 +.ifndef BFIN_HOST + loadinc P3, P4, R3 +.endif + loadinc P4, P5, R4 + loadinc FP, P0, R7 + loadinc P0, I0, R1 + loadinc P1, I1, R1 + loadinc P2, I2, R1 +.ifndef BFIN_HOST + loadinc P3, I0, R1 +.endif + loadinc P4, I2, R1 + loadinc P5, I3, R1 + + A1 = A0 = 0; + R0 = 0x01 (Z); + A0.x = R0; + imm32 r4, 0x32e02d1a + A1.x = R4; + A0.w = A1.x; + R3 = A0.w; + R2 = A0.x; + imm32 r0, 0x0000001a + imm32 r1, 0x00000001 + CC = R1 == R2; + if CC jump 1f; + fail +1: + CC = R0 == R3 + if CC jump 2f; + fail +2: + pass + +.data +_buf: + .rept 0x80 + .long 0 + .endr diff --git a/sim/testsuite/bfin/logic.s b/sim/testsuite/bfin/logic.s new file mode 100644 index 0000000..9a41ccd --- /dev/null +++ b/sim/testsuite/bfin/logic.s @@ -0,0 +1,64 @@ +// test program for microcontroller instructions +// Test instructions +// r4 = r2 & r3; +// r4 = r2 | r3; +// r4 = r2 ^ r3; +// r4 = ~ r2; +# mach: bfin + +.include "testutils.inc" + start + + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + + R7 = R0 & R1; + DBGA ( R7.L , 0x1111 ); + DBGA ( R7.H , 0x1111 ); + + R7 = R2 & R3; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + + R7 = R0 | R1; + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + + R7 = R2 | R3; + DBGA ( R7.L , 0x000f ); + DBGA ( R7.H , 0x0000 ); + + R7 = R0 ^ R1; + DBGA ( R7.L , 0xeeee ); + DBGA ( R7.H , 0xeeee ); + + R7 = R2 ^ R3; + DBGA ( R7.L , 0x000e ); + DBGA ( R7.H , 0x0000 ); + + R7 = ~ R0; + DBGA ( R7.L , 0xeeee ); + DBGA ( R7.H , 0xeeee ); + + R7 = ~ R2; + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0xffff ); + + pass + + .data +data0: + .dw 0x1111 + .dw 0x1111 + .dw 0xffff + .dw 0xffff + .dw 0x0001 + .dw 0x0000 + .dw 0x000f + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/bfin/loop_snafu.s b/sim/testsuite/bfin/loop_snafu.s new file mode 100644 index 0000000..b1e3664 --- /dev/null +++ b/sim/testsuite/bfin/loop_snafu.s @@ -0,0 +1,28 @@ +# mach: bfin + +.include "testutils.inc" + start + + r5=10; + p1=r5; + r7=20; + lsetup (lstart, lend) lc0=p1; + +lstart: + nop; + nop; + nop; + nop; + jump lend; + nop; + nop; + nop; +lend: + r7 += -1; + + nop; + nop; + + dbga( r7.l,10); + + pass diff --git a/sim/testsuite/bfin/loop_strncpy.s b/sim/testsuite/bfin/loop_strncpy.s new file mode 100644 index 0000000..13b3711 --- /dev/null +++ b/sim/testsuite/bfin/loop_strncpy.s @@ -0,0 +1,76 @@ +# Blackfin testcase for loop counter values when jumping out from the last insn +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + loadsym r1, dest; + r0 = r1; + loadsym r1, src; + r2 = 0x10; + +_strncpy: + CC = R2 == 0; + if CC JUMP 4f; + + P2 = R2 ; /* size */ + P0 = R0 ; /* dst*/ + P1 = R1 ; /* src*/ + + LSETUP (1f, 2f) LC0 = P2; +1: + R1 = B [P1++] (Z); + B [P0++] = R1; + CC = R1 == 0; +2: + if CC jump 3f; + + fail + + /* if src is shorter than n, we need to null pad bytes in dest + * but, we can get here when the last byte is zero, and we don't + * want to copy an extra byte at the end, so we need to check + */ +3: + R2 = LC0; + CHECKREG R2, 0x0a; + + CC = R2 + if ! CC jump 4f; + + LSETUP(5f, 5f) LC0; +5: + B [P0++] = R1; + +4: + loadsym P1, answer; + P0 = R0; + p2 = 0x20; + LSETUP (6f, 7f) LC0 = P2; +6: + R1 = B [P0++]; + R2 = B [P1++]; + CC = R1 == R2 + IF ! CC JUMP wrong; +7: + NOP; + + pass + +wrong: + fail + + .data +dest: + .db 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F + .db 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F + +src: + .db 0x21, 0x22, 0x23, 0x24, 0x25, 0x00, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30 + +answer: + .db 0x21, 0x22, 0x23, 0x24, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + .db 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F diff --git a/sim/testsuite/bfin/lp0.s b/sim/testsuite/bfin/lp0.s new file mode 100644 index 0000000..dd7bc30 --- /dev/null +++ b/sim/testsuite/bfin/lp0.s @@ -0,0 +1,17 @@ +// Assert that loops can have coincidental loop ends. +# mach: bfin + +.include "testutils.inc" + start + + + P0 = 3; + R1 = 0; + LSETUP ( out0 , out1 ) LC0 = P0; +out0: + LSETUP ( out1 , out1 ) LC1 = P0; +out1: + R1 += 1; + + DBGA ( R1.L , 9 ); + pass diff --git a/sim/testsuite/bfin/lp1.s b/sim/testsuite/bfin/lp1.s new file mode 100644 index 0000000..89fa2a9 --- /dev/null +++ b/sim/testsuite/bfin/lp1.s @@ -0,0 +1,16 @@ +# mach: bfin +.include "testutils.inc" + start + + P0 = 10; + + LSETUP ( xxx , yyy ) LC0 = P0; +xxx: + R1 += 1; + CC = R1 == 3; +yyy: + IF CC JUMP zzz; + R3 = 7; +zzz: + DBGA ( R1.L , 3 ); + pass diff --git a/sim/testsuite/bfin/lsetup.s b/sim/testsuite/bfin/lsetup.s new file mode 100644 index 0000000..ac39613 --- /dev/null +++ b/sim/testsuite/bfin/lsetup.s @@ -0,0 +1,109 @@ +# Blackfin testcase for playing with LSETUP +# mach: bfin + + .include "testutils.inc" + + start + + R0 = 0x123; + P0 = R0; + LSETUP (.L1, .L1) LC0 = P0; +.L1: + R0 += -1; + + R1 = 0; + CC = R1 == R0; + IF CC JUMP 1f; + fail +1: + p0=10; + loadsym i0, _buf + imm32 r0, 0x12345678 + LSETUP(.L2, .L3) lc0 = p0; +.L2: + [i0++] = r0; +.L3: + [i0++] = r0; + + loadsym R1, _buf + R0 = 0x50; + R1 = R0 + R1; + R0 = I0; + CC = R0 == R1; + if CC JUMP 2f; + fail +2: + + r5=10; + p1=r5; + r7=20; + lsetup (.L4, .L5) lc0=p1; +.L4: + nop; + nop; + nop; + nop; + jump .L5; + nop; + nop; + nop; +.L5: + r7 += -1; + + R0 = 10 (Z); + CC = R7 == R0; + if CC jump 3f; + fail +3: + r1 = 1; + r2 = 2; + r0 = 0; + p1 = 10; + loadsym p0, _buf; + lsetup (.L6, .L7) lc0 = p1; +.L6: + [p0++] = r1; +.L7: + [p0++] = r2; + + r3 = P0; + loadsym r1, _buf + r0 = 80; + r1 = r1 + r0; + CC = R1 == R3 + if CC jump 4f; + fail +4: + + R0 = 1; + R1 = 2; + R2 = 3; + R4 = 4; + P1 = R1; + LSETUP (.L8, .L8) LC0 = P1; + R5 = 5; + R6 = 6; + R7 = 7; +.L8: + R1 += 1; + + R7 = 4; + CC = R7 == R1; + if CC jump 5f; + fail +5: + P1 = R1; + LSETUP (.L9, .L9 ) LC1 = P1; +.L9: + R1 += 1; + R7 = 8; + if CC jump 6f; + fail +6: + pass + +.data +_buf: + .rept 0x80 + .long 0 + .endr diff --git a/sim/testsuite/bfin/m0boundary.s b/sim/testsuite/bfin/m0boundary.s new file mode 100644 index 0000000..5995d88 --- /dev/null +++ b/sim/testsuite/bfin/m0boundary.s @@ -0,0 +1,46 @@ +# mach: bfin + +.include "testutils.inc" + start + +// setup a circular buffer calculation based on illegal register values + I0 = 0xf2ef (Z); + I0.H = 0xff88; + + L0 = 0xbd5f (Z); + L0.H = 0xea9b; + + M0 = 0x0000 (Z); + M0.H = 0x8000; + + B0 = 0x3fb9 (Z); + B0.H = 0xff80; + +op1: + I0 -= M0; + + R0 = I0; + DBGA ( R0.H , 0x7f88 ); + DBGA ( R0.L , 0xf2ef ); + +// setup a circular buffer calculation based on illegal register values + I0 = 0xf2ef (Z); + I0.H = 0xff88; + + L0 = 0xbd5f (Z); + L0.H = 0xea9b; + + M0 = 0x0001 (Z); + M0.H = 0x8000; + + B0 = 0x3fb9 (Z); + B0.H = 0xff80; + +op2: + I0 -= M0; + + R0 = I0; + DBGA ( R0.H , 0x7f88 ); + DBGA ( R0.L , 0xf2ee ); + + pass diff --git a/sim/testsuite/bfin/m1.S b/sim/testsuite/bfin/m1.S new file mode 100644 index 0000000..5ddc5d3 --- /dev/null +++ b/sim/testsuite/bfin/m1.S @@ -0,0 +1,58 @@ +// MAC test program. +// Test for positive and negative saturation using +// SIGNED FRACTIONAL mode. +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + +// load r0=0x00007fff +// load r1=0x00007fff + loadsym p0, data0 + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + + R5 = 0; + R4 = 0; + BITSET( R4 , 9 ); + A1 = A0 = 0; + +LOOP1: + A1 -= R0.L * R1.L, A0 += R0.L * R1.L; +//_DBG a1; +//_DBG a0; + R4 += -1; + CC = R4 == R5; + IF !CC JUMP LOOP1; +R3 = ASTAT; +CHECKREG R3, (_AV1S|_AV1|_AV0S|_AV0|_AC0|_AC0_COPY|_CC|_AZ); + + _DBG A1; + _DBG A0; + + R6 = A1.w; + _DBG ASTAT; + R7.L = A1.x; + R3 = ASTAT; + _DBG r3; + CHECKREG R3, (_AV1S|_AV1|_AV0S|_AV0|_AC0|_AC0_COPY|_CC|_AZ); + + CHECKREG R6, 0; + CHECKREG R7, 0x0000FF80; + R6 = A0.w; + R7.L = A0.x; + CHECKREG R6, 0xffffffff; + CHECKREG R7, 0x7f; + + pass + + .data 0x1000; +data0: + .dw 0x7fff + .dw 0x0000 + .dw 0x7fff + .dw 0x0000 diff --git a/sim/testsuite/bfin/m10.s b/sim/testsuite/bfin/m10.s new file mode 100644 index 0000000..5feb42f --- /dev/null +++ b/sim/testsuite/bfin/m10.s @@ -0,0 +1,63 @@ +# mach: bfin + +// Test extraction from accumulators: +// ROUND/TRUNCATE in UNSIGNED FRACTIONAL mode +// test ops: "+=" + +.include "testutils.inc" + start + + +// load r0=0xfffef000 +// load r1=0xfffff000 +// load r2=0x00008000 +// load r3=0x00018000 +// load r4=0x0000007f + loadsym P0, data0 + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// round +// 0x00fffef000 -> 0xffff + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1, R5.L = A0 (FU); + DBGA ( R5.L , 0xffff ); + DBGA ( R5.H , 0xffff ); + +// truncate +// 0x00fffef00 -> 0xfffe + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1, R5.L = A0 (TFU); + DBGA ( R5.L , 0xfffe ); + DBGA ( R5.H , 0xfffe ); + +// round +// 0x00fffff000 -> 0xffff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R5.H = A1, R5.L = A0 (FU); + DBGA ( R5.L , 0xffff ); + DBGA ( R5.H , 0xffff ); + + pass + + .data; +data0: + .dw 0xf000 + .dw 0xfffe + .dw 0xf000 + .dw 0xffff + .dw 0x8000 + .dw 0x0000 + .dw 0x8000 + .dw 0x0001 + .dw 0x007f + .dw 0x0000 diff --git a/sim/testsuite/bfin/m11.s b/sim/testsuite/bfin/m11.s new file mode 100644 index 0000000..843c0ab --- /dev/null +++ b/sim/testsuite/bfin/m11.s @@ -0,0 +1,72 @@ +// Test extraction from accumulators: +// SCALE in SIGNED FRACTIONAL mode +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x3fff0000 +// load r1=0x0fffc000 +// load r2=0x7ff00000 +// load r3=0x80100000 +// load r4=0x000000ff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// SCALE +// 0x003fff0000 -> SCALE 0x7ffe + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1, R5.L = A0 (S2RND); + DBGA ( R5.L , 0x7ffe ); + DBGA ( R5.H , 0x7ffe ); + +// SCALE +// 0x000fffc000 -> SCALE 0x2000 + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R5.H = A1, R5.L = A0 (S2RND); + DBGA ( R5.L , 0x2000 ); + DBGA ( R5.H , 0x2000 ); + +// SCALE +// 0x007ff00000 -> SCALE 0x7fff + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + R5.H = A1, R5.L = A0 (S2RND); + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + +// SCALE +// 0xff80100000 -> SCALE 0x8000 + A1 = A0 = 0; + A1.w = R3; + A0.w = R3; + A1.x = R4.L; + A0.x = R4.L; + R5.H = A1, R5.L = A0 (S2RND); + DBGA ( R5.L , 0x8000 ); + DBGA ( R5.H , 0x8000 ); + + pass + + .data; +data0: + .dw 0x0000 + .dw 0x3fff + .dw 0xc000 + .dw 0x0fff + .dw 0x0000 + .dw 0x7ff0 + .dw 0x0000 + .dw 0x8010 + .dw 0x00ff + .dw 0x0000 diff --git a/sim/testsuite/bfin/m12.s b/sim/testsuite/bfin/m12.s new file mode 100644 index 0000000..37306e7 --- /dev/null +++ b/sim/testsuite/bfin/m12.s @@ -0,0 +1,74 @@ +// Test extraction from accumulators: +// SCALE in SIGNED INTEGER mode +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x00000fff +// load r1=0x00007fff +// load r2=0xffffffff +// load r3=0xffff0fff +// load r4=0x000000ff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// SCALE +// 0x0000000fff -> SCALE 0x1ffe + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1, R5.L = A0 (ISS2); + DBGA ( R5.L , 0x1ffe ); + DBGA ( R5.H , 0x1ffe ); + +// SCALE +// 0x0000007fff -> SCALE 0x7fff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R5.H = A1, R5.L = A0 (ISS2); + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + +// SCALE +// 0xffffffffff -> SCALE 0xfffe + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + A1.x = R4.L; + A0.x = R4.L; + R5.H = A1, R5.L = A0 (ISS2); + DBGA ( R5.L , 0xfffe ); + DBGA ( R5.H , 0xfffe ); + +// SCALE +// 0xffffff0fff -> SCALE 0x8000 + A1 = A0 = 0; + A1.w = R3; + A0.w = R3; + A1.x = R4.L; + A0.x = R4.L; + R5.H = A1, R5.L = A0 (ISS2); + DBGA ( R5.L , 0x8000 ); + DBGA ( R5.H , 0x8000 ); + + pass + + .data +data0: + .dw 0x0fff + .dw 0x0000 + .dw 0x7fff + .dw 0x0000 + .dw 0xffff + .dw 0xffff + .dw 0x0fff + .dw 0xffff + .dw 0x00ff + .dw 0x0000 diff --git a/sim/testsuite/bfin/m13.s b/sim/testsuite/bfin/m13.s new file mode 100644 index 0000000..05547a7 --- /dev/null +++ b/sim/testsuite/bfin/m13.s @@ -0,0 +1,93 @@ +// Test extraction from accumulators: +// SIGNED FRACTIONAL and SIGNED INT mode into register PAIR +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x7ffffff0 +// load r1=0xfffffff0 +// load r2=0x0fffffff +// load r3=0x80100000 +// load r4=0x000000ff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// extract +// 0x007ffffff0 -> 0x7fffffff0 + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R7 = A1, R6 = A0; + DBGA ( R7.L , 0xfff0 ); + DBGA ( R7.H , 0x7fff ); + DBGA ( R6.L , 0xfff0 ); + DBGA ( R6.H , 0x7fff ); + +// extract with saturate +// 0x00fffffff0 -> 0x7ffffffff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R7 = A1, R6 = A0; + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x7fff ); + +// extract with saturate negative +// 0xff0ffffff0 -> 0x80000000 + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + A1.x = R4.L; + A0.x = R4.L; + R7 = A1, R6 = A0; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x8000 ); + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + +// extract integer (same as fract) +// 0x007ffffff0 -> 0x7fffffff0 + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R7 = A1, R6 = A0 (IS); + DBGA ( R7.L , 0xfff0 ); + DBGA ( R7.H , 0x7fff ); + DBGA ( R6.L , 0xfff0 ); + DBGA ( R6.H , 0x7fff ); + +// extract with saturate negative +// 0xff0ffffff0 -> 0x80000000 + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + A1.x = R4.L; + A0.x = R4.L; + R7 = A1, R6 = A0 (IS); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x8000 ); + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + + pass + + .data +data0: + .dw 0xfff0 + .dw 0x7fff + .dw 0xfff0 + .dw 0xffff + .dw 0xffff + .dw 0x0fff + .dw 0x0000 + .dw 0x8010 + .dw 0x00ff + .dw 0x0000 diff --git a/sim/testsuite/bfin/m14.s b/sim/testsuite/bfin/m14.s new file mode 100644 index 0000000..bd3134e --- /dev/null +++ b/sim/testsuite/bfin/m14.s @@ -0,0 +1,82 @@ +// Test extraction from accumulators: +// UNSIGNED FRACTIONAL and SIGNED INT mode into register PAIR +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x7ffffff0 +// load r1=0xfffffff0 +// load r2=0x0fffffff +// load r3=0x00000001 +// load r4=0x000000ff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// extract +// 0x00fffffff0 -> 0xffffffff0 + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R7 = A1, R6 = A0 (FU); + DBGA ( R7.L , 0xfff0 ); + DBGA ( R7.H , 0xffff ); + DBGA ( R6.L , 0xfff0 ); + DBGA ( R6.H , 0xffff ); + +// extract with saturation +// 0x01fffffff0 -> 0xfffffffff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + A1.x = R3.L; + A0.x = R3.L; + R7 = A1, R6 = A0 (FU); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + +// extract with saturation +// 0xfffffffff0 -> 0xfffffffff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + A1.x = R4.L; + A0.x = R4.L; + R7 = A1, R6 = A0 (FU); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + +// extract unsigned +// 0x00fffffff0 -> 0xffffffff0 + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R7 = A1, R6 = A0 (FU); + DBGA ( R7.L , 0xfff0 ); + DBGA ( R7.H , 0xffff ); + DBGA ( R6.L , 0xfff0 ); + DBGA ( R6.H , 0xffff ); + + pass + + .data +data0: + .dw 0xfff0 + .dw 0x7fff + .dw 0xfff0 + .dw 0xffff + .dw 0xffff + .dw 0x0fff + .dw 0x0001 + .dw 0x0000 + .dw 0x00ff + .dw 0x0000 diff --git a/sim/testsuite/bfin/m15.s b/sim/testsuite/bfin/m15.s new file mode 100644 index 0000000..e429232 --- /dev/null +++ b/sim/testsuite/bfin/m15.s @@ -0,0 +1,80 @@ +// Test extraction from accumulators: +// SIGNED FRACTIONAL and SIGNED INT mode into register PAIR with SCALE +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x0ffffff0 +// load r1=0x7ffffff0 +// load r2=0x0fffffff +// load r3=0x80100000 +// load r4=0x000000ff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// extract +// 0x000ffffff0 -> 0x1ffffffe0 + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R7 = A1, R6 = A0 (S2RND); + DBGA ( R7.L , 0xffe0 ); + DBGA ( R7.H , 0x1fff ); + DBGA ( R6.L , 0xffe0 ); + DBGA ( R6.H , 0x1fff ); + +// extract (saturate) +// 0x007ffffff0 -> 0x7ffffffff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R7 = A1, R6 = A0 (S2RND); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x7fff ); + +// extract (saturate negative) +// 0xff0ffffff0 -> 0x80000000 + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + A1.x = R4.L; + A0.x = R4.L; + R7 = A1, R6 = A0 (S2RND); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x8000 ); + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + +// extract int +// 0x000ffffff0 -> 0x1ffffffe0 + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R7 = A1, R6 = A0 (ISS2); + DBGA ( R7.L , 0xffe0 ); + DBGA ( R7.H , 0x1fff ); + DBGA ( R6.L , 0xffe0 ); + DBGA ( R6.H , 0x1fff ); + + pass + + .data +data0: + .dw 0xfff0 + .dw 0x0fff + .dw 0xfff0 + .dw 0x7fff + .dw 0xffff + .dw 0x0fff + .dw 0x0000 + .dw 0x8010 + .dw 0x00ff + .dw 0x0000 diff --git a/sim/testsuite/bfin/m16.s b/sim/testsuite/bfin/m16.s new file mode 100644 index 0000000..9cbc57c --- /dev/null +++ b/sim/testsuite/bfin/m16.s @@ -0,0 +1,65 @@ +// Test various moves to single register half +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x7fffffff +// load r1=0x00ffffff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// extract only to high half + R5 = 0; + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1; + DBGA ( R5.L , 0x0000 ); + DBGA ( R5.H , 0x7fff ); + +// extract only to low half + R5 = 0; + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.L = A0; + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x0000 ); + +// extract only to high half + R5 = 0; + A1 = A0 = 0; + R5.H = ( A1 += R0.H * R0.H ), A0 += R0.H * R0.H; + DBGA ( R5.L , 0x0000 ); + DBGA ( R5.H , 0x7ffe ); + +// extract only to low half + R5 = 0; + A1 = A0 = 0; + A1 += R0.H * R0.H, R5.L = ( A0 += R0.H * R0.H ); + DBGA ( R5.L , 0x7ffe ); + DBGA ( R5.H , 0x0000 ); + + pass + + .data +data0: + .dw 0xffff + .dw 0x7fff + .dw 0xffff + .dw 0x00ff + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/bfin/m17.s b/sim/testsuite/bfin/m17.s new file mode 100644 index 0000000..c7aec4b --- /dev/null +++ b/sim/testsuite/bfin/m17.s @@ -0,0 +1,74 @@ +// Test various moves to single register +# mach: bfin + + +.include "testutils.inc" + start + + +// load r0=0x7fffffff +// load r1=0x00ffffff +// load r2=0xf0000000 +// load r3=0x0000007f + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + +// extract only to high register + R5 = 0; + R4 = 0; + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5 = A1; + DBGA ( R4.L , 0x0000 ); + DBGA ( R4.H , 0x0000 ); + DBGA ( R5.L , 0xffff ); + DBGA ( R5.H , 0x7fff ); + +// extract only to low register + R5 = 0; + R4 = 0; + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R4 = A0; + DBGA ( R4.L , 0xffff ); + DBGA ( R4.H , 0x7fff ); + DBGA ( R5.L , 0x0000 ); + DBGA ( R5.H , 0x0000 ); + +// extract only to high reg + R5 = 0; + R4 = 0; + A1 = A0 = 0; + R5 = ( A1 += R0.H * R0.H ), A0 += R0.H * R0.H; + DBGA ( R4.L , 0x0000 ); + DBGA ( R4.H , 0x0000 ); + DBGA ( R5.L , 0x0002 ); + DBGA ( R5.H , 0x7ffe ); + +// extract only to low reg + R5 = 0; + R4 = 0; + A1 = A0 = 0; + A1 += R0.H * R0.H, R4 = ( A0 += R0.H * R0.H ); + DBGA ( R4.L , 0x0002 ); + DBGA ( R4.H , 0x7ffe ); + DBGA ( R5.L , 0x0000 ); + DBGA ( R5.H , 0x0000 ); + + pass + + .data +data0: + .dw 0xffff + .dw 0x7fff + .dw 0xffff + .dw 0x00ff + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 diff --git a/sim/testsuite/bfin/m2.s b/sim/testsuite/bfin/m2.s new file mode 100644 index 0000000..2ff155c --- /dev/null +++ b/sim/testsuite/bfin/m2.s @@ -0,0 +1,263 @@ +// MAC test program. +// Test basic edge values +// SIGNED FRACTIONAL mode +// test ops: "+=" "-=" "=" "NOP" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80007fff +// load r1=0x80007fff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// 0x7fff * 0x7fff = 0x007ffe0002 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 += R0.L * R1.L, A0 += R0.L * R1.L; + R6 = A1.w; + _DBG ASTAT; + _DBG A0; + R7.L = A1.x; + _DBG ASTAT; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x7ffe ); + DBGA ( R7.L , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// 0x8000 * 0x7fff = 0xff80010000 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 += R0.H * R1.L, A0 += R0.H * R1.L; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8001 ); + DBGA ( R7.L , 0xffff ); + _DBG ASTAT; + R7 = ASTAT; + DBGA (R7.H, 0x0); + DBGA (R7.L, 0x0); + +// 0x8000 * 0x8000 = 0x007fffffff + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 += R0.H * R1.H, A0 += R0.H * R1.H; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + DBGA ( R7.L , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// saturate positive by first loading large value into accums +// expected value is 0x7fffffffff + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A1.x = R3.L; + A0.w = R2; + A0.x = R3.L; + A1 += R0.L * R1.L, A0 += R0.L * R1.L; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0x007f ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate negative +// expected value is 0x8000000000 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.x = R4.L; + A0.x = R4.L; + A1 += R0.L * R1.H, A0 += R0.L * R1.H; + R6 = A1.w; + _DBG ASTAT; + R7.L = A1.x; + _DBG ASTAT; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xff80 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate positive with "-=" +// expected value is 0x7fffffffff + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A1.x = R3.L; + A0.w = R2; + A0.x = R3.L; + A1 -= R0.H * R1.L, A0 -= R0.H * R1.L; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0x007f ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate negative with "-=" +// expected value is 0x8000000000 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.x = R4.L; + A0.x = R4.L; + A1 -= R0.L * R1.L, A0 -= R0.L * R1.L; + R6 = A1.w; + _DBG ASTAT; + R7.L = A1.x; + _DBG ASTAT; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xff80 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 ); + +// 0x8000 * 0x8000 = 0xff80000001 with "-=" + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 -= R0.H * R1.H, A0 -= R0.H * R1.H; + R6 = A1.w; + _DBG ASTAT; + R7.L = A1.x; + _DBG ASTAT; + + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + DBGA ( R7.L , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// 0x7fff * 0x7fff = 0x007ffe0002 with "=" + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 += R0.L * R1.L, A0 += R0.L * R1.L; + A1 = R0.L * R1.L, A0 = R0.L * R1.L; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x7ffe ); + DBGA ( R7.L , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// 0x7fff * 0x7fff = 0x007ffe0002 with "NOP" + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 += R0.L * R1.L; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x7ffe ); + DBGA ( R7.L , 0x0000 ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// 0x8000 * 0x8000 = 0x007fffffff with "NOP" + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 += R0.H * R1.H; + _DBG A1; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + DBGA ( R7.L , 0x0000 ); + + R6 = A0.w; + _DBG ASTAT; + R7.L = A0.x; + _DBG ASTAT; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + R7 = ASTAT; _dbg astat; +//AV1 AV1S should be 0. + DBGA ( R7.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + + _DBG ASTAT; + A1 = A0 = 0; + _DBG A1; + _DBG R0; _DBG R1; + A1 += R0.L * R1.L; // make sure overflow flag is not set to zero + _DBG A1; + _DBG ASTAT; + R7 = ASTAT; +//AV1S should be 0. + DBGA ( R7.H, 0x0000 ); + DBGA ( R7.L, 0x0000 ); + + pass + + .data +data0: + .dw 0x7fff + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/bfin/m3.s b/sim/testsuite/bfin/m3.s new file mode 100644 index 0000000..116263c --- /dev/null +++ b/sim/testsuite/bfin/m3.s @@ -0,0 +1,138 @@ +// MAC test program. +// Test basic edge values +// UNSIGNED FRACTIONAL mode U +// test ops: "+=" "-=" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80007fff +// load r1=0x80007fff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 +// load r5=0xffffffff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + + dbga(r0.h, 0x8000); + dbga(r0.l, 0x7fff); + dbga(r1.h, 0x8000); + dbga(r1.l, 0x7fff); + dbga(r2.h, 0xf000); + dbga(r2.l, 0); + +// 0x8000 * 0x7fff = 0x003fff8000 + A1 = A0 = 0; + A1 += R0.H * R1.L, A0 += R0.H * R1.L (FU); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x3fff ); + DBGA ( R7.L , 0x0000 ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x3fff ); + DBGA ( R7.L , 0x0000 ); + +// 0x8000 * 0x8000 = 0x0040000000 + A1 = A0 = 0; + A1 += R0.H * R1.H, A0 += R0.H * R1.H (FU); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + DBGA ( R7.L , 0x0000 ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + DBGA ( R7.L , 0x0000 ); + +// 0xffff * 0xffff = 0x00fffe0001 + A1 = A0 = 0; + A1 += R5.H * R5.H, A0 += R5.H * R5.H (FU); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0xfffe ); + DBGA ( R7.L , 0x0000 ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0xfffe ); + DBGA ( R7.L , 0x0000 ); + +// saturate high by first loading large value into accums +// expected value is 0xffffffffff + A1 = A0 = 0; + A1.w = R5; + A1.x = R5.L; + A0.w = R5; + A0.x = R5.L; + A1 += R5.H * R5.H, A0 += R5.H * R5.H (FU); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0xffff ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0xffff ); + +// saturate low with "-=" +// expected value is 0x0000000000 + A1 = A0 = 0; + A1 -= R4.L * R4.L, A0 -= R4.L * R4.L (FU); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + +// saturate low with "-=" +// expected value is 0x0000000000 + A1 = A0 = 0; + A1 -= R1.H * R0.H, A0 -= R1.H * R0.H (FU); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + + pass + + .data +data0: + .dw 0x7fff + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 + .dw 0xffff + .dw 0xffff diff --git a/sim/testsuite/bfin/m4.s b/sim/testsuite/bfin/m4.s new file mode 100644 index 0000000..8977063 --- /dev/null +++ b/sim/testsuite/bfin/m4.s @@ -0,0 +1,124 @@ +// MAC test program. +// Test basic edge values +// SIGNED INTEGER mode +// test ops: "+=" "-=" "=" "NOP" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80007fff +// load r1=0x80007fff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// 0x7fff * 0x7fff = 0x003fff0001 + A1 = A0 = 0; + A1 += R0.L * R1.L, A0 += R0.L * R1.L (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x3fff ); + DBGA ( R7.L , 0x0000 ); + +// 0x8000 * 0x7fff = 0xffc0008000 + A1 = A0 = 0; + A1 += R0.H * R1.L, A0 += R0.H * R1.L (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0xc000 ); + DBGA ( R7.L , 0xffff ); + +// 0x8000 * 0x8000 = 0x0040000000 + A1 = A0 = 0; + A1 += R0.H * R1.H, A0 += R0.H * R1.H (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + DBGA ( R7.L , 0x0000 ); + +// saturate positive by first loading large value into accums +// expected value is 0x7fffffffff + A1 = A0 = 0; + A1.w = R2; + A1.x = R3.L; + A0.w = R2; + A0.x = R3.L; + A1 += R0.L * R1.L, A0 += R0.L * R1.L (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0x007f ); + +// saturate negative +// expected value is 0x8000000000 + A1 = A0 = 0; + A1.x = R4.L; + A0.x = R4.L; + A1 += R0.L * R1.H, A0 += R0.L * R1.H (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xff80 ); + +// saturate positive with "-=" +// expected value is 0x7fffffffff + A1 = A0 = 0; + A1.w = R2; + A1.x = R3.L; + A0.w = R2; + A0.x = R3.L; + A1 -= R0.H * R1.L, A0 -= R0.H * R1.L (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0x007f ); + +// saturate negative with "-=" +// expected value is 0x8000000000 + A1 = A0 = 0; + A1.x = R4.L; + A0.x = R4.L; + A1 -= R0.L * R1.L, A0 -= R0.L * R1.L (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xff80 ); + +// 0x8000 * 0x8000 = 0xffc0000000 with "-=" + A1 = A0 = 0; + A1 -= R0.H * R1.H, A0 -= R0.H * R1.H (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xc000 ); + DBGA ( R7.L , 0xffff ); + + pass + + .data 0x1000; +data0: + .dw 0x7fff + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/bfin/m5.s b/sim/testsuite/bfin/m5.s new file mode 100644 index 0000000..e39a2e0 --- /dev/null +++ b/sim/testsuite/bfin/m5.s @@ -0,0 +1,153 @@ +// Test result extraction of mac instructions. +// Test basic edge values +// SIGNED FRACTIONAL mode into SINGLE destination register +// test ops: "+=" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80007fff +// load r1=0x80007fff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 + loadsym p0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// simple extraction with no saturation +// 0x7fff * 0x7fff = 0x007ffe0002 -> 0x7ffe + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + R5.H = (A1 += R0.L * R1.L), R5.L = (A0 += R0.L * R1.L); + DBGA ( R5.L , 0x7ffe ); + DBGA ( R5.H , 0x7ffe ); + _DBG ASTAT; + R7 = ASTAT; + DBGA (R7.H, 0x0); + DBGA (R7.L, 0x0); + +// positive saturation at 32 bits +// 0x0 * 0x0 + 0x7ff0000000 -> 0x7fff + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A1.x = R3.L; + A0.x = R3.L; + A0.w = R2; + R5.H = (A1 += R0.L * R2.L), R5.L = (A0 += R0.L * R2.L); + _DBG A1; + _DBG A0; + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + _DBG ASTAT; + R7 = ASTAT; + _DBG R7; + DBGA (R7.H, 0x300); + DBGA (R7.L, 0x8); + +// positive saturation at 32 bits +// 0x7fff * 0x7fff + 0x7ff0000000 -> 0x7fff + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A1.x = R3.L; + A0.w = R2; + A0.x = R3.L; + R5.H = (A1 += R0.L * R1.L), R5.L = (A0 += R0.L * R1.L); + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + _DBG ASTAT; + R7 = ASTAT; + DBGA (R7.H, 0x30f); + DBGA (R7.L, 0x8); + +// negative saturation at 32 bits +// 0x0 * 0x0 + 0x80f0000000 -> 0x8000 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A1.x = R4.L; + A0.w = R2; + A0.x = R4.L; + R5.H = (A1 += R0.L * R2.L), R5.L = (A0 += R0.L * R2.L); + DBGA ( R5.L , 0x8000 ); + DBGA ( R5.H , 0x8000 ); + _DBG A1; + _DBG A0; + _DBG ASTAT; + R7=ASTAT; + _DBG R7; + DBGA (R7.H, 0x300); + DBGA (R7.L, 0x0008); + +// negative saturation at 32 bits +// 0x7fff * 0x8000 + 0x80f0000000 -> 0x8000 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A1.x = R4.L; + A0.w = R2; + A0.x = R4.L; + R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L); + DBGA ( R5.L , 0x8000 ); + DBGA ( R5.H , 0x8000 ); + R7=ASTAT; + _DBG ASTAT; + DBGA (R7.H, 0x300); + DBGA (R7.L, 0x0008); + +// negative saturation at 32 bits on MAC only +// 0x7fff * 0x8000 + 0x80f0000000 -> 0x8000 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A0.w = R2; + A0.x = R4.L; + _DBG ASTAT; + R5.H = A1, R5.L = (A0 += R0.H * R1.L); + _DBG A0; + DBGA ( R5.L , 0x8000 ); + DBGA ( R5.H , 0x0000 ); + R7=ASTAT; + _DBG ASTAT; + DBGA (R7.H, 0x300); + DBGA (R7.L, 0x0009); + +// 0x0100 * 0x0100 = 0x00020000 -> 0x0002 + R7 = 0; + ASTAT = R7; + R0.L = 0x0100; + R1.L = 0x0100; + A1 = A0 = 0; + R5.H = (A1 = R0.L * R1.L), R5.L = (A0 = R0.L * R1.L) (T); + DBGA ( R5.L , 0x0002 ); + DBGA ( R5.H , 0x0002 ); + R7 = ASTAT; + DBGA (R7.H, 0x000); + DBGA (R7.L, 0x000); + + pass + + .data +data0: + .dw 0x7fff + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/bfin/m6.s b/sim/testsuite/bfin/m6.s new file mode 100644 index 0000000..738d623 --- /dev/null +++ b/sim/testsuite/bfin/m6.s @@ -0,0 +1,57 @@ +// Test result extraction of mac instructions. +// Test basic edge values +// SIGNED INTEGER mode into SINGLE destination register +// test ops: "+=" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80000001 +// load r1=0x80007fff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// integer extraction with no saturation +// 0x1 * 0x1 = 0x0000000001 -> 0x1 + A1 = A0 = 0; + R5.H = (A1 += R0.L * R0.L), R5.L = (A0 += R0.L * R0.L) (IS); + DBGA ( R5.L , 0x1 ); + DBGA ( R5.H , 0x1 ); + +// integer extraction with positive saturation +// 0x7fff * 0x7f -> 0x7fff + A1 = A0 = 0; + R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IS); + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + +// integer extraction with negative saturation +// 0x8000 * 0x7f -> 0x8000 + A1 = A0 = 0; + R5.H = (A1 += R1.H * R3.L), R5.L = (A0 += R1.H * R3.L) (IS); + DBGA ( R5.L , 0x8000 ); + DBGA ( R5.H , 0x8000 ); + + pass + + .data; +data0: + .dw 0x0001 + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/bfin/m7.s b/sim/testsuite/bfin/m7.s new file mode 100644 index 0000000..07e664e --- /dev/null +++ b/sim/testsuite/bfin/m7.s @@ -0,0 +1,66 @@ +// Test result extraction of mac instructions. +// Test basic edge values +// UNSIGNED FRACTIONAL mode into SINGLE destination register +// test ops: "+=" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80000001 +// load r1=0x80007fff +// load r2=0xf000ffff +// load r3=0x0000007f +// load r4=0x00000080 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// extraction with no saturation (truncate) +// 0x8000 * 0x7fff = 0x003fff8000 -> 0x3fff + A1 = A0 = 0; + R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L) (TFU); + DBGA ( R5.L , 0x3fff ); + DBGA ( R5.H , 0x3fff ); + +// extraction with no saturation (round) +// 0x8000 * 0x7fff = 0x003fff8000 -> 0x4000 + A1 = A0 = 0; + R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L) (FU); + DBGA ( R5.L , 0x4000 ); + DBGA ( R5.H , 0x4000 ); + +// extraction with no saturation +// 0xffff * 0xffff = 0x00fffe0001 -> 0xfffe + A1 = A0 = 0; + R5.H = (A1 += R2.L * R2.L), R5.L = (A0 += R2.L * R2.L) (FU); + DBGA ( R5.L , 0xfffe ); + DBGA ( R5.H , 0xfffe ); + +// extraction with saturation +//0x7ffffe0001 -> 0xffff + A1 = A0 = 0; + A1.x = R3.L; + A0.x = R3.L; + R5.H = (A1 += R2.L * R2.L), R5.L = (A0 += R2.L * R2.L) (FU); + DBGA ( R5.L , 0xffff ); + DBGA ( R5.H , 0xffff ); + + pass + + .data +data0: + .dw 0x0001 + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0xffff + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/bfin/m8.s b/sim/testsuite/bfin/m8.s new file mode 100644 index 0000000..fe8507f --- /dev/null +++ b/sim/testsuite/bfin/m8.s @@ -0,0 +1,54 @@ +// MAC test program. +// Test result extraction of mac instructions. +// Test basic edge values +// UNSIGNED INTEGER mode into SINGLE destination register +// test ops: "+=" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80000002 +// load r1=0x80007fff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 +// load r5=0xffffffff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + +// 0x0002 * 0x0002 = 0x0000000004 -> 0x0004 + A1 = A0 = 0; + R5.H = (A1 += R0.L * R0.L), R5.L = (A0 += R0.L * R0.L) (IU); + DBGA ( R5.L , 0x4 ); + DBGA ( R5.H , 0x4 ); + +// 0x7fff * 0x007f = 0x00003f7f81 -> 0xffff + A1 = A0 = 0; + R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IU); + R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IU); + DBGA ( R5.L , 0xffff ); + DBGA ( R5.H , 0xffff ); + + pass + + .data; +data0: + .dw 0x0002 + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 + .dw 0xffff + .dw 0xffff diff --git a/sim/testsuite/bfin/m9.s b/sim/testsuite/bfin/m9.s new file mode 100644 index 0000000..79cab4c --- /dev/null +++ b/sim/testsuite/bfin/m9.s @@ -0,0 +1,91 @@ +// Test extraction from accumulators: +// ROUND/TRUNCATE in SIGNED FRACTIONAL mode +// test ops: "+=" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x7ffef000 +// load r1=0x7ffff000 +// load r2=0x00008000 +// load r3=0x00018000 +// load r4=0x0000007f + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// round +// 0x007ffef00 -> 0x7fff + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1, R5.L = A0; + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + +// round with ovflw +// 0x007ffff00 -> 0x7fff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R5.H = A1, R5.L = A0; + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + +// trunc +// 0x007ffef00 -> 0x7ffe + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1, R5.L = A0 (T); + DBGA ( R5.L , 0x7ffe ); + DBGA ( R5.H , 0x7ffe ); + +// round with ovflw +// 0x7f7ffff00 -> 0x7fff + A1 = A0 = 0; + A1.w = R1; + A1.x = R4.L; + A0.w = R1; + A0.x = R4.L; + R5.H = A1, R5.L = A0; + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + +// round, nearest even is zero +// 0x0000008000 -> 0x0000 + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + R5.H = A1, R5.L = A0; + DBGA ( R5.L , 0x0 ); + DBGA ( R5.H , 0x0 ); + +// round, nearest even is 2 +// 0x00000018000 -> 0x0002 + A1 = A0 = 0; + A1.w = R3; + A0.w = R3; + R5.H = A1, R5.L = A0; + DBGA ( R5.L , 0x2 ); + DBGA ( R5.H , 0x2 ); + + pass + + .data +data0: + .dw 0xf000 + .dw 0x7ffe + .dw 0xf000 + .dw 0x7ffe + .dw 0x8000 + .dw 0x0000 + .dw 0x8000 + .dw 0x0001 + .dw 0x007f + .dw 0x0000 diff --git a/sim/testsuite/bfin/mac2halfreg.S b/sim/testsuite/bfin/mac2halfreg.S new file mode 100644 index 0000000..0a73dd3 --- /dev/null +++ b/sim/testsuite/bfin/mac2halfreg.S @@ -0,0 +1,27 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + r3.h=0x8000; + r2.h=0x8000; + r7=0; + r6.l=0x7f; + a0.x=r6.l; + r6.h=0x7fff; + r6.l=0xffff; + a0.w=r6; + _dbg a0; + r3.l=(a0+=r3.h*r2.h); + r7=ASTAT; + _dbg A0; + _dbg r3; + _dbg ASTAT; +//AV0 does not overflow + checkreg r7, (_VS|_V|_V_COPY); + + pass diff --git a/sim/testsuite/bfin/math.s b/sim/testsuite/bfin/math.s new file mode 100644 index 0000000..bd88f70 --- /dev/null +++ b/sim/testsuite/bfin/math.s @@ -0,0 +1,66 @@ +# Blackfin testcase for ashift +# mach: bfin + + .include "testutils.inc" + + start + + R0 = 5; + R0 += -1; + R1 = 4; + CC = R0 == R1; + if CC jump 1f; + fail +1: + + imm32 r2, 0xff901234 + r4=8; + i2=r2; + m2 = 4; + a0 = 0; + r1.l = (a0 += r4.l *r4.l) (IS) || I2 += m2 || nop; + r0 = i2; + imm32 r1, 0xff901238; + CC = r1 == r0; + if CC jump 2f; + fail +2: + + A0 = 0; + A1 = 0; + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R2.H = 0xf12e; + R2.L = 0xbeaa; + R3.L = 0x00ff; + A1.w = R2; + A1.x = R3; + R0.H = 0xd136; + R0.L = 0x459d; + R1.H = 0xabd6; + R1.L = 0x9ec7; + + R5 = A1 , A0 = R1.L * R0.L (FU); + + R0 = -1 (X); + CC = r5 == r0; + if CC jump 3f; + fail +3: + + R0.L = 0x7bb8; + R0.H = 0x8d5e; + R4.L = 0x7e1c; + R4.H = 0x9e22; + R6.H = R4.H * R0.L (M), R6.L = R4.L * R0.H (ISS2); + + imm32 r0, 0x80008000 + CC = r6 == r0; + if CC jump 4f; + fail +4: + pass diff --git a/sim/testsuite/bfin/max_min_flags.s b/sim/testsuite/bfin/max_min_flags.s new file mode 100644 index 0000000..a4ad33b --- /dev/null +++ b/sim/testsuite/bfin/max_min_flags.s @@ -0,0 +1,275 @@ +// Check Flag Settings for MAX/MIN +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + r0=1; + r1= -1; + r2=min(r1,r0); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x2); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0xffff); + dbga (r2.h, 0xffff); + + r2=min(r0,r1); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x2); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0xffff); + dbga (r2.h, 0xffff); + + r2=max(r1,r0); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x0); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x1); + dbga (r2.h, 0x0); + + r2=max(r0,r1); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x0); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x1); + dbga (r2.h, 0x0); + + r0.h=1; + r2=min(r1,r0) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x2); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0xffff); + dbga (r2.h, 0xffff); + + r2=min(r0,r1) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x2); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0xffff); + dbga (r2.h, 0xffff); + + r2=max(r1,r0) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x0); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x1); + dbga (r2.h, 0x1); + + r2=max(r0,r1) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x0); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x1); + dbga (r2.h, 0x1); + + r0=0; + r2=max(r1,r0); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x1); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 1); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x0); + dbga (r2.h, 0x0); + + r0.h=1; + r2=max(r1,r0) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x1); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 1); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x0); + dbga (r2.h, 0x1); + + pass diff --git a/sim/testsuite/bfin/mc_s2.s b/sim/testsuite/bfin/mc_s2.s new file mode 100644 index 0000000..024ee92 --- /dev/null +++ b/sim/testsuite/bfin/mc_s2.s @@ -0,0 +1,78 @@ +/* SHIFT test program. + * Test r0, r1, A0 <<= BITMUX; + */ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + +// load r0=0x90000001 +// load r1=0x90000002 +// load r2=0x00000000 +// load r3=0x00000000 +// load r4=0x20000002 +// load r5=0x00000000 + loadsym P1, data0; + +// insert two bits, both equal to 1 +// A0: 00 0000 0000 -> 00 0000 0003 +// r0: 9000 0001 -> 2000 0002 +// r1: 9000 0002 -> 2000 0004 + R0 = [ P1 + 0 ]; + R1 = [ P1 + 4 ]; + A0.w = R2; + A0.x = R3.L; + BITMUX( R0 , R1, A0) (ASL); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0003 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R0.L , 0x0002 ); + DBGA ( R0.H , 0x2000 ); + DBGA ( R1.L , 0x0004 ); + DBGA ( R1.H , 0x2000 ); + +// insert two bits, one equal to 1, other to 0 +// A0: 00 0000 0000 -> 00 0000 0001 +// r0: 9000 0001 -> 2000 0002 +// r4: 2000 0002 -> 4000 0004 + R0 = [ P1 + 0 ]; + R4 = [ P1 + 16 ]; + A0.w = R2; + A0.x = R3.L; + BITMUX( R0 , R4, A0) (ASL); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R0.L , 0x0002 ); + DBGA ( R0.H , 0x2000 ); + DBGA ( R4.L , 0x0004 ); + DBGA ( R4.H , 0x4000 ); + + pass + + .data +data0: + .dw 0x0001 + .dw 0x9000 + + .dw 0x0002 + .dw 0x9000 + + .dw 0x0000 + .dw 0x0000 + + .dw 0x0000 + .dw 0x0000 + + .dw 0x0002 + .dw 0x2000 + + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/bfin/mdma-32bit-1d-neg-count.c b/sim/testsuite/bfin/mdma-32bit-1d-neg-count.c new file mode 100644 index 0000000..e380254 --- /dev/null +++ b/sim/testsuite/bfin/mdma-32bit-1d-neg-count.c @@ -0,0 +1,18 @@ +/* Basic MDMA device tests. +# mach: bfin +# cc: -mcpu=bf537 -nostdlib -lc +# sim: --env operating --model bf537 +*/ + +#include "test.h" + +static volatile struct bfin_dma *s = (void *)MDMA_S1_NEXT_DESC_PTR; +static volatile struct bfin_dma *d = (void *)MDMA_D1_NEXT_DESC_PTR; + +#include "mdma-skel.h" + +void mdma_memcpy (bu32 dst, bu32 src, bu32 size) +{ + /* Negative transfers start at end of buffer. */ + _mdma_memcpy (dst + size - 4, src + size - 4, size, -4); +} diff --git a/sim/testsuite/bfin/mdma-32bit-1d.c b/sim/testsuite/bfin/mdma-32bit-1d.c new file mode 100644 index 0000000..acb891e --- /dev/null +++ b/sim/testsuite/bfin/mdma-32bit-1d.c @@ -0,0 +1,17 @@ +/* Basic MDMA device tests. +# mach: bfin +# cc: -mcpu=bf537 -nostdlib -lc +# sim: --env operating --model bf537 +*/ + +#include "test.h" + +static volatile struct bfin_dma *s = (void *)MDMA_S0_NEXT_DESC_PTR; +static volatile struct bfin_dma *d = (void *)MDMA_D0_NEXT_DESC_PTR; + +#include "mdma-skel.h" + +void mdma_memcpy (bu32 dst, bu32 src, bu32 size) +{ + _mdma_memcpy (dst, src, size, 4); +} diff --git a/sim/testsuite/bfin/mdma-8bit-1d-neg-count.c b/sim/testsuite/bfin/mdma-8bit-1d-neg-count.c new file mode 100644 index 0000000..26ba577 --- /dev/null +++ b/sim/testsuite/bfin/mdma-8bit-1d-neg-count.c @@ -0,0 +1,18 @@ +/* Basic MDMA device tests. +# mach: bfin +# cc: -mcpu=bf537 -nostdlib -lc +# sim: --env operating --model bf537 +*/ + +#include "test.h" + +static volatile struct bfin_dma *s = (void *)MDMA_S1_NEXT_DESC_PTR; +static volatile struct bfin_dma *d = (void *)MDMA_D1_NEXT_DESC_PTR; + +#include "mdma-skel.h" + +void mdma_memcpy (bu32 dst, bu32 src, bu32 size) +{ + /* Negative transfers start at end of buffer. */ + _mdma_memcpy (dst + size - 1, src + size - 1, size, -1); +} diff --git a/sim/testsuite/bfin/mdma-8bit-1d.c b/sim/testsuite/bfin/mdma-8bit-1d.c new file mode 100644 index 0000000..8384093 --- /dev/null +++ b/sim/testsuite/bfin/mdma-8bit-1d.c @@ -0,0 +1,17 @@ +/* Basic MDMA device tests. +# mach: bfin +# cc: -mcpu=bf537 -nostdlib -lc +# sim: --env operating --model bf537 +*/ + +#include "test.h" + +static volatile struct bfin_dma *s = (void *)MDMA_S0_NEXT_DESC_PTR; +static volatile struct bfin_dma *d = (void *)MDMA_D0_NEXT_DESC_PTR; + +#include "mdma-skel.h" + +void mdma_memcpy (bu32 dst, bu32 src, bu32 size) +{ + _mdma_memcpy (dst, src, size, 1); +} diff --git a/sim/testsuite/bfin/mdma-skel.h b/sim/testsuite/bfin/mdma-skel.h new file mode 100644 index 0000000..920eff2 --- /dev/null +++ b/sim/testsuite/bfin/mdma-skel.h @@ -0,0 +1,80 @@ +#include +#include + +void _mdma_memcpy (bu32 dst, bu32 src, bu32 size, bs16 mod) +{ + bu32 count = size >> (abs (mod) / 2); + bu16 wdsize; + switch (abs (mod)) + { + case 4: wdsize = WDSIZE_32; break; + case 2: wdsize = WDSIZE_16; break; + default: wdsize = WDSIZE_8; break; + } + + s->config = d->config = 0; + + d->irq_status = DMA_DONE | DMA_ERR; + + /* Destination */ + d->start_addr = dst; + d->x_count = count; + d->x_modify = mod; + d->irq_status = DMA_DONE | DMA_ERR; + + /* Source */ + s->start_addr = src; + s->x_count = count; + s->x_modify = mod; + s->irq_status = DMA_DONE | DMA_ERR; + + /* Enable */ + s->config = DMAEN | wdsize; + d->config = WNR | DI_EN | DMAEN | wdsize; + + while (!(d->irq_status & DMA_DONE)) + continue; +} + +void mdma_memcpy (bu32 dst, bu32 src, bu32 size); + +#ifndef MAX_LEN +#define MAX_LEN 0x40000 +#endif +bu32 _data[(MAX_LEN / 4) * 2 + 3]; +char *data = (char *)(_data + 1); + +int _start (void) +{ + char *src, *dst; + bu32 len, canary, *canaries[3]; + + canary = 0x12345678; + + len = 4; + while (len < MAX_LEN) + { + src = data; + dst = data + len + 4; + /* Set up the canaries. */ + canaries[0] = (void *)&src[-4]; + canaries[1] = (void *)&dst[-4]; + canaries[2] = (void *)&dst[len]; + *canaries[0] = *canaries[1] = *canaries[2] = canary; + + memset (src, 0xad, len); + memset (dst, 0x00, len); + + mdma_memcpy ((bu32)dst, (bu32)src, len); + if (memcmp (src, dst, len)) + DBG_FAIL; + + if (*canaries[0] != canary || + *canaries[1] != canary || + *canaries[2] != canary) + DBG_FAIL; + + len <<= 4; + } + DBG_PASS; +} diff --git a/sim/testsuite/bfin/mem3.s b/sim/testsuite/bfin/mem3.s new file mode 100644 index 0000000..da070e0 --- /dev/null +++ b/sim/testsuite/bfin/mem3.s @@ -0,0 +1,42 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0.H = 0x1234; + R0.L = 0x5678; + loadsym P0, data0; + + [ P0 ] = R0; + P1 = [ P0 ]; + _DBG P1; + R1 = [ P0 ]; + _DBG R1; + CC = R0 == R1; + IF !CC JUMP abrt; + + W [ P0 ] = R0; + R1 = W [ P0 ] (Z); + R2 = R0; + R2 <<= 16; + R2 >>= 16; + _DBG R1; + CC = R2 == R1; + IF !CC JUMP abrt; + + B [ P0 ] = R0; + R1 = B [ P0 ] (Z); + R2 = R0; + R2 <<= 24; + R2 >>= 24; + _DBG R1; + CC = R2 == R1; + IF !CC JUMP abrt; + pass +abrt: + fail; + + .data +data0: + .dd 0xDEADBEAF; diff --git a/sim/testsuite/bfin/mmr-exception.s b/sim/testsuite/bfin/mmr-exception.s new file mode 100644 index 0000000..5e9a268 --- /dev/null +++ b/sim/testsuite/bfin/mmr-exception.s @@ -0,0 +1,43 @@ +# Blackfin testcase for MMR exceptions in a lower EVT +# mach: bfin +# sim: --environment operating + + .include "testutils.inc" + + start + + imm32 P0, 0xFFE02000 + loadsym R1, _evx + [P0 + (4 * 3)] = R1; + loadsym R1, _ivg9 + [P0 + (4 * 9)] = R1; + CSYNC; + + RETI = R1; + RAISE 9; + R0 = -1; + STI R0; + RTI; + dbg_fail + +_ivg9: + # Invalid MMR + imm32 P0, 0xFFEE0000 +1: [P0] = R0; +9: dbg_fail + +_evx: + # Make sure SEQSTAT is set to correct value + R0 = SEQSTAT; + R0 = R0.B; + R1 = 0x2e (x); + CC = R0 == R1; + IF !CC JUMP 9b; + + # Make sure RETX is set to correct address + loadsym R0, 1b; + R1 = RETX; + CC = R0 == R1; + IF !CC JUMP 9b; + + dbg_pass diff --git a/sim/testsuite/bfin/move.s b/sim/testsuite/bfin/move.s new file mode 100644 index 0000000..b8f41c8 --- /dev/null +++ b/sim/testsuite/bfin/move.s @@ -0,0 +1,36 @@ +# Blackfin testcase for register move instructions +# mach: bfin + + + .include "testutils.inc" + + start + + .macro move reg0:req, reg1:req, clobber:req + imm32 \reg0, 0x5555aaaa + imm32 \reg1, 0x12345678 + imm32 \clobber, 0x12345678 + \reg0 = \reg1; + CC = \reg0 == \clobber; + if CC jump 1f; + fail +1: + .endm + + move R0, R1, R2 + move R0, R2, R3 + move R0, R2, R4 + move R0, R3, R5 + move R0, R4, R6 + move R0, R5, R7 + move R0, R6, R1 + move R0, R7, R2 + move R7, R0, R1 + move R7, R1, R2 + move R7, R2, R3 + move R7, R3, R4 + move R7, R4, R5 + move R7, R5, R6 + move R7, R6, R0 + + pass diff --git a/sim/testsuite/bfin/msa_acp_5.10.S b/sim/testsuite/bfin/msa_acp_5.10.S new file mode 100644 index 0000000..75e50e3 --- /dev/null +++ b/sim/testsuite/bfin/msa_acp_5.10.S @@ -0,0 +1,40 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + init_r_regs 0 + astat = r0; + + r1.l = 0x0; + r1.h = 0x8000; + A0.w=r1; + _dbg a1; + a0 = a0 << 8; + _dbg a0; + _dbg astat; + + + A0 = - A0; + _dbg astat; + _dbg a0; + r7 = astat; + checkreg r7, (_AV0|_AV0S); + + r1.l = 0x0; + r1.h = 0x8000; + A1.w=r1; + _dbg a0; + a1 = a1 << 8; + _dbg a1; + _dbg astat; + r7 = astat; + checkreg r7, (_AV0|_AV0S|_AN); + + A1 = - A1; + r7 = astat; + checkreg r7, (_AV1|_AV1S|_AV0|_AV0S); + _dbg astat; + _dbg a1; + pass; diff --git a/sim/testsuite/bfin/msa_acp_5.12_1.S b/sim/testsuite/bfin/msa_acp_5.12_1.S new file mode 100644 index 0000000..d65496d --- /dev/null +++ b/sim/testsuite/bfin/msa_acp_5.12_1.S @@ -0,0 +1,71 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + + init_r_regs 0; + ASTAT = r0; + + r0 = -1; + A0 = r0; + _dbg astat; + r0 +=1; + _dbg astat; + A0 = A0 (S); + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AN) + _dbg a0; + _dbg astat; + A0 = 0; + A0 = A0 (S); + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AZ) + _dbg a0; + _dbg astat; + + r0 = -1; + A1 = r0; + _dbg astat; + r0 +=1; + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AZ); + _dbg astat; + A1 = A1 (S); + r7 = astat; + _dbg astat; + checkreg r7, (_AC0|_AC0_COPY|_AN) + _dbg a1; + _dbg astat; + A1 = 0; + A1 = A1 (S); + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AZ) + _dbg a1; + _dbg astat; + + r1.l = 0x0; + r1.h = 0x8000; + a1 = r1; + a1 = a1 << 8; + _dbg a1; + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AN) + a1 = a1(s); + _dbg astat; + _dbg a1; + r7 = astat; + checkreg r7, (_AV1S|_AV1|_AC0|_AC0_COPY|_AN) + + r1.l = 0x0; + r1.h = 0x8000; + a0 = r1; + a0 = a0 << 8; + _dbg a0; + a0 = a0(s); + _dbg astat; + _dbg a0; + r7 = astat; + checkreg r7, (_AV1S|_AV1|_AV0S|_AV0|_AC0|_AC0_COPY|_AN) + pass diff --git a/sim/testsuite/bfin/msa_acp_5.12_2.S b/sim/testsuite/bfin/msa_acp_5.12_2.S new file mode 100644 index 0000000..e965ad1 --- /dev/null +++ b/sim/testsuite/bfin/msa_acp_5.12_2.S @@ -0,0 +1,58 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + r0 = 0; + ASTAT = R0; + + r0 = -1; + A0 = r0; + A1 = 0; + _dbg astat; + r0 +=1; + _dbg astat; + A1 = A1(S), A0 = A0 (S); + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AN|_AZ); + _dbg a0; + _dbg astat; + + r0.l = 0x0; + r0.h = 0x8000; + r1 = 1; + a0 = r0; + a0 = a0 << 8; + a1 = r1; + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AN); + dbga(r7.l,0x1006); + dbga(r7.h,0); + + A1 = A1(S), A0 = A0(S); + _dbg a0; + _dbg a1; + _dbg astat; + r7 = astat; + checkreg r7, (_AV0S|_AV0|_AC0|_AC0_COPY|_AN); + + r0.l = 0x0; + r0.h = 0x8000; + r1 = 0; + a1 = r0; + a1 = a1 << 8; + a0 = r1; + r7 = astat; + + A1 = A1(S), A0 = A0(S); + _dbg a0; + _dbg a1; + _dbg astat; + r7 = astat; + checkreg r7, (_AV1S|_AV1|_AV0S|_AC0|_AC0_COPY|_AN|_AZ); + dbga(r7.l,0x1007); + + dbga(r7.h,0xe); + + pass; diff --git a/sim/testsuite/bfin/msa_acp_5_10.s b/sim/testsuite/bfin/msa_acp_5_10.s new file mode 100644 index 0000000..eae4277 --- /dev/null +++ b/sim/testsuite/bfin/msa_acp_5_10.s @@ -0,0 +1,69 @@ +# mach: bfin + +.include "testutils.inc" + start + + + r1.l = 0x0; + r1.h = 0x8000; + A0.w=r1; + _dbg a1; + a0 = a0 << 8; + _dbg a0; + _dbg astat; + + A0 = - A0; + _dbg astat; + _dbg a0; + r7 = astat; + + cc = az; + r7 = cc; + dbga(r7.l, 0); + cc = an; + r7 = cc; + dbga(r7.l, 0); + cc = av0; + r7 = cc; + dbga(r7.l, 1); + cc = av0s; + r7 = cc; + dbga(r7.l, 1); + cc = av1; + r7 = cc; + dbga(r7.l, 0); + cc = av1s; + r7 = cc; + dbga(r7.l, 0); + + r1.l = 0x0; + r1.h = 0x8000; + A1.w=r1; + _dbg a0; + a1 = a1 << 8; + _dbg a1; + _dbg astat; + + A1 = - A1; + cc = az; + r7 = cc; + dbga(r7.l, 0); + cc = an; + r7 = cc; + dbga(r7.l, 0); + cc = av0; + r7 = cc; + dbga(r7.l, 1); + cc = av0s; + r7 = cc; + dbga(r7.l, 1); + cc = av1; + r7 = cc; + dbga(r7.l, 1); + cc = av1s; + r7 = cc; + dbga(r7.l, 1); + + _dbg astat; + _dbg a1; + pass diff --git a/sim/testsuite/bfin/mult.s b/sim/testsuite/bfin/mult.s new file mode 100644 index 0000000..26bb55e --- /dev/null +++ b/sim/testsuite/bfin/mult.s @@ -0,0 +1,22 @@ +# Blackfin testcase for multiply +# mach: bfin + + .include "testutils.inc" + + start + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + A0 = 0; + A1 = 0; + R0.L = 0x0400; + R1.L = 0x0010; + R2.L = ( A0 = R0.L * R1.L ) (S2RND); + R3 = 0x1 (Z); + CC = R3 == R2; + if CC jump 1f; + fail +1: + pass diff --git a/sim/testsuite/bfin/neg-2.S b/sim/testsuite/bfin/neg-2.S new file mode 100644 index 0000000..4430171 --- /dev/null +++ b/sim/testsuite/bfin/neg-2.S @@ -0,0 +1,42 @@ +# Blackfin testcase for negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x8000; + R0.L = 0x0000; + R1 = -R0; + R7 = ASTAT; + R2.H = 0x8000; + R2.L = 0x0000; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AC0 AC0_COPY */ + R3.H = HI(_AZ|_AC0|_AC0_COPY); + R3.L = LO(_AZ|_AC0|_AC0_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AN V V_COPY VS */ + R3.H = HI(_AN|_V|_V_COPY|_VS); + R3.L = LO(_AN|_V|_V_COPY|_VS); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/neg-3.S b/sim/testsuite/bfin/neg-3.S new file mode 100644 index 0000000..f1f0a2f --- /dev/null +++ b/sim/testsuite/bfin/neg-3.S @@ -0,0 +1,42 @@ +# Blackfin testcase for negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x0; + R0.L = 0x0; + R1 = -R0; + R7 = ASTAT; + R2.H = 0x0; + R2.L = 0x0; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN V V_COPY */ + R3.H = HI(_AN|_V|_V_COPY); + R3.L = LO(_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ AC0 AC0_COPY */ + R3.H = HI(_AZ|_AC0|_AC0_COPY); + R3.L = LO(_AZ|_AC0|_AC0_COPY); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/neg.S b/sim/testsuite/bfin/neg.S new file mode 100644 index 0000000..45649a1 --- /dev/null +++ b/sim/testsuite/bfin/neg.S @@ -0,0 +1,42 @@ +# Blackfin testcase for negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x1234; + R0.L = 0x5678; + R1 = -R0; + R7 = ASTAT; + R2.H = 0xedcb; + R2.L = 0xa988; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ V V_COPY AC0 AC0_COPY */ + R3.H = HI(_AZ|_V|_V_COPY|_AC0|_AC0_COPY); + R3.L = LO(_AZ|_V|_V_COPY|_AC0|_AC0_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AN */ + R3.H = HI(_AN); + R3.L = LO(_AN); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/nshift.s b/sim/testsuite/bfin/nshift.s new file mode 100644 index 0000000..f9e345b --- /dev/null +++ b/sim/testsuite/bfin/nshift.s @@ -0,0 +1,33 @@ +// ACP 5.18: Shifter uses wrong shift value +# mach: bfin + +.include "testutils.inc" + start + + + r0=0; + r0.h=0x8000; + r1=0x20 (z); + r0 >>>= r1; + dbga (r0.h, 0xffff); + dbga (r0.l, 0xffff); + + r0=0; + r0.h=0x7fff; + r0 >>>= r1; + dbga (r0.h, 0x0000); + dbga (r0.l, 0x0000); + + r0.l=0xffff; + r0.h=0xffff; + r0 >>= r1; + dbga (r0.h, 0x0000); + dbga (r0.l, 0x0000); + + r0.l=0xffff; + r0.h=0xffff; + r0 <<= r1; + dbga (r0.h, 0x0000); + dbga (r0.l, 0x0000); + + pass; diff --git a/sim/testsuite/bfin/pr.s b/sim/testsuite/bfin/pr.s new file mode 100644 index 0000000..d290184 --- /dev/null +++ b/sim/testsuite/bfin/pr.s @@ -0,0 +1,81 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym R3, foo; + I1 = R3; + + R4 = 0x10 + R4 = R4 + R3; + P0 = R4; + + R4 = 0x14; + R4 = R4 + R3; + I0 = R4; + + r0 = 0x22; + loadsym P1, bar; + + [i0] = r0; + [i1] = r0; + +doItAgain: + + p2 = 4; + r5=0; + + LSETUP ( lstart , lend) LC0 = P2; +lstart: + + MNOP || R2 = [ I0 ++ ] || R1 = [ I1 ++ ]; + CC = R1 == R2; + IF CC JUMP lend; + R1 = [ P1 + 0x0 ]; + R1 = R1 + R0; + [ P1 + 0x0 ] = R1; + +lend: + NOP; + + if !cc jump _halt0; + cc = r5 == 0; + if !cc jump _halt0; + + r4=1; + r5=r5+r4; + r1=i0; + R4 = 0x24; + R4 = R3 + R4 + CC = R1 == R4 + if !CC JUMP _fail; + + i2=i0; + r2=0x1234; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + jump doItAgain; + +_halt0: + r0=i0; + R4 = 0x34; + R4 = R4 + R3; + CC = R0 == R4; + IF !CC JUMP _fail; + + pass; + +_fail: + fail; + + .data +foo: + .space (0x100); + +bar: + .space (0x1000); diff --git a/sim/testsuite/bfin/push-pop-multiple.s b/sim/testsuite/bfin/push-pop-multiple.s new file mode 100644 index 0000000..2a2b356 --- /dev/null +++ b/sim/testsuite/bfin/push-pop-multiple.s @@ -0,0 +1,169 @@ +# Blackfin testcase for push/pop multiples instructions +# mach: bfin + + .include "testutils.inc" + + # Tests follow the pattern: + # - do the push multiple + # - write a garbage value to all registers pushed + # - do the pop multiple + # - check all registers popped against known values + + start + + # Repeat the same operation multiple times, so this: + # do_x moo, R, 1 + # becomes this: + # moo R1, 0x11111111 + # moo R0, 0x00000000 + .macro _do_x func:req, reg:req, max:req, x:req + .ifle (\max - \x) + \func \reg\()\x, 0x\x\x\x\x\x\x\x\x + .endif + .endm + .macro do_x func:req, reg:req, max:req + .ifc \reg, R + _do_x \func, \reg, \max, 7 + _do_x \func, \reg, \max, 6 + .endif + _do_x \func, \reg, \max, 5 + _do_x \func, \reg, \max, 4 + _do_x \func, \reg, \max, 3 + _do_x \func, \reg, \max, 2 + _do_x \func, \reg, \max, 1 + _do_x \func, \reg, \max, 0 + .endm + + # Keep the garbage value in I0 + .macro loadi reg:req, val:req + \reg = I0; + .endm + imm32 I0, 0xAABCDEFF + + # + # Test push/pop multiples with (R7:x) syntax + # + + _push_r_tests: + + # initialize all Rx regs with a known value + do_x imm32, R, 0 + + .macro checkr tochk:req, val:req + P0 = \tochk; + imm32 P1, \val + CC = P0 == P1; + IF !CC JUMP 8f; + .endm + + .macro pushr maxr:req + _push_r\maxr: + [--SP] = (R7:\maxr); + do_x loadi, R, \maxr + (R7:\maxr) = [SP++]; + do_x checkr, R, \maxr + # need to do a long jump to avoid PCREL issues + jump 9f; + 8: jump.l 1f; + 9: + .endm + + pushr 7 + pushr 6 + pushr 5 + pushr 4 + pushr 3 + pushr 2 + pushr 1 + pushr 0 + + # + # Test push/pop multiples with (P5:x) syntax + # + + _push_p_tests: + + # initialize all Px regs with a known value + do_x imm32, P, 0 + + .macro checkp tochk:req, val:req + R0 = \tochk; + imm32 R1, \val + CC = R0 == R1; + IF !CC JUMP 8f; + .endm + + .macro pushp maxp:req + _push_p\maxp: + [--SP] = (P5:\maxp); + do_x loadi, P, \maxp + (P5:\maxp) = [SP++]; + do_x checkp, P, \maxp + # need to do a long jump to avoid PCREL issues + jump 9f; + 8: jump.l 1f; + 9: + .endm + + # checkp func clobbers R0/R1 + L0 = R0; + L1 = R1; + pushp 5 + pushp 4 + pushp 3 + pushp 2 + pushp 1 + pushp 0 + R0 = L0; + R1 = L1; + + # + # Test push/pop multiples with (R7:x, P5:x) syntax + # + + _push_rp_tests: + + .macro _pushrp maxr:req, maxp:req + _push_r\maxr\()_p\maxp: + [--SP] = (R7:\maxr, P5:\maxp); + do_x loadi, R, \maxr + do_x loadi, P, \maxp + (R7:\maxr, P5:\maxp) = [SP++]; + # checkr func clobbers P0/P1 + L0 = P0; + L1 = P1; + do_x checkr, R, \maxr + P1 = L1; + P0 = L0; + # checkp func clobbers R0/R1 + L0 = R0; + L1 = R1; + do_x checkp, P, \maxp + R0 = L0; + R1 = L1; + # need to do a long jump to avoid PCREL issues + jump 9f; + 8: jump.l 1f; + 9: + .endm + .macro pushrp maxr:req + _pushrp \maxr, 5 + _pushrp \maxr, 4 + _pushrp \maxr, 3 + _pushrp \maxr, 2 + _pushrp \maxr, 1 + _pushrp \maxr, 0 + .endm + + pushrp 7 + pushrp 6 + pushrp 5 + pushrp 4 + pushrp 3 + pushrp 2 + pushrp 1 + pushrp 0 + + pass +1: + fail diff --git a/sim/testsuite/bfin/push-pop.s b/sim/testsuite/bfin/push-pop.s new file mode 100644 index 0000000..bd6eda8 --- /dev/null +++ b/sim/testsuite/bfin/push-pop.s @@ -0,0 +1,95 @@ +# Blackfin testcase for push/pop instructions +# mach: bfin + + .include "testutils.inc" + + start + + # This uses R0/R1 as scratch ... assume those work fine in general + .macro check loader:req, reg:req + \loader \reg, 0x12345678 + [--SP] = \reg; + R0 = [SP]; + R1 = \reg; + CC = R0 == R1; + IF !CC JUMP 8f; + \loader \reg, 0x87654321 + \reg = [SP++]; + CC = R0 == R1; + IF !CC JUMP 8f; + # need to do a long jump to avoid PCREL issues + jump 9f; + 8: jump 1f; + 9: + .endm + .macro imm_check reg:req + check imm32, \reg + .endm + .macro dmm_check reg:req + check dmm32, \reg + .endm + + imm_check R2 + imm_check R3 + imm_check R4 + imm_check R5 + imm_check R6 + imm_check R7 + imm_check P0 + imm_check P1 + imm_check P2 + imm_check P3 + imm_check P4 + imm_check P5 + imm_check FP + imm_check I0 + imm_check I1 + imm_check I2 + imm_check I3 + imm_check M0 + imm_check M1 + imm_check M2 + imm_check M3 + imm_check B0 + imm_check B1 + imm_check B2 + imm_check B3 + imm_check L0 + imm_check L1 + imm_check L2 + imm_check L3 + dmm_check A0.X + dmm_check A0.W + dmm_check A1.X + dmm_check A1.W + dmm_check LC0 + dmm_check LC1 + # Make sure the top/bottom regs have bit 1 set + dmm_check LT0 + dmm_check LT1 + dmm_check LB0 + dmm_check LB1 + dmm_check RETS + + # These require supervisor resources +.ifndef BFIN_HOST + dmm_check RETI + dmm_check RETX + dmm_check RETN + # RETE likes to change on the fly with an ICE + # dmm_check RETE + # CYCLES can be user mode, but screws kernel + dmm_check CYCLES + dmm_check CYCLES2 + dmm_check USP + + # No one pushes/pops these +# dmm_check EMUDAT + dmm_check SEQSTAT + dmm_check SYSCFG +.endif + dmm_check ASTAT + + pass +1: + fail diff --git a/sim/testsuite/bfin/pushpopreg_1.s b/sim/testsuite/bfin/pushpopreg_1.s new file mode 100644 index 0000000..5bf4aa6 --- /dev/null +++ b/sim/testsuite/bfin/pushpopreg_1.s @@ -0,0 +1,292 @@ +# mach: bfin + +.include "testutils.inc" + start + + + r0.l = 0x1111; + r0.h = 0x0011; + r1.l = 0x2222; + r1.h = 0x0022; + r2.l = 0x3333; + r2.h = 0x0033; + r3.l = 0x4444; + r3.h = 0x0044; + r4.l = 0x5555; + r4.h = 0x0055; + r5.l = 0x6666; + r5.h = 0x0066; + r6.l = 0x7777; + r6.h = 0x0077; + r7.l = 0x8888; + r7.h = 0x0088; + p1.l = 0x5a5a; + p1.h = 0x005a; + p2.l = 0x6363; + p2.h = 0x0063; + p3.l = 0x7777; + p3.h = 0x0077; + p4.l = 0x7878; + p4.h = 0x0078; + p5.l = 0x3e3e; + p5.h = 0x003e; + sp = 0x4000(x); + + jump.s prog_start; + + nop; + nop; // ADD reg update to roll back + nop; + +prog_start: + nop; + [--sp] = r0; + [--sp] = r1; + [--sp] = r2; + [--sp] = r3; + [--sp] = r4; + [--sp] = r5; + [--sp] = r6; + [--sp] = r7; + [--sp] = p0; + [--sp] = p1; + [--sp] = p2; + [--sp] = p3; + [--sp] = p4; + [--sp] = p5; + + nop; + nop; + nop; + nop; + r0.l = 0xdead; + r0.h = 0xdead; + r1.l = 0xdead; + r1.h = 0xdead; + r2.l = 0xdead; + r2.h = 0xdead; + r3.l = 0xdead; + r3.h = 0xdead; + r4.l = 0xdead; + r4.h = 0xdead; + r5.l = 0xdead; + r5.h = 0xdead; + r6.l = 0xdead; + r6.h = 0xdead; + r7.l = 0xdead; + r7.h = 0xdead; + p1.l = 0xdead; + p1.h = 0xdead; + p2.l = 0xdead; + p2.h = 0xdead; + p3.l = 0xdead; + p3.h = 0xdead; + p4.l = 0xdead; + p4.h = 0xdead; + p5.l = 0xdead; + p5.h = 0xdead; + nop; + nop; + nop; + r0 = [sp++]; + r1 = [sp++]; + r2 = [sp++]; + r3 = [sp++]; + r4 = [sp++]; + r5 = [sp++]; + r6 = [sp++]; + r7 = [sp++]; + p0 = [sp++]; + p1 = [sp++]; + p2 = [sp++]; + p3 = [sp++]; + p4 = [sp++]; + p5 = [sp++]; + + nop; + nop; + nop; + nop; + nop; + nop; + nop; +_tp1: + nop; + nop; + nop; + nop; + nop; + nop; + nop; + [--sp] = r0; + [--sp] = r1; + [--sp] = r2; + [--sp] = r3; + [--sp] = r4; + [--sp] = r5; + [--sp] = r6; + [--sp] = r7; + [--sp] = p0; + [--sp] = p1; + [--sp] = p2; + [--sp] = p3; + [--sp] = p4; + [--sp] = p5; + + nop; + nop; + nop; + nop; + r0.l = 0xdead; + r0.h = 0xdead; + r1.l = 0xdead; + r1.h = 0xdead; + r2.l = 0xdead; + r2.h = 0xdead; + r3.l = 0xdead; + r3.h = 0xdead; + r4.l = 0xdead; + r4.h = 0xdead; + r5.l = 0xdead; + r5.h = 0xdead; + r6.l = 0xdead; + r6.h = 0xdead; + r7.l = 0xdead; + r7.h = 0xdead; + p1.l = 0xdead; + p1.h = 0xdead; + p2.l = 0xdead; + p2.h = 0xdead; + p3.l = 0xdead; + p3.h = 0xdead; + p4.l = 0xdead; + p4.h = 0xdead; + p5.l = 0xdead; + p5.h = 0xdead; + nop; + nop; + nop; + r0 = [sp++]; + r1 = [sp++]; + r2 = [sp++]; + r3 = [sp++]; + r4 = [sp++]; + r5 = [sp++]; + r6 = [sp++]; + r7 = [sp++]; + p0 = [sp++]; + p1 = [sp++]; + a0.x = [sp++]; + + a1.w = r0; //preserve r0 + + r0 = a0.x; + DBGA(r0.l,0x0063); + + a0.w = [sp++]; + r0 = a0.w; + DBGA(r0.l,0x7777); + DBGA(r0.h,0x0077); + + a0 = a1; //perserver r0, still + + a1.x = [sp++]; + r0 = a1.x; + DBGA(r0.l,0x0078); + + a1.w = [sp++]; + r0 = a1.w; + DBGA(r0.l,0x3e3e); + DBGA(r0.h,0x003e); + + r0 = a0.w; //restore r0 + + nop; + nop; + nop; + nop; + nop; + nop; + nop; +_tp2: + nop; + nop; + nop; + [--sp] = r0; + [--sp] = r1; + [--sp] = r2; + [--sp] = r3; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + [--sp] = p0; + [--sp] = p1; + [--sp] = p2; + [--sp] = p3; + [--sp] = p4; + [--sp] = p5; + + nop; + nop; + nop; + nop; + r0.l = 0xdead; + r0.h = 0xdead; + r1.l = 0xdead; + r1.h = 0xdead; + r2.l = 0xdead; + r2.h = 0xdead; + r3.l = 0xdead; + r3.h = 0xdead; + r4.l = 0xdead; + r4.h = 0xdead; + r5.l = 0xdead; + r5.h = 0xdead; + r6.l = 0xdead; + r6.h = 0xdead; + r7.l = 0xdead; + r7.h = 0xdead; + p1.l = 0xdead; + p1.h = 0xdead; + p2.l = 0xdead; + p2.h = 0xdead; + p3.l = 0xdead; + p3.h = 0xdead; + p4.l = 0xdead; + p4.h = 0xdead; + p5.l = 0xdead; + p5.h = 0xdead; + nop; + nop; + nop; + r0 = [sp++]; + r1 = [sp++]; + r2 = [sp++]; + r3 = [sp++]; + r4 = [sp++]; + r5 = [sp++]; + r6 = [sp++]; + r7 = [sp++]; + p0 = [sp++]; + p1 = [sp++]; + p2 = [sp++]; + p3 = [sp++]; + p4 = [sp++]; + p5 = [sp++]; + + nop; + nop; + nop; + nop; + nop; + nop; + nop; +_tp3: + nop; + nop; + nop; + nop; + nop; +_halt: + pass; diff --git a/sim/testsuite/bfin/quadaddsub.s b/sim/testsuite/bfin/quadaddsub.s new file mode 100644 index 0000000..1502179 --- /dev/null +++ b/sim/testsuite/bfin/quadaddsub.s @@ -0,0 +1,58 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R6.L = 32767; + R6.H = 2768; + R1.L = 2767; + R1.H = 2768; + + r7=0; + astat = r7; + r3 = r6 -|- r1; + _DBG r3; + _DBG ASTAT; + r7=ASTAT; + _DBG R7; + DBGA (R7.H, 0x0); + DBGA (R7.L, 0x3005); + + r7=0; + astat=r7; + r2 = r6 +|+ r1; + _DBG r2; + _DBG ASTAT; + r7=ASTAT; + _DBG R7; + DBGA (R7.H, 0x0300); + DBGA (R7.L, 0x000a); + + r7=0; + astat=r7; + r2 = r6 +|+ r1, r3 = r6 -|- r1; + + _DBG r2; + _DBG r3; + _DBG ASTAT; + + R7 = ASTAT; + _DBG R7; + DBGA (R7.H, 0x0300); + DBGA (R7.L, 0x000b); + + r7=0; + astat=r7; + r2 = r6 +|- r1, r3 = r6 -|+ r1; + + _DBG r2; + _DBG r3; + _DBG ASTAT; + + R7 = ASTAT; + _DBG R7; + DBGA (R7.H, 0x0300); + DBGA (R7.L, 0x000b); + + pass diff --git a/sim/testsuite/bfin/random_0001.s b/sim/testsuite/bfin/random_0001.s new file mode 100644 index 0000000..3cc946f --- /dev/null +++ b/sim/testsuite/bfin/random_0001.s @@ -0,0 +1,13 @@ +# Test for saturation behavior with fract multiplication +# mach: bfin + +.include "testutils.inc" + + start + + dmm32 A0.w, 0x45c1969f; + dmm32 A0.x, 0x00000000; + R4 = A0 (IU); + checkreg R4, 0x45c1969f; + + pass diff --git a/sim/testsuite/bfin/random_0002.S b/sim/testsuite/bfin/random_0002.S new file mode 100644 index 0000000..3567ae0 --- /dev/null +++ b/sim/testsuite/bfin/random_0002.S @@ -0,0 +1,25 @@ +# Test for ASTAT V overflows with dsp mult insns +# mach: bfin + +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x54604e00 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY); + imm32 R1, 0x47f491c5; + imm32 R3, 0xfe4cfc98; + imm32 R7, 0x77aa2b21; + R3.L = R7.H * R1.H (IU); + checkreg R3, 0xfe4cffff; + checkreg ASTAT, (0x54604e00 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x10f00200 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AN); + imm32 R0, 0x24f45737; + imm32 R1, 0x6752f56b; + imm32 R4, 0x3f939925; + R4.H = R0.L * R1.H (IS); + checkreg R4, 0x7fff9925; + checkreg ASTAT, (0x10f00200 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0003.S b/sim/testsuite/bfin/random_0003.S new file mode 100644 index 0000000..d9852f2 --- /dev/null +++ b/sim/testsuite/bfin/random_0003.S @@ -0,0 +1,48 @@ +# Test for ASTAT AN setting when overflows occur +# mach: bfin + +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x18204a80 | _AV1S | _AV0 | _AQ | _CC | _AC0_COPY | _AN | _AZ); + dmm32 A1.w, 0x1098e30b; + dmm32 A1.x, 0x0000001f; + imm32 R0, 0x440ed6ae; + imm32 R5, 0x3272c296; + R0.H = (A1 += R0.L * R5.H); + checkreg R0, 0x7fffd6ae; + checkreg A1.w, 0x00500e03; + checkreg A1.x, 0x0000001f; + checkreg ASTAT, (0x18204a80 | _VS | _V | _AV1S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x28c08e90 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN); + dmm32 A0.w, 0xb9da9f02; + dmm32 A0.x, 0x00000010; + imm32 R0, 0xc104b252; + R0.L = A0 (IS); + checkreg R0, 0xc1047fff; + checkreg ASTAT, (0x28c08e90 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x3cc04000 | _AV0S | _AV0 | _CC | _AC0_COPY | _AZ); + dmm32 A0.w, 0x2cc20f30; + dmm32 A0.x, 0xffffffd0; + imm32 R2, 0x367adfeb; + imm32 R5, 0x53eeff3c; + A0 += R5.H * R2.H (IS); + checkreg A0.w, 0x3e9e429c; + checkreg A0.x, 0xffffffd0; + checkreg ASTAT, (0x3cc04000 | _AV0S | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x18c0ca90 | _V | _AV1S | _AV1 | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ); + dmm32 A1.w, 0x0614ca96; + dmm32 A1.x, 0x00000053; + imm32 R3, 0x6c490457; + R3 = (A1 -= R3.L * R3.L) (M, S2RND); + checkreg R3, 0x7fffffff; + checkreg A1.w, 0x0601f505; + checkreg A1.x, 0x00000053; + checkreg ASTAT, (0x18c0ca90 | _VS | _V | _AV1S | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ); + + pass diff --git a/sim/testsuite/bfin/random_0004.S b/sim/testsuite/bfin/random_0004.S new file mode 100644 index 0000000..fddabbc --- /dev/null +++ b/sim/testsuite/bfin/random_0004.S @@ -0,0 +1,33 @@ +# Test for ASTAT bits being written when they shouldn't (only a reg mov) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x1c304e90 | _VS | _V | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x74d5f9df; + dmm32 A0.x, 0x0000005e; + imm32 R4, 0x00b47e9b; + R4 = A0; + checkreg R4, 0x7fffffff; + checkreg ASTAT, (0x1c304e90 | _VS | _V | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x6cd08a00 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _AN | _AZ); + dmm32 A1.w, 0x124e2817; + dmm32 A1.x, 0x00000011; + imm32 R2, 0x545a7c91; + R2.H = A1; + checkreg R2, 0x7fff7c91; + checkreg ASTAT, (0x6cd08a00 | _VS | _V | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x60700280 | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN); + dmm32 A0.w, 0x02184a1c; + dmm32 A0.x, 0xffffffc0; + imm32 R5, 0x60dc408a; + R5.L = A0 (IS); + checkreg R5, 0x60dc8000; + checkreg ASTAT, (0x60700280 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0005.S b/sim/testsuite/bfin/random_0005.S new file mode 100644 index 0000000..8980dfe --- /dev/null +++ b/sim/testsuite/bfin/random_0005.S @@ -0,0 +1,24 @@ +# Test for ASTAT AZ bit update with 16 bit add and sub insns +# mach: bfin + +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x10a04e10 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY); + imm32 R3, 0x05fd7405; + imm32 R7, 0x7fff7fff; + R3.H = R7.L - R7.H (NS); + checkreg R3, 0x00007405; + checkreg ASTAT, (0x10a04e10 | _VS | _AV1S | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x64200e10 | _VS | _AV0S | _AC1 | _AC0 | _AZ); + imm32 R1, 0x2c388489; + imm32 R3, 0x38f39dcc; + imm32 R5, 0x27ed8efa; + R3.H = R1.L + R5.L (NS); + checkreg R3, 0x13839dcc; + checkreg ASTAT, (0x64200e10 | _VS | _V | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + pass diff --git a/sim/testsuite/bfin/random_0006.S b/sim/testsuite/bfin/random_0006.S new file mode 100644 index 0000000..bafe19a --- /dev/null +++ b/sim/testsuite/bfin/random_0006.S @@ -0,0 +1,23 @@ +# Test BYTEOP[123]P behavior when source reg pairs match +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + imm32 R0, (0x18204e10 | _VS | _AV1S | _AV0S | _AC1 | _CC); ASTAT = R0; + imm32 R1, 0x05b931c4; + imm32 R4, 0x05f205f2; + R4 = BYTEOP1P (R1:0, R1:0) (T, R); + + imm32 R0, (0x3470cc10 | _VS | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); ASTAT = R0; + imm32 R1, 0x00000000; + imm32 R6, 0x0000007f; + R6 = BYTEOP2P (R1:0, R1:0) (RNDH); + + imm32 R0, (0x1c708c90 | _VS | _V | _AV1S | _AC0 | _V_COPY | _AC0_COPY | _AN); ASTAT = R0; + imm32 R0, 0x3e2a80ca; + imm32 R1, 0x20dec740; + R0 = BYTEOP3P (R1:0, R1:0) (LO); + + pass diff --git a/sim/testsuite/bfin/random_0007.S b/sim/testsuite/bfin/random_0007.S new file mode 100644 index 0000000..eb98e07 --- /dev/null +++ b/sim/testsuite/bfin/random_0007.S @@ -0,0 +1,60 @@ +# Make sure the acc regs are updated even when the search criteria is not met +# (this implicitly affects the top 8 bits) +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x08e00690 | _VS | _AC1 | _AN); + dmm32 A0.w, 0x42357aea; + dmm32 A0.x, 0x00000001; + dmm32 A1.w, 0x3a3f0000; + dmm32 A1.x, 0x00000000; + imm32 P0, 0x7119f94d; + imm32 R4, 0xcdeea690; + imm32 R5, 0xffb58000; + imm32 R6, 0x72252b1e; + (R4, R5) = SEARCH R6 (GE); + checkreg R4, 0x7119f94d; + checkreg A0.w, 0x00007aea; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0x00007225; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x08e00690 | _VS | _AC1 | _AN); + + dmm32 ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x4193c6bc; + dmm32 A0.x, 0xffffffd4; + dmm32 A1.w, 0xa97e7452; + dmm32 A1.x, 0xffffffff; + imm32 P0, 0x51e152a5; + imm32 R1, 0x36deeb9a; + imm32 R5, 0x386ab3f7; + imm32 R7, 0x2a3d5114; + (R5, R1) = SEARCH R7 (GT); + checkreg R1, 0x51e152a5; + checkreg A0.w, 0x00005114; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0x00007452; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x4193c6bc; + dmm32 A0.x, 0xffffffd4; + dmm32 A1.w, 0x0000ffff; + dmm32 A1.x, 0x00000000; + imm32 P0, 0x51e152a5; + imm32 R1, 0x36deeb9a; + imm32 R5, 0x386ab3f7; + imm32 R7, 0xFa3d5114; + (R5, R1) = SEARCH R7 (GT); + checkreg R1, 0x51e152a5; + checkreg A0.w, 0x00005114; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + pass diff --git a/sim/testsuite/bfin/random_0008.S b/sim/testsuite/bfin/random_0008.S new file mode 100644 index 0000000..d856b0c --- /dev/null +++ b/sim/testsuite/bfin/random_0008.S @@ -0,0 +1,44 @@ +# check ASTAT ac/av flags are handled correctly when doing Acc = -Acc +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x5020ca80 | _VS | _AV1S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0x549e07b3; + dmm32 A1.x, 0x0000002a; + A1 = -A1; + checkreg A1.w, 0xab61f84d; + checkreg A1.x, 0xffffffd5; + checkreg ASTAT, (0x5020ca80 | _VS | _AV1S | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x48908a10 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AN); + dmm32 A0.w, 0x3c57e100; + dmm32 A0.x, 0xfffffff2; + dmm32 A1.w, 0xfb63b8a0; + dmm32 A1.x, 0xffffffff; + A1 = -A0; + checkreg A1.w, 0xc3a81f00; + checkreg A1.x, 0x0000000d; + checkreg ASTAT, (0x48908a10 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY); + + dmm32 ASTAT, (0x10900880 | _V | _AC0 | _CC | _AC0_COPY); + dmm32 A0.w, 0x4ca147ce; + dmm32 A0.x, 0xffffff9d; + dmm32 A1.w, 0x0e2534b9; + dmm32 A1.x, 0xffffff85; + A0 = -A1; + checkreg A0.w, 0xf1dacb47; + checkreg A0.x, 0x0000007a; + checkreg ASTAT, (0x10900880 | _V | _CC); + + dmm32 ASTAT, (0x34904e90 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x7826f07d; + dmm32 A0.x, 0xffffffc2; + A0 = -A0; + checkreg A0.w, 0x87d90f83; + checkreg A0.x, 0x0000003d; + checkreg ASTAT, (0x34904e90 | _VS | _V | _AV1S | _AC1 | _V_COPY); + + pass diff --git a/sim/testsuite/bfin/random_0009.S b/sim/testsuite/bfin/random_0009.S new file mode 100644 index 0000000..6b3960a --- /dev/null +++ b/sim/testsuite/bfin/random_0009.S @@ -0,0 +1,103 @@ +# Verify ASTAT bits are set correctly during dsp mac insns +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x16ba2677; + dmm32 A0.x, 0x00000000; + imm32 R4, 0x80007fff; + A0 -= R4.H * R4.H (W32); + checkreg A0.w, 0x96ba2678; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x3c30c800 | _VS | _AV0S | _AC1 | _CC); + dmm32 A0.w, 0xf170d0c7; + dmm32 A0.x, 0xffffffff; + imm32 R2, 0x80008000; + A0 -= R2.H * R2.L (W32); + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x3c30c800 | _VS | _AV0S | _AV0 | _AC1 | _CC); + + dmm32 ASTAT, (0x6c200880 | _VS | _AV1S | _AC1 | _AC0 | _CC | _AN); + dmm32 A0.x, 0x560a1c52; + dmm32 A0.x, 0xffffffbb; + imm32 R5, 0x8000ffff; + A0 = R5.H * R5.H (W32); + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x6c200880 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _AN); + + dmm32 ASTAT, (0x58908a90 | _VS | _AC1 | _AC0 | _AQ); + dmm32 A0.w, 0x00c5a4e0; + dmm32 A0.x, 0x00000000; + imm32 R0, 0xffffb33a; + imm32 R2, 0xffffb33a; + imm32 R3, 0xb33a4cc6; + R2 = (A0 -= R0.L * R3.H) (FU); + checkreg R2, 0x00000000; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x58908a90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x2cc00c90 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY); + dmm32 A0.w, 0x00a38000; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x2aa2ffff; + imm32 R1, 0xff5c711e; + imm32 R4, 0x2913dc90; + R0 = (A0 -= R4.L * R1.L) (IU); + checkreg R0, 0x00000000; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x2cc00c90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x3880c280 | _VS | _AC1 | _AZ); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R4, 0x139ad315; + imm32 R6, 0x7fff0000; + R4.L = (A0 -= R6.H * R6.H) (FU); + checkreg R4, 0x139a0000; + checkreg ASTAT, (0x3880c280 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AZ); + + dmm32 ASTAT, (0x48408290 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0x6b426a69; + dmm32 A0.x, 0xffffffba; + imm32 R0, 0x24038000; + imm32 R2, 0xf62c7780; + imm32 R3, 0x5a64f8e8; + R2.L = (A0 -= R3.L * R0.L) (IH); + checkreg R2, 0xf62c8000; + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x48408290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x7c00c210 | _VS | _AC1 | _AN); + dmm32 A1.w, 0x730173e9; + dmm32 A1.x, 0xffffffae; + imm32 R4, 0x8000ffff; + imm32 R5, 0x738559e8; + R5.H = (A1 -= R4.L * R5.L) (M, IH); + checkreg R5, 0x800059e8; + checkreg A1.w, 0x80000000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x7c00c210 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY | _AN); + + dmm32 ASTAT, (0x4830c400 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AZ); + dmm32 A0.w, 0x033a05f0; + dmm32 A0.x, 0x00000000; + imm32 R3, 0x5992dd5a; + imm32 R4, 0x098a889e; + imm32 R6, 0x8000de08; + R6.L = (A0 -= R4.L * R3.H) (TFU); + checkreg R6, 0x80000000; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x4830c400 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _CC | _V_COPY | _AZ); + + pass diff --git a/sim/testsuite/bfin/random_0010.S b/sim/testsuite/bfin/random_0010.S new file mode 100644 index 0000000..c434edb --- /dev/null +++ b/sim/testsuite/bfin/random_0010.S @@ -0,0 +1,78 @@ +# Test logical left shift (vector) insns with larger shift values +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x30400e90 | _VS | _AV0S | _AC1 | _AQ | _AN); + imm32 R5, 0xb0b40000; + imm32 R6, 0xf43a5d3c; + R6 = R5 << 0x19 (V, S); + checkreg R6, 0xff610000; + checkreg ASTAT, (0x30400e90 | _VS | _AV0S | _AC1 | _AQ | _AN | _AZ); + + dmm32 ASTAT, (0x34104410 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN); + imm32 R2, 0xff2abd08; + imm32 R5, 0xf610ffff; + R2 = R5 << 0x11 (V, S); + checkreg R2, 0xffffffff; + checkreg ASTAT, (0x34104410 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN); + + dmm32 ASTAT, (0x6cd0c680 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + imm32 R0, 0x760ecf8e; + imm32 R1, 0x3f5c8af5; + R0 = R1 << 0x17 (V, S); + checkreg R0, 0x001fffc5; + checkreg ASTAT, (0x6cd0c680 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x44a04280 | _AV1S | _AV1 | _AC1 | _AC0 | _CC); + imm32 R4, 0x520cb3d4; + imm32 R6, 0x67141e28; + R6 = R4 << 0x14 (V, S); + checkreg R6, 0x0005fffb; + checkreg ASTAT, (0x44a04280 | _AV1S | _AV1 | _AC1 | _AC0 | _CC | _AN); + + dmm32 ASTAT, (0x14600c10 | _VS | _AV1S | _AC1 | _AC0 | _AN); + imm32 R3, 0x40407f7e; + imm32 R4, 0xc081e040; + R3 = R4 << 0x1a (V, S); + checkreg R3, 0xff02ff81; + checkreg ASTAT, (0x14600c10 | _VS | _AV1S | _AC1 | _AC0 | _AN); + + dmm32 ASTAT, (0x04f00490 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY); + imm32 R5, 0x63654235; + imm32 R7, 0x00008000; + R5 = R7 << 0x18 (V, S); + checkreg R5, 0x0000ff80; + checkreg ASTAT, (0x04f00490 | _VS | _AV0S | _AC1 | _AQ | _AN | _AZ); + + dmm32 ASTAT, (0x3830ca90 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AN); + imm32 R1, 0x40000000; + imm32 R2, 0x7fffffff; + R1 = R2 << 0x16 (V, S); + checkreg R1, 0x001fffff; + checkreg ASTAT, (0x3830ca90 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN); + + dmm32 ASTAT, (0x24e08890 | _VS | _AV0S | _AC1 | _CC | _AN | _AZ); + imm32 R2, 0xfffe0000; + imm32 R3, 0xd9d90000; + R2 = R3 << 0x19 (V, S); + checkreg R2, 0xffb30000; + checkreg ASTAT, (0x24e08890 | _VS | _AV0S | _AC1 | _CC | _AN | _AZ); + + dmm32 ASTAT, (0x30f0c200 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AZ); + imm32 R0, 0x32590000; + imm32 R2, 0x708bb53f; + R0 = R2 << 0x1c (V, S); + checkreg R0, 0x0708fb53; + checkreg ASTAT, (0x30f0c200 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x4cc00080 | _VS | _V | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN); + imm32 R3, 0x3563cfa3; + imm32 R7, 0x027e2255; + R7 = R3 << 0x1f (V, S); + checkreg R7, 0x1ab1e7d1; + checkreg ASTAT, (0x4cc00080 | _VS | _AC1 | _AQ | _AC0_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0011.S b/sim/testsuite/bfin/random_0011.S new file mode 100644 index 0000000..0b0ccac --- /dev/null +++ b/sim/testsuite/bfin/random_0011.S @@ -0,0 +1,102 @@ +# test acc shifts larger than they should be, and ASTAT flags +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x7cc0c090 | _VS | _V | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ); + dmm32 A0.w, 0x1890bdbc; + dmm32 A0.x, 0x00000079; + A0 = A0 << 0x2; + checkreg A0.w, 0x6242f6f0; + checkreg A0.x, 0xffffffe4; + checkreg ASTAT, (0x7cc0c090 | _VS | _V | _AC1 | _AQ | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x50508600 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0x02fe375e; + dmm32 A1.x, 0x00000000; + A1 = A1 >> 0x21; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0xffffffaf; + checkreg ASTAT, (0x50508600 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x7c800a10 | _VS | _AV0S | _AV0 | _AC1); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + A0 = A0 << 0x1f; + checkreg ASTAT, (0x7c800a10 | _VS | _AV0S | _AC1 | _AZ); + + dmm32 ASTAT, (0x4440c080 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x2e4b0bba; + dmm32 A0.x, 0xffffff8c; + A0 = A0 >> 0x25; + checkreg A0.w, 0xd0000000; + checkreg A0.x, 0x0000005d; + checkreg ASTAT, (0x4440c080 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x4c90c680 | _VS | _AV1S | _AV0S | _AC0 | _CC); + dmm32 A1.w, 0x3ae26599; + dmm32 A1.x, 0xfffffff3; + A1 = A1 >> 0x25; + checkreg A1.w, 0xc8000000; + checkreg A1.x, 0x0000002c; + checkreg ASTAT, (0x4c90c680 | _VS | _AV1S | _AV0S | _AC0 | _CC); + + dmm32 ASTAT, (0x3c204000 | _AV1 | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC); + dmm32 A1.w, 0x1686a378; + dmm32 A1.x, 0x0000006a; + A1 = A1 >> 0x16; + checkreg A1.w, 0x0001a85a; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x3c204000 | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC); + + dmm32 ASTAT, (0x30500800 | _VS | _AV0S | _AQ); + dmm32 A1.w, 0x6575285f; + dmm32 A1.x, 0x00000000; + A1 = A1 >> 0x2e; + checkreg A1.w, 0xa17c0000; + checkreg A1.x, 0xffffffd4; + checkreg ASTAT, (0x30500800 | _VS | _AV0S | _AQ | _AN); + + dmm32 ASTAT, (0x70c04010 | _VS | _AV0S | _AQ | _CC); + dmm32 A1.w, 0x0c7da4e2; + dmm32 A1.x, 0x00000000; + A1 = A1 >> 0x29; + checkreg A1.w, 0x71000000; + checkreg A1.x, 0xffffffd2; + checkreg ASTAT, (0x70c04010 | _VS | _AV0S | _AQ | _CC | _AN); + + dmm32 ASTAT, (0x74000600 | _VS | _AC1 | _AQ); + dmm32 A0.w, 0xd0e47afa; + dmm32 A0.x, 0x00000006; + A0 = A0 >> 0x32; + checkreg A0.w, 0x1ebe8000; + checkreg A0.x, 0x00000039; + checkreg ASTAT, (0x74000600 | _VS | _AC1 | _AQ); + + dmm32 ASTAT, (0x4ce08200 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ); + dmm32 A1.w, 0x1b158860; + dmm32 A1.x, 0x00000068; + A1 = A1 >> 0x21; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000030; + checkreg ASTAT, (0x4ce08200 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ); + + dmm32 ASTAT, (0x48c00610 | _VS | _AV1S | _AQ | _CC | _AN); + dmm32 A1.w, 0x0a2c41e4; + dmm32 A1.x, 0x00000000; + A1 = A1 >> 0x25; + checkreg A1.w, 0x20000000; + checkreg A1.x, 0x0000000f; + checkreg ASTAT, (0x48c00610 | _VS | _AV1S | _AQ | _CC); + + dmm32 ASTAT, (0x08700400 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY | _AZ); + dmm32 A0.w, 0xec125059; + dmm32 A0.x, 0xffffffff; + A0 = A0 >> 0x32; + checkreg A0.w, 0x94164000; + checkreg A0.x, 0x00000004; + checkreg ASTAT, (0x08700400 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY); + + pass diff --git a/sim/testsuite/bfin/random_0012.S b/sim/testsuite/bfin/random_0012.S new file mode 100644 index 0000000..cedf359 --- /dev/null +++ b/sim/testsuite/bfin/random_0012.S @@ -0,0 +1,52 @@ +# test VIT_MAX behavior when high Acc bits are set +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x5860c690 | _VS | _AV0S | _AC1 | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0xd81562e8; + dmm32 A0.x, 0xffffffff; + imm32 R4, 0x15c2d815; + imm32 R5, 0xc9bd3a6b; + R4.L = VIT_MAX (R5) (ASR); + checkreg R4, 0x15c23a6b; + checkreg A0.w, 0x6c0ab174; + checkreg A0.x, 0x0000007f; + checkreg ASTAT, (0x5860c690 | _VS | _AV0S | _AC1 | _AQ | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x48308090 | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x715cf6e6; + dmm32 A0.x, 0xffffffb6; + imm32 R3, 0x3a89c7ed; + imm32 R4, 0x4819bbf9; + R3.L = VIT_MAX (R4) (ASR); + checkreg R3, 0x3a89bbf9; + checkreg A0.w, 0x38ae7b73; + checkreg A0.x, 0x0000005b; + checkreg ASTAT, (0x48308090 | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x18104c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); + dmm32 A0.w, 0xea06f130; + dmm32 A0.x, 0xffffffff; + imm32 R2, 0x62ce98f1; + imm32 R5, 0x045415f9; + R2.L = VIT_MAX (R5) (ASR); + checkreg R2, 0x62ce15f9; + checkreg A0.w, 0x75037898; + checkreg A0.x, 0x0000007f; + checkreg ASTAT, (0x18104c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x0090ce10 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A0.w, 0xffffffff; + dmm32 A0.x, 0xffffffff; + imm32 R0, 0xc9647fff; + imm32 R6, 0x1d4baeb8; + R6.L = VIT_MAX (R0) (ASR); + checkreg R6, 0x1d4bc964; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0x0000007f; + checkreg ASTAT, (0x0090ce10 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0013.S b/sim/testsuite/bfin/random_0013.S new file mode 100644 index 0000000..9a427b3 --- /dev/null +++ b/sim/testsuite/bfin/random_0013.S @@ -0,0 +1,417 @@ +# Ensure that dsp insns with IH modifiers saturate first, then round +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x24304400 | _VS | _AV1S | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ); + dmm32 A0.w, 0x3883de11; + dmm32 A0.x, 0x00000025; + imm32 R2, 0xeb641947; + imm32 R3, 0x66d10863; + imm32 R5, 0x00d44f5a; + R5.L = (A0 += R3.L * R2.L) (IH); + checkreg R5, 0x00d47fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x24304400 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x04b04e10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0x1e069e1a; + dmm32 A0.x, 0xfffffff5; + imm32 R3, 0xffff0001; + R3.L = A0 (IH); + checkreg R3, 0xffff8000; + checkreg ASTAT, (0x04b04e10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x14f08600 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x766c79cc; + dmm32 A0.x, 0xffffffd9; + imm32 R4, 0x14801bff; + R4.L = A0 (IH); + checkreg R4, 0x14808000; + checkreg ASTAT, (0x14f08600 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x6060c600 | _VS | _AV1S | _AV0S | _AC1 | _V_COPY | _AN | _AZ); + dmm32 A0.w, 0x1e7461de; + dmm32 A0.x, 0xffffff91; + imm32 R6, 0x1ba08a9e; + R6.L = A0 (IH); + checkreg R6, 0x1ba08000; + checkreg ASTAT, (0x6060c600 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AN); + + dmm32 ASTAT, (0x28700e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); + dmm32 A0.w, 0xfb5acc4e; + dmm32 A0.x, 0xfffffffe; + imm32 R4, 0x15baf604; + R4.L = A0 (IH); + checkreg R4, 0x15ba8000; + checkreg ASTAT, (0x28700e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x24708610 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A0.w, 0x0de70c92; + dmm32 A0.x, 0xffffffde; + imm32 R3, 0x0f323c4c; + R3.L = A0 (IH); + checkreg R3, 0x0f328000; + checkreg ASTAT, (0x24708610 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x6800c880 | _AV1 | _AV0 | _AQ | _AZ); + dmm32 A0.w, 0x482bfb59; + dmm32 A0.x, 0x0000005e; + imm32 R6, 0x4616e4ad; + imm32 R7, 0x4a88b2b1; + R6.L = (A0 += R6.H * R7.L) (IH); + checkreg R6, 0x46167fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x6800c880 | _VS | _V | _AV1 | _AV0S | _AV0 | _AQ | _V_COPY | _AZ); + + dmm32 ASTAT, (0x44d08280 | _VS | _V | _AQ | _V_COPY | _AZ); + dmm32 A0.w, 0xf29e3a4c; + dmm32 A0.x, 0x0000003b; + imm32 R2, 0x004027d0; + imm32 R4, 0x44761fd1; + imm32 R7, 0x7fff0001; + R7.L = (A0 -= R4.H * R2.H) (IH); + checkreg R7, 0x7fff7fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x44d08280 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AZ); + + dmm32 ASTAT, (0x18a00680 | _VS | _AV1S | _AQ | _CC); + dmm32 A0.w, 0x174c203a; + dmm32 A0.x, 0x00000060; + imm32 R3, 0x1f100000; + R3.L = A0 (IH); + checkreg R3, 0x1f107fff; + checkreg ASTAT, (0x18a00680 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x38e04090 | _VS | _AV0S | _AQ | _AN | _AZ); + dmm32 A0.w, 0x5db9b913; + dmm32 A0.x, 0x00000048; + imm32 R0, 0xd513ffff; + imm32 R2, 0xfcee02ff; + R0.L = (A0 -= R2.H * R0.H) (IH); + checkreg R0, 0xd5137fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x38e04090 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x2030c680 | _VS | _V | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x113de06e; + dmm32 A0.x, 0x00000006; + imm32 R3, 0x3de9b335; + R3.L = A0 (IH); + checkreg R3, 0x3de97fff; + checkreg ASTAT, (0x2030c680 | _VS | _V | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x14300210 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x3219dde5; + dmm32 A0.x, 0xfffffffe; + imm32 R2, 0x8000ffde; + R2.L = A0 (IH); + checkreg R2, 0x80008000; + checkreg ASTAT, (0x14300210 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x5c304e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x500d8a96; + dmm32 A0.x, 0x00000071; + imm32 R2, 0x47bc6a2d; + R2.L = A0 (IH); + checkreg R2, 0x47bc7fff; + checkreg ASTAT, (0x5c304e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x40d04410 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0xed76198b; + dmm32 A0.x, 0xffffffdd; + imm32 R4, 0x485f8000; + R4.L = A0 (IH); + checkreg ASTAT, (0x40d04410 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x34f00290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0xc0000000; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x80008000; + imm32 R3, 0x2cb77eda; + R0.L = (A0 += R3.H * R3.H) (IH); + checkreg R0, 0x80007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x34f00290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x2490c610 | _VS | _V | _V_COPY | _AN); + dmm32 A0.w, 0xc2375c00; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x8000ffff; + imm32 R1, 0xac86b35f; + imm32 R6, 0x3cb137de; + R0.L = (A0 -= R6.H * R1.H) (IH); + checkreg R0, 0x80007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x2490c610 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AN); + + dmm32 ASTAT, (0x3000c810 | _VS | _AC0 | _AQ | _CC | _AN); + dmm32 A0.w, 0x44fe7a9d; + dmm32 A0.x, 0x0000006e; + imm32 R2, 0xbb4f8000; + imm32 R4, 0xfe2d7fff; + imm32 R7, 0x5da7ea43; + R7.L = (A0 += R4.L * R2.L) (IH); + checkreg R7, 0x5da77fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x3000c810 | _VS | _V | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x1c708000 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AZ); + dmm32 A0.w, 0x6ad001aa; + dmm32 A0.x, 0x0000002a; + imm32 R6, 0x7fff65d9; + R6.L = A0 (IH); + checkreg R6, 0x7fff7fff; + checkreg ASTAT, (0x1c708000 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x1430cc80 | _AV0S | _AC0 | _AQ | _AN | _AZ); + dmm32 A0.w, 0x5c04c87a; + dmm32 A0.x, 0x00000002; + imm32 R1, 0x6752c24c; + imm32 R7, 0x21f7c24f; + R1.L = (A0 -= R1.H * R7.H) (IH); + checkreg R1, 0x67527fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x1430cc80 | _VS | _V | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x44500c80 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A0.w, 0x603980cf; + dmm32 A0.x, 0xffffffff; + imm32 R3, 0xffffffff; + R3.L = A0 (IH); + checkreg R3, 0xffff8000; + checkreg ASTAT, (0x44500c80 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x70508c90 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY); + dmm32 A0.w, 0x097b558d; + dmm32 A0.x, 0x00000005; + imm32 R1, 0x80002c0a; + R1.L = A0 (IH); + checkreg R1, 0x80007fff; + checkreg ASTAT, (0x70508c90 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x1820c410 | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); + dmm32 A0.w, 0x69470e6b; + dmm32 A0.x, 0x0000005a; + imm32 R1, 0x3a0e82ef; + imm32 R4, 0x2c0af024; + imm32 R6, 0x5a301523; + R1.L = (A0 += R6.L * R4.L) (IH); + checkreg R1, 0x3a0e7fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x1820c410 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x14a04e10 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0xaaa829c8; + dmm32 A0.x, 0x0000000f; + imm32 R3, 0x901b7fff; + imm32 R4, 0xf8d50755; + imm32 R6, 0x0a98c742; + R4.L = (A0 += R3.L * R6.L) (IH); + checkreg R4, 0xf8d57fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x14a04e10 | _VS | _V | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x7c70c800 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY); + dmm32 A0.w, 0x3875c265; + dmm32 A0.x, 0x0000000e; + imm32 R0, 0x8000af00; + imm32 R3, 0x071fe97d; + imm32 R5, 0x72d82b4b; + R0.L = (A0 += R3.H * R5.H) (IH); + checkreg R0, 0x80007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x7c70c800 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x04508a80 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY); + dmm32 A0.w, 0x5055d0b1; + dmm32 A0.x, 0x00000009; + imm32 R2, 0x7b9b1a96; + imm32 R4, 0x56a17f45; + R4.L = (A0 -= R4.L * R2.L) (IH); + checkreg R4, 0x56a17fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x04508a80 | _VS | _V | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x60408c90 | _VS | _AV1 | _CC | _AC0_COPY); + dmm32 A1.w, 0x4d722bbd; + dmm32 A1.x, 0x0000000a; + imm32 R1, 0x31c46841; + imm32 R4, 0xe31521b2; + imm32 R6, 0x49d747d4; + R6.H = (A1 -= R1.L * R4.L) (M, IH); + checkreg R6, 0x7fff47d4; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x60408c90 | _VS | _V | _AV1S | _AV1 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x7c808690 | _VS | _AV1S | _AC1 | _AC0 | _AC0_COPY); + dmm32 A0.w, 0x48379e0d; + dmm32 A0.x, 0x00000061; + imm32 R0, 0x272c8000; + imm32 R4, 0x7fff7fff; + R0.L = (A0 += R4.L * R4.H) (IH); + checkreg R0, 0x272c7fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x7c808690 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x10308800 | _VS | _AC1 | _AC0 | _AQ | _AN); + dmm32 A1.w, 0x9ddbf339; + dmm32 A1.x, 0x00000010; + imm32 R1, 0x00679160; + imm32 R5, 0x1fa0ffff; + imm32 R6, 0x4312c2cd; + R6.H = (A1 -= R1.L * R5.H) (IH); + checkreg R6, 0x7fffc2cd; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x10308800 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x3040ca90 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC | _AN | _AZ); + dmm32 A0.w, 0x2d631ab7; + dmm32 A0.x, 0x00000066; + imm32 R5, 0x325c8000; + R5.L = A0 (IH); + checkreg R5, 0x325c7fff; + checkreg ASTAT, (0x3040ca90 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x5ca08c90 | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0x86fce74b; + dmm32 A0.x, 0x0000007f; + imm32 R1, 0x3e9e0014; + imm32 R7, 0x6d73d06c; + R7.L = (A0 += R1.L * R7.H) (IH); + checkreg R7, 0x6d737fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x5ca08c90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x50e0c880 | _VS | _AC1); + dmm32 A0.w, 0x9e40a194; + dmm32 A0.x, 0x00000000; + imm32 R5, 0x6ba7ac29; + imm32 R6, 0x50a97ffe; + R5.L = (A0 += R6.L * R5.H) (IH); + checkreg R5, 0x6ba77fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x50e0c880 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY); + + dmm32 ASTAT, (0x3ce0c810 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x9abe32ae; + dmm32 A0.x, 0xffffffc2; + imm32 R2, 0x8000e9a0; + R2.L = A0 (IH); + checkreg R2, 0x80008000; + checkreg ASTAT, (0x3ce0c810 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x6090c010 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY); + dmm32 A0.w, 0x53e97a53; + dmm32 A0.x, 0x0000004d; + imm32 R1, 0x289e2e4e; + R1.L = A0 (IH); + checkreg R1, 0x289e7fff; + checkreg ASTAT, (0x6090c010 | _VS | _V | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x34708800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); + dmm32 A0.w, 0x1035b3fa; + dmm32 A0.x, 0x00000001; + imm32 R1, 0xec227fff; + R1.L = A0 (IH); + checkreg ASTAT, (0x34708800 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x30200c00 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _V_COPY); + imm32 R1, 0x30d07fff; + imm32 R2, 0x007f1105; + imm32 R4, 0x7fffffff; + R1.H = R2.L * R4.L (M, IH); + checkreg R1, 0x11057fff; + checkreg ASTAT, (0x30200c00 | _VS | _AV1S | _AV0S | _AV0 | _AC1); + + dmm32 ASTAT, (0x1c008200 | _VS | _V | _AV1S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); + dmm32 A0.w, 0x46ccaead; + dmm32 A0.x, 0x0000006b; + imm32 R4, 0x80003753; + imm32 R5, 0x128216a3; + imm32 R6, 0x7c3455c4; + R4.L = (A0 += R5.L * R6.H) (IH); + checkreg R4, 0x80007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x1c008200 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x14304e10 | _VS | _AV0S | _AV0 | _AC0); + dmm32 A0.w, 0x7fc17d70; + dmm32 A0.x, 0x0000000f; + imm32 R3, 0x5cb72991; + imm32 R4, 0x3a823142; + imm32 R7, 0xde5bf5a2; + R7.L = (A0 += R4.H * R3.H) (IH); + checkreg R7, 0xde5b7fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x14304e10 | _VS | _V | _AV0S | _AV0 | _AC0 | _V_COPY); + + dmm32 ASTAT, (0x10900290 | _VS | _V | _AQ | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x7fb16a1d; + dmm32 A0.x, 0x00000052; + imm32 R0, 0x1e4a7fff; + imm32 R2, 0x62b886f4; + imm32 R3, 0x80004104; + R3.L = (A0 -= R2.H * R0.H) (IH); + checkreg R3, 0x80007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x10900290 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x18608400 | _VS | _AV1S | _AQ | _AC0_COPY | _AN); + dmm32 A1.w, 0x62fcbde0; + dmm32 A1.x, 0x0000006a; + imm32 R2, 0x60339fcc; + imm32 R3, 0x5fa9f612; + imm32 R4, 0x6f006000; + R2.H = (A1 += R3.L * R4.H) (IH); + checkreg R2, 0x7fff9fcc; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x18608400 | _VS | _V | _AV1S | _AV1 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x60100210 | _VS | _V | _CC | _V_COPY | _AN); + dmm32 A0.w, 0x52a9b75e; + dmm32 A0.x, 0x00000003; + imm32 R0, 0xffff349c; + imm32 R6, 0x0084550f; + R0.L = (A0 += R6.L * R0.H) (IH); + checkreg R0, 0xffff7fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x60100210 | _VS | _V | _AV0S | _AV0 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x7840cc10 | _VS | _V | _AV0 | _AC1 | _V_COPY | _AN | _AZ); + dmm32 A0.w, 0x22aa6b49; + dmm32 A0.x, 0x0000006a; + imm32 R1, 0x17528642; + imm32 R5, 0x8000a49b; + imm32 R6, 0x03ec4bb6; + R5.L = (A0 -= R1.H * R6.H) (IH); + checkreg R5, 0x80007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x7840cc10 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN | _AZ); + + pass diff --git a/sim/testsuite/bfin/random_0014.S b/sim/testsuite/bfin/random_0014.S new file mode 100644 index 0000000..c77b305 --- /dev/null +++ b/sim/testsuite/bfin/random_0014.S @@ -0,0 +1,82 @@ +# Test a few corner cases with various shift insns +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x38404290 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0xf53d356e; + dmm32 A0.x, 0xffffffff; + imm32 R5, 0xaa156b54; + A0 = ASHIFT A0 BY R5.L; + checkreg A0.w, 0x56e00000; + checkreg A0.x, 0xffffffd3; + checkreg ASTAT, (0x38404290 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x28e00410 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY); + dmm32 A0.w, 0x1dfd2a85; + dmm32 A0.x, 0xffffffbe; + imm32 R2, 0x4b7cf707; + A0 = LSHIFT A0 BY R2.L; + checkreg A0.w, 0xfe954280; + checkreg A0.x, 0x0000000e; + checkreg ASTAT, (0x28e00410 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY); + + dmm32 ASTAT, (0x60404e00 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0xd4aa6e10; + dmm32 A1.x, 0xffffffff; + imm32 R4, 0xb4bb3054; + A1 = ASHIFT A1 BY R4.L; + checkreg A1.w, 0xe1000000; + checkreg A1.x, 0xffffffa6; + checkreg ASTAT, (0x60404e00 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x00608810 | _V | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0x0dbadb4f; + dmm32 A1.x, 0x00000035; + imm32 R3, 0x3cc3f7db; + A1 = LSHIFT A1 BY R3.L; + checkreg A1.w, 0x78000000; + checkreg A1.x, 0xffffffda; + checkreg ASTAT, (0x00608810 | _V | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x14900e10 | _VS | _AC0 | _CC | _AC0_COPY); + imm32 R0, 0x6286ee56; + imm32 R7, 0x5cd969c5; + R0 = ASHIFT R0 BY R7.L; + checkreg R0, 0x50ddcac0; + checkreg ASTAT, (0x14900e10 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x28904a90 | _VS | _V | _AV0S | _V_COPY | _AZ); + imm32 R0, 0x00000000; + imm32 R5, 0x00008000; + imm32 R6, 0x03488f9a; + R0.L = ASHIFT R5.L BY R6.L; + checkreg ASTAT, (0x28904a90 | _VS | _V | _AV0S | _V_COPY | _AZ); + + dmm32 ASTAT, (0x3c10c890 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY); + imm32 R1, 0x29162006; + imm32 R3, 0xffff0345; + imm32 R4, 0x8ff5e6bb; + R1.H = ASHIFT R4.H BY R3.L; + checkreg R1, 0xfea02006; + checkreg ASTAT, (0x3c10c890 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x78600e00 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC); + imm32 R0, 0xd5b1804d; + imm32 R1, 0x522c817d; + imm32 R5, 0xfca6f990; + R1.H = ASHIFT R5.H BY R0.L; + checkreg R1, 0xc000817d; + checkreg ASTAT, (0x78600e00 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x64b04890 | _VS | _V | _AV0S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + imm32 R4, 0x80000000; + imm32 R6, 0x4e840a3e; + imm32 R7, 0x20102e48; + R6.L = ASHIFT R4.H BY R7.L; + checkreg R6, 0x4e840000; + checkreg ASTAT, (0x64b04890 | _VS | _V | _AV0S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); + + pass diff --git a/sim/testsuite/bfin/random_0015.S b/sim/testsuite/bfin/random_0015.S new file mode 100644 index 0000000..60d6317 --- /dev/null +++ b/sim/testsuite/bfin/random_0015.S @@ -0,0 +1,25 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x5c70c410 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN); + dmm32 A1.w, 0xb7cc6ddd; + dmm32 A1.x, 0x00000004; + imm32 R3, 0x3f225ae3; + A1 = ASHIFT A1 BY R3.L; + checkreg A1.w, 0x00000025; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x5c70c410 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY); + + dmm32 ASTAT, (0x4810ca80 | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY | _AN); + dmm32 A1.w, 0x7396e11c; + dmm32 A1.x, 0xffffffba; + imm32 R3, 0x6e5f9f48; + A1 = ASHIFT A1 BY R3.L; + checkreg A1.w, 0x96e11c00; + checkreg A1.x, 0x00000073; + checkreg ASTAT, (0x4810ca80 | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY); + + pass diff --git a/sim/testsuite/bfin/random_0016.S b/sim/testsuite/bfin/random_0016.S new file mode 100644 index 0000000..0b45074 --- /dev/null +++ b/sim/testsuite/bfin/random_0016.S @@ -0,0 +1,26 @@ +# Test LSHIFT values and ASTAT flags +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x7ce00000 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY | _AN); + dmm32 A0.w, 0xe1a3909e; + dmm32 A0.x, 0xffffffff; + imm32 R2, 0x214a26f6; + A0 = LSHIFT A0 BY R2.L; + checkreg A0.w, 0x3ff868e4; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x7ce00000 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x64008a00 | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _CC | _AN); + dmm32 A0.w, 0x72af1593; + dmm32 A0.x, 0xfffffffd; + imm32 R2, 0x6505b40c; + A0 = LSHIFT A0 BY R2.L; + checkreg A0.w, 0xf1593000; + checkreg A0.x, 0x0000002a; + checkreg ASTAT, (0x64008a00 | _AV1 | _AV0S | _AC0 | _AQ | _CC); + + pass diff --git a/sim/testsuite/bfin/random_0017.S b/sim/testsuite/bfin/random_0017.S new file mode 100644 index 0000000..edfb650 --- /dev/null +++ b/sim/testsuite/bfin/random_0017.S @@ -0,0 +1,23 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x68000a10 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x2771851d; + dmm32 A0.x, 0xffffffc9; + A0 = A0 >>> 0x1b; + checkreg A0.w, 0xfffff924; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x68000a10 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x74804c10 | _VS | _AC1 | _AC0 | _CC | _AN | _AZ); + dmm32 A1.w, 0xda2eb5c0; + dmm32 A1.x, 0xffffffff; + A1 = A1 >>> 0x11; + checkreg A1.w, 0xffffed17; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x74804c10 | _VS | _AC1 | _AC0 | _CC | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0018.S b/sim/testsuite/bfin/random_0018.S new file mode 100644 index 0000000..f6ec033 --- /dev/null +++ b/sim/testsuite/bfin/random_0018.S @@ -0,0 +1,69 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x40204090 | _AV1S | _AV0S | _AV0 | _AQ | _AN | _AZ); + imm32 R1, 0x33e91405; + imm32 R4, 0x3fa1377c; + R4.H = R1.H >>> 0x1d; + checkreg R4, 0x9f48377c; + checkreg ASTAT, (0x40204090 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x64800010 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY); + imm32 R0, 0xf64722bc; + R0.L = R0.L >>> 0xd (S); + checkreg R0, 0xf6470001; + checkreg ASTAT, (0x64800010 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x70300e10 | _VS | _AQ | _AC0_COPY | _AN); + imm32 R5, 0x2a8771ff; + R5 = R5 >>> 0x1d (V); + checkreg R5, 0x54388ff8; + checkreg ASTAT, (0x70300e10 | _VS | _V | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x04600000 | _VS | _AV1S | _AC0 | _AQ | _CC | _AC0_COPY); + imm32 R6, 0x0c3a7fff; + imm32 R7, 0x03460f23; + R6.H = R7.L >>> 0x1f (S); + checkreg R6, 0x1e467fff; + checkreg ASTAT, (0x04600000 | _VS | _AV1S | _AC0 | _AQ | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x40704010 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + imm32 R3, 0xfa2cee19; + imm32 R5, 0xfa2cee17; + R3.L = R5.H >>> 0xd (S); + checkreg R3, 0xfa2cffff; + checkreg ASTAT, (0x40704010 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x20308c90 | _VS | _AV1S | _AV0S | _CC | _AN); + imm32 R2, 0xd4b70c2f; + imm32 R5, 0x0279838b; + R5.H = R2.H >>> 0x1f (S); + checkreg R5, 0xa96e838b; + checkreg ASTAT, (0x20308c90 | _VS | _AV1S | _AV0S | _CC | _AN); + + dmm32 ASTAT, (0x10a08690 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + imm32 R4, 0x5cae64fc; + imm32 R6, 0x288e1461; + R4.H = R6.L >>> 0x1e (S); + checkreg R4, 0x518464fc; + checkreg ASTAT, (0x10a08690 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY); + + dmm32 ASTAT, (0x48908010 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC); + imm32 R1, 0x4f8f004a; + imm32 R5, 0x7fff70c1; + R5.L = R1.L >>> 0x1e (S); + checkreg R5, 0x7fff0128; + checkreg ASTAT, (0x48908010 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC); + + dmm32 ASTAT, (0x00f00490 | _VS | _AV0S | _AV0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A0.w, 0x32b127c8; + dmm32 A0.x, 0x0000001a; + A0 = A0 >>> 0x6; + checkreg A0.w, 0x68cac49f; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x00f00490 | _VS | _AV0S | _AQ | _CC | _AC0_COPY); + + pass diff --git a/sim/testsuite/bfin/random_0019.S b/sim/testsuite/bfin/random_0019.S new file mode 100644 index 0000000..2da09c4 --- /dev/null +++ b/sim/testsuite/bfin/random_0019.S @@ -0,0 +1,216 @@ +# Test a few (W32) corner cases +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x68b0ca90 | _VS | _AV1S | _AV0S | _CC | _AC0_COPY | _AN | _AZ); + dmm32 A1.w, 0x70da33ff; + dmm32 A1.x, 0x0000000f; + imm32 R0, 0x5e29f819; + imm32 R1, 0x3f59520b; + A1 += R0.L * R1.L (M, W32); + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x68b0ca90 | _VS | _AV1S | _AV1 | _AV0S | _CC | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x18300c10 | _VS | _AV1S | _AN); + dmm32 A0.w, 0x1096b1c1; + dmm32 A0.x, 0xfffffff1; + imm32 R6, 0x3a0178ee; + imm32 R7, 0x17c95e45; + A0 -= R6.L * R7.L (W32); + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x18300c10 | _VS | _AV1S | _AV0S | _AV0 | _AN); + + dmm32 ASTAT, (0x68508800 | _VS | _AV1S | _AV0S | _CC | _AZ); + dmm32 A0.w, 0x30c8f917; + dmm32 A0.x, 0xffffffc8; + imm32 R3, 0x7ad1091c; + imm32 R4, 0x80002874; + A0 -= R3.L * R4.L (W32); + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x68508800 | _VS | _AV1S | _AV0S | _AV0 | _CC | _AZ); + + dmm32 ASTAT, (0x58708e90 | _VS | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY); + dmm32 A0.w, 0x13de4c3d; + dmm32 A0.x, 0xffffffa5; + imm32 R0, 0xf70f956f; + imm32 R2, 0xf837e08c; + A0 -= R0.L * R2.H (W32); + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x58708e90 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY); + + dmm32 ASTAT, (0x70800280 | _VS | _AV1S | _AC1 | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0x80140410; + dmm32 A0.x, 0x00000000; + imm32 R1, 0x028b09a4; + imm32 R4, 0x00007ffc; + A0 += R4.L * R1.H (W32); + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x70800280 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x0060c610 | _VS | _AC1 | _AC0 | _AC0_COPY | _AN | _AZ); + dmm32 A1.w, 0x1794b937; + dmm32 A1.x, 0xfffffff5; + imm32 R6, 0x008e1c0d; + A1 -= R6.L * R6.L (W32); + checkreg A1.w, 0x80000000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x0060c610 | _VS | _AV1S | _AV1 | _AC1 | _AC0 | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x2c600410 | _VS | _AV0S | _AC1 | _CC | _AN); + dmm32 A1.w, 0x2d03ef79; + dmm32 A1.x, 0x00000079; + imm32 R5, 0x15d1b500; + imm32 R6, 0xf7962b39; + A1 += R6.L * R5.H (W32); + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x2c600410 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _CC | _AN); + + dmm32 ASTAT, (0x5cf04e10 | _VS | _AV0S | _AC1 | _CC | _AC0_COPY); + dmm32 A0.w, 0x4d50b3f0; + dmm32 A0.x, 0xfffffffc; + imm32 R4, 0x6671002a; + imm32 R7, 0x00288000; + A0 += R4.L * R7.L (W32); + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x5cf04e10 | _VS | _AV0S | _AV0 | _AC1 | _CC | _AC0_COPY); + + + dmm32 ASTAT, (0x28908000 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AN); + dmm32 A1.w, 0xc94e99f1; + dmm32 A1.x, 0x00000021; + imm32 R4, 0x7fff52b7; + imm32 R7, 0x3ebb26c6; + A1 += R7.L * R4.L (M, W32); + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x28908000 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x34708a00 | _VS | _AV0S | _AQ | _CC | _AC0_COPY); + dmm32 A1.w, 0xf61f316d; + dmm32 A1.x, 0x00000061; + imm32 R1, 0x86f0ffff; + imm32 R3, 0x791048c5; + A1 += R1.L * R3.L (M, W32); + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x34708a00 | _VS | _AV1S | _AV1 | _AV0S | _AQ | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x5020c280 | _VS | _V | _AC1 | _AC0 | _V_COPY); + dmm32 A1.w, 0x8700591f; + dmm32 A1.x, 0x00000007; + imm32 R2, 0x145b00b1; + imm32 R3, 0x7fffffff; + A1 -= R3.L * R2.H (M, W32); + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x5020c280 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _V_COPY); + + dmm32 ASTAT, (0x00000290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); + dmm32 A0.w, 0xfe84e1ec; + dmm32 A0.x, 0xffffffff; + imm32 R1, 0x07e73e7b; + imm32 R3, 0x00033e7b; + A0 -= R3.L * R1.H (W32); + checkreg A0.w, 0xfaa965f2; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x00000290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x78204a80 | _VS | _AV1S | _CC | _AN); + dmm32 A0.w, 0xca398210; + dmm32 A0.x, 0xffffffff; + imm32 R3, 0xffff0000; + imm32 R7, 0x00000000; + A0 += R7.L * R3.L (W32); + checkreg ASTAT, (0x78204a80 | _VS | _AV1S | _CC | _AN); + + dmm32 ASTAT, (0x04208890 | _VS | _AC1 | _AC0_COPY); + dmm32 A0.w, 0x224cbaee; + dmm32 A0.x, 0x00000000; + imm32 R3, 0x3db86584; + imm32 R6, 0xdb505ed8; + A0 -= R6.L * R3.H (W32); + checkreg A0.w, 0xf491746e; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x04208890 | _VS | _AC1 | _AC0_COPY); + + dmm32 ASTAT, (0x3c908600 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY); + dmm32 A0.w, 0x03f7c0ec; + dmm32 A0.x, 0x00000000; + imm32 R1, 0x1c25c7b4; + imm32 R5, 0x3f7da612; + A0 -= R5.L * R1.L (W32); + checkreg A0.w, 0xdc6a3b9c; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x3c908600 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY); + + dmm32 ASTAT, (0x7cb08680 | _VS | _AQ | _CC | _AN); + dmm32 A0.w, 0xdc7c243c; + dmm32 A0.x, 0xffffffff; + imm32 R0, 0xe2ccef4c; + imm32 R5, 0x7fff8000; + A0 += R5.L * R0.L (W32); + checkreg A0.w, 0xed30243c; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x7cb08680 | _VS | _AQ | _CC | _AN); + + dmm32 ASTAT, (0x78f00080 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AN); + dmm32 A0.w, 0x39180f38; + dmm32 A0.x, 0x00000000; + imm32 R4, 0x01308ac1; + imm32 R6, 0x7ffff8fd; + A0 = R6.L * R4.H (W32); + checkreg A0.w, 0xffef58e0; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x78f00080 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x7050c090 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0x010909b0; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x80000000; + imm32 R6, 0x6ad06150; + A1 = R6.L * R0.H (W32); + checkreg A1.w, 0x9eb00000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x7050c090 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x68c04c10 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AN); + dmm32 A0.w, 0x43687862; + dmm32 A0.x, 0x00000000; + imm32 R2, 0xff278000; + imm32 R4, 0x0000436a; + A0 += R2.L * R4.L (W32); + checkreg A0.w, 0xfffe7862; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x68c04c10 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x74a00200 | _AV1 | _AV0S | _AV0 | _AC1 | _V_COPY | _AC0_COPY | _AN | _AZ); + dmm32 A1.w, 0x64c15e6b; + dmm32 A1.x, 0xffffff87; + imm32 R4, 0x30b3e20d; + imm32 R7, 0x4a562069; + A1 = R4.L * R7.H (M, W32); + checkreg A1.w, 0xf74db25e; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x74a00200 | _AV0S | _AV0 | _AC1 | _V_COPY | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x70f08410 | _AV0 | _AC1 | _AC0_COPY | _AN | _AZ); + dmm32 A0.w, 0x5f011b0d; + dmm32 A0.x, 0xffffff86; + imm32 R3, 0x21f93a90; + imm32 R4, 0x1c82d429; + A0 = R3.H * R4.L (W32); + checkreg A0.w, 0xf45d49c2; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x70f08410 | _AC1 | _AC0_COPY | _AN | _AZ); + + pass diff --git a/sim/testsuite/bfin/random_0020.S b/sim/testsuite/bfin/random_0020.S new file mode 100644 index 0000000..d140fb1 --- /dev/null +++ b/sim/testsuite/bfin/random_0020.S @@ -0,0 +1,434 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x0cb08810 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + dmm32 A1.w, 0xfcdbede4; + dmm32 A1.x, 0xffffffff; + imm32 R5, 0x14c5c1c7; + imm32 R7, 0x006a5040; + R5 = (A1 += R7.L * R7.H) (M, IU); + checkreg R5, 0xfcfd2864; + checkreg A1.w, 0xfcfd2864; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x0cb08810 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x6c508a90 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0x0bcd165c; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x439a7ef1; + imm32 R3, 0x47670015; + imm32 R6, 0x00008000; + R3 = (A1 += R6.L * R0.L) (M, IU); + checkreg R3, 0xcc54965c; + checkreg A1.w, 0xcc54965c; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x6c508a90 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x38900480 | _VS | _AV0S | _AN); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x8000ffff; + imm32 R3, 0x0000ffff; + imm32 R6, 0xcb2cf810; + R3 = (A1 += R6.L * R1.L) (M, IU); + checkreg R3, 0xf81007f0; + checkreg A1.w, 0xf81007f0; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x38900480 | _VS | _AV0S | _AN); + + dmm32 ASTAT, (0x20100610 | _VS | _AC1 | _AQ | _AN); + dmm32 A1.w, 0x36491cf0; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x10771108; + imm32 R2, 0x7fb14fe2; + imm32 R7, 0x3649ffff; + R1 = (A1 = R7.L * R2.H) (M, IU); + checkreg R1, 0xffff804f; + checkreg A1.w, 0xffff804f; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x20100610 | _VS | _AC1 | _AQ | _AN); + + dmm32 ASTAT, (0x6c304400 | _VS | _AV1S | _AC1 | _AQ); + dmm32 A1.w, 0xd831c3b7; + dmm32 A1.x, 0xffffffff; + imm32 R3, 0x3a98144b; + imm32 R7, 0xd831c3b7; + R7 = (A1 -= R3.L * R3.H) (M, IU); + checkreg R7, 0xd38cb92f; + checkreg A1.w, 0xd38cb92f; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x6c304400 | _VS | _AV1S | _AC1 | _AQ); + + dmm32 ASTAT, (0x3c50c810 | _VS | _AV1S | _AN | _AZ); + dmm32 A0.w, 0x13cd1c6c; + dmm32 A0.x, 0x00000000; + imm32 R2, 0x4000e935; + imm32 R3, 0xe0b313cd; + R3.L = (A0 += R3.H * R2.L) (IU); + checkreg R3, 0xe0b3ffff; + checkreg A0.w, 0xe07e8c7b; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x3c50c810 | _VS | _V | _AV1S | _V_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x7c900280 | _AV1S | _AV0S | _AC1 | _AQ); + dmm32 A0.w, 0x057e5874; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x1c0af520; + imm32 R6, 0x7caea317; + imm32 R7, 0x107e8ce4; + R6.L = (A0 += R7.L * R0.L) (IU); + checkreg R6, 0x7caeffff; + checkreg A0.w, 0x8c6628f4; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x7c900280 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x6cf04090 | _VS | _AV1S | _AV0S | _AC1 | _AZ); + dmm32 A0.w, 0xdc7d7b8c; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x788e00d2; + imm32 R6, 0x03666070; + R0.L = (A0 -= R6.H * R6.H) (IU); + checkreg R0, 0x788effff; + checkreg A0.w, 0xdc71eee8; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x6cf04090 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AZ); + + dmm32 ASTAT, (0x4cc04c80 | _VS | _CC); + dmm32 A1.w, 0x41620ea7; + dmm32 A1.x, 0x00000057; + imm32 R1, 0xf611262c; + imm32 R3, 0x7fff7fff; + imm32 R4, 0x247ee19c; + R1 = (A1 += R4.L * R3.L) (IU); + checkreg R1, 0xffffffff; + checkreg A1.w, 0xb22f2d0b; + checkreg A1.x, 0x00000057; + checkreg ASTAT, (0x4cc04c80 | _VS | _V | _CC | _V_COPY); + + dmm32 ASTAT, (0x28e04610 | _VS | _AV0S | _AC1 | _AC0 | _AN); + dmm32 A0.w, 0xe1753d16; + dmm32 A0.x, 0xffffffff; + imm32 R0, 0x7fffffff; + imm32 R5, 0x2792ffff; + imm32 R7, 0xffffd6fa; + R7.L = (A0 = R0.L * R5.L) (IU); + checkreg R7, 0xffffffff; + checkreg A0.w, 0xfffe0001; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x28e04610 | _VS | _V | _AV0S | _AC1 | _AC0 | _V_COPY | _AN); + + dmm32 ASTAT, (0x7c900280 | _AV1S | _AV0S | _AC1 | _AQ); + dmm32 A0.w, 0x057e5874; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x1c0af520; + imm32 R6, 0x7caea317; + imm32 R7, 0x107e8ce4; + R6.L = (A0 += R7.L * R0.L) (IU); + checkreg R6, 0x7caeffff; + checkreg A0.w, 0x8c6628f4; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x7c900280 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x00304000 | _VS | _AV1S | _AQ | _AZ); + dmm32 A0.w, 0x615bac86; + dmm32 A0.x, 0x00000000; + imm32 R2, 0x6d2cbec6; + imm32 R3, 0xe09db667; + R3.L = (A0 += R3.H * R2.H) (IU); + checkreg R3, 0xe09dffff; + checkreg A0.w, 0xc1252082; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x00304000 | _VS | _V | _AV1S | _AQ | _V_COPY | _AZ); + + dmm32 ASTAT, (0x5cc00080 | _VS | _AV1S | _AC0 | _CC); + dmm32 A1.w, 0x70d9985a; + dmm32 A1.x, 0xffffffd6; + imm32 R1, 0x8000fdeb; + imm32 R2, 0x20e07e89; + R1.H = (A1 += R2.L * R1.L) (M, IU); + checkreg A1.w, 0xee5b251d; + checkreg A1.x, 0xffffffd6; + checkreg ASTAT, (0x5cc00080 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY); + + dmm32 ASTAT, (0x60e0ce80 | _VS | _AC0 | _AQ | _CC); + dmm32 A1.w, 0x67798cf6; + dmm32 A1.x, 0x00000044; + imm32 R0, 0x00000000; + imm32 R1, 0x00008e16; + imm32 R7, 0x00000000; + R7 = (A1 -= R0.L * R1.L) (M, IU); + checkreg R7, 0x7fffffff; + checkreg A1.w, 0x67798cf6; + checkreg A1.x, 0x00000044; + checkreg ASTAT, (0x60e0ce80 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x00500210 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0x6f47fe74; + dmm32 A1.x, 0x00000022; + imm32 R5, 0x3482aa64; + imm32 R6, 0x48320cd9; + R5.H = (A1 -= R6.L * R5.L) (M, IU); + checkreg R5, 0x7fffaa64; + checkreg A1.w, 0x66badfb0; + checkreg A1.x, 0x00000022; + checkreg ASTAT, (0x00500210 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x60f04890 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0x43fdb94f; + dmm32 A1.x, 0xffffff97; + imm32 R1, 0x80000000; + imm32 R7, 0x0f9b234b; + R1.H = (A1 += R7.L * R1.H) (M, IU); + checkreg A1.w, 0x55a3394f; + checkreg A1.x, 0xffffff97; + checkreg ASTAT, (0x60f04890 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x60f0c280 | _V | _AV1S | _AV1 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); + dmm32 A1.w, 0x33205f9e; + dmm32 A1.x, 0xfffffffc; + imm32 R3, 0x39e0545d; + imm32 R6, 0x0e133731; + R3 = (A1 -= R3.L * R6.H) (M, IU); + checkreg R3, 0x80000000; + checkreg A1.w, 0x2e7d06b7; + checkreg A1.x, 0xfffffffc; + checkreg ASTAT, (0x60f0c280 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x6c300490 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0x2a477a36; + dmm32 A1.x, 0xfffffff8; + imm32 R0, 0xff020000; + imm32 R5, 0x00000000; + imm32 R7, 0xffff8000; + R5.H = (A1 -= R0.L * R7.H) (M, IU); + checkreg R5, 0x80000000; + checkreg ASTAT, (0x6c300490 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x1400c210 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AN); + dmm32 A1.w, 0x68033dca; + dmm32 A1.x, 0xffffffff; + imm32 R1, 0x00000000; + imm32 R3, 0x00a36a42; + imm32 R7, 0x3afd7fff; + R3.H = (A1 -= R1.L * R7.H) (M, IU); + checkreg R3, 0x80006a42; + checkreg ASTAT, (0x1400c210 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x00104810 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN); + dmm32 A1.w, 0xeb4e9a1d; + dmm32 A1.x, 0xffffff8c; + imm32 R1, 0xffffec05; + imm32 R5, 0x80000000; + imm32 R6, 0x5ffa604a; + R1.H = (A1 += R6.L * R5.H) (M, IU); + checkreg R1, 0x8000ec05; + checkreg A1.w, 0x1b739a1d; + checkreg A1.x, 0xffffff8d; + checkreg ASTAT, (0x00104810 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x48600280 | _VS | _AV1S | _AV0 | _AC1 | _CC | _AC0_COPY); + dmm32 A1.w, 0x54463e5f; + dmm32 A1.x, 0xffffff94; + imm32 R1, 0x2e0d6820; + imm32 R4, 0x37855c3d; + imm32 R6, 0x7b3ca7a0; + R6.H = (A1 += R4.L * R1.L) (M, IU); + checkreg R6, 0x8000a7a0; + checkreg A1.w, 0x79ca8dff; + checkreg A1.x, 0xffffff94; + checkreg ASTAT, (0x48600280 | _VS | _V | _AV1S | _AV0 | _AC1 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x3c008480 | _VS | _AV1S | _AC1 | _AC0 | _CC); + dmm32 A0.w, 0xcdff712a; + dmm32 A0.x, 0xffffffff; + imm32 R0, 0x2f3dfc31; + imm32 R2, 0x1b1a4b4c; + imm32 R6, 0x7cbed409; + R2 = (A0 += R6.H * R0.L) (IU); + checkreg R2, 0xffffffff; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x3c008480 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY); + + dmm32 ASTAT, (0x4ce0ce80 | _VS | _AC1 | _AC0 | _CC); + dmm32 A0.w, 0xfefe27a4; + dmm32 A0.x, 0xffffffff; + imm32 R0, 0x08270055; + imm32 R1, 0x0000ffc2; + imm32 R6, 0x5ca7213b; + R6.L = (A0 += R1.L * R0.H) (IU); + checkreg R6, 0x5ca7ffff; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x4ce0ce80 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY); + + dmm32 ASTAT, (0x7020ca10 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY); + dmm32 A0.w, 0xec60b144; + dmm32 A0.x, 0xffffffff; + imm32 R0, 0x147e9190; + imm32 R1, 0x2b813e9e; + imm32 R4, 0xab65ffff; + R0 = (A0 += R1.L * R4.H) (IU); + checkreg R0, 0xffffffff; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x7020ca10 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x28e08210 | _VS | _AQ | _AN); + dmm32 A0.w, 0xe650ec98; + dmm32 A0.x, 0xffffffff; + imm32 R1, 0xcca1b6ef; + imm32 R2, 0xd762b783; + imm32 R3, 0xef34e465; + R2 = (A0 += R3.L * R1.H) (IU); + checkreg R2, 0xffffffff; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x28e08210 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x58904e00 | _VS | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); + dmm32 A0.w, 0xb84b0e88; + dmm32 A0.x, 0xffffffff; + imm32 R0, 0x8367ffff; + imm32 R1, 0xb6a1af0a; + R1.L = (A0 += R0.H * R1.H) (IU); + checkreg R1, 0xb6a1ffff; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x58904e00 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x30900810 | _VS | _AV1S | _AC1 | _AQ | _CC); + dmm32 A1.w, 0xd0762eff; + dmm32 A1.x, 0xffffffff; + imm32 R0, 0x00000000; + imm32 R1, 0x1d9b7fff; + imm32 R3, 0xf32bf32b; + R0.H = (A1 += R1.L * R3.L) (M, IU); + checkreg R0, 0x7fff0000; + checkreg A1.w, 0x4a0abbd4; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x30900810 | _VS | _V | _AV1S | _AC1 | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x74408290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY); + dmm32 A1.w, 0xf1008000; + dmm32 A1.x, 0xffffffff; + imm32 R3, 0x0bb78001; + imm32 R5, 0x0be78000; + imm32 R7, 0x17cd9a40; + R3.H = (A1 += R7.L * R5.L) (M, IU); + checkreg R3, 0x80008001; + checkreg A1.w, 0xbe208000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x74408290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x40900490 | _VS | _AV1S); + dmm32 A1.w, 0xa9d97d12; + dmm32 A1.x, 0xffffffff; + imm32 R0, 0x4e01ffff; + imm32 R3, 0x12abdd35; + imm32 R7, 0xa9d966d6; + R7.H = (A1 += R0.L * R3.L) (M, IU); + checkreg R7, 0x800066d6; + checkreg A1.w, 0xa9d89fdd; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x40900490 | _VS | _V | _AV1S | _V_COPY); + + dmm32 ASTAT, (0x20a04290 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN); + dmm32 A1.w, 0xe552d880; + dmm32 A1.x, 0xffffffff; + imm32 R3, 0xfe6bf901; + imm32 R5, 0xfae40000; + imm32 R6, 0x3917f106; + R5.H = (A1 += R6.L * R3.H) (M, IU); + checkreg R5, 0x80000000; + checkreg A1.w, 0xd6708a02; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x20a04290 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x2050c490 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0xfcd2b056; + dmm32 A1.x, 0xffffffff; + imm32 R2, 0xff36c118; + imm32 R4, 0xfffe0001; + imm32 R7, 0x7fff00f4; + R7.H = (A1 += R2.L * R4.H) (M, IU); + checkreg R7, 0x800000f4; + checkreg A1.w, 0xbdeb2e26; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x2050c490 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x30708290 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ); + dmm32 A1.w, 0x391f1bbc; + dmm32 A1.x, 0x0000004d; + imm32 R3, 0xae387ec2; + imm32 R4, 0x7fff99ff; + imm32 R5, 0x46730cf4; + R5 = (A1 += R4.L * R3.H) (M, IU); + checkreg R5, 0x7fffffff; + checkreg A1.w, 0xf3b41d84; + checkreg A1.x, 0x0000004c; + checkreg ASTAT, (0x30708290 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x60d00200 | _VS | _AV1S | _CC); + dmm32 A1.w, 0x002b5780; + dmm32 A1.x, 0x00000000; + imm32 R1, 0xa07dffff; + imm32 R2, 0xf90db994; + imm32 R4, 0x46150060; + R2.H = (A1 -= R1.L * R4.L) (M, IU); + checkreg R2, 0x7fffb994; + checkreg A1.w, 0x002b57e0; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x60d00200 | _VS | _V | _AV1S | _CC | _V_COPY); + + dmm32 ASTAT, (0x5c600a80 | _VS | _V | _AV1S | _AV1 | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0x52768086; + dmm32 A1.x, 0x00000035; + imm32 R2, 0x1e89d049; + imm32 R6, 0x5312dd14; + imm32 R7, 0x02e3d1f4; + R7 = (A1 += R2.L * R6.L) (M, IU); + checkreg R7, 0x7fffffff; + checkreg A1.w, 0x2941cb3a; + checkreg A1.x, 0x00000035; + checkreg ASTAT, (0x5c600a80 | _VS | _V | _AV1S | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x60908080 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ); + dmm32 A1.w, 0x00005d96; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x00006828; + imm32 R5, 0xfffe5480; + imm32 R7, 0x40000009; + R5 = (A1 -= R1.L * R7.H) (M, IU); + checkreg R5, 0xe5f65d96; + checkreg A1.w, 0xe5f65d96; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x60908080 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x3cb08080 | _VS | _AC1 | _CC | _AC0_COPY | _AZ); + dmm32 A1.w, 0x8b063fca; + dmm32 A1.x, 0xffffffa2; + imm32 R3, 0x5f5b566b; + imm32 R4, 0x800022e6; + imm32 R5, 0x741acdad; + R3 = (A1 += R5.L * R4.L) (M, IU); + checkreg R3, 0x80000000; + checkreg A1.w, 0x842a0338; + checkreg A1.x, 0xffffffa2; + checkreg ASTAT, (0x3cb08080 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x60d08a00 | _VS | _AC0 | _AQ | _AN); + dmm32 A1.w, 0x54eebd9e; + dmm32 A1.x, 0x00000000; + imm32 R5, 0x05fa881c; + imm32 R7, 0xb0728448; + R5 = (A1 -= R7.L * R5.L) (M, IU); + checkreg R5, 0x7fffffff; + checkreg A1.w, 0x96b605be; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x60d08a00 | _VS | _V | _AC0 | _AQ | _V_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0021.S b/sim/testsuite/bfin/random_0021.S new file mode 100644 index 0000000..2497a44 --- /dev/null +++ b/sim/testsuite/bfin/random_0021.S @@ -0,0 +1,45 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x5c604280 | _VS | _AV1S | _AV0S); + imm32 R3, 0xfe0103fe; + imm32 R5, 0x1e53cdd8; + R3.H = R5.L * R3.H (M, IU); + checkreg R3, 0x800003fe; + checkreg ASTAT, (0x5c604280 | _VS | _V | _AV1S | _AV0S | _V_COPY); + + dmm32 ASTAT, (0x74a04c00 | _VS | _AV1S | _CC | _AN); + imm32 R4, 0xfffeffff; + imm32 R5, 0x174e174e; + R5.H = R4.L * R5.H (M, IU); + checkreg R5, 0xe8b2174e; + checkreg ASTAT, (0x74a04c00 | _VS | _AV1S | _CC | _AN); + + dmm32 ASTAT, (0x34308890 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AN); + imm32 R3, 0x7fffffff; + imm32 R4, 0x077b8000; + imm32 R7, 0x03bd03bd; + R3.H = R4.L * R7.H (M, IU); + checkreg R3, 0x8000ffff; + checkreg ASTAT, (0x34308890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x58700a90 | _VS | _AV1S | _AC1 | _AQ | _CC | _AN); + imm32 R1, 0x58978212; + imm32 R3, 0x62b5775a; + imm32 R6, 0x4c9c9ee3; + R6.H = R1.L * R3.L (M, IU); + checkreg R6, 0x80009ee3; + checkreg ASTAT, (0x58700a90 | _VS | _V | _AV1S | _AC1 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x40204e00 | _VS | _AV1S | _AV0S | _CC | _AN); + imm32 R3, 0x297fee00; + imm32 R5, 0x79aa9d21; + imm32 R6, 0xfffe7484; + R6.H = R5.L * R3.L (M, IU); + checkreg R6, 0x80007484; + checkreg ASTAT, (0x40204e00 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0022.S b/sim/testsuite/bfin/random_0022.S new file mode 100644 index 0000000..fce2803 --- /dev/null +++ b/sim/testsuite/bfin/random_0022.S @@ -0,0 +1,212 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x2090c600 | _VS | _AC1 | _AQ | _CC | _AN); + dmm32 A0.w, 0xf041e418; + dmm32 A0.x, 0xffffffff; + imm32 R4, 0x51296cc2; + imm32 R7, 0xca05cb74; + R4.L = (A0 += R7.H * R4.L) (TFU); + checkreg R4, 0x5129ffff; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x2090c600 | _VS | _V | _AV0S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x68508090 | _VS | _AV0S | _AC1 | _AC0_COPY); + dmm32 A1.w, 0xf934c2ea; + dmm32 A1.x, 0xffffffff; + imm32 R0, 0x4c8c85a2; + imm32 R1, 0x13507fff; + imm32 R7, 0x1bd0df6a; + R0.H = (A1 += R7.L * R1.L) (TFU); + checkreg R0, 0xffff85a2; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x68508090 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x54e0c200 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0xed4a5c88; + dmm32 A0.x, 0xffffffff; + imm32 R1, 0x1332a428; + imm32 R4, 0x59fd2452; + imm32 R6, 0x001fffc3; + R4.L = (A0 += R1.H * R6.L) (TFU); + checkreg R4, 0x59fdffff; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x54e0c200 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x70500000 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN); + dmm32 A0.w, 0xb959adf4; + dmm32 A0.x, 0xffffffff; + imm32 R0, 0xffc20000; + imm32 R4, 0x9b83ffff; + R0.L = (A0 += R4.L * R4.H) (TFU); + checkreg R0, 0xffc2ffff; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x70500000 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x58f04890 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); + dmm32 A0.w, 0xfd1277cc; + dmm32 A0.x, 0xffffffff; + imm32 R5, 0xfffdffe2; + imm32 R7, 0x1a9bcac8; + R5.L = (A0 += R5.H * R7.L) (TFU); + checkreg R5, 0xfffdffff; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x58f04890 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x2840ce90 | _VS | _AV0S | _AC1 | _AC0 | _AC0_COPY); + dmm32 A1.w, 0x1543f138; + dmm32 A1.x, 0xffffffce; + imm32 R3, 0xf4620000; + imm32 R4, 0x80008000; + imm32 R7, 0x0d156000; + R4.H = (A1 -= R3.L * R7.L) (M, TFU); + checkreg R4, 0x80008000; + checkreg A1.w, 0x1543f138; + checkreg A1.x, 0xffffffce; + checkreg ASTAT, (0x2840ce90 | _VS | _V | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x04000c90 | _AV0S | _AC0 | _AC0_COPY | _AN); + dmm32 A1.w, 0x7c7b42a9; + dmm32 A1.x, 0x00000027; + imm32 R2, 0x28454c31; + imm32 R5, 0xf220f1b0; + imm32 R6, 0x257ab18b; + R2.H = (A1 -= R5.L * R6.L) (M, TFU); + checkreg R2, 0x7fff4c31; + checkreg A1.w, 0x86685819; + checkreg A1.x, 0x00000027; + checkreg ASTAT, (0x04000c90 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x6810ce80 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x00008000; + imm32 R6, 0x5857bcbe; + R6.H = (A1 = R6.L * R0.L) (M, TFU); + checkreg R6, 0xde5fbcbe; + checkreg A1.w, 0xde5f0000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x6810ce80 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x78c00c80 | _VS | _V | _AC0 | _V_COPY | _AN); + dmm32 A1.w, 0x63391186; + dmm32 A1.x, 0x0000005e; + imm32 R2, 0x34a8b6ef; + imm32 R7, 0x7c8142e2; + R7.H = (A1 = R2.L * R2.H) (M, TFU); + checkreg R7, 0xf0f842e2; + checkreg A1.w, 0xf0f898d8; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x78c00c80 | _VS | _AC0 | _AN); + + dmm32 ASTAT, (0x70704410 | _VS | _V | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0x3fff0001; + dmm32 A1.x, 0x00000000; + imm32 R0, 0xffffffff; + imm32 R7, 0x80007fff; + R7.H = (A1 = R0.L * R7.L) (M, TFU); + checkreg R7, 0xffff7fff; + checkreg A1.w, 0xffff8001; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x70704410 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x00b08610 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0xe75e6c55; + dmm32 A1.x, 0xffffffff; + imm32 R1, 0x5073b60d; + imm32 R3, 0x1c5eecaf; + R1.H = (A1 = R3.L * R3.H) (M, TFU); + checkreg R1, 0xfddcb60d; + checkreg A1.w, 0xfddc0c42; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x00b08610 | _VS | _AV1S | _AV0S | _AV0 | _AQ | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x00304690 | _AV1 | _AV0S | _AV0 | _AQ | _AZ); + dmm32 A1.w, 0x2ef1b58e; + dmm32 A1.x, 0xffffffd7; + imm32 R3, 0x37807856; + imm32 R4, 0x2cd7d02c; + imm32 R5, 0x4435ba51; + R4.H = (A1 -= R3.L * R5.L) (M, TFU); + checkreg R4, 0x8000d02c; + checkreg A1.w, 0xd75d2658; + checkreg A1.x, 0xffffffd6; + checkreg ASTAT, (0x00304690 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AZ); + + dmm32 ASTAT, (0x74c0c600 | _VS | _AV1 | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0x4325067d; + dmm32 A1.x, 0xffffffee; + imm32 R0, 0x35ca7288; + imm32 R5, 0x5ec6e257; + R0.H = (A1 += R0.L * R5.H) (M, TFU); + checkreg R0, 0x80007288; + checkreg A1.w, 0x6d8b8bad; + checkreg A1.x, 0xffffffee; + checkreg ASTAT, (0x74c0c600 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x50704690 | _VS | _AQ); + dmm32 A1.w, 0xd0cea2a8; + dmm32 A1.x, 0xffffffff; + imm32 R0, 0x11b4e24e; + imm32 R2, 0xecd6793c; + imm32 R7, 0x329c2dd6; + R0.H = (A1 -= R7.L * R2.L) (M, TFU); + checkreg R0, 0xbb19e24e; + checkreg A1.w, 0xbb19be80; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x50704690 | _VS | _AQ); + + dmm32 ASTAT, (0x10d08000 | _VS | _AC1 | _AN); + dmm32 A1.w, 0x32dd86a1; + dmm32 A1.x, 0xffffffd7; + imm32 R1, 0xb2310000; + imm32 R3, 0xd63992d2; + imm32 R5, 0x2b93b27f; + R5.H = (A1 += R3.L * R1.L) (M, TFU); + checkreg R5, 0x8000b27f; + checkreg A1.w, 0x32dd86a1; + checkreg A1.x, 0xffffffd7; + checkreg ASTAT, (0x10d08000 | _VS | _V | _AC1 | _V_COPY | _AN); + + dmm32 ASTAT, (0x3010c600 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0xf99eabd6; + dmm32 A1.x, 0xffffffff; + imm32 R2, 0x0c196618; + imm32 R5, 0x00008000; + imm32 R6, 0x6617ffff; + R5.H = (A1 -= R6.L * R2.L) (M, TFU); + checkreg R5, 0xf99f8000; + checkreg A1.w, 0xf99f11ee; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x3010c600 | _VS | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _AC0_COPY); + + dmm32 ASTAT, (0x30f0ca80 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AN); + dmm32 A0.w, 0x74ea7d56; + dmm32 A0.x, 0xffffffff; + imm32 R0, 0x29abffff; + imm32 R2, 0xade1ffff; + imm32 R7, 0x20ada3b8; + R0.L = (A0 += R2.L * R7.L) (TFU); + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x30f0ca80 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AN); + + dmm32 ASTAT, (0x48608210 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AN); + dmm32 A0.w, 0x120f0000; + dmm32 A0.x, 0xffffffff; + imm32 R3, 0xfeacf0c4; + R3.L = (A0 += R3.H * R3.H) (TFU); + checkreg R3, 0xfeacffff; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x48608210 | _VS | _V | _AV1S | _AV0S | _AV0 | _CC | _V_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0023.S b/sim/testsuite/bfin/random_0023.S new file mode 100644 index 0000000..9dd2d1a --- /dev/null +++ b/sim/testsuite/bfin/random_0023.S @@ -0,0 +1,97 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x60608a90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0xf41fbf3f; + dmm32 A1.x, 0x00000000; + imm32 R5, 0xd8d95310; + imm32 R6, 0xd0457fff; + R5.H = (A1 -= R6.L * R6.H) (M, FU); + checkreg R5, 0x7fff5310; + checkreg A1.w, 0x8bfe0f84; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x60608a90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x54b0ca90 | _VS | _AV1S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0xf88288c8; + dmm32 A1.x, 0xffffffff; + imm32 R0, 0xfffe6736; + imm32 R2, 0x8000f882; + imm32 R3, 0xffff8391; + R0.H = (A1 += R3.L * R2.L) (M, FU); + checkreg R0, 0x80006736; + checkreg A1.w, 0x7fb7d06a; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x54b0ca90 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x1c500480 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0x9083dd08; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x00000000; + imm32 R4, 0x00002492; + R4.H = (A1 += R4.L * R0.H) (M, FU); + checkreg R4, 0x7fff2492; + checkreg ASTAT, (0x1c500480 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x7c00c810 | _AV1S | _AC1 | _AC0); + dmm32 A1.w, 0x69e86d3f; + dmm32 A1.x, 0xffffffc2; + imm32 R1, 0x64f42c5b; + imm32 R3, 0x4128529d; + R3 = (A1 -= R3.L * R1.L) (M, FU); + checkreg R3, 0x80000000; + checkreg A1.w, 0x5b981370; + checkreg A1.x, 0xffffffc2; + checkreg ASTAT, (0x7c00c810 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY); + + dmm32 ASTAT, (0x5cc0c480 | _VS | _AQ | _CC); + dmm32 A1.w, 0x34bbe964; + dmm32 A1.x, 0x00000036; + imm32 R1, 0x7fffffff; + imm32 R5, 0x7fff427e; + A1 -= R5.L * R1.L (M, FU); + checkreg A1.w, 0xf23e2be2; + checkreg A1.x, 0x00000035; + checkreg ASTAT, (0x5cc0c480 | _VS | _AQ | _CC); + +# here the result is zero, and the _V bit is set + dmm32 ASTAT, 0x0; + dmm32 A0.w, 0x00008492; + dmm32 A0.x, 0x00000000; + imm32 R2, 0x7fff0002; + imm32 R3, 0xfa6e8492; + imm32 R6, 0xffff0002; + R6 = (A0 -= R3.L * R2.L) (FU); + checkreg R6, 0x00000000; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, ( _VS | _V | _AV0S | _AV0 | _V_COPY); + +# here the result is zero, and the _V bit is not set + dmm32 ASTAT, (_V | _V_COPY); + dmm32 A0.w, 0x1fffc000; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x80004000; + imm32 R4, 0x1fffffff; + imm32 R6, 0x80000000; + R4.L = (A0 -= R0.L * R6.H) (FU); + checkreg R4, 0x1fff0000; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (_AV0S | _AV0); + + dmm32 ASTAT, (0x0c108610 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); + dmm32 A0.w, 0x0000eaf0; + dmm32 A0.x, 0x00000000; + imm32 R1, 0x00010000; + imm32 R6, 0xfbf10001; + R1.L = (A0 -= R6.H * R1.H) (FU); + checkreg R1, 0x00010000; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x0c108610 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0024.S b/sim/testsuite/bfin/random_0024.S new file mode 100644 index 0000000..dab8880 --- /dev/null +++ b/sim/testsuite/bfin/random_0024.S @@ -0,0 +1,264 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x3ce00800 | _VS | _AV1S | _AV0S | _AQ | _AZ); + imm32 R2, 0x00000000; + imm32 R4, 0x00000000; + imm32 R7, 0x00000000; + R2 = ASHIFT R7 BY R4.L (S); + checkreg ASTAT, (0x3ce00800 | _VS | _AV1S | _AV0S | _AQ | _AZ); + checkreg R2, 0x00000000; + checkreg R4, 0x00000000; + checkreg R7, 0x00000000; + + dmm32 ASTAT, (0x7c104680 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ); + imm32 R7, 0x00000000; + R7 = R7 << 0xe (S); + checkreg R7, 0x00000000; + checkreg ASTAT, (0x7c104680 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x10d08690 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); + imm32 R2, 0x0000ffff; + imm32 R5, 0x00000000; + R2 = R5 << 0x1a (S); + checkreg R2, 0x00000000; + checkreg ASTAT, (0x10d08690 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x30f08e90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); + imm32 R6, 0x00000000; + R6 = ASHIFT R6 BY R6.L (S); + checkreg ASTAT, (0x30f08e90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); + checkreg R6, 0x00000000; + + dmm32 ASTAT, (0x4060c800 | _VS | _AV0S | _AC1 | _CC | _AZ); + imm32 R5, 0x00000000; + imm32 R7, 0x00000000; + R5 = R7 << 0x15 (S); + checkreg ASTAT, (0x4060c800 | _VS | _AV0S | _AC1 | _CC | _AZ); + checkreg R5, 0x00000000; + checkreg R7, 0x00000000; + + dmm32 ASTAT, (0x78604a10 | _VS | _AN); + imm32 R1, 0x00000000; + imm32 R4, 0xe1a88000; + R4 = R1 << 0xb (S); + checkreg R4, 0x00000000; + checkreg ASTAT, (0x78604a10 | _VS | _AZ); + + dmm32 ASTAT, (0x64304800 | _VS | _AV1S | _AV0S | _AC0_COPY); + imm32 R2, 0x00000000; + imm32 R7, 0x00000000; + R7 = R2 << 0xa (S); + checkreg ASTAT, (0x64304800 | _VS | _AV1S | _AV0S | _AC0_COPY | _AZ); + checkreg R2, 0x00000000; + checkreg R7, 0x00000000; + + dmm32 ASTAT, (0x68f0c280 | _VS | _AC1 | _AC0_COPY | _AN); + imm32 R2, 0x00000000; + imm32 R5, 0x0000f74a; + R5 = R2 << 0x10 (S); + checkreg R5, 0x00000000; + checkreg ASTAT, (0x68f0c280 | _VS | _AC1 | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x54200c80 | _VS | _AV1S | _AV0S | _AQ); + imm32 R1, 0x00000000; + imm32 R2, 0x00000000; + R2 = R1 << 0xa (S); + checkreg ASTAT, (0x54200c80 | _VS | _AV1S | _AV0S | _AQ | _AZ); + checkreg R1, 0x00000000; + checkreg R2, 0x00000000; + + dmm32 ASTAT, (0x20300a80 | _VS | _AV1S | _CC | _AZ); + imm32 R2, 0x00000000; + imm32 R7, 0x00000000; + R7 = R2 << 0x8 (S); + checkreg ASTAT, (0x20300a80 | _VS | _AV1S | _CC | _AZ); + checkreg R2, 0x00000000; + checkreg R7, 0x00000000; + + dmm32 ASTAT, (0x14408e10 | _VS | _AV0S | _AQ | _CC | _AZ); + imm32 R4, 0x0000007f; + imm32 R6, 0x00000000; + R4 = R6 << 0x3 (S); + checkreg R4, 0x00000000; + checkreg ASTAT, (0x14408e10 | _VS | _AV0S | _AQ | _CC | _AZ); + + dmm32 ASTAT, (0x2850c490 | _VS | _AV1S | _AV0S | _AZ); + imm32 R5, 0x00000000; + imm32 R7, 0xf67f0000; + R7 = ASHIFT R5 BY R7.L (S); + checkreg R7, 0x00000000; + checkreg ASTAT, (0x2850c490 | _VS | _AV1S | _AV0S | _AZ); + + dmm32 ASTAT, (0x24a00400 | _VS | _AV1S | _AC0 | _AC0_COPY | _AN); + imm32 R4, 0x00001e68; + imm32 R6, 0x00000000; + R4 = R6 << 0x8 (S); + checkreg R4, 0x00000000; + checkreg ASTAT, (0x24a00400 | _VS | _AV1S | _AC0 | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x34608e00 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY | _AN); + imm32 R1, 0x00000000; + imm32 R5, 0x272beb60; + R5 = R1 << 0xa (S); + checkreg R5, 0x00000000; + checkreg ASTAT, (0x34608e00 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AZ); + + dmm32 ASTAT, (0x20800c90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AN); + imm32 R3, 0x532993ba; + imm32 R5, 0x00000000; + R3 = R5 << 0x9 (S); + checkreg R3, 0x00000000; + checkreg ASTAT, (0x20800c90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x5430c090 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY); + imm32 R1, 0xb1510802; + imm32 R6, 0x00000000; + R1 = R6 << 0x1e (S); + checkreg R1, 0x00000000; + checkreg ASTAT, (0x5430c090 | _VS | _AV0S | _AC0 | _AQ | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x5cf04c90 | _VS | _AV1S | _AC1 | _AQ | _AC0_COPY); + dmm32 A1.w, 0xf9bc55b7; + dmm32 A1.x, 0x0000002a; + imm32 R0, 0x002d0024; + imm32 R1, 0x16970042; + A1 += R0.L * R1.L; + checkreg A1.w, 0xf9bc6847; + checkreg A1.x, 0x0000002a; + checkreg ASTAT, (0x5cf04c90 | _VS | _AV1S | _AC1 | _AQ | _AC0_COPY); + + dmm32 ASTAT, (0x7c804090 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); + imm32 R5, 0x00000000; + imm32 R7, 0xfe773828; + R7 = R5 << 0x19 (S); + checkreg R7, 0x00000000; + checkreg ASTAT, (0x7c804090 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x30f04e90 | _VS | _AV0S | _AC0 | _AQ); + imm32 R3, 0x00000000; + imm32 R7, 0x00000372; + R7 = R3 << 0x6 (S); + checkreg R7, 0x00000000; + checkreg ASTAT, (0x30f04e90 | _VS | _AV0S | _AC0 | _AQ | _AZ); + + dmm32 ASTAT, (0x04708210 | _VS | _AV1S | _AC0 | _AQ | _AN); + imm32 R5, 0x00000000; + imm32 R7, 0x79b3d220; + R7 = R5 << 0x13 (S); + checkreg R7, 0x00000000; + checkreg ASTAT, (0x04708210 | _VS | _AV1S | _AC0 | _AQ | _AZ); + + dmm32 ASTAT, (0x24e08680 | _VS | _AV0S | _AC1 | _CC | _AZ); + imm32 R0, 0x00000000; + imm32 R6, 0x00000000; + imm32 R7, 0xa820afc0; + R6 = ASHIFT R0 BY R7.L (S); + checkreg ASTAT, (0x24e08680 | _VS | _AV0S | _AC1 | _CC | _AZ); + checkreg R0, 0x00000000; + checkreg R6, 0x00000000; + checkreg R7, 0xa820afc0; + + dmm32 ASTAT, (0x0ca0c090 | _VS | _AQ | _AZ); + imm32 R6, 0x00000000; + imm32 R7, 0x0000001f; + R7 = R6 << 0x14 (S); + checkreg R7, 0x00000000; + checkreg ASTAT, (0x0ca0c090 | _VS | _AQ | _AZ); + + dmm32 ASTAT, (0x20204680 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY); + imm32 R6, 0x00000000; + R6 = R6 << 0x15 (S); + checkreg ASTAT, (0x20204680 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AZ); + checkreg R6, 0x00000000; + + dmm32 ASTAT, (0x14f08c00 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ); + imm32 R2, 0x00000000; + imm32 R6, 0x00007fff; + R6 = R2 << 0x1b (S); + checkreg R6, 0x00000000; + checkreg ASTAT, (0x14f08c00 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x50b08c00 | _VS | _AC1 | _AQ | _CC | _AN); + imm32 R1, 0x00000000; + imm32 R4, 0x0000fffd; + R4 = R1 << 0x9 (S); + checkreg R4, 0x00000000; + checkreg ASTAT, (0x50b08c00 | _VS | _AC1 | _AQ | _CC | _AZ); + + dmm32 ASTAT, (0x1cb04200 | _VS | _AV0S | _AC1 | _CC); + imm32 R0, 0x00000000; + imm32 R2, 0xdeab0000; + R2 = R0 << 0x1e (S); + checkreg R2, 0x00000000; + checkreg ASTAT, (0x1cb04200 | _VS | _AV0S | _AC1 | _CC | _AZ); + + dmm32 ASTAT, (0x54c0ca00 | _VS | _AV1S | _AV0S | _AC1); + imm32 R6, 0x00000000; + imm32 R7, 0x9ec9c597; + R7 = R6 << 0x8 (S); + checkreg R7, 0x00000000; + checkreg ASTAT, (0x54c0ca00 | _VS | _AV1S | _AV0S | _AC1 | _AZ); + + dmm32 ASTAT, (0x18804400 | _VS | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AN); + imm32 R7, 0x00000000; + R7 = R7 << 0x1d (S); + checkreg ASTAT, (0x18804400 | _VS | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ); + checkreg R7, 0x00000000; + + dmm32 ASTAT, (0x40c08e90 | _VS | _AV1S | _AV0S | _CC); + imm32 R2, 0x00000000; + imm32 R5, 0x80000000; + imm32 R7, 0x00000000; + R5 = ASHIFT R2 BY R7.L (S); + checkreg R5, 0x00000000; + checkreg ASTAT, (0x40c08e90 | _VS | _AV1S | _AV0S | _CC | _AZ); + + dmm32 ASTAT, (0x70b04290 | _VS | _AV1S | _AV0S | _AQ | _AZ); + imm32 R5, 0x8000c2d0; + imm32 R6, 0x00000000; + R5 = R6 << 0x2 (S); + checkreg R5, 0x00000000; + checkreg ASTAT, (0x70b04290 | _VS | _AV1S | _AV0S | _AQ | _AZ); + + dmm32 ASTAT, (0x7cf04480 | _VS | _AV0S | _AC0 | _AC0_COPY | _AZ); + imm32 R3, 0x00000000; + imm32 R7, 0x00000000; + R7 = ASHIFT R3 BY R7.L (S); + checkreg ASTAT, (0x7cf04480 | _VS | _AV0S | _AC0 | _AC0_COPY | _AZ); + checkreg R3, 0x00000000; + checkreg R7, 0x00000000; + + dmm32 ASTAT, (0x78d0c290 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); + imm32 R1, 0x7c98345a; + imm32 R4, 0x00000000; + R1 = ASHIFT R4 BY R1.L (S); + checkreg R1, 0x00000000; + checkreg ASTAT, (0x78d0c290 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x58400e80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY); + imm32 R2, 0x00000000; + imm32 R4, 0x7fffffff; + R4 = R2 << 0x8 (S); + checkreg R4, 0x00000000; + checkreg ASTAT, (0x58400e80 | _VS | _AV0S | _AQ | _CC | _AZ); + + dmm32 ASTAT, (0x4c804080 | _VS | _V | _AV1S | _AV0S | _AV0 | _V_COPY); + imm32 R3, 0x00000000; + imm32 R7, 0x3d196b66; + R7 = ASHIFT R3 BY R3.L (S); + checkreg R7, 0x00000000; + checkreg ASTAT, (0x4c804080 | _VS | _AV1S | _AV0S | _AV0 | _AZ); + + dmm32 ASTAT, (0x44304a10 | _VS | _AV0S | _AQ | _AZ); + imm32 R4, 0x00000000; + imm32 R6, 0x00000000; + R6 = R4 << 0x11 (S); + checkreg ASTAT, (0x44304a10 | _VS | _AV0S | _AQ | _AZ); + checkreg R4, 0x00000000; + checkreg R6, 0x00000000; + + pass diff --git a/sim/testsuite/bfin/random_0025.S b/sim/testsuite/bfin/random_0025.S new file mode 100644 index 0000000..14cf049 --- /dev/null +++ b/sim/testsuite/bfin/random_0025.S @@ -0,0 +1,681 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x74f00490 | _VS | _V | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + imm32 R0, 0x10cfffff; + imm32 R6, 0x06a1ea20; + R0.H = R6.H >>> 0x1b; + checkreg R0, 0xd420ffff; + checkreg ASTAT, (0x74f00490 | _VS | _V | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x78704000 | _VS | _V | _AC0 | _V_COPY); + imm32 R3, 0x80007fff; + R3.L = R3.L >>> 0x1f; + checkreg R3, 0x8000fffe; + checkreg ASTAT, (0x78704000 | _VS | _V | _AC0 | _V_COPY | _AN); + + dmm32 ASTAT, (0x5ce08c00 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AN); + imm32 R3, 0xef9f04f4; + imm32 R6, 0x11037fff; + R3.L = R6.H >>> 0x1d; + checkreg R3, 0xef9f8818; + checkreg ASTAT, (0x5ce08c00 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x14904890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + imm32 R2, 0x00af03a2; + imm32 R7, 0x0b470440; + R7.L = R2.L >>> 0x1a; + checkreg R7, 0x0b47e880; + checkreg ASTAT, (0x14904890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x3040ca00 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AN); + imm32 R1, 0x3bd8d8ef; + imm32 R7, 0x7b15ffff; + R1.H = R7.H >>> 0x1f; + checkreg R1, 0xf62ad8ef; + checkreg ASTAT, (0x3040ca00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x68404600 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AZ); + imm32 R0, 0xfffffffc; + imm32 R1, 0x7ffffffe; + R0.H = R1.H >>> 0x1f; + checkreg R0, 0xfffefffc; + checkreg ASTAT, (0x68404600 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AN); + + dmm32 ASTAT, (0x54108890 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + imm32 R1, 0x30b38b8d; + imm32 R3, 0x1c830bb1; + R1.H = R3.L >>> 0x1c; + checkreg R1, 0xbb108b8d; + checkreg ASTAT, (0x54108890 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x3cc00e80 | _VS | _AV1S | _AC0); + imm32 R6, 0x1b42549c; + R6.L = R6.L >>> 0x1f; + checkreg R6, 0x1b42a938; + checkreg ASTAT, (0x3cc00e80 | _VS | _V | _AV1S | _AC0 | _V_COPY | _AN); + + dmm32 ASTAT, (0x1ca04490 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY); + imm32 R0, 0x0b040a99; + imm32 R6, 0x2716ffff; + R6.H = R0.L >>> 0x1c; + checkreg R6, 0xa990ffff; + checkreg ASTAT, (0x1ca04490 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x14800880 | _VS | _AC0 | _AN | _AZ); + imm32 R2, 0x7fff7fff; + imm32 R7, 0x0a014f10; + R7 = R2 >>> 0x1f (V); + checkreg R7, 0xfffefffe; + checkreg ASTAT, (0x14800880 | _VS | _V | _AC0 | _V_COPY | _AN); + + dmm32 ASTAT, (0x04a08000 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); + imm32 R7, 0x7fffffff; + R7 = R7 >>> 0x10 (V); + checkreg R7, 0x0000ffff; + checkreg ASTAT, (0x04a08000 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x4c204090 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY); + imm32 R2, 0x00030003; + imm32 R6, 0x2c962c96; + R6 = R2 >>> 0x10 (V); + checkreg R6, 0x00000000; + checkreg ASTAT, (0x4c204090 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x14400e00 | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AQ | _AC0_COPY); + imm32 R0, 0x3a567ee8; + imm32 R4, 0x7e163337; + R0 = R4 >>> 0x10 (V); + checkreg R0, 0x00000000; + checkreg ASTAT, (0x14400e00 | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AQ | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x30200a10 | _VS | _AN); + imm32 R2, 0xffff0f44; + R2 = R2 >>> 0x1c (V); + checkreg R2, 0xfff0f440; + checkreg ASTAT, (0x30200a10 | _VS | _V | _V_COPY | _AN); + + dmm32 ASTAT, (0x10c0c080 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); + imm32 R1, 0x1d4571f3; + imm32 R2, 0x1d45ffff; + R2 = R1 >>> 0x10 (V); + checkreg R2, 0x00000000; + checkreg ASTAT, (0x10c0c080 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x4cd08c90 | _VS | _AV1S | _AV0S | _CC); + imm32 R2, 0x8000ffff; + imm32 R3, 0x0f757fff; + R3 = R2 >>> 0x10 (V); + checkreg R3, 0xffffffff; + checkreg ASTAT, (0x4cd08c90 | _VS | _AV1S | _AV0S | _CC | _AN); + + dmm32 ASTAT, (0x68004a00 | _VS | _AV0S | _AQ | _AN); + imm32 R6, 0x366a7fff; + imm32 R7, 0xe4ca366a; + R7 = R6 >>> 0x1f (V); + checkreg R7, 0x6cd4fffe; + checkreg ASTAT, (0x68004a00 | _VS | _V | _AV0S | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x14c0ca80 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + imm32 R6, 0x3468e405; + imm32 R7, 0x0fd2ee59; + R7 = R6 >>> 0x10 (V); + checkreg R7, 0x0000ffff; + checkreg ASTAT, (0x14c0ca80 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x1460cc90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN | _AZ); + imm32 R3, 0x2b8ffe22; + imm32 R4, 0x2f17d9d2; + R4 = R3 >>> 0x1e (V); + checkreg R4, 0xae3cf888; + checkreg ASTAT, (0x1460cc90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x30d04290 | _VS | _AC1 | _AQ | _CC); + imm32 R1, 0x3afe2bd0; + imm32 R4, 0x57e37450; + R4 = R1 >>> 0x10 (V); + checkreg R4, 0x00000000; + checkreg ASTAT, (0x30d04290 | _VS | _AC1 | _AQ | _CC | _AZ); + + dmm32 ASTAT, (0x04600600 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN); + imm32 R0, 0xedbbfffe; + imm32 R4, 0x169330ac; + R0 = R4 >>> 0x1e (V); + checkreg R0, 0x5a4cc2b0; + checkreg ASTAT, (0x04600600 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY | _AN); + + dmm32 ASTAT, (0x64c0c290 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _CC | _AN); + imm32 R1, 0x788b2d30; + imm32 R6, 0x78f61ce9; + R6 = R1 >>> 0x10 (V); + checkreg R6, 0x00000000; + checkreg ASTAT, (0x64c0c290 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _CC | _AZ); + + dmm32 ASTAT, (0x74d04680 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY); + imm32 R0, 0x0b7d1dc6; + imm32 R7, 0x3d27f3e5; + R7 = R0 >>> 0x10 (V); + checkreg R7, 0x00000000; + checkreg ASTAT, (0x74d04680 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x74900000 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC); + imm32 R5, 0xffc70074; + imm32 R7, 0xf49916ce; + R5 = R7 >>> 0x10 (V); + checkreg R5, 0xffff0000; + checkreg ASTAT, (0x74900000 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AN | _AZ); + + dmm32 ASTAT, (0x6ca0c400 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN); + imm32 R0, 0x1e0287a7; + imm32 R4, 0x30aa2286; + R0 = R4 >>> 0x10 (V); + checkreg R0, 0x00000000; + checkreg ASTAT, (0x6ca0c400 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x10204a00 | _VS | _CC | _AN); + imm32 R5, 0xa6b04dd0; + imm32 R6, 0xfedb4cd8; + R5 = R6 >>> 0x1f (V); + checkreg R5, 0xfdb699b0; + checkreg ASTAT, (0x10204a00 | _VS | _V | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x30e04290 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY); + imm32 R2, 0x0c55766f; + imm32 R3, 0x28c00004; + R2 = R3 >>> 0x10 (V); + checkreg R2, 0x00000000; + checkreg ASTAT, (0x30e04290 | _VS | _AV1S | _AV0S | _AC1 | _AZ); + + dmm32 ASTAT, (0x34b0c410 | _VS | _AQ | _CC); + imm32 R7, 0x0f7b2928; + R7 = R7 >>> 0x1e (V); + checkreg R7, 0x3deca4a0; + checkreg ASTAT, (0x34b0c410 | _VS | _V | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x18504800 | _VS | _AV1S | _AC1 | _AC0_COPY); + imm32 R4, 0x0baad54f; + imm32 R7, 0x05bf0c50; + R4 = R7 >>> 0x10 (V); + checkreg R4, 0x00000000; + checkreg ASTAT, (0x18504800 | _VS | _AV1S | _AC1 | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x2cd04290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY); + imm32 R0, 0x1199ca48; + imm32 R7, 0x4ee24366; + R7 = R0 >>> 0x10 (V); + checkreg R7, 0x0000ffff; + checkreg ASTAT, (0x2cd04290 | _VS | _AV1S | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x24304c90 | _VS | _AV0S | _AC1 | _AC0 | _CC); + imm32 R3, 0x528af4b6; + imm32 R6, 0x18d26b4a; + R3 = R6 >>> 0x10 (V); + checkreg R3, 0x00000000; + checkreg ASTAT, (0x24304c90 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AZ); + + dmm32 ASTAT, (0x70504200 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ); + imm32 R1, 0x255f0000; + imm32 R4, 0x96e0e654; + imm32 R6, 0x255fd442; + R4 = ASHIFT R1 BY R6.L; + checkreg R4, 0x957c0000; + checkreg ASTAT, (0x70504200 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x10004210 | _VS | _AV1S | _AC1 | _AQ); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R3, 0x13f865f4; + A1 = ASHIFT A1 BY R3.L; + checkreg ASTAT, (0x10004210 | _VS | _AV1S | _AC1 | _AQ | _AZ); + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg R3, 0x13f865f4; + + dmm32 ASTAT, (0x1c90c400 | _VS | _AV0S | _AC1 | _AZ); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R3, 0x00000000; + A0 = ASHIFT A0 BY R3.L; + checkreg ASTAT, (0x1c90c400 | _VS | _AV0S | _AC1 | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R3, 0x00000000; + + dmm32 ASTAT, (0x4820c280 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AN); + dmm32 A1.w, 0x00000001; + dmm32 A1.x, 0x00000000; + imm32 R3, 0x4a4a7fff; + A1 = LSHIFT A1 BY R3.L; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x4820c280 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AZ); + + dmm32 ASTAT, (0x1c20cc10 | _VS | _AC1 | _AN); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x00000000; + A1 = LSHIFT A1 BY R0.L; + checkreg ASTAT, (0x1c20cc10 | _VS | _AC1 | _AZ); + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg R0, 0x00000000; + + dmm32 ASTAT, (0x1c608e90 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AC0_COPY | _AZ); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R4, 0x10cb0000; + A0 = ASHIFT A0 BY R4.L; + checkreg ASTAT, (0x1c608e90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R4, 0x10cb0000; + + dmm32 ASTAT, (0x6870ce00 | _VS | _AC1 | _AC0_COPY | _AZ); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R4, 0x00000000; + A1 = LSHIFT A1 BY R4.L; + checkreg ASTAT, (0x6870ce00 | _VS | _AC1 | _AC0_COPY | _AZ); + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg R4, 0x00000000; + + dmm32 ASTAT, (0x04200290 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AZ); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R2, 0x00000000; + A0 = LSHIFT A0 BY R2.L; + checkreg ASTAT, (0x04200290 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R2, 0x00000000; + + dmm32 ASTAT, (0x0c404e80 | _VS | _V | _V_COPY); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R7, 0xc400e200; + A0 = ASHIFT A0 BY R7.L; + checkreg ASTAT, (0x0c404e80 | _VS | _V | _V_COPY | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R7, 0xc400e200; + + dmm32 ASTAT, (0x04e00800 | _VS | _AV1S | _AV0S); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R0, 0xe603ffff; + A0 = LSHIFT A0 BY R0.L; + checkreg ASTAT, (0x04e00800 | _VS | _AV1S | _AV0S | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R0, 0xe603ffff; + + dmm32 ASTAT, (0x40904090 | _VS | _AV0S | _AC1 | _CC | _AZ); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R6, 0x00000000; + A1 = LSHIFT A1 BY R6.L; + checkreg ASTAT, (0x40904090 | _VS | _AV0S | _AC1 | _CC | _AZ); + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg R6, 0x00000000; + + dmm32 ASTAT, (0x24f04c10 | _VS | _V | _AC1 | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x023d0ac0; + dmm32 A0.x, 0x00000000; + imm32 R2, 0xfffe05e0; + A0 = ASHIFT A0 BY R2.L; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x24f04c10 | _VS | _V | _AC1 | _V_COPY | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x2860c410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AC0_COPY); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R4, 0x00000000; + A1 = ASHIFT A1 BY R4.L; + checkreg ASTAT, (0x2860c410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AC0_COPY | _AZ); + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg R4, 0x00000000; + + dmm32 ASTAT, (0x40000a00 | _VS | _V | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AN); + imm32 R2, 0x4e59ffff; + imm32 R6, 0x2c450001; + R6 = ASHIFT R2 BY R6.L (V); + checkreg R6, 0x9cb2fffe; + checkreg ASTAT, (0x40000a00 | _VS | _V | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x3c700410 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AC0_COPY | _AZ); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R6, 0x0d1144c0; + A0 = LSHIFT A0 BY R6.L; + checkreg ASTAT, (0x3c700410 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R6, 0x0d1144c0; + + dmm32 ASTAT, (0x5c10ca80 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ); + dmm32 A1.w, 0x80000000; + dmm32 A1.x, 0x00000000; + imm32 R7, 0x472d2397; + A1 = LSHIFT A1 BY R7.L; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x5c10ca80 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x10004c00 | _VS | _AQ | _AZ); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R2, 0x80000000; + A1 = LSHIFT A1 BY R2.L; + checkreg ASTAT, (0x10004c00 | _VS | _AQ | _AZ); + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg R2, 0x80000000; + + dmm32 ASTAT, (0x30308480 | _VS | _AV0S | _AQ); + dmm32 A0.w, 0x19b289d0; + dmm32 A0.x, 0x00000000; + imm32 R6, 0xffff0ce2; + A0 = LSHIFT A0 BY R6.L; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x30308480 | _VS | _AV0S | _AQ | _AZ); + + dmm32 ASTAT, (0x28708280 | _VS | _AV1S | _AC1 | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0x3f050000; + dmm32 A0.x, 0x00000000; + imm32 R6, 0xc0fb081a; + A0 = LSHIFT A0 BY R6.L; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x28708280 | _VS | _AV1S | _AC1 | _AQ | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x18708280 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AN); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R3, 0xeca83337; + A0 = LSHIFT A0 BY R3.L; + checkreg ASTAT, (0x18708280 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R3, 0xeca83337; + + dmm32 ASTAT, (0x78b0c010 | _VS | _AV1S | _AC1 | _AC0 | _AN); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R5, 0x00000000; + A1 = ASHIFT A1 BY R5.L; + checkreg ASTAT, (0x78b0c010 | _VS | _AV1S | _AC1 | _AC0 | _AZ); + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg R5, 0x00000000; + + dmm32 ASTAT, (0x50d00680 | _VS | _AV1S | _AV0S | _AC1 | _AQ); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R3, 0x05600000; + A1 = LSHIFT A1 BY R3.L; + checkreg ASTAT, (0x50d00680 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AZ); + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg R3, 0x05600000; + + dmm32 ASTAT, (0x04108880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC); + dmm32 A0.w, 0x046b40e7; + dmm32 A0.x, 0x00000000; + imm32 R3, 0x20a220a2; + A0 = ASHIFT A0 BY R3.L; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x04108880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AZ); + + dmm32 ASTAT, (0x6850cc80 | _VS | _AV1S | _AV0S | _AV0 | _AC0_COPY | _AN); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R1, 0x623d1bad; + A0 = ASHIFT A0 BY R1.L; + checkreg ASTAT, (0x6850cc80 | _VS | _AV1S | _AV0S | _AC0_COPY | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R1, 0x623d1bad; + + dmm32 ASTAT, (0x44d04a80 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R4, 0x211b1629; + A1 = LSHIFT A1 BY R4.L; + checkreg ASTAT, (0x44d04a80 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ); + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg R4, 0x211b1629; + + dmm32 ASTAT, (0x1c304480 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _AZ); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R1, 0xffffa0e5; + A0 = ASHIFT A0 BY R1.L; + checkreg ASTAT, (0x1c304480 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R1, 0xffffa0e5; + + dmm32 ASTAT, (0x54c00c90 | _VS | _AV0S | _AC1 | _CC | _AZ); + dmm32 A1.w, 0x01cdbb21; + dmm32 A1.x, 0x00000000; + imm32 R7, 0x696f3de3; + A1 = ASHIFT A1 BY R7.L; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x54c00c90 | _VS | _AV0S | _AC1 | _CC | _AZ); + + dmm32 ASTAT, (0x7c30c690 | _VS | _AV1S | _AV0S | _AC1 | _AC0_COPY | _AN); + dmm32 A1.w, 0x00007400; + dmm32 A1.x, 0x00000000; + imm32 R4, 0x6fc3cc21; + A1 = LSHIFT A1 BY R4.L; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x7c30c690 | _VS | _AV1S | _AV0S | _AC1 | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x1c404200 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AN); + imm32 R2, 0x1e000001; + imm32 R4, 0x037b7038; + imm32 R5, 0x57beffff; + R4.L = ASHIFT R5.H BY R2.L; + checkreg R4, 0x037baf7c; + checkreg ASTAT, (0x1c404200 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x24e08c80 | _VS | _AV1S | _CC); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R6, 0x11f23024; + A0 = LSHIFT A0 BY R6.L; + checkreg ASTAT, (0x24e08c80 | _VS | _AV1S | _CC | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R6, 0x11f23024; + + dmm32 ASTAT, (0x3ce04080 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R2, 0x00000000; + A0 = ASHIFT A0 BY R2.L; + checkreg ASTAT, (0x3ce04080 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R2, 0x00000000; + + dmm32 ASTAT, (0x28800280 | _VS | _AV1S | _AV0S | _CC | _AZ); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x00000000; + A0 = LSHIFT A0 BY R0.L; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x28800280 | _VS | _AV1S | _AV0S | _CC | _AZ); + + dmm32 ASTAT, (0x68708810 | _VS | _V | _AV1S | _AV0S | _AV1 | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0x80000000; + dmm32 A1.x, 0xffffffea; + imm32 R2, 0x0121e8d9; + A1 = ASHIFT A1 BY R2.L; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x68708810 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x24c00890 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x1b9411f4; + A1 = LSHIFT A1 BY R0.L; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x24c00890 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x4480ce00 | _VS | _AC1); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + A1 = A1 << 0x5; + checkreg ASTAT, (0x4480ce00 | _VS | _AC1 | _AZ); + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + + dmm32 ASTAT, (0x6cf0cc10 | _VS | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + A1 = A1 >> 0x3b; + checkreg ASTAT, (0x6cf0cc10 | _VS | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + + dmm32 ASTAT, (0x50d00a80 | _VS | _AV1S | _AV0S | _AC1 | _AN); + dmm32 A1.w, 0x028ab5f4; + dmm32 A1.x, 0x00000000; + A1 = A1 >> 0x1f; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x50d00a80 | _VS | _AV1S | _AV0S | _AC1 | _AZ); + + dmm32 ASTAT, (0x14c00490 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0x0001f0f0; + dmm32 A1.x, 0x00000000; + A1 = A1 >> 0x14; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x14c00490 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x14808a80 | _VS | _AV1S | _AV0S | _AC1 | _AN); + dmm32 A0.w, 0x000fc1a6; + dmm32 A0.x, 0x00000000; + A0 = A0 >> 0x1f; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x14808a80 | _VS | _AV1S | _AV0S | _AC1 | _AZ); + + dmm32 ASTAT, (0x3c80ca90 | _VS | _AV0S | _AC0 | _AQ | _CC | _AZ); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + A1 = A1 >>> 0x1e; + checkreg ASTAT, (0x3c80ca90 | _VS | _AV0S | _AC0 | _AQ | _CC | _AZ); + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000000; + + dmm32 ASTAT, (0x4c200c90 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ); + imm32 R2, 0xf1815f1a; + imm32 R7, 0x0a917fff; + R7.L = R2.L >>> 0x13; + checkreg R7, 0x0a914000; + checkreg ASTAT, (0x4c200c90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x0cf0cc80 | _VS | _AV0S | _AC0_COPY | _AZ); + imm32 R0, 0x000081ad; + imm32 R2, 0x00000000; + R2.H = R0.L >>> 0x19; + checkreg R2, 0xd6800000; + checkreg ASTAT, (0x0cf0cc80 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x04304c10 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY | _AN); + imm32 R1, 0x33dd7fff; + imm32 R7, 0xae86a2f4; + R1 = R7 >>> 0x13 (V); + checkreg R1, 0xc0008000; + checkreg ASTAT, (0x04304c10 | _VS | _V | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x7850c800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN); + imm32 R4, 0x0000fffe; + imm32 R7, 0x5906fc4f; + R4.L = R7.H >>> 0x15; + checkreg R4, 0x00003000; + checkreg ASTAT, (0x7850c800 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY); + + dmm32 ASTAT, (0x64804c90 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN); + imm32 R1, 0x000009e3; + imm32 R4, 0x44418b70; + R1.H = R4.L >>> 0x17; + checkreg R1, 0xe00009e3; + checkreg ASTAT, (0x64804c90 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x2c508410 | _VS | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY | _AZ); + imm32 R0, 0x43d731e2; + imm32 R4, 0x60995f48; + R0.L = R4.H >>> 0x17; + checkreg R0, 0x43d73200; + checkreg ASTAT, (0x2c508410 | _VS | _V | _AV1 | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x0c900010 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + A0 = A0 >>> 0xc; + checkreg ASTAT, (0x0c900010 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + + dmm32 ASTAT, (0x40c00e80 | _VS | _AV1 | _AV0S | _CC | _AN | _AZ); + imm32 R1, 0x0bf14680; + imm32 R3, 0x1875266d; + R3.H = R1.L >>> 0x1d; + checkreg R3, 0x3400266d; + checkreg ASTAT, (0x40c00e80 | _VS | _V | _AV1 | _AV0S | _CC | _V_COPY); + + dmm32 ASTAT, (0x78100a00 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AC0_COPY | _AN); + imm32 R4, 0x67c0a470; + imm32 R7, 0x000026c0; + R4 = R7 >>> 0x1d (V); + checkreg R4, 0x00003600; + checkreg ASTAT, (0x78100a00 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x6cd04610 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY); + imm32 R0, 0x0f9535a6; + imm32 R5, 0x31018b62; + R0 = R5 >>> 0x12 (V); + checkreg R0, 0x40008000; + checkreg ASTAT, (0x6cd04610 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x58a08800 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + imm32 R2, 0x023cffff; + imm32 R6, 0x0d6d8000; + R6.L = R2.H >>> 0x18; + checkreg R6, 0x0d6d3c00; + checkreg ASTAT, (0x58a08800 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x5cc00600 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); + imm32 R2, 0xa9d7c2fd; + imm32 R4, 0xfffed266; + R2.L = R4.L >>> 0x12; + checkreg R2, 0xa9d78000; + checkreg ASTAT, (0x5cc00600 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x5c900400 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY | _AN); + imm32 R1, 0xf37e61a8; + imm32 R4, 0x5522a41c; + R4 = R1 >>> 0x12 (V); + checkreg R4, 0x80000000; + checkreg ASTAT, (0x5c900400 | _VS | _V | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ); + + pass diff --git a/sim/testsuite/bfin/random_0026.S b/sim/testsuite/bfin/random_0026.S new file mode 100644 index 0000000..526b007 --- /dev/null +++ b/sim/testsuite/bfin/random_0026.S @@ -0,0 +1,195 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x4c60c810 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY); + dmm32 A0.w, 0x7fffffff; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x00000000; + imm32 R5, 0x00007fff; + imm32 R7, 0x00000000; + R7.L = (A0 += R0.L * R5.L) (IH); + checkreg R7, 0x00007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x4c60c810 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x00500680 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN); + dmm32 A0.w, 0x80000000; + dmm32 A0.x, 0xffffffff; + imm32 R2, 0xffffffff; + imm32 R4, 0xa8dd8000; + imm32 R7, 0x80000000; + R4.L = (A0 -= R2.L * R7.H) (IH); + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg R4, 0xa8dd8000; + checkreg ASTAT, (0x00500680 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x50408c90 | _VS | _V | _AV1S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AN); + dmm32 A1.w, 0xfa400000; + dmm32 A1.x, 0xffffffad; + imm32 R0, 0x366b1c84; + imm32 R3, 0x7fffffff; + imm32 R7, 0x32528aa5; + R3.H = (A1 += R0.L * R7.L) (M, IH); + checkreg R3, 0x8000ffff; + checkreg A1.w, 0x80000000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x50408c90 | _VS | _V | _AV1S | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x0c400c10 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0xef56cbd3; + dmm32 A1.x, 0x00000000; + imm32 R3, 0x7fff0003; + imm32 R4, 0x385cffff; + imm32 R7, 0x680dffff; + R7.H = (A1 -= R4.L * R3.H) (M, IH); + checkreg R7, 0x7fffffff; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x0c400c10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x2c604c00 | _AV1S | _AV0 | _AC1); + dmm32 A1.w, 0xf54ee9bb; + dmm32 A1.x, 0x0000004a; + imm32 R3, 0x10bb4bdc; + imm32 R4, 0x7f29c57d; + imm32 R7, 0x2c03f00a; + R4.H = (A1 -= R3.L * R7.H) (M, IH); + checkreg R4, 0x7fffc57d; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x2c604c00 | _VS | _V | _AV1S | _AV1 | _AV0 | _AC1 | _V_COPY); + + dmm32 ASTAT, (0x2c304800 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY); + dmm32 A1.w, 0xc1a6b608; + dmm32 A1.x, 0x00000056; + imm32 R2, 0xd0457fff; + imm32 R6, 0xf4b2ffff; + R6.H = (A1 += R2.L * R6.H) (M, IH); + checkreg R6, 0x7fffffff; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x2c304800 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY); + + dmm32 ASTAT, (0x04a08810 | _VS | _AV1S | _AC1 | _AC0 | _AN); + dmm32 A1.w, 0xe9574334; + dmm32 A1.x, 0x00000056; + imm32 R3, 0xffffb2bc; + imm32 R5, 0x03eb4d44; + imm32 R6, 0x33852750; + R5.H = (A1 -= R6.L * R3.L) (M, IH); + checkreg R5, 0x7fff4d44; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x04a08810 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _V_COPY | _AN); + + dmm32 ASTAT, (0x5860c210 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY); + dmm32 A1.w, 0xd5030654; + dmm32 A1.x, 0x0000001c; + imm32 R0, 0x20ccb6ee; + imm32 R2, 0x74c21675; + imm32 R4, 0x7fff7fff; + R2.H = (A1 -= R0.L * R4.L) (M, IH); + checkreg R2, 0x7fff1675; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x5860c210 | _VS | _V | _AV1S | _AV1 | _AC1 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x34800e00 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0xf0b59d3f; + dmm32 A1.x, 0xffffffef; + imm32 R4, 0x28bd7772; + imm32 R6, 0xef66ce6a; + imm32 R7, 0x80000000; + R6.H = (A1 -= R4.L * R7.H) (M, IH); + checkreg R6, 0x8000ce6a; + checkreg A1.w, 0x80000000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x34800e00 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x5c804a90 | _VS | _AV1S | _AV0S | _AQ | _AN); + dmm32 A1.w, 0xc90d8c2f; + dmm32 A1.x, 0xffffffee; + imm32 R0, 0x80006a2f; + imm32 R3, 0x80000000; + R3.H = (A1 += R0.L * R0.H) (M, IH); + checkreg A1.w, 0x80000000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x5c804a90 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x5c90c010 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AN); + dmm32 A1.w, 0x80ca2186; + dmm32 A1.x, 0x00000000; + imm32 R1, 0xf3ec0000; + imm32 R3, 0x5a859a0a; + imm32 R6, 0x19e852d9; + R3.H = (A1 -= R1.L * R6.L) (M, IH); + checkreg R3, 0x7fff9a0a; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x5c90c010 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC0 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x00f00a10 | _VS | _V | _AV0S | _CC | _V_COPY | _AN); + dmm32 A1.w, 0x9f5baab0; + dmm32 A1.x, 0x00000019; + imm32 R1, 0x1bb2489b; + imm32 R6, 0x0aa80127; + R1.H = (A1 -= R6.L * R6.H) (M, IH); + checkreg R1, 0x7fff489b; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x00f00a10 | _VS | _V | _AV1S | _AV1 | _AV0S | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x3c808210 | _VS | _V | _AV1S | _V_COPY | _AN); + dmm32 A1.w, 0xe09f1e24; + dmm32 A1.x, 0x00000025; + imm32 R1, 0x255b55bc; + imm32 R2, 0x7f1bd115; + imm32 R3, 0xbc978902; + R2.H = (A1 -= R3.L * R1.H) (M, IH); + checkreg R2, 0x7fffd115; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x3c808210 | _VS | _V | _AV1S | _AV1 | _V_COPY | _AN); + + dmm32 ASTAT, (0x1ca04600 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0xb80e1ddd; + dmm32 A1.x, 0xffffffca; + imm32 R0, 0x2155a4b5; + imm32 R1, 0x5dd905c2; + imm32 R2, 0x769083dc; + R1.H = (A1 -= R2.L * R0.H) (M, IH); + checkreg R1, 0x800005c2; + checkreg A1.w, 0x80000000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x1ca04600 | _VS | _V | _AV1S | _AV1 | _AV0S | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x1cb0cc90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0xfc7c3973; + dmm32 A1.x, 0xffffff8a; + imm32 R1, 0x58a6c4e7; + imm32 R4, 0x19b16033; + imm32 R6, 0x301ff2ba; + R6.H = (A1 -= R4.L * R1.H) (M, IH); + checkreg R6, 0x8000f2ba; + checkreg A1.w, 0x80000000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x1cb0cc90 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x2c800810 | _VS | _AV1S | _AQ | _CC | _AN); + dmm32 A1.w, 0xd86a7676; + dmm32 A1.x, 0xffffff97; + imm32 R3, 0x443fea83; + imm32 R4, 0x47ed4ac3; + imm32 R6, 0x7fffffff; + R4.H = (A1 += R3.L * R6.L) (M, IH); + checkreg R4, 0x80004ac3; + checkreg A1.w, 0x80000000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x2c800810 | _VS | _V | _AV1S | _AV1 | _AQ | _CC | _V_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0027.S b/sim/testsuite/bfin/random_0027.S new file mode 100644 index 0000000..06ea3c8 --- /dev/null +++ b/sim/testsuite/bfin/random_0027.S @@ -0,0 +1,266 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x2850c890 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY); + dmm32 A1.w, 0xa605868e; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x56dd0982; + imm32 R4, 0x50e37862; + imm32 R5, 0x597fc81a; + R4.H = (A1 -= R5.L * R1.L) (M, IS); + checkreg R4, 0x7fff7862; + checkreg A1.w, 0xa818ff5a; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x2850c890 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x08100a00 | _VS | _AC1 | _AC0 | _CC); + dmm32 A1.w, 0xeb710132; + dmm32 A1.x, 0xffffffcf; + imm32 R4, 0x750d92cc; + imm32 R7, 0xf9a22cee; + R4.H = (A1 -= R7.L * R7.H) (M, IS); + checkreg R4, 0x800092cc; + checkreg A1.w, 0xbfa11496; + checkreg A1.x, 0xffffffcf; + checkreg ASTAT, (0x08100a00 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY); + + dmm32 ASTAT, (0x44e00410 | _VS | _AV0S | _AQ | _AN); + dmm32 A1.w, 0x95489ea8; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x360dca41; + imm32 R4, 0x7fffe848; + imm32 R7, 0x278abda8; + R7 = (A1 -= R4.L * R1.L) (M, IS); + checkreg R7, 0x7fffffff; + checkreg A1.w, 0xa805d460; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x44e00410 | _VS | _V | _AV0S | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x0480c800 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ); + dmm32 A1.w, 0xcfa4f43b; + dmm32 A1.x, 0x0000006c; + imm32 R3, 0x0903dd55; + imm32 R7, 0x7fffc2b1; + A1 -= R3.L * R7.L (M, IS); + checkreg A1.w, 0xea028276; + checkreg A1.x, 0x0000006c; + checkreg ASTAT, (0x0480c800 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x3c204410 | _VS | _AV0S | _AN); + dmm32 A1.w, 0x928b984e; + dmm32 A1.x, 0xffffffd5; + imm32 R5, 0x00003ddd; + imm32 R7, 0x8000ffff; + A1 += R5.L * R7.L (M, IS); + checkreg A1.w, 0xd0685a71; + checkreg A1.x, 0xffffffd5; + checkreg ASTAT, (0x3c204410 | _VS | _AV0S | _AN); + + dmm32 ASTAT, (0x4840c890 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN); + dmm32 A1.w, 0x8837abf1; + dmm32 A1.x, 0x00000000; + imm32 R3, 0x10c90000; + imm32 R7, 0x7fffe6b8; + A1 += R7.L * R3.H (M, IS); + checkreg A1.w, 0x868f5269; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x4840c890 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x78604a80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY); + dmm32 A1.w, 0xdca875cf; + dmm32 A1.x, 0x0000002c; + imm32 R3, 0x4c0892ef; + imm32 R5, 0x001fea98; + R5.H = (A1 += R5.L * R3.H) (M, IS); + checkreg R5, 0x7fffea98; + checkreg A1.w, 0xd64cea8f; + checkreg A1.x, 0x0000002c; + checkreg ASTAT, (0x78604a80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x00a04210 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0xec5ef880; + dmm32 A1.x, 0xfffffffe; + imm32 R0, 0x229657d6; + imm32 R7, 0xedd48000; + A1 += R0.L * R7.L (M, IS); + checkreg A1.w, 0x1849f880; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x00a04210 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x0840ce80 | _VS | _AV1S | _AV0S | _AC1 | _AQ); + dmm32 A1.w, 0xe4a5a6e1; + dmm32 A1.x, 0x00000078; + imm32 R0, 0xf059329d; + imm32 R7, 0x7fff7512; + A1 += R7.L * R0.L (M, IS); + checkreg A1.w, 0xfbcaf6eb; + checkreg A1.x, 0x00000078; + checkreg ASTAT, (0x0840ce80 | _VS | _AV1S | _AV0S | _AC1 | _AQ); + + dmm32 ASTAT, (0x60100810 | _VS | _AV0S | _AQ | _AC0_COPY | _AZ); + dmm32 A1.w, 0xd56a8232; + dmm32 A1.x, 0x00000033; + imm32 R0, 0x09b22c69; + imm32 R7, 0x434f1d64; + A1 -= R0.L * R7.L (M, IS); + checkreg A1.w, 0xd051442e; + checkreg A1.x, 0x00000033; + checkreg ASTAT, (0x60100810 | _VS | _AV0S | _AQ | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x58e08410 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0x86c9a59e; + dmm32 A1.x, 0xffffff9a; + imm32 R1, 0x22573f31; + imm32 R6, 0x2d0c0155; + A1 += R1.L * R6.H (M, IS); + checkreg A1.w, 0x91e838ea; + checkreg A1.x, 0xffffff9a; + checkreg ASTAT, (0x58e08410 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x64a0c690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN); + dmm32 A1.w, 0xc5c840aa; + dmm32 A1.x, 0x00000000; + imm32 R4, 0xffff7fff; + imm32 R7, 0x658e833f; + A1 -= R7.L * R4.H (M, IS); + checkreg A1.w, 0x4288c3e9; + checkreg A1.x, 0x00000001; + checkreg ASTAT, (0x64a0c690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x08804610 | _VS | _V | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AN); + dmm32 A1.w, 0xf1000000; + dmm32 A1.x, 0x00000040; + imm32 R3, 0x0cd4edf1; + imm32 R6, 0x4dfc08b8; + R6.H = (A1 += R6.L * R3.H) (M, IS); + checkreg R6, 0x7fff08b8; + checkreg A1.w, 0xf16fd860; + checkreg A1.x, 0x00000040; + checkreg ASTAT, (0x08804610 | _VS | _V | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x7c004690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN); + dmm32 A1.w, 0xd4deb886; + dmm32 A1.x, 0x00000001; + imm32 R1, 0x80008000; + imm32 R6, 0x22fb6e50; + imm32 R7, 0x3fcb147f; + R1.H = (A1 -= R7.L * R6.L) (M, IS); + checkreg R1, 0x7fff8000; + checkreg A1.w, 0xcc09bed6; + checkreg A1.x, 0x00000001; + checkreg ASTAT, (0x7c004690 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x40a00400 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN); + dmm32 A1.w, 0x9698e35b; + dmm32 A1.x, 0xfffffffc; + imm32 R5, 0x8000038c; + imm32 R6, 0x3152ffff; + A1 -= R6.L * R5.L (M, IS); + checkreg A1.w, 0x9698e6e7; + checkreg A1.x, 0xfffffffc; + checkreg ASTAT, (0x40a00400 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x54c00810 | _VS | _V | _AC1 | _CC | _V_COPY | _AN | _AZ); + dmm32 A1.w, 0x9b02b9c6; + dmm32 A1.x, 0xffffffd4; + imm32 R2, 0xff020105; + imm32 R3, 0xa8ff8000; + R3.H = (A1 -= R2.L * R3.L) (M, IS); + checkreg R3, 0x80008000; + checkreg A1.w, 0x9a8039c6; + checkreg A1.x, 0xffffffd4; + checkreg ASTAT, (0x54c00810 | _VS | _V | _AC1 | _CC | _V_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x58808680 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0x990456b2; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x2b76c7b2; + imm32 R3, 0x659803c8; + imm32 R7, 0x7fffffff; + R3.H = (A1 += R7.L * R0.L) (M, IS); + checkreg R3, 0x7fff03c8; + checkreg A1.w, 0x99038f00; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x58808680 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x3ce04690 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY); + dmm32 A1.w, 0x95d1d45a; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x4331b012; + imm32 R5, 0x7fff8000; + A1 -= R0.L * R5.H (M, IS); + checkreg A1.w, 0xbdc8846c; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x3ce04690 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x30e04410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC); + dmm32 A1.w, 0xcf49e4c9; + dmm32 A1.x, 0x00000000; + imm32 R1, 0xe968a740; + imm32 R3, 0xd7383cd5; + imm32 R6, 0x5a87c89b; + R1 = (A1 += R3.L * R6.H) (M, IS); + checkreg R1, 0x7fffffff; + checkreg A1.w, 0xe4ccdb1c; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x30e04410 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x2cb04890 | _VS | _AC1 | _AQ | _AC0_COPY); + dmm32 A1.w, 0x8bdaf471; + dmm32 A1.x, 0xffffffbd; + imm32 R3, 0x728d99b1; + imm32 R7, 0x181d83c2; + A1 -= R7.L * R3.L (M, IS); + checkreg A1.w, 0xd671e94f; + checkreg A1.x, 0xffffffbd; + checkreg ASTAT, (0x2cb04890 | _VS | _AC1 | _AQ | _AC0_COPY); + + dmm32 ASTAT, (0x20908680 | _VS | _AV0S | _AC1 | _AQ | _CC | _AZ); + dmm32 A1.w, 0xc1cb8a00; + dmm32 A1.x, 0x00000000; + imm32 R1, 0xc1e98ea8; + imm32 R7, 0x0000961f; + A1 -= R7.L * R1.L (M, IS); + checkreg A1.w, 0xfccbd3a8; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x20908680 | _VS | _AV0S | _AC1 | _AQ | _CC | _AZ); + + dmm32 ASTAT, (0x64a0cc80 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AZ); + dmm32 A1.w, 0xfb328cb4; + dmm32 A1.x, 0xffffff9b; + imm32 R2, 0x8000ffff; + imm32 R3, 0x64d21863; + imm32 R6, 0x3b7618a6; + R2.H = (A1 += R3.L * R6.H) (M, IS); + checkreg A1.w, 0x00dc9b56; + checkreg A1.x, 0xffffff9c; + checkreg ASTAT, (0x64a0cc80 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AZ); + + dmm32 ASTAT, (0x3c00ca90 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0xbfb4c632; + dmm32 A1.x, 0x00000044; + imm32 R1, 0x7fffffff; + imm32 R3, 0xf3e9182e; + imm32 R5, 0x3c94d844; + R5.H = (A1 += R1.L * R3.H) (M, IS); + checkreg R5, 0x7fffd844; + checkreg A1.w, 0xbfb3d249; + checkreg A1.x, 0x00000044; + checkreg ASTAT, (0x3c00ca90 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x48c0cc10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); + dmm32 A1.w, 0x83144651; + dmm32 A1.x, 0x00000000; + imm32 R3, 0x04d0ffff; + imm32 R4, 0x9dc8f8d8; + imm32 R7, 0x23180d75; + R3 = (A1 += R4.L * R7.L) (M, IS); + checkreg R3, 0x7fffffff; + checkreg A1.w, 0x82b3f909; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x48c0cc10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); + + pass diff --git a/sim/testsuite/bfin/random_0028.S b/sim/testsuite/bfin/random_0028.S new file mode 100644 index 0000000..2fd31c9 --- /dev/null +++ b/sim/testsuite/bfin/random_0028.S @@ -0,0 +1,220 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x44004010 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY); + dmm32 A1.w, 0x851fa4fc; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x00000000; + imm32 R2, 0x80000000; + imm32 R5, 0x139d77b4; + R5.H = (A1 += R2.L * R0.L) (M, S2RND); + checkreg R5, 0x7fff77b4; + checkreg A1.w, 0x851fa4fc; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x44004010 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x48000600 | _VS | _V | _AV1S | _CC | _V_COPY); + dmm32 A1.w, 0xc5ee7420; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x45f17fff; + imm32 R2, 0x00000000; + imm32 R4, 0xffffffff; + R1 = (A1 -= R2.L * R4.H) (M, S2RND); + checkreg R1, 0x7fffffff; + checkreg A1.w, 0xc5ee7420; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x48000600 | _VS | _V | _AV1S | _CC | _V_COPY); + + dmm32 ASTAT, (0x48500a10 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AZ); + dmm32 A1.w, 0x965cddab; + dmm32 A1.x, 0x00000063; + imm32 R1, 0x1d4cc3e7; + imm32 R3, 0xe7ce9d8e; + imm32 R6, 0x3cc80b2f; + R6.H = (A1 -= R3.L * R1.L) (M, S2RND); + checkreg R6, 0x7fff0b2f; + checkreg A1.w, 0xe1b28889; + checkreg A1.x, 0x00000063; + checkreg ASTAT, (0x48500a10 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x44308410 | _VS | _AV0S | _CC | _AN); + dmm32 A1.w, 0x92315df7; + dmm32 A1.x, 0x0000007e; + imm32 R1, 0x9e4b24e0; + imm32 R4, 0xe3da8000; + imm32 R7, 0x00ba086c; + R1.H = (A1 -= R7.L * R4.H) (M, S2RND); + checkreg R1, 0x7fff24e0; + checkreg A1.w, 0x8ab26dff; + checkreg A1.x, 0x0000007e; + checkreg ASTAT, (0x44308410 | _VS | _V | _AV0S | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x10a00090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0x8ed084bf; + dmm32 A1.x, 0xffffffbe; + imm32 R0, 0x8000ffff; + imm32 R3, 0xbb4e34ef; + imm32 R5, 0x7af8492d; + R5 = (A1 += R3.L * R0.L) (M, S2RND); + checkreg R5, 0x80000000; + checkreg A1.w, 0xc3bf4fd0; + checkreg A1.x, 0xffffffbe; + checkreg ASTAT, (0x10a00090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x10f04e10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AN | _AZ); + dmm32 A1.w, 0x81becdd8; + dmm32 A1.x, 0x00000058; + imm32 R2, 0x14946201; + imm32 R4, 0x1a162edd; + R2.H = (A1 -= R2.L * R4.L) (M, S2RND); + checkreg R2, 0x7fff6201; + checkreg A1.w, 0x6fce04fb; + checkreg A1.x, 0x00000058; + checkreg ASTAT, (0x10f04e10 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x20f04c80 | _VS | _AV0S | _AN); + dmm32 A1.w, 0xe9cc0041; + dmm32 A1.x, 0x00000079; + imm32 R1, 0x0f62a5a2; + imm32 R3, 0x4e8e9bdd; + imm32 R7, 0x6630d991; + R1 = (A1 -= R3.L * R7.H) (M, S2RND); + checkreg R1, 0x7fffffff; + checkreg A1.w, 0x11c4b8d1; + checkreg A1.x, 0x0000007a; + checkreg ASTAT, (0x20f04c80 | _VS | _V | _AV0S | _V_COPY | _AN); + + dmm32 ASTAT, (0x20104e00 | _VS | _AC1 | _AC0 | _AQ | _AN); + dmm32 A1.w, 0xadeb5c67; + dmm32 A1.x, 0xffffffa6; + imm32 R1, 0x07911840; + imm32 R7, 0x01070000; + R7 = (A1 += R1.L * R7.H) (M, S2RND); + checkreg R7, 0x80000000; + checkreg A1.w, 0xae044627; + checkreg A1.x, 0xffffffa6; + checkreg ASTAT, (0x20104e00 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x08e04010 | _VS | _AV0S); + dmm32 A1.w, 0xff80f384; + dmm32 A1.x, 0x00000003; + imm32 R1, 0x00000000; + imm32 R2, 0x8000387c; + imm32 R3, 0x1e547fff; + R2.H = (A1 -= R1.L * R3.L) (M, S2RND); + checkreg R2, 0x7fff387c; + checkreg A1.w, 0xff80f384; + checkreg A1.x, 0x00000003; + checkreg ASTAT, (0x08e04010 | _VS | _V | _AV0S | _V_COPY); + + dmm32 ASTAT, (0x0cf08280 | _VS | _AV1S | _AC1 | _CC | _AN); + dmm32 A1.w, 0x80000000; + dmm32 A1.x, 0xffffff80; + imm32 R2, 0xecc35cac; + imm32 R4, 0x00007fff; + imm32 R7, 0x80000000; + R7 = (A1 -= R4.L * R2.L) (M, S2RND); + checkreg R7, 0x80000000; + checkreg A1.w, 0x51aa5cac; + checkreg A1.x, 0xffffff80; + checkreg ASTAT, (0x0cf08280 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x40c08090 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0xfcbe6525; + dmm32 A1.x, 0x00000039; + imm32 R0, 0x0003f3c0; + imm32 R2, 0xfffffffc; + imm32 R6, 0xffff0000; + R0.H = (A1 -= R2.L * R6.H) (M, S2RND); + checkreg R0, 0x7ffff3c0; + checkreg A1.w, 0xfcc26521; + checkreg A1.x, 0x00000039; + checkreg ASTAT, (0x40c08090 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x00704c10 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY); + dmm32 A1.w, 0xdfbb3c19; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x50407788; + imm32 R4, 0x50407788; + imm32 R6, 0x0d3f0c0a; + R6.H = (A1 -= R4.L * R0.L) (M, S2RND); + checkreg R6, 0x7fff0c0a; + checkreg A1.w, 0xa7eb83d9; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x00704c10 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x3c50c610 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); + dmm32 A1.w, 0xbc7ca70b; + dmm32 A1.x, 0xffffff80; + imm32 R1, 0x76b3a772; + imm32 R2, 0x5cc87864; + imm32 R5, 0x33169c34; + R1 = (A1 += R2.L * R5.H) (M, S2RND); + checkreg R1, 0x80000000; + checkreg A1.w, 0xd482eba3; + checkreg A1.x, 0xffffff80; + checkreg ASTAT, (0x3c50c610 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x50008480 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY); + dmm32 A1.w, 0xd843bd0f; + dmm32 A1.x, 0x00000027; + imm32 R0, 0xc5d36b7c; + imm32 R7, 0x7fff8000; + R0.H = (A1 += R0.L * R7.L) (M, S2RND); + checkreg R0, 0x7fff6b7c; + checkreg A1.w, 0x0e01bd0f; + checkreg A1.x, 0x00000028; + checkreg ASTAT, (0x50008480 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x50208610 | _VS | _V | _AV1S | _AV0S | _V_COPY | _AN); + dmm32 A1.w, 0xcf30f0be; + dmm32 A1.x, 0xffffffad; + imm32 R0, 0x6d8f3470; + imm32 R4, 0x4174b386; + imm32 R6, 0x0793b3dd; + R0.H = (A1 -= R4.L * R6.H) (M, S2RND); + checkreg R0, 0x80003470; + checkreg A1.w, 0xd17430cc; + checkreg A1.x, 0xffffffad; + checkreg ASTAT, (0x50208610 | _VS | _V | _AV1S | _AV0S | _V_COPY | _AN); + + dmm32 ASTAT, (0x60700c10 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0xc867b111; + dmm32 A1.x, 0xffffff90; + imm32 R4, 0x580f445e; + imm32 R5, 0x1fb2e64b; + imm32 R6, 0xb6bc814b; + R6.H = (A1 += R5.L * R4.L) (M, S2RND); + checkreg R6, 0x8000814b; + checkreg A1.w, 0xc18a2c9b; + checkreg A1.x, 0xffffff90; + checkreg ASTAT, (0x60700c10 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x4070c080 | _AV0S | _CC); + dmm32 A1.w, 0xe1239b9f; + dmm32 A1.x, 0xffffffcd; + imm32 R4, 0xe4d2beb4; + imm32 R5, 0x1c919600; + imm32 R6, 0x18356124; + R5.H = (A1 -= R4.L * R6.L) (M, S2RND); + checkreg R5, 0x80009600; + checkreg A1.w, 0xf9ea964f; + checkreg A1.x, 0xffffffcd; + checkreg ASTAT, (0x4070c080 | _VS | _V | _AV0S | _CC | _V_COPY); + + dmm32 ASTAT, (0x50608210 | _VS | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0xe8c00d5a; + dmm32 A1.x, 0xffffffbe; + imm32 R1, 0x2baf99f2; + imm32 R4, 0x03e69887; + imm32 R7, 0x07f45a0f; + R1 = (A1 -= R7.L * R4.H) (M, S2RND); + checkreg R1, 0x80000000; + checkreg A1.w, 0xe760f6e0; + checkreg A1.x, 0xffffffbe; + checkreg ASTAT, (0x50608210 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0029.S b/sim/testsuite/bfin/random_0029.S new file mode 100644 index 0000000..c754995 --- /dev/null +++ b/sim/testsuite/bfin/random_0029.S @@ -0,0 +1,184 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x2030ca00 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); + dmm32 A1.w, 0xdf7ce5c7; + dmm32 A1.x, 0xffffff9c; + imm32 R0, 0x098ecb70; + imm32 R1, 0x80000000; + R1.H = (A1 += R0.L * R1.H) (M, ISS2); + checkreg R1, 0x80000000; + checkreg A1.w, 0xc534e5c7; + checkreg A1.x, 0xffffff9c; + checkreg ASTAT, (0x2030ca00 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x00100600 | _VS | _AQ | _AZ); + dmm32 A1.w, 0xdf39474d; + dmm32 A1.x, 0xffffffd9; + imm32 R2, 0x64864b87; + imm32 R3, 0x61a97f85; + imm32 R6, 0x1bcacb1a; + R2.H = (A1 -= R6.L * R3.L) (M, ISS2); + checkreg R2, 0x80004b87; + checkreg A1.w, 0xf992dccb; + checkreg A1.x, 0xffffffd9; + checkreg ASTAT, (0x00100600 | _VS | _V | _AQ | _V_COPY | _AZ); + + dmm32 ASTAT, (0x50f0c290 | _VS | _AC0 | _AQ | _CC | _AC0_COPY); + dmm32 A1.w, 0xb0a49eb4; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x1a1607f3; + imm32 R1, 0x6dcc7fff; + imm32 R6, 0x80008000; + R6.H = (A1 -= R1.L * R0.H) (M, ISS2); + checkreg R6, 0x7fff8000; + checkreg A1.w, 0xa399b8ca; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x50f0c290 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x48b04c10 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0x91b35cde; + dmm32 A1.x, 0x0000006c; + imm32 R1, 0xf473c458; + imm32 R5, 0x1358b0c2; + imm32 R7, 0xfbf00410; + R5.H = (A1 -= R1.L * R7.H) (M, ISS2); + checkreg R5, 0x7fffb0c2; + checkreg A1.w, 0xcc69025e; + checkreg A1.x, 0x0000006c; + checkreg ASTAT, (0x48b04c10 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x1ca04210 | _VS | _AC0 | _AQ | _AN | _AZ); + dmm32 A1.w, 0xf516677c; + dmm32 A1.x, 0x00000015; + imm32 R5, 0x218d4960; + imm32 R6, 0xfa8c8000; + R5 = (A1 -= R6.L * R5.H) (M, ISS2); + checkreg R5, 0x7fffffff; + checkreg A1.w, 0x05dce77c; + checkreg A1.x, 0x00000016; + checkreg ASTAT, (0x1ca04210 | _VS | _V | _AC0 | _AQ | _V_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x04004490 | _VS | _AC1 | _AN); + dmm32 A1.w, 0xd1795d0a; + dmm32 A1.x, 0x00000000; + imm32 R2, 0x67bd270e; + imm32 R3, 0xda302534; + imm32 R7, 0x7fffa2af; + R2.H = (A1 += R7.L * R3.L) (M, ISS2); + checkreg R2, 0x7fff270e; + checkreg A1.w, 0xc3e9b396; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x04004490 | _VS | _V | _AC1 | _V_COPY | _AN); + + dmm32 ASTAT, (0x60600490 | _VS | _AV1S | _AC1 | _CC | _AC0_COPY | _AZ); + dmm32 A1.w, 0xeb8abaea; + dmm32 A1.x, 0x00000036; + imm32 R1, 0x111687e8; + imm32 R5, 0x111687e8; + R1 = (A1 += R1.L * R5.L) (M, ISS2); + checkreg R1, 0x7fffffff; + checkreg A1.w, 0xabc93d2a; + checkreg A1.x, 0x00000036; + checkreg ASTAT, (0x60600490 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x30200e80 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY | _AN); + dmm32 A1.w, 0xd3275e78; + dmm32 A1.x, 0xffffff89; + imm32 R3, 0xfee80d8d; + imm32 R6, 0x1c1a8000; + imm32 R7, 0x00000000; + R3 = (A1 += R7.L * R6.L) (M, ISS2); + checkreg R3, 0x80000000; + checkreg A1.w, 0xd3275e78; + checkreg A1.x, 0xffffff89; + checkreg ASTAT, (0x30200e80 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x50208610 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY); + dmm32 A1.w, 0xb3b71810; + dmm32 A1.x, 0x00000000; + imm32 R4, 0xfc2f7ffe; + imm32 R5, 0x7fffffff; + imm32 R7, 0x3488c040; + R7.H = (A1 -= R4.L * R5.H) (M, ISS2); + checkreg R7, 0x7fffc040; + checkreg A1.w, 0x73b8980e; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x50208610 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x48d04410 | _VS | _AV1S | _AV0S | _AC0 | _AQ); + dmm32 A1.w, 0xeb066305; + dmm32 A1.x, 0xffffff9c; + imm32 R0, 0x80002105; + imm32 R4, 0xf4fbe11e; + imm32 R7, 0xffffb83a; + R7 = (A1 += R0.L * R4.L) (M, ISS2); + checkreg R7, 0x80000000; + checkreg A1.w, 0x080fa69b; + checkreg A1.x, 0xffffff9d; + checkreg ASTAT, (0x48d04410 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x3850c090 | _VS | _AV1S | _AV0S | _AC1 | _CC); + dmm32 A1.w, 0xdfed6537; + dmm32 A1.x, 0xffffffae; + imm32 R0, 0xe962c700; + imm32 R4, 0x32c97fff; + imm32 R7, 0x28da7373; + R4.H = (A1 += R7.L * R0.H) (M, ISS2); + checkreg R4, 0x80007fff; + checkreg A1.w, 0x492d423d; + checkreg A1.x, 0xffffffaf; + checkreg ASTAT, (0x3850c090 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY); + + dmm32 ASTAT, (0x78a0ce00 | _VS | _AV1S | _AC0 | _AQ | _CC); + dmm32 A1.w, 0x8c733a78; + dmm32 A1.x, 0x0000002d; + imm32 R1, 0x3840acb0; + imm32 R3, 0x47b843ad; + imm32 R7, 0x7fff4d00; + R7 = (A1 += R1.L * R3.H) (M, ISS2); + checkreg R7, 0x7fffffff; + checkreg A1.w, 0x751c28f8; + checkreg A1.x, 0x0000002d; + checkreg ASTAT, (0x78a0ce00 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x3cf08880 | _VS | _AV1S | _AV0S | _AC0); + dmm32 A1.w, 0xbde0b55f; + dmm32 A1.x, 0xfffffffd; + imm32 R0, 0x80002300; + imm32 R5, 0x635db45a; + imm32 R7, 0x67e67af3; + R7 = (A1 += R0.L * R5.L) (M, ISS2); + checkreg R7, 0x80000000; + checkreg A1.w, 0xd689035f; + checkreg A1.x, 0xfffffffd; + checkreg ASTAT, (0x3cf08880 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY); + + dmm32 ASTAT, (0x58608410 | _VS | _AQ | _CC | _AZ); + dmm32 A1.w, 0xe4660b32; + dmm32 A1.x, 0xffffff84; + imm32 R1, 0x2c6c9118; + imm32 R2, 0x007793ad; + imm32 R7, 0x526c17d9; + R1.H = (A1 -= R2.L * R7.L) (M, ISS2); + checkreg R1, 0x80009118; + checkreg A1.w, 0xee7d528d; + checkreg A1.x, 0xffffff84; + checkreg ASTAT, (0x58608410 | _VS | _V | _AQ | _CC | _V_COPY | _AZ); + + dmm32 ASTAT, (0x2020c210 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN); + dmm32 A1.w, 0x8da6c28f; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x0000fff7; + imm32 R4, 0xf85a0000; + imm32 R7, 0x7fff0000; + R7 = (A1 += R4.L * R1.L) (M, ISS2); + checkreg R7, 0x7fffffff; + checkreg A1.w, 0x8da6c28f; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x2020c210 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0030.S b/sim/testsuite/bfin/random_0030.S new file mode 100644 index 0000000..417fb28 --- /dev/null +++ b/sim/testsuite/bfin/random_0030.S @@ -0,0 +1,177 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x00a0cc80 | _VS | _AV1S | _AQ | _CC | _AN); + dmm32 A1.w, 0x8f7fea28; + dmm32 A1.x, 0x00000005; + imm32 R2, 0x000014f2; + imm32 R4, 0x7fff7fff; + imm32 R7, 0x14d3a258; + R7.H = (A1 -= R4.L * R2.H) (M, T); + checkreg R7, 0x7fffa258; + checkreg A1.w, 0x8f7fea28; + checkreg A1.x, 0x00000005; + checkreg ASTAT, (0x00a0cc80 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x7c90c410 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY); + dmm32 A1.w, 0xbfed6ffc; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x7fffffff; + imm32 R5, 0x00000000; + imm32 R6, 0xf70a7fff; + R0.H = (A1 -= R5.L * R6.L) (M, T); + checkreg ASTAT, (0x7c90c410 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY); + checkreg A1.w, 0xbfed6ffc; + checkreg A1.x, 0x00000000; + checkreg R0, 0x7fffffff; + checkreg R5, 0x00000000; + checkreg R6, 0xf70a7fff; + + dmm32 ASTAT, (0x2c508a10 | _VS | _AV1S | _AV0S | _AC1 | _AQ); + dmm32 A1.w, 0xfffd8001; + dmm32 A1.x, 0x00000000; + imm32 R3, 0x00018000; + imm32 R4, 0x7fff8000; + imm32 R5, 0x7fff0002; + R3.H = (A1 += R5.L * R4.L) (M, T); + checkreg R3, 0x7fff8000; + checkreg A1.w, 0xfffe8001; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x2c508a10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x28408c90 | _VS | _AV1S | _AC0 | _AQ | _AC0_COPY | _AN); + dmm32 A1.w, 0x842fbc0a; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x04c44422; + imm32 R3, 0x40f67fff; + imm32 R7, 0x448c0856; + R7.H = (A1 -= R3.L * R0.H) (M, T); + checkreg R7, 0x7fff0856; + checkreg A1.w, 0x81cdc0ce; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x28408c90 | _VS | _V | _AV1S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x44708c10 | _AV1S | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0xaa016cf5; + dmm32 A1.x, 0xffffffdb; + imm32 R2, 0x25908079; + imm32 R5, 0x46eabfcd; + imm32 R7, 0x67066230; + R2.H = (A1 += R5.L * R7.H) (M, T); + checkreg R2, 0x80008079; + checkreg A1.w, 0x902b66c3; + checkreg A1.x, 0xffffffdb; + checkreg ASTAT, (0x44708c10 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x3c604090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0x8eef28b0; + dmm32 A1.x, 0x00000023; + imm32 R0, 0x000156b2; + imm32 R1, 0xfc1a8000; + imm32 R5, 0x7fff7fff; + R5.H = (A1 += R1.L * R0.H) (M, T); + checkreg A1.w, 0x8eeea8b0; + checkreg A1.x, 0x00000023; + checkreg ASTAT, (0x3c604090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x74208e00 | _VS | _AV0S | _AC0 | _AQ | _AC0_COPY); + dmm32 A1.w, 0xed3c9973; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x80000000; + imm32 R1, 0x7fff8000; + imm32 R2, 0x00000000; + R1.H = (A1 -= R2.L * R0.H) (M, T); + checkreg ASTAT, (0x74208e00 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY); + checkreg A1.w, 0xed3c9973; + checkreg A1.x, 0x00000000; + checkreg R0, 0x80000000; + checkreg R1, 0x7fff8000; + checkreg R2, 0x00000000; + + dmm32 ASTAT, (0x10308800 | _VS | _AV0S | _AC0 | _AC0_COPY); + dmm32 A1.w, 0x8b345e6e; + dmm32 A1.x, 0x00000000; + imm32 R3, 0xc40c1663; + imm32 R4, 0xd0347fff; + imm32 R7, 0x4249da20; + R3.H = (A1 += R4.L * R7.H) (M, T); + checkreg R3, 0x7fff1663; + checkreg A1.w, 0xac589c25; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x10308800 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x1c104880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AZ); + dmm32 A1.w, 0xa333ecbc; + dmm32 A1.x, 0xffffffea; + imm32 R2, 0x7fffffff; + imm32 R3, 0x72ea7fff; + imm32 R4, 0x07348ad1; + R4.H = (A1 += R2.L * R3.L) (M, T); + checkreg R4, 0x80008ad1; + checkreg A1.w, 0xa3336cbd; + checkreg A1.x, 0xffffffea; + checkreg ASTAT, (0x1c104880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AZ); + + dmm32 ASTAT, (0x44904e00 | _VS); + dmm32 A1.w, 0x90202372; + dmm32 A1.x, 0xffffffc4; + imm32 R2, 0x138ac9fc; + imm32 R3, 0x720a427f; + imm32 R4, 0x800000f5; + R3.H = (A1 += R4.L * R2.H) (M, T); + checkreg R3, 0x8000427f; + checkreg A1.w, 0x9032d684; + checkreg A1.x, 0xffffffc4; + checkreg ASTAT, (0x44904e00 | _VS | _V | _V_COPY); + + dmm32 ASTAT, (0x48f04c90 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN); + dmm32 A1.w, 0xe9c97364; + dmm32 A1.x, 0xffffffef; + imm32 R2, 0x001dffe9; + imm32 R3, 0x50f06d20; + imm32 R6, 0x6179b75b; + R6.H = (A1 -= R3.L * R2.L) (M, T); + checkreg R6, 0x8000b75b; + checkreg A1.w, 0x7cb34144; + checkreg A1.x, 0xffffffef; + checkreg ASTAT, (0x48f04c90 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x68d00e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + dmm32 A1.w, 0xf3d34812; + dmm32 A1.x, 0xffffff95; + imm32 R1, 0xf7419a18; + imm32 R6, 0x0fdf83b3; + imm32 R7, 0x0b831070; + R7.H = (A1 -= R6.L * R1.H) (M, T); + checkreg R7, 0x80001070; + checkreg A1.w, 0x6be1229f; + checkreg A1.x, 0xffffff96; + checkreg ASTAT, (0x68d00e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x3060ce80 | _VS | _AV1S | _AC1 | _CC | _AN); + dmm32 A1.w, 0xe0c1fc60; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x00e97fff; + imm32 R7, 0x3fff0001; + R1.H = (A1 += R1.L * R7.H) (M, T); + checkreg R1, 0x7fff7fff; + checkreg A1.w, 0x00c13c61; + checkreg A1.x, 0x00000001; + checkreg ASTAT, (0x3060ce80 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x3c80c000 | _VS | _AV0S | _AC0_COPY | _AN); + dmm32 A1.w, 0xb0e43973; + dmm32 A1.x, 0xffffffbc; + imm32 R0, 0x511a6fe3; + imm32 R1, 0x43fe2c80; + imm32 R2, 0x424b5c19; + R0.H = (A1 -= R2.L * R1.H) (M, T); + checkreg R0, 0x80006fe3; + checkreg A1.w, 0x986e4da5; + checkreg A1.x, 0xffffffbc; + checkreg ASTAT, (0x3c80c000 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0031.S b/sim/testsuite/bfin/random_0031.S new file mode 100644 index 0000000..4a849e1 --- /dev/null +++ b/sim/testsuite/bfin/random_0031.S @@ -0,0 +1,185 @@ +# Check that VS in ASTAT is set with add/sub insns (and not just V) +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x2810c010 | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + imm32 R0, 0x27f3a149; + imm32 R3, 0x3cae7c58; + imm32 R4, 0x33c97634; + R3.H = R0.L - R4.H (NS); + checkreg R3, 0x6d807c58; + checkreg ASTAT, (0x2810c010 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x64c00680 | _AQ | _AC0_COPY); + imm32 R1, 0x1b7b025c; + imm32 R5, 0x1ba46ce6; + R5.L = R5.L + R1.H (NS); + checkreg R5, 0x1ba48861; + checkreg ASTAT, (0x64c00680 | _VS | _V | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x68b04200 | _AV1S | _AV0 | _AC0 | _AQ | _AN); + imm32 R3, 0x4b91870f; + imm32 R6, 0x5972bae0; + imm32 R7, 0x31f7dfb7; + R7.H = R6.L + R3.L (S); + checkreg R7, 0x8000dfb7; + checkreg ASTAT, (0x68b04200 | _VS | _V | _AV1S | _AV0 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x78208e90 | _CC | _AN); + imm32 R3, 0x40b63bc7; + imm32 R5, 0x49c89df9; + R3.H = R5.L - R3.H (NS); + checkreg R3, 0x5d433bc7; + checkreg ASTAT, (0x78208e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x00904680 | _AV1S | _AV1 | _AV0 | _AC1 | _AQ | _AZ); + imm32 R2, 0x23a2c115; + imm32 R4, 0x6977581e; + imm32 R6, 0x41900942; + R4.L = R2.L - R6.H (NS); + checkreg R4, 0x69777f85; + checkreg ASTAT, (0x00904680 | _VS | _V | _AV1S | _AV1 | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x78d08210 | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ); + imm32 R0, 0x4317139e; + imm32 R1, 0x49ed40d6; + R0.L = R1.L + R0.H (NS); + checkreg R0, 0x431783ed; + checkreg ASTAT, (0x78d08210 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AN); + + dmm32 ASTAT, (0x58d00e10 | _AV1 | _AQ | _CC); + imm32 R0, 0x09ea77a2; + imm32 R1, 0x6ccd0b05; + imm32 R2, 0x761c63af; + R1.H = R0.L + R2.H (NS); + checkreg R1, 0xedbe0b05; + checkreg ASTAT, (0x58d00e10 | _VS | _V | _AV1 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x30c08000 | _AC0 | _AQ | _AC0_COPY); + imm32 R4, 0x36d243cb; + imm32 R5, 0xcd127add; + R4.H = R5.L + R4.L (NS); + checkreg R4, 0xbea843cb; + checkreg ASTAT, (0x30c08000 | _VS | _V | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x74108400 | _V | _AV1 | _AC1 | _AC0 | _AC0_COPY); + imm32 R0, 0x4e1893ea; + imm32 R1, 0x13cf5cc8; + imm32 R3, 0x7441949e; + R1.L = R0.L - R3.H (NS); + checkreg R1, 0x13cf1fa9; + checkreg ASTAT, (0x74108400 | _VS | _V | _AV1 | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x7420ce10 | _AV1S | _AV1 | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN | _AZ); + imm32 R4, 0x532c8fb1; + imm32 R6, 0x582420d2; + R6.H = R4.L - R4.H (NS); + checkreg R6, 0x3c8520d2; + checkreg ASTAT, (0x7420ce10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x74704010 | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY); + imm32 R3, 0x6f6a7429; + imm32 R5, 0x2ea5c47e; + R5.H = R5.L - R3.H (NS); + checkreg R5, 0x5514c47e; + checkreg ASTAT, (0x74704010 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x0ce08490 | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AZ); + imm32 R1, 0xfd18a0b0; + imm32 R4, 0x259e2151; + R4.L = R1.L - R4.H (NS); + checkreg R4, 0x259e7b12; + checkreg ASTAT, (0x0ce08490 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x54b08810 | _V | _AV1S | _AV0S | _AC0_COPY | _AN); + imm32 R3, 0x7a763675; + imm32 R6, 0x23c4a335; + R3.L = R6.L + R6.L (NS); + checkreg R3, 0x7a76466a; + checkreg ASTAT, (0x54b08810 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x70f0c080 | _AV1S | _AV0S | _AC0); + imm32 R4, 0x55fab7e4; + imm32 R5, 0x7dbd9b06; + R5.H = R5.L - R4.H (S); + checkreg R5, 0x80009b06; + checkreg ASTAT, (0x70f0c080 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x5ce04680 | _AV0 | _AC0 | _V_COPY | _AC0_COPY | _AN); + imm32 R0, 0x19cacbdb; + imm32 R2, 0x151cb293; + imm32 R4, 0x571c351a; + R0.H = R4.L - R2.L (S); + checkreg R0, 0x7fffcbdb; + checkreg ASTAT, (0x5ce04680 | _VS | _V | _AV0 | _V_COPY); + + dmm32 ASTAT, (0x0c604a00 | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AZ); + imm32 R3, 0x5432c45d; + imm32 R6, 0x62519952; + R3.L = R6.L + R6.L (S); + checkreg R3, 0x54328000; + checkreg ASTAT, (0x0c604a00 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x58708c90 | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN | _AZ); + imm32 R0, 0x1f3f3c0e; + imm32 R4, 0x5fae58d2; + R0.H = R0.L + R4.L (NS); + checkreg R0, 0x94e03c0e; + checkreg ASTAT, (0x58708c90 | _VS | _V | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x34b00a00 | _V | _AV1S | _AC1 | _CC | _V_COPY | _AZ); + imm32 R3, 0x6ea226dc; + imm32 R4, 0x045c6d64; + imm32 R7, 0x7e599a25; + R7.L = R3.L + R4.L (NS); + checkreg R7, 0x7e599440; + checkreg ASTAT, (0x34b00a00 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x40a0c010 | _AV1S | _AC0); + imm32 R2, 0x641501ef; + imm32 R7, 0x3acb49aa; + R2.H = R7.L + R7.H (NS); + checkreg R2, 0x847501ef; + checkreg ASTAT, (0x40a0c010 | _VS | _V | _AV1S | _V_COPY | _AN); + + dmm32 ASTAT, (0x78f04090 | _AV1S | _AC1 | _AQ | _CC | _AZ); + imm32 R2, 0x65681fdf; + imm32 R3, 0x5fffe0d3; + imm32 R5, 0x37df99cd; + R2.H = R5.L - R3.H (NS); + checkreg R2, 0x39ce1fdf; + checkreg ASTAT, (0x78f04090 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x0cc04e10 | _AV1S | _AQ | _CC); + imm32 R3, 0x571977df; + imm32 R4, 0x029671d0; + R3.L = R4.L + R3.H (NS); + checkreg R3, 0x5719c8e9; + checkreg ASTAT, (0x0cc04e10 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x00104880 | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + imm32 R0, 0x4c98aa07; + imm32 R4, 0x5e9da59f; + R4.H = R0.L + R0.L (S); + checkreg R4, 0x8000a59f; + checkreg ASTAT, (0x00104880 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x08008c00 | _AV1S | _AV0S | _AV0 | _CC | _AC0_COPY); + imm32 R4, 0x58ee2400; + imm32 R6, 0x2e97af3e; + R4.L = R6.L + R6.L (NS); + checkreg R4, 0x58ee5e7c; + checkreg ASTAT, (0x08008c00 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x2ce0c290 | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + imm32 R2, 0x2d467e64; + imm32 R6, 0x31aeb601; + imm32 R7, 0x1523a746; + R7.L = R2.L - R6.L (S); + checkreg R7, 0x15237fff; + checkreg ASTAT, (0x2ce0c290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); + + pass diff --git a/sim/testsuite/bfin/random_0032.S b/sim/testsuite/bfin/random_0032.S new file mode 100644 index 0000000..bfded41 --- /dev/null +++ b/sim/testsuite/bfin/random_0032.S @@ -0,0 +1,154 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x74308400 | _VS | _AV1S | _AV0S | _CC | _AN); + dmm32 A0.w, 0x5d4cf98c; + dmm32 A0.x, 0xffffffff; + imm32 R0, 0xba16ffff; + imm32 R4, 0x8000109d; + imm32 R6, 0x8000b212; + R6.L = (A0 -= R4.L * R0.L) (IH); + checkreg R6, 0x80008000; + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x74308400 | _VS | _V | _AV1S | _AV0S | _AV0 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x34e0ce80 | _VS | _V | _AV1S | _V_COPY | _AN); + dmm32 A0.w, 0x64bb88af; + dmm32 A0.x, 0xffffffff; + imm32 R5, 0x00008000; + imm32 R7, 0x0001ad69; + R5.L = (A0 += R7.H * R7.L) (IH); + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x34e0ce80 | _VS | _V | _AV1S | _AV0S | _AV0 | _V_COPY | _AN); + + dmm32 ASTAT, (0x4c204c10 | _VS | _V | _AV0S | _AQ | _V_COPY | _AN); + dmm32 A1.w, 0x75642aaf; + dmm32 A1.x, 0xffffffff; + imm32 R2, 0x133dffff; + imm32 R4, 0xc00006aa; + imm32 R7, 0x7fffffff; + R4.H = (A1 -= R2.L * R7.H) (IH); + checkreg R4, 0x800006aa; + checkreg A1.w, 0x80000000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x4c204c10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x48600400 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AN); + dmm32 A0.w, 0x534a596c; + dmm32 A0.x, 0xffffffff; + imm32 R1, 0x7fff86a7; + imm32 R5, 0x1163d244; + R1.L = (A0 -= R5.L * R1.L) (IH); + checkreg R1, 0x7fff8000; + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x48600400 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x38008c90 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); + dmm32 A1.w, 0x80000000; + dmm32 A1.x, 0xffffffff; + imm32 R0, 0x7fffffff; + imm32 R1, 0xdee9214c; + imm32 R4, 0x79f3c80a; + R1.H = (A1 += R0.L * R4.H) (M, IH); + checkreg R1, 0x8000214c; + checkreg ASTAT, (0x38008c90 | _VS | _AV1S | _AV1 | _AC1 | _CC | _AN); + + dmm32 ASTAT, (0x4cb00a00 | _VS | _AV1S | _AV0S | _AC1 | _AN); + dmm32 A0.w, 0x804e7e2f; + dmm32 A0.x, 0xffffffff; + imm32 R1, 0x3fccdf09; + imm32 R2, 0x09e71015; + imm32 R6, 0x761ac984; + R2.L = (A0 += R6.L * R1.H) (IH); + checkreg R2, 0x09e78000; + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x4cb00a00 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _V_COPY | _AN); + + dmm32 ASTAT, (0x08904c00 | _VS | _AV0S | _AQ | _AZ); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R1, 0x80000000; + imm32 R2, 0x0001de54; + imm32 R5, 0x80000000; + R1.L = (A0 -= R5.H * R2.H) (TFU); + checkreg ASTAT, (0x08904c00 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R1, 0x80000000; + checkreg R2, 0x0001de54; + checkreg R5, 0x80000000; + + dmm32 ASTAT, (0x00d04810 | _VS | _AV0S | _CC | _AC0_COPY | _AZ); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R4, 0x00020000; + imm32 R5, 0x35a26677; + R4.L = (A0 -= R5.H * R4.H) (TFU); + checkreg ASTAT, (0x00d04810 | _VS | _V | _AV0S | _AV0 | _CC | _V_COPY | _AC0_COPY | _AZ); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg R4, 0x00020000; + checkreg R5, 0x35a26677; + + dmm32 ASTAT, (0x08100a80 | _VS | _AV0S | _AQ | _CC); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x000300cc; + imm32 R4, 0x00029150; + imm32 R7, 0x00ff00ff; + R4.L = (A0 -= R0.L * R7.L) (IU); + checkreg R4, 0x00020000; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x08100a80 | _VS | _V | _AV0S | _AV0 | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x6c20c400 | _VS | _AV1S | _AV0S | _CC); + dmm32 A0.w, 0x860c9ac9; + dmm32 A0.x, 0xffffffff; + imm32 R2, 0x860c9a1b; + R2.L = (A0 -= R2.H * R2.L) (IH); + checkreg R2, 0x860c8000; + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x6c20c400 | _VS | _V | _AV1S | _AV0S | _AV0 | _CC | _V_COPY); + + dmm32 ASTAT, (0x20f00c10 | _VS | _AV0S | _AQ); + dmm32 A0.w, 0x0000de90; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x00000003; + imm32 R1, 0xfffd8000; + imm32 R5, 0x4a31921c; + R1.L = (A0 -= R5.L * R0.L) (FU); + checkreg R1, 0xfffd0000; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x20f00c10 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x38700690 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY); + dmm32 A1.w, 0x00000000; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x58863d39; + imm32 R1, 0x45377355; + imm32 R6, 0x00030000; + R1.H = (A1 -= R0.L * R6.H) (TFU); + checkreg R1, 0x00007355; + checkreg ASTAT, (0x38700690 | _VS | _V | _AV1S | _AV1 | _AC1 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x48704880 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); + dmm32 A0.w, 0x7fffd68a; + dmm32 A0.x, 0xffffffff; + imm32 R7, 0x06d88000; + R7.L = A0 (IH); + checkreg A0.w, 0x7fffd68a; + checkreg A0.x, 0xffffffff; + checkreg R7, 0x06d88000; + checkreg ASTAT, (0x48704880 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0033.S b/sim/testsuite/bfin/random_0033.S new file mode 100644 index 0000000..4835396 --- /dev/null +++ b/sim/testsuite/bfin/random_0033.S @@ -0,0 +1,64 @@ +# Verify registers saturate and ASTAT bits are updated correctly +# with the RND12 subtract insn +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x24a00410 | _VS | _AV1S | _AV0 | _AC0 | _AC0_COPY | _AN); + imm32 R5, 0x0fb35119; + imm32 R6, 0xffffffff; + imm32 R7, 0x80000000; + R6.H = R5 - R7 (RND12); + checkreg R6, 0x7fffffff; + checkreg ASTAT, (0x24a00410 | _VS | _V | _AV1S | _AV0 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x08c08000 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + imm32 R3, 0x80003f8f; + imm32 R5, 0x6267c92c; + imm32 R6, 0x80000000; + R5.L = R3 - R6 (RND12); + checkreg R5, 0x62670004; + checkreg ASTAT, (0x08c08000 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x04200c10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY); + imm32 R1, 0x7fff0000; + imm32 R5, 0x80000000; + R1.L = R5 - R5 (RND12); + checkreg ASTAT, (0x04200c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AZ); + checkreg R1, 0x7fff0000; + checkreg R5, 0x80000000; + + dmm32 ASTAT, (0x40600e90 | _VS | _AV1S | _AV0S | _AQ | _CC); + imm32 R1, 0x80000000; + imm32 R5, 0x00008000; + imm32 R6, 0x00000000; + R5.L = R6 - R1 (RND12); + checkreg R5, 0x00007fff; + checkreg ASTAT, (0x40600e90 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x68300880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ); + imm32 R1, 0xf8ed0000; + imm32 R6, 0x80000000; + R1.H = R1 - R6 (RND12); + checkreg R1, 0x7fff0000; + checkreg ASTAT, (0x68300880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x70d0c410 | _VS | _AV0S | _AQ); + imm32 R0, 0x80000000; + imm32 R1, 0x71455f95; + imm32 R4, 0xd4871012; + R4.H = R1 - R0 (RND12); + checkreg R4, 0x7fff1012; + checkreg ASTAT, (0x70d0c410 | _VS | _V | _AV0S | _AQ | _V_COPY); + + dmm32 ASTAT, (0x34500e00 | _VS | _AV0S | _AC1 | _CC | _AZ); + imm32 R2, 0x00000000; + imm32 R5, 0x00000000; + imm32 R6, 0x80000000; + R2.L = R5 - R6 (RND12); + checkreg R2, 0x00007fff; + checkreg ASTAT, (0x34500e00 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY); + + pass diff --git a/sim/testsuite/bfin/random_0034.S b/sim/testsuite/bfin/random_0034.S new file mode 100644 index 0000000..7aeaadb --- /dev/null +++ b/sim/testsuite/bfin/random_0034.S @@ -0,0 +1,129 @@ +# Verify sign extension behavior with simultaneous acc additions, and +# verify that no ASTAT bits get changed as a result +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ); + dmm32 A0.w, 0x589145b7; + dmm32 A0.x, 0xffffffee; + dmm32 A1.w, 0x0b247b05; + dmm32 A1.x, 0x0000005a; + imm32 R3, 0x1e414332; + imm32 R4, 0x351715b7; + R3 = A1.L + A1.H, R4 = A0.L + A0.H; + checkreg R3, 0x00008629; + checkreg R4, 0x00009e48; + checkreg ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ); + + dmm32 ASTAT, (0x40e0cc00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0xb2c58001; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xe999dc28; + dmm32 A1.x, 0xffffffff; + imm32 R0, 0xe58d5ffa; + imm32 R4, 0x7fff7fff; + R0 = A1.L + A1.H, R4 = A0.L + A0.H; + checkreg R0, 0xffffc5c1; + checkreg R4, 0xffff32c6; + checkreg ASTAT, (0x40e0cc00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x3420ca80 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC); + dmm32 A0.w, 0xeff48350; + dmm32 A0.x, 0xffffffff; + dmm32 A1.w, 0x5a3f623a; + dmm32 A1.x, 0xffffffff; + imm32 R4, 0xffff152f; + imm32 R6, 0xdd13218a; + R4 = A1.L + A1.H, R6 = A0.L + A0.H; + checkreg R4, 0x0000bc79; + checkreg R6, 0xffff7344; + checkreg ASTAT, (0x3420ca80 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC); + + dmm32 ASTAT, (0x10204880 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AN); + dmm32 A0.w, 0x6da679bb; + dmm32 A0.x, 0xffffff96; + dmm32 A1.w, 0x1f5fb024; + dmm32 A1.x, 0x00000000; + imm32 R3, 0x3ebf8000; + imm32 R6, 0x025f2e8c; + R6 = A1.L + A1.H, R3 = A0.L + A0.H; + checkreg R3, 0x0000e761; + checkreg R6, 0xffffcf83; + checkreg ASTAT, (0x10204880 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x6ca00c90 | _V | _AV1S | _AV1 | _AC0_COPY | _AN | _AZ); + dmm32 A0.w, 0x59abaa84; + dmm32 A0.x, 0xffffffe1; + dmm32 A1.w, 0x71541efe; + dmm32 A1.x, 0x00000009; + imm32 R0, 0x2c41e797; + imm32 R5, 0x7bfa5e8a; + R0 = A1.L + A1.H, R5 = A0.L + A0.H; + checkreg R0, 0x00009052; + checkreg R5, 0x0000042f; + checkreg ASTAT, (0x6ca00c90 | _V | _AV1S | _AV1 | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x1c50c290 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AN); + dmm32 A0.w, 0xffffffff; + dmm32 A0.x, 0xffffffff; + dmm32 A1.w, 0xc49ca8db; + dmm32 A1.x, 0xffffffff; + imm32 R3, 0x0f62ffff; + imm32 R4, 0x09505188; + R4 = A1.L + A1.H, R3 = A0.L + A0.H; + checkreg R3, 0xfffffffe; + checkreg R4, 0xffff6d77; + checkreg ASTAT, (0x1c50c290 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AN); + + dmm32 ASTAT, (0x70e04a90 | _VS | _AV0S | _AQ); + dmm32 A0.w, 0xd827823e; + dmm32 A0.x, 0xffffffff; + dmm32 A1.w, 0x303d11ba; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x80007fff; + imm32 R6, 0xffc4feb3; + R6 = A1.L + A1.H, R1 = A0.L + A0.H; + checkreg R1, 0xffff5a65; + checkreg R6, 0x000041f7; + checkreg ASTAT, (0x70e04a90 | _VS | _AV0S | _AQ); + + dmm32 ASTAT, (0x5c80c200 | _VS | _AV0S | _AQ | _AC0_COPY | _AN); + dmm32 A0.w, 0x97049850; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xffffa014; + dmm32 A1.x, 0xffffffff; + imm32 R0, 0x04828378; + imm32 R5, 0x3d9effff; + R0 = A1.L + A1.H, R5 = A0.L + A0.H; + checkreg R0, 0xffffa013; + checkreg R5, 0xffff2f54; + checkreg ASTAT, (0x5c80c200 | _VS | _AV0S | _AQ | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x6c604600 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AZ); + dmm32 A0.w, 0xac43c455; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0x03de6f39; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x5bbfd2d1; + imm32 R3, 0x22425ebc; + R3 = A1.L + A1.H, R0 = A0.L + A0.H; + checkreg R0, 0xffff7098; + checkreg R3, 0x00007317; + checkreg ASTAT, (0x6c604600 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AZ); + + dmm32 ASTAT, (0x7cd04280 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0xb63ac8f5; + dmm32 A0.x, 0xffffffe0; + dmm32 A1.w, 0x358b94e8; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x80007fff; + imm32 R6, 0x4f4a8883; + R6 = A1.L + A1.H, R1 = A0.L + A0.H; + checkreg R1, 0xffff7f2f; + checkreg R6, 0xffffca73; + checkreg ASTAT, (0x7cd04280 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + pass diff --git a/sim/testsuite/bfin/random_0035.S b/sim/testsuite/bfin/random_0035.S new file mode 100644 index 0000000..7c10517 --- /dev/null +++ b/sim/testsuite/bfin/random_0035.S @@ -0,0 +1,31 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x3080ca10 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY); + dmm32 A0.w, 0xee917987; + dmm32 A0.x, 0x0000007f; + dmm32 A1.w, 0x116e8678; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x4d56fd82; + R1.L = (A0 += A1); + checkreg R1, 0x4d567fff; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0x0000007f; + checkreg ASTAT, (0x3080ca10 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY); + + dmm32 ASTAT, (0x00c04290 | _VS | _V | _AV0S | _V_COPY); + dmm32 A0.w, 0xe4f8e4c1; + dmm32 A0.x, 0x0000007f; + dmm32 A1.w, 0x1b071b3e; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x4b5126c6; + R1.L = (A0 += A1); + checkreg R1, 0x4b517fff; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0x0000007f; + checkreg ASTAT, (0x00c04290 | _VS | _V | _AV0S | _V_COPY); + + pass diff --git a/sim/testsuite/bfin/random_0036.S b/sim/testsuite/bfin/random_0036.S new file mode 100644 index 0000000..7e75da9 --- /dev/null +++ b/sim/testsuite/bfin/random_0036.S @@ -0,0 +1,309 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x3ce04490 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY); + dmm32 A0.w, 0x7d8d8272; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xe0004138; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0x7d8e7fff; + imm32 R2, 0xffff8001; + A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); + checkreg A0.w, 0xfd8c0273; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x3ce04490 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY); + + dmm32 ASTAT, (0x70b0c800 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x53931540; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xf07795da; + dmm32 A1.x, 0x0000007f; + imm32 R2, 0x8931da0a; + imm32 R4, 0xffff41eb; + imm32 R5, 0x7fff41eb; + A1 += R5.L * R4.H (M), R2 = (A0 -= R5.L * R4.H) (FU); + checkreg R2, 0x11a8572b; + checkreg A0.w, 0x11a8572b; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x70b0c800 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AC0_COPY); + + dmm32 ASTAT, (0x58100410 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0xaeba0d61; + dmm32 A0.x, 0x00000041; + dmm32 A1.w, 0xbb313d2f; + dmm32 A1.x, 0x0000007f; + imm32 R4, 0x1ea2588d; + imm32 R7, 0xffffffff; + A1 += R4.L * R7.H (M), A0 += R4.L * R7.L (FU); + checkreg A0.w, 0x0746b4d4; + checkreg A0.x, 0x00000042; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x58100410 | _VS | _V | _AV1S | _AV1 | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x58704200 | _VS | _AV1S | _AV0S); + dmm32 A0.w, 0xb7ab4854; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xe0002429; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0xb7ac8000; + imm32 R2, 0x80008001; + A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); + checkreg A0.w, 0xf7ab4854; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x58704200 | _VS | _AV1S | _AV1 | _AV0S); + + dmm32 ASTAT, (0x38d0c800 | _VS | _AV1S | _AV0S); + dmm32 A0.w, 0xfffe0001; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xffff4001; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0xffffffff; + imm32 R2, 0xffffffff; + A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); + checkreg A0.w, 0xfffc0002; + checkreg A0.x, 0x00000001; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x38d0c800 | _VS | _AV1S | _AV1 | _AV0S); + + dmm32 ASTAT, (0x24e0ca80 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY); + dmm32 A0.w, 0x0000000a; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xff5439dc; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0x3ea961c5; + imm32 R6, 0xffff0510; + A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x24e0ca80 | _VS | _V | _AV1S | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x7800cc80 | _VS | _AC1 | _AC0 | _CC | _AC0_COPY); + dmm32 A0.w, 0xfffe0001; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xffff4001; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0xffffffff; + imm32 R2, 0x0000ffff; + A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x7800cc80 | _VS | _AV1S | _AV1 | _AC1 | _AC0 | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x50200800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY); + dmm32 A0.w, 0x6970968f; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xe0004b47; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0x69717fff; + imm32 R2, 0xffff8001; + A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); + checkreg A0.w, 0xe96f1690; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x50200800 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AC0_COPY); + + dmm32 ASTAT, (0x34704080 | _VS | _AV1S | _AV1 | _AV0S | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0x0839a708; + dmm32 A0.x, 0xffffff80; + dmm32 A1.w, 0xffffffff; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0x0c8c109a; + imm32 R2, 0x109a0c8c; + imm32 R5, 0x006dd6ac; + A1 -= R5.L * R0.L (M), R2.L = (A0 += R5.H * R0.L) (FU); + checkreg R2, 0x109affff; + checkreg A0.w, 0x0840b89a; + checkreg A0.x, 0xffffff80; + checkreg ASTAT, (0x34704080 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x78108090 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY); + dmm32 A0.w, 0x21edde12; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xe0006f08; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0x21ee7fff; + imm32 R2, 0xffff8001; + A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); + checkreg A0.w, 0xa1ec5e13; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x78108090 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY); + + dmm32 ASTAT, (0x50b08a10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x00000007; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xf8b109fc; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0x27827703; + imm32 R6, 0xffff03ca; + A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x50b08a10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x34e0c800 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY); + dmm32 A0.w, 0xffffffff; + dmm32 A0.x, 0xffffffff; + dmm32 A1.w, 0xefc2be42; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0x53574850; + imm32 R6, 0xffff1400; + A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU); + checkreg A0.w, 0xaca95356; + checkreg A0.x, 0xffffffff; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x34e0c800 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY); + + dmm32 ASTAT, (0x24608c80 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY); + dmm32 A0.w, 0x0f03f0fc; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xe000787d; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0x0f04ffff; + imm32 R2, 0xffff8001; + A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); + checkreg A0.w, 0x0f01f0fd; + checkreg A0.x, 0x00000001; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x24608c80 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY); + + dmm32 ASTAT, (0x58404690 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0x1e65e19a; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xe00070cc; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0x1e66ffff; + imm32 R2, 0xffff8001; + A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); + checkreg A0.w, 0x1e63e19b; + checkreg A0.x, 0x00000001; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x58404690 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x08004a10 | _VS | _AV1S | _AV1 | _AC0 | _CC | _AC0_COPY); + dmm32 A1.w, 0xffffffff; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0x293a8000; + imm32 R3, 0xd0e6382b; + A1 += R3.L * R0.H (M, FU); + checkreg ASTAT, (0x08004a10 | _VS | _AV1S | _AV1 | _AC0 | _CC | _AC0_COPY); + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg R0, 0x293a8000; + checkreg R3, 0xd0e6382b; + + dmm32 ASTAT, (0x28e00e00 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY); + dmm32 A0.w, 0xfffe0001; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xffff4001; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0xffffffff; + imm32 R2, 0x0000ffff; + A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x28e00e00 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY); + + dmm32 ASTAT, (0x14004690 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); + dmm32 A1.w, 0xffffffff; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0x369a8000; + imm32 R3, 0xf023457e; + A1 += R3.L * R0.H (M, FU); + checkreg ASTAT, (0x14004690 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg R0, 0x369a8000; + checkreg R3, 0xf023457e; + + dmm32 ASTAT, (0x5c600680 | _VS | _AV1S | _AQ | _CC); + dmm32 A0.w, 0xfffe0001; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xffff4001; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0xffffffff; + imm32 R2, 0xffffffff; + A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); + checkreg A0.w, 0xfffc0002; + checkreg A0.x, 0x00000001; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x5c600680 | _VS | _AV1S | _AV1 | _AQ | _CC); + + dmm32 ASTAT, (0x7cd00800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY); + dmm32 A0.w, 0xfffe0001; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xffff4001; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0xffffffff; + imm32 R2, 0x0000ffff; + A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x7cd00800 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AC0_COPY); + + dmm32 ASTAT, (0x78e0cc10 | _VS | _AV1S | _AV0S | _AC1); + dmm32 A0.w, 0xfffe0001; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xffff4001; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0xffffffff; + imm32 R2, 0xffffffff; + A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); + checkreg A0.w, 0xfffc0002; + checkreg A0.x, 0x00000001; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x78e0cc10 | _VS | _AV1S | _AV1 | _AV0S | _AC1); + + dmm32 ASTAT, (0x1cd04c80 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x00000015; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xfeeaa91d; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0x50246875; + imm32 R6, 0xffff0aab; + A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU); + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x1cd04c80 | _VS | _V | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x18304890 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0xfffffffe; + dmm32 A0.x, 0xffffffff; + dmm32 A1.w, 0xffffca85; + dmm32 A1.x, 0x0000007f; + imm32 R0, 0xffffffff; + imm32 R3, 0xffffdc58; + imm32 R7, 0xffff950a; + A1 -= R7.L * R0.H (M), R3.L = (A0 -= R7.L * R0.H) (FU); + checkreg R3, 0xffffffff; + checkreg A0.w, 0x6af69508; + checkreg A0.x, 0xffffffff; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x18304890 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + pass diff --git a/sim/testsuite/bfin/random_0037.S b/sim/testsuite/bfin/random_0037.S new file mode 100644 index 0000000..05eae8a --- /dev/null +++ b/sim/testsuite/bfin/random_0037.S @@ -0,0 +1,84 @@ +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x1880c200 | _VS | _AV1S | _AV0S | _AC1); + dmm32 A0.w, 0x2b9a5661; + dmm32 A0.x, 0x00000032; + dmm32 A1.w, 0x1a0c4c8c; + dmm32 A1.x, 0xffffff80; + imm32 R0, 0x694a9cb0; + imm32 R6, 0x651cc0dd; + A1 += R0.L * R0.H (M), R6.L = (A0 += R0.L * R0.H) (TFU); + checkreg R6, 0x651cffff; + checkreg A0.w, 0x6c0bd141; + checkreg A0.x, 0x00000032; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0xffffff80; + checkreg ASTAT, (0x1880c200 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _V_COPY); + + dmm32 ASTAT, (0x14104490 | _VS | _AV1S | _AZ); + dmm32 A0.w, 0x6ec017a0; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xff6f5846; + dmm32 A1.x, 0x0000007f; + imm32 R3, 0x256a8306; + imm32 R6, 0x6a8ca1e4; + imm32 R7, 0x2e579ce0; + R6.H = (A1 -= R3.L * R7.L) (M), A0 = R3.L * R7.L (TFU); + checkreg R6, 0x7fffa1e4; + checkreg A0.w, 0x504a4d40; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x14104490 | _VS | _V | _AV1S | _AV1 | _V_COPY | _AZ); + + dmm32 ASTAT, (0x20008080 | _VS | _V | _AV1S | _AV0 | _AC1 | _AC0 | _AQ); + dmm32 A0.w, 0x58b9bdf1; + dmm32 A0.x, 0xffffffe2; + dmm32 A1.w, 0x42c9fae8; + dmm32 A1.x, 0xffffff80; + imm32 R1, 0x68df1898; + imm32 R2, 0x3ae1b1f0; + imm32 R5, 0x61c3f5ef; + A1 += R2.L * R5.L (M), R1.L = (A0 -= R2.L * R5.L) (TFU); + checkreg R1, 0x68dfffff; + checkreg A0.w, 0xadc8eee1; + checkreg A0.x, 0xffffffe1; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0xffffff80; + checkreg ASTAT, (0x20008080 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x1c70ca90 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x082c2157; + dmm32 A0.x, 0xffffff9f; + dmm32 A1.w, 0x275e1474; + dmm32 A1.x, 0xffffff80; + imm32 R1, 0x7d3179fd; + imm32 R2, 0x5b41566f; + R2.H = (A1 -= R1.L * R1.H) (M), R2.L = (A0 = R1.L * R1.L) (TFU); + checkreg R2, 0x80003a21; + checkreg A0.w, 0x3a212409; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0xffffff80; + checkreg ASTAT, (0x1c70ca90 | _VS | _V | _AV1S | _AV1 | _AV0S | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x7460cc10 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY); + dmm32 A0.w, 0x7fffffff; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xf20b4000; + dmm32 A1.x, 0x0000007f; + imm32 R1, 0x2ca2d045; + imm32 R6, 0x6e516a3c; + R1.H = (A1 -= R1.L * R6.H) (M), A0 = R1.L * R6.H (TFU); + checkreg R1, 0x7fffd045; + checkreg A0.w, 0x59bf8bd5; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0x0000007f; + checkreg ASTAT, (0x7460cc10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _CC | _V_COPY); + + pass diff --git a/sim/testsuite/bfin/run-tests.sh b/sim/testsuite/bfin/run-tests.sh new file mode 100755 index 0000000..c5ee777 --- /dev/null +++ b/sim/testsuite/bfin/run-tests.sh @@ -0,0 +1,249 @@ +#!/bin/sh + +usage() { + cat <<-EOF + Usage: $0 [-rs] [-rj ] [-rh ] [tests] + + If no tests are specified, all tests are processed. + + Options: + -rs Run on simulator + -rj Run on board via JTAG + -rh Run on board ip + -j Num jobs to run + EOF + exit ${1:-1} +} + +: ${MAKE:=make} +boardip= +boardjtag= +run_sim=false +run_jtag=false +run_host=false +jobs=`getconf _NPROCESSORS_ONLN 2>/dev/null || echo 1` +: $(( jobs += 1 )) +while [ -n "$1" ] ; do + case $1 in + -rs) run_sim=true;; + -rj) boardjtag=$2; shift; run_jtag=true;; + -rh) boardip=$2; shift; run_host=true;; + -j) jobs=$2; shift;; + -*) usage;; + *) break;; + esac + shift +done +${run_jtag} || ${run_host} || ${run_sim} || run_sim=true + +if ${run_host} && [ -z "${boardip}" ] ; then + usage +fi + +cd "${0%/*}" || exit 1 + +dorsh() { + # rsh sucks and does not pass up its exit status, so we have to: + # on board: + # - send all output to stdout + # - send exit status to stderr + # on host: + # - swap stdout and stderr + # - pass exit status to `exit` + # - send stderr back to stdout and up + (exit \ + $(rsh -l root $boardip \ + '(/tmp/'$1') 2>&1; ret=$?; echo $ret 1>&2; [ $ret -eq 0 ] && rm -f /tmp/'$1 \ + 3>&1 1>&2 2>&3) \ + 2>&1) 2>&1 +} + +dojtag() { + if grep -q CHECKREG ${1%.x} ; then + echo "DBGA does not work via JTAG" + exit 77 + fi + + cat <<-EOF > commands + target remote localhost:2000 + load + + b *_pass + commands + exit 0 + end + + b *_fail + commands + exit 1 + end + + # we're executing at EVT1, so this doesn't really help ... + set ((long *)0xFFE02000)[3] = _fail + set ((long *)0xFFE02000)[5] = _fail + + c + EOF + bfin-elf-gdb -x commands "$1" + ret=$? + rm -f commands + exit ${ret} +} + +testit() { + local name=$1 x=$2 y=`echo $2 | sed 's:\.[xX]$::'` out rsh_out addr + shift; shift + local fail=`grep xfail ${y}` + if [ "${name}" = "HOST" -a ! -f $x ] ; then + return + fi + printf '%-5s %-40s' ${name} ${x} + out=`"$@" ${x} 2>&1` + (pf "${out}") + if [ $? -ne 0 ] ; then + if [ "${name}" = "SIM" ] ; then + tmp=`echo ${out} | awk '{print $3}' | sed 's/://'` + tmp1=`expr index "${out}" "program stopped with signal 4"` + if [ ${tmp1} -eq 1 ] ; then + printf 'illegal instruction\n' + elif [ -n "${tmp}" ] ; then + printf 'FAIL at line ' + addr=`echo $out | sed 's:^[A-Za-z ]*::' | sed 's:^0x[0-9][0-9] ::' | sed 's:^[A-Za-z ]*::' | awk '{print $1}'` + bfin-elf-addr2line -e ${x} ${addr} | awk -F "/" '{print $NF}' + fi + elif [ "${name}" = "HOST" ] ; then + rsh_out=`rsh -l root $boardip '/bin/dmesg -c | /bin/grep -e DBGA -e "FAULT "'` + tmp=`echo ${rsh_out} | sed 's:\].*$::' | awk '{print $NF}' | awk -F ":" '{print $NF}'` + if [ -n "${tmp}" ] ; then + echo "${rsh_out}" + printf 'FAIL at line ' + bfin-elf-addr2line -e ${x} $(echo ${rsh_out} | sed 's:\].*$::' | awk '{print $NF}') | awk -F "/" '{print $NF}' + fi + fi + ret=$(( ret + 1 )) + if [ -z "${fail}" ] ; then + unexpected_fail=$(( unexpected_fail + 1 )) + echo "!!!Expected Pass, but fail" + fi + else + if [ ! -z "${fail}" ] ; then + unexpected_pass=$(( unexpected_pass + 1 )) + echo "!!!Expected fail, but pass" + else + expected_pass=$(( expected_pass + 1 )) + fi + fi +} + +pf() { + local ret=$? + if [ ${ret} -eq 0 ] ; then + echo "PASS" + elif [ ${ret} -eq 77 ] ; then + echo "SKIP $*" + else + echo "FAIL! $*" + exit 1 + fi +} + +[ $# -eq 0 ] && set -- *.[Ss] +bins_hw=$( (${run_sim} || ${run_jtag}) && printf '%s.x ' "$@") +if ${run_host} ; then + for files in "$@" ; do + tmp=`grep -e CYCLES -e TESTSET -e CLI -e STI -e RTX -e RTI -e SEQSTAT $files -l` + if [ -z "${tmp}" ] ; then + bins_host=`echo "${bins_host} ${files}.X"` + else + echo "skipping ${files}, since it isn't userspace friendly" + fi + done +fi +if [ -n "${bins_hw}" ] ; then + bins_all="${bins_hw}" +fi + +if [ -n "${bins_host}" ] ; then + bins_all="${bins_all} ${bins_host}" +fi + +if [ -z "${bins_all}" ] ; then + exit +fi + +printf 'Compiling tests: ' +${MAKE} -s -j ${bins_all} +pf + +if ${run_jtag} ; then + printf 'Setting up gdbproxy (see gdbproxy.log): ' + killall -q bfin-gdbproxy + bfin-gdbproxy -q bfin --reset --board=${boardjtag} --init-sdram >gdbproxy.log 2>&1 & + t=0 + while [ ${t} -lt 5 ] ; do + if netstat -nap 2>&1 | grep -q ^tcp.*:2000.*gdbproxy ; then + break + else + : $(( t += 1 )) + sleep 1 + fi + done + pf +fi + +if ${run_host} ; then + printf 'Uploading tests to board "%s": ' "${boardip}" + rcp ${bins_host} root@${boardip}:/tmp/ + pf + rsh -l root $boardip '/bin/dmesg -c' > /dev/null +fi + +SIM="../../../bfin/run" +if [ ! -x ${SIM} ] ; then + SIM="bfin-elf-run" +fi +echo "Using sim: ${SIM}" + +ret=0 +unexpected_fail=0 +unexpected_pass=0 +expected_pass=0 +pids=() +for s in "$@" ; do + ( + out=$( + ${run_sim} && testit SIM ${s}.x ${SIM} `sed -n '/^# sim:/s|^[^:]*:||p' ${s}` + ${run_jtag} && testit JTAG ${s}.x dojtag + ${run_host} && testit HOST ${s}.X dorsh + ) + case $out in + *PASS*) ;; + *) echo "$out" ;; + esac + ) & + pids+=( $! ) + if [[ ${#pids[@]} -gt ${jobs} ]] ; then + wait ${pids[0]} + pids=( ${pids[@]:1} ) + fi +done +wait + +killall -q bfin-gdbproxy +if [ ${ret} -eq 0 ] ; then + rm -f gdbproxy.log +# ${MAKE} -s clean & + exit 0 +else + echo number of failures ${ret} + if [ ${unexpected_pass} -gt 0 ] ; then + echo "Unexpected passes: ${unexpected_pass}" + fi + if [ ${unexpected_fail} -gt 0 ] ; then + echo "Unexpected fails: ${unexpected_fail}" + fi + if [ ${expected_pass} -gt 0 ] ; then + echo "passes : ${expected_pass}" + fi + exit 1 +fi diff --git a/sim/testsuite/bfin/s0.s b/sim/testsuite/bfin/s0.s new file mode 100644 index 0000000..8fa53f2 --- /dev/null +++ b/sim/testsuite/bfin/s0.s @@ -0,0 +1,12 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 10; + P0 = R0; + LSETUP ( ls0 , ls0 ) LC0 = P0; +ls0: + R0 += -1; + DBGA ( R0.L , 0 ); + pass diff --git a/sim/testsuite/bfin/s1.s b/sim/testsuite/bfin/s1.s new file mode 100644 index 0000000..262dc06 --- /dev/null +++ b/sim/testsuite/bfin/s1.s @@ -0,0 +1,25 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 1; + R1 = 2; + R2 = 3; + R4 = 4; + P1 = R1; + LSETUP ( ls0 , ls0 ) LC0 = P1; + R5 = 5; + R6 = 6; + R7 = 7; + +ls0: R1 += 1; + + DBGA ( R1.L , 4 ); + P1 = R1; + LSETUP ( ls1 , ls1 ) LC1 = P1; +ls1: R1 += 1; + + DBGA ( R1.L , 8 ); + + pass diff --git a/sim/testsuite/bfin/s10.s b/sim/testsuite/bfin/s10.s new file mode 100644 index 0000000..503cabf --- /dev/null +++ b/sim/testsuite/bfin/s10.s @@ -0,0 +1,77 @@ +// Shifter test program. +// Test instructions +// RL0 = SIGNBITS R1; +// RL0 = SIGNBITS RL1; +// RL0 = SIGNBITS RH1; + +# mach: bfin + +.include "testutils.inc" + start + + +// on 32-b word + + R1.L = 0xffff; + R1.H = 0x7fff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0000 ); + + R1.L = 0xffff; + R1.H = 0x30ff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0001 ); + + R1.L = 0xff0f; + R1.H = 0x10ff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0002 ); + + R1.L = 0xff0f; + R1.H = 0xe0ff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0002 ); + + R1.L = 0x0001; + R1.H = 0x0000; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0001e ); + + R1.L = 0xfffe; + R1.H = 0xffff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0001e ); + + R1.L = 0xffff; // return largest norm for -1 + R1.H = 0xffff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0001f ); + + R1.L = 0; // return largest norm for zero + R1.H = 0; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x001f ); + +// on 16-b word + + R1.L = 0x7fff; + R1.H = 0xffff; + R0.L = SIGNBITS R1.L; + DBGA ( R0.L , 0x0000 ); + + R1.L = 0x0fff; + R1.H = 0x0001; + R0.L = SIGNBITS R1.H; + DBGA ( R0.L , 0x000e ); + + R1.L = 0x0fff; + R1.H = 0xffff; + R0.L = SIGNBITS R1.H; + DBGA ( R0.L , 0x000f ); + + R1.L = 0x0fff; + R1.H = 0xfffe; + R0.L = SIGNBITS R1.H; + DBGA ( R0.L , 0x000e ); + + pass diff --git a/sim/testsuite/bfin/s11.s b/sim/testsuite/bfin/s11.s new file mode 100644 index 0000000..16a57eb --- /dev/null +++ b/sim/testsuite/bfin/s11.s @@ -0,0 +1,177 @@ +# mach: bfin + +// Shift test program. +// Test instructions +// RL0 = CC = BXOR (A0 AND R1) << 1; +// RL0 = CC = BXOR A0 AND R1; +// A0 <<=1 (BXOR A0 AND A1 CC); +// RL3 = CC = BXOR A0 AND A1 CC; + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + +// RL0 = CC = BXOR (A0 AND R1) << 1; + R0.L = 0x1000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + R1.L = 0xffff; + R1.H = 0xffff; + R2.L = CC = BXORSHIFT( A0 , R1 ); + R0 = A0.w; + DBGA ( R0.L , 0x2000 ); + DBGA ( R0.H , 0x0000 ); + R0.L = A0.x; + DBGA ( R0.L , 0x0000 ); + R0 = CC; + DBGA ( R0.L , 0x0001 ); + DBGA ( R0.H , 0x0000 ); + DBGA ( R2.L , 0x0001 ); + + R0.L = 0x1000; + R0.H = 0x0001; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + R1.L = 0xffff; + R1.H = 0xffff; + R2.L = CC = BXORSHIFT( A0 , R1 ); + R0 = A0.w; + DBGA ( R0.L , 0x2000 ); + DBGA ( R0.H , 0x0002 ); + R0.L = A0.x; + DBGA ( R0.L , 0x0000 ); + R0 = CC; + DBGA ( R0.L , 0x0000 ); + DBGA ( R0.H , 0x0000 ); + DBGA ( R2.L , 0x0000 ); + + R0.L = 0xffff; + R0.H = 0xffff; + A0.w = R0; + R0.L = 0x00ff; + A0.x = R0.L; + R1.L = 0xffff; + R1.H = 0xffff; + R2.L = CC = BXORSHIFT( A0 , R1 ); + R0 = A0.w; + DBGA ( R0.L , 0xfffe ); + DBGA ( R0.H , 0xffff ); + R0.L = A0.x; + DBGA ( R0.L , 0xffff ); + R0 = CC; + DBGA ( R0.L , 0x0001 ); + DBGA ( R0.H , 0x0000 ); + DBGA ( R2.L , 0x0001 ); + +// no + R0.L = 0xffff; + R0.H = 0xffff; + A0.w = R0; + R0.L = 0x00ff; + A0.x = R0.L; + R1.L = 0xffff; + R1.H = 0xffff; + R2.L = CC = BXOR( A0 , R1 ); + R0 = A0.w; + DBGA ( R0.L , 0xffff ); + DBGA ( R0.H , 0xffff ); + R0.L = A0.x; + DBGA ( R0.L , 0xffff ); + R0 = CC; + DBGA ( R0.L , 0x0000 ); + DBGA ( R0.H , 0x0000 ); + DBGA ( R2.H , 0x0000 ); + +// A0 <<=1 (BXOR A0 AND A1 CC); + + R0.L = 0x1000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + R0.L = 0xffff; + R0.H = 0xffff; + A1.w = R0; + R0.L = 0x00ff; + A1.x = R0.L; + R0.L = 0x0000; + R0.H = 0x0000; + CC = R0; + A0 = BXORSHIFT( A0 , A1, CC ); + R0 = A0.w; + DBGA ( R0.L , 0x2001 ); + DBGA ( R0.H , 0x0000 ); + R0.L = A0.x; + DBGA ( R0.L , 0x0000 ); + + R0.L = 0x1000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + R0.L = 0x0fff; + R0.H = 0xffff; + A1.w = R0; + R0.L = 0x00ff; + A1.x = R0.L; + R0.L = 0x0000; + R0.H = 0x0000; + CC = R0; + A0 = BXORSHIFT( A0 , A1, CC ); + R0 = A0.w; + DBGA ( R0.L , 0x2000 ); + DBGA ( R0.H , 0x0000 ); + R0.L = A0.x; + DBGA ( R0.L , 0x0000 ); + + R0.L = 0x1000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + R0.L = 0xffff; + R0.H = 0xffff; + A1.w = R0; + R0.L = 0x00ff; + A1.x = R0.L; + R0.L = 0x0001; + R0.H = 0x0000; + CC = R0; + A0 = BXORSHIFT( A0 , A1, CC ); + R0 = A0.w; + DBGA ( R0.L , 0x2000 ); + DBGA ( R0.H , 0x0000 ); + R0.L = A0.x; + DBGA ( R0.L , 0x0000 ); + +// no + + R0.L = 0x1000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + R0.L = 0xffff; + R0.H = 0xffff; + A1.w = R0; + R0.L = 0x00ff; + A1.x = R0.L; + R0.L = 0x0000; + R0.H = 0x0000; + CC = R0; + R2.L = CC = BXOR( A0 , A1, CC ); + R0 = A0.w; + DBGA ( R0.L , 0x1000 ); + DBGA ( R0.H , 0x0000 ); + R0.L = A0.x; + DBGA ( R0.L , 0x0000 ); + DBGA ( R2.L , 0x0001 ); + R0 = CC; + DBGA ( R0.L , 0x0001 ); + + pass diff --git a/sim/testsuite/bfin/s12.s b/sim/testsuite/bfin/s12.s new file mode 100644 index 0000000..2f66798 --- /dev/null +++ b/sim/testsuite/bfin/s12.s @@ -0,0 +1,84 @@ +// Shifter test program. +// Test instructions +// RL5 = EXPADJ R4 BY RL2; +# mach: bfin + +.include "testutils.inc" + start + + + R0.L = 30; // large norm of small value + R0.H = 1; // make sure high half is not used + R1.L = 0x0000; + R1.H = 0x1000; // small norm (2) of large value + R7.L = EXPADJ( R1 , R0.L ); + DBGA ( R7.L , 0x0002 ); + + R0.L = 3; // small norm of large value + R0.H = 1; // make sure high half is not used + R1.L = 0x0000; + R1.H = 0xff00; // small norm (2) of large value + R7.L = EXPADJ( R1 , R0.L ); + DBGA ( R7.L , 0x0003 ); + + R0.L = 3; + R0.H = 1; + R1.L = 0xffff; + R1.H = 0xffff; + R7.L = EXPADJ( R1 , R0.L ); + DBGA ( R7.L , 0x0003 ); + + R0.L = 31; + R0.H = 1; + R1.L = 0x0000; // norm=0 + R1.H = 0x8000; + R7.L = EXPADJ( R1 , R0.L ); + DBGA ( R7.L , 0x0000 ); + +// RL5 = EXPADJ/EXPADJ R4 BY RL2; + + R0.L = 15; + R1.L = 0x0800; + R1.H = 0x1000; + R7.L = EXPADJ( R1 , R0.L ) (V); + DBGA ( R7.L , 0x0002 ); + + R0.L = 15; + R1.L = 0x1000; + R1.H = 0x0800; + R7.L = EXPADJ( R1 , R0.L ) (V); + DBGA ( R7.L , 0x0002 ); + + R0.L = 1; + R1.L = 0x0800; + R1.H = 0x1000; + R7.L = EXPADJ( R1 , R0.L ) (V); + DBGA ( R7.L , 0x0001 ); + + R0.L = 14; + R1.L = 0xff00; + R1.H = 0xfff0; + R7.L = EXPADJ( R1 , R0.L ) (V); + DBGA ( R7.L , 0x0007 ); + +// RL5 = EXPADJ RL4 BY RL2; + + R0.L = 14; + R1.L = 0xff00; + R1.H = 0x1000; + R7.L = EXPADJ( R1.L , R0.L ); + DBGA ( R7.L , 0x0007 ); + + R0.L = 3; + R1.L = 0xff00; + R1.H = 0x1000; + R7.L = EXPADJ( R1.L , R0.L ); + DBGA ( R7.L , 0x0003 ); + + R0.L = 14; + R1.L = 0x1000; + R1.H = 0xff00; + R7.L = EXPADJ( R1.H , R0.L ); + DBGA ( R7.L , 0x0007 ); + + pass diff --git a/sim/testsuite/bfin/s13.s b/sim/testsuite/bfin/s13.s new file mode 100644 index 0000000..22b77b7 --- /dev/null +++ b/sim/testsuite/bfin/s13.s @@ -0,0 +1,215 @@ +// Test rl3 = ashift (rh0 by r5; +// Test rl3 = lshift (rh0 by r5); +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + + R0 = 0; + ASTAT = R0; + R0.L = 0x1; + R0.H = 0x1; + R5.L = 4; + R7.L = ASHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x0010 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R0.L = 0x8000; + R0.H = 0x1; + R5.L = -4; + R5.H = 0; + R7.L = ASHIFT R0.L BY R5.L; + DBGA ( R7.L , 0xf800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R0.L = 0x0; + R0.H = 0x1; + R5.L = 0; + R5.H = 0; + R7.L = ASHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R5.L = -4; + R5.H = 0; + R7.H = ASHIFT R0.H BY R5.L; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0xf800 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R5.L = -4; + R5.H = 0; + R7.L = ASHIFT R0.H BY R5.L; + DBGA ( R7.L , 0xf800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0xffff; + R5.L = 31; // should accept mag of +31 + R5.H = 0; + R7.L = ASHIFT R0.H BY R5.L; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x0100; + R5.L = 63; // mag of 63 will appear as -1 since 6 bits are masked + R5.H = 0; + R7.L = ASHIFT R0.H BY R5.L; + DBGA ( R7.L , 0x0080 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic shifts + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R5.L = -4; + R5.H = 0; + R7.L = LSHIFT R0.H BY R5.L; + DBGA ( R7.L , 0x0800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x1; + R5.L = 4; + R5.H = 0; + R7.H = LSHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0010 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x0; + R0.H = 0x0; + R5.L = 0; + R5.H = 0; + R7.L = LSHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x1; + R0.H = 0x0; + R5.L = 15; + R5.H = 0; + R7.L = LSHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x0100; + R0.H = 0x0; + R5.L = 63; // mag of 63 will appear as -1 since 6 bits are masked + R5.H = 0; + R7.L = LSHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x0080 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x0100; + R0.H = 0x0; + R5.L = 31; // should accept mag of +31 + R5.H = 0; + R7.L = LSHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/bfin/s14.s b/sim/testsuite/bfin/s14.s new file mode 100644 index 0000000..99814ee --- /dev/null +++ b/sim/testsuite/bfin/s14.s @@ -0,0 +1,350 @@ +// reg-based SHIFT test program. +// Test r4 = ASHIFT (r2 by rl3); +// Test r4 = LSHIFT (r2 by rl3); +# mach: bfin + +.include "testutils.inc" + start + + + R0.L = 0x0001; + R0.H = 0x8000; + +// arithmetic +// left by 31 +// 8000 0001 -> 8000 0000 + R7 = 0; + ASTAT = R7; + R3.L = 31; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 32 +// 8000 0001 -> 8000 0000 + R7 = 0; + ASTAT = R7; + R3.L = 32; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 40 +// 8000 0001 -> 8000 0000 + R7 = 0; + ASTAT = R7; + R3.L = 40; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0xFF80 ); + DBGA ( R6.H , 0xFFFF ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by -32 +// 8000 0001 -> 8000 0000 + R7 = 0; + ASTAT = R7; + R3.L = -32; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 63 (off scale) +// 8000 0001 -> 0000 0000 + R7 = 0; + ASTAT = R7; + R0.L = 1; + R0.H = 0; + R3.L = 63; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 255 looks like -1 (mask 7 bits) +// 8000 0001 -> 0000 0000 + R7 = 0; + ASTAT = R7; + R0.L = 0x0100; + R0.H = 0; + R3.L = 255; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0080 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 +// 8000 0001 -> 0000 0002 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = 1; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 1 +// 8000 0001 -> 0000 0002 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = -1; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xc000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by -31 +// 8000 0001 -> ffff ffff + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = -31; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// left by largest positive magnitude of 31 (0x1f) +// 8000 0001 -> 8000 0000 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = 31; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// left by 1 +// 8000 0001 -> 0000 0002 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = 1; + R3.H = 0; + R6 = LSHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// right by 1 +// 8000 0001 -> 4000 0000 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = -1; + R3.H = 0; + R6 = LSHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0001 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = -31; + R3.H = 0; + R6 = LSHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// right by -32 +// 8000 0001 -> 0000 0001 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = -32; + R3.H = 0; + R6 = LSHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// by +40 +// 8000 0001 -> 0000 0001 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = 40; + R3.H = 0; + R6 = LSHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0080 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// rot +// left by 1 +// 8000 0001 -> 0000 0002 cc=1 + R7 = 0; + CC = R7; + R6 = ROT R0 BY 1; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; DBGA ( R7.L , 0x0001 ); + +// rot +// right by -1 +// 8000 0001 -> 4000 0000 cc=1 + R7 = 0; + CC = R7; + R6 = ROT R0 BY -1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + R7 = CC; DBGA ( R7.L , 0x0001 ); + +// rot +// right by largest positive magnitude of 31 +// 8000 0001 -> a000 0000 cc=0 + R7 = 0; + CC = R7; + R6 = ROT R0 BY 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xa000 ); + R7 = CC; DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest positive magnitude of 31 with cc=1 +// 8000 0001 cc=1 -> a000 0000 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xe000 ); + R7 = CC; DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0005 cc=0 + R7 = 0; + CC = R7; + R6 = ROT R0 BY -31; + DBGA ( R6.L , 0x0005 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 with cc=1 +// 8000 0001 cc=1 -> 0000 0007 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY -31; + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; DBGA ( R7.L , 0x0000 ); + +// rot +// left by 7 +// 8000 0001 cc=1 -> 0000 00e0 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 7; + DBGA ( R6.L , 0x00e0 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; DBGA ( R7.L , 0x0000 ); + +// rot by zero +// 8000 0001 -> 8000 000 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 0; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x8000 ); + R7 = CC; DBGA ( R7.L , 0x0001 ); + +// 0 by 1 + R7 = 0; + R0 = 0; + ASTAT = R7; + R6 = R0 << 1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/bfin/s15.s b/sim/testsuite/bfin/s15.s new file mode 100644 index 0000000..9c32d48 --- /dev/null +++ b/sim/testsuite/bfin/s15.s @@ -0,0 +1,149 @@ +// reg-based SHIFT test program. +# mach: bfin + +.include "testutils.inc" + start + + +// Test FEXT with no sign extension + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0810; // pos=8 len=16 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x34de ); + DBGA ( R7.H , 0 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0814; // pos=8 len=20 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x34de ); + DBGA ( R7.H , 0x0002 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0800; // pos=8 len=0 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x0001; // pos=0 len=1 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x1 ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x0101; // pos=1 len=1 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x1810; // pos=24 len=16 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x00ff ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x0020; // pos=0 len=32 is like pos=0 len=0 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x0 ); + DBGA ( R7.H , 0x0 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x2020; // pos=32 len=32 is like pos=0 len=0 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x1f01; // pos=31 len=1 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x1 ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x1000; // pos=16 len=0 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + +// Test FEXT with sign extension + + R0.L = 0xdead; + R0.H = 0x12f4; + R1.L = 0x0810; // pos=8 len=16 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0xf4de ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0810; // pos=8 len=16 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0x34de ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xdead; + R0.H = 0xf234; + R1.L = 0x1f01; // pos=31 len=1 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdead; + R0.H = 0xf234; + R1.L = 0x1f02; // pos=31 len=2 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x101f; // pos=16 len=31 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x1001; // pos=16 len=1 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x1000; // pos=16 len=0 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/bfin/s16.s b/sim/testsuite/bfin/s16.s new file mode 100644 index 0000000..6741cf3 --- /dev/null +++ b/sim/testsuite/bfin/s16.s @@ -0,0 +1,170 @@ +// reg-based SHIFT test program. +# mach: bfin + +.include "testutils.inc" + start + + +// Test FDEP with no sign extension + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c08; // pos=12 len=8 + R1.H = 0x00ff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0x123f ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c04; // pos=12 len=4 + R1.H = 0x00ff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0x1234 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c05; // pos=12 len=5 + R1.H = 0x00ff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0x1235 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0010; // pos=0 len=16 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x1234 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0011; // pos=0 len=17 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x1234 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0114; // pos=1 len=20 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x1235 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x001f; // pos=0 len=31 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x1234 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x1c04; // pos=28 len=4 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xdead ); + DBGA ( R7.H , 0xf234 ); + + R0.L = 0xdead; + R0.H = 0x0234; + R1.L = 0x1d04; // pos=29 len=4 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xdead ); + DBGA ( R7.H , 0xe234 ); + + R0.L = 0xdead; + R0.H = 0x0234; + R1.L = 0x1f04; // pos=31 len=4 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xdead ); + DBGA ( R7.H , 0x8234 ); + + R0.L = 0xdead; + R0.H = 0x0234; + R1.L = 0x2004; // pos=32 len=4, same as pos=0 len=4 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xdeaf ); + DBGA ( R7.H , 0x0234 ); + +// Test FDEP with sign extension + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c08; // pos=12 len=8 + R1.H = 0x00ff; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c08; // pos=12 len=8 + R1.H = 0x007f; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0x0007 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0110; // pos=1 len=16 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0101; // pos=1 len=1 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0102; // pos=1 len=2 + R1.H = 0x0001; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0x0002 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0002; // pos=0 len=2 + R1.H = 0x0001; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0000; // pos=0 len=0 + R1.H = 0x000f; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/bfin/s17.s b/sim/testsuite/bfin/s17.s new file mode 100644 index 0000000..530a93b --- /dev/null +++ b/sim/testsuite/bfin/s17.s @@ -0,0 +1,46 @@ +// shifter test program. +// Test instructions ONES +# mach: bfin + +.include "testutils.inc" + start + + + R7 = 0; + ASTAT = R7; + R0.L = 0x1; + R0.H = 0x0; + R7.L = ONES R0; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0000; + R0.H = 0x8000; + R7.L = ONES R0; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + + R0.L = 0x0001; + R0.H = 0x8000; + R7.L = ONES R0; + DBGA ( R7.L , 0x0002 ); + DBGA ( R7.H , 0x0000 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R7.L = ONES R0; + DBGA ( R7.L , 0x0020 ); + DBGA ( R7.H , 0x0000 ); + + R0.L = 0x0000; + R0.H = 0x0000; + R7.L = ONES R0; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + + pass diff --git a/sim/testsuite/bfin/s18.s b/sim/testsuite/bfin/s18.s new file mode 100644 index 0000000..6f26cc8 --- /dev/null +++ b/sim/testsuite/bfin/s18.s @@ -0,0 +1,132 @@ +// Immediate dual 16b SHIFT test program. +// Test r4 = ASHIFT/ASHIFT (r2 by 10); +// Test r4 = ASHIFT/ASHIFT (r2 by 10) S; +// Test r4 = LSHIFT/LSHIFT (r2 by 10); +# mach: bfin + +.include "testutils.inc" + start + + +// arithmetic +// left by largest positive magnitude of 15 (0xf) +// 8001 -> 8000 + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R6 = R0 << 15 (V); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by largest positive magnitude of 15 (0xf) with saturation + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R6 = R0 << 15 (V , S); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R6 = R0 << 1 (V); + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0200 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 saturating + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R6 = R0 << 1 (V , S); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x0200 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 15 saturating + R7 = 0; + ASTAT = R7; + R0.L = 0xfff0; + R0.H = 0x0000; + R6 = R0 << 15 (V , S); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 15 + R7 = 0; + ASTAT = R7; + R0.L = 0x8000; + R0.H = 0x0100; + R6 = R0 >>> 15 (V); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 15 (sat has no effect) + R7 = 0; + ASTAT = R7; + R0.L = 0x8000; + R0.H = 0x0100; + R6 = R0 >>> 15 (V); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// right by 15 + R7 = 0; + ASTAT = R7; + R0.L = 0x8000; + R0.H = 0x0100; + R6 = R0 >> 15 (V); + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/bfin/s19.s b/sim/testsuite/bfin/s19.s new file mode 100644 index 0000000..8e37ca2 --- /dev/null +++ b/sim/testsuite/bfin/s19.s @@ -0,0 +1,140 @@ +// REG-BASED dual 16b SHIFT test program. +// Test r4 = ASHIFT/ASHIFT (r2 by rl1); +// Test r4 = ASHIFT/ASHIFT (r2 by rl1) S; +// Test r4 = LSHIFT/LSHIFT (r2 by rl1); +# mach: bfin + +.include "testutils.inc" + start + + +// arithmetic +// left by largest positive magnitude of 15 (0xf) +// 8001 -> 8000 + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R1.L = 15; + R6 = ASHIFT R0 BY R1.L (V); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by largest positive magnitude of 15 (0xf) with saturation + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R1.L = 15; + R6 = ASHIFT R0 BY R1.L (V , S); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R1.L = 1; + R6 = ASHIFT R0 BY R1.L (V); + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0200 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 saturating + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R1.L = 1; + R6 = ASHIFT R0 BY R1.L (V , S); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x0200 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 15 saturating + R7 = 0; + ASTAT = R7; + R0.L = 0xfff0; + R0.H = 0x0000; + R1.L = 15; + R6 = ASHIFT R0 BY R1.L (V , S); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 15 + R7 = 0; + ASTAT = R7; + R0.L = 0x8000; + R0.H = 0x0100; + R1.L = -15; + R6 = ASHIFT R0 BY R1.L (V); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 15 (sat has no effect) + R7 = 0; + ASTAT = R7; + R0.L = 0x8000; + R0.H = 0x0100; + R1.L = -15; + R6 = ASHIFT R0 BY R1.L (V , S); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// right by 15 + R7 = 0; + ASTAT = R7; + R0.L = 0x8000; + R0.H = 0x0100; + R1.L = -15; + R6 = LSHIFT R0 BY R1.L (V); + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/bfin/s2.s b/sim/testsuite/bfin/s2.s new file mode 100644 index 0000000..4b8ab2d --- /dev/null +++ b/sim/testsuite/bfin/s2.s @@ -0,0 +1,47 @@ +# mach: bfin + +.include "testutils.inc" + start + +// Test pc relative indirect branches. + P4 = 0; + loadsym P1 jtab; + +LL1: + P2 = P1 + ( P4 << 1 ); + R0 = W [ P2 ] (Z); + P0 = R0; + R2 = P4; + +jp: + JUMP ( PC + P0 ); + + DBGA ( R2.L , 0 ); + JUMP.L done; + + DBGA ( R2.L , 1 ); + JUMP.L done; + + DBGA ( R2.L , 2 ); + JUMP.L done; + + DBGA ( R2.L , 3 ); + JUMP.L done; + + DBGA ( R2.L , 4 ); + JUMP.L done; + +done: + P4 += 1; + CC = P4 < 4 (IU); + IF CC JUMP LL1; + pass + + .data + +jtab: + .dw 2; //.dw (2+0*8) + .dw 10; //.dw (2+1*8) + .dw 18; //.dw (2+2*8) + .dw 26; //.dw (2+3*8) + .dw 34; //.dw (2+4*8) diff --git a/sim/testsuite/bfin/s20.s b/sim/testsuite/bfin/s20.s new file mode 100644 index 0000000..7f97d22 --- /dev/null +++ b/sim/testsuite/bfin/s20.s @@ -0,0 +1,25 @@ +// Test byte-align instructions +# mach: bfin + +.include "testutils.inc" + start + + + R0.L = 0xabcd; + R0.H = 0x1234; + R1.L = 0x4567; + R1.H = 0xdead; + + R2 = ALIGN8 ( R1 , R0 ); + DBGA ( R2.L , 0x34ab ); + DBGA ( R2.H , 0x6712 ); + + R2 = ALIGN16 ( R1 , R0 ); + DBGA ( R2.L , 0x1234 ); + DBGA ( R2.H , 0x4567 ); + + R2 = ALIGN24 ( R1 , R0 ); + DBGA ( R2.L , 0x6712 ); + DBGA ( R2.H , 0xad45 ); + + pass diff --git a/sim/testsuite/bfin/s21.s b/sim/testsuite/bfin/s21.s new file mode 100644 index 0000000..b528dd9 --- /dev/null +++ b/sim/testsuite/bfin/s21.s @@ -0,0 +1,298 @@ +// Copyright (c) 1997,1998,1999 Analog Devices Inc., All Rights Reserved +// Test A0 = ROT (A0 by imm6); +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + A0 = A1 = 0; + +// rot +// left by 1 +// 00 8000 0001 -> 01 0000 0002 cc=0 + R0.L = 0x0001; + R0.H = 0x8000; + R7 = 0; + CC = R7; + A1 = A0 = 0; + A0.w = R0; + A0 = ROT A0 BY 1; + R1 = A0.w; + DBGA ( R1.L , 0x0002 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0001 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by 1 +// 80 0000 0001 -> 00 0000 0002 cc=1 + R7 = 0; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 1; + R1 = A0.w; + DBGA ( R1.L , 0x0002 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// left by 1 with cc=1 +// 80 8000 0001 -> 01 0000 0003 cc=1 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x8000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 1; + R1 = A0.w; + DBGA ( R1.L , 0x0003 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0001 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// left by 2 with cc=1 +// 80 0000 0001 -> 00 0000 0007 cc=0 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 2; + R1 = A0.w; + DBGA ( R1.L , 0x0007 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by 3 with cc=0 + R7 = 0; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 3; + R1 = A0.w; + DBGA ( R1.L , 0x000a ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by largest positive magnitude of 31 +// 80 0000 0001 -> 00 a000 0000 cc=0 + R7 = 0; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 31; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0xa000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by 1 +// 80 0000 0001 -> 40 0000 0000 cc=1 + R7 = 0; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY -1; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0040 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by 1 +// 80 0000 0001 -> c0 0000 0000 cc=1 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY -1; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0xffc0 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by 2 +// 80 0000 0001 -> e0 0000 0000 cc=0 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY -2; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0xffe0 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by 9 +// 80 0000 0001 -> 01 c000 0000 cc=0 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY -9; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0xc000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0001 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by 9 with reg +// 80 0000 0001 -> 01 c000 0000 cc=0 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + R5 = -9; + A0 = ROT A0 BY R5.L; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0xc000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0001 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot left by 4 with cc=1 + R0.L = 0x789a; + R0.H = 0x3456; + A0.w = R0; + R0.L = 0x12; + A0.x = R0; + + R0 = 1; + CC = R0; + + A0 = ROT A0 BY 4; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x4567 ); DBGA ( R4.L , 0x89a8 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0023 ); + +// rot left by 28 with cc=1 + R0.L = 0x789a; + R0.H = 0x3456; + A0.w = R0; + R0.L = 0x12; + A0.x = R0; + + R0 = 1; + CC = R0; + + A0 = ROT A0 BY 28; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xa891 ); DBGA ( R4.L , 0xa2b3 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff89 ); + +// rot right by 4 with cc=1 + R0.L = 0x789a; + R0.H = 0x3456; + A0.w = R0; + R0.L = 0x12; + A0.x = R0; + + R0 = 1; + CC = R0; + + A0 = ROT A0 BY -4; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x2345 ); DBGA ( R4.L , 0x6789 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0051 ); + +// rot right by 8 with cc=1 + R0.L = 0x789a; + R0.H = 0x3456; + A0.w = R0; + R0.L = 0x12; + A0.x = R0; + + R0 = 1; + CC = R0; + + A0 = ROT A0 BY -28; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xcf13 ); DBGA ( R4.L , 0x5123 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff8a ); + + pass diff --git a/sim/testsuite/bfin/s3.s b/sim/testsuite/bfin/s3.s new file mode 100644 index 0000000..d3178a4 --- /dev/null +++ b/sim/testsuite/bfin/s3.s @@ -0,0 +1,88 @@ +// SHIFT test program. +// Test A0 = ASHIFT (A0 by r3); +# mach: bfin + +.include "testutils.inc" + start + +// load r0=0x0000001f +// load r1=0x00000020 +// load r2=0x00000000 +// load r3=0x00000000 +// load r4=0x00000001 +// load r5=0x00000080 + loadsym P0, data0; + P1 = P0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + +// left by largest positive magnitude of 31 (0x1f) +// A0: 80 0000 0001 -> 80 0000 0000 + R7 = 0; + ASTAT = R7; + A0.w = R4; + A0.x = R5.L; + A0 = ASHIFT A0 BY R0.L; + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + DBGA ( R7.L , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// left by largest positive magnitude + 1 = 32 (0x20), which is -32 +// A0: 80 0000 0001 -> + R7 = 0; + ASTAT = R7; + A0.w = R4; + A0.x = R5.L; + A0 = ASHIFT A0 BY R1.L; + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0xff80 ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// by -1 +// A0: 80 0000 0001 -> c0 0000 0000 + A0.w = R4; + A0.x = R5.L; + + R3.L = 0x00ff; + + A0 = ASHIFT A0 BY R3.L; + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xffc0 ); + + pass + + .data +data0: + .dw 0x001f + .dw 0x0000 + .dw 0x0020 + .dw 0x0000 + .dw 0x0059 + .dw 0x0000 + .dw 0x005a + .dw 0x0000 + .dw 0x0001 + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/bfin/s30.s b/sim/testsuite/bfin/s30.s new file mode 100644 index 0000000..4ec6ef4 --- /dev/null +++ b/sim/testsuite/bfin/s30.s @@ -0,0 +1,152 @@ +// Test signbits40 +# mach: bfin + +.include "testutils.inc" + start + + +// positive value in accum, smaller than 1.0 + A1 = A0 = 0; + R0.L = 0xffff; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0x8000 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); + +// neg value in accum, larger than -1.0 + A1 = A0 = 0; + R0.L = 0x0000; + R0.H = 0xffff; + A0.w = R0; + R0.L = 0x00ff; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); + +// positive value in accum, larger than 1.0 + A1 = A0 = 0; + R0.L = 0xffff; + R0.H = 0xffff; + A0.w = R0; + R0.L = 0x000f; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); + +// negative value in accum, smaller than -1.0 + A1 = A0 = 0; + R0.L = 0x0000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0080; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); + +// no normalization + A1 = A0 = 0; + R0.L = 0xfffa; + R0.H = 0x7fff; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0xfffa ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); + +// no normalization (-1.0) + A1 = A0 = 0; + R0.L = 0x0000; + R0.H = 0x8000; + A0.w = R0; + R0.L = 0x00ff; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); + +// norm by 1 + A1 = A0 = 0; + R0.L = 0x0000; + R0.H = 0x8000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x4000 ); DBGA ( R4.L , 0x0000 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); + +// norm by 1 + A1 = A0 = 0; + R0.L = 0x0000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x00ff; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); + + pass diff --git a/sim/testsuite/bfin/s4.s b/sim/testsuite/bfin/s4.s new file mode 100644 index 0000000..784c57d --- /dev/null +++ b/sim/testsuite/bfin/s4.s @@ -0,0 +1,214 @@ +// Immediate SHIFT test program. +// Test r4 = ASHIFT (r2 by 10); +// Test r4 = LSHIFT (r2 by 10); +// Test r4 = ROT (r2 by 10); +# mach: bfin + +.include "testutils.inc" + start + + + init_r_regs 0; + ASTAT = R0; + +// load r0=0x80000001 +// load r1=0x00000000 +// load r2=0x00000000 +// load r3=0x00000000 +// load r4=0x00000000 +// load r5=0x00000000 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + +// arithmetic +// left by largest positive magnitude of 31 (0x1f) +// 8000 0001 -> 8000 0000 + R7 = 0; + ASTAT = R7; + R6 = R0 << 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 +// 8000 0001 -> 0000 0002 + R6 = R0 << 1; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 1 +// 8000 0001 -> c000 0000 + R7 = 0; + ASTAT = R7; + R6 = R0 >>> 1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xc000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by largest negative magnitude of -31 +// 8000 0001 -> ffff ffff + R6 = R0 >>> 31; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + +// logic +// left by largest positive magnitude of 31 (0x1f) +// 8000 0001 -> 8000 0000 + R6 = R0 << 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + +// logic +// left by 1 +// 8000 0001 -> 0000 0002 + R6 = R0 << 1; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + +// logic +// right by 1 +// 8000 0001 -> 4000 0000 + R6 = R0 >> 1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + +// logic +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0001 + R6 = R0 >> 31; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x0000 ); + +// rot +// left by 1 +// 8000 0001 -> 0000 0002 cc=1 + R7 = 0; + CC = R7; + R6 = ROT R0 BY 1; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by -1 +// 8000 0001 -> 4000 0000 cc=1 + R7 = 0; + CC = R7; + R6 = ROT R0 BY -1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by largest positive magnitude of 31 +// 8000 0001 -> a000 0000 cc=0 + R7 = 0; + CC = R7; + R6 = ROT R0 BY 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xa000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest positive magnitude of 31 with cc=1 +// 8000 0001 cc=1 -> a000 0000 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xe000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0005 cc=0 + R7 = 0; + CC = R7; + R6 = ROT R0 BY -31; + DBGA ( R6.L , 0x0005 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 with cc=1 +// 8000 0001 cc=1 -> 0000 0007 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY -31; + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by 7 +// 8000 0001 cc=1 -> 0000 00e0 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 7; + DBGA ( R6.L , 0x00e0 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot by zero +// 8000 0001 -> 8000 000 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 0; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x8000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// 0 by 1 + R7 = 0; + R0 = 0; + ASTAT = R7; + R6 = R0 << 1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass + + .data +data0: + .dw 0x0001 + .dw 0x8000 + .dd 0x0000 + .dd 0x0 + .dd 0x0 + .dd 0x0 + .dd 0x0 + .dd 0x0 diff --git a/sim/testsuite/bfin/s5.s b/sim/testsuite/bfin/s5.s new file mode 100644 index 0000000..7f38cd4 --- /dev/null +++ b/sim/testsuite/bfin/s5.s @@ -0,0 +1,118 @@ +// Test r4 = ROT (r2 by r3); +# mach: bfin + +.include "testutils.inc" + start + + + R0.L = 0x0001; + R0.H = 0x8000; + +// rot +// left by 1 +// 8000 0001 -> 0000 0002 cc=1 + R7 = 0; + CC = R7; + R1 = 1; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by -1 +// 8000 0001 -> 4000 0000 cc=1 + R7 = 0; + CC = R7; + R1.L = 0xffff; // check alternate mechanism for immediates + R1.H = 0xffff; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by largest positive magnitude of 31 +// 8000 0001 -> a000 0000 cc=0 + R7 = 0; + CC = R7; + R1 = 31; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xa000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest positive magnitude of 31 with cc=1 +// 8000 0001 cc=1 -> a000 0000 cc=0 + R7 = 1; + CC = R7; + R1 = 31; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xe000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0005 cc=0 + R7 = 0; + CC = R7; + R1 = -31; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0005 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 with cc=1 +// 8000 0001 cc=1 -> 0000 0007 cc=0 + R7 = 1; + CC = R7; + R1 = -31; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by 7 +// 8000 0001 cc=1 -> 0000 00e0 cc=0 + R7 = 1; + CC = R7; + R1 = 7; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x00e0 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot by zero +// 8000 0001 -> 8000 0000 + R7 = 1; + CC = R7; + R1 = 0; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x8000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot by 0b1100 0001 is the same as by 1 (mask 6 bits) +// 8000 0001 -> 0000 0002 cc=1 + R7 = 0; + CC = R7; + R1 = 0xc1 (X); + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + + pass diff --git a/sim/testsuite/bfin/s6.s b/sim/testsuite/bfin/s6.s new file mode 100644 index 0000000..6fc9a2b --- /dev/null +++ b/sim/testsuite/bfin/s6.s @@ -0,0 +1,83 @@ +// Test r4 = VMAX/VMAX (r5,r1) A0<<2; +# mach: bfin + +.include "testutils.inc" + start + + +// Both max values are in high half, hence both bits +// into A0 are 1 + A0 = 0; + R1.L = 0x2; // max in r1 is 3 + R1.H = 0x3; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASL); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0003 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// max value in r1 is in low, so second bit into A0 is zero + A0 = 0; + R1.L = 0x3; // max in r1 is 3 + R1.H = 0x2; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASL); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0002 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// both max values in low, so both bits into A0 are zero + R0.L = 0x8000; + R0.H = 0x0; + A0.w = R0; + R1.L = 0x3; // max in r1 is 3 + R1.H = 0x2; + + R0.L = 0x7; // max in r0 is 7 + R0.H = 0x6; + + R6 = VIT_MAX( R1 , R0 ) (ASL); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0002 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// Test for correct max when one value overflows + A0 = 0; + R1.L = 0x7fff; // max in r1 is 0x8001 (overflowed) + R1.H = 0x8001; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASL); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x8001 ); + R7 = A0.w; + DBGA ( R7.L , 0x0003 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + + pass diff --git a/sim/testsuite/bfin/s7.s b/sim/testsuite/bfin/s7.s new file mode 100644 index 0000000..0cda60e --- /dev/null +++ b/sim/testsuite/bfin/s7.s @@ -0,0 +1,83 @@ +// Test r4 = VMAX/VMAX (r5,r1) A0>>2; +# mach: bfin + +.include "testutils.inc" + start + + +// Both max values are in high half, hence both bits +// into A0 are 1 + A0 = 0; + R1.L = 0x2; // max in r1 is 3 + R1.H = 0x3; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASR); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0xc000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// max value in r1 is in low, so second bit into A0 is zero + A0 = 0; + R1.L = 0x3; // max in r1 is 3 + R1.H = 0x2; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASR); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x4000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// both max values in low, so both bits into A0 are zero + R0.L = 0x8000; + R0.H = 0x0; + A0.w = R0; + R1.L = 0x3; // max in r1 is 3 + R1.H = 0x2; + + R0.L = 0x7; // max in r0 is 7 + R0.H = 0x6; + + R6 = VIT_MAX( R1 , R0 ) (ASR); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x2000 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// Test for correct max when one value overflows + A0 = 0; + R1.L = 0x7fff; // max in r1 is 0x8001 (overflowed) + R1.H = 0x8001; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASR); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x8001 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0xc000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + + pass diff --git a/sim/testsuite/bfin/s8.s b/sim/testsuite/bfin/s8.s new file mode 100644 index 0000000..46d156e --- /dev/null +++ b/sim/testsuite/bfin/s8.s @@ -0,0 +1,55 @@ +// Test rl4 = VMAX r5 A0<<1; +// Test rl4 = VMAX r5 A0>>1; +# mach: bfin + +.include "testutils.inc" + start + + +// max value in high half, hence bit into A0 is one + A0 = 0; + R1.L = 0x2; // max in r1 is 3 + R1.H = 0x3; + + R6.L = VIT_MAX( R1 ) (ASL); + + DBGA ( R6.L , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// max value in low half, hence bit into A0 is zero + R0.L = 0x8000; + R0.H = 0x8000; + A0.w = R0; + R1.L = 0x8001; // max in r1 is 8001 + R1.H = 0x7f00; + + R6.L = VIT_MAX( R1 ) (ASL); + + DBGA ( R6.L , 0x8001 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0001 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0001 ); + +// max value in high half, hence bit into A0 is one + R0.L = 0x8000; + R0.H = 0x0000; + A0.w = R0; + R1.L = 0x7fff; // max in r1 is 8001 + R1.H = 0x8001; + + R6.L = VIT_MAX( R1 ) (ASR); + + DBGA ( R6.L , 0x8001 ); + R7 = A0.w; + DBGA ( R7.L , 0x4000 ); + DBGA ( R7.H , 0x8000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + + pass diff --git a/sim/testsuite/bfin/s9.s b/sim/testsuite/bfin/s9.s new file mode 100644 index 0000000..7293e3a --- /dev/null +++ b/sim/testsuite/bfin/s9.s @@ -0,0 +1,134 @@ +// Test rl3 = ashift (rh0 by 7); +// Test rl3 = lshift (rh0 by 7); +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + + R0 = 0; + ASTAT = R0; + R0.L = 0x1; + R0.H = 0x1; + R7.L = R0.L << 4; + DBGA ( R7.L , 0x0010 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R0.L = 0x8000; + R0.H = 0x1; + R7.L = R0.L >>> 4; + DBGA ( R7.L , 0xf800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R0.L = 0x0; + R0.H = 0x1; + R7.L = R0.L << 0; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R7.H = R0.H >>> 4; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0xf800 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R7.L = R0.H >>> 4; + DBGA ( R7.L , 0xf800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic shifts + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R7.L = R0.H >> 4; + DBGA ( R7.L , 0x0800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x1; + R7.H = R0.L << 4; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0010 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x0; + R0.H = 0x0; + R7.L = R0.L << 0; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x1; + R0.H = 0x0; + R7.L = R0.L << 15; + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/bfin/saatest.s b/sim/testsuite/bfin/saatest.s new file mode 100644 index 0000000..3957627 --- /dev/null +++ b/sim/testsuite/bfin/saatest.s @@ -0,0 +1,222 @@ +# mach: bfin + +.include "testutils.inc" + start + + + I0 = 0 (X); + I1 = 0 (X); + A0 = A1 = 0; + init_r_regs 0; + ASTAT = R0; + +// This section of code will test the SAA instructions and sum of accumulators; + + loadsym I0, tstvecI; + + R0 = [ I0 ++ ]; + R2 = [ I0 ++ ]; + +// +++++++++++++++ TG11.001 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 15 15 15 15 // +// r1 ==> 0 0 0 0 // +// // +// Output:r2 ==> 0 0 0 30 // +// r3 ==> 0 0 0 30 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + SAA ( R1:0 , R3:2 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x001e ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x001e ); + DBGA ( R7.H , 0x0000 ); + + A1 = A0 = 0; + +// +++++++++++++++ TG11.002 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 15 15 15 15 // +// r1 ==> 0 0 0 0 // +// // +// Output:r2 ==> 0 0 0 30 // +// r3 ==> 0 0 0 30 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + SAA ( R1:0 , R3:2 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x001e ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x001e ); + DBGA ( R7.H , 0x0000 ); + + A1 = A0 = 0; + +// +++++++++++++++ TG11.003 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 240 240 240 240 // +// r1 ==> 0 0 0 0 // +// // +// Output:r2 ==> 0 480 // +// r3 ==> 0 480 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + R0 = [ I0 ++ ]; + R2 = [ I0 ++ ]; + + SAA ( R3:2 , R1:0 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x01e0 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x01e0 ); + DBGA ( R7.H , 0x0000 ); + + A1 = A0 = 0; + +// +++++++++++++++ TG11.004 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 240 240 240 240 // +// r1 ==> 0 0 0 0 // +// // +// Output:r2 ==> 0 480 // +// r3 ==> 0 480 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + SAA ( R1:0 , R3:2 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x01e0 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x01e0 ); + DBGA ( R7.H , 0x0000 ); + + A1 = A0 = 0; +// +++++++++++++++ TG11.005 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 0 0 0 0 // +// r1 ==> 0 0 0 0 // +// // +// Output:r2 ==> 0 0 // +// r3 ==> 0 0 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + R0 = [ I0 ++ ]; + R2 = [ I0 ++ ]; + + SAA ( R1:0 , R3:2 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + +// +++++++++++++++ TG11.006 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 255 255 255 255 // +// r1 ==> 255 255 255 255 // +// // +// Output:r2 ==> 0 0 // +// r3 ==> 0 0 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + SAA ( R3:2 , R1:0 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + + A1 = A0 = 0; + +// +++++++++++++++ TG12.001 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 255 255 255 255 // +// r1 ==> 255 255 255 255 // +// // +// Output:r2 ==> 0 0 // +// r3 ==> 0 0 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + loadsym I0, tstvecK; + B0 = I0; + L0.L = 4; + loadsym I1, tstvecJ; + B1 = I1; + L1.L = 4; + + P0 = 64 (X); + R0 = [ I0 ++ ]; + R2 = [ I1 ++ ]; + LSETUP ( l$1 , l$1 ) LC0 = P0; +l$1: + SAA ( R1:0 , R3:2 ) || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; + + R2 = A1.L + A1.H, R3 = A0.L + A0.H; + R7 = R2 + R3 (NS); + DBGA ( R7.L , 0xff00 ); + DBGA ( R7.H , 0x0000 ); + + R5.L = 0xfffa; + A1 = R5; + R5.H = 0xfff0; + A0 = R5; + + loadsym I0, tstvecI; + R0 = [ I0 ++ ]; + R2 = [ I0 ++ ]; + SAA ( R1:0 , R3:2 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x000e ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0xffff ); + + pass + + .data +tstvecI: + .dw 0x0000 + .dw 0x0000 + .dw 0x0f0f + .dw 0x0f0f + .dw 0x0000 + .dw 0x0000 + .dw 0xf0f0 + .dw 0xf0f0 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0xffff + .dw 0xffff + .dw 0xffff + .dw 0xffff + + .data +tstvecJ: + .dw 0xffff + .dw 0xffff + .dw 0xffff + .dw 0xffff + .dw 0xffff + .dw 0xffff + .dw 0xffff + .dw 0xffff + + .data +tstvecK: + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/bfin/se_all16bitopcodes.S b/sim/testsuite/bfin/se_all16bitopcodes.S new file mode 100644 index 0000000..042621e --- /dev/null +++ b/sim/testsuite/bfin/se_all16bitopcodes.S @@ -0,0 +1,349 @@ +/* + * Blackfin testcase for testing illegal/legal 16-bit opcodes from userspace + * we track all instructions which cause some sort of exception when run from + * userspace, this is normally EXCAUSE : + * - 0x21 : illegal instruction + * - 0x22 : illegal instruction combination + * - 0x2e : use of supervisor resource from userspace + * and walk every instruction from 0x0000 to 0xbfff + */ + +# mach: bfin +# sim: --environment operating + +#include "test.h" + +#define SE_ALL_BITS 16 +#define SE_ALL_NEW_INSN_STUB +#include "se_allopcodes.h" + .include "testutils.inc" + +.macro se_all_load_insn + R2 = W[P5]; + R0 = R2; +.endm + +.macro se_all_next_insn + /* increment, and go again. */ + R0 = R2; + + R0 += 1; + /* finish once we hit the 32bit limit */ + R1 = 0xC000 (Z); + CC = R1 == R0; + IF CC JUMP pass_lvl; + + W[P5] = R0; +.endm + +.macro se_all_new_insn_stub + jump _legal_instruction; +.endm + +.macro se_all_insn_init + .dw 0x0000; +.endm +.macro se_all_insn_table + /* this table must be sorted, and end with zero */ + /* start end SEQSTAT */ + .dw 0x0001, 0x000f, 0x21 + .dw 0x0011, 0x0013, 0x2e +.ifndef BFIN_JTAG + .dw 0x0014, 0x0014, 0x2e /* anomaly - RTX works when emulator attached */ +.endif + .dw 0x0015, 0x001F, 0x21 + .dw 0x0021, 0x0022, 0x21 + .dw 0x0026, 0x0026, 0x21 +.ifndef BFIN_JTAG + .dw 0x0027, 0x0027, 0x21 /* anomaly 492 - unknown */ +.endif + .dw 0x0028, 0x002F, 0x21 + .dw 0x0030, 0x0037, 0x2e + .dw 0x0038, 0x003F, 0x21 + .dw 0x0040, 0x0047, 0x2e + .dw 0x0048, 0x004F, 0x21 + .dw 0x0058, 0x005F, 0x21 + .dw 0x0068, 0x006F, 0x21 + .dw 0x0078, 0x007F, 0x21 + .dw 0x0088, 0x008F, 0x21 + .dw 0x0090, 0x009F, 0x2E + .dw 0x00a0, 0x00a0, 0x00 + .dw 0x00a1, 0x00a1, 0x01 + .dw 0x00a2, 0x00a2, 0x02 + .dw 0x00a3, 0x00a3, 0x03 + .dw 0x00a4, 0x00a4, 0x04 + .dw 0x00a5, 0x00a5, 0x05 + .dw 0x00a6, 0x00a6, 0x06 + .dw 0x00a7, 0x00a7, 0x07 + .dw 0x00a8, 0x00a8, 0x08 + .dw 0x00a9, 0x00a9, 0x09 + .dw 0x00aa, 0x00aa, 0x0a + .dw 0x00ab, 0x00ab, 0x0b + .dw 0x00ac, 0x00ac, 0x0c + .dw 0x00ad, 0x00ad, 0x0d + .dw 0x00ae, 0x00ae, 0x0e + .dw 0x00af, 0x00af, 0x0f + .dw 0x00b6, 0x010f, 0x21 + .dw 0x0124, 0x0124, 0x21 +.ifndef BFIN_JTAG + .dw 0x0125, 0x0125, 0x21 /* anomaly 492 res = [SP++] */ +.endif + .dw 0x0128, 0x012F, 0x21 + .dw 0x0138, 0x0138, 0x22 + .dw 0x0139, 0x013F, 0x2E + .dw 0x0164, 0x0164, 0x21 +.ifndef BFIN_JTAG + .dw 0x0165, 0x0165, 0x21 /* anomaly 492 [--SP] = res */ +.endif + .dw 0x0168, 0x016F, 0x21 + .dw 0x0178, 0x017F, 0x2E + .dw 0x0180, 0x01FF, 0x21 + .dw 0x0210, 0x0217, 0x21 +.ifndef BFIN_JTAG + .dw 0x0219, 0x021F, 0x21 /* anomaly 492 CC = !CC opcode is 0000 0010 0001 1xxx */ +.endif + .dw 0x0220, 0x023F, 0x21 + .dw 0x0280, 0x02FF, 0x21 + .dw 0x0305, 0x0305, 0x21 + .dw 0x0325, 0x0325, 0x21 + .dw 0x0345, 0x0345, 0x21 + .dw 0x0365, 0x0365, 0x21 + .dw 0x0385, 0x0385, 0x21 + .dw 0x03a5, 0x03a5, 0x21 + .dw 0x03c5, 0x03c5, 0x21 + .dw 0x03e5, 0x03e5, 0x21 + .dw 0x0400, 0x047F, 0x21 + .dw 0x0486, 0x04Bf, 0x21 + .dw 0x04c6, 0x04FF, 0x21 + .dw 0x0501, 0x0507, 0x21 + .dw 0x0509, 0x050F, 0x21 + .dw 0x0511, 0x0517, 0x21 + .dw 0x0519, 0x051F, 0x21 + .dw 0x0521, 0x0527, 0x21 + .dw 0x0529, 0x052F, 0x21 + .dw 0x0531, 0x0537, 0x21 + .dw 0x0539, 0x053F, 0x21 + .dw 0x0541, 0x0547, 0x21 + .dw 0x0549, 0x054F, 0x21 + .dw 0x0551, 0x0557, 0x21 + .dw 0x0559, 0x055F, 0x21 + .dw 0x0561, 0x0567, 0x21 + .dw 0x0569, 0x056F, 0x21 + .dw 0x0571, 0x0577, 0x21 + .dw 0x0579, 0x057F, 0x21 + .dw 0x0586, 0x0587, 0x21 + .dw 0x058e, 0x058F, 0x21 + .dw 0x0596, 0x0597, 0x21 + .dw 0x059e, 0x059f, 0x21 + .dw 0x05a6, 0x05a7, 0x21 + .dw 0x05ae, 0x05af, 0x21 + .dw 0x05b6, 0x05b7, 0x21 + .dw 0x05be, 0x05bf, 0x21 + .dw 0x05c6, 0x05c7, 0x21 + .dw 0x05ce, 0x05cf, 0x21 + .dw 0x05d6, 0x05d7, 0x21 + .dw 0x05de, 0x05df, 0x21 + .dw 0x05e6, 0x05e7, 0x21 + .dw 0x05ee, 0x05ef, 0x21 + .dw 0x05f6, 0x05f7, 0x21 + .dw 0x05fe, 0x05ff, 0x21 + .dw 0x0a81, 0x0aff, 0x21 + .dw 0x0b01, 0x0b7f, 0x21 + .dw 0x0b81, 0x0bff, 0x21 + .dw 0x0e80, 0x0fff, 0x21 + .dw 0x3104, 0x3105, 0x21 + .dw 0x310c, 0x310d, 0x21 + .dw 0x3114, 0x3115, 0x21 + .dw 0x311c, 0x311d, 0x21 + .dw 0x3124, 0x3125, 0x21 + .dw 0x312c, 0x312d, 0x21 + .dw 0x3134, 0x3135, 0x21 + .dw 0x313c, 0x313d, 0x21 + .dw 0x3140, 0x317F, 0x21 + .dw 0x31c0, 0x31ff, 0x2E + .dw 0x3304, 0x3305, 0x21 + .dw 0x330c, 0x330d, 0x21 + .dw 0x3314, 0x3315, 0x21 + .dw 0x331c, 0x331d, 0x21 + .dw 0x3324, 0x3325, 0x21 + .dw 0x332c, 0x332d, 0x21 + .dw 0x3334, 0x3335, 0x21 + .dw 0x333c, 0x333d, 0x21 + .dw 0x3340, 0x337f, 0x21 + .dw 0x33c0, 0x33ff, 0x2e + .dw 0x3504, 0x3507, 0x21 + .dw 0x350c, 0x350F, 0x21 + .dw 0x3514, 0x3517, 0x21 + .dw 0x351c, 0x351F, 0x21 + .dw 0x3524, 0x3527, 0x21 + .dw 0x352c, 0x352f, 0x21 + .dw 0x3534, 0x3537, 0x21 + .dw 0x353c, 0x353f, 0x21 + .dw 0x3540, 0x35c6, 0x21 + .dw 0x35c7, 0x35c7, 0x2e + .dw 0x35c8, 0x35ce, 0x21 + .dw 0x35cf, 0x35cf, 0x2e + .dw 0x35d0, 0x35d6, 0x21 + .dw 0x35d7, 0x35d7, 0x2e + .dw 0x35d8, 0x35de, 0x21 + .dw 0x35df, 0x35df, 0x2e + .dw 0x35e0, 0x35e6, 0x21 + .dw 0x35e7, 0x35e7, 0x2e + .dw 0x35e8, 0x35ee, 0x21 + .dw 0x35ef, 0x35ef, 0x2e + .dw 0x35f0, 0x35f6, 0x21 + .dw 0x35f7, 0x35f7, 0x2e + .dw 0x35f8, 0x35fe, 0x21 + .dw 0x35ff, 0x35ff, 0x2e + .dw 0x3704, 0x3707, 0x21 + .dw 0x370c, 0x370f, 0x21 + .dw 0x3714, 0x3717, 0x21 + .dw 0x371c, 0x371f, 0x21 + .dw 0x3724, 0x3727, 0x21 + .dw 0x372c, 0x372f, 0x21 + .dw 0x3734, 0x3737, 0x21 + .dw 0x373c, 0x37c6, 0x21 + .dw 0x37c7, 0x37c7, 0x2e + .dw 0x37c8, 0x37ce, 0x21 + .dw 0x37cf, 0x37cf, 0x2e + .dw 0x37d0, 0x37d6, 0x21 + .dw 0x37d7, 0x37d7, 0x2e + .dw 0x37d8, 0x37de, 0x21 + .dw 0x37df, 0x37df, 0x2e + .dw 0x37e0, 0x37e6, 0x21 + .dw 0x37e7, 0x37e7, 0x2e + .dw 0x37e8, 0x37ee, 0x21 + .dw 0x37ef, 0x37ef, 0x2e + .dw 0x37f0, 0x37f6, 0x21 + .dw 0x37f7, 0x37f7, 0x2e + .dw 0x37f8, 0x37fe, 0x21 + .dw 0x37ff, 0x37ff, 0x2e + .dw 0x3820, 0x382f, 0x21 + .dw 0x3860, 0x386f, 0x21 + .dw 0x38a0, 0x38af, 0x21 + .dw 0x38b0, 0x38bf, 0x21 + .dw 0x38e0, 0x38ef, 0x21 + .dw 0x38f0, 0x38ff, 0x21 + .dw 0x3904, 0x3907, 0x21 + .dw 0x390c, 0x390f, 0x21 + .dw 0x3914, 0x3917, 0x21 + .dw 0x391c, 0x392f, 0x21 + .dw 0x3934, 0x3937, 0x21 + .dw 0x393c, 0x39bf, 0x21 + .dw 0x397f, 0x397f, 0x2e + .dw 0x3980, 0x39bf, 0x21 + .dw 0x39c0, 0x39c0, 0x2e + .dw 0x39c1, 0x39c7, 0x21 + .dw 0x39c8, 0x39c8, 0x2e + .dw 0x39c9, 0x39cf, 0x21 + .dw 0x39d0, 0x39d0, 0x2e + .dw 0x39d1, 0x39d7, 0x21 + .dw 0x39d8, 0x39d8, 0x2e + .dw 0x39d9, 0x39ef, 0x21 + .dw 0x39f0, 0x39f0, 0x2e + .dw 0x39f1, 0x39f6, 0x21 + .dw 0x39f7, 0x39f8, 0x2e + .dw 0x39f9, 0x39fe, 0x21 + .dw 0x39ff, 0x39ff, 0x2e + .dw 0x3a00, 0x3bff, 0x21 + .dw 0x3c80, 0x3cff, 0x21 + .dw 0x3d04, 0x3d07, 0x21 + .dw 0x3d0c, 0x3d0f, 0x21 + .dw 0x3d14, 0x3d17, 0x21 + .dw 0x3d1c, 0x3d1f, 0x21 + .dw 0x3d24, 0x3d27, 0x21 + .dw 0x3d2c, 0x3d2f, 0x21 + .dw 0x3d34, 0x3d37, 0x21 + .dw 0x3d3c, 0x3dbf, 0X21 + .dw 0x3dc0, 0x3dc0, 0x2e + .dw 0x3dc1, 0x3dc6, 0x21 + .dw 0x3dc7, 0x3dc8, 0x2e + .dw 0x3dc9, 0x3dce, 0x21 + .dw 0x3dcf, 0x3dd0, 0x2e + .dw 0x3dd1, 0x3dd6, 0x21 + .dw 0x3dd7, 0x3dd8, 0x2e + .dw 0x3dd9, 0x3dde, 0x21 + .dw 0x3ddf, 0x3de0, 0x2e + .dw 0x3de1, 0x3de6, 0x21 + .dw 0x3de7, 0x3de8, 0x2e + .dw 0x3de9, 0x3dee, 0x21 + .dw 0x3def, 0x3df0, 0x2e + .dw 0x3df1, 0x3df6, 0x21 + .dw 0x3df7, 0x3df8, 0x2e + .dw 0x3df9, 0x3dfe, 0x21 + .dw 0x3dff, 0x3e7f, 0x2e + .dw 0x3e80, 0x3eb7, 0x21 + .dw 0x3eb8, 0x3ebf, 0x2e + .dw 0x3ec0, 0x3ef7, 0x21 + .dw 0x3ef8, 0x3f03, 0x2e + .dw 0x3f04, 0x3f07, 0x21 + .dw 0x3f08, 0x3f0b, 0x2e + .dw 0x3f0c, 0x3f0f, 0x21 + .dw 0x3f10, 0x3f13, 0x2e + .dw 0x3f14, 0x3f17, 0x21 + .dw 0x3f18, 0x3f1b, 0x2e + .dw 0x3f1c, 0x3f1f, 0x21 + .dw 0x3f20, 0x3f23, 0x2e + .dw 0x3f24, 0x3f27, 0x21 + .dw 0x3f28, 0x3f2b, 0x2e + .dw 0x3f2c, 0x3f2f, 0x21 + .dw 0x3f30, 0x3f33, 0x2e + .dw 0x3f34, 0x3f37, 0x21 + .dw 0x3f38, 0x3f3b, 0x2e + .dw 0x3f3c, 0x3f3d, 0x21 + .dw 0x3f3e, 0x3f3f, 0x2e + .dw 0x3f40, 0x3fb7, 0x21 + .dw 0x3fb8, 0x3fc0, 0x2e + .dw 0x3fc1, 0x3fc6, 0x21 + .dw 0x3fc7, 0x3fc8, 0x2e + .dw 0x3fc9, 0x3fce, 0x21 + .dw 0x3fcf, 0x3fd0, 0x2e + .dw 0x3fd1, 0x3fd6, 0x21 + .dw 0x3fd7, 0x3fd8, 0x2e + .dw 0x3fd9, 0x3fde, 0x21 + .dw 0x3fdf, 0x3fe0, 0x2e + .dw 0x3fe1, 0x3fe6, 0x21 + .dw 0x3fe7, 0x3fe8, 0x2e + .dw 0x3fe9, 0x3fee, 0x21 + .dw 0x3fef, 0x3ff0, 0x2e + .dw 0x3ff1, 0x3ff6, 0x21 + .dw 0x3ff7, 0x3fff, 0x2e + .dw 0x4180, 0x41FF, 0x21 + .dw 0x4480, 0x44bF, 0x21 + .dw 0x4600, 0x47FF, 0x21 + .dw 0x7000, 0x7FFF, 0x21 + .dw 0x9040, 0x9040, 0x22 + .dw 0x9049, 0x9049, 0x22 + .dw 0x9052, 0x9052, 0x22 + .dw 0x905b, 0x905b, 0x22 + .dw 0x9064, 0x9064, 0x22 + .dw 0x906d, 0x906d, 0x22 + .dw 0x9076, 0x9076, 0x22 + .dw 0x907f, 0x907f, 0x22 + .dw 0x90c0, 0x90c0, 0x22 + .dw 0x90c9, 0x90c9, 0x22 + .dw 0x90d2, 0x90d2, 0x22 + .dw 0x90db, 0x90db, 0x22 + .dw 0x90e4, 0x90e4, 0x22 + .dw 0x90ed, 0x90ed, 0x22 + .dw 0x90f6, 0x90f6, 0x22 + .dw 0x90ff, 0x90ff, 0x22 + .dw 0x9180, 0x91ff, 0x21 + .dw 0x9380, 0x93ff, 0x21 + .dw 0x9580, 0x95ff, 0x21 + .dw 0x9640, 0x967f, 0x21 + .dw 0x96c0, 0x96ff, 0x21 + .dw 0x9740, 0x97ff, 0x21 + .dw 0x9980, 0x99ff, 0x21 + .dw 0x9a40, 0x9a7f, 0x21 + .dw 0x9ac0, 0x9aff, 0x21 + .dw 0x9b40, 0x9bff, 0x21 + .dw 0x9c60, 0x9c7f, 0x21 + .dw 0x9ce0, 0x9cff, 0x21 + .dw 0x9d60, 0x9d7f, 0x21 + .dw 0x9ef0, 0x9eff, 0x21 + .dw 0x9f70, 0x9f7f, 0x21 + .dw 0x0000, 0x0000, 0x00 +.endm + + se_all_test diff --git a/sim/testsuite/bfin/se_all32bitopcodes.S b/sim/testsuite/bfin/se_all32bitopcodes.S new file mode 100644 index 0000000..6ffe6d1 --- /dev/null +++ b/sim/testsuite/bfin/se_all32bitopcodes.S @@ -0,0 +1,34184 @@ +/* + * Blackfin testcase for testing illegal/legal 32-bit opcodes from userspace + * we track all instructions which cause some sort of exception when run from + * userspace, this is normally EXCAUSE : + * - 0x21 : illegal instruction + * - 0x22 : illegal instruction combination + * - 0x2e : use of supervisor resource from userspace + * and walk every instruction from 0x00000000 to 0xffffffff (and have 0xc000 set) + */ + +# Don't want to enable for normal `make check` as it takes way too long in +# the sim -- executes over 3 billion insns, and even at 10 MIPS, that's 10+ +# minutes. Useful for directed testing, but that's about it. +# mach: none +# sim: --environment operating +# xfail: too many invalid insns are decoded as valid + +#include "test.h" + +#define SE_ALL_BITS 32 +#include "se_allopcodes.h" + .include "testutils.inc" + +.macro se_all_load_insn + R2 = [P5]; + R0 = R2 << 16; + R1 = R2 >> 16; + R0 = R0 | R1; +.endm + +.macro se_all_next_insn + /* increment, and go again. */ + R0 = R2; + + /* Is this the last insn we'll execute ? */ + imm32 R1, 0xfffff7ff; + CC = R1 == R0; + IF CC JUMP pass_lvl; + + /* cut across the opcode space in an efficient manner: + * increment the high 16bits first since the low 16bits encode + * the type of insn ... */ + imm32 R1, 0x10000; + R0 = R1 + R0; + CC = R1 < R0 (IU); + IF CC jump 1f (bp); + + R0 += 1; + /* skip any 16bit insn chunks */ + R1 = R0; + R1.L = 0xC000; + CC = R0 < R1 (IU); + IF CC R0 = R1; +1: + + /* skip parallel insns */ + R1 = R0; + R1.L = 0xe800; /* allow linkage insns */ + CC = R0 == R1; + IF CC jump 1f; + CC = BITTST (R0, 11); + IF !CC jump 1f (bp); + R1 = 0x800; + R0 = R0 + R1; +1: + +.ifndef BFIN_JTAG + /* Skip debug insns when running in the sim. */ + R1.L = 0xff00; + R1.H = 0x0000; + R2 = R0 & R1; + R1.L = 0xf000; + CC = R1 == R2; + IF !CC jump 1f (bp); + R0.L = 0xf100; + R0.H = 0x0000; +1: +.endif + + [P5] = R0; +.endm + +.macro se_all_insn_init + .dw 0xc000; + .dw 0x0000; +.endm +.macro se_all_insn_table + /* this table must be sorted, and end with zero */ + /* start end SEQSTAT */ + .dw 0x1a00, 0xc000, 0x1fff, 0xc000, 0x21, 0 + .dw 0x3a00, 0xc000, 0x3fff, 0xc000, 0x21, 0 + .dw 0x5a00, 0xc000, 0x5fff, 0xc000, 0x21, 0 + .dw 0x7a00, 0xc000, 0x7fff, 0xc000, 0x21, 0 + .dw 0x9a00, 0xc000, 0x9fff, 0xc000, 0x21, 0 + .dw 0xba00, 0xc000, 0xbfff, 0xc000, 0x21, 0 + .dw 0xda00, 0xc000, 0xdfff, 0xc000, 0x21, 0 + .dw 0xfa00, 0xc000, 0xffff, 0xc000, 0x21, 0 + .dw 0x1a00, 0xc001, 0x1fff, 0xc001, 0x21, 0 + .dw 0x3a00, 0xc001, 0x3fff, 0xc001, 0x21, 0 + .dw 0x5a00, 0xc001, 0x5fff, 0xc001, 0x21, 0 + .dw 0x7a00, 0xc001, 0x7fff, 0xc001, 0x21, 0 + .dw 0x9a00, 0xc001, 0x9fff, 0xc001, 0x21, 0 + .dw 0xba00, 0xc001, 0xbfff, 0xc001, 0x21, 0 + .dw 0xda00, 0xc001, 0xdfff, 0xc001, 0x21, 0 + .dw 0xfa00, 0xc001, 0xffff, 0xc001, 0x21, 0 + .dw 0x1a00, 0xc002, 0x1fff, 0xc002, 0x21, 0 + .dw 0x3a00, 0xc002, 0x3fff, 0xc002, 0x21, 0 + .dw 0x5a00, 0xc002, 0x5fff, 0xc002, 0x21, 0 + .dw 0x7a00, 0xc002, 0x7fff, 0xc002, 0x21, 0 + .dw 0x9a00, 0xc002, 0x9fff, 0xc002, 0x21, 0 + .dw 0xba00, 0xc002, 0xbfff, 0xc002, 0x21, 0 + .dw 0xda00, 0xc002, 0xdfff, 0xc002, 0x21, 0 + .dw 0xfa00, 0xc002, 0xffff, 0xc002, 0x21, 0 + .dw 0x1a00, 0xc003, 0x1fff, 0xc003, 0x21, 0 + .dw 0x3a00, 0xc003, 0xffff, 0xc003, 0x21, 0 + .dw 0x1a00, 0xc004, 0x1fff, 0xc004, 0x21, 0 + .dw 0x3a00, 0xc004, 0x3fff, 0xc004, 0x21, 0 + .dw 0x5a00, 0xc004, 0x5fff, 0xc004, 0x21, 0 + .dw 0x7a00, 0xc004, 0x7fff, 0xc004, 0x21, 0 + .dw 0x9a00, 0xc004, 0x9fff, 0xc004, 0x21, 0 + .dw 0xba00, 0xc004, 0xbfff, 0xc004, 0x21, 0 + .dw 0xda00, 0xc004, 0xdfff, 0xc004, 0x21, 0 + .dw 0xfa00, 0xc004, 0xffff, 0xc004, 0x21, 0 + .dw 0x1a00, 0xc005, 0x1fff, 0xc005, 0x21, 0 + .dw 0x3a00, 0xc005, 0x3fff, 0xc005, 0x21, 0 + .dw 0x5a00, 0xc005, 0x5fff, 0xc005, 0x21, 0 + .dw 0x7a00, 0xc005, 0x7fff, 0xc005, 0x21, 0 + .dw 0x9a00, 0xc005, 0x9fff, 0xc005, 0x21, 0 + .dw 0xba00, 0xc005, 0xbfff, 0xc005, 0x21, 0 + .dw 0xda00, 0xc005, 0xdfff, 0xc005, 0x21, 0 + .dw 0xfa00, 0xc005, 0xffff, 0xc005, 0x21, 0 + .dw 0x1a00, 0xc006, 0x1fff, 0xc006, 0x21, 0 + .dw 0x3a00, 0xc006, 0x3fff, 0xc006, 0x21, 0 + .dw 0x5a00, 0xc006, 0x5fff, 0xc006, 0x21, 0 + .dw 0x7a00, 0xc006, 0x7fff, 0xc006, 0x21, 0 + .dw 0x9a00, 0xc006, 0x9fff, 0xc006, 0x21, 0 + .dw 0xba00, 0xc006, 0xbfff, 0xc006, 0x21, 0 + .dw 0xda00, 0xc006, 0xdfff, 0xc006, 0x21, 0 + .dw 0xfa00, 0xc006, 0xffff, 0xc006, 0x21, 0 + .dw 0x1a00, 0xc007, 0x1fff, 0xc007, 0x21, 0 + .dw 0x3a00, 0xc007, 0x1fff, 0xc008, 0x21, 0 + .dw 0x2040, 0xc008, 0x207f, 0xc008, 0x21, 0 + .dw 0x20c0, 0xc008, 0x20ff, 0xc008, 0x21, 0 + .dw 0x2140, 0xc008, 0x217f, 0xc008, 0x21, 0 + .dw 0x21c0, 0xc008, 0x21ff, 0xc008, 0x21, 0 + .dw 0x2240, 0xc008, 0x227f, 0xc008, 0x21, 0 + .dw 0x22c0, 0xc008, 0x22ff, 0xc008, 0x21, 0 + .dw 0x2340, 0xc008, 0x237f, 0xc008, 0x21, 0 + .dw 0x23c0, 0xc008, 0x23ff, 0xc008, 0x21, 0 + .dw 0x2440, 0xc008, 0x247f, 0xc008, 0x21, 0 + .dw 0x24c0, 0xc008, 0x24ff, 0xc008, 0x21, 0 + .dw 0x2540, 0xc008, 0x257f, 0xc008, 0x21, 0 + .dw 0x25c0, 0xc008, 0x25ff, 0xc008, 0x21, 0 + .dw 0x2640, 0xc008, 0x267f, 0xc008, 0x21, 0 + .dw 0x26c0, 0xc008, 0x26ff, 0xc008, 0x21, 0 + .dw 0x2740, 0xc008, 0x277f, 0xc008, 0x21, 0 + .dw 0x27c0, 0xc008, 0x27ff, 0xc008, 0x21, 0 + .dw 0x2840, 0xc008, 0x287f, 0xc008, 0x21, 0 + .dw 0x28c0, 0xc008, 0x28ff, 0xc008, 0x21, 0 + .dw 0x2940, 0xc008, 0x297f, 0xc008, 0x21, 0 + .dw 0x29c0, 0xc008, 0x29ff, 0xc008, 0x21, 0 + .dw 0x2a40, 0xc008, 0x2a7f, 0xc008, 0x21, 0 + .dw 0x2ac0, 0xc008, 0x2aff, 0xc008, 0x21, 0 + .dw 0x2b40, 0xc008, 0x2b7f, 0xc008, 0x21, 0 + .dw 0x2bc0, 0xc008, 0x2bff, 0xc008, 0x21, 0 + .dw 0x2c40, 0xc008, 0x2c7f, 0xc008, 0x21, 0 + .dw 0x2cc0, 0xc008, 0x2cff, 0xc008, 0x21, 0 + .dw 0x2d40, 0xc008, 0x2d7f, 0xc008, 0x21, 0 + .dw 0x2dc0, 0xc008, 0x2dff, 0xc008, 0x21, 0 + .dw 0x2e40, 0xc008, 0x2e7f, 0xc008, 0x21, 0 + .dw 0x2ec0, 0xc008, 0x2eff, 0xc008, 0x21, 0 + .dw 0x2f40, 0xc008, 0x2f7f, 0xc008, 0x21, 0 + .dw 0x2fc0, 0xc008, 0x2fff, 0xc008, 0x21, 0 + .dw 0x3040, 0xc008, 0x307f, 0xc008, 0x21, 0 + .dw 0x30c0, 0xc008, 0x30ff, 0xc008, 0x21, 0 + .dw 0x3140, 0xc008, 0x317f, 0xc008, 0x21, 0 + .dw 0x31c0, 0xc008, 0x31ff, 0xc008, 0x21, 0 + .dw 0x3240, 0xc008, 0x327f, 0xc008, 0x21, 0 + .dw 0x32c0, 0xc008, 0x32ff, 0xc008, 0x21, 0 + .dw 0x3340, 0xc008, 0x337f, 0xc008, 0x21, 0 + .dw 0x33c0, 0xc008, 0x33ff, 0xc008, 0x21, 0 + .dw 0x3440, 0xc008, 0x347f, 0xc008, 0x21, 0 + .dw 0x34c0, 0xc008, 0x34ff, 0xc008, 0x21, 0 + .dw 0x3540, 0xc008, 0x357f, 0xc008, 0x21, 0 + .dw 0x35c0, 0xc008, 0x35ff, 0xc008, 0x21, 0 + .dw 0x3640, 0xc008, 0x367f, 0xc008, 0x21, 0 + .dw 0x36c0, 0xc008, 0x36ff, 0xc008, 0x21, 0 + .dw 0x3740, 0xc008, 0x377f, 0xc008, 0x21, 0 + .dw 0x37c0, 0xc008, 0x37ff, 0xc008, 0x21, 0 + .dw 0x3840, 0xc008, 0x387f, 0xc008, 0x21, 0 + .dw 0x38c0, 0xc008, 0x38ff, 0xc008, 0x21, 0 + .dw 0x3940, 0xc008, 0x397f, 0xc008, 0x21, 0 + .dw 0x39c0, 0xc008, 0x5fff, 0xc008, 0x21, 0 + .dw 0x6040, 0xc008, 0x607f, 0xc008, 0x21, 0 + .dw 0x60c0, 0xc008, 0x60ff, 0xc008, 0x21, 0 + .dw 0x6140, 0xc008, 0x617f, 0xc008, 0x21, 0 + .dw 0x61c0, 0xc008, 0x61ff, 0xc008, 0x21, 0 + .dw 0x6240, 0xc008, 0x627f, 0xc008, 0x21, 0 + .dw 0x62c0, 0xc008, 0x62ff, 0xc008, 0x21, 0 + .dw 0x6340, 0xc008, 0x637f, 0xc008, 0x21, 0 + .dw 0x63c0, 0xc008, 0x63ff, 0xc008, 0x21, 0 + .dw 0x6440, 0xc008, 0x647f, 0xc008, 0x21, 0 + .dw 0x64c0, 0xc008, 0x64ff, 0xc008, 0x21, 0 + .dw 0x6540, 0xc008, 0x657f, 0xc008, 0x21, 0 + .dw 0x65c0, 0xc008, 0x65ff, 0xc008, 0x21, 0 + .dw 0x6640, 0xc008, 0x667f, 0xc008, 0x21, 0 + .dw 0x66c0, 0xc008, 0x66ff, 0xc008, 0x21, 0 + .dw 0x6740, 0xc008, 0x677f, 0xc008, 0x21, 0 + .dw 0x67c0, 0xc008, 0x67ff, 0xc008, 0x21, 0 + .dw 0x6840, 0xc008, 0x687f, 0xc008, 0x21, 0 + .dw 0x68c0, 0xc008, 0x68ff, 0xc008, 0x21, 0 + .dw 0x6940, 0xc008, 0x697f, 0xc008, 0x21, 0 + .dw 0x69c0, 0xc008, 0x69ff, 0xc008, 0x21, 0 + .dw 0x6a40, 0xc008, 0x6a7f, 0xc008, 0x21, 0 + .dw 0x6ac0, 0xc008, 0x6aff, 0xc008, 0x21, 0 + .dw 0x6b40, 0xc008, 0x6b7f, 0xc008, 0x21, 0 + .dw 0x6bc0, 0xc008, 0x6bff, 0xc008, 0x21, 0 + .dw 0x6c40, 0xc008, 0x6c7f, 0xc008, 0x21, 0 + .dw 0x6cc0, 0xc008, 0x6cff, 0xc008, 0x21, 0 + .dw 0x6d40, 0xc008, 0x6d7f, 0xc008, 0x21, 0 + .dw 0x6dc0, 0xc008, 0x6dff, 0xc008, 0x21, 0 + .dw 0x6e40, 0xc008, 0x6e7f, 0xc008, 0x21, 0 + .dw 0x6ec0, 0xc008, 0x6eff, 0xc008, 0x21, 0 + .dw 0x6f40, 0xc008, 0x6f7f, 0xc008, 0x21, 0 + .dw 0x6fc0, 0xc008, 0x6fff, 0xc008, 0x21, 0 + .dw 0x7040, 0xc008, 0x707f, 0xc008, 0x21, 0 + .dw 0x70c0, 0xc008, 0x70ff, 0xc008, 0x21, 0 + .dw 0x7140, 0xc008, 0x717f, 0xc008, 0x21, 0 + .dw 0x71c0, 0xc008, 0x71ff, 0xc008, 0x21, 0 + .dw 0x7240, 0xc008, 0x727f, 0xc008, 0x21, 0 + .dw 0x72c0, 0xc008, 0x72ff, 0xc008, 0x21, 0 + .dw 0x7340, 0xc008, 0x737f, 0xc008, 0x21, 0 + .dw 0x73c0, 0xc008, 0x73ff, 0xc008, 0x21, 0 + .dw 0x7440, 0xc008, 0x747f, 0xc008, 0x21, 0 + .dw 0x74c0, 0xc008, 0x74ff, 0xc008, 0x21, 0 + .dw 0x7540, 0xc008, 0x757f, 0xc008, 0x21, 0 + .dw 0x75c0, 0xc008, 0x75ff, 0xc008, 0x21, 0 + .dw 0x7640, 0xc008, 0x767f, 0xc008, 0x21, 0 + .dw 0x76c0, 0xc008, 0x76ff, 0xc008, 0x21, 0 + .dw 0x7740, 0xc008, 0x777f, 0xc008, 0x21, 0 + .dw 0x77c0, 0xc008, 0x77ff, 0xc008, 0x21, 0 + .dw 0x7840, 0xc008, 0x787f, 0xc008, 0x21, 0 + .dw 0x78c0, 0xc008, 0x78ff, 0xc008, 0x21, 0 + .dw 0x7940, 0xc008, 0x797f, 0xc008, 0x21, 0 + .dw 0x79c0, 0xc008, 0x9fff, 0xc008, 0x21, 0 + .dw 0xa040, 0xc008, 0xa07f, 0xc008, 0x21, 0 + .dw 0xa0c0, 0xc008, 0xa0ff, 0xc008, 0x21, 0 + .dw 0xa140, 0xc008, 0xa17f, 0xc008, 0x21, 0 + .dw 0xa1c0, 0xc008, 0xa1ff, 0xc008, 0x21, 0 + .dw 0xa240, 0xc008, 0xa27f, 0xc008, 0x21, 0 + .dw 0xa2c0, 0xc008, 0xa2ff, 0xc008, 0x21, 0 + .dw 0xa340, 0xc008, 0xa37f, 0xc008, 0x21, 0 + .dw 0xa3c0, 0xc008, 0xa3ff, 0xc008, 0x21, 0 + .dw 0xa440, 0xc008, 0xa47f, 0xc008, 0x21, 0 + .dw 0xa4c0, 0xc008, 0xa4ff, 0xc008, 0x21, 0 + .dw 0xa540, 0xc008, 0xa57f, 0xc008, 0x21, 0 + .dw 0xa5c0, 0xc008, 0xa5ff, 0xc008, 0x21, 0 + .dw 0xa640, 0xc008, 0xa67f, 0xc008, 0x21, 0 + .dw 0xa6c0, 0xc008, 0xa6ff, 0xc008, 0x21, 0 + .dw 0xa740, 0xc008, 0xa77f, 0xc008, 0x21, 0 + .dw 0xa7c0, 0xc008, 0xa7ff, 0xc008, 0x21, 0 + .dw 0xa840, 0xc008, 0xa87f, 0xc008, 0x21, 0 + .dw 0xa8c0, 0xc008, 0xa8ff, 0xc008, 0x21, 0 + .dw 0xa940, 0xc008, 0xa97f, 0xc008, 0x21, 0 + .dw 0xa9c0, 0xc008, 0xa9ff, 0xc008, 0x21, 0 + .dw 0xaa40, 0xc008, 0xaa7f, 0xc008, 0x21, 0 + .dw 0xaac0, 0xc008, 0xaaff, 0xc008, 0x21, 0 + .dw 0xab40, 0xc008, 0xab7f, 0xc008, 0x21, 0 + .dw 0xabc0, 0xc008, 0xabff, 0xc008, 0x21, 0 + .dw 0xac40, 0xc008, 0xac7f, 0xc008, 0x21, 0 + .dw 0xacc0, 0xc008, 0xacff, 0xc008, 0x21, 0 + .dw 0xad40, 0xc008, 0xad7f, 0xc008, 0x21, 0 + .dw 0xadc0, 0xc008, 0xadff, 0xc008, 0x21, 0 + .dw 0xae40, 0xc008, 0xae7f, 0xc008, 0x21, 0 + .dw 0xaec0, 0xc008, 0xaeff, 0xc008, 0x21, 0 + .dw 0xaf40, 0xc008, 0xaf7f, 0xc008, 0x21, 0 + .dw 0xafc0, 0xc008, 0xafff, 0xc008, 0x21, 0 + .dw 0xb040, 0xc008, 0xb07f, 0xc008, 0x21, 0 + .dw 0xb0c0, 0xc008, 0xb0ff, 0xc008, 0x21, 0 + .dw 0xb140, 0xc008, 0xb17f, 0xc008, 0x21, 0 + .dw 0xb1c0, 0xc008, 0xb1ff, 0xc008, 0x21, 0 + .dw 0xb240, 0xc008, 0xb27f, 0xc008, 0x21, 0 + .dw 0xb2c0, 0xc008, 0xb2ff, 0xc008, 0x21, 0 + .dw 0xb340, 0xc008, 0xb37f, 0xc008, 0x21, 0 + .dw 0xb3c0, 0xc008, 0xb3ff, 0xc008, 0x21, 0 + .dw 0xb440, 0xc008, 0xb47f, 0xc008, 0x21, 0 + .dw 0xb4c0, 0xc008, 0xb4ff, 0xc008, 0x21, 0 + .dw 0xb540, 0xc008, 0xb57f, 0xc008, 0x21, 0 + .dw 0xb5c0, 0xc008, 0xb5ff, 0xc008, 0x21, 0 + .dw 0xb640, 0xc008, 0xb67f, 0xc008, 0x21, 0 + .dw 0xb6c0, 0xc008, 0xb6ff, 0xc008, 0x21, 0 + .dw 0xb740, 0xc008, 0xb77f, 0xc008, 0x21, 0 + .dw 0xb7c0, 0xc008, 0xb7ff, 0xc008, 0x21, 0 + .dw 0xb840, 0xc008, 0xb87f, 0xc008, 0x21, 0 + .dw 0xb8c0, 0xc008, 0xb8ff, 0xc008, 0x21, 0 + .dw 0xb940, 0xc008, 0xb97f, 0xc008, 0x21, 0 + .dw 0xb9c0, 0xc008, 0xdfff, 0xc008, 0x21, 0 + .dw 0xe040, 0xc008, 0xe07f, 0xc008, 0x21, 0 + .dw 0xe0c0, 0xc008, 0xe0ff, 0xc008, 0x21, 0 + .dw 0xe140, 0xc008, 0xe17f, 0xc008, 0x21, 0 + .dw 0xe1c0, 0xc008, 0xe1ff, 0xc008, 0x21, 0 + .dw 0xe240, 0xc008, 0xe27f, 0xc008, 0x21, 0 + .dw 0xe2c0, 0xc008, 0xe2ff, 0xc008, 0x21, 0 + .dw 0xe340, 0xc008, 0xe37f, 0xc008, 0x21, 0 + .dw 0xe3c0, 0xc008, 0xe3ff, 0xc008, 0x21, 0 + .dw 0xe440, 0xc008, 0xe47f, 0xc008, 0x21, 0 + .dw 0xe4c0, 0xc008, 0xe4ff, 0xc008, 0x21, 0 + .dw 0xe540, 0xc008, 0xe57f, 0xc008, 0x21, 0 + .dw 0xe5c0, 0xc008, 0xe5ff, 0xc008, 0x21, 0 + .dw 0xe640, 0xc008, 0xe67f, 0xc008, 0x21, 0 + .dw 0xe6c0, 0xc008, 0xe6ff, 0xc008, 0x21, 0 + .dw 0xe740, 0xc008, 0xe77f, 0xc008, 0x21, 0 + .dw 0xe7c0, 0xc008, 0xe7ff, 0xc008, 0x21, 0 + .dw 0xe840, 0xc008, 0xe87f, 0xc008, 0x21, 0 + .dw 0xe8c0, 0xc008, 0xe8ff, 0xc008, 0x21, 0 + .dw 0xe940, 0xc008, 0xe97f, 0xc008, 0x21, 0 + .dw 0xe9c0, 0xc008, 0xe9ff, 0xc008, 0x21, 0 + .dw 0xea40, 0xc008, 0xea7f, 0xc008, 0x21, 0 + .dw 0xeac0, 0xc008, 0xeaff, 0xc008, 0x21, 0 + .dw 0xeb40, 0xc008, 0xeb7f, 0xc008, 0x21, 0 + .dw 0xebc0, 0xc008, 0xebff, 0xc008, 0x21, 0 + .dw 0xec40, 0xc008, 0xec7f, 0xc008, 0x21, 0 + .dw 0xecc0, 0xc008, 0xecff, 0xc008, 0x21, 0 + .dw 0xed40, 0xc008, 0xed7f, 0xc008, 0x21, 0 + .dw 0xedc0, 0xc008, 0xedff, 0xc008, 0x21, 0 + .dw 0xee40, 0xc008, 0xee7f, 0xc008, 0x21, 0 + .dw 0xeec0, 0xc008, 0xeeff, 0xc008, 0x21, 0 + .dw 0xef40, 0xc008, 0xef7f, 0xc008, 0x21, 0 + .dw 0xefc0, 0xc008, 0xefff, 0xc008, 0x21, 0 + .dw 0xf040, 0xc008, 0xf07f, 0xc008, 0x21, 0 + .dw 0xf0c0, 0xc008, 0xf0ff, 0xc008, 0x21, 0 + .dw 0xf140, 0xc008, 0xf17f, 0xc008, 0x21, 0 + .dw 0xf1c0, 0xc008, 0xf1ff, 0xc008, 0x21, 0 + .dw 0xf240, 0xc008, 0xf27f, 0xc008, 0x21, 0 + .dw 0xf2c0, 0xc008, 0xf2ff, 0xc008, 0x21, 0 + .dw 0xf340, 0xc008, 0xf37f, 0xc008, 0x21, 0 + .dw 0xf3c0, 0xc008, 0xf3ff, 0xc008, 0x21, 0 + .dw 0xf440, 0xc008, 0xf47f, 0xc008, 0x21, 0 + .dw 0xf4c0, 0xc008, 0xf4ff, 0xc008, 0x21, 0 + .dw 0xf540, 0xc008, 0xf57f, 0xc008, 0x21, 0 + .dw 0xf5c0, 0xc008, 0xf5ff, 0xc008, 0x21, 0 + .dw 0xf640, 0xc008, 0xf67f, 0xc008, 0x21, 0 + .dw 0xf6c0, 0xc008, 0xf6ff, 0xc008, 0x21, 0 + .dw 0xf740, 0xc008, 0xf77f, 0xc008, 0x21, 0 + .dw 0xf7c0, 0xc008, 0xf7ff, 0xc008, 0x21, 0 + .dw 0xf840, 0xc008, 0xf87f, 0xc008, 0x21, 0 + .dw 0xf8c0, 0xc008, 0xf8ff, 0xc008, 0x21, 0 + .dw 0xf940, 0xc008, 0xf97f, 0xc008, 0x21, 0 + .dw 0xf9c0, 0xc008, 0x1fff, 0xc009, 0x21, 0 + .dw 0x2040, 0xc009, 0x207f, 0xc009, 0x21, 0 + .dw 0x20c0, 0xc009, 0x20ff, 0xc009, 0x21, 0 + .dw 0x2140, 0xc009, 0x217f, 0xc009, 0x21, 0 + .dw 0x21c0, 0xc009, 0x21ff, 0xc009, 0x21, 0 + .dw 0x2240, 0xc009, 0x227f, 0xc009, 0x21, 0 + .dw 0x22c0, 0xc009, 0x22ff, 0xc009, 0x21, 0 + .dw 0x2340, 0xc009, 0x237f, 0xc009, 0x21, 0 + .dw 0x23c0, 0xc009, 0x23ff, 0xc009, 0x21, 0 + .dw 0x2440, 0xc009, 0x247f, 0xc009, 0x21, 0 + .dw 0x24c0, 0xc009, 0x24ff, 0xc009, 0x21, 0 + .dw 0x2540, 0xc009, 0x257f, 0xc009, 0x21, 0 + .dw 0x25c0, 0xc009, 0x25ff, 0xc009, 0x21, 0 + .dw 0x2640, 0xc009, 0x267f, 0xc009, 0x21, 0 + .dw 0x26c0, 0xc009, 0x26ff, 0xc009, 0x21, 0 + .dw 0x2740, 0xc009, 0x277f, 0xc009, 0x21, 0 + .dw 0x27c0, 0xc009, 0x27ff, 0xc009, 0x21, 0 + .dw 0x2840, 0xc009, 0x287f, 0xc009, 0x21, 0 + .dw 0x28c0, 0xc009, 0x28ff, 0xc009, 0x21, 0 + .dw 0x2940, 0xc009, 0x297f, 0xc009, 0x21, 0 + .dw 0x29c0, 0xc009, 0x29ff, 0xc009, 0x21, 0 + .dw 0x2a40, 0xc009, 0x2a7f, 0xc009, 0x21, 0 + .dw 0x2ac0, 0xc009, 0x2aff, 0xc009, 0x21, 0 + .dw 0x2b40, 0xc009, 0x2b7f, 0xc009, 0x21, 0 + .dw 0x2bc0, 0xc009, 0x2bff, 0xc009, 0x21, 0 + .dw 0x2c40, 0xc009, 0x2c7f, 0xc009, 0x21, 0 + .dw 0x2cc0, 0xc009, 0x2cff, 0xc009, 0x21, 0 + .dw 0x2d40, 0xc009, 0x2d7f, 0xc009, 0x21, 0 + .dw 0x2dc0, 0xc009, 0x2dff, 0xc009, 0x21, 0 + .dw 0x2e40, 0xc009, 0x2e7f, 0xc009, 0x21, 0 + .dw 0x2ec0, 0xc009, 0x2eff, 0xc009, 0x21, 0 + .dw 0x2f40, 0xc009, 0x2f7f, 0xc009, 0x21, 0 + .dw 0x2fc0, 0xc009, 0x2fff, 0xc009, 0x21, 0 + .dw 0x3040, 0xc009, 0x307f, 0xc009, 0x21, 0 + .dw 0x30c0, 0xc009, 0x30ff, 0xc009, 0x21, 0 + .dw 0x3140, 0xc009, 0x317f, 0xc009, 0x21, 0 + .dw 0x31c0, 0xc009, 0x31ff, 0xc009, 0x21, 0 + .dw 0x3240, 0xc009, 0x327f, 0xc009, 0x21, 0 + .dw 0x32c0, 0xc009, 0x32ff, 0xc009, 0x21, 0 + .dw 0x3340, 0xc009, 0x337f, 0xc009, 0x21, 0 + .dw 0x33c0, 0xc009, 0x33ff, 0xc009, 0x21, 0 + .dw 0x3440, 0xc009, 0x347f, 0xc009, 0x21, 0 + .dw 0x34c0, 0xc009, 0x34ff, 0xc009, 0x21, 0 + .dw 0x3540, 0xc009, 0x357f, 0xc009, 0x21, 0 + .dw 0x35c0, 0xc009, 0x35ff, 0xc009, 0x21, 0 + .dw 0x3640, 0xc009, 0x367f, 0xc009, 0x21, 0 + .dw 0x36c0, 0xc009, 0x36ff, 0xc009, 0x21, 0 + .dw 0x3740, 0xc009, 0x377f, 0xc009, 0x21, 0 + .dw 0x37c0, 0xc009, 0x37ff, 0xc009, 0x21, 0 + .dw 0x3840, 0xc009, 0x387f, 0xc009, 0x21, 0 + .dw 0x38c0, 0xc009, 0x38ff, 0xc009, 0x21, 0 + .dw 0x3940, 0xc009, 0x397f, 0xc009, 0x21, 0 + .dw 0x39c0, 0xc009, 0x5fff, 0xc009, 0x21, 0 + .dw 0x6040, 0xc009, 0x607f, 0xc009, 0x21, 0 + .dw 0x60c0, 0xc009, 0x60ff, 0xc009, 0x21, 0 + .dw 0x6140, 0xc009, 0x617f, 0xc009, 0x21, 0 + .dw 0x61c0, 0xc009, 0x61ff, 0xc009, 0x21, 0 + .dw 0x6240, 0xc009, 0x627f, 0xc009, 0x21, 0 + .dw 0x62c0, 0xc009, 0x62ff, 0xc009, 0x21, 0 + .dw 0x6340, 0xc009, 0x637f, 0xc009, 0x21, 0 + .dw 0x63c0, 0xc009, 0x63ff, 0xc009, 0x21, 0 + .dw 0x6440, 0xc009, 0x647f, 0xc009, 0x21, 0 + .dw 0x64c0, 0xc009, 0x64ff, 0xc009, 0x21, 0 + .dw 0x6540, 0xc009, 0x657f, 0xc009, 0x21, 0 + .dw 0x65c0, 0xc009, 0x65ff, 0xc009, 0x21, 0 + .dw 0x6640, 0xc009, 0x667f, 0xc009, 0x21, 0 + .dw 0x66c0, 0xc009, 0x66ff, 0xc009, 0x21, 0 + .dw 0x6740, 0xc009, 0x677f, 0xc009, 0x21, 0 + .dw 0x67c0, 0xc009, 0x67ff, 0xc009, 0x21, 0 + .dw 0x6840, 0xc009, 0x687f, 0xc009, 0x21, 0 + .dw 0x68c0, 0xc009, 0x68ff, 0xc009, 0x21, 0 + .dw 0x6940, 0xc009, 0x697f, 0xc009, 0x21, 0 + .dw 0x69c0, 0xc009, 0x69ff, 0xc009, 0x21, 0 + .dw 0x6a40, 0xc009, 0x6a7f, 0xc009, 0x21, 0 + .dw 0x6ac0, 0xc009, 0x6aff, 0xc009, 0x21, 0 + .dw 0x6b40, 0xc009, 0x6b7f, 0xc009, 0x21, 0 + .dw 0x6bc0, 0xc009, 0x6bff, 0xc009, 0x21, 0 + .dw 0x6c40, 0xc009, 0x6c7f, 0xc009, 0x21, 0 + .dw 0x6cc0, 0xc009, 0x6cff, 0xc009, 0x21, 0 + .dw 0x6d40, 0xc009, 0x6d7f, 0xc009, 0x21, 0 + .dw 0x6dc0, 0xc009, 0x6dff, 0xc009, 0x21, 0 + .dw 0x6e40, 0xc009, 0x6e7f, 0xc009, 0x21, 0 + .dw 0x6ec0, 0xc009, 0x6eff, 0xc009, 0x21, 0 + .dw 0x6f40, 0xc009, 0x6f7f, 0xc009, 0x21, 0 + .dw 0x6fc0, 0xc009, 0x6fff, 0xc009, 0x21, 0 + .dw 0x7040, 0xc009, 0x707f, 0xc009, 0x21, 0 + .dw 0x70c0, 0xc009, 0x70ff, 0xc009, 0x21, 0 + .dw 0x7140, 0xc009, 0x717f, 0xc009, 0x21, 0 + .dw 0x71c0, 0xc009, 0x71ff, 0xc009, 0x21, 0 + .dw 0x7240, 0xc009, 0x727f, 0xc009, 0x21, 0 + .dw 0x72c0, 0xc009, 0x72ff, 0xc009, 0x21, 0 + .dw 0x7340, 0xc009, 0x737f, 0xc009, 0x21, 0 + .dw 0x73c0, 0xc009, 0x73ff, 0xc009, 0x21, 0 + .dw 0x7440, 0xc009, 0x747f, 0xc009, 0x21, 0 + .dw 0x74c0, 0xc009, 0x74ff, 0xc009, 0x21, 0 + .dw 0x7540, 0xc009, 0x757f, 0xc009, 0x21, 0 + .dw 0x75c0, 0xc009, 0x75ff, 0xc009, 0x21, 0 + .dw 0x7640, 0xc009, 0x767f, 0xc009, 0x21, 0 + .dw 0x76c0, 0xc009, 0x76ff, 0xc009, 0x21, 0 + .dw 0x7740, 0xc009, 0x777f, 0xc009, 0x21, 0 + .dw 0x77c0, 0xc009, 0x77ff, 0xc009, 0x21, 0 + .dw 0x7840, 0xc009, 0x787f, 0xc009, 0x21, 0 + .dw 0x78c0, 0xc009, 0x78ff, 0xc009, 0x21, 0 + .dw 0x7940, 0xc009, 0x797f, 0xc009, 0x21, 0 + .dw 0x79c0, 0xc009, 0x9fff, 0xc009, 0x21, 0 + .dw 0xa040, 0xc009, 0xa07f, 0xc009, 0x21, 0 + .dw 0xa0c0, 0xc009, 0xa0ff, 0xc009, 0x21, 0 + .dw 0xa140, 0xc009, 0xa17f, 0xc009, 0x21, 0 + .dw 0xa1c0, 0xc009, 0xa1ff, 0xc009, 0x21, 0 + .dw 0xa240, 0xc009, 0xa27f, 0xc009, 0x21, 0 + .dw 0xa2c0, 0xc009, 0xa2ff, 0xc009, 0x21, 0 + .dw 0xa340, 0xc009, 0xa37f, 0xc009, 0x21, 0 + .dw 0xa3c0, 0xc009, 0xa3ff, 0xc009, 0x21, 0 + .dw 0xa440, 0xc009, 0xa47f, 0xc009, 0x21, 0 + .dw 0xa4c0, 0xc009, 0xa4ff, 0xc009, 0x21, 0 + .dw 0xa540, 0xc009, 0xa57f, 0xc009, 0x21, 0 + .dw 0xa5c0, 0xc009, 0xa5ff, 0xc009, 0x21, 0 + .dw 0xa640, 0xc009, 0xa67f, 0xc009, 0x21, 0 + .dw 0xa6c0, 0xc009, 0xa6ff, 0xc009, 0x21, 0 + .dw 0xa740, 0xc009, 0xa77f, 0xc009, 0x21, 0 + .dw 0xa7c0, 0xc009, 0xa7ff, 0xc009, 0x21, 0 + .dw 0xa840, 0xc009, 0xa87f, 0xc009, 0x21, 0 + .dw 0xa8c0, 0xc009, 0xa8ff, 0xc009, 0x21, 0 + .dw 0xa940, 0xc009, 0xa97f, 0xc009, 0x21, 0 + .dw 0xa9c0, 0xc009, 0xa9ff, 0xc009, 0x21, 0 + .dw 0xaa40, 0xc009, 0xaa7f, 0xc009, 0x21, 0 + .dw 0xaac0, 0xc009, 0xaaff, 0xc009, 0x21, 0 + .dw 0xab40, 0xc009, 0xab7f, 0xc009, 0x21, 0 + .dw 0xabc0, 0xc009, 0xabff, 0xc009, 0x21, 0 + .dw 0xac40, 0xc009, 0xac7f, 0xc009, 0x21, 0 + .dw 0xacc0, 0xc009, 0xacff, 0xc009, 0x21, 0 + .dw 0xad40, 0xc009, 0xad7f, 0xc009, 0x21, 0 + .dw 0xadc0, 0xc009, 0xadff, 0xc009, 0x21, 0 + .dw 0xae40, 0xc009, 0xae7f, 0xc009, 0x21, 0 + .dw 0xaec0, 0xc009, 0xaeff, 0xc009, 0x21, 0 + .dw 0xaf40, 0xc009, 0xaf7f, 0xc009, 0x21, 0 + .dw 0xafc0, 0xc009, 0xafff, 0xc009, 0x21, 0 + .dw 0xb040, 0xc009, 0xb07f, 0xc009, 0x21, 0 + .dw 0xb0c0, 0xc009, 0xb0ff, 0xc009, 0x21, 0 + .dw 0xb140, 0xc009, 0xb17f, 0xc009, 0x21, 0 + .dw 0xb1c0, 0xc009, 0xb1ff, 0xc009, 0x21, 0 + .dw 0xb240, 0xc009, 0xb27f, 0xc009, 0x21, 0 + .dw 0xb2c0, 0xc009, 0xb2ff, 0xc009, 0x21, 0 + .dw 0xb340, 0xc009, 0xb37f, 0xc009, 0x21, 0 + .dw 0xb3c0, 0xc009, 0xb3ff, 0xc009, 0x21, 0 + .dw 0xb440, 0xc009, 0xb47f, 0xc009, 0x21, 0 + .dw 0xb4c0, 0xc009, 0xb4ff, 0xc009, 0x21, 0 + .dw 0xb540, 0xc009, 0xb57f, 0xc009, 0x21, 0 + .dw 0xb5c0, 0xc009, 0xb5ff, 0xc009, 0x21, 0 + .dw 0xb640, 0xc009, 0xb67f, 0xc009, 0x21, 0 + .dw 0xb6c0, 0xc009, 0xb6ff, 0xc009, 0x21, 0 + .dw 0xb740, 0xc009, 0xb77f, 0xc009, 0x21, 0 + .dw 0xb7c0, 0xc009, 0xb7ff, 0xc009, 0x21, 0 + .dw 0xb840, 0xc009, 0xb87f, 0xc009, 0x21, 0 + .dw 0xb8c0, 0xc009, 0xb8ff, 0xc009, 0x21, 0 + .dw 0xb940, 0xc009, 0xb97f, 0xc009, 0x21, 0 + .dw 0xb9c0, 0xc009, 0xdfff, 0xc009, 0x21, 0 + .dw 0xe040, 0xc009, 0xe07f, 0xc009, 0x21, 0 + .dw 0xe0c0, 0xc009, 0xe0ff, 0xc009, 0x21, 0 + .dw 0xe140, 0xc009, 0xe17f, 0xc009, 0x21, 0 + .dw 0xe1c0, 0xc009, 0xe1ff, 0xc009, 0x21, 0 + .dw 0xe240, 0xc009, 0xe27f, 0xc009, 0x21, 0 + .dw 0xe2c0, 0xc009, 0xe2ff, 0xc009, 0x21, 0 + .dw 0xe340, 0xc009, 0xe37f, 0xc009, 0x21, 0 + .dw 0xe3c0, 0xc009, 0xe3ff, 0xc009, 0x21, 0 + .dw 0xe440, 0xc009, 0xe47f, 0xc009, 0x21, 0 + .dw 0xe4c0, 0xc009, 0xe4ff, 0xc009, 0x21, 0 + .dw 0xe540, 0xc009, 0xe57f, 0xc009, 0x21, 0 + .dw 0xe5c0, 0xc009, 0xe5ff, 0xc009, 0x21, 0 + .dw 0xe640, 0xc009, 0xe67f, 0xc009, 0x21, 0 + .dw 0xe6c0, 0xc009, 0xe6ff, 0xc009, 0x21, 0 + .dw 0xe740, 0xc009, 0xe77f, 0xc009, 0x21, 0 + .dw 0xe7c0, 0xc009, 0xe7ff, 0xc009, 0x21, 0 + .dw 0xe840, 0xc009, 0xe87f, 0xc009, 0x21, 0 + .dw 0xe8c0, 0xc009, 0xe8ff, 0xc009, 0x21, 0 + .dw 0xe940, 0xc009, 0xe97f, 0xc009, 0x21, 0 + .dw 0xe9c0, 0xc009, 0xe9ff, 0xc009, 0x21, 0 + .dw 0xea40, 0xc009, 0xea7f, 0xc009, 0x21, 0 + .dw 0xeac0, 0xc009, 0xeaff, 0xc009, 0x21, 0 + .dw 0xeb40, 0xc009, 0xeb7f, 0xc009, 0x21, 0 + .dw 0xebc0, 0xc009, 0xebff, 0xc009, 0x21, 0 + .dw 0xec40, 0xc009, 0xec7f, 0xc009, 0x21, 0 + .dw 0xecc0, 0xc009, 0xecff, 0xc009, 0x21, 0 + .dw 0xed40, 0xc009, 0xed7f, 0xc009, 0x21, 0 + .dw 0xedc0, 0xc009, 0xedff, 0xc009, 0x21, 0 + .dw 0xee40, 0xc009, 0xee7f, 0xc009, 0x21, 0 + .dw 0xeec0, 0xc009, 0xeeff, 0xc009, 0x21, 0 + .dw 0xef40, 0xc009, 0xef7f, 0xc009, 0x21, 0 + .dw 0xefc0, 0xc009, 0xefff, 0xc009, 0x21, 0 + .dw 0xf040, 0xc009, 0xf07f, 0xc009, 0x21, 0 + .dw 0xf0c0, 0xc009, 0xf0ff, 0xc009, 0x21, 0 + .dw 0xf140, 0xc009, 0xf17f, 0xc009, 0x21, 0 + .dw 0xf1c0, 0xc009, 0xf1ff, 0xc009, 0x21, 0 + .dw 0xf240, 0xc009, 0xf27f, 0xc009, 0x21, 0 + .dw 0xf2c0, 0xc009, 0xf2ff, 0xc009, 0x21, 0 + .dw 0xf340, 0xc009, 0xf37f, 0xc009, 0x21, 0 + .dw 0xf3c0, 0xc009, 0xf3ff, 0xc009, 0x21, 0 + .dw 0xf440, 0xc009, 0xf47f, 0xc009, 0x21, 0 + .dw 0xf4c0, 0xc009, 0xf4ff, 0xc009, 0x21, 0 + .dw 0xf540, 0xc009, 0xf57f, 0xc009, 0x21, 0 + .dw 0xf5c0, 0xc009, 0xf5ff, 0xc009, 0x21, 0 + .dw 0xf640, 0xc009, 0xf67f, 0xc009, 0x21, 0 + .dw 0xf6c0, 0xc009, 0xf6ff, 0xc009, 0x21, 0 + .dw 0xf740, 0xc009, 0xf77f, 0xc009, 0x21, 0 + .dw 0xf7c0, 0xc009, 0xf7ff, 0xc009, 0x21, 0 + .dw 0xf840, 0xc009, 0xf87f, 0xc009, 0x21, 0 + .dw 0xf8c0, 0xc009, 0xf8ff, 0xc009, 0x21, 0 + .dw 0xf940, 0xc009, 0xf97f, 0xc009, 0x21, 0 + .dw 0xf9c0, 0xc009, 0x1fff, 0xc00a, 0x21, 0 + .dw 0x2040, 0xc00a, 0x207f, 0xc00a, 0x21, 0 + .dw 0x20c0, 0xc00a, 0x20ff, 0xc00a, 0x21, 0 + .dw 0x2140, 0xc00a, 0x217f, 0xc00a, 0x21, 0 + .dw 0x21c0, 0xc00a, 0x21ff, 0xc00a, 0x21, 0 + .dw 0x2240, 0xc00a, 0x227f, 0xc00a, 0x21, 0 + .dw 0x22c0, 0xc00a, 0x22ff, 0xc00a, 0x21, 0 + .dw 0x2340, 0xc00a, 0x237f, 0xc00a, 0x21, 0 + .dw 0x23c0, 0xc00a, 0x23ff, 0xc00a, 0x21, 0 + .dw 0x2440, 0xc00a, 0x247f, 0xc00a, 0x21, 0 + .dw 0x24c0, 0xc00a, 0x24ff, 0xc00a, 0x21, 0 + .dw 0x2540, 0xc00a, 0x257f, 0xc00a, 0x21, 0 + .dw 0x25c0, 0xc00a, 0x25ff, 0xc00a, 0x21, 0 + .dw 0x2640, 0xc00a, 0x267f, 0xc00a, 0x21, 0 + .dw 0x26c0, 0xc00a, 0x26ff, 0xc00a, 0x21, 0 + .dw 0x2740, 0xc00a, 0x277f, 0xc00a, 0x21, 0 + .dw 0x27c0, 0xc00a, 0x27ff, 0xc00a, 0x21, 0 + .dw 0x2840, 0xc00a, 0x287f, 0xc00a, 0x21, 0 + .dw 0x28c0, 0xc00a, 0x28ff, 0xc00a, 0x21, 0 + .dw 0x2940, 0xc00a, 0x297f, 0xc00a, 0x21, 0 + .dw 0x29c0, 0xc00a, 0x29ff, 0xc00a, 0x21, 0 + .dw 0x2a40, 0xc00a, 0x2a7f, 0xc00a, 0x21, 0 + .dw 0x2ac0, 0xc00a, 0x2aff, 0xc00a, 0x21, 0 + .dw 0x2b40, 0xc00a, 0x2b7f, 0xc00a, 0x21, 0 + .dw 0x2bc0, 0xc00a, 0x2bff, 0xc00a, 0x21, 0 + .dw 0x2c40, 0xc00a, 0x2c7f, 0xc00a, 0x21, 0 + .dw 0x2cc0, 0xc00a, 0x2cff, 0xc00a, 0x21, 0 + .dw 0x2d40, 0xc00a, 0x2d7f, 0xc00a, 0x21, 0 + .dw 0x2dc0, 0xc00a, 0x2dff, 0xc00a, 0x21, 0 + .dw 0x2e40, 0xc00a, 0x2e7f, 0xc00a, 0x21, 0 + .dw 0x2ec0, 0xc00a, 0x2eff, 0xc00a, 0x21, 0 + .dw 0x2f40, 0xc00a, 0x2f7f, 0xc00a, 0x21, 0 + .dw 0x2fc0, 0xc00a, 0x2fff, 0xc00a, 0x21, 0 + .dw 0x3040, 0xc00a, 0x307f, 0xc00a, 0x21, 0 + .dw 0x30c0, 0xc00a, 0x30ff, 0xc00a, 0x21, 0 + .dw 0x3140, 0xc00a, 0x317f, 0xc00a, 0x21, 0 + .dw 0x31c0, 0xc00a, 0x31ff, 0xc00a, 0x21, 0 + .dw 0x3240, 0xc00a, 0x327f, 0xc00a, 0x21, 0 + .dw 0x32c0, 0xc00a, 0x32ff, 0xc00a, 0x21, 0 + .dw 0x3340, 0xc00a, 0x337f, 0xc00a, 0x21, 0 + .dw 0x33c0, 0xc00a, 0x33ff, 0xc00a, 0x21, 0 + .dw 0x3440, 0xc00a, 0x347f, 0xc00a, 0x21, 0 + .dw 0x34c0, 0xc00a, 0x34ff, 0xc00a, 0x21, 0 + .dw 0x3540, 0xc00a, 0x357f, 0xc00a, 0x21, 0 + .dw 0x35c0, 0xc00a, 0x35ff, 0xc00a, 0x21, 0 + .dw 0x3640, 0xc00a, 0x367f, 0xc00a, 0x21, 0 + .dw 0x36c0, 0xc00a, 0x36ff, 0xc00a, 0x21, 0 + .dw 0x3740, 0xc00a, 0x377f, 0xc00a, 0x21, 0 + .dw 0x37c0, 0xc00a, 0x37ff, 0xc00a, 0x21, 0 + .dw 0x3840, 0xc00a, 0x387f, 0xc00a, 0x21, 0 + .dw 0x38c0, 0xc00a, 0x38ff, 0xc00a, 0x21, 0 + .dw 0x3940, 0xc00a, 0x397f, 0xc00a, 0x21, 0 + .dw 0x39c0, 0xc00a, 0x5fff, 0xc00a, 0x21, 0 + .dw 0x6040, 0xc00a, 0x607f, 0xc00a, 0x21, 0 + .dw 0x60c0, 0xc00a, 0x60ff, 0xc00a, 0x21, 0 + .dw 0x6140, 0xc00a, 0x617f, 0xc00a, 0x21, 0 + .dw 0x61c0, 0xc00a, 0x61ff, 0xc00a, 0x21, 0 + .dw 0x6240, 0xc00a, 0x627f, 0xc00a, 0x21, 0 + .dw 0x62c0, 0xc00a, 0x62ff, 0xc00a, 0x21, 0 + .dw 0x6340, 0xc00a, 0x637f, 0xc00a, 0x21, 0 + .dw 0x63c0, 0xc00a, 0x63ff, 0xc00a, 0x21, 0 + .dw 0x6440, 0xc00a, 0x647f, 0xc00a, 0x21, 0 + .dw 0x64c0, 0xc00a, 0x64ff, 0xc00a, 0x21, 0 + .dw 0x6540, 0xc00a, 0x657f, 0xc00a, 0x21, 0 + .dw 0x65c0, 0xc00a, 0x65ff, 0xc00a, 0x21, 0 + .dw 0x6640, 0xc00a, 0x667f, 0xc00a, 0x21, 0 + .dw 0x66c0, 0xc00a, 0x66ff, 0xc00a, 0x21, 0 + .dw 0x6740, 0xc00a, 0x677f, 0xc00a, 0x21, 0 + .dw 0x67c0, 0xc00a, 0x67ff, 0xc00a, 0x21, 0 + .dw 0x6840, 0xc00a, 0x687f, 0xc00a, 0x21, 0 + .dw 0x68c0, 0xc00a, 0x68ff, 0xc00a, 0x21, 0 + .dw 0x6940, 0xc00a, 0x697f, 0xc00a, 0x21, 0 + .dw 0x69c0, 0xc00a, 0x69ff, 0xc00a, 0x21, 0 + .dw 0x6a40, 0xc00a, 0x6a7f, 0xc00a, 0x21, 0 + .dw 0x6ac0, 0xc00a, 0x6aff, 0xc00a, 0x21, 0 + .dw 0x6b40, 0xc00a, 0x6b7f, 0xc00a, 0x21, 0 + .dw 0x6bc0, 0xc00a, 0x6bff, 0xc00a, 0x21, 0 + .dw 0x6c40, 0xc00a, 0x6c7f, 0xc00a, 0x21, 0 + .dw 0x6cc0, 0xc00a, 0x6cff, 0xc00a, 0x21, 0 + .dw 0x6d40, 0xc00a, 0x6d7f, 0xc00a, 0x21, 0 + .dw 0x6dc0, 0xc00a, 0x6dff, 0xc00a, 0x21, 0 + .dw 0x6e40, 0xc00a, 0x6e7f, 0xc00a, 0x21, 0 + .dw 0x6ec0, 0xc00a, 0x6eff, 0xc00a, 0x21, 0 + .dw 0x6f40, 0xc00a, 0x6f7f, 0xc00a, 0x21, 0 + .dw 0x6fc0, 0xc00a, 0x6fff, 0xc00a, 0x21, 0 + .dw 0x7040, 0xc00a, 0x707f, 0xc00a, 0x21, 0 + .dw 0x70c0, 0xc00a, 0x70ff, 0xc00a, 0x21, 0 + .dw 0x7140, 0xc00a, 0x717f, 0xc00a, 0x21, 0 + .dw 0x71c0, 0xc00a, 0x71ff, 0xc00a, 0x21, 0 + .dw 0x7240, 0xc00a, 0x727f, 0xc00a, 0x21, 0 + .dw 0x72c0, 0xc00a, 0x72ff, 0xc00a, 0x21, 0 + .dw 0x7340, 0xc00a, 0x737f, 0xc00a, 0x21, 0 + .dw 0x73c0, 0xc00a, 0x73ff, 0xc00a, 0x21, 0 + .dw 0x7440, 0xc00a, 0x747f, 0xc00a, 0x21, 0 + .dw 0x74c0, 0xc00a, 0x74ff, 0xc00a, 0x21, 0 + .dw 0x7540, 0xc00a, 0x757f, 0xc00a, 0x21, 0 + .dw 0x75c0, 0xc00a, 0x75ff, 0xc00a, 0x21, 0 + .dw 0x7640, 0xc00a, 0x767f, 0xc00a, 0x21, 0 + .dw 0x76c0, 0xc00a, 0x76ff, 0xc00a, 0x21, 0 + .dw 0x7740, 0xc00a, 0x777f, 0xc00a, 0x21, 0 + .dw 0x77c0, 0xc00a, 0x77ff, 0xc00a, 0x21, 0 + .dw 0x7840, 0xc00a, 0x787f, 0xc00a, 0x21, 0 + .dw 0x78c0, 0xc00a, 0x78ff, 0xc00a, 0x21, 0 + .dw 0x7940, 0xc00a, 0x797f, 0xc00a, 0x21, 0 + .dw 0x79c0, 0xc00a, 0x9fff, 0xc00a, 0x21, 0 + .dw 0xa040, 0xc00a, 0xa07f, 0xc00a, 0x21, 0 + .dw 0xa0c0, 0xc00a, 0xa0ff, 0xc00a, 0x21, 0 + .dw 0xa140, 0xc00a, 0xa17f, 0xc00a, 0x21, 0 + .dw 0xa1c0, 0xc00a, 0xa1ff, 0xc00a, 0x21, 0 + .dw 0xa240, 0xc00a, 0xa27f, 0xc00a, 0x21, 0 + .dw 0xa2c0, 0xc00a, 0xa2ff, 0xc00a, 0x21, 0 + .dw 0xa340, 0xc00a, 0xa37f, 0xc00a, 0x21, 0 + .dw 0xa3c0, 0xc00a, 0xa3ff, 0xc00a, 0x21, 0 + .dw 0xa440, 0xc00a, 0xa47f, 0xc00a, 0x21, 0 + .dw 0xa4c0, 0xc00a, 0xa4ff, 0xc00a, 0x21, 0 + .dw 0xa540, 0xc00a, 0xa57f, 0xc00a, 0x21, 0 + .dw 0xa5c0, 0xc00a, 0xa5ff, 0xc00a, 0x21, 0 + .dw 0xa640, 0xc00a, 0xa67f, 0xc00a, 0x21, 0 + .dw 0xa6c0, 0xc00a, 0xa6ff, 0xc00a, 0x21, 0 + .dw 0xa740, 0xc00a, 0xa77f, 0xc00a, 0x21, 0 + .dw 0xa7c0, 0xc00a, 0xa7ff, 0xc00a, 0x21, 0 + .dw 0xa840, 0xc00a, 0xa87f, 0xc00a, 0x21, 0 + .dw 0xa8c0, 0xc00a, 0xa8ff, 0xc00a, 0x21, 0 + .dw 0xa940, 0xc00a, 0xa97f, 0xc00a, 0x21, 0 + .dw 0xa9c0, 0xc00a, 0xa9ff, 0xc00a, 0x21, 0 + .dw 0xaa40, 0xc00a, 0xaa7f, 0xc00a, 0x21, 0 + .dw 0xaac0, 0xc00a, 0xaaff, 0xc00a, 0x21, 0 + .dw 0xab40, 0xc00a, 0xab7f, 0xc00a, 0x21, 0 + .dw 0xabc0, 0xc00a, 0xabff, 0xc00a, 0x21, 0 + .dw 0xac40, 0xc00a, 0xac7f, 0xc00a, 0x21, 0 + .dw 0xacc0, 0xc00a, 0xacff, 0xc00a, 0x21, 0 + .dw 0xad40, 0xc00a, 0xad7f, 0xc00a, 0x21, 0 + .dw 0xadc0, 0xc00a, 0xadff, 0xc00a, 0x21, 0 + .dw 0xae40, 0xc00a, 0xae7f, 0xc00a, 0x21, 0 + .dw 0xaec0, 0xc00a, 0xaeff, 0xc00a, 0x21, 0 + .dw 0xaf40, 0xc00a, 0xaf7f, 0xc00a, 0x21, 0 + .dw 0xafc0, 0xc00a, 0xafff, 0xc00a, 0x21, 0 + .dw 0xb040, 0xc00a, 0xb07f, 0xc00a, 0x21, 0 + .dw 0xb0c0, 0xc00a, 0xb0ff, 0xc00a, 0x21, 0 + .dw 0xb140, 0xc00a, 0xb17f, 0xc00a, 0x21, 0 + .dw 0xb1c0, 0xc00a, 0xb1ff, 0xc00a, 0x21, 0 + .dw 0xb240, 0xc00a, 0xb27f, 0xc00a, 0x21, 0 + .dw 0xb2c0, 0xc00a, 0xb2ff, 0xc00a, 0x21, 0 + .dw 0xb340, 0xc00a, 0xb37f, 0xc00a, 0x21, 0 + .dw 0xb3c0, 0xc00a, 0xb3ff, 0xc00a, 0x21, 0 + .dw 0xb440, 0xc00a, 0xb47f, 0xc00a, 0x21, 0 + .dw 0xb4c0, 0xc00a, 0xb4ff, 0xc00a, 0x21, 0 + .dw 0xb540, 0xc00a, 0xb57f, 0xc00a, 0x21, 0 + .dw 0xb5c0, 0xc00a, 0xb5ff, 0xc00a, 0x21, 0 + .dw 0xb640, 0xc00a, 0xb67f, 0xc00a, 0x21, 0 + .dw 0xb6c0, 0xc00a, 0xb6ff, 0xc00a, 0x21, 0 + .dw 0xb740, 0xc00a, 0xb77f, 0xc00a, 0x21, 0 + .dw 0xb7c0, 0xc00a, 0xb7ff, 0xc00a, 0x21, 0 + .dw 0xb840, 0xc00a, 0xb87f, 0xc00a, 0x21, 0 + .dw 0xb8c0, 0xc00a, 0xb8ff, 0xc00a, 0x21, 0 + .dw 0xb940, 0xc00a, 0xb97f, 0xc00a, 0x21, 0 + .dw 0xb9c0, 0xc00a, 0xdfff, 0xc00a, 0x21, 0 + .dw 0xe040, 0xc00a, 0xe07f, 0xc00a, 0x21, 0 + .dw 0xe0c0, 0xc00a, 0xe0ff, 0xc00a, 0x21, 0 + .dw 0xe140, 0xc00a, 0xe17f, 0xc00a, 0x21, 0 + .dw 0xe1c0, 0xc00a, 0xe1ff, 0xc00a, 0x21, 0 + .dw 0xe240, 0xc00a, 0xe27f, 0xc00a, 0x21, 0 + .dw 0xe2c0, 0xc00a, 0xe2ff, 0xc00a, 0x21, 0 + .dw 0xe340, 0xc00a, 0xe37f, 0xc00a, 0x21, 0 + .dw 0xe3c0, 0xc00a, 0xe3ff, 0xc00a, 0x21, 0 + .dw 0xe440, 0xc00a, 0xe47f, 0xc00a, 0x21, 0 + .dw 0xe4c0, 0xc00a, 0xe4ff, 0xc00a, 0x21, 0 + .dw 0xe540, 0xc00a, 0xe57f, 0xc00a, 0x21, 0 + .dw 0xe5c0, 0xc00a, 0xe5ff, 0xc00a, 0x21, 0 + .dw 0xe640, 0xc00a, 0xe67f, 0xc00a, 0x21, 0 + .dw 0xe6c0, 0xc00a, 0xe6ff, 0xc00a, 0x21, 0 + .dw 0xe740, 0xc00a, 0xe77f, 0xc00a, 0x21, 0 + .dw 0xe7c0, 0xc00a, 0xe7ff, 0xc00a, 0x21, 0 + .dw 0xe840, 0xc00a, 0xe87f, 0xc00a, 0x21, 0 + .dw 0xe8c0, 0xc00a, 0xe8ff, 0xc00a, 0x21, 0 + .dw 0xe940, 0xc00a, 0xe97f, 0xc00a, 0x21, 0 + .dw 0xe9c0, 0xc00a, 0xe9ff, 0xc00a, 0x21, 0 + .dw 0xea40, 0xc00a, 0xea7f, 0xc00a, 0x21, 0 + .dw 0xeac0, 0xc00a, 0xeaff, 0xc00a, 0x21, 0 + .dw 0xeb40, 0xc00a, 0xeb7f, 0xc00a, 0x21, 0 + .dw 0xebc0, 0xc00a, 0xebff, 0xc00a, 0x21, 0 + .dw 0xec40, 0xc00a, 0xec7f, 0xc00a, 0x21, 0 + .dw 0xecc0, 0xc00a, 0xecff, 0xc00a, 0x21, 0 + .dw 0xed40, 0xc00a, 0xed7f, 0xc00a, 0x21, 0 + .dw 0xedc0, 0xc00a, 0xedff, 0xc00a, 0x21, 0 + .dw 0xee40, 0xc00a, 0xee7f, 0xc00a, 0x21, 0 + .dw 0xeec0, 0xc00a, 0xeeff, 0xc00a, 0x21, 0 + .dw 0xef40, 0xc00a, 0xef7f, 0xc00a, 0x21, 0 + .dw 0xefc0, 0xc00a, 0xefff, 0xc00a, 0x21, 0 + .dw 0xf040, 0xc00a, 0xf07f, 0xc00a, 0x21, 0 + .dw 0xf0c0, 0xc00a, 0xf0ff, 0xc00a, 0x21, 0 + .dw 0xf140, 0xc00a, 0xf17f, 0xc00a, 0x21, 0 + .dw 0xf1c0, 0xc00a, 0xf1ff, 0xc00a, 0x21, 0 + .dw 0xf240, 0xc00a, 0xf27f, 0xc00a, 0x21, 0 + .dw 0xf2c0, 0xc00a, 0xf2ff, 0xc00a, 0x21, 0 + .dw 0xf340, 0xc00a, 0xf37f, 0xc00a, 0x21, 0 + .dw 0xf3c0, 0xc00a, 0xf3ff, 0xc00a, 0x21, 0 + .dw 0xf440, 0xc00a, 0xf47f, 0xc00a, 0x21, 0 + .dw 0xf4c0, 0xc00a, 0xf4ff, 0xc00a, 0x21, 0 + .dw 0xf540, 0xc00a, 0xf57f, 0xc00a, 0x21, 0 + .dw 0xf5c0, 0xc00a, 0xf5ff, 0xc00a, 0x21, 0 + .dw 0xf640, 0xc00a, 0xf67f, 0xc00a, 0x21, 0 + .dw 0xf6c0, 0xc00a, 0xf6ff, 0xc00a, 0x21, 0 + .dw 0xf740, 0xc00a, 0xf77f, 0xc00a, 0x21, 0 + .dw 0xf7c0, 0xc00a, 0xf7ff, 0xc00a, 0x21, 0 + .dw 0xf840, 0xc00a, 0xf87f, 0xc00a, 0x21, 0 + .dw 0xf8c0, 0xc00a, 0xf8ff, 0xc00a, 0x21, 0 + .dw 0xf940, 0xc00a, 0xf97f, 0xc00a, 0x21, 0 + .dw 0xf9c0, 0xc00a, 0x1fff, 0xc00b, 0x21, 0 + .dw 0x2040, 0xc00b, 0x207f, 0xc00b, 0x21, 0 + .dw 0x20c0, 0xc00b, 0x20ff, 0xc00b, 0x21, 0 + .dw 0x2140, 0xc00b, 0x217f, 0xc00b, 0x21, 0 + .dw 0x21c0, 0xc00b, 0x21ff, 0xc00b, 0x21, 0 + .dw 0x2240, 0xc00b, 0x227f, 0xc00b, 0x21, 0 + .dw 0x22c0, 0xc00b, 0x22ff, 0xc00b, 0x21, 0 + .dw 0x2340, 0xc00b, 0x237f, 0xc00b, 0x21, 0 + .dw 0x23c0, 0xc00b, 0x23ff, 0xc00b, 0x21, 0 + .dw 0x2440, 0xc00b, 0x247f, 0xc00b, 0x21, 0 + .dw 0x24c0, 0xc00b, 0x24ff, 0xc00b, 0x21, 0 + .dw 0x2540, 0xc00b, 0x257f, 0xc00b, 0x21, 0 + .dw 0x25c0, 0xc00b, 0x25ff, 0xc00b, 0x21, 0 + .dw 0x2640, 0xc00b, 0x267f, 0xc00b, 0x21, 0 + .dw 0x26c0, 0xc00b, 0x26ff, 0xc00b, 0x21, 0 + .dw 0x2740, 0xc00b, 0x277f, 0xc00b, 0x21, 0 + .dw 0x27c0, 0xc00b, 0x27ff, 0xc00b, 0x21, 0 + .dw 0x2840, 0xc00b, 0x287f, 0xc00b, 0x21, 0 + .dw 0x28c0, 0xc00b, 0x28ff, 0xc00b, 0x21, 0 + .dw 0x2940, 0xc00b, 0x297f, 0xc00b, 0x21, 0 + .dw 0x29c0, 0xc00b, 0x29ff, 0xc00b, 0x21, 0 + .dw 0x2a40, 0xc00b, 0x2a7f, 0xc00b, 0x21, 0 + .dw 0x2ac0, 0xc00b, 0x2aff, 0xc00b, 0x21, 0 + .dw 0x2b40, 0xc00b, 0x2b7f, 0xc00b, 0x21, 0 + .dw 0x2bc0, 0xc00b, 0x2bff, 0xc00b, 0x21, 0 + .dw 0x2c40, 0xc00b, 0x2c7f, 0xc00b, 0x21, 0 + .dw 0x2cc0, 0xc00b, 0x2cff, 0xc00b, 0x21, 0 + .dw 0x2d40, 0xc00b, 0x2d7f, 0xc00b, 0x21, 0 + .dw 0x2dc0, 0xc00b, 0x2dff, 0xc00b, 0x21, 0 + .dw 0x2e40, 0xc00b, 0x2e7f, 0xc00b, 0x21, 0 + .dw 0x2ec0, 0xc00b, 0x2eff, 0xc00b, 0x21, 0 + .dw 0x2f40, 0xc00b, 0x2f7f, 0xc00b, 0x21, 0 + .dw 0x2fc0, 0xc00b, 0x2fff, 0xc00b, 0x21, 0 + .dw 0x3040, 0xc00b, 0x307f, 0xc00b, 0x21, 0 + .dw 0x30c0, 0xc00b, 0x30ff, 0xc00b, 0x21, 0 + .dw 0x3140, 0xc00b, 0x317f, 0xc00b, 0x21, 0 + .dw 0x31c0, 0xc00b, 0x31ff, 0xc00b, 0x21, 0 + .dw 0x3240, 0xc00b, 0x327f, 0xc00b, 0x21, 0 + .dw 0x32c0, 0xc00b, 0x32ff, 0xc00b, 0x21, 0 + .dw 0x3340, 0xc00b, 0x337f, 0xc00b, 0x21, 0 + .dw 0x33c0, 0xc00b, 0x33ff, 0xc00b, 0x21, 0 + .dw 0x3440, 0xc00b, 0x347f, 0xc00b, 0x21, 0 + .dw 0x34c0, 0xc00b, 0x34ff, 0xc00b, 0x21, 0 + .dw 0x3540, 0xc00b, 0x357f, 0xc00b, 0x21, 0 + .dw 0x35c0, 0xc00b, 0x35ff, 0xc00b, 0x21, 0 + .dw 0x3640, 0xc00b, 0x367f, 0xc00b, 0x21, 0 + .dw 0x36c0, 0xc00b, 0x36ff, 0xc00b, 0x21, 0 + .dw 0x3740, 0xc00b, 0x377f, 0xc00b, 0x21, 0 + .dw 0x37c0, 0xc00b, 0x37ff, 0xc00b, 0x21, 0 + .dw 0x3840, 0xc00b, 0x387f, 0xc00b, 0x21, 0 + .dw 0x38c0, 0xc00b, 0x38ff, 0xc00b, 0x21, 0 + .dw 0x3940, 0xc00b, 0x397f, 0xc00b, 0x21, 0 + .dw 0x39c0, 0xc00b, 0xffff, 0xc00b, 0x21, 0 + .dw 0x0040, 0xc00c, 0x007f, 0xc00c, 0x21, 0 + .dw 0x00c0, 0xc00c, 0x00ff, 0xc00c, 0x21, 0 + .dw 0x0140, 0xc00c, 0x017f, 0xc00c, 0x21, 0 + .dw 0x01c0, 0xc00c, 0x01ff, 0xc00c, 0x21, 0 + .dw 0x0240, 0xc00c, 0x027f, 0xc00c, 0x21, 0 + .dw 0x02c0, 0xc00c, 0x02ff, 0xc00c, 0x21, 0 + .dw 0x0340, 0xc00c, 0x037f, 0xc00c, 0x21, 0 + .dw 0x03c0, 0xc00c, 0x03ff, 0xc00c, 0x21, 0 + .dw 0x0440, 0xc00c, 0x047f, 0xc00c, 0x21, 0 + .dw 0x04c0, 0xc00c, 0x04ff, 0xc00c, 0x21, 0 + .dw 0x0540, 0xc00c, 0x057f, 0xc00c, 0x21, 0 + .dw 0x05c0, 0xc00c, 0x05ff, 0xc00c, 0x21, 0 + .dw 0x0640, 0xc00c, 0x067f, 0xc00c, 0x21, 0 + .dw 0x06c0, 0xc00c, 0x06ff, 0xc00c, 0x21, 0 + .dw 0x0740, 0xc00c, 0x077f, 0xc00c, 0x21, 0 + .dw 0x07c0, 0xc00c, 0x07ff, 0xc00c, 0x21, 0 + .dw 0x0840, 0xc00c, 0x087f, 0xc00c, 0x21, 0 + .dw 0x08c0, 0xc00c, 0x08ff, 0xc00c, 0x21, 0 + .dw 0x0940, 0xc00c, 0x097f, 0xc00c, 0x21, 0 + .dw 0x09c0, 0xc00c, 0x09ff, 0xc00c, 0x21, 0 + .dw 0x0a40, 0xc00c, 0x0a7f, 0xc00c, 0x21, 0 + .dw 0x0ac0, 0xc00c, 0x0aff, 0xc00c, 0x21, 0 + .dw 0x0b40, 0xc00c, 0x0b7f, 0xc00c, 0x21, 0 + .dw 0x0bc0, 0xc00c, 0x0bff, 0xc00c, 0x21, 0 + .dw 0x0c40, 0xc00c, 0x0c7f, 0xc00c, 0x21, 0 + .dw 0x0cc0, 0xc00c, 0x0cff, 0xc00c, 0x21, 0 + .dw 0x0d40, 0xc00c, 0x0d7f, 0xc00c, 0x21, 0 + .dw 0x0dc0, 0xc00c, 0x0dff, 0xc00c, 0x21, 0 + .dw 0x0e40, 0xc00c, 0x0e7f, 0xc00c, 0x21, 0 + .dw 0x0ec0, 0xc00c, 0x0eff, 0xc00c, 0x21, 0 + .dw 0x0f40, 0xc00c, 0x0f7f, 0xc00c, 0x21, 0 + .dw 0x0fc0, 0xc00c, 0x0fff, 0xc00c, 0x21, 0 + .dw 0x1040, 0xc00c, 0x107f, 0xc00c, 0x21, 0 + .dw 0x10c0, 0xc00c, 0x10ff, 0xc00c, 0x21, 0 + .dw 0x1140, 0xc00c, 0x117f, 0xc00c, 0x21, 0 + .dw 0x11c0, 0xc00c, 0x11ff, 0xc00c, 0x21, 0 + .dw 0x1240, 0xc00c, 0x127f, 0xc00c, 0x21, 0 + .dw 0x12c0, 0xc00c, 0x12ff, 0xc00c, 0x21, 0 + .dw 0x1340, 0xc00c, 0x137f, 0xc00c, 0x21, 0 + .dw 0x13c0, 0xc00c, 0x13ff, 0xc00c, 0x21, 0 + .dw 0x1440, 0xc00c, 0x147f, 0xc00c, 0x21, 0 + .dw 0x14c0, 0xc00c, 0x14ff, 0xc00c, 0x21, 0 + .dw 0x1540, 0xc00c, 0x157f, 0xc00c, 0x21, 0 + .dw 0x15c0, 0xc00c, 0x15ff, 0xc00c, 0x21, 0 + .dw 0x1640, 0xc00c, 0x167f, 0xc00c, 0x21, 0 + .dw 0x16c0, 0xc00c, 0x16ff, 0xc00c, 0x21, 0 + .dw 0x1740, 0xc00c, 0x177f, 0xc00c, 0x21, 0 + .dw 0x17c0, 0xc00c, 0x17ff, 0xc00c, 0x21, 0 + .dw 0x1840, 0xc00c, 0x187f, 0xc00c, 0x21, 0 + .dw 0x18c0, 0xc00c, 0x18ff, 0xc00c, 0x21, 0 + .dw 0x1940, 0xc00c, 0x197f, 0xc00c, 0x21, 0 + .dw 0x19c0, 0xc00c, 0x1fff, 0xc00c, 0x21, 0 + .dw 0x2040, 0xc00c, 0x207f, 0xc00c, 0x21, 0 + .dw 0x20c0, 0xc00c, 0x20ff, 0xc00c, 0x21, 0 + .dw 0x2140, 0xc00c, 0x217f, 0xc00c, 0x21, 0 + .dw 0x21c0, 0xc00c, 0x21ff, 0xc00c, 0x21, 0 + .dw 0x2240, 0xc00c, 0x227f, 0xc00c, 0x21, 0 + .dw 0x22c0, 0xc00c, 0x22ff, 0xc00c, 0x21, 0 + .dw 0x2340, 0xc00c, 0x237f, 0xc00c, 0x21, 0 + .dw 0x23c0, 0xc00c, 0x23ff, 0xc00c, 0x21, 0 + .dw 0x2440, 0xc00c, 0x247f, 0xc00c, 0x21, 0 + .dw 0x24c0, 0xc00c, 0x24ff, 0xc00c, 0x21, 0 + .dw 0x2540, 0xc00c, 0x257f, 0xc00c, 0x21, 0 + .dw 0x25c0, 0xc00c, 0x25ff, 0xc00c, 0x21, 0 + .dw 0x2640, 0xc00c, 0x267f, 0xc00c, 0x21, 0 + .dw 0x26c0, 0xc00c, 0x26ff, 0xc00c, 0x21, 0 + .dw 0x2740, 0xc00c, 0x277f, 0xc00c, 0x21, 0 + .dw 0x27c0, 0xc00c, 0x27ff, 0xc00c, 0x21, 0 + .dw 0x2840, 0xc00c, 0x287f, 0xc00c, 0x21, 0 + .dw 0x28c0, 0xc00c, 0x28ff, 0xc00c, 0x21, 0 + .dw 0x2940, 0xc00c, 0x297f, 0xc00c, 0x21, 0 + .dw 0x29c0, 0xc00c, 0x29ff, 0xc00c, 0x21, 0 + .dw 0x2a40, 0xc00c, 0x2a7f, 0xc00c, 0x21, 0 + .dw 0x2ac0, 0xc00c, 0x2aff, 0xc00c, 0x21, 0 + .dw 0x2b40, 0xc00c, 0x2b7f, 0xc00c, 0x21, 0 + .dw 0x2bc0, 0xc00c, 0x2bff, 0xc00c, 0x21, 0 + .dw 0x2c40, 0xc00c, 0x2c7f, 0xc00c, 0x21, 0 + .dw 0x2cc0, 0xc00c, 0x2cff, 0xc00c, 0x21, 0 + .dw 0x2d40, 0xc00c, 0x2d7f, 0xc00c, 0x21, 0 + .dw 0x2dc0, 0xc00c, 0x2dff, 0xc00c, 0x21, 0 + .dw 0x2e40, 0xc00c, 0x2e7f, 0xc00c, 0x21, 0 + .dw 0x2ec0, 0xc00c, 0x2eff, 0xc00c, 0x21, 0 + .dw 0x2f40, 0xc00c, 0x2f7f, 0xc00c, 0x21, 0 + .dw 0x2fc0, 0xc00c, 0x2fff, 0xc00c, 0x21, 0 + .dw 0x3040, 0xc00c, 0x307f, 0xc00c, 0x21, 0 + .dw 0x30c0, 0xc00c, 0x30ff, 0xc00c, 0x21, 0 + .dw 0x3140, 0xc00c, 0x317f, 0xc00c, 0x21, 0 + .dw 0x31c0, 0xc00c, 0x31ff, 0xc00c, 0x21, 0 + .dw 0x3240, 0xc00c, 0x327f, 0xc00c, 0x21, 0 + .dw 0x32c0, 0xc00c, 0x32ff, 0xc00c, 0x21, 0 + .dw 0x3340, 0xc00c, 0x337f, 0xc00c, 0x21, 0 + .dw 0x33c0, 0xc00c, 0x33ff, 0xc00c, 0x21, 0 + .dw 0x3440, 0xc00c, 0x347f, 0xc00c, 0x21, 0 + .dw 0x34c0, 0xc00c, 0x34ff, 0xc00c, 0x21, 0 + .dw 0x3540, 0xc00c, 0x357f, 0xc00c, 0x21, 0 + .dw 0x35c0, 0xc00c, 0x35ff, 0xc00c, 0x21, 0 + .dw 0x3640, 0xc00c, 0x367f, 0xc00c, 0x21, 0 + .dw 0x36c0, 0xc00c, 0x36ff, 0xc00c, 0x21, 0 + .dw 0x3740, 0xc00c, 0x377f, 0xc00c, 0x21, 0 + .dw 0x37c0, 0xc00c, 0x37ff, 0xc00c, 0x21, 0 + .dw 0x3840, 0xc00c, 0x387f, 0xc00c, 0x21, 0 + .dw 0x38c0, 0xc00c, 0x38ff, 0xc00c, 0x21, 0 + .dw 0x3940, 0xc00c, 0x397f, 0xc00c, 0x21, 0 + .dw 0x39c0, 0xc00c, 0x3fff, 0xc00c, 0x21, 0 + .dw 0x4040, 0xc00c, 0x407f, 0xc00c, 0x21, 0 + .dw 0x40c0, 0xc00c, 0x40ff, 0xc00c, 0x21, 0 + .dw 0x4140, 0xc00c, 0x417f, 0xc00c, 0x21, 0 + .dw 0x41c0, 0xc00c, 0x41ff, 0xc00c, 0x21, 0 + .dw 0x4240, 0xc00c, 0x427f, 0xc00c, 0x21, 0 + .dw 0x42c0, 0xc00c, 0x42ff, 0xc00c, 0x21, 0 + .dw 0x4340, 0xc00c, 0x437f, 0xc00c, 0x21, 0 + .dw 0x43c0, 0xc00c, 0x43ff, 0xc00c, 0x21, 0 + .dw 0x4440, 0xc00c, 0x447f, 0xc00c, 0x21, 0 + .dw 0x44c0, 0xc00c, 0x44ff, 0xc00c, 0x21, 0 + .dw 0x4540, 0xc00c, 0x457f, 0xc00c, 0x21, 0 + .dw 0x45c0, 0xc00c, 0x45ff, 0xc00c, 0x21, 0 + .dw 0x4640, 0xc00c, 0x467f, 0xc00c, 0x21, 0 + .dw 0x46c0, 0xc00c, 0x46ff, 0xc00c, 0x21, 0 + .dw 0x4740, 0xc00c, 0x477f, 0xc00c, 0x21, 0 + .dw 0x47c0, 0xc00c, 0x47ff, 0xc00c, 0x21, 0 + .dw 0x4840, 0xc00c, 0x487f, 0xc00c, 0x21, 0 + .dw 0x48c0, 0xc00c, 0x48ff, 0xc00c, 0x21, 0 + .dw 0x4940, 0xc00c, 0x497f, 0xc00c, 0x21, 0 + .dw 0x49c0, 0xc00c, 0x49ff, 0xc00c, 0x21, 0 + .dw 0x4a40, 0xc00c, 0x4a7f, 0xc00c, 0x21, 0 + .dw 0x4ac0, 0xc00c, 0x4aff, 0xc00c, 0x21, 0 + .dw 0x4b40, 0xc00c, 0x4b7f, 0xc00c, 0x21, 0 + .dw 0x4bc0, 0xc00c, 0x4bff, 0xc00c, 0x21, 0 + .dw 0x4c40, 0xc00c, 0x4c7f, 0xc00c, 0x21, 0 + .dw 0x4cc0, 0xc00c, 0x4cff, 0xc00c, 0x21, 0 + .dw 0x4d40, 0xc00c, 0x4d7f, 0xc00c, 0x21, 0 + .dw 0x4dc0, 0xc00c, 0x4dff, 0xc00c, 0x21, 0 + .dw 0x4e40, 0xc00c, 0x4e7f, 0xc00c, 0x21, 0 + .dw 0x4ec0, 0xc00c, 0x4eff, 0xc00c, 0x21, 0 + .dw 0x4f40, 0xc00c, 0x4f7f, 0xc00c, 0x21, 0 + .dw 0x4fc0, 0xc00c, 0x4fff, 0xc00c, 0x21, 0 + .dw 0x5040, 0xc00c, 0x507f, 0xc00c, 0x21, 0 + .dw 0x50c0, 0xc00c, 0x50ff, 0xc00c, 0x21, 0 + .dw 0x5140, 0xc00c, 0x517f, 0xc00c, 0x21, 0 + .dw 0x51c0, 0xc00c, 0x51ff, 0xc00c, 0x21, 0 + .dw 0x5240, 0xc00c, 0x527f, 0xc00c, 0x21, 0 + .dw 0x52c0, 0xc00c, 0x52ff, 0xc00c, 0x21, 0 + .dw 0x5340, 0xc00c, 0x537f, 0xc00c, 0x21, 0 + .dw 0x53c0, 0xc00c, 0x53ff, 0xc00c, 0x21, 0 + .dw 0x5440, 0xc00c, 0x547f, 0xc00c, 0x21, 0 + .dw 0x54c0, 0xc00c, 0x54ff, 0xc00c, 0x21, 0 + .dw 0x5540, 0xc00c, 0x557f, 0xc00c, 0x21, 0 + .dw 0x55c0, 0xc00c, 0x55ff, 0xc00c, 0x21, 0 + .dw 0x5640, 0xc00c, 0x567f, 0xc00c, 0x21, 0 + .dw 0x56c0, 0xc00c, 0x56ff, 0xc00c, 0x21, 0 + .dw 0x5740, 0xc00c, 0x577f, 0xc00c, 0x21, 0 + .dw 0x57c0, 0xc00c, 0x57ff, 0xc00c, 0x21, 0 + .dw 0x5840, 0xc00c, 0x587f, 0xc00c, 0x21, 0 + .dw 0x58c0, 0xc00c, 0x58ff, 0xc00c, 0x21, 0 + .dw 0x5940, 0xc00c, 0x597f, 0xc00c, 0x21, 0 + .dw 0x59c0, 0xc00c, 0x5fff, 0xc00c, 0x21, 0 + .dw 0x6040, 0xc00c, 0x607f, 0xc00c, 0x21, 0 + .dw 0x60c0, 0xc00c, 0x60ff, 0xc00c, 0x21, 0 + .dw 0x6140, 0xc00c, 0x617f, 0xc00c, 0x21, 0 + .dw 0x61c0, 0xc00c, 0x61ff, 0xc00c, 0x21, 0 + .dw 0x6240, 0xc00c, 0x627f, 0xc00c, 0x21, 0 + .dw 0x62c0, 0xc00c, 0x62ff, 0xc00c, 0x21, 0 + .dw 0x6340, 0xc00c, 0x637f, 0xc00c, 0x21, 0 + .dw 0x63c0, 0xc00c, 0x63ff, 0xc00c, 0x21, 0 + .dw 0x6440, 0xc00c, 0x647f, 0xc00c, 0x21, 0 + .dw 0x64c0, 0xc00c, 0x64ff, 0xc00c, 0x21, 0 + .dw 0x6540, 0xc00c, 0x657f, 0xc00c, 0x21, 0 + .dw 0x65c0, 0xc00c, 0x65ff, 0xc00c, 0x21, 0 + .dw 0x6640, 0xc00c, 0x667f, 0xc00c, 0x21, 0 + .dw 0x66c0, 0xc00c, 0x66ff, 0xc00c, 0x21, 0 + .dw 0x6740, 0xc00c, 0x677f, 0xc00c, 0x21, 0 + .dw 0x67c0, 0xc00c, 0x67ff, 0xc00c, 0x21, 0 + .dw 0x6840, 0xc00c, 0x687f, 0xc00c, 0x21, 0 + .dw 0x68c0, 0xc00c, 0x68ff, 0xc00c, 0x21, 0 + .dw 0x6940, 0xc00c, 0x697f, 0xc00c, 0x21, 0 + .dw 0x69c0, 0xc00c, 0x69ff, 0xc00c, 0x21, 0 + .dw 0x6a40, 0xc00c, 0x6a7f, 0xc00c, 0x21, 0 + .dw 0x6ac0, 0xc00c, 0x6aff, 0xc00c, 0x21, 0 + .dw 0x6b40, 0xc00c, 0x6b7f, 0xc00c, 0x21, 0 + .dw 0x6bc0, 0xc00c, 0x6bff, 0xc00c, 0x21, 0 + .dw 0x6c40, 0xc00c, 0x6c7f, 0xc00c, 0x21, 0 + .dw 0x6cc0, 0xc00c, 0x6cff, 0xc00c, 0x21, 0 + .dw 0x6d40, 0xc00c, 0x6d7f, 0xc00c, 0x21, 0 + .dw 0x6dc0, 0xc00c, 0x6dff, 0xc00c, 0x21, 0 + .dw 0x6e40, 0xc00c, 0x6e7f, 0xc00c, 0x21, 0 + .dw 0x6ec0, 0xc00c, 0x6eff, 0xc00c, 0x21, 0 + .dw 0x6f40, 0xc00c, 0x6f7f, 0xc00c, 0x21, 0 + .dw 0x6fc0, 0xc00c, 0x6fff, 0xc00c, 0x21, 0 + .dw 0x7040, 0xc00c, 0x707f, 0xc00c, 0x21, 0 + .dw 0x70c0, 0xc00c, 0x70ff, 0xc00c, 0x21, 0 + .dw 0x7140, 0xc00c, 0x717f, 0xc00c, 0x21, 0 + .dw 0x71c0, 0xc00c, 0x71ff, 0xc00c, 0x21, 0 + .dw 0x7240, 0xc00c, 0x727f, 0xc00c, 0x21, 0 + .dw 0x72c0, 0xc00c, 0x72ff, 0xc00c, 0x21, 0 + .dw 0x7340, 0xc00c, 0x737f, 0xc00c, 0x21, 0 + .dw 0x73c0, 0xc00c, 0x73ff, 0xc00c, 0x21, 0 + .dw 0x7440, 0xc00c, 0x747f, 0xc00c, 0x21, 0 + .dw 0x74c0, 0xc00c, 0x74ff, 0xc00c, 0x21, 0 + .dw 0x7540, 0xc00c, 0x757f, 0xc00c, 0x21, 0 + .dw 0x75c0, 0xc00c, 0x75ff, 0xc00c, 0x21, 0 + .dw 0x7640, 0xc00c, 0x767f, 0xc00c, 0x21, 0 + .dw 0x76c0, 0xc00c, 0x76ff, 0xc00c, 0x21, 0 + .dw 0x7740, 0xc00c, 0x777f, 0xc00c, 0x21, 0 + .dw 0x77c0, 0xc00c, 0x77ff, 0xc00c, 0x21, 0 + .dw 0x7840, 0xc00c, 0x787f, 0xc00c, 0x21, 0 + .dw 0x78c0, 0xc00c, 0x78ff, 0xc00c, 0x21, 0 + .dw 0x7940, 0xc00c, 0x797f, 0xc00c, 0x21, 0 + .dw 0x79c0, 0xc00c, 0x7fff, 0xc00c, 0x21, 0 + .dw 0x8040, 0xc00c, 0x807f, 0xc00c, 0x21, 0 + .dw 0x80c0, 0xc00c, 0x80ff, 0xc00c, 0x21, 0 + .dw 0x8140, 0xc00c, 0x817f, 0xc00c, 0x21, 0 + .dw 0x81c0, 0xc00c, 0x81ff, 0xc00c, 0x21, 0 + .dw 0x8240, 0xc00c, 0x827f, 0xc00c, 0x21, 0 + .dw 0x82c0, 0xc00c, 0x82ff, 0xc00c, 0x21, 0 + .dw 0x8340, 0xc00c, 0x837f, 0xc00c, 0x21, 0 + .dw 0x83c0, 0xc00c, 0x83ff, 0xc00c, 0x21, 0 + .dw 0x8440, 0xc00c, 0x847f, 0xc00c, 0x21, 0 + .dw 0x84c0, 0xc00c, 0x84ff, 0xc00c, 0x21, 0 + .dw 0x8540, 0xc00c, 0x857f, 0xc00c, 0x21, 0 + .dw 0x85c0, 0xc00c, 0x85ff, 0xc00c, 0x21, 0 + .dw 0x8640, 0xc00c, 0x867f, 0xc00c, 0x21, 0 + .dw 0x86c0, 0xc00c, 0x86ff, 0xc00c, 0x21, 0 + .dw 0x8740, 0xc00c, 0x877f, 0xc00c, 0x21, 0 + .dw 0x87c0, 0xc00c, 0x87ff, 0xc00c, 0x21, 0 + .dw 0x8840, 0xc00c, 0x887f, 0xc00c, 0x21, 0 + .dw 0x88c0, 0xc00c, 0x88ff, 0xc00c, 0x21, 0 + .dw 0x8940, 0xc00c, 0x897f, 0xc00c, 0x21, 0 + .dw 0x89c0, 0xc00c, 0x89ff, 0xc00c, 0x21, 0 + .dw 0x8a40, 0xc00c, 0x8a7f, 0xc00c, 0x21, 0 + .dw 0x8ac0, 0xc00c, 0x8aff, 0xc00c, 0x21, 0 + .dw 0x8b40, 0xc00c, 0x8b7f, 0xc00c, 0x21, 0 + .dw 0x8bc0, 0xc00c, 0x8bff, 0xc00c, 0x21, 0 + .dw 0x8c40, 0xc00c, 0x8c7f, 0xc00c, 0x21, 0 + .dw 0x8cc0, 0xc00c, 0x8cff, 0xc00c, 0x21, 0 + .dw 0x8d40, 0xc00c, 0x8d7f, 0xc00c, 0x21, 0 + .dw 0x8dc0, 0xc00c, 0x8dff, 0xc00c, 0x21, 0 + .dw 0x8e40, 0xc00c, 0x8e7f, 0xc00c, 0x21, 0 + .dw 0x8ec0, 0xc00c, 0x8eff, 0xc00c, 0x21, 0 + .dw 0x8f40, 0xc00c, 0x8f7f, 0xc00c, 0x21, 0 + .dw 0x8fc0, 0xc00c, 0x8fff, 0xc00c, 0x21, 0 + .dw 0x9040, 0xc00c, 0x907f, 0xc00c, 0x21, 0 + .dw 0x90c0, 0xc00c, 0x90ff, 0xc00c, 0x21, 0 + .dw 0x9140, 0xc00c, 0x917f, 0xc00c, 0x21, 0 + .dw 0x91c0, 0xc00c, 0x91ff, 0xc00c, 0x21, 0 + .dw 0x9240, 0xc00c, 0x927f, 0xc00c, 0x21, 0 + .dw 0x92c0, 0xc00c, 0x92ff, 0xc00c, 0x21, 0 + .dw 0x9340, 0xc00c, 0x937f, 0xc00c, 0x21, 0 + .dw 0x93c0, 0xc00c, 0x93ff, 0xc00c, 0x21, 0 + .dw 0x9440, 0xc00c, 0x947f, 0xc00c, 0x21, 0 + .dw 0x94c0, 0xc00c, 0x94ff, 0xc00c, 0x21, 0 + .dw 0x9540, 0xc00c, 0x957f, 0xc00c, 0x21, 0 + .dw 0x95c0, 0xc00c, 0x95ff, 0xc00c, 0x21, 0 + .dw 0x9640, 0xc00c, 0x967f, 0xc00c, 0x21, 0 + .dw 0x96c0, 0xc00c, 0x96ff, 0xc00c, 0x21, 0 + .dw 0x9740, 0xc00c, 0x977f, 0xc00c, 0x21, 0 + .dw 0x97c0, 0xc00c, 0x97ff, 0xc00c, 0x21, 0 + .dw 0x9840, 0xc00c, 0x987f, 0xc00c, 0x21, 0 + .dw 0x98c0, 0xc00c, 0x98ff, 0xc00c, 0x21, 0 + .dw 0x9940, 0xc00c, 0x997f, 0xc00c, 0x21, 0 + .dw 0x99c0, 0xc00c, 0x9fff, 0xc00c, 0x21, 0 + .dw 0xa040, 0xc00c, 0xa07f, 0xc00c, 0x21, 0 + .dw 0xa0c0, 0xc00c, 0xa0ff, 0xc00c, 0x21, 0 + .dw 0xa140, 0xc00c, 0xa17f, 0xc00c, 0x21, 0 + .dw 0xa1c0, 0xc00c, 0xa1ff, 0xc00c, 0x21, 0 + .dw 0xa240, 0xc00c, 0xa27f, 0xc00c, 0x21, 0 + .dw 0xa2c0, 0xc00c, 0xa2ff, 0xc00c, 0x21, 0 + .dw 0xa340, 0xc00c, 0xa37f, 0xc00c, 0x21, 0 + .dw 0xa3c0, 0xc00c, 0xa3ff, 0xc00c, 0x21, 0 + .dw 0xa440, 0xc00c, 0xa47f, 0xc00c, 0x21, 0 + .dw 0xa4c0, 0xc00c, 0xa4ff, 0xc00c, 0x21, 0 + .dw 0xa540, 0xc00c, 0xa57f, 0xc00c, 0x21, 0 + .dw 0xa5c0, 0xc00c, 0xa5ff, 0xc00c, 0x21, 0 + .dw 0xa640, 0xc00c, 0xa67f, 0xc00c, 0x21, 0 + .dw 0xa6c0, 0xc00c, 0xa6ff, 0xc00c, 0x21, 0 + .dw 0xa740, 0xc00c, 0xa77f, 0xc00c, 0x21, 0 + .dw 0xa7c0, 0xc00c, 0xa7ff, 0xc00c, 0x21, 0 + .dw 0xa840, 0xc00c, 0xa87f, 0xc00c, 0x21, 0 + .dw 0xa8c0, 0xc00c, 0xa8ff, 0xc00c, 0x21, 0 + .dw 0xa940, 0xc00c, 0xa97f, 0xc00c, 0x21, 0 + .dw 0xa9c0, 0xc00c, 0xa9ff, 0xc00c, 0x21, 0 + .dw 0xaa40, 0xc00c, 0xaa7f, 0xc00c, 0x21, 0 + .dw 0xaac0, 0xc00c, 0xaaff, 0xc00c, 0x21, 0 + .dw 0xab40, 0xc00c, 0xab7f, 0xc00c, 0x21, 0 + .dw 0xabc0, 0xc00c, 0xabff, 0xc00c, 0x21, 0 + .dw 0xac40, 0xc00c, 0xac7f, 0xc00c, 0x21, 0 + .dw 0xacc0, 0xc00c, 0xacff, 0xc00c, 0x21, 0 + .dw 0xad40, 0xc00c, 0xad7f, 0xc00c, 0x21, 0 + .dw 0xadc0, 0xc00c, 0xadff, 0xc00c, 0x21, 0 + .dw 0xae40, 0xc00c, 0xae7f, 0xc00c, 0x21, 0 + .dw 0xaec0, 0xc00c, 0xaeff, 0xc00c, 0x21, 0 + .dw 0xaf40, 0xc00c, 0xaf7f, 0xc00c, 0x21, 0 + .dw 0xafc0, 0xc00c, 0xafff, 0xc00c, 0x21, 0 + .dw 0xb040, 0xc00c, 0xb07f, 0xc00c, 0x21, 0 + .dw 0xb0c0, 0xc00c, 0xb0ff, 0xc00c, 0x21, 0 + .dw 0xb140, 0xc00c, 0xb17f, 0xc00c, 0x21, 0 + .dw 0xb1c0, 0xc00c, 0xb1ff, 0xc00c, 0x21, 0 + .dw 0xb240, 0xc00c, 0xb27f, 0xc00c, 0x21, 0 + .dw 0xb2c0, 0xc00c, 0xb2ff, 0xc00c, 0x21, 0 + .dw 0xb340, 0xc00c, 0xb37f, 0xc00c, 0x21, 0 + .dw 0xb3c0, 0xc00c, 0xb3ff, 0xc00c, 0x21, 0 + .dw 0xb440, 0xc00c, 0xb47f, 0xc00c, 0x21, 0 + .dw 0xb4c0, 0xc00c, 0xb4ff, 0xc00c, 0x21, 0 + .dw 0xb540, 0xc00c, 0xb57f, 0xc00c, 0x21, 0 + .dw 0xb5c0, 0xc00c, 0xb5ff, 0xc00c, 0x21, 0 + .dw 0xb640, 0xc00c, 0xb67f, 0xc00c, 0x21, 0 + .dw 0xb6c0, 0xc00c, 0xb6ff, 0xc00c, 0x21, 0 + .dw 0xb740, 0xc00c, 0xb77f, 0xc00c, 0x21, 0 + .dw 0xb7c0, 0xc00c, 0xb7ff, 0xc00c, 0x21, 0 + .dw 0xb840, 0xc00c, 0xb87f, 0xc00c, 0x21, 0 + .dw 0xb8c0, 0xc00c, 0xb8ff, 0xc00c, 0x21, 0 + .dw 0xb940, 0xc00c, 0xb97f, 0xc00c, 0x21, 0 + .dw 0xb9c0, 0xc00c, 0xbfff, 0xc00c, 0x21, 0 + .dw 0xc040, 0xc00c, 0xc07f, 0xc00c, 0x21, 0 + .dw 0xc0c0, 0xc00c, 0xc0ff, 0xc00c, 0x21, 0 + .dw 0xc140, 0xc00c, 0xc17f, 0xc00c, 0x21, 0 + .dw 0xc1c0, 0xc00c, 0xc1ff, 0xc00c, 0x21, 0 + .dw 0xc240, 0xc00c, 0xc27f, 0xc00c, 0x21, 0 + .dw 0xc2c0, 0xc00c, 0xc2ff, 0xc00c, 0x21, 0 + .dw 0xc340, 0xc00c, 0xc37f, 0xc00c, 0x21, 0 + .dw 0xc3c0, 0xc00c, 0xc3ff, 0xc00c, 0x21, 0 + .dw 0xc440, 0xc00c, 0xc47f, 0xc00c, 0x21, 0 + .dw 0xc4c0, 0xc00c, 0xc4ff, 0xc00c, 0x21, 0 + .dw 0xc540, 0xc00c, 0xc57f, 0xc00c, 0x21, 0 + .dw 0xc5c0, 0xc00c, 0xc5ff, 0xc00c, 0x21, 0 + .dw 0xc640, 0xc00c, 0xc67f, 0xc00c, 0x21, 0 + .dw 0xc6c0, 0xc00c, 0xc6ff, 0xc00c, 0x21, 0 + .dw 0xc740, 0xc00c, 0xc77f, 0xc00c, 0x21, 0 + .dw 0xc7c0, 0xc00c, 0xc7ff, 0xc00c, 0x21, 0 + .dw 0xc840, 0xc00c, 0xc87f, 0xc00c, 0x21, 0 + .dw 0xc8c0, 0xc00c, 0xc8ff, 0xc00c, 0x21, 0 + .dw 0xc940, 0xc00c, 0xc97f, 0xc00c, 0x21, 0 + .dw 0xc9c0, 0xc00c, 0xc9ff, 0xc00c, 0x21, 0 + .dw 0xca40, 0xc00c, 0xca7f, 0xc00c, 0x21, 0 + .dw 0xcac0, 0xc00c, 0xcaff, 0xc00c, 0x21, 0 + .dw 0xcb40, 0xc00c, 0xcb7f, 0xc00c, 0x21, 0 + .dw 0xcbc0, 0xc00c, 0xcbff, 0xc00c, 0x21, 0 + .dw 0xcc40, 0xc00c, 0xcc7f, 0xc00c, 0x21, 0 + .dw 0xccc0, 0xc00c, 0xccff, 0xc00c, 0x21, 0 + .dw 0xcd40, 0xc00c, 0xcd7f, 0xc00c, 0x21, 0 + .dw 0xcdc0, 0xc00c, 0xcdff, 0xc00c, 0x21, 0 + .dw 0xce40, 0xc00c, 0xce7f, 0xc00c, 0x21, 0 + .dw 0xcec0, 0xc00c, 0xceff, 0xc00c, 0x21, 0 + .dw 0xcf40, 0xc00c, 0xcf7f, 0xc00c, 0x21, 0 + .dw 0xcfc0, 0xc00c, 0xcfff, 0xc00c, 0x21, 0 + .dw 0xd040, 0xc00c, 0xd07f, 0xc00c, 0x21, 0 + .dw 0xd0c0, 0xc00c, 0xd0ff, 0xc00c, 0x21, 0 + .dw 0xd140, 0xc00c, 0xd17f, 0xc00c, 0x21, 0 + .dw 0xd1c0, 0xc00c, 0xd1ff, 0xc00c, 0x21, 0 + .dw 0xd240, 0xc00c, 0xd27f, 0xc00c, 0x21, 0 + .dw 0xd2c0, 0xc00c, 0xd2ff, 0xc00c, 0x21, 0 + .dw 0xd340, 0xc00c, 0xd37f, 0xc00c, 0x21, 0 + .dw 0xd3c0, 0xc00c, 0xd3ff, 0xc00c, 0x21, 0 + .dw 0xd440, 0xc00c, 0xd47f, 0xc00c, 0x21, 0 + .dw 0xd4c0, 0xc00c, 0xd4ff, 0xc00c, 0x21, 0 + .dw 0xd540, 0xc00c, 0xd57f, 0xc00c, 0x21, 0 + .dw 0xd5c0, 0xc00c, 0xd5ff, 0xc00c, 0x21, 0 + .dw 0xd640, 0xc00c, 0xd67f, 0xc00c, 0x21, 0 + .dw 0xd6c0, 0xc00c, 0xd6ff, 0xc00c, 0x21, 0 + .dw 0xd740, 0xc00c, 0xd77f, 0xc00c, 0x21, 0 + .dw 0xd7c0, 0xc00c, 0xd7ff, 0xc00c, 0x21, 0 + .dw 0xd840, 0xc00c, 0xd87f, 0xc00c, 0x21, 0 + .dw 0xd8c0, 0xc00c, 0xd8ff, 0xc00c, 0x21, 0 + .dw 0xd940, 0xc00c, 0xd97f, 0xc00c, 0x21, 0 + .dw 0xd9c0, 0xc00c, 0xdfff, 0xc00c, 0x21, 0 + .dw 0xe040, 0xc00c, 0xe07f, 0xc00c, 0x21, 0 + .dw 0xe0c0, 0xc00c, 0xe0ff, 0xc00c, 0x21, 0 + .dw 0xe140, 0xc00c, 0xe17f, 0xc00c, 0x21, 0 + .dw 0xe1c0, 0xc00c, 0xe1ff, 0xc00c, 0x21, 0 + .dw 0xe240, 0xc00c, 0xe27f, 0xc00c, 0x21, 0 + .dw 0xe2c0, 0xc00c, 0xe2ff, 0xc00c, 0x21, 0 + .dw 0xe340, 0xc00c, 0xe37f, 0xc00c, 0x21, 0 + .dw 0xe3c0, 0xc00c, 0xe3ff, 0xc00c, 0x21, 0 + .dw 0xe440, 0xc00c, 0xe47f, 0xc00c, 0x21, 0 + .dw 0xe4c0, 0xc00c, 0xe4ff, 0xc00c, 0x21, 0 + .dw 0xe540, 0xc00c, 0xe57f, 0xc00c, 0x21, 0 + .dw 0xe5c0, 0xc00c, 0xe5ff, 0xc00c, 0x21, 0 + .dw 0xe640, 0xc00c, 0xe67f, 0xc00c, 0x21, 0 + .dw 0xe6c0, 0xc00c, 0xe6ff, 0xc00c, 0x21, 0 + .dw 0xe740, 0xc00c, 0xe77f, 0xc00c, 0x21, 0 + .dw 0xe7c0, 0xc00c, 0xe7ff, 0xc00c, 0x21, 0 + .dw 0xe840, 0xc00c, 0xe87f, 0xc00c, 0x21, 0 + .dw 0xe8c0, 0xc00c, 0xe8ff, 0xc00c, 0x21, 0 + .dw 0xe940, 0xc00c, 0xe97f, 0xc00c, 0x21, 0 + .dw 0xe9c0, 0xc00c, 0xe9ff, 0xc00c, 0x21, 0 + .dw 0xea40, 0xc00c, 0xea7f, 0xc00c, 0x21, 0 + .dw 0xeac0, 0xc00c, 0xeaff, 0xc00c, 0x21, 0 + .dw 0xeb40, 0xc00c, 0xeb7f, 0xc00c, 0x21, 0 + .dw 0xebc0, 0xc00c, 0xebff, 0xc00c, 0x21, 0 + .dw 0xec40, 0xc00c, 0xec7f, 0xc00c, 0x21, 0 + .dw 0xecc0, 0xc00c, 0xecff, 0xc00c, 0x21, 0 + .dw 0xed40, 0xc00c, 0xed7f, 0xc00c, 0x21, 0 + .dw 0xedc0, 0xc00c, 0xedff, 0xc00c, 0x21, 0 + .dw 0xee40, 0xc00c, 0xee7f, 0xc00c, 0x21, 0 + .dw 0xeec0, 0xc00c, 0xeeff, 0xc00c, 0x21, 0 + .dw 0xef40, 0xc00c, 0xef7f, 0xc00c, 0x21, 0 + .dw 0xefc0, 0xc00c, 0xefff, 0xc00c, 0x21, 0 + .dw 0xf040, 0xc00c, 0xf07f, 0xc00c, 0x21, 0 + .dw 0xf0c0, 0xc00c, 0xf0ff, 0xc00c, 0x21, 0 + .dw 0xf140, 0xc00c, 0xf17f, 0xc00c, 0x21, 0 + .dw 0xf1c0, 0xc00c, 0xf1ff, 0xc00c, 0x21, 0 + .dw 0xf240, 0xc00c, 0xf27f, 0xc00c, 0x21, 0 + .dw 0xf2c0, 0xc00c, 0xf2ff, 0xc00c, 0x21, 0 + .dw 0xf340, 0xc00c, 0xf37f, 0xc00c, 0x21, 0 + .dw 0xf3c0, 0xc00c, 0xf3ff, 0xc00c, 0x21, 0 + .dw 0xf440, 0xc00c, 0xf47f, 0xc00c, 0x21, 0 + .dw 0xf4c0, 0xc00c, 0xf4ff, 0xc00c, 0x21, 0 + .dw 0xf540, 0xc00c, 0xf57f, 0xc00c, 0x21, 0 + .dw 0xf5c0, 0xc00c, 0xf5ff, 0xc00c, 0x21, 0 + .dw 0xf640, 0xc00c, 0xf67f, 0xc00c, 0x21, 0 + .dw 0xf6c0, 0xc00c, 0xf6ff, 0xc00c, 0x21, 0 + .dw 0xf740, 0xc00c, 0xf77f, 0xc00c, 0x21, 0 + .dw 0xf7c0, 0xc00c, 0xf7ff, 0xc00c, 0x21, 0 + .dw 0xf840, 0xc00c, 0xf87f, 0xc00c, 0x21, 0 + .dw 0xf8c0, 0xc00c, 0xf8ff, 0xc00c, 0x21, 0 + .dw 0xf940, 0xc00c, 0xf97f, 0xc00c, 0x21, 0 + .dw 0xf9c0, 0xc00c, 0xffff, 0xc00c, 0x21, 0 + .dw 0x0040, 0xc00d, 0x007f, 0xc00d, 0x21, 0 + .dw 0x00c0, 0xc00d, 0x00ff, 0xc00d, 0x21, 0 + .dw 0x0140, 0xc00d, 0x017f, 0xc00d, 0x21, 0 + .dw 0x01c0, 0xc00d, 0x01ff, 0xc00d, 0x21, 0 + .dw 0x0240, 0xc00d, 0x027f, 0xc00d, 0x21, 0 + .dw 0x02c0, 0xc00d, 0x02ff, 0xc00d, 0x21, 0 + .dw 0x0340, 0xc00d, 0x037f, 0xc00d, 0x21, 0 + .dw 0x03c0, 0xc00d, 0x03ff, 0xc00d, 0x21, 0 + .dw 0x0440, 0xc00d, 0x047f, 0xc00d, 0x21, 0 + .dw 0x04c0, 0xc00d, 0x04ff, 0xc00d, 0x21, 0 + .dw 0x0540, 0xc00d, 0x057f, 0xc00d, 0x21, 0 + .dw 0x05c0, 0xc00d, 0x05ff, 0xc00d, 0x21, 0 + .dw 0x0640, 0xc00d, 0x067f, 0xc00d, 0x21, 0 + .dw 0x06c0, 0xc00d, 0x06ff, 0xc00d, 0x21, 0 + .dw 0x0740, 0xc00d, 0x077f, 0xc00d, 0x21, 0 + .dw 0x07c0, 0xc00d, 0x07ff, 0xc00d, 0x21, 0 + .dw 0x0840, 0xc00d, 0x087f, 0xc00d, 0x21, 0 + .dw 0x08c0, 0xc00d, 0x08ff, 0xc00d, 0x21, 0 + .dw 0x0940, 0xc00d, 0x097f, 0xc00d, 0x21, 0 + .dw 0x09c0, 0xc00d, 0x09ff, 0xc00d, 0x21, 0 + .dw 0x0a40, 0xc00d, 0x0a7f, 0xc00d, 0x21, 0 + .dw 0x0ac0, 0xc00d, 0x0aff, 0xc00d, 0x21, 0 + .dw 0x0b40, 0xc00d, 0x0b7f, 0xc00d, 0x21, 0 + .dw 0x0bc0, 0xc00d, 0x0bff, 0xc00d, 0x21, 0 + .dw 0x0c40, 0xc00d, 0x0c7f, 0xc00d, 0x21, 0 + .dw 0x0cc0, 0xc00d, 0x0cff, 0xc00d, 0x21, 0 + .dw 0x0d40, 0xc00d, 0x0d7f, 0xc00d, 0x21, 0 + .dw 0x0dc0, 0xc00d, 0x0dff, 0xc00d, 0x21, 0 + .dw 0x0e40, 0xc00d, 0x0e7f, 0xc00d, 0x21, 0 + .dw 0x0ec0, 0xc00d, 0x0eff, 0xc00d, 0x21, 0 + .dw 0x0f40, 0xc00d, 0x0f7f, 0xc00d, 0x21, 0 + .dw 0x0fc0, 0xc00d, 0x0fff, 0xc00d, 0x21, 0 + .dw 0x1040, 0xc00d, 0x107f, 0xc00d, 0x21, 0 + .dw 0x10c0, 0xc00d, 0x10ff, 0xc00d, 0x21, 0 + .dw 0x1140, 0xc00d, 0x117f, 0xc00d, 0x21, 0 + .dw 0x11c0, 0xc00d, 0x11ff, 0xc00d, 0x21, 0 + .dw 0x1240, 0xc00d, 0x127f, 0xc00d, 0x21, 0 + .dw 0x12c0, 0xc00d, 0x12ff, 0xc00d, 0x21, 0 + .dw 0x1340, 0xc00d, 0x137f, 0xc00d, 0x21, 0 + .dw 0x13c0, 0xc00d, 0x13ff, 0xc00d, 0x21, 0 + .dw 0x1440, 0xc00d, 0x147f, 0xc00d, 0x21, 0 + .dw 0x14c0, 0xc00d, 0x14ff, 0xc00d, 0x21, 0 + .dw 0x1540, 0xc00d, 0x157f, 0xc00d, 0x21, 0 + .dw 0x15c0, 0xc00d, 0x15ff, 0xc00d, 0x21, 0 + .dw 0x1640, 0xc00d, 0x167f, 0xc00d, 0x21, 0 + .dw 0x16c0, 0xc00d, 0x16ff, 0xc00d, 0x21, 0 + .dw 0x1740, 0xc00d, 0x177f, 0xc00d, 0x21, 0 + .dw 0x17c0, 0xc00d, 0x17ff, 0xc00d, 0x21, 0 + .dw 0x1840, 0xc00d, 0x187f, 0xc00d, 0x21, 0 + .dw 0x18c0, 0xc00d, 0x18ff, 0xc00d, 0x21, 0 + .dw 0x1940, 0xc00d, 0x197f, 0xc00d, 0x21, 0 + .dw 0x19c0, 0xc00d, 0x1fff, 0xc00d, 0x21, 0 + .dw 0x2040, 0xc00d, 0x207f, 0xc00d, 0x21, 0 + .dw 0x20c0, 0xc00d, 0x20ff, 0xc00d, 0x21, 0 + .dw 0x2140, 0xc00d, 0x217f, 0xc00d, 0x21, 0 + .dw 0x21c0, 0xc00d, 0x21ff, 0xc00d, 0x21, 0 + .dw 0x2240, 0xc00d, 0x227f, 0xc00d, 0x21, 0 + .dw 0x22c0, 0xc00d, 0x22ff, 0xc00d, 0x21, 0 + .dw 0x2340, 0xc00d, 0x237f, 0xc00d, 0x21, 0 + .dw 0x23c0, 0xc00d, 0x23ff, 0xc00d, 0x21, 0 + .dw 0x2440, 0xc00d, 0x247f, 0xc00d, 0x21, 0 + .dw 0x24c0, 0xc00d, 0x24ff, 0xc00d, 0x21, 0 + .dw 0x2540, 0xc00d, 0x257f, 0xc00d, 0x21, 0 + .dw 0x25c0, 0xc00d, 0x25ff, 0xc00d, 0x21, 0 + .dw 0x2640, 0xc00d, 0x267f, 0xc00d, 0x21, 0 + .dw 0x26c0, 0xc00d, 0x26ff, 0xc00d, 0x21, 0 + .dw 0x2740, 0xc00d, 0x277f, 0xc00d, 0x21, 0 + .dw 0x27c0, 0xc00d, 0x27ff, 0xc00d, 0x21, 0 + .dw 0x2840, 0xc00d, 0x287f, 0xc00d, 0x21, 0 + .dw 0x28c0, 0xc00d, 0x28ff, 0xc00d, 0x21, 0 + .dw 0x2940, 0xc00d, 0x297f, 0xc00d, 0x21, 0 + .dw 0x29c0, 0xc00d, 0x29ff, 0xc00d, 0x21, 0 + .dw 0x2a40, 0xc00d, 0x2a7f, 0xc00d, 0x21, 0 + .dw 0x2ac0, 0xc00d, 0x2aff, 0xc00d, 0x21, 0 + .dw 0x2b40, 0xc00d, 0x2b7f, 0xc00d, 0x21, 0 + .dw 0x2bc0, 0xc00d, 0x2bff, 0xc00d, 0x21, 0 + .dw 0x2c40, 0xc00d, 0x2c7f, 0xc00d, 0x21, 0 + .dw 0x2cc0, 0xc00d, 0x2cff, 0xc00d, 0x21, 0 + .dw 0x2d40, 0xc00d, 0x2d7f, 0xc00d, 0x21, 0 + .dw 0x2dc0, 0xc00d, 0x2dff, 0xc00d, 0x21, 0 + .dw 0x2e40, 0xc00d, 0x2e7f, 0xc00d, 0x21, 0 + .dw 0x2ec0, 0xc00d, 0x2eff, 0xc00d, 0x21, 0 + .dw 0x2f40, 0xc00d, 0x2f7f, 0xc00d, 0x21, 0 + .dw 0x2fc0, 0xc00d, 0x2fff, 0xc00d, 0x21, 0 + .dw 0x3040, 0xc00d, 0x307f, 0xc00d, 0x21, 0 + .dw 0x30c0, 0xc00d, 0x30ff, 0xc00d, 0x21, 0 + .dw 0x3140, 0xc00d, 0x317f, 0xc00d, 0x21, 0 + .dw 0x31c0, 0xc00d, 0x31ff, 0xc00d, 0x21, 0 + .dw 0x3240, 0xc00d, 0x327f, 0xc00d, 0x21, 0 + .dw 0x32c0, 0xc00d, 0x32ff, 0xc00d, 0x21, 0 + .dw 0x3340, 0xc00d, 0x337f, 0xc00d, 0x21, 0 + .dw 0x33c0, 0xc00d, 0x33ff, 0xc00d, 0x21, 0 + .dw 0x3440, 0xc00d, 0x347f, 0xc00d, 0x21, 0 + .dw 0x34c0, 0xc00d, 0x34ff, 0xc00d, 0x21, 0 + .dw 0x3540, 0xc00d, 0x357f, 0xc00d, 0x21, 0 + .dw 0x35c0, 0xc00d, 0x35ff, 0xc00d, 0x21, 0 + .dw 0x3640, 0xc00d, 0x367f, 0xc00d, 0x21, 0 + .dw 0x36c0, 0xc00d, 0x36ff, 0xc00d, 0x21, 0 + .dw 0x3740, 0xc00d, 0x377f, 0xc00d, 0x21, 0 + .dw 0x37c0, 0xc00d, 0x37ff, 0xc00d, 0x21, 0 + .dw 0x3840, 0xc00d, 0x387f, 0xc00d, 0x21, 0 + .dw 0x38c0, 0xc00d, 0x38ff, 0xc00d, 0x21, 0 + .dw 0x3940, 0xc00d, 0x397f, 0xc00d, 0x21, 0 + .dw 0x39c0, 0xc00d, 0x3fff, 0xc00d, 0x21, 0 + .dw 0x4040, 0xc00d, 0x407f, 0xc00d, 0x21, 0 + .dw 0x40c0, 0xc00d, 0x40ff, 0xc00d, 0x21, 0 + .dw 0x4140, 0xc00d, 0x417f, 0xc00d, 0x21, 0 + .dw 0x41c0, 0xc00d, 0x41ff, 0xc00d, 0x21, 0 + .dw 0x4240, 0xc00d, 0x427f, 0xc00d, 0x21, 0 + .dw 0x42c0, 0xc00d, 0x42ff, 0xc00d, 0x21, 0 + .dw 0x4340, 0xc00d, 0x437f, 0xc00d, 0x21, 0 + .dw 0x43c0, 0xc00d, 0x43ff, 0xc00d, 0x21, 0 + .dw 0x4440, 0xc00d, 0x447f, 0xc00d, 0x21, 0 + .dw 0x44c0, 0xc00d, 0x44ff, 0xc00d, 0x21, 0 + .dw 0x4540, 0xc00d, 0x457f, 0xc00d, 0x21, 0 + .dw 0x45c0, 0xc00d, 0x45ff, 0xc00d, 0x21, 0 + .dw 0x4640, 0xc00d, 0x467f, 0xc00d, 0x21, 0 + .dw 0x46c0, 0xc00d, 0x46ff, 0xc00d, 0x21, 0 + .dw 0x4740, 0xc00d, 0x477f, 0xc00d, 0x21, 0 + .dw 0x47c0, 0xc00d, 0x47ff, 0xc00d, 0x21, 0 + .dw 0x4840, 0xc00d, 0x487f, 0xc00d, 0x21, 0 + .dw 0x48c0, 0xc00d, 0x48ff, 0xc00d, 0x21, 0 + .dw 0x4940, 0xc00d, 0x497f, 0xc00d, 0x21, 0 + .dw 0x49c0, 0xc00d, 0x49ff, 0xc00d, 0x21, 0 + .dw 0x4a40, 0xc00d, 0x4a7f, 0xc00d, 0x21, 0 + .dw 0x4ac0, 0xc00d, 0x4aff, 0xc00d, 0x21, 0 + .dw 0x4b40, 0xc00d, 0x4b7f, 0xc00d, 0x21, 0 + .dw 0x4bc0, 0xc00d, 0x4bff, 0xc00d, 0x21, 0 + .dw 0x4c40, 0xc00d, 0x4c7f, 0xc00d, 0x21, 0 + .dw 0x4cc0, 0xc00d, 0x4cff, 0xc00d, 0x21, 0 + .dw 0x4d40, 0xc00d, 0x4d7f, 0xc00d, 0x21, 0 + .dw 0x4dc0, 0xc00d, 0x4dff, 0xc00d, 0x21, 0 + .dw 0x4e40, 0xc00d, 0x4e7f, 0xc00d, 0x21, 0 + .dw 0x4ec0, 0xc00d, 0x4eff, 0xc00d, 0x21, 0 + .dw 0x4f40, 0xc00d, 0x4f7f, 0xc00d, 0x21, 0 + .dw 0x4fc0, 0xc00d, 0x4fff, 0xc00d, 0x21, 0 + .dw 0x5040, 0xc00d, 0x507f, 0xc00d, 0x21, 0 + .dw 0x50c0, 0xc00d, 0x50ff, 0xc00d, 0x21, 0 + .dw 0x5140, 0xc00d, 0x517f, 0xc00d, 0x21, 0 + .dw 0x51c0, 0xc00d, 0x51ff, 0xc00d, 0x21, 0 + .dw 0x5240, 0xc00d, 0x527f, 0xc00d, 0x21, 0 + .dw 0x52c0, 0xc00d, 0x52ff, 0xc00d, 0x21, 0 + .dw 0x5340, 0xc00d, 0x537f, 0xc00d, 0x21, 0 + .dw 0x53c0, 0xc00d, 0x53ff, 0xc00d, 0x21, 0 + .dw 0x5440, 0xc00d, 0x547f, 0xc00d, 0x21, 0 + .dw 0x54c0, 0xc00d, 0x54ff, 0xc00d, 0x21, 0 + .dw 0x5540, 0xc00d, 0x557f, 0xc00d, 0x21, 0 + .dw 0x55c0, 0xc00d, 0x55ff, 0xc00d, 0x21, 0 + .dw 0x5640, 0xc00d, 0x567f, 0xc00d, 0x21, 0 + .dw 0x56c0, 0xc00d, 0x56ff, 0xc00d, 0x21, 0 + .dw 0x5740, 0xc00d, 0x577f, 0xc00d, 0x21, 0 + .dw 0x57c0, 0xc00d, 0x57ff, 0xc00d, 0x21, 0 + .dw 0x5840, 0xc00d, 0x587f, 0xc00d, 0x21, 0 + .dw 0x58c0, 0xc00d, 0x58ff, 0xc00d, 0x21, 0 + .dw 0x5940, 0xc00d, 0x597f, 0xc00d, 0x21, 0 + .dw 0x59c0, 0xc00d, 0x5fff, 0xc00d, 0x21, 0 + .dw 0x6040, 0xc00d, 0x607f, 0xc00d, 0x21, 0 + .dw 0x60c0, 0xc00d, 0x60ff, 0xc00d, 0x21, 0 + .dw 0x6140, 0xc00d, 0x617f, 0xc00d, 0x21, 0 + .dw 0x61c0, 0xc00d, 0x61ff, 0xc00d, 0x21, 0 + .dw 0x6240, 0xc00d, 0x627f, 0xc00d, 0x21, 0 + .dw 0x62c0, 0xc00d, 0x62ff, 0xc00d, 0x21, 0 + .dw 0x6340, 0xc00d, 0x637f, 0xc00d, 0x21, 0 + .dw 0x63c0, 0xc00d, 0x63ff, 0xc00d, 0x21, 0 + .dw 0x6440, 0xc00d, 0x647f, 0xc00d, 0x21, 0 + .dw 0x64c0, 0xc00d, 0x64ff, 0xc00d, 0x21, 0 + .dw 0x6540, 0xc00d, 0x657f, 0xc00d, 0x21, 0 + .dw 0x65c0, 0xc00d, 0x65ff, 0xc00d, 0x21, 0 + .dw 0x6640, 0xc00d, 0x667f, 0xc00d, 0x21, 0 + .dw 0x66c0, 0xc00d, 0x66ff, 0xc00d, 0x21, 0 + .dw 0x6740, 0xc00d, 0x677f, 0xc00d, 0x21, 0 + .dw 0x67c0, 0xc00d, 0x67ff, 0xc00d, 0x21, 0 + .dw 0x6840, 0xc00d, 0x687f, 0xc00d, 0x21, 0 + .dw 0x68c0, 0xc00d, 0x68ff, 0xc00d, 0x21, 0 + .dw 0x6940, 0xc00d, 0x697f, 0xc00d, 0x21, 0 + .dw 0x69c0, 0xc00d, 0x69ff, 0xc00d, 0x21, 0 + .dw 0x6a40, 0xc00d, 0x6a7f, 0xc00d, 0x21, 0 + .dw 0x6ac0, 0xc00d, 0x6aff, 0xc00d, 0x21, 0 + .dw 0x6b40, 0xc00d, 0x6b7f, 0xc00d, 0x21, 0 + .dw 0x6bc0, 0xc00d, 0x6bff, 0xc00d, 0x21, 0 + .dw 0x6c40, 0xc00d, 0x6c7f, 0xc00d, 0x21, 0 + .dw 0x6cc0, 0xc00d, 0x6cff, 0xc00d, 0x21, 0 + .dw 0x6d40, 0xc00d, 0x6d7f, 0xc00d, 0x21, 0 + .dw 0x6dc0, 0xc00d, 0x6dff, 0xc00d, 0x21, 0 + .dw 0x6e40, 0xc00d, 0x6e7f, 0xc00d, 0x21, 0 + .dw 0x6ec0, 0xc00d, 0x6eff, 0xc00d, 0x21, 0 + .dw 0x6f40, 0xc00d, 0x6f7f, 0xc00d, 0x21, 0 + .dw 0x6fc0, 0xc00d, 0x6fff, 0xc00d, 0x21, 0 + .dw 0x7040, 0xc00d, 0x707f, 0xc00d, 0x21, 0 + .dw 0x70c0, 0xc00d, 0x70ff, 0xc00d, 0x21, 0 + .dw 0x7140, 0xc00d, 0x717f, 0xc00d, 0x21, 0 + .dw 0x71c0, 0xc00d, 0x71ff, 0xc00d, 0x21, 0 + .dw 0x7240, 0xc00d, 0x727f, 0xc00d, 0x21, 0 + .dw 0x72c0, 0xc00d, 0x72ff, 0xc00d, 0x21, 0 + .dw 0x7340, 0xc00d, 0x737f, 0xc00d, 0x21, 0 + .dw 0x73c0, 0xc00d, 0x73ff, 0xc00d, 0x21, 0 + .dw 0x7440, 0xc00d, 0x747f, 0xc00d, 0x21, 0 + .dw 0x74c0, 0xc00d, 0x74ff, 0xc00d, 0x21, 0 + .dw 0x7540, 0xc00d, 0x757f, 0xc00d, 0x21, 0 + .dw 0x75c0, 0xc00d, 0x75ff, 0xc00d, 0x21, 0 + .dw 0x7640, 0xc00d, 0x767f, 0xc00d, 0x21, 0 + .dw 0x76c0, 0xc00d, 0x76ff, 0xc00d, 0x21, 0 + .dw 0x7740, 0xc00d, 0x777f, 0xc00d, 0x21, 0 + .dw 0x77c0, 0xc00d, 0x77ff, 0xc00d, 0x21, 0 + .dw 0x7840, 0xc00d, 0x787f, 0xc00d, 0x21, 0 + .dw 0x78c0, 0xc00d, 0x78ff, 0xc00d, 0x21, 0 + .dw 0x7940, 0xc00d, 0x797f, 0xc00d, 0x21, 0 + .dw 0x79c0, 0xc00d, 0x7fff, 0xc00d, 0x21, 0 + .dw 0x8040, 0xc00d, 0x807f, 0xc00d, 0x21, 0 + .dw 0x80c0, 0xc00d, 0x80ff, 0xc00d, 0x21, 0 + .dw 0x8140, 0xc00d, 0x817f, 0xc00d, 0x21, 0 + .dw 0x81c0, 0xc00d, 0x81ff, 0xc00d, 0x21, 0 + .dw 0x8240, 0xc00d, 0x827f, 0xc00d, 0x21, 0 + .dw 0x82c0, 0xc00d, 0x82ff, 0xc00d, 0x21, 0 + .dw 0x8340, 0xc00d, 0x837f, 0xc00d, 0x21, 0 + .dw 0x83c0, 0xc00d, 0x83ff, 0xc00d, 0x21, 0 + .dw 0x8440, 0xc00d, 0x847f, 0xc00d, 0x21, 0 + .dw 0x84c0, 0xc00d, 0x84ff, 0xc00d, 0x21, 0 + .dw 0x8540, 0xc00d, 0x857f, 0xc00d, 0x21, 0 + .dw 0x85c0, 0xc00d, 0x85ff, 0xc00d, 0x21, 0 + .dw 0x8640, 0xc00d, 0x867f, 0xc00d, 0x21, 0 + .dw 0x86c0, 0xc00d, 0x86ff, 0xc00d, 0x21, 0 + .dw 0x8740, 0xc00d, 0x877f, 0xc00d, 0x21, 0 + .dw 0x87c0, 0xc00d, 0x87ff, 0xc00d, 0x21, 0 + .dw 0x8840, 0xc00d, 0x887f, 0xc00d, 0x21, 0 + .dw 0x88c0, 0xc00d, 0x88ff, 0xc00d, 0x21, 0 + .dw 0x8940, 0xc00d, 0x897f, 0xc00d, 0x21, 0 + .dw 0x89c0, 0xc00d, 0x89ff, 0xc00d, 0x21, 0 + .dw 0x8a40, 0xc00d, 0x8a7f, 0xc00d, 0x21, 0 + .dw 0x8ac0, 0xc00d, 0x8aff, 0xc00d, 0x21, 0 + .dw 0x8b40, 0xc00d, 0x8b7f, 0xc00d, 0x21, 0 + .dw 0x8bc0, 0xc00d, 0x8bff, 0xc00d, 0x21, 0 + .dw 0x8c40, 0xc00d, 0x8c7f, 0xc00d, 0x21, 0 + .dw 0x8cc0, 0xc00d, 0x8cff, 0xc00d, 0x21, 0 + .dw 0x8d40, 0xc00d, 0x8d7f, 0xc00d, 0x21, 0 + .dw 0x8dc0, 0xc00d, 0x8dff, 0xc00d, 0x21, 0 + .dw 0x8e40, 0xc00d, 0x8e7f, 0xc00d, 0x21, 0 + .dw 0x8ec0, 0xc00d, 0x8eff, 0xc00d, 0x21, 0 + .dw 0x8f40, 0xc00d, 0x8f7f, 0xc00d, 0x21, 0 + .dw 0x8fc0, 0xc00d, 0x8fff, 0xc00d, 0x21, 0 + .dw 0x9040, 0xc00d, 0x907f, 0xc00d, 0x21, 0 + .dw 0x90c0, 0xc00d, 0x90ff, 0xc00d, 0x21, 0 + .dw 0x9140, 0xc00d, 0x917f, 0xc00d, 0x21, 0 + .dw 0x91c0, 0xc00d, 0x91ff, 0xc00d, 0x21, 0 + .dw 0x9240, 0xc00d, 0x927f, 0xc00d, 0x21, 0 + .dw 0x92c0, 0xc00d, 0x92ff, 0xc00d, 0x21, 0 + .dw 0x9340, 0xc00d, 0x937f, 0xc00d, 0x21, 0 + .dw 0x93c0, 0xc00d, 0x93ff, 0xc00d, 0x21, 0 + .dw 0x9440, 0xc00d, 0x947f, 0xc00d, 0x21, 0 + .dw 0x94c0, 0xc00d, 0x94ff, 0xc00d, 0x21, 0 + .dw 0x9540, 0xc00d, 0x957f, 0xc00d, 0x21, 0 + .dw 0x95c0, 0xc00d, 0x95ff, 0xc00d, 0x21, 0 + .dw 0x9640, 0xc00d, 0x967f, 0xc00d, 0x21, 0 + .dw 0x96c0, 0xc00d, 0x96ff, 0xc00d, 0x21, 0 + .dw 0x9740, 0xc00d, 0x977f, 0xc00d, 0x21, 0 + .dw 0x97c0, 0xc00d, 0x97ff, 0xc00d, 0x21, 0 + .dw 0x9840, 0xc00d, 0x987f, 0xc00d, 0x21, 0 + .dw 0x98c0, 0xc00d, 0x98ff, 0xc00d, 0x21, 0 + .dw 0x9940, 0xc00d, 0x997f, 0xc00d, 0x21, 0 + .dw 0x99c0, 0xc00d, 0x9fff, 0xc00d, 0x21, 0 + .dw 0xa040, 0xc00d, 0xa07f, 0xc00d, 0x21, 0 + .dw 0xa0c0, 0xc00d, 0xa0ff, 0xc00d, 0x21, 0 + .dw 0xa140, 0xc00d, 0xa17f, 0xc00d, 0x21, 0 + .dw 0xa1c0, 0xc00d, 0xa1ff, 0xc00d, 0x21, 0 + .dw 0xa240, 0xc00d, 0xa27f, 0xc00d, 0x21, 0 + .dw 0xa2c0, 0xc00d, 0xa2ff, 0xc00d, 0x21, 0 + .dw 0xa340, 0xc00d, 0xa37f, 0xc00d, 0x21, 0 + .dw 0xa3c0, 0xc00d, 0xa3ff, 0xc00d, 0x21, 0 + .dw 0xa440, 0xc00d, 0xa47f, 0xc00d, 0x21, 0 + .dw 0xa4c0, 0xc00d, 0xa4ff, 0xc00d, 0x21, 0 + .dw 0xa540, 0xc00d, 0xa57f, 0xc00d, 0x21, 0 + .dw 0xa5c0, 0xc00d, 0xa5ff, 0xc00d, 0x21, 0 + .dw 0xa640, 0xc00d, 0xa67f, 0xc00d, 0x21, 0 + .dw 0xa6c0, 0xc00d, 0xa6ff, 0xc00d, 0x21, 0 + .dw 0xa740, 0xc00d, 0xa77f, 0xc00d, 0x21, 0 + .dw 0xa7c0, 0xc00d, 0xa7ff, 0xc00d, 0x21, 0 + .dw 0xa840, 0xc00d, 0xa87f, 0xc00d, 0x21, 0 + .dw 0xa8c0, 0xc00d, 0xa8ff, 0xc00d, 0x21, 0 + .dw 0xa940, 0xc00d, 0xa97f, 0xc00d, 0x21, 0 + .dw 0xa9c0, 0xc00d, 0xa9ff, 0xc00d, 0x21, 0 + .dw 0xaa40, 0xc00d, 0xaa7f, 0xc00d, 0x21, 0 + .dw 0xaac0, 0xc00d, 0xaaff, 0xc00d, 0x21, 0 + .dw 0xab40, 0xc00d, 0xab7f, 0xc00d, 0x21, 0 + .dw 0xabc0, 0xc00d, 0xabff, 0xc00d, 0x21, 0 + .dw 0xac40, 0xc00d, 0xac7f, 0xc00d, 0x21, 0 + .dw 0xacc0, 0xc00d, 0xacff, 0xc00d, 0x21, 0 + .dw 0xad40, 0xc00d, 0xad7f, 0xc00d, 0x21, 0 + .dw 0xadc0, 0xc00d, 0xadff, 0xc00d, 0x21, 0 + .dw 0xae40, 0xc00d, 0xae7f, 0xc00d, 0x21, 0 + .dw 0xaec0, 0xc00d, 0xaeff, 0xc00d, 0x21, 0 + .dw 0xaf40, 0xc00d, 0xaf7f, 0xc00d, 0x21, 0 + .dw 0xafc0, 0xc00d, 0xafff, 0xc00d, 0x21, 0 + .dw 0xb040, 0xc00d, 0xb07f, 0xc00d, 0x21, 0 + .dw 0xb0c0, 0xc00d, 0xb0ff, 0xc00d, 0x21, 0 + .dw 0xb140, 0xc00d, 0xb17f, 0xc00d, 0x21, 0 + .dw 0xb1c0, 0xc00d, 0xb1ff, 0xc00d, 0x21, 0 + .dw 0xb240, 0xc00d, 0xb27f, 0xc00d, 0x21, 0 + .dw 0xb2c0, 0xc00d, 0xb2ff, 0xc00d, 0x21, 0 + .dw 0xb340, 0xc00d, 0xb37f, 0xc00d, 0x21, 0 + .dw 0xb3c0, 0xc00d, 0xb3ff, 0xc00d, 0x21, 0 + .dw 0xb440, 0xc00d, 0xb47f, 0xc00d, 0x21, 0 + .dw 0xb4c0, 0xc00d, 0xb4ff, 0xc00d, 0x21, 0 + .dw 0xb540, 0xc00d, 0xb57f, 0xc00d, 0x21, 0 + .dw 0xb5c0, 0xc00d, 0xb5ff, 0xc00d, 0x21, 0 + .dw 0xb640, 0xc00d, 0xb67f, 0xc00d, 0x21, 0 + .dw 0xb6c0, 0xc00d, 0xb6ff, 0xc00d, 0x21, 0 + .dw 0xb740, 0xc00d, 0xb77f, 0xc00d, 0x21, 0 + .dw 0xb7c0, 0xc00d, 0xb7ff, 0xc00d, 0x21, 0 + .dw 0xb840, 0xc00d, 0xb87f, 0xc00d, 0x21, 0 + .dw 0xb8c0, 0xc00d, 0xb8ff, 0xc00d, 0x21, 0 + .dw 0xb940, 0xc00d, 0xb97f, 0xc00d, 0x21, 0 + .dw 0xb9c0, 0xc00d, 0xbfff, 0xc00d, 0x21, 0 + .dw 0xc040, 0xc00d, 0xc07f, 0xc00d, 0x21, 0 + .dw 0xc0c0, 0xc00d, 0xc0ff, 0xc00d, 0x21, 0 + .dw 0xc140, 0xc00d, 0xc17f, 0xc00d, 0x21, 0 + .dw 0xc1c0, 0xc00d, 0xc1ff, 0xc00d, 0x21, 0 + .dw 0xc240, 0xc00d, 0xc27f, 0xc00d, 0x21, 0 + .dw 0xc2c0, 0xc00d, 0xc2ff, 0xc00d, 0x21, 0 + .dw 0xc340, 0xc00d, 0xc37f, 0xc00d, 0x21, 0 + .dw 0xc3c0, 0xc00d, 0xc3ff, 0xc00d, 0x21, 0 + .dw 0xc440, 0xc00d, 0xc47f, 0xc00d, 0x21, 0 + .dw 0xc4c0, 0xc00d, 0xc4ff, 0xc00d, 0x21, 0 + .dw 0xc540, 0xc00d, 0xc57f, 0xc00d, 0x21, 0 + .dw 0xc5c0, 0xc00d, 0xc5ff, 0xc00d, 0x21, 0 + .dw 0xc640, 0xc00d, 0xc67f, 0xc00d, 0x21, 0 + .dw 0xc6c0, 0xc00d, 0xc6ff, 0xc00d, 0x21, 0 + .dw 0xc740, 0xc00d, 0xc77f, 0xc00d, 0x21, 0 + .dw 0xc7c0, 0xc00d, 0xc7ff, 0xc00d, 0x21, 0 + .dw 0xc840, 0xc00d, 0xc87f, 0xc00d, 0x21, 0 + .dw 0xc8c0, 0xc00d, 0xc8ff, 0xc00d, 0x21, 0 + .dw 0xc940, 0xc00d, 0xc97f, 0xc00d, 0x21, 0 + .dw 0xc9c0, 0xc00d, 0xc9ff, 0xc00d, 0x21, 0 + .dw 0xca40, 0xc00d, 0xca7f, 0xc00d, 0x21, 0 + .dw 0xcac0, 0xc00d, 0xcaff, 0xc00d, 0x21, 0 + .dw 0xcb40, 0xc00d, 0xcb7f, 0xc00d, 0x21, 0 + .dw 0xcbc0, 0xc00d, 0xcbff, 0xc00d, 0x21, 0 + .dw 0xcc40, 0xc00d, 0xcc7f, 0xc00d, 0x21, 0 + .dw 0xccc0, 0xc00d, 0xccff, 0xc00d, 0x21, 0 + .dw 0xcd40, 0xc00d, 0xcd7f, 0xc00d, 0x21, 0 + .dw 0xcdc0, 0xc00d, 0xcdff, 0xc00d, 0x21, 0 + .dw 0xce40, 0xc00d, 0xce7f, 0xc00d, 0x21, 0 + .dw 0xcec0, 0xc00d, 0xceff, 0xc00d, 0x21, 0 + .dw 0xcf40, 0xc00d, 0xcf7f, 0xc00d, 0x21, 0 + .dw 0xcfc0, 0xc00d, 0xcfff, 0xc00d, 0x21, 0 + .dw 0xd040, 0xc00d, 0xd07f, 0xc00d, 0x21, 0 + .dw 0xd0c0, 0xc00d, 0xd0ff, 0xc00d, 0x21, 0 + .dw 0xd140, 0xc00d, 0xd17f, 0xc00d, 0x21, 0 + .dw 0xd1c0, 0xc00d, 0xd1ff, 0xc00d, 0x21, 0 + .dw 0xd240, 0xc00d, 0xd27f, 0xc00d, 0x21, 0 + .dw 0xd2c0, 0xc00d, 0xd2ff, 0xc00d, 0x21, 0 + .dw 0xd340, 0xc00d, 0xd37f, 0xc00d, 0x21, 0 + .dw 0xd3c0, 0xc00d, 0xd3ff, 0xc00d, 0x21, 0 + .dw 0xd440, 0xc00d, 0xd47f, 0xc00d, 0x21, 0 + .dw 0xd4c0, 0xc00d, 0xd4ff, 0xc00d, 0x21, 0 + .dw 0xd540, 0xc00d, 0xd57f, 0xc00d, 0x21, 0 + .dw 0xd5c0, 0xc00d, 0xd5ff, 0xc00d, 0x21, 0 + .dw 0xd640, 0xc00d, 0xd67f, 0xc00d, 0x21, 0 + .dw 0xd6c0, 0xc00d, 0xd6ff, 0xc00d, 0x21, 0 + .dw 0xd740, 0xc00d, 0xd77f, 0xc00d, 0x21, 0 + .dw 0xd7c0, 0xc00d, 0xd7ff, 0xc00d, 0x21, 0 + .dw 0xd840, 0xc00d, 0xd87f, 0xc00d, 0x21, 0 + .dw 0xd8c0, 0xc00d, 0xd8ff, 0xc00d, 0x21, 0 + .dw 0xd940, 0xc00d, 0xd97f, 0xc00d, 0x21, 0 + .dw 0xd9c0, 0xc00d, 0xdfff, 0xc00d, 0x21, 0 + .dw 0xe040, 0xc00d, 0xe07f, 0xc00d, 0x21, 0 + .dw 0xe0c0, 0xc00d, 0xe0ff, 0xc00d, 0x21, 0 + .dw 0xe140, 0xc00d, 0xe17f, 0xc00d, 0x21, 0 + .dw 0xe1c0, 0xc00d, 0xe1ff, 0xc00d, 0x21, 0 + .dw 0xe240, 0xc00d, 0xe27f, 0xc00d, 0x21, 0 + .dw 0xe2c0, 0xc00d, 0xe2ff, 0xc00d, 0x21, 0 + .dw 0xe340, 0xc00d, 0xe37f, 0xc00d, 0x21, 0 + .dw 0xe3c0, 0xc00d, 0xe3ff, 0xc00d, 0x21, 0 + .dw 0xe440, 0xc00d, 0xe47f, 0xc00d, 0x21, 0 + .dw 0xe4c0, 0xc00d, 0xe4ff, 0xc00d, 0x21, 0 + .dw 0xe540, 0xc00d, 0xe57f, 0xc00d, 0x21, 0 + .dw 0xe5c0, 0xc00d, 0xe5ff, 0xc00d, 0x21, 0 + .dw 0xe640, 0xc00d, 0xe67f, 0xc00d, 0x21, 0 + .dw 0xe6c0, 0xc00d, 0xe6ff, 0xc00d, 0x21, 0 + .dw 0xe740, 0xc00d, 0xe77f, 0xc00d, 0x21, 0 + .dw 0xe7c0, 0xc00d, 0xe7ff, 0xc00d, 0x21, 0 + .dw 0xe840, 0xc00d, 0xe87f, 0xc00d, 0x21, 0 + .dw 0xe8c0, 0xc00d, 0xe8ff, 0xc00d, 0x21, 0 + .dw 0xe940, 0xc00d, 0xe97f, 0xc00d, 0x21, 0 + .dw 0xe9c0, 0xc00d, 0xe9ff, 0xc00d, 0x21, 0 + .dw 0xea40, 0xc00d, 0xea7f, 0xc00d, 0x21, 0 + .dw 0xeac0, 0xc00d, 0xeaff, 0xc00d, 0x21, 0 + .dw 0xeb40, 0xc00d, 0xeb7f, 0xc00d, 0x21, 0 + .dw 0xebc0, 0xc00d, 0xebff, 0xc00d, 0x21, 0 + .dw 0xec40, 0xc00d, 0xec7f, 0xc00d, 0x21, 0 + .dw 0xecc0, 0xc00d, 0xecff, 0xc00d, 0x21, 0 + .dw 0xed40, 0xc00d, 0xed7f, 0xc00d, 0x21, 0 + .dw 0xedc0, 0xc00d, 0xedff, 0xc00d, 0x21, 0 + .dw 0xee40, 0xc00d, 0xee7f, 0xc00d, 0x21, 0 + .dw 0xeec0, 0xc00d, 0xeeff, 0xc00d, 0x21, 0 + .dw 0xef40, 0xc00d, 0xef7f, 0xc00d, 0x21, 0 + .dw 0xefc0, 0xc00d, 0xefff, 0xc00d, 0x21, 0 + .dw 0xf040, 0xc00d, 0xf07f, 0xc00d, 0x21, 0 + .dw 0xf0c0, 0xc00d, 0xf0ff, 0xc00d, 0x21, 0 + .dw 0xf140, 0xc00d, 0xf17f, 0xc00d, 0x21, 0 + .dw 0xf1c0, 0xc00d, 0xf1ff, 0xc00d, 0x21, 0 + .dw 0xf240, 0xc00d, 0xf27f, 0xc00d, 0x21, 0 + .dw 0xf2c0, 0xc00d, 0xf2ff, 0xc00d, 0x21, 0 + .dw 0xf340, 0xc00d, 0xf37f, 0xc00d, 0x21, 0 + .dw 0xf3c0, 0xc00d, 0xf3ff, 0xc00d, 0x21, 0 + .dw 0xf440, 0xc00d, 0xf47f, 0xc00d, 0x21, 0 + .dw 0xf4c0, 0xc00d, 0xf4ff, 0xc00d, 0x21, 0 + .dw 0xf540, 0xc00d, 0xf57f, 0xc00d, 0x21, 0 + .dw 0xf5c0, 0xc00d, 0xf5ff, 0xc00d, 0x21, 0 + .dw 0xf640, 0xc00d, 0xf67f, 0xc00d, 0x21, 0 + .dw 0xf6c0, 0xc00d, 0xf6ff, 0xc00d, 0x21, 0 + .dw 0xf740, 0xc00d, 0xf77f, 0xc00d, 0x21, 0 + .dw 0xf7c0, 0xc00d, 0xf7ff, 0xc00d, 0x21, 0 + .dw 0xf840, 0xc00d, 0xf87f, 0xc00d, 0x21, 0 + .dw 0xf8c0, 0xc00d, 0xf8ff, 0xc00d, 0x21, 0 + .dw 0xf940, 0xc00d, 0xf97f, 0xc00d, 0x21, 0 + .dw 0xf9c0, 0xc00d, 0xffff, 0xc00d, 0x21, 0 + .dw 0x0040, 0xc00e, 0x007f, 0xc00e, 0x21, 0 + .dw 0x00c0, 0xc00e, 0x00ff, 0xc00e, 0x21, 0 + .dw 0x0140, 0xc00e, 0x017f, 0xc00e, 0x21, 0 + .dw 0x01c0, 0xc00e, 0x01ff, 0xc00e, 0x21, 0 + .dw 0x0240, 0xc00e, 0x027f, 0xc00e, 0x21, 0 + .dw 0x02c0, 0xc00e, 0x02ff, 0xc00e, 0x21, 0 + .dw 0x0340, 0xc00e, 0x037f, 0xc00e, 0x21, 0 + .dw 0x03c0, 0xc00e, 0x03ff, 0xc00e, 0x21, 0 + .dw 0x0440, 0xc00e, 0x047f, 0xc00e, 0x21, 0 + .dw 0x04c0, 0xc00e, 0x04ff, 0xc00e, 0x21, 0 + .dw 0x0540, 0xc00e, 0x057f, 0xc00e, 0x21, 0 + .dw 0x05c0, 0xc00e, 0x05ff, 0xc00e, 0x21, 0 + .dw 0x0640, 0xc00e, 0x067f, 0xc00e, 0x21, 0 + .dw 0x06c0, 0xc00e, 0x06ff, 0xc00e, 0x21, 0 + .dw 0x0740, 0xc00e, 0x077f, 0xc00e, 0x21, 0 + .dw 0x07c0, 0xc00e, 0x07ff, 0xc00e, 0x21, 0 + .dw 0x0840, 0xc00e, 0x087f, 0xc00e, 0x21, 0 + .dw 0x08c0, 0xc00e, 0x08ff, 0xc00e, 0x21, 0 + .dw 0x0940, 0xc00e, 0x097f, 0xc00e, 0x21, 0 + .dw 0x09c0, 0xc00e, 0x09ff, 0xc00e, 0x21, 0 + .dw 0x0a40, 0xc00e, 0x0a7f, 0xc00e, 0x21, 0 + .dw 0x0ac0, 0xc00e, 0x0aff, 0xc00e, 0x21, 0 + .dw 0x0b40, 0xc00e, 0x0b7f, 0xc00e, 0x21, 0 + .dw 0x0bc0, 0xc00e, 0x0bff, 0xc00e, 0x21, 0 + .dw 0x0c40, 0xc00e, 0x0c7f, 0xc00e, 0x21, 0 + .dw 0x0cc0, 0xc00e, 0x0cff, 0xc00e, 0x21, 0 + .dw 0x0d40, 0xc00e, 0x0d7f, 0xc00e, 0x21, 0 + .dw 0x0dc0, 0xc00e, 0x0dff, 0xc00e, 0x21, 0 + .dw 0x0e40, 0xc00e, 0x0e7f, 0xc00e, 0x21, 0 + .dw 0x0ec0, 0xc00e, 0x0eff, 0xc00e, 0x21, 0 + .dw 0x0f40, 0xc00e, 0x0f7f, 0xc00e, 0x21, 0 + .dw 0x0fc0, 0xc00e, 0x0fff, 0xc00e, 0x21, 0 + .dw 0x1040, 0xc00e, 0x107f, 0xc00e, 0x21, 0 + .dw 0x10c0, 0xc00e, 0x10ff, 0xc00e, 0x21, 0 + .dw 0x1140, 0xc00e, 0x117f, 0xc00e, 0x21, 0 + .dw 0x11c0, 0xc00e, 0x11ff, 0xc00e, 0x21, 0 + .dw 0x1240, 0xc00e, 0x127f, 0xc00e, 0x21, 0 + .dw 0x12c0, 0xc00e, 0x12ff, 0xc00e, 0x21, 0 + .dw 0x1340, 0xc00e, 0x137f, 0xc00e, 0x21, 0 + .dw 0x13c0, 0xc00e, 0x13ff, 0xc00e, 0x21, 0 + .dw 0x1440, 0xc00e, 0x147f, 0xc00e, 0x21, 0 + .dw 0x14c0, 0xc00e, 0x14ff, 0xc00e, 0x21, 0 + .dw 0x1540, 0xc00e, 0x157f, 0xc00e, 0x21, 0 + .dw 0x15c0, 0xc00e, 0x15ff, 0xc00e, 0x21, 0 + .dw 0x1640, 0xc00e, 0x167f, 0xc00e, 0x21, 0 + .dw 0x16c0, 0xc00e, 0x16ff, 0xc00e, 0x21, 0 + .dw 0x1740, 0xc00e, 0x177f, 0xc00e, 0x21, 0 + .dw 0x17c0, 0xc00e, 0x17ff, 0xc00e, 0x21, 0 + .dw 0x1840, 0xc00e, 0x187f, 0xc00e, 0x21, 0 + .dw 0x18c0, 0xc00e, 0x18ff, 0xc00e, 0x21, 0 + .dw 0x1940, 0xc00e, 0x197f, 0xc00e, 0x21, 0 + .dw 0x19c0, 0xc00e, 0x1fff, 0xc00e, 0x21, 0 + .dw 0x2040, 0xc00e, 0x207f, 0xc00e, 0x21, 0 + .dw 0x20c0, 0xc00e, 0x20ff, 0xc00e, 0x21, 0 + .dw 0x2140, 0xc00e, 0x217f, 0xc00e, 0x21, 0 + .dw 0x21c0, 0xc00e, 0x21ff, 0xc00e, 0x21, 0 + .dw 0x2240, 0xc00e, 0x227f, 0xc00e, 0x21, 0 + .dw 0x22c0, 0xc00e, 0x22ff, 0xc00e, 0x21, 0 + .dw 0x2340, 0xc00e, 0x237f, 0xc00e, 0x21, 0 + .dw 0x23c0, 0xc00e, 0x23ff, 0xc00e, 0x21, 0 + .dw 0x2440, 0xc00e, 0x247f, 0xc00e, 0x21, 0 + .dw 0x24c0, 0xc00e, 0x24ff, 0xc00e, 0x21, 0 + .dw 0x2540, 0xc00e, 0x257f, 0xc00e, 0x21, 0 + .dw 0x25c0, 0xc00e, 0x25ff, 0xc00e, 0x21, 0 + .dw 0x2640, 0xc00e, 0x267f, 0xc00e, 0x21, 0 + .dw 0x26c0, 0xc00e, 0x26ff, 0xc00e, 0x21, 0 + .dw 0x2740, 0xc00e, 0x277f, 0xc00e, 0x21, 0 + .dw 0x27c0, 0xc00e, 0x27ff, 0xc00e, 0x21, 0 + .dw 0x2840, 0xc00e, 0x287f, 0xc00e, 0x21, 0 + .dw 0x28c0, 0xc00e, 0x28ff, 0xc00e, 0x21, 0 + .dw 0x2940, 0xc00e, 0x297f, 0xc00e, 0x21, 0 + .dw 0x29c0, 0xc00e, 0x29ff, 0xc00e, 0x21, 0 + .dw 0x2a40, 0xc00e, 0x2a7f, 0xc00e, 0x21, 0 + .dw 0x2ac0, 0xc00e, 0x2aff, 0xc00e, 0x21, 0 + .dw 0x2b40, 0xc00e, 0x2b7f, 0xc00e, 0x21, 0 + .dw 0x2bc0, 0xc00e, 0x2bff, 0xc00e, 0x21, 0 + .dw 0x2c40, 0xc00e, 0x2c7f, 0xc00e, 0x21, 0 + .dw 0x2cc0, 0xc00e, 0x2cff, 0xc00e, 0x21, 0 + .dw 0x2d40, 0xc00e, 0x2d7f, 0xc00e, 0x21, 0 + .dw 0x2dc0, 0xc00e, 0x2dff, 0xc00e, 0x21, 0 + .dw 0x2e40, 0xc00e, 0x2e7f, 0xc00e, 0x21, 0 + .dw 0x2ec0, 0xc00e, 0x2eff, 0xc00e, 0x21, 0 + .dw 0x2f40, 0xc00e, 0x2f7f, 0xc00e, 0x21, 0 + .dw 0x2fc0, 0xc00e, 0x2fff, 0xc00e, 0x21, 0 + .dw 0x3040, 0xc00e, 0x307f, 0xc00e, 0x21, 0 + .dw 0x30c0, 0xc00e, 0x30ff, 0xc00e, 0x21, 0 + .dw 0x3140, 0xc00e, 0x317f, 0xc00e, 0x21, 0 + .dw 0x31c0, 0xc00e, 0x31ff, 0xc00e, 0x21, 0 + .dw 0x3240, 0xc00e, 0x327f, 0xc00e, 0x21, 0 + .dw 0x32c0, 0xc00e, 0x32ff, 0xc00e, 0x21, 0 + .dw 0x3340, 0xc00e, 0x337f, 0xc00e, 0x21, 0 + .dw 0x33c0, 0xc00e, 0x33ff, 0xc00e, 0x21, 0 + .dw 0x3440, 0xc00e, 0x347f, 0xc00e, 0x21, 0 + .dw 0x34c0, 0xc00e, 0x34ff, 0xc00e, 0x21, 0 + .dw 0x3540, 0xc00e, 0x357f, 0xc00e, 0x21, 0 + .dw 0x35c0, 0xc00e, 0x35ff, 0xc00e, 0x21, 0 + .dw 0x3640, 0xc00e, 0x367f, 0xc00e, 0x21, 0 + .dw 0x36c0, 0xc00e, 0x36ff, 0xc00e, 0x21, 0 + .dw 0x3740, 0xc00e, 0x377f, 0xc00e, 0x21, 0 + .dw 0x37c0, 0xc00e, 0x37ff, 0xc00e, 0x21, 0 + .dw 0x3840, 0xc00e, 0x387f, 0xc00e, 0x21, 0 + .dw 0x38c0, 0xc00e, 0x38ff, 0xc00e, 0x21, 0 + .dw 0x3940, 0xc00e, 0x397f, 0xc00e, 0x21, 0 + .dw 0x39c0, 0xc00e, 0x3fff, 0xc00e, 0x21, 0 + .dw 0x4040, 0xc00e, 0x407f, 0xc00e, 0x21, 0 + .dw 0x40c0, 0xc00e, 0x40ff, 0xc00e, 0x21, 0 + .dw 0x4140, 0xc00e, 0x417f, 0xc00e, 0x21, 0 + .dw 0x41c0, 0xc00e, 0x41ff, 0xc00e, 0x21, 0 + .dw 0x4240, 0xc00e, 0x427f, 0xc00e, 0x21, 0 + .dw 0x42c0, 0xc00e, 0x42ff, 0xc00e, 0x21, 0 + .dw 0x4340, 0xc00e, 0x437f, 0xc00e, 0x21, 0 + .dw 0x43c0, 0xc00e, 0x43ff, 0xc00e, 0x21, 0 + .dw 0x4440, 0xc00e, 0x447f, 0xc00e, 0x21, 0 + .dw 0x44c0, 0xc00e, 0x44ff, 0xc00e, 0x21, 0 + .dw 0x4540, 0xc00e, 0x457f, 0xc00e, 0x21, 0 + .dw 0x45c0, 0xc00e, 0x45ff, 0xc00e, 0x21, 0 + .dw 0x4640, 0xc00e, 0x467f, 0xc00e, 0x21, 0 + .dw 0x46c0, 0xc00e, 0x46ff, 0xc00e, 0x21, 0 + .dw 0x4740, 0xc00e, 0x477f, 0xc00e, 0x21, 0 + .dw 0x47c0, 0xc00e, 0x47ff, 0xc00e, 0x21, 0 + .dw 0x4840, 0xc00e, 0x487f, 0xc00e, 0x21, 0 + .dw 0x48c0, 0xc00e, 0x48ff, 0xc00e, 0x21, 0 + .dw 0x4940, 0xc00e, 0x497f, 0xc00e, 0x21, 0 + .dw 0x49c0, 0xc00e, 0x49ff, 0xc00e, 0x21, 0 + .dw 0x4a40, 0xc00e, 0x4a7f, 0xc00e, 0x21, 0 + .dw 0x4ac0, 0xc00e, 0x4aff, 0xc00e, 0x21, 0 + .dw 0x4b40, 0xc00e, 0x4b7f, 0xc00e, 0x21, 0 + .dw 0x4bc0, 0xc00e, 0x4bff, 0xc00e, 0x21, 0 + .dw 0x4c40, 0xc00e, 0x4c7f, 0xc00e, 0x21, 0 + .dw 0x4cc0, 0xc00e, 0x4cff, 0xc00e, 0x21, 0 + .dw 0x4d40, 0xc00e, 0x4d7f, 0xc00e, 0x21, 0 + .dw 0x4dc0, 0xc00e, 0x4dff, 0xc00e, 0x21, 0 + .dw 0x4e40, 0xc00e, 0x4e7f, 0xc00e, 0x21, 0 + .dw 0x4ec0, 0xc00e, 0x4eff, 0xc00e, 0x21, 0 + .dw 0x4f40, 0xc00e, 0x4f7f, 0xc00e, 0x21, 0 + .dw 0x4fc0, 0xc00e, 0x4fff, 0xc00e, 0x21, 0 + .dw 0x5040, 0xc00e, 0x507f, 0xc00e, 0x21, 0 + .dw 0x50c0, 0xc00e, 0x50ff, 0xc00e, 0x21, 0 + .dw 0x5140, 0xc00e, 0x517f, 0xc00e, 0x21, 0 + .dw 0x51c0, 0xc00e, 0x51ff, 0xc00e, 0x21, 0 + .dw 0x5240, 0xc00e, 0x527f, 0xc00e, 0x21, 0 + .dw 0x52c0, 0xc00e, 0x52ff, 0xc00e, 0x21, 0 + .dw 0x5340, 0xc00e, 0x537f, 0xc00e, 0x21, 0 + .dw 0x53c0, 0xc00e, 0x53ff, 0xc00e, 0x21, 0 + .dw 0x5440, 0xc00e, 0x547f, 0xc00e, 0x21, 0 + .dw 0x54c0, 0xc00e, 0x54ff, 0xc00e, 0x21, 0 + .dw 0x5540, 0xc00e, 0x557f, 0xc00e, 0x21, 0 + .dw 0x55c0, 0xc00e, 0x55ff, 0xc00e, 0x21, 0 + .dw 0x5640, 0xc00e, 0x567f, 0xc00e, 0x21, 0 + .dw 0x56c0, 0xc00e, 0x56ff, 0xc00e, 0x21, 0 + .dw 0x5740, 0xc00e, 0x577f, 0xc00e, 0x21, 0 + .dw 0x57c0, 0xc00e, 0x57ff, 0xc00e, 0x21, 0 + .dw 0x5840, 0xc00e, 0x587f, 0xc00e, 0x21, 0 + .dw 0x58c0, 0xc00e, 0x58ff, 0xc00e, 0x21, 0 + .dw 0x5940, 0xc00e, 0x597f, 0xc00e, 0x21, 0 + .dw 0x59c0, 0xc00e, 0x5fff, 0xc00e, 0x21, 0 + .dw 0x6040, 0xc00e, 0x607f, 0xc00e, 0x21, 0 + .dw 0x60c0, 0xc00e, 0x60ff, 0xc00e, 0x21, 0 + .dw 0x6140, 0xc00e, 0x617f, 0xc00e, 0x21, 0 + .dw 0x61c0, 0xc00e, 0x61ff, 0xc00e, 0x21, 0 + .dw 0x6240, 0xc00e, 0x627f, 0xc00e, 0x21, 0 + .dw 0x62c0, 0xc00e, 0x62ff, 0xc00e, 0x21, 0 + .dw 0x6340, 0xc00e, 0x637f, 0xc00e, 0x21, 0 + .dw 0x63c0, 0xc00e, 0x63ff, 0xc00e, 0x21, 0 + .dw 0x6440, 0xc00e, 0x647f, 0xc00e, 0x21, 0 + .dw 0x64c0, 0xc00e, 0x64ff, 0xc00e, 0x21, 0 + .dw 0x6540, 0xc00e, 0x657f, 0xc00e, 0x21, 0 + .dw 0x65c0, 0xc00e, 0x65ff, 0xc00e, 0x21, 0 + .dw 0x6640, 0xc00e, 0x667f, 0xc00e, 0x21, 0 + .dw 0x66c0, 0xc00e, 0x66ff, 0xc00e, 0x21, 0 + .dw 0x6740, 0xc00e, 0x677f, 0xc00e, 0x21, 0 + .dw 0x67c0, 0xc00e, 0x67ff, 0xc00e, 0x21, 0 + .dw 0x6840, 0xc00e, 0x687f, 0xc00e, 0x21, 0 + .dw 0x68c0, 0xc00e, 0x68ff, 0xc00e, 0x21, 0 + .dw 0x6940, 0xc00e, 0x697f, 0xc00e, 0x21, 0 + .dw 0x69c0, 0xc00e, 0x69ff, 0xc00e, 0x21, 0 + .dw 0x6a40, 0xc00e, 0x6a7f, 0xc00e, 0x21, 0 + .dw 0x6ac0, 0xc00e, 0x6aff, 0xc00e, 0x21, 0 + .dw 0x6b40, 0xc00e, 0x6b7f, 0xc00e, 0x21, 0 + .dw 0x6bc0, 0xc00e, 0x6bff, 0xc00e, 0x21, 0 + .dw 0x6c40, 0xc00e, 0x6c7f, 0xc00e, 0x21, 0 + .dw 0x6cc0, 0xc00e, 0x6cff, 0xc00e, 0x21, 0 + .dw 0x6d40, 0xc00e, 0x6d7f, 0xc00e, 0x21, 0 + .dw 0x6dc0, 0xc00e, 0x6dff, 0xc00e, 0x21, 0 + .dw 0x6e40, 0xc00e, 0x6e7f, 0xc00e, 0x21, 0 + .dw 0x6ec0, 0xc00e, 0x6eff, 0xc00e, 0x21, 0 + .dw 0x6f40, 0xc00e, 0x6f7f, 0xc00e, 0x21, 0 + .dw 0x6fc0, 0xc00e, 0x6fff, 0xc00e, 0x21, 0 + .dw 0x7040, 0xc00e, 0x707f, 0xc00e, 0x21, 0 + .dw 0x70c0, 0xc00e, 0x70ff, 0xc00e, 0x21, 0 + .dw 0x7140, 0xc00e, 0x717f, 0xc00e, 0x21, 0 + .dw 0x71c0, 0xc00e, 0x71ff, 0xc00e, 0x21, 0 + .dw 0x7240, 0xc00e, 0x727f, 0xc00e, 0x21, 0 + .dw 0x72c0, 0xc00e, 0x72ff, 0xc00e, 0x21, 0 + .dw 0x7340, 0xc00e, 0x737f, 0xc00e, 0x21, 0 + .dw 0x73c0, 0xc00e, 0x73ff, 0xc00e, 0x21, 0 + .dw 0x7440, 0xc00e, 0x747f, 0xc00e, 0x21, 0 + .dw 0x74c0, 0xc00e, 0x74ff, 0xc00e, 0x21, 0 + .dw 0x7540, 0xc00e, 0x757f, 0xc00e, 0x21, 0 + .dw 0x75c0, 0xc00e, 0x75ff, 0xc00e, 0x21, 0 + .dw 0x7640, 0xc00e, 0x767f, 0xc00e, 0x21, 0 + .dw 0x76c0, 0xc00e, 0x76ff, 0xc00e, 0x21, 0 + .dw 0x7740, 0xc00e, 0x777f, 0xc00e, 0x21, 0 + .dw 0x77c0, 0xc00e, 0x77ff, 0xc00e, 0x21, 0 + .dw 0x7840, 0xc00e, 0x787f, 0xc00e, 0x21, 0 + .dw 0x78c0, 0xc00e, 0x78ff, 0xc00e, 0x21, 0 + .dw 0x7940, 0xc00e, 0x797f, 0xc00e, 0x21, 0 + .dw 0x79c0, 0xc00e, 0x7fff, 0xc00e, 0x21, 0 + .dw 0x8040, 0xc00e, 0x807f, 0xc00e, 0x21, 0 + .dw 0x80c0, 0xc00e, 0x80ff, 0xc00e, 0x21, 0 + .dw 0x8140, 0xc00e, 0x817f, 0xc00e, 0x21, 0 + .dw 0x81c0, 0xc00e, 0x81ff, 0xc00e, 0x21, 0 + .dw 0x8240, 0xc00e, 0x827f, 0xc00e, 0x21, 0 + .dw 0x82c0, 0xc00e, 0x82ff, 0xc00e, 0x21, 0 + .dw 0x8340, 0xc00e, 0x837f, 0xc00e, 0x21, 0 + .dw 0x83c0, 0xc00e, 0x83ff, 0xc00e, 0x21, 0 + .dw 0x8440, 0xc00e, 0x847f, 0xc00e, 0x21, 0 + .dw 0x84c0, 0xc00e, 0x84ff, 0xc00e, 0x21, 0 + .dw 0x8540, 0xc00e, 0x857f, 0xc00e, 0x21, 0 + .dw 0x85c0, 0xc00e, 0x85ff, 0xc00e, 0x21, 0 + .dw 0x8640, 0xc00e, 0x867f, 0xc00e, 0x21, 0 + .dw 0x86c0, 0xc00e, 0x86ff, 0xc00e, 0x21, 0 + .dw 0x8740, 0xc00e, 0x877f, 0xc00e, 0x21, 0 + .dw 0x87c0, 0xc00e, 0x87ff, 0xc00e, 0x21, 0 + .dw 0x8840, 0xc00e, 0x887f, 0xc00e, 0x21, 0 + .dw 0x88c0, 0xc00e, 0x88ff, 0xc00e, 0x21, 0 + .dw 0x8940, 0xc00e, 0x897f, 0xc00e, 0x21, 0 + .dw 0x89c0, 0xc00e, 0x89ff, 0xc00e, 0x21, 0 + .dw 0x8a40, 0xc00e, 0x8a7f, 0xc00e, 0x21, 0 + .dw 0x8ac0, 0xc00e, 0x8aff, 0xc00e, 0x21, 0 + .dw 0x8b40, 0xc00e, 0x8b7f, 0xc00e, 0x21, 0 + .dw 0x8bc0, 0xc00e, 0x8bff, 0xc00e, 0x21, 0 + .dw 0x8c40, 0xc00e, 0x8c7f, 0xc00e, 0x21, 0 + .dw 0x8cc0, 0xc00e, 0x8cff, 0xc00e, 0x21, 0 + .dw 0x8d40, 0xc00e, 0x8d7f, 0xc00e, 0x21, 0 + .dw 0x8dc0, 0xc00e, 0x8dff, 0xc00e, 0x21, 0 + .dw 0x8e40, 0xc00e, 0x8e7f, 0xc00e, 0x21, 0 + .dw 0x8ec0, 0xc00e, 0x8eff, 0xc00e, 0x21, 0 + .dw 0x8f40, 0xc00e, 0x8f7f, 0xc00e, 0x21, 0 + .dw 0x8fc0, 0xc00e, 0x8fff, 0xc00e, 0x21, 0 + .dw 0x9040, 0xc00e, 0x907f, 0xc00e, 0x21, 0 + .dw 0x90c0, 0xc00e, 0x90ff, 0xc00e, 0x21, 0 + .dw 0x9140, 0xc00e, 0x917f, 0xc00e, 0x21, 0 + .dw 0x91c0, 0xc00e, 0x91ff, 0xc00e, 0x21, 0 + .dw 0x9240, 0xc00e, 0x927f, 0xc00e, 0x21, 0 + .dw 0x92c0, 0xc00e, 0x92ff, 0xc00e, 0x21, 0 + .dw 0x9340, 0xc00e, 0x937f, 0xc00e, 0x21, 0 + .dw 0x93c0, 0xc00e, 0x93ff, 0xc00e, 0x21, 0 + .dw 0x9440, 0xc00e, 0x947f, 0xc00e, 0x21, 0 + .dw 0x94c0, 0xc00e, 0x94ff, 0xc00e, 0x21, 0 + .dw 0x9540, 0xc00e, 0x957f, 0xc00e, 0x21, 0 + .dw 0x95c0, 0xc00e, 0x95ff, 0xc00e, 0x21, 0 + .dw 0x9640, 0xc00e, 0x967f, 0xc00e, 0x21, 0 + .dw 0x96c0, 0xc00e, 0x96ff, 0xc00e, 0x21, 0 + .dw 0x9740, 0xc00e, 0x977f, 0xc00e, 0x21, 0 + .dw 0x97c0, 0xc00e, 0x97ff, 0xc00e, 0x21, 0 + .dw 0x9840, 0xc00e, 0x987f, 0xc00e, 0x21, 0 + .dw 0x98c0, 0xc00e, 0x98ff, 0xc00e, 0x21, 0 + .dw 0x9940, 0xc00e, 0x997f, 0xc00e, 0x21, 0 + .dw 0x99c0, 0xc00e, 0x9fff, 0xc00e, 0x21, 0 + .dw 0xa040, 0xc00e, 0xa07f, 0xc00e, 0x21, 0 + .dw 0xa0c0, 0xc00e, 0xa0ff, 0xc00e, 0x21, 0 + .dw 0xa140, 0xc00e, 0xa17f, 0xc00e, 0x21, 0 + .dw 0xa1c0, 0xc00e, 0xa1ff, 0xc00e, 0x21, 0 + .dw 0xa240, 0xc00e, 0xa27f, 0xc00e, 0x21, 0 + .dw 0xa2c0, 0xc00e, 0xa2ff, 0xc00e, 0x21, 0 + .dw 0xa340, 0xc00e, 0xa37f, 0xc00e, 0x21, 0 + .dw 0xa3c0, 0xc00e, 0xa3ff, 0xc00e, 0x21, 0 + .dw 0xa440, 0xc00e, 0xa47f, 0xc00e, 0x21, 0 + .dw 0xa4c0, 0xc00e, 0xa4ff, 0xc00e, 0x21, 0 + .dw 0xa540, 0xc00e, 0xa57f, 0xc00e, 0x21, 0 + .dw 0xa5c0, 0xc00e, 0xa5ff, 0xc00e, 0x21, 0 + .dw 0xa640, 0xc00e, 0xa67f, 0xc00e, 0x21, 0 + .dw 0xa6c0, 0xc00e, 0xa6ff, 0xc00e, 0x21, 0 + .dw 0xa740, 0xc00e, 0xa77f, 0xc00e, 0x21, 0 + .dw 0xa7c0, 0xc00e, 0xa7ff, 0xc00e, 0x21, 0 + .dw 0xa840, 0xc00e, 0xa87f, 0xc00e, 0x21, 0 + .dw 0xa8c0, 0xc00e, 0xa8ff, 0xc00e, 0x21, 0 + .dw 0xa940, 0xc00e, 0xa97f, 0xc00e, 0x21, 0 + .dw 0xa9c0, 0xc00e, 0xa9ff, 0xc00e, 0x21, 0 + .dw 0xaa40, 0xc00e, 0xaa7f, 0xc00e, 0x21, 0 + .dw 0xaac0, 0xc00e, 0xaaff, 0xc00e, 0x21, 0 + .dw 0xab40, 0xc00e, 0xab7f, 0xc00e, 0x21, 0 + .dw 0xabc0, 0xc00e, 0xabff, 0xc00e, 0x21, 0 + .dw 0xac40, 0xc00e, 0xac7f, 0xc00e, 0x21, 0 + .dw 0xacc0, 0xc00e, 0xacff, 0xc00e, 0x21, 0 + .dw 0xad40, 0xc00e, 0xad7f, 0xc00e, 0x21, 0 + .dw 0xadc0, 0xc00e, 0xadff, 0xc00e, 0x21, 0 + .dw 0xae40, 0xc00e, 0xae7f, 0xc00e, 0x21, 0 + .dw 0xaec0, 0xc00e, 0xaeff, 0xc00e, 0x21, 0 + .dw 0xaf40, 0xc00e, 0xaf7f, 0xc00e, 0x21, 0 + .dw 0xafc0, 0xc00e, 0xafff, 0xc00e, 0x21, 0 + .dw 0xb040, 0xc00e, 0xb07f, 0xc00e, 0x21, 0 + .dw 0xb0c0, 0xc00e, 0xb0ff, 0xc00e, 0x21, 0 + .dw 0xb140, 0xc00e, 0xb17f, 0xc00e, 0x21, 0 + .dw 0xb1c0, 0xc00e, 0xb1ff, 0xc00e, 0x21, 0 + .dw 0xb240, 0xc00e, 0xb27f, 0xc00e, 0x21, 0 + .dw 0xb2c0, 0xc00e, 0xb2ff, 0xc00e, 0x21, 0 + .dw 0xb340, 0xc00e, 0xb37f, 0xc00e, 0x21, 0 + .dw 0xb3c0, 0xc00e, 0xb3ff, 0xc00e, 0x21, 0 + .dw 0xb440, 0xc00e, 0xb47f, 0xc00e, 0x21, 0 + .dw 0xb4c0, 0xc00e, 0xb4ff, 0xc00e, 0x21, 0 + .dw 0xb540, 0xc00e, 0xb57f, 0xc00e, 0x21, 0 + .dw 0xb5c0, 0xc00e, 0xb5ff, 0xc00e, 0x21, 0 + .dw 0xb640, 0xc00e, 0xb67f, 0xc00e, 0x21, 0 + .dw 0xb6c0, 0xc00e, 0xb6ff, 0xc00e, 0x21, 0 + .dw 0xb740, 0xc00e, 0xb77f, 0xc00e, 0x21, 0 + .dw 0xb7c0, 0xc00e, 0xb7ff, 0xc00e, 0x21, 0 + .dw 0xb840, 0xc00e, 0xb87f, 0xc00e, 0x21, 0 + .dw 0xb8c0, 0xc00e, 0xb8ff, 0xc00e, 0x21, 0 + .dw 0xb940, 0xc00e, 0xb97f, 0xc00e, 0x21, 0 + .dw 0xb9c0, 0xc00e, 0xbfff, 0xc00e, 0x21, 0 + .dw 0xc040, 0xc00e, 0xc07f, 0xc00e, 0x21, 0 + .dw 0xc0c0, 0xc00e, 0xc0ff, 0xc00e, 0x21, 0 + .dw 0xc140, 0xc00e, 0xc17f, 0xc00e, 0x21, 0 + .dw 0xc1c0, 0xc00e, 0xc1ff, 0xc00e, 0x21, 0 + .dw 0xc240, 0xc00e, 0xc27f, 0xc00e, 0x21, 0 + .dw 0xc2c0, 0xc00e, 0xc2ff, 0xc00e, 0x21, 0 + .dw 0xc340, 0xc00e, 0xc37f, 0xc00e, 0x21, 0 + .dw 0xc3c0, 0xc00e, 0xc3ff, 0xc00e, 0x21, 0 + .dw 0xc440, 0xc00e, 0xc47f, 0xc00e, 0x21, 0 + .dw 0xc4c0, 0xc00e, 0xc4ff, 0xc00e, 0x21, 0 + .dw 0xc540, 0xc00e, 0xc57f, 0xc00e, 0x21, 0 + .dw 0xc5c0, 0xc00e, 0xc5ff, 0xc00e, 0x21, 0 + .dw 0xc640, 0xc00e, 0xc67f, 0xc00e, 0x21, 0 + .dw 0xc6c0, 0xc00e, 0xc6ff, 0xc00e, 0x21, 0 + .dw 0xc740, 0xc00e, 0xc77f, 0xc00e, 0x21, 0 + .dw 0xc7c0, 0xc00e, 0xc7ff, 0xc00e, 0x21, 0 + .dw 0xc840, 0xc00e, 0xc87f, 0xc00e, 0x21, 0 + .dw 0xc8c0, 0xc00e, 0xc8ff, 0xc00e, 0x21, 0 + .dw 0xc940, 0xc00e, 0xc97f, 0xc00e, 0x21, 0 + .dw 0xc9c0, 0xc00e, 0xc9ff, 0xc00e, 0x21, 0 + .dw 0xca40, 0xc00e, 0xca7f, 0xc00e, 0x21, 0 + .dw 0xcac0, 0xc00e, 0xcaff, 0xc00e, 0x21, 0 + .dw 0xcb40, 0xc00e, 0xcb7f, 0xc00e, 0x21, 0 + .dw 0xcbc0, 0xc00e, 0xcbff, 0xc00e, 0x21, 0 + .dw 0xcc40, 0xc00e, 0xcc7f, 0xc00e, 0x21, 0 + .dw 0xccc0, 0xc00e, 0xccff, 0xc00e, 0x21, 0 + .dw 0xcd40, 0xc00e, 0xcd7f, 0xc00e, 0x21, 0 + .dw 0xcdc0, 0xc00e, 0xcdff, 0xc00e, 0x21, 0 + .dw 0xce40, 0xc00e, 0xce7f, 0xc00e, 0x21, 0 + .dw 0xcec0, 0xc00e, 0xceff, 0xc00e, 0x21, 0 + .dw 0xcf40, 0xc00e, 0xcf7f, 0xc00e, 0x21, 0 + .dw 0xcfc0, 0xc00e, 0xcfff, 0xc00e, 0x21, 0 + .dw 0xd040, 0xc00e, 0xd07f, 0xc00e, 0x21, 0 + .dw 0xd0c0, 0xc00e, 0xd0ff, 0xc00e, 0x21, 0 + .dw 0xd140, 0xc00e, 0xd17f, 0xc00e, 0x21, 0 + .dw 0xd1c0, 0xc00e, 0xd1ff, 0xc00e, 0x21, 0 + .dw 0xd240, 0xc00e, 0xd27f, 0xc00e, 0x21, 0 + .dw 0xd2c0, 0xc00e, 0xd2ff, 0xc00e, 0x21, 0 + .dw 0xd340, 0xc00e, 0xd37f, 0xc00e, 0x21, 0 + .dw 0xd3c0, 0xc00e, 0xd3ff, 0xc00e, 0x21, 0 + .dw 0xd440, 0xc00e, 0xd47f, 0xc00e, 0x21, 0 + .dw 0xd4c0, 0xc00e, 0xd4ff, 0xc00e, 0x21, 0 + .dw 0xd540, 0xc00e, 0xd57f, 0xc00e, 0x21, 0 + .dw 0xd5c0, 0xc00e, 0xd5ff, 0xc00e, 0x21, 0 + .dw 0xd640, 0xc00e, 0xd67f, 0xc00e, 0x21, 0 + .dw 0xd6c0, 0xc00e, 0xd6ff, 0xc00e, 0x21, 0 + .dw 0xd740, 0xc00e, 0xd77f, 0xc00e, 0x21, 0 + .dw 0xd7c0, 0xc00e, 0xd7ff, 0xc00e, 0x21, 0 + .dw 0xd840, 0xc00e, 0xd87f, 0xc00e, 0x21, 0 + .dw 0xd8c0, 0xc00e, 0xd8ff, 0xc00e, 0x21, 0 + .dw 0xd940, 0xc00e, 0xd97f, 0xc00e, 0x21, 0 + .dw 0xd9c0, 0xc00e, 0xdfff, 0xc00e, 0x21, 0 + .dw 0xe040, 0xc00e, 0xe07f, 0xc00e, 0x21, 0 + .dw 0xe0c0, 0xc00e, 0xe0ff, 0xc00e, 0x21, 0 + .dw 0xe140, 0xc00e, 0xe17f, 0xc00e, 0x21, 0 + .dw 0xe1c0, 0xc00e, 0xe1ff, 0xc00e, 0x21, 0 + .dw 0xe240, 0xc00e, 0xe27f, 0xc00e, 0x21, 0 + .dw 0xe2c0, 0xc00e, 0xe2ff, 0xc00e, 0x21, 0 + .dw 0xe340, 0xc00e, 0xe37f, 0xc00e, 0x21, 0 + .dw 0xe3c0, 0xc00e, 0xe3ff, 0xc00e, 0x21, 0 + .dw 0xe440, 0xc00e, 0xe47f, 0xc00e, 0x21, 0 + .dw 0xe4c0, 0xc00e, 0xe4ff, 0xc00e, 0x21, 0 + .dw 0xe540, 0xc00e, 0xe57f, 0xc00e, 0x21, 0 + .dw 0xe5c0, 0xc00e, 0xe5ff, 0xc00e, 0x21, 0 + .dw 0xe640, 0xc00e, 0xe67f, 0xc00e, 0x21, 0 + .dw 0xe6c0, 0xc00e, 0xe6ff, 0xc00e, 0x21, 0 + .dw 0xe740, 0xc00e, 0xe77f, 0xc00e, 0x21, 0 + .dw 0xe7c0, 0xc00e, 0xe7ff, 0xc00e, 0x21, 0 + .dw 0xe840, 0xc00e, 0xe87f, 0xc00e, 0x21, 0 + .dw 0xe8c0, 0xc00e, 0xe8ff, 0xc00e, 0x21, 0 + .dw 0xe940, 0xc00e, 0xe97f, 0xc00e, 0x21, 0 + .dw 0xe9c0, 0xc00e, 0xe9ff, 0xc00e, 0x21, 0 + .dw 0xea40, 0xc00e, 0xea7f, 0xc00e, 0x21, 0 + .dw 0xeac0, 0xc00e, 0xeaff, 0xc00e, 0x21, 0 + .dw 0xeb40, 0xc00e, 0xeb7f, 0xc00e, 0x21, 0 + .dw 0xebc0, 0xc00e, 0xebff, 0xc00e, 0x21, 0 + .dw 0xec40, 0xc00e, 0xec7f, 0xc00e, 0x21, 0 + .dw 0xecc0, 0xc00e, 0xecff, 0xc00e, 0x21, 0 + .dw 0xed40, 0xc00e, 0xed7f, 0xc00e, 0x21, 0 + .dw 0xedc0, 0xc00e, 0xedff, 0xc00e, 0x21, 0 + .dw 0xee40, 0xc00e, 0xee7f, 0xc00e, 0x21, 0 + .dw 0xeec0, 0xc00e, 0xeeff, 0xc00e, 0x21, 0 + .dw 0xef40, 0xc00e, 0xef7f, 0xc00e, 0x21, 0 + .dw 0xefc0, 0xc00e, 0xefff, 0xc00e, 0x21, 0 + .dw 0xf040, 0xc00e, 0xf07f, 0xc00e, 0x21, 0 + .dw 0xf0c0, 0xc00e, 0xf0ff, 0xc00e, 0x21, 0 + .dw 0xf140, 0xc00e, 0xf17f, 0xc00e, 0x21, 0 + .dw 0xf1c0, 0xc00e, 0xf1ff, 0xc00e, 0x21, 0 + .dw 0xf240, 0xc00e, 0xf27f, 0xc00e, 0x21, 0 + .dw 0xf2c0, 0xc00e, 0xf2ff, 0xc00e, 0x21, 0 + .dw 0xf340, 0xc00e, 0xf37f, 0xc00e, 0x21, 0 + .dw 0xf3c0, 0xc00e, 0xf3ff, 0xc00e, 0x21, 0 + .dw 0xf440, 0xc00e, 0xf47f, 0xc00e, 0x21, 0 + .dw 0xf4c0, 0xc00e, 0xf4ff, 0xc00e, 0x21, 0 + .dw 0xf540, 0xc00e, 0xf57f, 0xc00e, 0x21, 0 + .dw 0xf5c0, 0xc00e, 0xf5ff, 0xc00e, 0x21, 0 + .dw 0xf640, 0xc00e, 0xf67f, 0xc00e, 0x21, 0 + .dw 0xf6c0, 0xc00e, 0xf6ff, 0xc00e, 0x21, 0 + .dw 0xf740, 0xc00e, 0xf77f, 0xc00e, 0x21, 0 + .dw 0xf7c0, 0xc00e, 0xf7ff, 0xc00e, 0x21, 0 + .dw 0xf840, 0xc00e, 0xf87f, 0xc00e, 0x21, 0 + .dw 0xf8c0, 0xc00e, 0xf8ff, 0xc00e, 0x21, 0 + .dw 0xf940, 0xc00e, 0xf97f, 0xc00e, 0x21, 0 + .dw 0xf9c0, 0xc00e, 0xffff, 0xc00e, 0x21, 0 + .dw 0x0040, 0xc00f, 0x007f, 0xc00f, 0x21, 0 + .dw 0x00c0, 0xc00f, 0x00ff, 0xc00f, 0x21, 0 + .dw 0x0140, 0xc00f, 0x017f, 0xc00f, 0x21, 0 + .dw 0x01c0, 0xc00f, 0x01ff, 0xc00f, 0x21, 0 + .dw 0x0240, 0xc00f, 0x027f, 0xc00f, 0x21, 0 + .dw 0x02c0, 0xc00f, 0x02ff, 0xc00f, 0x21, 0 + .dw 0x0340, 0xc00f, 0x037f, 0xc00f, 0x21, 0 + .dw 0x03c0, 0xc00f, 0x03ff, 0xc00f, 0x21, 0 + .dw 0x0440, 0xc00f, 0x047f, 0xc00f, 0x21, 0 + .dw 0x04c0, 0xc00f, 0x04ff, 0xc00f, 0x21, 0 + .dw 0x0540, 0xc00f, 0x057f, 0xc00f, 0x21, 0 + .dw 0x05c0, 0xc00f, 0x05ff, 0xc00f, 0x21, 0 + .dw 0x0640, 0xc00f, 0x067f, 0xc00f, 0x21, 0 + .dw 0x06c0, 0xc00f, 0x06ff, 0xc00f, 0x21, 0 + .dw 0x0740, 0xc00f, 0x077f, 0xc00f, 0x21, 0 + .dw 0x07c0, 0xc00f, 0x07ff, 0xc00f, 0x21, 0 + .dw 0x0840, 0xc00f, 0x087f, 0xc00f, 0x21, 0 + .dw 0x08c0, 0xc00f, 0x08ff, 0xc00f, 0x21, 0 + .dw 0x0940, 0xc00f, 0x097f, 0xc00f, 0x21, 0 + .dw 0x09c0, 0xc00f, 0x09ff, 0xc00f, 0x21, 0 + .dw 0x0a40, 0xc00f, 0x0a7f, 0xc00f, 0x21, 0 + .dw 0x0ac0, 0xc00f, 0x0aff, 0xc00f, 0x21, 0 + .dw 0x0b40, 0xc00f, 0x0b7f, 0xc00f, 0x21, 0 + .dw 0x0bc0, 0xc00f, 0x0bff, 0xc00f, 0x21, 0 + .dw 0x0c40, 0xc00f, 0x0c7f, 0xc00f, 0x21, 0 + .dw 0x0cc0, 0xc00f, 0x0cff, 0xc00f, 0x21, 0 + .dw 0x0d40, 0xc00f, 0x0d7f, 0xc00f, 0x21, 0 + .dw 0x0dc0, 0xc00f, 0x0dff, 0xc00f, 0x21, 0 + .dw 0x0e40, 0xc00f, 0x0e7f, 0xc00f, 0x21, 0 + .dw 0x0ec0, 0xc00f, 0x0eff, 0xc00f, 0x21, 0 + .dw 0x0f40, 0xc00f, 0x0f7f, 0xc00f, 0x21, 0 + .dw 0x0fc0, 0xc00f, 0x0fff, 0xc00f, 0x21, 0 + .dw 0x1040, 0xc00f, 0x107f, 0xc00f, 0x21, 0 + .dw 0x10c0, 0xc00f, 0x10ff, 0xc00f, 0x21, 0 + .dw 0x1140, 0xc00f, 0x117f, 0xc00f, 0x21, 0 + .dw 0x11c0, 0xc00f, 0x11ff, 0xc00f, 0x21, 0 + .dw 0x1240, 0xc00f, 0x127f, 0xc00f, 0x21, 0 + .dw 0x12c0, 0xc00f, 0x12ff, 0xc00f, 0x21, 0 + .dw 0x1340, 0xc00f, 0x137f, 0xc00f, 0x21, 0 + .dw 0x13c0, 0xc00f, 0x13ff, 0xc00f, 0x21, 0 + .dw 0x1440, 0xc00f, 0x147f, 0xc00f, 0x21, 0 + .dw 0x14c0, 0xc00f, 0x14ff, 0xc00f, 0x21, 0 + .dw 0x1540, 0xc00f, 0x157f, 0xc00f, 0x21, 0 + .dw 0x15c0, 0xc00f, 0x15ff, 0xc00f, 0x21, 0 + .dw 0x1640, 0xc00f, 0x167f, 0xc00f, 0x21, 0 + .dw 0x16c0, 0xc00f, 0x16ff, 0xc00f, 0x21, 0 + .dw 0x1740, 0xc00f, 0x177f, 0xc00f, 0x21, 0 + .dw 0x17c0, 0xc00f, 0x17ff, 0xc00f, 0x21, 0 + .dw 0x1840, 0xc00f, 0x187f, 0xc00f, 0x21, 0 + .dw 0x18c0, 0xc00f, 0x18ff, 0xc00f, 0x21, 0 + .dw 0x1940, 0xc00f, 0x197f, 0xc00f, 0x21, 0 + .dw 0x19c0, 0xc00f, 0x1fff, 0xc00f, 0x21, 0 + .dw 0x2040, 0xc00f, 0x207f, 0xc00f, 0x21, 0 + .dw 0x20c0, 0xc00f, 0x20ff, 0xc00f, 0x21, 0 + .dw 0x2140, 0xc00f, 0x217f, 0xc00f, 0x21, 0 + .dw 0x21c0, 0xc00f, 0x21ff, 0xc00f, 0x21, 0 + .dw 0x2240, 0xc00f, 0x227f, 0xc00f, 0x21, 0 + .dw 0x22c0, 0xc00f, 0x22ff, 0xc00f, 0x21, 0 + .dw 0x2340, 0xc00f, 0x237f, 0xc00f, 0x21, 0 + .dw 0x23c0, 0xc00f, 0x23ff, 0xc00f, 0x21, 0 + .dw 0x2440, 0xc00f, 0x247f, 0xc00f, 0x21, 0 + .dw 0x24c0, 0xc00f, 0x24ff, 0xc00f, 0x21, 0 + .dw 0x2540, 0xc00f, 0x257f, 0xc00f, 0x21, 0 + .dw 0x25c0, 0xc00f, 0x25ff, 0xc00f, 0x21, 0 + .dw 0x2640, 0xc00f, 0x267f, 0xc00f, 0x21, 0 + .dw 0x26c0, 0xc00f, 0x26ff, 0xc00f, 0x21, 0 + .dw 0x2740, 0xc00f, 0x277f, 0xc00f, 0x21, 0 + .dw 0x27c0, 0xc00f, 0x27ff, 0xc00f, 0x21, 0 + .dw 0x2840, 0xc00f, 0x287f, 0xc00f, 0x21, 0 + .dw 0x28c0, 0xc00f, 0x28ff, 0xc00f, 0x21, 0 + .dw 0x2940, 0xc00f, 0x297f, 0xc00f, 0x21, 0 + .dw 0x29c0, 0xc00f, 0x29ff, 0xc00f, 0x21, 0 + .dw 0x2a40, 0xc00f, 0x2a7f, 0xc00f, 0x21, 0 + .dw 0x2ac0, 0xc00f, 0x2aff, 0xc00f, 0x21, 0 + .dw 0x2b40, 0xc00f, 0x2b7f, 0xc00f, 0x21, 0 + .dw 0x2bc0, 0xc00f, 0x2bff, 0xc00f, 0x21, 0 + .dw 0x2c40, 0xc00f, 0x2c7f, 0xc00f, 0x21, 0 + .dw 0x2cc0, 0xc00f, 0x2cff, 0xc00f, 0x21, 0 + .dw 0x2d40, 0xc00f, 0x2d7f, 0xc00f, 0x21, 0 + .dw 0x2dc0, 0xc00f, 0x2dff, 0xc00f, 0x21, 0 + .dw 0x2e40, 0xc00f, 0x2e7f, 0xc00f, 0x21, 0 + .dw 0x2ec0, 0xc00f, 0x2eff, 0xc00f, 0x21, 0 + .dw 0x2f40, 0xc00f, 0x2f7f, 0xc00f, 0x21, 0 + .dw 0x2fc0, 0xc00f, 0x2fff, 0xc00f, 0x21, 0 + .dw 0x3040, 0xc00f, 0x307f, 0xc00f, 0x21, 0 + .dw 0x30c0, 0xc00f, 0x30ff, 0xc00f, 0x21, 0 + .dw 0x3140, 0xc00f, 0x317f, 0xc00f, 0x21, 0 + .dw 0x31c0, 0xc00f, 0x31ff, 0xc00f, 0x21, 0 + .dw 0x3240, 0xc00f, 0x327f, 0xc00f, 0x21, 0 + .dw 0x32c0, 0xc00f, 0x32ff, 0xc00f, 0x21, 0 + .dw 0x3340, 0xc00f, 0x337f, 0xc00f, 0x21, 0 + .dw 0x33c0, 0xc00f, 0x33ff, 0xc00f, 0x21, 0 + .dw 0x3440, 0xc00f, 0x347f, 0xc00f, 0x21, 0 + .dw 0x34c0, 0xc00f, 0x34ff, 0xc00f, 0x21, 0 + .dw 0x3540, 0xc00f, 0x357f, 0xc00f, 0x21, 0 + .dw 0x35c0, 0xc00f, 0x35ff, 0xc00f, 0x21, 0 + .dw 0x3640, 0xc00f, 0x367f, 0xc00f, 0x21, 0 + .dw 0x36c0, 0xc00f, 0x36ff, 0xc00f, 0x21, 0 + .dw 0x3740, 0xc00f, 0x377f, 0xc00f, 0x21, 0 + .dw 0x37c0, 0xc00f, 0x37ff, 0xc00f, 0x21, 0 + .dw 0x3840, 0xc00f, 0x387f, 0xc00f, 0x21, 0 + .dw 0x38c0, 0xc00f, 0x38ff, 0xc00f, 0x21, 0 + .dw 0x3940, 0xc00f, 0x397f, 0xc00f, 0x21, 0 + .dw 0x39c0, 0xc00f, 0xffff, 0xc00f, 0x21, 0 + .dw 0x1a00, 0xc010, 0x1fff, 0xc010, 0x21, 0 + .dw 0x3a00, 0xc010, 0x3fff, 0xc010, 0x21, 0 + .dw 0x5a00, 0xc010, 0x5fff, 0xc010, 0x21, 0 + .dw 0x7a00, 0xc010, 0x7fff, 0xc010, 0x21, 0 + .dw 0x9a00, 0xc010, 0x9fff, 0xc010, 0x21, 0 + .dw 0xba00, 0xc010, 0xbfff, 0xc010, 0x21, 0 + .dw 0xda00, 0xc010, 0xdfff, 0xc010, 0x21, 0 + .dw 0xfa00, 0xc010, 0xffff, 0xc010, 0x21, 0 + .dw 0x1a00, 0xc011, 0x1fff, 0xc011, 0x21, 0 + .dw 0x3a00, 0xc011, 0x3fff, 0xc011, 0x21, 0 + .dw 0x5a00, 0xc011, 0x5fff, 0xc011, 0x21, 0 + .dw 0x7a00, 0xc011, 0x7fff, 0xc011, 0x21, 0 + .dw 0x9a00, 0xc011, 0x9fff, 0xc011, 0x21, 0 + .dw 0xba00, 0xc011, 0xbfff, 0xc011, 0x21, 0 + .dw 0xda00, 0xc011, 0xdfff, 0xc011, 0x21, 0 + .dw 0xfa00, 0xc011, 0xffff, 0xc011, 0x21, 0 + .dw 0x1a00, 0xc012, 0x1fff, 0xc012, 0x21, 0 + .dw 0x3a00, 0xc012, 0x3fff, 0xc012, 0x21, 0 + .dw 0x5a00, 0xc012, 0x5fff, 0xc012, 0x21, 0 + .dw 0x7a00, 0xc012, 0x7fff, 0xc012, 0x21, 0 + .dw 0x9a00, 0xc012, 0x9fff, 0xc012, 0x21, 0 + .dw 0xba00, 0xc012, 0xbfff, 0xc012, 0x21, 0 + .dw 0xda00, 0xc012, 0xdfff, 0xc012, 0x21, 0 + .dw 0xfa00, 0xc012, 0xffff, 0xc013, 0x21, 0 + .dw 0x1a00, 0xc014, 0x1fff, 0xc014, 0x21, 0 + .dw 0x3a00, 0xc014, 0x3fff, 0xc014, 0x21, 0 + .dw 0x5a00, 0xc014, 0x5fff, 0xc014, 0x21, 0 + .dw 0x7a00, 0xc014, 0x7fff, 0xc014, 0x21, 0 + .dw 0x9a00, 0xc014, 0x9fff, 0xc014, 0x21, 0 + .dw 0xba00, 0xc014, 0xbfff, 0xc014, 0x21, 0 + .dw 0xda00, 0xc014, 0xdfff, 0xc014, 0x21, 0 + .dw 0xfa00, 0xc014, 0xffff, 0xc014, 0x21, 0 + .dw 0x1a00, 0xc015, 0x1fff, 0xc015, 0x21, 0 + .dw 0x3a00, 0xc015, 0x3fff, 0xc015, 0x21, 0 + .dw 0x5a00, 0xc015, 0x5fff, 0xc015, 0x21, 0 + .dw 0x7a00, 0xc015, 0x7fff, 0xc015, 0x21, 0 + .dw 0x9a00, 0xc015, 0x9fff, 0xc015, 0x21, 0 + .dw 0xba00, 0xc015, 0xbfff, 0xc015, 0x21, 0 + .dw 0xda00, 0xc015, 0xdfff, 0xc015, 0x21, 0 + .dw 0xfa00, 0xc015, 0xffff, 0xc015, 0x21, 0 + .dw 0x1a00, 0xc016, 0x1fff, 0xc016, 0x21, 0 + .dw 0x3a00, 0xc016, 0x3fff, 0xc016, 0x21, 0 + .dw 0x5a00, 0xc016, 0x5fff, 0xc016, 0x21, 0 + .dw 0x7a00, 0xc016, 0x7fff, 0xc016, 0x21, 0 + .dw 0x9a00, 0xc016, 0x9fff, 0xc016, 0x21, 0 + .dw 0xba00, 0xc016, 0xbfff, 0xc016, 0x21, 0 + .dw 0xda00, 0xc016, 0xdfff, 0xc016, 0x21, 0 + .dw 0xfa00, 0xc016, 0xffff, 0xc016, 0x21, 0 + .dw 0x1a00, 0xc017, 0x1fff, 0xc017, 0x21, 0 + .dw 0x3a00, 0xc017, 0x1fff, 0xc018, 0x21, 0 + .dw 0x2040, 0xc018, 0x207f, 0xc018, 0x21, 0 + .dw 0x20c0, 0xc018, 0x20ff, 0xc018, 0x21, 0 + .dw 0x2140, 0xc018, 0x217f, 0xc018, 0x21, 0 + .dw 0x21c0, 0xc018, 0x21ff, 0xc018, 0x21, 0 + .dw 0x2240, 0xc018, 0x227f, 0xc018, 0x21, 0 + .dw 0x22c0, 0xc018, 0x22ff, 0xc018, 0x21, 0 + .dw 0x2340, 0xc018, 0x237f, 0xc018, 0x21, 0 + .dw 0x23c0, 0xc018, 0x23ff, 0xc018, 0x21, 0 + .dw 0x2440, 0xc018, 0x247f, 0xc018, 0x21, 0 + .dw 0x24c0, 0xc018, 0x24ff, 0xc018, 0x21, 0 + .dw 0x2540, 0xc018, 0x257f, 0xc018, 0x21, 0 + .dw 0x25c0, 0xc018, 0x25ff, 0xc018, 0x21, 0 + .dw 0x2640, 0xc018, 0x267f, 0xc018, 0x21, 0 + .dw 0x26c0, 0xc018, 0x26ff, 0xc018, 0x21, 0 + .dw 0x2740, 0xc018, 0x277f, 0xc018, 0x21, 0 + .dw 0x27c0, 0xc018, 0x27ff, 0xc018, 0x21, 0 + .dw 0x2840, 0xc018, 0x287f, 0xc018, 0x21, 0 + .dw 0x28c0, 0xc018, 0x28ff, 0xc018, 0x21, 0 + .dw 0x2940, 0xc018, 0x297f, 0xc018, 0x21, 0 + .dw 0x29c0, 0xc018, 0x29ff, 0xc018, 0x21, 0 + .dw 0x2a40, 0xc018, 0x2a7f, 0xc018, 0x21, 0 + .dw 0x2ac0, 0xc018, 0x2aff, 0xc018, 0x21, 0 + .dw 0x2b40, 0xc018, 0x2b7f, 0xc018, 0x21, 0 + .dw 0x2bc0, 0xc018, 0x2bff, 0xc018, 0x21, 0 + .dw 0x2c40, 0xc018, 0x2c7f, 0xc018, 0x21, 0 + .dw 0x2cc0, 0xc018, 0x2cff, 0xc018, 0x21, 0 + .dw 0x2d40, 0xc018, 0x2d7f, 0xc018, 0x21, 0 + .dw 0x2dc0, 0xc018, 0x2dff, 0xc018, 0x21, 0 + .dw 0x2e40, 0xc018, 0x2e7f, 0xc018, 0x21, 0 + .dw 0x2ec0, 0xc018, 0x2eff, 0xc018, 0x21, 0 + .dw 0x2f40, 0xc018, 0x2f7f, 0xc018, 0x21, 0 + .dw 0x2fc0, 0xc018, 0x2fff, 0xc018, 0x21, 0 + .dw 0x3040, 0xc018, 0x307f, 0xc018, 0x21, 0 + .dw 0x30c0, 0xc018, 0x30ff, 0xc018, 0x21, 0 + .dw 0x3140, 0xc018, 0x317f, 0xc018, 0x21, 0 + .dw 0x31c0, 0xc018, 0x31ff, 0xc018, 0x21, 0 + .dw 0x3240, 0xc018, 0x327f, 0xc018, 0x21, 0 + .dw 0x32c0, 0xc018, 0x32ff, 0xc018, 0x21, 0 + .dw 0x3340, 0xc018, 0x337f, 0xc018, 0x21, 0 + .dw 0x33c0, 0xc018, 0x33ff, 0xc018, 0x21, 0 + .dw 0x3440, 0xc018, 0x347f, 0xc018, 0x21, 0 + .dw 0x34c0, 0xc018, 0x34ff, 0xc018, 0x21, 0 + .dw 0x3540, 0xc018, 0x357f, 0xc018, 0x21, 0 + .dw 0x35c0, 0xc018, 0x35ff, 0xc018, 0x21, 0 + .dw 0x3640, 0xc018, 0x367f, 0xc018, 0x21, 0 + .dw 0x36c0, 0xc018, 0x36ff, 0xc018, 0x21, 0 + .dw 0x3740, 0xc018, 0x377f, 0xc018, 0x21, 0 + .dw 0x37c0, 0xc018, 0x37ff, 0xc018, 0x21, 0 + .dw 0x3840, 0xc018, 0x387f, 0xc018, 0x21, 0 + .dw 0x38c0, 0xc018, 0x38ff, 0xc018, 0x21, 0 + .dw 0x3940, 0xc018, 0x397f, 0xc018, 0x21, 0 + .dw 0x39c0, 0xc018, 0x5fff, 0xc018, 0x21, 0 + .dw 0x6040, 0xc018, 0x607f, 0xc018, 0x21, 0 + .dw 0x60c0, 0xc018, 0x60ff, 0xc018, 0x21, 0 + .dw 0x6140, 0xc018, 0x617f, 0xc018, 0x21, 0 + .dw 0x61c0, 0xc018, 0x61ff, 0xc018, 0x21, 0 + .dw 0x6240, 0xc018, 0x627f, 0xc018, 0x21, 0 + .dw 0x62c0, 0xc018, 0x62ff, 0xc018, 0x21, 0 + .dw 0x6340, 0xc018, 0x637f, 0xc018, 0x21, 0 + .dw 0x63c0, 0xc018, 0x63ff, 0xc018, 0x21, 0 + .dw 0x6440, 0xc018, 0x647f, 0xc018, 0x21, 0 + .dw 0x64c0, 0xc018, 0x64ff, 0xc018, 0x21, 0 + .dw 0x6540, 0xc018, 0x657f, 0xc018, 0x21, 0 + .dw 0x65c0, 0xc018, 0x65ff, 0xc018, 0x21, 0 + .dw 0x6640, 0xc018, 0x667f, 0xc018, 0x21, 0 + .dw 0x66c0, 0xc018, 0x66ff, 0xc018, 0x21, 0 + .dw 0x6740, 0xc018, 0x677f, 0xc018, 0x21, 0 + .dw 0x67c0, 0xc018, 0x67ff, 0xc018, 0x21, 0 + .dw 0x6840, 0xc018, 0x687f, 0xc018, 0x21, 0 + .dw 0x68c0, 0xc018, 0x68ff, 0xc018, 0x21, 0 + .dw 0x6940, 0xc018, 0x697f, 0xc018, 0x21, 0 + .dw 0x69c0, 0xc018, 0x69ff, 0xc018, 0x21, 0 + .dw 0x6a40, 0xc018, 0x6a7f, 0xc018, 0x21, 0 + .dw 0x6ac0, 0xc018, 0x6aff, 0xc018, 0x21, 0 + .dw 0x6b40, 0xc018, 0x6b7f, 0xc018, 0x21, 0 + .dw 0x6bc0, 0xc018, 0x6bff, 0xc018, 0x21, 0 + .dw 0x6c40, 0xc018, 0x6c7f, 0xc018, 0x21, 0 + .dw 0x6cc0, 0xc018, 0x6cff, 0xc018, 0x21, 0 + .dw 0x6d40, 0xc018, 0x6d7f, 0xc018, 0x21, 0 + .dw 0x6dc0, 0xc018, 0x6dff, 0xc018, 0x21, 0 + .dw 0x6e40, 0xc018, 0x6e7f, 0xc018, 0x21, 0 + .dw 0x6ec0, 0xc018, 0x6eff, 0xc018, 0x21, 0 + .dw 0x6f40, 0xc018, 0x6f7f, 0xc018, 0x21, 0 + .dw 0x6fc0, 0xc018, 0x6fff, 0xc018, 0x21, 0 + .dw 0x7040, 0xc018, 0x707f, 0xc018, 0x21, 0 + .dw 0x70c0, 0xc018, 0x70ff, 0xc018, 0x21, 0 + .dw 0x7140, 0xc018, 0x717f, 0xc018, 0x21, 0 + .dw 0x71c0, 0xc018, 0x71ff, 0xc018, 0x21, 0 + .dw 0x7240, 0xc018, 0x727f, 0xc018, 0x21, 0 + .dw 0x72c0, 0xc018, 0x72ff, 0xc018, 0x21, 0 + .dw 0x7340, 0xc018, 0x737f, 0xc018, 0x21, 0 + .dw 0x73c0, 0xc018, 0x73ff, 0xc018, 0x21, 0 + .dw 0x7440, 0xc018, 0x747f, 0xc018, 0x21, 0 + .dw 0x74c0, 0xc018, 0x74ff, 0xc018, 0x21, 0 + .dw 0x7540, 0xc018, 0x757f, 0xc018, 0x21, 0 + .dw 0x75c0, 0xc018, 0x75ff, 0xc018, 0x21, 0 + .dw 0x7640, 0xc018, 0x767f, 0xc018, 0x21, 0 + .dw 0x76c0, 0xc018, 0x76ff, 0xc018, 0x21, 0 + .dw 0x7740, 0xc018, 0x777f, 0xc018, 0x21, 0 + .dw 0x77c0, 0xc018, 0x77ff, 0xc018, 0x21, 0 + .dw 0x7840, 0xc018, 0x787f, 0xc018, 0x21, 0 + .dw 0x78c0, 0xc018, 0x78ff, 0xc018, 0x21, 0 + .dw 0x7940, 0xc018, 0x797f, 0xc018, 0x21, 0 + .dw 0x79c0, 0xc018, 0x9fff, 0xc018, 0x21, 0 + .dw 0xa040, 0xc018, 0xa07f, 0xc018, 0x21, 0 + .dw 0xa0c0, 0xc018, 0xa0ff, 0xc018, 0x21, 0 + .dw 0xa140, 0xc018, 0xa17f, 0xc018, 0x21, 0 + .dw 0xa1c0, 0xc018, 0xa1ff, 0xc018, 0x21, 0 + .dw 0xa240, 0xc018, 0xa27f, 0xc018, 0x21, 0 + .dw 0xa2c0, 0xc018, 0xa2ff, 0xc018, 0x21, 0 + .dw 0xa340, 0xc018, 0xa37f, 0xc018, 0x21, 0 + .dw 0xa3c0, 0xc018, 0xa3ff, 0xc018, 0x21, 0 + .dw 0xa440, 0xc018, 0xa47f, 0xc018, 0x21, 0 + .dw 0xa4c0, 0xc018, 0xa4ff, 0xc018, 0x21, 0 + .dw 0xa540, 0xc018, 0xa57f, 0xc018, 0x21, 0 + .dw 0xa5c0, 0xc018, 0xa5ff, 0xc018, 0x21, 0 + .dw 0xa640, 0xc018, 0xa67f, 0xc018, 0x21, 0 + .dw 0xa6c0, 0xc018, 0xa6ff, 0xc018, 0x21, 0 + .dw 0xa740, 0xc018, 0xa77f, 0xc018, 0x21, 0 + .dw 0xa7c0, 0xc018, 0xa7ff, 0xc018, 0x21, 0 + .dw 0xa840, 0xc018, 0xa87f, 0xc018, 0x21, 0 + .dw 0xa8c0, 0xc018, 0xa8ff, 0xc018, 0x21, 0 + .dw 0xa940, 0xc018, 0xa97f, 0xc018, 0x21, 0 + .dw 0xa9c0, 0xc018, 0xa9ff, 0xc018, 0x21, 0 + .dw 0xaa40, 0xc018, 0xaa7f, 0xc018, 0x21, 0 + .dw 0xaac0, 0xc018, 0xaaff, 0xc018, 0x21, 0 + .dw 0xab40, 0xc018, 0xab7f, 0xc018, 0x21, 0 + .dw 0xabc0, 0xc018, 0xabff, 0xc018, 0x21, 0 + .dw 0xac40, 0xc018, 0xac7f, 0xc018, 0x21, 0 + .dw 0xacc0, 0xc018, 0xacff, 0xc018, 0x21, 0 + .dw 0xad40, 0xc018, 0xad7f, 0xc018, 0x21, 0 + .dw 0xadc0, 0xc018, 0xadff, 0xc018, 0x21, 0 + .dw 0xae40, 0xc018, 0xae7f, 0xc018, 0x21, 0 + .dw 0xaec0, 0xc018, 0xaeff, 0xc018, 0x21, 0 + .dw 0xaf40, 0xc018, 0xaf7f, 0xc018, 0x21, 0 + .dw 0xafc0, 0xc018, 0xafff, 0xc018, 0x21, 0 + .dw 0xb040, 0xc018, 0xb07f, 0xc018, 0x21, 0 + .dw 0xb0c0, 0xc018, 0xb0ff, 0xc018, 0x21, 0 + .dw 0xb140, 0xc018, 0xb17f, 0xc018, 0x21, 0 + .dw 0xb1c0, 0xc018, 0xb1ff, 0xc018, 0x21, 0 + .dw 0xb240, 0xc018, 0xb27f, 0xc018, 0x21, 0 + .dw 0xb2c0, 0xc018, 0xb2ff, 0xc018, 0x21, 0 + .dw 0xb340, 0xc018, 0xb37f, 0xc018, 0x21, 0 + .dw 0xb3c0, 0xc018, 0xb3ff, 0xc018, 0x21, 0 + .dw 0xb440, 0xc018, 0xb47f, 0xc018, 0x21, 0 + .dw 0xb4c0, 0xc018, 0xb4ff, 0xc018, 0x21, 0 + .dw 0xb540, 0xc018, 0xb57f, 0xc018, 0x21, 0 + .dw 0xb5c0, 0xc018, 0xb5ff, 0xc018, 0x21, 0 + .dw 0xb640, 0xc018, 0xb67f, 0xc018, 0x21, 0 + .dw 0xb6c0, 0xc018, 0xb6ff, 0xc018, 0x21, 0 + .dw 0xb740, 0xc018, 0xb77f, 0xc018, 0x21, 0 + .dw 0xb7c0, 0xc018, 0xb7ff, 0xc018, 0x21, 0 + .dw 0xb840, 0xc018, 0xb87f, 0xc018, 0x21, 0 + .dw 0xb8c0, 0xc018, 0xb8ff, 0xc018, 0x21, 0 + .dw 0xb940, 0xc018, 0xb97f, 0xc018, 0x21, 0 + .dw 0xb9c0, 0xc018, 0xdfff, 0xc018, 0x21, 0 + .dw 0xe040, 0xc018, 0xe07f, 0xc018, 0x21, 0 + .dw 0xe0c0, 0xc018, 0xe0ff, 0xc018, 0x21, 0 + .dw 0xe140, 0xc018, 0xe17f, 0xc018, 0x21, 0 + .dw 0xe1c0, 0xc018, 0xe1ff, 0xc018, 0x21, 0 + .dw 0xe240, 0xc018, 0xe27f, 0xc018, 0x21, 0 + .dw 0xe2c0, 0xc018, 0xe2ff, 0xc018, 0x21, 0 + .dw 0xe340, 0xc018, 0xe37f, 0xc018, 0x21, 0 + .dw 0xe3c0, 0xc018, 0xe3ff, 0xc018, 0x21, 0 + .dw 0xe440, 0xc018, 0xe47f, 0xc018, 0x21, 0 + .dw 0xe4c0, 0xc018, 0xe4ff, 0xc018, 0x21, 0 + .dw 0xe540, 0xc018, 0xe57f, 0xc018, 0x21, 0 + .dw 0xe5c0, 0xc018, 0xe5ff, 0xc018, 0x21, 0 + .dw 0xe640, 0xc018, 0xe67f, 0xc018, 0x21, 0 + .dw 0xe6c0, 0xc018, 0xe6ff, 0xc018, 0x21, 0 + .dw 0xe740, 0xc018, 0xe77f, 0xc018, 0x21, 0 + .dw 0xe7c0, 0xc018, 0xe7ff, 0xc018, 0x21, 0 + .dw 0xe840, 0xc018, 0xe87f, 0xc018, 0x21, 0 + .dw 0xe8c0, 0xc018, 0xe8ff, 0xc018, 0x21, 0 + .dw 0xe940, 0xc018, 0xe97f, 0xc018, 0x21, 0 + .dw 0xe9c0, 0xc018, 0xe9ff, 0xc018, 0x21, 0 + .dw 0xea40, 0xc018, 0xea7f, 0xc018, 0x21, 0 + .dw 0xeac0, 0xc018, 0xeaff, 0xc018, 0x21, 0 + .dw 0xeb40, 0xc018, 0xeb7f, 0xc018, 0x21, 0 + .dw 0xebc0, 0xc018, 0xebff, 0xc018, 0x21, 0 + .dw 0xec40, 0xc018, 0xec7f, 0xc018, 0x21, 0 + .dw 0xecc0, 0xc018, 0xecff, 0xc018, 0x21, 0 + .dw 0xed40, 0xc018, 0xed7f, 0xc018, 0x21, 0 + .dw 0xedc0, 0xc018, 0xedff, 0xc018, 0x21, 0 + .dw 0xee40, 0xc018, 0xee7f, 0xc018, 0x21, 0 + .dw 0xeec0, 0xc018, 0xeeff, 0xc018, 0x21, 0 + .dw 0xef40, 0xc018, 0xef7f, 0xc018, 0x21, 0 + .dw 0xefc0, 0xc018, 0xefff, 0xc018, 0x21, 0 + .dw 0xf040, 0xc018, 0xf07f, 0xc018, 0x21, 0 + .dw 0xf0c0, 0xc018, 0xf0ff, 0xc018, 0x21, 0 + .dw 0xf140, 0xc018, 0xf17f, 0xc018, 0x21, 0 + .dw 0xf1c0, 0xc018, 0xf1ff, 0xc018, 0x21, 0 + .dw 0xf240, 0xc018, 0xf27f, 0xc018, 0x21, 0 + .dw 0xf2c0, 0xc018, 0xf2ff, 0xc018, 0x21, 0 + .dw 0xf340, 0xc018, 0xf37f, 0xc018, 0x21, 0 + .dw 0xf3c0, 0xc018, 0xf3ff, 0xc018, 0x21, 0 + .dw 0xf440, 0xc018, 0xf47f, 0xc018, 0x21, 0 + .dw 0xf4c0, 0xc018, 0xf4ff, 0xc018, 0x21, 0 + .dw 0xf540, 0xc018, 0xf57f, 0xc018, 0x21, 0 + .dw 0xf5c0, 0xc018, 0xf5ff, 0xc018, 0x21, 0 + .dw 0xf640, 0xc018, 0xf67f, 0xc018, 0x21, 0 + .dw 0xf6c0, 0xc018, 0xf6ff, 0xc018, 0x21, 0 + .dw 0xf740, 0xc018, 0xf77f, 0xc018, 0x21, 0 + .dw 0xf7c0, 0xc018, 0xf7ff, 0xc018, 0x21, 0 + .dw 0xf840, 0xc018, 0xf87f, 0xc018, 0x21, 0 + .dw 0xf8c0, 0xc018, 0xf8ff, 0xc018, 0x21, 0 + .dw 0xf940, 0xc018, 0xf97f, 0xc018, 0x21, 0 + .dw 0xf9c0, 0xc018, 0x1fff, 0xc019, 0x21, 0 + .dw 0x2040, 0xc019, 0x207f, 0xc019, 0x21, 0 + .dw 0x20c0, 0xc019, 0x20ff, 0xc019, 0x21, 0 + .dw 0x2140, 0xc019, 0x217f, 0xc019, 0x21, 0 + .dw 0x21c0, 0xc019, 0x21ff, 0xc019, 0x21, 0 + .dw 0x2240, 0xc019, 0x227f, 0xc019, 0x21, 0 + .dw 0x22c0, 0xc019, 0x22ff, 0xc019, 0x21, 0 + .dw 0x2340, 0xc019, 0x237f, 0xc019, 0x21, 0 + .dw 0x23c0, 0xc019, 0x23ff, 0xc019, 0x21, 0 + .dw 0x2440, 0xc019, 0x247f, 0xc019, 0x21, 0 + .dw 0x24c0, 0xc019, 0x24ff, 0xc019, 0x21, 0 + .dw 0x2540, 0xc019, 0x257f, 0xc019, 0x21, 0 + .dw 0x25c0, 0xc019, 0x25ff, 0xc019, 0x21, 0 + .dw 0x2640, 0xc019, 0x267f, 0xc019, 0x21, 0 + .dw 0x26c0, 0xc019, 0x26ff, 0xc019, 0x21, 0 + .dw 0x2740, 0xc019, 0x277f, 0xc019, 0x21, 0 + .dw 0x27c0, 0xc019, 0x27ff, 0xc019, 0x21, 0 + .dw 0x2840, 0xc019, 0x287f, 0xc019, 0x21, 0 + .dw 0x28c0, 0xc019, 0x28ff, 0xc019, 0x21, 0 + .dw 0x2940, 0xc019, 0x297f, 0xc019, 0x21, 0 + .dw 0x29c0, 0xc019, 0x29ff, 0xc019, 0x21, 0 + .dw 0x2a40, 0xc019, 0x2a7f, 0xc019, 0x21, 0 + .dw 0x2ac0, 0xc019, 0x2aff, 0xc019, 0x21, 0 + .dw 0x2b40, 0xc019, 0x2b7f, 0xc019, 0x21, 0 + .dw 0x2bc0, 0xc019, 0x2bff, 0xc019, 0x21, 0 + .dw 0x2c40, 0xc019, 0x2c7f, 0xc019, 0x21, 0 + .dw 0x2cc0, 0xc019, 0x2cff, 0xc019, 0x21, 0 + .dw 0x2d40, 0xc019, 0x2d7f, 0xc019, 0x21, 0 + .dw 0x2dc0, 0xc019, 0x2dff, 0xc019, 0x21, 0 + .dw 0x2e40, 0xc019, 0x2e7f, 0xc019, 0x21, 0 + .dw 0x2ec0, 0xc019, 0x2eff, 0xc019, 0x21, 0 + .dw 0x2f40, 0xc019, 0x2f7f, 0xc019, 0x21, 0 + .dw 0x2fc0, 0xc019, 0x2fff, 0xc019, 0x21, 0 + .dw 0x3040, 0xc019, 0x307f, 0xc019, 0x21, 0 + .dw 0x30c0, 0xc019, 0x30ff, 0xc019, 0x21, 0 + .dw 0x3140, 0xc019, 0x317f, 0xc019, 0x21, 0 + .dw 0x31c0, 0xc019, 0x31ff, 0xc019, 0x21, 0 + .dw 0x3240, 0xc019, 0x327f, 0xc019, 0x21, 0 + .dw 0x32c0, 0xc019, 0x32ff, 0xc019, 0x21, 0 + .dw 0x3340, 0xc019, 0x337f, 0xc019, 0x21, 0 + .dw 0x33c0, 0xc019, 0x33ff, 0xc019, 0x21, 0 + .dw 0x3440, 0xc019, 0x347f, 0xc019, 0x21, 0 + .dw 0x34c0, 0xc019, 0x34ff, 0xc019, 0x21, 0 + .dw 0x3540, 0xc019, 0x357f, 0xc019, 0x21, 0 + .dw 0x35c0, 0xc019, 0x35ff, 0xc019, 0x21, 0 + .dw 0x3640, 0xc019, 0x367f, 0xc019, 0x21, 0 + .dw 0x36c0, 0xc019, 0x36ff, 0xc019, 0x21, 0 + .dw 0x3740, 0xc019, 0x377f, 0xc019, 0x21, 0 + .dw 0x37c0, 0xc019, 0x37ff, 0xc019, 0x21, 0 + .dw 0x3840, 0xc019, 0x387f, 0xc019, 0x21, 0 + .dw 0x38c0, 0xc019, 0x38ff, 0xc019, 0x21, 0 + .dw 0x3940, 0xc019, 0x397f, 0xc019, 0x21, 0 + .dw 0x39c0, 0xc019, 0x5fff, 0xc019, 0x21, 0 + .dw 0x6040, 0xc019, 0x607f, 0xc019, 0x21, 0 + .dw 0x60c0, 0xc019, 0x60ff, 0xc019, 0x21, 0 + .dw 0x6140, 0xc019, 0x617f, 0xc019, 0x21, 0 + .dw 0x61c0, 0xc019, 0x61ff, 0xc019, 0x21, 0 + .dw 0x6240, 0xc019, 0x627f, 0xc019, 0x21, 0 + .dw 0x62c0, 0xc019, 0x62ff, 0xc019, 0x21, 0 + .dw 0x6340, 0xc019, 0x637f, 0xc019, 0x21, 0 + .dw 0x63c0, 0xc019, 0x63ff, 0xc019, 0x21, 0 + .dw 0x6440, 0xc019, 0x647f, 0xc019, 0x21, 0 + .dw 0x64c0, 0xc019, 0x64ff, 0xc019, 0x21, 0 + .dw 0x6540, 0xc019, 0x657f, 0xc019, 0x21, 0 + .dw 0x65c0, 0xc019, 0x65ff, 0xc019, 0x21, 0 + .dw 0x6640, 0xc019, 0x667f, 0xc019, 0x21, 0 + .dw 0x66c0, 0xc019, 0x66ff, 0xc019, 0x21, 0 + .dw 0x6740, 0xc019, 0x677f, 0xc019, 0x21, 0 + .dw 0x67c0, 0xc019, 0x67ff, 0xc019, 0x21, 0 + .dw 0x6840, 0xc019, 0x687f, 0xc019, 0x21, 0 + .dw 0x68c0, 0xc019, 0x68ff, 0xc019, 0x21, 0 + .dw 0x6940, 0xc019, 0x697f, 0xc019, 0x21, 0 + .dw 0x69c0, 0xc019, 0x69ff, 0xc019, 0x21, 0 + .dw 0x6a40, 0xc019, 0x6a7f, 0xc019, 0x21, 0 + .dw 0x6ac0, 0xc019, 0x6aff, 0xc019, 0x21, 0 + .dw 0x6b40, 0xc019, 0x6b7f, 0xc019, 0x21, 0 + .dw 0x6bc0, 0xc019, 0x6bff, 0xc019, 0x21, 0 + .dw 0x6c40, 0xc019, 0x6c7f, 0xc019, 0x21, 0 + .dw 0x6cc0, 0xc019, 0x6cff, 0xc019, 0x21, 0 + .dw 0x6d40, 0xc019, 0x6d7f, 0xc019, 0x21, 0 + .dw 0x6dc0, 0xc019, 0x6dff, 0xc019, 0x21, 0 + .dw 0x6e40, 0xc019, 0x6e7f, 0xc019, 0x21, 0 + .dw 0x6ec0, 0xc019, 0x6eff, 0xc019, 0x21, 0 + .dw 0x6f40, 0xc019, 0x6f7f, 0xc019, 0x21, 0 + .dw 0x6fc0, 0xc019, 0x6fff, 0xc019, 0x21, 0 + .dw 0x7040, 0xc019, 0x707f, 0xc019, 0x21, 0 + .dw 0x70c0, 0xc019, 0x70ff, 0xc019, 0x21, 0 + .dw 0x7140, 0xc019, 0x717f, 0xc019, 0x21, 0 + .dw 0x71c0, 0xc019, 0x71ff, 0xc019, 0x21, 0 + .dw 0x7240, 0xc019, 0x727f, 0xc019, 0x21, 0 + .dw 0x72c0, 0xc019, 0x72ff, 0xc019, 0x21, 0 + .dw 0x7340, 0xc019, 0x737f, 0xc019, 0x21, 0 + .dw 0x73c0, 0xc019, 0x73ff, 0xc019, 0x21, 0 + .dw 0x7440, 0xc019, 0x747f, 0xc019, 0x21, 0 + .dw 0x74c0, 0xc019, 0x74ff, 0xc019, 0x21, 0 + .dw 0x7540, 0xc019, 0x757f, 0xc019, 0x21, 0 + .dw 0x75c0, 0xc019, 0x75ff, 0xc019, 0x21, 0 + .dw 0x7640, 0xc019, 0x767f, 0xc019, 0x21, 0 + .dw 0x76c0, 0xc019, 0x76ff, 0xc019, 0x21, 0 + .dw 0x7740, 0xc019, 0x777f, 0xc019, 0x21, 0 + .dw 0x77c0, 0xc019, 0x77ff, 0xc019, 0x21, 0 + .dw 0x7840, 0xc019, 0x787f, 0xc019, 0x21, 0 + .dw 0x78c0, 0xc019, 0x78ff, 0xc019, 0x21, 0 + .dw 0x7940, 0xc019, 0x797f, 0xc019, 0x21, 0 + .dw 0x79c0, 0xc019, 0x9fff, 0xc019, 0x21, 0 + .dw 0xa040, 0xc019, 0xa07f, 0xc019, 0x21, 0 + .dw 0xa0c0, 0xc019, 0xa0ff, 0xc019, 0x21, 0 + .dw 0xa140, 0xc019, 0xa17f, 0xc019, 0x21, 0 + .dw 0xa1c0, 0xc019, 0xa1ff, 0xc019, 0x21, 0 + .dw 0xa240, 0xc019, 0xa27f, 0xc019, 0x21, 0 + .dw 0xa2c0, 0xc019, 0xa2ff, 0xc019, 0x21, 0 + .dw 0xa340, 0xc019, 0xa37f, 0xc019, 0x21, 0 + .dw 0xa3c0, 0xc019, 0xa3ff, 0xc019, 0x21, 0 + .dw 0xa440, 0xc019, 0xa47f, 0xc019, 0x21, 0 + .dw 0xa4c0, 0xc019, 0xa4ff, 0xc019, 0x21, 0 + .dw 0xa540, 0xc019, 0xa57f, 0xc019, 0x21, 0 + .dw 0xa5c0, 0xc019, 0xa5ff, 0xc019, 0x21, 0 + .dw 0xa640, 0xc019, 0xa67f, 0xc019, 0x21, 0 + .dw 0xa6c0, 0xc019, 0xa6ff, 0xc019, 0x21, 0 + .dw 0xa740, 0xc019, 0xa77f, 0xc019, 0x21, 0 + .dw 0xa7c0, 0xc019, 0xa7ff, 0xc019, 0x21, 0 + .dw 0xa840, 0xc019, 0xa87f, 0xc019, 0x21, 0 + .dw 0xa8c0, 0xc019, 0xa8ff, 0xc019, 0x21, 0 + .dw 0xa940, 0xc019, 0xa97f, 0xc019, 0x21, 0 + .dw 0xa9c0, 0xc019, 0xa9ff, 0xc019, 0x21, 0 + .dw 0xaa40, 0xc019, 0xaa7f, 0xc019, 0x21, 0 + .dw 0xaac0, 0xc019, 0xaaff, 0xc019, 0x21, 0 + .dw 0xab40, 0xc019, 0xab7f, 0xc019, 0x21, 0 + .dw 0xabc0, 0xc019, 0xabff, 0xc019, 0x21, 0 + .dw 0xac40, 0xc019, 0xac7f, 0xc019, 0x21, 0 + .dw 0xacc0, 0xc019, 0xacff, 0xc019, 0x21, 0 + .dw 0xad40, 0xc019, 0xad7f, 0xc019, 0x21, 0 + .dw 0xadc0, 0xc019, 0xadff, 0xc019, 0x21, 0 + .dw 0xae40, 0xc019, 0xae7f, 0xc019, 0x21, 0 + .dw 0xaec0, 0xc019, 0xaeff, 0xc019, 0x21, 0 + .dw 0xaf40, 0xc019, 0xaf7f, 0xc019, 0x21, 0 + .dw 0xafc0, 0xc019, 0xafff, 0xc019, 0x21, 0 + .dw 0xb040, 0xc019, 0xb07f, 0xc019, 0x21, 0 + .dw 0xb0c0, 0xc019, 0xb0ff, 0xc019, 0x21, 0 + .dw 0xb140, 0xc019, 0xb17f, 0xc019, 0x21, 0 + .dw 0xb1c0, 0xc019, 0xb1ff, 0xc019, 0x21, 0 + .dw 0xb240, 0xc019, 0xb27f, 0xc019, 0x21, 0 + .dw 0xb2c0, 0xc019, 0xb2ff, 0xc019, 0x21, 0 + .dw 0xb340, 0xc019, 0xb37f, 0xc019, 0x21, 0 + .dw 0xb3c0, 0xc019, 0xb3ff, 0xc019, 0x21, 0 + .dw 0xb440, 0xc019, 0xb47f, 0xc019, 0x21, 0 + .dw 0xb4c0, 0xc019, 0xb4ff, 0xc019, 0x21, 0 + .dw 0xb540, 0xc019, 0xb57f, 0xc019, 0x21, 0 + .dw 0xb5c0, 0xc019, 0xb5ff, 0xc019, 0x21, 0 + .dw 0xb640, 0xc019, 0xb67f, 0xc019, 0x21, 0 + .dw 0xb6c0, 0xc019, 0xb6ff, 0xc019, 0x21, 0 + .dw 0xb740, 0xc019, 0xb77f, 0xc019, 0x21, 0 + .dw 0xb7c0, 0xc019, 0xb7ff, 0xc019, 0x21, 0 + .dw 0xb840, 0xc019, 0xb87f, 0xc019, 0x21, 0 + .dw 0xb8c0, 0xc019, 0xb8ff, 0xc019, 0x21, 0 + .dw 0xb940, 0xc019, 0xb97f, 0xc019, 0x21, 0 + .dw 0xb9c0, 0xc019, 0xdfff, 0xc019, 0x21, 0 + .dw 0xe040, 0xc019, 0xe07f, 0xc019, 0x21, 0 + .dw 0xe0c0, 0xc019, 0xe0ff, 0xc019, 0x21, 0 + .dw 0xe140, 0xc019, 0xe17f, 0xc019, 0x21, 0 + .dw 0xe1c0, 0xc019, 0xe1ff, 0xc019, 0x21, 0 + .dw 0xe240, 0xc019, 0xe27f, 0xc019, 0x21, 0 + .dw 0xe2c0, 0xc019, 0xe2ff, 0xc019, 0x21, 0 + .dw 0xe340, 0xc019, 0xe37f, 0xc019, 0x21, 0 + .dw 0xe3c0, 0xc019, 0xe3ff, 0xc019, 0x21, 0 + .dw 0xe440, 0xc019, 0xe47f, 0xc019, 0x21, 0 + .dw 0xe4c0, 0xc019, 0xe4ff, 0xc019, 0x21, 0 + .dw 0xe540, 0xc019, 0xe57f, 0xc019, 0x21, 0 + .dw 0xe5c0, 0xc019, 0xe5ff, 0xc019, 0x21, 0 + .dw 0xe640, 0xc019, 0xe67f, 0xc019, 0x21, 0 + .dw 0xe6c0, 0xc019, 0xe6ff, 0xc019, 0x21, 0 + .dw 0xe740, 0xc019, 0xe77f, 0xc019, 0x21, 0 + .dw 0xe7c0, 0xc019, 0xe7ff, 0xc019, 0x21, 0 + .dw 0xe840, 0xc019, 0xe87f, 0xc019, 0x21, 0 + .dw 0xe8c0, 0xc019, 0xe8ff, 0xc019, 0x21, 0 + .dw 0xe940, 0xc019, 0xe97f, 0xc019, 0x21, 0 + .dw 0xe9c0, 0xc019, 0xe9ff, 0xc019, 0x21, 0 + .dw 0xea40, 0xc019, 0xea7f, 0xc019, 0x21, 0 + .dw 0xeac0, 0xc019, 0xeaff, 0xc019, 0x21, 0 + .dw 0xeb40, 0xc019, 0xeb7f, 0xc019, 0x21, 0 + .dw 0xebc0, 0xc019, 0xebff, 0xc019, 0x21, 0 + .dw 0xec40, 0xc019, 0xec7f, 0xc019, 0x21, 0 + .dw 0xecc0, 0xc019, 0xecff, 0xc019, 0x21, 0 + .dw 0xed40, 0xc019, 0xed7f, 0xc019, 0x21, 0 + .dw 0xedc0, 0xc019, 0xedff, 0xc019, 0x21, 0 + .dw 0xee40, 0xc019, 0xee7f, 0xc019, 0x21, 0 + .dw 0xeec0, 0xc019, 0xeeff, 0xc019, 0x21, 0 + .dw 0xef40, 0xc019, 0xef7f, 0xc019, 0x21, 0 + .dw 0xefc0, 0xc019, 0xefff, 0xc019, 0x21, 0 + .dw 0xf040, 0xc019, 0xf07f, 0xc019, 0x21, 0 + .dw 0xf0c0, 0xc019, 0xf0ff, 0xc019, 0x21, 0 + .dw 0xf140, 0xc019, 0xf17f, 0xc019, 0x21, 0 + .dw 0xf1c0, 0xc019, 0xf1ff, 0xc019, 0x21, 0 + .dw 0xf240, 0xc019, 0xf27f, 0xc019, 0x21, 0 + .dw 0xf2c0, 0xc019, 0xf2ff, 0xc019, 0x21, 0 + .dw 0xf340, 0xc019, 0xf37f, 0xc019, 0x21, 0 + .dw 0xf3c0, 0xc019, 0xf3ff, 0xc019, 0x21, 0 + .dw 0xf440, 0xc019, 0xf47f, 0xc019, 0x21, 0 + .dw 0xf4c0, 0xc019, 0xf4ff, 0xc019, 0x21, 0 + .dw 0xf540, 0xc019, 0xf57f, 0xc019, 0x21, 0 + .dw 0xf5c0, 0xc019, 0xf5ff, 0xc019, 0x21, 0 + .dw 0xf640, 0xc019, 0xf67f, 0xc019, 0x21, 0 + .dw 0xf6c0, 0xc019, 0xf6ff, 0xc019, 0x21, 0 + .dw 0xf740, 0xc019, 0xf77f, 0xc019, 0x21, 0 + .dw 0xf7c0, 0xc019, 0xf7ff, 0xc019, 0x21, 0 + .dw 0xf840, 0xc019, 0xf87f, 0xc019, 0x21, 0 + .dw 0xf8c0, 0xc019, 0xf8ff, 0xc019, 0x21, 0 + .dw 0xf940, 0xc019, 0xf97f, 0xc019, 0x21, 0 + .dw 0xf9c0, 0xc019, 0x1fff, 0xc01a, 0x21, 0 + .dw 0x2040, 0xc01a, 0x207f, 0xc01a, 0x21, 0 + .dw 0x20c0, 0xc01a, 0x20ff, 0xc01a, 0x21, 0 + .dw 0x2140, 0xc01a, 0x217f, 0xc01a, 0x21, 0 + .dw 0x21c0, 0xc01a, 0x21ff, 0xc01a, 0x21, 0 + .dw 0x2240, 0xc01a, 0x227f, 0xc01a, 0x21, 0 + .dw 0x22c0, 0xc01a, 0x22ff, 0xc01a, 0x21, 0 + .dw 0x2340, 0xc01a, 0x237f, 0xc01a, 0x21, 0 + .dw 0x23c0, 0xc01a, 0x23ff, 0xc01a, 0x21, 0 + .dw 0x2440, 0xc01a, 0x247f, 0xc01a, 0x21, 0 + .dw 0x24c0, 0xc01a, 0x24ff, 0xc01a, 0x21, 0 + .dw 0x2540, 0xc01a, 0x257f, 0xc01a, 0x21, 0 + .dw 0x25c0, 0xc01a, 0x25ff, 0xc01a, 0x21, 0 + .dw 0x2640, 0xc01a, 0x267f, 0xc01a, 0x21, 0 + .dw 0x26c0, 0xc01a, 0x26ff, 0xc01a, 0x21, 0 + .dw 0x2740, 0xc01a, 0x277f, 0xc01a, 0x21, 0 + .dw 0x27c0, 0xc01a, 0x27ff, 0xc01a, 0x21, 0 + .dw 0x2840, 0xc01a, 0x287f, 0xc01a, 0x21, 0 + .dw 0x28c0, 0xc01a, 0x28ff, 0xc01a, 0x21, 0 + .dw 0x2940, 0xc01a, 0x297f, 0xc01a, 0x21, 0 + .dw 0x29c0, 0xc01a, 0x29ff, 0xc01a, 0x21, 0 + .dw 0x2a40, 0xc01a, 0x2a7f, 0xc01a, 0x21, 0 + .dw 0x2ac0, 0xc01a, 0x2aff, 0xc01a, 0x21, 0 + .dw 0x2b40, 0xc01a, 0x2b7f, 0xc01a, 0x21, 0 + .dw 0x2bc0, 0xc01a, 0x2bff, 0xc01a, 0x21, 0 + .dw 0x2c40, 0xc01a, 0x2c7f, 0xc01a, 0x21, 0 + .dw 0x2cc0, 0xc01a, 0x2cff, 0xc01a, 0x21, 0 + .dw 0x2d40, 0xc01a, 0x2d7f, 0xc01a, 0x21, 0 + .dw 0x2dc0, 0xc01a, 0x2dff, 0xc01a, 0x21, 0 + .dw 0x2e40, 0xc01a, 0x2e7f, 0xc01a, 0x21, 0 + .dw 0x2ec0, 0xc01a, 0x2eff, 0xc01a, 0x21, 0 + .dw 0x2f40, 0xc01a, 0x2f7f, 0xc01a, 0x21, 0 + .dw 0x2fc0, 0xc01a, 0x2fff, 0xc01a, 0x21, 0 + .dw 0x3040, 0xc01a, 0x307f, 0xc01a, 0x21, 0 + .dw 0x30c0, 0xc01a, 0x30ff, 0xc01a, 0x21, 0 + .dw 0x3140, 0xc01a, 0x317f, 0xc01a, 0x21, 0 + .dw 0x31c0, 0xc01a, 0x31ff, 0xc01a, 0x21, 0 + .dw 0x3240, 0xc01a, 0x327f, 0xc01a, 0x21, 0 + .dw 0x32c0, 0xc01a, 0x32ff, 0xc01a, 0x21, 0 + .dw 0x3340, 0xc01a, 0x337f, 0xc01a, 0x21, 0 + .dw 0x33c0, 0xc01a, 0x33ff, 0xc01a, 0x21, 0 + .dw 0x3440, 0xc01a, 0x347f, 0xc01a, 0x21, 0 + .dw 0x34c0, 0xc01a, 0x34ff, 0xc01a, 0x21, 0 + .dw 0x3540, 0xc01a, 0x357f, 0xc01a, 0x21, 0 + .dw 0x35c0, 0xc01a, 0x35ff, 0xc01a, 0x21, 0 + .dw 0x3640, 0xc01a, 0x367f, 0xc01a, 0x21, 0 + .dw 0x36c0, 0xc01a, 0x36ff, 0xc01a, 0x21, 0 + .dw 0x3740, 0xc01a, 0x377f, 0xc01a, 0x21, 0 + .dw 0x37c0, 0xc01a, 0x37ff, 0xc01a, 0x21, 0 + .dw 0x3840, 0xc01a, 0x387f, 0xc01a, 0x21, 0 + .dw 0x38c0, 0xc01a, 0x38ff, 0xc01a, 0x21, 0 + .dw 0x3940, 0xc01a, 0x397f, 0xc01a, 0x21, 0 + .dw 0x39c0, 0xc01a, 0x5fff, 0xc01a, 0x21, 0 + .dw 0x6040, 0xc01a, 0x607f, 0xc01a, 0x21, 0 + .dw 0x60c0, 0xc01a, 0x60ff, 0xc01a, 0x21, 0 + .dw 0x6140, 0xc01a, 0x617f, 0xc01a, 0x21, 0 + .dw 0x61c0, 0xc01a, 0x61ff, 0xc01a, 0x21, 0 + .dw 0x6240, 0xc01a, 0x627f, 0xc01a, 0x21, 0 + .dw 0x62c0, 0xc01a, 0x62ff, 0xc01a, 0x21, 0 + .dw 0x6340, 0xc01a, 0x637f, 0xc01a, 0x21, 0 + .dw 0x63c0, 0xc01a, 0x63ff, 0xc01a, 0x21, 0 + .dw 0x6440, 0xc01a, 0x647f, 0xc01a, 0x21, 0 + .dw 0x64c0, 0xc01a, 0x64ff, 0xc01a, 0x21, 0 + .dw 0x6540, 0xc01a, 0x657f, 0xc01a, 0x21, 0 + .dw 0x65c0, 0xc01a, 0x65ff, 0xc01a, 0x21, 0 + .dw 0x6640, 0xc01a, 0x667f, 0xc01a, 0x21, 0 + .dw 0x66c0, 0xc01a, 0x66ff, 0xc01a, 0x21, 0 + .dw 0x6740, 0xc01a, 0x677f, 0xc01a, 0x21, 0 + .dw 0x67c0, 0xc01a, 0x67ff, 0xc01a, 0x21, 0 + .dw 0x6840, 0xc01a, 0x687f, 0xc01a, 0x21, 0 + .dw 0x68c0, 0xc01a, 0x68ff, 0xc01a, 0x21, 0 + .dw 0x6940, 0xc01a, 0x697f, 0xc01a, 0x21, 0 + .dw 0x69c0, 0xc01a, 0x69ff, 0xc01a, 0x21, 0 + .dw 0x6a40, 0xc01a, 0x6a7f, 0xc01a, 0x21, 0 + .dw 0x6ac0, 0xc01a, 0x6aff, 0xc01a, 0x21, 0 + .dw 0x6b40, 0xc01a, 0x6b7f, 0xc01a, 0x21, 0 + .dw 0x6bc0, 0xc01a, 0x6bff, 0xc01a, 0x21, 0 + .dw 0x6c40, 0xc01a, 0x6c7f, 0xc01a, 0x21, 0 + .dw 0x6cc0, 0xc01a, 0x6cff, 0xc01a, 0x21, 0 + .dw 0x6d40, 0xc01a, 0x6d7f, 0xc01a, 0x21, 0 + .dw 0x6dc0, 0xc01a, 0x6dff, 0xc01a, 0x21, 0 + .dw 0x6e40, 0xc01a, 0x6e7f, 0xc01a, 0x21, 0 + .dw 0x6ec0, 0xc01a, 0x6eff, 0xc01a, 0x21, 0 + .dw 0x6f40, 0xc01a, 0x6f7f, 0xc01a, 0x21, 0 + .dw 0x6fc0, 0xc01a, 0x6fff, 0xc01a, 0x21, 0 + .dw 0x7040, 0xc01a, 0x707f, 0xc01a, 0x21, 0 + .dw 0x70c0, 0xc01a, 0x70ff, 0xc01a, 0x21, 0 + .dw 0x7140, 0xc01a, 0x717f, 0xc01a, 0x21, 0 + .dw 0x71c0, 0xc01a, 0x71ff, 0xc01a, 0x21, 0 + .dw 0x7240, 0xc01a, 0x727f, 0xc01a, 0x21, 0 + .dw 0x72c0, 0xc01a, 0x72ff, 0xc01a, 0x21, 0 + .dw 0x7340, 0xc01a, 0x737f, 0xc01a, 0x21, 0 + .dw 0x73c0, 0xc01a, 0x73ff, 0xc01a, 0x21, 0 + .dw 0x7440, 0xc01a, 0x747f, 0xc01a, 0x21, 0 + .dw 0x74c0, 0xc01a, 0x74ff, 0xc01a, 0x21, 0 + .dw 0x7540, 0xc01a, 0x757f, 0xc01a, 0x21, 0 + .dw 0x75c0, 0xc01a, 0x75ff, 0xc01a, 0x21, 0 + .dw 0x7640, 0xc01a, 0x767f, 0xc01a, 0x21, 0 + .dw 0x76c0, 0xc01a, 0x76ff, 0xc01a, 0x21, 0 + .dw 0x7740, 0xc01a, 0x777f, 0xc01a, 0x21, 0 + .dw 0x77c0, 0xc01a, 0x77ff, 0xc01a, 0x21, 0 + .dw 0x7840, 0xc01a, 0x787f, 0xc01a, 0x21, 0 + .dw 0x78c0, 0xc01a, 0x78ff, 0xc01a, 0x21, 0 + .dw 0x7940, 0xc01a, 0x797f, 0xc01a, 0x21, 0 + .dw 0x79c0, 0xc01a, 0x9fff, 0xc01a, 0x21, 0 + .dw 0xa040, 0xc01a, 0xa07f, 0xc01a, 0x21, 0 + .dw 0xa0c0, 0xc01a, 0xa0ff, 0xc01a, 0x21, 0 + .dw 0xa140, 0xc01a, 0xa17f, 0xc01a, 0x21, 0 + .dw 0xa1c0, 0xc01a, 0xa1ff, 0xc01a, 0x21, 0 + .dw 0xa240, 0xc01a, 0xa27f, 0xc01a, 0x21, 0 + .dw 0xa2c0, 0xc01a, 0xa2ff, 0xc01a, 0x21, 0 + .dw 0xa340, 0xc01a, 0xa37f, 0xc01a, 0x21, 0 + .dw 0xa3c0, 0xc01a, 0xa3ff, 0xc01a, 0x21, 0 + .dw 0xa440, 0xc01a, 0xa47f, 0xc01a, 0x21, 0 + .dw 0xa4c0, 0xc01a, 0xa4ff, 0xc01a, 0x21, 0 + .dw 0xa540, 0xc01a, 0xa57f, 0xc01a, 0x21, 0 + .dw 0xa5c0, 0xc01a, 0xa5ff, 0xc01a, 0x21, 0 + .dw 0xa640, 0xc01a, 0xa67f, 0xc01a, 0x21, 0 + .dw 0xa6c0, 0xc01a, 0xa6ff, 0xc01a, 0x21, 0 + .dw 0xa740, 0xc01a, 0xa77f, 0xc01a, 0x21, 0 + .dw 0xa7c0, 0xc01a, 0xa7ff, 0xc01a, 0x21, 0 + .dw 0xa840, 0xc01a, 0xa87f, 0xc01a, 0x21, 0 + .dw 0xa8c0, 0xc01a, 0xa8ff, 0xc01a, 0x21, 0 + .dw 0xa940, 0xc01a, 0xa97f, 0xc01a, 0x21, 0 + .dw 0xa9c0, 0xc01a, 0xa9ff, 0xc01a, 0x21, 0 + .dw 0xaa40, 0xc01a, 0xaa7f, 0xc01a, 0x21, 0 + .dw 0xaac0, 0xc01a, 0xaaff, 0xc01a, 0x21, 0 + .dw 0xab40, 0xc01a, 0xab7f, 0xc01a, 0x21, 0 + .dw 0xabc0, 0xc01a, 0xabff, 0xc01a, 0x21, 0 + .dw 0xac40, 0xc01a, 0xac7f, 0xc01a, 0x21, 0 + .dw 0xacc0, 0xc01a, 0xacff, 0xc01a, 0x21, 0 + .dw 0xad40, 0xc01a, 0xad7f, 0xc01a, 0x21, 0 + .dw 0xadc0, 0xc01a, 0xadff, 0xc01a, 0x21, 0 + .dw 0xae40, 0xc01a, 0xae7f, 0xc01a, 0x21, 0 + .dw 0xaec0, 0xc01a, 0xaeff, 0xc01a, 0x21, 0 + .dw 0xaf40, 0xc01a, 0xaf7f, 0xc01a, 0x21, 0 + .dw 0xafc0, 0xc01a, 0xafff, 0xc01a, 0x21, 0 + .dw 0xb040, 0xc01a, 0xb07f, 0xc01a, 0x21, 0 + .dw 0xb0c0, 0xc01a, 0xb0ff, 0xc01a, 0x21, 0 + .dw 0xb140, 0xc01a, 0xb17f, 0xc01a, 0x21, 0 + .dw 0xb1c0, 0xc01a, 0xb1ff, 0xc01a, 0x21, 0 + .dw 0xb240, 0xc01a, 0xb27f, 0xc01a, 0x21, 0 + .dw 0xb2c0, 0xc01a, 0xb2ff, 0xc01a, 0x21, 0 + .dw 0xb340, 0xc01a, 0xb37f, 0xc01a, 0x21, 0 + .dw 0xb3c0, 0xc01a, 0xb3ff, 0xc01a, 0x21, 0 + .dw 0xb440, 0xc01a, 0xb47f, 0xc01a, 0x21, 0 + .dw 0xb4c0, 0xc01a, 0xb4ff, 0xc01a, 0x21, 0 + .dw 0xb540, 0xc01a, 0xb57f, 0xc01a, 0x21, 0 + .dw 0xb5c0, 0xc01a, 0xb5ff, 0xc01a, 0x21, 0 + .dw 0xb640, 0xc01a, 0xb67f, 0xc01a, 0x21, 0 + .dw 0xb6c0, 0xc01a, 0xb6ff, 0xc01a, 0x21, 0 + .dw 0xb740, 0xc01a, 0xb77f, 0xc01a, 0x21, 0 + .dw 0xb7c0, 0xc01a, 0xb7ff, 0xc01a, 0x21, 0 + .dw 0xb840, 0xc01a, 0xb87f, 0xc01a, 0x21, 0 + .dw 0xb8c0, 0xc01a, 0xb8ff, 0xc01a, 0x21, 0 + .dw 0xb940, 0xc01a, 0xb97f, 0xc01a, 0x21, 0 + .dw 0xb9c0, 0xc01a, 0xdfff, 0xc01a, 0x21, 0 + .dw 0xe040, 0xc01a, 0xe07f, 0xc01a, 0x21, 0 + .dw 0xe0c0, 0xc01a, 0xe0ff, 0xc01a, 0x21, 0 + .dw 0xe140, 0xc01a, 0xe17f, 0xc01a, 0x21, 0 + .dw 0xe1c0, 0xc01a, 0xe1ff, 0xc01a, 0x21, 0 + .dw 0xe240, 0xc01a, 0xe27f, 0xc01a, 0x21, 0 + .dw 0xe2c0, 0xc01a, 0xe2ff, 0xc01a, 0x21, 0 + .dw 0xe340, 0xc01a, 0xe37f, 0xc01a, 0x21, 0 + .dw 0xe3c0, 0xc01a, 0xe3ff, 0xc01a, 0x21, 0 + .dw 0xe440, 0xc01a, 0xe47f, 0xc01a, 0x21, 0 + .dw 0xe4c0, 0xc01a, 0xe4ff, 0xc01a, 0x21, 0 + .dw 0xe540, 0xc01a, 0xe57f, 0xc01a, 0x21, 0 + .dw 0xe5c0, 0xc01a, 0xe5ff, 0xc01a, 0x21, 0 + .dw 0xe640, 0xc01a, 0xe67f, 0xc01a, 0x21, 0 + .dw 0xe6c0, 0xc01a, 0xe6ff, 0xc01a, 0x21, 0 + .dw 0xe740, 0xc01a, 0xe77f, 0xc01a, 0x21, 0 + .dw 0xe7c0, 0xc01a, 0xe7ff, 0xc01a, 0x21, 0 + .dw 0xe840, 0xc01a, 0xe87f, 0xc01a, 0x21, 0 + .dw 0xe8c0, 0xc01a, 0xe8ff, 0xc01a, 0x21, 0 + .dw 0xe940, 0xc01a, 0xe97f, 0xc01a, 0x21, 0 + .dw 0xe9c0, 0xc01a, 0xe9ff, 0xc01a, 0x21, 0 + .dw 0xea40, 0xc01a, 0xea7f, 0xc01a, 0x21, 0 + .dw 0xeac0, 0xc01a, 0xeaff, 0xc01a, 0x21, 0 + .dw 0xeb40, 0xc01a, 0xeb7f, 0xc01a, 0x21, 0 + .dw 0xebc0, 0xc01a, 0xebff, 0xc01a, 0x21, 0 + .dw 0xec40, 0xc01a, 0xec7f, 0xc01a, 0x21, 0 + .dw 0xecc0, 0xc01a, 0xecff, 0xc01a, 0x21, 0 + .dw 0xed40, 0xc01a, 0xed7f, 0xc01a, 0x21, 0 + .dw 0xedc0, 0xc01a, 0xedff, 0xc01a, 0x21, 0 + .dw 0xee40, 0xc01a, 0xee7f, 0xc01a, 0x21, 0 + .dw 0xeec0, 0xc01a, 0xeeff, 0xc01a, 0x21, 0 + .dw 0xef40, 0xc01a, 0xef7f, 0xc01a, 0x21, 0 + .dw 0xefc0, 0xc01a, 0xefff, 0xc01a, 0x21, 0 + .dw 0xf040, 0xc01a, 0xf07f, 0xc01a, 0x21, 0 + .dw 0xf0c0, 0xc01a, 0xf0ff, 0xc01a, 0x21, 0 + .dw 0xf140, 0xc01a, 0xf17f, 0xc01a, 0x21, 0 + .dw 0xf1c0, 0xc01a, 0xf1ff, 0xc01a, 0x21, 0 + .dw 0xf240, 0xc01a, 0xf27f, 0xc01a, 0x21, 0 + .dw 0xf2c0, 0xc01a, 0xf2ff, 0xc01a, 0x21, 0 + .dw 0xf340, 0xc01a, 0xf37f, 0xc01a, 0x21, 0 + .dw 0xf3c0, 0xc01a, 0xf3ff, 0xc01a, 0x21, 0 + .dw 0xf440, 0xc01a, 0xf47f, 0xc01a, 0x21, 0 + .dw 0xf4c0, 0xc01a, 0xf4ff, 0xc01a, 0x21, 0 + .dw 0xf540, 0xc01a, 0xf57f, 0xc01a, 0x21, 0 + .dw 0xf5c0, 0xc01a, 0xf5ff, 0xc01a, 0x21, 0 + .dw 0xf640, 0xc01a, 0xf67f, 0xc01a, 0x21, 0 + .dw 0xf6c0, 0xc01a, 0xf6ff, 0xc01a, 0x21, 0 + .dw 0xf740, 0xc01a, 0xf77f, 0xc01a, 0x21, 0 + .dw 0xf7c0, 0xc01a, 0xf7ff, 0xc01a, 0x21, 0 + .dw 0xf840, 0xc01a, 0xf87f, 0xc01a, 0x21, 0 + .dw 0xf8c0, 0xc01a, 0xf8ff, 0xc01a, 0x21, 0 + .dw 0xf940, 0xc01a, 0xf97f, 0xc01a, 0x21, 0 + .dw 0xf9c0, 0xc01a, 0xffff, 0xc01b, 0x21, 0 + .dw 0x0040, 0xc01c, 0x007f, 0xc01c, 0x21, 0 + .dw 0x00c0, 0xc01c, 0x00ff, 0xc01c, 0x21, 0 + .dw 0x0140, 0xc01c, 0x017f, 0xc01c, 0x21, 0 + .dw 0x01c0, 0xc01c, 0x01ff, 0xc01c, 0x21, 0 + .dw 0x0240, 0xc01c, 0x027f, 0xc01c, 0x21, 0 + .dw 0x02c0, 0xc01c, 0x02ff, 0xc01c, 0x21, 0 + .dw 0x0340, 0xc01c, 0x037f, 0xc01c, 0x21, 0 + .dw 0x03c0, 0xc01c, 0x03ff, 0xc01c, 0x21, 0 + .dw 0x0440, 0xc01c, 0x047f, 0xc01c, 0x21, 0 + .dw 0x04c0, 0xc01c, 0x04ff, 0xc01c, 0x21, 0 + .dw 0x0540, 0xc01c, 0x057f, 0xc01c, 0x21, 0 + .dw 0x05c0, 0xc01c, 0x05ff, 0xc01c, 0x21, 0 + .dw 0x0640, 0xc01c, 0x067f, 0xc01c, 0x21, 0 + .dw 0x06c0, 0xc01c, 0x06ff, 0xc01c, 0x21, 0 + .dw 0x0740, 0xc01c, 0x077f, 0xc01c, 0x21, 0 + .dw 0x07c0, 0xc01c, 0x07ff, 0xc01c, 0x21, 0 + .dw 0x0840, 0xc01c, 0x087f, 0xc01c, 0x21, 0 + .dw 0x08c0, 0xc01c, 0x08ff, 0xc01c, 0x21, 0 + .dw 0x0940, 0xc01c, 0x097f, 0xc01c, 0x21, 0 + .dw 0x09c0, 0xc01c, 0x09ff, 0xc01c, 0x21, 0 + .dw 0x0a40, 0xc01c, 0x0a7f, 0xc01c, 0x21, 0 + .dw 0x0ac0, 0xc01c, 0x0aff, 0xc01c, 0x21, 0 + .dw 0x0b40, 0xc01c, 0x0b7f, 0xc01c, 0x21, 0 + .dw 0x0bc0, 0xc01c, 0x0bff, 0xc01c, 0x21, 0 + .dw 0x0c40, 0xc01c, 0x0c7f, 0xc01c, 0x21, 0 + .dw 0x0cc0, 0xc01c, 0x0cff, 0xc01c, 0x21, 0 + .dw 0x0d40, 0xc01c, 0x0d7f, 0xc01c, 0x21, 0 + .dw 0x0dc0, 0xc01c, 0x0dff, 0xc01c, 0x21, 0 + .dw 0x0e40, 0xc01c, 0x0e7f, 0xc01c, 0x21, 0 + .dw 0x0ec0, 0xc01c, 0x0eff, 0xc01c, 0x21, 0 + .dw 0x0f40, 0xc01c, 0x0f7f, 0xc01c, 0x21, 0 + .dw 0x0fc0, 0xc01c, 0x0fff, 0xc01c, 0x21, 0 + .dw 0x1040, 0xc01c, 0x107f, 0xc01c, 0x21, 0 + .dw 0x10c0, 0xc01c, 0x10ff, 0xc01c, 0x21, 0 + .dw 0x1140, 0xc01c, 0x117f, 0xc01c, 0x21, 0 + .dw 0x11c0, 0xc01c, 0x11ff, 0xc01c, 0x21, 0 + .dw 0x1240, 0xc01c, 0x127f, 0xc01c, 0x21, 0 + .dw 0x12c0, 0xc01c, 0x12ff, 0xc01c, 0x21, 0 + .dw 0x1340, 0xc01c, 0x137f, 0xc01c, 0x21, 0 + .dw 0x13c0, 0xc01c, 0x13ff, 0xc01c, 0x21, 0 + .dw 0x1440, 0xc01c, 0x147f, 0xc01c, 0x21, 0 + .dw 0x14c0, 0xc01c, 0x14ff, 0xc01c, 0x21, 0 + .dw 0x1540, 0xc01c, 0x157f, 0xc01c, 0x21, 0 + .dw 0x15c0, 0xc01c, 0x15ff, 0xc01c, 0x21, 0 + .dw 0x1640, 0xc01c, 0x167f, 0xc01c, 0x21, 0 + .dw 0x16c0, 0xc01c, 0x16ff, 0xc01c, 0x21, 0 + .dw 0x1740, 0xc01c, 0x177f, 0xc01c, 0x21, 0 + .dw 0x17c0, 0xc01c, 0x17ff, 0xc01c, 0x21, 0 + .dw 0x1840, 0xc01c, 0x187f, 0xc01c, 0x21, 0 + .dw 0x18c0, 0xc01c, 0x18ff, 0xc01c, 0x21, 0 + .dw 0x1940, 0xc01c, 0x197f, 0xc01c, 0x21, 0 + .dw 0x19c0, 0xc01c, 0x1fff, 0xc01c, 0x21, 0 + .dw 0x2040, 0xc01c, 0x207f, 0xc01c, 0x21, 0 + .dw 0x20c0, 0xc01c, 0x20ff, 0xc01c, 0x21, 0 + .dw 0x2140, 0xc01c, 0x217f, 0xc01c, 0x21, 0 + .dw 0x21c0, 0xc01c, 0x21ff, 0xc01c, 0x21, 0 + .dw 0x2240, 0xc01c, 0x227f, 0xc01c, 0x21, 0 + .dw 0x22c0, 0xc01c, 0x22ff, 0xc01c, 0x21, 0 + .dw 0x2340, 0xc01c, 0x237f, 0xc01c, 0x21, 0 + .dw 0x23c0, 0xc01c, 0x23ff, 0xc01c, 0x21, 0 + .dw 0x2440, 0xc01c, 0x247f, 0xc01c, 0x21, 0 + .dw 0x24c0, 0xc01c, 0x24ff, 0xc01c, 0x21, 0 + .dw 0x2540, 0xc01c, 0x257f, 0xc01c, 0x21, 0 + .dw 0x25c0, 0xc01c, 0x25ff, 0xc01c, 0x21, 0 + .dw 0x2640, 0xc01c, 0x267f, 0xc01c, 0x21, 0 + .dw 0x26c0, 0xc01c, 0x26ff, 0xc01c, 0x21, 0 + .dw 0x2740, 0xc01c, 0x277f, 0xc01c, 0x21, 0 + .dw 0x27c0, 0xc01c, 0x27ff, 0xc01c, 0x21, 0 + .dw 0x2840, 0xc01c, 0x287f, 0xc01c, 0x21, 0 + .dw 0x28c0, 0xc01c, 0x28ff, 0xc01c, 0x21, 0 + .dw 0x2940, 0xc01c, 0x297f, 0xc01c, 0x21, 0 + .dw 0x29c0, 0xc01c, 0x29ff, 0xc01c, 0x21, 0 + .dw 0x2a40, 0xc01c, 0x2a7f, 0xc01c, 0x21, 0 + .dw 0x2ac0, 0xc01c, 0x2aff, 0xc01c, 0x21, 0 + .dw 0x2b40, 0xc01c, 0x2b7f, 0xc01c, 0x21, 0 + .dw 0x2bc0, 0xc01c, 0x2bff, 0xc01c, 0x21, 0 + .dw 0x2c40, 0xc01c, 0x2c7f, 0xc01c, 0x21, 0 + .dw 0x2cc0, 0xc01c, 0x2cff, 0xc01c, 0x21, 0 + .dw 0x2d40, 0xc01c, 0x2d7f, 0xc01c, 0x21, 0 + .dw 0x2dc0, 0xc01c, 0x2dff, 0xc01c, 0x21, 0 + .dw 0x2e40, 0xc01c, 0x2e7f, 0xc01c, 0x21, 0 + .dw 0x2ec0, 0xc01c, 0x2eff, 0xc01c, 0x21, 0 + .dw 0x2f40, 0xc01c, 0x2f7f, 0xc01c, 0x21, 0 + .dw 0x2fc0, 0xc01c, 0x2fff, 0xc01c, 0x21, 0 + .dw 0x3040, 0xc01c, 0x307f, 0xc01c, 0x21, 0 + .dw 0x30c0, 0xc01c, 0x30ff, 0xc01c, 0x21, 0 + .dw 0x3140, 0xc01c, 0x317f, 0xc01c, 0x21, 0 + .dw 0x31c0, 0xc01c, 0x31ff, 0xc01c, 0x21, 0 + .dw 0x3240, 0xc01c, 0x327f, 0xc01c, 0x21, 0 + .dw 0x32c0, 0xc01c, 0x32ff, 0xc01c, 0x21, 0 + .dw 0x3340, 0xc01c, 0x337f, 0xc01c, 0x21, 0 + .dw 0x33c0, 0xc01c, 0x33ff, 0xc01c, 0x21, 0 + .dw 0x3440, 0xc01c, 0x347f, 0xc01c, 0x21, 0 + .dw 0x34c0, 0xc01c, 0x34ff, 0xc01c, 0x21, 0 + .dw 0x3540, 0xc01c, 0x357f, 0xc01c, 0x21, 0 + .dw 0x35c0, 0xc01c, 0x35ff, 0xc01c, 0x21, 0 + .dw 0x3640, 0xc01c, 0x367f, 0xc01c, 0x21, 0 + .dw 0x36c0, 0xc01c, 0x36ff, 0xc01c, 0x21, 0 + .dw 0x3740, 0xc01c, 0x377f, 0xc01c, 0x21, 0 + .dw 0x37c0, 0xc01c, 0x37ff, 0xc01c, 0x21, 0 + .dw 0x3840, 0xc01c, 0x387f, 0xc01c, 0x21, 0 + .dw 0x38c0, 0xc01c, 0x38ff, 0xc01c, 0x21, 0 + .dw 0x3940, 0xc01c, 0x397f, 0xc01c, 0x21, 0 + .dw 0x39c0, 0xc01c, 0x3fff, 0xc01c, 0x21, 0 + .dw 0x4040, 0xc01c, 0x407f, 0xc01c, 0x21, 0 + .dw 0x40c0, 0xc01c, 0x40ff, 0xc01c, 0x21, 0 + .dw 0x4140, 0xc01c, 0x417f, 0xc01c, 0x21, 0 + .dw 0x41c0, 0xc01c, 0x41ff, 0xc01c, 0x21, 0 + .dw 0x4240, 0xc01c, 0x427f, 0xc01c, 0x21, 0 + .dw 0x42c0, 0xc01c, 0x42ff, 0xc01c, 0x21, 0 + .dw 0x4340, 0xc01c, 0x437f, 0xc01c, 0x21, 0 + .dw 0x43c0, 0xc01c, 0x43ff, 0xc01c, 0x21, 0 + .dw 0x4440, 0xc01c, 0x447f, 0xc01c, 0x21, 0 + .dw 0x44c0, 0xc01c, 0x44ff, 0xc01c, 0x21, 0 + .dw 0x4540, 0xc01c, 0x457f, 0xc01c, 0x21, 0 + .dw 0x45c0, 0xc01c, 0x45ff, 0xc01c, 0x21, 0 + .dw 0x4640, 0xc01c, 0x467f, 0xc01c, 0x21, 0 + .dw 0x46c0, 0xc01c, 0x46ff, 0xc01c, 0x21, 0 + .dw 0x4740, 0xc01c, 0x477f, 0xc01c, 0x21, 0 + .dw 0x47c0, 0xc01c, 0x47ff, 0xc01c, 0x21, 0 + .dw 0x4840, 0xc01c, 0x487f, 0xc01c, 0x21, 0 + .dw 0x48c0, 0xc01c, 0x48ff, 0xc01c, 0x21, 0 + .dw 0x4940, 0xc01c, 0x497f, 0xc01c, 0x21, 0 + .dw 0x49c0, 0xc01c, 0x49ff, 0xc01c, 0x21, 0 + .dw 0x4a40, 0xc01c, 0x4a7f, 0xc01c, 0x21, 0 + .dw 0x4ac0, 0xc01c, 0x4aff, 0xc01c, 0x21, 0 + .dw 0x4b40, 0xc01c, 0x4b7f, 0xc01c, 0x21, 0 + .dw 0x4bc0, 0xc01c, 0x4bff, 0xc01c, 0x21, 0 + .dw 0x4c40, 0xc01c, 0x4c7f, 0xc01c, 0x21, 0 + .dw 0x4cc0, 0xc01c, 0x4cff, 0xc01c, 0x21, 0 + .dw 0x4d40, 0xc01c, 0x4d7f, 0xc01c, 0x21, 0 + .dw 0x4dc0, 0xc01c, 0x4dff, 0xc01c, 0x21, 0 + .dw 0x4e40, 0xc01c, 0x4e7f, 0xc01c, 0x21, 0 + .dw 0x4ec0, 0xc01c, 0x4eff, 0xc01c, 0x21, 0 + .dw 0x4f40, 0xc01c, 0x4f7f, 0xc01c, 0x21, 0 + .dw 0x4fc0, 0xc01c, 0x4fff, 0xc01c, 0x21, 0 + .dw 0x5040, 0xc01c, 0x507f, 0xc01c, 0x21, 0 + .dw 0x50c0, 0xc01c, 0x50ff, 0xc01c, 0x21, 0 + .dw 0x5140, 0xc01c, 0x517f, 0xc01c, 0x21, 0 + .dw 0x51c0, 0xc01c, 0x51ff, 0xc01c, 0x21, 0 + .dw 0x5240, 0xc01c, 0x527f, 0xc01c, 0x21, 0 + .dw 0x52c0, 0xc01c, 0x52ff, 0xc01c, 0x21, 0 + .dw 0x5340, 0xc01c, 0x537f, 0xc01c, 0x21, 0 + .dw 0x53c0, 0xc01c, 0x53ff, 0xc01c, 0x21, 0 + .dw 0x5440, 0xc01c, 0x547f, 0xc01c, 0x21, 0 + .dw 0x54c0, 0xc01c, 0x54ff, 0xc01c, 0x21, 0 + .dw 0x5540, 0xc01c, 0x557f, 0xc01c, 0x21, 0 + .dw 0x55c0, 0xc01c, 0x55ff, 0xc01c, 0x21, 0 + .dw 0x5640, 0xc01c, 0x567f, 0xc01c, 0x21, 0 + .dw 0x56c0, 0xc01c, 0x56ff, 0xc01c, 0x21, 0 + .dw 0x5740, 0xc01c, 0x577f, 0xc01c, 0x21, 0 + .dw 0x57c0, 0xc01c, 0x57ff, 0xc01c, 0x21, 0 + .dw 0x5840, 0xc01c, 0x587f, 0xc01c, 0x21, 0 + .dw 0x58c0, 0xc01c, 0x58ff, 0xc01c, 0x21, 0 + .dw 0x5940, 0xc01c, 0x597f, 0xc01c, 0x21, 0 + .dw 0x59c0, 0xc01c, 0x5fff, 0xc01c, 0x21, 0 + .dw 0x6040, 0xc01c, 0x607f, 0xc01c, 0x21, 0 + .dw 0x60c0, 0xc01c, 0x60ff, 0xc01c, 0x21, 0 + .dw 0x6140, 0xc01c, 0x617f, 0xc01c, 0x21, 0 + .dw 0x61c0, 0xc01c, 0x61ff, 0xc01c, 0x21, 0 + .dw 0x6240, 0xc01c, 0x627f, 0xc01c, 0x21, 0 + .dw 0x62c0, 0xc01c, 0x62ff, 0xc01c, 0x21, 0 + .dw 0x6340, 0xc01c, 0x637f, 0xc01c, 0x21, 0 + .dw 0x63c0, 0xc01c, 0x63ff, 0xc01c, 0x21, 0 + .dw 0x6440, 0xc01c, 0x647f, 0xc01c, 0x21, 0 + .dw 0x64c0, 0xc01c, 0x64ff, 0xc01c, 0x21, 0 + .dw 0x6540, 0xc01c, 0x657f, 0xc01c, 0x21, 0 + .dw 0x65c0, 0xc01c, 0x65ff, 0xc01c, 0x21, 0 + .dw 0x6640, 0xc01c, 0x667f, 0xc01c, 0x21, 0 + .dw 0x66c0, 0xc01c, 0x66ff, 0xc01c, 0x21, 0 + .dw 0x6740, 0xc01c, 0x677f, 0xc01c, 0x21, 0 + .dw 0x67c0, 0xc01c, 0x67ff, 0xc01c, 0x21, 0 + .dw 0x6840, 0xc01c, 0x687f, 0xc01c, 0x21, 0 + .dw 0x68c0, 0xc01c, 0x68ff, 0xc01c, 0x21, 0 + .dw 0x6940, 0xc01c, 0x697f, 0xc01c, 0x21, 0 + .dw 0x69c0, 0xc01c, 0x69ff, 0xc01c, 0x21, 0 + .dw 0x6a40, 0xc01c, 0x6a7f, 0xc01c, 0x21, 0 + .dw 0x6ac0, 0xc01c, 0x6aff, 0xc01c, 0x21, 0 + .dw 0x6b40, 0xc01c, 0x6b7f, 0xc01c, 0x21, 0 + .dw 0x6bc0, 0xc01c, 0x6bff, 0xc01c, 0x21, 0 + .dw 0x6c40, 0xc01c, 0x6c7f, 0xc01c, 0x21, 0 + .dw 0x6cc0, 0xc01c, 0x6cff, 0xc01c, 0x21, 0 + .dw 0x6d40, 0xc01c, 0x6d7f, 0xc01c, 0x21, 0 + .dw 0x6dc0, 0xc01c, 0x6dff, 0xc01c, 0x21, 0 + .dw 0x6e40, 0xc01c, 0x6e7f, 0xc01c, 0x21, 0 + .dw 0x6ec0, 0xc01c, 0x6eff, 0xc01c, 0x21, 0 + .dw 0x6f40, 0xc01c, 0x6f7f, 0xc01c, 0x21, 0 + .dw 0x6fc0, 0xc01c, 0x6fff, 0xc01c, 0x21, 0 + .dw 0x7040, 0xc01c, 0x707f, 0xc01c, 0x21, 0 + .dw 0x70c0, 0xc01c, 0x70ff, 0xc01c, 0x21, 0 + .dw 0x7140, 0xc01c, 0x717f, 0xc01c, 0x21, 0 + .dw 0x71c0, 0xc01c, 0x71ff, 0xc01c, 0x21, 0 + .dw 0x7240, 0xc01c, 0x727f, 0xc01c, 0x21, 0 + .dw 0x72c0, 0xc01c, 0x72ff, 0xc01c, 0x21, 0 + .dw 0x7340, 0xc01c, 0x737f, 0xc01c, 0x21, 0 + .dw 0x73c0, 0xc01c, 0x73ff, 0xc01c, 0x21, 0 + .dw 0x7440, 0xc01c, 0x747f, 0xc01c, 0x21, 0 + .dw 0x74c0, 0xc01c, 0x74ff, 0xc01c, 0x21, 0 + .dw 0x7540, 0xc01c, 0x757f, 0xc01c, 0x21, 0 + .dw 0x75c0, 0xc01c, 0x75ff, 0xc01c, 0x21, 0 + .dw 0x7640, 0xc01c, 0x767f, 0xc01c, 0x21, 0 + .dw 0x76c0, 0xc01c, 0x76ff, 0xc01c, 0x21, 0 + .dw 0x7740, 0xc01c, 0x777f, 0xc01c, 0x21, 0 + .dw 0x77c0, 0xc01c, 0x77ff, 0xc01c, 0x21, 0 + .dw 0x7840, 0xc01c, 0x787f, 0xc01c, 0x21, 0 + .dw 0x78c0, 0xc01c, 0x78ff, 0xc01c, 0x21, 0 + .dw 0x7940, 0xc01c, 0x797f, 0xc01c, 0x21, 0 + .dw 0x79c0, 0xc01c, 0x7fff, 0xc01c, 0x21, 0 + .dw 0x8040, 0xc01c, 0x807f, 0xc01c, 0x21, 0 + .dw 0x80c0, 0xc01c, 0x80ff, 0xc01c, 0x21, 0 + .dw 0x8140, 0xc01c, 0x817f, 0xc01c, 0x21, 0 + .dw 0x81c0, 0xc01c, 0x81ff, 0xc01c, 0x21, 0 + .dw 0x8240, 0xc01c, 0x827f, 0xc01c, 0x21, 0 + .dw 0x82c0, 0xc01c, 0x82ff, 0xc01c, 0x21, 0 + .dw 0x8340, 0xc01c, 0x837f, 0xc01c, 0x21, 0 + .dw 0x83c0, 0xc01c, 0x83ff, 0xc01c, 0x21, 0 + .dw 0x8440, 0xc01c, 0x847f, 0xc01c, 0x21, 0 + .dw 0x84c0, 0xc01c, 0x84ff, 0xc01c, 0x21, 0 + .dw 0x8540, 0xc01c, 0x857f, 0xc01c, 0x21, 0 + .dw 0x85c0, 0xc01c, 0x85ff, 0xc01c, 0x21, 0 + .dw 0x8640, 0xc01c, 0x867f, 0xc01c, 0x21, 0 + .dw 0x86c0, 0xc01c, 0x86ff, 0xc01c, 0x21, 0 + .dw 0x8740, 0xc01c, 0x877f, 0xc01c, 0x21, 0 + .dw 0x87c0, 0xc01c, 0x87ff, 0xc01c, 0x21, 0 + .dw 0x8840, 0xc01c, 0x887f, 0xc01c, 0x21, 0 + .dw 0x88c0, 0xc01c, 0x88ff, 0xc01c, 0x21, 0 + .dw 0x8940, 0xc01c, 0x897f, 0xc01c, 0x21, 0 + .dw 0x89c0, 0xc01c, 0x89ff, 0xc01c, 0x21, 0 + .dw 0x8a40, 0xc01c, 0x8a7f, 0xc01c, 0x21, 0 + .dw 0x8ac0, 0xc01c, 0x8aff, 0xc01c, 0x21, 0 + .dw 0x8b40, 0xc01c, 0x8b7f, 0xc01c, 0x21, 0 + .dw 0x8bc0, 0xc01c, 0x8bff, 0xc01c, 0x21, 0 + .dw 0x8c40, 0xc01c, 0x8c7f, 0xc01c, 0x21, 0 + .dw 0x8cc0, 0xc01c, 0x8cff, 0xc01c, 0x21, 0 + .dw 0x8d40, 0xc01c, 0x8d7f, 0xc01c, 0x21, 0 + .dw 0x8dc0, 0xc01c, 0x8dff, 0xc01c, 0x21, 0 + .dw 0x8e40, 0xc01c, 0x8e7f, 0xc01c, 0x21, 0 + .dw 0x8ec0, 0xc01c, 0x8eff, 0xc01c, 0x21, 0 + .dw 0x8f40, 0xc01c, 0x8f7f, 0xc01c, 0x21, 0 + .dw 0x8fc0, 0xc01c, 0x8fff, 0xc01c, 0x21, 0 + .dw 0x9040, 0xc01c, 0x907f, 0xc01c, 0x21, 0 + .dw 0x90c0, 0xc01c, 0x90ff, 0xc01c, 0x21, 0 + .dw 0x9140, 0xc01c, 0x917f, 0xc01c, 0x21, 0 + .dw 0x91c0, 0xc01c, 0x91ff, 0xc01c, 0x21, 0 + .dw 0x9240, 0xc01c, 0x927f, 0xc01c, 0x21, 0 + .dw 0x92c0, 0xc01c, 0x92ff, 0xc01c, 0x21, 0 + .dw 0x9340, 0xc01c, 0x937f, 0xc01c, 0x21, 0 + .dw 0x93c0, 0xc01c, 0x93ff, 0xc01c, 0x21, 0 + .dw 0x9440, 0xc01c, 0x947f, 0xc01c, 0x21, 0 + .dw 0x94c0, 0xc01c, 0x94ff, 0xc01c, 0x21, 0 + .dw 0x9540, 0xc01c, 0x957f, 0xc01c, 0x21, 0 + .dw 0x95c0, 0xc01c, 0x95ff, 0xc01c, 0x21, 0 + .dw 0x9640, 0xc01c, 0x967f, 0xc01c, 0x21, 0 + .dw 0x96c0, 0xc01c, 0x96ff, 0xc01c, 0x21, 0 + .dw 0x9740, 0xc01c, 0x977f, 0xc01c, 0x21, 0 + .dw 0x97c0, 0xc01c, 0x97ff, 0xc01c, 0x21, 0 + .dw 0x9840, 0xc01c, 0x987f, 0xc01c, 0x21, 0 + .dw 0x98c0, 0xc01c, 0x98ff, 0xc01c, 0x21, 0 + .dw 0x9940, 0xc01c, 0x997f, 0xc01c, 0x21, 0 + .dw 0x99c0, 0xc01c, 0x9fff, 0xc01c, 0x21, 0 + .dw 0xa040, 0xc01c, 0xa07f, 0xc01c, 0x21, 0 + .dw 0xa0c0, 0xc01c, 0xa0ff, 0xc01c, 0x21, 0 + .dw 0xa140, 0xc01c, 0xa17f, 0xc01c, 0x21, 0 + .dw 0xa1c0, 0xc01c, 0xa1ff, 0xc01c, 0x21, 0 + .dw 0xa240, 0xc01c, 0xa27f, 0xc01c, 0x21, 0 + .dw 0xa2c0, 0xc01c, 0xa2ff, 0xc01c, 0x21, 0 + .dw 0xa340, 0xc01c, 0xa37f, 0xc01c, 0x21, 0 + .dw 0xa3c0, 0xc01c, 0xa3ff, 0xc01c, 0x21, 0 + .dw 0xa440, 0xc01c, 0xa47f, 0xc01c, 0x21, 0 + .dw 0xa4c0, 0xc01c, 0xa4ff, 0xc01c, 0x21, 0 + .dw 0xa540, 0xc01c, 0xa57f, 0xc01c, 0x21, 0 + .dw 0xa5c0, 0xc01c, 0xa5ff, 0xc01c, 0x21, 0 + .dw 0xa640, 0xc01c, 0xa67f, 0xc01c, 0x21, 0 + .dw 0xa6c0, 0xc01c, 0xa6ff, 0xc01c, 0x21, 0 + .dw 0xa740, 0xc01c, 0xa77f, 0xc01c, 0x21, 0 + .dw 0xa7c0, 0xc01c, 0xa7ff, 0xc01c, 0x21, 0 + .dw 0xa840, 0xc01c, 0xa87f, 0xc01c, 0x21, 0 + .dw 0xa8c0, 0xc01c, 0xa8ff, 0xc01c, 0x21, 0 + .dw 0xa940, 0xc01c, 0xa97f, 0xc01c, 0x21, 0 + .dw 0xa9c0, 0xc01c, 0xa9ff, 0xc01c, 0x21, 0 + .dw 0xaa40, 0xc01c, 0xaa7f, 0xc01c, 0x21, 0 + .dw 0xaac0, 0xc01c, 0xaaff, 0xc01c, 0x21, 0 + .dw 0xab40, 0xc01c, 0xab7f, 0xc01c, 0x21, 0 + .dw 0xabc0, 0xc01c, 0xabff, 0xc01c, 0x21, 0 + .dw 0xac40, 0xc01c, 0xac7f, 0xc01c, 0x21, 0 + .dw 0xacc0, 0xc01c, 0xacff, 0xc01c, 0x21, 0 + .dw 0xad40, 0xc01c, 0xad7f, 0xc01c, 0x21, 0 + .dw 0xadc0, 0xc01c, 0xadff, 0xc01c, 0x21, 0 + .dw 0xae40, 0xc01c, 0xae7f, 0xc01c, 0x21, 0 + .dw 0xaec0, 0xc01c, 0xaeff, 0xc01c, 0x21, 0 + .dw 0xaf40, 0xc01c, 0xaf7f, 0xc01c, 0x21, 0 + .dw 0xafc0, 0xc01c, 0xafff, 0xc01c, 0x21, 0 + .dw 0xb040, 0xc01c, 0xb07f, 0xc01c, 0x21, 0 + .dw 0xb0c0, 0xc01c, 0xb0ff, 0xc01c, 0x21, 0 + .dw 0xb140, 0xc01c, 0xb17f, 0xc01c, 0x21, 0 + .dw 0xb1c0, 0xc01c, 0xb1ff, 0xc01c, 0x21, 0 + .dw 0xb240, 0xc01c, 0xb27f, 0xc01c, 0x21, 0 + .dw 0xb2c0, 0xc01c, 0xb2ff, 0xc01c, 0x21, 0 + .dw 0xb340, 0xc01c, 0xb37f, 0xc01c, 0x21, 0 + .dw 0xb3c0, 0xc01c, 0xb3ff, 0xc01c, 0x21, 0 + .dw 0xb440, 0xc01c, 0xb47f, 0xc01c, 0x21, 0 + .dw 0xb4c0, 0xc01c, 0xb4ff, 0xc01c, 0x21, 0 + .dw 0xb540, 0xc01c, 0xb57f, 0xc01c, 0x21, 0 + .dw 0xb5c0, 0xc01c, 0xb5ff, 0xc01c, 0x21, 0 + .dw 0xb640, 0xc01c, 0xb67f, 0xc01c, 0x21, 0 + .dw 0xb6c0, 0xc01c, 0xb6ff, 0xc01c, 0x21, 0 + .dw 0xb740, 0xc01c, 0xb77f, 0xc01c, 0x21, 0 + .dw 0xb7c0, 0xc01c, 0xb7ff, 0xc01c, 0x21, 0 + .dw 0xb840, 0xc01c, 0xb87f, 0xc01c, 0x21, 0 + .dw 0xb8c0, 0xc01c, 0xb8ff, 0xc01c, 0x21, 0 + .dw 0xb940, 0xc01c, 0xb97f, 0xc01c, 0x21, 0 + .dw 0xb9c0, 0xc01c, 0xbfff, 0xc01c, 0x21, 0 + .dw 0xc040, 0xc01c, 0xc07f, 0xc01c, 0x21, 0 + .dw 0xc0c0, 0xc01c, 0xc0ff, 0xc01c, 0x21, 0 + .dw 0xc140, 0xc01c, 0xc17f, 0xc01c, 0x21, 0 + .dw 0xc1c0, 0xc01c, 0xc1ff, 0xc01c, 0x21, 0 + .dw 0xc240, 0xc01c, 0xc27f, 0xc01c, 0x21, 0 + .dw 0xc2c0, 0xc01c, 0xc2ff, 0xc01c, 0x21, 0 + .dw 0xc340, 0xc01c, 0xc37f, 0xc01c, 0x21, 0 + .dw 0xc3c0, 0xc01c, 0xc3ff, 0xc01c, 0x21, 0 + .dw 0xc440, 0xc01c, 0xc47f, 0xc01c, 0x21, 0 + .dw 0xc4c0, 0xc01c, 0xc4ff, 0xc01c, 0x21, 0 + .dw 0xc540, 0xc01c, 0xc57f, 0xc01c, 0x21, 0 + .dw 0xc5c0, 0xc01c, 0xc5ff, 0xc01c, 0x21, 0 + .dw 0xc640, 0xc01c, 0xc67f, 0xc01c, 0x21, 0 + .dw 0xc6c0, 0xc01c, 0xc6ff, 0xc01c, 0x21, 0 + .dw 0xc740, 0xc01c, 0xc77f, 0xc01c, 0x21, 0 + .dw 0xc7c0, 0xc01c, 0xc7ff, 0xc01c, 0x21, 0 + .dw 0xc840, 0xc01c, 0xc87f, 0xc01c, 0x21, 0 + .dw 0xc8c0, 0xc01c, 0xc8ff, 0xc01c, 0x21, 0 + .dw 0xc940, 0xc01c, 0xc97f, 0xc01c, 0x21, 0 + .dw 0xc9c0, 0xc01c, 0xc9ff, 0xc01c, 0x21, 0 + .dw 0xca40, 0xc01c, 0xca7f, 0xc01c, 0x21, 0 + .dw 0xcac0, 0xc01c, 0xcaff, 0xc01c, 0x21, 0 + .dw 0xcb40, 0xc01c, 0xcb7f, 0xc01c, 0x21, 0 + .dw 0xcbc0, 0xc01c, 0xcbff, 0xc01c, 0x21, 0 + .dw 0xcc40, 0xc01c, 0xcc7f, 0xc01c, 0x21, 0 + .dw 0xccc0, 0xc01c, 0xccff, 0xc01c, 0x21, 0 + .dw 0xcd40, 0xc01c, 0xcd7f, 0xc01c, 0x21, 0 + .dw 0xcdc0, 0xc01c, 0xcdff, 0xc01c, 0x21, 0 + .dw 0xce40, 0xc01c, 0xce7f, 0xc01c, 0x21, 0 + .dw 0xcec0, 0xc01c, 0xceff, 0xc01c, 0x21, 0 + .dw 0xcf40, 0xc01c, 0xcf7f, 0xc01c, 0x21, 0 + .dw 0xcfc0, 0xc01c, 0xcfff, 0xc01c, 0x21, 0 + .dw 0xd040, 0xc01c, 0xd07f, 0xc01c, 0x21, 0 + .dw 0xd0c0, 0xc01c, 0xd0ff, 0xc01c, 0x21, 0 + .dw 0xd140, 0xc01c, 0xd17f, 0xc01c, 0x21, 0 + .dw 0xd1c0, 0xc01c, 0xd1ff, 0xc01c, 0x21, 0 + .dw 0xd240, 0xc01c, 0xd27f, 0xc01c, 0x21, 0 + .dw 0xd2c0, 0xc01c, 0xd2ff, 0xc01c, 0x21, 0 + .dw 0xd340, 0xc01c, 0xd37f, 0xc01c, 0x21, 0 + .dw 0xd3c0, 0xc01c, 0xd3ff, 0xc01c, 0x21, 0 + .dw 0xd440, 0xc01c, 0xd47f, 0xc01c, 0x21, 0 + .dw 0xd4c0, 0xc01c, 0xd4ff, 0xc01c, 0x21, 0 + .dw 0xd540, 0xc01c, 0xd57f, 0xc01c, 0x21, 0 + .dw 0xd5c0, 0xc01c, 0xd5ff, 0xc01c, 0x21, 0 + .dw 0xd640, 0xc01c, 0xd67f, 0xc01c, 0x21, 0 + .dw 0xd6c0, 0xc01c, 0xd6ff, 0xc01c, 0x21, 0 + .dw 0xd740, 0xc01c, 0xd77f, 0xc01c, 0x21, 0 + .dw 0xd7c0, 0xc01c, 0xd7ff, 0xc01c, 0x21, 0 + .dw 0xd840, 0xc01c, 0xd87f, 0xc01c, 0x21, 0 + .dw 0xd8c0, 0xc01c, 0xd8ff, 0xc01c, 0x21, 0 + .dw 0xd940, 0xc01c, 0xd97f, 0xc01c, 0x21, 0 + .dw 0xd9c0, 0xc01c, 0xdfff, 0xc01c, 0x21, 0 + .dw 0xe040, 0xc01c, 0xe07f, 0xc01c, 0x21, 0 + .dw 0xe0c0, 0xc01c, 0xe0ff, 0xc01c, 0x21, 0 + .dw 0xe140, 0xc01c, 0xe17f, 0xc01c, 0x21, 0 + .dw 0xe1c0, 0xc01c, 0xe1ff, 0xc01c, 0x21, 0 + .dw 0xe240, 0xc01c, 0xe27f, 0xc01c, 0x21, 0 + .dw 0xe2c0, 0xc01c, 0xe2ff, 0xc01c, 0x21, 0 + .dw 0xe340, 0xc01c, 0xe37f, 0xc01c, 0x21, 0 + .dw 0xe3c0, 0xc01c, 0xe3ff, 0xc01c, 0x21, 0 + .dw 0xe440, 0xc01c, 0xe47f, 0xc01c, 0x21, 0 + .dw 0xe4c0, 0xc01c, 0xe4ff, 0xc01c, 0x21, 0 + .dw 0xe540, 0xc01c, 0xe57f, 0xc01c, 0x21, 0 + .dw 0xe5c0, 0xc01c, 0xe5ff, 0xc01c, 0x21, 0 + .dw 0xe640, 0xc01c, 0xe67f, 0xc01c, 0x21, 0 + .dw 0xe6c0, 0xc01c, 0xe6ff, 0xc01c, 0x21, 0 + .dw 0xe740, 0xc01c, 0xe77f, 0xc01c, 0x21, 0 + .dw 0xe7c0, 0xc01c, 0xe7ff, 0xc01c, 0x21, 0 + .dw 0xe840, 0xc01c, 0xe87f, 0xc01c, 0x21, 0 + .dw 0xe8c0, 0xc01c, 0xe8ff, 0xc01c, 0x21, 0 + .dw 0xe940, 0xc01c, 0xe97f, 0xc01c, 0x21, 0 + .dw 0xe9c0, 0xc01c, 0xe9ff, 0xc01c, 0x21, 0 + .dw 0xea40, 0xc01c, 0xea7f, 0xc01c, 0x21, 0 + .dw 0xeac0, 0xc01c, 0xeaff, 0xc01c, 0x21, 0 + .dw 0xeb40, 0xc01c, 0xeb7f, 0xc01c, 0x21, 0 + .dw 0xebc0, 0xc01c, 0xebff, 0xc01c, 0x21, 0 + .dw 0xec40, 0xc01c, 0xec7f, 0xc01c, 0x21, 0 + .dw 0xecc0, 0xc01c, 0xecff, 0xc01c, 0x21, 0 + .dw 0xed40, 0xc01c, 0xed7f, 0xc01c, 0x21, 0 + .dw 0xedc0, 0xc01c, 0xedff, 0xc01c, 0x21, 0 + .dw 0xee40, 0xc01c, 0xee7f, 0xc01c, 0x21, 0 + .dw 0xeec0, 0xc01c, 0xeeff, 0xc01c, 0x21, 0 + .dw 0xef40, 0xc01c, 0xef7f, 0xc01c, 0x21, 0 + .dw 0xefc0, 0xc01c, 0xefff, 0xc01c, 0x21, 0 + .dw 0xf040, 0xc01c, 0xf07f, 0xc01c, 0x21, 0 + .dw 0xf0c0, 0xc01c, 0xf0ff, 0xc01c, 0x21, 0 + .dw 0xf140, 0xc01c, 0xf17f, 0xc01c, 0x21, 0 + .dw 0xf1c0, 0xc01c, 0xf1ff, 0xc01c, 0x21, 0 + .dw 0xf240, 0xc01c, 0xf27f, 0xc01c, 0x21, 0 + .dw 0xf2c0, 0xc01c, 0xf2ff, 0xc01c, 0x21, 0 + .dw 0xf340, 0xc01c, 0xf37f, 0xc01c, 0x21, 0 + .dw 0xf3c0, 0xc01c, 0xf3ff, 0xc01c, 0x21, 0 + .dw 0xf440, 0xc01c, 0xf47f, 0xc01c, 0x21, 0 + .dw 0xf4c0, 0xc01c, 0xf4ff, 0xc01c, 0x21, 0 + .dw 0xf540, 0xc01c, 0xf57f, 0xc01c, 0x21, 0 + .dw 0xf5c0, 0xc01c, 0xf5ff, 0xc01c, 0x21, 0 + .dw 0xf640, 0xc01c, 0xf67f, 0xc01c, 0x21, 0 + .dw 0xf6c0, 0xc01c, 0xf6ff, 0xc01c, 0x21, 0 + .dw 0xf740, 0xc01c, 0xf77f, 0xc01c, 0x21, 0 + .dw 0xf7c0, 0xc01c, 0xf7ff, 0xc01c, 0x21, 0 + .dw 0xf840, 0xc01c, 0xf87f, 0xc01c, 0x21, 0 + .dw 0xf8c0, 0xc01c, 0xf8ff, 0xc01c, 0x21, 0 + .dw 0xf940, 0xc01c, 0xf97f, 0xc01c, 0x21, 0 + .dw 0xf9c0, 0xc01c, 0xffff, 0xc01c, 0x21, 0 + .dw 0x0040, 0xc01d, 0x007f, 0xc01d, 0x21, 0 + .dw 0x00c0, 0xc01d, 0x00ff, 0xc01d, 0x21, 0 + .dw 0x0140, 0xc01d, 0x017f, 0xc01d, 0x21, 0 + .dw 0x01c0, 0xc01d, 0x01ff, 0xc01d, 0x21, 0 + .dw 0x0240, 0xc01d, 0x027f, 0xc01d, 0x21, 0 + .dw 0x02c0, 0xc01d, 0x02ff, 0xc01d, 0x21, 0 + .dw 0x0340, 0xc01d, 0x037f, 0xc01d, 0x21, 0 + .dw 0x03c0, 0xc01d, 0x03ff, 0xc01d, 0x21, 0 + .dw 0x0440, 0xc01d, 0x047f, 0xc01d, 0x21, 0 + .dw 0x04c0, 0xc01d, 0x04ff, 0xc01d, 0x21, 0 + .dw 0x0540, 0xc01d, 0x057f, 0xc01d, 0x21, 0 + .dw 0x05c0, 0xc01d, 0x05ff, 0xc01d, 0x21, 0 + .dw 0x0640, 0xc01d, 0x067f, 0xc01d, 0x21, 0 + .dw 0x06c0, 0xc01d, 0x06ff, 0xc01d, 0x21, 0 + .dw 0x0740, 0xc01d, 0x077f, 0xc01d, 0x21, 0 + .dw 0x07c0, 0xc01d, 0x07ff, 0xc01d, 0x21, 0 + .dw 0x0840, 0xc01d, 0x087f, 0xc01d, 0x21, 0 + .dw 0x08c0, 0xc01d, 0x08ff, 0xc01d, 0x21, 0 + .dw 0x0940, 0xc01d, 0x097f, 0xc01d, 0x21, 0 + .dw 0x09c0, 0xc01d, 0x09ff, 0xc01d, 0x21, 0 + .dw 0x0a40, 0xc01d, 0x0a7f, 0xc01d, 0x21, 0 + .dw 0x0ac0, 0xc01d, 0x0aff, 0xc01d, 0x21, 0 + .dw 0x0b40, 0xc01d, 0x0b7f, 0xc01d, 0x21, 0 + .dw 0x0bc0, 0xc01d, 0x0bff, 0xc01d, 0x21, 0 + .dw 0x0c40, 0xc01d, 0x0c7f, 0xc01d, 0x21, 0 + .dw 0x0cc0, 0xc01d, 0x0cff, 0xc01d, 0x21, 0 + .dw 0x0d40, 0xc01d, 0x0d7f, 0xc01d, 0x21, 0 + .dw 0x0dc0, 0xc01d, 0x0dff, 0xc01d, 0x21, 0 + .dw 0x0e40, 0xc01d, 0x0e7f, 0xc01d, 0x21, 0 + .dw 0x0ec0, 0xc01d, 0x0eff, 0xc01d, 0x21, 0 + .dw 0x0f40, 0xc01d, 0x0f7f, 0xc01d, 0x21, 0 + .dw 0x0fc0, 0xc01d, 0x0fff, 0xc01d, 0x21, 0 + .dw 0x1040, 0xc01d, 0x107f, 0xc01d, 0x21, 0 + .dw 0x10c0, 0xc01d, 0x10ff, 0xc01d, 0x21, 0 + .dw 0x1140, 0xc01d, 0x117f, 0xc01d, 0x21, 0 + .dw 0x11c0, 0xc01d, 0x11ff, 0xc01d, 0x21, 0 + .dw 0x1240, 0xc01d, 0x127f, 0xc01d, 0x21, 0 + .dw 0x12c0, 0xc01d, 0x12ff, 0xc01d, 0x21, 0 + .dw 0x1340, 0xc01d, 0x137f, 0xc01d, 0x21, 0 + .dw 0x13c0, 0xc01d, 0x13ff, 0xc01d, 0x21, 0 + .dw 0x1440, 0xc01d, 0x147f, 0xc01d, 0x21, 0 + .dw 0x14c0, 0xc01d, 0x14ff, 0xc01d, 0x21, 0 + .dw 0x1540, 0xc01d, 0x157f, 0xc01d, 0x21, 0 + .dw 0x15c0, 0xc01d, 0x15ff, 0xc01d, 0x21, 0 + .dw 0x1640, 0xc01d, 0x167f, 0xc01d, 0x21, 0 + .dw 0x16c0, 0xc01d, 0x16ff, 0xc01d, 0x21, 0 + .dw 0x1740, 0xc01d, 0x177f, 0xc01d, 0x21, 0 + .dw 0x17c0, 0xc01d, 0x17ff, 0xc01d, 0x21, 0 + .dw 0x1840, 0xc01d, 0x187f, 0xc01d, 0x21, 0 + .dw 0x18c0, 0xc01d, 0x18ff, 0xc01d, 0x21, 0 + .dw 0x1940, 0xc01d, 0x197f, 0xc01d, 0x21, 0 + .dw 0x19c0, 0xc01d, 0x1fff, 0xc01d, 0x21, 0 + .dw 0x2040, 0xc01d, 0x207f, 0xc01d, 0x21, 0 + .dw 0x20c0, 0xc01d, 0x20ff, 0xc01d, 0x21, 0 + .dw 0x2140, 0xc01d, 0x217f, 0xc01d, 0x21, 0 + .dw 0x21c0, 0xc01d, 0x21ff, 0xc01d, 0x21, 0 + .dw 0x2240, 0xc01d, 0x227f, 0xc01d, 0x21, 0 + .dw 0x22c0, 0xc01d, 0x22ff, 0xc01d, 0x21, 0 + .dw 0x2340, 0xc01d, 0x237f, 0xc01d, 0x21, 0 + .dw 0x23c0, 0xc01d, 0x23ff, 0xc01d, 0x21, 0 + .dw 0x2440, 0xc01d, 0x247f, 0xc01d, 0x21, 0 + .dw 0x24c0, 0xc01d, 0x24ff, 0xc01d, 0x21, 0 + .dw 0x2540, 0xc01d, 0x257f, 0xc01d, 0x21, 0 + .dw 0x25c0, 0xc01d, 0x25ff, 0xc01d, 0x21, 0 + .dw 0x2640, 0xc01d, 0x267f, 0xc01d, 0x21, 0 + .dw 0x26c0, 0xc01d, 0x26ff, 0xc01d, 0x21, 0 + .dw 0x2740, 0xc01d, 0x277f, 0xc01d, 0x21, 0 + .dw 0x27c0, 0xc01d, 0x27ff, 0xc01d, 0x21, 0 + .dw 0x2840, 0xc01d, 0x287f, 0xc01d, 0x21, 0 + .dw 0x28c0, 0xc01d, 0x28ff, 0xc01d, 0x21, 0 + .dw 0x2940, 0xc01d, 0x297f, 0xc01d, 0x21, 0 + .dw 0x29c0, 0xc01d, 0x29ff, 0xc01d, 0x21, 0 + .dw 0x2a40, 0xc01d, 0x2a7f, 0xc01d, 0x21, 0 + .dw 0x2ac0, 0xc01d, 0x2aff, 0xc01d, 0x21, 0 + .dw 0x2b40, 0xc01d, 0x2b7f, 0xc01d, 0x21, 0 + .dw 0x2bc0, 0xc01d, 0x2bff, 0xc01d, 0x21, 0 + .dw 0x2c40, 0xc01d, 0x2c7f, 0xc01d, 0x21, 0 + .dw 0x2cc0, 0xc01d, 0x2cff, 0xc01d, 0x21, 0 + .dw 0x2d40, 0xc01d, 0x2d7f, 0xc01d, 0x21, 0 + .dw 0x2dc0, 0xc01d, 0x2dff, 0xc01d, 0x21, 0 + .dw 0x2e40, 0xc01d, 0x2e7f, 0xc01d, 0x21, 0 + .dw 0x2ec0, 0xc01d, 0x2eff, 0xc01d, 0x21, 0 + .dw 0x2f40, 0xc01d, 0x2f7f, 0xc01d, 0x21, 0 + .dw 0x2fc0, 0xc01d, 0x2fff, 0xc01d, 0x21, 0 + .dw 0x3040, 0xc01d, 0x307f, 0xc01d, 0x21, 0 + .dw 0x30c0, 0xc01d, 0x30ff, 0xc01d, 0x21, 0 + .dw 0x3140, 0xc01d, 0x317f, 0xc01d, 0x21, 0 + .dw 0x31c0, 0xc01d, 0x31ff, 0xc01d, 0x21, 0 + .dw 0x3240, 0xc01d, 0x327f, 0xc01d, 0x21, 0 + .dw 0x32c0, 0xc01d, 0x32ff, 0xc01d, 0x21, 0 + .dw 0x3340, 0xc01d, 0x337f, 0xc01d, 0x21, 0 + .dw 0x33c0, 0xc01d, 0x33ff, 0xc01d, 0x21, 0 + .dw 0x3440, 0xc01d, 0x347f, 0xc01d, 0x21, 0 + .dw 0x34c0, 0xc01d, 0x34ff, 0xc01d, 0x21, 0 + .dw 0x3540, 0xc01d, 0x357f, 0xc01d, 0x21, 0 + .dw 0x35c0, 0xc01d, 0x35ff, 0xc01d, 0x21, 0 + .dw 0x3640, 0xc01d, 0x367f, 0xc01d, 0x21, 0 + .dw 0x36c0, 0xc01d, 0x36ff, 0xc01d, 0x21, 0 + .dw 0x3740, 0xc01d, 0x377f, 0xc01d, 0x21, 0 + .dw 0x37c0, 0xc01d, 0x37ff, 0xc01d, 0x21, 0 + .dw 0x3840, 0xc01d, 0x387f, 0xc01d, 0x21, 0 + .dw 0x38c0, 0xc01d, 0x38ff, 0xc01d, 0x21, 0 + .dw 0x3940, 0xc01d, 0x397f, 0xc01d, 0x21, 0 + .dw 0x39c0, 0xc01d, 0x3fff, 0xc01d, 0x21, 0 + .dw 0x4040, 0xc01d, 0x407f, 0xc01d, 0x21, 0 + .dw 0x40c0, 0xc01d, 0x40ff, 0xc01d, 0x21, 0 + .dw 0x4140, 0xc01d, 0x417f, 0xc01d, 0x21, 0 + .dw 0x41c0, 0xc01d, 0x41ff, 0xc01d, 0x21, 0 + .dw 0x4240, 0xc01d, 0x427f, 0xc01d, 0x21, 0 + .dw 0x42c0, 0xc01d, 0x42ff, 0xc01d, 0x21, 0 + .dw 0x4340, 0xc01d, 0x437f, 0xc01d, 0x21, 0 + .dw 0x43c0, 0xc01d, 0x43ff, 0xc01d, 0x21, 0 + .dw 0x4440, 0xc01d, 0x447f, 0xc01d, 0x21, 0 + .dw 0x44c0, 0xc01d, 0x44ff, 0xc01d, 0x21, 0 + .dw 0x4540, 0xc01d, 0x457f, 0xc01d, 0x21, 0 + .dw 0x45c0, 0xc01d, 0x45ff, 0xc01d, 0x21, 0 + .dw 0x4640, 0xc01d, 0x467f, 0xc01d, 0x21, 0 + .dw 0x46c0, 0xc01d, 0x46ff, 0xc01d, 0x21, 0 + .dw 0x4740, 0xc01d, 0x477f, 0xc01d, 0x21, 0 + .dw 0x47c0, 0xc01d, 0x47ff, 0xc01d, 0x21, 0 + .dw 0x4840, 0xc01d, 0x487f, 0xc01d, 0x21, 0 + .dw 0x48c0, 0xc01d, 0x48ff, 0xc01d, 0x21, 0 + .dw 0x4940, 0xc01d, 0x497f, 0xc01d, 0x21, 0 + .dw 0x49c0, 0xc01d, 0x49ff, 0xc01d, 0x21, 0 + .dw 0x4a40, 0xc01d, 0x4a7f, 0xc01d, 0x21, 0 + .dw 0x4ac0, 0xc01d, 0x4aff, 0xc01d, 0x21, 0 + .dw 0x4b40, 0xc01d, 0x4b7f, 0xc01d, 0x21, 0 + .dw 0x4bc0, 0xc01d, 0x4bff, 0xc01d, 0x21, 0 + .dw 0x4c40, 0xc01d, 0x4c7f, 0xc01d, 0x21, 0 + .dw 0x4cc0, 0xc01d, 0x4cff, 0xc01d, 0x21, 0 + .dw 0x4d40, 0xc01d, 0x4d7f, 0xc01d, 0x21, 0 + .dw 0x4dc0, 0xc01d, 0x4dff, 0xc01d, 0x21, 0 + .dw 0x4e40, 0xc01d, 0x4e7f, 0xc01d, 0x21, 0 + .dw 0x4ec0, 0xc01d, 0x4eff, 0xc01d, 0x21, 0 + .dw 0x4f40, 0xc01d, 0x4f7f, 0xc01d, 0x21, 0 + .dw 0x4fc0, 0xc01d, 0x4fff, 0xc01d, 0x21, 0 + .dw 0x5040, 0xc01d, 0x507f, 0xc01d, 0x21, 0 + .dw 0x50c0, 0xc01d, 0x50ff, 0xc01d, 0x21, 0 + .dw 0x5140, 0xc01d, 0x517f, 0xc01d, 0x21, 0 + .dw 0x51c0, 0xc01d, 0x51ff, 0xc01d, 0x21, 0 + .dw 0x5240, 0xc01d, 0x527f, 0xc01d, 0x21, 0 + .dw 0x52c0, 0xc01d, 0x52ff, 0xc01d, 0x21, 0 + .dw 0x5340, 0xc01d, 0x537f, 0xc01d, 0x21, 0 + .dw 0x53c0, 0xc01d, 0x53ff, 0xc01d, 0x21, 0 + .dw 0x5440, 0xc01d, 0x547f, 0xc01d, 0x21, 0 + .dw 0x54c0, 0xc01d, 0x54ff, 0xc01d, 0x21, 0 + .dw 0x5540, 0xc01d, 0x557f, 0xc01d, 0x21, 0 + .dw 0x55c0, 0xc01d, 0x55ff, 0xc01d, 0x21, 0 + .dw 0x5640, 0xc01d, 0x567f, 0xc01d, 0x21, 0 + .dw 0x56c0, 0xc01d, 0x56ff, 0xc01d, 0x21, 0 + .dw 0x5740, 0xc01d, 0x577f, 0xc01d, 0x21, 0 + .dw 0x57c0, 0xc01d, 0x57ff, 0xc01d, 0x21, 0 + .dw 0x5840, 0xc01d, 0x587f, 0xc01d, 0x21, 0 + .dw 0x58c0, 0xc01d, 0x58ff, 0xc01d, 0x21, 0 + .dw 0x5940, 0xc01d, 0x597f, 0xc01d, 0x21, 0 + .dw 0x59c0, 0xc01d, 0x5fff, 0xc01d, 0x21, 0 + .dw 0x6040, 0xc01d, 0x607f, 0xc01d, 0x21, 0 + .dw 0x60c0, 0xc01d, 0x60ff, 0xc01d, 0x21, 0 + .dw 0x6140, 0xc01d, 0x617f, 0xc01d, 0x21, 0 + .dw 0x61c0, 0xc01d, 0x61ff, 0xc01d, 0x21, 0 + .dw 0x6240, 0xc01d, 0x627f, 0xc01d, 0x21, 0 + .dw 0x62c0, 0xc01d, 0x62ff, 0xc01d, 0x21, 0 + .dw 0x6340, 0xc01d, 0x637f, 0xc01d, 0x21, 0 + .dw 0x63c0, 0xc01d, 0x63ff, 0xc01d, 0x21, 0 + .dw 0x6440, 0xc01d, 0x647f, 0xc01d, 0x21, 0 + .dw 0x64c0, 0xc01d, 0x64ff, 0xc01d, 0x21, 0 + .dw 0x6540, 0xc01d, 0x657f, 0xc01d, 0x21, 0 + .dw 0x65c0, 0xc01d, 0x65ff, 0xc01d, 0x21, 0 + .dw 0x6640, 0xc01d, 0x667f, 0xc01d, 0x21, 0 + .dw 0x66c0, 0xc01d, 0x66ff, 0xc01d, 0x21, 0 + .dw 0x6740, 0xc01d, 0x677f, 0xc01d, 0x21, 0 + .dw 0x67c0, 0xc01d, 0x67ff, 0xc01d, 0x21, 0 + .dw 0x6840, 0xc01d, 0x687f, 0xc01d, 0x21, 0 + .dw 0x68c0, 0xc01d, 0x68ff, 0xc01d, 0x21, 0 + .dw 0x6940, 0xc01d, 0x697f, 0xc01d, 0x21, 0 + .dw 0x69c0, 0xc01d, 0x69ff, 0xc01d, 0x21, 0 + .dw 0x6a40, 0xc01d, 0x6a7f, 0xc01d, 0x21, 0 + .dw 0x6ac0, 0xc01d, 0x6aff, 0xc01d, 0x21, 0 + .dw 0x6b40, 0xc01d, 0x6b7f, 0xc01d, 0x21, 0 + .dw 0x6bc0, 0xc01d, 0x6bff, 0xc01d, 0x21, 0 + .dw 0x6c40, 0xc01d, 0x6c7f, 0xc01d, 0x21, 0 + .dw 0x6cc0, 0xc01d, 0x6cff, 0xc01d, 0x21, 0 + .dw 0x6d40, 0xc01d, 0x6d7f, 0xc01d, 0x21, 0 + .dw 0x6dc0, 0xc01d, 0x6dff, 0xc01d, 0x21, 0 + .dw 0x6e40, 0xc01d, 0x6e7f, 0xc01d, 0x21, 0 + .dw 0x6ec0, 0xc01d, 0x6eff, 0xc01d, 0x21, 0 + .dw 0x6f40, 0xc01d, 0x6f7f, 0xc01d, 0x21, 0 + .dw 0x6fc0, 0xc01d, 0x6fff, 0xc01d, 0x21, 0 + .dw 0x7040, 0xc01d, 0x707f, 0xc01d, 0x21, 0 + .dw 0x70c0, 0xc01d, 0x70ff, 0xc01d, 0x21, 0 + .dw 0x7140, 0xc01d, 0x717f, 0xc01d, 0x21, 0 + .dw 0x71c0, 0xc01d, 0x71ff, 0xc01d, 0x21, 0 + .dw 0x7240, 0xc01d, 0x727f, 0xc01d, 0x21, 0 + .dw 0x72c0, 0xc01d, 0x72ff, 0xc01d, 0x21, 0 + .dw 0x7340, 0xc01d, 0x737f, 0xc01d, 0x21, 0 + .dw 0x73c0, 0xc01d, 0x73ff, 0xc01d, 0x21, 0 + .dw 0x7440, 0xc01d, 0x747f, 0xc01d, 0x21, 0 + .dw 0x74c0, 0xc01d, 0x74ff, 0xc01d, 0x21, 0 + .dw 0x7540, 0xc01d, 0x757f, 0xc01d, 0x21, 0 + .dw 0x75c0, 0xc01d, 0x75ff, 0xc01d, 0x21, 0 + .dw 0x7640, 0xc01d, 0x767f, 0xc01d, 0x21, 0 + .dw 0x76c0, 0xc01d, 0x76ff, 0xc01d, 0x21, 0 + .dw 0x7740, 0xc01d, 0x777f, 0xc01d, 0x21, 0 + .dw 0x77c0, 0xc01d, 0x77ff, 0xc01d, 0x21, 0 + .dw 0x7840, 0xc01d, 0x787f, 0xc01d, 0x21, 0 + .dw 0x78c0, 0xc01d, 0x78ff, 0xc01d, 0x21, 0 + .dw 0x7940, 0xc01d, 0x797f, 0xc01d, 0x21, 0 + .dw 0x79c0, 0xc01d, 0x7fff, 0xc01d, 0x21, 0 + .dw 0x8040, 0xc01d, 0x807f, 0xc01d, 0x21, 0 + .dw 0x80c0, 0xc01d, 0x80ff, 0xc01d, 0x21, 0 + .dw 0x8140, 0xc01d, 0x817f, 0xc01d, 0x21, 0 + .dw 0x81c0, 0xc01d, 0x81ff, 0xc01d, 0x21, 0 + .dw 0x8240, 0xc01d, 0x827f, 0xc01d, 0x21, 0 + .dw 0x82c0, 0xc01d, 0x82ff, 0xc01d, 0x21, 0 + .dw 0x8340, 0xc01d, 0x837f, 0xc01d, 0x21, 0 + .dw 0x83c0, 0xc01d, 0x83ff, 0xc01d, 0x21, 0 + .dw 0x8440, 0xc01d, 0x847f, 0xc01d, 0x21, 0 + .dw 0x84c0, 0xc01d, 0x84ff, 0xc01d, 0x21, 0 + .dw 0x8540, 0xc01d, 0x857f, 0xc01d, 0x21, 0 + .dw 0x85c0, 0xc01d, 0x85ff, 0xc01d, 0x21, 0 + .dw 0x8640, 0xc01d, 0x867f, 0xc01d, 0x21, 0 + .dw 0x86c0, 0xc01d, 0x86ff, 0xc01d, 0x21, 0 + .dw 0x8740, 0xc01d, 0x877f, 0xc01d, 0x21, 0 + .dw 0x87c0, 0xc01d, 0x87ff, 0xc01d, 0x21, 0 + .dw 0x8840, 0xc01d, 0x887f, 0xc01d, 0x21, 0 + .dw 0x88c0, 0xc01d, 0x88ff, 0xc01d, 0x21, 0 + .dw 0x8940, 0xc01d, 0x897f, 0xc01d, 0x21, 0 + .dw 0x89c0, 0xc01d, 0x89ff, 0xc01d, 0x21, 0 + .dw 0x8a40, 0xc01d, 0x8a7f, 0xc01d, 0x21, 0 + .dw 0x8ac0, 0xc01d, 0x8aff, 0xc01d, 0x21, 0 + .dw 0x8b40, 0xc01d, 0x8b7f, 0xc01d, 0x21, 0 + .dw 0x8bc0, 0xc01d, 0x8bff, 0xc01d, 0x21, 0 + .dw 0x8c40, 0xc01d, 0x8c7f, 0xc01d, 0x21, 0 + .dw 0x8cc0, 0xc01d, 0x8cff, 0xc01d, 0x21, 0 + .dw 0x8d40, 0xc01d, 0x8d7f, 0xc01d, 0x21, 0 + .dw 0x8dc0, 0xc01d, 0x8dff, 0xc01d, 0x21, 0 + .dw 0x8e40, 0xc01d, 0x8e7f, 0xc01d, 0x21, 0 + .dw 0x8ec0, 0xc01d, 0x8eff, 0xc01d, 0x21, 0 + .dw 0x8f40, 0xc01d, 0x8f7f, 0xc01d, 0x21, 0 + .dw 0x8fc0, 0xc01d, 0x8fff, 0xc01d, 0x21, 0 + .dw 0x9040, 0xc01d, 0x907f, 0xc01d, 0x21, 0 + .dw 0x90c0, 0xc01d, 0x90ff, 0xc01d, 0x21, 0 + .dw 0x9140, 0xc01d, 0x917f, 0xc01d, 0x21, 0 + .dw 0x91c0, 0xc01d, 0x91ff, 0xc01d, 0x21, 0 + .dw 0x9240, 0xc01d, 0x927f, 0xc01d, 0x21, 0 + .dw 0x92c0, 0xc01d, 0x92ff, 0xc01d, 0x21, 0 + .dw 0x9340, 0xc01d, 0x937f, 0xc01d, 0x21, 0 + .dw 0x93c0, 0xc01d, 0x93ff, 0xc01d, 0x21, 0 + .dw 0x9440, 0xc01d, 0x947f, 0xc01d, 0x21, 0 + .dw 0x94c0, 0xc01d, 0x94ff, 0xc01d, 0x21, 0 + .dw 0x9540, 0xc01d, 0x957f, 0xc01d, 0x21, 0 + .dw 0x95c0, 0xc01d, 0x95ff, 0xc01d, 0x21, 0 + .dw 0x9640, 0xc01d, 0x967f, 0xc01d, 0x21, 0 + .dw 0x96c0, 0xc01d, 0x96ff, 0xc01d, 0x21, 0 + .dw 0x9740, 0xc01d, 0x977f, 0xc01d, 0x21, 0 + .dw 0x97c0, 0xc01d, 0x97ff, 0xc01d, 0x21, 0 + .dw 0x9840, 0xc01d, 0x987f, 0xc01d, 0x21, 0 + .dw 0x98c0, 0xc01d, 0x98ff, 0xc01d, 0x21, 0 + .dw 0x9940, 0xc01d, 0x997f, 0xc01d, 0x21, 0 + .dw 0x99c0, 0xc01d, 0x9fff, 0xc01d, 0x21, 0 + .dw 0xa040, 0xc01d, 0xa07f, 0xc01d, 0x21, 0 + .dw 0xa0c0, 0xc01d, 0xa0ff, 0xc01d, 0x21, 0 + .dw 0xa140, 0xc01d, 0xa17f, 0xc01d, 0x21, 0 + .dw 0xa1c0, 0xc01d, 0xa1ff, 0xc01d, 0x21, 0 + .dw 0xa240, 0xc01d, 0xa27f, 0xc01d, 0x21, 0 + .dw 0xa2c0, 0xc01d, 0xa2ff, 0xc01d, 0x21, 0 + .dw 0xa340, 0xc01d, 0xa37f, 0xc01d, 0x21, 0 + .dw 0xa3c0, 0xc01d, 0xa3ff, 0xc01d, 0x21, 0 + .dw 0xa440, 0xc01d, 0xa47f, 0xc01d, 0x21, 0 + .dw 0xa4c0, 0xc01d, 0xa4ff, 0xc01d, 0x21, 0 + .dw 0xa540, 0xc01d, 0xa57f, 0xc01d, 0x21, 0 + .dw 0xa5c0, 0xc01d, 0xa5ff, 0xc01d, 0x21, 0 + .dw 0xa640, 0xc01d, 0xa67f, 0xc01d, 0x21, 0 + .dw 0xa6c0, 0xc01d, 0xa6ff, 0xc01d, 0x21, 0 + .dw 0xa740, 0xc01d, 0xa77f, 0xc01d, 0x21, 0 + .dw 0xa7c0, 0xc01d, 0xa7ff, 0xc01d, 0x21, 0 + .dw 0xa840, 0xc01d, 0xa87f, 0xc01d, 0x21, 0 + .dw 0xa8c0, 0xc01d, 0xa8ff, 0xc01d, 0x21, 0 + .dw 0xa940, 0xc01d, 0xa97f, 0xc01d, 0x21, 0 + .dw 0xa9c0, 0xc01d, 0xa9ff, 0xc01d, 0x21, 0 + .dw 0xaa40, 0xc01d, 0xaa7f, 0xc01d, 0x21, 0 + .dw 0xaac0, 0xc01d, 0xaaff, 0xc01d, 0x21, 0 + .dw 0xab40, 0xc01d, 0xab7f, 0xc01d, 0x21, 0 + .dw 0xabc0, 0xc01d, 0xabff, 0xc01d, 0x21, 0 + .dw 0xac40, 0xc01d, 0xac7f, 0xc01d, 0x21, 0 + .dw 0xacc0, 0xc01d, 0xacff, 0xc01d, 0x21, 0 + .dw 0xad40, 0xc01d, 0xad7f, 0xc01d, 0x21, 0 + .dw 0xadc0, 0xc01d, 0xadff, 0xc01d, 0x21, 0 + .dw 0xae40, 0xc01d, 0xae7f, 0xc01d, 0x21, 0 + .dw 0xaec0, 0xc01d, 0xaeff, 0xc01d, 0x21, 0 + .dw 0xaf40, 0xc01d, 0xaf7f, 0xc01d, 0x21, 0 + .dw 0xafc0, 0xc01d, 0xafff, 0xc01d, 0x21, 0 + .dw 0xb040, 0xc01d, 0xb07f, 0xc01d, 0x21, 0 + .dw 0xb0c0, 0xc01d, 0xb0ff, 0xc01d, 0x21, 0 + .dw 0xb140, 0xc01d, 0xb17f, 0xc01d, 0x21, 0 + .dw 0xb1c0, 0xc01d, 0xb1ff, 0xc01d, 0x21, 0 + .dw 0xb240, 0xc01d, 0xb27f, 0xc01d, 0x21, 0 + .dw 0xb2c0, 0xc01d, 0xb2ff, 0xc01d, 0x21, 0 + .dw 0xb340, 0xc01d, 0xb37f, 0xc01d, 0x21, 0 + .dw 0xb3c0, 0xc01d, 0xb3ff, 0xc01d, 0x21, 0 + .dw 0xb440, 0xc01d, 0xb47f, 0xc01d, 0x21, 0 + .dw 0xb4c0, 0xc01d, 0xb4ff, 0xc01d, 0x21, 0 + .dw 0xb540, 0xc01d, 0xb57f, 0xc01d, 0x21, 0 + .dw 0xb5c0, 0xc01d, 0xb5ff, 0xc01d, 0x21, 0 + .dw 0xb640, 0xc01d, 0xb67f, 0xc01d, 0x21, 0 + .dw 0xb6c0, 0xc01d, 0xb6ff, 0xc01d, 0x21, 0 + .dw 0xb740, 0xc01d, 0xb77f, 0xc01d, 0x21, 0 + .dw 0xb7c0, 0xc01d, 0xb7ff, 0xc01d, 0x21, 0 + .dw 0xb840, 0xc01d, 0xb87f, 0xc01d, 0x21, 0 + .dw 0xb8c0, 0xc01d, 0xb8ff, 0xc01d, 0x21, 0 + .dw 0xb940, 0xc01d, 0xb97f, 0xc01d, 0x21, 0 + .dw 0xb9c0, 0xc01d, 0xbfff, 0xc01d, 0x21, 0 + .dw 0xc040, 0xc01d, 0xc07f, 0xc01d, 0x21, 0 + .dw 0xc0c0, 0xc01d, 0xc0ff, 0xc01d, 0x21, 0 + .dw 0xc140, 0xc01d, 0xc17f, 0xc01d, 0x21, 0 + .dw 0xc1c0, 0xc01d, 0xc1ff, 0xc01d, 0x21, 0 + .dw 0xc240, 0xc01d, 0xc27f, 0xc01d, 0x21, 0 + .dw 0xc2c0, 0xc01d, 0xc2ff, 0xc01d, 0x21, 0 + .dw 0xc340, 0xc01d, 0xc37f, 0xc01d, 0x21, 0 + .dw 0xc3c0, 0xc01d, 0xc3ff, 0xc01d, 0x21, 0 + .dw 0xc440, 0xc01d, 0xc47f, 0xc01d, 0x21, 0 + .dw 0xc4c0, 0xc01d, 0xc4ff, 0xc01d, 0x21, 0 + .dw 0xc540, 0xc01d, 0xc57f, 0xc01d, 0x21, 0 + .dw 0xc5c0, 0xc01d, 0xc5ff, 0xc01d, 0x21, 0 + .dw 0xc640, 0xc01d, 0xc67f, 0xc01d, 0x21, 0 + .dw 0xc6c0, 0xc01d, 0xc6ff, 0xc01d, 0x21, 0 + .dw 0xc740, 0xc01d, 0xc77f, 0xc01d, 0x21, 0 + .dw 0xc7c0, 0xc01d, 0xc7ff, 0xc01d, 0x21, 0 + .dw 0xc840, 0xc01d, 0xc87f, 0xc01d, 0x21, 0 + .dw 0xc8c0, 0xc01d, 0xc8ff, 0xc01d, 0x21, 0 + .dw 0xc940, 0xc01d, 0xc97f, 0xc01d, 0x21, 0 + .dw 0xc9c0, 0xc01d, 0xc9ff, 0xc01d, 0x21, 0 + .dw 0xca40, 0xc01d, 0xca7f, 0xc01d, 0x21, 0 + .dw 0xcac0, 0xc01d, 0xcaff, 0xc01d, 0x21, 0 + .dw 0xcb40, 0xc01d, 0xcb7f, 0xc01d, 0x21, 0 + .dw 0xcbc0, 0xc01d, 0xcbff, 0xc01d, 0x21, 0 + .dw 0xcc40, 0xc01d, 0xcc7f, 0xc01d, 0x21, 0 + .dw 0xccc0, 0xc01d, 0xccff, 0xc01d, 0x21, 0 + .dw 0xcd40, 0xc01d, 0xcd7f, 0xc01d, 0x21, 0 + .dw 0xcdc0, 0xc01d, 0xcdff, 0xc01d, 0x21, 0 + .dw 0xce40, 0xc01d, 0xce7f, 0xc01d, 0x21, 0 + .dw 0xcec0, 0xc01d, 0xceff, 0xc01d, 0x21, 0 + .dw 0xcf40, 0xc01d, 0xcf7f, 0xc01d, 0x21, 0 + .dw 0xcfc0, 0xc01d, 0xcfff, 0xc01d, 0x21, 0 + .dw 0xd040, 0xc01d, 0xd07f, 0xc01d, 0x21, 0 + .dw 0xd0c0, 0xc01d, 0xd0ff, 0xc01d, 0x21, 0 + .dw 0xd140, 0xc01d, 0xd17f, 0xc01d, 0x21, 0 + .dw 0xd1c0, 0xc01d, 0xd1ff, 0xc01d, 0x21, 0 + .dw 0xd240, 0xc01d, 0xd27f, 0xc01d, 0x21, 0 + .dw 0xd2c0, 0xc01d, 0xd2ff, 0xc01d, 0x21, 0 + .dw 0xd340, 0xc01d, 0xd37f, 0xc01d, 0x21, 0 + .dw 0xd3c0, 0xc01d, 0xd3ff, 0xc01d, 0x21, 0 + .dw 0xd440, 0xc01d, 0xd47f, 0xc01d, 0x21, 0 + .dw 0xd4c0, 0xc01d, 0xd4ff, 0xc01d, 0x21, 0 + .dw 0xd540, 0xc01d, 0xd57f, 0xc01d, 0x21, 0 + .dw 0xd5c0, 0xc01d, 0xd5ff, 0xc01d, 0x21, 0 + .dw 0xd640, 0xc01d, 0xd67f, 0xc01d, 0x21, 0 + .dw 0xd6c0, 0xc01d, 0xd6ff, 0xc01d, 0x21, 0 + .dw 0xd740, 0xc01d, 0xd77f, 0xc01d, 0x21, 0 + .dw 0xd7c0, 0xc01d, 0xd7ff, 0xc01d, 0x21, 0 + .dw 0xd840, 0xc01d, 0xd87f, 0xc01d, 0x21, 0 + .dw 0xd8c0, 0xc01d, 0xd8ff, 0xc01d, 0x21, 0 + .dw 0xd940, 0xc01d, 0xd97f, 0xc01d, 0x21, 0 + .dw 0xd9c0, 0xc01d, 0xdfff, 0xc01d, 0x21, 0 + .dw 0xe040, 0xc01d, 0xe07f, 0xc01d, 0x21, 0 + .dw 0xe0c0, 0xc01d, 0xe0ff, 0xc01d, 0x21, 0 + .dw 0xe140, 0xc01d, 0xe17f, 0xc01d, 0x21, 0 + .dw 0xe1c0, 0xc01d, 0xe1ff, 0xc01d, 0x21, 0 + .dw 0xe240, 0xc01d, 0xe27f, 0xc01d, 0x21, 0 + .dw 0xe2c0, 0xc01d, 0xe2ff, 0xc01d, 0x21, 0 + .dw 0xe340, 0xc01d, 0xe37f, 0xc01d, 0x21, 0 + .dw 0xe3c0, 0xc01d, 0xe3ff, 0xc01d, 0x21, 0 + .dw 0xe440, 0xc01d, 0xe47f, 0xc01d, 0x21, 0 + .dw 0xe4c0, 0xc01d, 0xe4ff, 0xc01d, 0x21, 0 + .dw 0xe540, 0xc01d, 0xe57f, 0xc01d, 0x21, 0 + .dw 0xe5c0, 0xc01d, 0xe5ff, 0xc01d, 0x21, 0 + .dw 0xe640, 0xc01d, 0xe67f, 0xc01d, 0x21, 0 + .dw 0xe6c0, 0xc01d, 0xe6ff, 0xc01d, 0x21, 0 + .dw 0xe740, 0xc01d, 0xe77f, 0xc01d, 0x21, 0 + .dw 0xe7c0, 0xc01d, 0xe7ff, 0xc01d, 0x21, 0 + .dw 0xe840, 0xc01d, 0xe87f, 0xc01d, 0x21, 0 + .dw 0xe8c0, 0xc01d, 0xe8ff, 0xc01d, 0x21, 0 + .dw 0xe940, 0xc01d, 0xe97f, 0xc01d, 0x21, 0 + .dw 0xe9c0, 0xc01d, 0xe9ff, 0xc01d, 0x21, 0 + .dw 0xea40, 0xc01d, 0xea7f, 0xc01d, 0x21, 0 + .dw 0xeac0, 0xc01d, 0xeaff, 0xc01d, 0x21, 0 + .dw 0xeb40, 0xc01d, 0xeb7f, 0xc01d, 0x21, 0 + .dw 0xebc0, 0xc01d, 0xebff, 0xc01d, 0x21, 0 + .dw 0xec40, 0xc01d, 0xec7f, 0xc01d, 0x21, 0 + .dw 0xecc0, 0xc01d, 0xecff, 0xc01d, 0x21, 0 + .dw 0xed40, 0xc01d, 0xed7f, 0xc01d, 0x21, 0 + .dw 0xedc0, 0xc01d, 0xedff, 0xc01d, 0x21, 0 + .dw 0xee40, 0xc01d, 0xee7f, 0xc01d, 0x21, 0 + .dw 0xeec0, 0xc01d, 0xeeff, 0xc01d, 0x21, 0 + .dw 0xef40, 0xc01d, 0xef7f, 0xc01d, 0x21, 0 + .dw 0xefc0, 0xc01d, 0xefff, 0xc01d, 0x21, 0 + .dw 0xf040, 0xc01d, 0xf07f, 0xc01d, 0x21, 0 + .dw 0xf0c0, 0xc01d, 0xf0ff, 0xc01d, 0x21, 0 + .dw 0xf140, 0xc01d, 0xf17f, 0xc01d, 0x21, 0 + .dw 0xf1c0, 0xc01d, 0xf1ff, 0xc01d, 0x21, 0 + .dw 0xf240, 0xc01d, 0xf27f, 0xc01d, 0x21, 0 + .dw 0xf2c0, 0xc01d, 0xf2ff, 0xc01d, 0x21, 0 + .dw 0xf340, 0xc01d, 0xf37f, 0xc01d, 0x21, 0 + .dw 0xf3c0, 0xc01d, 0xf3ff, 0xc01d, 0x21, 0 + .dw 0xf440, 0xc01d, 0xf47f, 0xc01d, 0x21, 0 + .dw 0xf4c0, 0xc01d, 0xf4ff, 0xc01d, 0x21, 0 + .dw 0xf540, 0xc01d, 0xf57f, 0xc01d, 0x21, 0 + .dw 0xf5c0, 0xc01d, 0xf5ff, 0xc01d, 0x21, 0 + .dw 0xf640, 0xc01d, 0xf67f, 0xc01d, 0x21, 0 + .dw 0xf6c0, 0xc01d, 0xf6ff, 0xc01d, 0x21, 0 + .dw 0xf740, 0xc01d, 0xf77f, 0xc01d, 0x21, 0 + .dw 0xf7c0, 0xc01d, 0xf7ff, 0xc01d, 0x21, 0 + .dw 0xf840, 0xc01d, 0xf87f, 0xc01d, 0x21, 0 + .dw 0xf8c0, 0xc01d, 0xf8ff, 0xc01d, 0x21, 0 + .dw 0xf940, 0xc01d, 0xf97f, 0xc01d, 0x21, 0 + .dw 0xf9c0, 0xc01d, 0xffff, 0xc01d, 0x21, 0 + .dw 0x0040, 0xc01e, 0x007f, 0xc01e, 0x21, 0 + .dw 0x00c0, 0xc01e, 0x00ff, 0xc01e, 0x21, 0 + .dw 0x0140, 0xc01e, 0x017f, 0xc01e, 0x21, 0 + .dw 0x01c0, 0xc01e, 0x01ff, 0xc01e, 0x21, 0 + .dw 0x0240, 0xc01e, 0x027f, 0xc01e, 0x21, 0 + .dw 0x02c0, 0xc01e, 0x02ff, 0xc01e, 0x21, 0 + .dw 0x0340, 0xc01e, 0x037f, 0xc01e, 0x21, 0 + .dw 0x03c0, 0xc01e, 0x03ff, 0xc01e, 0x21, 0 + .dw 0x0440, 0xc01e, 0x047f, 0xc01e, 0x21, 0 + .dw 0x04c0, 0xc01e, 0x04ff, 0xc01e, 0x21, 0 + .dw 0x0540, 0xc01e, 0x057f, 0xc01e, 0x21, 0 + .dw 0x05c0, 0xc01e, 0x05ff, 0xc01e, 0x21, 0 + .dw 0x0640, 0xc01e, 0x067f, 0xc01e, 0x21, 0 + .dw 0x06c0, 0xc01e, 0x06ff, 0xc01e, 0x21, 0 + .dw 0x0740, 0xc01e, 0x077f, 0xc01e, 0x21, 0 + .dw 0x07c0, 0xc01e, 0x07ff, 0xc01e, 0x21, 0 + .dw 0x0840, 0xc01e, 0x087f, 0xc01e, 0x21, 0 + .dw 0x08c0, 0xc01e, 0x08ff, 0xc01e, 0x21, 0 + .dw 0x0940, 0xc01e, 0x097f, 0xc01e, 0x21, 0 + .dw 0x09c0, 0xc01e, 0x09ff, 0xc01e, 0x21, 0 + .dw 0x0a40, 0xc01e, 0x0a7f, 0xc01e, 0x21, 0 + .dw 0x0ac0, 0xc01e, 0x0aff, 0xc01e, 0x21, 0 + .dw 0x0b40, 0xc01e, 0x0b7f, 0xc01e, 0x21, 0 + .dw 0x0bc0, 0xc01e, 0x0bff, 0xc01e, 0x21, 0 + .dw 0x0c40, 0xc01e, 0x0c7f, 0xc01e, 0x21, 0 + .dw 0x0cc0, 0xc01e, 0x0cff, 0xc01e, 0x21, 0 + .dw 0x0d40, 0xc01e, 0x0d7f, 0xc01e, 0x21, 0 + .dw 0x0dc0, 0xc01e, 0x0dff, 0xc01e, 0x21, 0 + .dw 0x0e40, 0xc01e, 0x0e7f, 0xc01e, 0x21, 0 + .dw 0x0ec0, 0xc01e, 0x0eff, 0xc01e, 0x21, 0 + .dw 0x0f40, 0xc01e, 0x0f7f, 0xc01e, 0x21, 0 + .dw 0x0fc0, 0xc01e, 0x0fff, 0xc01e, 0x21, 0 + .dw 0x1040, 0xc01e, 0x107f, 0xc01e, 0x21, 0 + .dw 0x10c0, 0xc01e, 0x10ff, 0xc01e, 0x21, 0 + .dw 0x1140, 0xc01e, 0x117f, 0xc01e, 0x21, 0 + .dw 0x11c0, 0xc01e, 0x11ff, 0xc01e, 0x21, 0 + .dw 0x1240, 0xc01e, 0x127f, 0xc01e, 0x21, 0 + .dw 0x12c0, 0xc01e, 0x12ff, 0xc01e, 0x21, 0 + .dw 0x1340, 0xc01e, 0x137f, 0xc01e, 0x21, 0 + .dw 0x13c0, 0xc01e, 0x13ff, 0xc01e, 0x21, 0 + .dw 0x1440, 0xc01e, 0x147f, 0xc01e, 0x21, 0 + .dw 0x14c0, 0xc01e, 0x14ff, 0xc01e, 0x21, 0 + .dw 0x1540, 0xc01e, 0x157f, 0xc01e, 0x21, 0 + .dw 0x15c0, 0xc01e, 0x15ff, 0xc01e, 0x21, 0 + .dw 0x1640, 0xc01e, 0x167f, 0xc01e, 0x21, 0 + .dw 0x16c0, 0xc01e, 0x16ff, 0xc01e, 0x21, 0 + .dw 0x1740, 0xc01e, 0x177f, 0xc01e, 0x21, 0 + .dw 0x17c0, 0xc01e, 0x17ff, 0xc01e, 0x21, 0 + .dw 0x1840, 0xc01e, 0x187f, 0xc01e, 0x21, 0 + .dw 0x18c0, 0xc01e, 0x18ff, 0xc01e, 0x21, 0 + .dw 0x1940, 0xc01e, 0x197f, 0xc01e, 0x21, 0 + .dw 0x19c0, 0xc01e, 0x1fff, 0xc01e, 0x21, 0 + .dw 0x2040, 0xc01e, 0x207f, 0xc01e, 0x21, 0 + .dw 0x20c0, 0xc01e, 0x20ff, 0xc01e, 0x21, 0 + .dw 0x2140, 0xc01e, 0x217f, 0xc01e, 0x21, 0 + .dw 0x21c0, 0xc01e, 0x21ff, 0xc01e, 0x21, 0 + .dw 0x2240, 0xc01e, 0x227f, 0xc01e, 0x21, 0 + .dw 0x22c0, 0xc01e, 0x22ff, 0xc01e, 0x21, 0 + .dw 0x2340, 0xc01e, 0x237f, 0xc01e, 0x21, 0 + .dw 0x23c0, 0xc01e, 0x23ff, 0xc01e, 0x21, 0 + .dw 0x2440, 0xc01e, 0x247f, 0xc01e, 0x21, 0 + .dw 0x24c0, 0xc01e, 0x24ff, 0xc01e, 0x21, 0 + .dw 0x2540, 0xc01e, 0x257f, 0xc01e, 0x21, 0 + .dw 0x25c0, 0xc01e, 0x25ff, 0xc01e, 0x21, 0 + .dw 0x2640, 0xc01e, 0x267f, 0xc01e, 0x21, 0 + .dw 0x26c0, 0xc01e, 0x26ff, 0xc01e, 0x21, 0 + .dw 0x2740, 0xc01e, 0x277f, 0xc01e, 0x21, 0 + .dw 0x27c0, 0xc01e, 0x27ff, 0xc01e, 0x21, 0 + .dw 0x2840, 0xc01e, 0x287f, 0xc01e, 0x21, 0 + .dw 0x28c0, 0xc01e, 0x28ff, 0xc01e, 0x21, 0 + .dw 0x2940, 0xc01e, 0x297f, 0xc01e, 0x21, 0 + .dw 0x29c0, 0xc01e, 0x29ff, 0xc01e, 0x21, 0 + .dw 0x2a40, 0xc01e, 0x2a7f, 0xc01e, 0x21, 0 + .dw 0x2ac0, 0xc01e, 0x2aff, 0xc01e, 0x21, 0 + .dw 0x2b40, 0xc01e, 0x2b7f, 0xc01e, 0x21, 0 + .dw 0x2bc0, 0xc01e, 0x2bff, 0xc01e, 0x21, 0 + .dw 0x2c40, 0xc01e, 0x2c7f, 0xc01e, 0x21, 0 + .dw 0x2cc0, 0xc01e, 0x2cff, 0xc01e, 0x21, 0 + .dw 0x2d40, 0xc01e, 0x2d7f, 0xc01e, 0x21, 0 + .dw 0x2dc0, 0xc01e, 0x2dff, 0xc01e, 0x21, 0 + .dw 0x2e40, 0xc01e, 0x2e7f, 0xc01e, 0x21, 0 + .dw 0x2ec0, 0xc01e, 0x2eff, 0xc01e, 0x21, 0 + .dw 0x2f40, 0xc01e, 0x2f7f, 0xc01e, 0x21, 0 + .dw 0x2fc0, 0xc01e, 0x2fff, 0xc01e, 0x21, 0 + .dw 0x3040, 0xc01e, 0x307f, 0xc01e, 0x21, 0 + .dw 0x30c0, 0xc01e, 0x30ff, 0xc01e, 0x21, 0 + .dw 0x3140, 0xc01e, 0x317f, 0xc01e, 0x21, 0 + .dw 0x31c0, 0xc01e, 0x31ff, 0xc01e, 0x21, 0 + .dw 0x3240, 0xc01e, 0x327f, 0xc01e, 0x21, 0 + .dw 0x32c0, 0xc01e, 0x32ff, 0xc01e, 0x21, 0 + .dw 0x3340, 0xc01e, 0x337f, 0xc01e, 0x21, 0 + .dw 0x33c0, 0xc01e, 0x33ff, 0xc01e, 0x21, 0 + .dw 0x3440, 0xc01e, 0x347f, 0xc01e, 0x21, 0 + .dw 0x34c0, 0xc01e, 0x34ff, 0xc01e, 0x21, 0 + .dw 0x3540, 0xc01e, 0x357f, 0xc01e, 0x21, 0 + .dw 0x35c0, 0xc01e, 0x35ff, 0xc01e, 0x21, 0 + .dw 0x3640, 0xc01e, 0x367f, 0xc01e, 0x21, 0 + .dw 0x36c0, 0xc01e, 0x36ff, 0xc01e, 0x21, 0 + .dw 0x3740, 0xc01e, 0x377f, 0xc01e, 0x21, 0 + .dw 0x37c0, 0xc01e, 0x37ff, 0xc01e, 0x21, 0 + .dw 0x3840, 0xc01e, 0x387f, 0xc01e, 0x21, 0 + .dw 0x38c0, 0xc01e, 0x38ff, 0xc01e, 0x21, 0 + .dw 0x3940, 0xc01e, 0x397f, 0xc01e, 0x21, 0 + .dw 0x39c0, 0xc01e, 0x3fff, 0xc01e, 0x21, 0 + .dw 0x4040, 0xc01e, 0x407f, 0xc01e, 0x21, 0 + .dw 0x40c0, 0xc01e, 0x40ff, 0xc01e, 0x21, 0 + .dw 0x4140, 0xc01e, 0x417f, 0xc01e, 0x21, 0 + .dw 0x41c0, 0xc01e, 0x41ff, 0xc01e, 0x21, 0 + .dw 0x4240, 0xc01e, 0x427f, 0xc01e, 0x21, 0 + .dw 0x42c0, 0xc01e, 0x42ff, 0xc01e, 0x21, 0 + .dw 0x4340, 0xc01e, 0x437f, 0xc01e, 0x21, 0 + .dw 0x43c0, 0xc01e, 0x43ff, 0xc01e, 0x21, 0 + .dw 0x4440, 0xc01e, 0x447f, 0xc01e, 0x21, 0 + .dw 0x44c0, 0xc01e, 0x44ff, 0xc01e, 0x21, 0 + .dw 0x4540, 0xc01e, 0x457f, 0xc01e, 0x21, 0 + .dw 0x45c0, 0xc01e, 0x45ff, 0xc01e, 0x21, 0 + .dw 0x4640, 0xc01e, 0x467f, 0xc01e, 0x21, 0 + .dw 0x46c0, 0xc01e, 0x46ff, 0xc01e, 0x21, 0 + .dw 0x4740, 0xc01e, 0x477f, 0xc01e, 0x21, 0 + .dw 0x47c0, 0xc01e, 0x47ff, 0xc01e, 0x21, 0 + .dw 0x4840, 0xc01e, 0x487f, 0xc01e, 0x21, 0 + .dw 0x48c0, 0xc01e, 0x48ff, 0xc01e, 0x21, 0 + .dw 0x4940, 0xc01e, 0x497f, 0xc01e, 0x21, 0 + .dw 0x49c0, 0xc01e, 0x49ff, 0xc01e, 0x21, 0 + .dw 0x4a40, 0xc01e, 0x4a7f, 0xc01e, 0x21, 0 + .dw 0x4ac0, 0xc01e, 0x4aff, 0xc01e, 0x21, 0 + .dw 0x4b40, 0xc01e, 0x4b7f, 0xc01e, 0x21, 0 + .dw 0x4bc0, 0xc01e, 0x4bff, 0xc01e, 0x21, 0 + .dw 0x4c40, 0xc01e, 0x4c7f, 0xc01e, 0x21, 0 + .dw 0x4cc0, 0xc01e, 0x4cff, 0xc01e, 0x21, 0 + .dw 0x4d40, 0xc01e, 0x4d7f, 0xc01e, 0x21, 0 + .dw 0x4dc0, 0xc01e, 0x4dff, 0xc01e, 0x21, 0 + .dw 0x4e40, 0xc01e, 0x4e7f, 0xc01e, 0x21, 0 + .dw 0x4ec0, 0xc01e, 0x4eff, 0xc01e, 0x21, 0 + .dw 0x4f40, 0xc01e, 0x4f7f, 0xc01e, 0x21, 0 + .dw 0x4fc0, 0xc01e, 0x4fff, 0xc01e, 0x21, 0 + .dw 0x5040, 0xc01e, 0x507f, 0xc01e, 0x21, 0 + .dw 0x50c0, 0xc01e, 0x50ff, 0xc01e, 0x21, 0 + .dw 0x5140, 0xc01e, 0x517f, 0xc01e, 0x21, 0 + .dw 0x51c0, 0xc01e, 0x51ff, 0xc01e, 0x21, 0 + .dw 0x5240, 0xc01e, 0x527f, 0xc01e, 0x21, 0 + .dw 0x52c0, 0xc01e, 0x52ff, 0xc01e, 0x21, 0 + .dw 0x5340, 0xc01e, 0x537f, 0xc01e, 0x21, 0 + .dw 0x53c0, 0xc01e, 0x53ff, 0xc01e, 0x21, 0 + .dw 0x5440, 0xc01e, 0x547f, 0xc01e, 0x21, 0 + .dw 0x54c0, 0xc01e, 0x54ff, 0xc01e, 0x21, 0 + .dw 0x5540, 0xc01e, 0x557f, 0xc01e, 0x21, 0 + .dw 0x55c0, 0xc01e, 0x55ff, 0xc01e, 0x21, 0 + .dw 0x5640, 0xc01e, 0x567f, 0xc01e, 0x21, 0 + .dw 0x56c0, 0xc01e, 0x56ff, 0xc01e, 0x21, 0 + .dw 0x5740, 0xc01e, 0x577f, 0xc01e, 0x21, 0 + .dw 0x57c0, 0xc01e, 0x57ff, 0xc01e, 0x21, 0 + .dw 0x5840, 0xc01e, 0x587f, 0xc01e, 0x21, 0 + .dw 0x58c0, 0xc01e, 0x58ff, 0xc01e, 0x21, 0 + .dw 0x5940, 0xc01e, 0x597f, 0xc01e, 0x21, 0 + .dw 0x59c0, 0xc01e, 0x5fff, 0xc01e, 0x21, 0 + .dw 0x6040, 0xc01e, 0x607f, 0xc01e, 0x21, 0 + .dw 0x60c0, 0xc01e, 0x60ff, 0xc01e, 0x21, 0 + .dw 0x6140, 0xc01e, 0x617f, 0xc01e, 0x21, 0 + .dw 0x61c0, 0xc01e, 0x61ff, 0xc01e, 0x21, 0 + .dw 0x6240, 0xc01e, 0x627f, 0xc01e, 0x21, 0 + .dw 0x62c0, 0xc01e, 0x62ff, 0xc01e, 0x21, 0 + .dw 0x6340, 0xc01e, 0x637f, 0xc01e, 0x21, 0 + .dw 0x63c0, 0xc01e, 0x63ff, 0xc01e, 0x21, 0 + .dw 0x6440, 0xc01e, 0x647f, 0xc01e, 0x21, 0 + .dw 0x64c0, 0xc01e, 0x64ff, 0xc01e, 0x21, 0 + .dw 0x6540, 0xc01e, 0x657f, 0xc01e, 0x21, 0 + .dw 0x65c0, 0xc01e, 0x65ff, 0xc01e, 0x21, 0 + .dw 0x6640, 0xc01e, 0x667f, 0xc01e, 0x21, 0 + .dw 0x66c0, 0xc01e, 0x66ff, 0xc01e, 0x21, 0 + .dw 0x6740, 0xc01e, 0x677f, 0xc01e, 0x21, 0 + .dw 0x67c0, 0xc01e, 0x67ff, 0xc01e, 0x21, 0 + .dw 0x6840, 0xc01e, 0x687f, 0xc01e, 0x21, 0 + .dw 0x68c0, 0xc01e, 0x68ff, 0xc01e, 0x21, 0 + .dw 0x6940, 0xc01e, 0x697f, 0xc01e, 0x21, 0 + .dw 0x69c0, 0xc01e, 0x69ff, 0xc01e, 0x21, 0 + .dw 0x6a40, 0xc01e, 0x6a7f, 0xc01e, 0x21, 0 + .dw 0x6ac0, 0xc01e, 0x6aff, 0xc01e, 0x21, 0 + .dw 0x6b40, 0xc01e, 0x6b7f, 0xc01e, 0x21, 0 + .dw 0x6bc0, 0xc01e, 0x6bff, 0xc01e, 0x21, 0 + .dw 0x6c40, 0xc01e, 0x6c7f, 0xc01e, 0x21, 0 + .dw 0x6cc0, 0xc01e, 0x6cff, 0xc01e, 0x21, 0 + .dw 0x6d40, 0xc01e, 0x6d7f, 0xc01e, 0x21, 0 + .dw 0x6dc0, 0xc01e, 0x6dff, 0xc01e, 0x21, 0 + .dw 0x6e40, 0xc01e, 0x6e7f, 0xc01e, 0x21, 0 + .dw 0x6ec0, 0xc01e, 0x6eff, 0xc01e, 0x21, 0 + .dw 0x6f40, 0xc01e, 0x6f7f, 0xc01e, 0x21, 0 + .dw 0x6fc0, 0xc01e, 0x6fff, 0xc01e, 0x21, 0 + .dw 0x7040, 0xc01e, 0x707f, 0xc01e, 0x21, 0 + .dw 0x70c0, 0xc01e, 0x70ff, 0xc01e, 0x21, 0 + .dw 0x7140, 0xc01e, 0x717f, 0xc01e, 0x21, 0 + .dw 0x71c0, 0xc01e, 0x71ff, 0xc01e, 0x21, 0 + .dw 0x7240, 0xc01e, 0x727f, 0xc01e, 0x21, 0 + .dw 0x72c0, 0xc01e, 0x72ff, 0xc01e, 0x21, 0 + .dw 0x7340, 0xc01e, 0x737f, 0xc01e, 0x21, 0 + .dw 0x73c0, 0xc01e, 0x73ff, 0xc01e, 0x21, 0 + .dw 0x7440, 0xc01e, 0x747f, 0xc01e, 0x21, 0 + .dw 0x74c0, 0xc01e, 0x74ff, 0xc01e, 0x21, 0 + .dw 0x7540, 0xc01e, 0x757f, 0xc01e, 0x21, 0 + .dw 0x75c0, 0xc01e, 0x75ff, 0xc01e, 0x21, 0 + .dw 0x7640, 0xc01e, 0x767f, 0xc01e, 0x21, 0 + .dw 0x76c0, 0xc01e, 0x76ff, 0xc01e, 0x21, 0 + .dw 0x7740, 0xc01e, 0x777f, 0xc01e, 0x21, 0 + .dw 0x77c0, 0xc01e, 0x77ff, 0xc01e, 0x21, 0 + .dw 0x7840, 0xc01e, 0x787f, 0xc01e, 0x21, 0 + .dw 0x78c0, 0xc01e, 0x78ff, 0xc01e, 0x21, 0 + .dw 0x7940, 0xc01e, 0x797f, 0xc01e, 0x21, 0 + .dw 0x79c0, 0xc01e, 0x7fff, 0xc01e, 0x21, 0 + .dw 0x8040, 0xc01e, 0x807f, 0xc01e, 0x21, 0 + .dw 0x80c0, 0xc01e, 0x80ff, 0xc01e, 0x21, 0 + .dw 0x8140, 0xc01e, 0x817f, 0xc01e, 0x21, 0 + .dw 0x81c0, 0xc01e, 0x81ff, 0xc01e, 0x21, 0 + .dw 0x8240, 0xc01e, 0x827f, 0xc01e, 0x21, 0 + .dw 0x82c0, 0xc01e, 0x82ff, 0xc01e, 0x21, 0 + .dw 0x8340, 0xc01e, 0x837f, 0xc01e, 0x21, 0 + .dw 0x83c0, 0xc01e, 0x83ff, 0xc01e, 0x21, 0 + .dw 0x8440, 0xc01e, 0x847f, 0xc01e, 0x21, 0 + .dw 0x84c0, 0xc01e, 0x84ff, 0xc01e, 0x21, 0 + .dw 0x8540, 0xc01e, 0x857f, 0xc01e, 0x21, 0 + .dw 0x85c0, 0xc01e, 0x85ff, 0xc01e, 0x21, 0 + .dw 0x8640, 0xc01e, 0x867f, 0xc01e, 0x21, 0 + .dw 0x86c0, 0xc01e, 0x86ff, 0xc01e, 0x21, 0 + .dw 0x8740, 0xc01e, 0x877f, 0xc01e, 0x21, 0 + .dw 0x87c0, 0xc01e, 0x87ff, 0xc01e, 0x21, 0 + .dw 0x8840, 0xc01e, 0x887f, 0xc01e, 0x21, 0 + .dw 0x88c0, 0xc01e, 0x88ff, 0xc01e, 0x21, 0 + .dw 0x8940, 0xc01e, 0x897f, 0xc01e, 0x21, 0 + .dw 0x89c0, 0xc01e, 0x89ff, 0xc01e, 0x21, 0 + .dw 0x8a40, 0xc01e, 0x8a7f, 0xc01e, 0x21, 0 + .dw 0x8ac0, 0xc01e, 0x8aff, 0xc01e, 0x21, 0 + .dw 0x8b40, 0xc01e, 0x8b7f, 0xc01e, 0x21, 0 + .dw 0x8bc0, 0xc01e, 0x8bff, 0xc01e, 0x21, 0 + .dw 0x8c40, 0xc01e, 0x8c7f, 0xc01e, 0x21, 0 + .dw 0x8cc0, 0xc01e, 0x8cff, 0xc01e, 0x21, 0 + .dw 0x8d40, 0xc01e, 0x8d7f, 0xc01e, 0x21, 0 + .dw 0x8dc0, 0xc01e, 0x8dff, 0xc01e, 0x21, 0 + .dw 0x8e40, 0xc01e, 0x8e7f, 0xc01e, 0x21, 0 + .dw 0x8ec0, 0xc01e, 0x8eff, 0xc01e, 0x21, 0 + .dw 0x8f40, 0xc01e, 0x8f7f, 0xc01e, 0x21, 0 + .dw 0x8fc0, 0xc01e, 0x8fff, 0xc01e, 0x21, 0 + .dw 0x9040, 0xc01e, 0x907f, 0xc01e, 0x21, 0 + .dw 0x90c0, 0xc01e, 0x90ff, 0xc01e, 0x21, 0 + .dw 0x9140, 0xc01e, 0x917f, 0xc01e, 0x21, 0 + .dw 0x91c0, 0xc01e, 0x91ff, 0xc01e, 0x21, 0 + .dw 0x9240, 0xc01e, 0x927f, 0xc01e, 0x21, 0 + .dw 0x92c0, 0xc01e, 0x92ff, 0xc01e, 0x21, 0 + .dw 0x9340, 0xc01e, 0x937f, 0xc01e, 0x21, 0 + .dw 0x93c0, 0xc01e, 0x93ff, 0xc01e, 0x21, 0 + .dw 0x9440, 0xc01e, 0x947f, 0xc01e, 0x21, 0 + .dw 0x94c0, 0xc01e, 0x94ff, 0xc01e, 0x21, 0 + .dw 0x9540, 0xc01e, 0x957f, 0xc01e, 0x21, 0 + .dw 0x95c0, 0xc01e, 0x95ff, 0xc01e, 0x21, 0 + .dw 0x9640, 0xc01e, 0x967f, 0xc01e, 0x21, 0 + .dw 0x96c0, 0xc01e, 0x96ff, 0xc01e, 0x21, 0 + .dw 0x9740, 0xc01e, 0x977f, 0xc01e, 0x21, 0 + .dw 0x97c0, 0xc01e, 0x97ff, 0xc01e, 0x21, 0 + .dw 0x9840, 0xc01e, 0x987f, 0xc01e, 0x21, 0 + .dw 0x98c0, 0xc01e, 0x98ff, 0xc01e, 0x21, 0 + .dw 0x9940, 0xc01e, 0x997f, 0xc01e, 0x21, 0 + .dw 0x99c0, 0xc01e, 0x9fff, 0xc01e, 0x21, 0 + .dw 0xa040, 0xc01e, 0xa07f, 0xc01e, 0x21, 0 + .dw 0xa0c0, 0xc01e, 0xa0ff, 0xc01e, 0x21, 0 + .dw 0xa140, 0xc01e, 0xa17f, 0xc01e, 0x21, 0 + .dw 0xa1c0, 0xc01e, 0xa1ff, 0xc01e, 0x21, 0 + .dw 0xa240, 0xc01e, 0xa27f, 0xc01e, 0x21, 0 + .dw 0xa2c0, 0xc01e, 0xa2ff, 0xc01e, 0x21, 0 + .dw 0xa340, 0xc01e, 0xa37f, 0xc01e, 0x21, 0 + .dw 0xa3c0, 0xc01e, 0xa3ff, 0xc01e, 0x21, 0 + .dw 0xa440, 0xc01e, 0xa47f, 0xc01e, 0x21, 0 + .dw 0xa4c0, 0xc01e, 0xa4ff, 0xc01e, 0x21, 0 + .dw 0xa540, 0xc01e, 0xa57f, 0xc01e, 0x21, 0 + .dw 0xa5c0, 0xc01e, 0xa5ff, 0xc01e, 0x21, 0 + .dw 0xa640, 0xc01e, 0xa67f, 0xc01e, 0x21, 0 + .dw 0xa6c0, 0xc01e, 0xa6ff, 0xc01e, 0x21, 0 + .dw 0xa740, 0xc01e, 0xa77f, 0xc01e, 0x21, 0 + .dw 0xa7c0, 0xc01e, 0xa7ff, 0xc01e, 0x21, 0 + .dw 0xa840, 0xc01e, 0xa87f, 0xc01e, 0x21, 0 + .dw 0xa8c0, 0xc01e, 0xa8ff, 0xc01e, 0x21, 0 + .dw 0xa940, 0xc01e, 0xa97f, 0xc01e, 0x21, 0 + .dw 0xa9c0, 0xc01e, 0xa9ff, 0xc01e, 0x21, 0 + .dw 0xaa40, 0xc01e, 0xaa7f, 0xc01e, 0x21, 0 + .dw 0xaac0, 0xc01e, 0xaaff, 0xc01e, 0x21, 0 + .dw 0xab40, 0xc01e, 0xab7f, 0xc01e, 0x21, 0 + .dw 0xabc0, 0xc01e, 0xabff, 0xc01e, 0x21, 0 + .dw 0xac40, 0xc01e, 0xac7f, 0xc01e, 0x21, 0 + .dw 0xacc0, 0xc01e, 0xacff, 0xc01e, 0x21, 0 + .dw 0xad40, 0xc01e, 0xad7f, 0xc01e, 0x21, 0 + .dw 0xadc0, 0xc01e, 0xadff, 0xc01e, 0x21, 0 + .dw 0xae40, 0xc01e, 0xae7f, 0xc01e, 0x21, 0 + .dw 0xaec0, 0xc01e, 0xaeff, 0xc01e, 0x21, 0 + .dw 0xaf40, 0xc01e, 0xaf7f, 0xc01e, 0x21, 0 + .dw 0xafc0, 0xc01e, 0xafff, 0xc01e, 0x21, 0 + .dw 0xb040, 0xc01e, 0xb07f, 0xc01e, 0x21, 0 + .dw 0xb0c0, 0xc01e, 0xb0ff, 0xc01e, 0x21, 0 + .dw 0xb140, 0xc01e, 0xb17f, 0xc01e, 0x21, 0 + .dw 0xb1c0, 0xc01e, 0xb1ff, 0xc01e, 0x21, 0 + .dw 0xb240, 0xc01e, 0xb27f, 0xc01e, 0x21, 0 + .dw 0xb2c0, 0xc01e, 0xb2ff, 0xc01e, 0x21, 0 + .dw 0xb340, 0xc01e, 0xb37f, 0xc01e, 0x21, 0 + .dw 0xb3c0, 0xc01e, 0xb3ff, 0xc01e, 0x21, 0 + .dw 0xb440, 0xc01e, 0xb47f, 0xc01e, 0x21, 0 + .dw 0xb4c0, 0xc01e, 0xb4ff, 0xc01e, 0x21, 0 + .dw 0xb540, 0xc01e, 0xb57f, 0xc01e, 0x21, 0 + .dw 0xb5c0, 0xc01e, 0xb5ff, 0xc01e, 0x21, 0 + .dw 0xb640, 0xc01e, 0xb67f, 0xc01e, 0x21, 0 + .dw 0xb6c0, 0xc01e, 0xb6ff, 0xc01e, 0x21, 0 + .dw 0xb740, 0xc01e, 0xb77f, 0xc01e, 0x21, 0 + .dw 0xb7c0, 0xc01e, 0xb7ff, 0xc01e, 0x21, 0 + .dw 0xb840, 0xc01e, 0xb87f, 0xc01e, 0x21, 0 + .dw 0xb8c0, 0xc01e, 0xb8ff, 0xc01e, 0x21, 0 + .dw 0xb940, 0xc01e, 0xb97f, 0xc01e, 0x21, 0 + .dw 0xb9c0, 0xc01e, 0xbfff, 0xc01e, 0x21, 0 + .dw 0xc040, 0xc01e, 0xc07f, 0xc01e, 0x21, 0 + .dw 0xc0c0, 0xc01e, 0xc0ff, 0xc01e, 0x21, 0 + .dw 0xc140, 0xc01e, 0xc17f, 0xc01e, 0x21, 0 + .dw 0xc1c0, 0xc01e, 0xc1ff, 0xc01e, 0x21, 0 + .dw 0xc240, 0xc01e, 0xc27f, 0xc01e, 0x21, 0 + .dw 0xc2c0, 0xc01e, 0xc2ff, 0xc01e, 0x21, 0 + .dw 0xc340, 0xc01e, 0xc37f, 0xc01e, 0x21, 0 + .dw 0xc3c0, 0xc01e, 0xc3ff, 0xc01e, 0x21, 0 + .dw 0xc440, 0xc01e, 0xc47f, 0xc01e, 0x21, 0 + .dw 0xc4c0, 0xc01e, 0xc4ff, 0xc01e, 0x21, 0 + .dw 0xc540, 0xc01e, 0xc57f, 0xc01e, 0x21, 0 + .dw 0xc5c0, 0xc01e, 0xc5ff, 0xc01e, 0x21, 0 + .dw 0xc640, 0xc01e, 0xc67f, 0xc01e, 0x21, 0 + .dw 0xc6c0, 0xc01e, 0xc6ff, 0xc01e, 0x21, 0 + .dw 0xc740, 0xc01e, 0xc77f, 0xc01e, 0x21, 0 + .dw 0xc7c0, 0xc01e, 0xc7ff, 0xc01e, 0x21, 0 + .dw 0xc840, 0xc01e, 0xc87f, 0xc01e, 0x21, 0 + .dw 0xc8c0, 0xc01e, 0xc8ff, 0xc01e, 0x21, 0 + .dw 0xc940, 0xc01e, 0xc97f, 0xc01e, 0x21, 0 + .dw 0xc9c0, 0xc01e, 0xc9ff, 0xc01e, 0x21, 0 + .dw 0xca40, 0xc01e, 0xca7f, 0xc01e, 0x21, 0 + .dw 0xcac0, 0xc01e, 0xcaff, 0xc01e, 0x21, 0 + .dw 0xcb40, 0xc01e, 0xcb7f, 0xc01e, 0x21, 0 + .dw 0xcbc0, 0xc01e, 0xcbff, 0xc01e, 0x21, 0 + .dw 0xcc40, 0xc01e, 0xcc7f, 0xc01e, 0x21, 0 + .dw 0xccc0, 0xc01e, 0xccff, 0xc01e, 0x21, 0 + .dw 0xcd40, 0xc01e, 0xcd7f, 0xc01e, 0x21, 0 + .dw 0xcdc0, 0xc01e, 0xcdff, 0xc01e, 0x21, 0 + .dw 0xce40, 0xc01e, 0xce7f, 0xc01e, 0x21, 0 + .dw 0xcec0, 0xc01e, 0xceff, 0xc01e, 0x21, 0 + .dw 0xcf40, 0xc01e, 0xcf7f, 0xc01e, 0x21, 0 + .dw 0xcfc0, 0xc01e, 0xcfff, 0xc01e, 0x21, 0 + .dw 0xd040, 0xc01e, 0xd07f, 0xc01e, 0x21, 0 + .dw 0xd0c0, 0xc01e, 0xd0ff, 0xc01e, 0x21, 0 + .dw 0xd140, 0xc01e, 0xd17f, 0xc01e, 0x21, 0 + .dw 0xd1c0, 0xc01e, 0xd1ff, 0xc01e, 0x21, 0 + .dw 0xd240, 0xc01e, 0xd27f, 0xc01e, 0x21, 0 + .dw 0xd2c0, 0xc01e, 0xd2ff, 0xc01e, 0x21, 0 + .dw 0xd340, 0xc01e, 0xd37f, 0xc01e, 0x21, 0 + .dw 0xd3c0, 0xc01e, 0xd3ff, 0xc01e, 0x21, 0 + .dw 0xd440, 0xc01e, 0xd47f, 0xc01e, 0x21, 0 + .dw 0xd4c0, 0xc01e, 0xd4ff, 0xc01e, 0x21, 0 + .dw 0xd540, 0xc01e, 0xd57f, 0xc01e, 0x21, 0 + .dw 0xd5c0, 0xc01e, 0xd5ff, 0xc01e, 0x21, 0 + .dw 0xd640, 0xc01e, 0xd67f, 0xc01e, 0x21, 0 + .dw 0xd6c0, 0xc01e, 0xd6ff, 0xc01e, 0x21, 0 + .dw 0xd740, 0xc01e, 0xd77f, 0xc01e, 0x21, 0 + .dw 0xd7c0, 0xc01e, 0xd7ff, 0xc01e, 0x21, 0 + .dw 0xd840, 0xc01e, 0xd87f, 0xc01e, 0x21, 0 + .dw 0xd8c0, 0xc01e, 0xd8ff, 0xc01e, 0x21, 0 + .dw 0xd940, 0xc01e, 0xd97f, 0xc01e, 0x21, 0 + .dw 0xd9c0, 0xc01e, 0xdfff, 0xc01e, 0x21, 0 + .dw 0xe040, 0xc01e, 0xe07f, 0xc01e, 0x21, 0 + .dw 0xe0c0, 0xc01e, 0xe0ff, 0xc01e, 0x21, 0 + .dw 0xe140, 0xc01e, 0xe17f, 0xc01e, 0x21, 0 + .dw 0xe1c0, 0xc01e, 0xe1ff, 0xc01e, 0x21, 0 + .dw 0xe240, 0xc01e, 0xe27f, 0xc01e, 0x21, 0 + .dw 0xe2c0, 0xc01e, 0xe2ff, 0xc01e, 0x21, 0 + .dw 0xe340, 0xc01e, 0xe37f, 0xc01e, 0x21, 0 + .dw 0xe3c0, 0xc01e, 0xe3ff, 0xc01e, 0x21, 0 + .dw 0xe440, 0xc01e, 0xe47f, 0xc01e, 0x21, 0 + .dw 0xe4c0, 0xc01e, 0xe4ff, 0xc01e, 0x21, 0 + .dw 0xe540, 0xc01e, 0xe57f, 0xc01e, 0x21, 0 + .dw 0xe5c0, 0xc01e, 0xe5ff, 0xc01e, 0x21, 0 + .dw 0xe640, 0xc01e, 0xe67f, 0xc01e, 0x21, 0 + .dw 0xe6c0, 0xc01e, 0xe6ff, 0xc01e, 0x21, 0 + .dw 0xe740, 0xc01e, 0xe77f, 0xc01e, 0x21, 0 + .dw 0xe7c0, 0xc01e, 0xe7ff, 0xc01e, 0x21, 0 + .dw 0xe840, 0xc01e, 0xe87f, 0xc01e, 0x21, 0 + .dw 0xe8c0, 0xc01e, 0xe8ff, 0xc01e, 0x21, 0 + .dw 0xe940, 0xc01e, 0xe97f, 0xc01e, 0x21, 0 + .dw 0xe9c0, 0xc01e, 0xe9ff, 0xc01e, 0x21, 0 + .dw 0xea40, 0xc01e, 0xea7f, 0xc01e, 0x21, 0 + .dw 0xeac0, 0xc01e, 0xeaff, 0xc01e, 0x21, 0 + .dw 0xeb40, 0xc01e, 0xeb7f, 0xc01e, 0x21, 0 + .dw 0xebc0, 0xc01e, 0xebff, 0xc01e, 0x21, 0 + .dw 0xec40, 0xc01e, 0xec7f, 0xc01e, 0x21, 0 + .dw 0xecc0, 0xc01e, 0xecff, 0xc01e, 0x21, 0 + .dw 0xed40, 0xc01e, 0xed7f, 0xc01e, 0x21, 0 + .dw 0xedc0, 0xc01e, 0xedff, 0xc01e, 0x21, 0 + .dw 0xee40, 0xc01e, 0xee7f, 0xc01e, 0x21, 0 + .dw 0xeec0, 0xc01e, 0xeeff, 0xc01e, 0x21, 0 + .dw 0xef40, 0xc01e, 0xef7f, 0xc01e, 0x21, 0 + .dw 0xefc0, 0xc01e, 0xefff, 0xc01e, 0x21, 0 + .dw 0xf040, 0xc01e, 0xf07f, 0xc01e, 0x21, 0 + .dw 0xf0c0, 0xc01e, 0xf0ff, 0xc01e, 0x21, 0 + .dw 0xf140, 0xc01e, 0xf17f, 0xc01e, 0x21, 0 + .dw 0xf1c0, 0xc01e, 0xf1ff, 0xc01e, 0x21, 0 + .dw 0xf240, 0xc01e, 0xf27f, 0xc01e, 0x21, 0 + .dw 0xf2c0, 0xc01e, 0xf2ff, 0xc01e, 0x21, 0 + .dw 0xf340, 0xc01e, 0xf37f, 0xc01e, 0x21, 0 + .dw 0xf3c0, 0xc01e, 0xf3ff, 0xc01e, 0x21, 0 + .dw 0xf440, 0xc01e, 0xf47f, 0xc01e, 0x21, 0 + .dw 0xf4c0, 0xc01e, 0xf4ff, 0xc01e, 0x21, 0 + .dw 0xf540, 0xc01e, 0xf57f, 0xc01e, 0x21, 0 + .dw 0xf5c0, 0xc01e, 0xf5ff, 0xc01e, 0x21, 0 + .dw 0xf640, 0xc01e, 0xf67f, 0xc01e, 0x21, 0 + .dw 0xf6c0, 0xc01e, 0xf6ff, 0xc01e, 0x21, 0 + .dw 0xf740, 0xc01e, 0xf77f, 0xc01e, 0x21, 0 + .dw 0xf7c0, 0xc01e, 0xf7ff, 0xc01e, 0x21, 0 + .dw 0xf840, 0xc01e, 0xf87f, 0xc01e, 0x21, 0 + .dw 0xf8c0, 0xc01e, 0xf8ff, 0xc01e, 0x21, 0 + .dw 0xf940, 0xc01e, 0xf97f, 0xc01e, 0x21, 0 + .dw 0xf9c0, 0xc01e, 0xffff, 0xc01e, 0x21, 0 + .dw 0x0040, 0xc01f, 0x007f, 0xc01f, 0x21, 0 + .dw 0x00c0, 0xc01f, 0x00ff, 0xc01f, 0x21, 0 + .dw 0x0140, 0xc01f, 0x017f, 0xc01f, 0x21, 0 + .dw 0x01c0, 0xc01f, 0x01ff, 0xc01f, 0x21, 0 + .dw 0x0240, 0xc01f, 0x027f, 0xc01f, 0x21, 0 + .dw 0x02c0, 0xc01f, 0x02ff, 0xc01f, 0x21, 0 + .dw 0x0340, 0xc01f, 0x037f, 0xc01f, 0x21, 0 + .dw 0x03c0, 0xc01f, 0x03ff, 0xc01f, 0x21, 0 + .dw 0x0440, 0xc01f, 0x047f, 0xc01f, 0x21, 0 + .dw 0x04c0, 0xc01f, 0x04ff, 0xc01f, 0x21, 0 + .dw 0x0540, 0xc01f, 0x057f, 0xc01f, 0x21, 0 + .dw 0x05c0, 0xc01f, 0x05ff, 0xc01f, 0x21, 0 + .dw 0x0640, 0xc01f, 0x067f, 0xc01f, 0x21, 0 + .dw 0x06c0, 0xc01f, 0x06ff, 0xc01f, 0x21, 0 + .dw 0x0740, 0xc01f, 0x077f, 0xc01f, 0x21, 0 + .dw 0x07c0, 0xc01f, 0x07ff, 0xc01f, 0x21, 0 + .dw 0x0840, 0xc01f, 0x087f, 0xc01f, 0x21, 0 + .dw 0x08c0, 0xc01f, 0x08ff, 0xc01f, 0x21, 0 + .dw 0x0940, 0xc01f, 0x097f, 0xc01f, 0x21, 0 + .dw 0x09c0, 0xc01f, 0x09ff, 0xc01f, 0x21, 0 + .dw 0x0a40, 0xc01f, 0x0a7f, 0xc01f, 0x21, 0 + .dw 0x0ac0, 0xc01f, 0x0aff, 0xc01f, 0x21, 0 + .dw 0x0b40, 0xc01f, 0x0b7f, 0xc01f, 0x21, 0 + .dw 0x0bc0, 0xc01f, 0x0bff, 0xc01f, 0x21, 0 + .dw 0x0c40, 0xc01f, 0x0c7f, 0xc01f, 0x21, 0 + .dw 0x0cc0, 0xc01f, 0x0cff, 0xc01f, 0x21, 0 + .dw 0x0d40, 0xc01f, 0x0d7f, 0xc01f, 0x21, 0 + .dw 0x0dc0, 0xc01f, 0x0dff, 0xc01f, 0x21, 0 + .dw 0x0e40, 0xc01f, 0x0e7f, 0xc01f, 0x21, 0 + .dw 0x0ec0, 0xc01f, 0x0eff, 0xc01f, 0x21, 0 + .dw 0x0f40, 0xc01f, 0x0f7f, 0xc01f, 0x21, 0 + .dw 0x0fc0, 0xc01f, 0x0fff, 0xc01f, 0x21, 0 + .dw 0x1040, 0xc01f, 0x107f, 0xc01f, 0x21, 0 + .dw 0x10c0, 0xc01f, 0x10ff, 0xc01f, 0x21, 0 + .dw 0x1140, 0xc01f, 0x117f, 0xc01f, 0x21, 0 + .dw 0x11c0, 0xc01f, 0x11ff, 0xc01f, 0x21, 0 + .dw 0x1240, 0xc01f, 0x127f, 0xc01f, 0x21, 0 + .dw 0x12c0, 0xc01f, 0x12ff, 0xc01f, 0x21, 0 + .dw 0x1340, 0xc01f, 0x137f, 0xc01f, 0x21, 0 + .dw 0x13c0, 0xc01f, 0x13ff, 0xc01f, 0x21, 0 + .dw 0x1440, 0xc01f, 0x147f, 0xc01f, 0x21, 0 + .dw 0x14c0, 0xc01f, 0x14ff, 0xc01f, 0x21, 0 + .dw 0x1540, 0xc01f, 0x157f, 0xc01f, 0x21, 0 + .dw 0x15c0, 0xc01f, 0x15ff, 0xc01f, 0x21, 0 + .dw 0x1640, 0xc01f, 0x167f, 0xc01f, 0x21, 0 + .dw 0x16c0, 0xc01f, 0x16ff, 0xc01f, 0x21, 0 + .dw 0x1740, 0xc01f, 0x177f, 0xc01f, 0x21, 0 + .dw 0x17c0, 0xc01f, 0x17ff, 0xc01f, 0x21, 0 + .dw 0x1840, 0xc01f, 0x187f, 0xc01f, 0x21, 0 + .dw 0x18c0, 0xc01f, 0x18ff, 0xc01f, 0x21, 0 + .dw 0x1940, 0xc01f, 0x197f, 0xc01f, 0x21, 0 + .dw 0x19c0, 0xc01f, 0x1fff, 0xc01f, 0x21, 0 + .dw 0x2040, 0xc01f, 0x207f, 0xc01f, 0x21, 0 + .dw 0x20c0, 0xc01f, 0x20ff, 0xc01f, 0x21, 0 + .dw 0x2140, 0xc01f, 0x217f, 0xc01f, 0x21, 0 + .dw 0x21c0, 0xc01f, 0x21ff, 0xc01f, 0x21, 0 + .dw 0x2240, 0xc01f, 0x227f, 0xc01f, 0x21, 0 + .dw 0x22c0, 0xc01f, 0x22ff, 0xc01f, 0x21, 0 + .dw 0x2340, 0xc01f, 0x237f, 0xc01f, 0x21, 0 + .dw 0x23c0, 0xc01f, 0x23ff, 0xc01f, 0x21, 0 + .dw 0x2440, 0xc01f, 0x247f, 0xc01f, 0x21, 0 + .dw 0x24c0, 0xc01f, 0x24ff, 0xc01f, 0x21, 0 + .dw 0x2540, 0xc01f, 0x257f, 0xc01f, 0x21, 0 + .dw 0x25c0, 0xc01f, 0x25ff, 0xc01f, 0x21, 0 + .dw 0x2640, 0xc01f, 0x267f, 0xc01f, 0x21, 0 + .dw 0x26c0, 0xc01f, 0x26ff, 0xc01f, 0x21, 0 + .dw 0x2740, 0xc01f, 0x277f, 0xc01f, 0x21, 0 + .dw 0x27c0, 0xc01f, 0x27ff, 0xc01f, 0x21, 0 + .dw 0x2840, 0xc01f, 0x287f, 0xc01f, 0x21, 0 + .dw 0x28c0, 0xc01f, 0x28ff, 0xc01f, 0x21, 0 + .dw 0x2940, 0xc01f, 0x297f, 0xc01f, 0x21, 0 + .dw 0x29c0, 0xc01f, 0x29ff, 0xc01f, 0x21, 0 + .dw 0x2a40, 0xc01f, 0x2a7f, 0xc01f, 0x21, 0 + .dw 0x2ac0, 0xc01f, 0x2aff, 0xc01f, 0x21, 0 + .dw 0x2b40, 0xc01f, 0x2b7f, 0xc01f, 0x21, 0 + .dw 0x2bc0, 0xc01f, 0x2bff, 0xc01f, 0x21, 0 + .dw 0x2c40, 0xc01f, 0x2c7f, 0xc01f, 0x21, 0 + .dw 0x2cc0, 0xc01f, 0x2cff, 0xc01f, 0x21, 0 + .dw 0x2d40, 0xc01f, 0x2d7f, 0xc01f, 0x21, 0 + .dw 0x2dc0, 0xc01f, 0x2dff, 0xc01f, 0x21, 0 + .dw 0x2e40, 0xc01f, 0x2e7f, 0xc01f, 0x21, 0 + .dw 0x2ec0, 0xc01f, 0x2eff, 0xc01f, 0x21, 0 + .dw 0x2f40, 0xc01f, 0x2f7f, 0xc01f, 0x21, 0 + .dw 0x2fc0, 0xc01f, 0x2fff, 0xc01f, 0x21, 0 + .dw 0x3040, 0xc01f, 0x307f, 0xc01f, 0x21, 0 + .dw 0x30c0, 0xc01f, 0x30ff, 0xc01f, 0x21, 0 + .dw 0x3140, 0xc01f, 0x317f, 0xc01f, 0x21, 0 + .dw 0x31c0, 0xc01f, 0x31ff, 0xc01f, 0x21, 0 + .dw 0x3240, 0xc01f, 0x327f, 0xc01f, 0x21, 0 + .dw 0x32c0, 0xc01f, 0x32ff, 0xc01f, 0x21, 0 + .dw 0x3340, 0xc01f, 0x337f, 0xc01f, 0x21, 0 + .dw 0x33c0, 0xc01f, 0x33ff, 0xc01f, 0x21, 0 + .dw 0x3440, 0xc01f, 0x347f, 0xc01f, 0x21, 0 + .dw 0x34c0, 0xc01f, 0x34ff, 0xc01f, 0x21, 0 + .dw 0x3540, 0xc01f, 0x357f, 0xc01f, 0x21, 0 + .dw 0x35c0, 0xc01f, 0x35ff, 0xc01f, 0x21, 0 + .dw 0x3640, 0xc01f, 0x367f, 0xc01f, 0x21, 0 + .dw 0x36c0, 0xc01f, 0x36ff, 0xc01f, 0x21, 0 + .dw 0x3740, 0xc01f, 0x377f, 0xc01f, 0x21, 0 + .dw 0x37c0, 0xc01f, 0x37ff, 0xc01f, 0x21, 0 + .dw 0x3840, 0xc01f, 0x387f, 0xc01f, 0x21, 0 + .dw 0x38c0, 0xc01f, 0x38ff, 0xc01f, 0x21, 0 + .dw 0x3940, 0xc01f, 0x397f, 0xc01f, 0x21, 0 + .dw 0x39c0, 0xc01f, 0x1fff, 0xc020, 0x21, 0 + .dw 0x3a00, 0xc020, 0x5fff, 0xc020, 0x21, 0 + .dw 0x7a00, 0xc020, 0x9fff, 0xc020, 0x21, 0 + .dw 0xba00, 0xc020, 0xdfff, 0xc020, 0x21, 0 + .dw 0xfa00, 0xc020, 0x1fff, 0xc021, 0x21, 0 + .dw 0x3a00, 0xc021, 0x5fff, 0xc021, 0x21, 0 + .dw 0x7a00, 0xc021, 0x9fff, 0xc021, 0x21, 0 + .dw 0xba00, 0xc021, 0xdfff, 0xc021, 0x21, 0 + .dw 0xfa00, 0xc021, 0x1fff, 0xc022, 0x21, 0 + .dw 0x3a00, 0xc022, 0x5fff, 0xc022, 0x21, 0 + .dw 0x7a00, 0xc022, 0x9fff, 0xc022, 0x21, 0 + .dw 0xba00, 0xc022, 0xdfff, 0xc022, 0x21, 0 + .dw 0xfa00, 0xc022, 0x1fff, 0xc023, 0x21, 0 + .dw 0x3a00, 0xc023, 0xffff, 0xc023, 0x21, 0 + .dw 0x1a00, 0xc024, 0x1fff, 0xc024, 0x21, 0 + .dw 0x3a00, 0xc024, 0x3fff, 0xc024, 0x21, 0 + .dw 0x5a00, 0xc024, 0x5fff, 0xc024, 0x21, 0 + .dw 0x7a00, 0xc024, 0x7fff, 0xc024, 0x21, 0 + .dw 0x9a00, 0xc024, 0x9fff, 0xc024, 0x21, 0 + .dw 0xba00, 0xc024, 0xbfff, 0xc024, 0x21, 0 + .dw 0xda00, 0xc024, 0xdfff, 0xc024, 0x21, 0 + .dw 0xfa00, 0xc024, 0xffff, 0xc024, 0x21, 0 + .dw 0x1a00, 0xc025, 0x1fff, 0xc025, 0x21, 0 + .dw 0x3a00, 0xc025, 0x3fff, 0xc025, 0x21, 0 + .dw 0x5a00, 0xc025, 0x5fff, 0xc025, 0x21, 0 + .dw 0x7a00, 0xc025, 0x7fff, 0xc025, 0x21, 0 + .dw 0x9a00, 0xc025, 0x9fff, 0xc025, 0x21, 0 + .dw 0xba00, 0xc025, 0xbfff, 0xc025, 0x21, 0 + .dw 0xda00, 0xc025, 0xdfff, 0xc025, 0x21, 0 + .dw 0xfa00, 0xc025, 0xffff, 0xc025, 0x21, 0 + .dw 0x1a00, 0xc026, 0x1fff, 0xc026, 0x21, 0 + .dw 0x3a00, 0xc026, 0x3fff, 0xc026, 0x21, 0 + .dw 0x5a00, 0xc026, 0x5fff, 0xc026, 0x21, 0 + .dw 0x7a00, 0xc026, 0x7fff, 0xc026, 0x21, 0 + .dw 0x9a00, 0xc026, 0x9fff, 0xc026, 0x21, 0 + .dw 0xba00, 0xc026, 0xbfff, 0xc026, 0x21, 0 + .dw 0xda00, 0xc026, 0xdfff, 0xc026, 0x21, 0 + .dw 0xfa00, 0xc026, 0xffff, 0xc026, 0x21, 0 + .dw 0x1a00, 0xc027, 0x1fff, 0xc027, 0x21, 0 + .dw 0x3a00, 0xc027, 0x1fff, 0xc028, 0x21, 0 + .dw 0x2040, 0xc028, 0x207f, 0xc028, 0x21, 0 + .dw 0x20c0, 0xc028, 0x20ff, 0xc028, 0x21, 0 + .dw 0x2140, 0xc028, 0x217f, 0xc028, 0x21, 0 + .dw 0x21c0, 0xc028, 0x21ff, 0xc028, 0x21, 0 + .dw 0x2240, 0xc028, 0x227f, 0xc028, 0x21, 0 + .dw 0x22c0, 0xc028, 0x22ff, 0xc028, 0x21, 0 + .dw 0x2340, 0xc028, 0x237f, 0xc028, 0x21, 0 + .dw 0x23c0, 0xc028, 0x23ff, 0xc028, 0x21, 0 + .dw 0x2440, 0xc028, 0x247f, 0xc028, 0x21, 0 + .dw 0x24c0, 0xc028, 0x24ff, 0xc028, 0x21, 0 + .dw 0x2540, 0xc028, 0x257f, 0xc028, 0x21, 0 + .dw 0x25c0, 0xc028, 0x25ff, 0xc028, 0x21, 0 + .dw 0x2640, 0xc028, 0x267f, 0xc028, 0x21, 0 + .dw 0x26c0, 0xc028, 0x26ff, 0xc028, 0x21, 0 + .dw 0x2740, 0xc028, 0x277f, 0xc028, 0x21, 0 + .dw 0x27c0, 0xc028, 0x27ff, 0xc028, 0x21, 0 + .dw 0x2840, 0xc028, 0x287f, 0xc028, 0x21, 0 + .dw 0x28c0, 0xc028, 0x28ff, 0xc028, 0x21, 0 + .dw 0x2940, 0xc028, 0x297f, 0xc028, 0x21, 0 + .dw 0x29c0, 0xc028, 0x29ff, 0xc028, 0x21, 0 + .dw 0x2a40, 0xc028, 0x2a7f, 0xc028, 0x21, 0 + .dw 0x2ac0, 0xc028, 0x2aff, 0xc028, 0x21, 0 + .dw 0x2b40, 0xc028, 0x2b7f, 0xc028, 0x21, 0 + .dw 0x2bc0, 0xc028, 0x2bff, 0xc028, 0x21, 0 + .dw 0x2c40, 0xc028, 0x2c7f, 0xc028, 0x21, 0 + .dw 0x2cc0, 0xc028, 0x2cff, 0xc028, 0x21, 0 + .dw 0x2d40, 0xc028, 0x2d7f, 0xc028, 0x21, 0 + .dw 0x2dc0, 0xc028, 0x2dff, 0xc028, 0x21, 0 + .dw 0x2e40, 0xc028, 0x2e7f, 0xc028, 0x21, 0 + .dw 0x2ec0, 0xc028, 0x2eff, 0xc028, 0x21, 0 + .dw 0x2f40, 0xc028, 0x2f7f, 0xc028, 0x21, 0 + .dw 0x2fc0, 0xc028, 0x2fff, 0xc028, 0x21, 0 + .dw 0x3040, 0xc028, 0x307f, 0xc028, 0x21, 0 + .dw 0x30c0, 0xc028, 0x30ff, 0xc028, 0x21, 0 + .dw 0x3140, 0xc028, 0x317f, 0xc028, 0x21, 0 + .dw 0x31c0, 0xc028, 0x31ff, 0xc028, 0x21, 0 + .dw 0x3240, 0xc028, 0x327f, 0xc028, 0x21, 0 + .dw 0x32c0, 0xc028, 0x32ff, 0xc028, 0x21, 0 + .dw 0x3340, 0xc028, 0x337f, 0xc028, 0x21, 0 + .dw 0x33c0, 0xc028, 0x33ff, 0xc028, 0x21, 0 + .dw 0x3440, 0xc028, 0x347f, 0xc028, 0x21, 0 + .dw 0x34c0, 0xc028, 0x34ff, 0xc028, 0x21, 0 + .dw 0x3540, 0xc028, 0x357f, 0xc028, 0x21, 0 + .dw 0x35c0, 0xc028, 0x35ff, 0xc028, 0x21, 0 + .dw 0x3640, 0xc028, 0x367f, 0xc028, 0x21, 0 + .dw 0x36c0, 0xc028, 0x36ff, 0xc028, 0x21, 0 + .dw 0x3740, 0xc028, 0x377f, 0xc028, 0x21, 0 + .dw 0x37c0, 0xc028, 0x37ff, 0xc028, 0x21, 0 + .dw 0x3840, 0xc028, 0x387f, 0xc028, 0x21, 0 + .dw 0x38c0, 0xc028, 0x38ff, 0xc028, 0x21, 0 + .dw 0x3940, 0xc028, 0x397f, 0xc028, 0x21, 0 + .dw 0x39c0, 0xc028, 0x5fff, 0xc028, 0x21, 0 + .dw 0x6040, 0xc028, 0x607f, 0xc028, 0x21, 0 + .dw 0x60c0, 0xc028, 0x60ff, 0xc028, 0x21, 0 + .dw 0x6140, 0xc028, 0x617f, 0xc028, 0x21, 0 + .dw 0x61c0, 0xc028, 0x61ff, 0xc028, 0x21, 0 + .dw 0x6240, 0xc028, 0x627f, 0xc028, 0x21, 0 + .dw 0x62c0, 0xc028, 0x62ff, 0xc028, 0x21, 0 + .dw 0x6340, 0xc028, 0x637f, 0xc028, 0x21, 0 + .dw 0x63c0, 0xc028, 0x63ff, 0xc028, 0x21, 0 + .dw 0x6440, 0xc028, 0x647f, 0xc028, 0x21, 0 + .dw 0x64c0, 0xc028, 0x64ff, 0xc028, 0x21, 0 + .dw 0x6540, 0xc028, 0x657f, 0xc028, 0x21, 0 + .dw 0x65c0, 0xc028, 0x65ff, 0xc028, 0x21, 0 + .dw 0x6640, 0xc028, 0x667f, 0xc028, 0x21, 0 + .dw 0x66c0, 0xc028, 0x66ff, 0xc028, 0x21, 0 + .dw 0x6740, 0xc028, 0x677f, 0xc028, 0x21, 0 + .dw 0x67c0, 0xc028, 0x67ff, 0xc028, 0x21, 0 + .dw 0x6840, 0xc028, 0x687f, 0xc028, 0x21, 0 + .dw 0x68c0, 0xc028, 0x68ff, 0xc028, 0x21, 0 + .dw 0x6940, 0xc028, 0x697f, 0xc028, 0x21, 0 + .dw 0x69c0, 0xc028, 0x69ff, 0xc028, 0x21, 0 + .dw 0x6a40, 0xc028, 0x6a7f, 0xc028, 0x21, 0 + .dw 0x6ac0, 0xc028, 0x6aff, 0xc028, 0x21, 0 + .dw 0x6b40, 0xc028, 0x6b7f, 0xc028, 0x21, 0 + .dw 0x6bc0, 0xc028, 0x6bff, 0xc028, 0x21, 0 + .dw 0x6c40, 0xc028, 0x6c7f, 0xc028, 0x21, 0 + .dw 0x6cc0, 0xc028, 0x6cff, 0xc028, 0x21, 0 + .dw 0x6d40, 0xc028, 0x6d7f, 0xc028, 0x21, 0 + .dw 0x6dc0, 0xc028, 0x6dff, 0xc028, 0x21, 0 + .dw 0x6e40, 0xc028, 0x6e7f, 0xc028, 0x21, 0 + .dw 0x6ec0, 0xc028, 0x6eff, 0xc028, 0x21, 0 + .dw 0x6f40, 0xc028, 0x6f7f, 0xc028, 0x21, 0 + .dw 0x6fc0, 0xc028, 0x6fff, 0xc028, 0x21, 0 + .dw 0x7040, 0xc028, 0x707f, 0xc028, 0x21, 0 + .dw 0x70c0, 0xc028, 0x70ff, 0xc028, 0x21, 0 + .dw 0x7140, 0xc028, 0x717f, 0xc028, 0x21, 0 + .dw 0x71c0, 0xc028, 0x71ff, 0xc028, 0x21, 0 + .dw 0x7240, 0xc028, 0x727f, 0xc028, 0x21, 0 + .dw 0x72c0, 0xc028, 0x72ff, 0xc028, 0x21, 0 + .dw 0x7340, 0xc028, 0x737f, 0xc028, 0x21, 0 + .dw 0x73c0, 0xc028, 0x73ff, 0xc028, 0x21, 0 + .dw 0x7440, 0xc028, 0x747f, 0xc028, 0x21, 0 + .dw 0x74c0, 0xc028, 0x74ff, 0xc028, 0x21, 0 + .dw 0x7540, 0xc028, 0x757f, 0xc028, 0x21, 0 + .dw 0x75c0, 0xc028, 0x75ff, 0xc028, 0x21, 0 + .dw 0x7640, 0xc028, 0x767f, 0xc028, 0x21, 0 + .dw 0x76c0, 0xc028, 0x76ff, 0xc028, 0x21, 0 + .dw 0x7740, 0xc028, 0x777f, 0xc028, 0x21, 0 + .dw 0x77c0, 0xc028, 0x77ff, 0xc028, 0x21, 0 + .dw 0x7840, 0xc028, 0x787f, 0xc028, 0x21, 0 + .dw 0x78c0, 0xc028, 0x78ff, 0xc028, 0x21, 0 + .dw 0x7940, 0xc028, 0x797f, 0xc028, 0x21, 0 + .dw 0x79c0, 0xc028, 0x9fff, 0xc028, 0x21, 0 + .dw 0xa040, 0xc028, 0xa07f, 0xc028, 0x21, 0 + .dw 0xa0c0, 0xc028, 0xa0ff, 0xc028, 0x21, 0 + .dw 0xa140, 0xc028, 0xa17f, 0xc028, 0x21, 0 + .dw 0xa1c0, 0xc028, 0xa1ff, 0xc028, 0x21, 0 + .dw 0xa240, 0xc028, 0xa27f, 0xc028, 0x21, 0 + .dw 0xa2c0, 0xc028, 0xa2ff, 0xc028, 0x21, 0 + .dw 0xa340, 0xc028, 0xa37f, 0xc028, 0x21, 0 + .dw 0xa3c0, 0xc028, 0xa3ff, 0xc028, 0x21, 0 + .dw 0xa440, 0xc028, 0xa47f, 0xc028, 0x21, 0 + .dw 0xa4c0, 0xc028, 0xa4ff, 0xc028, 0x21, 0 + .dw 0xa540, 0xc028, 0xa57f, 0xc028, 0x21, 0 + .dw 0xa5c0, 0xc028, 0xa5ff, 0xc028, 0x21, 0 + .dw 0xa640, 0xc028, 0xa67f, 0xc028, 0x21, 0 + .dw 0xa6c0, 0xc028, 0xa6ff, 0xc028, 0x21, 0 + .dw 0xa740, 0xc028, 0xa77f, 0xc028, 0x21, 0 + .dw 0xa7c0, 0xc028, 0xa7ff, 0xc028, 0x21, 0 + .dw 0xa840, 0xc028, 0xa87f, 0xc028, 0x21, 0 + .dw 0xa8c0, 0xc028, 0xa8ff, 0xc028, 0x21, 0 + .dw 0xa940, 0xc028, 0xa97f, 0xc028, 0x21, 0 + .dw 0xa9c0, 0xc028, 0xa9ff, 0xc028, 0x21, 0 + .dw 0xaa40, 0xc028, 0xaa7f, 0xc028, 0x21, 0 + .dw 0xaac0, 0xc028, 0xaaff, 0xc028, 0x21, 0 + .dw 0xab40, 0xc028, 0xab7f, 0xc028, 0x21, 0 + .dw 0xabc0, 0xc028, 0xabff, 0xc028, 0x21, 0 + .dw 0xac40, 0xc028, 0xac7f, 0xc028, 0x21, 0 + .dw 0xacc0, 0xc028, 0xacff, 0xc028, 0x21, 0 + .dw 0xad40, 0xc028, 0xad7f, 0xc028, 0x21, 0 + .dw 0xadc0, 0xc028, 0xadff, 0xc028, 0x21, 0 + .dw 0xae40, 0xc028, 0xae7f, 0xc028, 0x21, 0 + .dw 0xaec0, 0xc028, 0xaeff, 0xc028, 0x21, 0 + .dw 0xaf40, 0xc028, 0xaf7f, 0xc028, 0x21, 0 + .dw 0xafc0, 0xc028, 0xafff, 0xc028, 0x21, 0 + .dw 0xb040, 0xc028, 0xb07f, 0xc028, 0x21, 0 + .dw 0xb0c0, 0xc028, 0xb0ff, 0xc028, 0x21, 0 + .dw 0xb140, 0xc028, 0xb17f, 0xc028, 0x21, 0 + .dw 0xb1c0, 0xc028, 0xb1ff, 0xc028, 0x21, 0 + .dw 0xb240, 0xc028, 0xb27f, 0xc028, 0x21, 0 + .dw 0xb2c0, 0xc028, 0xb2ff, 0xc028, 0x21, 0 + .dw 0xb340, 0xc028, 0xb37f, 0xc028, 0x21, 0 + .dw 0xb3c0, 0xc028, 0xb3ff, 0xc028, 0x21, 0 + .dw 0xb440, 0xc028, 0xb47f, 0xc028, 0x21, 0 + .dw 0xb4c0, 0xc028, 0xb4ff, 0xc028, 0x21, 0 + .dw 0xb540, 0xc028, 0xb57f, 0xc028, 0x21, 0 + .dw 0xb5c0, 0xc028, 0xb5ff, 0xc028, 0x21, 0 + .dw 0xb640, 0xc028, 0xb67f, 0xc028, 0x21, 0 + .dw 0xb6c0, 0xc028, 0xb6ff, 0xc028, 0x21, 0 + .dw 0xb740, 0xc028, 0xb77f, 0xc028, 0x21, 0 + .dw 0xb7c0, 0xc028, 0xb7ff, 0xc028, 0x21, 0 + .dw 0xb840, 0xc028, 0xb87f, 0xc028, 0x21, 0 + .dw 0xb8c0, 0xc028, 0xb8ff, 0xc028, 0x21, 0 + .dw 0xb940, 0xc028, 0xb97f, 0xc028, 0x21, 0 + .dw 0xb9c0, 0xc028, 0xdfff, 0xc028, 0x21, 0 + .dw 0xe040, 0xc028, 0xe07f, 0xc028, 0x21, 0 + .dw 0xe0c0, 0xc028, 0xe0ff, 0xc028, 0x21, 0 + .dw 0xe140, 0xc028, 0xe17f, 0xc028, 0x21, 0 + .dw 0xe1c0, 0xc028, 0xe1ff, 0xc028, 0x21, 0 + .dw 0xe240, 0xc028, 0xe27f, 0xc028, 0x21, 0 + .dw 0xe2c0, 0xc028, 0xe2ff, 0xc028, 0x21, 0 + .dw 0xe340, 0xc028, 0xe37f, 0xc028, 0x21, 0 + .dw 0xe3c0, 0xc028, 0xe3ff, 0xc028, 0x21, 0 + .dw 0xe440, 0xc028, 0xe47f, 0xc028, 0x21, 0 + .dw 0xe4c0, 0xc028, 0xe4ff, 0xc028, 0x21, 0 + .dw 0xe540, 0xc028, 0xe57f, 0xc028, 0x21, 0 + .dw 0xe5c0, 0xc028, 0xe5ff, 0xc028, 0x21, 0 + .dw 0xe640, 0xc028, 0xe67f, 0xc028, 0x21, 0 + .dw 0xe6c0, 0xc028, 0xe6ff, 0xc028, 0x21, 0 + .dw 0xe740, 0xc028, 0xe77f, 0xc028, 0x21, 0 + .dw 0xe7c0, 0xc028, 0xe7ff, 0xc028, 0x21, 0 + .dw 0xe840, 0xc028, 0xe87f, 0xc028, 0x21, 0 + .dw 0xe8c0, 0xc028, 0xe8ff, 0xc028, 0x21, 0 + .dw 0xe940, 0xc028, 0xe97f, 0xc028, 0x21, 0 + .dw 0xe9c0, 0xc028, 0xe9ff, 0xc028, 0x21, 0 + .dw 0xea40, 0xc028, 0xea7f, 0xc028, 0x21, 0 + .dw 0xeac0, 0xc028, 0xeaff, 0xc028, 0x21, 0 + .dw 0xeb40, 0xc028, 0xeb7f, 0xc028, 0x21, 0 + .dw 0xebc0, 0xc028, 0xebff, 0xc028, 0x21, 0 + .dw 0xec40, 0xc028, 0xec7f, 0xc028, 0x21, 0 + .dw 0xecc0, 0xc028, 0xecff, 0xc028, 0x21, 0 + .dw 0xed40, 0xc028, 0xed7f, 0xc028, 0x21, 0 + .dw 0xedc0, 0xc028, 0xedff, 0xc028, 0x21, 0 + .dw 0xee40, 0xc028, 0xee7f, 0xc028, 0x21, 0 + .dw 0xeec0, 0xc028, 0xeeff, 0xc028, 0x21, 0 + .dw 0xef40, 0xc028, 0xef7f, 0xc028, 0x21, 0 + .dw 0xefc0, 0xc028, 0xefff, 0xc028, 0x21, 0 + .dw 0xf040, 0xc028, 0xf07f, 0xc028, 0x21, 0 + .dw 0xf0c0, 0xc028, 0xf0ff, 0xc028, 0x21, 0 + .dw 0xf140, 0xc028, 0xf17f, 0xc028, 0x21, 0 + .dw 0xf1c0, 0xc028, 0xf1ff, 0xc028, 0x21, 0 + .dw 0xf240, 0xc028, 0xf27f, 0xc028, 0x21, 0 + .dw 0xf2c0, 0xc028, 0xf2ff, 0xc028, 0x21, 0 + .dw 0xf340, 0xc028, 0xf37f, 0xc028, 0x21, 0 + .dw 0xf3c0, 0xc028, 0xf3ff, 0xc028, 0x21, 0 + .dw 0xf440, 0xc028, 0xf47f, 0xc028, 0x21, 0 + .dw 0xf4c0, 0xc028, 0xf4ff, 0xc028, 0x21, 0 + .dw 0xf540, 0xc028, 0xf57f, 0xc028, 0x21, 0 + .dw 0xf5c0, 0xc028, 0xf5ff, 0xc028, 0x21, 0 + .dw 0xf640, 0xc028, 0xf67f, 0xc028, 0x21, 0 + .dw 0xf6c0, 0xc028, 0xf6ff, 0xc028, 0x21, 0 + .dw 0xf740, 0xc028, 0xf77f, 0xc028, 0x21, 0 + .dw 0xf7c0, 0xc028, 0xf7ff, 0xc028, 0x21, 0 + .dw 0xf840, 0xc028, 0xf87f, 0xc028, 0x21, 0 + .dw 0xf8c0, 0xc028, 0xf8ff, 0xc028, 0x21, 0 + .dw 0xf940, 0xc028, 0xf97f, 0xc028, 0x21, 0 + .dw 0xf9c0, 0xc028, 0x1fff, 0xc029, 0x21, 0 + .dw 0x2040, 0xc029, 0x207f, 0xc029, 0x21, 0 + .dw 0x20c0, 0xc029, 0x20ff, 0xc029, 0x21, 0 + .dw 0x2140, 0xc029, 0x217f, 0xc029, 0x21, 0 + .dw 0x21c0, 0xc029, 0x21ff, 0xc029, 0x21, 0 + .dw 0x2240, 0xc029, 0x227f, 0xc029, 0x21, 0 + .dw 0x22c0, 0xc029, 0x22ff, 0xc029, 0x21, 0 + .dw 0x2340, 0xc029, 0x237f, 0xc029, 0x21, 0 + .dw 0x23c0, 0xc029, 0x23ff, 0xc029, 0x21, 0 + .dw 0x2440, 0xc029, 0x247f, 0xc029, 0x21, 0 + .dw 0x24c0, 0xc029, 0x24ff, 0xc029, 0x21, 0 + .dw 0x2540, 0xc029, 0x257f, 0xc029, 0x21, 0 + .dw 0x25c0, 0xc029, 0x25ff, 0xc029, 0x21, 0 + .dw 0x2640, 0xc029, 0x267f, 0xc029, 0x21, 0 + .dw 0x26c0, 0xc029, 0x26ff, 0xc029, 0x21, 0 + .dw 0x2740, 0xc029, 0x277f, 0xc029, 0x21, 0 + .dw 0x27c0, 0xc029, 0x27ff, 0xc029, 0x21, 0 + .dw 0x2840, 0xc029, 0x287f, 0xc029, 0x21, 0 + .dw 0x28c0, 0xc029, 0x28ff, 0xc029, 0x21, 0 + .dw 0x2940, 0xc029, 0x297f, 0xc029, 0x21, 0 + .dw 0x29c0, 0xc029, 0x29ff, 0xc029, 0x21, 0 + .dw 0x2a40, 0xc029, 0x2a7f, 0xc029, 0x21, 0 + .dw 0x2ac0, 0xc029, 0x2aff, 0xc029, 0x21, 0 + .dw 0x2b40, 0xc029, 0x2b7f, 0xc029, 0x21, 0 + .dw 0x2bc0, 0xc029, 0x2bff, 0xc029, 0x21, 0 + .dw 0x2c40, 0xc029, 0x2c7f, 0xc029, 0x21, 0 + .dw 0x2cc0, 0xc029, 0x2cff, 0xc029, 0x21, 0 + .dw 0x2d40, 0xc029, 0x2d7f, 0xc029, 0x21, 0 + .dw 0x2dc0, 0xc029, 0x2dff, 0xc029, 0x21, 0 + .dw 0x2e40, 0xc029, 0x2e7f, 0xc029, 0x21, 0 + .dw 0x2ec0, 0xc029, 0x2eff, 0xc029, 0x21, 0 + .dw 0x2f40, 0xc029, 0x2f7f, 0xc029, 0x21, 0 + .dw 0x2fc0, 0xc029, 0x2fff, 0xc029, 0x21, 0 + .dw 0x3040, 0xc029, 0x307f, 0xc029, 0x21, 0 + .dw 0x30c0, 0xc029, 0x30ff, 0xc029, 0x21, 0 + .dw 0x3140, 0xc029, 0x317f, 0xc029, 0x21, 0 + .dw 0x31c0, 0xc029, 0x31ff, 0xc029, 0x21, 0 + .dw 0x3240, 0xc029, 0x327f, 0xc029, 0x21, 0 + .dw 0x32c0, 0xc029, 0x32ff, 0xc029, 0x21, 0 + .dw 0x3340, 0xc029, 0x337f, 0xc029, 0x21, 0 + .dw 0x33c0, 0xc029, 0x33ff, 0xc029, 0x21, 0 + .dw 0x3440, 0xc029, 0x347f, 0xc029, 0x21, 0 + .dw 0x34c0, 0xc029, 0x34ff, 0xc029, 0x21, 0 + .dw 0x3540, 0xc029, 0x357f, 0xc029, 0x21, 0 + .dw 0x35c0, 0xc029, 0x35ff, 0xc029, 0x21, 0 + .dw 0x3640, 0xc029, 0x367f, 0xc029, 0x21, 0 + .dw 0x36c0, 0xc029, 0x36ff, 0xc029, 0x21, 0 + .dw 0x3740, 0xc029, 0x377f, 0xc029, 0x21, 0 + .dw 0x37c0, 0xc029, 0x37ff, 0xc029, 0x21, 0 + .dw 0x3840, 0xc029, 0x387f, 0xc029, 0x21, 0 + .dw 0x38c0, 0xc029, 0x38ff, 0xc029, 0x21, 0 + .dw 0x3940, 0xc029, 0x397f, 0xc029, 0x21, 0 + .dw 0x39c0, 0xc029, 0x5fff, 0xc029, 0x21, 0 + .dw 0x6040, 0xc029, 0x607f, 0xc029, 0x21, 0 + .dw 0x60c0, 0xc029, 0x60ff, 0xc029, 0x21, 0 + .dw 0x6140, 0xc029, 0x617f, 0xc029, 0x21, 0 + .dw 0x61c0, 0xc029, 0x61ff, 0xc029, 0x21, 0 + .dw 0x6240, 0xc029, 0x627f, 0xc029, 0x21, 0 + .dw 0x62c0, 0xc029, 0x62ff, 0xc029, 0x21, 0 + .dw 0x6340, 0xc029, 0x637f, 0xc029, 0x21, 0 + .dw 0x63c0, 0xc029, 0x63ff, 0xc029, 0x21, 0 + .dw 0x6440, 0xc029, 0x647f, 0xc029, 0x21, 0 + .dw 0x64c0, 0xc029, 0x64ff, 0xc029, 0x21, 0 + .dw 0x6540, 0xc029, 0x657f, 0xc029, 0x21, 0 + .dw 0x65c0, 0xc029, 0x65ff, 0xc029, 0x21, 0 + .dw 0x6640, 0xc029, 0x667f, 0xc029, 0x21, 0 + .dw 0x66c0, 0xc029, 0x66ff, 0xc029, 0x21, 0 + .dw 0x6740, 0xc029, 0x677f, 0xc029, 0x21, 0 + .dw 0x67c0, 0xc029, 0x67ff, 0xc029, 0x21, 0 + .dw 0x6840, 0xc029, 0x687f, 0xc029, 0x21, 0 + .dw 0x68c0, 0xc029, 0x68ff, 0xc029, 0x21, 0 + .dw 0x6940, 0xc029, 0x697f, 0xc029, 0x21, 0 + .dw 0x69c0, 0xc029, 0x69ff, 0xc029, 0x21, 0 + .dw 0x6a40, 0xc029, 0x6a7f, 0xc029, 0x21, 0 + .dw 0x6ac0, 0xc029, 0x6aff, 0xc029, 0x21, 0 + .dw 0x6b40, 0xc029, 0x6b7f, 0xc029, 0x21, 0 + .dw 0x6bc0, 0xc029, 0x6bff, 0xc029, 0x21, 0 + .dw 0x6c40, 0xc029, 0x6c7f, 0xc029, 0x21, 0 + .dw 0x6cc0, 0xc029, 0x6cff, 0xc029, 0x21, 0 + .dw 0x6d40, 0xc029, 0x6d7f, 0xc029, 0x21, 0 + .dw 0x6dc0, 0xc029, 0x6dff, 0xc029, 0x21, 0 + .dw 0x6e40, 0xc029, 0x6e7f, 0xc029, 0x21, 0 + .dw 0x6ec0, 0xc029, 0x6eff, 0xc029, 0x21, 0 + .dw 0x6f40, 0xc029, 0x6f7f, 0xc029, 0x21, 0 + .dw 0x6fc0, 0xc029, 0x6fff, 0xc029, 0x21, 0 + .dw 0x7040, 0xc029, 0x707f, 0xc029, 0x21, 0 + .dw 0x70c0, 0xc029, 0x70ff, 0xc029, 0x21, 0 + .dw 0x7140, 0xc029, 0x717f, 0xc029, 0x21, 0 + .dw 0x71c0, 0xc029, 0x71ff, 0xc029, 0x21, 0 + .dw 0x7240, 0xc029, 0x727f, 0xc029, 0x21, 0 + .dw 0x72c0, 0xc029, 0x72ff, 0xc029, 0x21, 0 + .dw 0x7340, 0xc029, 0x737f, 0xc029, 0x21, 0 + .dw 0x73c0, 0xc029, 0x73ff, 0xc029, 0x21, 0 + .dw 0x7440, 0xc029, 0x747f, 0xc029, 0x21, 0 + .dw 0x74c0, 0xc029, 0x74ff, 0xc029, 0x21, 0 + .dw 0x7540, 0xc029, 0x757f, 0xc029, 0x21, 0 + .dw 0x75c0, 0xc029, 0x75ff, 0xc029, 0x21, 0 + .dw 0x7640, 0xc029, 0x767f, 0xc029, 0x21, 0 + .dw 0x76c0, 0xc029, 0x76ff, 0xc029, 0x21, 0 + .dw 0x7740, 0xc029, 0x777f, 0xc029, 0x21, 0 + .dw 0x77c0, 0xc029, 0x77ff, 0xc029, 0x21, 0 + .dw 0x7840, 0xc029, 0x787f, 0xc029, 0x21, 0 + .dw 0x78c0, 0xc029, 0x78ff, 0xc029, 0x21, 0 + .dw 0x7940, 0xc029, 0x797f, 0xc029, 0x21, 0 + .dw 0x79c0, 0xc029, 0x9fff, 0xc029, 0x21, 0 + .dw 0xa040, 0xc029, 0xa07f, 0xc029, 0x21, 0 + .dw 0xa0c0, 0xc029, 0xa0ff, 0xc029, 0x21, 0 + .dw 0xa140, 0xc029, 0xa17f, 0xc029, 0x21, 0 + .dw 0xa1c0, 0xc029, 0xa1ff, 0xc029, 0x21, 0 + .dw 0xa240, 0xc029, 0xa27f, 0xc029, 0x21, 0 + .dw 0xa2c0, 0xc029, 0xa2ff, 0xc029, 0x21, 0 + .dw 0xa340, 0xc029, 0xa37f, 0xc029, 0x21, 0 + .dw 0xa3c0, 0xc029, 0xa3ff, 0xc029, 0x21, 0 + .dw 0xa440, 0xc029, 0xa47f, 0xc029, 0x21, 0 + .dw 0xa4c0, 0xc029, 0xa4ff, 0xc029, 0x21, 0 + .dw 0xa540, 0xc029, 0xa57f, 0xc029, 0x21, 0 + .dw 0xa5c0, 0xc029, 0xa5ff, 0xc029, 0x21, 0 + .dw 0xa640, 0xc029, 0xa67f, 0xc029, 0x21, 0 + .dw 0xa6c0, 0xc029, 0xa6ff, 0xc029, 0x21, 0 + .dw 0xa740, 0xc029, 0xa77f, 0xc029, 0x21, 0 + .dw 0xa7c0, 0xc029, 0xa7ff, 0xc029, 0x21, 0 + .dw 0xa840, 0xc029, 0xa87f, 0xc029, 0x21, 0 + .dw 0xa8c0, 0xc029, 0xa8ff, 0xc029, 0x21, 0 + .dw 0xa940, 0xc029, 0xa97f, 0xc029, 0x21, 0 + .dw 0xa9c0, 0xc029, 0xa9ff, 0xc029, 0x21, 0 + .dw 0xaa40, 0xc029, 0xaa7f, 0xc029, 0x21, 0 + .dw 0xaac0, 0xc029, 0xaaff, 0xc029, 0x21, 0 + .dw 0xab40, 0xc029, 0xab7f, 0xc029, 0x21, 0 + .dw 0xabc0, 0xc029, 0xabff, 0xc029, 0x21, 0 + .dw 0xac40, 0xc029, 0xac7f, 0xc029, 0x21, 0 + .dw 0xacc0, 0xc029, 0xacff, 0xc029, 0x21, 0 + .dw 0xad40, 0xc029, 0xad7f, 0xc029, 0x21, 0 + .dw 0xadc0, 0xc029, 0xadff, 0xc029, 0x21, 0 + .dw 0xae40, 0xc029, 0xae7f, 0xc029, 0x21, 0 + .dw 0xaec0, 0xc029, 0xaeff, 0xc029, 0x21, 0 + .dw 0xaf40, 0xc029, 0xaf7f, 0xc029, 0x21, 0 + .dw 0xafc0, 0xc029, 0xafff, 0xc029, 0x21, 0 + .dw 0xb040, 0xc029, 0xb07f, 0xc029, 0x21, 0 + .dw 0xb0c0, 0xc029, 0xb0ff, 0xc029, 0x21, 0 + .dw 0xb140, 0xc029, 0xb17f, 0xc029, 0x21, 0 + .dw 0xb1c0, 0xc029, 0xb1ff, 0xc029, 0x21, 0 + .dw 0xb240, 0xc029, 0xb27f, 0xc029, 0x21, 0 + .dw 0xb2c0, 0xc029, 0xb2ff, 0xc029, 0x21, 0 + .dw 0xb340, 0xc029, 0xb37f, 0xc029, 0x21, 0 + .dw 0xb3c0, 0xc029, 0xb3ff, 0xc029, 0x21, 0 + .dw 0xb440, 0xc029, 0xb47f, 0xc029, 0x21, 0 + .dw 0xb4c0, 0xc029, 0xb4ff, 0xc029, 0x21, 0 + .dw 0xb540, 0xc029, 0xb57f, 0xc029, 0x21, 0 + .dw 0xb5c0, 0xc029, 0xb5ff, 0xc029, 0x21, 0 + .dw 0xb640, 0xc029, 0xb67f, 0xc029, 0x21, 0 + .dw 0xb6c0, 0xc029, 0xb6ff, 0xc029, 0x21, 0 + .dw 0xb740, 0xc029, 0xb77f, 0xc029, 0x21, 0 + .dw 0xb7c0, 0xc029, 0xb7ff, 0xc029, 0x21, 0 + .dw 0xb840, 0xc029, 0xb87f, 0xc029, 0x21, 0 + .dw 0xb8c0, 0xc029, 0xb8ff, 0xc029, 0x21, 0 + .dw 0xb940, 0xc029, 0xb97f, 0xc029, 0x21, 0 + .dw 0xb9c0, 0xc029, 0xdfff, 0xc029, 0x21, 0 + .dw 0xe040, 0xc029, 0xe07f, 0xc029, 0x21, 0 + .dw 0xe0c0, 0xc029, 0xe0ff, 0xc029, 0x21, 0 + .dw 0xe140, 0xc029, 0xe17f, 0xc029, 0x21, 0 + .dw 0xe1c0, 0xc029, 0xe1ff, 0xc029, 0x21, 0 + .dw 0xe240, 0xc029, 0xe27f, 0xc029, 0x21, 0 + .dw 0xe2c0, 0xc029, 0xe2ff, 0xc029, 0x21, 0 + .dw 0xe340, 0xc029, 0xe37f, 0xc029, 0x21, 0 + .dw 0xe3c0, 0xc029, 0xe3ff, 0xc029, 0x21, 0 + .dw 0xe440, 0xc029, 0xe47f, 0xc029, 0x21, 0 + .dw 0xe4c0, 0xc029, 0xe4ff, 0xc029, 0x21, 0 + .dw 0xe540, 0xc029, 0xe57f, 0xc029, 0x21, 0 + .dw 0xe5c0, 0xc029, 0xe5ff, 0xc029, 0x21, 0 + .dw 0xe640, 0xc029, 0xe67f, 0xc029, 0x21, 0 + .dw 0xe6c0, 0xc029, 0xe6ff, 0xc029, 0x21, 0 + .dw 0xe740, 0xc029, 0xe77f, 0xc029, 0x21, 0 + .dw 0xe7c0, 0xc029, 0xe7ff, 0xc029, 0x21, 0 + .dw 0xe840, 0xc029, 0xe87f, 0xc029, 0x21, 0 + .dw 0xe8c0, 0xc029, 0xe8ff, 0xc029, 0x21, 0 + .dw 0xe940, 0xc029, 0xe97f, 0xc029, 0x21, 0 + .dw 0xe9c0, 0xc029, 0xe9ff, 0xc029, 0x21, 0 + .dw 0xea40, 0xc029, 0xea7f, 0xc029, 0x21, 0 + .dw 0xeac0, 0xc029, 0xeaff, 0xc029, 0x21, 0 + .dw 0xeb40, 0xc029, 0xeb7f, 0xc029, 0x21, 0 + .dw 0xebc0, 0xc029, 0xebff, 0xc029, 0x21, 0 + .dw 0xec40, 0xc029, 0xec7f, 0xc029, 0x21, 0 + .dw 0xecc0, 0xc029, 0xecff, 0xc029, 0x21, 0 + .dw 0xed40, 0xc029, 0xed7f, 0xc029, 0x21, 0 + .dw 0xedc0, 0xc029, 0xedff, 0xc029, 0x21, 0 + .dw 0xee40, 0xc029, 0xee7f, 0xc029, 0x21, 0 + .dw 0xeec0, 0xc029, 0xeeff, 0xc029, 0x21, 0 + .dw 0xef40, 0xc029, 0xef7f, 0xc029, 0x21, 0 + .dw 0xefc0, 0xc029, 0xefff, 0xc029, 0x21, 0 + .dw 0xf040, 0xc029, 0xf07f, 0xc029, 0x21, 0 + .dw 0xf0c0, 0xc029, 0xf0ff, 0xc029, 0x21, 0 + .dw 0xf140, 0xc029, 0xf17f, 0xc029, 0x21, 0 + .dw 0xf1c0, 0xc029, 0xf1ff, 0xc029, 0x21, 0 + .dw 0xf240, 0xc029, 0xf27f, 0xc029, 0x21, 0 + .dw 0xf2c0, 0xc029, 0xf2ff, 0xc029, 0x21, 0 + .dw 0xf340, 0xc029, 0xf37f, 0xc029, 0x21, 0 + .dw 0xf3c0, 0xc029, 0xf3ff, 0xc029, 0x21, 0 + .dw 0xf440, 0xc029, 0xf47f, 0xc029, 0x21, 0 + .dw 0xf4c0, 0xc029, 0xf4ff, 0xc029, 0x21, 0 + .dw 0xf540, 0xc029, 0xf57f, 0xc029, 0x21, 0 + .dw 0xf5c0, 0xc029, 0xf5ff, 0xc029, 0x21, 0 + .dw 0xf640, 0xc029, 0xf67f, 0xc029, 0x21, 0 + .dw 0xf6c0, 0xc029, 0xf6ff, 0xc029, 0x21, 0 + .dw 0xf740, 0xc029, 0xf77f, 0xc029, 0x21, 0 + .dw 0xf7c0, 0xc029, 0xf7ff, 0xc029, 0x21, 0 + .dw 0xf840, 0xc029, 0xf87f, 0xc029, 0x21, 0 + .dw 0xf8c0, 0xc029, 0xf8ff, 0xc029, 0x21, 0 + .dw 0xf940, 0xc029, 0xf97f, 0xc029, 0x21, 0 + .dw 0xf9c0, 0xc029, 0x1fff, 0xc02a, 0x21, 0 + .dw 0x2040, 0xc02a, 0x207f, 0xc02a, 0x21, 0 + .dw 0x20c0, 0xc02a, 0x20ff, 0xc02a, 0x21, 0 + .dw 0x2140, 0xc02a, 0x217f, 0xc02a, 0x21, 0 + .dw 0x21c0, 0xc02a, 0x21ff, 0xc02a, 0x21, 0 + .dw 0x2240, 0xc02a, 0x227f, 0xc02a, 0x21, 0 + .dw 0x22c0, 0xc02a, 0x22ff, 0xc02a, 0x21, 0 + .dw 0x2340, 0xc02a, 0x237f, 0xc02a, 0x21, 0 + .dw 0x23c0, 0xc02a, 0x23ff, 0xc02a, 0x21, 0 + .dw 0x2440, 0xc02a, 0x247f, 0xc02a, 0x21, 0 + .dw 0x24c0, 0xc02a, 0x24ff, 0xc02a, 0x21, 0 + .dw 0x2540, 0xc02a, 0x257f, 0xc02a, 0x21, 0 + .dw 0x25c0, 0xc02a, 0x25ff, 0xc02a, 0x21, 0 + .dw 0x2640, 0xc02a, 0x267f, 0xc02a, 0x21, 0 + .dw 0x26c0, 0xc02a, 0x26ff, 0xc02a, 0x21, 0 + .dw 0x2740, 0xc02a, 0x277f, 0xc02a, 0x21, 0 + .dw 0x27c0, 0xc02a, 0x27ff, 0xc02a, 0x21, 0 + .dw 0x2840, 0xc02a, 0x287f, 0xc02a, 0x21, 0 + .dw 0x28c0, 0xc02a, 0x28ff, 0xc02a, 0x21, 0 + .dw 0x2940, 0xc02a, 0x297f, 0xc02a, 0x21, 0 + .dw 0x29c0, 0xc02a, 0x29ff, 0xc02a, 0x21, 0 + .dw 0x2a40, 0xc02a, 0x2a7f, 0xc02a, 0x21, 0 + .dw 0x2ac0, 0xc02a, 0x2aff, 0xc02a, 0x21, 0 + .dw 0x2b40, 0xc02a, 0x2b7f, 0xc02a, 0x21, 0 + .dw 0x2bc0, 0xc02a, 0x2bff, 0xc02a, 0x21, 0 + .dw 0x2c40, 0xc02a, 0x2c7f, 0xc02a, 0x21, 0 + .dw 0x2cc0, 0xc02a, 0x2cff, 0xc02a, 0x21, 0 + .dw 0x2d40, 0xc02a, 0x2d7f, 0xc02a, 0x21, 0 + .dw 0x2dc0, 0xc02a, 0x2dff, 0xc02a, 0x21, 0 + .dw 0x2e40, 0xc02a, 0x2e7f, 0xc02a, 0x21, 0 + .dw 0x2ec0, 0xc02a, 0x2eff, 0xc02a, 0x21, 0 + .dw 0x2f40, 0xc02a, 0x2f7f, 0xc02a, 0x21, 0 + .dw 0x2fc0, 0xc02a, 0x2fff, 0xc02a, 0x21, 0 + .dw 0x3040, 0xc02a, 0x307f, 0xc02a, 0x21, 0 + .dw 0x30c0, 0xc02a, 0x30ff, 0xc02a, 0x21, 0 + .dw 0x3140, 0xc02a, 0x317f, 0xc02a, 0x21, 0 + .dw 0x31c0, 0xc02a, 0x31ff, 0xc02a, 0x21, 0 + .dw 0x3240, 0xc02a, 0x327f, 0xc02a, 0x21, 0 + .dw 0x32c0, 0xc02a, 0x32ff, 0xc02a, 0x21, 0 + .dw 0x3340, 0xc02a, 0x337f, 0xc02a, 0x21, 0 + .dw 0x33c0, 0xc02a, 0x33ff, 0xc02a, 0x21, 0 + .dw 0x3440, 0xc02a, 0x347f, 0xc02a, 0x21, 0 + .dw 0x34c0, 0xc02a, 0x34ff, 0xc02a, 0x21, 0 + .dw 0x3540, 0xc02a, 0x357f, 0xc02a, 0x21, 0 + .dw 0x35c0, 0xc02a, 0x35ff, 0xc02a, 0x21, 0 + .dw 0x3640, 0xc02a, 0x367f, 0xc02a, 0x21, 0 + .dw 0x36c0, 0xc02a, 0x36ff, 0xc02a, 0x21, 0 + .dw 0x3740, 0xc02a, 0x377f, 0xc02a, 0x21, 0 + .dw 0x37c0, 0xc02a, 0x37ff, 0xc02a, 0x21, 0 + .dw 0x3840, 0xc02a, 0x387f, 0xc02a, 0x21, 0 + .dw 0x38c0, 0xc02a, 0x38ff, 0xc02a, 0x21, 0 + .dw 0x3940, 0xc02a, 0x397f, 0xc02a, 0x21, 0 + .dw 0x39c0, 0xc02a, 0x5fff, 0xc02a, 0x21, 0 + .dw 0x6040, 0xc02a, 0x607f, 0xc02a, 0x21, 0 + .dw 0x60c0, 0xc02a, 0x60ff, 0xc02a, 0x21, 0 + .dw 0x6140, 0xc02a, 0x617f, 0xc02a, 0x21, 0 + .dw 0x61c0, 0xc02a, 0x61ff, 0xc02a, 0x21, 0 + .dw 0x6240, 0xc02a, 0x627f, 0xc02a, 0x21, 0 + .dw 0x62c0, 0xc02a, 0x62ff, 0xc02a, 0x21, 0 + .dw 0x6340, 0xc02a, 0x637f, 0xc02a, 0x21, 0 + .dw 0x63c0, 0xc02a, 0x63ff, 0xc02a, 0x21, 0 + .dw 0x6440, 0xc02a, 0x647f, 0xc02a, 0x21, 0 + .dw 0x64c0, 0xc02a, 0x64ff, 0xc02a, 0x21, 0 + .dw 0x6540, 0xc02a, 0x657f, 0xc02a, 0x21, 0 + .dw 0x65c0, 0xc02a, 0x65ff, 0xc02a, 0x21, 0 + .dw 0x6640, 0xc02a, 0x667f, 0xc02a, 0x21, 0 + .dw 0x66c0, 0xc02a, 0x66ff, 0xc02a, 0x21, 0 + .dw 0x6740, 0xc02a, 0x677f, 0xc02a, 0x21, 0 + .dw 0x67c0, 0xc02a, 0x67ff, 0xc02a, 0x21, 0 + .dw 0x6840, 0xc02a, 0x687f, 0xc02a, 0x21, 0 + .dw 0x68c0, 0xc02a, 0x68ff, 0xc02a, 0x21, 0 + .dw 0x6940, 0xc02a, 0x697f, 0xc02a, 0x21, 0 + .dw 0x69c0, 0xc02a, 0x69ff, 0xc02a, 0x21, 0 + .dw 0x6a40, 0xc02a, 0x6a7f, 0xc02a, 0x21, 0 + .dw 0x6ac0, 0xc02a, 0x6aff, 0xc02a, 0x21, 0 + .dw 0x6b40, 0xc02a, 0x6b7f, 0xc02a, 0x21, 0 + .dw 0x6bc0, 0xc02a, 0x6bff, 0xc02a, 0x21, 0 + .dw 0x6c40, 0xc02a, 0x6c7f, 0xc02a, 0x21, 0 + .dw 0x6cc0, 0xc02a, 0x6cff, 0xc02a, 0x21, 0 + .dw 0x6d40, 0xc02a, 0x6d7f, 0xc02a, 0x21, 0 + .dw 0x6dc0, 0xc02a, 0x6dff, 0xc02a, 0x21, 0 + .dw 0x6e40, 0xc02a, 0x6e7f, 0xc02a, 0x21, 0 + .dw 0x6ec0, 0xc02a, 0x6eff, 0xc02a, 0x21, 0 + .dw 0x6f40, 0xc02a, 0x6f7f, 0xc02a, 0x21, 0 + .dw 0x6fc0, 0xc02a, 0x6fff, 0xc02a, 0x21, 0 + .dw 0x7040, 0xc02a, 0x707f, 0xc02a, 0x21, 0 + .dw 0x70c0, 0xc02a, 0x70ff, 0xc02a, 0x21, 0 + .dw 0x7140, 0xc02a, 0x717f, 0xc02a, 0x21, 0 + .dw 0x71c0, 0xc02a, 0x71ff, 0xc02a, 0x21, 0 + .dw 0x7240, 0xc02a, 0x727f, 0xc02a, 0x21, 0 + .dw 0x72c0, 0xc02a, 0x72ff, 0xc02a, 0x21, 0 + .dw 0x7340, 0xc02a, 0x737f, 0xc02a, 0x21, 0 + .dw 0x73c0, 0xc02a, 0x73ff, 0xc02a, 0x21, 0 + .dw 0x7440, 0xc02a, 0x747f, 0xc02a, 0x21, 0 + .dw 0x74c0, 0xc02a, 0x74ff, 0xc02a, 0x21, 0 + .dw 0x7540, 0xc02a, 0x757f, 0xc02a, 0x21, 0 + .dw 0x75c0, 0xc02a, 0x75ff, 0xc02a, 0x21, 0 + .dw 0x7640, 0xc02a, 0x767f, 0xc02a, 0x21, 0 + .dw 0x76c0, 0xc02a, 0x76ff, 0xc02a, 0x21, 0 + .dw 0x7740, 0xc02a, 0x777f, 0xc02a, 0x21, 0 + .dw 0x77c0, 0xc02a, 0x77ff, 0xc02a, 0x21, 0 + .dw 0x7840, 0xc02a, 0x787f, 0xc02a, 0x21, 0 + .dw 0x78c0, 0xc02a, 0x78ff, 0xc02a, 0x21, 0 + .dw 0x7940, 0xc02a, 0x797f, 0xc02a, 0x21, 0 + .dw 0x79c0, 0xc02a, 0x9fff, 0xc02a, 0x21, 0 + .dw 0xa040, 0xc02a, 0xa07f, 0xc02a, 0x21, 0 + .dw 0xa0c0, 0xc02a, 0xa0ff, 0xc02a, 0x21, 0 + .dw 0xa140, 0xc02a, 0xa17f, 0xc02a, 0x21, 0 + .dw 0xa1c0, 0xc02a, 0xa1ff, 0xc02a, 0x21, 0 + .dw 0xa240, 0xc02a, 0xa27f, 0xc02a, 0x21, 0 + .dw 0xa2c0, 0xc02a, 0xa2ff, 0xc02a, 0x21, 0 + .dw 0xa340, 0xc02a, 0xa37f, 0xc02a, 0x21, 0 + .dw 0xa3c0, 0xc02a, 0xa3ff, 0xc02a, 0x21, 0 + .dw 0xa440, 0xc02a, 0xa47f, 0xc02a, 0x21, 0 + .dw 0xa4c0, 0xc02a, 0xa4ff, 0xc02a, 0x21, 0 + .dw 0xa540, 0xc02a, 0xa57f, 0xc02a, 0x21, 0 + .dw 0xa5c0, 0xc02a, 0xa5ff, 0xc02a, 0x21, 0 + .dw 0xa640, 0xc02a, 0xa67f, 0xc02a, 0x21, 0 + .dw 0xa6c0, 0xc02a, 0xa6ff, 0xc02a, 0x21, 0 + .dw 0xa740, 0xc02a, 0xa77f, 0xc02a, 0x21, 0 + .dw 0xa7c0, 0xc02a, 0xa7ff, 0xc02a, 0x21, 0 + .dw 0xa840, 0xc02a, 0xa87f, 0xc02a, 0x21, 0 + .dw 0xa8c0, 0xc02a, 0xa8ff, 0xc02a, 0x21, 0 + .dw 0xa940, 0xc02a, 0xa97f, 0xc02a, 0x21, 0 + .dw 0xa9c0, 0xc02a, 0xa9ff, 0xc02a, 0x21, 0 + .dw 0xaa40, 0xc02a, 0xaa7f, 0xc02a, 0x21, 0 + .dw 0xaac0, 0xc02a, 0xaaff, 0xc02a, 0x21, 0 + .dw 0xab40, 0xc02a, 0xab7f, 0xc02a, 0x21, 0 + .dw 0xabc0, 0xc02a, 0xabff, 0xc02a, 0x21, 0 + .dw 0xac40, 0xc02a, 0xac7f, 0xc02a, 0x21, 0 + .dw 0xacc0, 0xc02a, 0xacff, 0xc02a, 0x21, 0 + .dw 0xad40, 0xc02a, 0xad7f, 0xc02a, 0x21, 0 + .dw 0xadc0, 0xc02a, 0xadff, 0xc02a, 0x21, 0 + .dw 0xae40, 0xc02a, 0xae7f, 0xc02a, 0x21, 0 + .dw 0xaec0, 0xc02a, 0xaeff, 0xc02a, 0x21, 0 + .dw 0xaf40, 0xc02a, 0xaf7f, 0xc02a, 0x21, 0 + .dw 0xafc0, 0xc02a, 0xafff, 0xc02a, 0x21, 0 + .dw 0xb040, 0xc02a, 0xb07f, 0xc02a, 0x21, 0 + .dw 0xb0c0, 0xc02a, 0xb0ff, 0xc02a, 0x21, 0 + .dw 0xb140, 0xc02a, 0xb17f, 0xc02a, 0x21, 0 + .dw 0xb1c0, 0xc02a, 0xb1ff, 0xc02a, 0x21, 0 + .dw 0xb240, 0xc02a, 0xb27f, 0xc02a, 0x21, 0 + .dw 0xb2c0, 0xc02a, 0xb2ff, 0xc02a, 0x21, 0 + .dw 0xb340, 0xc02a, 0xb37f, 0xc02a, 0x21, 0 + .dw 0xb3c0, 0xc02a, 0xb3ff, 0xc02a, 0x21, 0 + .dw 0xb440, 0xc02a, 0xb47f, 0xc02a, 0x21, 0 + .dw 0xb4c0, 0xc02a, 0xb4ff, 0xc02a, 0x21, 0 + .dw 0xb540, 0xc02a, 0xb57f, 0xc02a, 0x21, 0 + .dw 0xb5c0, 0xc02a, 0xb5ff, 0xc02a, 0x21, 0 + .dw 0xb640, 0xc02a, 0xb67f, 0xc02a, 0x21, 0 + .dw 0xb6c0, 0xc02a, 0xb6ff, 0xc02a, 0x21, 0 + .dw 0xb740, 0xc02a, 0xb77f, 0xc02a, 0x21, 0 + .dw 0xb7c0, 0xc02a, 0xb7ff, 0xc02a, 0x21, 0 + .dw 0xb840, 0xc02a, 0xb87f, 0xc02a, 0x21, 0 + .dw 0xb8c0, 0xc02a, 0xb8ff, 0xc02a, 0x21, 0 + .dw 0xb940, 0xc02a, 0xb97f, 0xc02a, 0x21, 0 + .dw 0xb9c0, 0xc02a, 0xdfff, 0xc02a, 0x21, 0 + .dw 0xe040, 0xc02a, 0xe07f, 0xc02a, 0x21, 0 + .dw 0xe0c0, 0xc02a, 0xe0ff, 0xc02a, 0x21, 0 + .dw 0xe140, 0xc02a, 0xe17f, 0xc02a, 0x21, 0 + .dw 0xe1c0, 0xc02a, 0xe1ff, 0xc02a, 0x21, 0 + .dw 0xe240, 0xc02a, 0xe27f, 0xc02a, 0x21, 0 + .dw 0xe2c0, 0xc02a, 0xe2ff, 0xc02a, 0x21, 0 + .dw 0xe340, 0xc02a, 0xe37f, 0xc02a, 0x21, 0 + .dw 0xe3c0, 0xc02a, 0xe3ff, 0xc02a, 0x21, 0 + .dw 0xe440, 0xc02a, 0xe47f, 0xc02a, 0x21, 0 + .dw 0xe4c0, 0xc02a, 0xe4ff, 0xc02a, 0x21, 0 + .dw 0xe540, 0xc02a, 0xe57f, 0xc02a, 0x21, 0 + .dw 0xe5c0, 0xc02a, 0xe5ff, 0xc02a, 0x21, 0 + .dw 0xe640, 0xc02a, 0xe67f, 0xc02a, 0x21, 0 + .dw 0xe6c0, 0xc02a, 0xe6ff, 0xc02a, 0x21, 0 + .dw 0xe740, 0xc02a, 0xe77f, 0xc02a, 0x21, 0 + .dw 0xe7c0, 0xc02a, 0xe7ff, 0xc02a, 0x21, 0 + .dw 0xe840, 0xc02a, 0xe87f, 0xc02a, 0x21, 0 + .dw 0xe8c0, 0xc02a, 0xe8ff, 0xc02a, 0x21, 0 + .dw 0xe940, 0xc02a, 0xe97f, 0xc02a, 0x21, 0 + .dw 0xe9c0, 0xc02a, 0xe9ff, 0xc02a, 0x21, 0 + .dw 0xea40, 0xc02a, 0xea7f, 0xc02a, 0x21, 0 + .dw 0xeac0, 0xc02a, 0xeaff, 0xc02a, 0x21, 0 + .dw 0xeb40, 0xc02a, 0xeb7f, 0xc02a, 0x21, 0 + .dw 0xebc0, 0xc02a, 0xebff, 0xc02a, 0x21, 0 + .dw 0xec40, 0xc02a, 0xec7f, 0xc02a, 0x21, 0 + .dw 0xecc0, 0xc02a, 0xecff, 0xc02a, 0x21, 0 + .dw 0xed40, 0xc02a, 0xed7f, 0xc02a, 0x21, 0 + .dw 0xedc0, 0xc02a, 0xedff, 0xc02a, 0x21, 0 + .dw 0xee40, 0xc02a, 0xee7f, 0xc02a, 0x21, 0 + .dw 0xeec0, 0xc02a, 0xeeff, 0xc02a, 0x21, 0 + .dw 0xef40, 0xc02a, 0xef7f, 0xc02a, 0x21, 0 + .dw 0xefc0, 0xc02a, 0xefff, 0xc02a, 0x21, 0 + .dw 0xf040, 0xc02a, 0xf07f, 0xc02a, 0x21, 0 + .dw 0xf0c0, 0xc02a, 0xf0ff, 0xc02a, 0x21, 0 + .dw 0xf140, 0xc02a, 0xf17f, 0xc02a, 0x21, 0 + .dw 0xf1c0, 0xc02a, 0xf1ff, 0xc02a, 0x21, 0 + .dw 0xf240, 0xc02a, 0xf27f, 0xc02a, 0x21, 0 + .dw 0xf2c0, 0xc02a, 0xf2ff, 0xc02a, 0x21, 0 + .dw 0xf340, 0xc02a, 0xf37f, 0xc02a, 0x21, 0 + .dw 0xf3c0, 0xc02a, 0xf3ff, 0xc02a, 0x21, 0 + .dw 0xf440, 0xc02a, 0xf47f, 0xc02a, 0x21, 0 + .dw 0xf4c0, 0xc02a, 0xf4ff, 0xc02a, 0x21, 0 + .dw 0xf540, 0xc02a, 0xf57f, 0xc02a, 0x21, 0 + .dw 0xf5c0, 0xc02a, 0xf5ff, 0xc02a, 0x21, 0 + .dw 0xf640, 0xc02a, 0xf67f, 0xc02a, 0x21, 0 + .dw 0xf6c0, 0xc02a, 0xf6ff, 0xc02a, 0x21, 0 + .dw 0xf740, 0xc02a, 0xf77f, 0xc02a, 0x21, 0 + .dw 0xf7c0, 0xc02a, 0xf7ff, 0xc02a, 0x21, 0 + .dw 0xf840, 0xc02a, 0xf87f, 0xc02a, 0x21, 0 + .dw 0xf8c0, 0xc02a, 0xf8ff, 0xc02a, 0x21, 0 + .dw 0xf940, 0xc02a, 0xf97f, 0xc02a, 0x21, 0 + .dw 0xf9c0, 0xc02a, 0x1fff, 0xc02b, 0x21, 0 + .dw 0x2040, 0xc02b, 0x207f, 0xc02b, 0x21, 0 + .dw 0x20c0, 0xc02b, 0x20ff, 0xc02b, 0x21, 0 + .dw 0x2140, 0xc02b, 0x217f, 0xc02b, 0x21, 0 + .dw 0x21c0, 0xc02b, 0x21ff, 0xc02b, 0x21, 0 + .dw 0x2240, 0xc02b, 0x227f, 0xc02b, 0x21, 0 + .dw 0x22c0, 0xc02b, 0x22ff, 0xc02b, 0x21, 0 + .dw 0x2340, 0xc02b, 0x237f, 0xc02b, 0x21, 0 + .dw 0x23c0, 0xc02b, 0x23ff, 0xc02b, 0x21, 0 + .dw 0x2440, 0xc02b, 0x247f, 0xc02b, 0x21, 0 + .dw 0x24c0, 0xc02b, 0x24ff, 0xc02b, 0x21, 0 + .dw 0x2540, 0xc02b, 0x257f, 0xc02b, 0x21, 0 + .dw 0x25c0, 0xc02b, 0x25ff, 0xc02b, 0x21, 0 + .dw 0x2640, 0xc02b, 0x267f, 0xc02b, 0x21, 0 + .dw 0x26c0, 0xc02b, 0x26ff, 0xc02b, 0x21, 0 + .dw 0x2740, 0xc02b, 0x277f, 0xc02b, 0x21, 0 + .dw 0x27c0, 0xc02b, 0x27ff, 0xc02b, 0x21, 0 + .dw 0x2840, 0xc02b, 0x287f, 0xc02b, 0x21, 0 + .dw 0x28c0, 0xc02b, 0x28ff, 0xc02b, 0x21, 0 + .dw 0x2940, 0xc02b, 0x297f, 0xc02b, 0x21, 0 + .dw 0x29c0, 0xc02b, 0x29ff, 0xc02b, 0x21, 0 + .dw 0x2a40, 0xc02b, 0x2a7f, 0xc02b, 0x21, 0 + .dw 0x2ac0, 0xc02b, 0x2aff, 0xc02b, 0x21, 0 + .dw 0x2b40, 0xc02b, 0x2b7f, 0xc02b, 0x21, 0 + .dw 0x2bc0, 0xc02b, 0x2bff, 0xc02b, 0x21, 0 + .dw 0x2c40, 0xc02b, 0x2c7f, 0xc02b, 0x21, 0 + .dw 0x2cc0, 0xc02b, 0x2cff, 0xc02b, 0x21, 0 + .dw 0x2d40, 0xc02b, 0x2d7f, 0xc02b, 0x21, 0 + .dw 0x2dc0, 0xc02b, 0x2dff, 0xc02b, 0x21, 0 + .dw 0x2e40, 0xc02b, 0x2e7f, 0xc02b, 0x21, 0 + .dw 0x2ec0, 0xc02b, 0x2eff, 0xc02b, 0x21, 0 + .dw 0x2f40, 0xc02b, 0x2f7f, 0xc02b, 0x21, 0 + .dw 0x2fc0, 0xc02b, 0x2fff, 0xc02b, 0x21, 0 + .dw 0x3040, 0xc02b, 0x307f, 0xc02b, 0x21, 0 + .dw 0x30c0, 0xc02b, 0x30ff, 0xc02b, 0x21, 0 + .dw 0x3140, 0xc02b, 0x317f, 0xc02b, 0x21, 0 + .dw 0x31c0, 0xc02b, 0x31ff, 0xc02b, 0x21, 0 + .dw 0x3240, 0xc02b, 0x327f, 0xc02b, 0x21, 0 + .dw 0x32c0, 0xc02b, 0x32ff, 0xc02b, 0x21, 0 + .dw 0x3340, 0xc02b, 0x337f, 0xc02b, 0x21, 0 + .dw 0x33c0, 0xc02b, 0x33ff, 0xc02b, 0x21, 0 + .dw 0x3440, 0xc02b, 0x347f, 0xc02b, 0x21, 0 + .dw 0x34c0, 0xc02b, 0x34ff, 0xc02b, 0x21, 0 + .dw 0x3540, 0xc02b, 0x357f, 0xc02b, 0x21, 0 + .dw 0x35c0, 0xc02b, 0x35ff, 0xc02b, 0x21, 0 + .dw 0x3640, 0xc02b, 0x367f, 0xc02b, 0x21, 0 + .dw 0x36c0, 0xc02b, 0x36ff, 0xc02b, 0x21, 0 + .dw 0x3740, 0xc02b, 0x377f, 0xc02b, 0x21, 0 + .dw 0x37c0, 0xc02b, 0x37ff, 0xc02b, 0x21, 0 + .dw 0x3840, 0xc02b, 0x387f, 0xc02b, 0x21, 0 + .dw 0x38c0, 0xc02b, 0x38ff, 0xc02b, 0x21, 0 + .dw 0x3940, 0xc02b, 0x397f, 0xc02b, 0x21, 0 + .dw 0x39c0, 0xc02b, 0xffff, 0xc02b, 0x21, 0 + .dw 0x0040, 0xc02c, 0x007f, 0xc02c, 0x21, 0 + .dw 0x00c0, 0xc02c, 0x00ff, 0xc02c, 0x21, 0 + .dw 0x0140, 0xc02c, 0x017f, 0xc02c, 0x21, 0 + .dw 0x01c0, 0xc02c, 0x01ff, 0xc02c, 0x21, 0 + .dw 0x0240, 0xc02c, 0x027f, 0xc02c, 0x21, 0 + .dw 0x02c0, 0xc02c, 0x02ff, 0xc02c, 0x21, 0 + .dw 0x0340, 0xc02c, 0x037f, 0xc02c, 0x21, 0 + .dw 0x03c0, 0xc02c, 0x03ff, 0xc02c, 0x21, 0 + .dw 0x0440, 0xc02c, 0x047f, 0xc02c, 0x21, 0 + .dw 0x04c0, 0xc02c, 0x04ff, 0xc02c, 0x21, 0 + .dw 0x0540, 0xc02c, 0x057f, 0xc02c, 0x21, 0 + .dw 0x05c0, 0xc02c, 0x05ff, 0xc02c, 0x21, 0 + .dw 0x0640, 0xc02c, 0x067f, 0xc02c, 0x21, 0 + .dw 0x06c0, 0xc02c, 0x06ff, 0xc02c, 0x21, 0 + .dw 0x0740, 0xc02c, 0x077f, 0xc02c, 0x21, 0 + .dw 0x07c0, 0xc02c, 0x07ff, 0xc02c, 0x21, 0 + .dw 0x0840, 0xc02c, 0x087f, 0xc02c, 0x21, 0 + .dw 0x08c0, 0xc02c, 0x08ff, 0xc02c, 0x21, 0 + .dw 0x0940, 0xc02c, 0x097f, 0xc02c, 0x21, 0 + .dw 0x09c0, 0xc02c, 0x09ff, 0xc02c, 0x21, 0 + .dw 0x0a40, 0xc02c, 0x0a7f, 0xc02c, 0x21, 0 + .dw 0x0ac0, 0xc02c, 0x0aff, 0xc02c, 0x21, 0 + .dw 0x0b40, 0xc02c, 0x0b7f, 0xc02c, 0x21, 0 + .dw 0x0bc0, 0xc02c, 0x0bff, 0xc02c, 0x21, 0 + .dw 0x0c40, 0xc02c, 0x0c7f, 0xc02c, 0x21, 0 + .dw 0x0cc0, 0xc02c, 0x0cff, 0xc02c, 0x21, 0 + .dw 0x0d40, 0xc02c, 0x0d7f, 0xc02c, 0x21, 0 + .dw 0x0dc0, 0xc02c, 0x0dff, 0xc02c, 0x21, 0 + .dw 0x0e40, 0xc02c, 0x0e7f, 0xc02c, 0x21, 0 + .dw 0x0ec0, 0xc02c, 0x0eff, 0xc02c, 0x21, 0 + .dw 0x0f40, 0xc02c, 0x0f7f, 0xc02c, 0x21, 0 + .dw 0x0fc0, 0xc02c, 0x0fff, 0xc02c, 0x21, 0 + .dw 0x1040, 0xc02c, 0x107f, 0xc02c, 0x21, 0 + .dw 0x10c0, 0xc02c, 0x10ff, 0xc02c, 0x21, 0 + .dw 0x1140, 0xc02c, 0x117f, 0xc02c, 0x21, 0 + .dw 0x11c0, 0xc02c, 0x11ff, 0xc02c, 0x21, 0 + .dw 0x1240, 0xc02c, 0x127f, 0xc02c, 0x21, 0 + .dw 0x12c0, 0xc02c, 0x12ff, 0xc02c, 0x21, 0 + .dw 0x1340, 0xc02c, 0x137f, 0xc02c, 0x21, 0 + .dw 0x13c0, 0xc02c, 0x13ff, 0xc02c, 0x21, 0 + .dw 0x1440, 0xc02c, 0x147f, 0xc02c, 0x21, 0 + .dw 0x14c0, 0xc02c, 0x14ff, 0xc02c, 0x21, 0 + .dw 0x1540, 0xc02c, 0x157f, 0xc02c, 0x21, 0 + .dw 0x15c0, 0xc02c, 0x15ff, 0xc02c, 0x21, 0 + .dw 0x1640, 0xc02c, 0x167f, 0xc02c, 0x21, 0 + .dw 0x16c0, 0xc02c, 0x16ff, 0xc02c, 0x21, 0 + .dw 0x1740, 0xc02c, 0x177f, 0xc02c, 0x21, 0 + .dw 0x17c0, 0xc02c, 0x17ff, 0xc02c, 0x21, 0 + .dw 0x1840, 0xc02c, 0x187f, 0xc02c, 0x21, 0 + .dw 0x18c0, 0xc02c, 0x18ff, 0xc02c, 0x21, 0 + .dw 0x1940, 0xc02c, 0x197f, 0xc02c, 0x21, 0 + .dw 0x19c0, 0xc02c, 0x1fff, 0xc02c, 0x21, 0 + .dw 0x2040, 0xc02c, 0x207f, 0xc02c, 0x21, 0 + .dw 0x20c0, 0xc02c, 0x20ff, 0xc02c, 0x21, 0 + .dw 0x2140, 0xc02c, 0x217f, 0xc02c, 0x21, 0 + .dw 0x21c0, 0xc02c, 0x21ff, 0xc02c, 0x21, 0 + .dw 0x2240, 0xc02c, 0x227f, 0xc02c, 0x21, 0 + .dw 0x22c0, 0xc02c, 0x22ff, 0xc02c, 0x21, 0 + .dw 0x2340, 0xc02c, 0x237f, 0xc02c, 0x21, 0 + .dw 0x23c0, 0xc02c, 0x23ff, 0xc02c, 0x21, 0 + .dw 0x2440, 0xc02c, 0x247f, 0xc02c, 0x21, 0 + .dw 0x24c0, 0xc02c, 0x24ff, 0xc02c, 0x21, 0 + .dw 0x2540, 0xc02c, 0x257f, 0xc02c, 0x21, 0 + .dw 0x25c0, 0xc02c, 0x25ff, 0xc02c, 0x21, 0 + .dw 0x2640, 0xc02c, 0x267f, 0xc02c, 0x21, 0 + .dw 0x26c0, 0xc02c, 0x26ff, 0xc02c, 0x21, 0 + .dw 0x2740, 0xc02c, 0x277f, 0xc02c, 0x21, 0 + .dw 0x27c0, 0xc02c, 0x27ff, 0xc02c, 0x21, 0 + .dw 0x2840, 0xc02c, 0x287f, 0xc02c, 0x21, 0 + .dw 0x28c0, 0xc02c, 0x28ff, 0xc02c, 0x21, 0 + .dw 0x2940, 0xc02c, 0x297f, 0xc02c, 0x21, 0 + .dw 0x29c0, 0xc02c, 0x29ff, 0xc02c, 0x21, 0 + .dw 0x2a40, 0xc02c, 0x2a7f, 0xc02c, 0x21, 0 + .dw 0x2ac0, 0xc02c, 0x2aff, 0xc02c, 0x21, 0 + .dw 0x2b40, 0xc02c, 0x2b7f, 0xc02c, 0x21, 0 + .dw 0x2bc0, 0xc02c, 0x2bff, 0xc02c, 0x21, 0 + .dw 0x2c40, 0xc02c, 0x2c7f, 0xc02c, 0x21, 0 + .dw 0x2cc0, 0xc02c, 0x2cff, 0xc02c, 0x21, 0 + .dw 0x2d40, 0xc02c, 0x2d7f, 0xc02c, 0x21, 0 + .dw 0x2dc0, 0xc02c, 0x2dff, 0xc02c, 0x21, 0 + .dw 0x2e40, 0xc02c, 0x2e7f, 0xc02c, 0x21, 0 + .dw 0x2ec0, 0xc02c, 0x2eff, 0xc02c, 0x21, 0 + .dw 0x2f40, 0xc02c, 0x2f7f, 0xc02c, 0x21, 0 + .dw 0x2fc0, 0xc02c, 0x2fff, 0xc02c, 0x21, 0 + .dw 0x3040, 0xc02c, 0x307f, 0xc02c, 0x21, 0 + .dw 0x30c0, 0xc02c, 0x30ff, 0xc02c, 0x21, 0 + .dw 0x3140, 0xc02c, 0x317f, 0xc02c, 0x21, 0 + .dw 0x31c0, 0xc02c, 0x31ff, 0xc02c, 0x21, 0 + .dw 0x3240, 0xc02c, 0x327f, 0xc02c, 0x21, 0 + .dw 0x32c0, 0xc02c, 0x32ff, 0xc02c, 0x21, 0 + .dw 0x3340, 0xc02c, 0x337f, 0xc02c, 0x21, 0 + .dw 0x33c0, 0xc02c, 0x33ff, 0xc02c, 0x21, 0 + .dw 0x3440, 0xc02c, 0x347f, 0xc02c, 0x21, 0 + .dw 0x34c0, 0xc02c, 0x34ff, 0xc02c, 0x21, 0 + .dw 0x3540, 0xc02c, 0x357f, 0xc02c, 0x21, 0 + .dw 0x35c0, 0xc02c, 0x35ff, 0xc02c, 0x21, 0 + .dw 0x3640, 0xc02c, 0x367f, 0xc02c, 0x21, 0 + .dw 0x36c0, 0xc02c, 0x36ff, 0xc02c, 0x21, 0 + .dw 0x3740, 0xc02c, 0x377f, 0xc02c, 0x21, 0 + .dw 0x37c0, 0xc02c, 0x37ff, 0xc02c, 0x21, 0 + .dw 0x3840, 0xc02c, 0x387f, 0xc02c, 0x21, 0 + .dw 0x38c0, 0xc02c, 0x38ff, 0xc02c, 0x21, 0 + .dw 0x3940, 0xc02c, 0x397f, 0xc02c, 0x21, 0 + .dw 0x39c0, 0xc02c, 0x3fff, 0xc02c, 0x21, 0 + .dw 0x4040, 0xc02c, 0x407f, 0xc02c, 0x21, 0 + .dw 0x40c0, 0xc02c, 0x40ff, 0xc02c, 0x21, 0 + .dw 0x4140, 0xc02c, 0x417f, 0xc02c, 0x21, 0 + .dw 0x41c0, 0xc02c, 0x41ff, 0xc02c, 0x21, 0 + .dw 0x4240, 0xc02c, 0x427f, 0xc02c, 0x21, 0 + .dw 0x42c0, 0xc02c, 0x42ff, 0xc02c, 0x21, 0 + .dw 0x4340, 0xc02c, 0x437f, 0xc02c, 0x21, 0 + .dw 0x43c0, 0xc02c, 0x43ff, 0xc02c, 0x21, 0 + .dw 0x4440, 0xc02c, 0x447f, 0xc02c, 0x21, 0 + .dw 0x44c0, 0xc02c, 0x44ff, 0xc02c, 0x21, 0 + .dw 0x4540, 0xc02c, 0x457f, 0xc02c, 0x21, 0 + .dw 0x45c0, 0xc02c, 0x45ff, 0xc02c, 0x21, 0 + .dw 0x4640, 0xc02c, 0x467f, 0xc02c, 0x21, 0 + .dw 0x46c0, 0xc02c, 0x46ff, 0xc02c, 0x21, 0 + .dw 0x4740, 0xc02c, 0x477f, 0xc02c, 0x21, 0 + .dw 0x47c0, 0xc02c, 0x47ff, 0xc02c, 0x21, 0 + .dw 0x4840, 0xc02c, 0x487f, 0xc02c, 0x21, 0 + .dw 0x48c0, 0xc02c, 0x48ff, 0xc02c, 0x21, 0 + .dw 0x4940, 0xc02c, 0x497f, 0xc02c, 0x21, 0 + .dw 0x49c0, 0xc02c, 0x49ff, 0xc02c, 0x21, 0 + .dw 0x4a40, 0xc02c, 0x4a7f, 0xc02c, 0x21, 0 + .dw 0x4ac0, 0xc02c, 0x4aff, 0xc02c, 0x21, 0 + .dw 0x4b40, 0xc02c, 0x4b7f, 0xc02c, 0x21, 0 + .dw 0x4bc0, 0xc02c, 0x4bff, 0xc02c, 0x21, 0 + .dw 0x4c40, 0xc02c, 0x4c7f, 0xc02c, 0x21, 0 + .dw 0x4cc0, 0xc02c, 0x4cff, 0xc02c, 0x21, 0 + .dw 0x4d40, 0xc02c, 0x4d7f, 0xc02c, 0x21, 0 + .dw 0x4dc0, 0xc02c, 0x4dff, 0xc02c, 0x21, 0 + .dw 0x4e40, 0xc02c, 0x4e7f, 0xc02c, 0x21, 0 + .dw 0x4ec0, 0xc02c, 0x4eff, 0xc02c, 0x21, 0 + .dw 0x4f40, 0xc02c, 0x4f7f, 0xc02c, 0x21, 0 + .dw 0x4fc0, 0xc02c, 0x4fff, 0xc02c, 0x21, 0 + .dw 0x5040, 0xc02c, 0x507f, 0xc02c, 0x21, 0 + .dw 0x50c0, 0xc02c, 0x50ff, 0xc02c, 0x21, 0 + .dw 0x5140, 0xc02c, 0x517f, 0xc02c, 0x21, 0 + .dw 0x51c0, 0xc02c, 0x51ff, 0xc02c, 0x21, 0 + .dw 0x5240, 0xc02c, 0x527f, 0xc02c, 0x21, 0 + .dw 0x52c0, 0xc02c, 0x52ff, 0xc02c, 0x21, 0 + .dw 0x5340, 0xc02c, 0x537f, 0xc02c, 0x21, 0 + .dw 0x53c0, 0xc02c, 0x53ff, 0xc02c, 0x21, 0 + .dw 0x5440, 0xc02c, 0x547f, 0xc02c, 0x21, 0 + .dw 0x54c0, 0xc02c, 0x54ff, 0xc02c, 0x21, 0 + .dw 0x5540, 0xc02c, 0x557f, 0xc02c, 0x21, 0 + .dw 0x55c0, 0xc02c, 0x55ff, 0xc02c, 0x21, 0 + .dw 0x5640, 0xc02c, 0x567f, 0xc02c, 0x21, 0 + .dw 0x56c0, 0xc02c, 0x56ff, 0xc02c, 0x21, 0 + .dw 0x5740, 0xc02c, 0x577f, 0xc02c, 0x21, 0 + .dw 0x57c0, 0xc02c, 0x57ff, 0xc02c, 0x21, 0 + .dw 0x5840, 0xc02c, 0x587f, 0xc02c, 0x21, 0 + .dw 0x58c0, 0xc02c, 0x58ff, 0xc02c, 0x21, 0 + .dw 0x5940, 0xc02c, 0x597f, 0xc02c, 0x21, 0 + .dw 0x59c0, 0xc02c, 0x5fff, 0xc02c, 0x21, 0 + .dw 0x6040, 0xc02c, 0x607f, 0xc02c, 0x21, 0 + .dw 0x60c0, 0xc02c, 0x60ff, 0xc02c, 0x21, 0 + .dw 0x6140, 0xc02c, 0x617f, 0xc02c, 0x21, 0 + .dw 0x61c0, 0xc02c, 0x61ff, 0xc02c, 0x21, 0 + .dw 0x6240, 0xc02c, 0x627f, 0xc02c, 0x21, 0 + .dw 0x62c0, 0xc02c, 0x62ff, 0xc02c, 0x21, 0 + .dw 0x6340, 0xc02c, 0x637f, 0xc02c, 0x21, 0 + .dw 0x63c0, 0xc02c, 0x63ff, 0xc02c, 0x21, 0 + .dw 0x6440, 0xc02c, 0x647f, 0xc02c, 0x21, 0 + .dw 0x64c0, 0xc02c, 0x64ff, 0xc02c, 0x21, 0 + .dw 0x6540, 0xc02c, 0x657f, 0xc02c, 0x21, 0 + .dw 0x65c0, 0xc02c, 0x65ff, 0xc02c, 0x21, 0 + .dw 0x6640, 0xc02c, 0x667f, 0xc02c, 0x21, 0 + .dw 0x66c0, 0xc02c, 0x66ff, 0xc02c, 0x21, 0 + .dw 0x6740, 0xc02c, 0x677f, 0xc02c, 0x21, 0 + .dw 0x67c0, 0xc02c, 0x67ff, 0xc02c, 0x21, 0 + .dw 0x6840, 0xc02c, 0x687f, 0xc02c, 0x21, 0 + .dw 0x68c0, 0xc02c, 0x68ff, 0xc02c, 0x21, 0 + .dw 0x6940, 0xc02c, 0x697f, 0xc02c, 0x21, 0 + .dw 0x69c0, 0xc02c, 0x69ff, 0xc02c, 0x21, 0 + .dw 0x6a40, 0xc02c, 0x6a7f, 0xc02c, 0x21, 0 + .dw 0x6ac0, 0xc02c, 0x6aff, 0xc02c, 0x21, 0 + .dw 0x6b40, 0xc02c, 0x6b7f, 0xc02c, 0x21, 0 + .dw 0x6bc0, 0xc02c, 0x6bff, 0xc02c, 0x21, 0 + .dw 0x6c40, 0xc02c, 0x6c7f, 0xc02c, 0x21, 0 + .dw 0x6cc0, 0xc02c, 0x6cff, 0xc02c, 0x21, 0 + .dw 0x6d40, 0xc02c, 0x6d7f, 0xc02c, 0x21, 0 + .dw 0x6dc0, 0xc02c, 0x6dff, 0xc02c, 0x21, 0 + .dw 0x6e40, 0xc02c, 0x6e7f, 0xc02c, 0x21, 0 + .dw 0x6ec0, 0xc02c, 0x6eff, 0xc02c, 0x21, 0 + .dw 0x6f40, 0xc02c, 0x6f7f, 0xc02c, 0x21, 0 + .dw 0x6fc0, 0xc02c, 0x6fff, 0xc02c, 0x21, 0 + .dw 0x7040, 0xc02c, 0x707f, 0xc02c, 0x21, 0 + .dw 0x70c0, 0xc02c, 0x70ff, 0xc02c, 0x21, 0 + .dw 0x7140, 0xc02c, 0x717f, 0xc02c, 0x21, 0 + .dw 0x71c0, 0xc02c, 0x71ff, 0xc02c, 0x21, 0 + .dw 0x7240, 0xc02c, 0x727f, 0xc02c, 0x21, 0 + .dw 0x72c0, 0xc02c, 0x72ff, 0xc02c, 0x21, 0 + .dw 0x7340, 0xc02c, 0x737f, 0xc02c, 0x21, 0 + .dw 0x73c0, 0xc02c, 0x73ff, 0xc02c, 0x21, 0 + .dw 0x7440, 0xc02c, 0x747f, 0xc02c, 0x21, 0 + .dw 0x74c0, 0xc02c, 0x74ff, 0xc02c, 0x21, 0 + .dw 0x7540, 0xc02c, 0x757f, 0xc02c, 0x21, 0 + .dw 0x75c0, 0xc02c, 0x75ff, 0xc02c, 0x21, 0 + .dw 0x7640, 0xc02c, 0x767f, 0xc02c, 0x21, 0 + .dw 0x76c0, 0xc02c, 0x76ff, 0xc02c, 0x21, 0 + .dw 0x7740, 0xc02c, 0x777f, 0xc02c, 0x21, 0 + .dw 0x77c0, 0xc02c, 0x77ff, 0xc02c, 0x21, 0 + .dw 0x7840, 0xc02c, 0x787f, 0xc02c, 0x21, 0 + .dw 0x78c0, 0xc02c, 0x78ff, 0xc02c, 0x21, 0 + .dw 0x7940, 0xc02c, 0x797f, 0xc02c, 0x21, 0 + .dw 0x79c0, 0xc02c, 0x7fff, 0xc02c, 0x21, 0 + .dw 0x8040, 0xc02c, 0x807f, 0xc02c, 0x21, 0 + .dw 0x80c0, 0xc02c, 0x80ff, 0xc02c, 0x21, 0 + .dw 0x8140, 0xc02c, 0x817f, 0xc02c, 0x21, 0 + .dw 0x81c0, 0xc02c, 0x81ff, 0xc02c, 0x21, 0 + .dw 0x8240, 0xc02c, 0x827f, 0xc02c, 0x21, 0 + .dw 0x82c0, 0xc02c, 0x82ff, 0xc02c, 0x21, 0 + .dw 0x8340, 0xc02c, 0x837f, 0xc02c, 0x21, 0 + .dw 0x83c0, 0xc02c, 0x83ff, 0xc02c, 0x21, 0 + .dw 0x8440, 0xc02c, 0x847f, 0xc02c, 0x21, 0 + .dw 0x84c0, 0xc02c, 0x84ff, 0xc02c, 0x21, 0 + .dw 0x8540, 0xc02c, 0x857f, 0xc02c, 0x21, 0 + .dw 0x85c0, 0xc02c, 0x85ff, 0xc02c, 0x21, 0 + .dw 0x8640, 0xc02c, 0x867f, 0xc02c, 0x21, 0 + .dw 0x86c0, 0xc02c, 0x86ff, 0xc02c, 0x21, 0 + .dw 0x8740, 0xc02c, 0x877f, 0xc02c, 0x21, 0 + .dw 0x87c0, 0xc02c, 0x87ff, 0xc02c, 0x21, 0 + .dw 0x8840, 0xc02c, 0x887f, 0xc02c, 0x21, 0 + .dw 0x88c0, 0xc02c, 0x88ff, 0xc02c, 0x21, 0 + .dw 0x8940, 0xc02c, 0x897f, 0xc02c, 0x21, 0 + .dw 0x89c0, 0xc02c, 0x89ff, 0xc02c, 0x21, 0 + .dw 0x8a40, 0xc02c, 0x8a7f, 0xc02c, 0x21, 0 + .dw 0x8ac0, 0xc02c, 0x8aff, 0xc02c, 0x21, 0 + .dw 0x8b40, 0xc02c, 0x8b7f, 0xc02c, 0x21, 0 + .dw 0x8bc0, 0xc02c, 0x8bff, 0xc02c, 0x21, 0 + .dw 0x8c40, 0xc02c, 0x8c7f, 0xc02c, 0x21, 0 + .dw 0x8cc0, 0xc02c, 0x8cff, 0xc02c, 0x21, 0 + .dw 0x8d40, 0xc02c, 0x8d7f, 0xc02c, 0x21, 0 + .dw 0x8dc0, 0xc02c, 0x8dff, 0xc02c, 0x21, 0 + .dw 0x8e40, 0xc02c, 0x8e7f, 0xc02c, 0x21, 0 + .dw 0x8ec0, 0xc02c, 0x8eff, 0xc02c, 0x21, 0 + .dw 0x8f40, 0xc02c, 0x8f7f, 0xc02c, 0x21, 0 + .dw 0x8fc0, 0xc02c, 0x8fff, 0xc02c, 0x21, 0 + .dw 0x9040, 0xc02c, 0x907f, 0xc02c, 0x21, 0 + .dw 0x90c0, 0xc02c, 0x90ff, 0xc02c, 0x21, 0 + .dw 0x9140, 0xc02c, 0x917f, 0xc02c, 0x21, 0 + .dw 0x91c0, 0xc02c, 0x91ff, 0xc02c, 0x21, 0 + .dw 0x9240, 0xc02c, 0x927f, 0xc02c, 0x21, 0 + .dw 0x92c0, 0xc02c, 0x92ff, 0xc02c, 0x21, 0 + .dw 0x9340, 0xc02c, 0x937f, 0xc02c, 0x21, 0 + .dw 0x93c0, 0xc02c, 0x93ff, 0xc02c, 0x21, 0 + .dw 0x9440, 0xc02c, 0x947f, 0xc02c, 0x21, 0 + .dw 0x94c0, 0xc02c, 0x94ff, 0xc02c, 0x21, 0 + .dw 0x9540, 0xc02c, 0x957f, 0xc02c, 0x21, 0 + .dw 0x95c0, 0xc02c, 0x95ff, 0xc02c, 0x21, 0 + .dw 0x9640, 0xc02c, 0x967f, 0xc02c, 0x21, 0 + .dw 0x96c0, 0xc02c, 0x96ff, 0xc02c, 0x21, 0 + .dw 0x9740, 0xc02c, 0x977f, 0xc02c, 0x21, 0 + .dw 0x97c0, 0xc02c, 0x97ff, 0xc02c, 0x21, 0 + .dw 0x9840, 0xc02c, 0x987f, 0xc02c, 0x21, 0 + .dw 0x98c0, 0xc02c, 0x98ff, 0xc02c, 0x21, 0 + .dw 0x9940, 0xc02c, 0x997f, 0xc02c, 0x21, 0 + .dw 0x99c0, 0xc02c, 0x9fff, 0xc02c, 0x21, 0 + .dw 0xa040, 0xc02c, 0xa07f, 0xc02c, 0x21, 0 + .dw 0xa0c0, 0xc02c, 0xa0ff, 0xc02c, 0x21, 0 + .dw 0xa140, 0xc02c, 0xa17f, 0xc02c, 0x21, 0 + .dw 0xa1c0, 0xc02c, 0xa1ff, 0xc02c, 0x21, 0 + .dw 0xa240, 0xc02c, 0xa27f, 0xc02c, 0x21, 0 + .dw 0xa2c0, 0xc02c, 0xa2ff, 0xc02c, 0x21, 0 + .dw 0xa340, 0xc02c, 0xa37f, 0xc02c, 0x21, 0 + .dw 0xa3c0, 0xc02c, 0xa3ff, 0xc02c, 0x21, 0 + .dw 0xa440, 0xc02c, 0xa47f, 0xc02c, 0x21, 0 + .dw 0xa4c0, 0xc02c, 0xa4ff, 0xc02c, 0x21, 0 + .dw 0xa540, 0xc02c, 0xa57f, 0xc02c, 0x21, 0 + .dw 0xa5c0, 0xc02c, 0xa5ff, 0xc02c, 0x21, 0 + .dw 0xa640, 0xc02c, 0xa67f, 0xc02c, 0x21, 0 + .dw 0xa6c0, 0xc02c, 0xa6ff, 0xc02c, 0x21, 0 + .dw 0xa740, 0xc02c, 0xa77f, 0xc02c, 0x21, 0 + .dw 0xa7c0, 0xc02c, 0xa7ff, 0xc02c, 0x21, 0 + .dw 0xa840, 0xc02c, 0xa87f, 0xc02c, 0x21, 0 + .dw 0xa8c0, 0xc02c, 0xa8ff, 0xc02c, 0x21, 0 + .dw 0xa940, 0xc02c, 0xa97f, 0xc02c, 0x21, 0 + .dw 0xa9c0, 0xc02c, 0xa9ff, 0xc02c, 0x21, 0 + .dw 0xaa40, 0xc02c, 0xaa7f, 0xc02c, 0x21, 0 + .dw 0xaac0, 0xc02c, 0xaaff, 0xc02c, 0x21, 0 + .dw 0xab40, 0xc02c, 0xab7f, 0xc02c, 0x21, 0 + .dw 0xabc0, 0xc02c, 0xabff, 0xc02c, 0x21, 0 + .dw 0xac40, 0xc02c, 0xac7f, 0xc02c, 0x21, 0 + .dw 0xacc0, 0xc02c, 0xacff, 0xc02c, 0x21, 0 + .dw 0xad40, 0xc02c, 0xad7f, 0xc02c, 0x21, 0 + .dw 0xadc0, 0xc02c, 0xadff, 0xc02c, 0x21, 0 + .dw 0xae40, 0xc02c, 0xae7f, 0xc02c, 0x21, 0 + .dw 0xaec0, 0xc02c, 0xaeff, 0xc02c, 0x21, 0 + .dw 0xaf40, 0xc02c, 0xaf7f, 0xc02c, 0x21, 0 + .dw 0xafc0, 0xc02c, 0xafff, 0xc02c, 0x21, 0 + .dw 0xb040, 0xc02c, 0xb07f, 0xc02c, 0x21, 0 + .dw 0xb0c0, 0xc02c, 0xb0ff, 0xc02c, 0x21, 0 + .dw 0xb140, 0xc02c, 0xb17f, 0xc02c, 0x21, 0 + .dw 0xb1c0, 0xc02c, 0xb1ff, 0xc02c, 0x21, 0 + .dw 0xb240, 0xc02c, 0xb27f, 0xc02c, 0x21, 0 + .dw 0xb2c0, 0xc02c, 0xb2ff, 0xc02c, 0x21, 0 + .dw 0xb340, 0xc02c, 0xb37f, 0xc02c, 0x21, 0 + .dw 0xb3c0, 0xc02c, 0xb3ff, 0xc02c, 0x21, 0 + .dw 0xb440, 0xc02c, 0xb47f, 0xc02c, 0x21, 0 + .dw 0xb4c0, 0xc02c, 0xb4ff, 0xc02c, 0x21, 0 + .dw 0xb540, 0xc02c, 0xb57f, 0xc02c, 0x21, 0 + .dw 0xb5c0, 0xc02c, 0xb5ff, 0xc02c, 0x21, 0 + .dw 0xb640, 0xc02c, 0xb67f, 0xc02c, 0x21, 0 + .dw 0xb6c0, 0xc02c, 0xb6ff, 0xc02c, 0x21, 0 + .dw 0xb740, 0xc02c, 0xb77f, 0xc02c, 0x21, 0 + .dw 0xb7c0, 0xc02c, 0xb7ff, 0xc02c, 0x21, 0 + .dw 0xb840, 0xc02c, 0xb87f, 0xc02c, 0x21, 0 + .dw 0xb8c0, 0xc02c, 0xb8ff, 0xc02c, 0x21, 0 + .dw 0xb940, 0xc02c, 0xb97f, 0xc02c, 0x21, 0 + .dw 0xb9c0, 0xc02c, 0xbfff, 0xc02c, 0x21, 0 + .dw 0xc040, 0xc02c, 0xc07f, 0xc02c, 0x21, 0 + .dw 0xc0c0, 0xc02c, 0xc0ff, 0xc02c, 0x21, 0 + .dw 0xc140, 0xc02c, 0xc17f, 0xc02c, 0x21, 0 + .dw 0xc1c0, 0xc02c, 0xc1ff, 0xc02c, 0x21, 0 + .dw 0xc240, 0xc02c, 0xc27f, 0xc02c, 0x21, 0 + .dw 0xc2c0, 0xc02c, 0xc2ff, 0xc02c, 0x21, 0 + .dw 0xc340, 0xc02c, 0xc37f, 0xc02c, 0x21, 0 + .dw 0xc3c0, 0xc02c, 0xc3ff, 0xc02c, 0x21, 0 + .dw 0xc440, 0xc02c, 0xc47f, 0xc02c, 0x21, 0 + .dw 0xc4c0, 0xc02c, 0xc4ff, 0xc02c, 0x21, 0 + .dw 0xc540, 0xc02c, 0xc57f, 0xc02c, 0x21, 0 + .dw 0xc5c0, 0xc02c, 0xc5ff, 0xc02c, 0x21, 0 + .dw 0xc640, 0xc02c, 0xc67f, 0xc02c, 0x21, 0 + .dw 0xc6c0, 0xc02c, 0xc6ff, 0xc02c, 0x21, 0 + .dw 0xc740, 0xc02c, 0xc77f, 0xc02c, 0x21, 0 + .dw 0xc7c0, 0xc02c, 0xc7ff, 0xc02c, 0x21, 0 + .dw 0xc840, 0xc02c, 0xc87f, 0xc02c, 0x21, 0 + .dw 0xc8c0, 0xc02c, 0xc8ff, 0xc02c, 0x21, 0 + .dw 0xc940, 0xc02c, 0xc97f, 0xc02c, 0x21, 0 + .dw 0xc9c0, 0xc02c, 0xc9ff, 0xc02c, 0x21, 0 + .dw 0xca40, 0xc02c, 0xca7f, 0xc02c, 0x21, 0 + .dw 0xcac0, 0xc02c, 0xcaff, 0xc02c, 0x21, 0 + .dw 0xcb40, 0xc02c, 0xcb7f, 0xc02c, 0x21, 0 + .dw 0xcbc0, 0xc02c, 0xcbff, 0xc02c, 0x21, 0 + .dw 0xcc40, 0xc02c, 0xcc7f, 0xc02c, 0x21, 0 + .dw 0xccc0, 0xc02c, 0xccff, 0xc02c, 0x21, 0 + .dw 0xcd40, 0xc02c, 0xcd7f, 0xc02c, 0x21, 0 + .dw 0xcdc0, 0xc02c, 0xcdff, 0xc02c, 0x21, 0 + .dw 0xce40, 0xc02c, 0xce7f, 0xc02c, 0x21, 0 + .dw 0xcec0, 0xc02c, 0xceff, 0xc02c, 0x21, 0 + .dw 0xcf40, 0xc02c, 0xcf7f, 0xc02c, 0x21, 0 + .dw 0xcfc0, 0xc02c, 0xcfff, 0xc02c, 0x21, 0 + .dw 0xd040, 0xc02c, 0xd07f, 0xc02c, 0x21, 0 + .dw 0xd0c0, 0xc02c, 0xd0ff, 0xc02c, 0x21, 0 + .dw 0xd140, 0xc02c, 0xd17f, 0xc02c, 0x21, 0 + .dw 0xd1c0, 0xc02c, 0xd1ff, 0xc02c, 0x21, 0 + .dw 0xd240, 0xc02c, 0xd27f, 0xc02c, 0x21, 0 + .dw 0xd2c0, 0xc02c, 0xd2ff, 0xc02c, 0x21, 0 + .dw 0xd340, 0xc02c, 0xd37f, 0xc02c, 0x21, 0 + .dw 0xd3c0, 0xc02c, 0xd3ff, 0xc02c, 0x21, 0 + .dw 0xd440, 0xc02c, 0xd47f, 0xc02c, 0x21, 0 + .dw 0xd4c0, 0xc02c, 0xd4ff, 0xc02c, 0x21, 0 + .dw 0xd540, 0xc02c, 0xd57f, 0xc02c, 0x21, 0 + .dw 0xd5c0, 0xc02c, 0xd5ff, 0xc02c, 0x21, 0 + .dw 0xd640, 0xc02c, 0xd67f, 0xc02c, 0x21, 0 + .dw 0xd6c0, 0xc02c, 0xd6ff, 0xc02c, 0x21, 0 + .dw 0xd740, 0xc02c, 0xd77f, 0xc02c, 0x21, 0 + .dw 0xd7c0, 0xc02c, 0xd7ff, 0xc02c, 0x21, 0 + .dw 0xd840, 0xc02c, 0xd87f, 0xc02c, 0x21, 0 + .dw 0xd8c0, 0xc02c, 0xd8ff, 0xc02c, 0x21, 0 + .dw 0xd940, 0xc02c, 0xd97f, 0xc02c, 0x21, 0 + .dw 0xd9c0, 0xc02c, 0xdfff, 0xc02c, 0x21, 0 + .dw 0xe040, 0xc02c, 0xe07f, 0xc02c, 0x21, 0 + .dw 0xe0c0, 0xc02c, 0xe0ff, 0xc02c, 0x21, 0 + .dw 0xe140, 0xc02c, 0xe17f, 0xc02c, 0x21, 0 + .dw 0xe1c0, 0xc02c, 0xe1ff, 0xc02c, 0x21, 0 + .dw 0xe240, 0xc02c, 0xe27f, 0xc02c, 0x21, 0 + .dw 0xe2c0, 0xc02c, 0xe2ff, 0xc02c, 0x21, 0 + .dw 0xe340, 0xc02c, 0xe37f, 0xc02c, 0x21, 0 + .dw 0xe3c0, 0xc02c, 0xe3ff, 0xc02c, 0x21, 0 + .dw 0xe440, 0xc02c, 0xe47f, 0xc02c, 0x21, 0 + .dw 0xe4c0, 0xc02c, 0xe4ff, 0xc02c, 0x21, 0 + .dw 0xe540, 0xc02c, 0xe57f, 0xc02c, 0x21, 0 + .dw 0xe5c0, 0xc02c, 0xe5ff, 0xc02c, 0x21, 0 + .dw 0xe640, 0xc02c, 0xe67f, 0xc02c, 0x21, 0 + .dw 0xe6c0, 0xc02c, 0xe6ff, 0xc02c, 0x21, 0 + .dw 0xe740, 0xc02c, 0xe77f, 0xc02c, 0x21, 0 + .dw 0xe7c0, 0xc02c, 0xe7ff, 0xc02c, 0x21, 0 + .dw 0xe840, 0xc02c, 0xe87f, 0xc02c, 0x21, 0 + .dw 0xe8c0, 0xc02c, 0xe8ff, 0xc02c, 0x21, 0 + .dw 0xe940, 0xc02c, 0xe97f, 0xc02c, 0x21, 0 + .dw 0xe9c0, 0xc02c, 0xe9ff, 0xc02c, 0x21, 0 + .dw 0xea40, 0xc02c, 0xea7f, 0xc02c, 0x21, 0 + .dw 0xeac0, 0xc02c, 0xeaff, 0xc02c, 0x21, 0 + .dw 0xeb40, 0xc02c, 0xeb7f, 0xc02c, 0x21, 0 + .dw 0xebc0, 0xc02c, 0xebff, 0xc02c, 0x21, 0 + .dw 0xec40, 0xc02c, 0xec7f, 0xc02c, 0x21, 0 + .dw 0xecc0, 0xc02c, 0xecff, 0xc02c, 0x21, 0 + .dw 0xed40, 0xc02c, 0xed7f, 0xc02c, 0x21, 0 + .dw 0xedc0, 0xc02c, 0xedff, 0xc02c, 0x21, 0 + .dw 0xee40, 0xc02c, 0xee7f, 0xc02c, 0x21, 0 + .dw 0xeec0, 0xc02c, 0xeeff, 0xc02c, 0x21, 0 + .dw 0xef40, 0xc02c, 0xef7f, 0xc02c, 0x21, 0 + .dw 0xefc0, 0xc02c, 0xefff, 0xc02c, 0x21, 0 + .dw 0xf040, 0xc02c, 0xf07f, 0xc02c, 0x21, 0 + .dw 0xf0c0, 0xc02c, 0xf0ff, 0xc02c, 0x21, 0 + .dw 0xf140, 0xc02c, 0xf17f, 0xc02c, 0x21, 0 + .dw 0xf1c0, 0xc02c, 0xf1ff, 0xc02c, 0x21, 0 + .dw 0xf240, 0xc02c, 0xf27f, 0xc02c, 0x21, 0 + .dw 0xf2c0, 0xc02c, 0xf2ff, 0xc02c, 0x21, 0 + .dw 0xf340, 0xc02c, 0xf37f, 0xc02c, 0x21, 0 + .dw 0xf3c0, 0xc02c, 0xf3ff, 0xc02c, 0x21, 0 + .dw 0xf440, 0xc02c, 0xf47f, 0xc02c, 0x21, 0 + .dw 0xf4c0, 0xc02c, 0xf4ff, 0xc02c, 0x21, 0 + .dw 0xf540, 0xc02c, 0xf57f, 0xc02c, 0x21, 0 + .dw 0xf5c0, 0xc02c, 0xf5ff, 0xc02c, 0x21, 0 + .dw 0xf640, 0xc02c, 0xf67f, 0xc02c, 0x21, 0 + .dw 0xf6c0, 0xc02c, 0xf6ff, 0xc02c, 0x21, 0 + .dw 0xf740, 0xc02c, 0xf77f, 0xc02c, 0x21, 0 + .dw 0xf7c0, 0xc02c, 0xf7ff, 0xc02c, 0x21, 0 + .dw 0xf840, 0xc02c, 0xf87f, 0xc02c, 0x21, 0 + .dw 0xf8c0, 0xc02c, 0xf8ff, 0xc02c, 0x21, 0 + .dw 0xf940, 0xc02c, 0xf97f, 0xc02c, 0x21, 0 + .dw 0xf9c0, 0xc02c, 0xffff, 0xc02c, 0x21, 0 + .dw 0x0040, 0xc02d, 0x007f, 0xc02d, 0x21, 0 + .dw 0x00c0, 0xc02d, 0x00ff, 0xc02d, 0x21, 0 + .dw 0x0140, 0xc02d, 0x017f, 0xc02d, 0x21, 0 + .dw 0x01c0, 0xc02d, 0x01ff, 0xc02d, 0x21, 0 + .dw 0x0240, 0xc02d, 0x027f, 0xc02d, 0x21, 0 + .dw 0x02c0, 0xc02d, 0x02ff, 0xc02d, 0x21, 0 + .dw 0x0340, 0xc02d, 0x037f, 0xc02d, 0x21, 0 + .dw 0x03c0, 0xc02d, 0x03ff, 0xc02d, 0x21, 0 + .dw 0x0440, 0xc02d, 0x047f, 0xc02d, 0x21, 0 + .dw 0x04c0, 0xc02d, 0x04ff, 0xc02d, 0x21, 0 + .dw 0x0540, 0xc02d, 0x057f, 0xc02d, 0x21, 0 + .dw 0x05c0, 0xc02d, 0x05ff, 0xc02d, 0x21, 0 + .dw 0x0640, 0xc02d, 0x067f, 0xc02d, 0x21, 0 + .dw 0x06c0, 0xc02d, 0x06ff, 0xc02d, 0x21, 0 + .dw 0x0740, 0xc02d, 0x077f, 0xc02d, 0x21, 0 + .dw 0x07c0, 0xc02d, 0x07ff, 0xc02d, 0x21, 0 + .dw 0x0840, 0xc02d, 0x087f, 0xc02d, 0x21, 0 + .dw 0x08c0, 0xc02d, 0x08ff, 0xc02d, 0x21, 0 + .dw 0x0940, 0xc02d, 0x097f, 0xc02d, 0x21, 0 + .dw 0x09c0, 0xc02d, 0x09ff, 0xc02d, 0x21, 0 + .dw 0x0a40, 0xc02d, 0x0a7f, 0xc02d, 0x21, 0 + .dw 0x0ac0, 0xc02d, 0x0aff, 0xc02d, 0x21, 0 + .dw 0x0b40, 0xc02d, 0x0b7f, 0xc02d, 0x21, 0 + .dw 0x0bc0, 0xc02d, 0x0bff, 0xc02d, 0x21, 0 + .dw 0x0c40, 0xc02d, 0x0c7f, 0xc02d, 0x21, 0 + .dw 0x0cc0, 0xc02d, 0x0cff, 0xc02d, 0x21, 0 + .dw 0x0d40, 0xc02d, 0x0d7f, 0xc02d, 0x21, 0 + .dw 0x0dc0, 0xc02d, 0x0dff, 0xc02d, 0x21, 0 + .dw 0x0e40, 0xc02d, 0x0e7f, 0xc02d, 0x21, 0 + .dw 0x0ec0, 0xc02d, 0x0eff, 0xc02d, 0x21, 0 + .dw 0x0f40, 0xc02d, 0x0f7f, 0xc02d, 0x21, 0 + .dw 0x0fc0, 0xc02d, 0x0fff, 0xc02d, 0x21, 0 + .dw 0x1040, 0xc02d, 0x107f, 0xc02d, 0x21, 0 + .dw 0x10c0, 0xc02d, 0x10ff, 0xc02d, 0x21, 0 + .dw 0x1140, 0xc02d, 0x117f, 0xc02d, 0x21, 0 + .dw 0x11c0, 0xc02d, 0x11ff, 0xc02d, 0x21, 0 + .dw 0x1240, 0xc02d, 0x127f, 0xc02d, 0x21, 0 + .dw 0x12c0, 0xc02d, 0x12ff, 0xc02d, 0x21, 0 + .dw 0x1340, 0xc02d, 0x137f, 0xc02d, 0x21, 0 + .dw 0x13c0, 0xc02d, 0x13ff, 0xc02d, 0x21, 0 + .dw 0x1440, 0xc02d, 0x147f, 0xc02d, 0x21, 0 + .dw 0x14c0, 0xc02d, 0x14ff, 0xc02d, 0x21, 0 + .dw 0x1540, 0xc02d, 0x157f, 0xc02d, 0x21, 0 + .dw 0x15c0, 0xc02d, 0x15ff, 0xc02d, 0x21, 0 + .dw 0x1640, 0xc02d, 0x167f, 0xc02d, 0x21, 0 + .dw 0x16c0, 0xc02d, 0x16ff, 0xc02d, 0x21, 0 + .dw 0x1740, 0xc02d, 0x177f, 0xc02d, 0x21, 0 + .dw 0x17c0, 0xc02d, 0x17ff, 0xc02d, 0x21, 0 + .dw 0x1840, 0xc02d, 0x187f, 0xc02d, 0x21, 0 + .dw 0x18c0, 0xc02d, 0x18ff, 0xc02d, 0x21, 0 + .dw 0x1940, 0xc02d, 0x197f, 0xc02d, 0x21, 0 + .dw 0x19c0, 0xc02d, 0x1fff, 0xc02d, 0x21, 0 + .dw 0x2040, 0xc02d, 0x207f, 0xc02d, 0x21, 0 + .dw 0x20c0, 0xc02d, 0x20ff, 0xc02d, 0x21, 0 + .dw 0x2140, 0xc02d, 0x217f, 0xc02d, 0x21, 0 + .dw 0x21c0, 0xc02d, 0x21ff, 0xc02d, 0x21, 0 + .dw 0x2240, 0xc02d, 0x227f, 0xc02d, 0x21, 0 + .dw 0x22c0, 0xc02d, 0x22ff, 0xc02d, 0x21, 0 + .dw 0x2340, 0xc02d, 0x237f, 0xc02d, 0x21, 0 + .dw 0x23c0, 0xc02d, 0x23ff, 0xc02d, 0x21, 0 + .dw 0x2440, 0xc02d, 0x247f, 0xc02d, 0x21, 0 + .dw 0x24c0, 0xc02d, 0x24ff, 0xc02d, 0x21, 0 + .dw 0x2540, 0xc02d, 0x257f, 0xc02d, 0x21, 0 + .dw 0x25c0, 0xc02d, 0x25ff, 0xc02d, 0x21, 0 + .dw 0x2640, 0xc02d, 0x267f, 0xc02d, 0x21, 0 + .dw 0x26c0, 0xc02d, 0x26ff, 0xc02d, 0x21, 0 + .dw 0x2740, 0xc02d, 0x277f, 0xc02d, 0x21, 0 + .dw 0x27c0, 0xc02d, 0x27ff, 0xc02d, 0x21, 0 + .dw 0x2840, 0xc02d, 0x287f, 0xc02d, 0x21, 0 + .dw 0x28c0, 0xc02d, 0x28ff, 0xc02d, 0x21, 0 + .dw 0x2940, 0xc02d, 0x297f, 0xc02d, 0x21, 0 + .dw 0x29c0, 0xc02d, 0x29ff, 0xc02d, 0x21, 0 + .dw 0x2a40, 0xc02d, 0x2a7f, 0xc02d, 0x21, 0 + .dw 0x2ac0, 0xc02d, 0x2aff, 0xc02d, 0x21, 0 + .dw 0x2b40, 0xc02d, 0x2b7f, 0xc02d, 0x21, 0 + .dw 0x2bc0, 0xc02d, 0x2bff, 0xc02d, 0x21, 0 + .dw 0x2c40, 0xc02d, 0x2c7f, 0xc02d, 0x21, 0 + .dw 0x2cc0, 0xc02d, 0x2cff, 0xc02d, 0x21, 0 + .dw 0x2d40, 0xc02d, 0x2d7f, 0xc02d, 0x21, 0 + .dw 0x2dc0, 0xc02d, 0x2dff, 0xc02d, 0x21, 0 + .dw 0x2e40, 0xc02d, 0x2e7f, 0xc02d, 0x21, 0 + .dw 0x2ec0, 0xc02d, 0x2eff, 0xc02d, 0x21, 0 + .dw 0x2f40, 0xc02d, 0x2f7f, 0xc02d, 0x21, 0 + .dw 0x2fc0, 0xc02d, 0x2fff, 0xc02d, 0x21, 0 + .dw 0x3040, 0xc02d, 0x307f, 0xc02d, 0x21, 0 + .dw 0x30c0, 0xc02d, 0x30ff, 0xc02d, 0x21, 0 + .dw 0x3140, 0xc02d, 0x317f, 0xc02d, 0x21, 0 + .dw 0x31c0, 0xc02d, 0x31ff, 0xc02d, 0x21, 0 + .dw 0x3240, 0xc02d, 0x327f, 0xc02d, 0x21, 0 + .dw 0x32c0, 0xc02d, 0x32ff, 0xc02d, 0x21, 0 + .dw 0x3340, 0xc02d, 0x337f, 0xc02d, 0x21, 0 + .dw 0x33c0, 0xc02d, 0x33ff, 0xc02d, 0x21, 0 + .dw 0x3440, 0xc02d, 0x347f, 0xc02d, 0x21, 0 + .dw 0x34c0, 0xc02d, 0x34ff, 0xc02d, 0x21, 0 + .dw 0x3540, 0xc02d, 0x357f, 0xc02d, 0x21, 0 + .dw 0x35c0, 0xc02d, 0x35ff, 0xc02d, 0x21, 0 + .dw 0x3640, 0xc02d, 0x367f, 0xc02d, 0x21, 0 + .dw 0x36c0, 0xc02d, 0x36ff, 0xc02d, 0x21, 0 + .dw 0x3740, 0xc02d, 0x377f, 0xc02d, 0x21, 0 + .dw 0x37c0, 0xc02d, 0x37ff, 0xc02d, 0x21, 0 + .dw 0x3840, 0xc02d, 0x387f, 0xc02d, 0x21, 0 + .dw 0x38c0, 0xc02d, 0x38ff, 0xc02d, 0x21, 0 + .dw 0x3940, 0xc02d, 0x397f, 0xc02d, 0x21, 0 + .dw 0x39c0, 0xc02d, 0x3fff, 0xc02d, 0x21, 0 + .dw 0x4040, 0xc02d, 0x407f, 0xc02d, 0x21, 0 + .dw 0x40c0, 0xc02d, 0x40ff, 0xc02d, 0x21, 0 + .dw 0x4140, 0xc02d, 0x417f, 0xc02d, 0x21, 0 + .dw 0x41c0, 0xc02d, 0x41ff, 0xc02d, 0x21, 0 + .dw 0x4240, 0xc02d, 0x427f, 0xc02d, 0x21, 0 + .dw 0x42c0, 0xc02d, 0x42ff, 0xc02d, 0x21, 0 + .dw 0x4340, 0xc02d, 0x437f, 0xc02d, 0x21, 0 + .dw 0x43c0, 0xc02d, 0x43ff, 0xc02d, 0x21, 0 + .dw 0x4440, 0xc02d, 0x447f, 0xc02d, 0x21, 0 + .dw 0x44c0, 0xc02d, 0x44ff, 0xc02d, 0x21, 0 + .dw 0x4540, 0xc02d, 0x457f, 0xc02d, 0x21, 0 + .dw 0x45c0, 0xc02d, 0x45ff, 0xc02d, 0x21, 0 + .dw 0x4640, 0xc02d, 0x467f, 0xc02d, 0x21, 0 + .dw 0x46c0, 0xc02d, 0x46ff, 0xc02d, 0x21, 0 + .dw 0x4740, 0xc02d, 0x477f, 0xc02d, 0x21, 0 + .dw 0x47c0, 0xc02d, 0x47ff, 0xc02d, 0x21, 0 + .dw 0x4840, 0xc02d, 0x487f, 0xc02d, 0x21, 0 + .dw 0x48c0, 0xc02d, 0x48ff, 0xc02d, 0x21, 0 + .dw 0x4940, 0xc02d, 0x497f, 0xc02d, 0x21, 0 + .dw 0x49c0, 0xc02d, 0x49ff, 0xc02d, 0x21, 0 + .dw 0x4a40, 0xc02d, 0x4a7f, 0xc02d, 0x21, 0 + .dw 0x4ac0, 0xc02d, 0x4aff, 0xc02d, 0x21, 0 + .dw 0x4b40, 0xc02d, 0x4b7f, 0xc02d, 0x21, 0 + .dw 0x4bc0, 0xc02d, 0x4bff, 0xc02d, 0x21, 0 + .dw 0x4c40, 0xc02d, 0x4c7f, 0xc02d, 0x21, 0 + .dw 0x4cc0, 0xc02d, 0x4cff, 0xc02d, 0x21, 0 + .dw 0x4d40, 0xc02d, 0x4d7f, 0xc02d, 0x21, 0 + .dw 0x4dc0, 0xc02d, 0x4dff, 0xc02d, 0x21, 0 + .dw 0x4e40, 0xc02d, 0x4e7f, 0xc02d, 0x21, 0 + .dw 0x4ec0, 0xc02d, 0x4eff, 0xc02d, 0x21, 0 + .dw 0x4f40, 0xc02d, 0x4f7f, 0xc02d, 0x21, 0 + .dw 0x4fc0, 0xc02d, 0x4fff, 0xc02d, 0x21, 0 + .dw 0x5040, 0xc02d, 0x507f, 0xc02d, 0x21, 0 + .dw 0x50c0, 0xc02d, 0x50ff, 0xc02d, 0x21, 0 + .dw 0x5140, 0xc02d, 0x517f, 0xc02d, 0x21, 0 + .dw 0x51c0, 0xc02d, 0x51ff, 0xc02d, 0x21, 0 + .dw 0x5240, 0xc02d, 0x527f, 0xc02d, 0x21, 0 + .dw 0x52c0, 0xc02d, 0x52ff, 0xc02d, 0x21, 0 + .dw 0x5340, 0xc02d, 0x537f, 0xc02d, 0x21, 0 + .dw 0x53c0, 0xc02d, 0x53ff, 0xc02d, 0x21, 0 + .dw 0x5440, 0xc02d, 0x547f, 0xc02d, 0x21, 0 + .dw 0x54c0, 0xc02d, 0x54ff, 0xc02d, 0x21, 0 + .dw 0x5540, 0xc02d, 0x557f, 0xc02d, 0x21, 0 + .dw 0x55c0, 0xc02d, 0x55ff, 0xc02d, 0x21, 0 + .dw 0x5640, 0xc02d, 0x567f, 0xc02d, 0x21, 0 + .dw 0x56c0, 0xc02d, 0x56ff, 0xc02d, 0x21, 0 + .dw 0x5740, 0xc02d, 0x577f, 0xc02d, 0x21, 0 + .dw 0x57c0, 0xc02d, 0x57ff, 0xc02d, 0x21, 0 + .dw 0x5840, 0xc02d, 0x587f, 0xc02d, 0x21, 0 + .dw 0x58c0, 0xc02d, 0x58ff, 0xc02d, 0x21, 0 + .dw 0x5940, 0xc02d, 0x597f, 0xc02d, 0x21, 0 + .dw 0x59c0, 0xc02d, 0x5fff, 0xc02d, 0x21, 0 + .dw 0x6040, 0xc02d, 0x607f, 0xc02d, 0x21, 0 + .dw 0x60c0, 0xc02d, 0x60ff, 0xc02d, 0x21, 0 + .dw 0x6140, 0xc02d, 0x617f, 0xc02d, 0x21, 0 + .dw 0x61c0, 0xc02d, 0x61ff, 0xc02d, 0x21, 0 + .dw 0x6240, 0xc02d, 0x627f, 0xc02d, 0x21, 0 + .dw 0x62c0, 0xc02d, 0x62ff, 0xc02d, 0x21, 0 + .dw 0x6340, 0xc02d, 0x637f, 0xc02d, 0x21, 0 + .dw 0x63c0, 0xc02d, 0x63ff, 0xc02d, 0x21, 0 + .dw 0x6440, 0xc02d, 0x647f, 0xc02d, 0x21, 0 + .dw 0x64c0, 0xc02d, 0x64ff, 0xc02d, 0x21, 0 + .dw 0x6540, 0xc02d, 0x657f, 0xc02d, 0x21, 0 + .dw 0x65c0, 0xc02d, 0x65ff, 0xc02d, 0x21, 0 + .dw 0x6640, 0xc02d, 0x667f, 0xc02d, 0x21, 0 + .dw 0x66c0, 0xc02d, 0x66ff, 0xc02d, 0x21, 0 + .dw 0x6740, 0xc02d, 0x677f, 0xc02d, 0x21, 0 + .dw 0x67c0, 0xc02d, 0x67ff, 0xc02d, 0x21, 0 + .dw 0x6840, 0xc02d, 0x687f, 0xc02d, 0x21, 0 + .dw 0x68c0, 0xc02d, 0x68ff, 0xc02d, 0x21, 0 + .dw 0x6940, 0xc02d, 0x697f, 0xc02d, 0x21, 0 + .dw 0x69c0, 0xc02d, 0x69ff, 0xc02d, 0x21, 0 + .dw 0x6a40, 0xc02d, 0x6a7f, 0xc02d, 0x21, 0 + .dw 0x6ac0, 0xc02d, 0x6aff, 0xc02d, 0x21, 0 + .dw 0x6b40, 0xc02d, 0x6b7f, 0xc02d, 0x21, 0 + .dw 0x6bc0, 0xc02d, 0x6bff, 0xc02d, 0x21, 0 + .dw 0x6c40, 0xc02d, 0x6c7f, 0xc02d, 0x21, 0 + .dw 0x6cc0, 0xc02d, 0x6cff, 0xc02d, 0x21, 0 + .dw 0x6d40, 0xc02d, 0x6d7f, 0xc02d, 0x21, 0 + .dw 0x6dc0, 0xc02d, 0x6dff, 0xc02d, 0x21, 0 + .dw 0x6e40, 0xc02d, 0x6e7f, 0xc02d, 0x21, 0 + .dw 0x6ec0, 0xc02d, 0x6eff, 0xc02d, 0x21, 0 + .dw 0x6f40, 0xc02d, 0x6f7f, 0xc02d, 0x21, 0 + .dw 0x6fc0, 0xc02d, 0x6fff, 0xc02d, 0x21, 0 + .dw 0x7040, 0xc02d, 0x707f, 0xc02d, 0x21, 0 + .dw 0x70c0, 0xc02d, 0x70ff, 0xc02d, 0x21, 0 + .dw 0x7140, 0xc02d, 0x717f, 0xc02d, 0x21, 0 + .dw 0x71c0, 0xc02d, 0x71ff, 0xc02d, 0x21, 0 + .dw 0x7240, 0xc02d, 0x727f, 0xc02d, 0x21, 0 + .dw 0x72c0, 0xc02d, 0x72ff, 0xc02d, 0x21, 0 + .dw 0x7340, 0xc02d, 0x737f, 0xc02d, 0x21, 0 + .dw 0x73c0, 0xc02d, 0x73ff, 0xc02d, 0x21, 0 + .dw 0x7440, 0xc02d, 0x747f, 0xc02d, 0x21, 0 + .dw 0x74c0, 0xc02d, 0x74ff, 0xc02d, 0x21, 0 + .dw 0x7540, 0xc02d, 0x757f, 0xc02d, 0x21, 0 + .dw 0x75c0, 0xc02d, 0x75ff, 0xc02d, 0x21, 0 + .dw 0x7640, 0xc02d, 0x767f, 0xc02d, 0x21, 0 + .dw 0x76c0, 0xc02d, 0x76ff, 0xc02d, 0x21, 0 + .dw 0x7740, 0xc02d, 0x777f, 0xc02d, 0x21, 0 + .dw 0x77c0, 0xc02d, 0x77ff, 0xc02d, 0x21, 0 + .dw 0x7840, 0xc02d, 0x787f, 0xc02d, 0x21, 0 + .dw 0x78c0, 0xc02d, 0x78ff, 0xc02d, 0x21, 0 + .dw 0x7940, 0xc02d, 0x797f, 0xc02d, 0x21, 0 + .dw 0x79c0, 0xc02d, 0x7fff, 0xc02d, 0x21, 0 + .dw 0x8040, 0xc02d, 0x807f, 0xc02d, 0x21, 0 + .dw 0x80c0, 0xc02d, 0x80ff, 0xc02d, 0x21, 0 + .dw 0x8140, 0xc02d, 0x817f, 0xc02d, 0x21, 0 + .dw 0x81c0, 0xc02d, 0x81ff, 0xc02d, 0x21, 0 + .dw 0x8240, 0xc02d, 0x827f, 0xc02d, 0x21, 0 + .dw 0x82c0, 0xc02d, 0x82ff, 0xc02d, 0x21, 0 + .dw 0x8340, 0xc02d, 0x837f, 0xc02d, 0x21, 0 + .dw 0x83c0, 0xc02d, 0x83ff, 0xc02d, 0x21, 0 + .dw 0x8440, 0xc02d, 0x847f, 0xc02d, 0x21, 0 + .dw 0x84c0, 0xc02d, 0x84ff, 0xc02d, 0x21, 0 + .dw 0x8540, 0xc02d, 0x857f, 0xc02d, 0x21, 0 + .dw 0x85c0, 0xc02d, 0x85ff, 0xc02d, 0x21, 0 + .dw 0x8640, 0xc02d, 0x867f, 0xc02d, 0x21, 0 + .dw 0x86c0, 0xc02d, 0x86ff, 0xc02d, 0x21, 0 + .dw 0x8740, 0xc02d, 0x877f, 0xc02d, 0x21, 0 + .dw 0x87c0, 0xc02d, 0x87ff, 0xc02d, 0x21, 0 + .dw 0x8840, 0xc02d, 0x887f, 0xc02d, 0x21, 0 + .dw 0x88c0, 0xc02d, 0x88ff, 0xc02d, 0x21, 0 + .dw 0x8940, 0xc02d, 0x897f, 0xc02d, 0x21, 0 + .dw 0x89c0, 0xc02d, 0x89ff, 0xc02d, 0x21, 0 + .dw 0x8a40, 0xc02d, 0x8a7f, 0xc02d, 0x21, 0 + .dw 0x8ac0, 0xc02d, 0x8aff, 0xc02d, 0x21, 0 + .dw 0x8b40, 0xc02d, 0x8b7f, 0xc02d, 0x21, 0 + .dw 0x8bc0, 0xc02d, 0x8bff, 0xc02d, 0x21, 0 + .dw 0x8c40, 0xc02d, 0x8c7f, 0xc02d, 0x21, 0 + .dw 0x8cc0, 0xc02d, 0x8cff, 0xc02d, 0x21, 0 + .dw 0x8d40, 0xc02d, 0x8d7f, 0xc02d, 0x21, 0 + .dw 0x8dc0, 0xc02d, 0x8dff, 0xc02d, 0x21, 0 + .dw 0x8e40, 0xc02d, 0x8e7f, 0xc02d, 0x21, 0 + .dw 0x8ec0, 0xc02d, 0x8eff, 0xc02d, 0x21, 0 + .dw 0x8f40, 0xc02d, 0x8f7f, 0xc02d, 0x21, 0 + .dw 0x8fc0, 0xc02d, 0x8fff, 0xc02d, 0x21, 0 + .dw 0x9040, 0xc02d, 0x907f, 0xc02d, 0x21, 0 + .dw 0x90c0, 0xc02d, 0x90ff, 0xc02d, 0x21, 0 + .dw 0x9140, 0xc02d, 0x917f, 0xc02d, 0x21, 0 + .dw 0x91c0, 0xc02d, 0x91ff, 0xc02d, 0x21, 0 + .dw 0x9240, 0xc02d, 0x927f, 0xc02d, 0x21, 0 + .dw 0x92c0, 0xc02d, 0x92ff, 0xc02d, 0x21, 0 + .dw 0x9340, 0xc02d, 0x937f, 0xc02d, 0x21, 0 + .dw 0x93c0, 0xc02d, 0x93ff, 0xc02d, 0x21, 0 + .dw 0x9440, 0xc02d, 0x947f, 0xc02d, 0x21, 0 + .dw 0x94c0, 0xc02d, 0x94ff, 0xc02d, 0x21, 0 + .dw 0x9540, 0xc02d, 0x957f, 0xc02d, 0x21, 0 + .dw 0x95c0, 0xc02d, 0x95ff, 0xc02d, 0x21, 0 + .dw 0x9640, 0xc02d, 0x967f, 0xc02d, 0x21, 0 + .dw 0x96c0, 0xc02d, 0x96ff, 0xc02d, 0x21, 0 + .dw 0x9740, 0xc02d, 0x977f, 0xc02d, 0x21, 0 + .dw 0x97c0, 0xc02d, 0x97ff, 0xc02d, 0x21, 0 + .dw 0x9840, 0xc02d, 0x987f, 0xc02d, 0x21, 0 + .dw 0x98c0, 0xc02d, 0x98ff, 0xc02d, 0x21, 0 + .dw 0x9940, 0xc02d, 0x997f, 0xc02d, 0x21, 0 + .dw 0x99c0, 0xc02d, 0x9fff, 0xc02d, 0x21, 0 + .dw 0xa040, 0xc02d, 0xa07f, 0xc02d, 0x21, 0 + .dw 0xa0c0, 0xc02d, 0xa0ff, 0xc02d, 0x21, 0 + .dw 0xa140, 0xc02d, 0xa17f, 0xc02d, 0x21, 0 + .dw 0xa1c0, 0xc02d, 0xa1ff, 0xc02d, 0x21, 0 + .dw 0xa240, 0xc02d, 0xa27f, 0xc02d, 0x21, 0 + .dw 0xa2c0, 0xc02d, 0xa2ff, 0xc02d, 0x21, 0 + .dw 0xa340, 0xc02d, 0xa37f, 0xc02d, 0x21, 0 + .dw 0xa3c0, 0xc02d, 0xa3ff, 0xc02d, 0x21, 0 + .dw 0xa440, 0xc02d, 0xa47f, 0xc02d, 0x21, 0 + .dw 0xa4c0, 0xc02d, 0xa4ff, 0xc02d, 0x21, 0 + .dw 0xa540, 0xc02d, 0xa57f, 0xc02d, 0x21, 0 + .dw 0xa5c0, 0xc02d, 0xa5ff, 0xc02d, 0x21, 0 + .dw 0xa640, 0xc02d, 0xa67f, 0xc02d, 0x21, 0 + .dw 0xa6c0, 0xc02d, 0xa6ff, 0xc02d, 0x21, 0 + .dw 0xa740, 0xc02d, 0xa77f, 0xc02d, 0x21, 0 + .dw 0xa7c0, 0xc02d, 0xa7ff, 0xc02d, 0x21, 0 + .dw 0xa840, 0xc02d, 0xa87f, 0xc02d, 0x21, 0 + .dw 0xa8c0, 0xc02d, 0xa8ff, 0xc02d, 0x21, 0 + .dw 0xa940, 0xc02d, 0xa97f, 0xc02d, 0x21, 0 + .dw 0xa9c0, 0xc02d, 0xa9ff, 0xc02d, 0x21, 0 + .dw 0xaa40, 0xc02d, 0xaa7f, 0xc02d, 0x21, 0 + .dw 0xaac0, 0xc02d, 0xaaff, 0xc02d, 0x21, 0 + .dw 0xab40, 0xc02d, 0xab7f, 0xc02d, 0x21, 0 + .dw 0xabc0, 0xc02d, 0xabff, 0xc02d, 0x21, 0 + .dw 0xac40, 0xc02d, 0xac7f, 0xc02d, 0x21, 0 + .dw 0xacc0, 0xc02d, 0xacff, 0xc02d, 0x21, 0 + .dw 0xad40, 0xc02d, 0xad7f, 0xc02d, 0x21, 0 + .dw 0xadc0, 0xc02d, 0xadff, 0xc02d, 0x21, 0 + .dw 0xae40, 0xc02d, 0xae7f, 0xc02d, 0x21, 0 + .dw 0xaec0, 0xc02d, 0xaeff, 0xc02d, 0x21, 0 + .dw 0xaf40, 0xc02d, 0xaf7f, 0xc02d, 0x21, 0 + .dw 0xafc0, 0xc02d, 0xafff, 0xc02d, 0x21, 0 + .dw 0xb040, 0xc02d, 0xb07f, 0xc02d, 0x21, 0 + .dw 0xb0c0, 0xc02d, 0xb0ff, 0xc02d, 0x21, 0 + .dw 0xb140, 0xc02d, 0xb17f, 0xc02d, 0x21, 0 + .dw 0xb1c0, 0xc02d, 0xb1ff, 0xc02d, 0x21, 0 + .dw 0xb240, 0xc02d, 0xb27f, 0xc02d, 0x21, 0 + .dw 0xb2c0, 0xc02d, 0xb2ff, 0xc02d, 0x21, 0 + .dw 0xb340, 0xc02d, 0xb37f, 0xc02d, 0x21, 0 + .dw 0xb3c0, 0xc02d, 0xb3ff, 0xc02d, 0x21, 0 + .dw 0xb440, 0xc02d, 0xb47f, 0xc02d, 0x21, 0 + .dw 0xb4c0, 0xc02d, 0xb4ff, 0xc02d, 0x21, 0 + .dw 0xb540, 0xc02d, 0xb57f, 0xc02d, 0x21, 0 + .dw 0xb5c0, 0xc02d, 0xb5ff, 0xc02d, 0x21, 0 + .dw 0xb640, 0xc02d, 0xb67f, 0xc02d, 0x21, 0 + .dw 0xb6c0, 0xc02d, 0xb6ff, 0xc02d, 0x21, 0 + .dw 0xb740, 0xc02d, 0xb77f, 0xc02d, 0x21, 0 + .dw 0xb7c0, 0xc02d, 0xb7ff, 0xc02d, 0x21, 0 + .dw 0xb840, 0xc02d, 0xb87f, 0xc02d, 0x21, 0 + .dw 0xb8c0, 0xc02d, 0xb8ff, 0xc02d, 0x21, 0 + .dw 0xb940, 0xc02d, 0xb97f, 0xc02d, 0x21, 0 + .dw 0xb9c0, 0xc02d, 0xbfff, 0xc02d, 0x21, 0 + .dw 0xc040, 0xc02d, 0xc07f, 0xc02d, 0x21, 0 + .dw 0xc0c0, 0xc02d, 0xc0ff, 0xc02d, 0x21, 0 + .dw 0xc140, 0xc02d, 0xc17f, 0xc02d, 0x21, 0 + .dw 0xc1c0, 0xc02d, 0xc1ff, 0xc02d, 0x21, 0 + .dw 0xc240, 0xc02d, 0xc27f, 0xc02d, 0x21, 0 + .dw 0xc2c0, 0xc02d, 0xc2ff, 0xc02d, 0x21, 0 + .dw 0xc340, 0xc02d, 0xc37f, 0xc02d, 0x21, 0 + .dw 0xc3c0, 0xc02d, 0xc3ff, 0xc02d, 0x21, 0 + .dw 0xc440, 0xc02d, 0xc47f, 0xc02d, 0x21, 0 + .dw 0xc4c0, 0xc02d, 0xc4ff, 0xc02d, 0x21, 0 + .dw 0xc540, 0xc02d, 0xc57f, 0xc02d, 0x21, 0 + .dw 0xc5c0, 0xc02d, 0xc5ff, 0xc02d, 0x21, 0 + .dw 0xc640, 0xc02d, 0xc67f, 0xc02d, 0x21, 0 + .dw 0xc6c0, 0xc02d, 0xc6ff, 0xc02d, 0x21, 0 + .dw 0xc740, 0xc02d, 0xc77f, 0xc02d, 0x21, 0 + .dw 0xc7c0, 0xc02d, 0xc7ff, 0xc02d, 0x21, 0 + .dw 0xc840, 0xc02d, 0xc87f, 0xc02d, 0x21, 0 + .dw 0xc8c0, 0xc02d, 0xc8ff, 0xc02d, 0x21, 0 + .dw 0xc940, 0xc02d, 0xc97f, 0xc02d, 0x21, 0 + .dw 0xc9c0, 0xc02d, 0xc9ff, 0xc02d, 0x21, 0 + .dw 0xca40, 0xc02d, 0xca7f, 0xc02d, 0x21, 0 + .dw 0xcac0, 0xc02d, 0xcaff, 0xc02d, 0x21, 0 + .dw 0xcb40, 0xc02d, 0xcb7f, 0xc02d, 0x21, 0 + .dw 0xcbc0, 0xc02d, 0xcbff, 0xc02d, 0x21, 0 + .dw 0xcc40, 0xc02d, 0xcc7f, 0xc02d, 0x21, 0 + .dw 0xccc0, 0xc02d, 0xccff, 0xc02d, 0x21, 0 + .dw 0xcd40, 0xc02d, 0xcd7f, 0xc02d, 0x21, 0 + .dw 0xcdc0, 0xc02d, 0xcdff, 0xc02d, 0x21, 0 + .dw 0xce40, 0xc02d, 0xce7f, 0xc02d, 0x21, 0 + .dw 0xcec0, 0xc02d, 0xceff, 0xc02d, 0x21, 0 + .dw 0xcf40, 0xc02d, 0xcf7f, 0xc02d, 0x21, 0 + .dw 0xcfc0, 0xc02d, 0xcfff, 0xc02d, 0x21, 0 + .dw 0xd040, 0xc02d, 0xd07f, 0xc02d, 0x21, 0 + .dw 0xd0c0, 0xc02d, 0xd0ff, 0xc02d, 0x21, 0 + .dw 0xd140, 0xc02d, 0xd17f, 0xc02d, 0x21, 0 + .dw 0xd1c0, 0xc02d, 0xd1ff, 0xc02d, 0x21, 0 + .dw 0xd240, 0xc02d, 0xd27f, 0xc02d, 0x21, 0 + .dw 0xd2c0, 0xc02d, 0xd2ff, 0xc02d, 0x21, 0 + .dw 0xd340, 0xc02d, 0xd37f, 0xc02d, 0x21, 0 + .dw 0xd3c0, 0xc02d, 0xd3ff, 0xc02d, 0x21, 0 + .dw 0xd440, 0xc02d, 0xd47f, 0xc02d, 0x21, 0 + .dw 0xd4c0, 0xc02d, 0xd4ff, 0xc02d, 0x21, 0 + .dw 0xd540, 0xc02d, 0xd57f, 0xc02d, 0x21, 0 + .dw 0xd5c0, 0xc02d, 0xd5ff, 0xc02d, 0x21, 0 + .dw 0xd640, 0xc02d, 0xd67f, 0xc02d, 0x21, 0 + .dw 0xd6c0, 0xc02d, 0xd6ff, 0xc02d, 0x21, 0 + .dw 0xd740, 0xc02d, 0xd77f, 0xc02d, 0x21, 0 + .dw 0xd7c0, 0xc02d, 0xd7ff, 0xc02d, 0x21, 0 + .dw 0xd840, 0xc02d, 0xd87f, 0xc02d, 0x21, 0 + .dw 0xd8c0, 0xc02d, 0xd8ff, 0xc02d, 0x21, 0 + .dw 0xd940, 0xc02d, 0xd97f, 0xc02d, 0x21, 0 + .dw 0xd9c0, 0xc02d, 0xdfff, 0xc02d, 0x21, 0 + .dw 0xe040, 0xc02d, 0xe07f, 0xc02d, 0x21, 0 + .dw 0xe0c0, 0xc02d, 0xe0ff, 0xc02d, 0x21, 0 + .dw 0xe140, 0xc02d, 0xe17f, 0xc02d, 0x21, 0 + .dw 0xe1c0, 0xc02d, 0xe1ff, 0xc02d, 0x21, 0 + .dw 0xe240, 0xc02d, 0xe27f, 0xc02d, 0x21, 0 + .dw 0xe2c0, 0xc02d, 0xe2ff, 0xc02d, 0x21, 0 + .dw 0xe340, 0xc02d, 0xe37f, 0xc02d, 0x21, 0 + .dw 0xe3c0, 0xc02d, 0xe3ff, 0xc02d, 0x21, 0 + .dw 0xe440, 0xc02d, 0xe47f, 0xc02d, 0x21, 0 + .dw 0xe4c0, 0xc02d, 0xe4ff, 0xc02d, 0x21, 0 + .dw 0xe540, 0xc02d, 0xe57f, 0xc02d, 0x21, 0 + .dw 0xe5c0, 0xc02d, 0xe5ff, 0xc02d, 0x21, 0 + .dw 0xe640, 0xc02d, 0xe67f, 0xc02d, 0x21, 0 + .dw 0xe6c0, 0xc02d, 0xe6ff, 0xc02d, 0x21, 0 + .dw 0xe740, 0xc02d, 0xe77f, 0xc02d, 0x21, 0 + .dw 0xe7c0, 0xc02d, 0xe7ff, 0xc02d, 0x21, 0 + .dw 0xe840, 0xc02d, 0xe87f, 0xc02d, 0x21, 0 + .dw 0xe8c0, 0xc02d, 0xe8ff, 0xc02d, 0x21, 0 + .dw 0xe940, 0xc02d, 0xe97f, 0xc02d, 0x21, 0 + .dw 0xe9c0, 0xc02d, 0xe9ff, 0xc02d, 0x21, 0 + .dw 0xea40, 0xc02d, 0xea7f, 0xc02d, 0x21, 0 + .dw 0xeac0, 0xc02d, 0xeaff, 0xc02d, 0x21, 0 + .dw 0xeb40, 0xc02d, 0xeb7f, 0xc02d, 0x21, 0 + .dw 0xebc0, 0xc02d, 0xebff, 0xc02d, 0x21, 0 + .dw 0xec40, 0xc02d, 0xec7f, 0xc02d, 0x21, 0 + .dw 0xecc0, 0xc02d, 0xecff, 0xc02d, 0x21, 0 + .dw 0xed40, 0xc02d, 0xed7f, 0xc02d, 0x21, 0 + .dw 0xedc0, 0xc02d, 0xedff, 0xc02d, 0x21, 0 + .dw 0xee40, 0xc02d, 0xee7f, 0xc02d, 0x21, 0 + .dw 0xeec0, 0xc02d, 0xeeff, 0xc02d, 0x21, 0 + .dw 0xef40, 0xc02d, 0xef7f, 0xc02d, 0x21, 0 + .dw 0xefc0, 0xc02d, 0xefff, 0xc02d, 0x21, 0 + .dw 0xf040, 0xc02d, 0xf07f, 0xc02d, 0x21, 0 + .dw 0xf0c0, 0xc02d, 0xf0ff, 0xc02d, 0x21, 0 + .dw 0xf140, 0xc02d, 0xf17f, 0xc02d, 0x21, 0 + .dw 0xf1c0, 0xc02d, 0xf1ff, 0xc02d, 0x21, 0 + .dw 0xf240, 0xc02d, 0xf27f, 0xc02d, 0x21, 0 + .dw 0xf2c0, 0xc02d, 0xf2ff, 0xc02d, 0x21, 0 + .dw 0xf340, 0xc02d, 0xf37f, 0xc02d, 0x21, 0 + .dw 0xf3c0, 0xc02d, 0xf3ff, 0xc02d, 0x21, 0 + .dw 0xf440, 0xc02d, 0xf47f, 0xc02d, 0x21, 0 + .dw 0xf4c0, 0xc02d, 0xf4ff, 0xc02d, 0x21, 0 + .dw 0xf540, 0xc02d, 0xf57f, 0xc02d, 0x21, 0 + .dw 0xf5c0, 0xc02d, 0xf5ff, 0xc02d, 0x21, 0 + .dw 0xf640, 0xc02d, 0xf67f, 0xc02d, 0x21, 0 + .dw 0xf6c0, 0xc02d, 0xf6ff, 0xc02d, 0x21, 0 + .dw 0xf740, 0xc02d, 0xf77f, 0xc02d, 0x21, 0 + .dw 0xf7c0, 0xc02d, 0xf7ff, 0xc02d, 0x21, 0 + .dw 0xf840, 0xc02d, 0xf87f, 0xc02d, 0x21, 0 + .dw 0xf8c0, 0xc02d, 0xf8ff, 0xc02d, 0x21, 0 + .dw 0xf940, 0xc02d, 0xf97f, 0xc02d, 0x21, 0 + .dw 0xf9c0, 0xc02d, 0xffff, 0xc02d, 0x21, 0 + .dw 0x0040, 0xc02e, 0x007f, 0xc02e, 0x21, 0 + .dw 0x00c0, 0xc02e, 0x00ff, 0xc02e, 0x21, 0 + .dw 0x0140, 0xc02e, 0x017f, 0xc02e, 0x21, 0 + .dw 0x01c0, 0xc02e, 0x01ff, 0xc02e, 0x21, 0 + .dw 0x0240, 0xc02e, 0x027f, 0xc02e, 0x21, 0 + .dw 0x02c0, 0xc02e, 0x02ff, 0xc02e, 0x21, 0 + .dw 0x0340, 0xc02e, 0x037f, 0xc02e, 0x21, 0 + .dw 0x03c0, 0xc02e, 0x03ff, 0xc02e, 0x21, 0 + .dw 0x0440, 0xc02e, 0x047f, 0xc02e, 0x21, 0 + .dw 0x04c0, 0xc02e, 0x04ff, 0xc02e, 0x21, 0 + .dw 0x0540, 0xc02e, 0x057f, 0xc02e, 0x21, 0 + .dw 0x05c0, 0xc02e, 0x05ff, 0xc02e, 0x21, 0 + .dw 0x0640, 0xc02e, 0x067f, 0xc02e, 0x21, 0 + .dw 0x06c0, 0xc02e, 0x06ff, 0xc02e, 0x21, 0 + .dw 0x0740, 0xc02e, 0x077f, 0xc02e, 0x21, 0 + .dw 0x07c0, 0xc02e, 0x07ff, 0xc02e, 0x21, 0 + .dw 0x0840, 0xc02e, 0x087f, 0xc02e, 0x21, 0 + .dw 0x08c0, 0xc02e, 0x08ff, 0xc02e, 0x21, 0 + .dw 0x0940, 0xc02e, 0x097f, 0xc02e, 0x21, 0 + .dw 0x09c0, 0xc02e, 0x09ff, 0xc02e, 0x21, 0 + .dw 0x0a40, 0xc02e, 0x0a7f, 0xc02e, 0x21, 0 + .dw 0x0ac0, 0xc02e, 0x0aff, 0xc02e, 0x21, 0 + .dw 0x0b40, 0xc02e, 0x0b7f, 0xc02e, 0x21, 0 + .dw 0x0bc0, 0xc02e, 0x0bff, 0xc02e, 0x21, 0 + .dw 0x0c40, 0xc02e, 0x0c7f, 0xc02e, 0x21, 0 + .dw 0x0cc0, 0xc02e, 0x0cff, 0xc02e, 0x21, 0 + .dw 0x0d40, 0xc02e, 0x0d7f, 0xc02e, 0x21, 0 + .dw 0x0dc0, 0xc02e, 0x0dff, 0xc02e, 0x21, 0 + .dw 0x0e40, 0xc02e, 0x0e7f, 0xc02e, 0x21, 0 + .dw 0x0ec0, 0xc02e, 0x0eff, 0xc02e, 0x21, 0 + .dw 0x0f40, 0xc02e, 0x0f7f, 0xc02e, 0x21, 0 + .dw 0x0fc0, 0xc02e, 0x0fff, 0xc02e, 0x21, 0 + .dw 0x1040, 0xc02e, 0x107f, 0xc02e, 0x21, 0 + .dw 0x10c0, 0xc02e, 0x10ff, 0xc02e, 0x21, 0 + .dw 0x1140, 0xc02e, 0x117f, 0xc02e, 0x21, 0 + .dw 0x11c0, 0xc02e, 0x11ff, 0xc02e, 0x21, 0 + .dw 0x1240, 0xc02e, 0x127f, 0xc02e, 0x21, 0 + .dw 0x12c0, 0xc02e, 0x12ff, 0xc02e, 0x21, 0 + .dw 0x1340, 0xc02e, 0x137f, 0xc02e, 0x21, 0 + .dw 0x13c0, 0xc02e, 0x13ff, 0xc02e, 0x21, 0 + .dw 0x1440, 0xc02e, 0x147f, 0xc02e, 0x21, 0 + .dw 0x14c0, 0xc02e, 0x14ff, 0xc02e, 0x21, 0 + .dw 0x1540, 0xc02e, 0x157f, 0xc02e, 0x21, 0 + .dw 0x15c0, 0xc02e, 0x15ff, 0xc02e, 0x21, 0 + .dw 0x1640, 0xc02e, 0x167f, 0xc02e, 0x21, 0 + .dw 0x16c0, 0xc02e, 0x16ff, 0xc02e, 0x21, 0 + .dw 0x1740, 0xc02e, 0x177f, 0xc02e, 0x21, 0 + .dw 0x17c0, 0xc02e, 0x17ff, 0xc02e, 0x21, 0 + .dw 0x1840, 0xc02e, 0x187f, 0xc02e, 0x21, 0 + .dw 0x18c0, 0xc02e, 0x18ff, 0xc02e, 0x21, 0 + .dw 0x1940, 0xc02e, 0x197f, 0xc02e, 0x21, 0 + .dw 0x19c0, 0xc02e, 0x1fff, 0xc02e, 0x21, 0 + .dw 0x2040, 0xc02e, 0x207f, 0xc02e, 0x21, 0 + .dw 0x20c0, 0xc02e, 0x20ff, 0xc02e, 0x21, 0 + .dw 0x2140, 0xc02e, 0x217f, 0xc02e, 0x21, 0 + .dw 0x21c0, 0xc02e, 0x21ff, 0xc02e, 0x21, 0 + .dw 0x2240, 0xc02e, 0x227f, 0xc02e, 0x21, 0 + .dw 0x22c0, 0xc02e, 0x22ff, 0xc02e, 0x21, 0 + .dw 0x2340, 0xc02e, 0x237f, 0xc02e, 0x21, 0 + .dw 0x23c0, 0xc02e, 0x23ff, 0xc02e, 0x21, 0 + .dw 0x2440, 0xc02e, 0x247f, 0xc02e, 0x21, 0 + .dw 0x24c0, 0xc02e, 0x24ff, 0xc02e, 0x21, 0 + .dw 0x2540, 0xc02e, 0x257f, 0xc02e, 0x21, 0 + .dw 0x25c0, 0xc02e, 0x25ff, 0xc02e, 0x21, 0 + .dw 0x2640, 0xc02e, 0x267f, 0xc02e, 0x21, 0 + .dw 0x26c0, 0xc02e, 0x26ff, 0xc02e, 0x21, 0 + .dw 0x2740, 0xc02e, 0x277f, 0xc02e, 0x21, 0 + .dw 0x27c0, 0xc02e, 0x27ff, 0xc02e, 0x21, 0 + .dw 0x2840, 0xc02e, 0x287f, 0xc02e, 0x21, 0 + .dw 0x28c0, 0xc02e, 0x28ff, 0xc02e, 0x21, 0 + .dw 0x2940, 0xc02e, 0x297f, 0xc02e, 0x21, 0 + .dw 0x29c0, 0xc02e, 0x29ff, 0xc02e, 0x21, 0 + .dw 0x2a40, 0xc02e, 0x2a7f, 0xc02e, 0x21, 0 + .dw 0x2ac0, 0xc02e, 0x2aff, 0xc02e, 0x21, 0 + .dw 0x2b40, 0xc02e, 0x2b7f, 0xc02e, 0x21, 0 + .dw 0x2bc0, 0xc02e, 0x2bff, 0xc02e, 0x21, 0 + .dw 0x2c40, 0xc02e, 0x2c7f, 0xc02e, 0x21, 0 + .dw 0x2cc0, 0xc02e, 0x2cff, 0xc02e, 0x21, 0 + .dw 0x2d40, 0xc02e, 0x2d7f, 0xc02e, 0x21, 0 + .dw 0x2dc0, 0xc02e, 0x2dff, 0xc02e, 0x21, 0 + .dw 0x2e40, 0xc02e, 0x2e7f, 0xc02e, 0x21, 0 + .dw 0x2ec0, 0xc02e, 0x2eff, 0xc02e, 0x21, 0 + .dw 0x2f40, 0xc02e, 0x2f7f, 0xc02e, 0x21, 0 + .dw 0x2fc0, 0xc02e, 0x2fff, 0xc02e, 0x21, 0 + .dw 0x3040, 0xc02e, 0x307f, 0xc02e, 0x21, 0 + .dw 0x30c0, 0xc02e, 0x30ff, 0xc02e, 0x21, 0 + .dw 0x3140, 0xc02e, 0x317f, 0xc02e, 0x21, 0 + .dw 0x31c0, 0xc02e, 0x31ff, 0xc02e, 0x21, 0 + .dw 0x3240, 0xc02e, 0x327f, 0xc02e, 0x21, 0 + .dw 0x32c0, 0xc02e, 0x32ff, 0xc02e, 0x21, 0 + .dw 0x3340, 0xc02e, 0x337f, 0xc02e, 0x21, 0 + .dw 0x33c0, 0xc02e, 0x33ff, 0xc02e, 0x21, 0 + .dw 0x3440, 0xc02e, 0x347f, 0xc02e, 0x21, 0 + .dw 0x34c0, 0xc02e, 0x34ff, 0xc02e, 0x21, 0 + .dw 0x3540, 0xc02e, 0x357f, 0xc02e, 0x21, 0 + .dw 0x35c0, 0xc02e, 0x35ff, 0xc02e, 0x21, 0 + .dw 0x3640, 0xc02e, 0x367f, 0xc02e, 0x21, 0 + .dw 0x36c0, 0xc02e, 0x36ff, 0xc02e, 0x21, 0 + .dw 0x3740, 0xc02e, 0x377f, 0xc02e, 0x21, 0 + .dw 0x37c0, 0xc02e, 0x37ff, 0xc02e, 0x21, 0 + .dw 0x3840, 0xc02e, 0x387f, 0xc02e, 0x21, 0 + .dw 0x38c0, 0xc02e, 0x38ff, 0xc02e, 0x21, 0 + .dw 0x3940, 0xc02e, 0x397f, 0xc02e, 0x21, 0 + .dw 0x39c0, 0xc02e, 0x3fff, 0xc02e, 0x21, 0 + .dw 0x4040, 0xc02e, 0x407f, 0xc02e, 0x21, 0 + .dw 0x40c0, 0xc02e, 0x40ff, 0xc02e, 0x21, 0 + .dw 0x4140, 0xc02e, 0x417f, 0xc02e, 0x21, 0 + .dw 0x41c0, 0xc02e, 0x41ff, 0xc02e, 0x21, 0 + .dw 0x4240, 0xc02e, 0x427f, 0xc02e, 0x21, 0 + .dw 0x42c0, 0xc02e, 0x42ff, 0xc02e, 0x21, 0 + .dw 0x4340, 0xc02e, 0x437f, 0xc02e, 0x21, 0 + .dw 0x43c0, 0xc02e, 0x43ff, 0xc02e, 0x21, 0 + .dw 0x4440, 0xc02e, 0x447f, 0xc02e, 0x21, 0 + .dw 0x44c0, 0xc02e, 0x44ff, 0xc02e, 0x21, 0 + .dw 0x4540, 0xc02e, 0x457f, 0xc02e, 0x21, 0 + .dw 0x45c0, 0xc02e, 0x45ff, 0xc02e, 0x21, 0 + .dw 0x4640, 0xc02e, 0x467f, 0xc02e, 0x21, 0 + .dw 0x46c0, 0xc02e, 0x46ff, 0xc02e, 0x21, 0 + .dw 0x4740, 0xc02e, 0x477f, 0xc02e, 0x21, 0 + .dw 0x47c0, 0xc02e, 0x47ff, 0xc02e, 0x21, 0 + .dw 0x4840, 0xc02e, 0x487f, 0xc02e, 0x21, 0 + .dw 0x48c0, 0xc02e, 0x48ff, 0xc02e, 0x21, 0 + .dw 0x4940, 0xc02e, 0x497f, 0xc02e, 0x21, 0 + .dw 0x49c0, 0xc02e, 0x49ff, 0xc02e, 0x21, 0 + .dw 0x4a40, 0xc02e, 0x4a7f, 0xc02e, 0x21, 0 + .dw 0x4ac0, 0xc02e, 0x4aff, 0xc02e, 0x21, 0 + .dw 0x4b40, 0xc02e, 0x4b7f, 0xc02e, 0x21, 0 + .dw 0x4bc0, 0xc02e, 0x4bff, 0xc02e, 0x21, 0 + .dw 0x4c40, 0xc02e, 0x4c7f, 0xc02e, 0x21, 0 + .dw 0x4cc0, 0xc02e, 0x4cff, 0xc02e, 0x21, 0 + .dw 0x4d40, 0xc02e, 0x4d7f, 0xc02e, 0x21, 0 + .dw 0x4dc0, 0xc02e, 0x4dff, 0xc02e, 0x21, 0 + .dw 0x4e40, 0xc02e, 0x4e7f, 0xc02e, 0x21, 0 + .dw 0x4ec0, 0xc02e, 0x4eff, 0xc02e, 0x21, 0 + .dw 0x4f40, 0xc02e, 0x4f7f, 0xc02e, 0x21, 0 + .dw 0x4fc0, 0xc02e, 0x4fff, 0xc02e, 0x21, 0 + .dw 0x5040, 0xc02e, 0x507f, 0xc02e, 0x21, 0 + .dw 0x50c0, 0xc02e, 0x50ff, 0xc02e, 0x21, 0 + .dw 0x5140, 0xc02e, 0x517f, 0xc02e, 0x21, 0 + .dw 0x51c0, 0xc02e, 0x51ff, 0xc02e, 0x21, 0 + .dw 0x5240, 0xc02e, 0x527f, 0xc02e, 0x21, 0 + .dw 0x52c0, 0xc02e, 0x52ff, 0xc02e, 0x21, 0 + .dw 0x5340, 0xc02e, 0x537f, 0xc02e, 0x21, 0 + .dw 0x53c0, 0xc02e, 0x53ff, 0xc02e, 0x21, 0 + .dw 0x5440, 0xc02e, 0x547f, 0xc02e, 0x21, 0 + .dw 0x54c0, 0xc02e, 0x54ff, 0xc02e, 0x21, 0 + .dw 0x5540, 0xc02e, 0x557f, 0xc02e, 0x21, 0 + .dw 0x55c0, 0xc02e, 0x55ff, 0xc02e, 0x21, 0 + .dw 0x5640, 0xc02e, 0x567f, 0xc02e, 0x21, 0 + .dw 0x56c0, 0xc02e, 0x56ff, 0xc02e, 0x21, 0 + .dw 0x5740, 0xc02e, 0x577f, 0xc02e, 0x21, 0 + .dw 0x57c0, 0xc02e, 0x57ff, 0xc02e, 0x21, 0 + .dw 0x5840, 0xc02e, 0x587f, 0xc02e, 0x21, 0 + .dw 0x58c0, 0xc02e, 0x58ff, 0xc02e, 0x21, 0 + .dw 0x5940, 0xc02e, 0x597f, 0xc02e, 0x21, 0 + .dw 0x59c0, 0xc02e, 0x5fff, 0xc02e, 0x21, 0 + .dw 0x6040, 0xc02e, 0x607f, 0xc02e, 0x21, 0 + .dw 0x60c0, 0xc02e, 0x60ff, 0xc02e, 0x21, 0 + .dw 0x6140, 0xc02e, 0x617f, 0xc02e, 0x21, 0 + .dw 0x61c0, 0xc02e, 0x61ff, 0xc02e, 0x21, 0 + .dw 0x6240, 0xc02e, 0x627f, 0xc02e, 0x21, 0 + .dw 0x62c0, 0xc02e, 0x62ff, 0xc02e, 0x21, 0 + .dw 0x6340, 0xc02e, 0x637f, 0xc02e, 0x21, 0 + .dw 0x63c0, 0xc02e, 0x63ff, 0xc02e, 0x21, 0 + .dw 0x6440, 0xc02e, 0x647f, 0xc02e, 0x21, 0 + .dw 0x64c0, 0xc02e, 0x64ff, 0xc02e, 0x21, 0 + .dw 0x6540, 0xc02e, 0x657f, 0xc02e, 0x21, 0 + .dw 0x65c0, 0xc02e, 0x65ff, 0xc02e, 0x21, 0 + .dw 0x6640, 0xc02e, 0x667f, 0xc02e, 0x21, 0 + .dw 0x66c0, 0xc02e, 0x66ff, 0xc02e, 0x21, 0 + .dw 0x6740, 0xc02e, 0x677f, 0xc02e, 0x21, 0 + .dw 0x67c0, 0xc02e, 0x67ff, 0xc02e, 0x21, 0 + .dw 0x6840, 0xc02e, 0x687f, 0xc02e, 0x21, 0 + .dw 0x68c0, 0xc02e, 0x68ff, 0xc02e, 0x21, 0 + .dw 0x6940, 0xc02e, 0x697f, 0xc02e, 0x21, 0 + .dw 0x69c0, 0xc02e, 0x69ff, 0xc02e, 0x21, 0 + .dw 0x6a40, 0xc02e, 0x6a7f, 0xc02e, 0x21, 0 + .dw 0x6ac0, 0xc02e, 0x6aff, 0xc02e, 0x21, 0 + .dw 0x6b40, 0xc02e, 0x6b7f, 0xc02e, 0x21, 0 + .dw 0x6bc0, 0xc02e, 0x6bff, 0xc02e, 0x21, 0 + .dw 0x6c40, 0xc02e, 0x6c7f, 0xc02e, 0x21, 0 + .dw 0x6cc0, 0xc02e, 0x6cff, 0xc02e, 0x21, 0 + .dw 0x6d40, 0xc02e, 0x6d7f, 0xc02e, 0x21, 0 + .dw 0x6dc0, 0xc02e, 0x6dff, 0xc02e, 0x21, 0 + .dw 0x6e40, 0xc02e, 0x6e7f, 0xc02e, 0x21, 0 + .dw 0x6ec0, 0xc02e, 0x6eff, 0xc02e, 0x21, 0 + .dw 0x6f40, 0xc02e, 0x6f7f, 0xc02e, 0x21, 0 + .dw 0x6fc0, 0xc02e, 0x6fff, 0xc02e, 0x21, 0 + .dw 0x7040, 0xc02e, 0x707f, 0xc02e, 0x21, 0 + .dw 0x70c0, 0xc02e, 0x70ff, 0xc02e, 0x21, 0 + .dw 0x7140, 0xc02e, 0x717f, 0xc02e, 0x21, 0 + .dw 0x71c0, 0xc02e, 0x71ff, 0xc02e, 0x21, 0 + .dw 0x7240, 0xc02e, 0x727f, 0xc02e, 0x21, 0 + .dw 0x72c0, 0xc02e, 0x72ff, 0xc02e, 0x21, 0 + .dw 0x7340, 0xc02e, 0x737f, 0xc02e, 0x21, 0 + .dw 0x73c0, 0xc02e, 0x73ff, 0xc02e, 0x21, 0 + .dw 0x7440, 0xc02e, 0x747f, 0xc02e, 0x21, 0 + .dw 0x74c0, 0xc02e, 0x74ff, 0xc02e, 0x21, 0 + .dw 0x7540, 0xc02e, 0x757f, 0xc02e, 0x21, 0 + .dw 0x75c0, 0xc02e, 0x75ff, 0xc02e, 0x21, 0 + .dw 0x7640, 0xc02e, 0x767f, 0xc02e, 0x21, 0 + .dw 0x76c0, 0xc02e, 0x76ff, 0xc02e, 0x21, 0 + .dw 0x7740, 0xc02e, 0x777f, 0xc02e, 0x21, 0 + .dw 0x77c0, 0xc02e, 0x77ff, 0xc02e, 0x21, 0 + .dw 0x7840, 0xc02e, 0x787f, 0xc02e, 0x21, 0 + .dw 0x78c0, 0xc02e, 0x78ff, 0xc02e, 0x21, 0 + .dw 0x7940, 0xc02e, 0x797f, 0xc02e, 0x21, 0 + .dw 0x79c0, 0xc02e, 0x7fff, 0xc02e, 0x21, 0 + .dw 0x8040, 0xc02e, 0x807f, 0xc02e, 0x21, 0 + .dw 0x80c0, 0xc02e, 0x80ff, 0xc02e, 0x21, 0 + .dw 0x8140, 0xc02e, 0x817f, 0xc02e, 0x21, 0 + .dw 0x81c0, 0xc02e, 0x81ff, 0xc02e, 0x21, 0 + .dw 0x8240, 0xc02e, 0x827f, 0xc02e, 0x21, 0 + .dw 0x82c0, 0xc02e, 0x82ff, 0xc02e, 0x21, 0 + .dw 0x8340, 0xc02e, 0x837f, 0xc02e, 0x21, 0 + .dw 0x83c0, 0xc02e, 0x83ff, 0xc02e, 0x21, 0 + .dw 0x8440, 0xc02e, 0x847f, 0xc02e, 0x21, 0 + .dw 0x84c0, 0xc02e, 0x84ff, 0xc02e, 0x21, 0 + .dw 0x8540, 0xc02e, 0x857f, 0xc02e, 0x21, 0 + .dw 0x85c0, 0xc02e, 0x85ff, 0xc02e, 0x21, 0 + .dw 0x8640, 0xc02e, 0x867f, 0xc02e, 0x21, 0 + .dw 0x86c0, 0xc02e, 0x86ff, 0xc02e, 0x21, 0 + .dw 0x8740, 0xc02e, 0x877f, 0xc02e, 0x21, 0 + .dw 0x87c0, 0xc02e, 0x87ff, 0xc02e, 0x21, 0 + .dw 0x8840, 0xc02e, 0x887f, 0xc02e, 0x21, 0 + .dw 0x88c0, 0xc02e, 0x88ff, 0xc02e, 0x21, 0 + .dw 0x8940, 0xc02e, 0x897f, 0xc02e, 0x21, 0 + .dw 0x89c0, 0xc02e, 0x89ff, 0xc02e, 0x21, 0 + .dw 0x8a40, 0xc02e, 0x8a7f, 0xc02e, 0x21, 0 + .dw 0x8ac0, 0xc02e, 0x8aff, 0xc02e, 0x21, 0 + .dw 0x8b40, 0xc02e, 0x8b7f, 0xc02e, 0x21, 0 + .dw 0x8bc0, 0xc02e, 0x8bff, 0xc02e, 0x21, 0 + .dw 0x8c40, 0xc02e, 0x8c7f, 0xc02e, 0x21, 0 + .dw 0x8cc0, 0xc02e, 0x8cff, 0xc02e, 0x21, 0 + .dw 0x8d40, 0xc02e, 0x8d7f, 0xc02e, 0x21, 0 + .dw 0x8dc0, 0xc02e, 0x8dff, 0xc02e, 0x21, 0 + .dw 0x8e40, 0xc02e, 0x8e7f, 0xc02e, 0x21, 0 + .dw 0x8ec0, 0xc02e, 0x8eff, 0xc02e, 0x21, 0 + .dw 0x8f40, 0xc02e, 0x8f7f, 0xc02e, 0x21, 0 + .dw 0x8fc0, 0xc02e, 0x8fff, 0xc02e, 0x21, 0 + .dw 0x9040, 0xc02e, 0x907f, 0xc02e, 0x21, 0 + .dw 0x90c0, 0xc02e, 0x90ff, 0xc02e, 0x21, 0 + .dw 0x9140, 0xc02e, 0x917f, 0xc02e, 0x21, 0 + .dw 0x91c0, 0xc02e, 0x91ff, 0xc02e, 0x21, 0 + .dw 0x9240, 0xc02e, 0x927f, 0xc02e, 0x21, 0 + .dw 0x92c0, 0xc02e, 0x92ff, 0xc02e, 0x21, 0 + .dw 0x9340, 0xc02e, 0x937f, 0xc02e, 0x21, 0 + .dw 0x93c0, 0xc02e, 0x93ff, 0xc02e, 0x21, 0 + .dw 0x9440, 0xc02e, 0x947f, 0xc02e, 0x21, 0 + .dw 0x94c0, 0xc02e, 0x94ff, 0xc02e, 0x21, 0 + .dw 0x9540, 0xc02e, 0x957f, 0xc02e, 0x21, 0 + .dw 0x95c0, 0xc02e, 0x95ff, 0xc02e, 0x21, 0 + .dw 0x9640, 0xc02e, 0x967f, 0xc02e, 0x21, 0 + .dw 0x96c0, 0xc02e, 0x96ff, 0xc02e, 0x21, 0 + .dw 0x9740, 0xc02e, 0x977f, 0xc02e, 0x21, 0 + .dw 0x97c0, 0xc02e, 0x97ff, 0xc02e, 0x21, 0 + .dw 0x9840, 0xc02e, 0x987f, 0xc02e, 0x21, 0 + .dw 0x98c0, 0xc02e, 0x98ff, 0xc02e, 0x21, 0 + .dw 0x9940, 0xc02e, 0x997f, 0xc02e, 0x21, 0 + .dw 0x99c0, 0xc02e, 0x9fff, 0xc02e, 0x21, 0 + .dw 0xa040, 0xc02e, 0xa07f, 0xc02e, 0x21, 0 + .dw 0xa0c0, 0xc02e, 0xa0ff, 0xc02e, 0x21, 0 + .dw 0xa140, 0xc02e, 0xa17f, 0xc02e, 0x21, 0 + .dw 0xa1c0, 0xc02e, 0xa1ff, 0xc02e, 0x21, 0 + .dw 0xa240, 0xc02e, 0xa27f, 0xc02e, 0x21, 0 + .dw 0xa2c0, 0xc02e, 0xa2ff, 0xc02e, 0x21, 0 + .dw 0xa340, 0xc02e, 0xa37f, 0xc02e, 0x21, 0 + .dw 0xa3c0, 0xc02e, 0xa3ff, 0xc02e, 0x21, 0 + .dw 0xa440, 0xc02e, 0xa47f, 0xc02e, 0x21, 0 + .dw 0xa4c0, 0xc02e, 0xa4ff, 0xc02e, 0x21, 0 + .dw 0xa540, 0xc02e, 0xa57f, 0xc02e, 0x21, 0 + .dw 0xa5c0, 0xc02e, 0xa5ff, 0xc02e, 0x21, 0 + .dw 0xa640, 0xc02e, 0xa67f, 0xc02e, 0x21, 0 + .dw 0xa6c0, 0xc02e, 0xa6ff, 0xc02e, 0x21, 0 + .dw 0xa740, 0xc02e, 0xa77f, 0xc02e, 0x21, 0 + .dw 0xa7c0, 0xc02e, 0xa7ff, 0xc02e, 0x21, 0 + .dw 0xa840, 0xc02e, 0xa87f, 0xc02e, 0x21, 0 + .dw 0xa8c0, 0xc02e, 0xa8ff, 0xc02e, 0x21, 0 + .dw 0xa940, 0xc02e, 0xa97f, 0xc02e, 0x21, 0 + .dw 0xa9c0, 0xc02e, 0xa9ff, 0xc02e, 0x21, 0 + .dw 0xaa40, 0xc02e, 0xaa7f, 0xc02e, 0x21, 0 + .dw 0xaac0, 0xc02e, 0xaaff, 0xc02e, 0x21, 0 + .dw 0xab40, 0xc02e, 0xab7f, 0xc02e, 0x21, 0 + .dw 0xabc0, 0xc02e, 0xabff, 0xc02e, 0x21, 0 + .dw 0xac40, 0xc02e, 0xac7f, 0xc02e, 0x21, 0 + .dw 0xacc0, 0xc02e, 0xacff, 0xc02e, 0x21, 0 + .dw 0xad40, 0xc02e, 0xad7f, 0xc02e, 0x21, 0 + .dw 0xadc0, 0xc02e, 0xadff, 0xc02e, 0x21, 0 + .dw 0xae40, 0xc02e, 0xae7f, 0xc02e, 0x21, 0 + .dw 0xaec0, 0xc02e, 0xaeff, 0xc02e, 0x21, 0 + .dw 0xaf40, 0xc02e, 0xaf7f, 0xc02e, 0x21, 0 + .dw 0xafc0, 0xc02e, 0xafff, 0xc02e, 0x21, 0 + .dw 0xb040, 0xc02e, 0xb07f, 0xc02e, 0x21, 0 + .dw 0xb0c0, 0xc02e, 0xb0ff, 0xc02e, 0x21, 0 + .dw 0xb140, 0xc02e, 0xb17f, 0xc02e, 0x21, 0 + .dw 0xb1c0, 0xc02e, 0xb1ff, 0xc02e, 0x21, 0 + .dw 0xb240, 0xc02e, 0xb27f, 0xc02e, 0x21, 0 + .dw 0xb2c0, 0xc02e, 0xb2ff, 0xc02e, 0x21, 0 + .dw 0xb340, 0xc02e, 0xb37f, 0xc02e, 0x21, 0 + .dw 0xb3c0, 0xc02e, 0xb3ff, 0xc02e, 0x21, 0 + .dw 0xb440, 0xc02e, 0xb47f, 0xc02e, 0x21, 0 + .dw 0xb4c0, 0xc02e, 0xb4ff, 0xc02e, 0x21, 0 + .dw 0xb540, 0xc02e, 0xb57f, 0xc02e, 0x21, 0 + .dw 0xb5c0, 0xc02e, 0xb5ff, 0xc02e, 0x21, 0 + .dw 0xb640, 0xc02e, 0xb67f, 0xc02e, 0x21, 0 + .dw 0xb6c0, 0xc02e, 0xb6ff, 0xc02e, 0x21, 0 + .dw 0xb740, 0xc02e, 0xb77f, 0xc02e, 0x21, 0 + .dw 0xb7c0, 0xc02e, 0xb7ff, 0xc02e, 0x21, 0 + .dw 0xb840, 0xc02e, 0xb87f, 0xc02e, 0x21, 0 + .dw 0xb8c0, 0xc02e, 0xb8ff, 0xc02e, 0x21, 0 + .dw 0xb940, 0xc02e, 0xb97f, 0xc02e, 0x21, 0 + .dw 0xb9c0, 0xc02e, 0xbfff, 0xc02e, 0x21, 0 + .dw 0xc040, 0xc02e, 0xc07f, 0xc02e, 0x21, 0 + .dw 0xc0c0, 0xc02e, 0xc0ff, 0xc02e, 0x21, 0 + .dw 0xc140, 0xc02e, 0xc17f, 0xc02e, 0x21, 0 + .dw 0xc1c0, 0xc02e, 0xc1ff, 0xc02e, 0x21, 0 + .dw 0xc240, 0xc02e, 0xc27f, 0xc02e, 0x21, 0 + .dw 0xc2c0, 0xc02e, 0xc2ff, 0xc02e, 0x21, 0 + .dw 0xc340, 0xc02e, 0xc37f, 0xc02e, 0x21, 0 + .dw 0xc3c0, 0xc02e, 0xc3ff, 0xc02e, 0x21, 0 + .dw 0xc440, 0xc02e, 0xc47f, 0xc02e, 0x21, 0 + .dw 0xc4c0, 0xc02e, 0xc4ff, 0xc02e, 0x21, 0 + .dw 0xc540, 0xc02e, 0xc57f, 0xc02e, 0x21, 0 + .dw 0xc5c0, 0xc02e, 0xc5ff, 0xc02e, 0x21, 0 + .dw 0xc640, 0xc02e, 0xc67f, 0xc02e, 0x21, 0 + .dw 0xc6c0, 0xc02e, 0xc6ff, 0xc02e, 0x21, 0 + .dw 0xc740, 0xc02e, 0xc77f, 0xc02e, 0x21, 0 + .dw 0xc7c0, 0xc02e, 0xc7ff, 0xc02e, 0x21, 0 + .dw 0xc840, 0xc02e, 0xc87f, 0xc02e, 0x21, 0 + .dw 0xc8c0, 0xc02e, 0xc8ff, 0xc02e, 0x21, 0 + .dw 0xc940, 0xc02e, 0xc97f, 0xc02e, 0x21, 0 + .dw 0xc9c0, 0xc02e, 0xc9ff, 0xc02e, 0x21, 0 + .dw 0xca40, 0xc02e, 0xca7f, 0xc02e, 0x21, 0 + .dw 0xcac0, 0xc02e, 0xcaff, 0xc02e, 0x21, 0 + .dw 0xcb40, 0xc02e, 0xcb7f, 0xc02e, 0x21, 0 + .dw 0xcbc0, 0xc02e, 0xcbff, 0xc02e, 0x21, 0 + .dw 0xcc40, 0xc02e, 0xcc7f, 0xc02e, 0x21, 0 + .dw 0xccc0, 0xc02e, 0xccff, 0xc02e, 0x21, 0 + .dw 0xcd40, 0xc02e, 0xcd7f, 0xc02e, 0x21, 0 + .dw 0xcdc0, 0xc02e, 0xcdff, 0xc02e, 0x21, 0 + .dw 0xce40, 0xc02e, 0xce7f, 0xc02e, 0x21, 0 + .dw 0xcec0, 0xc02e, 0xceff, 0xc02e, 0x21, 0 + .dw 0xcf40, 0xc02e, 0xcf7f, 0xc02e, 0x21, 0 + .dw 0xcfc0, 0xc02e, 0xcfff, 0xc02e, 0x21, 0 + .dw 0xd040, 0xc02e, 0xd07f, 0xc02e, 0x21, 0 + .dw 0xd0c0, 0xc02e, 0xd0ff, 0xc02e, 0x21, 0 + .dw 0xd140, 0xc02e, 0xd17f, 0xc02e, 0x21, 0 + .dw 0xd1c0, 0xc02e, 0xd1ff, 0xc02e, 0x21, 0 + .dw 0xd240, 0xc02e, 0xd27f, 0xc02e, 0x21, 0 + .dw 0xd2c0, 0xc02e, 0xd2ff, 0xc02e, 0x21, 0 + .dw 0xd340, 0xc02e, 0xd37f, 0xc02e, 0x21, 0 + .dw 0xd3c0, 0xc02e, 0xd3ff, 0xc02e, 0x21, 0 + .dw 0xd440, 0xc02e, 0xd47f, 0xc02e, 0x21, 0 + .dw 0xd4c0, 0xc02e, 0xd4ff, 0xc02e, 0x21, 0 + .dw 0xd540, 0xc02e, 0xd57f, 0xc02e, 0x21, 0 + .dw 0xd5c0, 0xc02e, 0xd5ff, 0xc02e, 0x21, 0 + .dw 0xd640, 0xc02e, 0xd67f, 0xc02e, 0x21, 0 + .dw 0xd6c0, 0xc02e, 0xd6ff, 0xc02e, 0x21, 0 + .dw 0xd740, 0xc02e, 0xd77f, 0xc02e, 0x21, 0 + .dw 0xd7c0, 0xc02e, 0xd7ff, 0xc02e, 0x21, 0 + .dw 0xd840, 0xc02e, 0xd87f, 0xc02e, 0x21, 0 + .dw 0xd8c0, 0xc02e, 0xd8ff, 0xc02e, 0x21, 0 + .dw 0xd940, 0xc02e, 0xd97f, 0xc02e, 0x21, 0 + .dw 0xd9c0, 0xc02e, 0xdfff, 0xc02e, 0x21, 0 + .dw 0xe040, 0xc02e, 0xe07f, 0xc02e, 0x21, 0 + .dw 0xe0c0, 0xc02e, 0xe0ff, 0xc02e, 0x21, 0 + .dw 0xe140, 0xc02e, 0xe17f, 0xc02e, 0x21, 0 + .dw 0xe1c0, 0xc02e, 0xe1ff, 0xc02e, 0x21, 0 + .dw 0xe240, 0xc02e, 0xe27f, 0xc02e, 0x21, 0 + .dw 0xe2c0, 0xc02e, 0xe2ff, 0xc02e, 0x21, 0 + .dw 0xe340, 0xc02e, 0xe37f, 0xc02e, 0x21, 0 + .dw 0xe3c0, 0xc02e, 0xe3ff, 0xc02e, 0x21, 0 + .dw 0xe440, 0xc02e, 0xe47f, 0xc02e, 0x21, 0 + .dw 0xe4c0, 0xc02e, 0xe4ff, 0xc02e, 0x21, 0 + .dw 0xe540, 0xc02e, 0xe57f, 0xc02e, 0x21, 0 + .dw 0xe5c0, 0xc02e, 0xe5ff, 0xc02e, 0x21, 0 + .dw 0xe640, 0xc02e, 0xe67f, 0xc02e, 0x21, 0 + .dw 0xe6c0, 0xc02e, 0xe6ff, 0xc02e, 0x21, 0 + .dw 0xe740, 0xc02e, 0xe77f, 0xc02e, 0x21, 0 + .dw 0xe7c0, 0xc02e, 0xe7ff, 0xc02e, 0x21, 0 + .dw 0xe840, 0xc02e, 0xe87f, 0xc02e, 0x21, 0 + .dw 0xe8c0, 0xc02e, 0xe8ff, 0xc02e, 0x21, 0 + .dw 0xe940, 0xc02e, 0xe97f, 0xc02e, 0x21, 0 + .dw 0xe9c0, 0xc02e, 0xe9ff, 0xc02e, 0x21, 0 + .dw 0xea40, 0xc02e, 0xea7f, 0xc02e, 0x21, 0 + .dw 0xeac0, 0xc02e, 0xeaff, 0xc02e, 0x21, 0 + .dw 0xeb40, 0xc02e, 0xeb7f, 0xc02e, 0x21, 0 + .dw 0xebc0, 0xc02e, 0xebff, 0xc02e, 0x21, 0 + .dw 0xec40, 0xc02e, 0xec7f, 0xc02e, 0x21, 0 + .dw 0xecc0, 0xc02e, 0xecff, 0xc02e, 0x21, 0 + .dw 0xed40, 0xc02e, 0xed7f, 0xc02e, 0x21, 0 + .dw 0xedc0, 0xc02e, 0xedff, 0xc02e, 0x21, 0 + .dw 0xee40, 0xc02e, 0xee7f, 0xc02e, 0x21, 0 + .dw 0xeec0, 0xc02e, 0xeeff, 0xc02e, 0x21, 0 + .dw 0xef40, 0xc02e, 0xef7f, 0xc02e, 0x21, 0 + .dw 0xefc0, 0xc02e, 0xefff, 0xc02e, 0x21, 0 + .dw 0xf040, 0xc02e, 0xf07f, 0xc02e, 0x21, 0 + .dw 0xf0c0, 0xc02e, 0xf0ff, 0xc02e, 0x21, 0 + .dw 0xf140, 0xc02e, 0xf17f, 0xc02e, 0x21, 0 + .dw 0xf1c0, 0xc02e, 0xf1ff, 0xc02e, 0x21, 0 + .dw 0xf240, 0xc02e, 0xf27f, 0xc02e, 0x21, 0 + .dw 0xf2c0, 0xc02e, 0xf2ff, 0xc02e, 0x21, 0 + .dw 0xf340, 0xc02e, 0xf37f, 0xc02e, 0x21, 0 + .dw 0xf3c0, 0xc02e, 0xf3ff, 0xc02e, 0x21, 0 + .dw 0xf440, 0xc02e, 0xf47f, 0xc02e, 0x21, 0 + .dw 0xf4c0, 0xc02e, 0xf4ff, 0xc02e, 0x21, 0 + .dw 0xf540, 0xc02e, 0xf57f, 0xc02e, 0x21, 0 + .dw 0xf5c0, 0xc02e, 0xf5ff, 0xc02e, 0x21, 0 + .dw 0xf640, 0xc02e, 0xf67f, 0xc02e, 0x21, 0 + .dw 0xf6c0, 0xc02e, 0xf6ff, 0xc02e, 0x21, 0 + .dw 0xf740, 0xc02e, 0xf77f, 0xc02e, 0x21, 0 + .dw 0xf7c0, 0xc02e, 0xf7ff, 0xc02e, 0x21, 0 + .dw 0xf840, 0xc02e, 0xf87f, 0xc02e, 0x21, 0 + .dw 0xf8c0, 0xc02e, 0xf8ff, 0xc02e, 0x21, 0 + .dw 0xf940, 0xc02e, 0xf97f, 0xc02e, 0x21, 0 + .dw 0xf9c0, 0xc02e, 0xffff, 0xc02e, 0x21, 0 + .dw 0x0040, 0xc02f, 0x007f, 0xc02f, 0x21, 0 + .dw 0x00c0, 0xc02f, 0x00ff, 0xc02f, 0x21, 0 + .dw 0x0140, 0xc02f, 0x017f, 0xc02f, 0x21, 0 + .dw 0x01c0, 0xc02f, 0x01ff, 0xc02f, 0x21, 0 + .dw 0x0240, 0xc02f, 0x027f, 0xc02f, 0x21, 0 + .dw 0x02c0, 0xc02f, 0x02ff, 0xc02f, 0x21, 0 + .dw 0x0340, 0xc02f, 0x037f, 0xc02f, 0x21, 0 + .dw 0x03c0, 0xc02f, 0x03ff, 0xc02f, 0x21, 0 + .dw 0x0440, 0xc02f, 0x047f, 0xc02f, 0x21, 0 + .dw 0x04c0, 0xc02f, 0x04ff, 0xc02f, 0x21, 0 + .dw 0x0540, 0xc02f, 0x057f, 0xc02f, 0x21, 0 + .dw 0x05c0, 0xc02f, 0x05ff, 0xc02f, 0x21, 0 + .dw 0x0640, 0xc02f, 0x067f, 0xc02f, 0x21, 0 + .dw 0x06c0, 0xc02f, 0x06ff, 0xc02f, 0x21, 0 + .dw 0x0740, 0xc02f, 0x077f, 0xc02f, 0x21, 0 + .dw 0x07c0, 0xc02f, 0x07ff, 0xc02f, 0x21, 0 + .dw 0x0840, 0xc02f, 0x087f, 0xc02f, 0x21, 0 + .dw 0x08c0, 0xc02f, 0x08ff, 0xc02f, 0x21, 0 + .dw 0x0940, 0xc02f, 0x097f, 0xc02f, 0x21, 0 + .dw 0x09c0, 0xc02f, 0x09ff, 0xc02f, 0x21, 0 + .dw 0x0a40, 0xc02f, 0x0a7f, 0xc02f, 0x21, 0 + .dw 0x0ac0, 0xc02f, 0x0aff, 0xc02f, 0x21, 0 + .dw 0x0b40, 0xc02f, 0x0b7f, 0xc02f, 0x21, 0 + .dw 0x0bc0, 0xc02f, 0x0bff, 0xc02f, 0x21, 0 + .dw 0x0c40, 0xc02f, 0x0c7f, 0xc02f, 0x21, 0 + .dw 0x0cc0, 0xc02f, 0x0cff, 0xc02f, 0x21, 0 + .dw 0x0d40, 0xc02f, 0x0d7f, 0xc02f, 0x21, 0 + .dw 0x0dc0, 0xc02f, 0x0dff, 0xc02f, 0x21, 0 + .dw 0x0e40, 0xc02f, 0x0e7f, 0xc02f, 0x21, 0 + .dw 0x0ec0, 0xc02f, 0x0eff, 0xc02f, 0x21, 0 + .dw 0x0f40, 0xc02f, 0x0f7f, 0xc02f, 0x21, 0 + .dw 0x0fc0, 0xc02f, 0x0fff, 0xc02f, 0x21, 0 + .dw 0x1040, 0xc02f, 0x107f, 0xc02f, 0x21, 0 + .dw 0x10c0, 0xc02f, 0x10ff, 0xc02f, 0x21, 0 + .dw 0x1140, 0xc02f, 0x117f, 0xc02f, 0x21, 0 + .dw 0x11c0, 0xc02f, 0x11ff, 0xc02f, 0x21, 0 + .dw 0x1240, 0xc02f, 0x127f, 0xc02f, 0x21, 0 + .dw 0x12c0, 0xc02f, 0x12ff, 0xc02f, 0x21, 0 + .dw 0x1340, 0xc02f, 0x137f, 0xc02f, 0x21, 0 + .dw 0x13c0, 0xc02f, 0x13ff, 0xc02f, 0x21, 0 + .dw 0x1440, 0xc02f, 0x147f, 0xc02f, 0x21, 0 + .dw 0x14c0, 0xc02f, 0x14ff, 0xc02f, 0x21, 0 + .dw 0x1540, 0xc02f, 0x157f, 0xc02f, 0x21, 0 + .dw 0x15c0, 0xc02f, 0x15ff, 0xc02f, 0x21, 0 + .dw 0x1640, 0xc02f, 0x167f, 0xc02f, 0x21, 0 + .dw 0x16c0, 0xc02f, 0x16ff, 0xc02f, 0x21, 0 + .dw 0x1740, 0xc02f, 0x177f, 0xc02f, 0x21, 0 + .dw 0x17c0, 0xc02f, 0x17ff, 0xc02f, 0x21, 0 + .dw 0x1840, 0xc02f, 0x187f, 0xc02f, 0x21, 0 + .dw 0x18c0, 0xc02f, 0x18ff, 0xc02f, 0x21, 0 + .dw 0x1940, 0xc02f, 0x197f, 0xc02f, 0x21, 0 + .dw 0x19c0, 0xc02f, 0x1fff, 0xc02f, 0x21, 0 + .dw 0x2040, 0xc02f, 0x207f, 0xc02f, 0x21, 0 + .dw 0x20c0, 0xc02f, 0x20ff, 0xc02f, 0x21, 0 + .dw 0x2140, 0xc02f, 0x217f, 0xc02f, 0x21, 0 + .dw 0x21c0, 0xc02f, 0x21ff, 0xc02f, 0x21, 0 + .dw 0x2240, 0xc02f, 0x227f, 0xc02f, 0x21, 0 + .dw 0x22c0, 0xc02f, 0x22ff, 0xc02f, 0x21, 0 + .dw 0x2340, 0xc02f, 0x237f, 0xc02f, 0x21, 0 + .dw 0x23c0, 0xc02f, 0x23ff, 0xc02f, 0x21, 0 + .dw 0x2440, 0xc02f, 0x247f, 0xc02f, 0x21, 0 + .dw 0x24c0, 0xc02f, 0x24ff, 0xc02f, 0x21, 0 + .dw 0x2540, 0xc02f, 0x257f, 0xc02f, 0x21, 0 + .dw 0x25c0, 0xc02f, 0x25ff, 0xc02f, 0x21, 0 + .dw 0x2640, 0xc02f, 0x267f, 0xc02f, 0x21, 0 + .dw 0x26c0, 0xc02f, 0x26ff, 0xc02f, 0x21, 0 + .dw 0x2740, 0xc02f, 0x277f, 0xc02f, 0x21, 0 + .dw 0x27c0, 0xc02f, 0x27ff, 0xc02f, 0x21, 0 + .dw 0x2840, 0xc02f, 0x287f, 0xc02f, 0x21, 0 + .dw 0x28c0, 0xc02f, 0x28ff, 0xc02f, 0x21, 0 + .dw 0x2940, 0xc02f, 0x297f, 0xc02f, 0x21, 0 + .dw 0x29c0, 0xc02f, 0x29ff, 0xc02f, 0x21, 0 + .dw 0x2a40, 0xc02f, 0x2a7f, 0xc02f, 0x21, 0 + .dw 0x2ac0, 0xc02f, 0x2aff, 0xc02f, 0x21, 0 + .dw 0x2b40, 0xc02f, 0x2b7f, 0xc02f, 0x21, 0 + .dw 0x2bc0, 0xc02f, 0x2bff, 0xc02f, 0x21, 0 + .dw 0x2c40, 0xc02f, 0x2c7f, 0xc02f, 0x21, 0 + .dw 0x2cc0, 0xc02f, 0x2cff, 0xc02f, 0x21, 0 + .dw 0x2d40, 0xc02f, 0x2d7f, 0xc02f, 0x21, 0 + .dw 0x2dc0, 0xc02f, 0x2dff, 0xc02f, 0x21, 0 + .dw 0x2e40, 0xc02f, 0x2e7f, 0xc02f, 0x21, 0 + .dw 0x2ec0, 0xc02f, 0x2eff, 0xc02f, 0x21, 0 + .dw 0x2f40, 0xc02f, 0x2f7f, 0xc02f, 0x21, 0 + .dw 0x2fc0, 0xc02f, 0x2fff, 0xc02f, 0x21, 0 + .dw 0x3040, 0xc02f, 0x307f, 0xc02f, 0x21, 0 + .dw 0x30c0, 0xc02f, 0x30ff, 0xc02f, 0x21, 0 + .dw 0x3140, 0xc02f, 0x317f, 0xc02f, 0x21, 0 + .dw 0x31c0, 0xc02f, 0x31ff, 0xc02f, 0x21, 0 + .dw 0x3240, 0xc02f, 0x327f, 0xc02f, 0x21, 0 + .dw 0x32c0, 0xc02f, 0x32ff, 0xc02f, 0x21, 0 + .dw 0x3340, 0xc02f, 0x337f, 0xc02f, 0x21, 0 + .dw 0x33c0, 0xc02f, 0x33ff, 0xc02f, 0x21, 0 + .dw 0x3440, 0xc02f, 0x347f, 0xc02f, 0x21, 0 + .dw 0x34c0, 0xc02f, 0x34ff, 0xc02f, 0x21, 0 + .dw 0x3540, 0xc02f, 0x357f, 0xc02f, 0x21, 0 + .dw 0x35c0, 0xc02f, 0x35ff, 0xc02f, 0x21, 0 + .dw 0x3640, 0xc02f, 0x367f, 0xc02f, 0x21, 0 + .dw 0x36c0, 0xc02f, 0x36ff, 0xc02f, 0x21, 0 + .dw 0x3740, 0xc02f, 0x377f, 0xc02f, 0x21, 0 + .dw 0x37c0, 0xc02f, 0x37ff, 0xc02f, 0x21, 0 + .dw 0x3840, 0xc02f, 0x387f, 0xc02f, 0x21, 0 + .dw 0x38c0, 0xc02f, 0x38ff, 0xc02f, 0x21, 0 + .dw 0x3940, 0xc02f, 0x397f, 0xc02f, 0x21, 0 + .dw 0x39c0, 0xc02f, 0x1fff, 0xc030, 0x21, 0 + .dw 0x3a00, 0xc030, 0x5fff, 0xc030, 0x21, 0 + .dw 0x7a00, 0xc030, 0x9fff, 0xc030, 0x21, 0 + .dw 0xba00, 0xc030, 0xdfff, 0xc030, 0x21, 0 + .dw 0xfa00, 0xc030, 0x1fff, 0xc031, 0x21, 0 + .dw 0x3a00, 0xc031, 0x5fff, 0xc031, 0x21, 0 + .dw 0x7a00, 0xc031, 0x9fff, 0xc031, 0x21, 0 + .dw 0xba00, 0xc031, 0xdfff, 0xc031, 0x21, 0 + .dw 0xfa00, 0xc031, 0x1fff, 0xc032, 0x21, 0 + .dw 0x3a00, 0xc032, 0x5fff, 0xc032, 0x21, 0 + .dw 0x7a00, 0xc032, 0x9fff, 0xc032, 0x21, 0 + .dw 0xba00, 0xc032, 0xdfff, 0xc032, 0x21, 0 + .dw 0xfa00, 0xc032, 0xffff, 0xc033, 0x21, 0 + .dw 0x1a00, 0xc034, 0x1fff, 0xc034, 0x21, 0 + .dw 0x3a00, 0xc034, 0x3fff, 0xc034, 0x21, 0 + .dw 0x5a00, 0xc034, 0x5fff, 0xc034, 0x21, 0 + .dw 0x7a00, 0xc034, 0x7fff, 0xc034, 0x21, 0 + .dw 0x9a00, 0xc034, 0x9fff, 0xc034, 0x21, 0 + .dw 0xba00, 0xc034, 0xbfff, 0xc034, 0x21, 0 + .dw 0xda00, 0xc034, 0xdfff, 0xc034, 0x21, 0 + .dw 0xfa00, 0xc034, 0xffff, 0xc034, 0x21, 0 + .dw 0x1a00, 0xc035, 0x1fff, 0xc035, 0x21, 0 + .dw 0x3a00, 0xc035, 0x3fff, 0xc035, 0x21, 0 + .dw 0x5a00, 0xc035, 0x5fff, 0xc035, 0x21, 0 + .dw 0x7a00, 0xc035, 0x7fff, 0xc035, 0x21, 0 + .dw 0x9a00, 0xc035, 0x9fff, 0xc035, 0x21, 0 + .dw 0xba00, 0xc035, 0xbfff, 0xc035, 0x21, 0 + .dw 0xda00, 0xc035, 0xdfff, 0xc035, 0x21, 0 + .dw 0xfa00, 0xc035, 0xffff, 0xc035, 0x21, 0 + .dw 0x1a00, 0xc036, 0x1fff, 0xc036, 0x21, 0 + .dw 0x3a00, 0xc036, 0x3fff, 0xc036, 0x21, 0 + .dw 0x5a00, 0xc036, 0x5fff, 0xc036, 0x21, 0 + .dw 0x7a00, 0xc036, 0x7fff, 0xc036, 0x21, 0 + .dw 0x9a00, 0xc036, 0x9fff, 0xc036, 0x21, 0 + .dw 0xba00, 0xc036, 0xbfff, 0xc036, 0x21, 0 + .dw 0xda00, 0xc036, 0xdfff, 0xc036, 0x21, 0 + .dw 0xfa00, 0xc036, 0xffff, 0xc036, 0x21, 0 + .dw 0x1a00, 0xc037, 0x1fff, 0xc037, 0x21, 0 + .dw 0x3a00, 0xc037, 0x1fff, 0xc038, 0x21, 0 + .dw 0x2040, 0xc038, 0x207f, 0xc038, 0x21, 0 + .dw 0x20c0, 0xc038, 0x20ff, 0xc038, 0x21, 0 + .dw 0x2140, 0xc038, 0x217f, 0xc038, 0x21, 0 + .dw 0x21c0, 0xc038, 0x21ff, 0xc038, 0x21, 0 + .dw 0x2240, 0xc038, 0x227f, 0xc038, 0x21, 0 + .dw 0x22c0, 0xc038, 0x22ff, 0xc038, 0x21, 0 + .dw 0x2340, 0xc038, 0x237f, 0xc038, 0x21, 0 + .dw 0x23c0, 0xc038, 0x23ff, 0xc038, 0x21, 0 + .dw 0x2440, 0xc038, 0x247f, 0xc038, 0x21, 0 + .dw 0x24c0, 0xc038, 0x24ff, 0xc038, 0x21, 0 + .dw 0x2540, 0xc038, 0x257f, 0xc038, 0x21, 0 + .dw 0x25c0, 0xc038, 0x25ff, 0xc038, 0x21, 0 + .dw 0x2640, 0xc038, 0x267f, 0xc038, 0x21, 0 + .dw 0x26c0, 0xc038, 0x26ff, 0xc038, 0x21, 0 + .dw 0x2740, 0xc038, 0x277f, 0xc038, 0x21, 0 + .dw 0x27c0, 0xc038, 0x27ff, 0xc038, 0x21, 0 + .dw 0x2840, 0xc038, 0x287f, 0xc038, 0x21, 0 + .dw 0x28c0, 0xc038, 0x28ff, 0xc038, 0x21, 0 + .dw 0x2940, 0xc038, 0x297f, 0xc038, 0x21, 0 + .dw 0x29c0, 0xc038, 0x29ff, 0xc038, 0x21, 0 + .dw 0x2a40, 0xc038, 0x2a7f, 0xc038, 0x21, 0 + .dw 0x2ac0, 0xc038, 0x2aff, 0xc038, 0x21, 0 + .dw 0x2b40, 0xc038, 0x2b7f, 0xc038, 0x21, 0 + .dw 0x2bc0, 0xc038, 0x2bff, 0xc038, 0x21, 0 + .dw 0x2c40, 0xc038, 0x2c7f, 0xc038, 0x21, 0 + .dw 0x2cc0, 0xc038, 0x2cff, 0xc038, 0x21, 0 + .dw 0x2d40, 0xc038, 0x2d7f, 0xc038, 0x21, 0 + .dw 0x2dc0, 0xc038, 0x2dff, 0xc038, 0x21, 0 + .dw 0x2e40, 0xc038, 0x2e7f, 0xc038, 0x21, 0 + .dw 0x2ec0, 0xc038, 0x2eff, 0xc038, 0x21, 0 + .dw 0x2f40, 0xc038, 0x2f7f, 0xc038, 0x21, 0 + .dw 0x2fc0, 0xc038, 0x2fff, 0xc038, 0x21, 0 + .dw 0x3040, 0xc038, 0x307f, 0xc038, 0x21, 0 + .dw 0x30c0, 0xc038, 0x30ff, 0xc038, 0x21, 0 + .dw 0x3140, 0xc038, 0x317f, 0xc038, 0x21, 0 + .dw 0x31c0, 0xc038, 0x31ff, 0xc038, 0x21, 0 + .dw 0x3240, 0xc038, 0x327f, 0xc038, 0x21, 0 + .dw 0x32c0, 0xc038, 0x32ff, 0xc038, 0x21, 0 + .dw 0x3340, 0xc038, 0x337f, 0xc038, 0x21, 0 + .dw 0x33c0, 0xc038, 0x33ff, 0xc038, 0x21, 0 + .dw 0x3440, 0xc038, 0x347f, 0xc038, 0x21, 0 + .dw 0x34c0, 0xc038, 0x34ff, 0xc038, 0x21, 0 + .dw 0x3540, 0xc038, 0x357f, 0xc038, 0x21, 0 + .dw 0x35c0, 0xc038, 0x35ff, 0xc038, 0x21, 0 + .dw 0x3640, 0xc038, 0x367f, 0xc038, 0x21, 0 + .dw 0x36c0, 0xc038, 0x36ff, 0xc038, 0x21, 0 + .dw 0x3740, 0xc038, 0x377f, 0xc038, 0x21, 0 + .dw 0x37c0, 0xc038, 0x37ff, 0xc038, 0x21, 0 + .dw 0x3840, 0xc038, 0x387f, 0xc038, 0x21, 0 + .dw 0x38c0, 0xc038, 0x38ff, 0xc038, 0x21, 0 + .dw 0x3940, 0xc038, 0x397f, 0xc038, 0x21, 0 + .dw 0x39c0, 0xc038, 0x5fff, 0xc038, 0x21, 0 + .dw 0x6040, 0xc038, 0x607f, 0xc038, 0x21, 0 + .dw 0x60c0, 0xc038, 0x60ff, 0xc038, 0x21, 0 + .dw 0x6140, 0xc038, 0x617f, 0xc038, 0x21, 0 + .dw 0x61c0, 0xc038, 0x61ff, 0xc038, 0x21, 0 + .dw 0x6240, 0xc038, 0x627f, 0xc038, 0x21, 0 + .dw 0x62c0, 0xc038, 0x62ff, 0xc038, 0x21, 0 + .dw 0x6340, 0xc038, 0x637f, 0xc038, 0x21, 0 + .dw 0x63c0, 0xc038, 0x63ff, 0xc038, 0x21, 0 + .dw 0x6440, 0xc038, 0x647f, 0xc038, 0x21, 0 + .dw 0x64c0, 0xc038, 0x64ff, 0xc038, 0x21, 0 + .dw 0x6540, 0xc038, 0x657f, 0xc038, 0x21, 0 + .dw 0x65c0, 0xc038, 0x65ff, 0xc038, 0x21, 0 + .dw 0x6640, 0xc038, 0x667f, 0xc038, 0x21, 0 + .dw 0x66c0, 0xc038, 0x66ff, 0xc038, 0x21, 0 + .dw 0x6740, 0xc038, 0x677f, 0xc038, 0x21, 0 + .dw 0x67c0, 0xc038, 0x67ff, 0xc038, 0x21, 0 + .dw 0x6840, 0xc038, 0x687f, 0xc038, 0x21, 0 + .dw 0x68c0, 0xc038, 0x68ff, 0xc038, 0x21, 0 + .dw 0x6940, 0xc038, 0x697f, 0xc038, 0x21, 0 + .dw 0x69c0, 0xc038, 0x69ff, 0xc038, 0x21, 0 + .dw 0x6a40, 0xc038, 0x6a7f, 0xc038, 0x21, 0 + .dw 0x6ac0, 0xc038, 0x6aff, 0xc038, 0x21, 0 + .dw 0x6b40, 0xc038, 0x6b7f, 0xc038, 0x21, 0 + .dw 0x6bc0, 0xc038, 0x6bff, 0xc038, 0x21, 0 + .dw 0x6c40, 0xc038, 0x6c7f, 0xc038, 0x21, 0 + .dw 0x6cc0, 0xc038, 0x6cff, 0xc038, 0x21, 0 + .dw 0x6d40, 0xc038, 0x6d7f, 0xc038, 0x21, 0 + .dw 0x6dc0, 0xc038, 0x6dff, 0xc038, 0x21, 0 + .dw 0x6e40, 0xc038, 0x6e7f, 0xc038, 0x21, 0 + .dw 0x6ec0, 0xc038, 0x6eff, 0xc038, 0x21, 0 + .dw 0x6f40, 0xc038, 0x6f7f, 0xc038, 0x21, 0 + .dw 0x6fc0, 0xc038, 0x6fff, 0xc038, 0x21, 0 + .dw 0x7040, 0xc038, 0x707f, 0xc038, 0x21, 0 + .dw 0x70c0, 0xc038, 0x70ff, 0xc038, 0x21, 0 + .dw 0x7140, 0xc038, 0x717f, 0xc038, 0x21, 0 + .dw 0x71c0, 0xc038, 0x71ff, 0xc038, 0x21, 0 + .dw 0x7240, 0xc038, 0x727f, 0xc038, 0x21, 0 + .dw 0x72c0, 0xc038, 0x72ff, 0xc038, 0x21, 0 + .dw 0x7340, 0xc038, 0x737f, 0xc038, 0x21, 0 + .dw 0x73c0, 0xc038, 0x73ff, 0xc038, 0x21, 0 + .dw 0x7440, 0xc038, 0x747f, 0xc038, 0x21, 0 + .dw 0x74c0, 0xc038, 0x74ff, 0xc038, 0x21, 0 + .dw 0x7540, 0xc038, 0x757f, 0xc038, 0x21, 0 + .dw 0x75c0, 0xc038, 0x75ff, 0xc038, 0x21, 0 + .dw 0x7640, 0xc038, 0x767f, 0xc038, 0x21, 0 + .dw 0x76c0, 0xc038, 0x76ff, 0xc038, 0x21, 0 + .dw 0x7740, 0xc038, 0x777f, 0xc038, 0x21, 0 + .dw 0x77c0, 0xc038, 0x77ff, 0xc038, 0x21, 0 + .dw 0x7840, 0xc038, 0x787f, 0xc038, 0x21, 0 + .dw 0x78c0, 0xc038, 0x78ff, 0xc038, 0x21, 0 + .dw 0x7940, 0xc038, 0x797f, 0xc038, 0x21, 0 + .dw 0x79c0, 0xc038, 0x9fff, 0xc038, 0x21, 0 + .dw 0xa040, 0xc038, 0xa07f, 0xc038, 0x21, 0 + .dw 0xa0c0, 0xc038, 0xa0ff, 0xc038, 0x21, 0 + .dw 0xa140, 0xc038, 0xa17f, 0xc038, 0x21, 0 + .dw 0xa1c0, 0xc038, 0xa1ff, 0xc038, 0x21, 0 + .dw 0xa240, 0xc038, 0xa27f, 0xc038, 0x21, 0 + .dw 0xa2c0, 0xc038, 0xa2ff, 0xc038, 0x21, 0 + .dw 0xa340, 0xc038, 0xa37f, 0xc038, 0x21, 0 + .dw 0xa3c0, 0xc038, 0xa3ff, 0xc038, 0x21, 0 + .dw 0xa440, 0xc038, 0xa47f, 0xc038, 0x21, 0 + .dw 0xa4c0, 0xc038, 0xa4ff, 0xc038, 0x21, 0 + .dw 0xa540, 0xc038, 0xa57f, 0xc038, 0x21, 0 + .dw 0xa5c0, 0xc038, 0xa5ff, 0xc038, 0x21, 0 + .dw 0xa640, 0xc038, 0xa67f, 0xc038, 0x21, 0 + .dw 0xa6c0, 0xc038, 0xa6ff, 0xc038, 0x21, 0 + .dw 0xa740, 0xc038, 0xa77f, 0xc038, 0x21, 0 + .dw 0xa7c0, 0xc038, 0xa7ff, 0xc038, 0x21, 0 + .dw 0xa840, 0xc038, 0xa87f, 0xc038, 0x21, 0 + .dw 0xa8c0, 0xc038, 0xa8ff, 0xc038, 0x21, 0 + .dw 0xa940, 0xc038, 0xa97f, 0xc038, 0x21, 0 + .dw 0xa9c0, 0xc038, 0xa9ff, 0xc038, 0x21, 0 + .dw 0xaa40, 0xc038, 0xaa7f, 0xc038, 0x21, 0 + .dw 0xaac0, 0xc038, 0xaaff, 0xc038, 0x21, 0 + .dw 0xab40, 0xc038, 0xab7f, 0xc038, 0x21, 0 + .dw 0xabc0, 0xc038, 0xabff, 0xc038, 0x21, 0 + .dw 0xac40, 0xc038, 0xac7f, 0xc038, 0x21, 0 + .dw 0xacc0, 0xc038, 0xacff, 0xc038, 0x21, 0 + .dw 0xad40, 0xc038, 0xad7f, 0xc038, 0x21, 0 + .dw 0xadc0, 0xc038, 0xadff, 0xc038, 0x21, 0 + .dw 0xae40, 0xc038, 0xae7f, 0xc038, 0x21, 0 + .dw 0xaec0, 0xc038, 0xaeff, 0xc038, 0x21, 0 + .dw 0xaf40, 0xc038, 0xaf7f, 0xc038, 0x21, 0 + .dw 0xafc0, 0xc038, 0xafff, 0xc038, 0x21, 0 + .dw 0xb040, 0xc038, 0xb07f, 0xc038, 0x21, 0 + .dw 0xb0c0, 0xc038, 0xb0ff, 0xc038, 0x21, 0 + .dw 0xb140, 0xc038, 0xb17f, 0xc038, 0x21, 0 + .dw 0xb1c0, 0xc038, 0xb1ff, 0xc038, 0x21, 0 + .dw 0xb240, 0xc038, 0xb27f, 0xc038, 0x21, 0 + .dw 0xb2c0, 0xc038, 0xb2ff, 0xc038, 0x21, 0 + .dw 0xb340, 0xc038, 0xb37f, 0xc038, 0x21, 0 + .dw 0xb3c0, 0xc038, 0xb3ff, 0xc038, 0x21, 0 + .dw 0xb440, 0xc038, 0xb47f, 0xc038, 0x21, 0 + .dw 0xb4c0, 0xc038, 0xb4ff, 0xc038, 0x21, 0 + .dw 0xb540, 0xc038, 0xb57f, 0xc038, 0x21, 0 + .dw 0xb5c0, 0xc038, 0xb5ff, 0xc038, 0x21, 0 + .dw 0xb640, 0xc038, 0xb67f, 0xc038, 0x21, 0 + .dw 0xb6c0, 0xc038, 0xb6ff, 0xc038, 0x21, 0 + .dw 0xb740, 0xc038, 0xb77f, 0xc038, 0x21, 0 + .dw 0xb7c0, 0xc038, 0xb7ff, 0xc038, 0x21, 0 + .dw 0xb840, 0xc038, 0xb87f, 0xc038, 0x21, 0 + .dw 0xb8c0, 0xc038, 0xb8ff, 0xc038, 0x21, 0 + .dw 0xb940, 0xc038, 0xb97f, 0xc038, 0x21, 0 + .dw 0xb9c0, 0xc038, 0xdfff, 0xc038, 0x21, 0 + .dw 0xe040, 0xc038, 0xe07f, 0xc038, 0x21, 0 + .dw 0xe0c0, 0xc038, 0xe0ff, 0xc038, 0x21, 0 + .dw 0xe140, 0xc038, 0xe17f, 0xc038, 0x21, 0 + .dw 0xe1c0, 0xc038, 0xe1ff, 0xc038, 0x21, 0 + .dw 0xe240, 0xc038, 0xe27f, 0xc038, 0x21, 0 + .dw 0xe2c0, 0xc038, 0xe2ff, 0xc038, 0x21, 0 + .dw 0xe340, 0xc038, 0xe37f, 0xc038, 0x21, 0 + .dw 0xe3c0, 0xc038, 0xe3ff, 0xc038, 0x21, 0 + .dw 0xe440, 0xc038, 0xe47f, 0xc038, 0x21, 0 + .dw 0xe4c0, 0xc038, 0xe4ff, 0xc038, 0x21, 0 + .dw 0xe540, 0xc038, 0xe57f, 0xc038, 0x21, 0 + .dw 0xe5c0, 0xc038, 0xe5ff, 0xc038, 0x21, 0 + .dw 0xe640, 0xc038, 0xe67f, 0xc038, 0x21, 0 + .dw 0xe6c0, 0xc038, 0xe6ff, 0xc038, 0x21, 0 + .dw 0xe740, 0xc038, 0xe77f, 0xc038, 0x21, 0 + .dw 0xe7c0, 0xc038, 0xe7ff, 0xc038, 0x21, 0 + .dw 0xe840, 0xc038, 0xe87f, 0xc038, 0x21, 0 + .dw 0xe8c0, 0xc038, 0xe8ff, 0xc038, 0x21, 0 + .dw 0xe940, 0xc038, 0xe97f, 0xc038, 0x21, 0 + .dw 0xe9c0, 0xc038, 0xe9ff, 0xc038, 0x21, 0 + .dw 0xea40, 0xc038, 0xea7f, 0xc038, 0x21, 0 + .dw 0xeac0, 0xc038, 0xeaff, 0xc038, 0x21, 0 + .dw 0xeb40, 0xc038, 0xeb7f, 0xc038, 0x21, 0 + .dw 0xebc0, 0xc038, 0xebff, 0xc038, 0x21, 0 + .dw 0xec40, 0xc038, 0xec7f, 0xc038, 0x21, 0 + .dw 0xecc0, 0xc038, 0xecff, 0xc038, 0x21, 0 + .dw 0xed40, 0xc038, 0xed7f, 0xc038, 0x21, 0 + .dw 0xedc0, 0xc038, 0xedff, 0xc038, 0x21, 0 + .dw 0xee40, 0xc038, 0xee7f, 0xc038, 0x21, 0 + .dw 0xeec0, 0xc038, 0xeeff, 0xc038, 0x21, 0 + .dw 0xef40, 0xc038, 0xef7f, 0xc038, 0x21, 0 + .dw 0xefc0, 0xc038, 0xefff, 0xc038, 0x21, 0 + .dw 0xf040, 0xc038, 0xf07f, 0xc038, 0x21, 0 + .dw 0xf0c0, 0xc038, 0xf0ff, 0xc038, 0x21, 0 + .dw 0xf140, 0xc038, 0xf17f, 0xc038, 0x21, 0 + .dw 0xf1c0, 0xc038, 0xf1ff, 0xc038, 0x21, 0 + .dw 0xf240, 0xc038, 0xf27f, 0xc038, 0x21, 0 + .dw 0xf2c0, 0xc038, 0xf2ff, 0xc038, 0x21, 0 + .dw 0xf340, 0xc038, 0xf37f, 0xc038, 0x21, 0 + .dw 0xf3c0, 0xc038, 0xf3ff, 0xc038, 0x21, 0 + .dw 0xf440, 0xc038, 0xf47f, 0xc038, 0x21, 0 + .dw 0xf4c0, 0xc038, 0xf4ff, 0xc038, 0x21, 0 + .dw 0xf540, 0xc038, 0xf57f, 0xc038, 0x21, 0 + .dw 0xf5c0, 0xc038, 0xf5ff, 0xc038, 0x21, 0 + .dw 0xf640, 0xc038, 0xf67f, 0xc038, 0x21, 0 + .dw 0xf6c0, 0xc038, 0xf6ff, 0xc038, 0x21, 0 + .dw 0xf740, 0xc038, 0xf77f, 0xc038, 0x21, 0 + .dw 0xf7c0, 0xc038, 0xf7ff, 0xc038, 0x21, 0 + .dw 0xf840, 0xc038, 0xf87f, 0xc038, 0x21, 0 + .dw 0xf8c0, 0xc038, 0xf8ff, 0xc038, 0x21, 0 + .dw 0xf940, 0xc038, 0xf97f, 0xc038, 0x21, 0 + .dw 0xf9c0, 0xc038, 0x1fff, 0xc039, 0x21, 0 + .dw 0x2040, 0xc039, 0x207f, 0xc039, 0x21, 0 + .dw 0x20c0, 0xc039, 0x20ff, 0xc039, 0x21, 0 + .dw 0x2140, 0xc039, 0x217f, 0xc039, 0x21, 0 + .dw 0x21c0, 0xc039, 0x21ff, 0xc039, 0x21, 0 + .dw 0x2240, 0xc039, 0x227f, 0xc039, 0x21, 0 + .dw 0x22c0, 0xc039, 0x22ff, 0xc039, 0x21, 0 + .dw 0x2340, 0xc039, 0x237f, 0xc039, 0x21, 0 + .dw 0x23c0, 0xc039, 0x23ff, 0xc039, 0x21, 0 + .dw 0x2440, 0xc039, 0x247f, 0xc039, 0x21, 0 + .dw 0x24c0, 0xc039, 0x24ff, 0xc039, 0x21, 0 + .dw 0x2540, 0xc039, 0x257f, 0xc039, 0x21, 0 + .dw 0x25c0, 0xc039, 0x25ff, 0xc039, 0x21, 0 + .dw 0x2640, 0xc039, 0x267f, 0xc039, 0x21, 0 + .dw 0x26c0, 0xc039, 0x26ff, 0xc039, 0x21, 0 + .dw 0x2740, 0xc039, 0x277f, 0xc039, 0x21, 0 + .dw 0x27c0, 0xc039, 0x27ff, 0xc039, 0x21, 0 + .dw 0x2840, 0xc039, 0x287f, 0xc039, 0x21, 0 + .dw 0x28c0, 0xc039, 0x28ff, 0xc039, 0x21, 0 + .dw 0x2940, 0xc039, 0x297f, 0xc039, 0x21, 0 + .dw 0x29c0, 0xc039, 0x29ff, 0xc039, 0x21, 0 + .dw 0x2a40, 0xc039, 0x2a7f, 0xc039, 0x21, 0 + .dw 0x2ac0, 0xc039, 0x2aff, 0xc039, 0x21, 0 + .dw 0x2b40, 0xc039, 0x2b7f, 0xc039, 0x21, 0 + .dw 0x2bc0, 0xc039, 0x2bff, 0xc039, 0x21, 0 + .dw 0x2c40, 0xc039, 0x2c7f, 0xc039, 0x21, 0 + .dw 0x2cc0, 0xc039, 0x2cff, 0xc039, 0x21, 0 + .dw 0x2d40, 0xc039, 0x2d7f, 0xc039, 0x21, 0 + .dw 0x2dc0, 0xc039, 0x2dff, 0xc039, 0x21, 0 + .dw 0x2e40, 0xc039, 0x2e7f, 0xc039, 0x21, 0 + .dw 0x2ec0, 0xc039, 0x2eff, 0xc039, 0x21, 0 + .dw 0x2f40, 0xc039, 0x2f7f, 0xc039, 0x21, 0 + .dw 0x2fc0, 0xc039, 0x2fff, 0xc039, 0x21, 0 + .dw 0x3040, 0xc039, 0x307f, 0xc039, 0x21, 0 + .dw 0x30c0, 0xc039, 0x30ff, 0xc039, 0x21, 0 + .dw 0x3140, 0xc039, 0x317f, 0xc039, 0x21, 0 + .dw 0x31c0, 0xc039, 0x31ff, 0xc039, 0x21, 0 + .dw 0x3240, 0xc039, 0x327f, 0xc039, 0x21, 0 + .dw 0x32c0, 0xc039, 0x32ff, 0xc039, 0x21, 0 + .dw 0x3340, 0xc039, 0x337f, 0xc039, 0x21, 0 + .dw 0x33c0, 0xc039, 0x33ff, 0xc039, 0x21, 0 + .dw 0x3440, 0xc039, 0x347f, 0xc039, 0x21, 0 + .dw 0x34c0, 0xc039, 0x34ff, 0xc039, 0x21, 0 + .dw 0x3540, 0xc039, 0x357f, 0xc039, 0x21, 0 + .dw 0x35c0, 0xc039, 0x35ff, 0xc039, 0x21, 0 + .dw 0x3640, 0xc039, 0x367f, 0xc039, 0x21, 0 + .dw 0x36c0, 0xc039, 0x36ff, 0xc039, 0x21, 0 + .dw 0x3740, 0xc039, 0x377f, 0xc039, 0x21, 0 + .dw 0x37c0, 0xc039, 0x37ff, 0xc039, 0x21, 0 + .dw 0x3840, 0xc039, 0x387f, 0xc039, 0x21, 0 + .dw 0x38c0, 0xc039, 0x38ff, 0xc039, 0x21, 0 + .dw 0x3940, 0xc039, 0x397f, 0xc039, 0x21, 0 + .dw 0x39c0, 0xc039, 0x5fff, 0xc039, 0x21, 0 + .dw 0x6040, 0xc039, 0x607f, 0xc039, 0x21, 0 + .dw 0x60c0, 0xc039, 0x60ff, 0xc039, 0x21, 0 + .dw 0x6140, 0xc039, 0x617f, 0xc039, 0x21, 0 + .dw 0x61c0, 0xc039, 0x61ff, 0xc039, 0x21, 0 + .dw 0x6240, 0xc039, 0x627f, 0xc039, 0x21, 0 + .dw 0x62c0, 0xc039, 0x62ff, 0xc039, 0x21, 0 + .dw 0x6340, 0xc039, 0x637f, 0xc039, 0x21, 0 + .dw 0x63c0, 0xc039, 0x63ff, 0xc039, 0x21, 0 + .dw 0x6440, 0xc039, 0x647f, 0xc039, 0x21, 0 + .dw 0x64c0, 0xc039, 0x64ff, 0xc039, 0x21, 0 + .dw 0x6540, 0xc039, 0x657f, 0xc039, 0x21, 0 + .dw 0x65c0, 0xc039, 0x65ff, 0xc039, 0x21, 0 + .dw 0x6640, 0xc039, 0x667f, 0xc039, 0x21, 0 + .dw 0x66c0, 0xc039, 0x66ff, 0xc039, 0x21, 0 + .dw 0x6740, 0xc039, 0x677f, 0xc039, 0x21, 0 + .dw 0x67c0, 0xc039, 0x67ff, 0xc039, 0x21, 0 + .dw 0x6840, 0xc039, 0x687f, 0xc039, 0x21, 0 + .dw 0x68c0, 0xc039, 0x68ff, 0xc039, 0x21, 0 + .dw 0x6940, 0xc039, 0x697f, 0xc039, 0x21, 0 + .dw 0x69c0, 0xc039, 0x69ff, 0xc039, 0x21, 0 + .dw 0x6a40, 0xc039, 0x6a7f, 0xc039, 0x21, 0 + .dw 0x6ac0, 0xc039, 0x6aff, 0xc039, 0x21, 0 + .dw 0x6b40, 0xc039, 0x6b7f, 0xc039, 0x21, 0 + .dw 0x6bc0, 0xc039, 0x6bff, 0xc039, 0x21, 0 + .dw 0x6c40, 0xc039, 0x6c7f, 0xc039, 0x21, 0 + .dw 0x6cc0, 0xc039, 0x6cff, 0xc039, 0x21, 0 + .dw 0x6d40, 0xc039, 0x6d7f, 0xc039, 0x21, 0 + .dw 0x6dc0, 0xc039, 0x6dff, 0xc039, 0x21, 0 + .dw 0x6e40, 0xc039, 0x6e7f, 0xc039, 0x21, 0 + .dw 0x6ec0, 0xc039, 0x6eff, 0xc039, 0x21, 0 + .dw 0x6f40, 0xc039, 0x6f7f, 0xc039, 0x21, 0 + .dw 0x6fc0, 0xc039, 0x6fff, 0xc039, 0x21, 0 + .dw 0x7040, 0xc039, 0x707f, 0xc039, 0x21, 0 + .dw 0x70c0, 0xc039, 0x70ff, 0xc039, 0x21, 0 + .dw 0x7140, 0xc039, 0x717f, 0xc039, 0x21, 0 + .dw 0x71c0, 0xc039, 0x71ff, 0xc039, 0x21, 0 + .dw 0x7240, 0xc039, 0x727f, 0xc039, 0x21, 0 + .dw 0x72c0, 0xc039, 0x72ff, 0xc039, 0x21, 0 + .dw 0x7340, 0xc039, 0x737f, 0xc039, 0x21, 0 + .dw 0x73c0, 0xc039, 0x73ff, 0xc039, 0x21, 0 + .dw 0x7440, 0xc039, 0x747f, 0xc039, 0x21, 0 + .dw 0x74c0, 0xc039, 0x74ff, 0xc039, 0x21, 0 + .dw 0x7540, 0xc039, 0x757f, 0xc039, 0x21, 0 + .dw 0x75c0, 0xc039, 0x75ff, 0xc039, 0x21, 0 + .dw 0x7640, 0xc039, 0x767f, 0xc039, 0x21, 0 + .dw 0x76c0, 0xc039, 0x76ff, 0xc039, 0x21, 0 + .dw 0x7740, 0xc039, 0x777f, 0xc039, 0x21, 0 + .dw 0x77c0, 0xc039, 0x77ff, 0xc039, 0x21, 0 + .dw 0x7840, 0xc039, 0x787f, 0xc039, 0x21, 0 + .dw 0x78c0, 0xc039, 0x78ff, 0xc039, 0x21, 0 + .dw 0x7940, 0xc039, 0x797f, 0xc039, 0x21, 0 + .dw 0x79c0, 0xc039, 0x9fff, 0xc039, 0x21, 0 + .dw 0xa040, 0xc039, 0xa07f, 0xc039, 0x21, 0 + .dw 0xa0c0, 0xc039, 0xa0ff, 0xc039, 0x21, 0 + .dw 0xa140, 0xc039, 0xa17f, 0xc039, 0x21, 0 + .dw 0xa1c0, 0xc039, 0xa1ff, 0xc039, 0x21, 0 + .dw 0xa240, 0xc039, 0xa27f, 0xc039, 0x21, 0 + .dw 0xa2c0, 0xc039, 0xa2ff, 0xc039, 0x21, 0 + .dw 0xa340, 0xc039, 0xa37f, 0xc039, 0x21, 0 + .dw 0xa3c0, 0xc039, 0xa3ff, 0xc039, 0x21, 0 + .dw 0xa440, 0xc039, 0xa47f, 0xc039, 0x21, 0 + .dw 0xa4c0, 0xc039, 0xa4ff, 0xc039, 0x21, 0 + .dw 0xa540, 0xc039, 0xa57f, 0xc039, 0x21, 0 + .dw 0xa5c0, 0xc039, 0xa5ff, 0xc039, 0x21, 0 + .dw 0xa640, 0xc039, 0xa67f, 0xc039, 0x21, 0 + .dw 0xa6c0, 0xc039, 0xa6ff, 0xc039, 0x21, 0 + .dw 0xa740, 0xc039, 0xa77f, 0xc039, 0x21, 0 + .dw 0xa7c0, 0xc039, 0xa7ff, 0xc039, 0x21, 0 + .dw 0xa840, 0xc039, 0xa87f, 0xc039, 0x21, 0 + .dw 0xa8c0, 0xc039, 0xa8ff, 0xc039, 0x21, 0 + .dw 0xa940, 0xc039, 0xa97f, 0xc039, 0x21, 0 + .dw 0xa9c0, 0xc039, 0xa9ff, 0xc039, 0x21, 0 + .dw 0xaa40, 0xc039, 0xaa7f, 0xc039, 0x21, 0 + .dw 0xaac0, 0xc039, 0xaaff, 0xc039, 0x21, 0 + .dw 0xab40, 0xc039, 0xab7f, 0xc039, 0x21, 0 + .dw 0xabc0, 0xc039, 0xabff, 0xc039, 0x21, 0 + .dw 0xac40, 0xc039, 0xac7f, 0xc039, 0x21, 0 + .dw 0xacc0, 0xc039, 0xacff, 0xc039, 0x21, 0 + .dw 0xad40, 0xc039, 0xad7f, 0xc039, 0x21, 0 + .dw 0xadc0, 0xc039, 0xadff, 0xc039, 0x21, 0 + .dw 0xae40, 0xc039, 0xae7f, 0xc039, 0x21, 0 + .dw 0xaec0, 0xc039, 0xaeff, 0xc039, 0x21, 0 + .dw 0xaf40, 0xc039, 0xaf7f, 0xc039, 0x21, 0 + .dw 0xafc0, 0xc039, 0xafff, 0xc039, 0x21, 0 + .dw 0xb040, 0xc039, 0xb07f, 0xc039, 0x21, 0 + .dw 0xb0c0, 0xc039, 0xb0ff, 0xc039, 0x21, 0 + .dw 0xb140, 0xc039, 0xb17f, 0xc039, 0x21, 0 + .dw 0xb1c0, 0xc039, 0xb1ff, 0xc039, 0x21, 0 + .dw 0xb240, 0xc039, 0xb27f, 0xc039, 0x21, 0 + .dw 0xb2c0, 0xc039, 0xb2ff, 0xc039, 0x21, 0 + .dw 0xb340, 0xc039, 0xb37f, 0xc039, 0x21, 0 + .dw 0xb3c0, 0xc039, 0xb3ff, 0xc039, 0x21, 0 + .dw 0xb440, 0xc039, 0xb47f, 0xc039, 0x21, 0 + .dw 0xb4c0, 0xc039, 0xb4ff, 0xc039, 0x21, 0 + .dw 0xb540, 0xc039, 0xb57f, 0xc039, 0x21, 0 + .dw 0xb5c0, 0xc039, 0xb5ff, 0xc039, 0x21, 0 + .dw 0xb640, 0xc039, 0xb67f, 0xc039, 0x21, 0 + .dw 0xb6c0, 0xc039, 0xb6ff, 0xc039, 0x21, 0 + .dw 0xb740, 0xc039, 0xb77f, 0xc039, 0x21, 0 + .dw 0xb7c0, 0xc039, 0xb7ff, 0xc039, 0x21, 0 + .dw 0xb840, 0xc039, 0xb87f, 0xc039, 0x21, 0 + .dw 0xb8c0, 0xc039, 0xb8ff, 0xc039, 0x21, 0 + .dw 0xb940, 0xc039, 0xb97f, 0xc039, 0x21, 0 + .dw 0xb9c0, 0xc039, 0xdfff, 0xc039, 0x21, 0 + .dw 0xe040, 0xc039, 0xe07f, 0xc039, 0x21, 0 + .dw 0xe0c0, 0xc039, 0xe0ff, 0xc039, 0x21, 0 + .dw 0xe140, 0xc039, 0xe17f, 0xc039, 0x21, 0 + .dw 0xe1c0, 0xc039, 0xe1ff, 0xc039, 0x21, 0 + .dw 0xe240, 0xc039, 0xe27f, 0xc039, 0x21, 0 + .dw 0xe2c0, 0xc039, 0xe2ff, 0xc039, 0x21, 0 + .dw 0xe340, 0xc039, 0xe37f, 0xc039, 0x21, 0 + .dw 0xe3c0, 0xc039, 0xe3ff, 0xc039, 0x21, 0 + .dw 0xe440, 0xc039, 0xe47f, 0xc039, 0x21, 0 + .dw 0xe4c0, 0xc039, 0xe4ff, 0xc039, 0x21, 0 + .dw 0xe540, 0xc039, 0xe57f, 0xc039, 0x21, 0 + .dw 0xe5c0, 0xc039, 0xe5ff, 0xc039, 0x21, 0 + .dw 0xe640, 0xc039, 0xe67f, 0xc039, 0x21, 0 + .dw 0xe6c0, 0xc039, 0xe6ff, 0xc039, 0x21, 0 + .dw 0xe740, 0xc039, 0xe77f, 0xc039, 0x21, 0 + .dw 0xe7c0, 0xc039, 0xe7ff, 0xc039, 0x21, 0 + .dw 0xe840, 0xc039, 0xe87f, 0xc039, 0x21, 0 + .dw 0xe8c0, 0xc039, 0xe8ff, 0xc039, 0x21, 0 + .dw 0xe940, 0xc039, 0xe97f, 0xc039, 0x21, 0 + .dw 0xe9c0, 0xc039, 0xe9ff, 0xc039, 0x21, 0 + .dw 0xea40, 0xc039, 0xea7f, 0xc039, 0x21, 0 + .dw 0xeac0, 0xc039, 0xeaff, 0xc039, 0x21, 0 + .dw 0xeb40, 0xc039, 0xeb7f, 0xc039, 0x21, 0 + .dw 0xebc0, 0xc039, 0xebff, 0xc039, 0x21, 0 + .dw 0xec40, 0xc039, 0xec7f, 0xc039, 0x21, 0 + .dw 0xecc0, 0xc039, 0xecff, 0xc039, 0x21, 0 + .dw 0xed40, 0xc039, 0xed7f, 0xc039, 0x21, 0 + .dw 0xedc0, 0xc039, 0xedff, 0xc039, 0x21, 0 + .dw 0xee40, 0xc039, 0xee7f, 0xc039, 0x21, 0 + .dw 0xeec0, 0xc039, 0xeeff, 0xc039, 0x21, 0 + .dw 0xef40, 0xc039, 0xef7f, 0xc039, 0x21, 0 + .dw 0xefc0, 0xc039, 0xefff, 0xc039, 0x21, 0 + .dw 0xf040, 0xc039, 0xf07f, 0xc039, 0x21, 0 + .dw 0xf0c0, 0xc039, 0xf0ff, 0xc039, 0x21, 0 + .dw 0xf140, 0xc039, 0xf17f, 0xc039, 0x21, 0 + .dw 0xf1c0, 0xc039, 0xf1ff, 0xc039, 0x21, 0 + .dw 0xf240, 0xc039, 0xf27f, 0xc039, 0x21, 0 + .dw 0xf2c0, 0xc039, 0xf2ff, 0xc039, 0x21, 0 + .dw 0xf340, 0xc039, 0xf37f, 0xc039, 0x21, 0 + .dw 0xf3c0, 0xc039, 0xf3ff, 0xc039, 0x21, 0 + .dw 0xf440, 0xc039, 0xf47f, 0xc039, 0x21, 0 + .dw 0xf4c0, 0xc039, 0xf4ff, 0xc039, 0x21, 0 + .dw 0xf540, 0xc039, 0xf57f, 0xc039, 0x21, 0 + .dw 0xf5c0, 0xc039, 0xf5ff, 0xc039, 0x21, 0 + .dw 0xf640, 0xc039, 0xf67f, 0xc039, 0x21, 0 + .dw 0xf6c0, 0xc039, 0xf6ff, 0xc039, 0x21, 0 + .dw 0xf740, 0xc039, 0xf77f, 0xc039, 0x21, 0 + .dw 0xf7c0, 0xc039, 0xf7ff, 0xc039, 0x21, 0 + .dw 0xf840, 0xc039, 0xf87f, 0xc039, 0x21, 0 + .dw 0xf8c0, 0xc039, 0xf8ff, 0xc039, 0x21, 0 + .dw 0xf940, 0xc039, 0xf97f, 0xc039, 0x21, 0 + .dw 0xf9c0, 0xc039, 0x1fff, 0xc03a, 0x21, 0 + .dw 0x2040, 0xc03a, 0x207f, 0xc03a, 0x21, 0 + .dw 0x20c0, 0xc03a, 0x20ff, 0xc03a, 0x21, 0 + .dw 0x2140, 0xc03a, 0x217f, 0xc03a, 0x21, 0 + .dw 0x21c0, 0xc03a, 0x21ff, 0xc03a, 0x21, 0 + .dw 0x2240, 0xc03a, 0x227f, 0xc03a, 0x21, 0 + .dw 0x22c0, 0xc03a, 0x22ff, 0xc03a, 0x21, 0 + .dw 0x2340, 0xc03a, 0x237f, 0xc03a, 0x21, 0 + .dw 0x23c0, 0xc03a, 0x23ff, 0xc03a, 0x21, 0 + .dw 0x2440, 0xc03a, 0x247f, 0xc03a, 0x21, 0 + .dw 0x24c0, 0xc03a, 0x24ff, 0xc03a, 0x21, 0 + .dw 0x2540, 0xc03a, 0x257f, 0xc03a, 0x21, 0 + .dw 0x25c0, 0xc03a, 0x25ff, 0xc03a, 0x21, 0 + .dw 0x2640, 0xc03a, 0x267f, 0xc03a, 0x21, 0 + .dw 0x26c0, 0xc03a, 0x26ff, 0xc03a, 0x21, 0 + .dw 0x2740, 0xc03a, 0x277f, 0xc03a, 0x21, 0 + .dw 0x27c0, 0xc03a, 0x27ff, 0xc03a, 0x21, 0 + .dw 0x2840, 0xc03a, 0x287f, 0xc03a, 0x21, 0 + .dw 0x28c0, 0xc03a, 0x28ff, 0xc03a, 0x21, 0 + .dw 0x2940, 0xc03a, 0x297f, 0xc03a, 0x21, 0 + .dw 0x29c0, 0xc03a, 0x29ff, 0xc03a, 0x21, 0 + .dw 0x2a40, 0xc03a, 0x2a7f, 0xc03a, 0x21, 0 + .dw 0x2ac0, 0xc03a, 0x2aff, 0xc03a, 0x21, 0 + .dw 0x2b40, 0xc03a, 0x2b7f, 0xc03a, 0x21, 0 + .dw 0x2bc0, 0xc03a, 0x2bff, 0xc03a, 0x21, 0 + .dw 0x2c40, 0xc03a, 0x2c7f, 0xc03a, 0x21, 0 + .dw 0x2cc0, 0xc03a, 0x2cff, 0xc03a, 0x21, 0 + .dw 0x2d40, 0xc03a, 0x2d7f, 0xc03a, 0x21, 0 + .dw 0x2dc0, 0xc03a, 0x2dff, 0xc03a, 0x21, 0 + .dw 0x2e40, 0xc03a, 0x2e7f, 0xc03a, 0x21, 0 + .dw 0x2ec0, 0xc03a, 0x2eff, 0xc03a, 0x21, 0 + .dw 0x2f40, 0xc03a, 0x2f7f, 0xc03a, 0x21, 0 + .dw 0x2fc0, 0xc03a, 0x2fff, 0xc03a, 0x21, 0 + .dw 0x3040, 0xc03a, 0x307f, 0xc03a, 0x21, 0 + .dw 0x30c0, 0xc03a, 0x30ff, 0xc03a, 0x21, 0 + .dw 0x3140, 0xc03a, 0x317f, 0xc03a, 0x21, 0 + .dw 0x31c0, 0xc03a, 0x31ff, 0xc03a, 0x21, 0 + .dw 0x3240, 0xc03a, 0x327f, 0xc03a, 0x21, 0 + .dw 0x32c0, 0xc03a, 0x32ff, 0xc03a, 0x21, 0 + .dw 0x3340, 0xc03a, 0x337f, 0xc03a, 0x21, 0 + .dw 0x33c0, 0xc03a, 0x33ff, 0xc03a, 0x21, 0 + .dw 0x3440, 0xc03a, 0x347f, 0xc03a, 0x21, 0 + .dw 0x34c0, 0xc03a, 0x34ff, 0xc03a, 0x21, 0 + .dw 0x3540, 0xc03a, 0x357f, 0xc03a, 0x21, 0 + .dw 0x35c0, 0xc03a, 0x35ff, 0xc03a, 0x21, 0 + .dw 0x3640, 0xc03a, 0x367f, 0xc03a, 0x21, 0 + .dw 0x36c0, 0xc03a, 0x36ff, 0xc03a, 0x21, 0 + .dw 0x3740, 0xc03a, 0x377f, 0xc03a, 0x21, 0 + .dw 0x37c0, 0xc03a, 0x37ff, 0xc03a, 0x21, 0 + .dw 0x3840, 0xc03a, 0x387f, 0xc03a, 0x21, 0 + .dw 0x38c0, 0xc03a, 0x38ff, 0xc03a, 0x21, 0 + .dw 0x3940, 0xc03a, 0x397f, 0xc03a, 0x21, 0 + .dw 0x39c0, 0xc03a, 0x5fff, 0xc03a, 0x21, 0 + .dw 0x6040, 0xc03a, 0x607f, 0xc03a, 0x21, 0 + .dw 0x60c0, 0xc03a, 0x60ff, 0xc03a, 0x21, 0 + .dw 0x6140, 0xc03a, 0x617f, 0xc03a, 0x21, 0 + .dw 0x61c0, 0xc03a, 0x61ff, 0xc03a, 0x21, 0 + .dw 0x6240, 0xc03a, 0x627f, 0xc03a, 0x21, 0 + .dw 0x62c0, 0xc03a, 0x62ff, 0xc03a, 0x21, 0 + .dw 0x6340, 0xc03a, 0x637f, 0xc03a, 0x21, 0 + .dw 0x63c0, 0xc03a, 0x63ff, 0xc03a, 0x21, 0 + .dw 0x6440, 0xc03a, 0x647f, 0xc03a, 0x21, 0 + .dw 0x64c0, 0xc03a, 0x64ff, 0xc03a, 0x21, 0 + .dw 0x6540, 0xc03a, 0x657f, 0xc03a, 0x21, 0 + .dw 0x65c0, 0xc03a, 0x65ff, 0xc03a, 0x21, 0 + .dw 0x6640, 0xc03a, 0x667f, 0xc03a, 0x21, 0 + .dw 0x66c0, 0xc03a, 0x66ff, 0xc03a, 0x21, 0 + .dw 0x6740, 0xc03a, 0x677f, 0xc03a, 0x21, 0 + .dw 0x67c0, 0xc03a, 0x67ff, 0xc03a, 0x21, 0 + .dw 0x6840, 0xc03a, 0x687f, 0xc03a, 0x21, 0 + .dw 0x68c0, 0xc03a, 0x68ff, 0xc03a, 0x21, 0 + .dw 0x6940, 0xc03a, 0x697f, 0xc03a, 0x21, 0 + .dw 0x69c0, 0xc03a, 0x69ff, 0xc03a, 0x21, 0 + .dw 0x6a40, 0xc03a, 0x6a7f, 0xc03a, 0x21, 0 + .dw 0x6ac0, 0xc03a, 0x6aff, 0xc03a, 0x21, 0 + .dw 0x6b40, 0xc03a, 0x6b7f, 0xc03a, 0x21, 0 + .dw 0x6bc0, 0xc03a, 0x6bff, 0xc03a, 0x21, 0 + .dw 0x6c40, 0xc03a, 0x6c7f, 0xc03a, 0x21, 0 + .dw 0x6cc0, 0xc03a, 0x6cff, 0xc03a, 0x21, 0 + .dw 0x6d40, 0xc03a, 0x6d7f, 0xc03a, 0x21, 0 + .dw 0x6dc0, 0xc03a, 0x6dff, 0xc03a, 0x21, 0 + .dw 0x6e40, 0xc03a, 0x6e7f, 0xc03a, 0x21, 0 + .dw 0x6ec0, 0xc03a, 0x6eff, 0xc03a, 0x21, 0 + .dw 0x6f40, 0xc03a, 0x6f7f, 0xc03a, 0x21, 0 + .dw 0x6fc0, 0xc03a, 0x6fff, 0xc03a, 0x21, 0 + .dw 0x7040, 0xc03a, 0x707f, 0xc03a, 0x21, 0 + .dw 0x70c0, 0xc03a, 0x70ff, 0xc03a, 0x21, 0 + .dw 0x7140, 0xc03a, 0x717f, 0xc03a, 0x21, 0 + .dw 0x71c0, 0xc03a, 0x71ff, 0xc03a, 0x21, 0 + .dw 0x7240, 0xc03a, 0x727f, 0xc03a, 0x21, 0 + .dw 0x72c0, 0xc03a, 0x72ff, 0xc03a, 0x21, 0 + .dw 0x7340, 0xc03a, 0x737f, 0xc03a, 0x21, 0 + .dw 0x73c0, 0xc03a, 0x73ff, 0xc03a, 0x21, 0 + .dw 0x7440, 0xc03a, 0x747f, 0xc03a, 0x21, 0 + .dw 0x74c0, 0xc03a, 0x74ff, 0xc03a, 0x21, 0 + .dw 0x7540, 0xc03a, 0x757f, 0xc03a, 0x21, 0 + .dw 0x75c0, 0xc03a, 0x75ff, 0xc03a, 0x21, 0 + .dw 0x7640, 0xc03a, 0x767f, 0xc03a, 0x21, 0 + .dw 0x76c0, 0xc03a, 0x76ff, 0xc03a, 0x21, 0 + .dw 0x7740, 0xc03a, 0x777f, 0xc03a, 0x21, 0 + .dw 0x77c0, 0xc03a, 0x77ff, 0xc03a, 0x21, 0 + .dw 0x7840, 0xc03a, 0x787f, 0xc03a, 0x21, 0 + .dw 0x78c0, 0xc03a, 0x78ff, 0xc03a, 0x21, 0 + .dw 0x7940, 0xc03a, 0x797f, 0xc03a, 0x21, 0 + .dw 0x79c0, 0xc03a, 0x9fff, 0xc03a, 0x21, 0 + .dw 0xa040, 0xc03a, 0xa07f, 0xc03a, 0x21, 0 + .dw 0xa0c0, 0xc03a, 0xa0ff, 0xc03a, 0x21, 0 + .dw 0xa140, 0xc03a, 0xa17f, 0xc03a, 0x21, 0 + .dw 0xa1c0, 0xc03a, 0xa1ff, 0xc03a, 0x21, 0 + .dw 0xa240, 0xc03a, 0xa27f, 0xc03a, 0x21, 0 + .dw 0xa2c0, 0xc03a, 0xa2ff, 0xc03a, 0x21, 0 + .dw 0xa340, 0xc03a, 0xa37f, 0xc03a, 0x21, 0 + .dw 0xa3c0, 0xc03a, 0xa3ff, 0xc03a, 0x21, 0 + .dw 0xa440, 0xc03a, 0xa47f, 0xc03a, 0x21, 0 + .dw 0xa4c0, 0xc03a, 0xa4ff, 0xc03a, 0x21, 0 + .dw 0xa540, 0xc03a, 0xa57f, 0xc03a, 0x21, 0 + .dw 0xa5c0, 0xc03a, 0xa5ff, 0xc03a, 0x21, 0 + .dw 0xa640, 0xc03a, 0xa67f, 0xc03a, 0x21, 0 + .dw 0xa6c0, 0xc03a, 0xa6ff, 0xc03a, 0x21, 0 + .dw 0xa740, 0xc03a, 0xa77f, 0xc03a, 0x21, 0 + .dw 0xa7c0, 0xc03a, 0xa7ff, 0xc03a, 0x21, 0 + .dw 0xa840, 0xc03a, 0xa87f, 0xc03a, 0x21, 0 + .dw 0xa8c0, 0xc03a, 0xa8ff, 0xc03a, 0x21, 0 + .dw 0xa940, 0xc03a, 0xa97f, 0xc03a, 0x21, 0 + .dw 0xa9c0, 0xc03a, 0xa9ff, 0xc03a, 0x21, 0 + .dw 0xaa40, 0xc03a, 0xaa7f, 0xc03a, 0x21, 0 + .dw 0xaac0, 0xc03a, 0xaaff, 0xc03a, 0x21, 0 + .dw 0xab40, 0xc03a, 0xab7f, 0xc03a, 0x21, 0 + .dw 0xabc0, 0xc03a, 0xabff, 0xc03a, 0x21, 0 + .dw 0xac40, 0xc03a, 0xac7f, 0xc03a, 0x21, 0 + .dw 0xacc0, 0xc03a, 0xacff, 0xc03a, 0x21, 0 + .dw 0xad40, 0xc03a, 0xad7f, 0xc03a, 0x21, 0 + .dw 0xadc0, 0xc03a, 0xadff, 0xc03a, 0x21, 0 + .dw 0xae40, 0xc03a, 0xae7f, 0xc03a, 0x21, 0 + .dw 0xaec0, 0xc03a, 0xaeff, 0xc03a, 0x21, 0 + .dw 0xaf40, 0xc03a, 0xaf7f, 0xc03a, 0x21, 0 + .dw 0xafc0, 0xc03a, 0xafff, 0xc03a, 0x21, 0 + .dw 0xb040, 0xc03a, 0xb07f, 0xc03a, 0x21, 0 + .dw 0xb0c0, 0xc03a, 0xb0ff, 0xc03a, 0x21, 0 + .dw 0xb140, 0xc03a, 0xb17f, 0xc03a, 0x21, 0 + .dw 0xb1c0, 0xc03a, 0xb1ff, 0xc03a, 0x21, 0 + .dw 0xb240, 0xc03a, 0xb27f, 0xc03a, 0x21, 0 + .dw 0xb2c0, 0xc03a, 0xb2ff, 0xc03a, 0x21, 0 + .dw 0xb340, 0xc03a, 0xb37f, 0xc03a, 0x21, 0 + .dw 0xb3c0, 0xc03a, 0xb3ff, 0xc03a, 0x21, 0 + .dw 0xb440, 0xc03a, 0xb47f, 0xc03a, 0x21, 0 + .dw 0xb4c0, 0xc03a, 0xb4ff, 0xc03a, 0x21, 0 + .dw 0xb540, 0xc03a, 0xb57f, 0xc03a, 0x21, 0 + .dw 0xb5c0, 0xc03a, 0xb5ff, 0xc03a, 0x21, 0 + .dw 0xb640, 0xc03a, 0xb67f, 0xc03a, 0x21, 0 + .dw 0xb6c0, 0xc03a, 0xb6ff, 0xc03a, 0x21, 0 + .dw 0xb740, 0xc03a, 0xb77f, 0xc03a, 0x21, 0 + .dw 0xb7c0, 0xc03a, 0xb7ff, 0xc03a, 0x21, 0 + .dw 0xb840, 0xc03a, 0xb87f, 0xc03a, 0x21, 0 + .dw 0xb8c0, 0xc03a, 0xb8ff, 0xc03a, 0x21, 0 + .dw 0xb940, 0xc03a, 0xb97f, 0xc03a, 0x21, 0 + .dw 0xb9c0, 0xc03a, 0xdfff, 0xc03a, 0x21, 0 + .dw 0xe040, 0xc03a, 0xe07f, 0xc03a, 0x21, 0 + .dw 0xe0c0, 0xc03a, 0xe0ff, 0xc03a, 0x21, 0 + .dw 0xe140, 0xc03a, 0xe17f, 0xc03a, 0x21, 0 + .dw 0xe1c0, 0xc03a, 0xe1ff, 0xc03a, 0x21, 0 + .dw 0xe240, 0xc03a, 0xe27f, 0xc03a, 0x21, 0 + .dw 0xe2c0, 0xc03a, 0xe2ff, 0xc03a, 0x21, 0 + .dw 0xe340, 0xc03a, 0xe37f, 0xc03a, 0x21, 0 + .dw 0xe3c0, 0xc03a, 0xe3ff, 0xc03a, 0x21, 0 + .dw 0xe440, 0xc03a, 0xe47f, 0xc03a, 0x21, 0 + .dw 0xe4c0, 0xc03a, 0xe4ff, 0xc03a, 0x21, 0 + .dw 0xe540, 0xc03a, 0xe57f, 0xc03a, 0x21, 0 + .dw 0xe5c0, 0xc03a, 0xe5ff, 0xc03a, 0x21, 0 + .dw 0xe640, 0xc03a, 0xe67f, 0xc03a, 0x21, 0 + .dw 0xe6c0, 0xc03a, 0xe6ff, 0xc03a, 0x21, 0 + .dw 0xe740, 0xc03a, 0xe77f, 0xc03a, 0x21, 0 + .dw 0xe7c0, 0xc03a, 0xe7ff, 0xc03a, 0x21, 0 + .dw 0xe840, 0xc03a, 0xe87f, 0xc03a, 0x21, 0 + .dw 0xe8c0, 0xc03a, 0xe8ff, 0xc03a, 0x21, 0 + .dw 0xe940, 0xc03a, 0xe97f, 0xc03a, 0x21, 0 + .dw 0xe9c0, 0xc03a, 0xe9ff, 0xc03a, 0x21, 0 + .dw 0xea40, 0xc03a, 0xea7f, 0xc03a, 0x21, 0 + .dw 0xeac0, 0xc03a, 0xeaff, 0xc03a, 0x21, 0 + .dw 0xeb40, 0xc03a, 0xeb7f, 0xc03a, 0x21, 0 + .dw 0xebc0, 0xc03a, 0xebff, 0xc03a, 0x21, 0 + .dw 0xec40, 0xc03a, 0xec7f, 0xc03a, 0x21, 0 + .dw 0xecc0, 0xc03a, 0xecff, 0xc03a, 0x21, 0 + .dw 0xed40, 0xc03a, 0xed7f, 0xc03a, 0x21, 0 + .dw 0xedc0, 0xc03a, 0xedff, 0xc03a, 0x21, 0 + .dw 0xee40, 0xc03a, 0xee7f, 0xc03a, 0x21, 0 + .dw 0xeec0, 0xc03a, 0xeeff, 0xc03a, 0x21, 0 + .dw 0xef40, 0xc03a, 0xef7f, 0xc03a, 0x21, 0 + .dw 0xefc0, 0xc03a, 0xefff, 0xc03a, 0x21, 0 + .dw 0xf040, 0xc03a, 0xf07f, 0xc03a, 0x21, 0 + .dw 0xf0c0, 0xc03a, 0xf0ff, 0xc03a, 0x21, 0 + .dw 0xf140, 0xc03a, 0xf17f, 0xc03a, 0x21, 0 + .dw 0xf1c0, 0xc03a, 0xf1ff, 0xc03a, 0x21, 0 + .dw 0xf240, 0xc03a, 0xf27f, 0xc03a, 0x21, 0 + .dw 0xf2c0, 0xc03a, 0xf2ff, 0xc03a, 0x21, 0 + .dw 0xf340, 0xc03a, 0xf37f, 0xc03a, 0x21, 0 + .dw 0xf3c0, 0xc03a, 0xf3ff, 0xc03a, 0x21, 0 + .dw 0xf440, 0xc03a, 0xf47f, 0xc03a, 0x21, 0 + .dw 0xf4c0, 0xc03a, 0xf4ff, 0xc03a, 0x21, 0 + .dw 0xf540, 0xc03a, 0xf57f, 0xc03a, 0x21, 0 + .dw 0xf5c0, 0xc03a, 0xf5ff, 0xc03a, 0x21, 0 + .dw 0xf640, 0xc03a, 0xf67f, 0xc03a, 0x21, 0 + .dw 0xf6c0, 0xc03a, 0xf6ff, 0xc03a, 0x21, 0 + .dw 0xf740, 0xc03a, 0xf77f, 0xc03a, 0x21, 0 + .dw 0xf7c0, 0xc03a, 0xf7ff, 0xc03a, 0x21, 0 + .dw 0xf840, 0xc03a, 0xf87f, 0xc03a, 0x21, 0 + .dw 0xf8c0, 0xc03a, 0xf8ff, 0xc03a, 0x21, 0 + .dw 0xf940, 0xc03a, 0xf97f, 0xc03a, 0x21, 0 + .dw 0xf9c0, 0xc03a, 0xffff, 0xc03b, 0x21, 0 + .dw 0x0040, 0xc03c, 0x007f, 0xc03c, 0x21, 0 + .dw 0x00c0, 0xc03c, 0x00ff, 0xc03c, 0x21, 0 + .dw 0x0140, 0xc03c, 0x017f, 0xc03c, 0x21, 0 + .dw 0x01c0, 0xc03c, 0x01ff, 0xc03c, 0x21, 0 + .dw 0x0240, 0xc03c, 0x027f, 0xc03c, 0x21, 0 + .dw 0x02c0, 0xc03c, 0x02ff, 0xc03c, 0x21, 0 + .dw 0x0340, 0xc03c, 0x037f, 0xc03c, 0x21, 0 + .dw 0x03c0, 0xc03c, 0x03ff, 0xc03c, 0x21, 0 + .dw 0x0440, 0xc03c, 0x047f, 0xc03c, 0x21, 0 + .dw 0x04c0, 0xc03c, 0x04ff, 0xc03c, 0x21, 0 + .dw 0x0540, 0xc03c, 0x057f, 0xc03c, 0x21, 0 + .dw 0x05c0, 0xc03c, 0x05ff, 0xc03c, 0x21, 0 + .dw 0x0640, 0xc03c, 0x067f, 0xc03c, 0x21, 0 + .dw 0x06c0, 0xc03c, 0x06ff, 0xc03c, 0x21, 0 + .dw 0x0740, 0xc03c, 0x077f, 0xc03c, 0x21, 0 + .dw 0x07c0, 0xc03c, 0x07ff, 0xc03c, 0x21, 0 + .dw 0x0840, 0xc03c, 0x087f, 0xc03c, 0x21, 0 + .dw 0x08c0, 0xc03c, 0x08ff, 0xc03c, 0x21, 0 + .dw 0x0940, 0xc03c, 0x097f, 0xc03c, 0x21, 0 + .dw 0x09c0, 0xc03c, 0x09ff, 0xc03c, 0x21, 0 + .dw 0x0a40, 0xc03c, 0x0a7f, 0xc03c, 0x21, 0 + .dw 0x0ac0, 0xc03c, 0x0aff, 0xc03c, 0x21, 0 + .dw 0x0b40, 0xc03c, 0x0b7f, 0xc03c, 0x21, 0 + .dw 0x0bc0, 0xc03c, 0x0bff, 0xc03c, 0x21, 0 + .dw 0x0c40, 0xc03c, 0x0c7f, 0xc03c, 0x21, 0 + .dw 0x0cc0, 0xc03c, 0x0cff, 0xc03c, 0x21, 0 + .dw 0x0d40, 0xc03c, 0x0d7f, 0xc03c, 0x21, 0 + .dw 0x0dc0, 0xc03c, 0x0dff, 0xc03c, 0x21, 0 + .dw 0x0e40, 0xc03c, 0x0e7f, 0xc03c, 0x21, 0 + .dw 0x0ec0, 0xc03c, 0x0eff, 0xc03c, 0x21, 0 + .dw 0x0f40, 0xc03c, 0x0f7f, 0xc03c, 0x21, 0 + .dw 0x0fc0, 0xc03c, 0x0fff, 0xc03c, 0x21, 0 + .dw 0x1040, 0xc03c, 0x107f, 0xc03c, 0x21, 0 + .dw 0x10c0, 0xc03c, 0x10ff, 0xc03c, 0x21, 0 + .dw 0x1140, 0xc03c, 0x117f, 0xc03c, 0x21, 0 + .dw 0x11c0, 0xc03c, 0x11ff, 0xc03c, 0x21, 0 + .dw 0x1240, 0xc03c, 0x127f, 0xc03c, 0x21, 0 + .dw 0x12c0, 0xc03c, 0x12ff, 0xc03c, 0x21, 0 + .dw 0x1340, 0xc03c, 0x137f, 0xc03c, 0x21, 0 + .dw 0x13c0, 0xc03c, 0x13ff, 0xc03c, 0x21, 0 + .dw 0x1440, 0xc03c, 0x147f, 0xc03c, 0x21, 0 + .dw 0x14c0, 0xc03c, 0x14ff, 0xc03c, 0x21, 0 + .dw 0x1540, 0xc03c, 0x157f, 0xc03c, 0x21, 0 + .dw 0x15c0, 0xc03c, 0x15ff, 0xc03c, 0x21, 0 + .dw 0x1640, 0xc03c, 0x167f, 0xc03c, 0x21, 0 + .dw 0x16c0, 0xc03c, 0x16ff, 0xc03c, 0x21, 0 + .dw 0x1740, 0xc03c, 0x177f, 0xc03c, 0x21, 0 + .dw 0x17c0, 0xc03c, 0x17ff, 0xc03c, 0x21, 0 + .dw 0x1840, 0xc03c, 0x187f, 0xc03c, 0x21, 0 + .dw 0x18c0, 0xc03c, 0x18ff, 0xc03c, 0x21, 0 + .dw 0x1940, 0xc03c, 0x197f, 0xc03c, 0x21, 0 + .dw 0x19c0, 0xc03c, 0x1fff, 0xc03c, 0x21, 0 + .dw 0x2040, 0xc03c, 0x207f, 0xc03c, 0x21, 0 + .dw 0x20c0, 0xc03c, 0x20ff, 0xc03c, 0x21, 0 + .dw 0x2140, 0xc03c, 0x217f, 0xc03c, 0x21, 0 + .dw 0x21c0, 0xc03c, 0x21ff, 0xc03c, 0x21, 0 + .dw 0x2240, 0xc03c, 0x227f, 0xc03c, 0x21, 0 + .dw 0x22c0, 0xc03c, 0x22ff, 0xc03c, 0x21, 0 + .dw 0x2340, 0xc03c, 0x237f, 0xc03c, 0x21, 0 + .dw 0x23c0, 0xc03c, 0x23ff, 0xc03c, 0x21, 0 + .dw 0x2440, 0xc03c, 0x247f, 0xc03c, 0x21, 0 + .dw 0x24c0, 0xc03c, 0x24ff, 0xc03c, 0x21, 0 + .dw 0x2540, 0xc03c, 0x257f, 0xc03c, 0x21, 0 + .dw 0x25c0, 0xc03c, 0x25ff, 0xc03c, 0x21, 0 + .dw 0x2640, 0xc03c, 0x267f, 0xc03c, 0x21, 0 + .dw 0x26c0, 0xc03c, 0x26ff, 0xc03c, 0x21, 0 + .dw 0x2740, 0xc03c, 0x277f, 0xc03c, 0x21, 0 + .dw 0x27c0, 0xc03c, 0x27ff, 0xc03c, 0x21, 0 + .dw 0x2840, 0xc03c, 0x287f, 0xc03c, 0x21, 0 + .dw 0x28c0, 0xc03c, 0x28ff, 0xc03c, 0x21, 0 + .dw 0x2940, 0xc03c, 0x297f, 0xc03c, 0x21, 0 + .dw 0x29c0, 0xc03c, 0x29ff, 0xc03c, 0x21, 0 + .dw 0x2a40, 0xc03c, 0x2a7f, 0xc03c, 0x21, 0 + .dw 0x2ac0, 0xc03c, 0x2aff, 0xc03c, 0x21, 0 + .dw 0x2b40, 0xc03c, 0x2b7f, 0xc03c, 0x21, 0 + .dw 0x2bc0, 0xc03c, 0x2bff, 0xc03c, 0x21, 0 + .dw 0x2c40, 0xc03c, 0x2c7f, 0xc03c, 0x21, 0 + .dw 0x2cc0, 0xc03c, 0x2cff, 0xc03c, 0x21, 0 + .dw 0x2d40, 0xc03c, 0x2d7f, 0xc03c, 0x21, 0 + .dw 0x2dc0, 0xc03c, 0x2dff, 0xc03c, 0x21, 0 + .dw 0x2e40, 0xc03c, 0x2e7f, 0xc03c, 0x21, 0 + .dw 0x2ec0, 0xc03c, 0x2eff, 0xc03c, 0x21, 0 + .dw 0x2f40, 0xc03c, 0x2f7f, 0xc03c, 0x21, 0 + .dw 0x2fc0, 0xc03c, 0x2fff, 0xc03c, 0x21, 0 + .dw 0x3040, 0xc03c, 0x307f, 0xc03c, 0x21, 0 + .dw 0x30c0, 0xc03c, 0x30ff, 0xc03c, 0x21, 0 + .dw 0x3140, 0xc03c, 0x317f, 0xc03c, 0x21, 0 + .dw 0x31c0, 0xc03c, 0x31ff, 0xc03c, 0x21, 0 + .dw 0x3240, 0xc03c, 0x327f, 0xc03c, 0x21, 0 + .dw 0x32c0, 0xc03c, 0x32ff, 0xc03c, 0x21, 0 + .dw 0x3340, 0xc03c, 0x337f, 0xc03c, 0x21, 0 + .dw 0x33c0, 0xc03c, 0x33ff, 0xc03c, 0x21, 0 + .dw 0x3440, 0xc03c, 0x347f, 0xc03c, 0x21, 0 + .dw 0x34c0, 0xc03c, 0x34ff, 0xc03c, 0x21, 0 + .dw 0x3540, 0xc03c, 0x357f, 0xc03c, 0x21, 0 + .dw 0x35c0, 0xc03c, 0x35ff, 0xc03c, 0x21, 0 + .dw 0x3640, 0xc03c, 0x367f, 0xc03c, 0x21, 0 + .dw 0x36c0, 0xc03c, 0x36ff, 0xc03c, 0x21, 0 + .dw 0x3740, 0xc03c, 0x377f, 0xc03c, 0x21, 0 + .dw 0x37c0, 0xc03c, 0x37ff, 0xc03c, 0x21, 0 + .dw 0x3840, 0xc03c, 0x387f, 0xc03c, 0x21, 0 + .dw 0x38c0, 0xc03c, 0x38ff, 0xc03c, 0x21, 0 + .dw 0x3940, 0xc03c, 0x397f, 0xc03c, 0x21, 0 + .dw 0x39c0, 0xc03c, 0x3fff, 0xc03c, 0x21, 0 + .dw 0x4040, 0xc03c, 0x407f, 0xc03c, 0x21, 0 + .dw 0x40c0, 0xc03c, 0x40ff, 0xc03c, 0x21, 0 + .dw 0x4140, 0xc03c, 0x417f, 0xc03c, 0x21, 0 + .dw 0x41c0, 0xc03c, 0x41ff, 0xc03c, 0x21, 0 + .dw 0x4240, 0xc03c, 0x427f, 0xc03c, 0x21, 0 + .dw 0x42c0, 0xc03c, 0x42ff, 0xc03c, 0x21, 0 + .dw 0x4340, 0xc03c, 0x437f, 0xc03c, 0x21, 0 + .dw 0x43c0, 0xc03c, 0x43ff, 0xc03c, 0x21, 0 + .dw 0x4440, 0xc03c, 0x447f, 0xc03c, 0x21, 0 + .dw 0x44c0, 0xc03c, 0x44ff, 0xc03c, 0x21, 0 + .dw 0x4540, 0xc03c, 0x457f, 0xc03c, 0x21, 0 + .dw 0x45c0, 0xc03c, 0x45ff, 0xc03c, 0x21, 0 + .dw 0x4640, 0xc03c, 0x467f, 0xc03c, 0x21, 0 + .dw 0x46c0, 0xc03c, 0x46ff, 0xc03c, 0x21, 0 + .dw 0x4740, 0xc03c, 0x477f, 0xc03c, 0x21, 0 + .dw 0x47c0, 0xc03c, 0x47ff, 0xc03c, 0x21, 0 + .dw 0x4840, 0xc03c, 0x487f, 0xc03c, 0x21, 0 + .dw 0x48c0, 0xc03c, 0x48ff, 0xc03c, 0x21, 0 + .dw 0x4940, 0xc03c, 0x497f, 0xc03c, 0x21, 0 + .dw 0x49c0, 0xc03c, 0x49ff, 0xc03c, 0x21, 0 + .dw 0x4a40, 0xc03c, 0x4a7f, 0xc03c, 0x21, 0 + .dw 0x4ac0, 0xc03c, 0x4aff, 0xc03c, 0x21, 0 + .dw 0x4b40, 0xc03c, 0x4b7f, 0xc03c, 0x21, 0 + .dw 0x4bc0, 0xc03c, 0x4bff, 0xc03c, 0x21, 0 + .dw 0x4c40, 0xc03c, 0x4c7f, 0xc03c, 0x21, 0 + .dw 0x4cc0, 0xc03c, 0x4cff, 0xc03c, 0x21, 0 + .dw 0x4d40, 0xc03c, 0x4d7f, 0xc03c, 0x21, 0 + .dw 0x4dc0, 0xc03c, 0x4dff, 0xc03c, 0x21, 0 + .dw 0x4e40, 0xc03c, 0x4e7f, 0xc03c, 0x21, 0 + .dw 0x4ec0, 0xc03c, 0x4eff, 0xc03c, 0x21, 0 + .dw 0x4f40, 0xc03c, 0x4f7f, 0xc03c, 0x21, 0 + .dw 0x4fc0, 0xc03c, 0x4fff, 0xc03c, 0x21, 0 + .dw 0x5040, 0xc03c, 0x507f, 0xc03c, 0x21, 0 + .dw 0x50c0, 0xc03c, 0x50ff, 0xc03c, 0x21, 0 + .dw 0x5140, 0xc03c, 0x517f, 0xc03c, 0x21, 0 + .dw 0x51c0, 0xc03c, 0x51ff, 0xc03c, 0x21, 0 + .dw 0x5240, 0xc03c, 0x527f, 0xc03c, 0x21, 0 + .dw 0x52c0, 0xc03c, 0x52ff, 0xc03c, 0x21, 0 + .dw 0x5340, 0xc03c, 0x537f, 0xc03c, 0x21, 0 + .dw 0x53c0, 0xc03c, 0x53ff, 0xc03c, 0x21, 0 + .dw 0x5440, 0xc03c, 0x547f, 0xc03c, 0x21, 0 + .dw 0x54c0, 0xc03c, 0x54ff, 0xc03c, 0x21, 0 + .dw 0x5540, 0xc03c, 0x557f, 0xc03c, 0x21, 0 + .dw 0x55c0, 0xc03c, 0x55ff, 0xc03c, 0x21, 0 + .dw 0x5640, 0xc03c, 0x567f, 0xc03c, 0x21, 0 + .dw 0x56c0, 0xc03c, 0x56ff, 0xc03c, 0x21, 0 + .dw 0x5740, 0xc03c, 0x577f, 0xc03c, 0x21, 0 + .dw 0x57c0, 0xc03c, 0x57ff, 0xc03c, 0x21, 0 + .dw 0x5840, 0xc03c, 0x587f, 0xc03c, 0x21, 0 + .dw 0x58c0, 0xc03c, 0x58ff, 0xc03c, 0x21, 0 + .dw 0x5940, 0xc03c, 0x597f, 0xc03c, 0x21, 0 + .dw 0x59c0, 0xc03c, 0x5fff, 0xc03c, 0x21, 0 + .dw 0x6040, 0xc03c, 0x607f, 0xc03c, 0x21, 0 + .dw 0x60c0, 0xc03c, 0x60ff, 0xc03c, 0x21, 0 + .dw 0x6140, 0xc03c, 0x617f, 0xc03c, 0x21, 0 + .dw 0x61c0, 0xc03c, 0x61ff, 0xc03c, 0x21, 0 + .dw 0x6240, 0xc03c, 0x627f, 0xc03c, 0x21, 0 + .dw 0x62c0, 0xc03c, 0x62ff, 0xc03c, 0x21, 0 + .dw 0x6340, 0xc03c, 0x637f, 0xc03c, 0x21, 0 + .dw 0x63c0, 0xc03c, 0x63ff, 0xc03c, 0x21, 0 + .dw 0x6440, 0xc03c, 0x647f, 0xc03c, 0x21, 0 + .dw 0x64c0, 0xc03c, 0x64ff, 0xc03c, 0x21, 0 + .dw 0x6540, 0xc03c, 0x657f, 0xc03c, 0x21, 0 + .dw 0x65c0, 0xc03c, 0x65ff, 0xc03c, 0x21, 0 + .dw 0x6640, 0xc03c, 0x667f, 0xc03c, 0x21, 0 + .dw 0x66c0, 0xc03c, 0x66ff, 0xc03c, 0x21, 0 + .dw 0x6740, 0xc03c, 0x677f, 0xc03c, 0x21, 0 + .dw 0x67c0, 0xc03c, 0x67ff, 0xc03c, 0x21, 0 + .dw 0x6840, 0xc03c, 0x687f, 0xc03c, 0x21, 0 + .dw 0x68c0, 0xc03c, 0x68ff, 0xc03c, 0x21, 0 + .dw 0x6940, 0xc03c, 0x697f, 0xc03c, 0x21, 0 + .dw 0x69c0, 0xc03c, 0x69ff, 0xc03c, 0x21, 0 + .dw 0x6a40, 0xc03c, 0x6a7f, 0xc03c, 0x21, 0 + .dw 0x6ac0, 0xc03c, 0x6aff, 0xc03c, 0x21, 0 + .dw 0x6b40, 0xc03c, 0x6b7f, 0xc03c, 0x21, 0 + .dw 0x6bc0, 0xc03c, 0x6bff, 0xc03c, 0x21, 0 + .dw 0x6c40, 0xc03c, 0x6c7f, 0xc03c, 0x21, 0 + .dw 0x6cc0, 0xc03c, 0x6cff, 0xc03c, 0x21, 0 + .dw 0x6d40, 0xc03c, 0x6d7f, 0xc03c, 0x21, 0 + .dw 0x6dc0, 0xc03c, 0x6dff, 0xc03c, 0x21, 0 + .dw 0x6e40, 0xc03c, 0x6e7f, 0xc03c, 0x21, 0 + .dw 0x6ec0, 0xc03c, 0x6eff, 0xc03c, 0x21, 0 + .dw 0x6f40, 0xc03c, 0x6f7f, 0xc03c, 0x21, 0 + .dw 0x6fc0, 0xc03c, 0x6fff, 0xc03c, 0x21, 0 + .dw 0x7040, 0xc03c, 0x707f, 0xc03c, 0x21, 0 + .dw 0x70c0, 0xc03c, 0x70ff, 0xc03c, 0x21, 0 + .dw 0x7140, 0xc03c, 0x717f, 0xc03c, 0x21, 0 + .dw 0x71c0, 0xc03c, 0x71ff, 0xc03c, 0x21, 0 + .dw 0x7240, 0xc03c, 0x727f, 0xc03c, 0x21, 0 + .dw 0x72c0, 0xc03c, 0x72ff, 0xc03c, 0x21, 0 + .dw 0x7340, 0xc03c, 0x737f, 0xc03c, 0x21, 0 + .dw 0x73c0, 0xc03c, 0x73ff, 0xc03c, 0x21, 0 + .dw 0x7440, 0xc03c, 0x747f, 0xc03c, 0x21, 0 + .dw 0x74c0, 0xc03c, 0x74ff, 0xc03c, 0x21, 0 + .dw 0x7540, 0xc03c, 0x757f, 0xc03c, 0x21, 0 + .dw 0x75c0, 0xc03c, 0x75ff, 0xc03c, 0x21, 0 + .dw 0x7640, 0xc03c, 0x767f, 0xc03c, 0x21, 0 + .dw 0x76c0, 0xc03c, 0x76ff, 0xc03c, 0x21, 0 + .dw 0x7740, 0xc03c, 0x777f, 0xc03c, 0x21, 0 + .dw 0x77c0, 0xc03c, 0x77ff, 0xc03c, 0x21, 0 + .dw 0x7840, 0xc03c, 0x787f, 0xc03c, 0x21, 0 + .dw 0x78c0, 0xc03c, 0x78ff, 0xc03c, 0x21, 0 + .dw 0x7940, 0xc03c, 0x797f, 0xc03c, 0x21, 0 + .dw 0x79c0, 0xc03c, 0x7fff, 0xc03c, 0x21, 0 + .dw 0x8040, 0xc03c, 0x807f, 0xc03c, 0x21, 0 + .dw 0x80c0, 0xc03c, 0x80ff, 0xc03c, 0x21, 0 + .dw 0x8140, 0xc03c, 0x817f, 0xc03c, 0x21, 0 + .dw 0x81c0, 0xc03c, 0x81ff, 0xc03c, 0x21, 0 + .dw 0x8240, 0xc03c, 0x827f, 0xc03c, 0x21, 0 + .dw 0x82c0, 0xc03c, 0x82ff, 0xc03c, 0x21, 0 + .dw 0x8340, 0xc03c, 0x837f, 0xc03c, 0x21, 0 + .dw 0x83c0, 0xc03c, 0x83ff, 0xc03c, 0x21, 0 + .dw 0x8440, 0xc03c, 0x847f, 0xc03c, 0x21, 0 + .dw 0x84c0, 0xc03c, 0x84ff, 0xc03c, 0x21, 0 + .dw 0x8540, 0xc03c, 0x857f, 0xc03c, 0x21, 0 + .dw 0x85c0, 0xc03c, 0x85ff, 0xc03c, 0x21, 0 + .dw 0x8640, 0xc03c, 0x867f, 0xc03c, 0x21, 0 + .dw 0x86c0, 0xc03c, 0x86ff, 0xc03c, 0x21, 0 + .dw 0x8740, 0xc03c, 0x877f, 0xc03c, 0x21, 0 + .dw 0x87c0, 0xc03c, 0x87ff, 0xc03c, 0x21, 0 + .dw 0x8840, 0xc03c, 0x887f, 0xc03c, 0x21, 0 + .dw 0x88c0, 0xc03c, 0x88ff, 0xc03c, 0x21, 0 + .dw 0x8940, 0xc03c, 0x897f, 0xc03c, 0x21, 0 + .dw 0x89c0, 0xc03c, 0x89ff, 0xc03c, 0x21, 0 + .dw 0x8a40, 0xc03c, 0x8a7f, 0xc03c, 0x21, 0 + .dw 0x8ac0, 0xc03c, 0x8aff, 0xc03c, 0x21, 0 + .dw 0x8b40, 0xc03c, 0x8b7f, 0xc03c, 0x21, 0 + .dw 0x8bc0, 0xc03c, 0x8bff, 0xc03c, 0x21, 0 + .dw 0x8c40, 0xc03c, 0x8c7f, 0xc03c, 0x21, 0 + .dw 0x8cc0, 0xc03c, 0x8cff, 0xc03c, 0x21, 0 + .dw 0x8d40, 0xc03c, 0x8d7f, 0xc03c, 0x21, 0 + .dw 0x8dc0, 0xc03c, 0x8dff, 0xc03c, 0x21, 0 + .dw 0x8e40, 0xc03c, 0x8e7f, 0xc03c, 0x21, 0 + .dw 0x8ec0, 0xc03c, 0x8eff, 0xc03c, 0x21, 0 + .dw 0x8f40, 0xc03c, 0x8f7f, 0xc03c, 0x21, 0 + .dw 0x8fc0, 0xc03c, 0x8fff, 0xc03c, 0x21, 0 + .dw 0x9040, 0xc03c, 0x907f, 0xc03c, 0x21, 0 + .dw 0x90c0, 0xc03c, 0x90ff, 0xc03c, 0x21, 0 + .dw 0x9140, 0xc03c, 0x917f, 0xc03c, 0x21, 0 + .dw 0x91c0, 0xc03c, 0x91ff, 0xc03c, 0x21, 0 + .dw 0x9240, 0xc03c, 0x927f, 0xc03c, 0x21, 0 + .dw 0x92c0, 0xc03c, 0x92ff, 0xc03c, 0x21, 0 + .dw 0x9340, 0xc03c, 0x937f, 0xc03c, 0x21, 0 + .dw 0x93c0, 0xc03c, 0x93ff, 0xc03c, 0x21, 0 + .dw 0x9440, 0xc03c, 0x947f, 0xc03c, 0x21, 0 + .dw 0x94c0, 0xc03c, 0x94ff, 0xc03c, 0x21, 0 + .dw 0x9540, 0xc03c, 0x957f, 0xc03c, 0x21, 0 + .dw 0x95c0, 0xc03c, 0x95ff, 0xc03c, 0x21, 0 + .dw 0x9640, 0xc03c, 0x967f, 0xc03c, 0x21, 0 + .dw 0x96c0, 0xc03c, 0x96ff, 0xc03c, 0x21, 0 + .dw 0x9740, 0xc03c, 0x977f, 0xc03c, 0x21, 0 + .dw 0x97c0, 0xc03c, 0x97ff, 0xc03c, 0x21, 0 + .dw 0x9840, 0xc03c, 0x987f, 0xc03c, 0x21, 0 + .dw 0x98c0, 0xc03c, 0x98ff, 0xc03c, 0x21, 0 + .dw 0x9940, 0xc03c, 0x997f, 0xc03c, 0x21, 0 + .dw 0x99c0, 0xc03c, 0x9fff, 0xc03c, 0x21, 0 + .dw 0xa040, 0xc03c, 0xa07f, 0xc03c, 0x21, 0 + .dw 0xa0c0, 0xc03c, 0xa0ff, 0xc03c, 0x21, 0 + .dw 0xa140, 0xc03c, 0xa17f, 0xc03c, 0x21, 0 + .dw 0xa1c0, 0xc03c, 0xa1ff, 0xc03c, 0x21, 0 + .dw 0xa240, 0xc03c, 0xa27f, 0xc03c, 0x21, 0 + .dw 0xa2c0, 0xc03c, 0xa2ff, 0xc03c, 0x21, 0 + .dw 0xa340, 0xc03c, 0xa37f, 0xc03c, 0x21, 0 + .dw 0xa3c0, 0xc03c, 0xa3ff, 0xc03c, 0x21, 0 + .dw 0xa440, 0xc03c, 0xa47f, 0xc03c, 0x21, 0 + .dw 0xa4c0, 0xc03c, 0xa4ff, 0xc03c, 0x21, 0 + .dw 0xa540, 0xc03c, 0xa57f, 0xc03c, 0x21, 0 + .dw 0xa5c0, 0xc03c, 0xa5ff, 0xc03c, 0x21, 0 + .dw 0xa640, 0xc03c, 0xa67f, 0xc03c, 0x21, 0 + .dw 0xa6c0, 0xc03c, 0xa6ff, 0xc03c, 0x21, 0 + .dw 0xa740, 0xc03c, 0xa77f, 0xc03c, 0x21, 0 + .dw 0xa7c0, 0xc03c, 0xa7ff, 0xc03c, 0x21, 0 + .dw 0xa840, 0xc03c, 0xa87f, 0xc03c, 0x21, 0 + .dw 0xa8c0, 0xc03c, 0xa8ff, 0xc03c, 0x21, 0 + .dw 0xa940, 0xc03c, 0xa97f, 0xc03c, 0x21, 0 + .dw 0xa9c0, 0xc03c, 0xa9ff, 0xc03c, 0x21, 0 + .dw 0xaa40, 0xc03c, 0xaa7f, 0xc03c, 0x21, 0 + .dw 0xaac0, 0xc03c, 0xaaff, 0xc03c, 0x21, 0 + .dw 0xab40, 0xc03c, 0xab7f, 0xc03c, 0x21, 0 + .dw 0xabc0, 0xc03c, 0xabff, 0xc03c, 0x21, 0 + .dw 0xac40, 0xc03c, 0xac7f, 0xc03c, 0x21, 0 + .dw 0xacc0, 0xc03c, 0xacff, 0xc03c, 0x21, 0 + .dw 0xad40, 0xc03c, 0xad7f, 0xc03c, 0x21, 0 + .dw 0xadc0, 0xc03c, 0xadff, 0xc03c, 0x21, 0 + .dw 0xae40, 0xc03c, 0xae7f, 0xc03c, 0x21, 0 + .dw 0xaec0, 0xc03c, 0xaeff, 0xc03c, 0x21, 0 + .dw 0xaf40, 0xc03c, 0xaf7f, 0xc03c, 0x21, 0 + .dw 0xafc0, 0xc03c, 0xafff, 0xc03c, 0x21, 0 + .dw 0xb040, 0xc03c, 0xb07f, 0xc03c, 0x21, 0 + .dw 0xb0c0, 0xc03c, 0xb0ff, 0xc03c, 0x21, 0 + .dw 0xb140, 0xc03c, 0xb17f, 0xc03c, 0x21, 0 + .dw 0xb1c0, 0xc03c, 0xb1ff, 0xc03c, 0x21, 0 + .dw 0xb240, 0xc03c, 0xb27f, 0xc03c, 0x21, 0 + .dw 0xb2c0, 0xc03c, 0xb2ff, 0xc03c, 0x21, 0 + .dw 0xb340, 0xc03c, 0xb37f, 0xc03c, 0x21, 0 + .dw 0xb3c0, 0xc03c, 0xb3ff, 0xc03c, 0x21, 0 + .dw 0xb440, 0xc03c, 0xb47f, 0xc03c, 0x21, 0 + .dw 0xb4c0, 0xc03c, 0xb4ff, 0xc03c, 0x21, 0 + .dw 0xb540, 0xc03c, 0xb57f, 0xc03c, 0x21, 0 + .dw 0xb5c0, 0xc03c, 0xb5ff, 0xc03c, 0x21, 0 + .dw 0xb640, 0xc03c, 0xb67f, 0xc03c, 0x21, 0 + .dw 0xb6c0, 0xc03c, 0xb6ff, 0xc03c, 0x21, 0 + .dw 0xb740, 0xc03c, 0xb77f, 0xc03c, 0x21, 0 + .dw 0xb7c0, 0xc03c, 0xb7ff, 0xc03c, 0x21, 0 + .dw 0xb840, 0xc03c, 0xb87f, 0xc03c, 0x21, 0 + .dw 0xb8c0, 0xc03c, 0xb8ff, 0xc03c, 0x21, 0 + .dw 0xb940, 0xc03c, 0xb97f, 0xc03c, 0x21, 0 + .dw 0xb9c0, 0xc03c, 0xbfff, 0xc03c, 0x21, 0 + .dw 0xc040, 0xc03c, 0xc07f, 0xc03c, 0x21, 0 + .dw 0xc0c0, 0xc03c, 0xc0ff, 0xc03c, 0x21, 0 + .dw 0xc140, 0xc03c, 0xc17f, 0xc03c, 0x21, 0 + .dw 0xc1c0, 0xc03c, 0xc1ff, 0xc03c, 0x21, 0 + .dw 0xc240, 0xc03c, 0xc27f, 0xc03c, 0x21, 0 + .dw 0xc2c0, 0xc03c, 0xc2ff, 0xc03c, 0x21, 0 + .dw 0xc340, 0xc03c, 0xc37f, 0xc03c, 0x21, 0 + .dw 0xc3c0, 0xc03c, 0xc3ff, 0xc03c, 0x21, 0 + .dw 0xc440, 0xc03c, 0xc47f, 0xc03c, 0x21, 0 + .dw 0xc4c0, 0xc03c, 0xc4ff, 0xc03c, 0x21, 0 + .dw 0xc540, 0xc03c, 0xc57f, 0xc03c, 0x21, 0 + .dw 0xc5c0, 0xc03c, 0xc5ff, 0xc03c, 0x21, 0 + .dw 0xc640, 0xc03c, 0xc67f, 0xc03c, 0x21, 0 + .dw 0xc6c0, 0xc03c, 0xc6ff, 0xc03c, 0x21, 0 + .dw 0xc740, 0xc03c, 0xc77f, 0xc03c, 0x21, 0 + .dw 0xc7c0, 0xc03c, 0xc7ff, 0xc03c, 0x21, 0 + .dw 0xc840, 0xc03c, 0xc87f, 0xc03c, 0x21, 0 + .dw 0xc8c0, 0xc03c, 0xc8ff, 0xc03c, 0x21, 0 + .dw 0xc940, 0xc03c, 0xc97f, 0xc03c, 0x21, 0 + .dw 0xc9c0, 0xc03c, 0xc9ff, 0xc03c, 0x21, 0 + .dw 0xca40, 0xc03c, 0xca7f, 0xc03c, 0x21, 0 + .dw 0xcac0, 0xc03c, 0xcaff, 0xc03c, 0x21, 0 + .dw 0xcb40, 0xc03c, 0xcb7f, 0xc03c, 0x21, 0 + .dw 0xcbc0, 0xc03c, 0xcbff, 0xc03c, 0x21, 0 + .dw 0xcc40, 0xc03c, 0xcc7f, 0xc03c, 0x21, 0 + .dw 0xccc0, 0xc03c, 0xccff, 0xc03c, 0x21, 0 + .dw 0xcd40, 0xc03c, 0xcd7f, 0xc03c, 0x21, 0 + .dw 0xcdc0, 0xc03c, 0xcdff, 0xc03c, 0x21, 0 + .dw 0xce40, 0xc03c, 0xce7f, 0xc03c, 0x21, 0 + .dw 0xcec0, 0xc03c, 0xceff, 0xc03c, 0x21, 0 + .dw 0xcf40, 0xc03c, 0xcf7f, 0xc03c, 0x21, 0 + .dw 0xcfc0, 0xc03c, 0xcfff, 0xc03c, 0x21, 0 + .dw 0xd040, 0xc03c, 0xd07f, 0xc03c, 0x21, 0 + .dw 0xd0c0, 0xc03c, 0xd0ff, 0xc03c, 0x21, 0 + .dw 0xd140, 0xc03c, 0xd17f, 0xc03c, 0x21, 0 + .dw 0xd1c0, 0xc03c, 0xd1ff, 0xc03c, 0x21, 0 + .dw 0xd240, 0xc03c, 0xd27f, 0xc03c, 0x21, 0 + .dw 0xd2c0, 0xc03c, 0xd2ff, 0xc03c, 0x21, 0 + .dw 0xd340, 0xc03c, 0xd37f, 0xc03c, 0x21, 0 + .dw 0xd3c0, 0xc03c, 0xd3ff, 0xc03c, 0x21, 0 + .dw 0xd440, 0xc03c, 0xd47f, 0xc03c, 0x21, 0 + .dw 0xd4c0, 0xc03c, 0xd4ff, 0xc03c, 0x21, 0 + .dw 0xd540, 0xc03c, 0xd57f, 0xc03c, 0x21, 0 + .dw 0xd5c0, 0xc03c, 0xd5ff, 0xc03c, 0x21, 0 + .dw 0xd640, 0xc03c, 0xd67f, 0xc03c, 0x21, 0 + .dw 0xd6c0, 0xc03c, 0xd6ff, 0xc03c, 0x21, 0 + .dw 0xd740, 0xc03c, 0xd77f, 0xc03c, 0x21, 0 + .dw 0xd7c0, 0xc03c, 0xd7ff, 0xc03c, 0x21, 0 + .dw 0xd840, 0xc03c, 0xd87f, 0xc03c, 0x21, 0 + .dw 0xd8c0, 0xc03c, 0xd8ff, 0xc03c, 0x21, 0 + .dw 0xd940, 0xc03c, 0xd97f, 0xc03c, 0x21, 0 + .dw 0xd9c0, 0xc03c, 0xdfff, 0xc03c, 0x21, 0 + .dw 0xe040, 0xc03c, 0xe07f, 0xc03c, 0x21, 0 + .dw 0xe0c0, 0xc03c, 0xe0ff, 0xc03c, 0x21, 0 + .dw 0xe140, 0xc03c, 0xe17f, 0xc03c, 0x21, 0 + .dw 0xe1c0, 0xc03c, 0xe1ff, 0xc03c, 0x21, 0 + .dw 0xe240, 0xc03c, 0xe27f, 0xc03c, 0x21, 0 + .dw 0xe2c0, 0xc03c, 0xe2ff, 0xc03c, 0x21, 0 + .dw 0xe340, 0xc03c, 0xe37f, 0xc03c, 0x21, 0 + .dw 0xe3c0, 0xc03c, 0xe3ff, 0xc03c, 0x21, 0 + .dw 0xe440, 0xc03c, 0xe47f, 0xc03c, 0x21, 0 + .dw 0xe4c0, 0xc03c, 0xe4ff, 0xc03c, 0x21, 0 + .dw 0xe540, 0xc03c, 0xe57f, 0xc03c, 0x21, 0 + .dw 0xe5c0, 0xc03c, 0xe5ff, 0xc03c, 0x21, 0 + .dw 0xe640, 0xc03c, 0xe67f, 0xc03c, 0x21, 0 + .dw 0xe6c0, 0xc03c, 0xe6ff, 0xc03c, 0x21, 0 + .dw 0xe740, 0xc03c, 0xe77f, 0xc03c, 0x21, 0 + .dw 0xe7c0, 0xc03c, 0xe7ff, 0xc03c, 0x21, 0 + .dw 0xe840, 0xc03c, 0xe87f, 0xc03c, 0x21, 0 + .dw 0xe8c0, 0xc03c, 0xe8ff, 0xc03c, 0x21, 0 + .dw 0xe940, 0xc03c, 0xe97f, 0xc03c, 0x21, 0 + .dw 0xe9c0, 0xc03c, 0xe9ff, 0xc03c, 0x21, 0 + .dw 0xea40, 0xc03c, 0xea7f, 0xc03c, 0x21, 0 + .dw 0xeac0, 0xc03c, 0xeaff, 0xc03c, 0x21, 0 + .dw 0xeb40, 0xc03c, 0xeb7f, 0xc03c, 0x21, 0 + .dw 0xebc0, 0xc03c, 0xebff, 0xc03c, 0x21, 0 + .dw 0xec40, 0xc03c, 0xec7f, 0xc03c, 0x21, 0 + .dw 0xecc0, 0xc03c, 0xecff, 0xc03c, 0x21, 0 + .dw 0xed40, 0xc03c, 0xed7f, 0xc03c, 0x21, 0 + .dw 0xedc0, 0xc03c, 0xedff, 0xc03c, 0x21, 0 + .dw 0xee40, 0xc03c, 0xee7f, 0xc03c, 0x21, 0 + .dw 0xeec0, 0xc03c, 0xeeff, 0xc03c, 0x21, 0 + .dw 0xef40, 0xc03c, 0xef7f, 0xc03c, 0x21, 0 + .dw 0xefc0, 0xc03c, 0xefff, 0xc03c, 0x21, 0 + .dw 0xf040, 0xc03c, 0xf07f, 0xc03c, 0x21, 0 + .dw 0xf0c0, 0xc03c, 0xf0ff, 0xc03c, 0x21, 0 + .dw 0xf140, 0xc03c, 0xf17f, 0xc03c, 0x21, 0 + .dw 0xf1c0, 0xc03c, 0xf1ff, 0xc03c, 0x21, 0 + .dw 0xf240, 0xc03c, 0xf27f, 0xc03c, 0x21, 0 + .dw 0xf2c0, 0xc03c, 0xf2ff, 0xc03c, 0x21, 0 + .dw 0xf340, 0xc03c, 0xf37f, 0xc03c, 0x21, 0 + .dw 0xf3c0, 0xc03c, 0xf3ff, 0xc03c, 0x21, 0 + .dw 0xf440, 0xc03c, 0xf47f, 0xc03c, 0x21, 0 + .dw 0xf4c0, 0xc03c, 0xf4ff, 0xc03c, 0x21, 0 + .dw 0xf540, 0xc03c, 0xf57f, 0xc03c, 0x21, 0 + .dw 0xf5c0, 0xc03c, 0xf5ff, 0xc03c, 0x21, 0 + .dw 0xf640, 0xc03c, 0xf67f, 0xc03c, 0x21, 0 + .dw 0xf6c0, 0xc03c, 0xf6ff, 0xc03c, 0x21, 0 + .dw 0xf740, 0xc03c, 0xf77f, 0xc03c, 0x21, 0 + .dw 0xf7c0, 0xc03c, 0xf7ff, 0xc03c, 0x21, 0 + .dw 0xf840, 0xc03c, 0xf87f, 0xc03c, 0x21, 0 + .dw 0xf8c0, 0xc03c, 0xf8ff, 0xc03c, 0x21, 0 + .dw 0xf940, 0xc03c, 0xf97f, 0xc03c, 0x21, 0 + .dw 0xf9c0, 0xc03c, 0xffff, 0xc03c, 0x21, 0 + .dw 0x0040, 0xc03d, 0x007f, 0xc03d, 0x21, 0 + .dw 0x00c0, 0xc03d, 0x00ff, 0xc03d, 0x21, 0 + .dw 0x0140, 0xc03d, 0x017f, 0xc03d, 0x21, 0 + .dw 0x01c0, 0xc03d, 0x01ff, 0xc03d, 0x21, 0 + .dw 0x0240, 0xc03d, 0x027f, 0xc03d, 0x21, 0 + .dw 0x02c0, 0xc03d, 0x02ff, 0xc03d, 0x21, 0 + .dw 0x0340, 0xc03d, 0x037f, 0xc03d, 0x21, 0 + .dw 0x03c0, 0xc03d, 0x03ff, 0xc03d, 0x21, 0 + .dw 0x0440, 0xc03d, 0x047f, 0xc03d, 0x21, 0 + .dw 0x04c0, 0xc03d, 0x04ff, 0xc03d, 0x21, 0 + .dw 0x0540, 0xc03d, 0x057f, 0xc03d, 0x21, 0 + .dw 0x05c0, 0xc03d, 0x05ff, 0xc03d, 0x21, 0 + .dw 0x0640, 0xc03d, 0x067f, 0xc03d, 0x21, 0 + .dw 0x06c0, 0xc03d, 0x06ff, 0xc03d, 0x21, 0 + .dw 0x0740, 0xc03d, 0x077f, 0xc03d, 0x21, 0 + .dw 0x07c0, 0xc03d, 0x07ff, 0xc03d, 0x21, 0 + .dw 0x0840, 0xc03d, 0x087f, 0xc03d, 0x21, 0 + .dw 0x08c0, 0xc03d, 0x08ff, 0xc03d, 0x21, 0 + .dw 0x0940, 0xc03d, 0x097f, 0xc03d, 0x21, 0 + .dw 0x09c0, 0xc03d, 0x09ff, 0xc03d, 0x21, 0 + .dw 0x0a40, 0xc03d, 0x0a7f, 0xc03d, 0x21, 0 + .dw 0x0ac0, 0xc03d, 0x0aff, 0xc03d, 0x21, 0 + .dw 0x0b40, 0xc03d, 0x0b7f, 0xc03d, 0x21, 0 + .dw 0x0bc0, 0xc03d, 0x0bff, 0xc03d, 0x21, 0 + .dw 0x0c40, 0xc03d, 0x0c7f, 0xc03d, 0x21, 0 + .dw 0x0cc0, 0xc03d, 0x0cff, 0xc03d, 0x21, 0 + .dw 0x0d40, 0xc03d, 0x0d7f, 0xc03d, 0x21, 0 + .dw 0x0dc0, 0xc03d, 0x0dff, 0xc03d, 0x21, 0 + .dw 0x0e40, 0xc03d, 0x0e7f, 0xc03d, 0x21, 0 + .dw 0x0ec0, 0xc03d, 0x0eff, 0xc03d, 0x21, 0 + .dw 0x0f40, 0xc03d, 0x0f7f, 0xc03d, 0x21, 0 + .dw 0x0fc0, 0xc03d, 0x0fff, 0xc03d, 0x21, 0 + .dw 0x1040, 0xc03d, 0x107f, 0xc03d, 0x21, 0 + .dw 0x10c0, 0xc03d, 0x10ff, 0xc03d, 0x21, 0 + .dw 0x1140, 0xc03d, 0x117f, 0xc03d, 0x21, 0 + .dw 0x11c0, 0xc03d, 0x11ff, 0xc03d, 0x21, 0 + .dw 0x1240, 0xc03d, 0x127f, 0xc03d, 0x21, 0 + .dw 0x12c0, 0xc03d, 0x12ff, 0xc03d, 0x21, 0 + .dw 0x1340, 0xc03d, 0x137f, 0xc03d, 0x21, 0 + .dw 0x13c0, 0xc03d, 0x13ff, 0xc03d, 0x21, 0 + .dw 0x1440, 0xc03d, 0x147f, 0xc03d, 0x21, 0 + .dw 0x14c0, 0xc03d, 0x14ff, 0xc03d, 0x21, 0 + .dw 0x1540, 0xc03d, 0x157f, 0xc03d, 0x21, 0 + .dw 0x15c0, 0xc03d, 0x15ff, 0xc03d, 0x21, 0 + .dw 0x1640, 0xc03d, 0x167f, 0xc03d, 0x21, 0 + .dw 0x16c0, 0xc03d, 0x16ff, 0xc03d, 0x21, 0 + .dw 0x1740, 0xc03d, 0x177f, 0xc03d, 0x21, 0 + .dw 0x17c0, 0xc03d, 0x17ff, 0xc03d, 0x21, 0 + .dw 0x1840, 0xc03d, 0x187f, 0xc03d, 0x21, 0 + .dw 0x18c0, 0xc03d, 0x18ff, 0xc03d, 0x21, 0 + .dw 0x1940, 0xc03d, 0x197f, 0xc03d, 0x21, 0 + .dw 0x19c0, 0xc03d, 0x1fff, 0xc03d, 0x21, 0 + .dw 0x2040, 0xc03d, 0x207f, 0xc03d, 0x21, 0 + .dw 0x20c0, 0xc03d, 0x20ff, 0xc03d, 0x21, 0 + .dw 0x2140, 0xc03d, 0x217f, 0xc03d, 0x21, 0 + .dw 0x21c0, 0xc03d, 0x21ff, 0xc03d, 0x21, 0 + .dw 0x2240, 0xc03d, 0x227f, 0xc03d, 0x21, 0 + .dw 0x22c0, 0xc03d, 0x22ff, 0xc03d, 0x21, 0 + .dw 0x2340, 0xc03d, 0x237f, 0xc03d, 0x21, 0 + .dw 0x23c0, 0xc03d, 0x23ff, 0xc03d, 0x21, 0 + .dw 0x2440, 0xc03d, 0x247f, 0xc03d, 0x21, 0 + .dw 0x24c0, 0xc03d, 0x24ff, 0xc03d, 0x21, 0 + .dw 0x2540, 0xc03d, 0x257f, 0xc03d, 0x21, 0 + .dw 0x25c0, 0xc03d, 0x25ff, 0xc03d, 0x21, 0 + .dw 0x2640, 0xc03d, 0x267f, 0xc03d, 0x21, 0 + .dw 0x26c0, 0xc03d, 0x26ff, 0xc03d, 0x21, 0 + .dw 0x2740, 0xc03d, 0x277f, 0xc03d, 0x21, 0 + .dw 0x27c0, 0xc03d, 0x27ff, 0xc03d, 0x21, 0 + .dw 0x2840, 0xc03d, 0x287f, 0xc03d, 0x21, 0 + .dw 0x28c0, 0xc03d, 0x28ff, 0xc03d, 0x21, 0 + .dw 0x2940, 0xc03d, 0x297f, 0xc03d, 0x21, 0 + .dw 0x29c0, 0xc03d, 0x29ff, 0xc03d, 0x21, 0 + .dw 0x2a40, 0xc03d, 0x2a7f, 0xc03d, 0x21, 0 + .dw 0x2ac0, 0xc03d, 0x2aff, 0xc03d, 0x21, 0 + .dw 0x2b40, 0xc03d, 0x2b7f, 0xc03d, 0x21, 0 + .dw 0x2bc0, 0xc03d, 0x2bff, 0xc03d, 0x21, 0 + .dw 0x2c40, 0xc03d, 0x2c7f, 0xc03d, 0x21, 0 + .dw 0x2cc0, 0xc03d, 0x2cff, 0xc03d, 0x21, 0 + .dw 0x2d40, 0xc03d, 0x2d7f, 0xc03d, 0x21, 0 + .dw 0x2dc0, 0xc03d, 0x2dff, 0xc03d, 0x21, 0 + .dw 0x2e40, 0xc03d, 0x2e7f, 0xc03d, 0x21, 0 + .dw 0x2ec0, 0xc03d, 0x2eff, 0xc03d, 0x21, 0 + .dw 0x2f40, 0xc03d, 0x2f7f, 0xc03d, 0x21, 0 + .dw 0x2fc0, 0xc03d, 0x2fff, 0xc03d, 0x21, 0 + .dw 0x3040, 0xc03d, 0x307f, 0xc03d, 0x21, 0 + .dw 0x30c0, 0xc03d, 0x30ff, 0xc03d, 0x21, 0 + .dw 0x3140, 0xc03d, 0x317f, 0xc03d, 0x21, 0 + .dw 0x31c0, 0xc03d, 0x31ff, 0xc03d, 0x21, 0 + .dw 0x3240, 0xc03d, 0x327f, 0xc03d, 0x21, 0 + .dw 0x32c0, 0xc03d, 0x32ff, 0xc03d, 0x21, 0 + .dw 0x3340, 0xc03d, 0x337f, 0xc03d, 0x21, 0 + .dw 0x33c0, 0xc03d, 0x33ff, 0xc03d, 0x21, 0 + .dw 0x3440, 0xc03d, 0x347f, 0xc03d, 0x21, 0 + .dw 0x34c0, 0xc03d, 0x34ff, 0xc03d, 0x21, 0 + .dw 0x3540, 0xc03d, 0x357f, 0xc03d, 0x21, 0 + .dw 0x35c0, 0xc03d, 0x35ff, 0xc03d, 0x21, 0 + .dw 0x3640, 0xc03d, 0x367f, 0xc03d, 0x21, 0 + .dw 0x36c0, 0xc03d, 0x36ff, 0xc03d, 0x21, 0 + .dw 0x3740, 0xc03d, 0x377f, 0xc03d, 0x21, 0 + .dw 0x37c0, 0xc03d, 0x37ff, 0xc03d, 0x21, 0 + .dw 0x3840, 0xc03d, 0x387f, 0xc03d, 0x21, 0 + .dw 0x38c0, 0xc03d, 0x38ff, 0xc03d, 0x21, 0 + .dw 0x3940, 0xc03d, 0x397f, 0xc03d, 0x21, 0 + .dw 0x39c0, 0xc03d, 0x3fff, 0xc03d, 0x21, 0 + .dw 0x4040, 0xc03d, 0x407f, 0xc03d, 0x21, 0 + .dw 0x40c0, 0xc03d, 0x40ff, 0xc03d, 0x21, 0 + .dw 0x4140, 0xc03d, 0x417f, 0xc03d, 0x21, 0 + .dw 0x41c0, 0xc03d, 0x41ff, 0xc03d, 0x21, 0 + .dw 0x4240, 0xc03d, 0x427f, 0xc03d, 0x21, 0 + .dw 0x42c0, 0xc03d, 0x42ff, 0xc03d, 0x21, 0 + .dw 0x4340, 0xc03d, 0x437f, 0xc03d, 0x21, 0 + .dw 0x43c0, 0xc03d, 0x43ff, 0xc03d, 0x21, 0 + .dw 0x4440, 0xc03d, 0x447f, 0xc03d, 0x21, 0 + .dw 0x44c0, 0xc03d, 0x44ff, 0xc03d, 0x21, 0 + .dw 0x4540, 0xc03d, 0x457f, 0xc03d, 0x21, 0 + .dw 0x45c0, 0xc03d, 0x45ff, 0xc03d, 0x21, 0 + .dw 0x4640, 0xc03d, 0x467f, 0xc03d, 0x21, 0 + .dw 0x46c0, 0xc03d, 0x46ff, 0xc03d, 0x21, 0 + .dw 0x4740, 0xc03d, 0x477f, 0xc03d, 0x21, 0 + .dw 0x47c0, 0xc03d, 0x47ff, 0xc03d, 0x21, 0 + .dw 0x4840, 0xc03d, 0x487f, 0xc03d, 0x21, 0 + .dw 0x48c0, 0xc03d, 0x48ff, 0xc03d, 0x21, 0 + .dw 0x4940, 0xc03d, 0x497f, 0xc03d, 0x21, 0 + .dw 0x49c0, 0xc03d, 0x49ff, 0xc03d, 0x21, 0 + .dw 0x4a40, 0xc03d, 0x4a7f, 0xc03d, 0x21, 0 + .dw 0x4ac0, 0xc03d, 0x4aff, 0xc03d, 0x21, 0 + .dw 0x4b40, 0xc03d, 0x4b7f, 0xc03d, 0x21, 0 + .dw 0x4bc0, 0xc03d, 0x4bff, 0xc03d, 0x21, 0 + .dw 0x4c40, 0xc03d, 0x4c7f, 0xc03d, 0x21, 0 + .dw 0x4cc0, 0xc03d, 0x4cff, 0xc03d, 0x21, 0 + .dw 0x4d40, 0xc03d, 0x4d7f, 0xc03d, 0x21, 0 + .dw 0x4dc0, 0xc03d, 0x4dff, 0xc03d, 0x21, 0 + .dw 0x4e40, 0xc03d, 0x4e7f, 0xc03d, 0x21, 0 + .dw 0x4ec0, 0xc03d, 0x4eff, 0xc03d, 0x21, 0 + .dw 0x4f40, 0xc03d, 0x4f7f, 0xc03d, 0x21, 0 + .dw 0x4fc0, 0xc03d, 0x4fff, 0xc03d, 0x21, 0 + .dw 0x5040, 0xc03d, 0x507f, 0xc03d, 0x21, 0 + .dw 0x50c0, 0xc03d, 0x50ff, 0xc03d, 0x21, 0 + .dw 0x5140, 0xc03d, 0x517f, 0xc03d, 0x21, 0 + .dw 0x51c0, 0xc03d, 0x51ff, 0xc03d, 0x21, 0 + .dw 0x5240, 0xc03d, 0x527f, 0xc03d, 0x21, 0 + .dw 0x52c0, 0xc03d, 0x52ff, 0xc03d, 0x21, 0 + .dw 0x5340, 0xc03d, 0x537f, 0xc03d, 0x21, 0 + .dw 0x53c0, 0xc03d, 0x53ff, 0xc03d, 0x21, 0 + .dw 0x5440, 0xc03d, 0x547f, 0xc03d, 0x21, 0 + .dw 0x54c0, 0xc03d, 0x54ff, 0xc03d, 0x21, 0 + .dw 0x5540, 0xc03d, 0x557f, 0xc03d, 0x21, 0 + .dw 0x55c0, 0xc03d, 0x55ff, 0xc03d, 0x21, 0 + .dw 0x5640, 0xc03d, 0x567f, 0xc03d, 0x21, 0 + .dw 0x56c0, 0xc03d, 0x56ff, 0xc03d, 0x21, 0 + .dw 0x5740, 0xc03d, 0x577f, 0xc03d, 0x21, 0 + .dw 0x57c0, 0xc03d, 0x57ff, 0xc03d, 0x21, 0 + .dw 0x5840, 0xc03d, 0x587f, 0xc03d, 0x21, 0 + .dw 0x58c0, 0xc03d, 0x58ff, 0xc03d, 0x21, 0 + .dw 0x5940, 0xc03d, 0x597f, 0xc03d, 0x21, 0 + .dw 0x59c0, 0xc03d, 0x5fff, 0xc03d, 0x21, 0 + .dw 0x6040, 0xc03d, 0x607f, 0xc03d, 0x21, 0 + .dw 0x60c0, 0xc03d, 0x60ff, 0xc03d, 0x21, 0 + .dw 0x6140, 0xc03d, 0x617f, 0xc03d, 0x21, 0 + .dw 0x61c0, 0xc03d, 0x61ff, 0xc03d, 0x21, 0 + .dw 0x6240, 0xc03d, 0x627f, 0xc03d, 0x21, 0 + .dw 0x62c0, 0xc03d, 0x62ff, 0xc03d, 0x21, 0 + .dw 0x6340, 0xc03d, 0x637f, 0xc03d, 0x21, 0 + .dw 0x63c0, 0xc03d, 0x63ff, 0xc03d, 0x21, 0 + .dw 0x6440, 0xc03d, 0x647f, 0xc03d, 0x21, 0 + .dw 0x64c0, 0xc03d, 0x64ff, 0xc03d, 0x21, 0 + .dw 0x6540, 0xc03d, 0x657f, 0xc03d, 0x21, 0 + .dw 0x65c0, 0xc03d, 0x65ff, 0xc03d, 0x21, 0 + .dw 0x6640, 0xc03d, 0x667f, 0xc03d, 0x21, 0 + .dw 0x66c0, 0xc03d, 0x66ff, 0xc03d, 0x21, 0 + .dw 0x6740, 0xc03d, 0x677f, 0xc03d, 0x21, 0 + .dw 0x67c0, 0xc03d, 0x67ff, 0xc03d, 0x21, 0 + .dw 0x6840, 0xc03d, 0x687f, 0xc03d, 0x21, 0 + .dw 0x68c0, 0xc03d, 0x68ff, 0xc03d, 0x21, 0 + .dw 0x6940, 0xc03d, 0x697f, 0xc03d, 0x21, 0 + .dw 0x69c0, 0xc03d, 0x69ff, 0xc03d, 0x21, 0 + .dw 0x6a40, 0xc03d, 0x6a7f, 0xc03d, 0x21, 0 + .dw 0x6ac0, 0xc03d, 0x6aff, 0xc03d, 0x21, 0 + .dw 0x6b40, 0xc03d, 0x6b7f, 0xc03d, 0x21, 0 + .dw 0x6bc0, 0xc03d, 0x6bff, 0xc03d, 0x21, 0 + .dw 0x6c40, 0xc03d, 0x6c7f, 0xc03d, 0x21, 0 + .dw 0x6cc0, 0xc03d, 0x6cff, 0xc03d, 0x21, 0 + .dw 0x6d40, 0xc03d, 0x6d7f, 0xc03d, 0x21, 0 + .dw 0x6dc0, 0xc03d, 0x6dff, 0xc03d, 0x21, 0 + .dw 0x6e40, 0xc03d, 0x6e7f, 0xc03d, 0x21, 0 + .dw 0x6ec0, 0xc03d, 0x6eff, 0xc03d, 0x21, 0 + .dw 0x6f40, 0xc03d, 0x6f7f, 0xc03d, 0x21, 0 + .dw 0x6fc0, 0xc03d, 0x6fff, 0xc03d, 0x21, 0 + .dw 0x7040, 0xc03d, 0x707f, 0xc03d, 0x21, 0 + .dw 0x70c0, 0xc03d, 0x70ff, 0xc03d, 0x21, 0 + .dw 0x7140, 0xc03d, 0x717f, 0xc03d, 0x21, 0 + .dw 0x71c0, 0xc03d, 0x71ff, 0xc03d, 0x21, 0 + .dw 0x7240, 0xc03d, 0x727f, 0xc03d, 0x21, 0 + .dw 0x72c0, 0xc03d, 0x72ff, 0xc03d, 0x21, 0 + .dw 0x7340, 0xc03d, 0x737f, 0xc03d, 0x21, 0 + .dw 0x73c0, 0xc03d, 0x73ff, 0xc03d, 0x21, 0 + .dw 0x7440, 0xc03d, 0x747f, 0xc03d, 0x21, 0 + .dw 0x74c0, 0xc03d, 0x74ff, 0xc03d, 0x21, 0 + .dw 0x7540, 0xc03d, 0x757f, 0xc03d, 0x21, 0 + .dw 0x75c0, 0xc03d, 0x75ff, 0xc03d, 0x21, 0 + .dw 0x7640, 0xc03d, 0x767f, 0xc03d, 0x21, 0 + .dw 0x76c0, 0xc03d, 0x76ff, 0xc03d, 0x21, 0 + .dw 0x7740, 0xc03d, 0x777f, 0xc03d, 0x21, 0 + .dw 0x77c0, 0xc03d, 0x77ff, 0xc03d, 0x21, 0 + .dw 0x7840, 0xc03d, 0x787f, 0xc03d, 0x21, 0 + .dw 0x78c0, 0xc03d, 0x78ff, 0xc03d, 0x21, 0 + .dw 0x7940, 0xc03d, 0x797f, 0xc03d, 0x21, 0 + .dw 0x79c0, 0xc03d, 0x7fff, 0xc03d, 0x21, 0 + .dw 0x8040, 0xc03d, 0x807f, 0xc03d, 0x21, 0 + .dw 0x80c0, 0xc03d, 0x80ff, 0xc03d, 0x21, 0 + .dw 0x8140, 0xc03d, 0x817f, 0xc03d, 0x21, 0 + .dw 0x81c0, 0xc03d, 0x81ff, 0xc03d, 0x21, 0 + .dw 0x8240, 0xc03d, 0x827f, 0xc03d, 0x21, 0 + .dw 0x82c0, 0xc03d, 0x82ff, 0xc03d, 0x21, 0 + .dw 0x8340, 0xc03d, 0x837f, 0xc03d, 0x21, 0 + .dw 0x83c0, 0xc03d, 0x83ff, 0xc03d, 0x21, 0 + .dw 0x8440, 0xc03d, 0x847f, 0xc03d, 0x21, 0 + .dw 0x84c0, 0xc03d, 0x84ff, 0xc03d, 0x21, 0 + .dw 0x8540, 0xc03d, 0x857f, 0xc03d, 0x21, 0 + .dw 0x85c0, 0xc03d, 0x85ff, 0xc03d, 0x21, 0 + .dw 0x8640, 0xc03d, 0x867f, 0xc03d, 0x21, 0 + .dw 0x86c0, 0xc03d, 0x86ff, 0xc03d, 0x21, 0 + .dw 0x8740, 0xc03d, 0x877f, 0xc03d, 0x21, 0 + .dw 0x87c0, 0xc03d, 0x87ff, 0xc03d, 0x21, 0 + .dw 0x8840, 0xc03d, 0x887f, 0xc03d, 0x21, 0 + .dw 0x88c0, 0xc03d, 0x88ff, 0xc03d, 0x21, 0 + .dw 0x8940, 0xc03d, 0x897f, 0xc03d, 0x21, 0 + .dw 0x89c0, 0xc03d, 0x89ff, 0xc03d, 0x21, 0 + .dw 0x8a40, 0xc03d, 0x8a7f, 0xc03d, 0x21, 0 + .dw 0x8ac0, 0xc03d, 0x8aff, 0xc03d, 0x21, 0 + .dw 0x8b40, 0xc03d, 0x8b7f, 0xc03d, 0x21, 0 + .dw 0x8bc0, 0xc03d, 0x8bff, 0xc03d, 0x21, 0 + .dw 0x8c40, 0xc03d, 0x8c7f, 0xc03d, 0x21, 0 + .dw 0x8cc0, 0xc03d, 0x8cff, 0xc03d, 0x21, 0 + .dw 0x8d40, 0xc03d, 0x8d7f, 0xc03d, 0x21, 0 + .dw 0x8dc0, 0xc03d, 0x8dff, 0xc03d, 0x21, 0 + .dw 0x8e40, 0xc03d, 0x8e7f, 0xc03d, 0x21, 0 + .dw 0x8ec0, 0xc03d, 0x8eff, 0xc03d, 0x21, 0 + .dw 0x8f40, 0xc03d, 0x8f7f, 0xc03d, 0x21, 0 + .dw 0x8fc0, 0xc03d, 0x8fff, 0xc03d, 0x21, 0 + .dw 0x9040, 0xc03d, 0x907f, 0xc03d, 0x21, 0 + .dw 0x90c0, 0xc03d, 0x90ff, 0xc03d, 0x21, 0 + .dw 0x9140, 0xc03d, 0x917f, 0xc03d, 0x21, 0 + .dw 0x91c0, 0xc03d, 0x91ff, 0xc03d, 0x21, 0 + .dw 0x9240, 0xc03d, 0x927f, 0xc03d, 0x21, 0 + .dw 0x92c0, 0xc03d, 0x92ff, 0xc03d, 0x21, 0 + .dw 0x9340, 0xc03d, 0x937f, 0xc03d, 0x21, 0 + .dw 0x93c0, 0xc03d, 0x93ff, 0xc03d, 0x21, 0 + .dw 0x9440, 0xc03d, 0x947f, 0xc03d, 0x21, 0 + .dw 0x94c0, 0xc03d, 0x94ff, 0xc03d, 0x21, 0 + .dw 0x9540, 0xc03d, 0x957f, 0xc03d, 0x21, 0 + .dw 0x95c0, 0xc03d, 0x95ff, 0xc03d, 0x21, 0 + .dw 0x9640, 0xc03d, 0x967f, 0xc03d, 0x21, 0 + .dw 0x96c0, 0xc03d, 0x96ff, 0xc03d, 0x21, 0 + .dw 0x9740, 0xc03d, 0x977f, 0xc03d, 0x21, 0 + .dw 0x97c0, 0xc03d, 0x97ff, 0xc03d, 0x21, 0 + .dw 0x9840, 0xc03d, 0x987f, 0xc03d, 0x21, 0 + .dw 0x98c0, 0xc03d, 0x98ff, 0xc03d, 0x21, 0 + .dw 0x9940, 0xc03d, 0x997f, 0xc03d, 0x21, 0 + .dw 0x99c0, 0xc03d, 0x9fff, 0xc03d, 0x21, 0 + .dw 0xa040, 0xc03d, 0xa07f, 0xc03d, 0x21, 0 + .dw 0xa0c0, 0xc03d, 0xa0ff, 0xc03d, 0x21, 0 + .dw 0xa140, 0xc03d, 0xa17f, 0xc03d, 0x21, 0 + .dw 0xa1c0, 0xc03d, 0xa1ff, 0xc03d, 0x21, 0 + .dw 0xa240, 0xc03d, 0xa27f, 0xc03d, 0x21, 0 + .dw 0xa2c0, 0xc03d, 0xa2ff, 0xc03d, 0x21, 0 + .dw 0xa340, 0xc03d, 0xa37f, 0xc03d, 0x21, 0 + .dw 0xa3c0, 0xc03d, 0xa3ff, 0xc03d, 0x21, 0 + .dw 0xa440, 0xc03d, 0xa47f, 0xc03d, 0x21, 0 + .dw 0xa4c0, 0xc03d, 0xa4ff, 0xc03d, 0x21, 0 + .dw 0xa540, 0xc03d, 0xa57f, 0xc03d, 0x21, 0 + .dw 0xa5c0, 0xc03d, 0xa5ff, 0xc03d, 0x21, 0 + .dw 0xa640, 0xc03d, 0xa67f, 0xc03d, 0x21, 0 + .dw 0xa6c0, 0xc03d, 0xa6ff, 0xc03d, 0x21, 0 + .dw 0xa740, 0xc03d, 0xa77f, 0xc03d, 0x21, 0 + .dw 0xa7c0, 0xc03d, 0xa7ff, 0xc03d, 0x21, 0 + .dw 0xa840, 0xc03d, 0xa87f, 0xc03d, 0x21, 0 + .dw 0xa8c0, 0xc03d, 0xa8ff, 0xc03d, 0x21, 0 + .dw 0xa940, 0xc03d, 0xa97f, 0xc03d, 0x21, 0 + .dw 0xa9c0, 0xc03d, 0xa9ff, 0xc03d, 0x21, 0 + .dw 0xaa40, 0xc03d, 0xaa7f, 0xc03d, 0x21, 0 + .dw 0xaac0, 0xc03d, 0xaaff, 0xc03d, 0x21, 0 + .dw 0xab40, 0xc03d, 0xab7f, 0xc03d, 0x21, 0 + .dw 0xabc0, 0xc03d, 0xabff, 0xc03d, 0x21, 0 + .dw 0xac40, 0xc03d, 0xac7f, 0xc03d, 0x21, 0 + .dw 0xacc0, 0xc03d, 0xacff, 0xc03d, 0x21, 0 + .dw 0xad40, 0xc03d, 0xad7f, 0xc03d, 0x21, 0 + .dw 0xadc0, 0xc03d, 0xadff, 0xc03d, 0x21, 0 + .dw 0xae40, 0xc03d, 0xae7f, 0xc03d, 0x21, 0 + .dw 0xaec0, 0xc03d, 0xaeff, 0xc03d, 0x21, 0 + .dw 0xaf40, 0xc03d, 0xaf7f, 0xc03d, 0x21, 0 + .dw 0xafc0, 0xc03d, 0xafff, 0xc03d, 0x21, 0 + .dw 0xb040, 0xc03d, 0xb07f, 0xc03d, 0x21, 0 + .dw 0xb0c0, 0xc03d, 0xb0ff, 0xc03d, 0x21, 0 + .dw 0xb140, 0xc03d, 0xb17f, 0xc03d, 0x21, 0 + .dw 0xb1c0, 0xc03d, 0xb1ff, 0xc03d, 0x21, 0 + .dw 0xb240, 0xc03d, 0xb27f, 0xc03d, 0x21, 0 + .dw 0xb2c0, 0xc03d, 0xb2ff, 0xc03d, 0x21, 0 + .dw 0xb340, 0xc03d, 0xb37f, 0xc03d, 0x21, 0 + .dw 0xb3c0, 0xc03d, 0xb3ff, 0xc03d, 0x21, 0 + .dw 0xb440, 0xc03d, 0xb47f, 0xc03d, 0x21, 0 + .dw 0xb4c0, 0xc03d, 0xb4ff, 0xc03d, 0x21, 0 + .dw 0xb540, 0xc03d, 0xb57f, 0xc03d, 0x21, 0 + .dw 0xb5c0, 0xc03d, 0xb5ff, 0xc03d, 0x21, 0 + .dw 0xb640, 0xc03d, 0xb67f, 0xc03d, 0x21, 0 + .dw 0xb6c0, 0xc03d, 0xb6ff, 0xc03d, 0x21, 0 + .dw 0xb740, 0xc03d, 0xb77f, 0xc03d, 0x21, 0 + .dw 0xb7c0, 0xc03d, 0xb7ff, 0xc03d, 0x21, 0 + .dw 0xb840, 0xc03d, 0xb87f, 0xc03d, 0x21, 0 + .dw 0xb8c0, 0xc03d, 0xb8ff, 0xc03d, 0x21, 0 + .dw 0xb940, 0xc03d, 0xb97f, 0xc03d, 0x21, 0 + .dw 0xb9c0, 0xc03d, 0xbfff, 0xc03d, 0x21, 0 + .dw 0xc040, 0xc03d, 0xc07f, 0xc03d, 0x21, 0 + .dw 0xc0c0, 0xc03d, 0xc0ff, 0xc03d, 0x21, 0 + .dw 0xc140, 0xc03d, 0xc17f, 0xc03d, 0x21, 0 + .dw 0xc1c0, 0xc03d, 0xc1ff, 0xc03d, 0x21, 0 + .dw 0xc240, 0xc03d, 0xc27f, 0xc03d, 0x21, 0 + .dw 0xc2c0, 0xc03d, 0xc2ff, 0xc03d, 0x21, 0 + .dw 0xc340, 0xc03d, 0xc37f, 0xc03d, 0x21, 0 + .dw 0xc3c0, 0xc03d, 0xc3ff, 0xc03d, 0x21, 0 + .dw 0xc440, 0xc03d, 0xc47f, 0xc03d, 0x21, 0 + .dw 0xc4c0, 0xc03d, 0xc4ff, 0xc03d, 0x21, 0 + .dw 0xc540, 0xc03d, 0xc57f, 0xc03d, 0x21, 0 + .dw 0xc5c0, 0xc03d, 0xc5ff, 0xc03d, 0x21, 0 + .dw 0xc640, 0xc03d, 0xc67f, 0xc03d, 0x21, 0 + .dw 0xc6c0, 0xc03d, 0xc6ff, 0xc03d, 0x21, 0 + .dw 0xc740, 0xc03d, 0xc77f, 0xc03d, 0x21, 0 + .dw 0xc7c0, 0xc03d, 0xc7ff, 0xc03d, 0x21, 0 + .dw 0xc840, 0xc03d, 0xc87f, 0xc03d, 0x21, 0 + .dw 0xc8c0, 0xc03d, 0xc8ff, 0xc03d, 0x21, 0 + .dw 0xc940, 0xc03d, 0xc97f, 0xc03d, 0x21, 0 + .dw 0xc9c0, 0xc03d, 0xc9ff, 0xc03d, 0x21, 0 + .dw 0xca40, 0xc03d, 0xca7f, 0xc03d, 0x21, 0 + .dw 0xcac0, 0xc03d, 0xcaff, 0xc03d, 0x21, 0 + .dw 0xcb40, 0xc03d, 0xcb7f, 0xc03d, 0x21, 0 + .dw 0xcbc0, 0xc03d, 0xcbff, 0xc03d, 0x21, 0 + .dw 0xcc40, 0xc03d, 0xcc7f, 0xc03d, 0x21, 0 + .dw 0xccc0, 0xc03d, 0xccff, 0xc03d, 0x21, 0 + .dw 0xcd40, 0xc03d, 0xcd7f, 0xc03d, 0x21, 0 + .dw 0xcdc0, 0xc03d, 0xcdff, 0xc03d, 0x21, 0 + .dw 0xce40, 0xc03d, 0xce7f, 0xc03d, 0x21, 0 + .dw 0xcec0, 0xc03d, 0xceff, 0xc03d, 0x21, 0 + .dw 0xcf40, 0xc03d, 0xcf7f, 0xc03d, 0x21, 0 + .dw 0xcfc0, 0xc03d, 0xcfff, 0xc03d, 0x21, 0 + .dw 0xd040, 0xc03d, 0xd07f, 0xc03d, 0x21, 0 + .dw 0xd0c0, 0xc03d, 0xd0ff, 0xc03d, 0x21, 0 + .dw 0xd140, 0xc03d, 0xd17f, 0xc03d, 0x21, 0 + .dw 0xd1c0, 0xc03d, 0xd1ff, 0xc03d, 0x21, 0 + .dw 0xd240, 0xc03d, 0xd27f, 0xc03d, 0x21, 0 + .dw 0xd2c0, 0xc03d, 0xd2ff, 0xc03d, 0x21, 0 + .dw 0xd340, 0xc03d, 0xd37f, 0xc03d, 0x21, 0 + .dw 0xd3c0, 0xc03d, 0xd3ff, 0xc03d, 0x21, 0 + .dw 0xd440, 0xc03d, 0xd47f, 0xc03d, 0x21, 0 + .dw 0xd4c0, 0xc03d, 0xd4ff, 0xc03d, 0x21, 0 + .dw 0xd540, 0xc03d, 0xd57f, 0xc03d, 0x21, 0 + .dw 0xd5c0, 0xc03d, 0xd5ff, 0xc03d, 0x21, 0 + .dw 0xd640, 0xc03d, 0xd67f, 0xc03d, 0x21, 0 + .dw 0xd6c0, 0xc03d, 0xd6ff, 0xc03d, 0x21, 0 + .dw 0xd740, 0xc03d, 0xd77f, 0xc03d, 0x21, 0 + .dw 0xd7c0, 0xc03d, 0xd7ff, 0xc03d, 0x21, 0 + .dw 0xd840, 0xc03d, 0xd87f, 0xc03d, 0x21, 0 + .dw 0xd8c0, 0xc03d, 0xd8ff, 0xc03d, 0x21, 0 + .dw 0xd940, 0xc03d, 0xd97f, 0xc03d, 0x21, 0 + .dw 0xd9c0, 0xc03d, 0xdfff, 0xc03d, 0x21, 0 + .dw 0xe040, 0xc03d, 0xe07f, 0xc03d, 0x21, 0 + .dw 0xe0c0, 0xc03d, 0xe0ff, 0xc03d, 0x21, 0 + .dw 0xe140, 0xc03d, 0xe17f, 0xc03d, 0x21, 0 + .dw 0xe1c0, 0xc03d, 0xe1ff, 0xc03d, 0x21, 0 + .dw 0xe240, 0xc03d, 0xe27f, 0xc03d, 0x21, 0 + .dw 0xe2c0, 0xc03d, 0xe2ff, 0xc03d, 0x21, 0 + .dw 0xe340, 0xc03d, 0xe37f, 0xc03d, 0x21, 0 + .dw 0xe3c0, 0xc03d, 0xe3ff, 0xc03d, 0x21, 0 + .dw 0xe440, 0xc03d, 0xe47f, 0xc03d, 0x21, 0 + .dw 0xe4c0, 0xc03d, 0xe4ff, 0xc03d, 0x21, 0 + .dw 0xe540, 0xc03d, 0xe57f, 0xc03d, 0x21, 0 + .dw 0xe5c0, 0xc03d, 0xe5ff, 0xc03d, 0x21, 0 + .dw 0xe640, 0xc03d, 0xe67f, 0xc03d, 0x21, 0 + .dw 0xe6c0, 0xc03d, 0xe6ff, 0xc03d, 0x21, 0 + .dw 0xe740, 0xc03d, 0xe77f, 0xc03d, 0x21, 0 + .dw 0xe7c0, 0xc03d, 0xe7ff, 0xc03d, 0x21, 0 + .dw 0xe840, 0xc03d, 0xe87f, 0xc03d, 0x21, 0 + .dw 0xe8c0, 0xc03d, 0xe8ff, 0xc03d, 0x21, 0 + .dw 0xe940, 0xc03d, 0xe97f, 0xc03d, 0x21, 0 + .dw 0xe9c0, 0xc03d, 0xe9ff, 0xc03d, 0x21, 0 + .dw 0xea40, 0xc03d, 0xea7f, 0xc03d, 0x21, 0 + .dw 0xeac0, 0xc03d, 0xeaff, 0xc03d, 0x21, 0 + .dw 0xeb40, 0xc03d, 0xeb7f, 0xc03d, 0x21, 0 + .dw 0xebc0, 0xc03d, 0xebff, 0xc03d, 0x21, 0 + .dw 0xec40, 0xc03d, 0xec7f, 0xc03d, 0x21, 0 + .dw 0xecc0, 0xc03d, 0xecff, 0xc03d, 0x21, 0 + .dw 0xed40, 0xc03d, 0xed7f, 0xc03d, 0x21, 0 + .dw 0xedc0, 0xc03d, 0xedff, 0xc03d, 0x21, 0 + .dw 0xee40, 0xc03d, 0xee7f, 0xc03d, 0x21, 0 + .dw 0xeec0, 0xc03d, 0xeeff, 0xc03d, 0x21, 0 + .dw 0xef40, 0xc03d, 0xef7f, 0xc03d, 0x21, 0 + .dw 0xefc0, 0xc03d, 0xefff, 0xc03d, 0x21, 0 + .dw 0xf040, 0xc03d, 0xf07f, 0xc03d, 0x21, 0 + .dw 0xf0c0, 0xc03d, 0xf0ff, 0xc03d, 0x21, 0 + .dw 0xf140, 0xc03d, 0xf17f, 0xc03d, 0x21, 0 + .dw 0xf1c0, 0xc03d, 0xf1ff, 0xc03d, 0x21, 0 + .dw 0xf240, 0xc03d, 0xf27f, 0xc03d, 0x21, 0 + .dw 0xf2c0, 0xc03d, 0xf2ff, 0xc03d, 0x21, 0 + .dw 0xf340, 0xc03d, 0xf37f, 0xc03d, 0x21, 0 + .dw 0xf3c0, 0xc03d, 0xf3ff, 0xc03d, 0x21, 0 + .dw 0xf440, 0xc03d, 0xf47f, 0xc03d, 0x21, 0 + .dw 0xf4c0, 0xc03d, 0xf4ff, 0xc03d, 0x21, 0 + .dw 0xf540, 0xc03d, 0xf57f, 0xc03d, 0x21, 0 + .dw 0xf5c0, 0xc03d, 0xf5ff, 0xc03d, 0x21, 0 + .dw 0xf640, 0xc03d, 0xf67f, 0xc03d, 0x21, 0 + .dw 0xf6c0, 0xc03d, 0xf6ff, 0xc03d, 0x21, 0 + .dw 0xf740, 0xc03d, 0xf77f, 0xc03d, 0x21, 0 + .dw 0xf7c0, 0xc03d, 0xf7ff, 0xc03d, 0x21, 0 + .dw 0xf840, 0xc03d, 0xf87f, 0xc03d, 0x21, 0 + .dw 0xf8c0, 0xc03d, 0xf8ff, 0xc03d, 0x21, 0 + .dw 0xf940, 0xc03d, 0xf97f, 0xc03d, 0x21, 0 + .dw 0xf9c0, 0xc03d, 0xffff, 0xc03d, 0x21, 0 + .dw 0x0040, 0xc03e, 0x007f, 0xc03e, 0x21, 0 + .dw 0x00c0, 0xc03e, 0x00ff, 0xc03e, 0x21, 0 + .dw 0x0140, 0xc03e, 0x017f, 0xc03e, 0x21, 0 + .dw 0x01c0, 0xc03e, 0x01ff, 0xc03e, 0x21, 0 + .dw 0x0240, 0xc03e, 0x027f, 0xc03e, 0x21, 0 + .dw 0x02c0, 0xc03e, 0x02ff, 0xc03e, 0x21, 0 + .dw 0x0340, 0xc03e, 0x037f, 0xc03e, 0x21, 0 + .dw 0x03c0, 0xc03e, 0x03ff, 0xc03e, 0x21, 0 + .dw 0x0440, 0xc03e, 0x047f, 0xc03e, 0x21, 0 + .dw 0x04c0, 0xc03e, 0x04ff, 0xc03e, 0x21, 0 + .dw 0x0540, 0xc03e, 0x057f, 0xc03e, 0x21, 0 + .dw 0x05c0, 0xc03e, 0x05ff, 0xc03e, 0x21, 0 + .dw 0x0640, 0xc03e, 0x067f, 0xc03e, 0x21, 0 + .dw 0x06c0, 0xc03e, 0x06ff, 0xc03e, 0x21, 0 + .dw 0x0740, 0xc03e, 0x077f, 0xc03e, 0x21, 0 + .dw 0x07c0, 0xc03e, 0x07ff, 0xc03e, 0x21, 0 + .dw 0x0840, 0xc03e, 0x087f, 0xc03e, 0x21, 0 + .dw 0x08c0, 0xc03e, 0x08ff, 0xc03e, 0x21, 0 + .dw 0x0940, 0xc03e, 0x097f, 0xc03e, 0x21, 0 + .dw 0x09c0, 0xc03e, 0x09ff, 0xc03e, 0x21, 0 + .dw 0x0a40, 0xc03e, 0x0a7f, 0xc03e, 0x21, 0 + .dw 0x0ac0, 0xc03e, 0x0aff, 0xc03e, 0x21, 0 + .dw 0x0b40, 0xc03e, 0x0b7f, 0xc03e, 0x21, 0 + .dw 0x0bc0, 0xc03e, 0x0bff, 0xc03e, 0x21, 0 + .dw 0x0c40, 0xc03e, 0x0c7f, 0xc03e, 0x21, 0 + .dw 0x0cc0, 0xc03e, 0x0cff, 0xc03e, 0x21, 0 + .dw 0x0d40, 0xc03e, 0x0d7f, 0xc03e, 0x21, 0 + .dw 0x0dc0, 0xc03e, 0x0dff, 0xc03e, 0x21, 0 + .dw 0x0e40, 0xc03e, 0x0e7f, 0xc03e, 0x21, 0 + .dw 0x0ec0, 0xc03e, 0x0eff, 0xc03e, 0x21, 0 + .dw 0x0f40, 0xc03e, 0x0f7f, 0xc03e, 0x21, 0 + .dw 0x0fc0, 0xc03e, 0x0fff, 0xc03e, 0x21, 0 + .dw 0x1040, 0xc03e, 0x107f, 0xc03e, 0x21, 0 + .dw 0x10c0, 0xc03e, 0x10ff, 0xc03e, 0x21, 0 + .dw 0x1140, 0xc03e, 0x117f, 0xc03e, 0x21, 0 + .dw 0x11c0, 0xc03e, 0x11ff, 0xc03e, 0x21, 0 + .dw 0x1240, 0xc03e, 0x127f, 0xc03e, 0x21, 0 + .dw 0x12c0, 0xc03e, 0x12ff, 0xc03e, 0x21, 0 + .dw 0x1340, 0xc03e, 0x137f, 0xc03e, 0x21, 0 + .dw 0x13c0, 0xc03e, 0x13ff, 0xc03e, 0x21, 0 + .dw 0x1440, 0xc03e, 0x147f, 0xc03e, 0x21, 0 + .dw 0x14c0, 0xc03e, 0x14ff, 0xc03e, 0x21, 0 + .dw 0x1540, 0xc03e, 0x157f, 0xc03e, 0x21, 0 + .dw 0x15c0, 0xc03e, 0x15ff, 0xc03e, 0x21, 0 + .dw 0x1640, 0xc03e, 0x167f, 0xc03e, 0x21, 0 + .dw 0x16c0, 0xc03e, 0x16ff, 0xc03e, 0x21, 0 + .dw 0x1740, 0xc03e, 0x177f, 0xc03e, 0x21, 0 + .dw 0x17c0, 0xc03e, 0x17ff, 0xc03e, 0x21, 0 + .dw 0x1840, 0xc03e, 0x187f, 0xc03e, 0x21, 0 + .dw 0x18c0, 0xc03e, 0x18ff, 0xc03e, 0x21, 0 + .dw 0x1940, 0xc03e, 0x197f, 0xc03e, 0x21, 0 + .dw 0x19c0, 0xc03e, 0x1fff, 0xc03e, 0x21, 0 + .dw 0x2040, 0xc03e, 0x207f, 0xc03e, 0x21, 0 + .dw 0x20c0, 0xc03e, 0x20ff, 0xc03e, 0x21, 0 + .dw 0x2140, 0xc03e, 0x217f, 0xc03e, 0x21, 0 + .dw 0x21c0, 0xc03e, 0x21ff, 0xc03e, 0x21, 0 + .dw 0x2240, 0xc03e, 0x227f, 0xc03e, 0x21, 0 + .dw 0x22c0, 0xc03e, 0x22ff, 0xc03e, 0x21, 0 + .dw 0x2340, 0xc03e, 0x237f, 0xc03e, 0x21, 0 + .dw 0x23c0, 0xc03e, 0x23ff, 0xc03e, 0x21, 0 + .dw 0x2440, 0xc03e, 0x247f, 0xc03e, 0x21, 0 + .dw 0x24c0, 0xc03e, 0x24ff, 0xc03e, 0x21, 0 + .dw 0x2540, 0xc03e, 0x257f, 0xc03e, 0x21, 0 + .dw 0x25c0, 0xc03e, 0x25ff, 0xc03e, 0x21, 0 + .dw 0x2640, 0xc03e, 0x267f, 0xc03e, 0x21, 0 + .dw 0x26c0, 0xc03e, 0x26ff, 0xc03e, 0x21, 0 + .dw 0x2740, 0xc03e, 0x277f, 0xc03e, 0x21, 0 + .dw 0x27c0, 0xc03e, 0x27ff, 0xc03e, 0x21, 0 + .dw 0x2840, 0xc03e, 0x287f, 0xc03e, 0x21, 0 + .dw 0x28c0, 0xc03e, 0x28ff, 0xc03e, 0x21, 0 + .dw 0x2940, 0xc03e, 0x297f, 0xc03e, 0x21, 0 + .dw 0x29c0, 0xc03e, 0x29ff, 0xc03e, 0x21, 0 + .dw 0x2a40, 0xc03e, 0x2a7f, 0xc03e, 0x21, 0 + .dw 0x2ac0, 0xc03e, 0x2aff, 0xc03e, 0x21, 0 + .dw 0x2b40, 0xc03e, 0x2b7f, 0xc03e, 0x21, 0 + .dw 0x2bc0, 0xc03e, 0x2bff, 0xc03e, 0x21, 0 + .dw 0x2c40, 0xc03e, 0x2c7f, 0xc03e, 0x21, 0 + .dw 0x2cc0, 0xc03e, 0x2cff, 0xc03e, 0x21, 0 + .dw 0x2d40, 0xc03e, 0x2d7f, 0xc03e, 0x21, 0 + .dw 0x2dc0, 0xc03e, 0x2dff, 0xc03e, 0x21, 0 + .dw 0x2e40, 0xc03e, 0x2e7f, 0xc03e, 0x21, 0 + .dw 0x2ec0, 0xc03e, 0x2eff, 0xc03e, 0x21, 0 + .dw 0x2f40, 0xc03e, 0x2f7f, 0xc03e, 0x21, 0 + .dw 0x2fc0, 0xc03e, 0x2fff, 0xc03e, 0x21, 0 + .dw 0x3040, 0xc03e, 0x307f, 0xc03e, 0x21, 0 + .dw 0x30c0, 0xc03e, 0x30ff, 0xc03e, 0x21, 0 + .dw 0x3140, 0xc03e, 0x317f, 0xc03e, 0x21, 0 + .dw 0x31c0, 0xc03e, 0x31ff, 0xc03e, 0x21, 0 + .dw 0x3240, 0xc03e, 0x327f, 0xc03e, 0x21, 0 + .dw 0x32c0, 0xc03e, 0x32ff, 0xc03e, 0x21, 0 + .dw 0x3340, 0xc03e, 0x337f, 0xc03e, 0x21, 0 + .dw 0x33c0, 0xc03e, 0x33ff, 0xc03e, 0x21, 0 + .dw 0x3440, 0xc03e, 0x347f, 0xc03e, 0x21, 0 + .dw 0x34c0, 0xc03e, 0x34ff, 0xc03e, 0x21, 0 + .dw 0x3540, 0xc03e, 0x357f, 0xc03e, 0x21, 0 + .dw 0x35c0, 0xc03e, 0x35ff, 0xc03e, 0x21, 0 + .dw 0x3640, 0xc03e, 0x367f, 0xc03e, 0x21, 0 + .dw 0x36c0, 0xc03e, 0x36ff, 0xc03e, 0x21, 0 + .dw 0x3740, 0xc03e, 0x377f, 0xc03e, 0x21, 0 + .dw 0x37c0, 0xc03e, 0x37ff, 0xc03e, 0x21, 0 + .dw 0x3840, 0xc03e, 0x387f, 0xc03e, 0x21, 0 + .dw 0x38c0, 0xc03e, 0x38ff, 0xc03e, 0x21, 0 + .dw 0x3940, 0xc03e, 0x397f, 0xc03e, 0x21, 0 + .dw 0x39c0, 0xc03e, 0x3fff, 0xc03e, 0x21, 0 + .dw 0x4040, 0xc03e, 0x407f, 0xc03e, 0x21, 0 + .dw 0x40c0, 0xc03e, 0x40ff, 0xc03e, 0x21, 0 + .dw 0x4140, 0xc03e, 0x417f, 0xc03e, 0x21, 0 + .dw 0x41c0, 0xc03e, 0x41ff, 0xc03e, 0x21, 0 + .dw 0x4240, 0xc03e, 0x427f, 0xc03e, 0x21, 0 + .dw 0x42c0, 0xc03e, 0x42ff, 0xc03e, 0x21, 0 + .dw 0x4340, 0xc03e, 0x437f, 0xc03e, 0x21, 0 + .dw 0x43c0, 0xc03e, 0x43ff, 0xc03e, 0x21, 0 + .dw 0x4440, 0xc03e, 0x447f, 0xc03e, 0x21, 0 + .dw 0x44c0, 0xc03e, 0x44ff, 0xc03e, 0x21, 0 + .dw 0x4540, 0xc03e, 0x457f, 0xc03e, 0x21, 0 + .dw 0x45c0, 0xc03e, 0x45ff, 0xc03e, 0x21, 0 + .dw 0x4640, 0xc03e, 0x467f, 0xc03e, 0x21, 0 + .dw 0x46c0, 0xc03e, 0x46ff, 0xc03e, 0x21, 0 + .dw 0x4740, 0xc03e, 0x477f, 0xc03e, 0x21, 0 + .dw 0x47c0, 0xc03e, 0x47ff, 0xc03e, 0x21, 0 + .dw 0x4840, 0xc03e, 0x487f, 0xc03e, 0x21, 0 + .dw 0x48c0, 0xc03e, 0x48ff, 0xc03e, 0x21, 0 + .dw 0x4940, 0xc03e, 0x497f, 0xc03e, 0x21, 0 + .dw 0x49c0, 0xc03e, 0x49ff, 0xc03e, 0x21, 0 + .dw 0x4a40, 0xc03e, 0x4a7f, 0xc03e, 0x21, 0 + .dw 0x4ac0, 0xc03e, 0x4aff, 0xc03e, 0x21, 0 + .dw 0x4b40, 0xc03e, 0x4b7f, 0xc03e, 0x21, 0 + .dw 0x4bc0, 0xc03e, 0x4bff, 0xc03e, 0x21, 0 + .dw 0x4c40, 0xc03e, 0x4c7f, 0xc03e, 0x21, 0 + .dw 0x4cc0, 0xc03e, 0x4cff, 0xc03e, 0x21, 0 + .dw 0x4d40, 0xc03e, 0x4d7f, 0xc03e, 0x21, 0 + .dw 0x4dc0, 0xc03e, 0x4dff, 0xc03e, 0x21, 0 + .dw 0x4e40, 0xc03e, 0x4e7f, 0xc03e, 0x21, 0 + .dw 0x4ec0, 0xc03e, 0x4eff, 0xc03e, 0x21, 0 + .dw 0x4f40, 0xc03e, 0x4f7f, 0xc03e, 0x21, 0 + .dw 0x4fc0, 0xc03e, 0x4fff, 0xc03e, 0x21, 0 + .dw 0x5040, 0xc03e, 0x507f, 0xc03e, 0x21, 0 + .dw 0x50c0, 0xc03e, 0x50ff, 0xc03e, 0x21, 0 + .dw 0x5140, 0xc03e, 0x517f, 0xc03e, 0x21, 0 + .dw 0x51c0, 0xc03e, 0x51ff, 0xc03e, 0x21, 0 + .dw 0x5240, 0xc03e, 0x527f, 0xc03e, 0x21, 0 + .dw 0x52c0, 0xc03e, 0x52ff, 0xc03e, 0x21, 0 + .dw 0x5340, 0xc03e, 0x537f, 0xc03e, 0x21, 0 + .dw 0x53c0, 0xc03e, 0x53ff, 0xc03e, 0x21, 0 + .dw 0x5440, 0xc03e, 0x547f, 0xc03e, 0x21, 0 + .dw 0x54c0, 0xc03e, 0x54ff, 0xc03e, 0x21, 0 + .dw 0x5540, 0xc03e, 0x557f, 0xc03e, 0x21, 0 + .dw 0x55c0, 0xc03e, 0x55ff, 0xc03e, 0x21, 0 + .dw 0x5640, 0xc03e, 0x567f, 0xc03e, 0x21, 0 + .dw 0x56c0, 0xc03e, 0x56ff, 0xc03e, 0x21, 0 + .dw 0x5740, 0xc03e, 0x577f, 0xc03e, 0x21, 0 + .dw 0x57c0, 0xc03e, 0x57ff, 0xc03e, 0x21, 0 + .dw 0x5840, 0xc03e, 0x587f, 0xc03e, 0x21, 0 + .dw 0x58c0, 0xc03e, 0x58ff, 0xc03e, 0x21, 0 + .dw 0x5940, 0xc03e, 0x597f, 0xc03e, 0x21, 0 + .dw 0x59c0, 0xc03e, 0x5fff, 0xc03e, 0x21, 0 + .dw 0x6040, 0xc03e, 0x607f, 0xc03e, 0x21, 0 + .dw 0x60c0, 0xc03e, 0x60ff, 0xc03e, 0x21, 0 + .dw 0x6140, 0xc03e, 0x617f, 0xc03e, 0x21, 0 + .dw 0x61c0, 0xc03e, 0x61ff, 0xc03e, 0x21, 0 + .dw 0x6240, 0xc03e, 0x627f, 0xc03e, 0x21, 0 + .dw 0x62c0, 0xc03e, 0x62ff, 0xc03e, 0x21, 0 + .dw 0x6340, 0xc03e, 0x637f, 0xc03e, 0x21, 0 + .dw 0x63c0, 0xc03e, 0x63ff, 0xc03e, 0x21, 0 + .dw 0x6440, 0xc03e, 0x647f, 0xc03e, 0x21, 0 + .dw 0x64c0, 0xc03e, 0x64ff, 0xc03e, 0x21, 0 + .dw 0x6540, 0xc03e, 0x657f, 0xc03e, 0x21, 0 + .dw 0x65c0, 0xc03e, 0x65ff, 0xc03e, 0x21, 0 + .dw 0x6640, 0xc03e, 0x667f, 0xc03e, 0x21, 0 + .dw 0x66c0, 0xc03e, 0x66ff, 0xc03e, 0x21, 0 + .dw 0x6740, 0xc03e, 0x677f, 0xc03e, 0x21, 0 + .dw 0x67c0, 0xc03e, 0x67ff, 0xc03e, 0x21, 0 + .dw 0x6840, 0xc03e, 0x687f, 0xc03e, 0x21, 0 + .dw 0x68c0, 0xc03e, 0x68ff, 0xc03e, 0x21, 0 + .dw 0x6940, 0xc03e, 0x697f, 0xc03e, 0x21, 0 + .dw 0x69c0, 0xc03e, 0x69ff, 0xc03e, 0x21, 0 + .dw 0x6a40, 0xc03e, 0x6a7f, 0xc03e, 0x21, 0 + .dw 0x6ac0, 0xc03e, 0x6aff, 0xc03e, 0x21, 0 + .dw 0x6b40, 0xc03e, 0x6b7f, 0xc03e, 0x21, 0 + .dw 0x6bc0, 0xc03e, 0x6bff, 0xc03e, 0x21, 0 + .dw 0x6c40, 0xc03e, 0x6c7f, 0xc03e, 0x21, 0 + .dw 0x6cc0, 0xc03e, 0x6cff, 0xc03e, 0x21, 0 + .dw 0x6d40, 0xc03e, 0x6d7f, 0xc03e, 0x21, 0 + .dw 0x6dc0, 0xc03e, 0x6dff, 0xc03e, 0x21, 0 + .dw 0x6e40, 0xc03e, 0x6e7f, 0xc03e, 0x21, 0 + .dw 0x6ec0, 0xc03e, 0x6eff, 0xc03e, 0x21, 0 + .dw 0x6f40, 0xc03e, 0x6f7f, 0xc03e, 0x21, 0 + .dw 0x6fc0, 0xc03e, 0x6fff, 0xc03e, 0x21, 0 + .dw 0x7040, 0xc03e, 0x707f, 0xc03e, 0x21, 0 + .dw 0x70c0, 0xc03e, 0x70ff, 0xc03e, 0x21, 0 + .dw 0x7140, 0xc03e, 0x717f, 0xc03e, 0x21, 0 + .dw 0x71c0, 0xc03e, 0x71ff, 0xc03e, 0x21, 0 + .dw 0x7240, 0xc03e, 0x727f, 0xc03e, 0x21, 0 + .dw 0x72c0, 0xc03e, 0x72ff, 0xc03e, 0x21, 0 + .dw 0x7340, 0xc03e, 0x737f, 0xc03e, 0x21, 0 + .dw 0x73c0, 0xc03e, 0x73ff, 0xc03e, 0x21, 0 + .dw 0x7440, 0xc03e, 0x747f, 0xc03e, 0x21, 0 + .dw 0x74c0, 0xc03e, 0x74ff, 0xc03e, 0x21, 0 + .dw 0x7540, 0xc03e, 0x757f, 0xc03e, 0x21, 0 + .dw 0x75c0, 0xc03e, 0x75ff, 0xc03e, 0x21, 0 + .dw 0x7640, 0xc03e, 0x767f, 0xc03e, 0x21, 0 + .dw 0x76c0, 0xc03e, 0x76ff, 0xc03e, 0x21, 0 + .dw 0x7740, 0xc03e, 0x777f, 0xc03e, 0x21, 0 + .dw 0x77c0, 0xc03e, 0x77ff, 0xc03e, 0x21, 0 + .dw 0x7840, 0xc03e, 0x787f, 0xc03e, 0x21, 0 + .dw 0x78c0, 0xc03e, 0x78ff, 0xc03e, 0x21, 0 + .dw 0x7940, 0xc03e, 0x797f, 0xc03e, 0x21, 0 + .dw 0x79c0, 0xc03e, 0x7fff, 0xc03e, 0x21, 0 + .dw 0x8040, 0xc03e, 0x807f, 0xc03e, 0x21, 0 + .dw 0x80c0, 0xc03e, 0x80ff, 0xc03e, 0x21, 0 + .dw 0x8140, 0xc03e, 0x817f, 0xc03e, 0x21, 0 + .dw 0x81c0, 0xc03e, 0x81ff, 0xc03e, 0x21, 0 + .dw 0x8240, 0xc03e, 0x827f, 0xc03e, 0x21, 0 + .dw 0x82c0, 0xc03e, 0x82ff, 0xc03e, 0x21, 0 + .dw 0x8340, 0xc03e, 0x837f, 0xc03e, 0x21, 0 + .dw 0x83c0, 0xc03e, 0x83ff, 0xc03e, 0x21, 0 + .dw 0x8440, 0xc03e, 0x847f, 0xc03e, 0x21, 0 + .dw 0x84c0, 0xc03e, 0x84ff, 0xc03e, 0x21, 0 + .dw 0x8540, 0xc03e, 0x857f, 0xc03e, 0x21, 0 + .dw 0x85c0, 0xc03e, 0x85ff, 0xc03e, 0x21, 0 + .dw 0x8640, 0xc03e, 0x867f, 0xc03e, 0x21, 0 + .dw 0x86c0, 0xc03e, 0x86ff, 0xc03e, 0x21, 0 + .dw 0x8740, 0xc03e, 0x877f, 0xc03e, 0x21, 0 + .dw 0x87c0, 0xc03e, 0x87ff, 0xc03e, 0x21, 0 + .dw 0x8840, 0xc03e, 0x887f, 0xc03e, 0x21, 0 + .dw 0x88c0, 0xc03e, 0x88ff, 0xc03e, 0x21, 0 + .dw 0x8940, 0xc03e, 0x897f, 0xc03e, 0x21, 0 + .dw 0x89c0, 0xc03e, 0x89ff, 0xc03e, 0x21, 0 + .dw 0x8a40, 0xc03e, 0x8a7f, 0xc03e, 0x21, 0 + .dw 0x8ac0, 0xc03e, 0x8aff, 0xc03e, 0x21, 0 + .dw 0x8b40, 0xc03e, 0x8b7f, 0xc03e, 0x21, 0 + .dw 0x8bc0, 0xc03e, 0x8bff, 0xc03e, 0x21, 0 + .dw 0x8c40, 0xc03e, 0x8c7f, 0xc03e, 0x21, 0 + .dw 0x8cc0, 0xc03e, 0x8cff, 0xc03e, 0x21, 0 + .dw 0x8d40, 0xc03e, 0x8d7f, 0xc03e, 0x21, 0 + .dw 0x8dc0, 0xc03e, 0x8dff, 0xc03e, 0x21, 0 + .dw 0x8e40, 0xc03e, 0x8e7f, 0xc03e, 0x21, 0 + .dw 0x8ec0, 0xc03e, 0x8eff, 0xc03e, 0x21, 0 + .dw 0x8f40, 0xc03e, 0x8f7f, 0xc03e, 0x21, 0 + .dw 0x8fc0, 0xc03e, 0x8fff, 0xc03e, 0x21, 0 + .dw 0x9040, 0xc03e, 0x907f, 0xc03e, 0x21, 0 + .dw 0x90c0, 0xc03e, 0x90ff, 0xc03e, 0x21, 0 + .dw 0x9140, 0xc03e, 0x917f, 0xc03e, 0x21, 0 + .dw 0x91c0, 0xc03e, 0x91ff, 0xc03e, 0x21, 0 + .dw 0x9240, 0xc03e, 0x927f, 0xc03e, 0x21, 0 + .dw 0x92c0, 0xc03e, 0x92ff, 0xc03e, 0x21, 0 + .dw 0x9340, 0xc03e, 0x937f, 0xc03e, 0x21, 0 + .dw 0x93c0, 0xc03e, 0x93ff, 0xc03e, 0x21, 0 + .dw 0x9440, 0xc03e, 0x947f, 0xc03e, 0x21, 0 + .dw 0x94c0, 0xc03e, 0x94ff, 0xc03e, 0x21, 0 + .dw 0x9540, 0xc03e, 0x957f, 0xc03e, 0x21, 0 + .dw 0x95c0, 0xc03e, 0x95ff, 0xc03e, 0x21, 0 + .dw 0x9640, 0xc03e, 0x967f, 0xc03e, 0x21, 0 + .dw 0x96c0, 0xc03e, 0x96ff, 0xc03e, 0x21, 0 + .dw 0x9740, 0xc03e, 0x977f, 0xc03e, 0x21, 0 + .dw 0x97c0, 0xc03e, 0x97ff, 0xc03e, 0x21, 0 + .dw 0x9840, 0xc03e, 0x987f, 0xc03e, 0x21, 0 + .dw 0x98c0, 0xc03e, 0x98ff, 0xc03e, 0x21, 0 + .dw 0x9940, 0xc03e, 0x997f, 0xc03e, 0x21, 0 + .dw 0x99c0, 0xc03e, 0x9fff, 0xc03e, 0x21, 0 + .dw 0xa040, 0xc03e, 0xa07f, 0xc03e, 0x21, 0 + .dw 0xa0c0, 0xc03e, 0xa0ff, 0xc03e, 0x21, 0 + .dw 0xa140, 0xc03e, 0xa17f, 0xc03e, 0x21, 0 + .dw 0xa1c0, 0xc03e, 0xa1ff, 0xc03e, 0x21, 0 + .dw 0xa240, 0xc03e, 0xa27f, 0xc03e, 0x21, 0 + .dw 0xa2c0, 0xc03e, 0xa2ff, 0xc03e, 0x21, 0 + .dw 0xa340, 0xc03e, 0xa37f, 0xc03e, 0x21, 0 + .dw 0xa3c0, 0xc03e, 0xa3ff, 0xc03e, 0x21, 0 + .dw 0xa440, 0xc03e, 0xa47f, 0xc03e, 0x21, 0 + .dw 0xa4c0, 0xc03e, 0xa4ff, 0xc03e, 0x21, 0 + .dw 0xa540, 0xc03e, 0xa57f, 0xc03e, 0x21, 0 + .dw 0xa5c0, 0xc03e, 0xa5ff, 0xc03e, 0x21, 0 + .dw 0xa640, 0xc03e, 0xa67f, 0xc03e, 0x21, 0 + .dw 0xa6c0, 0xc03e, 0xa6ff, 0xc03e, 0x21, 0 + .dw 0xa740, 0xc03e, 0xa77f, 0xc03e, 0x21, 0 + .dw 0xa7c0, 0xc03e, 0xa7ff, 0xc03e, 0x21, 0 + .dw 0xa840, 0xc03e, 0xa87f, 0xc03e, 0x21, 0 + .dw 0xa8c0, 0xc03e, 0xa8ff, 0xc03e, 0x21, 0 + .dw 0xa940, 0xc03e, 0xa97f, 0xc03e, 0x21, 0 + .dw 0xa9c0, 0xc03e, 0xa9ff, 0xc03e, 0x21, 0 + .dw 0xaa40, 0xc03e, 0xaa7f, 0xc03e, 0x21, 0 + .dw 0xaac0, 0xc03e, 0xaaff, 0xc03e, 0x21, 0 + .dw 0xab40, 0xc03e, 0xab7f, 0xc03e, 0x21, 0 + .dw 0xabc0, 0xc03e, 0xabff, 0xc03e, 0x21, 0 + .dw 0xac40, 0xc03e, 0xac7f, 0xc03e, 0x21, 0 + .dw 0xacc0, 0xc03e, 0xacff, 0xc03e, 0x21, 0 + .dw 0xad40, 0xc03e, 0xad7f, 0xc03e, 0x21, 0 + .dw 0xadc0, 0xc03e, 0xadff, 0xc03e, 0x21, 0 + .dw 0xae40, 0xc03e, 0xae7f, 0xc03e, 0x21, 0 + .dw 0xaec0, 0xc03e, 0xaeff, 0xc03e, 0x21, 0 + .dw 0xaf40, 0xc03e, 0xaf7f, 0xc03e, 0x21, 0 + .dw 0xafc0, 0xc03e, 0xafff, 0xc03e, 0x21, 0 + .dw 0xb040, 0xc03e, 0xb07f, 0xc03e, 0x21, 0 + .dw 0xb0c0, 0xc03e, 0xb0ff, 0xc03e, 0x21, 0 + .dw 0xb140, 0xc03e, 0xb17f, 0xc03e, 0x21, 0 + .dw 0xb1c0, 0xc03e, 0xb1ff, 0xc03e, 0x21, 0 + .dw 0xb240, 0xc03e, 0xb27f, 0xc03e, 0x21, 0 + .dw 0xb2c0, 0xc03e, 0xb2ff, 0xc03e, 0x21, 0 + .dw 0xb340, 0xc03e, 0xb37f, 0xc03e, 0x21, 0 + .dw 0xb3c0, 0xc03e, 0xb3ff, 0xc03e, 0x21, 0 + .dw 0xb440, 0xc03e, 0xb47f, 0xc03e, 0x21, 0 + .dw 0xb4c0, 0xc03e, 0xb4ff, 0xc03e, 0x21, 0 + .dw 0xb540, 0xc03e, 0xb57f, 0xc03e, 0x21, 0 + .dw 0xb5c0, 0xc03e, 0xb5ff, 0xc03e, 0x21, 0 + .dw 0xb640, 0xc03e, 0xb67f, 0xc03e, 0x21, 0 + .dw 0xb6c0, 0xc03e, 0xb6ff, 0xc03e, 0x21, 0 + .dw 0xb740, 0xc03e, 0xb77f, 0xc03e, 0x21, 0 + .dw 0xb7c0, 0xc03e, 0xb7ff, 0xc03e, 0x21, 0 + .dw 0xb840, 0xc03e, 0xb87f, 0xc03e, 0x21, 0 + .dw 0xb8c0, 0xc03e, 0xb8ff, 0xc03e, 0x21, 0 + .dw 0xb940, 0xc03e, 0xb97f, 0xc03e, 0x21, 0 + .dw 0xb9c0, 0xc03e, 0xbfff, 0xc03e, 0x21, 0 + .dw 0xc040, 0xc03e, 0xc07f, 0xc03e, 0x21, 0 + .dw 0xc0c0, 0xc03e, 0xc0ff, 0xc03e, 0x21, 0 + .dw 0xc140, 0xc03e, 0xc17f, 0xc03e, 0x21, 0 + .dw 0xc1c0, 0xc03e, 0xc1ff, 0xc03e, 0x21, 0 + .dw 0xc240, 0xc03e, 0xc27f, 0xc03e, 0x21, 0 + .dw 0xc2c0, 0xc03e, 0xc2ff, 0xc03e, 0x21, 0 + .dw 0xc340, 0xc03e, 0xc37f, 0xc03e, 0x21, 0 + .dw 0xc3c0, 0xc03e, 0xc3ff, 0xc03e, 0x21, 0 + .dw 0xc440, 0xc03e, 0xc47f, 0xc03e, 0x21, 0 + .dw 0xc4c0, 0xc03e, 0xc4ff, 0xc03e, 0x21, 0 + .dw 0xc540, 0xc03e, 0xc57f, 0xc03e, 0x21, 0 + .dw 0xc5c0, 0xc03e, 0xc5ff, 0xc03e, 0x21, 0 + .dw 0xc640, 0xc03e, 0xc67f, 0xc03e, 0x21, 0 + .dw 0xc6c0, 0xc03e, 0xc6ff, 0xc03e, 0x21, 0 + .dw 0xc740, 0xc03e, 0xc77f, 0xc03e, 0x21, 0 + .dw 0xc7c0, 0xc03e, 0xc7ff, 0xc03e, 0x21, 0 + .dw 0xc840, 0xc03e, 0xc87f, 0xc03e, 0x21, 0 + .dw 0xc8c0, 0xc03e, 0xc8ff, 0xc03e, 0x21, 0 + .dw 0xc940, 0xc03e, 0xc97f, 0xc03e, 0x21, 0 + .dw 0xc9c0, 0xc03e, 0xc9ff, 0xc03e, 0x21, 0 + .dw 0xca40, 0xc03e, 0xca7f, 0xc03e, 0x21, 0 + .dw 0xcac0, 0xc03e, 0xcaff, 0xc03e, 0x21, 0 + .dw 0xcb40, 0xc03e, 0xcb7f, 0xc03e, 0x21, 0 + .dw 0xcbc0, 0xc03e, 0xcbff, 0xc03e, 0x21, 0 + .dw 0xcc40, 0xc03e, 0xcc7f, 0xc03e, 0x21, 0 + .dw 0xccc0, 0xc03e, 0xccff, 0xc03e, 0x21, 0 + .dw 0xcd40, 0xc03e, 0xcd7f, 0xc03e, 0x21, 0 + .dw 0xcdc0, 0xc03e, 0xcdff, 0xc03e, 0x21, 0 + .dw 0xce40, 0xc03e, 0xce7f, 0xc03e, 0x21, 0 + .dw 0xcec0, 0xc03e, 0xceff, 0xc03e, 0x21, 0 + .dw 0xcf40, 0xc03e, 0xcf7f, 0xc03e, 0x21, 0 + .dw 0xcfc0, 0xc03e, 0xcfff, 0xc03e, 0x21, 0 + .dw 0xd040, 0xc03e, 0xd07f, 0xc03e, 0x21, 0 + .dw 0xd0c0, 0xc03e, 0xd0ff, 0xc03e, 0x21, 0 + .dw 0xd140, 0xc03e, 0xd17f, 0xc03e, 0x21, 0 + .dw 0xd1c0, 0xc03e, 0xd1ff, 0xc03e, 0x21, 0 + .dw 0xd240, 0xc03e, 0xd27f, 0xc03e, 0x21, 0 + .dw 0xd2c0, 0xc03e, 0xd2ff, 0xc03e, 0x21, 0 + .dw 0xd340, 0xc03e, 0xd37f, 0xc03e, 0x21, 0 + .dw 0xd3c0, 0xc03e, 0xd3ff, 0xc03e, 0x21, 0 + .dw 0xd440, 0xc03e, 0xd47f, 0xc03e, 0x21, 0 + .dw 0xd4c0, 0xc03e, 0xd4ff, 0xc03e, 0x21, 0 + .dw 0xd540, 0xc03e, 0xd57f, 0xc03e, 0x21, 0 + .dw 0xd5c0, 0xc03e, 0xd5ff, 0xc03e, 0x21, 0 + .dw 0xd640, 0xc03e, 0xd67f, 0xc03e, 0x21, 0 + .dw 0xd6c0, 0xc03e, 0xd6ff, 0xc03e, 0x21, 0 + .dw 0xd740, 0xc03e, 0xd77f, 0xc03e, 0x21, 0 + .dw 0xd7c0, 0xc03e, 0xd7ff, 0xc03e, 0x21, 0 + .dw 0xd840, 0xc03e, 0xd87f, 0xc03e, 0x21, 0 + .dw 0xd8c0, 0xc03e, 0xd8ff, 0xc03e, 0x21, 0 + .dw 0xd940, 0xc03e, 0xd97f, 0xc03e, 0x21, 0 + .dw 0xd9c0, 0xc03e, 0xdfff, 0xc03e, 0x21, 0 + .dw 0xe040, 0xc03e, 0xe07f, 0xc03e, 0x21, 0 + .dw 0xe0c0, 0xc03e, 0xe0ff, 0xc03e, 0x21, 0 + .dw 0xe140, 0xc03e, 0xe17f, 0xc03e, 0x21, 0 + .dw 0xe1c0, 0xc03e, 0xe1ff, 0xc03e, 0x21, 0 + .dw 0xe240, 0xc03e, 0xe27f, 0xc03e, 0x21, 0 + .dw 0xe2c0, 0xc03e, 0xe2ff, 0xc03e, 0x21, 0 + .dw 0xe340, 0xc03e, 0xe37f, 0xc03e, 0x21, 0 + .dw 0xe3c0, 0xc03e, 0xe3ff, 0xc03e, 0x21, 0 + .dw 0xe440, 0xc03e, 0xe47f, 0xc03e, 0x21, 0 + .dw 0xe4c0, 0xc03e, 0xe4ff, 0xc03e, 0x21, 0 + .dw 0xe540, 0xc03e, 0xe57f, 0xc03e, 0x21, 0 + .dw 0xe5c0, 0xc03e, 0xe5ff, 0xc03e, 0x21, 0 + .dw 0xe640, 0xc03e, 0xe67f, 0xc03e, 0x21, 0 + .dw 0xe6c0, 0xc03e, 0xe6ff, 0xc03e, 0x21, 0 + .dw 0xe740, 0xc03e, 0xe77f, 0xc03e, 0x21, 0 + .dw 0xe7c0, 0xc03e, 0xe7ff, 0xc03e, 0x21, 0 + .dw 0xe840, 0xc03e, 0xe87f, 0xc03e, 0x21, 0 + .dw 0xe8c0, 0xc03e, 0xe8ff, 0xc03e, 0x21, 0 + .dw 0xe940, 0xc03e, 0xe97f, 0xc03e, 0x21, 0 + .dw 0xe9c0, 0xc03e, 0xe9ff, 0xc03e, 0x21, 0 + .dw 0xea40, 0xc03e, 0xea7f, 0xc03e, 0x21, 0 + .dw 0xeac0, 0xc03e, 0xeaff, 0xc03e, 0x21, 0 + .dw 0xeb40, 0xc03e, 0xeb7f, 0xc03e, 0x21, 0 + .dw 0xebc0, 0xc03e, 0xebff, 0xc03e, 0x21, 0 + .dw 0xec40, 0xc03e, 0xec7f, 0xc03e, 0x21, 0 + .dw 0xecc0, 0xc03e, 0xecff, 0xc03e, 0x21, 0 + .dw 0xed40, 0xc03e, 0xed7f, 0xc03e, 0x21, 0 + .dw 0xedc0, 0xc03e, 0xedff, 0xc03e, 0x21, 0 + .dw 0xee40, 0xc03e, 0xee7f, 0xc03e, 0x21, 0 + .dw 0xeec0, 0xc03e, 0xeeff, 0xc03e, 0x21, 0 + .dw 0xef40, 0xc03e, 0xef7f, 0xc03e, 0x21, 0 + .dw 0xefc0, 0xc03e, 0xefff, 0xc03e, 0x21, 0 + .dw 0xf040, 0xc03e, 0xf07f, 0xc03e, 0x21, 0 + .dw 0xf0c0, 0xc03e, 0xf0ff, 0xc03e, 0x21, 0 + .dw 0xf140, 0xc03e, 0xf17f, 0xc03e, 0x21, 0 + .dw 0xf1c0, 0xc03e, 0xf1ff, 0xc03e, 0x21, 0 + .dw 0xf240, 0xc03e, 0xf27f, 0xc03e, 0x21, 0 + .dw 0xf2c0, 0xc03e, 0xf2ff, 0xc03e, 0x21, 0 + .dw 0xf340, 0xc03e, 0xf37f, 0xc03e, 0x21, 0 + .dw 0xf3c0, 0xc03e, 0xf3ff, 0xc03e, 0x21, 0 + .dw 0xf440, 0xc03e, 0xf47f, 0xc03e, 0x21, 0 + .dw 0xf4c0, 0xc03e, 0xf4ff, 0xc03e, 0x21, 0 + .dw 0xf540, 0xc03e, 0xf57f, 0xc03e, 0x21, 0 + .dw 0xf5c0, 0xc03e, 0xf5ff, 0xc03e, 0x21, 0 + .dw 0xf640, 0xc03e, 0xf67f, 0xc03e, 0x21, 0 + .dw 0xf6c0, 0xc03e, 0xf6ff, 0xc03e, 0x21, 0 + .dw 0xf740, 0xc03e, 0xf77f, 0xc03e, 0x21, 0 + .dw 0xf7c0, 0xc03e, 0xf7ff, 0xc03e, 0x21, 0 + .dw 0xf840, 0xc03e, 0xf87f, 0xc03e, 0x21, 0 + .dw 0xf8c0, 0xc03e, 0xf8ff, 0xc03e, 0x21, 0 + .dw 0xf940, 0xc03e, 0xf97f, 0xc03e, 0x21, 0 + .dw 0xf9c0, 0xc03e, 0xffff, 0xc03e, 0x21, 0 + .dw 0x0040, 0xc03f, 0x007f, 0xc03f, 0x21, 0 + .dw 0x00c0, 0xc03f, 0x00ff, 0xc03f, 0x21, 0 + .dw 0x0140, 0xc03f, 0x017f, 0xc03f, 0x21, 0 + .dw 0x01c0, 0xc03f, 0x01ff, 0xc03f, 0x21, 0 + .dw 0x0240, 0xc03f, 0x027f, 0xc03f, 0x21, 0 + .dw 0x02c0, 0xc03f, 0x02ff, 0xc03f, 0x21, 0 + .dw 0x0340, 0xc03f, 0x037f, 0xc03f, 0x21, 0 + .dw 0x03c0, 0xc03f, 0x03ff, 0xc03f, 0x21, 0 + .dw 0x0440, 0xc03f, 0x047f, 0xc03f, 0x21, 0 + .dw 0x04c0, 0xc03f, 0x04ff, 0xc03f, 0x21, 0 + .dw 0x0540, 0xc03f, 0x057f, 0xc03f, 0x21, 0 + .dw 0x05c0, 0xc03f, 0x05ff, 0xc03f, 0x21, 0 + .dw 0x0640, 0xc03f, 0x067f, 0xc03f, 0x21, 0 + .dw 0x06c0, 0xc03f, 0x06ff, 0xc03f, 0x21, 0 + .dw 0x0740, 0xc03f, 0x077f, 0xc03f, 0x21, 0 + .dw 0x07c0, 0xc03f, 0x07ff, 0xc03f, 0x21, 0 + .dw 0x0840, 0xc03f, 0x087f, 0xc03f, 0x21, 0 + .dw 0x08c0, 0xc03f, 0x08ff, 0xc03f, 0x21, 0 + .dw 0x0940, 0xc03f, 0x097f, 0xc03f, 0x21, 0 + .dw 0x09c0, 0xc03f, 0x09ff, 0xc03f, 0x21, 0 + .dw 0x0a40, 0xc03f, 0x0a7f, 0xc03f, 0x21, 0 + .dw 0x0ac0, 0xc03f, 0x0aff, 0xc03f, 0x21, 0 + .dw 0x0b40, 0xc03f, 0x0b7f, 0xc03f, 0x21, 0 + .dw 0x0bc0, 0xc03f, 0x0bff, 0xc03f, 0x21, 0 + .dw 0x0c40, 0xc03f, 0x0c7f, 0xc03f, 0x21, 0 + .dw 0x0cc0, 0xc03f, 0x0cff, 0xc03f, 0x21, 0 + .dw 0x0d40, 0xc03f, 0x0d7f, 0xc03f, 0x21, 0 + .dw 0x0dc0, 0xc03f, 0x0dff, 0xc03f, 0x21, 0 + .dw 0x0e40, 0xc03f, 0x0e7f, 0xc03f, 0x21, 0 + .dw 0x0ec0, 0xc03f, 0x0eff, 0xc03f, 0x21, 0 + .dw 0x0f40, 0xc03f, 0x0f7f, 0xc03f, 0x21, 0 + .dw 0x0fc0, 0xc03f, 0x0fff, 0xc03f, 0x21, 0 + .dw 0x1040, 0xc03f, 0x107f, 0xc03f, 0x21, 0 + .dw 0x10c0, 0xc03f, 0x10ff, 0xc03f, 0x21, 0 + .dw 0x1140, 0xc03f, 0x117f, 0xc03f, 0x21, 0 + .dw 0x11c0, 0xc03f, 0x11ff, 0xc03f, 0x21, 0 + .dw 0x1240, 0xc03f, 0x127f, 0xc03f, 0x21, 0 + .dw 0x12c0, 0xc03f, 0x12ff, 0xc03f, 0x21, 0 + .dw 0x1340, 0xc03f, 0x137f, 0xc03f, 0x21, 0 + .dw 0x13c0, 0xc03f, 0x13ff, 0xc03f, 0x21, 0 + .dw 0x1440, 0xc03f, 0x147f, 0xc03f, 0x21, 0 + .dw 0x14c0, 0xc03f, 0x14ff, 0xc03f, 0x21, 0 + .dw 0x1540, 0xc03f, 0x157f, 0xc03f, 0x21, 0 + .dw 0x15c0, 0xc03f, 0x15ff, 0xc03f, 0x21, 0 + .dw 0x1640, 0xc03f, 0x167f, 0xc03f, 0x21, 0 + .dw 0x16c0, 0xc03f, 0x16ff, 0xc03f, 0x21, 0 + .dw 0x1740, 0xc03f, 0x177f, 0xc03f, 0x21, 0 + .dw 0x17c0, 0xc03f, 0x17ff, 0xc03f, 0x21, 0 + .dw 0x1840, 0xc03f, 0x187f, 0xc03f, 0x21, 0 + .dw 0x18c0, 0xc03f, 0x18ff, 0xc03f, 0x21, 0 + .dw 0x1940, 0xc03f, 0x197f, 0xc03f, 0x21, 0 + .dw 0x19c0, 0xc03f, 0x1fff, 0xc03f, 0x21, 0 + .dw 0x2040, 0xc03f, 0x207f, 0xc03f, 0x21, 0 + .dw 0x20c0, 0xc03f, 0x20ff, 0xc03f, 0x21, 0 + .dw 0x2140, 0xc03f, 0x217f, 0xc03f, 0x21, 0 + .dw 0x21c0, 0xc03f, 0x21ff, 0xc03f, 0x21, 0 + .dw 0x2240, 0xc03f, 0x227f, 0xc03f, 0x21, 0 + .dw 0x22c0, 0xc03f, 0x22ff, 0xc03f, 0x21, 0 + .dw 0x2340, 0xc03f, 0x237f, 0xc03f, 0x21, 0 + .dw 0x23c0, 0xc03f, 0x23ff, 0xc03f, 0x21, 0 + .dw 0x2440, 0xc03f, 0x247f, 0xc03f, 0x21, 0 + .dw 0x24c0, 0xc03f, 0x24ff, 0xc03f, 0x21, 0 + .dw 0x2540, 0xc03f, 0x257f, 0xc03f, 0x21, 0 + .dw 0x25c0, 0xc03f, 0x25ff, 0xc03f, 0x21, 0 + .dw 0x2640, 0xc03f, 0x267f, 0xc03f, 0x21, 0 + .dw 0x26c0, 0xc03f, 0x26ff, 0xc03f, 0x21, 0 + .dw 0x2740, 0xc03f, 0x277f, 0xc03f, 0x21, 0 + .dw 0x27c0, 0xc03f, 0x27ff, 0xc03f, 0x21, 0 + .dw 0x2840, 0xc03f, 0x287f, 0xc03f, 0x21, 0 + .dw 0x28c0, 0xc03f, 0x28ff, 0xc03f, 0x21, 0 + .dw 0x2940, 0xc03f, 0x297f, 0xc03f, 0x21, 0 + .dw 0x29c0, 0xc03f, 0x29ff, 0xc03f, 0x21, 0 + .dw 0x2a40, 0xc03f, 0x2a7f, 0xc03f, 0x21, 0 + .dw 0x2ac0, 0xc03f, 0x2aff, 0xc03f, 0x21, 0 + .dw 0x2b40, 0xc03f, 0x2b7f, 0xc03f, 0x21, 0 + .dw 0x2bc0, 0xc03f, 0x2bff, 0xc03f, 0x21, 0 + .dw 0x2c40, 0xc03f, 0x2c7f, 0xc03f, 0x21, 0 + .dw 0x2cc0, 0xc03f, 0x2cff, 0xc03f, 0x21, 0 + .dw 0x2d40, 0xc03f, 0x2d7f, 0xc03f, 0x21, 0 + .dw 0x2dc0, 0xc03f, 0x2dff, 0xc03f, 0x21, 0 + .dw 0x2e40, 0xc03f, 0x2e7f, 0xc03f, 0x21, 0 + .dw 0x2ec0, 0xc03f, 0x2eff, 0xc03f, 0x21, 0 + .dw 0x2f40, 0xc03f, 0x2f7f, 0xc03f, 0x21, 0 + .dw 0x2fc0, 0xc03f, 0x2fff, 0xc03f, 0x21, 0 + .dw 0x3040, 0xc03f, 0x307f, 0xc03f, 0x21, 0 + .dw 0x30c0, 0xc03f, 0x30ff, 0xc03f, 0x21, 0 + .dw 0x3140, 0xc03f, 0x317f, 0xc03f, 0x21, 0 + .dw 0x31c0, 0xc03f, 0x31ff, 0xc03f, 0x21, 0 + .dw 0x3240, 0xc03f, 0x327f, 0xc03f, 0x21, 0 + .dw 0x32c0, 0xc03f, 0x32ff, 0xc03f, 0x21, 0 + .dw 0x3340, 0xc03f, 0x337f, 0xc03f, 0x21, 0 + .dw 0x33c0, 0xc03f, 0x33ff, 0xc03f, 0x21, 0 + .dw 0x3440, 0xc03f, 0x347f, 0xc03f, 0x21, 0 + .dw 0x34c0, 0xc03f, 0x34ff, 0xc03f, 0x21, 0 + .dw 0x3540, 0xc03f, 0x357f, 0xc03f, 0x21, 0 + .dw 0x35c0, 0xc03f, 0x35ff, 0xc03f, 0x21, 0 + .dw 0x3640, 0xc03f, 0x367f, 0xc03f, 0x21, 0 + .dw 0x36c0, 0xc03f, 0x36ff, 0xc03f, 0x21, 0 + .dw 0x3740, 0xc03f, 0x377f, 0xc03f, 0x21, 0 + .dw 0x37c0, 0xc03f, 0x37ff, 0xc03f, 0x21, 0 + .dw 0x3840, 0xc03f, 0x387f, 0xc03f, 0x21, 0 + .dw 0x38c0, 0xc03f, 0x38ff, 0xc03f, 0x21, 0 + .dw 0x3940, 0xc03f, 0x397f, 0xc03f, 0x21, 0 + .dw 0x39c0, 0xc03f, 0x1fff, 0xc040, 0x21, 0 + .dw 0x3a00, 0xc040, 0x5fff, 0xc040, 0x21, 0 + .dw 0x7a00, 0xc040, 0x9fff, 0xc040, 0x21, 0 + .dw 0xba00, 0xc040, 0xdfff, 0xc040, 0x21, 0 + .dw 0xfa00, 0xc040, 0x1fff, 0xc041, 0x21, 0 + .dw 0x3a00, 0xc041, 0x5fff, 0xc041, 0x21, 0 + .dw 0x7a00, 0xc041, 0x9fff, 0xc041, 0x21, 0 + .dw 0xba00, 0xc041, 0xdfff, 0xc041, 0x21, 0 + .dw 0xfa00, 0xc041, 0x1fff, 0xc042, 0x21, 0 + .dw 0x3a00, 0xc042, 0x5fff, 0xc042, 0x21, 0 + .dw 0x7a00, 0xc042, 0x9fff, 0xc042, 0x21, 0 + .dw 0xba00, 0xc042, 0xdfff, 0xc042, 0x21, 0 + .dw 0xfa00, 0xc042, 0x1fff, 0xc043, 0x21, 0 + .dw 0x3a00, 0xc043, 0xffff, 0xc043, 0x21, 0 + .dw 0x1a00, 0xc044, 0x1fff, 0xc044, 0x21, 0 + .dw 0x3a00, 0xc044, 0x3fff, 0xc044, 0x21, 0 + .dw 0x5a00, 0xc044, 0x5fff, 0xc044, 0x21, 0 + .dw 0x7a00, 0xc044, 0x7fff, 0xc044, 0x21, 0 + .dw 0x9a00, 0xc044, 0x9fff, 0xc044, 0x21, 0 + .dw 0xba00, 0xc044, 0xbfff, 0xc044, 0x21, 0 + .dw 0xda00, 0xc044, 0xdfff, 0xc044, 0x21, 0 + .dw 0xfa00, 0xc044, 0xffff, 0xc044, 0x21, 0 + .dw 0x1a00, 0xc045, 0x1fff, 0xc045, 0x21, 0 + .dw 0x3a00, 0xc045, 0x3fff, 0xc045, 0x21, 0 + .dw 0x5a00, 0xc045, 0x5fff, 0xc045, 0x21, 0 + .dw 0x7a00, 0xc045, 0x7fff, 0xc045, 0x21, 0 + .dw 0x9a00, 0xc045, 0x9fff, 0xc045, 0x21, 0 + .dw 0xba00, 0xc045, 0xbfff, 0xc045, 0x21, 0 + .dw 0xda00, 0xc045, 0xdfff, 0xc045, 0x21, 0 + .dw 0xfa00, 0xc045, 0xffff, 0xc045, 0x21, 0 + .dw 0x1a00, 0xc046, 0x1fff, 0xc046, 0x21, 0 + .dw 0x3a00, 0xc046, 0x3fff, 0xc046, 0x21, 0 + .dw 0x5a00, 0xc046, 0x5fff, 0xc046, 0x21, 0 + .dw 0x7a00, 0xc046, 0x7fff, 0xc046, 0x21, 0 + .dw 0x9a00, 0xc046, 0x9fff, 0xc046, 0x21, 0 + .dw 0xba00, 0xc046, 0xbfff, 0xc046, 0x21, 0 + .dw 0xda00, 0xc046, 0xdfff, 0xc046, 0x21, 0 + .dw 0xfa00, 0xc046, 0xffff, 0xc046, 0x21, 0 + .dw 0x1a00, 0xc047, 0x1fff, 0xc047, 0x21, 0 + .dw 0x3a00, 0xc047, 0x1fff, 0xc050, 0x21, 0 + .dw 0x3a00, 0xc050, 0x5fff, 0xc050, 0x21, 0 + .dw 0x7a00, 0xc050, 0x9fff, 0xc050, 0x21, 0 + .dw 0xba00, 0xc050, 0xdfff, 0xc050, 0x21, 0 + .dw 0xfa00, 0xc050, 0x1fff, 0xc051, 0x21, 0 + .dw 0x3a00, 0xc051, 0x5fff, 0xc051, 0x21, 0 + .dw 0x7a00, 0xc051, 0x9fff, 0xc051, 0x21, 0 + .dw 0xba00, 0xc051, 0xdfff, 0xc051, 0x21, 0 + .dw 0xfa00, 0xc051, 0x1fff, 0xc052, 0x21, 0 + .dw 0x3a00, 0xc052, 0x5fff, 0xc052, 0x21, 0 + .dw 0x7a00, 0xc052, 0x9fff, 0xc052, 0x21, 0 + .dw 0xba00, 0xc052, 0xdfff, 0xc052, 0x21, 0 + .dw 0xfa00, 0xc052, 0xffff, 0xc053, 0x21, 0 + .dw 0x1a00, 0xc054, 0x1fff, 0xc054, 0x21, 0 + .dw 0x3a00, 0xc054, 0x3fff, 0xc054, 0x21, 0 + .dw 0x5a00, 0xc054, 0x5fff, 0xc054, 0x21, 0 + .dw 0x7a00, 0xc054, 0x7fff, 0xc054, 0x21, 0 + .dw 0x9a00, 0xc054, 0x9fff, 0xc054, 0x21, 0 + .dw 0xba00, 0xc054, 0xbfff, 0xc054, 0x21, 0 + .dw 0xda00, 0xc054, 0xdfff, 0xc054, 0x21, 0 + .dw 0xfa00, 0xc054, 0xffff, 0xc054, 0x21, 0 + .dw 0x1a00, 0xc055, 0x1fff, 0xc055, 0x21, 0 + .dw 0x3a00, 0xc055, 0x3fff, 0xc055, 0x21, 0 + .dw 0x5a00, 0xc055, 0x5fff, 0xc055, 0x21, 0 + .dw 0x7a00, 0xc055, 0x7fff, 0xc055, 0x21, 0 + .dw 0x9a00, 0xc055, 0x9fff, 0xc055, 0x21, 0 + .dw 0xba00, 0xc055, 0xbfff, 0xc055, 0x21, 0 + .dw 0xda00, 0xc055, 0xdfff, 0xc055, 0x21, 0 + .dw 0xfa00, 0xc055, 0xffff, 0xc055, 0x21, 0 + .dw 0x1a00, 0xc056, 0x1fff, 0xc056, 0x21, 0 + .dw 0x3a00, 0xc056, 0x3fff, 0xc056, 0x21, 0 + .dw 0x5a00, 0xc056, 0x5fff, 0xc056, 0x21, 0 + .dw 0x7a00, 0xc056, 0x7fff, 0xc056, 0x21, 0 + .dw 0x9a00, 0xc056, 0x9fff, 0xc056, 0x21, 0 + .dw 0xba00, 0xc056, 0xbfff, 0xc056, 0x21, 0 + .dw 0xda00, 0xc056, 0xdfff, 0xc056, 0x21, 0 + .dw 0xfa00, 0xc056, 0xffff, 0xc056, 0x21, 0 + .dw 0x1a00, 0xc057, 0x1fff, 0xc057, 0x21, 0 + .dw 0x3a00, 0xc057, 0xffff, 0xc05f, 0x21, 0 + .dw 0x1a00, 0xc060, 0x3fff, 0xc060, 0x21, 0 + .dw 0x5a00, 0xc060, 0x7fff, 0xc060, 0x21, 0 + .dw 0x9a00, 0xc060, 0xbfff, 0xc060, 0x21, 0 + .dw 0xda00, 0xc060, 0xffff, 0xc060, 0x21, 0 + .dw 0x1a00, 0xc061, 0x3fff, 0xc061, 0x21, 0 + .dw 0x5a00, 0xc061, 0x7fff, 0xc061, 0x21, 0 + .dw 0x9a00, 0xc061, 0xbfff, 0xc061, 0x21, 0 + .dw 0xda00, 0xc061, 0xffff, 0xc061, 0x21, 0 + .dw 0x1a00, 0xc062, 0x3fff, 0xc062, 0x21, 0 + .dw 0x5a00, 0xc062, 0x7fff, 0xc062, 0x21, 0 + .dw 0x9a00, 0xc062, 0xbfff, 0xc062, 0x21, 0 + .dw 0xda00, 0xc062, 0xffff, 0xc062, 0x21, 0 + .dw 0x1a00, 0xc063, 0xffff, 0xc06f, 0x21, 0 + .dw 0x1a00, 0xc070, 0x3fff, 0xc070, 0x21, 0 + .dw 0x5a00, 0xc070, 0x7fff, 0xc070, 0x21, 0 + .dw 0x9a00, 0xc070, 0xbfff, 0xc070, 0x21, 0 + .dw 0xda00, 0xc070, 0xffff, 0xc070, 0x21, 0 + .dw 0x1a00, 0xc071, 0x3fff, 0xc071, 0x21, 0 + .dw 0x5a00, 0xc071, 0x7fff, 0xc071, 0x21, 0 + .dw 0x9a00, 0xc071, 0xbfff, 0xc071, 0x21, 0 + .dw 0xda00, 0xc071, 0xffff, 0xc071, 0x21, 0 + .dw 0x1a00, 0xc072, 0x3fff, 0xc072, 0x21, 0 + .dw 0x5a00, 0xc072, 0x7fff, 0xc072, 0x21, 0 + .dw 0x9a00, 0xc072, 0xbfff, 0xc072, 0x21, 0 + .dw 0xda00, 0xc072, 0xffff, 0xc07f, 0x21, 0 + .dw 0x1a00, 0xc080, 0x1fff, 0xc080, 0x21, 0 + .dw 0x3a00, 0xc080, 0x3fff, 0xc080, 0x21, 0 + .dw 0x5a00, 0xc080, 0x5fff, 0xc080, 0x21, 0 + .dw 0x7a00, 0xc080, 0x7fff, 0xc080, 0x21, 0 + .dw 0x9a00, 0xc080, 0x9fff, 0xc080, 0x21, 0 + .dw 0xba00, 0xc080, 0xbfff, 0xc080, 0x21, 0 + .dw 0xda00, 0xc080, 0xdfff, 0xc080, 0x21, 0 + .dw 0xfa00, 0xc080, 0xffff, 0xc080, 0x21, 0 + .dw 0x1a00, 0xc081, 0x1fff, 0xc081, 0x21, 0 + .dw 0x3a00, 0xc081, 0x3fff, 0xc081, 0x21, 0 + .dw 0x5a00, 0xc081, 0x5fff, 0xc081, 0x21, 0 + .dw 0x7a00, 0xc081, 0x7fff, 0xc081, 0x21, 0 + .dw 0x9a00, 0xc081, 0x9fff, 0xc081, 0x21, 0 + .dw 0xba00, 0xc081, 0xbfff, 0xc081, 0x21, 0 + .dw 0xda00, 0xc081, 0xdfff, 0xc081, 0x21, 0 + .dw 0xfa00, 0xc081, 0xffff, 0xc081, 0x21, 0 + .dw 0x1a00, 0xc082, 0x1fff, 0xc082, 0x21, 0 + .dw 0x3a00, 0xc082, 0x3fff, 0xc082, 0x21, 0 + .dw 0x5a00, 0xc082, 0x5fff, 0xc082, 0x21, 0 + .dw 0x7a00, 0xc082, 0x7fff, 0xc082, 0x21, 0 + .dw 0x9a00, 0xc082, 0x9fff, 0xc082, 0x21, 0 + .dw 0xba00, 0xc082, 0xbfff, 0xc082, 0x21, 0 + .dw 0xda00, 0xc082, 0xdfff, 0xc082, 0x21, 0 + .dw 0xfa00, 0xc082, 0xffff, 0xc082, 0x21, 0 + .dw 0x1a00, 0xc083, 0x1fff, 0xc083, 0x21, 0 + .dw 0x3a00, 0xc083, 0xffff, 0xc083, 0x21, 0 + .dw 0x1a00, 0xc084, 0x1fff, 0xc084, 0x21, 0 + .dw 0x3a00, 0xc084, 0x3fff, 0xc084, 0x21, 0 + .dw 0x5a00, 0xc084, 0x5fff, 0xc084, 0x21, 0 + .dw 0x7a00, 0xc084, 0x7fff, 0xc084, 0x21, 0 + .dw 0x9a00, 0xc084, 0x9fff, 0xc084, 0x21, 0 + .dw 0xba00, 0xc084, 0xbfff, 0xc084, 0x21, 0 + .dw 0xda00, 0xc084, 0xdfff, 0xc084, 0x21, 0 + .dw 0xfa00, 0xc084, 0xffff, 0xc084, 0x21, 0 + .dw 0x1a00, 0xc085, 0x1fff, 0xc085, 0x21, 0 + .dw 0x3a00, 0xc085, 0x3fff, 0xc085, 0x21, 0 + .dw 0x5a00, 0xc085, 0x5fff, 0xc085, 0x21, 0 + .dw 0x7a00, 0xc085, 0x7fff, 0xc085, 0x21, 0 + .dw 0x9a00, 0xc085, 0x9fff, 0xc085, 0x21, 0 + .dw 0xba00, 0xc085, 0xbfff, 0xc085, 0x21, 0 + .dw 0xda00, 0xc085, 0xdfff, 0xc085, 0x21, 0 + .dw 0xfa00, 0xc085, 0xffff, 0xc085, 0x21, 0 + .dw 0x1a00, 0xc086, 0x1fff, 0xc086, 0x21, 0 + .dw 0x3a00, 0xc086, 0x3fff, 0xc086, 0x21, 0 + .dw 0x5a00, 0xc086, 0x5fff, 0xc086, 0x21, 0 + .dw 0x7a00, 0xc086, 0x7fff, 0xc086, 0x21, 0 + .dw 0x9a00, 0xc086, 0x9fff, 0xc086, 0x21, 0 + .dw 0xba00, 0xc086, 0xbfff, 0xc086, 0x21, 0 + .dw 0xda00, 0xc086, 0xdfff, 0xc086, 0x21, 0 + .dw 0xfa00, 0xc086, 0xffff, 0xc086, 0x21, 0 + .dw 0x1a00, 0xc087, 0x1fff, 0xc087, 0x21, 0 + .dw 0x3a00, 0xc087, 0x1fff, 0xc088, 0x21, 0 + .dw 0x2040, 0xc088, 0x207f, 0xc088, 0x21, 0 + .dw 0x20c0, 0xc088, 0x20ff, 0xc088, 0x21, 0 + .dw 0x2140, 0xc088, 0x217f, 0xc088, 0x21, 0 + .dw 0x21c0, 0xc088, 0x21ff, 0xc088, 0x21, 0 + .dw 0x2240, 0xc088, 0x227f, 0xc088, 0x21, 0 + .dw 0x22c0, 0xc088, 0x22ff, 0xc088, 0x21, 0 + .dw 0x2340, 0xc088, 0x237f, 0xc088, 0x21, 0 + .dw 0x23c0, 0xc088, 0x23ff, 0xc088, 0x21, 0 + .dw 0x2440, 0xc088, 0x247f, 0xc088, 0x21, 0 + .dw 0x24c0, 0xc088, 0x24ff, 0xc088, 0x21, 0 + .dw 0x2540, 0xc088, 0x257f, 0xc088, 0x21, 0 + .dw 0x25c0, 0xc088, 0x25ff, 0xc088, 0x21, 0 + .dw 0x2640, 0xc088, 0x267f, 0xc088, 0x21, 0 + .dw 0x26c0, 0xc088, 0x26ff, 0xc088, 0x21, 0 + .dw 0x2740, 0xc088, 0x277f, 0xc088, 0x21, 0 + .dw 0x27c0, 0xc088, 0x27ff, 0xc088, 0x21, 0 + .dw 0x2840, 0xc088, 0x287f, 0xc088, 0x21, 0 + .dw 0x28c0, 0xc088, 0x28ff, 0xc088, 0x21, 0 + .dw 0x2940, 0xc088, 0x297f, 0xc088, 0x21, 0 + .dw 0x29c0, 0xc088, 0x29ff, 0xc088, 0x21, 0 + .dw 0x2a40, 0xc088, 0x2a7f, 0xc088, 0x21, 0 + .dw 0x2ac0, 0xc088, 0x2aff, 0xc088, 0x21, 0 + .dw 0x2b40, 0xc088, 0x2b7f, 0xc088, 0x21, 0 + .dw 0x2bc0, 0xc088, 0x2bff, 0xc088, 0x21, 0 + .dw 0x2c40, 0xc088, 0x2c7f, 0xc088, 0x21, 0 + .dw 0x2cc0, 0xc088, 0x2cff, 0xc088, 0x21, 0 + .dw 0x2d40, 0xc088, 0x2d7f, 0xc088, 0x21, 0 + .dw 0x2dc0, 0xc088, 0x2dff, 0xc088, 0x21, 0 + .dw 0x2e40, 0xc088, 0x2e7f, 0xc088, 0x21, 0 + .dw 0x2ec0, 0xc088, 0x2eff, 0xc088, 0x21, 0 + .dw 0x2f40, 0xc088, 0x2f7f, 0xc088, 0x21, 0 + .dw 0x2fc0, 0xc088, 0x2fff, 0xc088, 0x21, 0 + .dw 0x3040, 0xc088, 0x307f, 0xc088, 0x21, 0 + .dw 0x30c0, 0xc088, 0x30ff, 0xc088, 0x21, 0 + .dw 0x3140, 0xc088, 0x317f, 0xc088, 0x21, 0 + .dw 0x31c0, 0xc088, 0x31ff, 0xc088, 0x21, 0 + .dw 0x3240, 0xc088, 0x327f, 0xc088, 0x21, 0 + .dw 0x32c0, 0xc088, 0x32ff, 0xc088, 0x21, 0 + .dw 0x3340, 0xc088, 0x337f, 0xc088, 0x21, 0 + .dw 0x33c0, 0xc088, 0x33ff, 0xc088, 0x21, 0 + .dw 0x3440, 0xc088, 0x347f, 0xc088, 0x21, 0 + .dw 0x34c0, 0xc088, 0x34ff, 0xc088, 0x21, 0 + .dw 0x3540, 0xc088, 0x357f, 0xc088, 0x21, 0 + .dw 0x35c0, 0xc088, 0x35ff, 0xc088, 0x21, 0 + .dw 0x3640, 0xc088, 0x367f, 0xc088, 0x21, 0 + .dw 0x36c0, 0xc088, 0x36ff, 0xc088, 0x21, 0 + .dw 0x3740, 0xc088, 0x377f, 0xc088, 0x21, 0 + .dw 0x37c0, 0xc088, 0x37ff, 0xc088, 0x21, 0 + .dw 0x3840, 0xc088, 0x387f, 0xc088, 0x21, 0 + .dw 0x38c0, 0xc088, 0x38ff, 0xc088, 0x21, 0 + .dw 0x3940, 0xc088, 0x397f, 0xc088, 0x21, 0 + .dw 0x39c0, 0xc088, 0x5fff, 0xc088, 0x21, 0 + .dw 0x6040, 0xc088, 0x607f, 0xc088, 0x21, 0 + .dw 0x60c0, 0xc088, 0x60ff, 0xc088, 0x21, 0 + .dw 0x6140, 0xc088, 0x617f, 0xc088, 0x21, 0 + .dw 0x61c0, 0xc088, 0x61ff, 0xc088, 0x21, 0 + .dw 0x6240, 0xc088, 0x627f, 0xc088, 0x21, 0 + .dw 0x62c0, 0xc088, 0x62ff, 0xc088, 0x21, 0 + .dw 0x6340, 0xc088, 0x637f, 0xc088, 0x21, 0 + .dw 0x63c0, 0xc088, 0x63ff, 0xc088, 0x21, 0 + .dw 0x6440, 0xc088, 0x647f, 0xc088, 0x21, 0 + .dw 0x64c0, 0xc088, 0x64ff, 0xc088, 0x21, 0 + .dw 0x6540, 0xc088, 0x657f, 0xc088, 0x21, 0 + .dw 0x65c0, 0xc088, 0x65ff, 0xc088, 0x21, 0 + .dw 0x6640, 0xc088, 0x667f, 0xc088, 0x21, 0 + .dw 0x66c0, 0xc088, 0x66ff, 0xc088, 0x21, 0 + .dw 0x6740, 0xc088, 0x677f, 0xc088, 0x21, 0 + .dw 0x67c0, 0xc088, 0x67ff, 0xc088, 0x21, 0 + .dw 0x6840, 0xc088, 0x687f, 0xc088, 0x21, 0 + .dw 0x68c0, 0xc088, 0x68ff, 0xc088, 0x21, 0 + .dw 0x6940, 0xc088, 0x697f, 0xc088, 0x21, 0 + .dw 0x69c0, 0xc088, 0x69ff, 0xc088, 0x21, 0 + .dw 0x6a40, 0xc088, 0x6a7f, 0xc088, 0x21, 0 + .dw 0x6ac0, 0xc088, 0x6aff, 0xc088, 0x21, 0 + .dw 0x6b40, 0xc088, 0x6b7f, 0xc088, 0x21, 0 + .dw 0x6bc0, 0xc088, 0x6bff, 0xc088, 0x21, 0 + .dw 0x6c40, 0xc088, 0x6c7f, 0xc088, 0x21, 0 + .dw 0x6cc0, 0xc088, 0x6cff, 0xc088, 0x21, 0 + .dw 0x6d40, 0xc088, 0x6d7f, 0xc088, 0x21, 0 + .dw 0x6dc0, 0xc088, 0x6dff, 0xc088, 0x21, 0 + .dw 0x6e40, 0xc088, 0x6e7f, 0xc088, 0x21, 0 + .dw 0x6ec0, 0xc088, 0x6eff, 0xc088, 0x21, 0 + .dw 0x6f40, 0xc088, 0x6f7f, 0xc088, 0x21, 0 + .dw 0x6fc0, 0xc088, 0x6fff, 0xc088, 0x21, 0 + .dw 0x7040, 0xc088, 0x707f, 0xc088, 0x21, 0 + .dw 0x70c0, 0xc088, 0x70ff, 0xc088, 0x21, 0 + .dw 0x7140, 0xc088, 0x717f, 0xc088, 0x21, 0 + .dw 0x71c0, 0xc088, 0x71ff, 0xc088, 0x21, 0 + .dw 0x7240, 0xc088, 0x727f, 0xc088, 0x21, 0 + .dw 0x72c0, 0xc088, 0x72ff, 0xc088, 0x21, 0 + .dw 0x7340, 0xc088, 0x737f, 0xc088, 0x21, 0 + .dw 0x73c0, 0xc088, 0x73ff, 0xc088, 0x21, 0 + .dw 0x7440, 0xc088, 0x747f, 0xc088, 0x21, 0 + .dw 0x74c0, 0xc088, 0x74ff, 0xc088, 0x21, 0 + .dw 0x7540, 0xc088, 0x757f, 0xc088, 0x21, 0 + .dw 0x75c0, 0xc088, 0x75ff, 0xc088, 0x21, 0 + .dw 0x7640, 0xc088, 0x767f, 0xc088, 0x21, 0 + .dw 0x76c0, 0xc088, 0x76ff, 0xc088, 0x21, 0 + .dw 0x7740, 0xc088, 0x777f, 0xc088, 0x21, 0 + .dw 0x77c0, 0xc088, 0x77ff, 0xc088, 0x21, 0 + .dw 0x7840, 0xc088, 0x787f, 0xc088, 0x21, 0 + .dw 0x78c0, 0xc088, 0x78ff, 0xc088, 0x21, 0 + .dw 0x7940, 0xc088, 0x797f, 0xc088, 0x21, 0 + .dw 0x79c0, 0xc088, 0x9fff, 0xc088, 0x21, 0 + .dw 0xa040, 0xc088, 0xa07f, 0xc088, 0x21, 0 + .dw 0xa0c0, 0xc088, 0xa0ff, 0xc088, 0x21, 0 + .dw 0xa140, 0xc088, 0xa17f, 0xc088, 0x21, 0 + .dw 0xa1c0, 0xc088, 0xa1ff, 0xc088, 0x21, 0 + .dw 0xa240, 0xc088, 0xa27f, 0xc088, 0x21, 0 + .dw 0xa2c0, 0xc088, 0xa2ff, 0xc088, 0x21, 0 + .dw 0xa340, 0xc088, 0xa37f, 0xc088, 0x21, 0 + .dw 0xa3c0, 0xc088, 0xa3ff, 0xc088, 0x21, 0 + .dw 0xa440, 0xc088, 0xa47f, 0xc088, 0x21, 0 + .dw 0xa4c0, 0xc088, 0xa4ff, 0xc088, 0x21, 0 + .dw 0xa540, 0xc088, 0xa57f, 0xc088, 0x21, 0 + .dw 0xa5c0, 0xc088, 0xa5ff, 0xc088, 0x21, 0 + .dw 0xa640, 0xc088, 0xa67f, 0xc088, 0x21, 0 + .dw 0xa6c0, 0xc088, 0xa6ff, 0xc088, 0x21, 0 + .dw 0xa740, 0xc088, 0xa77f, 0xc088, 0x21, 0 + .dw 0xa7c0, 0xc088, 0xa7ff, 0xc088, 0x21, 0 + .dw 0xa840, 0xc088, 0xa87f, 0xc088, 0x21, 0 + .dw 0xa8c0, 0xc088, 0xa8ff, 0xc088, 0x21, 0 + .dw 0xa940, 0xc088, 0xa97f, 0xc088, 0x21, 0 + .dw 0xa9c0, 0xc088, 0xa9ff, 0xc088, 0x21, 0 + .dw 0xaa40, 0xc088, 0xaa7f, 0xc088, 0x21, 0 + .dw 0xaac0, 0xc088, 0xaaff, 0xc088, 0x21, 0 + .dw 0xab40, 0xc088, 0xab7f, 0xc088, 0x21, 0 + .dw 0xabc0, 0xc088, 0xabff, 0xc088, 0x21, 0 + .dw 0xac40, 0xc088, 0xac7f, 0xc088, 0x21, 0 + .dw 0xacc0, 0xc088, 0xacff, 0xc088, 0x21, 0 + .dw 0xad40, 0xc088, 0xad7f, 0xc088, 0x21, 0 + .dw 0xadc0, 0xc088, 0xadff, 0xc088, 0x21, 0 + .dw 0xae40, 0xc088, 0xae7f, 0xc088, 0x21, 0 + .dw 0xaec0, 0xc088, 0xaeff, 0xc088, 0x21, 0 + .dw 0xaf40, 0xc088, 0xaf7f, 0xc088, 0x21, 0 + .dw 0xafc0, 0xc088, 0xafff, 0xc088, 0x21, 0 + .dw 0xb040, 0xc088, 0xb07f, 0xc088, 0x21, 0 + .dw 0xb0c0, 0xc088, 0xb0ff, 0xc088, 0x21, 0 + .dw 0xb140, 0xc088, 0xb17f, 0xc088, 0x21, 0 + .dw 0xb1c0, 0xc088, 0xb1ff, 0xc088, 0x21, 0 + .dw 0xb240, 0xc088, 0xb27f, 0xc088, 0x21, 0 + .dw 0xb2c0, 0xc088, 0xb2ff, 0xc088, 0x21, 0 + .dw 0xb340, 0xc088, 0xb37f, 0xc088, 0x21, 0 + .dw 0xb3c0, 0xc088, 0xb3ff, 0xc088, 0x21, 0 + .dw 0xb440, 0xc088, 0xb47f, 0xc088, 0x21, 0 + .dw 0xb4c0, 0xc088, 0xb4ff, 0xc088, 0x21, 0 + .dw 0xb540, 0xc088, 0xb57f, 0xc088, 0x21, 0 + .dw 0xb5c0, 0xc088, 0xb5ff, 0xc088, 0x21, 0 + .dw 0xb640, 0xc088, 0xb67f, 0xc088, 0x21, 0 + .dw 0xb6c0, 0xc088, 0xb6ff, 0xc088, 0x21, 0 + .dw 0xb740, 0xc088, 0xb77f, 0xc088, 0x21, 0 + .dw 0xb7c0, 0xc088, 0xb7ff, 0xc088, 0x21, 0 + .dw 0xb840, 0xc088, 0xb87f, 0xc088, 0x21, 0 + .dw 0xb8c0, 0xc088, 0xb8ff, 0xc088, 0x21, 0 + .dw 0xb940, 0xc088, 0xb97f, 0xc088, 0x21, 0 + .dw 0xb9c0, 0xc088, 0xdfff, 0xc088, 0x21, 0 + .dw 0xe040, 0xc088, 0xe07f, 0xc088, 0x21, 0 + .dw 0xe0c0, 0xc088, 0xe0ff, 0xc088, 0x21, 0 + .dw 0xe140, 0xc088, 0xe17f, 0xc088, 0x21, 0 + .dw 0xe1c0, 0xc088, 0xe1ff, 0xc088, 0x21, 0 + .dw 0xe240, 0xc088, 0xe27f, 0xc088, 0x21, 0 + .dw 0xe2c0, 0xc088, 0xe2ff, 0xc088, 0x21, 0 + .dw 0xe340, 0xc088, 0xe37f, 0xc088, 0x21, 0 + .dw 0xe3c0, 0xc088, 0xe3ff, 0xc088, 0x21, 0 + .dw 0xe440, 0xc088, 0xe47f, 0xc088, 0x21, 0 + .dw 0xe4c0, 0xc088, 0xe4ff, 0xc088, 0x21, 0 + .dw 0xe540, 0xc088, 0xe57f, 0xc088, 0x21, 0 + .dw 0xe5c0, 0xc088, 0xe5ff, 0xc088, 0x21, 0 + .dw 0xe640, 0xc088, 0xe67f, 0xc088, 0x21, 0 + .dw 0xe6c0, 0xc088, 0xe6ff, 0xc088, 0x21, 0 + .dw 0xe740, 0xc088, 0xe77f, 0xc088, 0x21, 0 + .dw 0xe7c0, 0xc088, 0xe7ff, 0xc088, 0x21, 0 + .dw 0xe840, 0xc088, 0xe87f, 0xc088, 0x21, 0 + .dw 0xe8c0, 0xc088, 0xe8ff, 0xc088, 0x21, 0 + .dw 0xe940, 0xc088, 0xe97f, 0xc088, 0x21, 0 + .dw 0xe9c0, 0xc088, 0xe9ff, 0xc088, 0x21, 0 + .dw 0xea40, 0xc088, 0xea7f, 0xc088, 0x21, 0 + .dw 0xeac0, 0xc088, 0xeaff, 0xc088, 0x21, 0 + .dw 0xeb40, 0xc088, 0xeb7f, 0xc088, 0x21, 0 + .dw 0xebc0, 0xc088, 0xebff, 0xc088, 0x21, 0 + .dw 0xec40, 0xc088, 0xec7f, 0xc088, 0x21, 0 + .dw 0xecc0, 0xc088, 0xecff, 0xc088, 0x21, 0 + .dw 0xed40, 0xc088, 0xed7f, 0xc088, 0x21, 0 + .dw 0xedc0, 0xc088, 0xedff, 0xc088, 0x21, 0 + .dw 0xee40, 0xc088, 0xee7f, 0xc088, 0x21, 0 + .dw 0xeec0, 0xc088, 0xeeff, 0xc088, 0x21, 0 + .dw 0xef40, 0xc088, 0xef7f, 0xc088, 0x21, 0 + .dw 0xefc0, 0xc088, 0xefff, 0xc088, 0x21, 0 + .dw 0xf040, 0xc088, 0xf07f, 0xc088, 0x21, 0 + .dw 0xf0c0, 0xc088, 0xf0ff, 0xc088, 0x21, 0 + .dw 0xf140, 0xc088, 0xf17f, 0xc088, 0x21, 0 + .dw 0xf1c0, 0xc088, 0xf1ff, 0xc088, 0x21, 0 + .dw 0xf240, 0xc088, 0xf27f, 0xc088, 0x21, 0 + .dw 0xf2c0, 0xc088, 0xf2ff, 0xc088, 0x21, 0 + .dw 0xf340, 0xc088, 0xf37f, 0xc088, 0x21, 0 + .dw 0xf3c0, 0xc088, 0xf3ff, 0xc088, 0x21, 0 + .dw 0xf440, 0xc088, 0xf47f, 0xc088, 0x21, 0 + .dw 0xf4c0, 0xc088, 0xf4ff, 0xc088, 0x21, 0 + .dw 0xf540, 0xc088, 0xf57f, 0xc088, 0x21, 0 + .dw 0xf5c0, 0xc088, 0xf5ff, 0xc088, 0x21, 0 + .dw 0xf640, 0xc088, 0xf67f, 0xc088, 0x21, 0 + .dw 0xf6c0, 0xc088, 0xf6ff, 0xc088, 0x21, 0 + .dw 0xf740, 0xc088, 0xf77f, 0xc088, 0x21, 0 + .dw 0xf7c0, 0xc088, 0xf7ff, 0xc088, 0x21, 0 + .dw 0xf840, 0xc088, 0xf87f, 0xc088, 0x21, 0 + .dw 0xf8c0, 0xc088, 0xf8ff, 0xc088, 0x21, 0 + .dw 0xf940, 0xc088, 0xf97f, 0xc088, 0x21, 0 + .dw 0xf9c0, 0xc088, 0x1fff, 0xc089, 0x21, 0 + .dw 0x2040, 0xc089, 0x207f, 0xc089, 0x21, 0 + .dw 0x20c0, 0xc089, 0x20ff, 0xc089, 0x21, 0 + .dw 0x2140, 0xc089, 0x217f, 0xc089, 0x21, 0 + .dw 0x21c0, 0xc089, 0x21ff, 0xc089, 0x21, 0 + .dw 0x2240, 0xc089, 0x227f, 0xc089, 0x21, 0 + .dw 0x22c0, 0xc089, 0x22ff, 0xc089, 0x21, 0 + .dw 0x2340, 0xc089, 0x237f, 0xc089, 0x21, 0 + .dw 0x23c0, 0xc089, 0x23ff, 0xc089, 0x21, 0 + .dw 0x2440, 0xc089, 0x247f, 0xc089, 0x21, 0 + .dw 0x24c0, 0xc089, 0x24ff, 0xc089, 0x21, 0 + .dw 0x2540, 0xc089, 0x257f, 0xc089, 0x21, 0 + .dw 0x25c0, 0xc089, 0x25ff, 0xc089, 0x21, 0 + .dw 0x2640, 0xc089, 0x267f, 0xc089, 0x21, 0 + .dw 0x26c0, 0xc089, 0x26ff, 0xc089, 0x21, 0 + .dw 0x2740, 0xc089, 0x277f, 0xc089, 0x21, 0 + .dw 0x27c0, 0xc089, 0x27ff, 0xc089, 0x21, 0 + .dw 0x2840, 0xc089, 0x287f, 0xc089, 0x21, 0 + .dw 0x28c0, 0xc089, 0x28ff, 0xc089, 0x21, 0 + .dw 0x2940, 0xc089, 0x297f, 0xc089, 0x21, 0 + .dw 0x29c0, 0xc089, 0x29ff, 0xc089, 0x21, 0 + .dw 0x2a40, 0xc089, 0x2a7f, 0xc089, 0x21, 0 + .dw 0x2ac0, 0xc089, 0x2aff, 0xc089, 0x21, 0 + .dw 0x2b40, 0xc089, 0x2b7f, 0xc089, 0x21, 0 + .dw 0x2bc0, 0xc089, 0x2bff, 0xc089, 0x21, 0 + .dw 0x2c40, 0xc089, 0x2c7f, 0xc089, 0x21, 0 + .dw 0x2cc0, 0xc089, 0x2cff, 0xc089, 0x21, 0 + .dw 0x2d40, 0xc089, 0x2d7f, 0xc089, 0x21, 0 + .dw 0x2dc0, 0xc089, 0x2dff, 0xc089, 0x21, 0 + .dw 0x2e40, 0xc089, 0x2e7f, 0xc089, 0x21, 0 + .dw 0x2ec0, 0xc089, 0x2eff, 0xc089, 0x21, 0 + .dw 0x2f40, 0xc089, 0x2f7f, 0xc089, 0x21, 0 + .dw 0x2fc0, 0xc089, 0x2fff, 0xc089, 0x21, 0 + .dw 0x3040, 0xc089, 0x307f, 0xc089, 0x21, 0 + .dw 0x30c0, 0xc089, 0x30ff, 0xc089, 0x21, 0 + .dw 0x3140, 0xc089, 0x317f, 0xc089, 0x21, 0 + .dw 0x31c0, 0xc089, 0x31ff, 0xc089, 0x21, 0 + .dw 0x3240, 0xc089, 0x327f, 0xc089, 0x21, 0 + .dw 0x32c0, 0xc089, 0x32ff, 0xc089, 0x21, 0 + .dw 0x3340, 0xc089, 0x337f, 0xc089, 0x21, 0 + .dw 0x33c0, 0xc089, 0x33ff, 0xc089, 0x21, 0 + .dw 0x3440, 0xc089, 0x347f, 0xc089, 0x21, 0 + .dw 0x34c0, 0xc089, 0x34ff, 0xc089, 0x21, 0 + .dw 0x3540, 0xc089, 0x357f, 0xc089, 0x21, 0 + .dw 0x35c0, 0xc089, 0x35ff, 0xc089, 0x21, 0 + .dw 0x3640, 0xc089, 0x367f, 0xc089, 0x21, 0 + .dw 0x36c0, 0xc089, 0x36ff, 0xc089, 0x21, 0 + .dw 0x3740, 0xc089, 0x377f, 0xc089, 0x21, 0 + .dw 0x37c0, 0xc089, 0x37ff, 0xc089, 0x21, 0 + .dw 0x3840, 0xc089, 0x387f, 0xc089, 0x21, 0 + .dw 0x38c0, 0xc089, 0x38ff, 0xc089, 0x21, 0 + .dw 0x3940, 0xc089, 0x397f, 0xc089, 0x21, 0 + .dw 0x39c0, 0xc089, 0x5fff, 0xc089, 0x21, 0 + .dw 0x6040, 0xc089, 0x607f, 0xc089, 0x21, 0 + .dw 0x60c0, 0xc089, 0x60ff, 0xc089, 0x21, 0 + .dw 0x6140, 0xc089, 0x617f, 0xc089, 0x21, 0 + .dw 0x61c0, 0xc089, 0x61ff, 0xc089, 0x21, 0 + .dw 0x6240, 0xc089, 0x627f, 0xc089, 0x21, 0 + .dw 0x62c0, 0xc089, 0x62ff, 0xc089, 0x21, 0 + .dw 0x6340, 0xc089, 0x637f, 0xc089, 0x21, 0 + .dw 0x63c0, 0xc089, 0x63ff, 0xc089, 0x21, 0 + .dw 0x6440, 0xc089, 0x647f, 0xc089, 0x21, 0 + .dw 0x64c0, 0xc089, 0x64ff, 0xc089, 0x21, 0 + .dw 0x6540, 0xc089, 0x657f, 0xc089, 0x21, 0 + .dw 0x65c0, 0xc089, 0x65ff, 0xc089, 0x21, 0 + .dw 0x6640, 0xc089, 0x667f, 0xc089, 0x21, 0 + .dw 0x66c0, 0xc089, 0x66ff, 0xc089, 0x21, 0 + .dw 0x6740, 0xc089, 0x677f, 0xc089, 0x21, 0 + .dw 0x67c0, 0xc089, 0x67ff, 0xc089, 0x21, 0 + .dw 0x6840, 0xc089, 0x687f, 0xc089, 0x21, 0 + .dw 0x68c0, 0xc089, 0x68ff, 0xc089, 0x21, 0 + .dw 0x6940, 0xc089, 0x697f, 0xc089, 0x21, 0 + .dw 0x69c0, 0xc089, 0x69ff, 0xc089, 0x21, 0 + .dw 0x6a40, 0xc089, 0x6a7f, 0xc089, 0x21, 0 + .dw 0x6ac0, 0xc089, 0x6aff, 0xc089, 0x21, 0 + .dw 0x6b40, 0xc089, 0x6b7f, 0xc089, 0x21, 0 + .dw 0x6bc0, 0xc089, 0x6bff, 0xc089, 0x21, 0 + .dw 0x6c40, 0xc089, 0x6c7f, 0xc089, 0x21, 0 + .dw 0x6cc0, 0xc089, 0x6cff, 0xc089, 0x21, 0 + .dw 0x6d40, 0xc089, 0x6d7f, 0xc089, 0x21, 0 + .dw 0x6dc0, 0xc089, 0x6dff, 0xc089, 0x21, 0 + .dw 0x6e40, 0xc089, 0x6e7f, 0xc089, 0x21, 0 + .dw 0x6ec0, 0xc089, 0x6eff, 0xc089, 0x21, 0 + .dw 0x6f40, 0xc089, 0x6f7f, 0xc089, 0x21, 0 + .dw 0x6fc0, 0xc089, 0x6fff, 0xc089, 0x21, 0 + .dw 0x7040, 0xc089, 0x707f, 0xc089, 0x21, 0 + .dw 0x70c0, 0xc089, 0x70ff, 0xc089, 0x21, 0 + .dw 0x7140, 0xc089, 0x717f, 0xc089, 0x21, 0 + .dw 0x71c0, 0xc089, 0x71ff, 0xc089, 0x21, 0 + .dw 0x7240, 0xc089, 0x727f, 0xc089, 0x21, 0 + .dw 0x72c0, 0xc089, 0x72ff, 0xc089, 0x21, 0 + .dw 0x7340, 0xc089, 0x737f, 0xc089, 0x21, 0 + .dw 0x73c0, 0xc089, 0x73ff, 0xc089, 0x21, 0 + .dw 0x7440, 0xc089, 0x747f, 0xc089, 0x21, 0 + .dw 0x74c0, 0xc089, 0x74ff, 0xc089, 0x21, 0 + .dw 0x7540, 0xc089, 0x757f, 0xc089, 0x21, 0 + .dw 0x75c0, 0xc089, 0x75ff, 0xc089, 0x21, 0 + .dw 0x7640, 0xc089, 0x767f, 0xc089, 0x21, 0 + .dw 0x76c0, 0xc089, 0x76ff, 0xc089, 0x21, 0 + .dw 0x7740, 0xc089, 0x777f, 0xc089, 0x21, 0 + .dw 0x77c0, 0xc089, 0x77ff, 0xc089, 0x21, 0 + .dw 0x7840, 0xc089, 0x787f, 0xc089, 0x21, 0 + .dw 0x78c0, 0xc089, 0x78ff, 0xc089, 0x21, 0 + .dw 0x7940, 0xc089, 0x797f, 0xc089, 0x21, 0 + .dw 0x79c0, 0xc089, 0x9fff, 0xc089, 0x21, 0 + .dw 0xa040, 0xc089, 0xa07f, 0xc089, 0x21, 0 + .dw 0xa0c0, 0xc089, 0xa0ff, 0xc089, 0x21, 0 + .dw 0xa140, 0xc089, 0xa17f, 0xc089, 0x21, 0 + .dw 0xa1c0, 0xc089, 0xa1ff, 0xc089, 0x21, 0 + .dw 0xa240, 0xc089, 0xa27f, 0xc089, 0x21, 0 + .dw 0xa2c0, 0xc089, 0xa2ff, 0xc089, 0x21, 0 + .dw 0xa340, 0xc089, 0xa37f, 0xc089, 0x21, 0 + .dw 0xa3c0, 0xc089, 0xa3ff, 0xc089, 0x21, 0 + .dw 0xa440, 0xc089, 0xa47f, 0xc089, 0x21, 0 + .dw 0xa4c0, 0xc089, 0xa4ff, 0xc089, 0x21, 0 + .dw 0xa540, 0xc089, 0xa57f, 0xc089, 0x21, 0 + .dw 0xa5c0, 0xc089, 0xa5ff, 0xc089, 0x21, 0 + .dw 0xa640, 0xc089, 0xa67f, 0xc089, 0x21, 0 + .dw 0xa6c0, 0xc089, 0xa6ff, 0xc089, 0x21, 0 + .dw 0xa740, 0xc089, 0xa77f, 0xc089, 0x21, 0 + .dw 0xa7c0, 0xc089, 0xa7ff, 0xc089, 0x21, 0 + .dw 0xa840, 0xc089, 0xa87f, 0xc089, 0x21, 0 + .dw 0xa8c0, 0xc089, 0xa8ff, 0xc089, 0x21, 0 + .dw 0xa940, 0xc089, 0xa97f, 0xc089, 0x21, 0 + .dw 0xa9c0, 0xc089, 0xa9ff, 0xc089, 0x21, 0 + .dw 0xaa40, 0xc089, 0xaa7f, 0xc089, 0x21, 0 + .dw 0xaac0, 0xc089, 0xaaff, 0xc089, 0x21, 0 + .dw 0xab40, 0xc089, 0xab7f, 0xc089, 0x21, 0 + .dw 0xabc0, 0xc089, 0xabff, 0xc089, 0x21, 0 + .dw 0xac40, 0xc089, 0xac7f, 0xc089, 0x21, 0 + .dw 0xacc0, 0xc089, 0xacff, 0xc089, 0x21, 0 + .dw 0xad40, 0xc089, 0xad7f, 0xc089, 0x21, 0 + .dw 0xadc0, 0xc089, 0xadff, 0xc089, 0x21, 0 + .dw 0xae40, 0xc089, 0xae7f, 0xc089, 0x21, 0 + .dw 0xaec0, 0xc089, 0xaeff, 0xc089, 0x21, 0 + .dw 0xaf40, 0xc089, 0xaf7f, 0xc089, 0x21, 0 + .dw 0xafc0, 0xc089, 0xafff, 0xc089, 0x21, 0 + .dw 0xb040, 0xc089, 0xb07f, 0xc089, 0x21, 0 + .dw 0xb0c0, 0xc089, 0xb0ff, 0xc089, 0x21, 0 + .dw 0xb140, 0xc089, 0xb17f, 0xc089, 0x21, 0 + .dw 0xb1c0, 0xc089, 0xb1ff, 0xc089, 0x21, 0 + .dw 0xb240, 0xc089, 0xb27f, 0xc089, 0x21, 0 + .dw 0xb2c0, 0xc089, 0xb2ff, 0xc089, 0x21, 0 + .dw 0xb340, 0xc089, 0xb37f, 0xc089, 0x21, 0 + .dw 0xb3c0, 0xc089, 0xb3ff, 0xc089, 0x21, 0 + .dw 0xb440, 0xc089, 0xb47f, 0xc089, 0x21, 0 + .dw 0xb4c0, 0xc089, 0xb4ff, 0xc089, 0x21, 0 + .dw 0xb540, 0xc089, 0xb57f, 0xc089, 0x21, 0 + .dw 0xb5c0, 0xc089, 0xb5ff, 0xc089, 0x21, 0 + .dw 0xb640, 0xc089, 0xb67f, 0xc089, 0x21, 0 + .dw 0xb6c0, 0xc089, 0xb6ff, 0xc089, 0x21, 0 + .dw 0xb740, 0xc089, 0xb77f, 0xc089, 0x21, 0 + .dw 0xb7c0, 0xc089, 0xb7ff, 0xc089, 0x21, 0 + .dw 0xb840, 0xc089, 0xb87f, 0xc089, 0x21, 0 + .dw 0xb8c0, 0xc089, 0xb8ff, 0xc089, 0x21, 0 + .dw 0xb940, 0xc089, 0xb97f, 0xc089, 0x21, 0 + .dw 0xb9c0, 0xc089, 0xdfff, 0xc089, 0x21, 0 + .dw 0xe040, 0xc089, 0xe07f, 0xc089, 0x21, 0 + .dw 0xe0c0, 0xc089, 0xe0ff, 0xc089, 0x21, 0 + .dw 0xe140, 0xc089, 0xe17f, 0xc089, 0x21, 0 + .dw 0xe1c0, 0xc089, 0xe1ff, 0xc089, 0x21, 0 + .dw 0xe240, 0xc089, 0xe27f, 0xc089, 0x21, 0 + .dw 0xe2c0, 0xc089, 0xe2ff, 0xc089, 0x21, 0 + .dw 0xe340, 0xc089, 0xe37f, 0xc089, 0x21, 0 + .dw 0xe3c0, 0xc089, 0xe3ff, 0xc089, 0x21, 0 + .dw 0xe440, 0xc089, 0xe47f, 0xc089, 0x21, 0 + .dw 0xe4c0, 0xc089, 0xe4ff, 0xc089, 0x21, 0 + .dw 0xe540, 0xc089, 0xe57f, 0xc089, 0x21, 0 + .dw 0xe5c0, 0xc089, 0xe5ff, 0xc089, 0x21, 0 + .dw 0xe640, 0xc089, 0xe67f, 0xc089, 0x21, 0 + .dw 0xe6c0, 0xc089, 0xe6ff, 0xc089, 0x21, 0 + .dw 0xe740, 0xc089, 0xe77f, 0xc089, 0x21, 0 + .dw 0xe7c0, 0xc089, 0xe7ff, 0xc089, 0x21, 0 + .dw 0xe840, 0xc089, 0xe87f, 0xc089, 0x21, 0 + .dw 0xe8c0, 0xc089, 0xe8ff, 0xc089, 0x21, 0 + .dw 0xe940, 0xc089, 0xe97f, 0xc089, 0x21, 0 + .dw 0xe9c0, 0xc089, 0xe9ff, 0xc089, 0x21, 0 + .dw 0xea40, 0xc089, 0xea7f, 0xc089, 0x21, 0 + .dw 0xeac0, 0xc089, 0xeaff, 0xc089, 0x21, 0 + .dw 0xeb40, 0xc089, 0xeb7f, 0xc089, 0x21, 0 + .dw 0xebc0, 0xc089, 0xebff, 0xc089, 0x21, 0 + .dw 0xec40, 0xc089, 0xec7f, 0xc089, 0x21, 0 + .dw 0xecc0, 0xc089, 0xecff, 0xc089, 0x21, 0 + .dw 0xed40, 0xc089, 0xed7f, 0xc089, 0x21, 0 + .dw 0xedc0, 0xc089, 0xedff, 0xc089, 0x21, 0 + .dw 0xee40, 0xc089, 0xee7f, 0xc089, 0x21, 0 + .dw 0xeec0, 0xc089, 0xeeff, 0xc089, 0x21, 0 + .dw 0xef40, 0xc089, 0xef7f, 0xc089, 0x21, 0 + .dw 0xefc0, 0xc089, 0xefff, 0xc089, 0x21, 0 + .dw 0xf040, 0xc089, 0xf07f, 0xc089, 0x21, 0 + .dw 0xf0c0, 0xc089, 0xf0ff, 0xc089, 0x21, 0 + .dw 0xf140, 0xc089, 0xf17f, 0xc089, 0x21, 0 + .dw 0xf1c0, 0xc089, 0xf1ff, 0xc089, 0x21, 0 + .dw 0xf240, 0xc089, 0xf27f, 0xc089, 0x21, 0 + .dw 0xf2c0, 0xc089, 0xf2ff, 0xc089, 0x21, 0 + .dw 0xf340, 0xc089, 0xf37f, 0xc089, 0x21, 0 + .dw 0xf3c0, 0xc089, 0xf3ff, 0xc089, 0x21, 0 + .dw 0xf440, 0xc089, 0xf47f, 0xc089, 0x21, 0 + .dw 0xf4c0, 0xc089, 0xf4ff, 0xc089, 0x21, 0 + .dw 0xf540, 0xc089, 0xf57f, 0xc089, 0x21, 0 + .dw 0xf5c0, 0xc089, 0xf5ff, 0xc089, 0x21, 0 + .dw 0xf640, 0xc089, 0xf67f, 0xc089, 0x21, 0 + .dw 0xf6c0, 0xc089, 0xf6ff, 0xc089, 0x21, 0 + .dw 0xf740, 0xc089, 0xf77f, 0xc089, 0x21, 0 + .dw 0xf7c0, 0xc089, 0xf7ff, 0xc089, 0x21, 0 + .dw 0xf840, 0xc089, 0xf87f, 0xc089, 0x21, 0 + .dw 0xf8c0, 0xc089, 0xf8ff, 0xc089, 0x21, 0 + .dw 0xf940, 0xc089, 0xf97f, 0xc089, 0x21, 0 + .dw 0xf9c0, 0xc089, 0x1fff, 0xc08a, 0x21, 0 + .dw 0x2040, 0xc08a, 0x207f, 0xc08a, 0x21, 0 + .dw 0x20c0, 0xc08a, 0x20ff, 0xc08a, 0x21, 0 + .dw 0x2140, 0xc08a, 0x217f, 0xc08a, 0x21, 0 + .dw 0x21c0, 0xc08a, 0x21ff, 0xc08a, 0x21, 0 + .dw 0x2240, 0xc08a, 0x227f, 0xc08a, 0x21, 0 + .dw 0x22c0, 0xc08a, 0x22ff, 0xc08a, 0x21, 0 + .dw 0x2340, 0xc08a, 0x237f, 0xc08a, 0x21, 0 + .dw 0x23c0, 0xc08a, 0x23ff, 0xc08a, 0x21, 0 + .dw 0x2440, 0xc08a, 0x247f, 0xc08a, 0x21, 0 + .dw 0x24c0, 0xc08a, 0x24ff, 0xc08a, 0x21, 0 + .dw 0x2540, 0xc08a, 0x257f, 0xc08a, 0x21, 0 + .dw 0x25c0, 0xc08a, 0x25ff, 0xc08a, 0x21, 0 + .dw 0x2640, 0xc08a, 0x267f, 0xc08a, 0x21, 0 + .dw 0x26c0, 0xc08a, 0x26ff, 0xc08a, 0x21, 0 + .dw 0x2740, 0xc08a, 0x277f, 0xc08a, 0x21, 0 + .dw 0x27c0, 0xc08a, 0x27ff, 0xc08a, 0x21, 0 + .dw 0x2840, 0xc08a, 0x287f, 0xc08a, 0x21, 0 + .dw 0x28c0, 0xc08a, 0x28ff, 0xc08a, 0x21, 0 + .dw 0x2940, 0xc08a, 0x297f, 0xc08a, 0x21, 0 + .dw 0x29c0, 0xc08a, 0x29ff, 0xc08a, 0x21, 0 + .dw 0x2a40, 0xc08a, 0x2a7f, 0xc08a, 0x21, 0 + .dw 0x2ac0, 0xc08a, 0x2aff, 0xc08a, 0x21, 0 + .dw 0x2b40, 0xc08a, 0x2b7f, 0xc08a, 0x21, 0 + .dw 0x2bc0, 0xc08a, 0x2bff, 0xc08a, 0x21, 0 + .dw 0x2c40, 0xc08a, 0x2c7f, 0xc08a, 0x21, 0 + .dw 0x2cc0, 0xc08a, 0x2cff, 0xc08a, 0x21, 0 + .dw 0x2d40, 0xc08a, 0x2d7f, 0xc08a, 0x21, 0 + .dw 0x2dc0, 0xc08a, 0x2dff, 0xc08a, 0x21, 0 + .dw 0x2e40, 0xc08a, 0x2e7f, 0xc08a, 0x21, 0 + .dw 0x2ec0, 0xc08a, 0x2eff, 0xc08a, 0x21, 0 + .dw 0x2f40, 0xc08a, 0x2f7f, 0xc08a, 0x21, 0 + .dw 0x2fc0, 0xc08a, 0x2fff, 0xc08a, 0x21, 0 + .dw 0x3040, 0xc08a, 0x307f, 0xc08a, 0x21, 0 + .dw 0x30c0, 0xc08a, 0x30ff, 0xc08a, 0x21, 0 + .dw 0x3140, 0xc08a, 0x317f, 0xc08a, 0x21, 0 + .dw 0x31c0, 0xc08a, 0x31ff, 0xc08a, 0x21, 0 + .dw 0x3240, 0xc08a, 0x327f, 0xc08a, 0x21, 0 + .dw 0x32c0, 0xc08a, 0x32ff, 0xc08a, 0x21, 0 + .dw 0x3340, 0xc08a, 0x337f, 0xc08a, 0x21, 0 + .dw 0x33c0, 0xc08a, 0x33ff, 0xc08a, 0x21, 0 + .dw 0x3440, 0xc08a, 0x347f, 0xc08a, 0x21, 0 + .dw 0x34c0, 0xc08a, 0x34ff, 0xc08a, 0x21, 0 + .dw 0x3540, 0xc08a, 0x357f, 0xc08a, 0x21, 0 + .dw 0x35c0, 0xc08a, 0x35ff, 0xc08a, 0x21, 0 + .dw 0x3640, 0xc08a, 0x367f, 0xc08a, 0x21, 0 + .dw 0x36c0, 0xc08a, 0x36ff, 0xc08a, 0x21, 0 + .dw 0x3740, 0xc08a, 0x377f, 0xc08a, 0x21, 0 + .dw 0x37c0, 0xc08a, 0x37ff, 0xc08a, 0x21, 0 + .dw 0x3840, 0xc08a, 0x387f, 0xc08a, 0x21, 0 + .dw 0x38c0, 0xc08a, 0x38ff, 0xc08a, 0x21, 0 + .dw 0x3940, 0xc08a, 0x397f, 0xc08a, 0x21, 0 + .dw 0x39c0, 0xc08a, 0x5fff, 0xc08a, 0x21, 0 + .dw 0x6040, 0xc08a, 0x607f, 0xc08a, 0x21, 0 + .dw 0x60c0, 0xc08a, 0x60ff, 0xc08a, 0x21, 0 + .dw 0x6140, 0xc08a, 0x617f, 0xc08a, 0x21, 0 + .dw 0x61c0, 0xc08a, 0x61ff, 0xc08a, 0x21, 0 + .dw 0x6240, 0xc08a, 0x627f, 0xc08a, 0x21, 0 + .dw 0x62c0, 0xc08a, 0x62ff, 0xc08a, 0x21, 0 + .dw 0x6340, 0xc08a, 0x637f, 0xc08a, 0x21, 0 + .dw 0x63c0, 0xc08a, 0x63ff, 0xc08a, 0x21, 0 + .dw 0x6440, 0xc08a, 0x647f, 0xc08a, 0x21, 0 + .dw 0x64c0, 0xc08a, 0x64ff, 0xc08a, 0x21, 0 + .dw 0x6540, 0xc08a, 0x657f, 0xc08a, 0x21, 0 + .dw 0x65c0, 0xc08a, 0x65ff, 0xc08a, 0x21, 0 + .dw 0x6640, 0xc08a, 0x667f, 0xc08a, 0x21, 0 + .dw 0x66c0, 0xc08a, 0x66ff, 0xc08a, 0x21, 0 + .dw 0x6740, 0xc08a, 0x677f, 0xc08a, 0x21, 0 + .dw 0x67c0, 0xc08a, 0x67ff, 0xc08a, 0x21, 0 + .dw 0x6840, 0xc08a, 0x687f, 0xc08a, 0x21, 0 + .dw 0x68c0, 0xc08a, 0x68ff, 0xc08a, 0x21, 0 + .dw 0x6940, 0xc08a, 0x697f, 0xc08a, 0x21, 0 + .dw 0x69c0, 0xc08a, 0x69ff, 0xc08a, 0x21, 0 + .dw 0x6a40, 0xc08a, 0x6a7f, 0xc08a, 0x21, 0 + .dw 0x6ac0, 0xc08a, 0x6aff, 0xc08a, 0x21, 0 + .dw 0x6b40, 0xc08a, 0x6b7f, 0xc08a, 0x21, 0 + .dw 0x6bc0, 0xc08a, 0x6bff, 0xc08a, 0x21, 0 + .dw 0x6c40, 0xc08a, 0x6c7f, 0xc08a, 0x21, 0 + .dw 0x6cc0, 0xc08a, 0x6cff, 0xc08a, 0x21, 0 + .dw 0x6d40, 0xc08a, 0x6d7f, 0xc08a, 0x21, 0 + .dw 0x6dc0, 0xc08a, 0x6dff, 0xc08a, 0x21, 0 + .dw 0x6e40, 0xc08a, 0x6e7f, 0xc08a, 0x21, 0 + .dw 0x6ec0, 0xc08a, 0x6eff, 0xc08a, 0x21, 0 + .dw 0x6f40, 0xc08a, 0x6f7f, 0xc08a, 0x21, 0 + .dw 0x6fc0, 0xc08a, 0x6fff, 0xc08a, 0x21, 0 + .dw 0x7040, 0xc08a, 0x707f, 0xc08a, 0x21, 0 + .dw 0x70c0, 0xc08a, 0x70ff, 0xc08a, 0x21, 0 + .dw 0x7140, 0xc08a, 0x717f, 0xc08a, 0x21, 0 + .dw 0x71c0, 0xc08a, 0x71ff, 0xc08a, 0x21, 0 + .dw 0x7240, 0xc08a, 0x727f, 0xc08a, 0x21, 0 + .dw 0x72c0, 0xc08a, 0x72ff, 0xc08a, 0x21, 0 + .dw 0x7340, 0xc08a, 0x737f, 0xc08a, 0x21, 0 + .dw 0x73c0, 0xc08a, 0x73ff, 0xc08a, 0x21, 0 + .dw 0x7440, 0xc08a, 0x747f, 0xc08a, 0x21, 0 + .dw 0x74c0, 0xc08a, 0x74ff, 0xc08a, 0x21, 0 + .dw 0x7540, 0xc08a, 0x757f, 0xc08a, 0x21, 0 + .dw 0x75c0, 0xc08a, 0x75ff, 0xc08a, 0x21, 0 + .dw 0x7640, 0xc08a, 0x767f, 0xc08a, 0x21, 0 + .dw 0x76c0, 0xc08a, 0x76ff, 0xc08a, 0x21, 0 + .dw 0x7740, 0xc08a, 0x777f, 0xc08a, 0x21, 0 + .dw 0x77c0, 0xc08a, 0x77ff, 0xc08a, 0x21, 0 + .dw 0x7840, 0xc08a, 0x787f, 0xc08a, 0x21, 0 + .dw 0x78c0, 0xc08a, 0x78ff, 0xc08a, 0x21, 0 + .dw 0x7940, 0xc08a, 0x797f, 0xc08a, 0x21, 0 + .dw 0x79c0, 0xc08a, 0x9fff, 0xc08a, 0x21, 0 + .dw 0xa040, 0xc08a, 0xa07f, 0xc08a, 0x21, 0 + .dw 0xa0c0, 0xc08a, 0xa0ff, 0xc08a, 0x21, 0 + .dw 0xa140, 0xc08a, 0xa17f, 0xc08a, 0x21, 0 + .dw 0xa1c0, 0xc08a, 0xa1ff, 0xc08a, 0x21, 0 + .dw 0xa240, 0xc08a, 0xa27f, 0xc08a, 0x21, 0 + .dw 0xa2c0, 0xc08a, 0xa2ff, 0xc08a, 0x21, 0 + .dw 0xa340, 0xc08a, 0xa37f, 0xc08a, 0x21, 0 + .dw 0xa3c0, 0xc08a, 0xa3ff, 0xc08a, 0x21, 0 + .dw 0xa440, 0xc08a, 0xa47f, 0xc08a, 0x21, 0 + .dw 0xa4c0, 0xc08a, 0xa4ff, 0xc08a, 0x21, 0 + .dw 0xa540, 0xc08a, 0xa57f, 0xc08a, 0x21, 0 + .dw 0xa5c0, 0xc08a, 0xa5ff, 0xc08a, 0x21, 0 + .dw 0xa640, 0xc08a, 0xa67f, 0xc08a, 0x21, 0 + .dw 0xa6c0, 0xc08a, 0xa6ff, 0xc08a, 0x21, 0 + .dw 0xa740, 0xc08a, 0xa77f, 0xc08a, 0x21, 0 + .dw 0xa7c0, 0xc08a, 0xa7ff, 0xc08a, 0x21, 0 + .dw 0xa840, 0xc08a, 0xa87f, 0xc08a, 0x21, 0 + .dw 0xa8c0, 0xc08a, 0xa8ff, 0xc08a, 0x21, 0 + .dw 0xa940, 0xc08a, 0xa97f, 0xc08a, 0x21, 0 + .dw 0xa9c0, 0xc08a, 0xa9ff, 0xc08a, 0x21, 0 + .dw 0xaa40, 0xc08a, 0xaa7f, 0xc08a, 0x21, 0 + .dw 0xaac0, 0xc08a, 0xaaff, 0xc08a, 0x21, 0 + .dw 0xab40, 0xc08a, 0xab7f, 0xc08a, 0x21, 0 + .dw 0xabc0, 0xc08a, 0xabff, 0xc08a, 0x21, 0 + .dw 0xac40, 0xc08a, 0xac7f, 0xc08a, 0x21, 0 + .dw 0xacc0, 0xc08a, 0xacff, 0xc08a, 0x21, 0 + .dw 0xad40, 0xc08a, 0xad7f, 0xc08a, 0x21, 0 + .dw 0xadc0, 0xc08a, 0xadff, 0xc08a, 0x21, 0 + .dw 0xae40, 0xc08a, 0xae7f, 0xc08a, 0x21, 0 + .dw 0xaec0, 0xc08a, 0xaeff, 0xc08a, 0x21, 0 + .dw 0xaf40, 0xc08a, 0xaf7f, 0xc08a, 0x21, 0 + .dw 0xafc0, 0xc08a, 0xafff, 0xc08a, 0x21, 0 + .dw 0xb040, 0xc08a, 0xb07f, 0xc08a, 0x21, 0 + .dw 0xb0c0, 0xc08a, 0xb0ff, 0xc08a, 0x21, 0 + .dw 0xb140, 0xc08a, 0xb17f, 0xc08a, 0x21, 0 + .dw 0xb1c0, 0xc08a, 0xb1ff, 0xc08a, 0x21, 0 + .dw 0xb240, 0xc08a, 0xb27f, 0xc08a, 0x21, 0 + .dw 0xb2c0, 0xc08a, 0xb2ff, 0xc08a, 0x21, 0 + .dw 0xb340, 0xc08a, 0xb37f, 0xc08a, 0x21, 0 + .dw 0xb3c0, 0xc08a, 0xb3ff, 0xc08a, 0x21, 0 + .dw 0xb440, 0xc08a, 0xb47f, 0xc08a, 0x21, 0 + .dw 0xb4c0, 0xc08a, 0xb4ff, 0xc08a, 0x21, 0 + .dw 0xb540, 0xc08a, 0xb57f, 0xc08a, 0x21, 0 + .dw 0xb5c0, 0xc08a, 0xb5ff, 0xc08a, 0x21, 0 + .dw 0xb640, 0xc08a, 0xb67f, 0xc08a, 0x21, 0 + .dw 0xb6c0, 0xc08a, 0xb6ff, 0xc08a, 0x21, 0 + .dw 0xb740, 0xc08a, 0xb77f, 0xc08a, 0x21, 0 + .dw 0xb7c0, 0xc08a, 0xb7ff, 0xc08a, 0x21, 0 + .dw 0xb840, 0xc08a, 0xb87f, 0xc08a, 0x21, 0 + .dw 0xb8c0, 0xc08a, 0xb8ff, 0xc08a, 0x21, 0 + .dw 0xb940, 0xc08a, 0xb97f, 0xc08a, 0x21, 0 + .dw 0xb9c0, 0xc08a, 0xdfff, 0xc08a, 0x21, 0 + .dw 0xe040, 0xc08a, 0xe07f, 0xc08a, 0x21, 0 + .dw 0xe0c0, 0xc08a, 0xe0ff, 0xc08a, 0x21, 0 + .dw 0xe140, 0xc08a, 0xe17f, 0xc08a, 0x21, 0 + .dw 0xe1c0, 0xc08a, 0xe1ff, 0xc08a, 0x21, 0 + .dw 0xe240, 0xc08a, 0xe27f, 0xc08a, 0x21, 0 + .dw 0xe2c0, 0xc08a, 0xe2ff, 0xc08a, 0x21, 0 + .dw 0xe340, 0xc08a, 0xe37f, 0xc08a, 0x21, 0 + .dw 0xe3c0, 0xc08a, 0xe3ff, 0xc08a, 0x21, 0 + .dw 0xe440, 0xc08a, 0xe47f, 0xc08a, 0x21, 0 + .dw 0xe4c0, 0xc08a, 0xe4ff, 0xc08a, 0x21, 0 + .dw 0xe540, 0xc08a, 0xe57f, 0xc08a, 0x21, 0 + .dw 0xe5c0, 0xc08a, 0xe5ff, 0xc08a, 0x21, 0 + .dw 0xe640, 0xc08a, 0xe67f, 0xc08a, 0x21, 0 + .dw 0xe6c0, 0xc08a, 0xe6ff, 0xc08a, 0x21, 0 + .dw 0xe740, 0xc08a, 0xe77f, 0xc08a, 0x21, 0 + .dw 0xe7c0, 0xc08a, 0xe7ff, 0xc08a, 0x21, 0 + .dw 0xe840, 0xc08a, 0xe87f, 0xc08a, 0x21, 0 + .dw 0xe8c0, 0xc08a, 0xe8ff, 0xc08a, 0x21, 0 + .dw 0xe940, 0xc08a, 0xe97f, 0xc08a, 0x21, 0 + .dw 0xe9c0, 0xc08a, 0xe9ff, 0xc08a, 0x21, 0 + .dw 0xea40, 0xc08a, 0xea7f, 0xc08a, 0x21, 0 + .dw 0xeac0, 0xc08a, 0xeaff, 0xc08a, 0x21, 0 + .dw 0xeb40, 0xc08a, 0xeb7f, 0xc08a, 0x21, 0 + .dw 0xebc0, 0xc08a, 0xebff, 0xc08a, 0x21, 0 + .dw 0xec40, 0xc08a, 0xec7f, 0xc08a, 0x21, 0 + .dw 0xecc0, 0xc08a, 0xecff, 0xc08a, 0x21, 0 + .dw 0xed40, 0xc08a, 0xed7f, 0xc08a, 0x21, 0 + .dw 0xedc0, 0xc08a, 0xedff, 0xc08a, 0x21, 0 + .dw 0xee40, 0xc08a, 0xee7f, 0xc08a, 0x21, 0 + .dw 0xeec0, 0xc08a, 0xeeff, 0xc08a, 0x21, 0 + .dw 0xef40, 0xc08a, 0xef7f, 0xc08a, 0x21, 0 + .dw 0xefc0, 0xc08a, 0xefff, 0xc08a, 0x21, 0 + .dw 0xf040, 0xc08a, 0xf07f, 0xc08a, 0x21, 0 + .dw 0xf0c0, 0xc08a, 0xf0ff, 0xc08a, 0x21, 0 + .dw 0xf140, 0xc08a, 0xf17f, 0xc08a, 0x21, 0 + .dw 0xf1c0, 0xc08a, 0xf1ff, 0xc08a, 0x21, 0 + .dw 0xf240, 0xc08a, 0xf27f, 0xc08a, 0x21, 0 + .dw 0xf2c0, 0xc08a, 0xf2ff, 0xc08a, 0x21, 0 + .dw 0xf340, 0xc08a, 0xf37f, 0xc08a, 0x21, 0 + .dw 0xf3c0, 0xc08a, 0xf3ff, 0xc08a, 0x21, 0 + .dw 0xf440, 0xc08a, 0xf47f, 0xc08a, 0x21, 0 + .dw 0xf4c0, 0xc08a, 0xf4ff, 0xc08a, 0x21, 0 + .dw 0xf540, 0xc08a, 0xf57f, 0xc08a, 0x21, 0 + .dw 0xf5c0, 0xc08a, 0xf5ff, 0xc08a, 0x21, 0 + .dw 0xf640, 0xc08a, 0xf67f, 0xc08a, 0x21, 0 + .dw 0xf6c0, 0xc08a, 0xf6ff, 0xc08a, 0x21, 0 + .dw 0xf740, 0xc08a, 0xf77f, 0xc08a, 0x21, 0 + .dw 0xf7c0, 0xc08a, 0xf7ff, 0xc08a, 0x21, 0 + .dw 0xf840, 0xc08a, 0xf87f, 0xc08a, 0x21, 0 + .dw 0xf8c0, 0xc08a, 0xf8ff, 0xc08a, 0x21, 0 + .dw 0xf940, 0xc08a, 0xf97f, 0xc08a, 0x21, 0 + .dw 0xf9c0, 0xc08a, 0x1fff, 0xc08b, 0x21, 0 + .dw 0x2040, 0xc08b, 0x207f, 0xc08b, 0x21, 0 + .dw 0x20c0, 0xc08b, 0x20ff, 0xc08b, 0x21, 0 + .dw 0x2140, 0xc08b, 0x217f, 0xc08b, 0x21, 0 + .dw 0x21c0, 0xc08b, 0x21ff, 0xc08b, 0x21, 0 + .dw 0x2240, 0xc08b, 0x227f, 0xc08b, 0x21, 0 + .dw 0x22c0, 0xc08b, 0x22ff, 0xc08b, 0x21, 0 + .dw 0x2340, 0xc08b, 0x237f, 0xc08b, 0x21, 0 + .dw 0x23c0, 0xc08b, 0x23ff, 0xc08b, 0x21, 0 + .dw 0x2440, 0xc08b, 0x247f, 0xc08b, 0x21, 0 + .dw 0x24c0, 0xc08b, 0x24ff, 0xc08b, 0x21, 0 + .dw 0x2540, 0xc08b, 0x257f, 0xc08b, 0x21, 0 + .dw 0x25c0, 0xc08b, 0x25ff, 0xc08b, 0x21, 0 + .dw 0x2640, 0xc08b, 0x267f, 0xc08b, 0x21, 0 + .dw 0x26c0, 0xc08b, 0x26ff, 0xc08b, 0x21, 0 + .dw 0x2740, 0xc08b, 0x277f, 0xc08b, 0x21, 0 + .dw 0x27c0, 0xc08b, 0x27ff, 0xc08b, 0x21, 0 + .dw 0x2840, 0xc08b, 0x287f, 0xc08b, 0x21, 0 + .dw 0x28c0, 0xc08b, 0x28ff, 0xc08b, 0x21, 0 + .dw 0x2940, 0xc08b, 0x297f, 0xc08b, 0x21, 0 + .dw 0x29c0, 0xc08b, 0x29ff, 0xc08b, 0x21, 0 + .dw 0x2a40, 0xc08b, 0x2a7f, 0xc08b, 0x21, 0 + .dw 0x2ac0, 0xc08b, 0x2aff, 0xc08b, 0x21, 0 + .dw 0x2b40, 0xc08b, 0x2b7f, 0xc08b, 0x21, 0 + .dw 0x2bc0, 0xc08b, 0x2bff, 0xc08b, 0x21, 0 + .dw 0x2c40, 0xc08b, 0x2c7f, 0xc08b, 0x21, 0 + .dw 0x2cc0, 0xc08b, 0x2cff, 0xc08b, 0x21, 0 + .dw 0x2d40, 0xc08b, 0x2d7f, 0xc08b, 0x21, 0 + .dw 0x2dc0, 0xc08b, 0x2dff, 0xc08b, 0x21, 0 + .dw 0x2e40, 0xc08b, 0x2e7f, 0xc08b, 0x21, 0 + .dw 0x2ec0, 0xc08b, 0x2eff, 0xc08b, 0x21, 0 + .dw 0x2f40, 0xc08b, 0x2f7f, 0xc08b, 0x21, 0 + .dw 0x2fc0, 0xc08b, 0x2fff, 0xc08b, 0x21, 0 + .dw 0x3040, 0xc08b, 0x307f, 0xc08b, 0x21, 0 + .dw 0x30c0, 0xc08b, 0x30ff, 0xc08b, 0x21, 0 + .dw 0x3140, 0xc08b, 0x317f, 0xc08b, 0x21, 0 + .dw 0x31c0, 0xc08b, 0x31ff, 0xc08b, 0x21, 0 + .dw 0x3240, 0xc08b, 0x327f, 0xc08b, 0x21, 0 + .dw 0x32c0, 0xc08b, 0x32ff, 0xc08b, 0x21, 0 + .dw 0x3340, 0xc08b, 0x337f, 0xc08b, 0x21, 0 + .dw 0x33c0, 0xc08b, 0x33ff, 0xc08b, 0x21, 0 + .dw 0x3440, 0xc08b, 0x347f, 0xc08b, 0x21, 0 + .dw 0x34c0, 0xc08b, 0x34ff, 0xc08b, 0x21, 0 + .dw 0x3540, 0xc08b, 0x357f, 0xc08b, 0x21, 0 + .dw 0x35c0, 0xc08b, 0x35ff, 0xc08b, 0x21, 0 + .dw 0x3640, 0xc08b, 0x367f, 0xc08b, 0x21, 0 + .dw 0x36c0, 0xc08b, 0x36ff, 0xc08b, 0x21, 0 + .dw 0x3740, 0xc08b, 0x377f, 0xc08b, 0x21, 0 + .dw 0x37c0, 0xc08b, 0x37ff, 0xc08b, 0x21, 0 + .dw 0x3840, 0xc08b, 0x387f, 0xc08b, 0x21, 0 + .dw 0x38c0, 0xc08b, 0x38ff, 0xc08b, 0x21, 0 + .dw 0x3940, 0xc08b, 0x397f, 0xc08b, 0x21, 0 + .dw 0x39c0, 0xc08b, 0xffff, 0xc08b, 0x21, 0 + .dw 0x0040, 0xc08c, 0x007f, 0xc08c, 0x21, 0 + .dw 0x00c0, 0xc08c, 0x00ff, 0xc08c, 0x21, 0 + .dw 0x0140, 0xc08c, 0x017f, 0xc08c, 0x21, 0 + .dw 0x01c0, 0xc08c, 0x01ff, 0xc08c, 0x21, 0 + .dw 0x0240, 0xc08c, 0x027f, 0xc08c, 0x21, 0 + .dw 0x02c0, 0xc08c, 0x02ff, 0xc08c, 0x21, 0 + .dw 0x0340, 0xc08c, 0x037f, 0xc08c, 0x21, 0 + .dw 0x03c0, 0xc08c, 0x03ff, 0xc08c, 0x21, 0 + .dw 0x0440, 0xc08c, 0x047f, 0xc08c, 0x21, 0 + .dw 0x04c0, 0xc08c, 0x04ff, 0xc08c, 0x21, 0 + .dw 0x0540, 0xc08c, 0x057f, 0xc08c, 0x21, 0 + .dw 0x05c0, 0xc08c, 0x05ff, 0xc08c, 0x21, 0 + .dw 0x0640, 0xc08c, 0x067f, 0xc08c, 0x21, 0 + .dw 0x06c0, 0xc08c, 0x06ff, 0xc08c, 0x21, 0 + .dw 0x0740, 0xc08c, 0x077f, 0xc08c, 0x21, 0 + .dw 0x07c0, 0xc08c, 0x07ff, 0xc08c, 0x21, 0 + .dw 0x0840, 0xc08c, 0x087f, 0xc08c, 0x21, 0 + .dw 0x08c0, 0xc08c, 0x08ff, 0xc08c, 0x21, 0 + .dw 0x0940, 0xc08c, 0x097f, 0xc08c, 0x21, 0 + .dw 0x09c0, 0xc08c, 0x09ff, 0xc08c, 0x21, 0 + .dw 0x0a40, 0xc08c, 0x0a7f, 0xc08c, 0x21, 0 + .dw 0x0ac0, 0xc08c, 0x0aff, 0xc08c, 0x21, 0 + .dw 0x0b40, 0xc08c, 0x0b7f, 0xc08c, 0x21, 0 + .dw 0x0bc0, 0xc08c, 0x0bff, 0xc08c, 0x21, 0 + .dw 0x0c40, 0xc08c, 0x0c7f, 0xc08c, 0x21, 0 + .dw 0x0cc0, 0xc08c, 0x0cff, 0xc08c, 0x21, 0 + .dw 0x0d40, 0xc08c, 0x0d7f, 0xc08c, 0x21, 0 + .dw 0x0dc0, 0xc08c, 0x0dff, 0xc08c, 0x21, 0 + .dw 0x0e40, 0xc08c, 0x0e7f, 0xc08c, 0x21, 0 + .dw 0x0ec0, 0xc08c, 0x0eff, 0xc08c, 0x21, 0 + .dw 0x0f40, 0xc08c, 0x0f7f, 0xc08c, 0x21, 0 + .dw 0x0fc0, 0xc08c, 0x0fff, 0xc08c, 0x21, 0 + .dw 0x1040, 0xc08c, 0x107f, 0xc08c, 0x21, 0 + .dw 0x10c0, 0xc08c, 0x10ff, 0xc08c, 0x21, 0 + .dw 0x1140, 0xc08c, 0x117f, 0xc08c, 0x21, 0 + .dw 0x11c0, 0xc08c, 0x11ff, 0xc08c, 0x21, 0 + .dw 0x1240, 0xc08c, 0x127f, 0xc08c, 0x21, 0 + .dw 0x12c0, 0xc08c, 0x12ff, 0xc08c, 0x21, 0 + .dw 0x1340, 0xc08c, 0x137f, 0xc08c, 0x21, 0 + .dw 0x13c0, 0xc08c, 0x13ff, 0xc08c, 0x21, 0 + .dw 0x1440, 0xc08c, 0x147f, 0xc08c, 0x21, 0 + .dw 0x14c0, 0xc08c, 0x14ff, 0xc08c, 0x21, 0 + .dw 0x1540, 0xc08c, 0x157f, 0xc08c, 0x21, 0 + .dw 0x15c0, 0xc08c, 0x15ff, 0xc08c, 0x21, 0 + .dw 0x1640, 0xc08c, 0x167f, 0xc08c, 0x21, 0 + .dw 0x16c0, 0xc08c, 0x16ff, 0xc08c, 0x21, 0 + .dw 0x1740, 0xc08c, 0x177f, 0xc08c, 0x21, 0 + .dw 0x17c0, 0xc08c, 0x17ff, 0xc08c, 0x21, 0 + .dw 0x1840, 0xc08c, 0x187f, 0xc08c, 0x21, 0 + .dw 0x18c0, 0xc08c, 0x18ff, 0xc08c, 0x21, 0 + .dw 0x1940, 0xc08c, 0x197f, 0xc08c, 0x21, 0 + .dw 0x19c0, 0xc08c, 0x1fff, 0xc08c, 0x21, 0 + .dw 0x2040, 0xc08c, 0x207f, 0xc08c, 0x21, 0 + .dw 0x20c0, 0xc08c, 0x20ff, 0xc08c, 0x21, 0 + .dw 0x2140, 0xc08c, 0x217f, 0xc08c, 0x21, 0 + .dw 0x21c0, 0xc08c, 0x21ff, 0xc08c, 0x21, 0 + .dw 0x2240, 0xc08c, 0x227f, 0xc08c, 0x21, 0 + .dw 0x22c0, 0xc08c, 0x22ff, 0xc08c, 0x21, 0 + .dw 0x2340, 0xc08c, 0x237f, 0xc08c, 0x21, 0 + .dw 0x23c0, 0xc08c, 0x23ff, 0xc08c, 0x21, 0 + .dw 0x2440, 0xc08c, 0x247f, 0xc08c, 0x21, 0 + .dw 0x24c0, 0xc08c, 0x24ff, 0xc08c, 0x21, 0 + .dw 0x2540, 0xc08c, 0x257f, 0xc08c, 0x21, 0 + .dw 0x25c0, 0xc08c, 0x25ff, 0xc08c, 0x21, 0 + .dw 0x2640, 0xc08c, 0x267f, 0xc08c, 0x21, 0 + .dw 0x26c0, 0xc08c, 0x26ff, 0xc08c, 0x21, 0 + .dw 0x2740, 0xc08c, 0x277f, 0xc08c, 0x21, 0 + .dw 0x27c0, 0xc08c, 0x27ff, 0xc08c, 0x21, 0 + .dw 0x2840, 0xc08c, 0x287f, 0xc08c, 0x21, 0 + .dw 0x28c0, 0xc08c, 0x28ff, 0xc08c, 0x21, 0 + .dw 0x2940, 0xc08c, 0x297f, 0xc08c, 0x21, 0 + .dw 0x29c0, 0xc08c, 0x29ff, 0xc08c, 0x21, 0 + .dw 0x2a40, 0xc08c, 0x2a7f, 0xc08c, 0x21, 0 + .dw 0x2ac0, 0xc08c, 0x2aff, 0xc08c, 0x21, 0 + .dw 0x2b40, 0xc08c, 0x2b7f, 0xc08c, 0x21, 0 + .dw 0x2bc0, 0xc08c, 0x2bff, 0xc08c, 0x21, 0 + .dw 0x2c40, 0xc08c, 0x2c7f, 0xc08c, 0x21, 0 + .dw 0x2cc0, 0xc08c, 0x2cff, 0xc08c, 0x21, 0 + .dw 0x2d40, 0xc08c, 0x2d7f, 0xc08c, 0x21, 0 + .dw 0x2dc0, 0xc08c, 0x2dff, 0xc08c, 0x21, 0 + .dw 0x2e40, 0xc08c, 0x2e7f, 0xc08c, 0x21, 0 + .dw 0x2ec0, 0xc08c, 0x2eff, 0xc08c, 0x21, 0 + .dw 0x2f40, 0xc08c, 0x2f7f, 0xc08c, 0x21, 0 + .dw 0x2fc0, 0xc08c, 0x2fff, 0xc08c, 0x21, 0 + .dw 0x3040, 0xc08c, 0x307f, 0xc08c, 0x21, 0 + .dw 0x30c0, 0xc08c, 0x30ff, 0xc08c, 0x21, 0 + .dw 0x3140, 0xc08c, 0x317f, 0xc08c, 0x21, 0 + .dw 0x31c0, 0xc08c, 0x31ff, 0xc08c, 0x21, 0 + .dw 0x3240, 0xc08c, 0x327f, 0xc08c, 0x21, 0 + .dw 0x32c0, 0xc08c, 0x32ff, 0xc08c, 0x21, 0 + .dw 0x3340, 0xc08c, 0x337f, 0xc08c, 0x21, 0 + .dw 0x33c0, 0xc08c, 0x33ff, 0xc08c, 0x21, 0 + .dw 0x3440, 0xc08c, 0x347f, 0xc08c, 0x21, 0 + .dw 0x34c0, 0xc08c, 0x34ff, 0xc08c, 0x21, 0 + .dw 0x3540, 0xc08c, 0x357f, 0xc08c, 0x21, 0 + .dw 0x35c0, 0xc08c, 0x35ff, 0xc08c, 0x21, 0 + .dw 0x3640, 0xc08c, 0x367f, 0xc08c, 0x21, 0 + .dw 0x36c0, 0xc08c, 0x36ff, 0xc08c, 0x21, 0 + .dw 0x3740, 0xc08c, 0x377f, 0xc08c, 0x21, 0 + .dw 0x37c0, 0xc08c, 0x37ff, 0xc08c, 0x21, 0 + .dw 0x3840, 0xc08c, 0x387f, 0xc08c, 0x21, 0 + .dw 0x38c0, 0xc08c, 0x38ff, 0xc08c, 0x21, 0 + .dw 0x3940, 0xc08c, 0x397f, 0xc08c, 0x21, 0 + .dw 0x39c0, 0xc08c, 0x3fff, 0xc08c, 0x21, 0 + .dw 0x4040, 0xc08c, 0x407f, 0xc08c, 0x21, 0 + .dw 0x40c0, 0xc08c, 0x40ff, 0xc08c, 0x21, 0 + .dw 0x4140, 0xc08c, 0x417f, 0xc08c, 0x21, 0 + .dw 0x41c0, 0xc08c, 0x41ff, 0xc08c, 0x21, 0 + .dw 0x4240, 0xc08c, 0x427f, 0xc08c, 0x21, 0 + .dw 0x42c0, 0xc08c, 0x42ff, 0xc08c, 0x21, 0 + .dw 0x4340, 0xc08c, 0x437f, 0xc08c, 0x21, 0 + .dw 0x43c0, 0xc08c, 0x43ff, 0xc08c, 0x21, 0 + .dw 0x4440, 0xc08c, 0x447f, 0xc08c, 0x21, 0 + .dw 0x44c0, 0xc08c, 0x44ff, 0xc08c, 0x21, 0 + .dw 0x4540, 0xc08c, 0x457f, 0xc08c, 0x21, 0 + .dw 0x45c0, 0xc08c, 0x45ff, 0xc08c, 0x21, 0 + .dw 0x4640, 0xc08c, 0x467f, 0xc08c, 0x21, 0 + .dw 0x46c0, 0xc08c, 0x46ff, 0xc08c, 0x21, 0 + .dw 0x4740, 0xc08c, 0x477f, 0xc08c, 0x21, 0 + .dw 0x47c0, 0xc08c, 0x47ff, 0xc08c, 0x21, 0 + .dw 0x4840, 0xc08c, 0x487f, 0xc08c, 0x21, 0 + .dw 0x48c0, 0xc08c, 0x48ff, 0xc08c, 0x21, 0 + .dw 0x4940, 0xc08c, 0x497f, 0xc08c, 0x21, 0 + .dw 0x49c0, 0xc08c, 0x49ff, 0xc08c, 0x21, 0 + .dw 0x4a40, 0xc08c, 0x4a7f, 0xc08c, 0x21, 0 + .dw 0x4ac0, 0xc08c, 0x4aff, 0xc08c, 0x21, 0 + .dw 0x4b40, 0xc08c, 0x4b7f, 0xc08c, 0x21, 0 + .dw 0x4bc0, 0xc08c, 0x4bff, 0xc08c, 0x21, 0 + .dw 0x4c40, 0xc08c, 0x4c7f, 0xc08c, 0x21, 0 + .dw 0x4cc0, 0xc08c, 0x4cff, 0xc08c, 0x21, 0 + .dw 0x4d40, 0xc08c, 0x4d7f, 0xc08c, 0x21, 0 + .dw 0x4dc0, 0xc08c, 0x4dff, 0xc08c, 0x21, 0 + .dw 0x4e40, 0xc08c, 0x4e7f, 0xc08c, 0x21, 0 + .dw 0x4ec0, 0xc08c, 0x4eff, 0xc08c, 0x21, 0 + .dw 0x4f40, 0xc08c, 0x4f7f, 0xc08c, 0x21, 0 + .dw 0x4fc0, 0xc08c, 0x4fff, 0xc08c, 0x21, 0 + .dw 0x5040, 0xc08c, 0x507f, 0xc08c, 0x21, 0 + .dw 0x50c0, 0xc08c, 0x50ff, 0xc08c, 0x21, 0 + .dw 0x5140, 0xc08c, 0x517f, 0xc08c, 0x21, 0 + .dw 0x51c0, 0xc08c, 0x51ff, 0xc08c, 0x21, 0 + .dw 0x5240, 0xc08c, 0x527f, 0xc08c, 0x21, 0 + .dw 0x52c0, 0xc08c, 0x52ff, 0xc08c, 0x21, 0 + .dw 0x5340, 0xc08c, 0x537f, 0xc08c, 0x21, 0 + .dw 0x53c0, 0xc08c, 0x53ff, 0xc08c, 0x21, 0 + .dw 0x5440, 0xc08c, 0x547f, 0xc08c, 0x21, 0 + .dw 0x54c0, 0xc08c, 0x54ff, 0xc08c, 0x21, 0 + .dw 0x5540, 0xc08c, 0x557f, 0xc08c, 0x21, 0 + .dw 0x55c0, 0xc08c, 0x55ff, 0xc08c, 0x21, 0 + .dw 0x5640, 0xc08c, 0x567f, 0xc08c, 0x21, 0 + .dw 0x56c0, 0xc08c, 0x56ff, 0xc08c, 0x21, 0 + .dw 0x5740, 0xc08c, 0x577f, 0xc08c, 0x21, 0 + .dw 0x57c0, 0xc08c, 0x57ff, 0xc08c, 0x21, 0 + .dw 0x5840, 0xc08c, 0x587f, 0xc08c, 0x21, 0 + .dw 0x58c0, 0xc08c, 0x58ff, 0xc08c, 0x21, 0 + .dw 0x5940, 0xc08c, 0x597f, 0xc08c, 0x21, 0 + .dw 0x59c0, 0xc08c, 0x5fff, 0xc08c, 0x21, 0 + .dw 0x6040, 0xc08c, 0x607f, 0xc08c, 0x21, 0 + .dw 0x60c0, 0xc08c, 0x60ff, 0xc08c, 0x21, 0 + .dw 0x6140, 0xc08c, 0x617f, 0xc08c, 0x21, 0 + .dw 0x61c0, 0xc08c, 0x61ff, 0xc08c, 0x21, 0 + .dw 0x6240, 0xc08c, 0x627f, 0xc08c, 0x21, 0 + .dw 0x62c0, 0xc08c, 0x62ff, 0xc08c, 0x21, 0 + .dw 0x6340, 0xc08c, 0x637f, 0xc08c, 0x21, 0 + .dw 0x63c0, 0xc08c, 0x63ff, 0xc08c, 0x21, 0 + .dw 0x6440, 0xc08c, 0x647f, 0xc08c, 0x21, 0 + .dw 0x64c0, 0xc08c, 0x64ff, 0xc08c, 0x21, 0 + .dw 0x6540, 0xc08c, 0x657f, 0xc08c, 0x21, 0 + .dw 0x65c0, 0xc08c, 0x65ff, 0xc08c, 0x21, 0 + .dw 0x6640, 0xc08c, 0x667f, 0xc08c, 0x21, 0 + .dw 0x66c0, 0xc08c, 0x66ff, 0xc08c, 0x21, 0 + .dw 0x6740, 0xc08c, 0x677f, 0xc08c, 0x21, 0 + .dw 0x67c0, 0xc08c, 0x67ff, 0xc08c, 0x21, 0 + .dw 0x6840, 0xc08c, 0x687f, 0xc08c, 0x21, 0 + .dw 0x68c0, 0xc08c, 0x68ff, 0xc08c, 0x21, 0 + .dw 0x6940, 0xc08c, 0x697f, 0xc08c, 0x21, 0 + .dw 0x69c0, 0xc08c, 0x69ff, 0xc08c, 0x21, 0 + .dw 0x6a40, 0xc08c, 0x6a7f, 0xc08c, 0x21, 0 + .dw 0x6ac0, 0xc08c, 0x6aff, 0xc08c, 0x21, 0 + .dw 0x6b40, 0xc08c, 0x6b7f, 0xc08c, 0x21, 0 + .dw 0x6bc0, 0xc08c, 0x6bff, 0xc08c, 0x21, 0 + .dw 0x6c40, 0xc08c, 0x6c7f, 0xc08c, 0x21, 0 + .dw 0x6cc0, 0xc08c, 0x6cff, 0xc08c, 0x21, 0 + .dw 0x6d40, 0xc08c, 0x6d7f, 0xc08c, 0x21, 0 + .dw 0x6dc0, 0xc08c, 0x6dff, 0xc08c, 0x21, 0 + .dw 0x6e40, 0xc08c, 0x6e7f, 0xc08c, 0x21, 0 + .dw 0x6ec0, 0xc08c, 0x6eff, 0xc08c, 0x21, 0 + .dw 0x6f40, 0xc08c, 0x6f7f, 0xc08c, 0x21, 0 + .dw 0x6fc0, 0xc08c, 0x6fff, 0xc08c, 0x21, 0 + .dw 0x7040, 0xc08c, 0x707f, 0xc08c, 0x21, 0 + .dw 0x70c0, 0xc08c, 0x70ff, 0xc08c, 0x21, 0 + .dw 0x7140, 0xc08c, 0x717f, 0xc08c, 0x21, 0 + .dw 0x71c0, 0xc08c, 0x71ff, 0xc08c, 0x21, 0 + .dw 0x7240, 0xc08c, 0x727f, 0xc08c, 0x21, 0 + .dw 0x72c0, 0xc08c, 0x72ff, 0xc08c, 0x21, 0 + .dw 0x7340, 0xc08c, 0x737f, 0xc08c, 0x21, 0 + .dw 0x73c0, 0xc08c, 0x73ff, 0xc08c, 0x21, 0 + .dw 0x7440, 0xc08c, 0x747f, 0xc08c, 0x21, 0 + .dw 0x74c0, 0xc08c, 0x74ff, 0xc08c, 0x21, 0 + .dw 0x7540, 0xc08c, 0x757f, 0xc08c, 0x21, 0 + .dw 0x75c0, 0xc08c, 0x75ff, 0xc08c, 0x21, 0 + .dw 0x7640, 0xc08c, 0x767f, 0xc08c, 0x21, 0 + .dw 0x76c0, 0xc08c, 0x76ff, 0xc08c, 0x21, 0 + .dw 0x7740, 0xc08c, 0x777f, 0xc08c, 0x21, 0 + .dw 0x77c0, 0xc08c, 0x77ff, 0xc08c, 0x21, 0 + .dw 0x7840, 0xc08c, 0x787f, 0xc08c, 0x21, 0 + .dw 0x78c0, 0xc08c, 0x78ff, 0xc08c, 0x21, 0 + .dw 0x7940, 0xc08c, 0x797f, 0xc08c, 0x21, 0 + .dw 0x79c0, 0xc08c, 0x7fff, 0xc08c, 0x21, 0 + .dw 0x8040, 0xc08c, 0x807f, 0xc08c, 0x21, 0 + .dw 0x80c0, 0xc08c, 0x80ff, 0xc08c, 0x21, 0 + .dw 0x8140, 0xc08c, 0x817f, 0xc08c, 0x21, 0 + .dw 0x81c0, 0xc08c, 0x81ff, 0xc08c, 0x21, 0 + .dw 0x8240, 0xc08c, 0x827f, 0xc08c, 0x21, 0 + .dw 0x82c0, 0xc08c, 0x82ff, 0xc08c, 0x21, 0 + .dw 0x8340, 0xc08c, 0x837f, 0xc08c, 0x21, 0 + .dw 0x83c0, 0xc08c, 0x83ff, 0xc08c, 0x21, 0 + .dw 0x8440, 0xc08c, 0x847f, 0xc08c, 0x21, 0 + .dw 0x84c0, 0xc08c, 0x84ff, 0xc08c, 0x21, 0 + .dw 0x8540, 0xc08c, 0x857f, 0xc08c, 0x21, 0 + .dw 0x85c0, 0xc08c, 0x85ff, 0xc08c, 0x21, 0 + .dw 0x8640, 0xc08c, 0x867f, 0xc08c, 0x21, 0 + .dw 0x86c0, 0xc08c, 0x86ff, 0xc08c, 0x21, 0 + .dw 0x8740, 0xc08c, 0x877f, 0xc08c, 0x21, 0 + .dw 0x87c0, 0xc08c, 0x87ff, 0xc08c, 0x21, 0 + .dw 0x8840, 0xc08c, 0x887f, 0xc08c, 0x21, 0 + .dw 0x88c0, 0xc08c, 0x88ff, 0xc08c, 0x21, 0 + .dw 0x8940, 0xc08c, 0x897f, 0xc08c, 0x21, 0 + .dw 0x89c0, 0xc08c, 0x89ff, 0xc08c, 0x21, 0 + .dw 0x8a40, 0xc08c, 0x8a7f, 0xc08c, 0x21, 0 + .dw 0x8ac0, 0xc08c, 0x8aff, 0xc08c, 0x21, 0 + .dw 0x8b40, 0xc08c, 0x8b7f, 0xc08c, 0x21, 0 + .dw 0x8bc0, 0xc08c, 0x8bff, 0xc08c, 0x21, 0 + .dw 0x8c40, 0xc08c, 0x8c7f, 0xc08c, 0x21, 0 + .dw 0x8cc0, 0xc08c, 0x8cff, 0xc08c, 0x21, 0 + .dw 0x8d40, 0xc08c, 0x8d7f, 0xc08c, 0x21, 0 + .dw 0x8dc0, 0xc08c, 0x8dff, 0xc08c, 0x21, 0 + .dw 0x8e40, 0xc08c, 0x8e7f, 0xc08c, 0x21, 0 + .dw 0x8ec0, 0xc08c, 0x8eff, 0xc08c, 0x21, 0 + .dw 0x8f40, 0xc08c, 0x8f7f, 0xc08c, 0x21, 0 + .dw 0x8fc0, 0xc08c, 0x8fff, 0xc08c, 0x21, 0 + .dw 0x9040, 0xc08c, 0x907f, 0xc08c, 0x21, 0 + .dw 0x90c0, 0xc08c, 0x90ff, 0xc08c, 0x21, 0 + .dw 0x9140, 0xc08c, 0x917f, 0xc08c, 0x21, 0 + .dw 0x91c0, 0xc08c, 0x91ff, 0xc08c, 0x21, 0 + .dw 0x9240, 0xc08c, 0x927f, 0xc08c, 0x21, 0 + .dw 0x92c0, 0xc08c, 0x92ff, 0xc08c, 0x21, 0 + .dw 0x9340, 0xc08c, 0x937f, 0xc08c, 0x21, 0 + .dw 0x93c0, 0xc08c, 0x93ff, 0xc08c, 0x21, 0 + .dw 0x9440, 0xc08c, 0x947f, 0xc08c, 0x21, 0 + .dw 0x94c0, 0xc08c, 0x94ff, 0xc08c, 0x21, 0 + .dw 0x9540, 0xc08c, 0x957f, 0xc08c, 0x21, 0 + .dw 0x95c0, 0xc08c, 0x95ff, 0xc08c, 0x21, 0 + .dw 0x9640, 0xc08c, 0x967f, 0xc08c, 0x21, 0 + .dw 0x96c0, 0xc08c, 0x96ff, 0xc08c, 0x21, 0 + .dw 0x9740, 0xc08c, 0x977f, 0xc08c, 0x21, 0 + .dw 0x97c0, 0xc08c, 0x97ff, 0xc08c, 0x21, 0 + .dw 0x9840, 0xc08c, 0x987f, 0xc08c, 0x21, 0 + .dw 0x98c0, 0xc08c, 0x98ff, 0xc08c, 0x21, 0 + .dw 0x9940, 0xc08c, 0x997f, 0xc08c, 0x21, 0 + .dw 0x99c0, 0xc08c, 0x9fff, 0xc08c, 0x21, 0 + .dw 0xa040, 0xc08c, 0xa07f, 0xc08c, 0x21, 0 + .dw 0xa0c0, 0xc08c, 0xa0ff, 0xc08c, 0x21, 0 + .dw 0xa140, 0xc08c, 0xa17f, 0xc08c, 0x21, 0 + .dw 0xa1c0, 0xc08c, 0xa1ff, 0xc08c, 0x21, 0 + .dw 0xa240, 0xc08c, 0xa27f, 0xc08c, 0x21, 0 + .dw 0xa2c0, 0xc08c, 0xa2ff, 0xc08c, 0x21, 0 + .dw 0xa340, 0xc08c, 0xa37f, 0xc08c, 0x21, 0 + .dw 0xa3c0, 0xc08c, 0xa3ff, 0xc08c, 0x21, 0 + .dw 0xa440, 0xc08c, 0xa47f, 0xc08c, 0x21, 0 + .dw 0xa4c0, 0xc08c, 0xa4ff, 0xc08c, 0x21, 0 + .dw 0xa540, 0xc08c, 0xa57f, 0xc08c, 0x21, 0 + .dw 0xa5c0, 0xc08c, 0xa5ff, 0xc08c, 0x21, 0 + .dw 0xa640, 0xc08c, 0xa67f, 0xc08c, 0x21, 0 + .dw 0xa6c0, 0xc08c, 0xa6ff, 0xc08c, 0x21, 0 + .dw 0xa740, 0xc08c, 0xa77f, 0xc08c, 0x21, 0 + .dw 0xa7c0, 0xc08c, 0xa7ff, 0xc08c, 0x21, 0 + .dw 0xa840, 0xc08c, 0xa87f, 0xc08c, 0x21, 0 + .dw 0xa8c0, 0xc08c, 0xa8ff, 0xc08c, 0x21, 0 + .dw 0xa940, 0xc08c, 0xa97f, 0xc08c, 0x21, 0 + .dw 0xa9c0, 0xc08c, 0xa9ff, 0xc08c, 0x21, 0 + .dw 0xaa40, 0xc08c, 0xaa7f, 0xc08c, 0x21, 0 + .dw 0xaac0, 0xc08c, 0xaaff, 0xc08c, 0x21, 0 + .dw 0xab40, 0xc08c, 0xab7f, 0xc08c, 0x21, 0 + .dw 0xabc0, 0xc08c, 0xabff, 0xc08c, 0x21, 0 + .dw 0xac40, 0xc08c, 0xac7f, 0xc08c, 0x21, 0 + .dw 0xacc0, 0xc08c, 0xacff, 0xc08c, 0x21, 0 + .dw 0xad40, 0xc08c, 0xad7f, 0xc08c, 0x21, 0 + .dw 0xadc0, 0xc08c, 0xadff, 0xc08c, 0x21, 0 + .dw 0xae40, 0xc08c, 0xae7f, 0xc08c, 0x21, 0 + .dw 0xaec0, 0xc08c, 0xaeff, 0xc08c, 0x21, 0 + .dw 0xaf40, 0xc08c, 0xaf7f, 0xc08c, 0x21, 0 + .dw 0xafc0, 0xc08c, 0xafff, 0xc08c, 0x21, 0 + .dw 0xb040, 0xc08c, 0xb07f, 0xc08c, 0x21, 0 + .dw 0xb0c0, 0xc08c, 0xb0ff, 0xc08c, 0x21, 0 + .dw 0xb140, 0xc08c, 0xb17f, 0xc08c, 0x21, 0 + .dw 0xb1c0, 0xc08c, 0xb1ff, 0xc08c, 0x21, 0 + .dw 0xb240, 0xc08c, 0xb27f, 0xc08c, 0x21, 0 + .dw 0xb2c0, 0xc08c, 0xb2ff, 0xc08c, 0x21, 0 + .dw 0xb340, 0xc08c, 0xb37f, 0xc08c, 0x21, 0 + .dw 0xb3c0, 0xc08c, 0xb3ff, 0xc08c, 0x21, 0 + .dw 0xb440, 0xc08c, 0xb47f, 0xc08c, 0x21, 0 + .dw 0xb4c0, 0xc08c, 0xb4ff, 0xc08c, 0x21, 0 + .dw 0xb540, 0xc08c, 0xb57f, 0xc08c, 0x21, 0 + .dw 0xb5c0, 0xc08c, 0xb5ff, 0xc08c, 0x21, 0 + .dw 0xb640, 0xc08c, 0xb67f, 0xc08c, 0x21, 0 + .dw 0xb6c0, 0xc08c, 0xb6ff, 0xc08c, 0x21, 0 + .dw 0xb740, 0xc08c, 0xb77f, 0xc08c, 0x21, 0 + .dw 0xb7c0, 0xc08c, 0xb7ff, 0xc08c, 0x21, 0 + .dw 0xb840, 0xc08c, 0xb87f, 0xc08c, 0x21, 0 + .dw 0xb8c0, 0xc08c, 0xb8ff, 0xc08c, 0x21, 0 + .dw 0xb940, 0xc08c, 0xb97f, 0xc08c, 0x21, 0 + .dw 0xb9c0, 0xc08c, 0xbfff, 0xc08c, 0x21, 0 + .dw 0xc040, 0xc08c, 0xc07f, 0xc08c, 0x21, 0 + .dw 0xc0c0, 0xc08c, 0xc0ff, 0xc08c, 0x21, 0 + .dw 0xc140, 0xc08c, 0xc17f, 0xc08c, 0x21, 0 + .dw 0xc1c0, 0xc08c, 0xc1ff, 0xc08c, 0x21, 0 + .dw 0xc240, 0xc08c, 0xc27f, 0xc08c, 0x21, 0 + .dw 0xc2c0, 0xc08c, 0xc2ff, 0xc08c, 0x21, 0 + .dw 0xc340, 0xc08c, 0xc37f, 0xc08c, 0x21, 0 + .dw 0xc3c0, 0xc08c, 0xc3ff, 0xc08c, 0x21, 0 + .dw 0xc440, 0xc08c, 0xc47f, 0xc08c, 0x21, 0 + .dw 0xc4c0, 0xc08c, 0xc4ff, 0xc08c, 0x21, 0 + .dw 0xc540, 0xc08c, 0xc57f, 0xc08c, 0x21, 0 + .dw 0xc5c0, 0xc08c, 0xc5ff, 0xc08c, 0x21, 0 + .dw 0xc640, 0xc08c, 0xc67f, 0xc08c, 0x21, 0 + .dw 0xc6c0, 0xc08c, 0xc6ff, 0xc08c, 0x21, 0 + .dw 0xc740, 0xc08c, 0xc77f, 0xc08c, 0x21, 0 + .dw 0xc7c0, 0xc08c, 0xc7ff, 0xc08c, 0x21, 0 + .dw 0xc840, 0xc08c, 0xc87f, 0xc08c, 0x21, 0 + .dw 0xc8c0, 0xc08c, 0xc8ff, 0xc08c, 0x21, 0 + .dw 0xc940, 0xc08c, 0xc97f, 0xc08c, 0x21, 0 + .dw 0xc9c0, 0xc08c, 0xc9ff, 0xc08c, 0x21, 0 + .dw 0xca40, 0xc08c, 0xca7f, 0xc08c, 0x21, 0 + .dw 0xcac0, 0xc08c, 0xcaff, 0xc08c, 0x21, 0 + .dw 0xcb40, 0xc08c, 0xcb7f, 0xc08c, 0x21, 0 + .dw 0xcbc0, 0xc08c, 0xcbff, 0xc08c, 0x21, 0 + .dw 0xcc40, 0xc08c, 0xcc7f, 0xc08c, 0x21, 0 + .dw 0xccc0, 0xc08c, 0xccff, 0xc08c, 0x21, 0 + .dw 0xcd40, 0xc08c, 0xcd7f, 0xc08c, 0x21, 0 + .dw 0xcdc0, 0xc08c, 0xcdff, 0xc08c, 0x21, 0 + .dw 0xce40, 0xc08c, 0xce7f, 0xc08c, 0x21, 0 + .dw 0xcec0, 0xc08c, 0xceff, 0xc08c, 0x21, 0 + .dw 0xcf40, 0xc08c, 0xcf7f, 0xc08c, 0x21, 0 + .dw 0xcfc0, 0xc08c, 0xcfff, 0xc08c, 0x21, 0 + .dw 0xd040, 0xc08c, 0xd07f, 0xc08c, 0x21, 0 + .dw 0xd0c0, 0xc08c, 0xd0ff, 0xc08c, 0x21, 0 + .dw 0xd140, 0xc08c, 0xd17f, 0xc08c, 0x21, 0 + .dw 0xd1c0, 0xc08c, 0xd1ff, 0xc08c, 0x21, 0 + .dw 0xd240, 0xc08c, 0xd27f, 0xc08c, 0x21, 0 + .dw 0xd2c0, 0xc08c, 0xd2ff, 0xc08c, 0x21, 0 + .dw 0xd340, 0xc08c, 0xd37f, 0xc08c, 0x21, 0 + .dw 0xd3c0, 0xc08c, 0xd3ff, 0xc08c, 0x21, 0 + .dw 0xd440, 0xc08c, 0xd47f, 0xc08c, 0x21, 0 + .dw 0xd4c0, 0xc08c, 0xd4ff, 0xc08c, 0x21, 0 + .dw 0xd540, 0xc08c, 0xd57f, 0xc08c, 0x21, 0 + .dw 0xd5c0, 0xc08c, 0xd5ff, 0xc08c, 0x21, 0 + .dw 0xd640, 0xc08c, 0xd67f, 0xc08c, 0x21, 0 + .dw 0xd6c0, 0xc08c, 0xd6ff, 0xc08c, 0x21, 0 + .dw 0xd740, 0xc08c, 0xd77f, 0xc08c, 0x21, 0 + .dw 0xd7c0, 0xc08c, 0xd7ff, 0xc08c, 0x21, 0 + .dw 0xd840, 0xc08c, 0xd87f, 0xc08c, 0x21, 0 + .dw 0xd8c0, 0xc08c, 0xd8ff, 0xc08c, 0x21, 0 + .dw 0xd940, 0xc08c, 0xd97f, 0xc08c, 0x21, 0 + .dw 0xd9c0, 0xc08c, 0xdfff, 0xc08c, 0x21, 0 + .dw 0xe040, 0xc08c, 0xe07f, 0xc08c, 0x21, 0 + .dw 0xe0c0, 0xc08c, 0xe0ff, 0xc08c, 0x21, 0 + .dw 0xe140, 0xc08c, 0xe17f, 0xc08c, 0x21, 0 + .dw 0xe1c0, 0xc08c, 0xe1ff, 0xc08c, 0x21, 0 + .dw 0xe240, 0xc08c, 0xe27f, 0xc08c, 0x21, 0 + .dw 0xe2c0, 0xc08c, 0xe2ff, 0xc08c, 0x21, 0 + .dw 0xe340, 0xc08c, 0xe37f, 0xc08c, 0x21, 0 + .dw 0xe3c0, 0xc08c, 0xe3ff, 0xc08c, 0x21, 0 + .dw 0xe440, 0xc08c, 0xe47f, 0xc08c, 0x21, 0 + .dw 0xe4c0, 0xc08c, 0xe4ff, 0xc08c, 0x21, 0 + .dw 0xe540, 0xc08c, 0xe57f, 0xc08c, 0x21, 0 + .dw 0xe5c0, 0xc08c, 0xe5ff, 0xc08c, 0x21, 0 + .dw 0xe640, 0xc08c, 0xe67f, 0xc08c, 0x21, 0 + .dw 0xe6c0, 0xc08c, 0xe6ff, 0xc08c, 0x21, 0 + .dw 0xe740, 0xc08c, 0xe77f, 0xc08c, 0x21, 0 + .dw 0xe7c0, 0xc08c, 0xe7ff, 0xc08c, 0x21, 0 + .dw 0xe840, 0xc08c, 0xe87f, 0xc08c, 0x21, 0 + .dw 0xe8c0, 0xc08c, 0xe8ff, 0xc08c, 0x21, 0 + .dw 0xe940, 0xc08c, 0xe97f, 0xc08c, 0x21, 0 + .dw 0xe9c0, 0xc08c, 0xe9ff, 0xc08c, 0x21, 0 + .dw 0xea40, 0xc08c, 0xea7f, 0xc08c, 0x21, 0 + .dw 0xeac0, 0xc08c, 0xeaff, 0xc08c, 0x21, 0 + .dw 0xeb40, 0xc08c, 0xeb7f, 0xc08c, 0x21, 0 + .dw 0xebc0, 0xc08c, 0xebff, 0xc08c, 0x21, 0 + .dw 0xec40, 0xc08c, 0xec7f, 0xc08c, 0x21, 0 + .dw 0xecc0, 0xc08c, 0xecff, 0xc08c, 0x21, 0 + .dw 0xed40, 0xc08c, 0xed7f, 0xc08c, 0x21, 0 + .dw 0xedc0, 0xc08c, 0xedff, 0xc08c, 0x21, 0 + .dw 0xee40, 0xc08c, 0xee7f, 0xc08c, 0x21, 0 + .dw 0xeec0, 0xc08c, 0xeeff, 0xc08c, 0x21, 0 + .dw 0xef40, 0xc08c, 0xef7f, 0xc08c, 0x21, 0 + .dw 0xefc0, 0xc08c, 0xefff, 0xc08c, 0x21, 0 + .dw 0xf040, 0xc08c, 0xf07f, 0xc08c, 0x21, 0 + .dw 0xf0c0, 0xc08c, 0xf0ff, 0xc08c, 0x21, 0 + .dw 0xf140, 0xc08c, 0xf17f, 0xc08c, 0x21, 0 + .dw 0xf1c0, 0xc08c, 0xf1ff, 0xc08c, 0x21, 0 + .dw 0xf240, 0xc08c, 0xf27f, 0xc08c, 0x21, 0 + .dw 0xf2c0, 0xc08c, 0xf2ff, 0xc08c, 0x21, 0 + .dw 0xf340, 0xc08c, 0xf37f, 0xc08c, 0x21, 0 + .dw 0xf3c0, 0xc08c, 0xf3ff, 0xc08c, 0x21, 0 + .dw 0xf440, 0xc08c, 0xf47f, 0xc08c, 0x21, 0 + .dw 0xf4c0, 0xc08c, 0xf4ff, 0xc08c, 0x21, 0 + .dw 0xf540, 0xc08c, 0xf57f, 0xc08c, 0x21, 0 + .dw 0xf5c0, 0xc08c, 0xf5ff, 0xc08c, 0x21, 0 + .dw 0xf640, 0xc08c, 0xf67f, 0xc08c, 0x21, 0 + .dw 0xf6c0, 0xc08c, 0xf6ff, 0xc08c, 0x21, 0 + .dw 0xf740, 0xc08c, 0xf77f, 0xc08c, 0x21, 0 + .dw 0xf7c0, 0xc08c, 0xf7ff, 0xc08c, 0x21, 0 + .dw 0xf840, 0xc08c, 0xf87f, 0xc08c, 0x21, 0 + .dw 0xf8c0, 0xc08c, 0xf8ff, 0xc08c, 0x21, 0 + .dw 0xf940, 0xc08c, 0xf97f, 0xc08c, 0x21, 0 + .dw 0xf9c0, 0xc08c, 0xffff, 0xc08c, 0x21, 0 + .dw 0x0040, 0xc08d, 0x007f, 0xc08d, 0x21, 0 + .dw 0x00c0, 0xc08d, 0x00ff, 0xc08d, 0x21, 0 + .dw 0x0140, 0xc08d, 0x017f, 0xc08d, 0x21, 0 + .dw 0x01c0, 0xc08d, 0x01ff, 0xc08d, 0x21, 0 + .dw 0x0240, 0xc08d, 0x027f, 0xc08d, 0x21, 0 + .dw 0x02c0, 0xc08d, 0x02ff, 0xc08d, 0x21, 0 + .dw 0x0340, 0xc08d, 0x037f, 0xc08d, 0x21, 0 + .dw 0x03c0, 0xc08d, 0x03ff, 0xc08d, 0x21, 0 + .dw 0x0440, 0xc08d, 0x047f, 0xc08d, 0x21, 0 + .dw 0x04c0, 0xc08d, 0x04ff, 0xc08d, 0x21, 0 + .dw 0x0540, 0xc08d, 0x057f, 0xc08d, 0x21, 0 + .dw 0x05c0, 0xc08d, 0x05ff, 0xc08d, 0x21, 0 + .dw 0x0640, 0xc08d, 0x067f, 0xc08d, 0x21, 0 + .dw 0x06c0, 0xc08d, 0x06ff, 0xc08d, 0x21, 0 + .dw 0x0740, 0xc08d, 0x077f, 0xc08d, 0x21, 0 + .dw 0x07c0, 0xc08d, 0x07ff, 0xc08d, 0x21, 0 + .dw 0x0840, 0xc08d, 0x087f, 0xc08d, 0x21, 0 + .dw 0x08c0, 0xc08d, 0x08ff, 0xc08d, 0x21, 0 + .dw 0x0940, 0xc08d, 0x097f, 0xc08d, 0x21, 0 + .dw 0x09c0, 0xc08d, 0x09ff, 0xc08d, 0x21, 0 + .dw 0x0a40, 0xc08d, 0x0a7f, 0xc08d, 0x21, 0 + .dw 0x0ac0, 0xc08d, 0x0aff, 0xc08d, 0x21, 0 + .dw 0x0b40, 0xc08d, 0x0b7f, 0xc08d, 0x21, 0 + .dw 0x0bc0, 0xc08d, 0x0bff, 0xc08d, 0x21, 0 + .dw 0x0c40, 0xc08d, 0x0c7f, 0xc08d, 0x21, 0 + .dw 0x0cc0, 0xc08d, 0x0cff, 0xc08d, 0x21, 0 + .dw 0x0d40, 0xc08d, 0x0d7f, 0xc08d, 0x21, 0 + .dw 0x0dc0, 0xc08d, 0x0dff, 0xc08d, 0x21, 0 + .dw 0x0e40, 0xc08d, 0x0e7f, 0xc08d, 0x21, 0 + .dw 0x0ec0, 0xc08d, 0x0eff, 0xc08d, 0x21, 0 + .dw 0x0f40, 0xc08d, 0x0f7f, 0xc08d, 0x21, 0 + .dw 0x0fc0, 0xc08d, 0x0fff, 0xc08d, 0x21, 0 + .dw 0x1040, 0xc08d, 0x107f, 0xc08d, 0x21, 0 + .dw 0x10c0, 0xc08d, 0x10ff, 0xc08d, 0x21, 0 + .dw 0x1140, 0xc08d, 0x117f, 0xc08d, 0x21, 0 + .dw 0x11c0, 0xc08d, 0x11ff, 0xc08d, 0x21, 0 + .dw 0x1240, 0xc08d, 0x127f, 0xc08d, 0x21, 0 + .dw 0x12c0, 0xc08d, 0x12ff, 0xc08d, 0x21, 0 + .dw 0x1340, 0xc08d, 0x137f, 0xc08d, 0x21, 0 + .dw 0x13c0, 0xc08d, 0x13ff, 0xc08d, 0x21, 0 + .dw 0x1440, 0xc08d, 0x147f, 0xc08d, 0x21, 0 + .dw 0x14c0, 0xc08d, 0x14ff, 0xc08d, 0x21, 0 + .dw 0x1540, 0xc08d, 0x157f, 0xc08d, 0x21, 0 + .dw 0x15c0, 0xc08d, 0x15ff, 0xc08d, 0x21, 0 + .dw 0x1640, 0xc08d, 0x167f, 0xc08d, 0x21, 0 + .dw 0x16c0, 0xc08d, 0x16ff, 0xc08d, 0x21, 0 + .dw 0x1740, 0xc08d, 0x177f, 0xc08d, 0x21, 0 + .dw 0x17c0, 0xc08d, 0x17ff, 0xc08d, 0x21, 0 + .dw 0x1840, 0xc08d, 0x187f, 0xc08d, 0x21, 0 + .dw 0x18c0, 0xc08d, 0x18ff, 0xc08d, 0x21, 0 + .dw 0x1940, 0xc08d, 0x197f, 0xc08d, 0x21, 0 + .dw 0x19c0, 0xc08d, 0x1fff, 0xc08d, 0x21, 0 + .dw 0x2040, 0xc08d, 0x207f, 0xc08d, 0x21, 0 + .dw 0x20c0, 0xc08d, 0x20ff, 0xc08d, 0x21, 0 + .dw 0x2140, 0xc08d, 0x217f, 0xc08d, 0x21, 0 + .dw 0x21c0, 0xc08d, 0x21ff, 0xc08d, 0x21, 0 + .dw 0x2240, 0xc08d, 0x227f, 0xc08d, 0x21, 0 + .dw 0x22c0, 0xc08d, 0x22ff, 0xc08d, 0x21, 0 + .dw 0x2340, 0xc08d, 0x237f, 0xc08d, 0x21, 0 + .dw 0x23c0, 0xc08d, 0x23ff, 0xc08d, 0x21, 0 + .dw 0x2440, 0xc08d, 0x247f, 0xc08d, 0x21, 0 + .dw 0x24c0, 0xc08d, 0x24ff, 0xc08d, 0x21, 0 + .dw 0x2540, 0xc08d, 0x257f, 0xc08d, 0x21, 0 + .dw 0x25c0, 0xc08d, 0x25ff, 0xc08d, 0x21, 0 + .dw 0x2640, 0xc08d, 0x267f, 0xc08d, 0x21, 0 + .dw 0x26c0, 0xc08d, 0x26ff, 0xc08d, 0x21, 0 + .dw 0x2740, 0xc08d, 0x277f, 0xc08d, 0x21, 0 + .dw 0x27c0, 0xc08d, 0x27ff, 0xc08d, 0x21, 0 + .dw 0x2840, 0xc08d, 0x287f, 0xc08d, 0x21, 0 + .dw 0x28c0, 0xc08d, 0x28ff, 0xc08d, 0x21, 0 + .dw 0x2940, 0xc08d, 0x297f, 0xc08d, 0x21, 0 + .dw 0x29c0, 0xc08d, 0x29ff, 0xc08d, 0x21, 0 + .dw 0x2a40, 0xc08d, 0x2a7f, 0xc08d, 0x21, 0 + .dw 0x2ac0, 0xc08d, 0x2aff, 0xc08d, 0x21, 0 + .dw 0x2b40, 0xc08d, 0x2b7f, 0xc08d, 0x21, 0 + .dw 0x2bc0, 0xc08d, 0x2bff, 0xc08d, 0x21, 0 + .dw 0x2c40, 0xc08d, 0x2c7f, 0xc08d, 0x21, 0 + .dw 0x2cc0, 0xc08d, 0x2cff, 0xc08d, 0x21, 0 + .dw 0x2d40, 0xc08d, 0x2d7f, 0xc08d, 0x21, 0 + .dw 0x2dc0, 0xc08d, 0x2dff, 0xc08d, 0x21, 0 + .dw 0x2e40, 0xc08d, 0x2e7f, 0xc08d, 0x21, 0 + .dw 0x2ec0, 0xc08d, 0x2eff, 0xc08d, 0x21, 0 + .dw 0x2f40, 0xc08d, 0x2f7f, 0xc08d, 0x21, 0 + .dw 0x2fc0, 0xc08d, 0x2fff, 0xc08d, 0x21, 0 + .dw 0x3040, 0xc08d, 0x307f, 0xc08d, 0x21, 0 + .dw 0x30c0, 0xc08d, 0x30ff, 0xc08d, 0x21, 0 + .dw 0x3140, 0xc08d, 0x317f, 0xc08d, 0x21, 0 + .dw 0x31c0, 0xc08d, 0x31ff, 0xc08d, 0x21, 0 + .dw 0x3240, 0xc08d, 0x327f, 0xc08d, 0x21, 0 + .dw 0x32c0, 0xc08d, 0x32ff, 0xc08d, 0x21, 0 + .dw 0x3340, 0xc08d, 0x337f, 0xc08d, 0x21, 0 + .dw 0x33c0, 0xc08d, 0x33ff, 0xc08d, 0x21, 0 + .dw 0x3440, 0xc08d, 0x347f, 0xc08d, 0x21, 0 + .dw 0x34c0, 0xc08d, 0x34ff, 0xc08d, 0x21, 0 + .dw 0x3540, 0xc08d, 0x357f, 0xc08d, 0x21, 0 + .dw 0x35c0, 0xc08d, 0x35ff, 0xc08d, 0x21, 0 + .dw 0x3640, 0xc08d, 0x367f, 0xc08d, 0x21, 0 + .dw 0x36c0, 0xc08d, 0x36ff, 0xc08d, 0x21, 0 + .dw 0x3740, 0xc08d, 0x377f, 0xc08d, 0x21, 0 + .dw 0x37c0, 0xc08d, 0x37ff, 0xc08d, 0x21, 0 + .dw 0x3840, 0xc08d, 0x387f, 0xc08d, 0x21, 0 + .dw 0x38c0, 0xc08d, 0x38ff, 0xc08d, 0x21, 0 + .dw 0x3940, 0xc08d, 0x397f, 0xc08d, 0x21, 0 + .dw 0x39c0, 0xc08d, 0x3fff, 0xc08d, 0x21, 0 + .dw 0x4040, 0xc08d, 0x407f, 0xc08d, 0x21, 0 + .dw 0x40c0, 0xc08d, 0x40ff, 0xc08d, 0x21, 0 + .dw 0x4140, 0xc08d, 0x417f, 0xc08d, 0x21, 0 + .dw 0x41c0, 0xc08d, 0x41ff, 0xc08d, 0x21, 0 + .dw 0x4240, 0xc08d, 0x427f, 0xc08d, 0x21, 0 + .dw 0x42c0, 0xc08d, 0x42ff, 0xc08d, 0x21, 0 + .dw 0x4340, 0xc08d, 0x437f, 0xc08d, 0x21, 0 + .dw 0x43c0, 0xc08d, 0x43ff, 0xc08d, 0x21, 0 + .dw 0x4440, 0xc08d, 0x447f, 0xc08d, 0x21, 0 + .dw 0x44c0, 0xc08d, 0x44ff, 0xc08d, 0x21, 0 + .dw 0x4540, 0xc08d, 0x457f, 0xc08d, 0x21, 0 + .dw 0x45c0, 0xc08d, 0x45ff, 0xc08d, 0x21, 0 + .dw 0x4640, 0xc08d, 0x467f, 0xc08d, 0x21, 0 + .dw 0x46c0, 0xc08d, 0x46ff, 0xc08d, 0x21, 0 + .dw 0x4740, 0xc08d, 0x477f, 0xc08d, 0x21, 0 + .dw 0x47c0, 0xc08d, 0x47ff, 0xc08d, 0x21, 0 + .dw 0x4840, 0xc08d, 0x487f, 0xc08d, 0x21, 0 + .dw 0x48c0, 0xc08d, 0x48ff, 0xc08d, 0x21, 0 + .dw 0x4940, 0xc08d, 0x497f, 0xc08d, 0x21, 0 + .dw 0x49c0, 0xc08d, 0x49ff, 0xc08d, 0x21, 0 + .dw 0x4a40, 0xc08d, 0x4a7f, 0xc08d, 0x21, 0 + .dw 0x4ac0, 0xc08d, 0x4aff, 0xc08d, 0x21, 0 + .dw 0x4b40, 0xc08d, 0x4b7f, 0xc08d, 0x21, 0 + .dw 0x4bc0, 0xc08d, 0x4bff, 0xc08d, 0x21, 0 + .dw 0x4c40, 0xc08d, 0x4c7f, 0xc08d, 0x21, 0 + .dw 0x4cc0, 0xc08d, 0x4cff, 0xc08d, 0x21, 0 + .dw 0x4d40, 0xc08d, 0x4d7f, 0xc08d, 0x21, 0 + .dw 0x4dc0, 0xc08d, 0x4dff, 0xc08d, 0x21, 0 + .dw 0x4e40, 0xc08d, 0x4e7f, 0xc08d, 0x21, 0 + .dw 0x4ec0, 0xc08d, 0x4eff, 0xc08d, 0x21, 0 + .dw 0x4f40, 0xc08d, 0x4f7f, 0xc08d, 0x21, 0 + .dw 0x4fc0, 0xc08d, 0x4fff, 0xc08d, 0x21, 0 + .dw 0x5040, 0xc08d, 0x507f, 0xc08d, 0x21, 0 + .dw 0x50c0, 0xc08d, 0x50ff, 0xc08d, 0x21, 0 + .dw 0x5140, 0xc08d, 0x517f, 0xc08d, 0x21, 0 + .dw 0x51c0, 0xc08d, 0x51ff, 0xc08d, 0x21, 0 + .dw 0x5240, 0xc08d, 0x527f, 0xc08d, 0x21, 0 + .dw 0x52c0, 0xc08d, 0x52ff, 0xc08d, 0x21, 0 + .dw 0x5340, 0xc08d, 0x537f, 0xc08d, 0x21, 0 + .dw 0x53c0, 0xc08d, 0x53ff, 0xc08d, 0x21, 0 + .dw 0x5440, 0xc08d, 0x547f, 0xc08d, 0x21, 0 + .dw 0x54c0, 0xc08d, 0x54ff, 0xc08d, 0x21, 0 + .dw 0x5540, 0xc08d, 0x557f, 0xc08d, 0x21, 0 + .dw 0x55c0, 0xc08d, 0x55ff, 0xc08d, 0x21, 0 + .dw 0x5640, 0xc08d, 0x567f, 0xc08d, 0x21, 0 + .dw 0x56c0, 0xc08d, 0x56ff, 0xc08d, 0x21, 0 + .dw 0x5740, 0xc08d, 0x577f, 0xc08d, 0x21, 0 + .dw 0x57c0, 0xc08d, 0x57ff, 0xc08d, 0x21, 0 + .dw 0x5840, 0xc08d, 0x587f, 0xc08d, 0x21, 0 + .dw 0x58c0, 0xc08d, 0x58ff, 0xc08d, 0x21, 0 + .dw 0x5940, 0xc08d, 0x597f, 0xc08d, 0x21, 0 + .dw 0x59c0, 0xc08d, 0x5fff, 0xc08d, 0x21, 0 + .dw 0x6040, 0xc08d, 0x607f, 0xc08d, 0x21, 0 + .dw 0x60c0, 0xc08d, 0x60ff, 0xc08d, 0x21, 0 + .dw 0x6140, 0xc08d, 0x617f, 0xc08d, 0x21, 0 + .dw 0x61c0, 0xc08d, 0x61ff, 0xc08d, 0x21, 0 + .dw 0x6240, 0xc08d, 0x627f, 0xc08d, 0x21, 0 + .dw 0x62c0, 0xc08d, 0x62ff, 0xc08d, 0x21, 0 + .dw 0x6340, 0xc08d, 0x637f, 0xc08d, 0x21, 0 + .dw 0x63c0, 0xc08d, 0x63ff, 0xc08d, 0x21, 0 + .dw 0x6440, 0xc08d, 0x647f, 0xc08d, 0x21, 0 + .dw 0x64c0, 0xc08d, 0x64ff, 0xc08d, 0x21, 0 + .dw 0x6540, 0xc08d, 0x657f, 0xc08d, 0x21, 0 + .dw 0x65c0, 0xc08d, 0x65ff, 0xc08d, 0x21, 0 + .dw 0x6640, 0xc08d, 0x667f, 0xc08d, 0x21, 0 + .dw 0x66c0, 0xc08d, 0x66ff, 0xc08d, 0x21, 0 + .dw 0x6740, 0xc08d, 0x677f, 0xc08d, 0x21, 0 + .dw 0x67c0, 0xc08d, 0x67ff, 0xc08d, 0x21, 0 + .dw 0x6840, 0xc08d, 0x687f, 0xc08d, 0x21, 0 + .dw 0x68c0, 0xc08d, 0x68ff, 0xc08d, 0x21, 0 + .dw 0x6940, 0xc08d, 0x697f, 0xc08d, 0x21, 0 + .dw 0x69c0, 0xc08d, 0x69ff, 0xc08d, 0x21, 0 + .dw 0x6a40, 0xc08d, 0x6a7f, 0xc08d, 0x21, 0 + .dw 0x6ac0, 0xc08d, 0x6aff, 0xc08d, 0x21, 0 + .dw 0x6b40, 0xc08d, 0x6b7f, 0xc08d, 0x21, 0 + .dw 0x6bc0, 0xc08d, 0x6bff, 0xc08d, 0x21, 0 + .dw 0x6c40, 0xc08d, 0x6c7f, 0xc08d, 0x21, 0 + .dw 0x6cc0, 0xc08d, 0x6cff, 0xc08d, 0x21, 0 + .dw 0x6d40, 0xc08d, 0x6d7f, 0xc08d, 0x21, 0 + .dw 0x6dc0, 0xc08d, 0x6dff, 0xc08d, 0x21, 0 + .dw 0x6e40, 0xc08d, 0x6e7f, 0xc08d, 0x21, 0 + .dw 0x6ec0, 0xc08d, 0x6eff, 0xc08d, 0x21, 0 + .dw 0x6f40, 0xc08d, 0x6f7f, 0xc08d, 0x21, 0 + .dw 0x6fc0, 0xc08d, 0x6fff, 0xc08d, 0x21, 0 + .dw 0x7040, 0xc08d, 0x707f, 0xc08d, 0x21, 0 + .dw 0x70c0, 0xc08d, 0x70ff, 0xc08d, 0x21, 0 + .dw 0x7140, 0xc08d, 0x717f, 0xc08d, 0x21, 0 + .dw 0x71c0, 0xc08d, 0x71ff, 0xc08d, 0x21, 0 + .dw 0x7240, 0xc08d, 0x727f, 0xc08d, 0x21, 0 + .dw 0x72c0, 0xc08d, 0x72ff, 0xc08d, 0x21, 0 + .dw 0x7340, 0xc08d, 0x737f, 0xc08d, 0x21, 0 + .dw 0x73c0, 0xc08d, 0x73ff, 0xc08d, 0x21, 0 + .dw 0x7440, 0xc08d, 0x747f, 0xc08d, 0x21, 0 + .dw 0x74c0, 0xc08d, 0x74ff, 0xc08d, 0x21, 0 + .dw 0x7540, 0xc08d, 0x757f, 0xc08d, 0x21, 0 + .dw 0x75c0, 0xc08d, 0x75ff, 0xc08d, 0x21, 0 + .dw 0x7640, 0xc08d, 0x767f, 0xc08d, 0x21, 0 + .dw 0x76c0, 0xc08d, 0x76ff, 0xc08d, 0x21, 0 + .dw 0x7740, 0xc08d, 0x777f, 0xc08d, 0x21, 0 + .dw 0x77c0, 0xc08d, 0x77ff, 0xc08d, 0x21, 0 + .dw 0x7840, 0xc08d, 0x787f, 0xc08d, 0x21, 0 + .dw 0x78c0, 0xc08d, 0x78ff, 0xc08d, 0x21, 0 + .dw 0x7940, 0xc08d, 0x797f, 0xc08d, 0x21, 0 + .dw 0x79c0, 0xc08d, 0x7fff, 0xc08d, 0x21, 0 + .dw 0x8040, 0xc08d, 0x807f, 0xc08d, 0x21, 0 + .dw 0x80c0, 0xc08d, 0x80ff, 0xc08d, 0x21, 0 + .dw 0x8140, 0xc08d, 0x817f, 0xc08d, 0x21, 0 + .dw 0x81c0, 0xc08d, 0x81ff, 0xc08d, 0x21, 0 + .dw 0x8240, 0xc08d, 0x827f, 0xc08d, 0x21, 0 + .dw 0x82c0, 0xc08d, 0x82ff, 0xc08d, 0x21, 0 + .dw 0x8340, 0xc08d, 0x837f, 0xc08d, 0x21, 0 + .dw 0x83c0, 0xc08d, 0x83ff, 0xc08d, 0x21, 0 + .dw 0x8440, 0xc08d, 0x847f, 0xc08d, 0x21, 0 + .dw 0x84c0, 0xc08d, 0x84ff, 0xc08d, 0x21, 0 + .dw 0x8540, 0xc08d, 0x857f, 0xc08d, 0x21, 0 + .dw 0x85c0, 0xc08d, 0x85ff, 0xc08d, 0x21, 0 + .dw 0x8640, 0xc08d, 0x867f, 0xc08d, 0x21, 0 + .dw 0x86c0, 0xc08d, 0x86ff, 0xc08d, 0x21, 0 + .dw 0x8740, 0xc08d, 0x877f, 0xc08d, 0x21, 0 + .dw 0x87c0, 0xc08d, 0x87ff, 0xc08d, 0x21, 0 + .dw 0x8840, 0xc08d, 0x887f, 0xc08d, 0x21, 0 + .dw 0x88c0, 0xc08d, 0x88ff, 0xc08d, 0x21, 0 + .dw 0x8940, 0xc08d, 0x897f, 0xc08d, 0x21, 0 + .dw 0x89c0, 0xc08d, 0x89ff, 0xc08d, 0x21, 0 + .dw 0x8a40, 0xc08d, 0x8a7f, 0xc08d, 0x21, 0 + .dw 0x8ac0, 0xc08d, 0x8aff, 0xc08d, 0x21, 0 + .dw 0x8b40, 0xc08d, 0x8b7f, 0xc08d, 0x21, 0 + .dw 0x8bc0, 0xc08d, 0x8bff, 0xc08d, 0x21, 0 + .dw 0x8c40, 0xc08d, 0x8c7f, 0xc08d, 0x21, 0 + .dw 0x8cc0, 0xc08d, 0x8cff, 0xc08d, 0x21, 0 + .dw 0x8d40, 0xc08d, 0x8d7f, 0xc08d, 0x21, 0 + .dw 0x8dc0, 0xc08d, 0x8dff, 0xc08d, 0x21, 0 + .dw 0x8e40, 0xc08d, 0x8e7f, 0xc08d, 0x21, 0 + .dw 0x8ec0, 0xc08d, 0x8eff, 0xc08d, 0x21, 0 + .dw 0x8f40, 0xc08d, 0x8f7f, 0xc08d, 0x21, 0 + .dw 0x8fc0, 0xc08d, 0x8fff, 0xc08d, 0x21, 0 + .dw 0x9040, 0xc08d, 0x907f, 0xc08d, 0x21, 0 + .dw 0x90c0, 0xc08d, 0x90ff, 0xc08d, 0x21, 0 + .dw 0x9140, 0xc08d, 0x917f, 0xc08d, 0x21, 0 + .dw 0x91c0, 0xc08d, 0x91ff, 0xc08d, 0x21, 0 + .dw 0x9240, 0xc08d, 0x927f, 0xc08d, 0x21, 0 + .dw 0x92c0, 0xc08d, 0x92ff, 0xc08d, 0x21, 0 + .dw 0x9340, 0xc08d, 0x937f, 0xc08d, 0x21, 0 + .dw 0x93c0, 0xc08d, 0x93ff, 0xc08d, 0x21, 0 + .dw 0x9440, 0xc08d, 0x947f, 0xc08d, 0x21, 0 + .dw 0x94c0, 0xc08d, 0x94ff, 0xc08d, 0x21, 0 + .dw 0x9540, 0xc08d, 0x957f, 0xc08d, 0x21, 0 + .dw 0x95c0, 0xc08d, 0x95ff, 0xc08d, 0x21, 0 + .dw 0x9640, 0xc08d, 0x967f, 0xc08d, 0x21, 0 + .dw 0x96c0, 0xc08d, 0x96ff, 0xc08d, 0x21, 0 + .dw 0x9740, 0xc08d, 0x977f, 0xc08d, 0x21, 0 + .dw 0x97c0, 0xc08d, 0x97ff, 0xc08d, 0x21, 0 + .dw 0x9840, 0xc08d, 0x987f, 0xc08d, 0x21, 0 + .dw 0x98c0, 0xc08d, 0x98ff, 0xc08d, 0x21, 0 + .dw 0x9940, 0xc08d, 0x997f, 0xc08d, 0x21, 0 + .dw 0x99c0, 0xc08d, 0x9fff, 0xc08d, 0x21, 0 + .dw 0xa040, 0xc08d, 0xa07f, 0xc08d, 0x21, 0 + .dw 0xa0c0, 0xc08d, 0xa0ff, 0xc08d, 0x21, 0 + .dw 0xa140, 0xc08d, 0xa17f, 0xc08d, 0x21, 0 + .dw 0xa1c0, 0xc08d, 0xa1ff, 0xc08d, 0x21, 0 + .dw 0xa240, 0xc08d, 0xa27f, 0xc08d, 0x21, 0 + .dw 0xa2c0, 0xc08d, 0xa2ff, 0xc08d, 0x21, 0 + .dw 0xa340, 0xc08d, 0xa37f, 0xc08d, 0x21, 0 + .dw 0xa3c0, 0xc08d, 0xa3ff, 0xc08d, 0x21, 0 + .dw 0xa440, 0xc08d, 0xa47f, 0xc08d, 0x21, 0 + .dw 0xa4c0, 0xc08d, 0xa4ff, 0xc08d, 0x21, 0 + .dw 0xa540, 0xc08d, 0xa57f, 0xc08d, 0x21, 0 + .dw 0xa5c0, 0xc08d, 0xa5ff, 0xc08d, 0x21, 0 + .dw 0xa640, 0xc08d, 0xa67f, 0xc08d, 0x21, 0 + .dw 0xa6c0, 0xc08d, 0xa6ff, 0xc08d, 0x21, 0 + .dw 0xa740, 0xc08d, 0xa77f, 0xc08d, 0x21, 0 + .dw 0xa7c0, 0xc08d, 0xa7ff, 0xc08d, 0x21, 0 + .dw 0xa840, 0xc08d, 0xa87f, 0xc08d, 0x21, 0 + .dw 0xa8c0, 0xc08d, 0xa8ff, 0xc08d, 0x21, 0 + .dw 0xa940, 0xc08d, 0xa97f, 0xc08d, 0x21, 0 + .dw 0xa9c0, 0xc08d, 0xa9ff, 0xc08d, 0x21, 0 + .dw 0xaa40, 0xc08d, 0xaa7f, 0xc08d, 0x21, 0 + .dw 0xaac0, 0xc08d, 0xaaff, 0xc08d, 0x21, 0 + .dw 0xab40, 0xc08d, 0xab7f, 0xc08d, 0x21, 0 + .dw 0xabc0, 0xc08d, 0xabff, 0xc08d, 0x21, 0 + .dw 0xac40, 0xc08d, 0xac7f, 0xc08d, 0x21, 0 + .dw 0xacc0, 0xc08d, 0xacff, 0xc08d, 0x21, 0 + .dw 0xad40, 0xc08d, 0xad7f, 0xc08d, 0x21, 0 + .dw 0xadc0, 0xc08d, 0xadff, 0xc08d, 0x21, 0 + .dw 0xae40, 0xc08d, 0xae7f, 0xc08d, 0x21, 0 + .dw 0xaec0, 0xc08d, 0xaeff, 0xc08d, 0x21, 0 + .dw 0xaf40, 0xc08d, 0xaf7f, 0xc08d, 0x21, 0 + .dw 0xafc0, 0xc08d, 0xafff, 0xc08d, 0x21, 0 + .dw 0xb040, 0xc08d, 0xb07f, 0xc08d, 0x21, 0 + .dw 0xb0c0, 0xc08d, 0xb0ff, 0xc08d, 0x21, 0 + .dw 0xb140, 0xc08d, 0xb17f, 0xc08d, 0x21, 0 + .dw 0xb1c0, 0xc08d, 0xb1ff, 0xc08d, 0x21, 0 + .dw 0xb240, 0xc08d, 0xb27f, 0xc08d, 0x21, 0 + .dw 0xb2c0, 0xc08d, 0xb2ff, 0xc08d, 0x21, 0 + .dw 0xb340, 0xc08d, 0xb37f, 0xc08d, 0x21, 0 + .dw 0xb3c0, 0xc08d, 0xb3ff, 0xc08d, 0x21, 0 + .dw 0xb440, 0xc08d, 0xb47f, 0xc08d, 0x21, 0 + .dw 0xb4c0, 0xc08d, 0xb4ff, 0xc08d, 0x21, 0 + .dw 0xb540, 0xc08d, 0xb57f, 0xc08d, 0x21, 0 + .dw 0xb5c0, 0xc08d, 0xb5ff, 0xc08d, 0x21, 0 + .dw 0xb640, 0xc08d, 0xb67f, 0xc08d, 0x21, 0 + .dw 0xb6c0, 0xc08d, 0xb6ff, 0xc08d, 0x21, 0 + .dw 0xb740, 0xc08d, 0xb77f, 0xc08d, 0x21, 0 + .dw 0xb7c0, 0xc08d, 0xb7ff, 0xc08d, 0x21, 0 + .dw 0xb840, 0xc08d, 0xb87f, 0xc08d, 0x21, 0 + .dw 0xb8c0, 0xc08d, 0xb8ff, 0xc08d, 0x21, 0 + .dw 0xb940, 0xc08d, 0xb97f, 0xc08d, 0x21, 0 + .dw 0xb9c0, 0xc08d, 0xbfff, 0xc08d, 0x21, 0 + .dw 0xc040, 0xc08d, 0xc07f, 0xc08d, 0x21, 0 + .dw 0xc0c0, 0xc08d, 0xc0ff, 0xc08d, 0x21, 0 + .dw 0xc140, 0xc08d, 0xc17f, 0xc08d, 0x21, 0 + .dw 0xc1c0, 0xc08d, 0xc1ff, 0xc08d, 0x21, 0 + .dw 0xc240, 0xc08d, 0xc27f, 0xc08d, 0x21, 0 + .dw 0xc2c0, 0xc08d, 0xc2ff, 0xc08d, 0x21, 0 + .dw 0xc340, 0xc08d, 0xc37f, 0xc08d, 0x21, 0 + .dw 0xc3c0, 0xc08d, 0xc3ff, 0xc08d, 0x21, 0 + .dw 0xc440, 0xc08d, 0xc47f, 0xc08d, 0x21, 0 + .dw 0xc4c0, 0xc08d, 0xc4ff, 0xc08d, 0x21, 0 + .dw 0xc540, 0xc08d, 0xc57f, 0xc08d, 0x21, 0 + .dw 0xc5c0, 0xc08d, 0xc5ff, 0xc08d, 0x21, 0 + .dw 0xc640, 0xc08d, 0xc67f, 0xc08d, 0x21, 0 + .dw 0xc6c0, 0xc08d, 0xc6ff, 0xc08d, 0x21, 0 + .dw 0xc740, 0xc08d, 0xc77f, 0xc08d, 0x21, 0 + .dw 0xc7c0, 0xc08d, 0xc7ff, 0xc08d, 0x21, 0 + .dw 0xc840, 0xc08d, 0xc87f, 0xc08d, 0x21, 0 + .dw 0xc8c0, 0xc08d, 0xc8ff, 0xc08d, 0x21, 0 + .dw 0xc940, 0xc08d, 0xc97f, 0xc08d, 0x21, 0 + .dw 0xc9c0, 0xc08d, 0xc9ff, 0xc08d, 0x21, 0 + .dw 0xca40, 0xc08d, 0xca7f, 0xc08d, 0x21, 0 + .dw 0xcac0, 0xc08d, 0xcaff, 0xc08d, 0x21, 0 + .dw 0xcb40, 0xc08d, 0xcb7f, 0xc08d, 0x21, 0 + .dw 0xcbc0, 0xc08d, 0xcbff, 0xc08d, 0x21, 0 + .dw 0xcc40, 0xc08d, 0xcc7f, 0xc08d, 0x21, 0 + .dw 0xccc0, 0xc08d, 0xccff, 0xc08d, 0x21, 0 + .dw 0xcd40, 0xc08d, 0xcd7f, 0xc08d, 0x21, 0 + .dw 0xcdc0, 0xc08d, 0xcdff, 0xc08d, 0x21, 0 + .dw 0xce40, 0xc08d, 0xce7f, 0xc08d, 0x21, 0 + .dw 0xcec0, 0xc08d, 0xceff, 0xc08d, 0x21, 0 + .dw 0xcf40, 0xc08d, 0xcf7f, 0xc08d, 0x21, 0 + .dw 0xcfc0, 0xc08d, 0xcfff, 0xc08d, 0x21, 0 + .dw 0xd040, 0xc08d, 0xd07f, 0xc08d, 0x21, 0 + .dw 0xd0c0, 0xc08d, 0xd0ff, 0xc08d, 0x21, 0 + .dw 0xd140, 0xc08d, 0xd17f, 0xc08d, 0x21, 0 + .dw 0xd1c0, 0xc08d, 0xd1ff, 0xc08d, 0x21, 0 + .dw 0xd240, 0xc08d, 0xd27f, 0xc08d, 0x21, 0 + .dw 0xd2c0, 0xc08d, 0xd2ff, 0xc08d, 0x21, 0 + .dw 0xd340, 0xc08d, 0xd37f, 0xc08d, 0x21, 0 + .dw 0xd3c0, 0xc08d, 0xd3ff, 0xc08d, 0x21, 0 + .dw 0xd440, 0xc08d, 0xd47f, 0xc08d, 0x21, 0 + .dw 0xd4c0, 0xc08d, 0xd4ff, 0xc08d, 0x21, 0 + .dw 0xd540, 0xc08d, 0xd57f, 0xc08d, 0x21, 0 + .dw 0xd5c0, 0xc08d, 0xd5ff, 0xc08d, 0x21, 0 + .dw 0xd640, 0xc08d, 0xd67f, 0xc08d, 0x21, 0 + .dw 0xd6c0, 0xc08d, 0xd6ff, 0xc08d, 0x21, 0 + .dw 0xd740, 0xc08d, 0xd77f, 0xc08d, 0x21, 0 + .dw 0xd7c0, 0xc08d, 0xd7ff, 0xc08d, 0x21, 0 + .dw 0xd840, 0xc08d, 0xd87f, 0xc08d, 0x21, 0 + .dw 0xd8c0, 0xc08d, 0xd8ff, 0xc08d, 0x21, 0 + .dw 0xd940, 0xc08d, 0xd97f, 0xc08d, 0x21, 0 + .dw 0xd9c0, 0xc08d, 0xdfff, 0xc08d, 0x21, 0 + .dw 0xe040, 0xc08d, 0xe07f, 0xc08d, 0x21, 0 + .dw 0xe0c0, 0xc08d, 0xe0ff, 0xc08d, 0x21, 0 + .dw 0xe140, 0xc08d, 0xe17f, 0xc08d, 0x21, 0 + .dw 0xe1c0, 0xc08d, 0xe1ff, 0xc08d, 0x21, 0 + .dw 0xe240, 0xc08d, 0xe27f, 0xc08d, 0x21, 0 + .dw 0xe2c0, 0xc08d, 0xe2ff, 0xc08d, 0x21, 0 + .dw 0xe340, 0xc08d, 0xe37f, 0xc08d, 0x21, 0 + .dw 0xe3c0, 0xc08d, 0xe3ff, 0xc08d, 0x21, 0 + .dw 0xe440, 0xc08d, 0xe47f, 0xc08d, 0x21, 0 + .dw 0xe4c0, 0xc08d, 0xe4ff, 0xc08d, 0x21, 0 + .dw 0xe540, 0xc08d, 0xe57f, 0xc08d, 0x21, 0 + .dw 0xe5c0, 0xc08d, 0xe5ff, 0xc08d, 0x21, 0 + .dw 0xe640, 0xc08d, 0xe67f, 0xc08d, 0x21, 0 + .dw 0xe6c0, 0xc08d, 0xe6ff, 0xc08d, 0x21, 0 + .dw 0xe740, 0xc08d, 0xe77f, 0xc08d, 0x21, 0 + .dw 0xe7c0, 0xc08d, 0xe7ff, 0xc08d, 0x21, 0 + .dw 0xe840, 0xc08d, 0xe87f, 0xc08d, 0x21, 0 + .dw 0xe8c0, 0xc08d, 0xe8ff, 0xc08d, 0x21, 0 + .dw 0xe940, 0xc08d, 0xe97f, 0xc08d, 0x21, 0 + .dw 0xe9c0, 0xc08d, 0xe9ff, 0xc08d, 0x21, 0 + .dw 0xea40, 0xc08d, 0xea7f, 0xc08d, 0x21, 0 + .dw 0xeac0, 0xc08d, 0xeaff, 0xc08d, 0x21, 0 + .dw 0xeb40, 0xc08d, 0xeb7f, 0xc08d, 0x21, 0 + .dw 0xebc0, 0xc08d, 0xebff, 0xc08d, 0x21, 0 + .dw 0xec40, 0xc08d, 0xec7f, 0xc08d, 0x21, 0 + .dw 0xecc0, 0xc08d, 0xecff, 0xc08d, 0x21, 0 + .dw 0xed40, 0xc08d, 0xed7f, 0xc08d, 0x21, 0 + .dw 0xedc0, 0xc08d, 0xedff, 0xc08d, 0x21, 0 + .dw 0xee40, 0xc08d, 0xee7f, 0xc08d, 0x21, 0 + .dw 0xeec0, 0xc08d, 0xeeff, 0xc08d, 0x21, 0 + .dw 0xef40, 0xc08d, 0xef7f, 0xc08d, 0x21, 0 + .dw 0xefc0, 0xc08d, 0xefff, 0xc08d, 0x21, 0 + .dw 0xf040, 0xc08d, 0xf07f, 0xc08d, 0x21, 0 + .dw 0xf0c0, 0xc08d, 0xf0ff, 0xc08d, 0x21, 0 + .dw 0xf140, 0xc08d, 0xf17f, 0xc08d, 0x21, 0 + .dw 0xf1c0, 0xc08d, 0xf1ff, 0xc08d, 0x21, 0 + .dw 0xf240, 0xc08d, 0xf27f, 0xc08d, 0x21, 0 + .dw 0xf2c0, 0xc08d, 0xf2ff, 0xc08d, 0x21, 0 + .dw 0xf340, 0xc08d, 0xf37f, 0xc08d, 0x21, 0 + .dw 0xf3c0, 0xc08d, 0xf3ff, 0xc08d, 0x21, 0 + .dw 0xf440, 0xc08d, 0xf47f, 0xc08d, 0x21, 0 + .dw 0xf4c0, 0xc08d, 0xf4ff, 0xc08d, 0x21, 0 + .dw 0xf540, 0xc08d, 0xf57f, 0xc08d, 0x21, 0 + .dw 0xf5c0, 0xc08d, 0xf5ff, 0xc08d, 0x21, 0 + .dw 0xf640, 0xc08d, 0xf67f, 0xc08d, 0x21, 0 + .dw 0xf6c0, 0xc08d, 0xf6ff, 0xc08d, 0x21, 0 + .dw 0xf740, 0xc08d, 0xf77f, 0xc08d, 0x21, 0 + .dw 0xf7c0, 0xc08d, 0xf7ff, 0xc08d, 0x21, 0 + .dw 0xf840, 0xc08d, 0xf87f, 0xc08d, 0x21, 0 + .dw 0xf8c0, 0xc08d, 0xf8ff, 0xc08d, 0x21, 0 + .dw 0xf940, 0xc08d, 0xf97f, 0xc08d, 0x21, 0 + .dw 0xf9c0, 0xc08d, 0xffff, 0xc08d, 0x21, 0 + .dw 0x0040, 0xc08e, 0x007f, 0xc08e, 0x21, 0 + .dw 0x00c0, 0xc08e, 0x00ff, 0xc08e, 0x21, 0 + .dw 0x0140, 0xc08e, 0x017f, 0xc08e, 0x21, 0 + .dw 0x01c0, 0xc08e, 0x01ff, 0xc08e, 0x21, 0 + .dw 0x0240, 0xc08e, 0x027f, 0xc08e, 0x21, 0 + .dw 0x02c0, 0xc08e, 0x02ff, 0xc08e, 0x21, 0 + .dw 0x0340, 0xc08e, 0x037f, 0xc08e, 0x21, 0 + .dw 0x03c0, 0xc08e, 0x03ff, 0xc08e, 0x21, 0 + .dw 0x0440, 0xc08e, 0x047f, 0xc08e, 0x21, 0 + .dw 0x04c0, 0xc08e, 0x04ff, 0xc08e, 0x21, 0 + .dw 0x0540, 0xc08e, 0x057f, 0xc08e, 0x21, 0 + .dw 0x05c0, 0xc08e, 0x05ff, 0xc08e, 0x21, 0 + .dw 0x0640, 0xc08e, 0x067f, 0xc08e, 0x21, 0 + .dw 0x06c0, 0xc08e, 0x06ff, 0xc08e, 0x21, 0 + .dw 0x0740, 0xc08e, 0x077f, 0xc08e, 0x21, 0 + .dw 0x07c0, 0xc08e, 0x07ff, 0xc08e, 0x21, 0 + .dw 0x0840, 0xc08e, 0x087f, 0xc08e, 0x21, 0 + .dw 0x08c0, 0xc08e, 0x08ff, 0xc08e, 0x21, 0 + .dw 0x0940, 0xc08e, 0x097f, 0xc08e, 0x21, 0 + .dw 0x09c0, 0xc08e, 0x09ff, 0xc08e, 0x21, 0 + .dw 0x0a40, 0xc08e, 0x0a7f, 0xc08e, 0x21, 0 + .dw 0x0ac0, 0xc08e, 0x0aff, 0xc08e, 0x21, 0 + .dw 0x0b40, 0xc08e, 0x0b7f, 0xc08e, 0x21, 0 + .dw 0x0bc0, 0xc08e, 0x0bff, 0xc08e, 0x21, 0 + .dw 0x0c40, 0xc08e, 0x0c7f, 0xc08e, 0x21, 0 + .dw 0x0cc0, 0xc08e, 0x0cff, 0xc08e, 0x21, 0 + .dw 0x0d40, 0xc08e, 0x0d7f, 0xc08e, 0x21, 0 + .dw 0x0dc0, 0xc08e, 0x0dff, 0xc08e, 0x21, 0 + .dw 0x0e40, 0xc08e, 0x0e7f, 0xc08e, 0x21, 0 + .dw 0x0ec0, 0xc08e, 0x0eff, 0xc08e, 0x21, 0 + .dw 0x0f40, 0xc08e, 0x0f7f, 0xc08e, 0x21, 0 + .dw 0x0fc0, 0xc08e, 0x0fff, 0xc08e, 0x21, 0 + .dw 0x1040, 0xc08e, 0x107f, 0xc08e, 0x21, 0 + .dw 0x10c0, 0xc08e, 0x10ff, 0xc08e, 0x21, 0 + .dw 0x1140, 0xc08e, 0x117f, 0xc08e, 0x21, 0 + .dw 0x11c0, 0xc08e, 0x11ff, 0xc08e, 0x21, 0 + .dw 0x1240, 0xc08e, 0x127f, 0xc08e, 0x21, 0 + .dw 0x12c0, 0xc08e, 0x12ff, 0xc08e, 0x21, 0 + .dw 0x1340, 0xc08e, 0x137f, 0xc08e, 0x21, 0 + .dw 0x13c0, 0xc08e, 0x13ff, 0xc08e, 0x21, 0 + .dw 0x1440, 0xc08e, 0x147f, 0xc08e, 0x21, 0 + .dw 0x14c0, 0xc08e, 0x14ff, 0xc08e, 0x21, 0 + .dw 0x1540, 0xc08e, 0x157f, 0xc08e, 0x21, 0 + .dw 0x15c0, 0xc08e, 0x15ff, 0xc08e, 0x21, 0 + .dw 0x1640, 0xc08e, 0x167f, 0xc08e, 0x21, 0 + .dw 0x16c0, 0xc08e, 0x16ff, 0xc08e, 0x21, 0 + .dw 0x1740, 0xc08e, 0x177f, 0xc08e, 0x21, 0 + .dw 0x17c0, 0xc08e, 0x17ff, 0xc08e, 0x21, 0 + .dw 0x1840, 0xc08e, 0x187f, 0xc08e, 0x21, 0 + .dw 0x18c0, 0xc08e, 0x18ff, 0xc08e, 0x21, 0 + .dw 0x1940, 0xc08e, 0x197f, 0xc08e, 0x21, 0 + .dw 0x19c0, 0xc08e, 0x1fff, 0xc08e, 0x21, 0 + .dw 0x2040, 0xc08e, 0x207f, 0xc08e, 0x21, 0 + .dw 0x20c0, 0xc08e, 0x20ff, 0xc08e, 0x21, 0 + .dw 0x2140, 0xc08e, 0x217f, 0xc08e, 0x21, 0 + .dw 0x21c0, 0xc08e, 0x21ff, 0xc08e, 0x21, 0 + .dw 0x2240, 0xc08e, 0x227f, 0xc08e, 0x21, 0 + .dw 0x22c0, 0xc08e, 0x22ff, 0xc08e, 0x21, 0 + .dw 0x2340, 0xc08e, 0x237f, 0xc08e, 0x21, 0 + .dw 0x23c0, 0xc08e, 0x23ff, 0xc08e, 0x21, 0 + .dw 0x2440, 0xc08e, 0x247f, 0xc08e, 0x21, 0 + .dw 0x24c0, 0xc08e, 0x24ff, 0xc08e, 0x21, 0 + .dw 0x2540, 0xc08e, 0x257f, 0xc08e, 0x21, 0 + .dw 0x25c0, 0xc08e, 0x25ff, 0xc08e, 0x21, 0 + .dw 0x2640, 0xc08e, 0x267f, 0xc08e, 0x21, 0 + .dw 0x26c0, 0xc08e, 0x26ff, 0xc08e, 0x21, 0 + .dw 0x2740, 0xc08e, 0x277f, 0xc08e, 0x21, 0 + .dw 0x27c0, 0xc08e, 0x27ff, 0xc08e, 0x21, 0 + .dw 0x2840, 0xc08e, 0x287f, 0xc08e, 0x21, 0 + .dw 0x28c0, 0xc08e, 0x28ff, 0xc08e, 0x21, 0 + .dw 0x2940, 0xc08e, 0x297f, 0xc08e, 0x21, 0 + .dw 0x29c0, 0xc08e, 0x29ff, 0xc08e, 0x21, 0 + .dw 0x2a40, 0xc08e, 0x2a7f, 0xc08e, 0x21, 0 + .dw 0x2ac0, 0xc08e, 0x2aff, 0xc08e, 0x21, 0 + .dw 0x2b40, 0xc08e, 0x2b7f, 0xc08e, 0x21, 0 + .dw 0x2bc0, 0xc08e, 0x2bff, 0xc08e, 0x21, 0 + .dw 0x2c40, 0xc08e, 0x2c7f, 0xc08e, 0x21, 0 + .dw 0x2cc0, 0xc08e, 0x2cff, 0xc08e, 0x21, 0 + .dw 0x2d40, 0xc08e, 0x2d7f, 0xc08e, 0x21, 0 + .dw 0x2dc0, 0xc08e, 0x2dff, 0xc08e, 0x21, 0 + .dw 0x2e40, 0xc08e, 0x2e7f, 0xc08e, 0x21, 0 + .dw 0x2ec0, 0xc08e, 0x2eff, 0xc08e, 0x21, 0 + .dw 0x2f40, 0xc08e, 0x2f7f, 0xc08e, 0x21, 0 + .dw 0x2fc0, 0xc08e, 0x2fff, 0xc08e, 0x21, 0 + .dw 0x3040, 0xc08e, 0x307f, 0xc08e, 0x21, 0 + .dw 0x30c0, 0xc08e, 0x30ff, 0xc08e, 0x21, 0 + .dw 0x3140, 0xc08e, 0x317f, 0xc08e, 0x21, 0 + .dw 0x31c0, 0xc08e, 0x31ff, 0xc08e, 0x21, 0 + .dw 0x3240, 0xc08e, 0x327f, 0xc08e, 0x21, 0 + .dw 0x32c0, 0xc08e, 0x32ff, 0xc08e, 0x21, 0 + .dw 0x3340, 0xc08e, 0x337f, 0xc08e, 0x21, 0 + .dw 0x33c0, 0xc08e, 0x33ff, 0xc08e, 0x21, 0 + .dw 0x3440, 0xc08e, 0x347f, 0xc08e, 0x21, 0 + .dw 0x34c0, 0xc08e, 0x34ff, 0xc08e, 0x21, 0 + .dw 0x3540, 0xc08e, 0x357f, 0xc08e, 0x21, 0 + .dw 0x35c0, 0xc08e, 0x35ff, 0xc08e, 0x21, 0 + .dw 0x3640, 0xc08e, 0x367f, 0xc08e, 0x21, 0 + .dw 0x36c0, 0xc08e, 0x36ff, 0xc08e, 0x21, 0 + .dw 0x3740, 0xc08e, 0x377f, 0xc08e, 0x21, 0 + .dw 0x37c0, 0xc08e, 0x37ff, 0xc08e, 0x21, 0 + .dw 0x3840, 0xc08e, 0x387f, 0xc08e, 0x21, 0 + .dw 0x38c0, 0xc08e, 0x38ff, 0xc08e, 0x21, 0 + .dw 0x3940, 0xc08e, 0x397f, 0xc08e, 0x21, 0 + .dw 0x39c0, 0xc08e, 0x3fff, 0xc08e, 0x21, 0 + .dw 0x4040, 0xc08e, 0x407f, 0xc08e, 0x21, 0 + .dw 0x40c0, 0xc08e, 0x40ff, 0xc08e, 0x21, 0 + .dw 0x4140, 0xc08e, 0x417f, 0xc08e, 0x21, 0 + .dw 0x41c0, 0xc08e, 0x41ff, 0xc08e, 0x21, 0 + .dw 0x4240, 0xc08e, 0x427f, 0xc08e, 0x21, 0 + .dw 0x42c0, 0xc08e, 0x42ff, 0xc08e, 0x21, 0 + .dw 0x4340, 0xc08e, 0x437f, 0xc08e, 0x21, 0 + .dw 0x43c0, 0xc08e, 0x43ff, 0xc08e, 0x21, 0 + .dw 0x4440, 0xc08e, 0x447f, 0xc08e, 0x21, 0 + .dw 0x44c0, 0xc08e, 0x44ff, 0xc08e, 0x21, 0 + .dw 0x4540, 0xc08e, 0x457f, 0xc08e, 0x21, 0 + .dw 0x45c0, 0xc08e, 0x45ff, 0xc08e, 0x21, 0 + .dw 0x4640, 0xc08e, 0x467f, 0xc08e, 0x21, 0 + .dw 0x46c0, 0xc08e, 0x46ff, 0xc08e, 0x21, 0 + .dw 0x4740, 0xc08e, 0x477f, 0xc08e, 0x21, 0 + .dw 0x47c0, 0xc08e, 0x47ff, 0xc08e, 0x21, 0 + .dw 0x4840, 0xc08e, 0x487f, 0xc08e, 0x21, 0 + .dw 0x48c0, 0xc08e, 0x48ff, 0xc08e, 0x21, 0 + .dw 0x4940, 0xc08e, 0x497f, 0xc08e, 0x21, 0 + .dw 0x49c0, 0xc08e, 0x49ff, 0xc08e, 0x21, 0 + .dw 0x4a40, 0xc08e, 0x4a7f, 0xc08e, 0x21, 0 + .dw 0x4ac0, 0xc08e, 0x4aff, 0xc08e, 0x21, 0 + .dw 0x4b40, 0xc08e, 0x4b7f, 0xc08e, 0x21, 0 + .dw 0x4bc0, 0xc08e, 0x4bff, 0xc08e, 0x21, 0 + .dw 0x4c40, 0xc08e, 0x4c7f, 0xc08e, 0x21, 0 + .dw 0x4cc0, 0xc08e, 0x4cff, 0xc08e, 0x21, 0 + .dw 0x4d40, 0xc08e, 0x4d7f, 0xc08e, 0x21, 0 + .dw 0x4dc0, 0xc08e, 0x4dff, 0xc08e, 0x21, 0 + .dw 0x4e40, 0xc08e, 0x4e7f, 0xc08e, 0x21, 0 + .dw 0x4ec0, 0xc08e, 0x4eff, 0xc08e, 0x21, 0 + .dw 0x4f40, 0xc08e, 0x4f7f, 0xc08e, 0x21, 0 + .dw 0x4fc0, 0xc08e, 0x4fff, 0xc08e, 0x21, 0 + .dw 0x5040, 0xc08e, 0x507f, 0xc08e, 0x21, 0 + .dw 0x50c0, 0xc08e, 0x50ff, 0xc08e, 0x21, 0 + .dw 0x5140, 0xc08e, 0x517f, 0xc08e, 0x21, 0 + .dw 0x51c0, 0xc08e, 0x51ff, 0xc08e, 0x21, 0 + .dw 0x5240, 0xc08e, 0x527f, 0xc08e, 0x21, 0 + .dw 0x52c0, 0xc08e, 0x52ff, 0xc08e, 0x21, 0 + .dw 0x5340, 0xc08e, 0x537f, 0xc08e, 0x21, 0 + .dw 0x53c0, 0xc08e, 0x53ff, 0xc08e, 0x21, 0 + .dw 0x5440, 0xc08e, 0x547f, 0xc08e, 0x21, 0 + .dw 0x54c0, 0xc08e, 0x54ff, 0xc08e, 0x21, 0 + .dw 0x5540, 0xc08e, 0x557f, 0xc08e, 0x21, 0 + .dw 0x55c0, 0xc08e, 0x55ff, 0xc08e, 0x21, 0 + .dw 0x5640, 0xc08e, 0x567f, 0xc08e, 0x21, 0 + .dw 0x56c0, 0xc08e, 0x56ff, 0xc08e, 0x21, 0 + .dw 0x5740, 0xc08e, 0x577f, 0xc08e, 0x21, 0 + .dw 0x57c0, 0xc08e, 0x57ff, 0xc08e, 0x21, 0 + .dw 0x5840, 0xc08e, 0x587f, 0xc08e, 0x21, 0 + .dw 0x58c0, 0xc08e, 0x58ff, 0xc08e, 0x21, 0 + .dw 0x5940, 0xc08e, 0x597f, 0xc08e, 0x21, 0 + .dw 0x59c0, 0xc08e, 0x5fff, 0xc08e, 0x21, 0 + .dw 0x6040, 0xc08e, 0x607f, 0xc08e, 0x21, 0 + .dw 0x60c0, 0xc08e, 0x60ff, 0xc08e, 0x21, 0 + .dw 0x6140, 0xc08e, 0x617f, 0xc08e, 0x21, 0 + .dw 0x61c0, 0xc08e, 0x61ff, 0xc08e, 0x21, 0 + .dw 0x6240, 0xc08e, 0x627f, 0xc08e, 0x21, 0 + .dw 0x62c0, 0xc08e, 0x62ff, 0xc08e, 0x21, 0 + .dw 0x6340, 0xc08e, 0x637f, 0xc08e, 0x21, 0 + .dw 0x63c0, 0xc08e, 0x63ff, 0xc08e, 0x21, 0 + .dw 0x6440, 0xc08e, 0x647f, 0xc08e, 0x21, 0 + .dw 0x64c0, 0xc08e, 0x64ff, 0xc08e, 0x21, 0 + .dw 0x6540, 0xc08e, 0x657f, 0xc08e, 0x21, 0 + .dw 0x65c0, 0xc08e, 0x65ff, 0xc08e, 0x21, 0 + .dw 0x6640, 0xc08e, 0x667f, 0xc08e, 0x21, 0 + .dw 0x66c0, 0xc08e, 0x66ff, 0xc08e, 0x21, 0 + .dw 0x6740, 0xc08e, 0x677f, 0xc08e, 0x21, 0 + .dw 0x67c0, 0xc08e, 0x67ff, 0xc08e, 0x21, 0 + .dw 0x6840, 0xc08e, 0x687f, 0xc08e, 0x21, 0 + .dw 0x68c0, 0xc08e, 0x68ff, 0xc08e, 0x21, 0 + .dw 0x6940, 0xc08e, 0x697f, 0xc08e, 0x21, 0 + .dw 0x69c0, 0xc08e, 0x69ff, 0xc08e, 0x21, 0 + .dw 0x6a40, 0xc08e, 0x6a7f, 0xc08e, 0x21, 0 + .dw 0x6ac0, 0xc08e, 0x6aff, 0xc08e, 0x21, 0 + .dw 0x6b40, 0xc08e, 0x6b7f, 0xc08e, 0x21, 0 + .dw 0x6bc0, 0xc08e, 0x6bff, 0xc08e, 0x21, 0 + .dw 0x6c40, 0xc08e, 0x6c7f, 0xc08e, 0x21, 0 + .dw 0x6cc0, 0xc08e, 0x6cff, 0xc08e, 0x21, 0 + .dw 0x6d40, 0xc08e, 0x6d7f, 0xc08e, 0x21, 0 + .dw 0x6dc0, 0xc08e, 0x6dff, 0xc08e, 0x21, 0 + .dw 0x6e40, 0xc08e, 0x6e7f, 0xc08e, 0x21, 0 + .dw 0x6ec0, 0xc08e, 0x6eff, 0xc08e, 0x21, 0 + .dw 0x6f40, 0xc08e, 0x6f7f, 0xc08e, 0x21, 0 + .dw 0x6fc0, 0xc08e, 0x6fff, 0xc08e, 0x21, 0 + .dw 0x7040, 0xc08e, 0x707f, 0xc08e, 0x21, 0 + .dw 0x70c0, 0xc08e, 0x70ff, 0xc08e, 0x21, 0 + .dw 0x7140, 0xc08e, 0x717f, 0xc08e, 0x21, 0 + .dw 0x71c0, 0xc08e, 0x71ff, 0xc08e, 0x21, 0 + .dw 0x7240, 0xc08e, 0x727f, 0xc08e, 0x21, 0 + .dw 0x72c0, 0xc08e, 0x72ff, 0xc08e, 0x21, 0 + .dw 0x7340, 0xc08e, 0x737f, 0xc08e, 0x21, 0 + .dw 0x73c0, 0xc08e, 0x73ff, 0xc08e, 0x21, 0 + .dw 0x7440, 0xc08e, 0x747f, 0xc08e, 0x21, 0 + .dw 0x74c0, 0xc08e, 0x74ff, 0xc08e, 0x21, 0 + .dw 0x7540, 0xc08e, 0x757f, 0xc08e, 0x21, 0 + .dw 0x75c0, 0xc08e, 0x75ff, 0xc08e, 0x21, 0 + .dw 0x7640, 0xc08e, 0x767f, 0xc08e, 0x21, 0 + .dw 0x76c0, 0xc08e, 0x76ff, 0xc08e, 0x21, 0 + .dw 0x7740, 0xc08e, 0x777f, 0xc08e, 0x21, 0 + .dw 0x77c0, 0xc08e, 0x77ff, 0xc08e, 0x21, 0 + .dw 0x7840, 0xc08e, 0x787f, 0xc08e, 0x21, 0 + .dw 0x78c0, 0xc08e, 0x78ff, 0xc08e, 0x21, 0 + .dw 0x7940, 0xc08e, 0x797f, 0xc08e, 0x21, 0 + .dw 0x79c0, 0xc08e, 0x7fff, 0xc08e, 0x21, 0 + .dw 0x8040, 0xc08e, 0x807f, 0xc08e, 0x21, 0 + .dw 0x80c0, 0xc08e, 0x80ff, 0xc08e, 0x21, 0 + .dw 0x8140, 0xc08e, 0x817f, 0xc08e, 0x21, 0 + .dw 0x81c0, 0xc08e, 0x81ff, 0xc08e, 0x21, 0 + .dw 0x8240, 0xc08e, 0x827f, 0xc08e, 0x21, 0 + .dw 0x82c0, 0xc08e, 0x82ff, 0xc08e, 0x21, 0 + .dw 0x8340, 0xc08e, 0x837f, 0xc08e, 0x21, 0 + .dw 0x83c0, 0xc08e, 0x83ff, 0xc08e, 0x21, 0 + .dw 0x8440, 0xc08e, 0x847f, 0xc08e, 0x21, 0 + .dw 0x84c0, 0xc08e, 0x84ff, 0xc08e, 0x21, 0 + .dw 0x8540, 0xc08e, 0x857f, 0xc08e, 0x21, 0 + .dw 0x85c0, 0xc08e, 0x85ff, 0xc08e, 0x21, 0 + .dw 0x8640, 0xc08e, 0x867f, 0xc08e, 0x21, 0 + .dw 0x86c0, 0xc08e, 0x86ff, 0xc08e, 0x21, 0 + .dw 0x8740, 0xc08e, 0x877f, 0xc08e, 0x21, 0 + .dw 0x87c0, 0xc08e, 0x87ff, 0xc08e, 0x21, 0 + .dw 0x8840, 0xc08e, 0x887f, 0xc08e, 0x21, 0 + .dw 0x88c0, 0xc08e, 0x88ff, 0xc08e, 0x21, 0 + .dw 0x8940, 0xc08e, 0x897f, 0xc08e, 0x21, 0 + .dw 0x89c0, 0xc08e, 0x89ff, 0xc08e, 0x21, 0 + .dw 0x8a40, 0xc08e, 0x8a7f, 0xc08e, 0x21, 0 + .dw 0x8ac0, 0xc08e, 0x8aff, 0xc08e, 0x21, 0 + .dw 0x8b40, 0xc08e, 0x8b7f, 0xc08e, 0x21, 0 + .dw 0x8bc0, 0xc08e, 0x8bff, 0xc08e, 0x21, 0 + .dw 0x8c40, 0xc08e, 0x8c7f, 0xc08e, 0x21, 0 + .dw 0x8cc0, 0xc08e, 0x8cff, 0xc08e, 0x21, 0 + .dw 0x8d40, 0xc08e, 0x8d7f, 0xc08e, 0x21, 0 + .dw 0x8dc0, 0xc08e, 0x8dff, 0xc08e, 0x21, 0 + .dw 0x8e40, 0xc08e, 0x8e7f, 0xc08e, 0x21, 0 + .dw 0x8ec0, 0xc08e, 0x8eff, 0xc08e, 0x21, 0 + .dw 0x8f40, 0xc08e, 0x8f7f, 0xc08e, 0x21, 0 + .dw 0x8fc0, 0xc08e, 0x8fff, 0xc08e, 0x21, 0 + .dw 0x9040, 0xc08e, 0x907f, 0xc08e, 0x21, 0 + .dw 0x90c0, 0xc08e, 0x90ff, 0xc08e, 0x21, 0 + .dw 0x9140, 0xc08e, 0x917f, 0xc08e, 0x21, 0 + .dw 0x91c0, 0xc08e, 0x91ff, 0xc08e, 0x21, 0 + .dw 0x9240, 0xc08e, 0x927f, 0xc08e, 0x21, 0 + .dw 0x92c0, 0xc08e, 0x92ff, 0xc08e, 0x21, 0 + .dw 0x9340, 0xc08e, 0x937f, 0xc08e, 0x21, 0 + .dw 0x93c0, 0xc08e, 0x93ff, 0xc08e, 0x21, 0 + .dw 0x9440, 0xc08e, 0x947f, 0xc08e, 0x21, 0 + .dw 0x94c0, 0xc08e, 0x94ff, 0xc08e, 0x21, 0 + .dw 0x9540, 0xc08e, 0x957f, 0xc08e, 0x21, 0 + .dw 0x95c0, 0xc08e, 0x95ff, 0xc08e, 0x21, 0 + .dw 0x9640, 0xc08e, 0x967f, 0xc08e, 0x21, 0 + .dw 0x96c0, 0xc08e, 0x96ff, 0xc08e, 0x21, 0 + .dw 0x9740, 0xc08e, 0x977f, 0xc08e, 0x21, 0 + .dw 0x97c0, 0xc08e, 0x97ff, 0xc08e, 0x21, 0 + .dw 0x9840, 0xc08e, 0x987f, 0xc08e, 0x21, 0 + .dw 0x98c0, 0xc08e, 0x98ff, 0xc08e, 0x21, 0 + .dw 0x9940, 0xc08e, 0x997f, 0xc08e, 0x21, 0 + .dw 0x99c0, 0xc08e, 0x9fff, 0xc08e, 0x21, 0 + .dw 0xa040, 0xc08e, 0xa07f, 0xc08e, 0x21, 0 + .dw 0xa0c0, 0xc08e, 0xa0ff, 0xc08e, 0x21, 0 + .dw 0xa140, 0xc08e, 0xa17f, 0xc08e, 0x21, 0 + .dw 0xa1c0, 0xc08e, 0xa1ff, 0xc08e, 0x21, 0 + .dw 0xa240, 0xc08e, 0xa27f, 0xc08e, 0x21, 0 + .dw 0xa2c0, 0xc08e, 0xa2ff, 0xc08e, 0x21, 0 + .dw 0xa340, 0xc08e, 0xa37f, 0xc08e, 0x21, 0 + .dw 0xa3c0, 0xc08e, 0xa3ff, 0xc08e, 0x21, 0 + .dw 0xa440, 0xc08e, 0xa47f, 0xc08e, 0x21, 0 + .dw 0xa4c0, 0xc08e, 0xa4ff, 0xc08e, 0x21, 0 + .dw 0xa540, 0xc08e, 0xa57f, 0xc08e, 0x21, 0 + .dw 0xa5c0, 0xc08e, 0xa5ff, 0xc08e, 0x21, 0 + .dw 0xa640, 0xc08e, 0xa67f, 0xc08e, 0x21, 0 + .dw 0xa6c0, 0xc08e, 0xa6ff, 0xc08e, 0x21, 0 + .dw 0xa740, 0xc08e, 0xa77f, 0xc08e, 0x21, 0 + .dw 0xa7c0, 0xc08e, 0xa7ff, 0xc08e, 0x21, 0 + .dw 0xa840, 0xc08e, 0xa87f, 0xc08e, 0x21, 0 + .dw 0xa8c0, 0xc08e, 0xa8ff, 0xc08e, 0x21, 0 + .dw 0xa940, 0xc08e, 0xa97f, 0xc08e, 0x21, 0 + .dw 0xa9c0, 0xc08e, 0xa9ff, 0xc08e, 0x21, 0 + .dw 0xaa40, 0xc08e, 0xaa7f, 0xc08e, 0x21, 0 + .dw 0xaac0, 0xc08e, 0xaaff, 0xc08e, 0x21, 0 + .dw 0xab40, 0xc08e, 0xab7f, 0xc08e, 0x21, 0 + .dw 0xabc0, 0xc08e, 0xabff, 0xc08e, 0x21, 0 + .dw 0xac40, 0xc08e, 0xac7f, 0xc08e, 0x21, 0 + .dw 0xacc0, 0xc08e, 0xacff, 0xc08e, 0x21, 0 + .dw 0xad40, 0xc08e, 0xad7f, 0xc08e, 0x21, 0 + .dw 0xadc0, 0xc08e, 0xadff, 0xc08e, 0x21, 0 + .dw 0xae40, 0xc08e, 0xae7f, 0xc08e, 0x21, 0 + .dw 0xaec0, 0xc08e, 0xaeff, 0xc08e, 0x21, 0 + .dw 0xaf40, 0xc08e, 0xaf7f, 0xc08e, 0x21, 0 + .dw 0xafc0, 0xc08e, 0xafff, 0xc08e, 0x21, 0 + .dw 0xb040, 0xc08e, 0xb07f, 0xc08e, 0x21, 0 + .dw 0xb0c0, 0xc08e, 0xb0ff, 0xc08e, 0x21, 0 + .dw 0xb140, 0xc08e, 0xb17f, 0xc08e, 0x21, 0 + .dw 0xb1c0, 0xc08e, 0xb1ff, 0xc08e, 0x21, 0 + .dw 0xb240, 0xc08e, 0xb27f, 0xc08e, 0x21, 0 + .dw 0xb2c0, 0xc08e, 0xb2ff, 0xc08e, 0x21, 0 + .dw 0xb340, 0xc08e, 0xb37f, 0xc08e, 0x21, 0 + .dw 0xb3c0, 0xc08e, 0xb3ff, 0xc08e, 0x21, 0 + .dw 0xb440, 0xc08e, 0xb47f, 0xc08e, 0x21, 0 + .dw 0xb4c0, 0xc08e, 0xb4ff, 0xc08e, 0x21, 0 + .dw 0xb540, 0xc08e, 0xb57f, 0xc08e, 0x21, 0 + .dw 0xb5c0, 0xc08e, 0xb5ff, 0xc08e, 0x21, 0 + .dw 0xb640, 0xc08e, 0xb67f, 0xc08e, 0x21, 0 + .dw 0xb6c0, 0xc08e, 0xb6ff, 0xc08e, 0x21, 0 + .dw 0xb740, 0xc08e, 0xb77f, 0xc08e, 0x21, 0 + .dw 0xb7c0, 0xc08e, 0xb7ff, 0xc08e, 0x21, 0 + .dw 0xb840, 0xc08e, 0xb87f, 0xc08e, 0x21, 0 + .dw 0xb8c0, 0xc08e, 0xb8ff, 0xc08e, 0x21, 0 + .dw 0xb940, 0xc08e, 0xb97f, 0xc08e, 0x21, 0 + .dw 0xb9c0, 0xc08e, 0xbfff, 0xc08e, 0x21, 0 + .dw 0xc040, 0xc08e, 0xc07f, 0xc08e, 0x21, 0 + .dw 0xc0c0, 0xc08e, 0xc0ff, 0xc08e, 0x21, 0 + .dw 0xc140, 0xc08e, 0xc17f, 0xc08e, 0x21, 0 + .dw 0xc1c0, 0xc08e, 0xc1ff, 0xc08e, 0x21, 0 + .dw 0xc240, 0xc08e, 0xc27f, 0xc08e, 0x21, 0 + .dw 0xc2c0, 0xc08e, 0xc2ff, 0xc08e, 0x21, 0 + .dw 0xc340, 0xc08e, 0xc37f, 0xc08e, 0x21, 0 + .dw 0xc3c0, 0xc08e, 0xc3ff, 0xc08e, 0x21, 0 + .dw 0xc440, 0xc08e, 0xc47f, 0xc08e, 0x21, 0 + .dw 0xc4c0, 0xc08e, 0xc4ff, 0xc08e, 0x21, 0 + .dw 0xc540, 0xc08e, 0xc57f, 0xc08e, 0x21, 0 + .dw 0xc5c0, 0xc08e, 0xc5ff, 0xc08e, 0x21, 0 + .dw 0xc640, 0xc08e, 0xc67f, 0xc08e, 0x21, 0 + .dw 0xc6c0, 0xc08e, 0xc6ff, 0xc08e, 0x21, 0 + .dw 0xc740, 0xc08e, 0xc77f, 0xc08e, 0x21, 0 + .dw 0xc7c0, 0xc08e, 0xc7ff, 0xc08e, 0x21, 0 + .dw 0xc840, 0xc08e, 0xc87f, 0xc08e, 0x21, 0 + .dw 0xc8c0, 0xc08e, 0xc8ff, 0xc08e, 0x21, 0 + .dw 0xc940, 0xc08e, 0xc97f, 0xc08e, 0x21, 0 + .dw 0xc9c0, 0xc08e, 0xc9ff, 0xc08e, 0x21, 0 + .dw 0xca40, 0xc08e, 0xca7f, 0xc08e, 0x21, 0 + .dw 0xcac0, 0xc08e, 0xcaff, 0xc08e, 0x21, 0 + .dw 0xcb40, 0xc08e, 0xcb7f, 0xc08e, 0x21, 0 + .dw 0xcbc0, 0xc08e, 0xcbff, 0xc08e, 0x21, 0 + .dw 0xcc40, 0xc08e, 0xcc7f, 0xc08e, 0x21, 0 + .dw 0xccc0, 0xc08e, 0xccff, 0xc08e, 0x21, 0 + .dw 0xcd40, 0xc08e, 0xcd7f, 0xc08e, 0x21, 0 + .dw 0xcdc0, 0xc08e, 0xcdff, 0xc08e, 0x21, 0 + .dw 0xce40, 0xc08e, 0xce7f, 0xc08e, 0x21, 0 + .dw 0xcec0, 0xc08e, 0xceff, 0xc08e, 0x21, 0 + .dw 0xcf40, 0xc08e, 0xcf7f, 0xc08e, 0x21, 0 + .dw 0xcfc0, 0xc08e, 0xcfff, 0xc08e, 0x21, 0 + .dw 0xd040, 0xc08e, 0xd07f, 0xc08e, 0x21, 0 + .dw 0xd0c0, 0xc08e, 0xd0ff, 0xc08e, 0x21, 0 + .dw 0xd140, 0xc08e, 0xd17f, 0xc08e, 0x21, 0 + .dw 0xd1c0, 0xc08e, 0xd1ff, 0xc08e, 0x21, 0 + .dw 0xd240, 0xc08e, 0xd27f, 0xc08e, 0x21, 0 + .dw 0xd2c0, 0xc08e, 0xd2ff, 0xc08e, 0x21, 0 + .dw 0xd340, 0xc08e, 0xd37f, 0xc08e, 0x21, 0 + .dw 0xd3c0, 0xc08e, 0xd3ff, 0xc08e, 0x21, 0 + .dw 0xd440, 0xc08e, 0xd47f, 0xc08e, 0x21, 0 + .dw 0xd4c0, 0xc08e, 0xd4ff, 0xc08e, 0x21, 0 + .dw 0xd540, 0xc08e, 0xd57f, 0xc08e, 0x21, 0 + .dw 0xd5c0, 0xc08e, 0xd5ff, 0xc08e, 0x21, 0 + .dw 0xd640, 0xc08e, 0xd67f, 0xc08e, 0x21, 0 + .dw 0xd6c0, 0xc08e, 0xd6ff, 0xc08e, 0x21, 0 + .dw 0xd740, 0xc08e, 0xd77f, 0xc08e, 0x21, 0 + .dw 0xd7c0, 0xc08e, 0xd7ff, 0xc08e, 0x21, 0 + .dw 0xd840, 0xc08e, 0xd87f, 0xc08e, 0x21, 0 + .dw 0xd8c0, 0xc08e, 0xd8ff, 0xc08e, 0x21, 0 + .dw 0xd940, 0xc08e, 0xd97f, 0xc08e, 0x21, 0 + .dw 0xd9c0, 0xc08e, 0xdfff, 0xc08e, 0x21, 0 + .dw 0xe040, 0xc08e, 0xe07f, 0xc08e, 0x21, 0 + .dw 0xe0c0, 0xc08e, 0xe0ff, 0xc08e, 0x21, 0 + .dw 0xe140, 0xc08e, 0xe17f, 0xc08e, 0x21, 0 + .dw 0xe1c0, 0xc08e, 0xe1ff, 0xc08e, 0x21, 0 + .dw 0xe240, 0xc08e, 0xe27f, 0xc08e, 0x21, 0 + .dw 0xe2c0, 0xc08e, 0xe2ff, 0xc08e, 0x21, 0 + .dw 0xe340, 0xc08e, 0xe37f, 0xc08e, 0x21, 0 + .dw 0xe3c0, 0xc08e, 0xe3ff, 0xc08e, 0x21, 0 + .dw 0xe440, 0xc08e, 0xe47f, 0xc08e, 0x21, 0 + .dw 0xe4c0, 0xc08e, 0xe4ff, 0xc08e, 0x21, 0 + .dw 0xe540, 0xc08e, 0xe57f, 0xc08e, 0x21, 0 + .dw 0xe5c0, 0xc08e, 0xe5ff, 0xc08e, 0x21, 0 + .dw 0xe640, 0xc08e, 0xe67f, 0xc08e, 0x21, 0 + .dw 0xe6c0, 0xc08e, 0xe6ff, 0xc08e, 0x21, 0 + .dw 0xe740, 0xc08e, 0xe77f, 0xc08e, 0x21, 0 + .dw 0xe7c0, 0xc08e, 0xe7ff, 0xc08e, 0x21, 0 + .dw 0xe840, 0xc08e, 0xe87f, 0xc08e, 0x21, 0 + .dw 0xe8c0, 0xc08e, 0xe8ff, 0xc08e, 0x21, 0 + .dw 0xe940, 0xc08e, 0xe97f, 0xc08e, 0x21, 0 + .dw 0xe9c0, 0xc08e, 0xe9ff, 0xc08e, 0x21, 0 + .dw 0xea40, 0xc08e, 0xea7f, 0xc08e, 0x21, 0 + .dw 0xeac0, 0xc08e, 0xeaff, 0xc08e, 0x21, 0 + .dw 0xeb40, 0xc08e, 0xeb7f, 0xc08e, 0x21, 0 + .dw 0xebc0, 0xc08e, 0xebff, 0xc08e, 0x21, 0 + .dw 0xec40, 0xc08e, 0xec7f, 0xc08e, 0x21, 0 + .dw 0xecc0, 0xc08e, 0xecff, 0xc08e, 0x21, 0 + .dw 0xed40, 0xc08e, 0xed7f, 0xc08e, 0x21, 0 + .dw 0xedc0, 0xc08e, 0xedff, 0xc08e, 0x21, 0 + .dw 0xee40, 0xc08e, 0xee7f, 0xc08e, 0x21, 0 + .dw 0xeec0, 0xc08e, 0xeeff, 0xc08e, 0x21, 0 + .dw 0xef40, 0xc08e, 0xef7f, 0xc08e, 0x21, 0 + .dw 0xefc0, 0xc08e, 0xefff, 0xc08e, 0x21, 0 + .dw 0xf040, 0xc08e, 0xf07f, 0xc08e, 0x21, 0 + .dw 0xf0c0, 0xc08e, 0xf0ff, 0xc08e, 0x21, 0 + .dw 0xf140, 0xc08e, 0xf17f, 0xc08e, 0x21, 0 + .dw 0xf1c0, 0xc08e, 0xf1ff, 0xc08e, 0x21, 0 + .dw 0xf240, 0xc08e, 0xf27f, 0xc08e, 0x21, 0 + .dw 0xf2c0, 0xc08e, 0xf2ff, 0xc08e, 0x21, 0 + .dw 0xf340, 0xc08e, 0xf37f, 0xc08e, 0x21, 0 + .dw 0xf3c0, 0xc08e, 0xf3ff, 0xc08e, 0x21, 0 + .dw 0xf440, 0xc08e, 0xf47f, 0xc08e, 0x21, 0 + .dw 0xf4c0, 0xc08e, 0xf4ff, 0xc08e, 0x21, 0 + .dw 0xf540, 0xc08e, 0xf57f, 0xc08e, 0x21, 0 + .dw 0xf5c0, 0xc08e, 0xf5ff, 0xc08e, 0x21, 0 + .dw 0xf640, 0xc08e, 0xf67f, 0xc08e, 0x21, 0 + .dw 0xf6c0, 0xc08e, 0xf6ff, 0xc08e, 0x21, 0 + .dw 0xf740, 0xc08e, 0xf77f, 0xc08e, 0x21, 0 + .dw 0xf7c0, 0xc08e, 0xf7ff, 0xc08e, 0x21, 0 + .dw 0xf840, 0xc08e, 0xf87f, 0xc08e, 0x21, 0 + .dw 0xf8c0, 0xc08e, 0xf8ff, 0xc08e, 0x21, 0 + .dw 0xf940, 0xc08e, 0xf97f, 0xc08e, 0x21, 0 + .dw 0xf9c0, 0xc08e, 0xffff, 0xc08e, 0x21, 0 + .dw 0x0040, 0xc08f, 0x007f, 0xc08f, 0x21, 0 + .dw 0x00c0, 0xc08f, 0x00ff, 0xc08f, 0x21, 0 + .dw 0x0140, 0xc08f, 0x017f, 0xc08f, 0x21, 0 + .dw 0x01c0, 0xc08f, 0x01ff, 0xc08f, 0x21, 0 + .dw 0x0240, 0xc08f, 0x027f, 0xc08f, 0x21, 0 + .dw 0x02c0, 0xc08f, 0x02ff, 0xc08f, 0x21, 0 + .dw 0x0340, 0xc08f, 0x037f, 0xc08f, 0x21, 0 + .dw 0x03c0, 0xc08f, 0x03ff, 0xc08f, 0x21, 0 + .dw 0x0440, 0xc08f, 0x047f, 0xc08f, 0x21, 0 + .dw 0x04c0, 0xc08f, 0x04ff, 0xc08f, 0x21, 0 + .dw 0x0540, 0xc08f, 0x057f, 0xc08f, 0x21, 0 + .dw 0x05c0, 0xc08f, 0x05ff, 0xc08f, 0x21, 0 + .dw 0x0640, 0xc08f, 0x067f, 0xc08f, 0x21, 0 + .dw 0x06c0, 0xc08f, 0x06ff, 0xc08f, 0x21, 0 + .dw 0x0740, 0xc08f, 0x077f, 0xc08f, 0x21, 0 + .dw 0x07c0, 0xc08f, 0x07ff, 0xc08f, 0x21, 0 + .dw 0x0840, 0xc08f, 0x087f, 0xc08f, 0x21, 0 + .dw 0x08c0, 0xc08f, 0x08ff, 0xc08f, 0x21, 0 + .dw 0x0940, 0xc08f, 0x097f, 0xc08f, 0x21, 0 + .dw 0x09c0, 0xc08f, 0x09ff, 0xc08f, 0x21, 0 + .dw 0x0a40, 0xc08f, 0x0a7f, 0xc08f, 0x21, 0 + .dw 0x0ac0, 0xc08f, 0x0aff, 0xc08f, 0x21, 0 + .dw 0x0b40, 0xc08f, 0x0b7f, 0xc08f, 0x21, 0 + .dw 0x0bc0, 0xc08f, 0x0bff, 0xc08f, 0x21, 0 + .dw 0x0c40, 0xc08f, 0x0c7f, 0xc08f, 0x21, 0 + .dw 0x0cc0, 0xc08f, 0x0cff, 0xc08f, 0x21, 0 + .dw 0x0d40, 0xc08f, 0x0d7f, 0xc08f, 0x21, 0 + .dw 0x0dc0, 0xc08f, 0x0dff, 0xc08f, 0x21, 0 + .dw 0x0e40, 0xc08f, 0x0e7f, 0xc08f, 0x21, 0 + .dw 0x0ec0, 0xc08f, 0x0eff, 0xc08f, 0x21, 0 + .dw 0x0f40, 0xc08f, 0x0f7f, 0xc08f, 0x21, 0 + .dw 0x0fc0, 0xc08f, 0x0fff, 0xc08f, 0x21, 0 + .dw 0x1040, 0xc08f, 0x107f, 0xc08f, 0x21, 0 + .dw 0x10c0, 0xc08f, 0x10ff, 0xc08f, 0x21, 0 + .dw 0x1140, 0xc08f, 0x117f, 0xc08f, 0x21, 0 + .dw 0x11c0, 0xc08f, 0x11ff, 0xc08f, 0x21, 0 + .dw 0x1240, 0xc08f, 0x127f, 0xc08f, 0x21, 0 + .dw 0x12c0, 0xc08f, 0x12ff, 0xc08f, 0x21, 0 + .dw 0x1340, 0xc08f, 0x137f, 0xc08f, 0x21, 0 + .dw 0x13c0, 0xc08f, 0x13ff, 0xc08f, 0x21, 0 + .dw 0x1440, 0xc08f, 0x147f, 0xc08f, 0x21, 0 + .dw 0x14c0, 0xc08f, 0x14ff, 0xc08f, 0x21, 0 + .dw 0x1540, 0xc08f, 0x157f, 0xc08f, 0x21, 0 + .dw 0x15c0, 0xc08f, 0x15ff, 0xc08f, 0x21, 0 + .dw 0x1640, 0xc08f, 0x167f, 0xc08f, 0x21, 0 + .dw 0x16c0, 0xc08f, 0x16ff, 0xc08f, 0x21, 0 + .dw 0x1740, 0xc08f, 0x177f, 0xc08f, 0x21, 0 + .dw 0x17c0, 0xc08f, 0x17ff, 0xc08f, 0x21, 0 + .dw 0x1840, 0xc08f, 0x187f, 0xc08f, 0x21, 0 + .dw 0x18c0, 0xc08f, 0x18ff, 0xc08f, 0x21, 0 + .dw 0x1940, 0xc08f, 0x197f, 0xc08f, 0x21, 0 + .dw 0x19c0, 0xc08f, 0x1fff, 0xc08f, 0x21, 0 + .dw 0x2040, 0xc08f, 0x207f, 0xc08f, 0x21, 0 + .dw 0x20c0, 0xc08f, 0x20ff, 0xc08f, 0x21, 0 + .dw 0x2140, 0xc08f, 0x217f, 0xc08f, 0x21, 0 + .dw 0x21c0, 0xc08f, 0x21ff, 0xc08f, 0x21, 0 + .dw 0x2240, 0xc08f, 0x227f, 0xc08f, 0x21, 0 + .dw 0x22c0, 0xc08f, 0x22ff, 0xc08f, 0x21, 0 + .dw 0x2340, 0xc08f, 0x237f, 0xc08f, 0x21, 0 + .dw 0x23c0, 0xc08f, 0x23ff, 0xc08f, 0x21, 0 + .dw 0x2440, 0xc08f, 0x247f, 0xc08f, 0x21, 0 + .dw 0x24c0, 0xc08f, 0x24ff, 0xc08f, 0x21, 0 + .dw 0x2540, 0xc08f, 0x257f, 0xc08f, 0x21, 0 + .dw 0x25c0, 0xc08f, 0x25ff, 0xc08f, 0x21, 0 + .dw 0x2640, 0xc08f, 0x267f, 0xc08f, 0x21, 0 + .dw 0x26c0, 0xc08f, 0x26ff, 0xc08f, 0x21, 0 + .dw 0x2740, 0xc08f, 0x277f, 0xc08f, 0x21, 0 + .dw 0x27c0, 0xc08f, 0x27ff, 0xc08f, 0x21, 0 + .dw 0x2840, 0xc08f, 0x287f, 0xc08f, 0x21, 0 + .dw 0x28c0, 0xc08f, 0x28ff, 0xc08f, 0x21, 0 + .dw 0x2940, 0xc08f, 0x297f, 0xc08f, 0x21, 0 + .dw 0x29c0, 0xc08f, 0x29ff, 0xc08f, 0x21, 0 + .dw 0x2a40, 0xc08f, 0x2a7f, 0xc08f, 0x21, 0 + .dw 0x2ac0, 0xc08f, 0x2aff, 0xc08f, 0x21, 0 + .dw 0x2b40, 0xc08f, 0x2b7f, 0xc08f, 0x21, 0 + .dw 0x2bc0, 0xc08f, 0x2bff, 0xc08f, 0x21, 0 + .dw 0x2c40, 0xc08f, 0x2c7f, 0xc08f, 0x21, 0 + .dw 0x2cc0, 0xc08f, 0x2cff, 0xc08f, 0x21, 0 + .dw 0x2d40, 0xc08f, 0x2d7f, 0xc08f, 0x21, 0 + .dw 0x2dc0, 0xc08f, 0x2dff, 0xc08f, 0x21, 0 + .dw 0x2e40, 0xc08f, 0x2e7f, 0xc08f, 0x21, 0 + .dw 0x2ec0, 0xc08f, 0x2eff, 0xc08f, 0x21, 0 + .dw 0x2f40, 0xc08f, 0x2f7f, 0xc08f, 0x21, 0 + .dw 0x2fc0, 0xc08f, 0x2fff, 0xc08f, 0x21, 0 + .dw 0x3040, 0xc08f, 0x307f, 0xc08f, 0x21, 0 + .dw 0x30c0, 0xc08f, 0x30ff, 0xc08f, 0x21, 0 + .dw 0x3140, 0xc08f, 0x317f, 0xc08f, 0x21, 0 + .dw 0x31c0, 0xc08f, 0x31ff, 0xc08f, 0x21, 0 + .dw 0x3240, 0xc08f, 0x327f, 0xc08f, 0x21, 0 + .dw 0x32c0, 0xc08f, 0x32ff, 0xc08f, 0x21, 0 + .dw 0x3340, 0xc08f, 0x337f, 0xc08f, 0x21, 0 + .dw 0x33c0, 0xc08f, 0x33ff, 0xc08f, 0x21, 0 + .dw 0x3440, 0xc08f, 0x347f, 0xc08f, 0x21, 0 + .dw 0x34c0, 0xc08f, 0x34ff, 0xc08f, 0x21, 0 + .dw 0x3540, 0xc08f, 0x357f, 0xc08f, 0x21, 0 + .dw 0x35c0, 0xc08f, 0x35ff, 0xc08f, 0x21, 0 + .dw 0x3640, 0xc08f, 0x367f, 0xc08f, 0x21, 0 + .dw 0x36c0, 0xc08f, 0x36ff, 0xc08f, 0x21, 0 + .dw 0x3740, 0xc08f, 0x377f, 0xc08f, 0x21, 0 + .dw 0x37c0, 0xc08f, 0x37ff, 0xc08f, 0x21, 0 + .dw 0x3840, 0xc08f, 0x387f, 0xc08f, 0x21, 0 + .dw 0x38c0, 0xc08f, 0x38ff, 0xc08f, 0x21, 0 + .dw 0x3940, 0xc08f, 0x397f, 0xc08f, 0x21, 0 + .dw 0x39c0, 0xc08f, 0xffff, 0xc08f, 0x21, 0 + .dw 0x1a00, 0xc090, 0x1fff, 0xc090, 0x21, 0 + .dw 0x3a00, 0xc090, 0x3fff, 0xc090, 0x21, 0 + .dw 0x5a00, 0xc090, 0x5fff, 0xc090, 0x21, 0 + .dw 0x7a00, 0xc090, 0x7fff, 0xc090, 0x21, 0 + .dw 0x9a00, 0xc090, 0x9fff, 0xc090, 0x21, 0 + .dw 0xba00, 0xc090, 0xbfff, 0xc090, 0x21, 0 + .dw 0xda00, 0xc090, 0xdfff, 0xc090, 0x21, 0 + .dw 0xfa00, 0xc090, 0xffff, 0xc090, 0x21, 0 + .dw 0x1a00, 0xc091, 0x1fff, 0xc091, 0x21, 0 + .dw 0x3a00, 0xc091, 0x3fff, 0xc091, 0x21, 0 + .dw 0x5a00, 0xc091, 0x5fff, 0xc091, 0x21, 0 + .dw 0x7a00, 0xc091, 0x7fff, 0xc091, 0x21, 0 + .dw 0x9a00, 0xc091, 0x9fff, 0xc091, 0x21, 0 + .dw 0xba00, 0xc091, 0xbfff, 0xc091, 0x21, 0 + .dw 0xda00, 0xc091, 0xdfff, 0xc091, 0x21, 0 + .dw 0xfa00, 0xc091, 0xffff, 0xc091, 0x21, 0 + .dw 0x1a00, 0xc092, 0x1fff, 0xc092, 0x21, 0 + .dw 0x3a00, 0xc092, 0x3fff, 0xc092, 0x21, 0 + .dw 0x5a00, 0xc092, 0x5fff, 0xc092, 0x21, 0 + .dw 0x7a00, 0xc092, 0x7fff, 0xc092, 0x21, 0 + .dw 0x9a00, 0xc092, 0x9fff, 0xc092, 0x21, 0 + .dw 0xba00, 0xc092, 0xbfff, 0xc092, 0x21, 0 + .dw 0xda00, 0xc092, 0xdfff, 0xc092, 0x21, 0 + .dw 0xfa00, 0xc092, 0xffff, 0xc093, 0x21, 0 + .dw 0x1a00, 0xc094, 0x1fff, 0xc094, 0x21, 0 + .dw 0x3a00, 0xc094, 0x3fff, 0xc094, 0x21, 0 + .dw 0x5a00, 0xc094, 0x5fff, 0xc094, 0x21, 0 + .dw 0x7a00, 0xc094, 0x7fff, 0xc094, 0x21, 0 + .dw 0x9a00, 0xc094, 0x9fff, 0xc094, 0x21, 0 + .dw 0xba00, 0xc094, 0xbfff, 0xc094, 0x21, 0 + .dw 0xda00, 0xc094, 0xdfff, 0xc094, 0x21, 0 + .dw 0xfa00, 0xc094, 0xffff, 0xc094, 0x21, 0 + .dw 0x1a00, 0xc095, 0x1fff, 0xc095, 0x21, 0 + .dw 0x3a00, 0xc095, 0x3fff, 0xc095, 0x21, 0 + .dw 0x5a00, 0xc095, 0x5fff, 0xc095, 0x21, 0 + .dw 0x7a00, 0xc095, 0x7fff, 0xc095, 0x21, 0 + .dw 0x9a00, 0xc095, 0x9fff, 0xc095, 0x21, 0 + .dw 0xba00, 0xc095, 0xbfff, 0xc095, 0x21, 0 + .dw 0xda00, 0xc095, 0xdfff, 0xc095, 0x21, 0 + .dw 0xfa00, 0xc095, 0xffff, 0xc095, 0x21, 0 + .dw 0x1a00, 0xc096, 0x1fff, 0xc096, 0x21, 0 + .dw 0x3a00, 0xc096, 0x3fff, 0xc096, 0x21, 0 + .dw 0x5a00, 0xc096, 0x5fff, 0xc096, 0x21, 0 + .dw 0x7a00, 0xc096, 0x7fff, 0xc096, 0x21, 0 + .dw 0x9a00, 0xc096, 0x9fff, 0xc096, 0x21, 0 + .dw 0xba00, 0xc096, 0xbfff, 0xc096, 0x21, 0 + .dw 0xda00, 0xc096, 0xdfff, 0xc096, 0x21, 0 + .dw 0xfa00, 0xc096, 0xffff, 0xc096, 0x21, 0 + .dw 0x1a00, 0xc097, 0x1fff, 0xc097, 0x21, 0 + .dw 0x3a00, 0xc097, 0x1fff, 0xc098, 0x21, 0 + .dw 0x2040, 0xc098, 0x207f, 0xc098, 0x21, 0 + .dw 0x20c0, 0xc098, 0x20ff, 0xc098, 0x21, 0 + .dw 0x2140, 0xc098, 0x217f, 0xc098, 0x21, 0 + .dw 0x21c0, 0xc098, 0x21ff, 0xc098, 0x21, 0 + .dw 0x2240, 0xc098, 0x227f, 0xc098, 0x21, 0 + .dw 0x22c0, 0xc098, 0x22ff, 0xc098, 0x21, 0 + .dw 0x2340, 0xc098, 0x237f, 0xc098, 0x21, 0 + .dw 0x23c0, 0xc098, 0x23ff, 0xc098, 0x21, 0 + .dw 0x2440, 0xc098, 0x247f, 0xc098, 0x21, 0 + .dw 0x24c0, 0xc098, 0x24ff, 0xc098, 0x21, 0 + .dw 0x2540, 0xc098, 0x257f, 0xc098, 0x21, 0 + .dw 0x25c0, 0xc098, 0x25ff, 0xc098, 0x21, 0 + .dw 0x2640, 0xc098, 0x267f, 0xc098, 0x21, 0 + .dw 0x26c0, 0xc098, 0x26ff, 0xc098, 0x21, 0 + .dw 0x2740, 0xc098, 0x277f, 0xc098, 0x21, 0 + .dw 0x27c0, 0xc098, 0x27ff, 0xc098, 0x21, 0 + .dw 0x2840, 0xc098, 0x287f, 0xc098, 0x21, 0 + .dw 0x28c0, 0xc098, 0x28ff, 0xc098, 0x21, 0 + .dw 0x2940, 0xc098, 0x297f, 0xc098, 0x21, 0 + .dw 0x29c0, 0xc098, 0x29ff, 0xc098, 0x21, 0 + .dw 0x2a40, 0xc098, 0x2a7f, 0xc098, 0x21, 0 + .dw 0x2ac0, 0xc098, 0x2aff, 0xc098, 0x21, 0 + .dw 0x2b40, 0xc098, 0x2b7f, 0xc098, 0x21, 0 + .dw 0x2bc0, 0xc098, 0x2bff, 0xc098, 0x21, 0 + .dw 0x2c40, 0xc098, 0x2c7f, 0xc098, 0x21, 0 + .dw 0x2cc0, 0xc098, 0x2cff, 0xc098, 0x21, 0 + .dw 0x2d40, 0xc098, 0x2d7f, 0xc098, 0x21, 0 + .dw 0x2dc0, 0xc098, 0x2dff, 0xc098, 0x21, 0 + .dw 0x2e40, 0xc098, 0x2e7f, 0xc098, 0x21, 0 + .dw 0x2ec0, 0xc098, 0x2eff, 0xc098, 0x21, 0 + .dw 0x2f40, 0xc098, 0x2f7f, 0xc098, 0x21, 0 + .dw 0x2fc0, 0xc098, 0x2fff, 0xc098, 0x21, 0 + .dw 0x3040, 0xc098, 0x307f, 0xc098, 0x21, 0 + .dw 0x30c0, 0xc098, 0x30ff, 0xc098, 0x21, 0 + .dw 0x3140, 0xc098, 0x317f, 0xc098, 0x21, 0 + .dw 0x31c0, 0xc098, 0x31ff, 0xc098, 0x21, 0 + .dw 0x3240, 0xc098, 0x327f, 0xc098, 0x21, 0 + .dw 0x32c0, 0xc098, 0x32ff, 0xc098, 0x21, 0 + .dw 0x3340, 0xc098, 0x337f, 0xc098, 0x21, 0 + .dw 0x33c0, 0xc098, 0x33ff, 0xc098, 0x21, 0 + .dw 0x3440, 0xc098, 0x347f, 0xc098, 0x21, 0 + .dw 0x34c0, 0xc098, 0x34ff, 0xc098, 0x21, 0 + .dw 0x3540, 0xc098, 0x357f, 0xc098, 0x21, 0 + .dw 0x35c0, 0xc098, 0x35ff, 0xc098, 0x21, 0 + .dw 0x3640, 0xc098, 0x367f, 0xc098, 0x21, 0 + .dw 0x36c0, 0xc098, 0x36ff, 0xc098, 0x21, 0 + .dw 0x3740, 0xc098, 0x377f, 0xc098, 0x21, 0 + .dw 0x37c0, 0xc098, 0x37ff, 0xc098, 0x21, 0 + .dw 0x3840, 0xc098, 0x387f, 0xc098, 0x21, 0 + .dw 0x38c0, 0xc098, 0x38ff, 0xc098, 0x21, 0 + .dw 0x3940, 0xc098, 0x397f, 0xc098, 0x21, 0 + .dw 0x39c0, 0xc098, 0x5fff, 0xc098, 0x21, 0 + .dw 0x6040, 0xc098, 0x607f, 0xc098, 0x21, 0 + .dw 0x60c0, 0xc098, 0x60ff, 0xc098, 0x21, 0 + .dw 0x6140, 0xc098, 0x617f, 0xc098, 0x21, 0 + .dw 0x61c0, 0xc098, 0x61ff, 0xc098, 0x21, 0 + .dw 0x6240, 0xc098, 0x627f, 0xc098, 0x21, 0 + .dw 0x62c0, 0xc098, 0x62ff, 0xc098, 0x21, 0 + .dw 0x6340, 0xc098, 0x637f, 0xc098, 0x21, 0 + .dw 0x63c0, 0xc098, 0x63ff, 0xc098, 0x21, 0 + .dw 0x6440, 0xc098, 0x647f, 0xc098, 0x21, 0 + .dw 0x64c0, 0xc098, 0x64ff, 0xc098, 0x21, 0 + .dw 0x6540, 0xc098, 0x657f, 0xc098, 0x21, 0 + .dw 0x65c0, 0xc098, 0x65ff, 0xc098, 0x21, 0 + .dw 0x6640, 0xc098, 0x667f, 0xc098, 0x21, 0 + .dw 0x66c0, 0xc098, 0x66ff, 0xc098, 0x21, 0 + .dw 0x6740, 0xc098, 0x677f, 0xc098, 0x21, 0 + .dw 0x67c0, 0xc098, 0x67ff, 0xc098, 0x21, 0 + .dw 0x6840, 0xc098, 0x687f, 0xc098, 0x21, 0 + .dw 0x68c0, 0xc098, 0x68ff, 0xc098, 0x21, 0 + .dw 0x6940, 0xc098, 0x697f, 0xc098, 0x21, 0 + .dw 0x69c0, 0xc098, 0x69ff, 0xc098, 0x21, 0 + .dw 0x6a40, 0xc098, 0x6a7f, 0xc098, 0x21, 0 + .dw 0x6ac0, 0xc098, 0x6aff, 0xc098, 0x21, 0 + .dw 0x6b40, 0xc098, 0x6b7f, 0xc098, 0x21, 0 + .dw 0x6bc0, 0xc098, 0x6bff, 0xc098, 0x21, 0 + .dw 0x6c40, 0xc098, 0x6c7f, 0xc098, 0x21, 0 + .dw 0x6cc0, 0xc098, 0x6cff, 0xc098, 0x21, 0 + .dw 0x6d40, 0xc098, 0x6d7f, 0xc098, 0x21, 0 + .dw 0x6dc0, 0xc098, 0x6dff, 0xc098, 0x21, 0 + .dw 0x6e40, 0xc098, 0x6e7f, 0xc098, 0x21, 0 + .dw 0x6ec0, 0xc098, 0x6eff, 0xc098, 0x21, 0 + .dw 0x6f40, 0xc098, 0x6f7f, 0xc098, 0x21, 0 + .dw 0x6fc0, 0xc098, 0x6fff, 0xc098, 0x21, 0 + .dw 0x7040, 0xc098, 0x707f, 0xc098, 0x21, 0 + .dw 0x70c0, 0xc098, 0x70ff, 0xc098, 0x21, 0 + .dw 0x7140, 0xc098, 0x717f, 0xc098, 0x21, 0 + .dw 0x71c0, 0xc098, 0x71ff, 0xc098, 0x21, 0 + .dw 0x7240, 0xc098, 0x727f, 0xc098, 0x21, 0 + .dw 0x72c0, 0xc098, 0x72ff, 0xc098, 0x21, 0 + .dw 0x7340, 0xc098, 0x737f, 0xc098, 0x21, 0 + .dw 0x73c0, 0xc098, 0x73ff, 0xc098, 0x21, 0 + .dw 0x7440, 0xc098, 0x747f, 0xc098, 0x21, 0 + .dw 0x74c0, 0xc098, 0x74ff, 0xc098, 0x21, 0 + .dw 0x7540, 0xc098, 0x757f, 0xc098, 0x21, 0 + .dw 0x75c0, 0xc098, 0x75ff, 0xc098, 0x21, 0 + .dw 0x7640, 0xc098, 0x767f, 0xc098, 0x21, 0 + .dw 0x76c0, 0xc098, 0x76ff, 0xc098, 0x21, 0 + .dw 0x7740, 0xc098, 0x777f, 0xc098, 0x21, 0 + .dw 0x77c0, 0xc098, 0x77ff, 0xc098, 0x21, 0 + .dw 0x7840, 0xc098, 0x787f, 0xc098, 0x21, 0 + .dw 0x78c0, 0xc098, 0x78ff, 0xc098, 0x21, 0 + .dw 0x7940, 0xc098, 0x797f, 0xc098, 0x21, 0 + .dw 0x79c0, 0xc098, 0x9fff, 0xc098, 0x21, 0 + .dw 0xa040, 0xc098, 0xa07f, 0xc098, 0x21, 0 + .dw 0xa0c0, 0xc098, 0xa0ff, 0xc098, 0x21, 0 + .dw 0xa140, 0xc098, 0xa17f, 0xc098, 0x21, 0 + .dw 0xa1c0, 0xc098, 0xa1ff, 0xc098, 0x21, 0 + .dw 0xa240, 0xc098, 0xa27f, 0xc098, 0x21, 0 + .dw 0xa2c0, 0xc098, 0xa2ff, 0xc098, 0x21, 0 + .dw 0xa340, 0xc098, 0xa37f, 0xc098, 0x21, 0 + .dw 0xa3c0, 0xc098, 0xa3ff, 0xc098, 0x21, 0 + .dw 0xa440, 0xc098, 0xa47f, 0xc098, 0x21, 0 + .dw 0xa4c0, 0xc098, 0xa4ff, 0xc098, 0x21, 0 + .dw 0xa540, 0xc098, 0xa57f, 0xc098, 0x21, 0 + .dw 0xa5c0, 0xc098, 0xa5ff, 0xc098, 0x21, 0 + .dw 0xa640, 0xc098, 0xa67f, 0xc098, 0x21, 0 + .dw 0xa6c0, 0xc098, 0xa6ff, 0xc098, 0x21, 0 + .dw 0xa740, 0xc098, 0xa77f, 0xc098, 0x21, 0 + .dw 0xa7c0, 0xc098, 0xa7ff, 0xc098, 0x21, 0 + .dw 0xa840, 0xc098, 0xa87f, 0xc098, 0x21, 0 + .dw 0xa8c0, 0xc098, 0xa8ff, 0xc098, 0x21, 0 + .dw 0xa940, 0xc098, 0xa97f, 0xc098, 0x21, 0 + .dw 0xa9c0, 0xc098, 0xa9ff, 0xc098, 0x21, 0 + .dw 0xaa40, 0xc098, 0xaa7f, 0xc098, 0x21, 0 + .dw 0xaac0, 0xc098, 0xaaff, 0xc098, 0x21, 0 + .dw 0xab40, 0xc098, 0xab7f, 0xc098, 0x21, 0 + .dw 0xabc0, 0xc098, 0xabff, 0xc098, 0x21, 0 + .dw 0xac40, 0xc098, 0xac7f, 0xc098, 0x21, 0 + .dw 0xacc0, 0xc098, 0xacff, 0xc098, 0x21, 0 + .dw 0xad40, 0xc098, 0xad7f, 0xc098, 0x21, 0 + .dw 0xadc0, 0xc098, 0xadff, 0xc098, 0x21, 0 + .dw 0xae40, 0xc098, 0xae7f, 0xc098, 0x21, 0 + .dw 0xaec0, 0xc098, 0xaeff, 0xc098, 0x21, 0 + .dw 0xaf40, 0xc098, 0xaf7f, 0xc098, 0x21, 0 + .dw 0xafc0, 0xc098, 0xafff, 0xc098, 0x21, 0 + .dw 0xb040, 0xc098, 0xb07f, 0xc098, 0x21, 0 + .dw 0xb0c0, 0xc098, 0xb0ff, 0xc098, 0x21, 0 + .dw 0xb140, 0xc098, 0xb17f, 0xc098, 0x21, 0 + .dw 0xb1c0, 0xc098, 0xb1ff, 0xc098, 0x21, 0 + .dw 0xb240, 0xc098, 0xb27f, 0xc098, 0x21, 0 + .dw 0xb2c0, 0xc098, 0xb2ff, 0xc098, 0x21, 0 + .dw 0xb340, 0xc098, 0xb37f, 0xc098, 0x21, 0 + .dw 0xb3c0, 0xc098, 0xb3ff, 0xc098, 0x21, 0 + .dw 0xb440, 0xc098, 0xb47f, 0xc098, 0x21, 0 + .dw 0xb4c0, 0xc098, 0xb4ff, 0xc098, 0x21, 0 + .dw 0xb540, 0xc098, 0xb57f, 0xc098, 0x21, 0 + .dw 0xb5c0, 0xc098, 0xb5ff, 0xc098, 0x21, 0 + .dw 0xb640, 0xc098, 0xb67f, 0xc098, 0x21, 0 + .dw 0xb6c0, 0xc098, 0xb6ff, 0xc098, 0x21, 0 + .dw 0xb740, 0xc098, 0xb77f, 0xc098, 0x21, 0 + .dw 0xb7c0, 0xc098, 0xb7ff, 0xc098, 0x21, 0 + .dw 0xb840, 0xc098, 0xb87f, 0xc098, 0x21, 0 + .dw 0xb8c0, 0xc098, 0xb8ff, 0xc098, 0x21, 0 + .dw 0xb940, 0xc098, 0xb97f, 0xc098, 0x21, 0 + .dw 0xb9c0, 0xc098, 0xdfff, 0xc098, 0x21, 0 + .dw 0xe040, 0xc098, 0xe07f, 0xc098, 0x21, 0 + .dw 0xe0c0, 0xc098, 0xe0ff, 0xc098, 0x21, 0 + .dw 0xe140, 0xc098, 0xe17f, 0xc098, 0x21, 0 + .dw 0xe1c0, 0xc098, 0xe1ff, 0xc098, 0x21, 0 + .dw 0xe240, 0xc098, 0xe27f, 0xc098, 0x21, 0 + .dw 0xe2c0, 0xc098, 0xe2ff, 0xc098, 0x21, 0 + .dw 0xe340, 0xc098, 0xe37f, 0xc098, 0x21, 0 + .dw 0xe3c0, 0xc098, 0xe3ff, 0xc098, 0x21, 0 + .dw 0xe440, 0xc098, 0xe47f, 0xc098, 0x21, 0 + .dw 0xe4c0, 0xc098, 0xe4ff, 0xc098, 0x21, 0 + .dw 0xe540, 0xc098, 0xe57f, 0xc098, 0x21, 0 + .dw 0xe5c0, 0xc098, 0xe5ff, 0xc098, 0x21, 0 + .dw 0xe640, 0xc098, 0xe67f, 0xc098, 0x21, 0 + .dw 0xe6c0, 0xc098, 0xe6ff, 0xc098, 0x21, 0 + .dw 0xe740, 0xc098, 0xe77f, 0xc098, 0x21, 0 + .dw 0xe7c0, 0xc098, 0xe7ff, 0xc098, 0x21, 0 + .dw 0xe840, 0xc098, 0xe87f, 0xc098, 0x21, 0 + .dw 0xe8c0, 0xc098, 0xe8ff, 0xc098, 0x21, 0 + .dw 0xe940, 0xc098, 0xe97f, 0xc098, 0x21, 0 + .dw 0xe9c0, 0xc098, 0xe9ff, 0xc098, 0x21, 0 + .dw 0xea40, 0xc098, 0xea7f, 0xc098, 0x21, 0 + .dw 0xeac0, 0xc098, 0xeaff, 0xc098, 0x21, 0 + .dw 0xeb40, 0xc098, 0xeb7f, 0xc098, 0x21, 0 + .dw 0xebc0, 0xc098, 0xebff, 0xc098, 0x21, 0 + .dw 0xec40, 0xc098, 0xec7f, 0xc098, 0x21, 0 + .dw 0xecc0, 0xc098, 0xecff, 0xc098, 0x21, 0 + .dw 0xed40, 0xc098, 0xed7f, 0xc098, 0x21, 0 + .dw 0xedc0, 0xc098, 0xedff, 0xc098, 0x21, 0 + .dw 0xee40, 0xc098, 0xee7f, 0xc098, 0x21, 0 + .dw 0xeec0, 0xc098, 0xeeff, 0xc098, 0x21, 0 + .dw 0xef40, 0xc098, 0xef7f, 0xc098, 0x21, 0 + .dw 0xefc0, 0xc098, 0xefff, 0xc098, 0x21, 0 + .dw 0xf040, 0xc098, 0xf07f, 0xc098, 0x21, 0 + .dw 0xf0c0, 0xc098, 0xf0ff, 0xc098, 0x21, 0 + .dw 0xf140, 0xc098, 0xf17f, 0xc098, 0x21, 0 + .dw 0xf1c0, 0xc098, 0xf1ff, 0xc098, 0x21, 0 + .dw 0xf240, 0xc098, 0xf27f, 0xc098, 0x21, 0 + .dw 0xf2c0, 0xc098, 0xf2ff, 0xc098, 0x21, 0 + .dw 0xf340, 0xc098, 0xf37f, 0xc098, 0x21, 0 + .dw 0xf3c0, 0xc098, 0xf3ff, 0xc098, 0x21, 0 + .dw 0xf440, 0xc098, 0xf47f, 0xc098, 0x21, 0 + .dw 0xf4c0, 0xc098, 0xf4ff, 0xc098, 0x21, 0 + .dw 0xf540, 0xc098, 0xf57f, 0xc098, 0x21, 0 + .dw 0xf5c0, 0xc098, 0xf5ff, 0xc098, 0x21, 0 + .dw 0xf640, 0xc098, 0xf67f, 0xc098, 0x21, 0 + .dw 0xf6c0, 0xc098, 0xf6ff, 0xc098, 0x21, 0 + .dw 0xf740, 0xc098, 0xf77f, 0xc098, 0x21, 0 + .dw 0xf7c0, 0xc098, 0xf7ff, 0xc098, 0x21, 0 + .dw 0xf840, 0xc098, 0xf87f, 0xc098, 0x21, 0 + .dw 0xf8c0, 0xc098, 0xf8ff, 0xc098, 0x21, 0 + .dw 0xf940, 0xc098, 0xf97f, 0xc098, 0x21, 0 + .dw 0xf9c0, 0xc098, 0x1fff, 0xc099, 0x21, 0 + .dw 0x2040, 0xc099, 0x207f, 0xc099, 0x21, 0 + .dw 0x20c0, 0xc099, 0x20ff, 0xc099, 0x21, 0 + .dw 0x2140, 0xc099, 0x217f, 0xc099, 0x21, 0 + .dw 0x21c0, 0xc099, 0x21ff, 0xc099, 0x21, 0 + .dw 0x2240, 0xc099, 0x227f, 0xc099, 0x21, 0 + .dw 0x22c0, 0xc099, 0x22ff, 0xc099, 0x21, 0 + .dw 0x2340, 0xc099, 0x237f, 0xc099, 0x21, 0 + .dw 0x23c0, 0xc099, 0x23ff, 0xc099, 0x21, 0 + .dw 0x2440, 0xc099, 0x247f, 0xc099, 0x21, 0 + .dw 0x24c0, 0xc099, 0x24ff, 0xc099, 0x21, 0 + .dw 0x2540, 0xc099, 0x257f, 0xc099, 0x21, 0 + .dw 0x25c0, 0xc099, 0x25ff, 0xc099, 0x21, 0 + .dw 0x2640, 0xc099, 0x267f, 0xc099, 0x21, 0 + .dw 0x26c0, 0xc099, 0x26ff, 0xc099, 0x21, 0 + .dw 0x2740, 0xc099, 0x277f, 0xc099, 0x21, 0 + .dw 0x27c0, 0xc099, 0x27ff, 0xc099, 0x21, 0 + .dw 0x2840, 0xc099, 0x287f, 0xc099, 0x21, 0 + .dw 0x28c0, 0xc099, 0x28ff, 0xc099, 0x21, 0 + .dw 0x2940, 0xc099, 0x297f, 0xc099, 0x21, 0 + .dw 0x29c0, 0xc099, 0x29ff, 0xc099, 0x21, 0 + .dw 0x2a40, 0xc099, 0x2a7f, 0xc099, 0x21, 0 + .dw 0x2ac0, 0xc099, 0x2aff, 0xc099, 0x21, 0 + .dw 0x2b40, 0xc099, 0x2b7f, 0xc099, 0x21, 0 + .dw 0x2bc0, 0xc099, 0x2bff, 0xc099, 0x21, 0 + .dw 0x2c40, 0xc099, 0x2c7f, 0xc099, 0x21, 0 + .dw 0x2cc0, 0xc099, 0x2cff, 0xc099, 0x21, 0 + .dw 0x2d40, 0xc099, 0x2d7f, 0xc099, 0x21, 0 + .dw 0x2dc0, 0xc099, 0x2dff, 0xc099, 0x21, 0 + .dw 0x2e40, 0xc099, 0x2e7f, 0xc099, 0x21, 0 + .dw 0x2ec0, 0xc099, 0x2eff, 0xc099, 0x21, 0 + .dw 0x2f40, 0xc099, 0x2f7f, 0xc099, 0x21, 0 + .dw 0x2fc0, 0xc099, 0x2fff, 0xc099, 0x21, 0 + .dw 0x3040, 0xc099, 0x307f, 0xc099, 0x21, 0 + .dw 0x30c0, 0xc099, 0x30ff, 0xc099, 0x21, 0 + .dw 0x3140, 0xc099, 0x317f, 0xc099, 0x21, 0 + .dw 0x31c0, 0xc099, 0x31ff, 0xc099, 0x21, 0 + .dw 0x3240, 0xc099, 0x327f, 0xc099, 0x21, 0 + .dw 0x32c0, 0xc099, 0x32ff, 0xc099, 0x21, 0 + .dw 0x3340, 0xc099, 0x337f, 0xc099, 0x21, 0 + .dw 0x33c0, 0xc099, 0x33ff, 0xc099, 0x21, 0 + .dw 0x3440, 0xc099, 0x347f, 0xc099, 0x21, 0 + .dw 0x34c0, 0xc099, 0x34ff, 0xc099, 0x21, 0 + .dw 0x3540, 0xc099, 0x357f, 0xc099, 0x21, 0 + .dw 0x35c0, 0xc099, 0x35ff, 0xc099, 0x21, 0 + .dw 0x3640, 0xc099, 0x367f, 0xc099, 0x21, 0 + .dw 0x36c0, 0xc099, 0x36ff, 0xc099, 0x21, 0 + .dw 0x3740, 0xc099, 0x377f, 0xc099, 0x21, 0 + .dw 0x37c0, 0xc099, 0x37ff, 0xc099, 0x21, 0 + .dw 0x3840, 0xc099, 0x387f, 0xc099, 0x21, 0 + .dw 0x38c0, 0xc099, 0x38ff, 0xc099, 0x21, 0 + .dw 0x3940, 0xc099, 0x397f, 0xc099, 0x21, 0 + .dw 0x39c0, 0xc099, 0x5fff, 0xc099, 0x21, 0 + .dw 0x6040, 0xc099, 0x607f, 0xc099, 0x21, 0 + .dw 0x60c0, 0xc099, 0x60ff, 0xc099, 0x21, 0 + .dw 0x6140, 0xc099, 0x617f, 0xc099, 0x21, 0 + .dw 0x61c0, 0xc099, 0x61ff, 0xc099, 0x21, 0 + .dw 0x6240, 0xc099, 0x627f, 0xc099, 0x21, 0 + .dw 0x62c0, 0xc099, 0x62ff, 0xc099, 0x21, 0 + .dw 0x6340, 0xc099, 0x637f, 0xc099, 0x21, 0 + .dw 0x63c0, 0xc099, 0x63ff, 0xc099, 0x21, 0 + .dw 0x6440, 0xc099, 0x647f, 0xc099, 0x21, 0 + .dw 0x64c0, 0xc099, 0x64ff, 0xc099, 0x21, 0 + .dw 0x6540, 0xc099, 0x657f, 0xc099, 0x21, 0 + .dw 0x65c0, 0xc099, 0x65ff, 0xc099, 0x21, 0 + .dw 0x6640, 0xc099, 0x667f, 0xc099, 0x21, 0 + .dw 0x66c0, 0xc099, 0x66ff, 0xc099, 0x21, 0 + .dw 0x6740, 0xc099, 0x677f, 0xc099, 0x21, 0 + .dw 0x67c0, 0xc099, 0x67ff, 0xc099, 0x21, 0 + .dw 0x6840, 0xc099, 0x687f, 0xc099, 0x21, 0 + .dw 0x68c0, 0xc099, 0x68ff, 0xc099, 0x21, 0 + .dw 0x6940, 0xc099, 0x697f, 0xc099, 0x21, 0 + .dw 0x69c0, 0xc099, 0x69ff, 0xc099, 0x21, 0 + .dw 0x6a40, 0xc099, 0x6a7f, 0xc099, 0x21, 0 + .dw 0x6ac0, 0xc099, 0x6aff, 0xc099, 0x21, 0 + .dw 0x6b40, 0xc099, 0x6b7f, 0xc099, 0x21, 0 + .dw 0x6bc0, 0xc099, 0x6bff, 0xc099, 0x21, 0 + .dw 0x6c40, 0xc099, 0x6c7f, 0xc099, 0x21, 0 + .dw 0x6cc0, 0xc099, 0x6cff, 0xc099, 0x21, 0 + .dw 0x6d40, 0xc099, 0x6d7f, 0xc099, 0x21, 0 + .dw 0x6dc0, 0xc099, 0x6dff, 0xc099, 0x21, 0 + .dw 0x6e40, 0xc099, 0x6e7f, 0xc099, 0x21, 0 + .dw 0x6ec0, 0xc099, 0x6eff, 0xc099, 0x21, 0 + .dw 0x6f40, 0xc099, 0x6f7f, 0xc099, 0x21, 0 + .dw 0x6fc0, 0xc099, 0x6fff, 0xc099, 0x21, 0 + .dw 0x7040, 0xc099, 0x707f, 0xc099, 0x21, 0 + .dw 0x70c0, 0xc099, 0x70ff, 0xc099, 0x21, 0 + .dw 0x7140, 0xc099, 0x717f, 0xc099, 0x21, 0 + .dw 0x71c0, 0xc099, 0x71ff, 0xc099, 0x21, 0 + .dw 0x7240, 0xc099, 0x727f, 0xc099, 0x21, 0 + .dw 0x72c0, 0xc099, 0x72ff, 0xc099, 0x21, 0 + .dw 0x7340, 0xc099, 0x737f, 0xc099, 0x21, 0 + .dw 0x73c0, 0xc099, 0x73ff, 0xc099, 0x21, 0 + .dw 0x7440, 0xc099, 0x747f, 0xc099, 0x21, 0 + .dw 0x74c0, 0xc099, 0x74ff, 0xc099, 0x21, 0 + .dw 0x7540, 0xc099, 0x757f, 0xc099, 0x21, 0 + .dw 0x75c0, 0xc099, 0x75ff, 0xc099, 0x21, 0 + .dw 0x7640, 0xc099, 0x767f, 0xc099, 0x21, 0 + .dw 0x76c0, 0xc099, 0x76ff, 0xc099, 0x21, 0 + .dw 0x7740, 0xc099, 0x777f, 0xc099, 0x21, 0 + .dw 0x77c0, 0xc099, 0x77ff, 0xc099, 0x21, 0 + .dw 0x7840, 0xc099, 0x787f, 0xc099, 0x21, 0 + .dw 0x78c0, 0xc099, 0x78ff, 0xc099, 0x21, 0 + .dw 0x7940, 0xc099, 0x797f, 0xc099, 0x21, 0 + .dw 0x79c0, 0xc099, 0x9fff, 0xc099, 0x21, 0 + .dw 0xa040, 0xc099, 0xa07f, 0xc099, 0x21, 0 + .dw 0xa0c0, 0xc099, 0xa0ff, 0xc099, 0x21, 0 + .dw 0xa140, 0xc099, 0xa17f, 0xc099, 0x21, 0 + .dw 0xa1c0, 0xc099, 0xa1ff, 0xc099, 0x21, 0 + .dw 0xa240, 0xc099, 0xa27f, 0xc099, 0x21, 0 + .dw 0xa2c0, 0xc099, 0xa2ff, 0xc099, 0x21, 0 + .dw 0xa340, 0xc099, 0xa37f, 0xc099, 0x21, 0 + .dw 0xa3c0, 0xc099, 0xa3ff, 0xc099, 0x21, 0 + .dw 0xa440, 0xc099, 0xa47f, 0xc099, 0x21, 0 + .dw 0xa4c0, 0xc099, 0xa4ff, 0xc099, 0x21, 0 + .dw 0xa540, 0xc099, 0xa57f, 0xc099, 0x21, 0 + .dw 0xa5c0, 0xc099, 0xa5ff, 0xc099, 0x21, 0 + .dw 0xa640, 0xc099, 0xa67f, 0xc099, 0x21, 0 + .dw 0xa6c0, 0xc099, 0xa6ff, 0xc099, 0x21, 0 + .dw 0xa740, 0xc099, 0xa77f, 0xc099, 0x21, 0 + .dw 0xa7c0, 0xc099, 0xa7ff, 0xc099, 0x21, 0 + .dw 0xa840, 0xc099, 0xa87f, 0xc099, 0x21, 0 + .dw 0xa8c0, 0xc099, 0xa8ff, 0xc099, 0x21, 0 + .dw 0xa940, 0xc099, 0xa97f, 0xc099, 0x21, 0 + .dw 0xa9c0, 0xc099, 0xa9ff, 0xc099, 0x21, 0 + .dw 0xaa40, 0xc099, 0xaa7f, 0xc099, 0x21, 0 + .dw 0xaac0, 0xc099, 0xaaff, 0xc099, 0x21, 0 + .dw 0xab40, 0xc099, 0xab7f, 0xc099, 0x21, 0 + .dw 0xabc0, 0xc099, 0xabff, 0xc099, 0x21, 0 + .dw 0xac40, 0xc099, 0xac7f, 0xc099, 0x21, 0 + .dw 0xacc0, 0xc099, 0xacff, 0xc099, 0x21, 0 + .dw 0xad40, 0xc099, 0xad7f, 0xc099, 0x21, 0 + .dw 0xadc0, 0xc099, 0xadff, 0xc099, 0x21, 0 + .dw 0xae40, 0xc099, 0xae7f, 0xc099, 0x21, 0 + .dw 0xaec0, 0xc099, 0xaeff, 0xc099, 0x21, 0 + .dw 0xaf40, 0xc099, 0xaf7f, 0xc099, 0x21, 0 + .dw 0xafc0, 0xc099, 0xafff, 0xc099, 0x21, 0 + .dw 0xb040, 0xc099, 0xb07f, 0xc099, 0x21, 0 + .dw 0xb0c0, 0xc099, 0xb0ff, 0xc099, 0x21, 0 + .dw 0xb140, 0xc099, 0xb17f, 0xc099, 0x21, 0 + .dw 0xb1c0, 0xc099, 0xb1ff, 0xc099, 0x21, 0 + .dw 0xb240, 0xc099, 0xb27f, 0xc099, 0x21, 0 + .dw 0xb2c0, 0xc099, 0xb2ff, 0xc099, 0x21, 0 + .dw 0xb340, 0xc099, 0xb37f, 0xc099, 0x21, 0 + .dw 0xb3c0, 0xc099, 0xb3ff, 0xc099, 0x21, 0 + .dw 0xb440, 0xc099, 0xb47f, 0xc099, 0x21, 0 + .dw 0xb4c0, 0xc099, 0xb4ff, 0xc099, 0x21, 0 + .dw 0xb540, 0xc099, 0xb57f, 0xc099, 0x21, 0 + .dw 0xb5c0, 0xc099, 0xb5ff, 0xc099, 0x21, 0 + .dw 0xb640, 0xc099, 0xb67f, 0xc099, 0x21, 0 + .dw 0xb6c0, 0xc099, 0xb6ff, 0xc099, 0x21, 0 + .dw 0xb740, 0xc099, 0xb77f, 0xc099, 0x21, 0 + .dw 0xb7c0, 0xc099, 0xb7ff, 0xc099, 0x21, 0 + .dw 0xb840, 0xc099, 0xb87f, 0xc099, 0x21, 0 + .dw 0xb8c0, 0xc099, 0xb8ff, 0xc099, 0x21, 0 + .dw 0xb940, 0xc099, 0xb97f, 0xc099, 0x21, 0 + .dw 0xb9c0, 0xc099, 0xdfff, 0xc099, 0x21, 0 + .dw 0xe040, 0xc099, 0xe07f, 0xc099, 0x21, 0 + .dw 0xe0c0, 0xc099, 0xe0ff, 0xc099, 0x21, 0 + .dw 0xe140, 0xc099, 0xe17f, 0xc099, 0x21, 0 + .dw 0xe1c0, 0xc099, 0xe1ff, 0xc099, 0x21, 0 + .dw 0xe240, 0xc099, 0xe27f, 0xc099, 0x21, 0 + .dw 0xe2c0, 0xc099, 0xe2ff, 0xc099, 0x21, 0 + .dw 0xe340, 0xc099, 0xe37f, 0xc099, 0x21, 0 + .dw 0xe3c0, 0xc099, 0xe3ff, 0xc099, 0x21, 0 + .dw 0xe440, 0xc099, 0xe47f, 0xc099, 0x21, 0 + .dw 0xe4c0, 0xc099, 0xe4ff, 0xc099, 0x21, 0 + .dw 0xe540, 0xc099, 0xe57f, 0xc099, 0x21, 0 + .dw 0xe5c0, 0xc099, 0xe5ff, 0xc099, 0x21, 0 + .dw 0xe640, 0xc099, 0xe67f, 0xc099, 0x21, 0 + .dw 0xe6c0, 0xc099, 0xe6ff, 0xc099, 0x21, 0 + .dw 0xe740, 0xc099, 0xe77f, 0xc099, 0x21, 0 + .dw 0xe7c0, 0xc099, 0xe7ff, 0xc099, 0x21, 0 + .dw 0xe840, 0xc099, 0xe87f, 0xc099, 0x21, 0 + .dw 0xe8c0, 0xc099, 0xe8ff, 0xc099, 0x21, 0 + .dw 0xe940, 0xc099, 0xe97f, 0xc099, 0x21, 0 + .dw 0xe9c0, 0xc099, 0xe9ff, 0xc099, 0x21, 0 + .dw 0xea40, 0xc099, 0xea7f, 0xc099, 0x21, 0 + .dw 0xeac0, 0xc099, 0xeaff, 0xc099, 0x21, 0 + .dw 0xeb40, 0xc099, 0xeb7f, 0xc099, 0x21, 0 + .dw 0xebc0, 0xc099, 0xebff, 0xc099, 0x21, 0 + .dw 0xec40, 0xc099, 0xec7f, 0xc099, 0x21, 0 + .dw 0xecc0, 0xc099, 0xecff, 0xc099, 0x21, 0 + .dw 0xed40, 0xc099, 0xed7f, 0xc099, 0x21, 0 + .dw 0xedc0, 0xc099, 0xedff, 0xc099, 0x21, 0 + .dw 0xee40, 0xc099, 0xee7f, 0xc099, 0x21, 0 + .dw 0xeec0, 0xc099, 0xeeff, 0xc099, 0x21, 0 + .dw 0xef40, 0xc099, 0xef7f, 0xc099, 0x21, 0 + .dw 0xefc0, 0xc099, 0xefff, 0xc099, 0x21, 0 + .dw 0xf040, 0xc099, 0xf07f, 0xc099, 0x21, 0 + .dw 0xf0c0, 0xc099, 0xf0ff, 0xc099, 0x21, 0 + .dw 0xf140, 0xc099, 0xf17f, 0xc099, 0x21, 0 + .dw 0xf1c0, 0xc099, 0xf1ff, 0xc099, 0x21, 0 + .dw 0xf240, 0xc099, 0xf27f, 0xc099, 0x21, 0 + .dw 0xf2c0, 0xc099, 0xf2ff, 0xc099, 0x21, 0 + .dw 0xf340, 0xc099, 0xf37f, 0xc099, 0x21, 0 + .dw 0xf3c0, 0xc099, 0xf3ff, 0xc099, 0x21, 0 + .dw 0xf440, 0xc099, 0xf47f, 0xc099, 0x21, 0 + .dw 0xf4c0, 0xc099, 0xf4ff, 0xc099, 0x21, 0 + .dw 0xf540, 0xc099, 0xf57f, 0xc099, 0x21, 0 + .dw 0xf5c0, 0xc099, 0xf5ff, 0xc099, 0x21, 0 + .dw 0xf640, 0xc099, 0xf67f, 0xc099, 0x21, 0 + .dw 0xf6c0, 0xc099, 0xf6ff, 0xc099, 0x21, 0 + .dw 0xf740, 0xc099, 0xf77f, 0xc099, 0x21, 0 + .dw 0xf7c0, 0xc099, 0xf7ff, 0xc099, 0x21, 0 + .dw 0xf840, 0xc099, 0xf87f, 0xc099, 0x21, 0 + .dw 0xf8c0, 0xc099, 0xf8ff, 0xc099, 0x21, 0 + .dw 0xf940, 0xc099, 0xf97f, 0xc099, 0x21, 0 + .dw 0xf9c0, 0xc099, 0x1fff, 0xc09a, 0x21, 0 + .dw 0x2040, 0xc09a, 0x207f, 0xc09a, 0x21, 0 + .dw 0x20c0, 0xc09a, 0x20ff, 0xc09a, 0x21, 0 + .dw 0x2140, 0xc09a, 0x217f, 0xc09a, 0x21, 0 + .dw 0x21c0, 0xc09a, 0x21ff, 0xc09a, 0x21, 0 + .dw 0x2240, 0xc09a, 0x227f, 0xc09a, 0x21, 0 + .dw 0x22c0, 0xc09a, 0x22ff, 0xc09a, 0x21, 0 + .dw 0x2340, 0xc09a, 0x237f, 0xc09a, 0x21, 0 + .dw 0x23c0, 0xc09a, 0x23ff, 0xc09a, 0x21, 0 + .dw 0x2440, 0xc09a, 0x247f, 0xc09a, 0x21, 0 + .dw 0x24c0, 0xc09a, 0x24ff, 0xc09a, 0x21, 0 + .dw 0x2540, 0xc09a, 0x257f, 0xc09a, 0x21, 0 + .dw 0x25c0, 0xc09a, 0x25ff, 0xc09a, 0x21, 0 + .dw 0x2640, 0xc09a, 0x267f, 0xc09a, 0x21, 0 + .dw 0x26c0, 0xc09a, 0x26ff, 0xc09a, 0x21, 0 + .dw 0x2740, 0xc09a, 0x277f, 0xc09a, 0x21, 0 + .dw 0x27c0, 0xc09a, 0x27ff, 0xc09a, 0x21, 0 + .dw 0x2840, 0xc09a, 0x287f, 0xc09a, 0x21, 0 + .dw 0x28c0, 0xc09a, 0x28ff, 0xc09a, 0x21, 0 + .dw 0x2940, 0xc09a, 0x297f, 0xc09a, 0x21, 0 + .dw 0x29c0, 0xc09a, 0x29ff, 0xc09a, 0x21, 0 + .dw 0x2a40, 0xc09a, 0x2a7f, 0xc09a, 0x21, 0 + .dw 0x2ac0, 0xc09a, 0x2aff, 0xc09a, 0x21, 0 + .dw 0x2b40, 0xc09a, 0x2b7f, 0xc09a, 0x21, 0 + .dw 0x2bc0, 0xc09a, 0x2bff, 0xc09a, 0x21, 0 + .dw 0x2c40, 0xc09a, 0x2c7f, 0xc09a, 0x21, 0 + .dw 0x2cc0, 0xc09a, 0x2cff, 0xc09a, 0x21, 0 + .dw 0x2d40, 0xc09a, 0x2d7f, 0xc09a, 0x21, 0 + .dw 0x2dc0, 0xc09a, 0x2dff, 0xc09a, 0x21, 0 + .dw 0x2e40, 0xc09a, 0x2e7f, 0xc09a, 0x21, 0 + .dw 0x2ec0, 0xc09a, 0x2eff, 0xc09a, 0x21, 0 + .dw 0x2f40, 0xc09a, 0x2f7f, 0xc09a, 0x21, 0 + .dw 0x2fc0, 0xc09a, 0x2fff, 0xc09a, 0x21, 0 + .dw 0x3040, 0xc09a, 0x307f, 0xc09a, 0x21, 0 + .dw 0x30c0, 0xc09a, 0x30ff, 0xc09a, 0x21, 0 + .dw 0x3140, 0xc09a, 0x317f, 0xc09a, 0x21, 0 + .dw 0x31c0, 0xc09a, 0x31ff, 0xc09a, 0x21, 0 + .dw 0x3240, 0xc09a, 0x327f, 0xc09a, 0x21, 0 + .dw 0x32c0, 0xc09a, 0x32ff, 0xc09a, 0x21, 0 + .dw 0x3340, 0xc09a, 0x337f, 0xc09a, 0x21, 0 + .dw 0x33c0, 0xc09a, 0x33ff, 0xc09a, 0x21, 0 + .dw 0x3440, 0xc09a, 0x347f, 0xc09a, 0x21, 0 + .dw 0x34c0, 0xc09a, 0x34ff, 0xc09a, 0x21, 0 + .dw 0x3540, 0xc09a, 0x357f, 0xc09a, 0x21, 0 + .dw 0x35c0, 0xc09a, 0x35ff, 0xc09a, 0x21, 0 + .dw 0x3640, 0xc09a, 0x367f, 0xc09a, 0x21, 0 + .dw 0x36c0, 0xc09a, 0x36ff, 0xc09a, 0x21, 0 + .dw 0x3740, 0xc09a, 0x377f, 0xc09a, 0x21, 0 + .dw 0x37c0, 0xc09a, 0x37ff, 0xc09a, 0x21, 0 + .dw 0x3840, 0xc09a, 0x387f, 0xc09a, 0x21, 0 + .dw 0x38c0, 0xc09a, 0x38ff, 0xc09a, 0x21, 0 + .dw 0x3940, 0xc09a, 0x397f, 0xc09a, 0x21, 0 + .dw 0x39c0, 0xc09a, 0x5fff, 0xc09a, 0x21, 0 + .dw 0x6040, 0xc09a, 0x607f, 0xc09a, 0x21, 0 + .dw 0x60c0, 0xc09a, 0x60ff, 0xc09a, 0x21, 0 + .dw 0x6140, 0xc09a, 0x617f, 0xc09a, 0x21, 0 + .dw 0x61c0, 0xc09a, 0x61ff, 0xc09a, 0x21, 0 + .dw 0x6240, 0xc09a, 0x627f, 0xc09a, 0x21, 0 + .dw 0x62c0, 0xc09a, 0x62ff, 0xc09a, 0x21, 0 + .dw 0x6340, 0xc09a, 0x637f, 0xc09a, 0x21, 0 + .dw 0x63c0, 0xc09a, 0x63ff, 0xc09a, 0x21, 0 + .dw 0x6440, 0xc09a, 0x647f, 0xc09a, 0x21, 0 + .dw 0x64c0, 0xc09a, 0x64ff, 0xc09a, 0x21, 0 + .dw 0x6540, 0xc09a, 0x657f, 0xc09a, 0x21, 0 + .dw 0x65c0, 0xc09a, 0x65ff, 0xc09a, 0x21, 0 + .dw 0x6640, 0xc09a, 0x667f, 0xc09a, 0x21, 0 + .dw 0x66c0, 0xc09a, 0x66ff, 0xc09a, 0x21, 0 + .dw 0x6740, 0xc09a, 0x677f, 0xc09a, 0x21, 0 + .dw 0x67c0, 0xc09a, 0x67ff, 0xc09a, 0x21, 0 + .dw 0x6840, 0xc09a, 0x687f, 0xc09a, 0x21, 0 + .dw 0x68c0, 0xc09a, 0x68ff, 0xc09a, 0x21, 0 + .dw 0x6940, 0xc09a, 0x697f, 0xc09a, 0x21, 0 + .dw 0x69c0, 0xc09a, 0x69ff, 0xc09a, 0x21, 0 + .dw 0x6a40, 0xc09a, 0x6a7f, 0xc09a, 0x21, 0 + .dw 0x6ac0, 0xc09a, 0x6aff, 0xc09a, 0x21, 0 + .dw 0x6b40, 0xc09a, 0x6b7f, 0xc09a, 0x21, 0 + .dw 0x6bc0, 0xc09a, 0x6bff, 0xc09a, 0x21, 0 + .dw 0x6c40, 0xc09a, 0x6c7f, 0xc09a, 0x21, 0 + .dw 0x6cc0, 0xc09a, 0x6cff, 0xc09a, 0x21, 0 + .dw 0x6d40, 0xc09a, 0x6d7f, 0xc09a, 0x21, 0 + .dw 0x6dc0, 0xc09a, 0x6dff, 0xc09a, 0x21, 0 + .dw 0x6e40, 0xc09a, 0x6e7f, 0xc09a, 0x21, 0 + .dw 0x6ec0, 0xc09a, 0x6eff, 0xc09a, 0x21, 0 + .dw 0x6f40, 0xc09a, 0x6f7f, 0xc09a, 0x21, 0 + .dw 0x6fc0, 0xc09a, 0x6fff, 0xc09a, 0x21, 0 + .dw 0x7040, 0xc09a, 0x707f, 0xc09a, 0x21, 0 + .dw 0x70c0, 0xc09a, 0x70ff, 0xc09a, 0x21, 0 + .dw 0x7140, 0xc09a, 0x717f, 0xc09a, 0x21, 0 + .dw 0x71c0, 0xc09a, 0x71ff, 0xc09a, 0x21, 0 + .dw 0x7240, 0xc09a, 0x727f, 0xc09a, 0x21, 0 + .dw 0x72c0, 0xc09a, 0x72ff, 0xc09a, 0x21, 0 + .dw 0x7340, 0xc09a, 0x737f, 0xc09a, 0x21, 0 + .dw 0x73c0, 0xc09a, 0x73ff, 0xc09a, 0x21, 0 + .dw 0x7440, 0xc09a, 0x747f, 0xc09a, 0x21, 0 + .dw 0x74c0, 0xc09a, 0x74ff, 0xc09a, 0x21, 0 + .dw 0x7540, 0xc09a, 0x757f, 0xc09a, 0x21, 0 + .dw 0x75c0, 0xc09a, 0x75ff, 0xc09a, 0x21, 0 + .dw 0x7640, 0xc09a, 0x767f, 0xc09a, 0x21, 0 + .dw 0x76c0, 0xc09a, 0x76ff, 0xc09a, 0x21, 0 + .dw 0x7740, 0xc09a, 0x777f, 0xc09a, 0x21, 0 + .dw 0x77c0, 0xc09a, 0x77ff, 0xc09a, 0x21, 0 + .dw 0x7840, 0xc09a, 0x787f, 0xc09a, 0x21, 0 + .dw 0x78c0, 0xc09a, 0x78ff, 0xc09a, 0x21, 0 + .dw 0x7940, 0xc09a, 0x797f, 0xc09a, 0x21, 0 + .dw 0x79c0, 0xc09a, 0x9fff, 0xc09a, 0x21, 0 + .dw 0xa040, 0xc09a, 0xa07f, 0xc09a, 0x21, 0 + .dw 0xa0c0, 0xc09a, 0xa0ff, 0xc09a, 0x21, 0 + .dw 0xa140, 0xc09a, 0xa17f, 0xc09a, 0x21, 0 + .dw 0xa1c0, 0xc09a, 0xa1ff, 0xc09a, 0x21, 0 + .dw 0xa240, 0xc09a, 0xa27f, 0xc09a, 0x21, 0 + .dw 0xa2c0, 0xc09a, 0xa2ff, 0xc09a, 0x21, 0 + .dw 0xa340, 0xc09a, 0xa37f, 0xc09a, 0x21, 0 + .dw 0xa3c0, 0xc09a, 0xa3ff, 0xc09a, 0x21, 0 + .dw 0xa440, 0xc09a, 0xa47f, 0xc09a, 0x21, 0 + .dw 0xa4c0, 0xc09a, 0xa4ff, 0xc09a, 0x21, 0 + .dw 0xa540, 0xc09a, 0xa57f, 0xc09a, 0x21, 0 + .dw 0xa5c0, 0xc09a, 0xa5ff, 0xc09a, 0x21, 0 + .dw 0xa640, 0xc09a, 0xa67f, 0xc09a, 0x21, 0 + .dw 0xa6c0, 0xc09a, 0xa6ff, 0xc09a, 0x21, 0 + .dw 0xa740, 0xc09a, 0xa77f, 0xc09a, 0x21, 0 + .dw 0xa7c0, 0xc09a, 0xa7ff, 0xc09a, 0x21, 0 + .dw 0xa840, 0xc09a, 0xa87f, 0xc09a, 0x21, 0 + .dw 0xa8c0, 0xc09a, 0xa8ff, 0xc09a, 0x21, 0 + .dw 0xa940, 0xc09a, 0xa97f, 0xc09a, 0x21, 0 + .dw 0xa9c0, 0xc09a, 0xa9ff, 0xc09a, 0x21, 0 + .dw 0xaa40, 0xc09a, 0xaa7f, 0xc09a, 0x21, 0 + .dw 0xaac0, 0xc09a, 0xaaff, 0xc09a, 0x21, 0 + .dw 0xab40, 0xc09a, 0xab7f, 0xc09a, 0x21, 0 + .dw 0xabc0, 0xc09a, 0xabff, 0xc09a, 0x21, 0 + .dw 0xac40, 0xc09a, 0xac7f, 0xc09a, 0x21, 0 + .dw 0xacc0, 0xc09a, 0xacff, 0xc09a, 0x21, 0 + .dw 0xad40, 0xc09a, 0xad7f, 0xc09a, 0x21, 0 + .dw 0xadc0, 0xc09a, 0xadff, 0xc09a, 0x21, 0 + .dw 0xae40, 0xc09a, 0xae7f, 0xc09a, 0x21, 0 + .dw 0xaec0, 0xc09a, 0xaeff, 0xc09a, 0x21, 0 + .dw 0xaf40, 0xc09a, 0xaf7f, 0xc09a, 0x21, 0 + .dw 0xafc0, 0xc09a, 0xafff, 0xc09a, 0x21, 0 + .dw 0xb040, 0xc09a, 0xb07f, 0xc09a, 0x21, 0 + .dw 0xb0c0, 0xc09a, 0xb0ff, 0xc09a, 0x21, 0 + .dw 0xb140, 0xc09a, 0xb17f, 0xc09a, 0x21, 0 + .dw 0xb1c0, 0xc09a, 0xb1ff, 0xc09a, 0x21, 0 + .dw 0xb240, 0xc09a, 0xb27f, 0xc09a, 0x21, 0 + .dw 0xb2c0, 0xc09a, 0xb2ff, 0xc09a, 0x21, 0 + .dw 0xb340, 0xc09a, 0xb37f, 0xc09a, 0x21, 0 + .dw 0xb3c0, 0xc09a, 0xb3ff, 0xc09a, 0x21, 0 + .dw 0xb440, 0xc09a, 0xb47f, 0xc09a, 0x21, 0 + .dw 0xb4c0, 0xc09a, 0xb4ff, 0xc09a, 0x21, 0 + .dw 0xb540, 0xc09a, 0xb57f, 0xc09a, 0x21, 0 + .dw 0xb5c0, 0xc09a, 0xb5ff, 0xc09a, 0x21, 0 + .dw 0xb640, 0xc09a, 0xb67f, 0xc09a, 0x21, 0 + .dw 0xb6c0, 0xc09a, 0xb6ff, 0xc09a, 0x21, 0 + .dw 0xb740, 0xc09a, 0xb77f, 0xc09a, 0x21, 0 + .dw 0xb7c0, 0xc09a, 0xb7ff, 0xc09a, 0x21, 0 + .dw 0xb840, 0xc09a, 0xb87f, 0xc09a, 0x21, 0 + .dw 0xb8c0, 0xc09a, 0xb8ff, 0xc09a, 0x21, 0 + .dw 0xb940, 0xc09a, 0xb97f, 0xc09a, 0x21, 0 + .dw 0xb9c0, 0xc09a, 0xdfff, 0xc09a, 0x21, 0 + .dw 0xe040, 0xc09a, 0xe07f, 0xc09a, 0x21, 0 + .dw 0xe0c0, 0xc09a, 0xe0ff, 0xc09a, 0x21, 0 + .dw 0xe140, 0xc09a, 0xe17f, 0xc09a, 0x21, 0 + .dw 0xe1c0, 0xc09a, 0xe1ff, 0xc09a, 0x21, 0 + .dw 0xe240, 0xc09a, 0xe27f, 0xc09a, 0x21, 0 + .dw 0xe2c0, 0xc09a, 0xe2ff, 0xc09a, 0x21, 0 + .dw 0xe340, 0xc09a, 0xe37f, 0xc09a, 0x21, 0 + .dw 0xe3c0, 0xc09a, 0xe3ff, 0xc09a, 0x21, 0 + .dw 0xe440, 0xc09a, 0xe47f, 0xc09a, 0x21, 0 + .dw 0xe4c0, 0xc09a, 0xe4ff, 0xc09a, 0x21, 0 + .dw 0xe540, 0xc09a, 0xe57f, 0xc09a, 0x21, 0 + .dw 0xe5c0, 0xc09a, 0xe5ff, 0xc09a, 0x21, 0 + .dw 0xe640, 0xc09a, 0xe67f, 0xc09a, 0x21, 0 + .dw 0xe6c0, 0xc09a, 0xe6ff, 0xc09a, 0x21, 0 + .dw 0xe740, 0xc09a, 0xe77f, 0xc09a, 0x21, 0 + .dw 0xe7c0, 0xc09a, 0xe7ff, 0xc09a, 0x21, 0 + .dw 0xe840, 0xc09a, 0xe87f, 0xc09a, 0x21, 0 + .dw 0xe8c0, 0xc09a, 0xe8ff, 0xc09a, 0x21, 0 + .dw 0xe940, 0xc09a, 0xe97f, 0xc09a, 0x21, 0 + .dw 0xe9c0, 0xc09a, 0xe9ff, 0xc09a, 0x21, 0 + .dw 0xea40, 0xc09a, 0xea7f, 0xc09a, 0x21, 0 + .dw 0xeac0, 0xc09a, 0xeaff, 0xc09a, 0x21, 0 + .dw 0xeb40, 0xc09a, 0xeb7f, 0xc09a, 0x21, 0 + .dw 0xebc0, 0xc09a, 0xebff, 0xc09a, 0x21, 0 + .dw 0xec40, 0xc09a, 0xec7f, 0xc09a, 0x21, 0 + .dw 0xecc0, 0xc09a, 0xecff, 0xc09a, 0x21, 0 + .dw 0xed40, 0xc09a, 0xed7f, 0xc09a, 0x21, 0 + .dw 0xedc0, 0xc09a, 0xedff, 0xc09a, 0x21, 0 + .dw 0xee40, 0xc09a, 0xee7f, 0xc09a, 0x21, 0 + .dw 0xeec0, 0xc09a, 0xeeff, 0xc09a, 0x21, 0 + .dw 0xef40, 0xc09a, 0xef7f, 0xc09a, 0x21, 0 + .dw 0xefc0, 0xc09a, 0xefff, 0xc09a, 0x21, 0 + .dw 0xf040, 0xc09a, 0xf07f, 0xc09a, 0x21, 0 + .dw 0xf0c0, 0xc09a, 0xf0ff, 0xc09a, 0x21, 0 + .dw 0xf140, 0xc09a, 0xf17f, 0xc09a, 0x21, 0 + .dw 0xf1c0, 0xc09a, 0xf1ff, 0xc09a, 0x21, 0 + .dw 0xf240, 0xc09a, 0xf27f, 0xc09a, 0x21, 0 + .dw 0xf2c0, 0xc09a, 0xf2ff, 0xc09a, 0x21, 0 + .dw 0xf340, 0xc09a, 0xf37f, 0xc09a, 0x21, 0 + .dw 0xf3c0, 0xc09a, 0xf3ff, 0xc09a, 0x21, 0 + .dw 0xf440, 0xc09a, 0xf47f, 0xc09a, 0x21, 0 + .dw 0xf4c0, 0xc09a, 0xf4ff, 0xc09a, 0x21, 0 + .dw 0xf540, 0xc09a, 0xf57f, 0xc09a, 0x21, 0 + .dw 0xf5c0, 0xc09a, 0xf5ff, 0xc09a, 0x21, 0 + .dw 0xf640, 0xc09a, 0xf67f, 0xc09a, 0x21, 0 + .dw 0xf6c0, 0xc09a, 0xf6ff, 0xc09a, 0x21, 0 + .dw 0xf740, 0xc09a, 0xf77f, 0xc09a, 0x21, 0 + .dw 0xf7c0, 0xc09a, 0xf7ff, 0xc09a, 0x21, 0 + .dw 0xf840, 0xc09a, 0xf87f, 0xc09a, 0x21, 0 + .dw 0xf8c0, 0xc09a, 0xf8ff, 0xc09a, 0x21, 0 + .dw 0xf940, 0xc09a, 0xf97f, 0xc09a, 0x21, 0 + .dw 0xf9c0, 0xc09a, 0xffff, 0xc09b, 0x21, 0 + .dw 0x0040, 0xc09c, 0x007f, 0xc09c, 0x21, 0 + .dw 0x00c0, 0xc09c, 0x00ff, 0xc09c, 0x21, 0 + .dw 0x0140, 0xc09c, 0x017f, 0xc09c, 0x21, 0 + .dw 0x01c0, 0xc09c, 0x01ff, 0xc09c, 0x21, 0 + .dw 0x0240, 0xc09c, 0x027f, 0xc09c, 0x21, 0 + .dw 0x02c0, 0xc09c, 0x02ff, 0xc09c, 0x21, 0 + .dw 0x0340, 0xc09c, 0x037f, 0xc09c, 0x21, 0 + .dw 0x03c0, 0xc09c, 0x03ff, 0xc09c, 0x21, 0 + .dw 0x0440, 0xc09c, 0x047f, 0xc09c, 0x21, 0 + .dw 0x04c0, 0xc09c, 0x04ff, 0xc09c, 0x21, 0 + .dw 0x0540, 0xc09c, 0x057f, 0xc09c, 0x21, 0 + .dw 0x05c0, 0xc09c, 0x05ff, 0xc09c, 0x21, 0 + .dw 0x0640, 0xc09c, 0x067f, 0xc09c, 0x21, 0 + .dw 0x06c0, 0xc09c, 0x06ff, 0xc09c, 0x21, 0 + .dw 0x0740, 0xc09c, 0x077f, 0xc09c, 0x21, 0 + .dw 0x07c0, 0xc09c, 0x07ff, 0xc09c, 0x21, 0 + .dw 0x0840, 0xc09c, 0x087f, 0xc09c, 0x21, 0 + .dw 0x08c0, 0xc09c, 0x08ff, 0xc09c, 0x21, 0 + .dw 0x0940, 0xc09c, 0x097f, 0xc09c, 0x21, 0 + .dw 0x09c0, 0xc09c, 0x09ff, 0xc09c, 0x21, 0 + .dw 0x0a40, 0xc09c, 0x0a7f, 0xc09c, 0x21, 0 + .dw 0x0ac0, 0xc09c, 0x0aff, 0xc09c, 0x21, 0 + .dw 0x0b40, 0xc09c, 0x0b7f, 0xc09c, 0x21, 0 + .dw 0x0bc0, 0xc09c, 0x0bff, 0xc09c, 0x21, 0 + .dw 0x0c40, 0xc09c, 0x0c7f, 0xc09c, 0x21, 0 + .dw 0x0cc0, 0xc09c, 0x0cff, 0xc09c, 0x21, 0 + .dw 0x0d40, 0xc09c, 0x0d7f, 0xc09c, 0x21, 0 + .dw 0x0dc0, 0xc09c, 0x0dff, 0xc09c, 0x21, 0 + .dw 0x0e40, 0xc09c, 0x0e7f, 0xc09c, 0x21, 0 + .dw 0x0ec0, 0xc09c, 0x0eff, 0xc09c, 0x21, 0 + .dw 0x0f40, 0xc09c, 0x0f7f, 0xc09c, 0x21, 0 + .dw 0x0fc0, 0xc09c, 0x0fff, 0xc09c, 0x21, 0 + .dw 0x1040, 0xc09c, 0x107f, 0xc09c, 0x21, 0 + .dw 0x10c0, 0xc09c, 0x10ff, 0xc09c, 0x21, 0 + .dw 0x1140, 0xc09c, 0x117f, 0xc09c, 0x21, 0 + .dw 0x11c0, 0xc09c, 0x11ff, 0xc09c, 0x21, 0 + .dw 0x1240, 0xc09c, 0x127f, 0xc09c, 0x21, 0 + .dw 0x12c0, 0xc09c, 0x12ff, 0xc09c, 0x21, 0 + .dw 0x1340, 0xc09c, 0x137f, 0xc09c, 0x21, 0 + .dw 0x13c0, 0xc09c, 0x13ff, 0xc09c, 0x21, 0 + .dw 0x1440, 0xc09c, 0x147f, 0xc09c, 0x21, 0 + .dw 0x14c0, 0xc09c, 0x14ff, 0xc09c, 0x21, 0 + .dw 0x1540, 0xc09c, 0x157f, 0xc09c, 0x21, 0 + .dw 0x15c0, 0xc09c, 0x15ff, 0xc09c, 0x21, 0 + .dw 0x1640, 0xc09c, 0x167f, 0xc09c, 0x21, 0 + .dw 0x16c0, 0xc09c, 0x16ff, 0xc09c, 0x21, 0 + .dw 0x1740, 0xc09c, 0x177f, 0xc09c, 0x21, 0 + .dw 0x17c0, 0xc09c, 0x17ff, 0xc09c, 0x21, 0 + .dw 0x1840, 0xc09c, 0x187f, 0xc09c, 0x21, 0 + .dw 0x18c0, 0xc09c, 0x18ff, 0xc09c, 0x21, 0 + .dw 0x1940, 0xc09c, 0x197f, 0xc09c, 0x21, 0 + .dw 0x19c0, 0xc09c, 0x1fff, 0xc09c, 0x21, 0 + .dw 0x2040, 0xc09c, 0x207f, 0xc09c, 0x21, 0 + .dw 0x20c0, 0xc09c, 0x20ff, 0xc09c, 0x21, 0 + .dw 0x2140, 0xc09c, 0x217f, 0xc09c, 0x21, 0 + .dw 0x21c0, 0xc09c, 0x21ff, 0xc09c, 0x21, 0 + .dw 0x2240, 0xc09c, 0x227f, 0xc09c, 0x21, 0 + .dw 0x22c0, 0xc09c, 0x22ff, 0xc09c, 0x21, 0 + .dw 0x2340, 0xc09c, 0x237f, 0xc09c, 0x21, 0 + .dw 0x23c0, 0xc09c, 0x23ff, 0xc09c, 0x21, 0 + .dw 0x2440, 0xc09c, 0x247f, 0xc09c, 0x21, 0 + .dw 0x24c0, 0xc09c, 0x24ff, 0xc09c, 0x21, 0 + .dw 0x2540, 0xc09c, 0x257f, 0xc09c, 0x21, 0 + .dw 0x25c0, 0xc09c, 0x25ff, 0xc09c, 0x21, 0 + .dw 0x2640, 0xc09c, 0x267f, 0xc09c, 0x21, 0 + .dw 0x26c0, 0xc09c, 0x26ff, 0xc09c, 0x21, 0 + .dw 0x2740, 0xc09c, 0x277f, 0xc09c, 0x21, 0 + .dw 0x27c0, 0xc09c, 0x27ff, 0xc09c, 0x21, 0 + .dw 0x2840, 0xc09c, 0x287f, 0xc09c, 0x21, 0 + .dw 0x28c0, 0xc09c, 0x28ff, 0xc09c, 0x21, 0 + .dw 0x2940, 0xc09c, 0x297f, 0xc09c, 0x21, 0 + .dw 0x29c0, 0xc09c, 0x29ff, 0xc09c, 0x21, 0 + .dw 0x2a40, 0xc09c, 0x2a7f, 0xc09c, 0x21, 0 + .dw 0x2ac0, 0xc09c, 0x2aff, 0xc09c, 0x21, 0 + .dw 0x2b40, 0xc09c, 0x2b7f, 0xc09c, 0x21, 0 + .dw 0x2bc0, 0xc09c, 0x2bff, 0xc09c, 0x21, 0 + .dw 0x2c40, 0xc09c, 0x2c7f, 0xc09c, 0x21, 0 + .dw 0x2cc0, 0xc09c, 0x2cff, 0xc09c, 0x21, 0 + .dw 0x2d40, 0xc09c, 0x2d7f, 0xc09c, 0x21, 0 + .dw 0x2dc0, 0xc09c, 0x2dff, 0xc09c, 0x21, 0 + .dw 0x2e40, 0xc09c, 0x2e7f, 0xc09c, 0x21, 0 + .dw 0x2ec0, 0xc09c, 0x2eff, 0xc09c, 0x21, 0 + .dw 0x2f40, 0xc09c, 0x2f7f, 0xc09c, 0x21, 0 + .dw 0x2fc0, 0xc09c, 0x2fff, 0xc09c, 0x21, 0 + .dw 0x3040, 0xc09c, 0x307f, 0xc09c, 0x21, 0 + .dw 0x30c0, 0xc09c, 0x30ff, 0xc09c, 0x21, 0 + .dw 0x3140, 0xc09c, 0x317f, 0xc09c, 0x21, 0 + .dw 0x31c0, 0xc09c, 0x31ff, 0xc09c, 0x21, 0 + .dw 0x3240, 0xc09c, 0x327f, 0xc09c, 0x21, 0 + .dw 0x32c0, 0xc09c, 0x32ff, 0xc09c, 0x21, 0 + .dw 0x3340, 0xc09c, 0x337f, 0xc09c, 0x21, 0 + .dw 0x33c0, 0xc09c, 0x33ff, 0xc09c, 0x21, 0 + .dw 0x3440, 0xc09c, 0x347f, 0xc09c, 0x21, 0 + .dw 0x34c0, 0xc09c, 0x34ff, 0xc09c, 0x21, 0 + .dw 0x3540, 0xc09c, 0x357f, 0xc09c, 0x21, 0 + .dw 0x35c0, 0xc09c, 0x35ff, 0xc09c, 0x21, 0 + .dw 0x3640, 0xc09c, 0x367f, 0xc09c, 0x21, 0 + .dw 0x36c0, 0xc09c, 0x36ff, 0xc09c, 0x21, 0 + .dw 0x3740, 0xc09c, 0x377f, 0xc09c, 0x21, 0 + .dw 0x37c0, 0xc09c, 0x37ff, 0xc09c, 0x21, 0 + .dw 0x3840, 0xc09c, 0x387f, 0xc09c, 0x21, 0 + .dw 0x38c0, 0xc09c, 0x38ff, 0xc09c, 0x21, 0 + .dw 0x3940, 0xc09c, 0x397f, 0xc09c, 0x21, 0 + .dw 0x39c0, 0xc09c, 0x3fff, 0xc09c, 0x21, 0 + .dw 0x4040, 0xc09c, 0x407f, 0xc09c, 0x21, 0 + .dw 0x40c0, 0xc09c, 0x40ff, 0xc09c, 0x21, 0 + .dw 0x4140, 0xc09c, 0x417f, 0xc09c, 0x21, 0 + .dw 0x41c0, 0xc09c, 0x41ff, 0xc09c, 0x21, 0 + .dw 0x4240, 0xc09c, 0x427f, 0xc09c, 0x21, 0 + .dw 0x42c0, 0xc09c, 0x42ff, 0xc09c, 0x21, 0 + .dw 0x4340, 0xc09c, 0x437f, 0xc09c, 0x21, 0 + .dw 0x43c0, 0xc09c, 0x43ff, 0xc09c, 0x21, 0 + .dw 0x4440, 0xc09c, 0x447f, 0xc09c, 0x21, 0 + .dw 0x44c0, 0xc09c, 0x44ff, 0xc09c, 0x21, 0 + .dw 0x4540, 0xc09c, 0x457f, 0xc09c, 0x21, 0 + .dw 0x45c0, 0xc09c, 0x45ff, 0xc09c, 0x21, 0 + .dw 0x4640, 0xc09c, 0x467f, 0xc09c, 0x21, 0 + .dw 0x46c0, 0xc09c, 0x46ff, 0xc09c, 0x21, 0 + .dw 0x4740, 0xc09c, 0x477f, 0xc09c, 0x21, 0 + .dw 0x47c0, 0xc09c, 0x47ff, 0xc09c, 0x21, 0 + .dw 0x4840, 0xc09c, 0x487f, 0xc09c, 0x21, 0 + .dw 0x48c0, 0xc09c, 0x48ff, 0xc09c, 0x21, 0 + .dw 0x4940, 0xc09c, 0x497f, 0xc09c, 0x21, 0 + .dw 0x49c0, 0xc09c, 0x49ff, 0xc09c, 0x21, 0 + .dw 0x4a40, 0xc09c, 0x4a7f, 0xc09c, 0x21, 0 + .dw 0x4ac0, 0xc09c, 0x4aff, 0xc09c, 0x21, 0 + .dw 0x4b40, 0xc09c, 0x4b7f, 0xc09c, 0x21, 0 + .dw 0x4bc0, 0xc09c, 0x4bff, 0xc09c, 0x21, 0 + .dw 0x4c40, 0xc09c, 0x4c7f, 0xc09c, 0x21, 0 + .dw 0x4cc0, 0xc09c, 0x4cff, 0xc09c, 0x21, 0 + .dw 0x4d40, 0xc09c, 0x4d7f, 0xc09c, 0x21, 0 + .dw 0x4dc0, 0xc09c, 0x4dff, 0xc09c, 0x21, 0 + .dw 0x4e40, 0xc09c, 0x4e7f, 0xc09c, 0x21, 0 + .dw 0x4ec0, 0xc09c, 0x4eff, 0xc09c, 0x21, 0 + .dw 0x4f40, 0xc09c, 0x4f7f, 0xc09c, 0x21, 0 + .dw 0x4fc0, 0xc09c, 0x4fff, 0xc09c, 0x21, 0 + .dw 0x5040, 0xc09c, 0x507f, 0xc09c, 0x21, 0 + .dw 0x50c0, 0xc09c, 0x50ff, 0xc09c, 0x21, 0 + .dw 0x5140, 0xc09c, 0x517f, 0xc09c, 0x21, 0 + .dw 0x51c0, 0xc09c, 0x51ff, 0xc09c, 0x21, 0 + .dw 0x5240, 0xc09c, 0x527f, 0xc09c, 0x21, 0 + .dw 0x52c0, 0xc09c, 0x52ff, 0xc09c, 0x21, 0 + .dw 0x5340, 0xc09c, 0x537f, 0xc09c, 0x21, 0 + .dw 0x53c0, 0xc09c, 0x53ff, 0xc09c, 0x21, 0 + .dw 0x5440, 0xc09c, 0x547f, 0xc09c, 0x21, 0 + .dw 0x54c0, 0xc09c, 0x54ff, 0xc09c, 0x21, 0 + .dw 0x5540, 0xc09c, 0x557f, 0xc09c, 0x21, 0 + .dw 0x55c0, 0xc09c, 0x55ff, 0xc09c, 0x21, 0 + .dw 0x5640, 0xc09c, 0x567f, 0xc09c, 0x21, 0 + .dw 0x56c0, 0xc09c, 0x56ff, 0xc09c, 0x21, 0 + .dw 0x5740, 0xc09c, 0x577f, 0xc09c, 0x21, 0 + .dw 0x57c0, 0xc09c, 0x57ff, 0xc09c, 0x21, 0 + .dw 0x5840, 0xc09c, 0x587f, 0xc09c, 0x21, 0 + .dw 0x58c0, 0xc09c, 0x58ff, 0xc09c, 0x21, 0 + .dw 0x5940, 0xc09c, 0x597f, 0xc09c, 0x21, 0 + .dw 0x59c0, 0xc09c, 0x5fff, 0xc09c, 0x21, 0 + .dw 0x6040, 0xc09c, 0x607f, 0xc09c, 0x21, 0 + .dw 0x60c0, 0xc09c, 0x60ff, 0xc09c, 0x21, 0 + .dw 0x6140, 0xc09c, 0x617f, 0xc09c, 0x21, 0 + .dw 0x61c0, 0xc09c, 0x61ff, 0xc09c, 0x21, 0 + .dw 0x6240, 0xc09c, 0x627f, 0xc09c, 0x21, 0 + .dw 0x62c0, 0xc09c, 0x62ff, 0xc09c, 0x21, 0 + .dw 0x6340, 0xc09c, 0x637f, 0xc09c, 0x21, 0 + .dw 0x63c0, 0xc09c, 0x63ff, 0xc09c, 0x21, 0 + .dw 0x6440, 0xc09c, 0x647f, 0xc09c, 0x21, 0 + .dw 0x64c0, 0xc09c, 0x64ff, 0xc09c, 0x21, 0 + .dw 0x6540, 0xc09c, 0x657f, 0xc09c, 0x21, 0 + .dw 0x65c0, 0xc09c, 0x65ff, 0xc09c, 0x21, 0 + .dw 0x6640, 0xc09c, 0x667f, 0xc09c, 0x21, 0 + .dw 0x66c0, 0xc09c, 0x66ff, 0xc09c, 0x21, 0 + .dw 0x6740, 0xc09c, 0x677f, 0xc09c, 0x21, 0 + .dw 0x67c0, 0xc09c, 0x67ff, 0xc09c, 0x21, 0 + .dw 0x6840, 0xc09c, 0x687f, 0xc09c, 0x21, 0 + .dw 0x68c0, 0xc09c, 0x68ff, 0xc09c, 0x21, 0 + .dw 0x6940, 0xc09c, 0x697f, 0xc09c, 0x21, 0 + .dw 0x69c0, 0xc09c, 0x69ff, 0xc09c, 0x21, 0 + .dw 0x6a40, 0xc09c, 0x6a7f, 0xc09c, 0x21, 0 + .dw 0x6ac0, 0xc09c, 0x6aff, 0xc09c, 0x21, 0 + .dw 0x6b40, 0xc09c, 0x6b7f, 0xc09c, 0x21, 0 + .dw 0x6bc0, 0xc09c, 0x6bff, 0xc09c, 0x21, 0 + .dw 0x6c40, 0xc09c, 0x6c7f, 0xc09c, 0x21, 0 + .dw 0x6cc0, 0xc09c, 0x6cff, 0xc09c, 0x21, 0 + .dw 0x6d40, 0xc09c, 0x6d7f, 0xc09c, 0x21, 0 + .dw 0x6dc0, 0xc09c, 0x6dff, 0xc09c, 0x21, 0 + .dw 0x6e40, 0xc09c, 0x6e7f, 0xc09c, 0x21, 0 + .dw 0x6ec0, 0xc09c, 0x6eff, 0xc09c, 0x21, 0 + .dw 0x6f40, 0xc09c, 0x6f7f, 0xc09c, 0x21, 0 + .dw 0x6fc0, 0xc09c, 0x6fff, 0xc09c, 0x21, 0 + .dw 0x7040, 0xc09c, 0x707f, 0xc09c, 0x21, 0 + .dw 0x70c0, 0xc09c, 0x70ff, 0xc09c, 0x21, 0 + .dw 0x7140, 0xc09c, 0x717f, 0xc09c, 0x21, 0 + .dw 0x71c0, 0xc09c, 0x71ff, 0xc09c, 0x21, 0 + .dw 0x7240, 0xc09c, 0x727f, 0xc09c, 0x21, 0 + .dw 0x72c0, 0xc09c, 0x72ff, 0xc09c, 0x21, 0 + .dw 0x7340, 0xc09c, 0x737f, 0xc09c, 0x21, 0 + .dw 0x73c0, 0xc09c, 0x73ff, 0xc09c, 0x21, 0 + .dw 0x7440, 0xc09c, 0x747f, 0xc09c, 0x21, 0 + .dw 0x74c0, 0xc09c, 0x74ff, 0xc09c, 0x21, 0 + .dw 0x7540, 0xc09c, 0x757f, 0xc09c, 0x21, 0 + .dw 0x75c0, 0xc09c, 0x75ff, 0xc09c, 0x21, 0 + .dw 0x7640, 0xc09c, 0x767f, 0xc09c, 0x21, 0 + .dw 0x76c0, 0xc09c, 0x76ff, 0xc09c, 0x21, 0 + .dw 0x7740, 0xc09c, 0x777f, 0xc09c, 0x21, 0 + .dw 0x77c0, 0xc09c, 0x77ff, 0xc09c, 0x21, 0 + .dw 0x7840, 0xc09c, 0x787f, 0xc09c, 0x21, 0 + .dw 0x78c0, 0xc09c, 0x78ff, 0xc09c, 0x21, 0 + .dw 0x7940, 0xc09c, 0x797f, 0xc09c, 0x21, 0 + .dw 0x79c0, 0xc09c, 0x7fff, 0xc09c, 0x21, 0 + .dw 0x8040, 0xc09c, 0x807f, 0xc09c, 0x21, 0 + .dw 0x80c0, 0xc09c, 0x80ff, 0xc09c, 0x21, 0 + .dw 0x8140, 0xc09c, 0x817f, 0xc09c, 0x21, 0 + .dw 0x81c0, 0xc09c, 0x81ff, 0xc09c, 0x21, 0 + .dw 0x8240, 0xc09c, 0x827f, 0xc09c, 0x21, 0 + .dw 0x82c0, 0xc09c, 0x82ff, 0xc09c, 0x21, 0 + .dw 0x8340, 0xc09c, 0x837f, 0xc09c, 0x21, 0 + .dw 0x83c0, 0xc09c, 0x83ff, 0xc09c, 0x21, 0 + .dw 0x8440, 0xc09c, 0x847f, 0xc09c, 0x21, 0 + .dw 0x84c0, 0xc09c, 0x84ff, 0xc09c, 0x21, 0 + .dw 0x8540, 0xc09c, 0x857f, 0xc09c, 0x21, 0 + .dw 0x85c0, 0xc09c, 0x85ff, 0xc09c, 0x21, 0 + .dw 0x8640, 0xc09c, 0x867f, 0xc09c, 0x21, 0 + .dw 0x86c0, 0xc09c, 0x86ff, 0xc09c, 0x21, 0 + .dw 0x8740, 0xc09c, 0x877f, 0xc09c, 0x21, 0 + .dw 0x87c0, 0xc09c, 0x87ff, 0xc09c, 0x21, 0 + .dw 0x8840, 0xc09c, 0x887f, 0xc09c, 0x21, 0 + .dw 0x88c0, 0xc09c, 0x88ff, 0xc09c, 0x21, 0 + .dw 0x8940, 0xc09c, 0x897f, 0xc09c, 0x21, 0 + .dw 0x89c0, 0xc09c, 0x89ff, 0xc09c, 0x21, 0 + .dw 0x8a40, 0xc09c, 0x8a7f, 0xc09c, 0x21, 0 + .dw 0x8ac0, 0xc09c, 0x8aff, 0xc09c, 0x21, 0 + .dw 0x8b40, 0xc09c, 0x8b7f, 0xc09c, 0x21, 0 + .dw 0x8bc0, 0xc09c, 0x8bff, 0xc09c, 0x21, 0 + .dw 0x8c40, 0xc09c, 0x8c7f, 0xc09c, 0x21, 0 + .dw 0x8cc0, 0xc09c, 0x8cff, 0xc09c, 0x21, 0 + .dw 0x8d40, 0xc09c, 0x8d7f, 0xc09c, 0x21, 0 + .dw 0x8dc0, 0xc09c, 0x8dff, 0xc09c, 0x21, 0 + .dw 0x8e40, 0xc09c, 0x8e7f, 0xc09c, 0x21, 0 + .dw 0x8ec0, 0xc09c, 0x8eff, 0xc09c, 0x21, 0 + .dw 0x8f40, 0xc09c, 0x8f7f, 0xc09c, 0x21, 0 + .dw 0x8fc0, 0xc09c, 0x8fff, 0xc09c, 0x21, 0 + .dw 0x9040, 0xc09c, 0x907f, 0xc09c, 0x21, 0 + .dw 0x90c0, 0xc09c, 0x90ff, 0xc09c, 0x21, 0 + .dw 0x9140, 0xc09c, 0x917f, 0xc09c, 0x21, 0 + .dw 0x91c0, 0xc09c, 0x91ff, 0xc09c, 0x21, 0 + .dw 0x9240, 0xc09c, 0x927f, 0xc09c, 0x21, 0 + .dw 0x92c0, 0xc09c, 0x92ff, 0xc09c, 0x21, 0 + .dw 0x9340, 0xc09c, 0x937f, 0xc09c, 0x21, 0 + .dw 0x93c0, 0xc09c, 0x93ff, 0xc09c, 0x21, 0 + .dw 0x9440, 0xc09c, 0x947f, 0xc09c, 0x21, 0 + .dw 0x94c0, 0xc09c, 0x94ff, 0xc09c, 0x21, 0 + .dw 0x9540, 0xc09c, 0x957f, 0xc09c, 0x21, 0 + .dw 0x95c0, 0xc09c, 0x95ff, 0xc09c, 0x21, 0 + .dw 0x9640, 0xc09c, 0x967f, 0xc09c, 0x21, 0 + .dw 0x96c0, 0xc09c, 0x96ff, 0xc09c, 0x21, 0 + .dw 0x9740, 0xc09c, 0x977f, 0xc09c, 0x21, 0 + .dw 0x97c0, 0xc09c, 0x97ff, 0xc09c, 0x21, 0 + .dw 0x9840, 0xc09c, 0x987f, 0xc09c, 0x21, 0 + .dw 0x98c0, 0xc09c, 0x98ff, 0xc09c, 0x21, 0 + .dw 0x9940, 0xc09c, 0x997f, 0xc09c, 0x21, 0 + .dw 0x99c0, 0xc09c, 0x9fff, 0xc09c, 0x21, 0 + .dw 0xa040, 0xc09c, 0xa07f, 0xc09c, 0x21, 0 + .dw 0xa0c0, 0xc09c, 0xa0ff, 0xc09c, 0x21, 0 + .dw 0xa140, 0xc09c, 0xa17f, 0xc09c, 0x21, 0 + .dw 0xa1c0, 0xc09c, 0xa1ff, 0xc09c, 0x21, 0 + .dw 0xa240, 0xc09c, 0xa27f, 0xc09c, 0x21, 0 + .dw 0xa2c0, 0xc09c, 0xa2ff, 0xc09c, 0x21, 0 + .dw 0xa340, 0xc09c, 0xa37f, 0xc09c, 0x21, 0 + .dw 0xa3c0, 0xc09c, 0xa3ff, 0xc09c, 0x21, 0 + .dw 0xa440, 0xc09c, 0xa47f, 0xc09c, 0x21, 0 + .dw 0xa4c0, 0xc09c, 0xa4ff, 0xc09c, 0x21, 0 + .dw 0xa540, 0xc09c, 0xa57f, 0xc09c, 0x21, 0 + .dw 0xa5c0, 0xc09c, 0xa5ff, 0xc09c, 0x21, 0 + .dw 0xa640, 0xc09c, 0xa67f, 0xc09c, 0x21, 0 + .dw 0xa6c0, 0xc09c, 0xa6ff, 0xc09c, 0x21, 0 + .dw 0xa740, 0xc09c, 0xa77f, 0xc09c, 0x21, 0 + .dw 0xa7c0, 0xc09c, 0xa7ff, 0xc09c, 0x21, 0 + .dw 0xa840, 0xc09c, 0xa87f, 0xc09c, 0x21, 0 + .dw 0xa8c0, 0xc09c, 0xa8ff, 0xc09c, 0x21, 0 + .dw 0xa940, 0xc09c, 0xa97f, 0xc09c, 0x21, 0 + .dw 0xa9c0, 0xc09c, 0xa9ff, 0xc09c, 0x21, 0 + .dw 0xaa40, 0xc09c, 0xaa7f, 0xc09c, 0x21, 0 + .dw 0xaac0, 0xc09c, 0xaaff, 0xc09c, 0x21, 0 + .dw 0xab40, 0xc09c, 0xab7f, 0xc09c, 0x21, 0 + .dw 0xabc0, 0xc09c, 0xabff, 0xc09c, 0x21, 0 + .dw 0xac40, 0xc09c, 0xac7f, 0xc09c, 0x21, 0 + .dw 0xacc0, 0xc09c, 0xacff, 0xc09c, 0x21, 0 + .dw 0xad40, 0xc09c, 0xad7f, 0xc09c, 0x21, 0 + .dw 0xadc0, 0xc09c, 0xadff, 0xc09c, 0x21, 0 + .dw 0xae40, 0xc09c, 0xae7f, 0xc09c, 0x21, 0 + .dw 0xaec0, 0xc09c, 0xaeff, 0xc09c, 0x21, 0 + .dw 0xaf40, 0xc09c, 0xaf7f, 0xc09c, 0x21, 0 + .dw 0xafc0, 0xc09c, 0xafff, 0xc09c, 0x21, 0 + .dw 0xb040, 0xc09c, 0xb07f, 0xc09c, 0x21, 0 + .dw 0xb0c0, 0xc09c, 0xb0ff, 0xc09c, 0x21, 0 + .dw 0xb140, 0xc09c, 0xb17f, 0xc09c, 0x21, 0 + .dw 0xb1c0, 0xc09c, 0xb1ff, 0xc09c, 0x21, 0 + .dw 0xb240, 0xc09c, 0xb27f, 0xc09c, 0x21, 0 + .dw 0xb2c0, 0xc09c, 0xb2ff, 0xc09c, 0x21, 0 + .dw 0xb340, 0xc09c, 0xb37f, 0xc09c, 0x21, 0 + .dw 0xb3c0, 0xc09c, 0xb3ff, 0xc09c, 0x21, 0 + .dw 0xb440, 0xc09c, 0xb47f, 0xc09c, 0x21, 0 + .dw 0xb4c0, 0xc09c, 0xb4ff, 0xc09c, 0x21, 0 + .dw 0xb540, 0xc09c, 0xb57f, 0xc09c, 0x21, 0 + .dw 0xb5c0, 0xc09c, 0xb5ff, 0xc09c, 0x21, 0 + .dw 0xb640, 0xc09c, 0xb67f, 0xc09c, 0x21, 0 + .dw 0xb6c0, 0xc09c, 0xb6ff, 0xc09c, 0x21, 0 + .dw 0xb740, 0xc09c, 0xb77f, 0xc09c, 0x21, 0 + .dw 0xb7c0, 0xc09c, 0xb7ff, 0xc09c, 0x21, 0 + .dw 0xb840, 0xc09c, 0xb87f, 0xc09c, 0x21, 0 + .dw 0xb8c0, 0xc09c, 0xb8ff, 0xc09c, 0x21, 0 + .dw 0xb940, 0xc09c, 0xb97f, 0xc09c, 0x21, 0 + .dw 0xb9c0, 0xc09c, 0xbfff, 0xc09c, 0x21, 0 + .dw 0xc040, 0xc09c, 0xc07f, 0xc09c, 0x21, 0 + .dw 0xc0c0, 0xc09c, 0xc0ff, 0xc09c, 0x21, 0 + .dw 0xc140, 0xc09c, 0xc17f, 0xc09c, 0x21, 0 + .dw 0xc1c0, 0xc09c, 0xc1ff, 0xc09c, 0x21, 0 + .dw 0xc240, 0xc09c, 0xc27f, 0xc09c, 0x21, 0 + .dw 0xc2c0, 0xc09c, 0xc2ff, 0xc09c, 0x21, 0 + .dw 0xc340, 0xc09c, 0xc37f, 0xc09c, 0x21, 0 + .dw 0xc3c0, 0xc09c, 0xc3ff, 0xc09c, 0x21, 0 + .dw 0xc440, 0xc09c, 0xc47f, 0xc09c, 0x21, 0 + .dw 0xc4c0, 0xc09c, 0xc4ff, 0xc09c, 0x21, 0 + .dw 0xc540, 0xc09c, 0xc57f, 0xc09c, 0x21, 0 + .dw 0xc5c0, 0xc09c, 0xc5ff, 0xc09c, 0x21, 0 + .dw 0xc640, 0xc09c, 0xc67f, 0xc09c, 0x21, 0 + .dw 0xc6c0, 0xc09c, 0xc6ff, 0xc09c, 0x21, 0 + .dw 0xc740, 0xc09c, 0xc77f, 0xc09c, 0x21, 0 + .dw 0xc7c0, 0xc09c, 0xc7ff, 0xc09c, 0x21, 0 + .dw 0xc840, 0xc09c, 0xc87f, 0xc09c, 0x21, 0 + .dw 0xc8c0, 0xc09c, 0xc8ff, 0xc09c, 0x21, 0 + .dw 0xc940, 0xc09c, 0xc97f, 0xc09c, 0x21, 0 + .dw 0xc9c0, 0xc09c, 0xc9ff, 0xc09c, 0x21, 0 + .dw 0xca40, 0xc09c, 0xca7f, 0xc09c, 0x21, 0 + .dw 0xcac0, 0xc09c, 0xcaff, 0xc09c, 0x21, 0 + .dw 0xcb40, 0xc09c, 0xcb7f, 0xc09c, 0x21, 0 + .dw 0xcbc0, 0xc09c, 0xcbff, 0xc09c, 0x21, 0 + .dw 0xcc40, 0xc09c, 0xcc7f, 0xc09c, 0x21, 0 + .dw 0xccc0, 0xc09c, 0xccff, 0xc09c, 0x21, 0 + .dw 0xcd40, 0xc09c, 0xcd7f, 0xc09c, 0x21, 0 + .dw 0xcdc0, 0xc09c, 0xcdff, 0xc09c, 0x21, 0 + .dw 0xce40, 0xc09c, 0xce7f, 0xc09c, 0x21, 0 + .dw 0xcec0, 0xc09c, 0xceff, 0xc09c, 0x21, 0 + .dw 0xcf40, 0xc09c, 0xcf7f, 0xc09c, 0x21, 0 + .dw 0xcfc0, 0xc09c, 0xcfff, 0xc09c, 0x21, 0 + .dw 0xd040, 0xc09c, 0xd07f, 0xc09c, 0x21, 0 + .dw 0xd0c0, 0xc09c, 0xd0ff, 0xc09c, 0x21, 0 + .dw 0xd140, 0xc09c, 0xd17f, 0xc09c, 0x21, 0 + .dw 0xd1c0, 0xc09c, 0xd1ff, 0xc09c, 0x21, 0 + .dw 0xd240, 0xc09c, 0xd27f, 0xc09c, 0x21, 0 + .dw 0xd2c0, 0xc09c, 0xd2ff, 0xc09c, 0x21, 0 + .dw 0xd340, 0xc09c, 0xd37f, 0xc09c, 0x21, 0 + .dw 0xd3c0, 0xc09c, 0xd3ff, 0xc09c, 0x21, 0 + .dw 0xd440, 0xc09c, 0xd47f, 0xc09c, 0x21, 0 + .dw 0xd4c0, 0xc09c, 0xd4ff, 0xc09c, 0x21, 0 + .dw 0xd540, 0xc09c, 0xd57f, 0xc09c, 0x21, 0 + .dw 0xd5c0, 0xc09c, 0xd5ff, 0xc09c, 0x21, 0 + .dw 0xd640, 0xc09c, 0xd67f, 0xc09c, 0x21, 0 + .dw 0xd6c0, 0xc09c, 0xd6ff, 0xc09c, 0x21, 0 + .dw 0xd740, 0xc09c, 0xd77f, 0xc09c, 0x21, 0 + .dw 0xd7c0, 0xc09c, 0xd7ff, 0xc09c, 0x21, 0 + .dw 0xd840, 0xc09c, 0xd87f, 0xc09c, 0x21, 0 + .dw 0xd8c0, 0xc09c, 0xd8ff, 0xc09c, 0x21, 0 + .dw 0xd940, 0xc09c, 0xd97f, 0xc09c, 0x21, 0 + .dw 0xd9c0, 0xc09c, 0xdfff, 0xc09c, 0x21, 0 + .dw 0xe040, 0xc09c, 0xe07f, 0xc09c, 0x21, 0 + .dw 0xe0c0, 0xc09c, 0xe0ff, 0xc09c, 0x21, 0 + .dw 0xe140, 0xc09c, 0xe17f, 0xc09c, 0x21, 0 + .dw 0xe1c0, 0xc09c, 0xe1ff, 0xc09c, 0x21, 0 + .dw 0xe240, 0xc09c, 0xe27f, 0xc09c, 0x21, 0 + .dw 0xe2c0, 0xc09c, 0xe2ff, 0xc09c, 0x21, 0 + .dw 0xe340, 0xc09c, 0xe37f, 0xc09c, 0x21, 0 + .dw 0xe3c0, 0xc09c, 0xe3ff, 0xc09c, 0x21, 0 + .dw 0xe440, 0xc09c, 0xe47f, 0xc09c, 0x21, 0 + .dw 0xe4c0, 0xc09c, 0xe4ff, 0xc09c, 0x21, 0 + .dw 0xe540, 0xc09c, 0xe57f, 0xc09c, 0x21, 0 + .dw 0xe5c0, 0xc09c, 0xe5ff, 0xc09c, 0x21, 0 + .dw 0xe640, 0xc09c, 0xe67f, 0xc09c, 0x21, 0 + .dw 0xe6c0, 0xc09c, 0xe6ff, 0xc09c, 0x21, 0 + .dw 0xe740, 0xc09c, 0xe77f, 0xc09c, 0x21, 0 + .dw 0xe7c0, 0xc09c, 0xe7ff, 0xc09c, 0x21, 0 + .dw 0xe840, 0xc09c, 0xe87f, 0xc09c, 0x21, 0 + .dw 0xe8c0, 0xc09c, 0xe8ff, 0xc09c, 0x21, 0 + .dw 0xe940, 0xc09c, 0xe97f, 0xc09c, 0x21, 0 + .dw 0xe9c0, 0xc09c, 0xe9ff, 0xc09c, 0x21, 0 + .dw 0xea40, 0xc09c, 0xea7f, 0xc09c, 0x21, 0 + .dw 0xeac0, 0xc09c, 0xeaff, 0xc09c, 0x21, 0 + .dw 0xeb40, 0xc09c, 0xeb7f, 0xc09c, 0x21, 0 + .dw 0xebc0, 0xc09c, 0xebff, 0xc09c, 0x21, 0 + .dw 0xec40, 0xc09c, 0xec7f, 0xc09c, 0x21, 0 + .dw 0xecc0, 0xc09c, 0xecff, 0xc09c, 0x21, 0 + .dw 0xed40, 0xc09c, 0xed7f, 0xc09c, 0x21, 0 + .dw 0xedc0, 0xc09c, 0xedff, 0xc09c, 0x21, 0 + .dw 0xee40, 0xc09c, 0xee7f, 0xc09c, 0x21, 0 + .dw 0xeec0, 0xc09c, 0xeeff, 0xc09c, 0x21, 0 + .dw 0xef40, 0xc09c, 0xef7f, 0xc09c, 0x21, 0 + .dw 0xefc0, 0xc09c, 0xefff, 0xc09c, 0x21, 0 + .dw 0xf040, 0xc09c, 0xf07f, 0xc09c, 0x21, 0 + .dw 0xf0c0, 0xc09c, 0xf0ff, 0xc09c, 0x21, 0 + .dw 0xf140, 0xc09c, 0xf17f, 0xc09c, 0x21, 0 + .dw 0xf1c0, 0xc09c, 0xf1ff, 0xc09c, 0x21, 0 + .dw 0xf240, 0xc09c, 0xf27f, 0xc09c, 0x21, 0 + .dw 0xf2c0, 0xc09c, 0xf2ff, 0xc09c, 0x21, 0 + .dw 0xf340, 0xc09c, 0xf37f, 0xc09c, 0x21, 0 + .dw 0xf3c0, 0xc09c, 0xf3ff, 0xc09c, 0x21, 0 + .dw 0xf440, 0xc09c, 0xf47f, 0xc09c, 0x21, 0 + .dw 0xf4c0, 0xc09c, 0xf4ff, 0xc09c, 0x21, 0 + .dw 0xf540, 0xc09c, 0xf57f, 0xc09c, 0x21, 0 + .dw 0xf5c0, 0xc09c, 0xf5ff, 0xc09c, 0x21, 0 + .dw 0xf640, 0xc09c, 0xf67f, 0xc09c, 0x21, 0 + .dw 0xf6c0, 0xc09c, 0xf6ff, 0xc09c, 0x21, 0 + .dw 0xf740, 0xc09c, 0xf77f, 0xc09c, 0x21, 0 + .dw 0xf7c0, 0xc09c, 0xf7ff, 0xc09c, 0x21, 0 + .dw 0xf840, 0xc09c, 0xf87f, 0xc09c, 0x21, 0 + .dw 0xf8c0, 0xc09c, 0xf8ff, 0xc09c, 0x21, 0 + .dw 0xf940, 0xc09c, 0xf97f, 0xc09c, 0x21, 0 + .dw 0xf9c0, 0xc09c, 0xffff, 0xc09c, 0x21, 0 + .dw 0x0040, 0xc09d, 0x007f, 0xc09d, 0x21, 0 + .dw 0x00c0, 0xc09d, 0x00ff, 0xc09d, 0x21, 0 + .dw 0x0140, 0xc09d, 0x017f, 0xc09d, 0x21, 0 + .dw 0x01c0, 0xc09d, 0x01ff, 0xc09d, 0x21, 0 + .dw 0x0240, 0xc09d, 0x027f, 0xc09d, 0x21, 0 + .dw 0x02c0, 0xc09d, 0x02ff, 0xc09d, 0x21, 0 + .dw 0x0340, 0xc09d, 0x037f, 0xc09d, 0x21, 0 + .dw 0x03c0, 0xc09d, 0x03ff, 0xc09d, 0x21, 0 + .dw 0x0440, 0xc09d, 0x047f, 0xc09d, 0x21, 0 + .dw 0x04c0, 0xc09d, 0x04ff, 0xc09d, 0x21, 0 + .dw 0x0540, 0xc09d, 0x057f, 0xc09d, 0x21, 0 + .dw 0x05c0, 0xc09d, 0x05ff, 0xc09d, 0x21, 0 + .dw 0x0640, 0xc09d, 0x067f, 0xc09d, 0x21, 0 + .dw 0x06c0, 0xc09d, 0x06ff, 0xc09d, 0x21, 0 + .dw 0x0740, 0xc09d, 0x077f, 0xc09d, 0x21, 0 + .dw 0x07c0, 0xc09d, 0x07ff, 0xc09d, 0x21, 0 + .dw 0x0840, 0xc09d, 0x087f, 0xc09d, 0x21, 0 + .dw 0x08c0, 0xc09d, 0x08ff, 0xc09d, 0x21, 0 + .dw 0x0940, 0xc09d, 0x097f, 0xc09d, 0x21, 0 + .dw 0x09c0, 0xc09d, 0x09ff, 0xc09d, 0x21, 0 + .dw 0x0a40, 0xc09d, 0x0a7f, 0xc09d, 0x21, 0 + .dw 0x0ac0, 0xc09d, 0x0aff, 0xc09d, 0x21, 0 + .dw 0x0b40, 0xc09d, 0x0b7f, 0xc09d, 0x21, 0 + .dw 0x0bc0, 0xc09d, 0x0bff, 0xc09d, 0x21, 0 + .dw 0x0c40, 0xc09d, 0x0c7f, 0xc09d, 0x21, 0 + .dw 0x0cc0, 0xc09d, 0x0cff, 0xc09d, 0x21, 0 + .dw 0x0d40, 0xc09d, 0x0d7f, 0xc09d, 0x21, 0 + .dw 0x0dc0, 0xc09d, 0x0dff, 0xc09d, 0x21, 0 + .dw 0x0e40, 0xc09d, 0x0e7f, 0xc09d, 0x21, 0 + .dw 0x0ec0, 0xc09d, 0x0eff, 0xc09d, 0x21, 0 + .dw 0x0f40, 0xc09d, 0x0f7f, 0xc09d, 0x21, 0 + .dw 0x0fc0, 0xc09d, 0x0fff, 0xc09d, 0x21, 0 + .dw 0x1040, 0xc09d, 0x107f, 0xc09d, 0x21, 0 + .dw 0x10c0, 0xc09d, 0x10ff, 0xc09d, 0x21, 0 + .dw 0x1140, 0xc09d, 0x117f, 0xc09d, 0x21, 0 + .dw 0x11c0, 0xc09d, 0x11ff, 0xc09d, 0x21, 0 + .dw 0x1240, 0xc09d, 0x127f, 0xc09d, 0x21, 0 + .dw 0x12c0, 0xc09d, 0x12ff, 0xc09d, 0x21, 0 + .dw 0x1340, 0xc09d, 0x137f, 0xc09d, 0x21, 0 + .dw 0x13c0, 0xc09d, 0x13ff, 0xc09d, 0x21, 0 + .dw 0x1440, 0xc09d, 0x147f, 0xc09d, 0x21, 0 + .dw 0x14c0, 0xc09d, 0x14ff, 0xc09d, 0x21, 0 + .dw 0x1540, 0xc09d, 0x157f, 0xc09d, 0x21, 0 + .dw 0x15c0, 0xc09d, 0x15ff, 0xc09d, 0x21, 0 + .dw 0x1640, 0xc09d, 0x167f, 0xc09d, 0x21, 0 + .dw 0x16c0, 0xc09d, 0x16ff, 0xc09d, 0x21, 0 + .dw 0x1740, 0xc09d, 0x177f, 0xc09d, 0x21, 0 + .dw 0x17c0, 0xc09d, 0x17ff, 0xc09d, 0x21, 0 + .dw 0x1840, 0xc09d, 0x187f, 0xc09d, 0x21, 0 + .dw 0x18c0, 0xc09d, 0x18ff, 0xc09d, 0x21, 0 + .dw 0x1940, 0xc09d, 0x197f, 0xc09d, 0x21, 0 + .dw 0x19c0, 0xc09d, 0x1fff, 0xc09d, 0x21, 0 + .dw 0x2040, 0xc09d, 0x207f, 0xc09d, 0x21, 0 + .dw 0x20c0, 0xc09d, 0x20ff, 0xc09d, 0x21, 0 + .dw 0x2140, 0xc09d, 0x217f, 0xc09d, 0x21, 0 + .dw 0x21c0, 0xc09d, 0x21ff, 0xc09d, 0x21, 0 + .dw 0x2240, 0xc09d, 0x227f, 0xc09d, 0x21, 0 + .dw 0x22c0, 0xc09d, 0x22ff, 0xc09d, 0x21, 0 + .dw 0x2340, 0xc09d, 0x237f, 0xc09d, 0x21, 0 + .dw 0x23c0, 0xc09d, 0x23ff, 0xc09d, 0x21, 0 + .dw 0x2440, 0xc09d, 0x247f, 0xc09d, 0x21, 0 + .dw 0x24c0, 0xc09d, 0x24ff, 0xc09d, 0x21, 0 + .dw 0x2540, 0xc09d, 0x257f, 0xc09d, 0x21, 0 + .dw 0x25c0, 0xc09d, 0x25ff, 0xc09d, 0x21, 0 + .dw 0x2640, 0xc09d, 0x267f, 0xc09d, 0x21, 0 + .dw 0x26c0, 0xc09d, 0x26ff, 0xc09d, 0x21, 0 + .dw 0x2740, 0xc09d, 0x277f, 0xc09d, 0x21, 0 + .dw 0x27c0, 0xc09d, 0x27ff, 0xc09d, 0x21, 0 + .dw 0x2840, 0xc09d, 0x287f, 0xc09d, 0x21, 0 + .dw 0x28c0, 0xc09d, 0x28ff, 0xc09d, 0x21, 0 + .dw 0x2940, 0xc09d, 0x297f, 0xc09d, 0x21, 0 + .dw 0x29c0, 0xc09d, 0x29ff, 0xc09d, 0x21, 0 + .dw 0x2a40, 0xc09d, 0x2a7f, 0xc09d, 0x21, 0 + .dw 0x2ac0, 0xc09d, 0x2aff, 0xc09d, 0x21, 0 + .dw 0x2b40, 0xc09d, 0x2b7f, 0xc09d, 0x21, 0 + .dw 0x2bc0, 0xc09d, 0x2bff, 0xc09d, 0x21, 0 + .dw 0x2c40, 0xc09d, 0x2c7f, 0xc09d, 0x21, 0 + .dw 0x2cc0, 0xc09d, 0x2cff, 0xc09d, 0x21, 0 + .dw 0x2d40, 0xc09d, 0x2d7f, 0xc09d, 0x21, 0 + .dw 0x2dc0, 0xc09d, 0x2dff, 0xc09d, 0x21, 0 + .dw 0x2e40, 0xc09d, 0x2e7f, 0xc09d, 0x21, 0 + .dw 0x2ec0, 0xc09d, 0x2eff, 0xc09d, 0x21, 0 + .dw 0x2f40, 0xc09d, 0x2f7f, 0xc09d, 0x21, 0 + .dw 0x2fc0, 0xc09d, 0x2fff, 0xc09d, 0x21, 0 + .dw 0x3040, 0xc09d, 0x307f, 0xc09d, 0x21, 0 + .dw 0x30c0, 0xc09d, 0x30ff, 0xc09d, 0x21, 0 + .dw 0x3140, 0xc09d, 0x317f, 0xc09d, 0x21, 0 + .dw 0x31c0, 0xc09d, 0x31ff, 0xc09d, 0x21, 0 + .dw 0x3240, 0xc09d, 0x327f, 0xc09d, 0x21, 0 + .dw 0x32c0, 0xc09d, 0x32ff, 0xc09d, 0x21, 0 + .dw 0x3340, 0xc09d, 0x337f, 0xc09d, 0x21, 0 + .dw 0x33c0, 0xc09d, 0x33ff, 0xc09d, 0x21, 0 + .dw 0x3440, 0xc09d, 0x347f, 0xc09d, 0x21, 0 + .dw 0x34c0, 0xc09d, 0x34ff, 0xc09d, 0x21, 0 + .dw 0x3540, 0xc09d, 0x357f, 0xc09d, 0x21, 0 + .dw 0x35c0, 0xc09d, 0x35ff, 0xc09d, 0x21, 0 + .dw 0x3640, 0xc09d, 0x367f, 0xc09d, 0x21, 0 + .dw 0x36c0, 0xc09d, 0x36ff, 0xc09d, 0x21, 0 + .dw 0x3740, 0xc09d, 0x377f, 0xc09d, 0x21, 0 + .dw 0x37c0, 0xc09d, 0x37ff, 0xc09d, 0x21, 0 + .dw 0x3840, 0xc09d, 0x387f, 0xc09d, 0x21, 0 + .dw 0x38c0, 0xc09d, 0x38ff, 0xc09d, 0x21, 0 + .dw 0x3940, 0xc09d, 0x397f, 0xc09d, 0x21, 0 + .dw 0x39c0, 0xc09d, 0x3fff, 0xc09d, 0x21, 0 + .dw 0x4040, 0xc09d, 0x407f, 0xc09d, 0x21, 0 + .dw 0x40c0, 0xc09d, 0x40ff, 0xc09d, 0x21, 0 + .dw 0x4140, 0xc09d, 0x417f, 0xc09d, 0x21, 0 + .dw 0x41c0, 0xc09d, 0x41ff, 0xc09d, 0x21, 0 + .dw 0x4240, 0xc09d, 0x427f, 0xc09d, 0x21, 0 + .dw 0x42c0, 0xc09d, 0x42ff, 0xc09d, 0x21, 0 + .dw 0x4340, 0xc09d, 0x437f, 0xc09d, 0x21, 0 + .dw 0x43c0, 0xc09d, 0x43ff, 0xc09d, 0x21, 0 + .dw 0x4440, 0xc09d, 0x447f, 0xc09d, 0x21, 0 + .dw 0x44c0, 0xc09d, 0x44ff, 0xc09d, 0x21, 0 + .dw 0x4540, 0xc09d, 0x457f, 0xc09d, 0x21, 0 + .dw 0x45c0, 0xc09d, 0x45ff, 0xc09d, 0x21, 0 + .dw 0x4640, 0xc09d, 0x467f, 0xc09d, 0x21, 0 + .dw 0x46c0, 0xc09d, 0x46ff, 0xc09d, 0x21, 0 + .dw 0x4740, 0xc09d, 0x477f, 0xc09d, 0x21, 0 + .dw 0x47c0, 0xc09d, 0x47ff, 0xc09d, 0x21, 0 + .dw 0x4840, 0xc09d, 0x487f, 0xc09d, 0x21, 0 + .dw 0x48c0, 0xc09d, 0x48ff, 0xc09d, 0x21, 0 + .dw 0x4940, 0xc09d, 0x497f, 0xc09d, 0x21, 0 + .dw 0x49c0, 0xc09d, 0x49ff, 0xc09d, 0x21, 0 + .dw 0x4a40, 0xc09d, 0x4a7f, 0xc09d, 0x21, 0 + .dw 0x4ac0, 0xc09d, 0x4aff, 0xc09d, 0x21, 0 + .dw 0x4b40, 0xc09d, 0x4b7f, 0xc09d, 0x21, 0 + .dw 0x4bc0, 0xc09d, 0x4bff, 0xc09d, 0x21, 0 + .dw 0x4c40, 0xc09d, 0x4c7f, 0xc09d, 0x21, 0 + .dw 0x4cc0, 0xc09d, 0x4cff, 0xc09d, 0x21, 0 + .dw 0x4d40, 0xc09d, 0x4d7f, 0xc09d, 0x21, 0 + .dw 0x4dc0, 0xc09d, 0x4dff, 0xc09d, 0x21, 0 + .dw 0x4e40, 0xc09d, 0x4e7f, 0xc09d, 0x21, 0 + .dw 0x4ec0, 0xc09d, 0x4eff, 0xc09d, 0x21, 0 + .dw 0x4f40, 0xc09d, 0x4f7f, 0xc09d, 0x21, 0 + .dw 0x4fc0, 0xc09d, 0x4fff, 0xc09d, 0x21, 0 + .dw 0x5040, 0xc09d, 0x507f, 0xc09d, 0x21, 0 + .dw 0x50c0, 0xc09d, 0x50ff, 0xc09d, 0x21, 0 + .dw 0x5140, 0xc09d, 0x517f, 0xc09d, 0x21, 0 + .dw 0x51c0, 0xc09d, 0x51ff, 0xc09d, 0x21, 0 + .dw 0x5240, 0xc09d, 0x527f, 0xc09d, 0x21, 0 + .dw 0x52c0, 0xc09d, 0x52ff, 0xc09d, 0x21, 0 + .dw 0x5340, 0xc09d, 0x537f, 0xc09d, 0x21, 0 + .dw 0x53c0, 0xc09d, 0x53ff, 0xc09d, 0x21, 0 + .dw 0x5440, 0xc09d, 0x547f, 0xc09d, 0x21, 0 + .dw 0x54c0, 0xc09d, 0x54ff, 0xc09d, 0x21, 0 + .dw 0x5540, 0xc09d, 0x557f, 0xc09d, 0x21, 0 + .dw 0x55c0, 0xc09d, 0x55ff, 0xc09d, 0x21, 0 + .dw 0x5640, 0xc09d, 0x567f, 0xc09d, 0x21, 0 + .dw 0x56c0, 0xc09d, 0x56ff, 0xc09d, 0x21, 0 + .dw 0x5740, 0xc09d, 0x577f, 0xc09d, 0x21, 0 + .dw 0x57c0, 0xc09d, 0x57ff, 0xc09d, 0x21, 0 + .dw 0x5840, 0xc09d, 0x587f, 0xc09d, 0x21, 0 + .dw 0x58c0, 0xc09d, 0x58ff, 0xc09d, 0x21, 0 + .dw 0x5940, 0xc09d, 0x597f, 0xc09d, 0x21, 0 + .dw 0x59c0, 0xc09d, 0x5fff, 0xc09d, 0x21, 0 + .dw 0x6040, 0xc09d, 0x607f, 0xc09d, 0x21, 0 + .dw 0x60c0, 0xc09d, 0x60ff, 0xc09d, 0x21, 0 + .dw 0x6140, 0xc09d, 0x617f, 0xc09d, 0x21, 0 + .dw 0x61c0, 0xc09d, 0x61ff, 0xc09d, 0x21, 0 + .dw 0x6240, 0xc09d, 0x627f, 0xc09d, 0x21, 0 + .dw 0x62c0, 0xc09d, 0x62ff, 0xc09d, 0x21, 0 + .dw 0x6340, 0xc09d, 0x637f, 0xc09d, 0x21, 0 + .dw 0x63c0, 0xc09d, 0x63ff, 0xc09d, 0x21, 0 + .dw 0x6440, 0xc09d, 0x647f, 0xc09d, 0x21, 0 + .dw 0x64c0, 0xc09d, 0x64ff, 0xc09d, 0x21, 0 + .dw 0x6540, 0xc09d, 0x657f, 0xc09d, 0x21, 0 + .dw 0x65c0, 0xc09d, 0x65ff, 0xc09d, 0x21, 0 + .dw 0x6640, 0xc09d, 0x667f, 0xc09d, 0x21, 0 + .dw 0x66c0, 0xc09d, 0x66ff, 0xc09d, 0x21, 0 + .dw 0x6740, 0xc09d, 0x677f, 0xc09d, 0x21, 0 + .dw 0x67c0, 0xc09d, 0x67ff, 0xc09d, 0x21, 0 + .dw 0x6840, 0xc09d, 0x687f, 0xc09d, 0x21, 0 + .dw 0x68c0, 0xc09d, 0x68ff, 0xc09d, 0x21, 0 + .dw 0x6940, 0xc09d, 0x697f, 0xc09d, 0x21, 0 + .dw 0x69c0, 0xc09d, 0x69ff, 0xc09d, 0x21, 0 + .dw 0x6a40, 0xc09d, 0x6a7f, 0xc09d, 0x21, 0 + .dw 0x6ac0, 0xc09d, 0x6aff, 0xc09d, 0x21, 0 + .dw 0x6b40, 0xc09d, 0x6b7f, 0xc09d, 0x21, 0 + .dw 0x6bc0, 0xc09d, 0x6bff, 0xc09d, 0x21, 0 + .dw 0x6c40, 0xc09d, 0x6c7f, 0xc09d, 0x21, 0 + .dw 0x6cc0, 0xc09d, 0x6cff, 0xc09d, 0x21, 0 + .dw 0x6d40, 0xc09d, 0x6d7f, 0xc09d, 0x21, 0 + .dw 0x6dc0, 0xc09d, 0x6dff, 0xc09d, 0x21, 0 + .dw 0x6e40, 0xc09d, 0x6e7f, 0xc09d, 0x21, 0 + .dw 0x6ec0, 0xc09d, 0x6eff, 0xc09d, 0x21, 0 + .dw 0x6f40, 0xc09d, 0x6f7f, 0xc09d, 0x21, 0 + .dw 0x6fc0, 0xc09d, 0x6fff, 0xc09d, 0x21, 0 + .dw 0x7040, 0xc09d, 0x707f, 0xc09d, 0x21, 0 + .dw 0x70c0, 0xc09d, 0x70ff, 0xc09d, 0x21, 0 + .dw 0x7140, 0xc09d, 0x717f, 0xc09d, 0x21, 0 + .dw 0x71c0, 0xc09d, 0x71ff, 0xc09d, 0x21, 0 + .dw 0x7240, 0xc09d, 0x727f, 0xc09d, 0x21, 0 + .dw 0x72c0, 0xc09d, 0x72ff, 0xc09d, 0x21, 0 + .dw 0x7340, 0xc09d, 0x737f, 0xc09d, 0x21, 0 + .dw 0x73c0, 0xc09d, 0x73ff, 0xc09d, 0x21, 0 + .dw 0x7440, 0xc09d, 0x747f, 0xc09d, 0x21, 0 + .dw 0x74c0, 0xc09d, 0x74ff, 0xc09d, 0x21, 0 + .dw 0x7540, 0xc09d, 0x757f, 0xc09d, 0x21, 0 + .dw 0x75c0, 0xc09d, 0x75ff, 0xc09d, 0x21, 0 + .dw 0x7640, 0xc09d, 0x767f, 0xc09d, 0x21, 0 + .dw 0x76c0, 0xc09d, 0x76ff, 0xc09d, 0x21, 0 + .dw 0x7740, 0xc09d, 0x777f, 0xc09d, 0x21, 0 + .dw 0x77c0, 0xc09d, 0x77ff, 0xc09d, 0x21, 0 + .dw 0x7840, 0xc09d, 0x787f, 0xc09d, 0x21, 0 + .dw 0x78c0, 0xc09d, 0x78ff, 0xc09d, 0x21, 0 + .dw 0x7940, 0xc09d, 0x797f, 0xc09d, 0x21, 0 + .dw 0x79c0, 0xc09d, 0x7fff, 0xc09d, 0x21, 0 + .dw 0x8040, 0xc09d, 0x807f, 0xc09d, 0x21, 0 + .dw 0x80c0, 0xc09d, 0x80ff, 0xc09d, 0x21, 0 + .dw 0x8140, 0xc09d, 0x817f, 0xc09d, 0x21, 0 + .dw 0x81c0, 0xc09d, 0x81ff, 0xc09d, 0x21, 0 + .dw 0x8240, 0xc09d, 0x827f, 0xc09d, 0x21, 0 + .dw 0x82c0, 0xc09d, 0x82ff, 0xc09d, 0x21, 0 + .dw 0x8340, 0xc09d, 0x837f, 0xc09d, 0x21, 0 + .dw 0x83c0, 0xc09d, 0x83ff, 0xc09d, 0x21, 0 + .dw 0x8440, 0xc09d, 0x847f, 0xc09d, 0x21, 0 + .dw 0x84c0, 0xc09d, 0x84ff, 0xc09d, 0x21, 0 + .dw 0x8540, 0xc09d, 0x857f, 0xc09d, 0x21, 0 + .dw 0x85c0, 0xc09d, 0x85ff, 0xc09d, 0x21, 0 + .dw 0x8640, 0xc09d, 0x867f, 0xc09d, 0x21, 0 + .dw 0x86c0, 0xc09d, 0x86ff, 0xc09d, 0x21, 0 + .dw 0x8740, 0xc09d, 0x877f, 0xc09d, 0x21, 0 + .dw 0x87c0, 0xc09d, 0x87ff, 0xc09d, 0x21, 0 + .dw 0x8840, 0xc09d, 0x887f, 0xc09d, 0x21, 0 + .dw 0x88c0, 0xc09d, 0x88ff, 0xc09d, 0x21, 0 + .dw 0x8940, 0xc09d, 0x897f, 0xc09d, 0x21, 0 + .dw 0x89c0, 0xc09d, 0x89ff, 0xc09d, 0x21, 0 + .dw 0x8a40, 0xc09d, 0x8a7f, 0xc09d, 0x21, 0 + .dw 0x8ac0, 0xc09d, 0x8aff, 0xc09d, 0x21, 0 + .dw 0x8b40, 0xc09d, 0x8b7f, 0xc09d, 0x21, 0 + .dw 0x8bc0, 0xc09d, 0x8bff, 0xc09d, 0x21, 0 + .dw 0x8c40, 0xc09d, 0x8c7f, 0xc09d, 0x21, 0 + .dw 0x8cc0, 0xc09d, 0x8cff, 0xc09d, 0x21, 0 + .dw 0x8d40, 0xc09d, 0x8d7f, 0xc09d, 0x21, 0 + .dw 0x8dc0, 0xc09d, 0x8dff, 0xc09d, 0x21, 0 + .dw 0x8e40, 0xc09d, 0x8e7f, 0xc09d, 0x21, 0 + .dw 0x8ec0, 0xc09d, 0x8eff, 0xc09d, 0x21, 0 + .dw 0x8f40, 0xc09d, 0x8f7f, 0xc09d, 0x21, 0 + .dw 0x8fc0, 0xc09d, 0x8fff, 0xc09d, 0x21, 0 + .dw 0x9040, 0xc09d, 0x907f, 0xc09d, 0x21, 0 + .dw 0x90c0, 0xc09d, 0x90ff, 0xc09d, 0x21, 0 + .dw 0x9140, 0xc09d, 0x917f, 0xc09d, 0x21, 0 + .dw 0x91c0, 0xc09d, 0x91ff, 0xc09d, 0x21, 0 + .dw 0x9240, 0xc09d, 0x927f, 0xc09d, 0x21, 0 + .dw 0x92c0, 0xc09d, 0x92ff, 0xc09d, 0x21, 0 + .dw 0x9340, 0xc09d, 0x937f, 0xc09d, 0x21, 0 + .dw 0x93c0, 0xc09d, 0x93ff, 0xc09d, 0x21, 0 + .dw 0x9440, 0xc09d, 0x947f, 0xc09d, 0x21, 0 + .dw 0x94c0, 0xc09d, 0x94ff, 0xc09d, 0x21, 0 + .dw 0x9540, 0xc09d, 0x957f, 0xc09d, 0x21, 0 + .dw 0x95c0, 0xc09d, 0x95ff, 0xc09d, 0x21, 0 + .dw 0x9640, 0xc09d, 0x967f, 0xc09d, 0x21, 0 + .dw 0x96c0, 0xc09d, 0x96ff, 0xc09d, 0x21, 0 + .dw 0x9740, 0xc09d, 0x977f, 0xc09d, 0x21, 0 + .dw 0x97c0, 0xc09d, 0x97ff, 0xc09d, 0x21, 0 + .dw 0x9840, 0xc09d, 0x987f, 0xc09d, 0x21, 0 + .dw 0x98c0, 0xc09d, 0x98ff, 0xc09d, 0x21, 0 + .dw 0x9940, 0xc09d, 0x997f, 0xc09d, 0x21, 0 + .dw 0x99c0, 0xc09d, 0x9fff, 0xc09d, 0x21, 0 + .dw 0xa040, 0xc09d, 0xa07f, 0xc09d, 0x21, 0 + .dw 0xa0c0, 0xc09d, 0xa0ff, 0xc09d, 0x21, 0 + .dw 0xa140, 0xc09d, 0xa17f, 0xc09d, 0x21, 0 + .dw 0xa1c0, 0xc09d, 0xa1ff, 0xc09d, 0x21, 0 + .dw 0xa240, 0xc09d, 0xa27f, 0xc09d, 0x21, 0 + .dw 0xa2c0, 0xc09d, 0xa2ff, 0xc09d, 0x21, 0 + .dw 0xa340, 0xc09d, 0xa37f, 0xc09d, 0x21, 0 + .dw 0xa3c0, 0xc09d, 0xa3ff, 0xc09d, 0x21, 0 + .dw 0xa440, 0xc09d, 0xa47f, 0xc09d, 0x21, 0 + .dw 0xa4c0, 0xc09d, 0xa4ff, 0xc09d, 0x21, 0 + .dw 0xa540, 0xc09d, 0xa57f, 0xc09d, 0x21, 0 + .dw 0xa5c0, 0xc09d, 0xa5ff, 0xc09d, 0x21, 0 + .dw 0xa640, 0xc09d, 0xa67f, 0xc09d, 0x21, 0 + .dw 0xa6c0, 0xc09d, 0xa6ff, 0xc09d, 0x21, 0 + .dw 0xa740, 0xc09d, 0xa77f, 0xc09d, 0x21, 0 + .dw 0xa7c0, 0xc09d, 0xa7ff, 0xc09d, 0x21, 0 + .dw 0xa840, 0xc09d, 0xa87f, 0xc09d, 0x21, 0 + .dw 0xa8c0, 0xc09d, 0xa8ff, 0xc09d, 0x21, 0 + .dw 0xa940, 0xc09d, 0xa97f, 0xc09d, 0x21, 0 + .dw 0xa9c0, 0xc09d, 0xa9ff, 0xc09d, 0x21, 0 + .dw 0xaa40, 0xc09d, 0xaa7f, 0xc09d, 0x21, 0 + .dw 0xaac0, 0xc09d, 0xaaff, 0xc09d, 0x21, 0 + .dw 0xab40, 0xc09d, 0xab7f, 0xc09d, 0x21, 0 + .dw 0xabc0, 0xc09d, 0xabff, 0xc09d, 0x21, 0 + .dw 0xac40, 0xc09d, 0xac7f, 0xc09d, 0x21, 0 + .dw 0xacc0, 0xc09d, 0xacff, 0xc09d, 0x21, 0 + .dw 0xad40, 0xc09d, 0xad7f, 0xc09d, 0x21, 0 + .dw 0xadc0, 0xc09d, 0xadff, 0xc09d, 0x21, 0 + .dw 0xae40, 0xc09d, 0xae7f, 0xc09d, 0x21, 0 + .dw 0xaec0, 0xc09d, 0xaeff, 0xc09d, 0x21, 0 + .dw 0xaf40, 0xc09d, 0xaf7f, 0xc09d, 0x21, 0 + .dw 0xafc0, 0xc09d, 0xafff, 0xc09d, 0x21, 0 + .dw 0xb040, 0xc09d, 0xb07f, 0xc09d, 0x21, 0 + .dw 0xb0c0, 0xc09d, 0xb0ff, 0xc09d, 0x21, 0 + .dw 0xb140, 0xc09d, 0xb17f, 0xc09d, 0x21, 0 + .dw 0xb1c0, 0xc09d, 0xb1ff, 0xc09d, 0x21, 0 + .dw 0xb240, 0xc09d, 0xb27f, 0xc09d, 0x21, 0 + .dw 0xb2c0, 0xc09d, 0xb2ff, 0xc09d, 0x21, 0 + .dw 0xb340, 0xc09d, 0xb37f, 0xc09d, 0x21, 0 + .dw 0xb3c0, 0xc09d, 0xb3ff, 0xc09d, 0x21, 0 + .dw 0xb440, 0xc09d, 0xb47f, 0xc09d, 0x21, 0 + .dw 0xb4c0, 0xc09d, 0xb4ff, 0xc09d, 0x21, 0 + .dw 0xb540, 0xc09d, 0xb57f, 0xc09d, 0x21, 0 + .dw 0xb5c0, 0xc09d, 0xb5ff, 0xc09d, 0x21, 0 + .dw 0xb640, 0xc09d, 0xb67f, 0xc09d, 0x21, 0 + .dw 0xb6c0, 0xc09d, 0xb6ff, 0xc09d, 0x21, 0 + .dw 0xb740, 0xc09d, 0xb77f, 0xc09d, 0x21, 0 + .dw 0xb7c0, 0xc09d, 0xb7ff, 0xc09d, 0x21, 0 + .dw 0xb840, 0xc09d, 0xb87f, 0xc09d, 0x21, 0 + .dw 0xb8c0, 0xc09d, 0xb8ff, 0xc09d, 0x21, 0 + .dw 0xb940, 0xc09d, 0xb97f, 0xc09d, 0x21, 0 + .dw 0xb9c0, 0xc09d, 0xbfff, 0xc09d, 0x21, 0 + .dw 0xc040, 0xc09d, 0xc07f, 0xc09d, 0x21, 0 + .dw 0xc0c0, 0xc09d, 0xc0ff, 0xc09d, 0x21, 0 + .dw 0xc140, 0xc09d, 0xc17f, 0xc09d, 0x21, 0 + .dw 0xc1c0, 0xc09d, 0xc1ff, 0xc09d, 0x21, 0 + .dw 0xc240, 0xc09d, 0xc27f, 0xc09d, 0x21, 0 + .dw 0xc2c0, 0xc09d, 0xc2ff, 0xc09d, 0x21, 0 + .dw 0xc340, 0xc09d, 0xc37f, 0xc09d, 0x21, 0 + .dw 0xc3c0, 0xc09d, 0xc3ff, 0xc09d, 0x21, 0 + .dw 0xc440, 0xc09d, 0xc47f, 0xc09d, 0x21, 0 + .dw 0xc4c0, 0xc09d, 0xc4ff, 0xc09d, 0x21, 0 + .dw 0xc540, 0xc09d, 0xc57f, 0xc09d, 0x21, 0 + .dw 0xc5c0, 0xc09d, 0xc5ff, 0xc09d, 0x21, 0 + .dw 0xc640, 0xc09d, 0xc67f, 0xc09d, 0x21, 0 + .dw 0xc6c0, 0xc09d, 0xc6ff, 0xc09d, 0x21, 0 + .dw 0xc740, 0xc09d, 0xc77f, 0xc09d, 0x21, 0 + .dw 0xc7c0, 0xc09d, 0xc7ff, 0xc09d, 0x21, 0 + .dw 0xc840, 0xc09d, 0xc87f, 0xc09d, 0x21, 0 + .dw 0xc8c0, 0xc09d, 0xc8ff, 0xc09d, 0x21, 0 + .dw 0xc940, 0xc09d, 0xc97f, 0xc09d, 0x21, 0 + .dw 0xc9c0, 0xc09d, 0xc9ff, 0xc09d, 0x21, 0 + .dw 0xca40, 0xc09d, 0xca7f, 0xc09d, 0x21, 0 + .dw 0xcac0, 0xc09d, 0xcaff, 0xc09d, 0x21, 0 + .dw 0xcb40, 0xc09d, 0xcb7f, 0xc09d, 0x21, 0 + .dw 0xcbc0, 0xc09d, 0xcbff, 0xc09d, 0x21, 0 + .dw 0xcc40, 0xc09d, 0xcc7f, 0xc09d, 0x21, 0 + .dw 0xccc0, 0xc09d, 0xccff, 0xc09d, 0x21, 0 + .dw 0xcd40, 0xc09d, 0xcd7f, 0xc09d, 0x21, 0 + .dw 0xcdc0, 0xc09d, 0xcdff, 0xc09d, 0x21, 0 + .dw 0xce40, 0xc09d, 0xce7f, 0xc09d, 0x21, 0 + .dw 0xcec0, 0xc09d, 0xceff, 0xc09d, 0x21, 0 + .dw 0xcf40, 0xc09d, 0xcf7f, 0xc09d, 0x21, 0 + .dw 0xcfc0, 0xc09d, 0xcfff, 0xc09d, 0x21, 0 + .dw 0xd040, 0xc09d, 0xd07f, 0xc09d, 0x21, 0 + .dw 0xd0c0, 0xc09d, 0xd0ff, 0xc09d, 0x21, 0 + .dw 0xd140, 0xc09d, 0xd17f, 0xc09d, 0x21, 0 + .dw 0xd1c0, 0xc09d, 0xd1ff, 0xc09d, 0x21, 0 + .dw 0xd240, 0xc09d, 0xd27f, 0xc09d, 0x21, 0 + .dw 0xd2c0, 0xc09d, 0xd2ff, 0xc09d, 0x21, 0 + .dw 0xd340, 0xc09d, 0xd37f, 0xc09d, 0x21, 0 + .dw 0xd3c0, 0xc09d, 0xd3ff, 0xc09d, 0x21, 0 + .dw 0xd440, 0xc09d, 0xd47f, 0xc09d, 0x21, 0 + .dw 0xd4c0, 0xc09d, 0xd4ff, 0xc09d, 0x21, 0 + .dw 0xd540, 0xc09d, 0xd57f, 0xc09d, 0x21, 0 + .dw 0xd5c0, 0xc09d, 0xd5ff, 0xc09d, 0x21, 0 + .dw 0xd640, 0xc09d, 0xd67f, 0xc09d, 0x21, 0 + .dw 0xd6c0, 0xc09d, 0xd6ff, 0xc09d, 0x21, 0 + .dw 0xd740, 0xc09d, 0xd77f, 0xc09d, 0x21, 0 + .dw 0xd7c0, 0xc09d, 0xd7ff, 0xc09d, 0x21, 0 + .dw 0xd840, 0xc09d, 0xd87f, 0xc09d, 0x21, 0 + .dw 0xd8c0, 0xc09d, 0xd8ff, 0xc09d, 0x21, 0 + .dw 0xd940, 0xc09d, 0xd97f, 0xc09d, 0x21, 0 + .dw 0xd9c0, 0xc09d, 0xdfff, 0xc09d, 0x21, 0 + .dw 0xe040, 0xc09d, 0xe07f, 0xc09d, 0x21, 0 + .dw 0xe0c0, 0xc09d, 0xe0ff, 0xc09d, 0x21, 0 + .dw 0xe140, 0xc09d, 0xe17f, 0xc09d, 0x21, 0 + .dw 0xe1c0, 0xc09d, 0xe1ff, 0xc09d, 0x21, 0 + .dw 0xe240, 0xc09d, 0xe27f, 0xc09d, 0x21, 0 + .dw 0xe2c0, 0xc09d, 0xe2ff, 0xc09d, 0x21, 0 + .dw 0xe340, 0xc09d, 0xe37f, 0xc09d, 0x21, 0 + .dw 0xe3c0, 0xc09d, 0xe3ff, 0xc09d, 0x21, 0 + .dw 0xe440, 0xc09d, 0xe47f, 0xc09d, 0x21, 0 + .dw 0xe4c0, 0xc09d, 0xe4ff, 0xc09d, 0x21, 0 + .dw 0xe540, 0xc09d, 0xe57f, 0xc09d, 0x21, 0 + .dw 0xe5c0, 0xc09d, 0xe5ff, 0xc09d, 0x21, 0 + .dw 0xe640, 0xc09d, 0xe67f, 0xc09d, 0x21, 0 + .dw 0xe6c0, 0xc09d, 0xe6ff, 0xc09d, 0x21, 0 + .dw 0xe740, 0xc09d, 0xe77f, 0xc09d, 0x21, 0 + .dw 0xe7c0, 0xc09d, 0xe7ff, 0xc09d, 0x21, 0 + .dw 0xe840, 0xc09d, 0xe87f, 0xc09d, 0x21, 0 + .dw 0xe8c0, 0xc09d, 0xe8ff, 0xc09d, 0x21, 0 + .dw 0xe940, 0xc09d, 0xe97f, 0xc09d, 0x21, 0 + .dw 0xe9c0, 0xc09d, 0xe9ff, 0xc09d, 0x21, 0 + .dw 0xea40, 0xc09d, 0xea7f, 0xc09d, 0x21, 0 + .dw 0xeac0, 0xc09d, 0xeaff, 0xc09d, 0x21, 0 + .dw 0xeb40, 0xc09d, 0xeb7f, 0xc09d, 0x21, 0 + .dw 0xebc0, 0xc09d, 0xebff, 0xc09d, 0x21, 0 + .dw 0xec40, 0xc09d, 0xec7f, 0xc09d, 0x21, 0 + .dw 0xecc0, 0xc09d, 0xecff, 0xc09d, 0x21, 0 + .dw 0xed40, 0xc09d, 0xed7f, 0xc09d, 0x21, 0 + .dw 0xedc0, 0xc09d, 0xedff, 0xc09d, 0x21, 0 + .dw 0xee40, 0xc09d, 0xee7f, 0xc09d, 0x21, 0 + .dw 0xeec0, 0xc09d, 0xeeff, 0xc09d, 0x21, 0 + .dw 0xef40, 0xc09d, 0xef7f, 0xc09d, 0x21, 0 + .dw 0xefc0, 0xc09d, 0xefff, 0xc09d, 0x21, 0 + .dw 0xf040, 0xc09d, 0xf07f, 0xc09d, 0x21, 0 + .dw 0xf0c0, 0xc09d, 0xf0ff, 0xc09d, 0x21, 0 + .dw 0xf140, 0xc09d, 0xf17f, 0xc09d, 0x21, 0 + .dw 0xf1c0, 0xc09d, 0xf1ff, 0xc09d, 0x21, 0 + .dw 0xf240, 0xc09d, 0xf27f, 0xc09d, 0x21, 0 + .dw 0xf2c0, 0xc09d, 0xf2ff, 0xc09d, 0x21, 0 + .dw 0xf340, 0xc09d, 0xf37f, 0xc09d, 0x21, 0 + .dw 0xf3c0, 0xc09d, 0xf3ff, 0xc09d, 0x21, 0 + .dw 0xf440, 0xc09d, 0xf47f, 0xc09d, 0x21, 0 + .dw 0xf4c0, 0xc09d, 0xf4ff, 0xc09d, 0x21, 0 + .dw 0xf540, 0xc09d, 0xf57f, 0xc09d, 0x21, 0 + .dw 0xf5c0, 0xc09d, 0xf5ff, 0xc09d, 0x21, 0 + .dw 0xf640, 0xc09d, 0xf67f, 0xc09d, 0x21, 0 + .dw 0xf6c0, 0xc09d, 0xf6ff, 0xc09d, 0x21, 0 + .dw 0xf740, 0xc09d, 0xf77f, 0xc09d, 0x21, 0 + .dw 0xf7c0, 0xc09d, 0xf7ff, 0xc09d, 0x21, 0 + .dw 0xf840, 0xc09d, 0xf87f, 0xc09d, 0x21, 0 + .dw 0xf8c0, 0xc09d, 0xf8ff, 0xc09d, 0x21, 0 + .dw 0xf940, 0xc09d, 0xf97f, 0xc09d, 0x21, 0 + .dw 0xf9c0, 0xc09d, 0xffff, 0xc09d, 0x21, 0 + .dw 0x0040, 0xc09e, 0x007f, 0xc09e, 0x21, 0 + .dw 0x00c0, 0xc09e, 0x00ff, 0xc09e, 0x21, 0 + .dw 0x0140, 0xc09e, 0x017f, 0xc09e, 0x21, 0 + .dw 0x01c0, 0xc09e, 0x01ff, 0xc09e, 0x21, 0 + .dw 0x0240, 0xc09e, 0x027f, 0xc09e, 0x21, 0 + .dw 0x02c0, 0xc09e, 0x02ff, 0xc09e, 0x21, 0 + .dw 0x0340, 0xc09e, 0x037f, 0xc09e, 0x21, 0 + .dw 0x03c0, 0xc09e, 0x03ff, 0xc09e, 0x21, 0 + .dw 0x0440, 0xc09e, 0x047f, 0xc09e, 0x21, 0 + .dw 0x04c0, 0xc09e, 0x04ff, 0xc09e, 0x21, 0 + .dw 0x0540, 0xc09e, 0x057f, 0xc09e, 0x21, 0 + .dw 0x05c0, 0xc09e, 0x05ff, 0xc09e, 0x21, 0 + .dw 0x0640, 0xc09e, 0x067f, 0xc09e, 0x21, 0 + .dw 0x06c0, 0xc09e, 0x06ff, 0xc09e, 0x21, 0 + .dw 0x0740, 0xc09e, 0x077f, 0xc09e, 0x21, 0 + .dw 0x07c0, 0xc09e, 0x07ff, 0xc09e, 0x21, 0 + .dw 0x0840, 0xc09e, 0x087f, 0xc09e, 0x21, 0 + .dw 0x08c0, 0xc09e, 0x08ff, 0xc09e, 0x21, 0 + .dw 0x0940, 0xc09e, 0x097f, 0xc09e, 0x21, 0 + .dw 0x09c0, 0xc09e, 0x09ff, 0xc09e, 0x21, 0 + .dw 0x0a40, 0xc09e, 0x0a7f, 0xc09e, 0x21, 0 + .dw 0x0ac0, 0xc09e, 0x0aff, 0xc09e, 0x21, 0 + .dw 0x0b40, 0xc09e, 0x0b7f, 0xc09e, 0x21, 0 + .dw 0x0bc0, 0xc09e, 0x0bff, 0xc09e, 0x21, 0 + .dw 0x0c40, 0xc09e, 0x0c7f, 0xc09e, 0x21, 0 + .dw 0x0cc0, 0xc09e, 0x0cff, 0xc09e, 0x21, 0 + .dw 0x0d40, 0xc09e, 0x0d7f, 0xc09e, 0x21, 0 + .dw 0x0dc0, 0xc09e, 0x0dff, 0xc09e, 0x21, 0 + .dw 0x0e40, 0xc09e, 0x0e7f, 0xc09e, 0x21, 0 + .dw 0x0ec0, 0xc09e, 0x0eff, 0xc09e, 0x21, 0 + .dw 0x0f40, 0xc09e, 0x0f7f, 0xc09e, 0x21, 0 + .dw 0x0fc0, 0xc09e, 0x0fff, 0xc09e, 0x21, 0 + .dw 0x1040, 0xc09e, 0x107f, 0xc09e, 0x21, 0 + .dw 0x10c0, 0xc09e, 0x10ff, 0xc09e, 0x21, 0 + .dw 0x1140, 0xc09e, 0x117f, 0xc09e, 0x21, 0 + .dw 0x11c0, 0xc09e, 0x11ff, 0xc09e, 0x21, 0 + .dw 0x1240, 0xc09e, 0x127f, 0xc09e, 0x21, 0 + .dw 0x12c0, 0xc09e, 0x12ff, 0xc09e, 0x21, 0 + .dw 0x1340, 0xc09e, 0x137f, 0xc09e, 0x21, 0 + .dw 0x13c0, 0xc09e, 0x13ff, 0xc09e, 0x21, 0 + .dw 0x1440, 0xc09e, 0x147f, 0xc09e, 0x21, 0 + .dw 0x14c0, 0xc09e, 0x14ff, 0xc09e, 0x21, 0 + .dw 0x1540, 0xc09e, 0x157f, 0xc09e, 0x21, 0 + .dw 0x15c0, 0xc09e, 0x15ff, 0xc09e, 0x21, 0 + .dw 0x1640, 0xc09e, 0x167f, 0xc09e, 0x21, 0 + .dw 0x16c0, 0xc09e, 0x16ff, 0xc09e, 0x21, 0 + .dw 0x1740, 0xc09e, 0x177f, 0xc09e, 0x21, 0 + .dw 0x17c0, 0xc09e, 0x17ff, 0xc09e, 0x21, 0 + .dw 0x1840, 0xc09e, 0x187f, 0xc09e, 0x21, 0 + .dw 0x18c0, 0xc09e, 0x18ff, 0xc09e, 0x21, 0 + .dw 0x1940, 0xc09e, 0x197f, 0xc09e, 0x21, 0 + .dw 0x19c0, 0xc09e, 0x1fff, 0xc09e, 0x21, 0 + .dw 0x2040, 0xc09e, 0x207f, 0xc09e, 0x21, 0 + .dw 0x20c0, 0xc09e, 0x20ff, 0xc09e, 0x21, 0 + .dw 0x2140, 0xc09e, 0x217f, 0xc09e, 0x21, 0 + .dw 0x21c0, 0xc09e, 0x21ff, 0xc09e, 0x21, 0 + .dw 0x2240, 0xc09e, 0x227f, 0xc09e, 0x21, 0 + .dw 0x22c0, 0xc09e, 0x22ff, 0xc09e, 0x21, 0 + .dw 0x2340, 0xc09e, 0x237f, 0xc09e, 0x21, 0 + .dw 0x23c0, 0xc09e, 0x23ff, 0xc09e, 0x21, 0 + .dw 0x2440, 0xc09e, 0x247f, 0xc09e, 0x21, 0 + .dw 0x24c0, 0xc09e, 0x24ff, 0xc09e, 0x21, 0 + .dw 0x2540, 0xc09e, 0x257f, 0xc09e, 0x21, 0 + .dw 0x25c0, 0xc09e, 0x25ff, 0xc09e, 0x21, 0 + .dw 0x2640, 0xc09e, 0x267f, 0xc09e, 0x21, 0 + .dw 0x26c0, 0xc09e, 0x26ff, 0xc09e, 0x21, 0 + .dw 0x2740, 0xc09e, 0x277f, 0xc09e, 0x21, 0 + .dw 0x27c0, 0xc09e, 0x27ff, 0xc09e, 0x21, 0 + .dw 0x2840, 0xc09e, 0x287f, 0xc09e, 0x21, 0 + .dw 0x28c0, 0xc09e, 0x28ff, 0xc09e, 0x21, 0 + .dw 0x2940, 0xc09e, 0x297f, 0xc09e, 0x21, 0 + .dw 0x29c0, 0xc09e, 0x29ff, 0xc09e, 0x21, 0 + .dw 0x2a40, 0xc09e, 0x2a7f, 0xc09e, 0x21, 0 + .dw 0x2ac0, 0xc09e, 0x2aff, 0xc09e, 0x21, 0 + .dw 0x2b40, 0xc09e, 0x2b7f, 0xc09e, 0x21, 0 + .dw 0x2bc0, 0xc09e, 0x2bff, 0xc09e, 0x21, 0 + .dw 0x2c40, 0xc09e, 0x2c7f, 0xc09e, 0x21, 0 + .dw 0x2cc0, 0xc09e, 0x2cff, 0xc09e, 0x21, 0 + .dw 0x2d40, 0xc09e, 0x2d7f, 0xc09e, 0x21, 0 + .dw 0x2dc0, 0xc09e, 0x2dff, 0xc09e, 0x21, 0 + .dw 0x2e40, 0xc09e, 0x2e7f, 0xc09e, 0x21, 0 + .dw 0x2ec0, 0xc09e, 0x2eff, 0xc09e, 0x21, 0 + .dw 0x2f40, 0xc09e, 0x2f7f, 0xc09e, 0x21, 0 + .dw 0x2fc0, 0xc09e, 0x2fff, 0xc09e, 0x21, 0 + .dw 0x3040, 0xc09e, 0x307f, 0xc09e, 0x21, 0 + .dw 0x30c0, 0xc09e, 0x30ff, 0xc09e, 0x21, 0 + .dw 0x3140, 0xc09e, 0x317f, 0xc09e, 0x21, 0 + .dw 0x31c0, 0xc09e, 0x31ff, 0xc09e, 0x21, 0 + .dw 0x3240, 0xc09e, 0x327f, 0xc09e, 0x21, 0 + .dw 0x32c0, 0xc09e, 0x32ff, 0xc09e, 0x21, 0 + .dw 0x3340, 0xc09e, 0x337f, 0xc09e, 0x21, 0 + .dw 0x33c0, 0xc09e, 0x33ff, 0xc09e, 0x21, 0 + .dw 0x3440, 0xc09e, 0x347f, 0xc09e, 0x21, 0 + .dw 0x34c0, 0xc09e, 0x34ff, 0xc09e, 0x21, 0 + .dw 0x3540, 0xc09e, 0x357f, 0xc09e, 0x21, 0 + .dw 0x35c0, 0xc09e, 0x35ff, 0xc09e, 0x21, 0 + .dw 0x3640, 0xc09e, 0x367f, 0xc09e, 0x21, 0 + .dw 0x36c0, 0xc09e, 0x36ff, 0xc09e, 0x21, 0 + .dw 0x3740, 0xc09e, 0x377f, 0xc09e, 0x21, 0 + .dw 0x37c0, 0xc09e, 0x37ff, 0xc09e, 0x21, 0 + .dw 0x3840, 0xc09e, 0x387f, 0xc09e, 0x21, 0 + .dw 0x38c0, 0xc09e, 0x38ff, 0xc09e, 0x21, 0 + .dw 0x3940, 0xc09e, 0x397f, 0xc09e, 0x21, 0 + .dw 0x39c0, 0xc09e, 0x3fff, 0xc09e, 0x21, 0 + .dw 0x4040, 0xc09e, 0x407f, 0xc09e, 0x21, 0 + .dw 0x40c0, 0xc09e, 0x40ff, 0xc09e, 0x21, 0 + .dw 0x4140, 0xc09e, 0x417f, 0xc09e, 0x21, 0 + .dw 0x41c0, 0xc09e, 0x41ff, 0xc09e, 0x21, 0 + .dw 0x4240, 0xc09e, 0x427f, 0xc09e, 0x21, 0 + .dw 0x42c0, 0xc09e, 0x42ff, 0xc09e, 0x21, 0 + .dw 0x4340, 0xc09e, 0x437f, 0xc09e, 0x21, 0 + .dw 0x43c0, 0xc09e, 0x43ff, 0xc09e, 0x21, 0 + .dw 0x4440, 0xc09e, 0x447f, 0xc09e, 0x21, 0 + .dw 0x44c0, 0xc09e, 0x44ff, 0xc09e, 0x21, 0 + .dw 0x4540, 0xc09e, 0x457f, 0xc09e, 0x21, 0 + .dw 0x45c0, 0xc09e, 0x45ff, 0xc09e, 0x21, 0 + .dw 0x4640, 0xc09e, 0x467f, 0xc09e, 0x21, 0 + .dw 0x46c0, 0xc09e, 0x46ff, 0xc09e, 0x21, 0 + .dw 0x4740, 0xc09e, 0x477f, 0xc09e, 0x21, 0 + .dw 0x47c0, 0xc09e, 0x47ff, 0xc09e, 0x21, 0 + .dw 0x4840, 0xc09e, 0x487f, 0xc09e, 0x21, 0 + .dw 0x48c0, 0xc09e, 0x48ff, 0xc09e, 0x21, 0 + .dw 0x4940, 0xc09e, 0x497f, 0xc09e, 0x21, 0 + .dw 0x49c0, 0xc09e, 0x49ff, 0xc09e, 0x21, 0 + .dw 0x4a40, 0xc09e, 0x4a7f, 0xc09e, 0x21, 0 + .dw 0x4ac0, 0xc09e, 0x4aff, 0xc09e, 0x21, 0 + .dw 0x4b40, 0xc09e, 0x4b7f, 0xc09e, 0x21, 0 + .dw 0x4bc0, 0xc09e, 0x4bff, 0xc09e, 0x21, 0 + .dw 0x4c40, 0xc09e, 0x4c7f, 0xc09e, 0x21, 0 + .dw 0x4cc0, 0xc09e, 0x4cff, 0xc09e, 0x21, 0 + .dw 0x4d40, 0xc09e, 0x4d7f, 0xc09e, 0x21, 0 + .dw 0x4dc0, 0xc09e, 0x4dff, 0xc09e, 0x21, 0 + .dw 0x4e40, 0xc09e, 0x4e7f, 0xc09e, 0x21, 0 + .dw 0x4ec0, 0xc09e, 0x4eff, 0xc09e, 0x21, 0 + .dw 0x4f40, 0xc09e, 0x4f7f, 0xc09e, 0x21, 0 + .dw 0x4fc0, 0xc09e, 0x4fff, 0xc09e, 0x21, 0 + .dw 0x5040, 0xc09e, 0x507f, 0xc09e, 0x21, 0 + .dw 0x50c0, 0xc09e, 0x50ff, 0xc09e, 0x21, 0 + .dw 0x5140, 0xc09e, 0x517f, 0xc09e, 0x21, 0 + .dw 0x51c0, 0xc09e, 0x51ff, 0xc09e, 0x21, 0 + .dw 0x5240, 0xc09e, 0x527f, 0xc09e, 0x21, 0 + .dw 0x52c0, 0xc09e, 0x52ff, 0xc09e, 0x21, 0 + .dw 0x5340, 0xc09e, 0x537f, 0xc09e, 0x21, 0 + .dw 0x53c0, 0xc09e, 0x53ff, 0xc09e, 0x21, 0 + .dw 0x5440, 0xc09e, 0x547f, 0xc09e, 0x21, 0 + .dw 0x54c0, 0xc09e, 0x54ff, 0xc09e, 0x21, 0 + .dw 0x5540, 0xc09e, 0x557f, 0xc09e, 0x21, 0 + .dw 0x55c0, 0xc09e, 0x55ff, 0xc09e, 0x21, 0 + .dw 0x5640, 0xc09e, 0x567f, 0xc09e, 0x21, 0 + .dw 0x56c0, 0xc09e, 0x56ff, 0xc09e, 0x21, 0 + .dw 0x5740, 0xc09e, 0x577f, 0xc09e, 0x21, 0 + .dw 0x57c0, 0xc09e, 0x57ff, 0xc09e, 0x21, 0 + .dw 0x5840, 0xc09e, 0x587f, 0xc09e, 0x21, 0 + .dw 0x58c0, 0xc09e, 0x58ff, 0xc09e, 0x21, 0 + .dw 0x5940, 0xc09e, 0x597f, 0xc09e, 0x21, 0 + .dw 0x59c0, 0xc09e, 0x5fff, 0xc09e, 0x21, 0 + .dw 0x6040, 0xc09e, 0x607f, 0xc09e, 0x21, 0 + .dw 0x60c0, 0xc09e, 0x60ff, 0xc09e, 0x21, 0 + .dw 0x6140, 0xc09e, 0x617f, 0xc09e, 0x21, 0 + .dw 0x61c0, 0xc09e, 0x61ff, 0xc09e, 0x21, 0 + .dw 0x6240, 0xc09e, 0x627f, 0xc09e, 0x21, 0 + .dw 0x62c0, 0xc09e, 0x62ff, 0xc09e, 0x21, 0 + .dw 0x6340, 0xc09e, 0x637f, 0xc09e, 0x21, 0 + .dw 0x63c0, 0xc09e, 0x63ff, 0xc09e, 0x21, 0 + .dw 0x6440, 0xc09e, 0x647f, 0xc09e, 0x21, 0 + .dw 0x64c0, 0xc09e, 0x64ff, 0xc09e, 0x21, 0 + .dw 0x6540, 0xc09e, 0x657f, 0xc09e, 0x21, 0 + .dw 0x65c0, 0xc09e, 0x65ff, 0xc09e, 0x21, 0 + .dw 0x6640, 0xc09e, 0x667f, 0xc09e, 0x21, 0 + .dw 0x66c0, 0xc09e, 0x66ff, 0xc09e, 0x21, 0 + .dw 0x6740, 0xc09e, 0x677f, 0xc09e, 0x21, 0 + .dw 0x67c0, 0xc09e, 0x67ff, 0xc09e, 0x21, 0 + .dw 0x6840, 0xc09e, 0x687f, 0xc09e, 0x21, 0 + .dw 0x68c0, 0xc09e, 0x68ff, 0xc09e, 0x21, 0 + .dw 0x6940, 0xc09e, 0x697f, 0xc09e, 0x21, 0 + .dw 0x69c0, 0xc09e, 0x69ff, 0xc09e, 0x21, 0 + .dw 0x6a40, 0xc09e, 0x6a7f, 0xc09e, 0x21, 0 + .dw 0x6ac0, 0xc09e, 0x6aff, 0xc09e, 0x21, 0 + .dw 0x6b40, 0xc09e, 0x6b7f, 0xc09e, 0x21, 0 + .dw 0x6bc0, 0xc09e, 0x6bff, 0xc09e, 0x21, 0 + .dw 0x6c40, 0xc09e, 0x6c7f, 0xc09e, 0x21, 0 + .dw 0x6cc0, 0xc09e, 0x6cff, 0xc09e, 0x21, 0 + .dw 0x6d40, 0xc09e, 0x6d7f, 0xc09e, 0x21, 0 + .dw 0x6dc0, 0xc09e, 0x6dff, 0xc09e, 0x21, 0 + .dw 0x6e40, 0xc09e, 0x6e7f, 0xc09e, 0x21, 0 + .dw 0x6ec0, 0xc09e, 0x6eff, 0xc09e, 0x21, 0 + .dw 0x6f40, 0xc09e, 0x6f7f, 0xc09e, 0x21, 0 + .dw 0x6fc0, 0xc09e, 0x6fff, 0xc09e, 0x21, 0 + .dw 0x7040, 0xc09e, 0x707f, 0xc09e, 0x21, 0 + .dw 0x70c0, 0xc09e, 0x70ff, 0xc09e, 0x21, 0 + .dw 0x7140, 0xc09e, 0x717f, 0xc09e, 0x21, 0 + .dw 0x71c0, 0xc09e, 0x71ff, 0xc09e, 0x21, 0 + .dw 0x7240, 0xc09e, 0x727f, 0xc09e, 0x21, 0 + .dw 0x72c0, 0xc09e, 0x72ff, 0xc09e, 0x21, 0 + .dw 0x7340, 0xc09e, 0x737f, 0xc09e, 0x21, 0 + .dw 0x73c0, 0xc09e, 0x73ff, 0xc09e, 0x21, 0 + .dw 0x7440, 0xc09e, 0x747f, 0xc09e, 0x21, 0 + .dw 0x74c0, 0xc09e, 0x74ff, 0xc09e, 0x21, 0 + .dw 0x7540, 0xc09e, 0x757f, 0xc09e, 0x21, 0 + .dw 0x75c0, 0xc09e, 0x75ff, 0xc09e, 0x21, 0 + .dw 0x7640, 0xc09e, 0x767f, 0xc09e, 0x21, 0 + .dw 0x76c0, 0xc09e, 0x76ff, 0xc09e, 0x21, 0 + .dw 0x7740, 0xc09e, 0x777f, 0xc09e, 0x21, 0 + .dw 0x77c0, 0xc09e, 0x77ff, 0xc09e, 0x21, 0 + .dw 0x7840, 0xc09e, 0x787f, 0xc09e, 0x21, 0 + .dw 0x78c0, 0xc09e, 0x78ff, 0xc09e, 0x21, 0 + .dw 0x7940, 0xc09e, 0x797f, 0xc09e, 0x21, 0 + .dw 0x79c0, 0xc09e, 0x7fff, 0xc09e, 0x21, 0 + .dw 0x8040, 0xc09e, 0x807f, 0xc09e, 0x21, 0 + .dw 0x80c0, 0xc09e, 0x80ff, 0xc09e, 0x21, 0 + .dw 0x8140, 0xc09e, 0x817f, 0xc09e, 0x21, 0 + .dw 0x81c0, 0xc09e, 0x81ff, 0xc09e, 0x21, 0 + .dw 0x8240, 0xc09e, 0x827f, 0xc09e, 0x21, 0 + .dw 0x82c0, 0xc09e, 0x82ff, 0xc09e, 0x21, 0 + .dw 0x8340, 0xc09e, 0x837f, 0xc09e, 0x21, 0 + .dw 0x83c0, 0xc09e, 0x83ff, 0xc09e, 0x21, 0 + .dw 0x8440, 0xc09e, 0x847f, 0xc09e, 0x21, 0 + .dw 0x84c0, 0xc09e, 0x84ff, 0xc09e, 0x21, 0 + .dw 0x8540, 0xc09e, 0x857f, 0xc09e, 0x21, 0 + .dw 0x85c0, 0xc09e, 0x85ff, 0xc09e, 0x21, 0 + .dw 0x8640, 0xc09e, 0x867f, 0xc09e, 0x21, 0 + .dw 0x86c0, 0xc09e, 0x86ff, 0xc09e, 0x21, 0 + .dw 0x8740, 0xc09e, 0x877f, 0xc09e, 0x21, 0 + .dw 0x87c0, 0xc09e, 0x87ff, 0xc09e, 0x21, 0 + .dw 0x8840, 0xc09e, 0x887f, 0xc09e, 0x21, 0 + .dw 0x88c0, 0xc09e, 0x88ff, 0xc09e, 0x21, 0 + .dw 0x8940, 0xc09e, 0x897f, 0xc09e, 0x21, 0 + .dw 0x89c0, 0xc09e, 0x89ff, 0xc09e, 0x21, 0 + .dw 0x8a40, 0xc09e, 0x8a7f, 0xc09e, 0x21, 0 + .dw 0x8ac0, 0xc09e, 0x8aff, 0xc09e, 0x21, 0 + .dw 0x8b40, 0xc09e, 0x8b7f, 0xc09e, 0x21, 0 + .dw 0x8bc0, 0xc09e, 0x8bff, 0xc09e, 0x21, 0 + .dw 0x8c40, 0xc09e, 0x8c7f, 0xc09e, 0x21, 0 + .dw 0x8cc0, 0xc09e, 0x8cff, 0xc09e, 0x21, 0 + .dw 0x8d40, 0xc09e, 0x8d7f, 0xc09e, 0x21, 0 + .dw 0x8dc0, 0xc09e, 0x8dff, 0xc09e, 0x21, 0 + .dw 0x8e40, 0xc09e, 0x8e7f, 0xc09e, 0x21, 0 + .dw 0x8ec0, 0xc09e, 0x8eff, 0xc09e, 0x21, 0 + .dw 0x8f40, 0xc09e, 0x8f7f, 0xc09e, 0x21, 0 + .dw 0x8fc0, 0xc09e, 0x8fff, 0xc09e, 0x21, 0 + .dw 0x9040, 0xc09e, 0x907f, 0xc09e, 0x21, 0 + .dw 0x90c0, 0xc09e, 0x90ff, 0xc09e, 0x21, 0 + .dw 0x9140, 0xc09e, 0x917f, 0xc09e, 0x21, 0 + .dw 0x91c0, 0xc09e, 0x91ff, 0xc09e, 0x21, 0 + .dw 0x9240, 0xc09e, 0x927f, 0xc09e, 0x21, 0 + .dw 0x92c0, 0xc09e, 0x92ff, 0xc09e, 0x21, 0 + .dw 0x9340, 0xc09e, 0x937f, 0xc09e, 0x21, 0 + .dw 0x93c0, 0xc09e, 0x93ff, 0xc09e, 0x21, 0 + .dw 0x9440, 0xc09e, 0x947f, 0xc09e, 0x21, 0 + .dw 0x94c0, 0xc09e, 0x94ff, 0xc09e, 0x21, 0 + .dw 0x9540, 0xc09e, 0x957f, 0xc09e, 0x21, 0 + .dw 0x95c0, 0xc09e, 0x95ff, 0xc09e, 0x21, 0 + .dw 0x9640, 0xc09e, 0x967f, 0xc09e, 0x21, 0 + .dw 0x96c0, 0xc09e, 0x96ff, 0xc09e, 0x21, 0 + .dw 0x9740, 0xc09e, 0x977f, 0xc09e, 0x21, 0 + .dw 0x97c0, 0xc09e, 0x97ff, 0xc09e, 0x21, 0 + .dw 0x9840, 0xc09e, 0x987f, 0xc09e, 0x21, 0 + .dw 0x98c0, 0xc09e, 0x98ff, 0xc09e, 0x21, 0 + .dw 0x9940, 0xc09e, 0x997f, 0xc09e, 0x21, 0 + .dw 0x99c0, 0xc09e, 0x9fff, 0xc09e, 0x21, 0 + .dw 0xa040, 0xc09e, 0xa07f, 0xc09e, 0x21, 0 + .dw 0xa0c0, 0xc09e, 0xa0ff, 0xc09e, 0x21, 0 + .dw 0xa140, 0xc09e, 0xa17f, 0xc09e, 0x21, 0 + .dw 0xa1c0, 0xc09e, 0xa1ff, 0xc09e, 0x21, 0 + .dw 0xa240, 0xc09e, 0xa27f, 0xc09e, 0x21, 0 + .dw 0xa2c0, 0xc09e, 0xa2ff, 0xc09e, 0x21, 0 + .dw 0xa340, 0xc09e, 0xa37f, 0xc09e, 0x21, 0 + .dw 0xa3c0, 0xc09e, 0xa3ff, 0xc09e, 0x21, 0 + .dw 0xa440, 0xc09e, 0xa47f, 0xc09e, 0x21, 0 + .dw 0xa4c0, 0xc09e, 0xa4ff, 0xc09e, 0x21, 0 + .dw 0xa540, 0xc09e, 0xa57f, 0xc09e, 0x21, 0 + .dw 0xa5c0, 0xc09e, 0xa5ff, 0xc09e, 0x21, 0 + .dw 0xa640, 0xc09e, 0xa67f, 0xc09e, 0x21, 0 + .dw 0xa6c0, 0xc09e, 0xa6ff, 0xc09e, 0x21, 0 + .dw 0xa740, 0xc09e, 0xa77f, 0xc09e, 0x21, 0 + .dw 0xa7c0, 0xc09e, 0xa7ff, 0xc09e, 0x21, 0 + .dw 0xa840, 0xc09e, 0xa87f, 0xc09e, 0x21, 0 + .dw 0xa8c0, 0xc09e, 0xa8ff, 0xc09e, 0x21, 0 + .dw 0xa940, 0xc09e, 0xa97f, 0xc09e, 0x21, 0 + .dw 0xa9c0, 0xc09e, 0xa9ff, 0xc09e, 0x21, 0 + .dw 0xaa40, 0xc09e, 0xaa7f, 0xc09e, 0x21, 0 + .dw 0xaac0, 0xc09e, 0xaaff, 0xc09e, 0x21, 0 + .dw 0xab40, 0xc09e, 0xab7f, 0xc09e, 0x21, 0 + .dw 0xabc0, 0xc09e, 0xabff, 0xc09e, 0x21, 0 + .dw 0xac40, 0xc09e, 0xac7f, 0xc09e, 0x21, 0 + .dw 0xacc0, 0xc09e, 0xacff, 0xc09e, 0x21, 0 + .dw 0xad40, 0xc09e, 0xad7f, 0xc09e, 0x21, 0 + .dw 0xadc0, 0xc09e, 0xadff, 0xc09e, 0x21, 0 + .dw 0xae40, 0xc09e, 0xae7f, 0xc09e, 0x21, 0 + .dw 0xaec0, 0xc09e, 0xaeff, 0xc09e, 0x21, 0 + .dw 0xaf40, 0xc09e, 0xaf7f, 0xc09e, 0x21, 0 + .dw 0xafc0, 0xc09e, 0xafff, 0xc09e, 0x21, 0 + .dw 0xb040, 0xc09e, 0xb07f, 0xc09e, 0x21, 0 + .dw 0xb0c0, 0xc09e, 0xb0ff, 0xc09e, 0x21, 0 + .dw 0xb140, 0xc09e, 0xb17f, 0xc09e, 0x21, 0 + .dw 0xb1c0, 0xc09e, 0xb1ff, 0xc09e, 0x21, 0 + .dw 0xb240, 0xc09e, 0xb27f, 0xc09e, 0x21, 0 + .dw 0xb2c0, 0xc09e, 0xb2ff, 0xc09e, 0x21, 0 + .dw 0xb340, 0xc09e, 0xb37f, 0xc09e, 0x21, 0 + .dw 0xb3c0, 0xc09e, 0xb3ff, 0xc09e, 0x21, 0 + .dw 0xb440, 0xc09e, 0xb47f, 0xc09e, 0x21, 0 + .dw 0xb4c0, 0xc09e, 0xb4ff, 0xc09e, 0x21, 0 + .dw 0xb540, 0xc09e, 0xb57f, 0xc09e, 0x21, 0 + .dw 0xb5c0, 0xc09e, 0xb5ff, 0xc09e, 0x21, 0 + .dw 0xb640, 0xc09e, 0xb67f, 0xc09e, 0x21, 0 + .dw 0xb6c0, 0xc09e, 0xb6ff, 0xc09e, 0x21, 0 + .dw 0xb740, 0xc09e, 0xb77f, 0xc09e, 0x21, 0 + .dw 0xb7c0, 0xc09e, 0xb7ff, 0xc09e, 0x21, 0 + .dw 0xb840, 0xc09e, 0xb87f, 0xc09e, 0x21, 0 + .dw 0xb8c0, 0xc09e, 0xb8ff, 0xc09e, 0x21, 0 + .dw 0xb940, 0xc09e, 0xb97f, 0xc09e, 0x21, 0 + .dw 0xb9c0, 0xc09e, 0xbfff, 0xc09e, 0x21, 0 + .dw 0xc040, 0xc09e, 0xc07f, 0xc09e, 0x21, 0 + .dw 0xc0c0, 0xc09e, 0xc0ff, 0xc09e, 0x21, 0 + .dw 0xc140, 0xc09e, 0xc17f, 0xc09e, 0x21, 0 + .dw 0xc1c0, 0xc09e, 0xc1ff, 0xc09e, 0x21, 0 + .dw 0xc240, 0xc09e, 0xc27f, 0xc09e, 0x21, 0 + .dw 0xc2c0, 0xc09e, 0xc2ff, 0xc09e, 0x21, 0 + .dw 0xc340, 0xc09e, 0xc37f, 0xc09e, 0x21, 0 + .dw 0xc3c0, 0xc09e, 0xc3ff, 0xc09e, 0x21, 0 + .dw 0xc440, 0xc09e, 0xc47f, 0xc09e, 0x21, 0 + .dw 0xc4c0, 0xc09e, 0xc4ff, 0xc09e, 0x21, 0 + .dw 0xc540, 0xc09e, 0xc57f, 0xc09e, 0x21, 0 + .dw 0xc5c0, 0xc09e, 0xc5ff, 0xc09e, 0x21, 0 + .dw 0xc640, 0xc09e, 0xc67f, 0xc09e, 0x21, 0 + .dw 0xc6c0, 0xc09e, 0xc6ff, 0xc09e, 0x21, 0 + .dw 0xc740, 0xc09e, 0xc77f, 0xc09e, 0x21, 0 + .dw 0xc7c0, 0xc09e, 0xc7ff, 0xc09e, 0x21, 0 + .dw 0xc840, 0xc09e, 0xc87f, 0xc09e, 0x21, 0 + .dw 0xc8c0, 0xc09e, 0xc8ff, 0xc09e, 0x21, 0 + .dw 0xc940, 0xc09e, 0xc97f, 0xc09e, 0x21, 0 + .dw 0xc9c0, 0xc09e, 0xc9ff, 0xc09e, 0x21, 0 + .dw 0xca40, 0xc09e, 0xca7f, 0xc09e, 0x21, 0 + .dw 0xcac0, 0xc09e, 0xcaff, 0xc09e, 0x21, 0 + .dw 0xcb40, 0xc09e, 0xcb7f, 0xc09e, 0x21, 0 + .dw 0xcbc0, 0xc09e, 0xcbff, 0xc09e, 0x21, 0 + .dw 0xcc40, 0xc09e, 0xcc7f, 0xc09e, 0x21, 0 + .dw 0xccc0, 0xc09e, 0xccff, 0xc09e, 0x21, 0 + .dw 0xcd40, 0xc09e, 0xcd7f, 0xc09e, 0x21, 0 + .dw 0xcdc0, 0xc09e, 0xcdff, 0xc09e, 0x21, 0 + .dw 0xce40, 0xc09e, 0xce7f, 0xc09e, 0x21, 0 + .dw 0xcec0, 0xc09e, 0xceff, 0xc09e, 0x21, 0 + .dw 0xcf40, 0xc09e, 0xcf7f, 0xc09e, 0x21, 0 + .dw 0xcfc0, 0xc09e, 0xcfff, 0xc09e, 0x21, 0 + .dw 0xd040, 0xc09e, 0xd07f, 0xc09e, 0x21, 0 + .dw 0xd0c0, 0xc09e, 0xd0ff, 0xc09e, 0x21, 0 + .dw 0xd140, 0xc09e, 0xd17f, 0xc09e, 0x21, 0 + .dw 0xd1c0, 0xc09e, 0xd1ff, 0xc09e, 0x21, 0 + .dw 0xd240, 0xc09e, 0xd27f, 0xc09e, 0x21, 0 + .dw 0xd2c0, 0xc09e, 0xd2ff, 0xc09e, 0x21, 0 + .dw 0xd340, 0xc09e, 0xd37f, 0xc09e, 0x21, 0 + .dw 0xd3c0, 0xc09e, 0xd3ff, 0xc09e, 0x21, 0 + .dw 0xd440, 0xc09e, 0xd47f, 0xc09e, 0x21, 0 + .dw 0xd4c0, 0xc09e, 0xd4ff, 0xc09e, 0x21, 0 + .dw 0xd540, 0xc09e, 0xd57f, 0xc09e, 0x21, 0 + .dw 0xd5c0, 0xc09e, 0xd5ff, 0xc09e, 0x21, 0 + .dw 0xd640, 0xc09e, 0xd67f, 0xc09e, 0x21, 0 + .dw 0xd6c0, 0xc09e, 0xd6ff, 0xc09e, 0x21, 0 + .dw 0xd740, 0xc09e, 0xd77f, 0xc09e, 0x21, 0 + .dw 0xd7c0, 0xc09e, 0xd7ff, 0xc09e, 0x21, 0 + .dw 0xd840, 0xc09e, 0xd87f, 0xc09e, 0x21, 0 + .dw 0xd8c0, 0xc09e, 0xd8ff, 0xc09e, 0x21, 0 + .dw 0xd940, 0xc09e, 0xd97f, 0xc09e, 0x21, 0 + .dw 0xd9c0, 0xc09e, 0xdfff, 0xc09e, 0x21, 0 + .dw 0xe040, 0xc09e, 0xe07f, 0xc09e, 0x21, 0 + .dw 0xe0c0, 0xc09e, 0xe0ff, 0xc09e, 0x21, 0 + .dw 0xe140, 0xc09e, 0xe17f, 0xc09e, 0x21, 0 + .dw 0xe1c0, 0xc09e, 0xe1ff, 0xc09e, 0x21, 0 + .dw 0xe240, 0xc09e, 0xe27f, 0xc09e, 0x21, 0 + .dw 0xe2c0, 0xc09e, 0xe2ff, 0xc09e, 0x21, 0 + .dw 0xe340, 0xc09e, 0xe37f, 0xc09e, 0x21, 0 + .dw 0xe3c0, 0xc09e, 0xe3ff, 0xc09e, 0x21, 0 + .dw 0xe440, 0xc09e, 0xe47f, 0xc09e, 0x21, 0 + .dw 0xe4c0, 0xc09e, 0xe4ff, 0xc09e, 0x21, 0 + .dw 0xe540, 0xc09e, 0xe57f, 0xc09e, 0x21, 0 + .dw 0xe5c0, 0xc09e, 0xe5ff, 0xc09e, 0x21, 0 + .dw 0xe640, 0xc09e, 0xe67f, 0xc09e, 0x21, 0 + .dw 0xe6c0, 0xc09e, 0xe6ff, 0xc09e, 0x21, 0 + .dw 0xe740, 0xc09e, 0xe77f, 0xc09e, 0x21, 0 + .dw 0xe7c0, 0xc09e, 0xe7ff, 0xc09e, 0x21, 0 + .dw 0xe840, 0xc09e, 0xe87f, 0xc09e, 0x21, 0 + .dw 0xe8c0, 0xc09e, 0xe8ff, 0xc09e, 0x21, 0 + .dw 0xe940, 0xc09e, 0xe97f, 0xc09e, 0x21, 0 + .dw 0xe9c0, 0xc09e, 0xe9ff, 0xc09e, 0x21, 0 + .dw 0xea40, 0xc09e, 0xea7f, 0xc09e, 0x21, 0 + .dw 0xeac0, 0xc09e, 0xeaff, 0xc09e, 0x21, 0 + .dw 0xeb40, 0xc09e, 0xeb7f, 0xc09e, 0x21, 0 + .dw 0xebc0, 0xc09e, 0xebff, 0xc09e, 0x21, 0 + .dw 0xec40, 0xc09e, 0xec7f, 0xc09e, 0x21, 0 + .dw 0xecc0, 0xc09e, 0xecff, 0xc09e, 0x21, 0 + .dw 0xed40, 0xc09e, 0xed7f, 0xc09e, 0x21, 0 + .dw 0xedc0, 0xc09e, 0xedff, 0xc09e, 0x21, 0 + .dw 0xee40, 0xc09e, 0xee7f, 0xc09e, 0x21, 0 + .dw 0xeec0, 0xc09e, 0xeeff, 0xc09e, 0x21, 0 + .dw 0xef40, 0xc09e, 0xef7f, 0xc09e, 0x21, 0 + .dw 0xefc0, 0xc09e, 0xefff, 0xc09e, 0x21, 0 + .dw 0xf040, 0xc09e, 0xf07f, 0xc09e, 0x21, 0 + .dw 0xf0c0, 0xc09e, 0xf0ff, 0xc09e, 0x21, 0 + .dw 0xf140, 0xc09e, 0xf17f, 0xc09e, 0x21, 0 + .dw 0xf1c0, 0xc09e, 0xf1ff, 0xc09e, 0x21, 0 + .dw 0xf240, 0xc09e, 0xf27f, 0xc09e, 0x21, 0 + .dw 0xf2c0, 0xc09e, 0xf2ff, 0xc09e, 0x21, 0 + .dw 0xf340, 0xc09e, 0xf37f, 0xc09e, 0x21, 0 + .dw 0xf3c0, 0xc09e, 0xf3ff, 0xc09e, 0x21, 0 + .dw 0xf440, 0xc09e, 0xf47f, 0xc09e, 0x21, 0 + .dw 0xf4c0, 0xc09e, 0xf4ff, 0xc09e, 0x21, 0 + .dw 0xf540, 0xc09e, 0xf57f, 0xc09e, 0x21, 0 + .dw 0xf5c0, 0xc09e, 0xf5ff, 0xc09e, 0x21, 0 + .dw 0xf640, 0xc09e, 0xf67f, 0xc09e, 0x21, 0 + .dw 0xf6c0, 0xc09e, 0xf6ff, 0xc09e, 0x21, 0 + .dw 0xf740, 0xc09e, 0xf77f, 0xc09e, 0x21, 0 + .dw 0xf7c0, 0xc09e, 0xf7ff, 0xc09e, 0x21, 0 + .dw 0xf840, 0xc09e, 0xf87f, 0xc09e, 0x21, 0 + .dw 0xf8c0, 0xc09e, 0xf8ff, 0xc09e, 0x21, 0 + .dw 0xf940, 0xc09e, 0xf97f, 0xc09e, 0x21, 0 + .dw 0xf9c0, 0xc09e, 0xffff, 0xc09e, 0x21, 0 + .dw 0x0040, 0xc09f, 0x007f, 0xc09f, 0x21, 0 + .dw 0x00c0, 0xc09f, 0x00ff, 0xc09f, 0x21, 0 + .dw 0x0140, 0xc09f, 0x017f, 0xc09f, 0x21, 0 + .dw 0x01c0, 0xc09f, 0x01ff, 0xc09f, 0x21, 0 + .dw 0x0240, 0xc09f, 0x027f, 0xc09f, 0x21, 0 + .dw 0x02c0, 0xc09f, 0x02ff, 0xc09f, 0x21, 0 + .dw 0x0340, 0xc09f, 0x037f, 0xc09f, 0x21, 0 + .dw 0x03c0, 0xc09f, 0x03ff, 0xc09f, 0x21, 0 + .dw 0x0440, 0xc09f, 0x047f, 0xc09f, 0x21, 0 + .dw 0x04c0, 0xc09f, 0x04ff, 0xc09f, 0x21, 0 + .dw 0x0540, 0xc09f, 0x057f, 0xc09f, 0x21, 0 + .dw 0x05c0, 0xc09f, 0x05ff, 0xc09f, 0x21, 0 + .dw 0x0640, 0xc09f, 0x067f, 0xc09f, 0x21, 0 + .dw 0x06c0, 0xc09f, 0x06ff, 0xc09f, 0x21, 0 + .dw 0x0740, 0xc09f, 0x077f, 0xc09f, 0x21, 0 + .dw 0x07c0, 0xc09f, 0x07ff, 0xc09f, 0x21, 0 + .dw 0x0840, 0xc09f, 0x087f, 0xc09f, 0x21, 0 + .dw 0x08c0, 0xc09f, 0x08ff, 0xc09f, 0x21, 0 + .dw 0x0940, 0xc09f, 0x097f, 0xc09f, 0x21, 0 + .dw 0x09c0, 0xc09f, 0x09ff, 0xc09f, 0x21, 0 + .dw 0x0a40, 0xc09f, 0x0a7f, 0xc09f, 0x21, 0 + .dw 0x0ac0, 0xc09f, 0x0aff, 0xc09f, 0x21, 0 + .dw 0x0b40, 0xc09f, 0x0b7f, 0xc09f, 0x21, 0 + .dw 0x0bc0, 0xc09f, 0x0bff, 0xc09f, 0x21, 0 + .dw 0x0c40, 0xc09f, 0x0c7f, 0xc09f, 0x21, 0 + .dw 0x0cc0, 0xc09f, 0x0cff, 0xc09f, 0x21, 0 + .dw 0x0d40, 0xc09f, 0x0d7f, 0xc09f, 0x21, 0 + .dw 0x0dc0, 0xc09f, 0x0dff, 0xc09f, 0x21, 0 + .dw 0x0e40, 0xc09f, 0x0e7f, 0xc09f, 0x21, 0 + .dw 0x0ec0, 0xc09f, 0x0eff, 0xc09f, 0x21, 0 + .dw 0x0f40, 0xc09f, 0x0f7f, 0xc09f, 0x21, 0 + .dw 0x0fc0, 0xc09f, 0x0fff, 0xc09f, 0x21, 0 + .dw 0x1040, 0xc09f, 0x107f, 0xc09f, 0x21, 0 + .dw 0x10c0, 0xc09f, 0x10ff, 0xc09f, 0x21, 0 + .dw 0x1140, 0xc09f, 0x117f, 0xc09f, 0x21, 0 + .dw 0x11c0, 0xc09f, 0x11ff, 0xc09f, 0x21, 0 + .dw 0x1240, 0xc09f, 0x127f, 0xc09f, 0x21, 0 + .dw 0x12c0, 0xc09f, 0x12ff, 0xc09f, 0x21, 0 + .dw 0x1340, 0xc09f, 0x137f, 0xc09f, 0x21, 0 + .dw 0x13c0, 0xc09f, 0x13ff, 0xc09f, 0x21, 0 + .dw 0x1440, 0xc09f, 0x147f, 0xc09f, 0x21, 0 + .dw 0x14c0, 0xc09f, 0x14ff, 0xc09f, 0x21, 0 + .dw 0x1540, 0xc09f, 0x157f, 0xc09f, 0x21, 0 + .dw 0x15c0, 0xc09f, 0x15ff, 0xc09f, 0x21, 0 + .dw 0x1640, 0xc09f, 0x167f, 0xc09f, 0x21, 0 + .dw 0x16c0, 0xc09f, 0x16ff, 0xc09f, 0x21, 0 + .dw 0x1740, 0xc09f, 0x177f, 0xc09f, 0x21, 0 + .dw 0x17c0, 0xc09f, 0x17ff, 0xc09f, 0x21, 0 + .dw 0x1840, 0xc09f, 0x187f, 0xc09f, 0x21, 0 + .dw 0x18c0, 0xc09f, 0x18ff, 0xc09f, 0x21, 0 + .dw 0x1940, 0xc09f, 0x197f, 0xc09f, 0x21, 0 + .dw 0x19c0, 0xc09f, 0x1fff, 0xc09f, 0x21, 0 + .dw 0x2040, 0xc09f, 0x207f, 0xc09f, 0x21, 0 + .dw 0x20c0, 0xc09f, 0x20ff, 0xc09f, 0x21, 0 + .dw 0x2140, 0xc09f, 0x217f, 0xc09f, 0x21, 0 + .dw 0x21c0, 0xc09f, 0x21ff, 0xc09f, 0x21, 0 + .dw 0x2240, 0xc09f, 0x227f, 0xc09f, 0x21, 0 + .dw 0x22c0, 0xc09f, 0x22ff, 0xc09f, 0x21, 0 + .dw 0x2340, 0xc09f, 0x237f, 0xc09f, 0x21, 0 + .dw 0x23c0, 0xc09f, 0x23ff, 0xc09f, 0x21, 0 + .dw 0x2440, 0xc09f, 0x247f, 0xc09f, 0x21, 0 + .dw 0x24c0, 0xc09f, 0x24ff, 0xc09f, 0x21, 0 + .dw 0x2540, 0xc09f, 0x257f, 0xc09f, 0x21, 0 + .dw 0x25c0, 0xc09f, 0x25ff, 0xc09f, 0x21, 0 + .dw 0x2640, 0xc09f, 0x267f, 0xc09f, 0x21, 0 + .dw 0x26c0, 0xc09f, 0x26ff, 0xc09f, 0x21, 0 + .dw 0x2740, 0xc09f, 0x277f, 0xc09f, 0x21, 0 + .dw 0x27c0, 0xc09f, 0x27ff, 0xc09f, 0x21, 0 + .dw 0x2840, 0xc09f, 0x287f, 0xc09f, 0x21, 0 + .dw 0x28c0, 0xc09f, 0x28ff, 0xc09f, 0x21, 0 + .dw 0x2940, 0xc09f, 0x297f, 0xc09f, 0x21, 0 + .dw 0x29c0, 0xc09f, 0x29ff, 0xc09f, 0x21, 0 + .dw 0x2a40, 0xc09f, 0x2a7f, 0xc09f, 0x21, 0 + .dw 0x2ac0, 0xc09f, 0x2aff, 0xc09f, 0x21, 0 + .dw 0x2b40, 0xc09f, 0x2b7f, 0xc09f, 0x21, 0 + .dw 0x2bc0, 0xc09f, 0x2bff, 0xc09f, 0x21, 0 + .dw 0x2c40, 0xc09f, 0x2c7f, 0xc09f, 0x21, 0 + .dw 0x2cc0, 0xc09f, 0x2cff, 0xc09f, 0x21, 0 + .dw 0x2d40, 0xc09f, 0x2d7f, 0xc09f, 0x21, 0 + .dw 0x2dc0, 0xc09f, 0x2dff, 0xc09f, 0x21, 0 + .dw 0x2e40, 0xc09f, 0x2e7f, 0xc09f, 0x21, 0 + .dw 0x2ec0, 0xc09f, 0x2eff, 0xc09f, 0x21, 0 + .dw 0x2f40, 0xc09f, 0x2f7f, 0xc09f, 0x21, 0 + .dw 0x2fc0, 0xc09f, 0x2fff, 0xc09f, 0x21, 0 + .dw 0x3040, 0xc09f, 0x307f, 0xc09f, 0x21, 0 + .dw 0x30c0, 0xc09f, 0x30ff, 0xc09f, 0x21, 0 + .dw 0x3140, 0xc09f, 0x317f, 0xc09f, 0x21, 0 + .dw 0x31c0, 0xc09f, 0x31ff, 0xc09f, 0x21, 0 + .dw 0x3240, 0xc09f, 0x327f, 0xc09f, 0x21, 0 + .dw 0x32c0, 0xc09f, 0x32ff, 0xc09f, 0x21, 0 + .dw 0x3340, 0xc09f, 0x337f, 0xc09f, 0x21, 0 + .dw 0x33c0, 0xc09f, 0x33ff, 0xc09f, 0x21, 0 + .dw 0x3440, 0xc09f, 0x347f, 0xc09f, 0x21, 0 + .dw 0x34c0, 0xc09f, 0x34ff, 0xc09f, 0x21, 0 + .dw 0x3540, 0xc09f, 0x357f, 0xc09f, 0x21, 0 + .dw 0x35c0, 0xc09f, 0x35ff, 0xc09f, 0x21, 0 + .dw 0x3640, 0xc09f, 0x367f, 0xc09f, 0x21, 0 + .dw 0x36c0, 0xc09f, 0x36ff, 0xc09f, 0x21, 0 + .dw 0x3740, 0xc09f, 0x377f, 0xc09f, 0x21, 0 + .dw 0x37c0, 0xc09f, 0x37ff, 0xc09f, 0x21, 0 + .dw 0x3840, 0xc09f, 0x387f, 0xc09f, 0x21, 0 + .dw 0x38c0, 0xc09f, 0x38ff, 0xc09f, 0x21, 0 + .dw 0x3940, 0xc09f, 0x397f, 0xc09f, 0x21, 0 + .dw 0x39c0, 0xc09f, 0x1fff, 0xc0c0, 0x21, 0 + .dw 0x3a00, 0xc0c0, 0x5fff, 0xc0c0, 0x21, 0 + .dw 0x7a00, 0xc0c0, 0x9fff, 0xc0c0, 0x21, 0 + .dw 0xba00, 0xc0c0, 0xdfff, 0xc0c0, 0x21, 0 + .dw 0xfa00, 0xc0c0, 0x1fff, 0xc0c1, 0x21, 0 + .dw 0x3a00, 0xc0c1, 0x5fff, 0xc0c1, 0x21, 0 + .dw 0x7a00, 0xc0c1, 0x9fff, 0xc0c1, 0x21, 0 + .dw 0xba00, 0xc0c1, 0xdfff, 0xc0c1, 0x21, 0 + .dw 0xfa00, 0xc0c1, 0x1fff, 0xc0c2, 0x21, 0 + .dw 0x3a00, 0xc0c2, 0x5fff, 0xc0c2, 0x21, 0 + .dw 0x7a00, 0xc0c2, 0x9fff, 0xc0c2, 0x21, 0 + .dw 0xba00, 0xc0c2, 0xdfff, 0xc0c2, 0x21, 0 + .dw 0xfa00, 0xc0c2, 0x1fff, 0xc0c3, 0x21, 0 + .dw 0x3a00, 0xc0c3, 0xffff, 0xc0c3, 0x21, 0 + .dw 0x1a00, 0xc0c4, 0x1fff, 0xc0c4, 0x21, 0 + .dw 0x3a00, 0xc0c4, 0x3fff, 0xc0c4, 0x21, 0 + .dw 0x5a00, 0xc0c4, 0x5fff, 0xc0c4, 0x21, 0 + .dw 0x7a00, 0xc0c4, 0x7fff, 0xc0c4, 0x21, 0 + .dw 0x9a00, 0xc0c4, 0x9fff, 0xc0c4, 0x21, 0 + .dw 0xba00, 0xc0c4, 0xbfff, 0xc0c4, 0x21, 0 + .dw 0xda00, 0xc0c4, 0xdfff, 0xc0c4, 0x21, 0 + .dw 0xfa00, 0xc0c4, 0xffff, 0xc0c4, 0x21, 0 + .dw 0x1a00, 0xc0c5, 0x1fff, 0xc0c5, 0x21, 0 + .dw 0x3a00, 0xc0c5, 0x3fff, 0xc0c5, 0x21, 0 + .dw 0x5a00, 0xc0c5, 0x5fff, 0xc0c5, 0x21, 0 + .dw 0x7a00, 0xc0c5, 0x7fff, 0xc0c5, 0x21, 0 + .dw 0x9a00, 0xc0c5, 0x9fff, 0xc0c5, 0x21, 0 + .dw 0xba00, 0xc0c5, 0xbfff, 0xc0c5, 0x21, 0 + .dw 0xda00, 0xc0c5, 0xdfff, 0xc0c5, 0x21, 0 + .dw 0xfa00, 0xc0c5, 0xffff, 0xc0c5, 0x21, 0 + .dw 0x1a00, 0xc0c6, 0x1fff, 0xc0c6, 0x21, 0 + .dw 0x3a00, 0xc0c6, 0x3fff, 0xc0c6, 0x21, 0 + .dw 0x5a00, 0xc0c6, 0x5fff, 0xc0c6, 0x21, 0 + .dw 0x7a00, 0xc0c6, 0x7fff, 0xc0c6, 0x21, 0 + .dw 0x9a00, 0xc0c6, 0x9fff, 0xc0c6, 0x21, 0 + .dw 0xba00, 0xc0c6, 0xbfff, 0xc0c6, 0x21, 0 + .dw 0xda00, 0xc0c6, 0xdfff, 0xc0c6, 0x21, 0 + .dw 0xfa00, 0xc0c6, 0xffff, 0xc0c6, 0x21, 0 + .dw 0x1a00, 0xc0c7, 0x1fff, 0xc0c7, 0x21, 0 + .dw 0x3a00, 0xc0c7, 0x1fff, 0xc0d0, 0x21, 0 + .dw 0x3a00, 0xc0d0, 0x5fff, 0xc0d0, 0x21, 0 + .dw 0x7a00, 0xc0d0, 0x9fff, 0xc0d0, 0x21, 0 + .dw 0xba00, 0xc0d0, 0xdfff, 0xc0d0, 0x21, 0 + .dw 0xfa00, 0xc0d0, 0x1fff, 0xc0d1, 0x21, 0 + .dw 0x3a00, 0xc0d1, 0x5fff, 0xc0d1, 0x21, 0 + .dw 0x7a00, 0xc0d1, 0x9fff, 0xc0d1, 0x21, 0 + .dw 0xba00, 0xc0d1, 0xdfff, 0xc0d1, 0x21, 0 + .dw 0xfa00, 0xc0d1, 0x1fff, 0xc0d2, 0x21, 0 + .dw 0x3a00, 0xc0d2, 0x5fff, 0xc0d2, 0x21, 0 + .dw 0x7a00, 0xc0d2, 0x9fff, 0xc0d2, 0x21, 0 + .dw 0xba00, 0xc0d2, 0xdfff, 0xc0d2, 0x21, 0 + .dw 0xfa00, 0xc0d2, 0xffff, 0xc0d3, 0x21, 0 + .dw 0x1a00, 0xc0d4, 0x1fff, 0xc0d4, 0x21, 0 + .dw 0x3a00, 0xc0d4, 0x3fff, 0xc0d4, 0x21, 0 + .dw 0x5a00, 0xc0d4, 0x5fff, 0xc0d4, 0x21, 0 + .dw 0x7a00, 0xc0d4, 0x7fff, 0xc0d4, 0x21, 0 + .dw 0x9a00, 0xc0d4, 0x9fff, 0xc0d4, 0x21, 0 + .dw 0xba00, 0xc0d4, 0xbfff, 0xc0d4, 0x21, 0 + .dw 0xda00, 0xc0d4, 0xdfff, 0xc0d4, 0x21, 0 + .dw 0xfa00, 0xc0d4, 0xffff, 0xc0d4, 0x21, 0 + .dw 0x1a00, 0xc0d5, 0x1fff, 0xc0d5, 0x21, 0 + .dw 0x3a00, 0xc0d5, 0x3fff, 0xc0d5, 0x21, 0 + .dw 0x5a00, 0xc0d5, 0x5fff, 0xc0d5, 0x21, 0 + .dw 0x7a00, 0xc0d5, 0x7fff, 0xc0d5, 0x21, 0 + .dw 0x9a00, 0xc0d5, 0x9fff, 0xc0d5, 0x21, 0 + .dw 0xba00, 0xc0d5, 0xbfff, 0xc0d5, 0x21, 0 + .dw 0xda00, 0xc0d5, 0xdfff, 0xc0d5, 0x21, 0 + .dw 0xfa00, 0xc0d5, 0xffff, 0xc0d5, 0x21, 0 + .dw 0x1a00, 0xc0d6, 0x1fff, 0xc0d6, 0x21, 0 + .dw 0x3a00, 0xc0d6, 0x3fff, 0xc0d6, 0x21, 0 + .dw 0x5a00, 0xc0d6, 0x5fff, 0xc0d6, 0x21, 0 + .dw 0x7a00, 0xc0d6, 0x7fff, 0xc0d6, 0x21, 0 + .dw 0x9a00, 0xc0d6, 0x9fff, 0xc0d6, 0x21, 0 + .dw 0xba00, 0xc0d6, 0xbfff, 0xc0d6, 0x21, 0 + .dw 0xda00, 0xc0d6, 0xdfff, 0xc0d6, 0x21, 0 + .dw 0xfa00, 0xc0d6, 0xffff, 0xc0d6, 0x21, 0 + .dw 0x1a00, 0xc0d7, 0x1fff, 0xc0d7, 0x21, 0 + .dw 0x3a00, 0xc0d7, 0xffff, 0xc0ff, 0x21, 0 + .dw 0x1a00, 0xc100, 0x1fff, 0xc100, 0x21, 0 + .dw 0x3a00, 0xc100, 0x3fff, 0xc100, 0x21, 0 + .dw 0x5a00, 0xc100, 0x5fff, 0xc100, 0x21, 0 + .dw 0x7a00, 0xc100, 0x7fff, 0xc100, 0x21, 0 + .dw 0x9a00, 0xc100, 0x9fff, 0xc100, 0x21, 0 + .dw 0xba00, 0xc100, 0xbfff, 0xc100, 0x21, 0 + .dw 0xda00, 0xc100, 0xdfff, 0xc100, 0x21, 0 + .dw 0xfa00, 0xc100, 0xffff, 0xc100, 0x21, 0 + .dw 0x1a00, 0xc101, 0x1fff, 0xc101, 0x21, 0 + .dw 0x3a00, 0xc101, 0x3fff, 0xc101, 0x21, 0 + .dw 0x5a00, 0xc101, 0x5fff, 0xc101, 0x21, 0 + .dw 0x7a00, 0xc101, 0x7fff, 0xc101, 0x21, 0 + .dw 0x9a00, 0xc101, 0x9fff, 0xc101, 0x21, 0 + .dw 0xba00, 0xc101, 0xbfff, 0xc101, 0x21, 0 + .dw 0xda00, 0xc101, 0xdfff, 0xc101, 0x21, 0 + .dw 0xfa00, 0xc101, 0xffff, 0xc101, 0x21, 0 + .dw 0x1a00, 0xc102, 0x1fff, 0xc102, 0x21, 0 + .dw 0x3a00, 0xc102, 0x3fff, 0xc102, 0x21, 0 + .dw 0x5a00, 0xc102, 0x5fff, 0xc102, 0x21, 0 + .dw 0x7a00, 0xc102, 0x7fff, 0xc102, 0x21, 0 + .dw 0x9a00, 0xc102, 0x9fff, 0xc102, 0x21, 0 + .dw 0xba00, 0xc102, 0xbfff, 0xc102, 0x21, 0 + .dw 0xda00, 0xc102, 0xdfff, 0xc102, 0x21, 0 + .dw 0xfa00, 0xc102, 0xffff, 0xc102, 0x21, 0 + .dw 0x1a00, 0xc103, 0x1fff, 0xc103, 0x21, 0 + .dw 0x3a00, 0xc103, 0xffff, 0xc103, 0x21, 0 + .dw 0x1a00, 0xc104, 0x1fff, 0xc104, 0x21, 0 + .dw 0x3a00, 0xc104, 0x3fff, 0xc104, 0x21, 0 + .dw 0x5a00, 0xc104, 0x5fff, 0xc104, 0x21, 0 + .dw 0x7a00, 0xc104, 0x7fff, 0xc104, 0x21, 0 + .dw 0x9a00, 0xc104, 0x9fff, 0xc104, 0x21, 0 + .dw 0xba00, 0xc104, 0xbfff, 0xc104, 0x21, 0 + .dw 0xda00, 0xc104, 0xdfff, 0xc104, 0x21, 0 + .dw 0xfa00, 0xc104, 0xffff, 0xc104, 0x21, 0 + .dw 0x1a00, 0xc105, 0x1fff, 0xc105, 0x21, 0 + .dw 0x3a00, 0xc105, 0x3fff, 0xc105, 0x21, 0 + .dw 0x5a00, 0xc105, 0x5fff, 0xc105, 0x21, 0 + .dw 0x7a00, 0xc105, 0x7fff, 0xc105, 0x21, 0 + .dw 0x9a00, 0xc105, 0x9fff, 0xc105, 0x21, 0 + .dw 0xba00, 0xc105, 0xbfff, 0xc105, 0x21, 0 + .dw 0xda00, 0xc105, 0xdfff, 0xc105, 0x21, 0 + .dw 0xfa00, 0xc105, 0xffff, 0xc105, 0x21, 0 + .dw 0x1a00, 0xc106, 0x1fff, 0xc106, 0x21, 0 + .dw 0x3a00, 0xc106, 0x3fff, 0xc106, 0x21, 0 + .dw 0x5a00, 0xc106, 0x5fff, 0xc106, 0x21, 0 + .dw 0x7a00, 0xc106, 0x7fff, 0xc106, 0x21, 0 + .dw 0x9a00, 0xc106, 0x9fff, 0xc106, 0x21, 0 + .dw 0xba00, 0xc106, 0xbfff, 0xc106, 0x21, 0 + .dw 0xda00, 0xc106, 0xdfff, 0xc106, 0x21, 0 + .dw 0xfa00, 0xc106, 0xffff, 0xc106, 0x21, 0 + .dw 0x1a00, 0xc107, 0x1fff, 0xc107, 0x21, 0 + .dw 0x3a00, 0xc107, 0x1fff, 0xc108, 0x21, 0 + .dw 0x2040, 0xc108, 0x207f, 0xc108, 0x21, 0 + .dw 0x20c0, 0xc108, 0x20ff, 0xc108, 0x21, 0 + .dw 0x2140, 0xc108, 0x217f, 0xc108, 0x21, 0 + .dw 0x21c0, 0xc108, 0x21ff, 0xc108, 0x21, 0 + .dw 0x2240, 0xc108, 0x227f, 0xc108, 0x21, 0 + .dw 0x22c0, 0xc108, 0x22ff, 0xc108, 0x21, 0 + .dw 0x2340, 0xc108, 0x237f, 0xc108, 0x21, 0 + .dw 0x23c0, 0xc108, 0x23ff, 0xc108, 0x21, 0 + .dw 0x2440, 0xc108, 0x247f, 0xc108, 0x21, 0 + .dw 0x24c0, 0xc108, 0x24ff, 0xc108, 0x21, 0 + .dw 0x2540, 0xc108, 0x257f, 0xc108, 0x21, 0 + .dw 0x25c0, 0xc108, 0x25ff, 0xc108, 0x21, 0 + .dw 0x2640, 0xc108, 0x267f, 0xc108, 0x21, 0 + .dw 0x26c0, 0xc108, 0x26ff, 0xc108, 0x21, 0 + .dw 0x2740, 0xc108, 0x277f, 0xc108, 0x21, 0 + .dw 0x27c0, 0xc108, 0x27ff, 0xc108, 0x21, 0 + .dw 0x2840, 0xc108, 0x287f, 0xc108, 0x21, 0 + .dw 0x28c0, 0xc108, 0x28ff, 0xc108, 0x21, 0 + .dw 0x2940, 0xc108, 0x297f, 0xc108, 0x21, 0 + .dw 0x29c0, 0xc108, 0x29ff, 0xc108, 0x21, 0 + .dw 0x2a40, 0xc108, 0x2a7f, 0xc108, 0x21, 0 + .dw 0x2ac0, 0xc108, 0x2aff, 0xc108, 0x21, 0 + .dw 0x2b40, 0xc108, 0x2b7f, 0xc108, 0x21, 0 + .dw 0x2bc0, 0xc108, 0x2bff, 0xc108, 0x21, 0 + .dw 0x2c40, 0xc108, 0x2c7f, 0xc108, 0x21, 0 + .dw 0x2cc0, 0xc108, 0x2cff, 0xc108, 0x21, 0 + .dw 0x2d40, 0xc108, 0x2d7f, 0xc108, 0x21, 0 + .dw 0x2dc0, 0xc108, 0x2dff, 0xc108, 0x21, 0 + .dw 0x2e40, 0xc108, 0x2e7f, 0xc108, 0x21, 0 + .dw 0x2ec0, 0xc108, 0x2eff, 0xc108, 0x21, 0 + .dw 0x2f40, 0xc108, 0x2f7f, 0xc108, 0x21, 0 + .dw 0x2fc0, 0xc108, 0x2fff, 0xc108, 0x21, 0 + .dw 0x3040, 0xc108, 0x307f, 0xc108, 0x21, 0 + .dw 0x30c0, 0xc108, 0x30ff, 0xc108, 0x21, 0 + .dw 0x3140, 0xc108, 0x317f, 0xc108, 0x21, 0 + .dw 0x31c0, 0xc108, 0x31ff, 0xc108, 0x21, 0 + .dw 0x3240, 0xc108, 0x327f, 0xc108, 0x21, 0 + .dw 0x32c0, 0xc108, 0x32ff, 0xc108, 0x21, 0 + .dw 0x3340, 0xc108, 0x337f, 0xc108, 0x21, 0 + .dw 0x33c0, 0xc108, 0x33ff, 0xc108, 0x21, 0 + .dw 0x3440, 0xc108, 0x347f, 0xc108, 0x21, 0 + .dw 0x34c0, 0xc108, 0x34ff, 0xc108, 0x21, 0 + .dw 0x3540, 0xc108, 0x357f, 0xc108, 0x21, 0 + .dw 0x35c0, 0xc108, 0x35ff, 0xc108, 0x21, 0 + .dw 0x3640, 0xc108, 0x367f, 0xc108, 0x21, 0 + .dw 0x36c0, 0xc108, 0x36ff, 0xc108, 0x21, 0 + .dw 0x3740, 0xc108, 0x377f, 0xc108, 0x21, 0 + .dw 0x37c0, 0xc108, 0x37ff, 0xc108, 0x21, 0 + .dw 0x3840, 0xc108, 0x387f, 0xc108, 0x21, 0 + .dw 0x38c0, 0xc108, 0x38ff, 0xc108, 0x21, 0 + .dw 0x3940, 0xc108, 0x397f, 0xc108, 0x21, 0 + .dw 0x39c0, 0xc108, 0x5fff, 0xc108, 0x21, 0 + .dw 0x6040, 0xc108, 0x607f, 0xc108, 0x21, 0 + .dw 0x60c0, 0xc108, 0x60ff, 0xc108, 0x21, 0 + .dw 0x6140, 0xc108, 0x617f, 0xc108, 0x21, 0 + .dw 0x61c0, 0xc108, 0x61ff, 0xc108, 0x21, 0 + .dw 0x6240, 0xc108, 0x627f, 0xc108, 0x21, 0 + .dw 0x62c0, 0xc108, 0x62ff, 0xc108, 0x21, 0 + .dw 0x6340, 0xc108, 0x637f, 0xc108, 0x21, 0 + .dw 0x63c0, 0xc108, 0x63ff, 0xc108, 0x21, 0 + .dw 0x6440, 0xc108, 0x647f, 0xc108, 0x21, 0 + .dw 0x64c0, 0xc108, 0x64ff, 0xc108, 0x21, 0 + .dw 0x6540, 0xc108, 0x657f, 0xc108, 0x21, 0 + .dw 0x65c0, 0xc108, 0x65ff, 0xc108, 0x21, 0 + .dw 0x6640, 0xc108, 0x667f, 0xc108, 0x21, 0 + .dw 0x66c0, 0xc108, 0x66ff, 0xc108, 0x21, 0 + .dw 0x6740, 0xc108, 0x677f, 0xc108, 0x21, 0 + .dw 0x67c0, 0xc108, 0x67ff, 0xc108, 0x21, 0 + .dw 0x6840, 0xc108, 0x687f, 0xc108, 0x21, 0 + .dw 0x68c0, 0xc108, 0x68ff, 0xc108, 0x21, 0 + .dw 0x6940, 0xc108, 0x697f, 0xc108, 0x21, 0 + .dw 0x69c0, 0xc108, 0x69ff, 0xc108, 0x21, 0 + .dw 0x6a40, 0xc108, 0x6a7f, 0xc108, 0x21, 0 + .dw 0x6ac0, 0xc108, 0x6aff, 0xc108, 0x21, 0 + .dw 0x6b40, 0xc108, 0x6b7f, 0xc108, 0x21, 0 + .dw 0x6bc0, 0xc108, 0x6bff, 0xc108, 0x21, 0 + .dw 0x6c40, 0xc108, 0x6c7f, 0xc108, 0x21, 0 + .dw 0x6cc0, 0xc108, 0x6cff, 0xc108, 0x21, 0 + .dw 0x6d40, 0xc108, 0x6d7f, 0xc108, 0x21, 0 + .dw 0x6dc0, 0xc108, 0x6dff, 0xc108, 0x21, 0 + .dw 0x6e40, 0xc108, 0x6e7f, 0xc108, 0x21, 0 + .dw 0x6ec0, 0xc108, 0x6eff, 0xc108, 0x21, 0 + .dw 0x6f40, 0xc108, 0x6f7f, 0xc108, 0x21, 0 + .dw 0x6fc0, 0xc108, 0x6fff, 0xc108, 0x21, 0 + .dw 0x7040, 0xc108, 0x707f, 0xc108, 0x21, 0 + .dw 0x70c0, 0xc108, 0x70ff, 0xc108, 0x21, 0 + .dw 0x7140, 0xc108, 0x717f, 0xc108, 0x21, 0 + .dw 0x71c0, 0xc108, 0x71ff, 0xc108, 0x21, 0 + .dw 0x7240, 0xc108, 0x727f, 0xc108, 0x21, 0 + .dw 0x72c0, 0xc108, 0x72ff, 0xc108, 0x21, 0 + .dw 0x7340, 0xc108, 0x737f, 0xc108, 0x21, 0 + .dw 0x73c0, 0xc108, 0x73ff, 0xc108, 0x21, 0 + .dw 0x7440, 0xc108, 0x747f, 0xc108, 0x21, 0 + .dw 0x74c0, 0xc108, 0x74ff, 0xc108, 0x21, 0 + .dw 0x7540, 0xc108, 0x757f, 0xc108, 0x21, 0 + .dw 0x75c0, 0xc108, 0x75ff, 0xc108, 0x21, 0 + .dw 0x7640, 0xc108, 0x767f, 0xc108, 0x21, 0 + .dw 0x76c0, 0xc108, 0x76ff, 0xc108, 0x21, 0 + .dw 0x7740, 0xc108, 0x777f, 0xc108, 0x21, 0 + .dw 0x77c0, 0xc108, 0x77ff, 0xc108, 0x21, 0 + .dw 0x7840, 0xc108, 0x787f, 0xc108, 0x21, 0 + .dw 0x78c0, 0xc108, 0x78ff, 0xc108, 0x21, 0 + .dw 0x7940, 0xc108, 0x797f, 0xc108, 0x21, 0 + .dw 0x79c0, 0xc108, 0x9fff, 0xc108, 0x21, 0 + .dw 0xa040, 0xc108, 0xa07f, 0xc108, 0x21, 0 + .dw 0xa0c0, 0xc108, 0xa0ff, 0xc108, 0x21, 0 + .dw 0xa140, 0xc108, 0xa17f, 0xc108, 0x21, 0 + .dw 0xa1c0, 0xc108, 0xa1ff, 0xc108, 0x21, 0 + .dw 0xa240, 0xc108, 0xa27f, 0xc108, 0x21, 0 + .dw 0xa2c0, 0xc108, 0xa2ff, 0xc108, 0x21, 0 + .dw 0xa340, 0xc108, 0xa37f, 0xc108, 0x21, 0 + .dw 0xa3c0, 0xc108, 0xa3ff, 0xc108, 0x21, 0 + .dw 0xa440, 0xc108, 0xa47f, 0xc108, 0x21, 0 + .dw 0xa4c0, 0xc108, 0xa4ff, 0xc108, 0x21, 0 + .dw 0xa540, 0xc108, 0xa57f, 0xc108, 0x21, 0 + .dw 0xa5c0, 0xc108, 0xa5ff, 0xc108, 0x21, 0 + .dw 0xa640, 0xc108, 0xa67f, 0xc108, 0x21, 0 + .dw 0xa6c0, 0xc108, 0xa6ff, 0xc108, 0x21, 0 + .dw 0xa740, 0xc108, 0xa77f, 0xc108, 0x21, 0 + .dw 0xa7c0, 0xc108, 0xa7ff, 0xc108, 0x21, 0 + .dw 0xa840, 0xc108, 0xa87f, 0xc108, 0x21, 0 + .dw 0xa8c0, 0xc108, 0xa8ff, 0xc108, 0x21, 0 + .dw 0xa940, 0xc108, 0xa97f, 0xc108, 0x21, 0 + .dw 0xa9c0, 0xc108, 0xa9ff, 0xc108, 0x21, 0 + .dw 0xaa40, 0xc108, 0xaa7f, 0xc108, 0x21, 0 + .dw 0xaac0, 0xc108, 0xaaff, 0xc108, 0x21, 0 + .dw 0xab40, 0xc108, 0xab7f, 0xc108, 0x21, 0 + .dw 0xabc0, 0xc108, 0xabff, 0xc108, 0x21, 0 + .dw 0xac40, 0xc108, 0xac7f, 0xc108, 0x21, 0 + .dw 0xacc0, 0xc108, 0xacff, 0xc108, 0x21, 0 + .dw 0xad40, 0xc108, 0xad7f, 0xc108, 0x21, 0 + .dw 0xadc0, 0xc108, 0xadff, 0xc108, 0x21, 0 + .dw 0xae40, 0xc108, 0xae7f, 0xc108, 0x21, 0 + .dw 0xaec0, 0xc108, 0xaeff, 0xc108, 0x21, 0 + .dw 0xaf40, 0xc108, 0xaf7f, 0xc108, 0x21, 0 + .dw 0xafc0, 0xc108, 0xafff, 0xc108, 0x21, 0 + .dw 0xb040, 0xc108, 0xb07f, 0xc108, 0x21, 0 + .dw 0xb0c0, 0xc108, 0xb0ff, 0xc108, 0x21, 0 + .dw 0xb140, 0xc108, 0xb17f, 0xc108, 0x21, 0 + .dw 0xb1c0, 0xc108, 0xb1ff, 0xc108, 0x21, 0 + .dw 0xb240, 0xc108, 0xb27f, 0xc108, 0x21, 0 + .dw 0xb2c0, 0xc108, 0xb2ff, 0xc108, 0x21, 0 + .dw 0xb340, 0xc108, 0xb37f, 0xc108, 0x21, 0 + .dw 0xb3c0, 0xc108, 0xb3ff, 0xc108, 0x21, 0 + .dw 0xb440, 0xc108, 0xb47f, 0xc108, 0x21, 0 + .dw 0xb4c0, 0xc108, 0xb4ff, 0xc108, 0x21, 0 + .dw 0xb540, 0xc108, 0xb57f, 0xc108, 0x21, 0 + .dw 0xb5c0, 0xc108, 0xb5ff, 0xc108, 0x21, 0 + .dw 0xb640, 0xc108, 0xb67f, 0xc108, 0x21, 0 + .dw 0xb6c0, 0xc108, 0xb6ff, 0xc108, 0x21, 0 + .dw 0xb740, 0xc108, 0xb77f, 0xc108, 0x21, 0 + .dw 0xb7c0, 0xc108, 0xb7ff, 0xc108, 0x21, 0 + .dw 0xb840, 0xc108, 0xb87f, 0xc108, 0x21, 0 + .dw 0xb8c0, 0xc108, 0xb8ff, 0xc108, 0x21, 0 + .dw 0xb940, 0xc108, 0xb97f, 0xc108, 0x21, 0 + .dw 0xb9c0, 0xc108, 0xdfff, 0xc108, 0x21, 0 + .dw 0xe040, 0xc108, 0xe07f, 0xc108, 0x21, 0 + .dw 0xe0c0, 0xc108, 0xe0ff, 0xc108, 0x21, 0 + .dw 0xe140, 0xc108, 0xe17f, 0xc108, 0x21, 0 + .dw 0xe1c0, 0xc108, 0xe1ff, 0xc108, 0x21, 0 + .dw 0xe240, 0xc108, 0xe27f, 0xc108, 0x21, 0 + .dw 0xe2c0, 0xc108, 0xe2ff, 0xc108, 0x21, 0 + .dw 0xe340, 0xc108, 0xe37f, 0xc108, 0x21, 0 + .dw 0xe3c0, 0xc108, 0xe3ff, 0xc108, 0x21, 0 + .dw 0xe440, 0xc108, 0xe47f, 0xc108, 0x21, 0 + .dw 0xe4c0, 0xc108, 0xe4ff, 0xc108, 0x21, 0 + .dw 0xe540, 0xc108, 0xe57f, 0xc108, 0x21, 0 + .dw 0xe5c0, 0xc108, 0xe5ff, 0xc108, 0x21, 0 + .dw 0xe640, 0xc108, 0xe67f, 0xc108, 0x21, 0 + .dw 0xe6c0, 0xc108, 0xe6ff, 0xc108, 0x21, 0 + .dw 0xe740, 0xc108, 0xe77f, 0xc108, 0x21, 0 + .dw 0xe7c0, 0xc108, 0xe7ff, 0xc108, 0x21, 0 + .dw 0xe840, 0xc108, 0xe87f, 0xc108, 0x21, 0 + .dw 0xe8c0, 0xc108, 0xe8ff, 0xc108, 0x21, 0 + .dw 0xe940, 0xc108, 0xe97f, 0xc108, 0x21, 0 + .dw 0xe9c0, 0xc108, 0xe9ff, 0xc108, 0x21, 0 + .dw 0xea40, 0xc108, 0xea7f, 0xc108, 0x21, 0 + .dw 0xeac0, 0xc108, 0xeaff, 0xc108, 0x21, 0 + .dw 0xeb40, 0xc108, 0xeb7f, 0xc108, 0x21, 0 + .dw 0xebc0, 0xc108, 0xebff, 0xc108, 0x21, 0 + .dw 0xec40, 0xc108, 0xec7f, 0xc108, 0x21, 0 + .dw 0xecc0, 0xc108, 0xecff, 0xc108, 0x21, 0 + .dw 0xed40, 0xc108, 0xed7f, 0xc108, 0x21, 0 + .dw 0xedc0, 0xc108, 0xedff, 0xc108, 0x21, 0 + .dw 0xee40, 0xc108, 0xee7f, 0xc108, 0x21, 0 + .dw 0xeec0, 0xc108, 0xeeff, 0xc108, 0x21, 0 + .dw 0xef40, 0xc108, 0xef7f, 0xc108, 0x21, 0 + .dw 0xefc0, 0xc108, 0xefff, 0xc108, 0x21, 0 + .dw 0xf040, 0xc108, 0xf07f, 0xc108, 0x21, 0 + .dw 0xf0c0, 0xc108, 0xf0ff, 0xc108, 0x21, 0 + .dw 0xf140, 0xc108, 0xf17f, 0xc108, 0x21, 0 + .dw 0xf1c0, 0xc108, 0xf1ff, 0xc108, 0x21, 0 + .dw 0xf240, 0xc108, 0xf27f, 0xc108, 0x21, 0 + .dw 0xf2c0, 0xc108, 0xf2ff, 0xc108, 0x21, 0 + .dw 0xf340, 0xc108, 0xf37f, 0xc108, 0x21, 0 + .dw 0xf3c0, 0xc108, 0xf3ff, 0xc108, 0x21, 0 + .dw 0xf440, 0xc108, 0xf47f, 0xc108, 0x21, 0 + .dw 0xf4c0, 0xc108, 0xf4ff, 0xc108, 0x21, 0 + .dw 0xf540, 0xc108, 0xf57f, 0xc108, 0x21, 0 + .dw 0xf5c0, 0xc108, 0xf5ff, 0xc108, 0x21, 0 + .dw 0xf640, 0xc108, 0xf67f, 0xc108, 0x21, 0 + .dw 0xf6c0, 0xc108, 0xf6ff, 0xc108, 0x21, 0 + .dw 0xf740, 0xc108, 0xf77f, 0xc108, 0x21, 0 + .dw 0xf7c0, 0xc108, 0xf7ff, 0xc108, 0x21, 0 + .dw 0xf840, 0xc108, 0xf87f, 0xc108, 0x21, 0 + .dw 0xf8c0, 0xc108, 0xf8ff, 0xc108, 0x21, 0 + .dw 0xf940, 0xc108, 0xf97f, 0xc108, 0x21, 0 + .dw 0xf9c0, 0xc108, 0x1fff, 0xc109, 0x21, 0 + .dw 0x2040, 0xc109, 0x207f, 0xc109, 0x21, 0 + .dw 0x20c0, 0xc109, 0x20ff, 0xc109, 0x21, 0 + .dw 0x2140, 0xc109, 0x217f, 0xc109, 0x21, 0 + .dw 0x21c0, 0xc109, 0x21ff, 0xc109, 0x21, 0 + .dw 0x2240, 0xc109, 0x227f, 0xc109, 0x21, 0 + .dw 0x22c0, 0xc109, 0x22ff, 0xc109, 0x21, 0 + .dw 0x2340, 0xc109, 0x237f, 0xc109, 0x21, 0 + .dw 0x23c0, 0xc109, 0x23ff, 0xc109, 0x21, 0 + .dw 0x2440, 0xc109, 0x247f, 0xc109, 0x21, 0 + .dw 0x24c0, 0xc109, 0x24ff, 0xc109, 0x21, 0 + .dw 0x2540, 0xc109, 0x257f, 0xc109, 0x21, 0 + .dw 0x25c0, 0xc109, 0x25ff, 0xc109, 0x21, 0 + .dw 0x2640, 0xc109, 0x267f, 0xc109, 0x21, 0 + .dw 0x26c0, 0xc109, 0x26ff, 0xc109, 0x21, 0 + .dw 0x2740, 0xc109, 0x277f, 0xc109, 0x21, 0 + .dw 0x27c0, 0xc109, 0x27ff, 0xc109, 0x21, 0 + .dw 0x2840, 0xc109, 0x287f, 0xc109, 0x21, 0 + .dw 0x28c0, 0xc109, 0x28ff, 0xc109, 0x21, 0 + .dw 0x2940, 0xc109, 0x297f, 0xc109, 0x21, 0 + .dw 0x29c0, 0xc109, 0x29ff, 0xc109, 0x21, 0 + .dw 0x2a40, 0xc109, 0x2a7f, 0xc109, 0x21, 0 + .dw 0x2ac0, 0xc109, 0x2aff, 0xc109, 0x21, 0 + .dw 0x2b40, 0xc109, 0x2b7f, 0xc109, 0x21, 0 + .dw 0x2bc0, 0xc109, 0x2bff, 0xc109, 0x21, 0 + .dw 0x2c40, 0xc109, 0x2c7f, 0xc109, 0x21, 0 + .dw 0x2cc0, 0xc109, 0x2cff, 0xc109, 0x21, 0 + .dw 0x2d40, 0xc109, 0x2d7f, 0xc109, 0x21, 0 + .dw 0x2dc0, 0xc109, 0x2dff, 0xc109, 0x21, 0 + .dw 0x2e40, 0xc109, 0x2e7f, 0xc109, 0x21, 0 + .dw 0x2ec0, 0xc109, 0x2eff, 0xc109, 0x21, 0 + .dw 0x2f40, 0xc109, 0x2f7f, 0xc109, 0x21, 0 + .dw 0x2fc0, 0xc109, 0x2fff, 0xc109, 0x21, 0 + .dw 0x3040, 0xc109, 0x307f, 0xc109, 0x21, 0 + .dw 0x30c0, 0xc109, 0x30ff, 0xc109, 0x21, 0 + .dw 0x3140, 0xc109, 0x317f, 0xc109, 0x21, 0 + .dw 0x31c0, 0xc109, 0x31ff, 0xc109, 0x21, 0 + .dw 0x3240, 0xc109, 0x327f, 0xc109, 0x21, 0 + .dw 0x32c0, 0xc109, 0x32ff, 0xc109, 0x21, 0 + .dw 0x3340, 0xc109, 0x337f, 0xc109, 0x21, 0 + .dw 0x33c0, 0xc109, 0x33ff, 0xc109, 0x21, 0 + .dw 0x3440, 0xc109, 0x347f, 0xc109, 0x21, 0 + .dw 0x34c0, 0xc109, 0x34ff, 0xc109, 0x21, 0 + .dw 0x3540, 0xc109, 0x357f, 0xc109, 0x21, 0 + .dw 0x35c0, 0xc109, 0x35ff, 0xc109, 0x21, 0 + .dw 0x3640, 0xc109, 0x367f, 0xc109, 0x21, 0 + .dw 0x36c0, 0xc109, 0x36ff, 0xc109, 0x21, 0 + .dw 0x3740, 0xc109, 0x377f, 0xc109, 0x21, 0 + .dw 0x37c0, 0xc109, 0x37ff, 0xc109, 0x21, 0 + .dw 0x3840, 0xc109, 0x387f, 0xc109, 0x21, 0 + .dw 0x38c0, 0xc109, 0x38ff, 0xc109, 0x21, 0 + .dw 0x3940, 0xc109, 0x397f, 0xc109, 0x21, 0 + .dw 0x39c0, 0xc109, 0x5fff, 0xc109, 0x21, 0 + .dw 0x6040, 0xc109, 0x607f, 0xc109, 0x21, 0 + .dw 0x60c0, 0xc109, 0x60ff, 0xc109, 0x21, 0 + .dw 0x6140, 0xc109, 0x617f, 0xc109, 0x21, 0 + .dw 0x61c0, 0xc109, 0x61ff, 0xc109, 0x21, 0 + .dw 0x6240, 0xc109, 0x627f, 0xc109, 0x21, 0 + .dw 0x62c0, 0xc109, 0x62ff, 0xc109, 0x21, 0 + .dw 0x6340, 0xc109, 0x637f, 0xc109, 0x21, 0 + .dw 0x63c0, 0xc109, 0x63ff, 0xc109, 0x21, 0 + .dw 0x6440, 0xc109, 0x647f, 0xc109, 0x21, 0 + .dw 0x64c0, 0xc109, 0x64ff, 0xc109, 0x21, 0 + .dw 0x6540, 0xc109, 0x657f, 0xc109, 0x21, 0 + .dw 0x65c0, 0xc109, 0x65ff, 0xc109, 0x21, 0 + .dw 0x6640, 0xc109, 0x667f, 0xc109, 0x21, 0 + .dw 0x66c0, 0xc109, 0x66ff, 0xc109, 0x21, 0 + .dw 0x6740, 0xc109, 0x677f, 0xc109, 0x21, 0 + .dw 0x67c0, 0xc109, 0x67ff, 0xc109, 0x21, 0 + .dw 0x6840, 0xc109, 0x687f, 0xc109, 0x21, 0 + .dw 0x68c0, 0xc109, 0x68ff, 0xc109, 0x21, 0 + .dw 0x6940, 0xc109, 0x697f, 0xc109, 0x21, 0 + .dw 0x69c0, 0xc109, 0x69ff, 0xc109, 0x21, 0 + .dw 0x6a40, 0xc109, 0x6a7f, 0xc109, 0x21, 0 + .dw 0x6ac0, 0xc109, 0x6aff, 0xc109, 0x21, 0 + .dw 0x6b40, 0xc109, 0x6b7f, 0xc109, 0x21, 0 + .dw 0x6bc0, 0xc109, 0x6bff, 0xc109, 0x21, 0 + .dw 0x6c40, 0xc109, 0x6c7f, 0xc109, 0x21, 0 + .dw 0x6cc0, 0xc109, 0x6cff, 0xc109, 0x21, 0 + .dw 0x6d40, 0xc109, 0x6d7f, 0xc109, 0x21, 0 + .dw 0x6dc0, 0xc109, 0x6dff, 0xc109, 0x21, 0 + .dw 0x6e40, 0xc109, 0x6e7f, 0xc109, 0x21, 0 + .dw 0x6ec0, 0xc109, 0x6eff, 0xc109, 0x21, 0 + .dw 0x6f40, 0xc109, 0x6f7f, 0xc109, 0x21, 0 + .dw 0x6fc0, 0xc109, 0x6fff, 0xc109, 0x21, 0 + .dw 0x7040, 0xc109, 0x707f, 0xc109, 0x21, 0 + .dw 0x70c0, 0xc109, 0x70ff, 0xc109, 0x21, 0 + .dw 0x7140, 0xc109, 0x717f, 0xc109, 0x21, 0 + .dw 0x71c0, 0xc109, 0x71ff, 0xc109, 0x21, 0 + .dw 0x7240, 0xc109, 0x727f, 0xc109, 0x21, 0 + .dw 0x72c0, 0xc109, 0x72ff, 0xc109, 0x21, 0 + .dw 0x7340, 0xc109, 0x737f, 0xc109, 0x21, 0 + .dw 0x73c0, 0xc109, 0x73ff, 0xc109, 0x21, 0 + .dw 0x7440, 0xc109, 0x747f, 0xc109, 0x21, 0 + .dw 0x74c0, 0xc109, 0x74ff, 0xc109, 0x21, 0 + .dw 0x7540, 0xc109, 0x757f, 0xc109, 0x21, 0 + .dw 0x75c0, 0xc109, 0x75ff, 0xc109, 0x21, 0 + .dw 0x7640, 0xc109, 0x767f, 0xc109, 0x21, 0 + .dw 0x76c0, 0xc109, 0x76ff, 0xc109, 0x21, 0 + .dw 0x7740, 0xc109, 0x777f, 0xc109, 0x21, 0 + .dw 0x77c0, 0xc109, 0x77ff, 0xc109, 0x21, 0 + .dw 0x7840, 0xc109, 0x787f, 0xc109, 0x21, 0 + .dw 0x78c0, 0xc109, 0x78ff, 0xc109, 0x21, 0 + .dw 0x7940, 0xc109, 0x797f, 0xc109, 0x21, 0 + .dw 0x79c0, 0xc109, 0x9fff, 0xc109, 0x21, 0 + .dw 0xa040, 0xc109, 0xa07f, 0xc109, 0x21, 0 + .dw 0xa0c0, 0xc109, 0xa0ff, 0xc109, 0x21, 0 + .dw 0xa140, 0xc109, 0xa17f, 0xc109, 0x21, 0 + .dw 0xa1c0, 0xc109, 0xa1ff, 0xc109, 0x21, 0 + .dw 0xa240, 0xc109, 0xa27f, 0xc109, 0x21, 0 + .dw 0xa2c0, 0xc109, 0xa2ff, 0xc109, 0x21, 0 + .dw 0xa340, 0xc109, 0xa37f, 0xc109, 0x21, 0 + .dw 0xa3c0, 0xc109, 0xa3ff, 0xc109, 0x21, 0 + .dw 0xa440, 0xc109, 0xa47f, 0xc109, 0x21, 0 + .dw 0xa4c0, 0xc109, 0xa4ff, 0xc109, 0x21, 0 + .dw 0xa540, 0xc109, 0xa57f, 0xc109, 0x21, 0 + .dw 0xa5c0, 0xc109, 0xa5ff, 0xc109, 0x21, 0 + .dw 0xa640, 0xc109, 0xa67f, 0xc109, 0x21, 0 + .dw 0xa6c0, 0xc109, 0xa6ff, 0xc109, 0x21, 0 + .dw 0xa740, 0xc109, 0xa77f, 0xc109, 0x21, 0 + .dw 0xa7c0, 0xc109, 0xa7ff, 0xc109, 0x21, 0 + .dw 0xa840, 0xc109, 0xa87f, 0xc109, 0x21, 0 + .dw 0xa8c0, 0xc109, 0xa8ff, 0xc109, 0x21, 0 + .dw 0xa940, 0xc109, 0xa97f, 0xc109, 0x21, 0 + .dw 0xa9c0, 0xc109, 0xa9ff, 0xc109, 0x21, 0 + .dw 0xaa40, 0xc109, 0xaa7f, 0xc109, 0x21, 0 + .dw 0xaac0, 0xc109, 0xaaff, 0xc109, 0x21, 0 + .dw 0xab40, 0xc109, 0xab7f, 0xc109, 0x21, 0 + .dw 0xabc0, 0xc109, 0xabff, 0xc109, 0x21, 0 + .dw 0xac40, 0xc109, 0xac7f, 0xc109, 0x21, 0 + .dw 0xacc0, 0xc109, 0xacff, 0xc109, 0x21, 0 + .dw 0xad40, 0xc109, 0xad7f, 0xc109, 0x21, 0 + .dw 0xadc0, 0xc109, 0xadff, 0xc109, 0x21, 0 + .dw 0xae40, 0xc109, 0xae7f, 0xc109, 0x21, 0 + .dw 0xaec0, 0xc109, 0xaeff, 0xc109, 0x21, 0 + .dw 0xaf40, 0xc109, 0xaf7f, 0xc109, 0x21, 0 + .dw 0xafc0, 0xc109, 0xafff, 0xc109, 0x21, 0 + .dw 0xb040, 0xc109, 0xb07f, 0xc109, 0x21, 0 + .dw 0xb0c0, 0xc109, 0xb0ff, 0xc109, 0x21, 0 + .dw 0xb140, 0xc109, 0xb17f, 0xc109, 0x21, 0 + .dw 0xb1c0, 0xc109, 0xb1ff, 0xc109, 0x21, 0 + .dw 0xb240, 0xc109, 0xb27f, 0xc109, 0x21, 0 + .dw 0xb2c0, 0xc109, 0xb2ff, 0xc109, 0x21, 0 + .dw 0xb340, 0xc109, 0xb37f, 0xc109, 0x21, 0 + .dw 0xb3c0, 0xc109, 0xb3ff, 0xc109, 0x21, 0 + .dw 0xb440, 0xc109, 0xb47f, 0xc109, 0x21, 0 + .dw 0xb4c0, 0xc109, 0xb4ff, 0xc109, 0x21, 0 + .dw 0xb540, 0xc109, 0xb57f, 0xc109, 0x21, 0 + .dw 0xb5c0, 0xc109, 0xb5ff, 0xc109, 0x21, 0 + .dw 0xb640, 0xc109, 0xb67f, 0xc109, 0x21, 0 + .dw 0xb6c0, 0xc109, 0xb6ff, 0xc109, 0x21, 0 + .dw 0xb740, 0xc109, 0xb77f, 0xc109, 0x21, 0 + .dw 0xb7c0, 0xc109, 0xb7ff, 0xc109, 0x21, 0 + .dw 0xb840, 0xc109, 0xb87f, 0xc109, 0x21, 0 + .dw 0xb8c0, 0xc109, 0xb8ff, 0xc109, 0x21, 0 + .dw 0xb940, 0xc109, 0xb97f, 0xc109, 0x21, 0 + .dw 0xb9c0, 0xc109, 0xdfff, 0xc109, 0x21, 0 + .dw 0xe040, 0xc109, 0xe07f, 0xc109, 0x21, 0 + .dw 0xe0c0, 0xc109, 0xe0ff, 0xc109, 0x21, 0 + .dw 0xe140, 0xc109, 0xe17f, 0xc109, 0x21, 0 + .dw 0xe1c0, 0xc109, 0xe1ff, 0xc109, 0x21, 0 + .dw 0xe240, 0xc109, 0xe27f, 0xc109, 0x21, 0 + .dw 0xe2c0, 0xc109, 0xe2ff, 0xc109, 0x21, 0 + .dw 0xe340, 0xc109, 0xe37f, 0xc109, 0x21, 0 + .dw 0xe3c0, 0xc109, 0xe3ff, 0xc109, 0x21, 0 + .dw 0xe440, 0xc109, 0xe47f, 0xc109, 0x21, 0 + .dw 0xe4c0, 0xc109, 0xe4ff, 0xc109, 0x21, 0 + .dw 0xe540, 0xc109, 0xe57f, 0xc109, 0x21, 0 + .dw 0xe5c0, 0xc109, 0xe5ff, 0xc109, 0x21, 0 + .dw 0xe640, 0xc109, 0xe67f, 0xc109, 0x21, 0 + .dw 0xe6c0, 0xc109, 0xe6ff, 0xc109, 0x21, 0 + .dw 0xe740, 0xc109, 0xe77f, 0xc109, 0x21, 0 + .dw 0xe7c0, 0xc109, 0xe7ff, 0xc109, 0x21, 0 + .dw 0xe840, 0xc109, 0xe87f, 0xc109, 0x21, 0 + .dw 0xe8c0, 0xc109, 0xe8ff, 0xc109, 0x21, 0 + .dw 0xe940, 0xc109, 0xe97f, 0xc109, 0x21, 0 + .dw 0xe9c0, 0xc109, 0xe9ff, 0xc109, 0x21, 0 + .dw 0xea40, 0xc109, 0xea7f, 0xc109, 0x21, 0 + .dw 0xeac0, 0xc109, 0xeaff, 0xc109, 0x21, 0 + .dw 0xeb40, 0xc109, 0xeb7f, 0xc109, 0x21, 0 + .dw 0xebc0, 0xc109, 0xebff, 0xc109, 0x21, 0 + .dw 0xec40, 0xc109, 0xec7f, 0xc109, 0x21, 0 + .dw 0xecc0, 0xc109, 0xecff, 0xc109, 0x21, 0 + .dw 0xed40, 0xc109, 0xed7f, 0xc109, 0x21, 0 + .dw 0xedc0, 0xc109, 0xedff, 0xc109, 0x21, 0 + .dw 0xee40, 0xc109, 0xee7f, 0xc109, 0x21, 0 + .dw 0xeec0, 0xc109, 0xeeff, 0xc109, 0x21, 0 + .dw 0xef40, 0xc109, 0xef7f, 0xc109, 0x21, 0 + .dw 0xefc0, 0xc109, 0xefff, 0xc109, 0x21, 0 + .dw 0xf040, 0xc109, 0xf07f, 0xc109, 0x21, 0 + .dw 0xf0c0, 0xc109, 0xf0ff, 0xc109, 0x21, 0 + .dw 0xf140, 0xc109, 0xf17f, 0xc109, 0x21, 0 + .dw 0xf1c0, 0xc109, 0xf1ff, 0xc109, 0x21, 0 + .dw 0xf240, 0xc109, 0xf27f, 0xc109, 0x21, 0 + .dw 0xf2c0, 0xc109, 0xf2ff, 0xc109, 0x21, 0 + .dw 0xf340, 0xc109, 0xf37f, 0xc109, 0x21, 0 + .dw 0xf3c0, 0xc109, 0xf3ff, 0xc109, 0x21, 0 + .dw 0xf440, 0xc109, 0xf47f, 0xc109, 0x21, 0 + .dw 0xf4c0, 0xc109, 0xf4ff, 0xc109, 0x21, 0 + .dw 0xf540, 0xc109, 0xf57f, 0xc109, 0x21, 0 + .dw 0xf5c0, 0xc109, 0xf5ff, 0xc109, 0x21, 0 + .dw 0xf640, 0xc109, 0xf67f, 0xc109, 0x21, 0 + .dw 0xf6c0, 0xc109, 0xf6ff, 0xc109, 0x21, 0 + .dw 0xf740, 0xc109, 0xf77f, 0xc109, 0x21, 0 + .dw 0xf7c0, 0xc109, 0xf7ff, 0xc109, 0x21, 0 + .dw 0xf840, 0xc109, 0xf87f, 0xc109, 0x21, 0 + .dw 0xf8c0, 0xc109, 0xf8ff, 0xc109, 0x21, 0 + .dw 0xf940, 0xc109, 0xf97f, 0xc109, 0x21, 0 + .dw 0xf9c0, 0xc109, 0x1fff, 0xc10a, 0x21, 0 + .dw 0x2040, 0xc10a, 0x207f, 0xc10a, 0x21, 0 + .dw 0x20c0, 0xc10a, 0x20ff, 0xc10a, 0x21, 0 + .dw 0x2140, 0xc10a, 0x217f, 0xc10a, 0x21, 0 + .dw 0x21c0, 0xc10a, 0x21ff, 0xc10a, 0x21, 0 + .dw 0x2240, 0xc10a, 0x227f, 0xc10a, 0x21, 0 + .dw 0x22c0, 0xc10a, 0x22ff, 0xc10a, 0x21, 0 + .dw 0x2340, 0xc10a, 0x237f, 0xc10a, 0x21, 0 + .dw 0x23c0, 0xc10a, 0x23ff, 0xc10a, 0x21, 0 + .dw 0x2440, 0xc10a, 0x247f, 0xc10a, 0x21, 0 + .dw 0x24c0, 0xc10a, 0x24ff, 0xc10a, 0x21, 0 + .dw 0x2540, 0xc10a, 0x257f, 0xc10a, 0x21, 0 + .dw 0x25c0, 0xc10a, 0x25ff, 0xc10a, 0x21, 0 + .dw 0x2640, 0xc10a, 0x267f, 0xc10a, 0x21, 0 + .dw 0x26c0, 0xc10a, 0x26ff, 0xc10a, 0x21, 0 + .dw 0x2740, 0xc10a, 0x277f, 0xc10a, 0x21, 0 + .dw 0x27c0, 0xc10a, 0x27ff, 0xc10a, 0x21, 0 + .dw 0x2840, 0xc10a, 0x287f, 0xc10a, 0x21, 0 + .dw 0x28c0, 0xc10a, 0x28ff, 0xc10a, 0x21, 0 + .dw 0x2940, 0xc10a, 0x297f, 0xc10a, 0x21, 0 + .dw 0x29c0, 0xc10a, 0x29ff, 0xc10a, 0x21, 0 + .dw 0x2a40, 0xc10a, 0x2a7f, 0xc10a, 0x21, 0 + .dw 0x2ac0, 0xc10a, 0x2aff, 0xc10a, 0x21, 0 + .dw 0x2b40, 0xc10a, 0x2b7f, 0xc10a, 0x21, 0 + .dw 0x2bc0, 0xc10a, 0x2bff, 0xc10a, 0x21, 0 + .dw 0x2c40, 0xc10a, 0x2c7f, 0xc10a, 0x21, 0 + .dw 0x2cc0, 0xc10a, 0x2cff, 0xc10a, 0x21, 0 + .dw 0x2d40, 0xc10a, 0x2d7f, 0xc10a, 0x21, 0 + .dw 0x2dc0, 0xc10a, 0x2dff, 0xc10a, 0x21, 0 + .dw 0x2e40, 0xc10a, 0x2e7f, 0xc10a, 0x21, 0 + .dw 0x2ec0, 0xc10a, 0x2eff, 0xc10a, 0x21, 0 + .dw 0x2f40, 0xc10a, 0x2f7f, 0xc10a, 0x21, 0 + .dw 0x2fc0, 0xc10a, 0x2fff, 0xc10a, 0x21, 0 + .dw 0x3040, 0xc10a, 0x307f, 0xc10a, 0x21, 0 + .dw 0x30c0, 0xc10a, 0x30ff, 0xc10a, 0x21, 0 + .dw 0x3140, 0xc10a, 0x317f, 0xc10a, 0x21, 0 + .dw 0x31c0, 0xc10a, 0x31ff, 0xc10a, 0x21, 0 + .dw 0x3240, 0xc10a, 0x327f, 0xc10a, 0x21, 0 + .dw 0x32c0, 0xc10a, 0x32ff, 0xc10a, 0x21, 0 + .dw 0x3340, 0xc10a, 0x337f, 0xc10a, 0x21, 0 + .dw 0x33c0, 0xc10a, 0x33ff, 0xc10a, 0x21, 0 + .dw 0x3440, 0xc10a, 0x347f, 0xc10a, 0x21, 0 + .dw 0x34c0, 0xc10a, 0x34ff, 0xc10a, 0x21, 0 + .dw 0x3540, 0xc10a, 0x357f, 0xc10a, 0x21, 0 + .dw 0x35c0, 0xc10a, 0x35ff, 0xc10a, 0x21, 0 + .dw 0x3640, 0xc10a, 0x367f, 0xc10a, 0x21, 0 + .dw 0x36c0, 0xc10a, 0x36ff, 0xc10a, 0x21, 0 + .dw 0x3740, 0xc10a, 0x377f, 0xc10a, 0x21, 0 + .dw 0x37c0, 0xc10a, 0x37ff, 0xc10a, 0x21, 0 + .dw 0x3840, 0xc10a, 0x387f, 0xc10a, 0x21, 0 + .dw 0x38c0, 0xc10a, 0x38ff, 0xc10a, 0x21, 0 + .dw 0x3940, 0xc10a, 0x397f, 0xc10a, 0x21, 0 + .dw 0x39c0, 0xc10a, 0x5fff, 0xc10a, 0x21, 0 + .dw 0x6040, 0xc10a, 0x607f, 0xc10a, 0x21, 0 + .dw 0x60c0, 0xc10a, 0x60ff, 0xc10a, 0x21, 0 + .dw 0x6140, 0xc10a, 0x617f, 0xc10a, 0x21, 0 + .dw 0x61c0, 0xc10a, 0x61ff, 0xc10a, 0x21, 0 + .dw 0x6240, 0xc10a, 0x627f, 0xc10a, 0x21, 0 + .dw 0x62c0, 0xc10a, 0x62ff, 0xc10a, 0x21, 0 + .dw 0x6340, 0xc10a, 0x637f, 0xc10a, 0x21, 0 + .dw 0x63c0, 0xc10a, 0x63ff, 0xc10a, 0x21, 0 + .dw 0x6440, 0xc10a, 0x647f, 0xc10a, 0x21, 0 + .dw 0x64c0, 0xc10a, 0x64ff, 0xc10a, 0x21, 0 + .dw 0x6540, 0xc10a, 0x657f, 0xc10a, 0x21, 0 + .dw 0x65c0, 0xc10a, 0x65ff, 0xc10a, 0x21, 0 + .dw 0x6640, 0xc10a, 0x667f, 0xc10a, 0x21, 0 + .dw 0x66c0, 0xc10a, 0x66ff, 0xc10a, 0x21, 0 + .dw 0x6740, 0xc10a, 0x677f, 0xc10a, 0x21, 0 + .dw 0x67c0, 0xc10a, 0x67ff, 0xc10a, 0x21, 0 + .dw 0x6840, 0xc10a, 0x687f, 0xc10a, 0x21, 0 + .dw 0x68c0, 0xc10a, 0x68ff, 0xc10a, 0x21, 0 + .dw 0x6940, 0xc10a, 0x697f, 0xc10a, 0x21, 0 + .dw 0x69c0, 0xc10a, 0x69ff, 0xc10a, 0x21, 0 + .dw 0x6a40, 0xc10a, 0x6a7f, 0xc10a, 0x21, 0 + .dw 0x6ac0, 0xc10a, 0x6aff, 0xc10a, 0x21, 0 + .dw 0x6b40, 0xc10a, 0x6b7f, 0xc10a, 0x21, 0 + .dw 0x6bc0, 0xc10a, 0x6bff, 0xc10a, 0x21, 0 + .dw 0x6c40, 0xc10a, 0x6c7f, 0xc10a, 0x21, 0 + .dw 0x6cc0, 0xc10a, 0x6cff, 0xc10a, 0x21, 0 + .dw 0x6d40, 0xc10a, 0x6d7f, 0xc10a, 0x21, 0 + .dw 0x6dc0, 0xc10a, 0x6dff, 0xc10a, 0x21, 0 + .dw 0x6e40, 0xc10a, 0x6e7f, 0xc10a, 0x21, 0 + .dw 0x6ec0, 0xc10a, 0x6eff, 0xc10a, 0x21, 0 + .dw 0x6f40, 0xc10a, 0x6f7f, 0xc10a, 0x21, 0 + .dw 0x6fc0, 0xc10a, 0x6fff, 0xc10a, 0x21, 0 + .dw 0x7040, 0xc10a, 0x707f, 0xc10a, 0x21, 0 + .dw 0x70c0, 0xc10a, 0x70ff, 0xc10a, 0x21, 0 + .dw 0x7140, 0xc10a, 0x717f, 0xc10a, 0x21, 0 + .dw 0x71c0, 0xc10a, 0x71ff, 0xc10a, 0x21, 0 + .dw 0x7240, 0xc10a, 0x727f, 0xc10a, 0x21, 0 + .dw 0x72c0, 0xc10a, 0x72ff, 0xc10a, 0x21, 0 + .dw 0x7340, 0xc10a, 0x737f, 0xc10a, 0x21, 0 + .dw 0x73c0, 0xc10a, 0x73ff, 0xc10a, 0x21, 0 + .dw 0x7440, 0xc10a, 0x747f, 0xc10a, 0x21, 0 + .dw 0x74c0, 0xc10a, 0x74ff, 0xc10a, 0x21, 0 + .dw 0x7540, 0xc10a, 0x757f, 0xc10a, 0x21, 0 + .dw 0x75c0, 0xc10a, 0x75ff, 0xc10a, 0x21, 0 + .dw 0x7640, 0xc10a, 0x767f, 0xc10a, 0x21, 0 + .dw 0x76c0, 0xc10a, 0x76ff, 0xc10a, 0x21, 0 + .dw 0x7740, 0xc10a, 0x777f, 0xc10a, 0x21, 0 + .dw 0x77c0, 0xc10a, 0x77ff, 0xc10a, 0x21, 0 + .dw 0x7840, 0xc10a, 0x787f, 0xc10a, 0x21, 0 + .dw 0x78c0, 0xc10a, 0x78ff, 0xc10a, 0x21, 0 + .dw 0x7940, 0xc10a, 0x797f, 0xc10a, 0x21, 0 + .dw 0x79c0, 0xc10a, 0x9fff, 0xc10a, 0x21, 0 + .dw 0xa040, 0xc10a, 0xa07f, 0xc10a, 0x21, 0 + .dw 0xa0c0, 0xc10a, 0xa0ff, 0xc10a, 0x21, 0 + .dw 0xa140, 0xc10a, 0xa17f, 0xc10a, 0x21, 0 + .dw 0xa1c0, 0xc10a, 0xa1ff, 0xc10a, 0x21, 0 + .dw 0xa240, 0xc10a, 0xa27f, 0xc10a, 0x21, 0 + .dw 0xa2c0, 0xc10a, 0xa2ff, 0xc10a, 0x21, 0 + .dw 0xa340, 0xc10a, 0xa37f, 0xc10a, 0x21, 0 + .dw 0xa3c0, 0xc10a, 0xa3ff, 0xc10a, 0x21, 0 + .dw 0xa440, 0xc10a, 0xa47f, 0xc10a, 0x21, 0 + .dw 0xa4c0, 0xc10a, 0xa4ff, 0xc10a, 0x21, 0 + .dw 0xa540, 0xc10a, 0xa57f, 0xc10a, 0x21, 0 + .dw 0xa5c0, 0xc10a, 0xa5ff, 0xc10a, 0x21, 0 + .dw 0xa640, 0xc10a, 0xa67f, 0xc10a, 0x21, 0 + .dw 0xa6c0, 0xc10a, 0xa6ff, 0xc10a, 0x21, 0 + .dw 0xa740, 0xc10a, 0xa77f, 0xc10a, 0x21, 0 + .dw 0xa7c0, 0xc10a, 0xa7ff, 0xc10a, 0x21, 0 + .dw 0xa840, 0xc10a, 0xa87f, 0xc10a, 0x21, 0 + .dw 0xa8c0, 0xc10a, 0xa8ff, 0xc10a, 0x21, 0 + .dw 0xa940, 0xc10a, 0xa97f, 0xc10a, 0x21, 0 + .dw 0xa9c0, 0xc10a, 0xa9ff, 0xc10a, 0x21, 0 + .dw 0xaa40, 0xc10a, 0xaa7f, 0xc10a, 0x21, 0 + .dw 0xaac0, 0xc10a, 0xaaff, 0xc10a, 0x21, 0 + .dw 0xab40, 0xc10a, 0xab7f, 0xc10a, 0x21, 0 + .dw 0xabc0, 0xc10a, 0xabff, 0xc10a, 0x21, 0 + .dw 0xac40, 0xc10a, 0xac7f, 0xc10a, 0x21, 0 + .dw 0xacc0, 0xc10a, 0xacff, 0xc10a, 0x21, 0 + .dw 0xad40, 0xc10a, 0xad7f, 0xc10a, 0x21, 0 + .dw 0xadc0, 0xc10a, 0xadff, 0xc10a, 0x21, 0 + .dw 0xae40, 0xc10a, 0xae7f, 0xc10a, 0x21, 0 + .dw 0xaec0, 0xc10a, 0xaeff, 0xc10a, 0x21, 0 + .dw 0xaf40, 0xc10a, 0xaf7f, 0xc10a, 0x21, 0 + .dw 0xafc0, 0xc10a, 0xafff, 0xc10a, 0x21, 0 + .dw 0xb040, 0xc10a, 0xb07f, 0xc10a, 0x21, 0 + .dw 0xb0c0, 0xc10a, 0xb0ff, 0xc10a, 0x21, 0 + .dw 0xb140, 0xc10a, 0xb17f, 0xc10a, 0x21, 0 + .dw 0xb1c0, 0xc10a, 0xb1ff, 0xc10a, 0x21, 0 + .dw 0xb240, 0xc10a, 0xb27f, 0xc10a, 0x21, 0 + .dw 0xb2c0, 0xc10a, 0xb2ff, 0xc10a, 0x21, 0 + .dw 0xb340, 0xc10a, 0xb37f, 0xc10a, 0x21, 0 + .dw 0xb3c0, 0xc10a, 0xb3ff, 0xc10a, 0x21, 0 + .dw 0xb440, 0xc10a, 0xb47f, 0xc10a, 0x21, 0 + .dw 0xb4c0, 0xc10a, 0xb4ff, 0xc10a, 0x21, 0 + .dw 0xb540, 0xc10a, 0xb57f, 0xc10a, 0x21, 0 + .dw 0xb5c0, 0xc10a, 0xb5ff, 0xc10a, 0x21, 0 + .dw 0xb640, 0xc10a, 0xb67f, 0xc10a, 0x21, 0 + .dw 0xb6c0, 0xc10a, 0xb6ff, 0xc10a, 0x21, 0 + .dw 0xb740, 0xc10a, 0xb77f, 0xc10a, 0x21, 0 + .dw 0xb7c0, 0xc10a, 0xb7ff, 0xc10a, 0x21, 0 + .dw 0xb840, 0xc10a, 0xb87f, 0xc10a, 0x21, 0 + .dw 0xb8c0, 0xc10a, 0xb8ff, 0xc10a, 0x21, 0 + .dw 0xb940, 0xc10a, 0xb97f, 0xc10a, 0x21, 0 + .dw 0xb9c0, 0xc10a, 0xdfff, 0xc10a, 0x21, 0 + .dw 0xe040, 0xc10a, 0xe07f, 0xc10a, 0x21, 0 + .dw 0xe0c0, 0xc10a, 0xe0ff, 0xc10a, 0x21, 0 + .dw 0xe140, 0xc10a, 0xe17f, 0xc10a, 0x21, 0 + .dw 0xe1c0, 0xc10a, 0xe1ff, 0xc10a, 0x21, 0 + .dw 0xe240, 0xc10a, 0xe27f, 0xc10a, 0x21, 0 + .dw 0xe2c0, 0xc10a, 0xe2ff, 0xc10a, 0x21, 0 + .dw 0xe340, 0xc10a, 0xe37f, 0xc10a, 0x21, 0 + .dw 0xe3c0, 0xc10a, 0xe3ff, 0xc10a, 0x21, 0 + .dw 0xe440, 0xc10a, 0xe47f, 0xc10a, 0x21, 0 + .dw 0xe4c0, 0xc10a, 0xe4ff, 0xc10a, 0x21, 0 + .dw 0xe540, 0xc10a, 0xe57f, 0xc10a, 0x21, 0 + .dw 0xe5c0, 0xc10a, 0xe5ff, 0xc10a, 0x21, 0 + .dw 0xe640, 0xc10a, 0xe67f, 0xc10a, 0x21, 0 + .dw 0xe6c0, 0xc10a, 0xe6ff, 0xc10a, 0x21, 0 + .dw 0xe740, 0xc10a, 0xe77f, 0xc10a, 0x21, 0 + .dw 0xe7c0, 0xc10a, 0xe7ff, 0xc10a, 0x21, 0 + .dw 0xe840, 0xc10a, 0xe87f, 0xc10a, 0x21, 0 + .dw 0xe8c0, 0xc10a, 0xe8ff, 0xc10a, 0x21, 0 + .dw 0xe940, 0xc10a, 0xe97f, 0xc10a, 0x21, 0 + .dw 0xe9c0, 0xc10a, 0xe9ff, 0xc10a, 0x21, 0 + .dw 0xea40, 0xc10a, 0xea7f, 0xc10a, 0x21, 0 + .dw 0xeac0, 0xc10a, 0xeaff, 0xc10a, 0x21, 0 + .dw 0xeb40, 0xc10a, 0xeb7f, 0xc10a, 0x21, 0 + .dw 0xebc0, 0xc10a, 0xebff, 0xc10a, 0x21, 0 + .dw 0xec40, 0xc10a, 0xec7f, 0xc10a, 0x21, 0 + .dw 0xecc0, 0xc10a, 0xecff, 0xc10a, 0x21, 0 + .dw 0xed40, 0xc10a, 0xed7f, 0xc10a, 0x21, 0 + .dw 0xedc0, 0xc10a, 0xedff, 0xc10a, 0x21, 0 + .dw 0xee40, 0xc10a, 0xee7f, 0xc10a, 0x21, 0 + .dw 0xeec0, 0xc10a, 0xeeff, 0xc10a, 0x21, 0 + .dw 0xef40, 0xc10a, 0xef7f, 0xc10a, 0x21, 0 + .dw 0xefc0, 0xc10a, 0xefff, 0xc10a, 0x21, 0 + .dw 0xf040, 0xc10a, 0xf07f, 0xc10a, 0x21, 0 + .dw 0xf0c0, 0xc10a, 0xf0ff, 0xc10a, 0x21, 0 + .dw 0xf140, 0xc10a, 0xf17f, 0xc10a, 0x21, 0 + .dw 0xf1c0, 0xc10a, 0xf1ff, 0xc10a, 0x21, 0 + .dw 0xf240, 0xc10a, 0xf27f, 0xc10a, 0x21, 0 + .dw 0xf2c0, 0xc10a, 0xf2ff, 0xc10a, 0x21, 0 + .dw 0xf340, 0xc10a, 0xf37f, 0xc10a, 0x21, 0 + .dw 0xf3c0, 0xc10a, 0xf3ff, 0xc10a, 0x21, 0 + .dw 0xf440, 0xc10a, 0xf47f, 0xc10a, 0x21, 0 + .dw 0xf4c0, 0xc10a, 0xf4ff, 0xc10a, 0x21, 0 + .dw 0xf540, 0xc10a, 0xf57f, 0xc10a, 0x21, 0 + .dw 0xf5c0, 0xc10a, 0xf5ff, 0xc10a, 0x21, 0 + .dw 0xf640, 0xc10a, 0xf67f, 0xc10a, 0x21, 0 + .dw 0xf6c0, 0xc10a, 0xf6ff, 0xc10a, 0x21, 0 + .dw 0xf740, 0xc10a, 0xf77f, 0xc10a, 0x21, 0 + .dw 0xf7c0, 0xc10a, 0xf7ff, 0xc10a, 0x21, 0 + .dw 0xf840, 0xc10a, 0xf87f, 0xc10a, 0x21, 0 + .dw 0xf8c0, 0xc10a, 0xf8ff, 0xc10a, 0x21, 0 + .dw 0xf940, 0xc10a, 0xf97f, 0xc10a, 0x21, 0 + .dw 0xf9c0, 0xc10a, 0x1fff, 0xc10b, 0x21, 0 + .dw 0x2040, 0xc10b, 0x207f, 0xc10b, 0x21, 0 + .dw 0x20c0, 0xc10b, 0x20ff, 0xc10b, 0x21, 0 + .dw 0x2140, 0xc10b, 0x217f, 0xc10b, 0x21, 0 + .dw 0x21c0, 0xc10b, 0x21ff, 0xc10b, 0x21, 0 + .dw 0x2240, 0xc10b, 0x227f, 0xc10b, 0x21, 0 + .dw 0x22c0, 0xc10b, 0x22ff, 0xc10b, 0x21, 0 + .dw 0x2340, 0xc10b, 0x237f, 0xc10b, 0x21, 0 + .dw 0x23c0, 0xc10b, 0x23ff, 0xc10b, 0x21, 0 + .dw 0x2440, 0xc10b, 0x247f, 0xc10b, 0x21, 0 + .dw 0x24c0, 0xc10b, 0x24ff, 0xc10b, 0x21, 0 + .dw 0x2540, 0xc10b, 0x257f, 0xc10b, 0x21, 0 + .dw 0x25c0, 0xc10b, 0x25ff, 0xc10b, 0x21, 0 + .dw 0x2640, 0xc10b, 0x267f, 0xc10b, 0x21, 0 + .dw 0x26c0, 0xc10b, 0x26ff, 0xc10b, 0x21, 0 + .dw 0x2740, 0xc10b, 0x277f, 0xc10b, 0x21, 0 + .dw 0x27c0, 0xc10b, 0x27ff, 0xc10b, 0x21, 0 + .dw 0x2840, 0xc10b, 0x287f, 0xc10b, 0x21, 0 + .dw 0x28c0, 0xc10b, 0x28ff, 0xc10b, 0x21, 0 + .dw 0x2940, 0xc10b, 0x297f, 0xc10b, 0x21, 0 + .dw 0x29c0, 0xc10b, 0x29ff, 0xc10b, 0x21, 0 + .dw 0x2a40, 0xc10b, 0x2a7f, 0xc10b, 0x21, 0 + .dw 0x2ac0, 0xc10b, 0x2aff, 0xc10b, 0x21, 0 + .dw 0x2b40, 0xc10b, 0x2b7f, 0xc10b, 0x21, 0 + .dw 0x2bc0, 0xc10b, 0x2bff, 0xc10b, 0x21, 0 + .dw 0x2c40, 0xc10b, 0x2c7f, 0xc10b, 0x21, 0 + .dw 0x2cc0, 0xc10b, 0x2cff, 0xc10b, 0x21, 0 + .dw 0x2d40, 0xc10b, 0x2d7f, 0xc10b, 0x21, 0 + .dw 0x2dc0, 0xc10b, 0x2dff, 0xc10b, 0x21, 0 + .dw 0x2e40, 0xc10b, 0x2e7f, 0xc10b, 0x21, 0 + .dw 0x2ec0, 0xc10b, 0x2eff, 0xc10b, 0x21, 0 + .dw 0x2f40, 0xc10b, 0x2f7f, 0xc10b, 0x21, 0 + .dw 0x2fc0, 0xc10b, 0x2fff, 0xc10b, 0x21, 0 + .dw 0x3040, 0xc10b, 0x307f, 0xc10b, 0x21, 0 + .dw 0x30c0, 0xc10b, 0x30ff, 0xc10b, 0x21, 0 + .dw 0x3140, 0xc10b, 0x317f, 0xc10b, 0x21, 0 + .dw 0x31c0, 0xc10b, 0x31ff, 0xc10b, 0x21, 0 + .dw 0x3240, 0xc10b, 0x327f, 0xc10b, 0x21, 0 + .dw 0x32c0, 0xc10b, 0x32ff, 0xc10b, 0x21, 0 + .dw 0x3340, 0xc10b, 0x337f, 0xc10b, 0x21, 0 + .dw 0x33c0, 0xc10b, 0x33ff, 0xc10b, 0x21, 0 + .dw 0x3440, 0xc10b, 0x347f, 0xc10b, 0x21, 0 + .dw 0x34c0, 0xc10b, 0x34ff, 0xc10b, 0x21, 0 + .dw 0x3540, 0xc10b, 0x357f, 0xc10b, 0x21, 0 + .dw 0x35c0, 0xc10b, 0x35ff, 0xc10b, 0x21, 0 + .dw 0x3640, 0xc10b, 0x367f, 0xc10b, 0x21, 0 + .dw 0x36c0, 0xc10b, 0x36ff, 0xc10b, 0x21, 0 + .dw 0x3740, 0xc10b, 0x377f, 0xc10b, 0x21, 0 + .dw 0x37c0, 0xc10b, 0x37ff, 0xc10b, 0x21, 0 + .dw 0x3840, 0xc10b, 0x387f, 0xc10b, 0x21, 0 + .dw 0x38c0, 0xc10b, 0x38ff, 0xc10b, 0x21, 0 + .dw 0x3940, 0xc10b, 0x397f, 0xc10b, 0x21, 0 + .dw 0x39c0, 0xc10b, 0xffff, 0xc10b, 0x21, 0 + .dw 0x0040, 0xc10c, 0x007f, 0xc10c, 0x21, 0 + .dw 0x00c0, 0xc10c, 0x00ff, 0xc10c, 0x21, 0 + .dw 0x0140, 0xc10c, 0x017f, 0xc10c, 0x21, 0 + .dw 0x01c0, 0xc10c, 0x01ff, 0xc10c, 0x21, 0 + .dw 0x0240, 0xc10c, 0x027f, 0xc10c, 0x21, 0 + .dw 0x02c0, 0xc10c, 0x02ff, 0xc10c, 0x21, 0 + .dw 0x0340, 0xc10c, 0x037f, 0xc10c, 0x21, 0 + .dw 0x03c0, 0xc10c, 0x03ff, 0xc10c, 0x21, 0 + .dw 0x0440, 0xc10c, 0x047f, 0xc10c, 0x21, 0 + .dw 0x04c0, 0xc10c, 0x04ff, 0xc10c, 0x21, 0 + .dw 0x0540, 0xc10c, 0x057f, 0xc10c, 0x21, 0 + .dw 0x05c0, 0xc10c, 0x05ff, 0xc10c, 0x21, 0 + .dw 0x0640, 0xc10c, 0x067f, 0xc10c, 0x21, 0 + .dw 0x06c0, 0xc10c, 0x06ff, 0xc10c, 0x21, 0 + .dw 0x0740, 0xc10c, 0x077f, 0xc10c, 0x21, 0 + .dw 0x07c0, 0xc10c, 0x07ff, 0xc10c, 0x21, 0 + .dw 0x0840, 0xc10c, 0x087f, 0xc10c, 0x21, 0 + .dw 0x08c0, 0xc10c, 0x08ff, 0xc10c, 0x21, 0 + .dw 0x0940, 0xc10c, 0x097f, 0xc10c, 0x21, 0 + .dw 0x09c0, 0xc10c, 0x09ff, 0xc10c, 0x21, 0 + .dw 0x0a40, 0xc10c, 0x0a7f, 0xc10c, 0x21, 0 + .dw 0x0ac0, 0xc10c, 0x0aff, 0xc10c, 0x21, 0 + .dw 0x0b40, 0xc10c, 0x0b7f, 0xc10c, 0x21, 0 + .dw 0x0bc0, 0xc10c, 0x0bff, 0xc10c, 0x21, 0 + .dw 0x0c40, 0xc10c, 0x0c7f, 0xc10c, 0x21, 0 + .dw 0x0cc0, 0xc10c, 0x0cff, 0xc10c, 0x21, 0 + .dw 0x0d40, 0xc10c, 0x0d7f, 0xc10c, 0x21, 0 + .dw 0x0dc0, 0xc10c, 0x0dff, 0xc10c, 0x21, 0 + .dw 0x0e40, 0xc10c, 0x0e7f, 0xc10c, 0x21, 0 + .dw 0x0ec0, 0xc10c, 0x0eff, 0xc10c, 0x21, 0 + .dw 0x0f40, 0xc10c, 0x0f7f, 0xc10c, 0x21, 0 + .dw 0x0fc0, 0xc10c, 0x0fff, 0xc10c, 0x21, 0 + .dw 0x1040, 0xc10c, 0x107f, 0xc10c, 0x21, 0 + .dw 0x10c0, 0xc10c, 0x10ff, 0xc10c, 0x21, 0 + .dw 0x1140, 0xc10c, 0x117f, 0xc10c, 0x21, 0 + .dw 0x11c0, 0xc10c, 0x11ff, 0xc10c, 0x21, 0 + .dw 0x1240, 0xc10c, 0x127f, 0xc10c, 0x21, 0 + .dw 0x12c0, 0xc10c, 0x12ff, 0xc10c, 0x21, 0 + .dw 0x1340, 0xc10c, 0x137f, 0xc10c, 0x21, 0 + .dw 0x13c0, 0xc10c, 0x13ff, 0xc10c, 0x21, 0 + .dw 0x1440, 0xc10c, 0x147f, 0xc10c, 0x21, 0 + .dw 0x14c0, 0xc10c, 0x14ff, 0xc10c, 0x21, 0 + .dw 0x1540, 0xc10c, 0x157f, 0xc10c, 0x21, 0 + .dw 0x15c0, 0xc10c, 0x15ff, 0xc10c, 0x21, 0 + .dw 0x1640, 0xc10c, 0x167f, 0xc10c, 0x21, 0 + .dw 0x16c0, 0xc10c, 0x16ff, 0xc10c, 0x21, 0 + .dw 0x1740, 0xc10c, 0x177f, 0xc10c, 0x21, 0 + .dw 0x17c0, 0xc10c, 0x17ff, 0xc10c, 0x21, 0 + .dw 0x1840, 0xc10c, 0x187f, 0xc10c, 0x21, 0 + .dw 0x18c0, 0xc10c, 0x18ff, 0xc10c, 0x21, 0 + .dw 0x1940, 0xc10c, 0x197f, 0xc10c, 0x21, 0 + .dw 0x19c0, 0xc10c, 0x1fff, 0xc10c, 0x21, 0 + .dw 0x2040, 0xc10c, 0x207f, 0xc10c, 0x21, 0 + .dw 0x20c0, 0xc10c, 0x20ff, 0xc10c, 0x21, 0 + .dw 0x2140, 0xc10c, 0x217f, 0xc10c, 0x21, 0 + .dw 0x21c0, 0xc10c, 0x21ff, 0xc10c, 0x21, 0 + .dw 0x2240, 0xc10c, 0x227f, 0xc10c, 0x21, 0 + .dw 0x22c0, 0xc10c, 0x22ff, 0xc10c, 0x21, 0 + .dw 0x2340, 0xc10c, 0x237f, 0xc10c, 0x21, 0 + .dw 0x23c0, 0xc10c, 0x23ff, 0xc10c, 0x21, 0 + .dw 0x2440, 0xc10c, 0x247f, 0xc10c, 0x21, 0 + .dw 0x24c0, 0xc10c, 0x24ff, 0xc10c, 0x21, 0 + .dw 0x2540, 0xc10c, 0x257f, 0xc10c, 0x21, 0 + .dw 0x25c0, 0xc10c, 0x25ff, 0xc10c, 0x21, 0 + .dw 0x2640, 0xc10c, 0x267f, 0xc10c, 0x21, 0 + .dw 0x26c0, 0xc10c, 0x26ff, 0xc10c, 0x21, 0 + .dw 0x2740, 0xc10c, 0x277f, 0xc10c, 0x21, 0 + .dw 0x27c0, 0xc10c, 0x27ff, 0xc10c, 0x21, 0 + .dw 0x2840, 0xc10c, 0x287f, 0xc10c, 0x21, 0 + .dw 0x28c0, 0xc10c, 0x28ff, 0xc10c, 0x21, 0 + .dw 0x2940, 0xc10c, 0x297f, 0xc10c, 0x21, 0 + .dw 0x29c0, 0xc10c, 0x29ff, 0xc10c, 0x21, 0 + .dw 0x2a40, 0xc10c, 0x2a7f, 0xc10c, 0x21, 0 + .dw 0x2ac0, 0xc10c, 0x2aff, 0xc10c, 0x21, 0 + .dw 0x2b40, 0xc10c, 0x2b7f, 0xc10c, 0x21, 0 + .dw 0x2bc0, 0xc10c, 0x2bff, 0xc10c, 0x21, 0 + .dw 0x2c40, 0xc10c, 0x2c7f, 0xc10c, 0x21, 0 + .dw 0x2cc0, 0xc10c, 0x2cff, 0xc10c, 0x21, 0 + .dw 0x2d40, 0xc10c, 0x2d7f, 0xc10c, 0x21, 0 + .dw 0x2dc0, 0xc10c, 0x2dff, 0xc10c, 0x21, 0 + .dw 0x2e40, 0xc10c, 0x2e7f, 0xc10c, 0x21, 0 + .dw 0x2ec0, 0xc10c, 0x2eff, 0xc10c, 0x21, 0 + .dw 0x2f40, 0xc10c, 0x2f7f, 0xc10c, 0x21, 0 + .dw 0x2fc0, 0xc10c, 0x2fff, 0xc10c, 0x21, 0 + .dw 0x3040, 0xc10c, 0x307f, 0xc10c, 0x21, 0 + .dw 0x30c0, 0xc10c, 0x30ff, 0xc10c, 0x21, 0 + .dw 0x3140, 0xc10c, 0x317f, 0xc10c, 0x21, 0 + .dw 0x31c0, 0xc10c, 0x31ff, 0xc10c, 0x21, 0 + .dw 0x3240, 0xc10c, 0x327f, 0xc10c, 0x21, 0 + .dw 0x32c0, 0xc10c, 0x32ff, 0xc10c, 0x21, 0 + .dw 0x3340, 0xc10c, 0x337f, 0xc10c, 0x21, 0 + .dw 0x33c0, 0xc10c, 0x33ff, 0xc10c, 0x21, 0 + .dw 0x3440, 0xc10c, 0x347f, 0xc10c, 0x21, 0 + .dw 0x34c0, 0xc10c, 0x34ff, 0xc10c, 0x21, 0 + .dw 0x3540, 0xc10c, 0x357f, 0xc10c, 0x21, 0 + .dw 0x35c0, 0xc10c, 0x35ff, 0xc10c, 0x21, 0 + .dw 0x3640, 0xc10c, 0x367f, 0xc10c, 0x21, 0 + .dw 0x36c0, 0xc10c, 0x36ff, 0xc10c, 0x21, 0 + .dw 0x3740, 0xc10c, 0x377f, 0xc10c, 0x21, 0 + .dw 0x37c0, 0xc10c, 0x37ff, 0xc10c, 0x21, 0 + .dw 0x3840, 0xc10c, 0x387f, 0xc10c, 0x21, 0 + .dw 0x38c0, 0xc10c, 0x38ff, 0xc10c, 0x21, 0 + .dw 0x3940, 0xc10c, 0x397f, 0xc10c, 0x21, 0 + .dw 0x39c0, 0xc10c, 0x3fff, 0xc10c, 0x21, 0 + .dw 0x4040, 0xc10c, 0x407f, 0xc10c, 0x21, 0 + .dw 0x40c0, 0xc10c, 0x40ff, 0xc10c, 0x21, 0 + .dw 0x4140, 0xc10c, 0x417f, 0xc10c, 0x21, 0 + .dw 0x41c0, 0xc10c, 0x41ff, 0xc10c, 0x21, 0 + .dw 0x4240, 0xc10c, 0x427f, 0xc10c, 0x21, 0 + .dw 0x42c0, 0xc10c, 0x42ff, 0xc10c, 0x21, 0 + .dw 0x4340, 0xc10c, 0x437f, 0xc10c, 0x21, 0 + .dw 0x43c0, 0xc10c, 0x43ff, 0xc10c, 0x21, 0 + .dw 0x4440, 0xc10c, 0x447f, 0xc10c, 0x21, 0 + .dw 0x44c0, 0xc10c, 0x44ff, 0xc10c, 0x21, 0 + .dw 0x4540, 0xc10c, 0x457f, 0xc10c, 0x21, 0 + .dw 0x45c0, 0xc10c, 0x45ff, 0xc10c, 0x21, 0 + .dw 0x4640, 0xc10c, 0x467f, 0xc10c, 0x21, 0 + .dw 0x46c0, 0xc10c, 0x46ff, 0xc10c, 0x21, 0 + .dw 0x4740, 0xc10c, 0x477f, 0xc10c, 0x21, 0 + .dw 0x47c0, 0xc10c, 0x47ff, 0xc10c, 0x21, 0 + .dw 0x4840, 0xc10c, 0x487f, 0xc10c, 0x21, 0 + .dw 0x48c0, 0xc10c, 0x48ff, 0xc10c, 0x21, 0 + .dw 0x4940, 0xc10c, 0x497f, 0xc10c, 0x21, 0 + .dw 0x49c0, 0xc10c, 0x49ff, 0xc10c, 0x21, 0 + .dw 0x4a40, 0xc10c, 0x4a7f, 0xc10c, 0x21, 0 + .dw 0x4ac0, 0xc10c, 0x4aff, 0xc10c, 0x21, 0 + .dw 0x4b40, 0xc10c, 0x4b7f, 0xc10c, 0x21, 0 + .dw 0x4bc0, 0xc10c, 0x4bff, 0xc10c, 0x21, 0 + .dw 0x4c40, 0xc10c, 0x4c7f, 0xc10c, 0x21, 0 + .dw 0x4cc0, 0xc10c, 0x4cff, 0xc10c, 0x21, 0 + .dw 0x4d40, 0xc10c, 0x4d7f, 0xc10c, 0x21, 0 + .dw 0x4dc0, 0xc10c, 0x4dff, 0xc10c, 0x21, 0 + .dw 0x4e40, 0xc10c, 0x4e7f, 0xc10c, 0x21, 0 + .dw 0x4ec0, 0xc10c, 0x4eff, 0xc10c, 0x21, 0 + .dw 0x4f40, 0xc10c, 0x4f7f, 0xc10c, 0x21, 0 + .dw 0x4fc0, 0xc10c, 0x4fff, 0xc10c, 0x21, 0 + .dw 0x5040, 0xc10c, 0x507f, 0xc10c, 0x21, 0 + .dw 0x50c0, 0xc10c, 0x50ff, 0xc10c, 0x21, 0 + .dw 0x5140, 0xc10c, 0x517f, 0xc10c, 0x21, 0 + .dw 0x51c0, 0xc10c, 0x51ff, 0xc10c, 0x21, 0 + .dw 0x5240, 0xc10c, 0x527f, 0xc10c, 0x21, 0 + .dw 0x52c0, 0xc10c, 0x52ff, 0xc10c, 0x21, 0 + .dw 0x5340, 0xc10c, 0x537f, 0xc10c, 0x21, 0 + .dw 0x53c0, 0xc10c, 0x53ff, 0xc10c, 0x21, 0 + .dw 0x5440, 0xc10c, 0x547f, 0xc10c, 0x21, 0 + .dw 0x54c0, 0xc10c, 0x54ff, 0xc10c, 0x21, 0 + .dw 0x5540, 0xc10c, 0x557f, 0xc10c, 0x21, 0 + .dw 0x55c0, 0xc10c, 0x55ff, 0xc10c, 0x21, 0 + .dw 0x5640, 0xc10c, 0x567f, 0xc10c, 0x21, 0 + .dw 0x56c0, 0xc10c, 0x56ff, 0xc10c, 0x21, 0 + .dw 0x5740, 0xc10c, 0x577f, 0xc10c, 0x21, 0 + .dw 0x57c0, 0xc10c, 0x57ff, 0xc10c, 0x21, 0 + .dw 0x5840, 0xc10c, 0x587f, 0xc10c, 0x21, 0 + .dw 0x58c0, 0xc10c, 0x58ff, 0xc10c, 0x21, 0 + .dw 0x5940, 0xc10c, 0x597f, 0xc10c, 0x21, 0 + .dw 0x59c0, 0xc10c, 0x5fff, 0xc10c, 0x21, 0 + .dw 0x6040, 0xc10c, 0x607f, 0xc10c, 0x21, 0 + .dw 0x60c0, 0xc10c, 0x60ff, 0xc10c, 0x21, 0 + .dw 0x6140, 0xc10c, 0x617f, 0xc10c, 0x21, 0 + .dw 0x61c0, 0xc10c, 0x61ff, 0xc10c, 0x21, 0 + .dw 0x6240, 0xc10c, 0x627f, 0xc10c, 0x21, 0 + .dw 0x62c0, 0xc10c, 0x62ff, 0xc10c, 0x21, 0 + .dw 0x6340, 0xc10c, 0x637f, 0xc10c, 0x21, 0 + .dw 0x63c0, 0xc10c, 0x63ff, 0xc10c, 0x21, 0 + .dw 0x6440, 0xc10c, 0x647f, 0xc10c, 0x21, 0 + .dw 0x64c0, 0xc10c, 0x64ff, 0xc10c, 0x21, 0 + .dw 0x6540, 0xc10c, 0x657f, 0xc10c, 0x21, 0 + .dw 0x65c0, 0xc10c, 0x65ff, 0xc10c, 0x21, 0 + .dw 0x6640, 0xc10c, 0x667f, 0xc10c, 0x21, 0 + .dw 0x66c0, 0xc10c, 0x66ff, 0xc10c, 0x21, 0 + .dw 0x6740, 0xc10c, 0x677f, 0xc10c, 0x21, 0 + .dw 0x67c0, 0xc10c, 0x67ff, 0xc10c, 0x21, 0 + .dw 0x6840, 0xc10c, 0x687f, 0xc10c, 0x21, 0 + .dw 0x68c0, 0xc10c, 0x68ff, 0xc10c, 0x21, 0 + .dw 0x6940, 0xc10c, 0x697f, 0xc10c, 0x21, 0 + .dw 0x69c0, 0xc10c, 0x69ff, 0xc10c, 0x21, 0 + .dw 0x6a40, 0xc10c, 0x6a7f, 0xc10c, 0x21, 0 + .dw 0x6ac0, 0xc10c, 0x6aff, 0xc10c, 0x21, 0 + .dw 0x6b40, 0xc10c, 0x6b7f, 0xc10c, 0x21, 0 + .dw 0x6bc0, 0xc10c, 0x6bff, 0xc10c, 0x21, 0 + .dw 0x6c40, 0xc10c, 0x6c7f, 0xc10c, 0x21, 0 + .dw 0x6cc0, 0xc10c, 0x6cff, 0xc10c, 0x21, 0 + .dw 0x6d40, 0xc10c, 0x6d7f, 0xc10c, 0x21, 0 + .dw 0x6dc0, 0xc10c, 0x6dff, 0xc10c, 0x21, 0 + .dw 0x6e40, 0xc10c, 0x6e7f, 0xc10c, 0x21, 0 + .dw 0x6ec0, 0xc10c, 0x6eff, 0xc10c, 0x21, 0 + .dw 0x6f40, 0xc10c, 0x6f7f, 0xc10c, 0x21, 0 + .dw 0x6fc0, 0xc10c, 0x6fff, 0xc10c, 0x21, 0 + .dw 0x7040, 0xc10c, 0x707f, 0xc10c, 0x21, 0 + .dw 0x70c0, 0xc10c, 0x70ff, 0xc10c, 0x21, 0 + .dw 0x7140, 0xc10c, 0x717f, 0xc10c, 0x21, 0 + .dw 0x71c0, 0xc10c, 0x71ff, 0xc10c, 0x21, 0 + .dw 0x7240, 0xc10c, 0x727f, 0xc10c, 0x21, 0 + .dw 0x72c0, 0xc10c, 0x72ff, 0xc10c, 0x21, 0 + .dw 0x7340, 0xc10c, 0x737f, 0xc10c, 0x21, 0 + .dw 0x73c0, 0xc10c, 0x73ff, 0xc10c, 0x21, 0 + .dw 0x7440, 0xc10c, 0x747f, 0xc10c, 0x21, 0 + .dw 0x74c0, 0xc10c, 0x74ff, 0xc10c, 0x21, 0 + .dw 0x7540, 0xc10c, 0x757f, 0xc10c, 0x21, 0 + .dw 0x75c0, 0xc10c, 0x75ff, 0xc10c, 0x21, 0 + .dw 0x7640, 0xc10c, 0x767f, 0xc10c, 0x21, 0 + .dw 0x76c0, 0xc10c, 0x76ff, 0xc10c, 0x21, 0 + .dw 0x7740, 0xc10c, 0x777f, 0xc10c, 0x21, 0 + .dw 0x77c0, 0xc10c, 0x77ff, 0xc10c, 0x21, 0 + .dw 0x7840, 0xc10c, 0x787f, 0xc10c, 0x21, 0 + .dw 0x78c0, 0xc10c, 0x78ff, 0xc10c, 0x21, 0 + .dw 0x7940, 0xc10c, 0x797f, 0xc10c, 0x21, 0 + .dw 0x79c0, 0xc10c, 0x7fff, 0xc10c, 0x21, 0 + .dw 0x8040, 0xc10c, 0x807f, 0xc10c, 0x21, 0 + .dw 0x80c0, 0xc10c, 0x80ff, 0xc10c, 0x21, 0 + .dw 0x8140, 0xc10c, 0x817f, 0xc10c, 0x21, 0 + .dw 0x81c0, 0xc10c, 0x81ff, 0xc10c, 0x21, 0 + .dw 0x8240, 0xc10c, 0x827f, 0xc10c, 0x21, 0 + .dw 0x82c0, 0xc10c, 0x82ff, 0xc10c, 0x21, 0 + .dw 0x8340, 0xc10c, 0x837f, 0xc10c, 0x21, 0 + .dw 0x83c0, 0xc10c, 0x83ff, 0xc10c, 0x21, 0 + .dw 0x8440, 0xc10c, 0x847f, 0xc10c, 0x21, 0 + .dw 0x84c0, 0xc10c, 0x84ff, 0xc10c, 0x21, 0 + .dw 0x8540, 0xc10c, 0x857f, 0xc10c, 0x21, 0 + .dw 0x85c0, 0xc10c, 0x85ff, 0xc10c, 0x21, 0 + .dw 0x8640, 0xc10c, 0x867f, 0xc10c, 0x21, 0 + .dw 0x86c0, 0xc10c, 0x86ff, 0xc10c, 0x21, 0 + .dw 0x8740, 0xc10c, 0x877f, 0xc10c, 0x21, 0 + .dw 0x87c0, 0xc10c, 0x87ff, 0xc10c, 0x21, 0 + .dw 0x8840, 0xc10c, 0x887f, 0xc10c, 0x21, 0 + .dw 0x88c0, 0xc10c, 0x88ff, 0xc10c, 0x21, 0 + .dw 0x8940, 0xc10c, 0x897f, 0xc10c, 0x21, 0 + .dw 0x89c0, 0xc10c, 0x89ff, 0xc10c, 0x21, 0 + .dw 0x8a40, 0xc10c, 0x8a7f, 0xc10c, 0x21, 0 + .dw 0x8ac0, 0xc10c, 0x8aff, 0xc10c, 0x21, 0 + .dw 0x8b40, 0xc10c, 0x8b7f, 0xc10c, 0x21, 0 + .dw 0x8bc0, 0xc10c, 0x8bff, 0xc10c, 0x21, 0 + .dw 0x8c40, 0xc10c, 0x8c7f, 0xc10c, 0x21, 0 + .dw 0x8cc0, 0xc10c, 0x8cff, 0xc10c, 0x21, 0 + .dw 0x8d40, 0xc10c, 0x8d7f, 0xc10c, 0x21, 0 + .dw 0x8dc0, 0xc10c, 0x8dff, 0xc10c, 0x21, 0 + .dw 0x8e40, 0xc10c, 0x8e7f, 0xc10c, 0x21, 0 + .dw 0x8ec0, 0xc10c, 0x8eff, 0xc10c, 0x21, 0 + .dw 0x8f40, 0xc10c, 0x8f7f, 0xc10c, 0x21, 0 + .dw 0x8fc0, 0xc10c, 0x8fff, 0xc10c, 0x21, 0 + .dw 0x9040, 0xc10c, 0x907f, 0xc10c, 0x21, 0 + .dw 0x90c0, 0xc10c, 0x90ff, 0xc10c, 0x21, 0 + .dw 0x9140, 0xc10c, 0x917f, 0xc10c, 0x21, 0 + .dw 0x91c0, 0xc10c, 0x91ff, 0xc10c, 0x21, 0 + .dw 0x9240, 0xc10c, 0x927f, 0xc10c, 0x21, 0 + .dw 0x92c0, 0xc10c, 0x92ff, 0xc10c, 0x21, 0 + .dw 0x9340, 0xc10c, 0x937f, 0xc10c, 0x21, 0 + .dw 0x93c0, 0xc10c, 0x93ff, 0xc10c, 0x21, 0 + .dw 0x9440, 0xc10c, 0x947f, 0xc10c, 0x21, 0 + .dw 0x94c0, 0xc10c, 0x94ff, 0xc10c, 0x21, 0 + .dw 0x9540, 0xc10c, 0x957f, 0xc10c, 0x21, 0 + .dw 0x95c0, 0xc10c, 0x95ff, 0xc10c, 0x21, 0 + .dw 0x9640, 0xc10c, 0x967f, 0xc10c, 0x21, 0 + .dw 0x96c0, 0xc10c, 0x96ff, 0xc10c, 0x21, 0 + .dw 0x9740, 0xc10c, 0x977f, 0xc10c, 0x21, 0 + .dw 0x97c0, 0xc10c, 0x97ff, 0xc10c, 0x21, 0 + .dw 0x9840, 0xc10c, 0x987f, 0xc10c, 0x21, 0 + .dw 0x98c0, 0xc10c, 0x98ff, 0xc10c, 0x21, 0 + .dw 0x9940, 0xc10c, 0x997f, 0xc10c, 0x21, 0 + .dw 0x99c0, 0xc10c, 0x9fff, 0xc10c, 0x21, 0 + .dw 0xa040, 0xc10c, 0xa07f, 0xc10c, 0x21, 0 + .dw 0xa0c0, 0xc10c, 0xa0ff, 0xc10c, 0x21, 0 + .dw 0xa140, 0xc10c, 0xa17f, 0xc10c, 0x21, 0 + .dw 0xa1c0, 0xc10c, 0xa1ff, 0xc10c, 0x21, 0 + .dw 0xa240, 0xc10c, 0xa27f, 0xc10c, 0x21, 0 + .dw 0xa2c0, 0xc10c, 0xa2ff, 0xc10c, 0x21, 0 + .dw 0xa340, 0xc10c, 0xa37f, 0xc10c, 0x21, 0 + .dw 0xa3c0, 0xc10c, 0xa3ff, 0xc10c, 0x21, 0 + .dw 0xa440, 0xc10c, 0xa47f, 0xc10c, 0x21, 0 + .dw 0xa4c0, 0xc10c, 0xa4ff, 0xc10c, 0x21, 0 + .dw 0xa540, 0xc10c, 0xa57f, 0xc10c, 0x21, 0 + .dw 0xa5c0, 0xc10c, 0xa5ff, 0xc10c, 0x21, 0 + .dw 0xa640, 0xc10c, 0xa67f, 0xc10c, 0x21, 0 + .dw 0xa6c0, 0xc10c, 0xa6ff, 0xc10c, 0x21, 0 + .dw 0xa740, 0xc10c, 0xa77f, 0xc10c, 0x21, 0 + .dw 0xa7c0, 0xc10c, 0xa7ff, 0xc10c, 0x21, 0 + .dw 0xa840, 0xc10c, 0xa87f, 0xc10c, 0x21, 0 + .dw 0xa8c0, 0xc10c, 0xa8ff, 0xc10c, 0x21, 0 + .dw 0xa940, 0xc10c, 0xa97f, 0xc10c, 0x21, 0 + .dw 0xa9c0, 0xc10c, 0xa9ff, 0xc10c, 0x21, 0 + .dw 0xaa40, 0xc10c, 0xaa7f, 0xc10c, 0x21, 0 + .dw 0xaac0, 0xc10c, 0xaaff, 0xc10c, 0x21, 0 + .dw 0xab40, 0xc10c, 0xab7f, 0xc10c, 0x21, 0 + .dw 0xabc0, 0xc10c, 0xabff, 0xc10c, 0x21, 0 + .dw 0xac40, 0xc10c, 0xac7f, 0xc10c, 0x21, 0 + .dw 0xacc0, 0xc10c, 0xacff, 0xc10c, 0x21, 0 + .dw 0xad40, 0xc10c, 0xad7f, 0xc10c, 0x21, 0 + .dw 0xadc0, 0xc10c, 0xadff, 0xc10c, 0x21, 0 + .dw 0xae40, 0xc10c, 0xae7f, 0xc10c, 0x21, 0 + .dw 0xaec0, 0xc10c, 0xaeff, 0xc10c, 0x21, 0 + .dw 0xaf40, 0xc10c, 0xaf7f, 0xc10c, 0x21, 0 + .dw 0xafc0, 0xc10c, 0xafff, 0xc10c, 0x21, 0 + .dw 0xb040, 0xc10c, 0xb07f, 0xc10c, 0x21, 0 + .dw 0xb0c0, 0xc10c, 0xb0ff, 0xc10c, 0x21, 0 + .dw 0xb140, 0xc10c, 0xb17f, 0xc10c, 0x21, 0 + .dw 0xb1c0, 0xc10c, 0xb1ff, 0xc10c, 0x21, 0 + .dw 0xb240, 0xc10c, 0xb27f, 0xc10c, 0x21, 0 + .dw 0xb2c0, 0xc10c, 0xb2ff, 0xc10c, 0x21, 0 + .dw 0xb340, 0xc10c, 0xb37f, 0xc10c, 0x21, 0 + .dw 0xb3c0, 0xc10c, 0xb3ff, 0xc10c, 0x21, 0 + .dw 0xb440, 0xc10c, 0xb47f, 0xc10c, 0x21, 0 + .dw 0xb4c0, 0xc10c, 0xb4ff, 0xc10c, 0x21, 0 + .dw 0xb540, 0xc10c, 0xb57f, 0xc10c, 0x21, 0 + .dw 0xb5c0, 0xc10c, 0xb5ff, 0xc10c, 0x21, 0 + .dw 0xb640, 0xc10c, 0xb67f, 0xc10c, 0x21, 0 + .dw 0xb6c0, 0xc10c, 0xb6ff, 0xc10c, 0x21, 0 + .dw 0xb740, 0xc10c, 0xb77f, 0xc10c, 0x21, 0 + .dw 0xb7c0, 0xc10c, 0xb7ff, 0xc10c, 0x21, 0 + .dw 0xb840, 0xc10c, 0xb87f, 0xc10c, 0x21, 0 + .dw 0xb8c0, 0xc10c, 0xb8ff, 0xc10c, 0x21, 0 + .dw 0xb940, 0xc10c, 0xb97f, 0xc10c, 0x21, 0 + .dw 0xb9c0, 0xc10c, 0xbfff, 0xc10c, 0x21, 0 + .dw 0xc040, 0xc10c, 0xc07f, 0xc10c, 0x21, 0 + .dw 0xc0c0, 0xc10c, 0xc0ff, 0xc10c, 0x21, 0 + .dw 0xc140, 0xc10c, 0xc17f, 0xc10c, 0x21, 0 + .dw 0xc1c0, 0xc10c, 0xc1ff, 0xc10c, 0x21, 0 + .dw 0xc240, 0xc10c, 0xc27f, 0xc10c, 0x21, 0 + .dw 0xc2c0, 0xc10c, 0xc2ff, 0xc10c, 0x21, 0 + .dw 0xc340, 0xc10c, 0xc37f, 0xc10c, 0x21, 0 + .dw 0xc3c0, 0xc10c, 0xc3ff, 0xc10c, 0x21, 0 + .dw 0xc440, 0xc10c, 0xc47f, 0xc10c, 0x21, 0 + .dw 0xc4c0, 0xc10c, 0xc4ff, 0xc10c, 0x21, 0 + .dw 0xc540, 0xc10c, 0xc57f, 0xc10c, 0x21, 0 + .dw 0xc5c0, 0xc10c, 0xc5ff, 0xc10c, 0x21, 0 + .dw 0xc640, 0xc10c, 0xc67f, 0xc10c, 0x21, 0 + .dw 0xc6c0, 0xc10c, 0xc6ff, 0xc10c, 0x21, 0 + .dw 0xc740, 0xc10c, 0xc77f, 0xc10c, 0x21, 0 + .dw 0xc7c0, 0xc10c, 0xc7ff, 0xc10c, 0x21, 0 + .dw 0xc840, 0xc10c, 0xc87f, 0xc10c, 0x21, 0 + .dw 0xc8c0, 0xc10c, 0xc8ff, 0xc10c, 0x21, 0 + .dw 0xc940, 0xc10c, 0xc97f, 0xc10c, 0x21, 0 + .dw 0xc9c0, 0xc10c, 0xc9ff, 0xc10c, 0x21, 0 + .dw 0xca40, 0xc10c, 0xca7f, 0xc10c, 0x21, 0 + .dw 0xcac0, 0xc10c, 0xcaff, 0xc10c, 0x21, 0 + .dw 0xcb40, 0xc10c, 0xcb7f, 0xc10c, 0x21, 0 + .dw 0xcbc0, 0xc10c, 0xcbff, 0xc10c, 0x21, 0 + .dw 0xcc40, 0xc10c, 0xcc7f, 0xc10c, 0x21, 0 + .dw 0xccc0, 0xc10c, 0xccff, 0xc10c, 0x21, 0 + .dw 0xcd40, 0xc10c, 0xcd7f, 0xc10c, 0x21, 0 + .dw 0xcdc0, 0xc10c, 0xcdff, 0xc10c, 0x21, 0 + .dw 0xce40, 0xc10c, 0xce7f, 0xc10c, 0x21, 0 + .dw 0xcec0, 0xc10c, 0xceff, 0xc10c, 0x21, 0 + .dw 0xcf40, 0xc10c, 0xcf7f, 0xc10c, 0x21, 0 + .dw 0xcfc0, 0xc10c, 0xcfff, 0xc10c, 0x21, 0 + .dw 0xd040, 0xc10c, 0xd07f, 0xc10c, 0x21, 0 + .dw 0xd0c0, 0xc10c, 0xd0ff, 0xc10c, 0x21, 0 + .dw 0xd140, 0xc10c, 0xd17f, 0xc10c, 0x21, 0 + .dw 0xd1c0, 0xc10c, 0xd1ff, 0xc10c, 0x21, 0 + .dw 0xd240, 0xc10c, 0xd27f, 0xc10c, 0x21, 0 + .dw 0xd2c0, 0xc10c, 0xd2ff, 0xc10c, 0x21, 0 + .dw 0xd340, 0xc10c, 0xd37f, 0xc10c, 0x21, 0 + .dw 0xd3c0, 0xc10c, 0xd3ff, 0xc10c, 0x21, 0 + .dw 0xd440, 0xc10c, 0xd47f, 0xc10c, 0x21, 0 + .dw 0xd4c0, 0xc10c, 0xd4ff, 0xc10c, 0x21, 0 + .dw 0xd540, 0xc10c, 0xd57f, 0xc10c, 0x21, 0 + .dw 0xd5c0, 0xc10c, 0xd5ff, 0xc10c, 0x21, 0 + .dw 0xd640, 0xc10c, 0xd67f, 0xc10c, 0x21, 0 + .dw 0xd6c0, 0xc10c, 0xd6ff, 0xc10c, 0x21, 0 + .dw 0xd740, 0xc10c, 0xd77f, 0xc10c, 0x21, 0 + .dw 0xd7c0, 0xc10c, 0xd7ff, 0xc10c, 0x21, 0 + .dw 0xd840, 0xc10c, 0xd87f, 0xc10c, 0x21, 0 + .dw 0xd8c0, 0xc10c, 0xd8ff, 0xc10c, 0x21, 0 + .dw 0xd940, 0xc10c, 0xd97f, 0xc10c, 0x21, 0 + .dw 0xd9c0, 0xc10c, 0xdfff, 0xc10c, 0x21, 0 + .dw 0xe040, 0xc10c, 0xe07f, 0xc10c, 0x21, 0 + .dw 0xe0c0, 0xc10c, 0xe0ff, 0xc10c, 0x21, 0 + .dw 0xe140, 0xc10c, 0xe17f, 0xc10c, 0x21, 0 + .dw 0xe1c0, 0xc10c, 0xe1ff, 0xc10c, 0x21, 0 + .dw 0xe240, 0xc10c, 0xe27f, 0xc10c, 0x21, 0 + .dw 0xe2c0, 0xc10c, 0xe2ff, 0xc10c, 0x21, 0 + .dw 0xe340, 0xc10c, 0xe37f, 0xc10c, 0x21, 0 + .dw 0xe3c0, 0xc10c, 0xe3ff, 0xc10c, 0x21, 0 + .dw 0xe440, 0xc10c, 0xe47f, 0xc10c, 0x21, 0 + .dw 0xe4c0, 0xc10c, 0xe4ff, 0xc10c, 0x21, 0 + .dw 0xe540, 0xc10c, 0xe57f, 0xc10c, 0x21, 0 + .dw 0xe5c0, 0xc10c, 0xe5ff, 0xc10c, 0x21, 0 + .dw 0xe640, 0xc10c, 0xe67f, 0xc10c, 0x21, 0 + .dw 0xe6c0, 0xc10c, 0xe6ff, 0xc10c, 0x21, 0 + .dw 0xe740, 0xc10c, 0xe77f, 0xc10c, 0x21, 0 + .dw 0xe7c0, 0xc10c, 0xe7ff, 0xc10c, 0x21, 0 + .dw 0xe840, 0xc10c, 0xe87f, 0xc10c, 0x21, 0 + .dw 0xe8c0, 0xc10c, 0xe8ff, 0xc10c, 0x21, 0 + .dw 0xe940, 0xc10c, 0xe97f, 0xc10c, 0x21, 0 + .dw 0xe9c0, 0xc10c, 0xe9ff, 0xc10c, 0x21, 0 + .dw 0xea40, 0xc10c, 0xea7f, 0xc10c, 0x21, 0 + .dw 0xeac0, 0xc10c, 0xeaff, 0xc10c, 0x21, 0 + .dw 0xeb40, 0xc10c, 0xeb7f, 0xc10c, 0x21, 0 + .dw 0xebc0, 0xc10c, 0xebff, 0xc10c, 0x21, 0 + .dw 0xec40, 0xc10c, 0xec7f, 0xc10c, 0x21, 0 + .dw 0xecc0, 0xc10c, 0xecff, 0xc10c, 0x21, 0 + .dw 0xed40, 0xc10c, 0xed7f, 0xc10c, 0x21, 0 + .dw 0xedc0, 0xc10c, 0xedff, 0xc10c, 0x21, 0 + .dw 0xee40, 0xc10c, 0xee7f, 0xc10c, 0x21, 0 + .dw 0xeec0, 0xc10c, 0xeeff, 0xc10c, 0x21, 0 + .dw 0xef40, 0xc10c, 0xef7f, 0xc10c, 0x21, 0 + .dw 0xefc0, 0xc10c, 0xefff, 0xc10c, 0x21, 0 + .dw 0xf040, 0xc10c, 0xf07f, 0xc10c, 0x21, 0 + .dw 0xf0c0, 0xc10c, 0xf0ff, 0xc10c, 0x21, 0 + .dw 0xf140, 0xc10c, 0xf17f, 0xc10c, 0x21, 0 + .dw 0xf1c0, 0xc10c, 0xf1ff, 0xc10c, 0x21, 0 + .dw 0xf240, 0xc10c, 0xf27f, 0xc10c, 0x21, 0 + .dw 0xf2c0, 0xc10c, 0xf2ff, 0xc10c, 0x21, 0 + .dw 0xf340, 0xc10c, 0xf37f, 0xc10c, 0x21, 0 + .dw 0xf3c0, 0xc10c, 0xf3ff, 0xc10c, 0x21, 0 + .dw 0xf440, 0xc10c, 0xf47f, 0xc10c, 0x21, 0 + .dw 0xf4c0, 0xc10c, 0xf4ff, 0xc10c, 0x21, 0 + .dw 0xf540, 0xc10c, 0xf57f, 0xc10c, 0x21, 0 + .dw 0xf5c0, 0xc10c, 0xf5ff, 0xc10c, 0x21, 0 + .dw 0xf640, 0xc10c, 0xf67f, 0xc10c, 0x21, 0 + .dw 0xf6c0, 0xc10c, 0xf6ff, 0xc10c, 0x21, 0 + .dw 0xf740, 0xc10c, 0xf77f, 0xc10c, 0x21, 0 + .dw 0xf7c0, 0xc10c, 0xf7ff, 0xc10c, 0x21, 0 + .dw 0xf840, 0xc10c, 0xf87f, 0xc10c, 0x21, 0 + .dw 0xf8c0, 0xc10c, 0xf8ff, 0xc10c, 0x21, 0 + .dw 0xf940, 0xc10c, 0xf97f, 0xc10c, 0x21, 0 + .dw 0xf9c0, 0xc10c, 0xffff, 0xc10c, 0x21, 0 + .dw 0x0040, 0xc10d, 0x007f, 0xc10d, 0x21, 0 + .dw 0x00c0, 0xc10d, 0x00ff, 0xc10d, 0x21, 0 + .dw 0x0140, 0xc10d, 0x017f, 0xc10d, 0x21, 0 + .dw 0x01c0, 0xc10d, 0x01ff, 0xc10d, 0x21, 0 + .dw 0x0240, 0xc10d, 0x027f, 0xc10d, 0x21, 0 + .dw 0x02c0, 0xc10d, 0x02ff, 0xc10d, 0x21, 0 + .dw 0x0340, 0xc10d, 0x037f, 0xc10d, 0x21, 0 + .dw 0x03c0, 0xc10d, 0x03ff, 0xc10d, 0x21, 0 + .dw 0x0440, 0xc10d, 0x047f, 0xc10d, 0x21, 0 + .dw 0x04c0, 0xc10d, 0x04ff, 0xc10d, 0x21, 0 + .dw 0x0540, 0xc10d, 0x057f, 0xc10d, 0x21, 0 + .dw 0x05c0, 0xc10d, 0x05ff, 0xc10d, 0x21, 0 + .dw 0x0640, 0xc10d, 0x067f, 0xc10d, 0x21, 0 + .dw 0x06c0, 0xc10d, 0x06ff, 0xc10d, 0x21, 0 + .dw 0x0740, 0xc10d, 0x077f, 0xc10d, 0x21, 0 + .dw 0x07c0, 0xc10d, 0x07ff, 0xc10d, 0x21, 0 + .dw 0x0840, 0xc10d, 0x087f, 0xc10d, 0x21, 0 + .dw 0x08c0, 0xc10d, 0x08ff, 0xc10d, 0x21, 0 + .dw 0x0940, 0xc10d, 0x097f, 0xc10d, 0x21, 0 + .dw 0x09c0, 0xc10d, 0x09ff, 0xc10d, 0x21, 0 + .dw 0x0a40, 0xc10d, 0x0a7f, 0xc10d, 0x21, 0 + .dw 0x0ac0, 0xc10d, 0x0aff, 0xc10d, 0x21, 0 + .dw 0x0b40, 0xc10d, 0x0b7f, 0xc10d, 0x21, 0 + .dw 0x0bc0, 0xc10d, 0x0bff, 0xc10d, 0x21, 0 + .dw 0x0c40, 0xc10d, 0x0c7f, 0xc10d, 0x21, 0 + .dw 0x0cc0, 0xc10d, 0x0cff, 0xc10d, 0x21, 0 + .dw 0x0d40, 0xc10d, 0x0d7f, 0xc10d, 0x21, 0 + .dw 0x0dc0, 0xc10d, 0x0dff, 0xc10d, 0x21, 0 + .dw 0x0e40, 0xc10d, 0x0e7f, 0xc10d, 0x21, 0 + .dw 0x0ec0, 0xc10d, 0x0eff, 0xc10d, 0x21, 0 + .dw 0x0f40, 0xc10d, 0x0f7f, 0xc10d, 0x21, 0 + .dw 0x0fc0, 0xc10d, 0x0fff, 0xc10d, 0x21, 0 + .dw 0x1040, 0xc10d, 0x107f, 0xc10d, 0x21, 0 + .dw 0x10c0, 0xc10d, 0x10ff, 0xc10d, 0x21, 0 + .dw 0x1140, 0xc10d, 0x117f, 0xc10d, 0x21, 0 + .dw 0x11c0, 0xc10d, 0x11ff, 0xc10d, 0x21, 0 + .dw 0x1240, 0xc10d, 0x127f, 0xc10d, 0x21, 0 + .dw 0x12c0, 0xc10d, 0x12ff, 0xc10d, 0x21, 0 + .dw 0x1340, 0xc10d, 0x137f, 0xc10d, 0x21, 0 + .dw 0x13c0, 0xc10d, 0x13ff, 0xc10d, 0x21, 0 + .dw 0x1440, 0xc10d, 0x147f, 0xc10d, 0x21, 0 + .dw 0x14c0, 0xc10d, 0x14ff, 0xc10d, 0x21, 0 + .dw 0x1540, 0xc10d, 0x157f, 0xc10d, 0x21, 0 + .dw 0x15c0, 0xc10d, 0x15ff, 0xc10d, 0x21, 0 + .dw 0x1640, 0xc10d, 0x167f, 0xc10d, 0x21, 0 + .dw 0x16c0, 0xc10d, 0x16ff, 0xc10d, 0x21, 0 + .dw 0x1740, 0xc10d, 0x177f, 0xc10d, 0x21, 0 + .dw 0x17c0, 0xc10d, 0x17ff, 0xc10d, 0x21, 0 + .dw 0x1840, 0xc10d, 0x187f, 0xc10d, 0x21, 0 + .dw 0x18c0, 0xc10d, 0x18ff, 0xc10d, 0x21, 0 + .dw 0x1940, 0xc10d, 0x197f, 0xc10d, 0x21, 0 + .dw 0x19c0, 0xc10d, 0x1fff, 0xc10d, 0x21, 0 + .dw 0x2040, 0xc10d, 0x207f, 0xc10d, 0x21, 0 + .dw 0x20c0, 0xc10d, 0x20ff, 0xc10d, 0x21, 0 + .dw 0x2140, 0xc10d, 0x217f, 0xc10d, 0x21, 0 + .dw 0x21c0, 0xc10d, 0x21ff, 0xc10d, 0x21, 0 + .dw 0x2240, 0xc10d, 0x227f, 0xc10d, 0x21, 0 + .dw 0x22c0, 0xc10d, 0x22ff, 0xc10d, 0x21, 0 + .dw 0x2340, 0xc10d, 0x237f, 0xc10d, 0x21, 0 + .dw 0x23c0, 0xc10d, 0x23ff, 0xc10d, 0x21, 0 + .dw 0x2440, 0xc10d, 0x247f, 0xc10d, 0x21, 0 + .dw 0x24c0, 0xc10d, 0x24ff, 0xc10d, 0x21, 0 + .dw 0x2540, 0xc10d, 0x257f, 0xc10d, 0x21, 0 + .dw 0x25c0, 0xc10d, 0x25ff, 0xc10d, 0x21, 0 + .dw 0x2640, 0xc10d, 0x267f, 0xc10d, 0x21, 0 + .dw 0x26c0, 0xc10d, 0x26ff, 0xc10d, 0x21, 0 + .dw 0x2740, 0xc10d, 0x277f, 0xc10d, 0x21, 0 + .dw 0x27c0, 0xc10d, 0x27ff, 0xc10d, 0x21, 0 + .dw 0x2840, 0xc10d, 0x287f, 0xc10d, 0x21, 0 + .dw 0x28c0, 0xc10d, 0x28ff, 0xc10d, 0x21, 0 + .dw 0x2940, 0xc10d, 0x297f, 0xc10d, 0x21, 0 + .dw 0x29c0, 0xc10d, 0x29ff, 0xc10d, 0x21, 0 + .dw 0x2a40, 0xc10d, 0x2a7f, 0xc10d, 0x21, 0 + .dw 0x2ac0, 0xc10d, 0x2aff, 0xc10d, 0x21, 0 + .dw 0x2b40, 0xc10d, 0x2b7f, 0xc10d, 0x21, 0 + .dw 0x2bc0, 0xc10d, 0x2bff, 0xc10d, 0x21, 0 + .dw 0x2c40, 0xc10d, 0x2c7f, 0xc10d, 0x21, 0 + .dw 0x2cc0, 0xc10d, 0x2cff, 0xc10d, 0x21, 0 + .dw 0x2d40, 0xc10d, 0x2d7f, 0xc10d, 0x21, 0 + .dw 0x2dc0, 0xc10d, 0x2dff, 0xc10d, 0x21, 0 + .dw 0x2e40, 0xc10d, 0x2e7f, 0xc10d, 0x21, 0 + .dw 0x2ec0, 0xc10d, 0x2eff, 0xc10d, 0x21, 0 + .dw 0x2f40, 0xc10d, 0x2f7f, 0xc10d, 0x21, 0 + .dw 0x2fc0, 0xc10d, 0x2fff, 0xc10d, 0x21, 0 + .dw 0x3040, 0xc10d, 0x307f, 0xc10d, 0x21, 0 + .dw 0x30c0, 0xc10d, 0x30ff, 0xc10d, 0x21, 0 + .dw 0x3140, 0xc10d, 0x317f, 0xc10d, 0x21, 0 + .dw 0x31c0, 0xc10d, 0x31ff, 0xc10d, 0x21, 0 + .dw 0x3240, 0xc10d, 0x327f, 0xc10d, 0x21, 0 + .dw 0x32c0, 0xc10d, 0x32ff, 0xc10d, 0x21, 0 + .dw 0x3340, 0xc10d, 0x337f, 0xc10d, 0x21, 0 + .dw 0x33c0, 0xc10d, 0x33ff, 0xc10d, 0x21, 0 + .dw 0x3440, 0xc10d, 0x347f, 0xc10d, 0x21, 0 + .dw 0x34c0, 0xc10d, 0x34ff, 0xc10d, 0x21, 0 + .dw 0x3540, 0xc10d, 0x357f, 0xc10d, 0x21, 0 + .dw 0x35c0, 0xc10d, 0x35ff, 0xc10d, 0x21, 0 + .dw 0x3640, 0xc10d, 0x367f, 0xc10d, 0x21, 0 + .dw 0x36c0, 0xc10d, 0x36ff, 0xc10d, 0x21, 0 + .dw 0x3740, 0xc10d, 0x377f, 0xc10d, 0x21, 0 + .dw 0x37c0, 0xc10d, 0x37ff, 0xc10d, 0x21, 0 + .dw 0x3840, 0xc10d, 0x387f, 0xc10d, 0x21, 0 + .dw 0x38c0, 0xc10d, 0x38ff, 0xc10d, 0x21, 0 + .dw 0x3940, 0xc10d, 0x397f, 0xc10d, 0x21, 0 + .dw 0x39c0, 0xc10d, 0x3fff, 0xc10d, 0x21, 0 + .dw 0x4040, 0xc10d, 0x407f, 0xc10d, 0x21, 0 + .dw 0x40c0, 0xc10d, 0x40ff, 0xc10d, 0x21, 0 + .dw 0x4140, 0xc10d, 0x417f, 0xc10d, 0x21, 0 + .dw 0x41c0, 0xc10d, 0x41ff, 0xc10d, 0x21, 0 + .dw 0x4240, 0xc10d, 0x427f, 0xc10d, 0x21, 0 + .dw 0x42c0, 0xc10d, 0x42ff, 0xc10d, 0x21, 0 + .dw 0x4340, 0xc10d, 0x437f, 0xc10d, 0x21, 0 + .dw 0x43c0, 0xc10d, 0x43ff, 0xc10d, 0x21, 0 + .dw 0x4440, 0xc10d, 0x447f, 0xc10d, 0x21, 0 + .dw 0x44c0, 0xc10d, 0x44ff, 0xc10d, 0x21, 0 + .dw 0x4540, 0xc10d, 0x457f, 0xc10d, 0x21, 0 + .dw 0x45c0, 0xc10d, 0x45ff, 0xc10d, 0x21, 0 + .dw 0x4640, 0xc10d, 0x467f, 0xc10d, 0x21, 0 + .dw 0x46c0, 0xc10d, 0x46ff, 0xc10d, 0x21, 0 + .dw 0x4740, 0xc10d, 0x477f, 0xc10d, 0x21, 0 + .dw 0x47c0, 0xc10d, 0x47ff, 0xc10d, 0x21, 0 + .dw 0x4840, 0xc10d, 0x487f, 0xc10d, 0x21, 0 + .dw 0x48c0, 0xc10d, 0x48ff, 0xc10d, 0x21, 0 + .dw 0x4940, 0xc10d, 0x497f, 0xc10d, 0x21, 0 + .dw 0x49c0, 0xc10d, 0x49ff, 0xc10d, 0x21, 0 + .dw 0x4a40, 0xc10d, 0x4a7f, 0xc10d, 0x21, 0 + .dw 0x4ac0, 0xc10d, 0x4aff, 0xc10d, 0x21, 0 + .dw 0x4b40, 0xc10d, 0x4b7f, 0xc10d, 0x21, 0 + .dw 0x4bc0, 0xc10d, 0x4bff, 0xc10d, 0x21, 0 + .dw 0x4c40, 0xc10d, 0x4c7f, 0xc10d, 0x21, 0 + .dw 0x4cc0, 0xc10d, 0x4cff, 0xc10d, 0x21, 0 + .dw 0x4d40, 0xc10d, 0x4d7f, 0xc10d, 0x21, 0 + .dw 0x4dc0, 0xc10d, 0x4dff, 0xc10d, 0x21, 0 + .dw 0x4e40, 0xc10d, 0x4e7f, 0xc10d, 0x21, 0 + .dw 0x4ec0, 0xc10d, 0x4eff, 0xc10d, 0x21, 0 + .dw 0x4f40, 0xc10d, 0x4f7f, 0xc10d, 0x21, 0 + .dw 0x4fc0, 0xc10d, 0x4fff, 0xc10d, 0x21, 0 + .dw 0x5040, 0xc10d, 0x507f, 0xc10d, 0x21, 0 + .dw 0x50c0, 0xc10d, 0x50ff, 0xc10d, 0x21, 0 + .dw 0x5140, 0xc10d, 0x517f, 0xc10d, 0x21, 0 + .dw 0x51c0, 0xc10d, 0x51ff, 0xc10d, 0x21, 0 + .dw 0x5240, 0xc10d, 0x527f, 0xc10d, 0x21, 0 + .dw 0x52c0, 0xc10d, 0x52ff, 0xc10d, 0x21, 0 + .dw 0x5340, 0xc10d, 0x537f, 0xc10d, 0x21, 0 + .dw 0x53c0, 0xc10d, 0x53ff, 0xc10d, 0x21, 0 + .dw 0x5440, 0xc10d, 0x547f, 0xc10d, 0x21, 0 + .dw 0x54c0, 0xc10d, 0x54ff, 0xc10d, 0x21, 0 + .dw 0x5540, 0xc10d, 0x557f, 0xc10d, 0x21, 0 + .dw 0x55c0, 0xc10d, 0x55ff, 0xc10d, 0x21, 0 + .dw 0x5640, 0xc10d, 0x567f, 0xc10d, 0x21, 0 + .dw 0x56c0, 0xc10d, 0x56ff, 0xc10d, 0x21, 0 + .dw 0x5740, 0xc10d, 0x577f, 0xc10d, 0x21, 0 + .dw 0x57c0, 0xc10d, 0x57ff, 0xc10d, 0x21, 0 + .dw 0x5840, 0xc10d, 0x587f, 0xc10d, 0x21, 0 + .dw 0x58c0, 0xc10d, 0x58ff, 0xc10d, 0x21, 0 + .dw 0x5940, 0xc10d, 0x597f, 0xc10d, 0x21, 0 + .dw 0x59c0, 0xc10d, 0x5fff, 0xc10d, 0x21, 0 + .dw 0x6040, 0xc10d, 0x607f, 0xc10d, 0x21, 0 + .dw 0x60c0, 0xc10d, 0x60ff, 0xc10d, 0x21, 0 + .dw 0x6140, 0xc10d, 0x617f, 0xc10d, 0x21, 0 + .dw 0x61c0, 0xc10d, 0x61ff, 0xc10d, 0x21, 0 + .dw 0x6240, 0xc10d, 0x627f, 0xc10d, 0x21, 0 + .dw 0x62c0, 0xc10d, 0x62ff, 0xc10d, 0x21, 0 + .dw 0x6340, 0xc10d, 0x637f, 0xc10d, 0x21, 0 + .dw 0x63c0, 0xc10d, 0x63ff, 0xc10d, 0x21, 0 + .dw 0x6440, 0xc10d, 0x647f, 0xc10d, 0x21, 0 + .dw 0x64c0, 0xc10d, 0x64ff, 0xc10d, 0x21, 0 + .dw 0x6540, 0xc10d, 0x657f, 0xc10d, 0x21, 0 + .dw 0x65c0, 0xc10d, 0x65ff, 0xc10d, 0x21, 0 + .dw 0x6640, 0xc10d, 0x667f, 0xc10d, 0x21, 0 + .dw 0x66c0, 0xc10d, 0x66ff, 0xc10d, 0x21, 0 + .dw 0x6740, 0xc10d, 0x677f, 0xc10d, 0x21, 0 + .dw 0x67c0, 0xc10d, 0x67ff, 0xc10d, 0x21, 0 + .dw 0x6840, 0xc10d, 0x687f, 0xc10d, 0x21, 0 + .dw 0x68c0, 0xc10d, 0x68ff, 0xc10d, 0x21, 0 + .dw 0x6940, 0xc10d, 0x697f, 0xc10d, 0x21, 0 + .dw 0x69c0, 0xc10d, 0x69ff, 0xc10d, 0x21, 0 + .dw 0x6a40, 0xc10d, 0x6a7f, 0xc10d, 0x21, 0 + .dw 0x6ac0, 0xc10d, 0x6aff, 0xc10d, 0x21, 0 + .dw 0x6b40, 0xc10d, 0x6b7f, 0xc10d, 0x21, 0 + .dw 0x6bc0, 0xc10d, 0x6bff, 0xc10d, 0x21, 0 + .dw 0x6c40, 0xc10d, 0x6c7f, 0xc10d, 0x21, 0 + .dw 0x6cc0, 0xc10d, 0x6cff, 0xc10d, 0x21, 0 + .dw 0x6d40, 0xc10d, 0x6d7f, 0xc10d, 0x21, 0 + .dw 0x6dc0, 0xc10d, 0x6dff, 0xc10d, 0x21, 0 + .dw 0x6e40, 0xc10d, 0x6e7f, 0xc10d, 0x21, 0 + .dw 0x6ec0, 0xc10d, 0x6eff, 0xc10d, 0x21, 0 + .dw 0x6f40, 0xc10d, 0x6f7f, 0xc10d, 0x21, 0 + .dw 0x6fc0, 0xc10d, 0x6fff, 0xc10d, 0x21, 0 + .dw 0x7040, 0xc10d, 0x707f, 0xc10d, 0x21, 0 + .dw 0x70c0, 0xc10d, 0x70ff, 0xc10d, 0x21, 0 + .dw 0x7140, 0xc10d, 0x717f, 0xc10d, 0x21, 0 + .dw 0x71c0, 0xc10d, 0x71ff, 0xc10d, 0x21, 0 + .dw 0x7240, 0xc10d, 0x727f, 0xc10d, 0x21, 0 + .dw 0x72c0, 0xc10d, 0x72ff, 0xc10d, 0x21, 0 + .dw 0x7340, 0xc10d, 0x737f, 0xc10d, 0x21, 0 + .dw 0x73c0, 0xc10d, 0x73ff, 0xc10d, 0x21, 0 + .dw 0x7440, 0xc10d, 0x747f, 0xc10d, 0x21, 0 + .dw 0x74c0, 0xc10d, 0x74ff, 0xc10d, 0x21, 0 + .dw 0x7540, 0xc10d, 0x757f, 0xc10d, 0x21, 0 + .dw 0x75c0, 0xc10d, 0x75ff, 0xc10d, 0x21, 0 + .dw 0x7640, 0xc10d, 0x767f, 0xc10d, 0x21, 0 + .dw 0x76c0, 0xc10d, 0x76ff, 0xc10d, 0x21, 0 + .dw 0x7740, 0xc10d, 0x777f, 0xc10d, 0x21, 0 + .dw 0x77c0, 0xc10d, 0x77ff, 0xc10d, 0x21, 0 + .dw 0x7840, 0xc10d, 0x787f, 0xc10d, 0x21, 0 + .dw 0x78c0, 0xc10d, 0x78ff, 0xc10d, 0x21, 0 + .dw 0x7940, 0xc10d, 0x797f, 0xc10d, 0x21, 0 + .dw 0x79c0, 0xc10d, 0x7fff, 0xc10d, 0x21, 0 + .dw 0x8040, 0xc10d, 0x807f, 0xc10d, 0x21, 0 + .dw 0x80c0, 0xc10d, 0x80ff, 0xc10d, 0x21, 0 + .dw 0x8140, 0xc10d, 0x817f, 0xc10d, 0x21, 0 + .dw 0x81c0, 0xc10d, 0x81ff, 0xc10d, 0x21, 0 + .dw 0x8240, 0xc10d, 0x827f, 0xc10d, 0x21, 0 + .dw 0x82c0, 0xc10d, 0x82ff, 0xc10d, 0x21, 0 + .dw 0x8340, 0xc10d, 0x837f, 0xc10d, 0x21, 0 + .dw 0x83c0, 0xc10d, 0x83ff, 0xc10d, 0x21, 0 + .dw 0x8440, 0xc10d, 0x847f, 0xc10d, 0x21, 0 + .dw 0x84c0, 0xc10d, 0x84ff, 0xc10d, 0x21, 0 + .dw 0x8540, 0xc10d, 0x857f, 0xc10d, 0x21, 0 + .dw 0x85c0, 0xc10d, 0x85ff, 0xc10d, 0x21, 0 + .dw 0x8640, 0xc10d, 0x867f, 0xc10d, 0x21, 0 + .dw 0x86c0, 0xc10d, 0x86ff, 0xc10d, 0x21, 0 + .dw 0x8740, 0xc10d, 0x877f, 0xc10d, 0x21, 0 + .dw 0x87c0, 0xc10d, 0x87ff, 0xc10d, 0x21, 0 + .dw 0x8840, 0xc10d, 0x887f, 0xc10d, 0x21, 0 + .dw 0x88c0, 0xc10d, 0x88ff, 0xc10d, 0x21, 0 + .dw 0x8940, 0xc10d, 0x897f, 0xc10d, 0x21, 0 + .dw 0x89c0, 0xc10d, 0x89ff, 0xc10d, 0x21, 0 + .dw 0x8a40, 0xc10d, 0x8a7f, 0xc10d, 0x21, 0 + .dw 0x8ac0, 0xc10d, 0x8aff, 0xc10d, 0x21, 0 + .dw 0x8b40, 0xc10d, 0x8b7f, 0xc10d, 0x21, 0 + .dw 0x8bc0, 0xc10d, 0x8bff, 0xc10d, 0x21, 0 + .dw 0x8c40, 0xc10d, 0x8c7f, 0xc10d, 0x21, 0 + .dw 0x8cc0, 0xc10d, 0x8cff, 0xc10d, 0x21, 0 + .dw 0x8d40, 0xc10d, 0x8d7f, 0xc10d, 0x21, 0 + .dw 0x8dc0, 0xc10d, 0x8dff, 0xc10d, 0x21, 0 + .dw 0x8e40, 0xc10d, 0x8e7f, 0xc10d, 0x21, 0 + .dw 0x8ec0, 0xc10d, 0x8eff, 0xc10d, 0x21, 0 + .dw 0x8f40, 0xc10d, 0x8f7f, 0xc10d, 0x21, 0 + .dw 0x8fc0, 0xc10d, 0x8fff, 0xc10d, 0x21, 0 + .dw 0x9040, 0xc10d, 0x907f, 0xc10d, 0x21, 0 + .dw 0x90c0, 0xc10d, 0x90ff, 0xc10d, 0x21, 0 + .dw 0x9140, 0xc10d, 0x917f, 0xc10d, 0x21, 0 + .dw 0x91c0, 0xc10d, 0x91ff, 0xc10d, 0x21, 0 + .dw 0x9240, 0xc10d, 0x927f, 0xc10d, 0x21, 0 + .dw 0x92c0, 0xc10d, 0x92ff, 0xc10d, 0x21, 0 + .dw 0x9340, 0xc10d, 0x937f, 0xc10d, 0x21, 0 + .dw 0x93c0, 0xc10d, 0x93ff, 0xc10d, 0x21, 0 + .dw 0x9440, 0xc10d, 0x947f, 0xc10d, 0x21, 0 + .dw 0x94c0, 0xc10d, 0x94ff, 0xc10d, 0x21, 0 + .dw 0x9540, 0xc10d, 0x957f, 0xc10d, 0x21, 0 + .dw 0x95c0, 0xc10d, 0x95ff, 0xc10d, 0x21, 0 + .dw 0x9640, 0xc10d, 0x967f, 0xc10d, 0x21, 0 + .dw 0x96c0, 0xc10d, 0x96ff, 0xc10d, 0x21, 0 + .dw 0x9740, 0xc10d, 0x977f, 0xc10d, 0x21, 0 + .dw 0x97c0, 0xc10d, 0x97ff, 0xc10d, 0x21, 0 + .dw 0x9840, 0xc10d, 0x987f, 0xc10d, 0x21, 0 + .dw 0x98c0, 0xc10d, 0x98ff, 0xc10d, 0x21, 0 + .dw 0x9940, 0xc10d, 0x997f, 0xc10d, 0x21, 0 + .dw 0x99c0, 0xc10d, 0x9fff, 0xc10d, 0x21, 0 + .dw 0xa040, 0xc10d, 0xa07f, 0xc10d, 0x21, 0 + .dw 0xa0c0, 0xc10d, 0xa0ff, 0xc10d, 0x21, 0 + .dw 0xa140, 0xc10d, 0xa17f, 0xc10d, 0x21, 0 + .dw 0xa1c0, 0xc10d, 0xa1ff, 0xc10d, 0x21, 0 + .dw 0xa240, 0xc10d, 0xa27f, 0xc10d, 0x21, 0 + .dw 0xa2c0, 0xc10d, 0xa2ff, 0xc10d, 0x21, 0 + .dw 0xa340, 0xc10d, 0xa37f, 0xc10d, 0x21, 0 + .dw 0xa3c0, 0xc10d, 0xa3ff, 0xc10d, 0x21, 0 + .dw 0xa440, 0xc10d, 0xa47f, 0xc10d, 0x21, 0 + .dw 0xa4c0, 0xc10d, 0xa4ff, 0xc10d, 0x21, 0 + .dw 0xa540, 0xc10d, 0xa57f, 0xc10d, 0x21, 0 + .dw 0xa5c0, 0xc10d, 0xa5ff, 0xc10d, 0x21, 0 + .dw 0xa640, 0xc10d, 0xa67f, 0xc10d, 0x21, 0 + .dw 0xa6c0, 0xc10d, 0xa6ff, 0xc10d, 0x21, 0 + .dw 0xa740, 0xc10d, 0xa77f, 0xc10d, 0x21, 0 + .dw 0xa7c0, 0xc10d, 0xa7ff, 0xc10d, 0x21, 0 + .dw 0xa840, 0xc10d, 0xa87f, 0xc10d, 0x21, 0 + .dw 0xa8c0, 0xc10d, 0xa8ff, 0xc10d, 0x21, 0 + .dw 0xa940, 0xc10d, 0xa97f, 0xc10d, 0x21, 0 + .dw 0xa9c0, 0xc10d, 0xa9ff, 0xc10d, 0x21, 0 + .dw 0xaa40, 0xc10d, 0xaa7f, 0xc10d, 0x21, 0 + .dw 0xaac0, 0xc10d, 0xaaff, 0xc10d, 0x21, 0 + .dw 0xab40, 0xc10d, 0xab7f, 0xc10d, 0x21, 0 + .dw 0xabc0, 0xc10d, 0xabff, 0xc10d, 0x21, 0 + .dw 0xac40, 0xc10d, 0xac7f, 0xc10d, 0x21, 0 + .dw 0xacc0, 0xc10d, 0xacff, 0xc10d, 0x21, 0 + .dw 0xad40, 0xc10d, 0xad7f, 0xc10d, 0x21, 0 + .dw 0xadc0, 0xc10d, 0xadff, 0xc10d, 0x21, 0 + .dw 0xae40, 0xc10d, 0xae7f, 0xc10d, 0x21, 0 + .dw 0xaec0, 0xc10d, 0xaeff, 0xc10d, 0x21, 0 + .dw 0xaf40, 0xc10d, 0xaf7f, 0xc10d, 0x21, 0 + .dw 0xafc0, 0xc10d, 0xafff, 0xc10d, 0x21, 0 + .dw 0xb040, 0xc10d, 0xb07f, 0xc10d, 0x21, 0 + .dw 0xb0c0, 0xc10d, 0xb0ff, 0xc10d, 0x21, 0 + .dw 0xb140, 0xc10d, 0xb17f, 0xc10d, 0x21, 0 + .dw 0xb1c0, 0xc10d, 0xb1ff, 0xc10d, 0x21, 0 + .dw 0xb240, 0xc10d, 0xb27f, 0xc10d, 0x21, 0 + .dw 0xb2c0, 0xc10d, 0xb2ff, 0xc10d, 0x21, 0 + .dw 0xb340, 0xc10d, 0xb37f, 0xc10d, 0x21, 0 + .dw 0xb3c0, 0xc10d, 0xb3ff, 0xc10d, 0x21, 0 + .dw 0xb440, 0xc10d, 0xb47f, 0xc10d, 0x21, 0 + .dw 0xb4c0, 0xc10d, 0xb4ff, 0xc10d, 0x21, 0 + .dw 0xb540, 0xc10d, 0xb57f, 0xc10d, 0x21, 0 + .dw 0xb5c0, 0xc10d, 0xb5ff, 0xc10d, 0x21, 0 + .dw 0xb640, 0xc10d, 0xb67f, 0xc10d, 0x21, 0 + .dw 0xb6c0, 0xc10d, 0xb6ff, 0xc10d, 0x21, 0 + .dw 0xb740, 0xc10d, 0xb77f, 0xc10d, 0x21, 0 + .dw 0xb7c0, 0xc10d, 0xb7ff, 0xc10d, 0x21, 0 + .dw 0xb840, 0xc10d, 0xb87f, 0xc10d, 0x21, 0 + .dw 0xb8c0, 0xc10d, 0xb8ff, 0xc10d, 0x21, 0 + .dw 0xb940, 0xc10d, 0xb97f, 0xc10d, 0x21, 0 + .dw 0xb9c0, 0xc10d, 0xbfff, 0xc10d, 0x21, 0 + .dw 0xc040, 0xc10d, 0xc07f, 0xc10d, 0x21, 0 + .dw 0xc0c0, 0xc10d, 0xc0ff, 0xc10d, 0x21, 0 + .dw 0xc140, 0xc10d, 0xc17f, 0xc10d, 0x21, 0 + .dw 0xc1c0, 0xc10d, 0xc1ff, 0xc10d, 0x21, 0 + .dw 0xc240, 0xc10d, 0xc27f, 0xc10d, 0x21, 0 + .dw 0xc2c0, 0xc10d, 0xc2ff, 0xc10d, 0x21, 0 + .dw 0xc340, 0xc10d, 0xc37f, 0xc10d, 0x21, 0 + .dw 0xc3c0, 0xc10d, 0xc3ff, 0xc10d, 0x21, 0 + .dw 0xc440, 0xc10d, 0xc47f, 0xc10d, 0x21, 0 + .dw 0xc4c0, 0xc10d, 0xc4ff, 0xc10d, 0x21, 0 + .dw 0xc540, 0xc10d, 0xc57f, 0xc10d, 0x21, 0 + .dw 0xc5c0, 0xc10d, 0xc5ff, 0xc10d, 0x21, 0 + .dw 0xc640, 0xc10d, 0xc67f, 0xc10d, 0x21, 0 + .dw 0xc6c0, 0xc10d, 0xc6ff, 0xc10d, 0x21, 0 + .dw 0xc740, 0xc10d, 0xc77f, 0xc10d, 0x21, 0 + .dw 0xc7c0, 0xc10d, 0xc7ff, 0xc10d, 0x21, 0 + .dw 0xc840, 0xc10d, 0xc87f, 0xc10d, 0x21, 0 + .dw 0xc8c0, 0xc10d, 0xc8ff, 0xc10d, 0x21, 0 + .dw 0xc940, 0xc10d, 0xc97f, 0xc10d, 0x21, 0 + .dw 0xc9c0, 0xc10d, 0xc9ff, 0xc10d, 0x21, 0 + .dw 0xca40, 0xc10d, 0xca7f, 0xc10d, 0x21, 0 + .dw 0xcac0, 0xc10d, 0xcaff, 0xc10d, 0x21, 0 + .dw 0xcb40, 0xc10d, 0xcb7f, 0xc10d, 0x21, 0 + .dw 0xcbc0, 0xc10d, 0xcbff, 0xc10d, 0x21, 0 + .dw 0xcc40, 0xc10d, 0xcc7f, 0xc10d, 0x21, 0 + .dw 0xccc0, 0xc10d, 0xccff, 0xc10d, 0x21, 0 + .dw 0xcd40, 0xc10d, 0xcd7f, 0xc10d, 0x21, 0 + .dw 0xcdc0, 0xc10d, 0xcdff, 0xc10d, 0x21, 0 + .dw 0xce40, 0xc10d, 0xce7f, 0xc10d, 0x21, 0 + .dw 0xcec0, 0xc10d, 0xceff, 0xc10d, 0x21, 0 + .dw 0xcf40, 0xc10d, 0xcf7f, 0xc10d, 0x21, 0 + .dw 0xcfc0, 0xc10d, 0xcfff, 0xc10d, 0x21, 0 + .dw 0xd040, 0xc10d, 0xd07f, 0xc10d, 0x21, 0 + .dw 0xd0c0, 0xc10d, 0xd0ff, 0xc10d, 0x21, 0 + .dw 0xd140, 0xc10d, 0xd17f, 0xc10d, 0x21, 0 + .dw 0xd1c0, 0xc10d, 0xd1ff, 0xc10d, 0x21, 0 + .dw 0xd240, 0xc10d, 0xd27f, 0xc10d, 0x21, 0 + .dw 0xd2c0, 0xc10d, 0xd2ff, 0xc10d, 0x21, 0 + .dw 0xd340, 0xc10d, 0xd37f, 0xc10d, 0x21, 0 + .dw 0xd3c0, 0xc10d, 0xd3ff, 0xc10d, 0x21, 0 + .dw 0xd440, 0xc10d, 0xd47f, 0xc10d, 0x21, 0 + .dw 0xd4c0, 0xc10d, 0xd4ff, 0xc10d, 0x21, 0 + .dw 0xd540, 0xc10d, 0xd57f, 0xc10d, 0x21, 0 + .dw 0xd5c0, 0xc10d, 0xd5ff, 0xc10d, 0x21, 0 + .dw 0xd640, 0xc10d, 0xd67f, 0xc10d, 0x21, 0 + .dw 0xd6c0, 0xc10d, 0xd6ff, 0xc10d, 0x21, 0 + .dw 0xd740, 0xc10d, 0xd77f, 0xc10d, 0x21, 0 + .dw 0xd7c0, 0xc10d, 0xd7ff, 0xc10d, 0x21, 0 + .dw 0xd840, 0xc10d, 0xd87f, 0xc10d, 0x21, 0 + .dw 0xd8c0, 0xc10d, 0xd8ff, 0xc10d, 0x21, 0 + .dw 0xd940, 0xc10d, 0xd97f, 0xc10d, 0x21, 0 + .dw 0xd9c0, 0xc10d, 0xdfff, 0xc10d, 0x21, 0 + .dw 0xe040, 0xc10d, 0xe07f, 0xc10d, 0x21, 0 + .dw 0xe0c0, 0xc10d, 0xe0ff, 0xc10d, 0x21, 0 + .dw 0xe140, 0xc10d, 0xe17f, 0xc10d, 0x21, 0 + .dw 0xe1c0, 0xc10d, 0xe1ff, 0xc10d, 0x21, 0 + .dw 0xe240, 0xc10d, 0xe27f, 0xc10d, 0x21, 0 + .dw 0xe2c0, 0xc10d, 0xe2ff, 0xc10d, 0x21, 0 + .dw 0xe340, 0xc10d, 0xe37f, 0xc10d, 0x21, 0 + .dw 0xe3c0, 0xc10d, 0xe3ff, 0xc10d, 0x21, 0 + .dw 0xe440, 0xc10d, 0xe47f, 0xc10d, 0x21, 0 + .dw 0xe4c0, 0xc10d, 0xe4ff, 0xc10d, 0x21, 0 + .dw 0xe540, 0xc10d, 0xe57f, 0xc10d, 0x21, 0 + .dw 0xe5c0, 0xc10d, 0xe5ff, 0xc10d, 0x21, 0 + .dw 0xe640, 0xc10d, 0xe67f, 0xc10d, 0x21, 0 + .dw 0xe6c0, 0xc10d, 0xe6ff, 0xc10d, 0x21, 0 + .dw 0xe740, 0xc10d, 0xe77f, 0xc10d, 0x21, 0 + .dw 0xe7c0, 0xc10d, 0xe7ff, 0xc10d, 0x21, 0 + .dw 0xe840, 0xc10d, 0xe87f, 0xc10d, 0x21, 0 + .dw 0xe8c0, 0xc10d, 0xe8ff, 0xc10d, 0x21, 0 + .dw 0xe940, 0xc10d, 0xe97f, 0xc10d, 0x21, 0 + .dw 0xe9c0, 0xc10d, 0xe9ff, 0xc10d, 0x21, 0 + .dw 0xea40, 0xc10d, 0xea7f, 0xc10d, 0x21, 0 + .dw 0xeac0, 0xc10d, 0xeaff, 0xc10d, 0x21, 0 + .dw 0xeb40, 0xc10d, 0xeb7f, 0xc10d, 0x21, 0 + .dw 0xebc0, 0xc10d, 0xebff, 0xc10d, 0x21, 0 + .dw 0xec40, 0xc10d, 0xec7f, 0xc10d, 0x21, 0 + .dw 0xecc0, 0xc10d, 0xecff, 0xc10d, 0x21, 0 + .dw 0xed40, 0xc10d, 0xed7f, 0xc10d, 0x21, 0 + .dw 0xedc0, 0xc10d, 0xedff, 0xc10d, 0x21, 0 + .dw 0xee40, 0xc10d, 0xee7f, 0xc10d, 0x21, 0 + .dw 0xeec0, 0xc10d, 0xeeff, 0xc10d, 0x21, 0 + .dw 0xef40, 0xc10d, 0xef7f, 0xc10d, 0x21, 0 + .dw 0xefc0, 0xc10d, 0xefff, 0xc10d, 0x21, 0 + .dw 0xf040, 0xc10d, 0xf07f, 0xc10d, 0x21, 0 + .dw 0xf0c0, 0xc10d, 0xf0ff, 0xc10d, 0x21, 0 + .dw 0xf140, 0xc10d, 0xf17f, 0xc10d, 0x21, 0 + .dw 0xf1c0, 0xc10d, 0xf1ff, 0xc10d, 0x21, 0 + .dw 0xf240, 0xc10d, 0xf27f, 0xc10d, 0x21, 0 + .dw 0xf2c0, 0xc10d, 0xf2ff, 0xc10d, 0x21, 0 + .dw 0xf340, 0xc10d, 0xf37f, 0xc10d, 0x21, 0 + .dw 0xf3c0, 0xc10d, 0xf3ff, 0xc10d, 0x21, 0 + .dw 0xf440, 0xc10d, 0xf47f, 0xc10d, 0x21, 0 + .dw 0xf4c0, 0xc10d, 0xf4ff, 0xc10d, 0x21, 0 + .dw 0xf540, 0xc10d, 0xf57f, 0xc10d, 0x21, 0 + .dw 0xf5c0, 0xc10d, 0xf5ff, 0xc10d, 0x21, 0 + .dw 0xf640, 0xc10d, 0xf67f, 0xc10d, 0x21, 0 + .dw 0xf6c0, 0xc10d, 0xf6ff, 0xc10d, 0x21, 0 + .dw 0xf740, 0xc10d, 0xf77f, 0xc10d, 0x21, 0 + .dw 0xf7c0, 0xc10d, 0xf7ff, 0xc10d, 0x21, 0 + .dw 0xf840, 0xc10d, 0xf87f, 0xc10d, 0x21, 0 + .dw 0xf8c0, 0xc10d, 0xf8ff, 0xc10d, 0x21, 0 + .dw 0xf940, 0xc10d, 0xf97f, 0xc10d, 0x21, 0 + .dw 0xf9c0, 0xc10d, 0xffff, 0xc10d, 0x21, 0 + .dw 0x0040, 0xc10e, 0x007f, 0xc10e, 0x21, 0 + .dw 0x00c0, 0xc10e, 0x00ff, 0xc10e, 0x21, 0 + .dw 0x0140, 0xc10e, 0x017f, 0xc10e, 0x21, 0 + .dw 0x01c0, 0xc10e, 0x01ff, 0xc10e, 0x21, 0 + .dw 0x0240, 0xc10e, 0x027f, 0xc10e, 0x21, 0 + .dw 0x02c0, 0xc10e, 0x02ff, 0xc10e, 0x21, 0 + .dw 0x0340, 0xc10e, 0x037f, 0xc10e, 0x21, 0 + .dw 0x03c0, 0xc10e, 0x03ff, 0xc10e, 0x21, 0 + .dw 0x0440, 0xc10e, 0x047f, 0xc10e, 0x21, 0 + .dw 0x04c0, 0xc10e, 0x04ff, 0xc10e, 0x21, 0 + .dw 0x0540, 0xc10e, 0x057f, 0xc10e, 0x21, 0 + .dw 0x05c0, 0xc10e, 0x05ff, 0xc10e, 0x21, 0 + .dw 0x0640, 0xc10e, 0x067f, 0xc10e, 0x21, 0 + .dw 0x06c0, 0xc10e, 0x06ff, 0xc10e, 0x21, 0 + .dw 0x0740, 0xc10e, 0x077f, 0xc10e, 0x21, 0 + .dw 0x07c0, 0xc10e, 0x07ff, 0xc10e, 0x21, 0 + .dw 0x0840, 0xc10e, 0x087f, 0xc10e, 0x21, 0 + .dw 0x08c0, 0xc10e, 0x08ff, 0xc10e, 0x21, 0 + .dw 0x0940, 0xc10e, 0x097f, 0xc10e, 0x21, 0 + .dw 0x09c0, 0xc10e, 0x09ff, 0xc10e, 0x21, 0 + .dw 0x0a40, 0xc10e, 0x0a7f, 0xc10e, 0x21, 0 + .dw 0x0ac0, 0xc10e, 0x0aff, 0xc10e, 0x21, 0 + .dw 0x0b40, 0xc10e, 0x0b7f, 0xc10e, 0x21, 0 + .dw 0x0bc0, 0xc10e, 0x0bff, 0xc10e, 0x21, 0 + .dw 0x0c40, 0xc10e, 0x0c7f, 0xc10e, 0x21, 0 + .dw 0x0cc0, 0xc10e, 0x0cff, 0xc10e, 0x21, 0 + .dw 0x0d40, 0xc10e, 0x0d7f, 0xc10e, 0x21, 0 + .dw 0x0dc0, 0xc10e, 0x0dff, 0xc10e, 0x21, 0 + .dw 0x0e40, 0xc10e, 0x0e7f, 0xc10e, 0x21, 0 + .dw 0x0ec0, 0xc10e, 0x0eff, 0xc10e, 0x21, 0 + .dw 0x0f40, 0xc10e, 0x0f7f, 0xc10e, 0x21, 0 + .dw 0x0fc0, 0xc10e, 0x0fff, 0xc10e, 0x21, 0 + .dw 0x1040, 0xc10e, 0x107f, 0xc10e, 0x21, 0 + .dw 0x10c0, 0xc10e, 0x10ff, 0xc10e, 0x21, 0 + .dw 0x1140, 0xc10e, 0x117f, 0xc10e, 0x21, 0 + .dw 0x11c0, 0xc10e, 0x11ff, 0xc10e, 0x21, 0 + .dw 0x1240, 0xc10e, 0x127f, 0xc10e, 0x21, 0 + .dw 0x12c0, 0xc10e, 0x12ff, 0xc10e, 0x21, 0 + .dw 0x1340, 0xc10e, 0x137f, 0xc10e, 0x21, 0 + .dw 0x13c0, 0xc10e, 0x13ff, 0xc10e, 0x21, 0 + .dw 0x1440, 0xc10e, 0x147f, 0xc10e, 0x21, 0 + .dw 0x14c0, 0xc10e, 0x14ff, 0xc10e, 0x21, 0 + .dw 0x1540, 0xc10e, 0x157f, 0xc10e, 0x21, 0 + .dw 0x15c0, 0xc10e, 0x15ff, 0xc10e, 0x21, 0 + .dw 0x1640, 0xc10e, 0x167f, 0xc10e, 0x21, 0 + .dw 0x16c0, 0xc10e, 0x16ff, 0xc10e, 0x21, 0 + .dw 0x1740, 0xc10e, 0x177f, 0xc10e, 0x21, 0 + .dw 0x17c0, 0xc10e, 0x17ff, 0xc10e, 0x21, 0 + .dw 0x1840, 0xc10e, 0x187f, 0xc10e, 0x21, 0 + .dw 0x18c0, 0xc10e, 0x18ff, 0xc10e, 0x21, 0 + .dw 0x1940, 0xc10e, 0x197f, 0xc10e, 0x21, 0 + .dw 0x19c0, 0xc10e, 0x1fff, 0xc10e, 0x21, 0 + .dw 0x2040, 0xc10e, 0x207f, 0xc10e, 0x21, 0 + .dw 0x20c0, 0xc10e, 0x20ff, 0xc10e, 0x21, 0 + .dw 0x2140, 0xc10e, 0x217f, 0xc10e, 0x21, 0 + .dw 0x21c0, 0xc10e, 0x21ff, 0xc10e, 0x21, 0 + .dw 0x2240, 0xc10e, 0x227f, 0xc10e, 0x21, 0 + .dw 0x22c0, 0xc10e, 0x22ff, 0xc10e, 0x21, 0 + .dw 0x2340, 0xc10e, 0x237f, 0xc10e, 0x21, 0 + .dw 0x23c0, 0xc10e, 0x23ff, 0xc10e, 0x21, 0 + .dw 0x2440, 0xc10e, 0x247f, 0xc10e, 0x21, 0 + .dw 0x24c0, 0xc10e, 0x24ff, 0xc10e, 0x21, 0 + .dw 0x2540, 0xc10e, 0x257f, 0xc10e, 0x21, 0 + .dw 0x25c0, 0xc10e, 0x25ff, 0xc10e, 0x21, 0 + .dw 0x2640, 0xc10e, 0x267f, 0xc10e, 0x21, 0 + .dw 0x26c0, 0xc10e, 0x26ff, 0xc10e, 0x21, 0 + .dw 0x2740, 0xc10e, 0x277f, 0xc10e, 0x21, 0 + .dw 0x27c0, 0xc10e, 0x27ff, 0xc10e, 0x21, 0 + .dw 0x2840, 0xc10e, 0x287f, 0xc10e, 0x21, 0 + .dw 0x28c0, 0xc10e, 0x28ff, 0xc10e, 0x21, 0 + .dw 0x2940, 0xc10e, 0x297f, 0xc10e, 0x21, 0 + .dw 0x29c0, 0xc10e, 0x29ff, 0xc10e, 0x21, 0 + .dw 0x2a40, 0xc10e, 0x2a7f, 0xc10e, 0x21, 0 + .dw 0x2ac0, 0xc10e, 0x2aff, 0xc10e, 0x21, 0 + .dw 0x2b40, 0xc10e, 0x2b7f, 0xc10e, 0x21, 0 + .dw 0x2bc0, 0xc10e, 0x2bff, 0xc10e, 0x21, 0 + .dw 0x2c40, 0xc10e, 0x2c7f, 0xc10e, 0x21, 0 + .dw 0x2cc0, 0xc10e, 0x2cff, 0xc10e, 0x21, 0 + .dw 0x2d40, 0xc10e, 0x2d7f, 0xc10e, 0x21, 0 + .dw 0x2dc0, 0xc10e, 0x2dff, 0xc10e, 0x21, 0 + .dw 0x2e40, 0xc10e, 0x2e7f, 0xc10e, 0x21, 0 + .dw 0x2ec0, 0xc10e, 0x2eff, 0xc10e, 0x21, 0 + .dw 0x2f40, 0xc10e, 0x2f7f, 0xc10e, 0x21, 0 + .dw 0x2fc0, 0xc10e, 0x2fff, 0xc10e, 0x21, 0 + .dw 0x3040, 0xc10e, 0x307f, 0xc10e, 0x21, 0 + .dw 0x30c0, 0xc10e, 0x30ff, 0xc10e, 0x21, 0 + .dw 0x3140, 0xc10e, 0x317f, 0xc10e, 0x21, 0 + .dw 0x31c0, 0xc10e, 0x31ff, 0xc10e, 0x21, 0 + .dw 0x3240, 0xc10e, 0x327f, 0xc10e, 0x21, 0 + .dw 0x32c0, 0xc10e, 0x32ff, 0xc10e, 0x21, 0 + .dw 0x3340, 0xc10e, 0x337f, 0xc10e, 0x21, 0 + .dw 0x33c0, 0xc10e, 0x33ff, 0xc10e, 0x21, 0 + .dw 0x3440, 0xc10e, 0x347f, 0xc10e, 0x21, 0 + .dw 0x34c0, 0xc10e, 0x34ff, 0xc10e, 0x21, 0 + .dw 0x3540, 0xc10e, 0x357f, 0xc10e, 0x21, 0 + .dw 0x35c0, 0xc10e, 0x35ff, 0xc10e, 0x21, 0 + .dw 0x3640, 0xc10e, 0x367f, 0xc10e, 0x21, 0 + .dw 0x36c0, 0xc10e, 0x36ff, 0xc10e, 0x21, 0 + .dw 0x3740, 0xc10e, 0x377f, 0xc10e, 0x21, 0 + .dw 0x37c0, 0xc10e, 0x37ff, 0xc10e, 0x21, 0 + .dw 0x3840, 0xc10e, 0x387f, 0xc10e, 0x21, 0 + .dw 0x38c0, 0xc10e, 0x38ff, 0xc10e, 0x21, 0 + .dw 0x3940, 0xc10e, 0x397f, 0xc10e, 0x21, 0 + .dw 0x39c0, 0xc10e, 0x3fff, 0xc10e, 0x21, 0 + .dw 0x4040, 0xc10e, 0x407f, 0xc10e, 0x21, 0 + .dw 0x40c0, 0xc10e, 0x40ff, 0xc10e, 0x21, 0 + .dw 0x4140, 0xc10e, 0x417f, 0xc10e, 0x21, 0 + .dw 0x41c0, 0xc10e, 0x41ff, 0xc10e, 0x21, 0 + .dw 0x4240, 0xc10e, 0x427f, 0xc10e, 0x21, 0 + .dw 0x42c0, 0xc10e, 0x42ff, 0xc10e, 0x21, 0 + .dw 0x4340, 0xc10e, 0x437f, 0xc10e, 0x21, 0 + .dw 0x43c0, 0xc10e, 0x43ff, 0xc10e, 0x21, 0 + .dw 0x4440, 0xc10e, 0x447f, 0xc10e, 0x21, 0 + .dw 0x44c0, 0xc10e, 0x44ff, 0xc10e, 0x21, 0 + .dw 0x4540, 0xc10e, 0x457f, 0xc10e, 0x21, 0 + .dw 0x45c0, 0xc10e, 0x45ff, 0xc10e, 0x21, 0 + .dw 0x4640, 0xc10e, 0x467f, 0xc10e, 0x21, 0 + .dw 0x46c0, 0xc10e, 0x46ff, 0xc10e, 0x21, 0 + .dw 0x4740, 0xc10e, 0x477f, 0xc10e, 0x21, 0 + .dw 0x47c0, 0xc10e, 0x47ff, 0xc10e, 0x21, 0 + .dw 0x4840, 0xc10e, 0x487f, 0xc10e, 0x21, 0 + .dw 0x48c0, 0xc10e, 0x48ff, 0xc10e, 0x21, 0 + .dw 0x4940, 0xc10e, 0x497f, 0xc10e, 0x21, 0 + .dw 0x49c0, 0xc10e, 0x49ff, 0xc10e, 0x21, 0 + .dw 0x4a40, 0xc10e, 0x4a7f, 0xc10e, 0x21, 0 + .dw 0x4ac0, 0xc10e, 0x4aff, 0xc10e, 0x21, 0 + .dw 0x4b40, 0xc10e, 0x4b7f, 0xc10e, 0x21, 0 + .dw 0x4bc0, 0xc10e, 0x4bff, 0xc10e, 0x21, 0 + .dw 0x4c40, 0xc10e, 0x4c7f, 0xc10e, 0x21, 0 + .dw 0x4cc0, 0xc10e, 0x4cff, 0xc10e, 0x21, 0 + .dw 0x4d40, 0xc10e, 0x4d7f, 0xc10e, 0x21, 0 + .dw 0x4dc0, 0xc10e, 0x4dff, 0xc10e, 0x21, 0 + .dw 0x4e40, 0xc10e, 0x4e7f, 0xc10e, 0x21, 0 + .dw 0x4ec0, 0xc10e, 0x4eff, 0xc10e, 0x21, 0 + .dw 0x4f40, 0xc10e, 0x4f7f, 0xc10e, 0x21, 0 + .dw 0x4fc0, 0xc10e, 0x4fff, 0xc10e, 0x21, 0 + .dw 0x5040, 0xc10e, 0x507f, 0xc10e, 0x21, 0 + .dw 0x50c0, 0xc10e, 0x50ff, 0xc10e, 0x21, 0 + .dw 0x5140, 0xc10e, 0x517f, 0xc10e, 0x21, 0 + .dw 0x51c0, 0xc10e, 0x51ff, 0xc10e, 0x21, 0 + .dw 0x5240, 0xc10e, 0x527f, 0xc10e, 0x21, 0 + .dw 0x52c0, 0xc10e, 0x52ff, 0xc10e, 0x21, 0 + .dw 0x5340, 0xc10e, 0x537f, 0xc10e, 0x21, 0 + .dw 0x53c0, 0xc10e, 0x53ff, 0xc10e, 0x21, 0 + .dw 0x5440, 0xc10e, 0x547f, 0xc10e, 0x21, 0 + .dw 0x54c0, 0xc10e, 0x54ff, 0xc10e, 0x21, 0 + .dw 0x5540, 0xc10e, 0x557f, 0xc10e, 0x21, 0 + .dw 0x55c0, 0xc10e, 0x55ff, 0xc10e, 0x21, 0 + .dw 0x5640, 0xc10e, 0x567f, 0xc10e, 0x21, 0 + .dw 0x56c0, 0xc10e, 0x56ff, 0xc10e, 0x21, 0 + .dw 0x5740, 0xc10e, 0x577f, 0xc10e, 0x21, 0 + .dw 0x57c0, 0xc10e, 0x57ff, 0xc10e, 0x21, 0 + .dw 0x5840, 0xc10e, 0x587f, 0xc10e, 0x21, 0 + .dw 0x58c0, 0xc10e, 0x58ff, 0xc10e, 0x21, 0 + .dw 0x5940, 0xc10e, 0x597f, 0xc10e, 0x21, 0 + .dw 0x59c0, 0xc10e, 0x5fff, 0xc10e, 0x21, 0 + .dw 0x6040, 0xc10e, 0x607f, 0xc10e, 0x21, 0 + .dw 0x60c0, 0xc10e, 0x60ff, 0xc10e, 0x21, 0 + .dw 0x6140, 0xc10e, 0x617f, 0xc10e, 0x21, 0 + .dw 0x61c0, 0xc10e, 0x61ff, 0xc10e, 0x21, 0 + .dw 0x6240, 0xc10e, 0x627f, 0xc10e, 0x21, 0 + .dw 0x62c0, 0xc10e, 0x62ff, 0xc10e, 0x21, 0 + .dw 0x6340, 0xc10e, 0x637f, 0xc10e, 0x21, 0 + .dw 0x63c0, 0xc10e, 0x63ff, 0xc10e, 0x21, 0 + .dw 0x6440, 0xc10e, 0x647f, 0xc10e, 0x21, 0 + .dw 0x64c0, 0xc10e, 0x64ff, 0xc10e, 0x21, 0 + .dw 0x6540, 0xc10e, 0x657f, 0xc10e, 0x21, 0 + .dw 0x65c0, 0xc10e, 0x65ff, 0xc10e, 0x21, 0 + .dw 0x6640, 0xc10e, 0x667f, 0xc10e, 0x21, 0 + .dw 0x66c0, 0xc10e, 0x66ff, 0xc10e, 0x21, 0 + .dw 0x6740, 0xc10e, 0x677f, 0xc10e, 0x21, 0 + .dw 0x67c0, 0xc10e, 0x67ff, 0xc10e, 0x21, 0 + .dw 0x6840, 0xc10e, 0x687f, 0xc10e, 0x21, 0 + .dw 0x68c0, 0xc10e, 0x68ff, 0xc10e, 0x21, 0 + .dw 0x6940, 0xc10e, 0x697f, 0xc10e, 0x21, 0 + .dw 0x69c0, 0xc10e, 0x69ff, 0xc10e, 0x21, 0 + .dw 0x6a40, 0xc10e, 0x6a7f, 0xc10e, 0x21, 0 + .dw 0x6ac0, 0xc10e, 0x6aff, 0xc10e, 0x21, 0 + .dw 0x6b40, 0xc10e, 0x6b7f, 0xc10e, 0x21, 0 + .dw 0x6bc0, 0xc10e, 0x6bff, 0xc10e, 0x21, 0 + .dw 0x6c40, 0xc10e, 0x6c7f, 0xc10e, 0x21, 0 + .dw 0x6cc0, 0xc10e, 0x6cff, 0xc10e, 0x21, 0 + .dw 0x6d40, 0xc10e, 0x6d7f, 0xc10e, 0x21, 0 + .dw 0x6dc0, 0xc10e, 0x6dff, 0xc10e, 0x21, 0 + .dw 0x6e40, 0xc10e, 0x6e7f, 0xc10e, 0x21, 0 + .dw 0x6ec0, 0xc10e, 0x6eff, 0xc10e, 0x21, 0 + .dw 0x6f40, 0xc10e, 0x6f7f, 0xc10e, 0x21, 0 + .dw 0x6fc0, 0xc10e, 0x6fff, 0xc10e, 0x21, 0 + .dw 0x7040, 0xc10e, 0x707f, 0xc10e, 0x21, 0 + .dw 0x70c0, 0xc10e, 0x70ff, 0xc10e, 0x21, 0 + .dw 0x7140, 0xc10e, 0x717f, 0xc10e, 0x21, 0 + .dw 0x71c0, 0xc10e, 0x71ff, 0xc10e, 0x21, 0 + .dw 0x7240, 0xc10e, 0x727f, 0xc10e, 0x21, 0 + .dw 0x72c0, 0xc10e, 0x72ff, 0xc10e, 0x21, 0 + .dw 0x7340, 0xc10e, 0x737f, 0xc10e, 0x21, 0 + .dw 0x73c0, 0xc10e, 0x73ff, 0xc10e, 0x21, 0 + .dw 0x7440, 0xc10e, 0x747f, 0xc10e, 0x21, 0 + .dw 0x74c0, 0xc10e, 0x74ff, 0xc10e, 0x21, 0 + .dw 0x7540, 0xc10e, 0x757f, 0xc10e, 0x21, 0 + .dw 0x75c0, 0xc10e, 0x75ff, 0xc10e, 0x21, 0 + .dw 0x7640, 0xc10e, 0x767f, 0xc10e, 0x21, 0 + .dw 0x76c0, 0xc10e, 0x76ff, 0xc10e, 0x21, 0 + .dw 0x7740, 0xc10e, 0x777f, 0xc10e, 0x21, 0 + .dw 0x77c0, 0xc10e, 0x77ff, 0xc10e, 0x21, 0 + .dw 0x7840, 0xc10e, 0x787f, 0xc10e, 0x21, 0 + .dw 0x78c0, 0xc10e, 0x78ff, 0xc10e, 0x21, 0 + .dw 0x7940, 0xc10e, 0x797f, 0xc10e, 0x21, 0 + .dw 0x79c0, 0xc10e, 0x7fff, 0xc10e, 0x21, 0 + .dw 0x8040, 0xc10e, 0x807f, 0xc10e, 0x21, 0 + .dw 0x80c0, 0xc10e, 0x80ff, 0xc10e, 0x21, 0 + .dw 0x8140, 0xc10e, 0x817f, 0xc10e, 0x21, 0 + .dw 0x81c0, 0xc10e, 0x81ff, 0xc10e, 0x21, 0 + .dw 0x8240, 0xc10e, 0x827f, 0xc10e, 0x21, 0 + .dw 0x82c0, 0xc10e, 0x82ff, 0xc10e, 0x21, 0 + .dw 0x8340, 0xc10e, 0x837f, 0xc10e, 0x21, 0 + .dw 0x83c0, 0xc10e, 0x83ff, 0xc10e, 0x21, 0 + .dw 0x8440, 0xc10e, 0x847f, 0xc10e, 0x21, 0 + .dw 0x84c0, 0xc10e, 0x84ff, 0xc10e, 0x21, 0 + .dw 0x8540, 0xc10e, 0x857f, 0xc10e, 0x21, 0 + .dw 0x85c0, 0xc10e, 0x85ff, 0xc10e, 0x21, 0 + .dw 0x8640, 0xc10e, 0x867f, 0xc10e, 0x21, 0 + .dw 0x86c0, 0xc10e, 0x86ff, 0xc10e, 0x21, 0 + .dw 0x8740, 0xc10e, 0x877f, 0xc10e, 0x21, 0 + .dw 0x87c0, 0xc10e, 0x87ff, 0xc10e, 0x21, 0 + .dw 0x8840, 0xc10e, 0x887f, 0xc10e, 0x21, 0 + .dw 0x88c0, 0xc10e, 0x88ff, 0xc10e, 0x21, 0 + .dw 0x8940, 0xc10e, 0x897f, 0xc10e, 0x21, 0 + .dw 0x89c0, 0xc10e, 0x89ff, 0xc10e, 0x21, 0 + .dw 0x8a40, 0xc10e, 0x8a7f, 0xc10e, 0x21, 0 + .dw 0x8ac0, 0xc10e, 0x8aff, 0xc10e, 0x21, 0 + .dw 0x8b40, 0xc10e, 0x8b7f, 0xc10e, 0x21, 0 + .dw 0x8bc0, 0xc10e, 0x8bff, 0xc10e, 0x21, 0 + .dw 0x8c40, 0xc10e, 0x8c7f, 0xc10e, 0x21, 0 + .dw 0x8cc0, 0xc10e, 0x8cff, 0xc10e, 0x21, 0 + .dw 0x8d40, 0xc10e, 0x8d7f, 0xc10e, 0x21, 0 + .dw 0x8dc0, 0xc10e, 0x8dff, 0xc10e, 0x21, 0 + .dw 0x8e40, 0xc10e, 0x8e7f, 0xc10e, 0x21, 0 + .dw 0x8ec0, 0xc10e, 0x8eff, 0xc10e, 0x21, 0 + .dw 0x8f40, 0xc10e, 0x8f7f, 0xc10e, 0x21, 0 + .dw 0x8fc0, 0xc10e, 0x8fff, 0xc10e, 0x21, 0 + .dw 0x9040, 0xc10e, 0x907f, 0xc10e, 0x21, 0 + .dw 0x90c0, 0xc10e, 0x90ff, 0xc10e, 0x21, 0 + .dw 0x9140, 0xc10e, 0x917f, 0xc10e, 0x21, 0 + .dw 0x91c0, 0xc10e, 0x91ff, 0xc10e, 0x21, 0 + .dw 0x9240, 0xc10e, 0x927f, 0xc10e, 0x21, 0 + .dw 0x92c0, 0xc10e, 0x92ff, 0xc10e, 0x21, 0 + .dw 0x9340, 0xc10e, 0x937f, 0xc10e, 0x21, 0 + .dw 0x93c0, 0xc10e, 0x93ff, 0xc10e, 0x21, 0 + .dw 0x9440, 0xc10e, 0x947f, 0xc10e, 0x21, 0 + .dw 0x94c0, 0xc10e, 0x94ff, 0xc10e, 0x21, 0 + .dw 0x9540, 0xc10e, 0x957f, 0xc10e, 0x21, 0 + .dw 0x95c0, 0xc10e, 0x95ff, 0xc10e, 0x21, 0 + .dw 0x9640, 0xc10e, 0x967f, 0xc10e, 0x21, 0 + .dw 0x96c0, 0xc10e, 0x96ff, 0xc10e, 0x21, 0 + .dw 0x9740, 0xc10e, 0x977f, 0xc10e, 0x21, 0 + .dw 0x97c0, 0xc10e, 0x97ff, 0xc10e, 0x21, 0 + .dw 0x9840, 0xc10e, 0x987f, 0xc10e, 0x21, 0 + .dw 0x98c0, 0xc10e, 0x98ff, 0xc10e, 0x21, 0 + .dw 0x9940, 0xc10e, 0x997f, 0xc10e, 0x21, 0 + .dw 0x99c0, 0xc10e, 0x9fff, 0xc10e, 0x21, 0 + .dw 0xa040, 0xc10e, 0xa07f, 0xc10e, 0x21, 0 + .dw 0xa0c0, 0xc10e, 0xa0ff, 0xc10e, 0x21, 0 + .dw 0xa140, 0xc10e, 0xa17f, 0xc10e, 0x21, 0 + .dw 0xa1c0, 0xc10e, 0xa1ff, 0xc10e, 0x21, 0 + .dw 0xa240, 0xc10e, 0xa27f, 0xc10e, 0x21, 0 + .dw 0xa2c0, 0xc10e, 0xa2ff, 0xc10e, 0x21, 0 + .dw 0xa340, 0xc10e, 0xa37f, 0xc10e, 0x21, 0 + .dw 0xa3c0, 0xc10e, 0xa3ff, 0xc10e, 0x21, 0 + .dw 0xa440, 0xc10e, 0xa47f, 0xc10e, 0x21, 0 + .dw 0xa4c0, 0xc10e, 0xa4ff, 0xc10e, 0x21, 0 + .dw 0xa540, 0xc10e, 0xa57f, 0xc10e, 0x21, 0 + .dw 0xa5c0, 0xc10e, 0xa5ff, 0xc10e, 0x21, 0 + .dw 0xa640, 0xc10e, 0xa67f, 0xc10e, 0x21, 0 + .dw 0xa6c0, 0xc10e, 0xa6ff, 0xc10e, 0x21, 0 + .dw 0xa740, 0xc10e, 0xa77f, 0xc10e, 0x21, 0 + .dw 0xa7c0, 0xc10e, 0xa7ff, 0xc10e, 0x21, 0 + .dw 0xa840, 0xc10e, 0xa87f, 0xc10e, 0x21, 0 + .dw 0xa8c0, 0xc10e, 0xa8ff, 0xc10e, 0x21, 0 + .dw 0xa940, 0xc10e, 0xa97f, 0xc10e, 0x21, 0 + .dw 0xa9c0, 0xc10e, 0xa9ff, 0xc10e, 0x21, 0 + .dw 0xaa40, 0xc10e, 0xaa7f, 0xc10e, 0x21, 0 + .dw 0xaac0, 0xc10e, 0xaaff, 0xc10e, 0x21, 0 + .dw 0xab40, 0xc10e, 0xab7f, 0xc10e, 0x21, 0 + .dw 0xabc0, 0xc10e, 0xabff, 0xc10e, 0x21, 0 + .dw 0xac40, 0xc10e, 0xac7f, 0xc10e, 0x21, 0 + .dw 0xacc0, 0xc10e, 0xacff, 0xc10e, 0x21, 0 + .dw 0xad40, 0xc10e, 0xad7f, 0xc10e, 0x21, 0 + .dw 0xadc0, 0xc10e, 0xadff, 0xc10e, 0x21, 0 + .dw 0xae40, 0xc10e, 0xae7f, 0xc10e, 0x21, 0 + .dw 0xaec0, 0xc10e, 0xaeff, 0xc10e, 0x21, 0 + .dw 0xaf40, 0xc10e, 0xaf7f, 0xc10e, 0x21, 0 + .dw 0xafc0, 0xc10e, 0xafff, 0xc10e, 0x21, 0 + .dw 0xb040, 0xc10e, 0xb07f, 0xc10e, 0x21, 0 + .dw 0xb0c0, 0xc10e, 0xb0ff, 0xc10e, 0x21, 0 + .dw 0xb140, 0xc10e, 0xb17f, 0xc10e, 0x21, 0 + .dw 0xb1c0, 0xc10e, 0xb1ff, 0xc10e, 0x21, 0 + .dw 0xb240, 0xc10e, 0xb27f, 0xc10e, 0x21, 0 + .dw 0xb2c0, 0xc10e, 0xb2ff, 0xc10e, 0x21, 0 + .dw 0xb340, 0xc10e, 0xb37f, 0xc10e, 0x21, 0 + .dw 0xb3c0, 0xc10e, 0xb3ff, 0xc10e, 0x21, 0 + .dw 0xb440, 0xc10e, 0xb47f, 0xc10e, 0x21, 0 + .dw 0xb4c0, 0xc10e, 0xb4ff, 0xc10e, 0x21, 0 + .dw 0xb540, 0xc10e, 0xb57f, 0xc10e, 0x21, 0 + .dw 0xb5c0, 0xc10e, 0xb5ff, 0xc10e, 0x21, 0 + .dw 0xb640, 0xc10e, 0xb67f, 0xc10e, 0x21, 0 + .dw 0xb6c0, 0xc10e, 0xb6ff, 0xc10e, 0x21, 0 + .dw 0xb740, 0xc10e, 0xb77f, 0xc10e, 0x21, 0 + .dw 0xb7c0, 0xc10e, 0xb7ff, 0xc10e, 0x21, 0 + .dw 0xb840, 0xc10e, 0xb87f, 0xc10e, 0x21, 0 + .dw 0xb8c0, 0xc10e, 0xb8ff, 0xc10e, 0x21, 0 + .dw 0xb940, 0xc10e, 0xb97f, 0xc10e, 0x21, 0 + .dw 0xb9c0, 0xc10e, 0xbfff, 0xc10e, 0x21, 0 + .dw 0xc040, 0xc10e, 0xc07f, 0xc10e, 0x21, 0 + .dw 0xc0c0, 0xc10e, 0xc0ff, 0xc10e, 0x21, 0 + .dw 0xc140, 0xc10e, 0xc17f, 0xc10e, 0x21, 0 + .dw 0xc1c0, 0xc10e, 0xc1ff, 0xc10e, 0x21, 0 + .dw 0xc240, 0xc10e, 0xc27f, 0xc10e, 0x21, 0 + .dw 0xc2c0, 0xc10e, 0xc2ff, 0xc10e, 0x21, 0 + .dw 0xc340, 0xc10e, 0xc37f, 0xc10e, 0x21, 0 + .dw 0xc3c0, 0xc10e, 0xc3ff, 0xc10e, 0x21, 0 + .dw 0xc440, 0xc10e, 0xc47f, 0xc10e, 0x21, 0 + .dw 0xc4c0, 0xc10e, 0xc4ff, 0xc10e, 0x21, 0 + .dw 0xc540, 0xc10e, 0xc57f, 0xc10e, 0x21, 0 + .dw 0xc5c0, 0xc10e, 0xc5ff, 0xc10e, 0x21, 0 + .dw 0xc640, 0xc10e, 0xc67f, 0xc10e, 0x21, 0 + .dw 0xc6c0, 0xc10e, 0xc6ff, 0xc10e, 0x21, 0 + .dw 0xc740, 0xc10e, 0xc77f, 0xc10e, 0x21, 0 + .dw 0xc7c0, 0xc10e, 0xc7ff, 0xc10e, 0x21, 0 + .dw 0xc840, 0xc10e, 0xc87f, 0xc10e, 0x21, 0 + .dw 0xc8c0, 0xc10e, 0xc8ff, 0xc10e, 0x21, 0 + .dw 0xc940, 0xc10e, 0xc97f, 0xc10e, 0x21, 0 + .dw 0xc9c0, 0xc10e, 0xc9ff, 0xc10e, 0x21, 0 + .dw 0xca40, 0xc10e, 0xca7f, 0xc10e, 0x21, 0 + .dw 0xcac0, 0xc10e, 0xcaff, 0xc10e, 0x21, 0 + .dw 0xcb40, 0xc10e, 0xcb7f, 0xc10e, 0x21, 0 + .dw 0xcbc0, 0xc10e, 0xcbff, 0xc10e, 0x21, 0 + .dw 0xcc40, 0xc10e, 0xcc7f, 0xc10e, 0x21, 0 + .dw 0xccc0, 0xc10e, 0xccff, 0xc10e, 0x21, 0 + .dw 0xcd40, 0xc10e, 0xcd7f, 0xc10e, 0x21, 0 + .dw 0xcdc0, 0xc10e, 0xcdff, 0xc10e, 0x21, 0 + .dw 0xce40, 0xc10e, 0xce7f, 0xc10e, 0x21, 0 + .dw 0xcec0, 0xc10e, 0xceff, 0xc10e, 0x21, 0 + .dw 0xcf40, 0xc10e, 0xcf7f, 0xc10e, 0x21, 0 + .dw 0xcfc0, 0xc10e, 0xcfff, 0xc10e, 0x21, 0 + .dw 0xd040, 0xc10e, 0xd07f, 0xc10e, 0x21, 0 + .dw 0xd0c0, 0xc10e, 0xd0ff, 0xc10e, 0x21, 0 + .dw 0xd140, 0xc10e, 0xd17f, 0xc10e, 0x21, 0 + .dw 0xd1c0, 0xc10e, 0xd1ff, 0xc10e, 0x21, 0 + .dw 0xd240, 0xc10e, 0xd27f, 0xc10e, 0x21, 0 + .dw 0xd2c0, 0xc10e, 0xd2ff, 0xc10e, 0x21, 0 + .dw 0xd340, 0xc10e, 0xd37f, 0xc10e, 0x21, 0 + .dw 0xd3c0, 0xc10e, 0xd3ff, 0xc10e, 0x21, 0 + .dw 0xd440, 0xc10e, 0xd47f, 0xc10e, 0x21, 0 + .dw 0xd4c0, 0xc10e, 0xd4ff, 0xc10e, 0x21, 0 + .dw 0xd540, 0xc10e, 0xd57f, 0xc10e, 0x21, 0 + .dw 0xd5c0, 0xc10e, 0xd5ff, 0xc10e, 0x21, 0 + .dw 0xd640, 0xc10e, 0xd67f, 0xc10e, 0x21, 0 + .dw 0xd6c0, 0xc10e, 0xd6ff, 0xc10e, 0x21, 0 + .dw 0xd740, 0xc10e, 0xd77f, 0xc10e, 0x21, 0 + .dw 0xd7c0, 0xc10e, 0xd7ff, 0xc10e, 0x21, 0 + .dw 0xd840, 0xc10e, 0xd87f, 0xc10e, 0x21, 0 + .dw 0xd8c0, 0xc10e, 0xd8ff, 0xc10e, 0x21, 0 + .dw 0xd940, 0xc10e, 0xd97f, 0xc10e, 0x21, 0 + .dw 0xd9c0, 0xc10e, 0xdfff, 0xc10e, 0x21, 0 + .dw 0xe040, 0xc10e, 0xe07f, 0xc10e, 0x21, 0 + .dw 0xe0c0, 0xc10e, 0xe0ff, 0xc10e, 0x21, 0 + .dw 0xe140, 0xc10e, 0xe17f, 0xc10e, 0x21, 0 + .dw 0xe1c0, 0xc10e, 0xe1ff, 0xc10e, 0x21, 0 + .dw 0xe240, 0xc10e, 0xe27f, 0xc10e, 0x21, 0 + .dw 0xe2c0, 0xc10e, 0xe2ff, 0xc10e, 0x21, 0 + .dw 0xe340, 0xc10e, 0xe37f, 0xc10e, 0x21, 0 + .dw 0xe3c0, 0xc10e, 0xe3ff, 0xc10e, 0x21, 0 + .dw 0xe440, 0xc10e, 0xe47f, 0xc10e, 0x21, 0 + .dw 0xe4c0, 0xc10e, 0xe4ff, 0xc10e, 0x21, 0 + .dw 0xe540, 0xc10e, 0xe57f, 0xc10e, 0x21, 0 + .dw 0xe5c0, 0xc10e, 0xe5ff, 0xc10e, 0x21, 0 + .dw 0xe640, 0xc10e, 0xe67f, 0xc10e, 0x21, 0 + .dw 0xe6c0, 0xc10e, 0xe6ff, 0xc10e, 0x21, 0 + .dw 0xe740, 0xc10e, 0xe77f, 0xc10e, 0x21, 0 + .dw 0xe7c0, 0xc10e, 0xe7ff, 0xc10e, 0x21, 0 + .dw 0xe840, 0xc10e, 0xe87f, 0xc10e, 0x21, 0 + .dw 0xe8c0, 0xc10e, 0xe8ff, 0xc10e, 0x21, 0 + .dw 0xe940, 0xc10e, 0xe97f, 0xc10e, 0x21, 0 + .dw 0xe9c0, 0xc10e, 0xe9ff, 0xc10e, 0x21, 0 + .dw 0xea40, 0xc10e, 0xea7f, 0xc10e, 0x21, 0 + .dw 0xeac0, 0xc10e, 0xeaff, 0xc10e, 0x21, 0 + .dw 0xeb40, 0xc10e, 0xeb7f, 0xc10e, 0x21, 0 + .dw 0xebc0, 0xc10e, 0xebff, 0xc10e, 0x21, 0 + .dw 0xec40, 0xc10e, 0xec7f, 0xc10e, 0x21, 0 + .dw 0xecc0, 0xc10e, 0xecff, 0xc10e, 0x21, 0 + .dw 0xed40, 0xc10e, 0xed7f, 0xc10e, 0x21, 0 + .dw 0xedc0, 0xc10e, 0xedff, 0xc10e, 0x21, 0 + .dw 0xee40, 0xc10e, 0xee7f, 0xc10e, 0x21, 0 + .dw 0xeec0, 0xc10e, 0xeeff, 0xc10e, 0x21, 0 + .dw 0xef40, 0xc10e, 0xef7f, 0xc10e, 0x21, 0 + .dw 0xefc0, 0xc10e, 0xefff, 0xc10e, 0x21, 0 + .dw 0xf040, 0xc10e, 0xf07f, 0xc10e, 0x21, 0 + .dw 0xf0c0, 0xc10e, 0xf0ff, 0xc10e, 0x21, 0 + .dw 0xf140, 0xc10e, 0xf17f, 0xc10e, 0x21, 0 + .dw 0xf1c0, 0xc10e, 0xf1ff, 0xc10e, 0x21, 0 + .dw 0xf240, 0xc10e, 0xf27f, 0xc10e, 0x21, 0 + .dw 0xf2c0, 0xc10e, 0xf2ff, 0xc10e, 0x21, 0 + .dw 0xf340, 0xc10e, 0xf37f, 0xc10e, 0x21, 0 + .dw 0xf3c0, 0xc10e, 0xf3ff, 0xc10e, 0x21, 0 + .dw 0xf440, 0xc10e, 0xf47f, 0xc10e, 0x21, 0 + .dw 0xf4c0, 0xc10e, 0xf4ff, 0xc10e, 0x21, 0 + .dw 0xf540, 0xc10e, 0xf57f, 0xc10e, 0x21, 0 + .dw 0xf5c0, 0xc10e, 0xf5ff, 0xc10e, 0x21, 0 + .dw 0xf640, 0xc10e, 0xf67f, 0xc10e, 0x21, 0 + .dw 0xf6c0, 0xc10e, 0xf6ff, 0xc10e, 0x21, 0 + .dw 0xf740, 0xc10e, 0xf77f, 0xc10e, 0x21, 0 + .dw 0xf7c0, 0xc10e, 0xf7ff, 0xc10e, 0x21, 0 + .dw 0xf840, 0xc10e, 0xf87f, 0xc10e, 0x21, 0 + .dw 0xf8c0, 0xc10e, 0xf8ff, 0xc10e, 0x21, 0 + .dw 0xf940, 0xc10e, 0xf97f, 0xc10e, 0x21, 0 + .dw 0xf9c0, 0xc10e, 0xffff, 0xc10e, 0x21, 0 + .dw 0x0040, 0xc10f, 0x007f, 0xc10f, 0x21, 0 + .dw 0x00c0, 0xc10f, 0x00ff, 0xc10f, 0x21, 0 + .dw 0x0140, 0xc10f, 0x017f, 0xc10f, 0x21, 0 + .dw 0x01c0, 0xc10f, 0x01ff, 0xc10f, 0x21, 0 + .dw 0x0240, 0xc10f, 0x027f, 0xc10f, 0x21, 0 + .dw 0x02c0, 0xc10f, 0x02ff, 0xc10f, 0x21, 0 + .dw 0x0340, 0xc10f, 0x037f, 0xc10f, 0x21, 0 + .dw 0x03c0, 0xc10f, 0x03ff, 0xc10f, 0x21, 0 + .dw 0x0440, 0xc10f, 0x047f, 0xc10f, 0x21, 0 + .dw 0x04c0, 0xc10f, 0x04ff, 0xc10f, 0x21, 0 + .dw 0x0540, 0xc10f, 0x057f, 0xc10f, 0x21, 0 + .dw 0x05c0, 0xc10f, 0x05ff, 0xc10f, 0x21, 0 + .dw 0x0640, 0xc10f, 0x067f, 0xc10f, 0x21, 0 + .dw 0x06c0, 0xc10f, 0x06ff, 0xc10f, 0x21, 0 + .dw 0x0740, 0xc10f, 0x077f, 0xc10f, 0x21, 0 + .dw 0x07c0, 0xc10f, 0x07ff, 0xc10f, 0x21, 0 + .dw 0x0840, 0xc10f, 0x087f, 0xc10f, 0x21, 0 + .dw 0x08c0, 0xc10f, 0x08ff, 0xc10f, 0x21, 0 + .dw 0x0940, 0xc10f, 0x097f, 0xc10f, 0x21, 0 + .dw 0x09c0, 0xc10f, 0x09ff, 0xc10f, 0x21, 0 + .dw 0x0a40, 0xc10f, 0x0a7f, 0xc10f, 0x21, 0 + .dw 0x0ac0, 0xc10f, 0x0aff, 0xc10f, 0x21, 0 + .dw 0x0b40, 0xc10f, 0x0b7f, 0xc10f, 0x21, 0 + .dw 0x0bc0, 0xc10f, 0x0bff, 0xc10f, 0x21, 0 + .dw 0x0c40, 0xc10f, 0x0c7f, 0xc10f, 0x21, 0 + .dw 0x0cc0, 0xc10f, 0x0cff, 0xc10f, 0x21, 0 + .dw 0x0d40, 0xc10f, 0x0d7f, 0xc10f, 0x21, 0 + .dw 0x0dc0, 0xc10f, 0x0dff, 0xc10f, 0x21, 0 + .dw 0x0e40, 0xc10f, 0x0e7f, 0xc10f, 0x21, 0 + .dw 0x0ec0, 0xc10f, 0x0eff, 0xc10f, 0x21, 0 + .dw 0x0f40, 0xc10f, 0x0f7f, 0xc10f, 0x21, 0 + .dw 0x0fc0, 0xc10f, 0x0fff, 0xc10f, 0x21, 0 + .dw 0x1040, 0xc10f, 0x107f, 0xc10f, 0x21, 0 + .dw 0x10c0, 0xc10f, 0x10ff, 0xc10f, 0x21, 0 + .dw 0x1140, 0xc10f, 0x117f, 0xc10f, 0x21, 0 + .dw 0x11c0, 0xc10f, 0x11ff, 0xc10f, 0x21, 0 + .dw 0x1240, 0xc10f, 0x127f, 0xc10f, 0x21, 0 + .dw 0x12c0, 0xc10f, 0x12ff, 0xc10f, 0x21, 0 + .dw 0x1340, 0xc10f, 0x137f, 0xc10f, 0x21, 0 + .dw 0x13c0, 0xc10f, 0x13ff, 0xc10f, 0x21, 0 + .dw 0x1440, 0xc10f, 0x147f, 0xc10f, 0x21, 0 + .dw 0x14c0, 0xc10f, 0x14ff, 0xc10f, 0x21, 0 + .dw 0x1540, 0xc10f, 0x157f, 0xc10f, 0x21, 0 + .dw 0x15c0, 0xc10f, 0x15ff, 0xc10f, 0x21, 0 + .dw 0x1640, 0xc10f, 0x167f, 0xc10f, 0x21, 0 + .dw 0x16c0, 0xc10f, 0x16ff, 0xc10f, 0x21, 0 + .dw 0x1740, 0xc10f, 0x177f, 0xc10f, 0x21, 0 + .dw 0x17c0, 0xc10f, 0x17ff, 0xc10f, 0x21, 0 + .dw 0x1840, 0xc10f, 0x187f, 0xc10f, 0x21, 0 + .dw 0x18c0, 0xc10f, 0x18ff, 0xc10f, 0x21, 0 + .dw 0x1940, 0xc10f, 0x197f, 0xc10f, 0x21, 0 + .dw 0x19c0, 0xc10f, 0x1fff, 0xc10f, 0x21, 0 + .dw 0x2040, 0xc10f, 0x207f, 0xc10f, 0x21, 0 + .dw 0x20c0, 0xc10f, 0x20ff, 0xc10f, 0x21, 0 + .dw 0x2140, 0xc10f, 0x217f, 0xc10f, 0x21, 0 + .dw 0x21c0, 0xc10f, 0x21ff, 0xc10f, 0x21, 0 + .dw 0x2240, 0xc10f, 0x227f, 0xc10f, 0x21, 0 + .dw 0x22c0, 0xc10f, 0x22ff, 0xc10f, 0x21, 0 + .dw 0x2340, 0xc10f, 0x237f, 0xc10f, 0x21, 0 + .dw 0x23c0, 0xc10f, 0x23ff, 0xc10f, 0x21, 0 + .dw 0x2440, 0xc10f, 0x247f, 0xc10f, 0x21, 0 + .dw 0x24c0, 0xc10f, 0x24ff, 0xc10f, 0x21, 0 + .dw 0x2540, 0xc10f, 0x257f, 0xc10f, 0x21, 0 + .dw 0x25c0, 0xc10f, 0x25ff, 0xc10f, 0x21, 0 + .dw 0x2640, 0xc10f, 0x267f, 0xc10f, 0x21, 0 + .dw 0x26c0, 0xc10f, 0x26ff, 0xc10f, 0x21, 0 + .dw 0x2740, 0xc10f, 0x277f, 0xc10f, 0x21, 0 + .dw 0x27c0, 0xc10f, 0x27ff, 0xc10f, 0x21, 0 + .dw 0x2840, 0xc10f, 0x287f, 0xc10f, 0x21, 0 + .dw 0x28c0, 0xc10f, 0x28ff, 0xc10f, 0x21, 0 + .dw 0x2940, 0xc10f, 0x297f, 0xc10f, 0x21, 0 + .dw 0x29c0, 0xc10f, 0x29ff, 0xc10f, 0x21, 0 + .dw 0x2a40, 0xc10f, 0x2a7f, 0xc10f, 0x21, 0 + .dw 0x2ac0, 0xc10f, 0x2aff, 0xc10f, 0x21, 0 + .dw 0x2b40, 0xc10f, 0x2b7f, 0xc10f, 0x21, 0 + .dw 0x2bc0, 0xc10f, 0x2bff, 0xc10f, 0x21, 0 + .dw 0x2c40, 0xc10f, 0x2c7f, 0xc10f, 0x21, 0 + .dw 0x2cc0, 0xc10f, 0x2cff, 0xc10f, 0x21, 0 + .dw 0x2d40, 0xc10f, 0x2d7f, 0xc10f, 0x21, 0 + .dw 0x2dc0, 0xc10f, 0x2dff, 0xc10f, 0x21, 0 + .dw 0x2e40, 0xc10f, 0x2e7f, 0xc10f, 0x21, 0 + .dw 0x2ec0, 0xc10f, 0x2eff, 0xc10f, 0x21, 0 + .dw 0x2f40, 0xc10f, 0x2f7f, 0xc10f, 0x21, 0 + .dw 0x2fc0, 0xc10f, 0x2fff, 0xc10f, 0x21, 0 + .dw 0x3040, 0xc10f, 0x307f, 0xc10f, 0x21, 0 + .dw 0x30c0, 0xc10f, 0x30ff, 0xc10f, 0x21, 0 + .dw 0x3140, 0xc10f, 0x317f, 0xc10f, 0x21, 0 + .dw 0x31c0, 0xc10f, 0x31ff, 0xc10f, 0x21, 0 + .dw 0x3240, 0xc10f, 0x327f, 0xc10f, 0x21, 0 + .dw 0x32c0, 0xc10f, 0x32ff, 0xc10f, 0x21, 0 + .dw 0x3340, 0xc10f, 0x337f, 0xc10f, 0x21, 0 + .dw 0x33c0, 0xc10f, 0x33ff, 0xc10f, 0x21, 0 + .dw 0x3440, 0xc10f, 0x347f, 0xc10f, 0x21, 0 + .dw 0x34c0, 0xc10f, 0x34ff, 0xc10f, 0x21, 0 + .dw 0x3540, 0xc10f, 0x357f, 0xc10f, 0x21, 0 + .dw 0x35c0, 0xc10f, 0x35ff, 0xc10f, 0x21, 0 + .dw 0x3640, 0xc10f, 0x367f, 0xc10f, 0x21, 0 + .dw 0x36c0, 0xc10f, 0x36ff, 0xc10f, 0x21, 0 + .dw 0x3740, 0xc10f, 0x377f, 0xc10f, 0x21, 0 + .dw 0x37c0, 0xc10f, 0x37ff, 0xc10f, 0x21, 0 + .dw 0x3840, 0xc10f, 0x387f, 0xc10f, 0x21, 0 + .dw 0x38c0, 0xc10f, 0x38ff, 0xc10f, 0x21, 0 + .dw 0x3940, 0xc10f, 0x397f, 0xc10f, 0x21, 0 + .dw 0x39c0, 0xc10f, 0xffff, 0xc10f, 0x21, 0 + .dw 0x1a00, 0xc110, 0x1fff, 0xc110, 0x21, 0 + .dw 0x3a00, 0xc110, 0x3fff, 0xc110, 0x21, 0 + .dw 0x5a00, 0xc110, 0x5fff, 0xc110, 0x21, 0 + .dw 0x7a00, 0xc110, 0x7fff, 0xc110, 0x21, 0 + .dw 0x9a00, 0xc110, 0x9fff, 0xc110, 0x21, 0 + .dw 0xba00, 0xc110, 0xbfff, 0xc110, 0x21, 0 + .dw 0xda00, 0xc110, 0xdfff, 0xc110, 0x21, 0 + .dw 0xfa00, 0xc110, 0xffff, 0xc110, 0x21, 0 + .dw 0x1a00, 0xc111, 0x1fff, 0xc111, 0x21, 0 + .dw 0x3a00, 0xc111, 0x3fff, 0xc111, 0x21, 0 + .dw 0x5a00, 0xc111, 0x5fff, 0xc111, 0x21, 0 + .dw 0x7a00, 0xc111, 0x7fff, 0xc111, 0x21, 0 + .dw 0x9a00, 0xc111, 0x9fff, 0xc111, 0x21, 0 + .dw 0xba00, 0xc111, 0xbfff, 0xc111, 0x21, 0 + .dw 0xda00, 0xc111, 0xdfff, 0xc111, 0x21, 0 + .dw 0xfa00, 0xc111, 0xffff, 0xc111, 0x21, 0 + .dw 0x1a00, 0xc112, 0x1fff, 0xc112, 0x21, 0 + .dw 0x3a00, 0xc112, 0x3fff, 0xc112, 0x21, 0 + .dw 0x5a00, 0xc112, 0x5fff, 0xc112, 0x21, 0 + .dw 0x7a00, 0xc112, 0x7fff, 0xc112, 0x21, 0 + .dw 0x9a00, 0xc112, 0x9fff, 0xc112, 0x21, 0 + .dw 0xba00, 0xc112, 0xbfff, 0xc112, 0x21, 0 + .dw 0xda00, 0xc112, 0xdfff, 0xc112, 0x21, 0 + .dw 0xfa00, 0xc112, 0xffff, 0xc113, 0x21, 0 + .dw 0x1a00, 0xc114, 0x1fff, 0xc114, 0x21, 0 + .dw 0x3a00, 0xc114, 0x3fff, 0xc114, 0x21, 0 + .dw 0x5a00, 0xc114, 0x5fff, 0xc114, 0x21, 0 + .dw 0x7a00, 0xc114, 0x7fff, 0xc114, 0x21, 0 + .dw 0x9a00, 0xc114, 0x9fff, 0xc114, 0x21, 0 + .dw 0xba00, 0xc114, 0xbfff, 0xc114, 0x21, 0 + .dw 0xda00, 0xc114, 0xdfff, 0xc114, 0x21, 0 + .dw 0xfa00, 0xc114, 0xffff, 0xc114, 0x21, 0 + .dw 0x1a00, 0xc115, 0x1fff, 0xc115, 0x21, 0 + .dw 0x3a00, 0xc115, 0x3fff, 0xc115, 0x21, 0 + .dw 0x5a00, 0xc115, 0x5fff, 0xc115, 0x21, 0 + .dw 0x7a00, 0xc115, 0x7fff, 0xc115, 0x21, 0 + .dw 0x9a00, 0xc115, 0x9fff, 0xc115, 0x21, 0 + .dw 0xba00, 0xc115, 0xbfff, 0xc115, 0x21, 0 + .dw 0xda00, 0xc115, 0xdfff, 0xc115, 0x21, 0 + .dw 0xfa00, 0xc115, 0xffff, 0xc115, 0x21, 0 + .dw 0x1a00, 0xc116, 0x1fff, 0xc116, 0x21, 0 + .dw 0x3a00, 0xc116, 0x3fff, 0xc116, 0x21, 0 + .dw 0x5a00, 0xc116, 0x5fff, 0xc116, 0x21, 0 + .dw 0x7a00, 0xc116, 0x7fff, 0xc116, 0x21, 0 + .dw 0x9a00, 0xc116, 0x9fff, 0xc116, 0x21, 0 + .dw 0xba00, 0xc116, 0xbfff, 0xc116, 0x21, 0 + .dw 0xda00, 0xc116, 0xdfff, 0xc116, 0x21, 0 + .dw 0xfa00, 0xc116, 0xffff, 0xc116, 0x21, 0 + .dw 0x1a00, 0xc117, 0x1fff, 0xc117, 0x21, 0 + .dw 0x3a00, 0xc117, 0x1fff, 0xc118, 0x21, 0 + .dw 0x2040, 0xc118, 0x207f, 0xc118, 0x21, 0 + .dw 0x20c0, 0xc118, 0x20ff, 0xc118, 0x21, 0 + .dw 0x2140, 0xc118, 0x217f, 0xc118, 0x21, 0 + .dw 0x21c0, 0xc118, 0x21ff, 0xc118, 0x21, 0 + .dw 0x2240, 0xc118, 0x227f, 0xc118, 0x21, 0 + .dw 0x22c0, 0xc118, 0x22ff, 0xc118, 0x21, 0 + .dw 0x2340, 0xc118, 0x237f, 0xc118, 0x21, 0 + .dw 0x23c0, 0xc118, 0x23ff, 0xc118, 0x21, 0 + .dw 0x2440, 0xc118, 0x247f, 0xc118, 0x21, 0 + .dw 0x24c0, 0xc118, 0x24ff, 0xc118, 0x21, 0 + .dw 0x2540, 0xc118, 0x257f, 0xc118, 0x21, 0 + .dw 0x25c0, 0xc118, 0x25ff, 0xc118, 0x21, 0 + .dw 0x2640, 0xc118, 0x267f, 0xc118, 0x21, 0 + .dw 0x26c0, 0xc118, 0x26ff, 0xc118, 0x21, 0 + .dw 0x2740, 0xc118, 0x277f, 0xc118, 0x21, 0 + .dw 0x27c0, 0xc118, 0x27ff, 0xc118, 0x21, 0 + .dw 0x2840, 0xc118, 0x287f, 0xc118, 0x21, 0 + .dw 0x28c0, 0xc118, 0x28ff, 0xc118, 0x21, 0 + .dw 0x2940, 0xc118, 0x297f, 0xc118, 0x21, 0 + .dw 0x29c0, 0xc118, 0x29ff, 0xc118, 0x21, 0 + .dw 0x2a40, 0xc118, 0x2a7f, 0xc118, 0x21, 0 + .dw 0x2ac0, 0xc118, 0x2aff, 0xc118, 0x21, 0 + .dw 0x2b40, 0xc118, 0x2b7f, 0xc118, 0x21, 0 + .dw 0x2bc0, 0xc118, 0x2bff, 0xc118, 0x21, 0 + .dw 0x2c40, 0xc118, 0x2c7f, 0xc118, 0x21, 0 + .dw 0x2cc0, 0xc118, 0x2cff, 0xc118, 0x21, 0 + .dw 0x2d40, 0xc118, 0x2d7f, 0xc118, 0x21, 0 + .dw 0x2dc0, 0xc118, 0x2dff, 0xc118, 0x21, 0 + .dw 0x2e40, 0xc118, 0x2e7f, 0xc118, 0x21, 0 + .dw 0x2ec0, 0xc118, 0x2eff, 0xc118, 0x21, 0 + .dw 0x2f40, 0xc118, 0x2f7f, 0xc118, 0x21, 0 + .dw 0x2fc0, 0xc118, 0x2fff, 0xc118, 0x21, 0 + .dw 0x3040, 0xc118, 0x307f, 0xc118, 0x21, 0 + .dw 0x30c0, 0xc118, 0x30ff, 0xc118, 0x21, 0 + .dw 0x3140, 0xc118, 0x317f, 0xc118, 0x21, 0 + .dw 0x31c0, 0xc118, 0x31ff, 0xc118, 0x21, 0 + .dw 0x3240, 0xc118, 0x327f, 0xc118, 0x21, 0 + .dw 0x32c0, 0xc118, 0x32ff, 0xc118, 0x21, 0 + .dw 0x3340, 0xc118, 0x337f, 0xc118, 0x21, 0 + .dw 0x33c0, 0xc118, 0x33ff, 0xc118, 0x21, 0 + .dw 0x3440, 0xc118, 0x347f, 0xc118, 0x21, 0 + .dw 0x34c0, 0xc118, 0x34ff, 0xc118, 0x21, 0 + .dw 0x3540, 0xc118, 0x357f, 0xc118, 0x21, 0 + .dw 0x35c0, 0xc118, 0x35ff, 0xc118, 0x21, 0 + .dw 0x3640, 0xc118, 0x367f, 0xc118, 0x21, 0 + .dw 0x36c0, 0xc118, 0x36ff, 0xc118, 0x21, 0 + .dw 0x3740, 0xc118, 0x377f, 0xc118, 0x21, 0 + .dw 0x37c0, 0xc118, 0x37ff, 0xc118, 0x21, 0 + .dw 0x3840, 0xc118, 0x387f, 0xc118, 0x21, 0 + .dw 0x38c0, 0xc118, 0x38ff, 0xc118, 0x21, 0 + .dw 0x3940, 0xc118, 0x397f, 0xc118, 0x21, 0 + .dw 0x39c0, 0xc118, 0x5fff, 0xc118, 0x21, 0 + .dw 0x6040, 0xc118, 0x607f, 0xc118, 0x21, 0 + .dw 0x60c0, 0xc118, 0x60ff, 0xc118, 0x21, 0 + .dw 0x6140, 0xc118, 0x617f, 0xc118, 0x21, 0 + .dw 0x61c0, 0xc118, 0x61ff, 0xc118, 0x21, 0 + .dw 0x6240, 0xc118, 0x627f, 0xc118, 0x21, 0 + .dw 0x62c0, 0xc118, 0x62ff, 0xc118, 0x21, 0 + .dw 0x6340, 0xc118, 0x637f, 0xc118, 0x21, 0 + .dw 0x63c0, 0xc118, 0x63ff, 0xc118, 0x21, 0 + .dw 0x6440, 0xc118, 0x647f, 0xc118, 0x21, 0 + .dw 0x64c0, 0xc118, 0x64ff, 0xc118, 0x21, 0 + .dw 0x6540, 0xc118, 0x657f, 0xc118, 0x21, 0 + .dw 0x65c0, 0xc118, 0x65ff, 0xc118, 0x21, 0 + .dw 0x6640, 0xc118, 0x667f, 0xc118, 0x21, 0 + .dw 0x66c0, 0xc118, 0x66ff, 0xc118, 0x21, 0 + .dw 0x6740, 0xc118, 0x677f, 0xc118, 0x21, 0 + .dw 0x67c0, 0xc118, 0x67ff, 0xc118, 0x21, 0 + .dw 0x6840, 0xc118, 0x687f, 0xc118, 0x21, 0 + .dw 0x68c0, 0xc118, 0x68ff, 0xc118, 0x21, 0 + .dw 0x6940, 0xc118, 0x697f, 0xc118, 0x21, 0 + .dw 0x69c0, 0xc118, 0x69ff, 0xc118, 0x21, 0 + .dw 0x6a40, 0xc118, 0x6a7f, 0xc118, 0x21, 0 + .dw 0x6ac0, 0xc118, 0x6aff, 0xc118, 0x21, 0 + .dw 0x6b40, 0xc118, 0x6b7f, 0xc118, 0x21, 0 + .dw 0x6bc0, 0xc118, 0x6bff, 0xc118, 0x21, 0 + .dw 0x6c40, 0xc118, 0x6c7f, 0xc118, 0x21, 0 + .dw 0x6cc0, 0xc118, 0x6cff, 0xc118, 0x21, 0 + .dw 0x6d40, 0xc118, 0x6d7f, 0xc118, 0x21, 0 + .dw 0x6dc0, 0xc118, 0x6dff, 0xc118, 0x21, 0 + .dw 0x6e40, 0xc118, 0x6e7f, 0xc118, 0x21, 0 + .dw 0x6ec0, 0xc118, 0x6eff, 0xc118, 0x21, 0 + .dw 0x6f40, 0xc118, 0x6f7f, 0xc118, 0x21, 0 + .dw 0x6fc0, 0xc118, 0x6fff, 0xc118, 0x21, 0 + .dw 0x7040, 0xc118, 0x707f, 0xc118, 0x21, 0 + .dw 0x70c0, 0xc118, 0x70ff, 0xc118, 0x21, 0 + .dw 0x7140, 0xc118, 0x717f, 0xc118, 0x21, 0 + .dw 0x71c0, 0xc118, 0x71ff, 0xc118, 0x21, 0 + .dw 0x7240, 0xc118, 0x727f, 0xc118, 0x21, 0 + .dw 0x72c0, 0xc118, 0x72ff, 0xc118, 0x21, 0 + .dw 0x7340, 0xc118, 0x737f, 0xc118, 0x21, 0 + .dw 0x73c0, 0xc118, 0x73ff, 0xc118, 0x21, 0 + .dw 0x7440, 0xc118, 0x747f, 0xc118, 0x21, 0 + .dw 0x74c0, 0xc118, 0x74ff, 0xc118, 0x21, 0 + .dw 0x7540, 0xc118, 0x757f, 0xc118, 0x21, 0 + .dw 0x75c0, 0xc118, 0x75ff, 0xc118, 0x21, 0 + .dw 0x7640, 0xc118, 0x767f, 0xc118, 0x21, 0 + .dw 0x76c0, 0xc118, 0x76ff, 0xc118, 0x21, 0 + .dw 0x7740, 0xc118, 0x777f, 0xc118, 0x21, 0 + .dw 0x77c0, 0xc118, 0x77ff, 0xc118, 0x21, 0 + .dw 0x7840, 0xc118, 0x787f, 0xc118, 0x21, 0 + .dw 0x78c0, 0xc118, 0x78ff, 0xc118, 0x21, 0 + .dw 0x7940, 0xc118, 0x797f, 0xc118, 0x21, 0 + .dw 0x79c0, 0xc118, 0x9fff, 0xc118, 0x21, 0 + .dw 0xa040, 0xc118, 0xa07f, 0xc118, 0x21, 0 + .dw 0xa0c0, 0xc118, 0xa0ff, 0xc118, 0x21, 0 + .dw 0xa140, 0xc118, 0xa17f, 0xc118, 0x21, 0 + .dw 0xa1c0, 0xc118, 0xa1ff, 0xc118, 0x21, 0 + .dw 0xa240, 0xc118, 0xa27f, 0xc118, 0x21, 0 + .dw 0xa2c0, 0xc118, 0xa2ff, 0xc118, 0x21, 0 + .dw 0xa340, 0xc118, 0xa37f, 0xc118, 0x21, 0 + .dw 0xa3c0, 0xc118, 0xa3ff, 0xc118, 0x21, 0 + .dw 0xa440, 0xc118, 0xa47f, 0xc118, 0x21, 0 + .dw 0xa4c0, 0xc118, 0xa4ff, 0xc118, 0x21, 0 + .dw 0xa540, 0xc118, 0xa57f, 0xc118, 0x21, 0 + .dw 0xa5c0, 0xc118, 0xa5ff, 0xc118, 0x21, 0 + .dw 0xa640, 0xc118, 0xa67f, 0xc118, 0x21, 0 + .dw 0xa6c0, 0xc118, 0xa6ff, 0xc118, 0x21, 0 + .dw 0xa740, 0xc118, 0xa77f, 0xc118, 0x21, 0 + .dw 0xa7c0, 0xc118, 0xa7ff, 0xc118, 0x21, 0 + .dw 0xa840, 0xc118, 0xa87f, 0xc118, 0x21, 0 + .dw 0xa8c0, 0xc118, 0xa8ff, 0xc118, 0x21, 0 + .dw 0xa940, 0xc118, 0xa97f, 0xc118, 0x21, 0 + .dw 0xa9c0, 0xc118, 0xa9ff, 0xc118, 0x21, 0 + .dw 0xaa40, 0xc118, 0xaa7f, 0xc118, 0x21, 0 + .dw 0xaac0, 0xc118, 0xaaff, 0xc118, 0x21, 0 + .dw 0xab40, 0xc118, 0xab7f, 0xc118, 0x21, 0 + .dw 0xabc0, 0xc118, 0xabff, 0xc118, 0x21, 0 + .dw 0xac40, 0xc118, 0xac7f, 0xc118, 0x21, 0 + .dw 0xacc0, 0xc118, 0xacff, 0xc118, 0x21, 0 + .dw 0xad40, 0xc118, 0xad7f, 0xc118, 0x21, 0 + .dw 0xadc0, 0xc118, 0xadff, 0xc118, 0x21, 0 + .dw 0xae40, 0xc118, 0xae7f, 0xc118, 0x21, 0 + .dw 0xaec0, 0xc118, 0xaeff, 0xc118, 0x21, 0 + .dw 0xaf40, 0xc118, 0xaf7f, 0xc118, 0x21, 0 + .dw 0xafc0, 0xc118, 0xafff, 0xc118, 0x21, 0 + .dw 0xb040, 0xc118, 0xb07f, 0xc118, 0x21, 0 + .dw 0xb0c0, 0xc118, 0xb0ff, 0xc118, 0x21, 0 + .dw 0xb140, 0xc118, 0xb17f, 0xc118, 0x21, 0 + .dw 0xb1c0, 0xc118, 0xb1ff, 0xc118, 0x21, 0 + .dw 0xb240, 0xc118, 0xb27f, 0xc118, 0x21, 0 + .dw 0xb2c0, 0xc118, 0xb2ff, 0xc118, 0x21, 0 + .dw 0xb340, 0xc118, 0xb37f, 0xc118, 0x21, 0 + .dw 0xb3c0, 0xc118, 0xb3ff, 0xc118, 0x21, 0 + .dw 0xb440, 0xc118, 0xb47f, 0xc118, 0x21, 0 + .dw 0xb4c0, 0xc118, 0xb4ff, 0xc118, 0x21, 0 + .dw 0xb540, 0xc118, 0xb57f, 0xc118, 0x21, 0 + .dw 0xb5c0, 0xc118, 0xb5ff, 0xc118, 0x21, 0 + .dw 0xb640, 0xc118, 0xb67f, 0xc118, 0x21, 0 + .dw 0xb6c0, 0xc118, 0xb6ff, 0xc118, 0x21, 0 + .dw 0xb740, 0xc118, 0xb77f, 0xc118, 0x21, 0 + .dw 0xb7c0, 0xc118, 0xb7ff, 0xc118, 0x21, 0 + .dw 0xb840, 0xc118, 0xb87f, 0xc118, 0x21, 0 + .dw 0xb8c0, 0xc118, 0xb8ff, 0xc118, 0x21, 0 + .dw 0xb940, 0xc118, 0xb97f, 0xc118, 0x21, 0 + .dw 0xb9c0, 0xc118, 0xdfff, 0xc118, 0x21, 0 + .dw 0xe040, 0xc118, 0xe07f, 0xc118, 0x21, 0 + .dw 0xe0c0, 0xc118, 0xe0ff, 0xc118, 0x21, 0 + .dw 0xe140, 0xc118, 0xe17f, 0xc118, 0x21, 0 + .dw 0xe1c0, 0xc118, 0xe1ff, 0xc118, 0x21, 0 + .dw 0xe240, 0xc118, 0xe27f, 0xc118, 0x21, 0 + .dw 0xe2c0, 0xc118, 0xe2ff, 0xc118, 0x21, 0 + .dw 0xe340, 0xc118, 0xe37f, 0xc118, 0x21, 0 + .dw 0xe3c0, 0xc118, 0xe3ff, 0xc118, 0x21, 0 + .dw 0xe440, 0xc118, 0xe47f, 0xc118, 0x21, 0 + .dw 0xe4c0, 0xc118, 0xe4ff, 0xc118, 0x21, 0 + .dw 0xe540, 0xc118, 0xe57f, 0xc118, 0x21, 0 + .dw 0xe5c0, 0xc118, 0xe5ff, 0xc118, 0x21, 0 + .dw 0xe640, 0xc118, 0xe67f, 0xc118, 0x21, 0 + .dw 0xe6c0, 0xc118, 0xe6ff, 0xc118, 0x21, 0 + .dw 0xe740, 0xc118, 0xe77f, 0xc118, 0x21, 0 + .dw 0xe7c0, 0xc118, 0xe7ff, 0xc118, 0x21, 0 + .dw 0xe840, 0xc118, 0xe87f, 0xc118, 0x21, 0 + .dw 0xe8c0, 0xc118, 0xe8ff, 0xc118, 0x21, 0 + .dw 0xe940, 0xc118, 0xe97f, 0xc118, 0x21, 0 + .dw 0xe9c0, 0xc118, 0xe9ff, 0xc118, 0x21, 0 + .dw 0xea40, 0xc118, 0xea7f, 0xc118, 0x21, 0 + .dw 0xeac0, 0xc118, 0xeaff, 0xc118, 0x21, 0 + .dw 0xeb40, 0xc118, 0xeb7f, 0xc118, 0x21, 0 + .dw 0xebc0, 0xc118, 0xebff, 0xc118, 0x21, 0 + .dw 0xec40, 0xc118, 0xec7f, 0xc118, 0x21, 0 + .dw 0xecc0, 0xc118, 0xecff, 0xc118, 0x21, 0 + .dw 0xed40, 0xc118, 0xed7f, 0xc118, 0x21, 0 + .dw 0xedc0, 0xc118, 0xedff, 0xc118, 0x21, 0 + .dw 0xee40, 0xc118, 0xee7f, 0xc118, 0x21, 0 + .dw 0xeec0, 0xc118, 0xeeff, 0xc118, 0x21, 0 + .dw 0xef40, 0xc118, 0xef7f, 0xc118, 0x21, 0 + .dw 0xefc0, 0xc118, 0xefff, 0xc118, 0x21, 0 + .dw 0xf040, 0xc118, 0xf07f, 0xc118, 0x21, 0 + .dw 0xf0c0, 0xc118, 0xf0ff, 0xc118, 0x21, 0 + .dw 0xf140, 0xc118, 0xf17f, 0xc118, 0x21, 0 + .dw 0xf1c0, 0xc118, 0xf1ff, 0xc118, 0x21, 0 + .dw 0xf240, 0xc118, 0xf27f, 0xc118, 0x21, 0 + .dw 0xf2c0, 0xc118, 0xf2ff, 0xc118, 0x21, 0 + .dw 0xf340, 0xc118, 0xf37f, 0xc118, 0x21, 0 + .dw 0xf3c0, 0xc118, 0xf3ff, 0xc118, 0x21, 0 + .dw 0xf440, 0xc118, 0xf47f, 0xc118, 0x21, 0 + .dw 0xf4c0, 0xc118, 0xf4ff, 0xc118, 0x21, 0 + .dw 0xf540, 0xc118, 0xf57f, 0xc118, 0x21, 0 + .dw 0xf5c0, 0xc118, 0xf5ff, 0xc118, 0x21, 0 + .dw 0xf640, 0xc118, 0xf67f, 0xc118, 0x21, 0 + .dw 0xf6c0, 0xc118, 0xf6ff, 0xc118, 0x21, 0 + .dw 0xf740, 0xc118, 0xf77f, 0xc118, 0x21, 0 + .dw 0xf7c0, 0xc118, 0xf7ff, 0xc118, 0x21, 0 + .dw 0xf840, 0xc118, 0xf87f, 0xc118, 0x21, 0 + .dw 0xf8c0, 0xc118, 0xf8ff, 0xc118, 0x21, 0 + .dw 0xf940, 0xc118, 0xf97f, 0xc118, 0x21, 0 + .dw 0xf9c0, 0xc118, 0x1fff, 0xc119, 0x21, 0 + .dw 0x2040, 0xc119, 0x207f, 0xc119, 0x21, 0 + .dw 0x20c0, 0xc119, 0x20ff, 0xc119, 0x21, 0 + .dw 0x2140, 0xc119, 0x217f, 0xc119, 0x21, 0 + .dw 0x21c0, 0xc119, 0x21ff, 0xc119, 0x21, 0 + .dw 0x2240, 0xc119, 0x227f, 0xc119, 0x21, 0 + .dw 0x22c0, 0xc119, 0x22ff, 0xc119, 0x21, 0 + .dw 0x2340, 0xc119, 0x237f, 0xc119, 0x21, 0 + .dw 0x23c0, 0xc119, 0x23ff, 0xc119, 0x21, 0 + .dw 0x2440, 0xc119, 0x247f, 0xc119, 0x21, 0 + .dw 0x24c0, 0xc119, 0x24ff, 0xc119, 0x21, 0 + .dw 0x2540, 0xc119, 0x257f, 0xc119, 0x21, 0 + .dw 0x25c0, 0xc119, 0x25ff, 0xc119, 0x21, 0 + .dw 0x2640, 0xc119, 0x267f, 0xc119, 0x21, 0 + .dw 0x26c0, 0xc119, 0x26ff, 0xc119, 0x21, 0 + .dw 0x2740, 0xc119, 0x277f, 0xc119, 0x21, 0 + .dw 0x27c0, 0xc119, 0x27ff, 0xc119, 0x21, 0 + .dw 0x2840, 0xc119, 0x287f, 0xc119, 0x21, 0 + .dw 0x28c0, 0xc119, 0x28ff, 0xc119, 0x21, 0 + .dw 0x2940, 0xc119, 0x297f, 0xc119, 0x21, 0 + .dw 0x29c0, 0xc119, 0x29ff, 0xc119, 0x21, 0 + .dw 0x2a40, 0xc119, 0x2a7f, 0xc119, 0x21, 0 + .dw 0x2ac0, 0xc119, 0x2aff, 0xc119, 0x21, 0 + .dw 0x2b40, 0xc119, 0x2b7f, 0xc119, 0x21, 0 + .dw 0x2bc0, 0xc119, 0x2bff, 0xc119, 0x21, 0 + .dw 0x2c40, 0xc119, 0x2c7f, 0xc119, 0x21, 0 + .dw 0x2cc0, 0xc119, 0x2cff, 0xc119, 0x21, 0 + .dw 0x2d40, 0xc119, 0x2d7f, 0xc119, 0x21, 0 + .dw 0x2dc0, 0xc119, 0x2dff, 0xc119, 0x21, 0 + .dw 0x2e40, 0xc119, 0x2e7f, 0xc119, 0x21, 0 + .dw 0x2ec0, 0xc119, 0x2eff, 0xc119, 0x21, 0 + .dw 0x2f40, 0xc119, 0x2f7f, 0xc119, 0x21, 0 + .dw 0x2fc0, 0xc119, 0x2fff, 0xc119, 0x21, 0 + .dw 0x3040, 0xc119, 0x307f, 0xc119, 0x21, 0 + .dw 0x30c0, 0xc119, 0x30ff, 0xc119, 0x21, 0 + .dw 0x3140, 0xc119, 0x317f, 0xc119, 0x21, 0 + .dw 0x31c0, 0xc119, 0x31ff, 0xc119, 0x21, 0 + .dw 0x3240, 0xc119, 0x327f, 0xc119, 0x21, 0 + .dw 0x32c0, 0xc119, 0x32ff, 0xc119, 0x21, 0 + .dw 0x3340, 0xc119, 0x337f, 0xc119, 0x21, 0 + .dw 0x33c0, 0xc119, 0x33ff, 0xc119, 0x21, 0 + .dw 0x3440, 0xc119, 0x347f, 0xc119, 0x21, 0 + .dw 0x34c0, 0xc119, 0x34ff, 0xc119, 0x21, 0 + .dw 0x3540, 0xc119, 0x357f, 0xc119, 0x21, 0 + .dw 0x35c0, 0xc119, 0x35ff, 0xc119, 0x21, 0 + .dw 0x3640, 0xc119, 0x367f, 0xc119, 0x21, 0 + .dw 0x36c0, 0xc119, 0x36ff, 0xc119, 0x21, 0 + .dw 0x3740, 0xc119, 0x377f, 0xc119, 0x21, 0 + .dw 0x37c0, 0xc119, 0x37ff, 0xc119, 0x21, 0 + .dw 0x3840, 0xc119, 0x387f, 0xc119, 0x21, 0 + .dw 0x38c0, 0xc119, 0x38ff, 0xc119, 0x21, 0 + .dw 0x3940, 0xc119, 0x397f, 0xc119, 0x21, 0 + .dw 0x39c0, 0xc119, 0x5fff, 0xc119, 0x21, 0 + .dw 0x6040, 0xc119, 0x607f, 0xc119, 0x21, 0 + .dw 0x60c0, 0xc119, 0x60ff, 0xc119, 0x21, 0 + .dw 0x6140, 0xc119, 0x617f, 0xc119, 0x21, 0 + .dw 0x61c0, 0xc119, 0x61ff, 0xc119, 0x21, 0 + .dw 0x6240, 0xc119, 0x627f, 0xc119, 0x21, 0 + .dw 0x62c0, 0xc119, 0x62ff, 0xc119, 0x21, 0 + .dw 0x6340, 0xc119, 0x637f, 0xc119, 0x21, 0 + .dw 0x63c0, 0xc119, 0x63ff, 0xc119, 0x21, 0 + .dw 0x6440, 0xc119, 0x647f, 0xc119, 0x21, 0 + .dw 0x64c0, 0xc119, 0x64ff, 0xc119, 0x21, 0 + .dw 0x6540, 0xc119, 0x657f, 0xc119, 0x21, 0 + .dw 0x65c0, 0xc119, 0x65ff, 0xc119, 0x21, 0 + .dw 0x6640, 0xc119, 0x667f, 0xc119, 0x21, 0 + .dw 0x66c0, 0xc119, 0x66ff, 0xc119, 0x21, 0 + .dw 0x6740, 0xc119, 0x677f, 0xc119, 0x21, 0 + .dw 0x67c0, 0xc119, 0x67ff, 0xc119, 0x21, 0 + .dw 0x6840, 0xc119, 0x687f, 0xc119, 0x21, 0 + .dw 0x68c0, 0xc119, 0x68ff, 0xc119, 0x21, 0 + .dw 0x6940, 0xc119, 0x697f, 0xc119, 0x21, 0 + .dw 0x69c0, 0xc119, 0x69ff, 0xc119, 0x21, 0 + .dw 0x6a40, 0xc119, 0x6a7f, 0xc119, 0x21, 0 + .dw 0x6ac0, 0xc119, 0x6aff, 0xc119, 0x21, 0 + .dw 0x6b40, 0xc119, 0x6b7f, 0xc119, 0x21, 0 + .dw 0x6bc0, 0xc119, 0x6bff, 0xc119, 0x21, 0 + .dw 0x6c40, 0xc119, 0x6c7f, 0xc119, 0x21, 0 + .dw 0x6cc0, 0xc119, 0x6cff, 0xc119, 0x21, 0 + .dw 0x6d40, 0xc119, 0x6d7f, 0xc119, 0x21, 0 + .dw 0x6dc0, 0xc119, 0x6dff, 0xc119, 0x21, 0 + .dw 0x6e40, 0xc119, 0x6e7f, 0xc119, 0x21, 0 + .dw 0x6ec0, 0xc119, 0x6eff, 0xc119, 0x21, 0 + .dw 0x6f40, 0xc119, 0x6f7f, 0xc119, 0x21, 0 + .dw 0x6fc0, 0xc119, 0x6fff, 0xc119, 0x21, 0 + .dw 0x7040, 0xc119, 0x707f, 0xc119, 0x21, 0 + .dw 0x70c0, 0xc119, 0x70ff, 0xc119, 0x21, 0 + .dw 0x7140, 0xc119, 0x717f, 0xc119, 0x21, 0 + .dw 0x71c0, 0xc119, 0x71ff, 0xc119, 0x21, 0 + .dw 0x7240, 0xc119, 0x727f, 0xc119, 0x21, 0 + .dw 0x72c0, 0xc119, 0x72ff, 0xc119, 0x21, 0 + .dw 0x7340, 0xc119, 0x737f, 0xc119, 0x21, 0 + .dw 0x73c0, 0xc119, 0x73ff, 0xc119, 0x21, 0 + .dw 0x7440, 0xc119, 0x747f, 0xc119, 0x21, 0 + .dw 0x74c0, 0xc119, 0x74ff, 0xc119, 0x21, 0 + .dw 0x7540, 0xc119, 0x757f, 0xc119, 0x21, 0 + .dw 0x75c0, 0xc119, 0x75ff, 0xc119, 0x21, 0 + .dw 0x7640, 0xc119, 0x767f, 0xc119, 0x21, 0 + .dw 0x76c0, 0xc119, 0x76ff, 0xc119, 0x21, 0 + .dw 0x7740, 0xc119, 0x777f, 0xc119, 0x21, 0 + .dw 0x77c0, 0xc119, 0x77ff, 0xc119, 0x21, 0 + .dw 0x7840, 0xc119, 0x787f, 0xc119, 0x21, 0 + .dw 0x78c0, 0xc119, 0x78ff, 0xc119, 0x21, 0 + .dw 0x7940, 0xc119, 0x797f, 0xc119, 0x21, 0 + .dw 0x79c0, 0xc119, 0x9fff, 0xc119, 0x21, 0 + .dw 0xa040, 0xc119, 0xa07f, 0xc119, 0x21, 0 + .dw 0xa0c0, 0xc119, 0xa0ff, 0xc119, 0x21, 0 + .dw 0xa140, 0xc119, 0xa17f, 0xc119, 0x21, 0 + .dw 0xa1c0, 0xc119, 0xa1ff, 0xc119, 0x21, 0 + .dw 0xa240, 0xc119, 0xa27f, 0xc119, 0x21, 0 + .dw 0xa2c0, 0xc119, 0xa2ff, 0xc119, 0x21, 0 + .dw 0xa340, 0xc119, 0xa37f, 0xc119, 0x21, 0 + .dw 0xa3c0, 0xc119, 0xa3ff, 0xc119, 0x21, 0 + .dw 0xa440, 0xc119, 0xa47f, 0xc119, 0x21, 0 + .dw 0xa4c0, 0xc119, 0xa4ff, 0xc119, 0x21, 0 + .dw 0xa540, 0xc119, 0xa57f, 0xc119, 0x21, 0 + .dw 0xa5c0, 0xc119, 0xa5ff, 0xc119, 0x21, 0 + .dw 0xa640, 0xc119, 0xa67f, 0xc119, 0x21, 0 + .dw 0xa6c0, 0xc119, 0xa6ff, 0xc119, 0x21, 0 + .dw 0xa740, 0xc119, 0xa77f, 0xc119, 0x21, 0 + .dw 0xa7c0, 0xc119, 0xa7ff, 0xc119, 0x21, 0 + .dw 0xa840, 0xc119, 0xa87f, 0xc119, 0x21, 0 + .dw 0xa8c0, 0xc119, 0xa8ff, 0xc119, 0x21, 0 + .dw 0xa940, 0xc119, 0xa97f, 0xc119, 0x21, 0 + .dw 0xa9c0, 0xc119, 0xa9ff, 0xc119, 0x21, 0 + .dw 0xaa40, 0xc119, 0xaa7f, 0xc119, 0x21, 0 + .dw 0xaac0, 0xc119, 0xaaff, 0xc119, 0x21, 0 + .dw 0xab40, 0xc119, 0xab7f, 0xc119, 0x21, 0 + .dw 0xabc0, 0xc119, 0xabff, 0xc119, 0x21, 0 + .dw 0xac40, 0xc119, 0xac7f, 0xc119, 0x21, 0 + .dw 0xacc0, 0xc119, 0xacff, 0xc119, 0x21, 0 + .dw 0xad40, 0xc119, 0xad7f, 0xc119, 0x21, 0 + .dw 0xadc0, 0xc119, 0xadff, 0xc119, 0x21, 0 + .dw 0xae40, 0xc119, 0xae7f, 0xc119, 0x21, 0 + .dw 0xaec0, 0xc119, 0xaeff, 0xc119, 0x21, 0 + .dw 0xaf40, 0xc119, 0xaf7f, 0xc119, 0x21, 0 + .dw 0xafc0, 0xc119, 0xafff, 0xc119, 0x21, 0 + .dw 0xb040, 0xc119, 0xb07f, 0xc119, 0x21, 0 + .dw 0xb0c0, 0xc119, 0xb0ff, 0xc119, 0x21, 0 + .dw 0xb140, 0xc119, 0xb17f, 0xc119, 0x21, 0 + .dw 0xb1c0, 0xc119, 0xb1ff, 0xc119, 0x21, 0 + .dw 0xb240, 0xc119, 0xb27f, 0xc119, 0x21, 0 + .dw 0xb2c0, 0xc119, 0xb2ff, 0xc119, 0x21, 0 + .dw 0xb340, 0xc119, 0xb37f, 0xc119, 0x21, 0 + .dw 0xb3c0, 0xc119, 0xb3ff, 0xc119, 0x21, 0 + .dw 0xb440, 0xc119, 0xb47f, 0xc119, 0x21, 0 + .dw 0xb4c0, 0xc119, 0xb4ff, 0xc119, 0x21, 0 + .dw 0xb540, 0xc119, 0xb57f, 0xc119, 0x21, 0 + .dw 0xb5c0, 0xc119, 0xb5ff, 0xc119, 0x21, 0 + .dw 0xb640, 0xc119, 0xb67f, 0xc119, 0x21, 0 + .dw 0xb6c0, 0xc119, 0xb6ff, 0xc119, 0x21, 0 + .dw 0xb740, 0xc119, 0xb77f, 0xc119, 0x21, 0 + .dw 0xb7c0, 0xc119, 0xb7ff, 0xc119, 0x21, 0 + .dw 0xb840, 0xc119, 0xb87f, 0xc119, 0x21, 0 + .dw 0xb8c0, 0xc119, 0xb8ff, 0xc119, 0x21, 0 + .dw 0xb940, 0xc119, 0xb97f, 0xc119, 0x21, 0 + .dw 0xb9c0, 0xc119, 0xdfff, 0xc119, 0x21, 0 + .dw 0xe040, 0xc119, 0xe07f, 0xc119, 0x21, 0 + .dw 0xe0c0, 0xc119, 0xe0ff, 0xc119, 0x21, 0 + .dw 0xe140, 0xc119, 0xe17f, 0xc119, 0x21, 0 + .dw 0xe1c0, 0xc119, 0xe1ff, 0xc119, 0x21, 0 + .dw 0xe240, 0xc119, 0xe27f, 0xc119, 0x21, 0 + .dw 0xe2c0, 0xc119, 0xe2ff, 0xc119, 0x21, 0 + .dw 0xe340, 0xc119, 0xe37f, 0xc119, 0x21, 0 + .dw 0xe3c0, 0xc119, 0xe3ff, 0xc119, 0x21, 0 + .dw 0xe440, 0xc119, 0xe47f, 0xc119, 0x21, 0 + .dw 0xe4c0, 0xc119, 0xe4ff, 0xc119, 0x21, 0 + .dw 0xe540, 0xc119, 0xe57f, 0xc119, 0x21, 0 + .dw 0xe5c0, 0xc119, 0xe5ff, 0xc119, 0x21, 0 + .dw 0xe640, 0xc119, 0xe67f, 0xc119, 0x21, 0 + .dw 0xe6c0, 0xc119, 0xe6ff, 0xc119, 0x21, 0 + .dw 0xe740, 0xc119, 0xe77f, 0xc119, 0x21, 0 + .dw 0xe7c0, 0xc119, 0xe7ff, 0xc119, 0x21, 0 + .dw 0xe840, 0xc119, 0xe87f, 0xc119, 0x21, 0 + .dw 0xe8c0, 0xc119, 0xe8ff, 0xc119, 0x21, 0 + .dw 0xe940, 0xc119, 0xe97f, 0xc119, 0x21, 0 + .dw 0xe9c0, 0xc119, 0xe9ff, 0xc119, 0x21, 0 + .dw 0xea40, 0xc119, 0xea7f, 0xc119, 0x21, 0 + .dw 0xeac0, 0xc119, 0xeaff, 0xc119, 0x21, 0 + .dw 0xeb40, 0xc119, 0xeb7f, 0xc119, 0x21, 0 + .dw 0xebc0, 0xc119, 0xebff, 0xc119, 0x21, 0 + .dw 0xec40, 0xc119, 0xec7f, 0xc119, 0x21, 0 + .dw 0xecc0, 0xc119, 0xecff, 0xc119, 0x21, 0 + .dw 0xed40, 0xc119, 0xed7f, 0xc119, 0x21, 0 + .dw 0xedc0, 0xc119, 0xedff, 0xc119, 0x21, 0 + .dw 0xee40, 0xc119, 0xee7f, 0xc119, 0x21, 0 + .dw 0xeec0, 0xc119, 0xeeff, 0xc119, 0x21, 0 + .dw 0xef40, 0xc119, 0xef7f, 0xc119, 0x21, 0 + .dw 0xefc0, 0xc119, 0xefff, 0xc119, 0x21, 0 + .dw 0xf040, 0xc119, 0xf07f, 0xc119, 0x21, 0 + .dw 0xf0c0, 0xc119, 0xf0ff, 0xc119, 0x21, 0 + .dw 0xf140, 0xc119, 0xf17f, 0xc119, 0x21, 0 + .dw 0xf1c0, 0xc119, 0xf1ff, 0xc119, 0x21, 0 + .dw 0xf240, 0xc119, 0xf27f, 0xc119, 0x21, 0 + .dw 0xf2c0, 0xc119, 0xf2ff, 0xc119, 0x21, 0 + .dw 0xf340, 0xc119, 0xf37f, 0xc119, 0x21, 0 + .dw 0xf3c0, 0xc119, 0xf3ff, 0xc119, 0x21, 0 + .dw 0xf440, 0xc119, 0xf47f, 0xc119, 0x21, 0 + .dw 0xf4c0, 0xc119, 0xf4ff, 0xc119, 0x21, 0 + .dw 0xf540, 0xc119, 0xf57f, 0xc119, 0x21, 0 + .dw 0xf5c0, 0xc119, 0xf5ff, 0xc119, 0x21, 0 + .dw 0xf640, 0xc119, 0xf67f, 0xc119, 0x21, 0 + .dw 0xf6c0, 0xc119, 0xf6ff, 0xc119, 0x21, 0 + .dw 0xf740, 0xc119, 0xf77f, 0xc119, 0x21, 0 + .dw 0xf7c0, 0xc119, 0xf7ff, 0xc119, 0x21, 0 + .dw 0xf840, 0xc119, 0xf87f, 0xc119, 0x21, 0 + .dw 0xf8c0, 0xc119, 0xf8ff, 0xc119, 0x21, 0 + .dw 0xf940, 0xc119, 0xf97f, 0xc119, 0x21, 0 + .dw 0xf9c0, 0xc119, 0x1fff, 0xc11a, 0x21, 0 + .dw 0x2040, 0xc11a, 0x207f, 0xc11a, 0x21, 0 + .dw 0x20c0, 0xc11a, 0x20ff, 0xc11a, 0x21, 0 + .dw 0x2140, 0xc11a, 0x217f, 0xc11a, 0x21, 0 + .dw 0x21c0, 0xc11a, 0x21ff, 0xc11a, 0x21, 0 + .dw 0x2240, 0xc11a, 0x227f, 0xc11a, 0x21, 0 + .dw 0x22c0, 0xc11a, 0x22ff, 0xc11a, 0x21, 0 + .dw 0x2340, 0xc11a, 0x237f, 0xc11a, 0x21, 0 + .dw 0x23c0, 0xc11a, 0x23ff, 0xc11a, 0x21, 0 + .dw 0x2440, 0xc11a, 0x247f, 0xc11a, 0x21, 0 + .dw 0x24c0, 0xc11a, 0x24ff, 0xc11a, 0x21, 0 + .dw 0x2540, 0xc11a, 0x257f, 0xc11a, 0x21, 0 + .dw 0x25c0, 0xc11a, 0x25ff, 0xc11a, 0x21, 0 + .dw 0x2640, 0xc11a, 0x267f, 0xc11a, 0x21, 0 + .dw 0x26c0, 0xc11a, 0x26ff, 0xc11a, 0x21, 0 + .dw 0x2740, 0xc11a, 0x277f, 0xc11a, 0x21, 0 + .dw 0x27c0, 0xc11a, 0x27ff, 0xc11a, 0x21, 0 + .dw 0x2840, 0xc11a, 0x287f, 0xc11a, 0x21, 0 + .dw 0x28c0, 0xc11a, 0x28ff, 0xc11a, 0x21, 0 + .dw 0x2940, 0xc11a, 0x297f, 0xc11a, 0x21, 0 + .dw 0x29c0, 0xc11a, 0x29ff, 0xc11a, 0x21, 0 + .dw 0x2a40, 0xc11a, 0x2a7f, 0xc11a, 0x21, 0 + .dw 0x2ac0, 0xc11a, 0x2aff, 0xc11a, 0x21, 0 + .dw 0x2b40, 0xc11a, 0x2b7f, 0xc11a, 0x21, 0 + .dw 0x2bc0, 0xc11a, 0x2bff, 0xc11a, 0x21, 0 + .dw 0x2c40, 0xc11a, 0x2c7f, 0xc11a, 0x21, 0 + .dw 0x2cc0, 0xc11a, 0x2cff, 0xc11a, 0x21, 0 + .dw 0x2d40, 0xc11a, 0x2d7f, 0xc11a, 0x21, 0 + .dw 0x2dc0, 0xc11a, 0x2dff, 0xc11a, 0x21, 0 + .dw 0x2e40, 0xc11a, 0x2e7f, 0xc11a, 0x21, 0 + .dw 0x2ec0, 0xc11a, 0x2eff, 0xc11a, 0x21, 0 + .dw 0x2f40, 0xc11a, 0x2f7f, 0xc11a, 0x21, 0 + .dw 0x2fc0, 0xc11a, 0x2fff, 0xc11a, 0x21, 0 + .dw 0x3040, 0xc11a, 0x307f, 0xc11a, 0x21, 0 + .dw 0x30c0, 0xc11a, 0x30ff, 0xc11a, 0x21, 0 + .dw 0x3140, 0xc11a, 0x317f, 0xc11a, 0x21, 0 + .dw 0x31c0, 0xc11a, 0x31ff, 0xc11a, 0x21, 0 + .dw 0x3240, 0xc11a, 0x327f, 0xc11a, 0x21, 0 + .dw 0x32c0, 0xc11a, 0x32ff, 0xc11a, 0x21, 0 + .dw 0x3340, 0xc11a, 0x337f, 0xc11a, 0x21, 0 + .dw 0x33c0, 0xc11a, 0x33ff, 0xc11a, 0x21, 0 + .dw 0x3440, 0xc11a, 0x347f, 0xc11a, 0x21, 0 + .dw 0x34c0, 0xc11a, 0x34ff, 0xc11a, 0x21, 0 + .dw 0x3540, 0xc11a, 0x357f, 0xc11a, 0x21, 0 + .dw 0x35c0, 0xc11a, 0x35ff, 0xc11a, 0x21, 0 + .dw 0x3640, 0xc11a, 0x367f, 0xc11a, 0x21, 0 + .dw 0x36c0, 0xc11a, 0x36ff, 0xc11a, 0x21, 0 + .dw 0x3740, 0xc11a, 0x377f, 0xc11a, 0x21, 0 + .dw 0x37c0, 0xc11a, 0x37ff, 0xc11a, 0x21, 0 + .dw 0x3840, 0xc11a, 0x387f, 0xc11a, 0x21, 0 + .dw 0x38c0, 0xc11a, 0x38ff, 0xc11a, 0x21, 0 + .dw 0x3940, 0xc11a, 0x397f, 0xc11a, 0x21, 0 + .dw 0x39c0, 0xc11a, 0x5fff, 0xc11a, 0x21, 0 + .dw 0x6040, 0xc11a, 0x607f, 0xc11a, 0x21, 0 + .dw 0x60c0, 0xc11a, 0x60ff, 0xc11a, 0x21, 0 + .dw 0x6140, 0xc11a, 0x617f, 0xc11a, 0x21, 0 + .dw 0x61c0, 0xc11a, 0x61ff, 0xc11a, 0x21, 0 + .dw 0x6240, 0xc11a, 0x627f, 0xc11a, 0x21, 0 + .dw 0x62c0, 0xc11a, 0x62ff, 0xc11a, 0x21, 0 + .dw 0x6340, 0xc11a, 0x637f, 0xc11a, 0x21, 0 + .dw 0x63c0, 0xc11a, 0x63ff, 0xc11a, 0x21, 0 + .dw 0x6440, 0xc11a, 0x647f, 0xc11a, 0x21, 0 + .dw 0x64c0, 0xc11a, 0x64ff, 0xc11a, 0x21, 0 + .dw 0x6540, 0xc11a, 0x657f, 0xc11a, 0x21, 0 + .dw 0x65c0, 0xc11a, 0x65ff, 0xc11a, 0x21, 0 + .dw 0x6640, 0xc11a, 0x667f, 0xc11a, 0x21, 0 + .dw 0x66c0, 0xc11a, 0x66ff, 0xc11a, 0x21, 0 + .dw 0x6740, 0xc11a, 0x677f, 0xc11a, 0x21, 0 + .dw 0x67c0, 0xc11a, 0x67ff, 0xc11a, 0x21, 0 + .dw 0x6840, 0xc11a, 0x687f, 0xc11a, 0x21, 0 + .dw 0x68c0, 0xc11a, 0x68ff, 0xc11a, 0x21, 0 + .dw 0x6940, 0xc11a, 0x697f, 0xc11a, 0x21, 0 + .dw 0x69c0, 0xc11a, 0x69ff, 0xc11a, 0x21, 0 + .dw 0x6a40, 0xc11a, 0x6a7f, 0xc11a, 0x21, 0 + .dw 0x6ac0, 0xc11a, 0x6aff, 0xc11a, 0x21, 0 + .dw 0x6b40, 0xc11a, 0x6b7f, 0xc11a, 0x21, 0 + .dw 0x6bc0, 0xc11a, 0x6bff, 0xc11a, 0x21, 0 + .dw 0x6c40, 0xc11a, 0x6c7f, 0xc11a, 0x21, 0 + .dw 0x6cc0, 0xc11a, 0x6cff, 0xc11a, 0x21, 0 + .dw 0x6d40, 0xc11a, 0x6d7f, 0xc11a, 0x21, 0 + .dw 0x6dc0, 0xc11a, 0x6dff, 0xc11a, 0x21, 0 + .dw 0x6e40, 0xc11a, 0x6e7f, 0xc11a, 0x21, 0 + .dw 0x6ec0, 0xc11a, 0x6eff, 0xc11a, 0x21, 0 + .dw 0x6f40, 0xc11a, 0x6f7f, 0xc11a, 0x21, 0 + .dw 0x6fc0, 0xc11a, 0x6fff, 0xc11a, 0x21, 0 + .dw 0x7040, 0xc11a, 0x707f, 0xc11a, 0x21, 0 + .dw 0x70c0, 0xc11a, 0x70ff, 0xc11a, 0x21, 0 + .dw 0x7140, 0xc11a, 0x717f, 0xc11a, 0x21, 0 + .dw 0x71c0, 0xc11a, 0x71ff, 0xc11a, 0x21, 0 + .dw 0x7240, 0xc11a, 0x727f, 0xc11a, 0x21, 0 + .dw 0x72c0, 0xc11a, 0x72ff, 0xc11a, 0x21, 0 + .dw 0x7340, 0xc11a, 0x737f, 0xc11a, 0x21, 0 + .dw 0x73c0, 0xc11a, 0x73ff, 0xc11a, 0x21, 0 + .dw 0x7440, 0xc11a, 0x747f, 0xc11a, 0x21, 0 + .dw 0x74c0, 0xc11a, 0x74ff, 0xc11a, 0x21, 0 + .dw 0x7540, 0xc11a, 0x757f, 0xc11a, 0x21, 0 + .dw 0x75c0, 0xc11a, 0x75ff, 0xc11a, 0x21, 0 + .dw 0x7640, 0xc11a, 0x767f, 0xc11a, 0x21, 0 + .dw 0x76c0, 0xc11a, 0x76ff, 0xc11a, 0x21, 0 + .dw 0x7740, 0xc11a, 0x777f, 0xc11a, 0x21, 0 + .dw 0x77c0, 0xc11a, 0x77ff, 0xc11a, 0x21, 0 + .dw 0x7840, 0xc11a, 0x787f, 0xc11a, 0x21, 0 + .dw 0x78c0, 0xc11a, 0x78ff, 0xc11a, 0x21, 0 + .dw 0x7940, 0xc11a, 0x797f, 0xc11a, 0x21, 0 + .dw 0x79c0, 0xc11a, 0x9fff, 0xc11a, 0x21, 0 + .dw 0xa040, 0xc11a, 0xa07f, 0xc11a, 0x21, 0 + .dw 0xa0c0, 0xc11a, 0xa0ff, 0xc11a, 0x21, 0 + .dw 0xa140, 0xc11a, 0xa17f, 0xc11a, 0x21, 0 + .dw 0xa1c0, 0xc11a, 0xa1ff, 0xc11a, 0x21, 0 + .dw 0xa240, 0xc11a, 0xa27f, 0xc11a, 0x21, 0 + .dw 0xa2c0, 0xc11a, 0xa2ff, 0xc11a, 0x21, 0 + .dw 0xa340, 0xc11a, 0xa37f, 0xc11a, 0x21, 0 + .dw 0xa3c0, 0xc11a, 0xa3ff, 0xc11a, 0x21, 0 + .dw 0xa440, 0xc11a, 0xa47f, 0xc11a, 0x21, 0 + .dw 0xa4c0, 0xc11a, 0xa4ff, 0xc11a, 0x21, 0 + .dw 0xa540, 0xc11a, 0xa57f, 0xc11a, 0x21, 0 + .dw 0xa5c0, 0xc11a, 0xa5ff, 0xc11a, 0x21, 0 + .dw 0xa640, 0xc11a, 0xa67f, 0xc11a, 0x21, 0 + .dw 0xa6c0, 0xc11a, 0xa6ff, 0xc11a, 0x21, 0 + .dw 0xa740, 0xc11a, 0xa77f, 0xc11a, 0x21, 0 + .dw 0xa7c0, 0xc11a, 0xa7ff, 0xc11a, 0x21, 0 + .dw 0xa840, 0xc11a, 0xa87f, 0xc11a, 0x21, 0 + .dw 0xa8c0, 0xc11a, 0xa8ff, 0xc11a, 0x21, 0 + .dw 0xa940, 0xc11a, 0xa97f, 0xc11a, 0x21, 0 + .dw 0xa9c0, 0xc11a, 0xa9ff, 0xc11a, 0x21, 0 + .dw 0xaa40, 0xc11a, 0xaa7f, 0xc11a, 0x21, 0 + .dw 0xaac0, 0xc11a, 0xaaff, 0xc11a, 0x21, 0 + .dw 0xab40, 0xc11a, 0xab7f, 0xc11a, 0x21, 0 + .dw 0xabc0, 0xc11a, 0xabff, 0xc11a, 0x21, 0 + .dw 0xac40, 0xc11a, 0xac7f, 0xc11a, 0x21, 0 + .dw 0xacc0, 0xc11a, 0xacff, 0xc11a, 0x21, 0 + .dw 0xad40, 0xc11a, 0xad7f, 0xc11a, 0x21, 0 + .dw 0xadc0, 0xc11a, 0xadff, 0xc11a, 0x21, 0 + .dw 0xae40, 0xc11a, 0xae7f, 0xc11a, 0x21, 0 + .dw 0xaec0, 0xc11a, 0xaeff, 0xc11a, 0x21, 0 + .dw 0xaf40, 0xc11a, 0xaf7f, 0xc11a, 0x21, 0 + .dw 0xafc0, 0xc11a, 0xafff, 0xc11a, 0x21, 0 + .dw 0xb040, 0xc11a, 0xb07f, 0xc11a, 0x21, 0 + .dw 0xb0c0, 0xc11a, 0xb0ff, 0xc11a, 0x21, 0 + .dw 0xb140, 0xc11a, 0xb17f, 0xc11a, 0x21, 0 + .dw 0xb1c0, 0xc11a, 0xb1ff, 0xc11a, 0x21, 0 + .dw 0xb240, 0xc11a, 0xb27f, 0xc11a, 0x21, 0 + .dw 0xb2c0, 0xc11a, 0xb2ff, 0xc11a, 0x21, 0 + .dw 0xb340, 0xc11a, 0xb37f, 0xc11a, 0x21, 0 + .dw 0xb3c0, 0xc11a, 0xb3ff, 0xc11a, 0x21, 0 + .dw 0xb440, 0xc11a, 0xb47f, 0xc11a, 0x21, 0 + .dw 0xb4c0, 0xc11a, 0xb4ff, 0xc11a, 0x21, 0 + .dw 0xb540, 0xc11a, 0xb57f, 0xc11a, 0x21, 0 + .dw 0xb5c0, 0xc11a, 0xb5ff, 0xc11a, 0x21, 0 + .dw 0xb640, 0xc11a, 0xb67f, 0xc11a, 0x21, 0 + .dw 0xb6c0, 0xc11a, 0xb6ff, 0xc11a, 0x21, 0 + .dw 0xb740, 0xc11a, 0xb77f, 0xc11a, 0x21, 0 + .dw 0xb7c0, 0xc11a, 0xb7ff, 0xc11a, 0x21, 0 + .dw 0xb840, 0xc11a, 0xb87f, 0xc11a, 0x21, 0 + .dw 0xb8c0, 0xc11a, 0xb8ff, 0xc11a, 0x21, 0 + .dw 0xb940, 0xc11a, 0xb97f, 0xc11a, 0x21, 0 + .dw 0xb9c0, 0xc11a, 0xdfff, 0xc11a, 0x21, 0 + .dw 0xe040, 0xc11a, 0xe07f, 0xc11a, 0x21, 0 + .dw 0xe0c0, 0xc11a, 0xe0ff, 0xc11a, 0x21, 0 + .dw 0xe140, 0xc11a, 0xe17f, 0xc11a, 0x21, 0 + .dw 0xe1c0, 0xc11a, 0xe1ff, 0xc11a, 0x21, 0 + .dw 0xe240, 0xc11a, 0xe27f, 0xc11a, 0x21, 0 + .dw 0xe2c0, 0xc11a, 0xe2ff, 0xc11a, 0x21, 0 + .dw 0xe340, 0xc11a, 0xe37f, 0xc11a, 0x21, 0 + .dw 0xe3c0, 0xc11a, 0xe3ff, 0xc11a, 0x21, 0 + .dw 0xe440, 0xc11a, 0xe47f, 0xc11a, 0x21, 0 + .dw 0xe4c0, 0xc11a, 0xe4ff, 0xc11a, 0x21, 0 + .dw 0xe540, 0xc11a, 0xe57f, 0xc11a, 0x21, 0 + .dw 0xe5c0, 0xc11a, 0xe5ff, 0xc11a, 0x21, 0 + .dw 0xe640, 0xc11a, 0xe67f, 0xc11a, 0x21, 0 + .dw 0xe6c0, 0xc11a, 0xe6ff, 0xc11a, 0x21, 0 + .dw 0xe740, 0xc11a, 0xe77f, 0xc11a, 0x21, 0 + .dw 0xe7c0, 0xc11a, 0xe7ff, 0xc11a, 0x21, 0 + .dw 0xe840, 0xc11a, 0xe87f, 0xc11a, 0x21, 0 + .dw 0xe8c0, 0xc11a, 0xe8ff, 0xc11a, 0x21, 0 + .dw 0xe940, 0xc11a, 0xe97f, 0xc11a, 0x21, 0 + .dw 0xe9c0, 0xc11a, 0xe9ff, 0xc11a, 0x21, 0 + .dw 0xea40, 0xc11a, 0xea7f, 0xc11a, 0x21, 0 + .dw 0xeac0, 0xc11a, 0xeaff, 0xc11a, 0x21, 0 + .dw 0xeb40, 0xc11a, 0xeb7f, 0xc11a, 0x21, 0 + .dw 0xebc0, 0xc11a, 0xebff, 0xc11a, 0x21, 0 + .dw 0xec40, 0xc11a, 0xec7f, 0xc11a, 0x21, 0 + .dw 0xecc0, 0xc11a, 0xecff, 0xc11a, 0x21, 0 + .dw 0xed40, 0xc11a, 0xed7f, 0xc11a, 0x21, 0 + .dw 0xedc0, 0xc11a, 0xedff, 0xc11a, 0x21, 0 + .dw 0xee40, 0xc11a, 0xee7f, 0xc11a, 0x21, 0 + .dw 0xeec0, 0xc11a, 0xeeff, 0xc11a, 0x21, 0 + .dw 0xef40, 0xc11a, 0xef7f, 0xc11a, 0x21, 0 + .dw 0xefc0, 0xc11a, 0xefff, 0xc11a, 0x21, 0 + .dw 0xf040, 0xc11a, 0xf07f, 0xc11a, 0x21, 0 + .dw 0xf0c0, 0xc11a, 0xf0ff, 0xc11a, 0x21, 0 + .dw 0xf140, 0xc11a, 0xf17f, 0xc11a, 0x21, 0 + .dw 0xf1c0, 0xc11a, 0xf1ff, 0xc11a, 0x21, 0 + .dw 0xf240, 0xc11a, 0xf27f, 0xc11a, 0x21, 0 + .dw 0xf2c0, 0xc11a, 0xf2ff, 0xc11a, 0x21, 0 + .dw 0xf340, 0xc11a, 0xf37f, 0xc11a, 0x21, 0 + .dw 0xf3c0, 0xc11a, 0xf3ff, 0xc11a, 0x21, 0 + .dw 0xf440, 0xc11a, 0xf47f, 0xc11a, 0x21, 0 + .dw 0xf4c0, 0xc11a, 0xf4ff, 0xc11a, 0x21, 0 + .dw 0xf540, 0xc11a, 0xf57f, 0xc11a, 0x21, 0 + .dw 0xf5c0, 0xc11a, 0xf5ff, 0xc11a, 0x21, 0 + .dw 0xf640, 0xc11a, 0xf67f, 0xc11a, 0x21, 0 + .dw 0xf6c0, 0xc11a, 0xf6ff, 0xc11a, 0x21, 0 + .dw 0xf740, 0xc11a, 0xf77f, 0xc11a, 0x21, 0 + .dw 0xf7c0, 0xc11a, 0xf7ff, 0xc11a, 0x21, 0 + .dw 0xf840, 0xc11a, 0xf87f, 0xc11a, 0x21, 0 + .dw 0xf8c0, 0xc11a, 0xf8ff, 0xc11a, 0x21, 0 + .dw 0xf940, 0xc11a, 0xf97f, 0xc11a, 0x21, 0 + .dw 0xf9c0, 0xc11a, 0xffff, 0xc11b, 0x21, 0 + .dw 0x0040, 0xc11c, 0x007f, 0xc11c, 0x21, 0 + .dw 0x00c0, 0xc11c, 0x00ff, 0xc11c, 0x21, 0 + .dw 0x0140, 0xc11c, 0x017f, 0xc11c, 0x21, 0 + .dw 0x01c0, 0xc11c, 0x01ff, 0xc11c, 0x21, 0 + .dw 0x0240, 0xc11c, 0x027f, 0xc11c, 0x21, 0 + .dw 0x02c0, 0xc11c, 0x02ff, 0xc11c, 0x21, 0 + .dw 0x0340, 0xc11c, 0x037f, 0xc11c, 0x21, 0 + .dw 0x03c0, 0xc11c, 0x03ff, 0xc11c, 0x21, 0 + .dw 0x0440, 0xc11c, 0x047f, 0xc11c, 0x21, 0 + .dw 0x04c0, 0xc11c, 0x04ff, 0xc11c, 0x21, 0 + .dw 0x0540, 0xc11c, 0x057f, 0xc11c, 0x21, 0 + .dw 0x05c0, 0xc11c, 0x05ff, 0xc11c, 0x21, 0 + .dw 0x0640, 0xc11c, 0x067f, 0xc11c, 0x21, 0 + .dw 0x06c0, 0xc11c, 0x06ff, 0xc11c, 0x21, 0 + .dw 0x0740, 0xc11c, 0x077f, 0xc11c, 0x21, 0 + .dw 0x07c0, 0xc11c, 0x07ff, 0xc11c, 0x21, 0 + .dw 0x0840, 0xc11c, 0x087f, 0xc11c, 0x21, 0 + .dw 0x08c0, 0xc11c, 0x08ff, 0xc11c, 0x21, 0 + .dw 0x0940, 0xc11c, 0x097f, 0xc11c, 0x21, 0 + .dw 0x09c0, 0xc11c, 0x09ff, 0xc11c, 0x21, 0 + .dw 0x0a40, 0xc11c, 0x0a7f, 0xc11c, 0x21, 0 + .dw 0x0ac0, 0xc11c, 0x0aff, 0xc11c, 0x21, 0 + .dw 0x0b40, 0xc11c, 0x0b7f, 0xc11c, 0x21, 0 + .dw 0x0bc0, 0xc11c, 0x0bff, 0xc11c, 0x21, 0 + .dw 0x0c40, 0xc11c, 0x0c7f, 0xc11c, 0x21, 0 + .dw 0x0cc0, 0xc11c, 0x0cff, 0xc11c, 0x21, 0 + .dw 0x0d40, 0xc11c, 0x0d7f, 0xc11c, 0x21, 0 + .dw 0x0dc0, 0xc11c, 0x0dff, 0xc11c, 0x21, 0 + .dw 0x0e40, 0xc11c, 0x0e7f, 0xc11c, 0x21, 0 + .dw 0x0ec0, 0xc11c, 0x0eff, 0xc11c, 0x21, 0 + .dw 0x0f40, 0xc11c, 0x0f7f, 0xc11c, 0x21, 0 + .dw 0x0fc0, 0xc11c, 0x0fff, 0xc11c, 0x21, 0 + .dw 0x1040, 0xc11c, 0x107f, 0xc11c, 0x21, 0 + .dw 0x10c0, 0xc11c, 0x10ff, 0xc11c, 0x21, 0 + .dw 0x1140, 0xc11c, 0x117f, 0xc11c, 0x21, 0 + .dw 0x11c0, 0xc11c, 0x11ff, 0xc11c, 0x21, 0 + .dw 0x1240, 0xc11c, 0x127f, 0xc11c, 0x21, 0 + .dw 0x12c0, 0xc11c, 0x12ff, 0xc11c, 0x21, 0 + .dw 0x1340, 0xc11c, 0x137f, 0xc11c, 0x21, 0 + .dw 0x13c0, 0xc11c, 0x13ff, 0xc11c, 0x21, 0 + .dw 0x1440, 0xc11c, 0x147f, 0xc11c, 0x21, 0 + .dw 0x14c0, 0xc11c, 0x14ff, 0xc11c, 0x21, 0 + .dw 0x1540, 0xc11c, 0x157f, 0xc11c, 0x21, 0 + .dw 0x15c0, 0xc11c, 0x15ff, 0xc11c, 0x21, 0 + .dw 0x1640, 0xc11c, 0x167f, 0xc11c, 0x21, 0 + .dw 0x16c0, 0xc11c, 0x16ff, 0xc11c, 0x21, 0 + .dw 0x1740, 0xc11c, 0x177f, 0xc11c, 0x21, 0 + .dw 0x17c0, 0xc11c, 0x17ff, 0xc11c, 0x21, 0 + .dw 0x1840, 0xc11c, 0x187f, 0xc11c, 0x21, 0 + .dw 0x18c0, 0xc11c, 0x18ff, 0xc11c, 0x21, 0 + .dw 0x1940, 0xc11c, 0x197f, 0xc11c, 0x21, 0 + .dw 0x19c0, 0xc11c, 0x1fff, 0xc11c, 0x21, 0 + .dw 0x2040, 0xc11c, 0x207f, 0xc11c, 0x21, 0 + .dw 0x20c0, 0xc11c, 0x20ff, 0xc11c, 0x21, 0 + .dw 0x2140, 0xc11c, 0x217f, 0xc11c, 0x21, 0 + .dw 0x21c0, 0xc11c, 0x21ff, 0xc11c, 0x21, 0 + .dw 0x2240, 0xc11c, 0x227f, 0xc11c, 0x21, 0 + .dw 0x22c0, 0xc11c, 0x22ff, 0xc11c, 0x21, 0 + .dw 0x2340, 0xc11c, 0x237f, 0xc11c, 0x21, 0 + .dw 0x23c0, 0xc11c, 0x23ff, 0xc11c, 0x21, 0 + .dw 0x2440, 0xc11c, 0x247f, 0xc11c, 0x21, 0 + .dw 0x24c0, 0xc11c, 0x24ff, 0xc11c, 0x21, 0 + .dw 0x2540, 0xc11c, 0x257f, 0xc11c, 0x21, 0 + .dw 0x25c0, 0xc11c, 0x25ff, 0xc11c, 0x21, 0 + .dw 0x2640, 0xc11c, 0x267f, 0xc11c, 0x21, 0 + .dw 0x26c0, 0xc11c, 0x26ff, 0xc11c, 0x21, 0 + .dw 0x2740, 0xc11c, 0x277f, 0xc11c, 0x21, 0 + .dw 0x27c0, 0xc11c, 0x27ff, 0xc11c, 0x21, 0 + .dw 0x2840, 0xc11c, 0x287f, 0xc11c, 0x21, 0 + .dw 0x28c0, 0xc11c, 0x28ff, 0xc11c, 0x21, 0 + .dw 0x2940, 0xc11c, 0x297f, 0xc11c, 0x21, 0 + .dw 0x29c0, 0xc11c, 0x29ff, 0xc11c, 0x21, 0 + .dw 0x2a40, 0xc11c, 0x2a7f, 0xc11c, 0x21, 0 + .dw 0x2ac0, 0xc11c, 0x2aff, 0xc11c, 0x21, 0 + .dw 0x2b40, 0xc11c, 0x2b7f, 0xc11c, 0x21, 0 + .dw 0x2bc0, 0xc11c, 0x2bff, 0xc11c, 0x21, 0 + .dw 0x2c40, 0xc11c, 0x2c7f, 0xc11c, 0x21, 0 + .dw 0x2cc0, 0xc11c, 0x2cff, 0xc11c, 0x21, 0 + .dw 0x2d40, 0xc11c, 0x2d7f, 0xc11c, 0x21, 0 + .dw 0x2dc0, 0xc11c, 0x2dff, 0xc11c, 0x21, 0 + .dw 0x2e40, 0xc11c, 0x2e7f, 0xc11c, 0x21, 0 + .dw 0x2ec0, 0xc11c, 0x2eff, 0xc11c, 0x21, 0 + .dw 0x2f40, 0xc11c, 0x2f7f, 0xc11c, 0x21, 0 + .dw 0x2fc0, 0xc11c, 0x2fff, 0xc11c, 0x21, 0 + .dw 0x3040, 0xc11c, 0x307f, 0xc11c, 0x21, 0 + .dw 0x30c0, 0xc11c, 0x30ff, 0xc11c, 0x21, 0 + .dw 0x3140, 0xc11c, 0x317f, 0xc11c, 0x21, 0 + .dw 0x31c0, 0xc11c, 0x31ff, 0xc11c, 0x21, 0 + .dw 0x3240, 0xc11c, 0x327f, 0xc11c, 0x21, 0 + .dw 0x32c0, 0xc11c, 0x32ff, 0xc11c, 0x21, 0 + .dw 0x3340, 0xc11c, 0x337f, 0xc11c, 0x21, 0 + .dw 0x33c0, 0xc11c, 0x33ff, 0xc11c, 0x21, 0 + .dw 0x3440, 0xc11c, 0x347f, 0xc11c, 0x21, 0 + .dw 0x34c0, 0xc11c, 0x34ff, 0xc11c, 0x21, 0 + .dw 0x3540, 0xc11c, 0x357f, 0xc11c, 0x21, 0 + .dw 0x35c0, 0xc11c, 0x35ff, 0xc11c, 0x21, 0 + .dw 0x3640, 0xc11c, 0x367f, 0xc11c, 0x21, 0 + .dw 0x36c0, 0xc11c, 0x36ff, 0xc11c, 0x21, 0 + .dw 0x3740, 0xc11c, 0x377f, 0xc11c, 0x21, 0 + .dw 0x37c0, 0xc11c, 0x37ff, 0xc11c, 0x21, 0 + .dw 0x3840, 0xc11c, 0x387f, 0xc11c, 0x21, 0 + .dw 0x38c0, 0xc11c, 0x38ff, 0xc11c, 0x21, 0 + .dw 0x3940, 0xc11c, 0x397f, 0xc11c, 0x21, 0 + .dw 0x39c0, 0xc11c, 0x3fff, 0xc11c, 0x21, 0 + .dw 0x4040, 0xc11c, 0x407f, 0xc11c, 0x21, 0 + .dw 0x40c0, 0xc11c, 0x40ff, 0xc11c, 0x21, 0 + .dw 0x4140, 0xc11c, 0x417f, 0xc11c, 0x21, 0 + .dw 0x41c0, 0xc11c, 0x41ff, 0xc11c, 0x21, 0 + .dw 0x4240, 0xc11c, 0x427f, 0xc11c, 0x21, 0 + .dw 0x42c0, 0xc11c, 0x42ff, 0xc11c, 0x21, 0 + .dw 0x4340, 0xc11c, 0x437f, 0xc11c, 0x21, 0 + .dw 0x43c0, 0xc11c, 0x43ff, 0xc11c, 0x21, 0 + .dw 0x4440, 0xc11c, 0x447f, 0xc11c, 0x21, 0 + .dw 0x44c0, 0xc11c, 0x44ff, 0xc11c, 0x21, 0 + .dw 0x4540, 0xc11c, 0x457f, 0xc11c, 0x21, 0 + .dw 0x45c0, 0xc11c, 0x45ff, 0xc11c, 0x21, 0 + .dw 0x4640, 0xc11c, 0x467f, 0xc11c, 0x21, 0 + .dw 0x46c0, 0xc11c, 0x46ff, 0xc11c, 0x21, 0 + .dw 0x4740, 0xc11c, 0x477f, 0xc11c, 0x21, 0 + .dw 0x47c0, 0xc11c, 0x47ff, 0xc11c, 0x21, 0 + .dw 0x4840, 0xc11c, 0x487f, 0xc11c, 0x21, 0 + .dw 0x48c0, 0xc11c, 0x48ff, 0xc11c, 0x21, 0 + .dw 0x4940, 0xc11c, 0x497f, 0xc11c, 0x21, 0 + .dw 0x49c0, 0xc11c, 0x49ff, 0xc11c, 0x21, 0 + .dw 0x4a40, 0xc11c, 0x4a7f, 0xc11c, 0x21, 0 + .dw 0x4ac0, 0xc11c, 0x4aff, 0xc11c, 0x21, 0 + .dw 0x4b40, 0xc11c, 0x4b7f, 0xc11c, 0x21, 0 + .dw 0x4bc0, 0xc11c, 0x4bff, 0xc11c, 0x21, 0 + .dw 0x4c40, 0xc11c, 0x4c7f, 0xc11c, 0x21, 0 + .dw 0x4cc0, 0xc11c, 0x4cff, 0xc11c, 0x21, 0 + .dw 0x4d40, 0xc11c, 0x4d7f, 0xc11c, 0x21, 0 + .dw 0x4dc0, 0xc11c, 0x4dff, 0xc11c, 0x21, 0 + .dw 0x4e40, 0xc11c, 0x4e7f, 0xc11c, 0x21, 0 + .dw 0x4ec0, 0xc11c, 0x4eff, 0xc11c, 0x21, 0 + .dw 0x4f40, 0xc11c, 0x4f7f, 0xc11c, 0x21, 0 + .dw 0x4fc0, 0xc11c, 0x4fff, 0xc11c, 0x21, 0 + .dw 0x5040, 0xc11c, 0x507f, 0xc11c, 0x21, 0 + .dw 0x50c0, 0xc11c, 0x50ff, 0xc11c, 0x21, 0 + .dw 0x5140, 0xc11c, 0x517f, 0xc11c, 0x21, 0 + .dw 0x51c0, 0xc11c, 0x51ff, 0xc11c, 0x21, 0 + .dw 0x5240, 0xc11c, 0x527f, 0xc11c, 0x21, 0 + .dw 0x52c0, 0xc11c, 0x52ff, 0xc11c, 0x21, 0 + .dw 0x5340, 0xc11c, 0x537f, 0xc11c, 0x21, 0 + .dw 0x53c0, 0xc11c, 0x53ff, 0xc11c, 0x21, 0 + .dw 0x5440, 0xc11c, 0x547f, 0xc11c, 0x21, 0 + .dw 0x54c0, 0xc11c, 0x54ff, 0xc11c, 0x21, 0 + .dw 0x5540, 0xc11c, 0x557f, 0xc11c, 0x21, 0 + .dw 0x55c0, 0xc11c, 0x55ff, 0xc11c, 0x21, 0 + .dw 0x5640, 0xc11c, 0x567f, 0xc11c, 0x21, 0 + .dw 0x56c0, 0xc11c, 0x56ff, 0xc11c, 0x21, 0 + .dw 0x5740, 0xc11c, 0x577f, 0xc11c, 0x21, 0 + .dw 0x57c0, 0xc11c, 0x57ff, 0xc11c, 0x21, 0 + .dw 0x5840, 0xc11c, 0x587f, 0xc11c, 0x21, 0 + .dw 0x58c0, 0xc11c, 0x58ff, 0xc11c, 0x21, 0 + .dw 0x5940, 0xc11c, 0x597f, 0xc11c, 0x21, 0 + .dw 0x59c0, 0xc11c, 0x5fff, 0xc11c, 0x21, 0 + .dw 0x6040, 0xc11c, 0x607f, 0xc11c, 0x21, 0 + .dw 0x60c0, 0xc11c, 0x60ff, 0xc11c, 0x21, 0 + .dw 0x6140, 0xc11c, 0x617f, 0xc11c, 0x21, 0 + .dw 0x61c0, 0xc11c, 0x61ff, 0xc11c, 0x21, 0 + .dw 0x6240, 0xc11c, 0x627f, 0xc11c, 0x21, 0 + .dw 0x62c0, 0xc11c, 0x62ff, 0xc11c, 0x21, 0 + .dw 0x6340, 0xc11c, 0x637f, 0xc11c, 0x21, 0 + .dw 0x63c0, 0xc11c, 0x63ff, 0xc11c, 0x21, 0 + .dw 0x6440, 0xc11c, 0x647f, 0xc11c, 0x21, 0 + .dw 0x64c0, 0xc11c, 0x64ff, 0xc11c, 0x21, 0 + .dw 0x6540, 0xc11c, 0x657f, 0xc11c, 0x21, 0 + .dw 0x65c0, 0xc11c, 0x65ff, 0xc11c, 0x21, 0 + .dw 0x6640, 0xc11c, 0x667f, 0xc11c, 0x21, 0 + .dw 0x66c0, 0xc11c, 0x66ff, 0xc11c, 0x21, 0 + .dw 0x6740, 0xc11c, 0x677f, 0xc11c, 0x21, 0 + .dw 0x67c0, 0xc11c, 0x67ff, 0xc11c, 0x21, 0 + .dw 0x6840, 0xc11c, 0x687f, 0xc11c, 0x21, 0 + .dw 0x68c0, 0xc11c, 0x68ff, 0xc11c, 0x21, 0 + .dw 0x6940, 0xc11c, 0x697f, 0xc11c, 0x21, 0 + .dw 0x69c0, 0xc11c, 0x69ff, 0xc11c, 0x21, 0 + .dw 0x6a40, 0xc11c, 0x6a7f, 0xc11c, 0x21, 0 + .dw 0x6ac0, 0xc11c, 0x6aff, 0xc11c, 0x21, 0 + .dw 0x6b40, 0xc11c, 0x6b7f, 0xc11c, 0x21, 0 + .dw 0x6bc0, 0xc11c, 0x6bff, 0xc11c, 0x21, 0 + .dw 0x6c40, 0xc11c, 0x6c7f, 0xc11c, 0x21, 0 + .dw 0x6cc0, 0xc11c, 0x6cff, 0xc11c, 0x21, 0 + .dw 0x6d40, 0xc11c, 0x6d7f, 0xc11c, 0x21, 0 + .dw 0x6dc0, 0xc11c, 0x6dff, 0xc11c, 0x21, 0 + .dw 0x6e40, 0xc11c, 0x6e7f, 0xc11c, 0x21, 0 + .dw 0x6ec0, 0xc11c, 0x6eff, 0xc11c, 0x21, 0 + .dw 0x6f40, 0xc11c, 0x6f7f, 0xc11c, 0x21, 0 + .dw 0x6fc0, 0xc11c, 0x6fff, 0xc11c, 0x21, 0 + .dw 0x7040, 0xc11c, 0x707f, 0xc11c, 0x21, 0 + .dw 0x70c0, 0xc11c, 0x70ff, 0xc11c, 0x21, 0 + .dw 0x7140, 0xc11c, 0x717f, 0xc11c, 0x21, 0 + .dw 0x71c0, 0xc11c, 0x71ff, 0xc11c, 0x21, 0 + .dw 0x7240, 0xc11c, 0x727f, 0xc11c, 0x21, 0 + .dw 0x72c0, 0xc11c, 0x72ff, 0xc11c, 0x21, 0 + .dw 0x7340, 0xc11c, 0x737f, 0xc11c, 0x21, 0 + .dw 0x73c0, 0xc11c, 0x73ff, 0xc11c, 0x21, 0 + .dw 0x7440, 0xc11c, 0x747f, 0xc11c, 0x21, 0 + .dw 0x74c0, 0xc11c, 0x74ff, 0xc11c, 0x21, 0 + .dw 0x7540, 0xc11c, 0x757f, 0xc11c, 0x21, 0 + .dw 0x75c0, 0xc11c, 0x75ff, 0xc11c, 0x21, 0 + .dw 0x7640, 0xc11c, 0x767f, 0xc11c, 0x21, 0 + .dw 0x76c0, 0xc11c, 0x76ff, 0xc11c, 0x21, 0 + .dw 0x7740, 0xc11c, 0x777f, 0xc11c, 0x21, 0 + .dw 0x77c0, 0xc11c, 0x77ff, 0xc11c, 0x21, 0 + .dw 0x7840, 0xc11c, 0x787f, 0xc11c, 0x21, 0 + .dw 0x78c0, 0xc11c, 0x78ff, 0xc11c, 0x21, 0 + .dw 0x7940, 0xc11c, 0x797f, 0xc11c, 0x21, 0 + .dw 0x79c0, 0xc11c, 0x7fff, 0xc11c, 0x21, 0 + .dw 0x8040, 0xc11c, 0x807f, 0xc11c, 0x21, 0 + .dw 0x80c0, 0xc11c, 0x80ff, 0xc11c, 0x21, 0 + .dw 0x8140, 0xc11c, 0x817f, 0xc11c, 0x21, 0 + .dw 0x81c0, 0xc11c, 0x81ff, 0xc11c, 0x21, 0 + .dw 0x8240, 0xc11c, 0x827f, 0xc11c, 0x21, 0 + .dw 0x82c0, 0xc11c, 0x82ff, 0xc11c, 0x21, 0 + .dw 0x8340, 0xc11c, 0x837f, 0xc11c, 0x21, 0 + .dw 0x83c0, 0xc11c, 0x83ff, 0xc11c, 0x21, 0 + .dw 0x8440, 0xc11c, 0x847f, 0xc11c, 0x21, 0 + .dw 0x84c0, 0xc11c, 0x84ff, 0xc11c, 0x21, 0 + .dw 0x8540, 0xc11c, 0x857f, 0xc11c, 0x21, 0 + .dw 0x85c0, 0xc11c, 0x85ff, 0xc11c, 0x21, 0 + .dw 0x8640, 0xc11c, 0x867f, 0xc11c, 0x21, 0 + .dw 0x86c0, 0xc11c, 0x86ff, 0xc11c, 0x21, 0 + .dw 0x8740, 0xc11c, 0x877f, 0xc11c, 0x21, 0 + .dw 0x87c0, 0xc11c, 0x87ff, 0xc11c, 0x21, 0 + .dw 0x8840, 0xc11c, 0x887f, 0xc11c, 0x21, 0 + .dw 0x88c0, 0xc11c, 0x88ff, 0xc11c, 0x21, 0 + .dw 0x8940, 0xc11c, 0x897f, 0xc11c, 0x21, 0 + .dw 0x89c0, 0xc11c, 0x89ff, 0xc11c, 0x21, 0 + .dw 0x8a40, 0xc11c, 0x8a7f, 0xc11c, 0x21, 0 + .dw 0x8ac0, 0xc11c, 0x8aff, 0xc11c, 0x21, 0 + .dw 0x8b40, 0xc11c, 0x8b7f, 0xc11c, 0x21, 0 + .dw 0x8bc0, 0xc11c, 0x8bff, 0xc11c, 0x21, 0 + .dw 0x8c40, 0xc11c, 0x8c7f, 0xc11c, 0x21, 0 + .dw 0x8cc0, 0xc11c, 0x8cff, 0xc11c, 0x21, 0 + .dw 0x8d40, 0xc11c, 0x8d7f, 0xc11c, 0x21, 0 + .dw 0x8dc0, 0xc11c, 0x8dff, 0xc11c, 0x21, 0 + .dw 0x8e40, 0xc11c, 0x8e7f, 0xc11c, 0x21, 0 + .dw 0x8ec0, 0xc11c, 0x8eff, 0xc11c, 0x21, 0 + .dw 0x8f40, 0xc11c, 0x8f7f, 0xc11c, 0x21, 0 + .dw 0x8fc0, 0xc11c, 0x8fff, 0xc11c, 0x21, 0 + .dw 0x9040, 0xc11c, 0x907f, 0xc11c, 0x21, 0 + .dw 0x90c0, 0xc11c, 0x90ff, 0xc11c, 0x21, 0 + .dw 0x9140, 0xc11c, 0x917f, 0xc11c, 0x21, 0 + .dw 0x91c0, 0xc11c, 0x91ff, 0xc11c, 0x21, 0 + .dw 0x9240, 0xc11c, 0x927f, 0xc11c, 0x21, 0 + .dw 0x92c0, 0xc11c, 0x92ff, 0xc11c, 0x21, 0 + .dw 0x9340, 0xc11c, 0x937f, 0xc11c, 0x21, 0 + .dw 0x93c0, 0xc11c, 0x93ff, 0xc11c, 0x21, 0 + .dw 0x9440, 0xc11c, 0x947f, 0xc11c, 0x21, 0 + .dw 0x94c0, 0xc11c, 0x94ff, 0xc11c, 0x21, 0 + .dw 0x9540, 0xc11c, 0x957f, 0xc11c, 0x21, 0 + .dw 0x95c0, 0xc11c, 0x95ff, 0xc11c, 0x21, 0 + .dw 0x9640, 0xc11c, 0x967f, 0xc11c, 0x21, 0 + .dw 0x96c0, 0xc11c, 0x96ff, 0xc11c, 0x21, 0 + .dw 0x9740, 0xc11c, 0x977f, 0xc11c, 0x21, 0 + .dw 0x97c0, 0xc11c, 0x97ff, 0xc11c, 0x21, 0 + .dw 0x9840, 0xc11c, 0x987f, 0xc11c, 0x21, 0 + .dw 0x98c0, 0xc11c, 0x98ff, 0xc11c, 0x21, 0 + .dw 0x9940, 0xc11c, 0x997f, 0xc11c, 0x21, 0 + .dw 0x99c0, 0xc11c, 0x9fff, 0xc11c, 0x21, 0 + .dw 0xa040, 0xc11c, 0xa07f, 0xc11c, 0x21, 0 + .dw 0xa0c0, 0xc11c, 0xa0ff, 0xc11c, 0x21, 0 + .dw 0xa140, 0xc11c, 0xa17f, 0xc11c, 0x21, 0 + .dw 0xa1c0, 0xc11c, 0xa1ff, 0xc11c, 0x21, 0 + .dw 0xa240, 0xc11c, 0xa27f, 0xc11c, 0x21, 0 + .dw 0xa2c0, 0xc11c, 0xa2ff, 0xc11c, 0x21, 0 + .dw 0xa340, 0xc11c, 0xa37f, 0xc11c, 0x21, 0 + .dw 0xa3c0, 0xc11c, 0xa3ff, 0xc11c, 0x21, 0 + .dw 0xa440, 0xc11c, 0xa47f, 0xc11c, 0x21, 0 + .dw 0xa4c0, 0xc11c, 0xa4ff, 0xc11c, 0x21, 0 + .dw 0xa540, 0xc11c, 0xa57f, 0xc11c, 0x21, 0 + .dw 0xa5c0, 0xc11c, 0xa5ff, 0xc11c, 0x21, 0 + .dw 0xa640, 0xc11c, 0xa67f, 0xc11c, 0x21, 0 + .dw 0xa6c0, 0xc11c, 0xa6ff, 0xc11c, 0x21, 0 + .dw 0xa740, 0xc11c, 0xa77f, 0xc11c, 0x21, 0 + .dw 0xa7c0, 0xc11c, 0xa7ff, 0xc11c, 0x21, 0 + .dw 0xa840, 0xc11c, 0xa87f, 0xc11c, 0x21, 0 + .dw 0xa8c0, 0xc11c, 0xa8ff, 0xc11c, 0x21, 0 + .dw 0xa940, 0xc11c, 0xa97f, 0xc11c, 0x21, 0 + .dw 0xa9c0, 0xc11c, 0xa9ff, 0xc11c, 0x21, 0 + .dw 0xaa40, 0xc11c, 0xaa7f, 0xc11c, 0x21, 0 + .dw 0xaac0, 0xc11c, 0xaaff, 0xc11c, 0x21, 0 + .dw 0xab40, 0xc11c, 0xab7f, 0xc11c, 0x21, 0 + .dw 0xabc0, 0xc11c, 0xabff, 0xc11c, 0x21, 0 + .dw 0xac40, 0xc11c, 0xac7f, 0xc11c, 0x21, 0 + .dw 0xacc0, 0xc11c, 0xacff, 0xc11c, 0x21, 0 + .dw 0xad40, 0xc11c, 0xad7f, 0xc11c, 0x21, 0 + .dw 0xadc0, 0xc11c, 0xadff, 0xc11c, 0x21, 0 + .dw 0xae40, 0xc11c, 0xae7f, 0xc11c, 0x21, 0 + .dw 0xaec0, 0xc11c, 0xaeff, 0xc11c, 0x21, 0 + .dw 0xaf40, 0xc11c, 0xaf7f, 0xc11c, 0x21, 0 + .dw 0xafc0, 0xc11c, 0xafff, 0xc11c, 0x21, 0 + .dw 0xb040, 0xc11c, 0xb07f, 0xc11c, 0x21, 0 + .dw 0xb0c0, 0xc11c, 0xb0ff, 0xc11c, 0x21, 0 + .dw 0xb140, 0xc11c, 0xb17f, 0xc11c, 0x21, 0 + .dw 0xb1c0, 0xc11c, 0xb1ff, 0xc11c, 0x21, 0 + .dw 0xb240, 0xc11c, 0xb27f, 0xc11c, 0x21, 0 + .dw 0xb2c0, 0xc11c, 0xb2ff, 0xc11c, 0x21, 0 + .dw 0xb340, 0xc11c, 0xb37f, 0xc11c, 0x21, 0 + .dw 0xb3c0, 0xc11c, 0xb3ff, 0xc11c, 0x21, 0 + .dw 0xb440, 0xc11c, 0xb47f, 0xc11c, 0x21, 0 + .dw 0xb4c0, 0xc11c, 0xb4ff, 0xc11c, 0x21, 0 + .dw 0xb540, 0xc11c, 0xb57f, 0xc11c, 0x21, 0 + .dw 0xb5c0, 0xc11c, 0xb5ff, 0xc11c, 0x21, 0 + .dw 0xb640, 0xc11c, 0xb67f, 0xc11c, 0x21, 0 + .dw 0xb6c0, 0xc11c, 0xb6ff, 0xc11c, 0x21, 0 + .dw 0xb740, 0xc11c, 0xb77f, 0xc11c, 0x21, 0 + .dw 0xb7c0, 0xc11c, 0xb7ff, 0xc11c, 0x21, 0 + .dw 0xb840, 0xc11c, 0xb87f, 0xc11c, 0x21, 0 + .dw 0xb8c0, 0xc11c, 0xb8ff, 0xc11c, 0x21, 0 + .dw 0xb940, 0xc11c, 0xb97f, 0xc11c, 0x21, 0 + .dw 0xb9c0, 0xc11c, 0xbfff, 0xc11c, 0x21, 0 + .dw 0xc040, 0xc11c, 0xc07f, 0xc11c, 0x21, 0 + .dw 0xc0c0, 0xc11c, 0xc0ff, 0xc11c, 0x21, 0 + .dw 0xc140, 0xc11c, 0xc17f, 0xc11c, 0x21, 0 + .dw 0xc1c0, 0xc11c, 0xc1ff, 0xc11c, 0x21, 0 + .dw 0xc240, 0xc11c, 0xc27f, 0xc11c, 0x21, 0 + .dw 0xc2c0, 0xc11c, 0xc2ff, 0xc11c, 0x21, 0 + .dw 0xc340, 0xc11c, 0xc37f, 0xc11c, 0x21, 0 + .dw 0xc3c0, 0xc11c, 0xc3ff, 0xc11c, 0x21, 0 + .dw 0xc440, 0xc11c, 0xc47f, 0xc11c, 0x21, 0 + .dw 0xc4c0, 0xc11c, 0xc4ff, 0xc11c, 0x21, 0 + .dw 0xc540, 0xc11c, 0xc57f, 0xc11c, 0x21, 0 + .dw 0xc5c0, 0xc11c, 0xc5ff, 0xc11c, 0x21, 0 + .dw 0xc640, 0xc11c, 0xc67f, 0xc11c, 0x21, 0 + .dw 0xc6c0, 0xc11c, 0xc6ff, 0xc11c, 0x21, 0 + .dw 0xc740, 0xc11c, 0xc77f, 0xc11c, 0x21, 0 + .dw 0xc7c0, 0xc11c, 0xc7ff, 0xc11c, 0x21, 0 + .dw 0xc840, 0xc11c, 0xc87f, 0xc11c, 0x21, 0 + .dw 0xc8c0, 0xc11c, 0xc8ff, 0xc11c, 0x21, 0 + .dw 0xc940, 0xc11c, 0xc97f, 0xc11c, 0x21, 0 + .dw 0xc9c0, 0xc11c, 0xc9ff, 0xc11c, 0x21, 0 + .dw 0xca40, 0xc11c, 0xca7f, 0xc11c, 0x21, 0 + .dw 0xcac0, 0xc11c, 0xcaff, 0xc11c, 0x21, 0 + .dw 0xcb40, 0xc11c, 0xcb7f, 0xc11c, 0x21, 0 + .dw 0xcbc0, 0xc11c, 0xcbff, 0xc11c, 0x21, 0 + .dw 0xcc40, 0xc11c, 0xcc7f, 0xc11c, 0x21, 0 + .dw 0xccc0, 0xc11c, 0xccff, 0xc11c, 0x21, 0 + .dw 0xcd40, 0xc11c, 0xcd7f, 0xc11c, 0x21, 0 + .dw 0xcdc0, 0xc11c, 0xcdff, 0xc11c, 0x21, 0 + .dw 0xce40, 0xc11c, 0xce7f, 0xc11c, 0x21, 0 + .dw 0xcec0, 0xc11c, 0xceff, 0xc11c, 0x21, 0 + .dw 0xcf40, 0xc11c, 0xcf7f, 0xc11c, 0x21, 0 + .dw 0xcfc0, 0xc11c, 0xcfff, 0xc11c, 0x21, 0 + .dw 0xd040, 0xc11c, 0xd07f, 0xc11c, 0x21, 0 + .dw 0xd0c0, 0xc11c, 0xd0ff, 0xc11c, 0x21, 0 + .dw 0xd140, 0xc11c, 0xd17f, 0xc11c, 0x21, 0 + .dw 0xd1c0, 0xc11c, 0xd1ff, 0xc11c, 0x21, 0 + .dw 0xd240, 0xc11c, 0xd27f, 0xc11c, 0x21, 0 + .dw 0xd2c0, 0xc11c, 0xd2ff, 0xc11c, 0x21, 0 + .dw 0xd340, 0xc11c, 0xd37f, 0xc11c, 0x21, 0 + .dw 0xd3c0, 0xc11c, 0xd3ff, 0xc11c, 0x21, 0 + .dw 0xd440, 0xc11c, 0xd47f, 0xc11c, 0x21, 0 + .dw 0xd4c0, 0xc11c, 0xd4ff, 0xc11c, 0x21, 0 + .dw 0xd540, 0xc11c, 0xd57f, 0xc11c, 0x21, 0 + .dw 0xd5c0, 0xc11c, 0xd5ff, 0xc11c, 0x21, 0 + .dw 0xd640, 0xc11c, 0xd67f, 0xc11c, 0x21, 0 + .dw 0xd6c0, 0xc11c, 0xd6ff, 0xc11c, 0x21, 0 + .dw 0xd740, 0xc11c, 0xd77f, 0xc11c, 0x21, 0 + .dw 0xd7c0, 0xc11c, 0xd7ff, 0xc11c, 0x21, 0 + .dw 0xd840, 0xc11c, 0xd87f, 0xc11c, 0x21, 0 + .dw 0xd8c0, 0xc11c, 0xd8ff, 0xc11c, 0x21, 0 + .dw 0xd940, 0xc11c, 0xd97f, 0xc11c, 0x21, 0 + .dw 0xd9c0, 0xc11c, 0xdfff, 0xc11c, 0x21, 0 + .dw 0xe040, 0xc11c, 0xe07f, 0xc11c, 0x21, 0 + .dw 0xe0c0, 0xc11c, 0xe0ff, 0xc11c, 0x21, 0 + .dw 0xe140, 0xc11c, 0xe17f, 0xc11c, 0x21, 0 + .dw 0xe1c0, 0xc11c, 0xe1ff, 0xc11c, 0x21, 0 + .dw 0xe240, 0xc11c, 0xe27f, 0xc11c, 0x21, 0 + .dw 0xe2c0, 0xc11c, 0xe2ff, 0xc11c, 0x21, 0 + .dw 0xe340, 0xc11c, 0xe37f, 0xc11c, 0x21, 0 + .dw 0xe3c0, 0xc11c, 0xe3ff, 0xc11c, 0x21, 0 + .dw 0xe440, 0xc11c, 0xe47f, 0xc11c, 0x21, 0 + .dw 0xe4c0, 0xc11c, 0xe4ff, 0xc11c, 0x21, 0 + .dw 0xe540, 0xc11c, 0xe57f, 0xc11c, 0x21, 0 + .dw 0xe5c0, 0xc11c, 0xe5ff, 0xc11c, 0x21, 0 + .dw 0xe640, 0xc11c, 0xe67f, 0xc11c, 0x21, 0 + .dw 0xe6c0, 0xc11c, 0xe6ff, 0xc11c, 0x21, 0 + .dw 0xe740, 0xc11c, 0xe77f, 0xc11c, 0x21, 0 + .dw 0xe7c0, 0xc11c, 0xe7ff, 0xc11c, 0x21, 0 + .dw 0xe840, 0xc11c, 0xe87f, 0xc11c, 0x21, 0 + .dw 0xe8c0, 0xc11c, 0xe8ff, 0xc11c, 0x21, 0 + .dw 0xe940, 0xc11c, 0xe97f, 0xc11c, 0x21, 0 + .dw 0xe9c0, 0xc11c, 0xe9ff, 0xc11c, 0x21, 0 + .dw 0xea40, 0xc11c, 0xea7f, 0xc11c, 0x21, 0 + .dw 0xeac0, 0xc11c, 0xeaff, 0xc11c, 0x21, 0 + .dw 0xeb40, 0xc11c, 0xeb7f, 0xc11c, 0x21, 0 + .dw 0xebc0, 0xc11c, 0xebff, 0xc11c, 0x21, 0 + .dw 0xec40, 0xc11c, 0xec7f, 0xc11c, 0x21, 0 + .dw 0xecc0, 0xc11c, 0xecff, 0xc11c, 0x21, 0 + .dw 0xed40, 0xc11c, 0xed7f, 0xc11c, 0x21, 0 + .dw 0xedc0, 0xc11c, 0xedff, 0xc11c, 0x21, 0 + .dw 0xee40, 0xc11c, 0xee7f, 0xc11c, 0x21, 0 + .dw 0xeec0, 0xc11c, 0xeeff, 0xc11c, 0x21, 0 + .dw 0xef40, 0xc11c, 0xef7f, 0xc11c, 0x21, 0 + .dw 0xefc0, 0xc11c, 0xefff, 0xc11c, 0x21, 0 + .dw 0xf040, 0xc11c, 0xf07f, 0xc11c, 0x21, 0 + .dw 0xf0c0, 0xc11c, 0xf0ff, 0xc11c, 0x21, 0 + .dw 0xf140, 0xc11c, 0xf17f, 0xc11c, 0x21, 0 + .dw 0xf1c0, 0xc11c, 0xf1ff, 0xc11c, 0x21, 0 + .dw 0xf240, 0xc11c, 0xf27f, 0xc11c, 0x21, 0 + .dw 0xf2c0, 0xc11c, 0xf2ff, 0xc11c, 0x21, 0 + .dw 0xf340, 0xc11c, 0xf37f, 0xc11c, 0x21, 0 + .dw 0xf3c0, 0xc11c, 0xf3ff, 0xc11c, 0x21, 0 + .dw 0xf440, 0xc11c, 0xf47f, 0xc11c, 0x21, 0 + .dw 0xf4c0, 0xc11c, 0xf4ff, 0xc11c, 0x21, 0 + .dw 0xf540, 0xc11c, 0xf57f, 0xc11c, 0x21, 0 + .dw 0xf5c0, 0xc11c, 0xf5ff, 0xc11c, 0x21, 0 + .dw 0xf640, 0xc11c, 0xf67f, 0xc11c, 0x21, 0 + .dw 0xf6c0, 0xc11c, 0xf6ff, 0xc11c, 0x21, 0 + .dw 0xf740, 0xc11c, 0xf77f, 0xc11c, 0x21, 0 + .dw 0xf7c0, 0xc11c, 0xf7ff, 0xc11c, 0x21, 0 + .dw 0xf840, 0xc11c, 0xf87f, 0xc11c, 0x21, 0 + .dw 0xf8c0, 0xc11c, 0xf8ff, 0xc11c, 0x21, 0 + .dw 0xf940, 0xc11c, 0xf97f, 0xc11c, 0x21, 0 + .dw 0xf9c0, 0xc11c, 0xffff, 0xc11c, 0x21, 0 + .dw 0x0040, 0xc11d, 0x007f, 0xc11d, 0x21, 0 + .dw 0x00c0, 0xc11d, 0x00ff, 0xc11d, 0x21, 0 + .dw 0x0140, 0xc11d, 0x017f, 0xc11d, 0x21, 0 + .dw 0x01c0, 0xc11d, 0x01ff, 0xc11d, 0x21, 0 + .dw 0x0240, 0xc11d, 0x027f, 0xc11d, 0x21, 0 + .dw 0x02c0, 0xc11d, 0x02ff, 0xc11d, 0x21, 0 + .dw 0x0340, 0xc11d, 0x037f, 0xc11d, 0x21, 0 + .dw 0x03c0, 0xc11d, 0x03ff, 0xc11d, 0x21, 0 + .dw 0x0440, 0xc11d, 0x047f, 0xc11d, 0x21, 0 + .dw 0x04c0, 0xc11d, 0x04ff, 0xc11d, 0x21, 0 + .dw 0x0540, 0xc11d, 0x057f, 0xc11d, 0x21, 0 + .dw 0x05c0, 0xc11d, 0x05ff, 0xc11d, 0x21, 0 + .dw 0x0640, 0xc11d, 0x067f, 0xc11d, 0x21, 0 + .dw 0x06c0, 0xc11d, 0x06ff, 0xc11d, 0x21, 0 + .dw 0x0740, 0xc11d, 0x077f, 0xc11d, 0x21, 0 + .dw 0x07c0, 0xc11d, 0x07ff, 0xc11d, 0x21, 0 + .dw 0x0840, 0xc11d, 0x087f, 0xc11d, 0x21, 0 + .dw 0x08c0, 0xc11d, 0x08ff, 0xc11d, 0x21, 0 + .dw 0x0940, 0xc11d, 0x097f, 0xc11d, 0x21, 0 + .dw 0x09c0, 0xc11d, 0x09ff, 0xc11d, 0x21, 0 + .dw 0x0a40, 0xc11d, 0x0a7f, 0xc11d, 0x21, 0 + .dw 0x0ac0, 0xc11d, 0x0aff, 0xc11d, 0x21, 0 + .dw 0x0b40, 0xc11d, 0x0b7f, 0xc11d, 0x21, 0 + .dw 0x0bc0, 0xc11d, 0x0bff, 0xc11d, 0x21, 0 + .dw 0x0c40, 0xc11d, 0x0c7f, 0xc11d, 0x21, 0 + .dw 0x0cc0, 0xc11d, 0x0cff, 0xc11d, 0x21, 0 + .dw 0x0d40, 0xc11d, 0x0d7f, 0xc11d, 0x21, 0 + .dw 0x0dc0, 0xc11d, 0x0dff, 0xc11d, 0x21, 0 + .dw 0x0e40, 0xc11d, 0x0e7f, 0xc11d, 0x21, 0 + .dw 0x0ec0, 0xc11d, 0x0eff, 0xc11d, 0x21, 0 + .dw 0x0f40, 0xc11d, 0x0f7f, 0xc11d, 0x21, 0 + .dw 0x0fc0, 0xc11d, 0x0fff, 0xc11d, 0x21, 0 + .dw 0x1040, 0xc11d, 0x107f, 0xc11d, 0x21, 0 + .dw 0x10c0, 0xc11d, 0x10ff, 0xc11d, 0x21, 0 + .dw 0x1140, 0xc11d, 0x117f, 0xc11d, 0x21, 0 + .dw 0x11c0, 0xc11d, 0x11ff, 0xc11d, 0x21, 0 + .dw 0x1240, 0xc11d, 0x127f, 0xc11d, 0x21, 0 + .dw 0x12c0, 0xc11d, 0x12ff, 0xc11d, 0x21, 0 + .dw 0x1340, 0xc11d, 0x137f, 0xc11d, 0x21, 0 + .dw 0x13c0, 0xc11d, 0x13ff, 0xc11d, 0x21, 0 + .dw 0x1440, 0xc11d, 0x147f, 0xc11d, 0x21, 0 + .dw 0x14c0, 0xc11d, 0x14ff, 0xc11d, 0x21, 0 + .dw 0x1540, 0xc11d, 0x157f, 0xc11d, 0x21, 0 + .dw 0x15c0, 0xc11d, 0x15ff, 0xc11d, 0x21, 0 + .dw 0x1640, 0xc11d, 0x167f, 0xc11d, 0x21, 0 + .dw 0x16c0, 0xc11d, 0x16ff, 0xc11d, 0x21, 0 + .dw 0x1740, 0xc11d, 0x177f, 0xc11d, 0x21, 0 + .dw 0x17c0, 0xc11d, 0x17ff, 0xc11d, 0x21, 0 + .dw 0x1840, 0xc11d, 0x187f, 0xc11d, 0x21, 0 + .dw 0x18c0, 0xc11d, 0x18ff, 0xc11d, 0x21, 0 + .dw 0x1940, 0xc11d, 0x197f, 0xc11d, 0x21, 0 + .dw 0x19c0, 0xc11d, 0x1fff, 0xc11d, 0x21, 0 + .dw 0x2040, 0xc11d, 0x207f, 0xc11d, 0x21, 0 + .dw 0x20c0, 0xc11d, 0x20ff, 0xc11d, 0x21, 0 + .dw 0x2140, 0xc11d, 0x217f, 0xc11d, 0x21, 0 + .dw 0x21c0, 0xc11d, 0x21ff, 0xc11d, 0x21, 0 + .dw 0x2240, 0xc11d, 0x227f, 0xc11d, 0x21, 0 + .dw 0x22c0, 0xc11d, 0x22ff, 0xc11d, 0x21, 0 + .dw 0x2340, 0xc11d, 0x237f, 0xc11d, 0x21, 0 + .dw 0x23c0, 0xc11d, 0x23ff, 0xc11d, 0x21, 0 + .dw 0x2440, 0xc11d, 0x247f, 0xc11d, 0x21, 0 + .dw 0x24c0, 0xc11d, 0x24ff, 0xc11d, 0x21, 0 + .dw 0x2540, 0xc11d, 0x257f, 0xc11d, 0x21, 0 + .dw 0x25c0, 0xc11d, 0x25ff, 0xc11d, 0x21, 0 + .dw 0x2640, 0xc11d, 0x267f, 0xc11d, 0x21, 0 + .dw 0x26c0, 0xc11d, 0x26ff, 0xc11d, 0x21, 0 + .dw 0x2740, 0xc11d, 0x277f, 0xc11d, 0x21, 0 + .dw 0x27c0, 0xc11d, 0x27ff, 0xc11d, 0x21, 0 + .dw 0x2840, 0xc11d, 0x287f, 0xc11d, 0x21, 0 + .dw 0x28c0, 0xc11d, 0x28ff, 0xc11d, 0x21, 0 + .dw 0x2940, 0xc11d, 0x297f, 0xc11d, 0x21, 0 + .dw 0x29c0, 0xc11d, 0x29ff, 0xc11d, 0x21, 0 + .dw 0x2a40, 0xc11d, 0x2a7f, 0xc11d, 0x21, 0 + .dw 0x2ac0, 0xc11d, 0x2aff, 0xc11d, 0x21, 0 + .dw 0x2b40, 0xc11d, 0x2b7f, 0xc11d, 0x21, 0 + .dw 0x2bc0, 0xc11d, 0x2bff, 0xc11d, 0x21, 0 + .dw 0x2c40, 0xc11d, 0x2c7f, 0xc11d, 0x21, 0 + .dw 0x2cc0, 0xc11d, 0x2cff, 0xc11d, 0x21, 0 + .dw 0x2d40, 0xc11d, 0x2d7f, 0xc11d, 0x21, 0 + .dw 0x2dc0, 0xc11d, 0x2dff, 0xc11d, 0x21, 0 + .dw 0x2e40, 0xc11d, 0x2e7f, 0xc11d, 0x21, 0 + .dw 0x2ec0, 0xc11d, 0x2eff, 0xc11d, 0x21, 0 + .dw 0x2f40, 0xc11d, 0x2f7f, 0xc11d, 0x21, 0 + .dw 0x2fc0, 0xc11d, 0x2fff, 0xc11d, 0x21, 0 + .dw 0x3040, 0xc11d, 0x307f, 0xc11d, 0x21, 0 + .dw 0x30c0, 0xc11d, 0x30ff, 0xc11d, 0x21, 0 + .dw 0x3140, 0xc11d, 0x317f, 0xc11d, 0x21, 0 + .dw 0x31c0, 0xc11d, 0x31ff, 0xc11d, 0x21, 0 + .dw 0x3240, 0xc11d, 0x327f, 0xc11d, 0x21, 0 + .dw 0x32c0, 0xc11d, 0x32ff, 0xc11d, 0x21, 0 + .dw 0x3340, 0xc11d, 0x337f, 0xc11d, 0x21, 0 + .dw 0x33c0, 0xc11d, 0x33ff, 0xc11d, 0x21, 0 + .dw 0x3440, 0xc11d, 0x347f, 0xc11d, 0x21, 0 + .dw 0x34c0, 0xc11d, 0x34ff, 0xc11d, 0x21, 0 + .dw 0x3540, 0xc11d, 0x357f, 0xc11d, 0x21, 0 + .dw 0x35c0, 0xc11d, 0x35ff, 0xc11d, 0x21, 0 + .dw 0x3640, 0xc11d, 0x367f, 0xc11d, 0x21, 0 + .dw 0x36c0, 0xc11d, 0x36ff, 0xc11d, 0x21, 0 + .dw 0x3740, 0xc11d, 0x377f, 0xc11d, 0x21, 0 + .dw 0x37c0, 0xc11d, 0x37ff, 0xc11d, 0x21, 0 + .dw 0x3840, 0xc11d, 0x387f, 0xc11d, 0x21, 0 + .dw 0x38c0, 0xc11d, 0x38ff, 0xc11d, 0x21, 0 + .dw 0x3940, 0xc11d, 0x397f, 0xc11d, 0x21, 0 + .dw 0x39c0, 0xc11d, 0x3fff, 0xc11d, 0x21, 0 + .dw 0x4040, 0xc11d, 0x407f, 0xc11d, 0x21, 0 + .dw 0x40c0, 0xc11d, 0x40ff, 0xc11d, 0x21, 0 + .dw 0x4140, 0xc11d, 0x417f, 0xc11d, 0x21, 0 + .dw 0x41c0, 0xc11d, 0x41ff, 0xc11d, 0x21, 0 + .dw 0x4240, 0xc11d, 0x427f, 0xc11d, 0x21, 0 + .dw 0x42c0, 0xc11d, 0x42ff, 0xc11d, 0x21, 0 + .dw 0x4340, 0xc11d, 0x437f, 0xc11d, 0x21, 0 + .dw 0x43c0, 0xc11d, 0x43ff, 0xc11d, 0x21, 0 + .dw 0x4440, 0xc11d, 0x447f, 0xc11d, 0x21, 0 + .dw 0x44c0, 0xc11d, 0x44ff, 0xc11d, 0x21, 0 + .dw 0x4540, 0xc11d, 0x457f, 0xc11d, 0x21, 0 + .dw 0x45c0, 0xc11d, 0x45ff, 0xc11d, 0x21, 0 + .dw 0x4640, 0xc11d, 0x467f, 0xc11d, 0x21, 0 + .dw 0x46c0, 0xc11d, 0x46ff, 0xc11d, 0x21, 0 + .dw 0x4740, 0xc11d, 0x477f, 0xc11d, 0x21, 0 + .dw 0x47c0, 0xc11d, 0x47ff, 0xc11d, 0x21, 0 + .dw 0x4840, 0xc11d, 0x487f, 0xc11d, 0x21, 0 + .dw 0x48c0, 0xc11d, 0x48ff, 0xc11d, 0x21, 0 + .dw 0x4940, 0xc11d, 0x497f, 0xc11d, 0x21, 0 + .dw 0x49c0, 0xc11d, 0x49ff, 0xc11d, 0x21, 0 + .dw 0x4a40, 0xc11d, 0x4a7f, 0xc11d, 0x21, 0 + .dw 0x4ac0, 0xc11d, 0x4aff, 0xc11d, 0x21, 0 + .dw 0x4b40, 0xc11d, 0x4b7f, 0xc11d, 0x21, 0 + .dw 0x4bc0, 0xc11d, 0x4bff, 0xc11d, 0x21, 0 + .dw 0x4c40, 0xc11d, 0x4c7f, 0xc11d, 0x21, 0 + .dw 0x4cc0, 0xc11d, 0x4cff, 0xc11d, 0x21, 0 + .dw 0x4d40, 0xc11d, 0x4d7f, 0xc11d, 0x21, 0 + .dw 0x4dc0, 0xc11d, 0x4dff, 0xc11d, 0x21, 0 + .dw 0x4e40, 0xc11d, 0x4e7f, 0xc11d, 0x21, 0 + .dw 0x4ec0, 0xc11d, 0x4eff, 0xc11d, 0x21, 0 + .dw 0x4f40, 0xc11d, 0x4f7f, 0xc11d, 0x21, 0 + .dw 0x4fc0, 0xc11d, 0x4fff, 0xc11d, 0x21, 0 + .dw 0x5040, 0xc11d, 0x507f, 0xc11d, 0x21, 0 + .dw 0x50c0, 0xc11d, 0x50ff, 0xc11d, 0x21, 0 + .dw 0x5140, 0xc11d, 0x517f, 0xc11d, 0x21, 0 + .dw 0x51c0, 0xc11d, 0x51ff, 0xc11d, 0x21, 0 + .dw 0x5240, 0xc11d, 0x527f, 0xc11d, 0x21, 0 + .dw 0x52c0, 0xc11d, 0x52ff, 0xc11d, 0x21, 0 + .dw 0x5340, 0xc11d, 0x537f, 0xc11d, 0x21, 0 + .dw 0x53c0, 0xc11d, 0x53ff, 0xc11d, 0x21, 0 + .dw 0x5440, 0xc11d, 0x547f, 0xc11d, 0x21, 0 + .dw 0x54c0, 0xc11d, 0x54ff, 0xc11d, 0x21, 0 + .dw 0x5540, 0xc11d, 0x557f, 0xc11d, 0x21, 0 + .dw 0x55c0, 0xc11d, 0x55ff, 0xc11d, 0x21, 0 + .dw 0x5640, 0xc11d, 0x567f, 0xc11d, 0x21, 0 + .dw 0x56c0, 0xc11d, 0x56ff, 0xc11d, 0x21, 0 + .dw 0x5740, 0xc11d, 0x577f, 0xc11d, 0x21, 0 + .dw 0x57c0, 0xc11d, 0x57ff, 0xc11d, 0x21, 0 + .dw 0x5840, 0xc11d, 0x587f, 0xc11d, 0x21, 0 + .dw 0x58c0, 0xc11d, 0x58ff, 0xc11d, 0x21, 0 + .dw 0x5940, 0xc11d, 0x597f, 0xc11d, 0x21, 0 + .dw 0x59c0, 0xc11d, 0x5fff, 0xc11d, 0x21, 0 + .dw 0x6040, 0xc11d, 0x607f, 0xc11d, 0x21, 0 + .dw 0x60c0, 0xc11d, 0x60ff, 0xc11d, 0x21, 0 + .dw 0x6140, 0xc11d, 0x617f, 0xc11d, 0x21, 0 + .dw 0x61c0, 0xc11d, 0x61ff, 0xc11d, 0x21, 0 + .dw 0x6240, 0xc11d, 0x627f, 0xc11d, 0x21, 0 + .dw 0x62c0, 0xc11d, 0x62ff, 0xc11d, 0x21, 0 + .dw 0x6340, 0xc11d, 0x637f, 0xc11d, 0x21, 0 + .dw 0x63c0, 0xc11d, 0x63ff, 0xc11d, 0x21, 0 + .dw 0x6440, 0xc11d, 0x647f, 0xc11d, 0x21, 0 + .dw 0x64c0, 0xc11d, 0x64ff, 0xc11d, 0x21, 0 + .dw 0x6540, 0xc11d, 0x657f, 0xc11d, 0x21, 0 + .dw 0x65c0, 0xc11d, 0x65ff, 0xc11d, 0x21, 0 + .dw 0x6640, 0xc11d, 0x667f, 0xc11d, 0x21, 0 + .dw 0x66c0, 0xc11d, 0x66ff, 0xc11d, 0x21, 0 + .dw 0x6740, 0xc11d, 0x677f, 0xc11d, 0x21, 0 + .dw 0x67c0, 0xc11d, 0x67ff, 0xc11d, 0x21, 0 + .dw 0x6840, 0xc11d, 0x687f, 0xc11d, 0x21, 0 + .dw 0x68c0, 0xc11d, 0x68ff, 0xc11d, 0x21, 0 + .dw 0x6940, 0xc11d, 0x697f, 0xc11d, 0x21, 0 + .dw 0x69c0, 0xc11d, 0x69ff, 0xc11d, 0x21, 0 + .dw 0x6a40, 0xc11d, 0x6a7f, 0xc11d, 0x21, 0 + .dw 0x6ac0, 0xc11d, 0x6aff, 0xc11d, 0x21, 0 + .dw 0x6b40, 0xc11d, 0x6b7f, 0xc11d, 0x21, 0 + .dw 0x6bc0, 0xc11d, 0x6bff, 0xc11d, 0x21, 0 + .dw 0x6c40, 0xc11d, 0x6c7f, 0xc11d, 0x21, 0 + .dw 0x6cc0, 0xc11d, 0x6cff, 0xc11d, 0x21, 0 + .dw 0x6d40, 0xc11d, 0x6d7f, 0xc11d, 0x21, 0 + .dw 0x6dc0, 0xc11d, 0x6dff, 0xc11d, 0x21, 0 + .dw 0x6e40, 0xc11d, 0x6e7f, 0xc11d, 0x21, 0 + .dw 0x6ec0, 0xc11d, 0x6eff, 0xc11d, 0x21, 0 + .dw 0x6f40, 0xc11d, 0x6f7f, 0xc11d, 0x21, 0 + .dw 0x6fc0, 0xc11d, 0x6fff, 0xc11d, 0x21, 0 + .dw 0x7040, 0xc11d, 0x707f, 0xc11d, 0x21, 0 + .dw 0x70c0, 0xc11d, 0x70ff, 0xc11d, 0x21, 0 + .dw 0x7140, 0xc11d, 0x717f, 0xc11d, 0x21, 0 + .dw 0x71c0, 0xc11d, 0x71ff, 0xc11d, 0x21, 0 + .dw 0x7240, 0xc11d, 0x727f, 0xc11d, 0x21, 0 + .dw 0x72c0, 0xc11d, 0x72ff, 0xc11d, 0x21, 0 + .dw 0x7340, 0xc11d, 0x737f, 0xc11d, 0x21, 0 + .dw 0x73c0, 0xc11d, 0x73ff, 0xc11d, 0x21, 0 + .dw 0x7440, 0xc11d, 0x747f, 0xc11d, 0x21, 0 + .dw 0x74c0, 0xc11d, 0x74ff, 0xc11d, 0x21, 0 + .dw 0x7540, 0xc11d, 0x757f, 0xc11d, 0x21, 0 + .dw 0x75c0, 0xc11d, 0x75ff, 0xc11d, 0x21, 0 + .dw 0x7640, 0xc11d, 0x767f, 0xc11d, 0x21, 0 + .dw 0x76c0, 0xc11d, 0x76ff, 0xc11d, 0x21, 0 + .dw 0x7740, 0xc11d, 0x777f, 0xc11d, 0x21, 0 + .dw 0x77c0, 0xc11d, 0x77ff, 0xc11d, 0x21, 0 + .dw 0x7840, 0xc11d, 0x787f, 0xc11d, 0x21, 0 + .dw 0x78c0, 0xc11d, 0x78ff, 0xc11d, 0x21, 0 + .dw 0x7940, 0xc11d, 0x797f, 0xc11d, 0x21, 0 + .dw 0x79c0, 0xc11d, 0x7fff, 0xc11d, 0x21, 0 + .dw 0x8040, 0xc11d, 0x807f, 0xc11d, 0x21, 0 + .dw 0x80c0, 0xc11d, 0x80ff, 0xc11d, 0x21, 0 + .dw 0x8140, 0xc11d, 0x817f, 0xc11d, 0x21, 0 + .dw 0x81c0, 0xc11d, 0x81ff, 0xc11d, 0x21, 0 + .dw 0x8240, 0xc11d, 0x827f, 0xc11d, 0x21, 0 + .dw 0x82c0, 0xc11d, 0x82ff, 0xc11d, 0x21, 0 + .dw 0x8340, 0xc11d, 0x837f, 0xc11d, 0x21, 0 + .dw 0x83c0, 0xc11d, 0x83ff, 0xc11d, 0x21, 0 + .dw 0x8440, 0xc11d, 0x847f, 0xc11d, 0x21, 0 + .dw 0x84c0, 0xc11d, 0x84ff, 0xc11d, 0x21, 0 + .dw 0x8540, 0xc11d, 0x857f, 0xc11d, 0x21, 0 + .dw 0x85c0, 0xc11d, 0x85ff, 0xc11d, 0x21, 0 + .dw 0x8640, 0xc11d, 0x867f, 0xc11d, 0x21, 0 + .dw 0x86c0, 0xc11d, 0x86ff, 0xc11d, 0x21, 0 + .dw 0x8740, 0xc11d, 0x877f, 0xc11d, 0x21, 0 + .dw 0x87c0, 0xc11d, 0x87ff, 0xc11d, 0x21, 0 + .dw 0x8840, 0xc11d, 0x887f, 0xc11d, 0x21, 0 + .dw 0x88c0, 0xc11d, 0x88ff, 0xc11d, 0x21, 0 + .dw 0x8940, 0xc11d, 0x897f, 0xc11d, 0x21, 0 + .dw 0x89c0, 0xc11d, 0x89ff, 0xc11d, 0x21, 0 + .dw 0x8a40, 0xc11d, 0x8a7f, 0xc11d, 0x21, 0 + .dw 0x8ac0, 0xc11d, 0x8aff, 0xc11d, 0x21, 0 + .dw 0x8b40, 0xc11d, 0x8b7f, 0xc11d, 0x21, 0 + .dw 0x8bc0, 0xc11d, 0x8bff, 0xc11d, 0x21, 0 + .dw 0x8c40, 0xc11d, 0x8c7f, 0xc11d, 0x21, 0 + .dw 0x8cc0, 0xc11d, 0x8cff, 0xc11d, 0x21, 0 + .dw 0x8d40, 0xc11d, 0x8d7f, 0xc11d, 0x21, 0 + .dw 0x8dc0, 0xc11d, 0x8dff, 0xc11d, 0x21, 0 + .dw 0x8e40, 0xc11d, 0x8e7f, 0xc11d, 0x21, 0 + .dw 0x8ec0, 0xc11d, 0x8eff, 0xc11d, 0x21, 0 + .dw 0x8f40, 0xc11d, 0x8f7f, 0xc11d, 0x21, 0 + .dw 0x8fc0, 0xc11d, 0x8fff, 0xc11d, 0x21, 0 + .dw 0x9040, 0xc11d, 0x907f, 0xc11d, 0x21, 0 + .dw 0x90c0, 0xc11d, 0x90ff, 0xc11d, 0x21, 0 + .dw 0x9140, 0xc11d, 0x917f, 0xc11d, 0x21, 0 + .dw 0x91c0, 0xc11d, 0x91ff, 0xc11d, 0x21, 0 + .dw 0x9240, 0xc11d, 0x927f, 0xc11d, 0x21, 0 + .dw 0x92c0, 0xc11d, 0x92ff, 0xc11d, 0x21, 0 + .dw 0x9340, 0xc11d, 0x937f, 0xc11d, 0x21, 0 + .dw 0x93c0, 0xc11d, 0x93ff, 0xc11d, 0x21, 0 + .dw 0x9440, 0xc11d, 0x947f, 0xc11d, 0x21, 0 + .dw 0x94c0, 0xc11d, 0x94ff, 0xc11d, 0x21, 0 + .dw 0x9540, 0xc11d, 0x957f, 0xc11d, 0x21, 0 + .dw 0x95c0, 0xc11d, 0x95ff, 0xc11d, 0x21, 0 + .dw 0x9640, 0xc11d, 0x967f, 0xc11d, 0x21, 0 + .dw 0x96c0, 0xc11d, 0x96ff, 0xc11d, 0x21, 0 + .dw 0x9740, 0xc11d, 0x977f, 0xc11d, 0x21, 0 + .dw 0x97c0, 0xc11d, 0x97ff, 0xc11d, 0x21, 0 + .dw 0x9840, 0xc11d, 0x987f, 0xc11d, 0x21, 0 + .dw 0x98c0, 0xc11d, 0x98ff, 0xc11d, 0x21, 0 + .dw 0x9940, 0xc11d, 0x997f, 0xc11d, 0x21, 0 + .dw 0x99c0, 0xc11d, 0x9fff, 0xc11d, 0x21, 0 + .dw 0xa040, 0xc11d, 0xa07f, 0xc11d, 0x21, 0 + .dw 0xa0c0, 0xc11d, 0xa0ff, 0xc11d, 0x21, 0 + .dw 0xa140, 0xc11d, 0xa17f, 0xc11d, 0x21, 0 + .dw 0xa1c0, 0xc11d, 0xa1ff, 0xc11d, 0x21, 0 + .dw 0xa240, 0xc11d, 0xa27f, 0xc11d, 0x21, 0 + .dw 0xa2c0, 0xc11d, 0xa2ff, 0xc11d, 0x21, 0 + .dw 0xa340, 0xc11d, 0xa37f, 0xc11d, 0x21, 0 + .dw 0xa3c0, 0xc11d, 0xa3ff, 0xc11d, 0x21, 0 + .dw 0xa440, 0xc11d, 0xa47f, 0xc11d, 0x21, 0 + .dw 0xa4c0, 0xc11d, 0xa4ff, 0xc11d, 0x21, 0 + .dw 0xa540, 0xc11d, 0xa57f, 0xc11d, 0x21, 0 + .dw 0xa5c0, 0xc11d, 0xa5ff, 0xc11d, 0x21, 0 + .dw 0xa640, 0xc11d, 0xa67f, 0xc11d, 0x21, 0 + .dw 0xa6c0, 0xc11d, 0xa6ff, 0xc11d, 0x21, 0 + .dw 0xa740, 0xc11d, 0xa77f, 0xc11d, 0x21, 0 + .dw 0xa7c0, 0xc11d, 0xa7ff, 0xc11d, 0x21, 0 + .dw 0xa840, 0xc11d, 0xa87f, 0xc11d, 0x21, 0 + .dw 0xa8c0, 0xc11d, 0xa8ff, 0xc11d, 0x21, 0 + .dw 0xa940, 0xc11d, 0xa97f, 0xc11d, 0x21, 0 + .dw 0xa9c0, 0xc11d, 0xa9ff, 0xc11d, 0x21, 0 + .dw 0xaa40, 0xc11d, 0xaa7f, 0xc11d, 0x21, 0 + .dw 0xaac0, 0xc11d, 0xaaff, 0xc11d, 0x21, 0 + .dw 0xab40, 0xc11d, 0xab7f, 0xc11d, 0x21, 0 + .dw 0xabc0, 0xc11d, 0xabff, 0xc11d, 0x21, 0 + .dw 0xac40, 0xc11d, 0xac7f, 0xc11d, 0x21, 0 + .dw 0xacc0, 0xc11d, 0xacff, 0xc11d, 0x21, 0 + .dw 0xad40, 0xc11d, 0xad7f, 0xc11d, 0x21, 0 + .dw 0xadc0, 0xc11d, 0xadff, 0xc11d, 0x21, 0 + .dw 0xae40, 0xc11d, 0xae7f, 0xc11d, 0x21, 0 + .dw 0xaec0, 0xc11d, 0xaeff, 0xc11d, 0x21, 0 + .dw 0xaf40, 0xc11d, 0xaf7f, 0xc11d, 0x21, 0 + .dw 0xafc0, 0xc11d, 0xafff, 0xc11d, 0x21, 0 + .dw 0xb040, 0xc11d, 0xb07f, 0xc11d, 0x21, 0 + .dw 0xb0c0, 0xc11d, 0xb0ff, 0xc11d, 0x21, 0 + .dw 0xb140, 0xc11d, 0xb17f, 0xc11d, 0x21, 0 + .dw 0xb1c0, 0xc11d, 0xb1ff, 0xc11d, 0x21, 0 + .dw 0xb240, 0xc11d, 0xb27f, 0xc11d, 0x21, 0 + .dw 0xb2c0, 0xc11d, 0xb2ff, 0xc11d, 0x21, 0 + .dw 0xb340, 0xc11d, 0xb37f, 0xc11d, 0x21, 0 + .dw 0xb3c0, 0xc11d, 0xb3ff, 0xc11d, 0x21, 0 + .dw 0xb440, 0xc11d, 0xb47f, 0xc11d, 0x21, 0 + .dw 0xb4c0, 0xc11d, 0xb4ff, 0xc11d, 0x21, 0 + .dw 0xb540, 0xc11d, 0xb57f, 0xc11d, 0x21, 0 + .dw 0xb5c0, 0xc11d, 0xb5ff, 0xc11d, 0x21, 0 + .dw 0xb640, 0xc11d, 0xb67f, 0xc11d, 0x21, 0 + .dw 0xb6c0, 0xc11d, 0xb6ff, 0xc11d, 0x21, 0 + .dw 0xb740, 0xc11d, 0xb77f, 0xc11d, 0x21, 0 + .dw 0xb7c0, 0xc11d, 0xb7ff, 0xc11d, 0x21, 0 + .dw 0xb840, 0xc11d, 0xb87f, 0xc11d, 0x21, 0 + .dw 0xb8c0, 0xc11d, 0xb8ff, 0xc11d, 0x21, 0 + .dw 0xb940, 0xc11d, 0xb97f, 0xc11d, 0x21, 0 + .dw 0xb9c0, 0xc11d, 0xbfff, 0xc11d, 0x21, 0 + .dw 0xc040, 0xc11d, 0xc07f, 0xc11d, 0x21, 0 + .dw 0xc0c0, 0xc11d, 0xc0ff, 0xc11d, 0x21, 0 + .dw 0xc140, 0xc11d, 0xc17f, 0xc11d, 0x21, 0 + .dw 0xc1c0, 0xc11d, 0xc1ff, 0xc11d, 0x21, 0 + .dw 0xc240, 0xc11d, 0xc27f, 0xc11d, 0x21, 0 + .dw 0xc2c0, 0xc11d, 0xc2ff, 0xc11d, 0x21, 0 + .dw 0xc340, 0xc11d, 0xc37f, 0xc11d, 0x21, 0 + .dw 0xc3c0, 0xc11d, 0xc3ff, 0xc11d, 0x21, 0 + .dw 0xc440, 0xc11d, 0xc47f, 0xc11d, 0x21, 0 + .dw 0xc4c0, 0xc11d, 0xc4ff, 0xc11d, 0x21, 0 + .dw 0xc540, 0xc11d, 0xc57f, 0xc11d, 0x21, 0 + .dw 0xc5c0, 0xc11d, 0xc5ff, 0xc11d, 0x21, 0 + .dw 0xc640, 0xc11d, 0xc67f, 0xc11d, 0x21, 0 + .dw 0xc6c0, 0xc11d, 0xc6ff, 0xc11d, 0x21, 0 + .dw 0xc740, 0xc11d, 0xc77f, 0xc11d, 0x21, 0 + .dw 0xc7c0, 0xc11d, 0xc7ff, 0xc11d, 0x21, 0 + .dw 0xc840, 0xc11d, 0xc87f, 0xc11d, 0x21, 0 + .dw 0xc8c0, 0xc11d, 0xc8ff, 0xc11d, 0x21, 0 + .dw 0xc940, 0xc11d, 0xc97f, 0xc11d, 0x21, 0 + .dw 0xc9c0, 0xc11d, 0xc9ff, 0xc11d, 0x21, 0 + .dw 0xca40, 0xc11d, 0xca7f, 0xc11d, 0x21, 0 + .dw 0xcac0, 0xc11d, 0xcaff, 0xc11d, 0x21, 0 + .dw 0xcb40, 0xc11d, 0xcb7f, 0xc11d, 0x21, 0 + .dw 0xcbc0, 0xc11d, 0xcbff, 0xc11d, 0x21, 0 + .dw 0xcc40, 0xc11d, 0xcc7f, 0xc11d, 0x21, 0 + .dw 0xccc0, 0xc11d, 0xccff, 0xc11d, 0x21, 0 + .dw 0xcd40, 0xc11d, 0xcd7f, 0xc11d, 0x21, 0 + .dw 0xcdc0, 0xc11d, 0xcdff, 0xc11d, 0x21, 0 + .dw 0xce40, 0xc11d, 0xce7f, 0xc11d, 0x21, 0 + .dw 0xcec0, 0xc11d, 0xceff, 0xc11d, 0x21, 0 + .dw 0xcf40, 0xc11d, 0xcf7f, 0xc11d, 0x21, 0 + .dw 0xcfc0, 0xc11d, 0xcfff, 0xc11d, 0x21, 0 + .dw 0xd040, 0xc11d, 0xd07f, 0xc11d, 0x21, 0 + .dw 0xd0c0, 0xc11d, 0xd0ff, 0xc11d, 0x21, 0 + .dw 0xd140, 0xc11d, 0xd17f, 0xc11d, 0x21, 0 + .dw 0xd1c0, 0xc11d, 0xd1ff, 0xc11d, 0x21, 0 + .dw 0xd240, 0xc11d, 0xd27f, 0xc11d, 0x21, 0 + .dw 0xd2c0, 0xc11d, 0xd2ff, 0xc11d, 0x21, 0 + .dw 0xd340, 0xc11d, 0xd37f, 0xc11d, 0x21, 0 + .dw 0xd3c0, 0xc11d, 0xd3ff, 0xc11d, 0x21, 0 + .dw 0xd440, 0xc11d, 0xd47f, 0xc11d, 0x21, 0 + .dw 0xd4c0, 0xc11d, 0xd4ff, 0xc11d, 0x21, 0 + .dw 0xd540, 0xc11d, 0xd57f, 0xc11d, 0x21, 0 + .dw 0xd5c0, 0xc11d, 0xd5ff, 0xc11d, 0x21, 0 + .dw 0xd640, 0xc11d, 0xd67f, 0xc11d, 0x21, 0 + .dw 0xd6c0, 0xc11d, 0xd6ff, 0xc11d, 0x21, 0 + .dw 0xd740, 0xc11d, 0xd77f, 0xc11d, 0x21, 0 + .dw 0xd7c0, 0xc11d, 0xd7ff, 0xc11d, 0x21, 0 + .dw 0xd840, 0xc11d, 0xd87f, 0xc11d, 0x21, 0 + .dw 0xd8c0, 0xc11d, 0xd8ff, 0xc11d, 0x21, 0 + .dw 0xd940, 0xc11d, 0xd97f, 0xc11d, 0x21, 0 + .dw 0xd9c0, 0xc11d, 0xdfff, 0xc11d, 0x21, 0 + .dw 0xe040, 0xc11d, 0xe07f, 0xc11d, 0x21, 0 + .dw 0xe0c0, 0xc11d, 0xe0ff, 0xc11d, 0x21, 0 + .dw 0xe140, 0xc11d, 0xe17f, 0xc11d, 0x21, 0 + .dw 0xe1c0, 0xc11d, 0xe1ff, 0xc11d, 0x21, 0 + .dw 0xe240, 0xc11d, 0xe27f, 0xc11d, 0x21, 0 + .dw 0xe2c0, 0xc11d, 0xe2ff, 0xc11d, 0x21, 0 + .dw 0xe340, 0xc11d, 0xe37f, 0xc11d, 0x21, 0 + .dw 0xe3c0, 0xc11d, 0xe3ff, 0xc11d, 0x21, 0 + .dw 0xe440, 0xc11d, 0xe47f, 0xc11d, 0x21, 0 + .dw 0xe4c0, 0xc11d, 0xe4ff, 0xc11d, 0x21, 0 + .dw 0xe540, 0xc11d, 0xe57f, 0xc11d, 0x21, 0 + .dw 0xe5c0, 0xc11d, 0xe5ff, 0xc11d, 0x21, 0 + .dw 0xe640, 0xc11d, 0xe67f, 0xc11d, 0x21, 0 + .dw 0xe6c0, 0xc11d, 0xe6ff, 0xc11d, 0x21, 0 + .dw 0xe740, 0xc11d, 0xe77f, 0xc11d, 0x21, 0 + .dw 0xe7c0, 0xc11d, 0xe7ff, 0xc11d, 0x21, 0 + .dw 0xe840, 0xc11d, 0xe87f, 0xc11d, 0x21, 0 + .dw 0xe8c0, 0xc11d, 0xe8ff, 0xc11d, 0x21, 0 + .dw 0xe940, 0xc11d, 0xe97f, 0xc11d, 0x21, 0 + .dw 0xe9c0, 0xc11d, 0xe9ff, 0xc11d, 0x21, 0 + .dw 0xea40, 0xc11d, 0xea7f, 0xc11d, 0x21, 0 + .dw 0xeac0, 0xc11d, 0xeaff, 0xc11d, 0x21, 0 + .dw 0xeb40, 0xc11d, 0xeb7f, 0xc11d, 0x21, 0 + .dw 0xebc0, 0xc11d, 0xebff, 0xc11d, 0x21, 0 + .dw 0xec40, 0xc11d, 0xec7f, 0xc11d, 0x21, 0 + .dw 0xecc0, 0xc11d, 0xecff, 0xc11d, 0x21, 0 + .dw 0xed40, 0xc11d, 0xed7f, 0xc11d, 0x21, 0 + .dw 0xedc0, 0xc11d, 0xedff, 0xc11d, 0x21, 0 + .dw 0xee40, 0xc11d, 0xee7f, 0xc11d, 0x21, 0 + .dw 0xeec0, 0xc11d, 0xeeff, 0xc11d, 0x21, 0 + .dw 0xef40, 0xc11d, 0xef7f, 0xc11d, 0x21, 0 + .dw 0xefc0, 0xc11d, 0xefff, 0xc11d, 0x21, 0 + .dw 0xf040, 0xc11d, 0xf07f, 0xc11d, 0x21, 0 + .dw 0xf0c0, 0xc11d, 0xf0ff, 0xc11d, 0x21, 0 + .dw 0xf140, 0xc11d, 0xf17f, 0xc11d, 0x21, 0 + .dw 0xf1c0, 0xc11d, 0xf1ff, 0xc11d, 0x21, 0 + .dw 0xf240, 0xc11d, 0xf27f, 0xc11d, 0x21, 0 + .dw 0xf2c0, 0xc11d, 0xf2ff, 0xc11d, 0x21, 0 + .dw 0xf340, 0xc11d, 0xf37f, 0xc11d, 0x21, 0 + .dw 0xf3c0, 0xc11d, 0xf3ff, 0xc11d, 0x21, 0 + .dw 0xf440, 0xc11d, 0xf47f, 0xc11d, 0x21, 0 + .dw 0xf4c0, 0xc11d, 0xf4ff, 0xc11d, 0x21, 0 + .dw 0xf540, 0xc11d, 0xf57f, 0xc11d, 0x21, 0 + .dw 0xf5c0, 0xc11d, 0xf5ff, 0xc11d, 0x21, 0 + .dw 0xf640, 0xc11d, 0xf67f, 0xc11d, 0x21, 0 + .dw 0xf6c0, 0xc11d, 0xf6ff, 0xc11d, 0x21, 0 + .dw 0xf740, 0xc11d, 0xf77f, 0xc11d, 0x21, 0 + .dw 0xf7c0, 0xc11d, 0xf7ff, 0xc11d, 0x21, 0 + .dw 0xf840, 0xc11d, 0xf87f, 0xc11d, 0x21, 0 + .dw 0xf8c0, 0xc11d, 0xf8ff, 0xc11d, 0x21, 0 + .dw 0xf940, 0xc11d, 0xf97f, 0xc11d, 0x21, 0 + .dw 0xf9c0, 0xc11d, 0xffff, 0xc11d, 0x21, 0 + .dw 0x0040, 0xc11e, 0x007f, 0xc11e, 0x21, 0 + .dw 0x00c0, 0xc11e, 0x00ff, 0xc11e, 0x21, 0 + .dw 0x0140, 0xc11e, 0x017f, 0xc11e, 0x21, 0 + .dw 0x01c0, 0xc11e, 0x01ff, 0xc11e, 0x21, 0 + .dw 0x0240, 0xc11e, 0x027f, 0xc11e, 0x21, 0 + .dw 0x02c0, 0xc11e, 0x02ff, 0xc11e, 0x21, 0 + .dw 0x0340, 0xc11e, 0x037f, 0xc11e, 0x21, 0 + .dw 0x03c0, 0xc11e, 0x03ff, 0xc11e, 0x21, 0 + .dw 0x0440, 0xc11e, 0x047f, 0xc11e, 0x21, 0 + .dw 0x04c0, 0xc11e, 0x04ff, 0xc11e, 0x21, 0 + .dw 0x0540, 0xc11e, 0x057f, 0xc11e, 0x21, 0 + .dw 0x05c0, 0xc11e, 0x05ff, 0xc11e, 0x21, 0 + .dw 0x0640, 0xc11e, 0x067f, 0xc11e, 0x21, 0 + .dw 0x06c0, 0xc11e, 0x06ff, 0xc11e, 0x21, 0 + .dw 0x0740, 0xc11e, 0x077f, 0xc11e, 0x21, 0 + .dw 0x07c0, 0xc11e, 0x07ff, 0xc11e, 0x21, 0 + .dw 0x0840, 0xc11e, 0x087f, 0xc11e, 0x21, 0 + .dw 0x08c0, 0xc11e, 0x08ff, 0xc11e, 0x21, 0 + .dw 0x0940, 0xc11e, 0x097f, 0xc11e, 0x21, 0 + .dw 0x09c0, 0xc11e, 0x09ff, 0xc11e, 0x21, 0 + .dw 0x0a40, 0xc11e, 0x0a7f, 0xc11e, 0x21, 0 + .dw 0x0ac0, 0xc11e, 0x0aff, 0xc11e, 0x21, 0 + .dw 0x0b40, 0xc11e, 0x0b7f, 0xc11e, 0x21, 0 + .dw 0x0bc0, 0xc11e, 0x0bff, 0xc11e, 0x21, 0 + .dw 0x0c40, 0xc11e, 0x0c7f, 0xc11e, 0x21, 0 + .dw 0x0cc0, 0xc11e, 0x0cff, 0xc11e, 0x21, 0 + .dw 0x0d40, 0xc11e, 0x0d7f, 0xc11e, 0x21, 0 + .dw 0x0dc0, 0xc11e, 0x0dff, 0xc11e, 0x21, 0 + .dw 0x0e40, 0xc11e, 0x0e7f, 0xc11e, 0x21, 0 + .dw 0x0ec0, 0xc11e, 0x0eff, 0xc11e, 0x21, 0 + .dw 0x0f40, 0xc11e, 0x0f7f, 0xc11e, 0x21, 0 + .dw 0x0fc0, 0xc11e, 0x0fff, 0xc11e, 0x21, 0 + .dw 0x1040, 0xc11e, 0x107f, 0xc11e, 0x21, 0 + .dw 0x10c0, 0xc11e, 0x10ff, 0xc11e, 0x21, 0 + .dw 0x1140, 0xc11e, 0x117f, 0xc11e, 0x21, 0 + .dw 0x11c0, 0xc11e, 0x11ff, 0xc11e, 0x21, 0 + .dw 0x1240, 0xc11e, 0x127f, 0xc11e, 0x21, 0 + .dw 0x12c0, 0xc11e, 0x12ff, 0xc11e, 0x21, 0 + .dw 0x1340, 0xc11e, 0x137f, 0xc11e, 0x21, 0 + .dw 0x13c0, 0xc11e, 0x13ff, 0xc11e, 0x21, 0 + .dw 0x1440, 0xc11e, 0x147f, 0xc11e, 0x21, 0 + .dw 0x14c0, 0xc11e, 0x14ff, 0xc11e, 0x21, 0 + .dw 0x1540, 0xc11e, 0x157f, 0xc11e, 0x21, 0 + .dw 0x15c0, 0xc11e, 0x15ff, 0xc11e, 0x21, 0 + .dw 0x1640, 0xc11e, 0x167f, 0xc11e, 0x21, 0 + .dw 0x16c0, 0xc11e, 0x16ff, 0xc11e, 0x21, 0 + .dw 0x1740, 0xc11e, 0x177f, 0xc11e, 0x21, 0 + .dw 0x17c0, 0xc11e, 0x17ff, 0xc11e, 0x21, 0 + .dw 0x1840, 0xc11e, 0x187f, 0xc11e, 0x21, 0 + .dw 0x18c0, 0xc11e, 0x18ff, 0xc11e, 0x21, 0 + .dw 0x1940, 0xc11e, 0x197f, 0xc11e, 0x21, 0 + .dw 0x19c0, 0xc11e, 0x1fff, 0xc11e, 0x21, 0 + .dw 0x2040, 0xc11e, 0x207f, 0xc11e, 0x21, 0 + .dw 0x20c0, 0xc11e, 0x20ff, 0xc11e, 0x21, 0 + .dw 0x2140, 0xc11e, 0x217f, 0xc11e, 0x21, 0 + .dw 0x21c0, 0xc11e, 0x21ff, 0xc11e, 0x21, 0 + .dw 0x2240, 0xc11e, 0x227f, 0xc11e, 0x21, 0 + .dw 0x22c0, 0xc11e, 0x22ff, 0xc11e, 0x21, 0 + .dw 0x2340, 0xc11e, 0x237f, 0xc11e, 0x21, 0 + .dw 0x23c0, 0xc11e, 0x23ff, 0xc11e, 0x21, 0 + .dw 0x2440, 0xc11e, 0x247f, 0xc11e, 0x21, 0 + .dw 0x24c0, 0xc11e, 0x24ff, 0xc11e, 0x21, 0 + .dw 0x2540, 0xc11e, 0x257f, 0xc11e, 0x21, 0 + .dw 0x25c0, 0xc11e, 0x25ff, 0xc11e, 0x21, 0 + .dw 0x2640, 0xc11e, 0x267f, 0xc11e, 0x21, 0 + .dw 0x26c0, 0xc11e, 0x26ff, 0xc11e, 0x21, 0 + .dw 0x2740, 0xc11e, 0x277f, 0xc11e, 0x21, 0 + .dw 0x27c0, 0xc11e, 0x27ff, 0xc11e, 0x21, 0 + .dw 0x2840, 0xc11e, 0x287f, 0xc11e, 0x21, 0 + .dw 0x28c0, 0xc11e, 0x28ff, 0xc11e, 0x21, 0 + .dw 0x2940, 0xc11e, 0x297f, 0xc11e, 0x21, 0 + .dw 0x29c0, 0xc11e, 0x29ff, 0xc11e, 0x21, 0 + .dw 0x2a40, 0xc11e, 0x2a7f, 0xc11e, 0x21, 0 + .dw 0x2ac0, 0xc11e, 0x2aff, 0xc11e, 0x21, 0 + .dw 0x2b40, 0xc11e, 0x2b7f, 0xc11e, 0x21, 0 + .dw 0x2bc0, 0xc11e, 0x2bff, 0xc11e, 0x21, 0 + .dw 0x2c40, 0xc11e, 0x2c7f, 0xc11e, 0x21, 0 + .dw 0x2cc0, 0xc11e, 0x2cff, 0xc11e, 0x21, 0 + .dw 0x2d40, 0xc11e, 0x2d7f, 0xc11e, 0x21, 0 + .dw 0x2dc0, 0xc11e, 0x2dff, 0xc11e, 0x21, 0 + .dw 0x2e40, 0xc11e, 0x2e7f, 0xc11e, 0x21, 0 + .dw 0x2ec0, 0xc11e, 0x2eff, 0xc11e, 0x21, 0 + .dw 0x2f40, 0xc11e, 0x2f7f, 0xc11e, 0x21, 0 + .dw 0x2fc0, 0xc11e, 0x2fff, 0xc11e, 0x21, 0 + .dw 0x3040, 0xc11e, 0x307f, 0xc11e, 0x21, 0 + .dw 0x30c0, 0xc11e, 0x30ff, 0xc11e, 0x21, 0 + .dw 0x3140, 0xc11e, 0x317f, 0xc11e, 0x21, 0 + .dw 0x31c0, 0xc11e, 0x31ff, 0xc11e, 0x21, 0 + .dw 0x3240, 0xc11e, 0x327f, 0xc11e, 0x21, 0 + .dw 0x32c0, 0xc11e, 0x32ff, 0xc11e, 0x21, 0 + .dw 0x3340, 0xc11e, 0x337f, 0xc11e, 0x21, 0 + .dw 0x33c0, 0xc11e, 0x33ff, 0xc11e, 0x21, 0 + .dw 0x3440, 0xc11e, 0x347f, 0xc11e, 0x21, 0 + .dw 0x34c0, 0xc11e, 0x34ff, 0xc11e, 0x21, 0 + .dw 0x3540, 0xc11e, 0x357f, 0xc11e, 0x21, 0 + .dw 0x35c0, 0xc11e, 0x35ff, 0xc11e, 0x21, 0 + .dw 0x3640, 0xc11e, 0x367f, 0xc11e, 0x21, 0 + .dw 0x36c0, 0xc11e, 0x36ff, 0xc11e, 0x21, 0 + .dw 0x3740, 0xc11e, 0x377f, 0xc11e, 0x21, 0 + .dw 0x37c0, 0xc11e, 0x37ff, 0xc11e, 0x21, 0 + .dw 0x3840, 0xc11e, 0x387f, 0xc11e, 0x21, 0 + .dw 0x38c0, 0xc11e, 0x38ff, 0xc11e, 0x21, 0 + .dw 0x3940, 0xc11e, 0x397f, 0xc11e, 0x21, 0 + .dw 0x39c0, 0xc11e, 0x3fff, 0xc11e, 0x21, 0 + .dw 0x4040, 0xc11e, 0x407f, 0xc11e, 0x21, 0 + .dw 0x40c0, 0xc11e, 0x40ff, 0xc11e, 0x21, 0 + .dw 0x4140, 0xc11e, 0x417f, 0xc11e, 0x21, 0 + .dw 0x41c0, 0xc11e, 0x41ff, 0xc11e, 0x21, 0 + .dw 0x4240, 0xc11e, 0x427f, 0xc11e, 0x21, 0 + .dw 0x42c0, 0xc11e, 0x42ff, 0xc11e, 0x21, 0 + .dw 0x4340, 0xc11e, 0x437f, 0xc11e, 0x21, 0 + .dw 0x43c0, 0xc11e, 0x43ff, 0xc11e, 0x21, 0 + .dw 0x4440, 0xc11e, 0x447f, 0xc11e, 0x21, 0 + .dw 0x44c0, 0xc11e, 0x44ff, 0xc11e, 0x21, 0 + .dw 0x4540, 0xc11e, 0x457f, 0xc11e, 0x21, 0 + .dw 0x45c0, 0xc11e, 0x45ff, 0xc11e, 0x21, 0 + .dw 0x4640, 0xc11e, 0x467f, 0xc11e, 0x21, 0 + .dw 0x46c0, 0xc11e, 0x46ff, 0xc11e, 0x21, 0 + .dw 0x4740, 0xc11e, 0x477f, 0xc11e, 0x21, 0 + .dw 0x47c0, 0xc11e, 0x47ff, 0xc11e, 0x21, 0 + .dw 0x4840, 0xc11e, 0x487f, 0xc11e, 0x21, 0 + .dw 0x48c0, 0xc11e, 0x48ff, 0xc11e, 0x21, 0 + .dw 0x4940, 0xc11e, 0x497f, 0xc11e, 0x21, 0 + .dw 0x49c0, 0xc11e, 0x49ff, 0xc11e, 0x21, 0 + .dw 0x4a40, 0xc11e, 0x4a7f, 0xc11e, 0x21, 0 + .dw 0x4ac0, 0xc11e, 0x4aff, 0xc11e, 0x21, 0 + .dw 0x4b40, 0xc11e, 0x4b7f, 0xc11e, 0x21, 0 + .dw 0x4bc0, 0xc11e, 0x4bff, 0xc11e, 0x21, 0 + .dw 0x4c40, 0xc11e, 0x4c7f, 0xc11e, 0x21, 0 + .dw 0x4cc0, 0xc11e, 0x4cff, 0xc11e, 0x21, 0 + .dw 0x4d40, 0xc11e, 0x4d7f, 0xc11e, 0x21, 0 + .dw 0x4dc0, 0xc11e, 0x4dff, 0xc11e, 0x21, 0 + .dw 0x4e40, 0xc11e, 0x4e7f, 0xc11e, 0x21, 0 + .dw 0x4ec0, 0xc11e, 0x4eff, 0xc11e, 0x21, 0 + .dw 0x4f40, 0xc11e, 0x4f7f, 0xc11e, 0x21, 0 + .dw 0x4fc0, 0xc11e, 0x4fff, 0xc11e, 0x21, 0 + .dw 0x5040, 0xc11e, 0x507f, 0xc11e, 0x21, 0 + .dw 0x50c0, 0xc11e, 0x50ff, 0xc11e, 0x21, 0 + .dw 0x5140, 0xc11e, 0x517f, 0xc11e, 0x21, 0 + .dw 0x51c0, 0xc11e, 0x51ff, 0xc11e, 0x21, 0 + .dw 0x5240, 0xc11e, 0x527f, 0xc11e, 0x21, 0 + .dw 0x52c0, 0xc11e, 0x52ff, 0xc11e, 0x21, 0 + .dw 0x5340, 0xc11e, 0x537f, 0xc11e, 0x21, 0 + .dw 0x53c0, 0xc11e, 0x53ff, 0xc11e, 0x21, 0 + .dw 0x5440, 0xc11e, 0x547f, 0xc11e, 0x21, 0 + .dw 0x54c0, 0xc11e, 0x54ff, 0xc11e, 0x21, 0 + .dw 0x5540, 0xc11e, 0x557f, 0xc11e, 0x21, 0 + .dw 0x55c0, 0xc11e, 0x55ff, 0xc11e, 0x21, 0 + .dw 0x5640, 0xc11e, 0x567f, 0xc11e, 0x21, 0 + .dw 0x56c0, 0xc11e, 0x56ff, 0xc11e, 0x21, 0 + .dw 0x5740, 0xc11e, 0x577f, 0xc11e, 0x21, 0 + .dw 0x57c0, 0xc11e, 0x57ff, 0xc11e, 0x21, 0 + .dw 0x5840, 0xc11e, 0x587f, 0xc11e, 0x21, 0 + .dw 0x58c0, 0xc11e, 0x58ff, 0xc11e, 0x21, 0 + .dw 0x5940, 0xc11e, 0x597f, 0xc11e, 0x21, 0 + .dw 0x59c0, 0xc11e, 0x5fff, 0xc11e, 0x21, 0 + .dw 0x6040, 0xc11e, 0x607f, 0xc11e, 0x21, 0 + .dw 0x60c0, 0xc11e, 0x60ff, 0xc11e, 0x21, 0 + .dw 0x6140, 0xc11e, 0x617f, 0xc11e, 0x21, 0 + .dw 0x61c0, 0xc11e, 0x61ff, 0xc11e, 0x21, 0 + .dw 0x6240, 0xc11e, 0x627f, 0xc11e, 0x21, 0 + .dw 0x62c0, 0xc11e, 0x62ff, 0xc11e, 0x21, 0 + .dw 0x6340, 0xc11e, 0x637f, 0xc11e, 0x21, 0 + .dw 0x63c0, 0xc11e, 0x63ff, 0xc11e, 0x21, 0 + .dw 0x6440, 0xc11e, 0x647f, 0xc11e, 0x21, 0 + .dw 0x64c0, 0xc11e, 0x64ff, 0xc11e, 0x21, 0 + .dw 0x6540, 0xc11e, 0x657f, 0xc11e, 0x21, 0 + .dw 0x65c0, 0xc11e, 0x65ff, 0xc11e, 0x21, 0 + .dw 0x6640, 0xc11e, 0x667f, 0xc11e, 0x21, 0 + .dw 0x66c0, 0xc11e, 0x66ff, 0xc11e, 0x21, 0 + .dw 0x6740, 0xc11e, 0x677f, 0xc11e, 0x21, 0 + .dw 0x67c0, 0xc11e, 0x67ff, 0xc11e, 0x21, 0 + .dw 0x6840, 0xc11e, 0x687f, 0xc11e, 0x21, 0 + .dw 0x68c0, 0xc11e, 0x68ff, 0xc11e, 0x21, 0 + .dw 0x6940, 0xc11e, 0x697f, 0xc11e, 0x21, 0 + .dw 0x69c0, 0xc11e, 0x69ff, 0xc11e, 0x21, 0 + .dw 0x6a40, 0xc11e, 0x6a7f, 0xc11e, 0x21, 0 + .dw 0x6ac0, 0xc11e, 0x6aff, 0xc11e, 0x21, 0 + .dw 0x6b40, 0xc11e, 0x6b7f, 0xc11e, 0x21, 0 + .dw 0x6bc0, 0xc11e, 0x6bff, 0xc11e, 0x21, 0 + .dw 0x6c40, 0xc11e, 0x6c7f, 0xc11e, 0x21, 0 + .dw 0x6cc0, 0xc11e, 0x6cff, 0xc11e, 0x21, 0 + .dw 0x6d40, 0xc11e, 0x6d7f, 0xc11e, 0x21, 0 + .dw 0x6dc0, 0xc11e, 0x6dff, 0xc11e, 0x21, 0 + .dw 0x6e40, 0xc11e, 0x6e7f, 0xc11e, 0x21, 0 + .dw 0x6ec0, 0xc11e, 0x6eff, 0xc11e, 0x21, 0 + .dw 0x6f40, 0xc11e, 0x6f7f, 0xc11e, 0x21, 0 + .dw 0x6fc0, 0xc11e, 0x6fff, 0xc11e, 0x21, 0 + .dw 0x7040, 0xc11e, 0x707f, 0xc11e, 0x21, 0 + .dw 0x70c0, 0xc11e, 0x70ff, 0xc11e, 0x21, 0 + .dw 0x7140, 0xc11e, 0x717f, 0xc11e, 0x21, 0 + .dw 0x71c0, 0xc11e, 0x71ff, 0xc11e, 0x21, 0 + .dw 0x7240, 0xc11e, 0x727f, 0xc11e, 0x21, 0 + .dw 0x72c0, 0xc11e, 0x72ff, 0xc11e, 0x21, 0 + .dw 0x7340, 0xc11e, 0x737f, 0xc11e, 0x21, 0 + .dw 0x73c0, 0xc11e, 0x73ff, 0xc11e, 0x21, 0 + .dw 0x7440, 0xc11e, 0x747f, 0xc11e, 0x21, 0 + .dw 0x74c0, 0xc11e, 0x74ff, 0xc11e, 0x21, 0 + .dw 0x7540, 0xc11e, 0x757f, 0xc11e, 0x21, 0 + .dw 0x75c0, 0xc11e, 0x75ff, 0xc11e, 0x21, 0 + .dw 0x7640, 0xc11e, 0x767f, 0xc11e, 0x21, 0 + .dw 0x76c0, 0xc11e, 0x76ff, 0xc11e, 0x21, 0 + .dw 0x7740, 0xc11e, 0x777f, 0xc11e, 0x21, 0 + .dw 0x77c0, 0xc11e, 0x77ff, 0xc11e, 0x21, 0 + .dw 0x7840, 0xc11e, 0x787f, 0xc11e, 0x21, 0 + .dw 0x78c0, 0xc11e, 0x78ff, 0xc11e, 0x21, 0 + .dw 0x7940, 0xc11e, 0x797f, 0xc11e, 0x21, 0 + .dw 0x79c0, 0xc11e, 0x7fff, 0xc11e, 0x21, 0 + .dw 0x8040, 0xc11e, 0x807f, 0xc11e, 0x21, 0 + .dw 0x80c0, 0xc11e, 0x80ff, 0xc11e, 0x21, 0 + .dw 0x8140, 0xc11e, 0x817f, 0xc11e, 0x21, 0 + .dw 0x81c0, 0xc11e, 0x81ff, 0xc11e, 0x21, 0 + .dw 0x8240, 0xc11e, 0x827f, 0xc11e, 0x21, 0 + .dw 0x82c0, 0xc11e, 0x82ff, 0xc11e, 0x21, 0 + .dw 0x8340, 0xc11e, 0x837f, 0xc11e, 0x21, 0 + .dw 0x83c0, 0xc11e, 0x83ff, 0xc11e, 0x21, 0 + .dw 0x8440, 0xc11e, 0x847f, 0xc11e, 0x21, 0 + .dw 0x84c0, 0xc11e, 0x84ff, 0xc11e, 0x21, 0 + .dw 0x8540, 0xc11e, 0x857f, 0xc11e, 0x21, 0 + .dw 0x85c0, 0xc11e, 0x85ff, 0xc11e, 0x21, 0 + .dw 0x8640, 0xc11e, 0x867f, 0xc11e, 0x21, 0 + .dw 0x86c0, 0xc11e, 0x86ff, 0xc11e, 0x21, 0 + .dw 0x8740, 0xc11e, 0x877f, 0xc11e, 0x21, 0 + .dw 0x87c0, 0xc11e, 0x87ff, 0xc11e, 0x21, 0 + .dw 0x8840, 0xc11e, 0x887f, 0xc11e, 0x21, 0 + .dw 0x88c0, 0xc11e, 0x88ff, 0xc11e, 0x21, 0 + .dw 0x8940, 0xc11e, 0x897f, 0xc11e, 0x21, 0 + .dw 0x89c0, 0xc11e, 0x89ff, 0xc11e, 0x21, 0 + .dw 0x8a40, 0xc11e, 0x8a7f, 0xc11e, 0x21, 0 + .dw 0x8ac0, 0xc11e, 0x8aff, 0xc11e, 0x21, 0 + .dw 0x8b40, 0xc11e, 0x8b7f, 0xc11e, 0x21, 0 + .dw 0x8bc0, 0xc11e, 0x8bff, 0xc11e, 0x21, 0 + .dw 0x8c40, 0xc11e, 0x8c7f, 0xc11e, 0x21, 0 + .dw 0x8cc0, 0xc11e, 0x8cff, 0xc11e, 0x21, 0 + .dw 0x8d40, 0xc11e, 0x8d7f, 0xc11e, 0x21, 0 + .dw 0x8dc0, 0xc11e, 0x8dff, 0xc11e, 0x21, 0 + .dw 0x8e40, 0xc11e, 0x8e7f, 0xc11e, 0x21, 0 + .dw 0x8ec0, 0xc11e, 0x8eff, 0xc11e, 0x21, 0 + .dw 0x8f40, 0xc11e, 0x8f7f, 0xc11e, 0x21, 0 + .dw 0x8fc0, 0xc11e, 0x8fff, 0xc11e, 0x21, 0 + .dw 0x9040, 0xc11e, 0x907f, 0xc11e, 0x21, 0 + .dw 0x90c0, 0xc11e, 0x90ff, 0xc11e, 0x21, 0 + .dw 0x9140, 0xc11e, 0x917f, 0xc11e, 0x21, 0 + .dw 0x91c0, 0xc11e, 0x91ff, 0xc11e, 0x21, 0 + .dw 0x9240, 0xc11e, 0x927f, 0xc11e, 0x21, 0 + .dw 0x92c0, 0xc11e, 0x92ff, 0xc11e, 0x21, 0 + .dw 0x9340, 0xc11e, 0x937f, 0xc11e, 0x21, 0 + .dw 0x93c0, 0xc11e, 0x93ff, 0xc11e, 0x21, 0 + .dw 0x9440, 0xc11e, 0x947f, 0xc11e, 0x21, 0 + .dw 0x94c0, 0xc11e, 0x94ff, 0xc11e, 0x21, 0 + .dw 0x9540, 0xc11e, 0x957f, 0xc11e, 0x21, 0 + .dw 0x95c0, 0xc11e, 0x95ff, 0xc11e, 0x21, 0 + .dw 0x9640, 0xc11e, 0x967f, 0xc11e, 0x21, 0 + .dw 0x96c0, 0xc11e, 0x96ff, 0xc11e, 0x21, 0 + .dw 0x9740, 0xc11e, 0x977f, 0xc11e, 0x21, 0 + .dw 0x97c0, 0xc11e, 0x97ff, 0xc11e, 0x21, 0 + .dw 0x9840, 0xc11e, 0x987f, 0xc11e, 0x21, 0 + .dw 0x98c0, 0xc11e, 0x98ff, 0xc11e, 0x21, 0 + .dw 0x9940, 0xc11e, 0x997f, 0xc11e, 0x21, 0 + .dw 0x99c0, 0xc11e, 0x9fff, 0xc11e, 0x21, 0 + .dw 0xa040, 0xc11e, 0xa07f, 0xc11e, 0x21, 0 + .dw 0xa0c0, 0xc11e, 0xa0ff, 0xc11e, 0x21, 0 + .dw 0xa140, 0xc11e, 0xa17f, 0xc11e, 0x21, 0 + .dw 0xa1c0, 0xc11e, 0xa1ff, 0xc11e, 0x21, 0 + .dw 0xa240, 0xc11e, 0xa27f, 0xc11e, 0x21, 0 + .dw 0xa2c0, 0xc11e, 0xa2ff, 0xc11e, 0x21, 0 + .dw 0xa340, 0xc11e, 0xa37f, 0xc11e, 0x21, 0 + .dw 0xa3c0, 0xc11e, 0xa3ff, 0xc11e, 0x21, 0 + .dw 0xa440, 0xc11e, 0xa47f, 0xc11e, 0x21, 0 + .dw 0xa4c0, 0xc11e, 0xa4ff, 0xc11e, 0x21, 0 + .dw 0xa540, 0xc11e, 0xa57f, 0xc11e, 0x21, 0 + .dw 0xa5c0, 0xc11e, 0xa5ff, 0xc11e, 0x21, 0 + .dw 0xa640, 0xc11e, 0xa67f, 0xc11e, 0x21, 0 + .dw 0xa6c0, 0xc11e, 0xa6ff, 0xc11e, 0x21, 0 + .dw 0xa740, 0xc11e, 0xa77f, 0xc11e, 0x21, 0 + .dw 0xa7c0, 0xc11e, 0xa7ff, 0xc11e, 0x21, 0 + .dw 0xa840, 0xc11e, 0xa87f, 0xc11e, 0x21, 0 + .dw 0xa8c0, 0xc11e, 0xa8ff, 0xc11e, 0x21, 0 + .dw 0xa940, 0xc11e, 0xa97f, 0xc11e, 0x21, 0 + .dw 0xa9c0, 0xc11e, 0xa9ff, 0xc11e, 0x21, 0 + .dw 0xaa40, 0xc11e, 0xaa7f, 0xc11e, 0x21, 0 + .dw 0xaac0, 0xc11e, 0xaaff, 0xc11e, 0x21, 0 + .dw 0xab40, 0xc11e, 0xab7f, 0xc11e, 0x21, 0 + .dw 0xabc0, 0xc11e, 0xabff, 0xc11e, 0x21, 0 + .dw 0xac40, 0xc11e, 0xac7f, 0xc11e, 0x21, 0 + .dw 0xacc0, 0xc11e, 0xacff, 0xc11e, 0x21, 0 + .dw 0xad40, 0xc11e, 0xad7f, 0xc11e, 0x21, 0 + .dw 0xadc0, 0xc11e, 0xadff, 0xc11e, 0x21, 0 + .dw 0xae40, 0xc11e, 0xae7f, 0xc11e, 0x21, 0 + .dw 0xaec0, 0xc11e, 0xaeff, 0xc11e, 0x21, 0 + .dw 0xaf40, 0xc11e, 0xaf7f, 0xc11e, 0x21, 0 + .dw 0xafc0, 0xc11e, 0xafff, 0xc11e, 0x21, 0 + .dw 0xb040, 0xc11e, 0xb07f, 0xc11e, 0x21, 0 + .dw 0xb0c0, 0xc11e, 0xb0ff, 0xc11e, 0x21, 0 + .dw 0xb140, 0xc11e, 0xb17f, 0xc11e, 0x21, 0 + .dw 0xb1c0, 0xc11e, 0xb1ff, 0xc11e, 0x21, 0 + .dw 0xb240, 0xc11e, 0xb27f, 0xc11e, 0x21, 0 + .dw 0xb2c0, 0xc11e, 0xb2ff, 0xc11e, 0x21, 0 + .dw 0xb340, 0xc11e, 0xb37f, 0xc11e, 0x21, 0 + .dw 0xb3c0, 0xc11e, 0xb3ff, 0xc11e, 0x21, 0 + .dw 0xb440, 0xc11e, 0xb47f, 0xc11e, 0x21, 0 + .dw 0xb4c0, 0xc11e, 0xb4ff, 0xc11e, 0x21, 0 + .dw 0xb540, 0xc11e, 0xb57f, 0xc11e, 0x21, 0 + .dw 0xb5c0, 0xc11e, 0xb5ff, 0xc11e, 0x21, 0 + .dw 0xb640, 0xc11e, 0xb67f, 0xc11e, 0x21, 0 + .dw 0xb6c0, 0xc11e, 0xb6ff, 0xc11e, 0x21, 0 + .dw 0xb740, 0xc11e, 0xb77f, 0xc11e, 0x21, 0 + .dw 0xb7c0, 0xc11e, 0xb7ff, 0xc11e, 0x21, 0 + .dw 0xb840, 0xc11e, 0xb87f, 0xc11e, 0x21, 0 + .dw 0xb8c0, 0xc11e, 0xb8ff, 0xc11e, 0x21, 0 + .dw 0xb940, 0xc11e, 0xb97f, 0xc11e, 0x21, 0 + .dw 0xb9c0, 0xc11e, 0xbfff, 0xc11e, 0x21, 0 + .dw 0xc040, 0xc11e, 0xc07f, 0xc11e, 0x21, 0 + .dw 0xc0c0, 0xc11e, 0xc0ff, 0xc11e, 0x21, 0 + .dw 0xc140, 0xc11e, 0xc17f, 0xc11e, 0x21, 0 + .dw 0xc1c0, 0xc11e, 0xc1ff, 0xc11e, 0x21, 0 + .dw 0xc240, 0xc11e, 0xc27f, 0xc11e, 0x21, 0 + .dw 0xc2c0, 0xc11e, 0xc2ff, 0xc11e, 0x21, 0 + .dw 0xc340, 0xc11e, 0xc37f, 0xc11e, 0x21, 0 + .dw 0xc3c0, 0xc11e, 0xc3ff, 0xc11e, 0x21, 0 + .dw 0xc440, 0xc11e, 0xc47f, 0xc11e, 0x21, 0 + .dw 0xc4c0, 0xc11e, 0xc4ff, 0xc11e, 0x21, 0 + .dw 0xc540, 0xc11e, 0xc57f, 0xc11e, 0x21, 0 + .dw 0xc5c0, 0xc11e, 0xc5ff, 0xc11e, 0x21, 0 + .dw 0xc640, 0xc11e, 0xc67f, 0xc11e, 0x21, 0 + .dw 0xc6c0, 0xc11e, 0xc6ff, 0xc11e, 0x21, 0 + .dw 0xc740, 0xc11e, 0xc77f, 0xc11e, 0x21, 0 + .dw 0xc7c0, 0xc11e, 0xc7ff, 0xc11e, 0x21, 0 + .dw 0xc840, 0xc11e, 0xc87f, 0xc11e, 0x21, 0 + .dw 0xc8c0, 0xc11e, 0xc8ff, 0xc11e, 0x21, 0 + .dw 0xc940, 0xc11e, 0xc97f, 0xc11e, 0x21, 0 + .dw 0xc9c0, 0xc11e, 0xc9ff, 0xc11e, 0x21, 0 + .dw 0xca40, 0xc11e, 0xca7f, 0xc11e, 0x21, 0 + .dw 0xcac0, 0xc11e, 0xcaff, 0xc11e, 0x21, 0 + .dw 0xcb40, 0xc11e, 0xcb7f, 0xc11e, 0x21, 0 + .dw 0xcbc0, 0xc11e, 0xcbff, 0xc11e, 0x21, 0 + .dw 0xcc40, 0xc11e, 0xcc7f, 0xc11e, 0x21, 0 + .dw 0xccc0, 0xc11e, 0xccff, 0xc11e, 0x21, 0 + .dw 0xcd40, 0xc11e, 0xcd7f, 0xc11e, 0x21, 0 + .dw 0xcdc0, 0xc11e, 0xcdff, 0xc11e, 0x21, 0 + .dw 0xce40, 0xc11e, 0xce7f, 0xc11e, 0x21, 0 + .dw 0xcec0, 0xc11e, 0xceff, 0xc11e, 0x21, 0 + .dw 0xcf40, 0xc11e, 0xcf7f, 0xc11e, 0x21, 0 + .dw 0xcfc0, 0xc11e, 0xcfff, 0xc11e, 0x21, 0 + .dw 0xd040, 0xc11e, 0xd07f, 0xc11e, 0x21, 0 + .dw 0xd0c0, 0xc11e, 0xd0ff, 0xc11e, 0x21, 0 + .dw 0xd140, 0xc11e, 0xd17f, 0xc11e, 0x21, 0 + .dw 0xd1c0, 0xc11e, 0xd1ff, 0xc11e, 0x21, 0 + .dw 0xd240, 0xc11e, 0xd27f, 0xc11e, 0x21, 0 + .dw 0xd2c0, 0xc11e, 0xd2ff, 0xc11e, 0x21, 0 + .dw 0xd340, 0xc11e, 0xd37f, 0xc11e, 0x21, 0 + .dw 0xd3c0, 0xc11e, 0xd3ff, 0xc11e, 0x21, 0 + .dw 0xd440, 0xc11e, 0xd47f, 0xc11e, 0x21, 0 + .dw 0xd4c0, 0xc11e, 0xd4ff, 0xc11e, 0x21, 0 + .dw 0xd540, 0xc11e, 0xd57f, 0xc11e, 0x21, 0 + .dw 0xd5c0, 0xc11e, 0xd5ff, 0xc11e, 0x21, 0 + .dw 0xd640, 0xc11e, 0xd67f, 0xc11e, 0x21, 0 + .dw 0xd6c0, 0xc11e, 0xd6ff, 0xc11e, 0x21, 0 + .dw 0xd740, 0xc11e, 0xd77f, 0xc11e, 0x21, 0 + .dw 0xd7c0, 0xc11e, 0xd7ff, 0xc11e, 0x21, 0 + .dw 0xd840, 0xc11e, 0xd87f, 0xc11e, 0x21, 0 + .dw 0xd8c0, 0xc11e, 0xd8ff, 0xc11e, 0x21, 0 + .dw 0xd940, 0xc11e, 0xd97f, 0xc11e, 0x21, 0 + .dw 0xd9c0, 0xc11e, 0xdfff, 0xc11e, 0x21, 0 + .dw 0xe040, 0xc11e, 0xe07f, 0xc11e, 0x21, 0 + .dw 0xe0c0, 0xc11e, 0xe0ff, 0xc11e, 0x21, 0 + .dw 0xe140, 0xc11e, 0xe17f, 0xc11e, 0x21, 0 + .dw 0xe1c0, 0xc11e, 0xe1ff, 0xc11e, 0x21, 0 + .dw 0xe240, 0xc11e, 0xe27f, 0xc11e, 0x21, 0 + .dw 0xe2c0, 0xc11e, 0xe2ff, 0xc11e, 0x21, 0 + .dw 0xe340, 0xc11e, 0xe37f, 0xc11e, 0x21, 0 + .dw 0xe3c0, 0xc11e, 0xe3ff, 0xc11e, 0x21, 0 + .dw 0xe440, 0xc11e, 0xe47f, 0xc11e, 0x21, 0 + .dw 0xe4c0, 0xc11e, 0xe4ff, 0xc11e, 0x21, 0 + .dw 0xe540, 0xc11e, 0xe57f, 0xc11e, 0x21, 0 + .dw 0xe5c0, 0xc11e, 0xe5ff, 0xc11e, 0x21, 0 + .dw 0xe640, 0xc11e, 0xe67f, 0xc11e, 0x21, 0 + .dw 0xe6c0, 0xc11e, 0xe6ff, 0xc11e, 0x21, 0 + .dw 0xe740, 0xc11e, 0xe77f, 0xc11e, 0x21, 0 + .dw 0xe7c0, 0xc11e, 0xe7ff, 0xc11e, 0x21, 0 + .dw 0xe840, 0xc11e, 0xe87f, 0xc11e, 0x21, 0 + .dw 0xe8c0, 0xc11e, 0xe8ff, 0xc11e, 0x21, 0 + .dw 0xe940, 0xc11e, 0xe97f, 0xc11e, 0x21, 0 + .dw 0xe9c0, 0xc11e, 0xe9ff, 0xc11e, 0x21, 0 + .dw 0xea40, 0xc11e, 0xea7f, 0xc11e, 0x21, 0 + .dw 0xeac0, 0xc11e, 0xeaff, 0xc11e, 0x21, 0 + .dw 0xeb40, 0xc11e, 0xeb7f, 0xc11e, 0x21, 0 + .dw 0xebc0, 0xc11e, 0xebff, 0xc11e, 0x21, 0 + .dw 0xec40, 0xc11e, 0xec7f, 0xc11e, 0x21, 0 + .dw 0xecc0, 0xc11e, 0xecff, 0xc11e, 0x21, 0 + .dw 0xed40, 0xc11e, 0xed7f, 0xc11e, 0x21, 0 + .dw 0xedc0, 0xc11e, 0xedff, 0xc11e, 0x21, 0 + .dw 0xee40, 0xc11e, 0xee7f, 0xc11e, 0x21, 0 + .dw 0xeec0, 0xc11e, 0xeeff, 0xc11e, 0x21, 0 + .dw 0xef40, 0xc11e, 0xef7f, 0xc11e, 0x21, 0 + .dw 0xefc0, 0xc11e, 0xefff, 0xc11e, 0x21, 0 + .dw 0xf040, 0xc11e, 0xf07f, 0xc11e, 0x21, 0 + .dw 0xf0c0, 0xc11e, 0xf0ff, 0xc11e, 0x21, 0 + .dw 0xf140, 0xc11e, 0xf17f, 0xc11e, 0x21, 0 + .dw 0xf1c0, 0xc11e, 0xf1ff, 0xc11e, 0x21, 0 + .dw 0xf240, 0xc11e, 0xf27f, 0xc11e, 0x21, 0 + .dw 0xf2c0, 0xc11e, 0xf2ff, 0xc11e, 0x21, 0 + .dw 0xf340, 0xc11e, 0xf37f, 0xc11e, 0x21, 0 + .dw 0xf3c0, 0xc11e, 0xf3ff, 0xc11e, 0x21, 0 + .dw 0xf440, 0xc11e, 0xf47f, 0xc11e, 0x21, 0 + .dw 0xf4c0, 0xc11e, 0xf4ff, 0xc11e, 0x21, 0 + .dw 0xf540, 0xc11e, 0xf57f, 0xc11e, 0x21, 0 + .dw 0xf5c0, 0xc11e, 0xf5ff, 0xc11e, 0x21, 0 + .dw 0xf640, 0xc11e, 0xf67f, 0xc11e, 0x21, 0 + .dw 0xf6c0, 0xc11e, 0xf6ff, 0xc11e, 0x21, 0 + .dw 0xf740, 0xc11e, 0xf77f, 0xc11e, 0x21, 0 + .dw 0xf7c0, 0xc11e, 0xf7ff, 0xc11e, 0x21, 0 + .dw 0xf840, 0xc11e, 0xf87f, 0xc11e, 0x21, 0 + .dw 0xf8c0, 0xc11e, 0xf8ff, 0xc11e, 0x21, 0 + .dw 0xf940, 0xc11e, 0xf97f, 0xc11e, 0x21, 0 + .dw 0xf9c0, 0xc11e, 0xffff, 0xc11e, 0x21, 0 + .dw 0x0040, 0xc11f, 0x007f, 0xc11f, 0x21, 0 + .dw 0x00c0, 0xc11f, 0x00ff, 0xc11f, 0x21, 0 + .dw 0x0140, 0xc11f, 0x017f, 0xc11f, 0x21, 0 + .dw 0x01c0, 0xc11f, 0x01ff, 0xc11f, 0x21, 0 + .dw 0x0240, 0xc11f, 0x027f, 0xc11f, 0x21, 0 + .dw 0x02c0, 0xc11f, 0x02ff, 0xc11f, 0x21, 0 + .dw 0x0340, 0xc11f, 0x037f, 0xc11f, 0x21, 0 + .dw 0x03c0, 0xc11f, 0x03ff, 0xc11f, 0x21, 0 + .dw 0x0440, 0xc11f, 0x047f, 0xc11f, 0x21, 0 + .dw 0x04c0, 0xc11f, 0x04ff, 0xc11f, 0x21, 0 + .dw 0x0540, 0xc11f, 0x057f, 0xc11f, 0x21, 0 + .dw 0x05c0, 0xc11f, 0x05ff, 0xc11f, 0x21, 0 + .dw 0x0640, 0xc11f, 0x067f, 0xc11f, 0x21, 0 + .dw 0x06c0, 0xc11f, 0x06ff, 0xc11f, 0x21, 0 + .dw 0x0740, 0xc11f, 0x077f, 0xc11f, 0x21, 0 + .dw 0x07c0, 0xc11f, 0x07ff, 0xc11f, 0x21, 0 + .dw 0x0840, 0xc11f, 0x087f, 0xc11f, 0x21, 0 + .dw 0x08c0, 0xc11f, 0x08ff, 0xc11f, 0x21, 0 + .dw 0x0940, 0xc11f, 0x097f, 0xc11f, 0x21, 0 + .dw 0x09c0, 0xc11f, 0x09ff, 0xc11f, 0x21, 0 + .dw 0x0a40, 0xc11f, 0x0a7f, 0xc11f, 0x21, 0 + .dw 0x0ac0, 0xc11f, 0x0aff, 0xc11f, 0x21, 0 + .dw 0x0b40, 0xc11f, 0x0b7f, 0xc11f, 0x21, 0 + .dw 0x0bc0, 0xc11f, 0x0bff, 0xc11f, 0x21, 0 + .dw 0x0c40, 0xc11f, 0x0c7f, 0xc11f, 0x21, 0 + .dw 0x0cc0, 0xc11f, 0x0cff, 0xc11f, 0x21, 0 + .dw 0x0d40, 0xc11f, 0x0d7f, 0xc11f, 0x21, 0 + .dw 0x0dc0, 0xc11f, 0x0dff, 0xc11f, 0x21, 0 + .dw 0x0e40, 0xc11f, 0x0e7f, 0xc11f, 0x21, 0 + .dw 0x0ec0, 0xc11f, 0x0eff, 0xc11f, 0x21, 0 + .dw 0x0f40, 0xc11f, 0x0f7f, 0xc11f, 0x21, 0 + .dw 0x0fc0, 0xc11f, 0x0fff, 0xc11f, 0x21, 0 + .dw 0x1040, 0xc11f, 0x107f, 0xc11f, 0x21, 0 + .dw 0x10c0, 0xc11f, 0x10ff, 0xc11f, 0x21, 0 + .dw 0x1140, 0xc11f, 0x117f, 0xc11f, 0x21, 0 + .dw 0x11c0, 0xc11f, 0x11ff, 0xc11f, 0x21, 0 + .dw 0x1240, 0xc11f, 0x127f, 0xc11f, 0x21, 0 + .dw 0x12c0, 0xc11f, 0x12ff, 0xc11f, 0x21, 0 + .dw 0x1340, 0xc11f, 0x137f, 0xc11f, 0x21, 0 + .dw 0x13c0, 0xc11f, 0x13ff, 0xc11f, 0x21, 0 + .dw 0x1440, 0xc11f, 0x147f, 0xc11f, 0x21, 0 + .dw 0x14c0, 0xc11f, 0x14ff, 0xc11f, 0x21, 0 + .dw 0x1540, 0xc11f, 0x157f, 0xc11f, 0x21, 0 + .dw 0x15c0, 0xc11f, 0x15ff, 0xc11f, 0x21, 0 + .dw 0x1640, 0xc11f, 0x167f, 0xc11f, 0x21, 0 + .dw 0x16c0, 0xc11f, 0x16ff, 0xc11f, 0x21, 0 + .dw 0x1740, 0xc11f, 0x177f, 0xc11f, 0x21, 0 + .dw 0x17c0, 0xc11f, 0x17ff, 0xc11f, 0x21, 0 + .dw 0x1840, 0xc11f, 0x187f, 0xc11f, 0x21, 0 + .dw 0x18c0, 0xc11f, 0x18ff, 0xc11f, 0x21, 0 + .dw 0x1940, 0xc11f, 0x197f, 0xc11f, 0x21, 0 + .dw 0x19c0, 0xc11f, 0x1fff, 0xc11f, 0x21, 0 + .dw 0x2040, 0xc11f, 0x207f, 0xc11f, 0x21, 0 + .dw 0x20c0, 0xc11f, 0x20ff, 0xc11f, 0x21, 0 + .dw 0x2140, 0xc11f, 0x217f, 0xc11f, 0x21, 0 + .dw 0x21c0, 0xc11f, 0x21ff, 0xc11f, 0x21, 0 + .dw 0x2240, 0xc11f, 0x227f, 0xc11f, 0x21, 0 + .dw 0x22c0, 0xc11f, 0x22ff, 0xc11f, 0x21, 0 + .dw 0x2340, 0xc11f, 0x237f, 0xc11f, 0x21, 0 + .dw 0x23c0, 0xc11f, 0x23ff, 0xc11f, 0x21, 0 + .dw 0x2440, 0xc11f, 0x247f, 0xc11f, 0x21, 0 + .dw 0x24c0, 0xc11f, 0x24ff, 0xc11f, 0x21, 0 + .dw 0x2540, 0xc11f, 0x257f, 0xc11f, 0x21, 0 + .dw 0x25c0, 0xc11f, 0x25ff, 0xc11f, 0x21, 0 + .dw 0x2640, 0xc11f, 0x267f, 0xc11f, 0x21, 0 + .dw 0x26c0, 0xc11f, 0x26ff, 0xc11f, 0x21, 0 + .dw 0x2740, 0xc11f, 0x277f, 0xc11f, 0x21, 0 + .dw 0x27c0, 0xc11f, 0x27ff, 0xc11f, 0x21, 0 + .dw 0x2840, 0xc11f, 0x287f, 0xc11f, 0x21, 0 + .dw 0x28c0, 0xc11f, 0x28ff, 0xc11f, 0x21, 0 + .dw 0x2940, 0xc11f, 0x297f, 0xc11f, 0x21, 0 + .dw 0x29c0, 0xc11f, 0x29ff, 0xc11f, 0x21, 0 + .dw 0x2a40, 0xc11f, 0x2a7f, 0xc11f, 0x21, 0 + .dw 0x2ac0, 0xc11f, 0x2aff, 0xc11f, 0x21, 0 + .dw 0x2b40, 0xc11f, 0x2b7f, 0xc11f, 0x21, 0 + .dw 0x2bc0, 0xc11f, 0x2bff, 0xc11f, 0x21, 0 + .dw 0x2c40, 0xc11f, 0x2c7f, 0xc11f, 0x21, 0 + .dw 0x2cc0, 0xc11f, 0x2cff, 0xc11f, 0x21, 0 + .dw 0x2d40, 0xc11f, 0x2d7f, 0xc11f, 0x21, 0 + .dw 0x2dc0, 0xc11f, 0x2dff, 0xc11f, 0x21, 0 + .dw 0x2e40, 0xc11f, 0x2e7f, 0xc11f, 0x21, 0 + .dw 0x2ec0, 0xc11f, 0x2eff, 0xc11f, 0x21, 0 + .dw 0x2f40, 0xc11f, 0x2f7f, 0xc11f, 0x21, 0 + .dw 0x2fc0, 0xc11f, 0x2fff, 0xc11f, 0x21, 0 + .dw 0x3040, 0xc11f, 0x307f, 0xc11f, 0x21, 0 + .dw 0x30c0, 0xc11f, 0x30ff, 0xc11f, 0x21, 0 + .dw 0x3140, 0xc11f, 0x317f, 0xc11f, 0x21, 0 + .dw 0x31c0, 0xc11f, 0x31ff, 0xc11f, 0x21, 0 + .dw 0x3240, 0xc11f, 0x327f, 0xc11f, 0x21, 0 + .dw 0x32c0, 0xc11f, 0x32ff, 0xc11f, 0x21, 0 + .dw 0x3340, 0xc11f, 0x337f, 0xc11f, 0x21, 0 + .dw 0x33c0, 0xc11f, 0x33ff, 0xc11f, 0x21, 0 + .dw 0x3440, 0xc11f, 0x347f, 0xc11f, 0x21, 0 + .dw 0x34c0, 0xc11f, 0x34ff, 0xc11f, 0x21, 0 + .dw 0x3540, 0xc11f, 0x357f, 0xc11f, 0x21, 0 + .dw 0x35c0, 0xc11f, 0x35ff, 0xc11f, 0x21, 0 + .dw 0x3640, 0xc11f, 0x367f, 0xc11f, 0x21, 0 + .dw 0x36c0, 0xc11f, 0x36ff, 0xc11f, 0x21, 0 + .dw 0x3740, 0xc11f, 0x377f, 0xc11f, 0x21, 0 + .dw 0x37c0, 0xc11f, 0x37ff, 0xc11f, 0x21, 0 + .dw 0x3840, 0xc11f, 0x387f, 0xc11f, 0x21, 0 + .dw 0x38c0, 0xc11f, 0x38ff, 0xc11f, 0x21, 0 + .dw 0x3940, 0xc11f, 0x397f, 0xc11f, 0x21, 0 + .dw 0x39c0, 0xc11f, 0x1fff, 0xc120, 0x21, 0 + .dw 0x3a00, 0xc120, 0x5fff, 0xc120, 0x21, 0 + .dw 0x7a00, 0xc120, 0x9fff, 0xc120, 0x21, 0 + .dw 0xba00, 0xc120, 0xdfff, 0xc120, 0x21, 0 + .dw 0xfa00, 0xc120, 0x1fff, 0xc121, 0x21, 0 + .dw 0x3a00, 0xc121, 0x5fff, 0xc121, 0x21, 0 + .dw 0x7a00, 0xc121, 0x9fff, 0xc121, 0x21, 0 + .dw 0xba00, 0xc121, 0xdfff, 0xc121, 0x21, 0 + .dw 0xfa00, 0xc121, 0x1fff, 0xc122, 0x21, 0 + .dw 0x3a00, 0xc122, 0x5fff, 0xc122, 0x21, 0 + .dw 0x7a00, 0xc122, 0x9fff, 0xc122, 0x21, 0 + .dw 0xba00, 0xc122, 0xdfff, 0xc122, 0x21, 0 + .dw 0xfa00, 0xc122, 0x1fff, 0xc123, 0x21, 0 + .dw 0x3a00, 0xc123, 0xffff, 0xc123, 0x21, 0 + .dw 0x1a00, 0xc124, 0x1fff, 0xc124, 0x21, 0 + .dw 0x3a00, 0xc124, 0x3fff, 0xc124, 0x21, 0 + .dw 0x5a00, 0xc124, 0x5fff, 0xc124, 0x21, 0 + .dw 0x7a00, 0xc124, 0x7fff, 0xc124, 0x21, 0 + .dw 0x9a00, 0xc124, 0x9fff, 0xc124, 0x21, 0 + .dw 0xba00, 0xc124, 0xbfff, 0xc124, 0x21, 0 + .dw 0xda00, 0xc124, 0xdfff, 0xc124, 0x21, 0 + .dw 0xfa00, 0xc124, 0xffff, 0xc124, 0x21, 0 + .dw 0x1a00, 0xc125, 0x1fff, 0xc125, 0x21, 0 + .dw 0x3a00, 0xc125, 0x3fff, 0xc125, 0x21, 0 + .dw 0x5a00, 0xc125, 0x5fff, 0xc125, 0x21, 0 + .dw 0x7a00, 0xc125, 0x7fff, 0xc125, 0x21, 0 + .dw 0x9a00, 0xc125, 0x9fff, 0xc125, 0x21, 0 + .dw 0xba00, 0xc125, 0xbfff, 0xc125, 0x21, 0 + .dw 0xda00, 0xc125, 0xdfff, 0xc125, 0x21, 0 + .dw 0xfa00, 0xc125, 0xffff, 0xc125, 0x21, 0 + .dw 0x1a00, 0xc126, 0x1fff, 0xc126, 0x21, 0 + .dw 0x3a00, 0xc126, 0x3fff, 0xc126, 0x21, 0 + .dw 0x5a00, 0xc126, 0x5fff, 0xc126, 0x21, 0 + .dw 0x7a00, 0xc126, 0x7fff, 0xc126, 0x21, 0 + .dw 0x9a00, 0xc126, 0x9fff, 0xc126, 0x21, 0 + .dw 0xba00, 0xc126, 0xbfff, 0xc126, 0x21, 0 + .dw 0xda00, 0xc126, 0xdfff, 0xc126, 0x21, 0 + .dw 0xfa00, 0xc126, 0xffff, 0xc126, 0x21, 0 + .dw 0x1a00, 0xc127, 0x1fff, 0xc127, 0x21, 0 + .dw 0x3a00, 0xc127, 0x1fff, 0xc128, 0x21, 0 + .dw 0x2040, 0xc128, 0x207f, 0xc128, 0x21, 0 + .dw 0x20c0, 0xc128, 0x20ff, 0xc128, 0x21, 0 + .dw 0x2140, 0xc128, 0x217f, 0xc128, 0x21, 0 + .dw 0x21c0, 0xc128, 0x21ff, 0xc128, 0x21, 0 + .dw 0x2240, 0xc128, 0x227f, 0xc128, 0x21, 0 + .dw 0x22c0, 0xc128, 0x22ff, 0xc128, 0x21, 0 + .dw 0x2340, 0xc128, 0x237f, 0xc128, 0x21, 0 + .dw 0x23c0, 0xc128, 0x23ff, 0xc128, 0x21, 0 + .dw 0x2440, 0xc128, 0x247f, 0xc128, 0x21, 0 + .dw 0x24c0, 0xc128, 0x24ff, 0xc128, 0x21, 0 + .dw 0x2540, 0xc128, 0x257f, 0xc128, 0x21, 0 + .dw 0x25c0, 0xc128, 0x25ff, 0xc128, 0x21, 0 + .dw 0x2640, 0xc128, 0x267f, 0xc128, 0x21, 0 + .dw 0x26c0, 0xc128, 0x26ff, 0xc128, 0x21, 0 + .dw 0x2740, 0xc128, 0x277f, 0xc128, 0x21, 0 + .dw 0x27c0, 0xc128, 0x27ff, 0xc128, 0x21, 0 + .dw 0x2840, 0xc128, 0x287f, 0xc128, 0x21, 0 + .dw 0x28c0, 0xc128, 0x28ff, 0xc128, 0x21, 0 + .dw 0x2940, 0xc128, 0x297f, 0xc128, 0x21, 0 + .dw 0x29c0, 0xc128, 0x29ff, 0xc128, 0x21, 0 + .dw 0x2a40, 0xc128, 0x2a7f, 0xc128, 0x21, 0 + .dw 0x2ac0, 0xc128, 0x2aff, 0xc128, 0x21, 0 + .dw 0x2b40, 0xc128, 0x2b7f, 0xc128, 0x21, 0 + .dw 0x2bc0, 0xc128, 0x2bff, 0xc128, 0x21, 0 + .dw 0x2c40, 0xc128, 0x2c7f, 0xc128, 0x21, 0 + .dw 0x2cc0, 0xc128, 0x2cff, 0xc128, 0x21, 0 + .dw 0x2d40, 0xc128, 0x2d7f, 0xc128, 0x21, 0 + .dw 0x2dc0, 0xc128, 0x2dff, 0xc128, 0x21, 0 + .dw 0x2e40, 0xc128, 0x2e7f, 0xc128, 0x21, 0 + .dw 0x2ec0, 0xc128, 0x2eff, 0xc128, 0x21, 0 + .dw 0x2f40, 0xc128, 0x2f7f, 0xc128, 0x21, 0 + .dw 0x2fc0, 0xc128, 0x2fff, 0xc128, 0x21, 0 + .dw 0x3040, 0xc128, 0x307f, 0xc128, 0x21, 0 + .dw 0x30c0, 0xc128, 0x30ff, 0xc128, 0x21, 0 + .dw 0x3140, 0xc128, 0x317f, 0xc128, 0x21, 0 + .dw 0x31c0, 0xc128, 0x31ff, 0xc128, 0x21, 0 + .dw 0x3240, 0xc128, 0x327f, 0xc128, 0x21, 0 + .dw 0x32c0, 0xc128, 0x32ff, 0xc128, 0x21, 0 + .dw 0x3340, 0xc128, 0x337f, 0xc128, 0x21, 0 + .dw 0x33c0, 0xc128, 0x33ff, 0xc128, 0x21, 0 + .dw 0x3440, 0xc128, 0x347f, 0xc128, 0x21, 0 + .dw 0x34c0, 0xc128, 0x34ff, 0xc128, 0x21, 0 + .dw 0x3540, 0xc128, 0x357f, 0xc128, 0x21, 0 + .dw 0x35c0, 0xc128, 0x35ff, 0xc128, 0x21, 0 + .dw 0x3640, 0xc128, 0x367f, 0xc128, 0x21, 0 + .dw 0x36c0, 0xc128, 0x36ff, 0xc128, 0x21, 0 + .dw 0x3740, 0xc128, 0x377f, 0xc128, 0x21, 0 + .dw 0x37c0, 0xc128, 0x37ff, 0xc128, 0x21, 0 + .dw 0x3840, 0xc128, 0x387f, 0xc128, 0x21, 0 + .dw 0x38c0, 0xc128, 0x38ff, 0xc128, 0x21, 0 + .dw 0x3940, 0xc128, 0x397f, 0xc128, 0x21, 0 + .dw 0x39c0, 0xc128, 0x5fff, 0xc128, 0x21, 0 + .dw 0x6040, 0xc128, 0x607f, 0xc128, 0x21, 0 + .dw 0x60c0, 0xc128, 0x60ff, 0xc128, 0x21, 0 + .dw 0x6140, 0xc128, 0x617f, 0xc128, 0x21, 0 + .dw 0x61c0, 0xc128, 0x61ff, 0xc128, 0x21, 0 + .dw 0x6240, 0xc128, 0x627f, 0xc128, 0x21, 0 + .dw 0x62c0, 0xc128, 0x62ff, 0xc128, 0x21, 0 + .dw 0x6340, 0xc128, 0x637f, 0xc128, 0x21, 0 + .dw 0x63c0, 0xc128, 0x63ff, 0xc128, 0x21, 0 + .dw 0x6440, 0xc128, 0x647f, 0xc128, 0x21, 0 + .dw 0x64c0, 0xc128, 0x64ff, 0xc128, 0x21, 0 + .dw 0x6540, 0xc128, 0x657f, 0xc128, 0x21, 0 + .dw 0x65c0, 0xc128, 0x65ff, 0xc128, 0x21, 0 + .dw 0x6640, 0xc128, 0x667f, 0xc128, 0x21, 0 + .dw 0x66c0, 0xc128, 0x66ff, 0xc128, 0x21, 0 + .dw 0x6740, 0xc128, 0x677f, 0xc128, 0x21, 0 + .dw 0x67c0, 0xc128, 0x67ff, 0xc128, 0x21, 0 + .dw 0x6840, 0xc128, 0x687f, 0xc128, 0x21, 0 + .dw 0x68c0, 0xc128, 0x68ff, 0xc128, 0x21, 0 + .dw 0x6940, 0xc128, 0x697f, 0xc128, 0x21, 0 + .dw 0x69c0, 0xc128, 0x69ff, 0xc128, 0x21, 0 + .dw 0x6a40, 0xc128, 0x6a7f, 0xc128, 0x21, 0 + .dw 0x6ac0, 0xc128, 0x6aff, 0xc128, 0x21, 0 + .dw 0x6b40, 0xc128, 0x6b7f, 0xc128, 0x21, 0 + .dw 0x6bc0, 0xc128, 0x6bff, 0xc128, 0x21, 0 + .dw 0x6c40, 0xc128, 0x6c7f, 0xc128, 0x21, 0 + .dw 0x6cc0, 0xc128, 0x6cff, 0xc128, 0x21, 0 + .dw 0x6d40, 0xc128, 0x6d7f, 0xc128, 0x21, 0 + .dw 0x6dc0, 0xc128, 0x6dff, 0xc128, 0x21, 0 + .dw 0x6e40, 0xc128, 0x6e7f, 0xc128, 0x21, 0 + .dw 0x6ec0, 0xc128, 0x6eff, 0xc128, 0x21, 0 + .dw 0x6f40, 0xc128, 0x6f7f, 0xc128, 0x21, 0 + .dw 0x6fc0, 0xc128, 0x6fff, 0xc128, 0x21, 0 + .dw 0x7040, 0xc128, 0x707f, 0xc128, 0x21, 0 + .dw 0x70c0, 0xc128, 0x70ff, 0xc128, 0x21, 0 + .dw 0x7140, 0xc128, 0x717f, 0xc128, 0x21, 0 + .dw 0x71c0, 0xc128, 0x71ff, 0xc128, 0x21, 0 + .dw 0x7240, 0xc128, 0x727f, 0xc128, 0x21, 0 + .dw 0x72c0, 0xc128, 0x72ff, 0xc128, 0x21, 0 + .dw 0x7340, 0xc128, 0x737f, 0xc128, 0x21, 0 + .dw 0x73c0, 0xc128, 0x73ff, 0xc128, 0x21, 0 + .dw 0x7440, 0xc128, 0x747f, 0xc128, 0x21, 0 + .dw 0x74c0, 0xc128, 0x74ff, 0xc128, 0x21, 0 + .dw 0x7540, 0xc128, 0x757f, 0xc128, 0x21, 0 + .dw 0x75c0, 0xc128, 0x75ff, 0xc128, 0x21, 0 + .dw 0x7640, 0xc128, 0x767f, 0xc128, 0x21, 0 + .dw 0x76c0, 0xc128, 0x76ff, 0xc128, 0x21, 0 + .dw 0x7740, 0xc128, 0x777f, 0xc128, 0x21, 0 + .dw 0x77c0, 0xc128, 0x77ff, 0xc128, 0x21, 0 + .dw 0x7840, 0xc128, 0x787f, 0xc128, 0x21, 0 + .dw 0x78c0, 0xc128, 0x78ff, 0xc128, 0x21, 0 + .dw 0x7940, 0xc128, 0x797f, 0xc128, 0x21, 0 + .dw 0x79c0, 0xc128, 0x9fff, 0xc128, 0x21, 0 + .dw 0xa040, 0xc128, 0xa07f, 0xc128, 0x21, 0 + .dw 0xa0c0, 0xc128, 0xa0ff, 0xc128, 0x21, 0 + .dw 0xa140, 0xc128, 0xa17f, 0xc128, 0x21, 0 + .dw 0xa1c0, 0xc128, 0xa1ff, 0xc128, 0x21, 0 + .dw 0xa240, 0xc128, 0xa27f, 0xc128, 0x21, 0 + .dw 0xa2c0, 0xc128, 0xa2ff, 0xc128, 0x21, 0 + .dw 0xa340, 0xc128, 0xa37f, 0xc128, 0x21, 0 + .dw 0xa3c0, 0xc128, 0xa3ff, 0xc128, 0x21, 0 + .dw 0xa440, 0xc128, 0xa47f, 0xc128, 0x21, 0 + .dw 0xa4c0, 0xc128, 0xa4ff, 0xc128, 0x21, 0 + .dw 0xa540, 0xc128, 0xa57f, 0xc128, 0x21, 0 + .dw 0xa5c0, 0xc128, 0xa5ff, 0xc128, 0x21, 0 + .dw 0xa640, 0xc128, 0xa67f, 0xc128, 0x21, 0 + .dw 0xa6c0, 0xc128, 0xa6ff, 0xc128, 0x21, 0 + .dw 0xa740, 0xc128, 0xa77f, 0xc128, 0x21, 0 + .dw 0xa7c0, 0xc128, 0xa7ff, 0xc128, 0x21, 0 + .dw 0xa840, 0xc128, 0xa87f, 0xc128, 0x21, 0 + .dw 0xa8c0, 0xc128, 0xa8ff, 0xc128, 0x21, 0 + .dw 0xa940, 0xc128, 0xa97f, 0xc128, 0x21, 0 + .dw 0xa9c0, 0xc128, 0xa9ff, 0xc128, 0x21, 0 + .dw 0xaa40, 0xc128, 0xaa7f, 0xc128, 0x21, 0 + .dw 0xaac0, 0xc128, 0xaaff, 0xc128, 0x21, 0 + .dw 0xab40, 0xc128, 0xab7f, 0xc128, 0x21, 0 + .dw 0xabc0, 0xc128, 0xabff, 0xc128, 0x21, 0 + .dw 0xac40, 0xc128, 0xac7f, 0xc128, 0x21, 0 + .dw 0xacc0, 0xc128, 0xacff, 0xc128, 0x21, 0 + .dw 0xad40, 0xc128, 0xad7f, 0xc128, 0x21, 0 + .dw 0xadc0, 0xc128, 0xadff, 0xc128, 0x21, 0 + .dw 0xae40, 0xc128, 0xae7f, 0xc128, 0x21, 0 + .dw 0xaec0, 0xc128, 0xaeff, 0xc128, 0x21, 0 + .dw 0xaf40, 0xc128, 0xaf7f, 0xc128, 0x21, 0 + .dw 0xafc0, 0xc128, 0xafff, 0xc128, 0x21, 0 + .dw 0xb040, 0xc128, 0xb07f, 0xc128, 0x21, 0 + .dw 0xb0c0, 0xc128, 0xb0ff, 0xc128, 0x21, 0 + .dw 0xb140, 0xc128, 0xb17f, 0xc128, 0x21, 0 + .dw 0xb1c0, 0xc128, 0xb1ff, 0xc128, 0x21, 0 + .dw 0xb240, 0xc128, 0xb27f, 0xc128, 0x21, 0 + .dw 0xb2c0, 0xc128, 0xb2ff, 0xc128, 0x21, 0 + .dw 0xb340, 0xc128, 0xb37f, 0xc128, 0x21, 0 + .dw 0xb3c0, 0xc128, 0xb3ff, 0xc128, 0x21, 0 + .dw 0xb440, 0xc128, 0xb47f, 0xc128, 0x21, 0 + .dw 0xb4c0, 0xc128, 0xb4ff, 0xc128, 0x21, 0 + .dw 0xb540, 0xc128, 0xb57f, 0xc128, 0x21, 0 + .dw 0xb5c0, 0xc128, 0xb5ff, 0xc128, 0x21, 0 + .dw 0xb640, 0xc128, 0xb67f, 0xc128, 0x21, 0 + .dw 0xb6c0, 0xc128, 0xb6ff, 0xc128, 0x21, 0 + .dw 0xb740, 0xc128, 0xb77f, 0xc128, 0x21, 0 + .dw 0xb7c0, 0xc128, 0xb7ff, 0xc128, 0x21, 0 + .dw 0xb840, 0xc128, 0xb87f, 0xc128, 0x21, 0 + .dw 0xb8c0, 0xc128, 0xb8ff, 0xc128, 0x21, 0 + .dw 0xb940, 0xc128, 0xb97f, 0xc128, 0x21, 0 + .dw 0xb9c0, 0xc128, 0xdfff, 0xc128, 0x21, 0 + .dw 0xe040, 0xc128, 0xe07f, 0xc128, 0x21, 0 + .dw 0xe0c0, 0xc128, 0xe0ff, 0xc128, 0x21, 0 + .dw 0xe140, 0xc128, 0xe17f, 0xc128, 0x21, 0 + .dw 0xe1c0, 0xc128, 0xe1ff, 0xc128, 0x21, 0 + .dw 0xe240, 0xc128, 0xe27f, 0xc128, 0x21, 0 + .dw 0xe2c0, 0xc128, 0xe2ff, 0xc128, 0x21, 0 + .dw 0xe340, 0xc128, 0xe37f, 0xc128, 0x21, 0 + .dw 0xe3c0, 0xc128, 0xe3ff, 0xc128, 0x21, 0 + .dw 0xe440, 0xc128, 0xe47f, 0xc128, 0x21, 0 + .dw 0xe4c0, 0xc128, 0xe4ff, 0xc128, 0x21, 0 + .dw 0xe540, 0xc128, 0xe57f, 0xc128, 0x21, 0 + .dw 0xe5c0, 0xc128, 0xe5ff, 0xc128, 0x21, 0 + .dw 0xe640, 0xc128, 0xe67f, 0xc128, 0x21, 0 + .dw 0xe6c0, 0xc128, 0xe6ff, 0xc128, 0x21, 0 + .dw 0xe740, 0xc128, 0xe77f, 0xc128, 0x21, 0 + .dw 0xe7c0, 0xc128, 0xe7ff, 0xc128, 0x21, 0 + .dw 0xe840, 0xc128, 0xe87f, 0xc128, 0x21, 0 + .dw 0xe8c0, 0xc128, 0xe8ff, 0xc128, 0x21, 0 + .dw 0xe940, 0xc128, 0xe97f, 0xc128, 0x21, 0 + .dw 0xe9c0, 0xc128, 0xe9ff, 0xc128, 0x21, 0 + .dw 0xea40, 0xc128, 0xea7f, 0xc128, 0x21, 0 + .dw 0xeac0, 0xc128, 0xeaff, 0xc128, 0x21, 0 + .dw 0xeb40, 0xc128, 0xeb7f, 0xc128, 0x21, 0 + .dw 0xebc0, 0xc128, 0xebff, 0xc128, 0x21, 0 + .dw 0xec40, 0xc128, 0xec7f, 0xc128, 0x21, 0 + .dw 0xecc0, 0xc128, 0xecff, 0xc128, 0x21, 0 + .dw 0xed40, 0xc128, 0xed7f, 0xc128, 0x21, 0 + .dw 0xedc0, 0xc128, 0xedff, 0xc128, 0x21, 0 + .dw 0xee40, 0xc128, 0xee7f, 0xc128, 0x21, 0 + .dw 0xeec0, 0xc128, 0xeeff, 0xc128, 0x21, 0 + .dw 0xef40, 0xc128, 0xef7f, 0xc128, 0x21, 0 + .dw 0xefc0, 0xc128, 0xefff, 0xc128, 0x21, 0 + .dw 0xf040, 0xc128, 0xf07f, 0xc128, 0x21, 0 + .dw 0xf0c0, 0xc128, 0xf0ff, 0xc128, 0x21, 0 + .dw 0xf140, 0xc128, 0xf17f, 0xc128, 0x21, 0 + .dw 0xf1c0, 0xc128, 0xf1ff, 0xc128, 0x21, 0 + .dw 0xf240, 0xc128, 0xf27f, 0xc128, 0x21, 0 + .dw 0xf2c0, 0xc128, 0xf2ff, 0xc128, 0x21, 0 + .dw 0xf340, 0xc128, 0xf37f, 0xc128, 0x21, 0 + .dw 0xf3c0, 0xc128, 0xf3ff, 0xc128, 0x21, 0 + .dw 0xf440, 0xc128, 0xf47f, 0xc128, 0x21, 0 + .dw 0xf4c0, 0xc128, 0xf4ff, 0xc128, 0x21, 0 + .dw 0xf540, 0xc128, 0xf57f, 0xc128, 0x21, 0 + .dw 0xf5c0, 0xc128, 0xf5ff, 0xc128, 0x21, 0 + .dw 0xf640, 0xc128, 0xf67f, 0xc128, 0x21, 0 + .dw 0xf6c0, 0xc128, 0xf6ff, 0xc128, 0x21, 0 + .dw 0xf740, 0xc128, 0xf77f, 0xc128, 0x21, 0 + .dw 0xf7c0, 0xc128, 0xf7ff, 0xc128, 0x21, 0 + .dw 0xf840, 0xc128, 0xf87f, 0xc128, 0x21, 0 + .dw 0xf8c0, 0xc128, 0xf8ff, 0xc128, 0x21, 0 + .dw 0xf940, 0xc128, 0xf97f, 0xc128, 0x21, 0 + .dw 0xf9c0, 0xc128, 0x1fff, 0xc129, 0x21, 0 + .dw 0x2040, 0xc129, 0x207f, 0xc129, 0x21, 0 + .dw 0x20c0, 0xc129, 0x20ff, 0xc129, 0x21, 0 + .dw 0x2140, 0xc129, 0x217f, 0xc129, 0x21, 0 + .dw 0x21c0, 0xc129, 0x21ff, 0xc129, 0x21, 0 + .dw 0x2240, 0xc129, 0x227f, 0xc129, 0x21, 0 + .dw 0x22c0, 0xc129, 0x22ff, 0xc129, 0x21, 0 + .dw 0x2340, 0xc129, 0x237f, 0xc129, 0x21, 0 + .dw 0x23c0, 0xc129, 0x23ff, 0xc129, 0x21, 0 + .dw 0x2440, 0xc129, 0x247f, 0xc129, 0x21, 0 + .dw 0x24c0, 0xc129, 0x24ff, 0xc129, 0x21, 0 + .dw 0x2540, 0xc129, 0x257f, 0xc129, 0x21, 0 + .dw 0x25c0, 0xc129, 0x25ff, 0xc129, 0x21, 0 + .dw 0x2640, 0xc129, 0x267f, 0xc129, 0x21, 0 + .dw 0x26c0, 0xc129, 0x26ff, 0xc129, 0x21, 0 + .dw 0x2740, 0xc129, 0x277f, 0xc129, 0x21, 0 + .dw 0x27c0, 0xc129, 0x27ff, 0xc129, 0x21, 0 + .dw 0x2840, 0xc129, 0x287f, 0xc129, 0x21, 0 + .dw 0x28c0, 0xc129, 0x28ff, 0xc129, 0x21, 0 + .dw 0x2940, 0xc129, 0x297f, 0xc129, 0x21, 0 + .dw 0x29c0, 0xc129, 0x29ff, 0xc129, 0x21, 0 + .dw 0x2a40, 0xc129, 0x2a7f, 0xc129, 0x21, 0 + .dw 0x2ac0, 0xc129, 0x2aff, 0xc129, 0x21, 0 + .dw 0x2b40, 0xc129, 0x2b7f, 0xc129, 0x21, 0 + .dw 0x2bc0, 0xc129, 0x2bff, 0xc129, 0x21, 0 + .dw 0x2c40, 0xc129, 0x2c7f, 0xc129, 0x21, 0 + .dw 0x2cc0, 0xc129, 0x2cff, 0xc129, 0x21, 0 + .dw 0x2d40, 0xc129, 0x2d7f, 0xc129, 0x21, 0 + .dw 0x2dc0, 0xc129, 0x2dff, 0xc129, 0x21, 0 + .dw 0x2e40, 0xc129, 0x2e7f, 0xc129, 0x21, 0 + .dw 0x2ec0, 0xc129, 0x2eff, 0xc129, 0x21, 0 + .dw 0x2f40, 0xc129, 0x2f7f, 0xc129, 0x21, 0 + .dw 0x2fc0, 0xc129, 0x2fff, 0xc129, 0x21, 0 + .dw 0x3040, 0xc129, 0x307f, 0xc129, 0x21, 0 + .dw 0x30c0, 0xc129, 0x30ff, 0xc129, 0x21, 0 + .dw 0x3140, 0xc129, 0x317f, 0xc129, 0x21, 0 + .dw 0x31c0, 0xc129, 0x31ff, 0xc129, 0x21, 0 + .dw 0x3240, 0xc129, 0x327f, 0xc129, 0x21, 0 + .dw 0x32c0, 0xc129, 0x32ff, 0xc129, 0x21, 0 + .dw 0x3340, 0xc129, 0x337f, 0xc129, 0x21, 0 + .dw 0x33c0, 0xc129, 0x33ff, 0xc129, 0x21, 0 + .dw 0x3440, 0xc129, 0x347f, 0xc129, 0x21, 0 + .dw 0x34c0, 0xc129, 0x34ff, 0xc129, 0x21, 0 + .dw 0x3540, 0xc129, 0x357f, 0xc129, 0x21, 0 + .dw 0x35c0, 0xc129, 0x35ff, 0xc129, 0x21, 0 + .dw 0x3640, 0xc129, 0x367f, 0xc129, 0x21, 0 + .dw 0x36c0, 0xc129, 0x36ff, 0xc129, 0x21, 0 + .dw 0x3740, 0xc129, 0x377f, 0xc129, 0x21, 0 + .dw 0x37c0, 0xc129, 0x37ff, 0xc129, 0x21, 0 + .dw 0x3840, 0xc129, 0x387f, 0xc129, 0x21, 0 + .dw 0x38c0, 0xc129, 0x38ff, 0xc129, 0x21, 0 + .dw 0x3940, 0xc129, 0x397f, 0xc129, 0x21, 0 + .dw 0x39c0, 0xc129, 0x5fff, 0xc129, 0x21, 0 + .dw 0x6040, 0xc129, 0x607f, 0xc129, 0x21, 0 + .dw 0x60c0, 0xc129, 0x60ff, 0xc129, 0x21, 0 + .dw 0x6140, 0xc129, 0x617f, 0xc129, 0x21, 0 + .dw 0x61c0, 0xc129, 0x61ff, 0xc129, 0x21, 0 + .dw 0x6240, 0xc129, 0x627f, 0xc129, 0x21, 0 + .dw 0x62c0, 0xc129, 0x62ff, 0xc129, 0x21, 0 + .dw 0x6340, 0xc129, 0x637f, 0xc129, 0x21, 0 + .dw 0x63c0, 0xc129, 0x63ff, 0xc129, 0x21, 0 + .dw 0x6440, 0xc129, 0x647f, 0xc129, 0x21, 0 + .dw 0x64c0, 0xc129, 0x64ff, 0xc129, 0x21, 0 + .dw 0x6540, 0xc129, 0x657f, 0xc129, 0x21, 0 + .dw 0x65c0, 0xc129, 0x65ff, 0xc129, 0x21, 0 + .dw 0x6640, 0xc129, 0x667f, 0xc129, 0x21, 0 + .dw 0x66c0, 0xc129, 0x66ff, 0xc129, 0x21, 0 + .dw 0x6740, 0xc129, 0x677f, 0xc129, 0x21, 0 + .dw 0x67c0, 0xc129, 0x67ff, 0xc129, 0x21, 0 + .dw 0x6840, 0xc129, 0x687f, 0xc129, 0x21, 0 + .dw 0x68c0, 0xc129, 0x68ff, 0xc129, 0x21, 0 + .dw 0x6940, 0xc129, 0x697f, 0xc129, 0x21, 0 + .dw 0x69c0, 0xc129, 0x69ff, 0xc129, 0x21, 0 + .dw 0x6a40, 0xc129, 0x6a7f, 0xc129, 0x21, 0 + .dw 0x6ac0, 0xc129, 0x6aff, 0xc129, 0x21, 0 + .dw 0x6b40, 0xc129, 0x6b7f, 0xc129, 0x21, 0 + .dw 0x6bc0, 0xc129, 0x6bff, 0xc129, 0x21, 0 + .dw 0x6c40, 0xc129, 0x6c7f, 0xc129, 0x21, 0 + .dw 0x6cc0, 0xc129, 0x6cff, 0xc129, 0x21, 0 + .dw 0x6d40, 0xc129, 0x6d7f, 0xc129, 0x21, 0 + .dw 0x6dc0, 0xc129, 0x6dff, 0xc129, 0x21, 0 + .dw 0x6e40, 0xc129, 0x6e7f, 0xc129, 0x21, 0 + .dw 0x6ec0, 0xc129, 0x6eff, 0xc129, 0x21, 0 + .dw 0x6f40, 0xc129, 0x6f7f, 0xc129, 0x21, 0 + .dw 0x6fc0, 0xc129, 0x6fff, 0xc129, 0x21, 0 + .dw 0x7040, 0xc129, 0x707f, 0xc129, 0x21, 0 + .dw 0x70c0, 0xc129, 0x70ff, 0xc129, 0x21, 0 + .dw 0x7140, 0xc129, 0x717f, 0xc129, 0x21, 0 + .dw 0x71c0, 0xc129, 0x71ff, 0xc129, 0x21, 0 + .dw 0x7240, 0xc129, 0x727f, 0xc129, 0x21, 0 + .dw 0x72c0, 0xc129, 0x72ff, 0xc129, 0x21, 0 + .dw 0x7340, 0xc129, 0x737f, 0xc129, 0x21, 0 + .dw 0x73c0, 0xc129, 0x73ff, 0xc129, 0x21, 0 + .dw 0x7440, 0xc129, 0x747f, 0xc129, 0x21, 0 + .dw 0x74c0, 0xc129, 0x74ff, 0xc129, 0x21, 0 + .dw 0x7540, 0xc129, 0x757f, 0xc129, 0x21, 0 + .dw 0x75c0, 0xc129, 0x75ff, 0xc129, 0x21, 0 + .dw 0x7640, 0xc129, 0x767f, 0xc129, 0x21, 0 + .dw 0x76c0, 0xc129, 0x76ff, 0xc129, 0x21, 0 + .dw 0x7740, 0xc129, 0x777f, 0xc129, 0x21, 0 + .dw 0x77c0, 0xc129, 0x77ff, 0xc129, 0x21, 0 + .dw 0x7840, 0xc129, 0x787f, 0xc129, 0x21, 0 + .dw 0x78c0, 0xc129, 0x78ff, 0xc129, 0x21, 0 + .dw 0x7940, 0xc129, 0x797f, 0xc129, 0x21, 0 + .dw 0x79c0, 0xc129, 0x9fff, 0xc129, 0x21, 0 + .dw 0xa040, 0xc129, 0xa07f, 0xc129, 0x21, 0 + .dw 0xa0c0, 0xc129, 0xa0ff, 0xc129, 0x21, 0 + .dw 0xa140, 0xc129, 0xa17f, 0xc129, 0x21, 0 + .dw 0xa1c0, 0xc129, 0xa1ff, 0xc129, 0x21, 0 + .dw 0xa240, 0xc129, 0xa27f, 0xc129, 0x21, 0 + .dw 0xa2c0, 0xc129, 0xa2ff, 0xc129, 0x21, 0 + .dw 0xa340, 0xc129, 0xa37f, 0xc129, 0x21, 0 + .dw 0xa3c0, 0xc129, 0xa3ff, 0xc129, 0x21, 0 + .dw 0xa440, 0xc129, 0xa47f, 0xc129, 0x21, 0 + .dw 0xa4c0, 0xc129, 0xa4ff, 0xc129, 0x21, 0 + .dw 0xa540, 0xc129, 0xa57f, 0xc129, 0x21, 0 + .dw 0xa5c0, 0xc129, 0xa5ff, 0xc129, 0x21, 0 + .dw 0xa640, 0xc129, 0xa67f, 0xc129, 0x21, 0 + .dw 0xa6c0, 0xc129, 0xa6ff, 0xc129, 0x21, 0 + .dw 0xa740, 0xc129, 0xa77f, 0xc129, 0x21, 0 + .dw 0xa7c0, 0xc129, 0xa7ff, 0xc129, 0x21, 0 + .dw 0xa840, 0xc129, 0xa87f, 0xc129, 0x21, 0 + .dw 0xa8c0, 0xc129, 0xa8ff, 0xc129, 0x21, 0 + .dw 0xa940, 0xc129, 0xa97f, 0xc129, 0x21, 0 + .dw 0xa9c0, 0xc129, 0xa9ff, 0xc129, 0x21, 0 + .dw 0xaa40, 0xc129, 0xaa7f, 0xc129, 0x21, 0 + .dw 0xaac0, 0xc129, 0xaaff, 0xc129, 0x21, 0 + .dw 0xab40, 0xc129, 0xab7f, 0xc129, 0x21, 0 + .dw 0xabc0, 0xc129, 0xabff, 0xc129, 0x21, 0 + .dw 0xac40, 0xc129, 0xac7f, 0xc129, 0x21, 0 + .dw 0xacc0, 0xc129, 0xacff, 0xc129, 0x21, 0 + .dw 0xad40, 0xc129, 0xad7f, 0xc129, 0x21, 0 + .dw 0xadc0, 0xc129, 0xadff, 0xc129, 0x21, 0 + .dw 0xae40, 0xc129, 0xae7f, 0xc129, 0x21, 0 + .dw 0xaec0, 0xc129, 0xaeff, 0xc129, 0x21, 0 + .dw 0xaf40, 0xc129, 0xaf7f, 0xc129, 0x21, 0 + .dw 0xafc0, 0xc129, 0xafff, 0xc129, 0x21, 0 + .dw 0xb040, 0xc129, 0xb07f, 0xc129, 0x21, 0 + .dw 0xb0c0, 0xc129, 0xb0ff, 0xc129, 0x21, 0 + .dw 0xb140, 0xc129, 0xb17f, 0xc129, 0x21, 0 + .dw 0xb1c0, 0xc129, 0xb1ff, 0xc129, 0x21, 0 + .dw 0xb240, 0xc129, 0xb27f, 0xc129, 0x21, 0 + .dw 0xb2c0, 0xc129, 0xb2ff, 0xc129, 0x21, 0 + .dw 0xb340, 0xc129, 0xb37f, 0xc129, 0x21, 0 + .dw 0xb3c0, 0xc129, 0xb3ff, 0xc129, 0x21, 0 + .dw 0xb440, 0xc129, 0xb47f, 0xc129, 0x21, 0 + .dw 0xb4c0, 0xc129, 0xb4ff, 0xc129, 0x21, 0 + .dw 0xb540, 0xc129, 0xb57f, 0xc129, 0x21, 0 + .dw 0xb5c0, 0xc129, 0xb5ff, 0xc129, 0x21, 0 + .dw 0xb640, 0xc129, 0xb67f, 0xc129, 0x21, 0 + .dw 0xb6c0, 0xc129, 0xb6ff, 0xc129, 0x21, 0 + .dw 0xb740, 0xc129, 0xb77f, 0xc129, 0x21, 0 + .dw 0xb7c0, 0xc129, 0xb7ff, 0xc129, 0x21, 0 + .dw 0xb840, 0xc129, 0xb87f, 0xc129, 0x21, 0 + .dw 0xb8c0, 0xc129, 0xb8ff, 0xc129, 0x21, 0 + .dw 0xb940, 0xc129, 0xb97f, 0xc129, 0x21, 0 + .dw 0xb9c0, 0xc129, 0xdfff, 0xc129, 0x21, 0 + .dw 0xe040, 0xc129, 0xe07f, 0xc129, 0x21, 0 + .dw 0xe0c0, 0xc129, 0xe0ff, 0xc129, 0x21, 0 + .dw 0xe140, 0xc129, 0xe17f, 0xc129, 0x21, 0 + .dw 0xe1c0, 0xc129, 0xe1ff, 0xc129, 0x21, 0 + .dw 0xe240, 0xc129, 0xe27f, 0xc129, 0x21, 0 + .dw 0xe2c0, 0xc129, 0xe2ff, 0xc129, 0x21, 0 + .dw 0xe340, 0xc129, 0xe37f, 0xc129, 0x21, 0 + .dw 0xe3c0, 0xc129, 0xe3ff, 0xc129, 0x21, 0 + .dw 0xe440, 0xc129, 0xe47f, 0xc129, 0x21, 0 + .dw 0xe4c0, 0xc129, 0xe4ff, 0xc129, 0x21, 0 + .dw 0xe540, 0xc129, 0xe57f, 0xc129, 0x21, 0 + .dw 0xe5c0, 0xc129, 0xe5ff, 0xc129, 0x21, 0 + .dw 0xe640, 0xc129, 0xe67f, 0xc129, 0x21, 0 + .dw 0xe6c0, 0xc129, 0xe6ff, 0xc129, 0x21, 0 + .dw 0xe740, 0xc129, 0xe77f, 0xc129, 0x21, 0 + .dw 0xe7c0, 0xc129, 0xe7ff, 0xc129, 0x21, 0 + .dw 0xe840, 0xc129, 0xe87f, 0xc129, 0x21, 0 + .dw 0xe8c0, 0xc129, 0xe8ff, 0xc129, 0x21, 0 + .dw 0xe940, 0xc129, 0xe97f, 0xc129, 0x21, 0 + .dw 0xe9c0, 0xc129, 0xe9ff, 0xc129, 0x21, 0 + .dw 0xea40, 0xc129, 0xea7f, 0xc129, 0x21, 0 + .dw 0xeac0, 0xc129, 0xeaff, 0xc129, 0x21, 0 + .dw 0xeb40, 0xc129, 0xeb7f, 0xc129, 0x21, 0 + .dw 0xebc0, 0xc129, 0xebff, 0xc129, 0x21, 0 + .dw 0xec40, 0xc129, 0xec7f, 0xc129, 0x21, 0 + .dw 0xecc0, 0xc129, 0xecff, 0xc129, 0x21, 0 + .dw 0xed40, 0xc129, 0xed7f, 0xc129, 0x21, 0 + .dw 0xedc0, 0xc129, 0xedff, 0xc129, 0x21, 0 + .dw 0xee40, 0xc129, 0xee7f, 0xc129, 0x21, 0 + .dw 0xeec0, 0xc129, 0xeeff, 0xc129, 0x21, 0 + .dw 0xef40, 0xc129, 0xef7f, 0xc129, 0x21, 0 + .dw 0xefc0, 0xc129, 0xefff, 0xc129, 0x21, 0 + .dw 0xf040, 0xc129, 0xf07f, 0xc129, 0x21, 0 + .dw 0xf0c0, 0xc129, 0xf0ff, 0xc129, 0x21, 0 + .dw 0xf140, 0xc129, 0xf17f, 0xc129, 0x21, 0 + .dw 0xf1c0, 0xc129, 0xf1ff, 0xc129, 0x21, 0 + .dw 0xf240, 0xc129, 0xf27f, 0xc129, 0x21, 0 + .dw 0xf2c0, 0xc129, 0xf2ff, 0xc129, 0x21, 0 + .dw 0xf340, 0xc129, 0xf37f, 0xc129, 0x21, 0 + .dw 0xf3c0, 0xc129, 0xf3ff, 0xc129, 0x21, 0 + .dw 0xf440, 0xc129, 0xf47f, 0xc129, 0x21, 0 + .dw 0xf4c0, 0xc129, 0xf4ff, 0xc129, 0x21, 0 + .dw 0xf540, 0xc129, 0xf57f, 0xc129, 0x21, 0 + .dw 0xf5c0, 0xc129, 0xf5ff, 0xc129, 0x21, 0 + .dw 0xf640, 0xc129, 0xf67f, 0xc129, 0x21, 0 + .dw 0xf6c0, 0xc129, 0xf6ff, 0xc129, 0x21, 0 + .dw 0xf740, 0xc129, 0xf77f, 0xc129, 0x21, 0 + .dw 0xf7c0, 0xc129, 0xf7ff, 0xc129, 0x21, 0 + .dw 0xf840, 0xc129, 0xf87f, 0xc129, 0x21, 0 + .dw 0xf8c0, 0xc129, 0xf8ff, 0xc129, 0x21, 0 + .dw 0xf940, 0xc129, 0xf97f, 0xc129, 0x21, 0 + .dw 0xf9c0, 0xc129, 0x1fff, 0xc12a, 0x21, 0 + .dw 0x2040, 0xc12a, 0x207f, 0xc12a, 0x21, 0 + .dw 0x20c0, 0xc12a, 0x20ff, 0xc12a, 0x21, 0 + .dw 0x2140, 0xc12a, 0x217f, 0xc12a, 0x21, 0 + .dw 0x21c0, 0xc12a, 0x21ff, 0xc12a, 0x21, 0 + .dw 0x2240, 0xc12a, 0x227f, 0xc12a, 0x21, 0 + .dw 0x22c0, 0xc12a, 0x22ff, 0xc12a, 0x21, 0 + .dw 0x2340, 0xc12a, 0x237f, 0xc12a, 0x21, 0 + .dw 0x23c0, 0xc12a, 0x23ff, 0xc12a, 0x21, 0 + .dw 0x2440, 0xc12a, 0x247f, 0xc12a, 0x21, 0 + .dw 0x24c0, 0xc12a, 0x24ff, 0xc12a, 0x21, 0 + .dw 0x2540, 0xc12a, 0x257f, 0xc12a, 0x21, 0 + .dw 0x25c0, 0xc12a, 0x25ff, 0xc12a, 0x21, 0 + .dw 0x2640, 0xc12a, 0x267f, 0xc12a, 0x21, 0 + .dw 0x26c0, 0xc12a, 0x26ff, 0xc12a, 0x21, 0 + .dw 0x2740, 0xc12a, 0x277f, 0xc12a, 0x21, 0 + .dw 0x27c0, 0xc12a, 0x27ff, 0xc12a, 0x21, 0 + .dw 0x2840, 0xc12a, 0x287f, 0xc12a, 0x21, 0 + .dw 0x28c0, 0xc12a, 0x28ff, 0xc12a, 0x21, 0 + .dw 0x2940, 0xc12a, 0x297f, 0xc12a, 0x21, 0 + .dw 0x29c0, 0xc12a, 0x29ff, 0xc12a, 0x21, 0 + .dw 0x2a40, 0xc12a, 0x2a7f, 0xc12a, 0x21, 0 + .dw 0x2ac0, 0xc12a, 0x2aff, 0xc12a, 0x21, 0 + .dw 0x2b40, 0xc12a, 0x2b7f, 0xc12a, 0x21, 0 + .dw 0x2bc0, 0xc12a, 0x2bff, 0xc12a, 0x21, 0 + .dw 0x2c40, 0xc12a, 0x2c7f, 0xc12a, 0x21, 0 + .dw 0x2cc0, 0xc12a, 0x2cff, 0xc12a, 0x21, 0 + .dw 0x2d40, 0xc12a, 0x2d7f, 0xc12a, 0x21, 0 + .dw 0x2dc0, 0xc12a, 0x2dff, 0xc12a, 0x21, 0 + .dw 0x2e40, 0xc12a, 0x2e7f, 0xc12a, 0x21, 0 + .dw 0x2ec0, 0xc12a, 0x2eff, 0xc12a, 0x21, 0 + .dw 0x2f40, 0xc12a, 0x2f7f, 0xc12a, 0x21, 0 + .dw 0x2fc0, 0xc12a, 0x2fff, 0xc12a, 0x21, 0 + .dw 0x3040, 0xc12a, 0x307f, 0xc12a, 0x21, 0 + .dw 0x30c0, 0xc12a, 0x30ff, 0xc12a, 0x21, 0 + .dw 0x3140, 0xc12a, 0x317f, 0xc12a, 0x21, 0 + .dw 0x31c0, 0xc12a, 0x31ff, 0xc12a, 0x21, 0 + .dw 0x3240, 0xc12a, 0x327f, 0xc12a, 0x21, 0 + .dw 0x32c0, 0xc12a, 0x32ff, 0xc12a, 0x21, 0 + .dw 0x3340, 0xc12a, 0x337f, 0xc12a, 0x21, 0 + .dw 0x33c0, 0xc12a, 0x33ff, 0xc12a, 0x21, 0 + .dw 0x3440, 0xc12a, 0x347f, 0xc12a, 0x21, 0 + .dw 0x34c0, 0xc12a, 0x34ff, 0xc12a, 0x21, 0 + .dw 0x3540, 0xc12a, 0x357f, 0xc12a, 0x21, 0 + .dw 0x35c0, 0xc12a, 0x35ff, 0xc12a, 0x21, 0 + .dw 0x3640, 0xc12a, 0x367f, 0xc12a, 0x21, 0 + .dw 0x36c0, 0xc12a, 0x36ff, 0xc12a, 0x21, 0 + .dw 0x3740, 0xc12a, 0x377f, 0xc12a, 0x21, 0 + .dw 0x37c0, 0xc12a, 0x37ff, 0xc12a, 0x21, 0 + .dw 0x3840, 0xc12a, 0x387f, 0xc12a, 0x21, 0 + .dw 0x38c0, 0xc12a, 0x38ff, 0xc12a, 0x21, 0 + .dw 0x3940, 0xc12a, 0x397f, 0xc12a, 0x21, 0 + .dw 0x39c0, 0xc12a, 0x5fff, 0xc12a, 0x21, 0 + .dw 0x6040, 0xc12a, 0x607f, 0xc12a, 0x21, 0 + .dw 0x60c0, 0xc12a, 0x60ff, 0xc12a, 0x21, 0 + .dw 0x6140, 0xc12a, 0x617f, 0xc12a, 0x21, 0 + .dw 0x61c0, 0xc12a, 0x61ff, 0xc12a, 0x21, 0 + .dw 0x6240, 0xc12a, 0x627f, 0xc12a, 0x21, 0 + .dw 0x62c0, 0xc12a, 0x62ff, 0xc12a, 0x21, 0 + .dw 0x6340, 0xc12a, 0x637f, 0xc12a, 0x21, 0 + .dw 0x63c0, 0xc12a, 0x63ff, 0xc12a, 0x21, 0 + .dw 0x6440, 0xc12a, 0x647f, 0xc12a, 0x21, 0 + .dw 0x64c0, 0xc12a, 0x64ff, 0xc12a, 0x21, 0 + .dw 0x6540, 0xc12a, 0x657f, 0xc12a, 0x21, 0 + .dw 0x65c0, 0xc12a, 0x65ff, 0xc12a, 0x21, 0 + .dw 0x6640, 0xc12a, 0x667f, 0xc12a, 0x21, 0 + .dw 0x66c0, 0xc12a, 0x66ff, 0xc12a, 0x21, 0 + .dw 0x6740, 0xc12a, 0x677f, 0xc12a, 0x21, 0 + .dw 0x67c0, 0xc12a, 0x67ff, 0xc12a, 0x21, 0 + .dw 0x6840, 0xc12a, 0x687f, 0xc12a, 0x21, 0 + .dw 0x68c0, 0xc12a, 0x68ff, 0xc12a, 0x21, 0 + .dw 0x6940, 0xc12a, 0x697f, 0xc12a, 0x21, 0 + .dw 0x69c0, 0xc12a, 0x69ff, 0xc12a, 0x21, 0 + .dw 0x6a40, 0xc12a, 0x6a7f, 0xc12a, 0x21, 0 + .dw 0x6ac0, 0xc12a, 0x6aff, 0xc12a, 0x21, 0 + .dw 0x6b40, 0xc12a, 0x6b7f, 0xc12a, 0x21, 0 + .dw 0x6bc0, 0xc12a, 0x6bff, 0xc12a, 0x21, 0 + .dw 0x6c40, 0xc12a, 0x6c7f, 0xc12a, 0x21, 0 + .dw 0x6cc0, 0xc12a, 0x6cff, 0xc12a, 0x21, 0 + .dw 0x6d40, 0xc12a, 0x6d7f, 0xc12a, 0x21, 0 + .dw 0x6dc0, 0xc12a, 0x6dff, 0xc12a, 0x21, 0 + .dw 0x6e40, 0xc12a, 0x6e7f, 0xc12a, 0x21, 0 + .dw 0x6ec0, 0xc12a, 0x6eff, 0xc12a, 0x21, 0 + .dw 0x6f40, 0xc12a, 0x6f7f, 0xc12a, 0x21, 0 + .dw 0x6fc0, 0xc12a, 0x6fff, 0xc12a, 0x21, 0 + .dw 0x7040, 0xc12a, 0x707f, 0xc12a, 0x21, 0 + .dw 0x70c0, 0xc12a, 0x70ff, 0xc12a, 0x21, 0 + .dw 0x7140, 0xc12a, 0x717f, 0xc12a, 0x21, 0 + .dw 0x71c0, 0xc12a, 0x71ff, 0xc12a, 0x21, 0 + .dw 0x7240, 0xc12a, 0x727f, 0xc12a, 0x21, 0 + .dw 0x72c0, 0xc12a, 0x72ff, 0xc12a, 0x21, 0 + .dw 0x7340, 0xc12a, 0x737f, 0xc12a, 0x21, 0 + .dw 0x73c0, 0xc12a, 0x73ff, 0xc12a, 0x21, 0 + .dw 0x7440, 0xc12a, 0x747f, 0xc12a, 0x21, 0 + .dw 0x74c0, 0xc12a, 0x74ff, 0xc12a, 0x21, 0 + .dw 0x7540, 0xc12a, 0x757f, 0xc12a, 0x21, 0 + .dw 0x75c0, 0xc12a, 0x75ff, 0xc12a, 0x21, 0 + .dw 0x7640, 0xc12a, 0x767f, 0xc12a, 0x21, 0 + .dw 0x76c0, 0xc12a, 0x76ff, 0xc12a, 0x21, 0 + .dw 0x7740, 0xc12a, 0x777f, 0xc12a, 0x21, 0 + .dw 0x77c0, 0xc12a, 0x77ff, 0xc12a, 0x21, 0 + .dw 0x7840, 0xc12a, 0x787f, 0xc12a, 0x21, 0 + .dw 0x78c0, 0xc12a, 0x78ff, 0xc12a, 0x21, 0 + .dw 0x7940, 0xc12a, 0x797f, 0xc12a, 0x21, 0 + .dw 0x79c0, 0xc12a, 0x9fff, 0xc12a, 0x21, 0 + .dw 0xa040, 0xc12a, 0xa07f, 0xc12a, 0x21, 0 + .dw 0xa0c0, 0xc12a, 0xa0ff, 0xc12a, 0x21, 0 + .dw 0xa140, 0xc12a, 0xa17f, 0xc12a, 0x21, 0 + .dw 0xa1c0, 0xc12a, 0xa1ff, 0xc12a, 0x21, 0 + .dw 0xa240, 0xc12a, 0xa27f, 0xc12a, 0x21, 0 + .dw 0xa2c0, 0xc12a, 0xa2ff, 0xc12a, 0x21, 0 + .dw 0xa340, 0xc12a, 0xa37f, 0xc12a, 0x21, 0 + .dw 0xa3c0, 0xc12a, 0xa3ff, 0xc12a, 0x21, 0 + .dw 0xa440, 0xc12a, 0xa47f, 0xc12a, 0x21, 0 + .dw 0xa4c0, 0xc12a, 0xa4ff, 0xc12a, 0x21, 0 + .dw 0xa540, 0xc12a, 0xa57f, 0xc12a, 0x21, 0 + .dw 0xa5c0, 0xc12a, 0xa5ff, 0xc12a, 0x21, 0 + .dw 0xa640, 0xc12a, 0xa67f, 0xc12a, 0x21, 0 + .dw 0xa6c0, 0xc12a, 0xa6ff, 0xc12a, 0x21, 0 + .dw 0xa740, 0xc12a, 0xa77f, 0xc12a, 0x21, 0 + .dw 0xa7c0, 0xc12a, 0xa7ff, 0xc12a, 0x21, 0 + .dw 0xa840, 0xc12a, 0xa87f, 0xc12a, 0x21, 0 + .dw 0xa8c0, 0xc12a, 0xa8ff, 0xc12a, 0x21, 0 + .dw 0xa940, 0xc12a, 0xa97f, 0xc12a, 0x21, 0 + .dw 0xa9c0, 0xc12a, 0xa9ff, 0xc12a, 0x21, 0 + .dw 0xaa40, 0xc12a, 0xaa7f, 0xc12a, 0x21, 0 + .dw 0xaac0, 0xc12a, 0xaaff, 0xc12a, 0x21, 0 + .dw 0xab40, 0xc12a, 0xab7f, 0xc12a, 0x21, 0 + .dw 0xabc0, 0xc12a, 0xabff, 0xc12a, 0x21, 0 + .dw 0xac40, 0xc12a, 0xac7f, 0xc12a, 0x21, 0 + .dw 0xacc0, 0xc12a, 0xacff, 0xc12a, 0x21, 0 + .dw 0xad40, 0xc12a, 0xad7f, 0xc12a, 0x21, 0 + .dw 0xadc0, 0xc12a, 0xadff, 0xc12a, 0x21, 0 + .dw 0xae40, 0xc12a, 0xae7f, 0xc12a, 0x21, 0 + .dw 0xaec0, 0xc12a, 0xaeff, 0xc12a, 0x21, 0 + .dw 0xaf40, 0xc12a, 0xaf7f, 0xc12a, 0x21, 0 + .dw 0xafc0, 0xc12a, 0xafff, 0xc12a, 0x21, 0 + .dw 0xb040, 0xc12a, 0xb07f, 0xc12a, 0x21, 0 + .dw 0xb0c0, 0xc12a, 0xb0ff, 0xc12a, 0x21, 0 + .dw 0xb140, 0xc12a, 0xb17f, 0xc12a, 0x21, 0 + .dw 0xb1c0, 0xc12a, 0xb1ff, 0xc12a, 0x21, 0 + .dw 0xb240, 0xc12a, 0xb27f, 0xc12a, 0x21, 0 + .dw 0xb2c0, 0xc12a, 0xb2ff, 0xc12a, 0x21, 0 + .dw 0xb340, 0xc12a, 0xb37f, 0xc12a, 0x21, 0 + .dw 0xb3c0, 0xc12a, 0xb3ff, 0xc12a, 0x21, 0 + .dw 0xb440, 0xc12a, 0xb47f, 0xc12a, 0x21, 0 + .dw 0xb4c0, 0xc12a, 0xb4ff, 0xc12a, 0x21, 0 + .dw 0xb540, 0xc12a, 0xb57f, 0xc12a, 0x21, 0 + .dw 0xb5c0, 0xc12a, 0xb5ff, 0xc12a, 0x21, 0 + .dw 0xb640, 0xc12a, 0xb67f, 0xc12a, 0x21, 0 + .dw 0xb6c0, 0xc12a, 0xb6ff, 0xc12a, 0x21, 0 + .dw 0xb740, 0xc12a, 0xb77f, 0xc12a, 0x21, 0 + .dw 0xb7c0, 0xc12a, 0xb7ff, 0xc12a, 0x21, 0 + .dw 0xb840, 0xc12a, 0xb87f, 0xc12a, 0x21, 0 + .dw 0xb8c0, 0xc12a, 0xb8ff, 0xc12a, 0x21, 0 + .dw 0xb940, 0xc12a, 0xb97f, 0xc12a, 0x21, 0 + .dw 0xb9c0, 0xc12a, 0xdfff, 0xc12a, 0x21, 0 + .dw 0xe040, 0xc12a, 0xe07f, 0xc12a, 0x21, 0 + .dw 0xe0c0, 0xc12a, 0xe0ff, 0xc12a, 0x21, 0 + .dw 0xe140, 0xc12a, 0xe17f, 0xc12a, 0x21, 0 + .dw 0xe1c0, 0xc12a, 0xe1ff, 0xc12a, 0x21, 0 + .dw 0xe240, 0xc12a, 0xe27f, 0xc12a, 0x21, 0 + .dw 0xe2c0, 0xc12a, 0xe2ff, 0xc12a, 0x21, 0 + .dw 0xe340, 0xc12a, 0xe37f, 0xc12a, 0x21, 0 + .dw 0xe3c0, 0xc12a, 0xe3ff, 0xc12a, 0x21, 0 + .dw 0xe440, 0xc12a, 0xe47f, 0xc12a, 0x21, 0 + .dw 0xe4c0, 0xc12a, 0xe4ff, 0xc12a, 0x21, 0 + .dw 0xe540, 0xc12a, 0xe57f, 0xc12a, 0x21, 0 + .dw 0xe5c0, 0xc12a, 0xe5ff, 0xc12a, 0x21, 0 + .dw 0xe640, 0xc12a, 0xe67f, 0xc12a, 0x21, 0 + .dw 0xe6c0, 0xc12a, 0xe6ff, 0xc12a, 0x21, 0 + .dw 0xe740, 0xc12a, 0xe77f, 0xc12a, 0x21, 0 + .dw 0xe7c0, 0xc12a, 0xe7ff, 0xc12a, 0x21, 0 + .dw 0xe840, 0xc12a, 0xe87f, 0xc12a, 0x21, 0 + .dw 0xe8c0, 0xc12a, 0xe8ff, 0xc12a, 0x21, 0 + .dw 0xe940, 0xc12a, 0xe97f, 0xc12a, 0x21, 0 + .dw 0xe9c0, 0xc12a, 0xe9ff, 0xc12a, 0x21, 0 + .dw 0xea40, 0xc12a, 0xea7f, 0xc12a, 0x21, 0 + .dw 0xeac0, 0xc12a, 0xeaff, 0xc12a, 0x21, 0 + .dw 0xeb40, 0xc12a, 0xeb7f, 0xc12a, 0x21, 0 + .dw 0xebc0, 0xc12a, 0xebff, 0xc12a, 0x21, 0 + .dw 0xec40, 0xc12a, 0xec7f, 0xc12a, 0x21, 0 + .dw 0xecc0, 0xc12a, 0xecff, 0xc12a, 0x21, 0 + .dw 0xed40, 0xc12a, 0xed7f, 0xc12a, 0x21, 0 + .dw 0xedc0, 0xc12a, 0xedff, 0xc12a, 0x21, 0 + .dw 0xee40, 0xc12a, 0xee7f, 0xc12a, 0x21, 0 + .dw 0xeec0, 0xc12a, 0xeeff, 0xc12a, 0x21, 0 + .dw 0xef40, 0xc12a, 0xef7f, 0xc12a, 0x21, 0 + .dw 0xefc0, 0xc12a, 0xefff, 0xc12a, 0x21, 0 + .dw 0xf040, 0xc12a, 0xf07f, 0xc12a, 0x21, 0 + .dw 0xf0c0, 0xc12a, 0xf0ff, 0xc12a, 0x21, 0 + .dw 0xf140, 0xc12a, 0xf17f, 0xc12a, 0x21, 0 + .dw 0xf1c0, 0xc12a, 0xf1ff, 0xc12a, 0x21, 0 + .dw 0xf240, 0xc12a, 0xf27f, 0xc12a, 0x21, 0 + .dw 0xf2c0, 0xc12a, 0xf2ff, 0xc12a, 0x21, 0 + .dw 0xf340, 0xc12a, 0xf37f, 0xc12a, 0x21, 0 + .dw 0xf3c0, 0xc12a, 0xf3ff, 0xc12a, 0x21, 0 + .dw 0xf440, 0xc12a, 0xf47f, 0xc12a, 0x21, 0 + .dw 0xf4c0, 0xc12a, 0xf4ff, 0xc12a, 0x21, 0 + .dw 0xf540, 0xc12a, 0xf57f, 0xc12a, 0x21, 0 + .dw 0xf5c0, 0xc12a, 0xf5ff, 0xc12a, 0x21, 0 + .dw 0xf640, 0xc12a, 0xf67f, 0xc12a, 0x21, 0 + .dw 0xf6c0, 0xc12a, 0xf6ff, 0xc12a, 0x21, 0 + .dw 0xf740, 0xc12a, 0xf77f, 0xc12a, 0x21, 0 + .dw 0xf7c0, 0xc12a, 0xf7ff, 0xc12a, 0x21, 0 + .dw 0xf840, 0xc12a, 0xf87f, 0xc12a, 0x21, 0 + .dw 0xf8c0, 0xc12a, 0xf8ff, 0xc12a, 0x21, 0 + .dw 0xf940, 0xc12a, 0xf97f, 0xc12a, 0x21, 0 + .dw 0xf9c0, 0xc12a, 0x1fff, 0xc12b, 0x21, 0 + .dw 0x2040, 0xc12b, 0x207f, 0xc12b, 0x21, 0 + .dw 0x20c0, 0xc12b, 0x20ff, 0xc12b, 0x21, 0 + .dw 0x2140, 0xc12b, 0x217f, 0xc12b, 0x21, 0 + .dw 0x21c0, 0xc12b, 0x21ff, 0xc12b, 0x21, 0 + .dw 0x2240, 0xc12b, 0x227f, 0xc12b, 0x21, 0 + .dw 0x22c0, 0xc12b, 0x22ff, 0xc12b, 0x21, 0 + .dw 0x2340, 0xc12b, 0x237f, 0xc12b, 0x21, 0 + .dw 0x23c0, 0xc12b, 0x23ff, 0xc12b, 0x21, 0 + .dw 0x2440, 0xc12b, 0x247f, 0xc12b, 0x21, 0 + .dw 0x24c0, 0xc12b, 0x24ff, 0xc12b, 0x21, 0 + .dw 0x2540, 0xc12b, 0x257f, 0xc12b, 0x21, 0 + .dw 0x25c0, 0xc12b, 0x25ff, 0xc12b, 0x21, 0 + .dw 0x2640, 0xc12b, 0x267f, 0xc12b, 0x21, 0 + .dw 0x26c0, 0xc12b, 0x26ff, 0xc12b, 0x21, 0 + .dw 0x2740, 0xc12b, 0x277f, 0xc12b, 0x21, 0 + .dw 0x27c0, 0xc12b, 0x27ff, 0xc12b, 0x21, 0 + .dw 0x2840, 0xc12b, 0x287f, 0xc12b, 0x21, 0 + .dw 0x28c0, 0xc12b, 0x28ff, 0xc12b, 0x21, 0 + .dw 0x2940, 0xc12b, 0x297f, 0xc12b, 0x21, 0 + .dw 0x29c0, 0xc12b, 0x29ff, 0xc12b, 0x21, 0 + .dw 0x2a40, 0xc12b, 0x2a7f, 0xc12b, 0x21, 0 + .dw 0x2ac0, 0xc12b, 0x2aff, 0xc12b, 0x21, 0 + .dw 0x2b40, 0xc12b, 0x2b7f, 0xc12b, 0x21, 0 + .dw 0x2bc0, 0xc12b, 0x2bff, 0xc12b, 0x21, 0 + .dw 0x2c40, 0xc12b, 0x2c7f, 0xc12b, 0x21, 0 + .dw 0x2cc0, 0xc12b, 0x2cff, 0xc12b, 0x21, 0 + .dw 0x2d40, 0xc12b, 0x2d7f, 0xc12b, 0x21, 0 + .dw 0x2dc0, 0xc12b, 0x2dff, 0xc12b, 0x21, 0 + .dw 0x2e40, 0xc12b, 0x2e7f, 0xc12b, 0x21, 0 + .dw 0x2ec0, 0xc12b, 0x2eff, 0xc12b, 0x21, 0 + .dw 0x2f40, 0xc12b, 0x2f7f, 0xc12b, 0x21, 0 + .dw 0x2fc0, 0xc12b, 0x2fff, 0xc12b, 0x21, 0 + .dw 0x3040, 0xc12b, 0x307f, 0xc12b, 0x21, 0 + .dw 0x30c0, 0xc12b, 0x30ff, 0xc12b, 0x21, 0 + .dw 0x3140, 0xc12b, 0x317f, 0xc12b, 0x21, 0 + .dw 0x31c0, 0xc12b, 0x31ff, 0xc12b, 0x21, 0 + .dw 0x3240, 0xc12b, 0x327f, 0xc12b, 0x21, 0 + .dw 0x32c0, 0xc12b, 0x32ff, 0xc12b, 0x21, 0 + .dw 0x3340, 0xc12b, 0x337f, 0xc12b, 0x21, 0 + .dw 0x33c0, 0xc12b, 0x33ff, 0xc12b, 0x21, 0 + .dw 0x3440, 0xc12b, 0x347f, 0xc12b, 0x21, 0 + .dw 0x34c0, 0xc12b, 0x34ff, 0xc12b, 0x21, 0 + .dw 0x3540, 0xc12b, 0x357f, 0xc12b, 0x21, 0 + .dw 0x35c0, 0xc12b, 0x35ff, 0xc12b, 0x21, 0 + .dw 0x3640, 0xc12b, 0x367f, 0xc12b, 0x21, 0 + .dw 0x36c0, 0xc12b, 0x36ff, 0xc12b, 0x21, 0 + .dw 0x3740, 0xc12b, 0x377f, 0xc12b, 0x21, 0 + .dw 0x37c0, 0xc12b, 0x37ff, 0xc12b, 0x21, 0 + .dw 0x3840, 0xc12b, 0x387f, 0xc12b, 0x21, 0 + .dw 0x38c0, 0xc12b, 0x38ff, 0xc12b, 0x21, 0 + .dw 0x3940, 0xc12b, 0x397f, 0xc12b, 0x21, 0 + .dw 0x39c0, 0xc12b, 0xffff, 0xc12b, 0x21, 0 + .dw 0x0040, 0xc12c, 0x007f, 0xc12c, 0x21, 0 + .dw 0x00c0, 0xc12c, 0x00ff, 0xc12c, 0x21, 0 + .dw 0x0140, 0xc12c, 0x017f, 0xc12c, 0x21, 0 + .dw 0x01c0, 0xc12c, 0x01ff, 0xc12c, 0x21, 0 + .dw 0x0240, 0xc12c, 0x027f, 0xc12c, 0x21, 0 + .dw 0x02c0, 0xc12c, 0x02ff, 0xc12c, 0x21, 0 + .dw 0x0340, 0xc12c, 0x037f, 0xc12c, 0x21, 0 + .dw 0x03c0, 0xc12c, 0x03ff, 0xc12c, 0x21, 0 + .dw 0x0440, 0xc12c, 0x047f, 0xc12c, 0x21, 0 + .dw 0x04c0, 0xc12c, 0x04ff, 0xc12c, 0x21, 0 + .dw 0x0540, 0xc12c, 0x057f, 0xc12c, 0x21, 0 + .dw 0x05c0, 0xc12c, 0x05ff, 0xc12c, 0x21, 0 + .dw 0x0640, 0xc12c, 0x067f, 0xc12c, 0x21, 0 + .dw 0x06c0, 0xc12c, 0x06ff, 0xc12c, 0x21, 0 + .dw 0x0740, 0xc12c, 0x077f, 0xc12c, 0x21, 0 + .dw 0x07c0, 0xc12c, 0x07ff, 0xc12c, 0x21, 0 + .dw 0x0840, 0xc12c, 0x087f, 0xc12c, 0x21, 0 + .dw 0x08c0, 0xc12c, 0x08ff, 0xc12c, 0x21, 0 + .dw 0x0940, 0xc12c, 0x097f, 0xc12c, 0x21, 0 + .dw 0x09c0, 0xc12c, 0x09ff, 0xc12c, 0x21, 0 + .dw 0x0a40, 0xc12c, 0x0a7f, 0xc12c, 0x21, 0 + .dw 0x0ac0, 0xc12c, 0x0aff, 0xc12c, 0x21, 0 + .dw 0x0b40, 0xc12c, 0x0b7f, 0xc12c, 0x21, 0 + .dw 0x0bc0, 0xc12c, 0x0bff, 0xc12c, 0x21, 0 + .dw 0x0c40, 0xc12c, 0x0c7f, 0xc12c, 0x21, 0 + .dw 0x0cc0, 0xc12c, 0x0cff, 0xc12c, 0x21, 0 + .dw 0x0d40, 0xc12c, 0x0d7f, 0xc12c, 0x21, 0 + .dw 0x0dc0, 0xc12c, 0x0dff, 0xc12c, 0x21, 0 + .dw 0x0e40, 0xc12c, 0x0e7f, 0xc12c, 0x21, 0 + .dw 0x0ec0, 0xc12c, 0x0eff, 0xc12c, 0x21, 0 + .dw 0x0f40, 0xc12c, 0x0f7f, 0xc12c, 0x21, 0 + .dw 0x0fc0, 0xc12c, 0x0fff, 0xc12c, 0x21, 0 + .dw 0x1040, 0xc12c, 0x107f, 0xc12c, 0x21, 0 + .dw 0x10c0, 0xc12c, 0x10ff, 0xc12c, 0x21, 0 + .dw 0x1140, 0xc12c, 0x117f, 0xc12c, 0x21, 0 + .dw 0x11c0, 0xc12c, 0x11ff, 0xc12c, 0x21, 0 + .dw 0x1240, 0xc12c, 0x127f, 0xc12c, 0x21, 0 + .dw 0x12c0, 0xc12c, 0x12ff, 0xc12c, 0x21, 0 + .dw 0x1340, 0xc12c, 0x137f, 0xc12c, 0x21, 0 + .dw 0x13c0, 0xc12c, 0x13ff, 0xc12c, 0x21, 0 + .dw 0x1440, 0xc12c, 0x147f, 0xc12c, 0x21, 0 + .dw 0x14c0, 0xc12c, 0x14ff, 0xc12c, 0x21, 0 + .dw 0x1540, 0xc12c, 0x157f, 0xc12c, 0x21, 0 + .dw 0x15c0, 0xc12c, 0x15ff, 0xc12c, 0x21, 0 + .dw 0x1640, 0xc12c, 0x167f, 0xc12c, 0x21, 0 + .dw 0x16c0, 0xc12c, 0x16ff, 0xc12c, 0x21, 0 + .dw 0x1740, 0xc12c, 0x177f, 0xc12c, 0x21, 0 + .dw 0x17c0, 0xc12c, 0x17ff, 0xc12c, 0x21, 0 + .dw 0x1840, 0xc12c, 0x187f, 0xc12c, 0x21, 0 + .dw 0x18c0, 0xc12c, 0x18ff, 0xc12c, 0x21, 0 + .dw 0x1940, 0xc12c, 0x197f, 0xc12c, 0x21, 0 + .dw 0x19c0, 0xc12c, 0x1fff, 0xc12c, 0x21, 0 + .dw 0x2040, 0xc12c, 0x207f, 0xc12c, 0x21, 0 + .dw 0x20c0, 0xc12c, 0x20ff, 0xc12c, 0x21, 0 + .dw 0x2140, 0xc12c, 0x217f, 0xc12c, 0x21, 0 + .dw 0x21c0, 0xc12c, 0x21ff, 0xc12c, 0x21, 0 + .dw 0x2240, 0xc12c, 0x227f, 0xc12c, 0x21, 0 + .dw 0x22c0, 0xc12c, 0x22ff, 0xc12c, 0x21, 0 + .dw 0x2340, 0xc12c, 0x237f, 0xc12c, 0x21, 0 + .dw 0x23c0, 0xc12c, 0x23ff, 0xc12c, 0x21, 0 + .dw 0x2440, 0xc12c, 0x247f, 0xc12c, 0x21, 0 + .dw 0x24c0, 0xc12c, 0x24ff, 0xc12c, 0x21, 0 + .dw 0x2540, 0xc12c, 0x257f, 0xc12c, 0x21, 0 + .dw 0x25c0, 0xc12c, 0x25ff, 0xc12c, 0x21, 0 + .dw 0x2640, 0xc12c, 0x267f, 0xc12c, 0x21, 0 + .dw 0x26c0, 0xc12c, 0x26ff, 0xc12c, 0x21, 0 + .dw 0x2740, 0xc12c, 0x277f, 0xc12c, 0x21, 0 + .dw 0x27c0, 0xc12c, 0x27ff, 0xc12c, 0x21, 0 + .dw 0x2840, 0xc12c, 0x287f, 0xc12c, 0x21, 0 + .dw 0x28c0, 0xc12c, 0x28ff, 0xc12c, 0x21, 0 + .dw 0x2940, 0xc12c, 0x297f, 0xc12c, 0x21, 0 + .dw 0x29c0, 0xc12c, 0x29ff, 0xc12c, 0x21, 0 + .dw 0x2a40, 0xc12c, 0x2a7f, 0xc12c, 0x21, 0 + .dw 0x2ac0, 0xc12c, 0x2aff, 0xc12c, 0x21, 0 + .dw 0x2b40, 0xc12c, 0x2b7f, 0xc12c, 0x21, 0 + .dw 0x2bc0, 0xc12c, 0x2bff, 0xc12c, 0x21, 0 + .dw 0x2c40, 0xc12c, 0x2c7f, 0xc12c, 0x21, 0 + .dw 0x2cc0, 0xc12c, 0x2cff, 0xc12c, 0x21, 0 + .dw 0x2d40, 0xc12c, 0x2d7f, 0xc12c, 0x21, 0 + .dw 0x2dc0, 0xc12c, 0x2dff, 0xc12c, 0x21, 0 + .dw 0x2e40, 0xc12c, 0x2e7f, 0xc12c, 0x21, 0 + .dw 0x2ec0, 0xc12c, 0x2eff, 0xc12c, 0x21, 0 + .dw 0x2f40, 0xc12c, 0x2f7f, 0xc12c, 0x21, 0 + .dw 0x2fc0, 0xc12c, 0x2fff, 0xc12c, 0x21, 0 + .dw 0x3040, 0xc12c, 0x307f, 0xc12c, 0x21, 0 + .dw 0x30c0, 0xc12c, 0x30ff, 0xc12c, 0x21, 0 + .dw 0x3140, 0xc12c, 0x317f, 0xc12c, 0x21, 0 + .dw 0x31c0, 0xc12c, 0x31ff, 0xc12c, 0x21, 0 + .dw 0x3240, 0xc12c, 0x327f, 0xc12c, 0x21, 0 + .dw 0x32c0, 0xc12c, 0x32ff, 0xc12c, 0x21, 0 + .dw 0x3340, 0xc12c, 0x337f, 0xc12c, 0x21, 0 + .dw 0x33c0, 0xc12c, 0x33ff, 0xc12c, 0x21, 0 + .dw 0x3440, 0xc12c, 0x347f, 0xc12c, 0x21, 0 + .dw 0x34c0, 0xc12c, 0x34ff, 0xc12c, 0x21, 0 + .dw 0x3540, 0xc12c, 0x357f, 0xc12c, 0x21, 0 + .dw 0x35c0, 0xc12c, 0x35ff, 0xc12c, 0x21, 0 + .dw 0x3640, 0xc12c, 0x367f, 0xc12c, 0x21, 0 + .dw 0x36c0, 0xc12c, 0x36ff, 0xc12c, 0x21, 0 + .dw 0x3740, 0xc12c, 0x377f, 0xc12c, 0x21, 0 + .dw 0x37c0, 0xc12c, 0x37ff, 0xc12c, 0x21, 0 + .dw 0x3840, 0xc12c, 0x387f, 0xc12c, 0x21, 0 + .dw 0x38c0, 0xc12c, 0x38ff, 0xc12c, 0x21, 0 + .dw 0x3940, 0xc12c, 0x397f, 0xc12c, 0x21, 0 + .dw 0x39c0, 0xc12c, 0x3fff, 0xc12c, 0x21, 0 + .dw 0x4040, 0xc12c, 0x407f, 0xc12c, 0x21, 0 + .dw 0x40c0, 0xc12c, 0x40ff, 0xc12c, 0x21, 0 + .dw 0x4140, 0xc12c, 0x417f, 0xc12c, 0x21, 0 + .dw 0x41c0, 0xc12c, 0x41ff, 0xc12c, 0x21, 0 + .dw 0x4240, 0xc12c, 0x427f, 0xc12c, 0x21, 0 + .dw 0x42c0, 0xc12c, 0x42ff, 0xc12c, 0x21, 0 + .dw 0x4340, 0xc12c, 0x437f, 0xc12c, 0x21, 0 + .dw 0x43c0, 0xc12c, 0x43ff, 0xc12c, 0x21, 0 + .dw 0x4440, 0xc12c, 0x447f, 0xc12c, 0x21, 0 + .dw 0x44c0, 0xc12c, 0x44ff, 0xc12c, 0x21, 0 + .dw 0x4540, 0xc12c, 0x457f, 0xc12c, 0x21, 0 + .dw 0x45c0, 0xc12c, 0x45ff, 0xc12c, 0x21, 0 + .dw 0x4640, 0xc12c, 0x467f, 0xc12c, 0x21, 0 + .dw 0x46c0, 0xc12c, 0x46ff, 0xc12c, 0x21, 0 + .dw 0x4740, 0xc12c, 0x477f, 0xc12c, 0x21, 0 + .dw 0x47c0, 0xc12c, 0x47ff, 0xc12c, 0x21, 0 + .dw 0x4840, 0xc12c, 0x487f, 0xc12c, 0x21, 0 + .dw 0x48c0, 0xc12c, 0x48ff, 0xc12c, 0x21, 0 + .dw 0x4940, 0xc12c, 0x497f, 0xc12c, 0x21, 0 + .dw 0x49c0, 0xc12c, 0x49ff, 0xc12c, 0x21, 0 + .dw 0x4a40, 0xc12c, 0x4a7f, 0xc12c, 0x21, 0 + .dw 0x4ac0, 0xc12c, 0x4aff, 0xc12c, 0x21, 0 + .dw 0x4b40, 0xc12c, 0x4b7f, 0xc12c, 0x21, 0 + .dw 0x4bc0, 0xc12c, 0x4bff, 0xc12c, 0x21, 0 + .dw 0x4c40, 0xc12c, 0x4c7f, 0xc12c, 0x21, 0 + .dw 0x4cc0, 0xc12c, 0x4cff, 0xc12c, 0x21, 0 + .dw 0x4d40, 0xc12c, 0x4d7f, 0xc12c, 0x21, 0 + .dw 0x4dc0, 0xc12c, 0x4dff, 0xc12c, 0x21, 0 + .dw 0x4e40, 0xc12c, 0x4e7f, 0xc12c, 0x21, 0 + .dw 0x4ec0, 0xc12c, 0x4eff, 0xc12c, 0x21, 0 + .dw 0x4f40, 0xc12c, 0x4f7f, 0xc12c, 0x21, 0 + .dw 0x4fc0, 0xc12c, 0x4fff, 0xc12c, 0x21, 0 + .dw 0x5040, 0xc12c, 0x507f, 0xc12c, 0x21, 0 + .dw 0x50c0, 0xc12c, 0x50ff, 0xc12c, 0x21, 0 + .dw 0x5140, 0xc12c, 0x517f, 0xc12c, 0x21, 0 + .dw 0x51c0, 0xc12c, 0x51ff, 0xc12c, 0x21, 0 + .dw 0x5240, 0xc12c, 0x527f, 0xc12c, 0x21, 0 + .dw 0x52c0, 0xc12c, 0x52ff, 0xc12c, 0x21, 0 + .dw 0x5340, 0xc12c, 0x537f, 0xc12c, 0x21, 0 + .dw 0x53c0, 0xc12c, 0x53ff, 0xc12c, 0x21, 0 + .dw 0x5440, 0xc12c, 0x547f, 0xc12c, 0x21, 0 + .dw 0x54c0, 0xc12c, 0x54ff, 0xc12c, 0x21, 0 + .dw 0x5540, 0xc12c, 0x557f, 0xc12c, 0x21, 0 + .dw 0x55c0, 0xc12c, 0x55ff, 0xc12c, 0x21, 0 + .dw 0x5640, 0xc12c, 0x567f, 0xc12c, 0x21, 0 + .dw 0x56c0, 0xc12c, 0x56ff, 0xc12c, 0x21, 0 + .dw 0x5740, 0xc12c, 0x577f, 0xc12c, 0x21, 0 + .dw 0x57c0, 0xc12c, 0x57ff, 0xc12c, 0x21, 0 + .dw 0x5840, 0xc12c, 0x587f, 0xc12c, 0x21, 0 + .dw 0x58c0, 0xc12c, 0x58ff, 0xc12c, 0x21, 0 + .dw 0x5940, 0xc12c, 0x597f, 0xc12c, 0x21, 0 + .dw 0x59c0, 0xc12c, 0x5fff, 0xc12c, 0x21, 0 + .dw 0x6040, 0xc12c, 0x607f, 0xc12c, 0x21, 0 + .dw 0x60c0, 0xc12c, 0x60ff, 0xc12c, 0x21, 0 + .dw 0x6140, 0xc12c, 0x617f, 0xc12c, 0x21, 0 + .dw 0x61c0, 0xc12c, 0x61ff, 0xc12c, 0x21, 0 + .dw 0x6240, 0xc12c, 0x627f, 0xc12c, 0x21, 0 + .dw 0x62c0, 0xc12c, 0x62ff, 0xc12c, 0x21, 0 + .dw 0x6340, 0xc12c, 0x637f, 0xc12c, 0x21, 0 + .dw 0x63c0, 0xc12c, 0x63ff, 0xc12c, 0x21, 0 + .dw 0x6440, 0xc12c, 0x647f, 0xc12c, 0x21, 0 + .dw 0x64c0, 0xc12c, 0x64ff, 0xc12c, 0x21, 0 + .dw 0x6540, 0xc12c, 0x657f, 0xc12c, 0x21, 0 + .dw 0x65c0, 0xc12c, 0x65ff, 0xc12c, 0x21, 0 + .dw 0x6640, 0xc12c, 0x667f, 0xc12c, 0x21, 0 + .dw 0x66c0, 0xc12c, 0x66ff, 0xc12c, 0x21, 0 + .dw 0x6740, 0xc12c, 0x677f, 0xc12c, 0x21, 0 + .dw 0x67c0, 0xc12c, 0x67ff, 0xc12c, 0x21, 0 + .dw 0x6840, 0xc12c, 0x687f, 0xc12c, 0x21, 0 + .dw 0x68c0, 0xc12c, 0x68ff, 0xc12c, 0x21, 0 + .dw 0x6940, 0xc12c, 0x697f, 0xc12c, 0x21, 0 + .dw 0x69c0, 0xc12c, 0x69ff, 0xc12c, 0x21, 0 + .dw 0x6a40, 0xc12c, 0x6a7f, 0xc12c, 0x21, 0 + .dw 0x6ac0, 0xc12c, 0x6aff, 0xc12c, 0x21, 0 + .dw 0x6b40, 0xc12c, 0x6b7f, 0xc12c, 0x21, 0 + .dw 0x6bc0, 0xc12c, 0x6bff, 0xc12c, 0x21, 0 + .dw 0x6c40, 0xc12c, 0x6c7f, 0xc12c, 0x21, 0 + .dw 0x6cc0, 0xc12c, 0x6cff, 0xc12c, 0x21, 0 + .dw 0x6d40, 0xc12c, 0x6d7f, 0xc12c, 0x21, 0 + .dw 0x6dc0, 0xc12c, 0x6dff, 0xc12c, 0x21, 0 + .dw 0x6e40, 0xc12c, 0x6e7f, 0xc12c, 0x21, 0 + .dw 0x6ec0, 0xc12c, 0x6eff, 0xc12c, 0x21, 0 + .dw 0x6f40, 0xc12c, 0x6f7f, 0xc12c, 0x21, 0 + .dw 0x6fc0, 0xc12c, 0x6fff, 0xc12c, 0x21, 0 + .dw 0x7040, 0xc12c, 0x707f, 0xc12c, 0x21, 0 + .dw 0x70c0, 0xc12c, 0x70ff, 0xc12c, 0x21, 0 + .dw 0x7140, 0xc12c, 0x717f, 0xc12c, 0x21, 0 + .dw 0x71c0, 0xc12c, 0x71ff, 0xc12c, 0x21, 0 + .dw 0x7240, 0xc12c, 0x727f, 0xc12c, 0x21, 0 + .dw 0x72c0, 0xc12c, 0x72ff, 0xc12c, 0x21, 0 + .dw 0x7340, 0xc12c, 0x737f, 0xc12c, 0x21, 0 + .dw 0x73c0, 0xc12c, 0x73ff, 0xc12c, 0x21, 0 + .dw 0x7440, 0xc12c, 0x747f, 0xc12c, 0x21, 0 + .dw 0x74c0, 0xc12c, 0x74ff, 0xc12c, 0x21, 0 + .dw 0x7540, 0xc12c, 0x757f, 0xc12c, 0x21, 0 + .dw 0x75c0, 0xc12c, 0x75ff, 0xc12c, 0x21, 0 + .dw 0x7640, 0xc12c, 0x767f, 0xc12c, 0x21, 0 + .dw 0x76c0, 0xc12c, 0x76ff, 0xc12c, 0x21, 0 + .dw 0x7740, 0xc12c, 0x777f, 0xc12c, 0x21, 0 + .dw 0x77c0, 0xc12c, 0x77ff, 0xc12c, 0x21, 0 + .dw 0x7840, 0xc12c, 0x787f, 0xc12c, 0x21, 0 + .dw 0x78c0, 0xc12c, 0x78ff, 0xc12c, 0x21, 0 + .dw 0x7940, 0xc12c, 0x797f, 0xc12c, 0x21, 0 + .dw 0x79c0, 0xc12c, 0x7fff, 0xc12c, 0x21, 0 + .dw 0x8040, 0xc12c, 0x807f, 0xc12c, 0x21, 0 + .dw 0x80c0, 0xc12c, 0x80ff, 0xc12c, 0x21, 0 + .dw 0x8140, 0xc12c, 0x817f, 0xc12c, 0x21, 0 + .dw 0x81c0, 0xc12c, 0x81ff, 0xc12c, 0x21, 0 + .dw 0x8240, 0xc12c, 0x827f, 0xc12c, 0x21, 0 + .dw 0x82c0, 0xc12c, 0x82ff, 0xc12c, 0x21, 0 + .dw 0x8340, 0xc12c, 0x837f, 0xc12c, 0x21, 0 + .dw 0x83c0, 0xc12c, 0x83ff, 0xc12c, 0x21, 0 + .dw 0x8440, 0xc12c, 0x847f, 0xc12c, 0x21, 0 + .dw 0x84c0, 0xc12c, 0x84ff, 0xc12c, 0x21, 0 + .dw 0x8540, 0xc12c, 0x857f, 0xc12c, 0x21, 0 + .dw 0x85c0, 0xc12c, 0x85ff, 0xc12c, 0x21, 0 + .dw 0x8640, 0xc12c, 0x867f, 0xc12c, 0x21, 0 + .dw 0x86c0, 0xc12c, 0x86ff, 0xc12c, 0x21, 0 + .dw 0x8740, 0xc12c, 0x877f, 0xc12c, 0x21, 0 + .dw 0x87c0, 0xc12c, 0x87ff, 0xc12c, 0x21, 0 + .dw 0x8840, 0xc12c, 0x887f, 0xc12c, 0x21, 0 + .dw 0x88c0, 0xc12c, 0x88ff, 0xc12c, 0x21, 0 + .dw 0x8940, 0xc12c, 0x897f, 0xc12c, 0x21, 0 + .dw 0x89c0, 0xc12c, 0x89ff, 0xc12c, 0x21, 0 + .dw 0x8a40, 0xc12c, 0x8a7f, 0xc12c, 0x21, 0 + .dw 0x8ac0, 0xc12c, 0x8aff, 0xc12c, 0x21, 0 + .dw 0x8b40, 0xc12c, 0x8b7f, 0xc12c, 0x21, 0 + .dw 0x8bc0, 0xc12c, 0x8bff, 0xc12c, 0x21, 0 + .dw 0x8c40, 0xc12c, 0x8c7f, 0xc12c, 0x21, 0 + .dw 0x8cc0, 0xc12c, 0x8cff, 0xc12c, 0x21, 0 + .dw 0x8d40, 0xc12c, 0x8d7f, 0xc12c, 0x21, 0 + .dw 0x8dc0, 0xc12c, 0x8dff, 0xc12c, 0x21, 0 + .dw 0x8e40, 0xc12c, 0x8e7f, 0xc12c, 0x21, 0 + .dw 0x8ec0, 0xc12c, 0x8eff, 0xc12c, 0x21, 0 + .dw 0x8f40, 0xc12c, 0x8f7f, 0xc12c, 0x21, 0 + .dw 0x8fc0, 0xc12c, 0x8fff, 0xc12c, 0x21, 0 + .dw 0x9040, 0xc12c, 0x907f, 0xc12c, 0x21, 0 + .dw 0x90c0, 0xc12c, 0x90ff, 0xc12c, 0x21, 0 + .dw 0x9140, 0xc12c, 0x917f, 0xc12c, 0x21, 0 + .dw 0x91c0, 0xc12c, 0x91ff, 0xc12c, 0x21, 0 + .dw 0x9240, 0xc12c, 0x927f, 0xc12c, 0x21, 0 + .dw 0x92c0, 0xc12c, 0x92ff, 0xc12c, 0x21, 0 + .dw 0x9340, 0xc12c, 0x937f, 0xc12c, 0x21, 0 + .dw 0x93c0, 0xc12c, 0x93ff, 0xc12c, 0x21, 0 + .dw 0x9440, 0xc12c, 0x947f, 0xc12c, 0x21, 0 + .dw 0x94c0, 0xc12c, 0x94ff, 0xc12c, 0x21, 0 + .dw 0x9540, 0xc12c, 0x957f, 0xc12c, 0x21, 0 + .dw 0x95c0, 0xc12c, 0x95ff, 0xc12c, 0x21, 0 + .dw 0x9640, 0xc12c, 0x967f, 0xc12c, 0x21, 0 + .dw 0x96c0, 0xc12c, 0x96ff, 0xc12c, 0x21, 0 + .dw 0x9740, 0xc12c, 0x977f, 0xc12c, 0x21, 0 + .dw 0x97c0, 0xc12c, 0x97ff, 0xc12c, 0x21, 0 + .dw 0x9840, 0xc12c, 0x987f, 0xc12c, 0x21, 0 + .dw 0x98c0, 0xc12c, 0x98ff, 0xc12c, 0x21, 0 + .dw 0x9940, 0xc12c, 0x997f, 0xc12c, 0x21, 0 + .dw 0x99c0, 0xc12c, 0x9fff, 0xc12c, 0x21, 0 + .dw 0xa040, 0xc12c, 0xa07f, 0xc12c, 0x21, 0 + .dw 0xa0c0, 0xc12c, 0xa0ff, 0xc12c, 0x21, 0 + .dw 0xa140, 0xc12c, 0xa17f, 0xc12c, 0x21, 0 + .dw 0xa1c0, 0xc12c, 0xa1ff, 0xc12c, 0x21, 0 + .dw 0xa240, 0xc12c, 0xa27f, 0xc12c, 0x21, 0 + .dw 0xa2c0, 0xc12c, 0xa2ff, 0xc12c, 0x21, 0 + .dw 0xa340, 0xc12c, 0xa37f, 0xc12c, 0x21, 0 + .dw 0xa3c0, 0xc12c, 0xa3ff, 0xc12c, 0x21, 0 + .dw 0xa440, 0xc12c, 0xa47f, 0xc12c, 0x21, 0 + .dw 0xa4c0, 0xc12c, 0xa4ff, 0xc12c, 0x21, 0 + .dw 0xa540, 0xc12c, 0xa57f, 0xc12c, 0x21, 0 + .dw 0xa5c0, 0xc12c, 0xa5ff, 0xc12c, 0x21, 0 + .dw 0xa640, 0xc12c, 0xa67f, 0xc12c, 0x21, 0 + .dw 0xa6c0, 0xc12c, 0xa6ff, 0xc12c, 0x21, 0 + .dw 0xa740, 0xc12c, 0xa77f, 0xc12c, 0x21, 0 + .dw 0xa7c0, 0xc12c, 0xa7ff, 0xc12c, 0x21, 0 + .dw 0xa840, 0xc12c, 0xa87f, 0xc12c, 0x21, 0 + .dw 0xa8c0, 0xc12c, 0xa8ff, 0xc12c, 0x21, 0 + .dw 0xa940, 0xc12c, 0xa97f, 0xc12c, 0x21, 0 + .dw 0xa9c0, 0xc12c, 0xa9ff, 0xc12c, 0x21, 0 + .dw 0xaa40, 0xc12c, 0xaa7f, 0xc12c, 0x21, 0 + .dw 0xaac0, 0xc12c, 0xaaff, 0xc12c, 0x21, 0 + .dw 0xab40, 0xc12c, 0xab7f, 0xc12c, 0x21, 0 + .dw 0xabc0, 0xc12c, 0xabff, 0xc12c, 0x21, 0 + .dw 0xac40, 0xc12c, 0xac7f, 0xc12c, 0x21, 0 + .dw 0xacc0, 0xc12c, 0xacff, 0xc12c, 0x21, 0 + .dw 0xad40, 0xc12c, 0xad7f, 0xc12c, 0x21, 0 + .dw 0xadc0, 0xc12c, 0xadff, 0xc12c, 0x21, 0 + .dw 0xae40, 0xc12c, 0xae7f, 0xc12c, 0x21, 0 + .dw 0xaec0, 0xc12c, 0xaeff, 0xc12c, 0x21, 0 + .dw 0xaf40, 0xc12c, 0xaf7f, 0xc12c, 0x21, 0 + .dw 0xafc0, 0xc12c, 0xafff, 0xc12c, 0x21, 0 + .dw 0xb040, 0xc12c, 0xb07f, 0xc12c, 0x21, 0 + .dw 0xb0c0, 0xc12c, 0xb0ff, 0xc12c, 0x21, 0 + .dw 0xb140, 0xc12c, 0xb17f, 0xc12c, 0x21, 0 + .dw 0xb1c0, 0xc12c, 0xb1ff, 0xc12c, 0x21, 0 + .dw 0xb240, 0xc12c, 0xb27f, 0xc12c, 0x21, 0 + .dw 0xb2c0, 0xc12c, 0xb2ff, 0xc12c, 0x21, 0 + .dw 0xb340, 0xc12c, 0xb37f, 0xc12c, 0x21, 0 + .dw 0xb3c0, 0xc12c, 0xb3ff, 0xc12c, 0x21, 0 + .dw 0xb440, 0xc12c, 0xb47f, 0xc12c, 0x21, 0 + .dw 0xb4c0, 0xc12c, 0xb4ff, 0xc12c, 0x21, 0 + .dw 0xb540, 0xc12c, 0xb57f, 0xc12c, 0x21, 0 + .dw 0xb5c0, 0xc12c, 0xb5ff, 0xc12c, 0x21, 0 + .dw 0xb640, 0xc12c, 0xb67f, 0xc12c, 0x21, 0 + .dw 0xb6c0, 0xc12c, 0xb6ff, 0xc12c, 0x21, 0 + .dw 0xb740, 0xc12c, 0xb77f, 0xc12c, 0x21, 0 + .dw 0xb7c0, 0xc12c, 0xb7ff, 0xc12c, 0x21, 0 + .dw 0xb840, 0xc12c, 0xb87f, 0xc12c, 0x21, 0 + .dw 0xb8c0, 0xc12c, 0xb8ff, 0xc12c, 0x21, 0 + .dw 0xb940, 0xc12c, 0xb97f, 0xc12c, 0x21, 0 + .dw 0xb9c0, 0xc12c, 0xbfff, 0xc12c, 0x21, 0 + .dw 0xc040, 0xc12c, 0xc07f, 0xc12c, 0x21, 0 + .dw 0xc0c0, 0xc12c, 0xc0ff, 0xc12c, 0x21, 0 + .dw 0xc140, 0xc12c, 0xc17f, 0xc12c, 0x21, 0 + .dw 0xc1c0, 0xc12c, 0xc1ff, 0xc12c, 0x21, 0 + .dw 0xc240, 0xc12c, 0xc27f, 0xc12c, 0x21, 0 + .dw 0xc2c0, 0xc12c, 0xc2ff, 0xc12c, 0x21, 0 + .dw 0xc340, 0xc12c, 0xc37f, 0xc12c, 0x21, 0 + .dw 0xc3c0, 0xc12c, 0xc3ff, 0xc12c, 0x21, 0 + .dw 0xc440, 0xc12c, 0xc47f, 0xc12c, 0x21, 0 + .dw 0xc4c0, 0xc12c, 0xc4ff, 0xc12c, 0x21, 0 + .dw 0xc540, 0xc12c, 0xc57f, 0xc12c, 0x21, 0 + .dw 0xc5c0, 0xc12c, 0xc5ff, 0xc12c, 0x21, 0 + .dw 0xc640, 0xc12c, 0xc67f, 0xc12c, 0x21, 0 + .dw 0xc6c0, 0xc12c, 0xc6ff, 0xc12c, 0x21, 0 + .dw 0xc740, 0xc12c, 0xc77f, 0xc12c, 0x21, 0 + .dw 0xc7c0, 0xc12c, 0xc7ff, 0xc12c, 0x21, 0 + .dw 0xc840, 0xc12c, 0xc87f, 0xc12c, 0x21, 0 + .dw 0xc8c0, 0xc12c, 0xc8ff, 0xc12c, 0x21, 0 + .dw 0xc940, 0xc12c, 0xc97f, 0xc12c, 0x21, 0 + .dw 0xc9c0, 0xc12c, 0xc9ff, 0xc12c, 0x21, 0 + .dw 0xca40, 0xc12c, 0xca7f, 0xc12c, 0x21, 0 + .dw 0xcac0, 0xc12c, 0xcaff, 0xc12c, 0x21, 0 + .dw 0xcb40, 0xc12c, 0xcb7f, 0xc12c, 0x21, 0 + .dw 0xcbc0, 0xc12c, 0xcbff, 0xc12c, 0x21, 0 + .dw 0xcc40, 0xc12c, 0xcc7f, 0xc12c, 0x21, 0 + .dw 0xccc0, 0xc12c, 0xccff, 0xc12c, 0x21, 0 + .dw 0xcd40, 0xc12c, 0xcd7f, 0xc12c, 0x21, 0 + .dw 0xcdc0, 0xc12c, 0xcdff, 0xc12c, 0x21, 0 + .dw 0xce40, 0xc12c, 0xce7f, 0xc12c, 0x21, 0 + .dw 0xcec0, 0xc12c, 0xceff, 0xc12c, 0x21, 0 + .dw 0xcf40, 0xc12c, 0xcf7f, 0xc12c, 0x21, 0 + .dw 0xcfc0, 0xc12c, 0xcfff, 0xc12c, 0x21, 0 + .dw 0xd040, 0xc12c, 0xd07f, 0xc12c, 0x21, 0 + .dw 0xd0c0, 0xc12c, 0xd0ff, 0xc12c, 0x21, 0 + .dw 0xd140, 0xc12c, 0xd17f, 0xc12c, 0x21, 0 + .dw 0xd1c0, 0xc12c, 0xd1ff, 0xc12c, 0x21, 0 + .dw 0xd240, 0xc12c, 0xd27f, 0xc12c, 0x21, 0 + .dw 0xd2c0, 0xc12c, 0xd2ff, 0xc12c, 0x21, 0 + .dw 0xd340, 0xc12c, 0xd37f, 0xc12c, 0x21, 0 + .dw 0xd3c0, 0xc12c, 0xd3ff, 0xc12c, 0x21, 0 + .dw 0xd440, 0xc12c, 0xd47f, 0xc12c, 0x21, 0 + .dw 0xd4c0, 0xc12c, 0xd4ff, 0xc12c, 0x21, 0 + .dw 0xd540, 0xc12c, 0xd57f, 0xc12c, 0x21, 0 + .dw 0xd5c0, 0xc12c, 0xd5ff, 0xc12c, 0x21, 0 + .dw 0xd640, 0xc12c, 0xd67f, 0xc12c, 0x21, 0 + .dw 0xd6c0, 0xc12c, 0xd6ff, 0xc12c, 0x21, 0 + .dw 0xd740, 0xc12c, 0xd77f, 0xc12c, 0x21, 0 + .dw 0xd7c0, 0xc12c, 0xd7ff, 0xc12c, 0x21, 0 + .dw 0xd840, 0xc12c, 0xd87f, 0xc12c, 0x21, 0 + .dw 0xd8c0, 0xc12c, 0xd8ff, 0xc12c, 0x21, 0 + .dw 0xd940, 0xc12c, 0xd97f, 0xc12c, 0x21, 0 + .dw 0xd9c0, 0xc12c, 0xdfff, 0xc12c, 0x21, 0 + .dw 0xe040, 0xc12c, 0xe07f, 0xc12c, 0x21, 0 + .dw 0xe0c0, 0xc12c, 0xe0ff, 0xc12c, 0x21, 0 + .dw 0xe140, 0xc12c, 0xe17f, 0xc12c, 0x21, 0 + .dw 0xe1c0, 0xc12c, 0xe1ff, 0xc12c, 0x21, 0 + .dw 0xe240, 0xc12c, 0xe27f, 0xc12c, 0x21, 0 + .dw 0xe2c0, 0xc12c, 0xe2ff, 0xc12c, 0x21, 0 + .dw 0xe340, 0xc12c, 0xe37f, 0xc12c, 0x21, 0 + .dw 0xe3c0, 0xc12c, 0xe3ff, 0xc12c, 0x21, 0 + .dw 0xe440, 0xc12c, 0xe47f, 0xc12c, 0x21, 0 + .dw 0xe4c0, 0xc12c, 0xe4ff, 0xc12c, 0x21, 0 + .dw 0xe540, 0xc12c, 0xe57f, 0xc12c, 0x21, 0 + .dw 0xe5c0, 0xc12c, 0xe5ff, 0xc12c, 0x21, 0 + .dw 0xe640, 0xc12c, 0xe67f, 0xc12c, 0x21, 0 + .dw 0xe6c0, 0xc12c, 0xe6ff, 0xc12c, 0x21, 0 + .dw 0xe740, 0xc12c, 0xe77f, 0xc12c, 0x21, 0 + .dw 0xe7c0, 0xc12c, 0xe7ff, 0xc12c, 0x21, 0 + .dw 0xe840, 0xc12c, 0xe87f, 0xc12c, 0x21, 0 + .dw 0xe8c0, 0xc12c, 0xe8ff, 0xc12c, 0x21, 0 + .dw 0xe940, 0xc12c, 0xe97f, 0xc12c, 0x21, 0 + .dw 0xe9c0, 0xc12c, 0xe9ff, 0xc12c, 0x21, 0 + .dw 0xea40, 0xc12c, 0xea7f, 0xc12c, 0x21, 0 + .dw 0xeac0, 0xc12c, 0xeaff, 0xc12c, 0x21, 0 + .dw 0xeb40, 0xc12c, 0xeb7f, 0xc12c, 0x21, 0 + .dw 0xebc0, 0xc12c, 0xebff, 0xc12c, 0x21, 0 + .dw 0xec40, 0xc12c, 0xec7f, 0xc12c, 0x21, 0 + .dw 0xecc0, 0xc12c, 0xecff, 0xc12c, 0x21, 0 + .dw 0xed40, 0xc12c, 0xed7f, 0xc12c, 0x21, 0 + .dw 0xedc0, 0xc12c, 0xedff, 0xc12c, 0x21, 0 + .dw 0xee40, 0xc12c, 0xee7f, 0xc12c, 0x21, 0 + .dw 0xeec0, 0xc12c, 0xeeff, 0xc12c, 0x21, 0 + .dw 0xef40, 0xc12c, 0xef7f, 0xc12c, 0x21, 0 + .dw 0xefc0, 0xc12c, 0xefff, 0xc12c, 0x21, 0 + .dw 0xf040, 0xc12c, 0xf07f, 0xc12c, 0x21, 0 + .dw 0xf0c0, 0xc12c, 0xf0ff, 0xc12c, 0x21, 0 + .dw 0xf140, 0xc12c, 0xf17f, 0xc12c, 0x21, 0 + .dw 0xf1c0, 0xc12c, 0xf1ff, 0xc12c, 0x21, 0 + .dw 0xf240, 0xc12c, 0xf27f, 0xc12c, 0x21, 0 + .dw 0xf2c0, 0xc12c, 0xf2ff, 0xc12c, 0x21, 0 + .dw 0xf340, 0xc12c, 0xf37f, 0xc12c, 0x21, 0 + .dw 0xf3c0, 0xc12c, 0xf3ff, 0xc12c, 0x21, 0 + .dw 0xf440, 0xc12c, 0xf47f, 0xc12c, 0x21, 0 + .dw 0xf4c0, 0xc12c, 0xf4ff, 0xc12c, 0x21, 0 + .dw 0xf540, 0xc12c, 0xf57f, 0xc12c, 0x21, 0 + .dw 0xf5c0, 0xc12c, 0xf5ff, 0xc12c, 0x21, 0 + .dw 0xf640, 0xc12c, 0xf67f, 0xc12c, 0x21, 0 + .dw 0xf6c0, 0xc12c, 0xf6ff, 0xc12c, 0x21, 0 + .dw 0xf740, 0xc12c, 0xf77f, 0xc12c, 0x21, 0 + .dw 0xf7c0, 0xc12c, 0xf7ff, 0xc12c, 0x21, 0 + .dw 0xf840, 0xc12c, 0xf87f, 0xc12c, 0x21, 0 + .dw 0xf8c0, 0xc12c, 0xf8ff, 0xc12c, 0x21, 0 + .dw 0xf940, 0xc12c, 0xf97f, 0xc12c, 0x21, 0 + .dw 0xf9c0, 0xc12c, 0xffff, 0xc12c, 0x21, 0 + .dw 0x0040, 0xc12d, 0x007f, 0xc12d, 0x21, 0 + .dw 0x00c0, 0xc12d, 0x00ff, 0xc12d, 0x21, 0 + .dw 0x0140, 0xc12d, 0x017f, 0xc12d, 0x21, 0 + .dw 0x01c0, 0xc12d, 0x01ff, 0xc12d, 0x21, 0 + .dw 0x0240, 0xc12d, 0x027f, 0xc12d, 0x21, 0 + .dw 0x02c0, 0xc12d, 0x02ff, 0xc12d, 0x21, 0 + .dw 0x0340, 0xc12d, 0x037f, 0xc12d, 0x21, 0 + .dw 0x03c0, 0xc12d, 0x03ff, 0xc12d, 0x21, 0 + .dw 0x0440, 0xc12d, 0x047f, 0xc12d, 0x21, 0 + .dw 0x04c0, 0xc12d, 0x04ff, 0xc12d, 0x21, 0 + .dw 0x0540, 0xc12d, 0x057f, 0xc12d, 0x21, 0 + .dw 0x05c0, 0xc12d, 0x05ff, 0xc12d, 0x21, 0 + .dw 0x0640, 0xc12d, 0x067f, 0xc12d, 0x21, 0 + .dw 0x06c0, 0xc12d, 0x06ff, 0xc12d, 0x21, 0 + .dw 0x0740, 0xc12d, 0x077f, 0xc12d, 0x21, 0 + .dw 0x07c0, 0xc12d, 0x07ff, 0xc12d, 0x21, 0 + .dw 0x0840, 0xc12d, 0x087f, 0xc12d, 0x21, 0 + .dw 0x08c0, 0xc12d, 0x08ff, 0xc12d, 0x21, 0 + .dw 0x0940, 0xc12d, 0x097f, 0xc12d, 0x21, 0 + .dw 0x09c0, 0xc12d, 0x09ff, 0xc12d, 0x21, 0 + .dw 0x0a40, 0xc12d, 0x0a7f, 0xc12d, 0x21, 0 + .dw 0x0ac0, 0xc12d, 0x0aff, 0xc12d, 0x21, 0 + .dw 0x0b40, 0xc12d, 0x0b7f, 0xc12d, 0x21, 0 + .dw 0x0bc0, 0xc12d, 0x0bff, 0xc12d, 0x21, 0 + .dw 0x0c40, 0xc12d, 0x0c7f, 0xc12d, 0x21, 0 + .dw 0x0cc0, 0xc12d, 0x0cff, 0xc12d, 0x21, 0 + .dw 0x0d40, 0xc12d, 0x0d7f, 0xc12d, 0x21, 0 + .dw 0x0dc0, 0xc12d, 0x0dff, 0xc12d, 0x21, 0 + .dw 0x0e40, 0xc12d, 0x0e7f, 0xc12d, 0x21, 0 + .dw 0x0ec0, 0xc12d, 0x0eff, 0xc12d, 0x21, 0 + .dw 0x0f40, 0xc12d, 0x0f7f, 0xc12d, 0x21, 0 + .dw 0x0fc0, 0xc12d, 0x0fff, 0xc12d, 0x21, 0 + .dw 0x1040, 0xc12d, 0x107f, 0xc12d, 0x21, 0 + .dw 0x10c0, 0xc12d, 0x10ff, 0xc12d, 0x21, 0 + .dw 0x1140, 0xc12d, 0x117f, 0xc12d, 0x21, 0 + .dw 0x11c0, 0xc12d, 0x11ff, 0xc12d, 0x21, 0 + .dw 0x1240, 0xc12d, 0x127f, 0xc12d, 0x21, 0 + .dw 0x12c0, 0xc12d, 0x12ff, 0xc12d, 0x21, 0 + .dw 0x1340, 0xc12d, 0x137f, 0xc12d, 0x21, 0 + .dw 0x13c0, 0xc12d, 0x13ff, 0xc12d, 0x21, 0 + .dw 0x1440, 0xc12d, 0x147f, 0xc12d, 0x21, 0 + .dw 0x14c0, 0xc12d, 0x14ff, 0xc12d, 0x21, 0 + .dw 0x1540, 0xc12d, 0x157f, 0xc12d, 0x21, 0 + .dw 0x15c0, 0xc12d, 0x15ff, 0xc12d, 0x21, 0 + .dw 0x1640, 0xc12d, 0x167f, 0xc12d, 0x21, 0 + .dw 0x16c0, 0xc12d, 0x16ff, 0xc12d, 0x21, 0 + .dw 0x1740, 0xc12d, 0x177f, 0xc12d, 0x21, 0 + .dw 0x17c0, 0xc12d, 0x17ff, 0xc12d, 0x21, 0 + .dw 0x1840, 0xc12d, 0x187f, 0xc12d, 0x21, 0 + .dw 0x18c0, 0xc12d, 0x18ff, 0xc12d, 0x21, 0 + .dw 0x1940, 0xc12d, 0x197f, 0xc12d, 0x21, 0 + .dw 0x19c0, 0xc12d, 0x1fff, 0xc12d, 0x21, 0 + .dw 0x2040, 0xc12d, 0x207f, 0xc12d, 0x21, 0 + .dw 0x20c0, 0xc12d, 0x20ff, 0xc12d, 0x21, 0 + .dw 0x2140, 0xc12d, 0x217f, 0xc12d, 0x21, 0 + .dw 0x21c0, 0xc12d, 0x21ff, 0xc12d, 0x21, 0 + .dw 0x2240, 0xc12d, 0x227f, 0xc12d, 0x21, 0 + .dw 0x22c0, 0xc12d, 0x22ff, 0xc12d, 0x21, 0 + .dw 0x2340, 0xc12d, 0x237f, 0xc12d, 0x21, 0 + .dw 0x23c0, 0xc12d, 0x23ff, 0xc12d, 0x21, 0 + .dw 0x2440, 0xc12d, 0x247f, 0xc12d, 0x21, 0 + .dw 0x24c0, 0xc12d, 0x24ff, 0xc12d, 0x21, 0 + .dw 0x2540, 0xc12d, 0x257f, 0xc12d, 0x21, 0 + .dw 0x25c0, 0xc12d, 0x25ff, 0xc12d, 0x21, 0 + .dw 0x2640, 0xc12d, 0x267f, 0xc12d, 0x21, 0 + .dw 0x26c0, 0xc12d, 0x26ff, 0xc12d, 0x21, 0 + .dw 0x2740, 0xc12d, 0x277f, 0xc12d, 0x21, 0 + .dw 0x27c0, 0xc12d, 0x27ff, 0xc12d, 0x21, 0 + .dw 0x2840, 0xc12d, 0x287f, 0xc12d, 0x21, 0 + .dw 0x28c0, 0xc12d, 0x28ff, 0xc12d, 0x21, 0 + .dw 0x2940, 0xc12d, 0x297f, 0xc12d, 0x21, 0 + .dw 0x29c0, 0xc12d, 0x29ff, 0xc12d, 0x21, 0 + .dw 0x2a40, 0xc12d, 0x2a7f, 0xc12d, 0x21, 0 + .dw 0x2ac0, 0xc12d, 0x2aff, 0xc12d, 0x21, 0 + .dw 0x2b40, 0xc12d, 0x2b7f, 0xc12d, 0x21, 0 + .dw 0x2bc0, 0xc12d, 0x2bff, 0xc12d, 0x21, 0 + .dw 0x2c40, 0xc12d, 0x2c7f, 0xc12d, 0x21, 0 + .dw 0x2cc0, 0xc12d, 0x2cff, 0xc12d, 0x21, 0 + .dw 0x2d40, 0xc12d, 0x2d7f, 0xc12d, 0x21, 0 + .dw 0x2dc0, 0xc12d, 0x2dff, 0xc12d, 0x21, 0 + .dw 0x2e40, 0xc12d, 0x2e7f, 0xc12d, 0x21, 0 + .dw 0x2ec0, 0xc12d, 0x2eff, 0xc12d, 0x21, 0 + .dw 0x2f40, 0xc12d, 0x2f7f, 0xc12d, 0x21, 0 + .dw 0x2fc0, 0xc12d, 0x2fff, 0xc12d, 0x21, 0 + .dw 0x3040, 0xc12d, 0x307f, 0xc12d, 0x21, 0 + .dw 0x30c0, 0xc12d, 0x30ff, 0xc12d, 0x21, 0 + .dw 0x3140, 0xc12d, 0x317f, 0xc12d, 0x21, 0 + .dw 0x31c0, 0xc12d, 0x31ff, 0xc12d, 0x21, 0 + .dw 0x3240, 0xc12d, 0x327f, 0xc12d, 0x21, 0 + .dw 0x32c0, 0xc12d, 0x32ff, 0xc12d, 0x21, 0 + .dw 0x3340, 0xc12d, 0x337f, 0xc12d, 0x21, 0 + .dw 0x33c0, 0xc12d, 0x33ff, 0xc12d, 0x21, 0 + .dw 0x3440, 0xc12d, 0x347f, 0xc12d, 0x21, 0 + .dw 0x34c0, 0xc12d, 0x34ff, 0xc12d, 0x21, 0 + .dw 0x3540, 0xc12d, 0x357f, 0xc12d, 0x21, 0 + .dw 0x35c0, 0xc12d, 0x35ff, 0xc12d, 0x21, 0 + .dw 0x3640, 0xc12d, 0x367f, 0xc12d, 0x21, 0 + .dw 0x36c0, 0xc12d, 0x36ff, 0xc12d, 0x21, 0 + .dw 0x3740, 0xc12d, 0x377f, 0xc12d, 0x21, 0 + .dw 0x37c0, 0xc12d, 0x37ff, 0xc12d, 0x21, 0 + .dw 0x3840, 0xc12d, 0x387f, 0xc12d, 0x21, 0 + .dw 0x38c0, 0xc12d, 0x38ff, 0xc12d, 0x21, 0 + .dw 0x3940, 0xc12d, 0x397f, 0xc12d, 0x21, 0 + .dw 0x39c0, 0xc12d, 0x3fff, 0xc12d, 0x21, 0 + .dw 0x4040, 0xc12d, 0x407f, 0xc12d, 0x21, 0 + .dw 0x40c0, 0xc12d, 0x40ff, 0xc12d, 0x21, 0 + .dw 0x4140, 0xc12d, 0x417f, 0xc12d, 0x21, 0 + .dw 0x41c0, 0xc12d, 0x41ff, 0xc12d, 0x21, 0 + .dw 0x4240, 0xc12d, 0x427f, 0xc12d, 0x21, 0 + .dw 0x42c0, 0xc12d, 0x42ff, 0xc12d, 0x21, 0 + .dw 0x4340, 0xc12d, 0x437f, 0xc12d, 0x21, 0 + .dw 0x43c0, 0xc12d, 0x43ff, 0xc12d, 0x21, 0 + .dw 0x4440, 0xc12d, 0x447f, 0xc12d, 0x21, 0 + .dw 0x44c0, 0xc12d, 0x44ff, 0xc12d, 0x21, 0 + .dw 0x4540, 0xc12d, 0x457f, 0xc12d, 0x21, 0 + .dw 0x45c0, 0xc12d, 0x45ff, 0xc12d, 0x21, 0 + .dw 0x4640, 0xc12d, 0x467f, 0xc12d, 0x21, 0 + .dw 0x46c0, 0xc12d, 0x46ff, 0xc12d, 0x21, 0 + .dw 0x4740, 0xc12d, 0x477f, 0xc12d, 0x21, 0 + .dw 0x47c0, 0xc12d, 0x47ff, 0xc12d, 0x21, 0 + .dw 0x4840, 0xc12d, 0x487f, 0xc12d, 0x21, 0 + .dw 0x48c0, 0xc12d, 0x48ff, 0xc12d, 0x21, 0 + .dw 0x4940, 0xc12d, 0x497f, 0xc12d, 0x21, 0 + .dw 0x49c0, 0xc12d, 0x49ff, 0xc12d, 0x21, 0 + .dw 0x4a40, 0xc12d, 0x4a7f, 0xc12d, 0x21, 0 + .dw 0x4ac0, 0xc12d, 0x4aff, 0xc12d, 0x21, 0 + .dw 0x4b40, 0xc12d, 0x4b7f, 0xc12d, 0x21, 0 + .dw 0x4bc0, 0xc12d, 0x4bff, 0xc12d, 0x21, 0 + .dw 0x4c40, 0xc12d, 0x4c7f, 0xc12d, 0x21, 0 + .dw 0x4cc0, 0xc12d, 0x4cff, 0xc12d, 0x21, 0 + .dw 0x4d40, 0xc12d, 0x4d7f, 0xc12d, 0x21, 0 + .dw 0x4dc0, 0xc12d, 0x4dff, 0xc12d, 0x21, 0 + .dw 0x4e40, 0xc12d, 0x4e7f, 0xc12d, 0x21, 0 + .dw 0x4ec0, 0xc12d, 0x4eff, 0xc12d, 0x21, 0 + .dw 0x4f40, 0xc12d, 0x4f7f, 0xc12d, 0x21, 0 + .dw 0x4fc0, 0xc12d, 0x4fff, 0xc12d, 0x21, 0 + .dw 0x5040, 0xc12d, 0x507f, 0xc12d, 0x21, 0 + .dw 0x50c0, 0xc12d, 0x50ff, 0xc12d, 0x21, 0 + .dw 0x5140, 0xc12d, 0x517f, 0xc12d, 0x21, 0 + .dw 0x51c0, 0xc12d, 0x51ff, 0xc12d, 0x21, 0 + .dw 0x5240, 0xc12d, 0x527f, 0xc12d, 0x21, 0 + .dw 0x52c0, 0xc12d, 0x52ff, 0xc12d, 0x21, 0 + .dw 0x5340, 0xc12d, 0x537f, 0xc12d, 0x21, 0 + .dw 0x53c0, 0xc12d, 0x53ff, 0xc12d, 0x21, 0 + .dw 0x5440, 0xc12d, 0x547f, 0xc12d, 0x21, 0 + .dw 0x54c0, 0xc12d, 0x54ff, 0xc12d, 0x21, 0 + .dw 0x5540, 0xc12d, 0x557f, 0xc12d, 0x21, 0 + .dw 0x55c0, 0xc12d, 0x55ff, 0xc12d, 0x21, 0 + .dw 0x5640, 0xc12d, 0x567f, 0xc12d, 0x21, 0 + .dw 0x56c0, 0xc12d, 0x56ff, 0xc12d, 0x21, 0 + .dw 0x5740, 0xc12d, 0x577f, 0xc12d, 0x21, 0 + .dw 0x57c0, 0xc12d, 0x57ff, 0xc12d, 0x21, 0 + .dw 0x5840, 0xc12d, 0x587f, 0xc12d, 0x21, 0 + .dw 0x58c0, 0xc12d, 0x58ff, 0xc12d, 0x21, 0 + .dw 0x5940, 0xc12d, 0x597f, 0xc12d, 0x21, 0 + .dw 0x59c0, 0xc12d, 0x5fff, 0xc12d, 0x21, 0 + .dw 0x6040, 0xc12d, 0x607f, 0xc12d, 0x21, 0 + .dw 0x60c0, 0xc12d, 0x60ff, 0xc12d, 0x21, 0 + .dw 0x6140, 0xc12d, 0x617f, 0xc12d, 0x21, 0 + .dw 0x61c0, 0xc12d, 0x61ff, 0xc12d, 0x21, 0 + .dw 0x6240, 0xc12d, 0x627f, 0xc12d, 0x21, 0 + .dw 0x62c0, 0xc12d, 0x62ff, 0xc12d, 0x21, 0 + .dw 0x6340, 0xc12d, 0x637f, 0xc12d, 0x21, 0 + .dw 0x63c0, 0xc12d, 0x63ff, 0xc12d, 0x21, 0 + .dw 0x6440, 0xc12d, 0x647f, 0xc12d, 0x21, 0 + .dw 0x64c0, 0xc12d, 0x64ff, 0xc12d, 0x21, 0 + .dw 0x6540, 0xc12d, 0x657f, 0xc12d, 0x21, 0 + .dw 0x65c0, 0xc12d, 0x65ff, 0xc12d, 0x21, 0 + .dw 0x6640, 0xc12d, 0x667f, 0xc12d, 0x21, 0 + .dw 0x66c0, 0xc12d, 0x66ff, 0xc12d, 0x21, 0 + .dw 0x6740, 0xc12d, 0x677f, 0xc12d, 0x21, 0 + .dw 0x67c0, 0xc12d, 0x67ff, 0xc12d, 0x21, 0 + .dw 0x6840, 0xc12d, 0x687f, 0xc12d, 0x21, 0 + .dw 0x68c0, 0xc12d, 0x68ff, 0xc12d, 0x21, 0 + .dw 0x6940, 0xc12d, 0x697f, 0xc12d, 0x21, 0 + .dw 0x69c0, 0xc12d, 0x69ff, 0xc12d, 0x21, 0 + .dw 0x6a40, 0xc12d, 0x6a7f, 0xc12d, 0x21, 0 + .dw 0x6ac0, 0xc12d, 0x6aff, 0xc12d, 0x21, 0 + .dw 0x6b40, 0xc12d, 0x6b7f, 0xc12d, 0x21, 0 + .dw 0x6bc0, 0xc12d, 0x6bff, 0xc12d, 0x21, 0 + .dw 0x6c40, 0xc12d, 0x6c7f, 0xc12d, 0x21, 0 + .dw 0x6cc0, 0xc12d, 0x6cff, 0xc12d, 0x21, 0 + .dw 0x6d40, 0xc12d, 0x6d7f, 0xc12d, 0x21, 0 + .dw 0x6dc0, 0xc12d, 0x6dff, 0xc12d, 0x21, 0 + .dw 0x6e40, 0xc12d, 0x6e7f, 0xc12d, 0x21, 0 + .dw 0x6ec0, 0xc12d, 0x6eff, 0xc12d, 0x21, 0 + .dw 0x6f40, 0xc12d, 0x6f7f, 0xc12d, 0x21, 0 + .dw 0x6fc0, 0xc12d, 0x6fff, 0xc12d, 0x21, 0 + .dw 0x7040, 0xc12d, 0x707f, 0xc12d, 0x21, 0 + .dw 0x70c0, 0xc12d, 0x70ff, 0xc12d, 0x21, 0 + .dw 0x7140, 0xc12d, 0x717f, 0xc12d, 0x21, 0 + .dw 0x71c0, 0xc12d, 0x71ff, 0xc12d, 0x21, 0 + .dw 0x7240, 0xc12d, 0x727f, 0xc12d, 0x21, 0 + .dw 0x72c0, 0xc12d, 0x72ff, 0xc12d, 0x21, 0 + .dw 0x7340, 0xc12d, 0x737f, 0xc12d, 0x21, 0 + .dw 0x73c0, 0xc12d, 0x73ff, 0xc12d, 0x21, 0 + .dw 0x7440, 0xc12d, 0x747f, 0xc12d, 0x21, 0 + .dw 0x74c0, 0xc12d, 0x74ff, 0xc12d, 0x21, 0 + .dw 0x7540, 0xc12d, 0x757f, 0xc12d, 0x21, 0 + .dw 0x75c0, 0xc12d, 0x75ff, 0xc12d, 0x21, 0 + .dw 0x7640, 0xc12d, 0x767f, 0xc12d, 0x21, 0 + .dw 0x76c0, 0xc12d, 0x76ff, 0xc12d, 0x21, 0 + .dw 0x7740, 0xc12d, 0x777f, 0xc12d, 0x21, 0 + .dw 0x77c0, 0xc12d, 0x77ff, 0xc12d, 0x21, 0 + .dw 0x7840, 0xc12d, 0x787f, 0xc12d, 0x21, 0 + .dw 0x78c0, 0xc12d, 0x78ff, 0xc12d, 0x21, 0 + .dw 0x7940, 0xc12d, 0x797f, 0xc12d, 0x21, 0 + .dw 0x79c0, 0xc12d, 0x7fff, 0xc12d, 0x21, 0 + .dw 0x8040, 0xc12d, 0x807f, 0xc12d, 0x21, 0 + .dw 0x80c0, 0xc12d, 0x80ff, 0xc12d, 0x21, 0 + .dw 0x8140, 0xc12d, 0x817f, 0xc12d, 0x21, 0 + .dw 0x81c0, 0xc12d, 0x81ff, 0xc12d, 0x21, 0 + .dw 0x8240, 0xc12d, 0x827f, 0xc12d, 0x21, 0 + .dw 0x82c0, 0xc12d, 0x82ff, 0xc12d, 0x21, 0 + .dw 0x8340, 0xc12d, 0x837f, 0xc12d, 0x21, 0 + .dw 0x83c0, 0xc12d, 0x83ff, 0xc12d, 0x21, 0 + .dw 0x8440, 0xc12d, 0x847f, 0xc12d, 0x21, 0 + .dw 0x84c0, 0xc12d, 0x84ff, 0xc12d, 0x21, 0 + .dw 0x8540, 0xc12d, 0x857f, 0xc12d, 0x21, 0 + .dw 0x85c0, 0xc12d, 0x85ff, 0xc12d, 0x21, 0 + .dw 0x8640, 0xc12d, 0x867f, 0xc12d, 0x21, 0 + .dw 0x86c0, 0xc12d, 0x86ff, 0xc12d, 0x21, 0 + .dw 0x8740, 0xc12d, 0x877f, 0xc12d, 0x21, 0 + .dw 0x87c0, 0xc12d, 0x87ff, 0xc12d, 0x21, 0 + .dw 0x8840, 0xc12d, 0x887f, 0xc12d, 0x21, 0 + .dw 0x88c0, 0xc12d, 0x88ff, 0xc12d, 0x21, 0 + .dw 0x8940, 0xc12d, 0x897f, 0xc12d, 0x21, 0 + .dw 0x89c0, 0xc12d, 0x89ff, 0xc12d, 0x21, 0 + .dw 0x8a40, 0xc12d, 0x8a7f, 0xc12d, 0x21, 0 + .dw 0x8ac0, 0xc12d, 0x8aff, 0xc12d, 0x21, 0 + .dw 0x8b40, 0xc12d, 0x8b7f, 0xc12d, 0x21, 0 + .dw 0x8bc0, 0xc12d, 0x8bff, 0xc12d, 0x21, 0 + .dw 0x8c40, 0xc12d, 0x8c7f, 0xc12d, 0x21, 0 + .dw 0x8cc0, 0xc12d, 0x8cff, 0xc12d, 0x21, 0 + .dw 0x8d40, 0xc12d, 0x8d7f, 0xc12d, 0x21, 0 + .dw 0x8dc0, 0xc12d, 0x8dff, 0xc12d, 0x21, 0 + .dw 0x8e40, 0xc12d, 0x8e7f, 0xc12d, 0x21, 0 + .dw 0x8ec0, 0xc12d, 0x8eff, 0xc12d, 0x21, 0 + .dw 0x8f40, 0xc12d, 0x8f7f, 0xc12d, 0x21, 0 + .dw 0x8fc0, 0xc12d, 0x8fff, 0xc12d, 0x21, 0 + .dw 0x9040, 0xc12d, 0x907f, 0xc12d, 0x21, 0 + .dw 0x90c0, 0xc12d, 0x90ff, 0xc12d, 0x21, 0 + .dw 0x9140, 0xc12d, 0x917f, 0xc12d, 0x21, 0 + .dw 0x91c0, 0xc12d, 0x91ff, 0xc12d, 0x21, 0 + .dw 0x9240, 0xc12d, 0x927f, 0xc12d, 0x21, 0 + .dw 0x92c0, 0xc12d, 0x92ff, 0xc12d, 0x21, 0 + .dw 0x9340, 0xc12d, 0x937f, 0xc12d, 0x21, 0 + .dw 0x93c0, 0xc12d, 0x93ff, 0xc12d, 0x21, 0 + .dw 0x9440, 0xc12d, 0x947f, 0xc12d, 0x21, 0 + .dw 0x94c0, 0xc12d, 0x94ff, 0xc12d, 0x21, 0 + .dw 0x9540, 0xc12d, 0x957f, 0xc12d, 0x21, 0 + .dw 0x95c0, 0xc12d, 0x95ff, 0xc12d, 0x21, 0 + .dw 0x9640, 0xc12d, 0x967f, 0xc12d, 0x21, 0 + .dw 0x96c0, 0xc12d, 0x96ff, 0xc12d, 0x21, 0 + .dw 0x9740, 0xc12d, 0x977f, 0xc12d, 0x21, 0 + .dw 0x97c0, 0xc12d, 0x97ff, 0xc12d, 0x21, 0 + .dw 0x9840, 0xc12d, 0x987f, 0xc12d, 0x21, 0 + .dw 0x98c0, 0xc12d, 0x98ff, 0xc12d, 0x21, 0 + .dw 0x9940, 0xc12d, 0x997f, 0xc12d, 0x21, 0 + .dw 0x99c0, 0xc12d, 0x9fff, 0xc12d, 0x21, 0 + .dw 0xa040, 0xc12d, 0xa07f, 0xc12d, 0x21, 0 + .dw 0xa0c0, 0xc12d, 0xa0ff, 0xc12d, 0x21, 0 + .dw 0xa140, 0xc12d, 0xa17f, 0xc12d, 0x21, 0 + .dw 0xa1c0, 0xc12d, 0xa1ff, 0xc12d, 0x21, 0 + .dw 0xa240, 0xc12d, 0xa27f, 0xc12d, 0x21, 0 + .dw 0xa2c0, 0xc12d, 0xa2ff, 0xc12d, 0x21, 0 + .dw 0xa340, 0xc12d, 0xa37f, 0xc12d, 0x21, 0 + .dw 0xa3c0, 0xc12d, 0xa3ff, 0xc12d, 0x21, 0 + .dw 0xa440, 0xc12d, 0xa47f, 0xc12d, 0x21, 0 + .dw 0xa4c0, 0xc12d, 0xa4ff, 0xc12d, 0x21, 0 + .dw 0xa540, 0xc12d, 0xa57f, 0xc12d, 0x21, 0 + .dw 0xa5c0, 0xc12d, 0xa5ff, 0xc12d, 0x21, 0 + .dw 0xa640, 0xc12d, 0xa67f, 0xc12d, 0x21, 0 + .dw 0xa6c0, 0xc12d, 0xa6ff, 0xc12d, 0x21, 0 + .dw 0xa740, 0xc12d, 0xa77f, 0xc12d, 0x21, 0 + .dw 0xa7c0, 0xc12d, 0xa7ff, 0xc12d, 0x21, 0 + .dw 0xa840, 0xc12d, 0xa87f, 0xc12d, 0x21, 0 + .dw 0xa8c0, 0xc12d, 0xa8ff, 0xc12d, 0x21, 0 + .dw 0xa940, 0xc12d, 0xa97f, 0xc12d, 0x21, 0 + .dw 0xa9c0, 0xc12d, 0xa9ff, 0xc12d, 0x21, 0 + .dw 0xaa40, 0xc12d, 0xaa7f, 0xc12d, 0x21, 0 + .dw 0xaac0, 0xc12d, 0xaaff, 0xc12d, 0x21, 0 + .dw 0xab40, 0xc12d, 0xab7f, 0xc12d, 0x21, 0 + .dw 0xabc0, 0xc12d, 0xabff, 0xc12d, 0x21, 0 + .dw 0xac40, 0xc12d, 0xac7f, 0xc12d, 0x21, 0 + .dw 0xacc0, 0xc12d, 0xacff, 0xc12d, 0x21, 0 + .dw 0xad40, 0xc12d, 0xad7f, 0xc12d, 0x21, 0 + .dw 0xadc0, 0xc12d, 0xadff, 0xc12d, 0x21, 0 + .dw 0xae40, 0xc12d, 0xae7f, 0xc12d, 0x21, 0 + .dw 0xaec0, 0xc12d, 0xaeff, 0xc12d, 0x21, 0 + .dw 0xaf40, 0xc12d, 0xaf7f, 0xc12d, 0x21, 0 + .dw 0xafc0, 0xc12d, 0xafff, 0xc12d, 0x21, 0 + .dw 0xb040, 0xc12d, 0xb07f, 0xc12d, 0x21, 0 + .dw 0xb0c0, 0xc12d, 0xb0ff, 0xc12d, 0x21, 0 + .dw 0xb140, 0xc12d, 0xb17f, 0xc12d, 0x21, 0 + .dw 0xb1c0, 0xc12d, 0xb1ff, 0xc12d, 0x21, 0 + .dw 0xb240, 0xc12d, 0xb27f, 0xc12d, 0x21, 0 + .dw 0xb2c0, 0xc12d, 0xb2ff, 0xc12d, 0x21, 0 + .dw 0xb340, 0xc12d, 0xb37f, 0xc12d, 0x21, 0 + .dw 0xb3c0, 0xc12d, 0xb3ff, 0xc12d, 0x21, 0 + .dw 0xb440, 0xc12d, 0xb47f, 0xc12d, 0x21, 0 + .dw 0xb4c0, 0xc12d, 0xb4ff, 0xc12d, 0x21, 0 + .dw 0xb540, 0xc12d, 0xb57f, 0xc12d, 0x21, 0 + .dw 0xb5c0, 0xc12d, 0xb5ff, 0xc12d, 0x21, 0 + .dw 0xb640, 0xc12d, 0xb67f, 0xc12d, 0x21, 0 + .dw 0xb6c0, 0xc12d, 0xb6ff, 0xc12d, 0x21, 0 + .dw 0xb740, 0xc12d, 0xb77f, 0xc12d, 0x21, 0 + .dw 0xb7c0, 0xc12d, 0xb7ff, 0xc12d, 0x21, 0 + .dw 0xb840, 0xc12d, 0xb87f, 0xc12d, 0x21, 0 + .dw 0xb8c0, 0xc12d, 0xb8ff, 0xc12d, 0x21, 0 + .dw 0xb940, 0xc12d, 0xb97f, 0xc12d, 0x21, 0 + .dw 0xb9c0, 0xc12d, 0xbfff, 0xc12d, 0x21, 0 + .dw 0xc040, 0xc12d, 0xc07f, 0xc12d, 0x21, 0 + .dw 0xc0c0, 0xc12d, 0xc0ff, 0xc12d, 0x21, 0 + .dw 0xc140, 0xc12d, 0xc17f, 0xc12d, 0x21, 0 + .dw 0xc1c0, 0xc12d, 0xc1ff, 0xc12d, 0x21, 0 + .dw 0xc240, 0xc12d, 0xc27f, 0xc12d, 0x21, 0 + .dw 0xc2c0, 0xc12d, 0xc2ff, 0xc12d, 0x21, 0 + .dw 0xc340, 0xc12d, 0xc37f, 0xc12d, 0x21, 0 + .dw 0xc3c0, 0xc12d, 0xc3ff, 0xc12d, 0x21, 0 + .dw 0xc440, 0xc12d, 0xc47f, 0xc12d, 0x21, 0 + .dw 0xc4c0, 0xc12d, 0xc4ff, 0xc12d, 0x21, 0 + .dw 0xc540, 0xc12d, 0xc57f, 0xc12d, 0x21, 0 + .dw 0xc5c0, 0xc12d, 0xc5ff, 0xc12d, 0x21, 0 + .dw 0xc640, 0xc12d, 0xc67f, 0xc12d, 0x21, 0 + .dw 0xc6c0, 0xc12d, 0xc6ff, 0xc12d, 0x21, 0 + .dw 0xc740, 0xc12d, 0xc77f, 0xc12d, 0x21, 0 + .dw 0xc7c0, 0xc12d, 0xc7ff, 0xc12d, 0x21, 0 + .dw 0xc840, 0xc12d, 0xc87f, 0xc12d, 0x21, 0 + .dw 0xc8c0, 0xc12d, 0xc8ff, 0xc12d, 0x21, 0 + .dw 0xc940, 0xc12d, 0xc97f, 0xc12d, 0x21, 0 + .dw 0xc9c0, 0xc12d, 0xc9ff, 0xc12d, 0x21, 0 + .dw 0xca40, 0xc12d, 0xca7f, 0xc12d, 0x21, 0 + .dw 0xcac0, 0xc12d, 0xcaff, 0xc12d, 0x21, 0 + .dw 0xcb40, 0xc12d, 0xcb7f, 0xc12d, 0x21, 0 + .dw 0xcbc0, 0xc12d, 0xcbff, 0xc12d, 0x21, 0 + .dw 0xcc40, 0xc12d, 0xcc7f, 0xc12d, 0x21, 0 + .dw 0xccc0, 0xc12d, 0xccff, 0xc12d, 0x21, 0 + .dw 0xcd40, 0xc12d, 0xcd7f, 0xc12d, 0x21, 0 + .dw 0xcdc0, 0xc12d, 0xcdff, 0xc12d, 0x21, 0 + .dw 0xce40, 0xc12d, 0xce7f, 0xc12d, 0x21, 0 + .dw 0xcec0, 0xc12d, 0xceff, 0xc12d, 0x21, 0 + .dw 0xcf40, 0xc12d, 0xcf7f, 0xc12d, 0x21, 0 + .dw 0xcfc0, 0xc12d, 0xcfff, 0xc12d, 0x21, 0 + .dw 0xd040, 0xc12d, 0xd07f, 0xc12d, 0x21, 0 + .dw 0xd0c0, 0xc12d, 0xd0ff, 0xc12d, 0x21, 0 + .dw 0xd140, 0xc12d, 0xd17f, 0xc12d, 0x21, 0 + .dw 0xd1c0, 0xc12d, 0xd1ff, 0xc12d, 0x21, 0 + .dw 0xd240, 0xc12d, 0xd27f, 0xc12d, 0x21, 0 + .dw 0xd2c0, 0xc12d, 0xd2ff, 0xc12d, 0x21, 0 + .dw 0xd340, 0xc12d, 0xd37f, 0xc12d, 0x21, 0 + .dw 0xd3c0, 0xc12d, 0xd3ff, 0xc12d, 0x21, 0 + .dw 0xd440, 0xc12d, 0xd47f, 0xc12d, 0x21, 0 + .dw 0xd4c0, 0xc12d, 0xd4ff, 0xc12d, 0x21, 0 + .dw 0xd540, 0xc12d, 0xd57f, 0xc12d, 0x21, 0 + .dw 0xd5c0, 0xc12d, 0xd5ff, 0xc12d, 0x21, 0 + .dw 0xd640, 0xc12d, 0xd67f, 0xc12d, 0x21, 0 + .dw 0xd6c0, 0xc12d, 0xd6ff, 0xc12d, 0x21, 0 + .dw 0xd740, 0xc12d, 0xd77f, 0xc12d, 0x21, 0 + .dw 0xd7c0, 0xc12d, 0xd7ff, 0xc12d, 0x21, 0 + .dw 0xd840, 0xc12d, 0xd87f, 0xc12d, 0x21, 0 + .dw 0xd8c0, 0xc12d, 0xd8ff, 0xc12d, 0x21, 0 + .dw 0xd940, 0xc12d, 0xd97f, 0xc12d, 0x21, 0 + .dw 0xd9c0, 0xc12d, 0xdfff, 0xc12d, 0x21, 0 + .dw 0xe040, 0xc12d, 0xe07f, 0xc12d, 0x21, 0 + .dw 0xe0c0, 0xc12d, 0xe0ff, 0xc12d, 0x21, 0 + .dw 0xe140, 0xc12d, 0xe17f, 0xc12d, 0x21, 0 + .dw 0xe1c0, 0xc12d, 0xe1ff, 0xc12d, 0x21, 0 + .dw 0xe240, 0xc12d, 0xe27f, 0xc12d, 0x21, 0 + .dw 0xe2c0, 0xc12d, 0xe2ff, 0xc12d, 0x21, 0 + .dw 0xe340, 0xc12d, 0xe37f, 0xc12d, 0x21, 0 + .dw 0xe3c0, 0xc12d, 0xe3ff, 0xc12d, 0x21, 0 + .dw 0xe440, 0xc12d, 0xe47f, 0xc12d, 0x21, 0 + .dw 0xe4c0, 0xc12d, 0xe4ff, 0xc12d, 0x21, 0 + .dw 0xe540, 0xc12d, 0xe57f, 0xc12d, 0x21, 0 + .dw 0xe5c0, 0xc12d, 0xe5ff, 0xc12d, 0x21, 0 + .dw 0xe640, 0xc12d, 0xe67f, 0xc12d, 0x21, 0 + .dw 0xe6c0, 0xc12d, 0xe6ff, 0xc12d, 0x21, 0 + .dw 0xe740, 0xc12d, 0xe77f, 0xc12d, 0x21, 0 + .dw 0xe7c0, 0xc12d, 0xe7ff, 0xc12d, 0x21, 0 + .dw 0xe840, 0xc12d, 0xe87f, 0xc12d, 0x21, 0 + .dw 0xe8c0, 0xc12d, 0xe8ff, 0xc12d, 0x21, 0 + .dw 0xe940, 0xc12d, 0xe97f, 0xc12d, 0x21, 0 + .dw 0xe9c0, 0xc12d, 0xe9ff, 0xc12d, 0x21, 0 + .dw 0xea40, 0xc12d, 0xea7f, 0xc12d, 0x21, 0 + .dw 0xeac0, 0xc12d, 0xeaff, 0xc12d, 0x21, 0 + .dw 0xeb40, 0xc12d, 0xeb7f, 0xc12d, 0x21, 0 + .dw 0xebc0, 0xc12d, 0xebff, 0xc12d, 0x21, 0 + .dw 0xec40, 0xc12d, 0xec7f, 0xc12d, 0x21, 0 + .dw 0xecc0, 0xc12d, 0xecff, 0xc12d, 0x21, 0 + .dw 0xed40, 0xc12d, 0xed7f, 0xc12d, 0x21, 0 + .dw 0xedc0, 0xc12d, 0xedff, 0xc12d, 0x21, 0 + .dw 0xee40, 0xc12d, 0xee7f, 0xc12d, 0x21, 0 + .dw 0xeec0, 0xc12d, 0xeeff, 0xc12d, 0x21, 0 + .dw 0xef40, 0xc12d, 0xef7f, 0xc12d, 0x21, 0 + .dw 0xefc0, 0xc12d, 0xefff, 0xc12d, 0x21, 0 + .dw 0xf040, 0xc12d, 0xf07f, 0xc12d, 0x21, 0 + .dw 0xf0c0, 0xc12d, 0xf0ff, 0xc12d, 0x21, 0 + .dw 0xf140, 0xc12d, 0xf17f, 0xc12d, 0x21, 0 + .dw 0xf1c0, 0xc12d, 0xf1ff, 0xc12d, 0x21, 0 + .dw 0xf240, 0xc12d, 0xf27f, 0xc12d, 0x21, 0 + .dw 0xf2c0, 0xc12d, 0xf2ff, 0xc12d, 0x21, 0 + .dw 0xf340, 0xc12d, 0xf37f, 0xc12d, 0x21, 0 + .dw 0xf3c0, 0xc12d, 0xf3ff, 0xc12d, 0x21, 0 + .dw 0xf440, 0xc12d, 0xf47f, 0xc12d, 0x21, 0 + .dw 0xf4c0, 0xc12d, 0xf4ff, 0xc12d, 0x21, 0 + .dw 0xf540, 0xc12d, 0xf57f, 0xc12d, 0x21, 0 + .dw 0xf5c0, 0xc12d, 0xf5ff, 0xc12d, 0x21, 0 + .dw 0xf640, 0xc12d, 0xf67f, 0xc12d, 0x21, 0 + .dw 0xf6c0, 0xc12d, 0xf6ff, 0xc12d, 0x21, 0 + .dw 0xf740, 0xc12d, 0xf77f, 0xc12d, 0x21, 0 + .dw 0xf7c0, 0xc12d, 0xf7ff, 0xc12d, 0x21, 0 + .dw 0xf840, 0xc12d, 0xf87f, 0xc12d, 0x21, 0 + .dw 0xf8c0, 0xc12d, 0xf8ff, 0xc12d, 0x21, 0 + .dw 0xf940, 0xc12d, 0xf97f, 0xc12d, 0x21, 0 + .dw 0xf9c0, 0xc12d, 0xffff, 0xc12d, 0x21, 0 + .dw 0x0040, 0xc12e, 0x007f, 0xc12e, 0x21, 0 + .dw 0x00c0, 0xc12e, 0x00ff, 0xc12e, 0x21, 0 + .dw 0x0140, 0xc12e, 0x017f, 0xc12e, 0x21, 0 + .dw 0x01c0, 0xc12e, 0x01ff, 0xc12e, 0x21, 0 + .dw 0x0240, 0xc12e, 0x027f, 0xc12e, 0x21, 0 + .dw 0x02c0, 0xc12e, 0x02ff, 0xc12e, 0x21, 0 + .dw 0x0340, 0xc12e, 0x037f, 0xc12e, 0x21, 0 + .dw 0x03c0, 0xc12e, 0x03ff, 0xc12e, 0x21, 0 + .dw 0x0440, 0xc12e, 0x047f, 0xc12e, 0x21, 0 + .dw 0x04c0, 0xc12e, 0x04ff, 0xc12e, 0x21, 0 + .dw 0x0540, 0xc12e, 0x057f, 0xc12e, 0x21, 0 + .dw 0x05c0, 0xc12e, 0x05ff, 0xc12e, 0x21, 0 + .dw 0x0640, 0xc12e, 0x067f, 0xc12e, 0x21, 0 + .dw 0x06c0, 0xc12e, 0x06ff, 0xc12e, 0x21, 0 + .dw 0x0740, 0xc12e, 0x077f, 0xc12e, 0x21, 0 + .dw 0x07c0, 0xc12e, 0x07ff, 0xc12e, 0x21, 0 + .dw 0x0840, 0xc12e, 0x087f, 0xc12e, 0x21, 0 + .dw 0x08c0, 0xc12e, 0x08ff, 0xc12e, 0x21, 0 + .dw 0x0940, 0xc12e, 0x097f, 0xc12e, 0x21, 0 + .dw 0x09c0, 0xc12e, 0x09ff, 0xc12e, 0x21, 0 + .dw 0x0a40, 0xc12e, 0x0a7f, 0xc12e, 0x21, 0 + .dw 0x0ac0, 0xc12e, 0x0aff, 0xc12e, 0x21, 0 + .dw 0x0b40, 0xc12e, 0x0b7f, 0xc12e, 0x21, 0 + .dw 0x0bc0, 0xc12e, 0x0bff, 0xc12e, 0x21, 0 + .dw 0x0c40, 0xc12e, 0x0c7f, 0xc12e, 0x21, 0 + .dw 0x0cc0, 0xc12e, 0x0cff, 0xc12e, 0x21, 0 + .dw 0x0d40, 0xc12e, 0x0d7f, 0xc12e, 0x21, 0 + .dw 0x0dc0, 0xc12e, 0x0dff, 0xc12e, 0x21, 0 + .dw 0x0e40, 0xc12e, 0x0e7f, 0xc12e, 0x21, 0 + .dw 0x0ec0, 0xc12e, 0x0eff, 0xc12e, 0x21, 0 + .dw 0x0f40, 0xc12e, 0x0f7f, 0xc12e, 0x21, 0 + .dw 0x0fc0, 0xc12e, 0x0fff, 0xc12e, 0x21, 0 + .dw 0x1040, 0xc12e, 0x107f, 0xc12e, 0x21, 0 + .dw 0x10c0, 0xc12e, 0x10ff, 0xc12e, 0x21, 0 + .dw 0x1140, 0xc12e, 0x117f, 0xc12e, 0x21, 0 + .dw 0x11c0, 0xc12e, 0x11ff, 0xc12e, 0x21, 0 + .dw 0x1240, 0xc12e, 0x127f, 0xc12e, 0x21, 0 + .dw 0x12c0, 0xc12e, 0x12ff, 0xc12e, 0x21, 0 + .dw 0x1340, 0xc12e, 0x137f, 0xc12e, 0x21, 0 + .dw 0x13c0, 0xc12e, 0x13ff, 0xc12e, 0x21, 0 + .dw 0x1440, 0xc12e, 0x147f, 0xc12e, 0x21, 0 + .dw 0x14c0, 0xc12e, 0x14ff, 0xc12e, 0x21, 0 + .dw 0x1540, 0xc12e, 0x157f, 0xc12e, 0x21, 0 + .dw 0x15c0, 0xc12e, 0x15ff, 0xc12e, 0x21, 0 + .dw 0x1640, 0xc12e, 0x167f, 0xc12e, 0x21, 0 + .dw 0x16c0, 0xc12e, 0x16ff, 0xc12e, 0x21, 0 + .dw 0x1740, 0xc12e, 0x177f, 0xc12e, 0x21, 0 + .dw 0x17c0, 0xc12e, 0x17ff, 0xc12e, 0x21, 0 + .dw 0x1840, 0xc12e, 0x187f, 0xc12e, 0x21, 0 + .dw 0x18c0, 0xc12e, 0x18ff, 0xc12e, 0x21, 0 + .dw 0x1940, 0xc12e, 0x197f, 0xc12e, 0x21, 0 + .dw 0x19c0, 0xc12e, 0x1fff, 0xc12e, 0x21, 0 + .dw 0x2040, 0xc12e, 0x207f, 0xc12e, 0x21, 0 + .dw 0x20c0, 0xc12e, 0x20ff, 0xc12e, 0x21, 0 + .dw 0x2140, 0xc12e, 0x217f, 0xc12e, 0x21, 0 + .dw 0x21c0, 0xc12e, 0x21ff, 0xc12e, 0x21, 0 + .dw 0x2240, 0xc12e, 0x227f, 0xc12e, 0x21, 0 + .dw 0x22c0, 0xc12e, 0x22ff, 0xc12e, 0x21, 0 + .dw 0x2340, 0xc12e, 0x237f, 0xc12e, 0x21, 0 + .dw 0x23c0, 0xc12e, 0x23ff, 0xc12e, 0x21, 0 + .dw 0x2440, 0xc12e, 0x247f, 0xc12e, 0x21, 0 + .dw 0x24c0, 0xc12e, 0x24ff, 0xc12e, 0x21, 0 + .dw 0x2540, 0xc12e, 0x257f, 0xc12e, 0x21, 0 + .dw 0x25c0, 0xc12e, 0x25ff, 0xc12e, 0x21, 0 + .dw 0x2640, 0xc12e, 0x267f, 0xc12e, 0x21, 0 + .dw 0x26c0, 0xc12e, 0x26ff, 0xc12e, 0x21, 0 + .dw 0x2740, 0xc12e, 0x277f, 0xc12e, 0x21, 0 + .dw 0x27c0, 0xc12e, 0x27ff, 0xc12e, 0x21, 0 + .dw 0x2840, 0xc12e, 0x287f, 0xc12e, 0x21, 0 + .dw 0x28c0, 0xc12e, 0x28ff, 0xc12e, 0x21, 0 + .dw 0x2940, 0xc12e, 0x297f, 0xc12e, 0x21, 0 + .dw 0x29c0, 0xc12e, 0x29ff, 0xc12e, 0x21, 0 + .dw 0x2a40, 0xc12e, 0x2a7f, 0xc12e, 0x21, 0 + .dw 0x2ac0, 0xc12e, 0x2aff, 0xc12e, 0x21, 0 + .dw 0x2b40, 0xc12e, 0x2b7f, 0xc12e, 0x21, 0 + .dw 0x2bc0, 0xc12e, 0x2bff, 0xc12e, 0x21, 0 + .dw 0x2c40, 0xc12e, 0x2c7f, 0xc12e, 0x21, 0 + .dw 0x2cc0, 0xc12e, 0x2cff, 0xc12e, 0x21, 0 + .dw 0x2d40, 0xc12e, 0x2d7f, 0xc12e, 0x21, 0 + .dw 0x2dc0, 0xc12e, 0x2dff, 0xc12e, 0x21, 0 + .dw 0x2e40, 0xc12e, 0x2e7f, 0xc12e, 0x21, 0 + .dw 0x2ec0, 0xc12e, 0x2eff, 0xc12e, 0x21, 0 + .dw 0x2f40, 0xc12e, 0x2f7f, 0xc12e, 0x21, 0 + .dw 0x2fc0, 0xc12e, 0x2fff, 0xc12e, 0x21, 0 + .dw 0x3040, 0xc12e, 0x307f, 0xc12e, 0x21, 0 + .dw 0x30c0, 0xc12e, 0x30ff, 0xc12e, 0x21, 0 + .dw 0x3140, 0xc12e, 0x317f, 0xc12e, 0x21, 0 + .dw 0x31c0, 0xc12e, 0x31ff, 0xc12e, 0x21, 0 + .dw 0x3240, 0xc12e, 0x327f, 0xc12e, 0x21, 0 + .dw 0x32c0, 0xc12e, 0x32ff, 0xc12e, 0x21, 0 + .dw 0x3340, 0xc12e, 0x337f, 0xc12e, 0x21, 0 + .dw 0x33c0, 0xc12e, 0x33ff, 0xc12e, 0x21, 0 + .dw 0x3440, 0xc12e, 0x347f, 0xc12e, 0x21, 0 + .dw 0x34c0, 0xc12e, 0x34ff, 0xc12e, 0x21, 0 + .dw 0x3540, 0xc12e, 0x357f, 0xc12e, 0x21, 0 + .dw 0x35c0, 0xc12e, 0x35ff, 0xc12e, 0x21, 0 + .dw 0x3640, 0xc12e, 0x367f, 0xc12e, 0x21, 0 + .dw 0x36c0, 0xc12e, 0x36ff, 0xc12e, 0x21, 0 + .dw 0x3740, 0xc12e, 0x377f, 0xc12e, 0x21, 0 + .dw 0x37c0, 0xc12e, 0x37ff, 0xc12e, 0x21, 0 + .dw 0x3840, 0xc12e, 0x387f, 0xc12e, 0x21, 0 + .dw 0x38c0, 0xc12e, 0x38ff, 0xc12e, 0x21, 0 + .dw 0x3940, 0xc12e, 0x397f, 0xc12e, 0x21, 0 + .dw 0x39c0, 0xc12e, 0x3fff, 0xc12e, 0x21, 0 + .dw 0x4040, 0xc12e, 0x407f, 0xc12e, 0x21, 0 + .dw 0x40c0, 0xc12e, 0x40ff, 0xc12e, 0x21, 0 + .dw 0x4140, 0xc12e, 0x417f, 0xc12e, 0x21, 0 + .dw 0x41c0, 0xc12e, 0x41ff, 0xc12e, 0x21, 0 + .dw 0x4240, 0xc12e, 0x427f, 0xc12e, 0x21, 0 + .dw 0x42c0, 0xc12e, 0x42ff, 0xc12e, 0x21, 0 + .dw 0x4340, 0xc12e, 0x437f, 0xc12e, 0x21, 0 + .dw 0x43c0, 0xc12e, 0x43ff, 0xc12e, 0x21, 0 + .dw 0x4440, 0xc12e, 0x447f, 0xc12e, 0x21, 0 + .dw 0x44c0, 0xc12e, 0x44ff, 0xc12e, 0x21, 0 + .dw 0x4540, 0xc12e, 0x457f, 0xc12e, 0x21, 0 + .dw 0x45c0, 0xc12e, 0x45ff, 0xc12e, 0x21, 0 + .dw 0x4640, 0xc12e, 0x467f, 0xc12e, 0x21, 0 + .dw 0x46c0, 0xc12e, 0x46ff, 0xc12e, 0x21, 0 + .dw 0x4740, 0xc12e, 0x477f, 0xc12e, 0x21, 0 + .dw 0x47c0, 0xc12e, 0x47ff, 0xc12e, 0x21, 0 + .dw 0x4840, 0xc12e, 0x487f, 0xc12e, 0x21, 0 + .dw 0x48c0, 0xc12e, 0x48ff, 0xc12e, 0x21, 0 + .dw 0x4940, 0xc12e, 0x497f, 0xc12e, 0x21, 0 + .dw 0x49c0, 0xc12e, 0x49ff, 0xc12e, 0x21, 0 + .dw 0x4a40, 0xc12e, 0x4a7f, 0xc12e, 0x21, 0 + .dw 0x4ac0, 0xc12e, 0x4aff, 0xc12e, 0x21, 0 + .dw 0x4b40, 0xc12e, 0x4b7f, 0xc12e, 0x21, 0 + .dw 0x4bc0, 0xc12e, 0x4bff, 0xc12e, 0x21, 0 + .dw 0x4c40, 0xc12e, 0x4c7f, 0xc12e, 0x21, 0 + .dw 0x4cc0, 0xc12e, 0x4cff, 0xc12e, 0x21, 0 + .dw 0x4d40, 0xc12e, 0x4d7f, 0xc12e, 0x21, 0 + .dw 0x4dc0, 0xc12e, 0x4dff, 0xc12e, 0x21, 0 + .dw 0x4e40, 0xc12e, 0x4e7f, 0xc12e, 0x21, 0 + .dw 0x4ec0, 0xc12e, 0x4eff, 0xc12e, 0x21, 0 + .dw 0x4f40, 0xc12e, 0x4f7f, 0xc12e, 0x21, 0 + .dw 0x4fc0, 0xc12e, 0x4fff, 0xc12e, 0x21, 0 + .dw 0x5040, 0xc12e, 0x507f, 0xc12e, 0x21, 0 + .dw 0x50c0, 0xc12e, 0x50ff, 0xc12e, 0x21, 0 + .dw 0x5140, 0xc12e, 0x517f, 0xc12e, 0x21, 0 + .dw 0x51c0, 0xc12e, 0x51ff, 0xc12e, 0x21, 0 + .dw 0x5240, 0xc12e, 0x527f, 0xc12e, 0x21, 0 + .dw 0x52c0, 0xc12e, 0x52ff, 0xc12e, 0x21, 0 + .dw 0x5340, 0xc12e, 0x537f, 0xc12e, 0x21, 0 + .dw 0x53c0, 0xc12e, 0x53ff, 0xc12e, 0x21, 0 + .dw 0x5440, 0xc12e, 0x547f, 0xc12e, 0x21, 0 + .dw 0x54c0, 0xc12e, 0x54ff, 0xc12e, 0x21, 0 + .dw 0x5540, 0xc12e, 0x557f, 0xc12e, 0x21, 0 + .dw 0x55c0, 0xc12e, 0x55ff, 0xc12e, 0x21, 0 + .dw 0x5640, 0xc12e, 0x567f, 0xc12e, 0x21, 0 + .dw 0x56c0, 0xc12e, 0x56ff, 0xc12e, 0x21, 0 + .dw 0x5740, 0xc12e, 0x577f, 0xc12e, 0x21, 0 + .dw 0x57c0, 0xc12e, 0x57ff, 0xc12e, 0x21, 0 + .dw 0x5840, 0xc12e, 0x587f, 0xc12e, 0x21, 0 + .dw 0x58c0, 0xc12e, 0x58ff, 0xc12e, 0x21, 0 + .dw 0x5940, 0xc12e, 0x597f, 0xc12e, 0x21, 0 + .dw 0x59c0, 0xc12e, 0x5fff, 0xc12e, 0x21, 0 + .dw 0x6040, 0xc12e, 0x607f, 0xc12e, 0x21, 0 + .dw 0x60c0, 0xc12e, 0x60ff, 0xc12e, 0x21, 0 + .dw 0x6140, 0xc12e, 0x617f, 0xc12e, 0x21, 0 + .dw 0x61c0, 0xc12e, 0x61ff, 0xc12e, 0x21, 0 + .dw 0x6240, 0xc12e, 0x627f, 0xc12e, 0x21, 0 + .dw 0x62c0, 0xc12e, 0x62ff, 0xc12e, 0x21, 0 + .dw 0x6340, 0xc12e, 0x637f, 0xc12e, 0x21, 0 + .dw 0x63c0, 0xc12e, 0x63ff, 0xc12e, 0x21, 0 + .dw 0x6440, 0xc12e, 0x647f, 0xc12e, 0x21, 0 + .dw 0x64c0, 0xc12e, 0x64ff, 0xc12e, 0x21, 0 + .dw 0x6540, 0xc12e, 0x657f, 0xc12e, 0x21, 0 + .dw 0x65c0, 0xc12e, 0x65ff, 0xc12e, 0x21, 0 + .dw 0x6640, 0xc12e, 0x667f, 0xc12e, 0x21, 0 + .dw 0x66c0, 0xc12e, 0x66ff, 0xc12e, 0x21, 0 + .dw 0x6740, 0xc12e, 0x677f, 0xc12e, 0x21, 0 + .dw 0x67c0, 0xc12e, 0x67ff, 0xc12e, 0x21, 0 + .dw 0x6840, 0xc12e, 0x687f, 0xc12e, 0x21, 0 + .dw 0x68c0, 0xc12e, 0x68ff, 0xc12e, 0x21, 0 + .dw 0x6940, 0xc12e, 0x697f, 0xc12e, 0x21, 0 + .dw 0x69c0, 0xc12e, 0x69ff, 0xc12e, 0x21, 0 + .dw 0x6a40, 0xc12e, 0x6a7f, 0xc12e, 0x21, 0 + .dw 0x6ac0, 0xc12e, 0x6aff, 0xc12e, 0x21, 0 + .dw 0x6b40, 0xc12e, 0x6b7f, 0xc12e, 0x21, 0 + .dw 0x6bc0, 0xc12e, 0x6bff, 0xc12e, 0x21, 0 + .dw 0x6c40, 0xc12e, 0x6c7f, 0xc12e, 0x21, 0 + .dw 0x6cc0, 0xc12e, 0x6cff, 0xc12e, 0x21, 0 + .dw 0x6d40, 0xc12e, 0x6d7f, 0xc12e, 0x21, 0 + .dw 0x6dc0, 0xc12e, 0x6dff, 0xc12e, 0x21, 0 + .dw 0x6e40, 0xc12e, 0x6e7f, 0xc12e, 0x21, 0 + .dw 0x6ec0, 0xc12e, 0x6eff, 0xc12e, 0x21, 0 + .dw 0x6f40, 0xc12e, 0x6f7f, 0xc12e, 0x21, 0 + .dw 0x6fc0, 0xc12e, 0x6fff, 0xc12e, 0x21, 0 + .dw 0x7040, 0xc12e, 0x707f, 0xc12e, 0x21, 0 + .dw 0x70c0, 0xc12e, 0x70ff, 0xc12e, 0x21, 0 + .dw 0x7140, 0xc12e, 0x717f, 0xc12e, 0x21, 0 + .dw 0x71c0, 0xc12e, 0x71ff, 0xc12e, 0x21, 0 + .dw 0x7240, 0xc12e, 0x727f, 0xc12e, 0x21, 0 + .dw 0x72c0, 0xc12e, 0x72ff, 0xc12e, 0x21, 0 + .dw 0x7340, 0xc12e, 0x737f, 0xc12e, 0x21, 0 + .dw 0x73c0, 0xc12e, 0x73ff, 0xc12e, 0x21, 0 + .dw 0x7440, 0xc12e, 0x747f, 0xc12e, 0x21, 0 + .dw 0x74c0, 0xc12e, 0x74ff, 0xc12e, 0x21, 0 + .dw 0x7540, 0xc12e, 0x757f, 0xc12e, 0x21, 0 + .dw 0x75c0, 0xc12e, 0x75ff, 0xc12e, 0x21, 0 + .dw 0x7640, 0xc12e, 0x767f, 0xc12e, 0x21, 0 + .dw 0x76c0, 0xc12e, 0x76ff, 0xc12e, 0x21, 0 + .dw 0x7740, 0xc12e, 0x777f, 0xc12e, 0x21, 0 + .dw 0x77c0, 0xc12e, 0x77ff, 0xc12e, 0x21, 0 + .dw 0x7840, 0xc12e, 0x787f, 0xc12e, 0x21, 0 + .dw 0x78c0, 0xc12e, 0x78ff, 0xc12e, 0x21, 0 + .dw 0x7940, 0xc12e, 0x797f, 0xc12e, 0x21, 0 + .dw 0x79c0, 0xc12e, 0x7fff, 0xc12e, 0x21, 0 + .dw 0x8040, 0xc12e, 0x807f, 0xc12e, 0x21, 0 + .dw 0x80c0, 0xc12e, 0x80ff, 0xc12e, 0x21, 0 + .dw 0x8140, 0xc12e, 0x817f, 0xc12e, 0x21, 0 + .dw 0x81c0, 0xc12e, 0x81ff, 0xc12e, 0x21, 0 + .dw 0x8240, 0xc12e, 0x827f, 0xc12e, 0x21, 0 + .dw 0x82c0, 0xc12e, 0x82ff, 0xc12e, 0x21, 0 + .dw 0x8340, 0xc12e, 0x837f, 0xc12e, 0x21, 0 + .dw 0x83c0, 0xc12e, 0x83ff, 0xc12e, 0x21, 0 + .dw 0x8440, 0xc12e, 0x847f, 0xc12e, 0x21, 0 + .dw 0x84c0, 0xc12e, 0x84ff, 0xc12e, 0x21, 0 + .dw 0x8540, 0xc12e, 0x857f, 0xc12e, 0x21, 0 + .dw 0x85c0, 0xc12e, 0x85ff, 0xc12e, 0x21, 0 + .dw 0x8640, 0xc12e, 0x867f, 0xc12e, 0x21, 0 + .dw 0x86c0, 0xc12e, 0x86ff, 0xc12e, 0x21, 0 + .dw 0x8740, 0xc12e, 0x877f, 0xc12e, 0x21, 0 + .dw 0x87c0, 0xc12e, 0x87ff, 0xc12e, 0x21, 0 + .dw 0x8840, 0xc12e, 0x887f, 0xc12e, 0x21, 0 + .dw 0x88c0, 0xc12e, 0x88ff, 0xc12e, 0x21, 0 + .dw 0x8940, 0xc12e, 0x897f, 0xc12e, 0x21, 0 + .dw 0x89c0, 0xc12e, 0x89ff, 0xc12e, 0x21, 0 + .dw 0x8a40, 0xc12e, 0x8a7f, 0xc12e, 0x21, 0 + .dw 0x8ac0, 0xc12e, 0x8aff, 0xc12e, 0x21, 0 + .dw 0x8b40, 0xc12e, 0x8b7f, 0xc12e, 0x21, 0 + .dw 0x8bc0, 0xc12e, 0x8bff, 0xc12e, 0x21, 0 + .dw 0x8c40, 0xc12e, 0x8c7f, 0xc12e, 0x21, 0 + .dw 0x8cc0, 0xc12e, 0x8cff, 0xc12e, 0x21, 0 + .dw 0x8d40, 0xc12e, 0x8d7f, 0xc12e, 0x21, 0 + .dw 0x8dc0, 0xc12e, 0x8dff, 0xc12e, 0x21, 0 + .dw 0x8e40, 0xc12e, 0x8e7f, 0xc12e, 0x21, 0 + .dw 0x8ec0, 0xc12e, 0x8eff, 0xc12e, 0x21, 0 + .dw 0x8f40, 0xc12e, 0x8f7f, 0xc12e, 0x21, 0 + .dw 0x8fc0, 0xc12e, 0x8fff, 0xc12e, 0x21, 0 + .dw 0x9040, 0xc12e, 0x907f, 0xc12e, 0x21, 0 + .dw 0x90c0, 0xc12e, 0x90ff, 0xc12e, 0x21, 0 + .dw 0x9140, 0xc12e, 0x917f, 0xc12e, 0x21, 0 + .dw 0x91c0, 0xc12e, 0x91ff, 0xc12e, 0x21, 0 + .dw 0x9240, 0xc12e, 0x927f, 0xc12e, 0x21, 0 + .dw 0x92c0, 0xc12e, 0x92ff, 0xc12e, 0x21, 0 + .dw 0x9340, 0xc12e, 0x937f, 0xc12e, 0x21, 0 + .dw 0x93c0, 0xc12e, 0x93ff, 0xc12e, 0x21, 0 + .dw 0x9440, 0xc12e, 0x947f, 0xc12e, 0x21, 0 + .dw 0x94c0, 0xc12e, 0x94ff, 0xc12e, 0x21, 0 + .dw 0x9540, 0xc12e, 0x957f, 0xc12e, 0x21, 0 + .dw 0x95c0, 0xc12e, 0x95ff, 0xc12e, 0x21, 0 + .dw 0x9640, 0xc12e, 0x967f, 0xc12e, 0x21, 0 + .dw 0x96c0, 0xc12e, 0x96ff, 0xc12e, 0x21, 0 + .dw 0x9740, 0xc12e, 0x977f, 0xc12e, 0x21, 0 + .dw 0x97c0, 0xc12e, 0x97ff, 0xc12e, 0x21, 0 + .dw 0x9840, 0xc12e, 0x987f, 0xc12e, 0x21, 0 + .dw 0x98c0, 0xc12e, 0x98ff, 0xc12e, 0x21, 0 + .dw 0x9940, 0xc12e, 0x997f, 0xc12e, 0x21, 0 + .dw 0x99c0, 0xc12e, 0x9fff, 0xc12e, 0x21, 0 + .dw 0xa040, 0xc12e, 0xa07f, 0xc12e, 0x21, 0 + .dw 0xa0c0, 0xc12e, 0xa0ff, 0xc12e, 0x21, 0 + .dw 0xa140, 0xc12e, 0xa17f, 0xc12e, 0x21, 0 + .dw 0xa1c0, 0xc12e, 0xa1ff, 0xc12e, 0x21, 0 + .dw 0xa240, 0xc12e, 0xa27f, 0xc12e, 0x21, 0 + .dw 0xa2c0, 0xc12e, 0xa2ff, 0xc12e, 0x21, 0 + .dw 0xa340, 0xc12e, 0xa37f, 0xc12e, 0x21, 0 + .dw 0xa3c0, 0xc12e, 0xa3ff, 0xc12e, 0x21, 0 + .dw 0xa440, 0xc12e, 0xa47f, 0xc12e, 0x21, 0 + .dw 0xa4c0, 0xc12e, 0xa4ff, 0xc12e, 0x21, 0 + .dw 0xa540, 0xc12e, 0xa57f, 0xc12e, 0x21, 0 + .dw 0xa5c0, 0xc12e, 0xa5ff, 0xc12e, 0x21, 0 + .dw 0xa640, 0xc12e, 0xa67f, 0xc12e, 0x21, 0 + .dw 0xa6c0, 0xc12e, 0xa6ff, 0xc12e, 0x21, 0 + .dw 0xa740, 0xc12e, 0xa77f, 0xc12e, 0x21, 0 + .dw 0xa7c0, 0xc12e, 0xa7ff, 0xc12e, 0x21, 0 + .dw 0xa840, 0xc12e, 0xa87f, 0xc12e, 0x21, 0 + .dw 0xa8c0, 0xc12e, 0xa8ff, 0xc12e, 0x21, 0 + .dw 0xa940, 0xc12e, 0xa97f, 0xc12e, 0x21, 0 + .dw 0xa9c0, 0xc12e, 0xa9ff, 0xc12e, 0x21, 0 + .dw 0xaa40, 0xc12e, 0xaa7f, 0xc12e, 0x21, 0 + .dw 0xaac0, 0xc12e, 0xaaff, 0xc12e, 0x21, 0 + .dw 0xab40, 0xc12e, 0xab7f, 0xc12e, 0x21, 0 + .dw 0xabc0, 0xc12e, 0xabff, 0xc12e, 0x21, 0 + .dw 0xac40, 0xc12e, 0xac7f, 0xc12e, 0x21, 0 + .dw 0xacc0, 0xc12e, 0xacff, 0xc12e, 0x21, 0 + .dw 0xad40, 0xc12e, 0xad7f, 0xc12e, 0x21, 0 + .dw 0xadc0, 0xc12e, 0xadff, 0xc12e, 0x21, 0 + .dw 0xae40, 0xc12e, 0xae7f, 0xc12e, 0x21, 0 + .dw 0xaec0, 0xc12e, 0xaeff, 0xc12e, 0x21, 0 + .dw 0xaf40, 0xc12e, 0xaf7f, 0xc12e, 0x21, 0 + .dw 0xafc0, 0xc12e, 0xafff, 0xc12e, 0x21, 0 + .dw 0xb040, 0xc12e, 0xb07f, 0xc12e, 0x21, 0 + .dw 0xb0c0, 0xc12e, 0xb0ff, 0xc12e, 0x21, 0 + .dw 0xb140, 0xc12e, 0xb17f, 0xc12e, 0x21, 0 + .dw 0xb1c0, 0xc12e, 0xb1ff, 0xc12e, 0x21, 0 + .dw 0xb240, 0xc12e, 0xb27f, 0xc12e, 0x21, 0 + .dw 0xb2c0, 0xc12e, 0xb2ff, 0xc12e, 0x21, 0 + .dw 0xb340, 0xc12e, 0xb37f, 0xc12e, 0x21, 0 + .dw 0xb3c0, 0xc12e, 0xb3ff, 0xc12e, 0x21, 0 + .dw 0xb440, 0xc12e, 0xb47f, 0xc12e, 0x21, 0 + .dw 0xb4c0, 0xc12e, 0xb4ff, 0xc12e, 0x21, 0 + .dw 0xb540, 0xc12e, 0xb57f, 0xc12e, 0x21, 0 + .dw 0xb5c0, 0xc12e, 0xb5ff, 0xc12e, 0x21, 0 + .dw 0xb640, 0xc12e, 0xb67f, 0xc12e, 0x21, 0 + .dw 0xb6c0, 0xc12e, 0xb6ff, 0xc12e, 0x21, 0 + .dw 0xb740, 0xc12e, 0xb77f, 0xc12e, 0x21, 0 + .dw 0xb7c0, 0xc12e, 0xb7ff, 0xc12e, 0x21, 0 + .dw 0xb840, 0xc12e, 0xb87f, 0xc12e, 0x21, 0 + .dw 0xb8c0, 0xc12e, 0xb8ff, 0xc12e, 0x21, 0 + .dw 0xb940, 0xc12e, 0xb97f, 0xc12e, 0x21, 0 + .dw 0xb9c0, 0xc12e, 0xbfff, 0xc12e, 0x21, 0 + .dw 0xc040, 0xc12e, 0xc07f, 0xc12e, 0x21, 0 + .dw 0xc0c0, 0xc12e, 0xc0ff, 0xc12e, 0x21, 0 + .dw 0xc140, 0xc12e, 0xc17f, 0xc12e, 0x21, 0 + .dw 0xc1c0, 0xc12e, 0xc1ff, 0xc12e, 0x21, 0 + .dw 0xc240, 0xc12e, 0xc27f, 0xc12e, 0x21, 0 + .dw 0xc2c0, 0xc12e, 0xc2ff, 0xc12e, 0x21, 0 + .dw 0xc340, 0xc12e, 0xc37f, 0xc12e, 0x21, 0 + .dw 0xc3c0, 0xc12e, 0xc3ff, 0xc12e, 0x21, 0 + .dw 0xc440, 0xc12e, 0xc47f, 0xc12e, 0x21, 0 + .dw 0xc4c0, 0xc12e, 0xc4ff, 0xc12e, 0x21, 0 + .dw 0xc540, 0xc12e, 0xc57f, 0xc12e, 0x21, 0 + .dw 0xc5c0, 0xc12e, 0xc5ff, 0xc12e, 0x21, 0 + .dw 0xc640, 0xc12e, 0xc67f, 0xc12e, 0x21, 0 + .dw 0xc6c0, 0xc12e, 0xc6ff, 0xc12e, 0x21, 0 + .dw 0xc740, 0xc12e, 0xc77f, 0xc12e, 0x21, 0 + .dw 0xc7c0, 0xc12e, 0xc7ff, 0xc12e, 0x21, 0 + .dw 0xc840, 0xc12e, 0xc87f, 0xc12e, 0x21, 0 + .dw 0xc8c0, 0xc12e, 0xc8ff, 0xc12e, 0x21, 0 + .dw 0xc940, 0xc12e, 0xc97f, 0xc12e, 0x21, 0 + .dw 0xc9c0, 0xc12e, 0xc9ff, 0xc12e, 0x21, 0 + .dw 0xca40, 0xc12e, 0xca7f, 0xc12e, 0x21, 0 + .dw 0xcac0, 0xc12e, 0xcaff, 0xc12e, 0x21, 0 + .dw 0xcb40, 0xc12e, 0xcb7f, 0xc12e, 0x21, 0 + .dw 0xcbc0, 0xc12e, 0xcbff, 0xc12e, 0x21, 0 + .dw 0xcc40, 0xc12e, 0xcc7f, 0xc12e, 0x21, 0 + .dw 0xccc0, 0xc12e, 0xccff, 0xc12e, 0x21, 0 + .dw 0xcd40, 0xc12e, 0xcd7f, 0xc12e, 0x21, 0 + .dw 0xcdc0, 0xc12e, 0xcdff, 0xc12e, 0x21, 0 + .dw 0xce40, 0xc12e, 0xce7f, 0xc12e, 0x21, 0 + .dw 0xcec0, 0xc12e, 0xceff, 0xc12e, 0x21, 0 + .dw 0xcf40, 0xc12e, 0xcf7f, 0xc12e, 0x21, 0 + .dw 0xcfc0, 0xc12e, 0xcfff, 0xc12e, 0x21, 0 + .dw 0xd040, 0xc12e, 0xd07f, 0xc12e, 0x21, 0 + .dw 0xd0c0, 0xc12e, 0xd0ff, 0xc12e, 0x21, 0 + .dw 0xd140, 0xc12e, 0xd17f, 0xc12e, 0x21, 0 + .dw 0xd1c0, 0xc12e, 0xd1ff, 0xc12e, 0x21, 0 + .dw 0xd240, 0xc12e, 0xd27f, 0xc12e, 0x21, 0 + .dw 0xd2c0, 0xc12e, 0xd2ff, 0xc12e, 0x21, 0 + .dw 0xd340, 0xc12e, 0xd37f, 0xc12e, 0x21, 0 + .dw 0xd3c0, 0xc12e, 0xd3ff, 0xc12e, 0x21, 0 + .dw 0xd440, 0xc12e, 0xd47f, 0xc12e, 0x21, 0 + .dw 0xd4c0, 0xc12e, 0xd4ff, 0xc12e, 0x21, 0 + .dw 0xd540, 0xc12e, 0xd57f, 0xc12e, 0x21, 0 + .dw 0xd5c0, 0xc12e, 0xd5ff, 0xc12e, 0x21, 0 + .dw 0xd640, 0xc12e, 0xd67f, 0xc12e, 0x21, 0 + .dw 0xd6c0, 0xc12e, 0xd6ff, 0xc12e, 0x21, 0 + .dw 0xd740, 0xc12e, 0xd77f, 0xc12e, 0x21, 0 + .dw 0xd7c0, 0xc12e, 0xd7ff, 0xc12e, 0x21, 0 + .dw 0xd840, 0xc12e, 0xd87f, 0xc12e, 0x21, 0 + .dw 0xd8c0, 0xc12e, 0xd8ff, 0xc12e, 0x21, 0 + .dw 0xd940, 0xc12e, 0xd97f, 0xc12e, 0x21, 0 + .dw 0xd9c0, 0xc12e, 0xdfff, 0xc12e, 0x21, 0 + .dw 0xe040, 0xc12e, 0xe07f, 0xc12e, 0x21, 0 + .dw 0xe0c0, 0xc12e, 0xe0ff, 0xc12e, 0x21, 0 + .dw 0xe140, 0xc12e, 0xe17f, 0xc12e, 0x21, 0 + .dw 0xe1c0, 0xc12e, 0xe1ff, 0xc12e, 0x21, 0 + .dw 0xe240, 0xc12e, 0xe27f, 0xc12e, 0x21, 0 + .dw 0xe2c0, 0xc12e, 0xe2ff, 0xc12e, 0x21, 0 + .dw 0xe340, 0xc12e, 0xe37f, 0xc12e, 0x21, 0 + .dw 0xe3c0, 0xc12e, 0xe3ff, 0xc12e, 0x21, 0 + .dw 0xe440, 0xc12e, 0xe47f, 0xc12e, 0x21, 0 + .dw 0xe4c0, 0xc12e, 0xe4ff, 0xc12e, 0x21, 0 + .dw 0xe540, 0xc12e, 0xe57f, 0xc12e, 0x21, 0 + .dw 0xe5c0, 0xc12e, 0xe5ff, 0xc12e, 0x21, 0 + .dw 0xe640, 0xc12e, 0xe67f, 0xc12e, 0x21, 0 + .dw 0xe6c0, 0xc12e, 0xe6ff, 0xc12e, 0x21, 0 + .dw 0xe740, 0xc12e, 0xe77f, 0xc12e, 0x21, 0 + .dw 0xe7c0, 0xc12e, 0xe7ff, 0xc12e, 0x21, 0 + .dw 0xe840, 0xc12e, 0xe87f, 0xc12e, 0x21, 0 + .dw 0xe8c0, 0xc12e, 0xe8ff, 0xc12e, 0x21, 0 + .dw 0xe940, 0xc12e, 0xe97f, 0xc12e, 0x21, 0 + .dw 0xe9c0, 0xc12e, 0xe9ff, 0xc12e, 0x21, 0 + .dw 0xea40, 0xc12e, 0xea7f, 0xc12e, 0x21, 0 + .dw 0xeac0, 0xc12e, 0xeaff, 0xc12e, 0x21, 0 + .dw 0xeb40, 0xc12e, 0xeb7f, 0xc12e, 0x21, 0 + .dw 0xebc0, 0xc12e, 0xebff, 0xc12e, 0x21, 0 + .dw 0xec40, 0xc12e, 0xec7f, 0xc12e, 0x21, 0 + .dw 0xecc0, 0xc12e, 0xecff, 0xc12e, 0x21, 0 + .dw 0xed40, 0xc12e, 0xed7f, 0xc12e, 0x21, 0 + .dw 0xedc0, 0xc12e, 0xedff, 0xc12e, 0x21, 0 + .dw 0xee40, 0xc12e, 0xee7f, 0xc12e, 0x21, 0 + .dw 0xeec0, 0xc12e, 0xeeff, 0xc12e, 0x21, 0 + .dw 0xef40, 0xc12e, 0xef7f, 0xc12e, 0x21, 0 + .dw 0xefc0, 0xc12e, 0xefff, 0xc12e, 0x21, 0 + .dw 0xf040, 0xc12e, 0xf07f, 0xc12e, 0x21, 0 + .dw 0xf0c0, 0xc12e, 0xf0ff, 0xc12e, 0x21, 0 + .dw 0xf140, 0xc12e, 0xf17f, 0xc12e, 0x21, 0 + .dw 0xf1c0, 0xc12e, 0xf1ff, 0xc12e, 0x21, 0 + .dw 0xf240, 0xc12e, 0xf27f, 0xc12e, 0x21, 0 + .dw 0xf2c0, 0xc12e, 0xf2ff, 0xc12e, 0x21, 0 + .dw 0xf340, 0xc12e, 0xf37f, 0xc12e, 0x21, 0 + .dw 0xf3c0, 0xc12e, 0xf3ff, 0xc12e, 0x21, 0 + .dw 0xf440, 0xc12e, 0xf47f, 0xc12e, 0x21, 0 + .dw 0xf4c0, 0xc12e, 0xf4ff, 0xc12e, 0x21, 0 + .dw 0xf540, 0xc12e, 0xf57f, 0xc12e, 0x21, 0 + .dw 0xf5c0, 0xc12e, 0xf5ff, 0xc12e, 0x21, 0 + .dw 0xf640, 0xc12e, 0xf67f, 0xc12e, 0x21, 0 + .dw 0xf6c0, 0xc12e, 0xf6ff, 0xc12e, 0x21, 0 + .dw 0xf740, 0xc12e, 0xf77f, 0xc12e, 0x21, 0 + .dw 0xf7c0, 0xc12e, 0xf7ff, 0xc12e, 0x21, 0 + .dw 0xf840, 0xc12e, 0xf87f, 0xc12e, 0x21, 0 + .dw 0xf8c0, 0xc12e, 0xf8ff, 0xc12e, 0x21, 0 + .dw 0xf940, 0xc12e, 0xf97f, 0xc12e, 0x21, 0 + .dw 0xf9c0, 0xc12e, 0xffff, 0xc12e, 0x21, 0 + .dw 0x0040, 0xc12f, 0x007f, 0xc12f, 0x21, 0 + .dw 0x00c0, 0xc12f, 0x00ff, 0xc12f, 0x21, 0 + .dw 0x0140, 0xc12f, 0x017f, 0xc12f, 0x21, 0 + .dw 0x01c0, 0xc12f, 0x01ff, 0xc12f, 0x21, 0 + .dw 0x0240, 0xc12f, 0x027f, 0xc12f, 0x21, 0 + .dw 0x02c0, 0xc12f, 0x02ff, 0xc12f, 0x21, 0 + .dw 0x0340, 0xc12f, 0x037f, 0xc12f, 0x21, 0 + .dw 0x03c0, 0xc12f, 0x03ff, 0xc12f, 0x21, 0 + .dw 0x0440, 0xc12f, 0x047f, 0xc12f, 0x21, 0 + .dw 0x04c0, 0xc12f, 0x04ff, 0xc12f, 0x21, 0 + .dw 0x0540, 0xc12f, 0x057f, 0xc12f, 0x21, 0 + .dw 0x05c0, 0xc12f, 0x05ff, 0xc12f, 0x21, 0 + .dw 0x0640, 0xc12f, 0x067f, 0xc12f, 0x21, 0 + .dw 0x06c0, 0xc12f, 0x06ff, 0xc12f, 0x21, 0 + .dw 0x0740, 0xc12f, 0x077f, 0xc12f, 0x21, 0 + .dw 0x07c0, 0xc12f, 0x07ff, 0xc12f, 0x21, 0 + .dw 0x0840, 0xc12f, 0x087f, 0xc12f, 0x21, 0 + .dw 0x08c0, 0xc12f, 0x08ff, 0xc12f, 0x21, 0 + .dw 0x0940, 0xc12f, 0x097f, 0xc12f, 0x21, 0 + .dw 0x09c0, 0xc12f, 0x09ff, 0xc12f, 0x21, 0 + .dw 0x0a40, 0xc12f, 0x0a7f, 0xc12f, 0x21, 0 + .dw 0x0ac0, 0xc12f, 0x0aff, 0xc12f, 0x21, 0 + .dw 0x0b40, 0xc12f, 0x0b7f, 0xc12f, 0x21, 0 + .dw 0x0bc0, 0xc12f, 0x0bff, 0xc12f, 0x21, 0 + .dw 0x0c40, 0xc12f, 0x0c7f, 0xc12f, 0x21, 0 + .dw 0x0cc0, 0xc12f, 0x0cff, 0xc12f, 0x21, 0 + .dw 0x0d40, 0xc12f, 0x0d7f, 0xc12f, 0x21, 0 + .dw 0x0dc0, 0xc12f, 0x0dff, 0xc12f, 0x21, 0 + .dw 0x0e40, 0xc12f, 0x0e7f, 0xc12f, 0x21, 0 + .dw 0x0ec0, 0xc12f, 0x0eff, 0xc12f, 0x21, 0 + .dw 0x0f40, 0xc12f, 0x0f7f, 0xc12f, 0x21, 0 + .dw 0x0fc0, 0xc12f, 0x0fff, 0xc12f, 0x21, 0 + .dw 0x1040, 0xc12f, 0x107f, 0xc12f, 0x21, 0 + .dw 0x10c0, 0xc12f, 0x10ff, 0xc12f, 0x21, 0 + .dw 0x1140, 0xc12f, 0x117f, 0xc12f, 0x21, 0 + .dw 0x11c0, 0xc12f, 0x11ff, 0xc12f, 0x21, 0 + .dw 0x1240, 0xc12f, 0x127f, 0xc12f, 0x21, 0 + .dw 0x12c0, 0xc12f, 0x12ff, 0xc12f, 0x21, 0 + .dw 0x1340, 0xc12f, 0x137f, 0xc12f, 0x21, 0 + .dw 0x13c0, 0xc12f, 0x13ff, 0xc12f, 0x21, 0 + .dw 0x1440, 0xc12f, 0x147f, 0xc12f, 0x21, 0 + .dw 0x14c0, 0xc12f, 0x14ff, 0xc12f, 0x21, 0 + .dw 0x1540, 0xc12f, 0x157f, 0xc12f, 0x21, 0 + .dw 0x15c0, 0xc12f, 0x15ff, 0xc12f, 0x21, 0 + .dw 0x1640, 0xc12f, 0x167f, 0xc12f, 0x21, 0 + .dw 0x16c0, 0xc12f, 0x16ff, 0xc12f, 0x21, 0 + .dw 0x1740, 0xc12f, 0x177f, 0xc12f, 0x21, 0 + .dw 0x17c0, 0xc12f, 0x17ff, 0xc12f, 0x21, 0 + .dw 0x1840, 0xc12f, 0x187f, 0xc12f, 0x21, 0 + .dw 0x18c0, 0xc12f, 0x18ff, 0xc12f, 0x21, 0 + .dw 0x1940, 0xc12f, 0x197f, 0xc12f, 0x21, 0 + .dw 0x19c0, 0xc12f, 0x1fff, 0xc12f, 0x21, 0 + .dw 0x2040, 0xc12f, 0x207f, 0xc12f, 0x21, 0 + .dw 0x20c0, 0xc12f, 0x20ff, 0xc12f, 0x21, 0 + .dw 0x2140, 0xc12f, 0x217f, 0xc12f, 0x21, 0 + .dw 0x21c0, 0xc12f, 0x21ff, 0xc12f, 0x21, 0 + .dw 0x2240, 0xc12f, 0x227f, 0xc12f, 0x21, 0 + .dw 0x22c0, 0xc12f, 0x22ff, 0xc12f, 0x21, 0 + .dw 0x2340, 0xc12f, 0x237f, 0xc12f, 0x21, 0 + .dw 0x23c0, 0xc12f, 0x23ff, 0xc12f, 0x21, 0 + .dw 0x2440, 0xc12f, 0x247f, 0xc12f, 0x21, 0 + .dw 0x24c0, 0xc12f, 0x24ff, 0xc12f, 0x21, 0 + .dw 0x2540, 0xc12f, 0x257f, 0xc12f, 0x21, 0 + .dw 0x25c0, 0xc12f, 0x25ff, 0xc12f, 0x21, 0 + .dw 0x2640, 0xc12f, 0x267f, 0xc12f, 0x21, 0 + .dw 0x26c0, 0xc12f, 0x26ff, 0xc12f, 0x21, 0 + .dw 0x2740, 0xc12f, 0x277f, 0xc12f, 0x21, 0 + .dw 0x27c0, 0xc12f, 0x27ff, 0xc12f, 0x21, 0 + .dw 0x2840, 0xc12f, 0x287f, 0xc12f, 0x21, 0 + .dw 0x28c0, 0xc12f, 0x28ff, 0xc12f, 0x21, 0 + .dw 0x2940, 0xc12f, 0x297f, 0xc12f, 0x21, 0 + .dw 0x29c0, 0xc12f, 0x29ff, 0xc12f, 0x21, 0 + .dw 0x2a40, 0xc12f, 0x2a7f, 0xc12f, 0x21, 0 + .dw 0x2ac0, 0xc12f, 0x2aff, 0xc12f, 0x21, 0 + .dw 0x2b40, 0xc12f, 0x2b7f, 0xc12f, 0x21, 0 + .dw 0x2bc0, 0xc12f, 0x2bff, 0xc12f, 0x21, 0 + .dw 0x2c40, 0xc12f, 0x2c7f, 0xc12f, 0x21, 0 + .dw 0x2cc0, 0xc12f, 0x2cff, 0xc12f, 0x21, 0 + .dw 0x2d40, 0xc12f, 0x2d7f, 0xc12f, 0x21, 0 + .dw 0x2dc0, 0xc12f, 0x2dff, 0xc12f, 0x21, 0 + .dw 0x2e40, 0xc12f, 0x2e7f, 0xc12f, 0x21, 0 + .dw 0x2ec0, 0xc12f, 0x2eff, 0xc12f, 0x21, 0 + .dw 0x2f40, 0xc12f, 0x2f7f, 0xc12f, 0x21, 0 + .dw 0x2fc0, 0xc12f, 0x2fff, 0xc12f, 0x21, 0 + .dw 0x3040, 0xc12f, 0x307f, 0xc12f, 0x21, 0 + .dw 0x30c0, 0xc12f, 0x30ff, 0xc12f, 0x21, 0 + .dw 0x3140, 0xc12f, 0x317f, 0xc12f, 0x21, 0 + .dw 0x31c0, 0xc12f, 0x31ff, 0xc12f, 0x21, 0 + .dw 0x3240, 0xc12f, 0x327f, 0xc12f, 0x21, 0 + .dw 0x32c0, 0xc12f, 0x32ff, 0xc12f, 0x21, 0 + .dw 0x3340, 0xc12f, 0x337f, 0xc12f, 0x21, 0 + .dw 0x33c0, 0xc12f, 0x33ff, 0xc12f, 0x21, 0 + .dw 0x3440, 0xc12f, 0x347f, 0xc12f, 0x21, 0 + .dw 0x34c0, 0xc12f, 0x34ff, 0xc12f, 0x21, 0 + .dw 0x3540, 0xc12f, 0x357f, 0xc12f, 0x21, 0 + .dw 0x35c0, 0xc12f, 0x35ff, 0xc12f, 0x21, 0 + .dw 0x3640, 0xc12f, 0x367f, 0xc12f, 0x21, 0 + .dw 0x36c0, 0xc12f, 0x36ff, 0xc12f, 0x21, 0 + .dw 0x3740, 0xc12f, 0x377f, 0xc12f, 0x21, 0 + .dw 0x37c0, 0xc12f, 0x37ff, 0xc12f, 0x21, 0 + .dw 0x3840, 0xc12f, 0x387f, 0xc12f, 0x21, 0 + .dw 0x38c0, 0xc12f, 0x38ff, 0xc12f, 0x21, 0 + .dw 0x3940, 0xc12f, 0x397f, 0xc12f, 0x21, 0 + .dw 0x39c0, 0xc12f, 0x1fff, 0xc130, 0x21, 0 + .dw 0x3a00, 0xc130, 0x5fff, 0xc130, 0x21, 0 + .dw 0x7a00, 0xc130, 0x9fff, 0xc130, 0x21, 0 + .dw 0xba00, 0xc130, 0xdfff, 0xc130, 0x21, 0 + .dw 0xfa00, 0xc130, 0x1fff, 0xc131, 0x21, 0 + .dw 0x3a00, 0xc131, 0x5fff, 0xc131, 0x21, 0 + .dw 0x7a00, 0xc131, 0x9fff, 0xc131, 0x21, 0 + .dw 0xba00, 0xc131, 0xdfff, 0xc131, 0x21, 0 + .dw 0xfa00, 0xc131, 0x1fff, 0xc132, 0x21, 0 + .dw 0x3a00, 0xc132, 0x5fff, 0xc132, 0x21, 0 + .dw 0x7a00, 0xc132, 0x9fff, 0xc132, 0x21, 0 + .dw 0xba00, 0xc132, 0xdfff, 0xc132, 0x21, 0 + .dw 0xfa00, 0xc132, 0xffff, 0xc133, 0x21, 0 + .dw 0x1a00, 0xc134, 0x1fff, 0xc134, 0x21, 0 + .dw 0x3a00, 0xc134, 0x3fff, 0xc134, 0x21, 0 + .dw 0x5a00, 0xc134, 0x5fff, 0xc134, 0x21, 0 + .dw 0x7a00, 0xc134, 0x7fff, 0xc134, 0x21, 0 + .dw 0x9a00, 0xc134, 0x9fff, 0xc134, 0x21, 0 + .dw 0xba00, 0xc134, 0xbfff, 0xc134, 0x21, 0 + .dw 0xda00, 0xc134, 0xdfff, 0xc134, 0x21, 0 + .dw 0xfa00, 0xc134, 0xffff, 0xc134, 0x21, 0 + .dw 0x1a00, 0xc135, 0x1fff, 0xc135, 0x21, 0 + .dw 0x3a00, 0xc135, 0x3fff, 0xc135, 0x21, 0 + .dw 0x5a00, 0xc135, 0x5fff, 0xc135, 0x21, 0 + .dw 0x7a00, 0xc135, 0x7fff, 0xc135, 0x21, 0 + .dw 0x9a00, 0xc135, 0x9fff, 0xc135, 0x21, 0 + .dw 0xba00, 0xc135, 0xbfff, 0xc135, 0x21, 0 + .dw 0xda00, 0xc135, 0xdfff, 0xc135, 0x21, 0 + .dw 0xfa00, 0xc135, 0xffff, 0xc135, 0x21, 0 + .dw 0x1a00, 0xc136, 0x1fff, 0xc136, 0x21, 0 + .dw 0x3a00, 0xc136, 0x3fff, 0xc136, 0x21, 0 + .dw 0x5a00, 0xc136, 0x5fff, 0xc136, 0x21, 0 + .dw 0x7a00, 0xc136, 0x7fff, 0xc136, 0x21, 0 + .dw 0x9a00, 0xc136, 0x9fff, 0xc136, 0x21, 0 + .dw 0xba00, 0xc136, 0xbfff, 0xc136, 0x21, 0 + .dw 0xda00, 0xc136, 0xdfff, 0xc136, 0x21, 0 + .dw 0xfa00, 0xc136, 0xffff, 0xc136, 0x21, 0 + .dw 0x1a00, 0xc137, 0x1fff, 0xc137, 0x21, 0 + .dw 0x3a00, 0xc137, 0x1fff, 0xc138, 0x21, 0 + .dw 0x2040, 0xc138, 0x207f, 0xc138, 0x21, 0 + .dw 0x20c0, 0xc138, 0x20ff, 0xc138, 0x21, 0 + .dw 0x2140, 0xc138, 0x217f, 0xc138, 0x21, 0 + .dw 0x21c0, 0xc138, 0x21ff, 0xc138, 0x21, 0 + .dw 0x2240, 0xc138, 0x227f, 0xc138, 0x21, 0 + .dw 0x22c0, 0xc138, 0x22ff, 0xc138, 0x21, 0 + .dw 0x2340, 0xc138, 0x237f, 0xc138, 0x21, 0 + .dw 0x23c0, 0xc138, 0x23ff, 0xc138, 0x21, 0 + .dw 0x2440, 0xc138, 0x247f, 0xc138, 0x21, 0 + .dw 0x24c0, 0xc138, 0x24ff, 0xc138, 0x21, 0 + .dw 0x2540, 0xc138, 0x257f, 0xc138, 0x21, 0 + .dw 0x25c0, 0xc138, 0x25ff, 0xc138, 0x21, 0 + .dw 0x2640, 0xc138, 0x267f, 0xc138, 0x21, 0 + .dw 0x26c0, 0xc138, 0x26ff, 0xc138, 0x21, 0 + .dw 0x2740, 0xc138, 0x277f, 0xc138, 0x21, 0 + .dw 0x27c0, 0xc138, 0x27ff, 0xc138, 0x21, 0 + .dw 0x2840, 0xc138, 0x287f, 0xc138, 0x21, 0 + .dw 0x28c0, 0xc138, 0x28ff, 0xc138, 0x21, 0 + .dw 0x2940, 0xc138, 0x297f, 0xc138, 0x21, 0 + .dw 0x29c0, 0xc138, 0x29ff, 0xc138, 0x21, 0 + .dw 0x2a40, 0xc138, 0x2a7f, 0xc138, 0x21, 0 + .dw 0x2ac0, 0xc138, 0x2aff, 0xc138, 0x21, 0 + .dw 0x2b40, 0xc138, 0x2b7f, 0xc138, 0x21, 0 + .dw 0x2bc0, 0xc138, 0x2bff, 0xc138, 0x21, 0 + .dw 0x2c40, 0xc138, 0x2c7f, 0xc138, 0x21, 0 + .dw 0x2cc0, 0xc138, 0x2cff, 0xc138, 0x21, 0 + .dw 0x2d40, 0xc138, 0x2d7f, 0xc138, 0x21, 0 + .dw 0x2dc0, 0xc138, 0x2dff, 0xc138, 0x21, 0 + .dw 0x2e40, 0xc138, 0x2e7f, 0xc138, 0x21, 0 + .dw 0x2ec0, 0xc138, 0x2eff, 0xc138, 0x21, 0 + .dw 0x2f40, 0xc138, 0x2f7f, 0xc138, 0x21, 0 + .dw 0x2fc0, 0xc138, 0x2fff, 0xc138, 0x21, 0 + .dw 0x3040, 0xc138, 0x307f, 0xc138, 0x21, 0 + .dw 0x30c0, 0xc138, 0x30ff, 0xc138, 0x21, 0 + .dw 0x3140, 0xc138, 0x317f, 0xc138, 0x21, 0 + .dw 0x31c0, 0xc138, 0x31ff, 0xc138, 0x21, 0 + .dw 0x3240, 0xc138, 0x327f, 0xc138, 0x21, 0 + .dw 0x32c0, 0xc138, 0x32ff, 0xc138, 0x21, 0 + .dw 0x3340, 0xc138, 0x337f, 0xc138, 0x21, 0 + .dw 0x33c0, 0xc138, 0x33ff, 0xc138, 0x21, 0 + .dw 0x3440, 0xc138, 0x347f, 0xc138, 0x21, 0 + .dw 0x34c0, 0xc138, 0x34ff, 0xc138, 0x21, 0 + .dw 0x3540, 0xc138, 0x357f, 0xc138, 0x21, 0 + .dw 0x35c0, 0xc138, 0x35ff, 0xc138, 0x21, 0 + .dw 0x3640, 0xc138, 0x367f, 0xc138, 0x21, 0 + .dw 0x36c0, 0xc138, 0x36ff, 0xc138, 0x21, 0 + .dw 0x3740, 0xc138, 0x377f, 0xc138, 0x21, 0 + .dw 0x37c0, 0xc138, 0x37ff, 0xc138, 0x21, 0 + .dw 0x3840, 0xc138, 0x387f, 0xc138, 0x21, 0 + .dw 0x38c0, 0xc138, 0x38ff, 0xc138, 0x21, 0 + .dw 0x3940, 0xc138, 0x397f, 0xc138, 0x21, 0 + .dw 0x39c0, 0xc138, 0x5fff, 0xc138, 0x21, 0 + .dw 0x6040, 0xc138, 0x607f, 0xc138, 0x21, 0 + .dw 0x60c0, 0xc138, 0x60ff, 0xc138, 0x21, 0 + .dw 0x6140, 0xc138, 0x617f, 0xc138, 0x21, 0 + .dw 0x61c0, 0xc138, 0x61ff, 0xc138, 0x21, 0 + .dw 0x6240, 0xc138, 0x627f, 0xc138, 0x21, 0 + .dw 0x62c0, 0xc138, 0x62ff, 0xc138, 0x21, 0 + .dw 0x6340, 0xc138, 0x637f, 0xc138, 0x21, 0 + .dw 0x63c0, 0xc138, 0x63ff, 0xc138, 0x21, 0 + .dw 0x6440, 0xc138, 0x647f, 0xc138, 0x21, 0 + .dw 0x64c0, 0xc138, 0x64ff, 0xc138, 0x21, 0 + .dw 0x6540, 0xc138, 0x657f, 0xc138, 0x21, 0 + .dw 0x65c0, 0xc138, 0x65ff, 0xc138, 0x21, 0 + .dw 0x6640, 0xc138, 0x667f, 0xc138, 0x21, 0 + .dw 0x66c0, 0xc138, 0x66ff, 0xc138, 0x21, 0 + .dw 0x6740, 0xc138, 0x677f, 0xc138, 0x21, 0 + .dw 0x67c0, 0xc138, 0x67ff, 0xc138, 0x21, 0 + .dw 0x6840, 0xc138, 0x687f, 0xc138, 0x21, 0 + .dw 0x68c0, 0xc138, 0x68ff, 0xc138, 0x21, 0 + .dw 0x6940, 0xc138, 0x697f, 0xc138, 0x21, 0 + .dw 0x69c0, 0xc138, 0x69ff, 0xc138, 0x21, 0 + .dw 0x6a40, 0xc138, 0x6a7f, 0xc138, 0x21, 0 + .dw 0x6ac0, 0xc138, 0x6aff, 0xc138, 0x21, 0 + .dw 0x6b40, 0xc138, 0x6b7f, 0xc138, 0x21, 0 + .dw 0x6bc0, 0xc138, 0x6bff, 0xc138, 0x21, 0 + .dw 0x6c40, 0xc138, 0x6c7f, 0xc138, 0x21, 0 + .dw 0x6cc0, 0xc138, 0x6cff, 0xc138, 0x21, 0 + .dw 0x6d40, 0xc138, 0x6d7f, 0xc138, 0x21, 0 + .dw 0x6dc0, 0xc138, 0x6dff, 0xc138, 0x21, 0 + .dw 0x6e40, 0xc138, 0x6e7f, 0xc138, 0x21, 0 + .dw 0x6ec0, 0xc138, 0x6eff, 0xc138, 0x21, 0 + .dw 0x6f40, 0xc138, 0x6f7f, 0xc138, 0x21, 0 + .dw 0x6fc0, 0xc138, 0x6fff, 0xc138, 0x21, 0 + .dw 0x7040, 0xc138, 0x707f, 0xc138, 0x21, 0 + .dw 0x70c0, 0xc138, 0x70ff, 0xc138, 0x21, 0 + .dw 0x7140, 0xc138, 0x717f, 0xc138, 0x21, 0 + .dw 0x71c0, 0xc138, 0x71ff, 0xc138, 0x21, 0 + .dw 0x7240, 0xc138, 0x727f, 0xc138, 0x21, 0 + .dw 0x72c0, 0xc138, 0x72ff, 0xc138, 0x21, 0 + .dw 0x7340, 0xc138, 0x737f, 0xc138, 0x21, 0 + .dw 0x73c0, 0xc138, 0x73ff, 0xc138, 0x21, 0 + .dw 0x7440, 0xc138, 0x747f, 0xc138, 0x21, 0 + .dw 0x74c0, 0xc138, 0x74ff, 0xc138, 0x21, 0 + .dw 0x7540, 0xc138, 0x757f, 0xc138, 0x21, 0 + .dw 0x75c0, 0xc138, 0x75ff, 0xc138, 0x21, 0 + .dw 0x7640, 0xc138, 0x767f, 0xc138, 0x21, 0 + .dw 0x76c0, 0xc138, 0x76ff, 0xc138, 0x21, 0 + .dw 0x7740, 0xc138, 0x777f, 0xc138, 0x21, 0 + .dw 0x77c0, 0xc138, 0x77ff, 0xc138, 0x21, 0 + .dw 0x7840, 0xc138, 0x787f, 0xc138, 0x21, 0 + .dw 0x78c0, 0xc138, 0x78ff, 0xc138, 0x21, 0 + .dw 0x7940, 0xc138, 0x797f, 0xc138, 0x21, 0 + .dw 0x79c0, 0xc138, 0x9fff, 0xc138, 0x21, 0 + .dw 0xa040, 0xc138, 0xa07f, 0xc138, 0x21, 0 + .dw 0xa0c0, 0xc138, 0xa0ff, 0xc138, 0x21, 0 + .dw 0xa140, 0xc138, 0xa17f, 0xc138, 0x21, 0 + .dw 0xa1c0, 0xc138, 0xa1ff, 0xc138, 0x21, 0 + .dw 0xa240, 0xc138, 0xa27f, 0xc138, 0x21, 0 + .dw 0xa2c0, 0xc138, 0xa2ff, 0xc138, 0x21, 0 + .dw 0xa340, 0xc138, 0xa37f, 0xc138, 0x21, 0 + .dw 0xa3c0, 0xc138, 0xa3ff, 0xc138, 0x21, 0 + .dw 0xa440, 0xc138, 0xa47f, 0xc138, 0x21, 0 + .dw 0xa4c0, 0xc138, 0xa4ff, 0xc138, 0x21, 0 + .dw 0xa540, 0xc138, 0xa57f, 0xc138, 0x21, 0 + .dw 0xa5c0, 0xc138, 0xa5ff, 0xc138, 0x21, 0 + .dw 0xa640, 0xc138, 0xa67f, 0xc138, 0x21, 0 + .dw 0xa6c0, 0xc138, 0xa6ff, 0xc138, 0x21, 0 + .dw 0xa740, 0xc138, 0xa77f, 0xc138, 0x21, 0 + .dw 0xa7c0, 0xc138, 0xa7ff, 0xc138, 0x21, 0 + .dw 0xa840, 0xc138, 0xa87f, 0xc138, 0x21, 0 + .dw 0xa8c0, 0xc138, 0xa8ff, 0xc138, 0x21, 0 + .dw 0xa940, 0xc138, 0xa97f, 0xc138, 0x21, 0 + .dw 0xa9c0, 0xc138, 0xa9ff, 0xc138, 0x21, 0 + .dw 0xaa40, 0xc138, 0xaa7f, 0xc138, 0x21, 0 + .dw 0xaac0, 0xc138, 0xaaff, 0xc138, 0x21, 0 + .dw 0xab40, 0xc138, 0xab7f, 0xc138, 0x21, 0 + .dw 0xabc0, 0xc138, 0xabff, 0xc138, 0x21, 0 + .dw 0xac40, 0xc138, 0xac7f, 0xc138, 0x21, 0 + .dw 0xacc0, 0xc138, 0xacff, 0xc138, 0x21, 0 + .dw 0xad40, 0xc138, 0xad7f, 0xc138, 0x21, 0 + .dw 0xadc0, 0xc138, 0xadff, 0xc138, 0x21, 0 + .dw 0xae40, 0xc138, 0xae7f, 0xc138, 0x21, 0 + .dw 0xaec0, 0xc138, 0xaeff, 0xc138, 0x21, 0 + .dw 0xaf40, 0xc138, 0xaf7f, 0xc138, 0x21, 0 + .dw 0xafc0, 0xc138, 0xafff, 0xc138, 0x21, 0 + .dw 0xb040, 0xc138, 0xb07f, 0xc138, 0x21, 0 + .dw 0xb0c0, 0xc138, 0xb0ff, 0xc138, 0x21, 0 + .dw 0xb140, 0xc138, 0xb17f, 0xc138, 0x21, 0 + .dw 0xb1c0, 0xc138, 0xb1ff, 0xc138, 0x21, 0 + .dw 0xb240, 0xc138, 0xb27f, 0xc138, 0x21, 0 + .dw 0xb2c0, 0xc138, 0xb2ff, 0xc138, 0x21, 0 + .dw 0xb340, 0xc138, 0xb37f, 0xc138, 0x21, 0 + .dw 0xb3c0, 0xc138, 0xb3ff, 0xc138, 0x21, 0 + .dw 0xb440, 0xc138, 0xb47f, 0xc138, 0x21, 0 + .dw 0xb4c0, 0xc138, 0xb4ff, 0xc138, 0x21, 0 + .dw 0xb540, 0xc138, 0xb57f, 0xc138, 0x21, 0 + .dw 0xb5c0, 0xc138, 0xb5ff, 0xc138, 0x21, 0 + .dw 0xb640, 0xc138, 0xb67f, 0xc138, 0x21, 0 + .dw 0xb6c0, 0xc138, 0xb6ff, 0xc138, 0x21, 0 + .dw 0xb740, 0xc138, 0xb77f, 0xc138, 0x21, 0 + .dw 0xb7c0, 0xc138, 0xb7ff, 0xc138, 0x21, 0 + .dw 0xb840, 0xc138, 0xb87f, 0xc138, 0x21, 0 + .dw 0xb8c0, 0xc138, 0xb8ff, 0xc138, 0x21, 0 + .dw 0xb940, 0xc138, 0xb97f, 0xc138, 0x21, 0 + .dw 0xb9c0, 0xc138, 0xdfff, 0xc138, 0x21, 0 + .dw 0xe040, 0xc138, 0xe07f, 0xc138, 0x21, 0 + .dw 0xe0c0, 0xc138, 0xe0ff, 0xc138, 0x21, 0 + .dw 0xe140, 0xc138, 0xe17f, 0xc138, 0x21, 0 + .dw 0xe1c0, 0xc138, 0xe1ff, 0xc138, 0x21, 0 + .dw 0xe240, 0xc138, 0xe27f, 0xc138, 0x21, 0 + .dw 0xe2c0, 0xc138, 0xe2ff, 0xc138, 0x21, 0 + .dw 0xe340, 0xc138, 0xe37f, 0xc138, 0x21, 0 + .dw 0xe3c0, 0xc138, 0xe3ff, 0xc138, 0x21, 0 + .dw 0xe440, 0xc138, 0xe47f, 0xc138, 0x21, 0 + .dw 0xe4c0, 0xc138, 0xe4ff, 0xc138, 0x21, 0 + .dw 0xe540, 0xc138, 0xe57f, 0xc138, 0x21, 0 + .dw 0xe5c0, 0xc138, 0xe5ff, 0xc138, 0x21, 0 + .dw 0xe640, 0xc138, 0xe67f, 0xc138, 0x21, 0 + .dw 0xe6c0, 0xc138, 0xe6ff, 0xc138, 0x21, 0 + .dw 0xe740, 0xc138, 0xe77f, 0xc138, 0x21, 0 + .dw 0xe7c0, 0xc138, 0xe7ff, 0xc138, 0x21, 0 + .dw 0xe840, 0xc138, 0xe87f, 0xc138, 0x21, 0 + .dw 0xe8c0, 0xc138, 0xe8ff, 0xc138, 0x21, 0 + .dw 0xe940, 0xc138, 0xe97f, 0xc138, 0x21, 0 + .dw 0xe9c0, 0xc138, 0xe9ff, 0xc138, 0x21, 0 + .dw 0xea40, 0xc138, 0xea7f, 0xc138, 0x21, 0 + .dw 0xeac0, 0xc138, 0xeaff, 0xc138, 0x21, 0 + .dw 0xeb40, 0xc138, 0xeb7f, 0xc138, 0x21, 0 + .dw 0xebc0, 0xc138, 0xebff, 0xc138, 0x21, 0 + .dw 0xec40, 0xc138, 0xec7f, 0xc138, 0x21, 0 + .dw 0xecc0, 0xc138, 0xecff, 0xc138, 0x21, 0 + .dw 0xed40, 0xc138, 0xed7f, 0xc138, 0x21, 0 + .dw 0xedc0, 0xc138, 0xedff, 0xc138, 0x21, 0 + .dw 0xee40, 0xc138, 0xee7f, 0xc138, 0x21, 0 + .dw 0xeec0, 0xc138, 0xeeff, 0xc138, 0x21, 0 + .dw 0xef40, 0xc138, 0xef7f, 0xc138, 0x21, 0 + .dw 0xefc0, 0xc138, 0xefff, 0xc138, 0x21, 0 + .dw 0xf040, 0xc138, 0xf07f, 0xc138, 0x21, 0 + .dw 0xf0c0, 0xc138, 0xf0ff, 0xc138, 0x21, 0 + .dw 0xf140, 0xc138, 0xf17f, 0xc138, 0x21, 0 + .dw 0xf1c0, 0xc138, 0xf1ff, 0xc138, 0x21, 0 + .dw 0xf240, 0xc138, 0xf27f, 0xc138, 0x21, 0 + .dw 0xf2c0, 0xc138, 0xf2ff, 0xc138, 0x21, 0 + .dw 0xf340, 0xc138, 0xf37f, 0xc138, 0x21, 0 + .dw 0xf3c0, 0xc138, 0xf3ff, 0xc138, 0x21, 0 + .dw 0xf440, 0xc138, 0xf47f, 0xc138, 0x21, 0 + .dw 0xf4c0, 0xc138, 0xf4ff, 0xc138, 0x21, 0 + .dw 0xf540, 0xc138, 0xf57f, 0xc138, 0x21, 0 + .dw 0xf5c0, 0xc138, 0xf5ff, 0xc138, 0x21, 0 + .dw 0xf640, 0xc138, 0xf67f, 0xc138, 0x21, 0 + .dw 0xf6c0, 0xc138, 0xf6ff, 0xc138, 0x21, 0 + .dw 0xf740, 0xc138, 0xf77f, 0xc138, 0x21, 0 + .dw 0xf7c0, 0xc138, 0xf7ff, 0xc138, 0x21, 0 + .dw 0xf840, 0xc138, 0xf87f, 0xc138, 0x21, 0 + .dw 0xf8c0, 0xc138, 0xf8ff, 0xc138, 0x21, 0 + .dw 0xf940, 0xc138, 0xf97f, 0xc138, 0x21, 0 + .dw 0xf9c0, 0xc138, 0x1fff, 0xc139, 0x21, 0 + .dw 0x2040, 0xc139, 0x207f, 0xc139, 0x21, 0 + .dw 0x20c0, 0xc139, 0x20ff, 0xc139, 0x21, 0 + .dw 0x2140, 0xc139, 0x217f, 0xc139, 0x21, 0 + .dw 0x21c0, 0xc139, 0x21ff, 0xc139, 0x21, 0 + .dw 0x2240, 0xc139, 0x227f, 0xc139, 0x21, 0 + .dw 0x22c0, 0xc139, 0x22ff, 0xc139, 0x21, 0 + .dw 0x2340, 0xc139, 0x237f, 0xc139, 0x21, 0 + .dw 0x23c0, 0xc139, 0x23ff, 0xc139, 0x21, 0 + .dw 0x2440, 0xc139, 0x247f, 0xc139, 0x21, 0 + .dw 0x24c0, 0xc139, 0x24ff, 0xc139, 0x21, 0 + .dw 0x2540, 0xc139, 0x257f, 0xc139, 0x21, 0 + .dw 0x25c0, 0xc139, 0x25ff, 0xc139, 0x21, 0 + .dw 0x2640, 0xc139, 0x267f, 0xc139, 0x21, 0 + .dw 0x26c0, 0xc139, 0x26ff, 0xc139, 0x21, 0 + .dw 0x2740, 0xc139, 0x277f, 0xc139, 0x21, 0 + .dw 0x27c0, 0xc139, 0x27ff, 0xc139, 0x21, 0 + .dw 0x2840, 0xc139, 0x287f, 0xc139, 0x21, 0 + .dw 0x28c0, 0xc139, 0x28ff, 0xc139, 0x21, 0 + .dw 0x2940, 0xc139, 0x297f, 0xc139, 0x21, 0 + .dw 0x29c0, 0xc139, 0x29ff, 0xc139, 0x21, 0 + .dw 0x2a40, 0xc139, 0x2a7f, 0xc139, 0x21, 0 + .dw 0x2ac0, 0xc139, 0x2aff, 0xc139, 0x21, 0 + .dw 0x2b40, 0xc139, 0x2b7f, 0xc139, 0x21, 0 + .dw 0x2bc0, 0xc139, 0x2bff, 0xc139, 0x21, 0 + .dw 0x2c40, 0xc139, 0x2c7f, 0xc139, 0x21, 0 + .dw 0x2cc0, 0xc139, 0x2cff, 0xc139, 0x21, 0 + .dw 0x2d40, 0xc139, 0x2d7f, 0xc139, 0x21, 0 + .dw 0x2dc0, 0xc139, 0x2dff, 0xc139, 0x21, 0 + .dw 0x2e40, 0xc139, 0x2e7f, 0xc139, 0x21, 0 + .dw 0x2ec0, 0xc139, 0x2eff, 0xc139, 0x21, 0 + .dw 0x2f40, 0xc139, 0x2f7f, 0xc139, 0x21, 0 + .dw 0x2fc0, 0xc139, 0x2fff, 0xc139, 0x21, 0 + .dw 0x3040, 0xc139, 0x307f, 0xc139, 0x21, 0 + .dw 0x30c0, 0xc139, 0x30ff, 0xc139, 0x21, 0 + .dw 0x3140, 0xc139, 0x317f, 0xc139, 0x21, 0 + .dw 0x31c0, 0xc139, 0x31ff, 0xc139, 0x21, 0 + .dw 0x3240, 0xc139, 0x327f, 0xc139, 0x21, 0 + .dw 0x32c0, 0xc139, 0x32ff, 0xc139, 0x21, 0 + .dw 0x3340, 0xc139, 0x337f, 0xc139, 0x21, 0 + .dw 0x33c0, 0xc139, 0x33ff, 0xc139, 0x21, 0 + .dw 0x3440, 0xc139, 0x347f, 0xc139, 0x21, 0 + .dw 0x34c0, 0xc139, 0x34ff, 0xc139, 0x21, 0 + .dw 0x3540, 0xc139, 0x357f, 0xc139, 0x21, 0 + .dw 0x35c0, 0xc139, 0x35ff, 0xc139, 0x21, 0 + .dw 0x3640, 0xc139, 0x367f, 0xc139, 0x21, 0 + .dw 0x36c0, 0xc139, 0x36ff, 0xc139, 0x21, 0 + .dw 0x3740, 0xc139, 0x377f, 0xc139, 0x21, 0 + .dw 0x37c0, 0xc139, 0x37ff, 0xc139, 0x21, 0 + .dw 0x3840, 0xc139, 0x387f, 0xc139, 0x21, 0 + .dw 0x38c0, 0xc139, 0x38ff, 0xc139, 0x21, 0 + .dw 0x3940, 0xc139, 0x397f, 0xc139, 0x21, 0 + .dw 0x39c0, 0xc139, 0x5fff, 0xc139, 0x21, 0 + .dw 0x6040, 0xc139, 0x607f, 0xc139, 0x21, 0 + .dw 0x60c0, 0xc139, 0x60ff, 0xc139, 0x21, 0 + .dw 0x6140, 0xc139, 0x617f, 0xc139, 0x21, 0 + .dw 0x61c0, 0xc139, 0x61ff, 0xc139, 0x21, 0 + .dw 0x6240, 0xc139, 0x627f, 0xc139, 0x21, 0 + .dw 0x62c0, 0xc139, 0x62ff, 0xc139, 0x21, 0 + .dw 0x6340, 0xc139, 0x637f, 0xc139, 0x21, 0 + .dw 0x63c0, 0xc139, 0x63ff, 0xc139, 0x21, 0 + .dw 0x6440, 0xc139, 0x647f, 0xc139, 0x21, 0 + .dw 0x64c0, 0xc139, 0x64ff, 0xc139, 0x21, 0 + .dw 0x6540, 0xc139, 0x657f, 0xc139, 0x21, 0 + .dw 0x65c0, 0xc139, 0x65ff, 0xc139, 0x21, 0 + .dw 0x6640, 0xc139, 0x667f, 0xc139, 0x21, 0 + .dw 0x66c0, 0xc139, 0x66ff, 0xc139, 0x21, 0 + .dw 0x6740, 0xc139, 0x677f, 0xc139, 0x21, 0 + .dw 0x67c0, 0xc139, 0x67ff, 0xc139, 0x21, 0 + .dw 0x6840, 0xc139, 0x687f, 0xc139, 0x21, 0 + .dw 0x68c0, 0xc139, 0x68ff, 0xc139, 0x21, 0 + .dw 0x6940, 0xc139, 0x697f, 0xc139, 0x21, 0 + .dw 0x69c0, 0xc139, 0x69ff, 0xc139, 0x21, 0 + .dw 0x6a40, 0xc139, 0x6a7f, 0xc139, 0x21, 0 + .dw 0x6ac0, 0xc139, 0x6aff, 0xc139, 0x21, 0 + .dw 0x6b40, 0xc139, 0x6b7f, 0xc139, 0x21, 0 + .dw 0x6bc0, 0xc139, 0x6bff, 0xc139, 0x21, 0 + .dw 0x6c40, 0xc139, 0x6c7f, 0xc139, 0x21, 0 + .dw 0x6cc0, 0xc139, 0x6cff, 0xc139, 0x21, 0 + .dw 0x6d40, 0xc139, 0x6d7f, 0xc139, 0x21, 0 + .dw 0x6dc0, 0xc139, 0x6dff, 0xc139, 0x21, 0 + .dw 0x6e40, 0xc139, 0x6e7f, 0xc139, 0x21, 0 + .dw 0x6ec0, 0xc139, 0x6eff, 0xc139, 0x21, 0 + .dw 0x6f40, 0xc139, 0x6f7f, 0xc139, 0x21, 0 + .dw 0x6fc0, 0xc139, 0x6fff, 0xc139, 0x21, 0 + .dw 0x7040, 0xc139, 0x707f, 0xc139, 0x21, 0 + .dw 0x70c0, 0xc139, 0x70ff, 0xc139, 0x21, 0 + .dw 0x7140, 0xc139, 0x717f, 0xc139, 0x21, 0 + .dw 0x71c0, 0xc139, 0x71ff, 0xc139, 0x21, 0 + .dw 0x7240, 0xc139, 0x727f, 0xc139, 0x21, 0 + .dw 0x72c0, 0xc139, 0x72ff, 0xc139, 0x21, 0 + .dw 0x7340, 0xc139, 0x737f, 0xc139, 0x21, 0 + .dw 0x73c0, 0xc139, 0x73ff, 0xc139, 0x21, 0 + .dw 0x7440, 0xc139, 0x747f, 0xc139, 0x21, 0 + .dw 0x74c0, 0xc139, 0x74ff, 0xc139, 0x21, 0 + .dw 0x7540, 0xc139, 0x757f, 0xc139, 0x21, 0 + .dw 0x75c0, 0xc139, 0x75ff, 0xc139, 0x21, 0 + .dw 0x7640, 0xc139, 0x767f, 0xc139, 0x21, 0 + .dw 0x76c0, 0xc139, 0x76ff, 0xc139, 0x21, 0 + .dw 0x7740, 0xc139, 0x777f, 0xc139, 0x21, 0 + .dw 0x77c0, 0xc139, 0x77ff, 0xc139, 0x21, 0 + .dw 0x7840, 0xc139, 0x787f, 0xc139, 0x21, 0 + .dw 0x78c0, 0xc139, 0x78ff, 0xc139, 0x21, 0 + .dw 0x7940, 0xc139, 0x797f, 0xc139, 0x21, 0 + .dw 0x79c0, 0xc139, 0x9fff, 0xc139, 0x21, 0 + .dw 0xa040, 0xc139, 0xa07f, 0xc139, 0x21, 0 + .dw 0xa0c0, 0xc139, 0xa0ff, 0xc139, 0x21, 0 + .dw 0xa140, 0xc139, 0xa17f, 0xc139, 0x21, 0 + .dw 0xa1c0, 0xc139, 0xa1ff, 0xc139, 0x21, 0 + .dw 0xa240, 0xc139, 0xa27f, 0xc139, 0x21, 0 + .dw 0xa2c0, 0xc139, 0xa2ff, 0xc139, 0x21, 0 + .dw 0xa340, 0xc139, 0xa37f, 0xc139, 0x21, 0 + .dw 0xa3c0, 0xc139, 0xa3ff, 0xc139, 0x21, 0 + .dw 0xa440, 0xc139, 0xa47f, 0xc139, 0x21, 0 + .dw 0xa4c0, 0xc139, 0xa4ff, 0xc139, 0x21, 0 + .dw 0xa540, 0xc139, 0xa57f, 0xc139, 0x21, 0 + .dw 0xa5c0, 0xc139, 0xa5ff, 0xc139, 0x21, 0 + .dw 0xa640, 0xc139, 0xa67f, 0xc139, 0x21, 0 + .dw 0xa6c0, 0xc139, 0xa6ff, 0xc139, 0x21, 0 + .dw 0xa740, 0xc139, 0xa77f, 0xc139, 0x21, 0 + .dw 0xa7c0, 0xc139, 0xa7ff, 0xc139, 0x21, 0 + .dw 0xa840, 0xc139, 0xa87f, 0xc139, 0x21, 0 + .dw 0xa8c0, 0xc139, 0xa8ff, 0xc139, 0x21, 0 + .dw 0xa940, 0xc139, 0xa97f, 0xc139, 0x21, 0 + .dw 0xa9c0, 0xc139, 0xa9ff, 0xc139, 0x21, 0 + .dw 0xaa40, 0xc139, 0xaa7f, 0xc139, 0x21, 0 + .dw 0xaac0, 0xc139, 0xaaff, 0xc139, 0x21, 0 + .dw 0xab40, 0xc139, 0xab7f, 0xc139, 0x21, 0 + .dw 0xabc0, 0xc139, 0xabff, 0xc139, 0x21, 0 + .dw 0xac40, 0xc139, 0xac7f, 0xc139, 0x21, 0 + .dw 0xacc0, 0xc139, 0xacff, 0xc139, 0x21, 0 + .dw 0xad40, 0xc139, 0xad7f, 0xc139, 0x21, 0 + .dw 0xadc0, 0xc139, 0xadff, 0xc139, 0x21, 0 + .dw 0xae40, 0xc139, 0xae7f, 0xc139, 0x21, 0 + .dw 0xaec0, 0xc139, 0xaeff, 0xc139, 0x21, 0 + .dw 0xaf40, 0xc139, 0xaf7f, 0xc139, 0x21, 0 + .dw 0xafc0, 0xc139, 0xafff, 0xc139, 0x21, 0 + .dw 0xb040, 0xc139, 0xb07f, 0xc139, 0x21, 0 + .dw 0xb0c0, 0xc139, 0xb0ff, 0xc139, 0x21, 0 + .dw 0xb140, 0xc139, 0xb17f, 0xc139, 0x21, 0 + .dw 0xb1c0, 0xc139, 0xb1ff, 0xc139, 0x21, 0 + .dw 0xb240, 0xc139, 0xb27f, 0xc139, 0x21, 0 + .dw 0xb2c0, 0xc139, 0xb2ff, 0xc139, 0x21, 0 + .dw 0xb340, 0xc139, 0xb37f, 0xc139, 0x21, 0 + .dw 0xb3c0, 0xc139, 0xb3ff, 0xc139, 0x21, 0 + .dw 0xb440, 0xc139, 0xb47f, 0xc139, 0x21, 0 + .dw 0xb4c0, 0xc139, 0xb4ff, 0xc139, 0x21, 0 + .dw 0xb540, 0xc139, 0xb57f, 0xc139, 0x21, 0 + .dw 0xb5c0, 0xc139, 0xb5ff, 0xc139, 0x21, 0 + .dw 0xb640, 0xc139, 0xb67f, 0xc139, 0x21, 0 + .dw 0xb6c0, 0xc139, 0xb6ff, 0xc139, 0x21, 0 + .dw 0xb740, 0xc139, 0xb77f, 0xc139, 0x21, 0 + .dw 0xb7c0, 0xc139, 0xb7ff, 0xc139, 0x21, 0 + .dw 0xb840, 0xc139, 0xb87f, 0xc139, 0x21, 0 + .dw 0xb8c0, 0xc139, 0xb8ff, 0xc139, 0x21, 0 + .dw 0xb940, 0xc139, 0xb97f, 0xc139, 0x21, 0 + .dw 0xb9c0, 0xc139, 0xdfff, 0xc139, 0x21, 0 + .dw 0xe040, 0xc139, 0xe07f, 0xc139, 0x21, 0 + .dw 0xe0c0, 0xc139, 0xe0ff, 0xc139, 0x21, 0 + .dw 0xe140, 0xc139, 0xe17f, 0xc139, 0x21, 0 + .dw 0xe1c0, 0xc139, 0xe1ff, 0xc139, 0x21, 0 + .dw 0xe240, 0xc139, 0xe27f, 0xc139, 0x21, 0 + .dw 0xe2c0, 0xc139, 0xe2ff, 0xc139, 0x21, 0 + .dw 0xe340, 0xc139, 0xe37f, 0xc139, 0x21, 0 + .dw 0xe3c0, 0xc139, 0xe3ff, 0xc139, 0x21, 0 + .dw 0xe440, 0xc139, 0xe47f, 0xc139, 0x21, 0 + .dw 0xe4c0, 0xc139, 0xe4ff, 0xc139, 0x21, 0 + .dw 0xe540, 0xc139, 0xe57f, 0xc139, 0x21, 0 + .dw 0xe5c0, 0xc139, 0xe5ff, 0xc139, 0x21, 0 + .dw 0xe640, 0xc139, 0xe67f, 0xc139, 0x21, 0 + .dw 0xe6c0, 0xc139, 0xe6ff, 0xc139, 0x21, 0 + .dw 0xe740, 0xc139, 0xe77f, 0xc139, 0x21, 0 + .dw 0xe7c0, 0xc139, 0xe7ff, 0xc139, 0x21, 0 + .dw 0xe840, 0xc139, 0xe87f, 0xc139, 0x21, 0 + .dw 0xe8c0, 0xc139, 0xe8ff, 0xc139, 0x21, 0 + .dw 0xe940, 0xc139, 0xe97f, 0xc139, 0x21, 0 + .dw 0xe9c0, 0xc139, 0xe9ff, 0xc139, 0x21, 0 + .dw 0xea40, 0xc139, 0xea7f, 0xc139, 0x21, 0 + .dw 0xeac0, 0xc139, 0xeaff, 0xc139, 0x21, 0 + .dw 0xeb40, 0xc139, 0xeb7f, 0xc139, 0x21, 0 + .dw 0xebc0, 0xc139, 0xebff, 0xc139, 0x21, 0 + .dw 0xec40, 0xc139, 0xec7f, 0xc139, 0x21, 0 + .dw 0xecc0, 0xc139, 0xecff, 0xc139, 0x21, 0 + .dw 0xed40, 0xc139, 0xed7f, 0xc139, 0x21, 0 + .dw 0xedc0, 0xc139, 0xedff, 0xc139, 0x21, 0 + .dw 0xee40, 0xc139, 0xee7f, 0xc139, 0x21, 0 + .dw 0xeec0, 0xc139, 0xeeff, 0xc139, 0x21, 0 + .dw 0xef40, 0xc139, 0xef7f, 0xc139, 0x21, 0 + .dw 0xefc0, 0xc139, 0xefff, 0xc139, 0x21, 0 + .dw 0xf040, 0xc139, 0xf07f, 0xc139, 0x21, 0 + .dw 0xf0c0, 0xc139, 0xf0ff, 0xc139, 0x21, 0 + .dw 0xf140, 0xc139, 0xf17f, 0xc139, 0x21, 0 + .dw 0xf1c0, 0xc139, 0xf1ff, 0xc139, 0x21, 0 + .dw 0xf240, 0xc139, 0xf27f, 0xc139, 0x21, 0 + .dw 0xf2c0, 0xc139, 0xf2ff, 0xc139, 0x21, 0 + .dw 0xf340, 0xc139, 0xf37f, 0xc139, 0x21, 0 + .dw 0xf3c0, 0xc139, 0xf3ff, 0xc139, 0x21, 0 + .dw 0xf440, 0xc139, 0xf47f, 0xc139, 0x21, 0 + .dw 0xf4c0, 0xc139, 0xf4ff, 0xc139, 0x21, 0 + .dw 0xf540, 0xc139, 0xf57f, 0xc139, 0x21, 0 + .dw 0xf5c0, 0xc139, 0xf5ff, 0xc139, 0x21, 0 + .dw 0xf640, 0xc139, 0xf67f, 0xc139, 0x21, 0 + .dw 0xf6c0, 0xc139, 0xf6ff, 0xc139, 0x21, 0 + .dw 0xf740, 0xc139, 0xf77f, 0xc139, 0x21, 0 + .dw 0xf7c0, 0xc139, 0xf7ff, 0xc139, 0x21, 0 + .dw 0xf840, 0xc139, 0xf87f, 0xc139, 0x21, 0 + .dw 0xf8c0, 0xc139, 0xf8ff, 0xc139, 0x21, 0 + .dw 0xf940, 0xc139, 0xf97f, 0xc139, 0x21, 0 + .dw 0xf9c0, 0xc139, 0x1fff, 0xc13a, 0x21, 0 + .dw 0x2040, 0xc13a, 0x207f, 0xc13a, 0x21, 0 + .dw 0x20c0, 0xc13a, 0x20ff, 0xc13a, 0x21, 0 + .dw 0x2140, 0xc13a, 0x217f, 0xc13a, 0x21, 0 + .dw 0x21c0, 0xc13a, 0x21ff, 0xc13a, 0x21, 0 + .dw 0x2240, 0xc13a, 0x227f, 0xc13a, 0x21, 0 + .dw 0x22c0, 0xc13a, 0x22ff, 0xc13a, 0x21, 0 + .dw 0x2340, 0xc13a, 0x237f, 0xc13a, 0x21, 0 + .dw 0x23c0, 0xc13a, 0x23ff, 0xc13a, 0x21, 0 + .dw 0x2440, 0xc13a, 0x247f, 0xc13a, 0x21, 0 + .dw 0x24c0, 0xc13a, 0x24ff, 0xc13a, 0x21, 0 + .dw 0x2540, 0xc13a, 0x257f, 0xc13a, 0x21, 0 + .dw 0x25c0, 0xc13a, 0x25ff, 0xc13a, 0x21, 0 + .dw 0x2640, 0xc13a, 0x267f, 0xc13a, 0x21, 0 + .dw 0x26c0, 0xc13a, 0x26ff, 0xc13a, 0x21, 0 + .dw 0x2740, 0xc13a, 0x277f, 0xc13a, 0x21, 0 + .dw 0x27c0, 0xc13a, 0x27ff, 0xc13a, 0x21, 0 + .dw 0x2840, 0xc13a, 0x287f, 0xc13a, 0x21, 0 + .dw 0x28c0, 0xc13a, 0x28ff, 0xc13a, 0x21, 0 + .dw 0x2940, 0xc13a, 0x297f, 0xc13a, 0x21, 0 + .dw 0x29c0, 0xc13a, 0x29ff, 0xc13a, 0x21, 0 + .dw 0x2a40, 0xc13a, 0x2a7f, 0xc13a, 0x21, 0 + .dw 0x2ac0, 0xc13a, 0x2aff, 0xc13a, 0x21, 0 + .dw 0x2b40, 0xc13a, 0x2b7f, 0xc13a, 0x21, 0 + .dw 0x2bc0, 0xc13a, 0x2bff, 0xc13a, 0x21, 0 + .dw 0x2c40, 0xc13a, 0x2c7f, 0xc13a, 0x21, 0 + .dw 0x2cc0, 0xc13a, 0x2cff, 0xc13a, 0x21, 0 + .dw 0x2d40, 0xc13a, 0x2d7f, 0xc13a, 0x21, 0 + .dw 0x2dc0, 0xc13a, 0x2dff, 0xc13a, 0x21, 0 + .dw 0x2e40, 0xc13a, 0x2e7f, 0xc13a, 0x21, 0 + .dw 0x2ec0, 0xc13a, 0x2eff, 0xc13a, 0x21, 0 + .dw 0x2f40, 0xc13a, 0x2f7f, 0xc13a, 0x21, 0 + .dw 0x2fc0, 0xc13a, 0x2fff, 0xc13a, 0x21, 0 + .dw 0x3040, 0xc13a, 0x307f, 0xc13a, 0x21, 0 + .dw 0x30c0, 0xc13a, 0x30ff, 0xc13a, 0x21, 0 + .dw 0x3140, 0xc13a, 0x317f, 0xc13a, 0x21, 0 + .dw 0x31c0, 0xc13a, 0x31ff, 0xc13a, 0x21, 0 + .dw 0x3240, 0xc13a, 0x327f, 0xc13a, 0x21, 0 + .dw 0x32c0, 0xc13a, 0x32ff, 0xc13a, 0x21, 0 + .dw 0x3340, 0xc13a, 0x337f, 0xc13a, 0x21, 0 + .dw 0x33c0, 0xc13a, 0x33ff, 0xc13a, 0x21, 0 + .dw 0x3440, 0xc13a, 0x347f, 0xc13a, 0x21, 0 + .dw 0x34c0, 0xc13a, 0x34ff, 0xc13a, 0x21, 0 + .dw 0x3540, 0xc13a, 0x357f, 0xc13a, 0x21, 0 + .dw 0x35c0, 0xc13a, 0x35ff, 0xc13a, 0x21, 0 + .dw 0x3640, 0xc13a, 0x367f, 0xc13a, 0x21, 0 + .dw 0x36c0, 0xc13a, 0x36ff, 0xc13a, 0x21, 0 + .dw 0x3740, 0xc13a, 0x377f, 0xc13a, 0x21, 0 + .dw 0x37c0, 0xc13a, 0x37ff, 0xc13a, 0x21, 0 + .dw 0x3840, 0xc13a, 0x387f, 0xc13a, 0x21, 0 + .dw 0x38c0, 0xc13a, 0x38ff, 0xc13a, 0x21, 0 + .dw 0x3940, 0xc13a, 0x397f, 0xc13a, 0x21, 0 + .dw 0x39c0, 0xc13a, 0x5fff, 0xc13a, 0x21, 0 + .dw 0x6040, 0xc13a, 0x607f, 0xc13a, 0x21, 0 + .dw 0x60c0, 0xc13a, 0x60ff, 0xc13a, 0x21, 0 + .dw 0x6140, 0xc13a, 0x617f, 0xc13a, 0x21, 0 + .dw 0x61c0, 0xc13a, 0x61ff, 0xc13a, 0x21, 0 + .dw 0x6240, 0xc13a, 0x627f, 0xc13a, 0x21, 0 + .dw 0x62c0, 0xc13a, 0x62ff, 0xc13a, 0x21, 0 + .dw 0x6340, 0xc13a, 0x637f, 0xc13a, 0x21, 0 + .dw 0x63c0, 0xc13a, 0x63ff, 0xc13a, 0x21, 0 + .dw 0x6440, 0xc13a, 0x647f, 0xc13a, 0x21, 0 + .dw 0x64c0, 0xc13a, 0x64ff, 0xc13a, 0x21, 0 + .dw 0x6540, 0xc13a, 0x657f, 0xc13a, 0x21, 0 + .dw 0x65c0, 0xc13a, 0x65ff, 0xc13a, 0x21, 0 + .dw 0x6640, 0xc13a, 0x667f, 0xc13a, 0x21, 0 + .dw 0x66c0, 0xc13a, 0x66ff, 0xc13a, 0x21, 0 + .dw 0x6740, 0xc13a, 0x677f, 0xc13a, 0x21, 0 + .dw 0x67c0, 0xc13a, 0x67ff, 0xc13a, 0x21, 0 + .dw 0x6840, 0xc13a, 0x687f, 0xc13a, 0x21, 0 + .dw 0x68c0, 0xc13a, 0x68ff, 0xc13a, 0x21, 0 + .dw 0x6940, 0xc13a, 0x697f, 0xc13a, 0x21, 0 + .dw 0x69c0, 0xc13a, 0x69ff, 0xc13a, 0x21, 0 + .dw 0x6a40, 0xc13a, 0x6a7f, 0xc13a, 0x21, 0 + .dw 0x6ac0, 0xc13a, 0x6aff, 0xc13a, 0x21, 0 + .dw 0x6b40, 0xc13a, 0x6b7f, 0xc13a, 0x21, 0 + .dw 0x6bc0, 0xc13a, 0x6bff, 0xc13a, 0x21, 0 + .dw 0x6c40, 0xc13a, 0x6c7f, 0xc13a, 0x21, 0 + .dw 0x6cc0, 0xc13a, 0x6cff, 0xc13a, 0x21, 0 + .dw 0x6d40, 0xc13a, 0x6d7f, 0xc13a, 0x21, 0 + .dw 0x6dc0, 0xc13a, 0x6dff, 0xc13a, 0x21, 0 + .dw 0x6e40, 0xc13a, 0x6e7f, 0xc13a, 0x21, 0 + .dw 0x6ec0, 0xc13a, 0x6eff, 0xc13a, 0x21, 0 + .dw 0x6f40, 0xc13a, 0x6f7f, 0xc13a, 0x21, 0 + .dw 0x6fc0, 0xc13a, 0x6fff, 0xc13a, 0x21, 0 + .dw 0x7040, 0xc13a, 0x707f, 0xc13a, 0x21, 0 + .dw 0x70c0, 0xc13a, 0x70ff, 0xc13a, 0x21, 0 + .dw 0x7140, 0xc13a, 0x717f, 0xc13a, 0x21, 0 + .dw 0x71c0, 0xc13a, 0x71ff, 0xc13a, 0x21, 0 + .dw 0x7240, 0xc13a, 0x727f, 0xc13a, 0x21, 0 + .dw 0x72c0, 0xc13a, 0x72ff, 0xc13a, 0x21, 0 + .dw 0x7340, 0xc13a, 0x737f, 0xc13a, 0x21, 0 + .dw 0x73c0, 0xc13a, 0x73ff, 0xc13a, 0x21, 0 + .dw 0x7440, 0xc13a, 0x747f, 0xc13a, 0x21, 0 + .dw 0x74c0, 0xc13a, 0x74ff, 0xc13a, 0x21, 0 + .dw 0x7540, 0xc13a, 0x757f, 0xc13a, 0x21, 0 + .dw 0x75c0, 0xc13a, 0x75ff, 0xc13a, 0x21, 0 + .dw 0x7640, 0xc13a, 0x767f, 0xc13a, 0x21, 0 + .dw 0x76c0, 0xc13a, 0x76ff, 0xc13a, 0x21, 0 + .dw 0x7740, 0xc13a, 0x777f, 0xc13a, 0x21, 0 + .dw 0x77c0, 0xc13a, 0x77ff, 0xc13a, 0x21, 0 + .dw 0x7840, 0xc13a, 0x787f, 0xc13a, 0x21, 0 + .dw 0x78c0, 0xc13a, 0x78ff, 0xc13a, 0x21, 0 + .dw 0x7940, 0xc13a, 0x797f, 0xc13a, 0x21, 0 + .dw 0x79c0, 0xc13a, 0x9fff, 0xc13a, 0x21, 0 + .dw 0xa040, 0xc13a, 0xa07f, 0xc13a, 0x21, 0 + .dw 0xa0c0, 0xc13a, 0xa0ff, 0xc13a, 0x21, 0 + .dw 0xa140, 0xc13a, 0xa17f, 0xc13a, 0x21, 0 + .dw 0xa1c0, 0xc13a, 0xa1ff, 0xc13a, 0x21, 0 + .dw 0xa240, 0xc13a, 0xa27f, 0xc13a, 0x21, 0 + .dw 0xa2c0, 0xc13a, 0xa2ff, 0xc13a, 0x21, 0 + .dw 0xa340, 0xc13a, 0xa37f, 0xc13a, 0x21, 0 + .dw 0xa3c0, 0xc13a, 0xa3ff, 0xc13a, 0x21, 0 + .dw 0xa440, 0xc13a, 0xa47f, 0xc13a, 0x21, 0 + .dw 0xa4c0, 0xc13a, 0xa4ff, 0xc13a, 0x21, 0 + .dw 0xa540, 0xc13a, 0xa57f, 0xc13a, 0x21, 0 + .dw 0xa5c0, 0xc13a, 0xa5ff, 0xc13a, 0x21, 0 + .dw 0xa640, 0xc13a, 0xa67f, 0xc13a, 0x21, 0 + .dw 0xa6c0, 0xc13a, 0xa6ff, 0xc13a, 0x21, 0 + .dw 0xa740, 0xc13a, 0xa77f, 0xc13a, 0x21, 0 + .dw 0xa7c0, 0xc13a, 0xa7ff, 0xc13a, 0x21, 0 + .dw 0xa840, 0xc13a, 0xa87f, 0xc13a, 0x21, 0 + .dw 0xa8c0, 0xc13a, 0xa8ff, 0xc13a, 0x21, 0 + .dw 0xa940, 0xc13a, 0xa97f, 0xc13a, 0x21, 0 + .dw 0xa9c0, 0xc13a, 0xa9ff, 0xc13a, 0x21, 0 + .dw 0xaa40, 0xc13a, 0xaa7f, 0xc13a, 0x21, 0 + .dw 0xaac0, 0xc13a, 0xaaff, 0xc13a, 0x21, 0 + .dw 0xab40, 0xc13a, 0xab7f, 0xc13a, 0x21, 0 + .dw 0xabc0, 0xc13a, 0xabff, 0xc13a, 0x21, 0 + .dw 0xac40, 0xc13a, 0xac7f, 0xc13a, 0x21, 0 + .dw 0xacc0, 0xc13a, 0xacff, 0xc13a, 0x21, 0 + .dw 0xad40, 0xc13a, 0xad7f, 0xc13a, 0x21, 0 + .dw 0xadc0, 0xc13a, 0xadff, 0xc13a, 0x21, 0 + .dw 0xae40, 0xc13a, 0xae7f, 0xc13a, 0x21, 0 + .dw 0xaec0, 0xc13a, 0xaeff, 0xc13a, 0x21, 0 + .dw 0xaf40, 0xc13a, 0xaf7f, 0xc13a, 0x21, 0 + .dw 0xafc0, 0xc13a, 0xafff, 0xc13a, 0x21, 0 + .dw 0xb040, 0xc13a, 0xb07f, 0xc13a, 0x21, 0 + .dw 0xb0c0, 0xc13a, 0xb0ff, 0xc13a, 0x21, 0 + .dw 0xb140, 0xc13a, 0xb17f, 0xc13a, 0x21, 0 + .dw 0xb1c0, 0xc13a, 0xb1ff, 0xc13a, 0x21, 0 + .dw 0xb240, 0xc13a, 0xb27f, 0xc13a, 0x21, 0 + .dw 0xb2c0, 0xc13a, 0xb2ff, 0xc13a, 0x21, 0 + .dw 0xb340, 0xc13a, 0xb37f, 0xc13a, 0x21, 0 + .dw 0xb3c0, 0xc13a, 0xb3ff, 0xc13a, 0x21, 0 + .dw 0xb440, 0xc13a, 0xb47f, 0xc13a, 0x21, 0 + .dw 0xb4c0, 0xc13a, 0xb4ff, 0xc13a, 0x21, 0 + .dw 0xb540, 0xc13a, 0xb57f, 0xc13a, 0x21, 0 + .dw 0xb5c0, 0xc13a, 0xb5ff, 0xc13a, 0x21, 0 + .dw 0xb640, 0xc13a, 0xb67f, 0xc13a, 0x21, 0 + .dw 0xb6c0, 0xc13a, 0xb6ff, 0xc13a, 0x21, 0 + .dw 0xb740, 0xc13a, 0xb77f, 0xc13a, 0x21, 0 + .dw 0xb7c0, 0xc13a, 0xb7ff, 0xc13a, 0x21, 0 + .dw 0xb840, 0xc13a, 0xb87f, 0xc13a, 0x21, 0 + .dw 0xb8c0, 0xc13a, 0xb8ff, 0xc13a, 0x21, 0 + .dw 0xb940, 0xc13a, 0xb97f, 0xc13a, 0x21, 0 + .dw 0xb9c0, 0xc13a, 0xdfff, 0xc13a, 0x21, 0 + .dw 0xe040, 0xc13a, 0xe07f, 0xc13a, 0x21, 0 + .dw 0xe0c0, 0xc13a, 0xe0ff, 0xc13a, 0x21, 0 + .dw 0xe140, 0xc13a, 0xe17f, 0xc13a, 0x21, 0 + .dw 0xe1c0, 0xc13a, 0xe1ff, 0xc13a, 0x21, 0 + .dw 0xe240, 0xc13a, 0xe27f, 0xc13a, 0x21, 0 + .dw 0xe2c0, 0xc13a, 0xe2ff, 0xc13a, 0x21, 0 + .dw 0xe340, 0xc13a, 0xe37f, 0xc13a, 0x21, 0 + .dw 0xe3c0, 0xc13a, 0xe3ff, 0xc13a, 0x21, 0 + .dw 0xe440, 0xc13a, 0xe47f, 0xc13a, 0x21, 0 + .dw 0xe4c0, 0xc13a, 0xe4ff, 0xc13a, 0x21, 0 + .dw 0xe540, 0xc13a, 0xe57f, 0xc13a, 0x21, 0 + .dw 0xe5c0, 0xc13a, 0xe5ff, 0xc13a, 0x21, 0 + .dw 0xe640, 0xc13a, 0xe67f, 0xc13a, 0x21, 0 + .dw 0xe6c0, 0xc13a, 0xe6ff, 0xc13a, 0x21, 0 + .dw 0xe740, 0xc13a, 0xe77f, 0xc13a, 0x21, 0 + .dw 0xe7c0, 0xc13a, 0xe7ff, 0xc13a, 0x21, 0 + .dw 0xe840, 0xc13a, 0xe87f, 0xc13a, 0x21, 0 + .dw 0xe8c0, 0xc13a, 0xe8ff, 0xc13a, 0x21, 0 + .dw 0xe940, 0xc13a, 0xe97f, 0xc13a, 0x21, 0 + .dw 0xe9c0, 0xc13a, 0xe9ff, 0xc13a, 0x21, 0 + .dw 0xea40, 0xc13a, 0xea7f, 0xc13a, 0x21, 0 + .dw 0xeac0, 0xc13a, 0xeaff, 0xc13a, 0x21, 0 + .dw 0xeb40, 0xc13a, 0xeb7f, 0xc13a, 0x21, 0 + .dw 0xebc0, 0xc13a, 0xebff, 0xc13a, 0x21, 0 + .dw 0xec40, 0xc13a, 0xec7f, 0xc13a, 0x21, 0 + .dw 0xecc0, 0xc13a, 0xecff, 0xc13a, 0x21, 0 + .dw 0xed40, 0xc13a, 0xed7f, 0xc13a, 0x21, 0 + .dw 0xedc0, 0xc13a, 0xedff, 0xc13a, 0x21, 0 + .dw 0xee40, 0xc13a, 0xee7f, 0xc13a, 0x21, 0 + .dw 0xeec0, 0xc13a, 0xeeff, 0xc13a, 0x21, 0 + .dw 0xef40, 0xc13a, 0xef7f, 0xc13a, 0x21, 0 + .dw 0xefc0, 0xc13a, 0xefff, 0xc13a, 0x21, 0 + .dw 0xf040, 0xc13a, 0xf07f, 0xc13a, 0x21, 0 + .dw 0xf0c0, 0xc13a, 0xf0ff, 0xc13a, 0x21, 0 + .dw 0xf140, 0xc13a, 0xf17f, 0xc13a, 0x21, 0 + .dw 0xf1c0, 0xc13a, 0xf1ff, 0xc13a, 0x21, 0 + .dw 0xf240, 0xc13a, 0xf27f, 0xc13a, 0x21, 0 + .dw 0xf2c0, 0xc13a, 0xf2ff, 0xc13a, 0x21, 0 + .dw 0xf340, 0xc13a, 0xf37f, 0xc13a, 0x21, 0 + .dw 0xf3c0, 0xc13a, 0xf3ff, 0xc13a, 0x21, 0 + .dw 0xf440, 0xc13a, 0xf47f, 0xc13a, 0x21, 0 + .dw 0xf4c0, 0xc13a, 0xf4ff, 0xc13a, 0x21, 0 + .dw 0xf540, 0xc13a, 0xf57f, 0xc13a, 0x21, 0 + .dw 0xf5c0, 0xc13a, 0xf5ff, 0xc13a, 0x21, 0 + .dw 0xf640, 0xc13a, 0xf67f, 0xc13a, 0x21, 0 + .dw 0xf6c0, 0xc13a, 0xf6ff, 0xc13a, 0x21, 0 + .dw 0xf740, 0xc13a, 0xf77f, 0xc13a, 0x21, 0 + .dw 0xf7c0, 0xc13a, 0xf7ff, 0xc13a, 0x21, 0 + .dw 0xf840, 0xc13a, 0xf87f, 0xc13a, 0x21, 0 + .dw 0xf8c0, 0xc13a, 0xf8ff, 0xc13a, 0x21, 0 + .dw 0xf940, 0xc13a, 0xf97f, 0xc13a, 0x21, 0 + .dw 0xf9c0, 0xc13a, 0xffff, 0xc13b, 0x21, 0 + .dw 0x0040, 0xc13c, 0x007f, 0xc13c, 0x21, 0 + .dw 0x00c0, 0xc13c, 0x00ff, 0xc13c, 0x21, 0 + .dw 0x0140, 0xc13c, 0x017f, 0xc13c, 0x21, 0 + .dw 0x01c0, 0xc13c, 0x01ff, 0xc13c, 0x21, 0 + .dw 0x0240, 0xc13c, 0x027f, 0xc13c, 0x21, 0 + .dw 0x02c0, 0xc13c, 0x02ff, 0xc13c, 0x21, 0 + .dw 0x0340, 0xc13c, 0x037f, 0xc13c, 0x21, 0 + .dw 0x03c0, 0xc13c, 0x03ff, 0xc13c, 0x21, 0 + .dw 0x0440, 0xc13c, 0x047f, 0xc13c, 0x21, 0 + .dw 0x04c0, 0xc13c, 0x04ff, 0xc13c, 0x21, 0 + .dw 0x0540, 0xc13c, 0x057f, 0xc13c, 0x21, 0 + .dw 0x05c0, 0xc13c, 0x05ff, 0xc13c, 0x21, 0 + .dw 0x0640, 0xc13c, 0x067f, 0xc13c, 0x21, 0 + .dw 0x06c0, 0xc13c, 0x06ff, 0xc13c, 0x21, 0 + .dw 0x0740, 0xc13c, 0x077f, 0xc13c, 0x21, 0 + .dw 0x07c0, 0xc13c, 0x07ff, 0xc13c, 0x21, 0 + .dw 0x0840, 0xc13c, 0x087f, 0xc13c, 0x21, 0 + .dw 0x08c0, 0xc13c, 0x08ff, 0xc13c, 0x21, 0 + .dw 0x0940, 0xc13c, 0x097f, 0xc13c, 0x21, 0 + .dw 0x09c0, 0xc13c, 0x09ff, 0xc13c, 0x21, 0 + .dw 0x0a40, 0xc13c, 0x0a7f, 0xc13c, 0x21, 0 + .dw 0x0ac0, 0xc13c, 0x0aff, 0xc13c, 0x21, 0 + .dw 0x0b40, 0xc13c, 0x0b7f, 0xc13c, 0x21, 0 + .dw 0x0bc0, 0xc13c, 0x0bff, 0xc13c, 0x21, 0 + .dw 0x0c40, 0xc13c, 0x0c7f, 0xc13c, 0x21, 0 + .dw 0x0cc0, 0xc13c, 0x0cff, 0xc13c, 0x21, 0 + .dw 0x0d40, 0xc13c, 0x0d7f, 0xc13c, 0x21, 0 + .dw 0x0dc0, 0xc13c, 0x0dff, 0xc13c, 0x21, 0 + .dw 0x0e40, 0xc13c, 0x0e7f, 0xc13c, 0x21, 0 + .dw 0x0ec0, 0xc13c, 0x0eff, 0xc13c, 0x21, 0 + .dw 0x0f40, 0xc13c, 0x0f7f, 0xc13c, 0x21, 0 + .dw 0x0fc0, 0xc13c, 0x0fff, 0xc13c, 0x21, 0 + .dw 0x1040, 0xc13c, 0x107f, 0xc13c, 0x21, 0 + .dw 0x10c0, 0xc13c, 0x10ff, 0xc13c, 0x21, 0 + .dw 0x1140, 0xc13c, 0x117f, 0xc13c, 0x21, 0 + .dw 0x11c0, 0xc13c, 0x11ff, 0xc13c, 0x21, 0 + .dw 0x1240, 0xc13c, 0x127f, 0xc13c, 0x21, 0 + .dw 0x12c0, 0xc13c, 0x12ff, 0xc13c, 0x21, 0 + .dw 0x1340, 0xc13c, 0x137f, 0xc13c, 0x21, 0 + .dw 0x13c0, 0xc13c, 0x13ff, 0xc13c, 0x21, 0 + .dw 0x1440, 0xc13c, 0x147f, 0xc13c, 0x21, 0 + .dw 0x14c0, 0xc13c, 0x14ff, 0xc13c, 0x21, 0 + .dw 0x1540, 0xc13c, 0x157f, 0xc13c, 0x21, 0 + .dw 0x15c0, 0xc13c, 0x15ff, 0xc13c, 0x21, 0 + .dw 0x1640, 0xc13c, 0x167f, 0xc13c, 0x21, 0 + .dw 0x16c0, 0xc13c, 0x16ff, 0xc13c, 0x21, 0 + .dw 0x1740, 0xc13c, 0x177f, 0xc13c, 0x21, 0 + .dw 0x17c0, 0xc13c, 0x17ff, 0xc13c, 0x21, 0 + .dw 0x1840, 0xc13c, 0x187f, 0xc13c, 0x21, 0 + .dw 0x18c0, 0xc13c, 0x18ff, 0xc13c, 0x21, 0 + .dw 0x1940, 0xc13c, 0x197f, 0xc13c, 0x21, 0 + .dw 0x19c0, 0xc13c, 0x1fff, 0xc13c, 0x21, 0 + .dw 0x2040, 0xc13c, 0x207f, 0xc13c, 0x21, 0 + .dw 0x20c0, 0xc13c, 0x20ff, 0xc13c, 0x21, 0 + .dw 0x2140, 0xc13c, 0x217f, 0xc13c, 0x21, 0 + .dw 0x21c0, 0xc13c, 0x21ff, 0xc13c, 0x21, 0 + .dw 0x2240, 0xc13c, 0x227f, 0xc13c, 0x21, 0 + .dw 0x22c0, 0xc13c, 0x22ff, 0xc13c, 0x21, 0 + .dw 0x2340, 0xc13c, 0x237f, 0xc13c, 0x21, 0 + .dw 0x23c0, 0xc13c, 0x23ff, 0xc13c, 0x21, 0 + .dw 0x2440, 0xc13c, 0x247f, 0xc13c, 0x21, 0 + .dw 0x24c0, 0xc13c, 0x24ff, 0xc13c, 0x21, 0 + .dw 0x2540, 0xc13c, 0x257f, 0xc13c, 0x21, 0 + .dw 0x25c0, 0xc13c, 0x25ff, 0xc13c, 0x21, 0 + .dw 0x2640, 0xc13c, 0x267f, 0xc13c, 0x21, 0 + .dw 0x26c0, 0xc13c, 0x26ff, 0xc13c, 0x21, 0 + .dw 0x2740, 0xc13c, 0x277f, 0xc13c, 0x21, 0 + .dw 0x27c0, 0xc13c, 0x27ff, 0xc13c, 0x21, 0 + .dw 0x2840, 0xc13c, 0x287f, 0xc13c, 0x21, 0 + .dw 0x28c0, 0xc13c, 0x28ff, 0xc13c, 0x21, 0 + .dw 0x2940, 0xc13c, 0x297f, 0xc13c, 0x21, 0 + .dw 0x29c0, 0xc13c, 0x29ff, 0xc13c, 0x21, 0 + .dw 0x2a40, 0xc13c, 0x2a7f, 0xc13c, 0x21, 0 + .dw 0x2ac0, 0xc13c, 0x2aff, 0xc13c, 0x21, 0 + .dw 0x2b40, 0xc13c, 0x2b7f, 0xc13c, 0x21, 0 + .dw 0x2bc0, 0xc13c, 0x2bff, 0xc13c, 0x21, 0 + .dw 0x2c40, 0xc13c, 0x2c7f, 0xc13c, 0x21, 0 + .dw 0x2cc0, 0xc13c, 0x2cff, 0xc13c, 0x21, 0 + .dw 0x2d40, 0xc13c, 0x2d7f, 0xc13c, 0x21, 0 + .dw 0x2dc0, 0xc13c, 0x2dff, 0xc13c, 0x21, 0 + .dw 0x2e40, 0xc13c, 0x2e7f, 0xc13c, 0x21, 0 + .dw 0x2ec0, 0xc13c, 0x2eff, 0xc13c, 0x21, 0 + .dw 0x2f40, 0xc13c, 0x2f7f, 0xc13c, 0x21, 0 + .dw 0x2fc0, 0xc13c, 0x2fff, 0xc13c, 0x21, 0 + .dw 0x3040, 0xc13c, 0x307f, 0xc13c, 0x21, 0 + .dw 0x30c0, 0xc13c, 0x30ff, 0xc13c, 0x21, 0 + .dw 0x3140, 0xc13c, 0x317f, 0xc13c, 0x21, 0 + .dw 0x31c0, 0xc13c, 0x31ff, 0xc13c, 0x21, 0 + .dw 0x3240, 0xc13c, 0x327f, 0xc13c, 0x21, 0 + .dw 0x32c0, 0xc13c, 0x32ff, 0xc13c, 0x21, 0 + .dw 0x3340, 0xc13c, 0x337f, 0xc13c, 0x21, 0 + .dw 0x33c0, 0xc13c, 0x33ff, 0xc13c, 0x21, 0 + .dw 0x3440, 0xc13c, 0x347f, 0xc13c, 0x21, 0 + .dw 0x34c0, 0xc13c, 0x34ff, 0xc13c, 0x21, 0 + .dw 0x3540, 0xc13c, 0x357f, 0xc13c, 0x21, 0 + .dw 0x35c0, 0xc13c, 0x35ff, 0xc13c, 0x21, 0 + .dw 0x3640, 0xc13c, 0x367f, 0xc13c, 0x21, 0 + .dw 0x36c0, 0xc13c, 0x36ff, 0xc13c, 0x21, 0 + .dw 0x3740, 0xc13c, 0x377f, 0xc13c, 0x21, 0 + .dw 0x37c0, 0xc13c, 0x37ff, 0xc13c, 0x21, 0 + .dw 0x3840, 0xc13c, 0x387f, 0xc13c, 0x21, 0 + .dw 0x38c0, 0xc13c, 0x38ff, 0xc13c, 0x21, 0 + .dw 0x3940, 0xc13c, 0x397f, 0xc13c, 0x21, 0 + .dw 0x39c0, 0xc13c, 0x3fff, 0xc13c, 0x21, 0 + .dw 0x4040, 0xc13c, 0x407f, 0xc13c, 0x21, 0 + .dw 0x40c0, 0xc13c, 0x40ff, 0xc13c, 0x21, 0 + .dw 0x4140, 0xc13c, 0x417f, 0xc13c, 0x21, 0 + .dw 0x41c0, 0xc13c, 0x41ff, 0xc13c, 0x21, 0 + .dw 0x4240, 0xc13c, 0x427f, 0xc13c, 0x21, 0 + .dw 0x42c0, 0xc13c, 0x42ff, 0xc13c, 0x21, 0 + .dw 0x4340, 0xc13c, 0x437f, 0xc13c, 0x21, 0 + .dw 0x43c0, 0xc13c, 0x43ff, 0xc13c, 0x21, 0 + .dw 0x4440, 0xc13c, 0x447f, 0xc13c, 0x21, 0 + .dw 0x44c0, 0xc13c, 0x44ff, 0xc13c, 0x21, 0 + .dw 0x4540, 0xc13c, 0x457f, 0xc13c, 0x21, 0 + .dw 0x45c0, 0xc13c, 0x45ff, 0xc13c, 0x21, 0 + .dw 0x4640, 0xc13c, 0x467f, 0xc13c, 0x21, 0 + .dw 0x46c0, 0xc13c, 0x46ff, 0xc13c, 0x21, 0 + .dw 0x4740, 0xc13c, 0x477f, 0xc13c, 0x21, 0 + .dw 0x47c0, 0xc13c, 0x47ff, 0xc13c, 0x21, 0 + .dw 0x4840, 0xc13c, 0x487f, 0xc13c, 0x21, 0 + .dw 0x48c0, 0xc13c, 0x48ff, 0xc13c, 0x21, 0 + .dw 0x4940, 0xc13c, 0x497f, 0xc13c, 0x21, 0 + .dw 0x49c0, 0xc13c, 0x49ff, 0xc13c, 0x21, 0 + .dw 0x4a40, 0xc13c, 0x4a7f, 0xc13c, 0x21, 0 + .dw 0x4ac0, 0xc13c, 0x4aff, 0xc13c, 0x21, 0 + .dw 0x4b40, 0xc13c, 0x4b7f, 0xc13c, 0x21, 0 + .dw 0x4bc0, 0xc13c, 0x4bff, 0xc13c, 0x21, 0 + .dw 0x4c40, 0xc13c, 0x4c7f, 0xc13c, 0x21, 0 + .dw 0x4cc0, 0xc13c, 0x4cff, 0xc13c, 0x21, 0 + .dw 0x4d40, 0xc13c, 0x4d7f, 0xc13c, 0x21, 0 + .dw 0x4dc0, 0xc13c, 0x4dff, 0xc13c, 0x21, 0 + .dw 0x4e40, 0xc13c, 0x4e7f, 0xc13c, 0x21, 0 + .dw 0x4ec0, 0xc13c, 0x4eff, 0xc13c, 0x21, 0 + .dw 0x4f40, 0xc13c, 0x4f7f, 0xc13c, 0x21, 0 + .dw 0x4fc0, 0xc13c, 0x4fff, 0xc13c, 0x21, 0 + .dw 0x5040, 0xc13c, 0x507f, 0xc13c, 0x21, 0 + .dw 0x50c0, 0xc13c, 0x50ff, 0xc13c, 0x21, 0 + .dw 0x5140, 0xc13c, 0x517f, 0xc13c, 0x21, 0 + .dw 0x51c0, 0xc13c, 0x51ff, 0xc13c, 0x21, 0 + .dw 0x5240, 0xc13c, 0x527f, 0xc13c, 0x21, 0 + .dw 0x52c0, 0xc13c, 0x52ff, 0xc13c, 0x21, 0 + .dw 0x5340, 0xc13c, 0x537f, 0xc13c, 0x21, 0 + .dw 0x53c0, 0xc13c, 0x53ff, 0xc13c, 0x21, 0 + .dw 0x5440, 0xc13c, 0x547f, 0xc13c, 0x21, 0 + .dw 0x54c0, 0xc13c, 0x54ff, 0xc13c, 0x21, 0 + .dw 0x5540, 0xc13c, 0x557f, 0xc13c, 0x21, 0 + .dw 0x55c0, 0xc13c, 0x55ff, 0xc13c, 0x21, 0 + .dw 0x5640, 0xc13c, 0x567f, 0xc13c, 0x21, 0 + .dw 0x56c0, 0xc13c, 0x56ff, 0xc13c, 0x21, 0 + .dw 0x5740, 0xc13c, 0x577f, 0xc13c, 0x21, 0 + .dw 0x57c0, 0xc13c, 0x57ff, 0xc13c, 0x21, 0 + .dw 0x5840, 0xc13c, 0x587f, 0xc13c, 0x21, 0 + .dw 0x58c0, 0xc13c, 0x58ff, 0xc13c, 0x21, 0 + .dw 0x5940, 0xc13c, 0x597f, 0xc13c, 0x21, 0 + .dw 0x59c0, 0xc13c, 0x5fff, 0xc13c, 0x21, 0 + .dw 0x6040, 0xc13c, 0x607f, 0xc13c, 0x21, 0 + .dw 0x60c0, 0xc13c, 0x60ff, 0xc13c, 0x21, 0 + .dw 0x6140, 0xc13c, 0x617f, 0xc13c, 0x21, 0 + .dw 0x61c0, 0xc13c, 0x61ff, 0xc13c, 0x21, 0 + .dw 0x6240, 0xc13c, 0x627f, 0xc13c, 0x21, 0 + .dw 0x62c0, 0xc13c, 0x62ff, 0xc13c, 0x21, 0 + .dw 0x6340, 0xc13c, 0x637f, 0xc13c, 0x21, 0 + .dw 0x63c0, 0xc13c, 0x63ff, 0xc13c, 0x21, 0 + .dw 0x6440, 0xc13c, 0x647f, 0xc13c, 0x21, 0 + .dw 0x64c0, 0xc13c, 0x64ff, 0xc13c, 0x21, 0 + .dw 0x6540, 0xc13c, 0x657f, 0xc13c, 0x21, 0 + .dw 0x65c0, 0xc13c, 0x65ff, 0xc13c, 0x21, 0 + .dw 0x6640, 0xc13c, 0x667f, 0xc13c, 0x21, 0 + .dw 0x66c0, 0xc13c, 0x66ff, 0xc13c, 0x21, 0 + .dw 0x6740, 0xc13c, 0x677f, 0xc13c, 0x21, 0 + .dw 0x67c0, 0xc13c, 0x67ff, 0xc13c, 0x21, 0 + .dw 0x6840, 0xc13c, 0x687f, 0xc13c, 0x21, 0 + .dw 0x68c0, 0xc13c, 0x68ff, 0xc13c, 0x21, 0 + .dw 0x6940, 0xc13c, 0x697f, 0xc13c, 0x21, 0 + .dw 0x69c0, 0xc13c, 0x69ff, 0xc13c, 0x21, 0 + .dw 0x6a40, 0xc13c, 0x6a7f, 0xc13c, 0x21, 0 + .dw 0x6ac0, 0xc13c, 0x6aff, 0xc13c, 0x21, 0 + .dw 0x6b40, 0xc13c, 0x6b7f, 0xc13c, 0x21, 0 + .dw 0x6bc0, 0xc13c, 0x6bff, 0xc13c, 0x21, 0 + .dw 0x6c40, 0xc13c, 0x6c7f, 0xc13c, 0x21, 0 + .dw 0x6cc0, 0xc13c, 0x6cff, 0xc13c, 0x21, 0 + .dw 0x6d40, 0xc13c, 0x6d7f, 0xc13c, 0x21, 0 + .dw 0x6dc0, 0xc13c, 0x6dff, 0xc13c, 0x21, 0 + .dw 0x6e40, 0xc13c, 0x6e7f, 0xc13c, 0x21, 0 + .dw 0x6ec0, 0xc13c, 0x6eff, 0xc13c, 0x21, 0 + .dw 0x6f40, 0xc13c, 0x6f7f, 0xc13c, 0x21, 0 + .dw 0x6fc0, 0xc13c, 0x6fff, 0xc13c, 0x21, 0 + .dw 0x7040, 0xc13c, 0x707f, 0xc13c, 0x21, 0 + .dw 0x70c0, 0xc13c, 0x70ff, 0xc13c, 0x21, 0 + .dw 0x7140, 0xc13c, 0x717f, 0xc13c, 0x21, 0 + .dw 0x71c0, 0xc13c, 0x71ff, 0xc13c, 0x21, 0 + .dw 0x7240, 0xc13c, 0x727f, 0xc13c, 0x21, 0 + .dw 0x72c0, 0xc13c, 0x72ff, 0xc13c, 0x21, 0 + .dw 0x7340, 0xc13c, 0x737f, 0xc13c, 0x21, 0 + .dw 0x73c0, 0xc13c, 0x73ff, 0xc13c, 0x21, 0 + .dw 0x7440, 0xc13c, 0x747f, 0xc13c, 0x21, 0 + .dw 0x74c0, 0xc13c, 0x74ff, 0xc13c, 0x21, 0 + .dw 0x7540, 0xc13c, 0x757f, 0xc13c, 0x21, 0 + .dw 0x75c0, 0xc13c, 0x75ff, 0xc13c, 0x21, 0 + .dw 0x7640, 0xc13c, 0x767f, 0xc13c, 0x21, 0 + .dw 0x76c0, 0xc13c, 0x76ff, 0xc13c, 0x21, 0 + .dw 0x7740, 0xc13c, 0x777f, 0xc13c, 0x21, 0 + .dw 0x77c0, 0xc13c, 0x77ff, 0xc13c, 0x21, 0 + .dw 0x7840, 0xc13c, 0x787f, 0xc13c, 0x21, 0 + .dw 0x78c0, 0xc13c, 0x78ff, 0xc13c, 0x21, 0 + .dw 0x7940, 0xc13c, 0x797f, 0xc13c, 0x21, 0 + .dw 0x79c0, 0xc13c, 0x7fff, 0xc13c, 0x21, 0 + .dw 0x8040, 0xc13c, 0x807f, 0xc13c, 0x21, 0 + .dw 0x80c0, 0xc13c, 0x80ff, 0xc13c, 0x21, 0 + .dw 0x8140, 0xc13c, 0x817f, 0xc13c, 0x21, 0 + .dw 0x81c0, 0xc13c, 0x81ff, 0xc13c, 0x21, 0 + .dw 0x8240, 0xc13c, 0x827f, 0xc13c, 0x21, 0 + .dw 0x82c0, 0xc13c, 0x82ff, 0xc13c, 0x21, 0 + .dw 0x8340, 0xc13c, 0x837f, 0xc13c, 0x21, 0 + .dw 0x83c0, 0xc13c, 0x83ff, 0xc13c, 0x21, 0 + .dw 0x8440, 0xc13c, 0x847f, 0xc13c, 0x21, 0 + .dw 0x84c0, 0xc13c, 0x84ff, 0xc13c, 0x21, 0 + .dw 0x8540, 0xc13c, 0x857f, 0xc13c, 0x21, 0 + .dw 0x85c0, 0xc13c, 0x85ff, 0xc13c, 0x21, 0 + .dw 0x8640, 0xc13c, 0x867f, 0xc13c, 0x21, 0 + .dw 0x86c0, 0xc13c, 0x86ff, 0xc13c, 0x21, 0 + .dw 0x8740, 0xc13c, 0x877f, 0xc13c, 0x21, 0 + .dw 0x87c0, 0xc13c, 0x87ff, 0xc13c, 0x21, 0 + .dw 0x8840, 0xc13c, 0x887f, 0xc13c, 0x21, 0 + .dw 0x88c0, 0xc13c, 0x88ff, 0xc13c, 0x21, 0 + .dw 0x8940, 0xc13c, 0x897f, 0xc13c, 0x21, 0 + .dw 0x89c0, 0xc13c, 0x89ff, 0xc13c, 0x21, 0 + .dw 0x8a40, 0xc13c, 0x8a7f, 0xc13c, 0x21, 0 + .dw 0x8ac0, 0xc13c, 0x8aff, 0xc13c, 0x21, 0 + .dw 0x8b40, 0xc13c, 0x8b7f, 0xc13c, 0x21, 0 + .dw 0x8bc0, 0xc13c, 0x8bff, 0xc13c, 0x21, 0 + .dw 0x8c40, 0xc13c, 0x8c7f, 0xc13c, 0x21, 0 + .dw 0x8cc0, 0xc13c, 0x8cff, 0xc13c, 0x21, 0 + .dw 0x8d40, 0xc13c, 0x8d7f, 0xc13c, 0x21, 0 + .dw 0x8dc0, 0xc13c, 0x8dff, 0xc13c, 0x21, 0 + .dw 0x8e40, 0xc13c, 0x8e7f, 0xc13c, 0x21, 0 + .dw 0x8ec0, 0xc13c, 0x8eff, 0xc13c, 0x21, 0 + .dw 0x8f40, 0xc13c, 0x8f7f, 0xc13c, 0x21, 0 + .dw 0x8fc0, 0xc13c, 0x8fff, 0xc13c, 0x21, 0 + .dw 0x9040, 0xc13c, 0x907f, 0xc13c, 0x21, 0 + .dw 0x90c0, 0xc13c, 0x90ff, 0xc13c, 0x21, 0 + .dw 0x9140, 0xc13c, 0x917f, 0xc13c, 0x21, 0 + .dw 0x91c0, 0xc13c, 0x91ff, 0xc13c, 0x21, 0 + .dw 0x9240, 0xc13c, 0x927f, 0xc13c, 0x21, 0 + .dw 0x92c0, 0xc13c, 0x92ff, 0xc13c, 0x21, 0 + .dw 0x9340, 0xc13c, 0x937f, 0xc13c, 0x21, 0 + .dw 0x93c0, 0xc13c, 0x93ff, 0xc13c, 0x21, 0 + .dw 0x9440, 0xc13c, 0x947f, 0xc13c, 0x21, 0 + .dw 0x94c0, 0xc13c, 0x94ff, 0xc13c, 0x21, 0 + .dw 0x9540, 0xc13c, 0x957f, 0xc13c, 0x21, 0 + .dw 0x95c0, 0xc13c, 0x95ff, 0xc13c, 0x21, 0 + .dw 0x9640, 0xc13c, 0x967f, 0xc13c, 0x21, 0 + .dw 0x96c0, 0xc13c, 0x96ff, 0xc13c, 0x21, 0 + .dw 0x9740, 0xc13c, 0x977f, 0xc13c, 0x21, 0 + .dw 0x97c0, 0xc13c, 0x97ff, 0xc13c, 0x21, 0 + .dw 0x9840, 0xc13c, 0x987f, 0xc13c, 0x21, 0 + .dw 0x98c0, 0xc13c, 0x98ff, 0xc13c, 0x21, 0 + .dw 0x9940, 0xc13c, 0x997f, 0xc13c, 0x21, 0 + .dw 0x99c0, 0xc13c, 0x9fff, 0xc13c, 0x21, 0 + .dw 0xa040, 0xc13c, 0xa07f, 0xc13c, 0x21, 0 + .dw 0xa0c0, 0xc13c, 0xa0ff, 0xc13c, 0x21, 0 + .dw 0xa140, 0xc13c, 0xa17f, 0xc13c, 0x21, 0 + .dw 0xa1c0, 0xc13c, 0xa1ff, 0xc13c, 0x21, 0 + .dw 0xa240, 0xc13c, 0xa27f, 0xc13c, 0x21, 0 + .dw 0xa2c0, 0xc13c, 0xa2ff, 0xc13c, 0x21, 0 + .dw 0xa340, 0xc13c, 0xa37f, 0xc13c, 0x21, 0 + .dw 0xa3c0, 0xc13c, 0xa3ff, 0xc13c, 0x21, 0 + .dw 0xa440, 0xc13c, 0xa47f, 0xc13c, 0x21, 0 + .dw 0xa4c0, 0xc13c, 0xa4ff, 0xc13c, 0x21, 0 + .dw 0xa540, 0xc13c, 0xa57f, 0xc13c, 0x21, 0 + .dw 0xa5c0, 0xc13c, 0xa5ff, 0xc13c, 0x21, 0 + .dw 0xa640, 0xc13c, 0xa67f, 0xc13c, 0x21, 0 + .dw 0xa6c0, 0xc13c, 0xa6ff, 0xc13c, 0x21, 0 + .dw 0xa740, 0xc13c, 0xa77f, 0xc13c, 0x21, 0 + .dw 0xa7c0, 0xc13c, 0xa7ff, 0xc13c, 0x21, 0 + .dw 0xa840, 0xc13c, 0xa87f, 0xc13c, 0x21, 0 + .dw 0xa8c0, 0xc13c, 0xa8ff, 0xc13c, 0x21, 0 + .dw 0xa940, 0xc13c, 0xa97f, 0xc13c, 0x21, 0 + .dw 0xa9c0, 0xc13c, 0xa9ff, 0xc13c, 0x21, 0 + .dw 0xaa40, 0xc13c, 0xaa7f, 0xc13c, 0x21, 0 + .dw 0xaac0, 0xc13c, 0xaaff, 0xc13c, 0x21, 0 + .dw 0xab40, 0xc13c, 0xab7f, 0xc13c, 0x21, 0 + .dw 0xabc0, 0xc13c, 0xabff, 0xc13c, 0x21, 0 + .dw 0xac40, 0xc13c, 0xac7f, 0xc13c, 0x21, 0 + .dw 0xacc0, 0xc13c, 0xacff, 0xc13c, 0x21, 0 + .dw 0xad40, 0xc13c, 0xad7f, 0xc13c, 0x21, 0 + .dw 0xadc0, 0xc13c, 0xadff, 0xc13c, 0x21, 0 + .dw 0xae40, 0xc13c, 0xae7f, 0xc13c, 0x21, 0 + .dw 0xaec0, 0xc13c, 0xaeff, 0xc13c, 0x21, 0 + .dw 0xaf40, 0xc13c, 0xaf7f, 0xc13c, 0x21, 0 + .dw 0xafc0, 0xc13c, 0xafff, 0xc13c, 0x21, 0 + .dw 0xb040, 0xc13c, 0xb07f, 0xc13c, 0x21, 0 + .dw 0xb0c0, 0xc13c, 0xb0ff, 0xc13c, 0x21, 0 + .dw 0xb140, 0xc13c, 0xb17f, 0xc13c, 0x21, 0 + .dw 0xb1c0, 0xc13c, 0xb1ff, 0xc13c, 0x21, 0 + .dw 0xb240, 0xc13c, 0xb27f, 0xc13c, 0x21, 0 + .dw 0xb2c0, 0xc13c, 0xb2ff, 0xc13c, 0x21, 0 + .dw 0xb340, 0xc13c, 0xb37f, 0xc13c, 0x21, 0 + .dw 0xb3c0, 0xc13c, 0xb3ff, 0xc13c, 0x21, 0 + .dw 0xb440, 0xc13c, 0xb47f, 0xc13c, 0x21, 0 + .dw 0xb4c0, 0xc13c, 0xb4ff, 0xc13c, 0x21, 0 + .dw 0xb540, 0xc13c, 0xb57f, 0xc13c, 0x21, 0 + .dw 0xb5c0, 0xc13c, 0xb5ff, 0xc13c, 0x21, 0 + .dw 0xb640, 0xc13c, 0xb67f, 0xc13c, 0x21, 0 + .dw 0xb6c0, 0xc13c, 0xb6ff, 0xc13c, 0x21, 0 + .dw 0xb740, 0xc13c, 0xb77f, 0xc13c, 0x21, 0 + .dw 0xb7c0, 0xc13c, 0xb7ff, 0xc13c, 0x21, 0 + .dw 0xb840, 0xc13c, 0xb87f, 0xc13c, 0x21, 0 + .dw 0xb8c0, 0xc13c, 0xb8ff, 0xc13c, 0x21, 0 + .dw 0xb940, 0xc13c, 0xb97f, 0xc13c, 0x21, 0 + .dw 0xb9c0, 0xc13c, 0xbfff, 0xc13c, 0x21, 0 + .dw 0xc040, 0xc13c, 0xc07f, 0xc13c, 0x21, 0 + .dw 0xc0c0, 0xc13c, 0xc0ff, 0xc13c, 0x21, 0 + .dw 0xc140, 0xc13c, 0xc17f, 0xc13c, 0x21, 0 + .dw 0xc1c0, 0xc13c, 0xc1ff, 0xc13c, 0x21, 0 + .dw 0xc240, 0xc13c, 0xc27f, 0xc13c, 0x21, 0 + .dw 0xc2c0, 0xc13c, 0xc2ff, 0xc13c, 0x21, 0 + .dw 0xc340, 0xc13c, 0xc37f, 0xc13c, 0x21, 0 + .dw 0xc3c0, 0xc13c, 0xc3ff, 0xc13c, 0x21, 0 + .dw 0xc440, 0xc13c, 0xc47f, 0xc13c, 0x21, 0 + .dw 0xc4c0, 0xc13c, 0xc4ff, 0xc13c, 0x21, 0 + .dw 0xc540, 0xc13c, 0xc57f, 0xc13c, 0x21, 0 + .dw 0xc5c0, 0xc13c, 0xc5ff, 0xc13c, 0x21, 0 + .dw 0xc640, 0xc13c, 0xc67f, 0xc13c, 0x21, 0 + .dw 0xc6c0, 0xc13c, 0xc6ff, 0xc13c, 0x21, 0 + .dw 0xc740, 0xc13c, 0xc77f, 0xc13c, 0x21, 0 + .dw 0xc7c0, 0xc13c, 0xc7ff, 0xc13c, 0x21, 0 + .dw 0xc840, 0xc13c, 0xc87f, 0xc13c, 0x21, 0 + .dw 0xc8c0, 0xc13c, 0xc8ff, 0xc13c, 0x21, 0 + .dw 0xc940, 0xc13c, 0xc97f, 0xc13c, 0x21, 0 + .dw 0xc9c0, 0xc13c, 0xc9ff, 0xc13c, 0x21, 0 + .dw 0xca40, 0xc13c, 0xca7f, 0xc13c, 0x21, 0 + .dw 0xcac0, 0xc13c, 0xcaff, 0xc13c, 0x21, 0 + .dw 0xcb40, 0xc13c, 0xcb7f, 0xc13c, 0x21, 0 + .dw 0xcbc0, 0xc13c, 0xcbff, 0xc13c, 0x21, 0 + .dw 0xcc40, 0xc13c, 0xcc7f, 0xc13c, 0x21, 0 + .dw 0xccc0, 0xc13c, 0xccff, 0xc13c, 0x21, 0 + .dw 0xcd40, 0xc13c, 0xcd7f, 0xc13c, 0x21, 0 + .dw 0xcdc0, 0xc13c, 0xcdff, 0xc13c, 0x21, 0 + .dw 0xce40, 0xc13c, 0xce7f, 0xc13c, 0x21, 0 + .dw 0xcec0, 0xc13c, 0xceff, 0xc13c, 0x21, 0 + .dw 0xcf40, 0xc13c, 0xcf7f, 0xc13c, 0x21, 0 + .dw 0xcfc0, 0xc13c, 0xcfff, 0xc13c, 0x21, 0 + .dw 0xd040, 0xc13c, 0xd07f, 0xc13c, 0x21, 0 + .dw 0xd0c0, 0xc13c, 0xd0ff, 0xc13c, 0x21, 0 + .dw 0xd140, 0xc13c, 0xd17f, 0xc13c, 0x21, 0 + .dw 0xd1c0, 0xc13c, 0xd1ff, 0xc13c, 0x21, 0 + .dw 0xd240, 0xc13c, 0xd27f, 0xc13c, 0x21, 0 + .dw 0xd2c0, 0xc13c, 0xd2ff, 0xc13c, 0x21, 0 + .dw 0xd340, 0xc13c, 0xd37f, 0xc13c, 0x21, 0 + .dw 0xd3c0, 0xc13c, 0xd3ff, 0xc13c, 0x21, 0 + .dw 0xd440, 0xc13c, 0xd47f, 0xc13c, 0x21, 0 + .dw 0xd4c0, 0xc13c, 0xd4ff, 0xc13c, 0x21, 0 + .dw 0xd540, 0xc13c, 0xd57f, 0xc13c, 0x21, 0 + .dw 0xd5c0, 0xc13c, 0xd5ff, 0xc13c, 0x21, 0 + .dw 0xd640, 0xc13c, 0xd67f, 0xc13c, 0x21, 0 + .dw 0xd6c0, 0xc13c, 0xd6ff, 0xc13c, 0x21, 0 + .dw 0xd740, 0xc13c, 0xd77f, 0xc13c, 0x21, 0 + .dw 0xd7c0, 0xc13c, 0xd7ff, 0xc13c, 0x21, 0 + .dw 0xd840, 0xc13c, 0xd87f, 0xc13c, 0x21, 0 + .dw 0xd8c0, 0xc13c, 0xd8ff, 0xc13c, 0x21, 0 + .dw 0xd940, 0xc13c, 0xd97f, 0xc13c, 0x21, 0 + .dw 0xd9c0, 0xc13c, 0xdfff, 0xc13c, 0x21, 0 + .dw 0xe040, 0xc13c, 0xe07f, 0xc13c, 0x21, 0 + .dw 0xe0c0, 0xc13c, 0xe0ff, 0xc13c, 0x21, 0 + .dw 0xe140, 0xc13c, 0xe17f, 0xc13c, 0x21, 0 + .dw 0xe1c0, 0xc13c, 0xe1ff, 0xc13c, 0x21, 0 + .dw 0xe240, 0xc13c, 0xe27f, 0xc13c, 0x21, 0 + .dw 0xe2c0, 0xc13c, 0xe2ff, 0xc13c, 0x21, 0 + .dw 0xe340, 0xc13c, 0xe37f, 0xc13c, 0x21, 0 + .dw 0xe3c0, 0xc13c, 0xe3ff, 0xc13c, 0x21, 0 + .dw 0xe440, 0xc13c, 0xe47f, 0xc13c, 0x21, 0 + .dw 0xe4c0, 0xc13c, 0xe4ff, 0xc13c, 0x21, 0 + .dw 0xe540, 0xc13c, 0xe57f, 0xc13c, 0x21, 0 + .dw 0xe5c0, 0xc13c, 0xe5ff, 0xc13c, 0x21, 0 + .dw 0xe640, 0xc13c, 0xe67f, 0xc13c, 0x21, 0 + .dw 0xe6c0, 0xc13c, 0xe6ff, 0xc13c, 0x21, 0 + .dw 0xe740, 0xc13c, 0xe77f, 0xc13c, 0x21, 0 + .dw 0xe7c0, 0xc13c, 0xe7ff, 0xc13c, 0x21, 0 + .dw 0xe840, 0xc13c, 0xe87f, 0xc13c, 0x21, 0 + .dw 0xe8c0, 0xc13c, 0xe8ff, 0xc13c, 0x21, 0 + .dw 0xe940, 0xc13c, 0xe97f, 0xc13c, 0x21, 0 + .dw 0xe9c0, 0xc13c, 0xe9ff, 0xc13c, 0x21, 0 + .dw 0xea40, 0xc13c, 0xea7f, 0xc13c, 0x21, 0 + .dw 0xeac0, 0xc13c, 0xeaff, 0xc13c, 0x21, 0 + .dw 0xeb40, 0xc13c, 0xeb7f, 0xc13c, 0x21, 0 + .dw 0xebc0, 0xc13c, 0xebff, 0xc13c, 0x21, 0 + .dw 0xec40, 0xc13c, 0xec7f, 0xc13c, 0x21, 0 + .dw 0xecc0, 0xc13c, 0xecff, 0xc13c, 0x21, 0 + .dw 0xed40, 0xc13c, 0xed7f, 0xc13c, 0x21, 0 + .dw 0xedc0, 0xc13c, 0xedff, 0xc13c, 0x21, 0 + .dw 0xee40, 0xc13c, 0xee7f, 0xc13c, 0x21, 0 + .dw 0xeec0, 0xc13c, 0xeeff, 0xc13c, 0x21, 0 + .dw 0xef40, 0xc13c, 0xef7f, 0xc13c, 0x21, 0 + .dw 0xefc0, 0xc13c, 0xefff, 0xc13c, 0x21, 0 + .dw 0xf040, 0xc13c, 0xf07f, 0xc13c, 0x21, 0 + .dw 0xf0c0, 0xc13c, 0xf0ff, 0xc13c, 0x21, 0 + .dw 0xf140, 0xc13c, 0xf17f, 0xc13c, 0x21, 0 + .dw 0xf1c0, 0xc13c, 0xf1ff, 0xc13c, 0x21, 0 + .dw 0xf240, 0xc13c, 0xf27f, 0xc13c, 0x21, 0 + .dw 0xf2c0, 0xc13c, 0xf2ff, 0xc13c, 0x21, 0 + .dw 0xf340, 0xc13c, 0xf37f, 0xc13c, 0x21, 0 + .dw 0xf3c0, 0xc13c, 0xf3ff, 0xc13c, 0x21, 0 + .dw 0xf440, 0xc13c, 0xf47f, 0xc13c, 0x21, 0 + .dw 0xf4c0, 0xc13c, 0xf4ff, 0xc13c, 0x21, 0 + .dw 0xf540, 0xc13c, 0xf57f, 0xc13c, 0x21, 0 + .dw 0xf5c0, 0xc13c, 0xf5ff, 0xc13c, 0x21, 0 + .dw 0xf640, 0xc13c, 0xf67f, 0xc13c, 0x21, 0 + .dw 0xf6c0, 0xc13c, 0xf6ff, 0xc13c, 0x21, 0 + .dw 0xf740, 0xc13c, 0xf77f, 0xc13c, 0x21, 0 + .dw 0xf7c0, 0xc13c, 0xf7ff, 0xc13c, 0x21, 0 + .dw 0xf840, 0xc13c, 0xf87f, 0xc13c, 0x21, 0 + .dw 0xf8c0, 0xc13c, 0xf8ff, 0xc13c, 0x21, 0 + .dw 0xf940, 0xc13c, 0xf97f, 0xc13c, 0x21, 0 + .dw 0xf9c0, 0xc13c, 0xffff, 0xc13c, 0x21, 0 + .dw 0x0040, 0xc13d, 0x007f, 0xc13d, 0x21, 0 + .dw 0x00c0, 0xc13d, 0x00ff, 0xc13d, 0x21, 0 + .dw 0x0140, 0xc13d, 0x017f, 0xc13d, 0x21, 0 + .dw 0x01c0, 0xc13d, 0x01ff, 0xc13d, 0x21, 0 + .dw 0x0240, 0xc13d, 0x027f, 0xc13d, 0x21, 0 + .dw 0x02c0, 0xc13d, 0x02ff, 0xc13d, 0x21, 0 + .dw 0x0340, 0xc13d, 0x037f, 0xc13d, 0x21, 0 + .dw 0x03c0, 0xc13d, 0x03ff, 0xc13d, 0x21, 0 + .dw 0x0440, 0xc13d, 0x047f, 0xc13d, 0x21, 0 + .dw 0x04c0, 0xc13d, 0x04ff, 0xc13d, 0x21, 0 + .dw 0x0540, 0xc13d, 0x057f, 0xc13d, 0x21, 0 + .dw 0x05c0, 0xc13d, 0x05ff, 0xc13d, 0x21, 0 + .dw 0x0640, 0xc13d, 0x067f, 0xc13d, 0x21, 0 + .dw 0x06c0, 0xc13d, 0x06ff, 0xc13d, 0x21, 0 + .dw 0x0740, 0xc13d, 0x077f, 0xc13d, 0x21, 0 + .dw 0x07c0, 0xc13d, 0x07ff, 0xc13d, 0x21, 0 + .dw 0x0840, 0xc13d, 0x087f, 0xc13d, 0x21, 0 + .dw 0x08c0, 0xc13d, 0x08ff, 0xc13d, 0x21, 0 + .dw 0x0940, 0xc13d, 0x097f, 0xc13d, 0x21, 0 + .dw 0x09c0, 0xc13d, 0x09ff, 0xc13d, 0x21, 0 + .dw 0x0a40, 0xc13d, 0x0a7f, 0xc13d, 0x21, 0 + .dw 0x0ac0, 0xc13d, 0x0aff, 0xc13d, 0x21, 0 + .dw 0x0b40, 0xc13d, 0x0b7f, 0xc13d, 0x21, 0 + .dw 0x0bc0, 0xc13d, 0x0bff, 0xc13d, 0x21, 0 + .dw 0x0c40, 0xc13d, 0x0c7f, 0xc13d, 0x21, 0 + .dw 0x0cc0, 0xc13d, 0x0cff, 0xc13d, 0x21, 0 + .dw 0x0d40, 0xc13d, 0x0d7f, 0xc13d, 0x21, 0 + .dw 0x0dc0, 0xc13d, 0x0dff, 0xc13d, 0x21, 0 + .dw 0x0e40, 0xc13d, 0x0e7f, 0xc13d, 0x21, 0 + .dw 0x0ec0, 0xc13d, 0x0eff, 0xc13d, 0x21, 0 + .dw 0x0f40, 0xc13d, 0x0f7f, 0xc13d, 0x21, 0 + .dw 0x0fc0, 0xc13d, 0x0fff, 0xc13d, 0x21, 0 + .dw 0x1040, 0xc13d, 0x107f, 0xc13d, 0x21, 0 + .dw 0x10c0, 0xc13d, 0x10ff, 0xc13d, 0x21, 0 + .dw 0x1140, 0xc13d, 0x117f, 0xc13d, 0x21, 0 + .dw 0x11c0, 0xc13d, 0x11ff, 0xc13d, 0x21, 0 + .dw 0x1240, 0xc13d, 0x127f, 0xc13d, 0x21, 0 + .dw 0x12c0, 0xc13d, 0x12ff, 0xc13d, 0x21, 0 + .dw 0x1340, 0xc13d, 0x137f, 0xc13d, 0x21, 0 + .dw 0x13c0, 0xc13d, 0x13ff, 0xc13d, 0x21, 0 + .dw 0x1440, 0xc13d, 0x147f, 0xc13d, 0x21, 0 + .dw 0x14c0, 0xc13d, 0x14ff, 0xc13d, 0x21, 0 + .dw 0x1540, 0xc13d, 0x157f, 0xc13d, 0x21, 0 + .dw 0x15c0, 0xc13d, 0x15ff, 0xc13d, 0x21, 0 + .dw 0x1640, 0xc13d, 0x167f, 0xc13d, 0x21, 0 + .dw 0x16c0, 0xc13d, 0x16ff, 0xc13d, 0x21, 0 + .dw 0x1740, 0xc13d, 0x177f, 0xc13d, 0x21, 0 + .dw 0x17c0, 0xc13d, 0x17ff, 0xc13d, 0x21, 0 + .dw 0x1840, 0xc13d, 0x187f, 0xc13d, 0x21, 0 + .dw 0x18c0, 0xc13d, 0x18ff, 0xc13d, 0x21, 0 + .dw 0x1940, 0xc13d, 0x197f, 0xc13d, 0x21, 0 + .dw 0x19c0, 0xc13d, 0x1fff, 0xc13d, 0x21, 0 + .dw 0x2040, 0xc13d, 0x207f, 0xc13d, 0x21, 0 + .dw 0x20c0, 0xc13d, 0x20ff, 0xc13d, 0x21, 0 + .dw 0x2140, 0xc13d, 0x217f, 0xc13d, 0x21, 0 + .dw 0x21c0, 0xc13d, 0x21ff, 0xc13d, 0x21, 0 + .dw 0x2240, 0xc13d, 0x227f, 0xc13d, 0x21, 0 + .dw 0x22c0, 0xc13d, 0x22ff, 0xc13d, 0x21, 0 + .dw 0x2340, 0xc13d, 0x237f, 0xc13d, 0x21, 0 + .dw 0x23c0, 0xc13d, 0x23ff, 0xc13d, 0x21, 0 + .dw 0x2440, 0xc13d, 0x247f, 0xc13d, 0x21, 0 + .dw 0x24c0, 0xc13d, 0x24ff, 0xc13d, 0x21, 0 + .dw 0x2540, 0xc13d, 0x257f, 0xc13d, 0x21, 0 + .dw 0x25c0, 0xc13d, 0x25ff, 0xc13d, 0x21, 0 + .dw 0x2640, 0xc13d, 0x267f, 0xc13d, 0x21, 0 + .dw 0x26c0, 0xc13d, 0x26ff, 0xc13d, 0x21, 0 + .dw 0x2740, 0xc13d, 0x277f, 0xc13d, 0x21, 0 + .dw 0x27c0, 0xc13d, 0x27ff, 0xc13d, 0x21, 0 + .dw 0x2840, 0xc13d, 0x287f, 0xc13d, 0x21, 0 + .dw 0x28c0, 0xc13d, 0x28ff, 0xc13d, 0x21, 0 + .dw 0x2940, 0xc13d, 0x297f, 0xc13d, 0x21, 0 + .dw 0x29c0, 0xc13d, 0x29ff, 0xc13d, 0x21, 0 + .dw 0x2a40, 0xc13d, 0x2a7f, 0xc13d, 0x21, 0 + .dw 0x2ac0, 0xc13d, 0x2aff, 0xc13d, 0x21, 0 + .dw 0x2b40, 0xc13d, 0x2b7f, 0xc13d, 0x21, 0 + .dw 0x2bc0, 0xc13d, 0x2bff, 0xc13d, 0x21, 0 + .dw 0x2c40, 0xc13d, 0x2c7f, 0xc13d, 0x21, 0 + .dw 0x2cc0, 0xc13d, 0x2cff, 0xc13d, 0x21, 0 + .dw 0x2d40, 0xc13d, 0x2d7f, 0xc13d, 0x21, 0 + .dw 0x2dc0, 0xc13d, 0x2dff, 0xc13d, 0x21, 0 + .dw 0x2e40, 0xc13d, 0x2e7f, 0xc13d, 0x21, 0 + .dw 0x2ec0, 0xc13d, 0x2eff, 0xc13d, 0x21, 0 + .dw 0x2f40, 0xc13d, 0x2f7f, 0xc13d, 0x21, 0 + .dw 0x2fc0, 0xc13d, 0x2fff, 0xc13d, 0x21, 0 + .dw 0x3040, 0xc13d, 0x307f, 0xc13d, 0x21, 0 + .dw 0x30c0, 0xc13d, 0x30ff, 0xc13d, 0x21, 0 + .dw 0x3140, 0xc13d, 0x317f, 0xc13d, 0x21, 0 + .dw 0x31c0, 0xc13d, 0x31ff, 0xc13d, 0x21, 0 + .dw 0x3240, 0xc13d, 0x327f, 0xc13d, 0x21, 0 + .dw 0x32c0, 0xc13d, 0x32ff, 0xc13d, 0x21, 0 + .dw 0x3340, 0xc13d, 0x337f, 0xc13d, 0x21, 0 + .dw 0x33c0, 0xc13d, 0x33ff, 0xc13d, 0x21, 0 + .dw 0x3440, 0xc13d, 0x347f, 0xc13d, 0x21, 0 + .dw 0x34c0, 0xc13d, 0x34ff, 0xc13d, 0x21, 0 + .dw 0x3540, 0xc13d, 0x357f, 0xc13d, 0x21, 0 + .dw 0x35c0, 0xc13d, 0x35ff, 0xc13d, 0x21, 0 + .dw 0x3640, 0xc13d, 0x367f, 0xc13d, 0x21, 0 + .dw 0x36c0, 0xc13d, 0x36ff, 0xc13d, 0x21, 0 + .dw 0x3740, 0xc13d, 0x377f, 0xc13d, 0x21, 0 + .dw 0x37c0, 0xc13d, 0x37ff, 0xc13d, 0x21, 0 + .dw 0x3840, 0xc13d, 0x387f, 0xc13d, 0x21, 0 + .dw 0x38c0, 0xc13d, 0x38ff, 0xc13d, 0x21, 0 + .dw 0x3940, 0xc13d, 0x397f, 0xc13d, 0x21, 0 + .dw 0x39c0, 0xc13d, 0x3fff, 0xc13d, 0x21, 0 + .dw 0x4040, 0xc13d, 0x407f, 0xc13d, 0x21, 0 + .dw 0x40c0, 0xc13d, 0x40ff, 0xc13d, 0x21, 0 + .dw 0x4140, 0xc13d, 0x417f, 0xc13d, 0x21, 0 + .dw 0x41c0, 0xc13d, 0x41ff, 0xc13d, 0x21, 0 + .dw 0x4240, 0xc13d, 0x427f, 0xc13d, 0x21, 0 + .dw 0x42c0, 0xc13d, 0x42ff, 0xc13d, 0x21, 0 + .dw 0x4340, 0xc13d, 0x437f, 0xc13d, 0x21, 0 + .dw 0x43c0, 0xc13d, 0x43ff, 0xc13d, 0x21, 0 + .dw 0x4440, 0xc13d, 0x447f, 0xc13d, 0x21, 0 + .dw 0x44c0, 0xc13d, 0x44ff, 0xc13d, 0x21, 0 + .dw 0x4540, 0xc13d, 0x457f, 0xc13d, 0x21, 0 + .dw 0x45c0, 0xc13d, 0x45ff, 0xc13d, 0x21, 0 + .dw 0x4640, 0xc13d, 0x467f, 0xc13d, 0x21, 0 + .dw 0x46c0, 0xc13d, 0x46ff, 0xc13d, 0x21, 0 + .dw 0x4740, 0xc13d, 0x477f, 0xc13d, 0x21, 0 + .dw 0x47c0, 0xc13d, 0x47ff, 0xc13d, 0x21, 0 + .dw 0x4840, 0xc13d, 0x487f, 0xc13d, 0x21, 0 + .dw 0x48c0, 0xc13d, 0x48ff, 0xc13d, 0x21, 0 + .dw 0x4940, 0xc13d, 0x497f, 0xc13d, 0x21, 0 + .dw 0x49c0, 0xc13d, 0x49ff, 0xc13d, 0x21, 0 + .dw 0x4a40, 0xc13d, 0x4a7f, 0xc13d, 0x21, 0 + .dw 0x4ac0, 0xc13d, 0x4aff, 0xc13d, 0x21, 0 + .dw 0x4b40, 0xc13d, 0x4b7f, 0xc13d, 0x21, 0 + .dw 0x4bc0, 0xc13d, 0x4bff, 0xc13d, 0x21, 0 + .dw 0x4c40, 0xc13d, 0x4c7f, 0xc13d, 0x21, 0 + .dw 0x4cc0, 0xc13d, 0x4cff, 0xc13d, 0x21, 0 + .dw 0x4d40, 0xc13d, 0x4d7f, 0xc13d, 0x21, 0 + .dw 0x4dc0, 0xc13d, 0x4dff, 0xc13d, 0x21, 0 + .dw 0x4e40, 0xc13d, 0x4e7f, 0xc13d, 0x21, 0 + .dw 0x4ec0, 0xc13d, 0x4eff, 0xc13d, 0x21, 0 + .dw 0x4f40, 0xc13d, 0x4f7f, 0xc13d, 0x21, 0 + .dw 0x4fc0, 0xc13d, 0x4fff, 0xc13d, 0x21, 0 + .dw 0x5040, 0xc13d, 0x507f, 0xc13d, 0x21, 0 + .dw 0x50c0, 0xc13d, 0x50ff, 0xc13d, 0x21, 0 + .dw 0x5140, 0xc13d, 0x517f, 0xc13d, 0x21, 0 + .dw 0x51c0, 0xc13d, 0x51ff, 0xc13d, 0x21, 0 + .dw 0x5240, 0xc13d, 0x527f, 0xc13d, 0x21, 0 + .dw 0x52c0, 0xc13d, 0x52ff, 0xc13d, 0x21, 0 + .dw 0x5340, 0xc13d, 0x537f, 0xc13d, 0x21, 0 + .dw 0x53c0, 0xc13d, 0x53ff, 0xc13d, 0x21, 0 + .dw 0x5440, 0xc13d, 0x547f, 0xc13d, 0x21, 0 + .dw 0x54c0, 0xc13d, 0x54ff, 0xc13d, 0x21, 0 + .dw 0x5540, 0xc13d, 0x557f, 0xc13d, 0x21, 0 + .dw 0x55c0, 0xc13d, 0x55ff, 0xc13d, 0x21, 0 + .dw 0x5640, 0xc13d, 0x567f, 0xc13d, 0x21, 0 + .dw 0x56c0, 0xc13d, 0x56ff, 0xc13d, 0x21, 0 + .dw 0x5740, 0xc13d, 0x577f, 0xc13d, 0x21, 0 + .dw 0x57c0, 0xc13d, 0x57ff, 0xc13d, 0x21, 0 + .dw 0x5840, 0xc13d, 0x587f, 0xc13d, 0x21, 0 + .dw 0x58c0, 0xc13d, 0x58ff, 0xc13d, 0x21, 0 + .dw 0x5940, 0xc13d, 0x597f, 0xc13d, 0x21, 0 + .dw 0x59c0, 0xc13d, 0x5fff, 0xc13d, 0x21, 0 + .dw 0x6040, 0xc13d, 0x607f, 0xc13d, 0x21, 0 + .dw 0x60c0, 0xc13d, 0x60ff, 0xc13d, 0x21, 0 + .dw 0x6140, 0xc13d, 0x617f, 0xc13d, 0x21, 0 + .dw 0x61c0, 0xc13d, 0x61ff, 0xc13d, 0x21, 0 + .dw 0x6240, 0xc13d, 0x627f, 0xc13d, 0x21, 0 + .dw 0x62c0, 0xc13d, 0x62ff, 0xc13d, 0x21, 0 + .dw 0x6340, 0xc13d, 0x637f, 0xc13d, 0x21, 0 + .dw 0x63c0, 0xc13d, 0x63ff, 0xc13d, 0x21, 0 + .dw 0x6440, 0xc13d, 0x647f, 0xc13d, 0x21, 0 + .dw 0x64c0, 0xc13d, 0x64ff, 0xc13d, 0x21, 0 + .dw 0x6540, 0xc13d, 0x657f, 0xc13d, 0x21, 0 + .dw 0x65c0, 0xc13d, 0x65ff, 0xc13d, 0x21, 0 + .dw 0x6640, 0xc13d, 0x667f, 0xc13d, 0x21, 0 + .dw 0x66c0, 0xc13d, 0x66ff, 0xc13d, 0x21, 0 + .dw 0x6740, 0xc13d, 0x677f, 0xc13d, 0x21, 0 + .dw 0x67c0, 0xc13d, 0x67ff, 0xc13d, 0x21, 0 + .dw 0x6840, 0xc13d, 0x687f, 0xc13d, 0x21, 0 + .dw 0x68c0, 0xc13d, 0x68ff, 0xc13d, 0x21, 0 + .dw 0x6940, 0xc13d, 0x697f, 0xc13d, 0x21, 0 + .dw 0x69c0, 0xc13d, 0x69ff, 0xc13d, 0x21, 0 + .dw 0x6a40, 0xc13d, 0x6a7f, 0xc13d, 0x21, 0 + .dw 0x6ac0, 0xc13d, 0x6aff, 0xc13d, 0x21, 0 + .dw 0x6b40, 0xc13d, 0x6b7f, 0xc13d, 0x21, 0 + .dw 0x6bc0, 0xc13d, 0x6bff, 0xc13d, 0x21, 0 + .dw 0x6c40, 0xc13d, 0x6c7f, 0xc13d, 0x21, 0 + .dw 0x6cc0, 0xc13d, 0x6cff, 0xc13d, 0x21, 0 + .dw 0x6d40, 0xc13d, 0x6d7f, 0xc13d, 0x21, 0 + .dw 0x6dc0, 0xc13d, 0x6dff, 0xc13d, 0x21, 0 + .dw 0x6e40, 0xc13d, 0x6e7f, 0xc13d, 0x21, 0 + .dw 0x6ec0, 0xc13d, 0x6eff, 0xc13d, 0x21, 0 + .dw 0x6f40, 0xc13d, 0x6f7f, 0xc13d, 0x21, 0 + .dw 0x6fc0, 0xc13d, 0x6fff, 0xc13d, 0x21, 0 + .dw 0x7040, 0xc13d, 0x707f, 0xc13d, 0x21, 0 + .dw 0x70c0, 0xc13d, 0x70ff, 0xc13d, 0x21, 0 + .dw 0x7140, 0xc13d, 0x717f, 0xc13d, 0x21, 0 + .dw 0x71c0, 0xc13d, 0x71ff, 0xc13d, 0x21, 0 + .dw 0x7240, 0xc13d, 0x727f, 0xc13d, 0x21, 0 + .dw 0x72c0, 0xc13d, 0x72ff, 0xc13d, 0x21, 0 + .dw 0x7340, 0xc13d, 0x737f, 0xc13d, 0x21, 0 + .dw 0x73c0, 0xc13d, 0x73ff, 0xc13d, 0x21, 0 + .dw 0x7440, 0xc13d, 0x747f, 0xc13d, 0x21, 0 + .dw 0x74c0, 0xc13d, 0x74ff, 0xc13d, 0x21, 0 + .dw 0x7540, 0xc13d, 0x757f, 0xc13d, 0x21, 0 + .dw 0x75c0, 0xc13d, 0x75ff, 0xc13d, 0x21, 0 + .dw 0x7640, 0xc13d, 0x767f, 0xc13d, 0x21, 0 + .dw 0x76c0, 0xc13d, 0x76ff, 0xc13d, 0x21, 0 + .dw 0x7740, 0xc13d, 0x777f, 0xc13d, 0x21, 0 + .dw 0x77c0, 0xc13d, 0x77ff, 0xc13d, 0x21, 0 + .dw 0x7840, 0xc13d, 0x787f, 0xc13d, 0x21, 0 + .dw 0x78c0, 0xc13d, 0x78ff, 0xc13d, 0x21, 0 + .dw 0x7940, 0xc13d, 0x797f, 0xc13d, 0x21, 0 + .dw 0x79c0, 0xc13d, 0x7fff, 0xc13d, 0x21, 0 + .dw 0x8040, 0xc13d, 0x807f, 0xc13d, 0x21, 0 + .dw 0x80c0, 0xc13d, 0x80ff, 0xc13d, 0x21, 0 + .dw 0x8140, 0xc13d, 0x817f, 0xc13d, 0x21, 0 + .dw 0x81c0, 0xc13d, 0x81ff, 0xc13d, 0x21, 0 + .dw 0x8240, 0xc13d, 0x827f, 0xc13d, 0x21, 0 + .dw 0x82c0, 0xc13d, 0x82ff, 0xc13d, 0x21, 0 + .dw 0x8340, 0xc13d, 0x837f, 0xc13d, 0x21, 0 + .dw 0x83c0, 0xc13d, 0x83ff, 0xc13d, 0x21, 0 + .dw 0x8440, 0xc13d, 0x847f, 0xc13d, 0x21, 0 + .dw 0x84c0, 0xc13d, 0x84ff, 0xc13d, 0x21, 0 + .dw 0x8540, 0xc13d, 0x857f, 0xc13d, 0x21, 0 + .dw 0x85c0, 0xc13d, 0x85ff, 0xc13d, 0x21, 0 + .dw 0x8640, 0xc13d, 0x867f, 0xc13d, 0x21, 0 + .dw 0x86c0, 0xc13d, 0x86ff, 0xc13d, 0x21, 0 + .dw 0x8740, 0xc13d, 0x877f, 0xc13d, 0x21, 0 + .dw 0x87c0, 0xc13d, 0x87ff, 0xc13d, 0x21, 0 + .dw 0x8840, 0xc13d, 0x887f, 0xc13d, 0x21, 0 + .dw 0x88c0, 0xc13d, 0x88ff, 0xc13d, 0x21, 0 + .dw 0x8940, 0xc13d, 0x897f, 0xc13d, 0x21, 0 + .dw 0x89c0, 0xc13d, 0x89ff, 0xc13d, 0x21, 0 + .dw 0x8a40, 0xc13d, 0x8a7f, 0xc13d, 0x21, 0 + .dw 0x8ac0, 0xc13d, 0x8aff, 0xc13d, 0x21, 0 + .dw 0x8b40, 0xc13d, 0x8b7f, 0xc13d, 0x21, 0 + .dw 0x8bc0, 0xc13d, 0x8bff, 0xc13d, 0x21, 0 + .dw 0x8c40, 0xc13d, 0x8c7f, 0xc13d, 0x21, 0 + .dw 0x8cc0, 0xc13d, 0x8cff, 0xc13d, 0x21, 0 + .dw 0x8d40, 0xc13d, 0x8d7f, 0xc13d, 0x21, 0 + .dw 0x8dc0, 0xc13d, 0x8dff, 0xc13d, 0x21, 0 + .dw 0x8e40, 0xc13d, 0x8e7f, 0xc13d, 0x21, 0 + .dw 0x8ec0, 0xc13d, 0x8eff, 0xc13d, 0x21, 0 + .dw 0x8f40, 0xc13d, 0x8f7f, 0xc13d, 0x21, 0 + .dw 0x8fc0, 0xc13d, 0x8fff, 0xc13d, 0x21, 0 + .dw 0x9040, 0xc13d, 0x907f, 0xc13d, 0x21, 0 + .dw 0x90c0, 0xc13d, 0x90ff, 0xc13d, 0x21, 0 + .dw 0x9140, 0xc13d, 0x917f, 0xc13d, 0x21, 0 + .dw 0x91c0, 0xc13d, 0x91ff, 0xc13d, 0x21, 0 + .dw 0x9240, 0xc13d, 0x927f, 0xc13d, 0x21, 0 + .dw 0x92c0, 0xc13d, 0x92ff, 0xc13d, 0x21, 0 + .dw 0x9340, 0xc13d, 0x937f, 0xc13d, 0x21, 0 + .dw 0x93c0, 0xc13d, 0x93ff, 0xc13d, 0x21, 0 + .dw 0x9440, 0xc13d, 0x947f, 0xc13d, 0x21, 0 + .dw 0x94c0, 0xc13d, 0x94ff, 0xc13d, 0x21, 0 + .dw 0x9540, 0xc13d, 0x957f, 0xc13d, 0x21, 0 + .dw 0x95c0, 0xc13d, 0x95ff, 0xc13d, 0x21, 0 + .dw 0x9640, 0xc13d, 0x967f, 0xc13d, 0x21, 0 + .dw 0x96c0, 0xc13d, 0x96ff, 0xc13d, 0x21, 0 + .dw 0x9740, 0xc13d, 0x977f, 0xc13d, 0x21, 0 + .dw 0x97c0, 0xc13d, 0x97ff, 0xc13d, 0x21, 0 + .dw 0x9840, 0xc13d, 0x987f, 0xc13d, 0x21, 0 + .dw 0x98c0, 0xc13d, 0x98ff, 0xc13d, 0x21, 0 + .dw 0x9940, 0xc13d, 0x997f, 0xc13d, 0x21, 0 + .dw 0x99c0, 0xc13d, 0x9fff, 0xc13d, 0x21, 0 + .dw 0xa040, 0xc13d, 0xa07f, 0xc13d, 0x21, 0 + .dw 0xa0c0, 0xc13d, 0xa0ff, 0xc13d, 0x21, 0 + .dw 0xa140, 0xc13d, 0xa17f, 0xc13d, 0x21, 0 + .dw 0xa1c0, 0xc13d, 0xa1ff, 0xc13d, 0x21, 0 + .dw 0xa240, 0xc13d, 0xa27f, 0xc13d, 0x21, 0 + .dw 0xa2c0, 0xc13d, 0xa2ff, 0xc13d, 0x21, 0 + .dw 0xa340, 0xc13d, 0xa37f, 0xc13d, 0x21, 0 + .dw 0xa3c0, 0xc13d, 0xa3ff, 0xc13d, 0x21, 0 + .dw 0xa440, 0xc13d, 0xa47f, 0xc13d, 0x21, 0 + .dw 0xa4c0, 0xc13d, 0xa4ff, 0xc13d, 0x21, 0 + .dw 0xa540, 0xc13d, 0xa57f, 0xc13d, 0x21, 0 + .dw 0xa5c0, 0xc13d, 0xa5ff, 0xc13d, 0x21, 0 + .dw 0xa640, 0xc13d, 0xa67f, 0xc13d, 0x21, 0 + .dw 0xa6c0, 0xc13d, 0xa6ff, 0xc13d, 0x21, 0 + .dw 0xa740, 0xc13d, 0xa77f, 0xc13d, 0x21, 0 + .dw 0xa7c0, 0xc13d, 0xa7ff, 0xc13d, 0x21, 0 + .dw 0xa840, 0xc13d, 0xa87f, 0xc13d, 0x21, 0 + .dw 0xa8c0, 0xc13d, 0xa8ff, 0xc13d, 0x21, 0 + .dw 0xa940, 0xc13d, 0xa97f, 0xc13d, 0x21, 0 + .dw 0xa9c0, 0xc13d, 0xa9ff, 0xc13d, 0x21, 0 + .dw 0xaa40, 0xc13d, 0xaa7f, 0xc13d, 0x21, 0 + .dw 0xaac0, 0xc13d, 0xaaff, 0xc13d, 0x21, 0 + .dw 0xab40, 0xc13d, 0xab7f, 0xc13d, 0x21, 0 + .dw 0xabc0, 0xc13d, 0xabff, 0xc13d, 0x21, 0 + .dw 0xac40, 0xc13d, 0xac7f, 0xc13d, 0x21, 0 + .dw 0xacc0, 0xc13d, 0xacff, 0xc13d, 0x21, 0 + .dw 0xad40, 0xc13d, 0xad7f, 0xc13d, 0x21, 0 + .dw 0xadc0, 0xc13d, 0xadff, 0xc13d, 0x21, 0 + .dw 0xae40, 0xc13d, 0xae7f, 0xc13d, 0x21, 0 + .dw 0xaec0, 0xc13d, 0xaeff, 0xc13d, 0x21, 0 + .dw 0xaf40, 0xc13d, 0xaf7f, 0xc13d, 0x21, 0 + .dw 0xafc0, 0xc13d, 0xafff, 0xc13d, 0x21, 0 + .dw 0xb040, 0xc13d, 0xb07f, 0xc13d, 0x21, 0 + .dw 0xb0c0, 0xc13d, 0xb0ff, 0xc13d, 0x21, 0 + .dw 0xb140, 0xc13d, 0xb17f, 0xc13d, 0x21, 0 + .dw 0xb1c0, 0xc13d, 0xb1ff, 0xc13d, 0x21, 0 + .dw 0xb240, 0xc13d, 0xb27f, 0xc13d, 0x21, 0 + .dw 0xb2c0, 0xc13d, 0xb2ff, 0xc13d, 0x21, 0 + .dw 0xb340, 0xc13d, 0xb37f, 0xc13d, 0x21, 0 + .dw 0xb3c0, 0xc13d, 0xb3ff, 0xc13d, 0x21, 0 + .dw 0xb440, 0xc13d, 0xb47f, 0xc13d, 0x21, 0 + .dw 0xb4c0, 0xc13d, 0xb4ff, 0xc13d, 0x21, 0 + .dw 0xb540, 0xc13d, 0xb57f, 0xc13d, 0x21, 0 + .dw 0xb5c0, 0xc13d, 0xb5ff, 0xc13d, 0x21, 0 + .dw 0xb640, 0xc13d, 0xb67f, 0xc13d, 0x21, 0 + .dw 0xb6c0, 0xc13d, 0xb6ff, 0xc13d, 0x21, 0 + .dw 0xb740, 0xc13d, 0xb77f, 0xc13d, 0x21, 0 + .dw 0xb7c0, 0xc13d, 0xb7ff, 0xc13d, 0x21, 0 + .dw 0xb840, 0xc13d, 0xb87f, 0xc13d, 0x21, 0 + .dw 0xb8c0, 0xc13d, 0xb8ff, 0xc13d, 0x21, 0 + .dw 0xb940, 0xc13d, 0xb97f, 0xc13d, 0x21, 0 + .dw 0xb9c0, 0xc13d, 0xbfff, 0xc13d, 0x21, 0 + .dw 0xc040, 0xc13d, 0xc07f, 0xc13d, 0x21, 0 + .dw 0xc0c0, 0xc13d, 0xc0ff, 0xc13d, 0x21, 0 + .dw 0xc140, 0xc13d, 0xc17f, 0xc13d, 0x21, 0 + .dw 0xc1c0, 0xc13d, 0xc1ff, 0xc13d, 0x21, 0 + .dw 0xc240, 0xc13d, 0xc27f, 0xc13d, 0x21, 0 + .dw 0xc2c0, 0xc13d, 0xc2ff, 0xc13d, 0x21, 0 + .dw 0xc340, 0xc13d, 0xc37f, 0xc13d, 0x21, 0 + .dw 0xc3c0, 0xc13d, 0xc3ff, 0xc13d, 0x21, 0 + .dw 0xc440, 0xc13d, 0xc47f, 0xc13d, 0x21, 0 + .dw 0xc4c0, 0xc13d, 0xc4ff, 0xc13d, 0x21, 0 + .dw 0xc540, 0xc13d, 0xc57f, 0xc13d, 0x21, 0 + .dw 0xc5c0, 0xc13d, 0xc5ff, 0xc13d, 0x21, 0 + .dw 0xc640, 0xc13d, 0xc67f, 0xc13d, 0x21, 0 + .dw 0xc6c0, 0xc13d, 0xc6ff, 0xc13d, 0x21, 0 + .dw 0xc740, 0xc13d, 0xc77f, 0xc13d, 0x21, 0 + .dw 0xc7c0, 0xc13d, 0xc7ff, 0xc13d, 0x21, 0 + .dw 0xc840, 0xc13d, 0xc87f, 0xc13d, 0x21, 0 + .dw 0xc8c0, 0xc13d, 0xc8ff, 0xc13d, 0x21, 0 + .dw 0xc940, 0xc13d, 0xc97f, 0xc13d, 0x21, 0 + .dw 0xc9c0, 0xc13d, 0xc9ff, 0xc13d, 0x21, 0 + .dw 0xca40, 0xc13d, 0xca7f, 0xc13d, 0x21, 0 + .dw 0xcac0, 0xc13d, 0xcaff, 0xc13d, 0x21, 0 + .dw 0xcb40, 0xc13d, 0xcb7f, 0xc13d, 0x21, 0 + .dw 0xcbc0, 0xc13d, 0xcbff, 0xc13d, 0x21, 0 + .dw 0xcc40, 0xc13d, 0xcc7f, 0xc13d, 0x21, 0 + .dw 0xccc0, 0xc13d, 0xccff, 0xc13d, 0x21, 0 + .dw 0xcd40, 0xc13d, 0xcd7f, 0xc13d, 0x21, 0 + .dw 0xcdc0, 0xc13d, 0xcdff, 0xc13d, 0x21, 0 + .dw 0xce40, 0xc13d, 0xce7f, 0xc13d, 0x21, 0 + .dw 0xcec0, 0xc13d, 0xceff, 0xc13d, 0x21, 0 + .dw 0xcf40, 0xc13d, 0xcf7f, 0xc13d, 0x21, 0 + .dw 0xcfc0, 0xc13d, 0xcfff, 0xc13d, 0x21, 0 + .dw 0xd040, 0xc13d, 0xd07f, 0xc13d, 0x21, 0 + .dw 0xd0c0, 0xc13d, 0xd0ff, 0xc13d, 0x21, 0 + .dw 0xd140, 0xc13d, 0xd17f, 0xc13d, 0x21, 0 + .dw 0xd1c0, 0xc13d, 0xd1ff, 0xc13d, 0x21, 0 + .dw 0xd240, 0xc13d, 0xd27f, 0xc13d, 0x21, 0 + .dw 0xd2c0, 0xc13d, 0xd2ff, 0xc13d, 0x21, 0 + .dw 0xd340, 0xc13d, 0xd37f, 0xc13d, 0x21, 0 + .dw 0xd3c0, 0xc13d, 0xd3ff, 0xc13d, 0x21, 0 + .dw 0xd440, 0xc13d, 0xd47f, 0xc13d, 0x21, 0 + .dw 0xd4c0, 0xc13d, 0xd4ff, 0xc13d, 0x21, 0 + .dw 0xd540, 0xc13d, 0xd57f, 0xc13d, 0x21, 0 + .dw 0xd5c0, 0xc13d, 0xd5ff, 0xc13d, 0x21, 0 + .dw 0xd640, 0xc13d, 0xd67f, 0xc13d, 0x21, 0 + .dw 0xd6c0, 0xc13d, 0xd6ff, 0xc13d, 0x21, 0 + .dw 0xd740, 0xc13d, 0xd77f, 0xc13d, 0x21, 0 + .dw 0xd7c0, 0xc13d, 0xd7ff, 0xc13d, 0x21, 0 + .dw 0xd840, 0xc13d, 0xd87f, 0xc13d, 0x21, 0 + .dw 0xd8c0, 0xc13d, 0xd8ff, 0xc13d, 0x21, 0 + .dw 0xd940, 0xc13d, 0xd97f, 0xc13d, 0x21, 0 + .dw 0xd9c0, 0xc13d, 0xdfff, 0xc13d, 0x21, 0 + .dw 0xe040, 0xc13d, 0xe07f, 0xc13d, 0x21, 0 + .dw 0xe0c0, 0xc13d, 0xe0ff, 0xc13d, 0x21, 0 + .dw 0xe140, 0xc13d, 0xe17f, 0xc13d, 0x21, 0 + .dw 0xe1c0, 0xc13d, 0xe1ff, 0xc13d, 0x21, 0 + .dw 0xe240, 0xc13d, 0xe27f, 0xc13d, 0x21, 0 + .dw 0xe2c0, 0xc13d, 0xe2ff, 0xc13d, 0x21, 0 + .dw 0xe340, 0xc13d, 0xe37f, 0xc13d, 0x21, 0 + .dw 0xe3c0, 0xc13d, 0xe3ff, 0xc13d, 0x21, 0 + .dw 0xe440, 0xc13d, 0xe47f, 0xc13d, 0x21, 0 + .dw 0xe4c0, 0xc13d, 0xe4ff, 0xc13d, 0x21, 0 + .dw 0xe540, 0xc13d, 0xe57f, 0xc13d, 0x21, 0 + .dw 0xe5c0, 0xc13d, 0xe5ff, 0xc13d, 0x21, 0 + .dw 0xe640, 0xc13d, 0xe67f, 0xc13d, 0x21, 0 + .dw 0xe6c0, 0xc13d, 0xe6ff, 0xc13d, 0x21, 0 + .dw 0xe740, 0xc13d, 0xe77f, 0xc13d, 0x21, 0 + .dw 0xe7c0, 0xc13d, 0xe7ff, 0xc13d, 0x21, 0 + .dw 0xe840, 0xc13d, 0xe87f, 0xc13d, 0x21, 0 + .dw 0xe8c0, 0xc13d, 0xe8ff, 0xc13d, 0x21, 0 + .dw 0xe940, 0xc13d, 0xe97f, 0xc13d, 0x21, 0 + .dw 0xe9c0, 0xc13d, 0xe9ff, 0xc13d, 0x21, 0 + .dw 0xea40, 0xc13d, 0xea7f, 0xc13d, 0x21, 0 + .dw 0xeac0, 0xc13d, 0xeaff, 0xc13d, 0x21, 0 + .dw 0xeb40, 0xc13d, 0xeb7f, 0xc13d, 0x21, 0 + .dw 0xebc0, 0xc13d, 0xebff, 0xc13d, 0x21, 0 + .dw 0xec40, 0xc13d, 0xec7f, 0xc13d, 0x21, 0 + .dw 0xecc0, 0xc13d, 0xecff, 0xc13d, 0x21, 0 + .dw 0xed40, 0xc13d, 0xed7f, 0xc13d, 0x21, 0 + .dw 0xedc0, 0xc13d, 0xedff, 0xc13d, 0x21, 0 + .dw 0xee40, 0xc13d, 0xee7f, 0xc13d, 0x21, 0 + .dw 0xeec0, 0xc13d, 0xeeff, 0xc13d, 0x21, 0 + .dw 0xef40, 0xc13d, 0xef7f, 0xc13d, 0x21, 0 + .dw 0xefc0, 0xc13d, 0xefff, 0xc13d, 0x21, 0 + .dw 0xf040, 0xc13d, 0xf07f, 0xc13d, 0x21, 0 + .dw 0xf0c0, 0xc13d, 0xf0ff, 0xc13d, 0x21, 0 + .dw 0xf140, 0xc13d, 0xf17f, 0xc13d, 0x21, 0 + .dw 0xf1c0, 0xc13d, 0xf1ff, 0xc13d, 0x21, 0 + .dw 0xf240, 0xc13d, 0xf27f, 0xc13d, 0x21, 0 + .dw 0xf2c0, 0xc13d, 0xf2ff, 0xc13d, 0x21, 0 + .dw 0xf340, 0xc13d, 0xf37f, 0xc13d, 0x21, 0 + .dw 0xf3c0, 0xc13d, 0xf3ff, 0xc13d, 0x21, 0 + .dw 0xf440, 0xc13d, 0xf47f, 0xc13d, 0x21, 0 + .dw 0xf4c0, 0xc13d, 0xf4ff, 0xc13d, 0x21, 0 + .dw 0xf540, 0xc13d, 0xf57f, 0xc13d, 0x21, 0 + .dw 0xf5c0, 0xc13d, 0xf5ff, 0xc13d, 0x21, 0 + .dw 0xf640, 0xc13d, 0xf67f, 0xc13d, 0x21, 0 + .dw 0xf6c0, 0xc13d, 0xf6ff, 0xc13d, 0x21, 0 + .dw 0xf740, 0xc13d, 0xf77f, 0xc13d, 0x21, 0 + .dw 0xf7c0, 0xc13d, 0xf7ff, 0xc13d, 0x21, 0 + .dw 0xf840, 0xc13d, 0xf87f, 0xc13d, 0x21, 0 + .dw 0xf8c0, 0xc13d, 0xf8ff, 0xc13d, 0x21, 0 + .dw 0xf940, 0xc13d, 0xf97f, 0xc13d, 0x21, 0 + .dw 0xf9c0, 0xc13d, 0xffff, 0xc13d, 0x21, 0 + .dw 0x0040, 0xc13e, 0x007f, 0xc13e, 0x21, 0 + .dw 0x00c0, 0xc13e, 0x00ff, 0xc13e, 0x21, 0 + .dw 0x0140, 0xc13e, 0x017f, 0xc13e, 0x21, 0 + .dw 0x01c0, 0xc13e, 0x01ff, 0xc13e, 0x21, 0 + .dw 0x0240, 0xc13e, 0x027f, 0xc13e, 0x21, 0 + .dw 0x02c0, 0xc13e, 0x02ff, 0xc13e, 0x21, 0 + .dw 0x0340, 0xc13e, 0x037f, 0xc13e, 0x21, 0 + .dw 0x03c0, 0xc13e, 0x03ff, 0xc13e, 0x21, 0 + .dw 0x0440, 0xc13e, 0x047f, 0xc13e, 0x21, 0 + .dw 0x04c0, 0xc13e, 0x04ff, 0xc13e, 0x21, 0 + .dw 0x0540, 0xc13e, 0x057f, 0xc13e, 0x21, 0 + .dw 0x05c0, 0xc13e, 0x05ff, 0xc13e, 0x21, 0 + .dw 0x0640, 0xc13e, 0x067f, 0xc13e, 0x21, 0 + .dw 0x06c0, 0xc13e, 0x06ff, 0xc13e, 0x21, 0 + .dw 0x0740, 0xc13e, 0x077f, 0xc13e, 0x21, 0 + .dw 0x07c0, 0xc13e, 0x07ff, 0xc13e, 0x21, 0 + .dw 0x0840, 0xc13e, 0x087f, 0xc13e, 0x21, 0 + .dw 0x08c0, 0xc13e, 0x08ff, 0xc13e, 0x21, 0 + .dw 0x0940, 0xc13e, 0x097f, 0xc13e, 0x21, 0 + .dw 0x09c0, 0xc13e, 0x09ff, 0xc13e, 0x21, 0 + .dw 0x0a40, 0xc13e, 0x0a7f, 0xc13e, 0x21, 0 + .dw 0x0ac0, 0xc13e, 0x0aff, 0xc13e, 0x21, 0 + .dw 0x0b40, 0xc13e, 0x0b7f, 0xc13e, 0x21, 0 + .dw 0x0bc0, 0xc13e, 0x0bff, 0xc13e, 0x21, 0 + .dw 0x0c40, 0xc13e, 0x0c7f, 0xc13e, 0x21, 0 + .dw 0x0cc0, 0xc13e, 0x0cff, 0xc13e, 0x21, 0 + .dw 0x0d40, 0xc13e, 0x0d7f, 0xc13e, 0x21, 0 + .dw 0x0dc0, 0xc13e, 0x0dff, 0xc13e, 0x21, 0 + .dw 0x0e40, 0xc13e, 0x0e7f, 0xc13e, 0x21, 0 + .dw 0x0ec0, 0xc13e, 0x0eff, 0xc13e, 0x21, 0 + .dw 0x0f40, 0xc13e, 0x0f7f, 0xc13e, 0x21, 0 + .dw 0x0fc0, 0xc13e, 0x0fff, 0xc13e, 0x21, 0 + .dw 0x1040, 0xc13e, 0x107f, 0xc13e, 0x21, 0 + .dw 0x10c0, 0xc13e, 0x10ff, 0xc13e, 0x21, 0 + .dw 0x1140, 0xc13e, 0x117f, 0xc13e, 0x21, 0 + .dw 0x11c0, 0xc13e, 0x11ff, 0xc13e, 0x21, 0 + .dw 0x1240, 0xc13e, 0x127f, 0xc13e, 0x21, 0 + .dw 0x12c0, 0xc13e, 0x12ff, 0xc13e, 0x21, 0 + .dw 0x1340, 0xc13e, 0x137f, 0xc13e, 0x21, 0 + .dw 0x13c0, 0xc13e, 0x13ff, 0xc13e, 0x21, 0 + .dw 0x1440, 0xc13e, 0x147f, 0xc13e, 0x21, 0 + .dw 0x14c0, 0xc13e, 0x14ff, 0xc13e, 0x21, 0 + .dw 0x1540, 0xc13e, 0x157f, 0xc13e, 0x21, 0 + .dw 0x15c0, 0xc13e, 0x15ff, 0xc13e, 0x21, 0 + .dw 0x1640, 0xc13e, 0x167f, 0xc13e, 0x21, 0 + .dw 0x16c0, 0xc13e, 0x16ff, 0xc13e, 0x21, 0 + .dw 0x1740, 0xc13e, 0x177f, 0xc13e, 0x21, 0 + .dw 0x17c0, 0xc13e, 0x17ff, 0xc13e, 0x21, 0 + .dw 0x1840, 0xc13e, 0x187f, 0xc13e, 0x21, 0 + .dw 0x18c0, 0xc13e, 0x18ff, 0xc13e, 0x21, 0 + .dw 0x1940, 0xc13e, 0x197f, 0xc13e, 0x21, 0 + .dw 0x19c0, 0xc13e, 0x1fff, 0xc13e, 0x21, 0 + .dw 0x2040, 0xc13e, 0x207f, 0xc13e, 0x21, 0 + .dw 0x20c0, 0xc13e, 0x20ff, 0xc13e, 0x21, 0 + .dw 0x2140, 0xc13e, 0x217f, 0xc13e, 0x21, 0 + .dw 0x21c0, 0xc13e, 0x21ff, 0xc13e, 0x21, 0 + .dw 0x2240, 0xc13e, 0x227f, 0xc13e, 0x21, 0 + .dw 0x22c0, 0xc13e, 0x22ff, 0xc13e, 0x21, 0 + .dw 0x2340, 0xc13e, 0x237f, 0xc13e, 0x21, 0 + .dw 0x23c0, 0xc13e, 0x23ff, 0xc13e, 0x21, 0 + .dw 0x2440, 0xc13e, 0x247f, 0xc13e, 0x21, 0 + .dw 0x24c0, 0xc13e, 0x24ff, 0xc13e, 0x21, 0 + .dw 0x2540, 0xc13e, 0x257f, 0xc13e, 0x21, 0 + .dw 0x25c0, 0xc13e, 0x25ff, 0xc13e, 0x21, 0 + .dw 0x2640, 0xc13e, 0x267f, 0xc13e, 0x21, 0 + .dw 0x26c0, 0xc13e, 0x26ff, 0xc13e, 0x21, 0 + .dw 0x2740, 0xc13e, 0x277f, 0xc13e, 0x21, 0 + .dw 0x27c0, 0xc13e, 0x27ff, 0xc13e, 0x21, 0 + .dw 0x2840, 0xc13e, 0x287f, 0xc13e, 0x21, 0 + .dw 0x28c0, 0xc13e, 0x28ff, 0xc13e, 0x21, 0 + .dw 0x2940, 0xc13e, 0x297f, 0xc13e, 0x21, 0 + .dw 0x29c0, 0xc13e, 0x29ff, 0xc13e, 0x21, 0 + .dw 0x2a40, 0xc13e, 0x2a7f, 0xc13e, 0x21, 0 + .dw 0x2ac0, 0xc13e, 0x2aff, 0xc13e, 0x21, 0 + .dw 0x2b40, 0xc13e, 0x2b7f, 0xc13e, 0x21, 0 + .dw 0x2bc0, 0xc13e, 0x2bff, 0xc13e, 0x21, 0 + .dw 0x2c40, 0xc13e, 0x2c7f, 0xc13e, 0x21, 0 + .dw 0x2cc0, 0xc13e, 0x2cff, 0xc13e, 0x21, 0 + .dw 0x2d40, 0xc13e, 0x2d7f, 0xc13e, 0x21, 0 + .dw 0x2dc0, 0xc13e, 0x2dff, 0xc13e, 0x21, 0 + .dw 0x2e40, 0xc13e, 0x2e7f, 0xc13e, 0x21, 0 + .dw 0x2ec0, 0xc13e, 0x2eff, 0xc13e, 0x21, 0 + .dw 0x2f40, 0xc13e, 0x2f7f, 0xc13e, 0x21, 0 + .dw 0x2fc0, 0xc13e, 0x2fff, 0xc13e, 0x21, 0 + .dw 0x3040, 0xc13e, 0x307f, 0xc13e, 0x21, 0 + .dw 0x30c0, 0xc13e, 0x30ff, 0xc13e, 0x21, 0 + .dw 0x3140, 0xc13e, 0x317f, 0xc13e, 0x21, 0 + .dw 0x31c0, 0xc13e, 0x31ff, 0xc13e, 0x21, 0 + .dw 0x3240, 0xc13e, 0x327f, 0xc13e, 0x21, 0 + .dw 0x32c0, 0xc13e, 0x32ff, 0xc13e, 0x21, 0 + .dw 0x3340, 0xc13e, 0x337f, 0xc13e, 0x21, 0 + .dw 0x33c0, 0xc13e, 0x33ff, 0xc13e, 0x21, 0 + .dw 0x3440, 0xc13e, 0x347f, 0xc13e, 0x21, 0 + .dw 0x34c0, 0xc13e, 0x34ff, 0xc13e, 0x21, 0 + .dw 0x3540, 0xc13e, 0x357f, 0xc13e, 0x21, 0 + .dw 0x35c0, 0xc13e, 0x35ff, 0xc13e, 0x21, 0 + .dw 0x3640, 0xc13e, 0x367f, 0xc13e, 0x21, 0 + .dw 0x36c0, 0xc13e, 0x36ff, 0xc13e, 0x21, 0 + .dw 0x3740, 0xc13e, 0x377f, 0xc13e, 0x21, 0 + .dw 0x37c0, 0xc13e, 0x37ff, 0xc13e, 0x21, 0 + .dw 0x3840, 0xc13e, 0x387f, 0xc13e, 0x21, 0 + .dw 0x38c0, 0xc13e, 0x38ff, 0xc13e, 0x21, 0 + .dw 0x3940, 0xc13e, 0x397f, 0xc13e, 0x21, 0 + .dw 0x39c0, 0xc13e, 0x3fff, 0xc13e, 0x21, 0 + .dw 0x4040, 0xc13e, 0x407f, 0xc13e, 0x21, 0 + .dw 0x40c0, 0xc13e, 0x40ff, 0xc13e, 0x21, 0 + .dw 0x4140, 0xc13e, 0x417f, 0xc13e, 0x21, 0 + .dw 0x41c0, 0xc13e, 0x41ff, 0xc13e, 0x21, 0 + .dw 0x4240, 0xc13e, 0x427f, 0xc13e, 0x21, 0 + .dw 0x42c0, 0xc13e, 0x42ff, 0xc13e, 0x21, 0 + .dw 0x4340, 0xc13e, 0x437f, 0xc13e, 0x21, 0 + .dw 0x43c0, 0xc13e, 0x43ff, 0xc13e, 0x21, 0 + .dw 0x4440, 0xc13e, 0x447f, 0xc13e, 0x21, 0 + .dw 0x44c0, 0xc13e, 0x44ff, 0xc13e, 0x21, 0 + .dw 0x4540, 0xc13e, 0x457f, 0xc13e, 0x21, 0 + .dw 0x45c0, 0xc13e, 0x45ff, 0xc13e, 0x21, 0 + .dw 0x4640, 0xc13e, 0x467f, 0xc13e, 0x21, 0 + .dw 0x46c0, 0xc13e, 0x46ff, 0xc13e, 0x21, 0 + .dw 0x4740, 0xc13e, 0x477f, 0xc13e, 0x21, 0 + .dw 0x47c0, 0xc13e, 0x47ff, 0xc13e, 0x21, 0 + .dw 0x4840, 0xc13e, 0x487f, 0xc13e, 0x21, 0 + .dw 0x48c0, 0xc13e, 0x48ff, 0xc13e, 0x21, 0 + .dw 0x4940, 0xc13e, 0x497f, 0xc13e, 0x21, 0 + .dw 0x49c0, 0xc13e, 0x49ff, 0xc13e, 0x21, 0 + .dw 0x4a40, 0xc13e, 0x4a7f, 0xc13e, 0x21, 0 + .dw 0x4ac0, 0xc13e, 0x4aff, 0xc13e, 0x21, 0 + .dw 0x4b40, 0xc13e, 0x4b7f, 0xc13e, 0x21, 0 + .dw 0x4bc0, 0xc13e, 0x4bff, 0xc13e, 0x21, 0 + .dw 0x4c40, 0xc13e, 0x4c7f, 0xc13e, 0x21, 0 + .dw 0x4cc0, 0xc13e, 0x4cff, 0xc13e, 0x21, 0 + .dw 0x4d40, 0xc13e, 0x4d7f, 0xc13e, 0x21, 0 + .dw 0x4dc0, 0xc13e, 0x4dff, 0xc13e, 0x21, 0 + .dw 0x4e40, 0xc13e, 0x4e7f, 0xc13e, 0x21, 0 + .dw 0x4ec0, 0xc13e, 0x4eff, 0xc13e, 0x21, 0 + .dw 0x4f40, 0xc13e, 0x4f7f, 0xc13e, 0x21, 0 + .dw 0x4fc0, 0xc13e, 0x4fff, 0xc13e, 0x21, 0 + .dw 0x5040, 0xc13e, 0x507f, 0xc13e, 0x21, 0 + .dw 0x50c0, 0xc13e, 0x50ff, 0xc13e, 0x21, 0 + .dw 0x5140, 0xc13e, 0x517f, 0xc13e, 0x21, 0 + .dw 0x51c0, 0xc13e, 0x51ff, 0xc13e, 0x21, 0 + .dw 0x5240, 0xc13e, 0x527f, 0xc13e, 0x21, 0 + .dw 0x52c0, 0xc13e, 0x52ff, 0xc13e, 0x21, 0 + .dw 0x5340, 0xc13e, 0x537f, 0xc13e, 0x21, 0 + .dw 0x53c0, 0xc13e, 0x53ff, 0xc13e, 0x21, 0 + .dw 0x5440, 0xc13e, 0x547f, 0xc13e, 0x21, 0 + .dw 0x54c0, 0xc13e, 0x54ff, 0xc13e, 0x21, 0 + .dw 0x5540, 0xc13e, 0x557f, 0xc13e, 0x21, 0 + .dw 0x55c0, 0xc13e, 0x55ff, 0xc13e, 0x21, 0 + .dw 0x5640, 0xc13e, 0x567f, 0xc13e, 0x21, 0 + .dw 0x56c0, 0xc13e, 0x56ff, 0xc13e, 0x21, 0 + .dw 0x5740, 0xc13e, 0x577f, 0xc13e, 0x21, 0 + .dw 0x57c0, 0xc13e, 0x57ff, 0xc13e, 0x21, 0 + .dw 0x5840, 0xc13e, 0x587f, 0xc13e, 0x21, 0 + .dw 0x58c0, 0xc13e, 0x58ff, 0xc13e, 0x21, 0 + .dw 0x5940, 0xc13e, 0x597f, 0xc13e, 0x21, 0 + .dw 0x59c0, 0xc13e, 0x5fff, 0xc13e, 0x21, 0 + .dw 0x6040, 0xc13e, 0x607f, 0xc13e, 0x21, 0 + .dw 0x60c0, 0xc13e, 0x60ff, 0xc13e, 0x21, 0 + .dw 0x6140, 0xc13e, 0x617f, 0xc13e, 0x21, 0 + .dw 0x61c0, 0xc13e, 0x61ff, 0xc13e, 0x21, 0 + .dw 0x6240, 0xc13e, 0x627f, 0xc13e, 0x21, 0 + .dw 0x62c0, 0xc13e, 0x62ff, 0xc13e, 0x21, 0 + .dw 0x6340, 0xc13e, 0x637f, 0xc13e, 0x21, 0 + .dw 0x63c0, 0xc13e, 0x63ff, 0xc13e, 0x21, 0 + .dw 0x6440, 0xc13e, 0x647f, 0xc13e, 0x21, 0 + .dw 0x64c0, 0xc13e, 0x64ff, 0xc13e, 0x21, 0 + .dw 0x6540, 0xc13e, 0x657f, 0xc13e, 0x21, 0 + .dw 0x65c0, 0xc13e, 0x65ff, 0xc13e, 0x21, 0 + .dw 0x6640, 0xc13e, 0x667f, 0xc13e, 0x21, 0 + .dw 0x66c0, 0xc13e, 0x66ff, 0xc13e, 0x21, 0 + .dw 0x6740, 0xc13e, 0x677f, 0xc13e, 0x21, 0 + .dw 0x67c0, 0xc13e, 0x67ff, 0xc13e, 0x21, 0 + .dw 0x6840, 0xc13e, 0x687f, 0xc13e, 0x21, 0 + .dw 0x68c0, 0xc13e, 0x68ff, 0xc13e, 0x21, 0 + .dw 0x6940, 0xc13e, 0x697f, 0xc13e, 0x21, 0 + .dw 0x69c0, 0xc13e, 0x69ff, 0xc13e, 0x21, 0 + .dw 0x6a40, 0xc13e, 0x6a7f, 0xc13e, 0x21, 0 + .dw 0x6ac0, 0xc13e, 0x6aff, 0xc13e, 0x21, 0 + .dw 0x6b40, 0xc13e, 0x6b7f, 0xc13e, 0x21, 0 + .dw 0x6bc0, 0xc13e, 0x6bff, 0xc13e, 0x21, 0 + .dw 0x6c40, 0xc13e, 0x6c7f, 0xc13e, 0x21, 0 + .dw 0x6cc0, 0xc13e, 0x6cff, 0xc13e, 0x21, 0 + .dw 0x6d40, 0xc13e, 0x6d7f, 0xc13e, 0x21, 0 + .dw 0x6dc0, 0xc13e, 0x6dff, 0xc13e, 0x21, 0 + .dw 0x6e40, 0xc13e, 0x6e7f, 0xc13e, 0x21, 0 + .dw 0x6ec0, 0xc13e, 0x6eff, 0xc13e, 0x21, 0 + .dw 0x6f40, 0xc13e, 0x6f7f, 0xc13e, 0x21, 0 + .dw 0x6fc0, 0xc13e, 0x6fff, 0xc13e, 0x21, 0 + .dw 0x7040, 0xc13e, 0x707f, 0xc13e, 0x21, 0 + .dw 0x70c0, 0xc13e, 0x70ff, 0xc13e, 0x21, 0 + .dw 0x7140, 0xc13e, 0x717f, 0xc13e, 0x21, 0 + .dw 0x71c0, 0xc13e, 0x71ff, 0xc13e, 0x21, 0 + .dw 0x7240, 0xc13e, 0x727f, 0xc13e, 0x21, 0 + .dw 0x72c0, 0xc13e, 0x72ff, 0xc13e, 0x21, 0 + .dw 0x7340, 0xc13e, 0x737f, 0xc13e, 0x21, 0 + .dw 0x73c0, 0xc13e, 0x73ff, 0xc13e, 0x21, 0 + .dw 0x7440, 0xc13e, 0x747f, 0xc13e, 0x21, 0 + .dw 0x74c0, 0xc13e, 0x74ff, 0xc13e, 0x21, 0 + .dw 0x7540, 0xc13e, 0x757f, 0xc13e, 0x21, 0 + .dw 0x75c0, 0xc13e, 0x75ff, 0xc13e, 0x21, 0 + .dw 0x7640, 0xc13e, 0x767f, 0xc13e, 0x21, 0 + .dw 0x76c0, 0xc13e, 0x76ff, 0xc13e, 0x21, 0 + .dw 0x7740, 0xc13e, 0x777f, 0xc13e, 0x21, 0 + .dw 0x77c0, 0xc13e, 0x77ff, 0xc13e, 0x21, 0 + .dw 0x7840, 0xc13e, 0x787f, 0xc13e, 0x21, 0 + .dw 0x78c0, 0xc13e, 0x78ff, 0xc13e, 0x21, 0 + .dw 0x7940, 0xc13e, 0x797f, 0xc13e, 0x21, 0 + .dw 0x79c0, 0xc13e, 0x7fff, 0xc13e, 0x21, 0 + .dw 0x8040, 0xc13e, 0x807f, 0xc13e, 0x21, 0 + .dw 0x80c0, 0xc13e, 0x80ff, 0xc13e, 0x21, 0 + .dw 0x8140, 0xc13e, 0x817f, 0xc13e, 0x21, 0 + .dw 0x81c0, 0xc13e, 0x81ff, 0xc13e, 0x21, 0 + .dw 0x8240, 0xc13e, 0x827f, 0xc13e, 0x21, 0 + .dw 0x82c0, 0xc13e, 0x82ff, 0xc13e, 0x21, 0 + .dw 0x8340, 0xc13e, 0x837f, 0xc13e, 0x21, 0 + .dw 0x83c0, 0xc13e, 0x83ff, 0xc13e, 0x21, 0 + .dw 0x8440, 0xc13e, 0x847f, 0xc13e, 0x21, 0 + .dw 0x84c0, 0xc13e, 0x84ff, 0xc13e, 0x21, 0 + .dw 0x8540, 0xc13e, 0x857f, 0xc13e, 0x21, 0 + .dw 0x85c0, 0xc13e, 0x85ff, 0xc13e, 0x21, 0 + .dw 0x8640, 0xc13e, 0x867f, 0xc13e, 0x21, 0 + .dw 0x86c0, 0xc13e, 0x86ff, 0xc13e, 0x21, 0 + .dw 0x8740, 0xc13e, 0x877f, 0xc13e, 0x21, 0 + .dw 0x87c0, 0xc13e, 0x87ff, 0xc13e, 0x21, 0 + .dw 0x8840, 0xc13e, 0x887f, 0xc13e, 0x21, 0 + .dw 0x88c0, 0xc13e, 0x88ff, 0xc13e, 0x21, 0 + .dw 0x8940, 0xc13e, 0x897f, 0xc13e, 0x21, 0 + .dw 0x89c0, 0xc13e, 0x89ff, 0xc13e, 0x21, 0 + .dw 0x8a40, 0xc13e, 0x8a7f, 0xc13e, 0x21, 0 + .dw 0x8ac0, 0xc13e, 0x8aff, 0xc13e, 0x21, 0 + .dw 0x8b40, 0xc13e, 0x8b7f, 0xc13e, 0x21, 0 + .dw 0x8bc0, 0xc13e, 0x8bff, 0xc13e, 0x21, 0 + .dw 0x8c40, 0xc13e, 0x8c7f, 0xc13e, 0x21, 0 + .dw 0x8cc0, 0xc13e, 0x8cff, 0xc13e, 0x21, 0 + .dw 0x8d40, 0xc13e, 0x8d7f, 0xc13e, 0x21, 0 + .dw 0x8dc0, 0xc13e, 0x8dff, 0xc13e, 0x21, 0 + .dw 0x8e40, 0xc13e, 0x8e7f, 0xc13e, 0x21, 0 + .dw 0x8ec0, 0xc13e, 0x8eff, 0xc13e, 0x21, 0 + .dw 0x8f40, 0xc13e, 0x8f7f, 0xc13e, 0x21, 0 + .dw 0x8fc0, 0xc13e, 0x8fff, 0xc13e, 0x21, 0 + .dw 0x9040, 0xc13e, 0x907f, 0xc13e, 0x21, 0 + .dw 0x90c0, 0xc13e, 0x90ff, 0xc13e, 0x21, 0 + .dw 0x9140, 0xc13e, 0x917f, 0xc13e, 0x21, 0 + .dw 0x91c0, 0xc13e, 0x91ff, 0xc13e, 0x21, 0 + .dw 0x9240, 0xc13e, 0x927f, 0xc13e, 0x21, 0 + .dw 0x92c0, 0xc13e, 0x92ff, 0xc13e, 0x21, 0 + .dw 0x9340, 0xc13e, 0x937f, 0xc13e, 0x21, 0 + .dw 0x93c0, 0xc13e, 0x93ff, 0xc13e, 0x21, 0 + .dw 0x9440, 0xc13e, 0x947f, 0xc13e, 0x21, 0 + .dw 0x94c0, 0xc13e, 0x94ff, 0xc13e, 0x21, 0 + .dw 0x9540, 0xc13e, 0x957f, 0xc13e, 0x21, 0 + .dw 0x95c0, 0xc13e, 0x95ff, 0xc13e, 0x21, 0 + .dw 0x9640, 0xc13e, 0x967f, 0xc13e, 0x21, 0 + .dw 0x96c0, 0xc13e, 0x96ff, 0xc13e, 0x21, 0 + .dw 0x9740, 0xc13e, 0x977f, 0xc13e, 0x21, 0 + .dw 0x97c0, 0xc13e, 0x97ff, 0xc13e, 0x21, 0 + .dw 0x9840, 0xc13e, 0x987f, 0xc13e, 0x21, 0 + .dw 0x98c0, 0xc13e, 0x98ff, 0xc13e, 0x21, 0 + .dw 0x9940, 0xc13e, 0x997f, 0xc13e, 0x21, 0 + .dw 0x99c0, 0xc13e, 0x9fff, 0xc13e, 0x21, 0 + .dw 0xa040, 0xc13e, 0xa07f, 0xc13e, 0x21, 0 + .dw 0xa0c0, 0xc13e, 0xa0ff, 0xc13e, 0x21, 0 + .dw 0xa140, 0xc13e, 0xa17f, 0xc13e, 0x21, 0 + .dw 0xa1c0, 0xc13e, 0xa1ff, 0xc13e, 0x21, 0 + .dw 0xa240, 0xc13e, 0xa27f, 0xc13e, 0x21, 0 + .dw 0xa2c0, 0xc13e, 0xa2ff, 0xc13e, 0x21, 0 + .dw 0xa340, 0xc13e, 0xa37f, 0xc13e, 0x21, 0 + .dw 0xa3c0, 0xc13e, 0xa3ff, 0xc13e, 0x21, 0 + .dw 0xa440, 0xc13e, 0xa47f, 0xc13e, 0x21, 0 + .dw 0xa4c0, 0xc13e, 0xa4ff, 0xc13e, 0x21, 0 + .dw 0xa540, 0xc13e, 0xa57f, 0xc13e, 0x21, 0 + .dw 0xa5c0, 0xc13e, 0xa5ff, 0xc13e, 0x21, 0 + .dw 0xa640, 0xc13e, 0xa67f, 0xc13e, 0x21, 0 + .dw 0xa6c0, 0xc13e, 0xa6ff, 0xc13e, 0x21, 0 + .dw 0xa740, 0xc13e, 0xa77f, 0xc13e, 0x21, 0 + .dw 0xa7c0, 0xc13e, 0xa7ff, 0xc13e, 0x21, 0 + .dw 0xa840, 0xc13e, 0xa87f, 0xc13e, 0x21, 0 + .dw 0xa8c0, 0xc13e, 0xa8ff, 0xc13e, 0x21, 0 + .dw 0xa940, 0xc13e, 0xa97f, 0xc13e, 0x21, 0 + .dw 0xa9c0, 0xc13e, 0xa9ff, 0xc13e, 0x21, 0 + .dw 0xaa40, 0xc13e, 0xaa7f, 0xc13e, 0x21, 0 + .dw 0xaac0, 0xc13e, 0xaaff, 0xc13e, 0x21, 0 + .dw 0xab40, 0xc13e, 0xab7f, 0xc13e, 0x21, 0 + .dw 0xabc0, 0xc13e, 0xabff, 0xc13e, 0x21, 0 + .dw 0xac40, 0xc13e, 0xac7f, 0xc13e, 0x21, 0 + .dw 0xacc0, 0xc13e, 0xacff, 0xc13e, 0x21, 0 + .dw 0xad40, 0xc13e, 0xad7f, 0xc13e, 0x21, 0 + .dw 0xadc0, 0xc13e, 0xadff, 0xc13e, 0x21, 0 + .dw 0xae40, 0xc13e, 0xae7f, 0xc13e, 0x21, 0 + .dw 0xaec0, 0xc13e, 0xaeff, 0xc13e, 0x21, 0 + .dw 0xaf40, 0xc13e, 0xaf7f, 0xc13e, 0x21, 0 + .dw 0xafc0, 0xc13e, 0xafff, 0xc13e, 0x21, 0 + .dw 0xb040, 0xc13e, 0xb07f, 0xc13e, 0x21, 0 + .dw 0xb0c0, 0xc13e, 0xb0ff, 0xc13e, 0x21, 0 + .dw 0xb140, 0xc13e, 0xb17f, 0xc13e, 0x21, 0 + .dw 0xb1c0, 0xc13e, 0xb1ff, 0xc13e, 0x21, 0 + .dw 0xb240, 0xc13e, 0xb27f, 0xc13e, 0x21, 0 + .dw 0xb2c0, 0xc13e, 0xb2ff, 0xc13e, 0x21, 0 + .dw 0xb340, 0xc13e, 0xb37f, 0xc13e, 0x21, 0 + .dw 0xb3c0, 0xc13e, 0xb3ff, 0xc13e, 0x21, 0 + .dw 0xb440, 0xc13e, 0xb47f, 0xc13e, 0x21, 0 + .dw 0xb4c0, 0xc13e, 0xb4ff, 0xc13e, 0x21, 0 + .dw 0xb540, 0xc13e, 0xb57f, 0xc13e, 0x21, 0 + .dw 0xb5c0, 0xc13e, 0xb5ff, 0xc13e, 0x21, 0 + .dw 0xb640, 0xc13e, 0xb67f, 0xc13e, 0x21, 0 + .dw 0xb6c0, 0xc13e, 0xb6ff, 0xc13e, 0x21, 0 + .dw 0xb740, 0xc13e, 0xb77f, 0xc13e, 0x21, 0 + .dw 0xb7c0, 0xc13e, 0xb7ff, 0xc13e, 0x21, 0 + .dw 0xb840, 0xc13e, 0xb87f, 0xc13e, 0x21, 0 + .dw 0xb8c0, 0xc13e, 0xb8ff, 0xc13e, 0x21, 0 + .dw 0xb940, 0xc13e, 0xb97f, 0xc13e, 0x21, 0 + .dw 0xb9c0, 0xc13e, 0xbfff, 0xc13e, 0x21, 0 + .dw 0xc040, 0xc13e, 0xc07f, 0xc13e, 0x21, 0 + .dw 0xc0c0, 0xc13e, 0xc0ff, 0xc13e, 0x21, 0 + .dw 0xc140, 0xc13e, 0xc17f, 0xc13e, 0x21, 0 + .dw 0xc1c0, 0xc13e, 0xc1ff, 0xc13e, 0x21, 0 + .dw 0xc240, 0xc13e, 0xc27f, 0xc13e, 0x21, 0 + .dw 0xc2c0, 0xc13e, 0xc2ff, 0xc13e, 0x21, 0 + .dw 0xc340, 0xc13e, 0xc37f, 0xc13e, 0x21, 0 + .dw 0xc3c0, 0xc13e, 0xc3ff, 0xc13e, 0x21, 0 + .dw 0xc440, 0xc13e, 0xc47f, 0xc13e, 0x21, 0 + .dw 0xc4c0, 0xc13e, 0xc4ff, 0xc13e, 0x21, 0 + .dw 0xc540, 0xc13e, 0xc57f, 0xc13e, 0x21, 0 + .dw 0xc5c0, 0xc13e, 0xc5ff, 0xc13e, 0x21, 0 + .dw 0xc640, 0xc13e, 0xc67f, 0xc13e, 0x21, 0 + .dw 0xc6c0, 0xc13e, 0xc6ff, 0xc13e, 0x21, 0 + .dw 0xc740, 0xc13e, 0xc77f, 0xc13e, 0x21, 0 + .dw 0xc7c0, 0xc13e, 0xc7ff, 0xc13e, 0x21, 0 + .dw 0xc840, 0xc13e, 0xc87f, 0xc13e, 0x21, 0 + .dw 0xc8c0, 0xc13e, 0xc8ff, 0xc13e, 0x21, 0 + .dw 0xc940, 0xc13e, 0xc97f, 0xc13e, 0x21, 0 + .dw 0xc9c0, 0xc13e, 0xc9ff, 0xc13e, 0x21, 0 + .dw 0xca40, 0xc13e, 0xca7f, 0xc13e, 0x21, 0 + .dw 0xcac0, 0xc13e, 0xcaff, 0xc13e, 0x21, 0 + .dw 0xcb40, 0xc13e, 0xcb7f, 0xc13e, 0x21, 0 + .dw 0xcbc0, 0xc13e, 0xcbff, 0xc13e, 0x21, 0 + .dw 0xcc40, 0xc13e, 0xcc7f, 0xc13e, 0x21, 0 + .dw 0xccc0, 0xc13e, 0xccff, 0xc13e, 0x21, 0 + .dw 0xcd40, 0xc13e, 0xcd7f, 0xc13e, 0x21, 0 + .dw 0xcdc0, 0xc13e, 0xcdff, 0xc13e, 0x21, 0 + .dw 0xce40, 0xc13e, 0xce7f, 0xc13e, 0x21, 0 + .dw 0xcec0, 0xc13e, 0xceff, 0xc13e, 0x21, 0 + .dw 0xcf40, 0xc13e, 0xcf7f, 0xc13e, 0x21, 0 + .dw 0xcfc0, 0xc13e, 0xcfff, 0xc13e, 0x21, 0 + .dw 0xd040, 0xc13e, 0xd07f, 0xc13e, 0x21, 0 + .dw 0xd0c0, 0xc13e, 0xd0ff, 0xc13e, 0x21, 0 + .dw 0xd140, 0xc13e, 0xd17f, 0xc13e, 0x21, 0 + .dw 0xd1c0, 0xc13e, 0xd1ff, 0xc13e, 0x21, 0 + .dw 0xd240, 0xc13e, 0xd27f, 0xc13e, 0x21, 0 + .dw 0xd2c0, 0xc13e, 0xd2ff, 0xc13e, 0x21, 0 + .dw 0xd340, 0xc13e, 0xd37f, 0xc13e, 0x21, 0 + .dw 0xd3c0, 0xc13e, 0xd3ff, 0xc13e, 0x21, 0 + .dw 0xd440, 0xc13e, 0xd47f, 0xc13e, 0x21, 0 + .dw 0xd4c0, 0xc13e, 0xd4ff, 0xc13e, 0x21, 0 + .dw 0xd540, 0xc13e, 0xd57f, 0xc13e, 0x21, 0 + .dw 0xd5c0, 0xc13e, 0xd5ff, 0xc13e, 0x21, 0 + .dw 0xd640, 0xc13e, 0xd67f, 0xc13e, 0x21, 0 + .dw 0xd6c0, 0xc13e, 0xd6ff, 0xc13e, 0x21, 0 + .dw 0xd740, 0xc13e, 0xd77f, 0xc13e, 0x21, 0 + .dw 0xd7c0, 0xc13e, 0xd7ff, 0xc13e, 0x21, 0 + .dw 0xd840, 0xc13e, 0xd87f, 0xc13e, 0x21, 0 + .dw 0xd8c0, 0xc13e, 0xd8ff, 0xc13e, 0x21, 0 + .dw 0xd940, 0xc13e, 0xd97f, 0xc13e, 0x21, 0 + .dw 0xd9c0, 0xc13e, 0xdfff, 0xc13e, 0x21, 0 + .dw 0xe040, 0xc13e, 0xe07f, 0xc13e, 0x21, 0 + .dw 0xe0c0, 0xc13e, 0xe0ff, 0xc13e, 0x21, 0 + .dw 0xe140, 0xc13e, 0xe17f, 0xc13e, 0x21, 0 + .dw 0xe1c0, 0xc13e, 0xe1ff, 0xc13e, 0x21, 0 + .dw 0xe240, 0xc13e, 0xe27f, 0xc13e, 0x21, 0 + .dw 0xe2c0, 0xc13e, 0xe2ff, 0xc13e, 0x21, 0 + .dw 0xe340, 0xc13e, 0xe37f, 0xc13e, 0x21, 0 + .dw 0xe3c0, 0xc13e, 0xe3ff, 0xc13e, 0x21, 0 + .dw 0xe440, 0xc13e, 0xe47f, 0xc13e, 0x21, 0 + .dw 0xe4c0, 0xc13e, 0xe4ff, 0xc13e, 0x21, 0 + .dw 0xe540, 0xc13e, 0xe57f, 0xc13e, 0x21, 0 + .dw 0xe5c0, 0xc13e, 0xe5ff, 0xc13e, 0x21, 0 + .dw 0xe640, 0xc13e, 0xe67f, 0xc13e, 0x21, 0 + .dw 0xe6c0, 0xc13e, 0xe6ff, 0xc13e, 0x21, 0 + .dw 0xe740, 0xc13e, 0xe77f, 0xc13e, 0x21, 0 + .dw 0xe7c0, 0xc13e, 0xe7ff, 0xc13e, 0x21, 0 + .dw 0xe840, 0xc13e, 0xe87f, 0xc13e, 0x21, 0 + .dw 0xe8c0, 0xc13e, 0xe8ff, 0xc13e, 0x21, 0 + .dw 0xe940, 0xc13e, 0xe97f, 0xc13e, 0x21, 0 + .dw 0xe9c0, 0xc13e, 0xe9ff, 0xc13e, 0x21, 0 + .dw 0xea40, 0xc13e, 0xea7f, 0xc13e, 0x21, 0 + .dw 0xeac0, 0xc13e, 0xeaff, 0xc13e, 0x21, 0 + .dw 0xeb40, 0xc13e, 0xeb7f, 0xc13e, 0x21, 0 + .dw 0xebc0, 0xc13e, 0xebff, 0xc13e, 0x21, 0 + .dw 0xec40, 0xc13e, 0xec7f, 0xc13e, 0x21, 0 + .dw 0xecc0, 0xc13e, 0xecff, 0xc13e, 0x21, 0 + .dw 0xed40, 0xc13e, 0xed7f, 0xc13e, 0x21, 0 + .dw 0xedc0, 0xc13e, 0xedff, 0xc13e, 0x21, 0 + .dw 0xee40, 0xc13e, 0xee7f, 0xc13e, 0x21, 0 + .dw 0xeec0, 0xc13e, 0xeeff, 0xc13e, 0x21, 0 + .dw 0xef40, 0xc13e, 0xef7f, 0xc13e, 0x21, 0 + .dw 0xefc0, 0xc13e, 0xefff, 0xc13e, 0x21, 0 + .dw 0xf040, 0xc13e, 0xf07f, 0xc13e, 0x21, 0 + .dw 0xf0c0, 0xc13e, 0xf0ff, 0xc13e, 0x21, 0 + .dw 0xf140, 0xc13e, 0xf17f, 0xc13e, 0x21, 0 + .dw 0xf1c0, 0xc13e, 0xf1ff, 0xc13e, 0x21, 0 + .dw 0xf240, 0xc13e, 0xf27f, 0xc13e, 0x21, 0 + .dw 0xf2c0, 0xc13e, 0xf2ff, 0xc13e, 0x21, 0 + .dw 0xf340, 0xc13e, 0xf37f, 0xc13e, 0x21, 0 + .dw 0xf3c0, 0xc13e, 0xf3ff, 0xc13e, 0x21, 0 + .dw 0xf440, 0xc13e, 0xf47f, 0xc13e, 0x21, 0 + .dw 0xf4c0, 0xc13e, 0xf4ff, 0xc13e, 0x21, 0 + .dw 0xf540, 0xc13e, 0xf57f, 0xc13e, 0x21, 0 + .dw 0xf5c0, 0xc13e, 0xf5ff, 0xc13e, 0x21, 0 + .dw 0xf640, 0xc13e, 0xf67f, 0xc13e, 0x21, 0 + .dw 0xf6c0, 0xc13e, 0xf6ff, 0xc13e, 0x21, 0 + .dw 0xf740, 0xc13e, 0xf77f, 0xc13e, 0x21, 0 + .dw 0xf7c0, 0xc13e, 0xf7ff, 0xc13e, 0x21, 0 + .dw 0xf840, 0xc13e, 0xf87f, 0xc13e, 0x21, 0 + .dw 0xf8c0, 0xc13e, 0xf8ff, 0xc13e, 0x21, 0 + .dw 0xf940, 0xc13e, 0xf97f, 0xc13e, 0x21, 0 + .dw 0xf9c0, 0xc13e, 0xffff, 0xc13e, 0x21, 0 + .dw 0x0040, 0xc13f, 0x007f, 0xc13f, 0x21, 0 + .dw 0x00c0, 0xc13f, 0x00ff, 0xc13f, 0x21, 0 + .dw 0x0140, 0xc13f, 0x017f, 0xc13f, 0x21, 0 + .dw 0x01c0, 0xc13f, 0x01ff, 0xc13f, 0x21, 0 + .dw 0x0240, 0xc13f, 0x027f, 0xc13f, 0x21, 0 + .dw 0x02c0, 0xc13f, 0x02ff, 0xc13f, 0x21, 0 + .dw 0x0340, 0xc13f, 0x037f, 0xc13f, 0x21, 0 + .dw 0x03c0, 0xc13f, 0x03ff, 0xc13f, 0x21, 0 + .dw 0x0440, 0xc13f, 0x047f, 0xc13f, 0x21, 0 + .dw 0x04c0, 0xc13f, 0x04ff, 0xc13f, 0x21, 0 + .dw 0x0540, 0xc13f, 0x057f, 0xc13f, 0x21, 0 + .dw 0x05c0, 0xc13f, 0x05ff, 0xc13f, 0x21, 0 + .dw 0x0640, 0xc13f, 0x067f, 0xc13f, 0x21, 0 + .dw 0x06c0, 0xc13f, 0x06ff, 0xc13f, 0x21, 0 + .dw 0x0740, 0xc13f, 0x077f, 0xc13f, 0x21, 0 + .dw 0x07c0, 0xc13f, 0x07ff, 0xc13f, 0x21, 0 + .dw 0x0840, 0xc13f, 0x087f, 0xc13f, 0x21, 0 + .dw 0x08c0, 0xc13f, 0x08ff, 0xc13f, 0x21, 0 + .dw 0x0940, 0xc13f, 0x097f, 0xc13f, 0x21, 0 + .dw 0x09c0, 0xc13f, 0x09ff, 0xc13f, 0x21, 0 + .dw 0x0a40, 0xc13f, 0x0a7f, 0xc13f, 0x21, 0 + .dw 0x0ac0, 0xc13f, 0x0aff, 0xc13f, 0x21, 0 + .dw 0x0b40, 0xc13f, 0x0b7f, 0xc13f, 0x21, 0 + .dw 0x0bc0, 0xc13f, 0x0bff, 0xc13f, 0x21, 0 + .dw 0x0c40, 0xc13f, 0x0c7f, 0xc13f, 0x21, 0 + .dw 0x0cc0, 0xc13f, 0x0cff, 0xc13f, 0x21, 0 + .dw 0x0d40, 0xc13f, 0x0d7f, 0xc13f, 0x21, 0 + .dw 0x0dc0, 0xc13f, 0x0dff, 0xc13f, 0x21, 0 + .dw 0x0e40, 0xc13f, 0x0e7f, 0xc13f, 0x21, 0 + .dw 0x0ec0, 0xc13f, 0x0eff, 0xc13f, 0x21, 0 + .dw 0x0f40, 0xc13f, 0x0f7f, 0xc13f, 0x21, 0 + .dw 0x0fc0, 0xc13f, 0x0fff, 0xc13f, 0x21, 0 + .dw 0x1040, 0xc13f, 0x107f, 0xc13f, 0x21, 0 + .dw 0x10c0, 0xc13f, 0x10ff, 0xc13f, 0x21, 0 + .dw 0x1140, 0xc13f, 0x117f, 0xc13f, 0x21, 0 + .dw 0x11c0, 0xc13f, 0x11ff, 0xc13f, 0x21, 0 + .dw 0x1240, 0xc13f, 0x127f, 0xc13f, 0x21, 0 + .dw 0x12c0, 0xc13f, 0x12ff, 0xc13f, 0x21, 0 + .dw 0x1340, 0xc13f, 0x137f, 0xc13f, 0x21, 0 + .dw 0x13c0, 0xc13f, 0x13ff, 0xc13f, 0x21, 0 + .dw 0x1440, 0xc13f, 0x147f, 0xc13f, 0x21, 0 + .dw 0x14c0, 0xc13f, 0x14ff, 0xc13f, 0x21, 0 + .dw 0x1540, 0xc13f, 0x157f, 0xc13f, 0x21, 0 + .dw 0x15c0, 0xc13f, 0x15ff, 0xc13f, 0x21, 0 + .dw 0x1640, 0xc13f, 0x167f, 0xc13f, 0x21, 0 + .dw 0x16c0, 0xc13f, 0x16ff, 0xc13f, 0x21, 0 + .dw 0x1740, 0xc13f, 0x177f, 0xc13f, 0x21, 0 + .dw 0x17c0, 0xc13f, 0x17ff, 0xc13f, 0x21, 0 + .dw 0x1840, 0xc13f, 0x187f, 0xc13f, 0x21, 0 + .dw 0x18c0, 0xc13f, 0x18ff, 0xc13f, 0x21, 0 + .dw 0x1940, 0xc13f, 0x197f, 0xc13f, 0x21, 0 + .dw 0x19c0, 0xc13f, 0x1fff, 0xc13f, 0x21, 0 + .dw 0x2040, 0xc13f, 0x207f, 0xc13f, 0x21, 0 + .dw 0x20c0, 0xc13f, 0x20ff, 0xc13f, 0x21, 0 + .dw 0x2140, 0xc13f, 0x217f, 0xc13f, 0x21, 0 + .dw 0x21c0, 0xc13f, 0x21ff, 0xc13f, 0x21, 0 + .dw 0x2240, 0xc13f, 0x227f, 0xc13f, 0x21, 0 + .dw 0x22c0, 0xc13f, 0x22ff, 0xc13f, 0x21, 0 + .dw 0x2340, 0xc13f, 0x237f, 0xc13f, 0x21, 0 + .dw 0x23c0, 0xc13f, 0x23ff, 0xc13f, 0x21, 0 + .dw 0x2440, 0xc13f, 0x247f, 0xc13f, 0x21, 0 + .dw 0x24c0, 0xc13f, 0x24ff, 0xc13f, 0x21, 0 + .dw 0x2540, 0xc13f, 0x257f, 0xc13f, 0x21, 0 + .dw 0x25c0, 0xc13f, 0x25ff, 0xc13f, 0x21, 0 + .dw 0x2640, 0xc13f, 0x267f, 0xc13f, 0x21, 0 + .dw 0x26c0, 0xc13f, 0x26ff, 0xc13f, 0x21, 0 + .dw 0x2740, 0xc13f, 0x277f, 0xc13f, 0x21, 0 + .dw 0x27c0, 0xc13f, 0x27ff, 0xc13f, 0x21, 0 + .dw 0x2840, 0xc13f, 0x287f, 0xc13f, 0x21, 0 + .dw 0x28c0, 0xc13f, 0x28ff, 0xc13f, 0x21, 0 + .dw 0x2940, 0xc13f, 0x297f, 0xc13f, 0x21, 0 + .dw 0x29c0, 0xc13f, 0x29ff, 0xc13f, 0x21, 0 + .dw 0x2a40, 0xc13f, 0x2a7f, 0xc13f, 0x21, 0 + .dw 0x2ac0, 0xc13f, 0x2aff, 0xc13f, 0x21, 0 + .dw 0x2b40, 0xc13f, 0x2b7f, 0xc13f, 0x21, 0 + .dw 0x2bc0, 0xc13f, 0x2bff, 0xc13f, 0x21, 0 + .dw 0x2c40, 0xc13f, 0x2c7f, 0xc13f, 0x21, 0 + .dw 0x2cc0, 0xc13f, 0x2cff, 0xc13f, 0x21, 0 + .dw 0x2d40, 0xc13f, 0x2d7f, 0xc13f, 0x21, 0 + .dw 0x2dc0, 0xc13f, 0x2dff, 0xc13f, 0x21, 0 + .dw 0x2e40, 0xc13f, 0x2e7f, 0xc13f, 0x21, 0 + .dw 0x2ec0, 0xc13f, 0x2eff, 0xc13f, 0x21, 0 + .dw 0x2f40, 0xc13f, 0x2f7f, 0xc13f, 0x21, 0 + .dw 0x2fc0, 0xc13f, 0x2fff, 0xc13f, 0x21, 0 + .dw 0x3040, 0xc13f, 0x307f, 0xc13f, 0x21, 0 + .dw 0x30c0, 0xc13f, 0x30ff, 0xc13f, 0x21, 0 + .dw 0x3140, 0xc13f, 0x317f, 0xc13f, 0x21, 0 + .dw 0x31c0, 0xc13f, 0x31ff, 0xc13f, 0x21, 0 + .dw 0x3240, 0xc13f, 0x327f, 0xc13f, 0x21, 0 + .dw 0x32c0, 0xc13f, 0x32ff, 0xc13f, 0x21, 0 + .dw 0x3340, 0xc13f, 0x337f, 0xc13f, 0x21, 0 + .dw 0x33c0, 0xc13f, 0x33ff, 0xc13f, 0x21, 0 + .dw 0x3440, 0xc13f, 0x347f, 0xc13f, 0x21, 0 + .dw 0x34c0, 0xc13f, 0x34ff, 0xc13f, 0x21, 0 + .dw 0x3540, 0xc13f, 0x357f, 0xc13f, 0x21, 0 + .dw 0x35c0, 0xc13f, 0x35ff, 0xc13f, 0x21, 0 + .dw 0x3640, 0xc13f, 0x367f, 0xc13f, 0x21, 0 + .dw 0x36c0, 0xc13f, 0x36ff, 0xc13f, 0x21, 0 + .dw 0x3740, 0xc13f, 0x377f, 0xc13f, 0x21, 0 + .dw 0x37c0, 0xc13f, 0x37ff, 0xc13f, 0x21, 0 + .dw 0x3840, 0xc13f, 0x387f, 0xc13f, 0x21, 0 + .dw 0x38c0, 0xc13f, 0x38ff, 0xc13f, 0x21, 0 + .dw 0x3940, 0xc13f, 0x397f, 0xc13f, 0x21, 0 + .dw 0x39c0, 0xc13f, 0x1fff, 0xc160, 0x21, 0 + .dw 0x3a00, 0xc160, 0x5fff, 0xc160, 0x21, 0 + .dw 0x7a00, 0xc160, 0x9fff, 0xc160, 0x21, 0 + .dw 0xba00, 0xc160, 0xdfff, 0xc160, 0x21, 0 + .dw 0xfa00, 0xc160, 0x1fff, 0xc161, 0x21, 0 + .dw 0x3a00, 0xc161, 0x5fff, 0xc161, 0x21, 0 + .dw 0x7a00, 0xc161, 0x9fff, 0xc161, 0x21, 0 + .dw 0xba00, 0xc161, 0xdfff, 0xc161, 0x21, 0 + .dw 0xfa00, 0xc161, 0x1fff, 0xc162, 0x21, 0 + .dw 0x3a00, 0xc162, 0x5fff, 0xc162, 0x21, 0 + .dw 0x7a00, 0xc162, 0x9fff, 0xc162, 0x21, 0 + .dw 0xba00, 0xc162, 0xdfff, 0xc162, 0x21, 0 + .dw 0xfa00, 0xc162, 0x1fff, 0xc163, 0x21, 0 + .dw 0x3a00, 0xc163, 0xffff, 0xc163, 0x21, 0 + .dw 0x1a00, 0xc164, 0x1fff, 0xc164, 0x21, 0 + .dw 0x3a00, 0xc164, 0x3fff, 0xc164, 0x21, 0 + .dw 0x5a00, 0xc164, 0x5fff, 0xc164, 0x21, 0 + .dw 0x7a00, 0xc164, 0x7fff, 0xc164, 0x21, 0 + .dw 0x9a00, 0xc164, 0x9fff, 0xc164, 0x21, 0 + .dw 0xba00, 0xc164, 0xbfff, 0xc164, 0x21, 0 + .dw 0xda00, 0xc164, 0xdfff, 0xc164, 0x21, 0 + .dw 0xfa00, 0xc164, 0xffff, 0xc164, 0x21, 0 + .dw 0x1a00, 0xc165, 0x1fff, 0xc165, 0x21, 0 + .dw 0x3a00, 0xc165, 0x3fff, 0xc165, 0x21, 0 + .dw 0x5a00, 0xc165, 0x5fff, 0xc165, 0x21, 0 + .dw 0x7a00, 0xc165, 0x7fff, 0xc165, 0x21, 0 + .dw 0x9a00, 0xc165, 0x9fff, 0xc165, 0x21, 0 + .dw 0xba00, 0xc165, 0xbfff, 0xc165, 0x21, 0 + .dw 0xda00, 0xc165, 0xdfff, 0xc165, 0x21, 0 + .dw 0xfa00, 0xc165, 0xffff, 0xc165, 0x21, 0 + .dw 0x1a00, 0xc166, 0x1fff, 0xc166, 0x21, 0 + .dw 0x3a00, 0xc166, 0x3fff, 0xc166, 0x21, 0 + .dw 0x5a00, 0xc166, 0x5fff, 0xc166, 0x21, 0 + .dw 0x7a00, 0xc166, 0x7fff, 0xc166, 0x21, 0 + .dw 0x9a00, 0xc166, 0x9fff, 0xc166, 0x21, 0 + .dw 0xba00, 0xc166, 0xbfff, 0xc166, 0x21, 0 + .dw 0xda00, 0xc166, 0xdfff, 0xc166, 0x21, 0 + .dw 0xfa00, 0xc166, 0xffff, 0xc166, 0x21, 0 + .dw 0x1a00, 0xc167, 0x1fff, 0xc167, 0x21, 0 + .dw 0x3a00, 0xc167, 0x1fff, 0xc170, 0x21, 0 + .dw 0x3a00, 0xc170, 0x5fff, 0xc170, 0x21, 0 + .dw 0x7a00, 0xc170, 0x9fff, 0xc170, 0x21, 0 + .dw 0xba00, 0xc170, 0xdfff, 0xc170, 0x21, 0 + .dw 0xfa00, 0xc170, 0x1fff, 0xc171, 0x21, 0 + .dw 0x3a00, 0xc171, 0x5fff, 0xc171, 0x21, 0 + .dw 0x7a00, 0xc171, 0x9fff, 0xc171, 0x21, 0 + .dw 0xba00, 0xc171, 0xdfff, 0xc171, 0x21, 0 + .dw 0xfa00, 0xc171, 0x1fff, 0xc172, 0x21, 0 + .dw 0x3a00, 0xc172, 0x5fff, 0xc172, 0x21, 0 + .dw 0x7a00, 0xc172, 0x9fff, 0xc172, 0x21, 0 + .dw 0xba00, 0xc172, 0xdfff, 0xc172, 0x21, 0 + .dw 0xfa00, 0xc172, 0xffff, 0xc173, 0x21, 0 + .dw 0x1a00, 0xc174, 0x1fff, 0xc174, 0x21, 0 + .dw 0x3a00, 0xc174, 0x3fff, 0xc174, 0x21, 0 + .dw 0x5a00, 0xc174, 0x5fff, 0xc174, 0x21, 0 + .dw 0x7a00, 0xc174, 0x7fff, 0xc174, 0x21, 0 + .dw 0x9a00, 0xc174, 0x9fff, 0xc174, 0x21, 0 + .dw 0xba00, 0xc174, 0xbfff, 0xc174, 0x21, 0 + .dw 0xda00, 0xc174, 0xdfff, 0xc174, 0x21, 0 + .dw 0xfa00, 0xc174, 0xffff, 0xc174, 0x21, 0 + .dw 0x1a00, 0xc175, 0x1fff, 0xc175, 0x21, 0 + .dw 0x3a00, 0xc175, 0x3fff, 0xc175, 0x21, 0 + .dw 0x5a00, 0xc175, 0x5fff, 0xc175, 0x21, 0 + .dw 0x7a00, 0xc175, 0x7fff, 0xc175, 0x21, 0 + .dw 0x9a00, 0xc175, 0x9fff, 0xc175, 0x21, 0 + .dw 0xba00, 0xc175, 0xbfff, 0xc175, 0x21, 0 + .dw 0xda00, 0xc175, 0xdfff, 0xc175, 0x21, 0 + .dw 0xfa00, 0xc175, 0xffff, 0xc175, 0x21, 0 + .dw 0x1a00, 0xc176, 0x1fff, 0xc176, 0x21, 0 + .dw 0x3a00, 0xc176, 0x3fff, 0xc176, 0x21, 0 + .dw 0x5a00, 0xc176, 0x5fff, 0xc176, 0x21, 0 + .dw 0x7a00, 0xc176, 0x7fff, 0xc176, 0x21, 0 + .dw 0x9a00, 0xc176, 0x9fff, 0xc176, 0x21, 0 + .dw 0xba00, 0xc176, 0xbfff, 0xc176, 0x21, 0 + .dw 0xda00, 0xc176, 0xdfff, 0xc176, 0x21, 0 + .dw 0xfa00, 0xc176, 0xffff, 0xc176, 0x21, 0 + .dw 0x1a00, 0xc177, 0x1fff, 0xc177, 0x21, 0 + .dw 0x3a00, 0xc177, 0x1fff, 0xc180, 0x21, 0 + .dw 0x3a00, 0xc180, 0x5fff, 0xc180, 0x21, 0 + .dw 0x7a00, 0xc180, 0x9fff, 0xc180, 0x21, 0 + .dw 0xba00, 0xc180, 0xdfff, 0xc180, 0x21, 0 + .dw 0xfa00, 0xc180, 0x1fff, 0xc181, 0x21, 0 + .dw 0x3a00, 0xc181, 0x5fff, 0xc181, 0x21, 0 + .dw 0x7a00, 0xc181, 0x9fff, 0xc181, 0x21, 0 + .dw 0xba00, 0xc181, 0xdfff, 0xc181, 0x21, 0 + .dw 0xfa00, 0xc181, 0x1fff, 0xc182, 0x21, 0 + .dw 0x3a00, 0xc182, 0x5fff, 0xc182, 0x21, 0 + .dw 0x7a00, 0xc182, 0x9fff, 0xc182, 0x21, 0 + .dw 0xba00, 0xc182, 0xdfff, 0xc182, 0x21, 0 + .dw 0xfa00, 0xc182, 0x1fff, 0xc183, 0x21, 0 + .dw 0x3a00, 0xc183, 0xffff, 0xc183, 0x21, 0 + .dw 0x1a00, 0xc184, 0x1fff, 0xc184, 0x21, 0 + .dw 0x3a00, 0xc184, 0x3fff, 0xc184, 0x21, 0 + .dw 0x5a00, 0xc184, 0x5fff, 0xc184, 0x21, 0 + .dw 0x7a00, 0xc184, 0x7fff, 0xc184, 0x21, 0 + .dw 0x9a00, 0xc184, 0x9fff, 0xc184, 0x21, 0 + .dw 0xba00, 0xc184, 0xbfff, 0xc184, 0x21, 0 + .dw 0xda00, 0xc184, 0xdfff, 0xc184, 0x21, 0 + .dw 0xfa00, 0xc184, 0xffff, 0xc184, 0x21, 0 + .dw 0x1a00, 0xc185, 0x1fff, 0xc185, 0x21, 0 + .dw 0x3a00, 0xc185, 0x3fff, 0xc185, 0x21, 0 + .dw 0x5a00, 0xc185, 0x5fff, 0xc185, 0x21, 0 + .dw 0x7a00, 0xc185, 0x7fff, 0xc185, 0x21, 0 + .dw 0x9a00, 0xc185, 0x9fff, 0xc185, 0x21, 0 + .dw 0xba00, 0xc185, 0xbfff, 0xc185, 0x21, 0 + .dw 0xda00, 0xc185, 0xdfff, 0xc185, 0x21, 0 + .dw 0xfa00, 0xc185, 0xffff, 0xc185, 0x21, 0 + .dw 0x1a00, 0xc186, 0x1fff, 0xc186, 0x21, 0 + .dw 0x3a00, 0xc186, 0x3fff, 0xc186, 0x21, 0 + .dw 0x5a00, 0xc186, 0x5fff, 0xc186, 0x21, 0 + .dw 0x7a00, 0xc186, 0x7fff, 0xc186, 0x21, 0 + .dw 0x9a00, 0xc186, 0x9fff, 0xc186, 0x21, 0 + .dw 0xba00, 0xc186, 0xbfff, 0xc186, 0x21, 0 + .dw 0xda00, 0xc186, 0xdfff, 0xc186, 0x21, 0 + .dw 0xfa00, 0xc186, 0xffff, 0xc186, 0x21, 0 + .dw 0x1a00, 0xc187, 0x1fff, 0xc187, 0x21, 0 + .dw 0x3a00, 0xc187, 0x1fff, 0xc188, 0x21, 0 + .dw 0x2040, 0xc188, 0x207f, 0xc188, 0x21, 0 + .dw 0x20c0, 0xc188, 0x20ff, 0xc188, 0x21, 0 + .dw 0x2140, 0xc188, 0x217f, 0xc188, 0x21, 0 + .dw 0x21c0, 0xc188, 0x21ff, 0xc188, 0x21, 0 + .dw 0x2240, 0xc188, 0x227f, 0xc188, 0x21, 0 + .dw 0x22c0, 0xc188, 0x22ff, 0xc188, 0x21, 0 + .dw 0x2340, 0xc188, 0x237f, 0xc188, 0x21, 0 + .dw 0x23c0, 0xc188, 0x23ff, 0xc188, 0x21, 0 + .dw 0x2440, 0xc188, 0x247f, 0xc188, 0x21, 0 + .dw 0x24c0, 0xc188, 0x24ff, 0xc188, 0x21, 0 + .dw 0x2540, 0xc188, 0x257f, 0xc188, 0x21, 0 + .dw 0x25c0, 0xc188, 0x25ff, 0xc188, 0x21, 0 + .dw 0x2640, 0xc188, 0x267f, 0xc188, 0x21, 0 + .dw 0x26c0, 0xc188, 0x26ff, 0xc188, 0x21, 0 + .dw 0x2740, 0xc188, 0x277f, 0xc188, 0x21, 0 + .dw 0x27c0, 0xc188, 0x27ff, 0xc188, 0x21, 0 + .dw 0x2840, 0xc188, 0x287f, 0xc188, 0x21, 0 + .dw 0x28c0, 0xc188, 0x28ff, 0xc188, 0x21, 0 + .dw 0x2940, 0xc188, 0x297f, 0xc188, 0x21, 0 + .dw 0x29c0, 0xc188, 0x29ff, 0xc188, 0x21, 0 + .dw 0x2a40, 0xc188, 0x2a7f, 0xc188, 0x21, 0 + .dw 0x2ac0, 0xc188, 0x2aff, 0xc188, 0x21, 0 + .dw 0x2b40, 0xc188, 0x2b7f, 0xc188, 0x21, 0 + .dw 0x2bc0, 0xc188, 0x2bff, 0xc188, 0x21, 0 + .dw 0x2c40, 0xc188, 0x2c7f, 0xc188, 0x21, 0 + .dw 0x2cc0, 0xc188, 0x2cff, 0xc188, 0x21, 0 + .dw 0x2d40, 0xc188, 0x2d7f, 0xc188, 0x21, 0 + .dw 0x2dc0, 0xc188, 0x2dff, 0xc188, 0x21, 0 + .dw 0x2e40, 0xc188, 0x2e7f, 0xc188, 0x21, 0 + .dw 0x2ec0, 0xc188, 0x2eff, 0xc188, 0x21, 0 + .dw 0x2f40, 0xc188, 0x2f7f, 0xc188, 0x21, 0 + .dw 0x2fc0, 0xc188, 0x2fff, 0xc188, 0x21, 0 + .dw 0x3040, 0xc188, 0x307f, 0xc188, 0x21, 0 + .dw 0x30c0, 0xc188, 0x30ff, 0xc188, 0x21, 0 + .dw 0x3140, 0xc188, 0x317f, 0xc188, 0x21, 0 + .dw 0x31c0, 0xc188, 0x31ff, 0xc188, 0x21, 0 + .dw 0x3240, 0xc188, 0x327f, 0xc188, 0x21, 0 + .dw 0x32c0, 0xc188, 0x32ff, 0xc188, 0x21, 0 + .dw 0x3340, 0xc188, 0x337f, 0xc188, 0x21, 0 + .dw 0x33c0, 0xc188, 0x33ff, 0xc188, 0x21, 0 + .dw 0x3440, 0xc188, 0x347f, 0xc188, 0x21, 0 + .dw 0x34c0, 0xc188, 0x34ff, 0xc188, 0x21, 0 + .dw 0x3540, 0xc188, 0x357f, 0xc188, 0x21, 0 + .dw 0x35c0, 0xc188, 0x35ff, 0xc188, 0x21, 0 + .dw 0x3640, 0xc188, 0x367f, 0xc188, 0x21, 0 + .dw 0x36c0, 0xc188, 0x36ff, 0xc188, 0x21, 0 + .dw 0x3740, 0xc188, 0x377f, 0xc188, 0x21, 0 + .dw 0x37c0, 0xc188, 0x37ff, 0xc188, 0x21, 0 + .dw 0x3840, 0xc188, 0x387f, 0xc188, 0x21, 0 + .dw 0x38c0, 0xc188, 0x38ff, 0xc188, 0x21, 0 + .dw 0x3940, 0xc188, 0x397f, 0xc188, 0x21, 0 + .dw 0x39c0, 0xc188, 0x5fff, 0xc188, 0x21, 0 + .dw 0x6040, 0xc188, 0x607f, 0xc188, 0x21, 0 + .dw 0x60c0, 0xc188, 0x60ff, 0xc188, 0x21, 0 + .dw 0x6140, 0xc188, 0x617f, 0xc188, 0x21, 0 + .dw 0x61c0, 0xc188, 0x61ff, 0xc188, 0x21, 0 + .dw 0x6240, 0xc188, 0x627f, 0xc188, 0x21, 0 + .dw 0x62c0, 0xc188, 0x62ff, 0xc188, 0x21, 0 + .dw 0x6340, 0xc188, 0x637f, 0xc188, 0x21, 0 + .dw 0x63c0, 0xc188, 0x63ff, 0xc188, 0x21, 0 + .dw 0x6440, 0xc188, 0x647f, 0xc188, 0x21, 0 + .dw 0x64c0, 0xc188, 0x64ff, 0xc188, 0x21, 0 + .dw 0x6540, 0xc188, 0x657f, 0xc188, 0x21, 0 + .dw 0x65c0, 0xc188, 0x65ff, 0xc188, 0x21, 0 + .dw 0x6640, 0xc188, 0x667f, 0xc188, 0x21, 0 + .dw 0x66c0, 0xc188, 0x66ff, 0xc188, 0x21, 0 + .dw 0x6740, 0xc188, 0x677f, 0xc188, 0x21, 0 + .dw 0x67c0, 0xc188, 0x67ff, 0xc188, 0x21, 0 + .dw 0x6840, 0xc188, 0x687f, 0xc188, 0x21, 0 + .dw 0x68c0, 0xc188, 0x68ff, 0xc188, 0x21, 0 + .dw 0x6940, 0xc188, 0x697f, 0xc188, 0x21, 0 + .dw 0x69c0, 0xc188, 0x69ff, 0xc188, 0x21, 0 + .dw 0x6a40, 0xc188, 0x6a7f, 0xc188, 0x21, 0 + .dw 0x6ac0, 0xc188, 0x6aff, 0xc188, 0x21, 0 + .dw 0x6b40, 0xc188, 0x6b7f, 0xc188, 0x21, 0 + .dw 0x6bc0, 0xc188, 0x6bff, 0xc188, 0x21, 0 + .dw 0x6c40, 0xc188, 0x6c7f, 0xc188, 0x21, 0 + .dw 0x6cc0, 0xc188, 0x6cff, 0xc188, 0x21, 0 + .dw 0x6d40, 0xc188, 0x6d7f, 0xc188, 0x21, 0 + .dw 0x6dc0, 0xc188, 0x6dff, 0xc188, 0x21, 0 + .dw 0x6e40, 0xc188, 0x6e7f, 0xc188, 0x21, 0 + .dw 0x6ec0, 0xc188, 0x6eff, 0xc188, 0x21, 0 + .dw 0x6f40, 0xc188, 0x6f7f, 0xc188, 0x21, 0 + .dw 0x6fc0, 0xc188, 0x6fff, 0xc188, 0x21, 0 + .dw 0x7040, 0xc188, 0x707f, 0xc188, 0x21, 0 + .dw 0x70c0, 0xc188, 0x70ff, 0xc188, 0x21, 0 + .dw 0x7140, 0xc188, 0x717f, 0xc188, 0x21, 0 + .dw 0x71c0, 0xc188, 0x71ff, 0xc188, 0x21, 0 + .dw 0x7240, 0xc188, 0x727f, 0xc188, 0x21, 0 + .dw 0x72c0, 0xc188, 0x72ff, 0xc188, 0x21, 0 + .dw 0x7340, 0xc188, 0x737f, 0xc188, 0x21, 0 + .dw 0x73c0, 0xc188, 0x73ff, 0xc188, 0x21, 0 + .dw 0x7440, 0xc188, 0x747f, 0xc188, 0x21, 0 + .dw 0x74c0, 0xc188, 0x74ff, 0xc188, 0x21, 0 + .dw 0x7540, 0xc188, 0x757f, 0xc188, 0x21, 0 + .dw 0x75c0, 0xc188, 0x75ff, 0xc188, 0x21, 0 + .dw 0x7640, 0xc188, 0x767f, 0xc188, 0x21, 0 + .dw 0x76c0, 0xc188, 0x76ff, 0xc188, 0x21, 0 + .dw 0x7740, 0xc188, 0x777f, 0xc188, 0x21, 0 + .dw 0x77c0, 0xc188, 0x77ff, 0xc188, 0x21, 0 + .dw 0x7840, 0xc188, 0x787f, 0xc188, 0x21, 0 + .dw 0x78c0, 0xc188, 0x78ff, 0xc188, 0x21, 0 + .dw 0x7940, 0xc188, 0x797f, 0xc188, 0x21, 0 + .dw 0x79c0, 0xc188, 0x9fff, 0xc188, 0x21, 0 + .dw 0xa040, 0xc188, 0xa07f, 0xc188, 0x21, 0 + .dw 0xa0c0, 0xc188, 0xa0ff, 0xc188, 0x21, 0 + .dw 0xa140, 0xc188, 0xa17f, 0xc188, 0x21, 0 + .dw 0xa1c0, 0xc188, 0xa1ff, 0xc188, 0x21, 0 + .dw 0xa240, 0xc188, 0xa27f, 0xc188, 0x21, 0 + .dw 0xa2c0, 0xc188, 0xa2ff, 0xc188, 0x21, 0 + .dw 0xa340, 0xc188, 0xa37f, 0xc188, 0x21, 0 + .dw 0xa3c0, 0xc188, 0xa3ff, 0xc188, 0x21, 0 + .dw 0xa440, 0xc188, 0xa47f, 0xc188, 0x21, 0 + .dw 0xa4c0, 0xc188, 0xa4ff, 0xc188, 0x21, 0 + .dw 0xa540, 0xc188, 0xa57f, 0xc188, 0x21, 0 + .dw 0xa5c0, 0xc188, 0xa5ff, 0xc188, 0x21, 0 + .dw 0xa640, 0xc188, 0xa67f, 0xc188, 0x21, 0 + .dw 0xa6c0, 0xc188, 0xa6ff, 0xc188, 0x21, 0 + .dw 0xa740, 0xc188, 0xa77f, 0xc188, 0x21, 0 + .dw 0xa7c0, 0xc188, 0xa7ff, 0xc188, 0x21, 0 + .dw 0xa840, 0xc188, 0xa87f, 0xc188, 0x21, 0 + .dw 0xa8c0, 0xc188, 0xa8ff, 0xc188, 0x21, 0 + .dw 0xa940, 0xc188, 0xa97f, 0xc188, 0x21, 0 + .dw 0xa9c0, 0xc188, 0xa9ff, 0xc188, 0x21, 0 + .dw 0xaa40, 0xc188, 0xaa7f, 0xc188, 0x21, 0 + .dw 0xaac0, 0xc188, 0xaaff, 0xc188, 0x21, 0 + .dw 0xab40, 0xc188, 0xab7f, 0xc188, 0x21, 0 + .dw 0xabc0, 0xc188, 0xabff, 0xc188, 0x21, 0 + .dw 0xac40, 0xc188, 0xac7f, 0xc188, 0x21, 0 + .dw 0xacc0, 0xc188, 0xacff, 0xc188, 0x21, 0 + .dw 0xad40, 0xc188, 0xad7f, 0xc188, 0x21, 0 + .dw 0xadc0, 0xc188, 0xadff, 0xc188, 0x21, 0 + .dw 0xae40, 0xc188, 0xae7f, 0xc188, 0x21, 0 + .dw 0xaec0, 0xc188, 0xaeff, 0xc188, 0x21, 0 + .dw 0xaf40, 0xc188, 0xaf7f, 0xc188, 0x21, 0 + .dw 0xafc0, 0xc188, 0xafff, 0xc188, 0x21, 0 + .dw 0xb040, 0xc188, 0xb07f, 0xc188, 0x21, 0 + .dw 0xb0c0, 0xc188, 0xb0ff, 0xc188, 0x21, 0 + .dw 0xb140, 0xc188, 0xb17f, 0xc188, 0x21, 0 + .dw 0xb1c0, 0xc188, 0xb1ff, 0xc188, 0x21, 0 + .dw 0xb240, 0xc188, 0xb27f, 0xc188, 0x21, 0 + .dw 0xb2c0, 0xc188, 0xb2ff, 0xc188, 0x21, 0 + .dw 0xb340, 0xc188, 0xb37f, 0xc188, 0x21, 0 + .dw 0xb3c0, 0xc188, 0xb3ff, 0xc188, 0x21, 0 + .dw 0xb440, 0xc188, 0xb47f, 0xc188, 0x21, 0 + .dw 0xb4c0, 0xc188, 0xb4ff, 0xc188, 0x21, 0 + .dw 0xb540, 0xc188, 0xb57f, 0xc188, 0x21, 0 + .dw 0xb5c0, 0xc188, 0xb5ff, 0xc188, 0x21, 0 + .dw 0xb640, 0xc188, 0xb67f, 0xc188, 0x21, 0 + .dw 0xb6c0, 0xc188, 0xb6ff, 0xc188, 0x21, 0 + .dw 0xb740, 0xc188, 0xb77f, 0xc188, 0x21, 0 + .dw 0xb7c0, 0xc188, 0xb7ff, 0xc188, 0x21, 0 + .dw 0xb840, 0xc188, 0xb87f, 0xc188, 0x21, 0 + .dw 0xb8c0, 0xc188, 0xb8ff, 0xc188, 0x21, 0 + .dw 0xb940, 0xc188, 0xb97f, 0xc188, 0x21, 0 + .dw 0xb9c0, 0xc188, 0xdfff, 0xc188, 0x21, 0 + .dw 0xe040, 0xc188, 0xe07f, 0xc188, 0x21, 0 + .dw 0xe0c0, 0xc188, 0xe0ff, 0xc188, 0x21, 0 + .dw 0xe140, 0xc188, 0xe17f, 0xc188, 0x21, 0 + .dw 0xe1c0, 0xc188, 0xe1ff, 0xc188, 0x21, 0 + .dw 0xe240, 0xc188, 0xe27f, 0xc188, 0x21, 0 + .dw 0xe2c0, 0xc188, 0xe2ff, 0xc188, 0x21, 0 + .dw 0xe340, 0xc188, 0xe37f, 0xc188, 0x21, 0 + .dw 0xe3c0, 0xc188, 0xe3ff, 0xc188, 0x21, 0 + .dw 0xe440, 0xc188, 0xe47f, 0xc188, 0x21, 0 + .dw 0xe4c0, 0xc188, 0xe4ff, 0xc188, 0x21, 0 + .dw 0xe540, 0xc188, 0xe57f, 0xc188, 0x21, 0 + .dw 0xe5c0, 0xc188, 0xe5ff, 0xc188, 0x21, 0 + .dw 0xe640, 0xc188, 0xe67f, 0xc188, 0x21, 0 + .dw 0xe6c0, 0xc188, 0xe6ff, 0xc188, 0x21, 0 + .dw 0xe740, 0xc188, 0xe77f, 0xc188, 0x21, 0 + .dw 0xe7c0, 0xc188, 0xe7ff, 0xc188, 0x21, 0 + .dw 0xe840, 0xc188, 0xe87f, 0xc188, 0x21, 0 + .dw 0xe8c0, 0xc188, 0xe8ff, 0xc188, 0x21, 0 + .dw 0xe940, 0xc188, 0xe97f, 0xc188, 0x21, 0 + .dw 0xe9c0, 0xc188, 0xe9ff, 0xc188, 0x21, 0 + .dw 0xea40, 0xc188, 0xea7f, 0xc188, 0x21, 0 + .dw 0xeac0, 0xc188, 0xeaff, 0xc188, 0x21, 0 + .dw 0xeb40, 0xc188, 0xeb7f, 0xc188, 0x21, 0 + .dw 0xebc0, 0xc188, 0xebff, 0xc188, 0x21, 0 + .dw 0xec40, 0xc188, 0xec7f, 0xc188, 0x21, 0 + .dw 0xecc0, 0xc188, 0xecff, 0xc188, 0x21, 0 + .dw 0xed40, 0xc188, 0xed7f, 0xc188, 0x21, 0 + .dw 0xedc0, 0xc188, 0xedff, 0xc188, 0x21, 0 + .dw 0xee40, 0xc188, 0xee7f, 0xc188, 0x21, 0 + .dw 0xeec0, 0xc188, 0xeeff, 0xc188, 0x21, 0 + .dw 0xef40, 0xc188, 0xef7f, 0xc188, 0x21, 0 + .dw 0xefc0, 0xc188, 0xefff, 0xc188, 0x21, 0 + .dw 0xf040, 0xc188, 0xf07f, 0xc188, 0x21, 0 + .dw 0xf0c0, 0xc188, 0xf0ff, 0xc188, 0x21, 0 + .dw 0xf140, 0xc188, 0xf17f, 0xc188, 0x21, 0 + .dw 0xf1c0, 0xc188, 0xf1ff, 0xc188, 0x21, 0 + .dw 0xf240, 0xc188, 0xf27f, 0xc188, 0x21, 0 + .dw 0xf2c0, 0xc188, 0xf2ff, 0xc188, 0x21, 0 + .dw 0xf340, 0xc188, 0xf37f, 0xc188, 0x21, 0 + .dw 0xf3c0, 0xc188, 0xf3ff, 0xc188, 0x21, 0 + .dw 0xf440, 0xc188, 0xf47f, 0xc188, 0x21, 0 + .dw 0xf4c0, 0xc188, 0xf4ff, 0xc188, 0x21, 0 + .dw 0xf540, 0xc188, 0xf57f, 0xc188, 0x21, 0 + .dw 0xf5c0, 0xc188, 0xf5ff, 0xc188, 0x21, 0 + .dw 0xf640, 0xc188, 0xf67f, 0xc188, 0x21, 0 + .dw 0xf6c0, 0xc188, 0xf6ff, 0xc188, 0x21, 0 + .dw 0xf740, 0xc188, 0xf77f, 0xc188, 0x21, 0 + .dw 0xf7c0, 0xc188, 0xf7ff, 0xc188, 0x21, 0 + .dw 0xf840, 0xc188, 0xf87f, 0xc188, 0x21, 0 + .dw 0xf8c0, 0xc188, 0xf8ff, 0xc188, 0x21, 0 + .dw 0xf940, 0xc188, 0xf97f, 0xc188, 0x21, 0 + .dw 0xf9c0, 0xc188, 0x1fff, 0xc189, 0x21, 0 + .dw 0x2040, 0xc189, 0x207f, 0xc189, 0x21, 0 + .dw 0x20c0, 0xc189, 0x20ff, 0xc189, 0x21, 0 + .dw 0x2140, 0xc189, 0x217f, 0xc189, 0x21, 0 + .dw 0x21c0, 0xc189, 0x21ff, 0xc189, 0x21, 0 + .dw 0x2240, 0xc189, 0x227f, 0xc189, 0x21, 0 + .dw 0x22c0, 0xc189, 0x22ff, 0xc189, 0x21, 0 + .dw 0x2340, 0xc189, 0x237f, 0xc189, 0x21, 0 + .dw 0x23c0, 0xc189, 0x23ff, 0xc189, 0x21, 0 + .dw 0x2440, 0xc189, 0x247f, 0xc189, 0x21, 0 + .dw 0x24c0, 0xc189, 0x24ff, 0xc189, 0x21, 0 + .dw 0x2540, 0xc189, 0x257f, 0xc189, 0x21, 0 + .dw 0x25c0, 0xc189, 0x25ff, 0xc189, 0x21, 0 + .dw 0x2640, 0xc189, 0x267f, 0xc189, 0x21, 0 + .dw 0x26c0, 0xc189, 0x26ff, 0xc189, 0x21, 0 + .dw 0x2740, 0xc189, 0x277f, 0xc189, 0x21, 0 + .dw 0x27c0, 0xc189, 0x27ff, 0xc189, 0x21, 0 + .dw 0x2840, 0xc189, 0x287f, 0xc189, 0x21, 0 + .dw 0x28c0, 0xc189, 0x28ff, 0xc189, 0x21, 0 + .dw 0x2940, 0xc189, 0x297f, 0xc189, 0x21, 0 + .dw 0x29c0, 0xc189, 0x29ff, 0xc189, 0x21, 0 + .dw 0x2a40, 0xc189, 0x2a7f, 0xc189, 0x21, 0 + .dw 0x2ac0, 0xc189, 0x2aff, 0xc189, 0x21, 0 + .dw 0x2b40, 0xc189, 0x2b7f, 0xc189, 0x21, 0 + .dw 0x2bc0, 0xc189, 0x2bff, 0xc189, 0x21, 0 + .dw 0x2c40, 0xc189, 0x2c7f, 0xc189, 0x21, 0 + .dw 0x2cc0, 0xc189, 0x2cff, 0xc189, 0x21, 0 + .dw 0x2d40, 0xc189, 0x2d7f, 0xc189, 0x21, 0 + .dw 0x2dc0, 0xc189, 0x2dff, 0xc189, 0x21, 0 + .dw 0x2e40, 0xc189, 0x2e7f, 0xc189, 0x21, 0 + .dw 0x2ec0, 0xc189, 0x2eff, 0xc189, 0x21, 0 + .dw 0x2f40, 0xc189, 0x2f7f, 0xc189, 0x21, 0 + .dw 0x2fc0, 0xc189, 0x2fff, 0xc189, 0x21, 0 + .dw 0x3040, 0xc189, 0x307f, 0xc189, 0x21, 0 + .dw 0x30c0, 0xc189, 0x30ff, 0xc189, 0x21, 0 + .dw 0x3140, 0xc189, 0x317f, 0xc189, 0x21, 0 + .dw 0x31c0, 0xc189, 0x31ff, 0xc189, 0x21, 0 + .dw 0x3240, 0xc189, 0x327f, 0xc189, 0x21, 0 + .dw 0x32c0, 0xc189, 0x32ff, 0xc189, 0x21, 0 + .dw 0x3340, 0xc189, 0x337f, 0xc189, 0x21, 0 + .dw 0x33c0, 0xc189, 0x33ff, 0xc189, 0x21, 0 + .dw 0x3440, 0xc189, 0x347f, 0xc189, 0x21, 0 + .dw 0x34c0, 0xc189, 0x34ff, 0xc189, 0x21, 0 + .dw 0x3540, 0xc189, 0x357f, 0xc189, 0x21, 0 + .dw 0x35c0, 0xc189, 0x35ff, 0xc189, 0x21, 0 + .dw 0x3640, 0xc189, 0x367f, 0xc189, 0x21, 0 + .dw 0x36c0, 0xc189, 0x36ff, 0xc189, 0x21, 0 + .dw 0x3740, 0xc189, 0x377f, 0xc189, 0x21, 0 + .dw 0x37c0, 0xc189, 0x37ff, 0xc189, 0x21, 0 + .dw 0x3840, 0xc189, 0x387f, 0xc189, 0x21, 0 + .dw 0x38c0, 0xc189, 0x38ff, 0xc189, 0x21, 0 + .dw 0x3940, 0xc189, 0x397f, 0xc189, 0x21, 0 + .dw 0x39c0, 0xc189, 0x5fff, 0xc189, 0x21, 0 + .dw 0x6040, 0xc189, 0x607f, 0xc189, 0x21, 0 + .dw 0x60c0, 0xc189, 0x60ff, 0xc189, 0x21, 0 + .dw 0x6140, 0xc189, 0x617f, 0xc189, 0x21, 0 + .dw 0x61c0, 0xc189, 0x61ff, 0xc189, 0x21, 0 + .dw 0x6240, 0xc189, 0x627f, 0xc189, 0x21, 0 + .dw 0x62c0, 0xc189, 0x62ff, 0xc189, 0x21, 0 + .dw 0x6340, 0xc189, 0x637f, 0xc189, 0x21, 0 + .dw 0x63c0, 0xc189, 0x63ff, 0xc189, 0x21, 0 + .dw 0x6440, 0xc189, 0x647f, 0xc189, 0x21, 0 + .dw 0x64c0, 0xc189, 0x64ff, 0xc189, 0x21, 0 + .dw 0x6540, 0xc189, 0x657f, 0xc189, 0x21, 0 + .dw 0x65c0, 0xc189, 0x65ff, 0xc189, 0x21, 0 + .dw 0x6640, 0xc189, 0x667f, 0xc189, 0x21, 0 + .dw 0x66c0, 0xc189, 0x66ff, 0xc189, 0x21, 0 + .dw 0x6740, 0xc189, 0x677f, 0xc189, 0x21, 0 + .dw 0x67c0, 0xc189, 0x67ff, 0xc189, 0x21, 0 + .dw 0x6840, 0xc189, 0x687f, 0xc189, 0x21, 0 + .dw 0x68c0, 0xc189, 0x68ff, 0xc189, 0x21, 0 + .dw 0x6940, 0xc189, 0x697f, 0xc189, 0x21, 0 + .dw 0x69c0, 0xc189, 0x69ff, 0xc189, 0x21, 0 + .dw 0x6a40, 0xc189, 0x6a7f, 0xc189, 0x21, 0 + .dw 0x6ac0, 0xc189, 0x6aff, 0xc189, 0x21, 0 + .dw 0x6b40, 0xc189, 0x6b7f, 0xc189, 0x21, 0 + .dw 0x6bc0, 0xc189, 0x6bff, 0xc189, 0x21, 0 + .dw 0x6c40, 0xc189, 0x6c7f, 0xc189, 0x21, 0 + .dw 0x6cc0, 0xc189, 0x6cff, 0xc189, 0x21, 0 + .dw 0x6d40, 0xc189, 0x6d7f, 0xc189, 0x21, 0 + .dw 0x6dc0, 0xc189, 0x6dff, 0xc189, 0x21, 0 + .dw 0x6e40, 0xc189, 0x6e7f, 0xc189, 0x21, 0 + .dw 0x6ec0, 0xc189, 0x6eff, 0xc189, 0x21, 0 + .dw 0x6f40, 0xc189, 0x6f7f, 0xc189, 0x21, 0 + .dw 0x6fc0, 0xc189, 0x6fff, 0xc189, 0x21, 0 + .dw 0x7040, 0xc189, 0x707f, 0xc189, 0x21, 0 + .dw 0x70c0, 0xc189, 0x70ff, 0xc189, 0x21, 0 + .dw 0x7140, 0xc189, 0x717f, 0xc189, 0x21, 0 + .dw 0x71c0, 0xc189, 0x71ff, 0xc189, 0x21, 0 + .dw 0x7240, 0xc189, 0x727f, 0xc189, 0x21, 0 + .dw 0x72c0, 0xc189, 0x72ff, 0xc189, 0x21, 0 + .dw 0x7340, 0xc189, 0x737f, 0xc189, 0x21, 0 + .dw 0x73c0, 0xc189, 0x73ff, 0xc189, 0x21, 0 + .dw 0x7440, 0xc189, 0x747f, 0xc189, 0x21, 0 + .dw 0x74c0, 0xc189, 0x74ff, 0xc189, 0x21, 0 + .dw 0x7540, 0xc189, 0x757f, 0xc189, 0x21, 0 + .dw 0x75c0, 0xc189, 0x75ff, 0xc189, 0x21, 0 + .dw 0x7640, 0xc189, 0x767f, 0xc189, 0x21, 0 + .dw 0x76c0, 0xc189, 0x76ff, 0xc189, 0x21, 0 + .dw 0x7740, 0xc189, 0x777f, 0xc189, 0x21, 0 + .dw 0x77c0, 0xc189, 0x77ff, 0xc189, 0x21, 0 + .dw 0x7840, 0xc189, 0x787f, 0xc189, 0x21, 0 + .dw 0x78c0, 0xc189, 0x78ff, 0xc189, 0x21, 0 + .dw 0x7940, 0xc189, 0x797f, 0xc189, 0x21, 0 + .dw 0x79c0, 0xc189, 0x9fff, 0xc189, 0x21, 0 + .dw 0xa040, 0xc189, 0xa07f, 0xc189, 0x21, 0 + .dw 0xa0c0, 0xc189, 0xa0ff, 0xc189, 0x21, 0 + .dw 0xa140, 0xc189, 0xa17f, 0xc189, 0x21, 0 + .dw 0xa1c0, 0xc189, 0xa1ff, 0xc189, 0x21, 0 + .dw 0xa240, 0xc189, 0xa27f, 0xc189, 0x21, 0 + .dw 0xa2c0, 0xc189, 0xa2ff, 0xc189, 0x21, 0 + .dw 0xa340, 0xc189, 0xa37f, 0xc189, 0x21, 0 + .dw 0xa3c0, 0xc189, 0xa3ff, 0xc189, 0x21, 0 + .dw 0xa440, 0xc189, 0xa47f, 0xc189, 0x21, 0 + .dw 0xa4c0, 0xc189, 0xa4ff, 0xc189, 0x21, 0 + .dw 0xa540, 0xc189, 0xa57f, 0xc189, 0x21, 0 + .dw 0xa5c0, 0xc189, 0xa5ff, 0xc189, 0x21, 0 + .dw 0xa640, 0xc189, 0xa67f, 0xc189, 0x21, 0 + .dw 0xa6c0, 0xc189, 0xa6ff, 0xc189, 0x21, 0 + .dw 0xa740, 0xc189, 0xa77f, 0xc189, 0x21, 0 + .dw 0xa7c0, 0xc189, 0xa7ff, 0xc189, 0x21, 0 + .dw 0xa840, 0xc189, 0xa87f, 0xc189, 0x21, 0 + .dw 0xa8c0, 0xc189, 0xa8ff, 0xc189, 0x21, 0 + .dw 0xa940, 0xc189, 0xa97f, 0xc189, 0x21, 0 + .dw 0xa9c0, 0xc189, 0xa9ff, 0xc189, 0x21, 0 + .dw 0xaa40, 0xc189, 0xaa7f, 0xc189, 0x21, 0 + .dw 0xaac0, 0xc189, 0xaaff, 0xc189, 0x21, 0 + .dw 0xab40, 0xc189, 0xab7f, 0xc189, 0x21, 0 + .dw 0xabc0, 0xc189, 0xabff, 0xc189, 0x21, 0 + .dw 0xac40, 0xc189, 0xac7f, 0xc189, 0x21, 0 + .dw 0xacc0, 0xc189, 0xacff, 0xc189, 0x21, 0 + .dw 0xad40, 0xc189, 0xad7f, 0xc189, 0x21, 0 + .dw 0xadc0, 0xc189, 0xadff, 0xc189, 0x21, 0 + .dw 0xae40, 0xc189, 0xae7f, 0xc189, 0x21, 0 + .dw 0xaec0, 0xc189, 0xaeff, 0xc189, 0x21, 0 + .dw 0xaf40, 0xc189, 0xaf7f, 0xc189, 0x21, 0 + .dw 0xafc0, 0xc189, 0xafff, 0xc189, 0x21, 0 + .dw 0xb040, 0xc189, 0xb07f, 0xc189, 0x21, 0 + .dw 0xb0c0, 0xc189, 0xb0ff, 0xc189, 0x21, 0 + .dw 0xb140, 0xc189, 0xb17f, 0xc189, 0x21, 0 + .dw 0xb1c0, 0xc189, 0xb1ff, 0xc189, 0x21, 0 + .dw 0xb240, 0xc189, 0xb27f, 0xc189, 0x21, 0 + .dw 0xb2c0, 0xc189, 0xb2ff, 0xc189, 0x21, 0 + .dw 0xb340, 0xc189, 0xb37f, 0xc189, 0x21, 0 + .dw 0xb3c0, 0xc189, 0xb3ff, 0xc189, 0x21, 0 + .dw 0xb440, 0xc189, 0xb47f, 0xc189, 0x21, 0 + .dw 0xb4c0, 0xc189, 0xb4ff, 0xc189, 0x21, 0 + .dw 0xb540, 0xc189, 0xb57f, 0xc189, 0x21, 0 + .dw 0xb5c0, 0xc189, 0xb5ff, 0xc189, 0x21, 0 + .dw 0xb640, 0xc189, 0xb67f, 0xc189, 0x21, 0 + .dw 0xb6c0, 0xc189, 0xb6ff, 0xc189, 0x21, 0 + .dw 0xb740, 0xc189, 0xb77f, 0xc189, 0x21, 0 + .dw 0xb7c0, 0xc189, 0xb7ff, 0xc189, 0x21, 0 + .dw 0xb840, 0xc189, 0xb87f, 0xc189, 0x21, 0 + .dw 0xb8c0, 0xc189, 0xb8ff, 0xc189, 0x21, 0 + .dw 0xb940, 0xc189, 0xb97f, 0xc189, 0x21, 0 + .dw 0xb9c0, 0xc189, 0xdfff, 0xc189, 0x21, 0 + .dw 0xe040, 0xc189, 0xe07f, 0xc189, 0x21, 0 + .dw 0xe0c0, 0xc189, 0xe0ff, 0xc189, 0x21, 0 + .dw 0xe140, 0xc189, 0xe17f, 0xc189, 0x21, 0 + .dw 0xe1c0, 0xc189, 0xe1ff, 0xc189, 0x21, 0 + .dw 0xe240, 0xc189, 0xe27f, 0xc189, 0x21, 0 + .dw 0xe2c0, 0xc189, 0xe2ff, 0xc189, 0x21, 0 + .dw 0xe340, 0xc189, 0xe37f, 0xc189, 0x21, 0 + .dw 0xe3c0, 0xc189, 0xe3ff, 0xc189, 0x21, 0 + .dw 0xe440, 0xc189, 0xe47f, 0xc189, 0x21, 0 + .dw 0xe4c0, 0xc189, 0xe4ff, 0xc189, 0x21, 0 + .dw 0xe540, 0xc189, 0xe57f, 0xc189, 0x21, 0 + .dw 0xe5c0, 0xc189, 0xe5ff, 0xc189, 0x21, 0 + .dw 0xe640, 0xc189, 0xe67f, 0xc189, 0x21, 0 + .dw 0xe6c0, 0xc189, 0xe6ff, 0xc189, 0x21, 0 + .dw 0xe740, 0xc189, 0xe77f, 0xc189, 0x21, 0 + .dw 0xe7c0, 0xc189, 0xe7ff, 0xc189, 0x21, 0 + .dw 0xe840, 0xc189, 0xe87f, 0xc189, 0x21, 0 + .dw 0xe8c0, 0xc189, 0xe8ff, 0xc189, 0x21, 0 + .dw 0xe940, 0xc189, 0xe97f, 0xc189, 0x21, 0 + .dw 0xe9c0, 0xc189, 0xe9ff, 0xc189, 0x21, 0 + .dw 0xea40, 0xc189, 0xea7f, 0xc189, 0x21, 0 + .dw 0xeac0, 0xc189, 0xeaff, 0xc189, 0x21, 0 + .dw 0xeb40, 0xc189, 0xeb7f, 0xc189, 0x21, 0 + .dw 0xebc0, 0xc189, 0xebff, 0xc189, 0x21, 0 + .dw 0xec40, 0xc189, 0xec7f, 0xc189, 0x21, 0 + .dw 0xecc0, 0xc189, 0xecff, 0xc189, 0x21, 0 + .dw 0xed40, 0xc189, 0xed7f, 0xc189, 0x21, 0 + .dw 0xedc0, 0xc189, 0xedff, 0xc189, 0x21, 0 + .dw 0xee40, 0xc189, 0xee7f, 0xc189, 0x21, 0 + .dw 0xeec0, 0xc189, 0xeeff, 0xc189, 0x21, 0 + .dw 0xef40, 0xc189, 0xef7f, 0xc189, 0x21, 0 + .dw 0xefc0, 0xc189, 0xefff, 0xc189, 0x21, 0 + .dw 0xf040, 0xc189, 0xf07f, 0xc189, 0x21, 0 + .dw 0xf0c0, 0xc189, 0xf0ff, 0xc189, 0x21, 0 + .dw 0xf140, 0xc189, 0xf17f, 0xc189, 0x21, 0 + .dw 0xf1c0, 0xc189, 0xf1ff, 0xc189, 0x21, 0 + .dw 0xf240, 0xc189, 0xf27f, 0xc189, 0x21, 0 + .dw 0xf2c0, 0xc189, 0xf2ff, 0xc189, 0x21, 0 + .dw 0xf340, 0xc189, 0xf37f, 0xc189, 0x21, 0 + .dw 0xf3c0, 0xc189, 0xf3ff, 0xc189, 0x21, 0 + .dw 0xf440, 0xc189, 0xf47f, 0xc189, 0x21, 0 + .dw 0xf4c0, 0xc189, 0xf4ff, 0xc189, 0x21, 0 + .dw 0xf540, 0xc189, 0xf57f, 0xc189, 0x21, 0 + .dw 0xf5c0, 0xc189, 0xf5ff, 0xc189, 0x21, 0 + .dw 0xf640, 0xc189, 0xf67f, 0xc189, 0x21, 0 + .dw 0xf6c0, 0xc189, 0xf6ff, 0xc189, 0x21, 0 + .dw 0xf740, 0xc189, 0xf77f, 0xc189, 0x21, 0 + .dw 0xf7c0, 0xc189, 0xf7ff, 0xc189, 0x21, 0 + .dw 0xf840, 0xc189, 0xf87f, 0xc189, 0x21, 0 + .dw 0xf8c0, 0xc189, 0xf8ff, 0xc189, 0x21, 0 + .dw 0xf940, 0xc189, 0xf97f, 0xc189, 0x21, 0 + .dw 0xf9c0, 0xc189, 0x1fff, 0xc18a, 0x21, 0 + .dw 0x2040, 0xc18a, 0x207f, 0xc18a, 0x21, 0 + .dw 0x20c0, 0xc18a, 0x20ff, 0xc18a, 0x21, 0 + .dw 0x2140, 0xc18a, 0x217f, 0xc18a, 0x21, 0 + .dw 0x21c0, 0xc18a, 0x21ff, 0xc18a, 0x21, 0 + .dw 0x2240, 0xc18a, 0x227f, 0xc18a, 0x21, 0 + .dw 0x22c0, 0xc18a, 0x22ff, 0xc18a, 0x21, 0 + .dw 0x2340, 0xc18a, 0x237f, 0xc18a, 0x21, 0 + .dw 0x23c0, 0xc18a, 0x23ff, 0xc18a, 0x21, 0 + .dw 0x2440, 0xc18a, 0x247f, 0xc18a, 0x21, 0 + .dw 0x24c0, 0xc18a, 0x24ff, 0xc18a, 0x21, 0 + .dw 0x2540, 0xc18a, 0x257f, 0xc18a, 0x21, 0 + .dw 0x25c0, 0xc18a, 0x25ff, 0xc18a, 0x21, 0 + .dw 0x2640, 0xc18a, 0x267f, 0xc18a, 0x21, 0 + .dw 0x26c0, 0xc18a, 0x26ff, 0xc18a, 0x21, 0 + .dw 0x2740, 0xc18a, 0x277f, 0xc18a, 0x21, 0 + .dw 0x27c0, 0xc18a, 0x27ff, 0xc18a, 0x21, 0 + .dw 0x2840, 0xc18a, 0x287f, 0xc18a, 0x21, 0 + .dw 0x28c0, 0xc18a, 0x28ff, 0xc18a, 0x21, 0 + .dw 0x2940, 0xc18a, 0x297f, 0xc18a, 0x21, 0 + .dw 0x29c0, 0xc18a, 0x29ff, 0xc18a, 0x21, 0 + .dw 0x2a40, 0xc18a, 0x2a7f, 0xc18a, 0x21, 0 + .dw 0x2ac0, 0xc18a, 0x2aff, 0xc18a, 0x21, 0 + .dw 0x2b40, 0xc18a, 0x2b7f, 0xc18a, 0x21, 0 + .dw 0x2bc0, 0xc18a, 0x2bff, 0xc18a, 0x21, 0 + .dw 0x2c40, 0xc18a, 0x2c7f, 0xc18a, 0x21, 0 + .dw 0x2cc0, 0xc18a, 0x2cff, 0xc18a, 0x21, 0 + .dw 0x2d40, 0xc18a, 0x2d7f, 0xc18a, 0x21, 0 + .dw 0x2dc0, 0xc18a, 0x2dff, 0xc18a, 0x21, 0 + .dw 0x2e40, 0xc18a, 0x2e7f, 0xc18a, 0x21, 0 + .dw 0x2ec0, 0xc18a, 0x2eff, 0xc18a, 0x21, 0 + .dw 0x2f40, 0xc18a, 0x2f7f, 0xc18a, 0x21, 0 + .dw 0x2fc0, 0xc18a, 0x2fff, 0xc18a, 0x21, 0 + .dw 0x3040, 0xc18a, 0x307f, 0xc18a, 0x21, 0 + .dw 0x30c0, 0xc18a, 0x30ff, 0xc18a, 0x21, 0 + .dw 0x3140, 0xc18a, 0x317f, 0xc18a, 0x21, 0 + .dw 0x31c0, 0xc18a, 0x31ff, 0xc18a, 0x21, 0 + .dw 0x3240, 0xc18a, 0x327f, 0xc18a, 0x21, 0 + .dw 0x32c0, 0xc18a, 0x32ff, 0xc18a, 0x21, 0 + .dw 0x3340, 0xc18a, 0x337f, 0xc18a, 0x21, 0 + .dw 0x33c0, 0xc18a, 0x33ff, 0xc18a, 0x21, 0 + .dw 0x3440, 0xc18a, 0x347f, 0xc18a, 0x21, 0 + .dw 0x34c0, 0xc18a, 0x34ff, 0xc18a, 0x21, 0 + .dw 0x3540, 0xc18a, 0x357f, 0xc18a, 0x21, 0 + .dw 0x35c0, 0xc18a, 0x35ff, 0xc18a, 0x21, 0 + .dw 0x3640, 0xc18a, 0x367f, 0xc18a, 0x21, 0 + .dw 0x36c0, 0xc18a, 0x36ff, 0xc18a, 0x21, 0 + .dw 0x3740, 0xc18a, 0x377f, 0xc18a, 0x21, 0 + .dw 0x37c0, 0xc18a, 0x37ff, 0xc18a, 0x21, 0 + .dw 0x3840, 0xc18a, 0x387f, 0xc18a, 0x21, 0 + .dw 0x38c0, 0xc18a, 0x38ff, 0xc18a, 0x21, 0 + .dw 0x3940, 0xc18a, 0x397f, 0xc18a, 0x21, 0 + .dw 0x39c0, 0xc18a, 0x5fff, 0xc18a, 0x21, 0 + .dw 0x6040, 0xc18a, 0x607f, 0xc18a, 0x21, 0 + .dw 0x60c0, 0xc18a, 0x60ff, 0xc18a, 0x21, 0 + .dw 0x6140, 0xc18a, 0x617f, 0xc18a, 0x21, 0 + .dw 0x61c0, 0xc18a, 0x61ff, 0xc18a, 0x21, 0 + .dw 0x6240, 0xc18a, 0x627f, 0xc18a, 0x21, 0 + .dw 0x62c0, 0xc18a, 0x62ff, 0xc18a, 0x21, 0 + .dw 0x6340, 0xc18a, 0x637f, 0xc18a, 0x21, 0 + .dw 0x63c0, 0xc18a, 0x63ff, 0xc18a, 0x21, 0 + .dw 0x6440, 0xc18a, 0x647f, 0xc18a, 0x21, 0 + .dw 0x64c0, 0xc18a, 0x64ff, 0xc18a, 0x21, 0 + .dw 0x6540, 0xc18a, 0x657f, 0xc18a, 0x21, 0 + .dw 0x65c0, 0xc18a, 0x65ff, 0xc18a, 0x21, 0 + .dw 0x6640, 0xc18a, 0x667f, 0xc18a, 0x21, 0 + .dw 0x66c0, 0xc18a, 0x66ff, 0xc18a, 0x21, 0 + .dw 0x6740, 0xc18a, 0x677f, 0xc18a, 0x21, 0 + .dw 0x67c0, 0xc18a, 0x67ff, 0xc18a, 0x21, 0 + .dw 0x6840, 0xc18a, 0x687f, 0xc18a, 0x21, 0 + .dw 0x68c0, 0xc18a, 0x68ff, 0xc18a, 0x21, 0 + .dw 0x6940, 0xc18a, 0x697f, 0xc18a, 0x21, 0 + .dw 0x69c0, 0xc18a, 0x69ff, 0xc18a, 0x21, 0 + .dw 0x6a40, 0xc18a, 0x6a7f, 0xc18a, 0x21, 0 + .dw 0x6ac0, 0xc18a, 0x6aff, 0xc18a, 0x21, 0 + .dw 0x6b40, 0xc18a, 0x6b7f, 0xc18a, 0x21, 0 + .dw 0x6bc0, 0xc18a, 0x6bff, 0xc18a, 0x21, 0 + .dw 0x6c40, 0xc18a, 0x6c7f, 0xc18a, 0x21, 0 + .dw 0x6cc0, 0xc18a, 0x6cff, 0xc18a, 0x21, 0 + .dw 0x6d40, 0xc18a, 0x6d7f, 0xc18a, 0x21, 0 + .dw 0x6dc0, 0xc18a, 0x6dff, 0xc18a, 0x21, 0 + .dw 0x6e40, 0xc18a, 0x6e7f, 0xc18a, 0x21, 0 + .dw 0x6ec0, 0xc18a, 0x6eff, 0xc18a, 0x21, 0 + .dw 0x6f40, 0xc18a, 0x6f7f, 0xc18a, 0x21, 0 + .dw 0x6fc0, 0xc18a, 0x6fff, 0xc18a, 0x21, 0 + .dw 0x7040, 0xc18a, 0x707f, 0xc18a, 0x21, 0 + .dw 0x70c0, 0xc18a, 0x70ff, 0xc18a, 0x21, 0 + .dw 0x7140, 0xc18a, 0x717f, 0xc18a, 0x21, 0 + .dw 0x71c0, 0xc18a, 0x71ff, 0xc18a, 0x21, 0 + .dw 0x7240, 0xc18a, 0x727f, 0xc18a, 0x21, 0 + .dw 0x72c0, 0xc18a, 0x72ff, 0xc18a, 0x21, 0 + .dw 0x7340, 0xc18a, 0x737f, 0xc18a, 0x21, 0 + .dw 0x73c0, 0xc18a, 0x73ff, 0xc18a, 0x21, 0 + .dw 0x7440, 0xc18a, 0x747f, 0xc18a, 0x21, 0 + .dw 0x74c0, 0xc18a, 0x74ff, 0xc18a, 0x21, 0 + .dw 0x7540, 0xc18a, 0x757f, 0xc18a, 0x21, 0 + .dw 0x75c0, 0xc18a, 0x75ff, 0xc18a, 0x21, 0 + .dw 0x7640, 0xc18a, 0x767f, 0xc18a, 0x21, 0 + .dw 0x76c0, 0xc18a, 0x76ff, 0xc18a, 0x21, 0 + .dw 0x7740, 0xc18a, 0x777f, 0xc18a, 0x21, 0 + .dw 0x77c0, 0xc18a, 0x77ff, 0xc18a, 0x21, 0 + .dw 0x7840, 0xc18a, 0x787f, 0xc18a, 0x21, 0 + .dw 0x78c0, 0xc18a, 0x78ff, 0xc18a, 0x21, 0 + .dw 0x7940, 0xc18a, 0x797f, 0xc18a, 0x21, 0 + .dw 0x79c0, 0xc18a, 0x9fff, 0xc18a, 0x21, 0 + .dw 0xa040, 0xc18a, 0xa07f, 0xc18a, 0x21, 0 + .dw 0xa0c0, 0xc18a, 0xa0ff, 0xc18a, 0x21, 0 + .dw 0xa140, 0xc18a, 0xa17f, 0xc18a, 0x21, 0 + .dw 0xa1c0, 0xc18a, 0xa1ff, 0xc18a, 0x21, 0 + .dw 0xa240, 0xc18a, 0xa27f, 0xc18a, 0x21, 0 + .dw 0xa2c0, 0xc18a, 0xa2ff, 0xc18a, 0x21, 0 + .dw 0xa340, 0xc18a, 0xa37f, 0xc18a, 0x21, 0 + .dw 0xa3c0, 0xc18a, 0xa3ff, 0xc18a, 0x21, 0 + .dw 0xa440, 0xc18a, 0xa47f, 0xc18a, 0x21, 0 + .dw 0xa4c0, 0xc18a, 0xa4ff, 0xc18a, 0x21, 0 + .dw 0xa540, 0xc18a, 0xa57f, 0xc18a, 0x21, 0 + .dw 0xa5c0, 0xc18a, 0xa5ff, 0xc18a, 0x21, 0 + .dw 0xa640, 0xc18a, 0xa67f, 0xc18a, 0x21, 0 + .dw 0xa6c0, 0xc18a, 0xa6ff, 0xc18a, 0x21, 0 + .dw 0xa740, 0xc18a, 0xa77f, 0xc18a, 0x21, 0 + .dw 0xa7c0, 0xc18a, 0xa7ff, 0xc18a, 0x21, 0 + .dw 0xa840, 0xc18a, 0xa87f, 0xc18a, 0x21, 0 + .dw 0xa8c0, 0xc18a, 0xa8ff, 0xc18a, 0x21, 0 + .dw 0xa940, 0xc18a, 0xa97f, 0xc18a, 0x21, 0 + .dw 0xa9c0, 0xc18a, 0xa9ff, 0xc18a, 0x21, 0 + .dw 0xaa40, 0xc18a, 0xaa7f, 0xc18a, 0x21, 0 + .dw 0xaac0, 0xc18a, 0xaaff, 0xc18a, 0x21, 0 + .dw 0xab40, 0xc18a, 0xab7f, 0xc18a, 0x21, 0 + .dw 0xabc0, 0xc18a, 0xabff, 0xc18a, 0x21, 0 + .dw 0xac40, 0xc18a, 0xac7f, 0xc18a, 0x21, 0 + .dw 0xacc0, 0xc18a, 0xacff, 0xc18a, 0x21, 0 + .dw 0xad40, 0xc18a, 0xad7f, 0xc18a, 0x21, 0 + .dw 0xadc0, 0xc18a, 0xadff, 0xc18a, 0x21, 0 + .dw 0xae40, 0xc18a, 0xae7f, 0xc18a, 0x21, 0 + .dw 0xaec0, 0xc18a, 0xaeff, 0xc18a, 0x21, 0 + .dw 0xaf40, 0xc18a, 0xaf7f, 0xc18a, 0x21, 0 + .dw 0xafc0, 0xc18a, 0xafff, 0xc18a, 0x21, 0 + .dw 0xb040, 0xc18a, 0xb07f, 0xc18a, 0x21, 0 + .dw 0xb0c0, 0xc18a, 0xb0ff, 0xc18a, 0x21, 0 + .dw 0xb140, 0xc18a, 0xb17f, 0xc18a, 0x21, 0 + .dw 0xb1c0, 0xc18a, 0xb1ff, 0xc18a, 0x21, 0 + .dw 0xb240, 0xc18a, 0xb27f, 0xc18a, 0x21, 0 + .dw 0xb2c0, 0xc18a, 0xb2ff, 0xc18a, 0x21, 0 + .dw 0xb340, 0xc18a, 0xb37f, 0xc18a, 0x21, 0 + .dw 0xb3c0, 0xc18a, 0xb3ff, 0xc18a, 0x21, 0 + .dw 0xb440, 0xc18a, 0xb47f, 0xc18a, 0x21, 0 + .dw 0xb4c0, 0xc18a, 0xb4ff, 0xc18a, 0x21, 0 + .dw 0xb540, 0xc18a, 0xb57f, 0xc18a, 0x21, 0 + .dw 0xb5c0, 0xc18a, 0xb5ff, 0xc18a, 0x21, 0 + .dw 0xb640, 0xc18a, 0xb67f, 0xc18a, 0x21, 0 + .dw 0xb6c0, 0xc18a, 0xb6ff, 0xc18a, 0x21, 0 + .dw 0xb740, 0xc18a, 0xb77f, 0xc18a, 0x21, 0 + .dw 0xb7c0, 0xc18a, 0xb7ff, 0xc18a, 0x21, 0 + .dw 0xb840, 0xc18a, 0xb87f, 0xc18a, 0x21, 0 + .dw 0xb8c0, 0xc18a, 0xb8ff, 0xc18a, 0x21, 0 + .dw 0xb940, 0xc18a, 0xb97f, 0xc18a, 0x21, 0 + .dw 0xb9c0, 0xc18a, 0xdfff, 0xc18a, 0x21, 0 + .dw 0xe040, 0xc18a, 0xe07f, 0xc18a, 0x21, 0 + .dw 0xe0c0, 0xc18a, 0xe0ff, 0xc18a, 0x21, 0 + .dw 0xe140, 0xc18a, 0xe17f, 0xc18a, 0x21, 0 + .dw 0xe1c0, 0xc18a, 0xe1ff, 0xc18a, 0x21, 0 + .dw 0xe240, 0xc18a, 0xe27f, 0xc18a, 0x21, 0 + .dw 0xe2c0, 0xc18a, 0xe2ff, 0xc18a, 0x21, 0 + .dw 0xe340, 0xc18a, 0xe37f, 0xc18a, 0x21, 0 + .dw 0xe3c0, 0xc18a, 0xe3ff, 0xc18a, 0x21, 0 + .dw 0xe440, 0xc18a, 0xe47f, 0xc18a, 0x21, 0 + .dw 0xe4c0, 0xc18a, 0xe4ff, 0xc18a, 0x21, 0 + .dw 0xe540, 0xc18a, 0xe57f, 0xc18a, 0x21, 0 + .dw 0xe5c0, 0xc18a, 0xe5ff, 0xc18a, 0x21, 0 + .dw 0xe640, 0xc18a, 0xe67f, 0xc18a, 0x21, 0 + .dw 0xe6c0, 0xc18a, 0xe6ff, 0xc18a, 0x21, 0 + .dw 0xe740, 0xc18a, 0xe77f, 0xc18a, 0x21, 0 + .dw 0xe7c0, 0xc18a, 0xe7ff, 0xc18a, 0x21, 0 + .dw 0xe840, 0xc18a, 0xe87f, 0xc18a, 0x21, 0 + .dw 0xe8c0, 0xc18a, 0xe8ff, 0xc18a, 0x21, 0 + .dw 0xe940, 0xc18a, 0xe97f, 0xc18a, 0x21, 0 + .dw 0xe9c0, 0xc18a, 0xe9ff, 0xc18a, 0x21, 0 + .dw 0xea40, 0xc18a, 0xea7f, 0xc18a, 0x21, 0 + .dw 0xeac0, 0xc18a, 0xeaff, 0xc18a, 0x21, 0 + .dw 0xeb40, 0xc18a, 0xeb7f, 0xc18a, 0x21, 0 + .dw 0xebc0, 0xc18a, 0xebff, 0xc18a, 0x21, 0 + .dw 0xec40, 0xc18a, 0xec7f, 0xc18a, 0x21, 0 + .dw 0xecc0, 0xc18a, 0xecff, 0xc18a, 0x21, 0 + .dw 0xed40, 0xc18a, 0xed7f, 0xc18a, 0x21, 0 + .dw 0xedc0, 0xc18a, 0xedff, 0xc18a, 0x21, 0 + .dw 0xee40, 0xc18a, 0xee7f, 0xc18a, 0x21, 0 + .dw 0xeec0, 0xc18a, 0xeeff, 0xc18a, 0x21, 0 + .dw 0xef40, 0xc18a, 0xef7f, 0xc18a, 0x21, 0 + .dw 0xefc0, 0xc18a, 0xefff, 0xc18a, 0x21, 0 + .dw 0xf040, 0xc18a, 0xf07f, 0xc18a, 0x21, 0 + .dw 0xf0c0, 0xc18a, 0xf0ff, 0xc18a, 0x21, 0 + .dw 0xf140, 0xc18a, 0xf17f, 0xc18a, 0x21, 0 + .dw 0xf1c0, 0xc18a, 0xf1ff, 0xc18a, 0x21, 0 + .dw 0xf240, 0xc18a, 0xf27f, 0xc18a, 0x21, 0 + .dw 0xf2c0, 0xc18a, 0xf2ff, 0xc18a, 0x21, 0 + .dw 0xf340, 0xc18a, 0xf37f, 0xc18a, 0x21, 0 + .dw 0xf3c0, 0xc18a, 0xf3ff, 0xc18a, 0x21, 0 + .dw 0xf440, 0xc18a, 0xf47f, 0xc18a, 0x21, 0 + .dw 0xf4c0, 0xc18a, 0xf4ff, 0xc18a, 0x21, 0 + .dw 0xf540, 0xc18a, 0xf57f, 0xc18a, 0x21, 0 + .dw 0xf5c0, 0xc18a, 0xf5ff, 0xc18a, 0x21, 0 + .dw 0xf640, 0xc18a, 0xf67f, 0xc18a, 0x21, 0 + .dw 0xf6c0, 0xc18a, 0xf6ff, 0xc18a, 0x21, 0 + .dw 0xf740, 0xc18a, 0xf77f, 0xc18a, 0x21, 0 + .dw 0xf7c0, 0xc18a, 0xf7ff, 0xc18a, 0x21, 0 + .dw 0xf840, 0xc18a, 0xf87f, 0xc18a, 0x21, 0 + .dw 0xf8c0, 0xc18a, 0xf8ff, 0xc18a, 0x21, 0 + .dw 0xf940, 0xc18a, 0xf97f, 0xc18a, 0x21, 0 + .dw 0xf9c0, 0xc18a, 0x1fff, 0xc18b, 0x21, 0 + .dw 0x2040, 0xc18b, 0x207f, 0xc18b, 0x21, 0 + .dw 0x20c0, 0xc18b, 0x20ff, 0xc18b, 0x21, 0 + .dw 0x2140, 0xc18b, 0x217f, 0xc18b, 0x21, 0 + .dw 0x21c0, 0xc18b, 0x21ff, 0xc18b, 0x21, 0 + .dw 0x2240, 0xc18b, 0x227f, 0xc18b, 0x21, 0 + .dw 0x22c0, 0xc18b, 0x22ff, 0xc18b, 0x21, 0 + .dw 0x2340, 0xc18b, 0x237f, 0xc18b, 0x21, 0 + .dw 0x23c0, 0xc18b, 0x23ff, 0xc18b, 0x21, 0 + .dw 0x2440, 0xc18b, 0x247f, 0xc18b, 0x21, 0 + .dw 0x24c0, 0xc18b, 0x24ff, 0xc18b, 0x21, 0 + .dw 0x2540, 0xc18b, 0x257f, 0xc18b, 0x21, 0 + .dw 0x25c0, 0xc18b, 0x25ff, 0xc18b, 0x21, 0 + .dw 0x2640, 0xc18b, 0x267f, 0xc18b, 0x21, 0 + .dw 0x26c0, 0xc18b, 0x26ff, 0xc18b, 0x21, 0 + .dw 0x2740, 0xc18b, 0x277f, 0xc18b, 0x21, 0 + .dw 0x27c0, 0xc18b, 0x27ff, 0xc18b, 0x21, 0 + .dw 0x2840, 0xc18b, 0x287f, 0xc18b, 0x21, 0 + .dw 0x28c0, 0xc18b, 0x28ff, 0xc18b, 0x21, 0 + .dw 0x2940, 0xc18b, 0x297f, 0xc18b, 0x21, 0 + .dw 0x29c0, 0xc18b, 0x29ff, 0xc18b, 0x21, 0 + .dw 0x2a40, 0xc18b, 0x2a7f, 0xc18b, 0x21, 0 + .dw 0x2ac0, 0xc18b, 0x2aff, 0xc18b, 0x21, 0 + .dw 0x2b40, 0xc18b, 0x2b7f, 0xc18b, 0x21, 0 + .dw 0x2bc0, 0xc18b, 0x2bff, 0xc18b, 0x21, 0 + .dw 0x2c40, 0xc18b, 0x2c7f, 0xc18b, 0x21, 0 + .dw 0x2cc0, 0xc18b, 0x2cff, 0xc18b, 0x21, 0 + .dw 0x2d40, 0xc18b, 0x2d7f, 0xc18b, 0x21, 0 + .dw 0x2dc0, 0xc18b, 0x2dff, 0xc18b, 0x21, 0 + .dw 0x2e40, 0xc18b, 0x2e7f, 0xc18b, 0x21, 0 + .dw 0x2ec0, 0xc18b, 0x2eff, 0xc18b, 0x21, 0 + .dw 0x2f40, 0xc18b, 0x2f7f, 0xc18b, 0x21, 0 + .dw 0x2fc0, 0xc18b, 0x2fff, 0xc18b, 0x21, 0 + .dw 0x3040, 0xc18b, 0x307f, 0xc18b, 0x21, 0 + .dw 0x30c0, 0xc18b, 0x30ff, 0xc18b, 0x21, 0 + .dw 0x3140, 0xc18b, 0x317f, 0xc18b, 0x21, 0 + .dw 0x31c0, 0xc18b, 0x31ff, 0xc18b, 0x21, 0 + .dw 0x3240, 0xc18b, 0x327f, 0xc18b, 0x21, 0 + .dw 0x32c0, 0xc18b, 0x32ff, 0xc18b, 0x21, 0 + .dw 0x3340, 0xc18b, 0x337f, 0xc18b, 0x21, 0 + .dw 0x33c0, 0xc18b, 0x33ff, 0xc18b, 0x21, 0 + .dw 0x3440, 0xc18b, 0x347f, 0xc18b, 0x21, 0 + .dw 0x34c0, 0xc18b, 0x34ff, 0xc18b, 0x21, 0 + .dw 0x3540, 0xc18b, 0x357f, 0xc18b, 0x21, 0 + .dw 0x35c0, 0xc18b, 0x35ff, 0xc18b, 0x21, 0 + .dw 0x3640, 0xc18b, 0x367f, 0xc18b, 0x21, 0 + .dw 0x36c0, 0xc18b, 0x36ff, 0xc18b, 0x21, 0 + .dw 0x3740, 0xc18b, 0x377f, 0xc18b, 0x21, 0 + .dw 0x37c0, 0xc18b, 0x37ff, 0xc18b, 0x21, 0 + .dw 0x3840, 0xc18b, 0x387f, 0xc18b, 0x21, 0 + .dw 0x38c0, 0xc18b, 0x38ff, 0xc18b, 0x21, 0 + .dw 0x3940, 0xc18b, 0x397f, 0xc18b, 0x21, 0 + .dw 0x39c0, 0xc18b, 0xffff, 0xc18b, 0x21, 0 + .dw 0x0040, 0xc18c, 0x007f, 0xc18c, 0x21, 0 + .dw 0x00c0, 0xc18c, 0x00ff, 0xc18c, 0x21, 0 + .dw 0x0140, 0xc18c, 0x017f, 0xc18c, 0x21, 0 + .dw 0x01c0, 0xc18c, 0x01ff, 0xc18c, 0x21, 0 + .dw 0x0240, 0xc18c, 0x027f, 0xc18c, 0x21, 0 + .dw 0x02c0, 0xc18c, 0x02ff, 0xc18c, 0x21, 0 + .dw 0x0340, 0xc18c, 0x037f, 0xc18c, 0x21, 0 + .dw 0x03c0, 0xc18c, 0x03ff, 0xc18c, 0x21, 0 + .dw 0x0440, 0xc18c, 0x047f, 0xc18c, 0x21, 0 + .dw 0x04c0, 0xc18c, 0x04ff, 0xc18c, 0x21, 0 + .dw 0x0540, 0xc18c, 0x057f, 0xc18c, 0x21, 0 + .dw 0x05c0, 0xc18c, 0x05ff, 0xc18c, 0x21, 0 + .dw 0x0640, 0xc18c, 0x067f, 0xc18c, 0x21, 0 + .dw 0x06c0, 0xc18c, 0x06ff, 0xc18c, 0x21, 0 + .dw 0x0740, 0xc18c, 0x077f, 0xc18c, 0x21, 0 + .dw 0x07c0, 0xc18c, 0x07ff, 0xc18c, 0x21, 0 + .dw 0x0840, 0xc18c, 0x087f, 0xc18c, 0x21, 0 + .dw 0x08c0, 0xc18c, 0x08ff, 0xc18c, 0x21, 0 + .dw 0x0940, 0xc18c, 0x097f, 0xc18c, 0x21, 0 + .dw 0x09c0, 0xc18c, 0x09ff, 0xc18c, 0x21, 0 + .dw 0x0a40, 0xc18c, 0x0a7f, 0xc18c, 0x21, 0 + .dw 0x0ac0, 0xc18c, 0x0aff, 0xc18c, 0x21, 0 + .dw 0x0b40, 0xc18c, 0x0b7f, 0xc18c, 0x21, 0 + .dw 0x0bc0, 0xc18c, 0x0bff, 0xc18c, 0x21, 0 + .dw 0x0c40, 0xc18c, 0x0c7f, 0xc18c, 0x21, 0 + .dw 0x0cc0, 0xc18c, 0x0cff, 0xc18c, 0x21, 0 + .dw 0x0d40, 0xc18c, 0x0d7f, 0xc18c, 0x21, 0 + .dw 0x0dc0, 0xc18c, 0x0dff, 0xc18c, 0x21, 0 + .dw 0x0e40, 0xc18c, 0x0e7f, 0xc18c, 0x21, 0 + .dw 0x0ec0, 0xc18c, 0x0eff, 0xc18c, 0x21, 0 + .dw 0x0f40, 0xc18c, 0x0f7f, 0xc18c, 0x21, 0 + .dw 0x0fc0, 0xc18c, 0x0fff, 0xc18c, 0x21, 0 + .dw 0x1040, 0xc18c, 0x107f, 0xc18c, 0x21, 0 + .dw 0x10c0, 0xc18c, 0x10ff, 0xc18c, 0x21, 0 + .dw 0x1140, 0xc18c, 0x117f, 0xc18c, 0x21, 0 + .dw 0x11c0, 0xc18c, 0x11ff, 0xc18c, 0x21, 0 + .dw 0x1240, 0xc18c, 0x127f, 0xc18c, 0x21, 0 + .dw 0x12c0, 0xc18c, 0x12ff, 0xc18c, 0x21, 0 + .dw 0x1340, 0xc18c, 0x137f, 0xc18c, 0x21, 0 + .dw 0x13c0, 0xc18c, 0x13ff, 0xc18c, 0x21, 0 + .dw 0x1440, 0xc18c, 0x147f, 0xc18c, 0x21, 0 + .dw 0x14c0, 0xc18c, 0x14ff, 0xc18c, 0x21, 0 + .dw 0x1540, 0xc18c, 0x157f, 0xc18c, 0x21, 0 + .dw 0x15c0, 0xc18c, 0x15ff, 0xc18c, 0x21, 0 + .dw 0x1640, 0xc18c, 0x167f, 0xc18c, 0x21, 0 + .dw 0x16c0, 0xc18c, 0x16ff, 0xc18c, 0x21, 0 + .dw 0x1740, 0xc18c, 0x177f, 0xc18c, 0x21, 0 + .dw 0x17c0, 0xc18c, 0x17ff, 0xc18c, 0x21, 0 + .dw 0x1840, 0xc18c, 0x187f, 0xc18c, 0x21, 0 + .dw 0x18c0, 0xc18c, 0x18ff, 0xc18c, 0x21, 0 + .dw 0x1940, 0xc18c, 0x197f, 0xc18c, 0x21, 0 + .dw 0x19c0, 0xc18c, 0x1fff, 0xc18c, 0x21, 0 + .dw 0x2040, 0xc18c, 0x207f, 0xc18c, 0x21, 0 + .dw 0x20c0, 0xc18c, 0x20ff, 0xc18c, 0x21, 0 + .dw 0x2140, 0xc18c, 0x217f, 0xc18c, 0x21, 0 + .dw 0x21c0, 0xc18c, 0x21ff, 0xc18c, 0x21, 0 + .dw 0x2240, 0xc18c, 0x227f, 0xc18c, 0x21, 0 + .dw 0x22c0, 0xc18c, 0x22ff, 0xc18c, 0x21, 0 + .dw 0x2340, 0xc18c, 0x237f, 0xc18c, 0x21, 0 + .dw 0x23c0, 0xc18c, 0x23ff, 0xc18c, 0x21, 0 + .dw 0x2440, 0xc18c, 0x247f, 0xc18c, 0x21, 0 + .dw 0x24c0, 0xc18c, 0x24ff, 0xc18c, 0x21, 0 + .dw 0x2540, 0xc18c, 0x257f, 0xc18c, 0x21, 0 + .dw 0x25c0, 0xc18c, 0x25ff, 0xc18c, 0x21, 0 + .dw 0x2640, 0xc18c, 0x267f, 0xc18c, 0x21, 0 + .dw 0x26c0, 0xc18c, 0x26ff, 0xc18c, 0x21, 0 + .dw 0x2740, 0xc18c, 0x277f, 0xc18c, 0x21, 0 + .dw 0x27c0, 0xc18c, 0x27ff, 0xc18c, 0x21, 0 + .dw 0x2840, 0xc18c, 0x287f, 0xc18c, 0x21, 0 + .dw 0x28c0, 0xc18c, 0x28ff, 0xc18c, 0x21, 0 + .dw 0x2940, 0xc18c, 0x297f, 0xc18c, 0x21, 0 + .dw 0x29c0, 0xc18c, 0x29ff, 0xc18c, 0x21, 0 + .dw 0x2a40, 0xc18c, 0x2a7f, 0xc18c, 0x21, 0 + .dw 0x2ac0, 0xc18c, 0x2aff, 0xc18c, 0x21, 0 + .dw 0x2b40, 0xc18c, 0x2b7f, 0xc18c, 0x21, 0 + .dw 0x2bc0, 0xc18c, 0x2bff, 0xc18c, 0x21, 0 + .dw 0x2c40, 0xc18c, 0x2c7f, 0xc18c, 0x21, 0 + .dw 0x2cc0, 0xc18c, 0x2cff, 0xc18c, 0x21, 0 + .dw 0x2d40, 0xc18c, 0x2d7f, 0xc18c, 0x21, 0 + .dw 0x2dc0, 0xc18c, 0x2dff, 0xc18c, 0x21, 0 + .dw 0x2e40, 0xc18c, 0x2e7f, 0xc18c, 0x21, 0 + .dw 0x2ec0, 0xc18c, 0x2eff, 0xc18c, 0x21, 0 + .dw 0x2f40, 0xc18c, 0x2f7f, 0xc18c, 0x21, 0 + .dw 0x2fc0, 0xc18c, 0x2fff, 0xc18c, 0x21, 0 + .dw 0x3040, 0xc18c, 0x307f, 0xc18c, 0x21, 0 + .dw 0x30c0, 0xc18c, 0x30ff, 0xc18c, 0x21, 0 + .dw 0x3140, 0xc18c, 0x317f, 0xc18c, 0x21, 0 + .dw 0x31c0, 0xc18c, 0x31ff, 0xc18c, 0x21, 0 + .dw 0x3240, 0xc18c, 0x327f, 0xc18c, 0x21, 0 + .dw 0x32c0, 0xc18c, 0x32ff, 0xc18c, 0x21, 0 + .dw 0x3340, 0xc18c, 0x337f, 0xc18c, 0x21, 0 + .dw 0x33c0, 0xc18c, 0x33ff, 0xc18c, 0x21, 0 + .dw 0x3440, 0xc18c, 0x347f, 0xc18c, 0x21, 0 + .dw 0x34c0, 0xc18c, 0x34ff, 0xc18c, 0x21, 0 + .dw 0x3540, 0xc18c, 0x357f, 0xc18c, 0x21, 0 + .dw 0x35c0, 0xc18c, 0x35ff, 0xc18c, 0x21, 0 + .dw 0x3640, 0xc18c, 0x367f, 0xc18c, 0x21, 0 + .dw 0x36c0, 0xc18c, 0x36ff, 0xc18c, 0x21, 0 + .dw 0x3740, 0xc18c, 0x377f, 0xc18c, 0x21, 0 + .dw 0x37c0, 0xc18c, 0x37ff, 0xc18c, 0x21, 0 + .dw 0x3840, 0xc18c, 0x387f, 0xc18c, 0x21, 0 + .dw 0x38c0, 0xc18c, 0x38ff, 0xc18c, 0x21, 0 + .dw 0x3940, 0xc18c, 0x397f, 0xc18c, 0x21, 0 + .dw 0x39c0, 0xc18c, 0x3fff, 0xc18c, 0x21, 0 + .dw 0x4040, 0xc18c, 0x407f, 0xc18c, 0x21, 0 + .dw 0x40c0, 0xc18c, 0x40ff, 0xc18c, 0x21, 0 + .dw 0x4140, 0xc18c, 0x417f, 0xc18c, 0x21, 0 + .dw 0x41c0, 0xc18c, 0x41ff, 0xc18c, 0x21, 0 + .dw 0x4240, 0xc18c, 0x427f, 0xc18c, 0x21, 0 + .dw 0x42c0, 0xc18c, 0x42ff, 0xc18c, 0x21, 0 + .dw 0x4340, 0xc18c, 0x437f, 0xc18c, 0x21, 0 + .dw 0x43c0, 0xc18c, 0x43ff, 0xc18c, 0x21, 0 + .dw 0x4440, 0xc18c, 0x447f, 0xc18c, 0x21, 0 + .dw 0x44c0, 0xc18c, 0x44ff, 0xc18c, 0x21, 0 + .dw 0x4540, 0xc18c, 0x457f, 0xc18c, 0x21, 0 + .dw 0x45c0, 0xc18c, 0x45ff, 0xc18c, 0x21, 0 + .dw 0x4640, 0xc18c, 0x467f, 0xc18c, 0x21, 0 + .dw 0x46c0, 0xc18c, 0x46ff, 0xc18c, 0x21, 0 + .dw 0x4740, 0xc18c, 0x477f, 0xc18c, 0x21, 0 + .dw 0x47c0, 0xc18c, 0x47ff, 0xc18c, 0x21, 0 + .dw 0x4840, 0xc18c, 0x487f, 0xc18c, 0x21, 0 + .dw 0x48c0, 0xc18c, 0x48ff, 0xc18c, 0x21, 0 + .dw 0x4940, 0xc18c, 0x497f, 0xc18c, 0x21, 0 + .dw 0x49c0, 0xc18c, 0x49ff, 0xc18c, 0x21, 0 + .dw 0x4a40, 0xc18c, 0x4a7f, 0xc18c, 0x21, 0 + .dw 0x4ac0, 0xc18c, 0x4aff, 0xc18c, 0x21, 0 + .dw 0x4b40, 0xc18c, 0x4b7f, 0xc18c, 0x21, 0 + .dw 0x4bc0, 0xc18c, 0x4bff, 0xc18c, 0x21, 0 + .dw 0x4c40, 0xc18c, 0x4c7f, 0xc18c, 0x21, 0 + .dw 0x4cc0, 0xc18c, 0x4cff, 0xc18c, 0x21, 0 + .dw 0x4d40, 0xc18c, 0x4d7f, 0xc18c, 0x21, 0 + .dw 0x4dc0, 0xc18c, 0x4dff, 0xc18c, 0x21, 0 + .dw 0x4e40, 0xc18c, 0x4e7f, 0xc18c, 0x21, 0 + .dw 0x4ec0, 0xc18c, 0x4eff, 0xc18c, 0x21, 0 + .dw 0x4f40, 0xc18c, 0x4f7f, 0xc18c, 0x21, 0 + .dw 0x4fc0, 0xc18c, 0x4fff, 0xc18c, 0x21, 0 + .dw 0x5040, 0xc18c, 0x507f, 0xc18c, 0x21, 0 + .dw 0x50c0, 0xc18c, 0x50ff, 0xc18c, 0x21, 0 + .dw 0x5140, 0xc18c, 0x517f, 0xc18c, 0x21, 0 + .dw 0x51c0, 0xc18c, 0x51ff, 0xc18c, 0x21, 0 + .dw 0x5240, 0xc18c, 0x527f, 0xc18c, 0x21, 0 + .dw 0x52c0, 0xc18c, 0x52ff, 0xc18c, 0x21, 0 + .dw 0x5340, 0xc18c, 0x537f, 0xc18c, 0x21, 0 + .dw 0x53c0, 0xc18c, 0x53ff, 0xc18c, 0x21, 0 + .dw 0x5440, 0xc18c, 0x547f, 0xc18c, 0x21, 0 + .dw 0x54c0, 0xc18c, 0x54ff, 0xc18c, 0x21, 0 + .dw 0x5540, 0xc18c, 0x557f, 0xc18c, 0x21, 0 + .dw 0x55c0, 0xc18c, 0x55ff, 0xc18c, 0x21, 0 + .dw 0x5640, 0xc18c, 0x567f, 0xc18c, 0x21, 0 + .dw 0x56c0, 0xc18c, 0x56ff, 0xc18c, 0x21, 0 + .dw 0x5740, 0xc18c, 0x577f, 0xc18c, 0x21, 0 + .dw 0x57c0, 0xc18c, 0x57ff, 0xc18c, 0x21, 0 + .dw 0x5840, 0xc18c, 0x587f, 0xc18c, 0x21, 0 + .dw 0x58c0, 0xc18c, 0x58ff, 0xc18c, 0x21, 0 + .dw 0x5940, 0xc18c, 0x597f, 0xc18c, 0x21, 0 + .dw 0x59c0, 0xc18c, 0x5fff, 0xc18c, 0x21, 0 + .dw 0x6040, 0xc18c, 0x607f, 0xc18c, 0x21, 0 + .dw 0x60c0, 0xc18c, 0x60ff, 0xc18c, 0x21, 0 + .dw 0x6140, 0xc18c, 0x617f, 0xc18c, 0x21, 0 + .dw 0x61c0, 0xc18c, 0x61ff, 0xc18c, 0x21, 0 + .dw 0x6240, 0xc18c, 0x627f, 0xc18c, 0x21, 0 + .dw 0x62c0, 0xc18c, 0x62ff, 0xc18c, 0x21, 0 + .dw 0x6340, 0xc18c, 0x637f, 0xc18c, 0x21, 0 + .dw 0x63c0, 0xc18c, 0x63ff, 0xc18c, 0x21, 0 + .dw 0x6440, 0xc18c, 0x647f, 0xc18c, 0x21, 0 + .dw 0x64c0, 0xc18c, 0x64ff, 0xc18c, 0x21, 0 + .dw 0x6540, 0xc18c, 0x657f, 0xc18c, 0x21, 0 + .dw 0x65c0, 0xc18c, 0x65ff, 0xc18c, 0x21, 0 + .dw 0x6640, 0xc18c, 0x667f, 0xc18c, 0x21, 0 + .dw 0x66c0, 0xc18c, 0x66ff, 0xc18c, 0x21, 0 + .dw 0x6740, 0xc18c, 0x677f, 0xc18c, 0x21, 0 + .dw 0x67c0, 0xc18c, 0x67ff, 0xc18c, 0x21, 0 + .dw 0x6840, 0xc18c, 0x687f, 0xc18c, 0x21, 0 + .dw 0x68c0, 0xc18c, 0x68ff, 0xc18c, 0x21, 0 + .dw 0x6940, 0xc18c, 0x697f, 0xc18c, 0x21, 0 + .dw 0x69c0, 0xc18c, 0x69ff, 0xc18c, 0x21, 0 + .dw 0x6a40, 0xc18c, 0x6a7f, 0xc18c, 0x21, 0 + .dw 0x6ac0, 0xc18c, 0x6aff, 0xc18c, 0x21, 0 + .dw 0x6b40, 0xc18c, 0x6b7f, 0xc18c, 0x21, 0 + .dw 0x6bc0, 0xc18c, 0x6bff, 0xc18c, 0x21, 0 + .dw 0x6c40, 0xc18c, 0x6c7f, 0xc18c, 0x21, 0 + .dw 0x6cc0, 0xc18c, 0x6cff, 0xc18c, 0x21, 0 + .dw 0x6d40, 0xc18c, 0x6d7f, 0xc18c, 0x21, 0 + .dw 0x6dc0, 0xc18c, 0x6dff, 0xc18c, 0x21, 0 + .dw 0x6e40, 0xc18c, 0x6e7f, 0xc18c, 0x21, 0 + .dw 0x6ec0, 0xc18c, 0x6eff, 0xc18c, 0x21, 0 + .dw 0x6f40, 0xc18c, 0x6f7f, 0xc18c, 0x21, 0 + .dw 0x6fc0, 0xc18c, 0x6fff, 0xc18c, 0x21, 0 + .dw 0x7040, 0xc18c, 0x707f, 0xc18c, 0x21, 0 + .dw 0x70c0, 0xc18c, 0x70ff, 0xc18c, 0x21, 0 + .dw 0x7140, 0xc18c, 0x717f, 0xc18c, 0x21, 0 + .dw 0x71c0, 0xc18c, 0x71ff, 0xc18c, 0x21, 0 + .dw 0x7240, 0xc18c, 0x727f, 0xc18c, 0x21, 0 + .dw 0x72c0, 0xc18c, 0x72ff, 0xc18c, 0x21, 0 + .dw 0x7340, 0xc18c, 0x737f, 0xc18c, 0x21, 0 + .dw 0x73c0, 0xc18c, 0x73ff, 0xc18c, 0x21, 0 + .dw 0x7440, 0xc18c, 0x747f, 0xc18c, 0x21, 0 + .dw 0x74c0, 0xc18c, 0x74ff, 0xc18c, 0x21, 0 + .dw 0x7540, 0xc18c, 0x757f, 0xc18c, 0x21, 0 + .dw 0x75c0, 0xc18c, 0x75ff, 0xc18c, 0x21, 0 + .dw 0x7640, 0xc18c, 0x767f, 0xc18c, 0x21, 0 + .dw 0x76c0, 0xc18c, 0x76ff, 0xc18c, 0x21, 0 + .dw 0x7740, 0xc18c, 0x777f, 0xc18c, 0x21, 0 + .dw 0x77c0, 0xc18c, 0x77ff, 0xc18c, 0x21, 0 + .dw 0x7840, 0xc18c, 0x787f, 0xc18c, 0x21, 0 + .dw 0x78c0, 0xc18c, 0x78ff, 0xc18c, 0x21, 0 + .dw 0x7940, 0xc18c, 0x797f, 0xc18c, 0x21, 0 + .dw 0x79c0, 0xc18c, 0x7fff, 0xc18c, 0x21, 0 + .dw 0x8040, 0xc18c, 0x807f, 0xc18c, 0x21, 0 + .dw 0x80c0, 0xc18c, 0x80ff, 0xc18c, 0x21, 0 + .dw 0x8140, 0xc18c, 0x817f, 0xc18c, 0x21, 0 + .dw 0x81c0, 0xc18c, 0x81ff, 0xc18c, 0x21, 0 + .dw 0x8240, 0xc18c, 0x827f, 0xc18c, 0x21, 0 + .dw 0x82c0, 0xc18c, 0x82ff, 0xc18c, 0x21, 0 + .dw 0x8340, 0xc18c, 0x837f, 0xc18c, 0x21, 0 + .dw 0x83c0, 0xc18c, 0x83ff, 0xc18c, 0x21, 0 + .dw 0x8440, 0xc18c, 0x847f, 0xc18c, 0x21, 0 + .dw 0x84c0, 0xc18c, 0x84ff, 0xc18c, 0x21, 0 + .dw 0x8540, 0xc18c, 0x857f, 0xc18c, 0x21, 0 + .dw 0x85c0, 0xc18c, 0x85ff, 0xc18c, 0x21, 0 + .dw 0x8640, 0xc18c, 0x867f, 0xc18c, 0x21, 0 + .dw 0x86c0, 0xc18c, 0x86ff, 0xc18c, 0x21, 0 + .dw 0x8740, 0xc18c, 0x877f, 0xc18c, 0x21, 0 + .dw 0x87c0, 0xc18c, 0x87ff, 0xc18c, 0x21, 0 + .dw 0x8840, 0xc18c, 0x887f, 0xc18c, 0x21, 0 + .dw 0x88c0, 0xc18c, 0x88ff, 0xc18c, 0x21, 0 + .dw 0x8940, 0xc18c, 0x897f, 0xc18c, 0x21, 0 + .dw 0x89c0, 0xc18c, 0x89ff, 0xc18c, 0x21, 0 + .dw 0x8a40, 0xc18c, 0x8a7f, 0xc18c, 0x21, 0 + .dw 0x8ac0, 0xc18c, 0x8aff, 0xc18c, 0x21, 0 + .dw 0x8b40, 0xc18c, 0x8b7f, 0xc18c, 0x21, 0 + .dw 0x8bc0, 0xc18c, 0x8bff, 0xc18c, 0x21, 0 + .dw 0x8c40, 0xc18c, 0x8c7f, 0xc18c, 0x21, 0 + .dw 0x8cc0, 0xc18c, 0x8cff, 0xc18c, 0x21, 0 + .dw 0x8d40, 0xc18c, 0x8d7f, 0xc18c, 0x21, 0 + .dw 0x8dc0, 0xc18c, 0x8dff, 0xc18c, 0x21, 0 + .dw 0x8e40, 0xc18c, 0x8e7f, 0xc18c, 0x21, 0 + .dw 0x8ec0, 0xc18c, 0x8eff, 0xc18c, 0x21, 0 + .dw 0x8f40, 0xc18c, 0x8f7f, 0xc18c, 0x21, 0 + .dw 0x8fc0, 0xc18c, 0x8fff, 0xc18c, 0x21, 0 + .dw 0x9040, 0xc18c, 0x907f, 0xc18c, 0x21, 0 + .dw 0x90c0, 0xc18c, 0x90ff, 0xc18c, 0x21, 0 + .dw 0x9140, 0xc18c, 0x917f, 0xc18c, 0x21, 0 + .dw 0x91c0, 0xc18c, 0x91ff, 0xc18c, 0x21, 0 + .dw 0x9240, 0xc18c, 0x927f, 0xc18c, 0x21, 0 + .dw 0x92c0, 0xc18c, 0x92ff, 0xc18c, 0x21, 0 + .dw 0x9340, 0xc18c, 0x937f, 0xc18c, 0x21, 0 + .dw 0x93c0, 0xc18c, 0x93ff, 0xc18c, 0x21, 0 + .dw 0x9440, 0xc18c, 0x947f, 0xc18c, 0x21, 0 + .dw 0x94c0, 0xc18c, 0x94ff, 0xc18c, 0x21, 0 + .dw 0x9540, 0xc18c, 0x957f, 0xc18c, 0x21, 0 + .dw 0x95c0, 0xc18c, 0x95ff, 0xc18c, 0x21, 0 + .dw 0x9640, 0xc18c, 0x967f, 0xc18c, 0x21, 0 + .dw 0x96c0, 0xc18c, 0x96ff, 0xc18c, 0x21, 0 + .dw 0x9740, 0xc18c, 0x977f, 0xc18c, 0x21, 0 + .dw 0x97c0, 0xc18c, 0x97ff, 0xc18c, 0x21, 0 + .dw 0x9840, 0xc18c, 0x987f, 0xc18c, 0x21, 0 + .dw 0x98c0, 0xc18c, 0x98ff, 0xc18c, 0x21, 0 + .dw 0x9940, 0xc18c, 0x997f, 0xc18c, 0x21, 0 + .dw 0x99c0, 0xc18c, 0x9fff, 0xc18c, 0x21, 0 + .dw 0xa040, 0xc18c, 0xa07f, 0xc18c, 0x21, 0 + .dw 0xa0c0, 0xc18c, 0xa0ff, 0xc18c, 0x21, 0 + .dw 0xa140, 0xc18c, 0xa17f, 0xc18c, 0x21, 0 + .dw 0xa1c0, 0xc18c, 0xa1ff, 0xc18c, 0x21, 0 + .dw 0xa240, 0xc18c, 0xa27f, 0xc18c, 0x21, 0 + .dw 0xa2c0, 0xc18c, 0xa2ff, 0xc18c, 0x21, 0 + .dw 0xa340, 0xc18c, 0xa37f, 0xc18c, 0x21, 0 + .dw 0xa3c0, 0xc18c, 0xa3ff, 0xc18c, 0x21, 0 + .dw 0xa440, 0xc18c, 0xa47f, 0xc18c, 0x21, 0 + .dw 0xa4c0, 0xc18c, 0xa4ff, 0xc18c, 0x21, 0 + .dw 0xa540, 0xc18c, 0xa57f, 0xc18c, 0x21, 0 + .dw 0xa5c0, 0xc18c, 0xa5ff, 0xc18c, 0x21, 0 + .dw 0xa640, 0xc18c, 0xa67f, 0xc18c, 0x21, 0 + .dw 0xa6c0, 0xc18c, 0xa6ff, 0xc18c, 0x21, 0 + .dw 0xa740, 0xc18c, 0xa77f, 0xc18c, 0x21, 0 + .dw 0xa7c0, 0xc18c, 0xa7ff, 0xc18c, 0x21, 0 + .dw 0xa840, 0xc18c, 0xa87f, 0xc18c, 0x21, 0 + .dw 0xa8c0, 0xc18c, 0xa8ff, 0xc18c, 0x21, 0 + .dw 0xa940, 0xc18c, 0xa97f, 0xc18c, 0x21, 0 + .dw 0xa9c0, 0xc18c, 0xa9ff, 0xc18c, 0x21, 0 + .dw 0xaa40, 0xc18c, 0xaa7f, 0xc18c, 0x21, 0 + .dw 0xaac0, 0xc18c, 0xaaff, 0xc18c, 0x21, 0 + .dw 0xab40, 0xc18c, 0xab7f, 0xc18c, 0x21, 0 + .dw 0xabc0, 0xc18c, 0xabff, 0xc18c, 0x21, 0 + .dw 0xac40, 0xc18c, 0xac7f, 0xc18c, 0x21, 0 + .dw 0xacc0, 0xc18c, 0xacff, 0xc18c, 0x21, 0 + .dw 0xad40, 0xc18c, 0xad7f, 0xc18c, 0x21, 0 + .dw 0xadc0, 0xc18c, 0xadff, 0xc18c, 0x21, 0 + .dw 0xae40, 0xc18c, 0xae7f, 0xc18c, 0x21, 0 + .dw 0xaec0, 0xc18c, 0xaeff, 0xc18c, 0x21, 0 + .dw 0xaf40, 0xc18c, 0xaf7f, 0xc18c, 0x21, 0 + .dw 0xafc0, 0xc18c, 0xafff, 0xc18c, 0x21, 0 + .dw 0xb040, 0xc18c, 0xb07f, 0xc18c, 0x21, 0 + .dw 0xb0c0, 0xc18c, 0xb0ff, 0xc18c, 0x21, 0 + .dw 0xb140, 0xc18c, 0xb17f, 0xc18c, 0x21, 0 + .dw 0xb1c0, 0xc18c, 0xb1ff, 0xc18c, 0x21, 0 + .dw 0xb240, 0xc18c, 0xb27f, 0xc18c, 0x21, 0 + .dw 0xb2c0, 0xc18c, 0xb2ff, 0xc18c, 0x21, 0 + .dw 0xb340, 0xc18c, 0xb37f, 0xc18c, 0x21, 0 + .dw 0xb3c0, 0xc18c, 0xb3ff, 0xc18c, 0x21, 0 + .dw 0xb440, 0xc18c, 0xb47f, 0xc18c, 0x21, 0 + .dw 0xb4c0, 0xc18c, 0xb4ff, 0xc18c, 0x21, 0 + .dw 0xb540, 0xc18c, 0xb57f, 0xc18c, 0x21, 0 + .dw 0xb5c0, 0xc18c, 0xb5ff, 0xc18c, 0x21, 0 + .dw 0xb640, 0xc18c, 0xb67f, 0xc18c, 0x21, 0 + .dw 0xb6c0, 0xc18c, 0xb6ff, 0xc18c, 0x21, 0 + .dw 0xb740, 0xc18c, 0xb77f, 0xc18c, 0x21, 0 + .dw 0xb7c0, 0xc18c, 0xb7ff, 0xc18c, 0x21, 0 + .dw 0xb840, 0xc18c, 0xb87f, 0xc18c, 0x21, 0 + .dw 0xb8c0, 0xc18c, 0xb8ff, 0xc18c, 0x21, 0 + .dw 0xb940, 0xc18c, 0xb97f, 0xc18c, 0x21, 0 + .dw 0xb9c0, 0xc18c, 0xbfff, 0xc18c, 0x21, 0 + .dw 0xc040, 0xc18c, 0xc07f, 0xc18c, 0x21, 0 + .dw 0xc0c0, 0xc18c, 0xc0ff, 0xc18c, 0x21, 0 + .dw 0xc140, 0xc18c, 0xc17f, 0xc18c, 0x21, 0 + .dw 0xc1c0, 0xc18c, 0xc1ff, 0xc18c, 0x21, 0 + .dw 0xc240, 0xc18c, 0xc27f, 0xc18c, 0x21, 0 + .dw 0xc2c0, 0xc18c, 0xc2ff, 0xc18c, 0x21, 0 + .dw 0xc340, 0xc18c, 0xc37f, 0xc18c, 0x21, 0 + .dw 0xc3c0, 0xc18c, 0xc3ff, 0xc18c, 0x21, 0 + .dw 0xc440, 0xc18c, 0xc47f, 0xc18c, 0x21, 0 + .dw 0xc4c0, 0xc18c, 0xc4ff, 0xc18c, 0x21, 0 + .dw 0xc540, 0xc18c, 0xc57f, 0xc18c, 0x21, 0 + .dw 0xc5c0, 0xc18c, 0xc5ff, 0xc18c, 0x21, 0 + .dw 0xc640, 0xc18c, 0xc67f, 0xc18c, 0x21, 0 + .dw 0xc6c0, 0xc18c, 0xc6ff, 0xc18c, 0x21, 0 + .dw 0xc740, 0xc18c, 0xc77f, 0xc18c, 0x21, 0 + .dw 0xc7c0, 0xc18c, 0xc7ff, 0xc18c, 0x21, 0 + .dw 0xc840, 0xc18c, 0xc87f, 0xc18c, 0x21, 0 + .dw 0xc8c0, 0xc18c, 0xc8ff, 0xc18c, 0x21, 0 + .dw 0xc940, 0xc18c, 0xc97f, 0xc18c, 0x21, 0 + .dw 0xc9c0, 0xc18c, 0xc9ff, 0xc18c, 0x21, 0 + .dw 0xca40, 0xc18c, 0xca7f, 0xc18c, 0x21, 0 + .dw 0xcac0, 0xc18c, 0xcaff, 0xc18c, 0x21, 0 + .dw 0xcb40, 0xc18c, 0xcb7f, 0xc18c, 0x21, 0 + .dw 0xcbc0, 0xc18c, 0xcbff, 0xc18c, 0x21, 0 + .dw 0xcc40, 0xc18c, 0xcc7f, 0xc18c, 0x21, 0 + .dw 0xccc0, 0xc18c, 0xccff, 0xc18c, 0x21, 0 + .dw 0xcd40, 0xc18c, 0xcd7f, 0xc18c, 0x21, 0 + .dw 0xcdc0, 0xc18c, 0xcdff, 0xc18c, 0x21, 0 + .dw 0xce40, 0xc18c, 0xce7f, 0xc18c, 0x21, 0 + .dw 0xcec0, 0xc18c, 0xceff, 0xc18c, 0x21, 0 + .dw 0xcf40, 0xc18c, 0xcf7f, 0xc18c, 0x21, 0 + .dw 0xcfc0, 0xc18c, 0xcfff, 0xc18c, 0x21, 0 + .dw 0xd040, 0xc18c, 0xd07f, 0xc18c, 0x21, 0 + .dw 0xd0c0, 0xc18c, 0xd0ff, 0xc18c, 0x21, 0 + .dw 0xd140, 0xc18c, 0xd17f, 0xc18c, 0x21, 0 + .dw 0xd1c0, 0xc18c, 0xd1ff, 0xc18c, 0x21, 0 + .dw 0xd240, 0xc18c, 0xd27f, 0xc18c, 0x21, 0 + .dw 0xd2c0, 0xc18c, 0xd2ff, 0xc18c, 0x21, 0 + .dw 0xd340, 0xc18c, 0xd37f, 0xc18c, 0x21, 0 + .dw 0xd3c0, 0xc18c, 0xd3ff, 0xc18c, 0x21, 0 + .dw 0xd440, 0xc18c, 0xd47f, 0xc18c, 0x21, 0 + .dw 0xd4c0, 0xc18c, 0xd4ff, 0xc18c, 0x21, 0 + .dw 0xd540, 0xc18c, 0xd57f, 0xc18c, 0x21, 0 + .dw 0xd5c0, 0xc18c, 0xd5ff, 0xc18c, 0x21, 0 + .dw 0xd640, 0xc18c, 0xd67f, 0xc18c, 0x21, 0 + .dw 0xd6c0, 0xc18c, 0xd6ff, 0xc18c, 0x21, 0 + .dw 0xd740, 0xc18c, 0xd77f, 0xc18c, 0x21, 0 + .dw 0xd7c0, 0xc18c, 0xd7ff, 0xc18c, 0x21, 0 + .dw 0xd840, 0xc18c, 0xd87f, 0xc18c, 0x21, 0 + .dw 0xd8c0, 0xc18c, 0xd8ff, 0xc18c, 0x21, 0 + .dw 0xd940, 0xc18c, 0xd97f, 0xc18c, 0x21, 0 + .dw 0xd9c0, 0xc18c, 0xdfff, 0xc18c, 0x21, 0 + .dw 0xe040, 0xc18c, 0xe07f, 0xc18c, 0x21, 0 + .dw 0xe0c0, 0xc18c, 0xe0ff, 0xc18c, 0x21, 0 + .dw 0xe140, 0xc18c, 0xe17f, 0xc18c, 0x21, 0 + .dw 0xe1c0, 0xc18c, 0xe1ff, 0xc18c, 0x21, 0 + .dw 0xe240, 0xc18c, 0xe27f, 0xc18c, 0x21, 0 + .dw 0xe2c0, 0xc18c, 0xe2ff, 0xc18c, 0x21, 0 + .dw 0xe340, 0xc18c, 0xe37f, 0xc18c, 0x21, 0 + .dw 0xe3c0, 0xc18c, 0xe3ff, 0xc18c, 0x21, 0 + .dw 0xe440, 0xc18c, 0xe47f, 0xc18c, 0x21, 0 + .dw 0xe4c0, 0xc18c, 0xe4ff, 0xc18c, 0x21, 0 + .dw 0xe540, 0xc18c, 0xe57f, 0xc18c, 0x21, 0 + .dw 0xe5c0, 0xc18c, 0xe5ff, 0xc18c, 0x21, 0 + .dw 0xe640, 0xc18c, 0xe67f, 0xc18c, 0x21, 0 + .dw 0xe6c0, 0xc18c, 0xe6ff, 0xc18c, 0x21, 0 + .dw 0xe740, 0xc18c, 0xe77f, 0xc18c, 0x21, 0 + .dw 0xe7c0, 0xc18c, 0xe7ff, 0xc18c, 0x21, 0 + .dw 0xe840, 0xc18c, 0xe87f, 0xc18c, 0x21, 0 + .dw 0xe8c0, 0xc18c, 0xe8ff, 0xc18c, 0x21, 0 + .dw 0xe940, 0xc18c, 0xe97f, 0xc18c, 0x21, 0 + .dw 0xe9c0, 0xc18c, 0xe9ff, 0xc18c, 0x21, 0 + .dw 0xea40, 0xc18c, 0xea7f, 0xc18c, 0x21, 0 + .dw 0xeac0, 0xc18c, 0xeaff, 0xc18c, 0x21, 0 + .dw 0xeb40, 0xc18c, 0xeb7f, 0xc18c, 0x21, 0 + .dw 0xebc0, 0xc18c, 0xebff, 0xc18c, 0x21, 0 + .dw 0xec40, 0xc18c, 0xec7f, 0xc18c, 0x21, 0 + .dw 0xecc0, 0xc18c, 0xecff, 0xc18c, 0x21, 0 + .dw 0xed40, 0xc18c, 0xed7f, 0xc18c, 0x21, 0 + .dw 0xedc0, 0xc18c, 0xedff, 0xc18c, 0x21, 0 + .dw 0xee40, 0xc18c, 0xee7f, 0xc18c, 0x21, 0 + .dw 0xeec0, 0xc18c, 0xeeff, 0xc18c, 0x21, 0 + .dw 0xef40, 0xc18c, 0xef7f, 0xc18c, 0x21, 0 + .dw 0xefc0, 0xc18c, 0xefff, 0xc18c, 0x21, 0 + .dw 0xf040, 0xc18c, 0xf07f, 0xc18c, 0x21, 0 + .dw 0xf0c0, 0xc18c, 0xf0ff, 0xc18c, 0x21, 0 + .dw 0xf140, 0xc18c, 0xf17f, 0xc18c, 0x21, 0 + .dw 0xf1c0, 0xc18c, 0xf1ff, 0xc18c, 0x21, 0 + .dw 0xf240, 0xc18c, 0xf27f, 0xc18c, 0x21, 0 + .dw 0xf2c0, 0xc18c, 0xf2ff, 0xc18c, 0x21, 0 + .dw 0xf340, 0xc18c, 0xf37f, 0xc18c, 0x21, 0 + .dw 0xf3c0, 0xc18c, 0xf3ff, 0xc18c, 0x21, 0 + .dw 0xf440, 0xc18c, 0xf47f, 0xc18c, 0x21, 0 + .dw 0xf4c0, 0xc18c, 0xf4ff, 0xc18c, 0x21, 0 + .dw 0xf540, 0xc18c, 0xf57f, 0xc18c, 0x21, 0 + .dw 0xf5c0, 0xc18c, 0xf5ff, 0xc18c, 0x21, 0 + .dw 0xf640, 0xc18c, 0xf67f, 0xc18c, 0x21, 0 + .dw 0xf6c0, 0xc18c, 0xf6ff, 0xc18c, 0x21, 0 + .dw 0xf740, 0xc18c, 0xf77f, 0xc18c, 0x21, 0 + .dw 0xf7c0, 0xc18c, 0xf7ff, 0xc18c, 0x21, 0 + .dw 0xf840, 0xc18c, 0xf87f, 0xc18c, 0x21, 0 + .dw 0xf8c0, 0xc18c, 0xf8ff, 0xc18c, 0x21, 0 + .dw 0xf940, 0xc18c, 0xf97f, 0xc18c, 0x21, 0 + .dw 0xf9c0, 0xc18c, 0xffff, 0xc18c, 0x21, 0 + .dw 0x0040, 0xc18d, 0x007f, 0xc18d, 0x21, 0 + .dw 0x00c0, 0xc18d, 0x00ff, 0xc18d, 0x21, 0 + .dw 0x0140, 0xc18d, 0x017f, 0xc18d, 0x21, 0 + .dw 0x01c0, 0xc18d, 0x01ff, 0xc18d, 0x21, 0 + .dw 0x0240, 0xc18d, 0x027f, 0xc18d, 0x21, 0 + .dw 0x02c0, 0xc18d, 0x02ff, 0xc18d, 0x21, 0 + .dw 0x0340, 0xc18d, 0x037f, 0xc18d, 0x21, 0 + .dw 0x03c0, 0xc18d, 0x03ff, 0xc18d, 0x21, 0 + .dw 0x0440, 0xc18d, 0x047f, 0xc18d, 0x21, 0 + .dw 0x04c0, 0xc18d, 0x04ff, 0xc18d, 0x21, 0 + .dw 0x0540, 0xc18d, 0x057f, 0xc18d, 0x21, 0 + .dw 0x05c0, 0xc18d, 0x05ff, 0xc18d, 0x21, 0 + .dw 0x0640, 0xc18d, 0x067f, 0xc18d, 0x21, 0 + .dw 0x06c0, 0xc18d, 0x06ff, 0xc18d, 0x21, 0 + .dw 0x0740, 0xc18d, 0x077f, 0xc18d, 0x21, 0 + .dw 0x07c0, 0xc18d, 0x07ff, 0xc18d, 0x21, 0 + .dw 0x0840, 0xc18d, 0x087f, 0xc18d, 0x21, 0 + .dw 0x08c0, 0xc18d, 0x08ff, 0xc18d, 0x21, 0 + .dw 0x0940, 0xc18d, 0x097f, 0xc18d, 0x21, 0 + .dw 0x09c0, 0xc18d, 0x09ff, 0xc18d, 0x21, 0 + .dw 0x0a40, 0xc18d, 0x0a7f, 0xc18d, 0x21, 0 + .dw 0x0ac0, 0xc18d, 0x0aff, 0xc18d, 0x21, 0 + .dw 0x0b40, 0xc18d, 0x0b7f, 0xc18d, 0x21, 0 + .dw 0x0bc0, 0xc18d, 0x0bff, 0xc18d, 0x21, 0 + .dw 0x0c40, 0xc18d, 0x0c7f, 0xc18d, 0x21, 0 + .dw 0x0cc0, 0xc18d, 0x0cff, 0xc18d, 0x21, 0 + .dw 0x0d40, 0xc18d, 0x0d7f, 0xc18d, 0x21, 0 + .dw 0x0dc0, 0xc18d, 0x0dff, 0xc18d, 0x21, 0 + .dw 0x0e40, 0xc18d, 0x0e7f, 0xc18d, 0x21, 0 + .dw 0x0ec0, 0xc18d, 0x0eff, 0xc18d, 0x21, 0 + .dw 0x0f40, 0xc18d, 0x0f7f, 0xc18d, 0x21, 0 + .dw 0x0fc0, 0xc18d, 0x0fff, 0xc18d, 0x21, 0 + .dw 0x1040, 0xc18d, 0x107f, 0xc18d, 0x21, 0 + .dw 0x10c0, 0xc18d, 0x10ff, 0xc18d, 0x21, 0 + .dw 0x1140, 0xc18d, 0x117f, 0xc18d, 0x21, 0 + .dw 0x11c0, 0xc18d, 0x11ff, 0xc18d, 0x21, 0 + .dw 0x1240, 0xc18d, 0x127f, 0xc18d, 0x21, 0 + .dw 0x12c0, 0xc18d, 0x12ff, 0xc18d, 0x21, 0 + .dw 0x1340, 0xc18d, 0x137f, 0xc18d, 0x21, 0 + .dw 0x13c0, 0xc18d, 0x13ff, 0xc18d, 0x21, 0 + .dw 0x1440, 0xc18d, 0x147f, 0xc18d, 0x21, 0 + .dw 0x14c0, 0xc18d, 0x14ff, 0xc18d, 0x21, 0 + .dw 0x1540, 0xc18d, 0x157f, 0xc18d, 0x21, 0 + .dw 0x15c0, 0xc18d, 0x15ff, 0xc18d, 0x21, 0 + .dw 0x1640, 0xc18d, 0x167f, 0xc18d, 0x21, 0 + .dw 0x16c0, 0xc18d, 0x16ff, 0xc18d, 0x21, 0 + .dw 0x1740, 0xc18d, 0x177f, 0xc18d, 0x21, 0 + .dw 0x17c0, 0xc18d, 0x17ff, 0xc18d, 0x21, 0 + .dw 0x1840, 0xc18d, 0x187f, 0xc18d, 0x21, 0 + .dw 0x18c0, 0xc18d, 0x18ff, 0xc18d, 0x21, 0 + .dw 0x1940, 0xc18d, 0x197f, 0xc18d, 0x21, 0 + .dw 0x19c0, 0xc18d, 0x1fff, 0xc18d, 0x21, 0 + .dw 0x2040, 0xc18d, 0x207f, 0xc18d, 0x21, 0 + .dw 0x20c0, 0xc18d, 0x20ff, 0xc18d, 0x21, 0 + .dw 0x2140, 0xc18d, 0x217f, 0xc18d, 0x21, 0 + .dw 0x21c0, 0xc18d, 0x21ff, 0xc18d, 0x21, 0 + .dw 0x2240, 0xc18d, 0x227f, 0xc18d, 0x21, 0 + .dw 0x22c0, 0xc18d, 0x22ff, 0xc18d, 0x21, 0 + .dw 0x2340, 0xc18d, 0x237f, 0xc18d, 0x21, 0 + .dw 0x23c0, 0xc18d, 0x23ff, 0xc18d, 0x21, 0 + .dw 0x2440, 0xc18d, 0x247f, 0xc18d, 0x21, 0 + .dw 0x24c0, 0xc18d, 0x24ff, 0xc18d, 0x21, 0 + .dw 0x2540, 0xc18d, 0x257f, 0xc18d, 0x21, 0 + .dw 0x25c0, 0xc18d, 0x25ff, 0xc18d, 0x21, 0 + .dw 0x2640, 0xc18d, 0x267f, 0xc18d, 0x21, 0 + .dw 0x26c0, 0xc18d, 0x26ff, 0xc18d, 0x21, 0 + .dw 0x2740, 0xc18d, 0x277f, 0xc18d, 0x21, 0 + .dw 0x27c0, 0xc18d, 0x27ff, 0xc18d, 0x21, 0 + .dw 0x2840, 0xc18d, 0x287f, 0xc18d, 0x21, 0 + .dw 0x28c0, 0xc18d, 0x28ff, 0xc18d, 0x21, 0 + .dw 0x2940, 0xc18d, 0x297f, 0xc18d, 0x21, 0 + .dw 0x29c0, 0xc18d, 0x29ff, 0xc18d, 0x21, 0 + .dw 0x2a40, 0xc18d, 0x2a7f, 0xc18d, 0x21, 0 + .dw 0x2ac0, 0xc18d, 0x2aff, 0xc18d, 0x21, 0 + .dw 0x2b40, 0xc18d, 0x2b7f, 0xc18d, 0x21, 0 + .dw 0x2bc0, 0xc18d, 0x2bff, 0xc18d, 0x21, 0 + .dw 0x2c40, 0xc18d, 0x2c7f, 0xc18d, 0x21, 0 + .dw 0x2cc0, 0xc18d, 0x2cff, 0xc18d, 0x21, 0 + .dw 0x2d40, 0xc18d, 0x2d7f, 0xc18d, 0x21, 0 + .dw 0x2dc0, 0xc18d, 0x2dff, 0xc18d, 0x21, 0 + .dw 0x2e40, 0xc18d, 0x2e7f, 0xc18d, 0x21, 0 + .dw 0x2ec0, 0xc18d, 0x2eff, 0xc18d, 0x21, 0 + .dw 0x2f40, 0xc18d, 0x2f7f, 0xc18d, 0x21, 0 + .dw 0x2fc0, 0xc18d, 0x2fff, 0xc18d, 0x21, 0 + .dw 0x3040, 0xc18d, 0x307f, 0xc18d, 0x21, 0 + .dw 0x30c0, 0xc18d, 0x30ff, 0xc18d, 0x21, 0 + .dw 0x3140, 0xc18d, 0x317f, 0xc18d, 0x21, 0 + .dw 0x31c0, 0xc18d, 0x31ff, 0xc18d, 0x21, 0 + .dw 0x3240, 0xc18d, 0x327f, 0xc18d, 0x21, 0 + .dw 0x32c0, 0xc18d, 0x32ff, 0xc18d, 0x21, 0 + .dw 0x3340, 0xc18d, 0x337f, 0xc18d, 0x21, 0 + .dw 0x33c0, 0xc18d, 0x33ff, 0xc18d, 0x21, 0 + .dw 0x3440, 0xc18d, 0x347f, 0xc18d, 0x21, 0 + .dw 0x34c0, 0xc18d, 0x34ff, 0xc18d, 0x21, 0 + .dw 0x3540, 0xc18d, 0x357f, 0xc18d, 0x21, 0 + .dw 0x35c0, 0xc18d, 0x35ff, 0xc18d, 0x21, 0 + .dw 0x3640, 0xc18d, 0x367f, 0xc18d, 0x21, 0 + .dw 0x36c0, 0xc18d, 0x36ff, 0xc18d, 0x21, 0 + .dw 0x3740, 0xc18d, 0x377f, 0xc18d, 0x21, 0 + .dw 0x37c0, 0xc18d, 0x37ff, 0xc18d, 0x21, 0 + .dw 0x3840, 0xc18d, 0x387f, 0xc18d, 0x21, 0 + .dw 0x38c0, 0xc18d, 0x38ff, 0xc18d, 0x21, 0 + .dw 0x3940, 0xc18d, 0x397f, 0xc18d, 0x21, 0 + .dw 0x39c0, 0xc18d, 0x3fff, 0xc18d, 0x21, 0 + .dw 0x4040, 0xc18d, 0x407f, 0xc18d, 0x21, 0 + .dw 0x40c0, 0xc18d, 0x40ff, 0xc18d, 0x21, 0 + .dw 0x4140, 0xc18d, 0x417f, 0xc18d, 0x21, 0 + .dw 0x41c0, 0xc18d, 0x41ff, 0xc18d, 0x21, 0 + .dw 0x4240, 0xc18d, 0x427f, 0xc18d, 0x21, 0 + .dw 0x42c0, 0xc18d, 0x42ff, 0xc18d, 0x21, 0 + .dw 0x4340, 0xc18d, 0x437f, 0xc18d, 0x21, 0 + .dw 0x43c0, 0xc18d, 0x43ff, 0xc18d, 0x21, 0 + .dw 0x4440, 0xc18d, 0x447f, 0xc18d, 0x21, 0 + .dw 0x44c0, 0xc18d, 0x44ff, 0xc18d, 0x21, 0 + .dw 0x4540, 0xc18d, 0x457f, 0xc18d, 0x21, 0 + .dw 0x45c0, 0xc18d, 0x45ff, 0xc18d, 0x21, 0 + .dw 0x4640, 0xc18d, 0x467f, 0xc18d, 0x21, 0 + .dw 0x46c0, 0xc18d, 0x46ff, 0xc18d, 0x21, 0 + .dw 0x4740, 0xc18d, 0x477f, 0xc18d, 0x21, 0 + .dw 0x47c0, 0xc18d, 0x47ff, 0xc18d, 0x21, 0 + .dw 0x4840, 0xc18d, 0x487f, 0xc18d, 0x21, 0 + .dw 0x48c0, 0xc18d, 0x48ff, 0xc18d, 0x21, 0 + .dw 0x4940, 0xc18d, 0x497f, 0xc18d, 0x21, 0 + .dw 0x49c0, 0xc18d, 0x49ff, 0xc18d, 0x21, 0 + .dw 0x4a40, 0xc18d, 0x4a7f, 0xc18d, 0x21, 0 + .dw 0x4ac0, 0xc18d, 0x4aff, 0xc18d, 0x21, 0 + .dw 0x4b40, 0xc18d, 0x4b7f, 0xc18d, 0x21, 0 + .dw 0x4bc0, 0xc18d, 0x4bff, 0xc18d, 0x21, 0 + .dw 0x4c40, 0xc18d, 0x4c7f, 0xc18d, 0x21, 0 + .dw 0x4cc0, 0xc18d, 0x4cff, 0xc18d, 0x21, 0 + .dw 0x4d40, 0xc18d, 0x4d7f, 0xc18d, 0x21, 0 + .dw 0x4dc0, 0xc18d, 0x4dff, 0xc18d, 0x21, 0 + .dw 0x4e40, 0xc18d, 0x4e7f, 0xc18d, 0x21, 0 + .dw 0x4ec0, 0xc18d, 0x4eff, 0xc18d, 0x21, 0 + .dw 0x4f40, 0xc18d, 0x4f7f, 0xc18d, 0x21, 0 + .dw 0x4fc0, 0xc18d, 0x4fff, 0xc18d, 0x21, 0 + .dw 0x5040, 0xc18d, 0x507f, 0xc18d, 0x21, 0 + .dw 0x50c0, 0xc18d, 0x50ff, 0xc18d, 0x21, 0 + .dw 0x5140, 0xc18d, 0x517f, 0xc18d, 0x21, 0 + .dw 0x51c0, 0xc18d, 0x51ff, 0xc18d, 0x21, 0 + .dw 0x5240, 0xc18d, 0x527f, 0xc18d, 0x21, 0 + .dw 0x52c0, 0xc18d, 0x52ff, 0xc18d, 0x21, 0 + .dw 0x5340, 0xc18d, 0x537f, 0xc18d, 0x21, 0 + .dw 0x53c0, 0xc18d, 0x53ff, 0xc18d, 0x21, 0 + .dw 0x5440, 0xc18d, 0x547f, 0xc18d, 0x21, 0 + .dw 0x54c0, 0xc18d, 0x54ff, 0xc18d, 0x21, 0 + .dw 0x5540, 0xc18d, 0x557f, 0xc18d, 0x21, 0 + .dw 0x55c0, 0xc18d, 0x55ff, 0xc18d, 0x21, 0 + .dw 0x5640, 0xc18d, 0x567f, 0xc18d, 0x21, 0 + .dw 0x56c0, 0xc18d, 0x56ff, 0xc18d, 0x21, 0 + .dw 0x5740, 0xc18d, 0x577f, 0xc18d, 0x21, 0 + .dw 0x57c0, 0xc18d, 0x57ff, 0xc18d, 0x21, 0 + .dw 0x5840, 0xc18d, 0x587f, 0xc18d, 0x21, 0 + .dw 0x58c0, 0xc18d, 0x58ff, 0xc18d, 0x21, 0 + .dw 0x5940, 0xc18d, 0x597f, 0xc18d, 0x21, 0 + .dw 0x59c0, 0xc18d, 0x5fff, 0xc18d, 0x21, 0 + .dw 0x6040, 0xc18d, 0x607f, 0xc18d, 0x21, 0 + .dw 0x60c0, 0xc18d, 0x60ff, 0xc18d, 0x21, 0 + .dw 0x6140, 0xc18d, 0x617f, 0xc18d, 0x21, 0 + .dw 0x61c0, 0xc18d, 0x61ff, 0xc18d, 0x21, 0 + .dw 0x6240, 0xc18d, 0x627f, 0xc18d, 0x21, 0 + .dw 0x62c0, 0xc18d, 0x62ff, 0xc18d, 0x21, 0 + .dw 0x6340, 0xc18d, 0x637f, 0xc18d, 0x21, 0 + .dw 0x63c0, 0xc18d, 0x63ff, 0xc18d, 0x21, 0 + .dw 0x6440, 0xc18d, 0x647f, 0xc18d, 0x21, 0 + .dw 0x64c0, 0xc18d, 0x64ff, 0xc18d, 0x21, 0 + .dw 0x6540, 0xc18d, 0x657f, 0xc18d, 0x21, 0 + .dw 0x65c0, 0xc18d, 0x65ff, 0xc18d, 0x21, 0 + .dw 0x6640, 0xc18d, 0x667f, 0xc18d, 0x21, 0 + .dw 0x66c0, 0xc18d, 0x66ff, 0xc18d, 0x21, 0 + .dw 0x6740, 0xc18d, 0x677f, 0xc18d, 0x21, 0 + .dw 0x67c0, 0xc18d, 0x67ff, 0xc18d, 0x21, 0 + .dw 0x6840, 0xc18d, 0x687f, 0xc18d, 0x21, 0 + .dw 0x68c0, 0xc18d, 0x68ff, 0xc18d, 0x21, 0 + .dw 0x6940, 0xc18d, 0x697f, 0xc18d, 0x21, 0 + .dw 0x69c0, 0xc18d, 0x69ff, 0xc18d, 0x21, 0 + .dw 0x6a40, 0xc18d, 0x6a7f, 0xc18d, 0x21, 0 + .dw 0x6ac0, 0xc18d, 0x6aff, 0xc18d, 0x21, 0 + .dw 0x6b40, 0xc18d, 0x6b7f, 0xc18d, 0x21, 0 + .dw 0x6bc0, 0xc18d, 0x6bff, 0xc18d, 0x21, 0 + .dw 0x6c40, 0xc18d, 0x6c7f, 0xc18d, 0x21, 0 + .dw 0x6cc0, 0xc18d, 0x6cff, 0xc18d, 0x21, 0 + .dw 0x6d40, 0xc18d, 0x6d7f, 0xc18d, 0x21, 0 + .dw 0x6dc0, 0xc18d, 0x6dff, 0xc18d, 0x21, 0 + .dw 0x6e40, 0xc18d, 0x6e7f, 0xc18d, 0x21, 0 + .dw 0x6ec0, 0xc18d, 0x6eff, 0xc18d, 0x21, 0 + .dw 0x6f40, 0xc18d, 0x6f7f, 0xc18d, 0x21, 0 + .dw 0x6fc0, 0xc18d, 0x6fff, 0xc18d, 0x21, 0 + .dw 0x7040, 0xc18d, 0x707f, 0xc18d, 0x21, 0 + .dw 0x70c0, 0xc18d, 0x70ff, 0xc18d, 0x21, 0 + .dw 0x7140, 0xc18d, 0x717f, 0xc18d, 0x21, 0 + .dw 0x71c0, 0xc18d, 0x71ff, 0xc18d, 0x21, 0 + .dw 0x7240, 0xc18d, 0x727f, 0xc18d, 0x21, 0 + .dw 0x72c0, 0xc18d, 0x72ff, 0xc18d, 0x21, 0 + .dw 0x7340, 0xc18d, 0x737f, 0xc18d, 0x21, 0 + .dw 0x73c0, 0xc18d, 0x73ff, 0xc18d, 0x21, 0 + .dw 0x7440, 0xc18d, 0x747f, 0xc18d, 0x21, 0 + .dw 0x74c0, 0xc18d, 0x74ff, 0xc18d, 0x21, 0 + .dw 0x7540, 0xc18d, 0x757f, 0xc18d, 0x21, 0 + .dw 0x75c0, 0xc18d, 0x75ff, 0xc18d, 0x21, 0 + .dw 0x7640, 0xc18d, 0x767f, 0xc18d, 0x21, 0 + .dw 0x76c0, 0xc18d, 0x76ff, 0xc18d, 0x21, 0 + .dw 0x7740, 0xc18d, 0x777f, 0xc18d, 0x21, 0 + .dw 0x77c0, 0xc18d, 0x77ff, 0xc18d, 0x21, 0 + .dw 0x7840, 0xc18d, 0x787f, 0xc18d, 0x21, 0 + .dw 0x78c0, 0xc18d, 0x78ff, 0xc18d, 0x21, 0 + .dw 0x7940, 0xc18d, 0x797f, 0xc18d, 0x21, 0 + .dw 0x79c0, 0xc18d, 0x7fff, 0xc18d, 0x21, 0 + .dw 0x8040, 0xc18d, 0x807f, 0xc18d, 0x21, 0 + .dw 0x80c0, 0xc18d, 0x80ff, 0xc18d, 0x21, 0 + .dw 0x8140, 0xc18d, 0x817f, 0xc18d, 0x21, 0 + .dw 0x81c0, 0xc18d, 0x81ff, 0xc18d, 0x21, 0 + .dw 0x8240, 0xc18d, 0x827f, 0xc18d, 0x21, 0 + .dw 0x82c0, 0xc18d, 0x82ff, 0xc18d, 0x21, 0 + .dw 0x8340, 0xc18d, 0x837f, 0xc18d, 0x21, 0 + .dw 0x83c0, 0xc18d, 0x83ff, 0xc18d, 0x21, 0 + .dw 0x8440, 0xc18d, 0x847f, 0xc18d, 0x21, 0 + .dw 0x84c0, 0xc18d, 0x84ff, 0xc18d, 0x21, 0 + .dw 0x8540, 0xc18d, 0x857f, 0xc18d, 0x21, 0 + .dw 0x85c0, 0xc18d, 0x85ff, 0xc18d, 0x21, 0 + .dw 0x8640, 0xc18d, 0x867f, 0xc18d, 0x21, 0 + .dw 0x86c0, 0xc18d, 0x86ff, 0xc18d, 0x21, 0 + .dw 0x8740, 0xc18d, 0x877f, 0xc18d, 0x21, 0 + .dw 0x87c0, 0xc18d, 0x87ff, 0xc18d, 0x21, 0 + .dw 0x8840, 0xc18d, 0x887f, 0xc18d, 0x21, 0 + .dw 0x88c0, 0xc18d, 0x88ff, 0xc18d, 0x21, 0 + .dw 0x8940, 0xc18d, 0x897f, 0xc18d, 0x21, 0 + .dw 0x89c0, 0xc18d, 0x89ff, 0xc18d, 0x21, 0 + .dw 0x8a40, 0xc18d, 0x8a7f, 0xc18d, 0x21, 0 + .dw 0x8ac0, 0xc18d, 0x8aff, 0xc18d, 0x21, 0 + .dw 0x8b40, 0xc18d, 0x8b7f, 0xc18d, 0x21, 0 + .dw 0x8bc0, 0xc18d, 0x8bff, 0xc18d, 0x21, 0 + .dw 0x8c40, 0xc18d, 0x8c7f, 0xc18d, 0x21, 0 + .dw 0x8cc0, 0xc18d, 0x8cff, 0xc18d, 0x21, 0 + .dw 0x8d40, 0xc18d, 0x8d7f, 0xc18d, 0x21, 0 + .dw 0x8dc0, 0xc18d, 0x8dff, 0xc18d, 0x21, 0 + .dw 0x8e40, 0xc18d, 0x8e7f, 0xc18d, 0x21, 0 + .dw 0x8ec0, 0xc18d, 0x8eff, 0xc18d, 0x21, 0 + .dw 0x8f40, 0xc18d, 0x8f7f, 0xc18d, 0x21, 0 + .dw 0x8fc0, 0xc18d, 0x8fff, 0xc18d, 0x21, 0 + .dw 0x9040, 0xc18d, 0x907f, 0xc18d, 0x21, 0 + .dw 0x90c0, 0xc18d, 0x90ff, 0xc18d, 0x21, 0 + .dw 0x9140, 0xc18d, 0x917f, 0xc18d, 0x21, 0 + .dw 0x91c0, 0xc18d, 0x91ff, 0xc18d, 0x21, 0 + .dw 0x9240, 0xc18d, 0x927f, 0xc18d, 0x21, 0 + .dw 0x92c0, 0xc18d, 0x92ff, 0xc18d, 0x21, 0 + .dw 0x9340, 0xc18d, 0x937f, 0xc18d, 0x21, 0 + .dw 0x93c0, 0xc18d, 0x93ff, 0xc18d, 0x21, 0 + .dw 0x9440, 0xc18d, 0x947f, 0xc18d, 0x21, 0 + .dw 0x94c0, 0xc18d, 0x94ff, 0xc18d, 0x21, 0 + .dw 0x9540, 0xc18d, 0x957f, 0xc18d, 0x21, 0 + .dw 0x95c0, 0xc18d, 0x95ff, 0xc18d, 0x21, 0 + .dw 0x9640, 0xc18d, 0x967f, 0xc18d, 0x21, 0 + .dw 0x96c0, 0xc18d, 0x96ff, 0xc18d, 0x21, 0 + .dw 0x9740, 0xc18d, 0x977f, 0xc18d, 0x21, 0 + .dw 0x97c0, 0xc18d, 0x97ff, 0xc18d, 0x21, 0 + .dw 0x9840, 0xc18d, 0x987f, 0xc18d, 0x21, 0 + .dw 0x98c0, 0xc18d, 0x98ff, 0xc18d, 0x21, 0 + .dw 0x9940, 0xc18d, 0x997f, 0xc18d, 0x21, 0 + .dw 0x99c0, 0xc18d, 0x9fff, 0xc18d, 0x21, 0 + .dw 0xa040, 0xc18d, 0xa07f, 0xc18d, 0x21, 0 + .dw 0xa0c0, 0xc18d, 0xa0ff, 0xc18d, 0x21, 0 + .dw 0xa140, 0xc18d, 0xa17f, 0xc18d, 0x21, 0 + .dw 0xa1c0, 0xc18d, 0xa1ff, 0xc18d, 0x21, 0 + .dw 0xa240, 0xc18d, 0xa27f, 0xc18d, 0x21, 0 + .dw 0xa2c0, 0xc18d, 0xa2ff, 0xc18d, 0x21, 0 + .dw 0xa340, 0xc18d, 0xa37f, 0xc18d, 0x21, 0 + .dw 0xa3c0, 0xc18d, 0xa3ff, 0xc18d, 0x21, 0 + .dw 0xa440, 0xc18d, 0xa47f, 0xc18d, 0x21, 0 + .dw 0xa4c0, 0xc18d, 0xa4ff, 0xc18d, 0x21, 0 + .dw 0xa540, 0xc18d, 0xa57f, 0xc18d, 0x21, 0 + .dw 0xa5c0, 0xc18d, 0xa5ff, 0xc18d, 0x21, 0 + .dw 0xa640, 0xc18d, 0xa67f, 0xc18d, 0x21, 0 + .dw 0xa6c0, 0xc18d, 0xa6ff, 0xc18d, 0x21, 0 + .dw 0xa740, 0xc18d, 0xa77f, 0xc18d, 0x21, 0 + .dw 0xa7c0, 0xc18d, 0xa7ff, 0xc18d, 0x21, 0 + .dw 0xa840, 0xc18d, 0xa87f, 0xc18d, 0x21, 0 + .dw 0xa8c0, 0xc18d, 0xa8ff, 0xc18d, 0x21, 0 + .dw 0xa940, 0xc18d, 0xa97f, 0xc18d, 0x21, 0 + .dw 0xa9c0, 0xc18d, 0xa9ff, 0xc18d, 0x21, 0 + .dw 0xaa40, 0xc18d, 0xaa7f, 0xc18d, 0x21, 0 + .dw 0xaac0, 0xc18d, 0xaaff, 0xc18d, 0x21, 0 + .dw 0xab40, 0xc18d, 0xab7f, 0xc18d, 0x21, 0 + .dw 0xabc0, 0xc18d, 0xabff, 0xc18d, 0x21, 0 + .dw 0xac40, 0xc18d, 0xac7f, 0xc18d, 0x21, 0 + .dw 0xacc0, 0xc18d, 0xacff, 0xc18d, 0x21, 0 + .dw 0xad40, 0xc18d, 0xad7f, 0xc18d, 0x21, 0 + .dw 0xadc0, 0xc18d, 0xadff, 0xc18d, 0x21, 0 + .dw 0xae40, 0xc18d, 0xae7f, 0xc18d, 0x21, 0 + .dw 0xaec0, 0xc18d, 0xaeff, 0xc18d, 0x21, 0 + .dw 0xaf40, 0xc18d, 0xaf7f, 0xc18d, 0x21, 0 + .dw 0xafc0, 0xc18d, 0xafff, 0xc18d, 0x21, 0 + .dw 0xb040, 0xc18d, 0xb07f, 0xc18d, 0x21, 0 + .dw 0xb0c0, 0xc18d, 0xb0ff, 0xc18d, 0x21, 0 + .dw 0xb140, 0xc18d, 0xb17f, 0xc18d, 0x21, 0 + .dw 0xb1c0, 0xc18d, 0xb1ff, 0xc18d, 0x21, 0 + .dw 0xb240, 0xc18d, 0xb27f, 0xc18d, 0x21, 0 + .dw 0xb2c0, 0xc18d, 0xb2ff, 0xc18d, 0x21, 0 + .dw 0xb340, 0xc18d, 0xb37f, 0xc18d, 0x21, 0 + .dw 0xb3c0, 0xc18d, 0xb3ff, 0xc18d, 0x21, 0 + .dw 0xb440, 0xc18d, 0xb47f, 0xc18d, 0x21, 0 + .dw 0xb4c0, 0xc18d, 0xb4ff, 0xc18d, 0x21, 0 + .dw 0xb540, 0xc18d, 0xb57f, 0xc18d, 0x21, 0 + .dw 0xb5c0, 0xc18d, 0xb5ff, 0xc18d, 0x21, 0 + .dw 0xb640, 0xc18d, 0xb67f, 0xc18d, 0x21, 0 + .dw 0xb6c0, 0xc18d, 0xb6ff, 0xc18d, 0x21, 0 + .dw 0xb740, 0xc18d, 0xb77f, 0xc18d, 0x21, 0 + .dw 0xb7c0, 0xc18d, 0xb7ff, 0xc18d, 0x21, 0 + .dw 0xb840, 0xc18d, 0xb87f, 0xc18d, 0x21, 0 + .dw 0xb8c0, 0xc18d, 0xb8ff, 0xc18d, 0x21, 0 + .dw 0xb940, 0xc18d, 0xb97f, 0xc18d, 0x21, 0 + .dw 0xb9c0, 0xc18d, 0xbfff, 0xc18d, 0x21, 0 + .dw 0xc040, 0xc18d, 0xc07f, 0xc18d, 0x21, 0 + .dw 0xc0c0, 0xc18d, 0xc0ff, 0xc18d, 0x21, 0 + .dw 0xc140, 0xc18d, 0xc17f, 0xc18d, 0x21, 0 + .dw 0xc1c0, 0xc18d, 0xc1ff, 0xc18d, 0x21, 0 + .dw 0xc240, 0xc18d, 0xc27f, 0xc18d, 0x21, 0 + .dw 0xc2c0, 0xc18d, 0xc2ff, 0xc18d, 0x21, 0 + .dw 0xc340, 0xc18d, 0xc37f, 0xc18d, 0x21, 0 + .dw 0xc3c0, 0xc18d, 0xc3ff, 0xc18d, 0x21, 0 + .dw 0xc440, 0xc18d, 0xc47f, 0xc18d, 0x21, 0 + .dw 0xc4c0, 0xc18d, 0xc4ff, 0xc18d, 0x21, 0 + .dw 0xc540, 0xc18d, 0xc57f, 0xc18d, 0x21, 0 + .dw 0xc5c0, 0xc18d, 0xc5ff, 0xc18d, 0x21, 0 + .dw 0xc640, 0xc18d, 0xc67f, 0xc18d, 0x21, 0 + .dw 0xc6c0, 0xc18d, 0xc6ff, 0xc18d, 0x21, 0 + .dw 0xc740, 0xc18d, 0xc77f, 0xc18d, 0x21, 0 + .dw 0xc7c0, 0xc18d, 0xc7ff, 0xc18d, 0x21, 0 + .dw 0xc840, 0xc18d, 0xc87f, 0xc18d, 0x21, 0 + .dw 0xc8c0, 0xc18d, 0xc8ff, 0xc18d, 0x21, 0 + .dw 0xc940, 0xc18d, 0xc97f, 0xc18d, 0x21, 0 + .dw 0xc9c0, 0xc18d, 0xc9ff, 0xc18d, 0x21, 0 + .dw 0xca40, 0xc18d, 0xca7f, 0xc18d, 0x21, 0 + .dw 0xcac0, 0xc18d, 0xcaff, 0xc18d, 0x21, 0 + .dw 0xcb40, 0xc18d, 0xcb7f, 0xc18d, 0x21, 0 + .dw 0xcbc0, 0xc18d, 0xcbff, 0xc18d, 0x21, 0 + .dw 0xcc40, 0xc18d, 0xcc7f, 0xc18d, 0x21, 0 + .dw 0xccc0, 0xc18d, 0xccff, 0xc18d, 0x21, 0 + .dw 0xcd40, 0xc18d, 0xcd7f, 0xc18d, 0x21, 0 + .dw 0xcdc0, 0xc18d, 0xcdff, 0xc18d, 0x21, 0 + .dw 0xce40, 0xc18d, 0xce7f, 0xc18d, 0x21, 0 + .dw 0xcec0, 0xc18d, 0xceff, 0xc18d, 0x21, 0 + .dw 0xcf40, 0xc18d, 0xcf7f, 0xc18d, 0x21, 0 + .dw 0xcfc0, 0xc18d, 0xcfff, 0xc18d, 0x21, 0 + .dw 0xd040, 0xc18d, 0xd07f, 0xc18d, 0x21, 0 + .dw 0xd0c0, 0xc18d, 0xd0ff, 0xc18d, 0x21, 0 + .dw 0xd140, 0xc18d, 0xd17f, 0xc18d, 0x21, 0 + .dw 0xd1c0, 0xc18d, 0xd1ff, 0xc18d, 0x21, 0 + .dw 0xd240, 0xc18d, 0xd27f, 0xc18d, 0x21, 0 + .dw 0xd2c0, 0xc18d, 0xd2ff, 0xc18d, 0x21, 0 + .dw 0xd340, 0xc18d, 0xd37f, 0xc18d, 0x21, 0 + .dw 0xd3c0, 0xc18d, 0xd3ff, 0xc18d, 0x21, 0 + .dw 0xd440, 0xc18d, 0xd47f, 0xc18d, 0x21, 0 + .dw 0xd4c0, 0xc18d, 0xd4ff, 0xc18d, 0x21, 0 + .dw 0xd540, 0xc18d, 0xd57f, 0xc18d, 0x21, 0 + .dw 0xd5c0, 0xc18d, 0xd5ff, 0xc18d, 0x21, 0 + .dw 0xd640, 0xc18d, 0xd67f, 0xc18d, 0x21, 0 + .dw 0xd6c0, 0xc18d, 0xd6ff, 0xc18d, 0x21, 0 + .dw 0xd740, 0xc18d, 0xd77f, 0xc18d, 0x21, 0 + .dw 0xd7c0, 0xc18d, 0xd7ff, 0xc18d, 0x21, 0 + .dw 0xd840, 0xc18d, 0xd87f, 0xc18d, 0x21, 0 + .dw 0xd8c0, 0xc18d, 0xd8ff, 0xc18d, 0x21, 0 + .dw 0xd940, 0xc18d, 0xd97f, 0xc18d, 0x21, 0 + .dw 0xd9c0, 0xc18d, 0xdfff, 0xc18d, 0x21, 0 + .dw 0xe040, 0xc18d, 0xe07f, 0xc18d, 0x21, 0 + .dw 0xe0c0, 0xc18d, 0xe0ff, 0xc18d, 0x21, 0 + .dw 0xe140, 0xc18d, 0xe17f, 0xc18d, 0x21, 0 + .dw 0xe1c0, 0xc18d, 0xe1ff, 0xc18d, 0x21, 0 + .dw 0xe240, 0xc18d, 0xe27f, 0xc18d, 0x21, 0 + .dw 0xe2c0, 0xc18d, 0xe2ff, 0xc18d, 0x21, 0 + .dw 0xe340, 0xc18d, 0xe37f, 0xc18d, 0x21, 0 + .dw 0xe3c0, 0xc18d, 0xe3ff, 0xc18d, 0x21, 0 + .dw 0xe440, 0xc18d, 0xe47f, 0xc18d, 0x21, 0 + .dw 0xe4c0, 0xc18d, 0xe4ff, 0xc18d, 0x21, 0 + .dw 0xe540, 0xc18d, 0xe57f, 0xc18d, 0x21, 0 + .dw 0xe5c0, 0xc18d, 0xe5ff, 0xc18d, 0x21, 0 + .dw 0xe640, 0xc18d, 0xe67f, 0xc18d, 0x21, 0 + .dw 0xe6c0, 0xc18d, 0xe6ff, 0xc18d, 0x21, 0 + .dw 0xe740, 0xc18d, 0xe77f, 0xc18d, 0x21, 0 + .dw 0xe7c0, 0xc18d, 0xe7ff, 0xc18d, 0x21, 0 + .dw 0xe840, 0xc18d, 0xe87f, 0xc18d, 0x21, 0 + .dw 0xe8c0, 0xc18d, 0xe8ff, 0xc18d, 0x21, 0 + .dw 0xe940, 0xc18d, 0xe97f, 0xc18d, 0x21, 0 + .dw 0xe9c0, 0xc18d, 0xe9ff, 0xc18d, 0x21, 0 + .dw 0xea40, 0xc18d, 0xea7f, 0xc18d, 0x21, 0 + .dw 0xeac0, 0xc18d, 0xeaff, 0xc18d, 0x21, 0 + .dw 0xeb40, 0xc18d, 0xeb7f, 0xc18d, 0x21, 0 + .dw 0xebc0, 0xc18d, 0xebff, 0xc18d, 0x21, 0 + .dw 0xec40, 0xc18d, 0xec7f, 0xc18d, 0x21, 0 + .dw 0xecc0, 0xc18d, 0xecff, 0xc18d, 0x21, 0 + .dw 0xed40, 0xc18d, 0xed7f, 0xc18d, 0x21, 0 + .dw 0xedc0, 0xc18d, 0xedff, 0xc18d, 0x21, 0 + .dw 0xee40, 0xc18d, 0xee7f, 0xc18d, 0x21, 0 + .dw 0xeec0, 0xc18d, 0xeeff, 0xc18d, 0x21, 0 + .dw 0xef40, 0xc18d, 0xef7f, 0xc18d, 0x21, 0 + .dw 0xefc0, 0xc18d, 0xefff, 0xc18d, 0x21, 0 + .dw 0xf040, 0xc18d, 0xf07f, 0xc18d, 0x21, 0 + .dw 0xf0c0, 0xc18d, 0xf0ff, 0xc18d, 0x21, 0 + .dw 0xf140, 0xc18d, 0xf17f, 0xc18d, 0x21, 0 + .dw 0xf1c0, 0xc18d, 0xf1ff, 0xc18d, 0x21, 0 + .dw 0xf240, 0xc18d, 0xf27f, 0xc18d, 0x21, 0 + .dw 0xf2c0, 0xc18d, 0xf2ff, 0xc18d, 0x21, 0 + .dw 0xf340, 0xc18d, 0xf37f, 0xc18d, 0x21, 0 + .dw 0xf3c0, 0xc18d, 0xf3ff, 0xc18d, 0x21, 0 + .dw 0xf440, 0xc18d, 0xf47f, 0xc18d, 0x21, 0 + .dw 0xf4c0, 0xc18d, 0xf4ff, 0xc18d, 0x21, 0 + .dw 0xf540, 0xc18d, 0xf57f, 0xc18d, 0x21, 0 + .dw 0xf5c0, 0xc18d, 0xf5ff, 0xc18d, 0x21, 0 + .dw 0xf640, 0xc18d, 0xf67f, 0xc18d, 0x21, 0 + .dw 0xf6c0, 0xc18d, 0xf6ff, 0xc18d, 0x21, 0 + .dw 0xf740, 0xc18d, 0xf77f, 0xc18d, 0x21, 0 + .dw 0xf7c0, 0xc18d, 0xf7ff, 0xc18d, 0x21, 0 + .dw 0xf840, 0xc18d, 0xf87f, 0xc18d, 0x21, 0 + .dw 0xf8c0, 0xc18d, 0xf8ff, 0xc18d, 0x21, 0 + .dw 0xf940, 0xc18d, 0xf97f, 0xc18d, 0x21, 0 + .dw 0xf9c0, 0xc18d, 0xffff, 0xc18d, 0x21, 0 + .dw 0x0040, 0xc18e, 0x007f, 0xc18e, 0x21, 0 + .dw 0x00c0, 0xc18e, 0x00ff, 0xc18e, 0x21, 0 + .dw 0x0140, 0xc18e, 0x017f, 0xc18e, 0x21, 0 + .dw 0x01c0, 0xc18e, 0x01ff, 0xc18e, 0x21, 0 + .dw 0x0240, 0xc18e, 0x027f, 0xc18e, 0x21, 0 + .dw 0x02c0, 0xc18e, 0x02ff, 0xc18e, 0x21, 0 + .dw 0x0340, 0xc18e, 0x037f, 0xc18e, 0x21, 0 + .dw 0x03c0, 0xc18e, 0x03ff, 0xc18e, 0x21, 0 + .dw 0x0440, 0xc18e, 0x047f, 0xc18e, 0x21, 0 + .dw 0x04c0, 0xc18e, 0x04ff, 0xc18e, 0x21, 0 + .dw 0x0540, 0xc18e, 0x057f, 0xc18e, 0x21, 0 + .dw 0x05c0, 0xc18e, 0x05ff, 0xc18e, 0x21, 0 + .dw 0x0640, 0xc18e, 0x067f, 0xc18e, 0x21, 0 + .dw 0x06c0, 0xc18e, 0x06ff, 0xc18e, 0x21, 0 + .dw 0x0740, 0xc18e, 0x077f, 0xc18e, 0x21, 0 + .dw 0x07c0, 0xc18e, 0x07ff, 0xc18e, 0x21, 0 + .dw 0x0840, 0xc18e, 0x087f, 0xc18e, 0x21, 0 + .dw 0x08c0, 0xc18e, 0x08ff, 0xc18e, 0x21, 0 + .dw 0x0940, 0xc18e, 0x097f, 0xc18e, 0x21, 0 + .dw 0x09c0, 0xc18e, 0x09ff, 0xc18e, 0x21, 0 + .dw 0x0a40, 0xc18e, 0x0a7f, 0xc18e, 0x21, 0 + .dw 0x0ac0, 0xc18e, 0x0aff, 0xc18e, 0x21, 0 + .dw 0x0b40, 0xc18e, 0x0b7f, 0xc18e, 0x21, 0 + .dw 0x0bc0, 0xc18e, 0x0bff, 0xc18e, 0x21, 0 + .dw 0x0c40, 0xc18e, 0x0c7f, 0xc18e, 0x21, 0 + .dw 0x0cc0, 0xc18e, 0x0cff, 0xc18e, 0x21, 0 + .dw 0x0d40, 0xc18e, 0x0d7f, 0xc18e, 0x21, 0 + .dw 0x0dc0, 0xc18e, 0x0dff, 0xc18e, 0x21, 0 + .dw 0x0e40, 0xc18e, 0x0e7f, 0xc18e, 0x21, 0 + .dw 0x0ec0, 0xc18e, 0x0eff, 0xc18e, 0x21, 0 + .dw 0x0f40, 0xc18e, 0x0f7f, 0xc18e, 0x21, 0 + .dw 0x0fc0, 0xc18e, 0x0fff, 0xc18e, 0x21, 0 + .dw 0x1040, 0xc18e, 0x107f, 0xc18e, 0x21, 0 + .dw 0x10c0, 0xc18e, 0x10ff, 0xc18e, 0x21, 0 + .dw 0x1140, 0xc18e, 0x117f, 0xc18e, 0x21, 0 + .dw 0x11c0, 0xc18e, 0x11ff, 0xc18e, 0x21, 0 + .dw 0x1240, 0xc18e, 0x127f, 0xc18e, 0x21, 0 + .dw 0x12c0, 0xc18e, 0x12ff, 0xc18e, 0x21, 0 + .dw 0x1340, 0xc18e, 0x137f, 0xc18e, 0x21, 0 + .dw 0x13c0, 0xc18e, 0x13ff, 0xc18e, 0x21, 0 + .dw 0x1440, 0xc18e, 0x147f, 0xc18e, 0x21, 0 + .dw 0x14c0, 0xc18e, 0x14ff, 0xc18e, 0x21, 0 + .dw 0x1540, 0xc18e, 0x157f, 0xc18e, 0x21, 0 + .dw 0x15c0, 0xc18e, 0x15ff, 0xc18e, 0x21, 0 + .dw 0x1640, 0xc18e, 0x167f, 0xc18e, 0x21, 0 + .dw 0x16c0, 0xc18e, 0x16ff, 0xc18e, 0x21, 0 + .dw 0x1740, 0xc18e, 0x177f, 0xc18e, 0x21, 0 + .dw 0x17c0, 0xc18e, 0x17ff, 0xc18e, 0x21, 0 + .dw 0x1840, 0xc18e, 0x187f, 0xc18e, 0x21, 0 + .dw 0x18c0, 0xc18e, 0x18ff, 0xc18e, 0x21, 0 + .dw 0x1940, 0xc18e, 0x197f, 0xc18e, 0x21, 0 + .dw 0x19c0, 0xc18e, 0x1fff, 0xc18e, 0x21, 0 + .dw 0x2040, 0xc18e, 0x207f, 0xc18e, 0x21, 0 + .dw 0x20c0, 0xc18e, 0x20ff, 0xc18e, 0x21, 0 + .dw 0x2140, 0xc18e, 0x217f, 0xc18e, 0x21, 0 + .dw 0x21c0, 0xc18e, 0x21ff, 0xc18e, 0x21, 0 + .dw 0x2240, 0xc18e, 0x227f, 0xc18e, 0x21, 0 + .dw 0x22c0, 0xc18e, 0x22ff, 0xc18e, 0x21, 0 + .dw 0x2340, 0xc18e, 0x237f, 0xc18e, 0x21, 0 + .dw 0x23c0, 0xc18e, 0x23ff, 0xc18e, 0x21, 0 + .dw 0x2440, 0xc18e, 0x247f, 0xc18e, 0x21, 0 + .dw 0x24c0, 0xc18e, 0x24ff, 0xc18e, 0x21, 0 + .dw 0x2540, 0xc18e, 0x257f, 0xc18e, 0x21, 0 + .dw 0x25c0, 0xc18e, 0x25ff, 0xc18e, 0x21, 0 + .dw 0x2640, 0xc18e, 0x267f, 0xc18e, 0x21, 0 + .dw 0x26c0, 0xc18e, 0x26ff, 0xc18e, 0x21, 0 + .dw 0x2740, 0xc18e, 0x277f, 0xc18e, 0x21, 0 + .dw 0x27c0, 0xc18e, 0x27ff, 0xc18e, 0x21, 0 + .dw 0x2840, 0xc18e, 0x287f, 0xc18e, 0x21, 0 + .dw 0x28c0, 0xc18e, 0x28ff, 0xc18e, 0x21, 0 + .dw 0x2940, 0xc18e, 0x297f, 0xc18e, 0x21, 0 + .dw 0x29c0, 0xc18e, 0x29ff, 0xc18e, 0x21, 0 + .dw 0x2a40, 0xc18e, 0x2a7f, 0xc18e, 0x21, 0 + .dw 0x2ac0, 0xc18e, 0x2aff, 0xc18e, 0x21, 0 + .dw 0x2b40, 0xc18e, 0x2b7f, 0xc18e, 0x21, 0 + .dw 0x2bc0, 0xc18e, 0x2bff, 0xc18e, 0x21, 0 + .dw 0x2c40, 0xc18e, 0x2c7f, 0xc18e, 0x21, 0 + .dw 0x2cc0, 0xc18e, 0x2cff, 0xc18e, 0x21, 0 + .dw 0x2d40, 0xc18e, 0x2d7f, 0xc18e, 0x21, 0 + .dw 0x2dc0, 0xc18e, 0x2dff, 0xc18e, 0x21, 0 + .dw 0x2e40, 0xc18e, 0x2e7f, 0xc18e, 0x21, 0 + .dw 0x2ec0, 0xc18e, 0x2eff, 0xc18e, 0x21, 0 + .dw 0x2f40, 0xc18e, 0x2f7f, 0xc18e, 0x21, 0 + .dw 0x2fc0, 0xc18e, 0x2fff, 0xc18e, 0x21, 0 + .dw 0x3040, 0xc18e, 0x307f, 0xc18e, 0x21, 0 + .dw 0x30c0, 0xc18e, 0x30ff, 0xc18e, 0x21, 0 + .dw 0x3140, 0xc18e, 0x317f, 0xc18e, 0x21, 0 + .dw 0x31c0, 0xc18e, 0x31ff, 0xc18e, 0x21, 0 + .dw 0x3240, 0xc18e, 0x327f, 0xc18e, 0x21, 0 + .dw 0x32c0, 0xc18e, 0x32ff, 0xc18e, 0x21, 0 + .dw 0x3340, 0xc18e, 0x337f, 0xc18e, 0x21, 0 + .dw 0x33c0, 0xc18e, 0x33ff, 0xc18e, 0x21, 0 + .dw 0x3440, 0xc18e, 0x347f, 0xc18e, 0x21, 0 + .dw 0x34c0, 0xc18e, 0x34ff, 0xc18e, 0x21, 0 + .dw 0x3540, 0xc18e, 0x357f, 0xc18e, 0x21, 0 + .dw 0x35c0, 0xc18e, 0x35ff, 0xc18e, 0x21, 0 + .dw 0x3640, 0xc18e, 0x367f, 0xc18e, 0x21, 0 + .dw 0x36c0, 0xc18e, 0x36ff, 0xc18e, 0x21, 0 + .dw 0x3740, 0xc18e, 0x377f, 0xc18e, 0x21, 0 + .dw 0x37c0, 0xc18e, 0x37ff, 0xc18e, 0x21, 0 + .dw 0x3840, 0xc18e, 0x387f, 0xc18e, 0x21, 0 + .dw 0x38c0, 0xc18e, 0x38ff, 0xc18e, 0x21, 0 + .dw 0x3940, 0xc18e, 0x397f, 0xc18e, 0x21, 0 + .dw 0x39c0, 0xc18e, 0x3fff, 0xc18e, 0x21, 0 + .dw 0x4040, 0xc18e, 0x407f, 0xc18e, 0x21, 0 + .dw 0x40c0, 0xc18e, 0x40ff, 0xc18e, 0x21, 0 + .dw 0x4140, 0xc18e, 0x417f, 0xc18e, 0x21, 0 + .dw 0x41c0, 0xc18e, 0x41ff, 0xc18e, 0x21, 0 + .dw 0x4240, 0xc18e, 0x427f, 0xc18e, 0x21, 0 + .dw 0x42c0, 0xc18e, 0x42ff, 0xc18e, 0x21, 0 + .dw 0x4340, 0xc18e, 0x437f, 0xc18e, 0x21, 0 + .dw 0x43c0, 0xc18e, 0x43ff, 0xc18e, 0x21, 0 + .dw 0x4440, 0xc18e, 0x447f, 0xc18e, 0x21, 0 + .dw 0x44c0, 0xc18e, 0x44ff, 0xc18e, 0x21, 0 + .dw 0x4540, 0xc18e, 0x457f, 0xc18e, 0x21, 0 + .dw 0x45c0, 0xc18e, 0x45ff, 0xc18e, 0x21, 0 + .dw 0x4640, 0xc18e, 0x467f, 0xc18e, 0x21, 0 + .dw 0x46c0, 0xc18e, 0x46ff, 0xc18e, 0x21, 0 + .dw 0x4740, 0xc18e, 0x477f, 0xc18e, 0x21, 0 + .dw 0x47c0, 0xc18e, 0x47ff, 0xc18e, 0x21, 0 + .dw 0x4840, 0xc18e, 0x487f, 0xc18e, 0x21, 0 + .dw 0x48c0, 0xc18e, 0x48ff, 0xc18e, 0x21, 0 + .dw 0x4940, 0xc18e, 0x497f, 0xc18e, 0x21, 0 + .dw 0x49c0, 0xc18e, 0x49ff, 0xc18e, 0x21, 0 + .dw 0x4a40, 0xc18e, 0x4a7f, 0xc18e, 0x21, 0 + .dw 0x4ac0, 0xc18e, 0x4aff, 0xc18e, 0x21, 0 + .dw 0x4b40, 0xc18e, 0x4b7f, 0xc18e, 0x21, 0 + .dw 0x4bc0, 0xc18e, 0x4bff, 0xc18e, 0x21, 0 + .dw 0x4c40, 0xc18e, 0x4c7f, 0xc18e, 0x21, 0 + .dw 0x4cc0, 0xc18e, 0x4cff, 0xc18e, 0x21, 0 + .dw 0x4d40, 0xc18e, 0x4d7f, 0xc18e, 0x21, 0 + .dw 0x4dc0, 0xc18e, 0x4dff, 0xc18e, 0x21, 0 + .dw 0x4e40, 0xc18e, 0x4e7f, 0xc18e, 0x21, 0 + .dw 0x4ec0, 0xc18e, 0x4eff, 0xc18e, 0x21, 0 + .dw 0x4f40, 0xc18e, 0x4f7f, 0xc18e, 0x21, 0 + .dw 0x4fc0, 0xc18e, 0x4fff, 0xc18e, 0x21, 0 + .dw 0x5040, 0xc18e, 0x507f, 0xc18e, 0x21, 0 + .dw 0x50c0, 0xc18e, 0x50ff, 0xc18e, 0x21, 0 + .dw 0x5140, 0xc18e, 0x517f, 0xc18e, 0x21, 0 + .dw 0x51c0, 0xc18e, 0x51ff, 0xc18e, 0x21, 0 + .dw 0x5240, 0xc18e, 0x527f, 0xc18e, 0x21, 0 + .dw 0x52c0, 0xc18e, 0x52ff, 0xc18e, 0x21, 0 + .dw 0x5340, 0xc18e, 0x537f, 0xc18e, 0x21, 0 + .dw 0x53c0, 0xc18e, 0x53ff, 0xc18e, 0x21, 0 + .dw 0x5440, 0xc18e, 0x547f, 0xc18e, 0x21, 0 + .dw 0x54c0, 0xc18e, 0x54ff, 0xc18e, 0x21, 0 + .dw 0x5540, 0xc18e, 0x557f, 0xc18e, 0x21, 0 + .dw 0x55c0, 0xc18e, 0x55ff, 0xc18e, 0x21, 0 + .dw 0x5640, 0xc18e, 0x567f, 0xc18e, 0x21, 0 + .dw 0x56c0, 0xc18e, 0x56ff, 0xc18e, 0x21, 0 + .dw 0x5740, 0xc18e, 0x577f, 0xc18e, 0x21, 0 + .dw 0x57c0, 0xc18e, 0x57ff, 0xc18e, 0x21, 0 + .dw 0x5840, 0xc18e, 0x587f, 0xc18e, 0x21, 0 + .dw 0x58c0, 0xc18e, 0x58ff, 0xc18e, 0x21, 0 + .dw 0x5940, 0xc18e, 0x597f, 0xc18e, 0x21, 0 + .dw 0x59c0, 0xc18e, 0x5fff, 0xc18e, 0x21, 0 + .dw 0x6040, 0xc18e, 0x607f, 0xc18e, 0x21, 0 + .dw 0x60c0, 0xc18e, 0x60ff, 0xc18e, 0x21, 0 + .dw 0x6140, 0xc18e, 0x617f, 0xc18e, 0x21, 0 + .dw 0x61c0, 0xc18e, 0x61ff, 0xc18e, 0x21, 0 + .dw 0x6240, 0xc18e, 0x627f, 0xc18e, 0x21, 0 + .dw 0x62c0, 0xc18e, 0x62ff, 0xc18e, 0x21, 0 + .dw 0x6340, 0xc18e, 0x637f, 0xc18e, 0x21, 0 + .dw 0x63c0, 0xc18e, 0x63ff, 0xc18e, 0x21, 0 + .dw 0x6440, 0xc18e, 0x647f, 0xc18e, 0x21, 0 + .dw 0x64c0, 0xc18e, 0x64ff, 0xc18e, 0x21, 0 + .dw 0x6540, 0xc18e, 0x657f, 0xc18e, 0x21, 0 + .dw 0x65c0, 0xc18e, 0x65ff, 0xc18e, 0x21, 0 + .dw 0x6640, 0xc18e, 0x667f, 0xc18e, 0x21, 0 + .dw 0x66c0, 0xc18e, 0x66ff, 0xc18e, 0x21, 0 + .dw 0x6740, 0xc18e, 0x677f, 0xc18e, 0x21, 0 + .dw 0x67c0, 0xc18e, 0x67ff, 0xc18e, 0x21, 0 + .dw 0x6840, 0xc18e, 0x687f, 0xc18e, 0x21, 0 + .dw 0x68c0, 0xc18e, 0x68ff, 0xc18e, 0x21, 0 + .dw 0x6940, 0xc18e, 0x697f, 0xc18e, 0x21, 0 + .dw 0x69c0, 0xc18e, 0x69ff, 0xc18e, 0x21, 0 + .dw 0x6a40, 0xc18e, 0x6a7f, 0xc18e, 0x21, 0 + .dw 0x6ac0, 0xc18e, 0x6aff, 0xc18e, 0x21, 0 + .dw 0x6b40, 0xc18e, 0x6b7f, 0xc18e, 0x21, 0 + .dw 0x6bc0, 0xc18e, 0x6bff, 0xc18e, 0x21, 0 + .dw 0x6c40, 0xc18e, 0x6c7f, 0xc18e, 0x21, 0 + .dw 0x6cc0, 0xc18e, 0x6cff, 0xc18e, 0x21, 0 + .dw 0x6d40, 0xc18e, 0x6d7f, 0xc18e, 0x21, 0 + .dw 0x6dc0, 0xc18e, 0x6dff, 0xc18e, 0x21, 0 + .dw 0x6e40, 0xc18e, 0x6e7f, 0xc18e, 0x21, 0 + .dw 0x6ec0, 0xc18e, 0x6eff, 0xc18e, 0x21, 0 + .dw 0x6f40, 0xc18e, 0x6f7f, 0xc18e, 0x21, 0 + .dw 0x6fc0, 0xc18e, 0x6fff, 0xc18e, 0x21, 0 + .dw 0x7040, 0xc18e, 0x707f, 0xc18e, 0x21, 0 + .dw 0x70c0, 0xc18e, 0x70ff, 0xc18e, 0x21, 0 + .dw 0x7140, 0xc18e, 0x717f, 0xc18e, 0x21, 0 + .dw 0x71c0, 0xc18e, 0x71ff, 0xc18e, 0x21, 0 + .dw 0x7240, 0xc18e, 0x727f, 0xc18e, 0x21, 0 + .dw 0x72c0, 0xc18e, 0x72ff, 0xc18e, 0x21, 0 + .dw 0x7340, 0xc18e, 0x737f, 0xc18e, 0x21, 0 + .dw 0x73c0, 0xc18e, 0x73ff, 0xc18e, 0x21, 0 + .dw 0x7440, 0xc18e, 0x747f, 0xc18e, 0x21, 0 + .dw 0x74c0, 0xc18e, 0x74ff, 0xc18e, 0x21, 0 + .dw 0x7540, 0xc18e, 0x757f, 0xc18e, 0x21, 0 + .dw 0x75c0, 0xc18e, 0x75ff, 0xc18e, 0x21, 0 + .dw 0x7640, 0xc18e, 0x767f, 0xc18e, 0x21, 0 + .dw 0x76c0, 0xc18e, 0x76ff, 0xc18e, 0x21, 0 + .dw 0x7740, 0xc18e, 0x777f, 0xc18e, 0x21, 0 + .dw 0x77c0, 0xc18e, 0x77ff, 0xc18e, 0x21, 0 + .dw 0x7840, 0xc18e, 0x787f, 0xc18e, 0x21, 0 + .dw 0x78c0, 0xc18e, 0x78ff, 0xc18e, 0x21, 0 + .dw 0x7940, 0xc18e, 0x797f, 0xc18e, 0x21, 0 + .dw 0x79c0, 0xc18e, 0x7fff, 0xc18e, 0x21, 0 + .dw 0x8040, 0xc18e, 0x807f, 0xc18e, 0x21, 0 + .dw 0x80c0, 0xc18e, 0x80ff, 0xc18e, 0x21, 0 + .dw 0x8140, 0xc18e, 0x817f, 0xc18e, 0x21, 0 + .dw 0x81c0, 0xc18e, 0x81ff, 0xc18e, 0x21, 0 + .dw 0x8240, 0xc18e, 0x827f, 0xc18e, 0x21, 0 + .dw 0x82c0, 0xc18e, 0x82ff, 0xc18e, 0x21, 0 + .dw 0x8340, 0xc18e, 0x837f, 0xc18e, 0x21, 0 + .dw 0x83c0, 0xc18e, 0x83ff, 0xc18e, 0x21, 0 + .dw 0x8440, 0xc18e, 0x847f, 0xc18e, 0x21, 0 + .dw 0x84c0, 0xc18e, 0x84ff, 0xc18e, 0x21, 0 + .dw 0x8540, 0xc18e, 0x857f, 0xc18e, 0x21, 0 + .dw 0x85c0, 0xc18e, 0x85ff, 0xc18e, 0x21, 0 + .dw 0x8640, 0xc18e, 0x867f, 0xc18e, 0x21, 0 + .dw 0x86c0, 0xc18e, 0x86ff, 0xc18e, 0x21, 0 + .dw 0x8740, 0xc18e, 0x877f, 0xc18e, 0x21, 0 + .dw 0x87c0, 0xc18e, 0x87ff, 0xc18e, 0x21, 0 + .dw 0x8840, 0xc18e, 0x887f, 0xc18e, 0x21, 0 + .dw 0x88c0, 0xc18e, 0x88ff, 0xc18e, 0x21, 0 + .dw 0x8940, 0xc18e, 0x897f, 0xc18e, 0x21, 0 + .dw 0x89c0, 0xc18e, 0x89ff, 0xc18e, 0x21, 0 + .dw 0x8a40, 0xc18e, 0x8a7f, 0xc18e, 0x21, 0 + .dw 0x8ac0, 0xc18e, 0x8aff, 0xc18e, 0x21, 0 + .dw 0x8b40, 0xc18e, 0x8b7f, 0xc18e, 0x21, 0 + .dw 0x8bc0, 0xc18e, 0x8bff, 0xc18e, 0x21, 0 + .dw 0x8c40, 0xc18e, 0x8c7f, 0xc18e, 0x21, 0 + .dw 0x8cc0, 0xc18e, 0x8cff, 0xc18e, 0x21, 0 + .dw 0x8d40, 0xc18e, 0x8d7f, 0xc18e, 0x21, 0 + .dw 0x8dc0, 0xc18e, 0x8dff, 0xc18e, 0x21, 0 + .dw 0x8e40, 0xc18e, 0x8e7f, 0xc18e, 0x21, 0 + .dw 0x8ec0, 0xc18e, 0x8eff, 0xc18e, 0x21, 0 + .dw 0x8f40, 0xc18e, 0x8f7f, 0xc18e, 0x21, 0 + .dw 0x8fc0, 0xc18e, 0x8fff, 0xc18e, 0x21, 0 + .dw 0x9040, 0xc18e, 0x907f, 0xc18e, 0x21, 0 + .dw 0x90c0, 0xc18e, 0x90ff, 0xc18e, 0x21, 0 + .dw 0x9140, 0xc18e, 0x917f, 0xc18e, 0x21, 0 + .dw 0x91c0, 0xc18e, 0x91ff, 0xc18e, 0x21, 0 + .dw 0x9240, 0xc18e, 0x927f, 0xc18e, 0x21, 0 + .dw 0x92c0, 0xc18e, 0x92ff, 0xc18e, 0x21, 0 + .dw 0x9340, 0xc18e, 0x937f, 0xc18e, 0x21, 0 + .dw 0x93c0, 0xc18e, 0x93ff, 0xc18e, 0x21, 0 + .dw 0x9440, 0xc18e, 0x947f, 0xc18e, 0x21, 0 + .dw 0x94c0, 0xc18e, 0x94ff, 0xc18e, 0x21, 0 + .dw 0x9540, 0xc18e, 0x957f, 0xc18e, 0x21, 0 + .dw 0x95c0, 0xc18e, 0x95ff, 0xc18e, 0x21, 0 + .dw 0x9640, 0xc18e, 0x967f, 0xc18e, 0x21, 0 + .dw 0x96c0, 0xc18e, 0x96ff, 0xc18e, 0x21, 0 + .dw 0x9740, 0xc18e, 0x977f, 0xc18e, 0x21, 0 + .dw 0x97c0, 0xc18e, 0x97ff, 0xc18e, 0x21, 0 + .dw 0x9840, 0xc18e, 0x987f, 0xc18e, 0x21, 0 + .dw 0x98c0, 0xc18e, 0x98ff, 0xc18e, 0x21, 0 + .dw 0x9940, 0xc18e, 0x997f, 0xc18e, 0x21, 0 + .dw 0x99c0, 0xc18e, 0x9fff, 0xc18e, 0x21, 0 + .dw 0xa040, 0xc18e, 0xa07f, 0xc18e, 0x21, 0 + .dw 0xa0c0, 0xc18e, 0xa0ff, 0xc18e, 0x21, 0 + .dw 0xa140, 0xc18e, 0xa17f, 0xc18e, 0x21, 0 + .dw 0xa1c0, 0xc18e, 0xa1ff, 0xc18e, 0x21, 0 + .dw 0xa240, 0xc18e, 0xa27f, 0xc18e, 0x21, 0 + .dw 0xa2c0, 0xc18e, 0xa2ff, 0xc18e, 0x21, 0 + .dw 0xa340, 0xc18e, 0xa37f, 0xc18e, 0x21, 0 + .dw 0xa3c0, 0xc18e, 0xa3ff, 0xc18e, 0x21, 0 + .dw 0xa440, 0xc18e, 0xa47f, 0xc18e, 0x21, 0 + .dw 0xa4c0, 0xc18e, 0xa4ff, 0xc18e, 0x21, 0 + .dw 0xa540, 0xc18e, 0xa57f, 0xc18e, 0x21, 0 + .dw 0xa5c0, 0xc18e, 0xa5ff, 0xc18e, 0x21, 0 + .dw 0xa640, 0xc18e, 0xa67f, 0xc18e, 0x21, 0 + .dw 0xa6c0, 0xc18e, 0xa6ff, 0xc18e, 0x21, 0 + .dw 0xa740, 0xc18e, 0xa77f, 0xc18e, 0x21, 0 + .dw 0xa7c0, 0xc18e, 0xa7ff, 0xc18e, 0x21, 0 + .dw 0xa840, 0xc18e, 0xa87f, 0xc18e, 0x21, 0 + .dw 0xa8c0, 0xc18e, 0xa8ff, 0xc18e, 0x21, 0 + .dw 0xa940, 0xc18e, 0xa97f, 0xc18e, 0x21, 0 + .dw 0xa9c0, 0xc18e, 0xa9ff, 0xc18e, 0x21, 0 + .dw 0xaa40, 0xc18e, 0xaa7f, 0xc18e, 0x21, 0 + .dw 0xaac0, 0xc18e, 0xaaff, 0xc18e, 0x21, 0 + .dw 0xab40, 0xc18e, 0xab7f, 0xc18e, 0x21, 0 + .dw 0xabc0, 0xc18e, 0xabff, 0xc18e, 0x21, 0 + .dw 0xac40, 0xc18e, 0xac7f, 0xc18e, 0x21, 0 + .dw 0xacc0, 0xc18e, 0xacff, 0xc18e, 0x21, 0 + .dw 0xad40, 0xc18e, 0xad7f, 0xc18e, 0x21, 0 + .dw 0xadc0, 0xc18e, 0xadff, 0xc18e, 0x21, 0 + .dw 0xae40, 0xc18e, 0xae7f, 0xc18e, 0x21, 0 + .dw 0xaec0, 0xc18e, 0xaeff, 0xc18e, 0x21, 0 + .dw 0xaf40, 0xc18e, 0xaf7f, 0xc18e, 0x21, 0 + .dw 0xafc0, 0xc18e, 0xafff, 0xc18e, 0x21, 0 + .dw 0xb040, 0xc18e, 0xb07f, 0xc18e, 0x21, 0 + .dw 0xb0c0, 0xc18e, 0xb0ff, 0xc18e, 0x21, 0 + .dw 0xb140, 0xc18e, 0xb17f, 0xc18e, 0x21, 0 + .dw 0xb1c0, 0xc18e, 0xb1ff, 0xc18e, 0x21, 0 + .dw 0xb240, 0xc18e, 0xb27f, 0xc18e, 0x21, 0 + .dw 0xb2c0, 0xc18e, 0xb2ff, 0xc18e, 0x21, 0 + .dw 0xb340, 0xc18e, 0xb37f, 0xc18e, 0x21, 0 + .dw 0xb3c0, 0xc18e, 0xb3ff, 0xc18e, 0x21, 0 + .dw 0xb440, 0xc18e, 0xb47f, 0xc18e, 0x21, 0 + .dw 0xb4c0, 0xc18e, 0xb4ff, 0xc18e, 0x21, 0 + .dw 0xb540, 0xc18e, 0xb57f, 0xc18e, 0x21, 0 + .dw 0xb5c0, 0xc18e, 0xb5ff, 0xc18e, 0x21, 0 + .dw 0xb640, 0xc18e, 0xb67f, 0xc18e, 0x21, 0 + .dw 0xb6c0, 0xc18e, 0xb6ff, 0xc18e, 0x21, 0 + .dw 0xb740, 0xc18e, 0xb77f, 0xc18e, 0x21, 0 + .dw 0xb7c0, 0xc18e, 0xb7ff, 0xc18e, 0x21, 0 + .dw 0xb840, 0xc18e, 0xb87f, 0xc18e, 0x21, 0 + .dw 0xb8c0, 0xc18e, 0xb8ff, 0xc18e, 0x21, 0 + .dw 0xb940, 0xc18e, 0xb97f, 0xc18e, 0x21, 0 + .dw 0xb9c0, 0xc18e, 0xbfff, 0xc18e, 0x21, 0 + .dw 0xc040, 0xc18e, 0xc07f, 0xc18e, 0x21, 0 + .dw 0xc0c0, 0xc18e, 0xc0ff, 0xc18e, 0x21, 0 + .dw 0xc140, 0xc18e, 0xc17f, 0xc18e, 0x21, 0 + .dw 0xc1c0, 0xc18e, 0xc1ff, 0xc18e, 0x21, 0 + .dw 0xc240, 0xc18e, 0xc27f, 0xc18e, 0x21, 0 + .dw 0xc2c0, 0xc18e, 0xc2ff, 0xc18e, 0x21, 0 + .dw 0xc340, 0xc18e, 0xc37f, 0xc18e, 0x21, 0 + .dw 0xc3c0, 0xc18e, 0xc3ff, 0xc18e, 0x21, 0 + .dw 0xc440, 0xc18e, 0xc47f, 0xc18e, 0x21, 0 + .dw 0xc4c0, 0xc18e, 0xc4ff, 0xc18e, 0x21, 0 + .dw 0xc540, 0xc18e, 0xc57f, 0xc18e, 0x21, 0 + .dw 0xc5c0, 0xc18e, 0xc5ff, 0xc18e, 0x21, 0 + .dw 0xc640, 0xc18e, 0xc67f, 0xc18e, 0x21, 0 + .dw 0xc6c0, 0xc18e, 0xc6ff, 0xc18e, 0x21, 0 + .dw 0xc740, 0xc18e, 0xc77f, 0xc18e, 0x21, 0 + .dw 0xc7c0, 0xc18e, 0xc7ff, 0xc18e, 0x21, 0 + .dw 0xc840, 0xc18e, 0xc87f, 0xc18e, 0x21, 0 + .dw 0xc8c0, 0xc18e, 0xc8ff, 0xc18e, 0x21, 0 + .dw 0xc940, 0xc18e, 0xc97f, 0xc18e, 0x21, 0 + .dw 0xc9c0, 0xc18e, 0xc9ff, 0xc18e, 0x21, 0 + .dw 0xca40, 0xc18e, 0xca7f, 0xc18e, 0x21, 0 + .dw 0xcac0, 0xc18e, 0xcaff, 0xc18e, 0x21, 0 + .dw 0xcb40, 0xc18e, 0xcb7f, 0xc18e, 0x21, 0 + .dw 0xcbc0, 0xc18e, 0xcbff, 0xc18e, 0x21, 0 + .dw 0xcc40, 0xc18e, 0xcc7f, 0xc18e, 0x21, 0 + .dw 0xccc0, 0xc18e, 0xccff, 0xc18e, 0x21, 0 + .dw 0xcd40, 0xc18e, 0xcd7f, 0xc18e, 0x21, 0 + .dw 0xcdc0, 0xc18e, 0xcdff, 0xc18e, 0x21, 0 + .dw 0xce40, 0xc18e, 0xce7f, 0xc18e, 0x21, 0 + .dw 0xcec0, 0xc18e, 0xceff, 0xc18e, 0x21, 0 + .dw 0xcf40, 0xc18e, 0xcf7f, 0xc18e, 0x21, 0 + .dw 0xcfc0, 0xc18e, 0xcfff, 0xc18e, 0x21, 0 + .dw 0xd040, 0xc18e, 0xd07f, 0xc18e, 0x21, 0 + .dw 0xd0c0, 0xc18e, 0xd0ff, 0xc18e, 0x21, 0 + .dw 0xd140, 0xc18e, 0xd17f, 0xc18e, 0x21, 0 + .dw 0xd1c0, 0xc18e, 0xd1ff, 0xc18e, 0x21, 0 + .dw 0xd240, 0xc18e, 0xd27f, 0xc18e, 0x21, 0 + .dw 0xd2c0, 0xc18e, 0xd2ff, 0xc18e, 0x21, 0 + .dw 0xd340, 0xc18e, 0xd37f, 0xc18e, 0x21, 0 + .dw 0xd3c0, 0xc18e, 0xd3ff, 0xc18e, 0x21, 0 + .dw 0xd440, 0xc18e, 0xd47f, 0xc18e, 0x21, 0 + .dw 0xd4c0, 0xc18e, 0xd4ff, 0xc18e, 0x21, 0 + .dw 0xd540, 0xc18e, 0xd57f, 0xc18e, 0x21, 0 + .dw 0xd5c0, 0xc18e, 0xd5ff, 0xc18e, 0x21, 0 + .dw 0xd640, 0xc18e, 0xd67f, 0xc18e, 0x21, 0 + .dw 0xd6c0, 0xc18e, 0xd6ff, 0xc18e, 0x21, 0 + .dw 0xd740, 0xc18e, 0xd77f, 0xc18e, 0x21, 0 + .dw 0xd7c0, 0xc18e, 0xd7ff, 0xc18e, 0x21, 0 + .dw 0xd840, 0xc18e, 0xd87f, 0xc18e, 0x21, 0 + .dw 0xd8c0, 0xc18e, 0xd8ff, 0xc18e, 0x21, 0 + .dw 0xd940, 0xc18e, 0xd97f, 0xc18e, 0x21, 0 + .dw 0xd9c0, 0xc18e, 0xdfff, 0xc18e, 0x21, 0 + .dw 0xe040, 0xc18e, 0xe07f, 0xc18e, 0x21, 0 + .dw 0xe0c0, 0xc18e, 0xe0ff, 0xc18e, 0x21, 0 + .dw 0xe140, 0xc18e, 0xe17f, 0xc18e, 0x21, 0 + .dw 0xe1c0, 0xc18e, 0xe1ff, 0xc18e, 0x21, 0 + .dw 0xe240, 0xc18e, 0xe27f, 0xc18e, 0x21, 0 + .dw 0xe2c0, 0xc18e, 0xe2ff, 0xc18e, 0x21, 0 + .dw 0xe340, 0xc18e, 0xe37f, 0xc18e, 0x21, 0 + .dw 0xe3c0, 0xc18e, 0xe3ff, 0xc18e, 0x21, 0 + .dw 0xe440, 0xc18e, 0xe47f, 0xc18e, 0x21, 0 + .dw 0xe4c0, 0xc18e, 0xe4ff, 0xc18e, 0x21, 0 + .dw 0xe540, 0xc18e, 0xe57f, 0xc18e, 0x21, 0 + .dw 0xe5c0, 0xc18e, 0xe5ff, 0xc18e, 0x21, 0 + .dw 0xe640, 0xc18e, 0xe67f, 0xc18e, 0x21, 0 + .dw 0xe6c0, 0xc18e, 0xe6ff, 0xc18e, 0x21, 0 + .dw 0xe740, 0xc18e, 0xe77f, 0xc18e, 0x21, 0 + .dw 0xe7c0, 0xc18e, 0xe7ff, 0xc18e, 0x21, 0 + .dw 0xe840, 0xc18e, 0xe87f, 0xc18e, 0x21, 0 + .dw 0xe8c0, 0xc18e, 0xe8ff, 0xc18e, 0x21, 0 + .dw 0xe940, 0xc18e, 0xe97f, 0xc18e, 0x21, 0 + .dw 0xe9c0, 0xc18e, 0xe9ff, 0xc18e, 0x21, 0 + .dw 0xea40, 0xc18e, 0xea7f, 0xc18e, 0x21, 0 + .dw 0xeac0, 0xc18e, 0xeaff, 0xc18e, 0x21, 0 + .dw 0xeb40, 0xc18e, 0xeb7f, 0xc18e, 0x21, 0 + .dw 0xebc0, 0xc18e, 0xebff, 0xc18e, 0x21, 0 + .dw 0xec40, 0xc18e, 0xec7f, 0xc18e, 0x21, 0 + .dw 0xecc0, 0xc18e, 0xecff, 0xc18e, 0x21, 0 + .dw 0xed40, 0xc18e, 0xed7f, 0xc18e, 0x21, 0 + .dw 0xedc0, 0xc18e, 0xedff, 0xc18e, 0x21, 0 + .dw 0xee40, 0xc18e, 0xee7f, 0xc18e, 0x21, 0 + .dw 0xeec0, 0xc18e, 0xeeff, 0xc18e, 0x21, 0 + .dw 0xef40, 0xc18e, 0xef7f, 0xc18e, 0x21, 0 + .dw 0xefc0, 0xc18e, 0xefff, 0xc18e, 0x21, 0 + .dw 0xf040, 0xc18e, 0xf07f, 0xc18e, 0x21, 0 + .dw 0xf0c0, 0xc18e, 0xf0ff, 0xc18e, 0x21, 0 + .dw 0xf140, 0xc18e, 0xf17f, 0xc18e, 0x21, 0 + .dw 0xf1c0, 0xc18e, 0xf1ff, 0xc18e, 0x21, 0 + .dw 0xf240, 0xc18e, 0xf27f, 0xc18e, 0x21, 0 + .dw 0xf2c0, 0xc18e, 0xf2ff, 0xc18e, 0x21, 0 + .dw 0xf340, 0xc18e, 0xf37f, 0xc18e, 0x21, 0 + .dw 0xf3c0, 0xc18e, 0xf3ff, 0xc18e, 0x21, 0 + .dw 0xf440, 0xc18e, 0xf47f, 0xc18e, 0x21, 0 + .dw 0xf4c0, 0xc18e, 0xf4ff, 0xc18e, 0x21, 0 + .dw 0xf540, 0xc18e, 0xf57f, 0xc18e, 0x21, 0 + .dw 0xf5c0, 0xc18e, 0xf5ff, 0xc18e, 0x21, 0 + .dw 0xf640, 0xc18e, 0xf67f, 0xc18e, 0x21, 0 + .dw 0xf6c0, 0xc18e, 0xf6ff, 0xc18e, 0x21, 0 + .dw 0xf740, 0xc18e, 0xf77f, 0xc18e, 0x21, 0 + .dw 0xf7c0, 0xc18e, 0xf7ff, 0xc18e, 0x21, 0 + .dw 0xf840, 0xc18e, 0xf87f, 0xc18e, 0x21, 0 + .dw 0xf8c0, 0xc18e, 0xf8ff, 0xc18e, 0x21, 0 + .dw 0xf940, 0xc18e, 0xf97f, 0xc18e, 0x21, 0 + .dw 0xf9c0, 0xc18e, 0xffff, 0xc18e, 0x21, 0 + .dw 0x0040, 0xc18f, 0x007f, 0xc18f, 0x21, 0 + .dw 0x00c0, 0xc18f, 0x00ff, 0xc18f, 0x21, 0 + .dw 0x0140, 0xc18f, 0x017f, 0xc18f, 0x21, 0 + .dw 0x01c0, 0xc18f, 0x01ff, 0xc18f, 0x21, 0 + .dw 0x0240, 0xc18f, 0x027f, 0xc18f, 0x21, 0 + .dw 0x02c0, 0xc18f, 0x02ff, 0xc18f, 0x21, 0 + .dw 0x0340, 0xc18f, 0x037f, 0xc18f, 0x21, 0 + .dw 0x03c0, 0xc18f, 0x03ff, 0xc18f, 0x21, 0 + .dw 0x0440, 0xc18f, 0x047f, 0xc18f, 0x21, 0 + .dw 0x04c0, 0xc18f, 0x04ff, 0xc18f, 0x21, 0 + .dw 0x0540, 0xc18f, 0x057f, 0xc18f, 0x21, 0 + .dw 0x05c0, 0xc18f, 0x05ff, 0xc18f, 0x21, 0 + .dw 0x0640, 0xc18f, 0x067f, 0xc18f, 0x21, 0 + .dw 0x06c0, 0xc18f, 0x06ff, 0xc18f, 0x21, 0 + .dw 0x0740, 0xc18f, 0x077f, 0xc18f, 0x21, 0 + .dw 0x07c0, 0xc18f, 0x07ff, 0xc18f, 0x21, 0 + .dw 0x0840, 0xc18f, 0x087f, 0xc18f, 0x21, 0 + .dw 0x08c0, 0xc18f, 0x08ff, 0xc18f, 0x21, 0 + .dw 0x0940, 0xc18f, 0x097f, 0xc18f, 0x21, 0 + .dw 0x09c0, 0xc18f, 0x09ff, 0xc18f, 0x21, 0 + .dw 0x0a40, 0xc18f, 0x0a7f, 0xc18f, 0x21, 0 + .dw 0x0ac0, 0xc18f, 0x0aff, 0xc18f, 0x21, 0 + .dw 0x0b40, 0xc18f, 0x0b7f, 0xc18f, 0x21, 0 + .dw 0x0bc0, 0xc18f, 0x0bff, 0xc18f, 0x21, 0 + .dw 0x0c40, 0xc18f, 0x0c7f, 0xc18f, 0x21, 0 + .dw 0x0cc0, 0xc18f, 0x0cff, 0xc18f, 0x21, 0 + .dw 0x0d40, 0xc18f, 0x0d7f, 0xc18f, 0x21, 0 + .dw 0x0dc0, 0xc18f, 0x0dff, 0xc18f, 0x21, 0 + .dw 0x0e40, 0xc18f, 0x0e7f, 0xc18f, 0x21, 0 + .dw 0x0ec0, 0xc18f, 0x0eff, 0xc18f, 0x21, 0 + .dw 0x0f40, 0xc18f, 0x0f7f, 0xc18f, 0x21, 0 + .dw 0x0fc0, 0xc18f, 0x0fff, 0xc18f, 0x21, 0 + .dw 0x1040, 0xc18f, 0x107f, 0xc18f, 0x21, 0 + .dw 0x10c0, 0xc18f, 0x10ff, 0xc18f, 0x21, 0 + .dw 0x1140, 0xc18f, 0x117f, 0xc18f, 0x21, 0 + .dw 0x11c0, 0xc18f, 0x11ff, 0xc18f, 0x21, 0 + .dw 0x1240, 0xc18f, 0x127f, 0xc18f, 0x21, 0 + .dw 0x12c0, 0xc18f, 0x12ff, 0xc18f, 0x21, 0 + .dw 0x1340, 0xc18f, 0x137f, 0xc18f, 0x21, 0 + .dw 0x13c0, 0xc18f, 0x13ff, 0xc18f, 0x21, 0 + .dw 0x1440, 0xc18f, 0x147f, 0xc18f, 0x21, 0 + .dw 0x14c0, 0xc18f, 0x14ff, 0xc18f, 0x21, 0 + .dw 0x1540, 0xc18f, 0x157f, 0xc18f, 0x21, 0 + .dw 0x15c0, 0xc18f, 0x15ff, 0xc18f, 0x21, 0 + .dw 0x1640, 0xc18f, 0x167f, 0xc18f, 0x21, 0 + .dw 0x16c0, 0xc18f, 0x16ff, 0xc18f, 0x21, 0 + .dw 0x1740, 0xc18f, 0x177f, 0xc18f, 0x21, 0 + .dw 0x17c0, 0xc18f, 0x17ff, 0xc18f, 0x21, 0 + .dw 0x1840, 0xc18f, 0x187f, 0xc18f, 0x21, 0 + .dw 0x18c0, 0xc18f, 0x18ff, 0xc18f, 0x21, 0 + .dw 0x1940, 0xc18f, 0x197f, 0xc18f, 0x21, 0 + .dw 0x19c0, 0xc18f, 0x1fff, 0xc18f, 0x21, 0 + .dw 0x2040, 0xc18f, 0x207f, 0xc18f, 0x21, 0 + .dw 0x20c0, 0xc18f, 0x20ff, 0xc18f, 0x21, 0 + .dw 0x2140, 0xc18f, 0x217f, 0xc18f, 0x21, 0 + .dw 0x21c0, 0xc18f, 0x21ff, 0xc18f, 0x21, 0 + .dw 0x2240, 0xc18f, 0x227f, 0xc18f, 0x21, 0 + .dw 0x22c0, 0xc18f, 0x22ff, 0xc18f, 0x21, 0 + .dw 0x2340, 0xc18f, 0x237f, 0xc18f, 0x21, 0 + .dw 0x23c0, 0xc18f, 0x23ff, 0xc18f, 0x21, 0 + .dw 0x2440, 0xc18f, 0x247f, 0xc18f, 0x21, 0 + .dw 0x24c0, 0xc18f, 0x24ff, 0xc18f, 0x21, 0 + .dw 0x2540, 0xc18f, 0x257f, 0xc18f, 0x21, 0 + .dw 0x25c0, 0xc18f, 0x25ff, 0xc18f, 0x21, 0 + .dw 0x2640, 0xc18f, 0x267f, 0xc18f, 0x21, 0 + .dw 0x26c0, 0xc18f, 0x26ff, 0xc18f, 0x21, 0 + .dw 0x2740, 0xc18f, 0x277f, 0xc18f, 0x21, 0 + .dw 0x27c0, 0xc18f, 0x27ff, 0xc18f, 0x21, 0 + .dw 0x2840, 0xc18f, 0x287f, 0xc18f, 0x21, 0 + .dw 0x28c0, 0xc18f, 0x28ff, 0xc18f, 0x21, 0 + .dw 0x2940, 0xc18f, 0x297f, 0xc18f, 0x21, 0 + .dw 0x29c0, 0xc18f, 0x29ff, 0xc18f, 0x21, 0 + .dw 0x2a40, 0xc18f, 0x2a7f, 0xc18f, 0x21, 0 + .dw 0x2ac0, 0xc18f, 0x2aff, 0xc18f, 0x21, 0 + .dw 0x2b40, 0xc18f, 0x2b7f, 0xc18f, 0x21, 0 + .dw 0x2bc0, 0xc18f, 0x2bff, 0xc18f, 0x21, 0 + .dw 0x2c40, 0xc18f, 0x2c7f, 0xc18f, 0x21, 0 + .dw 0x2cc0, 0xc18f, 0x2cff, 0xc18f, 0x21, 0 + .dw 0x2d40, 0xc18f, 0x2d7f, 0xc18f, 0x21, 0 + .dw 0x2dc0, 0xc18f, 0x2dff, 0xc18f, 0x21, 0 + .dw 0x2e40, 0xc18f, 0x2e7f, 0xc18f, 0x21, 0 + .dw 0x2ec0, 0xc18f, 0x2eff, 0xc18f, 0x21, 0 + .dw 0x2f40, 0xc18f, 0x2f7f, 0xc18f, 0x21, 0 + .dw 0x2fc0, 0xc18f, 0x2fff, 0xc18f, 0x21, 0 + .dw 0x3040, 0xc18f, 0x307f, 0xc18f, 0x21, 0 + .dw 0x30c0, 0xc18f, 0x30ff, 0xc18f, 0x21, 0 + .dw 0x3140, 0xc18f, 0x317f, 0xc18f, 0x21, 0 + .dw 0x31c0, 0xc18f, 0x31ff, 0xc18f, 0x21, 0 + .dw 0x3240, 0xc18f, 0x327f, 0xc18f, 0x21, 0 + .dw 0x32c0, 0xc18f, 0x32ff, 0xc18f, 0x21, 0 + .dw 0x3340, 0xc18f, 0x337f, 0xc18f, 0x21, 0 + .dw 0x33c0, 0xc18f, 0x33ff, 0xc18f, 0x21, 0 + .dw 0x3440, 0xc18f, 0x347f, 0xc18f, 0x21, 0 + .dw 0x34c0, 0xc18f, 0x34ff, 0xc18f, 0x21, 0 + .dw 0x3540, 0xc18f, 0x357f, 0xc18f, 0x21, 0 + .dw 0x35c0, 0xc18f, 0x35ff, 0xc18f, 0x21, 0 + .dw 0x3640, 0xc18f, 0x367f, 0xc18f, 0x21, 0 + .dw 0x36c0, 0xc18f, 0x36ff, 0xc18f, 0x21, 0 + .dw 0x3740, 0xc18f, 0x377f, 0xc18f, 0x21, 0 + .dw 0x37c0, 0xc18f, 0x37ff, 0xc18f, 0x21, 0 + .dw 0x3840, 0xc18f, 0x387f, 0xc18f, 0x21, 0 + .dw 0x38c0, 0xc18f, 0x38ff, 0xc18f, 0x21, 0 + .dw 0x3940, 0xc18f, 0x397f, 0xc18f, 0x21, 0 + .dw 0x39c0, 0xc18f, 0x1fff, 0xc190, 0x21, 0 + .dw 0x3a00, 0xc190, 0x5fff, 0xc190, 0x21, 0 + .dw 0x7a00, 0xc190, 0x9fff, 0xc190, 0x21, 0 + .dw 0xba00, 0xc190, 0xdfff, 0xc190, 0x21, 0 + .dw 0xfa00, 0xc190, 0x1fff, 0xc191, 0x21, 0 + .dw 0x3a00, 0xc191, 0x5fff, 0xc191, 0x21, 0 + .dw 0x7a00, 0xc191, 0x9fff, 0xc191, 0x21, 0 + .dw 0xba00, 0xc191, 0xdfff, 0xc191, 0x21, 0 + .dw 0xfa00, 0xc191, 0x1fff, 0xc192, 0x21, 0 + .dw 0x3a00, 0xc192, 0x5fff, 0xc192, 0x21, 0 + .dw 0x7a00, 0xc192, 0x9fff, 0xc192, 0x21, 0 + .dw 0xba00, 0xc192, 0xdfff, 0xc192, 0x21, 0 + .dw 0xfa00, 0xc192, 0xffff, 0xc193, 0x21, 0 + .dw 0x1a00, 0xc194, 0x1fff, 0xc194, 0x21, 0 + .dw 0x3a00, 0xc194, 0x3fff, 0xc194, 0x21, 0 + .dw 0x5a00, 0xc194, 0x5fff, 0xc194, 0x21, 0 + .dw 0x7a00, 0xc194, 0x7fff, 0xc194, 0x21, 0 + .dw 0x9a00, 0xc194, 0x9fff, 0xc194, 0x21, 0 + .dw 0xba00, 0xc194, 0xbfff, 0xc194, 0x21, 0 + .dw 0xda00, 0xc194, 0xdfff, 0xc194, 0x21, 0 + .dw 0xfa00, 0xc194, 0xffff, 0xc194, 0x21, 0 + .dw 0x1a00, 0xc195, 0x1fff, 0xc195, 0x21, 0 + .dw 0x3a00, 0xc195, 0x3fff, 0xc195, 0x21, 0 + .dw 0x5a00, 0xc195, 0x5fff, 0xc195, 0x21, 0 + .dw 0x7a00, 0xc195, 0x7fff, 0xc195, 0x21, 0 + .dw 0x9a00, 0xc195, 0x9fff, 0xc195, 0x21, 0 + .dw 0xba00, 0xc195, 0xbfff, 0xc195, 0x21, 0 + .dw 0xda00, 0xc195, 0xdfff, 0xc195, 0x21, 0 + .dw 0xfa00, 0xc195, 0xffff, 0xc195, 0x21, 0 + .dw 0x1a00, 0xc196, 0x1fff, 0xc196, 0x21, 0 + .dw 0x3a00, 0xc196, 0x3fff, 0xc196, 0x21, 0 + .dw 0x5a00, 0xc196, 0x5fff, 0xc196, 0x21, 0 + .dw 0x7a00, 0xc196, 0x7fff, 0xc196, 0x21, 0 + .dw 0x9a00, 0xc196, 0x9fff, 0xc196, 0x21, 0 + .dw 0xba00, 0xc196, 0xbfff, 0xc196, 0x21, 0 + .dw 0xda00, 0xc196, 0xdfff, 0xc196, 0x21, 0 + .dw 0xfa00, 0xc196, 0xffff, 0xc196, 0x21, 0 + .dw 0x1a00, 0xc197, 0x1fff, 0xc197, 0x21, 0 + .dw 0x3a00, 0xc197, 0x1fff, 0xc198, 0x21, 0 + .dw 0x2040, 0xc198, 0x207f, 0xc198, 0x21, 0 + .dw 0x20c0, 0xc198, 0x20ff, 0xc198, 0x21, 0 + .dw 0x2140, 0xc198, 0x217f, 0xc198, 0x21, 0 + .dw 0x21c0, 0xc198, 0x21ff, 0xc198, 0x21, 0 + .dw 0x2240, 0xc198, 0x227f, 0xc198, 0x21, 0 + .dw 0x22c0, 0xc198, 0x22ff, 0xc198, 0x21, 0 + .dw 0x2340, 0xc198, 0x237f, 0xc198, 0x21, 0 + .dw 0x23c0, 0xc198, 0x23ff, 0xc198, 0x21, 0 + .dw 0x2440, 0xc198, 0x247f, 0xc198, 0x21, 0 + .dw 0x24c0, 0xc198, 0x24ff, 0xc198, 0x21, 0 + .dw 0x2540, 0xc198, 0x257f, 0xc198, 0x21, 0 + .dw 0x25c0, 0xc198, 0x25ff, 0xc198, 0x21, 0 + .dw 0x2640, 0xc198, 0x267f, 0xc198, 0x21, 0 + .dw 0x26c0, 0xc198, 0x26ff, 0xc198, 0x21, 0 + .dw 0x2740, 0xc198, 0x277f, 0xc198, 0x21, 0 + .dw 0x27c0, 0xc198, 0x27ff, 0xc198, 0x21, 0 + .dw 0x2840, 0xc198, 0x287f, 0xc198, 0x21, 0 + .dw 0x28c0, 0xc198, 0x28ff, 0xc198, 0x21, 0 + .dw 0x2940, 0xc198, 0x297f, 0xc198, 0x21, 0 + .dw 0x29c0, 0xc198, 0x29ff, 0xc198, 0x21, 0 + .dw 0x2a40, 0xc198, 0x2a7f, 0xc198, 0x21, 0 + .dw 0x2ac0, 0xc198, 0x2aff, 0xc198, 0x21, 0 + .dw 0x2b40, 0xc198, 0x2b7f, 0xc198, 0x21, 0 + .dw 0x2bc0, 0xc198, 0x2bff, 0xc198, 0x21, 0 + .dw 0x2c40, 0xc198, 0x2c7f, 0xc198, 0x21, 0 + .dw 0x2cc0, 0xc198, 0x2cff, 0xc198, 0x21, 0 + .dw 0x2d40, 0xc198, 0x2d7f, 0xc198, 0x21, 0 + .dw 0x2dc0, 0xc198, 0x2dff, 0xc198, 0x21, 0 + .dw 0x2e40, 0xc198, 0x2e7f, 0xc198, 0x21, 0 + .dw 0x2ec0, 0xc198, 0x2eff, 0xc198, 0x21, 0 + .dw 0x2f40, 0xc198, 0x2f7f, 0xc198, 0x21, 0 + .dw 0x2fc0, 0xc198, 0x2fff, 0xc198, 0x21, 0 + .dw 0x3040, 0xc198, 0x307f, 0xc198, 0x21, 0 + .dw 0x30c0, 0xc198, 0x30ff, 0xc198, 0x21, 0 + .dw 0x3140, 0xc198, 0x317f, 0xc198, 0x21, 0 + .dw 0x31c0, 0xc198, 0x31ff, 0xc198, 0x21, 0 + .dw 0x3240, 0xc198, 0x327f, 0xc198, 0x21, 0 + .dw 0x32c0, 0xc198, 0x32ff, 0xc198, 0x21, 0 + .dw 0x3340, 0xc198, 0x337f, 0xc198, 0x21, 0 + .dw 0x33c0, 0xc198, 0x33ff, 0xc198, 0x21, 0 + .dw 0x3440, 0xc198, 0x347f, 0xc198, 0x21, 0 + .dw 0x34c0, 0xc198, 0x34ff, 0xc198, 0x21, 0 + .dw 0x3540, 0xc198, 0x357f, 0xc198, 0x21, 0 + .dw 0x35c0, 0xc198, 0x35ff, 0xc198, 0x21, 0 + .dw 0x3640, 0xc198, 0x367f, 0xc198, 0x21, 0 + .dw 0x36c0, 0xc198, 0x36ff, 0xc198, 0x21, 0 + .dw 0x3740, 0xc198, 0x377f, 0xc198, 0x21, 0 + .dw 0x37c0, 0xc198, 0x37ff, 0xc198, 0x21, 0 + .dw 0x3840, 0xc198, 0x387f, 0xc198, 0x21, 0 + .dw 0x38c0, 0xc198, 0x38ff, 0xc198, 0x21, 0 + .dw 0x3940, 0xc198, 0x397f, 0xc198, 0x21, 0 + .dw 0x39c0, 0xc198, 0x5fff, 0xc198, 0x21, 0 + .dw 0x6040, 0xc198, 0x607f, 0xc198, 0x21, 0 + .dw 0x60c0, 0xc198, 0x60ff, 0xc198, 0x21, 0 + .dw 0x6140, 0xc198, 0x617f, 0xc198, 0x21, 0 + .dw 0x61c0, 0xc198, 0x61ff, 0xc198, 0x21, 0 + .dw 0x6240, 0xc198, 0x627f, 0xc198, 0x21, 0 + .dw 0x62c0, 0xc198, 0x62ff, 0xc198, 0x21, 0 + .dw 0x6340, 0xc198, 0x637f, 0xc198, 0x21, 0 + .dw 0x63c0, 0xc198, 0x63ff, 0xc198, 0x21, 0 + .dw 0x6440, 0xc198, 0x647f, 0xc198, 0x21, 0 + .dw 0x64c0, 0xc198, 0x64ff, 0xc198, 0x21, 0 + .dw 0x6540, 0xc198, 0x657f, 0xc198, 0x21, 0 + .dw 0x65c0, 0xc198, 0x65ff, 0xc198, 0x21, 0 + .dw 0x6640, 0xc198, 0x667f, 0xc198, 0x21, 0 + .dw 0x66c0, 0xc198, 0x66ff, 0xc198, 0x21, 0 + .dw 0x6740, 0xc198, 0x677f, 0xc198, 0x21, 0 + .dw 0x67c0, 0xc198, 0x67ff, 0xc198, 0x21, 0 + .dw 0x6840, 0xc198, 0x687f, 0xc198, 0x21, 0 + .dw 0x68c0, 0xc198, 0x68ff, 0xc198, 0x21, 0 + .dw 0x6940, 0xc198, 0x697f, 0xc198, 0x21, 0 + .dw 0x69c0, 0xc198, 0x69ff, 0xc198, 0x21, 0 + .dw 0x6a40, 0xc198, 0x6a7f, 0xc198, 0x21, 0 + .dw 0x6ac0, 0xc198, 0x6aff, 0xc198, 0x21, 0 + .dw 0x6b40, 0xc198, 0x6b7f, 0xc198, 0x21, 0 + .dw 0x6bc0, 0xc198, 0x6bff, 0xc198, 0x21, 0 + .dw 0x6c40, 0xc198, 0x6c7f, 0xc198, 0x21, 0 + .dw 0x6cc0, 0xc198, 0x6cff, 0xc198, 0x21, 0 + .dw 0x6d40, 0xc198, 0x6d7f, 0xc198, 0x21, 0 + .dw 0x6dc0, 0xc198, 0x6dff, 0xc198, 0x21, 0 + .dw 0x6e40, 0xc198, 0x6e7f, 0xc198, 0x21, 0 + .dw 0x6ec0, 0xc198, 0x6eff, 0xc198, 0x21, 0 + .dw 0x6f40, 0xc198, 0x6f7f, 0xc198, 0x21, 0 + .dw 0x6fc0, 0xc198, 0x6fff, 0xc198, 0x21, 0 + .dw 0x7040, 0xc198, 0x707f, 0xc198, 0x21, 0 + .dw 0x70c0, 0xc198, 0x70ff, 0xc198, 0x21, 0 + .dw 0x7140, 0xc198, 0x717f, 0xc198, 0x21, 0 + .dw 0x71c0, 0xc198, 0x71ff, 0xc198, 0x21, 0 + .dw 0x7240, 0xc198, 0x727f, 0xc198, 0x21, 0 + .dw 0x72c0, 0xc198, 0x72ff, 0xc198, 0x21, 0 + .dw 0x7340, 0xc198, 0x737f, 0xc198, 0x21, 0 + .dw 0x73c0, 0xc198, 0x73ff, 0xc198, 0x21, 0 + .dw 0x7440, 0xc198, 0x747f, 0xc198, 0x21, 0 + .dw 0x74c0, 0xc198, 0x74ff, 0xc198, 0x21, 0 + .dw 0x7540, 0xc198, 0x757f, 0xc198, 0x21, 0 + .dw 0x75c0, 0xc198, 0x75ff, 0xc198, 0x21, 0 + .dw 0x7640, 0xc198, 0x767f, 0xc198, 0x21, 0 + .dw 0x76c0, 0xc198, 0x76ff, 0xc198, 0x21, 0 + .dw 0x7740, 0xc198, 0x777f, 0xc198, 0x21, 0 + .dw 0x77c0, 0xc198, 0x77ff, 0xc198, 0x21, 0 + .dw 0x7840, 0xc198, 0x787f, 0xc198, 0x21, 0 + .dw 0x78c0, 0xc198, 0x78ff, 0xc198, 0x21, 0 + .dw 0x7940, 0xc198, 0x797f, 0xc198, 0x21, 0 + .dw 0x79c0, 0xc198, 0x9fff, 0xc198, 0x21, 0 + .dw 0xa040, 0xc198, 0xa07f, 0xc198, 0x21, 0 + .dw 0xa0c0, 0xc198, 0xa0ff, 0xc198, 0x21, 0 + .dw 0xa140, 0xc198, 0xa17f, 0xc198, 0x21, 0 + .dw 0xa1c0, 0xc198, 0xa1ff, 0xc198, 0x21, 0 + .dw 0xa240, 0xc198, 0xa27f, 0xc198, 0x21, 0 + .dw 0xa2c0, 0xc198, 0xa2ff, 0xc198, 0x21, 0 + .dw 0xa340, 0xc198, 0xa37f, 0xc198, 0x21, 0 + .dw 0xa3c0, 0xc198, 0xa3ff, 0xc198, 0x21, 0 + .dw 0xa440, 0xc198, 0xa47f, 0xc198, 0x21, 0 + .dw 0xa4c0, 0xc198, 0xa4ff, 0xc198, 0x21, 0 + .dw 0xa540, 0xc198, 0xa57f, 0xc198, 0x21, 0 + .dw 0xa5c0, 0xc198, 0xa5ff, 0xc198, 0x21, 0 + .dw 0xa640, 0xc198, 0xa67f, 0xc198, 0x21, 0 + .dw 0xa6c0, 0xc198, 0xa6ff, 0xc198, 0x21, 0 + .dw 0xa740, 0xc198, 0xa77f, 0xc198, 0x21, 0 + .dw 0xa7c0, 0xc198, 0xa7ff, 0xc198, 0x21, 0 + .dw 0xa840, 0xc198, 0xa87f, 0xc198, 0x21, 0 + .dw 0xa8c0, 0xc198, 0xa8ff, 0xc198, 0x21, 0 + .dw 0xa940, 0xc198, 0xa97f, 0xc198, 0x21, 0 + .dw 0xa9c0, 0xc198, 0xa9ff, 0xc198, 0x21, 0 + .dw 0xaa40, 0xc198, 0xaa7f, 0xc198, 0x21, 0 + .dw 0xaac0, 0xc198, 0xaaff, 0xc198, 0x21, 0 + .dw 0xab40, 0xc198, 0xab7f, 0xc198, 0x21, 0 + .dw 0xabc0, 0xc198, 0xabff, 0xc198, 0x21, 0 + .dw 0xac40, 0xc198, 0xac7f, 0xc198, 0x21, 0 + .dw 0xacc0, 0xc198, 0xacff, 0xc198, 0x21, 0 + .dw 0xad40, 0xc198, 0xad7f, 0xc198, 0x21, 0 + .dw 0xadc0, 0xc198, 0xadff, 0xc198, 0x21, 0 + .dw 0xae40, 0xc198, 0xae7f, 0xc198, 0x21, 0 + .dw 0xaec0, 0xc198, 0xaeff, 0xc198, 0x21, 0 + .dw 0xaf40, 0xc198, 0xaf7f, 0xc198, 0x21, 0 + .dw 0xafc0, 0xc198, 0xafff, 0xc198, 0x21, 0 + .dw 0xb040, 0xc198, 0xb07f, 0xc198, 0x21, 0 + .dw 0xb0c0, 0xc198, 0xb0ff, 0xc198, 0x21, 0 + .dw 0xb140, 0xc198, 0xb17f, 0xc198, 0x21, 0 + .dw 0xb1c0, 0xc198, 0xb1ff, 0xc198, 0x21, 0 + .dw 0xb240, 0xc198, 0xb27f, 0xc198, 0x21, 0 + .dw 0xb2c0, 0xc198, 0xb2ff, 0xc198, 0x21, 0 + .dw 0xb340, 0xc198, 0xb37f, 0xc198, 0x21, 0 + .dw 0xb3c0, 0xc198, 0xb3ff, 0xc198, 0x21, 0 + .dw 0xb440, 0xc198, 0xb47f, 0xc198, 0x21, 0 + .dw 0xb4c0, 0xc198, 0xb4ff, 0xc198, 0x21, 0 + .dw 0xb540, 0xc198, 0xb57f, 0xc198, 0x21, 0 + .dw 0xb5c0, 0xc198, 0xb5ff, 0xc198, 0x21, 0 + .dw 0xb640, 0xc198, 0xb67f, 0xc198, 0x21, 0 + .dw 0xb6c0, 0xc198, 0xb6ff, 0xc198, 0x21, 0 + .dw 0xb740, 0xc198, 0xb77f, 0xc198, 0x21, 0 + .dw 0xb7c0, 0xc198, 0xb7ff, 0xc198, 0x21, 0 + .dw 0xb840, 0xc198, 0xb87f, 0xc198, 0x21, 0 + .dw 0xb8c0, 0xc198, 0xb8ff, 0xc198, 0x21, 0 + .dw 0xb940, 0xc198, 0xb97f, 0xc198, 0x21, 0 + .dw 0xb9c0, 0xc198, 0xdfff, 0xc198, 0x21, 0 + .dw 0xe040, 0xc198, 0xe07f, 0xc198, 0x21, 0 + .dw 0xe0c0, 0xc198, 0xe0ff, 0xc198, 0x21, 0 + .dw 0xe140, 0xc198, 0xe17f, 0xc198, 0x21, 0 + .dw 0xe1c0, 0xc198, 0xe1ff, 0xc198, 0x21, 0 + .dw 0xe240, 0xc198, 0xe27f, 0xc198, 0x21, 0 + .dw 0xe2c0, 0xc198, 0xe2ff, 0xc198, 0x21, 0 + .dw 0xe340, 0xc198, 0xe37f, 0xc198, 0x21, 0 + .dw 0xe3c0, 0xc198, 0xe3ff, 0xc198, 0x21, 0 + .dw 0xe440, 0xc198, 0xe47f, 0xc198, 0x21, 0 + .dw 0xe4c0, 0xc198, 0xe4ff, 0xc198, 0x21, 0 + .dw 0xe540, 0xc198, 0xe57f, 0xc198, 0x21, 0 + .dw 0xe5c0, 0xc198, 0xe5ff, 0xc198, 0x21, 0 + .dw 0xe640, 0xc198, 0xe67f, 0xc198, 0x21, 0 + .dw 0xe6c0, 0xc198, 0xe6ff, 0xc198, 0x21, 0 + .dw 0xe740, 0xc198, 0xe77f, 0xc198, 0x21, 0 + .dw 0xe7c0, 0xc198, 0xe7ff, 0xc198, 0x21, 0 + .dw 0xe840, 0xc198, 0xe87f, 0xc198, 0x21, 0 + .dw 0xe8c0, 0xc198, 0xe8ff, 0xc198, 0x21, 0 + .dw 0xe940, 0xc198, 0xe97f, 0xc198, 0x21, 0 + .dw 0xe9c0, 0xc198, 0xe9ff, 0xc198, 0x21, 0 + .dw 0xea40, 0xc198, 0xea7f, 0xc198, 0x21, 0 + .dw 0xeac0, 0xc198, 0xeaff, 0xc198, 0x21, 0 + .dw 0xeb40, 0xc198, 0xeb7f, 0xc198, 0x21, 0 + .dw 0xebc0, 0xc198, 0xebff, 0xc198, 0x21, 0 + .dw 0xec40, 0xc198, 0xec7f, 0xc198, 0x21, 0 + .dw 0xecc0, 0xc198, 0xecff, 0xc198, 0x21, 0 + .dw 0xed40, 0xc198, 0xed7f, 0xc198, 0x21, 0 + .dw 0xedc0, 0xc198, 0xedff, 0xc198, 0x21, 0 + .dw 0xee40, 0xc198, 0xee7f, 0xc198, 0x21, 0 + .dw 0xeec0, 0xc198, 0xeeff, 0xc198, 0x21, 0 + .dw 0xef40, 0xc198, 0xef7f, 0xc198, 0x21, 0 + .dw 0xefc0, 0xc198, 0xefff, 0xc198, 0x21, 0 + .dw 0xf040, 0xc198, 0xf07f, 0xc198, 0x21, 0 + .dw 0xf0c0, 0xc198, 0xf0ff, 0xc198, 0x21, 0 + .dw 0xf140, 0xc198, 0xf17f, 0xc198, 0x21, 0 + .dw 0xf1c0, 0xc198, 0xf1ff, 0xc198, 0x21, 0 + .dw 0xf240, 0xc198, 0xf27f, 0xc198, 0x21, 0 + .dw 0xf2c0, 0xc198, 0xf2ff, 0xc198, 0x21, 0 + .dw 0xf340, 0xc198, 0xf37f, 0xc198, 0x21, 0 + .dw 0xf3c0, 0xc198, 0xf3ff, 0xc198, 0x21, 0 + .dw 0xf440, 0xc198, 0xf47f, 0xc198, 0x21, 0 + .dw 0xf4c0, 0xc198, 0xf4ff, 0xc198, 0x21, 0 + .dw 0xf540, 0xc198, 0xf57f, 0xc198, 0x21, 0 + .dw 0xf5c0, 0xc198, 0xf5ff, 0xc198, 0x21, 0 + .dw 0xf640, 0xc198, 0xf67f, 0xc198, 0x21, 0 + .dw 0xf6c0, 0xc198, 0xf6ff, 0xc198, 0x21, 0 + .dw 0xf740, 0xc198, 0xf77f, 0xc198, 0x21, 0 + .dw 0xf7c0, 0xc198, 0xf7ff, 0xc198, 0x21, 0 + .dw 0xf840, 0xc198, 0xf87f, 0xc198, 0x21, 0 + .dw 0xf8c0, 0xc198, 0xf8ff, 0xc198, 0x21, 0 + .dw 0xf940, 0xc198, 0xf97f, 0xc198, 0x21, 0 + .dw 0xf9c0, 0xc198, 0x1fff, 0xc199, 0x21, 0 + .dw 0x2040, 0xc199, 0x207f, 0xc199, 0x21, 0 + .dw 0x20c0, 0xc199, 0x20ff, 0xc199, 0x21, 0 + .dw 0x2140, 0xc199, 0x217f, 0xc199, 0x21, 0 + .dw 0x21c0, 0xc199, 0x21ff, 0xc199, 0x21, 0 + .dw 0x2240, 0xc199, 0x227f, 0xc199, 0x21, 0 + .dw 0x22c0, 0xc199, 0x22ff, 0xc199, 0x21, 0 + .dw 0x2340, 0xc199, 0x237f, 0xc199, 0x21, 0 + .dw 0x23c0, 0xc199, 0x23ff, 0xc199, 0x21, 0 + .dw 0x2440, 0xc199, 0x247f, 0xc199, 0x21, 0 + .dw 0x24c0, 0xc199, 0x24ff, 0xc199, 0x21, 0 + .dw 0x2540, 0xc199, 0x257f, 0xc199, 0x21, 0 + .dw 0x25c0, 0xc199, 0x25ff, 0xc199, 0x21, 0 + .dw 0x2640, 0xc199, 0x267f, 0xc199, 0x21, 0 + .dw 0x26c0, 0xc199, 0x26ff, 0xc199, 0x21, 0 + .dw 0x2740, 0xc199, 0x277f, 0xc199, 0x21, 0 + .dw 0x27c0, 0xc199, 0x27ff, 0xc199, 0x21, 0 + .dw 0x2840, 0xc199, 0x287f, 0xc199, 0x21, 0 + .dw 0x28c0, 0xc199, 0x28ff, 0xc199, 0x21, 0 + .dw 0x2940, 0xc199, 0x297f, 0xc199, 0x21, 0 + .dw 0x29c0, 0xc199, 0x29ff, 0xc199, 0x21, 0 + .dw 0x2a40, 0xc199, 0x2a7f, 0xc199, 0x21, 0 + .dw 0x2ac0, 0xc199, 0x2aff, 0xc199, 0x21, 0 + .dw 0x2b40, 0xc199, 0x2b7f, 0xc199, 0x21, 0 + .dw 0x2bc0, 0xc199, 0x2bff, 0xc199, 0x21, 0 + .dw 0x2c40, 0xc199, 0x2c7f, 0xc199, 0x21, 0 + .dw 0x2cc0, 0xc199, 0x2cff, 0xc199, 0x21, 0 + .dw 0x2d40, 0xc199, 0x2d7f, 0xc199, 0x21, 0 + .dw 0x2dc0, 0xc199, 0x2dff, 0xc199, 0x21, 0 + .dw 0x2e40, 0xc199, 0x2e7f, 0xc199, 0x21, 0 + .dw 0x2ec0, 0xc199, 0x2eff, 0xc199, 0x21, 0 + .dw 0x2f40, 0xc199, 0x2f7f, 0xc199, 0x21, 0 + .dw 0x2fc0, 0xc199, 0x2fff, 0xc199, 0x21, 0 + .dw 0x3040, 0xc199, 0x307f, 0xc199, 0x21, 0 + .dw 0x30c0, 0xc199, 0x30ff, 0xc199, 0x21, 0 + .dw 0x3140, 0xc199, 0x317f, 0xc199, 0x21, 0 + .dw 0x31c0, 0xc199, 0x31ff, 0xc199, 0x21, 0 + .dw 0x3240, 0xc199, 0x327f, 0xc199, 0x21, 0 + .dw 0x32c0, 0xc199, 0x32ff, 0xc199, 0x21, 0 + .dw 0x3340, 0xc199, 0x337f, 0xc199, 0x21, 0 + .dw 0x33c0, 0xc199, 0x33ff, 0xc199, 0x21, 0 + .dw 0x3440, 0xc199, 0x347f, 0xc199, 0x21, 0 + .dw 0x34c0, 0xc199, 0x34ff, 0xc199, 0x21, 0 + .dw 0x3540, 0xc199, 0x357f, 0xc199, 0x21, 0 + .dw 0x35c0, 0xc199, 0x35ff, 0xc199, 0x21, 0 + .dw 0x3640, 0xc199, 0x367f, 0xc199, 0x21, 0 + .dw 0x36c0, 0xc199, 0x36ff, 0xc199, 0x21, 0 + .dw 0x3740, 0xc199, 0x377f, 0xc199, 0x21, 0 + .dw 0x37c0, 0xc199, 0x37ff, 0xc199, 0x21, 0 + .dw 0x3840, 0xc199, 0x387f, 0xc199, 0x21, 0 + .dw 0x38c0, 0xc199, 0x38ff, 0xc199, 0x21, 0 + .dw 0x3940, 0xc199, 0x397f, 0xc199, 0x21, 0 + .dw 0x39c0, 0xc199, 0x5fff, 0xc199, 0x21, 0 + .dw 0x6040, 0xc199, 0x607f, 0xc199, 0x21, 0 + .dw 0x60c0, 0xc199, 0x60ff, 0xc199, 0x21, 0 + .dw 0x6140, 0xc199, 0x617f, 0xc199, 0x21, 0 + .dw 0x61c0, 0xc199, 0x61ff, 0xc199, 0x21, 0 + .dw 0x6240, 0xc199, 0x627f, 0xc199, 0x21, 0 + .dw 0x62c0, 0xc199, 0x62ff, 0xc199, 0x21, 0 + .dw 0x6340, 0xc199, 0x637f, 0xc199, 0x21, 0 + .dw 0x63c0, 0xc199, 0x63ff, 0xc199, 0x21, 0 + .dw 0x6440, 0xc199, 0x647f, 0xc199, 0x21, 0 + .dw 0x64c0, 0xc199, 0x64ff, 0xc199, 0x21, 0 + .dw 0x6540, 0xc199, 0x657f, 0xc199, 0x21, 0 + .dw 0x65c0, 0xc199, 0x65ff, 0xc199, 0x21, 0 + .dw 0x6640, 0xc199, 0x667f, 0xc199, 0x21, 0 + .dw 0x66c0, 0xc199, 0x66ff, 0xc199, 0x21, 0 + .dw 0x6740, 0xc199, 0x677f, 0xc199, 0x21, 0 + .dw 0x67c0, 0xc199, 0x67ff, 0xc199, 0x21, 0 + .dw 0x6840, 0xc199, 0x687f, 0xc199, 0x21, 0 + .dw 0x68c0, 0xc199, 0x68ff, 0xc199, 0x21, 0 + .dw 0x6940, 0xc199, 0x697f, 0xc199, 0x21, 0 + .dw 0x69c0, 0xc199, 0x69ff, 0xc199, 0x21, 0 + .dw 0x6a40, 0xc199, 0x6a7f, 0xc199, 0x21, 0 + .dw 0x6ac0, 0xc199, 0x6aff, 0xc199, 0x21, 0 + .dw 0x6b40, 0xc199, 0x6b7f, 0xc199, 0x21, 0 + .dw 0x6bc0, 0xc199, 0x6bff, 0xc199, 0x21, 0 + .dw 0x6c40, 0xc199, 0x6c7f, 0xc199, 0x21, 0 + .dw 0x6cc0, 0xc199, 0x6cff, 0xc199, 0x21, 0 + .dw 0x6d40, 0xc199, 0x6d7f, 0xc199, 0x21, 0 + .dw 0x6dc0, 0xc199, 0x6dff, 0xc199, 0x21, 0 + .dw 0x6e40, 0xc199, 0x6e7f, 0xc199, 0x21, 0 + .dw 0x6ec0, 0xc199, 0x6eff, 0xc199, 0x21, 0 + .dw 0x6f40, 0xc199, 0x6f7f, 0xc199, 0x21, 0 + .dw 0x6fc0, 0xc199, 0x6fff, 0xc199, 0x21, 0 + .dw 0x7040, 0xc199, 0x707f, 0xc199, 0x21, 0 + .dw 0x70c0, 0xc199, 0x70ff, 0xc199, 0x21, 0 + .dw 0x7140, 0xc199, 0x717f, 0xc199, 0x21, 0 + .dw 0x71c0, 0xc199, 0x71ff, 0xc199, 0x21, 0 + .dw 0x7240, 0xc199, 0x727f, 0xc199, 0x21, 0 + .dw 0x72c0, 0xc199, 0x72ff, 0xc199, 0x21, 0 + .dw 0x7340, 0xc199, 0x737f, 0xc199, 0x21, 0 + .dw 0x73c0, 0xc199, 0x73ff, 0xc199, 0x21, 0 + .dw 0x7440, 0xc199, 0x747f, 0xc199, 0x21, 0 + .dw 0x74c0, 0xc199, 0x74ff, 0xc199, 0x21, 0 + .dw 0x7540, 0xc199, 0x757f, 0xc199, 0x21, 0 + .dw 0x75c0, 0xc199, 0x75ff, 0xc199, 0x21, 0 + .dw 0x7640, 0xc199, 0x767f, 0xc199, 0x21, 0 + .dw 0x76c0, 0xc199, 0x76ff, 0xc199, 0x21, 0 + .dw 0x7740, 0xc199, 0x777f, 0xc199, 0x21, 0 + .dw 0x77c0, 0xc199, 0x77ff, 0xc199, 0x21, 0 + .dw 0x7840, 0xc199, 0x787f, 0xc199, 0x21, 0 + .dw 0x78c0, 0xc199, 0x78ff, 0xc199, 0x21, 0 + .dw 0x7940, 0xc199, 0x797f, 0xc199, 0x21, 0 + .dw 0x79c0, 0xc199, 0x9fff, 0xc199, 0x21, 0 + .dw 0xa040, 0xc199, 0xa07f, 0xc199, 0x21, 0 + .dw 0xa0c0, 0xc199, 0xa0ff, 0xc199, 0x21, 0 + .dw 0xa140, 0xc199, 0xa17f, 0xc199, 0x21, 0 + .dw 0xa1c0, 0xc199, 0xa1ff, 0xc199, 0x21, 0 + .dw 0xa240, 0xc199, 0xa27f, 0xc199, 0x21, 0 + .dw 0xa2c0, 0xc199, 0xa2ff, 0xc199, 0x21, 0 + .dw 0xa340, 0xc199, 0xa37f, 0xc199, 0x21, 0 + .dw 0xa3c0, 0xc199, 0xa3ff, 0xc199, 0x21, 0 + .dw 0xa440, 0xc199, 0xa47f, 0xc199, 0x21, 0 + .dw 0xa4c0, 0xc199, 0xa4ff, 0xc199, 0x21, 0 + .dw 0xa540, 0xc199, 0xa57f, 0xc199, 0x21, 0 + .dw 0xa5c0, 0xc199, 0xa5ff, 0xc199, 0x21, 0 + .dw 0xa640, 0xc199, 0xa67f, 0xc199, 0x21, 0 + .dw 0xa6c0, 0xc199, 0xa6ff, 0xc199, 0x21, 0 + .dw 0xa740, 0xc199, 0xa77f, 0xc199, 0x21, 0 + .dw 0xa7c0, 0xc199, 0xa7ff, 0xc199, 0x21, 0 + .dw 0xa840, 0xc199, 0xa87f, 0xc199, 0x21, 0 + .dw 0xa8c0, 0xc199, 0xa8ff, 0xc199, 0x21, 0 + .dw 0xa940, 0xc199, 0xa97f, 0xc199, 0x21, 0 + .dw 0xa9c0, 0xc199, 0xa9ff, 0xc199, 0x21, 0 + .dw 0xaa40, 0xc199, 0xaa7f, 0xc199, 0x21, 0 + .dw 0xaac0, 0xc199, 0xaaff, 0xc199, 0x21, 0 + .dw 0xab40, 0xc199, 0xab7f, 0xc199, 0x21, 0 + .dw 0xabc0, 0xc199, 0xabff, 0xc199, 0x21, 0 + .dw 0xac40, 0xc199, 0xac7f, 0xc199, 0x21, 0 + .dw 0xacc0, 0xc199, 0xacff, 0xc199, 0x21, 0 + .dw 0xad40, 0xc199, 0xad7f, 0xc199, 0x21, 0 + .dw 0xadc0, 0xc199, 0xadff, 0xc199, 0x21, 0 + .dw 0xae40, 0xc199, 0xae7f, 0xc199, 0x21, 0 + .dw 0xaec0, 0xc199, 0xaeff, 0xc199, 0x21, 0 + .dw 0xaf40, 0xc199, 0xaf7f, 0xc199, 0x21, 0 + .dw 0xafc0, 0xc199, 0xafff, 0xc199, 0x21, 0 + .dw 0xb040, 0xc199, 0xb07f, 0xc199, 0x21, 0 + .dw 0xb0c0, 0xc199, 0xb0ff, 0xc199, 0x21, 0 + .dw 0xb140, 0xc199, 0xb17f, 0xc199, 0x21, 0 + .dw 0xb1c0, 0xc199, 0xb1ff, 0xc199, 0x21, 0 + .dw 0xb240, 0xc199, 0xb27f, 0xc199, 0x21, 0 + .dw 0xb2c0, 0xc199, 0xb2ff, 0xc199, 0x21, 0 + .dw 0xb340, 0xc199, 0xb37f, 0xc199, 0x21, 0 + .dw 0xb3c0, 0xc199, 0xb3ff, 0xc199, 0x21, 0 + .dw 0xb440, 0xc199, 0xb47f, 0xc199, 0x21, 0 + .dw 0xb4c0, 0xc199, 0xb4ff, 0xc199, 0x21, 0 + .dw 0xb540, 0xc199, 0xb57f, 0xc199, 0x21, 0 + .dw 0xb5c0, 0xc199, 0xb5ff, 0xc199, 0x21, 0 + .dw 0xb640, 0xc199, 0xb67f, 0xc199, 0x21, 0 + .dw 0xb6c0, 0xc199, 0xb6ff, 0xc199, 0x21, 0 + .dw 0xb740, 0xc199, 0xb77f, 0xc199, 0x21, 0 + .dw 0xb7c0, 0xc199, 0xb7ff, 0xc199, 0x21, 0 + .dw 0xb840, 0xc199, 0xb87f, 0xc199, 0x21, 0 + .dw 0xb8c0, 0xc199, 0xb8ff, 0xc199, 0x21, 0 + .dw 0xb940, 0xc199, 0xb97f, 0xc199, 0x21, 0 + .dw 0xb9c0, 0xc199, 0xdfff, 0xc199, 0x21, 0 + .dw 0xe040, 0xc199, 0xe07f, 0xc199, 0x21, 0 + .dw 0xe0c0, 0xc199, 0xe0ff, 0xc199, 0x21, 0 + .dw 0xe140, 0xc199, 0xe17f, 0xc199, 0x21, 0 + .dw 0xe1c0, 0xc199, 0xe1ff, 0xc199, 0x21, 0 + .dw 0xe240, 0xc199, 0xe27f, 0xc199, 0x21, 0 + .dw 0xe2c0, 0xc199, 0xe2ff, 0xc199, 0x21, 0 + .dw 0xe340, 0xc199, 0xe37f, 0xc199, 0x21, 0 + .dw 0xe3c0, 0xc199, 0xe3ff, 0xc199, 0x21, 0 + .dw 0xe440, 0xc199, 0xe47f, 0xc199, 0x21, 0 + .dw 0xe4c0, 0xc199, 0xe4ff, 0xc199, 0x21, 0 + .dw 0xe540, 0xc199, 0xe57f, 0xc199, 0x21, 0 + .dw 0xe5c0, 0xc199, 0xe5ff, 0xc199, 0x21, 0 + .dw 0xe640, 0xc199, 0xe67f, 0xc199, 0x21, 0 + .dw 0xe6c0, 0xc199, 0xe6ff, 0xc199, 0x21, 0 + .dw 0xe740, 0xc199, 0xe77f, 0xc199, 0x21, 0 + .dw 0xe7c0, 0xc199, 0xe7ff, 0xc199, 0x21, 0 + .dw 0xe840, 0xc199, 0xe87f, 0xc199, 0x21, 0 + .dw 0xe8c0, 0xc199, 0xe8ff, 0xc199, 0x21, 0 + .dw 0xe940, 0xc199, 0xe97f, 0xc199, 0x21, 0 + .dw 0xe9c0, 0xc199, 0xe9ff, 0xc199, 0x21, 0 + .dw 0xea40, 0xc199, 0xea7f, 0xc199, 0x21, 0 + .dw 0xeac0, 0xc199, 0xeaff, 0xc199, 0x21, 0 + .dw 0xeb40, 0xc199, 0xeb7f, 0xc199, 0x21, 0 + .dw 0xebc0, 0xc199, 0xebff, 0xc199, 0x21, 0 + .dw 0xec40, 0xc199, 0xec7f, 0xc199, 0x21, 0 + .dw 0xecc0, 0xc199, 0xecff, 0xc199, 0x21, 0 + .dw 0xed40, 0xc199, 0xed7f, 0xc199, 0x21, 0 + .dw 0xedc0, 0xc199, 0xedff, 0xc199, 0x21, 0 + .dw 0xee40, 0xc199, 0xee7f, 0xc199, 0x21, 0 + .dw 0xeec0, 0xc199, 0xeeff, 0xc199, 0x21, 0 + .dw 0xef40, 0xc199, 0xef7f, 0xc199, 0x21, 0 + .dw 0xefc0, 0xc199, 0xefff, 0xc199, 0x21, 0 + .dw 0xf040, 0xc199, 0xf07f, 0xc199, 0x21, 0 + .dw 0xf0c0, 0xc199, 0xf0ff, 0xc199, 0x21, 0 + .dw 0xf140, 0xc199, 0xf17f, 0xc199, 0x21, 0 + .dw 0xf1c0, 0xc199, 0xf1ff, 0xc199, 0x21, 0 + .dw 0xf240, 0xc199, 0xf27f, 0xc199, 0x21, 0 + .dw 0xf2c0, 0xc199, 0xf2ff, 0xc199, 0x21, 0 + .dw 0xf340, 0xc199, 0xf37f, 0xc199, 0x21, 0 + .dw 0xf3c0, 0xc199, 0xf3ff, 0xc199, 0x21, 0 + .dw 0xf440, 0xc199, 0xf47f, 0xc199, 0x21, 0 + .dw 0xf4c0, 0xc199, 0xf4ff, 0xc199, 0x21, 0 + .dw 0xf540, 0xc199, 0xf57f, 0xc199, 0x21, 0 + .dw 0xf5c0, 0xc199, 0xf5ff, 0xc199, 0x21, 0 + .dw 0xf640, 0xc199, 0xf67f, 0xc199, 0x21, 0 + .dw 0xf6c0, 0xc199, 0xf6ff, 0xc199, 0x21, 0 + .dw 0xf740, 0xc199, 0xf77f, 0xc199, 0x21, 0 + .dw 0xf7c0, 0xc199, 0xf7ff, 0xc199, 0x21, 0 + .dw 0xf840, 0xc199, 0xf87f, 0xc199, 0x21, 0 + .dw 0xf8c0, 0xc199, 0xf8ff, 0xc199, 0x21, 0 + .dw 0xf940, 0xc199, 0xf97f, 0xc199, 0x21, 0 + .dw 0xf9c0, 0xc199, 0x1fff, 0xc19a, 0x21, 0 + .dw 0x2040, 0xc19a, 0x207f, 0xc19a, 0x21, 0 + .dw 0x20c0, 0xc19a, 0x20ff, 0xc19a, 0x21, 0 + .dw 0x2140, 0xc19a, 0x217f, 0xc19a, 0x21, 0 + .dw 0x21c0, 0xc19a, 0x21ff, 0xc19a, 0x21, 0 + .dw 0x2240, 0xc19a, 0x227f, 0xc19a, 0x21, 0 + .dw 0x22c0, 0xc19a, 0x22ff, 0xc19a, 0x21, 0 + .dw 0x2340, 0xc19a, 0x237f, 0xc19a, 0x21, 0 + .dw 0x23c0, 0xc19a, 0x23ff, 0xc19a, 0x21, 0 + .dw 0x2440, 0xc19a, 0x247f, 0xc19a, 0x21, 0 + .dw 0x24c0, 0xc19a, 0x24ff, 0xc19a, 0x21, 0 + .dw 0x2540, 0xc19a, 0x257f, 0xc19a, 0x21, 0 + .dw 0x25c0, 0xc19a, 0x25ff, 0xc19a, 0x21, 0 + .dw 0x2640, 0xc19a, 0x267f, 0xc19a, 0x21, 0 + .dw 0x26c0, 0xc19a, 0x26ff, 0xc19a, 0x21, 0 + .dw 0x2740, 0xc19a, 0x277f, 0xc19a, 0x21, 0 + .dw 0x27c0, 0xc19a, 0x27ff, 0xc19a, 0x21, 0 + .dw 0x2840, 0xc19a, 0x287f, 0xc19a, 0x21, 0 + .dw 0x28c0, 0xc19a, 0x28ff, 0xc19a, 0x21, 0 + .dw 0x2940, 0xc19a, 0x297f, 0xc19a, 0x21, 0 + .dw 0x29c0, 0xc19a, 0x29ff, 0xc19a, 0x21, 0 + .dw 0x2a40, 0xc19a, 0x2a7f, 0xc19a, 0x21, 0 + .dw 0x2ac0, 0xc19a, 0x2aff, 0xc19a, 0x21, 0 + .dw 0x2b40, 0xc19a, 0x2b7f, 0xc19a, 0x21, 0 + .dw 0x2bc0, 0xc19a, 0x2bff, 0xc19a, 0x21, 0 + .dw 0x2c40, 0xc19a, 0x2c7f, 0xc19a, 0x21, 0 + .dw 0x2cc0, 0xc19a, 0x2cff, 0xc19a, 0x21, 0 + .dw 0x2d40, 0xc19a, 0x2d7f, 0xc19a, 0x21, 0 + .dw 0x2dc0, 0xc19a, 0x2dff, 0xc19a, 0x21, 0 + .dw 0x2e40, 0xc19a, 0x2e7f, 0xc19a, 0x21, 0 + .dw 0x2ec0, 0xc19a, 0x2eff, 0xc19a, 0x21, 0 + .dw 0x2f40, 0xc19a, 0x2f7f, 0xc19a, 0x21, 0 + .dw 0x2fc0, 0xc19a, 0x2fff, 0xc19a, 0x21, 0 + .dw 0x3040, 0xc19a, 0x307f, 0xc19a, 0x21, 0 + .dw 0x30c0, 0xc19a, 0x30ff, 0xc19a, 0x21, 0 + .dw 0x3140, 0xc19a, 0x317f, 0xc19a, 0x21, 0 + .dw 0x31c0, 0xc19a, 0x31ff, 0xc19a, 0x21, 0 + .dw 0x3240, 0xc19a, 0x327f, 0xc19a, 0x21, 0 + .dw 0x32c0, 0xc19a, 0x32ff, 0xc19a, 0x21, 0 + .dw 0x3340, 0xc19a, 0x337f, 0xc19a, 0x21, 0 + .dw 0x33c0, 0xc19a, 0x33ff, 0xc19a, 0x21, 0 + .dw 0x3440, 0xc19a, 0x347f, 0xc19a, 0x21, 0 + .dw 0x34c0, 0xc19a, 0x34ff, 0xc19a, 0x21, 0 + .dw 0x3540, 0xc19a, 0x357f, 0xc19a, 0x21, 0 + .dw 0x35c0, 0xc19a, 0x35ff, 0xc19a, 0x21, 0 + .dw 0x3640, 0xc19a, 0x367f, 0xc19a, 0x21, 0 + .dw 0x36c0, 0xc19a, 0x36ff, 0xc19a, 0x21, 0 + .dw 0x3740, 0xc19a, 0x377f, 0xc19a, 0x21, 0 + .dw 0x37c0, 0xc19a, 0x37ff, 0xc19a, 0x21, 0 + .dw 0x3840, 0xc19a, 0x387f, 0xc19a, 0x21, 0 + .dw 0x38c0, 0xc19a, 0x38ff, 0xc19a, 0x21, 0 + .dw 0x3940, 0xc19a, 0x397f, 0xc19a, 0x21, 0 + .dw 0x39c0, 0xc19a, 0x5fff, 0xc19a, 0x21, 0 + .dw 0x6040, 0xc19a, 0x607f, 0xc19a, 0x21, 0 + .dw 0x60c0, 0xc19a, 0x60ff, 0xc19a, 0x21, 0 + .dw 0x6140, 0xc19a, 0x617f, 0xc19a, 0x21, 0 + .dw 0x61c0, 0xc19a, 0x61ff, 0xc19a, 0x21, 0 + .dw 0x6240, 0xc19a, 0x627f, 0xc19a, 0x21, 0 + .dw 0x62c0, 0xc19a, 0x62ff, 0xc19a, 0x21, 0 + .dw 0x6340, 0xc19a, 0x637f, 0xc19a, 0x21, 0 + .dw 0x63c0, 0xc19a, 0x63ff, 0xc19a, 0x21, 0 + .dw 0x6440, 0xc19a, 0x647f, 0xc19a, 0x21, 0 + .dw 0x64c0, 0xc19a, 0x64ff, 0xc19a, 0x21, 0 + .dw 0x6540, 0xc19a, 0x657f, 0xc19a, 0x21, 0 + .dw 0x65c0, 0xc19a, 0x65ff, 0xc19a, 0x21, 0 + .dw 0x6640, 0xc19a, 0x667f, 0xc19a, 0x21, 0 + .dw 0x66c0, 0xc19a, 0x66ff, 0xc19a, 0x21, 0 + .dw 0x6740, 0xc19a, 0x677f, 0xc19a, 0x21, 0 + .dw 0x67c0, 0xc19a, 0x67ff, 0xc19a, 0x21, 0 + .dw 0x6840, 0xc19a, 0x687f, 0xc19a, 0x21, 0 + .dw 0x68c0, 0xc19a, 0x68ff, 0xc19a, 0x21, 0 + .dw 0x6940, 0xc19a, 0x697f, 0xc19a, 0x21, 0 + .dw 0x69c0, 0xc19a, 0x69ff, 0xc19a, 0x21, 0 + .dw 0x6a40, 0xc19a, 0x6a7f, 0xc19a, 0x21, 0 + .dw 0x6ac0, 0xc19a, 0x6aff, 0xc19a, 0x21, 0 + .dw 0x6b40, 0xc19a, 0x6b7f, 0xc19a, 0x21, 0 + .dw 0x6bc0, 0xc19a, 0x6bff, 0xc19a, 0x21, 0 + .dw 0x6c40, 0xc19a, 0x6c7f, 0xc19a, 0x21, 0 + .dw 0x6cc0, 0xc19a, 0x6cff, 0xc19a, 0x21, 0 + .dw 0x6d40, 0xc19a, 0x6d7f, 0xc19a, 0x21, 0 + .dw 0x6dc0, 0xc19a, 0x6dff, 0xc19a, 0x21, 0 + .dw 0x6e40, 0xc19a, 0x6e7f, 0xc19a, 0x21, 0 + .dw 0x6ec0, 0xc19a, 0x6eff, 0xc19a, 0x21, 0 + .dw 0x6f40, 0xc19a, 0x6f7f, 0xc19a, 0x21, 0 + .dw 0x6fc0, 0xc19a, 0x6fff, 0xc19a, 0x21, 0 + .dw 0x7040, 0xc19a, 0x707f, 0xc19a, 0x21, 0 + .dw 0x70c0, 0xc19a, 0x70ff, 0xc19a, 0x21, 0 + .dw 0x7140, 0xc19a, 0x717f, 0xc19a, 0x21, 0 + .dw 0x71c0, 0xc19a, 0x71ff, 0xc19a, 0x21, 0 + .dw 0x7240, 0xc19a, 0x727f, 0xc19a, 0x21, 0 + .dw 0x72c0, 0xc19a, 0x72ff, 0xc19a, 0x21, 0 + .dw 0x7340, 0xc19a, 0x737f, 0xc19a, 0x21, 0 + .dw 0x73c0, 0xc19a, 0x73ff, 0xc19a, 0x21, 0 + .dw 0x7440, 0xc19a, 0x747f, 0xc19a, 0x21, 0 + .dw 0x74c0, 0xc19a, 0x74ff, 0xc19a, 0x21, 0 + .dw 0x7540, 0xc19a, 0x757f, 0xc19a, 0x21, 0 + .dw 0x75c0, 0xc19a, 0x75ff, 0xc19a, 0x21, 0 + .dw 0x7640, 0xc19a, 0x767f, 0xc19a, 0x21, 0 + .dw 0x76c0, 0xc19a, 0x76ff, 0xc19a, 0x21, 0 + .dw 0x7740, 0xc19a, 0x777f, 0xc19a, 0x21, 0 + .dw 0x77c0, 0xc19a, 0x77ff, 0xc19a, 0x21, 0 + .dw 0x7840, 0xc19a, 0x787f, 0xc19a, 0x21, 0 + .dw 0x78c0, 0xc19a, 0x78ff, 0xc19a, 0x21, 0 + .dw 0x7940, 0xc19a, 0x797f, 0xc19a, 0x21, 0 + .dw 0x79c0, 0xc19a, 0x9fff, 0xc19a, 0x21, 0 + .dw 0xa040, 0xc19a, 0xa07f, 0xc19a, 0x21, 0 + .dw 0xa0c0, 0xc19a, 0xa0ff, 0xc19a, 0x21, 0 + .dw 0xa140, 0xc19a, 0xa17f, 0xc19a, 0x21, 0 + .dw 0xa1c0, 0xc19a, 0xa1ff, 0xc19a, 0x21, 0 + .dw 0xa240, 0xc19a, 0xa27f, 0xc19a, 0x21, 0 + .dw 0xa2c0, 0xc19a, 0xa2ff, 0xc19a, 0x21, 0 + .dw 0xa340, 0xc19a, 0xa37f, 0xc19a, 0x21, 0 + .dw 0xa3c0, 0xc19a, 0xa3ff, 0xc19a, 0x21, 0 + .dw 0xa440, 0xc19a, 0xa47f, 0xc19a, 0x21, 0 + .dw 0xa4c0, 0xc19a, 0xa4ff, 0xc19a, 0x21, 0 + .dw 0xa540, 0xc19a, 0xa57f, 0xc19a, 0x21, 0 + .dw 0xa5c0, 0xc19a, 0xa5ff, 0xc19a, 0x21, 0 + .dw 0xa640, 0xc19a, 0xa67f, 0xc19a, 0x21, 0 + .dw 0xa6c0, 0xc19a, 0xa6ff, 0xc19a, 0x21, 0 + .dw 0xa740, 0xc19a, 0xa77f, 0xc19a, 0x21, 0 + .dw 0xa7c0, 0xc19a, 0xa7ff, 0xc19a, 0x21, 0 + .dw 0xa840, 0xc19a, 0xa87f, 0xc19a, 0x21, 0 + .dw 0xa8c0, 0xc19a, 0xa8ff, 0xc19a, 0x21, 0 + .dw 0xa940, 0xc19a, 0xa97f, 0xc19a, 0x21, 0 + .dw 0xa9c0, 0xc19a, 0xa9ff, 0xc19a, 0x21, 0 + .dw 0xaa40, 0xc19a, 0xaa7f, 0xc19a, 0x21, 0 + .dw 0xaac0, 0xc19a, 0xaaff, 0xc19a, 0x21, 0 + .dw 0xab40, 0xc19a, 0xab7f, 0xc19a, 0x21, 0 + .dw 0xabc0, 0xc19a, 0xabff, 0xc19a, 0x21, 0 + .dw 0xac40, 0xc19a, 0xac7f, 0xc19a, 0x21, 0 + .dw 0xacc0, 0xc19a, 0xacff, 0xc19a, 0x21, 0 + .dw 0xad40, 0xc19a, 0xad7f, 0xc19a, 0x21, 0 + .dw 0xadc0, 0xc19a, 0xadff, 0xc19a, 0x21, 0 + .dw 0xae40, 0xc19a, 0xae7f, 0xc19a, 0x21, 0 + .dw 0xaec0, 0xc19a, 0xaeff, 0xc19a, 0x21, 0 + .dw 0xaf40, 0xc19a, 0xaf7f, 0xc19a, 0x21, 0 + .dw 0xafc0, 0xc19a, 0xafff, 0xc19a, 0x21, 0 + .dw 0xb040, 0xc19a, 0xb07f, 0xc19a, 0x21, 0 + .dw 0xb0c0, 0xc19a, 0xb0ff, 0xc19a, 0x21, 0 + .dw 0xb140, 0xc19a, 0xb17f, 0xc19a, 0x21, 0 + .dw 0xb1c0, 0xc19a, 0xb1ff, 0xc19a, 0x21, 0 + .dw 0xb240, 0xc19a, 0xb27f, 0xc19a, 0x21, 0 + .dw 0xb2c0, 0xc19a, 0xb2ff, 0xc19a, 0x21, 0 + .dw 0xb340, 0xc19a, 0xb37f, 0xc19a, 0x21, 0 + .dw 0xb3c0, 0xc19a, 0xb3ff, 0xc19a, 0x21, 0 + .dw 0xb440, 0xc19a, 0xb47f, 0xc19a, 0x21, 0 + .dw 0xb4c0, 0xc19a, 0xb4ff, 0xc19a, 0x21, 0 + .dw 0xb540, 0xc19a, 0xb57f, 0xc19a, 0x21, 0 + .dw 0xb5c0, 0xc19a, 0xb5ff, 0xc19a, 0x21, 0 + .dw 0xb640, 0xc19a, 0xb67f, 0xc19a, 0x21, 0 + .dw 0xb6c0, 0xc19a, 0xb6ff, 0xc19a, 0x21, 0 + .dw 0xb740, 0xc19a, 0xb77f, 0xc19a, 0x21, 0 + .dw 0xb7c0, 0xc19a, 0xb7ff, 0xc19a, 0x21, 0 + .dw 0xb840, 0xc19a, 0xb87f, 0xc19a, 0x21, 0 + .dw 0xb8c0, 0xc19a, 0xb8ff, 0xc19a, 0x21, 0 + .dw 0xb940, 0xc19a, 0xb97f, 0xc19a, 0x21, 0 + .dw 0xb9c0, 0xc19a, 0xdfff, 0xc19a, 0x21, 0 + .dw 0xe040, 0xc19a, 0xe07f, 0xc19a, 0x21, 0 + .dw 0xe0c0, 0xc19a, 0xe0ff, 0xc19a, 0x21, 0 + .dw 0xe140, 0xc19a, 0xe17f, 0xc19a, 0x21, 0 + .dw 0xe1c0, 0xc19a, 0xe1ff, 0xc19a, 0x21, 0 + .dw 0xe240, 0xc19a, 0xe27f, 0xc19a, 0x21, 0 + .dw 0xe2c0, 0xc19a, 0xe2ff, 0xc19a, 0x21, 0 + .dw 0xe340, 0xc19a, 0xe37f, 0xc19a, 0x21, 0 + .dw 0xe3c0, 0xc19a, 0xe3ff, 0xc19a, 0x21, 0 + .dw 0xe440, 0xc19a, 0xe47f, 0xc19a, 0x21, 0 + .dw 0xe4c0, 0xc19a, 0xe4ff, 0xc19a, 0x21, 0 + .dw 0xe540, 0xc19a, 0xe57f, 0xc19a, 0x21, 0 + .dw 0xe5c0, 0xc19a, 0xe5ff, 0xc19a, 0x21, 0 + .dw 0xe640, 0xc19a, 0xe67f, 0xc19a, 0x21, 0 + .dw 0xe6c0, 0xc19a, 0xe6ff, 0xc19a, 0x21, 0 + .dw 0xe740, 0xc19a, 0xe77f, 0xc19a, 0x21, 0 + .dw 0xe7c0, 0xc19a, 0xe7ff, 0xc19a, 0x21, 0 + .dw 0xe840, 0xc19a, 0xe87f, 0xc19a, 0x21, 0 + .dw 0xe8c0, 0xc19a, 0xe8ff, 0xc19a, 0x21, 0 + .dw 0xe940, 0xc19a, 0xe97f, 0xc19a, 0x21, 0 + .dw 0xe9c0, 0xc19a, 0xe9ff, 0xc19a, 0x21, 0 + .dw 0xea40, 0xc19a, 0xea7f, 0xc19a, 0x21, 0 + .dw 0xeac0, 0xc19a, 0xeaff, 0xc19a, 0x21, 0 + .dw 0xeb40, 0xc19a, 0xeb7f, 0xc19a, 0x21, 0 + .dw 0xebc0, 0xc19a, 0xebff, 0xc19a, 0x21, 0 + .dw 0xec40, 0xc19a, 0xec7f, 0xc19a, 0x21, 0 + .dw 0xecc0, 0xc19a, 0xecff, 0xc19a, 0x21, 0 + .dw 0xed40, 0xc19a, 0xed7f, 0xc19a, 0x21, 0 + .dw 0xedc0, 0xc19a, 0xedff, 0xc19a, 0x21, 0 + .dw 0xee40, 0xc19a, 0xee7f, 0xc19a, 0x21, 0 + .dw 0xeec0, 0xc19a, 0xeeff, 0xc19a, 0x21, 0 + .dw 0xef40, 0xc19a, 0xef7f, 0xc19a, 0x21, 0 + .dw 0xefc0, 0xc19a, 0xefff, 0xc19a, 0x21, 0 + .dw 0xf040, 0xc19a, 0xf07f, 0xc19a, 0x21, 0 + .dw 0xf0c0, 0xc19a, 0xf0ff, 0xc19a, 0x21, 0 + .dw 0xf140, 0xc19a, 0xf17f, 0xc19a, 0x21, 0 + .dw 0xf1c0, 0xc19a, 0xf1ff, 0xc19a, 0x21, 0 + .dw 0xf240, 0xc19a, 0xf27f, 0xc19a, 0x21, 0 + .dw 0xf2c0, 0xc19a, 0xf2ff, 0xc19a, 0x21, 0 + .dw 0xf340, 0xc19a, 0xf37f, 0xc19a, 0x21, 0 + .dw 0xf3c0, 0xc19a, 0xf3ff, 0xc19a, 0x21, 0 + .dw 0xf440, 0xc19a, 0xf47f, 0xc19a, 0x21, 0 + .dw 0xf4c0, 0xc19a, 0xf4ff, 0xc19a, 0x21, 0 + .dw 0xf540, 0xc19a, 0xf57f, 0xc19a, 0x21, 0 + .dw 0xf5c0, 0xc19a, 0xf5ff, 0xc19a, 0x21, 0 + .dw 0xf640, 0xc19a, 0xf67f, 0xc19a, 0x21, 0 + .dw 0xf6c0, 0xc19a, 0xf6ff, 0xc19a, 0x21, 0 + .dw 0xf740, 0xc19a, 0xf77f, 0xc19a, 0x21, 0 + .dw 0xf7c0, 0xc19a, 0xf7ff, 0xc19a, 0x21, 0 + .dw 0xf840, 0xc19a, 0xf87f, 0xc19a, 0x21, 0 + .dw 0xf8c0, 0xc19a, 0xf8ff, 0xc19a, 0x21, 0 + .dw 0xf940, 0xc19a, 0xf97f, 0xc19a, 0x21, 0 + .dw 0xf9c0, 0xc19a, 0xffff, 0xc19b, 0x21, 0 + .dw 0x0040, 0xc19c, 0x007f, 0xc19c, 0x21, 0 + .dw 0x00c0, 0xc19c, 0x00ff, 0xc19c, 0x21, 0 + .dw 0x0140, 0xc19c, 0x017f, 0xc19c, 0x21, 0 + .dw 0x01c0, 0xc19c, 0x01ff, 0xc19c, 0x21, 0 + .dw 0x0240, 0xc19c, 0x027f, 0xc19c, 0x21, 0 + .dw 0x02c0, 0xc19c, 0x02ff, 0xc19c, 0x21, 0 + .dw 0x0340, 0xc19c, 0x037f, 0xc19c, 0x21, 0 + .dw 0x03c0, 0xc19c, 0x03ff, 0xc19c, 0x21, 0 + .dw 0x0440, 0xc19c, 0x047f, 0xc19c, 0x21, 0 + .dw 0x04c0, 0xc19c, 0x04ff, 0xc19c, 0x21, 0 + .dw 0x0540, 0xc19c, 0x057f, 0xc19c, 0x21, 0 + .dw 0x05c0, 0xc19c, 0x05ff, 0xc19c, 0x21, 0 + .dw 0x0640, 0xc19c, 0x067f, 0xc19c, 0x21, 0 + .dw 0x06c0, 0xc19c, 0x06ff, 0xc19c, 0x21, 0 + .dw 0x0740, 0xc19c, 0x077f, 0xc19c, 0x21, 0 + .dw 0x07c0, 0xc19c, 0x07ff, 0xc19c, 0x21, 0 + .dw 0x0840, 0xc19c, 0x087f, 0xc19c, 0x21, 0 + .dw 0x08c0, 0xc19c, 0x08ff, 0xc19c, 0x21, 0 + .dw 0x0940, 0xc19c, 0x097f, 0xc19c, 0x21, 0 + .dw 0x09c0, 0xc19c, 0x09ff, 0xc19c, 0x21, 0 + .dw 0x0a40, 0xc19c, 0x0a7f, 0xc19c, 0x21, 0 + .dw 0x0ac0, 0xc19c, 0x0aff, 0xc19c, 0x21, 0 + .dw 0x0b40, 0xc19c, 0x0b7f, 0xc19c, 0x21, 0 + .dw 0x0bc0, 0xc19c, 0x0bff, 0xc19c, 0x21, 0 + .dw 0x0c40, 0xc19c, 0x0c7f, 0xc19c, 0x21, 0 + .dw 0x0cc0, 0xc19c, 0x0cff, 0xc19c, 0x21, 0 + .dw 0x0d40, 0xc19c, 0x0d7f, 0xc19c, 0x21, 0 + .dw 0x0dc0, 0xc19c, 0x0dff, 0xc19c, 0x21, 0 + .dw 0x0e40, 0xc19c, 0x0e7f, 0xc19c, 0x21, 0 + .dw 0x0ec0, 0xc19c, 0x0eff, 0xc19c, 0x21, 0 + .dw 0x0f40, 0xc19c, 0x0f7f, 0xc19c, 0x21, 0 + .dw 0x0fc0, 0xc19c, 0x0fff, 0xc19c, 0x21, 0 + .dw 0x1040, 0xc19c, 0x107f, 0xc19c, 0x21, 0 + .dw 0x10c0, 0xc19c, 0x10ff, 0xc19c, 0x21, 0 + .dw 0x1140, 0xc19c, 0x117f, 0xc19c, 0x21, 0 + .dw 0x11c0, 0xc19c, 0x11ff, 0xc19c, 0x21, 0 + .dw 0x1240, 0xc19c, 0x127f, 0xc19c, 0x21, 0 + .dw 0x12c0, 0xc19c, 0x12ff, 0xc19c, 0x21, 0 + .dw 0x1340, 0xc19c, 0x137f, 0xc19c, 0x21, 0 + .dw 0x13c0, 0xc19c, 0x13ff, 0xc19c, 0x21, 0 + .dw 0x1440, 0xc19c, 0x147f, 0xc19c, 0x21, 0 + .dw 0x14c0, 0xc19c, 0x14ff, 0xc19c, 0x21, 0 + .dw 0x1540, 0xc19c, 0x157f, 0xc19c, 0x21, 0 + .dw 0x15c0, 0xc19c, 0x15ff, 0xc19c, 0x21, 0 + .dw 0x1640, 0xc19c, 0x167f, 0xc19c, 0x21, 0 + .dw 0x16c0, 0xc19c, 0x16ff, 0xc19c, 0x21, 0 + .dw 0x1740, 0xc19c, 0x177f, 0xc19c, 0x21, 0 + .dw 0x17c0, 0xc19c, 0x17ff, 0xc19c, 0x21, 0 + .dw 0x1840, 0xc19c, 0x187f, 0xc19c, 0x21, 0 + .dw 0x18c0, 0xc19c, 0x18ff, 0xc19c, 0x21, 0 + .dw 0x1940, 0xc19c, 0x197f, 0xc19c, 0x21, 0 + .dw 0x19c0, 0xc19c, 0x1fff, 0xc19c, 0x21, 0 + .dw 0x2040, 0xc19c, 0x207f, 0xc19c, 0x21, 0 + .dw 0x20c0, 0xc19c, 0x20ff, 0xc19c, 0x21, 0 + .dw 0x2140, 0xc19c, 0x217f, 0xc19c, 0x21, 0 + .dw 0x21c0, 0xc19c, 0x21ff, 0xc19c, 0x21, 0 + .dw 0x2240, 0xc19c, 0x227f, 0xc19c, 0x21, 0 + .dw 0x22c0, 0xc19c, 0x22ff, 0xc19c, 0x21, 0 + .dw 0x2340, 0xc19c, 0x237f, 0xc19c, 0x21, 0 + .dw 0x23c0, 0xc19c, 0x23ff, 0xc19c, 0x21, 0 + .dw 0x2440, 0xc19c, 0x247f, 0xc19c, 0x21, 0 + .dw 0x24c0, 0xc19c, 0x24ff, 0xc19c, 0x21, 0 + .dw 0x2540, 0xc19c, 0x257f, 0xc19c, 0x21, 0 + .dw 0x25c0, 0xc19c, 0x25ff, 0xc19c, 0x21, 0 + .dw 0x2640, 0xc19c, 0x267f, 0xc19c, 0x21, 0 + .dw 0x26c0, 0xc19c, 0x26ff, 0xc19c, 0x21, 0 + .dw 0x2740, 0xc19c, 0x277f, 0xc19c, 0x21, 0 + .dw 0x27c0, 0xc19c, 0x27ff, 0xc19c, 0x21, 0 + .dw 0x2840, 0xc19c, 0x287f, 0xc19c, 0x21, 0 + .dw 0x28c0, 0xc19c, 0x28ff, 0xc19c, 0x21, 0 + .dw 0x2940, 0xc19c, 0x297f, 0xc19c, 0x21, 0 + .dw 0x29c0, 0xc19c, 0x29ff, 0xc19c, 0x21, 0 + .dw 0x2a40, 0xc19c, 0x2a7f, 0xc19c, 0x21, 0 + .dw 0x2ac0, 0xc19c, 0x2aff, 0xc19c, 0x21, 0 + .dw 0x2b40, 0xc19c, 0x2b7f, 0xc19c, 0x21, 0 + .dw 0x2bc0, 0xc19c, 0x2bff, 0xc19c, 0x21, 0 + .dw 0x2c40, 0xc19c, 0x2c7f, 0xc19c, 0x21, 0 + .dw 0x2cc0, 0xc19c, 0x2cff, 0xc19c, 0x21, 0 + .dw 0x2d40, 0xc19c, 0x2d7f, 0xc19c, 0x21, 0 + .dw 0x2dc0, 0xc19c, 0x2dff, 0xc19c, 0x21, 0 + .dw 0x2e40, 0xc19c, 0x2e7f, 0xc19c, 0x21, 0 + .dw 0x2ec0, 0xc19c, 0x2eff, 0xc19c, 0x21, 0 + .dw 0x2f40, 0xc19c, 0x2f7f, 0xc19c, 0x21, 0 + .dw 0x2fc0, 0xc19c, 0x2fff, 0xc19c, 0x21, 0 + .dw 0x3040, 0xc19c, 0x307f, 0xc19c, 0x21, 0 + .dw 0x30c0, 0xc19c, 0x30ff, 0xc19c, 0x21, 0 + .dw 0x3140, 0xc19c, 0x317f, 0xc19c, 0x21, 0 + .dw 0x31c0, 0xc19c, 0x31ff, 0xc19c, 0x21, 0 + .dw 0x3240, 0xc19c, 0x327f, 0xc19c, 0x21, 0 + .dw 0x32c0, 0xc19c, 0x32ff, 0xc19c, 0x21, 0 + .dw 0x3340, 0xc19c, 0x337f, 0xc19c, 0x21, 0 + .dw 0x33c0, 0xc19c, 0x33ff, 0xc19c, 0x21, 0 + .dw 0x3440, 0xc19c, 0x347f, 0xc19c, 0x21, 0 + .dw 0x34c0, 0xc19c, 0x34ff, 0xc19c, 0x21, 0 + .dw 0x3540, 0xc19c, 0x357f, 0xc19c, 0x21, 0 + .dw 0x35c0, 0xc19c, 0x35ff, 0xc19c, 0x21, 0 + .dw 0x3640, 0xc19c, 0x367f, 0xc19c, 0x21, 0 + .dw 0x36c0, 0xc19c, 0x36ff, 0xc19c, 0x21, 0 + .dw 0x3740, 0xc19c, 0x377f, 0xc19c, 0x21, 0 + .dw 0x37c0, 0xc19c, 0x37ff, 0xc19c, 0x21, 0 + .dw 0x3840, 0xc19c, 0x387f, 0xc19c, 0x21, 0 + .dw 0x38c0, 0xc19c, 0x38ff, 0xc19c, 0x21, 0 + .dw 0x3940, 0xc19c, 0x397f, 0xc19c, 0x21, 0 + .dw 0x39c0, 0xc19c, 0x3fff, 0xc19c, 0x21, 0 + .dw 0x4040, 0xc19c, 0x407f, 0xc19c, 0x21, 0 + .dw 0x40c0, 0xc19c, 0x40ff, 0xc19c, 0x21, 0 + .dw 0x4140, 0xc19c, 0x417f, 0xc19c, 0x21, 0 + .dw 0x41c0, 0xc19c, 0x41ff, 0xc19c, 0x21, 0 + .dw 0x4240, 0xc19c, 0x427f, 0xc19c, 0x21, 0 + .dw 0x42c0, 0xc19c, 0x42ff, 0xc19c, 0x21, 0 + .dw 0x4340, 0xc19c, 0x437f, 0xc19c, 0x21, 0 + .dw 0x43c0, 0xc19c, 0x43ff, 0xc19c, 0x21, 0 + .dw 0x4440, 0xc19c, 0x447f, 0xc19c, 0x21, 0 + .dw 0x44c0, 0xc19c, 0x44ff, 0xc19c, 0x21, 0 + .dw 0x4540, 0xc19c, 0x457f, 0xc19c, 0x21, 0 + .dw 0x45c0, 0xc19c, 0x45ff, 0xc19c, 0x21, 0 + .dw 0x4640, 0xc19c, 0x467f, 0xc19c, 0x21, 0 + .dw 0x46c0, 0xc19c, 0x46ff, 0xc19c, 0x21, 0 + .dw 0x4740, 0xc19c, 0x477f, 0xc19c, 0x21, 0 + .dw 0x47c0, 0xc19c, 0x47ff, 0xc19c, 0x21, 0 + .dw 0x4840, 0xc19c, 0x487f, 0xc19c, 0x21, 0 + .dw 0x48c0, 0xc19c, 0x48ff, 0xc19c, 0x21, 0 + .dw 0x4940, 0xc19c, 0x497f, 0xc19c, 0x21, 0 + .dw 0x49c0, 0xc19c, 0x49ff, 0xc19c, 0x21, 0 + .dw 0x4a40, 0xc19c, 0x4a7f, 0xc19c, 0x21, 0 + .dw 0x4ac0, 0xc19c, 0x4aff, 0xc19c, 0x21, 0 + .dw 0x4b40, 0xc19c, 0x4b7f, 0xc19c, 0x21, 0 + .dw 0x4bc0, 0xc19c, 0x4bff, 0xc19c, 0x21, 0 + .dw 0x4c40, 0xc19c, 0x4c7f, 0xc19c, 0x21, 0 + .dw 0x4cc0, 0xc19c, 0x4cff, 0xc19c, 0x21, 0 + .dw 0x4d40, 0xc19c, 0x4d7f, 0xc19c, 0x21, 0 + .dw 0x4dc0, 0xc19c, 0x4dff, 0xc19c, 0x21, 0 + .dw 0x4e40, 0xc19c, 0x4e7f, 0xc19c, 0x21, 0 + .dw 0x4ec0, 0xc19c, 0x4eff, 0xc19c, 0x21, 0 + .dw 0x4f40, 0xc19c, 0x4f7f, 0xc19c, 0x21, 0 + .dw 0x4fc0, 0xc19c, 0x4fff, 0xc19c, 0x21, 0 + .dw 0x5040, 0xc19c, 0x507f, 0xc19c, 0x21, 0 + .dw 0x50c0, 0xc19c, 0x50ff, 0xc19c, 0x21, 0 + .dw 0x5140, 0xc19c, 0x517f, 0xc19c, 0x21, 0 + .dw 0x51c0, 0xc19c, 0x51ff, 0xc19c, 0x21, 0 + .dw 0x5240, 0xc19c, 0x527f, 0xc19c, 0x21, 0 + .dw 0x52c0, 0xc19c, 0x52ff, 0xc19c, 0x21, 0 + .dw 0x5340, 0xc19c, 0x537f, 0xc19c, 0x21, 0 + .dw 0x53c0, 0xc19c, 0x53ff, 0xc19c, 0x21, 0 + .dw 0x5440, 0xc19c, 0x547f, 0xc19c, 0x21, 0 + .dw 0x54c0, 0xc19c, 0x54ff, 0xc19c, 0x21, 0 + .dw 0x5540, 0xc19c, 0x557f, 0xc19c, 0x21, 0 + .dw 0x55c0, 0xc19c, 0x55ff, 0xc19c, 0x21, 0 + .dw 0x5640, 0xc19c, 0x567f, 0xc19c, 0x21, 0 + .dw 0x56c0, 0xc19c, 0x56ff, 0xc19c, 0x21, 0 + .dw 0x5740, 0xc19c, 0x577f, 0xc19c, 0x21, 0 + .dw 0x57c0, 0xc19c, 0x57ff, 0xc19c, 0x21, 0 + .dw 0x5840, 0xc19c, 0x587f, 0xc19c, 0x21, 0 + .dw 0x58c0, 0xc19c, 0x58ff, 0xc19c, 0x21, 0 + .dw 0x5940, 0xc19c, 0x597f, 0xc19c, 0x21, 0 + .dw 0x59c0, 0xc19c, 0x5fff, 0xc19c, 0x21, 0 + .dw 0x6040, 0xc19c, 0x607f, 0xc19c, 0x21, 0 + .dw 0x60c0, 0xc19c, 0x60ff, 0xc19c, 0x21, 0 + .dw 0x6140, 0xc19c, 0x617f, 0xc19c, 0x21, 0 + .dw 0x61c0, 0xc19c, 0x61ff, 0xc19c, 0x21, 0 + .dw 0x6240, 0xc19c, 0x627f, 0xc19c, 0x21, 0 + .dw 0x62c0, 0xc19c, 0x62ff, 0xc19c, 0x21, 0 + .dw 0x6340, 0xc19c, 0x637f, 0xc19c, 0x21, 0 + .dw 0x63c0, 0xc19c, 0x63ff, 0xc19c, 0x21, 0 + .dw 0x6440, 0xc19c, 0x647f, 0xc19c, 0x21, 0 + .dw 0x64c0, 0xc19c, 0x64ff, 0xc19c, 0x21, 0 + .dw 0x6540, 0xc19c, 0x657f, 0xc19c, 0x21, 0 + .dw 0x65c0, 0xc19c, 0x65ff, 0xc19c, 0x21, 0 + .dw 0x6640, 0xc19c, 0x667f, 0xc19c, 0x21, 0 + .dw 0x66c0, 0xc19c, 0x66ff, 0xc19c, 0x21, 0 + .dw 0x6740, 0xc19c, 0x677f, 0xc19c, 0x21, 0 + .dw 0x67c0, 0xc19c, 0x67ff, 0xc19c, 0x21, 0 + .dw 0x6840, 0xc19c, 0x687f, 0xc19c, 0x21, 0 + .dw 0x68c0, 0xc19c, 0x68ff, 0xc19c, 0x21, 0 + .dw 0x6940, 0xc19c, 0x697f, 0xc19c, 0x21, 0 + .dw 0x69c0, 0xc19c, 0x69ff, 0xc19c, 0x21, 0 + .dw 0x6a40, 0xc19c, 0x6a7f, 0xc19c, 0x21, 0 + .dw 0x6ac0, 0xc19c, 0x6aff, 0xc19c, 0x21, 0 + .dw 0x6b40, 0xc19c, 0x6b7f, 0xc19c, 0x21, 0 + .dw 0x6bc0, 0xc19c, 0x6bff, 0xc19c, 0x21, 0 + .dw 0x6c40, 0xc19c, 0x6c7f, 0xc19c, 0x21, 0 + .dw 0x6cc0, 0xc19c, 0x6cff, 0xc19c, 0x21, 0 + .dw 0x6d40, 0xc19c, 0x6d7f, 0xc19c, 0x21, 0 + .dw 0x6dc0, 0xc19c, 0x6dff, 0xc19c, 0x21, 0 + .dw 0x6e40, 0xc19c, 0x6e7f, 0xc19c, 0x21, 0 + .dw 0x6ec0, 0xc19c, 0x6eff, 0xc19c, 0x21, 0 + .dw 0x6f40, 0xc19c, 0x6f7f, 0xc19c, 0x21, 0 + .dw 0x6fc0, 0xc19c, 0x6fff, 0xc19c, 0x21, 0 + .dw 0x7040, 0xc19c, 0x707f, 0xc19c, 0x21, 0 + .dw 0x70c0, 0xc19c, 0x70ff, 0xc19c, 0x21, 0 + .dw 0x7140, 0xc19c, 0x717f, 0xc19c, 0x21, 0 + .dw 0x71c0, 0xc19c, 0x71ff, 0xc19c, 0x21, 0 + .dw 0x7240, 0xc19c, 0x727f, 0xc19c, 0x21, 0 + .dw 0x72c0, 0xc19c, 0x72ff, 0xc19c, 0x21, 0 + .dw 0x7340, 0xc19c, 0x737f, 0xc19c, 0x21, 0 + .dw 0x73c0, 0xc19c, 0x73ff, 0xc19c, 0x21, 0 + .dw 0x7440, 0xc19c, 0x747f, 0xc19c, 0x21, 0 + .dw 0x74c0, 0xc19c, 0x74ff, 0xc19c, 0x21, 0 + .dw 0x7540, 0xc19c, 0x757f, 0xc19c, 0x21, 0 + .dw 0x75c0, 0xc19c, 0x75ff, 0xc19c, 0x21, 0 + .dw 0x7640, 0xc19c, 0x767f, 0xc19c, 0x21, 0 + .dw 0x76c0, 0xc19c, 0x76ff, 0xc19c, 0x21, 0 + .dw 0x7740, 0xc19c, 0x777f, 0xc19c, 0x21, 0 + .dw 0x77c0, 0xc19c, 0x77ff, 0xc19c, 0x21, 0 + .dw 0x7840, 0xc19c, 0x787f, 0xc19c, 0x21, 0 + .dw 0x78c0, 0xc19c, 0x78ff, 0xc19c, 0x21, 0 + .dw 0x7940, 0xc19c, 0x797f, 0xc19c, 0x21, 0 + .dw 0x79c0, 0xc19c, 0x7fff, 0xc19c, 0x21, 0 + .dw 0x8040, 0xc19c, 0x807f, 0xc19c, 0x21, 0 + .dw 0x80c0, 0xc19c, 0x80ff, 0xc19c, 0x21, 0 + .dw 0x8140, 0xc19c, 0x817f, 0xc19c, 0x21, 0 + .dw 0x81c0, 0xc19c, 0x81ff, 0xc19c, 0x21, 0 + .dw 0x8240, 0xc19c, 0x827f, 0xc19c, 0x21, 0 + .dw 0x82c0, 0xc19c, 0x82ff, 0xc19c, 0x21, 0 + .dw 0x8340, 0xc19c, 0x837f, 0xc19c, 0x21, 0 + .dw 0x83c0, 0xc19c, 0x83ff, 0xc19c, 0x21, 0 + .dw 0x8440, 0xc19c, 0x847f, 0xc19c, 0x21, 0 + .dw 0x84c0, 0xc19c, 0x84ff, 0xc19c, 0x21, 0 + .dw 0x8540, 0xc19c, 0x857f, 0xc19c, 0x21, 0 + .dw 0x85c0, 0xc19c, 0x85ff, 0xc19c, 0x21, 0 + .dw 0x8640, 0xc19c, 0x867f, 0xc19c, 0x21, 0 + .dw 0x86c0, 0xc19c, 0x86ff, 0xc19c, 0x21, 0 + .dw 0x8740, 0xc19c, 0x877f, 0xc19c, 0x21, 0 + .dw 0x87c0, 0xc19c, 0x87ff, 0xc19c, 0x21, 0 + .dw 0x8840, 0xc19c, 0x887f, 0xc19c, 0x21, 0 + .dw 0x88c0, 0xc19c, 0x88ff, 0xc19c, 0x21, 0 + .dw 0x8940, 0xc19c, 0x897f, 0xc19c, 0x21, 0 + .dw 0x89c0, 0xc19c, 0x89ff, 0xc19c, 0x21, 0 + .dw 0x8a40, 0xc19c, 0x8a7f, 0xc19c, 0x21, 0 + .dw 0x8ac0, 0xc19c, 0x8aff, 0xc19c, 0x21, 0 + .dw 0x8b40, 0xc19c, 0x8b7f, 0xc19c, 0x21, 0 + .dw 0x8bc0, 0xc19c, 0x8bff, 0xc19c, 0x21, 0 + .dw 0x8c40, 0xc19c, 0x8c7f, 0xc19c, 0x21, 0 + .dw 0x8cc0, 0xc19c, 0x8cff, 0xc19c, 0x21, 0 + .dw 0x8d40, 0xc19c, 0x8d7f, 0xc19c, 0x21, 0 + .dw 0x8dc0, 0xc19c, 0x8dff, 0xc19c, 0x21, 0 + .dw 0x8e40, 0xc19c, 0x8e7f, 0xc19c, 0x21, 0 + .dw 0x8ec0, 0xc19c, 0x8eff, 0xc19c, 0x21, 0 + .dw 0x8f40, 0xc19c, 0x8f7f, 0xc19c, 0x21, 0 + .dw 0x8fc0, 0xc19c, 0x8fff, 0xc19c, 0x21, 0 + .dw 0x9040, 0xc19c, 0x907f, 0xc19c, 0x21, 0 + .dw 0x90c0, 0xc19c, 0x90ff, 0xc19c, 0x21, 0 + .dw 0x9140, 0xc19c, 0x917f, 0xc19c, 0x21, 0 + .dw 0x91c0, 0xc19c, 0x91ff, 0xc19c, 0x21, 0 + .dw 0x9240, 0xc19c, 0x927f, 0xc19c, 0x21, 0 + .dw 0x92c0, 0xc19c, 0x92ff, 0xc19c, 0x21, 0 + .dw 0x9340, 0xc19c, 0x937f, 0xc19c, 0x21, 0 + .dw 0x93c0, 0xc19c, 0x93ff, 0xc19c, 0x21, 0 + .dw 0x9440, 0xc19c, 0x947f, 0xc19c, 0x21, 0 + .dw 0x94c0, 0xc19c, 0x94ff, 0xc19c, 0x21, 0 + .dw 0x9540, 0xc19c, 0x957f, 0xc19c, 0x21, 0 + .dw 0x95c0, 0xc19c, 0x95ff, 0xc19c, 0x21, 0 + .dw 0x9640, 0xc19c, 0x967f, 0xc19c, 0x21, 0 + .dw 0x96c0, 0xc19c, 0x96ff, 0xc19c, 0x21, 0 + .dw 0x9740, 0xc19c, 0x977f, 0xc19c, 0x21, 0 + .dw 0x97c0, 0xc19c, 0x97ff, 0xc19c, 0x21, 0 + .dw 0x9840, 0xc19c, 0x987f, 0xc19c, 0x21, 0 + .dw 0x98c0, 0xc19c, 0x98ff, 0xc19c, 0x21, 0 + .dw 0x9940, 0xc19c, 0x997f, 0xc19c, 0x21, 0 + .dw 0x99c0, 0xc19c, 0x9fff, 0xc19c, 0x21, 0 + .dw 0xa040, 0xc19c, 0xa07f, 0xc19c, 0x21, 0 + .dw 0xa0c0, 0xc19c, 0xa0ff, 0xc19c, 0x21, 0 + .dw 0xa140, 0xc19c, 0xa17f, 0xc19c, 0x21, 0 + .dw 0xa1c0, 0xc19c, 0xa1ff, 0xc19c, 0x21, 0 + .dw 0xa240, 0xc19c, 0xa27f, 0xc19c, 0x21, 0 + .dw 0xa2c0, 0xc19c, 0xa2ff, 0xc19c, 0x21, 0 + .dw 0xa340, 0xc19c, 0xa37f, 0xc19c, 0x21, 0 + .dw 0xa3c0, 0xc19c, 0xa3ff, 0xc19c, 0x21, 0 + .dw 0xa440, 0xc19c, 0xa47f, 0xc19c, 0x21, 0 + .dw 0xa4c0, 0xc19c, 0xa4ff, 0xc19c, 0x21, 0 + .dw 0xa540, 0xc19c, 0xa57f, 0xc19c, 0x21, 0 + .dw 0xa5c0, 0xc19c, 0xa5ff, 0xc19c, 0x21, 0 + .dw 0xa640, 0xc19c, 0xa67f, 0xc19c, 0x21, 0 + .dw 0xa6c0, 0xc19c, 0xa6ff, 0xc19c, 0x21, 0 + .dw 0xa740, 0xc19c, 0xa77f, 0xc19c, 0x21, 0 + .dw 0xa7c0, 0xc19c, 0xa7ff, 0xc19c, 0x21, 0 + .dw 0xa840, 0xc19c, 0xa87f, 0xc19c, 0x21, 0 + .dw 0xa8c0, 0xc19c, 0xa8ff, 0xc19c, 0x21, 0 + .dw 0xa940, 0xc19c, 0xa97f, 0xc19c, 0x21, 0 + .dw 0xa9c0, 0xc19c, 0xa9ff, 0xc19c, 0x21, 0 + .dw 0xaa40, 0xc19c, 0xaa7f, 0xc19c, 0x21, 0 + .dw 0xaac0, 0xc19c, 0xaaff, 0xc19c, 0x21, 0 + .dw 0xab40, 0xc19c, 0xab7f, 0xc19c, 0x21, 0 + .dw 0xabc0, 0xc19c, 0xabff, 0xc19c, 0x21, 0 + .dw 0xac40, 0xc19c, 0xac7f, 0xc19c, 0x21, 0 + .dw 0xacc0, 0xc19c, 0xacff, 0xc19c, 0x21, 0 + .dw 0xad40, 0xc19c, 0xad7f, 0xc19c, 0x21, 0 + .dw 0xadc0, 0xc19c, 0xadff, 0xc19c, 0x21, 0 + .dw 0xae40, 0xc19c, 0xae7f, 0xc19c, 0x21, 0 + .dw 0xaec0, 0xc19c, 0xaeff, 0xc19c, 0x21, 0 + .dw 0xaf40, 0xc19c, 0xaf7f, 0xc19c, 0x21, 0 + .dw 0xafc0, 0xc19c, 0xafff, 0xc19c, 0x21, 0 + .dw 0xb040, 0xc19c, 0xb07f, 0xc19c, 0x21, 0 + .dw 0xb0c0, 0xc19c, 0xb0ff, 0xc19c, 0x21, 0 + .dw 0xb140, 0xc19c, 0xb17f, 0xc19c, 0x21, 0 + .dw 0xb1c0, 0xc19c, 0xb1ff, 0xc19c, 0x21, 0 + .dw 0xb240, 0xc19c, 0xb27f, 0xc19c, 0x21, 0 + .dw 0xb2c0, 0xc19c, 0xb2ff, 0xc19c, 0x21, 0 + .dw 0xb340, 0xc19c, 0xb37f, 0xc19c, 0x21, 0 + .dw 0xb3c0, 0xc19c, 0xb3ff, 0xc19c, 0x21, 0 + .dw 0xb440, 0xc19c, 0xb47f, 0xc19c, 0x21, 0 + .dw 0xb4c0, 0xc19c, 0xb4ff, 0xc19c, 0x21, 0 + .dw 0xb540, 0xc19c, 0xb57f, 0xc19c, 0x21, 0 + .dw 0xb5c0, 0xc19c, 0xb5ff, 0xc19c, 0x21, 0 + .dw 0xb640, 0xc19c, 0xb67f, 0xc19c, 0x21, 0 + .dw 0xb6c0, 0xc19c, 0xb6ff, 0xc19c, 0x21, 0 + .dw 0xb740, 0xc19c, 0xb77f, 0xc19c, 0x21, 0 + .dw 0xb7c0, 0xc19c, 0xb7ff, 0xc19c, 0x21, 0 + .dw 0xb840, 0xc19c, 0xb87f, 0xc19c, 0x21, 0 + .dw 0xb8c0, 0xc19c, 0xb8ff, 0xc19c, 0x21, 0 + .dw 0xb940, 0xc19c, 0xb97f, 0xc19c, 0x21, 0 + .dw 0xb9c0, 0xc19c, 0xbfff, 0xc19c, 0x21, 0 + .dw 0xc040, 0xc19c, 0xc07f, 0xc19c, 0x21, 0 + .dw 0xc0c0, 0xc19c, 0xc0ff, 0xc19c, 0x21, 0 + .dw 0xc140, 0xc19c, 0xc17f, 0xc19c, 0x21, 0 + .dw 0xc1c0, 0xc19c, 0xc1ff, 0xc19c, 0x21, 0 + .dw 0xc240, 0xc19c, 0xc27f, 0xc19c, 0x21, 0 + .dw 0xc2c0, 0xc19c, 0xc2ff, 0xc19c, 0x21, 0 + .dw 0xc340, 0xc19c, 0xc37f, 0xc19c, 0x21, 0 + .dw 0xc3c0, 0xc19c, 0xc3ff, 0xc19c, 0x21, 0 + .dw 0xc440, 0xc19c, 0xc47f, 0xc19c, 0x21, 0 + .dw 0xc4c0, 0xc19c, 0xc4ff, 0xc19c, 0x21, 0 + .dw 0xc540, 0xc19c, 0xc57f, 0xc19c, 0x21, 0 + .dw 0xc5c0, 0xc19c, 0xc5ff, 0xc19c, 0x21, 0 + .dw 0xc640, 0xc19c, 0xc67f, 0xc19c, 0x21, 0 + .dw 0xc6c0, 0xc19c, 0xc6ff, 0xc19c, 0x21, 0 + .dw 0xc740, 0xc19c, 0xc77f, 0xc19c, 0x21, 0 + .dw 0xc7c0, 0xc19c, 0xc7ff, 0xc19c, 0x21, 0 + .dw 0xc840, 0xc19c, 0xc87f, 0xc19c, 0x21, 0 + .dw 0xc8c0, 0xc19c, 0xc8ff, 0xc19c, 0x21, 0 + .dw 0xc940, 0xc19c, 0xc97f, 0xc19c, 0x21, 0 + .dw 0xc9c0, 0xc19c, 0xc9ff, 0xc19c, 0x21, 0 + .dw 0xca40, 0xc19c, 0xca7f, 0xc19c, 0x21, 0 + .dw 0xcac0, 0xc19c, 0xcaff, 0xc19c, 0x21, 0 + .dw 0xcb40, 0xc19c, 0xcb7f, 0xc19c, 0x21, 0 + .dw 0xcbc0, 0xc19c, 0xcbff, 0xc19c, 0x21, 0 + .dw 0xcc40, 0xc19c, 0xcc7f, 0xc19c, 0x21, 0 + .dw 0xccc0, 0xc19c, 0xccff, 0xc19c, 0x21, 0 + .dw 0xcd40, 0xc19c, 0xcd7f, 0xc19c, 0x21, 0 + .dw 0xcdc0, 0xc19c, 0xcdff, 0xc19c, 0x21, 0 + .dw 0xce40, 0xc19c, 0xce7f, 0xc19c, 0x21, 0 + .dw 0xcec0, 0xc19c, 0xceff, 0xc19c, 0x21, 0 + .dw 0xcf40, 0xc19c, 0xcf7f, 0xc19c, 0x21, 0 + .dw 0xcfc0, 0xc19c, 0xcfff, 0xc19c, 0x21, 0 + .dw 0xd040, 0xc19c, 0xd07f, 0xc19c, 0x21, 0 + .dw 0xd0c0, 0xc19c, 0xd0ff, 0xc19c, 0x21, 0 + .dw 0xd140, 0xc19c, 0xd17f, 0xc19c, 0x21, 0 + .dw 0xd1c0, 0xc19c, 0xd1ff, 0xc19c, 0x21, 0 + .dw 0xd240, 0xc19c, 0xd27f, 0xc19c, 0x21, 0 + .dw 0xd2c0, 0xc19c, 0xd2ff, 0xc19c, 0x21, 0 + .dw 0xd340, 0xc19c, 0xd37f, 0xc19c, 0x21, 0 + .dw 0xd3c0, 0xc19c, 0xd3ff, 0xc19c, 0x21, 0 + .dw 0xd440, 0xc19c, 0xd47f, 0xc19c, 0x21, 0 + .dw 0xd4c0, 0xc19c, 0xd4ff, 0xc19c, 0x21, 0 + .dw 0xd540, 0xc19c, 0xd57f, 0xc19c, 0x21, 0 + .dw 0xd5c0, 0xc19c, 0xd5ff, 0xc19c, 0x21, 0 + .dw 0xd640, 0xc19c, 0xd67f, 0xc19c, 0x21, 0 + .dw 0xd6c0, 0xc19c, 0xd6ff, 0xc19c, 0x21, 0 + .dw 0xd740, 0xc19c, 0xd77f, 0xc19c, 0x21, 0 + .dw 0xd7c0, 0xc19c, 0xd7ff, 0xc19c, 0x21, 0 + .dw 0xd840, 0xc19c, 0xd87f, 0xc19c, 0x21, 0 + .dw 0xd8c0, 0xc19c, 0xd8ff, 0xc19c, 0x21, 0 + .dw 0xd940, 0xc19c, 0xd97f, 0xc19c, 0x21, 0 + .dw 0xd9c0, 0xc19c, 0xdfff, 0xc19c, 0x21, 0 + .dw 0xe040, 0xc19c, 0xe07f, 0xc19c, 0x21, 0 + .dw 0xe0c0, 0xc19c, 0xe0ff, 0xc19c, 0x21, 0 + .dw 0xe140, 0xc19c, 0xe17f, 0xc19c, 0x21, 0 + .dw 0xe1c0, 0xc19c, 0xe1ff, 0xc19c, 0x21, 0 + .dw 0xe240, 0xc19c, 0xe27f, 0xc19c, 0x21, 0 + .dw 0xe2c0, 0xc19c, 0xe2ff, 0xc19c, 0x21, 0 + .dw 0xe340, 0xc19c, 0xe37f, 0xc19c, 0x21, 0 + .dw 0xe3c0, 0xc19c, 0xe3ff, 0xc19c, 0x21, 0 + .dw 0xe440, 0xc19c, 0xe47f, 0xc19c, 0x21, 0 + .dw 0xe4c0, 0xc19c, 0xe4ff, 0xc19c, 0x21, 0 + .dw 0xe540, 0xc19c, 0xe57f, 0xc19c, 0x21, 0 + .dw 0xe5c0, 0xc19c, 0xe5ff, 0xc19c, 0x21, 0 + .dw 0xe640, 0xc19c, 0xe67f, 0xc19c, 0x21, 0 + .dw 0xe6c0, 0xc19c, 0xe6ff, 0xc19c, 0x21, 0 + .dw 0xe740, 0xc19c, 0xe77f, 0xc19c, 0x21, 0 + .dw 0xe7c0, 0xc19c, 0xe7ff, 0xc19c, 0x21, 0 + .dw 0xe840, 0xc19c, 0xe87f, 0xc19c, 0x21, 0 + .dw 0xe8c0, 0xc19c, 0xe8ff, 0xc19c, 0x21, 0 + .dw 0xe940, 0xc19c, 0xe97f, 0xc19c, 0x21, 0 + .dw 0xe9c0, 0xc19c, 0xe9ff, 0xc19c, 0x21, 0 + .dw 0xea40, 0xc19c, 0xea7f, 0xc19c, 0x21, 0 + .dw 0xeac0, 0xc19c, 0xeaff, 0xc19c, 0x21, 0 + .dw 0xeb40, 0xc19c, 0xeb7f, 0xc19c, 0x21, 0 + .dw 0xebc0, 0xc19c, 0xebff, 0xc19c, 0x21, 0 + .dw 0xec40, 0xc19c, 0xec7f, 0xc19c, 0x21, 0 + .dw 0xecc0, 0xc19c, 0xecff, 0xc19c, 0x21, 0 + .dw 0xed40, 0xc19c, 0xed7f, 0xc19c, 0x21, 0 + .dw 0xedc0, 0xc19c, 0xedff, 0xc19c, 0x21, 0 + .dw 0xee40, 0xc19c, 0xee7f, 0xc19c, 0x21, 0 + .dw 0xeec0, 0xc19c, 0xeeff, 0xc19c, 0x21, 0 + .dw 0xef40, 0xc19c, 0xef7f, 0xc19c, 0x21, 0 + .dw 0xefc0, 0xc19c, 0xefff, 0xc19c, 0x21, 0 + .dw 0xf040, 0xc19c, 0xf07f, 0xc19c, 0x21, 0 + .dw 0xf0c0, 0xc19c, 0xf0ff, 0xc19c, 0x21, 0 + .dw 0xf140, 0xc19c, 0xf17f, 0xc19c, 0x21, 0 + .dw 0xf1c0, 0xc19c, 0xf1ff, 0xc19c, 0x21, 0 + .dw 0xf240, 0xc19c, 0xf27f, 0xc19c, 0x21, 0 + .dw 0xf2c0, 0xc19c, 0xf2ff, 0xc19c, 0x21, 0 + .dw 0xf340, 0xc19c, 0xf37f, 0xc19c, 0x21, 0 + .dw 0xf3c0, 0xc19c, 0xf3ff, 0xc19c, 0x21, 0 + .dw 0xf440, 0xc19c, 0xf47f, 0xc19c, 0x21, 0 + .dw 0xf4c0, 0xc19c, 0xf4ff, 0xc19c, 0x21, 0 + .dw 0xf540, 0xc19c, 0xf57f, 0xc19c, 0x21, 0 + .dw 0xf5c0, 0xc19c, 0xf5ff, 0xc19c, 0x21, 0 + .dw 0xf640, 0xc19c, 0xf67f, 0xc19c, 0x21, 0 + .dw 0xf6c0, 0xc19c, 0xf6ff, 0xc19c, 0x21, 0 + .dw 0xf740, 0xc19c, 0xf77f, 0xc19c, 0x21, 0 + .dw 0xf7c0, 0xc19c, 0xf7ff, 0xc19c, 0x21, 0 + .dw 0xf840, 0xc19c, 0xf87f, 0xc19c, 0x21, 0 + .dw 0xf8c0, 0xc19c, 0xf8ff, 0xc19c, 0x21, 0 + .dw 0xf940, 0xc19c, 0xf97f, 0xc19c, 0x21, 0 + .dw 0xf9c0, 0xc19c, 0xffff, 0xc19c, 0x21, 0 + .dw 0x0040, 0xc19d, 0x007f, 0xc19d, 0x21, 0 + .dw 0x00c0, 0xc19d, 0x00ff, 0xc19d, 0x21, 0 + .dw 0x0140, 0xc19d, 0x017f, 0xc19d, 0x21, 0 + .dw 0x01c0, 0xc19d, 0x01ff, 0xc19d, 0x21, 0 + .dw 0x0240, 0xc19d, 0x027f, 0xc19d, 0x21, 0 + .dw 0x02c0, 0xc19d, 0x02ff, 0xc19d, 0x21, 0 + .dw 0x0340, 0xc19d, 0x037f, 0xc19d, 0x21, 0 + .dw 0x03c0, 0xc19d, 0x03ff, 0xc19d, 0x21, 0 + .dw 0x0440, 0xc19d, 0x047f, 0xc19d, 0x21, 0 + .dw 0x04c0, 0xc19d, 0x04ff, 0xc19d, 0x21, 0 + .dw 0x0540, 0xc19d, 0x057f, 0xc19d, 0x21, 0 + .dw 0x05c0, 0xc19d, 0x05ff, 0xc19d, 0x21, 0 + .dw 0x0640, 0xc19d, 0x067f, 0xc19d, 0x21, 0 + .dw 0x06c0, 0xc19d, 0x06ff, 0xc19d, 0x21, 0 + .dw 0x0740, 0xc19d, 0x077f, 0xc19d, 0x21, 0 + .dw 0x07c0, 0xc19d, 0x07ff, 0xc19d, 0x21, 0 + .dw 0x0840, 0xc19d, 0x087f, 0xc19d, 0x21, 0 + .dw 0x08c0, 0xc19d, 0x08ff, 0xc19d, 0x21, 0 + .dw 0x0940, 0xc19d, 0x097f, 0xc19d, 0x21, 0 + .dw 0x09c0, 0xc19d, 0x09ff, 0xc19d, 0x21, 0 + .dw 0x0a40, 0xc19d, 0x0a7f, 0xc19d, 0x21, 0 + .dw 0x0ac0, 0xc19d, 0x0aff, 0xc19d, 0x21, 0 + .dw 0x0b40, 0xc19d, 0x0b7f, 0xc19d, 0x21, 0 + .dw 0x0bc0, 0xc19d, 0x0bff, 0xc19d, 0x21, 0 + .dw 0x0c40, 0xc19d, 0x0c7f, 0xc19d, 0x21, 0 + .dw 0x0cc0, 0xc19d, 0x0cff, 0xc19d, 0x21, 0 + .dw 0x0d40, 0xc19d, 0x0d7f, 0xc19d, 0x21, 0 + .dw 0x0dc0, 0xc19d, 0x0dff, 0xc19d, 0x21, 0 + .dw 0x0e40, 0xc19d, 0x0e7f, 0xc19d, 0x21, 0 + .dw 0x0ec0, 0xc19d, 0x0eff, 0xc19d, 0x21, 0 + .dw 0x0f40, 0xc19d, 0x0f7f, 0xc19d, 0x21, 0 + .dw 0x0fc0, 0xc19d, 0x0fff, 0xc19d, 0x21, 0 + .dw 0x1040, 0xc19d, 0x107f, 0xc19d, 0x21, 0 + .dw 0x10c0, 0xc19d, 0x10ff, 0xc19d, 0x21, 0 + .dw 0x1140, 0xc19d, 0x117f, 0xc19d, 0x21, 0 + .dw 0x11c0, 0xc19d, 0x11ff, 0xc19d, 0x21, 0 + .dw 0x1240, 0xc19d, 0x127f, 0xc19d, 0x21, 0 + .dw 0x12c0, 0xc19d, 0x12ff, 0xc19d, 0x21, 0 + .dw 0x1340, 0xc19d, 0x137f, 0xc19d, 0x21, 0 + .dw 0x13c0, 0xc19d, 0x13ff, 0xc19d, 0x21, 0 + .dw 0x1440, 0xc19d, 0x147f, 0xc19d, 0x21, 0 + .dw 0x14c0, 0xc19d, 0x14ff, 0xc19d, 0x21, 0 + .dw 0x1540, 0xc19d, 0x157f, 0xc19d, 0x21, 0 + .dw 0x15c0, 0xc19d, 0x15ff, 0xc19d, 0x21, 0 + .dw 0x1640, 0xc19d, 0x167f, 0xc19d, 0x21, 0 + .dw 0x16c0, 0xc19d, 0x16ff, 0xc19d, 0x21, 0 + .dw 0x1740, 0xc19d, 0x177f, 0xc19d, 0x21, 0 + .dw 0x17c0, 0xc19d, 0x17ff, 0xc19d, 0x21, 0 + .dw 0x1840, 0xc19d, 0x187f, 0xc19d, 0x21, 0 + .dw 0x18c0, 0xc19d, 0x18ff, 0xc19d, 0x21, 0 + .dw 0x1940, 0xc19d, 0x197f, 0xc19d, 0x21, 0 + .dw 0x19c0, 0xc19d, 0x1fff, 0xc19d, 0x21, 0 + .dw 0x2040, 0xc19d, 0x207f, 0xc19d, 0x21, 0 + .dw 0x20c0, 0xc19d, 0x20ff, 0xc19d, 0x21, 0 + .dw 0x2140, 0xc19d, 0x217f, 0xc19d, 0x21, 0 + .dw 0x21c0, 0xc19d, 0x21ff, 0xc19d, 0x21, 0 + .dw 0x2240, 0xc19d, 0x227f, 0xc19d, 0x21, 0 + .dw 0x22c0, 0xc19d, 0x22ff, 0xc19d, 0x21, 0 + .dw 0x2340, 0xc19d, 0x237f, 0xc19d, 0x21, 0 + .dw 0x23c0, 0xc19d, 0x23ff, 0xc19d, 0x21, 0 + .dw 0x2440, 0xc19d, 0x247f, 0xc19d, 0x21, 0 + .dw 0x24c0, 0xc19d, 0x24ff, 0xc19d, 0x21, 0 + .dw 0x2540, 0xc19d, 0x257f, 0xc19d, 0x21, 0 + .dw 0x25c0, 0xc19d, 0x25ff, 0xc19d, 0x21, 0 + .dw 0x2640, 0xc19d, 0x267f, 0xc19d, 0x21, 0 + .dw 0x26c0, 0xc19d, 0x26ff, 0xc19d, 0x21, 0 + .dw 0x2740, 0xc19d, 0x277f, 0xc19d, 0x21, 0 + .dw 0x27c0, 0xc19d, 0x27ff, 0xc19d, 0x21, 0 + .dw 0x2840, 0xc19d, 0x287f, 0xc19d, 0x21, 0 + .dw 0x28c0, 0xc19d, 0x28ff, 0xc19d, 0x21, 0 + .dw 0x2940, 0xc19d, 0x297f, 0xc19d, 0x21, 0 + .dw 0x29c0, 0xc19d, 0x29ff, 0xc19d, 0x21, 0 + .dw 0x2a40, 0xc19d, 0x2a7f, 0xc19d, 0x21, 0 + .dw 0x2ac0, 0xc19d, 0x2aff, 0xc19d, 0x21, 0 + .dw 0x2b40, 0xc19d, 0x2b7f, 0xc19d, 0x21, 0 + .dw 0x2bc0, 0xc19d, 0x2bff, 0xc19d, 0x21, 0 + .dw 0x2c40, 0xc19d, 0x2c7f, 0xc19d, 0x21, 0 + .dw 0x2cc0, 0xc19d, 0x2cff, 0xc19d, 0x21, 0 + .dw 0x2d40, 0xc19d, 0x2d7f, 0xc19d, 0x21, 0 + .dw 0x2dc0, 0xc19d, 0x2dff, 0xc19d, 0x21, 0 + .dw 0x2e40, 0xc19d, 0x2e7f, 0xc19d, 0x21, 0 + .dw 0x2ec0, 0xc19d, 0x2eff, 0xc19d, 0x21, 0 + .dw 0x2f40, 0xc19d, 0x2f7f, 0xc19d, 0x21, 0 + .dw 0x2fc0, 0xc19d, 0x2fff, 0xc19d, 0x21, 0 + .dw 0x3040, 0xc19d, 0x307f, 0xc19d, 0x21, 0 + .dw 0x30c0, 0xc19d, 0x30ff, 0xc19d, 0x21, 0 + .dw 0x3140, 0xc19d, 0x317f, 0xc19d, 0x21, 0 + .dw 0x31c0, 0xc19d, 0x31ff, 0xc19d, 0x21, 0 + .dw 0x3240, 0xc19d, 0x327f, 0xc19d, 0x21, 0 + .dw 0x32c0, 0xc19d, 0x32ff, 0xc19d, 0x21, 0 + .dw 0x3340, 0xc19d, 0x337f, 0xc19d, 0x21, 0 + .dw 0x33c0, 0xc19d, 0x33ff, 0xc19d, 0x21, 0 + .dw 0x3440, 0xc19d, 0x347f, 0xc19d, 0x21, 0 + .dw 0x34c0, 0xc19d, 0x34ff, 0xc19d, 0x21, 0 + .dw 0x3540, 0xc19d, 0x357f, 0xc19d, 0x21, 0 + .dw 0x35c0, 0xc19d, 0x35ff, 0xc19d, 0x21, 0 + .dw 0x3640, 0xc19d, 0x367f, 0xc19d, 0x21, 0 + .dw 0x36c0, 0xc19d, 0x36ff, 0xc19d, 0x21, 0 + .dw 0x3740, 0xc19d, 0x377f, 0xc19d, 0x21, 0 + .dw 0x37c0, 0xc19d, 0x37ff, 0xc19d, 0x21, 0 + .dw 0x3840, 0xc19d, 0x387f, 0xc19d, 0x21, 0 + .dw 0x38c0, 0xc19d, 0x38ff, 0xc19d, 0x21, 0 + .dw 0x3940, 0xc19d, 0x397f, 0xc19d, 0x21, 0 + .dw 0x39c0, 0xc19d, 0x3fff, 0xc19d, 0x21, 0 + .dw 0x4040, 0xc19d, 0x407f, 0xc19d, 0x21, 0 + .dw 0x40c0, 0xc19d, 0x40ff, 0xc19d, 0x21, 0 + .dw 0x4140, 0xc19d, 0x417f, 0xc19d, 0x21, 0 + .dw 0x41c0, 0xc19d, 0x41ff, 0xc19d, 0x21, 0 + .dw 0x4240, 0xc19d, 0x427f, 0xc19d, 0x21, 0 + .dw 0x42c0, 0xc19d, 0x42ff, 0xc19d, 0x21, 0 + .dw 0x4340, 0xc19d, 0x437f, 0xc19d, 0x21, 0 + .dw 0x43c0, 0xc19d, 0x43ff, 0xc19d, 0x21, 0 + .dw 0x4440, 0xc19d, 0x447f, 0xc19d, 0x21, 0 + .dw 0x44c0, 0xc19d, 0x44ff, 0xc19d, 0x21, 0 + .dw 0x4540, 0xc19d, 0x457f, 0xc19d, 0x21, 0 + .dw 0x45c0, 0xc19d, 0x45ff, 0xc19d, 0x21, 0 + .dw 0x4640, 0xc19d, 0x467f, 0xc19d, 0x21, 0 + .dw 0x46c0, 0xc19d, 0x46ff, 0xc19d, 0x21, 0 + .dw 0x4740, 0xc19d, 0x477f, 0xc19d, 0x21, 0 + .dw 0x47c0, 0xc19d, 0x47ff, 0xc19d, 0x21, 0 + .dw 0x4840, 0xc19d, 0x487f, 0xc19d, 0x21, 0 + .dw 0x48c0, 0xc19d, 0x48ff, 0xc19d, 0x21, 0 + .dw 0x4940, 0xc19d, 0x497f, 0xc19d, 0x21, 0 + .dw 0x49c0, 0xc19d, 0x49ff, 0xc19d, 0x21, 0 + .dw 0x4a40, 0xc19d, 0x4a7f, 0xc19d, 0x21, 0 + .dw 0x4ac0, 0xc19d, 0x4aff, 0xc19d, 0x21, 0 + .dw 0x4b40, 0xc19d, 0x4b7f, 0xc19d, 0x21, 0 + .dw 0x4bc0, 0xc19d, 0x4bff, 0xc19d, 0x21, 0 + .dw 0x4c40, 0xc19d, 0x4c7f, 0xc19d, 0x21, 0 + .dw 0x4cc0, 0xc19d, 0x4cff, 0xc19d, 0x21, 0 + .dw 0x4d40, 0xc19d, 0x4d7f, 0xc19d, 0x21, 0 + .dw 0x4dc0, 0xc19d, 0x4dff, 0xc19d, 0x21, 0 + .dw 0x4e40, 0xc19d, 0x4e7f, 0xc19d, 0x21, 0 + .dw 0x4ec0, 0xc19d, 0x4eff, 0xc19d, 0x21, 0 + .dw 0x4f40, 0xc19d, 0x4f7f, 0xc19d, 0x21, 0 + .dw 0x4fc0, 0xc19d, 0x4fff, 0xc19d, 0x21, 0 + .dw 0x5040, 0xc19d, 0x507f, 0xc19d, 0x21, 0 + .dw 0x50c0, 0xc19d, 0x50ff, 0xc19d, 0x21, 0 + .dw 0x5140, 0xc19d, 0x517f, 0xc19d, 0x21, 0 + .dw 0x51c0, 0xc19d, 0x51ff, 0xc19d, 0x21, 0 + .dw 0x5240, 0xc19d, 0x527f, 0xc19d, 0x21, 0 + .dw 0x52c0, 0xc19d, 0x52ff, 0xc19d, 0x21, 0 + .dw 0x5340, 0xc19d, 0x537f, 0xc19d, 0x21, 0 + .dw 0x53c0, 0xc19d, 0x53ff, 0xc19d, 0x21, 0 + .dw 0x5440, 0xc19d, 0x547f, 0xc19d, 0x21, 0 + .dw 0x54c0, 0xc19d, 0x54ff, 0xc19d, 0x21, 0 + .dw 0x5540, 0xc19d, 0x557f, 0xc19d, 0x21, 0 + .dw 0x55c0, 0xc19d, 0x55ff, 0xc19d, 0x21, 0 + .dw 0x5640, 0xc19d, 0x567f, 0xc19d, 0x21, 0 + .dw 0x56c0, 0xc19d, 0x56ff, 0xc19d, 0x21, 0 + .dw 0x5740, 0xc19d, 0x577f, 0xc19d, 0x21, 0 + .dw 0x57c0, 0xc19d, 0x57ff, 0xc19d, 0x21, 0 + .dw 0x5840, 0xc19d, 0x587f, 0xc19d, 0x21, 0 + .dw 0x58c0, 0xc19d, 0x58ff, 0xc19d, 0x21, 0 + .dw 0x5940, 0xc19d, 0x597f, 0xc19d, 0x21, 0 + .dw 0x59c0, 0xc19d, 0x5fff, 0xc19d, 0x21, 0 + .dw 0x6040, 0xc19d, 0x607f, 0xc19d, 0x21, 0 + .dw 0x60c0, 0xc19d, 0x60ff, 0xc19d, 0x21, 0 + .dw 0x6140, 0xc19d, 0x617f, 0xc19d, 0x21, 0 + .dw 0x61c0, 0xc19d, 0x61ff, 0xc19d, 0x21, 0 + .dw 0x6240, 0xc19d, 0x627f, 0xc19d, 0x21, 0 + .dw 0x62c0, 0xc19d, 0x62ff, 0xc19d, 0x21, 0 + .dw 0x6340, 0xc19d, 0x637f, 0xc19d, 0x21, 0 + .dw 0x63c0, 0xc19d, 0x63ff, 0xc19d, 0x21, 0 + .dw 0x6440, 0xc19d, 0x647f, 0xc19d, 0x21, 0 + .dw 0x64c0, 0xc19d, 0x64ff, 0xc19d, 0x21, 0 + .dw 0x6540, 0xc19d, 0x657f, 0xc19d, 0x21, 0 + .dw 0x65c0, 0xc19d, 0x65ff, 0xc19d, 0x21, 0 + .dw 0x6640, 0xc19d, 0x667f, 0xc19d, 0x21, 0 + .dw 0x66c0, 0xc19d, 0x66ff, 0xc19d, 0x21, 0 + .dw 0x6740, 0xc19d, 0x677f, 0xc19d, 0x21, 0 + .dw 0x67c0, 0xc19d, 0x67ff, 0xc19d, 0x21, 0 + .dw 0x6840, 0xc19d, 0x687f, 0xc19d, 0x21, 0 + .dw 0x68c0, 0xc19d, 0x68ff, 0xc19d, 0x21, 0 + .dw 0x6940, 0xc19d, 0x697f, 0xc19d, 0x21, 0 + .dw 0x69c0, 0xc19d, 0x69ff, 0xc19d, 0x21, 0 + .dw 0x6a40, 0xc19d, 0x6a7f, 0xc19d, 0x21, 0 + .dw 0x6ac0, 0xc19d, 0x6aff, 0xc19d, 0x21, 0 + .dw 0x6b40, 0xc19d, 0x6b7f, 0xc19d, 0x21, 0 + .dw 0x6bc0, 0xc19d, 0x6bff, 0xc19d, 0x21, 0 + .dw 0x6c40, 0xc19d, 0x6c7f, 0xc19d, 0x21, 0 + .dw 0x6cc0, 0xc19d, 0x6cff, 0xc19d, 0x21, 0 + .dw 0x6d40, 0xc19d, 0x6d7f, 0xc19d, 0x21, 0 + .dw 0x6dc0, 0xc19d, 0x6dff, 0xc19d, 0x21, 0 + .dw 0x6e40, 0xc19d, 0x6e7f, 0xc19d, 0x21, 0 + .dw 0x6ec0, 0xc19d, 0x6eff, 0xc19d, 0x21, 0 + .dw 0x6f40, 0xc19d, 0x6f7f, 0xc19d, 0x21, 0 + .dw 0x6fc0, 0xc19d, 0x6fff, 0xc19d, 0x21, 0 + .dw 0x7040, 0xc19d, 0x707f, 0xc19d, 0x21, 0 + .dw 0x70c0, 0xc19d, 0x70ff, 0xc19d, 0x21, 0 + .dw 0x7140, 0xc19d, 0x717f, 0xc19d, 0x21, 0 + .dw 0x71c0, 0xc19d, 0x71ff, 0xc19d, 0x21, 0 + .dw 0x7240, 0xc19d, 0x727f, 0xc19d, 0x21, 0 + .dw 0x72c0, 0xc19d, 0x72ff, 0xc19d, 0x21, 0 + .dw 0x7340, 0xc19d, 0x737f, 0xc19d, 0x21, 0 + .dw 0x73c0, 0xc19d, 0x73ff, 0xc19d, 0x21, 0 + .dw 0x7440, 0xc19d, 0x747f, 0xc19d, 0x21, 0 + .dw 0x74c0, 0xc19d, 0x74ff, 0xc19d, 0x21, 0 + .dw 0x7540, 0xc19d, 0x757f, 0xc19d, 0x21, 0 + .dw 0x75c0, 0xc19d, 0x75ff, 0xc19d, 0x21, 0 + .dw 0x7640, 0xc19d, 0x767f, 0xc19d, 0x21, 0 + .dw 0x76c0, 0xc19d, 0x76ff, 0xc19d, 0x21, 0 + .dw 0x7740, 0xc19d, 0x777f, 0xc19d, 0x21, 0 + .dw 0x77c0, 0xc19d, 0x77ff, 0xc19d, 0x21, 0 + .dw 0x7840, 0xc19d, 0x787f, 0xc19d, 0x21, 0 + .dw 0x78c0, 0xc19d, 0x78ff, 0xc19d, 0x21, 0 + .dw 0x7940, 0xc19d, 0x797f, 0xc19d, 0x21, 0 + .dw 0x79c0, 0xc19d, 0x7fff, 0xc19d, 0x21, 0 + .dw 0x8040, 0xc19d, 0x807f, 0xc19d, 0x21, 0 + .dw 0x80c0, 0xc19d, 0x80ff, 0xc19d, 0x21, 0 + .dw 0x8140, 0xc19d, 0x817f, 0xc19d, 0x21, 0 + .dw 0x81c0, 0xc19d, 0x81ff, 0xc19d, 0x21, 0 + .dw 0x8240, 0xc19d, 0x827f, 0xc19d, 0x21, 0 + .dw 0x82c0, 0xc19d, 0x82ff, 0xc19d, 0x21, 0 + .dw 0x8340, 0xc19d, 0x837f, 0xc19d, 0x21, 0 + .dw 0x83c0, 0xc19d, 0x83ff, 0xc19d, 0x21, 0 + .dw 0x8440, 0xc19d, 0x847f, 0xc19d, 0x21, 0 + .dw 0x84c0, 0xc19d, 0x84ff, 0xc19d, 0x21, 0 + .dw 0x8540, 0xc19d, 0x857f, 0xc19d, 0x21, 0 + .dw 0x85c0, 0xc19d, 0x85ff, 0xc19d, 0x21, 0 + .dw 0x8640, 0xc19d, 0x867f, 0xc19d, 0x21, 0 + .dw 0x86c0, 0xc19d, 0x86ff, 0xc19d, 0x21, 0 + .dw 0x8740, 0xc19d, 0x877f, 0xc19d, 0x21, 0 + .dw 0x87c0, 0xc19d, 0x87ff, 0xc19d, 0x21, 0 + .dw 0x8840, 0xc19d, 0x887f, 0xc19d, 0x21, 0 + .dw 0x88c0, 0xc19d, 0x88ff, 0xc19d, 0x21, 0 + .dw 0x8940, 0xc19d, 0x897f, 0xc19d, 0x21, 0 + .dw 0x89c0, 0xc19d, 0x89ff, 0xc19d, 0x21, 0 + .dw 0x8a40, 0xc19d, 0x8a7f, 0xc19d, 0x21, 0 + .dw 0x8ac0, 0xc19d, 0x8aff, 0xc19d, 0x21, 0 + .dw 0x8b40, 0xc19d, 0x8b7f, 0xc19d, 0x21, 0 + .dw 0x8bc0, 0xc19d, 0x8bff, 0xc19d, 0x21, 0 + .dw 0x8c40, 0xc19d, 0x8c7f, 0xc19d, 0x21, 0 + .dw 0x8cc0, 0xc19d, 0x8cff, 0xc19d, 0x21, 0 + .dw 0x8d40, 0xc19d, 0x8d7f, 0xc19d, 0x21, 0 + .dw 0x8dc0, 0xc19d, 0x8dff, 0xc19d, 0x21, 0 + .dw 0x8e40, 0xc19d, 0x8e7f, 0xc19d, 0x21, 0 + .dw 0x8ec0, 0xc19d, 0x8eff, 0xc19d, 0x21, 0 + .dw 0x8f40, 0xc19d, 0x8f7f, 0xc19d, 0x21, 0 + .dw 0x8fc0, 0xc19d, 0x8fff, 0xc19d, 0x21, 0 + .dw 0x9040, 0xc19d, 0x907f, 0xc19d, 0x21, 0 + .dw 0x90c0, 0xc19d, 0x90ff, 0xc19d, 0x21, 0 + .dw 0x9140, 0xc19d, 0x917f, 0xc19d, 0x21, 0 + .dw 0x91c0, 0xc19d, 0x91ff, 0xc19d, 0x21, 0 + .dw 0x9240, 0xc19d, 0x927f, 0xc19d, 0x21, 0 + .dw 0x92c0, 0xc19d, 0x92ff, 0xc19d, 0x21, 0 + .dw 0x9340, 0xc19d, 0x937f, 0xc19d, 0x21, 0 + .dw 0x93c0, 0xc19d, 0x93ff, 0xc19d, 0x21, 0 + .dw 0x9440, 0xc19d, 0x947f, 0xc19d, 0x21, 0 + .dw 0x94c0, 0xc19d, 0x94ff, 0xc19d, 0x21, 0 + .dw 0x9540, 0xc19d, 0x957f, 0xc19d, 0x21, 0 + .dw 0x95c0, 0xc19d, 0x95ff, 0xc19d, 0x21, 0 + .dw 0x9640, 0xc19d, 0x967f, 0xc19d, 0x21, 0 + .dw 0x96c0, 0xc19d, 0x96ff, 0xc19d, 0x21, 0 + .dw 0x9740, 0xc19d, 0x977f, 0xc19d, 0x21, 0 + .dw 0x97c0, 0xc19d, 0x97ff, 0xc19d, 0x21, 0 + .dw 0x9840, 0xc19d, 0x987f, 0xc19d, 0x21, 0 + .dw 0x98c0, 0xc19d, 0x98ff, 0xc19d, 0x21, 0 + .dw 0x9940, 0xc19d, 0x997f, 0xc19d, 0x21, 0 + .dw 0x99c0, 0xc19d, 0x9fff, 0xc19d, 0x21, 0 + .dw 0xa040, 0xc19d, 0xa07f, 0xc19d, 0x21, 0 + .dw 0xa0c0, 0xc19d, 0xa0ff, 0xc19d, 0x21, 0 + .dw 0xa140, 0xc19d, 0xa17f, 0xc19d, 0x21, 0 + .dw 0xa1c0, 0xc19d, 0xa1ff, 0xc19d, 0x21, 0 + .dw 0xa240, 0xc19d, 0xa27f, 0xc19d, 0x21, 0 + .dw 0xa2c0, 0xc19d, 0xa2ff, 0xc19d, 0x21, 0 + .dw 0xa340, 0xc19d, 0xa37f, 0xc19d, 0x21, 0 + .dw 0xa3c0, 0xc19d, 0xa3ff, 0xc19d, 0x21, 0 + .dw 0xa440, 0xc19d, 0xa47f, 0xc19d, 0x21, 0 + .dw 0xa4c0, 0xc19d, 0xa4ff, 0xc19d, 0x21, 0 + .dw 0xa540, 0xc19d, 0xa57f, 0xc19d, 0x21, 0 + .dw 0xa5c0, 0xc19d, 0xa5ff, 0xc19d, 0x21, 0 + .dw 0xa640, 0xc19d, 0xa67f, 0xc19d, 0x21, 0 + .dw 0xa6c0, 0xc19d, 0xa6ff, 0xc19d, 0x21, 0 + .dw 0xa740, 0xc19d, 0xa77f, 0xc19d, 0x21, 0 + .dw 0xa7c0, 0xc19d, 0xa7ff, 0xc19d, 0x21, 0 + .dw 0xa840, 0xc19d, 0xa87f, 0xc19d, 0x21, 0 + .dw 0xa8c0, 0xc19d, 0xa8ff, 0xc19d, 0x21, 0 + .dw 0xa940, 0xc19d, 0xa97f, 0xc19d, 0x21, 0 + .dw 0xa9c0, 0xc19d, 0xa9ff, 0xc19d, 0x21, 0 + .dw 0xaa40, 0xc19d, 0xaa7f, 0xc19d, 0x21, 0 + .dw 0xaac0, 0xc19d, 0xaaff, 0xc19d, 0x21, 0 + .dw 0xab40, 0xc19d, 0xab7f, 0xc19d, 0x21, 0 + .dw 0xabc0, 0xc19d, 0xabff, 0xc19d, 0x21, 0 + .dw 0xac40, 0xc19d, 0xac7f, 0xc19d, 0x21, 0 + .dw 0xacc0, 0xc19d, 0xacff, 0xc19d, 0x21, 0 + .dw 0xad40, 0xc19d, 0xad7f, 0xc19d, 0x21, 0 + .dw 0xadc0, 0xc19d, 0xadff, 0xc19d, 0x21, 0 + .dw 0xae40, 0xc19d, 0xae7f, 0xc19d, 0x21, 0 + .dw 0xaec0, 0xc19d, 0xaeff, 0xc19d, 0x21, 0 + .dw 0xaf40, 0xc19d, 0xaf7f, 0xc19d, 0x21, 0 + .dw 0xafc0, 0xc19d, 0xafff, 0xc19d, 0x21, 0 + .dw 0xb040, 0xc19d, 0xb07f, 0xc19d, 0x21, 0 + .dw 0xb0c0, 0xc19d, 0xb0ff, 0xc19d, 0x21, 0 + .dw 0xb140, 0xc19d, 0xb17f, 0xc19d, 0x21, 0 + .dw 0xb1c0, 0xc19d, 0xb1ff, 0xc19d, 0x21, 0 + .dw 0xb240, 0xc19d, 0xb27f, 0xc19d, 0x21, 0 + .dw 0xb2c0, 0xc19d, 0xb2ff, 0xc19d, 0x21, 0 + .dw 0xb340, 0xc19d, 0xb37f, 0xc19d, 0x21, 0 + .dw 0xb3c0, 0xc19d, 0xb3ff, 0xc19d, 0x21, 0 + .dw 0xb440, 0xc19d, 0xb47f, 0xc19d, 0x21, 0 + .dw 0xb4c0, 0xc19d, 0xb4ff, 0xc19d, 0x21, 0 + .dw 0xb540, 0xc19d, 0xb57f, 0xc19d, 0x21, 0 + .dw 0xb5c0, 0xc19d, 0xb5ff, 0xc19d, 0x21, 0 + .dw 0xb640, 0xc19d, 0xb67f, 0xc19d, 0x21, 0 + .dw 0xb6c0, 0xc19d, 0xb6ff, 0xc19d, 0x21, 0 + .dw 0xb740, 0xc19d, 0xb77f, 0xc19d, 0x21, 0 + .dw 0xb7c0, 0xc19d, 0xb7ff, 0xc19d, 0x21, 0 + .dw 0xb840, 0xc19d, 0xb87f, 0xc19d, 0x21, 0 + .dw 0xb8c0, 0xc19d, 0xb8ff, 0xc19d, 0x21, 0 + .dw 0xb940, 0xc19d, 0xb97f, 0xc19d, 0x21, 0 + .dw 0xb9c0, 0xc19d, 0xbfff, 0xc19d, 0x21, 0 + .dw 0xc040, 0xc19d, 0xc07f, 0xc19d, 0x21, 0 + .dw 0xc0c0, 0xc19d, 0xc0ff, 0xc19d, 0x21, 0 + .dw 0xc140, 0xc19d, 0xc17f, 0xc19d, 0x21, 0 + .dw 0xc1c0, 0xc19d, 0xc1ff, 0xc19d, 0x21, 0 + .dw 0xc240, 0xc19d, 0xc27f, 0xc19d, 0x21, 0 + .dw 0xc2c0, 0xc19d, 0xc2ff, 0xc19d, 0x21, 0 + .dw 0xc340, 0xc19d, 0xc37f, 0xc19d, 0x21, 0 + .dw 0xc3c0, 0xc19d, 0xc3ff, 0xc19d, 0x21, 0 + .dw 0xc440, 0xc19d, 0xc47f, 0xc19d, 0x21, 0 + .dw 0xc4c0, 0xc19d, 0xc4ff, 0xc19d, 0x21, 0 + .dw 0xc540, 0xc19d, 0xc57f, 0xc19d, 0x21, 0 + .dw 0xc5c0, 0xc19d, 0xc5ff, 0xc19d, 0x21, 0 + .dw 0xc640, 0xc19d, 0xc67f, 0xc19d, 0x21, 0 + .dw 0xc6c0, 0xc19d, 0xc6ff, 0xc19d, 0x21, 0 + .dw 0xc740, 0xc19d, 0xc77f, 0xc19d, 0x21, 0 + .dw 0xc7c0, 0xc19d, 0xc7ff, 0xc19d, 0x21, 0 + .dw 0xc840, 0xc19d, 0xc87f, 0xc19d, 0x21, 0 + .dw 0xc8c0, 0xc19d, 0xc8ff, 0xc19d, 0x21, 0 + .dw 0xc940, 0xc19d, 0xc97f, 0xc19d, 0x21, 0 + .dw 0xc9c0, 0xc19d, 0xc9ff, 0xc19d, 0x21, 0 + .dw 0xca40, 0xc19d, 0xca7f, 0xc19d, 0x21, 0 + .dw 0xcac0, 0xc19d, 0xcaff, 0xc19d, 0x21, 0 + .dw 0xcb40, 0xc19d, 0xcb7f, 0xc19d, 0x21, 0 + .dw 0xcbc0, 0xc19d, 0xcbff, 0xc19d, 0x21, 0 + .dw 0xcc40, 0xc19d, 0xcc7f, 0xc19d, 0x21, 0 + .dw 0xccc0, 0xc19d, 0xccff, 0xc19d, 0x21, 0 + .dw 0xcd40, 0xc19d, 0xcd7f, 0xc19d, 0x21, 0 + .dw 0xcdc0, 0xc19d, 0xcdff, 0xc19d, 0x21, 0 + .dw 0xce40, 0xc19d, 0xce7f, 0xc19d, 0x21, 0 + .dw 0xcec0, 0xc19d, 0xceff, 0xc19d, 0x21, 0 + .dw 0xcf40, 0xc19d, 0xcf7f, 0xc19d, 0x21, 0 + .dw 0xcfc0, 0xc19d, 0xcfff, 0xc19d, 0x21, 0 + .dw 0xd040, 0xc19d, 0xd07f, 0xc19d, 0x21, 0 + .dw 0xd0c0, 0xc19d, 0xd0ff, 0xc19d, 0x21, 0 + .dw 0xd140, 0xc19d, 0xd17f, 0xc19d, 0x21, 0 + .dw 0xd1c0, 0xc19d, 0xd1ff, 0xc19d, 0x21, 0 + .dw 0xd240, 0xc19d, 0xd27f, 0xc19d, 0x21, 0 + .dw 0xd2c0, 0xc19d, 0xd2ff, 0xc19d, 0x21, 0 + .dw 0xd340, 0xc19d, 0xd37f, 0xc19d, 0x21, 0 + .dw 0xd3c0, 0xc19d, 0xd3ff, 0xc19d, 0x21, 0 + .dw 0xd440, 0xc19d, 0xd47f, 0xc19d, 0x21, 0 + .dw 0xd4c0, 0xc19d, 0xd4ff, 0xc19d, 0x21, 0 + .dw 0xd540, 0xc19d, 0xd57f, 0xc19d, 0x21, 0 + .dw 0xd5c0, 0xc19d, 0xd5ff, 0xc19d, 0x21, 0 + .dw 0xd640, 0xc19d, 0xd67f, 0xc19d, 0x21, 0 + .dw 0xd6c0, 0xc19d, 0xd6ff, 0xc19d, 0x21, 0 + .dw 0xd740, 0xc19d, 0xd77f, 0xc19d, 0x21, 0 + .dw 0xd7c0, 0xc19d, 0xd7ff, 0xc19d, 0x21, 0 + .dw 0xd840, 0xc19d, 0xd87f, 0xc19d, 0x21, 0 + .dw 0xd8c0, 0xc19d, 0xd8ff, 0xc19d, 0x21, 0 + .dw 0xd940, 0xc19d, 0xd97f, 0xc19d, 0x21, 0 + .dw 0xd9c0, 0xc19d, 0xdfff, 0xc19d, 0x21, 0 + .dw 0xe040, 0xc19d, 0xe07f, 0xc19d, 0x21, 0 + .dw 0xe0c0, 0xc19d, 0xe0ff, 0xc19d, 0x21, 0 + .dw 0xe140, 0xc19d, 0xe17f, 0xc19d, 0x21, 0 + .dw 0xe1c0, 0xc19d, 0xe1ff, 0xc19d, 0x21, 0 + .dw 0xe240, 0xc19d, 0xe27f, 0xc19d, 0x21, 0 + .dw 0xe2c0, 0xc19d, 0xe2ff, 0xc19d, 0x21, 0 + .dw 0xe340, 0xc19d, 0xe37f, 0xc19d, 0x21, 0 + .dw 0xe3c0, 0xc19d, 0xe3ff, 0xc19d, 0x21, 0 + .dw 0xe440, 0xc19d, 0xe47f, 0xc19d, 0x21, 0 + .dw 0xe4c0, 0xc19d, 0xe4ff, 0xc19d, 0x21, 0 + .dw 0xe540, 0xc19d, 0xe57f, 0xc19d, 0x21, 0 + .dw 0xe5c0, 0xc19d, 0xe5ff, 0xc19d, 0x21, 0 + .dw 0xe640, 0xc19d, 0xe67f, 0xc19d, 0x21, 0 + .dw 0xe6c0, 0xc19d, 0xe6ff, 0xc19d, 0x21, 0 + .dw 0xe740, 0xc19d, 0xe77f, 0xc19d, 0x21, 0 + .dw 0xe7c0, 0xc19d, 0xe7ff, 0xc19d, 0x21, 0 + .dw 0xe840, 0xc19d, 0xe87f, 0xc19d, 0x21, 0 + .dw 0xe8c0, 0xc19d, 0xe8ff, 0xc19d, 0x21, 0 + .dw 0xe940, 0xc19d, 0xe97f, 0xc19d, 0x21, 0 + .dw 0xe9c0, 0xc19d, 0xe9ff, 0xc19d, 0x21, 0 + .dw 0xea40, 0xc19d, 0xea7f, 0xc19d, 0x21, 0 + .dw 0xeac0, 0xc19d, 0xeaff, 0xc19d, 0x21, 0 + .dw 0xeb40, 0xc19d, 0xeb7f, 0xc19d, 0x21, 0 + .dw 0xebc0, 0xc19d, 0xebff, 0xc19d, 0x21, 0 + .dw 0xec40, 0xc19d, 0xec7f, 0xc19d, 0x21, 0 + .dw 0xecc0, 0xc19d, 0xecff, 0xc19d, 0x21, 0 + .dw 0xed40, 0xc19d, 0xed7f, 0xc19d, 0x21, 0 + .dw 0xedc0, 0xc19d, 0xedff, 0xc19d, 0x21, 0 + .dw 0xee40, 0xc19d, 0xee7f, 0xc19d, 0x21, 0 + .dw 0xeec0, 0xc19d, 0xeeff, 0xc19d, 0x21, 0 + .dw 0xef40, 0xc19d, 0xef7f, 0xc19d, 0x21, 0 + .dw 0xefc0, 0xc19d, 0xefff, 0xc19d, 0x21, 0 + .dw 0xf040, 0xc19d, 0xf07f, 0xc19d, 0x21, 0 + .dw 0xf0c0, 0xc19d, 0xf0ff, 0xc19d, 0x21, 0 + .dw 0xf140, 0xc19d, 0xf17f, 0xc19d, 0x21, 0 + .dw 0xf1c0, 0xc19d, 0xf1ff, 0xc19d, 0x21, 0 + .dw 0xf240, 0xc19d, 0xf27f, 0xc19d, 0x21, 0 + .dw 0xf2c0, 0xc19d, 0xf2ff, 0xc19d, 0x21, 0 + .dw 0xf340, 0xc19d, 0xf37f, 0xc19d, 0x21, 0 + .dw 0xf3c0, 0xc19d, 0xf3ff, 0xc19d, 0x21, 0 + .dw 0xf440, 0xc19d, 0xf47f, 0xc19d, 0x21, 0 + .dw 0xf4c0, 0xc19d, 0xf4ff, 0xc19d, 0x21, 0 + .dw 0xf540, 0xc19d, 0xf57f, 0xc19d, 0x21, 0 + .dw 0xf5c0, 0xc19d, 0xf5ff, 0xc19d, 0x21, 0 + .dw 0xf640, 0xc19d, 0xf67f, 0xc19d, 0x21, 0 + .dw 0xf6c0, 0xc19d, 0xf6ff, 0xc19d, 0x21, 0 + .dw 0xf740, 0xc19d, 0xf77f, 0xc19d, 0x21, 0 + .dw 0xf7c0, 0xc19d, 0xf7ff, 0xc19d, 0x21, 0 + .dw 0xf840, 0xc19d, 0xf87f, 0xc19d, 0x21, 0 + .dw 0xf8c0, 0xc19d, 0xf8ff, 0xc19d, 0x21, 0 + .dw 0xf940, 0xc19d, 0xf97f, 0xc19d, 0x21, 0 + .dw 0xf9c0, 0xc19d, 0xffff, 0xc19d, 0x21, 0 + .dw 0x0040, 0xc19e, 0x007f, 0xc19e, 0x21, 0 + .dw 0x00c0, 0xc19e, 0x00ff, 0xc19e, 0x21, 0 + .dw 0x0140, 0xc19e, 0x017f, 0xc19e, 0x21, 0 + .dw 0x01c0, 0xc19e, 0x01ff, 0xc19e, 0x21, 0 + .dw 0x0240, 0xc19e, 0x027f, 0xc19e, 0x21, 0 + .dw 0x02c0, 0xc19e, 0x02ff, 0xc19e, 0x21, 0 + .dw 0x0340, 0xc19e, 0x037f, 0xc19e, 0x21, 0 + .dw 0x03c0, 0xc19e, 0x03ff, 0xc19e, 0x21, 0 + .dw 0x0440, 0xc19e, 0x047f, 0xc19e, 0x21, 0 + .dw 0x04c0, 0xc19e, 0x04ff, 0xc19e, 0x21, 0 + .dw 0x0540, 0xc19e, 0x057f, 0xc19e, 0x21, 0 + .dw 0x05c0, 0xc19e, 0x05ff, 0xc19e, 0x21, 0 + .dw 0x0640, 0xc19e, 0x067f, 0xc19e, 0x21, 0 + .dw 0x06c0, 0xc19e, 0x06ff, 0xc19e, 0x21, 0 + .dw 0x0740, 0xc19e, 0x077f, 0xc19e, 0x21, 0 + .dw 0x07c0, 0xc19e, 0x07ff, 0xc19e, 0x21, 0 + .dw 0x0840, 0xc19e, 0x087f, 0xc19e, 0x21, 0 + .dw 0x08c0, 0xc19e, 0x08ff, 0xc19e, 0x21, 0 + .dw 0x0940, 0xc19e, 0x097f, 0xc19e, 0x21, 0 + .dw 0x09c0, 0xc19e, 0x09ff, 0xc19e, 0x21, 0 + .dw 0x0a40, 0xc19e, 0x0a7f, 0xc19e, 0x21, 0 + .dw 0x0ac0, 0xc19e, 0x0aff, 0xc19e, 0x21, 0 + .dw 0x0b40, 0xc19e, 0x0b7f, 0xc19e, 0x21, 0 + .dw 0x0bc0, 0xc19e, 0x0bff, 0xc19e, 0x21, 0 + .dw 0x0c40, 0xc19e, 0x0c7f, 0xc19e, 0x21, 0 + .dw 0x0cc0, 0xc19e, 0x0cff, 0xc19e, 0x21, 0 + .dw 0x0d40, 0xc19e, 0x0d7f, 0xc19e, 0x21, 0 + .dw 0x0dc0, 0xc19e, 0x0dff, 0xc19e, 0x21, 0 + .dw 0x0e40, 0xc19e, 0x0e7f, 0xc19e, 0x21, 0 + .dw 0x0ec0, 0xc19e, 0x0eff, 0xc19e, 0x21, 0 + .dw 0x0f40, 0xc19e, 0x0f7f, 0xc19e, 0x21, 0 + .dw 0x0fc0, 0xc19e, 0x0fff, 0xc19e, 0x21, 0 + .dw 0x1040, 0xc19e, 0x107f, 0xc19e, 0x21, 0 + .dw 0x10c0, 0xc19e, 0x10ff, 0xc19e, 0x21, 0 + .dw 0x1140, 0xc19e, 0x117f, 0xc19e, 0x21, 0 + .dw 0x11c0, 0xc19e, 0x11ff, 0xc19e, 0x21, 0 + .dw 0x1240, 0xc19e, 0x127f, 0xc19e, 0x21, 0 + .dw 0x12c0, 0xc19e, 0x12ff, 0xc19e, 0x21, 0 + .dw 0x1340, 0xc19e, 0x137f, 0xc19e, 0x21, 0 + .dw 0x13c0, 0xc19e, 0x13ff, 0xc19e, 0x21, 0 + .dw 0x1440, 0xc19e, 0x147f, 0xc19e, 0x21, 0 + .dw 0x14c0, 0xc19e, 0x14ff, 0xc19e, 0x21, 0 + .dw 0x1540, 0xc19e, 0x157f, 0xc19e, 0x21, 0 + .dw 0x15c0, 0xc19e, 0x15ff, 0xc19e, 0x21, 0 + .dw 0x1640, 0xc19e, 0x167f, 0xc19e, 0x21, 0 + .dw 0x16c0, 0xc19e, 0x16ff, 0xc19e, 0x21, 0 + .dw 0x1740, 0xc19e, 0x177f, 0xc19e, 0x21, 0 + .dw 0x17c0, 0xc19e, 0x17ff, 0xc19e, 0x21, 0 + .dw 0x1840, 0xc19e, 0x187f, 0xc19e, 0x21, 0 + .dw 0x18c0, 0xc19e, 0x18ff, 0xc19e, 0x21, 0 + .dw 0x1940, 0xc19e, 0x197f, 0xc19e, 0x21, 0 + .dw 0x19c0, 0xc19e, 0x1fff, 0xc19e, 0x21, 0 + .dw 0x2040, 0xc19e, 0x207f, 0xc19e, 0x21, 0 + .dw 0x20c0, 0xc19e, 0x20ff, 0xc19e, 0x21, 0 + .dw 0x2140, 0xc19e, 0x217f, 0xc19e, 0x21, 0 + .dw 0x21c0, 0xc19e, 0x21ff, 0xc19e, 0x21, 0 + .dw 0x2240, 0xc19e, 0x227f, 0xc19e, 0x21, 0 + .dw 0x22c0, 0xc19e, 0x22ff, 0xc19e, 0x21, 0 + .dw 0x2340, 0xc19e, 0x237f, 0xc19e, 0x21, 0 + .dw 0x23c0, 0xc19e, 0x23ff, 0xc19e, 0x21, 0 + .dw 0x2440, 0xc19e, 0x247f, 0xc19e, 0x21, 0 + .dw 0x24c0, 0xc19e, 0x24ff, 0xc19e, 0x21, 0 + .dw 0x2540, 0xc19e, 0x257f, 0xc19e, 0x21, 0 + .dw 0x25c0, 0xc19e, 0x25ff, 0xc19e, 0x21, 0 + .dw 0x2640, 0xc19e, 0x267f, 0xc19e, 0x21, 0 + .dw 0x26c0, 0xc19e, 0x26ff, 0xc19e, 0x21, 0 + .dw 0x2740, 0xc19e, 0x277f, 0xc19e, 0x21, 0 + .dw 0x27c0, 0xc19e, 0x27ff, 0xc19e, 0x21, 0 + .dw 0x2840, 0xc19e, 0x287f, 0xc19e, 0x21, 0 + .dw 0x28c0, 0xc19e, 0x28ff, 0xc19e, 0x21, 0 + .dw 0x2940, 0xc19e, 0x297f, 0xc19e, 0x21, 0 + .dw 0x29c0, 0xc19e, 0x29ff, 0xc19e, 0x21, 0 + .dw 0x2a40, 0xc19e, 0x2a7f, 0xc19e, 0x21, 0 + .dw 0x2ac0, 0xc19e, 0x2aff, 0xc19e, 0x21, 0 + .dw 0x2b40, 0xc19e, 0x2b7f, 0xc19e, 0x21, 0 + .dw 0x2bc0, 0xc19e, 0x2bff, 0xc19e, 0x21, 0 + .dw 0x2c40, 0xc19e, 0x2c7f, 0xc19e, 0x21, 0 + .dw 0x2cc0, 0xc19e, 0x2cff, 0xc19e, 0x21, 0 + .dw 0x2d40, 0xc19e, 0x2d7f, 0xc19e, 0x21, 0 + .dw 0x2dc0, 0xc19e, 0x2dff, 0xc19e, 0x21, 0 + .dw 0x2e40, 0xc19e, 0x2e7f, 0xc19e, 0x21, 0 + .dw 0x2ec0, 0xc19e, 0x2eff, 0xc19e, 0x21, 0 + .dw 0x2f40, 0xc19e, 0x2f7f, 0xc19e, 0x21, 0 + .dw 0x2fc0, 0xc19e, 0x2fff, 0xc19e, 0x21, 0 + .dw 0x3040, 0xc19e, 0x307f, 0xc19e, 0x21, 0 + .dw 0x30c0, 0xc19e, 0x30ff, 0xc19e, 0x21, 0 + .dw 0x3140, 0xc19e, 0x317f, 0xc19e, 0x21, 0 + .dw 0x31c0, 0xc19e, 0x31ff, 0xc19e, 0x21, 0 + .dw 0x3240, 0xc19e, 0x327f, 0xc19e, 0x21, 0 + .dw 0x32c0, 0xc19e, 0x32ff, 0xc19e, 0x21, 0 + .dw 0x3340, 0xc19e, 0x337f, 0xc19e, 0x21, 0 + .dw 0x33c0, 0xc19e, 0x33ff, 0xc19e, 0x21, 0 + .dw 0x3440, 0xc19e, 0x347f, 0xc19e, 0x21, 0 + .dw 0x34c0, 0xc19e, 0x34ff, 0xc19e, 0x21, 0 + .dw 0x3540, 0xc19e, 0x357f, 0xc19e, 0x21, 0 + .dw 0x35c0, 0xc19e, 0x35ff, 0xc19e, 0x21, 0 + .dw 0x3640, 0xc19e, 0x367f, 0xc19e, 0x21, 0 + .dw 0x36c0, 0xc19e, 0x36ff, 0xc19e, 0x21, 0 + .dw 0x3740, 0xc19e, 0x377f, 0xc19e, 0x21, 0 + .dw 0x37c0, 0xc19e, 0x37ff, 0xc19e, 0x21, 0 + .dw 0x3840, 0xc19e, 0x387f, 0xc19e, 0x21, 0 + .dw 0x38c0, 0xc19e, 0x38ff, 0xc19e, 0x21, 0 + .dw 0x3940, 0xc19e, 0x397f, 0xc19e, 0x21, 0 + .dw 0x39c0, 0xc19e, 0x3fff, 0xc19e, 0x21, 0 + .dw 0x4040, 0xc19e, 0x407f, 0xc19e, 0x21, 0 + .dw 0x40c0, 0xc19e, 0x40ff, 0xc19e, 0x21, 0 + .dw 0x4140, 0xc19e, 0x417f, 0xc19e, 0x21, 0 + .dw 0x41c0, 0xc19e, 0x41ff, 0xc19e, 0x21, 0 + .dw 0x4240, 0xc19e, 0x427f, 0xc19e, 0x21, 0 + .dw 0x42c0, 0xc19e, 0x42ff, 0xc19e, 0x21, 0 + .dw 0x4340, 0xc19e, 0x437f, 0xc19e, 0x21, 0 + .dw 0x43c0, 0xc19e, 0x43ff, 0xc19e, 0x21, 0 + .dw 0x4440, 0xc19e, 0x447f, 0xc19e, 0x21, 0 + .dw 0x44c0, 0xc19e, 0x44ff, 0xc19e, 0x21, 0 + .dw 0x4540, 0xc19e, 0x457f, 0xc19e, 0x21, 0 + .dw 0x45c0, 0xc19e, 0x45ff, 0xc19e, 0x21, 0 + .dw 0x4640, 0xc19e, 0x467f, 0xc19e, 0x21, 0 + .dw 0x46c0, 0xc19e, 0x46ff, 0xc19e, 0x21, 0 + .dw 0x4740, 0xc19e, 0x477f, 0xc19e, 0x21, 0 + .dw 0x47c0, 0xc19e, 0x47ff, 0xc19e, 0x21, 0 + .dw 0x4840, 0xc19e, 0x487f, 0xc19e, 0x21, 0 + .dw 0x48c0, 0xc19e, 0x48ff, 0xc19e, 0x21, 0 + .dw 0x4940, 0xc19e, 0x497f, 0xc19e, 0x21, 0 + .dw 0x49c0, 0xc19e, 0x49ff, 0xc19e, 0x21, 0 + .dw 0x4a40, 0xc19e, 0x4a7f, 0xc19e, 0x21, 0 + .dw 0x4ac0, 0xc19e, 0x4aff, 0xc19e, 0x21, 0 + .dw 0x4b40, 0xc19e, 0x4b7f, 0xc19e, 0x21, 0 + .dw 0x4bc0, 0xc19e, 0x4bff, 0xc19e, 0x21, 0 + .dw 0x4c40, 0xc19e, 0x4c7f, 0xc19e, 0x21, 0 + .dw 0x4cc0, 0xc19e, 0x4cff, 0xc19e, 0x21, 0 + .dw 0x4d40, 0xc19e, 0x4d7f, 0xc19e, 0x21, 0 + .dw 0x4dc0, 0xc19e, 0x4dff, 0xc19e, 0x21, 0 + .dw 0x4e40, 0xc19e, 0x4e7f, 0xc19e, 0x21, 0 + .dw 0x4ec0, 0xc19e, 0x4eff, 0xc19e, 0x21, 0 + .dw 0x4f40, 0xc19e, 0x4f7f, 0xc19e, 0x21, 0 + .dw 0x4fc0, 0xc19e, 0x4fff, 0xc19e, 0x21, 0 + .dw 0x5040, 0xc19e, 0x507f, 0xc19e, 0x21, 0 + .dw 0x50c0, 0xc19e, 0x50ff, 0xc19e, 0x21, 0 + .dw 0x5140, 0xc19e, 0x517f, 0xc19e, 0x21, 0 + .dw 0x51c0, 0xc19e, 0x51ff, 0xc19e, 0x21, 0 + .dw 0x5240, 0xc19e, 0x527f, 0xc19e, 0x21, 0 + .dw 0x52c0, 0xc19e, 0x52ff, 0xc19e, 0x21, 0 + .dw 0x5340, 0xc19e, 0x537f, 0xc19e, 0x21, 0 + .dw 0x53c0, 0xc19e, 0x53ff, 0xc19e, 0x21, 0 + .dw 0x5440, 0xc19e, 0x547f, 0xc19e, 0x21, 0 + .dw 0x54c0, 0xc19e, 0x54ff, 0xc19e, 0x21, 0 + .dw 0x5540, 0xc19e, 0x557f, 0xc19e, 0x21, 0 + .dw 0x55c0, 0xc19e, 0x55ff, 0xc19e, 0x21, 0 + .dw 0x5640, 0xc19e, 0x567f, 0xc19e, 0x21, 0 + .dw 0x56c0, 0xc19e, 0x56ff, 0xc19e, 0x21, 0 + .dw 0x5740, 0xc19e, 0x577f, 0xc19e, 0x21, 0 + .dw 0x57c0, 0xc19e, 0x57ff, 0xc19e, 0x21, 0 + .dw 0x5840, 0xc19e, 0x587f, 0xc19e, 0x21, 0 + .dw 0x58c0, 0xc19e, 0x58ff, 0xc19e, 0x21, 0 + .dw 0x5940, 0xc19e, 0x597f, 0xc19e, 0x21, 0 + .dw 0x59c0, 0xc19e, 0x5fff, 0xc19e, 0x21, 0 + .dw 0x6040, 0xc19e, 0x607f, 0xc19e, 0x21, 0 + .dw 0x60c0, 0xc19e, 0x60ff, 0xc19e, 0x21, 0 + .dw 0x6140, 0xc19e, 0x617f, 0xc19e, 0x21, 0 + .dw 0x61c0, 0xc19e, 0x61ff, 0xc19e, 0x21, 0 + .dw 0x6240, 0xc19e, 0x627f, 0xc19e, 0x21, 0 + .dw 0x62c0, 0xc19e, 0x62ff, 0xc19e, 0x21, 0 + .dw 0x6340, 0xc19e, 0x637f, 0xc19e, 0x21, 0 + .dw 0x63c0, 0xc19e, 0x63ff, 0xc19e, 0x21, 0 + .dw 0x6440, 0xc19e, 0x647f, 0xc19e, 0x21, 0 + .dw 0x64c0, 0xc19e, 0x64ff, 0xc19e, 0x21, 0 + .dw 0x6540, 0xc19e, 0x657f, 0xc19e, 0x21, 0 + .dw 0x65c0, 0xc19e, 0x65ff, 0xc19e, 0x21, 0 + .dw 0x6640, 0xc19e, 0x667f, 0xc19e, 0x21, 0 + .dw 0x66c0, 0xc19e, 0x66ff, 0xc19e, 0x21, 0 + .dw 0x6740, 0xc19e, 0x677f, 0xc19e, 0x21, 0 + .dw 0x67c0, 0xc19e, 0x67ff, 0xc19e, 0x21, 0 + .dw 0x6840, 0xc19e, 0x687f, 0xc19e, 0x21, 0 + .dw 0x68c0, 0xc19e, 0x68ff, 0xc19e, 0x21, 0 + .dw 0x6940, 0xc19e, 0x697f, 0xc19e, 0x21, 0 + .dw 0x69c0, 0xc19e, 0x69ff, 0xc19e, 0x21, 0 + .dw 0x6a40, 0xc19e, 0x6a7f, 0xc19e, 0x21, 0 + .dw 0x6ac0, 0xc19e, 0x6aff, 0xc19e, 0x21, 0 + .dw 0x6b40, 0xc19e, 0x6b7f, 0xc19e, 0x21, 0 + .dw 0x6bc0, 0xc19e, 0x6bff, 0xc19e, 0x21, 0 + .dw 0x6c40, 0xc19e, 0x6c7f, 0xc19e, 0x21, 0 + .dw 0x6cc0, 0xc19e, 0x6cff, 0xc19e, 0x21, 0 + .dw 0x6d40, 0xc19e, 0x6d7f, 0xc19e, 0x21, 0 + .dw 0x6dc0, 0xc19e, 0x6dff, 0xc19e, 0x21, 0 + .dw 0x6e40, 0xc19e, 0x6e7f, 0xc19e, 0x21, 0 + .dw 0x6ec0, 0xc19e, 0x6eff, 0xc19e, 0x21, 0 + .dw 0x6f40, 0xc19e, 0x6f7f, 0xc19e, 0x21, 0 + .dw 0x6fc0, 0xc19e, 0x6fff, 0xc19e, 0x21, 0 + .dw 0x7040, 0xc19e, 0x707f, 0xc19e, 0x21, 0 + .dw 0x70c0, 0xc19e, 0x70ff, 0xc19e, 0x21, 0 + .dw 0x7140, 0xc19e, 0x717f, 0xc19e, 0x21, 0 + .dw 0x71c0, 0xc19e, 0x71ff, 0xc19e, 0x21, 0 + .dw 0x7240, 0xc19e, 0x727f, 0xc19e, 0x21, 0 + .dw 0x72c0, 0xc19e, 0x72ff, 0xc19e, 0x21, 0 + .dw 0x7340, 0xc19e, 0x737f, 0xc19e, 0x21, 0 + .dw 0x73c0, 0xc19e, 0x73ff, 0xc19e, 0x21, 0 + .dw 0x7440, 0xc19e, 0x747f, 0xc19e, 0x21, 0 + .dw 0x74c0, 0xc19e, 0x74ff, 0xc19e, 0x21, 0 + .dw 0x7540, 0xc19e, 0x757f, 0xc19e, 0x21, 0 + .dw 0x75c0, 0xc19e, 0x75ff, 0xc19e, 0x21, 0 + .dw 0x7640, 0xc19e, 0x767f, 0xc19e, 0x21, 0 + .dw 0x76c0, 0xc19e, 0x76ff, 0xc19e, 0x21, 0 + .dw 0x7740, 0xc19e, 0x777f, 0xc19e, 0x21, 0 + .dw 0x77c0, 0xc19e, 0x77ff, 0xc19e, 0x21, 0 + .dw 0x7840, 0xc19e, 0x787f, 0xc19e, 0x21, 0 + .dw 0x78c0, 0xc19e, 0x78ff, 0xc19e, 0x21, 0 + .dw 0x7940, 0xc19e, 0x797f, 0xc19e, 0x21, 0 + .dw 0x79c0, 0xc19e, 0x7fff, 0xc19e, 0x21, 0 + .dw 0x8040, 0xc19e, 0x807f, 0xc19e, 0x21, 0 + .dw 0x80c0, 0xc19e, 0x80ff, 0xc19e, 0x21, 0 + .dw 0x8140, 0xc19e, 0x817f, 0xc19e, 0x21, 0 + .dw 0x81c0, 0xc19e, 0x81ff, 0xc19e, 0x21, 0 + .dw 0x8240, 0xc19e, 0x827f, 0xc19e, 0x21, 0 + .dw 0x82c0, 0xc19e, 0x82ff, 0xc19e, 0x21, 0 + .dw 0x8340, 0xc19e, 0x837f, 0xc19e, 0x21, 0 + .dw 0x83c0, 0xc19e, 0x83ff, 0xc19e, 0x21, 0 + .dw 0x8440, 0xc19e, 0x847f, 0xc19e, 0x21, 0 + .dw 0x84c0, 0xc19e, 0x84ff, 0xc19e, 0x21, 0 + .dw 0x8540, 0xc19e, 0x857f, 0xc19e, 0x21, 0 + .dw 0x85c0, 0xc19e, 0x85ff, 0xc19e, 0x21, 0 + .dw 0x8640, 0xc19e, 0x867f, 0xc19e, 0x21, 0 + .dw 0x86c0, 0xc19e, 0x86ff, 0xc19e, 0x21, 0 + .dw 0x8740, 0xc19e, 0x877f, 0xc19e, 0x21, 0 + .dw 0x87c0, 0xc19e, 0x87ff, 0xc19e, 0x21, 0 + .dw 0x8840, 0xc19e, 0x887f, 0xc19e, 0x21, 0 + .dw 0x88c0, 0xc19e, 0x88ff, 0xc19e, 0x21, 0 + .dw 0x8940, 0xc19e, 0x897f, 0xc19e, 0x21, 0 + .dw 0x89c0, 0xc19e, 0x89ff, 0xc19e, 0x21, 0 + .dw 0x8a40, 0xc19e, 0x8a7f, 0xc19e, 0x21, 0 + .dw 0x8ac0, 0xc19e, 0x8aff, 0xc19e, 0x21, 0 + .dw 0x8b40, 0xc19e, 0x8b7f, 0xc19e, 0x21, 0 + .dw 0x8bc0, 0xc19e, 0x8bff, 0xc19e, 0x21, 0 + .dw 0x8c40, 0xc19e, 0x8c7f, 0xc19e, 0x21, 0 + .dw 0x8cc0, 0xc19e, 0x8cff, 0xc19e, 0x21, 0 + .dw 0x8d40, 0xc19e, 0x8d7f, 0xc19e, 0x21, 0 + .dw 0x8dc0, 0xc19e, 0x8dff, 0xc19e, 0x21, 0 + .dw 0x8e40, 0xc19e, 0x8e7f, 0xc19e, 0x21, 0 + .dw 0x8ec0, 0xc19e, 0x8eff, 0xc19e, 0x21, 0 + .dw 0x8f40, 0xc19e, 0x8f7f, 0xc19e, 0x21, 0 + .dw 0x8fc0, 0xc19e, 0x8fff, 0xc19e, 0x21, 0 + .dw 0x9040, 0xc19e, 0x907f, 0xc19e, 0x21, 0 + .dw 0x90c0, 0xc19e, 0x90ff, 0xc19e, 0x21, 0 + .dw 0x9140, 0xc19e, 0x917f, 0xc19e, 0x21, 0 + .dw 0x91c0, 0xc19e, 0x91ff, 0xc19e, 0x21, 0 + .dw 0x9240, 0xc19e, 0x927f, 0xc19e, 0x21, 0 + .dw 0x92c0, 0xc19e, 0x92ff, 0xc19e, 0x21, 0 + .dw 0x9340, 0xc19e, 0x937f, 0xc19e, 0x21, 0 + .dw 0x93c0, 0xc19e, 0x93ff, 0xc19e, 0x21, 0 + .dw 0x9440, 0xc19e, 0x947f, 0xc19e, 0x21, 0 + .dw 0x94c0, 0xc19e, 0x94ff, 0xc19e, 0x21, 0 + .dw 0x9540, 0xc19e, 0x957f, 0xc19e, 0x21, 0 + .dw 0x95c0, 0xc19e, 0x95ff, 0xc19e, 0x21, 0 + .dw 0x9640, 0xc19e, 0x967f, 0xc19e, 0x21, 0 + .dw 0x96c0, 0xc19e, 0x96ff, 0xc19e, 0x21, 0 + .dw 0x9740, 0xc19e, 0x977f, 0xc19e, 0x21, 0 + .dw 0x97c0, 0xc19e, 0x97ff, 0xc19e, 0x21, 0 + .dw 0x9840, 0xc19e, 0x987f, 0xc19e, 0x21, 0 + .dw 0x98c0, 0xc19e, 0x98ff, 0xc19e, 0x21, 0 + .dw 0x9940, 0xc19e, 0x997f, 0xc19e, 0x21, 0 + .dw 0x99c0, 0xc19e, 0x9fff, 0xc19e, 0x21, 0 + .dw 0xa040, 0xc19e, 0xa07f, 0xc19e, 0x21, 0 + .dw 0xa0c0, 0xc19e, 0xa0ff, 0xc19e, 0x21, 0 + .dw 0xa140, 0xc19e, 0xa17f, 0xc19e, 0x21, 0 + .dw 0xa1c0, 0xc19e, 0xa1ff, 0xc19e, 0x21, 0 + .dw 0xa240, 0xc19e, 0xa27f, 0xc19e, 0x21, 0 + .dw 0xa2c0, 0xc19e, 0xa2ff, 0xc19e, 0x21, 0 + .dw 0xa340, 0xc19e, 0xa37f, 0xc19e, 0x21, 0 + .dw 0xa3c0, 0xc19e, 0xa3ff, 0xc19e, 0x21, 0 + .dw 0xa440, 0xc19e, 0xa47f, 0xc19e, 0x21, 0 + .dw 0xa4c0, 0xc19e, 0xa4ff, 0xc19e, 0x21, 0 + .dw 0xa540, 0xc19e, 0xa57f, 0xc19e, 0x21, 0 + .dw 0xa5c0, 0xc19e, 0xa5ff, 0xc19e, 0x21, 0 + .dw 0xa640, 0xc19e, 0xa67f, 0xc19e, 0x21, 0 + .dw 0xa6c0, 0xc19e, 0xa6ff, 0xc19e, 0x21, 0 + .dw 0xa740, 0xc19e, 0xa77f, 0xc19e, 0x21, 0 + .dw 0xa7c0, 0xc19e, 0xa7ff, 0xc19e, 0x21, 0 + .dw 0xa840, 0xc19e, 0xa87f, 0xc19e, 0x21, 0 + .dw 0xa8c0, 0xc19e, 0xa8ff, 0xc19e, 0x21, 0 + .dw 0xa940, 0xc19e, 0xa97f, 0xc19e, 0x21, 0 + .dw 0xa9c0, 0xc19e, 0xa9ff, 0xc19e, 0x21, 0 + .dw 0xaa40, 0xc19e, 0xaa7f, 0xc19e, 0x21, 0 + .dw 0xaac0, 0xc19e, 0xaaff, 0xc19e, 0x21, 0 + .dw 0xab40, 0xc19e, 0xab7f, 0xc19e, 0x21, 0 + .dw 0xabc0, 0xc19e, 0xabff, 0xc19e, 0x21, 0 + .dw 0xac40, 0xc19e, 0xac7f, 0xc19e, 0x21, 0 + .dw 0xacc0, 0xc19e, 0xacff, 0xc19e, 0x21, 0 + .dw 0xad40, 0xc19e, 0xad7f, 0xc19e, 0x21, 0 + .dw 0xadc0, 0xc19e, 0xadff, 0xc19e, 0x21, 0 + .dw 0xae40, 0xc19e, 0xae7f, 0xc19e, 0x21, 0 + .dw 0xaec0, 0xc19e, 0xaeff, 0xc19e, 0x21, 0 + .dw 0xaf40, 0xc19e, 0xaf7f, 0xc19e, 0x21, 0 + .dw 0xafc0, 0xc19e, 0xafff, 0xc19e, 0x21, 0 + .dw 0xb040, 0xc19e, 0xb07f, 0xc19e, 0x21, 0 + .dw 0xb0c0, 0xc19e, 0xb0ff, 0xc19e, 0x21, 0 + .dw 0xb140, 0xc19e, 0xb17f, 0xc19e, 0x21, 0 + .dw 0xb1c0, 0xc19e, 0xb1ff, 0xc19e, 0x21, 0 + .dw 0xb240, 0xc19e, 0xb27f, 0xc19e, 0x21, 0 + .dw 0xb2c0, 0xc19e, 0xb2ff, 0xc19e, 0x21, 0 + .dw 0xb340, 0xc19e, 0xb37f, 0xc19e, 0x21, 0 + .dw 0xb3c0, 0xc19e, 0xb3ff, 0xc19e, 0x21, 0 + .dw 0xb440, 0xc19e, 0xb47f, 0xc19e, 0x21, 0 + .dw 0xb4c0, 0xc19e, 0xb4ff, 0xc19e, 0x21, 0 + .dw 0xb540, 0xc19e, 0xb57f, 0xc19e, 0x21, 0 + .dw 0xb5c0, 0xc19e, 0xb5ff, 0xc19e, 0x21, 0 + .dw 0xb640, 0xc19e, 0xb67f, 0xc19e, 0x21, 0 + .dw 0xb6c0, 0xc19e, 0xb6ff, 0xc19e, 0x21, 0 + .dw 0xb740, 0xc19e, 0xb77f, 0xc19e, 0x21, 0 + .dw 0xb7c0, 0xc19e, 0xb7ff, 0xc19e, 0x21, 0 + .dw 0xb840, 0xc19e, 0xb87f, 0xc19e, 0x21, 0 + .dw 0xb8c0, 0xc19e, 0xb8ff, 0xc19e, 0x21, 0 + .dw 0xb940, 0xc19e, 0xb97f, 0xc19e, 0x21, 0 + .dw 0xb9c0, 0xc19e, 0xbfff, 0xc19e, 0x21, 0 + .dw 0xc040, 0xc19e, 0xc07f, 0xc19e, 0x21, 0 + .dw 0xc0c0, 0xc19e, 0xc0ff, 0xc19e, 0x21, 0 + .dw 0xc140, 0xc19e, 0xc17f, 0xc19e, 0x21, 0 + .dw 0xc1c0, 0xc19e, 0xc1ff, 0xc19e, 0x21, 0 + .dw 0xc240, 0xc19e, 0xc27f, 0xc19e, 0x21, 0 + .dw 0xc2c0, 0xc19e, 0xc2ff, 0xc19e, 0x21, 0 + .dw 0xc340, 0xc19e, 0xc37f, 0xc19e, 0x21, 0 + .dw 0xc3c0, 0xc19e, 0xc3ff, 0xc19e, 0x21, 0 + .dw 0xc440, 0xc19e, 0xc47f, 0xc19e, 0x21, 0 + .dw 0xc4c0, 0xc19e, 0xc4ff, 0xc19e, 0x21, 0 + .dw 0xc540, 0xc19e, 0xc57f, 0xc19e, 0x21, 0 + .dw 0xc5c0, 0xc19e, 0xc5ff, 0xc19e, 0x21, 0 + .dw 0xc640, 0xc19e, 0xc67f, 0xc19e, 0x21, 0 + .dw 0xc6c0, 0xc19e, 0xc6ff, 0xc19e, 0x21, 0 + .dw 0xc740, 0xc19e, 0xc77f, 0xc19e, 0x21, 0 + .dw 0xc7c0, 0xc19e, 0xc7ff, 0xc19e, 0x21, 0 + .dw 0xc840, 0xc19e, 0xc87f, 0xc19e, 0x21, 0 + .dw 0xc8c0, 0xc19e, 0xc8ff, 0xc19e, 0x21, 0 + .dw 0xc940, 0xc19e, 0xc97f, 0xc19e, 0x21, 0 + .dw 0xc9c0, 0xc19e, 0xc9ff, 0xc19e, 0x21, 0 + .dw 0xca40, 0xc19e, 0xca7f, 0xc19e, 0x21, 0 + .dw 0xcac0, 0xc19e, 0xcaff, 0xc19e, 0x21, 0 + .dw 0xcb40, 0xc19e, 0xcb7f, 0xc19e, 0x21, 0 + .dw 0xcbc0, 0xc19e, 0xcbff, 0xc19e, 0x21, 0 + .dw 0xcc40, 0xc19e, 0xcc7f, 0xc19e, 0x21, 0 + .dw 0xccc0, 0xc19e, 0xccff, 0xc19e, 0x21, 0 + .dw 0xcd40, 0xc19e, 0xcd7f, 0xc19e, 0x21, 0 + .dw 0xcdc0, 0xc19e, 0xcdff, 0xc19e, 0x21, 0 + .dw 0xce40, 0xc19e, 0xce7f, 0xc19e, 0x21, 0 + .dw 0xcec0, 0xc19e, 0xceff, 0xc19e, 0x21, 0 + .dw 0xcf40, 0xc19e, 0xcf7f, 0xc19e, 0x21, 0 + .dw 0xcfc0, 0xc19e, 0xcfff, 0xc19e, 0x21, 0 + .dw 0xd040, 0xc19e, 0xd07f, 0xc19e, 0x21, 0 + .dw 0xd0c0, 0xc19e, 0xd0ff, 0xc19e, 0x21, 0 + .dw 0xd140, 0xc19e, 0xd17f, 0xc19e, 0x21, 0 + .dw 0xd1c0, 0xc19e, 0xd1ff, 0xc19e, 0x21, 0 + .dw 0xd240, 0xc19e, 0xd27f, 0xc19e, 0x21, 0 + .dw 0xd2c0, 0xc19e, 0xd2ff, 0xc19e, 0x21, 0 + .dw 0xd340, 0xc19e, 0xd37f, 0xc19e, 0x21, 0 + .dw 0xd3c0, 0xc19e, 0xd3ff, 0xc19e, 0x21, 0 + .dw 0xd440, 0xc19e, 0xd47f, 0xc19e, 0x21, 0 + .dw 0xd4c0, 0xc19e, 0xd4ff, 0xc19e, 0x21, 0 + .dw 0xd540, 0xc19e, 0xd57f, 0xc19e, 0x21, 0 + .dw 0xd5c0, 0xc19e, 0xd5ff, 0xc19e, 0x21, 0 + .dw 0xd640, 0xc19e, 0xd67f, 0xc19e, 0x21, 0 + .dw 0xd6c0, 0xc19e, 0xd6ff, 0xc19e, 0x21, 0 + .dw 0xd740, 0xc19e, 0xd77f, 0xc19e, 0x21, 0 + .dw 0xd7c0, 0xc19e, 0xd7ff, 0xc19e, 0x21, 0 + .dw 0xd840, 0xc19e, 0xd87f, 0xc19e, 0x21, 0 + .dw 0xd8c0, 0xc19e, 0xd8ff, 0xc19e, 0x21, 0 + .dw 0xd940, 0xc19e, 0xd97f, 0xc19e, 0x21, 0 + .dw 0xd9c0, 0xc19e, 0xdfff, 0xc19e, 0x21, 0 + .dw 0xe040, 0xc19e, 0xe07f, 0xc19e, 0x21, 0 + .dw 0xe0c0, 0xc19e, 0xe0ff, 0xc19e, 0x21, 0 + .dw 0xe140, 0xc19e, 0xe17f, 0xc19e, 0x21, 0 + .dw 0xe1c0, 0xc19e, 0xe1ff, 0xc19e, 0x21, 0 + .dw 0xe240, 0xc19e, 0xe27f, 0xc19e, 0x21, 0 + .dw 0xe2c0, 0xc19e, 0xe2ff, 0xc19e, 0x21, 0 + .dw 0xe340, 0xc19e, 0xe37f, 0xc19e, 0x21, 0 + .dw 0xe3c0, 0xc19e, 0xe3ff, 0xc19e, 0x21, 0 + .dw 0xe440, 0xc19e, 0xe47f, 0xc19e, 0x21, 0 + .dw 0xe4c0, 0xc19e, 0xe4ff, 0xc19e, 0x21, 0 + .dw 0xe540, 0xc19e, 0xe57f, 0xc19e, 0x21, 0 + .dw 0xe5c0, 0xc19e, 0xe5ff, 0xc19e, 0x21, 0 + .dw 0xe640, 0xc19e, 0xe67f, 0xc19e, 0x21, 0 + .dw 0xe6c0, 0xc19e, 0xe6ff, 0xc19e, 0x21, 0 + .dw 0xe740, 0xc19e, 0xe77f, 0xc19e, 0x21, 0 + .dw 0xe7c0, 0xc19e, 0xe7ff, 0xc19e, 0x21, 0 + .dw 0xe840, 0xc19e, 0xe87f, 0xc19e, 0x21, 0 + .dw 0xe8c0, 0xc19e, 0xe8ff, 0xc19e, 0x21, 0 + .dw 0xe940, 0xc19e, 0xe97f, 0xc19e, 0x21, 0 + .dw 0xe9c0, 0xc19e, 0xe9ff, 0xc19e, 0x21, 0 + .dw 0xea40, 0xc19e, 0xea7f, 0xc19e, 0x21, 0 + .dw 0xeac0, 0xc19e, 0xeaff, 0xc19e, 0x21, 0 + .dw 0xeb40, 0xc19e, 0xeb7f, 0xc19e, 0x21, 0 + .dw 0xebc0, 0xc19e, 0xebff, 0xc19e, 0x21, 0 + .dw 0xec40, 0xc19e, 0xec7f, 0xc19e, 0x21, 0 + .dw 0xecc0, 0xc19e, 0xecff, 0xc19e, 0x21, 0 + .dw 0xed40, 0xc19e, 0xed7f, 0xc19e, 0x21, 0 + .dw 0xedc0, 0xc19e, 0xedff, 0xc19e, 0x21, 0 + .dw 0xee40, 0xc19e, 0xee7f, 0xc19e, 0x21, 0 + .dw 0xeec0, 0xc19e, 0xeeff, 0xc19e, 0x21, 0 + .dw 0xef40, 0xc19e, 0xef7f, 0xc19e, 0x21, 0 + .dw 0xefc0, 0xc19e, 0xefff, 0xc19e, 0x21, 0 + .dw 0xf040, 0xc19e, 0xf07f, 0xc19e, 0x21, 0 + .dw 0xf0c0, 0xc19e, 0xf0ff, 0xc19e, 0x21, 0 + .dw 0xf140, 0xc19e, 0xf17f, 0xc19e, 0x21, 0 + .dw 0xf1c0, 0xc19e, 0xf1ff, 0xc19e, 0x21, 0 + .dw 0xf240, 0xc19e, 0xf27f, 0xc19e, 0x21, 0 + .dw 0xf2c0, 0xc19e, 0xf2ff, 0xc19e, 0x21, 0 + .dw 0xf340, 0xc19e, 0xf37f, 0xc19e, 0x21, 0 + .dw 0xf3c0, 0xc19e, 0xf3ff, 0xc19e, 0x21, 0 + .dw 0xf440, 0xc19e, 0xf47f, 0xc19e, 0x21, 0 + .dw 0xf4c0, 0xc19e, 0xf4ff, 0xc19e, 0x21, 0 + .dw 0xf540, 0xc19e, 0xf57f, 0xc19e, 0x21, 0 + .dw 0xf5c0, 0xc19e, 0xf5ff, 0xc19e, 0x21, 0 + .dw 0xf640, 0xc19e, 0xf67f, 0xc19e, 0x21, 0 + .dw 0xf6c0, 0xc19e, 0xf6ff, 0xc19e, 0x21, 0 + .dw 0xf740, 0xc19e, 0xf77f, 0xc19e, 0x21, 0 + .dw 0xf7c0, 0xc19e, 0xf7ff, 0xc19e, 0x21, 0 + .dw 0xf840, 0xc19e, 0xf87f, 0xc19e, 0x21, 0 + .dw 0xf8c0, 0xc19e, 0xf8ff, 0xc19e, 0x21, 0 + .dw 0xf940, 0xc19e, 0xf97f, 0xc19e, 0x21, 0 + .dw 0xf9c0, 0xc19e, 0xffff, 0xc19e, 0x21, 0 + .dw 0x0040, 0xc19f, 0x007f, 0xc19f, 0x21, 0 + .dw 0x00c0, 0xc19f, 0x00ff, 0xc19f, 0x21, 0 + .dw 0x0140, 0xc19f, 0x017f, 0xc19f, 0x21, 0 + .dw 0x01c0, 0xc19f, 0x01ff, 0xc19f, 0x21, 0 + .dw 0x0240, 0xc19f, 0x027f, 0xc19f, 0x21, 0 + .dw 0x02c0, 0xc19f, 0x02ff, 0xc19f, 0x21, 0 + .dw 0x0340, 0xc19f, 0x037f, 0xc19f, 0x21, 0 + .dw 0x03c0, 0xc19f, 0x03ff, 0xc19f, 0x21, 0 + .dw 0x0440, 0xc19f, 0x047f, 0xc19f, 0x21, 0 + .dw 0x04c0, 0xc19f, 0x04ff, 0xc19f, 0x21, 0 + .dw 0x0540, 0xc19f, 0x057f, 0xc19f, 0x21, 0 + .dw 0x05c0, 0xc19f, 0x05ff, 0xc19f, 0x21, 0 + .dw 0x0640, 0xc19f, 0x067f, 0xc19f, 0x21, 0 + .dw 0x06c0, 0xc19f, 0x06ff, 0xc19f, 0x21, 0 + .dw 0x0740, 0xc19f, 0x077f, 0xc19f, 0x21, 0 + .dw 0x07c0, 0xc19f, 0x07ff, 0xc19f, 0x21, 0 + .dw 0x0840, 0xc19f, 0x087f, 0xc19f, 0x21, 0 + .dw 0x08c0, 0xc19f, 0x08ff, 0xc19f, 0x21, 0 + .dw 0x0940, 0xc19f, 0x097f, 0xc19f, 0x21, 0 + .dw 0x09c0, 0xc19f, 0x09ff, 0xc19f, 0x21, 0 + .dw 0x0a40, 0xc19f, 0x0a7f, 0xc19f, 0x21, 0 + .dw 0x0ac0, 0xc19f, 0x0aff, 0xc19f, 0x21, 0 + .dw 0x0b40, 0xc19f, 0x0b7f, 0xc19f, 0x21, 0 + .dw 0x0bc0, 0xc19f, 0x0bff, 0xc19f, 0x21, 0 + .dw 0x0c40, 0xc19f, 0x0c7f, 0xc19f, 0x21, 0 + .dw 0x0cc0, 0xc19f, 0x0cff, 0xc19f, 0x21, 0 + .dw 0x0d40, 0xc19f, 0x0d7f, 0xc19f, 0x21, 0 + .dw 0x0dc0, 0xc19f, 0x0dff, 0xc19f, 0x21, 0 + .dw 0x0e40, 0xc19f, 0x0e7f, 0xc19f, 0x21, 0 + .dw 0x0ec0, 0xc19f, 0x0eff, 0xc19f, 0x21, 0 + .dw 0x0f40, 0xc19f, 0x0f7f, 0xc19f, 0x21, 0 + .dw 0x0fc0, 0xc19f, 0x0fff, 0xc19f, 0x21, 0 + .dw 0x1040, 0xc19f, 0x107f, 0xc19f, 0x21, 0 + .dw 0x10c0, 0xc19f, 0x10ff, 0xc19f, 0x21, 0 + .dw 0x1140, 0xc19f, 0x117f, 0xc19f, 0x21, 0 + .dw 0x11c0, 0xc19f, 0x11ff, 0xc19f, 0x21, 0 + .dw 0x1240, 0xc19f, 0x127f, 0xc19f, 0x21, 0 + .dw 0x12c0, 0xc19f, 0x12ff, 0xc19f, 0x21, 0 + .dw 0x1340, 0xc19f, 0x137f, 0xc19f, 0x21, 0 + .dw 0x13c0, 0xc19f, 0x13ff, 0xc19f, 0x21, 0 + .dw 0x1440, 0xc19f, 0x147f, 0xc19f, 0x21, 0 + .dw 0x14c0, 0xc19f, 0x14ff, 0xc19f, 0x21, 0 + .dw 0x1540, 0xc19f, 0x157f, 0xc19f, 0x21, 0 + .dw 0x15c0, 0xc19f, 0x15ff, 0xc19f, 0x21, 0 + .dw 0x1640, 0xc19f, 0x167f, 0xc19f, 0x21, 0 + .dw 0x16c0, 0xc19f, 0x16ff, 0xc19f, 0x21, 0 + .dw 0x1740, 0xc19f, 0x177f, 0xc19f, 0x21, 0 + .dw 0x17c0, 0xc19f, 0x17ff, 0xc19f, 0x21, 0 + .dw 0x1840, 0xc19f, 0x187f, 0xc19f, 0x21, 0 + .dw 0x18c0, 0xc19f, 0x18ff, 0xc19f, 0x21, 0 + .dw 0x1940, 0xc19f, 0x197f, 0xc19f, 0x21, 0 + .dw 0x19c0, 0xc19f, 0x1fff, 0xc19f, 0x21, 0 + .dw 0x2040, 0xc19f, 0x207f, 0xc19f, 0x21, 0 + .dw 0x20c0, 0xc19f, 0x20ff, 0xc19f, 0x21, 0 + .dw 0x2140, 0xc19f, 0x217f, 0xc19f, 0x21, 0 + .dw 0x21c0, 0xc19f, 0x21ff, 0xc19f, 0x21, 0 + .dw 0x2240, 0xc19f, 0x227f, 0xc19f, 0x21, 0 + .dw 0x22c0, 0xc19f, 0x22ff, 0xc19f, 0x21, 0 + .dw 0x2340, 0xc19f, 0x237f, 0xc19f, 0x21, 0 + .dw 0x23c0, 0xc19f, 0x23ff, 0xc19f, 0x21, 0 + .dw 0x2440, 0xc19f, 0x247f, 0xc19f, 0x21, 0 + .dw 0x24c0, 0xc19f, 0x24ff, 0xc19f, 0x21, 0 + .dw 0x2540, 0xc19f, 0x257f, 0xc19f, 0x21, 0 + .dw 0x25c0, 0xc19f, 0x25ff, 0xc19f, 0x21, 0 + .dw 0x2640, 0xc19f, 0x267f, 0xc19f, 0x21, 0 + .dw 0x26c0, 0xc19f, 0x26ff, 0xc19f, 0x21, 0 + .dw 0x2740, 0xc19f, 0x277f, 0xc19f, 0x21, 0 + .dw 0x27c0, 0xc19f, 0x27ff, 0xc19f, 0x21, 0 + .dw 0x2840, 0xc19f, 0x287f, 0xc19f, 0x21, 0 + .dw 0x28c0, 0xc19f, 0x28ff, 0xc19f, 0x21, 0 + .dw 0x2940, 0xc19f, 0x297f, 0xc19f, 0x21, 0 + .dw 0x29c0, 0xc19f, 0x29ff, 0xc19f, 0x21, 0 + .dw 0x2a40, 0xc19f, 0x2a7f, 0xc19f, 0x21, 0 + .dw 0x2ac0, 0xc19f, 0x2aff, 0xc19f, 0x21, 0 + .dw 0x2b40, 0xc19f, 0x2b7f, 0xc19f, 0x21, 0 + .dw 0x2bc0, 0xc19f, 0x2bff, 0xc19f, 0x21, 0 + .dw 0x2c40, 0xc19f, 0x2c7f, 0xc19f, 0x21, 0 + .dw 0x2cc0, 0xc19f, 0x2cff, 0xc19f, 0x21, 0 + .dw 0x2d40, 0xc19f, 0x2d7f, 0xc19f, 0x21, 0 + .dw 0x2dc0, 0xc19f, 0x2dff, 0xc19f, 0x21, 0 + .dw 0x2e40, 0xc19f, 0x2e7f, 0xc19f, 0x21, 0 + .dw 0x2ec0, 0xc19f, 0x2eff, 0xc19f, 0x21, 0 + .dw 0x2f40, 0xc19f, 0x2f7f, 0xc19f, 0x21, 0 + .dw 0x2fc0, 0xc19f, 0x2fff, 0xc19f, 0x21, 0 + .dw 0x3040, 0xc19f, 0x307f, 0xc19f, 0x21, 0 + .dw 0x30c0, 0xc19f, 0x30ff, 0xc19f, 0x21, 0 + .dw 0x3140, 0xc19f, 0x317f, 0xc19f, 0x21, 0 + .dw 0x31c0, 0xc19f, 0x31ff, 0xc19f, 0x21, 0 + .dw 0x3240, 0xc19f, 0x327f, 0xc19f, 0x21, 0 + .dw 0x32c0, 0xc19f, 0x32ff, 0xc19f, 0x21, 0 + .dw 0x3340, 0xc19f, 0x337f, 0xc19f, 0x21, 0 + .dw 0x33c0, 0xc19f, 0x33ff, 0xc19f, 0x21, 0 + .dw 0x3440, 0xc19f, 0x347f, 0xc19f, 0x21, 0 + .dw 0x34c0, 0xc19f, 0x34ff, 0xc19f, 0x21, 0 + .dw 0x3540, 0xc19f, 0x357f, 0xc19f, 0x21, 0 + .dw 0x35c0, 0xc19f, 0x35ff, 0xc19f, 0x21, 0 + .dw 0x3640, 0xc19f, 0x367f, 0xc19f, 0x21, 0 + .dw 0x36c0, 0xc19f, 0x36ff, 0xc19f, 0x21, 0 + .dw 0x3740, 0xc19f, 0x377f, 0xc19f, 0x21, 0 + .dw 0x37c0, 0xc19f, 0x37ff, 0xc19f, 0x21, 0 + .dw 0x3840, 0xc19f, 0x387f, 0xc19f, 0x21, 0 + .dw 0x38c0, 0xc19f, 0x38ff, 0xc19f, 0x21, 0 + .dw 0x3940, 0xc19f, 0x397f, 0xc19f, 0x21, 0 + .dw 0x39c0, 0xc19f, 0x1fff, 0xc200, 0x21, 0 + .dw 0x2800, 0xc200, 0xffff, 0xc203, 0x21, 0 + .dw 0x0200, 0xc204, 0x1fff, 0xc204, 0x21, 0 + .dw 0x2800, 0xc204, 0x3fff, 0xc204, 0x21, 0 + .dw 0x4200, 0xc204, 0x5fff, 0xc204, 0x21, 0 + .dw 0x6800, 0xc204, 0x7fff, 0xc204, 0x21, 0 + .dw 0x8200, 0xc204, 0x9fff, 0xc204, 0x21, 0 + .dw 0xa800, 0xc204, 0xbfff, 0xc204, 0x21, 0 + .dw 0xc200, 0xc204, 0xdfff, 0xc204, 0x21, 0 + .dw 0xe800, 0xc204, 0x1fff, 0xc208, 0x21, 0 + .dw 0x2040, 0xc208, 0x207f, 0xc208, 0x21, 0 + .dw 0x20c0, 0xc208, 0x20ff, 0xc208, 0x21, 0 + .dw 0x2140, 0xc208, 0x217f, 0xc208, 0x21, 0 + .dw 0x21c0, 0xc208, 0x21ff, 0xc208, 0x21, 0 + .dw 0x2240, 0xc208, 0x227f, 0xc208, 0x21, 0 + .dw 0x22c0, 0xc208, 0x22ff, 0xc208, 0x21, 0 + .dw 0x2340, 0xc208, 0x237f, 0xc208, 0x21, 0 + .dw 0x23c0, 0xc208, 0x23ff, 0xc208, 0x21, 0 + .dw 0x2440, 0xc208, 0x247f, 0xc208, 0x21, 0 + .dw 0x24c0, 0xc208, 0x24ff, 0xc208, 0x21, 0 + .dw 0x2540, 0xc208, 0x257f, 0xc208, 0x21, 0 + .dw 0x25c0, 0xc208, 0x25ff, 0xc208, 0x21, 0 + .dw 0x2640, 0xc208, 0x267f, 0xc208, 0x21, 0 + .dw 0x26c0, 0xc208, 0x26ff, 0xc208, 0x21, 0 + .dw 0x2740, 0xc208, 0x277f, 0xc208, 0x21, 0 + .dw 0x27c0, 0xc208, 0xffff, 0xc20b, 0x21, 0 + .dw 0x0040, 0xc20c, 0x007f, 0xc20c, 0x21, 0 + .dw 0x00c0, 0xc20c, 0x00ff, 0xc20c, 0x21, 0 + .dw 0x0140, 0xc20c, 0x017f, 0xc20c, 0x21, 0 + .dw 0x01c0, 0xc20c, 0x1fff, 0xc20c, 0x21, 0 + .dw 0x2040, 0xc20c, 0x207f, 0xc20c, 0x21, 0 + .dw 0x20c0, 0xc20c, 0x20ff, 0xc20c, 0x21, 0 + .dw 0x2140, 0xc20c, 0x217f, 0xc20c, 0x21, 0 + .dw 0x21c0, 0xc20c, 0x21ff, 0xc20c, 0x21, 0 + .dw 0x2240, 0xc20c, 0x227f, 0xc20c, 0x21, 0 + .dw 0x22c0, 0xc20c, 0x22ff, 0xc20c, 0x21, 0 + .dw 0x2340, 0xc20c, 0x237f, 0xc20c, 0x21, 0 + .dw 0x23c0, 0xc20c, 0x23ff, 0xc20c, 0x21, 0 + .dw 0x2440, 0xc20c, 0x247f, 0xc20c, 0x21, 0 + .dw 0x24c0, 0xc20c, 0x24ff, 0xc20c, 0x21, 0 + .dw 0x2540, 0xc20c, 0x257f, 0xc20c, 0x21, 0 + .dw 0x25c0, 0xc20c, 0x25ff, 0xc20c, 0x21, 0 + .dw 0x2640, 0xc20c, 0x267f, 0xc20c, 0x21, 0 + .dw 0x26c0, 0xc20c, 0x26ff, 0xc20c, 0x21, 0 + .dw 0x2740, 0xc20c, 0x277f, 0xc20c, 0x21, 0 + .dw 0x27c0, 0xc20c, 0x3fff, 0xc20c, 0x21, 0 + .dw 0x4040, 0xc20c, 0x407f, 0xc20c, 0x21, 0 + .dw 0x40c0, 0xc20c, 0x40ff, 0xc20c, 0x21, 0 + .dw 0x4140, 0xc20c, 0x417f, 0xc20c, 0x21, 0 + .dw 0x41c0, 0xc20c, 0x5fff, 0xc20c, 0x21, 0 + .dw 0x6040, 0xc20c, 0x607f, 0xc20c, 0x21, 0 + .dw 0x60c0, 0xc20c, 0x60ff, 0xc20c, 0x21, 0 + .dw 0x6140, 0xc20c, 0x617f, 0xc20c, 0x21, 0 + .dw 0x61c0, 0xc20c, 0x61ff, 0xc20c, 0x21, 0 + .dw 0x6240, 0xc20c, 0x627f, 0xc20c, 0x21, 0 + .dw 0x62c0, 0xc20c, 0x62ff, 0xc20c, 0x21, 0 + .dw 0x6340, 0xc20c, 0x637f, 0xc20c, 0x21, 0 + .dw 0x63c0, 0xc20c, 0x63ff, 0xc20c, 0x21, 0 + .dw 0x6440, 0xc20c, 0x647f, 0xc20c, 0x21, 0 + .dw 0x64c0, 0xc20c, 0x64ff, 0xc20c, 0x21, 0 + .dw 0x6540, 0xc20c, 0x657f, 0xc20c, 0x21, 0 + .dw 0x65c0, 0xc20c, 0x65ff, 0xc20c, 0x21, 0 + .dw 0x6640, 0xc20c, 0x667f, 0xc20c, 0x21, 0 + .dw 0x66c0, 0xc20c, 0x66ff, 0xc20c, 0x21, 0 + .dw 0x6740, 0xc20c, 0x677f, 0xc20c, 0x21, 0 + .dw 0x67c0, 0xc20c, 0x7fff, 0xc20c, 0x21, 0 + .dw 0x8040, 0xc20c, 0x807f, 0xc20c, 0x21, 0 + .dw 0x80c0, 0xc20c, 0x80ff, 0xc20c, 0x21, 0 + .dw 0x8140, 0xc20c, 0x817f, 0xc20c, 0x21, 0 + .dw 0x81c0, 0xc20c, 0x9fff, 0xc20c, 0x21, 0 + .dw 0xa040, 0xc20c, 0xa07f, 0xc20c, 0x21, 0 + .dw 0xa0c0, 0xc20c, 0xa0ff, 0xc20c, 0x21, 0 + .dw 0xa140, 0xc20c, 0xa17f, 0xc20c, 0x21, 0 + .dw 0xa1c0, 0xc20c, 0xa1ff, 0xc20c, 0x21, 0 + .dw 0xa240, 0xc20c, 0xa27f, 0xc20c, 0x21, 0 + .dw 0xa2c0, 0xc20c, 0xa2ff, 0xc20c, 0x21, 0 + .dw 0xa340, 0xc20c, 0xa37f, 0xc20c, 0x21, 0 + .dw 0xa3c0, 0xc20c, 0xa3ff, 0xc20c, 0x21, 0 + .dw 0xa440, 0xc20c, 0xa47f, 0xc20c, 0x21, 0 + .dw 0xa4c0, 0xc20c, 0xa4ff, 0xc20c, 0x21, 0 + .dw 0xa540, 0xc20c, 0xa57f, 0xc20c, 0x21, 0 + .dw 0xa5c0, 0xc20c, 0xa5ff, 0xc20c, 0x21, 0 + .dw 0xa640, 0xc20c, 0xa67f, 0xc20c, 0x21, 0 + .dw 0xa6c0, 0xc20c, 0xa6ff, 0xc20c, 0x21, 0 + .dw 0xa740, 0xc20c, 0xa77f, 0xc20c, 0x21, 0 + .dw 0xa7c0, 0xc20c, 0xbfff, 0xc20c, 0x21, 0 + .dw 0xc040, 0xc20c, 0xc07f, 0xc20c, 0x21, 0 + .dw 0xc0c0, 0xc20c, 0xc0ff, 0xc20c, 0x21, 0 + .dw 0xc140, 0xc20c, 0xc17f, 0xc20c, 0x21, 0 + .dw 0xc1c0, 0xc20c, 0xdfff, 0xc20c, 0x21, 0 + .dw 0xe040, 0xc20c, 0xe07f, 0xc20c, 0x21, 0 + .dw 0xe0c0, 0xc20c, 0xe0ff, 0xc20c, 0x21, 0 + .dw 0xe140, 0xc20c, 0xe17f, 0xc20c, 0x21, 0 + .dw 0xe1c0, 0xc20c, 0xe1ff, 0xc20c, 0x21, 0 + .dw 0xe240, 0xc20c, 0xe27f, 0xc20c, 0x21, 0 + .dw 0xe2c0, 0xc20c, 0xe2ff, 0xc20c, 0x21, 0 + .dw 0xe340, 0xc20c, 0xe37f, 0xc20c, 0x21, 0 + .dw 0xe3c0, 0xc20c, 0xe3ff, 0xc20c, 0x21, 0 + .dw 0xe440, 0xc20c, 0xe47f, 0xc20c, 0x21, 0 + .dw 0xe4c0, 0xc20c, 0xe4ff, 0xc20c, 0x21, 0 + .dw 0xe540, 0xc20c, 0xe57f, 0xc20c, 0x21, 0 + .dw 0xe5c0, 0xc20c, 0xe5ff, 0xc20c, 0x21, 0 + .dw 0xe640, 0xc20c, 0xe67f, 0xc20c, 0x21, 0 + .dw 0xe6c0, 0xc20c, 0xe6ff, 0xc20c, 0x21, 0 + .dw 0xe740, 0xc20c, 0xe77f, 0xc20c, 0x21, 0 + .dw 0xe7c0, 0xc20c, 0xffff, 0xc213, 0x21, 0 + .dw 0x0200, 0xc214, 0x1fff, 0xc214, 0x21, 0 + .dw 0x2800, 0xc214, 0x3fff, 0xc214, 0x21, 0 + .dw 0x4200, 0xc214, 0x5fff, 0xc214, 0x21, 0 + .dw 0x6800, 0xc214, 0x7fff, 0xc214, 0x21, 0 + .dw 0x8200, 0xc214, 0x9fff, 0xc214, 0x21, 0 + .dw 0xa800, 0xc214, 0xbfff, 0xc214, 0x21, 0 + .dw 0xc200, 0xc214, 0xdfff, 0xc214, 0x21, 0 + .dw 0xe800, 0xc214, 0xffff, 0xc21b, 0x21, 0 + .dw 0x0040, 0xc21c, 0x007f, 0xc21c, 0x21, 0 + .dw 0x00c0, 0xc21c, 0x00ff, 0xc21c, 0x21, 0 + .dw 0x0140, 0xc21c, 0x017f, 0xc21c, 0x21, 0 + .dw 0x01c0, 0xc21c, 0x1fff, 0xc21c, 0x21, 0 + .dw 0x2040, 0xc21c, 0x207f, 0xc21c, 0x21, 0 + .dw 0x20c0, 0xc21c, 0x20ff, 0xc21c, 0x21, 0 + .dw 0x2140, 0xc21c, 0x217f, 0xc21c, 0x21, 0 + .dw 0x21c0, 0xc21c, 0x21ff, 0xc21c, 0x21, 0 + .dw 0x2240, 0xc21c, 0x227f, 0xc21c, 0x21, 0 + .dw 0x22c0, 0xc21c, 0x22ff, 0xc21c, 0x21, 0 + .dw 0x2340, 0xc21c, 0x237f, 0xc21c, 0x21, 0 + .dw 0x23c0, 0xc21c, 0x23ff, 0xc21c, 0x21, 0 + .dw 0x2440, 0xc21c, 0x247f, 0xc21c, 0x21, 0 + .dw 0x24c0, 0xc21c, 0x24ff, 0xc21c, 0x21, 0 + .dw 0x2540, 0xc21c, 0x257f, 0xc21c, 0x21, 0 + .dw 0x25c0, 0xc21c, 0x25ff, 0xc21c, 0x21, 0 + .dw 0x2640, 0xc21c, 0x267f, 0xc21c, 0x21, 0 + .dw 0x26c0, 0xc21c, 0x26ff, 0xc21c, 0x21, 0 + .dw 0x2740, 0xc21c, 0x277f, 0xc21c, 0x21, 0 + .dw 0x27c0, 0xc21c, 0x3fff, 0xc21c, 0x21, 0 + .dw 0x4040, 0xc21c, 0x407f, 0xc21c, 0x21, 0 + .dw 0x40c0, 0xc21c, 0x40ff, 0xc21c, 0x21, 0 + .dw 0x4140, 0xc21c, 0x417f, 0xc21c, 0x21, 0 + .dw 0x41c0, 0xc21c, 0x5fff, 0xc21c, 0x21, 0 + .dw 0x6040, 0xc21c, 0x607f, 0xc21c, 0x21, 0 + .dw 0x60c0, 0xc21c, 0x60ff, 0xc21c, 0x21, 0 + .dw 0x6140, 0xc21c, 0x617f, 0xc21c, 0x21, 0 + .dw 0x61c0, 0xc21c, 0x61ff, 0xc21c, 0x21, 0 + .dw 0x6240, 0xc21c, 0x627f, 0xc21c, 0x21, 0 + .dw 0x62c0, 0xc21c, 0x62ff, 0xc21c, 0x21, 0 + .dw 0x6340, 0xc21c, 0x637f, 0xc21c, 0x21, 0 + .dw 0x63c0, 0xc21c, 0x63ff, 0xc21c, 0x21, 0 + .dw 0x6440, 0xc21c, 0x647f, 0xc21c, 0x21, 0 + .dw 0x64c0, 0xc21c, 0x64ff, 0xc21c, 0x21, 0 + .dw 0x6540, 0xc21c, 0x657f, 0xc21c, 0x21, 0 + .dw 0x65c0, 0xc21c, 0x65ff, 0xc21c, 0x21, 0 + .dw 0x6640, 0xc21c, 0x667f, 0xc21c, 0x21, 0 + .dw 0x66c0, 0xc21c, 0x66ff, 0xc21c, 0x21, 0 + .dw 0x6740, 0xc21c, 0x677f, 0xc21c, 0x21, 0 + .dw 0x67c0, 0xc21c, 0x7fff, 0xc21c, 0x21, 0 + .dw 0x8040, 0xc21c, 0x807f, 0xc21c, 0x21, 0 + .dw 0x80c0, 0xc21c, 0x80ff, 0xc21c, 0x21, 0 + .dw 0x8140, 0xc21c, 0x817f, 0xc21c, 0x21, 0 + .dw 0x81c0, 0xc21c, 0x9fff, 0xc21c, 0x21, 0 + .dw 0xa040, 0xc21c, 0xa07f, 0xc21c, 0x21, 0 + .dw 0xa0c0, 0xc21c, 0xa0ff, 0xc21c, 0x21, 0 + .dw 0xa140, 0xc21c, 0xa17f, 0xc21c, 0x21, 0 + .dw 0xa1c0, 0xc21c, 0xa1ff, 0xc21c, 0x21, 0 + .dw 0xa240, 0xc21c, 0xa27f, 0xc21c, 0x21, 0 + .dw 0xa2c0, 0xc21c, 0xa2ff, 0xc21c, 0x21, 0 + .dw 0xa340, 0xc21c, 0xa37f, 0xc21c, 0x21, 0 + .dw 0xa3c0, 0xc21c, 0xa3ff, 0xc21c, 0x21, 0 + .dw 0xa440, 0xc21c, 0xa47f, 0xc21c, 0x21, 0 + .dw 0xa4c0, 0xc21c, 0xa4ff, 0xc21c, 0x21, 0 + .dw 0xa540, 0xc21c, 0xa57f, 0xc21c, 0x21, 0 + .dw 0xa5c0, 0xc21c, 0xa5ff, 0xc21c, 0x21, 0 + .dw 0xa640, 0xc21c, 0xa67f, 0xc21c, 0x21, 0 + .dw 0xa6c0, 0xc21c, 0xa6ff, 0xc21c, 0x21, 0 + .dw 0xa740, 0xc21c, 0xa77f, 0xc21c, 0x21, 0 + .dw 0xa7c0, 0xc21c, 0xbfff, 0xc21c, 0x21, 0 + .dw 0xc040, 0xc21c, 0xc07f, 0xc21c, 0x21, 0 + .dw 0xc0c0, 0xc21c, 0xc0ff, 0xc21c, 0x21, 0 + .dw 0xc140, 0xc21c, 0xc17f, 0xc21c, 0x21, 0 + .dw 0xc1c0, 0xc21c, 0xdfff, 0xc21c, 0x21, 0 + .dw 0xe040, 0xc21c, 0xe07f, 0xc21c, 0x21, 0 + .dw 0xe0c0, 0xc21c, 0xe0ff, 0xc21c, 0x21, 0 + .dw 0xe140, 0xc21c, 0xe17f, 0xc21c, 0x21, 0 + .dw 0xe1c0, 0xc21c, 0xe1ff, 0xc21c, 0x21, 0 + .dw 0xe240, 0xc21c, 0xe27f, 0xc21c, 0x21, 0 + .dw 0xe2c0, 0xc21c, 0xe2ff, 0xc21c, 0x21, 0 + .dw 0xe340, 0xc21c, 0xe37f, 0xc21c, 0x21, 0 + .dw 0xe3c0, 0xc21c, 0xe3ff, 0xc21c, 0x21, 0 + .dw 0xe440, 0xc21c, 0xe47f, 0xc21c, 0x21, 0 + .dw 0xe4c0, 0xc21c, 0xe4ff, 0xc21c, 0x21, 0 + .dw 0xe540, 0xc21c, 0xe57f, 0xc21c, 0x21, 0 + .dw 0xe5c0, 0xc21c, 0xe5ff, 0xc21c, 0x21, 0 + .dw 0xe640, 0xc21c, 0xe67f, 0xc21c, 0x21, 0 + .dw 0xe6c0, 0xc21c, 0xe6ff, 0xc21c, 0x21, 0 + .dw 0xe740, 0xc21c, 0xe77f, 0xc21c, 0x21, 0 + .dw 0xe7c0, 0xc21c, 0x1fff, 0xc220, 0x21, 0 + .dw 0x2800, 0xc220, 0xffff, 0xc223, 0x21, 0 + .dw 0x0200, 0xc224, 0x1fff, 0xc224, 0x21, 0 + .dw 0x2800, 0xc224, 0x3fff, 0xc224, 0x21, 0 + .dw 0x4200, 0xc224, 0x5fff, 0xc224, 0x21, 0 + .dw 0x6800, 0xc224, 0x7fff, 0xc224, 0x21, 0 + .dw 0x8200, 0xc224, 0x9fff, 0xc224, 0x21, 0 + .dw 0xa800, 0xc224, 0xbfff, 0xc224, 0x21, 0 + .dw 0xc200, 0xc224, 0xdfff, 0xc224, 0x21, 0 + .dw 0xe800, 0xc224, 0x1fff, 0xc228, 0x21, 0 + .dw 0x2040, 0xc228, 0x207f, 0xc228, 0x21, 0 + .dw 0x20c0, 0xc228, 0x20ff, 0xc228, 0x21, 0 + .dw 0x2140, 0xc228, 0x217f, 0xc228, 0x21, 0 + .dw 0x21c0, 0xc228, 0x21ff, 0xc228, 0x21, 0 + .dw 0x2240, 0xc228, 0x227f, 0xc228, 0x21, 0 + .dw 0x22c0, 0xc228, 0x22ff, 0xc228, 0x21, 0 + .dw 0x2340, 0xc228, 0x237f, 0xc228, 0x21, 0 + .dw 0x23c0, 0xc228, 0x23ff, 0xc228, 0x21, 0 + .dw 0x2440, 0xc228, 0x247f, 0xc228, 0x21, 0 + .dw 0x24c0, 0xc228, 0x24ff, 0xc228, 0x21, 0 + .dw 0x2540, 0xc228, 0x257f, 0xc228, 0x21, 0 + .dw 0x25c0, 0xc228, 0x25ff, 0xc228, 0x21, 0 + .dw 0x2640, 0xc228, 0x267f, 0xc228, 0x21, 0 + .dw 0x26c0, 0xc228, 0x26ff, 0xc228, 0x21, 0 + .dw 0x2740, 0xc228, 0x277f, 0xc228, 0x21, 0 + .dw 0x27c0, 0xc228, 0xffff, 0xc22b, 0x21, 0 + .dw 0x0040, 0xc22c, 0x007f, 0xc22c, 0x21, 0 + .dw 0x00c0, 0xc22c, 0x00ff, 0xc22c, 0x21, 0 + .dw 0x0140, 0xc22c, 0x017f, 0xc22c, 0x21, 0 + .dw 0x01c0, 0xc22c, 0x1fff, 0xc22c, 0x21, 0 + .dw 0x2040, 0xc22c, 0x207f, 0xc22c, 0x21, 0 + .dw 0x20c0, 0xc22c, 0x20ff, 0xc22c, 0x21, 0 + .dw 0x2140, 0xc22c, 0x217f, 0xc22c, 0x21, 0 + .dw 0x21c0, 0xc22c, 0x21ff, 0xc22c, 0x21, 0 + .dw 0x2240, 0xc22c, 0x227f, 0xc22c, 0x21, 0 + .dw 0x22c0, 0xc22c, 0x22ff, 0xc22c, 0x21, 0 + .dw 0x2340, 0xc22c, 0x237f, 0xc22c, 0x21, 0 + .dw 0x23c0, 0xc22c, 0x23ff, 0xc22c, 0x21, 0 + .dw 0x2440, 0xc22c, 0x247f, 0xc22c, 0x21, 0 + .dw 0x24c0, 0xc22c, 0x24ff, 0xc22c, 0x21, 0 + .dw 0x2540, 0xc22c, 0x257f, 0xc22c, 0x21, 0 + .dw 0x25c0, 0xc22c, 0x25ff, 0xc22c, 0x21, 0 + .dw 0x2640, 0xc22c, 0x267f, 0xc22c, 0x21, 0 + .dw 0x26c0, 0xc22c, 0x26ff, 0xc22c, 0x21, 0 + .dw 0x2740, 0xc22c, 0x277f, 0xc22c, 0x21, 0 + .dw 0x27c0, 0xc22c, 0x3fff, 0xc22c, 0x21, 0 + .dw 0x4040, 0xc22c, 0x407f, 0xc22c, 0x21, 0 + .dw 0x40c0, 0xc22c, 0x40ff, 0xc22c, 0x21, 0 + .dw 0x4140, 0xc22c, 0x417f, 0xc22c, 0x21, 0 + .dw 0x41c0, 0xc22c, 0x5fff, 0xc22c, 0x21, 0 + .dw 0x6040, 0xc22c, 0x607f, 0xc22c, 0x21, 0 + .dw 0x60c0, 0xc22c, 0x60ff, 0xc22c, 0x21, 0 + .dw 0x6140, 0xc22c, 0x617f, 0xc22c, 0x21, 0 + .dw 0x61c0, 0xc22c, 0x61ff, 0xc22c, 0x21, 0 + .dw 0x6240, 0xc22c, 0x627f, 0xc22c, 0x21, 0 + .dw 0x62c0, 0xc22c, 0x62ff, 0xc22c, 0x21, 0 + .dw 0x6340, 0xc22c, 0x637f, 0xc22c, 0x21, 0 + .dw 0x63c0, 0xc22c, 0x63ff, 0xc22c, 0x21, 0 + .dw 0x6440, 0xc22c, 0x647f, 0xc22c, 0x21, 0 + .dw 0x64c0, 0xc22c, 0x64ff, 0xc22c, 0x21, 0 + .dw 0x6540, 0xc22c, 0x657f, 0xc22c, 0x21, 0 + .dw 0x65c0, 0xc22c, 0x65ff, 0xc22c, 0x21, 0 + .dw 0x6640, 0xc22c, 0x667f, 0xc22c, 0x21, 0 + .dw 0x66c0, 0xc22c, 0x66ff, 0xc22c, 0x21, 0 + .dw 0x6740, 0xc22c, 0x677f, 0xc22c, 0x21, 0 + .dw 0x67c0, 0xc22c, 0x7fff, 0xc22c, 0x21, 0 + .dw 0x8040, 0xc22c, 0x807f, 0xc22c, 0x21, 0 + .dw 0x80c0, 0xc22c, 0x80ff, 0xc22c, 0x21, 0 + .dw 0x8140, 0xc22c, 0x817f, 0xc22c, 0x21, 0 + .dw 0x81c0, 0xc22c, 0x9fff, 0xc22c, 0x21, 0 + .dw 0xa040, 0xc22c, 0xa07f, 0xc22c, 0x21, 0 + .dw 0xa0c0, 0xc22c, 0xa0ff, 0xc22c, 0x21, 0 + .dw 0xa140, 0xc22c, 0xa17f, 0xc22c, 0x21, 0 + .dw 0xa1c0, 0xc22c, 0xa1ff, 0xc22c, 0x21, 0 + .dw 0xa240, 0xc22c, 0xa27f, 0xc22c, 0x21, 0 + .dw 0xa2c0, 0xc22c, 0xa2ff, 0xc22c, 0x21, 0 + .dw 0xa340, 0xc22c, 0xa37f, 0xc22c, 0x21, 0 + .dw 0xa3c0, 0xc22c, 0xa3ff, 0xc22c, 0x21, 0 + .dw 0xa440, 0xc22c, 0xa47f, 0xc22c, 0x21, 0 + .dw 0xa4c0, 0xc22c, 0xa4ff, 0xc22c, 0x21, 0 + .dw 0xa540, 0xc22c, 0xa57f, 0xc22c, 0x21, 0 + .dw 0xa5c0, 0xc22c, 0xa5ff, 0xc22c, 0x21, 0 + .dw 0xa640, 0xc22c, 0xa67f, 0xc22c, 0x21, 0 + .dw 0xa6c0, 0xc22c, 0xa6ff, 0xc22c, 0x21, 0 + .dw 0xa740, 0xc22c, 0xa77f, 0xc22c, 0x21, 0 + .dw 0xa7c0, 0xc22c, 0xbfff, 0xc22c, 0x21, 0 + .dw 0xc040, 0xc22c, 0xc07f, 0xc22c, 0x21, 0 + .dw 0xc0c0, 0xc22c, 0xc0ff, 0xc22c, 0x21, 0 + .dw 0xc140, 0xc22c, 0xc17f, 0xc22c, 0x21, 0 + .dw 0xc1c0, 0xc22c, 0xdfff, 0xc22c, 0x21, 0 + .dw 0xe040, 0xc22c, 0xe07f, 0xc22c, 0x21, 0 + .dw 0xe0c0, 0xc22c, 0xe0ff, 0xc22c, 0x21, 0 + .dw 0xe140, 0xc22c, 0xe17f, 0xc22c, 0x21, 0 + .dw 0xe1c0, 0xc22c, 0xe1ff, 0xc22c, 0x21, 0 + .dw 0xe240, 0xc22c, 0xe27f, 0xc22c, 0x21, 0 + .dw 0xe2c0, 0xc22c, 0xe2ff, 0xc22c, 0x21, 0 + .dw 0xe340, 0xc22c, 0xe37f, 0xc22c, 0x21, 0 + .dw 0xe3c0, 0xc22c, 0xe3ff, 0xc22c, 0x21, 0 + .dw 0xe440, 0xc22c, 0xe47f, 0xc22c, 0x21, 0 + .dw 0xe4c0, 0xc22c, 0xe4ff, 0xc22c, 0x21, 0 + .dw 0xe540, 0xc22c, 0xe57f, 0xc22c, 0x21, 0 + .dw 0xe5c0, 0xc22c, 0xe5ff, 0xc22c, 0x21, 0 + .dw 0xe640, 0xc22c, 0xe67f, 0xc22c, 0x21, 0 + .dw 0xe6c0, 0xc22c, 0xe6ff, 0xc22c, 0x21, 0 + .dw 0xe740, 0xc22c, 0xe77f, 0xc22c, 0x21, 0 + .dw 0xe7c0, 0xc22c, 0xffff, 0xc233, 0x21, 0 + .dw 0x0200, 0xc234, 0x1fff, 0xc234, 0x21, 0 + .dw 0x2800, 0xc234, 0x3fff, 0xc234, 0x21, 0 + .dw 0x4200, 0xc234, 0x5fff, 0xc234, 0x21, 0 + .dw 0x6800, 0xc234, 0x7fff, 0xc234, 0x21, 0 + .dw 0x8200, 0xc234, 0x9fff, 0xc234, 0x21, 0 + .dw 0xa800, 0xc234, 0xbfff, 0xc234, 0x21, 0 + .dw 0xc200, 0xc234, 0xdfff, 0xc234, 0x21, 0 + .dw 0xe800, 0xc234, 0xffff, 0xc23b, 0x21, 0 + .dw 0x0040, 0xc23c, 0x007f, 0xc23c, 0x21, 0 + .dw 0x00c0, 0xc23c, 0x00ff, 0xc23c, 0x21, 0 + .dw 0x0140, 0xc23c, 0x017f, 0xc23c, 0x21, 0 + .dw 0x01c0, 0xc23c, 0x1fff, 0xc23c, 0x21, 0 + .dw 0x2040, 0xc23c, 0x207f, 0xc23c, 0x21, 0 + .dw 0x20c0, 0xc23c, 0x20ff, 0xc23c, 0x21, 0 + .dw 0x2140, 0xc23c, 0x217f, 0xc23c, 0x21, 0 + .dw 0x21c0, 0xc23c, 0x21ff, 0xc23c, 0x21, 0 + .dw 0x2240, 0xc23c, 0x227f, 0xc23c, 0x21, 0 + .dw 0x22c0, 0xc23c, 0x22ff, 0xc23c, 0x21, 0 + .dw 0x2340, 0xc23c, 0x237f, 0xc23c, 0x21, 0 + .dw 0x23c0, 0xc23c, 0x23ff, 0xc23c, 0x21, 0 + .dw 0x2440, 0xc23c, 0x247f, 0xc23c, 0x21, 0 + .dw 0x24c0, 0xc23c, 0x24ff, 0xc23c, 0x21, 0 + .dw 0x2540, 0xc23c, 0x257f, 0xc23c, 0x21, 0 + .dw 0x25c0, 0xc23c, 0x25ff, 0xc23c, 0x21, 0 + .dw 0x2640, 0xc23c, 0x267f, 0xc23c, 0x21, 0 + .dw 0x26c0, 0xc23c, 0x26ff, 0xc23c, 0x21, 0 + .dw 0x2740, 0xc23c, 0x277f, 0xc23c, 0x21, 0 + .dw 0x27c0, 0xc23c, 0x3fff, 0xc23c, 0x21, 0 + .dw 0x4040, 0xc23c, 0x407f, 0xc23c, 0x21, 0 + .dw 0x40c0, 0xc23c, 0x40ff, 0xc23c, 0x21, 0 + .dw 0x4140, 0xc23c, 0x417f, 0xc23c, 0x21, 0 + .dw 0x41c0, 0xc23c, 0x5fff, 0xc23c, 0x21, 0 + .dw 0x6040, 0xc23c, 0x607f, 0xc23c, 0x21, 0 + .dw 0x60c0, 0xc23c, 0x60ff, 0xc23c, 0x21, 0 + .dw 0x6140, 0xc23c, 0x617f, 0xc23c, 0x21, 0 + .dw 0x61c0, 0xc23c, 0x61ff, 0xc23c, 0x21, 0 + .dw 0x6240, 0xc23c, 0x627f, 0xc23c, 0x21, 0 + .dw 0x62c0, 0xc23c, 0x62ff, 0xc23c, 0x21, 0 + .dw 0x6340, 0xc23c, 0x637f, 0xc23c, 0x21, 0 + .dw 0x63c0, 0xc23c, 0x63ff, 0xc23c, 0x21, 0 + .dw 0x6440, 0xc23c, 0x647f, 0xc23c, 0x21, 0 + .dw 0x64c0, 0xc23c, 0x64ff, 0xc23c, 0x21, 0 + .dw 0x6540, 0xc23c, 0x657f, 0xc23c, 0x21, 0 + .dw 0x65c0, 0xc23c, 0x65ff, 0xc23c, 0x21, 0 + .dw 0x6640, 0xc23c, 0x667f, 0xc23c, 0x21, 0 + .dw 0x66c0, 0xc23c, 0x66ff, 0xc23c, 0x21, 0 + .dw 0x6740, 0xc23c, 0x677f, 0xc23c, 0x21, 0 + .dw 0x67c0, 0xc23c, 0x7fff, 0xc23c, 0x21, 0 + .dw 0x8040, 0xc23c, 0x807f, 0xc23c, 0x21, 0 + .dw 0x80c0, 0xc23c, 0x80ff, 0xc23c, 0x21, 0 + .dw 0x8140, 0xc23c, 0x817f, 0xc23c, 0x21, 0 + .dw 0x81c0, 0xc23c, 0x9fff, 0xc23c, 0x21, 0 + .dw 0xa040, 0xc23c, 0xa07f, 0xc23c, 0x21, 0 + .dw 0xa0c0, 0xc23c, 0xa0ff, 0xc23c, 0x21, 0 + .dw 0xa140, 0xc23c, 0xa17f, 0xc23c, 0x21, 0 + .dw 0xa1c0, 0xc23c, 0xa1ff, 0xc23c, 0x21, 0 + .dw 0xa240, 0xc23c, 0xa27f, 0xc23c, 0x21, 0 + .dw 0xa2c0, 0xc23c, 0xa2ff, 0xc23c, 0x21, 0 + .dw 0xa340, 0xc23c, 0xa37f, 0xc23c, 0x21, 0 + .dw 0xa3c0, 0xc23c, 0xa3ff, 0xc23c, 0x21, 0 + .dw 0xa440, 0xc23c, 0xa47f, 0xc23c, 0x21, 0 + .dw 0xa4c0, 0xc23c, 0xa4ff, 0xc23c, 0x21, 0 + .dw 0xa540, 0xc23c, 0xa57f, 0xc23c, 0x21, 0 + .dw 0xa5c0, 0xc23c, 0xa5ff, 0xc23c, 0x21, 0 + .dw 0xa640, 0xc23c, 0xa67f, 0xc23c, 0x21, 0 + .dw 0xa6c0, 0xc23c, 0xa6ff, 0xc23c, 0x21, 0 + .dw 0xa740, 0xc23c, 0xa77f, 0xc23c, 0x21, 0 + .dw 0xa7c0, 0xc23c, 0xbfff, 0xc23c, 0x21, 0 + .dw 0xc040, 0xc23c, 0xc07f, 0xc23c, 0x21, 0 + .dw 0xc0c0, 0xc23c, 0xc0ff, 0xc23c, 0x21, 0 + .dw 0xc140, 0xc23c, 0xc17f, 0xc23c, 0x21, 0 + .dw 0xc1c0, 0xc23c, 0xdfff, 0xc23c, 0x21, 0 + .dw 0xe040, 0xc23c, 0xe07f, 0xc23c, 0x21, 0 + .dw 0xe0c0, 0xc23c, 0xe0ff, 0xc23c, 0x21, 0 + .dw 0xe140, 0xc23c, 0xe17f, 0xc23c, 0x21, 0 + .dw 0xe1c0, 0xc23c, 0xe1ff, 0xc23c, 0x21, 0 + .dw 0xe240, 0xc23c, 0xe27f, 0xc23c, 0x21, 0 + .dw 0xe2c0, 0xc23c, 0xe2ff, 0xc23c, 0x21, 0 + .dw 0xe340, 0xc23c, 0xe37f, 0xc23c, 0x21, 0 + .dw 0xe3c0, 0xc23c, 0xe3ff, 0xc23c, 0x21, 0 + .dw 0xe440, 0xc23c, 0xe47f, 0xc23c, 0x21, 0 + .dw 0xe4c0, 0xc23c, 0xe4ff, 0xc23c, 0x21, 0 + .dw 0xe540, 0xc23c, 0xe57f, 0xc23c, 0x21, 0 + .dw 0xe5c0, 0xc23c, 0xe5ff, 0xc23c, 0x21, 0 + .dw 0xe640, 0xc23c, 0xe67f, 0xc23c, 0x21, 0 + .dw 0xe6c0, 0xc23c, 0xe6ff, 0xc23c, 0x21, 0 + .dw 0xe740, 0xc23c, 0xe77f, 0xc23c, 0x21, 0 + .dw 0xe7c0, 0xc23c, 0x1fff, 0xc240, 0x21, 0 + .dw 0x2800, 0xc240, 0xffff, 0xc243, 0x21, 0 + .dw 0x0200, 0xc244, 0x1fff, 0xc244, 0x21, 0 + .dw 0x2800, 0xc244, 0x3fff, 0xc244, 0x21, 0 + .dw 0x4200, 0xc244, 0x5fff, 0xc244, 0x21, 0 + .dw 0x6800, 0xc244, 0x7fff, 0xc244, 0x21, 0 + .dw 0x8200, 0xc244, 0x9fff, 0xc244, 0x21, 0 + .dw 0xa800, 0xc244, 0xbfff, 0xc244, 0x21, 0 + .dw 0xc200, 0xc244, 0xdfff, 0xc244, 0x21, 0 + .dw 0xe800, 0xc244, 0xffff, 0xc253, 0x21, 0 + .dw 0x0200, 0xc254, 0x1fff, 0xc254, 0x21, 0 + .dw 0x2800, 0xc254, 0x3fff, 0xc254, 0x21, 0 + .dw 0x4200, 0xc254, 0x5fff, 0xc254, 0x21, 0 + .dw 0x6800, 0xc254, 0x7fff, 0xc254, 0x21, 0 + .dw 0x8200, 0xc254, 0x9fff, 0xc254, 0x21, 0 + .dw 0xa800, 0xc254, 0xbfff, 0xc254, 0x21, 0 + .dw 0xc200, 0xc254, 0xdfff, 0xc254, 0x21, 0 + .dw 0xe800, 0xc254, 0x1fff, 0xc280, 0x21, 0 + .dw 0x2800, 0xc280, 0xffff, 0xc283, 0x21, 0 + .dw 0x0200, 0xc284, 0x1fff, 0xc284, 0x21, 0 + .dw 0x2800, 0xc284, 0x3fff, 0xc284, 0x21, 0 + .dw 0x4200, 0xc284, 0x5fff, 0xc284, 0x21, 0 + .dw 0x6800, 0xc284, 0x7fff, 0xc284, 0x21, 0 + .dw 0x8200, 0xc284, 0x9fff, 0xc284, 0x21, 0 + .dw 0xa800, 0xc284, 0xbfff, 0xc284, 0x21, 0 + .dw 0xc200, 0xc284, 0xdfff, 0xc284, 0x21, 0 + .dw 0xe800, 0xc284, 0x1fff, 0xc288, 0x21, 0 + .dw 0x2040, 0xc288, 0x207f, 0xc288, 0x21, 0 + .dw 0x20c0, 0xc288, 0x20ff, 0xc288, 0x21, 0 + .dw 0x2140, 0xc288, 0x217f, 0xc288, 0x21, 0 + .dw 0x21c0, 0xc288, 0x21ff, 0xc288, 0x21, 0 + .dw 0x2240, 0xc288, 0x227f, 0xc288, 0x21, 0 + .dw 0x22c0, 0xc288, 0x22ff, 0xc288, 0x21, 0 + .dw 0x2340, 0xc288, 0x237f, 0xc288, 0x21, 0 + .dw 0x23c0, 0xc288, 0x23ff, 0xc288, 0x21, 0 + .dw 0x2440, 0xc288, 0x247f, 0xc288, 0x21, 0 + .dw 0x24c0, 0xc288, 0x24ff, 0xc288, 0x21, 0 + .dw 0x2540, 0xc288, 0x257f, 0xc288, 0x21, 0 + .dw 0x25c0, 0xc288, 0x25ff, 0xc288, 0x21, 0 + .dw 0x2640, 0xc288, 0x267f, 0xc288, 0x21, 0 + .dw 0x26c0, 0xc288, 0x26ff, 0xc288, 0x21, 0 + .dw 0x2740, 0xc288, 0x277f, 0xc288, 0x21, 0 + .dw 0x27c0, 0xc288, 0xffff, 0xc28b, 0x21, 0 + .dw 0x0040, 0xc28c, 0x007f, 0xc28c, 0x21, 0 + .dw 0x00c0, 0xc28c, 0x00ff, 0xc28c, 0x21, 0 + .dw 0x0140, 0xc28c, 0x017f, 0xc28c, 0x21, 0 + .dw 0x01c0, 0xc28c, 0x1fff, 0xc28c, 0x21, 0 + .dw 0x2040, 0xc28c, 0x207f, 0xc28c, 0x21, 0 + .dw 0x20c0, 0xc28c, 0x20ff, 0xc28c, 0x21, 0 + .dw 0x2140, 0xc28c, 0x217f, 0xc28c, 0x21, 0 + .dw 0x21c0, 0xc28c, 0x21ff, 0xc28c, 0x21, 0 + .dw 0x2240, 0xc28c, 0x227f, 0xc28c, 0x21, 0 + .dw 0x22c0, 0xc28c, 0x22ff, 0xc28c, 0x21, 0 + .dw 0x2340, 0xc28c, 0x237f, 0xc28c, 0x21, 0 + .dw 0x23c0, 0xc28c, 0x23ff, 0xc28c, 0x21, 0 + .dw 0x2440, 0xc28c, 0x247f, 0xc28c, 0x21, 0 + .dw 0x24c0, 0xc28c, 0x24ff, 0xc28c, 0x21, 0 + .dw 0x2540, 0xc28c, 0x257f, 0xc28c, 0x21, 0 + .dw 0x25c0, 0xc28c, 0x25ff, 0xc28c, 0x21, 0 + .dw 0x2640, 0xc28c, 0x267f, 0xc28c, 0x21, 0 + .dw 0x26c0, 0xc28c, 0x26ff, 0xc28c, 0x21, 0 + .dw 0x2740, 0xc28c, 0x277f, 0xc28c, 0x21, 0 + .dw 0x27c0, 0xc28c, 0x3fff, 0xc28c, 0x21, 0 + .dw 0x4040, 0xc28c, 0x407f, 0xc28c, 0x21, 0 + .dw 0x40c0, 0xc28c, 0x40ff, 0xc28c, 0x21, 0 + .dw 0x4140, 0xc28c, 0x417f, 0xc28c, 0x21, 0 + .dw 0x41c0, 0xc28c, 0x5fff, 0xc28c, 0x21, 0 + .dw 0x6040, 0xc28c, 0x607f, 0xc28c, 0x21, 0 + .dw 0x60c0, 0xc28c, 0x60ff, 0xc28c, 0x21, 0 + .dw 0x6140, 0xc28c, 0x617f, 0xc28c, 0x21, 0 + .dw 0x61c0, 0xc28c, 0x61ff, 0xc28c, 0x21, 0 + .dw 0x6240, 0xc28c, 0x627f, 0xc28c, 0x21, 0 + .dw 0x62c0, 0xc28c, 0x62ff, 0xc28c, 0x21, 0 + .dw 0x6340, 0xc28c, 0x637f, 0xc28c, 0x21, 0 + .dw 0x63c0, 0xc28c, 0x63ff, 0xc28c, 0x21, 0 + .dw 0x6440, 0xc28c, 0x647f, 0xc28c, 0x21, 0 + .dw 0x64c0, 0xc28c, 0x64ff, 0xc28c, 0x21, 0 + .dw 0x6540, 0xc28c, 0x657f, 0xc28c, 0x21, 0 + .dw 0x65c0, 0xc28c, 0x65ff, 0xc28c, 0x21, 0 + .dw 0x6640, 0xc28c, 0x667f, 0xc28c, 0x21, 0 + .dw 0x66c0, 0xc28c, 0x66ff, 0xc28c, 0x21, 0 + .dw 0x6740, 0xc28c, 0x677f, 0xc28c, 0x21, 0 + .dw 0x67c0, 0xc28c, 0x7fff, 0xc28c, 0x21, 0 + .dw 0x8040, 0xc28c, 0x807f, 0xc28c, 0x21, 0 + .dw 0x80c0, 0xc28c, 0x80ff, 0xc28c, 0x21, 0 + .dw 0x8140, 0xc28c, 0x817f, 0xc28c, 0x21, 0 + .dw 0x81c0, 0xc28c, 0x9fff, 0xc28c, 0x21, 0 + .dw 0xa040, 0xc28c, 0xa07f, 0xc28c, 0x21, 0 + .dw 0xa0c0, 0xc28c, 0xa0ff, 0xc28c, 0x21, 0 + .dw 0xa140, 0xc28c, 0xa17f, 0xc28c, 0x21, 0 + .dw 0xa1c0, 0xc28c, 0xa1ff, 0xc28c, 0x21, 0 + .dw 0xa240, 0xc28c, 0xa27f, 0xc28c, 0x21, 0 + .dw 0xa2c0, 0xc28c, 0xa2ff, 0xc28c, 0x21, 0 + .dw 0xa340, 0xc28c, 0xa37f, 0xc28c, 0x21, 0 + .dw 0xa3c0, 0xc28c, 0xa3ff, 0xc28c, 0x21, 0 + .dw 0xa440, 0xc28c, 0xa47f, 0xc28c, 0x21, 0 + .dw 0xa4c0, 0xc28c, 0xa4ff, 0xc28c, 0x21, 0 + .dw 0xa540, 0xc28c, 0xa57f, 0xc28c, 0x21, 0 + .dw 0xa5c0, 0xc28c, 0xa5ff, 0xc28c, 0x21, 0 + .dw 0xa640, 0xc28c, 0xa67f, 0xc28c, 0x21, 0 + .dw 0xa6c0, 0xc28c, 0xa6ff, 0xc28c, 0x21, 0 + .dw 0xa740, 0xc28c, 0xa77f, 0xc28c, 0x21, 0 + .dw 0xa7c0, 0xc28c, 0xbfff, 0xc28c, 0x21, 0 + .dw 0xc040, 0xc28c, 0xc07f, 0xc28c, 0x21, 0 + .dw 0xc0c0, 0xc28c, 0xc0ff, 0xc28c, 0x21, 0 + .dw 0xc140, 0xc28c, 0xc17f, 0xc28c, 0x21, 0 + .dw 0xc1c0, 0xc28c, 0xdfff, 0xc28c, 0x21, 0 + .dw 0xe040, 0xc28c, 0xe07f, 0xc28c, 0x21, 0 + .dw 0xe0c0, 0xc28c, 0xe0ff, 0xc28c, 0x21, 0 + .dw 0xe140, 0xc28c, 0xe17f, 0xc28c, 0x21, 0 + .dw 0xe1c0, 0xc28c, 0xe1ff, 0xc28c, 0x21, 0 + .dw 0xe240, 0xc28c, 0xe27f, 0xc28c, 0x21, 0 + .dw 0xe2c0, 0xc28c, 0xe2ff, 0xc28c, 0x21, 0 + .dw 0xe340, 0xc28c, 0xe37f, 0xc28c, 0x21, 0 + .dw 0xe3c0, 0xc28c, 0xe3ff, 0xc28c, 0x21, 0 + .dw 0xe440, 0xc28c, 0xe47f, 0xc28c, 0x21, 0 + .dw 0xe4c0, 0xc28c, 0xe4ff, 0xc28c, 0x21, 0 + .dw 0xe540, 0xc28c, 0xe57f, 0xc28c, 0x21, 0 + .dw 0xe5c0, 0xc28c, 0xe5ff, 0xc28c, 0x21, 0 + .dw 0xe640, 0xc28c, 0xe67f, 0xc28c, 0x21, 0 + .dw 0xe6c0, 0xc28c, 0xe6ff, 0xc28c, 0x21, 0 + .dw 0xe740, 0xc28c, 0xe77f, 0xc28c, 0x21, 0 + .dw 0xe7c0, 0xc28c, 0xffff, 0xc293, 0x21, 0 + .dw 0x0200, 0xc294, 0x1fff, 0xc294, 0x21, 0 + .dw 0x2800, 0xc294, 0x3fff, 0xc294, 0x21, 0 + .dw 0x4200, 0xc294, 0x5fff, 0xc294, 0x21, 0 + .dw 0x6800, 0xc294, 0x7fff, 0xc294, 0x21, 0 + .dw 0x8200, 0xc294, 0x9fff, 0xc294, 0x21, 0 + .dw 0xa800, 0xc294, 0xbfff, 0xc294, 0x21, 0 + .dw 0xc200, 0xc294, 0xdfff, 0xc294, 0x21, 0 + .dw 0xe800, 0xc294, 0xffff, 0xc29b, 0x21, 0 + .dw 0x0040, 0xc29c, 0x007f, 0xc29c, 0x21, 0 + .dw 0x00c0, 0xc29c, 0x00ff, 0xc29c, 0x21, 0 + .dw 0x0140, 0xc29c, 0x017f, 0xc29c, 0x21, 0 + .dw 0x01c0, 0xc29c, 0x1fff, 0xc29c, 0x21, 0 + .dw 0x2040, 0xc29c, 0x207f, 0xc29c, 0x21, 0 + .dw 0x20c0, 0xc29c, 0x20ff, 0xc29c, 0x21, 0 + .dw 0x2140, 0xc29c, 0x217f, 0xc29c, 0x21, 0 + .dw 0x21c0, 0xc29c, 0x21ff, 0xc29c, 0x21, 0 + .dw 0x2240, 0xc29c, 0x227f, 0xc29c, 0x21, 0 + .dw 0x22c0, 0xc29c, 0x22ff, 0xc29c, 0x21, 0 + .dw 0x2340, 0xc29c, 0x237f, 0xc29c, 0x21, 0 + .dw 0x23c0, 0xc29c, 0x23ff, 0xc29c, 0x21, 0 + .dw 0x2440, 0xc29c, 0x247f, 0xc29c, 0x21, 0 + .dw 0x24c0, 0xc29c, 0x24ff, 0xc29c, 0x21, 0 + .dw 0x2540, 0xc29c, 0x257f, 0xc29c, 0x21, 0 + .dw 0x25c0, 0xc29c, 0x25ff, 0xc29c, 0x21, 0 + .dw 0x2640, 0xc29c, 0x267f, 0xc29c, 0x21, 0 + .dw 0x26c0, 0xc29c, 0x26ff, 0xc29c, 0x21, 0 + .dw 0x2740, 0xc29c, 0x277f, 0xc29c, 0x21, 0 + .dw 0x27c0, 0xc29c, 0x3fff, 0xc29c, 0x21, 0 + .dw 0x4040, 0xc29c, 0x407f, 0xc29c, 0x21, 0 + .dw 0x40c0, 0xc29c, 0x40ff, 0xc29c, 0x21, 0 + .dw 0x4140, 0xc29c, 0x417f, 0xc29c, 0x21, 0 + .dw 0x41c0, 0xc29c, 0x5fff, 0xc29c, 0x21, 0 + .dw 0x6040, 0xc29c, 0x607f, 0xc29c, 0x21, 0 + .dw 0x60c0, 0xc29c, 0x60ff, 0xc29c, 0x21, 0 + .dw 0x6140, 0xc29c, 0x617f, 0xc29c, 0x21, 0 + .dw 0x61c0, 0xc29c, 0x61ff, 0xc29c, 0x21, 0 + .dw 0x6240, 0xc29c, 0x627f, 0xc29c, 0x21, 0 + .dw 0x62c0, 0xc29c, 0x62ff, 0xc29c, 0x21, 0 + .dw 0x6340, 0xc29c, 0x637f, 0xc29c, 0x21, 0 + .dw 0x63c0, 0xc29c, 0x63ff, 0xc29c, 0x21, 0 + .dw 0x6440, 0xc29c, 0x647f, 0xc29c, 0x21, 0 + .dw 0x64c0, 0xc29c, 0x64ff, 0xc29c, 0x21, 0 + .dw 0x6540, 0xc29c, 0x657f, 0xc29c, 0x21, 0 + .dw 0x65c0, 0xc29c, 0x65ff, 0xc29c, 0x21, 0 + .dw 0x6640, 0xc29c, 0x667f, 0xc29c, 0x21, 0 + .dw 0x66c0, 0xc29c, 0x66ff, 0xc29c, 0x21, 0 + .dw 0x6740, 0xc29c, 0x677f, 0xc29c, 0x21, 0 + .dw 0x67c0, 0xc29c, 0x7fff, 0xc29c, 0x21, 0 + .dw 0x8040, 0xc29c, 0x807f, 0xc29c, 0x21, 0 + .dw 0x80c0, 0xc29c, 0x80ff, 0xc29c, 0x21, 0 + .dw 0x8140, 0xc29c, 0x817f, 0xc29c, 0x21, 0 + .dw 0x81c0, 0xc29c, 0x9fff, 0xc29c, 0x21, 0 + .dw 0xa040, 0xc29c, 0xa07f, 0xc29c, 0x21, 0 + .dw 0xa0c0, 0xc29c, 0xa0ff, 0xc29c, 0x21, 0 + .dw 0xa140, 0xc29c, 0xa17f, 0xc29c, 0x21, 0 + .dw 0xa1c0, 0xc29c, 0xa1ff, 0xc29c, 0x21, 0 + .dw 0xa240, 0xc29c, 0xa27f, 0xc29c, 0x21, 0 + .dw 0xa2c0, 0xc29c, 0xa2ff, 0xc29c, 0x21, 0 + .dw 0xa340, 0xc29c, 0xa37f, 0xc29c, 0x21, 0 + .dw 0xa3c0, 0xc29c, 0xa3ff, 0xc29c, 0x21, 0 + .dw 0xa440, 0xc29c, 0xa47f, 0xc29c, 0x21, 0 + .dw 0xa4c0, 0xc29c, 0xa4ff, 0xc29c, 0x21, 0 + .dw 0xa540, 0xc29c, 0xa57f, 0xc29c, 0x21, 0 + .dw 0xa5c0, 0xc29c, 0xa5ff, 0xc29c, 0x21, 0 + .dw 0xa640, 0xc29c, 0xa67f, 0xc29c, 0x21, 0 + .dw 0xa6c0, 0xc29c, 0xa6ff, 0xc29c, 0x21, 0 + .dw 0xa740, 0xc29c, 0xa77f, 0xc29c, 0x21, 0 + .dw 0xa7c0, 0xc29c, 0xbfff, 0xc29c, 0x21, 0 + .dw 0xc040, 0xc29c, 0xc07f, 0xc29c, 0x21, 0 + .dw 0xc0c0, 0xc29c, 0xc0ff, 0xc29c, 0x21, 0 + .dw 0xc140, 0xc29c, 0xc17f, 0xc29c, 0x21, 0 + .dw 0xc1c0, 0xc29c, 0xdfff, 0xc29c, 0x21, 0 + .dw 0xe040, 0xc29c, 0xe07f, 0xc29c, 0x21, 0 + .dw 0xe0c0, 0xc29c, 0xe0ff, 0xc29c, 0x21, 0 + .dw 0xe140, 0xc29c, 0xe17f, 0xc29c, 0x21, 0 + .dw 0xe1c0, 0xc29c, 0xe1ff, 0xc29c, 0x21, 0 + .dw 0xe240, 0xc29c, 0xe27f, 0xc29c, 0x21, 0 + .dw 0xe2c0, 0xc29c, 0xe2ff, 0xc29c, 0x21, 0 + .dw 0xe340, 0xc29c, 0xe37f, 0xc29c, 0x21, 0 + .dw 0xe3c0, 0xc29c, 0xe3ff, 0xc29c, 0x21, 0 + .dw 0xe440, 0xc29c, 0xe47f, 0xc29c, 0x21, 0 + .dw 0xe4c0, 0xc29c, 0xe4ff, 0xc29c, 0x21, 0 + .dw 0xe540, 0xc29c, 0xe57f, 0xc29c, 0x21, 0 + .dw 0xe5c0, 0xc29c, 0xe5ff, 0xc29c, 0x21, 0 + .dw 0xe640, 0xc29c, 0xe67f, 0xc29c, 0x21, 0 + .dw 0xe6c0, 0xc29c, 0xe6ff, 0xc29c, 0x21, 0 + .dw 0xe740, 0xc29c, 0xe77f, 0xc29c, 0x21, 0 + .dw 0xe7c0, 0xc29c, 0x1fff, 0xc2c0, 0x21, 0 + .dw 0x2800, 0xc2c0, 0xffff, 0xc2c3, 0x21, 0 + .dw 0x0200, 0xc2c4, 0x1fff, 0xc2c4, 0x21, 0 + .dw 0x2800, 0xc2c4, 0x3fff, 0xc2c4, 0x21, 0 + .dw 0x4200, 0xc2c4, 0x5fff, 0xc2c4, 0x21, 0 + .dw 0x6800, 0xc2c4, 0x7fff, 0xc2c4, 0x21, 0 + .dw 0x8200, 0xc2c4, 0x9fff, 0xc2c4, 0x21, 0 + .dw 0xa800, 0xc2c4, 0xbfff, 0xc2c4, 0x21, 0 + .dw 0xc200, 0xc2c4, 0xdfff, 0xc2c4, 0x21, 0 + .dw 0xe800, 0xc2c4, 0xffff, 0xc2d3, 0x21, 0 + .dw 0x0200, 0xc2d4, 0x1fff, 0xc2d4, 0x21, 0 + .dw 0x2800, 0xc2d4, 0x3fff, 0xc2d4, 0x21, 0 + .dw 0x4200, 0xc2d4, 0x5fff, 0xc2d4, 0x21, 0 + .dw 0x6800, 0xc2d4, 0x7fff, 0xc2d4, 0x21, 0 + .dw 0x8200, 0xc2d4, 0x9fff, 0xc2d4, 0x21, 0 + .dw 0xa800, 0xc2d4, 0xbfff, 0xc2d4, 0x21, 0 + .dw 0xc200, 0xc2d4, 0xdfff, 0xc2d4, 0x21, 0 + .dw 0xe800, 0xc2d4, 0x1fff, 0xc300, 0x21, 0 + .dw 0x2800, 0xc300, 0xffff, 0xc303, 0x21, 0 + .dw 0x0200, 0xc304, 0x1fff, 0xc304, 0x21, 0 + .dw 0x2800, 0xc304, 0x3fff, 0xc304, 0x21, 0 + .dw 0x4200, 0xc304, 0x5fff, 0xc304, 0x21, 0 + .dw 0x6800, 0xc304, 0x7fff, 0xc304, 0x21, 0 + .dw 0x8200, 0xc304, 0x9fff, 0xc304, 0x21, 0 + .dw 0xa800, 0xc304, 0xbfff, 0xc304, 0x21, 0 + .dw 0xc200, 0xc304, 0xdfff, 0xc304, 0x21, 0 + .dw 0xe800, 0xc304, 0x1fff, 0xc308, 0x21, 0 + .dw 0x2040, 0xc308, 0x207f, 0xc308, 0x21, 0 + .dw 0x20c0, 0xc308, 0x20ff, 0xc308, 0x21, 0 + .dw 0x2140, 0xc308, 0x217f, 0xc308, 0x21, 0 + .dw 0x21c0, 0xc308, 0x21ff, 0xc308, 0x21, 0 + .dw 0x2240, 0xc308, 0x227f, 0xc308, 0x21, 0 + .dw 0x22c0, 0xc308, 0x22ff, 0xc308, 0x21, 0 + .dw 0x2340, 0xc308, 0x237f, 0xc308, 0x21, 0 + .dw 0x23c0, 0xc308, 0x23ff, 0xc308, 0x21, 0 + .dw 0x2440, 0xc308, 0x247f, 0xc308, 0x21, 0 + .dw 0x24c0, 0xc308, 0x24ff, 0xc308, 0x21, 0 + .dw 0x2540, 0xc308, 0x257f, 0xc308, 0x21, 0 + .dw 0x25c0, 0xc308, 0x25ff, 0xc308, 0x21, 0 + .dw 0x2640, 0xc308, 0x267f, 0xc308, 0x21, 0 + .dw 0x26c0, 0xc308, 0x26ff, 0xc308, 0x21, 0 + .dw 0x2740, 0xc308, 0x277f, 0xc308, 0x21, 0 + .dw 0x27c0, 0xc308, 0xffff, 0xc30b, 0x21, 0 + .dw 0x0040, 0xc30c, 0x007f, 0xc30c, 0x21, 0 + .dw 0x00c0, 0xc30c, 0x00ff, 0xc30c, 0x21, 0 + .dw 0x0140, 0xc30c, 0x017f, 0xc30c, 0x21, 0 + .dw 0x01c0, 0xc30c, 0x1fff, 0xc30c, 0x21, 0 + .dw 0x2040, 0xc30c, 0x207f, 0xc30c, 0x21, 0 + .dw 0x20c0, 0xc30c, 0x20ff, 0xc30c, 0x21, 0 + .dw 0x2140, 0xc30c, 0x217f, 0xc30c, 0x21, 0 + .dw 0x21c0, 0xc30c, 0x21ff, 0xc30c, 0x21, 0 + .dw 0x2240, 0xc30c, 0x227f, 0xc30c, 0x21, 0 + .dw 0x22c0, 0xc30c, 0x22ff, 0xc30c, 0x21, 0 + .dw 0x2340, 0xc30c, 0x237f, 0xc30c, 0x21, 0 + .dw 0x23c0, 0xc30c, 0x23ff, 0xc30c, 0x21, 0 + .dw 0x2440, 0xc30c, 0x247f, 0xc30c, 0x21, 0 + .dw 0x24c0, 0xc30c, 0x24ff, 0xc30c, 0x21, 0 + .dw 0x2540, 0xc30c, 0x257f, 0xc30c, 0x21, 0 + .dw 0x25c0, 0xc30c, 0x25ff, 0xc30c, 0x21, 0 + .dw 0x2640, 0xc30c, 0x267f, 0xc30c, 0x21, 0 + .dw 0x26c0, 0xc30c, 0x26ff, 0xc30c, 0x21, 0 + .dw 0x2740, 0xc30c, 0x277f, 0xc30c, 0x21, 0 + .dw 0x27c0, 0xc30c, 0x3fff, 0xc30c, 0x21, 0 + .dw 0x4040, 0xc30c, 0x407f, 0xc30c, 0x21, 0 + .dw 0x40c0, 0xc30c, 0x40ff, 0xc30c, 0x21, 0 + .dw 0x4140, 0xc30c, 0x417f, 0xc30c, 0x21, 0 + .dw 0x41c0, 0xc30c, 0x5fff, 0xc30c, 0x21, 0 + .dw 0x6040, 0xc30c, 0x607f, 0xc30c, 0x21, 0 + .dw 0x60c0, 0xc30c, 0x60ff, 0xc30c, 0x21, 0 + .dw 0x6140, 0xc30c, 0x617f, 0xc30c, 0x21, 0 + .dw 0x61c0, 0xc30c, 0x61ff, 0xc30c, 0x21, 0 + .dw 0x6240, 0xc30c, 0x627f, 0xc30c, 0x21, 0 + .dw 0x62c0, 0xc30c, 0x62ff, 0xc30c, 0x21, 0 + .dw 0x6340, 0xc30c, 0x637f, 0xc30c, 0x21, 0 + .dw 0x63c0, 0xc30c, 0x63ff, 0xc30c, 0x21, 0 + .dw 0x6440, 0xc30c, 0x647f, 0xc30c, 0x21, 0 + .dw 0x64c0, 0xc30c, 0x64ff, 0xc30c, 0x21, 0 + .dw 0x6540, 0xc30c, 0x657f, 0xc30c, 0x21, 0 + .dw 0x65c0, 0xc30c, 0x65ff, 0xc30c, 0x21, 0 + .dw 0x6640, 0xc30c, 0x667f, 0xc30c, 0x21, 0 + .dw 0x66c0, 0xc30c, 0x66ff, 0xc30c, 0x21, 0 + .dw 0x6740, 0xc30c, 0x677f, 0xc30c, 0x21, 0 + .dw 0x67c0, 0xc30c, 0x7fff, 0xc30c, 0x21, 0 + .dw 0x8040, 0xc30c, 0x807f, 0xc30c, 0x21, 0 + .dw 0x80c0, 0xc30c, 0x80ff, 0xc30c, 0x21, 0 + .dw 0x8140, 0xc30c, 0x817f, 0xc30c, 0x21, 0 + .dw 0x81c0, 0xc30c, 0x9fff, 0xc30c, 0x21, 0 + .dw 0xa040, 0xc30c, 0xa07f, 0xc30c, 0x21, 0 + .dw 0xa0c0, 0xc30c, 0xa0ff, 0xc30c, 0x21, 0 + .dw 0xa140, 0xc30c, 0xa17f, 0xc30c, 0x21, 0 + .dw 0xa1c0, 0xc30c, 0xa1ff, 0xc30c, 0x21, 0 + .dw 0xa240, 0xc30c, 0xa27f, 0xc30c, 0x21, 0 + .dw 0xa2c0, 0xc30c, 0xa2ff, 0xc30c, 0x21, 0 + .dw 0xa340, 0xc30c, 0xa37f, 0xc30c, 0x21, 0 + .dw 0xa3c0, 0xc30c, 0xa3ff, 0xc30c, 0x21, 0 + .dw 0xa440, 0xc30c, 0xa47f, 0xc30c, 0x21, 0 + .dw 0xa4c0, 0xc30c, 0xa4ff, 0xc30c, 0x21, 0 + .dw 0xa540, 0xc30c, 0xa57f, 0xc30c, 0x21, 0 + .dw 0xa5c0, 0xc30c, 0xa5ff, 0xc30c, 0x21, 0 + .dw 0xa640, 0xc30c, 0xa67f, 0xc30c, 0x21, 0 + .dw 0xa6c0, 0xc30c, 0xa6ff, 0xc30c, 0x21, 0 + .dw 0xa740, 0xc30c, 0xa77f, 0xc30c, 0x21, 0 + .dw 0xa7c0, 0xc30c, 0xbfff, 0xc30c, 0x21, 0 + .dw 0xc040, 0xc30c, 0xc07f, 0xc30c, 0x21, 0 + .dw 0xc0c0, 0xc30c, 0xc0ff, 0xc30c, 0x21, 0 + .dw 0xc140, 0xc30c, 0xc17f, 0xc30c, 0x21, 0 + .dw 0xc1c0, 0xc30c, 0xdfff, 0xc30c, 0x21, 0 + .dw 0xe040, 0xc30c, 0xe07f, 0xc30c, 0x21, 0 + .dw 0xe0c0, 0xc30c, 0xe0ff, 0xc30c, 0x21, 0 + .dw 0xe140, 0xc30c, 0xe17f, 0xc30c, 0x21, 0 + .dw 0xe1c0, 0xc30c, 0xe1ff, 0xc30c, 0x21, 0 + .dw 0xe240, 0xc30c, 0xe27f, 0xc30c, 0x21, 0 + .dw 0xe2c0, 0xc30c, 0xe2ff, 0xc30c, 0x21, 0 + .dw 0xe340, 0xc30c, 0xe37f, 0xc30c, 0x21, 0 + .dw 0xe3c0, 0xc30c, 0xe3ff, 0xc30c, 0x21, 0 + .dw 0xe440, 0xc30c, 0xe47f, 0xc30c, 0x21, 0 + .dw 0xe4c0, 0xc30c, 0xe4ff, 0xc30c, 0x21, 0 + .dw 0xe540, 0xc30c, 0xe57f, 0xc30c, 0x21, 0 + .dw 0xe5c0, 0xc30c, 0xe5ff, 0xc30c, 0x21, 0 + .dw 0xe640, 0xc30c, 0xe67f, 0xc30c, 0x21, 0 + .dw 0xe6c0, 0xc30c, 0xe6ff, 0xc30c, 0x21, 0 + .dw 0xe740, 0xc30c, 0xe77f, 0xc30c, 0x21, 0 + .dw 0xe7c0, 0xc30c, 0xffff, 0xc313, 0x21, 0 + .dw 0x0200, 0xc314, 0x1fff, 0xc314, 0x21, 0 + .dw 0x2800, 0xc314, 0x3fff, 0xc314, 0x21, 0 + .dw 0x4200, 0xc314, 0x5fff, 0xc314, 0x21, 0 + .dw 0x6800, 0xc314, 0x7fff, 0xc314, 0x21, 0 + .dw 0x8200, 0xc314, 0x9fff, 0xc314, 0x21, 0 + .dw 0xa800, 0xc314, 0xbfff, 0xc314, 0x21, 0 + .dw 0xc200, 0xc314, 0xdfff, 0xc314, 0x21, 0 + .dw 0xe800, 0xc314, 0xffff, 0xc31b, 0x21, 0 + .dw 0x0040, 0xc31c, 0x007f, 0xc31c, 0x21, 0 + .dw 0x00c0, 0xc31c, 0x00ff, 0xc31c, 0x21, 0 + .dw 0x0140, 0xc31c, 0x017f, 0xc31c, 0x21, 0 + .dw 0x01c0, 0xc31c, 0x1fff, 0xc31c, 0x21, 0 + .dw 0x2040, 0xc31c, 0x207f, 0xc31c, 0x21, 0 + .dw 0x20c0, 0xc31c, 0x20ff, 0xc31c, 0x21, 0 + .dw 0x2140, 0xc31c, 0x217f, 0xc31c, 0x21, 0 + .dw 0x21c0, 0xc31c, 0x21ff, 0xc31c, 0x21, 0 + .dw 0x2240, 0xc31c, 0x227f, 0xc31c, 0x21, 0 + .dw 0x22c0, 0xc31c, 0x22ff, 0xc31c, 0x21, 0 + .dw 0x2340, 0xc31c, 0x237f, 0xc31c, 0x21, 0 + .dw 0x23c0, 0xc31c, 0x23ff, 0xc31c, 0x21, 0 + .dw 0x2440, 0xc31c, 0x247f, 0xc31c, 0x21, 0 + .dw 0x24c0, 0xc31c, 0x24ff, 0xc31c, 0x21, 0 + .dw 0x2540, 0xc31c, 0x257f, 0xc31c, 0x21, 0 + .dw 0x25c0, 0xc31c, 0x25ff, 0xc31c, 0x21, 0 + .dw 0x2640, 0xc31c, 0x267f, 0xc31c, 0x21, 0 + .dw 0x26c0, 0xc31c, 0x26ff, 0xc31c, 0x21, 0 + .dw 0x2740, 0xc31c, 0x277f, 0xc31c, 0x21, 0 + .dw 0x27c0, 0xc31c, 0x3fff, 0xc31c, 0x21, 0 + .dw 0x4040, 0xc31c, 0x407f, 0xc31c, 0x21, 0 + .dw 0x40c0, 0xc31c, 0x40ff, 0xc31c, 0x21, 0 + .dw 0x4140, 0xc31c, 0x417f, 0xc31c, 0x21, 0 + .dw 0x41c0, 0xc31c, 0x5fff, 0xc31c, 0x21, 0 + .dw 0x6040, 0xc31c, 0x607f, 0xc31c, 0x21, 0 + .dw 0x60c0, 0xc31c, 0x60ff, 0xc31c, 0x21, 0 + .dw 0x6140, 0xc31c, 0x617f, 0xc31c, 0x21, 0 + .dw 0x61c0, 0xc31c, 0x61ff, 0xc31c, 0x21, 0 + .dw 0x6240, 0xc31c, 0x627f, 0xc31c, 0x21, 0 + .dw 0x62c0, 0xc31c, 0x62ff, 0xc31c, 0x21, 0 + .dw 0x6340, 0xc31c, 0x637f, 0xc31c, 0x21, 0 + .dw 0x63c0, 0xc31c, 0x63ff, 0xc31c, 0x21, 0 + .dw 0x6440, 0xc31c, 0x647f, 0xc31c, 0x21, 0 + .dw 0x64c0, 0xc31c, 0x64ff, 0xc31c, 0x21, 0 + .dw 0x6540, 0xc31c, 0x657f, 0xc31c, 0x21, 0 + .dw 0x65c0, 0xc31c, 0x65ff, 0xc31c, 0x21, 0 + .dw 0x6640, 0xc31c, 0x667f, 0xc31c, 0x21, 0 + .dw 0x66c0, 0xc31c, 0x66ff, 0xc31c, 0x21, 0 + .dw 0x6740, 0xc31c, 0x677f, 0xc31c, 0x21, 0 + .dw 0x67c0, 0xc31c, 0x7fff, 0xc31c, 0x21, 0 + .dw 0x8040, 0xc31c, 0x807f, 0xc31c, 0x21, 0 + .dw 0x80c0, 0xc31c, 0x80ff, 0xc31c, 0x21, 0 + .dw 0x8140, 0xc31c, 0x817f, 0xc31c, 0x21, 0 + .dw 0x81c0, 0xc31c, 0x9fff, 0xc31c, 0x21, 0 + .dw 0xa040, 0xc31c, 0xa07f, 0xc31c, 0x21, 0 + .dw 0xa0c0, 0xc31c, 0xa0ff, 0xc31c, 0x21, 0 + .dw 0xa140, 0xc31c, 0xa17f, 0xc31c, 0x21, 0 + .dw 0xa1c0, 0xc31c, 0xa1ff, 0xc31c, 0x21, 0 + .dw 0xa240, 0xc31c, 0xa27f, 0xc31c, 0x21, 0 + .dw 0xa2c0, 0xc31c, 0xa2ff, 0xc31c, 0x21, 0 + .dw 0xa340, 0xc31c, 0xa37f, 0xc31c, 0x21, 0 + .dw 0xa3c0, 0xc31c, 0xa3ff, 0xc31c, 0x21, 0 + .dw 0xa440, 0xc31c, 0xa47f, 0xc31c, 0x21, 0 + .dw 0xa4c0, 0xc31c, 0xa4ff, 0xc31c, 0x21, 0 + .dw 0xa540, 0xc31c, 0xa57f, 0xc31c, 0x21, 0 + .dw 0xa5c0, 0xc31c, 0xa5ff, 0xc31c, 0x21, 0 + .dw 0xa640, 0xc31c, 0xa67f, 0xc31c, 0x21, 0 + .dw 0xa6c0, 0xc31c, 0xa6ff, 0xc31c, 0x21, 0 + .dw 0xa740, 0xc31c, 0xa77f, 0xc31c, 0x21, 0 + .dw 0xa7c0, 0xc31c, 0xbfff, 0xc31c, 0x21, 0 + .dw 0xc040, 0xc31c, 0xc07f, 0xc31c, 0x21, 0 + .dw 0xc0c0, 0xc31c, 0xc0ff, 0xc31c, 0x21, 0 + .dw 0xc140, 0xc31c, 0xc17f, 0xc31c, 0x21, 0 + .dw 0xc1c0, 0xc31c, 0xdfff, 0xc31c, 0x21, 0 + .dw 0xe040, 0xc31c, 0xe07f, 0xc31c, 0x21, 0 + .dw 0xe0c0, 0xc31c, 0xe0ff, 0xc31c, 0x21, 0 + .dw 0xe140, 0xc31c, 0xe17f, 0xc31c, 0x21, 0 + .dw 0xe1c0, 0xc31c, 0xe1ff, 0xc31c, 0x21, 0 + .dw 0xe240, 0xc31c, 0xe27f, 0xc31c, 0x21, 0 + .dw 0xe2c0, 0xc31c, 0xe2ff, 0xc31c, 0x21, 0 + .dw 0xe340, 0xc31c, 0xe37f, 0xc31c, 0x21, 0 + .dw 0xe3c0, 0xc31c, 0xe3ff, 0xc31c, 0x21, 0 + .dw 0xe440, 0xc31c, 0xe47f, 0xc31c, 0x21, 0 + .dw 0xe4c0, 0xc31c, 0xe4ff, 0xc31c, 0x21, 0 + .dw 0xe540, 0xc31c, 0xe57f, 0xc31c, 0x21, 0 + .dw 0xe5c0, 0xc31c, 0xe5ff, 0xc31c, 0x21, 0 + .dw 0xe640, 0xc31c, 0xe67f, 0xc31c, 0x21, 0 + .dw 0xe6c0, 0xc31c, 0xe6ff, 0xc31c, 0x21, 0 + .dw 0xe740, 0xc31c, 0xe77f, 0xc31c, 0x21, 0 + .dw 0xe7c0, 0xc31c, 0x1fff, 0xc320, 0x21, 0 + .dw 0x2800, 0xc320, 0xffff, 0xc323, 0x21, 0 + .dw 0x0200, 0xc324, 0x1fff, 0xc324, 0x21, 0 + .dw 0x2800, 0xc324, 0x3fff, 0xc324, 0x21, 0 + .dw 0x4200, 0xc324, 0x5fff, 0xc324, 0x21, 0 + .dw 0x6800, 0xc324, 0x7fff, 0xc324, 0x21, 0 + .dw 0x8200, 0xc324, 0x9fff, 0xc324, 0x21, 0 + .dw 0xa800, 0xc324, 0xbfff, 0xc324, 0x21, 0 + .dw 0xc200, 0xc324, 0xdfff, 0xc324, 0x21, 0 + .dw 0xe800, 0xc324, 0x1fff, 0xc328, 0x21, 0 + .dw 0x2040, 0xc328, 0x207f, 0xc328, 0x21, 0 + .dw 0x20c0, 0xc328, 0x20ff, 0xc328, 0x21, 0 + .dw 0x2140, 0xc328, 0x217f, 0xc328, 0x21, 0 + .dw 0x21c0, 0xc328, 0x21ff, 0xc328, 0x21, 0 + .dw 0x2240, 0xc328, 0x227f, 0xc328, 0x21, 0 + .dw 0x22c0, 0xc328, 0x22ff, 0xc328, 0x21, 0 + .dw 0x2340, 0xc328, 0x237f, 0xc328, 0x21, 0 + .dw 0x23c0, 0xc328, 0x23ff, 0xc328, 0x21, 0 + .dw 0x2440, 0xc328, 0x247f, 0xc328, 0x21, 0 + .dw 0x24c0, 0xc328, 0x24ff, 0xc328, 0x21, 0 + .dw 0x2540, 0xc328, 0x257f, 0xc328, 0x21, 0 + .dw 0x25c0, 0xc328, 0x25ff, 0xc328, 0x21, 0 + .dw 0x2640, 0xc328, 0x267f, 0xc328, 0x21, 0 + .dw 0x26c0, 0xc328, 0x26ff, 0xc328, 0x21, 0 + .dw 0x2740, 0xc328, 0x277f, 0xc328, 0x21, 0 + .dw 0x27c0, 0xc328, 0xffff, 0xc32b, 0x21, 0 + .dw 0x0040, 0xc32c, 0x007f, 0xc32c, 0x21, 0 + .dw 0x00c0, 0xc32c, 0x00ff, 0xc32c, 0x21, 0 + .dw 0x0140, 0xc32c, 0x017f, 0xc32c, 0x21, 0 + .dw 0x01c0, 0xc32c, 0x1fff, 0xc32c, 0x21, 0 + .dw 0x2040, 0xc32c, 0x207f, 0xc32c, 0x21, 0 + .dw 0x20c0, 0xc32c, 0x20ff, 0xc32c, 0x21, 0 + .dw 0x2140, 0xc32c, 0x217f, 0xc32c, 0x21, 0 + .dw 0x21c0, 0xc32c, 0x21ff, 0xc32c, 0x21, 0 + .dw 0x2240, 0xc32c, 0x227f, 0xc32c, 0x21, 0 + .dw 0x22c0, 0xc32c, 0x22ff, 0xc32c, 0x21, 0 + .dw 0x2340, 0xc32c, 0x237f, 0xc32c, 0x21, 0 + .dw 0x23c0, 0xc32c, 0x23ff, 0xc32c, 0x21, 0 + .dw 0x2440, 0xc32c, 0x247f, 0xc32c, 0x21, 0 + .dw 0x24c0, 0xc32c, 0x24ff, 0xc32c, 0x21, 0 + .dw 0x2540, 0xc32c, 0x257f, 0xc32c, 0x21, 0 + .dw 0x25c0, 0xc32c, 0x25ff, 0xc32c, 0x21, 0 + .dw 0x2640, 0xc32c, 0x267f, 0xc32c, 0x21, 0 + .dw 0x26c0, 0xc32c, 0x26ff, 0xc32c, 0x21, 0 + .dw 0x2740, 0xc32c, 0x277f, 0xc32c, 0x21, 0 + .dw 0x27c0, 0xc32c, 0x3fff, 0xc32c, 0x21, 0 + .dw 0x4040, 0xc32c, 0x407f, 0xc32c, 0x21, 0 + .dw 0x40c0, 0xc32c, 0x40ff, 0xc32c, 0x21, 0 + .dw 0x4140, 0xc32c, 0x417f, 0xc32c, 0x21, 0 + .dw 0x41c0, 0xc32c, 0x5fff, 0xc32c, 0x21, 0 + .dw 0x6040, 0xc32c, 0x607f, 0xc32c, 0x21, 0 + .dw 0x60c0, 0xc32c, 0x60ff, 0xc32c, 0x21, 0 + .dw 0x6140, 0xc32c, 0x617f, 0xc32c, 0x21, 0 + .dw 0x61c0, 0xc32c, 0x61ff, 0xc32c, 0x21, 0 + .dw 0x6240, 0xc32c, 0x627f, 0xc32c, 0x21, 0 + .dw 0x62c0, 0xc32c, 0x62ff, 0xc32c, 0x21, 0 + .dw 0x6340, 0xc32c, 0x637f, 0xc32c, 0x21, 0 + .dw 0x63c0, 0xc32c, 0x63ff, 0xc32c, 0x21, 0 + .dw 0x6440, 0xc32c, 0x647f, 0xc32c, 0x21, 0 + .dw 0x64c0, 0xc32c, 0x64ff, 0xc32c, 0x21, 0 + .dw 0x6540, 0xc32c, 0x657f, 0xc32c, 0x21, 0 + .dw 0x65c0, 0xc32c, 0x65ff, 0xc32c, 0x21, 0 + .dw 0x6640, 0xc32c, 0x667f, 0xc32c, 0x21, 0 + .dw 0x66c0, 0xc32c, 0x66ff, 0xc32c, 0x21, 0 + .dw 0x6740, 0xc32c, 0x677f, 0xc32c, 0x21, 0 + .dw 0x67c0, 0xc32c, 0x7fff, 0xc32c, 0x21, 0 + .dw 0x8040, 0xc32c, 0x807f, 0xc32c, 0x21, 0 + .dw 0x80c0, 0xc32c, 0x80ff, 0xc32c, 0x21, 0 + .dw 0x8140, 0xc32c, 0x817f, 0xc32c, 0x21, 0 + .dw 0x81c0, 0xc32c, 0x9fff, 0xc32c, 0x21, 0 + .dw 0xa040, 0xc32c, 0xa07f, 0xc32c, 0x21, 0 + .dw 0xa0c0, 0xc32c, 0xa0ff, 0xc32c, 0x21, 0 + .dw 0xa140, 0xc32c, 0xa17f, 0xc32c, 0x21, 0 + .dw 0xa1c0, 0xc32c, 0xa1ff, 0xc32c, 0x21, 0 + .dw 0xa240, 0xc32c, 0xa27f, 0xc32c, 0x21, 0 + .dw 0xa2c0, 0xc32c, 0xa2ff, 0xc32c, 0x21, 0 + .dw 0xa340, 0xc32c, 0xa37f, 0xc32c, 0x21, 0 + .dw 0xa3c0, 0xc32c, 0xa3ff, 0xc32c, 0x21, 0 + .dw 0xa440, 0xc32c, 0xa47f, 0xc32c, 0x21, 0 + .dw 0xa4c0, 0xc32c, 0xa4ff, 0xc32c, 0x21, 0 + .dw 0xa540, 0xc32c, 0xa57f, 0xc32c, 0x21, 0 + .dw 0xa5c0, 0xc32c, 0xa5ff, 0xc32c, 0x21, 0 + .dw 0xa640, 0xc32c, 0xa67f, 0xc32c, 0x21, 0 + .dw 0xa6c0, 0xc32c, 0xa6ff, 0xc32c, 0x21, 0 + .dw 0xa740, 0xc32c, 0xa77f, 0xc32c, 0x21, 0 + .dw 0xa7c0, 0xc32c, 0xbfff, 0xc32c, 0x21, 0 + .dw 0xc040, 0xc32c, 0xc07f, 0xc32c, 0x21, 0 + .dw 0xc0c0, 0xc32c, 0xc0ff, 0xc32c, 0x21, 0 + .dw 0xc140, 0xc32c, 0xc17f, 0xc32c, 0x21, 0 + .dw 0xc1c0, 0xc32c, 0xdfff, 0xc32c, 0x21, 0 + .dw 0xe040, 0xc32c, 0xe07f, 0xc32c, 0x21, 0 + .dw 0xe0c0, 0xc32c, 0xe0ff, 0xc32c, 0x21, 0 + .dw 0xe140, 0xc32c, 0xe17f, 0xc32c, 0x21, 0 + .dw 0xe1c0, 0xc32c, 0xe1ff, 0xc32c, 0x21, 0 + .dw 0xe240, 0xc32c, 0xe27f, 0xc32c, 0x21, 0 + .dw 0xe2c0, 0xc32c, 0xe2ff, 0xc32c, 0x21, 0 + .dw 0xe340, 0xc32c, 0xe37f, 0xc32c, 0x21, 0 + .dw 0xe3c0, 0xc32c, 0xe3ff, 0xc32c, 0x21, 0 + .dw 0xe440, 0xc32c, 0xe47f, 0xc32c, 0x21, 0 + .dw 0xe4c0, 0xc32c, 0xe4ff, 0xc32c, 0x21, 0 + .dw 0xe540, 0xc32c, 0xe57f, 0xc32c, 0x21, 0 + .dw 0xe5c0, 0xc32c, 0xe5ff, 0xc32c, 0x21, 0 + .dw 0xe640, 0xc32c, 0xe67f, 0xc32c, 0x21, 0 + .dw 0xe6c0, 0xc32c, 0xe6ff, 0xc32c, 0x21, 0 + .dw 0xe740, 0xc32c, 0xe77f, 0xc32c, 0x21, 0 + .dw 0xe7c0, 0xc32c, 0xffff, 0xc333, 0x21, 0 + .dw 0x0200, 0xc334, 0x1fff, 0xc334, 0x21, 0 + .dw 0x2800, 0xc334, 0x3fff, 0xc334, 0x21, 0 + .dw 0x4200, 0xc334, 0x5fff, 0xc334, 0x21, 0 + .dw 0x6800, 0xc334, 0x7fff, 0xc334, 0x21, 0 + .dw 0x8200, 0xc334, 0x9fff, 0xc334, 0x21, 0 + .dw 0xa800, 0xc334, 0xbfff, 0xc334, 0x21, 0 + .dw 0xc200, 0xc334, 0xdfff, 0xc334, 0x21, 0 + .dw 0xe800, 0xc334, 0xffff, 0xc33b, 0x21, 0 + .dw 0x0040, 0xc33c, 0x007f, 0xc33c, 0x21, 0 + .dw 0x00c0, 0xc33c, 0x00ff, 0xc33c, 0x21, 0 + .dw 0x0140, 0xc33c, 0x017f, 0xc33c, 0x21, 0 + .dw 0x01c0, 0xc33c, 0x1fff, 0xc33c, 0x21, 0 + .dw 0x2040, 0xc33c, 0x207f, 0xc33c, 0x21, 0 + .dw 0x20c0, 0xc33c, 0x20ff, 0xc33c, 0x21, 0 + .dw 0x2140, 0xc33c, 0x217f, 0xc33c, 0x21, 0 + .dw 0x21c0, 0xc33c, 0x21ff, 0xc33c, 0x21, 0 + .dw 0x2240, 0xc33c, 0x227f, 0xc33c, 0x21, 0 + .dw 0x22c0, 0xc33c, 0x22ff, 0xc33c, 0x21, 0 + .dw 0x2340, 0xc33c, 0x237f, 0xc33c, 0x21, 0 + .dw 0x23c0, 0xc33c, 0x23ff, 0xc33c, 0x21, 0 + .dw 0x2440, 0xc33c, 0x247f, 0xc33c, 0x21, 0 + .dw 0x24c0, 0xc33c, 0x24ff, 0xc33c, 0x21, 0 + .dw 0x2540, 0xc33c, 0x257f, 0xc33c, 0x21, 0 + .dw 0x25c0, 0xc33c, 0x25ff, 0xc33c, 0x21, 0 + .dw 0x2640, 0xc33c, 0x267f, 0xc33c, 0x21, 0 + .dw 0x26c0, 0xc33c, 0x26ff, 0xc33c, 0x21, 0 + .dw 0x2740, 0xc33c, 0x277f, 0xc33c, 0x21, 0 + .dw 0x27c0, 0xc33c, 0x3fff, 0xc33c, 0x21, 0 + .dw 0x4040, 0xc33c, 0x407f, 0xc33c, 0x21, 0 + .dw 0x40c0, 0xc33c, 0x40ff, 0xc33c, 0x21, 0 + .dw 0x4140, 0xc33c, 0x417f, 0xc33c, 0x21, 0 + .dw 0x41c0, 0xc33c, 0x5fff, 0xc33c, 0x21, 0 + .dw 0x6040, 0xc33c, 0x607f, 0xc33c, 0x21, 0 + .dw 0x60c0, 0xc33c, 0x60ff, 0xc33c, 0x21, 0 + .dw 0x6140, 0xc33c, 0x617f, 0xc33c, 0x21, 0 + .dw 0x61c0, 0xc33c, 0x61ff, 0xc33c, 0x21, 0 + .dw 0x6240, 0xc33c, 0x627f, 0xc33c, 0x21, 0 + .dw 0x62c0, 0xc33c, 0x62ff, 0xc33c, 0x21, 0 + .dw 0x6340, 0xc33c, 0x637f, 0xc33c, 0x21, 0 + .dw 0x63c0, 0xc33c, 0x63ff, 0xc33c, 0x21, 0 + .dw 0x6440, 0xc33c, 0x647f, 0xc33c, 0x21, 0 + .dw 0x64c0, 0xc33c, 0x64ff, 0xc33c, 0x21, 0 + .dw 0x6540, 0xc33c, 0x657f, 0xc33c, 0x21, 0 + .dw 0x65c0, 0xc33c, 0x65ff, 0xc33c, 0x21, 0 + .dw 0x6640, 0xc33c, 0x667f, 0xc33c, 0x21, 0 + .dw 0x66c0, 0xc33c, 0x66ff, 0xc33c, 0x21, 0 + .dw 0x6740, 0xc33c, 0x677f, 0xc33c, 0x21, 0 + .dw 0x67c0, 0xc33c, 0x7fff, 0xc33c, 0x21, 0 + .dw 0x8040, 0xc33c, 0x807f, 0xc33c, 0x21, 0 + .dw 0x80c0, 0xc33c, 0x80ff, 0xc33c, 0x21, 0 + .dw 0x8140, 0xc33c, 0x817f, 0xc33c, 0x21, 0 + .dw 0x81c0, 0xc33c, 0x9fff, 0xc33c, 0x21, 0 + .dw 0xa040, 0xc33c, 0xa07f, 0xc33c, 0x21, 0 + .dw 0xa0c0, 0xc33c, 0xa0ff, 0xc33c, 0x21, 0 + .dw 0xa140, 0xc33c, 0xa17f, 0xc33c, 0x21, 0 + .dw 0xa1c0, 0xc33c, 0xa1ff, 0xc33c, 0x21, 0 + .dw 0xa240, 0xc33c, 0xa27f, 0xc33c, 0x21, 0 + .dw 0xa2c0, 0xc33c, 0xa2ff, 0xc33c, 0x21, 0 + .dw 0xa340, 0xc33c, 0xa37f, 0xc33c, 0x21, 0 + .dw 0xa3c0, 0xc33c, 0xa3ff, 0xc33c, 0x21, 0 + .dw 0xa440, 0xc33c, 0xa47f, 0xc33c, 0x21, 0 + .dw 0xa4c0, 0xc33c, 0xa4ff, 0xc33c, 0x21, 0 + .dw 0xa540, 0xc33c, 0xa57f, 0xc33c, 0x21, 0 + .dw 0xa5c0, 0xc33c, 0xa5ff, 0xc33c, 0x21, 0 + .dw 0xa640, 0xc33c, 0xa67f, 0xc33c, 0x21, 0 + .dw 0xa6c0, 0xc33c, 0xa6ff, 0xc33c, 0x21, 0 + .dw 0xa740, 0xc33c, 0xa77f, 0xc33c, 0x21, 0 + .dw 0xa7c0, 0xc33c, 0xbfff, 0xc33c, 0x21, 0 + .dw 0xc040, 0xc33c, 0xc07f, 0xc33c, 0x21, 0 + .dw 0xc0c0, 0xc33c, 0xc0ff, 0xc33c, 0x21, 0 + .dw 0xc140, 0xc33c, 0xc17f, 0xc33c, 0x21, 0 + .dw 0xc1c0, 0xc33c, 0xdfff, 0xc33c, 0x21, 0 + .dw 0xe040, 0xc33c, 0xe07f, 0xc33c, 0x21, 0 + .dw 0xe0c0, 0xc33c, 0xe0ff, 0xc33c, 0x21, 0 + .dw 0xe140, 0xc33c, 0xe17f, 0xc33c, 0x21, 0 + .dw 0xe1c0, 0xc33c, 0xe1ff, 0xc33c, 0x21, 0 + .dw 0xe240, 0xc33c, 0xe27f, 0xc33c, 0x21, 0 + .dw 0xe2c0, 0xc33c, 0xe2ff, 0xc33c, 0x21, 0 + .dw 0xe340, 0xc33c, 0xe37f, 0xc33c, 0x21, 0 + .dw 0xe3c0, 0xc33c, 0xe3ff, 0xc33c, 0x21, 0 + .dw 0xe440, 0xc33c, 0xe47f, 0xc33c, 0x21, 0 + .dw 0xe4c0, 0xc33c, 0xe4ff, 0xc33c, 0x21, 0 + .dw 0xe540, 0xc33c, 0xe57f, 0xc33c, 0x21, 0 + .dw 0xe5c0, 0xc33c, 0xe5ff, 0xc33c, 0x21, 0 + .dw 0xe640, 0xc33c, 0xe67f, 0xc33c, 0x21, 0 + .dw 0xe6c0, 0xc33c, 0xe6ff, 0xc33c, 0x21, 0 + .dw 0xe740, 0xc33c, 0xe77f, 0xc33c, 0x21, 0 + .dw 0xe7c0, 0xc33c, 0x1fff, 0xc360, 0x21, 0 + .dw 0x2800, 0xc360, 0xffff, 0xc363, 0x21, 0 + .dw 0x0200, 0xc364, 0x1fff, 0xc364, 0x21, 0 + .dw 0x2800, 0xc364, 0x3fff, 0xc364, 0x21, 0 + .dw 0x4200, 0xc364, 0x5fff, 0xc364, 0x21, 0 + .dw 0x6800, 0xc364, 0x7fff, 0xc364, 0x21, 0 + .dw 0x8200, 0xc364, 0x9fff, 0xc364, 0x21, 0 + .dw 0xa800, 0xc364, 0xbfff, 0xc364, 0x21, 0 + .dw 0xc200, 0xc364, 0xdfff, 0xc364, 0x21, 0 + .dw 0xe800, 0xc364, 0xffff, 0xc373, 0x21, 0 + .dw 0x0200, 0xc374, 0x1fff, 0xc374, 0x21, 0 + .dw 0x2800, 0xc374, 0x3fff, 0xc374, 0x21, 0 + .dw 0x4200, 0xc374, 0x5fff, 0xc374, 0x21, 0 + .dw 0x6800, 0xc374, 0x7fff, 0xc374, 0x21, 0 + .dw 0x8200, 0xc374, 0x9fff, 0xc374, 0x21, 0 + .dw 0xa800, 0xc374, 0xbfff, 0xc374, 0x21, 0 + .dw 0xc200, 0xc374, 0xdfff, 0xc374, 0x21, 0 + .dw 0xe800, 0xc374, 0x1fff, 0xc380, 0x21, 0 + .dw 0x2800, 0xc380, 0xffff, 0xc383, 0x21, 0 + .dw 0x0200, 0xc384, 0x1fff, 0xc384, 0x21, 0 + .dw 0x2800, 0xc384, 0x3fff, 0xc384, 0x21, 0 + .dw 0x4200, 0xc384, 0x5fff, 0xc384, 0x21, 0 + .dw 0x6800, 0xc384, 0x7fff, 0xc384, 0x21, 0 + .dw 0x8200, 0xc384, 0x9fff, 0xc384, 0x21, 0 + .dw 0xa800, 0xc384, 0xbfff, 0xc384, 0x21, 0 + .dw 0xc200, 0xc384, 0xdfff, 0xc384, 0x21, 0 + .dw 0xe800, 0xc384, 0x1fff, 0xc388, 0x21, 0 + .dw 0x2040, 0xc388, 0x207f, 0xc388, 0x21, 0 + .dw 0x20c0, 0xc388, 0x20ff, 0xc388, 0x21, 0 + .dw 0x2140, 0xc388, 0x217f, 0xc388, 0x21, 0 + .dw 0x21c0, 0xc388, 0x21ff, 0xc388, 0x21, 0 + .dw 0x2240, 0xc388, 0x227f, 0xc388, 0x21, 0 + .dw 0x22c0, 0xc388, 0x22ff, 0xc388, 0x21, 0 + .dw 0x2340, 0xc388, 0x237f, 0xc388, 0x21, 0 + .dw 0x23c0, 0xc388, 0x23ff, 0xc388, 0x21, 0 + .dw 0x2440, 0xc388, 0x247f, 0xc388, 0x21, 0 + .dw 0x24c0, 0xc388, 0x24ff, 0xc388, 0x21, 0 + .dw 0x2540, 0xc388, 0x257f, 0xc388, 0x21, 0 + .dw 0x25c0, 0xc388, 0x25ff, 0xc388, 0x21, 0 + .dw 0x2640, 0xc388, 0x267f, 0xc388, 0x21, 0 + .dw 0x26c0, 0xc388, 0x26ff, 0xc388, 0x21, 0 + .dw 0x2740, 0xc388, 0x277f, 0xc388, 0x21, 0 + .dw 0x27c0, 0xc388, 0xffff, 0xc38b, 0x21, 0 + .dw 0x0040, 0xc38c, 0x007f, 0xc38c, 0x21, 0 + .dw 0x00c0, 0xc38c, 0x00ff, 0xc38c, 0x21, 0 + .dw 0x0140, 0xc38c, 0x017f, 0xc38c, 0x21, 0 + .dw 0x01c0, 0xc38c, 0x1fff, 0xc38c, 0x21, 0 + .dw 0x2040, 0xc38c, 0x207f, 0xc38c, 0x21, 0 + .dw 0x20c0, 0xc38c, 0x20ff, 0xc38c, 0x21, 0 + .dw 0x2140, 0xc38c, 0x217f, 0xc38c, 0x21, 0 + .dw 0x21c0, 0xc38c, 0x21ff, 0xc38c, 0x21, 0 + .dw 0x2240, 0xc38c, 0x227f, 0xc38c, 0x21, 0 + .dw 0x22c0, 0xc38c, 0x22ff, 0xc38c, 0x21, 0 + .dw 0x2340, 0xc38c, 0x237f, 0xc38c, 0x21, 0 + .dw 0x23c0, 0xc38c, 0x23ff, 0xc38c, 0x21, 0 + .dw 0x2440, 0xc38c, 0x247f, 0xc38c, 0x21, 0 + .dw 0x24c0, 0xc38c, 0x24ff, 0xc38c, 0x21, 0 + .dw 0x2540, 0xc38c, 0x257f, 0xc38c, 0x21, 0 + .dw 0x25c0, 0xc38c, 0x25ff, 0xc38c, 0x21, 0 + .dw 0x2640, 0xc38c, 0x267f, 0xc38c, 0x21, 0 + .dw 0x26c0, 0xc38c, 0x26ff, 0xc38c, 0x21, 0 + .dw 0x2740, 0xc38c, 0x277f, 0xc38c, 0x21, 0 + .dw 0x27c0, 0xc38c, 0x3fff, 0xc38c, 0x21, 0 + .dw 0x4040, 0xc38c, 0x407f, 0xc38c, 0x21, 0 + .dw 0x40c0, 0xc38c, 0x40ff, 0xc38c, 0x21, 0 + .dw 0x4140, 0xc38c, 0x417f, 0xc38c, 0x21, 0 + .dw 0x41c0, 0xc38c, 0x5fff, 0xc38c, 0x21, 0 + .dw 0x6040, 0xc38c, 0x607f, 0xc38c, 0x21, 0 + .dw 0x60c0, 0xc38c, 0x60ff, 0xc38c, 0x21, 0 + .dw 0x6140, 0xc38c, 0x617f, 0xc38c, 0x21, 0 + .dw 0x61c0, 0xc38c, 0x61ff, 0xc38c, 0x21, 0 + .dw 0x6240, 0xc38c, 0x627f, 0xc38c, 0x21, 0 + .dw 0x62c0, 0xc38c, 0x62ff, 0xc38c, 0x21, 0 + .dw 0x6340, 0xc38c, 0x637f, 0xc38c, 0x21, 0 + .dw 0x63c0, 0xc38c, 0x63ff, 0xc38c, 0x21, 0 + .dw 0x6440, 0xc38c, 0x647f, 0xc38c, 0x21, 0 + .dw 0x64c0, 0xc38c, 0x64ff, 0xc38c, 0x21, 0 + .dw 0x6540, 0xc38c, 0x657f, 0xc38c, 0x21, 0 + .dw 0x65c0, 0xc38c, 0x65ff, 0xc38c, 0x21, 0 + .dw 0x6640, 0xc38c, 0x667f, 0xc38c, 0x21, 0 + .dw 0x66c0, 0xc38c, 0x66ff, 0xc38c, 0x21, 0 + .dw 0x6740, 0xc38c, 0x677f, 0xc38c, 0x21, 0 + .dw 0x67c0, 0xc38c, 0x7fff, 0xc38c, 0x21, 0 + .dw 0x8040, 0xc38c, 0x807f, 0xc38c, 0x21, 0 + .dw 0x80c0, 0xc38c, 0x80ff, 0xc38c, 0x21, 0 + .dw 0x8140, 0xc38c, 0x817f, 0xc38c, 0x21, 0 + .dw 0x81c0, 0xc38c, 0x9fff, 0xc38c, 0x21, 0 + .dw 0xa040, 0xc38c, 0xa07f, 0xc38c, 0x21, 0 + .dw 0xa0c0, 0xc38c, 0xa0ff, 0xc38c, 0x21, 0 + .dw 0xa140, 0xc38c, 0xa17f, 0xc38c, 0x21, 0 + .dw 0xa1c0, 0xc38c, 0xa1ff, 0xc38c, 0x21, 0 + .dw 0xa240, 0xc38c, 0xa27f, 0xc38c, 0x21, 0 + .dw 0xa2c0, 0xc38c, 0xa2ff, 0xc38c, 0x21, 0 + .dw 0xa340, 0xc38c, 0xa37f, 0xc38c, 0x21, 0 + .dw 0xa3c0, 0xc38c, 0xa3ff, 0xc38c, 0x21, 0 + .dw 0xa440, 0xc38c, 0xa47f, 0xc38c, 0x21, 0 + .dw 0xa4c0, 0xc38c, 0xa4ff, 0xc38c, 0x21, 0 + .dw 0xa540, 0xc38c, 0xa57f, 0xc38c, 0x21, 0 + .dw 0xa5c0, 0xc38c, 0xa5ff, 0xc38c, 0x21, 0 + .dw 0xa640, 0xc38c, 0xa67f, 0xc38c, 0x21, 0 + .dw 0xa6c0, 0xc38c, 0xa6ff, 0xc38c, 0x21, 0 + .dw 0xa740, 0xc38c, 0xa77f, 0xc38c, 0x21, 0 + .dw 0xa7c0, 0xc38c, 0xbfff, 0xc38c, 0x21, 0 + .dw 0xc040, 0xc38c, 0xc07f, 0xc38c, 0x21, 0 + .dw 0xc0c0, 0xc38c, 0xc0ff, 0xc38c, 0x21, 0 + .dw 0xc140, 0xc38c, 0xc17f, 0xc38c, 0x21, 0 + .dw 0xc1c0, 0xc38c, 0xdfff, 0xc38c, 0x21, 0 + .dw 0xe040, 0xc38c, 0xe07f, 0xc38c, 0x21, 0 + .dw 0xe0c0, 0xc38c, 0xe0ff, 0xc38c, 0x21, 0 + .dw 0xe140, 0xc38c, 0xe17f, 0xc38c, 0x21, 0 + .dw 0xe1c0, 0xc38c, 0xe1ff, 0xc38c, 0x21, 0 + .dw 0xe240, 0xc38c, 0xe27f, 0xc38c, 0x21, 0 + .dw 0xe2c0, 0xc38c, 0xe2ff, 0xc38c, 0x21, 0 + .dw 0xe340, 0xc38c, 0xe37f, 0xc38c, 0x21, 0 + .dw 0xe3c0, 0xc38c, 0xe3ff, 0xc38c, 0x21, 0 + .dw 0xe440, 0xc38c, 0xe47f, 0xc38c, 0x21, 0 + .dw 0xe4c0, 0xc38c, 0xe4ff, 0xc38c, 0x21, 0 + .dw 0xe540, 0xc38c, 0xe57f, 0xc38c, 0x21, 0 + .dw 0xe5c0, 0xc38c, 0xe5ff, 0xc38c, 0x21, 0 + .dw 0xe640, 0xc38c, 0xe67f, 0xc38c, 0x21, 0 + .dw 0xe6c0, 0xc38c, 0xe6ff, 0xc38c, 0x21, 0 + .dw 0xe740, 0xc38c, 0xe77f, 0xc38c, 0x21, 0 + .dw 0xe7c0, 0xc38c, 0xffff, 0xc393, 0x21, 0 + .dw 0x0200, 0xc394, 0x1fff, 0xc394, 0x21, 0 + .dw 0x2800, 0xc394, 0x3fff, 0xc394, 0x21, 0 + .dw 0x4200, 0xc394, 0x5fff, 0xc394, 0x21, 0 + .dw 0x6800, 0xc394, 0x7fff, 0xc394, 0x21, 0 + .dw 0x8200, 0xc394, 0x9fff, 0xc394, 0x21, 0 + .dw 0xa800, 0xc394, 0xbfff, 0xc394, 0x21, 0 + .dw 0xc200, 0xc394, 0xdfff, 0xc394, 0x21, 0 + .dw 0xe800, 0xc394, 0xffff, 0xc39b, 0x21, 0 + .dw 0x0040, 0xc39c, 0x007f, 0xc39c, 0x21, 0 + .dw 0x00c0, 0xc39c, 0x00ff, 0xc39c, 0x21, 0 + .dw 0x0140, 0xc39c, 0x017f, 0xc39c, 0x21, 0 + .dw 0x01c0, 0xc39c, 0x1fff, 0xc39c, 0x21, 0 + .dw 0x2040, 0xc39c, 0x207f, 0xc39c, 0x21, 0 + .dw 0x20c0, 0xc39c, 0x20ff, 0xc39c, 0x21, 0 + .dw 0x2140, 0xc39c, 0x217f, 0xc39c, 0x21, 0 + .dw 0x21c0, 0xc39c, 0x21ff, 0xc39c, 0x21, 0 + .dw 0x2240, 0xc39c, 0x227f, 0xc39c, 0x21, 0 + .dw 0x22c0, 0xc39c, 0x22ff, 0xc39c, 0x21, 0 + .dw 0x2340, 0xc39c, 0x237f, 0xc39c, 0x21, 0 + .dw 0x23c0, 0xc39c, 0x23ff, 0xc39c, 0x21, 0 + .dw 0x2440, 0xc39c, 0x247f, 0xc39c, 0x21, 0 + .dw 0x24c0, 0xc39c, 0x24ff, 0xc39c, 0x21, 0 + .dw 0x2540, 0xc39c, 0x257f, 0xc39c, 0x21, 0 + .dw 0x25c0, 0xc39c, 0x25ff, 0xc39c, 0x21, 0 + .dw 0x2640, 0xc39c, 0x267f, 0xc39c, 0x21, 0 + .dw 0x26c0, 0xc39c, 0x26ff, 0xc39c, 0x21, 0 + .dw 0x2740, 0xc39c, 0x277f, 0xc39c, 0x21, 0 + .dw 0x27c0, 0xc39c, 0x3fff, 0xc39c, 0x21, 0 + .dw 0x4040, 0xc39c, 0x407f, 0xc39c, 0x21, 0 + .dw 0x40c0, 0xc39c, 0x40ff, 0xc39c, 0x21, 0 + .dw 0x4140, 0xc39c, 0x417f, 0xc39c, 0x21, 0 + .dw 0x41c0, 0xc39c, 0x5fff, 0xc39c, 0x21, 0 + .dw 0x6040, 0xc39c, 0x607f, 0xc39c, 0x21, 0 + .dw 0x60c0, 0xc39c, 0x60ff, 0xc39c, 0x21, 0 + .dw 0x6140, 0xc39c, 0x617f, 0xc39c, 0x21, 0 + .dw 0x61c0, 0xc39c, 0x61ff, 0xc39c, 0x21, 0 + .dw 0x6240, 0xc39c, 0x627f, 0xc39c, 0x21, 0 + .dw 0x62c0, 0xc39c, 0x62ff, 0xc39c, 0x21, 0 + .dw 0x6340, 0xc39c, 0x637f, 0xc39c, 0x21, 0 + .dw 0x63c0, 0xc39c, 0x63ff, 0xc39c, 0x21, 0 + .dw 0x6440, 0xc39c, 0x647f, 0xc39c, 0x21, 0 + .dw 0x64c0, 0xc39c, 0x64ff, 0xc39c, 0x21, 0 + .dw 0x6540, 0xc39c, 0x657f, 0xc39c, 0x21, 0 + .dw 0x65c0, 0xc39c, 0x65ff, 0xc39c, 0x21, 0 + .dw 0x6640, 0xc39c, 0x667f, 0xc39c, 0x21, 0 + .dw 0x66c0, 0xc39c, 0x66ff, 0xc39c, 0x21, 0 + .dw 0x6740, 0xc39c, 0x677f, 0xc39c, 0x21, 0 + .dw 0x67c0, 0xc39c, 0x7fff, 0xc39c, 0x21, 0 + .dw 0x8040, 0xc39c, 0x807f, 0xc39c, 0x21, 0 + .dw 0x80c0, 0xc39c, 0x80ff, 0xc39c, 0x21, 0 + .dw 0x8140, 0xc39c, 0x817f, 0xc39c, 0x21, 0 + .dw 0x81c0, 0xc39c, 0x9fff, 0xc39c, 0x21, 0 + .dw 0xa040, 0xc39c, 0xa07f, 0xc39c, 0x21, 0 + .dw 0xa0c0, 0xc39c, 0xa0ff, 0xc39c, 0x21, 0 + .dw 0xa140, 0xc39c, 0xa17f, 0xc39c, 0x21, 0 + .dw 0xa1c0, 0xc39c, 0xa1ff, 0xc39c, 0x21, 0 + .dw 0xa240, 0xc39c, 0xa27f, 0xc39c, 0x21, 0 + .dw 0xa2c0, 0xc39c, 0xa2ff, 0xc39c, 0x21, 0 + .dw 0xa340, 0xc39c, 0xa37f, 0xc39c, 0x21, 0 + .dw 0xa3c0, 0xc39c, 0xa3ff, 0xc39c, 0x21, 0 + .dw 0xa440, 0xc39c, 0xa47f, 0xc39c, 0x21, 0 + .dw 0xa4c0, 0xc39c, 0xa4ff, 0xc39c, 0x21, 0 + .dw 0xa540, 0xc39c, 0xa57f, 0xc39c, 0x21, 0 + .dw 0xa5c0, 0xc39c, 0xa5ff, 0xc39c, 0x21, 0 + .dw 0xa640, 0xc39c, 0xa67f, 0xc39c, 0x21, 0 + .dw 0xa6c0, 0xc39c, 0xa6ff, 0xc39c, 0x21, 0 + .dw 0xa740, 0xc39c, 0xa77f, 0xc39c, 0x21, 0 + .dw 0xa7c0, 0xc39c, 0xbfff, 0xc39c, 0x21, 0 + .dw 0xc040, 0xc39c, 0xc07f, 0xc39c, 0x21, 0 + .dw 0xc0c0, 0xc39c, 0xc0ff, 0xc39c, 0x21, 0 + .dw 0xc140, 0xc39c, 0xc17f, 0xc39c, 0x21, 0 + .dw 0xc1c0, 0xc39c, 0xdfff, 0xc39c, 0x21, 0 + .dw 0xe040, 0xc39c, 0xe07f, 0xc39c, 0x21, 0 + .dw 0xe0c0, 0xc39c, 0xe0ff, 0xc39c, 0x21, 0 + .dw 0xe140, 0xc39c, 0xe17f, 0xc39c, 0x21, 0 + .dw 0xe1c0, 0xc39c, 0xe1ff, 0xc39c, 0x21, 0 + .dw 0xe240, 0xc39c, 0xe27f, 0xc39c, 0x21, 0 + .dw 0xe2c0, 0xc39c, 0xe2ff, 0xc39c, 0x21, 0 + .dw 0xe340, 0xc39c, 0xe37f, 0xc39c, 0x21, 0 + .dw 0xe3c0, 0xc39c, 0xe3ff, 0xc39c, 0x21, 0 + .dw 0xe440, 0xc39c, 0xe47f, 0xc39c, 0x21, 0 + .dw 0xe4c0, 0xc39c, 0xe4ff, 0xc39c, 0x21, 0 + .dw 0xe540, 0xc39c, 0xe57f, 0xc39c, 0x21, 0 + .dw 0xe5c0, 0xc39c, 0xe5ff, 0xc39c, 0x21, 0 + .dw 0xe640, 0xc39c, 0xe67f, 0xc39c, 0x21, 0 + .dw 0xe6c0, 0xc39c, 0xe6ff, 0xc39c, 0x21, 0 + .dw 0xe740, 0xc39c, 0xe77f, 0xc39c, 0x21, 0 + .dw 0xe7c0, 0xc39c, 0xffff, 0xc3ff, 0x21, 0 + .dw 0x0000, 0xc401, 0x003f, 0xc401, 0x22, 0 + .dw 0x0240, 0xc401, 0x027f, 0xc401, 0x22, 0 + .dw 0x0480, 0xc401, 0x04bf, 0xc401, 0x22, 0 + .dw 0x06c0, 0xc401, 0x06ff, 0xc401, 0x22, 0 + .dw 0x0900, 0xc401, 0x093f, 0xc401, 0x22, 0 + .dw 0x0b40, 0xc401, 0x0b7f, 0xc401, 0x22, 0 + .dw 0x0d80, 0xc401, 0x0dbf, 0xc401, 0x22, 0 + .dw 0x0fc0, 0xc401, 0x103f, 0xc401, 0x22, 0 + .dw 0x1240, 0xc401, 0x127f, 0xc401, 0x22, 0 + .dw 0x1480, 0xc401, 0x14bf, 0xc401, 0x22, 0 + .dw 0x16c0, 0xc401, 0x16ff, 0xc401, 0x22, 0 + .dw 0x1900, 0xc401, 0x193f, 0xc401, 0x22, 0 + .dw 0x1b40, 0xc401, 0x1b7f, 0xc401, 0x22, 0 + .dw 0x1d80, 0xc401, 0x1dbf, 0xc401, 0x22, 0 + .dw 0x1fc0, 0xc401, 0x203f, 0xc401, 0x22, 0 + .dw 0x2240, 0xc401, 0x227f, 0xc401, 0x22, 0 + .dw 0x2480, 0xc401, 0x24bf, 0xc401, 0x22, 0 + .dw 0x26c0, 0xc401, 0x26ff, 0xc401, 0x22, 0 + .dw 0x2900, 0xc401, 0x293f, 0xc401, 0x22, 0 + .dw 0x2b40, 0xc401, 0x2b7f, 0xc401, 0x22, 0 + .dw 0x2d80, 0xc401, 0x2dbf, 0xc401, 0x22, 0 + .dw 0x2fc0, 0xc401, 0x303f, 0xc401, 0x22, 0 + .dw 0x3240, 0xc401, 0x327f, 0xc401, 0x22, 0 + .dw 0x3480, 0xc401, 0x34bf, 0xc401, 0x22, 0 + .dw 0x36c0, 0xc401, 0x36ff, 0xc401, 0x22, 0 + .dw 0x3900, 0xc401, 0x393f, 0xc401, 0x22, 0 + .dw 0x3b40, 0xc401, 0x3b7f, 0xc401, 0x22, 0 + .dw 0x3d80, 0xc401, 0x3dbf, 0xc401, 0x22, 0 + .dw 0x3fc0, 0xc401, 0x3fff, 0xc401, 0x22, 0 + .dw 0x4000, 0xc401, 0x7fff, 0xc401, 0x21, 0 + .dw 0x8000, 0xc401, 0x803f, 0xc401, 0x22, 0 + .dw 0x8240, 0xc401, 0x827f, 0xc401, 0x22, 0 + .dw 0x8480, 0xc401, 0x84bf, 0xc401, 0x22, 0 + .dw 0x86c0, 0xc401, 0x86ff, 0xc401, 0x22, 0 + .dw 0x8900, 0xc401, 0x893f, 0xc401, 0x22, 0 + .dw 0x8b40, 0xc401, 0x8b7f, 0xc401, 0x22, 0 + .dw 0x8d80, 0xc401, 0x8dbf, 0xc401, 0x22, 0 + .dw 0x8fc0, 0xc401, 0x903f, 0xc401, 0x22, 0 + .dw 0x9240, 0xc401, 0x927f, 0xc401, 0x22, 0 + .dw 0x9480, 0xc401, 0x94bf, 0xc401, 0x22, 0 + .dw 0x96c0, 0xc401, 0x96ff, 0xc401, 0x22, 0 + .dw 0x9900, 0xc401, 0x993f, 0xc401, 0x22, 0 + .dw 0x9b40, 0xc401, 0x9b7f, 0xc401, 0x22, 0 + .dw 0x9d80, 0xc401, 0x9dbf, 0xc401, 0x22, 0 + .dw 0x9fc0, 0xc401, 0xa03f, 0xc401, 0x22, 0 + .dw 0xa240, 0xc401, 0xa27f, 0xc401, 0x22, 0 + .dw 0xa480, 0xc401, 0xa4bf, 0xc401, 0x22, 0 + .dw 0xa6c0, 0xc401, 0xa6ff, 0xc401, 0x22, 0 + .dw 0xa900, 0xc401, 0xa93f, 0xc401, 0x22, 0 + .dw 0xab40, 0xc401, 0xab7f, 0xc401, 0x22, 0 + .dw 0xad80, 0xc401, 0xadbf, 0xc401, 0x22, 0 + .dw 0xafc0, 0xc401, 0xb03f, 0xc401, 0x22, 0 + .dw 0xb240, 0xc401, 0xb27f, 0xc401, 0x22, 0 + .dw 0xb480, 0xc401, 0xb4bf, 0xc401, 0x22, 0 + .dw 0xb6c0, 0xc401, 0xb6ff, 0xc401, 0x22, 0 + .dw 0xb900, 0xc401, 0xb93f, 0xc401, 0x22, 0 + .dw 0xbb40, 0xc401, 0xbb7f, 0xc401, 0x22, 0 + .dw 0xbd80, 0xc401, 0xbdbf, 0xc401, 0x22, 0 + .dw 0xbfc0, 0xc401, 0xc03f, 0xc401, 0x22, 0 + .dw 0xc240, 0xc401, 0xc27f, 0xc401, 0x22, 0 + .dw 0xc480, 0xc401, 0xc4bf, 0xc401, 0x22, 0 + .dw 0xc6c0, 0xc401, 0xc6ff, 0xc401, 0x22, 0 + .dw 0xc900, 0xc401, 0xc93f, 0xc401, 0x22, 0 + .dw 0xcb40, 0xc401, 0xcb7f, 0xc401, 0x22, 0 + .dw 0xcd80, 0xc401, 0xcdbf, 0xc401, 0x22, 0 + .dw 0xcfc0, 0xc401, 0xd03f, 0xc401, 0x22, 0 + .dw 0xd240, 0xc401, 0xd27f, 0xc401, 0x22, 0 + .dw 0xd480, 0xc401, 0xd4bf, 0xc401, 0x22, 0 + .dw 0xd6c0, 0xc401, 0xd6ff, 0xc401, 0x22, 0 + .dw 0xd900, 0xc401, 0xd93f, 0xc401, 0x22, 0 + .dw 0xdb40, 0xc401, 0xdb7f, 0xc401, 0x22, 0 + .dw 0xdd80, 0xc401, 0xddbf, 0xc401, 0x22, 0 + .dw 0xdfc0, 0xc401, 0xe03f, 0xc401, 0x22, 0 + .dw 0xe240, 0xc401, 0xe27f, 0xc401, 0x22, 0 + .dw 0xe480, 0xc401, 0xe4bf, 0xc401, 0x22, 0 + .dw 0xe6c0, 0xc401, 0xe6ff, 0xc401, 0x22, 0 + .dw 0xe900, 0xc401, 0xe93f, 0xc401, 0x22, 0 + .dw 0xeb40, 0xc401, 0xeb7f, 0xc401, 0x22, 0 + .dw 0xed80, 0xc401, 0xedbf, 0xc401, 0x22, 0 + .dw 0xefc0, 0xc401, 0xf03f, 0xc401, 0x22, 0 + .dw 0xf240, 0xc401, 0xf27f, 0xc401, 0x22, 0 + .dw 0xf480, 0xc401, 0xf4bf, 0xc401, 0x22, 0 + .dw 0xf6c0, 0xc401, 0xf6ff, 0xc401, 0x22, 0 + .dw 0xf900, 0xc401, 0xf93f, 0xc401, 0x22, 0 + .dw 0xfb40, 0xc401, 0xfb7f, 0xc401, 0x22, 0 + .dw 0xfd80, 0xc401, 0xfdbf, 0xc401, 0x22, 0 + .dw 0xffc0, 0xc401, 0xffff, 0xc401, 0x22, 0 + .dw 0x1000, 0xc402, 0x1fff, 0xc402, 0x21, 0 + .dw 0x3000, 0xc402, 0x3fff, 0xc402, 0x21, 0 + .dw 0x5000, 0xc402, 0x5fff, 0xc402, 0x21, 0 + .dw 0x7000, 0xc402, 0x7fff, 0xc402, 0x21, 0 + .dw 0x9000, 0xc402, 0x9fff, 0xc402, 0x21, 0 + .dw 0xb000, 0xc402, 0xbfff, 0xc402, 0x21, 0 + .dw 0xd000, 0xc402, 0xdfff, 0xc402, 0x21, 0 + .dw 0xf000, 0xc402, 0xffff, 0xc402, 0x21, 0 + .dw 0x1000, 0xc403, 0x1fff, 0xc403, 0x21, 0 + .dw 0x3000, 0xc403, 0x3fff, 0xc403, 0x21, 0 + .dw 0x5000, 0xc403, 0x5fff, 0xc403, 0x21, 0 + .dw 0x7000, 0xc403, 0x7fff, 0xc403, 0x21, 0 + .dw 0x9000, 0xc403, 0x9fff, 0xc403, 0x21, 0 + .dw 0xb000, 0xc403, 0xbfff, 0xc403, 0x21, 0 + .dw 0xd000, 0xc403, 0xdfff, 0xc403, 0x21, 0 + .dw 0xf000, 0xc403, 0xffff, 0xc403, 0x21, 0 + .dw 0x1000, 0xc404, 0x1fff, 0xc404, 0x21, 0 + .dw 0x3000, 0xc404, 0x3fff, 0xc404, 0x21, 0 + .dw 0x5000, 0xc404, 0x5fff, 0xc404, 0x21, 0 + .dw 0x7000, 0xc404, 0x7fff, 0xc404, 0x21, 0 + .dw 0x8000, 0xc404, 0x803f, 0xc404, 0x22, 0 + .dw 0x8240, 0xc404, 0x827f, 0xc404, 0x22, 0 + .dw 0x8480, 0xc404, 0x84bf, 0xc404, 0x22, 0 + .dw 0x86c0, 0xc404, 0x86ff, 0xc404, 0x22, 0 + .dw 0x8900, 0xc404, 0x893f, 0xc404, 0x22, 0 + .dw 0x8b40, 0xc404, 0x8b7f, 0xc404, 0x22, 0 + .dw 0x8d80, 0xc404, 0x8dbf, 0xc404, 0x22, 0 + .dw 0x8fc0, 0xc404, 0x8fff, 0xc404, 0x22, 0 + .dw 0x9000, 0xc404, 0x9fff, 0xc404, 0x21, 0 + .dw 0xa000, 0xc404, 0xa03f, 0xc404, 0x22, 0 + .dw 0xa240, 0xc404, 0xa27f, 0xc404, 0x22, 0 + .dw 0xa480, 0xc404, 0xa4bf, 0xc404, 0x22, 0 + .dw 0xa6c0, 0xc404, 0xa6ff, 0xc404, 0x22, 0 + .dw 0xa900, 0xc404, 0xa93f, 0xc404, 0x22, 0 + .dw 0xab40, 0xc404, 0xab7f, 0xc404, 0x22, 0 + .dw 0xad80, 0xc404, 0xadbf, 0xc404, 0x22, 0 + .dw 0xafc0, 0xc404, 0xafff, 0xc404, 0x22, 0 + .dw 0xb000, 0xc404, 0xffff, 0xc404, 0x21, 0 + .dw 0x1000, 0xc405, 0x3fff, 0xc405, 0x21, 0 + .dw 0x5000, 0xc405, 0x8fff, 0xc405, 0x21, 0 + .dw 0xa000, 0xc405, 0xcfff, 0xc405, 0x21, 0 + .dw 0xe000, 0xc405, 0xffff, 0xc405, 0x21, 0 + .dw 0x1000, 0xc406, 0x3fff, 0xc406, 0x21, 0 + .dw 0x5000, 0xc406, 0x7fff, 0xc406, 0x21, 0 + .dw 0x9000, 0xc406, 0xffff, 0xc406, 0x21, 0 + .dw 0x1000, 0xc407, 0x3fff, 0xc407, 0x21, 0 + .dw 0x5000, 0xc407, 0x7fff, 0xc407, 0x21, 0 + .dw 0x9000, 0xc407, 0xbfff, 0xc407, 0x21, 0 + .dw 0xd000, 0xc407, 0xdfff, 0xc407, 0x21, 0 + .dw 0xf000, 0xc407, 0xffff, 0xc407, 0x21, 0 + .dw 0x1000, 0xc408, 0x1fff, 0xc408, 0x21, 0 + .dw 0x3000, 0xc408, 0x3fff, 0xc408, 0x21, 0 + .dw 0x5000, 0xc408, 0x5fff, 0xc408, 0x21, 0 + .dw 0x7000, 0xc408, 0x7fff, 0xc408, 0x21, 0 + .dw 0x9000, 0xc408, 0x9fff, 0xc408, 0x21, 0 + .dw 0xb000, 0xc408, 0xbfff, 0xc408, 0x21, 0 + .dw 0xd000, 0xc408, 0xdfff, 0xc408, 0x21, 0 + .dw 0xf000, 0xc408, 0xffff, 0xc408, 0x21, 0 + .dw 0x1000, 0xc409, 0x1fff, 0xc409, 0x21, 0 + .dw 0x3000, 0xc409, 0x3fff, 0xc409, 0x21, 0 + .dw 0x5000, 0xc409, 0x7fff, 0xc409, 0x21, 0 + .dw 0x9000, 0xc409, 0x9fff, 0xc409, 0x21, 0 + .dw 0xb000, 0xc409, 0xbfff, 0xc409, 0x21, 0 + .dw 0xd000, 0xc409, 0xffff, 0xc409, 0x21, 0 + .dw 0x1000, 0xc40a, 0x3fff, 0xc40a, 0x21, 0 + .dw 0x5000, 0xc40a, 0xffff, 0xc40a, 0x21, 0 + .dw 0x1000, 0xc40b, 0x3fff, 0xc40b, 0x21, 0 + .dw 0x5000, 0xc40b, 0x7fff, 0xc40b, 0x21, 0 + .dw 0x9000, 0xc40b, 0x9fff, 0xc40b, 0x21, 0 + .dw 0xb000, 0xc40b, 0xbfff, 0xc40b, 0x21, 0 + .dw 0xd000, 0xc40b, 0xdfff, 0xc40b, 0x21, 0 + .dw 0xf000, 0xc40b, 0xffff, 0xc40b, 0x21, 0 + .dw 0x1000, 0xc40c, 0x3fff, 0xc40c, 0x21, 0 + .dw 0x4000, 0xc40c, 0x403f, 0xc40c, 0x22, 0 + .dw 0x4240, 0xc40c, 0x427f, 0xc40c, 0x22, 0 + .dw 0x4480, 0xc40c, 0x44bf, 0xc40c, 0x22, 0 + .dw 0x46c0, 0xc40c, 0x46ff, 0xc40c, 0x22, 0 + .dw 0x4900, 0xc40c, 0x493f, 0xc40c, 0x22, 0 + .dw 0x4b40, 0xc40c, 0x4b7f, 0xc40c, 0x22, 0 + .dw 0x4d80, 0xc40c, 0x4dbf, 0xc40c, 0x22, 0 + .dw 0x4fc0, 0xc40c, 0x4fff, 0xc40c, 0x22, 0 + .dw 0x5000, 0xc40c, 0xbfff, 0xc40c, 0x21, 0 + .dw 0xd000, 0xc40c, 0xffff, 0xc40c, 0x21, 0 + .dw 0x0000, 0xc40d, 0x003f, 0xc40d, 0x22, 0 + .dw 0x0240, 0xc40d, 0x027f, 0xc40d, 0x22, 0 + .dw 0x0480, 0xc40d, 0x04bf, 0xc40d, 0x22, 0 + .dw 0x06c0, 0xc40d, 0x06ff, 0xc40d, 0x22, 0 + .dw 0x0900, 0xc40d, 0x093f, 0xc40d, 0x22, 0 + .dw 0x0b40, 0xc40d, 0x0b7f, 0xc40d, 0x22, 0 + .dw 0x0d80, 0xc40d, 0x0dbf, 0xc40d, 0x22, 0 + .dw 0x0fc0, 0xc40d, 0x0fff, 0xc40d, 0x22, 0 + .dw 0x1000, 0xc40d, 0x3fff, 0xc40d, 0x21, 0 + .dw 0x4000, 0xc40d, 0x403f, 0xc40d, 0x22, 0 + .dw 0x4240, 0xc40d, 0x427f, 0xc40d, 0x22, 0 + .dw 0x4480, 0xc40d, 0x44bf, 0xc40d, 0x22, 0 + .dw 0x46c0, 0xc40d, 0x46ff, 0xc40d, 0x22, 0 + .dw 0x4900, 0xc40d, 0x493f, 0xc40d, 0x22, 0 + .dw 0x4b40, 0xc40d, 0x4b7f, 0xc40d, 0x22, 0 + .dw 0x4d80, 0xc40d, 0x4dbf, 0xc40d, 0x22, 0 + .dw 0x4fc0, 0xc40d, 0x4fff, 0xc40d, 0x22, 0 + .dw 0x5000, 0xc40d, 0x7fff, 0xc40d, 0x21, 0 + .dw 0x8000, 0xc40d, 0x803f, 0xc40d, 0x22, 0 + .dw 0x8240, 0xc40d, 0x827f, 0xc40d, 0x22, 0 + .dw 0x8480, 0xc40d, 0x84bf, 0xc40d, 0x22, 0 + .dw 0x86c0, 0xc40d, 0x86ff, 0xc40d, 0x22, 0 + .dw 0x8900, 0xc40d, 0x893f, 0xc40d, 0x22, 0 + .dw 0x8b40, 0xc40d, 0x8b7f, 0xc40d, 0x22, 0 + .dw 0x8d80, 0xc40d, 0x8dbf, 0xc40d, 0x22, 0 + .dw 0x8fc0, 0xc40d, 0x8fff, 0xc40d, 0x22, 0 + .dw 0x9000, 0xc40d, 0xbfff, 0xc40d, 0x21, 0 + .dw 0xc000, 0xc40d, 0xc03f, 0xc40d, 0x22, 0 + .dw 0xc240, 0xc40d, 0xc27f, 0xc40d, 0x22, 0 + .dw 0xc480, 0xc40d, 0xc4bf, 0xc40d, 0x22, 0 + .dw 0xc6c0, 0xc40d, 0xc6ff, 0xc40d, 0x22, 0 + .dw 0xc900, 0xc40d, 0xc93f, 0xc40d, 0x22, 0 + .dw 0xcb40, 0xc40d, 0xcb7f, 0xc40d, 0x22, 0 + .dw 0xcd80, 0xc40d, 0xcdbf, 0xc40d, 0x22, 0 + .dw 0xcfc0, 0xc40d, 0xcfff, 0xc40d, 0x22, 0 + .dw 0xd000, 0xc40d, 0xffff, 0xc40d, 0x21, 0 + .dw 0x1000, 0xc40e, 0x3fff, 0xc40e, 0x21, 0 + .dw 0x5000, 0xc40e, 0xbfff, 0xc40e, 0x21, 0 + .dw 0xd000, 0xc40e, 0xbfff, 0xc40f, 0x21, 0 + .dw 0xd000, 0xc40f, 0xffff, 0xc40f, 0x21, 0 + .dw 0x1000, 0xc410, 0x3fff, 0xc410, 0x21, 0 + .dw 0x5000, 0xc410, 0xbfff, 0xc410, 0x21, 0 + .dw 0xd000, 0xc410, 0xffff, 0xc410, 0x21, 0 + .dw 0x0000, 0xc411, 0x003f, 0xc411, 0x22, 0 + .dw 0x0240, 0xc411, 0x027f, 0xc411, 0x22, 0 + .dw 0x0480, 0xc411, 0x04bf, 0xc411, 0x22, 0 + .dw 0x06c0, 0xc411, 0x06ff, 0xc411, 0x22, 0 + .dw 0x0900, 0xc411, 0x093f, 0xc411, 0x22, 0 + .dw 0x0b40, 0xc411, 0x0b7f, 0xc411, 0x22, 0 + .dw 0x0d80, 0xc411, 0x0dbf, 0xc411, 0x22, 0 + .dw 0x0fc0, 0xc411, 0x0fff, 0xc411, 0x22, 0 + .dw 0x1000, 0xc411, 0x1fff, 0xc411, 0x21, 0 + .dw 0x2000, 0xc411, 0x203f, 0xc411, 0x22, 0 + .dw 0x2240, 0xc411, 0x227f, 0xc411, 0x22, 0 + .dw 0x2480, 0xc411, 0x24bf, 0xc411, 0x22, 0 + .dw 0x26c0, 0xc411, 0x26ff, 0xc411, 0x22, 0 + .dw 0x2900, 0xc411, 0x293f, 0xc411, 0x22, 0 + .dw 0x2b40, 0xc411, 0x2b7f, 0xc411, 0x22, 0 + .dw 0x2d80, 0xc411, 0x2dbf, 0xc411, 0x22, 0 + .dw 0x2fc0, 0xc411, 0x2fff, 0xc411, 0x22, 0 + .dw 0x3000, 0xc411, 0x3fff, 0xc411, 0x21, 0 + .dw 0x4000, 0xc411, 0x403f, 0xc411, 0x22, 0 + .dw 0x4240, 0xc411, 0x427f, 0xc411, 0x22, 0 + .dw 0x4480, 0xc411, 0x44bf, 0xc411, 0x22, 0 + .dw 0x46c0, 0xc411, 0x46ff, 0xc411, 0x22, 0 + .dw 0x4900, 0xc411, 0x493f, 0xc411, 0x22, 0 + .dw 0x4b40, 0xc411, 0x4b7f, 0xc411, 0x22, 0 + .dw 0x4d80, 0xc411, 0x4dbf, 0xc411, 0x22, 0 + .dw 0x4fc0, 0xc411, 0x4fff, 0xc411, 0x22, 0 + .dw 0x5000, 0xc411, 0x5fff, 0xc411, 0x21, 0 + .dw 0x6000, 0xc411, 0x603f, 0xc411, 0x22, 0 + .dw 0x6240, 0xc411, 0x627f, 0xc411, 0x22, 0 + .dw 0x6480, 0xc411, 0x64bf, 0xc411, 0x22, 0 + .dw 0x66c0, 0xc411, 0x66ff, 0xc411, 0x22, 0 + .dw 0x6900, 0xc411, 0x693f, 0xc411, 0x22, 0 + .dw 0x6b40, 0xc411, 0x6b7f, 0xc411, 0x22, 0 + .dw 0x6d80, 0xc411, 0x6dbf, 0xc411, 0x22, 0 + .dw 0x6fc0, 0xc411, 0x6fff, 0xc411, 0x22, 0 + .dw 0x7000, 0xc411, 0xffff, 0xc411, 0x21, 0 + .dw 0x0001, 0xc412, 0x0001, 0xc412, 0x21, 0 + .dw 0x0003, 0xc412, 0x000f, 0xc412, 0x21, 0 + .dw 0x0011, 0xc412, 0x0011, 0xc412, 0x21, 0 + .dw 0x0013, 0xc412, 0x003f, 0xc412, 0x21, 0 + .dw 0x0041, 0xc412, 0x0041, 0xc412, 0x21, 0 + .dw 0x0043, 0xc412, 0x004f, 0xc412, 0x21, 0 + .dw 0x0051, 0xc412, 0x0051, 0xc412, 0x21, 0 + .dw 0x0053, 0xc412, 0x007f, 0xc412, 0x21, 0 + .dw 0x0081, 0xc412, 0x0081, 0xc412, 0x21, 0 + .dw 0x0083, 0xc412, 0x008f, 0xc412, 0x21, 0 + .dw 0x0091, 0xc412, 0x0091, 0xc412, 0x21, 0 + .dw 0x0093, 0xc412, 0x00bf, 0xc412, 0x21, 0 + .dw 0x00c1, 0xc412, 0x00c1, 0xc412, 0x21, 0 + .dw 0x00c3, 0xc412, 0x00cf, 0xc412, 0x21, 0 + .dw 0x00d1, 0xc412, 0x00d1, 0xc412, 0x21, 0 + .dw 0x00d3, 0xc412, 0x00ff, 0xc412, 0x21, 0 + .dw 0x0101, 0xc412, 0x0101, 0xc412, 0x21, 0 + .dw 0x0103, 0xc412, 0x010f, 0xc412, 0x21, 0 + .dw 0x0111, 0xc412, 0x0111, 0xc412, 0x21, 0 + .dw 0x0113, 0xc412, 0x013f, 0xc412, 0x21, 0 + .dw 0x0141, 0xc412, 0x0141, 0xc412, 0x21, 0 + .dw 0x0143, 0xc412, 0x014f, 0xc412, 0x21, 0 + .dw 0x0151, 0xc412, 0x0151, 0xc412, 0x21, 0 + .dw 0x0153, 0xc412, 0x017f, 0xc412, 0x21, 0 + .dw 0x0181, 0xc412, 0x0181, 0xc412, 0x21, 0 + .dw 0x0183, 0xc412, 0x018f, 0xc412, 0x21, 0 + .dw 0x0191, 0xc412, 0x0191, 0xc412, 0x21, 0 + .dw 0x0193, 0xc412, 0x01bf, 0xc412, 0x21, 0 + .dw 0x01c1, 0xc412, 0x01c1, 0xc412, 0x21, 0 + .dw 0x01c3, 0xc412, 0x01cf, 0xc412, 0x21, 0 + .dw 0x01d1, 0xc412, 0x01d1, 0xc412, 0x21, 0 + .dw 0x01d3, 0xc412, 0x01ff, 0xc412, 0x21, 0 + .dw 0x0201, 0xc412, 0x0201, 0xc412, 0x21, 0 + .dw 0x0203, 0xc412, 0x020f, 0xc412, 0x21, 0 + .dw 0x0211, 0xc412, 0x0211, 0xc412, 0x21, 0 + .dw 0x0213, 0xc412, 0x023f, 0xc412, 0x21, 0 + .dw 0x0241, 0xc412, 0x0241, 0xc412, 0x21, 0 + .dw 0x0243, 0xc412, 0x024f, 0xc412, 0x21, 0 + .dw 0x0251, 0xc412, 0x0251, 0xc412, 0x21, 0 + .dw 0x0253, 0xc412, 0x027f, 0xc412, 0x21, 0 + .dw 0x0281, 0xc412, 0x0281, 0xc412, 0x21, 0 + .dw 0x0283, 0xc412, 0x028f, 0xc412, 0x21, 0 + .dw 0x0291, 0xc412, 0x0291, 0xc412, 0x21, 0 + .dw 0x0293, 0xc412, 0x02bf, 0xc412, 0x21, 0 + .dw 0x02c1, 0xc412, 0x02c1, 0xc412, 0x21, 0 + .dw 0x02c3, 0xc412, 0x02cf, 0xc412, 0x21, 0 + .dw 0x02d1, 0xc412, 0x02d1, 0xc412, 0x21, 0 + .dw 0x02d3, 0xc412, 0x02ff, 0xc412, 0x21, 0 + .dw 0x0301, 0xc412, 0x0301, 0xc412, 0x21, 0 + .dw 0x0303, 0xc412, 0x030f, 0xc412, 0x21, 0 + .dw 0x0311, 0xc412, 0x0311, 0xc412, 0x21, 0 + .dw 0x0313, 0xc412, 0x033f, 0xc412, 0x21, 0 + .dw 0x0341, 0xc412, 0x0341, 0xc412, 0x21, 0 + .dw 0x0343, 0xc412, 0x034f, 0xc412, 0x21, 0 + .dw 0x0351, 0xc412, 0x0351, 0xc412, 0x21, 0 + .dw 0x0353, 0xc412, 0x037f, 0xc412, 0x21, 0 + .dw 0x0381, 0xc412, 0x0381, 0xc412, 0x21, 0 + .dw 0x0383, 0xc412, 0x038f, 0xc412, 0x21, 0 + .dw 0x0391, 0xc412, 0x0391, 0xc412, 0x21, 0 + .dw 0x0393, 0xc412, 0x03bf, 0xc412, 0x21, 0 + .dw 0x03c1, 0xc412, 0x03c1, 0xc412, 0x21, 0 + .dw 0x03c3, 0xc412, 0x03cf, 0xc412, 0x21, 0 + .dw 0x03d1, 0xc412, 0x03d1, 0xc412, 0x21, 0 + .dw 0x03d3, 0xc412, 0x03ff, 0xc412, 0x21, 0 + .dw 0x0401, 0xc412, 0x0401, 0xc412, 0x21, 0 + .dw 0x0403, 0xc412, 0x040f, 0xc412, 0x21, 0 + .dw 0x0411, 0xc412, 0x0411, 0xc412, 0x21, 0 + .dw 0x0413, 0xc412, 0x043f, 0xc412, 0x21, 0 + .dw 0x0441, 0xc412, 0x0441, 0xc412, 0x21, 0 + .dw 0x0443, 0xc412, 0x044f, 0xc412, 0x21, 0 + .dw 0x0451, 0xc412, 0x0451, 0xc412, 0x21, 0 + .dw 0x0453, 0xc412, 0x047f, 0xc412, 0x21, 0 + .dw 0x0481, 0xc412, 0x0481, 0xc412, 0x21, 0 + .dw 0x0483, 0xc412, 0x048f, 0xc412, 0x21, 0 + .dw 0x0491, 0xc412, 0x0491, 0xc412, 0x21, 0 + .dw 0x0493, 0xc412, 0x04bf, 0xc412, 0x21, 0 + .dw 0x04c1, 0xc412, 0x04c1, 0xc412, 0x21, 0 + .dw 0x04c3, 0xc412, 0x04cf, 0xc412, 0x21, 0 + .dw 0x04d1, 0xc412, 0x04d1, 0xc412, 0x21, 0 + .dw 0x04d3, 0xc412, 0x04ff, 0xc412, 0x21, 0 + .dw 0x0501, 0xc412, 0x0501, 0xc412, 0x21, 0 + .dw 0x0503, 0xc412, 0x050f, 0xc412, 0x21, 0 + .dw 0x0511, 0xc412, 0x0511, 0xc412, 0x21, 0 + .dw 0x0513, 0xc412, 0x053f, 0xc412, 0x21, 0 + .dw 0x0541, 0xc412, 0x0541, 0xc412, 0x21, 0 + .dw 0x0543, 0xc412, 0x054f, 0xc412, 0x21, 0 + .dw 0x0551, 0xc412, 0x0551, 0xc412, 0x21, 0 + .dw 0x0553, 0xc412, 0x057f, 0xc412, 0x21, 0 + .dw 0x0581, 0xc412, 0x0581, 0xc412, 0x21, 0 + .dw 0x0583, 0xc412, 0x058f, 0xc412, 0x21, 0 + .dw 0x0591, 0xc412, 0x0591, 0xc412, 0x21, 0 + .dw 0x0593, 0xc412, 0x05bf, 0xc412, 0x21, 0 + .dw 0x05c1, 0xc412, 0x05c1, 0xc412, 0x21, 0 + .dw 0x05c3, 0xc412, 0x05cf, 0xc412, 0x21, 0 + .dw 0x05d1, 0xc412, 0x05d1, 0xc412, 0x21, 0 + .dw 0x05d3, 0xc412, 0x05ff, 0xc412, 0x21, 0 + .dw 0x0601, 0xc412, 0x0601, 0xc412, 0x21, 0 + .dw 0x0603, 0xc412, 0x060f, 0xc412, 0x21, 0 + .dw 0x0611, 0xc412, 0x0611, 0xc412, 0x21, 0 + .dw 0x0613, 0xc412, 0x063f, 0xc412, 0x21, 0 + .dw 0x0641, 0xc412, 0x0641, 0xc412, 0x21, 0 + .dw 0x0643, 0xc412, 0x064f, 0xc412, 0x21, 0 + .dw 0x0651, 0xc412, 0x0651, 0xc412, 0x21, 0 + .dw 0x0653, 0xc412, 0x067f, 0xc412, 0x21, 0 + .dw 0x0681, 0xc412, 0x0681, 0xc412, 0x21, 0 + .dw 0x0683, 0xc412, 0x068f, 0xc412, 0x21, 0 + .dw 0x0691, 0xc412, 0x0691, 0xc412, 0x21, 0 + .dw 0x0693, 0xc412, 0x06bf, 0xc412, 0x21, 0 + .dw 0x06c1, 0xc412, 0x06c1, 0xc412, 0x21, 0 + .dw 0x06c3, 0xc412, 0x06cf, 0xc412, 0x21, 0 + .dw 0x06d1, 0xc412, 0x06d1, 0xc412, 0x21, 0 + .dw 0x06d3, 0xc412, 0x06ff, 0xc412, 0x21, 0 + .dw 0x0701, 0xc412, 0x0701, 0xc412, 0x21, 0 + .dw 0x0703, 0xc412, 0x070f, 0xc412, 0x21, 0 + .dw 0x0711, 0xc412, 0x0711, 0xc412, 0x21, 0 + .dw 0x0713, 0xc412, 0x073f, 0xc412, 0x21, 0 + .dw 0x0741, 0xc412, 0x0741, 0xc412, 0x21, 0 + .dw 0x0743, 0xc412, 0x074f, 0xc412, 0x21, 0 + .dw 0x0751, 0xc412, 0x0751, 0xc412, 0x21, 0 + .dw 0x0753, 0xc412, 0x077f, 0xc412, 0x21, 0 + .dw 0x0781, 0xc412, 0x0781, 0xc412, 0x21, 0 + .dw 0x0783, 0xc412, 0x078f, 0xc412, 0x21, 0 + .dw 0x0791, 0xc412, 0x0791, 0xc412, 0x21, 0 + .dw 0x0793, 0xc412, 0x07bf, 0xc412, 0x21, 0 + .dw 0x07c1, 0xc412, 0x07c1, 0xc412, 0x21, 0 + .dw 0x07c3, 0xc412, 0x07cf, 0xc412, 0x21, 0 + .dw 0x07d1, 0xc412, 0x07d1, 0xc412, 0x21, 0 + .dw 0x07d3, 0xc412, 0x07ff, 0xc412, 0x21, 0 + .dw 0x0801, 0xc412, 0x0801, 0xc412, 0x21, 0 + .dw 0x0803, 0xc412, 0x080f, 0xc412, 0x21, 0 + .dw 0x0811, 0xc412, 0x0811, 0xc412, 0x21, 0 + .dw 0x0813, 0xc412, 0x083f, 0xc412, 0x21, 0 + .dw 0x0841, 0xc412, 0x0841, 0xc412, 0x21, 0 + .dw 0x0843, 0xc412, 0x084f, 0xc412, 0x21, 0 + .dw 0x0851, 0xc412, 0x0851, 0xc412, 0x21, 0 + .dw 0x0853, 0xc412, 0x087f, 0xc412, 0x21, 0 + .dw 0x0881, 0xc412, 0x0881, 0xc412, 0x21, 0 + .dw 0x0883, 0xc412, 0x088f, 0xc412, 0x21, 0 + .dw 0x0891, 0xc412, 0x0891, 0xc412, 0x21, 0 + .dw 0x0893, 0xc412, 0x08bf, 0xc412, 0x21, 0 + .dw 0x08c1, 0xc412, 0x08c1, 0xc412, 0x21, 0 + .dw 0x08c3, 0xc412, 0x08cf, 0xc412, 0x21, 0 + .dw 0x08d1, 0xc412, 0x08d1, 0xc412, 0x21, 0 + .dw 0x08d3, 0xc412, 0x08ff, 0xc412, 0x21, 0 + .dw 0x0901, 0xc412, 0x0901, 0xc412, 0x21, 0 + .dw 0x0903, 0xc412, 0x090f, 0xc412, 0x21, 0 + .dw 0x0911, 0xc412, 0x0911, 0xc412, 0x21, 0 + .dw 0x0913, 0xc412, 0x093f, 0xc412, 0x21, 0 + .dw 0x0941, 0xc412, 0x0941, 0xc412, 0x21, 0 + .dw 0x0943, 0xc412, 0x094f, 0xc412, 0x21, 0 + .dw 0x0951, 0xc412, 0x0951, 0xc412, 0x21, 0 + .dw 0x0953, 0xc412, 0x097f, 0xc412, 0x21, 0 + .dw 0x0981, 0xc412, 0x0981, 0xc412, 0x21, 0 + .dw 0x0983, 0xc412, 0x098f, 0xc412, 0x21, 0 + .dw 0x0991, 0xc412, 0x0991, 0xc412, 0x21, 0 + .dw 0x0993, 0xc412, 0x09bf, 0xc412, 0x21, 0 + .dw 0x09c1, 0xc412, 0x09c1, 0xc412, 0x21, 0 + .dw 0x09c3, 0xc412, 0x09cf, 0xc412, 0x21, 0 + .dw 0x09d1, 0xc412, 0x09d1, 0xc412, 0x21, 0 + .dw 0x09d3, 0xc412, 0x09ff, 0xc412, 0x21, 0 + .dw 0x0a01, 0xc412, 0x0a01, 0xc412, 0x21, 0 + .dw 0x0a03, 0xc412, 0x0a0f, 0xc412, 0x21, 0 + .dw 0x0a11, 0xc412, 0x0a11, 0xc412, 0x21, 0 + .dw 0x0a13, 0xc412, 0x0a3f, 0xc412, 0x21, 0 + .dw 0x0a41, 0xc412, 0x0a41, 0xc412, 0x21, 0 + .dw 0x0a43, 0xc412, 0x0a4f, 0xc412, 0x21, 0 + .dw 0x0a51, 0xc412, 0x0a51, 0xc412, 0x21, 0 + .dw 0x0a53, 0xc412, 0x0a7f, 0xc412, 0x21, 0 + .dw 0x0a81, 0xc412, 0x0a81, 0xc412, 0x21, 0 + .dw 0x0a83, 0xc412, 0x0a8f, 0xc412, 0x21, 0 + .dw 0x0a91, 0xc412, 0x0a91, 0xc412, 0x21, 0 + .dw 0x0a93, 0xc412, 0x0abf, 0xc412, 0x21, 0 + .dw 0x0ac1, 0xc412, 0x0ac1, 0xc412, 0x21, 0 + .dw 0x0ac3, 0xc412, 0x0acf, 0xc412, 0x21, 0 + .dw 0x0ad1, 0xc412, 0x0ad1, 0xc412, 0x21, 0 + .dw 0x0ad3, 0xc412, 0x0aff, 0xc412, 0x21, 0 + .dw 0x0b01, 0xc412, 0x0b01, 0xc412, 0x21, 0 + .dw 0x0b03, 0xc412, 0x0b0f, 0xc412, 0x21, 0 + .dw 0x0b11, 0xc412, 0x0b11, 0xc412, 0x21, 0 + .dw 0x0b13, 0xc412, 0x0b3f, 0xc412, 0x21, 0 + .dw 0x0b41, 0xc412, 0x0b41, 0xc412, 0x21, 0 + .dw 0x0b43, 0xc412, 0x0b4f, 0xc412, 0x21, 0 + .dw 0x0b51, 0xc412, 0x0b51, 0xc412, 0x21, 0 + .dw 0x0b53, 0xc412, 0x0b7f, 0xc412, 0x21, 0 + .dw 0x0b81, 0xc412, 0x0b81, 0xc412, 0x21, 0 + .dw 0x0b83, 0xc412, 0x0b8f, 0xc412, 0x21, 0 + .dw 0x0b91, 0xc412, 0x0b91, 0xc412, 0x21, 0 + .dw 0x0b93, 0xc412, 0x0bbf, 0xc412, 0x21, 0 + .dw 0x0bc1, 0xc412, 0x0bc1, 0xc412, 0x21, 0 + .dw 0x0bc3, 0xc412, 0x0bcf, 0xc412, 0x21, 0 + .dw 0x0bd1, 0xc412, 0x0bd1, 0xc412, 0x21, 0 + .dw 0x0bd3, 0xc412, 0x0bff, 0xc412, 0x21, 0 + .dw 0x0c01, 0xc412, 0x0c01, 0xc412, 0x21, 0 + .dw 0x0c03, 0xc412, 0x0c0f, 0xc412, 0x21, 0 + .dw 0x0c11, 0xc412, 0x0c11, 0xc412, 0x21, 0 + .dw 0x0c13, 0xc412, 0x0c3f, 0xc412, 0x21, 0 + .dw 0x0c41, 0xc412, 0x0c41, 0xc412, 0x21, 0 + .dw 0x0c43, 0xc412, 0x0c4f, 0xc412, 0x21, 0 + .dw 0x0c51, 0xc412, 0x0c51, 0xc412, 0x21, 0 + .dw 0x0c53, 0xc412, 0x0c7f, 0xc412, 0x21, 0 + .dw 0x0c81, 0xc412, 0x0c81, 0xc412, 0x21, 0 + .dw 0x0c83, 0xc412, 0x0c8f, 0xc412, 0x21, 0 + .dw 0x0c91, 0xc412, 0x0c91, 0xc412, 0x21, 0 + .dw 0x0c93, 0xc412, 0x0cbf, 0xc412, 0x21, 0 + .dw 0x0cc1, 0xc412, 0x0cc1, 0xc412, 0x21, 0 + .dw 0x0cc3, 0xc412, 0x0ccf, 0xc412, 0x21, 0 + .dw 0x0cd1, 0xc412, 0x0cd1, 0xc412, 0x21, 0 + .dw 0x0cd3, 0xc412, 0x0cff, 0xc412, 0x21, 0 + .dw 0x0d01, 0xc412, 0x0d01, 0xc412, 0x21, 0 + .dw 0x0d03, 0xc412, 0x0d0f, 0xc412, 0x21, 0 + .dw 0x0d11, 0xc412, 0x0d11, 0xc412, 0x21, 0 + .dw 0x0d13, 0xc412, 0x0d3f, 0xc412, 0x21, 0 + .dw 0x0d41, 0xc412, 0x0d41, 0xc412, 0x21, 0 + .dw 0x0d43, 0xc412, 0x0d4f, 0xc412, 0x21, 0 + .dw 0x0d51, 0xc412, 0x0d51, 0xc412, 0x21, 0 + .dw 0x0d53, 0xc412, 0x0d7f, 0xc412, 0x21, 0 + .dw 0x0d81, 0xc412, 0x0d81, 0xc412, 0x21, 0 + .dw 0x0d83, 0xc412, 0x0d8f, 0xc412, 0x21, 0 + .dw 0x0d91, 0xc412, 0x0d91, 0xc412, 0x21, 0 + .dw 0x0d93, 0xc412, 0x0dbf, 0xc412, 0x21, 0 + .dw 0x0dc1, 0xc412, 0x0dc1, 0xc412, 0x21, 0 + .dw 0x0dc3, 0xc412, 0x0dcf, 0xc412, 0x21, 0 + .dw 0x0dd1, 0xc412, 0x0dd1, 0xc412, 0x21, 0 + .dw 0x0dd3, 0xc412, 0x0dff, 0xc412, 0x21, 0 + .dw 0x0e01, 0xc412, 0x0e01, 0xc412, 0x21, 0 + .dw 0x0e03, 0xc412, 0x0e0f, 0xc412, 0x21, 0 + .dw 0x0e11, 0xc412, 0x0e11, 0xc412, 0x21, 0 + .dw 0x0e13, 0xc412, 0x0e3f, 0xc412, 0x21, 0 + .dw 0x0e41, 0xc412, 0x0e41, 0xc412, 0x21, 0 + .dw 0x0e43, 0xc412, 0x0e4f, 0xc412, 0x21, 0 + .dw 0x0e51, 0xc412, 0x0e51, 0xc412, 0x21, 0 + .dw 0x0e53, 0xc412, 0x0e7f, 0xc412, 0x21, 0 + .dw 0x0e81, 0xc412, 0x0e81, 0xc412, 0x21, 0 + .dw 0x0e83, 0xc412, 0x0e8f, 0xc412, 0x21, 0 + .dw 0x0e91, 0xc412, 0x0e91, 0xc412, 0x21, 0 + .dw 0x0e93, 0xc412, 0x0ebf, 0xc412, 0x21, 0 + .dw 0x0ec1, 0xc412, 0x0ec1, 0xc412, 0x21, 0 + .dw 0x0ec3, 0xc412, 0x0ecf, 0xc412, 0x21, 0 + .dw 0x0ed1, 0xc412, 0x0ed1, 0xc412, 0x21, 0 + .dw 0x0ed3, 0xc412, 0x0eff, 0xc412, 0x21, 0 + .dw 0x0f01, 0xc412, 0x0f01, 0xc412, 0x21, 0 + .dw 0x0f03, 0xc412, 0x0f0f, 0xc412, 0x21, 0 + .dw 0x0f11, 0xc412, 0x0f11, 0xc412, 0x21, 0 + .dw 0x0f13, 0xc412, 0x0f3f, 0xc412, 0x21, 0 + .dw 0x0f41, 0xc412, 0x0f41, 0xc412, 0x21, 0 + .dw 0x0f43, 0xc412, 0x0f4f, 0xc412, 0x21, 0 + .dw 0x0f51, 0xc412, 0x0f51, 0xc412, 0x21, 0 + .dw 0x0f53, 0xc412, 0x0f7f, 0xc412, 0x21, 0 + .dw 0x0f81, 0xc412, 0x0f81, 0xc412, 0x21, 0 + .dw 0x0f83, 0xc412, 0x0f8f, 0xc412, 0x21, 0 + .dw 0x0f91, 0xc412, 0x0f91, 0xc412, 0x21, 0 + .dw 0x0f93, 0xc412, 0x0fbf, 0xc412, 0x21, 0 + .dw 0x0fc1, 0xc412, 0x0fc1, 0xc412, 0x21, 0 + .dw 0x0fc3, 0xc412, 0x0fcf, 0xc412, 0x21, 0 + .dw 0x0fd1, 0xc412, 0x0fd1, 0xc412, 0x21, 0 + .dw 0x0fd3, 0xc412, 0x1fff, 0xc412, 0x21, 0 + .dw 0x2001, 0xc412, 0x2001, 0xc412, 0x21, 0 + .dw 0x2003, 0xc412, 0x200f, 0xc412, 0x21, 0 + .dw 0x2011, 0xc412, 0x2011, 0xc412, 0x21, 0 + .dw 0x2013, 0xc412, 0x203f, 0xc412, 0x21, 0 + .dw 0x2041, 0xc412, 0x2041, 0xc412, 0x21, 0 + .dw 0x2043, 0xc412, 0x204f, 0xc412, 0x21, 0 + .dw 0x2051, 0xc412, 0x2051, 0xc412, 0x21, 0 + .dw 0x2053, 0xc412, 0x207f, 0xc412, 0x21, 0 + .dw 0x2081, 0xc412, 0x2081, 0xc412, 0x21, 0 + .dw 0x2083, 0xc412, 0x208f, 0xc412, 0x21, 0 + .dw 0x2091, 0xc412, 0x2091, 0xc412, 0x21, 0 + .dw 0x2093, 0xc412, 0x20bf, 0xc412, 0x21, 0 + .dw 0x20c1, 0xc412, 0x20c1, 0xc412, 0x21, 0 + .dw 0x20c3, 0xc412, 0x20cf, 0xc412, 0x21, 0 + .dw 0x20d1, 0xc412, 0x20d1, 0xc412, 0x21, 0 + .dw 0x20d3, 0xc412, 0x20ff, 0xc412, 0x21, 0 + .dw 0x2101, 0xc412, 0x2101, 0xc412, 0x21, 0 + .dw 0x2103, 0xc412, 0x210f, 0xc412, 0x21, 0 + .dw 0x2111, 0xc412, 0x2111, 0xc412, 0x21, 0 + .dw 0x2113, 0xc412, 0x213f, 0xc412, 0x21, 0 + .dw 0x2141, 0xc412, 0x2141, 0xc412, 0x21, 0 + .dw 0x2143, 0xc412, 0x214f, 0xc412, 0x21, 0 + .dw 0x2151, 0xc412, 0x2151, 0xc412, 0x21, 0 + .dw 0x2153, 0xc412, 0x217f, 0xc412, 0x21, 0 + .dw 0x2181, 0xc412, 0x2181, 0xc412, 0x21, 0 + .dw 0x2183, 0xc412, 0x218f, 0xc412, 0x21, 0 + .dw 0x2191, 0xc412, 0x2191, 0xc412, 0x21, 0 + .dw 0x2193, 0xc412, 0x21bf, 0xc412, 0x21, 0 + .dw 0x21c1, 0xc412, 0x21c1, 0xc412, 0x21, 0 + .dw 0x21c3, 0xc412, 0x21cf, 0xc412, 0x21, 0 + .dw 0x21d1, 0xc412, 0x21d1, 0xc412, 0x21, 0 + .dw 0x21d3, 0xc412, 0x21ff, 0xc412, 0x21, 0 + .dw 0x2201, 0xc412, 0x2201, 0xc412, 0x21, 0 + .dw 0x2203, 0xc412, 0x220f, 0xc412, 0x21, 0 + .dw 0x2211, 0xc412, 0x2211, 0xc412, 0x21, 0 + .dw 0x2213, 0xc412, 0x223f, 0xc412, 0x21, 0 + .dw 0x2241, 0xc412, 0x2241, 0xc412, 0x21, 0 + .dw 0x2243, 0xc412, 0x224f, 0xc412, 0x21, 0 + .dw 0x2251, 0xc412, 0x2251, 0xc412, 0x21, 0 + .dw 0x2253, 0xc412, 0x227f, 0xc412, 0x21, 0 + .dw 0x2281, 0xc412, 0x2281, 0xc412, 0x21, 0 + .dw 0x2283, 0xc412, 0x228f, 0xc412, 0x21, 0 + .dw 0x2291, 0xc412, 0x2291, 0xc412, 0x21, 0 + .dw 0x2293, 0xc412, 0x22bf, 0xc412, 0x21, 0 + .dw 0x22c1, 0xc412, 0x22c1, 0xc412, 0x21, 0 + .dw 0x22c3, 0xc412, 0x22cf, 0xc412, 0x21, 0 + .dw 0x22d1, 0xc412, 0x22d1, 0xc412, 0x21, 0 + .dw 0x22d3, 0xc412, 0x22ff, 0xc412, 0x21, 0 + .dw 0x2301, 0xc412, 0x2301, 0xc412, 0x21, 0 + .dw 0x2303, 0xc412, 0x230f, 0xc412, 0x21, 0 + .dw 0x2311, 0xc412, 0x2311, 0xc412, 0x21, 0 + .dw 0x2313, 0xc412, 0x233f, 0xc412, 0x21, 0 + .dw 0x2341, 0xc412, 0x2341, 0xc412, 0x21, 0 + .dw 0x2343, 0xc412, 0x234f, 0xc412, 0x21, 0 + .dw 0x2351, 0xc412, 0x2351, 0xc412, 0x21, 0 + .dw 0x2353, 0xc412, 0x237f, 0xc412, 0x21, 0 + .dw 0x2381, 0xc412, 0x2381, 0xc412, 0x21, 0 + .dw 0x2383, 0xc412, 0x238f, 0xc412, 0x21, 0 + .dw 0x2391, 0xc412, 0x2391, 0xc412, 0x21, 0 + .dw 0x2393, 0xc412, 0x23bf, 0xc412, 0x21, 0 + .dw 0x23c1, 0xc412, 0x23c1, 0xc412, 0x21, 0 + .dw 0x23c3, 0xc412, 0x23cf, 0xc412, 0x21, 0 + .dw 0x23d1, 0xc412, 0x23d1, 0xc412, 0x21, 0 + .dw 0x23d3, 0xc412, 0x23ff, 0xc412, 0x21, 0 + .dw 0x2401, 0xc412, 0x2401, 0xc412, 0x21, 0 + .dw 0x2403, 0xc412, 0x240f, 0xc412, 0x21, 0 + .dw 0x2411, 0xc412, 0x2411, 0xc412, 0x21, 0 + .dw 0x2413, 0xc412, 0x243f, 0xc412, 0x21, 0 + .dw 0x2441, 0xc412, 0x2441, 0xc412, 0x21, 0 + .dw 0x2443, 0xc412, 0x244f, 0xc412, 0x21, 0 + .dw 0x2451, 0xc412, 0x2451, 0xc412, 0x21, 0 + .dw 0x2453, 0xc412, 0x247f, 0xc412, 0x21, 0 + .dw 0x2481, 0xc412, 0x2481, 0xc412, 0x21, 0 + .dw 0x2483, 0xc412, 0x248f, 0xc412, 0x21, 0 + .dw 0x2491, 0xc412, 0x2491, 0xc412, 0x21, 0 + .dw 0x2493, 0xc412, 0x24bf, 0xc412, 0x21, 0 + .dw 0x24c1, 0xc412, 0x24c1, 0xc412, 0x21, 0 + .dw 0x24c3, 0xc412, 0x24cf, 0xc412, 0x21, 0 + .dw 0x24d1, 0xc412, 0x24d1, 0xc412, 0x21, 0 + .dw 0x24d3, 0xc412, 0x24ff, 0xc412, 0x21, 0 + .dw 0x2501, 0xc412, 0x2501, 0xc412, 0x21, 0 + .dw 0x2503, 0xc412, 0x250f, 0xc412, 0x21, 0 + .dw 0x2511, 0xc412, 0x2511, 0xc412, 0x21, 0 + .dw 0x2513, 0xc412, 0x253f, 0xc412, 0x21, 0 + .dw 0x2541, 0xc412, 0x2541, 0xc412, 0x21, 0 + .dw 0x2543, 0xc412, 0x254f, 0xc412, 0x21, 0 + .dw 0x2551, 0xc412, 0x2551, 0xc412, 0x21, 0 + .dw 0x2553, 0xc412, 0x257f, 0xc412, 0x21, 0 + .dw 0x2581, 0xc412, 0x2581, 0xc412, 0x21, 0 + .dw 0x2583, 0xc412, 0x258f, 0xc412, 0x21, 0 + .dw 0x2591, 0xc412, 0x2591, 0xc412, 0x21, 0 + .dw 0x2593, 0xc412, 0x25bf, 0xc412, 0x21, 0 + .dw 0x25c1, 0xc412, 0x25c1, 0xc412, 0x21, 0 + .dw 0x25c3, 0xc412, 0x25cf, 0xc412, 0x21, 0 + .dw 0x25d1, 0xc412, 0x25d1, 0xc412, 0x21, 0 + .dw 0x25d3, 0xc412, 0x25ff, 0xc412, 0x21, 0 + .dw 0x2601, 0xc412, 0x2601, 0xc412, 0x21, 0 + .dw 0x2603, 0xc412, 0x260f, 0xc412, 0x21, 0 + .dw 0x2611, 0xc412, 0x2611, 0xc412, 0x21, 0 + .dw 0x2613, 0xc412, 0x263f, 0xc412, 0x21, 0 + .dw 0x2641, 0xc412, 0x2641, 0xc412, 0x21, 0 + .dw 0x2643, 0xc412, 0x264f, 0xc412, 0x21, 0 + .dw 0x2651, 0xc412, 0x2651, 0xc412, 0x21, 0 + .dw 0x2653, 0xc412, 0x267f, 0xc412, 0x21, 0 + .dw 0x2681, 0xc412, 0x2681, 0xc412, 0x21, 0 + .dw 0x2683, 0xc412, 0x268f, 0xc412, 0x21, 0 + .dw 0x2691, 0xc412, 0x2691, 0xc412, 0x21, 0 + .dw 0x2693, 0xc412, 0x26bf, 0xc412, 0x21, 0 + .dw 0x26c1, 0xc412, 0x26c1, 0xc412, 0x21, 0 + .dw 0x26c3, 0xc412, 0x26cf, 0xc412, 0x21, 0 + .dw 0x26d1, 0xc412, 0x26d1, 0xc412, 0x21, 0 + .dw 0x26d3, 0xc412, 0x26ff, 0xc412, 0x21, 0 + .dw 0x2701, 0xc412, 0x2701, 0xc412, 0x21, 0 + .dw 0x2703, 0xc412, 0x270f, 0xc412, 0x21, 0 + .dw 0x2711, 0xc412, 0x2711, 0xc412, 0x21, 0 + .dw 0x2713, 0xc412, 0x273f, 0xc412, 0x21, 0 + .dw 0x2741, 0xc412, 0x2741, 0xc412, 0x21, 0 + .dw 0x2743, 0xc412, 0x274f, 0xc412, 0x21, 0 + .dw 0x2751, 0xc412, 0x2751, 0xc412, 0x21, 0 + .dw 0x2753, 0xc412, 0x277f, 0xc412, 0x21, 0 + .dw 0x2781, 0xc412, 0x2781, 0xc412, 0x21, 0 + .dw 0x2783, 0xc412, 0x278f, 0xc412, 0x21, 0 + .dw 0x2791, 0xc412, 0x2791, 0xc412, 0x21, 0 + .dw 0x2793, 0xc412, 0x27bf, 0xc412, 0x21, 0 + .dw 0x27c1, 0xc412, 0x27c1, 0xc412, 0x21, 0 + .dw 0x27c3, 0xc412, 0x27cf, 0xc412, 0x21, 0 + .dw 0x27d1, 0xc412, 0x27d1, 0xc412, 0x21, 0 + .dw 0x27d3, 0xc412, 0x27ff, 0xc412, 0x21, 0 + .dw 0x2801, 0xc412, 0x2801, 0xc412, 0x21, 0 + .dw 0x2803, 0xc412, 0x280f, 0xc412, 0x21, 0 + .dw 0x2811, 0xc412, 0x2811, 0xc412, 0x21, 0 + .dw 0x2813, 0xc412, 0x283f, 0xc412, 0x21, 0 + .dw 0x2841, 0xc412, 0x2841, 0xc412, 0x21, 0 + .dw 0x2843, 0xc412, 0x284f, 0xc412, 0x21, 0 + .dw 0x2851, 0xc412, 0x2851, 0xc412, 0x21, 0 + .dw 0x2853, 0xc412, 0x287f, 0xc412, 0x21, 0 + .dw 0x2881, 0xc412, 0x2881, 0xc412, 0x21, 0 + .dw 0x2883, 0xc412, 0x288f, 0xc412, 0x21, 0 + .dw 0x2891, 0xc412, 0x2891, 0xc412, 0x21, 0 + .dw 0x2893, 0xc412, 0x28bf, 0xc412, 0x21, 0 + .dw 0x28c1, 0xc412, 0x28c1, 0xc412, 0x21, 0 + .dw 0x28c3, 0xc412, 0x28cf, 0xc412, 0x21, 0 + .dw 0x28d1, 0xc412, 0x28d1, 0xc412, 0x21, 0 + .dw 0x28d3, 0xc412, 0x28ff, 0xc412, 0x21, 0 + .dw 0x2901, 0xc412, 0x2901, 0xc412, 0x21, 0 + .dw 0x2903, 0xc412, 0x290f, 0xc412, 0x21, 0 + .dw 0x2911, 0xc412, 0x2911, 0xc412, 0x21, 0 + .dw 0x2913, 0xc412, 0x293f, 0xc412, 0x21, 0 + .dw 0x2941, 0xc412, 0x2941, 0xc412, 0x21, 0 + .dw 0x2943, 0xc412, 0x294f, 0xc412, 0x21, 0 + .dw 0x2951, 0xc412, 0x2951, 0xc412, 0x21, 0 + .dw 0x2953, 0xc412, 0x297f, 0xc412, 0x21, 0 + .dw 0x2981, 0xc412, 0x2981, 0xc412, 0x21, 0 + .dw 0x2983, 0xc412, 0x298f, 0xc412, 0x21, 0 + .dw 0x2991, 0xc412, 0x2991, 0xc412, 0x21, 0 + .dw 0x2993, 0xc412, 0x29bf, 0xc412, 0x21, 0 + .dw 0x29c1, 0xc412, 0x29c1, 0xc412, 0x21, 0 + .dw 0x29c3, 0xc412, 0x29cf, 0xc412, 0x21, 0 + .dw 0x29d1, 0xc412, 0x29d1, 0xc412, 0x21, 0 + .dw 0x29d3, 0xc412, 0x29ff, 0xc412, 0x21, 0 + .dw 0x2a01, 0xc412, 0x2a01, 0xc412, 0x21, 0 + .dw 0x2a03, 0xc412, 0x2a0f, 0xc412, 0x21, 0 + .dw 0x2a11, 0xc412, 0x2a11, 0xc412, 0x21, 0 + .dw 0x2a13, 0xc412, 0x2a3f, 0xc412, 0x21, 0 + .dw 0x2a41, 0xc412, 0x2a41, 0xc412, 0x21, 0 + .dw 0x2a43, 0xc412, 0x2a4f, 0xc412, 0x21, 0 + .dw 0x2a51, 0xc412, 0x2a51, 0xc412, 0x21, 0 + .dw 0x2a53, 0xc412, 0x2a7f, 0xc412, 0x21, 0 + .dw 0x2a81, 0xc412, 0x2a81, 0xc412, 0x21, 0 + .dw 0x2a83, 0xc412, 0x2a8f, 0xc412, 0x21, 0 + .dw 0x2a91, 0xc412, 0x2a91, 0xc412, 0x21, 0 + .dw 0x2a93, 0xc412, 0x2abf, 0xc412, 0x21, 0 + .dw 0x2ac1, 0xc412, 0x2ac1, 0xc412, 0x21, 0 + .dw 0x2ac3, 0xc412, 0x2acf, 0xc412, 0x21, 0 + .dw 0x2ad1, 0xc412, 0x2ad1, 0xc412, 0x21, 0 + .dw 0x2ad3, 0xc412, 0x2aff, 0xc412, 0x21, 0 + .dw 0x2b01, 0xc412, 0x2b01, 0xc412, 0x21, 0 + .dw 0x2b03, 0xc412, 0x2b0f, 0xc412, 0x21, 0 + .dw 0x2b11, 0xc412, 0x2b11, 0xc412, 0x21, 0 + .dw 0x2b13, 0xc412, 0x2b3f, 0xc412, 0x21, 0 + .dw 0x2b41, 0xc412, 0x2b41, 0xc412, 0x21, 0 + .dw 0x2b43, 0xc412, 0x2b4f, 0xc412, 0x21, 0 + .dw 0x2b51, 0xc412, 0x2b51, 0xc412, 0x21, 0 + .dw 0x2b53, 0xc412, 0x2b7f, 0xc412, 0x21, 0 + .dw 0x2b81, 0xc412, 0x2b81, 0xc412, 0x21, 0 + .dw 0x2b83, 0xc412, 0x2b8f, 0xc412, 0x21, 0 + .dw 0x2b91, 0xc412, 0x2b91, 0xc412, 0x21, 0 + .dw 0x2b93, 0xc412, 0x2bbf, 0xc412, 0x21, 0 + .dw 0x2bc1, 0xc412, 0x2bc1, 0xc412, 0x21, 0 + .dw 0x2bc3, 0xc412, 0x2bcf, 0xc412, 0x21, 0 + .dw 0x2bd1, 0xc412, 0x2bd1, 0xc412, 0x21, 0 + .dw 0x2bd3, 0xc412, 0x2bff, 0xc412, 0x21, 0 + .dw 0x2c01, 0xc412, 0x2c01, 0xc412, 0x21, 0 + .dw 0x2c03, 0xc412, 0x2c0f, 0xc412, 0x21, 0 + .dw 0x2c11, 0xc412, 0x2c11, 0xc412, 0x21, 0 + .dw 0x2c13, 0xc412, 0x2c3f, 0xc412, 0x21, 0 + .dw 0x2c41, 0xc412, 0x2c41, 0xc412, 0x21, 0 + .dw 0x2c43, 0xc412, 0x2c4f, 0xc412, 0x21, 0 + .dw 0x2c51, 0xc412, 0x2c51, 0xc412, 0x21, 0 + .dw 0x2c53, 0xc412, 0x2c7f, 0xc412, 0x21, 0 + .dw 0x2c81, 0xc412, 0x2c81, 0xc412, 0x21, 0 + .dw 0x2c83, 0xc412, 0x2c8f, 0xc412, 0x21, 0 + .dw 0x2c91, 0xc412, 0x2c91, 0xc412, 0x21, 0 + .dw 0x2c93, 0xc412, 0x2cbf, 0xc412, 0x21, 0 + .dw 0x2cc1, 0xc412, 0x2cc1, 0xc412, 0x21, 0 + .dw 0x2cc3, 0xc412, 0x2ccf, 0xc412, 0x21, 0 + .dw 0x2cd1, 0xc412, 0x2cd1, 0xc412, 0x21, 0 + .dw 0x2cd3, 0xc412, 0x2cff, 0xc412, 0x21, 0 + .dw 0x2d01, 0xc412, 0x2d01, 0xc412, 0x21, 0 + .dw 0x2d03, 0xc412, 0x2d0f, 0xc412, 0x21, 0 + .dw 0x2d11, 0xc412, 0x2d11, 0xc412, 0x21, 0 + .dw 0x2d13, 0xc412, 0x2d3f, 0xc412, 0x21, 0 + .dw 0x2d41, 0xc412, 0x2d41, 0xc412, 0x21, 0 + .dw 0x2d43, 0xc412, 0x2d4f, 0xc412, 0x21, 0 + .dw 0x2d51, 0xc412, 0x2d51, 0xc412, 0x21, 0 + .dw 0x2d53, 0xc412, 0x2d7f, 0xc412, 0x21, 0 + .dw 0x2d81, 0xc412, 0x2d81, 0xc412, 0x21, 0 + .dw 0x2d83, 0xc412, 0x2d8f, 0xc412, 0x21, 0 + .dw 0x2d91, 0xc412, 0x2d91, 0xc412, 0x21, 0 + .dw 0x2d93, 0xc412, 0x2dbf, 0xc412, 0x21, 0 + .dw 0x2dc1, 0xc412, 0x2dc1, 0xc412, 0x21, 0 + .dw 0x2dc3, 0xc412, 0x2dcf, 0xc412, 0x21, 0 + .dw 0x2dd1, 0xc412, 0x2dd1, 0xc412, 0x21, 0 + .dw 0x2dd3, 0xc412, 0x2dff, 0xc412, 0x21, 0 + .dw 0x2e01, 0xc412, 0x2e01, 0xc412, 0x21, 0 + .dw 0x2e03, 0xc412, 0x2e0f, 0xc412, 0x21, 0 + .dw 0x2e11, 0xc412, 0x2e11, 0xc412, 0x21, 0 + .dw 0x2e13, 0xc412, 0x2e3f, 0xc412, 0x21, 0 + .dw 0x2e41, 0xc412, 0x2e41, 0xc412, 0x21, 0 + .dw 0x2e43, 0xc412, 0x2e4f, 0xc412, 0x21, 0 + .dw 0x2e51, 0xc412, 0x2e51, 0xc412, 0x21, 0 + .dw 0x2e53, 0xc412, 0x2e7f, 0xc412, 0x21, 0 + .dw 0x2e81, 0xc412, 0x2e81, 0xc412, 0x21, 0 + .dw 0x2e83, 0xc412, 0x2e8f, 0xc412, 0x21, 0 + .dw 0x2e91, 0xc412, 0x2e91, 0xc412, 0x21, 0 + .dw 0x2e93, 0xc412, 0x2ebf, 0xc412, 0x21, 0 + .dw 0x2ec1, 0xc412, 0x2ec1, 0xc412, 0x21, 0 + .dw 0x2ec3, 0xc412, 0x2ecf, 0xc412, 0x21, 0 + .dw 0x2ed1, 0xc412, 0x2ed1, 0xc412, 0x21, 0 + .dw 0x2ed3, 0xc412, 0x2eff, 0xc412, 0x21, 0 + .dw 0x2f01, 0xc412, 0x2f01, 0xc412, 0x21, 0 + .dw 0x2f03, 0xc412, 0x2f0f, 0xc412, 0x21, 0 + .dw 0x2f11, 0xc412, 0x2f11, 0xc412, 0x21, 0 + .dw 0x2f13, 0xc412, 0x2f3f, 0xc412, 0x21, 0 + .dw 0x2f41, 0xc412, 0x2f41, 0xc412, 0x21, 0 + .dw 0x2f43, 0xc412, 0x2f4f, 0xc412, 0x21, 0 + .dw 0x2f51, 0xc412, 0x2f51, 0xc412, 0x21, 0 + .dw 0x2f53, 0xc412, 0x2f7f, 0xc412, 0x21, 0 + .dw 0x2f81, 0xc412, 0x2f81, 0xc412, 0x21, 0 + .dw 0x2f83, 0xc412, 0x2f8f, 0xc412, 0x21, 0 + .dw 0x2f91, 0xc412, 0x2f91, 0xc412, 0x21, 0 + .dw 0x2f93, 0xc412, 0x2fbf, 0xc412, 0x21, 0 + .dw 0x2fc1, 0xc412, 0x2fc1, 0xc412, 0x21, 0 + .dw 0x2fc3, 0xc412, 0x2fcf, 0xc412, 0x21, 0 + .dw 0x2fd1, 0xc412, 0x2fd1, 0xc412, 0x21, 0 + .dw 0x2fd3, 0xc412, 0xbfff, 0xc412, 0x21, 0 + .dw 0xd000, 0xc412, 0xffff, 0xc413, 0x21, 0 + .dw 0x0001, 0xc414, 0x0001, 0xc414, 0x21, 0 + .dw 0x0003, 0xc414, 0x000f, 0xc414, 0x21, 0 + .dw 0x0011, 0xc414, 0x0011, 0xc414, 0x21, 0 + .dw 0x0013, 0xc414, 0x003f, 0xc414, 0x21, 0 + .dw 0x0041, 0xc414, 0x0041, 0xc414, 0x21, 0 + .dw 0x0043, 0xc414, 0x004f, 0xc414, 0x21, 0 + .dw 0x0051, 0xc414, 0x0051, 0xc414, 0x21, 0 + .dw 0x0053, 0xc414, 0x007f, 0xc414, 0x21, 0 + .dw 0x0081, 0xc414, 0x0081, 0xc414, 0x21, 0 + .dw 0x0083, 0xc414, 0x008f, 0xc414, 0x21, 0 + .dw 0x0091, 0xc414, 0x0091, 0xc414, 0x21, 0 + .dw 0x0093, 0xc414, 0x00bf, 0xc414, 0x21, 0 + .dw 0x00c1, 0xc414, 0x00c1, 0xc414, 0x21, 0 + .dw 0x00c3, 0xc414, 0x00cf, 0xc414, 0x21, 0 + .dw 0x00d1, 0xc414, 0x00d1, 0xc414, 0x21, 0 + .dw 0x00d3, 0xc414, 0x00ff, 0xc414, 0x21, 0 + .dw 0x0101, 0xc414, 0x0101, 0xc414, 0x21, 0 + .dw 0x0103, 0xc414, 0x010f, 0xc414, 0x21, 0 + .dw 0x0111, 0xc414, 0x0111, 0xc414, 0x21, 0 + .dw 0x0113, 0xc414, 0x013f, 0xc414, 0x21, 0 + .dw 0x0141, 0xc414, 0x0141, 0xc414, 0x21, 0 + .dw 0x0143, 0xc414, 0x014f, 0xc414, 0x21, 0 + .dw 0x0151, 0xc414, 0x0151, 0xc414, 0x21, 0 + .dw 0x0153, 0xc414, 0x017f, 0xc414, 0x21, 0 + .dw 0x0181, 0xc414, 0x0181, 0xc414, 0x21, 0 + .dw 0x0183, 0xc414, 0x018f, 0xc414, 0x21, 0 + .dw 0x0191, 0xc414, 0x0191, 0xc414, 0x21, 0 + .dw 0x0193, 0xc414, 0x01bf, 0xc414, 0x21, 0 + .dw 0x01c1, 0xc414, 0x01c1, 0xc414, 0x21, 0 + .dw 0x01c3, 0xc414, 0x01cf, 0xc414, 0x21, 0 + .dw 0x01d1, 0xc414, 0x01d1, 0xc414, 0x21, 0 + .dw 0x01d3, 0xc414, 0x01ff, 0xc414, 0x21, 0 + .dw 0x0201, 0xc414, 0x0201, 0xc414, 0x21, 0 + .dw 0x0203, 0xc414, 0x020f, 0xc414, 0x21, 0 + .dw 0x0211, 0xc414, 0x0211, 0xc414, 0x21, 0 + .dw 0x0213, 0xc414, 0x023f, 0xc414, 0x21, 0 + .dw 0x0241, 0xc414, 0x0241, 0xc414, 0x21, 0 + .dw 0x0243, 0xc414, 0x024f, 0xc414, 0x21, 0 + .dw 0x0251, 0xc414, 0x0251, 0xc414, 0x21, 0 + .dw 0x0253, 0xc414, 0x027f, 0xc414, 0x21, 0 + .dw 0x0281, 0xc414, 0x0281, 0xc414, 0x21, 0 + .dw 0x0283, 0xc414, 0x028f, 0xc414, 0x21, 0 + .dw 0x0291, 0xc414, 0x0291, 0xc414, 0x21, 0 + .dw 0x0293, 0xc414, 0x02bf, 0xc414, 0x21, 0 + .dw 0x02c1, 0xc414, 0x02c1, 0xc414, 0x21, 0 + .dw 0x02c3, 0xc414, 0x02cf, 0xc414, 0x21, 0 + .dw 0x02d1, 0xc414, 0x02d1, 0xc414, 0x21, 0 + .dw 0x02d3, 0xc414, 0x02ff, 0xc414, 0x21, 0 + .dw 0x0301, 0xc414, 0x0301, 0xc414, 0x21, 0 + .dw 0x0303, 0xc414, 0x030f, 0xc414, 0x21, 0 + .dw 0x0311, 0xc414, 0x0311, 0xc414, 0x21, 0 + .dw 0x0313, 0xc414, 0x033f, 0xc414, 0x21, 0 + .dw 0x0341, 0xc414, 0x0341, 0xc414, 0x21, 0 + .dw 0x0343, 0xc414, 0x034f, 0xc414, 0x21, 0 + .dw 0x0351, 0xc414, 0x0351, 0xc414, 0x21, 0 + .dw 0x0353, 0xc414, 0x037f, 0xc414, 0x21, 0 + .dw 0x0381, 0xc414, 0x0381, 0xc414, 0x21, 0 + .dw 0x0383, 0xc414, 0x038f, 0xc414, 0x21, 0 + .dw 0x0391, 0xc414, 0x0391, 0xc414, 0x21, 0 + .dw 0x0393, 0xc414, 0x03bf, 0xc414, 0x21, 0 + .dw 0x03c1, 0xc414, 0x03c1, 0xc414, 0x21, 0 + .dw 0x03c3, 0xc414, 0x03cf, 0xc414, 0x21, 0 + .dw 0x03d1, 0xc414, 0x03d1, 0xc414, 0x21, 0 + .dw 0x03d3, 0xc414, 0x03ff, 0xc414, 0x21, 0 + .dw 0x0401, 0xc414, 0x0401, 0xc414, 0x21, 0 + .dw 0x0403, 0xc414, 0x040f, 0xc414, 0x21, 0 + .dw 0x0411, 0xc414, 0x0411, 0xc414, 0x21, 0 + .dw 0x0413, 0xc414, 0x043f, 0xc414, 0x21, 0 + .dw 0x0441, 0xc414, 0x0441, 0xc414, 0x21, 0 + .dw 0x0443, 0xc414, 0x044f, 0xc414, 0x21, 0 + .dw 0x0451, 0xc414, 0x0451, 0xc414, 0x21, 0 + .dw 0x0453, 0xc414, 0x047f, 0xc414, 0x21, 0 + .dw 0x0481, 0xc414, 0x0481, 0xc414, 0x21, 0 + .dw 0x0483, 0xc414, 0x048f, 0xc414, 0x21, 0 + .dw 0x0491, 0xc414, 0x0491, 0xc414, 0x21, 0 + .dw 0x0493, 0xc414, 0x04bf, 0xc414, 0x21, 0 + .dw 0x04c1, 0xc414, 0x04c1, 0xc414, 0x21, 0 + .dw 0x04c3, 0xc414, 0x04cf, 0xc414, 0x21, 0 + .dw 0x04d1, 0xc414, 0x04d1, 0xc414, 0x21, 0 + .dw 0x04d3, 0xc414, 0x04ff, 0xc414, 0x21, 0 + .dw 0x0501, 0xc414, 0x0501, 0xc414, 0x21, 0 + .dw 0x0503, 0xc414, 0x050f, 0xc414, 0x21, 0 + .dw 0x0511, 0xc414, 0x0511, 0xc414, 0x21, 0 + .dw 0x0513, 0xc414, 0x053f, 0xc414, 0x21, 0 + .dw 0x0541, 0xc414, 0x0541, 0xc414, 0x21, 0 + .dw 0x0543, 0xc414, 0x054f, 0xc414, 0x21, 0 + .dw 0x0551, 0xc414, 0x0551, 0xc414, 0x21, 0 + .dw 0x0553, 0xc414, 0x057f, 0xc414, 0x21, 0 + .dw 0x0581, 0xc414, 0x0581, 0xc414, 0x21, 0 + .dw 0x0583, 0xc414, 0x058f, 0xc414, 0x21, 0 + .dw 0x0591, 0xc414, 0x0591, 0xc414, 0x21, 0 + .dw 0x0593, 0xc414, 0x05bf, 0xc414, 0x21, 0 + .dw 0x05c1, 0xc414, 0x05c1, 0xc414, 0x21, 0 + .dw 0x05c3, 0xc414, 0x05cf, 0xc414, 0x21, 0 + .dw 0x05d1, 0xc414, 0x05d1, 0xc414, 0x21, 0 + .dw 0x05d3, 0xc414, 0x05ff, 0xc414, 0x21, 0 + .dw 0x0601, 0xc414, 0x0601, 0xc414, 0x21, 0 + .dw 0x0603, 0xc414, 0x060f, 0xc414, 0x21, 0 + .dw 0x0611, 0xc414, 0x0611, 0xc414, 0x21, 0 + .dw 0x0613, 0xc414, 0x063f, 0xc414, 0x21, 0 + .dw 0x0641, 0xc414, 0x0641, 0xc414, 0x21, 0 + .dw 0x0643, 0xc414, 0x064f, 0xc414, 0x21, 0 + .dw 0x0651, 0xc414, 0x0651, 0xc414, 0x21, 0 + .dw 0x0653, 0xc414, 0x067f, 0xc414, 0x21, 0 + .dw 0x0681, 0xc414, 0x0681, 0xc414, 0x21, 0 + .dw 0x0683, 0xc414, 0x068f, 0xc414, 0x21, 0 + .dw 0x0691, 0xc414, 0x0691, 0xc414, 0x21, 0 + .dw 0x0693, 0xc414, 0x06bf, 0xc414, 0x21, 0 + .dw 0x06c1, 0xc414, 0x06c1, 0xc414, 0x21, 0 + .dw 0x06c3, 0xc414, 0x06cf, 0xc414, 0x21, 0 + .dw 0x06d1, 0xc414, 0x06d1, 0xc414, 0x21, 0 + .dw 0x06d3, 0xc414, 0x06ff, 0xc414, 0x21, 0 + .dw 0x0701, 0xc414, 0x0701, 0xc414, 0x21, 0 + .dw 0x0703, 0xc414, 0x070f, 0xc414, 0x21, 0 + .dw 0x0711, 0xc414, 0x0711, 0xc414, 0x21, 0 + .dw 0x0713, 0xc414, 0x073f, 0xc414, 0x21, 0 + .dw 0x0741, 0xc414, 0x0741, 0xc414, 0x21, 0 + .dw 0x0743, 0xc414, 0x074f, 0xc414, 0x21, 0 + .dw 0x0751, 0xc414, 0x0751, 0xc414, 0x21, 0 + .dw 0x0753, 0xc414, 0x077f, 0xc414, 0x21, 0 + .dw 0x0781, 0xc414, 0x0781, 0xc414, 0x21, 0 + .dw 0x0783, 0xc414, 0x078f, 0xc414, 0x21, 0 + .dw 0x0791, 0xc414, 0x0791, 0xc414, 0x21, 0 + .dw 0x0793, 0xc414, 0x07bf, 0xc414, 0x21, 0 + .dw 0x07c1, 0xc414, 0x07c1, 0xc414, 0x21, 0 + .dw 0x07c3, 0xc414, 0x07cf, 0xc414, 0x21, 0 + .dw 0x07d1, 0xc414, 0x07d1, 0xc414, 0x21, 0 + .dw 0x07d3, 0xc414, 0x07ff, 0xc414, 0x21, 0 + .dw 0x0801, 0xc414, 0x0801, 0xc414, 0x21, 0 + .dw 0x0803, 0xc414, 0x080f, 0xc414, 0x21, 0 + .dw 0x0811, 0xc414, 0x0811, 0xc414, 0x21, 0 + .dw 0x0813, 0xc414, 0x083f, 0xc414, 0x21, 0 + .dw 0x0841, 0xc414, 0x0841, 0xc414, 0x21, 0 + .dw 0x0843, 0xc414, 0x084f, 0xc414, 0x21, 0 + .dw 0x0851, 0xc414, 0x0851, 0xc414, 0x21, 0 + .dw 0x0853, 0xc414, 0x087f, 0xc414, 0x21, 0 + .dw 0x0881, 0xc414, 0x0881, 0xc414, 0x21, 0 + .dw 0x0883, 0xc414, 0x088f, 0xc414, 0x21, 0 + .dw 0x0891, 0xc414, 0x0891, 0xc414, 0x21, 0 + .dw 0x0893, 0xc414, 0x08bf, 0xc414, 0x21, 0 + .dw 0x08c1, 0xc414, 0x08c1, 0xc414, 0x21, 0 + .dw 0x08c3, 0xc414, 0x08cf, 0xc414, 0x21, 0 + .dw 0x08d1, 0xc414, 0x08d1, 0xc414, 0x21, 0 + .dw 0x08d3, 0xc414, 0x08ff, 0xc414, 0x21, 0 + .dw 0x0901, 0xc414, 0x0901, 0xc414, 0x21, 0 + .dw 0x0903, 0xc414, 0x090f, 0xc414, 0x21, 0 + .dw 0x0911, 0xc414, 0x0911, 0xc414, 0x21, 0 + .dw 0x0913, 0xc414, 0x093f, 0xc414, 0x21, 0 + .dw 0x0941, 0xc414, 0x0941, 0xc414, 0x21, 0 + .dw 0x0943, 0xc414, 0x094f, 0xc414, 0x21, 0 + .dw 0x0951, 0xc414, 0x0951, 0xc414, 0x21, 0 + .dw 0x0953, 0xc414, 0x097f, 0xc414, 0x21, 0 + .dw 0x0981, 0xc414, 0x0981, 0xc414, 0x21, 0 + .dw 0x0983, 0xc414, 0x098f, 0xc414, 0x21, 0 + .dw 0x0991, 0xc414, 0x0991, 0xc414, 0x21, 0 + .dw 0x0993, 0xc414, 0x09bf, 0xc414, 0x21, 0 + .dw 0x09c1, 0xc414, 0x09c1, 0xc414, 0x21, 0 + .dw 0x09c3, 0xc414, 0x09cf, 0xc414, 0x21, 0 + .dw 0x09d1, 0xc414, 0x09d1, 0xc414, 0x21, 0 + .dw 0x09d3, 0xc414, 0x09ff, 0xc414, 0x21, 0 + .dw 0x0a01, 0xc414, 0x0a01, 0xc414, 0x21, 0 + .dw 0x0a03, 0xc414, 0x0a0f, 0xc414, 0x21, 0 + .dw 0x0a11, 0xc414, 0x0a11, 0xc414, 0x21, 0 + .dw 0x0a13, 0xc414, 0x0a3f, 0xc414, 0x21, 0 + .dw 0x0a41, 0xc414, 0x0a41, 0xc414, 0x21, 0 + .dw 0x0a43, 0xc414, 0x0a4f, 0xc414, 0x21, 0 + .dw 0x0a51, 0xc414, 0x0a51, 0xc414, 0x21, 0 + .dw 0x0a53, 0xc414, 0x0a7f, 0xc414, 0x21, 0 + .dw 0x0a81, 0xc414, 0x0a81, 0xc414, 0x21, 0 + .dw 0x0a83, 0xc414, 0x0a8f, 0xc414, 0x21, 0 + .dw 0x0a91, 0xc414, 0x0a91, 0xc414, 0x21, 0 + .dw 0x0a93, 0xc414, 0x0abf, 0xc414, 0x21, 0 + .dw 0x0ac1, 0xc414, 0x0ac1, 0xc414, 0x21, 0 + .dw 0x0ac3, 0xc414, 0x0acf, 0xc414, 0x21, 0 + .dw 0x0ad1, 0xc414, 0x0ad1, 0xc414, 0x21, 0 + .dw 0x0ad3, 0xc414, 0x0aff, 0xc414, 0x21, 0 + .dw 0x0b01, 0xc414, 0x0b01, 0xc414, 0x21, 0 + .dw 0x0b03, 0xc414, 0x0b0f, 0xc414, 0x21, 0 + .dw 0x0b11, 0xc414, 0x0b11, 0xc414, 0x21, 0 + .dw 0x0b13, 0xc414, 0x0b3f, 0xc414, 0x21, 0 + .dw 0x0b41, 0xc414, 0x0b41, 0xc414, 0x21, 0 + .dw 0x0b43, 0xc414, 0x0b4f, 0xc414, 0x21, 0 + .dw 0x0b51, 0xc414, 0x0b51, 0xc414, 0x21, 0 + .dw 0x0b53, 0xc414, 0x0b7f, 0xc414, 0x21, 0 + .dw 0x0b81, 0xc414, 0x0b81, 0xc414, 0x21, 0 + .dw 0x0b83, 0xc414, 0x0b8f, 0xc414, 0x21, 0 + .dw 0x0b91, 0xc414, 0x0b91, 0xc414, 0x21, 0 + .dw 0x0b93, 0xc414, 0x0bbf, 0xc414, 0x21, 0 + .dw 0x0bc1, 0xc414, 0x0bc1, 0xc414, 0x21, 0 + .dw 0x0bc3, 0xc414, 0x0bcf, 0xc414, 0x21, 0 + .dw 0x0bd1, 0xc414, 0x0bd1, 0xc414, 0x21, 0 + .dw 0x0bd3, 0xc414, 0x0bff, 0xc414, 0x21, 0 + .dw 0x0c01, 0xc414, 0x0c01, 0xc414, 0x21, 0 + .dw 0x0c03, 0xc414, 0x0c0f, 0xc414, 0x21, 0 + .dw 0x0c11, 0xc414, 0x0c11, 0xc414, 0x21, 0 + .dw 0x0c13, 0xc414, 0x0c3f, 0xc414, 0x21, 0 + .dw 0x0c41, 0xc414, 0x0c41, 0xc414, 0x21, 0 + .dw 0x0c43, 0xc414, 0x0c4f, 0xc414, 0x21, 0 + .dw 0x0c51, 0xc414, 0x0c51, 0xc414, 0x21, 0 + .dw 0x0c53, 0xc414, 0x0c7f, 0xc414, 0x21, 0 + .dw 0x0c81, 0xc414, 0x0c81, 0xc414, 0x21, 0 + .dw 0x0c83, 0xc414, 0x0c8f, 0xc414, 0x21, 0 + .dw 0x0c91, 0xc414, 0x0c91, 0xc414, 0x21, 0 + .dw 0x0c93, 0xc414, 0x0cbf, 0xc414, 0x21, 0 + .dw 0x0cc1, 0xc414, 0x0cc1, 0xc414, 0x21, 0 + .dw 0x0cc3, 0xc414, 0x0ccf, 0xc414, 0x21, 0 + .dw 0x0cd1, 0xc414, 0x0cd1, 0xc414, 0x21, 0 + .dw 0x0cd3, 0xc414, 0x0cff, 0xc414, 0x21, 0 + .dw 0x0d01, 0xc414, 0x0d01, 0xc414, 0x21, 0 + .dw 0x0d03, 0xc414, 0x0d0f, 0xc414, 0x21, 0 + .dw 0x0d11, 0xc414, 0x0d11, 0xc414, 0x21, 0 + .dw 0x0d13, 0xc414, 0x0d3f, 0xc414, 0x21, 0 + .dw 0x0d41, 0xc414, 0x0d41, 0xc414, 0x21, 0 + .dw 0x0d43, 0xc414, 0x0d4f, 0xc414, 0x21, 0 + .dw 0x0d51, 0xc414, 0x0d51, 0xc414, 0x21, 0 + .dw 0x0d53, 0xc414, 0x0d7f, 0xc414, 0x21, 0 + .dw 0x0d81, 0xc414, 0x0d81, 0xc414, 0x21, 0 + .dw 0x0d83, 0xc414, 0x0d8f, 0xc414, 0x21, 0 + .dw 0x0d91, 0xc414, 0x0d91, 0xc414, 0x21, 0 + .dw 0x0d93, 0xc414, 0x0dbf, 0xc414, 0x21, 0 + .dw 0x0dc1, 0xc414, 0x0dc1, 0xc414, 0x21, 0 + .dw 0x0dc3, 0xc414, 0x0dcf, 0xc414, 0x21, 0 + .dw 0x0dd1, 0xc414, 0x0dd1, 0xc414, 0x21, 0 + .dw 0x0dd3, 0xc414, 0x0dff, 0xc414, 0x21, 0 + .dw 0x0e01, 0xc414, 0x0e01, 0xc414, 0x21, 0 + .dw 0x0e03, 0xc414, 0x0e0f, 0xc414, 0x21, 0 + .dw 0x0e11, 0xc414, 0x0e11, 0xc414, 0x21, 0 + .dw 0x0e13, 0xc414, 0x0e3f, 0xc414, 0x21, 0 + .dw 0x0e41, 0xc414, 0x0e41, 0xc414, 0x21, 0 + .dw 0x0e43, 0xc414, 0x0e4f, 0xc414, 0x21, 0 + .dw 0x0e51, 0xc414, 0x0e51, 0xc414, 0x21, 0 + .dw 0x0e53, 0xc414, 0x0e7f, 0xc414, 0x21, 0 + .dw 0x0e81, 0xc414, 0x0e81, 0xc414, 0x21, 0 + .dw 0x0e83, 0xc414, 0x0e8f, 0xc414, 0x21, 0 + .dw 0x0e91, 0xc414, 0x0e91, 0xc414, 0x21, 0 + .dw 0x0e93, 0xc414, 0x0ebf, 0xc414, 0x21, 0 + .dw 0x0ec1, 0xc414, 0x0ec1, 0xc414, 0x21, 0 + .dw 0x0ec3, 0xc414, 0x0ecf, 0xc414, 0x21, 0 + .dw 0x0ed1, 0xc414, 0x0ed1, 0xc414, 0x21, 0 + .dw 0x0ed3, 0xc414, 0x0eff, 0xc414, 0x21, 0 + .dw 0x0f01, 0xc414, 0x0f01, 0xc414, 0x21, 0 + .dw 0x0f03, 0xc414, 0x0f0f, 0xc414, 0x21, 0 + .dw 0x0f11, 0xc414, 0x0f11, 0xc414, 0x21, 0 + .dw 0x0f13, 0xc414, 0x0f3f, 0xc414, 0x21, 0 + .dw 0x0f41, 0xc414, 0x0f41, 0xc414, 0x21, 0 + .dw 0x0f43, 0xc414, 0x0f4f, 0xc414, 0x21, 0 + .dw 0x0f51, 0xc414, 0x0f51, 0xc414, 0x21, 0 + .dw 0x0f53, 0xc414, 0x0f7f, 0xc414, 0x21, 0 + .dw 0x0f81, 0xc414, 0x0f81, 0xc414, 0x21, 0 + .dw 0x0f83, 0xc414, 0x0f8f, 0xc414, 0x21, 0 + .dw 0x0f91, 0xc414, 0x0f91, 0xc414, 0x21, 0 + .dw 0x0f93, 0xc414, 0x0fbf, 0xc414, 0x21, 0 + .dw 0x0fc1, 0xc414, 0x0fc1, 0xc414, 0x21, 0 + .dw 0x0fc3, 0xc414, 0x0fcf, 0xc414, 0x21, 0 + .dw 0x0fd1, 0xc414, 0x0fd1, 0xc414, 0x21, 0 + .dw 0x0fd3, 0xc414, 0x1fff, 0xc414, 0x21, 0 + .dw 0x2001, 0xc414, 0x2001, 0xc414, 0x21, 0 + .dw 0x2003, 0xc414, 0x200f, 0xc414, 0x21, 0 + .dw 0x2011, 0xc414, 0x2011, 0xc414, 0x21, 0 + .dw 0x2013, 0xc414, 0x203f, 0xc414, 0x21, 0 + .dw 0x2041, 0xc414, 0x2041, 0xc414, 0x21, 0 + .dw 0x2043, 0xc414, 0x204f, 0xc414, 0x21, 0 + .dw 0x2051, 0xc414, 0x2051, 0xc414, 0x21, 0 + .dw 0x2053, 0xc414, 0x207f, 0xc414, 0x21, 0 + .dw 0x2081, 0xc414, 0x2081, 0xc414, 0x21, 0 + .dw 0x2083, 0xc414, 0x208f, 0xc414, 0x21, 0 + .dw 0x2091, 0xc414, 0x2091, 0xc414, 0x21, 0 + .dw 0x2093, 0xc414, 0x20bf, 0xc414, 0x21, 0 + .dw 0x20c1, 0xc414, 0x20c1, 0xc414, 0x21, 0 + .dw 0x20c3, 0xc414, 0x20cf, 0xc414, 0x21, 0 + .dw 0x20d1, 0xc414, 0x20d1, 0xc414, 0x21, 0 + .dw 0x20d3, 0xc414, 0x20ff, 0xc414, 0x21, 0 + .dw 0x2101, 0xc414, 0x2101, 0xc414, 0x21, 0 + .dw 0x2103, 0xc414, 0x210f, 0xc414, 0x21, 0 + .dw 0x2111, 0xc414, 0x2111, 0xc414, 0x21, 0 + .dw 0x2113, 0xc414, 0x213f, 0xc414, 0x21, 0 + .dw 0x2141, 0xc414, 0x2141, 0xc414, 0x21, 0 + .dw 0x2143, 0xc414, 0x214f, 0xc414, 0x21, 0 + .dw 0x2151, 0xc414, 0x2151, 0xc414, 0x21, 0 + .dw 0x2153, 0xc414, 0x217f, 0xc414, 0x21, 0 + .dw 0x2181, 0xc414, 0x2181, 0xc414, 0x21, 0 + .dw 0x2183, 0xc414, 0x218f, 0xc414, 0x21, 0 + .dw 0x2191, 0xc414, 0x2191, 0xc414, 0x21, 0 + .dw 0x2193, 0xc414, 0x21bf, 0xc414, 0x21, 0 + .dw 0x21c1, 0xc414, 0x21c1, 0xc414, 0x21, 0 + .dw 0x21c3, 0xc414, 0x21cf, 0xc414, 0x21, 0 + .dw 0x21d1, 0xc414, 0x21d1, 0xc414, 0x21, 0 + .dw 0x21d3, 0xc414, 0x21ff, 0xc414, 0x21, 0 + .dw 0x2201, 0xc414, 0x2201, 0xc414, 0x21, 0 + .dw 0x2203, 0xc414, 0x220f, 0xc414, 0x21, 0 + .dw 0x2211, 0xc414, 0x2211, 0xc414, 0x21, 0 + .dw 0x2213, 0xc414, 0x223f, 0xc414, 0x21, 0 + .dw 0x2241, 0xc414, 0x2241, 0xc414, 0x21, 0 + .dw 0x2243, 0xc414, 0x224f, 0xc414, 0x21, 0 + .dw 0x2251, 0xc414, 0x2251, 0xc414, 0x21, 0 + .dw 0x2253, 0xc414, 0x227f, 0xc414, 0x21, 0 + .dw 0x2281, 0xc414, 0x2281, 0xc414, 0x21, 0 + .dw 0x2283, 0xc414, 0x228f, 0xc414, 0x21, 0 + .dw 0x2291, 0xc414, 0x2291, 0xc414, 0x21, 0 + .dw 0x2293, 0xc414, 0x22bf, 0xc414, 0x21, 0 + .dw 0x22c1, 0xc414, 0x22c1, 0xc414, 0x21, 0 + .dw 0x22c3, 0xc414, 0x22cf, 0xc414, 0x21, 0 + .dw 0x22d1, 0xc414, 0x22d1, 0xc414, 0x21, 0 + .dw 0x22d3, 0xc414, 0x22ff, 0xc414, 0x21, 0 + .dw 0x2301, 0xc414, 0x2301, 0xc414, 0x21, 0 + .dw 0x2303, 0xc414, 0x230f, 0xc414, 0x21, 0 + .dw 0x2311, 0xc414, 0x2311, 0xc414, 0x21, 0 + .dw 0x2313, 0xc414, 0x233f, 0xc414, 0x21, 0 + .dw 0x2341, 0xc414, 0x2341, 0xc414, 0x21, 0 + .dw 0x2343, 0xc414, 0x234f, 0xc414, 0x21, 0 + .dw 0x2351, 0xc414, 0x2351, 0xc414, 0x21, 0 + .dw 0x2353, 0xc414, 0x237f, 0xc414, 0x21, 0 + .dw 0x2381, 0xc414, 0x2381, 0xc414, 0x21, 0 + .dw 0x2383, 0xc414, 0x238f, 0xc414, 0x21, 0 + .dw 0x2391, 0xc414, 0x2391, 0xc414, 0x21, 0 + .dw 0x2393, 0xc414, 0x23bf, 0xc414, 0x21, 0 + .dw 0x23c1, 0xc414, 0x23c1, 0xc414, 0x21, 0 + .dw 0x23c3, 0xc414, 0x23cf, 0xc414, 0x21, 0 + .dw 0x23d1, 0xc414, 0x23d1, 0xc414, 0x21, 0 + .dw 0x23d3, 0xc414, 0x23ff, 0xc414, 0x21, 0 + .dw 0x2401, 0xc414, 0x2401, 0xc414, 0x21, 0 + .dw 0x2403, 0xc414, 0x240f, 0xc414, 0x21, 0 + .dw 0x2411, 0xc414, 0x2411, 0xc414, 0x21, 0 + .dw 0x2413, 0xc414, 0x243f, 0xc414, 0x21, 0 + .dw 0x2441, 0xc414, 0x2441, 0xc414, 0x21, 0 + .dw 0x2443, 0xc414, 0x244f, 0xc414, 0x21, 0 + .dw 0x2451, 0xc414, 0x2451, 0xc414, 0x21, 0 + .dw 0x2453, 0xc414, 0x247f, 0xc414, 0x21, 0 + .dw 0x2481, 0xc414, 0x2481, 0xc414, 0x21, 0 + .dw 0x2483, 0xc414, 0x248f, 0xc414, 0x21, 0 + .dw 0x2491, 0xc414, 0x2491, 0xc414, 0x21, 0 + .dw 0x2493, 0xc414, 0x24bf, 0xc414, 0x21, 0 + .dw 0x24c1, 0xc414, 0x24c1, 0xc414, 0x21, 0 + .dw 0x24c3, 0xc414, 0x24cf, 0xc414, 0x21, 0 + .dw 0x24d1, 0xc414, 0x24d1, 0xc414, 0x21, 0 + .dw 0x24d3, 0xc414, 0x24ff, 0xc414, 0x21, 0 + .dw 0x2501, 0xc414, 0x2501, 0xc414, 0x21, 0 + .dw 0x2503, 0xc414, 0x250f, 0xc414, 0x21, 0 + .dw 0x2511, 0xc414, 0x2511, 0xc414, 0x21, 0 + .dw 0x2513, 0xc414, 0x253f, 0xc414, 0x21, 0 + .dw 0x2541, 0xc414, 0x2541, 0xc414, 0x21, 0 + .dw 0x2543, 0xc414, 0x254f, 0xc414, 0x21, 0 + .dw 0x2551, 0xc414, 0x2551, 0xc414, 0x21, 0 + .dw 0x2553, 0xc414, 0x257f, 0xc414, 0x21, 0 + .dw 0x2581, 0xc414, 0x2581, 0xc414, 0x21, 0 + .dw 0x2583, 0xc414, 0x258f, 0xc414, 0x21, 0 + .dw 0x2591, 0xc414, 0x2591, 0xc414, 0x21, 0 + .dw 0x2593, 0xc414, 0x25bf, 0xc414, 0x21, 0 + .dw 0x25c1, 0xc414, 0x25c1, 0xc414, 0x21, 0 + .dw 0x25c3, 0xc414, 0x25cf, 0xc414, 0x21, 0 + .dw 0x25d1, 0xc414, 0x25d1, 0xc414, 0x21, 0 + .dw 0x25d3, 0xc414, 0x25ff, 0xc414, 0x21, 0 + .dw 0x2601, 0xc414, 0x2601, 0xc414, 0x21, 0 + .dw 0x2603, 0xc414, 0x260f, 0xc414, 0x21, 0 + .dw 0x2611, 0xc414, 0x2611, 0xc414, 0x21, 0 + .dw 0x2613, 0xc414, 0x263f, 0xc414, 0x21, 0 + .dw 0x2641, 0xc414, 0x2641, 0xc414, 0x21, 0 + .dw 0x2643, 0xc414, 0x264f, 0xc414, 0x21, 0 + .dw 0x2651, 0xc414, 0x2651, 0xc414, 0x21, 0 + .dw 0x2653, 0xc414, 0x267f, 0xc414, 0x21, 0 + .dw 0x2681, 0xc414, 0x2681, 0xc414, 0x21, 0 + .dw 0x2683, 0xc414, 0x268f, 0xc414, 0x21, 0 + .dw 0x2691, 0xc414, 0x2691, 0xc414, 0x21, 0 + .dw 0x2693, 0xc414, 0x26bf, 0xc414, 0x21, 0 + .dw 0x26c1, 0xc414, 0x26c1, 0xc414, 0x21, 0 + .dw 0x26c3, 0xc414, 0x26cf, 0xc414, 0x21, 0 + .dw 0x26d1, 0xc414, 0x26d1, 0xc414, 0x21, 0 + .dw 0x26d3, 0xc414, 0x26ff, 0xc414, 0x21, 0 + .dw 0x2701, 0xc414, 0x2701, 0xc414, 0x21, 0 + .dw 0x2703, 0xc414, 0x270f, 0xc414, 0x21, 0 + .dw 0x2711, 0xc414, 0x2711, 0xc414, 0x21, 0 + .dw 0x2713, 0xc414, 0x273f, 0xc414, 0x21, 0 + .dw 0x2741, 0xc414, 0x2741, 0xc414, 0x21, 0 + .dw 0x2743, 0xc414, 0x274f, 0xc414, 0x21, 0 + .dw 0x2751, 0xc414, 0x2751, 0xc414, 0x21, 0 + .dw 0x2753, 0xc414, 0x277f, 0xc414, 0x21, 0 + .dw 0x2781, 0xc414, 0x2781, 0xc414, 0x21, 0 + .dw 0x2783, 0xc414, 0x278f, 0xc414, 0x21, 0 + .dw 0x2791, 0xc414, 0x2791, 0xc414, 0x21, 0 + .dw 0x2793, 0xc414, 0x27bf, 0xc414, 0x21, 0 + .dw 0x27c1, 0xc414, 0x27c1, 0xc414, 0x21, 0 + .dw 0x27c3, 0xc414, 0x27cf, 0xc414, 0x21, 0 + .dw 0x27d1, 0xc414, 0x27d1, 0xc414, 0x21, 0 + .dw 0x27d3, 0xc414, 0x27ff, 0xc414, 0x21, 0 + .dw 0x2801, 0xc414, 0x2801, 0xc414, 0x21, 0 + .dw 0x2803, 0xc414, 0x280f, 0xc414, 0x21, 0 + .dw 0x2811, 0xc414, 0x2811, 0xc414, 0x21, 0 + .dw 0x2813, 0xc414, 0x283f, 0xc414, 0x21, 0 + .dw 0x2841, 0xc414, 0x2841, 0xc414, 0x21, 0 + .dw 0x2843, 0xc414, 0x284f, 0xc414, 0x21, 0 + .dw 0x2851, 0xc414, 0x2851, 0xc414, 0x21, 0 + .dw 0x2853, 0xc414, 0x287f, 0xc414, 0x21, 0 + .dw 0x2881, 0xc414, 0x2881, 0xc414, 0x21, 0 + .dw 0x2883, 0xc414, 0x288f, 0xc414, 0x21, 0 + .dw 0x2891, 0xc414, 0x2891, 0xc414, 0x21, 0 + .dw 0x2893, 0xc414, 0x28bf, 0xc414, 0x21, 0 + .dw 0x28c1, 0xc414, 0x28c1, 0xc414, 0x21, 0 + .dw 0x28c3, 0xc414, 0x28cf, 0xc414, 0x21, 0 + .dw 0x28d1, 0xc414, 0x28d1, 0xc414, 0x21, 0 + .dw 0x28d3, 0xc414, 0x28ff, 0xc414, 0x21, 0 + .dw 0x2901, 0xc414, 0x2901, 0xc414, 0x21, 0 + .dw 0x2903, 0xc414, 0x290f, 0xc414, 0x21, 0 + .dw 0x2911, 0xc414, 0x2911, 0xc414, 0x21, 0 + .dw 0x2913, 0xc414, 0x293f, 0xc414, 0x21, 0 + .dw 0x2941, 0xc414, 0x2941, 0xc414, 0x21, 0 + .dw 0x2943, 0xc414, 0x294f, 0xc414, 0x21, 0 + .dw 0x2951, 0xc414, 0x2951, 0xc414, 0x21, 0 + .dw 0x2953, 0xc414, 0x297f, 0xc414, 0x21, 0 + .dw 0x2981, 0xc414, 0x2981, 0xc414, 0x21, 0 + .dw 0x2983, 0xc414, 0x298f, 0xc414, 0x21, 0 + .dw 0x2991, 0xc414, 0x2991, 0xc414, 0x21, 0 + .dw 0x2993, 0xc414, 0x29bf, 0xc414, 0x21, 0 + .dw 0x29c1, 0xc414, 0x29c1, 0xc414, 0x21, 0 + .dw 0x29c3, 0xc414, 0x29cf, 0xc414, 0x21, 0 + .dw 0x29d1, 0xc414, 0x29d1, 0xc414, 0x21, 0 + .dw 0x29d3, 0xc414, 0x29ff, 0xc414, 0x21, 0 + .dw 0x2a01, 0xc414, 0x2a01, 0xc414, 0x21, 0 + .dw 0x2a03, 0xc414, 0x2a0f, 0xc414, 0x21, 0 + .dw 0x2a11, 0xc414, 0x2a11, 0xc414, 0x21, 0 + .dw 0x2a13, 0xc414, 0x2a3f, 0xc414, 0x21, 0 + .dw 0x2a41, 0xc414, 0x2a41, 0xc414, 0x21, 0 + .dw 0x2a43, 0xc414, 0x2a4f, 0xc414, 0x21, 0 + .dw 0x2a51, 0xc414, 0x2a51, 0xc414, 0x21, 0 + .dw 0x2a53, 0xc414, 0x2a7f, 0xc414, 0x21, 0 + .dw 0x2a81, 0xc414, 0x2a81, 0xc414, 0x21, 0 + .dw 0x2a83, 0xc414, 0x2a8f, 0xc414, 0x21, 0 + .dw 0x2a91, 0xc414, 0x2a91, 0xc414, 0x21, 0 + .dw 0x2a93, 0xc414, 0x2abf, 0xc414, 0x21, 0 + .dw 0x2ac1, 0xc414, 0x2ac1, 0xc414, 0x21, 0 + .dw 0x2ac3, 0xc414, 0x2acf, 0xc414, 0x21, 0 + .dw 0x2ad1, 0xc414, 0x2ad1, 0xc414, 0x21, 0 + .dw 0x2ad3, 0xc414, 0x2aff, 0xc414, 0x21, 0 + .dw 0x2b01, 0xc414, 0x2b01, 0xc414, 0x21, 0 + .dw 0x2b03, 0xc414, 0x2b0f, 0xc414, 0x21, 0 + .dw 0x2b11, 0xc414, 0x2b11, 0xc414, 0x21, 0 + .dw 0x2b13, 0xc414, 0x2b3f, 0xc414, 0x21, 0 + .dw 0x2b41, 0xc414, 0x2b41, 0xc414, 0x21, 0 + .dw 0x2b43, 0xc414, 0x2b4f, 0xc414, 0x21, 0 + .dw 0x2b51, 0xc414, 0x2b51, 0xc414, 0x21, 0 + .dw 0x2b53, 0xc414, 0x2b7f, 0xc414, 0x21, 0 + .dw 0x2b81, 0xc414, 0x2b81, 0xc414, 0x21, 0 + .dw 0x2b83, 0xc414, 0x2b8f, 0xc414, 0x21, 0 + .dw 0x2b91, 0xc414, 0x2b91, 0xc414, 0x21, 0 + .dw 0x2b93, 0xc414, 0x2bbf, 0xc414, 0x21, 0 + .dw 0x2bc1, 0xc414, 0x2bc1, 0xc414, 0x21, 0 + .dw 0x2bc3, 0xc414, 0x2bcf, 0xc414, 0x21, 0 + .dw 0x2bd1, 0xc414, 0x2bd1, 0xc414, 0x21, 0 + .dw 0x2bd3, 0xc414, 0x2bff, 0xc414, 0x21, 0 + .dw 0x2c01, 0xc414, 0x2c01, 0xc414, 0x21, 0 + .dw 0x2c03, 0xc414, 0x2c0f, 0xc414, 0x21, 0 + .dw 0x2c11, 0xc414, 0x2c11, 0xc414, 0x21, 0 + .dw 0x2c13, 0xc414, 0x2c3f, 0xc414, 0x21, 0 + .dw 0x2c41, 0xc414, 0x2c41, 0xc414, 0x21, 0 + .dw 0x2c43, 0xc414, 0x2c4f, 0xc414, 0x21, 0 + .dw 0x2c51, 0xc414, 0x2c51, 0xc414, 0x21, 0 + .dw 0x2c53, 0xc414, 0x2c7f, 0xc414, 0x21, 0 + .dw 0x2c81, 0xc414, 0x2c81, 0xc414, 0x21, 0 + .dw 0x2c83, 0xc414, 0x2c8f, 0xc414, 0x21, 0 + .dw 0x2c91, 0xc414, 0x2c91, 0xc414, 0x21, 0 + .dw 0x2c93, 0xc414, 0x2cbf, 0xc414, 0x21, 0 + .dw 0x2cc1, 0xc414, 0x2cc1, 0xc414, 0x21, 0 + .dw 0x2cc3, 0xc414, 0x2ccf, 0xc414, 0x21, 0 + .dw 0x2cd1, 0xc414, 0x2cd1, 0xc414, 0x21, 0 + .dw 0x2cd3, 0xc414, 0x2cff, 0xc414, 0x21, 0 + .dw 0x2d01, 0xc414, 0x2d01, 0xc414, 0x21, 0 + .dw 0x2d03, 0xc414, 0x2d0f, 0xc414, 0x21, 0 + .dw 0x2d11, 0xc414, 0x2d11, 0xc414, 0x21, 0 + .dw 0x2d13, 0xc414, 0x2d3f, 0xc414, 0x21, 0 + .dw 0x2d41, 0xc414, 0x2d41, 0xc414, 0x21, 0 + .dw 0x2d43, 0xc414, 0x2d4f, 0xc414, 0x21, 0 + .dw 0x2d51, 0xc414, 0x2d51, 0xc414, 0x21, 0 + .dw 0x2d53, 0xc414, 0x2d7f, 0xc414, 0x21, 0 + .dw 0x2d81, 0xc414, 0x2d81, 0xc414, 0x21, 0 + .dw 0x2d83, 0xc414, 0x2d8f, 0xc414, 0x21, 0 + .dw 0x2d91, 0xc414, 0x2d91, 0xc414, 0x21, 0 + .dw 0x2d93, 0xc414, 0x2dbf, 0xc414, 0x21, 0 + .dw 0x2dc1, 0xc414, 0x2dc1, 0xc414, 0x21, 0 + .dw 0x2dc3, 0xc414, 0x2dcf, 0xc414, 0x21, 0 + .dw 0x2dd1, 0xc414, 0x2dd1, 0xc414, 0x21, 0 + .dw 0x2dd3, 0xc414, 0x2dff, 0xc414, 0x21, 0 + .dw 0x2e01, 0xc414, 0x2e01, 0xc414, 0x21, 0 + .dw 0x2e03, 0xc414, 0x2e0f, 0xc414, 0x21, 0 + .dw 0x2e11, 0xc414, 0x2e11, 0xc414, 0x21, 0 + .dw 0x2e13, 0xc414, 0x2e3f, 0xc414, 0x21, 0 + .dw 0x2e41, 0xc414, 0x2e41, 0xc414, 0x21, 0 + .dw 0x2e43, 0xc414, 0x2e4f, 0xc414, 0x21, 0 + .dw 0x2e51, 0xc414, 0x2e51, 0xc414, 0x21, 0 + .dw 0x2e53, 0xc414, 0x2e7f, 0xc414, 0x21, 0 + .dw 0x2e81, 0xc414, 0x2e81, 0xc414, 0x21, 0 + .dw 0x2e83, 0xc414, 0x2e8f, 0xc414, 0x21, 0 + .dw 0x2e91, 0xc414, 0x2e91, 0xc414, 0x21, 0 + .dw 0x2e93, 0xc414, 0x2ebf, 0xc414, 0x21, 0 + .dw 0x2ec1, 0xc414, 0x2ec1, 0xc414, 0x21, 0 + .dw 0x2ec3, 0xc414, 0x2ecf, 0xc414, 0x21, 0 + .dw 0x2ed1, 0xc414, 0x2ed1, 0xc414, 0x21, 0 + .dw 0x2ed3, 0xc414, 0x2eff, 0xc414, 0x21, 0 + .dw 0x2f01, 0xc414, 0x2f01, 0xc414, 0x21, 0 + .dw 0x2f03, 0xc414, 0x2f0f, 0xc414, 0x21, 0 + .dw 0x2f11, 0xc414, 0x2f11, 0xc414, 0x21, 0 + .dw 0x2f13, 0xc414, 0x2f3f, 0xc414, 0x21, 0 + .dw 0x2f41, 0xc414, 0x2f41, 0xc414, 0x21, 0 + .dw 0x2f43, 0xc414, 0x2f4f, 0xc414, 0x21, 0 + .dw 0x2f51, 0xc414, 0x2f51, 0xc414, 0x21, 0 + .dw 0x2f53, 0xc414, 0x2f7f, 0xc414, 0x21, 0 + .dw 0x2f81, 0xc414, 0x2f81, 0xc414, 0x21, 0 + .dw 0x2f83, 0xc414, 0x2f8f, 0xc414, 0x21, 0 + .dw 0x2f91, 0xc414, 0x2f91, 0xc414, 0x21, 0 + .dw 0x2f93, 0xc414, 0x2fbf, 0xc414, 0x21, 0 + .dw 0x2fc1, 0xc414, 0x2fc1, 0xc414, 0x21, 0 + .dw 0x2fc3, 0xc414, 0x2fcf, 0xc414, 0x21, 0 + .dw 0x2fd1, 0xc414, 0x2fd1, 0xc414, 0x21, 0 + .dw 0x2fd3, 0xc414, 0x3fff, 0xc414, 0x21, 0 + .dw 0x4001, 0xc414, 0x4001, 0xc414, 0x21, 0 + .dw 0x4003, 0xc414, 0x400f, 0xc414, 0x21, 0 + .dw 0x4011, 0xc414, 0x4011, 0xc414, 0x21, 0 + .dw 0x4013, 0xc414, 0x403f, 0xc414, 0x21, 0 + .dw 0x4041, 0xc414, 0x4041, 0xc414, 0x21, 0 + .dw 0x4043, 0xc414, 0x404f, 0xc414, 0x21, 0 + .dw 0x4051, 0xc414, 0x4051, 0xc414, 0x21, 0 + .dw 0x4053, 0xc414, 0x407f, 0xc414, 0x21, 0 + .dw 0x4081, 0xc414, 0x4081, 0xc414, 0x21, 0 + .dw 0x4083, 0xc414, 0x408f, 0xc414, 0x21, 0 + .dw 0x4091, 0xc414, 0x4091, 0xc414, 0x21, 0 + .dw 0x4093, 0xc414, 0x40bf, 0xc414, 0x21, 0 + .dw 0x40c1, 0xc414, 0x40c1, 0xc414, 0x21, 0 + .dw 0x40c3, 0xc414, 0x40cf, 0xc414, 0x21, 0 + .dw 0x40d1, 0xc414, 0x40d1, 0xc414, 0x21, 0 + .dw 0x40d3, 0xc414, 0x40ff, 0xc414, 0x21, 0 + .dw 0x4101, 0xc414, 0x4101, 0xc414, 0x21, 0 + .dw 0x4103, 0xc414, 0x410f, 0xc414, 0x21, 0 + .dw 0x4111, 0xc414, 0x4111, 0xc414, 0x21, 0 + .dw 0x4113, 0xc414, 0x413f, 0xc414, 0x21, 0 + .dw 0x4141, 0xc414, 0x4141, 0xc414, 0x21, 0 + .dw 0x4143, 0xc414, 0x414f, 0xc414, 0x21, 0 + .dw 0x4151, 0xc414, 0x4151, 0xc414, 0x21, 0 + .dw 0x4153, 0xc414, 0x417f, 0xc414, 0x21, 0 + .dw 0x4181, 0xc414, 0x4181, 0xc414, 0x21, 0 + .dw 0x4183, 0xc414, 0x418f, 0xc414, 0x21, 0 + .dw 0x4191, 0xc414, 0x4191, 0xc414, 0x21, 0 + .dw 0x4193, 0xc414, 0x41bf, 0xc414, 0x21, 0 + .dw 0x41c1, 0xc414, 0x41c1, 0xc414, 0x21, 0 + .dw 0x41c3, 0xc414, 0x41cf, 0xc414, 0x21, 0 + .dw 0x41d1, 0xc414, 0x41d1, 0xc414, 0x21, 0 + .dw 0x41d3, 0xc414, 0x41ff, 0xc414, 0x21, 0 + .dw 0x4201, 0xc414, 0x4201, 0xc414, 0x21, 0 + .dw 0x4203, 0xc414, 0x420f, 0xc414, 0x21, 0 + .dw 0x4211, 0xc414, 0x4211, 0xc414, 0x21, 0 + .dw 0x4213, 0xc414, 0x423f, 0xc414, 0x21, 0 + .dw 0x4241, 0xc414, 0x4241, 0xc414, 0x21, 0 + .dw 0x4243, 0xc414, 0x424f, 0xc414, 0x21, 0 + .dw 0x4251, 0xc414, 0x4251, 0xc414, 0x21, 0 + .dw 0x4253, 0xc414, 0x427f, 0xc414, 0x21, 0 + .dw 0x4281, 0xc414, 0x4281, 0xc414, 0x21, 0 + .dw 0x4283, 0xc414, 0x428f, 0xc414, 0x21, 0 + .dw 0x4291, 0xc414, 0x4291, 0xc414, 0x21, 0 + .dw 0x4293, 0xc414, 0x42bf, 0xc414, 0x21, 0 + .dw 0x42c1, 0xc414, 0x42c1, 0xc414, 0x21, 0 + .dw 0x42c3, 0xc414, 0x42cf, 0xc414, 0x21, 0 + .dw 0x42d1, 0xc414, 0x42d1, 0xc414, 0x21, 0 + .dw 0x42d3, 0xc414, 0x42ff, 0xc414, 0x21, 0 + .dw 0x4301, 0xc414, 0x4301, 0xc414, 0x21, 0 + .dw 0x4303, 0xc414, 0x430f, 0xc414, 0x21, 0 + .dw 0x4311, 0xc414, 0x4311, 0xc414, 0x21, 0 + .dw 0x4313, 0xc414, 0x433f, 0xc414, 0x21, 0 + .dw 0x4341, 0xc414, 0x4341, 0xc414, 0x21, 0 + .dw 0x4343, 0xc414, 0x434f, 0xc414, 0x21, 0 + .dw 0x4351, 0xc414, 0x4351, 0xc414, 0x21, 0 + .dw 0x4353, 0xc414, 0x437f, 0xc414, 0x21, 0 + .dw 0x4381, 0xc414, 0x4381, 0xc414, 0x21, 0 + .dw 0x4383, 0xc414, 0x438f, 0xc414, 0x21, 0 + .dw 0x4391, 0xc414, 0x4391, 0xc414, 0x21, 0 + .dw 0x4393, 0xc414, 0x43bf, 0xc414, 0x21, 0 + .dw 0x43c1, 0xc414, 0x43c1, 0xc414, 0x21, 0 + .dw 0x43c3, 0xc414, 0x43cf, 0xc414, 0x21, 0 + .dw 0x43d1, 0xc414, 0x43d1, 0xc414, 0x21, 0 + .dw 0x43d3, 0xc414, 0x43ff, 0xc414, 0x21, 0 + .dw 0x4401, 0xc414, 0x4401, 0xc414, 0x21, 0 + .dw 0x4403, 0xc414, 0x440f, 0xc414, 0x21, 0 + .dw 0x4411, 0xc414, 0x4411, 0xc414, 0x21, 0 + .dw 0x4413, 0xc414, 0x443f, 0xc414, 0x21, 0 + .dw 0x4441, 0xc414, 0x4441, 0xc414, 0x21, 0 + .dw 0x4443, 0xc414, 0x444f, 0xc414, 0x21, 0 + .dw 0x4451, 0xc414, 0x4451, 0xc414, 0x21, 0 + .dw 0x4453, 0xc414, 0x447f, 0xc414, 0x21, 0 + .dw 0x4481, 0xc414, 0x4481, 0xc414, 0x21, 0 + .dw 0x4483, 0xc414, 0x448f, 0xc414, 0x21, 0 + .dw 0x4491, 0xc414, 0x4491, 0xc414, 0x21, 0 + .dw 0x4493, 0xc414, 0x44bf, 0xc414, 0x21, 0 + .dw 0x44c1, 0xc414, 0x44c1, 0xc414, 0x21, 0 + .dw 0x44c3, 0xc414, 0x44cf, 0xc414, 0x21, 0 + .dw 0x44d1, 0xc414, 0x44d1, 0xc414, 0x21, 0 + .dw 0x44d3, 0xc414, 0x44ff, 0xc414, 0x21, 0 + .dw 0x4501, 0xc414, 0x4501, 0xc414, 0x21, 0 + .dw 0x4503, 0xc414, 0x450f, 0xc414, 0x21, 0 + .dw 0x4511, 0xc414, 0x4511, 0xc414, 0x21, 0 + .dw 0x4513, 0xc414, 0x453f, 0xc414, 0x21, 0 + .dw 0x4541, 0xc414, 0x4541, 0xc414, 0x21, 0 + .dw 0x4543, 0xc414, 0x454f, 0xc414, 0x21, 0 + .dw 0x4551, 0xc414, 0x4551, 0xc414, 0x21, 0 + .dw 0x4553, 0xc414, 0x457f, 0xc414, 0x21, 0 + .dw 0x4581, 0xc414, 0x4581, 0xc414, 0x21, 0 + .dw 0x4583, 0xc414, 0x458f, 0xc414, 0x21, 0 + .dw 0x4591, 0xc414, 0x4591, 0xc414, 0x21, 0 + .dw 0x4593, 0xc414, 0x45bf, 0xc414, 0x21, 0 + .dw 0x45c1, 0xc414, 0x45c1, 0xc414, 0x21, 0 + .dw 0x45c3, 0xc414, 0x45cf, 0xc414, 0x21, 0 + .dw 0x45d1, 0xc414, 0x45d1, 0xc414, 0x21, 0 + .dw 0x45d3, 0xc414, 0x45ff, 0xc414, 0x21, 0 + .dw 0x4601, 0xc414, 0x4601, 0xc414, 0x21, 0 + .dw 0x4603, 0xc414, 0x460f, 0xc414, 0x21, 0 + .dw 0x4611, 0xc414, 0x4611, 0xc414, 0x21, 0 + .dw 0x4613, 0xc414, 0x463f, 0xc414, 0x21, 0 + .dw 0x4641, 0xc414, 0x4641, 0xc414, 0x21, 0 + .dw 0x4643, 0xc414, 0x464f, 0xc414, 0x21, 0 + .dw 0x4651, 0xc414, 0x4651, 0xc414, 0x21, 0 + .dw 0x4653, 0xc414, 0x467f, 0xc414, 0x21, 0 + .dw 0x4681, 0xc414, 0x4681, 0xc414, 0x21, 0 + .dw 0x4683, 0xc414, 0x468f, 0xc414, 0x21, 0 + .dw 0x4691, 0xc414, 0x4691, 0xc414, 0x21, 0 + .dw 0x4693, 0xc414, 0x46bf, 0xc414, 0x21, 0 + .dw 0x46c1, 0xc414, 0x46c1, 0xc414, 0x21, 0 + .dw 0x46c3, 0xc414, 0x46cf, 0xc414, 0x21, 0 + .dw 0x46d1, 0xc414, 0x46d1, 0xc414, 0x21, 0 + .dw 0x46d3, 0xc414, 0x46ff, 0xc414, 0x21, 0 + .dw 0x4701, 0xc414, 0x4701, 0xc414, 0x21, 0 + .dw 0x4703, 0xc414, 0x470f, 0xc414, 0x21, 0 + .dw 0x4711, 0xc414, 0x4711, 0xc414, 0x21, 0 + .dw 0x4713, 0xc414, 0x473f, 0xc414, 0x21, 0 + .dw 0x4741, 0xc414, 0x4741, 0xc414, 0x21, 0 + .dw 0x4743, 0xc414, 0x474f, 0xc414, 0x21, 0 + .dw 0x4751, 0xc414, 0x4751, 0xc414, 0x21, 0 + .dw 0x4753, 0xc414, 0x477f, 0xc414, 0x21, 0 + .dw 0x4781, 0xc414, 0x4781, 0xc414, 0x21, 0 + .dw 0x4783, 0xc414, 0x478f, 0xc414, 0x21, 0 + .dw 0x4791, 0xc414, 0x4791, 0xc414, 0x21, 0 + .dw 0x4793, 0xc414, 0x47bf, 0xc414, 0x21, 0 + .dw 0x47c1, 0xc414, 0x47c1, 0xc414, 0x21, 0 + .dw 0x47c3, 0xc414, 0x47cf, 0xc414, 0x21, 0 + .dw 0x47d1, 0xc414, 0x47d1, 0xc414, 0x21, 0 + .dw 0x47d3, 0xc414, 0x47ff, 0xc414, 0x21, 0 + .dw 0x4801, 0xc414, 0x4801, 0xc414, 0x21, 0 + .dw 0x4803, 0xc414, 0x480f, 0xc414, 0x21, 0 + .dw 0x4811, 0xc414, 0x4811, 0xc414, 0x21, 0 + .dw 0x4813, 0xc414, 0x483f, 0xc414, 0x21, 0 + .dw 0x4841, 0xc414, 0x4841, 0xc414, 0x21, 0 + .dw 0x4843, 0xc414, 0x484f, 0xc414, 0x21, 0 + .dw 0x4851, 0xc414, 0x4851, 0xc414, 0x21, 0 + .dw 0x4853, 0xc414, 0x487f, 0xc414, 0x21, 0 + .dw 0x4881, 0xc414, 0x4881, 0xc414, 0x21, 0 + .dw 0x4883, 0xc414, 0x488f, 0xc414, 0x21, 0 + .dw 0x4891, 0xc414, 0x4891, 0xc414, 0x21, 0 + .dw 0x4893, 0xc414, 0x48bf, 0xc414, 0x21, 0 + .dw 0x48c1, 0xc414, 0x48c1, 0xc414, 0x21, 0 + .dw 0x48c3, 0xc414, 0x48cf, 0xc414, 0x21, 0 + .dw 0x48d1, 0xc414, 0x48d1, 0xc414, 0x21, 0 + .dw 0x48d3, 0xc414, 0x48ff, 0xc414, 0x21, 0 + .dw 0x4901, 0xc414, 0x4901, 0xc414, 0x21, 0 + .dw 0x4903, 0xc414, 0x490f, 0xc414, 0x21, 0 + .dw 0x4911, 0xc414, 0x4911, 0xc414, 0x21, 0 + .dw 0x4913, 0xc414, 0x493f, 0xc414, 0x21, 0 + .dw 0x4941, 0xc414, 0x4941, 0xc414, 0x21, 0 + .dw 0x4943, 0xc414, 0x494f, 0xc414, 0x21, 0 + .dw 0x4951, 0xc414, 0x4951, 0xc414, 0x21, 0 + .dw 0x4953, 0xc414, 0x497f, 0xc414, 0x21, 0 + .dw 0x4981, 0xc414, 0x4981, 0xc414, 0x21, 0 + .dw 0x4983, 0xc414, 0x498f, 0xc414, 0x21, 0 + .dw 0x4991, 0xc414, 0x4991, 0xc414, 0x21, 0 + .dw 0x4993, 0xc414, 0x49bf, 0xc414, 0x21, 0 + .dw 0x49c1, 0xc414, 0x49c1, 0xc414, 0x21, 0 + .dw 0x49c3, 0xc414, 0x49cf, 0xc414, 0x21, 0 + .dw 0x49d1, 0xc414, 0x49d1, 0xc414, 0x21, 0 + .dw 0x49d3, 0xc414, 0x49ff, 0xc414, 0x21, 0 + .dw 0x4a01, 0xc414, 0x4a01, 0xc414, 0x21, 0 + .dw 0x4a03, 0xc414, 0x4a0f, 0xc414, 0x21, 0 + .dw 0x4a11, 0xc414, 0x4a11, 0xc414, 0x21, 0 + .dw 0x4a13, 0xc414, 0x4a3f, 0xc414, 0x21, 0 + .dw 0x4a41, 0xc414, 0x4a41, 0xc414, 0x21, 0 + .dw 0x4a43, 0xc414, 0x4a4f, 0xc414, 0x21, 0 + .dw 0x4a51, 0xc414, 0x4a51, 0xc414, 0x21, 0 + .dw 0x4a53, 0xc414, 0x4a7f, 0xc414, 0x21, 0 + .dw 0x4a81, 0xc414, 0x4a81, 0xc414, 0x21, 0 + .dw 0x4a83, 0xc414, 0x4a8f, 0xc414, 0x21, 0 + .dw 0x4a91, 0xc414, 0x4a91, 0xc414, 0x21, 0 + .dw 0x4a93, 0xc414, 0x4abf, 0xc414, 0x21, 0 + .dw 0x4ac1, 0xc414, 0x4ac1, 0xc414, 0x21, 0 + .dw 0x4ac3, 0xc414, 0x4acf, 0xc414, 0x21, 0 + .dw 0x4ad1, 0xc414, 0x4ad1, 0xc414, 0x21, 0 + .dw 0x4ad3, 0xc414, 0x4aff, 0xc414, 0x21, 0 + .dw 0x4b01, 0xc414, 0x4b01, 0xc414, 0x21, 0 + .dw 0x4b03, 0xc414, 0x4b0f, 0xc414, 0x21, 0 + .dw 0x4b11, 0xc414, 0x4b11, 0xc414, 0x21, 0 + .dw 0x4b13, 0xc414, 0x4b3f, 0xc414, 0x21, 0 + .dw 0x4b41, 0xc414, 0x4b41, 0xc414, 0x21, 0 + .dw 0x4b43, 0xc414, 0x4b4f, 0xc414, 0x21, 0 + .dw 0x4b51, 0xc414, 0x4b51, 0xc414, 0x21, 0 + .dw 0x4b53, 0xc414, 0x4b7f, 0xc414, 0x21, 0 + .dw 0x4b81, 0xc414, 0x4b81, 0xc414, 0x21, 0 + .dw 0x4b83, 0xc414, 0x4b8f, 0xc414, 0x21, 0 + .dw 0x4b91, 0xc414, 0x4b91, 0xc414, 0x21, 0 + .dw 0x4b93, 0xc414, 0x4bbf, 0xc414, 0x21, 0 + .dw 0x4bc1, 0xc414, 0x4bc1, 0xc414, 0x21, 0 + .dw 0x4bc3, 0xc414, 0x4bcf, 0xc414, 0x21, 0 + .dw 0x4bd1, 0xc414, 0x4bd1, 0xc414, 0x21, 0 + .dw 0x4bd3, 0xc414, 0x4bff, 0xc414, 0x21, 0 + .dw 0x4c01, 0xc414, 0x4c01, 0xc414, 0x21, 0 + .dw 0x4c03, 0xc414, 0x4c0f, 0xc414, 0x21, 0 + .dw 0x4c11, 0xc414, 0x4c11, 0xc414, 0x21, 0 + .dw 0x4c13, 0xc414, 0x4c3f, 0xc414, 0x21, 0 + .dw 0x4c41, 0xc414, 0x4c41, 0xc414, 0x21, 0 + .dw 0x4c43, 0xc414, 0x4c4f, 0xc414, 0x21, 0 + .dw 0x4c51, 0xc414, 0x4c51, 0xc414, 0x21, 0 + .dw 0x4c53, 0xc414, 0x4c7f, 0xc414, 0x21, 0 + .dw 0x4c81, 0xc414, 0x4c81, 0xc414, 0x21, 0 + .dw 0x4c83, 0xc414, 0x4c8f, 0xc414, 0x21, 0 + .dw 0x4c91, 0xc414, 0x4c91, 0xc414, 0x21, 0 + .dw 0x4c93, 0xc414, 0x4cbf, 0xc414, 0x21, 0 + .dw 0x4cc1, 0xc414, 0x4cc1, 0xc414, 0x21, 0 + .dw 0x4cc3, 0xc414, 0x4ccf, 0xc414, 0x21, 0 + .dw 0x4cd1, 0xc414, 0x4cd1, 0xc414, 0x21, 0 + .dw 0x4cd3, 0xc414, 0x4cff, 0xc414, 0x21, 0 + .dw 0x4d01, 0xc414, 0x4d01, 0xc414, 0x21, 0 + .dw 0x4d03, 0xc414, 0x4d0f, 0xc414, 0x21, 0 + .dw 0x4d11, 0xc414, 0x4d11, 0xc414, 0x21, 0 + .dw 0x4d13, 0xc414, 0x4d3f, 0xc414, 0x21, 0 + .dw 0x4d41, 0xc414, 0x4d41, 0xc414, 0x21, 0 + .dw 0x4d43, 0xc414, 0x4d4f, 0xc414, 0x21, 0 + .dw 0x4d51, 0xc414, 0x4d51, 0xc414, 0x21, 0 + .dw 0x4d53, 0xc414, 0x4d7f, 0xc414, 0x21, 0 + .dw 0x4d81, 0xc414, 0x4d81, 0xc414, 0x21, 0 + .dw 0x4d83, 0xc414, 0x4d8f, 0xc414, 0x21, 0 + .dw 0x4d91, 0xc414, 0x4d91, 0xc414, 0x21, 0 + .dw 0x4d93, 0xc414, 0x4dbf, 0xc414, 0x21, 0 + .dw 0x4dc1, 0xc414, 0x4dc1, 0xc414, 0x21, 0 + .dw 0x4dc3, 0xc414, 0x4dcf, 0xc414, 0x21, 0 + .dw 0x4dd1, 0xc414, 0x4dd1, 0xc414, 0x21, 0 + .dw 0x4dd3, 0xc414, 0x4dff, 0xc414, 0x21, 0 + .dw 0x4e01, 0xc414, 0x4e01, 0xc414, 0x21, 0 + .dw 0x4e03, 0xc414, 0x4e0f, 0xc414, 0x21, 0 + .dw 0x4e11, 0xc414, 0x4e11, 0xc414, 0x21, 0 + .dw 0x4e13, 0xc414, 0x4e3f, 0xc414, 0x21, 0 + .dw 0x4e41, 0xc414, 0x4e41, 0xc414, 0x21, 0 + .dw 0x4e43, 0xc414, 0x4e4f, 0xc414, 0x21, 0 + .dw 0x4e51, 0xc414, 0x4e51, 0xc414, 0x21, 0 + .dw 0x4e53, 0xc414, 0x4e7f, 0xc414, 0x21, 0 + .dw 0x4e81, 0xc414, 0x4e81, 0xc414, 0x21, 0 + .dw 0x4e83, 0xc414, 0x4e8f, 0xc414, 0x21, 0 + .dw 0x4e91, 0xc414, 0x4e91, 0xc414, 0x21, 0 + .dw 0x4e93, 0xc414, 0x4ebf, 0xc414, 0x21, 0 + .dw 0x4ec1, 0xc414, 0x4ec1, 0xc414, 0x21, 0 + .dw 0x4ec3, 0xc414, 0x4ecf, 0xc414, 0x21, 0 + .dw 0x4ed1, 0xc414, 0x4ed1, 0xc414, 0x21, 0 + .dw 0x4ed3, 0xc414, 0x4eff, 0xc414, 0x21, 0 + .dw 0x4f01, 0xc414, 0x4f01, 0xc414, 0x21, 0 + .dw 0x4f03, 0xc414, 0x4f0f, 0xc414, 0x21, 0 + .dw 0x4f11, 0xc414, 0x4f11, 0xc414, 0x21, 0 + .dw 0x4f13, 0xc414, 0x4f3f, 0xc414, 0x21, 0 + .dw 0x4f41, 0xc414, 0x4f41, 0xc414, 0x21, 0 + .dw 0x4f43, 0xc414, 0x4f4f, 0xc414, 0x21, 0 + .dw 0x4f51, 0xc414, 0x4f51, 0xc414, 0x21, 0 + .dw 0x4f53, 0xc414, 0x4f7f, 0xc414, 0x21, 0 + .dw 0x4f81, 0xc414, 0x4f81, 0xc414, 0x21, 0 + .dw 0x4f83, 0xc414, 0x4f8f, 0xc414, 0x21, 0 + .dw 0x4f91, 0xc414, 0x4f91, 0xc414, 0x21, 0 + .dw 0x4f93, 0xc414, 0x4fbf, 0xc414, 0x21, 0 + .dw 0x4fc1, 0xc414, 0x4fc1, 0xc414, 0x21, 0 + .dw 0x4fc3, 0xc414, 0x4fcf, 0xc414, 0x21, 0 + .dw 0x4fd1, 0xc414, 0x4fd1, 0xc414, 0x21, 0 + .dw 0x4fd3, 0xc414, 0x5fff, 0xc414, 0x21, 0 + .dw 0x6001, 0xc414, 0x6001, 0xc414, 0x21, 0 + .dw 0x6003, 0xc414, 0x600f, 0xc414, 0x21, 0 + .dw 0x6011, 0xc414, 0x6011, 0xc414, 0x21, 0 + .dw 0x6013, 0xc414, 0x603f, 0xc414, 0x21, 0 + .dw 0x6041, 0xc414, 0x6041, 0xc414, 0x21, 0 + .dw 0x6043, 0xc414, 0x604f, 0xc414, 0x21, 0 + .dw 0x6051, 0xc414, 0x6051, 0xc414, 0x21, 0 + .dw 0x6053, 0xc414, 0x607f, 0xc414, 0x21, 0 + .dw 0x6081, 0xc414, 0x6081, 0xc414, 0x21, 0 + .dw 0x6083, 0xc414, 0x608f, 0xc414, 0x21, 0 + .dw 0x6091, 0xc414, 0x6091, 0xc414, 0x21, 0 + .dw 0x6093, 0xc414, 0x60bf, 0xc414, 0x21, 0 + .dw 0x60c1, 0xc414, 0x60c1, 0xc414, 0x21, 0 + .dw 0x60c3, 0xc414, 0x60cf, 0xc414, 0x21, 0 + .dw 0x60d1, 0xc414, 0x60d1, 0xc414, 0x21, 0 + .dw 0x60d3, 0xc414, 0x60ff, 0xc414, 0x21, 0 + .dw 0x6101, 0xc414, 0x6101, 0xc414, 0x21, 0 + .dw 0x6103, 0xc414, 0x610f, 0xc414, 0x21, 0 + .dw 0x6111, 0xc414, 0x6111, 0xc414, 0x21, 0 + .dw 0x6113, 0xc414, 0x613f, 0xc414, 0x21, 0 + .dw 0x6141, 0xc414, 0x6141, 0xc414, 0x21, 0 + .dw 0x6143, 0xc414, 0x614f, 0xc414, 0x21, 0 + .dw 0x6151, 0xc414, 0x6151, 0xc414, 0x21, 0 + .dw 0x6153, 0xc414, 0x617f, 0xc414, 0x21, 0 + .dw 0x6181, 0xc414, 0x6181, 0xc414, 0x21, 0 + .dw 0x6183, 0xc414, 0x618f, 0xc414, 0x21, 0 + .dw 0x6191, 0xc414, 0x6191, 0xc414, 0x21, 0 + .dw 0x6193, 0xc414, 0x61bf, 0xc414, 0x21, 0 + .dw 0x61c1, 0xc414, 0x61c1, 0xc414, 0x21, 0 + .dw 0x61c3, 0xc414, 0x61cf, 0xc414, 0x21, 0 + .dw 0x61d1, 0xc414, 0x61d1, 0xc414, 0x21, 0 + .dw 0x61d3, 0xc414, 0x61ff, 0xc414, 0x21, 0 + .dw 0x6201, 0xc414, 0x6201, 0xc414, 0x21, 0 + .dw 0x6203, 0xc414, 0x620f, 0xc414, 0x21, 0 + .dw 0x6211, 0xc414, 0x6211, 0xc414, 0x21, 0 + .dw 0x6213, 0xc414, 0x623f, 0xc414, 0x21, 0 + .dw 0x6241, 0xc414, 0x6241, 0xc414, 0x21, 0 + .dw 0x6243, 0xc414, 0x624f, 0xc414, 0x21, 0 + .dw 0x6251, 0xc414, 0x6251, 0xc414, 0x21, 0 + .dw 0x6253, 0xc414, 0x627f, 0xc414, 0x21, 0 + .dw 0x6281, 0xc414, 0x6281, 0xc414, 0x21, 0 + .dw 0x6283, 0xc414, 0x628f, 0xc414, 0x21, 0 + .dw 0x6291, 0xc414, 0x6291, 0xc414, 0x21, 0 + .dw 0x6293, 0xc414, 0x62bf, 0xc414, 0x21, 0 + .dw 0x62c1, 0xc414, 0x62c1, 0xc414, 0x21, 0 + .dw 0x62c3, 0xc414, 0x62cf, 0xc414, 0x21, 0 + .dw 0x62d1, 0xc414, 0x62d1, 0xc414, 0x21, 0 + .dw 0x62d3, 0xc414, 0x62ff, 0xc414, 0x21, 0 + .dw 0x6301, 0xc414, 0x6301, 0xc414, 0x21, 0 + .dw 0x6303, 0xc414, 0x630f, 0xc414, 0x21, 0 + .dw 0x6311, 0xc414, 0x6311, 0xc414, 0x21, 0 + .dw 0x6313, 0xc414, 0x633f, 0xc414, 0x21, 0 + .dw 0x6341, 0xc414, 0x6341, 0xc414, 0x21, 0 + .dw 0x6343, 0xc414, 0x634f, 0xc414, 0x21, 0 + .dw 0x6351, 0xc414, 0x6351, 0xc414, 0x21, 0 + .dw 0x6353, 0xc414, 0x637f, 0xc414, 0x21, 0 + .dw 0x6381, 0xc414, 0x6381, 0xc414, 0x21, 0 + .dw 0x6383, 0xc414, 0x638f, 0xc414, 0x21, 0 + .dw 0x6391, 0xc414, 0x6391, 0xc414, 0x21, 0 + .dw 0x6393, 0xc414, 0x63bf, 0xc414, 0x21, 0 + .dw 0x63c1, 0xc414, 0x63c1, 0xc414, 0x21, 0 + .dw 0x63c3, 0xc414, 0x63cf, 0xc414, 0x21, 0 + .dw 0x63d1, 0xc414, 0x63d1, 0xc414, 0x21, 0 + .dw 0x63d3, 0xc414, 0x63ff, 0xc414, 0x21, 0 + .dw 0x6401, 0xc414, 0x6401, 0xc414, 0x21, 0 + .dw 0x6403, 0xc414, 0x640f, 0xc414, 0x21, 0 + .dw 0x6411, 0xc414, 0x6411, 0xc414, 0x21, 0 + .dw 0x6413, 0xc414, 0x643f, 0xc414, 0x21, 0 + .dw 0x6441, 0xc414, 0x6441, 0xc414, 0x21, 0 + .dw 0x6443, 0xc414, 0x644f, 0xc414, 0x21, 0 + .dw 0x6451, 0xc414, 0x6451, 0xc414, 0x21, 0 + .dw 0x6453, 0xc414, 0x647f, 0xc414, 0x21, 0 + .dw 0x6481, 0xc414, 0x6481, 0xc414, 0x21, 0 + .dw 0x6483, 0xc414, 0x648f, 0xc414, 0x21, 0 + .dw 0x6491, 0xc414, 0x6491, 0xc414, 0x21, 0 + .dw 0x6493, 0xc414, 0x64bf, 0xc414, 0x21, 0 + .dw 0x64c1, 0xc414, 0x64c1, 0xc414, 0x21, 0 + .dw 0x64c3, 0xc414, 0x64cf, 0xc414, 0x21, 0 + .dw 0x64d1, 0xc414, 0x64d1, 0xc414, 0x21, 0 + .dw 0x64d3, 0xc414, 0x64ff, 0xc414, 0x21, 0 + .dw 0x6501, 0xc414, 0x6501, 0xc414, 0x21, 0 + .dw 0x6503, 0xc414, 0x650f, 0xc414, 0x21, 0 + .dw 0x6511, 0xc414, 0x6511, 0xc414, 0x21, 0 + .dw 0x6513, 0xc414, 0x653f, 0xc414, 0x21, 0 + .dw 0x6541, 0xc414, 0x6541, 0xc414, 0x21, 0 + .dw 0x6543, 0xc414, 0x654f, 0xc414, 0x21, 0 + .dw 0x6551, 0xc414, 0x6551, 0xc414, 0x21, 0 + .dw 0x6553, 0xc414, 0x657f, 0xc414, 0x21, 0 + .dw 0x6581, 0xc414, 0x6581, 0xc414, 0x21, 0 + .dw 0x6583, 0xc414, 0x658f, 0xc414, 0x21, 0 + .dw 0x6591, 0xc414, 0x6591, 0xc414, 0x21, 0 + .dw 0x6593, 0xc414, 0x65bf, 0xc414, 0x21, 0 + .dw 0x65c1, 0xc414, 0x65c1, 0xc414, 0x21, 0 + .dw 0x65c3, 0xc414, 0x65cf, 0xc414, 0x21, 0 + .dw 0x65d1, 0xc414, 0x65d1, 0xc414, 0x21, 0 + .dw 0x65d3, 0xc414, 0x65ff, 0xc414, 0x21, 0 + .dw 0x6601, 0xc414, 0x6601, 0xc414, 0x21, 0 + .dw 0x6603, 0xc414, 0x660f, 0xc414, 0x21, 0 + .dw 0x6611, 0xc414, 0x6611, 0xc414, 0x21, 0 + .dw 0x6613, 0xc414, 0x663f, 0xc414, 0x21, 0 + .dw 0x6641, 0xc414, 0x6641, 0xc414, 0x21, 0 + .dw 0x6643, 0xc414, 0x664f, 0xc414, 0x21, 0 + .dw 0x6651, 0xc414, 0x6651, 0xc414, 0x21, 0 + .dw 0x6653, 0xc414, 0x667f, 0xc414, 0x21, 0 + .dw 0x6681, 0xc414, 0x6681, 0xc414, 0x21, 0 + .dw 0x6683, 0xc414, 0x668f, 0xc414, 0x21, 0 + .dw 0x6691, 0xc414, 0x6691, 0xc414, 0x21, 0 + .dw 0x6693, 0xc414, 0x66bf, 0xc414, 0x21, 0 + .dw 0x66c1, 0xc414, 0x66c1, 0xc414, 0x21, 0 + .dw 0x66c3, 0xc414, 0x66cf, 0xc414, 0x21, 0 + .dw 0x66d1, 0xc414, 0x66d1, 0xc414, 0x21, 0 + .dw 0x66d3, 0xc414, 0x66ff, 0xc414, 0x21, 0 + .dw 0x6701, 0xc414, 0x6701, 0xc414, 0x21, 0 + .dw 0x6703, 0xc414, 0x670f, 0xc414, 0x21, 0 + .dw 0x6711, 0xc414, 0x6711, 0xc414, 0x21, 0 + .dw 0x6713, 0xc414, 0x673f, 0xc414, 0x21, 0 + .dw 0x6741, 0xc414, 0x6741, 0xc414, 0x21, 0 + .dw 0x6743, 0xc414, 0x674f, 0xc414, 0x21, 0 + .dw 0x6751, 0xc414, 0x6751, 0xc414, 0x21, 0 + .dw 0x6753, 0xc414, 0x677f, 0xc414, 0x21, 0 + .dw 0x6781, 0xc414, 0x6781, 0xc414, 0x21, 0 + .dw 0x6783, 0xc414, 0x678f, 0xc414, 0x21, 0 + .dw 0x6791, 0xc414, 0x6791, 0xc414, 0x21, 0 + .dw 0x6793, 0xc414, 0x67bf, 0xc414, 0x21, 0 + .dw 0x67c1, 0xc414, 0x67c1, 0xc414, 0x21, 0 + .dw 0x67c3, 0xc414, 0x67cf, 0xc414, 0x21, 0 + .dw 0x67d1, 0xc414, 0x67d1, 0xc414, 0x21, 0 + .dw 0x67d3, 0xc414, 0x67ff, 0xc414, 0x21, 0 + .dw 0x6801, 0xc414, 0x6801, 0xc414, 0x21, 0 + .dw 0x6803, 0xc414, 0x680f, 0xc414, 0x21, 0 + .dw 0x6811, 0xc414, 0x6811, 0xc414, 0x21, 0 + .dw 0x6813, 0xc414, 0x683f, 0xc414, 0x21, 0 + .dw 0x6841, 0xc414, 0x6841, 0xc414, 0x21, 0 + .dw 0x6843, 0xc414, 0x684f, 0xc414, 0x21, 0 + .dw 0x6851, 0xc414, 0x6851, 0xc414, 0x21, 0 + .dw 0x6853, 0xc414, 0x687f, 0xc414, 0x21, 0 + .dw 0x6881, 0xc414, 0x6881, 0xc414, 0x21, 0 + .dw 0x6883, 0xc414, 0x688f, 0xc414, 0x21, 0 + .dw 0x6891, 0xc414, 0x6891, 0xc414, 0x21, 0 + .dw 0x6893, 0xc414, 0x68bf, 0xc414, 0x21, 0 + .dw 0x68c1, 0xc414, 0x68c1, 0xc414, 0x21, 0 + .dw 0x68c3, 0xc414, 0x68cf, 0xc414, 0x21, 0 + .dw 0x68d1, 0xc414, 0x68d1, 0xc414, 0x21, 0 + .dw 0x68d3, 0xc414, 0x68ff, 0xc414, 0x21, 0 + .dw 0x6901, 0xc414, 0x6901, 0xc414, 0x21, 0 + .dw 0x6903, 0xc414, 0x690f, 0xc414, 0x21, 0 + .dw 0x6911, 0xc414, 0x6911, 0xc414, 0x21, 0 + .dw 0x6913, 0xc414, 0x693f, 0xc414, 0x21, 0 + .dw 0x6941, 0xc414, 0x6941, 0xc414, 0x21, 0 + .dw 0x6943, 0xc414, 0x694f, 0xc414, 0x21, 0 + .dw 0x6951, 0xc414, 0x6951, 0xc414, 0x21, 0 + .dw 0x6953, 0xc414, 0x697f, 0xc414, 0x21, 0 + .dw 0x6981, 0xc414, 0x6981, 0xc414, 0x21, 0 + .dw 0x6983, 0xc414, 0x698f, 0xc414, 0x21, 0 + .dw 0x6991, 0xc414, 0x6991, 0xc414, 0x21, 0 + .dw 0x6993, 0xc414, 0x69bf, 0xc414, 0x21, 0 + .dw 0x69c1, 0xc414, 0x69c1, 0xc414, 0x21, 0 + .dw 0x69c3, 0xc414, 0x69cf, 0xc414, 0x21, 0 + .dw 0x69d1, 0xc414, 0x69d1, 0xc414, 0x21, 0 + .dw 0x69d3, 0xc414, 0x69ff, 0xc414, 0x21, 0 + .dw 0x6a01, 0xc414, 0x6a01, 0xc414, 0x21, 0 + .dw 0x6a03, 0xc414, 0x6a0f, 0xc414, 0x21, 0 + .dw 0x6a11, 0xc414, 0x6a11, 0xc414, 0x21, 0 + .dw 0x6a13, 0xc414, 0x6a3f, 0xc414, 0x21, 0 + .dw 0x6a41, 0xc414, 0x6a41, 0xc414, 0x21, 0 + .dw 0x6a43, 0xc414, 0x6a4f, 0xc414, 0x21, 0 + .dw 0x6a51, 0xc414, 0x6a51, 0xc414, 0x21, 0 + .dw 0x6a53, 0xc414, 0x6a7f, 0xc414, 0x21, 0 + .dw 0x6a81, 0xc414, 0x6a81, 0xc414, 0x21, 0 + .dw 0x6a83, 0xc414, 0x6a8f, 0xc414, 0x21, 0 + .dw 0x6a91, 0xc414, 0x6a91, 0xc414, 0x21, 0 + .dw 0x6a93, 0xc414, 0x6abf, 0xc414, 0x21, 0 + .dw 0x6ac1, 0xc414, 0x6ac1, 0xc414, 0x21, 0 + .dw 0x6ac3, 0xc414, 0x6acf, 0xc414, 0x21, 0 + .dw 0x6ad1, 0xc414, 0x6ad1, 0xc414, 0x21, 0 + .dw 0x6ad3, 0xc414, 0x6aff, 0xc414, 0x21, 0 + .dw 0x6b01, 0xc414, 0x6b01, 0xc414, 0x21, 0 + .dw 0x6b03, 0xc414, 0x6b0f, 0xc414, 0x21, 0 + .dw 0x6b11, 0xc414, 0x6b11, 0xc414, 0x21, 0 + .dw 0x6b13, 0xc414, 0x6b3f, 0xc414, 0x21, 0 + .dw 0x6b41, 0xc414, 0x6b41, 0xc414, 0x21, 0 + .dw 0x6b43, 0xc414, 0x6b4f, 0xc414, 0x21, 0 + .dw 0x6b51, 0xc414, 0x6b51, 0xc414, 0x21, 0 + .dw 0x6b53, 0xc414, 0x6b7f, 0xc414, 0x21, 0 + .dw 0x6b81, 0xc414, 0x6b81, 0xc414, 0x21, 0 + .dw 0x6b83, 0xc414, 0x6b8f, 0xc414, 0x21, 0 + .dw 0x6b91, 0xc414, 0x6b91, 0xc414, 0x21, 0 + .dw 0x6b93, 0xc414, 0x6bbf, 0xc414, 0x21, 0 + .dw 0x6bc1, 0xc414, 0x6bc1, 0xc414, 0x21, 0 + .dw 0x6bc3, 0xc414, 0x6bcf, 0xc414, 0x21, 0 + .dw 0x6bd1, 0xc414, 0x6bd1, 0xc414, 0x21, 0 + .dw 0x6bd3, 0xc414, 0x6bff, 0xc414, 0x21, 0 + .dw 0x6c01, 0xc414, 0x6c01, 0xc414, 0x21, 0 + .dw 0x6c03, 0xc414, 0x6c0f, 0xc414, 0x21, 0 + .dw 0x6c11, 0xc414, 0x6c11, 0xc414, 0x21, 0 + .dw 0x6c13, 0xc414, 0x6c3f, 0xc414, 0x21, 0 + .dw 0x6c41, 0xc414, 0x6c41, 0xc414, 0x21, 0 + .dw 0x6c43, 0xc414, 0x6c4f, 0xc414, 0x21, 0 + .dw 0x6c51, 0xc414, 0x6c51, 0xc414, 0x21, 0 + .dw 0x6c53, 0xc414, 0x6c7f, 0xc414, 0x21, 0 + .dw 0x6c81, 0xc414, 0x6c81, 0xc414, 0x21, 0 + .dw 0x6c83, 0xc414, 0x6c8f, 0xc414, 0x21, 0 + .dw 0x6c91, 0xc414, 0x6c91, 0xc414, 0x21, 0 + .dw 0x6c93, 0xc414, 0x6cbf, 0xc414, 0x21, 0 + .dw 0x6cc1, 0xc414, 0x6cc1, 0xc414, 0x21, 0 + .dw 0x6cc3, 0xc414, 0x6ccf, 0xc414, 0x21, 0 + .dw 0x6cd1, 0xc414, 0x6cd1, 0xc414, 0x21, 0 + .dw 0x6cd3, 0xc414, 0x6cff, 0xc414, 0x21, 0 + .dw 0x6d01, 0xc414, 0x6d01, 0xc414, 0x21, 0 + .dw 0x6d03, 0xc414, 0x6d0f, 0xc414, 0x21, 0 + .dw 0x6d11, 0xc414, 0x6d11, 0xc414, 0x21, 0 + .dw 0x6d13, 0xc414, 0x6d3f, 0xc414, 0x21, 0 + .dw 0x6d41, 0xc414, 0x6d41, 0xc414, 0x21, 0 + .dw 0x6d43, 0xc414, 0x6d4f, 0xc414, 0x21, 0 + .dw 0x6d51, 0xc414, 0x6d51, 0xc414, 0x21, 0 + .dw 0x6d53, 0xc414, 0x6d7f, 0xc414, 0x21, 0 + .dw 0x6d81, 0xc414, 0x6d81, 0xc414, 0x21, 0 + .dw 0x6d83, 0xc414, 0x6d8f, 0xc414, 0x21, 0 + .dw 0x6d91, 0xc414, 0x6d91, 0xc414, 0x21, 0 + .dw 0x6d93, 0xc414, 0x6dbf, 0xc414, 0x21, 0 + .dw 0x6dc1, 0xc414, 0x6dc1, 0xc414, 0x21, 0 + .dw 0x6dc3, 0xc414, 0x6dcf, 0xc414, 0x21, 0 + .dw 0x6dd1, 0xc414, 0x6dd1, 0xc414, 0x21, 0 + .dw 0x6dd3, 0xc414, 0x6dff, 0xc414, 0x21, 0 + .dw 0x6e01, 0xc414, 0x6e01, 0xc414, 0x21, 0 + .dw 0x6e03, 0xc414, 0x6e0f, 0xc414, 0x21, 0 + .dw 0x6e11, 0xc414, 0x6e11, 0xc414, 0x21, 0 + .dw 0x6e13, 0xc414, 0x6e3f, 0xc414, 0x21, 0 + .dw 0x6e41, 0xc414, 0x6e41, 0xc414, 0x21, 0 + .dw 0x6e43, 0xc414, 0x6e4f, 0xc414, 0x21, 0 + .dw 0x6e51, 0xc414, 0x6e51, 0xc414, 0x21, 0 + .dw 0x6e53, 0xc414, 0x6e7f, 0xc414, 0x21, 0 + .dw 0x6e81, 0xc414, 0x6e81, 0xc414, 0x21, 0 + .dw 0x6e83, 0xc414, 0x6e8f, 0xc414, 0x21, 0 + .dw 0x6e91, 0xc414, 0x6e91, 0xc414, 0x21, 0 + .dw 0x6e93, 0xc414, 0x6ebf, 0xc414, 0x21, 0 + .dw 0x6ec1, 0xc414, 0x6ec1, 0xc414, 0x21, 0 + .dw 0x6ec3, 0xc414, 0x6ecf, 0xc414, 0x21, 0 + .dw 0x6ed1, 0xc414, 0x6ed1, 0xc414, 0x21, 0 + .dw 0x6ed3, 0xc414, 0x6eff, 0xc414, 0x21, 0 + .dw 0x6f01, 0xc414, 0x6f01, 0xc414, 0x21, 0 + .dw 0x6f03, 0xc414, 0x6f0f, 0xc414, 0x21, 0 + .dw 0x6f11, 0xc414, 0x6f11, 0xc414, 0x21, 0 + .dw 0x6f13, 0xc414, 0x6f3f, 0xc414, 0x21, 0 + .dw 0x6f41, 0xc414, 0x6f41, 0xc414, 0x21, 0 + .dw 0x6f43, 0xc414, 0x6f4f, 0xc414, 0x21, 0 + .dw 0x6f51, 0xc414, 0x6f51, 0xc414, 0x21, 0 + .dw 0x6f53, 0xc414, 0x6f7f, 0xc414, 0x21, 0 + .dw 0x6f81, 0xc414, 0x6f81, 0xc414, 0x21, 0 + .dw 0x6f83, 0xc414, 0x6f8f, 0xc414, 0x21, 0 + .dw 0x6f91, 0xc414, 0x6f91, 0xc414, 0x21, 0 + .dw 0x6f93, 0xc414, 0x6fbf, 0xc414, 0x21, 0 + .dw 0x6fc1, 0xc414, 0x6fc1, 0xc414, 0x21, 0 + .dw 0x6fc3, 0xc414, 0x6fcf, 0xc414, 0x21, 0 + .dw 0x6fd1, 0xc414, 0x6fd1, 0xc414, 0x21, 0 + .dw 0x6fd3, 0xc414, 0xffff, 0xc414, 0x21, 0 + .dw 0x0000, 0xc415, 0x0000, 0xc415, 0x22, 0 + .dw 0x0001, 0xc415, 0x0001, 0xc415, 0x21, 0 + .dw 0x0002, 0xc415, 0x0002, 0xc415, 0x22, 0 + .dw 0x0003, 0xc415, 0x000f, 0xc415, 0x21, 0 + .dw 0x0010, 0xc415, 0x0010, 0xc415, 0x22, 0 + .dw 0x0011, 0xc415, 0x0011, 0xc415, 0x21, 0 + .dw 0x0012, 0xc415, 0x0012, 0xc415, 0x22, 0 + .dw 0x0013, 0xc415, 0x003f, 0xc415, 0x21, 0 + .dw 0x0041, 0xc415, 0x0041, 0xc415, 0x21, 0 + .dw 0x0043, 0xc415, 0x004f, 0xc415, 0x21, 0 + .dw 0x0051, 0xc415, 0x0051, 0xc415, 0x21, 0 + .dw 0x0053, 0xc415, 0x007f, 0xc415, 0x21, 0 + .dw 0x0081, 0xc415, 0x0081, 0xc415, 0x21, 0 + .dw 0x0083, 0xc415, 0x008f, 0xc415, 0x21, 0 + .dw 0x0091, 0xc415, 0x0091, 0xc415, 0x21, 0 + .dw 0x0093, 0xc415, 0x00bf, 0xc415, 0x21, 0 + .dw 0x00c1, 0xc415, 0x00c1, 0xc415, 0x21, 0 + .dw 0x00c3, 0xc415, 0x00cf, 0xc415, 0x21, 0 + .dw 0x00d1, 0xc415, 0x00d1, 0xc415, 0x21, 0 + .dw 0x00d3, 0xc415, 0x00ff, 0xc415, 0x21, 0 + .dw 0x0101, 0xc415, 0x0101, 0xc415, 0x21, 0 + .dw 0x0103, 0xc415, 0x010f, 0xc415, 0x21, 0 + .dw 0x0111, 0xc415, 0x0111, 0xc415, 0x21, 0 + .dw 0x0113, 0xc415, 0x013f, 0xc415, 0x21, 0 + .dw 0x0141, 0xc415, 0x0141, 0xc415, 0x21, 0 + .dw 0x0143, 0xc415, 0x014f, 0xc415, 0x21, 0 + .dw 0x0151, 0xc415, 0x0151, 0xc415, 0x21, 0 + .dw 0x0153, 0xc415, 0x017f, 0xc415, 0x21, 0 + .dw 0x0181, 0xc415, 0x0181, 0xc415, 0x21, 0 + .dw 0x0183, 0xc415, 0x018f, 0xc415, 0x21, 0 + .dw 0x0191, 0xc415, 0x0191, 0xc415, 0x21, 0 + .dw 0x0193, 0xc415, 0x01bf, 0xc415, 0x21, 0 + .dw 0x01c1, 0xc415, 0x01c1, 0xc415, 0x21, 0 + .dw 0x01c3, 0xc415, 0x01cf, 0xc415, 0x21, 0 + .dw 0x01d1, 0xc415, 0x01d1, 0xc415, 0x21, 0 + .dw 0x01d3, 0xc415, 0x01ff, 0xc415, 0x21, 0 + .dw 0x0201, 0xc415, 0x0201, 0xc415, 0x21, 0 + .dw 0x0203, 0xc415, 0x020f, 0xc415, 0x21, 0 + .dw 0x0211, 0xc415, 0x0211, 0xc415, 0x21, 0 + .dw 0x0213, 0xc415, 0x023f, 0xc415, 0x21, 0 + .dw 0x0240, 0xc415, 0x0240, 0xc415, 0x22, 0 + .dw 0x0241, 0xc415, 0x0241, 0xc415, 0x21, 0 + .dw 0x0242, 0xc415, 0x0242, 0xc415, 0x22, 0 + .dw 0x0243, 0xc415, 0x024f, 0xc415, 0x21, 0 + .dw 0x0250, 0xc415, 0x0250, 0xc415, 0x22, 0 + .dw 0x0251, 0xc415, 0x0251, 0xc415, 0x21, 0 + .dw 0x0252, 0xc415, 0x0252, 0xc415, 0x22, 0 + .dw 0x0253, 0xc415, 0x027f, 0xc415, 0x21, 0 + .dw 0x0281, 0xc415, 0x0281, 0xc415, 0x21, 0 + .dw 0x0283, 0xc415, 0x028f, 0xc415, 0x21, 0 + .dw 0x0291, 0xc415, 0x0291, 0xc415, 0x21, 0 + .dw 0x0293, 0xc415, 0x02bf, 0xc415, 0x21, 0 + .dw 0x02c1, 0xc415, 0x02c1, 0xc415, 0x21, 0 + .dw 0x02c3, 0xc415, 0x02cf, 0xc415, 0x21, 0 + .dw 0x02d1, 0xc415, 0x02d1, 0xc415, 0x21, 0 + .dw 0x02d3, 0xc415, 0x02ff, 0xc415, 0x21, 0 + .dw 0x0301, 0xc415, 0x0301, 0xc415, 0x21, 0 + .dw 0x0303, 0xc415, 0x030f, 0xc415, 0x21, 0 + .dw 0x0311, 0xc415, 0x0311, 0xc415, 0x21, 0 + .dw 0x0313, 0xc415, 0x033f, 0xc415, 0x21, 0 + .dw 0x0341, 0xc415, 0x0341, 0xc415, 0x21, 0 + .dw 0x0343, 0xc415, 0x034f, 0xc415, 0x21, 0 + .dw 0x0351, 0xc415, 0x0351, 0xc415, 0x21, 0 + .dw 0x0353, 0xc415, 0x037f, 0xc415, 0x21, 0 + .dw 0x0381, 0xc415, 0x0381, 0xc415, 0x21, 0 + .dw 0x0383, 0xc415, 0x038f, 0xc415, 0x21, 0 + .dw 0x0391, 0xc415, 0x0391, 0xc415, 0x21, 0 + .dw 0x0393, 0xc415, 0x03bf, 0xc415, 0x21, 0 + .dw 0x03c1, 0xc415, 0x03c1, 0xc415, 0x21, 0 + .dw 0x03c3, 0xc415, 0x03cf, 0xc415, 0x21, 0 + .dw 0x03d1, 0xc415, 0x03d1, 0xc415, 0x21, 0 + .dw 0x03d3, 0xc415, 0x03ff, 0xc415, 0x21, 0 + .dw 0x0401, 0xc415, 0x0401, 0xc415, 0x21, 0 + .dw 0x0403, 0xc415, 0x040f, 0xc415, 0x21, 0 + .dw 0x0411, 0xc415, 0x0411, 0xc415, 0x21, 0 + .dw 0x0413, 0xc415, 0x043f, 0xc415, 0x21, 0 + .dw 0x0441, 0xc415, 0x0441, 0xc415, 0x21, 0 + .dw 0x0443, 0xc415, 0x044f, 0xc415, 0x21, 0 + .dw 0x0451, 0xc415, 0x0451, 0xc415, 0x21, 0 + .dw 0x0453, 0xc415, 0x047f, 0xc415, 0x21, 0 + .dw 0x0480, 0xc415, 0x0480, 0xc415, 0x22, 0 + .dw 0x0481, 0xc415, 0x0481, 0xc415, 0x21, 0 + .dw 0x0482, 0xc415, 0x0482, 0xc415, 0x22, 0 + .dw 0x0483, 0xc415, 0x048f, 0xc415, 0x21, 0 + .dw 0x0490, 0xc415, 0x0490, 0xc415, 0x22, 0 + .dw 0x0491, 0xc415, 0x0491, 0xc415, 0x21, 0 + .dw 0x0492, 0xc415, 0x0492, 0xc415, 0x22, 0 + .dw 0x0493, 0xc415, 0x04bf, 0xc415, 0x21, 0 + .dw 0x04c1, 0xc415, 0x04c1, 0xc415, 0x21, 0 + .dw 0x04c3, 0xc415, 0x04cf, 0xc415, 0x21, 0 + .dw 0x04d1, 0xc415, 0x04d1, 0xc415, 0x21, 0 + .dw 0x04d3, 0xc415, 0x04ff, 0xc415, 0x21, 0 + .dw 0x0501, 0xc415, 0x0501, 0xc415, 0x21, 0 + .dw 0x0503, 0xc415, 0x050f, 0xc415, 0x21, 0 + .dw 0x0511, 0xc415, 0x0511, 0xc415, 0x21, 0 + .dw 0x0513, 0xc415, 0x053f, 0xc415, 0x21, 0 + .dw 0x0541, 0xc415, 0x0541, 0xc415, 0x21, 0 + .dw 0x0543, 0xc415, 0x054f, 0xc415, 0x21, 0 + .dw 0x0551, 0xc415, 0x0551, 0xc415, 0x21, 0 + .dw 0x0553, 0xc415, 0x057f, 0xc415, 0x21, 0 + .dw 0x0581, 0xc415, 0x0581, 0xc415, 0x21, 0 + .dw 0x0583, 0xc415, 0x058f, 0xc415, 0x21, 0 + .dw 0x0591, 0xc415, 0x0591, 0xc415, 0x21, 0 + .dw 0x0593, 0xc415, 0x05bf, 0xc415, 0x21, 0 + .dw 0x05c1, 0xc415, 0x05c1, 0xc415, 0x21, 0 + .dw 0x05c3, 0xc415, 0x05cf, 0xc415, 0x21, 0 + .dw 0x05d1, 0xc415, 0x05d1, 0xc415, 0x21, 0 + .dw 0x05d3, 0xc415, 0x05ff, 0xc415, 0x21, 0 + .dw 0x0601, 0xc415, 0x0601, 0xc415, 0x21, 0 + .dw 0x0603, 0xc415, 0x060f, 0xc415, 0x21, 0 + .dw 0x0611, 0xc415, 0x0611, 0xc415, 0x21, 0 + .dw 0x0613, 0xc415, 0x063f, 0xc415, 0x21, 0 + .dw 0x0641, 0xc415, 0x0641, 0xc415, 0x21, 0 + .dw 0x0643, 0xc415, 0x064f, 0xc415, 0x21, 0 + .dw 0x0651, 0xc415, 0x0651, 0xc415, 0x21, 0 + .dw 0x0653, 0xc415, 0x067f, 0xc415, 0x21, 0 + .dw 0x0681, 0xc415, 0x0681, 0xc415, 0x21, 0 + .dw 0x0683, 0xc415, 0x068f, 0xc415, 0x21, 0 + .dw 0x0691, 0xc415, 0x0691, 0xc415, 0x21, 0 + .dw 0x0693, 0xc415, 0x06bf, 0xc415, 0x21, 0 + .dw 0x06c0, 0xc415, 0x06c0, 0xc415, 0x22, 0 + .dw 0x06c1, 0xc415, 0x06c1, 0xc415, 0x21, 0 + .dw 0x06c2, 0xc415, 0x06c2, 0xc415, 0x22, 0 + .dw 0x06c3, 0xc415, 0x06cf, 0xc415, 0x21, 0 + .dw 0x06d0, 0xc415, 0x06d0, 0xc415, 0x22, 0 + .dw 0x06d1, 0xc415, 0x06d1, 0xc415, 0x21, 0 + .dw 0x06d2, 0xc415, 0x06d2, 0xc415, 0x22, 0 + .dw 0x06d3, 0xc415, 0x06ff, 0xc415, 0x21, 0 + .dw 0x0701, 0xc415, 0x0701, 0xc415, 0x21, 0 + .dw 0x0703, 0xc415, 0x070f, 0xc415, 0x21, 0 + .dw 0x0711, 0xc415, 0x0711, 0xc415, 0x21, 0 + .dw 0x0713, 0xc415, 0x073f, 0xc415, 0x21, 0 + .dw 0x0741, 0xc415, 0x0741, 0xc415, 0x21, 0 + .dw 0x0743, 0xc415, 0x074f, 0xc415, 0x21, 0 + .dw 0x0751, 0xc415, 0x0751, 0xc415, 0x21, 0 + .dw 0x0753, 0xc415, 0x077f, 0xc415, 0x21, 0 + .dw 0x0781, 0xc415, 0x0781, 0xc415, 0x21, 0 + .dw 0x0783, 0xc415, 0x078f, 0xc415, 0x21, 0 + .dw 0x0791, 0xc415, 0x0791, 0xc415, 0x21, 0 + .dw 0x0793, 0xc415, 0x07bf, 0xc415, 0x21, 0 + .dw 0x07c1, 0xc415, 0x07c1, 0xc415, 0x21, 0 + .dw 0x07c3, 0xc415, 0x07cf, 0xc415, 0x21, 0 + .dw 0x07d1, 0xc415, 0x07d1, 0xc415, 0x21, 0 + .dw 0x07d3, 0xc415, 0x07ff, 0xc415, 0x21, 0 + .dw 0x0801, 0xc415, 0x0801, 0xc415, 0x21, 0 + .dw 0x0803, 0xc415, 0x080f, 0xc415, 0x21, 0 + .dw 0x0811, 0xc415, 0x0811, 0xc415, 0x21, 0 + .dw 0x0813, 0xc415, 0x083f, 0xc415, 0x21, 0 + .dw 0x0841, 0xc415, 0x0841, 0xc415, 0x21, 0 + .dw 0x0843, 0xc415, 0x084f, 0xc415, 0x21, 0 + .dw 0x0851, 0xc415, 0x0851, 0xc415, 0x21, 0 + .dw 0x0853, 0xc415, 0x087f, 0xc415, 0x21, 0 + .dw 0x0881, 0xc415, 0x0881, 0xc415, 0x21, 0 + .dw 0x0883, 0xc415, 0x088f, 0xc415, 0x21, 0 + .dw 0x0891, 0xc415, 0x0891, 0xc415, 0x21, 0 + .dw 0x0893, 0xc415, 0x08bf, 0xc415, 0x21, 0 + .dw 0x08c1, 0xc415, 0x08c1, 0xc415, 0x21, 0 + .dw 0x08c3, 0xc415, 0x08cf, 0xc415, 0x21, 0 + .dw 0x08d1, 0xc415, 0x08d1, 0xc415, 0x21, 0 + .dw 0x08d3, 0xc415, 0x08ff, 0xc415, 0x21, 0 + .dw 0x0900, 0xc415, 0x0900, 0xc415, 0x22, 0 + .dw 0x0901, 0xc415, 0x0901, 0xc415, 0x21, 0 + .dw 0x0902, 0xc415, 0x0902, 0xc415, 0x22, 0 + .dw 0x0903, 0xc415, 0x090f, 0xc415, 0x21, 0 + .dw 0x0910, 0xc415, 0x0910, 0xc415, 0x22, 0 + .dw 0x0911, 0xc415, 0x0911, 0xc415, 0x21, 0 + .dw 0x0912, 0xc415, 0x0912, 0xc415, 0x22, 0 + .dw 0x0913, 0xc415, 0x093f, 0xc415, 0x21, 0 + .dw 0x0941, 0xc415, 0x0941, 0xc415, 0x21, 0 + .dw 0x0943, 0xc415, 0x094f, 0xc415, 0x21, 0 + .dw 0x0951, 0xc415, 0x0951, 0xc415, 0x21, 0 + .dw 0x0953, 0xc415, 0x097f, 0xc415, 0x21, 0 + .dw 0x0981, 0xc415, 0x0981, 0xc415, 0x21, 0 + .dw 0x0983, 0xc415, 0x098f, 0xc415, 0x21, 0 + .dw 0x0991, 0xc415, 0x0991, 0xc415, 0x21, 0 + .dw 0x0993, 0xc415, 0x09bf, 0xc415, 0x21, 0 + .dw 0x09c1, 0xc415, 0x09c1, 0xc415, 0x21, 0 + .dw 0x09c3, 0xc415, 0x09cf, 0xc415, 0x21, 0 + .dw 0x09d1, 0xc415, 0x09d1, 0xc415, 0x21, 0 + .dw 0x09d3, 0xc415, 0x09ff, 0xc415, 0x21, 0 + .dw 0x0a01, 0xc415, 0x0a01, 0xc415, 0x21, 0 + .dw 0x0a03, 0xc415, 0x0a0f, 0xc415, 0x21, 0 + .dw 0x0a11, 0xc415, 0x0a11, 0xc415, 0x21, 0 + .dw 0x0a13, 0xc415, 0x0a3f, 0xc415, 0x21, 0 + .dw 0x0a41, 0xc415, 0x0a41, 0xc415, 0x21, 0 + .dw 0x0a43, 0xc415, 0x0a4f, 0xc415, 0x21, 0 + .dw 0x0a51, 0xc415, 0x0a51, 0xc415, 0x21, 0 + .dw 0x0a53, 0xc415, 0x0a7f, 0xc415, 0x21, 0 + .dw 0x0a81, 0xc415, 0x0a81, 0xc415, 0x21, 0 + .dw 0x0a83, 0xc415, 0x0a8f, 0xc415, 0x21, 0 + .dw 0x0a91, 0xc415, 0x0a91, 0xc415, 0x21, 0 + .dw 0x0a93, 0xc415, 0x0abf, 0xc415, 0x21, 0 + .dw 0x0ac1, 0xc415, 0x0ac1, 0xc415, 0x21, 0 + .dw 0x0ac3, 0xc415, 0x0acf, 0xc415, 0x21, 0 + .dw 0x0ad1, 0xc415, 0x0ad1, 0xc415, 0x21, 0 + .dw 0x0ad3, 0xc415, 0x0aff, 0xc415, 0x21, 0 + .dw 0x0b01, 0xc415, 0x0b01, 0xc415, 0x21, 0 + .dw 0x0b03, 0xc415, 0x0b0f, 0xc415, 0x21, 0 + .dw 0x0b11, 0xc415, 0x0b11, 0xc415, 0x21, 0 + .dw 0x0b13, 0xc415, 0x0b3f, 0xc415, 0x21, 0 + .dw 0x0b40, 0xc415, 0x0b40, 0xc415, 0x22, 0 + .dw 0x0b41, 0xc415, 0x0b41, 0xc415, 0x21, 0 + .dw 0x0b42, 0xc415, 0x0b42, 0xc415, 0x22, 0 + .dw 0x0b43, 0xc415, 0x0b4f, 0xc415, 0x21, 0 + .dw 0x0b50, 0xc415, 0x0b50, 0xc415, 0x22, 0 + .dw 0x0b51, 0xc415, 0x0b51, 0xc415, 0x21, 0 + .dw 0x0b52, 0xc415, 0x0b52, 0xc415, 0x22, 0 + .dw 0x0b53, 0xc415, 0x0b7f, 0xc415, 0x21, 0 + .dw 0x0b81, 0xc415, 0x0b81, 0xc415, 0x21, 0 + .dw 0x0b83, 0xc415, 0x0b8f, 0xc415, 0x21, 0 + .dw 0x0b91, 0xc415, 0x0b91, 0xc415, 0x21, 0 + .dw 0x0b93, 0xc415, 0x0bbf, 0xc415, 0x21, 0 + .dw 0x0bc1, 0xc415, 0x0bc1, 0xc415, 0x21, 0 + .dw 0x0bc3, 0xc415, 0x0bcf, 0xc415, 0x21, 0 + .dw 0x0bd1, 0xc415, 0x0bd1, 0xc415, 0x21, 0 + .dw 0x0bd3, 0xc415, 0x0bff, 0xc415, 0x21, 0 + .dw 0x0c01, 0xc415, 0x0c01, 0xc415, 0x21, 0 + .dw 0x0c03, 0xc415, 0x0c0f, 0xc415, 0x21, 0 + .dw 0x0c11, 0xc415, 0x0c11, 0xc415, 0x21, 0 + .dw 0x0c13, 0xc415, 0x0c3f, 0xc415, 0x21, 0 + .dw 0x0c41, 0xc415, 0x0c41, 0xc415, 0x21, 0 + .dw 0x0c43, 0xc415, 0x0c4f, 0xc415, 0x21, 0 + .dw 0x0c51, 0xc415, 0x0c51, 0xc415, 0x21, 0 + .dw 0x0c53, 0xc415, 0x0c7f, 0xc415, 0x21, 0 + .dw 0x0c81, 0xc415, 0x0c81, 0xc415, 0x21, 0 + .dw 0x0c83, 0xc415, 0x0c8f, 0xc415, 0x21, 0 + .dw 0x0c91, 0xc415, 0x0c91, 0xc415, 0x21, 0 + .dw 0x0c93, 0xc415, 0x0cbf, 0xc415, 0x21, 0 + .dw 0x0cc1, 0xc415, 0x0cc1, 0xc415, 0x21, 0 + .dw 0x0cc3, 0xc415, 0x0ccf, 0xc415, 0x21, 0 + .dw 0x0cd1, 0xc415, 0x0cd1, 0xc415, 0x21, 0 + .dw 0x0cd3, 0xc415, 0x0cff, 0xc415, 0x21, 0 + .dw 0x0d01, 0xc415, 0x0d01, 0xc415, 0x21, 0 + .dw 0x0d03, 0xc415, 0x0d0f, 0xc415, 0x21, 0 + .dw 0x0d11, 0xc415, 0x0d11, 0xc415, 0x21, 0 + .dw 0x0d13, 0xc415, 0x0d3f, 0xc415, 0x21, 0 + .dw 0x0d41, 0xc415, 0x0d41, 0xc415, 0x21, 0 + .dw 0x0d43, 0xc415, 0x0d4f, 0xc415, 0x21, 0 + .dw 0x0d51, 0xc415, 0x0d51, 0xc415, 0x21, 0 + .dw 0x0d53, 0xc415, 0x0d7f, 0xc415, 0x21, 0 + .dw 0x0d80, 0xc415, 0x0d80, 0xc415, 0x22, 0 + .dw 0x0d81, 0xc415, 0x0d81, 0xc415, 0x21, 0 + .dw 0x0d82, 0xc415, 0x0d82, 0xc415, 0x22, 0 + .dw 0x0d83, 0xc415, 0x0d8f, 0xc415, 0x21, 0 + .dw 0x0d90, 0xc415, 0x0d90, 0xc415, 0x22, 0 + .dw 0x0d91, 0xc415, 0x0d91, 0xc415, 0x21, 0 + .dw 0x0d92, 0xc415, 0x0d92, 0xc415, 0x22, 0 + .dw 0x0d93, 0xc415, 0x0dbf, 0xc415, 0x21, 0 + .dw 0x0dc1, 0xc415, 0x0dc1, 0xc415, 0x21, 0 + .dw 0x0dc3, 0xc415, 0x0dcf, 0xc415, 0x21, 0 + .dw 0x0dd1, 0xc415, 0x0dd1, 0xc415, 0x21, 0 + .dw 0x0dd3, 0xc415, 0x0dff, 0xc415, 0x21, 0 + .dw 0x0e01, 0xc415, 0x0e01, 0xc415, 0x21, 0 + .dw 0x0e03, 0xc415, 0x0e0f, 0xc415, 0x21, 0 + .dw 0x0e11, 0xc415, 0x0e11, 0xc415, 0x21, 0 + .dw 0x0e13, 0xc415, 0x0e3f, 0xc415, 0x21, 0 + .dw 0x0e41, 0xc415, 0x0e41, 0xc415, 0x21, 0 + .dw 0x0e43, 0xc415, 0x0e4f, 0xc415, 0x21, 0 + .dw 0x0e51, 0xc415, 0x0e51, 0xc415, 0x21, 0 + .dw 0x0e53, 0xc415, 0x0e7f, 0xc415, 0x21, 0 + .dw 0x0e81, 0xc415, 0x0e81, 0xc415, 0x21, 0 + .dw 0x0e83, 0xc415, 0x0e8f, 0xc415, 0x21, 0 + .dw 0x0e91, 0xc415, 0x0e91, 0xc415, 0x21, 0 + .dw 0x0e93, 0xc415, 0x0ebf, 0xc415, 0x21, 0 + .dw 0x0ec1, 0xc415, 0x0ec1, 0xc415, 0x21, 0 + .dw 0x0ec3, 0xc415, 0x0ecf, 0xc415, 0x21, 0 + .dw 0x0ed1, 0xc415, 0x0ed1, 0xc415, 0x21, 0 + .dw 0x0ed3, 0xc415, 0x0eff, 0xc415, 0x21, 0 + .dw 0x0f01, 0xc415, 0x0f01, 0xc415, 0x21, 0 + .dw 0x0f03, 0xc415, 0x0f0f, 0xc415, 0x21, 0 + .dw 0x0f11, 0xc415, 0x0f11, 0xc415, 0x21, 0 + .dw 0x0f13, 0xc415, 0x0f3f, 0xc415, 0x21, 0 + .dw 0x0f41, 0xc415, 0x0f41, 0xc415, 0x21, 0 + .dw 0x0f43, 0xc415, 0x0f4f, 0xc415, 0x21, 0 + .dw 0x0f51, 0xc415, 0x0f51, 0xc415, 0x21, 0 + .dw 0x0f53, 0xc415, 0x0f7f, 0xc415, 0x21, 0 + .dw 0x0f81, 0xc415, 0x0f81, 0xc415, 0x21, 0 + .dw 0x0f83, 0xc415, 0x0f8f, 0xc415, 0x21, 0 + .dw 0x0f91, 0xc415, 0x0f91, 0xc415, 0x21, 0 + .dw 0x0f93, 0xc415, 0x0fbf, 0xc415, 0x21, 0 + .dw 0x0fc0, 0xc415, 0x0fc0, 0xc415, 0x22, 0 + .dw 0x0fc1, 0xc415, 0x0fc1, 0xc415, 0x21, 0 + .dw 0x0fc2, 0xc415, 0x0fc2, 0xc415, 0x22, 0 + .dw 0x0fc3, 0xc415, 0x0fcf, 0xc415, 0x21, 0 + .dw 0x0fd0, 0xc415, 0x0fd0, 0xc415, 0x22, 0 + .dw 0x0fd1, 0xc415, 0x0fd1, 0xc415, 0x21, 0 + .dw 0x0fd2, 0xc415, 0x0fd2, 0xc415, 0x22, 0 + .dw 0x0fd3, 0xc415, 0x1fff, 0xc415, 0x21, 0 + .dw 0x2000, 0xc415, 0x2000, 0xc415, 0x22, 0 + .dw 0x2001, 0xc415, 0x2001, 0xc415, 0x21, 0 + .dw 0x2002, 0xc415, 0x2002, 0xc415, 0x22, 0 + .dw 0x2003, 0xc415, 0x200f, 0xc415, 0x21, 0 + .dw 0x2010, 0xc415, 0x2010, 0xc415, 0x22, 0 + .dw 0x2011, 0xc415, 0x2011, 0xc415, 0x21, 0 + .dw 0x2012, 0xc415, 0x2012, 0xc415, 0x22, 0 + .dw 0x2013, 0xc415, 0x203f, 0xc415, 0x21, 0 + .dw 0x2041, 0xc415, 0x2041, 0xc415, 0x21, 0 + .dw 0x2043, 0xc415, 0x204f, 0xc415, 0x21, 0 + .dw 0x2051, 0xc415, 0x2051, 0xc415, 0x21, 0 + .dw 0x2053, 0xc415, 0x207f, 0xc415, 0x21, 0 + .dw 0x2081, 0xc415, 0x2081, 0xc415, 0x21, 0 + .dw 0x2083, 0xc415, 0x208f, 0xc415, 0x21, 0 + .dw 0x2091, 0xc415, 0x2091, 0xc415, 0x21, 0 + .dw 0x2093, 0xc415, 0x20bf, 0xc415, 0x21, 0 + .dw 0x20c1, 0xc415, 0x20c1, 0xc415, 0x21, 0 + .dw 0x20c3, 0xc415, 0x20cf, 0xc415, 0x21, 0 + .dw 0x20d1, 0xc415, 0x20d1, 0xc415, 0x21, 0 + .dw 0x20d3, 0xc415, 0x20ff, 0xc415, 0x21, 0 + .dw 0x2101, 0xc415, 0x2101, 0xc415, 0x21, 0 + .dw 0x2103, 0xc415, 0x210f, 0xc415, 0x21, 0 + .dw 0x2111, 0xc415, 0x2111, 0xc415, 0x21, 0 + .dw 0x2113, 0xc415, 0x213f, 0xc415, 0x21, 0 + .dw 0x2141, 0xc415, 0x2141, 0xc415, 0x21, 0 + .dw 0x2143, 0xc415, 0x214f, 0xc415, 0x21, 0 + .dw 0x2151, 0xc415, 0x2151, 0xc415, 0x21, 0 + .dw 0x2153, 0xc415, 0x217f, 0xc415, 0x21, 0 + .dw 0x2181, 0xc415, 0x2181, 0xc415, 0x21, 0 + .dw 0x2183, 0xc415, 0x218f, 0xc415, 0x21, 0 + .dw 0x2191, 0xc415, 0x2191, 0xc415, 0x21, 0 + .dw 0x2193, 0xc415, 0x21bf, 0xc415, 0x21, 0 + .dw 0x21c1, 0xc415, 0x21c1, 0xc415, 0x21, 0 + .dw 0x21c3, 0xc415, 0x21cf, 0xc415, 0x21, 0 + .dw 0x21d1, 0xc415, 0x21d1, 0xc415, 0x21, 0 + .dw 0x21d3, 0xc415, 0x21ff, 0xc415, 0x21, 0 + .dw 0x2201, 0xc415, 0x2201, 0xc415, 0x21, 0 + .dw 0x2203, 0xc415, 0x220f, 0xc415, 0x21, 0 + .dw 0x2211, 0xc415, 0x2211, 0xc415, 0x21, 0 + .dw 0x2213, 0xc415, 0x223f, 0xc415, 0x21, 0 + .dw 0x2240, 0xc415, 0x2240, 0xc415, 0x22, 0 + .dw 0x2241, 0xc415, 0x2241, 0xc415, 0x21, 0 + .dw 0x2242, 0xc415, 0x2242, 0xc415, 0x22, 0 + .dw 0x2243, 0xc415, 0x224f, 0xc415, 0x21, 0 + .dw 0x2250, 0xc415, 0x2250, 0xc415, 0x22, 0 + .dw 0x2251, 0xc415, 0x2251, 0xc415, 0x21, 0 + .dw 0x2252, 0xc415, 0x2252, 0xc415, 0x22, 0 + .dw 0x2253, 0xc415, 0x227f, 0xc415, 0x21, 0 + .dw 0x2281, 0xc415, 0x2281, 0xc415, 0x21, 0 + .dw 0x2283, 0xc415, 0x228f, 0xc415, 0x21, 0 + .dw 0x2291, 0xc415, 0x2291, 0xc415, 0x21, 0 + .dw 0x2293, 0xc415, 0x22bf, 0xc415, 0x21, 0 + .dw 0x22c1, 0xc415, 0x22c1, 0xc415, 0x21, 0 + .dw 0x22c3, 0xc415, 0x22cf, 0xc415, 0x21, 0 + .dw 0x22d1, 0xc415, 0x22d1, 0xc415, 0x21, 0 + .dw 0x22d3, 0xc415, 0x22ff, 0xc415, 0x21, 0 + .dw 0x2301, 0xc415, 0x2301, 0xc415, 0x21, 0 + .dw 0x2303, 0xc415, 0x230f, 0xc415, 0x21, 0 + .dw 0x2311, 0xc415, 0x2311, 0xc415, 0x21, 0 + .dw 0x2313, 0xc415, 0x233f, 0xc415, 0x21, 0 + .dw 0x2341, 0xc415, 0x2341, 0xc415, 0x21, 0 + .dw 0x2343, 0xc415, 0x234f, 0xc415, 0x21, 0 + .dw 0x2351, 0xc415, 0x2351, 0xc415, 0x21, 0 + .dw 0x2353, 0xc415, 0x237f, 0xc415, 0x21, 0 + .dw 0x2381, 0xc415, 0x2381, 0xc415, 0x21, 0 + .dw 0x2383, 0xc415, 0x238f, 0xc415, 0x21, 0 + .dw 0x2391, 0xc415, 0x2391, 0xc415, 0x21, 0 + .dw 0x2393, 0xc415, 0x23bf, 0xc415, 0x21, 0 + .dw 0x23c1, 0xc415, 0x23c1, 0xc415, 0x21, 0 + .dw 0x23c3, 0xc415, 0x23cf, 0xc415, 0x21, 0 + .dw 0x23d1, 0xc415, 0x23d1, 0xc415, 0x21, 0 + .dw 0x23d3, 0xc415, 0x23ff, 0xc415, 0x21, 0 + .dw 0x2401, 0xc415, 0x2401, 0xc415, 0x21, 0 + .dw 0x2403, 0xc415, 0x240f, 0xc415, 0x21, 0 + .dw 0x2411, 0xc415, 0x2411, 0xc415, 0x21, 0 + .dw 0x2413, 0xc415, 0x243f, 0xc415, 0x21, 0 + .dw 0x2441, 0xc415, 0x2441, 0xc415, 0x21, 0 + .dw 0x2443, 0xc415, 0x244f, 0xc415, 0x21, 0 + .dw 0x2451, 0xc415, 0x2451, 0xc415, 0x21, 0 + .dw 0x2453, 0xc415, 0x247f, 0xc415, 0x21, 0 + .dw 0x2480, 0xc415, 0x2480, 0xc415, 0x22, 0 + .dw 0x2481, 0xc415, 0x2481, 0xc415, 0x21, 0 + .dw 0x2482, 0xc415, 0x2482, 0xc415, 0x22, 0 + .dw 0x2483, 0xc415, 0x248f, 0xc415, 0x21, 0 + .dw 0x2490, 0xc415, 0x2490, 0xc415, 0x22, 0 + .dw 0x2491, 0xc415, 0x2491, 0xc415, 0x21, 0 + .dw 0x2492, 0xc415, 0x2492, 0xc415, 0x22, 0 + .dw 0x2493, 0xc415, 0x24bf, 0xc415, 0x21, 0 + .dw 0x24c1, 0xc415, 0x24c1, 0xc415, 0x21, 0 + .dw 0x24c3, 0xc415, 0x24cf, 0xc415, 0x21, 0 + .dw 0x24d1, 0xc415, 0x24d1, 0xc415, 0x21, 0 + .dw 0x24d3, 0xc415, 0x24ff, 0xc415, 0x21, 0 + .dw 0x2501, 0xc415, 0x2501, 0xc415, 0x21, 0 + .dw 0x2503, 0xc415, 0x250f, 0xc415, 0x21, 0 + .dw 0x2511, 0xc415, 0x2511, 0xc415, 0x21, 0 + .dw 0x2513, 0xc415, 0x253f, 0xc415, 0x21, 0 + .dw 0x2541, 0xc415, 0x2541, 0xc415, 0x21, 0 + .dw 0x2543, 0xc415, 0x254f, 0xc415, 0x21, 0 + .dw 0x2551, 0xc415, 0x2551, 0xc415, 0x21, 0 + .dw 0x2553, 0xc415, 0x257f, 0xc415, 0x21, 0 + .dw 0x2581, 0xc415, 0x2581, 0xc415, 0x21, 0 + .dw 0x2583, 0xc415, 0x258f, 0xc415, 0x21, 0 + .dw 0x2591, 0xc415, 0x2591, 0xc415, 0x21, 0 + .dw 0x2593, 0xc415, 0x25bf, 0xc415, 0x21, 0 + .dw 0x25c1, 0xc415, 0x25c1, 0xc415, 0x21, 0 + .dw 0x25c3, 0xc415, 0x25cf, 0xc415, 0x21, 0 + .dw 0x25d1, 0xc415, 0x25d1, 0xc415, 0x21, 0 + .dw 0x25d3, 0xc415, 0x25ff, 0xc415, 0x21, 0 + .dw 0x2601, 0xc415, 0x2601, 0xc415, 0x21, 0 + .dw 0x2603, 0xc415, 0x260f, 0xc415, 0x21, 0 + .dw 0x2611, 0xc415, 0x2611, 0xc415, 0x21, 0 + .dw 0x2613, 0xc415, 0x263f, 0xc415, 0x21, 0 + .dw 0x2641, 0xc415, 0x2641, 0xc415, 0x21, 0 + .dw 0x2643, 0xc415, 0x264f, 0xc415, 0x21, 0 + .dw 0x2651, 0xc415, 0x2651, 0xc415, 0x21, 0 + .dw 0x2653, 0xc415, 0x267f, 0xc415, 0x21, 0 + .dw 0x2681, 0xc415, 0x2681, 0xc415, 0x21, 0 + .dw 0x2683, 0xc415, 0x268f, 0xc415, 0x21, 0 + .dw 0x2691, 0xc415, 0x2691, 0xc415, 0x21, 0 + .dw 0x2693, 0xc415, 0x26bf, 0xc415, 0x21, 0 + .dw 0x26c0, 0xc415, 0x26c0, 0xc415, 0x22, 0 + .dw 0x26c1, 0xc415, 0x26c1, 0xc415, 0x21, 0 + .dw 0x26c2, 0xc415, 0x26c2, 0xc415, 0x22, 0 + .dw 0x26c3, 0xc415, 0x26cf, 0xc415, 0x21, 0 + .dw 0x26d0, 0xc415, 0x26d0, 0xc415, 0x22, 0 + .dw 0x26d1, 0xc415, 0x26d1, 0xc415, 0x21, 0 + .dw 0x26d2, 0xc415, 0x26d2, 0xc415, 0x22, 0 + .dw 0x26d3, 0xc415, 0x26ff, 0xc415, 0x21, 0 + .dw 0x2701, 0xc415, 0x2701, 0xc415, 0x21, 0 + .dw 0x2703, 0xc415, 0x270f, 0xc415, 0x21, 0 + .dw 0x2711, 0xc415, 0x2711, 0xc415, 0x21, 0 + .dw 0x2713, 0xc415, 0x273f, 0xc415, 0x21, 0 + .dw 0x2741, 0xc415, 0x2741, 0xc415, 0x21, 0 + .dw 0x2743, 0xc415, 0x274f, 0xc415, 0x21, 0 + .dw 0x2751, 0xc415, 0x2751, 0xc415, 0x21, 0 + .dw 0x2753, 0xc415, 0x277f, 0xc415, 0x21, 0 + .dw 0x2781, 0xc415, 0x2781, 0xc415, 0x21, 0 + .dw 0x2783, 0xc415, 0x278f, 0xc415, 0x21, 0 + .dw 0x2791, 0xc415, 0x2791, 0xc415, 0x21, 0 + .dw 0x2793, 0xc415, 0x27bf, 0xc415, 0x21, 0 + .dw 0x27c1, 0xc415, 0x27c1, 0xc415, 0x21, 0 + .dw 0x27c3, 0xc415, 0x27cf, 0xc415, 0x21, 0 + .dw 0x27d1, 0xc415, 0x27d1, 0xc415, 0x21, 0 + .dw 0x27d3, 0xc415, 0x27ff, 0xc415, 0x21, 0 + .dw 0x2801, 0xc415, 0x2801, 0xc415, 0x21, 0 + .dw 0x2803, 0xc415, 0x280f, 0xc415, 0x21, 0 + .dw 0x2811, 0xc415, 0x2811, 0xc415, 0x21, 0 + .dw 0x2813, 0xc415, 0x283f, 0xc415, 0x21, 0 + .dw 0x2841, 0xc415, 0x2841, 0xc415, 0x21, 0 + .dw 0x2843, 0xc415, 0x284f, 0xc415, 0x21, 0 + .dw 0x2851, 0xc415, 0x2851, 0xc415, 0x21, 0 + .dw 0x2853, 0xc415, 0x287f, 0xc415, 0x21, 0 + .dw 0x2881, 0xc415, 0x2881, 0xc415, 0x21, 0 + .dw 0x2883, 0xc415, 0x288f, 0xc415, 0x21, 0 + .dw 0x2891, 0xc415, 0x2891, 0xc415, 0x21, 0 + .dw 0x2893, 0xc415, 0x28bf, 0xc415, 0x21, 0 + .dw 0x28c1, 0xc415, 0x28c1, 0xc415, 0x21, 0 + .dw 0x28c3, 0xc415, 0x28cf, 0xc415, 0x21, 0 + .dw 0x28d1, 0xc415, 0x28d1, 0xc415, 0x21, 0 + .dw 0x28d3, 0xc415, 0x28ff, 0xc415, 0x21, 0 + .dw 0x2900, 0xc415, 0x2900, 0xc415, 0x22, 0 + .dw 0x2901, 0xc415, 0x2901, 0xc415, 0x21, 0 + .dw 0x2902, 0xc415, 0x2902, 0xc415, 0x22, 0 + .dw 0x2903, 0xc415, 0x290f, 0xc415, 0x21, 0 + .dw 0x2910, 0xc415, 0x2910, 0xc415, 0x22, 0 + .dw 0x2911, 0xc415, 0x2911, 0xc415, 0x21, 0 + .dw 0x2912, 0xc415, 0x2912, 0xc415, 0x22, 0 + .dw 0x2913, 0xc415, 0x293f, 0xc415, 0x21, 0 + .dw 0x2941, 0xc415, 0x2941, 0xc415, 0x21, 0 + .dw 0x2943, 0xc415, 0x294f, 0xc415, 0x21, 0 + .dw 0x2951, 0xc415, 0x2951, 0xc415, 0x21, 0 + .dw 0x2953, 0xc415, 0x297f, 0xc415, 0x21, 0 + .dw 0x2981, 0xc415, 0x2981, 0xc415, 0x21, 0 + .dw 0x2983, 0xc415, 0x298f, 0xc415, 0x21, 0 + .dw 0x2991, 0xc415, 0x2991, 0xc415, 0x21, 0 + .dw 0x2993, 0xc415, 0x29bf, 0xc415, 0x21, 0 + .dw 0x29c1, 0xc415, 0x29c1, 0xc415, 0x21, 0 + .dw 0x29c3, 0xc415, 0x29cf, 0xc415, 0x21, 0 + .dw 0x29d1, 0xc415, 0x29d1, 0xc415, 0x21, 0 + .dw 0x29d3, 0xc415, 0x29ff, 0xc415, 0x21, 0 + .dw 0x2a01, 0xc415, 0x2a01, 0xc415, 0x21, 0 + .dw 0x2a03, 0xc415, 0x2a0f, 0xc415, 0x21, 0 + .dw 0x2a11, 0xc415, 0x2a11, 0xc415, 0x21, 0 + .dw 0x2a13, 0xc415, 0x2a3f, 0xc415, 0x21, 0 + .dw 0x2a41, 0xc415, 0x2a41, 0xc415, 0x21, 0 + .dw 0x2a43, 0xc415, 0x2a4f, 0xc415, 0x21, 0 + .dw 0x2a51, 0xc415, 0x2a51, 0xc415, 0x21, 0 + .dw 0x2a53, 0xc415, 0x2a7f, 0xc415, 0x21, 0 + .dw 0x2a81, 0xc415, 0x2a81, 0xc415, 0x21, 0 + .dw 0x2a83, 0xc415, 0x2a8f, 0xc415, 0x21, 0 + .dw 0x2a91, 0xc415, 0x2a91, 0xc415, 0x21, 0 + .dw 0x2a93, 0xc415, 0x2abf, 0xc415, 0x21, 0 + .dw 0x2ac1, 0xc415, 0x2ac1, 0xc415, 0x21, 0 + .dw 0x2ac3, 0xc415, 0x2acf, 0xc415, 0x21, 0 + .dw 0x2ad1, 0xc415, 0x2ad1, 0xc415, 0x21, 0 + .dw 0x2ad3, 0xc415, 0x2aff, 0xc415, 0x21, 0 + .dw 0x2b01, 0xc415, 0x2b01, 0xc415, 0x21, 0 + .dw 0x2b03, 0xc415, 0x2b0f, 0xc415, 0x21, 0 + .dw 0x2b11, 0xc415, 0x2b11, 0xc415, 0x21, 0 + .dw 0x2b13, 0xc415, 0x2b3f, 0xc415, 0x21, 0 + .dw 0x2b40, 0xc415, 0x2b40, 0xc415, 0x22, 0 + .dw 0x2b41, 0xc415, 0x2b41, 0xc415, 0x21, 0 + .dw 0x2b42, 0xc415, 0x2b42, 0xc415, 0x22, 0 + .dw 0x2b43, 0xc415, 0x2b4f, 0xc415, 0x21, 0 + .dw 0x2b50, 0xc415, 0x2b50, 0xc415, 0x22, 0 + .dw 0x2b51, 0xc415, 0x2b51, 0xc415, 0x21, 0 + .dw 0x2b52, 0xc415, 0x2b52, 0xc415, 0x22, 0 + .dw 0x2b53, 0xc415, 0x2b7f, 0xc415, 0x21, 0 + .dw 0x2b81, 0xc415, 0x2b81, 0xc415, 0x21, 0 + .dw 0x2b83, 0xc415, 0x2b8f, 0xc415, 0x21, 0 + .dw 0x2b91, 0xc415, 0x2b91, 0xc415, 0x21, 0 + .dw 0x2b93, 0xc415, 0x2bbf, 0xc415, 0x21, 0 + .dw 0x2bc1, 0xc415, 0x2bc1, 0xc415, 0x21, 0 + .dw 0x2bc3, 0xc415, 0x2bcf, 0xc415, 0x21, 0 + .dw 0x2bd1, 0xc415, 0x2bd1, 0xc415, 0x21, 0 + .dw 0x2bd3, 0xc415, 0x2bff, 0xc415, 0x21, 0 + .dw 0x2c01, 0xc415, 0x2c01, 0xc415, 0x21, 0 + .dw 0x2c03, 0xc415, 0x2c0f, 0xc415, 0x21, 0 + .dw 0x2c11, 0xc415, 0x2c11, 0xc415, 0x21, 0 + .dw 0x2c13, 0xc415, 0x2c3f, 0xc415, 0x21, 0 + .dw 0x2c41, 0xc415, 0x2c41, 0xc415, 0x21, 0 + .dw 0x2c43, 0xc415, 0x2c4f, 0xc415, 0x21, 0 + .dw 0x2c51, 0xc415, 0x2c51, 0xc415, 0x21, 0 + .dw 0x2c53, 0xc415, 0x2c7f, 0xc415, 0x21, 0 + .dw 0x2c81, 0xc415, 0x2c81, 0xc415, 0x21, 0 + .dw 0x2c83, 0xc415, 0x2c8f, 0xc415, 0x21, 0 + .dw 0x2c91, 0xc415, 0x2c91, 0xc415, 0x21, 0 + .dw 0x2c93, 0xc415, 0x2cbf, 0xc415, 0x21, 0 + .dw 0x2cc1, 0xc415, 0x2cc1, 0xc415, 0x21, 0 + .dw 0x2cc3, 0xc415, 0x2ccf, 0xc415, 0x21, 0 + .dw 0x2cd1, 0xc415, 0x2cd1, 0xc415, 0x21, 0 + .dw 0x2cd3, 0xc415, 0x2cff, 0xc415, 0x21, 0 + .dw 0x2d01, 0xc415, 0x2d01, 0xc415, 0x21, 0 + .dw 0x2d03, 0xc415, 0x2d0f, 0xc415, 0x21, 0 + .dw 0x2d11, 0xc415, 0x2d11, 0xc415, 0x21, 0 + .dw 0x2d13, 0xc415, 0x2d3f, 0xc415, 0x21, 0 + .dw 0x2d41, 0xc415, 0x2d41, 0xc415, 0x21, 0 + .dw 0x2d43, 0xc415, 0x2d4f, 0xc415, 0x21, 0 + .dw 0x2d51, 0xc415, 0x2d51, 0xc415, 0x21, 0 + .dw 0x2d53, 0xc415, 0x2d7f, 0xc415, 0x21, 0 + .dw 0x2d80, 0xc415, 0x2d80, 0xc415, 0x22, 0 + .dw 0x2d81, 0xc415, 0x2d81, 0xc415, 0x21, 0 + .dw 0x2d82, 0xc415, 0x2d82, 0xc415, 0x22, 0 + .dw 0x2d83, 0xc415, 0x2d8f, 0xc415, 0x21, 0 + .dw 0x2d90, 0xc415, 0x2d90, 0xc415, 0x22, 0 + .dw 0x2d91, 0xc415, 0x2d91, 0xc415, 0x21, 0 + .dw 0x2d92, 0xc415, 0x2d92, 0xc415, 0x22, 0 + .dw 0x2d93, 0xc415, 0x2dbf, 0xc415, 0x21, 0 + .dw 0x2dc1, 0xc415, 0x2dc1, 0xc415, 0x21, 0 + .dw 0x2dc3, 0xc415, 0x2dcf, 0xc415, 0x21, 0 + .dw 0x2dd1, 0xc415, 0x2dd1, 0xc415, 0x21, 0 + .dw 0x2dd3, 0xc415, 0x2dff, 0xc415, 0x21, 0 + .dw 0x2e01, 0xc415, 0x2e01, 0xc415, 0x21, 0 + .dw 0x2e03, 0xc415, 0x2e0f, 0xc415, 0x21, 0 + .dw 0x2e11, 0xc415, 0x2e11, 0xc415, 0x21, 0 + .dw 0x2e13, 0xc415, 0x2e3f, 0xc415, 0x21, 0 + .dw 0x2e41, 0xc415, 0x2e41, 0xc415, 0x21, 0 + .dw 0x2e43, 0xc415, 0x2e4f, 0xc415, 0x21, 0 + .dw 0x2e51, 0xc415, 0x2e51, 0xc415, 0x21, 0 + .dw 0x2e53, 0xc415, 0x2e7f, 0xc415, 0x21, 0 + .dw 0x2e81, 0xc415, 0x2e81, 0xc415, 0x21, 0 + .dw 0x2e83, 0xc415, 0x2e8f, 0xc415, 0x21, 0 + .dw 0x2e91, 0xc415, 0x2e91, 0xc415, 0x21, 0 + .dw 0x2e93, 0xc415, 0x2ebf, 0xc415, 0x21, 0 + .dw 0x2ec1, 0xc415, 0x2ec1, 0xc415, 0x21, 0 + .dw 0x2ec3, 0xc415, 0x2ecf, 0xc415, 0x21, 0 + .dw 0x2ed1, 0xc415, 0x2ed1, 0xc415, 0x21, 0 + .dw 0x2ed3, 0xc415, 0x2eff, 0xc415, 0x21, 0 + .dw 0x2f01, 0xc415, 0x2f01, 0xc415, 0x21, 0 + .dw 0x2f03, 0xc415, 0x2f0f, 0xc415, 0x21, 0 + .dw 0x2f11, 0xc415, 0x2f11, 0xc415, 0x21, 0 + .dw 0x2f13, 0xc415, 0x2f3f, 0xc415, 0x21, 0 + .dw 0x2f41, 0xc415, 0x2f41, 0xc415, 0x21, 0 + .dw 0x2f43, 0xc415, 0x2f4f, 0xc415, 0x21, 0 + .dw 0x2f51, 0xc415, 0x2f51, 0xc415, 0x21, 0 + .dw 0x2f53, 0xc415, 0x2f7f, 0xc415, 0x21, 0 + .dw 0x2f81, 0xc415, 0x2f81, 0xc415, 0x21, 0 + .dw 0x2f83, 0xc415, 0x2f8f, 0xc415, 0x21, 0 + .dw 0x2f91, 0xc415, 0x2f91, 0xc415, 0x21, 0 + .dw 0x2f93, 0xc415, 0x2fbf, 0xc415, 0x21, 0 + .dw 0x2fc0, 0xc415, 0x2fc0, 0xc415, 0x22, 0 + .dw 0x2fc1, 0xc415, 0x2fc1, 0xc415, 0x21, 0 + .dw 0x2fc2, 0xc415, 0x2fc2, 0xc415, 0x22, 0 + .dw 0x2fc3, 0xc415, 0x2fcf, 0xc415, 0x21, 0 + .dw 0x2fd0, 0xc415, 0x2fd0, 0xc415, 0x22, 0 + .dw 0x2fd1, 0xc415, 0x2fd1, 0xc415, 0x21, 0 + .dw 0x2fd2, 0xc415, 0x2fd2, 0xc415, 0x22, 0 + .dw 0x2fd3, 0xc415, 0x3fff, 0xc415, 0x21, 0 + .dw 0x4000, 0xc415, 0x4000, 0xc415, 0x22, 0 + .dw 0x4001, 0xc415, 0x4001, 0xc415, 0x21, 0 + .dw 0x4002, 0xc415, 0x4002, 0xc415, 0x22, 0 + .dw 0x4003, 0xc415, 0x400f, 0xc415, 0x21, 0 + .dw 0x4010, 0xc415, 0x4010, 0xc415, 0x22, 0 + .dw 0x4011, 0xc415, 0x4011, 0xc415, 0x21, 0 + .dw 0x4012, 0xc415, 0x4012, 0xc415, 0x22, 0 + .dw 0x4013, 0xc415, 0x403f, 0xc415, 0x21, 0 + .dw 0x4041, 0xc415, 0x4041, 0xc415, 0x21, 0 + .dw 0x4043, 0xc415, 0x404f, 0xc415, 0x21, 0 + .dw 0x4051, 0xc415, 0x4051, 0xc415, 0x21, 0 + .dw 0x4053, 0xc415, 0x407f, 0xc415, 0x21, 0 + .dw 0x4081, 0xc415, 0x4081, 0xc415, 0x21, 0 + .dw 0x4083, 0xc415, 0x408f, 0xc415, 0x21, 0 + .dw 0x4091, 0xc415, 0x4091, 0xc415, 0x21, 0 + .dw 0x4093, 0xc415, 0x40bf, 0xc415, 0x21, 0 + .dw 0x40c1, 0xc415, 0x40c1, 0xc415, 0x21, 0 + .dw 0x40c3, 0xc415, 0x40cf, 0xc415, 0x21, 0 + .dw 0x40d1, 0xc415, 0x40d1, 0xc415, 0x21, 0 + .dw 0x40d3, 0xc415, 0x40ff, 0xc415, 0x21, 0 + .dw 0x4101, 0xc415, 0x4101, 0xc415, 0x21, 0 + .dw 0x4103, 0xc415, 0x410f, 0xc415, 0x21, 0 + .dw 0x4111, 0xc415, 0x4111, 0xc415, 0x21, 0 + .dw 0x4113, 0xc415, 0x413f, 0xc415, 0x21, 0 + .dw 0x4141, 0xc415, 0x4141, 0xc415, 0x21, 0 + .dw 0x4143, 0xc415, 0x414f, 0xc415, 0x21, 0 + .dw 0x4151, 0xc415, 0x4151, 0xc415, 0x21, 0 + .dw 0x4153, 0xc415, 0x417f, 0xc415, 0x21, 0 + .dw 0x4181, 0xc415, 0x4181, 0xc415, 0x21, 0 + .dw 0x4183, 0xc415, 0x418f, 0xc415, 0x21, 0 + .dw 0x4191, 0xc415, 0x4191, 0xc415, 0x21, 0 + .dw 0x4193, 0xc415, 0x41bf, 0xc415, 0x21, 0 + .dw 0x41c1, 0xc415, 0x41c1, 0xc415, 0x21, 0 + .dw 0x41c3, 0xc415, 0x41cf, 0xc415, 0x21, 0 + .dw 0x41d1, 0xc415, 0x41d1, 0xc415, 0x21, 0 + .dw 0x41d3, 0xc415, 0x41ff, 0xc415, 0x21, 0 + .dw 0x4201, 0xc415, 0x4201, 0xc415, 0x21, 0 + .dw 0x4203, 0xc415, 0x420f, 0xc415, 0x21, 0 + .dw 0x4211, 0xc415, 0x4211, 0xc415, 0x21, 0 + .dw 0x4213, 0xc415, 0x423f, 0xc415, 0x21, 0 + .dw 0x4240, 0xc415, 0x4240, 0xc415, 0x22, 0 + .dw 0x4241, 0xc415, 0x4241, 0xc415, 0x21, 0 + .dw 0x4242, 0xc415, 0x4242, 0xc415, 0x22, 0 + .dw 0x4243, 0xc415, 0x424f, 0xc415, 0x21, 0 + .dw 0x4250, 0xc415, 0x4250, 0xc415, 0x22, 0 + .dw 0x4251, 0xc415, 0x4251, 0xc415, 0x21, 0 + .dw 0x4252, 0xc415, 0x4252, 0xc415, 0x22, 0 + .dw 0x4253, 0xc415, 0x427f, 0xc415, 0x21, 0 + .dw 0x4281, 0xc415, 0x4281, 0xc415, 0x21, 0 + .dw 0x4283, 0xc415, 0x428f, 0xc415, 0x21, 0 + .dw 0x4291, 0xc415, 0x4291, 0xc415, 0x21, 0 + .dw 0x4293, 0xc415, 0x42bf, 0xc415, 0x21, 0 + .dw 0x42c1, 0xc415, 0x42c1, 0xc415, 0x21, 0 + .dw 0x42c3, 0xc415, 0x42cf, 0xc415, 0x21, 0 + .dw 0x42d1, 0xc415, 0x42d1, 0xc415, 0x21, 0 + .dw 0x42d3, 0xc415, 0x42ff, 0xc415, 0x21, 0 + .dw 0x4301, 0xc415, 0x4301, 0xc415, 0x21, 0 + .dw 0x4303, 0xc415, 0x430f, 0xc415, 0x21, 0 + .dw 0x4311, 0xc415, 0x4311, 0xc415, 0x21, 0 + .dw 0x4313, 0xc415, 0x433f, 0xc415, 0x21, 0 + .dw 0x4341, 0xc415, 0x4341, 0xc415, 0x21, 0 + .dw 0x4343, 0xc415, 0x434f, 0xc415, 0x21, 0 + .dw 0x4351, 0xc415, 0x4351, 0xc415, 0x21, 0 + .dw 0x4353, 0xc415, 0x437f, 0xc415, 0x21, 0 + .dw 0x4381, 0xc415, 0x4381, 0xc415, 0x21, 0 + .dw 0x4383, 0xc415, 0x438f, 0xc415, 0x21, 0 + .dw 0x4391, 0xc415, 0x4391, 0xc415, 0x21, 0 + .dw 0x4393, 0xc415, 0x43bf, 0xc415, 0x21, 0 + .dw 0x43c1, 0xc415, 0x43c1, 0xc415, 0x21, 0 + .dw 0x43c3, 0xc415, 0x43cf, 0xc415, 0x21, 0 + .dw 0x43d1, 0xc415, 0x43d1, 0xc415, 0x21, 0 + .dw 0x43d3, 0xc415, 0x43ff, 0xc415, 0x21, 0 + .dw 0x4401, 0xc415, 0x4401, 0xc415, 0x21, 0 + .dw 0x4403, 0xc415, 0x440f, 0xc415, 0x21, 0 + .dw 0x4411, 0xc415, 0x4411, 0xc415, 0x21, 0 + .dw 0x4413, 0xc415, 0x443f, 0xc415, 0x21, 0 + .dw 0x4441, 0xc415, 0x4441, 0xc415, 0x21, 0 + .dw 0x4443, 0xc415, 0x444f, 0xc415, 0x21, 0 + .dw 0x4451, 0xc415, 0x4451, 0xc415, 0x21, 0 + .dw 0x4453, 0xc415, 0x447f, 0xc415, 0x21, 0 + .dw 0x4480, 0xc415, 0x4480, 0xc415, 0x22, 0 + .dw 0x4481, 0xc415, 0x4481, 0xc415, 0x21, 0 + .dw 0x4482, 0xc415, 0x4482, 0xc415, 0x22, 0 + .dw 0x4483, 0xc415, 0x448f, 0xc415, 0x21, 0 + .dw 0x4490, 0xc415, 0x4490, 0xc415, 0x22, 0 + .dw 0x4491, 0xc415, 0x4491, 0xc415, 0x21, 0 + .dw 0x4492, 0xc415, 0x4492, 0xc415, 0x22, 0 + .dw 0x4493, 0xc415, 0x44bf, 0xc415, 0x21, 0 + .dw 0x44c1, 0xc415, 0x44c1, 0xc415, 0x21, 0 + .dw 0x44c3, 0xc415, 0x44cf, 0xc415, 0x21, 0 + .dw 0x44d1, 0xc415, 0x44d1, 0xc415, 0x21, 0 + .dw 0x44d3, 0xc415, 0x44ff, 0xc415, 0x21, 0 + .dw 0x4501, 0xc415, 0x4501, 0xc415, 0x21, 0 + .dw 0x4503, 0xc415, 0x450f, 0xc415, 0x21, 0 + .dw 0x4511, 0xc415, 0x4511, 0xc415, 0x21, 0 + .dw 0x4513, 0xc415, 0x453f, 0xc415, 0x21, 0 + .dw 0x4541, 0xc415, 0x4541, 0xc415, 0x21, 0 + .dw 0x4543, 0xc415, 0x454f, 0xc415, 0x21, 0 + .dw 0x4551, 0xc415, 0x4551, 0xc415, 0x21, 0 + .dw 0x4553, 0xc415, 0x457f, 0xc415, 0x21, 0 + .dw 0x4581, 0xc415, 0x4581, 0xc415, 0x21, 0 + .dw 0x4583, 0xc415, 0x458f, 0xc415, 0x21, 0 + .dw 0x4591, 0xc415, 0x4591, 0xc415, 0x21, 0 + .dw 0x4593, 0xc415, 0x45bf, 0xc415, 0x21, 0 + .dw 0x45c1, 0xc415, 0x45c1, 0xc415, 0x21, 0 + .dw 0x45c3, 0xc415, 0x45cf, 0xc415, 0x21, 0 + .dw 0x45d1, 0xc415, 0x45d1, 0xc415, 0x21, 0 + .dw 0x45d3, 0xc415, 0x45ff, 0xc415, 0x21, 0 + .dw 0x4601, 0xc415, 0x4601, 0xc415, 0x21, 0 + .dw 0x4603, 0xc415, 0x460f, 0xc415, 0x21, 0 + .dw 0x4611, 0xc415, 0x4611, 0xc415, 0x21, 0 + .dw 0x4613, 0xc415, 0x463f, 0xc415, 0x21, 0 + .dw 0x4641, 0xc415, 0x4641, 0xc415, 0x21, 0 + .dw 0x4643, 0xc415, 0x464f, 0xc415, 0x21, 0 + .dw 0x4651, 0xc415, 0x4651, 0xc415, 0x21, 0 + .dw 0x4653, 0xc415, 0x467f, 0xc415, 0x21, 0 + .dw 0x4681, 0xc415, 0x4681, 0xc415, 0x21, 0 + .dw 0x4683, 0xc415, 0x468f, 0xc415, 0x21, 0 + .dw 0x4691, 0xc415, 0x4691, 0xc415, 0x21, 0 + .dw 0x4693, 0xc415, 0x46bf, 0xc415, 0x21, 0 + .dw 0x46c0, 0xc415, 0x46c0, 0xc415, 0x22, 0 + .dw 0x46c1, 0xc415, 0x46c1, 0xc415, 0x21, 0 + .dw 0x46c2, 0xc415, 0x46c2, 0xc415, 0x22, 0 + .dw 0x46c3, 0xc415, 0x46cf, 0xc415, 0x21, 0 + .dw 0x46d0, 0xc415, 0x46d0, 0xc415, 0x22, 0 + .dw 0x46d1, 0xc415, 0x46d1, 0xc415, 0x21, 0 + .dw 0x46d2, 0xc415, 0x46d2, 0xc415, 0x22, 0 + .dw 0x46d3, 0xc415, 0x46ff, 0xc415, 0x21, 0 + .dw 0x4701, 0xc415, 0x4701, 0xc415, 0x21, 0 + .dw 0x4703, 0xc415, 0x470f, 0xc415, 0x21, 0 + .dw 0x4711, 0xc415, 0x4711, 0xc415, 0x21, 0 + .dw 0x4713, 0xc415, 0x473f, 0xc415, 0x21, 0 + .dw 0x4741, 0xc415, 0x4741, 0xc415, 0x21, 0 + .dw 0x4743, 0xc415, 0x474f, 0xc415, 0x21, 0 + .dw 0x4751, 0xc415, 0x4751, 0xc415, 0x21, 0 + .dw 0x4753, 0xc415, 0x477f, 0xc415, 0x21, 0 + .dw 0x4781, 0xc415, 0x4781, 0xc415, 0x21, 0 + .dw 0x4783, 0xc415, 0x478f, 0xc415, 0x21, 0 + .dw 0x4791, 0xc415, 0x4791, 0xc415, 0x21, 0 + .dw 0x4793, 0xc415, 0x47bf, 0xc415, 0x21, 0 + .dw 0x47c1, 0xc415, 0x47c1, 0xc415, 0x21, 0 + .dw 0x47c3, 0xc415, 0x47cf, 0xc415, 0x21, 0 + .dw 0x47d1, 0xc415, 0x47d1, 0xc415, 0x21, 0 + .dw 0x47d3, 0xc415, 0x47ff, 0xc415, 0x21, 0 + .dw 0x4801, 0xc415, 0x4801, 0xc415, 0x21, 0 + .dw 0x4803, 0xc415, 0x480f, 0xc415, 0x21, 0 + .dw 0x4811, 0xc415, 0x4811, 0xc415, 0x21, 0 + .dw 0x4813, 0xc415, 0x483f, 0xc415, 0x21, 0 + .dw 0x4841, 0xc415, 0x4841, 0xc415, 0x21, 0 + .dw 0x4843, 0xc415, 0x484f, 0xc415, 0x21, 0 + .dw 0x4851, 0xc415, 0x4851, 0xc415, 0x21, 0 + .dw 0x4853, 0xc415, 0x487f, 0xc415, 0x21, 0 + .dw 0x4881, 0xc415, 0x4881, 0xc415, 0x21, 0 + .dw 0x4883, 0xc415, 0x488f, 0xc415, 0x21, 0 + .dw 0x4891, 0xc415, 0x4891, 0xc415, 0x21, 0 + .dw 0x4893, 0xc415, 0x48bf, 0xc415, 0x21, 0 + .dw 0x48c1, 0xc415, 0x48c1, 0xc415, 0x21, 0 + .dw 0x48c3, 0xc415, 0x48cf, 0xc415, 0x21, 0 + .dw 0x48d1, 0xc415, 0x48d1, 0xc415, 0x21, 0 + .dw 0x48d3, 0xc415, 0x48ff, 0xc415, 0x21, 0 + .dw 0x4900, 0xc415, 0x4900, 0xc415, 0x22, 0 + .dw 0x4901, 0xc415, 0x4901, 0xc415, 0x21, 0 + .dw 0x4902, 0xc415, 0x4902, 0xc415, 0x22, 0 + .dw 0x4903, 0xc415, 0x490f, 0xc415, 0x21, 0 + .dw 0x4910, 0xc415, 0x4910, 0xc415, 0x22, 0 + .dw 0x4911, 0xc415, 0x4911, 0xc415, 0x21, 0 + .dw 0x4912, 0xc415, 0x4912, 0xc415, 0x22, 0 + .dw 0x4913, 0xc415, 0x493f, 0xc415, 0x21, 0 + .dw 0x4941, 0xc415, 0x4941, 0xc415, 0x21, 0 + .dw 0x4943, 0xc415, 0x494f, 0xc415, 0x21, 0 + .dw 0x4951, 0xc415, 0x4951, 0xc415, 0x21, 0 + .dw 0x4953, 0xc415, 0x497f, 0xc415, 0x21, 0 + .dw 0x4981, 0xc415, 0x4981, 0xc415, 0x21, 0 + .dw 0x4983, 0xc415, 0x498f, 0xc415, 0x21, 0 + .dw 0x4991, 0xc415, 0x4991, 0xc415, 0x21, 0 + .dw 0x4993, 0xc415, 0x49bf, 0xc415, 0x21, 0 + .dw 0x49c1, 0xc415, 0x49c1, 0xc415, 0x21, 0 + .dw 0x49c3, 0xc415, 0x49cf, 0xc415, 0x21, 0 + .dw 0x49d1, 0xc415, 0x49d1, 0xc415, 0x21, 0 + .dw 0x49d3, 0xc415, 0x49ff, 0xc415, 0x21, 0 + .dw 0x4a01, 0xc415, 0x4a01, 0xc415, 0x21, 0 + .dw 0x4a03, 0xc415, 0x4a0f, 0xc415, 0x21, 0 + .dw 0x4a11, 0xc415, 0x4a11, 0xc415, 0x21, 0 + .dw 0x4a13, 0xc415, 0x4a3f, 0xc415, 0x21, 0 + .dw 0x4a41, 0xc415, 0x4a41, 0xc415, 0x21, 0 + .dw 0x4a43, 0xc415, 0x4a4f, 0xc415, 0x21, 0 + .dw 0x4a51, 0xc415, 0x4a51, 0xc415, 0x21, 0 + .dw 0x4a53, 0xc415, 0x4a7f, 0xc415, 0x21, 0 + .dw 0x4a81, 0xc415, 0x4a81, 0xc415, 0x21, 0 + .dw 0x4a83, 0xc415, 0x4a8f, 0xc415, 0x21, 0 + .dw 0x4a91, 0xc415, 0x4a91, 0xc415, 0x21, 0 + .dw 0x4a93, 0xc415, 0x4abf, 0xc415, 0x21, 0 + .dw 0x4ac1, 0xc415, 0x4ac1, 0xc415, 0x21, 0 + .dw 0x4ac3, 0xc415, 0x4acf, 0xc415, 0x21, 0 + .dw 0x4ad1, 0xc415, 0x4ad1, 0xc415, 0x21, 0 + .dw 0x4ad3, 0xc415, 0x4aff, 0xc415, 0x21, 0 + .dw 0x4b01, 0xc415, 0x4b01, 0xc415, 0x21, 0 + .dw 0x4b03, 0xc415, 0x4b0f, 0xc415, 0x21, 0 + .dw 0x4b11, 0xc415, 0x4b11, 0xc415, 0x21, 0 + .dw 0x4b13, 0xc415, 0x4b3f, 0xc415, 0x21, 0 + .dw 0x4b40, 0xc415, 0x4b40, 0xc415, 0x22, 0 + .dw 0x4b41, 0xc415, 0x4b41, 0xc415, 0x21, 0 + .dw 0x4b42, 0xc415, 0x4b42, 0xc415, 0x22, 0 + .dw 0x4b43, 0xc415, 0x4b4f, 0xc415, 0x21, 0 + .dw 0x4b50, 0xc415, 0x4b50, 0xc415, 0x22, 0 + .dw 0x4b51, 0xc415, 0x4b51, 0xc415, 0x21, 0 + .dw 0x4b52, 0xc415, 0x4b52, 0xc415, 0x22, 0 + .dw 0x4b53, 0xc415, 0x4b7f, 0xc415, 0x21, 0 + .dw 0x4b81, 0xc415, 0x4b81, 0xc415, 0x21, 0 + .dw 0x4b83, 0xc415, 0x4b8f, 0xc415, 0x21, 0 + .dw 0x4b91, 0xc415, 0x4b91, 0xc415, 0x21, 0 + .dw 0x4b93, 0xc415, 0x4bbf, 0xc415, 0x21, 0 + .dw 0x4bc1, 0xc415, 0x4bc1, 0xc415, 0x21, 0 + .dw 0x4bc3, 0xc415, 0x4bcf, 0xc415, 0x21, 0 + .dw 0x4bd1, 0xc415, 0x4bd1, 0xc415, 0x21, 0 + .dw 0x4bd3, 0xc415, 0x4bff, 0xc415, 0x21, 0 + .dw 0x4c01, 0xc415, 0x4c01, 0xc415, 0x21, 0 + .dw 0x4c03, 0xc415, 0x4c0f, 0xc415, 0x21, 0 + .dw 0x4c11, 0xc415, 0x4c11, 0xc415, 0x21, 0 + .dw 0x4c13, 0xc415, 0x4c3f, 0xc415, 0x21, 0 + .dw 0x4c41, 0xc415, 0x4c41, 0xc415, 0x21, 0 + .dw 0x4c43, 0xc415, 0x4c4f, 0xc415, 0x21, 0 + .dw 0x4c51, 0xc415, 0x4c51, 0xc415, 0x21, 0 + .dw 0x4c53, 0xc415, 0x4c7f, 0xc415, 0x21, 0 + .dw 0x4c81, 0xc415, 0x4c81, 0xc415, 0x21, 0 + .dw 0x4c83, 0xc415, 0x4c8f, 0xc415, 0x21, 0 + .dw 0x4c91, 0xc415, 0x4c91, 0xc415, 0x21, 0 + .dw 0x4c93, 0xc415, 0x4cbf, 0xc415, 0x21, 0 + .dw 0x4cc1, 0xc415, 0x4cc1, 0xc415, 0x21, 0 + .dw 0x4cc3, 0xc415, 0x4ccf, 0xc415, 0x21, 0 + .dw 0x4cd1, 0xc415, 0x4cd1, 0xc415, 0x21, 0 + .dw 0x4cd3, 0xc415, 0x4cff, 0xc415, 0x21, 0 + .dw 0x4d01, 0xc415, 0x4d01, 0xc415, 0x21, 0 + .dw 0x4d03, 0xc415, 0x4d0f, 0xc415, 0x21, 0 + .dw 0x4d11, 0xc415, 0x4d11, 0xc415, 0x21, 0 + .dw 0x4d13, 0xc415, 0x4d3f, 0xc415, 0x21, 0 + .dw 0x4d41, 0xc415, 0x4d41, 0xc415, 0x21, 0 + .dw 0x4d43, 0xc415, 0x4d4f, 0xc415, 0x21, 0 + .dw 0x4d51, 0xc415, 0x4d51, 0xc415, 0x21, 0 + .dw 0x4d53, 0xc415, 0x4d7f, 0xc415, 0x21, 0 + .dw 0x4d80, 0xc415, 0x4d80, 0xc415, 0x22, 0 + .dw 0x4d81, 0xc415, 0x4d81, 0xc415, 0x21, 0 + .dw 0x4d82, 0xc415, 0x4d82, 0xc415, 0x22, 0 + .dw 0x4d83, 0xc415, 0x4d8f, 0xc415, 0x21, 0 + .dw 0x4d90, 0xc415, 0x4d90, 0xc415, 0x22, 0 + .dw 0x4d91, 0xc415, 0x4d91, 0xc415, 0x21, 0 + .dw 0x4d92, 0xc415, 0x4d92, 0xc415, 0x22, 0 + .dw 0x4d93, 0xc415, 0x4dbf, 0xc415, 0x21, 0 + .dw 0x4dc1, 0xc415, 0x4dc1, 0xc415, 0x21, 0 + .dw 0x4dc3, 0xc415, 0x4dcf, 0xc415, 0x21, 0 + .dw 0x4dd1, 0xc415, 0x4dd1, 0xc415, 0x21, 0 + .dw 0x4dd3, 0xc415, 0x4dff, 0xc415, 0x21, 0 + .dw 0x4e01, 0xc415, 0x4e01, 0xc415, 0x21, 0 + .dw 0x4e03, 0xc415, 0x4e0f, 0xc415, 0x21, 0 + .dw 0x4e11, 0xc415, 0x4e11, 0xc415, 0x21, 0 + .dw 0x4e13, 0xc415, 0x4e3f, 0xc415, 0x21, 0 + .dw 0x4e41, 0xc415, 0x4e41, 0xc415, 0x21, 0 + .dw 0x4e43, 0xc415, 0x4e4f, 0xc415, 0x21, 0 + .dw 0x4e51, 0xc415, 0x4e51, 0xc415, 0x21, 0 + .dw 0x4e53, 0xc415, 0x4e7f, 0xc415, 0x21, 0 + .dw 0x4e81, 0xc415, 0x4e81, 0xc415, 0x21, 0 + .dw 0x4e83, 0xc415, 0x4e8f, 0xc415, 0x21, 0 + .dw 0x4e91, 0xc415, 0x4e91, 0xc415, 0x21, 0 + .dw 0x4e93, 0xc415, 0x4ebf, 0xc415, 0x21, 0 + .dw 0x4ec1, 0xc415, 0x4ec1, 0xc415, 0x21, 0 + .dw 0x4ec3, 0xc415, 0x4ecf, 0xc415, 0x21, 0 + .dw 0x4ed1, 0xc415, 0x4ed1, 0xc415, 0x21, 0 + .dw 0x4ed3, 0xc415, 0x4eff, 0xc415, 0x21, 0 + .dw 0x4f01, 0xc415, 0x4f01, 0xc415, 0x21, 0 + .dw 0x4f03, 0xc415, 0x4f0f, 0xc415, 0x21, 0 + .dw 0x4f11, 0xc415, 0x4f11, 0xc415, 0x21, 0 + .dw 0x4f13, 0xc415, 0x4f3f, 0xc415, 0x21, 0 + .dw 0x4f41, 0xc415, 0x4f41, 0xc415, 0x21, 0 + .dw 0x4f43, 0xc415, 0x4f4f, 0xc415, 0x21, 0 + .dw 0x4f51, 0xc415, 0x4f51, 0xc415, 0x21, 0 + .dw 0x4f53, 0xc415, 0x4f7f, 0xc415, 0x21, 0 + .dw 0x4f81, 0xc415, 0x4f81, 0xc415, 0x21, 0 + .dw 0x4f83, 0xc415, 0x4f8f, 0xc415, 0x21, 0 + .dw 0x4f91, 0xc415, 0x4f91, 0xc415, 0x21, 0 + .dw 0x4f93, 0xc415, 0x4fbf, 0xc415, 0x21, 0 + .dw 0x4fc0, 0xc415, 0x4fc0, 0xc415, 0x22, 0 + .dw 0x4fc1, 0xc415, 0x4fc1, 0xc415, 0x21, 0 + .dw 0x4fc2, 0xc415, 0x4fc2, 0xc415, 0x22, 0 + .dw 0x4fc3, 0xc415, 0x4fcf, 0xc415, 0x21, 0 + .dw 0x4fd0, 0xc415, 0x4fd0, 0xc415, 0x22, 0 + .dw 0x4fd1, 0xc415, 0x4fd1, 0xc415, 0x21, 0 + .dw 0x4fd2, 0xc415, 0x4fd2, 0xc415, 0x22, 0 + .dw 0x4fd3, 0xc415, 0x5fff, 0xc415, 0x21, 0 + .dw 0x6000, 0xc415, 0x6000, 0xc415, 0x22, 0 + .dw 0x6001, 0xc415, 0x6001, 0xc415, 0x21, 0 + .dw 0x6002, 0xc415, 0x6002, 0xc415, 0x22, 0 + .dw 0x6003, 0xc415, 0x600f, 0xc415, 0x21, 0 + .dw 0x6010, 0xc415, 0x6010, 0xc415, 0x22, 0 + .dw 0x6011, 0xc415, 0x6011, 0xc415, 0x21, 0 + .dw 0x6012, 0xc415, 0x6012, 0xc415, 0x22, 0 + .dw 0x6013, 0xc415, 0x603f, 0xc415, 0x21, 0 + .dw 0x6041, 0xc415, 0x6041, 0xc415, 0x21, 0 + .dw 0x6043, 0xc415, 0x604f, 0xc415, 0x21, 0 + .dw 0x6051, 0xc415, 0x6051, 0xc415, 0x21, 0 + .dw 0x6053, 0xc415, 0x607f, 0xc415, 0x21, 0 + .dw 0x6081, 0xc415, 0x6081, 0xc415, 0x21, 0 + .dw 0x6083, 0xc415, 0x608f, 0xc415, 0x21, 0 + .dw 0x6091, 0xc415, 0x6091, 0xc415, 0x21, 0 + .dw 0x6093, 0xc415, 0x60bf, 0xc415, 0x21, 0 + .dw 0x60c1, 0xc415, 0x60c1, 0xc415, 0x21, 0 + .dw 0x60c3, 0xc415, 0x60cf, 0xc415, 0x21, 0 + .dw 0x60d1, 0xc415, 0x60d1, 0xc415, 0x21, 0 + .dw 0x60d3, 0xc415, 0x60ff, 0xc415, 0x21, 0 + .dw 0x6101, 0xc415, 0x6101, 0xc415, 0x21, 0 + .dw 0x6103, 0xc415, 0x610f, 0xc415, 0x21, 0 + .dw 0x6111, 0xc415, 0x6111, 0xc415, 0x21, 0 + .dw 0x6113, 0xc415, 0x613f, 0xc415, 0x21, 0 + .dw 0x6141, 0xc415, 0x6141, 0xc415, 0x21, 0 + .dw 0x6143, 0xc415, 0x614f, 0xc415, 0x21, 0 + .dw 0x6151, 0xc415, 0x6151, 0xc415, 0x21, 0 + .dw 0x6153, 0xc415, 0x617f, 0xc415, 0x21, 0 + .dw 0x6181, 0xc415, 0x6181, 0xc415, 0x21, 0 + .dw 0x6183, 0xc415, 0x618f, 0xc415, 0x21, 0 + .dw 0x6191, 0xc415, 0x6191, 0xc415, 0x21, 0 + .dw 0x6193, 0xc415, 0x61bf, 0xc415, 0x21, 0 + .dw 0x61c1, 0xc415, 0x61c1, 0xc415, 0x21, 0 + .dw 0x61c3, 0xc415, 0x61cf, 0xc415, 0x21, 0 + .dw 0x61d1, 0xc415, 0x61d1, 0xc415, 0x21, 0 + .dw 0x61d3, 0xc415, 0x61ff, 0xc415, 0x21, 0 + .dw 0x6201, 0xc415, 0x6201, 0xc415, 0x21, 0 + .dw 0x6203, 0xc415, 0x620f, 0xc415, 0x21, 0 + .dw 0x6211, 0xc415, 0x6211, 0xc415, 0x21, 0 + .dw 0x6213, 0xc415, 0x623f, 0xc415, 0x21, 0 + .dw 0x6240, 0xc415, 0x6240, 0xc415, 0x22, 0 + .dw 0x6241, 0xc415, 0x6241, 0xc415, 0x21, 0 + .dw 0x6242, 0xc415, 0x6242, 0xc415, 0x22, 0 + .dw 0x6243, 0xc415, 0x624f, 0xc415, 0x21, 0 + .dw 0x6250, 0xc415, 0x6250, 0xc415, 0x22, 0 + .dw 0x6251, 0xc415, 0x6251, 0xc415, 0x21, 0 + .dw 0x6252, 0xc415, 0x6252, 0xc415, 0x22, 0 + .dw 0x6253, 0xc415, 0x627f, 0xc415, 0x21, 0 + .dw 0x6281, 0xc415, 0x6281, 0xc415, 0x21, 0 + .dw 0x6283, 0xc415, 0x628f, 0xc415, 0x21, 0 + .dw 0x6291, 0xc415, 0x6291, 0xc415, 0x21, 0 + .dw 0x6293, 0xc415, 0x62bf, 0xc415, 0x21, 0 + .dw 0x62c1, 0xc415, 0x62c1, 0xc415, 0x21, 0 + .dw 0x62c3, 0xc415, 0x62cf, 0xc415, 0x21, 0 + .dw 0x62d1, 0xc415, 0x62d1, 0xc415, 0x21, 0 + .dw 0x62d3, 0xc415, 0x62ff, 0xc415, 0x21, 0 + .dw 0x6301, 0xc415, 0x6301, 0xc415, 0x21, 0 + .dw 0x6303, 0xc415, 0x630f, 0xc415, 0x21, 0 + .dw 0x6311, 0xc415, 0x6311, 0xc415, 0x21, 0 + .dw 0x6313, 0xc415, 0x633f, 0xc415, 0x21, 0 + .dw 0x6341, 0xc415, 0x6341, 0xc415, 0x21, 0 + .dw 0x6343, 0xc415, 0x634f, 0xc415, 0x21, 0 + .dw 0x6351, 0xc415, 0x6351, 0xc415, 0x21, 0 + .dw 0x6353, 0xc415, 0x637f, 0xc415, 0x21, 0 + .dw 0x6381, 0xc415, 0x6381, 0xc415, 0x21, 0 + .dw 0x6383, 0xc415, 0x638f, 0xc415, 0x21, 0 + .dw 0x6391, 0xc415, 0x6391, 0xc415, 0x21, 0 + .dw 0x6393, 0xc415, 0x63bf, 0xc415, 0x21, 0 + .dw 0x63c1, 0xc415, 0x63c1, 0xc415, 0x21, 0 + .dw 0x63c3, 0xc415, 0x63cf, 0xc415, 0x21, 0 + .dw 0x63d1, 0xc415, 0x63d1, 0xc415, 0x21, 0 + .dw 0x63d3, 0xc415, 0x63ff, 0xc415, 0x21, 0 + .dw 0x6401, 0xc415, 0x6401, 0xc415, 0x21, 0 + .dw 0x6403, 0xc415, 0x640f, 0xc415, 0x21, 0 + .dw 0x6411, 0xc415, 0x6411, 0xc415, 0x21, 0 + .dw 0x6413, 0xc415, 0x643f, 0xc415, 0x21, 0 + .dw 0x6441, 0xc415, 0x6441, 0xc415, 0x21, 0 + .dw 0x6443, 0xc415, 0x644f, 0xc415, 0x21, 0 + .dw 0x6451, 0xc415, 0x6451, 0xc415, 0x21, 0 + .dw 0x6453, 0xc415, 0x647f, 0xc415, 0x21, 0 + .dw 0x6480, 0xc415, 0x6480, 0xc415, 0x22, 0 + .dw 0x6481, 0xc415, 0x6481, 0xc415, 0x21, 0 + .dw 0x6482, 0xc415, 0x6482, 0xc415, 0x22, 0 + .dw 0x6483, 0xc415, 0x648f, 0xc415, 0x21, 0 + .dw 0x6490, 0xc415, 0x6490, 0xc415, 0x22, 0 + .dw 0x6491, 0xc415, 0x6491, 0xc415, 0x21, 0 + .dw 0x6492, 0xc415, 0x6492, 0xc415, 0x22, 0 + .dw 0x6493, 0xc415, 0x64bf, 0xc415, 0x21, 0 + .dw 0x64c1, 0xc415, 0x64c1, 0xc415, 0x21, 0 + .dw 0x64c3, 0xc415, 0x64cf, 0xc415, 0x21, 0 + .dw 0x64d1, 0xc415, 0x64d1, 0xc415, 0x21, 0 + .dw 0x64d3, 0xc415, 0x64ff, 0xc415, 0x21, 0 + .dw 0x6501, 0xc415, 0x6501, 0xc415, 0x21, 0 + .dw 0x6503, 0xc415, 0x650f, 0xc415, 0x21, 0 + .dw 0x6511, 0xc415, 0x6511, 0xc415, 0x21, 0 + .dw 0x6513, 0xc415, 0x653f, 0xc415, 0x21, 0 + .dw 0x6541, 0xc415, 0x6541, 0xc415, 0x21, 0 + .dw 0x6543, 0xc415, 0x654f, 0xc415, 0x21, 0 + .dw 0x6551, 0xc415, 0x6551, 0xc415, 0x21, 0 + .dw 0x6553, 0xc415, 0x657f, 0xc415, 0x21, 0 + .dw 0x6581, 0xc415, 0x6581, 0xc415, 0x21, 0 + .dw 0x6583, 0xc415, 0x658f, 0xc415, 0x21, 0 + .dw 0x6591, 0xc415, 0x6591, 0xc415, 0x21, 0 + .dw 0x6593, 0xc415, 0x65bf, 0xc415, 0x21, 0 + .dw 0x65c1, 0xc415, 0x65c1, 0xc415, 0x21, 0 + .dw 0x65c3, 0xc415, 0x65cf, 0xc415, 0x21, 0 + .dw 0x65d1, 0xc415, 0x65d1, 0xc415, 0x21, 0 + .dw 0x65d3, 0xc415, 0x65ff, 0xc415, 0x21, 0 + .dw 0x6601, 0xc415, 0x6601, 0xc415, 0x21, 0 + .dw 0x6603, 0xc415, 0x660f, 0xc415, 0x21, 0 + .dw 0x6611, 0xc415, 0x6611, 0xc415, 0x21, 0 + .dw 0x6613, 0xc415, 0x663f, 0xc415, 0x21, 0 + .dw 0x6641, 0xc415, 0x6641, 0xc415, 0x21, 0 + .dw 0x6643, 0xc415, 0x664f, 0xc415, 0x21, 0 + .dw 0x6651, 0xc415, 0x6651, 0xc415, 0x21, 0 + .dw 0x6653, 0xc415, 0x667f, 0xc415, 0x21, 0 + .dw 0x6681, 0xc415, 0x6681, 0xc415, 0x21, 0 + .dw 0x6683, 0xc415, 0x668f, 0xc415, 0x21, 0 + .dw 0x6691, 0xc415, 0x6691, 0xc415, 0x21, 0 + .dw 0x6693, 0xc415, 0x66bf, 0xc415, 0x21, 0 + .dw 0x66c0, 0xc415, 0x66c0, 0xc415, 0x22, 0 + .dw 0x66c1, 0xc415, 0x66c1, 0xc415, 0x21, 0 + .dw 0x66c2, 0xc415, 0x66c2, 0xc415, 0x22, 0 + .dw 0x66c3, 0xc415, 0x66cf, 0xc415, 0x21, 0 + .dw 0x66d0, 0xc415, 0x66d0, 0xc415, 0x22, 0 + .dw 0x66d1, 0xc415, 0x66d1, 0xc415, 0x21, 0 + .dw 0x66d2, 0xc415, 0x66d2, 0xc415, 0x22, 0 + .dw 0x66d3, 0xc415, 0x66ff, 0xc415, 0x21, 0 + .dw 0x6701, 0xc415, 0x6701, 0xc415, 0x21, 0 + .dw 0x6703, 0xc415, 0x670f, 0xc415, 0x21, 0 + .dw 0x6711, 0xc415, 0x6711, 0xc415, 0x21, 0 + .dw 0x6713, 0xc415, 0x673f, 0xc415, 0x21, 0 + .dw 0x6741, 0xc415, 0x6741, 0xc415, 0x21, 0 + .dw 0x6743, 0xc415, 0x674f, 0xc415, 0x21, 0 + .dw 0x6751, 0xc415, 0x6751, 0xc415, 0x21, 0 + .dw 0x6753, 0xc415, 0x677f, 0xc415, 0x21, 0 + .dw 0x6781, 0xc415, 0x6781, 0xc415, 0x21, 0 + .dw 0x6783, 0xc415, 0x678f, 0xc415, 0x21, 0 + .dw 0x6791, 0xc415, 0x6791, 0xc415, 0x21, 0 + .dw 0x6793, 0xc415, 0x67bf, 0xc415, 0x21, 0 + .dw 0x67c1, 0xc415, 0x67c1, 0xc415, 0x21, 0 + .dw 0x67c3, 0xc415, 0x67cf, 0xc415, 0x21, 0 + .dw 0x67d1, 0xc415, 0x67d1, 0xc415, 0x21, 0 + .dw 0x67d3, 0xc415, 0x67ff, 0xc415, 0x21, 0 + .dw 0x6801, 0xc415, 0x6801, 0xc415, 0x21, 0 + .dw 0x6803, 0xc415, 0x680f, 0xc415, 0x21, 0 + .dw 0x6811, 0xc415, 0x6811, 0xc415, 0x21, 0 + .dw 0x6813, 0xc415, 0x683f, 0xc415, 0x21, 0 + .dw 0x6841, 0xc415, 0x6841, 0xc415, 0x21, 0 + .dw 0x6843, 0xc415, 0x684f, 0xc415, 0x21, 0 + .dw 0x6851, 0xc415, 0x6851, 0xc415, 0x21, 0 + .dw 0x6853, 0xc415, 0x687f, 0xc415, 0x21, 0 + .dw 0x6881, 0xc415, 0x6881, 0xc415, 0x21, 0 + .dw 0x6883, 0xc415, 0x688f, 0xc415, 0x21, 0 + .dw 0x6891, 0xc415, 0x6891, 0xc415, 0x21, 0 + .dw 0x6893, 0xc415, 0x68bf, 0xc415, 0x21, 0 + .dw 0x68c1, 0xc415, 0x68c1, 0xc415, 0x21, 0 + .dw 0x68c3, 0xc415, 0x68cf, 0xc415, 0x21, 0 + .dw 0x68d1, 0xc415, 0x68d1, 0xc415, 0x21, 0 + .dw 0x68d3, 0xc415, 0x68ff, 0xc415, 0x21, 0 + .dw 0x6900, 0xc415, 0x6900, 0xc415, 0x22, 0 + .dw 0x6901, 0xc415, 0x6901, 0xc415, 0x21, 0 + .dw 0x6902, 0xc415, 0x6902, 0xc415, 0x22, 0 + .dw 0x6903, 0xc415, 0x690f, 0xc415, 0x21, 0 + .dw 0x6910, 0xc415, 0x6910, 0xc415, 0x22, 0 + .dw 0x6911, 0xc415, 0x6911, 0xc415, 0x21, 0 + .dw 0x6912, 0xc415, 0x6912, 0xc415, 0x22, 0 + .dw 0x6913, 0xc415, 0x693f, 0xc415, 0x21, 0 + .dw 0x6941, 0xc415, 0x6941, 0xc415, 0x21, 0 + .dw 0x6943, 0xc415, 0x694f, 0xc415, 0x21, 0 + .dw 0x6951, 0xc415, 0x6951, 0xc415, 0x21, 0 + .dw 0x6953, 0xc415, 0x697f, 0xc415, 0x21, 0 + .dw 0x6981, 0xc415, 0x6981, 0xc415, 0x21, 0 + .dw 0x6983, 0xc415, 0x698f, 0xc415, 0x21, 0 + .dw 0x6991, 0xc415, 0x6991, 0xc415, 0x21, 0 + .dw 0x6993, 0xc415, 0x69bf, 0xc415, 0x21, 0 + .dw 0x69c1, 0xc415, 0x69c1, 0xc415, 0x21, 0 + .dw 0x69c3, 0xc415, 0x69cf, 0xc415, 0x21, 0 + .dw 0x69d1, 0xc415, 0x69d1, 0xc415, 0x21, 0 + .dw 0x69d3, 0xc415, 0x69ff, 0xc415, 0x21, 0 + .dw 0x6a01, 0xc415, 0x6a01, 0xc415, 0x21, 0 + .dw 0x6a03, 0xc415, 0x6a0f, 0xc415, 0x21, 0 + .dw 0x6a11, 0xc415, 0x6a11, 0xc415, 0x21, 0 + .dw 0x6a13, 0xc415, 0x6a3f, 0xc415, 0x21, 0 + .dw 0x6a41, 0xc415, 0x6a41, 0xc415, 0x21, 0 + .dw 0x6a43, 0xc415, 0x6a4f, 0xc415, 0x21, 0 + .dw 0x6a51, 0xc415, 0x6a51, 0xc415, 0x21, 0 + .dw 0x6a53, 0xc415, 0x6a7f, 0xc415, 0x21, 0 + .dw 0x6a81, 0xc415, 0x6a81, 0xc415, 0x21, 0 + .dw 0x6a83, 0xc415, 0x6a8f, 0xc415, 0x21, 0 + .dw 0x6a91, 0xc415, 0x6a91, 0xc415, 0x21, 0 + .dw 0x6a93, 0xc415, 0x6abf, 0xc415, 0x21, 0 + .dw 0x6ac1, 0xc415, 0x6ac1, 0xc415, 0x21, 0 + .dw 0x6ac3, 0xc415, 0x6acf, 0xc415, 0x21, 0 + .dw 0x6ad1, 0xc415, 0x6ad1, 0xc415, 0x21, 0 + .dw 0x6ad3, 0xc415, 0x6aff, 0xc415, 0x21, 0 + .dw 0x6b01, 0xc415, 0x6b01, 0xc415, 0x21, 0 + .dw 0x6b03, 0xc415, 0x6b0f, 0xc415, 0x21, 0 + .dw 0x6b11, 0xc415, 0x6b11, 0xc415, 0x21, 0 + .dw 0x6b13, 0xc415, 0x6b3f, 0xc415, 0x21, 0 + .dw 0x6b40, 0xc415, 0x6b40, 0xc415, 0x22, 0 + .dw 0x6b41, 0xc415, 0x6b41, 0xc415, 0x21, 0 + .dw 0x6b42, 0xc415, 0x6b42, 0xc415, 0x22, 0 + .dw 0x6b43, 0xc415, 0x6b4f, 0xc415, 0x21, 0 + .dw 0x6b50, 0xc415, 0x6b50, 0xc415, 0x22, 0 + .dw 0x6b51, 0xc415, 0x6b51, 0xc415, 0x21, 0 + .dw 0x6b52, 0xc415, 0x6b52, 0xc415, 0x22, 0 + .dw 0x6b53, 0xc415, 0x6b7f, 0xc415, 0x21, 0 + .dw 0x6b81, 0xc415, 0x6b81, 0xc415, 0x21, 0 + .dw 0x6b83, 0xc415, 0x6b8f, 0xc415, 0x21, 0 + .dw 0x6b91, 0xc415, 0x6b91, 0xc415, 0x21, 0 + .dw 0x6b93, 0xc415, 0x6bbf, 0xc415, 0x21, 0 + .dw 0x6bc1, 0xc415, 0x6bc1, 0xc415, 0x21, 0 + .dw 0x6bc3, 0xc415, 0x6bcf, 0xc415, 0x21, 0 + .dw 0x6bd1, 0xc415, 0x6bd1, 0xc415, 0x21, 0 + .dw 0x6bd3, 0xc415, 0x6bff, 0xc415, 0x21, 0 + .dw 0x6c01, 0xc415, 0x6c01, 0xc415, 0x21, 0 + .dw 0x6c03, 0xc415, 0x6c0f, 0xc415, 0x21, 0 + .dw 0x6c11, 0xc415, 0x6c11, 0xc415, 0x21, 0 + .dw 0x6c13, 0xc415, 0x6c3f, 0xc415, 0x21, 0 + .dw 0x6c41, 0xc415, 0x6c41, 0xc415, 0x21, 0 + .dw 0x6c43, 0xc415, 0x6c4f, 0xc415, 0x21, 0 + .dw 0x6c51, 0xc415, 0x6c51, 0xc415, 0x21, 0 + .dw 0x6c53, 0xc415, 0x6c7f, 0xc415, 0x21, 0 + .dw 0x6c81, 0xc415, 0x6c81, 0xc415, 0x21, 0 + .dw 0x6c83, 0xc415, 0x6c8f, 0xc415, 0x21, 0 + .dw 0x6c91, 0xc415, 0x6c91, 0xc415, 0x21, 0 + .dw 0x6c93, 0xc415, 0x6cbf, 0xc415, 0x21, 0 + .dw 0x6cc1, 0xc415, 0x6cc1, 0xc415, 0x21, 0 + .dw 0x6cc3, 0xc415, 0x6ccf, 0xc415, 0x21, 0 + .dw 0x6cd1, 0xc415, 0x6cd1, 0xc415, 0x21, 0 + .dw 0x6cd3, 0xc415, 0x6cff, 0xc415, 0x21, 0 + .dw 0x6d01, 0xc415, 0x6d01, 0xc415, 0x21, 0 + .dw 0x6d03, 0xc415, 0x6d0f, 0xc415, 0x21, 0 + .dw 0x6d11, 0xc415, 0x6d11, 0xc415, 0x21, 0 + .dw 0x6d13, 0xc415, 0x6d3f, 0xc415, 0x21, 0 + .dw 0x6d41, 0xc415, 0x6d41, 0xc415, 0x21, 0 + .dw 0x6d43, 0xc415, 0x6d4f, 0xc415, 0x21, 0 + .dw 0x6d51, 0xc415, 0x6d51, 0xc415, 0x21, 0 + .dw 0x6d53, 0xc415, 0x6d7f, 0xc415, 0x21, 0 + .dw 0x6d80, 0xc415, 0x6d80, 0xc415, 0x22, 0 + .dw 0x6d81, 0xc415, 0x6d81, 0xc415, 0x21, 0 + .dw 0x6d82, 0xc415, 0x6d82, 0xc415, 0x22, 0 + .dw 0x6d83, 0xc415, 0x6d8f, 0xc415, 0x21, 0 + .dw 0x6d90, 0xc415, 0x6d90, 0xc415, 0x22, 0 + .dw 0x6d91, 0xc415, 0x6d91, 0xc415, 0x21, 0 + .dw 0x6d92, 0xc415, 0x6d92, 0xc415, 0x22, 0 + .dw 0x6d93, 0xc415, 0x6dbf, 0xc415, 0x21, 0 + .dw 0x6dc1, 0xc415, 0x6dc1, 0xc415, 0x21, 0 + .dw 0x6dc3, 0xc415, 0x6dcf, 0xc415, 0x21, 0 + .dw 0x6dd1, 0xc415, 0x6dd1, 0xc415, 0x21, 0 + .dw 0x6dd3, 0xc415, 0x6dff, 0xc415, 0x21, 0 + .dw 0x6e01, 0xc415, 0x6e01, 0xc415, 0x21, 0 + .dw 0x6e03, 0xc415, 0x6e0f, 0xc415, 0x21, 0 + .dw 0x6e11, 0xc415, 0x6e11, 0xc415, 0x21, 0 + .dw 0x6e13, 0xc415, 0x6e3f, 0xc415, 0x21, 0 + .dw 0x6e41, 0xc415, 0x6e41, 0xc415, 0x21, 0 + .dw 0x6e43, 0xc415, 0x6e4f, 0xc415, 0x21, 0 + .dw 0x6e51, 0xc415, 0x6e51, 0xc415, 0x21, 0 + .dw 0x6e53, 0xc415, 0x6e7f, 0xc415, 0x21, 0 + .dw 0x6e81, 0xc415, 0x6e81, 0xc415, 0x21, 0 + .dw 0x6e83, 0xc415, 0x6e8f, 0xc415, 0x21, 0 + .dw 0x6e91, 0xc415, 0x6e91, 0xc415, 0x21, 0 + .dw 0x6e93, 0xc415, 0x6ebf, 0xc415, 0x21, 0 + .dw 0x6ec1, 0xc415, 0x6ec1, 0xc415, 0x21, 0 + .dw 0x6ec3, 0xc415, 0x6ecf, 0xc415, 0x21, 0 + .dw 0x6ed1, 0xc415, 0x6ed1, 0xc415, 0x21, 0 + .dw 0x6ed3, 0xc415, 0x6eff, 0xc415, 0x21, 0 + .dw 0x6f01, 0xc415, 0x6f01, 0xc415, 0x21, 0 + .dw 0x6f03, 0xc415, 0x6f0f, 0xc415, 0x21, 0 + .dw 0x6f11, 0xc415, 0x6f11, 0xc415, 0x21, 0 + .dw 0x6f13, 0xc415, 0x6f3f, 0xc415, 0x21, 0 + .dw 0x6f41, 0xc415, 0x6f41, 0xc415, 0x21, 0 + .dw 0x6f43, 0xc415, 0x6f4f, 0xc415, 0x21, 0 + .dw 0x6f51, 0xc415, 0x6f51, 0xc415, 0x21, 0 + .dw 0x6f53, 0xc415, 0x6f7f, 0xc415, 0x21, 0 + .dw 0x6f81, 0xc415, 0x6f81, 0xc415, 0x21, 0 + .dw 0x6f83, 0xc415, 0x6f8f, 0xc415, 0x21, 0 + .dw 0x6f91, 0xc415, 0x6f91, 0xc415, 0x21, 0 + .dw 0x6f93, 0xc415, 0x6fbf, 0xc415, 0x21, 0 + .dw 0x6fc0, 0xc415, 0x6fc0, 0xc415, 0x22, 0 + .dw 0x6fc1, 0xc415, 0x6fc1, 0xc415, 0x21, 0 + .dw 0x6fc2, 0xc415, 0x6fc2, 0xc415, 0x22, 0 + .dw 0x6fc3, 0xc415, 0x6fcf, 0xc415, 0x21, 0 + .dw 0x6fd0, 0xc415, 0x6fd0, 0xc415, 0x22, 0 + .dw 0x6fd1, 0xc415, 0x6fd1, 0xc415, 0x21, 0 + .dw 0x6fd2, 0xc415, 0x6fd2, 0xc415, 0x22, 0 + .dw 0x6fd3, 0xc415, 0xffff, 0xc415, 0x21, 0 + .dw 0x0001, 0xc416, 0x0001, 0xc416, 0x21, 0 + .dw 0x0003, 0xc416, 0x000f, 0xc416, 0x21, 0 + .dw 0x0011, 0xc416, 0x0011, 0xc416, 0x21, 0 + .dw 0x0013, 0xc416, 0x003f, 0xc416, 0x21, 0 + .dw 0x0041, 0xc416, 0x0041, 0xc416, 0x21, 0 + .dw 0x0043, 0xc416, 0x004f, 0xc416, 0x21, 0 + .dw 0x0051, 0xc416, 0x0051, 0xc416, 0x21, 0 + .dw 0x0053, 0xc416, 0x007f, 0xc416, 0x21, 0 + .dw 0x0081, 0xc416, 0x0081, 0xc416, 0x21, 0 + .dw 0x0083, 0xc416, 0x008f, 0xc416, 0x21, 0 + .dw 0x0091, 0xc416, 0x0091, 0xc416, 0x21, 0 + .dw 0x0093, 0xc416, 0x00bf, 0xc416, 0x21, 0 + .dw 0x00c1, 0xc416, 0x00c1, 0xc416, 0x21, 0 + .dw 0x00c3, 0xc416, 0x00cf, 0xc416, 0x21, 0 + .dw 0x00d1, 0xc416, 0x00d1, 0xc416, 0x21, 0 + .dw 0x00d3, 0xc416, 0x00ff, 0xc416, 0x21, 0 + .dw 0x0101, 0xc416, 0x0101, 0xc416, 0x21, 0 + .dw 0x0103, 0xc416, 0x010f, 0xc416, 0x21, 0 + .dw 0x0111, 0xc416, 0x0111, 0xc416, 0x21, 0 + .dw 0x0113, 0xc416, 0x013f, 0xc416, 0x21, 0 + .dw 0x0141, 0xc416, 0x0141, 0xc416, 0x21, 0 + .dw 0x0143, 0xc416, 0x014f, 0xc416, 0x21, 0 + .dw 0x0151, 0xc416, 0x0151, 0xc416, 0x21, 0 + .dw 0x0153, 0xc416, 0x017f, 0xc416, 0x21, 0 + .dw 0x0181, 0xc416, 0x0181, 0xc416, 0x21, 0 + .dw 0x0183, 0xc416, 0x018f, 0xc416, 0x21, 0 + .dw 0x0191, 0xc416, 0x0191, 0xc416, 0x21, 0 + .dw 0x0193, 0xc416, 0x01bf, 0xc416, 0x21, 0 + .dw 0x01c1, 0xc416, 0x01c1, 0xc416, 0x21, 0 + .dw 0x01c3, 0xc416, 0x01cf, 0xc416, 0x21, 0 + .dw 0x01d1, 0xc416, 0x01d1, 0xc416, 0x21, 0 + .dw 0x01d3, 0xc416, 0x01ff, 0xc416, 0x21, 0 + .dw 0x0201, 0xc416, 0x0201, 0xc416, 0x21, 0 + .dw 0x0203, 0xc416, 0x020f, 0xc416, 0x21, 0 + .dw 0x0211, 0xc416, 0x0211, 0xc416, 0x21, 0 + .dw 0x0213, 0xc416, 0x023f, 0xc416, 0x21, 0 + .dw 0x0241, 0xc416, 0x0241, 0xc416, 0x21, 0 + .dw 0x0243, 0xc416, 0x024f, 0xc416, 0x21, 0 + .dw 0x0251, 0xc416, 0x0251, 0xc416, 0x21, 0 + .dw 0x0253, 0xc416, 0x027f, 0xc416, 0x21, 0 + .dw 0x0281, 0xc416, 0x0281, 0xc416, 0x21, 0 + .dw 0x0283, 0xc416, 0x028f, 0xc416, 0x21, 0 + .dw 0x0291, 0xc416, 0x0291, 0xc416, 0x21, 0 + .dw 0x0293, 0xc416, 0x02bf, 0xc416, 0x21, 0 + .dw 0x02c1, 0xc416, 0x02c1, 0xc416, 0x21, 0 + .dw 0x02c3, 0xc416, 0x02cf, 0xc416, 0x21, 0 + .dw 0x02d1, 0xc416, 0x02d1, 0xc416, 0x21, 0 + .dw 0x02d3, 0xc416, 0x02ff, 0xc416, 0x21, 0 + .dw 0x0301, 0xc416, 0x0301, 0xc416, 0x21, 0 + .dw 0x0303, 0xc416, 0x030f, 0xc416, 0x21, 0 + .dw 0x0311, 0xc416, 0x0311, 0xc416, 0x21, 0 + .dw 0x0313, 0xc416, 0x033f, 0xc416, 0x21, 0 + .dw 0x0341, 0xc416, 0x0341, 0xc416, 0x21, 0 + .dw 0x0343, 0xc416, 0x034f, 0xc416, 0x21, 0 + .dw 0x0351, 0xc416, 0x0351, 0xc416, 0x21, 0 + .dw 0x0353, 0xc416, 0x037f, 0xc416, 0x21, 0 + .dw 0x0381, 0xc416, 0x0381, 0xc416, 0x21, 0 + .dw 0x0383, 0xc416, 0x038f, 0xc416, 0x21, 0 + .dw 0x0391, 0xc416, 0x0391, 0xc416, 0x21, 0 + .dw 0x0393, 0xc416, 0x03bf, 0xc416, 0x21, 0 + .dw 0x03c1, 0xc416, 0x03c1, 0xc416, 0x21, 0 + .dw 0x03c3, 0xc416, 0x03cf, 0xc416, 0x21, 0 + .dw 0x03d1, 0xc416, 0x03d1, 0xc416, 0x21, 0 + .dw 0x03d3, 0xc416, 0x03ff, 0xc416, 0x21, 0 + .dw 0x0401, 0xc416, 0x0401, 0xc416, 0x21, 0 + .dw 0x0403, 0xc416, 0x040f, 0xc416, 0x21, 0 + .dw 0x0411, 0xc416, 0x0411, 0xc416, 0x21, 0 + .dw 0x0413, 0xc416, 0x043f, 0xc416, 0x21, 0 + .dw 0x0441, 0xc416, 0x0441, 0xc416, 0x21, 0 + .dw 0x0443, 0xc416, 0x044f, 0xc416, 0x21, 0 + .dw 0x0451, 0xc416, 0x0451, 0xc416, 0x21, 0 + .dw 0x0453, 0xc416, 0x047f, 0xc416, 0x21, 0 + .dw 0x0481, 0xc416, 0x0481, 0xc416, 0x21, 0 + .dw 0x0483, 0xc416, 0x048f, 0xc416, 0x21, 0 + .dw 0x0491, 0xc416, 0x0491, 0xc416, 0x21, 0 + .dw 0x0493, 0xc416, 0x04bf, 0xc416, 0x21, 0 + .dw 0x04c1, 0xc416, 0x04c1, 0xc416, 0x21, 0 + .dw 0x04c3, 0xc416, 0x04cf, 0xc416, 0x21, 0 + .dw 0x04d1, 0xc416, 0x04d1, 0xc416, 0x21, 0 + .dw 0x04d3, 0xc416, 0x04ff, 0xc416, 0x21, 0 + .dw 0x0501, 0xc416, 0x0501, 0xc416, 0x21, 0 + .dw 0x0503, 0xc416, 0x050f, 0xc416, 0x21, 0 + .dw 0x0511, 0xc416, 0x0511, 0xc416, 0x21, 0 + .dw 0x0513, 0xc416, 0x053f, 0xc416, 0x21, 0 + .dw 0x0541, 0xc416, 0x0541, 0xc416, 0x21, 0 + .dw 0x0543, 0xc416, 0x054f, 0xc416, 0x21, 0 + .dw 0x0551, 0xc416, 0x0551, 0xc416, 0x21, 0 + .dw 0x0553, 0xc416, 0x057f, 0xc416, 0x21, 0 + .dw 0x0581, 0xc416, 0x0581, 0xc416, 0x21, 0 + .dw 0x0583, 0xc416, 0x058f, 0xc416, 0x21, 0 + .dw 0x0591, 0xc416, 0x0591, 0xc416, 0x21, 0 + .dw 0x0593, 0xc416, 0x05bf, 0xc416, 0x21, 0 + .dw 0x05c1, 0xc416, 0x05c1, 0xc416, 0x21, 0 + .dw 0x05c3, 0xc416, 0x05cf, 0xc416, 0x21, 0 + .dw 0x05d1, 0xc416, 0x05d1, 0xc416, 0x21, 0 + .dw 0x05d3, 0xc416, 0x05ff, 0xc416, 0x21, 0 + .dw 0x0601, 0xc416, 0x0601, 0xc416, 0x21, 0 + .dw 0x0603, 0xc416, 0x060f, 0xc416, 0x21, 0 + .dw 0x0611, 0xc416, 0x0611, 0xc416, 0x21, 0 + .dw 0x0613, 0xc416, 0x063f, 0xc416, 0x21, 0 + .dw 0x0641, 0xc416, 0x0641, 0xc416, 0x21, 0 + .dw 0x0643, 0xc416, 0x064f, 0xc416, 0x21, 0 + .dw 0x0651, 0xc416, 0x0651, 0xc416, 0x21, 0 + .dw 0x0653, 0xc416, 0x067f, 0xc416, 0x21, 0 + .dw 0x0681, 0xc416, 0x0681, 0xc416, 0x21, 0 + .dw 0x0683, 0xc416, 0x068f, 0xc416, 0x21, 0 + .dw 0x0691, 0xc416, 0x0691, 0xc416, 0x21, 0 + .dw 0x0693, 0xc416, 0x06bf, 0xc416, 0x21, 0 + .dw 0x06c1, 0xc416, 0x06c1, 0xc416, 0x21, 0 + .dw 0x06c3, 0xc416, 0x06cf, 0xc416, 0x21, 0 + .dw 0x06d1, 0xc416, 0x06d1, 0xc416, 0x21, 0 + .dw 0x06d3, 0xc416, 0x06ff, 0xc416, 0x21, 0 + .dw 0x0701, 0xc416, 0x0701, 0xc416, 0x21, 0 + .dw 0x0703, 0xc416, 0x070f, 0xc416, 0x21, 0 + .dw 0x0711, 0xc416, 0x0711, 0xc416, 0x21, 0 + .dw 0x0713, 0xc416, 0x073f, 0xc416, 0x21, 0 + .dw 0x0741, 0xc416, 0x0741, 0xc416, 0x21, 0 + .dw 0x0743, 0xc416, 0x074f, 0xc416, 0x21, 0 + .dw 0x0751, 0xc416, 0x0751, 0xc416, 0x21, 0 + .dw 0x0753, 0xc416, 0x077f, 0xc416, 0x21, 0 + .dw 0x0781, 0xc416, 0x0781, 0xc416, 0x21, 0 + .dw 0x0783, 0xc416, 0x078f, 0xc416, 0x21, 0 + .dw 0x0791, 0xc416, 0x0791, 0xc416, 0x21, 0 + .dw 0x0793, 0xc416, 0x07bf, 0xc416, 0x21, 0 + .dw 0x07c1, 0xc416, 0x07c1, 0xc416, 0x21, 0 + .dw 0x07c3, 0xc416, 0x07cf, 0xc416, 0x21, 0 + .dw 0x07d1, 0xc416, 0x07d1, 0xc416, 0x21, 0 + .dw 0x07d3, 0xc416, 0x07ff, 0xc416, 0x21, 0 + .dw 0x0801, 0xc416, 0x0801, 0xc416, 0x21, 0 + .dw 0x0803, 0xc416, 0x080f, 0xc416, 0x21, 0 + .dw 0x0811, 0xc416, 0x0811, 0xc416, 0x21, 0 + .dw 0x0813, 0xc416, 0x083f, 0xc416, 0x21, 0 + .dw 0x0841, 0xc416, 0x0841, 0xc416, 0x21, 0 + .dw 0x0843, 0xc416, 0x084f, 0xc416, 0x21, 0 + .dw 0x0851, 0xc416, 0x0851, 0xc416, 0x21, 0 + .dw 0x0853, 0xc416, 0x087f, 0xc416, 0x21, 0 + .dw 0x0881, 0xc416, 0x0881, 0xc416, 0x21, 0 + .dw 0x0883, 0xc416, 0x088f, 0xc416, 0x21, 0 + .dw 0x0891, 0xc416, 0x0891, 0xc416, 0x21, 0 + .dw 0x0893, 0xc416, 0x08bf, 0xc416, 0x21, 0 + .dw 0x08c1, 0xc416, 0x08c1, 0xc416, 0x21, 0 + .dw 0x08c3, 0xc416, 0x08cf, 0xc416, 0x21, 0 + .dw 0x08d1, 0xc416, 0x08d1, 0xc416, 0x21, 0 + .dw 0x08d3, 0xc416, 0x08ff, 0xc416, 0x21, 0 + .dw 0x0901, 0xc416, 0x0901, 0xc416, 0x21, 0 + .dw 0x0903, 0xc416, 0x090f, 0xc416, 0x21, 0 + .dw 0x0911, 0xc416, 0x0911, 0xc416, 0x21, 0 + .dw 0x0913, 0xc416, 0x093f, 0xc416, 0x21, 0 + .dw 0x0941, 0xc416, 0x0941, 0xc416, 0x21, 0 + .dw 0x0943, 0xc416, 0x094f, 0xc416, 0x21, 0 + .dw 0x0951, 0xc416, 0x0951, 0xc416, 0x21, 0 + .dw 0x0953, 0xc416, 0x097f, 0xc416, 0x21, 0 + .dw 0x0981, 0xc416, 0x0981, 0xc416, 0x21, 0 + .dw 0x0983, 0xc416, 0x098f, 0xc416, 0x21, 0 + .dw 0x0991, 0xc416, 0x0991, 0xc416, 0x21, 0 + .dw 0x0993, 0xc416, 0x09bf, 0xc416, 0x21, 0 + .dw 0x09c1, 0xc416, 0x09c1, 0xc416, 0x21, 0 + .dw 0x09c3, 0xc416, 0x09cf, 0xc416, 0x21, 0 + .dw 0x09d1, 0xc416, 0x09d1, 0xc416, 0x21, 0 + .dw 0x09d3, 0xc416, 0x09ff, 0xc416, 0x21, 0 + .dw 0x0a01, 0xc416, 0x0a01, 0xc416, 0x21, 0 + .dw 0x0a03, 0xc416, 0x0a0f, 0xc416, 0x21, 0 + .dw 0x0a11, 0xc416, 0x0a11, 0xc416, 0x21, 0 + .dw 0x0a13, 0xc416, 0x0a3f, 0xc416, 0x21, 0 + .dw 0x0a41, 0xc416, 0x0a41, 0xc416, 0x21, 0 + .dw 0x0a43, 0xc416, 0x0a4f, 0xc416, 0x21, 0 + .dw 0x0a51, 0xc416, 0x0a51, 0xc416, 0x21, 0 + .dw 0x0a53, 0xc416, 0x0a7f, 0xc416, 0x21, 0 + .dw 0x0a81, 0xc416, 0x0a81, 0xc416, 0x21, 0 + .dw 0x0a83, 0xc416, 0x0a8f, 0xc416, 0x21, 0 + .dw 0x0a91, 0xc416, 0x0a91, 0xc416, 0x21, 0 + .dw 0x0a93, 0xc416, 0x0abf, 0xc416, 0x21, 0 + .dw 0x0ac1, 0xc416, 0x0ac1, 0xc416, 0x21, 0 + .dw 0x0ac3, 0xc416, 0x0acf, 0xc416, 0x21, 0 + .dw 0x0ad1, 0xc416, 0x0ad1, 0xc416, 0x21, 0 + .dw 0x0ad3, 0xc416, 0x0aff, 0xc416, 0x21, 0 + .dw 0x0b01, 0xc416, 0x0b01, 0xc416, 0x21, 0 + .dw 0x0b03, 0xc416, 0x0b0f, 0xc416, 0x21, 0 + .dw 0x0b11, 0xc416, 0x0b11, 0xc416, 0x21, 0 + .dw 0x0b13, 0xc416, 0x0b3f, 0xc416, 0x21, 0 + .dw 0x0b41, 0xc416, 0x0b41, 0xc416, 0x21, 0 + .dw 0x0b43, 0xc416, 0x0b4f, 0xc416, 0x21, 0 + .dw 0x0b51, 0xc416, 0x0b51, 0xc416, 0x21, 0 + .dw 0x0b53, 0xc416, 0x0b7f, 0xc416, 0x21, 0 + .dw 0x0b81, 0xc416, 0x0b81, 0xc416, 0x21, 0 + .dw 0x0b83, 0xc416, 0x0b8f, 0xc416, 0x21, 0 + .dw 0x0b91, 0xc416, 0x0b91, 0xc416, 0x21, 0 + .dw 0x0b93, 0xc416, 0x0bbf, 0xc416, 0x21, 0 + .dw 0x0bc1, 0xc416, 0x0bc1, 0xc416, 0x21, 0 + .dw 0x0bc3, 0xc416, 0x0bcf, 0xc416, 0x21, 0 + .dw 0x0bd1, 0xc416, 0x0bd1, 0xc416, 0x21, 0 + .dw 0x0bd3, 0xc416, 0x0bff, 0xc416, 0x21, 0 + .dw 0x0c01, 0xc416, 0x0c01, 0xc416, 0x21, 0 + .dw 0x0c03, 0xc416, 0x0c0f, 0xc416, 0x21, 0 + .dw 0x0c11, 0xc416, 0x0c11, 0xc416, 0x21, 0 + .dw 0x0c13, 0xc416, 0x0c3f, 0xc416, 0x21, 0 + .dw 0x0c41, 0xc416, 0x0c41, 0xc416, 0x21, 0 + .dw 0x0c43, 0xc416, 0x0c4f, 0xc416, 0x21, 0 + .dw 0x0c51, 0xc416, 0x0c51, 0xc416, 0x21, 0 + .dw 0x0c53, 0xc416, 0x0c7f, 0xc416, 0x21, 0 + .dw 0x0c81, 0xc416, 0x0c81, 0xc416, 0x21, 0 + .dw 0x0c83, 0xc416, 0x0c8f, 0xc416, 0x21, 0 + .dw 0x0c91, 0xc416, 0x0c91, 0xc416, 0x21, 0 + .dw 0x0c93, 0xc416, 0x0cbf, 0xc416, 0x21, 0 + .dw 0x0cc1, 0xc416, 0x0cc1, 0xc416, 0x21, 0 + .dw 0x0cc3, 0xc416, 0x0ccf, 0xc416, 0x21, 0 + .dw 0x0cd1, 0xc416, 0x0cd1, 0xc416, 0x21, 0 + .dw 0x0cd3, 0xc416, 0x0cff, 0xc416, 0x21, 0 + .dw 0x0d01, 0xc416, 0x0d01, 0xc416, 0x21, 0 + .dw 0x0d03, 0xc416, 0x0d0f, 0xc416, 0x21, 0 + .dw 0x0d11, 0xc416, 0x0d11, 0xc416, 0x21, 0 + .dw 0x0d13, 0xc416, 0x0d3f, 0xc416, 0x21, 0 + .dw 0x0d41, 0xc416, 0x0d41, 0xc416, 0x21, 0 + .dw 0x0d43, 0xc416, 0x0d4f, 0xc416, 0x21, 0 + .dw 0x0d51, 0xc416, 0x0d51, 0xc416, 0x21, 0 + .dw 0x0d53, 0xc416, 0x0d7f, 0xc416, 0x21, 0 + .dw 0x0d81, 0xc416, 0x0d81, 0xc416, 0x21, 0 + .dw 0x0d83, 0xc416, 0x0d8f, 0xc416, 0x21, 0 + .dw 0x0d91, 0xc416, 0x0d91, 0xc416, 0x21, 0 + .dw 0x0d93, 0xc416, 0x0dbf, 0xc416, 0x21, 0 + .dw 0x0dc1, 0xc416, 0x0dc1, 0xc416, 0x21, 0 + .dw 0x0dc3, 0xc416, 0x0dcf, 0xc416, 0x21, 0 + .dw 0x0dd1, 0xc416, 0x0dd1, 0xc416, 0x21, 0 + .dw 0x0dd3, 0xc416, 0x0dff, 0xc416, 0x21, 0 + .dw 0x0e01, 0xc416, 0x0e01, 0xc416, 0x21, 0 + .dw 0x0e03, 0xc416, 0x0e0f, 0xc416, 0x21, 0 + .dw 0x0e11, 0xc416, 0x0e11, 0xc416, 0x21, 0 + .dw 0x0e13, 0xc416, 0x0e3f, 0xc416, 0x21, 0 + .dw 0x0e41, 0xc416, 0x0e41, 0xc416, 0x21, 0 + .dw 0x0e43, 0xc416, 0x0e4f, 0xc416, 0x21, 0 + .dw 0x0e51, 0xc416, 0x0e51, 0xc416, 0x21, 0 + .dw 0x0e53, 0xc416, 0x0e7f, 0xc416, 0x21, 0 + .dw 0x0e81, 0xc416, 0x0e81, 0xc416, 0x21, 0 + .dw 0x0e83, 0xc416, 0x0e8f, 0xc416, 0x21, 0 + .dw 0x0e91, 0xc416, 0x0e91, 0xc416, 0x21, 0 + .dw 0x0e93, 0xc416, 0x0ebf, 0xc416, 0x21, 0 + .dw 0x0ec1, 0xc416, 0x0ec1, 0xc416, 0x21, 0 + .dw 0x0ec3, 0xc416, 0x0ecf, 0xc416, 0x21, 0 + .dw 0x0ed1, 0xc416, 0x0ed1, 0xc416, 0x21, 0 + .dw 0x0ed3, 0xc416, 0x0eff, 0xc416, 0x21, 0 + .dw 0x0f01, 0xc416, 0x0f01, 0xc416, 0x21, 0 + .dw 0x0f03, 0xc416, 0x0f0f, 0xc416, 0x21, 0 + .dw 0x0f11, 0xc416, 0x0f11, 0xc416, 0x21, 0 + .dw 0x0f13, 0xc416, 0x0f3f, 0xc416, 0x21, 0 + .dw 0x0f41, 0xc416, 0x0f41, 0xc416, 0x21, 0 + .dw 0x0f43, 0xc416, 0x0f4f, 0xc416, 0x21, 0 + .dw 0x0f51, 0xc416, 0x0f51, 0xc416, 0x21, 0 + .dw 0x0f53, 0xc416, 0x0f7f, 0xc416, 0x21, 0 + .dw 0x0f81, 0xc416, 0x0f81, 0xc416, 0x21, 0 + .dw 0x0f83, 0xc416, 0x0f8f, 0xc416, 0x21, 0 + .dw 0x0f91, 0xc416, 0x0f91, 0xc416, 0x21, 0 + .dw 0x0f93, 0xc416, 0x0fbf, 0xc416, 0x21, 0 + .dw 0x0fc1, 0xc416, 0x0fc1, 0xc416, 0x21, 0 + .dw 0x0fc3, 0xc416, 0x0fcf, 0xc416, 0x21, 0 + .dw 0x0fd1, 0xc416, 0x0fd1, 0xc416, 0x21, 0 + .dw 0x0fd3, 0xc416, 0x1fff, 0xc416, 0x21, 0 + .dw 0x2001, 0xc416, 0x2001, 0xc416, 0x21, 0 + .dw 0x2003, 0xc416, 0x200f, 0xc416, 0x21, 0 + .dw 0x2011, 0xc416, 0x2011, 0xc416, 0x21, 0 + .dw 0x2013, 0xc416, 0x203f, 0xc416, 0x21, 0 + .dw 0x2041, 0xc416, 0x2041, 0xc416, 0x21, 0 + .dw 0x2043, 0xc416, 0x204f, 0xc416, 0x21, 0 + .dw 0x2051, 0xc416, 0x2051, 0xc416, 0x21, 0 + .dw 0x2053, 0xc416, 0x207f, 0xc416, 0x21, 0 + .dw 0x2081, 0xc416, 0x2081, 0xc416, 0x21, 0 + .dw 0x2083, 0xc416, 0x208f, 0xc416, 0x21, 0 + .dw 0x2091, 0xc416, 0x2091, 0xc416, 0x21, 0 + .dw 0x2093, 0xc416, 0x20bf, 0xc416, 0x21, 0 + .dw 0x20c1, 0xc416, 0x20c1, 0xc416, 0x21, 0 + .dw 0x20c3, 0xc416, 0x20cf, 0xc416, 0x21, 0 + .dw 0x20d1, 0xc416, 0x20d1, 0xc416, 0x21, 0 + .dw 0x20d3, 0xc416, 0x20ff, 0xc416, 0x21, 0 + .dw 0x2101, 0xc416, 0x2101, 0xc416, 0x21, 0 + .dw 0x2103, 0xc416, 0x210f, 0xc416, 0x21, 0 + .dw 0x2111, 0xc416, 0x2111, 0xc416, 0x21, 0 + .dw 0x2113, 0xc416, 0x213f, 0xc416, 0x21, 0 + .dw 0x2141, 0xc416, 0x2141, 0xc416, 0x21, 0 + .dw 0x2143, 0xc416, 0x214f, 0xc416, 0x21, 0 + .dw 0x2151, 0xc416, 0x2151, 0xc416, 0x21, 0 + .dw 0x2153, 0xc416, 0x217f, 0xc416, 0x21, 0 + .dw 0x2181, 0xc416, 0x2181, 0xc416, 0x21, 0 + .dw 0x2183, 0xc416, 0x218f, 0xc416, 0x21, 0 + .dw 0x2191, 0xc416, 0x2191, 0xc416, 0x21, 0 + .dw 0x2193, 0xc416, 0x21bf, 0xc416, 0x21, 0 + .dw 0x21c1, 0xc416, 0x21c1, 0xc416, 0x21, 0 + .dw 0x21c3, 0xc416, 0x21cf, 0xc416, 0x21, 0 + .dw 0x21d1, 0xc416, 0x21d1, 0xc416, 0x21, 0 + .dw 0x21d3, 0xc416, 0x21ff, 0xc416, 0x21, 0 + .dw 0x2201, 0xc416, 0x2201, 0xc416, 0x21, 0 + .dw 0x2203, 0xc416, 0x220f, 0xc416, 0x21, 0 + .dw 0x2211, 0xc416, 0x2211, 0xc416, 0x21, 0 + .dw 0x2213, 0xc416, 0x223f, 0xc416, 0x21, 0 + .dw 0x2241, 0xc416, 0x2241, 0xc416, 0x21, 0 + .dw 0x2243, 0xc416, 0x224f, 0xc416, 0x21, 0 + .dw 0x2251, 0xc416, 0x2251, 0xc416, 0x21, 0 + .dw 0x2253, 0xc416, 0x227f, 0xc416, 0x21, 0 + .dw 0x2281, 0xc416, 0x2281, 0xc416, 0x21, 0 + .dw 0x2283, 0xc416, 0x228f, 0xc416, 0x21, 0 + .dw 0x2291, 0xc416, 0x2291, 0xc416, 0x21, 0 + .dw 0x2293, 0xc416, 0x22bf, 0xc416, 0x21, 0 + .dw 0x22c1, 0xc416, 0x22c1, 0xc416, 0x21, 0 + .dw 0x22c3, 0xc416, 0x22cf, 0xc416, 0x21, 0 + .dw 0x22d1, 0xc416, 0x22d1, 0xc416, 0x21, 0 + .dw 0x22d3, 0xc416, 0x22ff, 0xc416, 0x21, 0 + .dw 0x2301, 0xc416, 0x2301, 0xc416, 0x21, 0 + .dw 0x2303, 0xc416, 0x230f, 0xc416, 0x21, 0 + .dw 0x2311, 0xc416, 0x2311, 0xc416, 0x21, 0 + .dw 0x2313, 0xc416, 0x233f, 0xc416, 0x21, 0 + .dw 0x2341, 0xc416, 0x2341, 0xc416, 0x21, 0 + .dw 0x2343, 0xc416, 0x234f, 0xc416, 0x21, 0 + .dw 0x2351, 0xc416, 0x2351, 0xc416, 0x21, 0 + .dw 0x2353, 0xc416, 0x237f, 0xc416, 0x21, 0 + .dw 0x2381, 0xc416, 0x2381, 0xc416, 0x21, 0 + .dw 0x2383, 0xc416, 0x238f, 0xc416, 0x21, 0 + .dw 0x2391, 0xc416, 0x2391, 0xc416, 0x21, 0 + .dw 0x2393, 0xc416, 0x23bf, 0xc416, 0x21, 0 + .dw 0x23c1, 0xc416, 0x23c1, 0xc416, 0x21, 0 + .dw 0x23c3, 0xc416, 0x23cf, 0xc416, 0x21, 0 + .dw 0x23d1, 0xc416, 0x23d1, 0xc416, 0x21, 0 + .dw 0x23d3, 0xc416, 0x23ff, 0xc416, 0x21, 0 + .dw 0x2401, 0xc416, 0x2401, 0xc416, 0x21, 0 + .dw 0x2403, 0xc416, 0x240f, 0xc416, 0x21, 0 + .dw 0x2411, 0xc416, 0x2411, 0xc416, 0x21, 0 + .dw 0x2413, 0xc416, 0x243f, 0xc416, 0x21, 0 + .dw 0x2441, 0xc416, 0x2441, 0xc416, 0x21, 0 + .dw 0x2443, 0xc416, 0x244f, 0xc416, 0x21, 0 + .dw 0x2451, 0xc416, 0x2451, 0xc416, 0x21, 0 + .dw 0x2453, 0xc416, 0x247f, 0xc416, 0x21, 0 + .dw 0x2481, 0xc416, 0x2481, 0xc416, 0x21, 0 + .dw 0x2483, 0xc416, 0x248f, 0xc416, 0x21, 0 + .dw 0x2491, 0xc416, 0x2491, 0xc416, 0x21, 0 + .dw 0x2493, 0xc416, 0x24bf, 0xc416, 0x21, 0 + .dw 0x24c1, 0xc416, 0x24c1, 0xc416, 0x21, 0 + .dw 0x24c3, 0xc416, 0x24cf, 0xc416, 0x21, 0 + .dw 0x24d1, 0xc416, 0x24d1, 0xc416, 0x21, 0 + .dw 0x24d3, 0xc416, 0x24ff, 0xc416, 0x21, 0 + .dw 0x2501, 0xc416, 0x2501, 0xc416, 0x21, 0 + .dw 0x2503, 0xc416, 0x250f, 0xc416, 0x21, 0 + .dw 0x2511, 0xc416, 0x2511, 0xc416, 0x21, 0 + .dw 0x2513, 0xc416, 0x253f, 0xc416, 0x21, 0 + .dw 0x2541, 0xc416, 0x2541, 0xc416, 0x21, 0 + .dw 0x2543, 0xc416, 0x254f, 0xc416, 0x21, 0 + .dw 0x2551, 0xc416, 0x2551, 0xc416, 0x21, 0 + .dw 0x2553, 0xc416, 0x257f, 0xc416, 0x21, 0 + .dw 0x2581, 0xc416, 0x2581, 0xc416, 0x21, 0 + .dw 0x2583, 0xc416, 0x258f, 0xc416, 0x21, 0 + .dw 0x2591, 0xc416, 0x2591, 0xc416, 0x21, 0 + .dw 0x2593, 0xc416, 0x25bf, 0xc416, 0x21, 0 + .dw 0x25c1, 0xc416, 0x25c1, 0xc416, 0x21, 0 + .dw 0x25c3, 0xc416, 0x25cf, 0xc416, 0x21, 0 + .dw 0x25d1, 0xc416, 0x25d1, 0xc416, 0x21, 0 + .dw 0x25d3, 0xc416, 0x25ff, 0xc416, 0x21, 0 + .dw 0x2601, 0xc416, 0x2601, 0xc416, 0x21, 0 + .dw 0x2603, 0xc416, 0x260f, 0xc416, 0x21, 0 + .dw 0x2611, 0xc416, 0x2611, 0xc416, 0x21, 0 + .dw 0x2613, 0xc416, 0x263f, 0xc416, 0x21, 0 + .dw 0x2641, 0xc416, 0x2641, 0xc416, 0x21, 0 + .dw 0x2643, 0xc416, 0x264f, 0xc416, 0x21, 0 + .dw 0x2651, 0xc416, 0x2651, 0xc416, 0x21, 0 + .dw 0x2653, 0xc416, 0x267f, 0xc416, 0x21, 0 + .dw 0x2681, 0xc416, 0x2681, 0xc416, 0x21, 0 + .dw 0x2683, 0xc416, 0x268f, 0xc416, 0x21, 0 + .dw 0x2691, 0xc416, 0x2691, 0xc416, 0x21, 0 + .dw 0x2693, 0xc416, 0x26bf, 0xc416, 0x21, 0 + .dw 0x26c1, 0xc416, 0x26c1, 0xc416, 0x21, 0 + .dw 0x26c3, 0xc416, 0x26cf, 0xc416, 0x21, 0 + .dw 0x26d1, 0xc416, 0x26d1, 0xc416, 0x21, 0 + .dw 0x26d3, 0xc416, 0x26ff, 0xc416, 0x21, 0 + .dw 0x2701, 0xc416, 0x2701, 0xc416, 0x21, 0 + .dw 0x2703, 0xc416, 0x270f, 0xc416, 0x21, 0 + .dw 0x2711, 0xc416, 0x2711, 0xc416, 0x21, 0 + .dw 0x2713, 0xc416, 0x273f, 0xc416, 0x21, 0 + .dw 0x2741, 0xc416, 0x2741, 0xc416, 0x21, 0 + .dw 0x2743, 0xc416, 0x274f, 0xc416, 0x21, 0 + .dw 0x2751, 0xc416, 0x2751, 0xc416, 0x21, 0 + .dw 0x2753, 0xc416, 0x277f, 0xc416, 0x21, 0 + .dw 0x2781, 0xc416, 0x2781, 0xc416, 0x21, 0 + .dw 0x2783, 0xc416, 0x278f, 0xc416, 0x21, 0 + .dw 0x2791, 0xc416, 0x2791, 0xc416, 0x21, 0 + .dw 0x2793, 0xc416, 0x27bf, 0xc416, 0x21, 0 + .dw 0x27c1, 0xc416, 0x27c1, 0xc416, 0x21, 0 + .dw 0x27c3, 0xc416, 0x27cf, 0xc416, 0x21, 0 + .dw 0x27d1, 0xc416, 0x27d1, 0xc416, 0x21, 0 + .dw 0x27d3, 0xc416, 0x27ff, 0xc416, 0x21, 0 + .dw 0x2801, 0xc416, 0x2801, 0xc416, 0x21, 0 + .dw 0x2803, 0xc416, 0x280f, 0xc416, 0x21, 0 + .dw 0x2811, 0xc416, 0x2811, 0xc416, 0x21, 0 + .dw 0x2813, 0xc416, 0x283f, 0xc416, 0x21, 0 + .dw 0x2841, 0xc416, 0x2841, 0xc416, 0x21, 0 + .dw 0x2843, 0xc416, 0x284f, 0xc416, 0x21, 0 + .dw 0x2851, 0xc416, 0x2851, 0xc416, 0x21, 0 + .dw 0x2853, 0xc416, 0x287f, 0xc416, 0x21, 0 + .dw 0x2881, 0xc416, 0x2881, 0xc416, 0x21, 0 + .dw 0x2883, 0xc416, 0x288f, 0xc416, 0x21, 0 + .dw 0x2891, 0xc416, 0x2891, 0xc416, 0x21, 0 + .dw 0x2893, 0xc416, 0x28bf, 0xc416, 0x21, 0 + .dw 0x28c1, 0xc416, 0x28c1, 0xc416, 0x21, 0 + .dw 0x28c3, 0xc416, 0x28cf, 0xc416, 0x21, 0 + .dw 0x28d1, 0xc416, 0x28d1, 0xc416, 0x21, 0 + .dw 0x28d3, 0xc416, 0x28ff, 0xc416, 0x21, 0 + .dw 0x2901, 0xc416, 0x2901, 0xc416, 0x21, 0 + .dw 0x2903, 0xc416, 0x290f, 0xc416, 0x21, 0 + .dw 0x2911, 0xc416, 0x2911, 0xc416, 0x21, 0 + .dw 0x2913, 0xc416, 0x293f, 0xc416, 0x21, 0 + .dw 0x2941, 0xc416, 0x2941, 0xc416, 0x21, 0 + .dw 0x2943, 0xc416, 0x294f, 0xc416, 0x21, 0 + .dw 0x2951, 0xc416, 0x2951, 0xc416, 0x21, 0 + .dw 0x2953, 0xc416, 0x297f, 0xc416, 0x21, 0 + .dw 0x2981, 0xc416, 0x2981, 0xc416, 0x21, 0 + .dw 0x2983, 0xc416, 0x298f, 0xc416, 0x21, 0 + .dw 0x2991, 0xc416, 0x2991, 0xc416, 0x21, 0 + .dw 0x2993, 0xc416, 0x29bf, 0xc416, 0x21, 0 + .dw 0x29c1, 0xc416, 0x29c1, 0xc416, 0x21, 0 + .dw 0x29c3, 0xc416, 0x29cf, 0xc416, 0x21, 0 + .dw 0x29d1, 0xc416, 0x29d1, 0xc416, 0x21, 0 + .dw 0x29d3, 0xc416, 0x29ff, 0xc416, 0x21, 0 + .dw 0x2a01, 0xc416, 0x2a01, 0xc416, 0x21, 0 + .dw 0x2a03, 0xc416, 0x2a0f, 0xc416, 0x21, 0 + .dw 0x2a11, 0xc416, 0x2a11, 0xc416, 0x21, 0 + .dw 0x2a13, 0xc416, 0x2a3f, 0xc416, 0x21, 0 + .dw 0x2a41, 0xc416, 0x2a41, 0xc416, 0x21, 0 + .dw 0x2a43, 0xc416, 0x2a4f, 0xc416, 0x21, 0 + .dw 0x2a51, 0xc416, 0x2a51, 0xc416, 0x21, 0 + .dw 0x2a53, 0xc416, 0x2a7f, 0xc416, 0x21, 0 + .dw 0x2a81, 0xc416, 0x2a81, 0xc416, 0x21, 0 + .dw 0x2a83, 0xc416, 0x2a8f, 0xc416, 0x21, 0 + .dw 0x2a91, 0xc416, 0x2a91, 0xc416, 0x21, 0 + .dw 0x2a93, 0xc416, 0x2abf, 0xc416, 0x21, 0 + .dw 0x2ac1, 0xc416, 0x2ac1, 0xc416, 0x21, 0 + .dw 0x2ac3, 0xc416, 0x2acf, 0xc416, 0x21, 0 + .dw 0x2ad1, 0xc416, 0x2ad1, 0xc416, 0x21, 0 + .dw 0x2ad3, 0xc416, 0x2aff, 0xc416, 0x21, 0 + .dw 0x2b01, 0xc416, 0x2b01, 0xc416, 0x21, 0 + .dw 0x2b03, 0xc416, 0x2b0f, 0xc416, 0x21, 0 + .dw 0x2b11, 0xc416, 0x2b11, 0xc416, 0x21, 0 + .dw 0x2b13, 0xc416, 0x2b3f, 0xc416, 0x21, 0 + .dw 0x2b41, 0xc416, 0x2b41, 0xc416, 0x21, 0 + .dw 0x2b43, 0xc416, 0x2b4f, 0xc416, 0x21, 0 + .dw 0x2b51, 0xc416, 0x2b51, 0xc416, 0x21, 0 + .dw 0x2b53, 0xc416, 0x2b7f, 0xc416, 0x21, 0 + .dw 0x2b81, 0xc416, 0x2b81, 0xc416, 0x21, 0 + .dw 0x2b83, 0xc416, 0x2b8f, 0xc416, 0x21, 0 + .dw 0x2b91, 0xc416, 0x2b91, 0xc416, 0x21, 0 + .dw 0x2b93, 0xc416, 0x2bbf, 0xc416, 0x21, 0 + .dw 0x2bc1, 0xc416, 0x2bc1, 0xc416, 0x21, 0 + .dw 0x2bc3, 0xc416, 0x2bcf, 0xc416, 0x21, 0 + .dw 0x2bd1, 0xc416, 0x2bd1, 0xc416, 0x21, 0 + .dw 0x2bd3, 0xc416, 0x2bff, 0xc416, 0x21, 0 + .dw 0x2c01, 0xc416, 0x2c01, 0xc416, 0x21, 0 + .dw 0x2c03, 0xc416, 0x2c0f, 0xc416, 0x21, 0 + .dw 0x2c11, 0xc416, 0x2c11, 0xc416, 0x21, 0 + .dw 0x2c13, 0xc416, 0x2c3f, 0xc416, 0x21, 0 + .dw 0x2c41, 0xc416, 0x2c41, 0xc416, 0x21, 0 + .dw 0x2c43, 0xc416, 0x2c4f, 0xc416, 0x21, 0 + .dw 0x2c51, 0xc416, 0x2c51, 0xc416, 0x21, 0 + .dw 0x2c53, 0xc416, 0x2c7f, 0xc416, 0x21, 0 + .dw 0x2c81, 0xc416, 0x2c81, 0xc416, 0x21, 0 + .dw 0x2c83, 0xc416, 0x2c8f, 0xc416, 0x21, 0 + .dw 0x2c91, 0xc416, 0x2c91, 0xc416, 0x21, 0 + .dw 0x2c93, 0xc416, 0x2cbf, 0xc416, 0x21, 0 + .dw 0x2cc1, 0xc416, 0x2cc1, 0xc416, 0x21, 0 + .dw 0x2cc3, 0xc416, 0x2ccf, 0xc416, 0x21, 0 + .dw 0x2cd1, 0xc416, 0x2cd1, 0xc416, 0x21, 0 + .dw 0x2cd3, 0xc416, 0x2cff, 0xc416, 0x21, 0 + .dw 0x2d01, 0xc416, 0x2d01, 0xc416, 0x21, 0 + .dw 0x2d03, 0xc416, 0x2d0f, 0xc416, 0x21, 0 + .dw 0x2d11, 0xc416, 0x2d11, 0xc416, 0x21, 0 + .dw 0x2d13, 0xc416, 0x2d3f, 0xc416, 0x21, 0 + .dw 0x2d41, 0xc416, 0x2d41, 0xc416, 0x21, 0 + .dw 0x2d43, 0xc416, 0x2d4f, 0xc416, 0x21, 0 + .dw 0x2d51, 0xc416, 0x2d51, 0xc416, 0x21, 0 + .dw 0x2d53, 0xc416, 0x2d7f, 0xc416, 0x21, 0 + .dw 0x2d81, 0xc416, 0x2d81, 0xc416, 0x21, 0 + .dw 0x2d83, 0xc416, 0x2d8f, 0xc416, 0x21, 0 + .dw 0x2d91, 0xc416, 0x2d91, 0xc416, 0x21, 0 + .dw 0x2d93, 0xc416, 0x2dbf, 0xc416, 0x21, 0 + .dw 0x2dc1, 0xc416, 0x2dc1, 0xc416, 0x21, 0 + .dw 0x2dc3, 0xc416, 0x2dcf, 0xc416, 0x21, 0 + .dw 0x2dd1, 0xc416, 0x2dd1, 0xc416, 0x21, 0 + .dw 0x2dd3, 0xc416, 0x2dff, 0xc416, 0x21, 0 + .dw 0x2e01, 0xc416, 0x2e01, 0xc416, 0x21, 0 + .dw 0x2e03, 0xc416, 0x2e0f, 0xc416, 0x21, 0 + .dw 0x2e11, 0xc416, 0x2e11, 0xc416, 0x21, 0 + .dw 0x2e13, 0xc416, 0x2e3f, 0xc416, 0x21, 0 + .dw 0x2e41, 0xc416, 0x2e41, 0xc416, 0x21, 0 + .dw 0x2e43, 0xc416, 0x2e4f, 0xc416, 0x21, 0 + .dw 0x2e51, 0xc416, 0x2e51, 0xc416, 0x21, 0 + .dw 0x2e53, 0xc416, 0x2e7f, 0xc416, 0x21, 0 + .dw 0x2e81, 0xc416, 0x2e81, 0xc416, 0x21, 0 + .dw 0x2e83, 0xc416, 0x2e8f, 0xc416, 0x21, 0 + .dw 0x2e91, 0xc416, 0x2e91, 0xc416, 0x21, 0 + .dw 0x2e93, 0xc416, 0x2ebf, 0xc416, 0x21, 0 + .dw 0x2ec1, 0xc416, 0x2ec1, 0xc416, 0x21, 0 + .dw 0x2ec3, 0xc416, 0x2ecf, 0xc416, 0x21, 0 + .dw 0x2ed1, 0xc416, 0x2ed1, 0xc416, 0x21, 0 + .dw 0x2ed3, 0xc416, 0x2eff, 0xc416, 0x21, 0 + .dw 0x2f01, 0xc416, 0x2f01, 0xc416, 0x21, 0 + .dw 0x2f03, 0xc416, 0x2f0f, 0xc416, 0x21, 0 + .dw 0x2f11, 0xc416, 0x2f11, 0xc416, 0x21, 0 + .dw 0x2f13, 0xc416, 0x2f3f, 0xc416, 0x21, 0 + .dw 0x2f41, 0xc416, 0x2f41, 0xc416, 0x21, 0 + .dw 0x2f43, 0xc416, 0x2f4f, 0xc416, 0x21, 0 + .dw 0x2f51, 0xc416, 0x2f51, 0xc416, 0x21, 0 + .dw 0x2f53, 0xc416, 0x2f7f, 0xc416, 0x21, 0 + .dw 0x2f81, 0xc416, 0x2f81, 0xc416, 0x21, 0 + .dw 0x2f83, 0xc416, 0x2f8f, 0xc416, 0x21, 0 + .dw 0x2f91, 0xc416, 0x2f91, 0xc416, 0x21, 0 + .dw 0x2f93, 0xc416, 0x2fbf, 0xc416, 0x21, 0 + .dw 0x2fc1, 0xc416, 0x2fc1, 0xc416, 0x21, 0 + .dw 0x2fc3, 0xc416, 0x2fcf, 0xc416, 0x21, 0 + .dw 0x2fd1, 0xc416, 0x2fd1, 0xc416, 0x21, 0 + .dw 0x2fd3, 0xc416, 0x3fff, 0xc416, 0x21, 0 + .dw 0x4001, 0xc416, 0x4001, 0xc416, 0x21, 0 + .dw 0x4003, 0xc416, 0x400f, 0xc416, 0x21, 0 + .dw 0x4011, 0xc416, 0x4011, 0xc416, 0x21, 0 + .dw 0x4013, 0xc416, 0x403f, 0xc416, 0x21, 0 + .dw 0x4041, 0xc416, 0x4041, 0xc416, 0x21, 0 + .dw 0x4043, 0xc416, 0x404f, 0xc416, 0x21, 0 + .dw 0x4051, 0xc416, 0x4051, 0xc416, 0x21, 0 + .dw 0x4053, 0xc416, 0x407f, 0xc416, 0x21, 0 + .dw 0x4081, 0xc416, 0x4081, 0xc416, 0x21, 0 + .dw 0x4083, 0xc416, 0x408f, 0xc416, 0x21, 0 + .dw 0x4091, 0xc416, 0x4091, 0xc416, 0x21, 0 + .dw 0x4093, 0xc416, 0x40bf, 0xc416, 0x21, 0 + .dw 0x40c1, 0xc416, 0x40c1, 0xc416, 0x21, 0 + .dw 0x40c3, 0xc416, 0x40cf, 0xc416, 0x21, 0 + .dw 0x40d1, 0xc416, 0x40d1, 0xc416, 0x21, 0 + .dw 0x40d3, 0xc416, 0x40ff, 0xc416, 0x21, 0 + .dw 0x4101, 0xc416, 0x4101, 0xc416, 0x21, 0 + .dw 0x4103, 0xc416, 0x410f, 0xc416, 0x21, 0 + .dw 0x4111, 0xc416, 0x4111, 0xc416, 0x21, 0 + .dw 0x4113, 0xc416, 0x413f, 0xc416, 0x21, 0 + .dw 0x4141, 0xc416, 0x4141, 0xc416, 0x21, 0 + .dw 0x4143, 0xc416, 0x414f, 0xc416, 0x21, 0 + .dw 0x4151, 0xc416, 0x4151, 0xc416, 0x21, 0 + .dw 0x4153, 0xc416, 0x417f, 0xc416, 0x21, 0 + .dw 0x4181, 0xc416, 0x4181, 0xc416, 0x21, 0 + .dw 0x4183, 0xc416, 0x418f, 0xc416, 0x21, 0 + .dw 0x4191, 0xc416, 0x4191, 0xc416, 0x21, 0 + .dw 0x4193, 0xc416, 0x41bf, 0xc416, 0x21, 0 + .dw 0x41c1, 0xc416, 0x41c1, 0xc416, 0x21, 0 + .dw 0x41c3, 0xc416, 0x41cf, 0xc416, 0x21, 0 + .dw 0x41d1, 0xc416, 0x41d1, 0xc416, 0x21, 0 + .dw 0x41d3, 0xc416, 0x41ff, 0xc416, 0x21, 0 + .dw 0x4201, 0xc416, 0x4201, 0xc416, 0x21, 0 + .dw 0x4203, 0xc416, 0x420f, 0xc416, 0x21, 0 + .dw 0x4211, 0xc416, 0x4211, 0xc416, 0x21, 0 + .dw 0x4213, 0xc416, 0x423f, 0xc416, 0x21, 0 + .dw 0x4241, 0xc416, 0x4241, 0xc416, 0x21, 0 + .dw 0x4243, 0xc416, 0x424f, 0xc416, 0x21, 0 + .dw 0x4251, 0xc416, 0x4251, 0xc416, 0x21, 0 + .dw 0x4253, 0xc416, 0x427f, 0xc416, 0x21, 0 + .dw 0x4281, 0xc416, 0x4281, 0xc416, 0x21, 0 + .dw 0x4283, 0xc416, 0x428f, 0xc416, 0x21, 0 + .dw 0x4291, 0xc416, 0x4291, 0xc416, 0x21, 0 + .dw 0x4293, 0xc416, 0x42bf, 0xc416, 0x21, 0 + .dw 0x42c1, 0xc416, 0x42c1, 0xc416, 0x21, 0 + .dw 0x42c3, 0xc416, 0x42cf, 0xc416, 0x21, 0 + .dw 0x42d1, 0xc416, 0x42d1, 0xc416, 0x21, 0 + .dw 0x42d3, 0xc416, 0x42ff, 0xc416, 0x21, 0 + .dw 0x4301, 0xc416, 0x4301, 0xc416, 0x21, 0 + .dw 0x4303, 0xc416, 0x430f, 0xc416, 0x21, 0 + .dw 0x4311, 0xc416, 0x4311, 0xc416, 0x21, 0 + .dw 0x4313, 0xc416, 0x433f, 0xc416, 0x21, 0 + .dw 0x4341, 0xc416, 0x4341, 0xc416, 0x21, 0 + .dw 0x4343, 0xc416, 0x434f, 0xc416, 0x21, 0 + .dw 0x4351, 0xc416, 0x4351, 0xc416, 0x21, 0 + .dw 0x4353, 0xc416, 0x437f, 0xc416, 0x21, 0 + .dw 0x4381, 0xc416, 0x4381, 0xc416, 0x21, 0 + .dw 0x4383, 0xc416, 0x438f, 0xc416, 0x21, 0 + .dw 0x4391, 0xc416, 0x4391, 0xc416, 0x21, 0 + .dw 0x4393, 0xc416, 0x43bf, 0xc416, 0x21, 0 + .dw 0x43c1, 0xc416, 0x43c1, 0xc416, 0x21, 0 + .dw 0x43c3, 0xc416, 0x43cf, 0xc416, 0x21, 0 + .dw 0x43d1, 0xc416, 0x43d1, 0xc416, 0x21, 0 + .dw 0x43d3, 0xc416, 0x43ff, 0xc416, 0x21, 0 + .dw 0x4401, 0xc416, 0x4401, 0xc416, 0x21, 0 + .dw 0x4403, 0xc416, 0x440f, 0xc416, 0x21, 0 + .dw 0x4411, 0xc416, 0x4411, 0xc416, 0x21, 0 + .dw 0x4413, 0xc416, 0x443f, 0xc416, 0x21, 0 + .dw 0x4441, 0xc416, 0x4441, 0xc416, 0x21, 0 + .dw 0x4443, 0xc416, 0x444f, 0xc416, 0x21, 0 + .dw 0x4451, 0xc416, 0x4451, 0xc416, 0x21, 0 + .dw 0x4453, 0xc416, 0x447f, 0xc416, 0x21, 0 + .dw 0x4481, 0xc416, 0x4481, 0xc416, 0x21, 0 + .dw 0x4483, 0xc416, 0x448f, 0xc416, 0x21, 0 + .dw 0x4491, 0xc416, 0x4491, 0xc416, 0x21, 0 + .dw 0x4493, 0xc416, 0x44bf, 0xc416, 0x21, 0 + .dw 0x44c1, 0xc416, 0x44c1, 0xc416, 0x21, 0 + .dw 0x44c3, 0xc416, 0x44cf, 0xc416, 0x21, 0 + .dw 0x44d1, 0xc416, 0x44d1, 0xc416, 0x21, 0 + .dw 0x44d3, 0xc416, 0x44ff, 0xc416, 0x21, 0 + .dw 0x4501, 0xc416, 0x4501, 0xc416, 0x21, 0 + .dw 0x4503, 0xc416, 0x450f, 0xc416, 0x21, 0 + .dw 0x4511, 0xc416, 0x4511, 0xc416, 0x21, 0 + .dw 0x4513, 0xc416, 0x453f, 0xc416, 0x21, 0 + .dw 0x4541, 0xc416, 0x4541, 0xc416, 0x21, 0 + .dw 0x4543, 0xc416, 0x454f, 0xc416, 0x21, 0 + .dw 0x4551, 0xc416, 0x4551, 0xc416, 0x21, 0 + .dw 0x4553, 0xc416, 0x457f, 0xc416, 0x21, 0 + .dw 0x4581, 0xc416, 0x4581, 0xc416, 0x21, 0 + .dw 0x4583, 0xc416, 0x458f, 0xc416, 0x21, 0 + .dw 0x4591, 0xc416, 0x4591, 0xc416, 0x21, 0 + .dw 0x4593, 0xc416, 0x45bf, 0xc416, 0x21, 0 + .dw 0x45c1, 0xc416, 0x45c1, 0xc416, 0x21, 0 + .dw 0x45c3, 0xc416, 0x45cf, 0xc416, 0x21, 0 + .dw 0x45d1, 0xc416, 0x45d1, 0xc416, 0x21, 0 + .dw 0x45d3, 0xc416, 0x45ff, 0xc416, 0x21, 0 + .dw 0x4601, 0xc416, 0x4601, 0xc416, 0x21, 0 + .dw 0x4603, 0xc416, 0x460f, 0xc416, 0x21, 0 + .dw 0x4611, 0xc416, 0x4611, 0xc416, 0x21, 0 + .dw 0x4613, 0xc416, 0x463f, 0xc416, 0x21, 0 + .dw 0x4641, 0xc416, 0x4641, 0xc416, 0x21, 0 + .dw 0x4643, 0xc416, 0x464f, 0xc416, 0x21, 0 + .dw 0x4651, 0xc416, 0x4651, 0xc416, 0x21, 0 + .dw 0x4653, 0xc416, 0x467f, 0xc416, 0x21, 0 + .dw 0x4681, 0xc416, 0x4681, 0xc416, 0x21, 0 + .dw 0x4683, 0xc416, 0x468f, 0xc416, 0x21, 0 + .dw 0x4691, 0xc416, 0x4691, 0xc416, 0x21, 0 + .dw 0x4693, 0xc416, 0x46bf, 0xc416, 0x21, 0 + .dw 0x46c1, 0xc416, 0x46c1, 0xc416, 0x21, 0 + .dw 0x46c3, 0xc416, 0x46cf, 0xc416, 0x21, 0 + .dw 0x46d1, 0xc416, 0x46d1, 0xc416, 0x21, 0 + .dw 0x46d3, 0xc416, 0x46ff, 0xc416, 0x21, 0 + .dw 0x4701, 0xc416, 0x4701, 0xc416, 0x21, 0 + .dw 0x4703, 0xc416, 0x470f, 0xc416, 0x21, 0 + .dw 0x4711, 0xc416, 0x4711, 0xc416, 0x21, 0 + .dw 0x4713, 0xc416, 0x473f, 0xc416, 0x21, 0 + .dw 0x4741, 0xc416, 0x4741, 0xc416, 0x21, 0 + .dw 0x4743, 0xc416, 0x474f, 0xc416, 0x21, 0 + .dw 0x4751, 0xc416, 0x4751, 0xc416, 0x21, 0 + .dw 0x4753, 0xc416, 0x477f, 0xc416, 0x21, 0 + .dw 0x4781, 0xc416, 0x4781, 0xc416, 0x21, 0 + .dw 0x4783, 0xc416, 0x478f, 0xc416, 0x21, 0 + .dw 0x4791, 0xc416, 0x4791, 0xc416, 0x21, 0 + .dw 0x4793, 0xc416, 0x47bf, 0xc416, 0x21, 0 + .dw 0x47c1, 0xc416, 0x47c1, 0xc416, 0x21, 0 + .dw 0x47c3, 0xc416, 0x47cf, 0xc416, 0x21, 0 + .dw 0x47d1, 0xc416, 0x47d1, 0xc416, 0x21, 0 + .dw 0x47d3, 0xc416, 0x47ff, 0xc416, 0x21, 0 + .dw 0x4801, 0xc416, 0x4801, 0xc416, 0x21, 0 + .dw 0x4803, 0xc416, 0x480f, 0xc416, 0x21, 0 + .dw 0x4811, 0xc416, 0x4811, 0xc416, 0x21, 0 + .dw 0x4813, 0xc416, 0x483f, 0xc416, 0x21, 0 + .dw 0x4841, 0xc416, 0x4841, 0xc416, 0x21, 0 + .dw 0x4843, 0xc416, 0x484f, 0xc416, 0x21, 0 + .dw 0x4851, 0xc416, 0x4851, 0xc416, 0x21, 0 + .dw 0x4853, 0xc416, 0x487f, 0xc416, 0x21, 0 + .dw 0x4881, 0xc416, 0x4881, 0xc416, 0x21, 0 + .dw 0x4883, 0xc416, 0x488f, 0xc416, 0x21, 0 + .dw 0x4891, 0xc416, 0x4891, 0xc416, 0x21, 0 + .dw 0x4893, 0xc416, 0x48bf, 0xc416, 0x21, 0 + .dw 0x48c1, 0xc416, 0x48c1, 0xc416, 0x21, 0 + .dw 0x48c3, 0xc416, 0x48cf, 0xc416, 0x21, 0 + .dw 0x48d1, 0xc416, 0x48d1, 0xc416, 0x21, 0 + .dw 0x48d3, 0xc416, 0x48ff, 0xc416, 0x21, 0 + .dw 0x4901, 0xc416, 0x4901, 0xc416, 0x21, 0 + .dw 0x4903, 0xc416, 0x490f, 0xc416, 0x21, 0 + .dw 0x4911, 0xc416, 0x4911, 0xc416, 0x21, 0 + .dw 0x4913, 0xc416, 0x493f, 0xc416, 0x21, 0 + .dw 0x4941, 0xc416, 0x4941, 0xc416, 0x21, 0 + .dw 0x4943, 0xc416, 0x494f, 0xc416, 0x21, 0 + .dw 0x4951, 0xc416, 0x4951, 0xc416, 0x21, 0 + .dw 0x4953, 0xc416, 0x497f, 0xc416, 0x21, 0 + .dw 0x4981, 0xc416, 0x4981, 0xc416, 0x21, 0 + .dw 0x4983, 0xc416, 0x498f, 0xc416, 0x21, 0 + .dw 0x4991, 0xc416, 0x4991, 0xc416, 0x21, 0 + .dw 0x4993, 0xc416, 0x49bf, 0xc416, 0x21, 0 + .dw 0x49c1, 0xc416, 0x49c1, 0xc416, 0x21, 0 + .dw 0x49c3, 0xc416, 0x49cf, 0xc416, 0x21, 0 + .dw 0x49d1, 0xc416, 0x49d1, 0xc416, 0x21, 0 + .dw 0x49d3, 0xc416, 0x49ff, 0xc416, 0x21, 0 + .dw 0x4a01, 0xc416, 0x4a01, 0xc416, 0x21, 0 + .dw 0x4a03, 0xc416, 0x4a0f, 0xc416, 0x21, 0 + .dw 0x4a11, 0xc416, 0x4a11, 0xc416, 0x21, 0 + .dw 0x4a13, 0xc416, 0x4a3f, 0xc416, 0x21, 0 + .dw 0x4a41, 0xc416, 0x4a41, 0xc416, 0x21, 0 + .dw 0x4a43, 0xc416, 0x4a4f, 0xc416, 0x21, 0 + .dw 0x4a51, 0xc416, 0x4a51, 0xc416, 0x21, 0 + .dw 0x4a53, 0xc416, 0x4a7f, 0xc416, 0x21, 0 + .dw 0x4a81, 0xc416, 0x4a81, 0xc416, 0x21, 0 + .dw 0x4a83, 0xc416, 0x4a8f, 0xc416, 0x21, 0 + .dw 0x4a91, 0xc416, 0x4a91, 0xc416, 0x21, 0 + .dw 0x4a93, 0xc416, 0x4abf, 0xc416, 0x21, 0 + .dw 0x4ac1, 0xc416, 0x4ac1, 0xc416, 0x21, 0 + .dw 0x4ac3, 0xc416, 0x4acf, 0xc416, 0x21, 0 + .dw 0x4ad1, 0xc416, 0x4ad1, 0xc416, 0x21, 0 + .dw 0x4ad3, 0xc416, 0x4aff, 0xc416, 0x21, 0 + .dw 0x4b01, 0xc416, 0x4b01, 0xc416, 0x21, 0 + .dw 0x4b03, 0xc416, 0x4b0f, 0xc416, 0x21, 0 + .dw 0x4b11, 0xc416, 0x4b11, 0xc416, 0x21, 0 + .dw 0x4b13, 0xc416, 0x4b3f, 0xc416, 0x21, 0 + .dw 0x4b41, 0xc416, 0x4b41, 0xc416, 0x21, 0 + .dw 0x4b43, 0xc416, 0x4b4f, 0xc416, 0x21, 0 + .dw 0x4b51, 0xc416, 0x4b51, 0xc416, 0x21, 0 + .dw 0x4b53, 0xc416, 0x4b7f, 0xc416, 0x21, 0 + .dw 0x4b81, 0xc416, 0x4b81, 0xc416, 0x21, 0 + .dw 0x4b83, 0xc416, 0x4b8f, 0xc416, 0x21, 0 + .dw 0x4b91, 0xc416, 0x4b91, 0xc416, 0x21, 0 + .dw 0x4b93, 0xc416, 0x4bbf, 0xc416, 0x21, 0 + .dw 0x4bc1, 0xc416, 0x4bc1, 0xc416, 0x21, 0 + .dw 0x4bc3, 0xc416, 0x4bcf, 0xc416, 0x21, 0 + .dw 0x4bd1, 0xc416, 0x4bd1, 0xc416, 0x21, 0 + .dw 0x4bd3, 0xc416, 0x4bff, 0xc416, 0x21, 0 + .dw 0x4c01, 0xc416, 0x4c01, 0xc416, 0x21, 0 + .dw 0x4c03, 0xc416, 0x4c0f, 0xc416, 0x21, 0 + .dw 0x4c11, 0xc416, 0x4c11, 0xc416, 0x21, 0 + .dw 0x4c13, 0xc416, 0x4c3f, 0xc416, 0x21, 0 + .dw 0x4c41, 0xc416, 0x4c41, 0xc416, 0x21, 0 + .dw 0x4c43, 0xc416, 0x4c4f, 0xc416, 0x21, 0 + .dw 0x4c51, 0xc416, 0x4c51, 0xc416, 0x21, 0 + .dw 0x4c53, 0xc416, 0x4c7f, 0xc416, 0x21, 0 + .dw 0x4c81, 0xc416, 0x4c81, 0xc416, 0x21, 0 + .dw 0x4c83, 0xc416, 0x4c8f, 0xc416, 0x21, 0 + .dw 0x4c91, 0xc416, 0x4c91, 0xc416, 0x21, 0 + .dw 0x4c93, 0xc416, 0x4cbf, 0xc416, 0x21, 0 + .dw 0x4cc1, 0xc416, 0x4cc1, 0xc416, 0x21, 0 + .dw 0x4cc3, 0xc416, 0x4ccf, 0xc416, 0x21, 0 + .dw 0x4cd1, 0xc416, 0x4cd1, 0xc416, 0x21, 0 + .dw 0x4cd3, 0xc416, 0x4cff, 0xc416, 0x21, 0 + .dw 0x4d01, 0xc416, 0x4d01, 0xc416, 0x21, 0 + .dw 0x4d03, 0xc416, 0x4d0f, 0xc416, 0x21, 0 + .dw 0x4d11, 0xc416, 0x4d11, 0xc416, 0x21, 0 + .dw 0x4d13, 0xc416, 0x4d3f, 0xc416, 0x21, 0 + .dw 0x4d41, 0xc416, 0x4d41, 0xc416, 0x21, 0 + .dw 0x4d43, 0xc416, 0x4d4f, 0xc416, 0x21, 0 + .dw 0x4d51, 0xc416, 0x4d51, 0xc416, 0x21, 0 + .dw 0x4d53, 0xc416, 0x4d7f, 0xc416, 0x21, 0 + .dw 0x4d81, 0xc416, 0x4d81, 0xc416, 0x21, 0 + .dw 0x4d83, 0xc416, 0x4d8f, 0xc416, 0x21, 0 + .dw 0x4d91, 0xc416, 0x4d91, 0xc416, 0x21, 0 + .dw 0x4d93, 0xc416, 0x4dbf, 0xc416, 0x21, 0 + .dw 0x4dc1, 0xc416, 0x4dc1, 0xc416, 0x21, 0 + .dw 0x4dc3, 0xc416, 0x4dcf, 0xc416, 0x21, 0 + .dw 0x4dd1, 0xc416, 0x4dd1, 0xc416, 0x21, 0 + .dw 0x4dd3, 0xc416, 0x4dff, 0xc416, 0x21, 0 + .dw 0x4e01, 0xc416, 0x4e01, 0xc416, 0x21, 0 + .dw 0x4e03, 0xc416, 0x4e0f, 0xc416, 0x21, 0 + .dw 0x4e11, 0xc416, 0x4e11, 0xc416, 0x21, 0 + .dw 0x4e13, 0xc416, 0x4e3f, 0xc416, 0x21, 0 + .dw 0x4e41, 0xc416, 0x4e41, 0xc416, 0x21, 0 + .dw 0x4e43, 0xc416, 0x4e4f, 0xc416, 0x21, 0 + .dw 0x4e51, 0xc416, 0x4e51, 0xc416, 0x21, 0 + .dw 0x4e53, 0xc416, 0x4e7f, 0xc416, 0x21, 0 + .dw 0x4e81, 0xc416, 0x4e81, 0xc416, 0x21, 0 + .dw 0x4e83, 0xc416, 0x4e8f, 0xc416, 0x21, 0 + .dw 0x4e91, 0xc416, 0x4e91, 0xc416, 0x21, 0 + .dw 0x4e93, 0xc416, 0x4ebf, 0xc416, 0x21, 0 + .dw 0x4ec1, 0xc416, 0x4ec1, 0xc416, 0x21, 0 + .dw 0x4ec3, 0xc416, 0x4ecf, 0xc416, 0x21, 0 + .dw 0x4ed1, 0xc416, 0x4ed1, 0xc416, 0x21, 0 + .dw 0x4ed3, 0xc416, 0x4eff, 0xc416, 0x21, 0 + .dw 0x4f01, 0xc416, 0x4f01, 0xc416, 0x21, 0 + .dw 0x4f03, 0xc416, 0x4f0f, 0xc416, 0x21, 0 + .dw 0x4f11, 0xc416, 0x4f11, 0xc416, 0x21, 0 + .dw 0x4f13, 0xc416, 0x4f3f, 0xc416, 0x21, 0 + .dw 0x4f41, 0xc416, 0x4f41, 0xc416, 0x21, 0 + .dw 0x4f43, 0xc416, 0x4f4f, 0xc416, 0x21, 0 + .dw 0x4f51, 0xc416, 0x4f51, 0xc416, 0x21, 0 + .dw 0x4f53, 0xc416, 0x4f7f, 0xc416, 0x21, 0 + .dw 0x4f81, 0xc416, 0x4f81, 0xc416, 0x21, 0 + .dw 0x4f83, 0xc416, 0x4f8f, 0xc416, 0x21, 0 + .dw 0x4f91, 0xc416, 0x4f91, 0xc416, 0x21, 0 + .dw 0x4f93, 0xc416, 0x4fbf, 0xc416, 0x21, 0 + .dw 0x4fc1, 0xc416, 0x4fc1, 0xc416, 0x21, 0 + .dw 0x4fc3, 0xc416, 0x4fcf, 0xc416, 0x21, 0 + .dw 0x4fd1, 0xc416, 0x4fd1, 0xc416, 0x21, 0 + .dw 0x4fd3, 0xc416, 0x5fff, 0xc416, 0x21, 0 + .dw 0x6001, 0xc416, 0x6001, 0xc416, 0x21, 0 + .dw 0x6003, 0xc416, 0x600f, 0xc416, 0x21, 0 + .dw 0x6011, 0xc416, 0x6011, 0xc416, 0x21, 0 + .dw 0x6013, 0xc416, 0x603f, 0xc416, 0x21, 0 + .dw 0x6041, 0xc416, 0x6041, 0xc416, 0x21, 0 + .dw 0x6043, 0xc416, 0x604f, 0xc416, 0x21, 0 + .dw 0x6051, 0xc416, 0x6051, 0xc416, 0x21, 0 + .dw 0x6053, 0xc416, 0x607f, 0xc416, 0x21, 0 + .dw 0x6081, 0xc416, 0x6081, 0xc416, 0x21, 0 + .dw 0x6083, 0xc416, 0x608f, 0xc416, 0x21, 0 + .dw 0x6091, 0xc416, 0x6091, 0xc416, 0x21, 0 + .dw 0x6093, 0xc416, 0x60bf, 0xc416, 0x21, 0 + .dw 0x60c1, 0xc416, 0x60c1, 0xc416, 0x21, 0 + .dw 0x60c3, 0xc416, 0x60cf, 0xc416, 0x21, 0 + .dw 0x60d1, 0xc416, 0x60d1, 0xc416, 0x21, 0 + .dw 0x60d3, 0xc416, 0x60ff, 0xc416, 0x21, 0 + .dw 0x6101, 0xc416, 0x6101, 0xc416, 0x21, 0 + .dw 0x6103, 0xc416, 0x610f, 0xc416, 0x21, 0 + .dw 0x6111, 0xc416, 0x6111, 0xc416, 0x21, 0 + .dw 0x6113, 0xc416, 0x613f, 0xc416, 0x21, 0 + .dw 0x6141, 0xc416, 0x6141, 0xc416, 0x21, 0 + .dw 0x6143, 0xc416, 0x614f, 0xc416, 0x21, 0 + .dw 0x6151, 0xc416, 0x6151, 0xc416, 0x21, 0 + .dw 0x6153, 0xc416, 0x617f, 0xc416, 0x21, 0 + .dw 0x6181, 0xc416, 0x6181, 0xc416, 0x21, 0 + .dw 0x6183, 0xc416, 0x618f, 0xc416, 0x21, 0 + .dw 0x6191, 0xc416, 0x6191, 0xc416, 0x21, 0 + .dw 0x6193, 0xc416, 0x61bf, 0xc416, 0x21, 0 + .dw 0x61c1, 0xc416, 0x61c1, 0xc416, 0x21, 0 + .dw 0x61c3, 0xc416, 0x61cf, 0xc416, 0x21, 0 + .dw 0x61d1, 0xc416, 0x61d1, 0xc416, 0x21, 0 + .dw 0x61d3, 0xc416, 0x61ff, 0xc416, 0x21, 0 + .dw 0x6201, 0xc416, 0x6201, 0xc416, 0x21, 0 + .dw 0x6203, 0xc416, 0x620f, 0xc416, 0x21, 0 + .dw 0x6211, 0xc416, 0x6211, 0xc416, 0x21, 0 + .dw 0x6213, 0xc416, 0x623f, 0xc416, 0x21, 0 + .dw 0x6241, 0xc416, 0x6241, 0xc416, 0x21, 0 + .dw 0x6243, 0xc416, 0x624f, 0xc416, 0x21, 0 + .dw 0x6251, 0xc416, 0x6251, 0xc416, 0x21, 0 + .dw 0x6253, 0xc416, 0x627f, 0xc416, 0x21, 0 + .dw 0x6281, 0xc416, 0x6281, 0xc416, 0x21, 0 + .dw 0x6283, 0xc416, 0x628f, 0xc416, 0x21, 0 + .dw 0x6291, 0xc416, 0x6291, 0xc416, 0x21, 0 + .dw 0x6293, 0xc416, 0x62bf, 0xc416, 0x21, 0 + .dw 0x62c1, 0xc416, 0x62c1, 0xc416, 0x21, 0 + .dw 0x62c3, 0xc416, 0x62cf, 0xc416, 0x21, 0 + .dw 0x62d1, 0xc416, 0x62d1, 0xc416, 0x21, 0 + .dw 0x62d3, 0xc416, 0x62ff, 0xc416, 0x21, 0 + .dw 0x6301, 0xc416, 0x6301, 0xc416, 0x21, 0 + .dw 0x6303, 0xc416, 0x630f, 0xc416, 0x21, 0 + .dw 0x6311, 0xc416, 0x6311, 0xc416, 0x21, 0 + .dw 0x6313, 0xc416, 0x633f, 0xc416, 0x21, 0 + .dw 0x6341, 0xc416, 0x6341, 0xc416, 0x21, 0 + .dw 0x6343, 0xc416, 0x634f, 0xc416, 0x21, 0 + .dw 0x6351, 0xc416, 0x6351, 0xc416, 0x21, 0 + .dw 0x6353, 0xc416, 0x637f, 0xc416, 0x21, 0 + .dw 0x6381, 0xc416, 0x6381, 0xc416, 0x21, 0 + .dw 0x6383, 0xc416, 0x638f, 0xc416, 0x21, 0 + .dw 0x6391, 0xc416, 0x6391, 0xc416, 0x21, 0 + .dw 0x6393, 0xc416, 0x63bf, 0xc416, 0x21, 0 + .dw 0x63c1, 0xc416, 0x63c1, 0xc416, 0x21, 0 + .dw 0x63c3, 0xc416, 0x63cf, 0xc416, 0x21, 0 + .dw 0x63d1, 0xc416, 0x63d1, 0xc416, 0x21, 0 + .dw 0x63d3, 0xc416, 0x63ff, 0xc416, 0x21, 0 + .dw 0x6401, 0xc416, 0x6401, 0xc416, 0x21, 0 + .dw 0x6403, 0xc416, 0x640f, 0xc416, 0x21, 0 + .dw 0x6411, 0xc416, 0x6411, 0xc416, 0x21, 0 + .dw 0x6413, 0xc416, 0x643f, 0xc416, 0x21, 0 + .dw 0x6441, 0xc416, 0x6441, 0xc416, 0x21, 0 + .dw 0x6443, 0xc416, 0x644f, 0xc416, 0x21, 0 + .dw 0x6451, 0xc416, 0x6451, 0xc416, 0x21, 0 + .dw 0x6453, 0xc416, 0x647f, 0xc416, 0x21, 0 + .dw 0x6481, 0xc416, 0x6481, 0xc416, 0x21, 0 + .dw 0x6483, 0xc416, 0x648f, 0xc416, 0x21, 0 + .dw 0x6491, 0xc416, 0x6491, 0xc416, 0x21, 0 + .dw 0x6493, 0xc416, 0x64bf, 0xc416, 0x21, 0 + .dw 0x64c1, 0xc416, 0x64c1, 0xc416, 0x21, 0 + .dw 0x64c3, 0xc416, 0x64cf, 0xc416, 0x21, 0 + .dw 0x64d1, 0xc416, 0x64d1, 0xc416, 0x21, 0 + .dw 0x64d3, 0xc416, 0x64ff, 0xc416, 0x21, 0 + .dw 0x6501, 0xc416, 0x6501, 0xc416, 0x21, 0 + .dw 0x6503, 0xc416, 0x650f, 0xc416, 0x21, 0 + .dw 0x6511, 0xc416, 0x6511, 0xc416, 0x21, 0 + .dw 0x6513, 0xc416, 0x653f, 0xc416, 0x21, 0 + .dw 0x6541, 0xc416, 0x6541, 0xc416, 0x21, 0 + .dw 0x6543, 0xc416, 0x654f, 0xc416, 0x21, 0 + .dw 0x6551, 0xc416, 0x6551, 0xc416, 0x21, 0 + .dw 0x6553, 0xc416, 0x657f, 0xc416, 0x21, 0 + .dw 0x6581, 0xc416, 0x6581, 0xc416, 0x21, 0 + .dw 0x6583, 0xc416, 0x658f, 0xc416, 0x21, 0 + .dw 0x6591, 0xc416, 0x6591, 0xc416, 0x21, 0 + .dw 0x6593, 0xc416, 0x65bf, 0xc416, 0x21, 0 + .dw 0x65c1, 0xc416, 0x65c1, 0xc416, 0x21, 0 + .dw 0x65c3, 0xc416, 0x65cf, 0xc416, 0x21, 0 + .dw 0x65d1, 0xc416, 0x65d1, 0xc416, 0x21, 0 + .dw 0x65d3, 0xc416, 0x65ff, 0xc416, 0x21, 0 + .dw 0x6601, 0xc416, 0x6601, 0xc416, 0x21, 0 + .dw 0x6603, 0xc416, 0x660f, 0xc416, 0x21, 0 + .dw 0x6611, 0xc416, 0x6611, 0xc416, 0x21, 0 + .dw 0x6613, 0xc416, 0x663f, 0xc416, 0x21, 0 + .dw 0x6641, 0xc416, 0x6641, 0xc416, 0x21, 0 + .dw 0x6643, 0xc416, 0x664f, 0xc416, 0x21, 0 + .dw 0x6651, 0xc416, 0x6651, 0xc416, 0x21, 0 + .dw 0x6653, 0xc416, 0x667f, 0xc416, 0x21, 0 + .dw 0x6681, 0xc416, 0x6681, 0xc416, 0x21, 0 + .dw 0x6683, 0xc416, 0x668f, 0xc416, 0x21, 0 + .dw 0x6691, 0xc416, 0x6691, 0xc416, 0x21, 0 + .dw 0x6693, 0xc416, 0x66bf, 0xc416, 0x21, 0 + .dw 0x66c1, 0xc416, 0x66c1, 0xc416, 0x21, 0 + .dw 0x66c3, 0xc416, 0x66cf, 0xc416, 0x21, 0 + .dw 0x66d1, 0xc416, 0x66d1, 0xc416, 0x21, 0 + .dw 0x66d3, 0xc416, 0x66ff, 0xc416, 0x21, 0 + .dw 0x6701, 0xc416, 0x6701, 0xc416, 0x21, 0 + .dw 0x6703, 0xc416, 0x670f, 0xc416, 0x21, 0 + .dw 0x6711, 0xc416, 0x6711, 0xc416, 0x21, 0 + .dw 0x6713, 0xc416, 0x673f, 0xc416, 0x21, 0 + .dw 0x6741, 0xc416, 0x6741, 0xc416, 0x21, 0 + .dw 0x6743, 0xc416, 0x674f, 0xc416, 0x21, 0 + .dw 0x6751, 0xc416, 0x6751, 0xc416, 0x21, 0 + .dw 0x6753, 0xc416, 0x677f, 0xc416, 0x21, 0 + .dw 0x6781, 0xc416, 0x6781, 0xc416, 0x21, 0 + .dw 0x6783, 0xc416, 0x678f, 0xc416, 0x21, 0 + .dw 0x6791, 0xc416, 0x6791, 0xc416, 0x21, 0 + .dw 0x6793, 0xc416, 0x67bf, 0xc416, 0x21, 0 + .dw 0x67c1, 0xc416, 0x67c1, 0xc416, 0x21, 0 + .dw 0x67c3, 0xc416, 0x67cf, 0xc416, 0x21, 0 + .dw 0x67d1, 0xc416, 0x67d1, 0xc416, 0x21, 0 + .dw 0x67d3, 0xc416, 0x67ff, 0xc416, 0x21, 0 + .dw 0x6801, 0xc416, 0x6801, 0xc416, 0x21, 0 + .dw 0x6803, 0xc416, 0x680f, 0xc416, 0x21, 0 + .dw 0x6811, 0xc416, 0x6811, 0xc416, 0x21, 0 + .dw 0x6813, 0xc416, 0x683f, 0xc416, 0x21, 0 + .dw 0x6841, 0xc416, 0x6841, 0xc416, 0x21, 0 + .dw 0x6843, 0xc416, 0x684f, 0xc416, 0x21, 0 + .dw 0x6851, 0xc416, 0x6851, 0xc416, 0x21, 0 + .dw 0x6853, 0xc416, 0x687f, 0xc416, 0x21, 0 + .dw 0x6881, 0xc416, 0x6881, 0xc416, 0x21, 0 + .dw 0x6883, 0xc416, 0x688f, 0xc416, 0x21, 0 + .dw 0x6891, 0xc416, 0x6891, 0xc416, 0x21, 0 + .dw 0x6893, 0xc416, 0x68bf, 0xc416, 0x21, 0 + .dw 0x68c1, 0xc416, 0x68c1, 0xc416, 0x21, 0 + .dw 0x68c3, 0xc416, 0x68cf, 0xc416, 0x21, 0 + .dw 0x68d1, 0xc416, 0x68d1, 0xc416, 0x21, 0 + .dw 0x68d3, 0xc416, 0x68ff, 0xc416, 0x21, 0 + .dw 0x6901, 0xc416, 0x6901, 0xc416, 0x21, 0 + .dw 0x6903, 0xc416, 0x690f, 0xc416, 0x21, 0 + .dw 0x6911, 0xc416, 0x6911, 0xc416, 0x21, 0 + .dw 0x6913, 0xc416, 0x693f, 0xc416, 0x21, 0 + .dw 0x6941, 0xc416, 0x6941, 0xc416, 0x21, 0 + .dw 0x6943, 0xc416, 0x694f, 0xc416, 0x21, 0 + .dw 0x6951, 0xc416, 0x6951, 0xc416, 0x21, 0 + .dw 0x6953, 0xc416, 0x697f, 0xc416, 0x21, 0 + .dw 0x6981, 0xc416, 0x6981, 0xc416, 0x21, 0 + .dw 0x6983, 0xc416, 0x698f, 0xc416, 0x21, 0 + .dw 0x6991, 0xc416, 0x6991, 0xc416, 0x21, 0 + .dw 0x6993, 0xc416, 0x69bf, 0xc416, 0x21, 0 + .dw 0x69c1, 0xc416, 0x69c1, 0xc416, 0x21, 0 + .dw 0x69c3, 0xc416, 0x69cf, 0xc416, 0x21, 0 + .dw 0x69d1, 0xc416, 0x69d1, 0xc416, 0x21, 0 + .dw 0x69d3, 0xc416, 0x69ff, 0xc416, 0x21, 0 + .dw 0x6a01, 0xc416, 0x6a01, 0xc416, 0x21, 0 + .dw 0x6a03, 0xc416, 0x6a0f, 0xc416, 0x21, 0 + .dw 0x6a11, 0xc416, 0x6a11, 0xc416, 0x21, 0 + .dw 0x6a13, 0xc416, 0x6a3f, 0xc416, 0x21, 0 + .dw 0x6a41, 0xc416, 0x6a41, 0xc416, 0x21, 0 + .dw 0x6a43, 0xc416, 0x6a4f, 0xc416, 0x21, 0 + .dw 0x6a51, 0xc416, 0x6a51, 0xc416, 0x21, 0 + .dw 0x6a53, 0xc416, 0x6a7f, 0xc416, 0x21, 0 + .dw 0x6a81, 0xc416, 0x6a81, 0xc416, 0x21, 0 + .dw 0x6a83, 0xc416, 0x6a8f, 0xc416, 0x21, 0 + .dw 0x6a91, 0xc416, 0x6a91, 0xc416, 0x21, 0 + .dw 0x6a93, 0xc416, 0x6abf, 0xc416, 0x21, 0 + .dw 0x6ac1, 0xc416, 0x6ac1, 0xc416, 0x21, 0 + .dw 0x6ac3, 0xc416, 0x6acf, 0xc416, 0x21, 0 + .dw 0x6ad1, 0xc416, 0x6ad1, 0xc416, 0x21, 0 + .dw 0x6ad3, 0xc416, 0x6aff, 0xc416, 0x21, 0 + .dw 0x6b01, 0xc416, 0x6b01, 0xc416, 0x21, 0 + .dw 0x6b03, 0xc416, 0x6b0f, 0xc416, 0x21, 0 + .dw 0x6b11, 0xc416, 0x6b11, 0xc416, 0x21, 0 + .dw 0x6b13, 0xc416, 0x6b3f, 0xc416, 0x21, 0 + .dw 0x6b41, 0xc416, 0x6b41, 0xc416, 0x21, 0 + .dw 0x6b43, 0xc416, 0x6b4f, 0xc416, 0x21, 0 + .dw 0x6b51, 0xc416, 0x6b51, 0xc416, 0x21, 0 + .dw 0x6b53, 0xc416, 0x6b7f, 0xc416, 0x21, 0 + .dw 0x6b81, 0xc416, 0x6b81, 0xc416, 0x21, 0 + .dw 0x6b83, 0xc416, 0x6b8f, 0xc416, 0x21, 0 + .dw 0x6b91, 0xc416, 0x6b91, 0xc416, 0x21, 0 + .dw 0x6b93, 0xc416, 0x6bbf, 0xc416, 0x21, 0 + .dw 0x6bc1, 0xc416, 0x6bc1, 0xc416, 0x21, 0 + .dw 0x6bc3, 0xc416, 0x6bcf, 0xc416, 0x21, 0 + .dw 0x6bd1, 0xc416, 0x6bd1, 0xc416, 0x21, 0 + .dw 0x6bd3, 0xc416, 0x6bff, 0xc416, 0x21, 0 + .dw 0x6c01, 0xc416, 0x6c01, 0xc416, 0x21, 0 + .dw 0x6c03, 0xc416, 0x6c0f, 0xc416, 0x21, 0 + .dw 0x6c11, 0xc416, 0x6c11, 0xc416, 0x21, 0 + .dw 0x6c13, 0xc416, 0x6c3f, 0xc416, 0x21, 0 + .dw 0x6c41, 0xc416, 0x6c41, 0xc416, 0x21, 0 + .dw 0x6c43, 0xc416, 0x6c4f, 0xc416, 0x21, 0 + .dw 0x6c51, 0xc416, 0x6c51, 0xc416, 0x21, 0 + .dw 0x6c53, 0xc416, 0x6c7f, 0xc416, 0x21, 0 + .dw 0x6c81, 0xc416, 0x6c81, 0xc416, 0x21, 0 + .dw 0x6c83, 0xc416, 0x6c8f, 0xc416, 0x21, 0 + .dw 0x6c91, 0xc416, 0x6c91, 0xc416, 0x21, 0 + .dw 0x6c93, 0xc416, 0x6cbf, 0xc416, 0x21, 0 + .dw 0x6cc1, 0xc416, 0x6cc1, 0xc416, 0x21, 0 + .dw 0x6cc3, 0xc416, 0x6ccf, 0xc416, 0x21, 0 + .dw 0x6cd1, 0xc416, 0x6cd1, 0xc416, 0x21, 0 + .dw 0x6cd3, 0xc416, 0x6cff, 0xc416, 0x21, 0 + .dw 0x6d01, 0xc416, 0x6d01, 0xc416, 0x21, 0 + .dw 0x6d03, 0xc416, 0x6d0f, 0xc416, 0x21, 0 + .dw 0x6d11, 0xc416, 0x6d11, 0xc416, 0x21, 0 + .dw 0x6d13, 0xc416, 0x6d3f, 0xc416, 0x21, 0 + .dw 0x6d41, 0xc416, 0x6d41, 0xc416, 0x21, 0 + .dw 0x6d43, 0xc416, 0x6d4f, 0xc416, 0x21, 0 + .dw 0x6d51, 0xc416, 0x6d51, 0xc416, 0x21, 0 + .dw 0x6d53, 0xc416, 0x6d7f, 0xc416, 0x21, 0 + .dw 0x6d81, 0xc416, 0x6d81, 0xc416, 0x21, 0 + .dw 0x6d83, 0xc416, 0x6d8f, 0xc416, 0x21, 0 + .dw 0x6d91, 0xc416, 0x6d91, 0xc416, 0x21, 0 + .dw 0x6d93, 0xc416, 0x6dbf, 0xc416, 0x21, 0 + .dw 0x6dc1, 0xc416, 0x6dc1, 0xc416, 0x21, 0 + .dw 0x6dc3, 0xc416, 0x6dcf, 0xc416, 0x21, 0 + .dw 0x6dd1, 0xc416, 0x6dd1, 0xc416, 0x21, 0 + .dw 0x6dd3, 0xc416, 0x6dff, 0xc416, 0x21, 0 + .dw 0x6e01, 0xc416, 0x6e01, 0xc416, 0x21, 0 + .dw 0x6e03, 0xc416, 0x6e0f, 0xc416, 0x21, 0 + .dw 0x6e11, 0xc416, 0x6e11, 0xc416, 0x21, 0 + .dw 0x6e13, 0xc416, 0x6e3f, 0xc416, 0x21, 0 + .dw 0x6e41, 0xc416, 0x6e41, 0xc416, 0x21, 0 + .dw 0x6e43, 0xc416, 0x6e4f, 0xc416, 0x21, 0 + .dw 0x6e51, 0xc416, 0x6e51, 0xc416, 0x21, 0 + .dw 0x6e53, 0xc416, 0x6e7f, 0xc416, 0x21, 0 + .dw 0x6e81, 0xc416, 0x6e81, 0xc416, 0x21, 0 + .dw 0x6e83, 0xc416, 0x6e8f, 0xc416, 0x21, 0 + .dw 0x6e91, 0xc416, 0x6e91, 0xc416, 0x21, 0 + .dw 0x6e93, 0xc416, 0x6ebf, 0xc416, 0x21, 0 + .dw 0x6ec1, 0xc416, 0x6ec1, 0xc416, 0x21, 0 + .dw 0x6ec3, 0xc416, 0x6ecf, 0xc416, 0x21, 0 + .dw 0x6ed1, 0xc416, 0x6ed1, 0xc416, 0x21, 0 + .dw 0x6ed3, 0xc416, 0x6eff, 0xc416, 0x21, 0 + .dw 0x6f01, 0xc416, 0x6f01, 0xc416, 0x21, 0 + .dw 0x6f03, 0xc416, 0x6f0f, 0xc416, 0x21, 0 + .dw 0x6f11, 0xc416, 0x6f11, 0xc416, 0x21, 0 + .dw 0x6f13, 0xc416, 0x6f3f, 0xc416, 0x21, 0 + .dw 0x6f41, 0xc416, 0x6f41, 0xc416, 0x21, 0 + .dw 0x6f43, 0xc416, 0x6f4f, 0xc416, 0x21, 0 + .dw 0x6f51, 0xc416, 0x6f51, 0xc416, 0x21, 0 + .dw 0x6f53, 0xc416, 0x6f7f, 0xc416, 0x21, 0 + .dw 0x6f81, 0xc416, 0x6f81, 0xc416, 0x21, 0 + .dw 0x6f83, 0xc416, 0x6f8f, 0xc416, 0x21, 0 + .dw 0x6f91, 0xc416, 0x6f91, 0xc416, 0x21, 0 + .dw 0x6f93, 0xc416, 0x6fbf, 0xc416, 0x21, 0 + .dw 0x6fc1, 0xc416, 0x6fc1, 0xc416, 0x21, 0 + .dw 0x6fc3, 0xc416, 0x6fcf, 0xc416, 0x21, 0 + .dw 0x6fd1, 0xc416, 0x6fd1, 0xc416, 0x21, 0 + .dw 0x6fd3, 0xc416, 0xffff, 0xc416, 0x21, 0 + .dw 0x0001, 0xc417, 0x0001, 0xc417, 0x21, 0 + .dw 0x0003, 0xc417, 0x000f, 0xc417, 0x21, 0 + .dw 0x0011, 0xc417, 0x0011, 0xc417, 0x21, 0 + .dw 0x0013, 0xc417, 0x003f, 0xc417, 0x21, 0 + .dw 0x0041, 0xc417, 0x0041, 0xc417, 0x21, 0 + .dw 0x0043, 0xc417, 0x004f, 0xc417, 0x21, 0 + .dw 0x0051, 0xc417, 0x0051, 0xc417, 0x21, 0 + .dw 0x0053, 0xc417, 0x007f, 0xc417, 0x21, 0 + .dw 0x0081, 0xc417, 0x0081, 0xc417, 0x21, 0 + .dw 0x0083, 0xc417, 0x008f, 0xc417, 0x21, 0 + .dw 0x0091, 0xc417, 0x0091, 0xc417, 0x21, 0 + .dw 0x0093, 0xc417, 0x00bf, 0xc417, 0x21, 0 + .dw 0x00c1, 0xc417, 0x00c1, 0xc417, 0x21, 0 + .dw 0x00c3, 0xc417, 0x00cf, 0xc417, 0x21, 0 + .dw 0x00d1, 0xc417, 0x00d1, 0xc417, 0x21, 0 + .dw 0x00d3, 0xc417, 0x00ff, 0xc417, 0x21, 0 + .dw 0x0101, 0xc417, 0x0101, 0xc417, 0x21, 0 + .dw 0x0103, 0xc417, 0x010f, 0xc417, 0x21, 0 + .dw 0x0111, 0xc417, 0x0111, 0xc417, 0x21, 0 + .dw 0x0113, 0xc417, 0x013f, 0xc417, 0x21, 0 + .dw 0x0141, 0xc417, 0x0141, 0xc417, 0x21, 0 + .dw 0x0143, 0xc417, 0x014f, 0xc417, 0x21, 0 + .dw 0x0151, 0xc417, 0x0151, 0xc417, 0x21, 0 + .dw 0x0153, 0xc417, 0x017f, 0xc417, 0x21, 0 + .dw 0x0181, 0xc417, 0x0181, 0xc417, 0x21, 0 + .dw 0x0183, 0xc417, 0x018f, 0xc417, 0x21, 0 + .dw 0x0191, 0xc417, 0x0191, 0xc417, 0x21, 0 + .dw 0x0193, 0xc417, 0x01bf, 0xc417, 0x21, 0 + .dw 0x01c1, 0xc417, 0x01c1, 0xc417, 0x21, 0 + .dw 0x01c3, 0xc417, 0x01cf, 0xc417, 0x21, 0 + .dw 0x01d1, 0xc417, 0x01d1, 0xc417, 0x21, 0 + .dw 0x01d3, 0xc417, 0x01ff, 0xc417, 0x21, 0 + .dw 0x0201, 0xc417, 0x0201, 0xc417, 0x21, 0 + .dw 0x0203, 0xc417, 0x020f, 0xc417, 0x21, 0 + .dw 0x0211, 0xc417, 0x0211, 0xc417, 0x21, 0 + .dw 0x0213, 0xc417, 0x023f, 0xc417, 0x21, 0 + .dw 0x0241, 0xc417, 0x0241, 0xc417, 0x21, 0 + .dw 0x0243, 0xc417, 0x024f, 0xc417, 0x21, 0 + .dw 0x0251, 0xc417, 0x0251, 0xc417, 0x21, 0 + .dw 0x0253, 0xc417, 0x027f, 0xc417, 0x21, 0 + .dw 0x0281, 0xc417, 0x0281, 0xc417, 0x21, 0 + .dw 0x0283, 0xc417, 0x028f, 0xc417, 0x21, 0 + .dw 0x0291, 0xc417, 0x0291, 0xc417, 0x21, 0 + .dw 0x0293, 0xc417, 0x02bf, 0xc417, 0x21, 0 + .dw 0x02c1, 0xc417, 0x02c1, 0xc417, 0x21, 0 + .dw 0x02c3, 0xc417, 0x02cf, 0xc417, 0x21, 0 + .dw 0x02d1, 0xc417, 0x02d1, 0xc417, 0x21, 0 + .dw 0x02d3, 0xc417, 0x02ff, 0xc417, 0x21, 0 + .dw 0x0301, 0xc417, 0x0301, 0xc417, 0x21, 0 + .dw 0x0303, 0xc417, 0x030f, 0xc417, 0x21, 0 + .dw 0x0311, 0xc417, 0x0311, 0xc417, 0x21, 0 + .dw 0x0313, 0xc417, 0x033f, 0xc417, 0x21, 0 + .dw 0x0341, 0xc417, 0x0341, 0xc417, 0x21, 0 + .dw 0x0343, 0xc417, 0x034f, 0xc417, 0x21, 0 + .dw 0x0351, 0xc417, 0x0351, 0xc417, 0x21, 0 + .dw 0x0353, 0xc417, 0x037f, 0xc417, 0x21, 0 + .dw 0x0381, 0xc417, 0x0381, 0xc417, 0x21, 0 + .dw 0x0383, 0xc417, 0x038f, 0xc417, 0x21, 0 + .dw 0x0391, 0xc417, 0x0391, 0xc417, 0x21, 0 + .dw 0x0393, 0xc417, 0x03bf, 0xc417, 0x21, 0 + .dw 0x03c1, 0xc417, 0x03c1, 0xc417, 0x21, 0 + .dw 0x03c3, 0xc417, 0x03cf, 0xc417, 0x21, 0 + .dw 0x03d1, 0xc417, 0x03d1, 0xc417, 0x21, 0 + .dw 0x03d3, 0xc417, 0x03ff, 0xc417, 0x21, 0 + .dw 0x0401, 0xc417, 0x0401, 0xc417, 0x21, 0 + .dw 0x0403, 0xc417, 0x040f, 0xc417, 0x21, 0 + .dw 0x0411, 0xc417, 0x0411, 0xc417, 0x21, 0 + .dw 0x0413, 0xc417, 0x043f, 0xc417, 0x21, 0 + .dw 0x0441, 0xc417, 0x0441, 0xc417, 0x21, 0 + .dw 0x0443, 0xc417, 0x044f, 0xc417, 0x21, 0 + .dw 0x0451, 0xc417, 0x0451, 0xc417, 0x21, 0 + .dw 0x0453, 0xc417, 0x047f, 0xc417, 0x21, 0 + .dw 0x0481, 0xc417, 0x0481, 0xc417, 0x21, 0 + .dw 0x0483, 0xc417, 0x048f, 0xc417, 0x21, 0 + .dw 0x0491, 0xc417, 0x0491, 0xc417, 0x21, 0 + .dw 0x0493, 0xc417, 0x04bf, 0xc417, 0x21, 0 + .dw 0x04c1, 0xc417, 0x04c1, 0xc417, 0x21, 0 + .dw 0x04c3, 0xc417, 0x04cf, 0xc417, 0x21, 0 + .dw 0x04d1, 0xc417, 0x04d1, 0xc417, 0x21, 0 + .dw 0x04d3, 0xc417, 0x04ff, 0xc417, 0x21, 0 + .dw 0x0501, 0xc417, 0x0501, 0xc417, 0x21, 0 + .dw 0x0503, 0xc417, 0x050f, 0xc417, 0x21, 0 + .dw 0x0511, 0xc417, 0x0511, 0xc417, 0x21, 0 + .dw 0x0513, 0xc417, 0x053f, 0xc417, 0x21, 0 + .dw 0x0541, 0xc417, 0x0541, 0xc417, 0x21, 0 + .dw 0x0543, 0xc417, 0x054f, 0xc417, 0x21, 0 + .dw 0x0551, 0xc417, 0x0551, 0xc417, 0x21, 0 + .dw 0x0553, 0xc417, 0x057f, 0xc417, 0x21, 0 + .dw 0x0581, 0xc417, 0x0581, 0xc417, 0x21, 0 + .dw 0x0583, 0xc417, 0x058f, 0xc417, 0x21, 0 + .dw 0x0591, 0xc417, 0x0591, 0xc417, 0x21, 0 + .dw 0x0593, 0xc417, 0x05bf, 0xc417, 0x21, 0 + .dw 0x05c1, 0xc417, 0x05c1, 0xc417, 0x21, 0 + .dw 0x05c3, 0xc417, 0x05cf, 0xc417, 0x21, 0 + .dw 0x05d1, 0xc417, 0x05d1, 0xc417, 0x21, 0 + .dw 0x05d3, 0xc417, 0x05ff, 0xc417, 0x21, 0 + .dw 0x0601, 0xc417, 0x0601, 0xc417, 0x21, 0 + .dw 0x0603, 0xc417, 0x060f, 0xc417, 0x21, 0 + .dw 0x0611, 0xc417, 0x0611, 0xc417, 0x21, 0 + .dw 0x0613, 0xc417, 0x063f, 0xc417, 0x21, 0 + .dw 0x0641, 0xc417, 0x0641, 0xc417, 0x21, 0 + .dw 0x0643, 0xc417, 0x064f, 0xc417, 0x21, 0 + .dw 0x0651, 0xc417, 0x0651, 0xc417, 0x21, 0 + .dw 0x0653, 0xc417, 0x067f, 0xc417, 0x21, 0 + .dw 0x0681, 0xc417, 0x0681, 0xc417, 0x21, 0 + .dw 0x0683, 0xc417, 0x068f, 0xc417, 0x21, 0 + .dw 0x0691, 0xc417, 0x0691, 0xc417, 0x21, 0 + .dw 0x0693, 0xc417, 0x06bf, 0xc417, 0x21, 0 + .dw 0x06c1, 0xc417, 0x06c1, 0xc417, 0x21, 0 + .dw 0x06c3, 0xc417, 0x06cf, 0xc417, 0x21, 0 + .dw 0x06d1, 0xc417, 0x06d1, 0xc417, 0x21, 0 + .dw 0x06d3, 0xc417, 0x06ff, 0xc417, 0x21, 0 + .dw 0x0701, 0xc417, 0x0701, 0xc417, 0x21, 0 + .dw 0x0703, 0xc417, 0x070f, 0xc417, 0x21, 0 + .dw 0x0711, 0xc417, 0x0711, 0xc417, 0x21, 0 + .dw 0x0713, 0xc417, 0x073f, 0xc417, 0x21, 0 + .dw 0x0741, 0xc417, 0x0741, 0xc417, 0x21, 0 + .dw 0x0743, 0xc417, 0x074f, 0xc417, 0x21, 0 + .dw 0x0751, 0xc417, 0x0751, 0xc417, 0x21, 0 + .dw 0x0753, 0xc417, 0x077f, 0xc417, 0x21, 0 + .dw 0x0781, 0xc417, 0x0781, 0xc417, 0x21, 0 + .dw 0x0783, 0xc417, 0x078f, 0xc417, 0x21, 0 + .dw 0x0791, 0xc417, 0x0791, 0xc417, 0x21, 0 + .dw 0x0793, 0xc417, 0x07bf, 0xc417, 0x21, 0 + .dw 0x07c1, 0xc417, 0x07c1, 0xc417, 0x21, 0 + .dw 0x07c3, 0xc417, 0x07cf, 0xc417, 0x21, 0 + .dw 0x07d1, 0xc417, 0x07d1, 0xc417, 0x21, 0 + .dw 0x07d3, 0xc417, 0x07ff, 0xc417, 0x21, 0 + .dw 0x0801, 0xc417, 0x0801, 0xc417, 0x21, 0 + .dw 0x0803, 0xc417, 0x080f, 0xc417, 0x21, 0 + .dw 0x0811, 0xc417, 0x0811, 0xc417, 0x21, 0 + .dw 0x0813, 0xc417, 0x083f, 0xc417, 0x21, 0 + .dw 0x0841, 0xc417, 0x0841, 0xc417, 0x21, 0 + .dw 0x0843, 0xc417, 0x084f, 0xc417, 0x21, 0 + .dw 0x0851, 0xc417, 0x0851, 0xc417, 0x21, 0 + .dw 0x0853, 0xc417, 0x087f, 0xc417, 0x21, 0 + .dw 0x0881, 0xc417, 0x0881, 0xc417, 0x21, 0 + .dw 0x0883, 0xc417, 0x088f, 0xc417, 0x21, 0 + .dw 0x0891, 0xc417, 0x0891, 0xc417, 0x21, 0 + .dw 0x0893, 0xc417, 0x08bf, 0xc417, 0x21, 0 + .dw 0x08c1, 0xc417, 0x08c1, 0xc417, 0x21, 0 + .dw 0x08c3, 0xc417, 0x08cf, 0xc417, 0x21, 0 + .dw 0x08d1, 0xc417, 0x08d1, 0xc417, 0x21, 0 + .dw 0x08d3, 0xc417, 0x08ff, 0xc417, 0x21, 0 + .dw 0x0901, 0xc417, 0x0901, 0xc417, 0x21, 0 + .dw 0x0903, 0xc417, 0x090f, 0xc417, 0x21, 0 + .dw 0x0911, 0xc417, 0x0911, 0xc417, 0x21, 0 + .dw 0x0913, 0xc417, 0x093f, 0xc417, 0x21, 0 + .dw 0x0941, 0xc417, 0x0941, 0xc417, 0x21, 0 + .dw 0x0943, 0xc417, 0x094f, 0xc417, 0x21, 0 + .dw 0x0951, 0xc417, 0x0951, 0xc417, 0x21, 0 + .dw 0x0953, 0xc417, 0x097f, 0xc417, 0x21, 0 + .dw 0x0981, 0xc417, 0x0981, 0xc417, 0x21, 0 + .dw 0x0983, 0xc417, 0x098f, 0xc417, 0x21, 0 + .dw 0x0991, 0xc417, 0x0991, 0xc417, 0x21, 0 + .dw 0x0993, 0xc417, 0x09bf, 0xc417, 0x21, 0 + .dw 0x09c1, 0xc417, 0x09c1, 0xc417, 0x21, 0 + .dw 0x09c3, 0xc417, 0x09cf, 0xc417, 0x21, 0 + .dw 0x09d1, 0xc417, 0x09d1, 0xc417, 0x21, 0 + .dw 0x09d3, 0xc417, 0x09ff, 0xc417, 0x21, 0 + .dw 0x0a01, 0xc417, 0x0a01, 0xc417, 0x21, 0 + .dw 0x0a03, 0xc417, 0x0a0f, 0xc417, 0x21, 0 + .dw 0x0a11, 0xc417, 0x0a11, 0xc417, 0x21, 0 + .dw 0x0a13, 0xc417, 0x0a3f, 0xc417, 0x21, 0 + .dw 0x0a41, 0xc417, 0x0a41, 0xc417, 0x21, 0 + .dw 0x0a43, 0xc417, 0x0a4f, 0xc417, 0x21, 0 + .dw 0x0a51, 0xc417, 0x0a51, 0xc417, 0x21, 0 + .dw 0x0a53, 0xc417, 0x0a7f, 0xc417, 0x21, 0 + .dw 0x0a81, 0xc417, 0x0a81, 0xc417, 0x21, 0 + .dw 0x0a83, 0xc417, 0x0a8f, 0xc417, 0x21, 0 + .dw 0x0a91, 0xc417, 0x0a91, 0xc417, 0x21, 0 + .dw 0x0a93, 0xc417, 0x0abf, 0xc417, 0x21, 0 + .dw 0x0ac1, 0xc417, 0x0ac1, 0xc417, 0x21, 0 + .dw 0x0ac3, 0xc417, 0x0acf, 0xc417, 0x21, 0 + .dw 0x0ad1, 0xc417, 0x0ad1, 0xc417, 0x21, 0 + .dw 0x0ad3, 0xc417, 0x0aff, 0xc417, 0x21, 0 + .dw 0x0b01, 0xc417, 0x0b01, 0xc417, 0x21, 0 + .dw 0x0b03, 0xc417, 0x0b0f, 0xc417, 0x21, 0 + .dw 0x0b11, 0xc417, 0x0b11, 0xc417, 0x21, 0 + .dw 0x0b13, 0xc417, 0x0b3f, 0xc417, 0x21, 0 + .dw 0x0b41, 0xc417, 0x0b41, 0xc417, 0x21, 0 + .dw 0x0b43, 0xc417, 0x0b4f, 0xc417, 0x21, 0 + .dw 0x0b51, 0xc417, 0x0b51, 0xc417, 0x21, 0 + .dw 0x0b53, 0xc417, 0x0b7f, 0xc417, 0x21, 0 + .dw 0x0b81, 0xc417, 0x0b81, 0xc417, 0x21, 0 + .dw 0x0b83, 0xc417, 0x0b8f, 0xc417, 0x21, 0 + .dw 0x0b91, 0xc417, 0x0b91, 0xc417, 0x21, 0 + .dw 0x0b93, 0xc417, 0x0bbf, 0xc417, 0x21, 0 + .dw 0x0bc1, 0xc417, 0x0bc1, 0xc417, 0x21, 0 + .dw 0x0bc3, 0xc417, 0x0bcf, 0xc417, 0x21, 0 + .dw 0x0bd1, 0xc417, 0x0bd1, 0xc417, 0x21, 0 + .dw 0x0bd3, 0xc417, 0x0bff, 0xc417, 0x21, 0 + .dw 0x0c01, 0xc417, 0x0c01, 0xc417, 0x21, 0 + .dw 0x0c03, 0xc417, 0x0c0f, 0xc417, 0x21, 0 + .dw 0x0c11, 0xc417, 0x0c11, 0xc417, 0x21, 0 + .dw 0x0c13, 0xc417, 0x0c3f, 0xc417, 0x21, 0 + .dw 0x0c41, 0xc417, 0x0c41, 0xc417, 0x21, 0 + .dw 0x0c43, 0xc417, 0x0c4f, 0xc417, 0x21, 0 + .dw 0x0c51, 0xc417, 0x0c51, 0xc417, 0x21, 0 + .dw 0x0c53, 0xc417, 0x0c7f, 0xc417, 0x21, 0 + .dw 0x0c81, 0xc417, 0x0c81, 0xc417, 0x21, 0 + .dw 0x0c83, 0xc417, 0x0c8f, 0xc417, 0x21, 0 + .dw 0x0c91, 0xc417, 0x0c91, 0xc417, 0x21, 0 + .dw 0x0c93, 0xc417, 0x0cbf, 0xc417, 0x21, 0 + .dw 0x0cc1, 0xc417, 0x0cc1, 0xc417, 0x21, 0 + .dw 0x0cc3, 0xc417, 0x0ccf, 0xc417, 0x21, 0 + .dw 0x0cd1, 0xc417, 0x0cd1, 0xc417, 0x21, 0 + .dw 0x0cd3, 0xc417, 0x0cff, 0xc417, 0x21, 0 + .dw 0x0d01, 0xc417, 0x0d01, 0xc417, 0x21, 0 + .dw 0x0d03, 0xc417, 0x0d0f, 0xc417, 0x21, 0 + .dw 0x0d11, 0xc417, 0x0d11, 0xc417, 0x21, 0 + .dw 0x0d13, 0xc417, 0x0d3f, 0xc417, 0x21, 0 + .dw 0x0d41, 0xc417, 0x0d41, 0xc417, 0x21, 0 + .dw 0x0d43, 0xc417, 0x0d4f, 0xc417, 0x21, 0 + .dw 0x0d51, 0xc417, 0x0d51, 0xc417, 0x21, 0 + .dw 0x0d53, 0xc417, 0x0d7f, 0xc417, 0x21, 0 + .dw 0x0d81, 0xc417, 0x0d81, 0xc417, 0x21, 0 + .dw 0x0d83, 0xc417, 0x0d8f, 0xc417, 0x21, 0 + .dw 0x0d91, 0xc417, 0x0d91, 0xc417, 0x21, 0 + .dw 0x0d93, 0xc417, 0x0dbf, 0xc417, 0x21, 0 + .dw 0x0dc1, 0xc417, 0x0dc1, 0xc417, 0x21, 0 + .dw 0x0dc3, 0xc417, 0x0dcf, 0xc417, 0x21, 0 + .dw 0x0dd1, 0xc417, 0x0dd1, 0xc417, 0x21, 0 + .dw 0x0dd3, 0xc417, 0x0dff, 0xc417, 0x21, 0 + .dw 0x0e01, 0xc417, 0x0e01, 0xc417, 0x21, 0 + .dw 0x0e03, 0xc417, 0x0e0f, 0xc417, 0x21, 0 + .dw 0x0e11, 0xc417, 0x0e11, 0xc417, 0x21, 0 + .dw 0x0e13, 0xc417, 0x0e3f, 0xc417, 0x21, 0 + .dw 0x0e41, 0xc417, 0x0e41, 0xc417, 0x21, 0 + .dw 0x0e43, 0xc417, 0x0e4f, 0xc417, 0x21, 0 + .dw 0x0e51, 0xc417, 0x0e51, 0xc417, 0x21, 0 + .dw 0x0e53, 0xc417, 0x0e7f, 0xc417, 0x21, 0 + .dw 0x0e81, 0xc417, 0x0e81, 0xc417, 0x21, 0 + .dw 0x0e83, 0xc417, 0x0e8f, 0xc417, 0x21, 0 + .dw 0x0e91, 0xc417, 0x0e91, 0xc417, 0x21, 0 + .dw 0x0e93, 0xc417, 0x0ebf, 0xc417, 0x21, 0 + .dw 0x0ec1, 0xc417, 0x0ec1, 0xc417, 0x21, 0 + .dw 0x0ec3, 0xc417, 0x0ecf, 0xc417, 0x21, 0 + .dw 0x0ed1, 0xc417, 0x0ed1, 0xc417, 0x21, 0 + .dw 0x0ed3, 0xc417, 0x0eff, 0xc417, 0x21, 0 + .dw 0x0f01, 0xc417, 0x0f01, 0xc417, 0x21, 0 + .dw 0x0f03, 0xc417, 0x0f0f, 0xc417, 0x21, 0 + .dw 0x0f11, 0xc417, 0x0f11, 0xc417, 0x21, 0 + .dw 0x0f13, 0xc417, 0x0f3f, 0xc417, 0x21, 0 + .dw 0x0f41, 0xc417, 0x0f41, 0xc417, 0x21, 0 + .dw 0x0f43, 0xc417, 0x0f4f, 0xc417, 0x21, 0 + .dw 0x0f51, 0xc417, 0x0f51, 0xc417, 0x21, 0 + .dw 0x0f53, 0xc417, 0x0f7f, 0xc417, 0x21, 0 + .dw 0x0f81, 0xc417, 0x0f81, 0xc417, 0x21, 0 + .dw 0x0f83, 0xc417, 0x0f8f, 0xc417, 0x21, 0 + .dw 0x0f91, 0xc417, 0x0f91, 0xc417, 0x21, 0 + .dw 0x0f93, 0xc417, 0x0fbf, 0xc417, 0x21, 0 + .dw 0x0fc1, 0xc417, 0x0fc1, 0xc417, 0x21, 0 + .dw 0x0fc3, 0xc417, 0x0fcf, 0xc417, 0x21, 0 + .dw 0x0fd1, 0xc417, 0x0fd1, 0xc417, 0x21, 0 + .dw 0x0fd3, 0xc417, 0x1fff, 0xc417, 0x21, 0 + .dw 0x2001, 0xc417, 0x2001, 0xc417, 0x21, 0 + .dw 0x2003, 0xc417, 0x200f, 0xc417, 0x21, 0 + .dw 0x2011, 0xc417, 0x2011, 0xc417, 0x21, 0 + .dw 0x2013, 0xc417, 0x203f, 0xc417, 0x21, 0 + .dw 0x2041, 0xc417, 0x2041, 0xc417, 0x21, 0 + .dw 0x2043, 0xc417, 0x204f, 0xc417, 0x21, 0 + .dw 0x2051, 0xc417, 0x2051, 0xc417, 0x21, 0 + .dw 0x2053, 0xc417, 0x207f, 0xc417, 0x21, 0 + .dw 0x2081, 0xc417, 0x2081, 0xc417, 0x21, 0 + .dw 0x2083, 0xc417, 0x208f, 0xc417, 0x21, 0 + .dw 0x2091, 0xc417, 0x2091, 0xc417, 0x21, 0 + .dw 0x2093, 0xc417, 0x20bf, 0xc417, 0x21, 0 + .dw 0x20c1, 0xc417, 0x20c1, 0xc417, 0x21, 0 + .dw 0x20c3, 0xc417, 0x20cf, 0xc417, 0x21, 0 + .dw 0x20d1, 0xc417, 0x20d1, 0xc417, 0x21, 0 + .dw 0x20d3, 0xc417, 0x20ff, 0xc417, 0x21, 0 + .dw 0x2101, 0xc417, 0x2101, 0xc417, 0x21, 0 + .dw 0x2103, 0xc417, 0x210f, 0xc417, 0x21, 0 + .dw 0x2111, 0xc417, 0x2111, 0xc417, 0x21, 0 + .dw 0x2113, 0xc417, 0x213f, 0xc417, 0x21, 0 + .dw 0x2141, 0xc417, 0x2141, 0xc417, 0x21, 0 + .dw 0x2143, 0xc417, 0x214f, 0xc417, 0x21, 0 + .dw 0x2151, 0xc417, 0x2151, 0xc417, 0x21, 0 + .dw 0x2153, 0xc417, 0x217f, 0xc417, 0x21, 0 + .dw 0x2181, 0xc417, 0x2181, 0xc417, 0x21, 0 + .dw 0x2183, 0xc417, 0x218f, 0xc417, 0x21, 0 + .dw 0x2191, 0xc417, 0x2191, 0xc417, 0x21, 0 + .dw 0x2193, 0xc417, 0x21bf, 0xc417, 0x21, 0 + .dw 0x21c1, 0xc417, 0x21c1, 0xc417, 0x21, 0 + .dw 0x21c3, 0xc417, 0x21cf, 0xc417, 0x21, 0 + .dw 0x21d1, 0xc417, 0x21d1, 0xc417, 0x21, 0 + .dw 0x21d3, 0xc417, 0x21ff, 0xc417, 0x21, 0 + .dw 0x2201, 0xc417, 0x2201, 0xc417, 0x21, 0 + .dw 0x2203, 0xc417, 0x220f, 0xc417, 0x21, 0 + .dw 0x2211, 0xc417, 0x2211, 0xc417, 0x21, 0 + .dw 0x2213, 0xc417, 0x223f, 0xc417, 0x21, 0 + .dw 0x2241, 0xc417, 0x2241, 0xc417, 0x21, 0 + .dw 0x2243, 0xc417, 0x224f, 0xc417, 0x21, 0 + .dw 0x2251, 0xc417, 0x2251, 0xc417, 0x21, 0 + .dw 0x2253, 0xc417, 0x227f, 0xc417, 0x21, 0 + .dw 0x2281, 0xc417, 0x2281, 0xc417, 0x21, 0 + .dw 0x2283, 0xc417, 0x228f, 0xc417, 0x21, 0 + .dw 0x2291, 0xc417, 0x2291, 0xc417, 0x21, 0 + .dw 0x2293, 0xc417, 0x22bf, 0xc417, 0x21, 0 + .dw 0x22c1, 0xc417, 0x22c1, 0xc417, 0x21, 0 + .dw 0x22c3, 0xc417, 0x22cf, 0xc417, 0x21, 0 + .dw 0x22d1, 0xc417, 0x22d1, 0xc417, 0x21, 0 + .dw 0x22d3, 0xc417, 0x22ff, 0xc417, 0x21, 0 + .dw 0x2301, 0xc417, 0x2301, 0xc417, 0x21, 0 + .dw 0x2303, 0xc417, 0x230f, 0xc417, 0x21, 0 + .dw 0x2311, 0xc417, 0x2311, 0xc417, 0x21, 0 + .dw 0x2313, 0xc417, 0x233f, 0xc417, 0x21, 0 + .dw 0x2341, 0xc417, 0x2341, 0xc417, 0x21, 0 + .dw 0x2343, 0xc417, 0x234f, 0xc417, 0x21, 0 + .dw 0x2351, 0xc417, 0x2351, 0xc417, 0x21, 0 + .dw 0x2353, 0xc417, 0x237f, 0xc417, 0x21, 0 + .dw 0x2381, 0xc417, 0x2381, 0xc417, 0x21, 0 + .dw 0x2383, 0xc417, 0x238f, 0xc417, 0x21, 0 + .dw 0x2391, 0xc417, 0x2391, 0xc417, 0x21, 0 + .dw 0x2393, 0xc417, 0x23bf, 0xc417, 0x21, 0 + .dw 0x23c1, 0xc417, 0x23c1, 0xc417, 0x21, 0 + .dw 0x23c3, 0xc417, 0x23cf, 0xc417, 0x21, 0 + .dw 0x23d1, 0xc417, 0x23d1, 0xc417, 0x21, 0 + .dw 0x23d3, 0xc417, 0x23ff, 0xc417, 0x21, 0 + .dw 0x2401, 0xc417, 0x2401, 0xc417, 0x21, 0 + .dw 0x2403, 0xc417, 0x240f, 0xc417, 0x21, 0 + .dw 0x2411, 0xc417, 0x2411, 0xc417, 0x21, 0 + .dw 0x2413, 0xc417, 0x243f, 0xc417, 0x21, 0 + .dw 0x2441, 0xc417, 0x2441, 0xc417, 0x21, 0 + .dw 0x2443, 0xc417, 0x244f, 0xc417, 0x21, 0 + .dw 0x2451, 0xc417, 0x2451, 0xc417, 0x21, 0 + .dw 0x2453, 0xc417, 0x247f, 0xc417, 0x21, 0 + .dw 0x2481, 0xc417, 0x2481, 0xc417, 0x21, 0 + .dw 0x2483, 0xc417, 0x248f, 0xc417, 0x21, 0 + .dw 0x2491, 0xc417, 0x2491, 0xc417, 0x21, 0 + .dw 0x2493, 0xc417, 0x24bf, 0xc417, 0x21, 0 + .dw 0x24c1, 0xc417, 0x24c1, 0xc417, 0x21, 0 + .dw 0x24c3, 0xc417, 0x24cf, 0xc417, 0x21, 0 + .dw 0x24d1, 0xc417, 0x24d1, 0xc417, 0x21, 0 + .dw 0x24d3, 0xc417, 0x24ff, 0xc417, 0x21, 0 + .dw 0x2501, 0xc417, 0x2501, 0xc417, 0x21, 0 + .dw 0x2503, 0xc417, 0x250f, 0xc417, 0x21, 0 + .dw 0x2511, 0xc417, 0x2511, 0xc417, 0x21, 0 + .dw 0x2513, 0xc417, 0x253f, 0xc417, 0x21, 0 + .dw 0x2541, 0xc417, 0x2541, 0xc417, 0x21, 0 + .dw 0x2543, 0xc417, 0x254f, 0xc417, 0x21, 0 + .dw 0x2551, 0xc417, 0x2551, 0xc417, 0x21, 0 + .dw 0x2553, 0xc417, 0x257f, 0xc417, 0x21, 0 + .dw 0x2581, 0xc417, 0x2581, 0xc417, 0x21, 0 + .dw 0x2583, 0xc417, 0x258f, 0xc417, 0x21, 0 + .dw 0x2591, 0xc417, 0x2591, 0xc417, 0x21, 0 + .dw 0x2593, 0xc417, 0x25bf, 0xc417, 0x21, 0 + .dw 0x25c1, 0xc417, 0x25c1, 0xc417, 0x21, 0 + .dw 0x25c3, 0xc417, 0x25cf, 0xc417, 0x21, 0 + .dw 0x25d1, 0xc417, 0x25d1, 0xc417, 0x21, 0 + .dw 0x25d3, 0xc417, 0x25ff, 0xc417, 0x21, 0 + .dw 0x2601, 0xc417, 0x2601, 0xc417, 0x21, 0 + .dw 0x2603, 0xc417, 0x260f, 0xc417, 0x21, 0 + .dw 0x2611, 0xc417, 0x2611, 0xc417, 0x21, 0 + .dw 0x2613, 0xc417, 0x263f, 0xc417, 0x21, 0 + .dw 0x2641, 0xc417, 0x2641, 0xc417, 0x21, 0 + .dw 0x2643, 0xc417, 0x264f, 0xc417, 0x21, 0 + .dw 0x2651, 0xc417, 0x2651, 0xc417, 0x21, 0 + .dw 0x2653, 0xc417, 0x267f, 0xc417, 0x21, 0 + .dw 0x2681, 0xc417, 0x2681, 0xc417, 0x21, 0 + .dw 0x2683, 0xc417, 0x268f, 0xc417, 0x21, 0 + .dw 0x2691, 0xc417, 0x2691, 0xc417, 0x21, 0 + .dw 0x2693, 0xc417, 0x26bf, 0xc417, 0x21, 0 + .dw 0x26c1, 0xc417, 0x26c1, 0xc417, 0x21, 0 + .dw 0x26c3, 0xc417, 0x26cf, 0xc417, 0x21, 0 + .dw 0x26d1, 0xc417, 0x26d1, 0xc417, 0x21, 0 + .dw 0x26d3, 0xc417, 0x26ff, 0xc417, 0x21, 0 + .dw 0x2701, 0xc417, 0x2701, 0xc417, 0x21, 0 + .dw 0x2703, 0xc417, 0x270f, 0xc417, 0x21, 0 + .dw 0x2711, 0xc417, 0x2711, 0xc417, 0x21, 0 + .dw 0x2713, 0xc417, 0x273f, 0xc417, 0x21, 0 + .dw 0x2741, 0xc417, 0x2741, 0xc417, 0x21, 0 + .dw 0x2743, 0xc417, 0x274f, 0xc417, 0x21, 0 + .dw 0x2751, 0xc417, 0x2751, 0xc417, 0x21, 0 + .dw 0x2753, 0xc417, 0x277f, 0xc417, 0x21, 0 + .dw 0x2781, 0xc417, 0x2781, 0xc417, 0x21, 0 + .dw 0x2783, 0xc417, 0x278f, 0xc417, 0x21, 0 + .dw 0x2791, 0xc417, 0x2791, 0xc417, 0x21, 0 + .dw 0x2793, 0xc417, 0x27bf, 0xc417, 0x21, 0 + .dw 0x27c1, 0xc417, 0x27c1, 0xc417, 0x21, 0 + .dw 0x27c3, 0xc417, 0x27cf, 0xc417, 0x21, 0 + .dw 0x27d1, 0xc417, 0x27d1, 0xc417, 0x21, 0 + .dw 0x27d3, 0xc417, 0x27ff, 0xc417, 0x21, 0 + .dw 0x2801, 0xc417, 0x2801, 0xc417, 0x21, 0 + .dw 0x2803, 0xc417, 0x280f, 0xc417, 0x21, 0 + .dw 0x2811, 0xc417, 0x2811, 0xc417, 0x21, 0 + .dw 0x2813, 0xc417, 0x283f, 0xc417, 0x21, 0 + .dw 0x2841, 0xc417, 0x2841, 0xc417, 0x21, 0 + .dw 0x2843, 0xc417, 0x284f, 0xc417, 0x21, 0 + .dw 0x2851, 0xc417, 0x2851, 0xc417, 0x21, 0 + .dw 0x2853, 0xc417, 0x287f, 0xc417, 0x21, 0 + .dw 0x2881, 0xc417, 0x2881, 0xc417, 0x21, 0 + .dw 0x2883, 0xc417, 0x288f, 0xc417, 0x21, 0 + .dw 0x2891, 0xc417, 0x2891, 0xc417, 0x21, 0 + .dw 0x2893, 0xc417, 0x28bf, 0xc417, 0x21, 0 + .dw 0x28c1, 0xc417, 0x28c1, 0xc417, 0x21, 0 + .dw 0x28c3, 0xc417, 0x28cf, 0xc417, 0x21, 0 + .dw 0x28d1, 0xc417, 0x28d1, 0xc417, 0x21, 0 + .dw 0x28d3, 0xc417, 0x28ff, 0xc417, 0x21, 0 + .dw 0x2901, 0xc417, 0x2901, 0xc417, 0x21, 0 + .dw 0x2903, 0xc417, 0x290f, 0xc417, 0x21, 0 + .dw 0x2911, 0xc417, 0x2911, 0xc417, 0x21, 0 + .dw 0x2913, 0xc417, 0x293f, 0xc417, 0x21, 0 + .dw 0x2941, 0xc417, 0x2941, 0xc417, 0x21, 0 + .dw 0x2943, 0xc417, 0x294f, 0xc417, 0x21, 0 + .dw 0x2951, 0xc417, 0x2951, 0xc417, 0x21, 0 + .dw 0x2953, 0xc417, 0x297f, 0xc417, 0x21, 0 + .dw 0x2981, 0xc417, 0x2981, 0xc417, 0x21, 0 + .dw 0x2983, 0xc417, 0x298f, 0xc417, 0x21, 0 + .dw 0x2991, 0xc417, 0x2991, 0xc417, 0x21, 0 + .dw 0x2993, 0xc417, 0x29bf, 0xc417, 0x21, 0 + .dw 0x29c1, 0xc417, 0x29c1, 0xc417, 0x21, 0 + .dw 0x29c3, 0xc417, 0x29cf, 0xc417, 0x21, 0 + .dw 0x29d1, 0xc417, 0x29d1, 0xc417, 0x21, 0 + .dw 0x29d3, 0xc417, 0x29ff, 0xc417, 0x21, 0 + .dw 0x2a01, 0xc417, 0x2a01, 0xc417, 0x21, 0 + .dw 0x2a03, 0xc417, 0x2a0f, 0xc417, 0x21, 0 + .dw 0x2a11, 0xc417, 0x2a11, 0xc417, 0x21, 0 + .dw 0x2a13, 0xc417, 0x2a3f, 0xc417, 0x21, 0 + .dw 0x2a41, 0xc417, 0x2a41, 0xc417, 0x21, 0 + .dw 0x2a43, 0xc417, 0x2a4f, 0xc417, 0x21, 0 + .dw 0x2a51, 0xc417, 0x2a51, 0xc417, 0x21, 0 + .dw 0x2a53, 0xc417, 0x2a7f, 0xc417, 0x21, 0 + .dw 0x2a81, 0xc417, 0x2a81, 0xc417, 0x21, 0 + .dw 0x2a83, 0xc417, 0x2a8f, 0xc417, 0x21, 0 + .dw 0x2a91, 0xc417, 0x2a91, 0xc417, 0x21, 0 + .dw 0x2a93, 0xc417, 0x2abf, 0xc417, 0x21, 0 + .dw 0x2ac1, 0xc417, 0x2ac1, 0xc417, 0x21, 0 + .dw 0x2ac3, 0xc417, 0x2acf, 0xc417, 0x21, 0 + .dw 0x2ad1, 0xc417, 0x2ad1, 0xc417, 0x21, 0 + .dw 0x2ad3, 0xc417, 0x2aff, 0xc417, 0x21, 0 + .dw 0x2b01, 0xc417, 0x2b01, 0xc417, 0x21, 0 + .dw 0x2b03, 0xc417, 0x2b0f, 0xc417, 0x21, 0 + .dw 0x2b11, 0xc417, 0x2b11, 0xc417, 0x21, 0 + .dw 0x2b13, 0xc417, 0x2b3f, 0xc417, 0x21, 0 + .dw 0x2b41, 0xc417, 0x2b41, 0xc417, 0x21, 0 + .dw 0x2b43, 0xc417, 0x2b4f, 0xc417, 0x21, 0 + .dw 0x2b51, 0xc417, 0x2b51, 0xc417, 0x21, 0 + .dw 0x2b53, 0xc417, 0x2b7f, 0xc417, 0x21, 0 + .dw 0x2b81, 0xc417, 0x2b81, 0xc417, 0x21, 0 + .dw 0x2b83, 0xc417, 0x2b8f, 0xc417, 0x21, 0 + .dw 0x2b91, 0xc417, 0x2b91, 0xc417, 0x21, 0 + .dw 0x2b93, 0xc417, 0x2bbf, 0xc417, 0x21, 0 + .dw 0x2bc1, 0xc417, 0x2bc1, 0xc417, 0x21, 0 + .dw 0x2bc3, 0xc417, 0x2bcf, 0xc417, 0x21, 0 + .dw 0x2bd1, 0xc417, 0x2bd1, 0xc417, 0x21, 0 + .dw 0x2bd3, 0xc417, 0x2bff, 0xc417, 0x21, 0 + .dw 0x2c01, 0xc417, 0x2c01, 0xc417, 0x21, 0 + .dw 0x2c03, 0xc417, 0x2c0f, 0xc417, 0x21, 0 + .dw 0x2c11, 0xc417, 0x2c11, 0xc417, 0x21, 0 + .dw 0x2c13, 0xc417, 0x2c3f, 0xc417, 0x21, 0 + .dw 0x2c41, 0xc417, 0x2c41, 0xc417, 0x21, 0 + .dw 0x2c43, 0xc417, 0x2c4f, 0xc417, 0x21, 0 + .dw 0x2c51, 0xc417, 0x2c51, 0xc417, 0x21, 0 + .dw 0x2c53, 0xc417, 0x2c7f, 0xc417, 0x21, 0 + .dw 0x2c81, 0xc417, 0x2c81, 0xc417, 0x21, 0 + .dw 0x2c83, 0xc417, 0x2c8f, 0xc417, 0x21, 0 + .dw 0x2c91, 0xc417, 0x2c91, 0xc417, 0x21, 0 + .dw 0x2c93, 0xc417, 0x2cbf, 0xc417, 0x21, 0 + .dw 0x2cc1, 0xc417, 0x2cc1, 0xc417, 0x21, 0 + .dw 0x2cc3, 0xc417, 0x2ccf, 0xc417, 0x21, 0 + .dw 0x2cd1, 0xc417, 0x2cd1, 0xc417, 0x21, 0 + .dw 0x2cd3, 0xc417, 0x2cff, 0xc417, 0x21, 0 + .dw 0x2d01, 0xc417, 0x2d01, 0xc417, 0x21, 0 + .dw 0x2d03, 0xc417, 0x2d0f, 0xc417, 0x21, 0 + .dw 0x2d11, 0xc417, 0x2d11, 0xc417, 0x21, 0 + .dw 0x2d13, 0xc417, 0x2d3f, 0xc417, 0x21, 0 + .dw 0x2d41, 0xc417, 0x2d41, 0xc417, 0x21, 0 + .dw 0x2d43, 0xc417, 0x2d4f, 0xc417, 0x21, 0 + .dw 0x2d51, 0xc417, 0x2d51, 0xc417, 0x21, 0 + .dw 0x2d53, 0xc417, 0x2d7f, 0xc417, 0x21, 0 + .dw 0x2d81, 0xc417, 0x2d81, 0xc417, 0x21, 0 + .dw 0x2d83, 0xc417, 0x2d8f, 0xc417, 0x21, 0 + .dw 0x2d91, 0xc417, 0x2d91, 0xc417, 0x21, 0 + .dw 0x2d93, 0xc417, 0x2dbf, 0xc417, 0x21, 0 + .dw 0x2dc1, 0xc417, 0x2dc1, 0xc417, 0x21, 0 + .dw 0x2dc3, 0xc417, 0x2dcf, 0xc417, 0x21, 0 + .dw 0x2dd1, 0xc417, 0x2dd1, 0xc417, 0x21, 0 + .dw 0x2dd3, 0xc417, 0x2dff, 0xc417, 0x21, 0 + .dw 0x2e01, 0xc417, 0x2e01, 0xc417, 0x21, 0 + .dw 0x2e03, 0xc417, 0x2e0f, 0xc417, 0x21, 0 + .dw 0x2e11, 0xc417, 0x2e11, 0xc417, 0x21, 0 + .dw 0x2e13, 0xc417, 0x2e3f, 0xc417, 0x21, 0 + .dw 0x2e41, 0xc417, 0x2e41, 0xc417, 0x21, 0 + .dw 0x2e43, 0xc417, 0x2e4f, 0xc417, 0x21, 0 + .dw 0x2e51, 0xc417, 0x2e51, 0xc417, 0x21, 0 + .dw 0x2e53, 0xc417, 0x2e7f, 0xc417, 0x21, 0 + .dw 0x2e81, 0xc417, 0x2e81, 0xc417, 0x21, 0 + .dw 0x2e83, 0xc417, 0x2e8f, 0xc417, 0x21, 0 + .dw 0x2e91, 0xc417, 0x2e91, 0xc417, 0x21, 0 + .dw 0x2e93, 0xc417, 0x2ebf, 0xc417, 0x21, 0 + .dw 0x2ec1, 0xc417, 0x2ec1, 0xc417, 0x21, 0 + .dw 0x2ec3, 0xc417, 0x2ecf, 0xc417, 0x21, 0 + .dw 0x2ed1, 0xc417, 0x2ed1, 0xc417, 0x21, 0 + .dw 0x2ed3, 0xc417, 0x2eff, 0xc417, 0x21, 0 + .dw 0x2f01, 0xc417, 0x2f01, 0xc417, 0x21, 0 + .dw 0x2f03, 0xc417, 0x2f0f, 0xc417, 0x21, 0 + .dw 0x2f11, 0xc417, 0x2f11, 0xc417, 0x21, 0 + .dw 0x2f13, 0xc417, 0x2f3f, 0xc417, 0x21, 0 + .dw 0x2f41, 0xc417, 0x2f41, 0xc417, 0x21, 0 + .dw 0x2f43, 0xc417, 0x2f4f, 0xc417, 0x21, 0 + .dw 0x2f51, 0xc417, 0x2f51, 0xc417, 0x21, 0 + .dw 0x2f53, 0xc417, 0x2f7f, 0xc417, 0x21, 0 + .dw 0x2f81, 0xc417, 0x2f81, 0xc417, 0x21, 0 + .dw 0x2f83, 0xc417, 0x2f8f, 0xc417, 0x21, 0 + .dw 0x2f91, 0xc417, 0x2f91, 0xc417, 0x21, 0 + .dw 0x2f93, 0xc417, 0x2fbf, 0xc417, 0x21, 0 + .dw 0x2fc1, 0xc417, 0x2fc1, 0xc417, 0x21, 0 + .dw 0x2fc3, 0xc417, 0x2fcf, 0xc417, 0x21, 0 + .dw 0x2fd1, 0xc417, 0x2fd1, 0xc417, 0x21, 0 + .dw 0x2fd3, 0xc417, 0xffff, 0xc417, 0x21, 0 + .dw 0x1000, 0xc418, 0x3fff, 0xc418, 0x21, 0 + .dw 0x4000, 0xc418, 0x4000, 0xc418, 0x22, 0 + .dw 0x4001, 0xc418, 0x4001, 0xc418, 0x21, 0 + .dw 0x4002, 0xc418, 0x4002, 0xc418, 0x22, 0 + .dw 0x4003, 0xc418, 0x400f, 0xc418, 0x21, 0 + .dw 0x4010, 0xc418, 0x4010, 0xc418, 0x22, 0 + .dw 0x4011, 0xc418, 0x4011, 0xc418, 0x21, 0 + .dw 0x4012, 0xc418, 0x4012, 0xc418, 0x22, 0 + .dw 0x4013, 0xc418, 0x403f, 0xc418, 0x21, 0 + .dw 0x4041, 0xc418, 0x4041, 0xc418, 0x21, 0 + .dw 0x4043, 0xc418, 0x404f, 0xc418, 0x21, 0 + .dw 0x4051, 0xc418, 0x4051, 0xc418, 0x21, 0 + .dw 0x4053, 0xc418, 0x407f, 0xc418, 0x21, 0 + .dw 0x4081, 0xc418, 0x4081, 0xc418, 0x21, 0 + .dw 0x4083, 0xc418, 0x408f, 0xc418, 0x21, 0 + .dw 0x4091, 0xc418, 0x4091, 0xc418, 0x21, 0 + .dw 0x4093, 0xc418, 0x40bf, 0xc418, 0x21, 0 + .dw 0x40c1, 0xc418, 0x40c1, 0xc418, 0x21, 0 + .dw 0x40c3, 0xc418, 0x40cf, 0xc418, 0x21, 0 + .dw 0x40d1, 0xc418, 0x40d1, 0xc418, 0x21, 0 + .dw 0x40d3, 0xc418, 0x40ff, 0xc418, 0x21, 0 + .dw 0x4101, 0xc418, 0x4101, 0xc418, 0x21, 0 + .dw 0x4103, 0xc418, 0x410f, 0xc418, 0x21, 0 + .dw 0x4111, 0xc418, 0x4111, 0xc418, 0x21, 0 + .dw 0x4113, 0xc418, 0x413f, 0xc418, 0x21, 0 + .dw 0x4141, 0xc418, 0x4141, 0xc418, 0x21, 0 + .dw 0x4143, 0xc418, 0x414f, 0xc418, 0x21, 0 + .dw 0x4151, 0xc418, 0x4151, 0xc418, 0x21, 0 + .dw 0x4153, 0xc418, 0x417f, 0xc418, 0x21, 0 + .dw 0x4181, 0xc418, 0x4181, 0xc418, 0x21, 0 + .dw 0x4183, 0xc418, 0x418f, 0xc418, 0x21, 0 + .dw 0x4191, 0xc418, 0x4191, 0xc418, 0x21, 0 + .dw 0x4193, 0xc418, 0x41bf, 0xc418, 0x21, 0 + .dw 0x41c1, 0xc418, 0x41c1, 0xc418, 0x21, 0 + .dw 0x41c3, 0xc418, 0x41cf, 0xc418, 0x21, 0 + .dw 0x41d1, 0xc418, 0x41d1, 0xc418, 0x21, 0 + .dw 0x41d3, 0xc418, 0x41ff, 0xc418, 0x21, 0 + .dw 0x4201, 0xc418, 0x4201, 0xc418, 0x21, 0 + .dw 0x4203, 0xc418, 0x420f, 0xc418, 0x21, 0 + .dw 0x4211, 0xc418, 0x4211, 0xc418, 0x21, 0 + .dw 0x4213, 0xc418, 0x423f, 0xc418, 0x21, 0 + .dw 0x4240, 0xc418, 0x4240, 0xc418, 0x22, 0 + .dw 0x4241, 0xc418, 0x4241, 0xc418, 0x21, 0 + .dw 0x4242, 0xc418, 0x4242, 0xc418, 0x22, 0 + .dw 0x4243, 0xc418, 0x424f, 0xc418, 0x21, 0 + .dw 0x4250, 0xc418, 0x4250, 0xc418, 0x22, 0 + .dw 0x4251, 0xc418, 0x4251, 0xc418, 0x21, 0 + .dw 0x4252, 0xc418, 0x4252, 0xc418, 0x22, 0 + .dw 0x4253, 0xc418, 0x427f, 0xc418, 0x21, 0 + .dw 0x4281, 0xc418, 0x4281, 0xc418, 0x21, 0 + .dw 0x4283, 0xc418, 0x428f, 0xc418, 0x21, 0 + .dw 0x4291, 0xc418, 0x4291, 0xc418, 0x21, 0 + .dw 0x4293, 0xc418, 0x42bf, 0xc418, 0x21, 0 + .dw 0x42c1, 0xc418, 0x42c1, 0xc418, 0x21, 0 + .dw 0x42c3, 0xc418, 0x42cf, 0xc418, 0x21, 0 + .dw 0x42d1, 0xc418, 0x42d1, 0xc418, 0x21, 0 + .dw 0x42d3, 0xc418, 0x42ff, 0xc418, 0x21, 0 + .dw 0x4301, 0xc418, 0x4301, 0xc418, 0x21, 0 + .dw 0x4303, 0xc418, 0x430f, 0xc418, 0x21, 0 + .dw 0x4311, 0xc418, 0x4311, 0xc418, 0x21, 0 + .dw 0x4313, 0xc418, 0x433f, 0xc418, 0x21, 0 + .dw 0x4341, 0xc418, 0x4341, 0xc418, 0x21, 0 + .dw 0x4343, 0xc418, 0x434f, 0xc418, 0x21, 0 + .dw 0x4351, 0xc418, 0x4351, 0xc418, 0x21, 0 + .dw 0x4353, 0xc418, 0x437f, 0xc418, 0x21, 0 + .dw 0x4381, 0xc418, 0x4381, 0xc418, 0x21, 0 + .dw 0x4383, 0xc418, 0x438f, 0xc418, 0x21, 0 + .dw 0x4391, 0xc418, 0x4391, 0xc418, 0x21, 0 + .dw 0x4393, 0xc418, 0x43bf, 0xc418, 0x21, 0 + .dw 0x43c1, 0xc418, 0x43c1, 0xc418, 0x21, 0 + .dw 0x43c3, 0xc418, 0x43cf, 0xc418, 0x21, 0 + .dw 0x43d1, 0xc418, 0x43d1, 0xc418, 0x21, 0 + .dw 0x43d3, 0xc418, 0x43ff, 0xc418, 0x21, 0 + .dw 0x4401, 0xc418, 0x4401, 0xc418, 0x21, 0 + .dw 0x4403, 0xc418, 0x440f, 0xc418, 0x21, 0 + .dw 0x4411, 0xc418, 0x4411, 0xc418, 0x21, 0 + .dw 0x4413, 0xc418, 0x443f, 0xc418, 0x21, 0 + .dw 0x4441, 0xc418, 0x4441, 0xc418, 0x21, 0 + .dw 0x4443, 0xc418, 0x444f, 0xc418, 0x21, 0 + .dw 0x4451, 0xc418, 0x4451, 0xc418, 0x21, 0 + .dw 0x4453, 0xc418, 0x447f, 0xc418, 0x21, 0 + .dw 0x4480, 0xc418, 0x4480, 0xc418, 0x22, 0 + .dw 0x4481, 0xc418, 0x4481, 0xc418, 0x21, 0 + .dw 0x4482, 0xc418, 0x4482, 0xc418, 0x22, 0 + .dw 0x4483, 0xc418, 0x448f, 0xc418, 0x21, 0 + .dw 0x4490, 0xc418, 0x4490, 0xc418, 0x22, 0 + .dw 0x4491, 0xc418, 0x4491, 0xc418, 0x21, 0 + .dw 0x4492, 0xc418, 0x4492, 0xc418, 0x22, 0 + .dw 0x4493, 0xc418, 0x44bf, 0xc418, 0x21, 0 + .dw 0x44c1, 0xc418, 0x44c1, 0xc418, 0x21, 0 + .dw 0x44c3, 0xc418, 0x44cf, 0xc418, 0x21, 0 + .dw 0x44d1, 0xc418, 0x44d1, 0xc418, 0x21, 0 + .dw 0x44d3, 0xc418, 0x44ff, 0xc418, 0x21, 0 + .dw 0x4501, 0xc418, 0x4501, 0xc418, 0x21, 0 + .dw 0x4503, 0xc418, 0x450f, 0xc418, 0x21, 0 + .dw 0x4511, 0xc418, 0x4511, 0xc418, 0x21, 0 + .dw 0x4513, 0xc418, 0x453f, 0xc418, 0x21, 0 + .dw 0x4541, 0xc418, 0x4541, 0xc418, 0x21, 0 + .dw 0x4543, 0xc418, 0x454f, 0xc418, 0x21, 0 + .dw 0x4551, 0xc418, 0x4551, 0xc418, 0x21, 0 + .dw 0x4553, 0xc418, 0x457f, 0xc418, 0x21, 0 + .dw 0x4581, 0xc418, 0x4581, 0xc418, 0x21, 0 + .dw 0x4583, 0xc418, 0x458f, 0xc418, 0x21, 0 + .dw 0x4591, 0xc418, 0x4591, 0xc418, 0x21, 0 + .dw 0x4593, 0xc418, 0x45bf, 0xc418, 0x21, 0 + .dw 0x45c1, 0xc418, 0x45c1, 0xc418, 0x21, 0 + .dw 0x45c3, 0xc418, 0x45cf, 0xc418, 0x21, 0 + .dw 0x45d1, 0xc418, 0x45d1, 0xc418, 0x21, 0 + .dw 0x45d3, 0xc418, 0x45ff, 0xc418, 0x21, 0 + .dw 0x4601, 0xc418, 0x4601, 0xc418, 0x21, 0 + .dw 0x4603, 0xc418, 0x460f, 0xc418, 0x21, 0 + .dw 0x4611, 0xc418, 0x4611, 0xc418, 0x21, 0 + .dw 0x4613, 0xc418, 0x463f, 0xc418, 0x21, 0 + .dw 0x4641, 0xc418, 0x4641, 0xc418, 0x21, 0 + .dw 0x4643, 0xc418, 0x464f, 0xc418, 0x21, 0 + .dw 0x4651, 0xc418, 0x4651, 0xc418, 0x21, 0 + .dw 0x4653, 0xc418, 0x467f, 0xc418, 0x21, 0 + .dw 0x4681, 0xc418, 0x4681, 0xc418, 0x21, 0 + .dw 0x4683, 0xc418, 0x468f, 0xc418, 0x21, 0 + .dw 0x4691, 0xc418, 0x4691, 0xc418, 0x21, 0 + .dw 0x4693, 0xc418, 0x46bf, 0xc418, 0x21, 0 + .dw 0x46c0, 0xc418, 0x46c0, 0xc418, 0x22, 0 + .dw 0x46c1, 0xc418, 0x46c1, 0xc418, 0x21, 0 + .dw 0x46c2, 0xc418, 0x46c2, 0xc418, 0x22, 0 + .dw 0x46c3, 0xc418, 0x46cf, 0xc418, 0x21, 0 + .dw 0x46d0, 0xc418, 0x46d0, 0xc418, 0x22, 0 + .dw 0x46d1, 0xc418, 0x46d1, 0xc418, 0x21, 0 + .dw 0x46d2, 0xc418, 0x46d2, 0xc418, 0x22, 0 + .dw 0x46d3, 0xc418, 0x46ff, 0xc418, 0x21, 0 + .dw 0x4701, 0xc418, 0x4701, 0xc418, 0x21, 0 + .dw 0x4703, 0xc418, 0x470f, 0xc418, 0x21, 0 + .dw 0x4711, 0xc418, 0x4711, 0xc418, 0x21, 0 + .dw 0x4713, 0xc418, 0x473f, 0xc418, 0x21, 0 + .dw 0x4741, 0xc418, 0x4741, 0xc418, 0x21, 0 + .dw 0x4743, 0xc418, 0x474f, 0xc418, 0x21, 0 + .dw 0x4751, 0xc418, 0x4751, 0xc418, 0x21, 0 + .dw 0x4753, 0xc418, 0x477f, 0xc418, 0x21, 0 + .dw 0x4781, 0xc418, 0x4781, 0xc418, 0x21, 0 + .dw 0x4783, 0xc418, 0x478f, 0xc418, 0x21, 0 + .dw 0x4791, 0xc418, 0x4791, 0xc418, 0x21, 0 + .dw 0x4793, 0xc418, 0x47bf, 0xc418, 0x21, 0 + .dw 0x47c1, 0xc418, 0x47c1, 0xc418, 0x21, 0 + .dw 0x47c3, 0xc418, 0x47cf, 0xc418, 0x21, 0 + .dw 0x47d1, 0xc418, 0x47d1, 0xc418, 0x21, 0 + .dw 0x47d3, 0xc418, 0x47ff, 0xc418, 0x21, 0 + .dw 0x4801, 0xc418, 0x4801, 0xc418, 0x21, 0 + .dw 0x4803, 0xc418, 0x480f, 0xc418, 0x21, 0 + .dw 0x4811, 0xc418, 0x4811, 0xc418, 0x21, 0 + .dw 0x4813, 0xc418, 0x483f, 0xc418, 0x21, 0 + .dw 0x4841, 0xc418, 0x4841, 0xc418, 0x21, 0 + .dw 0x4843, 0xc418, 0x484f, 0xc418, 0x21, 0 + .dw 0x4851, 0xc418, 0x4851, 0xc418, 0x21, 0 + .dw 0x4853, 0xc418, 0x487f, 0xc418, 0x21, 0 + .dw 0x4881, 0xc418, 0x4881, 0xc418, 0x21, 0 + .dw 0x4883, 0xc418, 0x488f, 0xc418, 0x21, 0 + .dw 0x4891, 0xc418, 0x4891, 0xc418, 0x21, 0 + .dw 0x4893, 0xc418, 0x48bf, 0xc418, 0x21, 0 + .dw 0x48c1, 0xc418, 0x48c1, 0xc418, 0x21, 0 + .dw 0x48c3, 0xc418, 0x48cf, 0xc418, 0x21, 0 + .dw 0x48d1, 0xc418, 0x48d1, 0xc418, 0x21, 0 + .dw 0x48d3, 0xc418, 0x48ff, 0xc418, 0x21, 0 + .dw 0x4900, 0xc418, 0x4900, 0xc418, 0x22, 0 + .dw 0x4901, 0xc418, 0x4901, 0xc418, 0x21, 0 + .dw 0x4902, 0xc418, 0x4902, 0xc418, 0x22, 0 + .dw 0x4903, 0xc418, 0x490f, 0xc418, 0x21, 0 + .dw 0x4910, 0xc418, 0x4910, 0xc418, 0x22, 0 + .dw 0x4911, 0xc418, 0x4911, 0xc418, 0x21, 0 + .dw 0x4912, 0xc418, 0x4912, 0xc418, 0x22, 0 + .dw 0x4913, 0xc418, 0x493f, 0xc418, 0x21, 0 + .dw 0x4941, 0xc418, 0x4941, 0xc418, 0x21, 0 + .dw 0x4943, 0xc418, 0x494f, 0xc418, 0x21, 0 + .dw 0x4951, 0xc418, 0x4951, 0xc418, 0x21, 0 + .dw 0x4953, 0xc418, 0x497f, 0xc418, 0x21, 0 + .dw 0x4981, 0xc418, 0x4981, 0xc418, 0x21, 0 + .dw 0x4983, 0xc418, 0x498f, 0xc418, 0x21, 0 + .dw 0x4991, 0xc418, 0x4991, 0xc418, 0x21, 0 + .dw 0x4993, 0xc418, 0x49bf, 0xc418, 0x21, 0 + .dw 0x49c1, 0xc418, 0x49c1, 0xc418, 0x21, 0 + .dw 0x49c3, 0xc418, 0x49cf, 0xc418, 0x21, 0 + .dw 0x49d1, 0xc418, 0x49d1, 0xc418, 0x21, 0 + .dw 0x49d3, 0xc418, 0x49ff, 0xc418, 0x21, 0 + .dw 0x4a01, 0xc418, 0x4a01, 0xc418, 0x21, 0 + .dw 0x4a03, 0xc418, 0x4a0f, 0xc418, 0x21, 0 + .dw 0x4a11, 0xc418, 0x4a11, 0xc418, 0x21, 0 + .dw 0x4a13, 0xc418, 0x4a3f, 0xc418, 0x21, 0 + .dw 0x4a41, 0xc418, 0x4a41, 0xc418, 0x21, 0 + .dw 0x4a43, 0xc418, 0x4a4f, 0xc418, 0x21, 0 + .dw 0x4a51, 0xc418, 0x4a51, 0xc418, 0x21, 0 + .dw 0x4a53, 0xc418, 0x4a7f, 0xc418, 0x21, 0 + .dw 0x4a81, 0xc418, 0x4a81, 0xc418, 0x21, 0 + .dw 0x4a83, 0xc418, 0x4a8f, 0xc418, 0x21, 0 + .dw 0x4a91, 0xc418, 0x4a91, 0xc418, 0x21, 0 + .dw 0x4a93, 0xc418, 0x4abf, 0xc418, 0x21, 0 + .dw 0x4ac1, 0xc418, 0x4ac1, 0xc418, 0x21, 0 + .dw 0x4ac3, 0xc418, 0x4acf, 0xc418, 0x21, 0 + .dw 0x4ad1, 0xc418, 0x4ad1, 0xc418, 0x21, 0 + .dw 0x4ad3, 0xc418, 0x4aff, 0xc418, 0x21, 0 + .dw 0x4b01, 0xc418, 0x4b01, 0xc418, 0x21, 0 + .dw 0x4b03, 0xc418, 0x4b0f, 0xc418, 0x21, 0 + .dw 0x4b11, 0xc418, 0x4b11, 0xc418, 0x21, 0 + .dw 0x4b13, 0xc418, 0x4b3f, 0xc418, 0x21, 0 + .dw 0x4b40, 0xc418, 0x4b40, 0xc418, 0x22, 0 + .dw 0x4b41, 0xc418, 0x4b41, 0xc418, 0x21, 0 + .dw 0x4b42, 0xc418, 0x4b42, 0xc418, 0x22, 0 + .dw 0x4b43, 0xc418, 0x4b4f, 0xc418, 0x21, 0 + .dw 0x4b50, 0xc418, 0x4b50, 0xc418, 0x22, 0 + .dw 0x4b51, 0xc418, 0x4b51, 0xc418, 0x21, 0 + .dw 0x4b52, 0xc418, 0x4b52, 0xc418, 0x22, 0 + .dw 0x4b53, 0xc418, 0x4b7f, 0xc418, 0x21, 0 + .dw 0x4b81, 0xc418, 0x4b81, 0xc418, 0x21, 0 + .dw 0x4b83, 0xc418, 0x4b8f, 0xc418, 0x21, 0 + .dw 0x4b91, 0xc418, 0x4b91, 0xc418, 0x21, 0 + .dw 0x4b93, 0xc418, 0x4bbf, 0xc418, 0x21, 0 + .dw 0x4bc1, 0xc418, 0x4bc1, 0xc418, 0x21, 0 + .dw 0x4bc3, 0xc418, 0x4bcf, 0xc418, 0x21, 0 + .dw 0x4bd1, 0xc418, 0x4bd1, 0xc418, 0x21, 0 + .dw 0x4bd3, 0xc418, 0x4bff, 0xc418, 0x21, 0 + .dw 0x4c01, 0xc418, 0x4c01, 0xc418, 0x21, 0 + .dw 0x4c03, 0xc418, 0x4c0f, 0xc418, 0x21, 0 + .dw 0x4c11, 0xc418, 0x4c11, 0xc418, 0x21, 0 + .dw 0x4c13, 0xc418, 0x4c3f, 0xc418, 0x21, 0 + .dw 0x4c41, 0xc418, 0x4c41, 0xc418, 0x21, 0 + .dw 0x4c43, 0xc418, 0x4c4f, 0xc418, 0x21, 0 + .dw 0x4c51, 0xc418, 0x4c51, 0xc418, 0x21, 0 + .dw 0x4c53, 0xc418, 0x4c7f, 0xc418, 0x21, 0 + .dw 0x4c81, 0xc418, 0x4c81, 0xc418, 0x21, 0 + .dw 0x4c83, 0xc418, 0x4c8f, 0xc418, 0x21, 0 + .dw 0x4c91, 0xc418, 0x4c91, 0xc418, 0x21, 0 + .dw 0x4c93, 0xc418, 0x4cbf, 0xc418, 0x21, 0 + .dw 0x4cc1, 0xc418, 0x4cc1, 0xc418, 0x21, 0 + .dw 0x4cc3, 0xc418, 0x4ccf, 0xc418, 0x21, 0 + .dw 0x4cd1, 0xc418, 0x4cd1, 0xc418, 0x21, 0 + .dw 0x4cd3, 0xc418, 0x4cff, 0xc418, 0x21, 0 + .dw 0x4d01, 0xc418, 0x4d01, 0xc418, 0x21, 0 + .dw 0x4d03, 0xc418, 0x4d0f, 0xc418, 0x21, 0 + .dw 0x4d11, 0xc418, 0x4d11, 0xc418, 0x21, 0 + .dw 0x4d13, 0xc418, 0x4d3f, 0xc418, 0x21, 0 + .dw 0x4d41, 0xc418, 0x4d41, 0xc418, 0x21, 0 + .dw 0x4d43, 0xc418, 0x4d4f, 0xc418, 0x21, 0 + .dw 0x4d51, 0xc418, 0x4d51, 0xc418, 0x21, 0 + .dw 0x4d53, 0xc418, 0x4d7f, 0xc418, 0x21, 0 + .dw 0x4d80, 0xc418, 0x4d80, 0xc418, 0x22, 0 + .dw 0x4d81, 0xc418, 0x4d81, 0xc418, 0x21, 0 + .dw 0x4d82, 0xc418, 0x4d82, 0xc418, 0x22, 0 + .dw 0x4d83, 0xc418, 0x4d8f, 0xc418, 0x21, 0 + .dw 0x4d90, 0xc418, 0x4d90, 0xc418, 0x22, 0 + .dw 0x4d91, 0xc418, 0x4d91, 0xc418, 0x21, 0 + .dw 0x4d92, 0xc418, 0x4d92, 0xc418, 0x22, 0 + .dw 0x4d93, 0xc418, 0x4dbf, 0xc418, 0x21, 0 + .dw 0x4dc1, 0xc418, 0x4dc1, 0xc418, 0x21, 0 + .dw 0x4dc3, 0xc418, 0x4dcf, 0xc418, 0x21, 0 + .dw 0x4dd1, 0xc418, 0x4dd1, 0xc418, 0x21, 0 + .dw 0x4dd3, 0xc418, 0x4dff, 0xc418, 0x21, 0 + .dw 0x4e01, 0xc418, 0x4e01, 0xc418, 0x21, 0 + .dw 0x4e03, 0xc418, 0x4e0f, 0xc418, 0x21, 0 + .dw 0x4e11, 0xc418, 0x4e11, 0xc418, 0x21, 0 + .dw 0x4e13, 0xc418, 0x4e3f, 0xc418, 0x21, 0 + .dw 0x4e41, 0xc418, 0x4e41, 0xc418, 0x21, 0 + .dw 0x4e43, 0xc418, 0x4e4f, 0xc418, 0x21, 0 + .dw 0x4e51, 0xc418, 0x4e51, 0xc418, 0x21, 0 + .dw 0x4e53, 0xc418, 0x4e7f, 0xc418, 0x21, 0 + .dw 0x4e81, 0xc418, 0x4e81, 0xc418, 0x21, 0 + .dw 0x4e83, 0xc418, 0x4e8f, 0xc418, 0x21, 0 + .dw 0x4e91, 0xc418, 0x4e91, 0xc418, 0x21, 0 + .dw 0x4e93, 0xc418, 0x4ebf, 0xc418, 0x21, 0 + .dw 0x4ec1, 0xc418, 0x4ec1, 0xc418, 0x21, 0 + .dw 0x4ec3, 0xc418, 0x4ecf, 0xc418, 0x21, 0 + .dw 0x4ed1, 0xc418, 0x4ed1, 0xc418, 0x21, 0 + .dw 0x4ed3, 0xc418, 0x4eff, 0xc418, 0x21, 0 + .dw 0x4f01, 0xc418, 0x4f01, 0xc418, 0x21, 0 + .dw 0x4f03, 0xc418, 0x4f0f, 0xc418, 0x21, 0 + .dw 0x4f11, 0xc418, 0x4f11, 0xc418, 0x21, 0 + .dw 0x4f13, 0xc418, 0x4f3f, 0xc418, 0x21, 0 + .dw 0x4f41, 0xc418, 0x4f41, 0xc418, 0x21, 0 + .dw 0x4f43, 0xc418, 0x4f4f, 0xc418, 0x21, 0 + .dw 0x4f51, 0xc418, 0x4f51, 0xc418, 0x21, 0 + .dw 0x4f53, 0xc418, 0x4f7f, 0xc418, 0x21, 0 + .dw 0x4f81, 0xc418, 0x4f81, 0xc418, 0x21, 0 + .dw 0x4f83, 0xc418, 0x4f8f, 0xc418, 0x21, 0 + .dw 0x4f91, 0xc418, 0x4f91, 0xc418, 0x21, 0 + .dw 0x4f93, 0xc418, 0x4fbf, 0xc418, 0x21, 0 + .dw 0x4fc0, 0xc418, 0x4fc0, 0xc418, 0x22, 0 + .dw 0x4fc1, 0xc418, 0x4fc1, 0xc418, 0x21, 0 + .dw 0x4fc2, 0xc418, 0x4fc2, 0xc418, 0x22, 0 + .dw 0x4fc3, 0xc418, 0x4fcf, 0xc418, 0x21, 0 + .dw 0x4fd0, 0xc418, 0x4fd0, 0xc418, 0x22, 0 + .dw 0x4fd1, 0xc418, 0x4fd1, 0xc418, 0x21, 0 + .dw 0x4fd2, 0xc418, 0x4fd2, 0xc418, 0x22, 0 + .dw 0x4fd3, 0xc418, 0x5fff, 0xc418, 0x21, 0 + .dw 0x6000, 0xc418, 0x6000, 0xc418, 0x22, 0 + .dw 0x6001, 0xc418, 0x6001, 0xc418, 0x21, 0 + .dw 0x6002, 0xc418, 0x6002, 0xc418, 0x22, 0 + .dw 0x6003, 0xc418, 0x600f, 0xc418, 0x21, 0 + .dw 0x6010, 0xc418, 0x6010, 0xc418, 0x22, 0 + .dw 0x6011, 0xc418, 0x6011, 0xc418, 0x21, 0 + .dw 0x6012, 0xc418, 0x6012, 0xc418, 0x22, 0 + .dw 0x6013, 0xc418, 0x603f, 0xc418, 0x21, 0 + .dw 0x6041, 0xc418, 0x6041, 0xc418, 0x21, 0 + .dw 0x6043, 0xc418, 0x604f, 0xc418, 0x21, 0 + .dw 0x6051, 0xc418, 0x6051, 0xc418, 0x21, 0 + .dw 0x6053, 0xc418, 0x607f, 0xc418, 0x21, 0 + .dw 0x6081, 0xc418, 0x6081, 0xc418, 0x21, 0 + .dw 0x6083, 0xc418, 0x608f, 0xc418, 0x21, 0 + .dw 0x6091, 0xc418, 0x6091, 0xc418, 0x21, 0 + .dw 0x6093, 0xc418, 0x60bf, 0xc418, 0x21, 0 + .dw 0x60c1, 0xc418, 0x60c1, 0xc418, 0x21, 0 + .dw 0x60c3, 0xc418, 0x60cf, 0xc418, 0x21, 0 + .dw 0x60d1, 0xc418, 0x60d1, 0xc418, 0x21, 0 + .dw 0x60d3, 0xc418, 0x60ff, 0xc418, 0x21, 0 + .dw 0x6101, 0xc418, 0x6101, 0xc418, 0x21, 0 + .dw 0x6103, 0xc418, 0x610f, 0xc418, 0x21, 0 + .dw 0x6111, 0xc418, 0x6111, 0xc418, 0x21, 0 + .dw 0x6113, 0xc418, 0x613f, 0xc418, 0x21, 0 + .dw 0x6141, 0xc418, 0x6141, 0xc418, 0x21, 0 + .dw 0x6143, 0xc418, 0x614f, 0xc418, 0x21, 0 + .dw 0x6151, 0xc418, 0x6151, 0xc418, 0x21, 0 + .dw 0x6153, 0xc418, 0x617f, 0xc418, 0x21, 0 + .dw 0x6181, 0xc418, 0x6181, 0xc418, 0x21, 0 + .dw 0x6183, 0xc418, 0x618f, 0xc418, 0x21, 0 + .dw 0x6191, 0xc418, 0x6191, 0xc418, 0x21, 0 + .dw 0x6193, 0xc418, 0x61bf, 0xc418, 0x21, 0 + .dw 0x61c1, 0xc418, 0x61c1, 0xc418, 0x21, 0 + .dw 0x61c3, 0xc418, 0x61cf, 0xc418, 0x21, 0 + .dw 0x61d1, 0xc418, 0x61d1, 0xc418, 0x21, 0 + .dw 0x61d3, 0xc418, 0x61ff, 0xc418, 0x21, 0 + .dw 0x6201, 0xc418, 0x6201, 0xc418, 0x21, 0 + .dw 0x6203, 0xc418, 0x620f, 0xc418, 0x21, 0 + .dw 0x6211, 0xc418, 0x6211, 0xc418, 0x21, 0 + .dw 0x6213, 0xc418, 0x623f, 0xc418, 0x21, 0 + .dw 0x6240, 0xc418, 0x6240, 0xc418, 0x22, 0 + .dw 0x6241, 0xc418, 0x6241, 0xc418, 0x21, 0 + .dw 0x6242, 0xc418, 0x6242, 0xc418, 0x22, 0 + .dw 0x6243, 0xc418, 0x624f, 0xc418, 0x21, 0 + .dw 0x6250, 0xc418, 0x6250, 0xc418, 0x22, 0 + .dw 0x6251, 0xc418, 0x6251, 0xc418, 0x21, 0 + .dw 0x6252, 0xc418, 0x6252, 0xc418, 0x22, 0 + .dw 0x6253, 0xc418, 0x627f, 0xc418, 0x21, 0 + .dw 0x6281, 0xc418, 0x6281, 0xc418, 0x21, 0 + .dw 0x6283, 0xc418, 0x628f, 0xc418, 0x21, 0 + .dw 0x6291, 0xc418, 0x6291, 0xc418, 0x21, 0 + .dw 0x6293, 0xc418, 0x62bf, 0xc418, 0x21, 0 + .dw 0x62c1, 0xc418, 0x62c1, 0xc418, 0x21, 0 + .dw 0x62c3, 0xc418, 0x62cf, 0xc418, 0x21, 0 + .dw 0x62d1, 0xc418, 0x62d1, 0xc418, 0x21, 0 + .dw 0x62d3, 0xc418, 0x62ff, 0xc418, 0x21, 0 + .dw 0x6301, 0xc418, 0x6301, 0xc418, 0x21, 0 + .dw 0x6303, 0xc418, 0x630f, 0xc418, 0x21, 0 + .dw 0x6311, 0xc418, 0x6311, 0xc418, 0x21, 0 + .dw 0x6313, 0xc418, 0x633f, 0xc418, 0x21, 0 + .dw 0x6341, 0xc418, 0x6341, 0xc418, 0x21, 0 + .dw 0x6343, 0xc418, 0x634f, 0xc418, 0x21, 0 + .dw 0x6351, 0xc418, 0x6351, 0xc418, 0x21, 0 + .dw 0x6353, 0xc418, 0x637f, 0xc418, 0x21, 0 + .dw 0x6381, 0xc418, 0x6381, 0xc418, 0x21, 0 + .dw 0x6383, 0xc418, 0x638f, 0xc418, 0x21, 0 + .dw 0x6391, 0xc418, 0x6391, 0xc418, 0x21, 0 + .dw 0x6393, 0xc418, 0x63bf, 0xc418, 0x21, 0 + .dw 0x63c1, 0xc418, 0x63c1, 0xc418, 0x21, 0 + .dw 0x63c3, 0xc418, 0x63cf, 0xc418, 0x21, 0 + .dw 0x63d1, 0xc418, 0x63d1, 0xc418, 0x21, 0 + .dw 0x63d3, 0xc418, 0x63ff, 0xc418, 0x21, 0 + .dw 0x6401, 0xc418, 0x6401, 0xc418, 0x21, 0 + .dw 0x6403, 0xc418, 0x640f, 0xc418, 0x21, 0 + .dw 0x6411, 0xc418, 0x6411, 0xc418, 0x21, 0 + .dw 0x6413, 0xc418, 0x643f, 0xc418, 0x21, 0 + .dw 0x6441, 0xc418, 0x6441, 0xc418, 0x21, 0 + .dw 0x6443, 0xc418, 0x644f, 0xc418, 0x21, 0 + .dw 0x6451, 0xc418, 0x6451, 0xc418, 0x21, 0 + .dw 0x6453, 0xc418, 0x647f, 0xc418, 0x21, 0 + .dw 0x6480, 0xc418, 0x6480, 0xc418, 0x22, 0 + .dw 0x6481, 0xc418, 0x6481, 0xc418, 0x21, 0 + .dw 0x6482, 0xc418, 0x6482, 0xc418, 0x22, 0 + .dw 0x6483, 0xc418, 0x648f, 0xc418, 0x21, 0 + .dw 0x6490, 0xc418, 0x6490, 0xc418, 0x22, 0 + .dw 0x6491, 0xc418, 0x6491, 0xc418, 0x21, 0 + .dw 0x6492, 0xc418, 0x6492, 0xc418, 0x22, 0 + .dw 0x6493, 0xc418, 0x64bf, 0xc418, 0x21, 0 + .dw 0x64c1, 0xc418, 0x64c1, 0xc418, 0x21, 0 + .dw 0x64c3, 0xc418, 0x64cf, 0xc418, 0x21, 0 + .dw 0x64d1, 0xc418, 0x64d1, 0xc418, 0x21, 0 + .dw 0x64d3, 0xc418, 0x64ff, 0xc418, 0x21, 0 + .dw 0x6501, 0xc418, 0x6501, 0xc418, 0x21, 0 + .dw 0x6503, 0xc418, 0x650f, 0xc418, 0x21, 0 + .dw 0x6511, 0xc418, 0x6511, 0xc418, 0x21, 0 + .dw 0x6513, 0xc418, 0x653f, 0xc418, 0x21, 0 + .dw 0x6541, 0xc418, 0x6541, 0xc418, 0x21, 0 + .dw 0x6543, 0xc418, 0x654f, 0xc418, 0x21, 0 + .dw 0x6551, 0xc418, 0x6551, 0xc418, 0x21, 0 + .dw 0x6553, 0xc418, 0x657f, 0xc418, 0x21, 0 + .dw 0x6581, 0xc418, 0x6581, 0xc418, 0x21, 0 + .dw 0x6583, 0xc418, 0x658f, 0xc418, 0x21, 0 + .dw 0x6591, 0xc418, 0x6591, 0xc418, 0x21, 0 + .dw 0x6593, 0xc418, 0x65bf, 0xc418, 0x21, 0 + .dw 0x65c1, 0xc418, 0x65c1, 0xc418, 0x21, 0 + .dw 0x65c3, 0xc418, 0x65cf, 0xc418, 0x21, 0 + .dw 0x65d1, 0xc418, 0x65d1, 0xc418, 0x21, 0 + .dw 0x65d3, 0xc418, 0x65ff, 0xc418, 0x21, 0 + .dw 0x6601, 0xc418, 0x6601, 0xc418, 0x21, 0 + .dw 0x6603, 0xc418, 0x660f, 0xc418, 0x21, 0 + .dw 0x6611, 0xc418, 0x6611, 0xc418, 0x21, 0 + .dw 0x6613, 0xc418, 0x663f, 0xc418, 0x21, 0 + .dw 0x6641, 0xc418, 0x6641, 0xc418, 0x21, 0 + .dw 0x6643, 0xc418, 0x664f, 0xc418, 0x21, 0 + .dw 0x6651, 0xc418, 0x6651, 0xc418, 0x21, 0 + .dw 0x6653, 0xc418, 0x667f, 0xc418, 0x21, 0 + .dw 0x6681, 0xc418, 0x6681, 0xc418, 0x21, 0 + .dw 0x6683, 0xc418, 0x668f, 0xc418, 0x21, 0 + .dw 0x6691, 0xc418, 0x6691, 0xc418, 0x21, 0 + .dw 0x6693, 0xc418, 0x66bf, 0xc418, 0x21, 0 + .dw 0x66c0, 0xc418, 0x66c0, 0xc418, 0x22, 0 + .dw 0x66c1, 0xc418, 0x66c1, 0xc418, 0x21, 0 + .dw 0x66c2, 0xc418, 0x66c2, 0xc418, 0x22, 0 + .dw 0x66c3, 0xc418, 0x66cf, 0xc418, 0x21, 0 + .dw 0x66d0, 0xc418, 0x66d0, 0xc418, 0x22, 0 + .dw 0x66d1, 0xc418, 0x66d1, 0xc418, 0x21, 0 + .dw 0x66d2, 0xc418, 0x66d2, 0xc418, 0x22, 0 + .dw 0x66d3, 0xc418, 0x66ff, 0xc418, 0x21, 0 + .dw 0x6701, 0xc418, 0x6701, 0xc418, 0x21, 0 + .dw 0x6703, 0xc418, 0x670f, 0xc418, 0x21, 0 + .dw 0x6711, 0xc418, 0x6711, 0xc418, 0x21, 0 + .dw 0x6713, 0xc418, 0x673f, 0xc418, 0x21, 0 + .dw 0x6741, 0xc418, 0x6741, 0xc418, 0x21, 0 + .dw 0x6743, 0xc418, 0x674f, 0xc418, 0x21, 0 + .dw 0x6751, 0xc418, 0x6751, 0xc418, 0x21, 0 + .dw 0x6753, 0xc418, 0x677f, 0xc418, 0x21, 0 + .dw 0x6781, 0xc418, 0x6781, 0xc418, 0x21, 0 + .dw 0x6783, 0xc418, 0x678f, 0xc418, 0x21, 0 + .dw 0x6791, 0xc418, 0x6791, 0xc418, 0x21, 0 + .dw 0x6793, 0xc418, 0x67bf, 0xc418, 0x21, 0 + .dw 0x67c1, 0xc418, 0x67c1, 0xc418, 0x21, 0 + .dw 0x67c3, 0xc418, 0x67cf, 0xc418, 0x21, 0 + .dw 0x67d1, 0xc418, 0x67d1, 0xc418, 0x21, 0 + .dw 0x67d3, 0xc418, 0x67ff, 0xc418, 0x21, 0 + .dw 0x6801, 0xc418, 0x6801, 0xc418, 0x21, 0 + .dw 0x6803, 0xc418, 0x680f, 0xc418, 0x21, 0 + .dw 0x6811, 0xc418, 0x6811, 0xc418, 0x21, 0 + .dw 0x6813, 0xc418, 0x683f, 0xc418, 0x21, 0 + .dw 0x6841, 0xc418, 0x6841, 0xc418, 0x21, 0 + .dw 0x6843, 0xc418, 0x684f, 0xc418, 0x21, 0 + .dw 0x6851, 0xc418, 0x6851, 0xc418, 0x21, 0 + .dw 0x6853, 0xc418, 0x687f, 0xc418, 0x21, 0 + .dw 0x6881, 0xc418, 0x6881, 0xc418, 0x21, 0 + .dw 0x6883, 0xc418, 0x688f, 0xc418, 0x21, 0 + .dw 0x6891, 0xc418, 0x6891, 0xc418, 0x21, 0 + .dw 0x6893, 0xc418, 0x68bf, 0xc418, 0x21, 0 + .dw 0x68c1, 0xc418, 0x68c1, 0xc418, 0x21, 0 + .dw 0x68c3, 0xc418, 0x68cf, 0xc418, 0x21, 0 + .dw 0x68d1, 0xc418, 0x68d1, 0xc418, 0x21, 0 + .dw 0x68d3, 0xc418, 0x68ff, 0xc418, 0x21, 0 + .dw 0x6900, 0xc418, 0x6900, 0xc418, 0x22, 0 + .dw 0x6901, 0xc418, 0x6901, 0xc418, 0x21, 0 + .dw 0x6902, 0xc418, 0x6902, 0xc418, 0x22, 0 + .dw 0x6903, 0xc418, 0x690f, 0xc418, 0x21, 0 + .dw 0x6910, 0xc418, 0x6910, 0xc418, 0x22, 0 + .dw 0x6911, 0xc418, 0x6911, 0xc418, 0x21, 0 + .dw 0x6912, 0xc418, 0x6912, 0xc418, 0x22, 0 + .dw 0x6913, 0xc418, 0x693f, 0xc418, 0x21, 0 + .dw 0x6941, 0xc418, 0x6941, 0xc418, 0x21, 0 + .dw 0x6943, 0xc418, 0x694f, 0xc418, 0x21, 0 + .dw 0x6951, 0xc418, 0x6951, 0xc418, 0x21, 0 + .dw 0x6953, 0xc418, 0x697f, 0xc418, 0x21, 0 + .dw 0x6981, 0xc418, 0x6981, 0xc418, 0x21, 0 + .dw 0x6983, 0xc418, 0x698f, 0xc418, 0x21, 0 + .dw 0x6991, 0xc418, 0x6991, 0xc418, 0x21, 0 + .dw 0x6993, 0xc418, 0x69bf, 0xc418, 0x21, 0 + .dw 0x69c1, 0xc418, 0x69c1, 0xc418, 0x21, 0 + .dw 0x69c3, 0xc418, 0x69cf, 0xc418, 0x21, 0 + .dw 0x69d1, 0xc418, 0x69d1, 0xc418, 0x21, 0 + .dw 0x69d3, 0xc418, 0x69ff, 0xc418, 0x21, 0 + .dw 0x6a01, 0xc418, 0x6a01, 0xc418, 0x21, 0 + .dw 0x6a03, 0xc418, 0x6a0f, 0xc418, 0x21, 0 + .dw 0x6a11, 0xc418, 0x6a11, 0xc418, 0x21, 0 + .dw 0x6a13, 0xc418, 0x6a3f, 0xc418, 0x21, 0 + .dw 0x6a41, 0xc418, 0x6a41, 0xc418, 0x21, 0 + .dw 0x6a43, 0xc418, 0x6a4f, 0xc418, 0x21, 0 + .dw 0x6a51, 0xc418, 0x6a51, 0xc418, 0x21, 0 + .dw 0x6a53, 0xc418, 0x6a7f, 0xc418, 0x21, 0 + .dw 0x6a81, 0xc418, 0x6a81, 0xc418, 0x21, 0 + .dw 0x6a83, 0xc418, 0x6a8f, 0xc418, 0x21, 0 + .dw 0x6a91, 0xc418, 0x6a91, 0xc418, 0x21, 0 + .dw 0x6a93, 0xc418, 0x6abf, 0xc418, 0x21, 0 + .dw 0x6ac1, 0xc418, 0x6ac1, 0xc418, 0x21, 0 + .dw 0x6ac3, 0xc418, 0x6acf, 0xc418, 0x21, 0 + .dw 0x6ad1, 0xc418, 0x6ad1, 0xc418, 0x21, 0 + .dw 0x6ad3, 0xc418, 0x6aff, 0xc418, 0x21, 0 + .dw 0x6b01, 0xc418, 0x6b01, 0xc418, 0x21, 0 + .dw 0x6b03, 0xc418, 0x6b0f, 0xc418, 0x21, 0 + .dw 0x6b11, 0xc418, 0x6b11, 0xc418, 0x21, 0 + .dw 0x6b13, 0xc418, 0x6b3f, 0xc418, 0x21, 0 + .dw 0x6b40, 0xc418, 0x6b40, 0xc418, 0x22, 0 + .dw 0x6b41, 0xc418, 0x6b41, 0xc418, 0x21, 0 + .dw 0x6b42, 0xc418, 0x6b42, 0xc418, 0x22, 0 + .dw 0x6b43, 0xc418, 0x6b4f, 0xc418, 0x21, 0 + .dw 0x6b50, 0xc418, 0x6b50, 0xc418, 0x22, 0 + .dw 0x6b51, 0xc418, 0x6b51, 0xc418, 0x21, 0 + .dw 0x6b52, 0xc418, 0x6b52, 0xc418, 0x22, 0 + .dw 0x6b53, 0xc418, 0x6b7f, 0xc418, 0x21, 0 + .dw 0x6b81, 0xc418, 0x6b81, 0xc418, 0x21, 0 + .dw 0x6b83, 0xc418, 0x6b8f, 0xc418, 0x21, 0 + .dw 0x6b91, 0xc418, 0x6b91, 0xc418, 0x21, 0 + .dw 0x6b93, 0xc418, 0x6bbf, 0xc418, 0x21, 0 + .dw 0x6bc1, 0xc418, 0x6bc1, 0xc418, 0x21, 0 + .dw 0x6bc3, 0xc418, 0x6bcf, 0xc418, 0x21, 0 + .dw 0x6bd1, 0xc418, 0x6bd1, 0xc418, 0x21, 0 + .dw 0x6bd3, 0xc418, 0x6bff, 0xc418, 0x21, 0 + .dw 0x6c01, 0xc418, 0x6c01, 0xc418, 0x21, 0 + .dw 0x6c03, 0xc418, 0x6c0f, 0xc418, 0x21, 0 + .dw 0x6c11, 0xc418, 0x6c11, 0xc418, 0x21, 0 + .dw 0x6c13, 0xc418, 0x6c3f, 0xc418, 0x21, 0 + .dw 0x6c41, 0xc418, 0x6c41, 0xc418, 0x21, 0 + .dw 0x6c43, 0xc418, 0x6c4f, 0xc418, 0x21, 0 + .dw 0x6c51, 0xc418, 0x6c51, 0xc418, 0x21, 0 + .dw 0x6c53, 0xc418, 0x6c7f, 0xc418, 0x21, 0 + .dw 0x6c81, 0xc418, 0x6c81, 0xc418, 0x21, 0 + .dw 0x6c83, 0xc418, 0x6c8f, 0xc418, 0x21, 0 + .dw 0x6c91, 0xc418, 0x6c91, 0xc418, 0x21, 0 + .dw 0x6c93, 0xc418, 0x6cbf, 0xc418, 0x21, 0 + .dw 0x6cc1, 0xc418, 0x6cc1, 0xc418, 0x21, 0 + .dw 0x6cc3, 0xc418, 0x6ccf, 0xc418, 0x21, 0 + .dw 0x6cd1, 0xc418, 0x6cd1, 0xc418, 0x21, 0 + .dw 0x6cd3, 0xc418, 0x6cff, 0xc418, 0x21, 0 + .dw 0x6d01, 0xc418, 0x6d01, 0xc418, 0x21, 0 + .dw 0x6d03, 0xc418, 0x6d0f, 0xc418, 0x21, 0 + .dw 0x6d11, 0xc418, 0x6d11, 0xc418, 0x21, 0 + .dw 0x6d13, 0xc418, 0x6d3f, 0xc418, 0x21, 0 + .dw 0x6d41, 0xc418, 0x6d41, 0xc418, 0x21, 0 + .dw 0x6d43, 0xc418, 0x6d4f, 0xc418, 0x21, 0 + .dw 0x6d51, 0xc418, 0x6d51, 0xc418, 0x21, 0 + .dw 0x6d53, 0xc418, 0x6d7f, 0xc418, 0x21, 0 + .dw 0x6d80, 0xc418, 0x6d80, 0xc418, 0x22, 0 + .dw 0x6d81, 0xc418, 0x6d81, 0xc418, 0x21, 0 + .dw 0x6d82, 0xc418, 0x6d82, 0xc418, 0x22, 0 + .dw 0x6d83, 0xc418, 0x6d8f, 0xc418, 0x21, 0 + .dw 0x6d90, 0xc418, 0x6d90, 0xc418, 0x22, 0 + .dw 0x6d91, 0xc418, 0x6d91, 0xc418, 0x21, 0 + .dw 0x6d92, 0xc418, 0x6d92, 0xc418, 0x22, 0 + .dw 0x6d93, 0xc418, 0x6dbf, 0xc418, 0x21, 0 + .dw 0x6dc1, 0xc418, 0x6dc1, 0xc418, 0x21, 0 + .dw 0x6dc3, 0xc418, 0x6dcf, 0xc418, 0x21, 0 + .dw 0x6dd1, 0xc418, 0x6dd1, 0xc418, 0x21, 0 + .dw 0x6dd3, 0xc418, 0x6dff, 0xc418, 0x21, 0 + .dw 0x6e01, 0xc418, 0x6e01, 0xc418, 0x21, 0 + .dw 0x6e03, 0xc418, 0x6e0f, 0xc418, 0x21, 0 + .dw 0x6e11, 0xc418, 0x6e11, 0xc418, 0x21, 0 + .dw 0x6e13, 0xc418, 0x6e3f, 0xc418, 0x21, 0 + .dw 0x6e41, 0xc418, 0x6e41, 0xc418, 0x21, 0 + .dw 0x6e43, 0xc418, 0x6e4f, 0xc418, 0x21, 0 + .dw 0x6e51, 0xc418, 0x6e51, 0xc418, 0x21, 0 + .dw 0x6e53, 0xc418, 0x6e7f, 0xc418, 0x21, 0 + .dw 0x6e81, 0xc418, 0x6e81, 0xc418, 0x21, 0 + .dw 0x6e83, 0xc418, 0x6e8f, 0xc418, 0x21, 0 + .dw 0x6e91, 0xc418, 0x6e91, 0xc418, 0x21, 0 + .dw 0x6e93, 0xc418, 0x6ebf, 0xc418, 0x21, 0 + .dw 0x6ec1, 0xc418, 0x6ec1, 0xc418, 0x21, 0 + .dw 0x6ec3, 0xc418, 0x6ecf, 0xc418, 0x21, 0 + .dw 0x6ed1, 0xc418, 0x6ed1, 0xc418, 0x21, 0 + .dw 0x6ed3, 0xc418, 0x6eff, 0xc418, 0x21, 0 + .dw 0x6f01, 0xc418, 0x6f01, 0xc418, 0x21, 0 + .dw 0x6f03, 0xc418, 0x6f0f, 0xc418, 0x21, 0 + .dw 0x6f11, 0xc418, 0x6f11, 0xc418, 0x21, 0 + .dw 0x6f13, 0xc418, 0x6f3f, 0xc418, 0x21, 0 + .dw 0x6f41, 0xc418, 0x6f41, 0xc418, 0x21, 0 + .dw 0x6f43, 0xc418, 0x6f4f, 0xc418, 0x21, 0 + .dw 0x6f51, 0xc418, 0x6f51, 0xc418, 0x21, 0 + .dw 0x6f53, 0xc418, 0x6f7f, 0xc418, 0x21, 0 + .dw 0x6f81, 0xc418, 0x6f81, 0xc418, 0x21, 0 + .dw 0x6f83, 0xc418, 0x6f8f, 0xc418, 0x21, 0 + .dw 0x6f91, 0xc418, 0x6f91, 0xc418, 0x21, 0 + .dw 0x6f93, 0xc418, 0x6fbf, 0xc418, 0x21, 0 + .dw 0x6fc0, 0xc418, 0x6fc0, 0xc418, 0x22, 0 + .dw 0x6fc1, 0xc418, 0x6fc1, 0xc418, 0x21, 0 + .dw 0x6fc2, 0xc418, 0x6fc2, 0xc418, 0x22, 0 + .dw 0x6fc3, 0xc418, 0x6fcf, 0xc418, 0x21, 0 + .dw 0x6fd0, 0xc418, 0x6fd0, 0xc418, 0x22, 0 + .dw 0x6fd1, 0xc418, 0x6fd1, 0xc418, 0x21, 0 + .dw 0x6fd2, 0xc418, 0x6fd2, 0xc418, 0x22, 0 + .dw 0x6fd3, 0xc418, 0xffff, 0xc420, 0x21, 0 + .dw 0x0000, 0xc421, 0x003f, 0xc421, 0x22, 0 + .dw 0x0240, 0xc421, 0x027f, 0xc421, 0x22, 0 + .dw 0x0480, 0xc421, 0x04bf, 0xc421, 0x22, 0 + .dw 0x06c0, 0xc421, 0x06ff, 0xc421, 0x22, 0 + .dw 0x0900, 0xc421, 0x093f, 0xc421, 0x22, 0 + .dw 0x0b40, 0xc421, 0x0b7f, 0xc421, 0x22, 0 + .dw 0x0d80, 0xc421, 0x0dbf, 0xc421, 0x22, 0 + .dw 0x0fc0, 0xc421, 0x103f, 0xc421, 0x22, 0 + .dw 0x1240, 0xc421, 0x127f, 0xc421, 0x22, 0 + .dw 0x1480, 0xc421, 0x14bf, 0xc421, 0x22, 0 + .dw 0x16c0, 0xc421, 0x16ff, 0xc421, 0x22, 0 + .dw 0x1900, 0xc421, 0x193f, 0xc421, 0x22, 0 + .dw 0x1b40, 0xc421, 0x1b7f, 0xc421, 0x22, 0 + .dw 0x1d80, 0xc421, 0x1dbf, 0xc421, 0x22, 0 + .dw 0x1fc0, 0xc421, 0x203f, 0xc421, 0x22, 0 + .dw 0x2240, 0xc421, 0x227f, 0xc421, 0x22, 0 + .dw 0x2480, 0xc421, 0x24bf, 0xc421, 0x22, 0 + .dw 0x26c0, 0xc421, 0x26ff, 0xc421, 0x22, 0 + .dw 0x2900, 0xc421, 0x293f, 0xc421, 0x22, 0 + .dw 0x2b40, 0xc421, 0x2b7f, 0xc421, 0x22, 0 + .dw 0x2d80, 0xc421, 0x2dbf, 0xc421, 0x22, 0 + .dw 0x2fc0, 0xc421, 0x303f, 0xc421, 0x22, 0 + .dw 0x3240, 0xc421, 0x327f, 0xc421, 0x22, 0 + .dw 0x3480, 0xc421, 0x34bf, 0xc421, 0x22, 0 + .dw 0x36c0, 0xc421, 0x36ff, 0xc421, 0x22, 0 + .dw 0x3900, 0xc421, 0x393f, 0xc421, 0x22, 0 + .dw 0x3b40, 0xc421, 0x3b7f, 0xc421, 0x22, 0 + .dw 0x3d80, 0xc421, 0x3dbf, 0xc421, 0x22, 0 + .dw 0x3fc0, 0xc421, 0x3fff, 0xc421, 0x22, 0 + .dw 0x4000, 0xc421, 0x7fff, 0xc421, 0x21, 0 + .dw 0x8000, 0xc421, 0x803f, 0xc421, 0x22, 0 + .dw 0x8240, 0xc421, 0x827f, 0xc421, 0x22, 0 + .dw 0x8480, 0xc421, 0x84bf, 0xc421, 0x22, 0 + .dw 0x86c0, 0xc421, 0x86ff, 0xc421, 0x22, 0 + .dw 0x8900, 0xc421, 0x893f, 0xc421, 0x22, 0 + .dw 0x8b40, 0xc421, 0x8b7f, 0xc421, 0x22, 0 + .dw 0x8d80, 0xc421, 0x8dbf, 0xc421, 0x22, 0 + .dw 0x8fc0, 0xc421, 0x903f, 0xc421, 0x22, 0 + .dw 0x9240, 0xc421, 0x927f, 0xc421, 0x22, 0 + .dw 0x9480, 0xc421, 0x94bf, 0xc421, 0x22, 0 + .dw 0x96c0, 0xc421, 0x96ff, 0xc421, 0x22, 0 + .dw 0x9900, 0xc421, 0x993f, 0xc421, 0x22, 0 + .dw 0x9b40, 0xc421, 0x9b7f, 0xc421, 0x22, 0 + .dw 0x9d80, 0xc421, 0x9dbf, 0xc421, 0x22, 0 + .dw 0x9fc0, 0xc421, 0xa03f, 0xc421, 0x22, 0 + .dw 0xa240, 0xc421, 0xa27f, 0xc421, 0x22, 0 + .dw 0xa480, 0xc421, 0xa4bf, 0xc421, 0x22, 0 + .dw 0xa6c0, 0xc421, 0xa6ff, 0xc421, 0x22, 0 + .dw 0xa900, 0xc421, 0xa93f, 0xc421, 0x22, 0 + .dw 0xab40, 0xc421, 0xab7f, 0xc421, 0x22, 0 + .dw 0xad80, 0xc421, 0xadbf, 0xc421, 0x22, 0 + .dw 0xafc0, 0xc421, 0xb03f, 0xc421, 0x22, 0 + .dw 0xb240, 0xc421, 0xb27f, 0xc421, 0x22, 0 + .dw 0xb480, 0xc421, 0xb4bf, 0xc421, 0x22, 0 + .dw 0xb6c0, 0xc421, 0xb6ff, 0xc421, 0x22, 0 + .dw 0xb900, 0xc421, 0xb93f, 0xc421, 0x22, 0 + .dw 0xbb40, 0xc421, 0xbb7f, 0xc421, 0x22, 0 + .dw 0xbd80, 0xc421, 0xbdbf, 0xc421, 0x22, 0 + .dw 0xbfc0, 0xc421, 0xc03f, 0xc421, 0x22, 0 + .dw 0xc240, 0xc421, 0xc27f, 0xc421, 0x22, 0 + .dw 0xc480, 0xc421, 0xc4bf, 0xc421, 0x22, 0 + .dw 0xc6c0, 0xc421, 0xc6ff, 0xc421, 0x22, 0 + .dw 0xc900, 0xc421, 0xc93f, 0xc421, 0x22, 0 + .dw 0xcb40, 0xc421, 0xcb7f, 0xc421, 0x22, 0 + .dw 0xcd80, 0xc421, 0xcdbf, 0xc421, 0x22, 0 + .dw 0xcfc0, 0xc421, 0xd03f, 0xc421, 0x22, 0 + .dw 0xd240, 0xc421, 0xd27f, 0xc421, 0x22, 0 + .dw 0xd480, 0xc421, 0xd4bf, 0xc421, 0x22, 0 + .dw 0xd6c0, 0xc421, 0xd6ff, 0xc421, 0x22, 0 + .dw 0xd900, 0xc421, 0xd93f, 0xc421, 0x22, 0 + .dw 0xdb40, 0xc421, 0xdb7f, 0xc421, 0x22, 0 + .dw 0xdd80, 0xc421, 0xddbf, 0xc421, 0x22, 0 + .dw 0xdfc0, 0xc421, 0xe03f, 0xc421, 0x22, 0 + .dw 0xe240, 0xc421, 0xe27f, 0xc421, 0x22, 0 + .dw 0xe480, 0xc421, 0xe4bf, 0xc421, 0x22, 0 + .dw 0xe6c0, 0xc421, 0xe6ff, 0xc421, 0x22, 0 + .dw 0xe900, 0xc421, 0xe93f, 0xc421, 0x22, 0 + .dw 0xeb40, 0xc421, 0xeb7f, 0xc421, 0x22, 0 + .dw 0xed80, 0xc421, 0xedbf, 0xc421, 0x22, 0 + .dw 0xefc0, 0xc421, 0xf03f, 0xc421, 0x22, 0 + .dw 0xf240, 0xc421, 0xf27f, 0xc421, 0x22, 0 + .dw 0xf480, 0xc421, 0xf4bf, 0xc421, 0x22, 0 + .dw 0xf6c0, 0xc421, 0xf6ff, 0xc421, 0x22, 0 + .dw 0xf900, 0xc421, 0xf93f, 0xc421, 0x22, 0 + .dw 0xfb40, 0xc421, 0xfb7f, 0xc421, 0x22, 0 + .dw 0xfd80, 0xc421, 0xfdbf, 0xc421, 0x22, 0 + .dw 0xffc0, 0xc421, 0xffff, 0xc421, 0x22, 0 + .dw 0x1000, 0xc422, 0x1fff, 0xc422, 0x21, 0 + .dw 0x3000, 0xc422, 0x3fff, 0xc422, 0x21, 0 + .dw 0x5000, 0xc422, 0x5fff, 0xc422, 0x21, 0 + .dw 0x7000, 0xc422, 0x7fff, 0xc422, 0x21, 0 + .dw 0x9000, 0xc422, 0x9fff, 0xc422, 0x21, 0 + .dw 0xb000, 0xc422, 0xbfff, 0xc422, 0x21, 0 + .dw 0xd000, 0xc422, 0xdfff, 0xc422, 0x21, 0 + .dw 0xf000, 0xc422, 0xffff, 0xc422, 0x21, 0 + .dw 0x1000, 0xc423, 0x1fff, 0xc423, 0x21, 0 + .dw 0x3000, 0xc423, 0x3fff, 0xc423, 0x21, 0 + .dw 0x5000, 0xc423, 0x5fff, 0xc423, 0x21, 0 + .dw 0x7000, 0xc423, 0x7fff, 0xc423, 0x21, 0 + .dw 0x9000, 0xc423, 0x9fff, 0xc423, 0x21, 0 + .dw 0xb000, 0xc423, 0xbfff, 0xc423, 0x21, 0 + .dw 0xd000, 0xc423, 0xdfff, 0xc423, 0x21, 0 + .dw 0xf000, 0xc423, 0xffff, 0xc424, 0x21, 0 + .dw 0x1000, 0xc425, 0x3fff, 0xc425, 0x21, 0 + .dw 0x5000, 0xc425, 0x8fff, 0xc425, 0x21, 0 + .dw 0xa000, 0xc425, 0xcfff, 0xc425, 0x21, 0 + .dw 0xe000, 0xc425, 0xffff, 0xc428, 0x21, 0 + .dw 0x1000, 0xc429, 0x7fff, 0xc429, 0x21, 0 + .dw 0x9000, 0xc429, 0xffff, 0xc42a, 0x21, 0 + .dw 0x1000, 0xc42b, 0x3fff, 0xc42b, 0x21, 0 + .dw 0x5000, 0xc42b, 0xbfff, 0xc42c, 0x21, 0 + .dw 0xd000, 0xc42c, 0xffff, 0xc42d, 0x21, 0 + .dw 0x1000, 0xc42e, 0x3fff, 0xc42e, 0x21, 0 + .dw 0x5000, 0xc42e, 0xffff, 0xc42f, 0x21, 0 + .dw 0x1000, 0xc430, 0x3fff, 0xc430, 0x21, 0 + .dw 0x5000, 0xc430, 0xffff, 0xc435, 0x21, 0 + .dw 0x0001, 0xc436, 0x0001, 0xc436, 0x21, 0 + .dw 0x0003, 0xc436, 0x000f, 0xc436, 0x21, 0 + .dw 0x0011, 0xc436, 0x0011, 0xc436, 0x21, 0 + .dw 0x0013, 0xc436, 0x003f, 0xc436, 0x21, 0 + .dw 0x0041, 0xc436, 0x0041, 0xc436, 0x21, 0 + .dw 0x0043, 0xc436, 0x004f, 0xc436, 0x21, 0 + .dw 0x0051, 0xc436, 0x0051, 0xc436, 0x21, 0 + .dw 0x0053, 0xc436, 0x007f, 0xc436, 0x21, 0 + .dw 0x0081, 0xc436, 0x0081, 0xc436, 0x21, 0 + .dw 0x0083, 0xc436, 0x008f, 0xc436, 0x21, 0 + .dw 0x0091, 0xc436, 0x0091, 0xc436, 0x21, 0 + .dw 0x0093, 0xc436, 0x00bf, 0xc436, 0x21, 0 + .dw 0x00c1, 0xc436, 0x00c1, 0xc436, 0x21, 0 + .dw 0x00c3, 0xc436, 0x00cf, 0xc436, 0x21, 0 + .dw 0x00d1, 0xc436, 0x00d1, 0xc436, 0x21, 0 + .dw 0x00d3, 0xc436, 0x00ff, 0xc436, 0x21, 0 + .dw 0x0101, 0xc436, 0x0101, 0xc436, 0x21, 0 + .dw 0x0103, 0xc436, 0x010f, 0xc436, 0x21, 0 + .dw 0x0111, 0xc436, 0x0111, 0xc436, 0x21, 0 + .dw 0x0113, 0xc436, 0x013f, 0xc436, 0x21, 0 + .dw 0x0141, 0xc436, 0x0141, 0xc436, 0x21, 0 + .dw 0x0143, 0xc436, 0x014f, 0xc436, 0x21, 0 + .dw 0x0151, 0xc436, 0x0151, 0xc436, 0x21, 0 + .dw 0x0153, 0xc436, 0x017f, 0xc436, 0x21, 0 + .dw 0x0181, 0xc436, 0x0181, 0xc436, 0x21, 0 + .dw 0x0183, 0xc436, 0x018f, 0xc436, 0x21, 0 + .dw 0x0191, 0xc436, 0x0191, 0xc436, 0x21, 0 + .dw 0x0193, 0xc436, 0x01bf, 0xc436, 0x21, 0 + .dw 0x01c1, 0xc436, 0x01c1, 0xc436, 0x21, 0 + .dw 0x01c3, 0xc436, 0x01cf, 0xc436, 0x21, 0 + .dw 0x01d1, 0xc436, 0x01d1, 0xc436, 0x21, 0 + .dw 0x01d3, 0xc436, 0x01ff, 0xc436, 0x21, 0 + .dw 0x0201, 0xc436, 0x0201, 0xc436, 0x21, 0 + .dw 0x0203, 0xc436, 0x020f, 0xc436, 0x21, 0 + .dw 0x0211, 0xc436, 0x0211, 0xc436, 0x21, 0 + .dw 0x0213, 0xc436, 0x023f, 0xc436, 0x21, 0 + .dw 0x0241, 0xc436, 0x0241, 0xc436, 0x21, 0 + .dw 0x0243, 0xc436, 0x024f, 0xc436, 0x21, 0 + .dw 0x0251, 0xc436, 0x0251, 0xc436, 0x21, 0 + .dw 0x0253, 0xc436, 0x027f, 0xc436, 0x21, 0 + .dw 0x0281, 0xc436, 0x0281, 0xc436, 0x21, 0 + .dw 0x0283, 0xc436, 0x028f, 0xc436, 0x21, 0 + .dw 0x0291, 0xc436, 0x0291, 0xc436, 0x21, 0 + .dw 0x0293, 0xc436, 0x02bf, 0xc436, 0x21, 0 + .dw 0x02c1, 0xc436, 0x02c1, 0xc436, 0x21, 0 + .dw 0x02c3, 0xc436, 0x02cf, 0xc436, 0x21, 0 + .dw 0x02d1, 0xc436, 0x02d1, 0xc436, 0x21, 0 + .dw 0x02d3, 0xc436, 0x02ff, 0xc436, 0x21, 0 + .dw 0x0301, 0xc436, 0x0301, 0xc436, 0x21, 0 + .dw 0x0303, 0xc436, 0x030f, 0xc436, 0x21, 0 + .dw 0x0311, 0xc436, 0x0311, 0xc436, 0x21, 0 + .dw 0x0313, 0xc436, 0x033f, 0xc436, 0x21, 0 + .dw 0x0341, 0xc436, 0x0341, 0xc436, 0x21, 0 + .dw 0x0343, 0xc436, 0x034f, 0xc436, 0x21, 0 + .dw 0x0351, 0xc436, 0x0351, 0xc436, 0x21, 0 + .dw 0x0353, 0xc436, 0x037f, 0xc436, 0x21, 0 + .dw 0x0381, 0xc436, 0x0381, 0xc436, 0x21, 0 + .dw 0x0383, 0xc436, 0x038f, 0xc436, 0x21, 0 + .dw 0x0391, 0xc436, 0x0391, 0xc436, 0x21, 0 + .dw 0x0393, 0xc436, 0x03bf, 0xc436, 0x21, 0 + .dw 0x03c1, 0xc436, 0x03c1, 0xc436, 0x21, 0 + .dw 0x03c3, 0xc436, 0x03cf, 0xc436, 0x21, 0 + .dw 0x03d1, 0xc436, 0x03d1, 0xc436, 0x21, 0 + .dw 0x03d3, 0xc436, 0x03ff, 0xc436, 0x21, 0 + .dw 0x0401, 0xc436, 0x0401, 0xc436, 0x21, 0 + .dw 0x0403, 0xc436, 0x040f, 0xc436, 0x21, 0 + .dw 0x0411, 0xc436, 0x0411, 0xc436, 0x21, 0 + .dw 0x0413, 0xc436, 0x043f, 0xc436, 0x21, 0 + .dw 0x0441, 0xc436, 0x0441, 0xc436, 0x21, 0 + .dw 0x0443, 0xc436, 0x044f, 0xc436, 0x21, 0 + .dw 0x0451, 0xc436, 0x0451, 0xc436, 0x21, 0 + .dw 0x0453, 0xc436, 0x047f, 0xc436, 0x21, 0 + .dw 0x0481, 0xc436, 0x0481, 0xc436, 0x21, 0 + .dw 0x0483, 0xc436, 0x048f, 0xc436, 0x21, 0 + .dw 0x0491, 0xc436, 0x0491, 0xc436, 0x21, 0 + .dw 0x0493, 0xc436, 0x04bf, 0xc436, 0x21, 0 + .dw 0x04c1, 0xc436, 0x04c1, 0xc436, 0x21, 0 + .dw 0x04c3, 0xc436, 0x04cf, 0xc436, 0x21, 0 + .dw 0x04d1, 0xc436, 0x04d1, 0xc436, 0x21, 0 + .dw 0x04d3, 0xc436, 0x04ff, 0xc436, 0x21, 0 + .dw 0x0501, 0xc436, 0x0501, 0xc436, 0x21, 0 + .dw 0x0503, 0xc436, 0x050f, 0xc436, 0x21, 0 + .dw 0x0511, 0xc436, 0x0511, 0xc436, 0x21, 0 + .dw 0x0513, 0xc436, 0x053f, 0xc436, 0x21, 0 + .dw 0x0541, 0xc436, 0x0541, 0xc436, 0x21, 0 + .dw 0x0543, 0xc436, 0x054f, 0xc436, 0x21, 0 + .dw 0x0551, 0xc436, 0x0551, 0xc436, 0x21, 0 + .dw 0x0553, 0xc436, 0x057f, 0xc436, 0x21, 0 + .dw 0x0581, 0xc436, 0x0581, 0xc436, 0x21, 0 + .dw 0x0583, 0xc436, 0x058f, 0xc436, 0x21, 0 + .dw 0x0591, 0xc436, 0x0591, 0xc436, 0x21, 0 + .dw 0x0593, 0xc436, 0x05bf, 0xc436, 0x21, 0 + .dw 0x05c1, 0xc436, 0x05c1, 0xc436, 0x21, 0 + .dw 0x05c3, 0xc436, 0x05cf, 0xc436, 0x21, 0 + .dw 0x05d1, 0xc436, 0x05d1, 0xc436, 0x21, 0 + .dw 0x05d3, 0xc436, 0x05ff, 0xc436, 0x21, 0 + .dw 0x0601, 0xc436, 0x0601, 0xc436, 0x21, 0 + .dw 0x0603, 0xc436, 0x060f, 0xc436, 0x21, 0 + .dw 0x0611, 0xc436, 0x0611, 0xc436, 0x21, 0 + .dw 0x0613, 0xc436, 0x063f, 0xc436, 0x21, 0 + .dw 0x0641, 0xc436, 0x0641, 0xc436, 0x21, 0 + .dw 0x0643, 0xc436, 0x064f, 0xc436, 0x21, 0 + .dw 0x0651, 0xc436, 0x0651, 0xc436, 0x21, 0 + .dw 0x0653, 0xc436, 0x067f, 0xc436, 0x21, 0 + .dw 0x0681, 0xc436, 0x0681, 0xc436, 0x21, 0 + .dw 0x0683, 0xc436, 0x068f, 0xc436, 0x21, 0 + .dw 0x0691, 0xc436, 0x0691, 0xc436, 0x21, 0 + .dw 0x0693, 0xc436, 0x06bf, 0xc436, 0x21, 0 + .dw 0x06c1, 0xc436, 0x06c1, 0xc436, 0x21, 0 + .dw 0x06c3, 0xc436, 0x06cf, 0xc436, 0x21, 0 + .dw 0x06d1, 0xc436, 0x06d1, 0xc436, 0x21, 0 + .dw 0x06d3, 0xc436, 0x06ff, 0xc436, 0x21, 0 + .dw 0x0701, 0xc436, 0x0701, 0xc436, 0x21, 0 + .dw 0x0703, 0xc436, 0x070f, 0xc436, 0x21, 0 + .dw 0x0711, 0xc436, 0x0711, 0xc436, 0x21, 0 + .dw 0x0713, 0xc436, 0x073f, 0xc436, 0x21, 0 + .dw 0x0741, 0xc436, 0x0741, 0xc436, 0x21, 0 + .dw 0x0743, 0xc436, 0x074f, 0xc436, 0x21, 0 + .dw 0x0751, 0xc436, 0x0751, 0xc436, 0x21, 0 + .dw 0x0753, 0xc436, 0x077f, 0xc436, 0x21, 0 + .dw 0x0781, 0xc436, 0x0781, 0xc436, 0x21, 0 + .dw 0x0783, 0xc436, 0x078f, 0xc436, 0x21, 0 + .dw 0x0791, 0xc436, 0x0791, 0xc436, 0x21, 0 + .dw 0x0793, 0xc436, 0x07bf, 0xc436, 0x21, 0 + .dw 0x07c1, 0xc436, 0x07c1, 0xc436, 0x21, 0 + .dw 0x07c3, 0xc436, 0x07cf, 0xc436, 0x21, 0 + .dw 0x07d1, 0xc436, 0x07d1, 0xc436, 0x21, 0 + .dw 0x07d3, 0xc436, 0x07ff, 0xc436, 0x21, 0 + .dw 0x0801, 0xc436, 0x0801, 0xc436, 0x21, 0 + .dw 0x0803, 0xc436, 0x080f, 0xc436, 0x21, 0 + .dw 0x0811, 0xc436, 0x0811, 0xc436, 0x21, 0 + .dw 0x0813, 0xc436, 0x083f, 0xc436, 0x21, 0 + .dw 0x0841, 0xc436, 0x0841, 0xc436, 0x21, 0 + .dw 0x0843, 0xc436, 0x084f, 0xc436, 0x21, 0 + .dw 0x0851, 0xc436, 0x0851, 0xc436, 0x21, 0 + .dw 0x0853, 0xc436, 0x087f, 0xc436, 0x21, 0 + .dw 0x0881, 0xc436, 0x0881, 0xc436, 0x21, 0 + .dw 0x0883, 0xc436, 0x088f, 0xc436, 0x21, 0 + .dw 0x0891, 0xc436, 0x0891, 0xc436, 0x21, 0 + .dw 0x0893, 0xc436, 0x08bf, 0xc436, 0x21, 0 + .dw 0x08c1, 0xc436, 0x08c1, 0xc436, 0x21, 0 + .dw 0x08c3, 0xc436, 0x08cf, 0xc436, 0x21, 0 + .dw 0x08d1, 0xc436, 0x08d1, 0xc436, 0x21, 0 + .dw 0x08d3, 0xc436, 0x08ff, 0xc436, 0x21, 0 + .dw 0x0901, 0xc436, 0x0901, 0xc436, 0x21, 0 + .dw 0x0903, 0xc436, 0x090f, 0xc436, 0x21, 0 + .dw 0x0911, 0xc436, 0x0911, 0xc436, 0x21, 0 + .dw 0x0913, 0xc436, 0x093f, 0xc436, 0x21, 0 + .dw 0x0941, 0xc436, 0x0941, 0xc436, 0x21, 0 + .dw 0x0943, 0xc436, 0x094f, 0xc436, 0x21, 0 + .dw 0x0951, 0xc436, 0x0951, 0xc436, 0x21, 0 + .dw 0x0953, 0xc436, 0x097f, 0xc436, 0x21, 0 + .dw 0x0981, 0xc436, 0x0981, 0xc436, 0x21, 0 + .dw 0x0983, 0xc436, 0x098f, 0xc436, 0x21, 0 + .dw 0x0991, 0xc436, 0x0991, 0xc436, 0x21, 0 + .dw 0x0993, 0xc436, 0x09bf, 0xc436, 0x21, 0 + .dw 0x09c1, 0xc436, 0x09c1, 0xc436, 0x21, 0 + .dw 0x09c3, 0xc436, 0x09cf, 0xc436, 0x21, 0 + .dw 0x09d1, 0xc436, 0x09d1, 0xc436, 0x21, 0 + .dw 0x09d3, 0xc436, 0x09ff, 0xc436, 0x21, 0 + .dw 0x0a01, 0xc436, 0x0a01, 0xc436, 0x21, 0 + .dw 0x0a03, 0xc436, 0x0a0f, 0xc436, 0x21, 0 + .dw 0x0a11, 0xc436, 0x0a11, 0xc436, 0x21, 0 + .dw 0x0a13, 0xc436, 0x0a3f, 0xc436, 0x21, 0 + .dw 0x0a41, 0xc436, 0x0a41, 0xc436, 0x21, 0 + .dw 0x0a43, 0xc436, 0x0a4f, 0xc436, 0x21, 0 + .dw 0x0a51, 0xc436, 0x0a51, 0xc436, 0x21, 0 + .dw 0x0a53, 0xc436, 0x0a7f, 0xc436, 0x21, 0 + .dw 0x0a81, 0xc436, 0x0a81, 0xc436, 0x21, 0 + .dw 0x0a83, 0xc436, 0x0a8f, 0xc436, 0x21, 0 + .dw 0x0a91, 0xc436, 0x0a91, 0xc436, 0x21, 0 + .dw 0x0a93, 0xc436, 0x0abf, 0xc436, 0x21, 0 + .dw 0x0ac1, 0xc436, 0x0ac1, 0xc436, 0x21, 0 + .dw 0x0ac3, 0xc436, 0x0acf, 0xc436, 0x21, 0 + .dw 0x0ad1, 0xc436, 0x0ad1, 0xc436, 0x21, 0 + .dw 0x0ad3, 0xc436, 0x0aff, 0xc436, 0x21, 0 + .dw 0x0b01, 0xc436, 0x0b01, 0xc436, 0x21, 0 + .dw 0x0b03, 0xc436, 0x0b0f, 0xc436, 0x21, 0 + .dw 0x0b11, 0xc436, 0x0b11, 0xc436, 0x21, 0 + .dw 0x0b13, 0xc436, 0x0b3f, 0xc436, 0x21, 0 + .dw 0x0b41, 0xc436, 0x0b41, 0xc436, 0x21, 0 + .dw 0x0b43, 0xc436, 0x0b4f, 0xc436, 0x21, 0 + .dw 0x0b51, 0xc436, 0x0b51, 0xc436, 0x21, 0 + .dw 0x0b53, 0xc436, 0x0b7f, 0xc436, 0x21, 0 + .dw 0x0b81, 0xc436, 0x0b81, 0xc436, 0x21, 0 + .dw 0x0b83, 0xc436, 0x0b8f, 0xc436, 0x21, 0 + .dw 0x0b91, 0xc436, 0x0b91, 0xc436, 0x21, 0 + .dw 0x0b93, 0xc436, 0x0bbf, 0xc436, 0x21, 0 + .dw 0x0bc1, 0xc436, 0x0bc1, 0xc436, 0x21, 0 + .dw 0x0bc3, 0xc436, 0x0bcf, 0xc436, 0x21, 0 + .dw 0x0bd1, 0xc436, 0x0bd1, 0xc436, 0x21, 0 + .dw 0x0bd3, 0xc436, 0x0bff, 0xc436, 0x21, 0 + .dw 0x0c01, 0xc436, 0x0c01, 0xc436, 0x21, 0 + .dw 0x0c03, 0xc436, 0x0c0f, 0xc436, 0x21, 0 + .dw 0x0c11, 0xc436, 0x0c11, 0xc436, 0x21, 0 + .dw 0x0c13, 0xc436, 0x0c3f, 0xc436, 0x21, 0 + .dw 0x0c41, 0xc436, 0x0c41, 0xc436, 0x21, 0 + .dw 0x0c43, 0xc436, 0x0c4f, 0xc436, 0x21, 0 + .dw 0x0c51, 0xc436, 0x0c51, 0xc436, 0x21, 0 + .dw 0x0c53, 0xc436, 0x0c7f, 0xc436, 0x21, 0 + .dw 0x0c81, 0xc436, 0x0c81, 0xc436, 0x21, 0 + .dw 0x0c83, 0xc436, 0x0c8f, 0xc436, 0x21, 0 + .dw 0x0c91, 0xc436, 0x0c91, 0xc436, 0x21, 0 + .dw 0x0c93, 0xc436, 0x0cbf, 0xc436, 0x21, 0 + .dw 0x0cc1, 0xc436, 0x0cc1, 0xc436, 0x21, 0 + .dw 0x0cc3, 0xc436, 0x0ccf, 0xc436, 0x21, 0 + .dw 0x0cd1, 0xc436, 0x0cd1, 0xc436, 0x21, 0 + .dw 0x0cd3, 0xc436, 0x0cff, 0xc436, 0x21, 0 + .dw 0x0d01, 0xc436, 0x0d01, 0xc436, 0x21, 0 + .dw 0x0d03, 0xc436, 0x0d0f, 0xc436, 0x21, 0 + .dw 0x0d11, 0xc436, 0x0d11, 0xc436, 0x21, 0 + .dw 0x0d13, 0xc436, 0x0d3f, 0xc436, 0x21, 0 + .dw 0x0d41, 0xc436, 0x0d41, 0xc436, 0x21, 0 + .dw 0x0d43, 0xc436, 0x0d4f, 0xc436, 0x21, 0 + .dw 0x0d51, 0xc436, 0x0d51, 0xc436, 0x21, 0 + .dw 0x0d53, 0xc436, 0x0d7f, 0xc436, 0x21, 0 + .dw 0x0d81, 0xc436, 0x0d81, 0xc436, 0x21, 0 + .dw 0x0d83, 0xc436, 0x0d8f, 0xc436, 0x21, 0 + .dw 0x0d91, 0xc436, 0x0d91, 0xc436, 0x21, 0 + .dw 0x0d93, 0xc436, 0x0dbf, 0xc436, 0x21, 0 + .dw 0x0dc1, 0xc436, 0x0dc1, 0xc436, 0x21, 0 + .dw 0x0dc3, 0xc436, 0x0dcf, 0xc436, 0x21, 0 + .dw 0x0dd1, 0xc436, 0x0dd1, 0xc436, 0x21, 0 + .dw 0x0dd3, 0xc436, 0x0dff, 0xc436, 0x21, 0 + .dw 0x0e01, 0xc436, 0x0e01, 0xc436, 0x21, 0 + .dw 0x0e03, 0xc436, 0x0e0f, 0xc436, 0x21, 0 + .dw 0x0e11, 0xc436, 0x0e11, 0xc436, 0x21, 0 + .dw 0x0e13, 0xc436, 0x0e3f, 0xc436, 0x21, 0 + .dw 0x0e41, 0xc436, 0x0e41, 0xc436, 0x21, 0 + .dw 0x0e43, 0xc436, 0x0e4f, 0xc436, 0x21, 0 + .dw 0x0e51, 0xc436, 0x0e51, 0xc436, 0x21, 0 + .dw 0x0e53, 0xc436, 0x0e7f, 0xc436, 0x21, 0 + .dw 0x0e81, 0xc436, 0x0e81, 0xc436, 0x21, 0 + .dw 0x0e83, 0xc436, 0x0e8f, 0xc436, 0x21, 0 + .dw 0x0e91, 0xc436, 0x0e91, 0xc436, 0x21, 0 + .dw 0x0e93, 0xc436, 0x0ebf, 0xc436, 0x21, 0 + .dw 0x0ec1, 0xc436, 0x0ec1, 0xc436, 0x21, 0 + .dw 0x0ec3, 0xc436, 0x0ecf, 0xc436, 0x21, 0 + .dw 0x0ed1, 0xc436, 0x0ed1, 0xc436, 0x21, 0 + .dw 0x0ed3, 0xc436, 0x0eff, 0xc436, 0x21, 0 + .dw 0x0f01, 0xc436, 0x0f01, 0xc436, 0x21, 0 + .dw 0x0f03, 0xc436, 0x0f0f, 0xc436, 0x21, 0 + .dw 0x0f11, 0xc436, 0x0f11, 0xc436, 0x21, 0 + .dw 0x0f13, 0xc436, 0x0f3f, 0xc436, 0x21, 0 + .dw 0x0f41, 0xc436, 0x0f41, 0xc436, 0x21, 0 + .dw 0x0f43, 0xc436, 0x0f4f, 0xc436, 0x21, 0 + .dw 0x0f51, 0xc436, 0x0f51, 0xc436, 0x21, 0 + .dw 0x0f53, 0xc436, 0x0f7f, 0xc436, 0x21, 0 + .dw 0x0f81, 0xc436, 0x0f81, 0xc436, 0x21, 0 + .dw 0x0f83, 0xc436, 0x0f8f, 0xc436, 0x21, 0 + .dw 0x0f91, 0xc436, 0x0f91, 0xc436, 0x21, 0 + .dw 0x0f93, 0xc436, 0x0fbf, 0xc436, 0x21, 0 + .dw 0x0fc1, 0xc436, 0x0fc1, 0xc436, 0x21, 0 + .dw 0x0fc3, 0xc436, 0x0fcf, 0xc436, 0x21, 0 + .dw 0x0fd1, 0xc436, 0x0fd1, 0xc436, 0x21, 0 + .dw 0x0fd3, 0xc436, 0x1fff, 0xc436, 0x21, 0 + .dw 0x2001, 0xc436, 0x2001, 0xc436, 0x21, 0 + .dw 0x2003, 0xc436, 0x200f, 0xc436, 0x21, 0 + .dw 0x2011, 0xc436, 0x2011, 0xc436, 0x21, 0 + .dw 0x2013, 0xc436, 0x203f, 0xc436, 0x21, 0 + .dw 0x2041, 0xc436, 0x2041, 0xc436, 0x21, 0 + .dw 0x2043, 0xc436, 0x204f, 0xc436, 0x21, 0 + .dw 0x2051, 0xc436, 0x2051, 0xc436, 0x21, 0 + .dw 0x2053, 0xc436, 0x207f, 0xc436, 0x21, 0 + .dw 0x2081, 0xc436, 0x2081, 0xc436, 0x21, 0 + .dw 0x2083, 0xc436, 0x208f, 0xc436, 0x21, 0 + .dw 0x2091, 0xc436, 0x2091, 0xc436, 0x21, 0 + .dw 0x2093, 0xc436, 0x20bf, 0xc436, 0x21, 0 + .dw 0x20c1, 0xc436, 0x20c1, 0xc436, 0x21, 0 + .dw 0x20c3, 0xc436, 0x20cf, 0xc436, 0x21, 0 + .dw 0x20d1, 0xc436, 0x20d1, 0xc436, 0x21, 0 + .dw 0x20d3, 0xc436, 0x20ff, 0xc436, 0x21, 0 + .dw 0x2101, 0xc436, 0x2101, 0xc436, 0x21, 0 + .dw 0x2103, 0xc436, 0x210f, 0xc436, 0x21, 0 + .dw 0x2111, 0xc436, 0x2111, 0xc436, 0x21, 0 + .dw 0x2113, 0xc436, 0x213f, 0xc436, 0x21, 0 + .dw 0x2141, 0xc436, 0x2141, 0xc436, 0x21, 0 + .dw 0x2143, 0xc436, 0x214f, 0xc436, 0x21, 0 + .dw 0x2151, 0xc436, 0x2151, 0xc436, 0x21, 0 + .dw 0x2153, 0xc436, 0x217f, 0xc436, 0x21, 0 + .dw 0x2181, 0xc436, 0x2181, 0xc436, 0x21, 0 + .dw 0x2183, 0xc436, 0x218f, 0xc436, 0x21, 0 + .dw 0x2191, 0xc436, 0x2191, 0xc436, 0x21, 0 + .dw 0x2193, 0xc436, 0x21bf, 0xc436, 0x21, 0 + .dw 0x21c1, 0xc436, 0x21c1, 0xc436, 0x21, 0 + .dw 0x21c3, 0xc436, 0x21cf, 0xc436, 0x21, 0 + .dw 0x21d1, 0xc436, 0x21d1, 0xc436, 0x21, 0 + .dw 0x21d3, 0xc436, 0x21ff, 0xc436, 0x21, 0 + .dw 0x2201, 0xc436, 0x2201, 0xc436, 0x21, 0 + .dw 0x2203, 0xc436, 0x220f, 0xc436, 0x21, 0 + .dw 0x2211, 0xc436, 0x2211, 0xc436, 0x21, 0 + .dw 0x2213, 0xc436, 0x223f, 0xc436, 0x21, 0 + .dw 0x2241, 0xc436, 0x2241, 0xc436, 0x21, 0 + .dw 0x2243, 0xc436, 0x224f, 0xc436, 0x21, 0 + .dw 0x2251, 0xc436, 0x2251, 0xc436, 0x21, 0 + .dw 0x2253, 0xc436, 0x227f, 0xc436, 0x21, 0 + .dw 0x2281, 0xc436, 0x2281, 0xc436, 0x21, 0 + .dw 0x2283, 0xc436, 0x228f, 0xc436, 0x21, 0 + .dw 0x2291, 0xc436, 0x2291, 0xc436, 0x21, 0 + .dw 0x2293, 0xc436, 0x22bf, 0xc436, 0x21, 0 + .dw 0x22c1, 0xc436, 0x22c1, 0xc436, 0x21, 0 + .dw 0x22c3, 0xc436, 0x22cf, 0xc436, 0x21, 0 + .dw 0x22d1, 0xc436, 0x22d1, 0xc436, 0x21, 0 + .dw 0x22d3, 0xc436, 0x22ff, 0xc436, 0x21, 0 + .dw 0x2301, 0xc436, 0x2301, 0xc436, 0x21, 0 + .dw 0x2303, 0xc436, 0x230f, 0xc436, 0x21, 0 + .dw 0x2311, 0xc436, 0x2311, 0xc436, 0x21, 0 + .dw 0x2313, 0xc436, 0x233f, 0xc436, 0x21, 0 + .dw 0x2341, 0xc436, 0x2341, 0xc436, 0x21, 0 + .dw 0x2343, 0xc436, 0x234f, 0xc436, 0x21, 0 + .dw 0x2351, 0xc436, 0x2351, 0xc436, 0x21, 0 + .dw 0x2353, 0xc436, 0x237f, 0xc436, 0x21, 0 + .dw 0x2381, 0xc436, 0x2381, 0xc436, 0x21, 0 + .dw 0x2383, 0xc436, 0x238f, 0xc436, 0x21, 0 + .dw 0x2391, 0xc436, 0x2391, 0xc436, 0x21, 0 + .dw 0x2393, 0xc436, 0x23bf, 0xc436, 0x21, 0 + .dw 0x23c1, 0xc436, 0x23c1, 0xc436, 0x21, 0 + .dw 0x23c3, 0xc436, 0x23cf, 0xc436, 0x21, 0 + .dw 0x23d1, 0xc436, 0x23d1, 0xc436, 0x21, 0 + .dw 0x23d3, 0xc436, 0x23ff, 0xc436, 0x21, 0 + .dw 0x2401, 0xc436, 0x2401, 0xc436, 0x21, 0 + .dw 0x2403, 0xc436, 0x240f, 0xc436, 0x21, 0 + .dw 0x2411, 0xc436, 0x2411, 0xc436, 0x21, 0 + .dw 0x2413, 0xc436, 0x243f, 0xc436, 0x21, 0 + .dw 0x2441, 0xc436, 0x2441, 0xc436, 0x21, 0 + .dw 0x2443, 0xc436, 0x244f, 0xc436, 0x21, 0 + .dw 0x2451, 0xc436, 0x2451, 0xc436, 0x21, 0 + .dw 0x2453, 0xc436, 0x247f, 0xc436, 0x21, 0 + .dw 0x2481, 0xc436, 0x2481, 0xc436, 0x21, 0 + .dw 0x2483, 0xc436, 0x248f, 0xc436, 0x21, 0 + .dw 0x2491, 0xc436, 0x2491, 0xc436, 0x21, 0 + .dw 0x2493, 0xc436, 0x24bf, 0xc436, 0x21, 0 + .dw 0x24c1, 0xc436, 0x24c1, 0xc436, 0x21, 0 + .dw 0x24c3, 0xc436, 0x24cf, 0xc436, 0x21, 0 + .dw 0x24d1, 0xc436, 0x24d1, 0xc436, 0x21, 0 + .dw 0x24d3, 0xc436, 0x24ff, 0xc436, 0x21, 0 + .dw 0x2501, 0xc436, 0x2501, 0xc436, 0x21, 0 + .dw 0x2503, 0xc436, 0x250f, 0xc436, 0x21, 0 + .dw 0x2511, 0xc436, 0x2511, 0xc436, 0x21, 0 + .dw 0x2513, 0xc436, 0x253f, 0xc436, 0x21, 0 + .dw 0x2541, 0xc436, 0x2541, 0xc436, 0x21, 0 + .dw 0x2543, 0xc436, 0x254f, 0xc436, 0x21, 0 + .dw 0x2551, 0xc436, 0x2551, 0xc436, 0x21, 0 + .dw 0x2553, 0xc436, 0x257f, 0xc436, 0x21, 0 + .dw 0x2581, 0xc436, 0x2581, 0xc436, 0x21, 0 + .dw 0x2583, 0xc436, 0x258f, 0xc436, 0x21, 0 + .dw 0x2591, 0xc436, 0x2591, 0xc436, 0x21, 0 + .dw 0x2593, 0xc436, 0x25bf, 0xc436, 0x21, 0 + .dw 0x25c1, 0xc436, 0x25c1, 0xc436, 0x21, 0 + .dw 0x25c3, 0xc436, 0x25cf, 0xc436, 0x21, 0 + .dw 0x25d1, 0xc436, 0x25d1, 0xc436, 0x21, 0 + .dw 0x25d3, 0xc436, 0x25ff, 0xc436, 0x21, 0 + .dw 0x2601, 0xc436, 0x2601, 0xc436, 0x21, 0 + .dw 0x2603, 0xc436, 0x260f, 0xc436, 0x21, 0 + .dw 0x2611, 0xc436, 0x2611, 0xc436, 0x21, 0 + .dw 0x2613, 0xc436, 0x263f, 0xc436, 0x21, 0 + .dw 0x2641, 0xc436, 0x2641, 0xc436, 0x21, 0 + .dw 0x2643, 0xc436, 0x264f, 0xc436, 0x21, 0 + .dw 0x2651, 0xc436, 0x2651, 0xc436, 0x21, 0 + .dw 0x2653, 0xc436, 0x267f, 0xc436, 0x21, 0 + .dw 0x2681, 0xc436, 0x2681, 0xc436, 0x21, 0 + .dw 0x2683, 0xc436, 0x268f, 0xc436, 0x21, 0 + .dw 0x2691, 0xc436, 0x2691, 0xc436, 0x21, 0 + .dw 0x2693, 0xc436, 0x26bf, 0xc436, 0x21, 0 + .dw 0x26c1, 0xc436, 0x26c1, 0xc436, 0x21, 0 + .dw 0x26c3, 0xc436, 0x26cf, 0xc436, 0x21, 0 + .dw 0x26d1, 0xc436, 0x26d1, 0xc436, 0x21, 0 + .dw 0x26d3, 0xc436, 0x26ff, 0xc436, 0x21, 0 + .dw 0x2701, 0xc436, 0x2701, 0xc436, 0x21, 0 + .dw 0x2703, 0xc436, 0x270f, 0xc436, 0x21, 0 + .dw 0x2711, 0xc436, 0x2711, 0xc436, 0x21, 0 + .dw 0x2713, 0xc436, 0x273f, 0xc436, 0x21, 0 + .dw 0x2741, 0xc436, 0x2741, 0xc436, 0x21, 0 + .dw 0x2743, 0xc436, 0x274f, 0xc436, 0x21, 0 + .dw 0x2751, 0xc436, 0x2751, 0xc436, 0x21, 0 + .dw 0x2753, 0xc436, 0x277f, 0xc436, 0x21, 0 + .dw 0x2781, 0xc436, 0x2781, 0xc436, 0x21, 0 + .dw 0x2783, 0xc436, 0x278f, 0xc436, 0x21, 0 + .dw 0x2791, 0xc436, 0x2791, 0xc436, 0x21, 0 + .dw 0x2793, 0xc436, 0x27bf, 0xc436, 0x21, 0 + .dw 0x27c1, 0xc436, 0x27c1, 0xc436, 0x21, 0 + .dw 0x27c3, 0xc436, 0x27cf, 0xc436, 0x21, 0 + .dw 0x27d1, 0xc436, 0x27d1, 0xc436, 0x21, 0 + .dw 0x27d3, 0xc436, 0x27ff, 0xc436, 0x21, 0 + .dw 0x2801, 0xc436, 0x2801, 0xc436, 0x21, 0 + .dw 0x2803, 0xc436, 0x280f, 0xc436, 0x21, 0 + .dw 0x2811, 0xc436, 0x2811, 0xc436, 0x21, 0 + .dw 0x2813, 0xc436, 0x283f, 0xc436, 0x21, 0 + .dw 0x2841, 0xc436, 0x2841, 0xc436, 0x21, 0 + .dw 0x2843, 0xc436, 0x284f, 0xc436, 0x21, 0 + .dw 0x2851, 0xc436, 0x2851, 0xc436, 0x21, 0 + .dw 0x2853, 0xc436, 0x287f, 0xc436, 0x21, 0 + .dw 0x2881, 0xc436, 0x2881, 0xc436, 0x21, 0 + .dw 0x2883, 0xc436, 0x288f, 0xc436, 0x21, 0 + .dw 0x2891, 0xc436, 0x2891, 0xc436, 0x21, 0 + .dw 0x2893, 0xc436, 0x28bf, 0xc436, 0x21, 0 + .dw 0x28c1, 0xc436, 0x28c1, 0xc436, 0x21, 0 + .dw 0x28c3, 0xc436, 0x28cf, 0xc436, 0x21, 0 + .dw 0x28d1, 0xc436, 0x28d1, 0xc436, 0x21, 0 + .dw 0x28d3, 0xc436, 0x28ff, 0xc436, 0x21, 0 + .dw 0x2901, 0xc436, 0x2901, 0xc436, 0x21, 0 + .dw 0x2903, 0xc436, 0x290f, 0xc436, 0x21, 0 + .dw 0x2911, 0xc436, 0x2911, 0xc436, 0x21, 0 + .dw 0x2913, 0xc436, 0x293f, 0xc436, 0x21, 0 + .dw 0x2941, 0xc436, 0x2941, 0xc436, 0x21, 0 + .dw 0x2943, 0xc436, 0x294f, 0xc436, 0x21, 0 + .dw 0x2951, 0xc436, 0x2951, 0xc436, 0x21, 0 + .dw 0x2953, 0xc436, 0x297f, 0xc436, 0x21, 0 + .dw 0x2981, 0xc436, 0x2981, 0xc436, 0x21, 0 + .dw 0x2983, 0xc436, 0x298f, 0xc436, 0x21, 0 + .dw 0x2991, 0xc436, 0x2991, 0xc436, 0x21, 0 + .dw 0x2993, 0xc436, 0x29bf, 0xc436, 0x21, 0 + .dw 0x29c1, 0xc436, 0x29c1, 0xc436, 0x21, 0 + .dw 0x29c3, 0xc436, 0x29cf, 0xc436, 0x21, 0 + .dw 0x29d1, 0xc436, 0x29d1, 0xc436, 0x21, 0 + .dw 0x29d3, 0xc436, 0x29ff, 0xc436, 0x21, 0 + .dw 0x2a01, 0xc436, 0x2a01, 0xc436, 0x21, 0 + .dw 0x2a03, 0xc436, 0x2a0f, 0xc436, 0x21, 0 + .dw 0x2a11, 0xc436, 0x2a11, 0xc436, 0x21, 0 + .dw 0x2a13, 0xc436, 0x2a3f, 0xc436, 0x21, 0 + .dw 0x2a41, 0xc436, 0x2a41, 0xc436, 0x21, 0 + .dw 0x2a43, 0xc436, 0x2a4f, 0xc436, 0x21, 0 + .dw 0x2a51, 0xc436, 0x2a51, 0xc436, 0x21, 0 + .dw 0x2a53, 0xc436, 0x2a7f, 0xc436, 0x21, 0 + .dw 0x2a81, 0xc436, 0x2a81, 0xc436, 0x21, 0 + .dw 0x2a83, 0xc436, 0x2a8f, 0xc436, 0x21, 0 + .dw 0x2a91, 0xc436, 0x2a91, 0xc436, 0x21, 0 + .dw 0x2a93, 0xc436, 0x2abf, 0xc436, 0x21, 0 + .dw 0x2ac1, 0xc436, 0x2ac1, 0xc436, 0x21, 0 + .dw 0x2ac3, 0xc436, 0x2acf, 0xc436, 0x21, 0 + .dw 0x2ad1, 0xc436, 0x2ad1, 0xc436, 0x21, 0 + .dw 0x2ad3, 0xc436, 0x2aff, 0xc436, 0x21, 0 + .dw 0x2b01, 0xc436, 0x2b01, 0xc436, 0x21, 0 + .dw 0x2b03, 0xc436, 0x2b0f, 0xc436, 0x21, 0 + .dw 0x2b11, 0xc436, 0x2b11, 0xc436, 0x21, 0 + .dw 0x2b13, 0xc436, 0x2b3f, 0xc436, 0x21, 0 + .dw 0x2b41, 0xc436, 0x2b41, 0xc436, 0x21, 0 + .dw 0x2b43, 0xc436, 0x2b4f, 0xc436, 0x21, 0 + .dw 0x2b51, 0xc436, 0x2b51, 0xc436, 0x21, 0 + .dw 0x2b53, 0xc436, 0x2b7f, 0xc436, 0x21, 0 + .dw 0x2b81, 0xc436, 0x2b81, 0xc436, 0x21, 0 + .dw 0x2b83, 0xc436, 0x2b8f, 0xc436, 0x21, 0 + .dw 0x2b91, 0xc436, 0x2b91, 0xc436, 0x21, 0 + .dw 0x2b93, 0xc436, 0x2bbf, 0xc436, 0x21, 0 + .dw 0x2bc1, 0xc436, 0x2bc1, 0xc436, 0x21, 0 + .dw 0x2bc3, 0xc436, 0x2bcf, 0xc436, 0x21, 0 + .dw 0x2bd1, 0xc436, 0x2bd1, 0xc436, 0x21, 0 + .dw 0x2bd3, 0xc436, 0x2bff, 0xc436, 0x21, 0 + .dw 0x2c01, 0xc436, 0x2c01, 0xc436, 0x21, 0 + .dw 0x2c03, 0xc436, 0x2c0f, 0xc436, 0x21, 0 + .dw 0x2c11, 0xc436, 0x2c11, 0xc436, 0x21, 0 + .dw 0x2c13, 0xc436, 0x2c3f, 0xc436, 0x21, 0 + .dw 0x2c41, 0xc436, 0x2c41, 0xc436, 0x21, 0 + .dw 0x2c43, 0xc436, 0x2c4f, 0xc436, 0x21, 0 + .dw 0x2c51, 0xc436, 0x2c51, 0xc436, 0x21, 0 + .dw 0x2c53, 0xc436, 0x2c7f, 0xc436, 0x21, 0 + .dw 0x2c81, 0xc436, 0x2c81, 0xc436, 0x21, 0 + .dw 0x2c83, 0xc436, 0x2c8f, 0xc436, 0x21, 0 + .dw 0x2c91, 0xc436, 0x2c91, 0xc436, 0x21, 0 + .dw 0x2c93, 0xc436, 0x2cbf, 0xc436, 0x21, 0 + .dw 0x2cc1, 0xc436, 0x2cc1, 0xc436, 0x21, 0 + .dw 0x2cc3, 0xc436, 0x2ccf, 0xc436, 0x21, 0 + .dw 0x2cd1, 0xc436, 0x2cd1, 0xc436, 0x21, 0 + .dw 0x2cd3, 0xc436, 0x2cff, 0xc436, 0x21, 0 + .dw 0x2d01, 0xc436, 0x2d01, 0xc436, 0x21, 0 + .dw 0x2d03, 0xc436, 0x2d0f, 0xc436, 0x21, 0 + .dw 0x2d11, 0xc436, 0x2d11, 0xc436, 0x21, 0 + .dw 0x2d13, 0xc436, 0x2d3f, 0xc436, 0x21, 0 + .dw 0x2d41, 0xc436, 0x2d41, 0xc436, 0x21, 0 + .dw 0x2d43, 0xc436, 0x2d4f, 0xc436, 0x21, 0 + .dw 0x2d51, 0xc436, 0x2d51, 0xc436, 0x21, 0 + .dw 0x2d53, 0xc436, 0x2d7f, 0xc436, 0x21, 0 + .dw 0x2d81, 0xc436, 0x2d81, 0xc436, 0x21, 0 + .dw 0x2d83, 0xc436, 0x2d8f, 0xc436, 0x21, 0 + .dw 0x2d91, 0xc436, 0x2d91, 0xc436, 0x21, 0 + .dw 0x2d93, 0xc436, 0x2dbf, 0xc436, 0x21, 0 + .dw 0x2dc1, 0xc436, 0x2dc1, 0xc436, 0x21, 0 + .dw 0x2dc3, 0xc436, 0x2dcf, 0xc436, 0x21, 0 + .dw 0x2dd1, 0xc436, 0x2dd1, 0xc436, 0x21, 0 + .dw 0x2dd3, 0xc436, 0x2dff, 0xc436, 0x21, 0 + .dw 0x2e01, 0xc436, 0x2e01, 0xc436, 0x21, 0 + .dw 0x2e03, 0xc436, 0x2e0f, 0xc436, 0x21, 0 + .dw 0x2e11, 0xc436, 0x2e11, 0xc436, 0x21, 0 + .dw 0x2e13, 0xc436, 0x2e3f, 0xc436, 0x21, 0 + .dw 0x2e41, 0xc436, 0x2e41, 0xc436, 0x21, 0 + .dw 0x2e43, 0xc436, 0x2e4f, 0xc436, 0x21, 0 + .dw 0x2e51, 0xc436, 0x2e51, 0xc436, 0x21, 0 + .dw 0x2e53, 0xc436, 0x2e7f, 0xc436, 0x21, 0 + .dw 0x2e81, 0xc436, 0x2e81, 0xc436, 0x21, 0 + .dw 0x2e83, 0xc436, 0x2e8f, 0xc436, 0x21, 0 + .dw 0x2e91, 0xc436, 0x2e91, 0xc436, 0x21, 0 + .dw 0x2e93, 0xc436, 0x2ebf, 0xc436, 0x21, 0 + .dw 0x2ec1, 0xc436, 0x2ec1, 0xc436, 0x21, 0 + .dw 0x2ec3, 0xc436, 0x2ecf, 0xc436, 0x21, 0 + .dw 0x2ed1, 0xc436, 0x2ed1, 0xc436, 0x21, 0 + .dw 0x2ed3, 0xc436, 0x2eff, 0xc436, 0x21, 0 + .dw 0x2f01, 0xc436, 0x2f01, 0xc436, 0x21, 0 + .dw 0x2f03, 0xc436, 0x2f0f, 0xc436, 0x21, 0 + .dw 0x2f11, 0xc436, 0x2f11, 0xc436, 0x21, 0 + .dw 0x2f13, 0xc436, 0x2f3f, 0xc436, 0x21, 0 + .dw 0x2f41, 0xc436, 0x2f41, 0xc436, 0x21, 0 + .dw 0x2f43, 0xc436, 0x2f4f, 0xc436, 0x21, 0 + .dw 0x2f51, 0xc436, 0x2f51, 0xc436, 0x21, 0 + .dw 0x2f53, 0xc436, 0x2f7f, 0xc436, 0x21, 0 + .dw 0x2f81, 0xc436, 0x2f81, 0xc436, 0x21, 0 + .dw 0x2f83, 0xc436, 0x2f8f, 0xc436, 0x21, 0 + .dw 0x2f91, 0xc436, 0x2f91, 0xc436, 0x21, 0 + .dw 0x2f93, 0xc436, 0x2fbf, 0xc436, 0x21, 0 + .dw 0x2fc1, 0xc436, 0x2fc1, 0xc436, 0x21, 0 + .dw 0x2fc3, 0xc436, 0x2fcf, 0xc436, 0x21, 0 + .dw 0x2fd1, 0xc436, 0x2fd1, 0xc436, 0x21, 0 + .dw 0x2fd3, 0xc436, 0x3fff, 0xc436, 0x21, 0 + .dw 0x4001, 0xc436, 0x4001, 0xc436, 0x21, 0 + .dw 0x4003, 0xc436, 0x400f, 0xc436, 0x21, 0 + .dw 0x4011, 0xc436, 0x4011, 0xc436, 0x21, 0 + .dw 0x4013, 0xc436, 0x403f, 0xc436, 0x21, 0 + .dw 0x4041, 0xc436, 0x4041, 0xc436, 0x21, 0 + .dw 0x4043, 0xc436, 0x404f, 0xc436, 0x21, 0 + .dw 0x4051, 0xc436, 0x4051, 0xc436, 0x21, 0 + .dw 0x4053, 0xc436, 0x407f, 0xc436, 0x21, 0 + .dw 0x4081, 0xc436, 0x4081, 0xc436, 0x21, 0 + .dw 0x4083, 0xc436, 0x408f, 0xc436, 0x21, 0 + .dw 0x4091, 0xc436, 0x4091, 0xc436, 0x21, 0 + .dw 0x4093, 0xc436, 0x40bf, 0xc436, 0x21, 0 + .dw 0x40c1, 0xc436, 0x40c1, 0xc436, 0x21, 0 + .dw 0x40c3, 0xc436, 0x40cf, 0xc436, 0x21, 0 + .dw 0x40d1, 0xc436, 0x40d1, 0xc436, 0x21, 0 + .dw 0x40d3, 0xc436, 0x40ff, 0xc436, 0x21, 0 + .dw 0x4101, 0xc436, 0x4101, 0xc436, 0x21, 0 + .dw 0x4103, 0xc436, 0x410f, 0xc436, 0x21, 0 + .dw 0x4111, 0xc436, 0x4111, 0xc436, 0x21, 0 + .dw 0x4113, 0xc436, 0x413f, 0xc436, 0x21, 0 + .dw 0x4141, 0xc436, 0x4141, 0xc436, 0x21, 0 + .dw 0x4143, 0xc436, 0x414f, 0xc436, 0x21, 0 + .dw 0x4151, 0xc436, 0x4151, 0xc436, 0x21, 0 + .dw 0x4153, 0xc436, 0x417f, 0xc436, 0x21, 0 + .dw 0x4181, 0xc436, 0x4181, 0xc436, 0x21, 0 + .dw 0x4183, 0xc436, 0x418f, 0xc436, 0x21, 0 + .dw 0x4191, 0xc436, 0x4191, 0xc436, 0x21, 0 + .dw 0x4193, 0xc436, 0x41bf, 0xc436, 0x21, 0 + .dw 0x41c1, 0xc436, 0x41c1, 0xc436, 0x21, 0 + .dw 0x41c3, 0xc436, 0x41cf, 0xc436, 0x21, 0 + .dw 0x41d1, 0xc436, 0x41d1, 0xc436, 0x21, 0 + .dw 0x41d3, 0xc436, 0x41ff, 0xc436, 0x21, 0 + .dw 0x4201, 0xc436, 0x4201, 0xc436, 0x21, 0 + .dw 0x4203, 0xc436, 0x420f, 0xc436, 0x21, 0 + .dw 0x4211, 0xc436, 0x4211, 0xc436, 0x21, 0 + .dw 0x4213, 0xc436, 0x423f, 0xc436, 0x21, 0 + .dw 0x4241, 0xc436, 0x4241, 0xc436, 0x21, 0 + .dw 0x4243, 0xc436, 0x424f, 0xc436, 0x21, 0 + .dw 0x4251, 0xc436, 0x4251, 0xc436, 0x21, 0 + .dw 0x4253, 0xc436, 0x427f, 0xc436, 0x21, 0 + .dw 0x4281, 0xc436, 0x4281, 0xc436, 0x21, 0 + .dw 0x4283, 0xc436, 0x428f, 0xc436, 0x21, 0 + .dw 0x4291, 0xc436, 0x4291, 0xc436, 0x21, 0 + .dw 0x4293, 0xc436, 0x42bf, 0xc436, 0x21, 0 + .dw 0x42c1, 0xc436, 0x42c1, 0xc436, 0x21, 0 + .dw 0x42c3, 0xc436, 0x42cf, 0xc436, 0x21, 0 + .dw 0x42d1, 0xc436, 0x42d1, 0xc436, 0x21, 0 + .dw 0x42d3, 0xc436, 0x42ff, 0xc436, 0x21, 0 + .dw 0x4301, 0xc436, 0x4301, 0xc436, 0x21, 0 + .dw 0x4303, 0xc436, 0x430f, 0xc436, 0x21, 0 + .dw 0x4311, 0xc436, 0x4311, 0xc436, 0x21, 0 + .dw 0x4313, 0xc436, 0x433f, 0xc436, 0x21, 0 + .dw 0x4341, 0xc436, 0x4341, 0xc436, 0x21, 0 + .dw 0x4343, 0xc436, 0x434f, 0xc436, 0x21, 0 + .dw 0x4351, 0xc436, 0x4351, 0xc436, 0x21, 0 + .dw 0x4353, 0xc436, 0x437f, 0xc436, 0x21, 0 + .dw 0x4381, 0xc436, 0x4381, 0xc436, 0x21, 0 + .dw 0x4383, 0xc436, 0x438f, 0xc436, 0x21, 0 + .dw 0x4391, 0xc436, 0x4391, 0xc436, 0x21, 0 + .dw 0x4393, 0xc436, 0x43bf, 0xc436, 0x21, 0 + .dw 0x43c1, 0xc436, 0x43c1, 0xc436, 0x21, 0 + .dw 0x43c3, 0xc436, 0x43cf, 0xc436, 0x21, 0 + .dw 0x43d1, 0xc436, 0x43d1, 0xc436, 0x21, 0 + .dw 0x43d3, 0xc436, 0x43ff, 0xc436, 0x21, 0 + .dw 0x4401, 0xc436, 0x4401, 0xc436, 0x21, 0 + .dw 0x4403, 0xc436, 0x440f, 0xc436, 0x21, 0 + .dw 0x4411, 0xc436, 0x4411, 0xc436, 0x21, 0 + .dw 0x4413, 0xc436, 0x443f, 0xc436, 0x21, 0 + .dw 0x4441, 0xc436, 0x4441, 0xc436, 0x21, 0 + .dw 0x4443, 0xc436, 0x444f, 0xc436, 0x21, 0 + .dw 0x4451, 0xc436, 0x4451, 0xc436, 0x21, 0 + .dw 0x4453, 0xc436, 0x447f, 0xc436, 0x21, 0 + .dw 0x4481, 0xc436, 0x4481, 0xc436, 0x21, 0 + .dw 0x4483, 0xc436, 0x448f, 0xc436, 0x21, 0 + .dw 0x4491, 0xc436, 0x4491, 0xc436, 0x21, 0 + .dw 0x4493, 0xc436, 0x44bf, 0xc436, 0x21, 0 + .dw 0x44c1, 0xc436, 0x44c1, 0xc436, 0x21, 0 + .dw 0x44c3, 0xc436, 0x44cf, 0xc436, 0x21, 0 + .dw 0x44d1, 0xc436, 0x44d1, 0xc436, 0x21, 0 + .dw 0x44d3, 0xc436, 0x44ff, 0xc436, 0x21, 0 + .dw 0x4501, 0xc436, 0x4501, 0xc436, 0x21, 0 + .dw 0x4503, 0xc436, 0x450f, 0xc436, 0x21, 0 + .dw 0x4511, 0xc436, 0x4511, 0xc436, 0x21, 0 + .dw 0x4513, 0xc436, 0x453f, 0xc436, 0x21, 0 + .dw 0x4541, 0xc436, 0x4541, 0xc436, 0x21, 0 + .dw 0x4543, 0xc436, 0x454f, 0xc436, 0x21, 0 + .dw 0x4551, 0xc436, 0x4551, 0xc436, 0x21, 0 + .dw 0x4553, 0xc436, 0x457f, 0xc436, 0x21, 0 + .dw 0x4581, 0xc436, 0x4581, 0xc436, 0x21, 0 + .dw 0x4583, 0xc436, 0x458f, 0xc436, 0x21, 0 + .dw 0x4591, 0xc436, 0x4591, 0xc436, 0x21, 0 + .dw 0x4593, 0xc436, 0x45bf, 0xc436, 0x21, 0 + .dw 0x45c1, 0xc436, 0x45c1, 0xc436, 0x21, 0 + .dw 0x45c3, 0xc436, 0x45cf, 0xc436, 0x21, 0 + .dw 0x45d1, 0xc436, 0x45d1, 0xc436, 0x21, 0 + .dw 0x45d3, 0xc436, 0x45ff, 0xc436, 0x21, 0 + .dw 0x4601, 0xc436, 0x4601, 0xc436, 0x21, 0 + .dw 0x4603, 0xc436, 0x460f, 0xc436, 0x21, 0 + .dw 0x4611, 0xc436, 0x4611, 0xc436, 0x21, 0 + .dw 0x4613, 0xc436, 0x463f, 0xc436, 0x21, 0 + .dw 0x4641, 0xc436, 0x4641, 0xc436, 0x21, 0 + .dw 0x4643, 0xc436, 0x464f, 0xc436, 0x21, 0 + .dw 0x4651, 0xc436, 0x4651, 0xc436, 0x21, 0 + .dw 0x4653, 0xc436, 0x467f, 0xc436, 0x21, 0 + .dw 0x4681, 0xc436, 0x4681, 0xc436, 0x21, 0 + .dw 0x4683, 0xc436, 0x468f, 0xc436, 0x21, 0 + .dw 0x4691, 0xc436, 0x4691, 0xc436, 0x21, 0 + .dw 0x4693, 0xc436, 0x46bf, 0xc436, 0x21, 0 + .dw 0x46c1, 0xc436, 0x46c1, 0xc436, 0x21, 0 + .dw 0x46c3, 0xc436, 0x46cf, 0xc436, 0x21, 0 + .dw 0x46d1, 0xc436, 0x46d1, 0xc436, 0x21, 0 + .dw 0x46d3, 0xc436, 0x46ff, 0xc436, 0x21, 0 + .dw 0x4701, 0xc436, 0x4701, 0xc436, 0x21, 0 + .dw 0x4703, 0xc436, 0x470f, 0xc436, 0x21, 0 + .dw 0x4711, 0xc436, 0x4711, 0xc436, 0x21, 0 + .dw 0x4713, 0xc436, 0x473f, 0xc436, 0x21, 0 + .dw 0x4741, 0xc436, 0x4741, 0xc436, 0x21, 0 + .dw 0x4743, 0xc436, 0x474f, 0xc436, 0x21, 0 + .dw 0x4751, 0xc436, 0x4751, 0xc436, 0x21, 0 + .dw 0x4753, 0xc436, 0x477f, 0xc436, 0x21, 0 + .dw 0x4781, 0xc436, 0x4781, 0xc436, 0x21, 0 + .dw 0x4783, 0xc436, 0x478f, 0xc436, 0x21, 0 + .dw 0x4791, 0xc436, 0x4791, 0xc436, 0x21, 0 + .dw 0x4793, 0xc436, 0x47bf, 0xc436, 0x21, 0 + .dw 0x47c1, 0xc436, 0x47c1, 0xc436, 0x21, 0 + .dw 0x47c3, 0xc436, 0x47cf, 0xc436, 0x21, 0 + .dw 0x47d1, 0xc436, 0x47d1, 0xc436, 0x21, 0 + .dw 0x47d3, 0xc436, 0x47ff, 0xc436, 0x21, 0 + .dw 0x4801, 0xc436, 0x4801, 0xc436, 0x21, 0 + .dw 0x4803, 0xc436, 0x480f, 0xc436, 0x21, 0 + .dw 0x4811, 0xc436, 0x4811, 0xc436, 0x21, 0 + .dw 0x4813, 0xc436, 0x483f, 0xc436, 0x21, 0 + .dw 0x4841, 0xc436, 0x4841, 0xc436, 0x21, 0 + .dw 0x4843, 0xc436, 0x484f, 0xc436, 0x21, 0 + .dw 0x4851, 0xc436, 0x4851, 0xc436, 0x21, 0 + .dw 0x4853, 0xc436, 0x487f, 0xc436, 0x21, 0 + .dw 0x4881, 0xc436, 0x4881, 0xc436, 0x21, 0 + .dw 0x4883, 0xc436, 0x488f, 0xc436, 0x21, 0 + .dw 0x4891, 0xc436, 0x4891, 0xc436, 0x21, 0 + .dw 0x4893, 0xc436, 0x48bf, 0xc436, 0x21, 0 + .dw 0x48c1, 0xc436, 0x48c1, 0xc436, 0x21, 0 + .dw 0x48c3, 0xc436, 0x48cf, 0xc436, 0x21, 0 + .dw 0x48d1, 0xc436, 0x48d1, 0xc436, 0x21, 0 + .dw 0x48d3, 0xc436, 0x48ff, 0xc436, 0x21, 0 + .dw 0x4901, 0xc436, 0x4901, 0xc436, 0x21, 0 + .dw 0x4903, 0xc436, 0x490f, 0xc436, 0x21, 0 + .dw 0x4911, 0xc436, 0x4911, 0xc436, 0x21, 0 + .dw 0x4913, 0xc436, 0x493f, 0xc436, 0x21, 0 + .dw 0x4941, 0xc436, 0x4941, 0xc436, 0x21, 0 + .dw 0x4943, 0xc436, 0x494f, 0xc436, 0x21, 0 + .dw 0x4951, 0xc436, 0x4951, 0xc436, 0x21, 0 + .dw 0x4953, 0xc436, 0x497f, 0xc436, 0x21, 0 + .dw 0x4981, 0xc436, 0x4981, 0xc436, 0x21, 0 + .dw 0x4983, 0xc436, 0x498f, 0xc436, 0x21, 0 + .dw 0x4991, 0xc436, 0x4991, 0xc436, 0x21, 0 + .dw 0x4993, 0xc436, 0x49bf, 0xc436, 0x21, 0 + .dw 0x49c1, 0xc436, 0x49c1, 0xc436, 0x21, 0 + .dw 0x49c3, 0xc436, 0x49cf, 0xc436, 0x21, 0 + .dw 0x49d1, 0xc436, 0x49d1, 0xc436, 0x21, 0 + .dw 0x49d3, 0xc436, 0x49ff, 0xc436, 0x21, 0 + .dw 0x4a01, 0xc436, 0x4a01, 0xc436, 0x21, 0 + .dw 0x4a03, 0xc436, 0x4a0f, 0xc436, 0x21, 0 + .dw 0x4a11, 0xc436, 0x4a11, 0xc436, 0x21, 0 + .dw 0x4a13, 0xc436, 0x4a3f, 0xc436, 0x21, 0 + .dw 0x4a41, 0xc436, 0x4a41, 0xc436, 0x21, 0 + .dw 0x4a43, 0xc436, 0x4a4f, 0xc436, 0x21, 0 + .dw 0x4a51, 0xc436, 0x4a51, 0xc436, 0x21, 0 + .dw 0x4a53, 0xc436, 0x4a7f, 0xc436, 0x21, 0 + .dw 0x4a81, 0xc436, 0x4a81, 0xc436, 0x21, 0 + .dw 0x4a83, 0xc436, 0x4a8f, 0xc436, 0x21, 0 + .dw 0x4a91, 0xc436, 0x4a91, 0xc436, 0x21, 0 + .dw 0x4a93, 0xc436, 0x4abf, 0xc436, 0x21, 0 + .dw 0x4ac1, 0xc436, 0x4ac1, 0xc436, 0x21, 0 + .dw 0x4ac3, 0xc436, 0x4acf, 0xc436, 0x21, 0 + .dw 0x4ad1, 0xc436, 0x4ad1, 0xc436, 0x21, 0 + .dw 0x4ad3, 0xc436, 0x4aff, 0xc436, 0x21, 0 + .dw 0x4b01, 0xc436, 0x4b01, 0xc436, 0x21, 0 + .dw 0x4b03, 0xc436, 0x4b0f, 0xc436, 0x21, 0 + .dw 0x4b11, 0xc436, 0x4b11, 0xc436, 0x21, 0 + .dw 0x4b13, 0xc436, 0x4b3f, 0xc436, 0x21, 0 + .dw 0x4b41, 0xc436, 0x4b41, 0xc436, 0x21, 0 + .dw 0x4b43, 0xc436, 0x4b4f, 0xc436, 0x21, 0 + .dw 0x4b51, 0xc436, 0x4b51, 0xc436, 0x21, 0 + .dw 0x4b53, 0xc436, 0x4b7f, 0xc436, 0x21, 0 + .dw 0x4b81, 0xc436, 0x4b81, 0xc436, 0x21, 0 + .dw 0x4b83, 0xc436, 0x4b8f, 0xc436, 0x21, 0 + .dw 0x4b91, 0xc436, 0x4b91, 0xc436, 0x21, 0 + .dw 0x4b93, 0xc436, 0x4bbf, 0xc436, 0x21, 0 + .dw 0x4bc1, 0xc436, 0x4bc1, 0xc436, 0x21, 0 + .dw 0x4bc3, 0xc436, 0x4bcf, 0xc436, 0x21, 0 + .dw 0x4bd1, 0xc436, 0x4bd1, 0xc436, 0x21, 0 + .dw 0x4bd3, 0xc436, 0x4bff, 0xc436, 0x21, 0 + .dw 0x4c01, 0xc436, 0x4c01, 0xc436, 0x21, 0 + .dw 0x4c03, 0xc436, 0x4c0f, 0xc436, 0x21, 0 + .dw 0x4c11, 0xc436, 0x4c11, 0xc436, 0x21, 0 + .dw 0x4c13, 0xc436, 0x4c3f, 0xc436, 0x21, 0 + .dw 0x4c41, 0xc436, 0x4c41, 0xc436, 0x21, 0 + .dw 0x4c43, 0xc436, 0x4c4f, 0xc436, 0x21, 0 + .dw 0x4c51, 0xc436, 0x4c51, 0xc436, 0x21, 0 + .dw 0x4c53, 0xc436, 0x4c7f, 0xc436, 0x21, 0 + .dw 0x4c81, 0xc436, 0x4c81, 0xc436, 0x21, 0 + .dw 0x4c83, 0xc436, 0x4c8f, 0xc436, 0x21, 0 + .dw 0x4c91, 0xc436, 0x4c91, 0xc436, 0x21, 0 + .dw 0x4c93, 0xc436, 0x4cbf, 0xc436, 0x21, 0 + .dw 0x4cc1, 0xc436, 0x4cc1, 0xc436, 0x21, 0 + .dw 0x4cc3, 0xc436, 0x4ccf, 0xc436, 0x21, 0 + .dw 0x4cd1, 0xc436, 0x4cd1, 0xc436, 0x21, 0 + .dw 0x4cd3, 0xc436, 0x4cff, 0xc436, 0x21, 0 + .dw 0x4d01, 0xc436, 0x4d01, 0xc436, 0x21, 0 + .dw 0x4d03, 0xc436, 0x4d0f, 0xc436, 0x21, 0 + .dw 0x4d11, 0xc436, 0x4d11, 0xc436, 0x21, 0 + .dw 0x4d13, 0xc436, 0x4d3f, 0xc436, 0x21, 0 + .dw 0x4d41, 0xc436, 0x4d41, 0xc436, 0x21, 0 + .dw 0x4d43, 0xc436, 0x4d4f, 0xc436, 0x21, 0 + .dw 0x4d51, 0xc436, 0x4d51, 0xc436, 0x21, 0 + .dw 0x4d53, 0xc436, 0x4d7f, 0xc436, 0x21, 0 + .dw 0x4d81, 0xc436, 0x4d81, 0xc436, 0x21, 0 + .dw 0x4d83, 0xc436, 0x4d8f, 0xc436, 0x21, 0 + .dw 0x4d91, 0xc436, 0x4d91, 0xc436, 0x21, 0 + .dw 0x4d93, 0xc436, 0x4dbf, 0xc436, 0x21, 0 + .dw 0x4dc1, 0xc436, 0x4dc1, 0xc436, 0x21, 0 + .dw 0x4dc3, 0xc436, 0x4dcf, 0xc436, 0x21, 0 + .dw 0x4dd1, 0xc436, 0x4dd1, 0xc436, 0x21, 0 + .dw 0x4dd3, 0xc436, 0x4dff, 0xc436, 0x21, 0 + .dw 0x4e01, 0xc436, 0x4e01, 0xc436, 0x21, 0 + .dw 0x4e03, 0xc436, 0x4e0f, 0xc436, 0x21, 0 + .dw 0x4e11, 0xc436, 0x4e11, 0xc436, 0x21, 0 + .dw 0x4e13, 0xc436, 0x4e3f, 0xc436, 0x21, 0 + .dw 0x4e41, 0xc436, 0x4e41, 0xc436, 0x21, 0 + .dw 0x4e43, 0xc436, 0x4e4f, 0xc436, 0x21, 0 + .dw 0x4e51, 0xc436, 0x4e51, 0xc436, 0x21, 0 + .dw 0x4e53, 0xc436, 0x4e7f, 0xc436, 0x21, 0 + .dw 0x4e81, 0xc436, 0x4e81, 0xc436, 0x21, 0 + .dw 0x4e83, 0xc436, 0x4e8f, 0xc436, 0x21, 0 + .dw 0x4e91, 0xc436, 0x4e91, 0xc436, 0x21, 0 + .dw 0x4e93, 0xc436, 0x4ebf, 0xc436, 0x21, 0 + .dw 0x4ec1, 0xc436, 0x4ec1, 0xc436, 0x21, 0 + .dw 0x4ec3, 0xc436, 0x4ecf, 0xc436, 0x21, 0 + .dw 0x4ed1, 0xc436, 0x4ed1, 0xc436, 0x21, 0 + .dw 0x4ed3, 0xc436, 0x4eff, 0xc436, 0x21, 0 + .dw 0x4f01, 0xc436, 0x4f01, 0xc436, 0x21, 0 + .dw 0x4f03, 0xc436, 0x4f0f, 0xc436, 0x21, 0 + .dw 0x4f11, 0xc436, 0x4f11, 0xc436, 0x21, 0 + .dw 0x4f13, 0xc436, 0x4f3f, 0xc436, 0x21, 0 + .dw 0x4f41, 0xc436, 0x4f41, 0xc436, 0x21, 0 + .dw 0x4f43, 0xc436, 0x4f4f, 0xc436, 0x21, 0 + .dw 0x4f51, 0xc436, 0x4f51, 0xc436, 0x21, 0 + .dw 0x4f53, 0xc436, 0x4f7f, 0xc436, 0x21, 0 + .dw 0x4f81, 0xc436, 0x4f81, 0xc436, 0x21, 0 + .dw 0x4f83, 0xc436, 0x4f8f, 0xc436, 0x21, 0 + .dw 0x4f91, 0xc436, 0x4f91, 0xc436, 0x21, 0 + .dw 0x4f93, 0xc436, 0x4fbf, 0xc436, 0x21, 0 + .dw 0x4fc1, 0xc436, 0x4fc1, 0xc436, 0x21, 0 + .dw 0x4fc3, 0xc436, 0x4fcf, 0xc436, 0x21, 0 + .dw 0x4fd1, 0xc436, 0x4fd1, 0xc436, 0x21, 0 + .dw 0x4fd3, 0xc436, 0x5fff, 0xc436, 0x21, 0 + .dw 0x6001, 0xc436, 0x6001, 0xc436, 0x21, 0 + .dw 0x6003, 0xc436, 0x600f, 0xc436, 0x21, 0 + .dw 0x6011, 0xc436, 0x6011, 0xc436, 0x21, 0 + .dw 0x6013, 0xc436, 0x603f, 0xc436, 0x21, 0 + .dw 0x6041, 0xc436, 0x6041, 0xc436, 0x21, 0 + .dw 0x6043, 0xc436, 0x604f, 0xc436, 0x21, 0 + .dw 0x6051, 0xc436, 0x6051, 0xc436, 0x21, 0 + .dw 0x6053, 0xc436, 0x607f, 0xc436, 0x21, 0 + .dw 0x6081, 0xc436, 0x6081, 0xc436, 0x21, 0 + .dw 0x6083, 0xc436, 0x608f, 0xc436, 0x21, 0 + .dw 0x6091, 0xc436, 0x6091, 0xc436, 0x21, 0 + .dw 0x6093, 0xc436, 0x60bf, 0xc436, 0x21, 0 + .dw 0x60c1, 0xc436, 0x60c1, 0xc436, 0x21, 0 + .dw 0x60c3, 0xc436, 0x60cf, 0xc436, 0x21, 0 + .dw 0x60d1, 0xc436, 0x60d1, 0xc436, 0x21, 0 + .dw 0x60d3, 0xc436, 0x60ff, 0xc436, 0x21, 0 + .dw 0x6101, 0xc436, 0x6101, 0xc436, 0x21, 0 + .dw 0x6103, 0xc436, 0x610f, 0xc436, 0x21, 0 + .dw 0x6111, 0xc436, 0x6111, 0xc436, 0x21, 0 + .dw 0x6113, 0xc436, 0x613f, 0xc436, 0x21, 0 + .dw 0x6141, 0xc436, 0x6141, 0xc436, 0x21, 0 + .dw 0x6143, 0xc436, 0x614f, 0xc436, 0x21, 0 + .dw 0x6151, 0xc436, 0x6151, 0xc436, 0x21, 0 + .dw 0x6153, 0xc436, 0x617f, 0xc436, 0x21, 0 + .dw 0x6181, 0xc436, 0x6181, 0xc436, 0x21, 0 + .dw 0x6183, 0xc436, 0x618f, 0xc436, 0x21, 0 + .dw 0x6191, 0xc436, 0x6191, 0xc436, 0x21, 0 + .dw 0x6193, 0xc436, 0x61bf, 0xc436, 0x21, 0 + .dw 0x61c1, 0xc436, 0x61c1, 0xc436, 0x21, 0 + .dw 0x61c3, 0xc436, 0x61cf, 0xc436, 0x21, 0 + .dw 0x61d1, 0xc436, 0x61d1, 0xc436, 0x21, 0 + .dw 0x61d3, 0xc436, 0x61ff, 0xc436, 0x21, 0 + .dw 0x6201, 0xc436, 0x6201, 0xc436, 0x21, 0 + .dw 0x6203, 0xc436, 0x620f, 0xc436, 0x21, 0 + .dw 0x6211, 0xc436, 0x6211, 0xc436, 0x21, 0 + .dw 0x6213, 0xc436, 0x623f, 0xc436, 0x21, 0 + .dw 0x6241, 0xc436, 0x6241, 0xc436, 0x21, 0 + .dw 0x6243, 0xc436, 0x624f, 0xc436, 0x21, 0 + .dw 0x6251, 0xc436, 0x6251, 0xc436, 0x21, 0 + .dw 0x6253, 0xc436, 0x627f, 0xc436, 0x21, 0 + .dw 0x6281, 0xc436, 0x6281, 0xc436, 0x21, 0 + .dw 0x6283, 0xc436, 0x628f, 0xc436, 0x21, 0 + .dw 0x6291, 0xc436, 0x6291, 0xc436, 0x21, 0 + .dw 0x6293, 0xc436, 0x62bf, 0xc436, 0x21, 0 + .dw 0x62c1, 0xc436, 0x62c1, 0xc436, 0x21, 0 + .dw 0x62c3, 0xc436, 0x62cf, 0xc436, 0x21, 0 + .dw 0x62d1, 0xc436, 0x62d1, 0xc436, 0x21, 0 + .dw 0x62d3, 0xc436, 0x62ff, 0xc436, 0x21, 0 + .dw 0x6301, 0xc436, 0x6301, 0xc436, 0x21, 0 + .dw 0x6303, 0xc436, 0x630f, 0xc436, 0x21, 0 + .dw 0x6311, 0xc436, 0x6311, 0xc436, 0x21, 0 + .dw 0x6313, 0xc436, 0x633f, 0xc436, 0x21, 0 + .dw 0x6341, 0xc436, 0x6341, 0xc436, 0x21, 0 + .dw 0x6343, 0xc436, 0x634f, 0xc436, 0x21, 0 + .dw 0x6351, 0xc436, 0x6351, 0xc436, 0x21, 0 + .dw 0x6353, 0xc436, 0x637f, 0xc436, 0x21, 0 + .dw 0x6381, 0xc436, 0x6381, 0xc436, 0x21, 0 + .dw 0x6383, 0xc436, 0x638f, 0xc436, 0x21, 0 + .dw 0x6391, 0xc436, 0x6391, 0xc436, 0x21, 0 + .dw 0x6393, 0xc436, 0x63bf, 0xc436, 0x21, 0 + .dw 0x63c1, 0xc436, 0x63c1, 0xc436, 0x21, 0 + .dw 0x63c3, 0xc436, 0x63cf, 0xc436, 0x21, 0 + .dw 0x63d1, 0xc436, 0x63d1, 0xc436, 0x21, 0 + .dw 0x63d3, 0xc436, 0x63ff, 0xc436, 0x21, 0 + .dw 0x6401, 0xc436, 0x6401, 0xc436, 0x21, 0 + .dw 0x6403, 0xc436, 0x640f, 0xc436, 0x21, 0 + .dw 0x6411, 0xc436, 0x6411, 0xc436, 0x21, 0 + .dw 0x6413, 0xc436, 0x643f, 0xc436, 0x21, 0 + .dw 0x6441, 0xc436, 0x6441, 0xc436, 0x21, 0 + .dw 0x6443, 0xc436, 0x644f, 0xc436, 0x21, 0 + .dw 0x6451, 0xc436, 0x6451, 0xc436, 0x21, 0 + .dw 0x6453, 0xc436, 0x647f, 0xc436, 0x21, 0 + .dw 0x6481, 0xc436, 0x6481, 0xc436, 0x21, 0 + .dw 0x6483, 0xc436, 0x648f, 0xc436, 0x21, 0 + .dw 0x6491, 0xc436, 0x6491, 0xc436, 0x21, 0 + .dw 0x6493, 0xc436, 0x64bf, 0xc436, 0x21, 0 + .dw 0x64c1, 0xc436, 0x64c1, 0xc436, 0x21, 0 + .dw 0x64c3, 0xc436, 0x64cf, 0xc436, 0x21, 0 + .dw 0x64d1, 0xc436, 0x64d1, 0xc436, 0x21, 0 + .dw 0x64d3, 0xc436, 0x64ff, 0xc436, 0x21, 0 + .dw 0x6501, 0xc436, 0x6501, 0xc436, 0x21, 0 + .dw 0x6503, 0xc436, 0x650f, 0xc436, 0x21, 0 + .dw 0x6511, 0xc436, 0x6511, 0xc436, 0x21, 0 + .dw 0x6513, 0xc436, 0x653f, 0xc436, 0x21, 0 + .dw 0x6541, 0xc436, 0x6541, 0xc436, 0x21, 0 + .dw 0x6543, 0xc436, 0x654f, 0xc436, 0x21, 0 + .dw 0x6551, 0xc436, 0x6551, 0xc436, 0x21, 0 + .dw 0x6553, 0xc436, 0x657f, 0xc436, 0x21, 0 + .dw 0x6581, 0xc436, 0x6581, 0xc436, 0x21, 0 + .dw 0x6583, 0xc436, 0x658f, 0xc436, 0x21, 0 + .dw 0x6591, 0xc436, 0x6591, 0xc436, 0x21, 0 + .dw 0x6593, 0xc436, 0x65bf, 0xc436, 0x21, 0 + .dw 0x65c1, 0xc436, 0x65c1, 0xc436, 0x21, 0 + .dw 0x65c3, 0xc436, 0x65cf, 0xc436, 0x21, 0 + .dw 0x65d1, 0xc436, 0x65d1, 0xc436, 0x21, 0 + .dw 0x65d3, 0xc436, 0x65ff, 0xc436, 0x21, 0 + .dw 0x6601, 0xc436, 0x6601, 0xc436, 0x21, 0 + .dw 0x6603, 0xc436, 0x660f, 0xc436, 0x21, 0 + .dw 0x6611, 0xc436, 0x6611, 0xc436, 0x21, 0 + .dw 0x6613, 0xc436, 0x663f, 0xc436, 0x21, 0 + .dw 0x6641, 0xc436, 0x6641, 0xc436, 0x21, 0 + .dw 0x6643, 0xc436, 0x664f, 0xc436, 0x21, 0 + .dw 0x6651, 0xc436, 0x6651, 0xc436, 0x21, 0 + .dw 0x6653, 0xc436, 0x667f, 0xc436, 0x21, 0 + .dw 0x6681, 0xc436, 0x6681, 0xc436, 0x21, 0 + .dw 0x6683, 0xc436, 0x668f, 0xc436, 0x21, 0 + .dw 0x6691, 0xc436, 0x6691, 0xc436, 0x21, 0 + .dw 0x6693, 0xc436, 0x66bf, 0xc436, 0x21, 0 + .dw 0x66c1, 0xc436, 0x66c1, 0xc436, 0x21, 0 + .dw 0x66c3, 0xc436, 0x66cf, 0xc436, 0x21, 0 + .dw 0x66d1, 0xc436, 0x66d1, 0xc436, 0x21, 0 + .dw 0x66d3, 0xc436, 0x66ff, 0xc436, 0x21, 0 + .dw 0x6701, 0xc436, 0x6701, 0xc436, 0x21, 0 + .dw 0x6703, 0xc436, 0x670f, 0xc436, 0x21, 0 + .dw 0x6711, 0xc436, 0x6711, 0xc436, 0x21, 0 + .dw 0x6713, 0xc436, 0x673f, 0xc436, 0x21, 0 + .dw 0x6741, 0xc436, 0x6741, 0xc436, 0x21, 0 + .dw 0x6743, 0xc436, 0x674f, 0xc436, 0x21, 0 + .dw 0x6751, 0xc436, 0x6751, 0xc436, 0x21, 0 + .dw 0x6753, 0xc436, 0x677f, 0xc436, 0x21, 0 + .dw 0x6781, 0xc436, 0x6781, 0xc436, 0x21, 0 + .dw 0x6783, 0xc436, 0x678f, 0xc436, 0x21, 0 + .dw 0x6791, 0xc436, 0x6791, 0xc436, 0x21, 0 + .dw 0x6793, 0xc436, 0x67bf, 0xc436, 0x21, 0 + .dw 0x67c1, 0xc436, 0x67c1, 0xc436, 0x21, 0 + .dw 0x67c3, 0xc436, 0x67cf, 0xc436, 0x21, 0 + .dw 0x67d1, 0xc436, 0x67d1, 0xc436, 0x21, 0 + .dw 0x67d3, 0xc436, 0x67ff, 0xc436, 0x21, 0 + .dw 0x6801, 0xc436, 0x6801, 0xc436, 0x21, 0 + .dw 0x6803, 0xc436, 0x680f, 0xc436, 0x21, 0 + .dw 0x6811, 0xc436, 0x6811, 0xc436, 0x21, 0 + .dw 0x6813, 0xc436, 0x683f, 0xc436, 0x21, 0 + .dw 0x6841, 0xc436, 0x6841, 0xc436, 0x21, 0 + .dw 0x6843, 0xc436, 0x684f, 0xc436, 0x21, 0 + .dw 0x6851, 0xc436, 0x6851, 0xc436, 0x21, 0 + .dw 0x6853, 0xc436, 0x687f, 0xc436, 0x21, 0 + .dw 0x6881, 0xc436, 0x6881, 0xc436, 0x21, 0 + .dw 0x6883, 0xc436, 0x688f, 0xc436, 0x21, 0 + .dw 0x6891, 0xc436, 0x6891, 0xc436, 0x21, 0 + .dw 0x6893, 0xc436, 0x68bf, 0xc436, 0x21, 0 + .dw 0x68c1, 0xc436, 0x68c1, 0xc436, 0x21, 0 + .dw 0x68c3, 0xc436, 0x68cf, 0xc436, 0x21, 0 + .dw 0x68d1, 0xc436, 0x68d1, 0xc436, 0x21, 0 + .dw 0x68d3, 0xc436, 0x68ff, 0xc436, 0x21, 0 + .dw 0x6901, 0xc436, 0x6901, 0xc436, 0x21, 0 + .dw 0x6903, 0xc436, 0x690f, 0xc436, 0x21, 0 + .dw 0x6911, 0xc436, 0x6911, 0xc436, 0x21, 0 + .dw 0x6913, 0xc436, 0x693f, 0xc436, 0x21, 0 + .dw 0x6941, 0xc436, 0x6941, 0xc436, 0x21, 0 + .dw 0x6943, 0xc436, 0x694f, 0xc436, 0x21, 0 + .dw 0x6951, 0xc436, 0x6951, 0xc436, 0x21, 0 + .dw 0x6953, 0xc436, 0x697f, 0xc436, 0x21, 0 + .dw 0x6981, 0xc436, 0x6981, 0xc436, 0x21, 0 + .dw 0x6983, 0xc436, 0x698f, 0xc436, 0x21, 0 + .dw 0x6991, 0xc436, 0x6991, 0xc436, 0x21, 0 + .dw 0x6993, 0xc436, 0x69bf, 0xc436, 0x21, 0 + .dw 0x69c1, 0xc436, 0x69c1, 0xc436, 0x21, 0 + .dw 0x69c3, 0xc436, 0x69cf, 0xc436, 0x21, 0 + .dw 0x69d1, 0xc436, 0x69d1, 0xc436, 0x21, 0 + .dw 0x69d3, 0xc436, 0x69ff, 0xc436, 0x21, 0 + .dw 0x6a01, 0xc436, 0x6a01, 0xc436, 0x21, 0 + .dw 0x6a03, 0xc436, 0x6a0f, 0xc436, 0x21, 0 + .dw 0x6a11, 0xc436, 0x6a11, 0xc436, 0x21, 0 + .dw 0x6a13, 0xc436, 0x6a3f, 0xc436, 0x21, 0 + .dw 0x6a41, 0xc436, 0x6a41, 0xc436, 0x21, 0 + .dw 0x6a43, 0xc436, 0x6a4f, 0xc436, 0x21, 0 + .dw 0x6a51, 0xc436, 0x6a51, 0xc436, 0x21, 0 + .dw 0x6a53, 0xc436, 0x6a7f, 0xc436, 0x21, 0 + .dw 0x6a81, 0xc436, 0x6a81, 0xc436, 0x21, 0 + .dw 0x6a83, 0xc436, 0x6a8f, 0xc436, 0x21, 0 + .dw 0x6a91, 0xc436, 0x6a91, 0xc436, 0x21, 0 + .dw 0x6a93, 0xc436, 0x6abf, 0xc436, 0x21, 0 + .dw 0x6ac1, 0xc436, 0x6ac1, 0xc436, 0x21, 0 + .dw 0x6ac3, 0xc436, 0x6acf, 0xc436, 0x21, 0 + .dw 0x6ad1, 0xc436, 0x6ad1, 0xc436, 0x21, 0 + .dw 0x6ad3, 0xc436, 0x6aff, 0xc436, 0x21, 0 + .dw 0x6b01, 0xc436, 0x6b01, 0xc436, 0x21, 0 + .dw 0x6b03, 0xc436, 0x6b0f, 0xc436, 0x21, 0 + .dw 0x6b11, 0xc436, 0x6b11, 0xc436, 0x21, 0 + .dw 0x6b13, 0xc436, 0x6b3f, 0xc436, 0x21, 0 + .dw 0x6b41, 0xc436, 0x6b41, 0xc436, 0x21, 0 + .dw 0x6b43, 0xc436, 0x6b4f, 0xc436, 0x21, 0 + .dw 0x6b51, 0xc436, 0x6b51, 0xc436, 0x21, 0 + .dw 0x6b53, 0xc436, 0x6b7f, 0xc436, 0x21, 0 + .dw 0x6b81, 0xc436, 0x6b81, 0xc436, 0x21, 0 + .dw 0x6b83, 0xc436, 0x6b8f, 0xc436, 0x21, 0 + .dw 0x6b91, 0xc436, 0x6b91, 0xc436, 0x21, 0 + .dw 0x6b93, 0xc436, 0x6bbf, 0xc436, 0x21, 0 + .dw 0x6bc1, 0xc436, 0x6bc1, 0xc436, 0x21, 0 + .dw 0x6bc3, 0xc436, 0x6bcf, 0xc436, 0x21, 0 + .dw 0x6bd1, 0xc436, 0x6bd1, 0xc436, 0x21, 0 + .dw 0x6bd3, 0xc436, 0x6bff, 0xc436, 0x21, 0 + .dw 0x6c01, 0xc436, 0x6c01, 0xc436, 0x21, 0 + .dw 0x6c03, 0xc436, 0x6c0f, 0xc436, 0x21, 0 + .dw 0x6c11, 0xc436, 0x6c11, 0xc436, 0x21, 0 + .dw 0x6c13, 0xc436, 0x6c3f, 0xc436, 0x21, 0 + .dw 0x6c41, 0xc436, 0x6c41, 0xc436, 0x21, 0 + .dw 0x6c43, 0xc436, 0x6c4f, 0xc436, 0x21, 0 + .dw 0x6c51, 0xc436, 0x6c51, 0xc436, 0x21, 0 + .dw 0x6c53, 0xc436, 0x6c7f, 0xc436, 0x21, 0 + .dw 0x6c81, 0xc436, 0x6c81, 0xc436, 0x21, 0 + .dw 0x6c83, 0xc436, 0x6c8f, 0xc436, 0x21, 0 + .dw 0x6c91, 0xc436, 0x6c91, 0xc436, 0x21, 0 + .dw 0x6c93, 0xc436, 0x6cbf, 0xc436, 0x21, 0 + .dw 0x6cc1, 0xc436, 0x6cc1, 0xc436, 0x21, 0 + .dw 0x6cc3, 0xc436, 0x6ccf, 0xc436, 0x21, 0 + .dw 0x6cd1, 0xc436, 0x6cd1, 0xc436, 0x21, 0 + .dw 0x6cd3, 0xc436, 0x6cff, 0xc436, 0x21, 0 + .dw 0x6d01, 0xc436, 0x6d01, 0xc436, 0x21, 0 + .dw 0x6d03, 0xc436, 0x6d0f, 0xc436, 0x21, 0 + .dw 0x6d11, 0xc436, 0x6d11, 0xc436, 0x21, 0 + .dw 0x6d13, 0xc436, 0x6d3f, 0xc436, 0x21, 0 + .dw 0x6d41, 0xc436, 0x6d41, 0xc436, 0x21, 0 + .dw 0x6d43, 0xc436, 0x6d4f, 0xc436, 0x21, 0 + .dw 0x6d51, 0xc436, 0x6d51, 0xc436, 0x21, 0 + .dw 0x6d53, 0xc436, 0x6d7f, 0xc436, 0x21, 0 + .dw 0x6d81, 0xc436, 0x6d81, 0xc436, 0x21, 0 + .dw 0x6d83, 0xc436, 0x6d8f, 0xc436, 0x21, 0 + .dw 0x6d91, 0xc436, 0x6d91, 0xc436, 0x21, 0 + .dw 0x6d93, 0xc436, 0x6dbf, 0xc436, 0x21, 0 + .dw 0x6dc1, 0xc436, 0x6dc1, 0xc436, 0x21, 0 + .dw 0x6dc3, 0xc436, 0x6dcf, 0xc436, 0x21, 0 + .dw 0x6dd1, 0xc436, 0x6dd1, 0xc436, 0x21, 0 + .dw 0x6dd3, 0xc436, 0x6dff, 0xc436, 0x21, 0 + .dw 0x6e01, 0xc436, 0x6e01, 0xc436, 0x21, 0 + .dw 0x6e03, 0xc436, 0x6e0f, 0xc436, 0x21, 0 + .dw 0x6e11, 0xc436, 0x6e11, 0xc436, 0x21, 0 + .dw 0x6e13, 0xc436, 0x6e3f, 0xc436, 0x21, 0 + .dw 0x6e41, 0xc436, 0x6e41, 0xc436, 0x21, 0 + .dw 0x6e43, 0xc436, 0x6e4f, 0xc436, 0x21, 0 + .dw 0x6e51, 0xc436, 0x6e51, 0xc436, 0x21, 0 + .dw 0x6e53, 0xc436, 0x6e7f, 0xc436, 0x21, 0 + .dw 0x6e81, 0xc436, 0x6e81, 0xc436, 0x21, 0 + .dw 0x6e83, 0xc436, 0x6e8f, 0xc436, 0x21, 0 + .dw 0x6e91, 0xc436, 0x6e91, 0xc436, 0x21, 0 + .dw 0x6e93, 0xc436, 0x6ebf, 0xc436, 0x21, 0 + .dw 0x6ec1, 0xc436, 0x6ec1, 0xc436, 0x21, 0 + .dw 0x6ec3, 0xc436, 0x6ecf, 0xc436, 0x21, 0 + .dw 0x6ed1, 0xc436, 0x6ed1, 0xc436, 0x21, 0 + .dw 0x6ed3, 0xc436, 0x6eff, 0xc436, 0x21, 0 + .dw 0x6f01, 0xc436, 0x6f01, 0xc436, 0x21, 0 + .dw 0x6f03, 0xc436, 0x6f0f, 0xc436, 0x21, 0 + .dw 0x6f11, 0xc436, 0x6f11, 0xc436, 0x21, 0 + .dw 0x6f13, 0xc436, 0x6f3f, 0xc436, 0x21, 0 + .dw 0x6f41, 0xc436, 0x6f41, 0xc436, 0x21, 0 + .dw 0x6f43, 0xc436, 0x6f4f, 0xc436, 0x21, 0 + .dw 0x6f51, 0xc436, 0x6f51, 0xc436, 0x21, 0 + .dw 0x6f53, 0xc436, 0x6f7f, 0xc436, 0x21, 0 + .dw 0x6f81, 0xc436, 0x6f81, 0xc436, 0x21, 0 + .dw 0x6f83, 0xc436, 0x6f8f, 0xc436, 0x21, 0 + .dw 0x6f91, 0xc436, 0x6f91, 0xc436, 0x21, 0 + .dw 0x6f93, 0xc436, 0x6fbf, 0xc436, 0x21, 0 + .dw 0x6fc1, 0xc436, 0x6fc1, 0xc436, 0x21, 0 + .dw 0x6fc3, 0xc436, 0x6fcf, 0xc436, 0x21, 0 + .dw 0x6fd1, 0xc436, 0x6fd1, 0xc436, 0x21, 0 + .dw 0x6fd3, 0xc436, 0xffff, 0xc436, 0x21, 0 + .dw 0x0001, 0xc437, 0x0001, 0xc437, 0x21, 0 + .dw 0x0003, 0xc437, 0x000f, 0xc437, 0x21, 0 + .dw 0x0011, 0xc437, 0x0011, 0xc437, 0x21, 0 + .dw 0x0013, 0xc437, 0x003f, 0xc437, 0x21, 0 + .dw 0x0041, 0xc437, 0x0041, 0xc437, 0x21, 0 + .dw 0x0043, 0xc437, 0x004f, 0xc437, 0x21, 0 + .dw 0x0051, 0xc437, 0x0051, 0xc437, 0x21, 0 + .dw 0x0053, 0xc437, 0x007f, 0xc437, 0x21, 0 + .dw 0x0081, 0xc437, 0x0081, 0xc437, 0x21, 0 + .dw 0x0083, 0xc437, 0x008f, 0xc437, 0x21, 0 + .dw 0x0091, 0xc437, 0x0091, 0xc437, 0x21, 0 + .dw 0x0093, 0xc437, 0x00bf, 0xc437, 0x21, 0 + .dw 0x00c1, 0xc437, 0x00c1, 0xc437, 0x21, 0 + .dw 0x00c3, 0xc437, 0x00cf, 0xc437, 0x21, 0 + .dw 0x00d1, 0xc437, 0x00d1, 0xc437, 0x21, 0 + .dw 0x00d3, 0xc437, 0x00ff, 0xc437, 0x21, 0 + .dw 0x0101, 0xc437, 0x0101, 0xc437, 0x21, 0 + .dw 0x0103, 0xc437, 0x010f, 0xc437, 0x21, 0 + .dw 0x0111, 0xc437, 0x0111, 0xc437, 0x21, 0 + .dw 0x0113, 0xc437, 0x013f, 0xc437, 0x21, 0 + .dw 0x0141, 0xc437, 0x0141, 0xc437, 0x21, 0 + .dw 0x0143, 0xc437, 0x014f, 0xc437, 0x21, 0 + .dw 0x0151, 0xc437, 0x0151, 0xc437, 0x21, 0 + .dw 0x0153, 0xc437, 0x017f, 0xc437, 0x21, 0 + .dw 0x0181, 0xc437, 0x0181, 0xc437, 0x21, 0 + .dw 0x0183, 0xc437, 0x018f, 0xc437, 0x21, 0 + .dw 0x0191, 0xc437, 0x0191, 0xc437, 0x21, 0 + .dw 0x0193, 0xc437, 0x01bf, 0xc437, 0x21, 0 + .dw 0x01c1, 0xc437, 0x01c1, 0xc437, 0x21, 0 + .dw 0x01c3, 0xc437, 0x01cf, 0xc437, 0x21, 0 + .dw 0x01d1, 0xc437, 0x01d1, 0xc437, 0x21, 0 + .dw 0x01d3, 0xc437, 0x01ff, 0xc437, 0x21, 0 + .dw 0x0201, 0xc437, 0x0201, 0xc437, 0x21, 0 + .dw 0x0203, 0xc437, 0x020f, 0xc437, 0x21, 0 + .dw 0x0211, 0xc437, 0x0211, 0xc437, 0x21, 0 + .dw 0x0213, 0xc437, 0x023f, 0xc437, 0x21, 0 + .dw 0x0241, 0xc437, 0x0241, 0xc437, 0x21, 0 + .dw 0x0243, 0xc437, 0x024f, 0xc437, 0x21, 0 + .dw 0x0251, 0xc437, 0x0251, 0xc437, 0x21, 0 + .dw 0x0253, 0xc437, 0x027f, 0xc437, 0x21, 0 + .dw 0x0281, 0xc437, 0x0281, 0xc437, 0x21, 0 + .dw 0x0283, 0xc437, 0x028f, 0xc437, 0x21, 0 + .dw 0x0291, 0xc437, 0x0291, 0xc437, 0x21, 0 + .dw 0x0293, 0xc437, 0x02bf, 0xc437, 0x21, 0 + .dw 0x02c1, 0xc437, 0x02c1, 0xc437, 0x21, 0 + .dw 0x02c3, 0xc437, 0x02cf, 0xc437, 0x21, 0 + .dw 0x02d1, 0xc437, 0x02d1, 0xc437, 0x21, 0 + .dw 0x02d3, 0xc437, 0x02ff, 0xc437, 0x21, 0 + .dw 0x0301, 0xc437, 0x0301, 0xc437, 0x21, 0 + .dw 0x0303, 0xc437, 0x030f, 0xc437, 0x21, 0 + .dw 0x0311, 0xc437, 0x0311, 0xc437, 0x21, 0 + .dw 0x0313, 0xc437, 0x033f, 0xc437, 0x21, 0 + .dw 0x0341, 0xc437, 0x0341, 0xc437, 0x21, 0 + .dw 0x0343, 0xc437, 0x034f, 0xc437, 0x21, 0 + .dw 0x0351, 0xc437, 0x0351, 0xc437, 0x21, 0 + .dw 0x0353, 0xc437, 0x037f, 0xc437, 0x21, 0 + .dw 0x0381, 0xc437, 0x0381, 0xc437, 0x21, 0 + .dw 0x0383, 0xc437, 0x038f, 0xc437, 0x21, 0 + .dw 0x0391, 0xc437, 0x0391, 0xc437, 0x21, 0 + .dw 0x0393, 0xc437, 0x03bf, 0xc437, 0x21, 0 + .dw 0x03c1, 0xc437, 0x03c1, 0xc437, 0x21, 0 + .dw 0x03c3, 0xc437, 0x03cf, 0xc437, 0x21, 0 + .dw 0x03d1, 0xc437, 0x03d1, 0xc437, 0x21, 0 + .dw 0x03d3, 0xc437, 0x03ff, 0xc437, 0x21, 0 + .dw 0x0401, 0xc437, 0x0401, 0xc437, 0x21, 0 + .dw 0x0403, 0xc437, 0x040f, 0xc437, 0x21, 0 + .dw 0x0411, 0xc437, 0x0411, 0xc437, 0x21, 0 + .dw 0x0413, 0xc437, 0x043f, 0xc437, 0x21, 0 + .dw 0x0441, 0xc437, 0x0441, 0xc437, 0x21, 0 + .dw 0x0443, 0xc437, 0x044f, 0xc437, 0x21, 0 + .dw 0x0451, 0xc437, 0x0451, 0xc437, 0x21, 0 + .dw 0x0453, 0xc437, 0x047f, 0xc437, 0x21, 0 + .dw 0x0481, 0xc437, 0x0481, 0xc437, 0x21, 0 + .dw 0x0483, 0xc437, 0x048f, 0xc437, 0x21, 0 + .dw 0x0491, 0xc437, 0x0491, 0xc437, 0x21, 0 + .dw 0x0493, 0xc437, 0x04bf, 0xc437, 0x21, 0 + .dw 0x04c1, 0xc437, 0x04c1, 0xc437, 0x21, 0 + .dw 0x04c3, 0xc437, 0x04cf, 0xc437, 0x21, 0 + .dw 0x04d1, 0xc437, 0x04d1, 0xc437, 0x21, 0 + .dw 0x04d3, 0xc437, 0x04ff, 0xc437, 0x21, 0 + .dw 0x0501, 0xc437, 0x0501, 0xc437, 0x21, 0 + .dw 0x0503, 0xc437, 0x050f, 0xc437, 0x21, 0 + .dw 0x0511, 0xc437, 0x0511, 0xc437, 0x21, 0 + .dw 0x0513, 0xc437, 0x053f, 0xc437, 0x21, 0 + .dw 0x0541, 0xc437, 0x0541, 0xc437, 0x21, 0 + .dw 0x0543, 0xc437, 0x054f, 0xc437, 0x21, 0 + .dw 0x0551, 0xc437, 0x0551, 0xc437, 0x21, 0 + .dw 0x0553, 0xc437, 0x057f, 0xc437, 0x21, 0 + .dw 0x0581, 0xc437, 0x0581, 0xc437, 0x21, 0 + .dw 0x0583, 0xc437, 0x058f, 0xc437, 0x21, 0 + .dw 0x0591, 0xc437, 0x0591, 0xc437, 0x21, 0 + .dw 0x0593, 0xc437, 0x05bf, 0xc437, 0x21, 0 + .dw 0x05c1, 0xc437, 0x05c1, 0xc437, 0x21, 0 + .dw 0x05c3, 0xc437, 0x05cf, 0xc437, 0x21, 0 + .dw 0x05d1, 0xc437, 0x05d1, 0xc437, 0x21, 0 + .dw 0x05d3, 0xc437, 0x05ff, 0xc437, 0x21, 0 + .dw 0x0601, 0xc437, 0x0601, 0xc437, 0x21, 0 + .dw 0x0603, 0xc437, 0x060f, 0xc437, 0x21, 0 + .dw 0x0611, 0xc437, 0x0611, 0xc437, 0x21, 0 + .dw 0x0613, 0xc437, 0x063f, 0xc437, 0x21, 0 + .dw 0x0641, 0xc437, 0x0641, 0xc437, 0x21, 0 + .dw 0x0643, 0xc437, 0x064f, 0xc437, 0x21, 0 + .dw 0x0651, 0xc437, 0x0651, 0xc437, 0x21, 0 + .dw 0x0653, 0xc437, 0x067f, 0xc437, 0x21, 0 + .dw 0x0681, 0xc437, 0x0681, 0xc437, 0x21, 0 + .dw 0x0683, 0xc437, 0x068f, 0xc437, 0x21, 0 + .dw 0x0691, 0xc437, 0x0691, 0xc437, 0x21, 0 + .dw 0x0693, 0xc437, 0x06bf, 0xc437, 0x21, 0 + .dw 0x06c1, 0xc437, 0x06c1, 0xc437, 0x21, 0 + .dw 0x06c3, 0xc437, 0x06cf, 0xc437, 0x21, 0 + .dw 0x06d1, 0xc437, 0x06d1, 0xc437, 0x21, 0 + .dw 0x06d3, 0xc437, 0x06ff, 0xc437, 0x21, 0 + .dw 0x0701, 0xc437, 0x0701, 0xc437, 0x21, 0 + .dw 0x0703, 0xc437, 0x070f, 0xc437, 0x21, 0 + .dw 0x0711, 0xc437, 0x0711, 0xc437, 0x21, 0 + .dw 0x0713, 0xc437, 0x073f, 0xc437, 0x21, 0 + .dw 0x0741, 0xc437, 0x0741, 0xc437, 0x21, 0 + .dw 0x0743, 0xc437, 0x074f, 0xc437, 0x21, 0 + .dw 0x0751, 0xc437, 0x0751, 0xc437, 0x21, 0 + .dw 0x0753, 0xc437, 0x077f, 0xc437, 0x21, 0 + .dw 0x0781, 0xc437, 0x0781, 0xc437, 0x21, 0 + .dw 0x0783, 0xc437, 0x078f, 0xc437, 0x21, 0 + .dw 0x0791, 0xc437, 0x0791, 0xc437, 0x21, 0 + .dw 0x0793, 0xc437, 0x07bf, 0xc437, 0x21, 0 + .dw 0x07c1, 0xc437, 0x07c1, 0xc437, 0x21, 0 + .dw 0x07c3, 0xc437, 0x07cf, 0xc437, 0x21, 0 + .dw 0x07d1, 0xc437, 0x07d1, 0xc437, 0x21, 0 + .dw 0x07d3, 0xc437, 0x07ff, 0xc437, 0x21, 0 + .dw 0x0801, 0xc437, 0x0801, 0xc437, 0x21, 0 + .dw 0x0803, 0xc437, 0x080f, 0xc437, 0x21, 0 + .dw 0x0811, 0xc437, 0x0811, 0xc437, 0x21, 0 + .dw 0x0813, 0xc437, 0x083f, 0xc437, 0x21, 0 + .dw 0x0841, 0xc437, 0x0841, 0xc437, 0x21, 0 + .dw 0x0843, 0xc437, 0x084f, 0xc437, 0x21, 0 + .dw 0x0851, 0xc437, 0x0851, 0xc437, 0x21, 0 + .dw 0x0853, 0xc437, 0x087f, 0xc437, 0x21, 0 + .dw 0x0881, 0xc437, 0x0881, 0xc437, 0x21, 0 + .dw 0x0883, 0xc437, 0x088f, 0xc437, 0x21, 0 + .dw 0x0891, 0xc437, 0x0891, 0xc437, 0x21, 0 + .dw 0x0893, 0xc437, 0x08bf, 0xc437, 0x21, 0 + .dw 0x08c1, 0xc437, 0x08c1, 0xc437, 0x21, 0 + .dw 0x08c3, 0xc437, 0x08cf, 0xc437, 0x21, 0 + .dw 0x08d1, 0xc437, 0x08d1, 0xc437, 0x21, 0 + .dw 0x08d3, 0xc437, 0x08ff, 0xc437, 0x21, 0 + .dw 0x0901, 0xc437, 0x0901, 0xc437, 0x21, 0 + .dw 0x0903, 0xc437, 0x090f, 0xc437, 0x21, 0 + .dw 0x0911, 0xc437, 0x0911, 0xc437, 0x21, 0 + .dw 0x0913, 0xc437, 0x093f, 0xc437, 0x21, 0 + .dw 0x0941, 0xc437, 0x0941, 0xc437, 0x21, 0 + .dw 0x0943, 0xc437, 0x094f, 0xc437, 0x21, 0 + .dw 0x0951, 0xc437, 0x0951, 0xc437, 0x21, 0 + .dw 0x0953, 0xc437, 0x097f, 0xc437, 0x21, 0 + .dw 0x0981, 0xc437, 0x0981, 0xc437, 0x21, 0 + .dw 0x0983, 0xc437, 0x098f, 0xc437, 0x21, 0 + .dw 0x0991, 0xc437, 0x0991, 0xc437, 0x21, 0 + .dw 0x0993, 0xc437, 0x09bf, 0xc437, 0x21, 0 + .dw 0x09c1, 0xc437, 0x09c1, 0xc437, 0x21, 0 + .dw 0x09c3, 0xc437, 0x09cf, 0xc437, 0x21, 0 + .dw 0x09d1, 0xc437, 0x09d1, 0xc437, 0x21, 0 + .dw 0x09d3, 0xc437, 0x09ff, 0xc437, 0x21, 0 + .dw 0x0a01, 0xc437, 0x0a01, 0xc437, 0x21, 0 + .dw 0x0a03, 0xc437, 0x0a0f, 0xc437, 0x21, 0 + .dw 0x0a11, 0xc437, 0x0a11, 0xc437, 0x21, 0 + .dw 0x0a13, 0xc437, 0x0a3f, 0xc437, 0x21, 0 + .dw 0x0a41, 0xc437, 0x0a41, 0xc437, 0x21, 0 + .dw 0x0a43, 0xc437, 0x0a4f, 0xc437, 0x21, 0 + .dw 0x0a51, 0xc437, 0x0a51, 0xc437, 0x21, 0 + .dw 0x0a53, 0xc437, 0x0a7f, 0xc437, 0x21, 0 + .dw 0x0a81, 0xc437, 0x0a81, 0xc437, 0x21, 0 + .dw 0x0a83, 0xc437, 0x0a8f, 0xc437, 0x21, 0 + .dw 0x0a91, 0xc437, 0x0a91, 0xc437, 0x21, 0 + .dw 0x0a93, 0xc437, 0x0abf, 0xc437, 0x21, 0 + .dw 0x0ac1, 0xc437, 0x0ac1, 0xc437, 0x21, 0 + .dw 0x0ac3, 0xc437, 0x0acf, 0xc437, 0x21, 0 + .dw 0x0ad1, 0xc437, 0x0ad1, 0xc437, 0x21, 0 + .dw 0x0ad3, 0xc437, 0x0aff, 0xc437, 0x21, 0 + .dw 0x0b01, 0xc437, 0x0b01, 0xc437, 0x21, 0 + .dw 0x0b03, 0xc437, 0x0b0f, 0xc437, 0x21, 0 + .dw 0x0b11, 0xc437, 0x0b11, 0xc437, 0x21, 0 + .dw 0x0b13, 0xc437, 0x0b3f, 0xc437, 0x21, 0 + .dw 0x0b41, 0xc437, 0x0b41, 0xc437, 0x21, 0 + .dw 0x0b43, 0xc437, 0x0b4f, 0xc437, 0x21, 0 + .dw 0x0b51, 0xc437, 0x0b51, 0xc437, 0x21, 0 + .dw 0x0b53, 0xc437, 0x0b7f, 0xc437, 0x21, 0 + .dw 0x0b81, 0xc437, 0x0b81, 0xc437, 0x21, 0 + .dw 0x0b83, 0xc437, 0x0b8f, 0xc437, 0x21, 0 + .dw 0x0b91, 0xc437, 0x0b91, 0xc437, 0x21, 0 + .dw 0x0b93, 0xc437, 0x0bbf, 0xc437, 0x21, 0 + .dw 0x0bc1, 0xc437, 0x0bc1, 0xc437, 0x21, 0 + .dw 0x0bc3, 0xc437, 0x0bcf, 0xc437, 0x21, 0 + .dw 0x0bd1, 0xc437, 0x0bd1, 0xc437, 0x21, 0 + .dw 0x0bd3, 0xc437, 0x0bff, 0xc437, 0x21, 0 + .dw 0x0c01, 0xc437, 0x0c01, 0xc437, 0x21, 0 + .dw 0x0c03, 0xc437, 0x0c0f, 0xc437, 0x21, 0 + .dw 0x0c11, 0xc437, 0x0c11, 0xc437, 0x21, 0 + .dw 0x0c13, 0xc437, 0x0c3f, 0xc437, 0x21, 0 + .dw 0x0c41, 0xc437, 0x0c41, 0xc437, 0x21, 0 + .dw 0x0c43, 0xc437, 0x0c4f, 0xc437, 0x21, 0 + .dw 0x0c51, 0xc437, 0x0c51, 0xc437, 0x21, 0 + .dw 0x0c53, 0xc437, 0x0c7f, 0xc437, 0x21, 0 + .dw 0x0c81, 0xc437, 0x0c81, 0xc437, 0x21, 0 + .dw 0x0c83, 0xc437, 0x0c8f, 0xc437, 0x21, 0 + .dw 0x0c91, 0xc437, 0x0c91, 0xc437, 0x21, 0 + .dw 0x0c93, 0xc437, 0x0cbf, 0xc437, 0x21, 0 + .dw 0x0cc1, 0xc437, 0x0cc1, 0xc437, 0x21, 0 + .dw 0x0cc3, 0xc437, 0x0ccf, 0xc437, 0x21, 0 + .dw 0x0cd1, 0xc437, 0x0cd1, 0xc437, 0x21, 0 + .dw 0x0cd3, 0xc437, 0x0cff, 0xc437, 0x21, 0 + .dw 0x0d01, 0xc437, 0x0d01, 0xc437, 0x21, 0 + .dw 0x0d03, 0xc437, 0x0d0f, 0xc437, 0x21, 0 + .dw 0x0d11, 0xc437, 0x0d11, 0xc437, 0x21, 0 + .dw 0x0d13, 0xc437, 0x0d3f, 0xc437, 0x21, 0 + .dw 0x0d41, 0xc437, 0x0d41, 0xc437, 0x21, 0 + .dw 0x0d43, 0xc437, 0x0d4f, 0xc437, 0x21, 0 + .dw 0x0d51, 0xc437, 0x0d51, 0xc437, 0x21, 0 + .dw 0x0d53, 0xc437, 0x0d7f, 0xc437, 0x21, 0 + .dw 0x0d81, 0xc437, 0x0d81, 0xc437, 0x21, 0 + .dw 0x0d83, 0xc437, 0x0d8f, 0xc437, 0x21, 0 + .dw 0x0d91, 0xc437, 0x0d91, 0xc437, 0x21, 0 + .dw 0x0d93, 0xc437, 0x0dbf, 0xc437, 0x21, 0 + .dw 0x0dc1, 0xc437, 0x0dc1, 0xc437, 0x21, 0 + .dw 0x0dc3, 0xc437, 0x0dcf, 0xc437, 0x21, 0 + .dw 0x0dd1, 0xc437, 0x0dd1, 0xc437, 0x21, 0 + .dw 0x0dd3, 0xc437, 0x0dff, 0xc437, 0x21, 0 + .dw 0x0e01, 0xc437, 0x0e01, 0xc437, 0x21, 0 + .dw 0x0e03, 0xc437, 0x0e0f, 0xc437, 0x21, 0 + .dw 0x0e11, 0xc437, 0x0e11, 0xc437, 0x21, 0 + .dw 0x0e13, 0xc437, 0x0e3f, 0xc437, 0x21, 0 + .dw 0x0e41, 0xc437, 0x0e41, 0xc437, 0x21, 0 + .dw 0x0e43, 0xc437, 0x0e4f, 0xc437, 0x21, 0 + .dw 0x0e51, 0xc437, 0x0e51, 0xc437, 0x21, 0 + .dw 0x0e53, 0xc437, 0x0e7f, 0xc437, 0x21, 0 + .dw 0x0e81, 0xc437, 0x0e81, 0xc437, 0x21, 0 + .dw 0x0e83, 0xc437, 0x0e8f, 0xc437, 0x21, 0 + .dw 0x0e91, 0xc437, 0x0e91, 0xc437, 0x21, 0 + .dw 0x0e93, 0xc437, 0x0ebf, 0xc437, 0x21, 0 + .dw 0x0ec1, 0xc437, 0x0ec1, 0xc437, 0x21, 0 + .dw 0x0ec3, 0xc437, 0x0ecf, 0xc437, 0x21, 0 + .dw 0x0ed1, 0xc437, 0x0ed1, 0xc437, 0x21, 0 + .dw 0x0ed3, 0xc437, 0x0eff, 0xc437, 0x21, 0 + .dw 0x0f01, 0xc437, 0x0f01, 0xc437, 0x21, 0 + .dw 0x0f03, 0xc437, 0x0f0f, 0xc437, 0x21, 0 + .dw 0x0f11, 0xc437, 0x0f11, 0xc437, 0x21, 0 + .dw 0x0f13, 0xc437, 0x0f3f, 0xc437, 0x21, 0 + .dw 0x0f41, 0xc437, 0x0f41, 0xc437, 0x21, 0 + .dw 0x0f43, 0xc437, 0x0f4f, 0xc437, 0x21, 0 + .dw 0x0f51, 0xc437, 0x0f51, 0xc437, 0x21, 0 + .dw 0x0f53, 0xc437, 0x0f7f, 0xc437, 0x21, 0 + .dw 0x0f81, 0xc437, 0x0f81, 0xc437, 0x21, 0 + .dw 0x0f83, 0xc437, 0x0f8f, 0xc437, 0x21, 0 + .dw 0x0f91, 0xc437, 0x0f91, 0xc437, 0x21, 0 + .dw 0x0f93, 0xc437, 0x0fbf, 0xc437, 0x21, 0 + .dw 0x0fc1, 0xc437, 0x0fc1, 0xc437, 0x21, 0 + .dw 0x0fc3, 0xc437, 0x0fcf, 0xc437, 0x21, 0 + .dw 0x0fd1, 0xc437, 0x0fd1, 0xc437, 0x21, 0 + .dw 0x0fd3, 0xc437, 0x1fff, 0xc437, 0x21, 0 + .dw 0x2001, 0xc437, 0x2001, 0xc437, 0x21, 0 + .dw 0x2003, 0xc437, 0x200f, 0xc437, 0x21, 0 + .dw 0x2011, 0xc437, 0x2011, 0xc437, 0x21, 0 + .dw 0x2013, 0xc437, 0x203f, 0xc437, 0x21, 0 + .dw 0x2041, 0xc437, 0x2041, 0xc437, 0x21, 0 + .dw 0x2043, 0xc437, 0x204f, 0xc437, 0x21, 0 + .dw 0x2051, 0xc437, 0x2051, 0xc437, 0x21, 0 + .dw 0x2053, 0xc437, 0x207f, 0xc437, 0x21, 0 + .dw 0x2081, 0xc437, 0x2081, 0xc437, 0x21, 0 + .dw 0x2083, 0xc437, 0x208f, 0xc437, 0x21, 0 + .dw 0x2091, 0xc437, 0x2091, 0xc437, 0x21, 0 + .dw 0x2093, 0xc437, 0x20bf, 0xc437, 0x21, 0 + .dw 0x20c1, 0xc437, 0x20c1, 0xc437, 0x21, 0 + .dw 0x20c3, 0xc437, 0x20cf, 0xc437, 0x21, 0 + .dw 0x20d1, 0xc437, 0x20d1, 0xc437, 0x21, 0 + .dw 0x20d3, 0xc437, 0x20ff, 0xc437, 0x21, 0 + .dw 0x2101, 0xc437, 0x2101, 0xc437, 0x21, 0 + .dw 0x2103, 0xc437, 0x210f, 0xc437, 0x21, 0 + .dw 0x2111, 0xc437, 0x2111, 0xc437, 0x21, 0 + .dw 0x2113, 0xc437, 0x213f, 0xc437, 0x21, 0 + .dw 0x2141, 0xc437, 0x2141, 0xc437, 0x21, 0 + .dw 0x2143, 0xc437, 0x214f, 0xc437, 0x21, 0 + .dw 0x2151, 0xc437, 0x2151, 0xc437, 0x21, 0 + .dw 0x2153, 0xc437, 0x217f, 0xc437, 0x21, 0 + .dw 0x2181, 0xc437, 0x2181, 0xc437, 0x21, 0 + .dw 0x2183, 0xc437, 0x218f, 0xc437, 0x21, 0 + .dw 0x2191, 0xc437, 0x2191, 0xc437, 0x21, 0 + .dw 0x2193, 0xc437, 0x21bf, 0xc437, 0x21, 0 + .dw 0x21c1, 0xc437, 0x21c1, 0xc437, 0x21, 0 + .dw 0x21c3, 0xc437, 0x21cf, 0xc437, 0x21, 0 + .dw 0x21d1, 0xc437, 0x21d1, 0xc437, 0x21, 0 + .dw 0x21d3, 0xc437, 0x21ff, 0xc437, 0x21, 0 + .dw 0x2201, 0xc437, 0x2201, 0xc437, 0x21, 0 + .dw 0x2203, 0xc437, 0x220f, 0xc437, 0x21, 0 + .dw 0x2211, 0xc437, 0x2211, 0xc437, 0x21, 0 + .dw 0x2213, 0xc437, 0x223f, 0xc437, 0x21, 0 + .dw 0x2241, 0xc437, 0x2241, 0xc437, 0x21, 0 + .dw 0x2243, 0xc437, 0x224f, 0xc437, 0x21, 0 + .dw 0x2251, 0xc437, 0x2251, 0xc437, 0x21, 0 + .dw 0x2253, 0xc437, 0x227f, 0xc437, 0x21, 0 + .dw 0x2281, 0xc437, 0x2281, 0xc437, 0x21, 0 + .dw 0x2283, 0xc437, 0x228f, 0xc437, 0x21, 0 + .dw 0x2291, 0xc437, 0x2291, 0xc437, 0x21, 0 + .dw 0x2293, 0xc437, 0x22bf, 0xc437, 0x21, 0 + .dw 0x22c1, 0xc437, 0x22c1, 0xc437, 0x21, 0 + .dw 0x22c3, 0xc437, 0x22cf, 0xc437, 0x21, 0 + .dw 0x22d1, 0xc437, 0x22d1, 0xc437, 0x21, 0 + .dw 0x22d3, 0xc437, 0x22ff, 0xc437, 0x21, 0 + .dw 0x2301, 0xc437, 0x2301, 0xc437, 0x21, 0 + .dw 0x2303, 0xc437, 0x230f, 0xc437, 0x21, 0 + .dw 0x2311, 0xc437, 0x2311, 0xc437, 0x21, 0 + .dw 0x2313, 0xc437, 0x233f, 0xc437, 0x21, 0 + .dw 0x2341, 0xc437, 0x2341, 0xc437, 0x21, 0 + .dw 0x2343, 0xc437, 0x234f, 0xc437, 0x21, 0 + .dw 0x2351, 0xc437, 0x2351, 0xc437, 0x21, 0 + .dw 0x2353, 0xc437, 0x237f, 0xc437, 0x21, 0 + .dw 0x2381, 0xc437, 0x2381, 0xc437, 0x21, 0 + .dw 0x2383, 0xc437, 0x238f, 0xc437, 0x21, 0 + .dw 0x2391, 0xc437, 0x2391, 0xc437, 0x21, 0 + .dw 0x2393, 0xc437, 0x23bf, 0xc437, 0x21, 0 + .dw 0x23c1, 0xc437, 0x23c1, 0xc437, 0x21, 0 + .dw 0x23c3, 0xc437, 0x23cf, 0xc437, 0x21, 0 + .dw 0x23d1, 0xc437, 0x23d1, 0xc437, 0x21, 0 + .dw 0x23d3, 0xc437, 0x23ff, 0xc437, 0x21, 0 + .dw 0x2401, 0xc437, 0x2401, 0xc437, 0x21, 0 + .dw 0x2403, 0xc437, 0x240f, 0xc437, 0x21, 0 + .dw 0x2411, 0xc437, 0x2411, 0xc437, 0x21, 0 + .dw 0x2413, 0xc437, 0x243f, 0xc437, 0x21, 0 + .dw 0x2441, 0xc437, 0x2441, 0xc437, 0x21, 0 + .dw 0x2443, 0xc437, 0x244f, 0xc437, 0x21, 0 + .dw 0x2451, 0xc437, 0x2451, 0xc437, 0x21, 0 + .dw 0x2453, 0xc437, 0x247f, 0xc437, 0x21, 0 + .dw 0x2481, 0xc437, 0x2481, 0xc437, 0x21, 0 + .dw 0x2483, 0xc437, 0x248f, 0xc437, 0x21, 0 + .dw 0x2491, 0xc437, 0x2491, 0xc437, 0x21, 0 + .dw 0x2493, 0xc437, 0x24bf, 0xc437, 0x21, 0 + .dw 0x24c1, 0xc437, 0x24c1, 0xc437, 0x21, 0 + .dw 0x24c3, 0xc437, 0x24cf, 0xc437, 0x21, 0 + .dw 0x24d1, 0xc437, 0x24d1, 0xc437, 0x21, 0 + .dw 0x24d3, 0xc437, 0x24ff, 0xc437, 0x21, 0 + .dw 0x2501, 0xc437, 0x2501, 0xc437, 0x21, 0 + .dw 0x2503, 0xc437, 0x250f, 0xc437, 0x21, 0 + .dw 0x2511, 0xc437, 0x2511, 0xc437, 0x21, 0 + .dw 0x2513, 0xc437, 0x253f, 0xc437, 0x21, 0 + .dw 0x2541, 0xc437, 0x2541, 0xc437, 0x21, 0 + .dw 0x2543, 0xc437, 0x254f, 0xc437, 0x21, 0 + .dw 0x2551, 0xc437, 0x2551, 0xc437, 0x21, 0 + .dw 0x2553, 0xc437, 0x257f, 0xc437, 0x21, 0 + .dw 0x2581, 0xc437, 0x2581, 0xc437, 0x21, 0 + .dw 0x2583, 0xc437, 0x258f, 0xc437, 0x21, 0 + .dw 0x2591, 0xc437, 0x2591, 0xc437, 0x21, 0 + .dw 0x2593, 0xc437, 0x25bf, 0xc437, 0x21, 0 + .dw 0x25c1, 0xc437, 0x25c1, 0xc437, 0x21, 0 + .dw 0x25c3, 0xc437, 0x25cf, 0xc437, 0x21, 0 + .dw 0x25d1, 0xc437, 0x25d1, 0xc437, 0x21, 0 + .dw 0x25d3, 0xc437, 0x25ff, 0xc437, 0x21, 0 + .dw 0x2601, 0xc437, 0x2601, 0xc437, 0x21, 0 + .dw 0x2603, 0xc437, 0x260f, 0xc437, 0x21, 0 + .dw 0x2611, 0xc437, 0x2611, 0xc437, 0x21, 0 + .dw 0x2613, 0xc437, 0x263f, 0xc437, 0x21, 0 + .dw 0x2641, 0xc437, 0x2641, 0xc437, 0x21, 0 + .dw 0x2643, 0xc437, 0x264f, 0xc437, 0x21, 0 + .dw 0x2651, 0xc437, 0x2651, 0xc437, 0x21, 0 + .dw 0x2653, 0xc437, 0x267f, 0xc437, 0x21, 0 + .dw 0x2681, 0xc437, 0x2681, 0xc437, 0x21, 0 + .dw 0x2683, 0xc437, 0x268f, 0xc437, 0x21, 0 + .dw 0x2691, 0xc437, 0x2691, 0xc437, 0x21, 0 + .dw 0x2693, 0xc437, 0x26bf, 0xc437, 0x21, 0 + .dw 0x26c1, 0xc437, 0x26c1, 0xc437, 0x21, 0 + .dw 0x26c3, 0xc437, 0x26cf, 0xc437, 0x21, 0 + .dw 0x26d1, 0xc437, 0x26d1, 0xc437, 0x21, 0 + .dw 0x26d3, 0xc437, 0x26ff, 0xc437, 0x21, 0 + .dw 0x2701, 0xc437, 0x2701, 0xc437, 0x21, 0 + .dw 0x2703, 0xc437, 0x270f, 0xc437, 0x21, 0 + .dw 0x2711, 0xc437, 0x2711, 0xc437, 0x21, 0 + .dw 0x2713, 0xc437, 0x273f, 0xc437, 0x21, 0 + .dw 0x2741, 0xc437, 0x2741, 0xc437, 0x21, 0 + .dw 0x2743, 0xc437, 0x274f, 0xc437, 0x21, 0 + .dw 0x2751, 0xc437, 0x2751, 0xc437, 0x21, 0 + .dw 0x2753, 0xc437, 0x277f, 0xc437, 0x21, 0 + .dw 0x2781, 0xc437, 0x2781, 0xc437, 0x21, 0 + .dw 0x2783, 0xc437, 0x278f, 0xc437, 0x21, 0 + .dw 0x2791, 0xc437, 0x2791, 0xc437, 0x21, 0 + .dw 0x2793, 0xc437, 0x27bf, 0xc437, 0x21, 0 + .dw 0x27c1, 0xc437, 0x27c1, 0xc437, 0x21, 0 + .dw 0x27c3, 0xc437, 0x27cf, 0xc437, 0x21, 0 + .dw 0x27d1, 0xc437, 0x27d1, 0xc437, 0x21, 0 + .dw 0x27d3, 0xc437, 0x27ff, 0xc437, 0x21, 0 + .dw 0x2801, 0xc437, 0x2801, 0xc437, 0x21, 0 + .dw 0x2803, 0xc437, 0x280f, 0xc437, 0x21, 0 + .dw 0x2811, 0xc437, 0x2811, 0xc437, 0x21, 0 + .dw 0x2813, 0xc437, 0x283f, 0xc437, 0x21, 0 + .dw 0x2841, 0xc437, 0x2841, 0xc437, 0x21, 0 + .dw 0x2843, 0xc437, 0x284f, 0xc437, 0x21, 0 + .dw 0x2851, 0xc437, 0x2851, 0xc437, 0x21, 0 + .dw 0x2853, 0xc437, 0x287f, 0xc437, 0x21, 0 + .dw 0x2881, 0xc437, 0x2881, 0xc437, 0x21, 0 + .dw 0x2883, 0xc437, 0x288f, 0xc437, 0x21, 0 + .dw 0x2891, 0xc437, 0x2891, 0xc437, 0x21, 0 + .dw 0x2893, 0xc437, 0x28bf, 0xc437, 0x21, 0 + .dw 0x28c1, 0xc437, 0x28c1, 0xc437, 0x21, 0 + .dw 0x28c3, 0xc437, 0x28cf, 0xc437, 0x21, 0 + .dw 0x28d1, 0xc437, 0x28d1, 0xc437, 0x21, 0 + .dw 0x28d3, 0xc437, 0x28ff, 0xc437, 0x21, 0 + .dw 0x2901, 0xc437, 0x2901, 0xc437, 0x21, 0 + .dw 0x2903, 0xc437, 0x290f, 0xc437, 0x21, 0 + .dw 0x2911, 0xc437, 0x2911, 0xc437, 0x21, 0 + .dw 0x2913, 0xc437, 0x293f, 0xc437, 0x21, 0 + .dw 0x2941, 0xc437, 0x2941, 0xc437, 0x21, 0 + .dw 0x2943, 0xc437, 0x294f, 0xc437, 0x21, 0 + .dw 0x2951, 0xc437, 0x2951, 0xc437, 0x21, 0 + .dw 0x2953, 0xc437, 0x297f, 0xc437, 0x21, 0 + .dw 0x2981, 0xc437, 0x2981, 0xc437, 0x21, 0 + .dw 0x2983, 0xc437, 0x298f, 0xc437, 0x21, 0 + .dw 0x2991, 0xc437, 0x2991, 0xc437, 0x21, 0 + .dw 0x2993, 0xc437, 0x29bf, 0xc437, 0x21, 0 + .dw 0x29c1, 0xc437, 0x29c1, 0xc437, 0x21, 0 + .dw 0x29c3, 0xc437, 0x29cf, 0xc437, 0x21, 0 + .dw 0x29d1, 0xc437, 0x29d1, 0xc437, 0x21, 0 + .dw 0x29d3, 0xc437, 0x29ff, 0xc437, 0x21, 0 + .dw 0x2a01, 0xc437, 0x2a01, 0xc437, 0x21, 0 + .dw 0x2a03, 0xc437, 0x2a0f, 0xc437, 0x21, 0 + .dw 0x2a11, 0xc437, 0x2a11, 0xc437, 0x21, 0 + .dw 0x2a13, 0xc437, 0x2a3f, 0xc437, 0x21, 0 + .dw 0x2a41, 0xc437, 0x2a41, 0xc437, 0x21, 0 + .dw 0x2a43, 0xc437, 0x2a4f, 0xc437, 0x21, 0 + .dw 0x2a51, 0xc437, 0x2a51, 0xc437, 0x21, 0 + .dw 0x2a53, 0xc437, 0x2a7f, 0xc437, 0x21, 0 + .dw 0x2a81, 0xc437, 0x2a81, 0xc437, 0x21, 0 + .dw 0x2a83, 0xc437, 0x2a8f, 0xc437, 0x21, 0 + .dw 0x2a91, 0xc437, 0x2a91, 0xc437, 0x21, 0 + .dw 0x2a93, 0xc437, 0x2abf, 0xc437, 0x21, 0 + .dw 0x2ac1, 0xc437, 0x2ac1, 0xc437, 0x21, 0 + .dw 0x2ac3, 0xc437, 0x2acf, 0xc437, 0x21, 0 + .dw 0x2ad1, 0xc437, 0x2ad1, 0xc437, 0x21, 0 + .dw 0x2ad3, 0xc437, 0x2aff, 0xc437, 0x21, 0 + .dw 0x2b01, 0xc437, 0x2b01, 0xc437, 0x21, 0 + .dw 0x2b03, 0xc437, 0x2b0f, 0xc437, 0x21, 0 + .dw 0x2b11, 0xc437, 0x2b11, 0xc437, 0x21, 0 + .dw 0x2b13, 0xc437, 0x2b3f, 0xc437, 0x21, 0 + .dw 0x2b41, 0xc437, 0x2b41, 0xc437, 0x21, 0 + .dw 0x2b43, 0xc437, 0x2b4f, 0xc437, 0x21, 0 + .dw 0x2b51, 0xc437, 0x2b51, 0xc437, 0x21, 0 + .dw 0x2b53, 0xc437, 0x2b7f, 0xc437, 0x21, 0 + .dw 0x2b81, 0xc437, 0x2b81, 0xc437, 0x21, 0 + .dw 0x2b83, 0xc437, 0x2b8f, 0xc437, 0x21, 0 + .dw 0x2b91, 0xc437, 0x2b91, 0xc437, 0x21, 0 + .dw 0x2b93, 0xc437, 0x2bbf, 0xc437, 0x21, 0 + .dw 0x2bc1, 0xc437, 0x2bc1, 0xc437, 0x21, 0 + .dw 0x2bc3, 0xc437, 0x2bcf, 0xc437, 0x21, 0 + .dw 0x2bd1, 0xc437, 0x2bd1, 0xc437, 0x21, 0 + .dw 0x2bd3, 0xc437, 0x2bff, 0xc437, 0x21, 0 + .dw 0x2c01, 0xc437, 0x2c01, 0xc437, 0x21, 0 + .dw 0x2c03, 0xc437, 0x2c0f, 0xc437, 0x21, 0 + .dw 0x2c11, 0xc437, 0x2c11, 0xc437, 0x21, 0 + .dw 0x2c13, 0xc437, 0x2c3f, 0xc437, 0x21, 0 + .dw 0x2c41, 0xc437, 0x2c41, 0xc437, 0x21, 0 + .dw 0x2c43, 0xc437, 0x2c4f, 0xc437, 0x21, 0 + .dw 0x2c51, 0xc437, 0x2c51, 0xc437, 0x21, 0 + .dw 0x2c53, 0xc437, 0x2c7f, 0xc437, 0x21, 0 + .dw 0x2c81, 0xc437, 0x2c81, 0xc437, 0x21, 0 + .dw 0x2c83, 0xc437, 0x2c8f, 0xc437, 0x21, 0 + .dw 0x2c91, 0xc437, 0x2c91, 0xc437, 0x21, 0 + .dw 0x2c93, 0xc437, 0x2cbf, 0xc437, 0x21, 0 + .dw 0x2cc1, 0xc437, 0x2cc1, 0xc437, 0x21, 0 + .dw 0x2cc3, 0xc437, 0x2ccf, 0xc437, 0x21, 0 + .dw 0x2cd1, 0xc437, 0x2cd1, 0xc437, 0x21, 0 + .dw 0x2cd3, 0xc437, 0x2cff, 0xc437, 0x21, 0 + .dw 0x2d01, 0xc437, 0x2d01, 0xc437, 0x21, 0 + .dw 0x2d03, 0xc437, 0x2d0f, 0xc437, 0x21, 0 + .dw 0x2d11, 0xc437, 0x2d11, 0xc437, 0x21, 0 + .dw 0x2d13, 0xc437, 0x2d3f, 0xc437, 0x21, 0 + .dw 0x2d41, 0xc437, 0x2d41, 0xc437, 0x21, 0 + .dw 0x2d43, 0xc437, 0x2d4f, 0xc437, 0x21, 0 + .dw 0x2d51, 0xc437, 0x2d51, 0xc437, 0x21, 0 + .dw 0x2d53, 0xc437, 0x2d7f, 0xc437, 0x21, 0 + .dw 0x2d81, 0xc437, 0x2d81, 0xc437, 0x21, 0 + .dw 0x2d83, 0xc437, 0x2d8f, 0xc437, 0x21, 0 + .dw 0x2d91, 0xc437, 0x2d91, 0xc437, 0x21, 0 + .dw 0x2d93, 0xc437, 0x2dbf, 0xc437, 0x21, 0 + .dw 0x2dc1, 0xc437, 0x2dc1, 0xc437, 0x21, 0 + .dw 0x2dc3, 0xc437, 0x2dcf, 0xc437, 0x21, 0 + .dw 0x2dd1, 0xc437, 0x2dd1, 0xc437, 0x21, 0 + .dw 0x2dd3, 0xc437, 0x2dff, 0xc437, 0x21, 0 + .dw 0x2e01, 0xc437, 0x2e01, 0xc437, 0x21, 0 + .dw 0x2e03, 0xc437, 0x2e0f, 0xc437, 0x21, 0 + .dw 0x2e11, 0xc437, 0x2e11, 0xc437, 0x21, 0 + .dw 0x2e13, 0xc437, 0x2e3f, 0xc437, 0x21, 0 + .dw 0x2e41, 0xc437, 0x2e41, 0xc437, 0x21, 0 + .dw 0x2e43, 0xc437, 0x2e4f, 0xc437, 0x21, 0 + .dw 0x2e51, 0xc437, 0x2e51, 0xc437, 0x21, 0 + .dw 0x2e53, 0xc437, 0x2e7f, 0xc437, 0x21, 0 + .dw 0x2e81, 0xc437, 0x2e81, 0xc437, 0x21, 0 + .dw 0x2e83, 0xc437, 0x2e8f, 0xc437, 0x21, 0 + .dw 0x2e91, 0xc437, 0x2e91, 0xc437, 0x21, 0 + .dw 0x2e93, 0xc437, 0x2ebf, 0xc437, 0x21, 0 + .dw 0x2ec1, 0xc437, 0x2ec1, 0xc437, 0x21, 0 + .dw 0x2ec3, 0xc437, 0x2ecf, 0xc437, 0x21, 0 + .dw 0x2ed1, 0xc437, 0x2ed1, 0xc437, 0x21, 0 + .dw 0x2ed3, 0xc437, 0x2eff, 0xc437, 0x21, 0 + .dw 0x2f01, 0xc437, 0x2f01, 0xc437, 0x21, 0 + .dw 0x2f03, 0xc437, 0x2f0f, 0xc437, 0x21, 0 + .dw 0x2f11, 0xc437, 0x2f11, 0xc437, 0x21, 0 + .dw 0x2f13, 0xc437, 0x2f3f, 0xc437, 0x21, 0 + .dw 0x2f41, 0xc437, 0x2f41, 0xc437, 0x21, 0 + .dw 0x2f43, 0xc437, 0x2f4f, 0xc437, 0x21, 0 + .dw 0x2f51, 0xc437, 0x2f51, 0xc437, 0x21, 0 + .dw 0x2f53, 0xc437, 0x2f7f, 0xc437, 0x21, 0 + .dw 0x2f81, 0xc437, 0x2f81, 0xc437, 0x21, 0 + .dw 0x2f83, 0xc437, 0x2f8f, 0xc437, 0x21, 0 + .dw 0x2f91, 0xc437, 0x2f91, 0xc437, 0x21, 0 + .dw 0x2f93, 0xc437, 0x2fbf, 0xc437, 0x21, 0 + .dw 0x2fc1, 0xc437, 0x2fc1, 0xc437, 0x21, 0 + .dw 0x2fc3, 0xc437, 0x2fcf, 0xc437, 0x21, 0 + .dw 0x2fd1, 0xc437, 0x2fd1, 0xc437, 0x21, 0 + .dw 0x2fd3, 0xc437, 0xffff, 0xc5ff, 0x21, 0 + .dw 0x0040, 0xc600, 0x01ff, 0xc600, 0x21, 0 + .dw 0x0240, 0xc600, 0x03ff, 0xc600, 0x21, 0 + .dw 0x0440, 0xc600, 0x05ff, 0xc600, 0x21, 0 + .dw 0x0640, 0xc600, 0x07ff, 0xc600, 0x21, 0 + .dw 0x0840, 0xc600, 0x09ff, 0xc600, 0x21, 0 + .dw 0x0a40, 0xc600, 0x0bff, 0xc600, 0x21, 0 + .dw 0x0c40, 0xc600, 0x0dff, 0xc600, 0x21, 0 + .dw 0x0e40, 0xc600, 0x0fff, 0xc600, 0x21, 0 + .dw 0x1040, 0xc600, 0x11ff, 0xc600, 0x21, 0 + .dw 0x1240, 0xc600, 0x13ff, 0xc600, 0x21, 0 + .dw 0x1440, 0xc600, 0x15ff, 0xc600, 0x21, 0 + .dw 0x1640, 0xc600, 0x17ff, 0xc600, 0x21, 0 + .dw 0x1840, 0xc600, 0x19ff, 0xc600, 0x21, 0 + .dw 0x1a40, 0xc600, 0x1bff, 0xc600, 0x21, 0 + .dw 0x1c40, 0xc600, 0x1dff, 0xc600, 0x21, 0 + .dw 0x1e40, 0xc600, 0x1fff, 0xc600, 0x21, 0 + .dw 0x2040, 0xc600, 0x21ff, 0xc600, 0x21, 0 + .dw 0x2240, 0xc600, 0x23ff, 0xc600, 0x21, 0 + .dw 0x2440, 0xc600, 0x25ff, 0xc600, 0x21, 0 + .dw 0x2640, 0xc600, 0x27ff, 0xc600, 0x21, 0 + .dw 0x2840, 0xc600, 0x29ff, 0xc600, 0x21, 0 + .dw 0x2a40, 0xc600, 0x2bff, 0xc600, 0x21, 0 + .dw 0x2c40, 0xc600, 0x2dff, 0xc600, 0x21, 0 + .dw 0x2e40, 0xc600, 0x2fff, 0xc600, 0x21, 0 + .dw 0x3040, 0xc600, 0x31ff, 0xc600, 0x21, 0 + .dw 0x3240, 0xc600, 0x33ff, 0xc600, 0x21, 0 + .dw 0x3440, 0xc600, 0x35ff, 0xc600, 0x21, 0 + .dw 0x3640, 0xc600, 0x37ff, 0xc600, 0x21, 0 + .dw 0x3840, 0xc600, 0x39ff, 0xc600, 0x21, 0 + .dw 0x3a40, 0xc600, 0x3bff, 0xc600, 0x21, 0 + .dw 0x3c40, 0xc600, 0x3dff, 0xc600, 0x21, 0 + .dw 0x3e40, 0xc600, 0x3fff, 0xc600, 0x21, 0 + .dw 0x4040, 0xc600, 0x41ff, 0xc600, 0x21, 0 + .dw 0x4240, 0xc600, 0x43ff, 0xc600, 0x21, 0 + .dw 0x4440, 0xc600, 0x45ff, 0xc600, 0x21, 0 + .dw 0x4640, 0xc600, 0x47ff, 0xc600, 0x21, 0 + .dw 0x4840, 0xc600, 0x49ff, 0xc600, 0x21, 0 + .dw 0x4a40, 0xc600, 0x4bff, 0xc600, 0x21, 0 + .dw 0x4c40, 0xc600, 0x4dff, 0xc600, 0x21, 0 + .dw 0x4e40, 0xc600, 0x4fff, 0xc600, 0x21, 0 + .dw 0x5040, 0xc600, 0x51ff, 0xc600, 0x21, 0 + .dw 0x5240, 0xc600, 0x53ff, 0xc600, 0x21, 0 + .dw 0x5440, 0xc600, 0x55ff, 0xc600, 0x21, 0 + .dw 0x5640, 0xc600, 0x57ff, 0xc600, 0x21, 0 + .dw 0x5840, 0xc600, 0x59ff, 0xc600, 0x21, 0 + .dw 0x5a40, 0xc600, 0x5bff, 0xc600, 0x21, 0 + .dw 0x5c40, 0xc600, 0x5dff, 0xc600, 0x21, 0 + .dw 0x5e40, 0xc600, 0x5fff, 0xc600, 0x21, 0 + .dw 0x6040, 0xc600, 0x61ff, 0xc600, 0x21, 0 + .dw 0x6240, 0xc600, 0x63ff, 0xc600, 0x21, 0 + .dw 0x6440, 0xc600, 0x65ff, 0xc600, 0x21, 0 + .dw 0x6640, 0xc600, 0x67ff, 0xc600, 0x21, 0 + .dw 0x6840, 0xc600, 0x69ff, 0xc600, 0x21, 0 + .dw 0x6a40, 0xc600, 0x6bff, 0xc600, 0x21, 0 + .dw 0x6c40, 0xc600, 0x6dff, 0xc600, 0x21, 0 + .dw 0x6e40, 0xc600, 0x6fff, 0xc600, 0x21, 0 + .dw 0x7040, 0xc600, 0x71ff, 0xc600, 0x21, 0 + .dw 0x7240, 0xc600, 0x73ff, 0xc600, 0x21, 0 + .dw 0x7440, 0xc600, 0x75ff, 0xc600, 0x21, 0 + .dw 0x7640, 0xc600, 0x77ff, 0xc600, 0x21, 0 + .dw 0x7840, 0xc600, 0x79ff, 0xc600, 0x21, 0 + .dw 0x7a40, 0xc600, 0x7bff, 0xc600, 0x21, 0 + .dw 0x7c40, 0xc600, 0x7dff, 0xc600, 0x21, 0 + .dw 0x7e40, 0xc600, 0x7fff, 0xc600, 0x21, 0 + .dw 0x8040, 0xc600, 0x81ff, 0xc600, 0x21, 0 + .dw 0x8240, 0xc600, 0x83ff, 0xc600, 0x21, 0 + .dw 0x8440, 0xc600, 0x85ff, 0xc600, 0x21, 0 + .dw 0x8640, 0xc600, 0x87ff, 0xc600, 0x21, 0 + .dw 0x8840, 0xc600, 0x89ff, 0xc600, 0x21, 0 + .dw 0x8a40, 0xc600, 0x8bff, 0xc600, 0x21, 0 + .dw 0x8c40, 0xc600, 0x8dff, 0xc600, 0x21, 0 + .dw 0x8e40, 0xc600, 0x8fff, 0xc600, 0x21, 0 + .dw 0x9040, 0xc600, 0x91ff, 0xc600, 0x21, 0 + .dw 0x9240, 0xc600, 0x93ff, 0xc600, 0x21, 0 + .dw 0x9440, 0xc600, 0x95ff, 0xc600, 0x21, 0 + .dw 0x9640, 0xc600, 0x97ff, 0xc600, 0x21, 0 + .dw 0x9840, 0xc600, 0x99ff, 0xc600, 0x21, 0 + .dw 0x9a40, 0xc600, 0x9bff, 0xc600, 0x21, 0 + .dw 0x9c40, 0xc600, 0x9dff, 0xc600, 0x21, 0 + .dw 0x9e40, 0xc600, 0x9fff, 0xc600, 0x21, 0 + .dw 0xa040, 0xc600, 0xa1ff, 0xc600, 0x21, 0 + .dw 0xa240, 0xc600, 0xa3ff, 0xc600, 0x21, 0 + .dw 0xa440, 0xc600, 0xa5ff, 0xc600, 0x21, 0 + .dw 0xa640, 0xc600, 0xa7ff, 0xc600, 0x21, 0 + .dw 0xa840, 0xc600, 0xa9ff, 0xc600, 0x21, 0 + .dw 0xaa40, 0xc600, 0xabff, 0xc600, 0x21, 0 + .dw 0xac40, 0xc600, 0xadff, 0xc600, 0x21, 0 + .dw 0xae40, 0xc600, 0xafff, 0xc600, 0x21, 0 + .dw 0xb040, 0xc600, 0xb1ff, 0xc600, 0x21, 0 + .dw 0xb240, 0xc600, 0xb3ff, 0xc600, 0x21, 0 + .dw 0xb440, 0xc600, 0xb5ff, 0xc600, 0x21, 0 + .dw 0xb640, 0xc600, 0xb7ff, 0xc600, 0x21, 0 + .dw 0xb840, 0xc600, 0xb9ff, 0xc600, 0x21, 0 + .dw 0xba40, 0xc600, 0xbbff, 0xc600, 0x21, 0 + .dw 0xbc40, 0xc600, 0xbdff, 0xc600, 0x21, 0 + .dw 0xbe40, 0xc600, 0xffff, 0xc600, 0x21, 0 + .dw 0x0040, 0xc601, 0x01ff, 0xc601, 0x21, 0 + .dw 0x0240, 0xc601, 0x03ff, 0xc601, 0x21, 0 + .dw 0x0440, 0xc601, 0x05ff, 0xc601, 0x21, 0 + .dw 0x0640, 0xc601, 0x07ff, 0xc601, 0x21, 0 + .dw 0x0840, 0xc601, 0x09ff, 0xc601, 0x21, 0 + .dw 0x0a40, 0xc601, 0x0bff, 0xc601, 0x21, 0 + .dw 0x0c40, 0xc601, 0x0dff, 0xc601, 0x21, 0 + .dw 0x0e40, 0xc601, 0x3fff, 0xc601, 0x21, 0 + .dw 0x4040, 0xc601, 0x41ff, 0xc601, 0x21, 0 + .dw 0x4240, 0xc601, 0x43ff, 0xc601, 0x21, 0 + .dw 0x4440, 0xc601, 0x45ff, 0xc601, 0x21, 0 + .dw 0x4640, 0xc601, 0x47ff, 0xc601, 0x21, 0 + .dw 0x4840, 0xc601, 0x49ff, 0xc601, 0x21, 0 + .dw 0x4a40, 0xc601, 0x4bff, 0xc601, 0x21, 0 + .dw 0x4c40, 0xc601, 0x4dff, 0xc601, 0x21, 0 + .dw 0x4e40, 0xc601, 0x7fff, 0xc601, 0x21, 0 + .dw 0x8040, 0xc601, 0x81ff, 0xc601, 0x21, 0 + .dw 0x8240, 0xc601, 0x83ff, 0xc601, 0x21, 0 + .dw 0x8440, 0xc601, 0x85ff, 0xc601, 0x21, 0 + .dw 0x8640, 0xc601, 0x87ff, 0xc601, 0x21, 0 + .dw 0x8840, 0xc601, 0x89ff, 0xc601, 0x21, 0 + .dw 0x8a40, 0xc601, 0x8bff, 0xc601, 0x21, 0 + .dw 0x8c40, 0xc601, 0x8dff, 0xc601, 0x21, 0 + .dw 0x8e40, 0xc601, 0xffff, 0xc601, 0x21, 0 + .dw 0x0040, 0xc602, 0x01ff, 0xc602, 0x21, 0 + .dw 0x0240, 0xc602, 0x03ff, 0xc602, 0x21, 0 + .dw 0x0440, 0xc602, 0x05ff, 0xc602, 0x21, 0 + .dw 0x0640, 0xc602, 0x07ff, 0xc602, 0x21, 0 + .dw 0x0840, 0xc602, 0x09ff, 0xc602, 0x21, 0 + .dw 0x0a40, 0xc602, 0x0bff, 0xc602, 0x21, 0 + .dw 0x0c40, 0xc602, 0x0dff, 0xc602, 0x21, 0 + .dw 0x0e40, 0xc602, 0x3fff, 0xc602, 0x21, 0 + .dw 0x4040, 0xc602, 0x41ff, 0xc602, 0x21, 0 + .dw 0x4240, 0xc602, 0x43ff, 0xc602, 0x21, 0 + .dw 0x4440, 0xc602, 0x45ff, 0xc602, 0x21, 0 + .dw 0x4640, 0xc602, 0x47ff, 0xc602, 0x21, 0 + .dw 0x4840, 0xc602, 0x49ff, 0xc602, 0x21, 0 + .dw 0x4a40, 0xc602, 0x4bff, 0xc602, 0x21, 0 + .dw 0x4c40, 0xc602, 0x4dff, 0xc602, 0x21, 0 + .dw 0x4e40, 0xc602, 0x7fff, 0xc602, 0x21, 0 + .dw 0x8040, 0xc602, 0x81ff, 0xc602, 0x21, 0 + .dw 0x8240, 0xc602, 0x83ff, 0xc602, 0x21, 0 + .dw 0x8440, 0xc602, 0x85ff, 0xc602, 0x21, 0 + .dw 0x8640, 0xc602, 0x87ff, 0xc602, 0x21, 0 + .dw 0x8840, 0xc602, 0x89ff, 0xc602, 0x21, 0 + .dw 0x8a40, 0xc602, 0x8bff, 0xc602, 0x21, 0 + .dw 0x8c40, 0xc602, 0x8dff, 0xc602, 0x21, 0 + .dw 0x8e40, 0xc602, 0xbfff, 0xc602, 0x21, 0 + .dw 0xc040, 0xc602, 0xc1ff, 0xc602, 0x21, 0 + .dw 0xc240, 0xc602, 0xc3ff, 0xc602, 0x21, 0 + .dw 0xc440, 0xc602, 0xc5ff, 0xc602, 0x21, 0 + .dw 0xc640, 0xc602, 0xc7ff, 0xc602, 0x21, 0 + .dw 0xc840, 0xc602, 0xc9ff, 0xc602, 0x21, 0 + .dw 0xca40, 0xc602, 0xcbff, 0xc602, 0x21, 0 + .dw 0xcc40, 0xc602, 0xcdff, 0xc602, 0x21, 0 + .dw 0xce40, 0xc602, 0xffff, 0xc602, 0x21, 0 + .dw 0x0040, 0xc603, 0x01ff, 0xc603, 0x21, 0 + .dw 0x0240, 0xc603, 0x03ff, 0xc603, 0x21, 0 + .dw 0x0440, 0xc603, 0x05ff, 0xc603, 0x21, 0 + .dw 0x0640, 0xc603, 0x07ff, 0xc603, 0x21, 0 + .dw 0x0840, 0xc603, 0x09ff, 0xc603, 0x21, 0 + .dw 0x0a40, 0xc603, 0x0bff, 0xc603, 0x21, 0 + .dw 0x0c40, 0xc603, 0x0dff, 0xc603, 0x21, 0 + .dw 0x0e40, 0xc603, 0x0fff, 0xc603, 0x21, 0 + .dw 0x1040, 0xc603, 0x11ff, 0xc603, 0x21, 0 + .dw 0x1240, 0xc603, 0x13ff, 0xc603, 0x21, 0 + .dw 0x1440, 0xc603, 0x15ff, 0xc603, 0x21, 0 + .dw 0x1640, 0xc603, 0x17ff, 0xc603, 0x21, 0 + .dw 0x1840, 0xc603, 0x19ff, 0xc603, 0x21, 0 + .dw 0x1a40, 0xc603, 0x1bff, 0xc603, 0x21, 0 + .dw 0x1c40, 0xc603, 0x1dff, 0xc603, 0x21, 0 + .dw 0x1e40, 0xc603, 0x3fff, 0xc603, 0x21, 0 + .dw 0x4040, 0xc603, 0x41ff, 0xc603, 0x21, 0 + .dw 0x4240, 0xc603, 0x43ff, 0xc603, 0x21, 0 + .dw 0x4440, 0xc603, 0x45ff, 0xc603, 0x21, 0 + .dw 0x4640, 0xc603, 0x47ff, 0xc603, 0x21, 0 + .dw 0x4840, 0xc603, 0x49ff, 0xc603, 0x21, 0 + .dw 0x4a40, 0xc603, 0x4bff, 0xc603, 0x21, 0 + .dw 0x4c40, 0xc603, 0x4dff, 0xc603, 0x21, 0 + .dw 0x4e40, 0xc603, 0x4fff, 0xc603, 0x21, 0 + .dw 0x5040, 0xc603, 0x51ff, 0xc603, 0x21, 0 + .dw 0x5240, 0xc603, 0x53ff, 0xc603, 0x21, 0 + .dw 0x5440, 0xc603, 0x55ff, 0xc603, 0x21, 0 + .dw 0x5640, 0xc603, 0x57ff, 0xc603, 0x21, 0 + .dw 0x5840, 0xc603, 0x59ff, 0xc603, 0x21, 0 + .dw 0x5a40, 0xc603, 0x5bff, 0xc603, 0x21, 0 + .dw 0x5c40, 0xc603, 0x5dff, 0xc603, 0x21, 0 + .dw 0x5e40, 0xc603, 0x7fff, 0xc603, 0x21, 0 + .dw 0x8040, 0xc603, 0x81ff, 0xc603, 0x21, 0 + .dw 0x8240, 0xc603, 0x83ff, 0xc603, 0x21, 0 + .dw 0x8440, 0xc603, 0x85ff, 0xc603, 0x21, 0 + .dw 0x8640, 0xc603, 0x87ff, 0xc603, 0x21, 0 + .dw 0x8840, 0xc603, 0x89ff, 0xc603, 0x21, 0 + .dw 0x8a40, 0xc603, 0x8bff, 0xc603, 0x21, 0 + .dw 0x8c40, 0xc603, 0x8dff, 0xc603, 0x21, 0 + .dw 0x8e40, 0xc603, 0x8fff, 0xc603, 0x21, 0 + .dw 0x9040, 0xc603, 0x91ff, 0xc603, 0x21, 0 + .dw 0x9240, 0xc603, 0x93ff, 0xc603, 0x21, 0 + .dw 0x9440, 0xc603, 0x95ff, 0xc603, 0x21, 0 + .dw 0x9640, 0xc603, 0x97ff, 0xc603, 0x21, 0 + .dw 0x9840, 0xc603, 0x99ff, 0xc603, 0x21, 0 + .dw 0x9a40, 0xc603, 0x9bff, 0xc603, 0x21, 0 + .dw 0x9c40, 0xc603, 0x9dff, 0xc603, 0x21, 0 + .dw 0x9e40, 0xc603, 0xffff, 0xc603, 0x21, 0 + .dw 0x0040, 0xc604, 0x01ff, 0xc604, 0x21, 0 + .dw 0x0240, 0xc604, 0x03ff, 0xc604, 0x21, 0 + .dw 0x0440, 0xc604, 0x05ff, 0xc604, 0x21, 0 + .dw 0x0640, 0xc604, 0x07ff, 0xc604, 0x21, 0 + .dw 0x0840, 0xc604, 0x09ff, 0xc604, 0x21, 0 + .dw 0x0a40, 0xc604, 0x0bff, 0xc604, 0x21, 0 + .dw 0x0c40, 0xc604, 0x0dff, 0xc604, 0x21, 0 + .dw 0x0e40, 0xc604, 0x3fff, 0xc604, 0x21, 0 + .dw 0x4040, 0xc604, 0x41ff, 0xc604, 0x21, 0 + .dw 0x4240, 0xc604, 0x43ff, 0xc604, 0x21, 0 + .dw 0x4440, 0xc604, 0x45ff, 0xc604, 0x21, 0 + .dw 0x4640, 0xc604, 0x47ff, 0xc604, 0x21, 0 + .dw 0x4840, 0xc604, 0x49ff, 0xc604, 0x21, 0 + .dw 0x4a40, 0xc604, 0x4bff, 0xc604, 0x21, 0 + .dw 0x4c40, 0xc604, 0x4dff, 0xc604, 0x21, 0 + .dw 0x4e40, 0xc604, 0x7fff, 0xc604, 0x21, 0 + .dw 0x8040, 0xc604, 0x81ff, 0xc604, 0x21, 0 + .dw 0x8240, 0xc604, 0x83ff, 0xc604, 0x21, 0 + .dw 0x8440, 0xc604, 0x85ff, 0xc604, 0x21, 0 + .dw 0x8640, 0xc604, 0x87ff, 0xc604, 0x21, 0 + .dw 0x8840, 0xc604, 0x89ff, 0xc604, 0x21, 0 + .dw 0x8a40, 0xc604, 0x8bff, 0xc604, 0x21, 0 + .dw 0x8c40, 0xc604, 0x8dff, 0xc604, 0x21, 0 + .dw 0x8e40, 0xc604, 0xbfff, 0xc604, 0x21, 0 + .dw 0xc040, 0xc604, 0xc1ff, 0xc604, 0x21, 0 + .dw 0xc240, 0xc604, 0xc3ff, 0xc604, 0x21, 0 + .dw 0xc440, 0xc604, 0xc5ff, 0xc604, 0x21, 0 + .dw 0xc640, 0xc604, 0xc7ff, 0xc604, 0x21, 0 + .dw 0xc840, 0xc604, 0xc9ff, 0xc604, 0x21, 0 + .dw 0xca40, 0xc604, 0xcbff, 0xc604, 0x21, 0 + .dw 0xcc40, 0xc604, 0xcdff, 0xc604, 0x21, 0 + .dw 0xce40, 0xc604, 0xffff, 0xc604, 0x21, 0 + .dw 0x0040, 0xc605, 0x01ff, 0xc605, 0x21, 0 + .dw 0x0240, 0xc605, 0x03ff, 0xc605, 0x21, 0 + .dw 0x0440, 0xc605, 0x05ff, 0xc605, 0x21, 0 + .dw 0x0640, 0xc605, 0x07ff, 0xc605, 0x21, 0 + .dw 0x0840, 0xc605, 0x09ff, 0xc605, 0x21, 0 + .dw 0x0a40, 0xc605, 0x0bff, 0xc605, 0x21, 0 + .dw 0x0c40, 0xc605, 0x0dff, 0xc605, 0x21, 0 + .dw 0x0e40, 0xc605, 0x3fff, 0xc605, 0x21, 0 + .dw 0x4040, 0xc605, 0x41ff, 0xc605, 0x21, 0 + .dw 0x4240, 0xc605, 0x43ff, 0xc605, 0x21, 0 + .dw 0x4440, 0xc605, 0x45ff, 0xc605, 0x21, 0 + .dw 0x4640, 0xc605, 0x47ff, 0xc605, 0x21, 0 + .dw 0x4840, 0xc605, 0x49ff, 0xc605, 0x21, 0 + .dw 0x4a40, 0xc605, 0x4bff, 0xc605, 0x21, 0 + .dw 0x4c40, 0xc605, 0x4dff, 0xc605, 0x21, 0 + .dw 0x4e40, 0xc605, 0x7fff, 0xc605, 0x21, 0 + .dw 0x8040, 0xc605, 0x81ff, 0xc605, 0x21, 0 + .dw 0x8240, 0xc605, 0x83ff, 0xc605, 0x21, 0 + .dw 0x8440, 0xc605, 0x85ff, 0xc605, 0x21, 0 + .dw 0x8640, 0xc605, 0x87ff, 0xc605, 0x21, 0 + .dw 0x8840, 0xc605, 0x89ff, 0xc605, 0x21, 0 + .dw 0x8a40, 0xc605, 0x8bff, 0xc605, 0x21, 0 + .dw 0x8c40, 0xc605, 0x8dff, 0xc605, 0x21, 0 + .dw 0x8e40, 0xc605, 0xffff, 0xc605, 0x21, 0 + .dw 0x0040, 0xc606, 0x01ff, 0xc606, 0x21, 0 + .dw 0x0240, 0xc606, 0x03ff, 0xc606, 0x21, 0 + .dw 0x0440, 0xc606, 0x05ff, 0xc606, 0x21, 0 + .dw 0x0640, 0xc606, 0x07ff, 0xc606, 0x21, 0 + .dw 0x0840, 0xc606, 0x09ff, 0xc606, 0x21, 0 + .dw 0x0a40, 0xc606, 0x0bff, 0xc606, 0x21, 0 + .dw 0x0c40, 0xc606, 0x0dff, 0xc606, 0x21, 0 + .dw 0x0e40, 0xc606, 0x3fff, 0xc606, 0x21, 0 + .dw 0x4040, 0xc606, 0x41ff, 0xc606, 0x21, 0 + .dw 0x4240, 0xc606, 0x43ff, 0xc606, 0x21, 0 + .dw 0x4440, 0xc606, 0x45ff, 0xc606, 0x21, 0 + .dw 0x4640, 0xc606, 0x47ff, 0xc606, 0x21, 0 + .dw 0x4840, 0xc606, 0x49ff, 0xc606, 0x21, 0 + .dw 0x4a40, 0xc606, 0x4bff, 0xc606, 0x21, 0 + .dw 0x4c40, 0xc606, 0x4dff, 0xc606, 0x21, 0 + .dw 0x4e40, 0xc606, 0xbfff, 0xc606, 0x21, 0 + .dw 0xc040, 0xc606, 0xc1ff, 0xc606, 0x21, 0 + .dw 0xc240, 0xc606, 0xc3ff, 0xc606, 0x21, 0 + .dw 0xc440, 0xc606, 0xc5ff, 0xc606, 0x21, 0 + .dw 0xc640, 0xc606, 0xc7ff, 0xc606, 0x21, 0 + .dw 0xc840, 0xc606, 0xc9ff, 0xc606, 0x21, 0 + .dw 0xca40, 0xc606, 0xcbff, 0xc606, 0x21, 0 + .dw 0xcc40, 0xc606, 0xcdff, 0xc606, 0x21, 0 + .dw 0xce40, 0xc606, 0xffff, 0xc606, 0x21, 0 + .dw 0x0040, 0xc607, 0x01ff, 0xc607, 0x21, 0 + .dw 0x0240, 0xc607, 0x03ff, 0xc607, 0x21, 0 + .dw 0x0440, 0xc607, 0x05ff, 0xc607, 0x21, 0 + .dw 0x0640, 0xc607, 0x07ff, 0xc607, 0x21, 0 + .dw 0x0840, 0xc607, 0x09ff, 0xc607, 0x21, 0 + .dw 0x0a40, 0xc607, 0x0bff, 0xc607, 0x21, 0 + .dw 0x0c40, 0xc607, 0x0dff, 0xc607, 0x21, 0 + .dw 0x0e40, 0xc607, 0x3fff, 0xc607, 0x21, 0 + .dw 0x4040, 0xc607, 0x41ff, 0xc607, 0x21, 0 + .dw 0x4240, 0xc607, 0x43ff, 0xc607, 0x21, 0 + .dw 0x4440, 0xc607, 0x45ff, 0xc607, 0x21, 0 + .dw 0x4640, 0xc607, 0x47ff, 0xc607, 0x21, 0 + .dw 0x4840, 0xc607, 0x49ff, 0xc607, 0x21, 0 + .dw 0x4a40, 0xc607, 0x4bff, 0xc607, 0x21, 0 + .dw 0x4c40, 0xc607, 0x4dff, 0xc607, 0x21, 0 + .dw 0x4e40, 0xc607, 0x7fff, 0xc607, 0x21, 0 + .dw 0x8040, 0xc607, 0x81ff, 0xc607, 0x21, 0 + .dw 0x8240, 0xc607, 0x83ff, 0xc607, 0x21, 0 + .dw 0x8440, 0xc607, 0x85ff, 0xc607, 0x21, 0 + .dw 0x8640, 0xc607, 0x87ff, 0xc607, 0x21, 0 + .dw 0x8840, 0xc607, 0x89ff, 0xc607, 0x21, 0 + .dw 0x8a40, 0xc607, 0x8bff, 0xc607, 0x21, 0 + .dw 0x8c40, 0xc607, 0x8dff, 0xc607, 0x21, 0 + .dw 0x8e40, 0xc607, 0xbfff, 0xc607, 0x21, 0 + .dw 0xc040, 0xc607, 0xc1ff, 0xc607, 0x21, 0 + .dw 0xc240, 0xc607, 0xc3ff, 0xc607, 0x21, 0 + .dw 0xc440, 0xc607, 0xc5ff, 0xc607, 0x21, 0 + .dw 0xc640, 0xc607, 0xc7ff, 0xc607, 0x21, 0 + .dw 0xc840, 0xc607, 0xc9ff, 0xc607, 0x21, 0 + .dw 0xca40, 0xc607, 0xcbff, 0xc607, 0x21, 0 + .dw 0xcc40, 0xc607, 0xcdff, 0xc607, 0x21, 0 + .dw 0xce40, 0xc607, 0xffff, 0xc607, 0x21, 0 + .dw 0x0000, 0xc608, 0x0000, 0xc608, 0x22, 0 + .dw 0x0009, 0xc608, 0x0009, 0xc608, 0x22, 0 + .dw 0x0012, 0xc608, 0x0012, 0xc608, 0x22, 0 + .dw 0x001b, 0xc608, 0x001b, 0xc608, 0x22, 0 + .dw 0x0024, 0xc608, 0x0024, 0xc608, 0x22, 0 + .dw 0x002d, 0xc608, 0x002d, 0xc608, 0x22, 0 + .dw 0x0036, 0xc608, 0x0036, 0xc608, 0x22, 0 + .dw 0x003f, 0xc608, 0x003f, 0xc608, 0x22, 0 + .dw 0x0040, 0xc608, 0x01ff, 0xc608, 0x21, 0 + .dw 0x0200, 0xc608, 0x0200, 0xc608, 0x22, 0 + .dw 0x0209, 0xc608, 0x0209, 0xc608, 0x22, 0 + .dw 0x0212, 0xc608, 0x0212, 0xc608, 0x22, 0 + .dw 0x021b, 0xc608, 0x021b, 0xc608, 0x22, 0 + .dw 0x0224, 0xc608, 0x0224, 0xc608, 0x22, 0 + .dw 0x022d, 0xc608, 0x022d, 0xc608, 0x22, 0 + .dw 0x0236, 0xc608, 0x0236, 0xc608, 0x22, 0 + .dw 0x023f, 0xc608, 0x023f, 0xc608, 0x22, 0 + .dw 0x0240, 0xc608, 0x03ff, 0xc608, 0x21, 0 + .dw 0x0400, 0xc608, 0x0400, 0xc608, 0x22, 0 + .dw 0x0409, 0xc608, 0x0409, 0xc608, 0x22, 0 + .dw 0x0412, 0xc608, 0x0412, 0xc608, 0x22, 0 + .dw 0x041b, 0xc608, 0x041b, 0xc608, 0x22, 0 + .dw 0x0424, 0xc608, 0x0424, 0xc608, 0x22, 0 + .dw 0x042d, 0xc608, 0x042d, 0xc608, 0x22, 0 + .dw 0x0436, 0xc608, 0x0436, 0xc608, 0x22, 0 + .dw 0x043f, 0xc608, 0x043f, 0xc608, 0x22, 0 + .dw 0x0440, 0xc608, 0x05ff, 0xc608, 0x21, 0 + .dw 0x0600, 0xc608, 0x0600, 0xc608, 0x22, 0 + .dw 0x0609, 0xc608, 0x0609, 0xc608, 0x22, 0 + .dw 0x0612, 0xc608, 0x0612, 0xc608, 0x22, 0 + .dw 0x061b, 0xc608, 0x061b, 0xc608, 0x22, 0 + .dw 0x0624, 0xc608, 0x0624, 0xc608, 0x22, 0 + .dw 0x062d, 0xc608, 0x062d, 0xc608, 0x22, 0 + .dw 0x0636, 0xc608, 0x0636, 0xc608, 0x22, 0 + .dw 0x063f, 0xc608, 0x063f, 0xc608, 0x22, 0 + .dw 0x0640, 0xc608, 0x07ff, 0xc608, 0x21, 0 + .dw 0x0800, 0xc608, 0x0800, 0xc608, 0x22, 0 + .dw 0x0809, 0xc608, 0x0809, 0xc608, 0x22, 0 + .dw 0x0812, 0xc608, 0x0812, 0xc608, 0x22, 0 + .dw 0x081b, 0xc608, 0x081b, 0xc608, 0x22, 0 + .dw 0x0824, 0xc608, 0x0824, 0xc608, 0x22, 0 + .dw 0x082d, 0xc608, 0x082d, 0xc608, 0x22, 0 + .dw 0x0836, 0xc608, 0x0836, 0xc608, 0x22, 0 + .dw 0x083f, 0xc608, 0x083f, 0xc608, 0x22, 0 + .dw 0x0840, 0xc608, 0x09ff, 0xc608, 0x21, 0 + .dw 0x0a00, 0xc608, 0x0a00, 0xc608, 0x22, 0 + .dw 0x0a09, 0xc608, 0x0a09, 0xc608, 0x22, 0 + .dw 0x0a12, 0xc608, 0x0a12, 0xc608, 0x22, 0 + .dw 0x0a1b, 0xc608, 0x0a1b, 0xc608, 0x22, 0 + .dw 0x0a24, 0xc608, 0x0a24, 0xc608, 0x22, 0 + .dw 0x0a2d, 0xc608, 0x0a2d, 0xc608, 0x22, 0 + .dw 0x0a36, 0xc608, 0x0a36, 0xc608, 0x22, 0 + .dw 0x0a3f, 0xc608, 0x0a3f, 0xc608, 0x22, 0 + .dw 0x0a40, 0xc608, 0x0bff, 0xc608, 0x21, 0 + .dw 0x0c00, 0xc608, 0x0c00, 0xc608, 0x22, 0 + .dw 0x0c09, 0xc608, 0x0c09, 0xc608, 0x22, 0 + .dw 0x0c12, 0xc608, 0x0c12, 0xc608, 0x22, 0 + .dw 0x0c1b, 0xc608, 0x0c1b, 0xc608, 0x22, 0 + .dw 0x0c24, 0xc608, 0x0c24, 0xc608, 0x22, 0 + .dw 0x0c2d, 0xc608, 0x0c2d, 0xc608, 0x22, 0 + .dw 0x0c36, 0xc608, 0x0c36, 0xc608, 0x22, 0 + .dw 0x0c3f, 0xc608, 0x0c3f, 0xc608, 0x22, 0 + .dw 0x0c40, 0xc608, 0x0dff, 0xc608, 0x21, 0 + .dw 0x0e00, 0xc608, 0x0e00, 0xc608, 0x22, 0 + .dw 0x0e09, 0xc608, 0x0e09, 0xc608, 0x22, 0 + .dw 0x0e12, 0xc608, 0x0e12, 0xc608, 0x22, 0 + .dw 0x0e1b, 0xc608, 0x0e1b, 0xc608, 0x22, 0 + .dw 0x0e24, 0xc608, 0x0e24, 0xc608, 0x22, 0 + .dw 0x0e2d, 0xc608, 0x0e2d, 0xc608, 0x22, 0 + .dw 0x0e36, 0xc608, 0x0e36, 0xc608, 0x22, 0 + .dw 0x0e3f, 0xc608, 0x0e3f, 0xc608, 0x22, 0 + .dw 0x0e40, 0xc608, 0x3fff, 0xc608, 0x21, 0 + .dw 0x4000, 0xc608, 0x4000, 0xc608, 0x22, 0 + .dw 0x4009, 0xc608, 0x4009, 0xc608, 0x22, 0 + .dw 0x4012, 0xc608, 0x4012, 0xc608, 0x22, 0 + .dw 0x401b, 0xc608, 0x401b, 0xc608, 0x22, 0 + .dw 0x4024, 0xc608, 0x4024, 0xc608, 0x22, 0 + .dw 0x402d, 0xc608, 0x402d, 0xc608, 0x22, 0 + .dw 0x4036, 0xc608, 0x4036, 0xc608, 0x22, 0 + .dw 0x403f, 0xc608, 0x403f, 0xc608, 0x22, 0 + .dw 0x4040, 0xc608, 0x41ff, 0xc608, 0x21, 0 + .dw 0x4200, 0xc608, 0x4200, 0xc608, 0x22, 0 + .dw 0x4209, 0xc608, 0x4209, 0xc608, 0x22, 0 + .dw 0x4212, 0xc608, 0x4212, 0xc608, 0x22, 0 + .dw 0x421b, 0xc608, 0x421b, 0xc608, 0x22, 0 + .dw 0x4224, 0xc608, 0x4224, 0xc608, 0x22, 0 + .dw 0x422d, 0xc608, 0x422d, 0xc608, 0x22, 0 + .dw 0x4236, 0xc608, 0x4236, 0xc608, 0x22, 0 + .dw 0x423f, 0xc608, 0x423f, 0xc608, 0x22, 0 + .dw 0x4240, 0xc608, 0x43ff, 0xc608, 0x21, 0 + .dw 0x4400, 0xc608, 0x4400, 0xc608, 0x22, 0 + .dw 0x4409, 0xc608, 0x4409, 0xc608, 0x22, 0 + .dw 0x4412, 0xc608, 0x4412, 0xc608, 0x22, 0 + .dw 0x441b, 0xc608, 0x441b, 0xc608, 0x22, 0 + .dw 0x4424, 0xc608, 0x4424, 0xc608, 0x22, 0 + .dw 0x442d, 0xc608, 0x442d, 0xc608, 0x22, 0 + .dw 0x4436, 0xc608, 0x4436, 0xc608, 0x22, 0 + .dw 0x443f, 0xc608, 0x443f, 0xc608, 0x22, 0 + .dw 0x4440, 0xc608, 0x45ff, 0xc608, 0x21, 0 + .dw 0x4600, 0xc608, 0x4600, 0xc608, 0x22, 0 + .dw 0x4609, 0xc608, 0x4609, 0xc608, 0x22, 0 + .dw 0x4612, 0xc608, 0x4612, 0xc608, 0x22, 0 + .dw 0x461b, 0xc608, 0x461b, 0xc608, 0x22, 0 + .dw 0x4624, 0xc608, 0x4624, 0xc608, 0x22, 0 + .dw 0x462d, 0xc608, 0x462d, 0xc608, 0x22, 0 + .dw 0x4636, 0xc608, 0x4636, 0xc608, 0x22, 0 + .dw 0x463f, 0xc608, 0x463f, 0xc608, 0x22, 0 + .dw 0x4640, 0xc608, 0x47ff, 0xc608, 0x21, 0 + .dw 0x4800, 0xc608, 0x4800, 0xc608, 0x22, 0 + .dw 0x4809, 0xc608, 0x4809, 0xc608, 0x22, 0 + .dw 0x4812, 0xc608, 0x4812, 0xc608, 0x22, 0 + .dw 0x481b, 0xc608, 0x481b, 0xc608, 0x22, 0 + .dw 0x4824, 0xc608, 0x4824, 0xc608, 0x22, 0 + .dw 0x482d, 0xc608, 0x482d, 0xc608, 0x22, 0 + .dw 0x4836, 0xc608, 0x4836, 0xc608, 0x22, 0 + .dw 0x483f, 0xc608, 0x483f, 0xc608, 0x22, 0 + .dw 0x4840, 0xc608, 0x49ff, 0xc608, 0x21, 0 + .dw 0x4a00, 0xc608, 0x4a00, 0xc608, 0x22, 0 + .dw 0x4a09, 0xc608, 0x4a09, 0xc608, 0x22, 0 + .dw 0x4a12, 0xc608, 0x4a12, 0xc608, 0x22, 0 + .dw 0x4a1b, 0xc608, 0x4a1b, 0xc608, 0x22, 0 + .dw 0x4a24, 0xc608, 0x4a24, 0xc608, 0x22, 0 + .dw 0x4a2d, 0xc608, 0x4a2d, 0xc608, 0x22, 0 + .dw 0x4a36, 0xc608, 0x4a36, 0xc608, 0x22, 0 + .dw 0x4a3f, 0xc608, 0x4a3f, 0xc608, 0x22, 0 + .dw 0x4a40, 0xc608, 0x4bff, 0xc608, 0x21, 0 + .dw 0x4c00, 0xc608, 0x4c00, 0xc608, 0x22, 0 + .dw 0x4c09, 0xc608, 0x4c09, 0xc608, 0x22, 0 + .dw 0x4c12, 0xc608, 0x4c12, 0xc608, 0x22, 0 + .dw 0x4c1b, 0xc608, 0x4c1b, 0xc608, 0x22, 0 + .dw 0x4c24, 0xc608, 0x4c24, 0xc608, 0x22, 0 + .dw 0x4c2d, 0xc608, 0x4c2d, 0xc608, 0x22, 0 + .dw 0x4c36, 0xc608, 0x4c36, 0xc608, 0x22, 0 + .dw 0x4c3f, 0xc608, 0x4c3f, 0xc608, 0x22, 0 + .dw 0x4c40, 0xc608, 0x4dff, 0xc608, 0x21, 0 + .dw 0x4e00, 0xc608, 0x4e00, 0xc608, 0x22, 0 + .dw 0x4e09, 0xc608, 0x4e09, 0xc608, 0x22, 0 + .dw 0x4e12, 0xc608, 0x4e12, 0xc608, 0x22, 0 + .dw 0x4e1b, 0xc608, 0x4e1b, 0xc608, 0x22, 0 + .dw 0x4e24, 0xc608, 0x4e24, 0xc608, 0x22, 0 + .dw 0x4e2d, 0xc608, 0x4e2d, 0xc608, 0x22, 0 + .dw 0x4e36, 0xc608, 0x4e36, 0xc608, 0x22, 0 + .dw 0x4e3f, 0xc608, 0x4e3f, 0xc608, 0x22, 0 + .dw 0x4e40, 0xc608, 0xffff, 0xc608, 0x21, 0 + .dw 0x0040, 0xc609, 0x01ff, 0xc609, 0x21, 0 + .dw 0x0240, 0xc609, 0x03ff, 0xc609, 0x21, 0 + .dw 0x0440, 0xc609, 0x05ff, 0xc609, 0x21, 0 + .dw 0x0640, 0xc609, 0x07ff, 0xc609, 0x21, 0 + .dw 0x0840, 0xc609, 0x09ff, 0xc609, 0x21, 0 + .dw 0x0a40, 0xc609, 0x0bff, 0xc609, 0x21, 0 + .dw 0x0c40, 0xc609, 0x0dff, 0xc609, 0x21, 0 + .dw 0x0e40, 0xc609, 0x3fff, 0xc609, 0x21, 0 + .dw 0x4040, 0xc609, 0x41ff, 0xc609, 0x21, 0 + .dw 0x4240, 0xc609, 0x43ff, 0xc609, 0x21, 0 + .dw 0x4440, 0xc609, 0x45ff, 0xc609, 0x21, 0 + .dw 0x4640, 0xc609, 0x47ff, 0xc609, 0x21, 0 + .dw 0x4840, 0xc609, 0x49ff, 0xc609, 0x21, 0 + .dw 0x4a40, 0xc609, 0x4bff, 0xc609, 0x21, 0 + .dw 0x4c40, 0xc609, 0x4dff, 0xc609, 0x21, 0 + .dw 0x4e40, 0xc609, 0x7fff, 0xc609, 0x21, 0 + .dw 0x8040, 0xc609, 0x81ff, 0xc609, 0x21, 0 + .dw 0x8240, 0xc609, 0x83ff, 0xc609, 0x21, 0 + .dw 0x8440, 0xc609, 0x85ff, 0xc609, 0x21, 0 + .dw 0x8640, 0xc609, 0x87ff, 0xc609, 0x21, 0 + .dw 0x8840, 0xc609, 0x89ff, 0xc609, 0x21, 0 + .dw 0x8a40, 0xc609, 0x8bff, 0xc609, 0x21, 0 + .dw 0x8c40, 0xc609, 0x8dff, 0xc609, 0x21, 0 + .dw 0x8e40, 0xc609, 0xbfff, 0xc609, 0x21, 0 + .dw 0xc040, 0xc609, 0xc1ff, 0xc609, 0x21, 0 + .dw 0xc240, 0xc609, 0xc3ff, 0xc609, 0x21, 0 + .dw 0xc440, 0xc609, 0xc5ff, 0xc609, 0x21, 0 + .dw 0xc640, 0xc609, 0xc7ff, 0xc609, 0x21, 0 + .dw 0xc840, 0xc609, 0xc9ff, 0xc609, 0x21, 0 + .dw 0xca40, 0xc609, 0xcbff, 0xc609, 0x21, 0 + .dw 0xcc40, 0xc609, 0xcdff, 0xc609, 0x21, 0 + .dw 0xce40, 0xc609, 0xffff, 0xc609, 0x21, 0 + .dw 0x0040, 0xc60a, 0x01ff, 0xc60a, 0x21, 0 + .dw 0x0240, 0xc60a, 0x03ff, 0xc60a, 0x21, 0 + .dw 0x0440, 0xc60a, 0x05ff, 0xc60a, 0x21, 0 + .dw 0x0640, 0xc60a, 0x07ff, 0xc60a, 0x21, 0 + .dw 0x0840, 0xc60a, 0x09ff, 0xc60a, 0x21, 0 + .dw 0x0a40, 0xc60a, 0x0bff, 0xc60a, 0x21, 0 + .dw 0x0c40, 0xc60a, 0x0dff, 0xc60a, 0x21, 0 + .dw 0x0e40, 0xc60a, 0x3fff, 0xc60a, 0x21, 0 + .dw 0x4040, 0xc60a, 0x41ff, 0xc60a, 0x21, 0 + .dw 0x4240, 0xc60a, 0x43ff, 0xc60a, 0x21, 0 + .dw 0x4440, 0xc60a, 0x45ff, 0xc60a, 0x21, 0 + .dw 0x4640, 0xc60a, 0x47ff, 0xc60a, 0x21, 0 + .dw 0x4840, 0xc60a, 0x49ff, 0xc60a, 0x21, 0 + .dw 0x4a40, 0xc60a, 0x4bff, 0xc60a, 0x21, 0 + .dw 0x4c40, 0xc60a, 0x4dff, 0xc60a, 0x21, 0 + .dw 0x4e40, 0xc60a, 0x7fff, 0xc60a, 0x21, 0 + .dw 0x8040, 0xc60a, 0x81ff, 0xc60a, 0x21, 0 + .dw 0x8240, 0xc60a, 0x83ff, 0xc60a, 0x21, 0 + .dw 0x8440, 0xc60a, 0x85ff, 0xc60a, 0x21, 0 + .dw 0x8640, 0xc60a, 0x87ff, 0xc60a, 0x21, 0 + .dw 0x8840, 0xc60a, 0x89ff, 0xc60a, 0x21, 0 + .dw 0x8a40, 0xc60a, 0x8bff, 0xc60a, 0x21, 0 + .dw 0x8c40, 0xc60a, 0x8dff, 0xc60a, 0x21, 0 + .dw 0x8e40, 0xc60a, 0xbfff, 0xc60a, 0x21, 0 + .dw 0xc040, 0xc60a, 0xc1ff, 0xc60a, 0x21, 0 + .dw 0xc240, 0xc60a, 0xc3ff, 0xc60a, 0x21, 0 + .dw 0xc440, 0xc60a, 0xc5ff, 0xc60a, 0x21, 0 + .dw 0xc640, 0xc60a, 0xc7ff, 0xc60a, 0x21, 0 + .dw 0xc840, 0xc60a, 0xc9ff, 0xc60a, 0x21, 0 + .dw 0xca40, 0xc60a, 0xcbff, 0xc60a, 0x21, 0 + .dw 0xcc40, 0xc60a, 0xcdff, 0xc60a, 0x21, 0 + .dw 0xce40, 0xc60a, 0xffff, 0xc60a, 0x21, 0 + .dw 0x0040, 0xc60b, 0x01ff, 0xc60b, 0x21, 0 + .dw 0x0240, 0xc60b, 0x03ff, 0xc60b, 0x21, 0 + .dw 0x0440, 0xc60b, 0x05ff, 0xc60b, 0x21, 0 + .dw 0x0640, 0xc60b, 0x07ff, 0xc60b, 0x21, 0 + .dw 0x0840, 0xc60b, 0x09ff, 0xc60b, 0x21, 0 + .dw 0x0a40, 0xc60b, 0x0bff, 0xc60b, 0x21, 0 + .dw 0x0c40, 0xc60b, 0x0dff, 0xc60b, 0x21, 0 + .dw 0x0e40, 0xc60b, 0x3fff, 0xc60b, 0x21, 0 + .dw 0x4040, 0xc60b, 0x41ff, 0xc60b, 0x21, 0 + .dw 0x4240, 0xc60b, 0x43ff, 0xc60b, 0x21, 0 + .dw 0x4440, 0xc60b, 0x45ff, 0xc60b, 0x21, 0 + .dw 0x4640, 0xc60b, 0x47ff, 0xc60b, 0x21, 0 + .dw 0x4840, 0xc60b, 0x49ff, 0xc60b, 0x21, 0 + .dw 0x4a40, 0xc60b, 0x4bff, 0xc60b, 0x21, 0 + .dw 0x4c40, 0xc60b, 0x4dff, 0xc60b, 0x21, 0 + .dw 0x4e40, 0xc60b, 0xffff, 0xc60b, 0x21, 0 + .dw 0x0040, 0xc60c, 0x01ff, 0xc60c, 0x21, 0 + .dw 0x0240, 0xc60c, 0x03ff, 0xc60c, 0x21, 0 + .dw 0x0440, 0xc60c, 0x05ff, 0xc60c, 0x21, 0 + .dw 0x0640, 0xc60c, 0x07ff, 0xc60c, 0x21, 0 + .dw 0x0840, 0xc60c, 0x09ff, 0xc60c, 0x21, 0 + .dw 0x0a40, 0xc60c, 0x0bff, 0xc60c, 0x21, 0 + .dw 0x0c40, 0xc60c, 0x0dff, 0xc60c, 0x21, 0 + .dw 0x0e40, 0xc60c, 0x3fff, 0xc60c, 0x21, 0 + .dw 0x4040, 0xc60c, 0x41ff, 0xc60c, 0x21, 0 + .dw 0x4240, 0xc60c, 0x43ff, 0xc60c, 0x21, 0 + .dw 0x4440, 0xc60c, 0x45ff, 0xc60c, 0x21, 0 + .dw 0x4640, 0xc60c, 0x47ff, 0xc60c, 0x21, 0 + .dw 0x4840, 0xc60c, 0x49ff, 0xc60c, 0x21, 0 + .dw 0x4a40, 0xc60c, 0x4bff, 0xc60c, 0x21, 0 + .dw 0x4c40, 0xc60c, 0x4dff, 0xc60c, 0x21, 0 + .dw 0x4e40, 0xc60c, 0xffff, 0xc60c, 0x21, 0 + .dw 0x0040, 0xc60d, 0x01ff, 0xc60d, 0x21, 0 + .dw 0x0240, 0xc60d, 0x03ff, 0xc60d, 0x21, 0 + .dw 0x0440, 0xc60d, 0x05ff, 0xc60d, 0x21, 0 + .dw 0x0640, 0xc60d, 0x07ff, 0xc60d, 0x21, 0 + .dw 0x0840, 0xc60d, 0x09ff, 0xc60d, 0x21, 0 + .dw 0x0a40, 0xc60d, 0x0bff, 0xc60d, 0x21, 0 + .dw 0x0c40, 0xc60d, 0x0dff, 0xc60d, 0x21, 0 + .dw 0x0e40, 0xc60d, 0x3fff, 0xc60d, 0x21, 0 + .dw 0x4040, 0xc60d, 0x41ff, 0xc60d, 0x21, 0 + .dw 0x4240, 0xc60d, 0x43ff, 0xc60d, 0x21, 0 + .dw 0x4440, 0xc60d, 0x45ff, 0xc60d, 0x21, 0 + .dw 0x4640, 0xc60d, 0x47ff, 0xc60d, 0x21, 0 + .dw 0x4840, 0xc60d, 0x49ff, 0xc60d, 0x21, 0 + .dw 0x4a40, 0xc60d, 0x4bff, 0xc60d, 0x21, 0 + .dw 0x4c40, 0xc60d, 0x4dff, 0xc60d, 0x21, 0 + .dw 0x4e40, 0xc60d, 0x7fff, 0xc60d, 0x21, 0 + .dw 0x8040, 0xc60d, 0x81ff, 0xc60d, 0x21, 0 + .dw 0x8240, 0xc60d, 0x83ff, 0xc60d, 0x21, 0 + .dw 0x8440, 0xc60d, 0x85ff, 0xc60d, 0x21, 0 + .dw 0x8640, 0xc60d, 0x87ff, 0xc60d, 0x21, 0 + .dw 0x8840, 0xc60d, 0x89ff, 0xc60d, 0x21, 0 + .dw 0x8a40, 0xc60d, 0x8bff, 0xc60d, 0x21, 0 + .dw 0x8c40, 0xc60d, 0x8dff, 0xc60d, 0x21, 0 + .dw 0x8e40, 0xc60d, 0xffff, 0xc67f, 0x21, 0 + .dw 0xc000, 0xc680, 0xffff, 0xc680, 0x21, 0 + .dw 0x1000, 0xc681, 0x3fff, 0xc681, 0x21, 0 + .dw 0x5000, 0xc681, 0x7fff, 0xc681, 0x21, 0 + .dw 0x9000, 0xc681, 0xffff, 0xc681, 0x21, 0 + .dw 0x1000, 0xc682, 0x3fff, 0xc682, 0x21, 0 + .dw 0x5000, 0xc682, 0x7fff, 0xc682, 0x21, 0 + .dw 0x9000, 0xc682, 0xbfff, 0xc682, 0x21, 0 + .dw 0xd000, 0xc682, 0xffff, 0xc682, 0x21, 0 + .dw 0x2000, 0xc683, 0x3fff, 0xc683, 0x21, 0 + .dw 0x6000, 0xc683, 0x7fff, 0xc683, 0x21, 0 + .dw 0xa000, 0xc683, 0xffff, 0xe07f, 0x21, 0 + .dw 0x0400, 0xe080, 0x0fff, 0xe080, 0x21, 0 + .dw 0x1400, 0xe080, 0x1fff, 0xe080, 0x21, 0 + .dw 0x2400, 0xe080, 0x2fff, 0xe080, 0x21, 0 + .dw 0x3400, 0xe080, 0x3fff, 0xe080, 0x21, 0 + .dw 0x4400, 0xe080, 0x4fff, 0xe080, 0x21, 0 + .dw 0x5400, 0xe080, 0x5fff, 0xe080, 0x21, 0 + .dw 0x6400, 0xe080, 0x6fff, 0xe080, 0x21, 0 + .dw 0x7400, 0xe080, 0xffff, 0xe080, 0x21, 0 + .dw 0x0400, 0xe081, 0x0fff, 0xe081, 0x21, 0 + .dw 0x1400, 0xe081, 0x1fff, 0xe081, 0x21, 0 + .dw 0x2400, 0xe081, 0x2fff, 0xe081, 0x21, 0 + .dw 0x3400, 0xe081, 0x3fff, 0xe081, 0x21, 0 + .dw 0x4400, 0xe081, 0x4fff, 0xe081, 0x21, 0 + .dw 0x5400, 0xe081, 0x5fff, 0xe081, 0x21, 0 + .dw 0x6400, 0xe081, 0x6fff, 0xe081, 0x21, 0 + .dw 0x7400, 0xe081, 0xffff, 0xe081, 0x21, 0 + .dw 0x0400, 0xe082, 0x0fff, 0xe082, 0x21, 0 + .dw 0x1400, 0xe082, 0x1fff, 0xe082, 0x21, 0 + .dw 0x2400, 0xe082, 0x2fff, 0xe082, 0x21, 0 + .dw 0x3400, 0xe082, 0x3fff, 0xe082, 0x21, 0 + .dw 0x4400, 0xe082, 0x4fff, 0xe082, 0x21, 0 + .dw 0x5400, 0xe082, 0x5fff, 0xe082, 0x21, 0 + .dw 0x6400, 0xe082, 0x6fff, 0xe082, 0x21, 0 + .dw 0x7400, 0xe082, 0xffff, 0xe082, 0x21, 0 + .dw 0x0400, 0xe083, 0x0fff, 0xe083, 0x21, 0 + .dw 0x1400, 0xe083, 0x1fff, 0xe083, 0x21, 0 + .dw 0x2400, 0xe083, 0x2fff, 0xe083, 0x21, 0 + .dw 0x3400, 0xe083, 0x3fff, 0xe083, 0x21, 0 + .dw 0x4400, 0xe083, 0x4fff, 0xe083, 0x21, 0 + .dw 0x5400, 0xe083, 0x5fff, 0xe083, 0x21, 0 + .dw 0x6400, 0xe083, 0x6fff, 0xe083, 0x21, 0 + .dw 0x7400, 0xe083, 0xffff, 0xe083, 0x21, 0 + .dw 0x0400, 0xe084, 0x0fff, 0xe084, 0x21, 0 + .dw 0x1400, 0xe084, 0x1fff, 0xe084, 0x21, 0 + .dw 0x2400, 0xe084, 0x2fff, 0xe084, 0x21, 0 + .dw 0x3400, 0xe084, 0x3fff, 0xe084, 0x21, 0 + .dw 0x4400, 0xe084, 0x4fff, 0xe084, 0x21, 0 + .dw 0x5400, 0xe084, 0x5fff, 0xe084, 0x21, 0 + .dw 0x6400, 0xe084, 0x6fff, 0xe084, 0x21, 0 + .dw 0x7400, 0xe084, 0xffff, 0xe084, 0x21, 0 + .dw 0x0400, 0xe085, 0x0fff, 0xe085, 0x21, 0 + .dw 0x1400, 0xe085, 0x1fff, 0xe085, 0x21, 0 + .dw 0x2400, 0xe085, 0x2fff, 0xe085, 0x21, 0 + .dw 0x3400, 0xe085, 0x3fff, 0xe085, 0x21, 0 + .dw 0x4400, 0xe085, 0x4fff, 0xe085, 0x21, 0 + .dw 0x5400, 0xe085, 0x5fff, 0xe085, 0x21, 0 + .dw 0x6400, 0xe085, 0x6fff, 0xe085, 0x21, 0 + .dw 0x7400, 0xe085, 0xffff, 0xe085, 0x21, 0 + .dw 0x0400, 0xe086, 0x0fff, 0xe086, 0x21, 0 + .dw 0x1400, 0xe086, 0x1fff, 0xe086, 0x21, 0 + .dw 0x2400, 0xe086, 0x2fff, 0xe086, 0x21, 0 + .dw 0x3400, 0xe086, 0x3fff, 0xe086, 0x21, 0 + .dw 0x4400, 0xe086, 0x4fff, 0xe086, 0x21, 0 + .dw 0x5400, 0xe086, 0x5fff, 0xe086, 0x21, 0 + .dw 0x6400, 0xe086, 0x6fff, 0xe086, 0x21, 0 + .dw 0x7400, 0xe086, 0xffff, 0xe086, 0x21, 0 + .dw 0x0400, 0xe087, 0x0fff, 0xe087, 0x21, 0 + .dw 0x1400, 0xe087, 0x1fff, 0xe087, 0x21, 0 + .dw 0x2400, 0xe087, 0x2fff, 0xe087, 0x21, 0 + .dw 0x3400, 0xe087, 0x3fff, 0xe087, 0x21, 0 + .dw 0x4400, 0xe087, 0x4fff, 0xe087, 0x21, 0 + .dw 0x5400, 0xe087, 0x5fff, 0xe087, 0x21, 0 + .dw 0x6400, 0xe087, 0x6fff, 0xe087, 0x21, 0 + .dw 0x7400, 0xe087, 0xffff, 0xe087, 0x21, 0 + .dw 0x0400, 0xe088, 0x0fff, 0xe088, 0x21, 0 + .dw 0x1400, 0xe088, 0x1fff, 0xe088, 0x21, 0 + .dw 0x2400, 0xe088, 0x2fff, 0xe088, 0x21, 0 + .dw 0x3400, 0xe088, 0x3fff, 0xe088, 0x21, 0 + .dw 0x4400, 0xe088, 0x4fff, 0xe088, 0x21, 0 + .dw 0x5400, 0xe088, 0x5fff, 0xe088, 0x21, 0 + .dw 0x6400, 0xe088, 0x6fff, 0xe088, 0x21, 0 + .dw 0x7400, 0xe088, 0xffff, 0xe088, 0x21, 0 + .dw 0x0400, 0xe089, 0x0fff, 0xe089, 0x21, 0 + .dw 0x1400, 0xe089, 0x1fff, 0xe089, 0x21, 0 + .dw 0x2400, 0xe089, 0x2fff, 0xe089, 0x21, 0 + .dw 0x3400, 0xe089, 0x3fff, 0xe089, 0x21, 0 + .dw 0x4400, 0xe089, 0x4fff, 0xe089, 0x21, 0 + .dw 0x5400, 0xe089, 0x5fff, 0xe089, 0x21, 0 + .dw 0x6400, 0xe089, 0x6fff, 0xe089, 0x21, 0 + .dw 0x7400, 0xe089, 0xffff, 0xe089, 0x21, 0 + .dw 0x0400, 0xe08a, 0x0fff, 0xe08a, 0x21, 0 + .dw 0x1400, 0xe08a, 0x1fff, 0xe08a, 0x21, 0 + .dw 0x2400, 0xe08a, 0x2fff, 0xe08a, 0x21, 0 + .dw 0x3400, 0xe08a, 0x3fff, 0xe08a, 0x21, 0 + .dw 0x4400, 0xe08a, 0x4fff, 0xe08a, 0x21, 0 + .dw 0x5400, 0xe08a, 0x5fff, 0xe08a, 0x21, 0 + .dw 0x6400, 0xe08a, 0x6fff, 0xe08a, 0x21, 0 + .dw 0x7400, 0xe08a, 0xffff, 0xe08a, 0x21, 0 + .dw 0x0400, 0xe08b, 0x0fff, 0xe08b, 0x21, 0 + .dw 0x1400, 0xe08b, 0x1fff, 0xe08b, 0x21, 0 + .dw 0x2400, 0xe08b, 0x2fff, 0xe08b, 0x21, 0 + .dw 0x3400, 0xe08b, 0x3fff, 0xe08b, 0x21, 0 + .dw 0x4400, 0xe08b, 0x4fff, 0xe08b, 0x21, 0 + .dw 0x5400, 0xe08b, 0x5fff, 0xe08b, 0x21, 0 + .dw 0x6400, 0xe08b, 0x6fff, 0xe08b, 0x21, 0 + .dw 0x7400, 0xe08b, 0xffff, 0xe08b, 0x21, 0 + .dw 0x0400, 0xe08c, 0x0fff, 0xe08c, 0x21, 0 + .dw 0x1400, 0xe08c, 0x1fff, 0xe08c, 0x21, 0 + .dw 0x2400, 0xe08c, 0x2fff, 0xe08c, 0x21, 0 + .dw 0x3400, 0xe08c, 0x3fff, 0xe08c, 0x21, 0 + .dw 0x4400, 0xe08c, 0x4fff, 0xe08c, 0x21, 0 + .dw 0x5400, 0xe08c, 0x5fff, 0xe08c, 0x21, 0 + .dw 0x6400, 0xe08c, 0x6fff, 0xe08c, 0x21, 0 + .dw 0x7400, 0xe08c, 0xffff, 0xe08c, 0x21, 0 + .dw 0x0400, 0xe08d, 0x0fff, 0xe08d, 0x21, 0 + .dw 0x1400, 0xe08d, 0x1fff, 0xe08d, 0x21, 0 + .dw 0x2400, 0xe08d, 0x2fff, 0xe08d, 0x21, 0 + .dw 0x3400, 0xe08d, 0x3fff, 0xe08d, 0x21, 0 + .dw 0x4400, 0xe08d, 0x4fff, 0xe08d, 0x21, 0 + .dw 0x5400, 0xe08d, 0x5fff, 0xe08d, 0x21, 0 + .dw 0x6400, 0xe08d, 0x6fff, 0xe08d, 0x21, 0 + .dw 0x7400, 0xe08d, 0xffff, 0xe08d, 0x21, 0 + .dw 0x0400, 0xe08e, 0x0fff, 0xe08e, 0x21, 0 + .dw 0x1400, 0xe08e, 0x1fff, 0xe08e, 0x21, 0 + .dw 0x2400, 0xe08e, 0x2fff, 0xe08e, 0x21, 0 + .dw 0x3400, 0xe08e, 0x3fff, 0xe08e, 0x21, 0 + .dw 0x4400, 0xe08e, 0x4fff, 0xe08e, 0x21, 0 + .dw 0x5400, 0xe08e, 0x5fff, 0xe08e, 0x21, 0 + .dw 0x6400, 0xe08e, 0x6fff, 0xe08e, 0x21, 0 + .dw 0x7400, 0xe08e, 0xffff, 0xe08e, 0x21, 0 + .dw 0x0400, 0xe08f, 0x0fff, 0xe08f, 0x21, 0 + .dw 0x1400, 0xe08f, 0x1fff, 0xe08f, 0x21, 0 + .dw 0x2400, 0xe08f, 0x2fff, 0xe08f, 0x21, 0 + .dw 0x3400, 0xe08f, 0x3fff, 0xe08f, 0x21, 0 + .dw 0x4400, 0xe08f, 0x4fff, 0xe08f, 0x21, 0 + .dw 0x5400, 0xe08f, 0x5fff, 0xe08f, 0x21, 0 + .dw 0x6400, 0xe08f, 0x6fff, 0xe08f, 0x21, 0 + .dw 0x7400, 0xe08f, 0xffff, 0xe08f, 0x21, 0 + .dw 0x0400, 0xe090, 0x0fff, 0xe090, 0x21, 0 + .dw 0x1400, 0xe090, 0x1fff, 0xe090, 0x21, 0 + .dw 0x2400, 0xe090, 0x2fff, 0xe090, 0x21, 0 + .dw 0x3400, 0xe090, 0x3fff, 0xe090, 0x21, 0 + .dw 0x4400, 0xe090, 0x4fff, 0xe090, 0x21, 0 + .dw 0x5400, 0xe090, 0x5fff, 0xe090, 0x21, 0 + .dw 0x6400, 0xe090, 0x6fff, 0xe090, 0x21, 0 + .dw 0x7400, 0xe090, 0xffff, 0xe090, 0x21, 0 + .dw 0x0400, 0xe091, 0x0fff, 0xe091, 0x21, 0 + .dw 0x1400, 0xe091, 0x1fff, 0xe091, 0x21, 0 + .dw 0x2400, 0xe091, 0x2fff, 0xe091, 0x21, 0 + .dw 0x3400, 0xe091, 0x3fff, 0xe091, 0x21, 0 + .dw 0x4400, 0xe091, 0x4fff, 0xe091, 0x21, 0 + .dw 0x5400, 0xe091, 0x5fff, 0xe091, 0x21, 0 + .dw 0x6400, 0xe091, 0x6fff, 0xe091, 0x21, 0 + .dw 0x7400, 0xe091, 0xffff, 0xe091, 0x21, 0 + .dw 0x0400, 0xe092, 0x0fff, 0xe092, 0x21, 0 + .dw 0x1400, 0xe092, 0x1fff, 0xe092, 0x21, 0 + .dw 0x2400, 0xe092, 0x2fff, 0xe092, 0x21, 0 + .dw 0x3400, 0xe092, 0x3fff, 0xe092, 0x21, 0 + .dw 0x4400, 0xe092, 0x4fff, 0xe092, 0x21, 0 + .dw 0x5400, 0xe092, 0x5fff, 0xe092, 0x21, 0 + .dw 0x6400, 0xe092, 0x6fff, 0xe092, 0x21, 0 + .dw 0x7400, 0xe092, 0xffff, 0xe092, 0x21, 0 + .dw 0x0400, 0xe093, 0x0fff, 0xe093, 0x21, 0 + .dw 0x1400, 0xe093, 0x1fff, 0xe093, 0x21, 0 + .dw 0x2400, 0xe093, 0x2fff, 0xe093, 0x21, 0 + .dw 0x3400, 0xe093, 0x3fff, 0xe093, 0x21, 0 + .dw 0x4400, 0xe093, 0x4fff, 0xe093, 0x21, 0 + .dw 0x5400, 0xe093, 0x5fff, 0xe093, 0x21, 0 + .dw 0x6400, 0xe093, 0x6fff, 0xe093, 0x21, 0 + .dw 0x7400, 0xe093, 0xffff, 0xe093, 0x21, 0 + .dw 0x0400, 0xe094, 0x0fff, 0xe094, 0x21, 0 + .dw 0x1400, 0xe094, 0x1fff, 0xe094, 0x21, 0 + .dw 0x2400, 0xe094, 0x2fff, 0xe094, 0x21, 0 + .dw 0x3400, 0xe094, 0x3fff, 0xe094, 0x21, 0 + .dw 0x4400, 0xe094, 0x4fff, 0xe094, 0x21, 0 + .dw 0x5400, 0xe094, 0x5fff, 0xe094, 0x21, 0 + .dw 0x6400, 0xe094, 0x6fff, 0xe094, 0x21, 0 + .dw 0x7400, 0xe094, 0xffff, 0xe094, 0x21, 0 + .dw 0x0400, 0xe095, 0x0fff, 0xe095, 0x21, 0 + .dw 0x1400, 0xe095, 0x1fff, 0xe095, 0x21, 0 + .dw 0x2400, 0xe095, 0x2fff, 0xe095, 0x21, 0 + .dw 0x3400, 0xe095, 0x3fff, 0xe095, 0x21, 0 + .dw 0x4400, 0xe095, 0x4fff, 0xe095, 0x21, 0 + .dw 0x5400, 0xe095, 0x5fff, 0xe095, 0x21, 0 + .dw 0x6400, 0xe095, 0x6fff, 0xe095, 0x21, 0 + .dw 0x7400, 0xe095, 0xffff, 0xe095, 0x21, 0 + .dw 0x0400, 0xe096, 0x0fff, 0xe096, 0x21, 0 + .dw 0x1400, 0xe096, 0x1fff, 0xe096, 0x21, 0 + .dw 0x2400, 0xe096, 0x2fff, 0xe096, 0x21, 0 + .dw 0x3400, 0xe096, 0x3fff, 0xe096, 0x21, 0 + .dw 0x4400, 0xe096, 0x4fff, 0xe096, 0x21, 0 + .dw 0x5400, 0xe096, 0x5fff, 0xe096, 0x21, 0 + .dw 0x6400, 0xe096, 0x6fff, 0xe096, 0x21, 0 + .dw 0x7400, 0xe096, 0xffff, 0xe096, 0x21, 0 + .dw 0x0400, 0xe097, 0x0fff, 0xe097, 0x21, 0 + .dw 0x1400, 0xe097, 0x1fff, 0xe097, 0x21, 0 + .dw 0x2400, 0xe097, 0x2fff, 0xe097, 0x21, 0 + .dw 0x3400, 0xe097, 0x3fff, 0xe097, 0x21, 0 + .dw 0x4400, 0xe097, 0x4fff, 0xe097, 0x21, 0 + .dw 0x5400, 0xe097, 0x5fff, 0xe097, 0x21, 0 + .dw 0x6400, 0xe097, 0x6fff, 0xe097, 0x21, 0 + .dw 0x7400, 0xe097, 0xffff, 0xe097, 0x21, 0 + .dw 0x0400, 0xe098, 0x0fff, 0xe098, 0x21, 0 + .dw 0x1400, 0xe098, 0x1fff, 0xe098, 0x21, 0 + .dw 0x2400, 0xe098, 0x2fff, 0xe098, 0x21, 0 + .dw 0x3400, 0xe098, 0x3fff, 0xe098, 0x21, 0 + .dw 0x4400, 0xe098, 0x4fff, 0xe098, 0x21, 0 + .dw 0x5400, 0xe098, 0x5fff, 0xe098, 0x21, 0 + .dw 0x6400, 0xe098, 0x6fff, 0xe098, 0x21, 0 + .dw 0x7400, 0xe098, 0xffff, 0xe098, 0x21, 0 + .dw 0x0400, 0xe099, 0x0fff, 0xe099, 0x21, 0 + .dw 0x1400, 0xe099, 0x1fff, 0xe099, 0x21, 0 + .dw 0x2400, 0xe099, 0x2fff, 0xe099, 0x21, 0 + .dw 0x3400, 0xe099, 0x3fff, 0xe099, 0x21, 0 + .dw 0x4400, 0xe099, 0x4fff, 0xe099, 0x21, 0 + .dw 0x5400, 0xe099, 0x5fff, 0xe099, 0x21, 0 + .dw 0x6400, 0xe099, 0x6fff, 0xe099, 0x21, 0 + .dw 0x7400, 0xe099, 0xffff, 0xe099, 0x21, 0 + .dw 0x0400, 0xe09a, 0x0fff, 0xe09a, 0x21, 0 + .dw 0x1400, 0xe09a, 0x1fff, 0xe09a, 0x21, 0 + .dw 0x2400, 0xe09a, 0x2fff, 0xe09a, 0x21, 0 + .dw 0x3400, 0xe09a, 0x3fff, 0xe09a, 0x21, 0 + .dw 0x4400, 0xe09a, 0x4fff, 0xe09a, 0x21, 0 + .dw 0x5400, 0xe09a, 0x5fff, 0xe09a, 0x21, 0 + .dw 0x6400, 0xe09a, 0x6fff, 0xe09a, 0x21, 0 + .dw 0x7400, 0xe09a, 0xffff, 0xe09a, 0x21, 0 + .dw 0x0400, 0xe09b, 0x0fff, 0xe09b, 0x21, 0 + .dw 0x1400, 0xe09b, 0x1fff, 0xe09b, 0x21, 0 + .dw 0x2400, 0xe09b, 0x2fff, 0xe09b, 0x21, 0 + .dw 0x3400, 0xe09b, 0x3fff, 0xe09b, 0x21, 0 + .dw 0x4400, 0xe09b, 0x4fff, 0xe09b, 0x21, 0 + .dw 0x5400, 0xe09b, 0x5fff, 0xe09b, 0x21, 0 + .dw 0x6400, 0xe09b, 0x6fff, 0xe09b, 0x21, 0 + .dw 0x7400, 0xe09b, 0xffff, 0xe09b, 0x21, 0 + .dw 0x0400, 0xe09c, 0x0fff, 0xe09c, 0x21, 0 + .dw 0x1400, 0xe09c, 0x1fff, 0xe09c, 0x21, 0 + .dw 0x2400, 0xe09c, 0x2fff, 0xe09c, 0x21, 0 + .dw 0x3400, 0xe09c, 0x3fff, 0xe09c, 0x21, 0 + .dw 0x4400, 0xe09c, 0x4fff, 0xe09c, 0x21, 0 + .dw 0x5400, 0xe09c, 0x5fff, 0xe09c, 0x21, 0 + .dw 0x6400, 0xe09c, 0x6fff, 0xe09c, 0x21, 0 + .dw 0x7400, 0xe09c, 0xffff, 0xe09c, 0x21, 0 + .dw 0x0400, 0xe09d, 0x0fff, 0xe09d, 0x21, 0 + .dw 0x1400, 0xe09d, 0x1fff, 0xe09d, 0x21, 0 + .dw 0x2400, 0xe09d, 0x2fff, 0xe09d, 0x21, 0 + .dw 0x3400, 0xe09d, 0x3fff, 0xe09d, 0x21, 0 + .dw 0x4400, 0xe09d, 0x4fff, 0xe09d, 0x21, 0 + .dw 0x5400, 0xe09d, 0x5fff, 0xe09d, 0x21, 0 + .dw 0x6400, 0xe09d, 0x6fff, 0xe09d, 0x21, 0 + .dw 0x7400, 0xe09d, 0xffff, 0xe09d, 0x21, 0 + .dw 0x0400, 0xe09e, 0x0fff, 0xe09e, 0x21, 0 + .dw 0x1400, 0xe09e, 0x1fff, 0xe09e, 0x21, 0 + .dw 0x2400, 0xe09e, 0x2fff, 0xe09e, 0x21, 0 + .dw 0x3400, 0xe09e, 0x3fff, 0xe09e, 0x21, 0 + .dw 0x4400, 0xe09e, 0x4fff, 0xe09e, 0x21, 0 + .dw 0x5400, 0xe09e, 0x5fff, 0xe09e, 0x21, 0 + .dw 0x6400, 0xe09e, 0x6fff, 0xe09e, 0x21, 0 + .dw 0x7400, 0xe09e, 0xffff, 0xe09e, 0x21, 0 + .dw 0x0400, 0xe09f, 0x0fff, 0xe09f, 0x21, 0 + .dw 0x1400, 0xe09f, 0x1fff, 0xe09f, 0x21, 0 + .dw 0x2400, 0xe09f, 0x2fff, 0xe09f, 0x21, 0 + .dw 0x3400, 0xe09f, 0x3fff, 0xe09f, 0x21, 0 + .dw 0x4400, 0xe09f, 0x4fff, 0xe09f, 0x21, 0 + .dw 0x5400, 0xe09f, 0x5fff, 0xe09f, 0x21, 0 + .dw 0x6400, 0xe09f, 0x6fff, 0xe09f, 0x21, 0 + .dw 0x7400, 0xe09f, 0xffff, 0xe09f, 0x21, 0 + .dw 0x0400, 0xe0a0, 0x0fff, 0xe0a0, 0x21, 0 + .dw 0x1400, 0xe0a0, 0x1fff, 0xe0a0, 0x21, 0 + .dw 0x2400, 0xe0a0, 0x2fff, 0xe0a0, 0x21, 0 + .dw 0x3400, 0xe0a0, 0x3fff, 0xe0a0, 0x21, 0 + .dw 0x4400, 0xe0a0, 0x4fff, 0xe0a0, 0x21, 0 + .dw 0x5400, 0xe0a0, 0x5fff, 0xe0a0, 0x21, 0 + .dw 0x6400, 0xe0a0, 0x6fff, 0xe0a0, 0x21, 0 + .dw 0x7400, 0xe0a0, 0xffff, 0xe0a0, 0x21, 0 + .dw 0x0400, 0xe0a1, 0x0fff, 0xe0a1, 0x21, 0 + .dw 0x1400, 0xe0a1, 0x1fff, 0xe0a1, 0x21, 0 + .dw 0x2400, 0xe0a1, 0x2fff, 0xe0a1, 0x21, 0 + .dw 0x3400, 0xe0a1, 0x3fff, 0xe0a1, 0x21, 0 + .dw 0x4400, 0xe0a1, 0x4fff, 0xe0a1, 0x21, 0 + .dw 0x5400, 0xe0a1, 0x5fff, 0xe0a1, 0x21, 0 + .dw 0x6400, 0xe0a1, 0x6fff, 0xe0a1, 0x21, 0 + .dw 0x7400, 0xe0a1, 0xffff, 0xe0a1, 0x21, 0 + .dw 0x0400, 0xe0a2, 0x0fff, 0xe0a2, 0x21, 0 + .dw 0x1400, 0xe0a2, 0x1fff, 0xe0a2, 0x21, 0 + .dw 0x2400, 0xe0a2, 0x2fff, 0xe0a2, 0x21, 0 + .dw 0x3400, 0xe0a2, 0x3fff, 0xe0a2, 0x21, 0 + .dw 0x4400, 0xe0a2, 0x4fff, 0xe0a2, 0x21, 0 + .dw 0x5400, 0xe0a2, 0x5fff, 0xe0a2, 0x21, 0 + .dw 0x6400, 0xe0a2, 0x6fff, 0xe0a2, 0x21, 0 + .dw 0x7400, 0xe0a2, 0xffff, 0xe0a2, 0x21, 0 + .dw 0x0400, 0xe0a3, 0x0fff, 0xe0a3, 0x21, 0 + .dw 0x1400, 0xe0a3, 0x1fff, 0xe0a3, 0x21, 0 + .dw 0x2400, 0xe0a3, 0x2fff, 0xe0a3, 0x21, 0 + .dw 0x3400, 0xe0a3, 0x3fff, 0xe0a3, 0x21, 0 + .dw 0x4400, 0xe0a3, 0x4fff, 0xe0a3, 0x21, 0 + .dw 0x5400, 0xe0a3, 0x5fff, 0xe0a3, 0x21, 0 + .dw 0x6400, 0xe0a3, 0x6fff, 0xe0a3, 0x21, 0 + .dw 0x7400, 0xe0a3, 0xffff, 0xe0a3, 0x21, 0 + .dw 0x0400, 0xe0a4, 0x0fff, 0xe0a4, 0x21, 0 + .dw 0x1400, 0xe0a4, 0x1fff, 0xe0a4, 0x21, 0 + .dw 0x2400, 0xe0a4, 0x2fff, 0xe0a4, 0x21, 0 + .dw 0x3400, 0xe0a4, 0x3fff, 0xe0a4, 0x21, 0 + .dw 0x4400, 0xe0a4, 0x4fff, 0xe0a4, 0x21, 0 + .dw 0x5400, 0xe0a4, 0x5fff, 0xe0a4, 0x21, 0 + .dw 0x6400, 0xe0a4, 0x6fff, 0xe0a4, 0x21, 0 + .dw 0x7400, 0xe0a4, 0xffff, 0xe0a4, 0x21, 0 + .dw 0x0400, 0xe0a5, 0x0fff, 0xe0a5, 0x21, 0 + .dw 0x1400, 0xe0a5, 0x1fff, 0xe0a5, 0x21, 0 + .dw 0x2400, 0xe0a5, 0x2fff, 0xe0a5, 0x21, 0 + .dw 0x3400, 0xe0a5, 0x3fff, 0xe0a5, 0x21, 0 + .dw 0x4400, 0xe0a5, 0x4fff, 0xe0a5, 0x21, 0 + .dw 0x5400, 0xe0a5, 0x5fff, 0xe0a5, 0x21, 0 + .dw 0x6400, 0xe0a5, 0x6fff, 0xe0a5, 0x21, 0 + .dw 0x7400, 0xe0a5, 0xffff, 0xe0a5, 0x21, 0 + .dw 0x0400, 0xe0a6, 0x0fff, 0xe0a6, 0x21, 0 + .dw 0x1400, 0xe0a6, 0x1fff, 0xe0a6, 0x21, 0 + .dw 0x2400, 0xe0a6, 0x2fff, 0xe0a6, 0x21, 0 + .dw 0x3400, 0xe0a6, 0x3fff, 0xe0a6, 0x21, 0 + .dw 0x4400, 0xe0a6, 0x4fff, 0xe0a6, 0x21, 0 + .dw 0x5400, 0xe0a6, 0x5fff, 0xe0a6, 0x21, 0 + .dw 0x6400, 0xe0a6, 0x6fff, 0xe0a6, 0x21, 0 + .dw 0x7400, 0xe0a6, 0xffff, 0xe0a6, 0x21, 0 + .dw 0x0400, 0xe0a7, 0x0fff, 0xe0a7, 0x21, 0 + .dw 0x1400, 0xe0a7, 0x1fff, 0xe0a7, 0x21, 0 + .dw 0x2400, 0xe0a7, 0x2fff, 0xe0a7, 0x21, 0 + .dw 0x3400, 0xe0a7, 0x3fff, 0xe0a7, 0x21, 0 + .dw 0x4400, 0xe0a7, 0x4fff, 0xe0a7, 0x21, 0 + .dw 0x5400, 0xe0a7, 0x5fff, 0xe0a7, 0x21, 0 + .dw 0x6400, 0xe0a7, 0x6fff, 0xe0a7, 0x21, 0 + .dw 0x7400, 0xe0a7, 0xffff, 0xe0a7, 0x21, 0 + .dw 0x0400, 0xe0a8, 0x0fff, 0xe0a8, 0x21, 0 + .dw 0x1400, 0xe0a8, 0x1fff, 0xe0a8, 0x21, 0 + .dw 0x2400, 0xe0a8, 0x2fff, 0xe0a8, 0x21, 0 + .dw 0x3400, 0xe0a8, 0x3fff, 0xe0a8, 0x21, 0 + .dw 0x4400, 0xe0a8, 0x4fff, 0xe0a8, 0x21, 0 + .dw 0x5400, 0xe0a8, 0x5fff, 0xe0a8, 0x21, 0 + .dw 0x6400, 0xe0a8, 0x6fff, 0xe0a8, 0x21, 0 + .dw 0x7400, 0xe0a8, 0xffff, 0xe0a8, 0x21, 0 + .dw 0x0400, 0xe0a9, 0x0fff, 0xe0a9, 0x21, 0 + .dw 0x1400, 0xe0a9, 0x1fff, 0xe0a9, 0x21, 0 + .dw 0x2400, 0xe0a9, 0x2fff, 0xe0a9, 0x21, 0 + .dw 0x3400, 0xe0a9, 0x3fff, 0xe0a9, 0x21, 0 + .dw 0x4400, 0xe0a9, 0x4fff, 0xe0a9, 0x21, 0 + .dw 0x5400, 0xe0a9, 0x5fff, 0xe0a9, 0x21, 0 + .dw 0x6400, 0xe0a9, 0x6fff, 0xe0a9, 0x21, 0 + .dw 0x7400, 0xe0a9, 0xffff, 0xe0a9, 0x21, 0 + .dw 0x0400, 0xe0aa, 0x0fff, 0xe0aa, 0x21, 0 + .dw 0x1400, 0xe0aa, 0x1fff, 0xe0aa, 0x21, 0 + .dw 0x2400, 0xe0aa, 0x2fff, 0xe0aa, 0x21, 0 + .dw 0x3400, 0xe0aa, 0x3fff, 0xe0aa, 0x21, 0 + .dw 0x4400, 0xe0aa, 0x4fff, 0xe0aa, 0x21, 0 + .dw 0x5400, 0xe0aa, 0x5fff, 0xe0aa, 0x21, 0 + .dw 0x6400, 0xe0aa, 0x6fff, 0xe0aa, 0x21, 0 + .dw 0x7400, 0xe0aa, 0xffff, 0xe0aa, 0x21, 0 + .dw 0x0400, 0xe0ab, 0x0fff, 0xe0ab, 0x21, 0 + .dw 0x1400, 0xe0ab, 0x1fff, 0xe0ab, 0x21, 0 + .dw 0x2400, 0xe0ab, 0x2fff, 0xe0ab, 0x21, 0 + .dw 0x3400, 0xe0ab, 0x3fff, 0xe0ab, 0x21, 0 + .dw 0x4400, 0xe0ab, 0x4fff, 0xe0ab, 0x21, 0 + .dw 0x5400, 0xe0ab, 0x5fff, 0xe0ab, 0x21, 0 + .dw 0x6400, 0xe0ab, 0x6fff, 0xe0ab, 0x21, 0 + .dw 0x7400, 0xe0ab, 0xffff, 0xe0ab, 0x21, 0 + .dw 0x0400, 0xe0ac, 0x0fff, 0xe0ac, 0x21, 0 + .dw 0x1400, 0xe0ac, 0x1fff, 0xe0ac, 0x21, 0 + .dw 0x2400, 0xe0ac, 0x2fff, 0xe0ac, 0x21, 0 + .dw 0x3400, 0xe0ac, 0x3fff, 0xe0ac, 0x21, 0 + .dw 0x4400, 0xe0ac, 0x4fff, 0xe0ac, 0x21, 0 + .dw 0x5400, 0xe0ac, 0x5fff, 0xe0ac, 0x21, 0 + .dw 0x6400, 0xe0ac, 0x6fff, 0xe0ac, 0x21, 0 + .dw 0x7400, 0xe0ac, 0xffff, 0xe0ac, 0x21, 0 + .dw 0x0400, 0xe0ad, 0x0fff, 0xe0ad, 0x21, 0 + .dw 0x1400, 0xe0ad, 0x1fff, 0xe0ad, 0x21, 0 + .dw 0x2400, 0xe0ad, 0x2fff, 0xe0ad, 0x21, 0 + .dw 0x3400, 0xe0ad, 0x3fff, 0xe0ad, 0x21, 0 + .dw 0x4400, 0xe0ad, 0x4fff, 0xe0ad, 0x21, 0 + .dw 0x5400, 0xe0ad, 0x5fff, 0xe0ad, 0x21, 0 + .dw 0x6400, 0xe0ad, 0x6fff, 0xe0ad, 0x21, 0 + .dw 0x7400, 0xe0ad, 0xffff, 0xe0ad, 0x21, 0 + .dw 0x0400, 0xe0ae, 0x0fff, 0xe0ae, 0x21, 0 + .dw 0x1400, 0xe0ae, 0x1fff, 0xe0ae, 0x21, 0 + .dw 0x2400, 0xe0ae, 0x2fff, 0xe0ae, 0x21, 0 + .dw 0x3400, 0xe0ae, 0x3fff, 0xe0ae, 0x21, 0 + .dw 0x4400, 0xe0ae, 0x4fff, 0xe0ae, 0x21, 0 + .dw 0x5400, 0xe0ae, 0x5fff, 0xe0ae, 0x21, 0 + .dw 0x6400, 0xe0ae, 0x6fff, 0xe0ae, 0x21, 0 + .dw 0x7400, 0xe0ae, 0xffff, 0xe0ae, 0x21, 0 + .dw 0x0400, 0xe0af, 0x0fff, 0xe0af, 0x21, 0 + .dw 0x1400, 0xe0af, 0x1fff, 0xe0af, 0x21, 0 + .dw 0x2400, 0xe0af, 0x2fff, 0xe0af, 0x21, 0 + .dw 0x3400, 0xe0af, 0x3fff, 0xe0af, 0x21, 0 + .dw 0x4400, 0xe0af, 0x4fff, 0xe0af, 0x21, 0 + .dw 0x5400, 0xe0af, 0x5fff, 0xe0af, 0x21, 0 + .dw 0x6400, 0xe0af, 0x6fff, 0xe0af, 0x21, 0 + .dw 0x7400, 0xe0af, 0xffff, 0xe0af, 0x21, 0 + .dw 0x0400, 0xe0b0, 0x0fff, 0xe0b0, 0x21, 0 + .dw 0x1400, 0xe0b0, 0x1fff, 0xe0b0, 0x21, 0 + .dw 0x2400, 0xe0b0, 0x2fff, 0xe0b0, 0x21, 0 + .dw 0x3400, 0xe0b0, 0x3fff, 0xe0b0, 0x21, 0 + .dw 0x4400, 0xe0b0, 0x4fff, 0xe0b0, 0x21, 0 + .dw 0x5400, 0xe0b0, 0x5fff, 0xe0b0, 0x21, 0 + .dw 0x6400, 0xe0b0, 0x6fff, 0xe0b0, 0x21, 0 + .dw 0x7400, 0xe0b0, 0xffff, 0xe0b0, 0x21, 0 + .dw 0x0400, 0xe0b1, 0x0fff, 0xe0b1, 0x21, 0 + .dw 0x1400, 0xe0b1, 0x1fff, 0xe0b1, 0x21, 0 + .dw 0x2400, 0xe0b1, 0x2fff, 0xe0b1, 0x21, 0 + .dw 0x3400, 0xe0b1, 0x3fff, 0xe0b1, 0x21, 0 + .dw 0x4400, 0xe0b1, 0x4fff, 0xe0b1, 0x21, 0 + .dw 0x5400, 0xe0b1, 0x5fff, 0xe0b1, 0x21, 0 + .dw 0x6400, 0xe0b1, 0x6fff, 0xe0b1, 0x21, 0 + .dw 0x7400, 0xe0b1, 0xffff, 0xe0b1, 0x21, 0 + .dw 0x0400, 0xe0b2, 0x0fff, 0xe0b2, 0x21, 0 + .dw 0x1400, 0xe0b2, 0x1fff, 0xe0b2, 0x21, 0 + .dw 0x2400, 0xe0b2, 0x2fff, 0xe0b2, 0x21, 0 + .dw 0x3400, 0xe0b2, 0x3fff, 0xe0b2, 0x21, 0 + .dw 0x4400, 0xe0b2, 0x4fff, 0xe0b2, 0x21, 0 + .dw 0x5400, 0xe0b2, 0x5fff, 0xe0b2, 0x21, 0 + .dw 0x6400, 0xe0b2, 0x6fff, 0xe0b2, 0x21, 0 + .dw 0x7400, 0xe0b2, 0xffff, 0xe0b2, 0x21, 0 + .dw 0x0400, 0xe0b3, 0x0fff, 0xe0b3, 0x21, 0 + .dw 0x1400, 0xe0b3, 0x1fff, 0xe0b3, 0x21, 0 + .dw 0x2400, 0xe0b3, 0x2fff, 0xe0b3, 0x21, 0 + .dw 0x3400, 0xe0b3, 0x3fff, 0xe0b3, 0x21, 0 + .dw 0x4400, 0xe0b3, 0x4fff, 0xe0b3, 0x21, 0 + .dw 0x5400, 0xe0b3, 0x5fff, 0xe0b3, 0x21, 0 + .dw 0x6400, 0xe0b3, 0x6fff, 0xe0b3, 0x21, 0 + .dw 0x7400, 0xe0b3, 0xffff, 0xe0b3, 0x21, 0 + .dw 0x0400, 0xe0b4, 0x0fff, 0xe0b4, 0x21, 0 + .dw 0x1400, 0xe0b4, 0x1fff, 0xe0b4, 0x21, 0 + .dw 0x2400, 0xe0b4, 0x2fff, 0xe0b4, 0x21, 0 + .dw 0x3400, 0xe0b4, 0x3fff, 0xe0b4, 0x21, 0 + .dw 0x4400, 0xe0b4, 0x4fff, 0xe0b4, 0x21, 0 + .dw 0x5400, 0xe0b4, 0x5fff, 0xe0b4, 0x21, 0 + .dw 0x6400, 0xe0b4, 0x6fff, 0xe0b4, 0x21, 0 + .dw 0x7400, 0xe0b4, 0xffff, 0xe0b4, 0x21, 0 + .dw 0x0400, 0xe0b5, 0x0fff, 0xe0b5, 0x21, 0 + .dw 0x1400, 0xe0b5, 0x1fff, 0xe0b5, 0x21, 0 + .dw 0x2400, 0xe0b5, 0x2fff, 0xe0b5, 0x21, 0 + .dw 0x3400, 0xe0b5, 0x3fff, 0xe0b5, 0x21, 0 + .dw 0x4400, 0xe0b5, 0x4fff, 0xe0b5, 0x21, 0 + .dw 0x5400, 0xe0b5, 0x5fff, 0xe0b5, 0x21, 0 + .dw 0x6400, 0xe0b5, 0x6fff, 0xe0b5, 0x21, 0 + .dw 0x7400, 0xe0b5, 0xffff, 0xe0b5, 0x21, 0 + .dw 0x0400, 0xe0b6, 0x0fff, 0xe0b6, 0x21, 0 + .dw 0x1400, 0xe0b6, 0x1fff, 0xe0b6, 0x21, 0 + .dw 0x2400, 0xe0b6, 0x2fff, 0xe0b6, 0x21, 0 + .dw 0x3400, 0xe0b6, 0x3fff, 0xe0b6, 0x21, 0 + .dw 0x4400, 0xe0b6, 0x4fff, 0xe0b6, 0x21, 0 + .dw 0x5400, 0xe0b6, 0x5fff, 0xe0b6, 0x21, 0 + .dw 0x6400, 0xe0b6, 0x6fff, 0xe0b6, 0x21, 0 + .dw 0x7400, 0xe0b6, 0xffff, 0xe0b6, 0x21, 0 + .dw 0x0400, 0xe0b7, 0x0fff, 0xe0b7, 0x21, 0 + .dw 0x1400, 0xe0b7, 0x1fff, 0xe0b7, 0x21, 0 + .dw 0x2400, 0xe0b7, 0x2fff, 0xe0b7, 0x21, 0 + .dw 0x3400, 0xe0b7, 0x3fff, 0xe0b7, 0x21, 0 + .dw 0x4400, 0xe0b7, 0x4fff, 0xe0b7, 0x21, 0 + .dw 0x5400, 0xe0b7, 0x5fff, 0xe0b7, 0x21, 0 + .dw 0x6400, 0xe0b7, 0x6fff, 0xe0b7, 0x21, 0 + .dw 0x7400, 0xe0b7, 0xffff, 0xe0b7, 0x21, 0 + .dw 0x0400, 0xe0b8, 0x0fff, 0xe0b8, 0x21, 0 + .dw 0x1400, 0xe0b8, 0x1fff, 0xe0b8, 0x21, 0 + .dw 0x2400, 0xe0b8, 0x2fff, 0xe0b8, 0x21, 0 + .dw 0x3400, 0xe0b8, 0x3fff, 0xe0b8, 0x21, 0 + .dw 0x4400, 0xe0b8, 0x4fff, 0xe0b8, 0x21, 0 + .dw 0x5400, 0xe0b8, 0x5fff, 0xe0b8, 0x21, 0 + .dw 0x6400, 0xe0b8, 0x6fff, 0xe0b8, 0x21, 0 + .dw 0x7400, 0xe0b8, 0xffff, 0xe0b8, 0x21, 0 + .dw 0x0400, 0xe0b9, 0x0fff, 0xe0b9, 0x21, 0 + .dw 0x1400, 0xe0b9, 0x1fff, 0xe0b9, 0x21, 0 + .dw 0x2400, 0xe0b9, 0x2fff, 0xe0b9, 0x21, 0 + .dw 0x3400, 0xe0b9, 0x3fff, 0xe0b9, 0x21, 0 + .dw 0x4400, 0xe0b9, 0x4fff, 0xe0b9, 0x21, 0 + .dw 0x5400, 0xe0b9, 0x5fff, 0xe0b9, 0x21, 0 + .dw 0x6400, 0xe0b9, 0x6fff, 0xe0b9, 0x21, 0 + .dw 0x7400, 0xe0b9, 0xffff, 0xe0b9, 0x21, 0 + .dw 0x0400, 0xe0ba, 0x0fff, 0xe0ba, 0x21, 0 + .dw 0x1400, 0xe0ba, 0x1fff, 0xe0ba, 0x21, 0 + .dw 0x2400, 0xe0ba, 0x2fff, 0xe0ba, 0x21, 0 + .dw 0x3400, 0xe0ba, 0x3fff, 0xe0ba, 0x21, 0 + .dw 0x4400, 0xe0ba, 0x4fff, 0xe0ba, 0x21, 0 + .dw 0x5400, 0xe0ba, 0x5fff, 0xe0ba, 0x21, 0 + .dw 0x6400, 0xe0ba, 0x6fff, 0xe0ba, 0x21, 0 + .dw 0x7400, 0xe0ba, 0xffff, 0xe0ba, 0x21, 0 + .dw 0x0400, 0xe0bb, 0x0fff, 0xe0bb, 0x21, 0 + .dw 0x1400, 0xe0bb, 0x1fff, 0xe0bb, 0x21, 0 + .dw 0x2400, 0xe0bb, 0x2fff, 0xe0bb, 0x21, 0 + .dw 0x3400, 0xe0bb, 0x3fff, 0xe0bb, 0x21, 0 + .dw 0x4400, 0xe0bb, 0x4fff, 0xe0bb, 0x21, 0 + .dw 0x5400, 0xe0bb, 0x5fff, 0xe0bb, 0x21, 0 + .dw 0x6400, 0xe0bb, 0x6fff, 0xe0bb, 0x21, 0 + .dw 0x7400, 0xe0bb, 0xffff, 0xe0bb, 0x21, 0 + .dw 0x0400, 0xe0bc, 0x0fff, 0xe0bc, 0x21, 0 + .dw 0x1400, 0xe0bc, 0x1fff, 0xe0bc, 0x21, 0 + .dw 0x2400, 0xe0bc, 0x2fff, 0xe0bc, 0x21, 0 + .dw 0x3400, 0xe0bc, 0x3fff, 0xe0bc, 0x21, 0 + .dw 0x4400, 0xe0bc, 0x4fff, 0xe0bc, 0x21, 0 + .dw 0x5400, 0xe0bc, 0x5fff, 0xe0bc, 0x21, 0 + .dw 0x6400, 0xe0bc, 0x6fff, 0xe0bc, 0x21, 0 + .dw 0x7400, 0xe0bc, 0xffff, 0xe0bc, 0x21, 0 + .dw 0x0400, 0xe0bd, 0x0fff, 0xe0bd, 0x21, 0 + .dw 0x1400, 0xe0bd, 0x1fff, 0xe0bd, 0x21, 0 + .dw 0x2400, 0xe0bd, 0x2fff, 0xe0bd, 0x21, 0 + .dw 0x3400, 0xe0bd, 0x3fff, 0xe0bd, 0x21, 0 + .dw 0x4400, 0xe0bd, 0x4fff, 0xe0bd, 0x21, 0 + .dw 0x5400, 0xe0bd, 0x5fff, 0xe0bd, 0x21, 0 + .dw 0x6400, 0xe0bd, 0x6fff, 0xe0bd, 0x21, 0 + .dw 0x7400, 0xe0bd, 0xffff, 0xe0bd, 0x21, 0 + .dw 0x0400, 0xe0be, 0x0fff, 0xe0be, 0x21, 0 + .dw 0x1400, 0xe0be, 0x1fff, 0xe0be, 0x21, 0 + .dw 0x2400, 0xe0be, 0x2fff, 0xe0be, 0x21, 0 + .dw 0x3400, 0xe0be, 0x3fff, 0xe0be, 0x21, 0 + .dw 0x4400, 0xe0be, 0x4fff, 0xe0be, 0x21, 0 + .dw 0x5400, 0xe0be, 0x5fff, 0xe0be, 0x21, 0 + .dw 0x6400, 0xe0be, 0x6fff, 0xe0be, 0x21, 0 + .dw 0x7400, 0xe0be, 0xffff, 0xe0be, 0x21, 0 + .dw 0x0400, 0xe0bf, 0x0fff, 0xe0bf, 0x21, 0 + .dw 0x1400, 0xe0bf, 0x1fff, 0xe0bf, 0x21, 0 + .dw 0x2400, 0xe0bf, 0x2fff, 0xe0bf, 0x21, 0 + .dw 0x3400, 0xe0bf, 0x3fff, 0xe0bf, 0x21, 0 + .dw 0x4400, 0xe0bf, 0x4fff, 0xe0bf, 0x21, 0 + .dw 0x5400, 0xe0bf, 0x5fff, 0xe0bf, 0x21, 0 + .dw 0x6400, 0xe0bf, 0x6fff, 0xe0bf, 0x21, 0 + .dw 0x7400, 0xe0bf, 0xffff, 0xe0df, 0x21, 0 + .dw 0x0400, 0xe0e0, 0x0fff, 0xe0e0, 0x21, 0 + .dw 0x1400, 0xe0e0, 0x1fff, 0xe0e0, 0x21, 0 + .dw 0x2400, 0xe0e0, 0x2fff, 0xe0e0, 0x21, 0 + .dw 0x3400, 0xe0e0, 0x3fff, 0xe0e0, 0x21, 0 + .dw 0x4400, 0xe0e0, 0x4fff, 0xe0e0, 0x21, 0 + .dw 0x5400, 0xe0e0, 0x5fff, 0xe0e0, 0x21, 0 + .dw 0x6400, 0xe0e0, 0x6fff, 0xe0e0, 0x21, 0 + .dw 0x7400, 0xe0e0, 0xffff, 0xe0e0, 0x21, 0 + .dw 0x0400, 0xe0e1, 0x0fff, 0xe0e1, 0x21, 0 + .dw 0x1400, 0xe0e1, 0x1fff, 0xe0e1, 0x21, 0 + .dw 0x2400, 0xe0e1, 0x2fff, 0xe0e1, 0x21, 0 + .dw 0x3400, 0xe0e1, 0x3fff, 0xe0e1, 0x21, 0 + .dw 0x4400, 0xe0e1, 0x4fff, 0xe0e1, 0x21, 0 + .dw 0x5400, 0xe0e1, 0x5fff, 0xe0e1, 0x21, 0 + .dw 0x6400, 0xe0e1, 0x6fff, 0xe0e1, 0x21, 0 + .dw 0x7400, 0xe0e1, 0xffff, 0xe0e1, 0x21, 0 + .dw 0x0400, 0xe0e2, 0x0fff, 0xe0e2, 0x21, 0 + .dw 0x1400, 0xe0e2, 0x1fff, 0xe0e2, 0x21, 0 + .dw 0x2400, 0xe0e2, 0x2fff, 0xe0e2, 0x21, 0 + .dw 0x3400, 0xe0e2, 0x3fff, 0xe0e2, 0x21, 0 + .dw 0x4400, 0xe0e2, 0x4fff, 0xe0e2, 0x21, 0 + .dw 0x5400, 0xe0e2, 0x5fff, 0xe0e2, 0x21, 0 + .dw 0x6400, 0xe0e2, 0x6fff, 0xe0e2, 0x21, 0 + .dw 0x7400, 0xe0e2, 0xffff, 0xe0e2, 0x21, 0 + .dw 0x0400, 0xe0e3, 0x0fff, 0xe0e3, 0x21, 0 + .dw 0x1400, 0xe0e3, 0x1fff, 0xe0e3, 0x21, 0 + .dw 0x2400, 0xe0e3, 0x2fff, 0xe0e3, 0x21, 0 + .dw 0x3400, 0xe0e3, 0x3fff, 0xe0e3, 0x21, 0 + .dw 0x4400, 0xe0e3, 0x4fff, 0xe0e3, 0x21, 0 + .dw 0x5400, 0xe0e3, 0x5fff, 0xe0e3, 0x21, 0 + .dw 0x6400, 0xe0e3, 0x6fff, 0xe0e3, 0x21, 0 + .dw 0x7400, 0xe0e3, 0xffff, 0xe0e3, 0x21, 0 + .dw 0x0400, 0xe0e4, 0x0fff, 0xe0e4, 0x21, 0 + .dw 0x1400, 0xe0e4, 0x1fff, 0xe0e4, 0x21, 0 + .dw 0x2400, 0xe0e4, 0x2fff, 0xe0e4, 0x21, 0 + .dw 0x3400, 0xe0e4, 0x3fff, 0xe0e4, 0x21, 0 + .dw 0x4400, 0xe0e4, 0x4fff, 0xe0e4, 0x21, 0 + .dw 0x5400, 0xe0e4, 0x5fff, 0xe0e4, 0x21, 0 + .dw 0x6400, 0xe0e4, 0x6fff, 0xe0e4, 0x21, 0 + .dw 0x7400, 0xe0e4, 0xffff, 0xe0e4, 0x21, 0 + .dw 0x0400, 0xe0e5, 0x0fff, 0xe0e5, 0x21, 0 + .dw 0x1400, 0xe0e5, 0x1fff, 0xe0e5, 0x21, 0 + .dw 0x2400, 0xe0e5, 0x2fff, 0xe0e5, 0x21, 0 + .dw 0x3400, 0xe0e5, 0x3fff, 0xe0e5, 0x21, 0 + .dw 0x4400, 0xe0e5, 0x4fff, 0xe0e5, 0x21, 0 + .dw 0x5400, 0xe0e5, 0x5fff, 0xe0e5, 0x21, 0 + .dw 0x6400, 0xe0e5, 0x6fff, 0xe0e5, 0x21, 0 + .dw 0x7400, 0xe0e5, 0xffff, 0xe0e5, 0x21, 0 + .dw 0x0400, 0xe0e6, 0x0fff, 0xe0e6, 0x21, 0 + .dw 0x1400, 0xe0e6, 0x1fff, 0xe0e6, 0x21, 0 + .dw 0x2400, 0xe0e6, 0x2fff, 0xe0e6, 0x21, 0 + .dw 0x3400, 0xe0e6, 0x3fff, 0xe0e6, 0x21, 0 + .dw 0x4400, 0xe0e6, 0x4fff, 0xe0e6, 0x21, 0 + .dw 0x5400, 0xe0e6, 0x5fff, 0xe0e6, 0x21, 0 + .dw 0x6400, 0xe0e6, 0x6fff, 0xe0e6, 0x21, 0 + .dw 0x7400, 0xe0e6, 0xffff, 0xe0e6, 0x21, 0 + .dw 0x0400, 0xe0e7, 0x0fff, 0xe0e7, 0x21, 0 + .dw 0x1400, 0xe0e7, 0x1fff, 0xe0e7, 0x21, 0 + .dw 0x2400, 0xe0e7, 0x2fff, 0xe0e7, 0x21, 0 + .dw 0x3400, 0xe0e7, 0x3fff, 0xe0e7, 0x21, 0 + .dw 0x4400, 0xe0e7, 0x4fff, 0xe0e7, 0x21, 0 + .dw 0x5400, 0xe0e7, 0x5fff, 0xe0e7, 0x21, 0 + .dw 0x6400, 0xe0e7, 0x6fff, 0xe0e7, 0x21, 0 + .dw 0x7400, 0xe0e7, 0xffff, 0xe0e7, 0x21, 0 + .dw 0x0400, 0xe0e8, 0x0fff, 0xe0e8, 0x21, 0 + .dw 0x1400, 0xe0e8, 0x1fff, 0xe0e8, 0x21, 0 + .dw 0x2400, 0xe0e8, 0x2fff, 0xe0e8, 0x21, 0 + .dw 0x3400, 0xe0e8, 0x3fff, 0xe0e8, 0x21, 0 + .dw 0x4400, 0xe0e8, 0x4fff, 0xe0e8, 0x21, 0 + .dw 0x5400, 0xe0e8, 0x5fff, 0xe0e8, 0x21, 0 + .dw 0x6400, 0xe0e8, 0x6fff, 0xe0e8, 0x21, 0 + .dw 0x7400, 0xe0e8, 0xffff, 0xe0e8, 0x21, 0 + .dw 0x0400, 0xe0e9, 0x0fff, 0xe0e9, 0x21, 0 + .dw 0x1400, 0xe0e9, 0x1fff, 0xe0e9, 0x21, 0 + .dw 0x2400, 0xe0e9, 0x2fff, 0xe0e9, 0x21, 0 + .dw 0x3400, 0xe0e9, 0x3fff, 0xe0e9, 0x21, 0 + .dw 0x4400, 0xe0e9, 0x4fff, 0xe0e9, 0x21, 0 + .dw 0x5400, 0xe0e9, 0x5fff, 0xe0e9, 0x21, 0 + .dw 0x6400, 0xe0e9, 0x6fff, 0xe0e9, 0x21, 0 + .dw 0x7400, 0xe0e9, 0xffff, 0xe0e9, 0x21, 0 + .dw 0x0400, 0xe0ea, 0x0fff, 0xe0ea, 0x21, 0 + .dw 0x1400, 0xe0ea, 0x1fff, 0xe0ea, 0x21, 0 + .dw 0x2400, 0xe0ea, 0x2fff, 0xe0ea, 0x21, 0 + .dw 0x3400, 0xe0ea, 0x3fff, 0xe0ea, 0x21, 0 + .dw 0x4400, 0xe0ea, 0x4fff, 0xe0ea, 0x21, 0 + .dw 0x5400, 0xe0ea, 0x5fff, 0xe0ea, 0x21, 0 + .dw 0x6400, 0xe0ea, 0x6fff, 0xe0ea, 0x21, 0 + .dw 0x7400, 0xe0ea, 0xffff, 0xe0ea, 0x21, 0 + .dw 0x0400, 0xe0eb, 0x0fff, 0xe0eb, 0x21, 0 + .dw 0x1400, 0xe0eb, 0x1fff, 0xe0eb, 0x21, 0 + .dw 0x2400, 0xe0eb, 0x2fff, 0xe0eb, 0x21, 0 + .dw 0x3400, 0xe0eb, 0x3fff, 0xe0eb, 0x21, 0 + .dw 0x4400, 0xe0eb, 0x4fff, 0xe0eb, 0x21, 0 + .dw 0x5400, 0xe0eb, 0x5fff, 0xe0eb, 0x21, 0 + .dw 0x6400, 0xe0eb, 0x6fff, 0xe0eb, 0x21, 0 + .dw 0x7400, 0xe0eb, 0xffff, 0xe0eb, 0x21, 0 + .dw 0x0400, 0xe0ec, 0x0fff, 0xe0ec, 0x21, 0 + .dw 0x1400, 0xe0ec, 0x1fff, 0xe0ec, 0x21, 0 + .dw 0x2400, 0xe0ec, 0x2fff, 0xe0ec, 0x21, 0 + .dw 0x3400, 0xe0ec, 0x3fff, 0xe0ec, 0x21, 0 + .dw 0x4400, 0xe0ec, 0x4fff, 0xe0ec, 0x21, 0 + .dw 0x5400, 0xe0ec, 0x5fff, 0xe0ec, 0x21, 0 + .dw 0x6400, 0xe0ec, 0x6fff, 0xe0ec, 0x21, 0 + .dw 0x7400, 0xe0ec, 0xffff, 0xe0ec, 0x21, 0 + .dw 0x0400, 0xe0ed, 0x0fff, 0xe0ed, 0x21, 0 + .dw 0x1400, 0xe0ed, 0x1fff, 0xe0ed, 0x21, 0 + .dw 0x2400, 0xe0ed, 0x2fff, 0xe0ed, 0x21, 0 + .dw 0x3400, 0xe0ed, 0x3fff, 0xe0ed, 0x21, 0 + .dw 0x4400, 0xe0ed, 0x4fff, 0xe0ed, 0x21, 0 + .dw 0x5400, 0xe0ed, 0x5fff, 0xe0ed, 0x21, 0 + .dw 0x6400, 0xe0ed, 0x6fff, 0xe0ed, 0x21, 0 + .dw 0x7400, 0xe0ed, 0xffff, 0xe0ed, 0x21, 0 + .dw 0x0400, 0xe0ee, 0x0fff, 0xe0ee, 0x21, 0 + .dw 0x1400, 0xe0ee, 0x1fff, 0xe0ee, 0x21, 0 + .dw 0x2400, 0xe0ee, 0x2fff, 0xe0ee, 0x21, 0 + .dw 0x3400, 0xe0ee, 0x3fff, 0xe0ee, 0x21, 0 + .dw 0x4400, 0xe0ee, 0x4fff, 0xe0ee, 0x21, 0 + .dw 0x5400, 0xe0ee, 0x5fff, 0xe0ee, 0x21, 0 + .dw 0x6400, 0xe0ee, 0x6fff, 0xe0ee, 0x21, 0 + .dw 0x7400, 0xe0ee, 0xffff, 0xe0ee, 0x21, 0 + .dw 0x0400, 0xe0ef, 0x0fff, 0xe0ef, 0x21, 0 + .dw 0x1400, 0xe0ef, 0x1fff, 0xe0ef, 0x21, 0 + .dw 0x2400, 0xe0ef, 0x2fff, 0xe0ef, 0x21, 0 + .dw 0x3400, 0xe0ef, 0x3fff, 0xe0ef, 0x21, 0 + .dw 0x4400, 0xe0ef, 0x4fff, 0xe0ef, 0x21, 0 + .dw 0x5400, 0xe0ef, 0x5fff, 0xe0ef, 0x21, 0 + .dw 0x6400, 0xe0ef, 0x6fff, 0xe0ef, 0x21, 0 + .dw 0x7400, 0xe0ef, 0xffff, 0xe0ef, 0x21, 0 + .dw 0x0400, 0xe0f0, 0x0fff, 0xe0f0, 0x21, 0 + .dw 0x1400, 0xe0f0, 0x1fff, 0xe0f0, 0x21, 0 + .dw 0x2400, 0xe0f0, 0x2fff, 0xe0f0, 0x21, 0 + .dw 0x3400, 0xe0f0, 0x3fff, 0xe0f0, 0x21, 0 + .dw 0x4400, 0xe0f0, 0x4fff, 0xe0f0, 0x21, 0 + .dw 0x5400, 0xe0f0, 0x5fff, 0xe0f0, 0x21, 0 + .dw 0x6400, 0xe0f0, 0x6fff, 0xe0f0, 0x21, 0 + .dw 0x7400, 0xe0f0, 0xffff, 0xe0f0, 0x21, 0 + .dw 0x0400, 0xe0f1, 0x0fff, 0xe0f1, 0x21, 0 + .dw 0x1400, 0xe0f1, 0x1fff, 0xe0f1, 0x21, 0 + .dw 0x2400, 0xe0f1, 0x2fff, 0xe0f1, 0x21, 0 + .dw 0x3400, 0xe0f1, 0x3fff, 0xe0f1, 0x21, 0 + .dw 0x4400, 0xe0f1, 0x4fff, 0xe0f1, 0x21, 0 + .dw 0x5400, 0xe0f1, 0x5fff, 0xe0f1, 0x21, 0 + .dw 0x6400, 0xe0f1, 0x6fff, 0xe0f1, 0x21, 0 + .dw 0x7400, 0xe0f1, 0xffff, 0xe0f1, 0x21, 0 + .dw 0x0400, 0xe0f2, 0x0fff, 0xe0f2, 0x21, 0 + .dw 0x1400, 0xe0f2, 0x1fff, 0xe0f2, 0x21, 0 + .dw 0x2400, 0xe0f2, 0x2fff, 0xe0f2, 0x21, 0 + .dw 0x3400, 0xe0f2, 0x3fff, 0xe0f2, 0x21, 0 + .dw 0x4400, 0xe0f2, 0x4fff, 0xe0f2, 0x21, 0 + .dw 0x5400, 0xe0f2, 0x5fff, 0xe0f2, 0x21, 0 + .dw 0x6400, 0xe0f2, 0x6fff, 0xe0f2, 0x21, 0 + .dw 0x7400, 0xe0f2, 0xffff, 0xe0f2, 0x21, 0 + .dw 0x0400, 0xe0f3, 0x0fff, 0xe0f3, 0x21, 0 + .dw 0x1400, 0xe0f3, 0x1fff, 0xe0f3, 0x21, 0 + .dw 0x2400, 0xe0f3, 0x2fff, 0xe0f3, 0x21, 0 + .dw 0x3400, 0xe0f3, 0x3fff, 0xe0f3, 0x21, 0 + .dw 0x4400, 0xe0f3, 0x4fff, 0xe0f3, 0x21, 0 + .dw 0x5400, 0xe0f3, 0x5fff, 0xe0f3, 0x21, 0 + .dw 0x6400, 0xe0f3, 0x6fff, 0xe0f3, 0x21, 0 + .dw 0x7400, 0xe0f3, 0xffff, 0xe0f3, 0x21, 0 + .dw 0x0400, 0xe0f4, 0x0fff, 0xe0f4, 0x21, 0 + .dw 0x1400, 0xe0f4, 0x1fff, 0xe0f4, 0x21, 0 + .dw 0x2400, 0xe0f4, 0x2fff, 0xe0f4, 0x21, 0 + .dw 0x3400, 0xe0f4, 0x3fff, 0xe0f4, 0x21, 0 + .dw 0x4400, 0xe0f4, 0x4fff, 0xe0f4, 0x21, 0 + .dw 0x5400, 0xe0f4, 0x5fff, 0xe0f4, 0x21, 0 + .dw 0x6400, 0xe0f4, 0x6fff, 0xe0f4, 0x21, 0 + .dw 0x7400, 0xe0f4, 0xffff, 0xe0f4, 0x21, 0 + .dw 0x0400, 0xe0f5, 0x0fff, 0xe0f5, 0x21, 0 + .dw 0x1400, 0xe0f5, 0x1fff, 0xe0f5, 0x21, 0 + .dw 0x2400, 0xe0f5, 0x2fff, 0xe0f5, 0x21, 0 + .dw 0x3400, 0xe0f5, 0x3fff, 0xe0f5, 0x21, 0 + .dw 0x4400, 0xe0f5, 0x4fff, 0xe0f5, 0x21, 0 + .dw 0x5400, 0xe0f5, 0x5fff, 0xe0f5, 0x21, 0 + .dw 0x6400, 0xe0f5, 0x6fff, 0xe0f5, 0x21, 0 + .dw 0x7400, 0xe0f5, 0xffff, 0xe0f5, 0x21, 0 + .dw 0x0400, 0xe0f6, 0x0fff, 0xe0f6, 0x21, 0 + .dw 0x1400, 0xe0f6, 0x1fff, 0xe0f6, 0x21, 0 + .dw 0x2400, 0xe0f6, 0x2fff, 0xe0f6, 0x21, 0 + .dw 0x3400, 0xe0f6, 0x3fff, 0xe0f6, 0x21, 0 + .dw 0x4400, 0xe0f6, 0x4fff, 0xe0f6, 0x21, 0 + .dw 0x5400, 0xe0f6, 0x5fff, 0xe0f6, 0x21, 0 + .dw 0x6400, 0xe0f6, 0x6fff, 0xe0f6, 0x21, 0 + .dw 0x7400, 0xe0f6, 0xffff, 0xe0f6, 0x21, 0 + .dw 0x0400, 0xe0f7, 0x0fff, 0xe0f7, 0x21, 0 + .dw 0x1400, 0xe0f7, 0x1fff, 0xe0f7, 0x21, 0 + .dw 0x2400, 0xe0f7, 0x2fff, 0xe0f7, 0x21, 0 + .dw 0x3400, 0xe0f7, 0x3fff, 0xe0f7, 0x21, 0 + .dw 0x4400, 0xe0f7, 0x4fff, 0xe0f7, 0x21, 0 + .dw 0x5400, 0xe0f7, 0x5fff, 0xe0f7, 0x21, 0 + .dw 0x6400, 0xe0f7, 0x6fff, 0xe0f7, 0x21, 0 + .dw 0x7400, 0xe0f7, 0xffff, 0xe0f7, 0x21, 0 + .dw 0x0400, 0xe0f8, 0x0fff, 0xe0f8, 0x21, 0 + .dw 0x1400, 0xe0f8, 0x1fff, 0xe0f8, 0x21, 0 + .dw 0x2400, 0xe0f8, 0x2fff, 0xe0f8, 0x21, 0 + .dw 0x3400, 0xe0f8, 0x3fff, 0xe0f8, 0x21, 0 + .dw 0x4400, 0xe0f8, 0x4fff, 0xe0f8, 0x21, 0 + .dw 0x5400, 0xe0f8, 0x5fff, 0xe0f8, 0x21, 0 + .dw 0x6400, 0xe0f8, 0x6fff, 0xe0f8, 0x21, 0 + .dw 0x7400, 0xe0f8, 0xffff, 0xe0f8, 0x21, 0 + .dw 0x0400, 0xe0f9, 0x0fff, 0xe0f9, 0x21, 0 + .dw 0x1400, 0xe0f9, 0x1fff, 0xe0f9, 0x21, 0 + .dw 0x2400, 0xe0f9, 0x2fff, 0xe0f9, 0x21, 0 + .dw 0x3400, 0xe0f9, 0x3fff, 0xe0f9, 0x21, 0 + .dw 0x4400, 0xe0f9, 0x4fff, 0xe0f9, 0x21, 0 + .dw 0x5400, 0xe0f9, 0x5fff, 0xe0f9, 0x21, 0 + .dw 0x6400, 0xe0f9, 0x6fff, 0xe0f9, 0x21, 0 + .dw 0x7400, 0xe0f9, 0xffff, 0xe0f9, 0x21, 0 + .dw 0x0400, 0xe0fa, 0x0fff, 0xe0fa, 0x21, 0 + .dw 0x1400, 0xe0fa, 0x1fff, 0xe0fa, 0x21, 0 + .dw 0x2400, 0xe0fa, 0x2fff, 0xe0fa, 0x21, 0 + .dw 0x3400, 0xe0fa, 0x3fff, 0xe0fa, 0x21, 0 + .dw 0x4400, 0xe0fa, 0x4fff, 0xe0fa, 0x21, 0 + .dw 0x5400, 0xe0fa, 0x5fff, 0xe0fa, 0x21, 0 + .dw 0x6400, 0xe0fa, 0x6fff, 0xe0fa, 0x21, 0 + .dw 0x7400, 0xe0fa, 0xffff, 0xe0fa, 0x21, 0 + .dw 0x0400, 0xe0fb, 0x0fff, 0xe0fb, 0x21, 0 + .dw 0x1400, 0xe0fb, 0x1fff, 0xe0fb, 0x21, 0 + .dw 0x2400, 0xe0fb, 0x2fff, 0xe0fb, 0x21, 0 + .dw 0x3400, 0xe0fb, 0x3fff, 0xe0fb, 0x21, 0 + .dw 0x4400, 0xe0fb, 0x4fff, 0xe0fb, 0x21, 0 + .dw 0x5400, 0xe0fb, 0x5fff, 0xe0fb, 0x21, 0 + .dw 0x6400, 0xe0fb, 0x6fff, 0xe0fb, 0x21, 0 + .dw 0x7400, 0xe0fb, 0xffff, 0xe0fb, 0x21, 0 + .dw 0x0400, 0xe0fc, 0x0fff, 0xe0fc, 0x21, 0 + .dw 0x1400, 0xe0fc, 0x1fff, 0xe0fc, 0x21, 0 + .dw 0x2400, 0xe0fc, 0x2fff, 0xe0fc, 0x21, 0 + .dw 0x3400, 0xe0fc, 0x3fff, 0xe0fc, 0x21, 0 + .dw 0x4400, 0xe0fc, 0x4fff, 0xe0fc, 0x21, 0 + .dw 0x5400, 0xe0fc, 0x5fff, 0xe0fc, 0x21, 0 + .dw 0x6400, 0xe0fc, 0x6fff, 0xe0fc, 0x21, 0 + .dw 0x7400, 0xe0fc, 0xffff, 0xe0fc, 0x21, 0 + .dw 0x0400, 0xe0fd, 0x0fff, 0xe0fd, 0x21, 0 + .dw 0x1400, 0xe0fd, 0x1fff, 0xe0fd, 0x21, 0 + .dw 0x2400, 0xe0fd, 0x2fff, 0xe0fd, 0x21, 0 + .dw 0x3400, 0xe0fd, 0x3fff, 0xe0fd, 0x21, 0 + .dw 0x4400, 0xe0fd, 0x4fff, 0xe0fd, 0x21, 0 + .dw 0x5400, 0xe0fd, 0x5fff, 0xe0fd, 0x21, 0 + .dw 0x6400, 0xe0fd, 0x6fff, 0xe0fd, 0x21, 0 + .dw 0x7400, 0xe0fd, 0xffff, 0xe0fd, 0x21, 0 + .dw 0x0400, 0xe0fe, 0x0fff, 0xe0fe, 0x21, 0 + .dw 0x1400, 0xe0fe, 0x1fff, 0xe0fe, 0x21, 0 + .dw 0x2400, 0xe0fe, 0x2fff, 0xe0fe, 0x21, 0 + .dw 0x3400, 0xe0fe, 0x3fff, 0xe0fe, 0x21, 0 + .dw 0x4400, 0xe0fe, 0x4fff, 0xe0fe, 0x21, 0 + .dw 0x5400, 0xe0fe, 0x5fff, 0xe0fe, 0x21, 0 + .dw 0x6400, 0xe0fe, 0x6fff, 0xe0fe, 0x21, 0 + .dw 0x7400, 0xe0fe, 0xffff, 0xe0fe, 0x21, 0 + .dw 0x0400, 0xe0ff, 0x0fff, 0xe0ff, 0x21, 0 + .dw 0x1400, 0xe0ff, 0x1fff, 0xe0ff, 0x21, 0 + .dw 0x2400, 0xe0ff, 0x2fff, 0xe0ff, 0x21, 0 + .dw 0x3400, 0xe0ff, 0x3fff, 0xe0ff, 0x21, 0 + .dw 0x4400, 0xe0ff, 0x4fff, 0xe0ff, 0x21, 0 + .dw 0x5400, 0xe0ff, 0x5fff, 0xe0ff, 0x21, 0 + .dw 0x6400, 0xe0ff, 0x6fff, 0xe0ff, 0x21, 0 + .dw 0x7400, 0xe0ff, 0xffff, 0xe0ff, 0x21, 0 + .dw 0x0000, 0xe160, 0xffff, 0xe17f, 0x21, 0 + .dw 0x0000, 0xe1a0, 0xffff, 0xe1ff, 0x21, 0 + .dw 0x0000, 0xe4c0, 0xffff, 0xe4ff, 0x21, 0 + .dw 0x0000, 0xe5c0, 0xffff, 0xe5ff, 0x21, 0 + .dw 0x0000, 0xe6c0, 0xffff, 0xe6ff, 0x21, 0 + .dw 0x0000, 0xe740, 0xffff, 0xe7ff, 0x21, 0 + .dw 0x0000, 0xf001, 0xffff, 0xffff, 0x21, 0 + .dw 0x0000, 0x0000, 0x0000, 0x0000, 0x00, 0 +.endm + + se_all_test diff --git a/sim/testsuite/bfin/se_all32bitopcodes.lds b/sim/testsuite/bfin/se_all32bitopcodes.lds new file mode 100644 index 0000000..6f37d65 --- /dev/null +++ b/sim/testsuite/bfin/se_all32bitopcodes.lds @@ -0,0 +1,16 @@ +MEMORY +{ + L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000 + L1_DATA : ORIGIN = 0xFF800000, LENGTH = 0x8000 + SDRAM : ORIGIN = 0x4000, LENGTH = 0x4000000 +} + +OUTPUT_ARCH(bfin) +ENTRY(__start) + +SECTIONS +{ + .text : { *(.text) } >L1_CODE + .text.usr : { *(.text.usr) } >SDRAM + .data : { *(.data) } >SDRAM +} diff --git a/sim/testsuite/bfin/se_all64bitg0opcodes.S b/sim/testsuite/bfin/se_all64bitg0opcodes.S new file mode 100644 index 0000000..516583b --- /dev/null +++ b/sim/testsuite/bfin/se_all64bitg0opcodes.S @@ -0,0 +1,33369 @@ +/* + * Blackfin testcase for testing illegal/legal 64-bit opcodes (group 0) + * from userspace. we track all instructions which cause some sort of + * exception when run from userspace, this is normally EXCAUSE : + * - 0x22 : illegal instruction combination + * and walk every instruction from 0xC0000000 to 0xffffffff + * (and have 0x8000000 set) + */ + +# Don't want to enable for normal `make check` as it takes way too long in +# the sim -- executes over 3 billion insns, and even at 10 MIPS, that's 10+ +# minutes. Useful for directed testing, but that's about it. +# mach: none +# sim: --environment operating +# xfail: too many invalid insns are decoded as valid + +#include "test.h" + .include "testutils.inc" + +#define SE_ALL_BITS 32 +#include "se_allopcodes.h" + +.macro se_all_load_insn + R2 = [P5]; + R0 = R2 << 16; + R1 = R2 >> 16; + R0 = R0 | R1; +.endm + +.macro se_all_next_insn + /* increment, and go again. */ + R0 = R2; + + /* Is this the last insn we'll execute ? */ + R1 = -1 (x); + CC = R1 == R0; + IF CC JUMP pass_lvl; + + /* cut across the opcode space in an efficient manner: + * increment the high 16bits first since the low 16bits encode + * the type of insn ... */ + imm32 R1, 0x10000; + R0 = R1 + R0; + CC = R1 < R0 (IU); + IF CC jump 1f (bp); + + R0 += 1; + /* skip any 16bit insn chunks */ + R1 = R0; + R1.L = 0xC800; + CC = R0 < R1 (IU); + IF CC R0 = R1; +1: + + /* force parallel insns */ + BITSET (R0, 11); + + /* skip linkage insns */ + R1 = R0; + R2 = R0; + R1.L = 0xe800; + R2.L = 0xe802; + CC = R0 == R1; + IF CC R0 = R2; + + [P5] = R0; +.endm + +.macro se_all_insn_init + .dw 0xc800; /* 32bit */ + .dw 0x0000; /* insn */ + .dw 0x0000; /* || group1 */ + .dw 0x0000; /* || group2; */ +.endm +.macro se_all_insn_table + /* this table must be sorted, and end with zero */ + /* start end SEQSTAT */ + .dw 0x1a00, 0xc800, 0x1fff, 0xc800, 0x21, 0 + .dw 0x3a00, 0xc800, 0x3fff, 0xc800, 0x21, 0 + .dw 0x5a00, 0xc800, 0x5fff, 0xc800, 0x21, 0 + .dw 0x7a00, 0xc800, 0x7fff, 0xc800, 0x21, 0 + .dw 0x9a00, 0xc800, 0x9fff, 0xc800, 0x21, 0 + .dw 0xba00, 0xc800, 0xbfff, 0xc800, 0x21, 0 + .dw 0xda00, 0xc800, 0xdfff, 0xc800, 0x21, 0 + .dw 0xfa00, 0xc800, 0xffff, 0xc800, 0x21, 0 + .dw 0x1a00, 0xc801, 0x1fff, 0xc801, 0x21, 0 + .dw 0x3a00, 0xc801, 0x3fff, 0xc801, 0x21, 0 + .dw 0x5a00, 0xc801, 0x5fff, 0xc801, 0x21, 0 + .dw 0x7a00, 0xc801, 0x7fff, 0xc801, 0x21, 0 + .dw 0x9a00, 0xc801, 0x9fff, 0xc801, 0x21, 0 + .dw 0xba00, 0xc801, 0xbfff, 0xc801, 0x21, 0 + .dw 0xda00, 0xc801, 0xdfff, 0xc801, 0x21, 0 + .dw 0xfa00, 0xc801, 0xffff, 0xc801, 0x21, 0 + .dw 0x1a00, 0xc802, 0x1fff, 0xc802, 0x21, 0 + .dw 0x3a00, 0xc802, 0x3fff, 0xc802, 0x21, 0 + .dw 0x5a00, 0xc802, 0x5fff, 0xc802, 0x21, 0 + .dw 0x7a00, 0xc802, 0x7fff, 0xc802, 0x21, 0 + .dw 0x9a00, 0xc802, 0x9fff, 0xc802, 0x21, 0 + .dw 0xba00, 0xc802, 0xbfff, 0xc802, 0x21, 0 + .dw 0xda00, 0xc802, 0xdfff, 0xc802, 0x21, 0 + .dw 0xfa00, 0xc802, 0xffff, 0xc802, 0x21, 0 + .dw 0x1a00, 0xc803, 0x1fff, 0xc803, 0x21, 0 + .dw 0x3a00, 0xc803, 0xffff, 0xc803, 0x21, 0 + .dw 0x1a00, 0xc804, 0x1fff, 0xc804, 0x21, 0 + .dw 0x3a00, 0xc804, 0x3fff, 0xc804, 0x21, 0 + .dw 0x5a00, 0xc804, 0x5fff, 0xc804, 0x21, 0 + .dw 0x7a00, 0xc804, 0x7fff, 0xc804, 0x21, 0 + .dw 0x9a00, 0xc804, 0x9fff, 0xc804, 0x21, 0 + .dw 0xba00, 0xc804, 0xbfff, 0xc804, 0x21, 0 + .dw 0xda00, 0xc804, 0xdfff, 0xc804, 0x21, 0 + .dw 0xfa00, 0xc804, 0xffff, 0xc804, 0x21, 0 + .dw 0x1a00, 0xc805, 0x1fff, 0xc805, 0x21, 0 + .dw 0x3a00, 0xc805, 0x3fff, 0xc805, 0x21, 0 + .dw 0x5a00, 0xc805, 0x5fff, 0xc805, 0x21, 0 + .dw 0x7a00, 0xc805, 0x7fff, 0xc805, 0x21, 0 + .dw 0x9a00, 0xc805, 0x9fff, 0xc805, 0x21, 0 + .dw 0xba00, 0xc805, 0xbfff, 0xc805, 0x21, 0 + .dw 0xda00, 0xc805, 0xdfff, 0xc805, 0x21, 0 + .dw 0xfa00, 0xc805, 0xffff, 0xc805, 0x21, 0 + .dw 0x1a00, 0xc806, 0x1fff, 0xc806, 0x21, 0 + .dw 0x3a00, 0xc806, 0x3fff, 0xc806, 0x21, 0 + .dw 0x5a00, 0xc806, 0x5fff, 0xc806, 0x21, 0 + .dw 0x7a00, 0xc806, 0x7fff, 0xc806, 0x21, 0 + .dw 0x9a00, 0xc806, 0x9fff, 0xc806, 0x21, 0 + .dw 0xba00, 0xc806, 0xbfff, 0xc806, 0x21, 0 + .dw 0xda00, 0xc806, 0xdfff, 0xc806, 0x21, 0 + .dw 0xfa00, 0xc806, 0xffff, 0xc806, 0x21, 0 + .dw 0x1a00, 0xc807, 0x1fff, 0xc807, 0x21, 0 + .dw 0x3a00, 0xc807, 0x1fff, 0xc808, 0x21, 0 + .dw 0x2040, 0xc808, 0x207f, 0xc808, 0x21, 0 + .dw 0x20c0, 0xc808, 0x20ff, 0xc808, 0x21, 0 + .dw 0x2140, 0xc808, 0x217f, 0xc808, 0x21, 0 + .dw 0x21c0, 0xc808, 0x21ff, 0xc808, 0x21, 0 + .dw 0x2240, 0xc808, 0x227f, 0xc808, 0x21, 0 + .dw 0x22c0, 0xc808, 0x22ff, 0xc808, 0x21, 0 + .dw 0x2340, 0xc808, 0x237f, 0xc808, 0x21, 0 + .dw 0x23c0, 0xc808, 0x23ff, 0xc808, 0x21, 0 + .dw 0x2440, 0xc808, 0x247f, 0xc808, 0x21, 0 + .dw 0x24c0, 0xc808, 0x24ff, 0xc808, 0x21, 0 + .dw 0x2540, 0xc808, 0x257f, 0xc808, 0x21, 0 + .dw 0x25c0, 0xc808, 0x25ff, 0xc808, 0x21, 0 + .dw 0x2640, 0xc808, 0x267f, 0xc808, 0x21, 0 + .dw 0x26c0, 0xc808, 0x26ff, 0xc808, 0x21, 0 + .dw 0x2740, 0xc808, 0x277f, 0xc808, 0x21, 0 + .dw 0x27c0, 0xc808, 0x27ff, 0xc808, 0x21, 0 + .dw 0x2840, 0xc808, 0x287f, 0xc808, 0x21, 0 + .dw 0x28c0, 0xc808, 0x28ff, 0xc808, 0x21, 0 + .dw 0x2940, 0xc808, 0x297f, 0xc808, 0x21, 0 + .dw 0x29c0, 0xc808, 0x29ff, 0xc808, 0x21, 0 + .dw 0x2a40, 0xc808, 0x2a7f, 0xc808, 0x21, 0 + .dw 0x2ac0, 0xc808, 0x2aff, 0xc808, 0x21, 0 + .dw 0x2b40, 0xc808, 0x2b7f, 0xc808, 0x21, 0 + .dw 0x2bc0, 0xc808, 0x2bff, 0xc808, 0x21, 0 + .dw 0x2c40, 0xc808, 0x2c7f, 0xc808, 0x21, 0 + .dw 0x2cc0, 0xc808, 0x2cff, 0xc808, 0x21, 0 + .dw 0x2d40, 0xc808, 0x2d7f, 0xc808, 0x21, 0 + .dw 0x2dc0, 0xc808, 0x2dff, 0xc808, 0x21, 0 + .dw 0x2e40, 0xc808, 0x2e7f, 0xc808, 0x21, 0 + .dw 0x2ec0, 0xc808, 0x2eff, 0xc808, 0x21, 0 + .dw 0x2f40, 0xc808, 0x2f7f, 0xc808, 0x21, 0 + .dw 0x2fc0, 0xc808, 0x2fff, 0xc808, 0x21, 0 + .dw 0x3040, 0xc808, 0x307f, 0xc808, 0x21, 0 + .dw 0x30c0, 0xc808, 0x30ff, 0xc808, 0x21, 0 + .dw 0x3140, 0xc808, 0x317f, 0xc808, 0x21, 0 + .dw 0x31c0, 0xc808, 0x31ff, 0xc808, 0x21, 0 + .dw 0x3240, 0xc808, 0x327f, 0xc808, 0x21, 0 + .dw 0x32c0, 0xc808, 0x32ff, 0xc808, 0x21, 0 + .dw 0x3340, 0xc808, 0x337f, 0xc808, 0x21, 0 + .dw 0x33c0, 0xc808, 0x33ff, 0xc808, 0x21, 0 + .dw 0x3440, 0xc808, 0x347f, 0xc808, 0x21, 0 + .dw 0x34c0, 0xc808, 0x34ff, 0xc808, 0x21, 0 + .dw 0x3540, 0xc808, 0x357f, 0xc808, 0x21, 0 + .dw 0x35c0, 0xc808, 0x35ff, 0xc808, 0x21, 0 + .dw 0x3640, 0xc808, 0x367f, 0xc808, 0x21, 0 + .dw 0x36c0, 0xc808, 0x36ff, 0xc808, 0x21, 0 + .dw 0x3740, 0xc808, 0x377f, 0xc808, 0x21, 0 + .dw 0x37c0, 0xc808, 0x37ff, 0xc808, 0x21, 0 + .dw 0x3840, 0xc808, 0x387f, 0xc808, 0x21, 0 + .dw 0x38c0, 0xc808, 0x38ff, 0xc808, 0x21, 0 + .dw 0x3940, 0xc808, 0x397f, 0xc808, 0x21, 0 + .dw 0x39c0, 0xc808, 0x5fff, 0xc808, 0x21, 0 + .dw 0x6040, 0xc808, 0x607f, 0xc808, 0x21, 0 + .dw 0x60c0, 0xc808, 0x60ff, 0xc808, 0x21, 0 + .dw 0x6140, 0xc808, 0x617f, 0xc808, 0x21, 0 + .dw 0x61c0, 0xc808, 0x61ff, 0xc808, 0x21, 0 + .dw 0x6240, 0xc808, 0x627f, 0xc808, 0x21, 0 + .dw 0x62c0, 0xc808, 0x62ff, 0xc808, 0x21, 0 + .dw 0x6340, 0xc808, 0x637f, 0xc808, 0x21, 0 + .dw 0x63c0, 0xc808, 0x63ff, 0xc808, 0x21, 0 + .dw 0x6440, 0xc808, 0x647f, 0xc808, 0x21, 0 + .dw 0x64c0, 0xc808, 0x64ff, 0xc808, 0x21, 0 + .dw 0x6540, 0xc808, 0x657f, 0xc808, 0x21, 0 + .dw 0x65c0, 0xc808, 0x65ff, 0xc808, 0x21, 0 + .dw 0x6640, 0xc808, 0x667f, 0xc808, 0x21, 0 + .dw 0x66c0, 0xc808, 0x66ff, 0xc808, 0x21, 0 + .dw 0x6740, 0xc808, 0x677f, 0xc808, 0x21, 0 + .dw 0x67c0, 0xc808, 0x67ff, 0xc808, 0x21, 0 + .dw 0x6840, 0xc808, 0x687f, 0xc808, 0x21, 0 + .dw 0x68c0, 0xc808, 0x68ff, 0xc808, 0x21, 0 + .dw 0x6940, 0xc808, 0x697f, 0xc808, 0x21, 0 + .dw 0x69c0, 0xc808, 0x69ff, 0xc808, 0x21, 0 + .dw 0x6a40, 0xc808, 0x6a7f, 0xc808, 0x21, 0 + .dw 0x6ac0, 0xc808, 0x6aff, 0xc808, 0x21, 0 + .dw 0x6b40, 0xc808, 0x6b7f, 0xc808, 0x21, 0 + .dw 0x6bc0, 0xc808, 0x6bff, 0xc808, 0x21, 0 + .dw 0x6c40, 0xc808, 0x6c7f, 0xc808, 0x21, 0 + .dw 0x6cc0, 0xc808, 0x6cff, 0xc808, 0x21, 0 + .dw 0x6d40, 0xc808, 0x6d7f, 0xc808, 0x21, 0 + .dw 0x6dc0, 0xc808, 0x6dff, 0xc808, 0x21, 0 + .dw 0x6e40, 0xc808, 0x6e7f, 0xc808, 0x21, 0 + .dw 0x6ec0, 0xc808, 0x6eff, 0xc808, 0x21, 0 + .dw 0x6f40, 0xc808, 0x6f7f, 0xc808, 0x21, 0 + .dw 0x6fc0, 0xc808, 0x6fff, 0xc808, 0x21, 0 + .dw 0x7040, 0xc808, 0x707f, 0xc808, 0x21, 0 + .dw 0x70c0, 0xc808, 0x70ff, 0xc808, 0x21, 0 + .dw 0x7140, 0xc808, 0x717f, 0xc808, 0x21, 0 + .dw 0x71c0, 0xc808, 0x71ff, 0xc808, 0x21, 0 + .dw 0x7240, 0xc808, 0x727f, 0xc808, 0x21, 0 + .dw 0x72c0, 0xc808, 0x72ff, 0xc808, 0x21, 0 + .dw 0x7340, 0xc808, 0x737f, 0xc808, 0x21, 0 + .dw 0x73c0, 0xc808, 0x73ff, 0xc808, 0x21, 0 + .dw 0x7440, 0xc808, 0x747f, 0xc808, 0x21, 0 + .dw 0x74c0, 0xc808, 0x74ff, 0xc808, 0x21, 0 + .dw 0x7540, 0xc808, 0x757f, 0xc808, 0x21, 0 + .dw 0x75c0, 0xc808, 0x75ff, 0xc808, 0x21, 0 + .dw 0x7640, 0xc808, 0x767f, 0xc808, 0x21, 0 + .dw 0x76c0, 0xc808, 0x76ff, 0xc808, 0x21, 0 + .dw 0x7740, 0xc808, 0x777f, 0xc808, 0x21, 0 + .dw 0x77c0, 0xc808, 0x77ff, 0xc808, 0x21, 0 + .dw 0x7840, 0xc808, 0x787f, 0xc808, 0x21, 0 + .dw 0x78c0, 0xc808, 0x78ff, 0xc808, 0x21, 0 + .dw 0x7940, 0xc808, 0x797f, 0xc808, 0x21, 0 + .dw 0x79c0, 0xc808, 0x9fff, 0xc808, 0x21, 0 + .dw 0xa040, 0xc808, 0xa07f, 0xc808, 0x21, 0 + .dw 0xa0c0, 0xc808, 0xa0ff, 0xc808, 0x21, 0 + .dw 0xa140, 0xc808, 0xa17f, 0xc808, 0x21, 0 + .dw 0xa1c0, 0xc808, 0xa1ff, 0xc808, 0x21, 0 + .dw 0xa240, 0xc808, 0xa27f, 0xc808, 0x21, 0 + .dw 0xa2c0, 0xc808, 0xa2ff, 0xc808, 0x21, 0 + .dw 0xa340, 0xc808, 0xa37f, 0xc808, 0x21, 0 + .dw 0xa3c0, 0xc808, 0xa3ff, 0xc808, 0x21, 0 + .dw 0xa440, 0xc808, 0xa47f, 0xc808, 0x21, 0 + .dw 0xa4c0, 0xc808, 0xa4ff, 0xc808, 0x21, 0 + .dw 0xa540, 0xc808, 0xa57f, 0xc808, 0x21, 0 + .dw 0xa5c0, 0xc808, 0xa5ff, 0xc808, 0x21, 0 + .dw 0xa640, 0xc808, 0xa67f, 0xc808, 0x21, 0 + .dw 0xa6c0, 0xc808, 0xa6ff, 0xc808, 0x21, 0 + .dw 0xa740, 0xc808, 0xa77f, 0xc808, 0x21, 0 + .dw 0xa7c0, 0xc808, 0xa7ff, 0xc808, 0x21, 0 + .dw 0xa840, 0xc808, 0xa87f, 0xc808, 0x21, 0 + .dw 0xa8c0, 0xc808, 0xa8ff, 0xc808, 0x21, 0 + .dw 0xa940, 0xc808, 0xa97f, 0xc808, 0x21, 0 + .dw 0xa9c0, 0xc808, 0xa9ff, 0xc808, 0x21, 0 + .dw 0xaa40, 0xc808, 0xaa7f, 0xc808, 0x21, 0 + .dw 0xaac0, 0xc808, 0xaaff, 0xc808, 0x21, 0 + .dw 0xab40, 0xc808, 0xab7f, 0xc808, 0x21, 0 + .dw 0xabc0, 0xc808, 0xabff, 0xc808, 0x21, 0 + .dw 0xac40, 0xc808, 0xac7f, 0xc808, 0x21, 0 + .dw 0xacc0, 0xc808, 0xacff, 0xc808, 0x21, 0 + .dw 0xad40, 0xc808, 0xad7f, 0xc808, 0x21, 0 + .dw 0xadc0, 0xc808, 0xadff, 0xc808, 0x21, 0 + .dw 0xae40, 0xc808, 0xae7f, 0xc808, 0x21, 0 + .dw 0xaec0, 0xc808, 0xaeff, 0xc808, 0x21, 0 + .dw 0xaf40, 0xc808, 0xaf7f, 0xc808, 0x21, 0 + .dw 0xafc0, 0xc808, 0xafff, 0xc808, 0x21, 0 + .dw 0xb040, 0xc808, 0xb07f, 0xc808, 0x21, 0 + .dw 0xb0c0, 0xc808, 0xb0ff, 0xc808, 0x21, 0 + .dw 0xb140, 0xc808, 0xb17f, 0xc808, 0x21, 0 + .dw 0xb1c0, 0xc808, 0xb1ff, 0xc808, 0x21, 0 + .dw 0xb240, 0xc808, 0xb27f, 0xc808, 0x21, 0 + .dw 0xb2c0, 0xc808, 0xb2ff, 0xc808, 0x21, 0 + .dw 0xb340, 0xc808, 0xb37f, 0xc808, 0x21, 0 + .dw 0xb3c0, 0xc808, 0xb3ff, 0xc808, 0x21, 0 + .dw 0xb440, 0xc808, 0xb47f, 0xc808, 0x21, 0 + .dw 0xb4c0, 0xc808, 0xb4ff, 0xc808, 0x21, 0 + .dw 0xb540, 0xc808, 0xb57f, 0xc808, 0x21, 0 + .dw 0xb5c0, 0xc808, 0xb5ff, 0xc808, 0x21, 0 + .dw 0xb640, 0xc808, 0xb67f, 0xc808, 0x21, 0 + .dw 0xb6c0, 0xc808, 0xb6ff, 0xc808, 0x21, 0 + .dw 0xb740, 0xc808, 0xb77f, 0xc808, 0x21, 0 + .dw 0xb7c0, 0xc808, 0xb7ff, 0xc808, 0x21, 0 + .dw 0xb840, 0xc808, 0xb87f, 0xc808, 0x21, 0 + .dw 0xb8c0, 0xc808, 0xb8ff, 0xc808, 0x21, 0 + .dw 0xb940, 0xc808, 0xb97f, 0xc808, 0x21, 0 + .dw 0xb9c0, 0xc808, 0xdfff, 0xc808, 0x21, 0 + .dw 0xe040, 0xc808, 0xe07f, 0xc808, 0x21, 0 + .dw 0xe0c0, 0xc808, 0xe0ff, 0xc808, 0x21, 0 + .dw 0xe140, 0xc808, 0xe17f, 0xc808, 0x21, 0 + .dw 0xe1c0, 0xc808, 0xe1ff, 0xc808, 0x21, 0 + .dw 0xe240, 0xc808, 0xe27f, 0xc808, 0x21, 0 + .dw 0xe2c0, 0xc808, 0xe2ff, 0xc808, 0x21, 0 + .dw 0xe340, 0xc808, 0xe37f, 0xc808, 0x21, 0 + .dw 0xe3c0, 0xc808, 0xe3ff, 0xc808, 0x21, 0 + .dw 0xe440, 0xc808, 0xe47f, 0xc808, 0x21, 0 + .dw 0xe4c0, 0xc808, 0xe4ff, 0xc808, 0x21, 0 + .dw 0xe540, 0xc808, 0xe57f, 0xc808, 0x21, 0 + .dw 0xe5c0, 0xc808, 0xe5ff, 0xc808, 0x21, 0 + .dw 0xe640, 0xc808, 0xe67f, 0xc808, 0x21, 0 + .dw 0xe6c0, 0xc808, 0xe6ff, 0xc808, 0x21, 0 + .dw 0xe740, 0xc808, 0xe77f, 0xc808, 0x21, 0 + .dw 0xe7c0, 0xc808, 0xe7ff, 0xc808, 0x21, 0 + .dw 0xe840, 0xc808, 0xe87f, 0xc808, 0x21, 0 + .dw 0xe8c0, 0xc808, 0xe8ff, 0xc808, 0x21, 0 + .dw 0xe940, 0xc808, 0xe97f, 0xc808, 0x21, 0 + .dw 0xe9c0, 0xc808, 0xe9ff, 0xc808, 0x21, 0 + .dw 0xea40, 0xc808, 0xea7f, 0xc808, 0x21, 0 + .dw 0xeac0, 0xc808, 0xeaff, 0xc808, 0x21, 0 + .dw 0xeb40, 0xc808, 0xeb7f, 0xc808, 0x21, 0 + .dw 0xebc0, 0xc808, 0xebff, 0xc808, 0x21, 0 + .dw 0xec40, 0xc808, 0xec7f, 0xc808, 0x21, 0 + .dw 0xecc0, 0xc808, 0xecff, 0xc808, 0x21, 0 + .dw 0xed40, 0xc808, 0xed7f, 0xc808, 0x21, 0 + .dw 0xedc0, 0xc808, 0xedff, 0xc808, 0x21, 0 + .dw 0xee40, 0xc808, 0xee7f, 0xc808, 0x21, 0 + .dw 0xeec0, 0xc808, 0xeeff, 0xc808, 0x21, 0 + .dw 0xef40, 0xc808, 0xef7f, 0xc808, 0x21, 0 + .dw 0xefc0, 0xc808, 0xefff, 0xc808, 0x21, 0 + .dw 0xf040, 0xc808, 0xf07f, 0xc808, 0x21, 0 + .dw 0xf0c0, 0xc808, 0xf0ff, 0xc808, 0x21, 0 + .dw 0xf140, 0xc808, 0xf17f, 0xc808, 0x21, 0 + .dw 0xf1c0, 0xc808, 0xf1ff, 0xc808, 0x21, 0 + .dw 0xf240, 0xc808, 0xf27f, 0xc808, 0x21, 0 + .dw 0xf2c0, 0xc808, 0xf2ff, 0xc808, 0x21, 0 + .dw 0xf340, 0xc808, 0xf37f, 0xc808, 0x21, 0 + .dw 0xf3c0, 0xc808, 0xf3ff, 0xc808, 0x21, 0 + .dw 0xf440, 0xc808, 0xf47f, 0xc808, 0x21, 0 + .dw 0xf4c0, 0xc808, 0xf4ff, 0xc808, 0x21, 0 + .dw 0xf540, 0xc808, 0xf57f, 0xc808, 0x21, 0 + .dw 0xf5c0, 0xc808, 0xf5ff, 0xc808, 0x21, 0 + .dw 0xf640, 0xc808, 0xf67f, 0xc808, 0x21, 0 + .dw 0xf6c0, 0xc808, 0xf6ff, 0xc808, 0x21, 0 + .dw 0xf740, 0xc808, 0xf77f, 0xc808, 0x21, 0 + .dw 0xf7c0, 0xc808, 0xf7ff, 0xc808, 0x21, 0 + .dw 0xf840, 0xc808, 0xf87f, 0xc808, 0x21, 0 + .dw 0xf8c0, 0xc808, 0xf8ff, 0xc808, 0x21, 0 + .dw 0xf940, 0xc808, 0xf97f, 0xc808, 0x21, 0 + .dw 0xf9c0, 0xc808, 0x1fff, 0xc809, 0x21, 0 + .dw 0x2040, 0xc809, 0x207f, 0xc809, 0x21, 0 + .dw 0x20c0, 0xc809, 0x20ff, 0xc809, 0x21, 0 + .dw 0x2140, 0xc809, 0x217f, 0xc809, 0x21, 0 + .dw 0x21c0, 0xc809, 0x21ff, 0xc809, 0x21, 0 + .dw 0x2240, 0xc809, 0x227f, 0xc809, 0x21, 0 + .dw 0x22c0, 0xc809, 0x22ff, 0xc809, 0x21, 0 + .dw 0x2340, 0xc809, 0x237f, 0xc809, 0x21, 0 + .dw 0x23c0, 0xc809, 0x23ff, 0xc809, 0x21, 0 + .dw 0x2440, 0xc809, 0x247f, 0xc809, 0x21, 0 + .dw 0x24c0, 0xc809, 0x24ff, 0xc809, 0x21, 0 + .dw 0x2540, 0xc809, 0x257f, 0xc809, 0x21, 0 + .dw 0x25c0, 0xc809, 0x25ff, 0xc809, 0x21, 0 + .dw 0x2640, 0xc809, 0x267f, 0xc809, 0x21, 0 + .dw 0x26c0, 0xc809, 0x26ff, 0xc809, 0x21, 0 + .dw 0x2740, 0xc809, 0x277f, 0xc809, 0x21, 0 + .dw 0x27c0, 0xc809, 0x27ff, 0xc809, 0x21, 0 + .dw 0x2840, 0xc809, 0x287f, 0xc809, 0x21, 0 + .dw 0x28c0, 0xc809, 0x28ff, 0xc809, 0x21, 0 + .dw 0x2940, 0xc809, 0x297f, 0xc809, 0x21, 0 + .dw 0x29c0, 0xc809, 0x29ff, 0xc809, 0x21, 0 + .dw 0x2a40, 0xc809, 0x2a7f, 0xc809, 0x21, 0 + .dw 0x2ac0, 0xc809, 0x2aff, 0xc809, 0x21, 0 + .dw 0x2b40, 0xc809, 0x2b7f, 0xc809, 0x21, 0 + .dw 0x2bc0, 0xc809, 0x2bff, 0xc809, 0x21, 0 + .dw 0x2c40, 0xc809, 0x2c7f, 0xc809, 0x21, 0 + .dw 0x2cc0, 0xc809, 0x2cff, 0xc809, 0x21, 0 + .dw 0x2d40, 0xc809, 0x2d7f, 0xc809, 0x21, 0 + .dw 0x2dc0, 0xc809, 0x2dff, 0xc809, 0x21, 0 + .dw 0x2e40, 0xc809, 0x2e7f, 0xc809, 0x21, 0 + .dw 0x2ec0, 0xc809, 0x2eff, 0xc809, 0x21, 0 + .dw 0x2f40, 0xc809, 0x2f7f, 0xc809, 0x21, 0 + .dw 0x2fc0, 0xc809, 0x2fff, 0xc809, 0x21, 0 + .dw 0x3040, 0xc809, 0x307f, 0xc809, 0x21, 0 + .dw 0x30c0, 0xc809, 0x30ff, 0xc809, 0x21, 0 + .dw 0x3140, 0xc809, 0x317f, 0xc809, 0x21, 0 + .dw 0x31c0, 0xc809, 0x31ff, 0xc809, 0x21, 0 + .dw 0x3240, 0xc809, 0x327f, 0xc809, 0x21, 0 + .dw 0x32c0, 0xc809, 0x32ff, 0xc809, 0x21, 0 + .dw 0x3340, 0xc809, 0x337f, 0xc809, 0x21, 0 + .dw 0x33c0, 0xc809, 0x33ff, 0xc809, 0x21, 0 + .dw 0x3440, 0xc809, 0x347f, 0xc809, 0x21, 0 + .dw 0x34c0, 0xc809, 0x34ff, 0xc809, 0x21, 0 + .dw 0x3540, 0xc809, 0x357f, 0xc809, 0x21, 0 + .dw 0x35c0, 0xc809, 0x35ff, 0xc809, 0x21, 0 + .dw 0x3640, 0xc809, 0x367f, 0xc809, 0x21, 0 + .dw 0x36c0, 0xc809, 0x36ff, 0xc809, 0x21, 0 + .dw 0x3740, 0xc809, 0x377f, 0xc809, 0x21, 0 + .dw 0x37c0, 0xc809, 0x37ff, 0xc809, 0x21, 0 + .dw 0x3840, 0xc809, 0x387f, 0xc809, 0x21, 0 + .dw 0x38c0, 0xc809, 0x38ff, 0xc809, 0x21, 0 + .dw 0x3940, 0xc809, 0x397f, 0xc809, 0x21, 0 + .dw 0x39c0, 0xc809, 0x5fff, 0xc809, 0x21, 0 + .dw 0x6040, 0xc809, 0x607f, 0xc809, 0x21, 0 + .dw 0x60c0, 0xc809, 0x60ff, 0xc809, 0x21, 0 + .dw 0x6140, 0xc809, 0x617f, 0xc809, 0x21, 0 + .dw 0x61c0, 0xc809, 0x61ff, 0xc809, 0x21, 0 + .dw 0x6240, 0xc809, 0x627f, 0xc809, 0x21, 0 + .dw 0x62c0, 0xc809, 0x62ff, 0xc809, 0x21, 0 + .dw 0x6340, 0xc809, 0x637f, 0xc809, 0x21, 0 + .dw 0x63c0, 0xc809, 0x63ff, 0xc809, 0x21, 0 + .dw 0x6440, 0xc809, 0x647f, 0xc809, 0x21, 0 + .dw 0x64c0, 0xc809, 0x64ff, 0xc809, 0x21, 0 + .dw 0x6540, 0xc809, 0x657f, 0xc809, 0x21, 0 + .dw 0x65c0, 0xc809, 0x65ff, 0xc809, 0x21, 0 + .dw 0x6640, 0xc809, 0x667f, 0xc809, 0x21, 0 + .dw 0x66c0, 0xc809, 0x66ff, 0xc809, 0x21, 0 + .dw 0x6740, 0xc809, 0x677f, 0xc809, 0x21, 0 + .dw 0x67c0, 0xc809, 0x67ff, 0xc809, 0x21, 0 + .dw 0x6840, 0xc809, 0x687f, 0xc809, 0x21, 0 + .dw 0x68c0, 0xc809, 0x68ff, 0xc809, 0x21, 0 + .dw 0x6940, 0xc809, 0x697f, 0xc809, 0x21, 0 + .dw 0x69c0, 0xc809, 0x69ff, 0xc809, 0x21, 0 + .dw 0x6a40, 0xc809, 0x6a7f, 0xc809, 0x21, 0 + .dw 0x6ac0, 0xc809, 0x6aff, 0xc809, 0x21, 0 + .dw 0x6b40, 0xc809, 0x6b7f, 0xc809, 0x21, 0 + .dw 0x6bc0, 0xc809, 0x6bff, 0xc809, 0x21, 0 + .dw 0x6c40, 0xc809, 0x6c7f, 0xc809, 0x21, 0 + .dw 0x6cc0, 0xc809, 0x6cff, 0xc809, 0x21, 0 + .dw 0x6d40, 0xc809, 0x6d7f, 0xc809, 0x21, 0 + .dw 0x6dc0, 0xc809, 0x6dff, 0xc809, 0x21, 0 + .dw 0x6e40, 0xc809, 0x6e7f, 0xc809, 0x21, 0 + .dw 0x6ec0, 0xc809, 0x6eff, 0xc809, 0x21, 0 + .dw 0x6f40, 0xc809, 0x6f7f, 0xc809, 0x21, 0 + .dw 0x6fc0, 0xc809, 0x6fff, 0xc809, 0x21, 0 + .dw 0x7040, 0xc809, 0x707f, 0xc809, 0x21, 0 + .dw 0x70c0, 0xc809, 0x70ff, 0xc809, 0x21, 0 + .dw 0x7140, 0xc809, 0x717f, 0xc809, 0x21, 0 + .dw 0x71c0, 0xc809, 0x71ff, 0xc809, 0x21, 0 + .dw 0x7240, 0xc809, 0x727f, 0xc809, 0x21, 0 + .dw 0x72c0, 0xc809, 0x72ff, 0xc809, 0x21, 0 + .dw 0x7340, 0xc809, 0x737f, 0xc809, 0x21, 0 + .dw 0x73c0, 0xc809, 0x73ff, 0xc809, 0x21, 0 + .dw 0x7440, 0xc809, 0x747f, 0xc809, 0x21, 0 + .dw 0x74c0, 0xc809, 0x74ff, 0xc809, 0x21, 0 + .dw 0x7540, 0xc809, 0x757f, 0xc809, 0x21, 0 + .dw 0x75c0, 0xc809, 0x75ff, 0xc809, 0x21, 0 + .dw 0x7640, 0xc809, 0x767f, 0xc809, 0x21, 0 + .dw 0x76c0, 0xc809, 0x76ff, 0xc809, 0x21, 0 + .dw 0x7740, 0xc809, 0x777f, 0xc809, 0x21, 0 + .dw 0x77c0, 0xc809, 0x77ff, 0xc809, 0x21, 0 + .dw 0x7840, 0xc809, 0x787f, 0xc809, 0x21, 0 + .dw 0x78c0, 0xc809, 0x78ff, 0xc809, 0x21, 0 + .dw 0x7940, 0xc809, 0x797f, 0xc809, 0x21, 0 + .dw 0x79c0, 0xc809, 0x9fff, 0xc809, 0x21, 0 + .dw 0xa040, 0xc809, 0xa07f, 0xc809, 0x21, 0 + .dw 0xa0c0, 0xc809, 0xa0ff, 0xc809, 0x21, 0 + .dw 0xa140, 0xc809, 0xa17f, 0xc809, 0x21, 0 + .dw 0xa1c0, 0xc809, 0xa1ff, 0xc809, 0x21, 0 + .dw 0xa240, 0xc809, 0xa27f, 0xc809, 0x21, 0 + .dw 0xa2c0, 0xc809, 0xa2ff, 0xc809, 0x21, 0 + .dw 0xa340, 0xc809, 0xa37f, 0xc809, 0x21, 0 + .dw 0xa3c0, 0xc809, 0xa3ff, 0xc809, 0x21, 0 + .dw 0xa440, 0xc809, 0xa47f, 0xc809, 0x21, 0 + .dw 0xa4c0, 0xc809, 0xa4ff, 0xc809, 0x21, 0 + .dw 0xa540, 0xc809, 0xa57f, 0xc809, 0x21, 0 + .dw 0xa5c0, 0xc809, 0xa5ff, 0xc809, 0x21, 0 + .dw 0xa640, 0xc809, 0xa67f, 0xc809, 0x21, 0 + .dw 0xa6c0, 0xc809, 0xa6ff, 0xc809, 0x21, 0 + .dw 0xa740, 0xc809, 0xa77f, 0xc809, 0x21, 0 + .dw 0xa7c0, 0xc809, 0xa7ff, 0xc809, 0x21, 0 + .dw 0xa840, 0xc809, 0xa87f, 0xc809, 0x21, 0 + .dw 0xa8c0, 0xc809, 0xa8ff, 0xc809, 0x21, 0 + .dw 0xa940, 0xc809, 0xa97f, 0xc809, 0x21, 0 + .dw 0xa9c0, 0xc809, 0xa9ff, 0xc809, 0x21, 0 + .dw 0xaa40, 0xc809, 0xaa7f, 0xc809, 0x21, 0 + .dw 0xaac0, 0xc809, 0xaaff, 0xc809, 0x21, 0 + .dw 0xab40, 0xc809, 0xab7f, 0xc809, 0x21, 0 + .dw 0xabc0, 0xc809, 0xabff, 0xc809, 0x21, 0 + .dw 0xac40, 0xc809, 0xac7f, 0xc809, 0x21, 0 + .dw 0xacc0, 0xc809, 0xacff, 0xc809, 0x21, 0 + .dw 0xad40, 0xc809, 0xad7f, 0xc809, 0x21, 0 + .dw 0xadc0, 0xc809, 0xadff, 0xc809, 0x21, 0 + .dw 0xae40, 0xc809, 0xae7f, 0xc809, 0x21, 0 + .dw 0xaec0, 0xc809, 0xaeff, 0xc809, 0x21, 0 + .dw 0xaf40, 0xc809, 0xaf7f, 0xc809, 0x21, 0 + .dw 0xafc0, 0xc809, 0xafff, 0xc809, 0x21, 0 + .dw 0xb040, 0xc809, 0xb07f, 0xc809, 0x21, 0 + .dw 0xb0c0, 0xc809, 0xb0ff, 0xc809, 0x21, 0 + .dw 0xb140, 0xc809, 0xb17f, 0xc809, 0x21, 0 + .dw 0xb1c0, 0xc809, 0xb1ff, 0xc809, 0x21, 0 + .dw 0xb240, 0xc809, 0xb27f, 0xc809, 0x21, 0 + .dw 0xb2c0, 0xc809, 0xb2ff, 0xc809, 0x21, 0 + .dw 0xb340, 0xc809, 0xb37f, 0xc809, 0x21, 0 + .dw 0xb3c0, 0xc809, 0xb3ff, 0xc809, 0x21, 0 + .dw 0xb440, 0xc809, 0xb47f, 0xc809, 0x21, 0 + .dw 0xb4c0, 0xc809, 0xb4ff, 0xc809, 0x21, 0 + .dw 0xb540, 0xc809, 0xb57f, 0xc809, 0x21, 0 + .dw 0xb5c0, 0xc809, 0xb5ff, 0xc809, 0x21, 0 + .dw 0xb640, 0xc809, 0xb67f, 0xc809, 0x21, 0 + .dw 0xb6c0, 0xc809, 0xb6ff, 0xc809, 0x21, 0 + .dw 0xb740, 0xc809, 0xb77f, 0xc809, 0x21, 0 + .dw 0xb7c0, 0xc809, 0xb7ff, 0xc809, 0x21, 0 + .dw 0xb840, 0xc809, 0xb87f, 0xc809, 0x21, 0 + .dw 0xb8c0, 0xc809, 0xb8ff, 0xc809, 0x21, 0 + .dw 0xb940, 0xc809, 0xb97f, 0xc809, 0x21, 0 + .dw 0xb9c0, 0xc809, 0xdfff, 0xc809, 0x21, 0 + .dw 0xe040, 0xc809, 0xe07f, 0xc809, 0x21, 0 + .dw 0xe0c0, 0xc809, 0xe0ff, 0xc809, 0x21, 0 + .dw 0xe140, 0xc809, 0xe17f, 0xc809, 0x21, 0 + .dw 0xe1c0, 0xc809, 0xe1ff, 0xc809, 0x21, 0 + .dw 0xe240, 0xc809, 0xe27f, 0xc809, 0x21, 0 + .dw 0xe2c0, 0xc809, 0xe2ff, 0xc809, 0x21, 0 + .dw 0xe340, 0xc809, 0xe37f, 0xc809, 0x21, 0 + .dw 0xe3c0, 0xc809, 0xe3ff, 0xc809, 0x21, 0 + .dw 0xe440, 0xc809, 0xe47f, 0xc809, 0x21, 0 + .dw 0xe4c0, 0xc809, 0xe4ff, 0xc809, 0x21, 0 + .dw 0xe540, 0xc809, 0xe57f, 0xc809, 0x21, 0 + .dw 0xe5c0, 0xc809, 0xe5ff, 0xc809, 0x21, 0 + .dw 0xe640, 0xc809, 0xe67f, 0xc809, 0x21, 0 + .dw 0xe6c0, 0xc809, 0xe6ff, 0xc809, 0x21, 0 + .dw 0xe740, 0xc809, 0xe77f, 0xc809, 0x21, 0 + .dw 0xe7c0, 0xc809, 0xe7ff, 0xc809, 0x21, 0 + .dw 0xe840, 0xc809, 0xe87f, 0xc809, 0x21, 0 + .dw 0xe8c0, 0xc809, 0xe8ff, 0xc809, 0x21, 0 + .dw 0xe940, 0xc809, 0xe97f, 0xc809, 0x21, 0 + .dw 0xe9c0, 0xc809, 0xe9ff, 0xc809, 0x21, 0 + .dw 0xea40, 0xc809, 0xea7f, 0xc809, 0x21, 0 + .dw 0xeac0, 0xc809, 0xeaff, 0xc809, 0x21, 0 + .dw 0xeb40, 0xc809, 0xeb7f, 0xc809, 0x21, 0 + .dw 0xebc0, 0xc809, 0xebff, 0xc809, 0x21, 0 + .dw 0xec40, 0xc809, 0xec7f, 0xc809, 0x21, 0 + .dw 0xecc0, 0xc809, 0xecff, 0xc809, 0x21, 0 + .dw 0xed40, 0xc809, 0xed7f, 0xc809, 0x21, 0 + .dw 0xedc0, 0xc809, 0xedff, 0xc809, 0x21, 0 + .dw 0xee40, 0xc809, 0xee7f, 0xc809, 0x21, 0 + .dw 0xeec0, 0xc809, 0xeeff, 0xc809, 0x21, 0 + .dw 0xef40, 0xc809, 0xef7f, 0xc809, 0x21, 0 + .dw 0xefc0, 0xc809, 0xefff, 0xc809, 0x21, 0 + .dw 0xf040, 0xc809, 0xf07f, 0xc809, 0x21, 0 + .dw 0xf0c0, 0xc809, 0xf0ff, 0xc809, 0x21, 0 + .dw 0xf140, 0xc809, 0xf17f, 0xc809, 0x21, 0 + .dw 0xf1c0, 0xc809, 0xf1ff, 0xc809, 0x21, 0 + .dw 0xf240, 0xc809, 0xf27f, 0xc809, 0x21, 0 + .dw 0xf2c0, 0xc809, 0xf2ff, 0xc809, 0x21, 0 + .dw 0xf340, 0xc809, 0xf37f, 0xc809, 0x21, 0 + .dw 0xf3c0, 0xc809, 0xf3ff, 0xc809, 0x21, 0 + .dw 0xf440, 0xc809, 0xf47f, 0xc809, 0x21, 0 + .dw 0xf4c0, 0xc809, 0xf4ff, 0xc809, 0x21, 0 + .dw 0xf540, 0xc809, 0xf57f, 0xc809, 0x21, 0 + .dw 0xf5c0, 0xc809, 0xf5ff, 0xc809, 0x21, 0 + .dw 0xf640, 0xc809, 0xf67f, 0xc809, 0x21, 0 + .dw 0xf6c0, 0xc809, 0xf6ff, 0xc809, 0x21, 0 + .dw 0xf740, 0xc809, 0xf77f, 0xc809, 0x21, 0 + .dw 0xf7c0, 0xc809, 0xf7ff, 0xc809, 0x21, 0 + .dw 0xf840, 0xc809, 0xf87f, 0xc809, 0x21, 0 + .dw 0xf8c0, 0xc809, 0xf8ff, 0xc809, 0x21, 0 + .dw 0xf940, 0xc809, 0xf97f, 0xc809, 0x21, 0 + .dw 0xf9c0, 0xc809, 0x1fff, 0xc80a, 0x21, 0 + .dw 0x2040, 0xc80a, 0x207f, 0xc80a, 0x21, 0 + .dw 0x20c0, 0xc80a, 0x20ff, 0xc80a, 0x21, 0 + .dw 0x2140, 0xc80a, 0x217f, 0xc80a, 0x21, 0 + .dw 0x21c0, 0xc80a, 0x21ff, 0xc80a, 0x21, 0 + .dw 0x2240, 0xc80a, 0x227f, 0xc80a, 0x21, 0 + .dw 0x22c0, 0xc80a, 0x22ff, 0xc80a, 0x21, 0 + .dw 0x2340, 0xc80a, 0x237f, 0xc80a, 0x21, 0 + .dw 0x23c0, 0xc80a, 0x23ff, 0xc80a, 0x21, 0 + .dw 0x2440, 0xc80a, 0x247f, 0xc80a, 0x21, 0 + .dw 0x24c0, 0xc80a, 0x24ff, 0xc80a, 0x21, 0 + .dw 0x2540, 0xc80a, 0x257f, 0xc80a, 0x21, 0 + .dw 0x25c0, 0xc80a, 0x25ff, 0xc80a, 0x21, 0 + .dw 0x2640, 0xc80a, 0x267f, 0xc80a, 0x21, 0 + .dw 0x26c0, 0xc80a, 0x26ff, 0xc80a, 0x21, 0 + .dw 0x2740, 0xc80a, 0x277f, 0xc80a, 0x21, 0 + .dw 0x27c0, 0xc80a, 0x27ff, 0xc80a, 0x21, 0 + .dw 0x2840, 0xc80a, 0x287f, 0xc80a, 0x21, 0 + .dw 0x28c0, 0xc80a, 0x28ff, 0xc80a, 0x21, 0 + .dw 0x2940, 0xc80a, 0x297f, 0xc80a, 0x21, 0 + .dw 0x29c0, 0xc80a, 0x29ff, 0xc80a, 0x21, 0 + .dw 0x2a40, 0xc80a, 0x2a7f, 0xc80a, 0x21, 0 + .dw 0x2ac0, 0xc80a, 0x2aff, 0xc80a, 0x21, 0 + .dw 0x2b40, 0xc80a, 0x2b7f, 0xc80a, 0x21, 0 + .dw 0x2bc0, 0xc80a, 0x2bff, 0xc80a, 0x21, 0 + .dw 0x2c40, 0xc80a, 0x2c7f, 0xc80a, 0x21, 0 + .dw 0x2cc0, 0xc80a, 0x2cff, 0xc80a, 0x21, 0 + .dw 0x2d40, 0xc80a, 0x2d7f, 0xc80a, 0x21, 0 + .dw 0x2dc0, 0xc80a, 0x2dff, 0xc80a, 0x21, 0 + .dw 0x2e40, 0xc80a, 0x2e7f, 0xc80a, 0x21, 0 + .dw 0x2ec0, 0xc80a, 0x2eff, 0xc80a, 0x21, 0 + .dw 0x2f40, 0xc80a, 0x2f7f, 0xc80a, 0x21, 0 + .dw 0x2fc0, 0xc80a, 0x2fff, 0xc80a, 0x21, 0 + .dw 0x3040, 0xc80a, 0x307f, 0xc80a, 0x21, 0 + .dw 0x30c0, 0xc80a, 0x30ff, 0xc80a, 0x21, 0 + .dw 0x3140, 0xc80a, 0x317f, 0xc80a, 0x21, 0 + .dw 0x31c0, 0xc80a, 0x31ff, 0xc80a, 0x21, 0 + .dw 0x3240, 0xc80a, 0x327f, 0xc80a, 0x21, 0 + .dw 0x32c0, 0xc80a, 0x32ff, 0xc80a, 0x21, 0 + .dw 0x3340, 0xc80a, 0x337f, 0xc80a, 0x21, 0 + .dw 0x33c0, 0xc80a, 0x33ff, 0xc80a, 0x21, 0 + .dw 0x3440, 0xc80a, 0x347f, 0xc80a, 0x21, 0 + .dw 0x34c0, 0xc80a, 0x34ff, 0xc80a, 0x21, 0 + .dw 0x3540, 0xc80a, 0x357f, 0xc80a, 0x21, 0 + .dw 0x35c0, 0xc80a, 0x35ff, 0xc80a, 0x21, 0 + .dw 0x3640, 0xc80a, 0x367f, 0xc80a, 0x21, 0 + .dw 0x36c0, 0xc80a, 0x36ff, 0xc80a, 0x21, 0 + .dw 0x3740, 0xc80a, 0x377f, 0xc80a, 0x21, 0 + .dw 0x37c0, 0xc80a, 0x37ff, 0xc80a, 0x21, 0 + .dw 0x3840, 0xc80a, 0x387f, 0xc80a, 0x21, 0 + .dw 0x38c0, 0xc80a, 0x38ff, 0xc80a, 0x21, 0 + .dw 0x3940, 0xc80a, 0x397f, 0xc80a, 0x21, 0 + .dw 0x39c0, 0xc80a, 0x5fff, 0xc80a, 0x21, 0 + .dw 0x6040, 0xc80a, 0x607f, 0xc80a, 0x21, 0 + .dw 0x60c0, 0xc80a, 0x60ff, 0xc80a, 0x21, 0 + .dw 0x6140, 0xc80a, 0x617f, 0xc80a, 0x21, 0 + .dw 0x61c0, 0xc80a, 0x61ff, 0xc80a, 0x21, 0 + .dw 0x6240, 0xc80a, 0x627f, 0xc80a, 0x21, 0 + .dw 0x62c0, 0xc80a, 0x62ff, 0xc80a, 0x21, 0 + .dw 0x6340, 0xc80a, 0x637f, 0xc80a, 0x21, 0 + .dw 0x63c0, 0xc80a, 0x63ff, 0xc80a, 0x21, 0 + .dw 0x6440, 0xc80a, 0x647f, 0xc80a, 0x21, 0 + .dw 0x64c0, 0xc80a, 0x64ff, 0xc80a, 0x21, 0 + .dw 0x6540, 0xc80a, 0x657f, 0xc80a, 0x21, 0 + .dw 0x65c0, 0xc80a, 0x65ff, 0xc80a, 0x21, 0 + .dw 0x6640, 0xc80a, 0x667f, 0xc80a, 0x21, 0 + .dw 0x66c0, 0xc80a, 0x66ff, 0xc80a, 0x21, 0 + .dw 0x6740, 0xc80a, 0x677f, 0xc80a, 0x21, 0 + .dw 0x67c0, 0xc80a, 0x67ff, 0xc80a, 0x21, 0 + .dw 0x6840, 0xc80a, 0x687f, 0xc80a, 0x21, 0 + .dw 0x68c0, 0xc80a, 0x68ff, 0xc80a, 0x21, 0 + .dw 0x6940, 0xc80a, 0x697f, 0xc80a, 0x21, 0 + .dw 0x69c0, 0xc80a, 0x69ff, 0xc80a, 0x21, 0 + .dw 0x6a40, 0xc80a, 0x6a7f, 0xc80a, 0x21, 0 + .dw 0x6ac0, 0xc80a, 0x6aff, 0xc80a, 0x21, 0 + .dw 0x6b40, 0xc80a, 0x6b7f, 0xc80a, 0x21, 0 + .dw 0x6bc0, 0xc80a, 0x6bff, 0xc80a, 0x21, 0 + .dw 0x6c40, 0xc80a, 0x6c7f, 0xc80a, 0x21, 0 + .dw 0x6cc0, 0xc80a, 0x6cff, 0xc80a, 0x21, 0 + .dw 0x6d40, 0xc80a, 0x6d7f, 0xc80a, 0x21, 0 + .dw 0x6dc0, 0xc80a, 0x6dff, 0xc80a, 0x21, 0 + .dw 0x6e40, 0xc80a, 0x6e7f, 0xc80a, 0x21, 0 + .dw 0x6ec0, 0xc80a, 0x6eff, 0xc80a, 0x21, 0 + .dw 0x6f40, 0xc80a, 0x6f7f, 0xc80a, 0x21, 0 + .dw 0x6fc0, 0xc80a, 0x6fff, 0xc80a, 0x21, 0 + .dw 0x7040, 0xc80a, 0x707f, 0xc80a, 0x21, 0 + .dw 0x70c0, 0xc80a, 0x70ff, 0xc80a, 0x21, 0 + .dw 0x7140, 0xc80a, 0x717f, 0xc80a, 0x21, 0 + .dw 0x71c0, 0xc80a, 0x71ff, 0xc80a, 0x21, 0 + .dw 0x7240, 0xc80a, 0x727f, 0xc80a, 0x21, 0 + .dw 0x72c0, 0xc80a, 0x72ff, 0xc80a, 0x21, 0 + .dw 0x7340, 0xc80a, 0x737f, 0xc80a, 0x21, 0 + .dw 0x73c0, 0xc80a, 0x73ff, 0xc80a, 0x21, 0 + .dw 0x7440, 0xc80a, 0x747f, 0xc80a, 0x21, 0 + .dw 0x74c0, 0xc80a, 0x74ff, 0xc80a, 0x21, 0 + .dw 0x7540, 0xc80a, 0x757f, 0xc80a, 0x21, 0 + .dw 0x75c0, 0xc80a, 0x75ff, 0xc80a, 0x21, 0 + .dw 0x7640, 0xc80a, 0x767f, 0xc80a, 0x21, 0 + .dw 0x76c0, 0xc80a, 0x76ff, 0xc80a, 0x21, 0 + .dw 0x7740, 0xc80a, 0x777f, 0xc80a, 0x21, 0 + .dw 0x77c0, 0xc80a, 0x77ff, 0xc80a, 0x21, 0 + .dw 0x7840, 0xc80a, 0x787f, 0xc80a, 0x21, 0 + .dw 0x78c0, 0xc80a, 0x78ff, 0xc80a, 0x21, 0 + .dw 0x7940, 0xc80a, 0x797f, 0xc80a, 0x21, 0 + .dw 0x79c0, 0xc80a, 0x9fff, 0xc80a, 0x21, 0 + .dw 0xa040, 0xc80a, 0xa07f, 0xc80a, 0x21, 0 + .dw 0xa0c0, 0xc80a, 0xa0ff, 0xc80a, 0x21, 0 + .dw 0xa140, 0xc80a, 0xa17f, 0xc80a, 0x21, 0 + .dw 0xa1c0, 0xc80a, 0xa1ff, 0xc80a, 0x21, 0 + .dw 0xa240, 0xc80a, 0xa27f, 0xc80a, 0x21, 0 + .dw 0xa2c0, 0xc80a, 0xa2ff, 0xc80a, 0x21, 0 + .dw 0xa340, 0xc80a, 0xa37f, 0xc80a, 0x21, 0 + .dw 0xa3c0, 0xc80a, 0xa3ff, 0xc80a, 0x21, 0 + .dw 0xa440, 0xc80a, 0xa47f, 0xc80a, 0x21, 0 + .dw 0xa4c0, 0xc80a, 0xa4ff, 0xc80a, 0x21, 0 + .dw 0xa540, 0xc80a, 0xa57f, 0xc80a, 0x21, 0 + .dw 0xa5c0, 0xc80a, 0xa5ff, 0xc80a, 0x21, 0 + .dw 0xa640, 0xc80a, 0xa67f, 0xc80a, 0x21, 0 + .dw 0xa6c0, 0xc80a, 0xa6ff, 0xc80a, 0x21, 0 + .dw 0xa740, 0xc80a, 0xa77f, 0xc80a, 0x21, 0 + .dw 0xa7c0, 0xc80a, 0xa7ff, 0xc80a, 0x21, 0 + .dw 0xa840, 0xc80a, 0xa87f, 0xc80a, 0x21, 0 + .dw 0xa8c0, 0xc80a, 0xa8ff, 0xc80a, 0x21, 0 + .dw 0xa940, 0xc80a, 0xa97f, 0xc80a, 0x21, 0 + .dw 0xa9c0, 0xc80a, 0xa9ff, 0xc80a, 0x21, 0 + .dw 0xaa40, 0xc80a, 0xaa7f, 0xc80a, 0x21, 0 + .dw 0xaac0, 0xc80a, 0xaaff, 0xc80a, 0x21, 0 + .dw 0xab40, 0xc80a, 0xab7f, 0xc80a, 0x21, 0 + .dw 0xabc0, 0xc80a, 0xabff, 0xc80a, 0x21, 0 + .dw 0xac40, 0xc80a, 0xac7f, 0xc80a, 0x21, 0 + .dw 0xacc0, 0xc80a, 0xacff, 0xc80a, 0x21, 0 + .dw 0xad40, 0xc80a, 0xad7f, 0xc80a, 0x21, 0 + .dw 0xadc0, 0xc80a, 0xadff, 0xc80a, 0x21, 0 + .dw 0xae40, 0xc80a, 0xae7f, 0xc80a, 0x21, 0 + .dw 0xaec0, 0xc80a, 0xaeff, 0xc80a, 0x21, 0 + .dw 0xaf40, 0xc80a, 0xaf7f, 0xc80a, 0x21, 0 + .dw 0xafc0, 0xc80a, 0xafff, 0xc80a, 0x21, 0 + .dw 0xb040, 0xc80a, 0xb07f, 0xc80a, 0x21, 0 + .dw 0xb0c0, 0xc80a, 0xb0ff, 0xc80a, 0x21, 0 + .dw 0xb140, 0xc80a, 0xb17f, 0xc80a, 0x21, 0 + .dw 0xb1c0, 0xc80a, 0xb1ff, 0xc80a, 0x21, 0 + .dw 0xb240, 0xc80a, 0xb27f, 0xc80a, 0x21, 0 + .dw 0xb2c0, 0xc80a, 0xb2ff, 0xc80a, 0x21, 0 + .dw 0xb340, 0xc80a, 0xb37f, 0xc80a, 0x21, 0 + .dw 0xb3c0, 0xc80a, 0xb3ff, 0xc80a, 0x21, 0 + .dw 0xb440, 0xc80a, 0xb47f, 0xc80a, 0x21, 0 + .dw 0xb4c0, 0xc80a, 0xb4ff, 0xc80a, 0x21, 0 + .dw 0xb540, 0xc80a, 0xb57f, 0xc80a, 0x21, 0 + .dw 0xb5c0, 0xc80a, 0xb5ff, 0xc80a, 0x21, 0 + .dw 0xb640, 0xc80a, 0xb67f, 0xc80a, 0x21, 0 + .dw 0xb6c0, 0xc80a, 0xb6ff, 0xc80a, 0x21, 0 + .dw 0xb740, 0xc80a, 0xb77f, 0xc80a, 0x21, 0 + .dw 0xb7c0, 0xc80a, 0xb7ff, 0xc80a, 0x21, 0 + .dw 0xb840, 0xc80a, 0xb87f, 0xc80a, 0x21, 0 + .dw 0xb8c0, 0xc80a, 0xb8ff, 0xc80a, 0x21, 0 + .dw 0xb940, 0xc80a, 0xb97f, 0xc80a, 0x21, 0 + .dw 0xb9c0, 0xc80a, 0xdfff, 0xc80a, 0x21, 0 + .dw 0xe040, 0xc80a, 0xe07f, 0xc80a, 0x21, 0 + .dw 0xe0c0, 0xc80a, 0xe0ff, 0xc80a, 0x21, 0 + .dw 0xe140, 0xc80a, 0xe17f, 0xc80a, 0x21, 0 + .dw 0xe1c0, 0xc80a, 0xe1ff, 0xc80a, 0x21, 0 + .dw 0xe240, 0xc80a, 0xe27f, 0xc80a, 0x21, 0 + .dw 0xe2c0, 0xc80a, 0xe2ff, 0xc80a, 0x21, 0 + .dw 0xe340, 0xc80a, 0xe37f, 0xc80a, 0x21, 0 + .dw 0xe3c0, 0xc80a, 0xe3ff, 0xc80a, 0x21, 0 + .dw 0xe440, 0xc80a, 0xe47f, 0xc80a, 0x21, 0 + .dw 0xe4c0, 0xc80a, 0xe4ff, 0xc80a, 0x21, 0 + .dw 0xe540, 0xc80a, 0xe57f, 0xc80a, 0x21, 0 + .dw 0xe5c0, 0xc80a, 0xe5ff, 0xc80a, 0x21, 0 + .dw 0xe640, 0xc80a, 0xe67f, 0xc80a, 0x21, 0 + .dw 0xe6c0, 0xc80a, 0xe6ff, 0xc80a, 0x21, 0 + .dw 0xe740, 0xc80a, 0xe77f, 0xc80a, 0x21, 0 + .dw 0xe7c0, 0xc80a, 0xe7ff, 0xc80a, 0x21, 0 + .dw 0xe840, 0xc80a, 0xe87f, 0xc80a, 0x21, 0 + .dw 0xe8c0, 0xc80a, 0xe8ff, 0xc80a, 0x21, 0 + .dw 0xe940, 0xc80a, 0xe97f, 0xc80a, 0x21, 0 + .dw 0xe9c0, 0xc80a, 0xe9ff, 0xc80a, 0x21, 0 + .dw 0xea40, 0xc80a, 0xea7f, 0xc80a, 0x21, 0 + .dw 0xeac0, 0xc80a, 0xeaff, 0xc80a, 0x21, 0 + .dw 0xeb40, 0xc80a, 0xeb7f, 0xc80a, 0x21, 0 + .dw 0xebc0, 0xc80a, 0xebff, 0xc80a, 0x21, 0 + .dw 0xec40, 0xc80a, 0xec7f, 0xc80a, 0x21, 0 + .dw 0xecc0, 0xc80a, 0xecff, 0xc80a, 0x21, 0 + .dw 0xed40, 0xc80a, 0xed7f, 0xc80a, 0x21, 0 + .dw 0xedc0, 0xc80a, 0xedff, 0xc80a, 0x21, 0 + .dw 0xee40, 0xc80a, 0xee7f, 0xc80a, 0x21, 0 + .dw 0xeec0, 0xc80a, 0xeeff, 0xc80a, 0x21, 0 + .dw 0xef40, 0xc80a, 0xef7f, 0xc80a, 0x21, 0 + .dw 0xefc0, 0xc80a, 0xefff, 0xc80a, 0x21, 0 + .dw 0xf040, 0xc80a, 0xf07f, 0xc80a, 0x21, 0 + .dw 0xf0c0, 0xc80a, 0xf0ff, 0xc80a, 0x21, 0 + .dw 0xf140, 0xc80a, 0xf17f, 0xc80a, 0x21, 0 + .dw 0xf1c0, 0xc80a, 0xf1ff, 0xc80a, 0x21, 0 + .dw 0xf240, 0xc80a, 0xf27f, 0xc80a, 0x21, 0 + .dw 0xf2c0, 0xc80a, 0xf2ff, 0xc80a, 0x21, 0 + .dw 0xf340, 0xc80a, 0xf37f, 0xc80a, 0x21, 0 + .dw 0xf3c0, 0xc80a, 0xf3ff, 0xc80a, 0x21, 0 + .dw 0xf440, 0xc80a, 0xf47f, 0xc80a, 0x21, 0 + .dw 0xf4c0, 0xc80a, 0xf4ff, 0xc80a, 0x21, 0 + .dw 0xf540, 0xc80a, 0xf57f, 0xc80a, 0x21, 0 + .dw 0xf5c0, 0xc80a, 0xf5ff, 0xc80a, 0x21, 0 + .dw 0xf640, 0xc80a, 0xf67f, 0xc80a, 0x21, 0 + .dw 0xf6c0, 0xc80a, 0xf6ff, 0xc80a, 0x21, 0 + .dw 0xf740, 0xc80a, 0xf77f, 0xc80a, 0x21, 0 + .dw 0xf7c0, 0xc80a, 0xf7ff, 0xc80a, 0x21, 0 + .dw 0xf840, 0xc80a, 0xf87f, 0xc80a, 0x21, 0 + .dw 0xf8c0, 0xc80a, 0xf8ff, 0xc80a, 0x21, 0 + .dw 0xf940, 0xc80a, 0xf97f, 0xc80a, 0x21, 0 + .dw 0xf9c0, 0xc80a, 0x1fff, 0xc80b, 0x21, 0 + .dw 0x2040, 0xc80b, 0x207f, 0xc80b, 0x21, 0 + .dw 0x20c0, 0xc80b, 0x20ff, 0xc80b, 0x21, 0 + .dw 0x2140, 0xc80b, 0x217f, 0xc80b, 0x21, 0 + .dw 0x21c0, 0xc80b, 0x21ff, 0xc80b, 0x21, 0 + .dw 0x2240, 0xc80b, 0x227f, 0xc80b, 0x21, 0 + .dw 0x22c0, 0xc80b, 0x22ff, 0xc80b, 0x21, 0 + .dw 0x2340, 0xc80b, 0x237f, 0xc80b, 0x21, 0 + .dw 0x23c0, 0xc80b, 0x23ff, 0xc80b, 0x21, 0 + .dw 0x2440, 0xc80b, 0x247f, 0xc80b, 0x21, 0 + .dw 0x24c0, 0xc80b, 0x24ff, 0xc80b, 0x21, 0 + .dw 0x2540, 0xc80b, 0x257f, 0xc80b, 0x21, 0 + .dw 0x25c0, 0xc80b, 0x25ff, 0xc80b, 0x21, 0 + .dw 0x2640, 0xc80b, 0x267f, 0xc80b, 0x21, 0 + .dw 0x26c0, 0xc80b, 0x26ff, 0xc80b, 0x21, 0 + .dw 0x2740, 0xc80b, 0x277f, 0xc80b, 0x21, 0 + .dw 0x27c0, 0xc80b, 0x27ff, 0xc80b, 0x21, 0 + .dw 0x2840, 0xc80b, 0x287f, 0xc80b, 0x21, 0 + .dw 0x28c0, 0xc80b, 0x28ff, 0xc80b, 0x21, 0 + .dw 0x2940, 0xc80b, 0x297f, 0xc80b, 0x21, 0 + .dw 0x29c0, 0xc80b, 0x29ff, 0xc80b, 0x21, 0 + .dw 0x2a40, 0xc80b, 0x2a7f, 0xc80b, 0x21, 0 + .dw 0x2ac0, 0xc80b, 0x2aff, 0xc80b, 0x21, 0 + .dw 0x2b40, 0xc80b, 0x2b7f, 0xc80b, 0x21, 0 + .dw 0x2bc0, 0xc80b, 0x2bff, 0xc80b, 0x21, 0 + .dw 0x2c40, 0xc80b, 0x2c7f, 0xc80b, 0x21, 0 + .dw 0x2cc0, 0xc80b, 0x2cff, 0xc80b, 0x21, 0 + .dw 0x2d40, 0xc80b, 0x2d7f, 0xc80b, 0x21, 0 + .dw 0x2dc0, 0xc80b, 0x2dff, 0xc80b, 0x21, 0 + .dw 0x2e40, 0xc80b, 0x2e7f, 0xc80b, 0x21, 0 + .dw 0x2ec0, 0xc80b, 0x2eff, 0xc80b, 0x21, 0 + .dw 0x2f40, 0xc80b, 0x2f7f, 0xc80b, 0x21, 0 + .dw 0x2fc0, 0xc80b, 0x2fff, 0xc80b, 0x21, 0 + .dw 0x3040, 0xc80b, 0x307f, 0xc80b, 0x21, 0 + .dw 0x30c0, 0xc80b, 0x30ff, 0xc80b, 0x21, 0 + .dw 0x3140, 0xc80b, 0x317f, 0xc80b, 0x21, 0 + .dw 0x31c0, 0xc80b, 0x31ff, 0xc80b, 0x21, 0 + .dw 0x3240, 0xc80b, 0x327f, 0xc80b, 0x21, 0 + .dw 0x32c0, 0xc80b, 0x32ff, 0xc80b, 0x21, 0 + .dw 0x3340, 0xc80b, 0x337f, 0xc80b, 0x21, 0 + .dw 0x33c0, 0xc80b, 0x33ff, 0xc80b, 0x21, 0 + .dw 0x3440, 0xc80b, 0x347f, 0xc80b, 0x21, 0 + .dw 0x34c0, 0xc80b, 0x34ff, 0xc80b, 0x21, 0 + .dw 0x3540, 0xc80b, 0x357f, 0xc80b, 0x21, 0 + .dw 0x35c0, 0xc80b, 0x35ff, 0xc80b, 0x21, 0 + .dw 0x3640, 0xc80b, 0x367f, 0xc80b, 0x21, 0 + .dw 0x36c0, 0xc80b, 0x36ff, 0xc80b, 0x21, 0 + .dw 0x3740, 0xc80b, 0x377f, 0xc80b, 0x21, 0 + .dw 0x37c0, 0xc80b, 0x37ff, 0xc80b, 0x21, 0 + .dw 0x3840, 0xc80b, 0x387f, 0xc80b, 0x21, 0 + .dw 0x38c0, 0xc80b, 0x38ff, 0xc80b, 0x21, 0 + .dw 0x3940, 0xc80b, 0x397f, 0xc80b, 0x21, 0 + .dw 0x39c0, 0xc80b, 0xffff, 0xc80b, 0x21, 0 + .dw 0x0040, 0xc80c, 0x007f, 0xc80c, 0x21, 0 + .dw 0x00c0, 0xc80c, 0x00ff, 0xc80c, 0x21, 0 + .dw 0x0140, 0xc80c, 0x017f, 0xc80c, 0x21, 0 + .dw 0x01c0, 0xc80c, 0x01ff, 0xc80c, 0x21, 0 + .dw 0x0240, 0xc80c, 0x027f, 0xc80c, 0x21, 0 + .dw 0x02c0, 0xc80c, 0x02ff, 0xc80c, 0x21, 0 + .dw 0x0340, 0xc80c, 0x037f, 0xc80c, 0x21, 0 + .dw 0x03c0, 0xc80c, 0x03ff, 0xc80c, 0x21, 0 + .dw 0x0440, 0xc80c, 0x047f, 0xc80c, 0x21, 0 + .dw 0x04c0, 0xc80c, 0x04ff, 0xc80c, 0x21, 0 + .dw 0x0540, 0xc80c, 0x057f, 0xc80c, 0x21, 0 + .dw 0x05c0, 0xc80c, 0x05ff, 0xc80c, 0x21, 0 + .dw 0x0640, 0xc80c, 0x067f, 0xc80c, 0x21, 0 + .dw 0x06c0, 0xc80c, 0x06ff, 0xc80c, 0x21, 0 + .dw 0x0740, 0xc80c, 0x077f, 0xc80c, 0x21, 0 + .dw 0x07c0, 0xc80c, 0x07ff, 0xc80c, 0x21, 0 + .dw 0x0840, 0xc80c, 0x087f, 0xc80c, 0x21, 0 + .dw 0x08c0, 0xc80c, 0x08ff, 0xc80c, 0x21, 0 + .dw 0x0940, 0xc80c, 0x097f, 0xc80c, 0x21, 0 + .dw 0x09c0, 0xc80c, 0x09ff, 0xc80c, 0x21, 0 + .dw 0x0a40, 0xc80c, 0x0a7f, 0xc80c, 0x21, 0 + .dw 0x0ac0, 0xc80c, 0x0aff, 0xc80c, 0x21, 0 + .dw 0x0b40, 0xc80c, 0x0b7f, 0xc80c, 0x21, 0 + .dw 0x0bc0, 0xc80c, 0x0bff, 0xc80c, 0x21, 0 + .dw 0x0c40, 0xc80c, 0x0c7f, 0xc80c, 0x21, 0 + .dw 0x0cc0, 0xc80c, 0x0cff, 0xc80c, 0x21, 0 + .dw 0x0d40, 0xc80c, 0x0d7f, 0xc80c, 0x21, 0 + .dw 0x0dc0, 0xc80c, 0x0dff, 0xc80c, 0x21, 0 + .dw 0x0e40, 0xc80c, 0x0e7f, 0xc80c, 0x21, 0 + .dw 0x0ec0, 0xc80c, 0x0eff, 0xc80c, 0x21, 0 + .dw 0x0f40, 0xc80c, 0x0f7f, 0xc80c, 0x21, 0 + .dw 0x0fc0, 0xc80c, 0x0fff, 0xc80c, 0x21, 0 + .dw 0x1040, 0xc80c, 0x107f, 0xc80c, 0x21, 0 + .dw 0x10c0, 0xc80c, 0x10ff, 0xc80c, 0x21, 0 + .dw 0x1140, 0xc80c, 0x117f, 0xc80c, 0x21, 0 + .dw 0x11c0, 0xc80c, 0x11ff, 0xc80c, 0x21, 0 + .dw 0x1240, 0xc80c, 0x127f, 0xc80c, 0x21, 0 + .dw 0x12c0, 0xc80c, 0x12ff, 0xc80c, 0x21, 0 + .dw 0x1340, 0xc80c, 0x137f, 0xc80c, 0x21, 0 + .dw 0x13c0, 0xc80c, 0x13ff, 0xc80c, 0x21, 0 + .dw 0x1440, 0xc80c, 0x147f, 0xc80c, 0x21, 0 + .dw 0x14c0, 0xc80c, 0x14ff, 0xc80c, 0x21, 0 + .dw 0x1540, 0xc80c, 0x157f, 0xc80c, 0x21, 0 + .dw 0x15c0, 0xc80c, 0x15ff, 0xc80c, 0x21, 0 + .dw 0x1640, 0xc80c, 0x167f, 0xc80c, 0x21, 0 + .dw 0x16c0, 0xc80c, 0x16ff, 0xc80c, 0x21, 0 + .dw 0x1740, 0xc80c, 0x177f, 0xc80c, 0x21, 0 + .dw 0x17c0, 0xc80c, 0x17ff, 0xc80c, 0x21, 0 + .dw 0x1840, 0xc80c, 0x187f, 0xc80c, 0x21, 0 + .dw 0x18c0, 0xc80c, 0x18ff, 0xc80c, 0x21, 0 + .dw 0x1940, 0xc80c, 0x197f, 0xc80c, 0x21, 0 + .dw 0x19c0, 0xc80c, 0x1fff, 0xc80c, 0x21, 0 + .dw 0x2040, 0xc80c, 0x207f, 0xc80c, 0x21, 0 + .dw 0x20c0, 0xc80c, 0x20ff, 0xc80c, 0x21, 0 + .dw 0x2140, 0xc80c, 0x217f, 0xc80c, 0x21, 0 + .dw 0x21c0, 0xc80c, 0x21ff, 0xc80c, 0x21, 0 + .dw 0x2240, 0xc80c, 0x227f, 0xc80c, 0x21, 0 + .dw 0x22c0, 0xc80c, 0x22ff, 0xc80c, 0x21, 0 + .dw 0x2340, 0xc80c, 0x237f, 0xc80c, 0x21, 0 + .dw 0x23c0, 0xc80c, 0x23ff, 0xc80c, 0x21, 0 + .dw 0x2440, 0xc80c, 0x247f, 0xc80c, 0x21, 0 + .dw 0x24c0, 0xc80c, 0x24ff, 0xc80c, 0x21, 0 + .dw 0x2540, 0xc80c, 0x257f, 0xc80c, 0x21, 0 + .dw 0x25c0, 0xc80c, 0x25ff, 0xc80c, 0x21, 0 + .dw 0x2640, 0xc80c, 0x267f, 0xc80c, 0x21, 0 + .dw 0x26c0, 0xc80c, 0x26ff, 0xc80c, 0x21, 0 + .dw 0x2740, 0xc80c, 0x277f, 0xc80c, 0x21, 0 + .dw 0x27c0, 0xc80c, 0x27ff, 0xc80c, 0x21, 0 + .dw 0x2840, 0xc80c, 0x287f, 0xc80c, 0x21, 0 + .dw 0x28c0, 0xc80c, 0x28ff, 0xc80c, 0x21, 0 + .dw 0x2940, 0xc80c, 0x297f, 0xc80c, 0x21, 0 + .dw 0x29c0, 0xc80c, 0x29ff, 0xc80c, 0x21, 0 + .dw 0x2a40, 0xc80c, 0x2a7f, 0xc80c, 0x21, 0 + .dw 0x2ac0, 0xc80c, 0x2aff, 0xc80c, 0x21, 0 + .dw 0x2b40, 0xc80c, 0x2b7f, 0xc80c, 0x21, 0 + .dw 0x2bc0, 0xc80c, 0x2bff, 0xc80c, 0x21, 0 + .dw 0x2c40, 0xc80c, 0x2c7f, 0xc80c, 0x21, 0 + .dw 0x2cc0, 0xc80c, 0x2cff, 0xc80c, 0x21, 0 + .dw 0x2d40, 0xc80c, 0x2d7f, 0xc80c, 0x21, 0 + .dw 0x2dc0, 0xc80c, 0x2dff, 0xc80c, 0x21, 0 + .dw 0x2e40, 0xc80c, 0x2e7f, 0xc80c, 0x21, 0 + .dw 0x2ec0, 0xc80c, 0x2eff, 0xc80c, 0x21, 0 + .dw 0x2f40, 0xc80c, 0x2f7f, 0xc80c, 0x21, 0 + .dw 0x2fc0, 0xc80c, 0x2fff, 0xc80c, 0x21, 0 + .dw 0x3040, 0xc80c, 0x307f, 0xc80c, 0x21, 0 + .dw 0x30c0, 0xc80c, 0x30ff, 0xc80c, 0x21, 0 + .dw 0x3140, 0xc80c, 0x317f, 0xc80c, 0x21, 0 + .dw 0x31c0, 0xc80c, 0x31ff, 0xc80c, 0x21, 0 + .dw 0x3240, 0xc80c, 0x327f, 0xc80c, 0x21, 0 + .dw 0x32c0, 0xc80c, 0x32ff, 0xc80c, 0x21, 0 + .dw 0x3340, 0xc80c, 0x337f, 0xc80c, 0x21, 0 + .dw 0x33c0, 0xc80c, 0x33ff, 0xc80c, 0x21, 0 + .dw 0x3440, 0xc80c, 0x347f, 0xc80c, 0x21, 0 + .dw 0x34c0, 0xc80c, 0x34ff, 0xc80c, 0x21, 0 + .dw 0x3540, 0xc80c, 0x357f, 0xc80c, 0x21, 0 + .dw 0x35c0, 0xc80c, 0x35ff, 0xc80c, 0x21, 0 + .dw 0x3640, 0xc80c, 0x367f, 0xc80c, 0x21, 0 + .dw 0x36c0, 0xc80c, 0x36ff, 0xc80c, 0x21, 0 + .dw 0x3740, 0xc80c, 0x377f, 0xc80c, 0x21, 0 + .dw 0x37c0, 0xc80c, 0x37ff, 0xc80c, 0x21, 0 + .dw 0x3840, 0xc80c, 0x387f, 0xc80c, 0x21, 0 + .dw 0x38c0, 0xc80c, 0x38ff, 0xc80c, 0x21, 0 + .dw 0x3940, 0xc80c, 0x397f, 0xc80c, 0x21, 0 + .dw 0x39c0, 0xc80c, 0x3fff, 0xc80c, 0x21, 0 + .dw 0x4040, 0xc80c, 0x407f, 0xc80c, 0x21, 0 + .dw 0x40c0, 0xc80c, 0x40ff, 0xc80c, 0x21, 0 + .dw 0x4140, 0xc80c, 0x417f, 0xc80c, 0x21, 0 + .dw 0x41c0, 0xc80c, 0x41ff, 0xc80c, 0x21, 0 + .dw 0x4240, 0xc80c, 0x427f, 0xc80c, 0x21, 0 + .dw 0x42c0, 0xc80c, 0x42ff, 0xc80c, 0x21, 0 + .dw 0x4340, 0xc80c, 0x437f, 0xc80c, 0x21, 0 + .dw 0x43c0, 0xc80c, 0x43ff, 0xc80c, 0x21, 0 + .dw 0x4440, 0xc80c, 0x447f, 0xc80c, 0x21, 0 + .dw 0x44c0, 0xc80c, 0x44ff, 0xc80c, 0x21, 0 + .dw 0x4540, 0xc80c, 0x457f, 0xc80c, 0x21, 0 + .dw 0x45c0, 0xc80c, 0x45ff, 0xc80c, 0x21, 0 + .dw 0x4640, 0xc80c, 0x467f, 0xc80c, 0x21, 0 + .dw 0x46c0, 0xc80c, 0x46ff, 0xc80c, 0x21, 0 + .dw 0x4740, 0xc80c, 0x477f, 0xc80c, 0x21, 0 + .dw 0x47c0, 0xc80c, 0x47ff, 0xc80c, 0x21, 0 + .dw 0x4840, 0xc80c, 0x487f, 0xc80c, 0x21, 0 + .dw 0x48c0, 0xc80c, 0x48ff, 0xc80c, 0x21, 0 + .dw 0x4940, 0xc80c, 0x497f, 0xc80c, 0x21, 0 + .dw 0x49c0, 0xc80c, 0x49ff, 0xc80c, 0x21, 0 + .dw 0x4a40, 0xc80c, 0x4a7f, 0xc80c, 0x21, 0 + .dw 0x4ac0, 0xc80c, 0x4aff, 0xc80c, 0x21, 0 + .dw 0x4b40, 0xc80c, 0x4b7f, 0xc80c, 0x21, 0 + .dw 0x4bc0, 0xc80c, 0x4bff, 0xc80c, 0x21, 0 + .dw 0x4c40, 0xc80c, 0x4c7f, 0xc80c, 0x21, 0 + .dw 0x4cc0, 0xc80c, 0x4cff, 0xc80c, 0x21, 0 + .dw 0x4d40, 0xc80c, 0x4d7f, 0xc80c, 0x21, 0 + .dw 0x4dc0, 0xc80c, 0x4dff, 0xc80c, 0x21, 0 + .dw 0x4e40, 0xc80c, 0x4e7f, 0xc80c, 0x21, 0 + .dw 0x4ec0, 0xc80c, 0x4eff, 0xc80c, 0x21, 0 + .dw 0x4f40, 0xc80c, 0x4f7f, 0xc80c, 0x21, 0 + .dw 0x4fc0, 0xc80c, 0x4fff, 0xc80c, 0x21, 0 + .dw 0x5040, 0xc80c, 0x507f, 0xc80c, 0x21, 0 + .dw 0x50c0, 0xc80c, 0x50ff, 0xc80c, 0x21, 0 + .dw 0x5140, 0xc80c, 0x517f, 0xc80c, 0x21, 0 + .dw 0x51c0, 0xc80c, 0x51ff, 0xc80c, 0x21, 0 + .dw 0x5240, 0xc80c, 0x527f, 0xc80c, 0x21, 0 + .dw 0x52c0, 0xc80c, 0x52ff, 0xc80c, 0x21, 0 + .dw 0x5340, 0xc80c, 0x537f, 0xc80c, 0x21, 0 + .dw 0x53c0, 0xc80c, 0x53ff, 0xc80c, 0x21, 0 + .dw 0x5440, 0xc80c, 0x547f, 0xc80c, 0x21, 0 + .dw 0x54c0, 0xc80c, 0x54ff, 0xc80c, 0x21, 0 + .dw 0x5540, 0xc80c, 0x557f, 0xc80c, 0x21, 0 + .dw 0x55c0, 0xc80c, 0x55ff, 0xc80c, 0x21, 0 + .dw 0x5640, 0xc80c, 0x567f, 0xc80c, 0x21, 0 + .dw 0x56c0, 0xc80c, 0x56ff, 0xc80c, 0x21, 0 + .dw 0x5740, 0xc80c, 0x577f, 0xc80c, 0x21, 0 + .dw 0x57c0, 0xc80c, 0x57ff, 0xc80c, 0x21, 0 + .dw 0x5840, 0xc80c, 0x587f, 0xc80c, 0x21, 0 + .dw 0x58c0, 0xc80c, 0x58ff, 0xc80c, 0x21, 0 + .dw 0x5940, 0xc80c, 0x597f, 0xc80c, 0x21, 0 + .dw 0x59c0, 0xc80c, 0x5fff, 0xc80c, 0x21, 0 + .dw 0x6040, 0xc80c, 0x607f, 0xc80c, 0x21, 0 + .dw 0x60c0, 0xc80c, 0x60ff, 0xc80c, 0x21, 0 + .dw 0x6140, 0xc80c, 0x617f, 0xc80c, 0x21, 0 + .dw 0x61c0, 0xc80c, 0x61ff, 0xc80c, 0x21, 0 + .dw 0x6240, 0xc80c, 0x627f, 0xc80c, 0x21, 0 + .dw 0x62c0, 0xc80c, 0x62ff, 0xc80c, 0x21, 0 + .dw 0x6340, 0xc80c, 0x637f, 0xc80c, 0x21, 0 + .dw 0x63c0, 0xc80c, 0x63ff, 0xc80c, 0x21, 0 + .dw 0x6440, 0xc80c, 0x647f, 0xc80c, 0x21, 0 + .dw 0x64c0, 0xc80c, 0x64ff, 0xc80c, 0x21, 0 + .dw 0x6540, 0xc80c, 0x657f, 0xc80c, 0x21, 0 + .dw 0x65c0, 0xc80c, 0x65ff, 0xc80c, 0x21, 0 + .dw 0x6640, 0xc80c, 0x667f, 0xc80c, 0x21, 0 + .dw 0x66c0, 0xc80c, 0x66ff, 0xc80c, 0x21, 0 + .dw 0x6740, 0xc80c, 0x677f, 0xc80c, 0x21, 0 + .dw 0x67c0, 0xc80c, 0x67ff, 0xc80c, 0x21, 0 + .dw 0x6840, 0xc80c, 0x687f, 0xc80c, 0x21, 0 + .dw 0x68c0, 0xc80c, 0x68ff, 0xc80c, 0x21, 0 + .dw 0x6940, 0xc80c, 0x697f, 0xc80c, 0x21, 0 + .dw 0x69c0, 0xc80c, 0x69ff, 0xc80c, 0x21, 0 + .dw 0x6a40, 0xc80c, 0x6a7f, 0xc80c, 0x21, 0 + .dw 0x6ac0, 0xc80c, 0x6aff, 0xc80c, 0x21, 0 + .dw 0x6b40, 0xc80c, 0x6b7f, 0xc80c, 0x21, 0 + .dw 0x6bc0, 0xc80c, 0x6bff, 0xc80c, 0x21, 0 + .dw 0x6c40, 0xc80c, 0x6c7f, 0xc80c, 0x21, 0 + .dw 0x6cc0, 0xc80c, 0x6cff, 0xc80c, 0x21, 0 + .dw 0x6d40, 0xc80c, 0x6d7f, 0xc80c, 0x21, 0 + .dw 0x6dc0, 0xc80c, 0x6dff, 0xc80c, 0x21, 0 + .dw 0x6e40, 0xc80c, 0x6e7f, 0xc80c, 0x21, 0 + .dw 0x6ec0, 0xc80c, 0x6eff, 0xc80c, 0x21, 0 + .dw 0x6f40, 0xc80c, 0x6f7f, 0xc80c, 0x21, 0 + .dw 0x6fc0, 0xc80c, 0x6fff, 0xc80c, 0x21, 0 + .dw 0x7040, 0xc80c, 0x707f, 0xc80c, 0x21, 0 + .dw 0x70c0, 0xc80c, 0x70ff, 0xc80c, 0x21, 0 + .dw 0x7140, 0xc80c, 0x717f, 0xc80c, 0x21, 0 + .dw 0x71c0, 0xc80c, 0x71ff, 0xc80c, 0x21, 0 + .dw 0x7240, 0xc80c, 0x727f, 0xc80c, 0x21, 0 + .dw 0x72c0, 0xc80c, 0x72ff, 0xc80c, 0x21, 0 + .dw 0x7340, 0xc80c, 0x737f, 0xc80c, 0x21, 0 + .dw 0x73c0, 0xc80c, 0x73ff, 0xc80c, 0x21, 0 + .dw 0x7440, 0xc80c, 0x747f, 0xc80c, 0x21, 0 + .dw 0x74c0, 0xc80c, 0x74ff, 0xc80c, 0x21, 0 + .dw 0x7540, 0xc80c, 0x757f, 0xc80c, 0x21, 0 + .dw 0x75c0, 0xc80c, 0x75ff, 0xc80c, 0x21, 0 + .dw 0x7640, 0xc80c, 0x767f, 0xc80c, 0x21, 0 + .dw 0x76c0, 0xc80c, 0x76ff, 0xc80c, 0x21, 0 + .dw 0x7740, 0xc80c, 0x777f, 0xc80c, 0x21, 0 + .dw 0x77c0, 0xc80c, 0x77ff, 0xc80c, 0x21, 0 + .dw 0x7840, 0xc80c, 0x787f, 0xc80c, 0x21, 0 + .dw 0x78c0, 0xc80c, 0x78ff, 0xc80c, 0x21, 0 + .dw 0x7940, 0xc80c, 0x797f, 0xc80c, 0x21, 0 + .dw 0x79c0, 0xc80c, 0x7fff, 0xc80c, 0x21, 0 + .dw 0x8040, 0xc80c, 0x807f, 0xc80c, 0x21, 0 + .dw 0x80c0, 0xc80c, 0x80ff, 0xc80c, 0x21, 0 + .dw 0x8140, 0xc80c, 0x817f, 0xc80c, 0x21, 0 + .dw 0x81c0, 0xc80c, 0x81ff, 0xc80c, 0x21, 0 + .dw 0x8240, 0xc80c, 0x827f, 0xc80c, 0x21, 0 + .dw 0x82c0, 0xc80c, 0x82ff, 0xc80c, 0x21, 0 + .dw 0x8340, 0xc80c, 0x837f, 0xc80c, 0x21, 0 + .dw 0x83c0, 0xc80c, 0x83ff, 0xc80c, 0x21, 0 + .dw 0x8440, 0xc80c, 0x847f, 0xc80c, 0x21, 0 + .dw 0x84c0, 0xc80c, 0x84ff, 0xc80c, 0x21, 0 + .dw 0x8540, 0xc80c, 0x857f, 0xc80c, 0x21, 0 + .dw 0x85c0, 0xc80c, 0x85ff, 0xc80c, 0x21, 0 + .dw 0x8640, 0xc80c, 0x867f, 0xc80c, 0x21, 0 + .dw 0x86c0, 0xc80c, 0x86ff, 0xc80c, 0x21, 0 + .dw 0x8740, 0xc80c, 0x877f, 0xc80c, 0x21, 0 + .dw 0x87c0, 0xc80c, 0x87ff, 0xc80c, 0x21, 0 + .dw 0x8840, 0xc80c, 0x887f, 0xc80c, 0x21, 0 + .dw 0x88c0, 0xc80c, 0x88ff, 0xc80c, 0x21, 0 + .dw 0x8940, 0xc80c, 0x897f, 0xc80c, 0x21, 0 + .dw 0x89c0, 0xc80c, 0x89ff, 0xc80c, 0x21, 0 + .dw 0x8a40, 0xc80c, 0x8a7f, 0xc80c, 0x21, 0 + .dw 0x8ac0, 0xc80c, 0x8aff, 0xc80c, 0x21, 0 + .dw 0x8b40, 0xc80c, 0x8b7f, 0xc80c, 0x21, 0 + .dw 0x8bc0, 0xc80c, 0x8bff, 0xc80c, 0x21, 0 + .dw 0x8c40, 0xc80c, 0x8c7f, 0xc80c, 0x21, 0 + .dw 0x8cc0, 0xc80c, 0x8cff, 0xc80c, 0x21, 0 + .dw 0x8d40, 0xc80c, 0x8d7f, 0xc80c, 0x21, 0 + .dw 0x8dc0, 0xc80c, 0x8dff, 0xc80c, 0x21, 0 + .dw 0x8e40, 0xc80c, 0x8e7f, 0xc80c, 0x21, 0 + .dw 0x8ec0, 0xc80c, 0x8eff, 0xc80c, 0x21, 0 + .dw 0x8f40, 0xc80c, 0x8f7f, 0xc80c, 0x21, 0 + .dw 0x8fc0, 0xc80c, 0x8fff, 0xc80c, 0x21, 0 + .dw 0x9040, 0xc80c, 0x907f, 0xc80c, 0x21, 0 + .dw 0x90c0, 0xc80c, 0x90ff, 0xc80c, 0x21, 0 + .dw 0x9140, 0xc80c, 0x917f, 0xc80c, 0x21, 0 + .dw 0x91c0, 0xc80c, 0x91ff, 0xc80c, 0x21, 0 + .dw 0x9240, 0xc80c, 0x927f, 0xc80c, 0x21, 0 + .dw 0x92c0, 0xc80c, 0x92ff, 0xc80c, 0x21, 0 + .dw 0x9340, 0xc80c, 0x937f, 0xc80c, 0x21, 0 + .dw 0x93c0, 0xc80c, 0x93ff, 0xc80c, 0x21, 0 + .dw 0x9440, 0xc80c, 0x947f, 0xc80c, 0x21, 0 + .dw 0x94c0, 0xc80c, 0x94ff, 0xc80c, 0x21, 0 + .dw 0x9540, 0xc80c, 0x957f, 0xc80c, 0x21, 0 + .dw 0x95c0, 0xc80c, 0x95ff, 0xc80c, 0x21, 0 + .dw 0x9640, 0xc80c, 0x967f, 0xc80c, 0x21, 0 + .dw 0x96c0, 0xc80c, 0x96ff, 0xc80c, 0x21, 0 + .dw 0x9740, 0xc80c, 0x977f, 0xc80c, 0x21, 0 + .dw 0x97c0, 0xc80c, 0x97ff, 0xc80c, 0x21, 0 + .dw 0x9840, 0xc80c, 0x987f, 0xc80c, 0x21, 0 + .dw 0x98c0, 0xc80c, 0x98ff, 0xc80c, 0x21, 0 + .dw 0x9940, 0xc80c, 0x997f, 0xc80c, 0x21, 0 + .dw 0x99c0, 0xc80c, 0x9fff, 0xc80c, 0x21, 0 + .dw 0xa040, 0xc80c, 0xa07f, 0xc80c, 0x21, 0 + .dw 0xa0c0, 0xc80c, 0xa0ff, 0xc80c, 0x21, 0 + .dw 0xa140, 0xc80c, 0xa17f, 0xc80c, 0x21, 0 + .dw 0xa1c0, 0xc80c, 0xa1ff, 0xc80c, 0x21, 0 + .dw 0xa240, 0xc80c, 0xa27f, 0xc80c, 0x21, 0 + .dw 0xa2c0, 0xc80c, 0xa2ff, 0xc80c, 0x21, 0 + .dw 0xa340, 0xc80c, 0xa37f, 0xc80c, 0x21, 0 + .dw 0xa3c0, 0xc80c, 0xa3ff, 0xc80c, 0x21, 0 + .dw 0xa440, 0xc80c, 0xa47f, 0xc80c, 0x21, 0 + .dw 0xa4c0, 0xc80c, 0xa4ff, 0xc80c, 0x21, 0 + .dw 0xa540, 0xc80c, 0xa57f, 0xc80c, 0x21, 0 + .dw 0xa5c0, 0xc80c, 0xa5ff, 0xc80c, 0x21, 0 + .dw 0xa640, 0xc80c, 0xa67f, 0xc80c, 0x21, 0 + .dw 0xa6c0, 0xc80c, 0xa6ff, 0xc80c, 0x21, 0 + .dw 0xa740, 0xc80c, 0xa77f, 0xc80c, 0x21, 0 + .dw 0xa7c0, 0xc80c, 0xa7ff, 0xc80c, 0x21, 0 + .dw 0xa840, 0xc80c, 0xa87f, 0xc80c, 0x21, 0 + .dw 0xa8c0, 0xc80c, 0xa8ff, 0xc80c, 0x21, 0 + .dw 0xa940, 0xc80c, 0xa97f, 0xc80c, 0x21, 0 + .dw 0xa9c0, 0xc80c, 0xa9ff, 0xc80c, 0x21, 0 + .dw 0xaa40, 0xc80c, 0xaa7f, 0xc80c, 0x21, 0 + .dw 0xaac0, 0xc80c, 0xaaff, 0xc80c, 0x21, 0 + .dw 0xab40, 0xc80c, 0xab7f, 0xc80c, 0x21, 0 + .dw 0xabc0, 0xc80c, 0xabff, 0xc80c, 0x21, 0 + .dw 0xac40, 0xc80c, 0xac7f, 0xc80c, 0x21, 0 + .dw 0xacc0, 0xc80c, 0xacff, 0xc80c, 0x21, 0 + .dw 0xad40, 0xc80c, 0xad7f, 0xc80c, 0x21, 0 + .dw 0xadc0, 0xc80c, 0xadff, 0xc80c, 0x21, 0 + .dw 0xae40, 0xc80c, 0xae7f, 0xc80c, 0x21, 0 + .dw 0xaec0, 0xc80c, 0xaeff, 0xc80c, 0x21, 0 + .dw 0xaf40, 0xc80c, 0xaf7f, 0xc80c, 0x21, 0 + .dw 0xafc0, 0xc80c, 0xafff, 0xc80c, 0x21, 0 + .dw 0xb040, 0xc80c, 0xb07f, 0xc80c, 0x21, 0 + .dw 0xb0c0, 0xc80c, 0xb0ff, 0xc80c, 0x21, 0 + .dw 0xb140, 0xc80c, 0xb17f, 0xc80c, 0x21, 0 + .dw 0xb1c0, 0xc80c, 0xb1ff, 0xc80c, 0x21, 0 + .dw 0xb240, 0xc80c, 0xb27f, 0xc80c, 0x21, 0 + .dw 0xb2c0, 0xc80c, 0xb2ff, 0xc80c, 0x21, 0 + .dw 0xb340, 0xc80c, 0xb37f, 0xc80c, 0x21, 0 + .dw 0xb3c0, 0xc80c, 0xb3ff, 0xc80c, 0x21, 0 + .dw 0xb440, 0xc80c, 0xb47f, 0xc80c, 0x21, 0 + .dw 0xb4c0, 0xc80c, 0xb4ff, 0xc80c, 0x21, 0 + .dw 0xb540, 0xc80c, 0xb57f, 0xc80c, 0x21, 0 + .dw 0xb5c0, 0xc80c, 0xb5ff, 0xc80c, 0x21, 0 + .dw 0xb640, 0xc80c, 0xb67f, 0xc80c, 0x21, 0 + .dw 0xb6c0, 0xc80c, 0xb6ff, 0xc80c, 0x21, 0 + .dw 0xb740, 0xc80c, 0xb77f, 0xc80c, 0x21, 0 + .dw 0xb7c0, 0xc80c, 0xb7ff, 0xc80c, 0x21, 0 + .dw 0xb840, 0xc80c, 0xb87f, 0xc80c, 0x21, 0 + .dw 0xb8c0, 0xc80c, 0xb8ff, 0xc80c, 0x21, 0 + .dw 0xb940, 0xc80c, 0xb97f, 0xc80c, 0x21, 0 + .dw 0xb9c0, 0xc80c, 0xbfff, 0xc80c, 0x21, 0 + .dw 0xc040, 0xc80c, 0xc07f, 0xc80c, 0x21, 0 + .dw 0xc0c0, 0xc80c, 0xc0ff, 0xc80c, 0x21, 0 + .dw 0xc140, 0xc80c, 0xc17f, 0xc80c, 0x21, 0 + .dw 0xc1c0, 0xc80c, 0xc1ff, 0xc80c, 0x21, 0 + .dw 0xc240, 0xc80c, 0xc27f, 0xc80c, 0x21, 0 + .dw 0xc2c0, 0xc80c, 0xc2ff, 0xc80c, 0x21, 0 + .dw 0xc340, 0xc80c, 0xc37f, 0xc80c, 0x21, 0 + .dw 0xc3c0, 0xc80c, 0xc3ff, 0xc80c, 0x21, 0 + .dw 0xc440, 0xc80c, 0xc47f, 0xc80c, 0x21, 0 + .dw 0xc4c0, 0xc80c, 0xc4ff, 0xc80c, 0x21, 0 + .dw 0xc540, 0xc80c, 0xc57f, 0xc80c, 0x21, 0 + .dw 0xc5c0, 0xc80c, 0xc5ff, 0xc80c, 0x21, 0 + .dw 0xc640, 0xc80c, 0xc67f, 0xc80c, 0x21, 0 + .dw 0xc6c0, 0xc80c, 0xc6ff, 0xc80c, 0x21, 0 + .dw 0xc740, 0xc80c, 0xc77f, 0xc80c, 0x21, 0 + .dw 0xc7c0, 0xc80c, 0xc7ff, 0xc80c, 0x21, 0 + .dw 0xc840, 0xc80c, 0xc87f, 0xc80c, 0x21, 0 + .dw 0xc8c0, 0xc80c, 0xc8ff, 0xc80c, 0x21, 0 + .dw 0xc940, 0xc80c, 0xc97f, 0xc80c, 0x21, 0 + .dw 0xc9c0, 0xc80c, 0xc9ff, 0xc80c, 0x21, 0 + .dw 0xca40, 0xc80c, 0xca7f, 0xc80c, 0x21, 0 + .dw 0xcac0, 0xc80c, 0xcaff, 0xc80c, 0x21, 0 + .dw 0xcb40, 0xc80c, 0xcb7f, 0xc80c, 0x21, 0 + .dw 0xcbc0, 0xc80c, 0xcbff, 0xc80c, 0x21, 0 + .dw 0xcc40, 0xc80c, 0xcc7f, 0xc80c, 0x21, 0 + .dw 0xccc0, 0xc80c, 0xccff, 0xc80c, 0x21, 0 + .dw 0xcd40, 0xc80c, 0xcd7f, 0xc80c, 0x21, 0 + .dw 0xcdc0, 0xc80c, 0xcdff, 0xc80c, 0x21, 0 + .dw 0xce40, 0xc80c, 0xce7f, 0xc80c, 0x21, 0 + .dw 0xcec0, 0xc80c, 0xceff, 0xc80c, 0x21, 0 + .dw 0xcf40, 0xc80c, 0xcf7f, 0xc80c, 0x21, 0 + .dw 0xcfc0, 0xc80c, 0xcfff, 0xc80c, 0x21, 0 + .dw 0xd040, 0xc80c, 0xd07f, 0xc80c, 0x21, 0 + .dw 0xd0c0, 0xc80c, 0xd0ff, 0xc80c, 0x21, 0 + .dw 0xd140, 0xc80c, 0xd17f, 0xc80c, 0x21, 0 + .dw 0xd1c0, 0xc80c, 0xd1ff, 0xc80c, 0x21, 0 + .dw 0xd240, 0xc80c, 0xd27f, 0xc80c, 0x21, 0 + .dw 0xd2c0, 0xc80c, 0xd2ff, 0xc80c, 0x21, 0 + .dw 0xd340, 0xc80c, 0xd37f, 0xc80c, 0x21, 0 + .dw 0xd3c0, 0xc80c, 0xd3ff, 0xc80c, 0x21, 0 + .dw 0xd440, 0xc80c, 0xd47f, 0xc80c, 0x21, 0 + .dw 0xd4c0, 0xc80c, 0xd4ff, 0xc80c, 0x21, 0 + .dw 0xd540, 0xc80c, 0xd57f, 0xc80c, 0x21, 0 + .dw 0xd5c0, 0xc80c, 0xd5ff, 0xc80c, 0x21, 0 + .dw 0xd640, 0xc80c, 0xd67f, 0xc80c, 0x21, 0 + .dw 0xd6c0, 0xc80c, 0xd6ff, 0xc80c, 0x21, 0 + .dw 0xd740, 0xc80c, 0xd77f, 0xc80c, 0x21, 0 + .dw 0xd7c0, 0xc80c, 0xd7ff, 0xc80c, 0x21, 0 + .dw 0xd840, 0xc80c, 0xd87f, 0xc80c, 0x21, 0 + .dw 0xd8c0, 0xc80c, 0xd8ff, 0xc80c, 0x21, 0 + .dw 0xd940, 0xc80c, 0xd97f, 0xc80c, 0x21, 0 + .dw 0xd9c0, 0xc80c, 0xdfff, 0xc80c, 0x21, 0 + .dw 0xe040, 0xc80c, 0xe07f, 0xc80c, 0x21, 0 + .dw 0xe0c0, 0xc80c, 0xe0ff, 0xc80c, 0x21, 0 + .dw 0xe140, 0xc80c, 0xe17f, 0xc80c, 0x21, 0 + .dw 0xe1c0, 0xc80c, 0xe1ff, 0xc80c, 0x21, 0 + .dw 0xe240, 0xc80c, 0xe27f, 0xc80c, 0x21, 0 + .dw 0xe2c0, 0xc80c, 0xe2ff, 0xc80c, 0x21, 0 + .dw 0xe340, 0xc80c, 0xe37f, 0xc80c, 0x21, 0 + .dw 0xe3c0, 0xc80c, 0xe3ff, 0xc80c, 0x21, 0 + .dw 0xe440, 0xc80c, 0xe47f, 0xc80c, 0x21, 0 + .dw 0xe4c0, 0xc80c, 0xe4ff, 0xc80c, 0x21, 0 + .dw 0xe540, 0xc80c, 0xe57f, 0xc80c, 0x21, 0 + .dw 0xe5c0, 0xc80c, 0xe5ff, 0xc80c, 0x21, 0 + .dw 0xe640, 0xc80c, 0xe67f, 0xc80c, 0x21, 0 + .dw 0xe6c0, 0xc80c, 0xe6ff, 0xc80c, 0x21, 0 + .dw 0xe740, 0xc80c, 0xe77f, 0xc80c, 0x21, 0 + .dw 0xe7c0, 0xc80c, 0xe7ff, 0xc80c, 0x21, 0 + .dw 0xe840, 0xc80c, 0xe87f, 0xc80c, 0x21, 0 + .dw 0xe8c0, 0xc80c, 0xe8ff, 0xc80c, 0x21, 0 + .dw 0xe940, 0xc80c, 0xe97f, 0xc80c, 0x21, 0 + .dw 0xe9c0, 0xc80c, 0xe9ff, 0xc80c, 0x21, 0 + .dw 0xea40, 0xc80c, 0xea7f, 0xc80c, 0x21, 0 + .dw 0xeac0, 0xc80c, 0xeaff, 0xc80c, 0x21, 0 + .dw 0xeb40, 0xc80c, 0xeb7f, 0xc80c, 0x21, 0 + .dw 0xebc0, 0xc80c, 0xebff, 0xc80c, 0x21, 0 + .dw 0xec40, 0xc80c, 0xec7f, 0xc80c, 0x21, 0 + .dw 0xecc0, 0xc80c, 0xecff, 0xc80c, 0x21, 0 + .dw 0xed40, 0xc80c, 0xed7f, 0xc80c, 0x21, 0 + .dw 0xedc0, 0xc80c, 0xedff, 0xc80c, 0x21, 0 + .dw 0xee40, 0xc80c, 0xee7f, 0xc80c, 0x21, 0 + .dw 0xeec0, 0xc80c, 0xeeff, 0xc80c, 0x21, 0 + .dw 0xef40, 0xc80c, 0xef7f, 0xc80c, 0x21, 0 + .dw 0xefc0, 0xc80c, 0xefff, 0xc80c, 0x21, 0 + .dw 0xf040, 0xc80c, 0xf07f, 0xc80c, 0x21, 0 + .dw 0xf0c0, 0xc80c, 0xf0ff, 0xc80c, 0x21, 0 + .dw 0xf140, 0xc80c, 0xf17f, 0xc80c, 0x21, 0 + .dw 0xf1c0, 0xc80c, 0xf1ff, 0xc80c, 0x21, 0 + .dw 0xf240, 0xc80c, 0xf27f, 0xc80c, 0x21, 0 + .dw 0xf2c0, 0xc80c, 0xf2ff, 0xc80c, 0x21, 0 + .dw 0xf340, 0xc80c, 0xf37f, 0xc80c, 0x21, 0 + .dw 0xf3c0, 0xc80c, 0xf3ff, 0xc80c, 0x21, 0 + .dw 0xf440, 0xc80c, 0xf47f, 0xc80c, 0x21, 0 + .dw 0xf4c0, 0xc80c, 0xf4ff, 0xc80c, 0x21, 0 + .dw 0xf540, 0xc80c, 0xf57f, 0xc80c, 0x21, 0 + .dw 0xf5c0, 0xc80c, 0xf5ff, 0xc80c, 0x21, 0 + .dw 0xf640, 0xc80c, 0xf67f, 0xc80c, 0x21, 0 + .dw 0xf6c0, 0xc80c, 0xf6ff, 0xc80c, 0x21, 0 + .dw 0xf740, 0xc80c, 0xf77f, 0xc80c, 0x21, 0 + .dw 0xf7c0, 0xc80c, 0xf7ff, 0xc80c, 0x21, 0 + .dw 0xf840, 0xc80c, 0xf87f, 0xc80c, 0x21, 0 + .dw 0xf8c0, 0xc80c, 0xf8ff, 0xc80c, 0x21, 0 + .dw 0xf940, 0xc80c, 0xf97f, 0xc80c, 0x21, 0 + .dw 0xf9c0, 0xc80c, 0xffff, 0xc80c, 0x21, 0 + .dw 0x0040, 0xc80d, 0x007f, 0xc80d, 0x21, 0 + .dw 0x00c0, 0xc80d, 0x00ff, 0xc80d, 0x21, 0 + .dw 0x0140, 0xc80d, 0x017f, 0xc80d, 0x21, 0 + .dw 0x01c0, 0xc80d, 0x01ff, 0xc80d, 0x21, 0 + .dw 0x0240, 0xc80d, 0x027f, 0xc80d, 0x21, 0 + .dw 0x02c0, 0xc80d, 0x02ff, 0xc80d, 0x21, 0 + .dw 0x0340, 0xc80d, 0x037f, 0xc80d, 0x21, 0 + .dw 0x03c0, 0xc80d, 0x03ff, 0xc80d, 0x21, 0 + .dw 0x0440, 0xc80d, 0x047f, 0xc80d, 0x21, 0 + .dw 0x04c0, 0xc80d, 0x04ff, 0xc80d, 0x21, 0 + .dw 0x0540, 0xc80d, 0x057f, 0xc80d, 0x21, 0 + .dw 0x05c0, 0xc80d, 0x05ff, 0xc80d, 0x21, 0 + .dw 0x0640, 0xc80d, 0x067f, 0xc80d, 0x21, 0 + .dw 0x06c0, 0xc80d, 0x06ff, 0xc80d, 0x21, 0 + .dw 0x0740, 0xc80d, 0x077f, 0xc80d, 0x21, 0 + .dw 0x07c0, 0xc80d, 0x07ff, 0xc80d, 0x21, 0 + .dw 0x0840, 0xc80d, 0x087f, 0xc80d, 0x21, 0 + .dw 0x08c0, 0xc80d, 0x08ff, 0xc80d, 0x21, 0 + .dw 0x0940, 0xc80d, 0x097f, 0xc80d, 0x21, 0 + .dw 0x09c0, 0xc80d, 0x09ff, 0xc80d, 0x21, 0 + .dw 0x0a40, 0xc80d, 0x0a7f, 0xc80d, 0x21, 0 + .dw 0x0ac0, 0xc80d, 0x0aff, 0xc80d, 0x21, 0 + .dw 0x0b40, 0xc80d, 0x0b7f, 0xc80d, 0x21, 0 + .dw 0x0bc0, 0xc80d, 0x0bff, 0xc80d, 0x21, 0 + .dw 0x0c40, 0xc80d, 0x0c7f, 0xc80d, 0x21, 0 + .dw 0x0cc0, 0xc80d, 0x0cff, 0xc80d, 0x21, 0 + .dw 0x0d40, 0xc80d, 0x0d7f, 0xc80d, 0x21, 0 + .dw 0x0dc0, 0xc80d, 0x0dff, 0xc80d, 0x21, 0 + .dw 0x0e40, 0xc80d, 0x0e7f, 0xc80d, 0x21, 0 + .dw 0x0ec0, 0xc80d, 0x0eff, 0xc80d, 0x21, 0 + .dw 0x0f40, 0xc80d, 0x0f7f, 0xc80d, 0x21, 0 + .dw 0x0fc0, 0xc80d, 0x0fff, 0xc80d, 0x21, 0 + .dw 0x1040, 0xc80d, 0x107f, 0xc80d, 0x21, 0 + .dw 0x10c0, 0xc80d, 0x10ff, 0xc80d, 0x21, 0 + .dw 0x1140, 0xc80d, 0x117f, 0xc80d, 0x21, 0 + .dw 0x11c0, 0xc80d, 0x11ff, 0xc80d, 0x21, 0 + .dw 0x1240, 0xc80d, 0x127f, 0xc80d, 0x21, 0 + .dw 0x12c0, 0xc80d, 0x12ff, 0xc80d, 0x21, 0 + .dw 0x1340, 0xc80d, 0x137f, 0xc80d, 0x21, 0 + .dw 0x13c0, 0xc80d, 0x13ff, 0xc80d, 0x21, 0 + .dw 0x1440, 0xc80d, 0x147f, 0xc80d, 0x21, 0 + .dw 0x14c0, 0xc80d, 0x14ff, 0xc80d, 0x21, 0 + .dw 0x1540, 0xc80d, 0x157f, 0xc80d, 0x21, 0 + .dw 0x15c0, 0xc80d, 0x15ff, 0xc80d, 0x21, 0 + .dw 0x1640, 0xc80d, 0x167f, 0xc80d, 0x21, 0 + .dw 0x16c0, 0xc80d, 0x16ff, 0xc80d, 0x21, 0 + .dw 0x1740, 0xc80d, 0x177f, 0xc80d, 0x21, 0 + .dw 0x17c0, 0xc80d, 0x17ff, 0xc80d, 0x21, 0 + .dw 0x1840, 0xc80d, 0x187f, 0xc80d, 0x21, 0 + .dw 0x18c0, 0xc80d, 0x18ff, 0xc80d, 0x21, 0 + .dw 0x1940, 0xc80d, 0x197f, 0xc80d, 0x21, 0 + .dw 0x19c0, 0xc80d, 0x1fff, 0xc80d, 0x21, 0 + .dw 0x2040, 0xc80d, 0x207f, 0xc80d, 0x21, 0 + .dw 0x20c0, 0xc80d, 0x20ff, 0xc80d, 0x21, 0 + .dw 0x2140, 0xc80d, 0x217f, 0xc80d, 0x21, 0 + .dw 0x21c0, 0xc80d, 0x21ff, 0xc80d, 0x21, 0 + .dw 0x2240, 0xc80d, 0x227f, 0xc80d, 0x21, 0 + .dw 0x22c0, 0xc80d, 0x22ff, 0xc80d, 0x21, 0 + .dw 0x2340, 0xc80d, 0x237f, 0xc80d, 0x21, 0 + .dw 0x23c0, 0xc80d, 0x23ff, 0xc80d, 0x21, 0 + .dw 0x2440, 0xc80d, 0x247f, 0xc80d, 0x21, 0 + .dw 0x24c0, 0xc80d, 0x24ff, 0xc80d, 0x21, 0 + .dw 0x2540, 0xc80d, 0x257f, 0xc80d, 0x21, 0 + .dw 0x25c0, 0xc80d, 0x25ff, 0xc80d, 0x21, 0 + .dw 0x2640, 0xc80d, 0x267f, 0xc80d, 0x21, 0 + .dw 0x26c0, 0xc80d, 0x26ff, 0xc80d, 0x21, 0 + .dw 0x2740, 0xc80d, 0x277f, 0xc80d, 0x21, 0 + .dw 0x27c0, 0xc80d, 0x27ff, 0xc80d, 0x21, 0 + .dw 0x2840, 0xc80d, 0x287f, 0xc80d, 0x21, 0 + .dw 0x28c0, 0xc80d, 0x28ff, 0xc80d, 0x21, 0 + .dw 0x2940, 0xc80d, 0x297f, 0xc80d, 0x21, 0 + .dw 0x29c0, 0xc80d, 0x29ff, 0xc80d, 0x21, 0 + .dw 0x2a40, 0xc80d, 0x2a7f, 0xc80d, 0x21, 0 + .dw 0x2ac0, 0xc80d, 0x2aff, 0xc80d, 0x21, 0 + .dw 0x2b40, 0xc80d, 0x2b7f, 0xc80d, 0x21, 0 + .dw 0x2bc0, 0xc80d, 0x2bff, 0xc80d, 0x21, 0 + .dw 0x2c40, 0xc80d, 0x2c7f, 0xc80d, 0x21, 0 + .dw 0x2cc0, 0xc80d, 0x2cff, 0xc80d, 0x21, 0 + .dw 0x2d40, 0xc80d, 0x2d7f, 0xc80d, 0x21, 0 + .dw 0x2dc0, 0xc80d, 0x2dff, 0xc80d, 0x21, 0 + .dw 0x2e40, 0xc80d, 0x2e7f, 0xc80d, 0x21, 0 + .dw 0x2ec0, 0xc80d, 0x2eff, 0xc80d, 0x21, 0 + .dw 0x2f40, 0xc80d, 0x2f7f, 0xc80d, 0x21, 0 + .dw 0x2fc0, 0xc80d, 0x2fff, 0xc80d, 0x21, 0 + .dw 0x3040, 0xc80d, 0x307f, 0xc80d, 0x21, 0 + .dw 0x30c0, 0xc80d, 0x30ff, 0xc80d, 0x21, 0 + .dw 0x3140, 0xc80d, 0x317f, 0xc80d, 0x21, 0 + .dw 0x31c0, 0xc80d, 0x31ff, 0xc80d, 0x21, 0 + .dw 0x3240, 0xc80d, 0x327f, 0xc80d, 0x21, 0 + .dw 0x32c0, 0xc80d, 0x32ff, 0xc80d, 0x21, 0 + .dw 0x3340, 0xc80d, 0x337f, 0xc80d, 0x21, 0 + .dw 0x33c0, 0xc80d, 0x33ff, 0xc80d, 0x21, 0 + .dw 0x3440, 0xc80d, 0x347f, 0xc80d, 0x21, 0 + .dw 0x34c0, 0xc80d, 0x34ff, 0xc80d, 0x21, 0 + .dw 0x3540, 0xc80d, 0x357f, 0xc80d, 0x21, 0 + .dw 0x35c0, 0xc80d, 0x35ff, 0xc80d, 0x21, 0 + .dw 0x3640, 0xc80d, 0x367f, 0xc80d, 0x21, 0 + .dw 0x36c0, 0xc80d, 0x36ff, 0xc80d, 0x21, 0 + .dw 0x3740, 0xc80d, 0x377f, 0xc80d, 0x21, 0 + .dw 0x37c0, 0xc80d, 0x37ff, 0xc80d, 0x21, 0 + .dw 0x3840, 0xc80d, 0x387f, 0xc80d, 0x21, 0 + .dw 0x38c0, 0xc80d, 0x38ff, 0xc80d, 0x21, 0 + .dw 0x3940, 0xc80d, 0x397f, 0xc80d, 0x21, 0 + .dw 0x39c0, 0xc80d, 0x3fff, 0xc80d, 0x21, 0 + .dw 0x4040, 0xc80d, 0x407f, 0xc80d, 0x21, 0 + .dw 0x40c0, 0xc80d, 0x40ff, 0xc80d, 0x21, 0 + .dw 0x4140, 0xc80d, 0x417f, 0xc80d, 0x21, 0 + .dw 0x41c0, 0xc80d, 0x41ff, 0xc80d, 0x21, 0 + .dw 0x4240, 0xc80d, 0x427f, 0xc80d, 0x21, 0 + .dw 0x42c0, 0xc80d, 0x42ff, 0xc80d, 0x21, 0 + .dw 0x4340, 0xc80d, 0x437f, 0xc80d, 0x21, 0 + .dw 0x43c0, 0xc80d, 0x43ff, 0xc80d, 0x21, 0 + .dw 0x4440, 0xc80d, 0x447f, 0xc80d, 0x21, 0 + .dw 0x44c0, 0xc80d, 0x44ff, 0xc80d, 0x21, 0 + .dw 0x4540, 0xc80d, 0x457f, 0xc80d, 0x21, 0 + .dw 0x45c0, 0xc80d, 0x45ff, 0xc80d, 0x21, 0 + .dw 0x4640, 0xc80d, 0x467f, 0xc80d, 0x21, 0 + .dw 0x46c0, 0xc80d, 0x46ff, 0xc80d, 0x21, 0 + .dw 0x4740, 0xc80d, 0x477f, 0xc80d, 0x21, 0 + .dw 0x47c0, 0xc80d, 0x47ff, 0xc80d, 0x21, 0 + .dw 0x4840, 0xc80d, 0x487f, 0xc80d, 0x21, 0 + .dw 0x48c0, 0xc80d, 0x48ff, 0xc80d, 0x21, 0 + .dw 0x4940, 0xc80d, 0x497f, 0xc80d, 0x21, 0 + .dw 0x49c0, 0xc80d, 0x49ff, 0xc80d, 0x21, 0 + .dw 0x4a40, 0xc80d, 0x4a7f, 0xc80d, 0x21, 0 + .dw 0x4ac0, 0xc80d, 0x4aff, 0xc80d, 0x21, 0 + .dw 0x4b40, 0xc80d, 0x4b7f, 0xc80d, 0x21, 0 + .dw 0x4bc0, 0xc80d, 0x4bff, 0xc80d, 0x21, 0 + .dw 0x4c40, 0xc80d, 0x4c7f, 0xc80d, 0x21, 0 + .dw 0x4cc0, 0xc80d, 0x4cff, 0xc80d, 0x21, 0 + .dw 0x4d40, 0xc80d, 0x4d7f, 0xc80d, 0x21, 0 + .dw 0x4dc0, 0xc80d, 0x4dff, 0xc80d, 0x21, 0 + .dw 0x4e40, 0xc80d, 0x4e7f, 0xc80d, 0x21, 0 + .dw 0x4ec0, 0xc80d, 0x4eff, 0xc80d, 0x21, 0 + .dw 0x4f40, 0xc80d, 0x4f7f, 0xc80d, 0x21, 0 + .dw 0x4fc0, 0xc80d, 0x4fff, 0xc80d, 0x21, 0 + .dw 0x5040, 0xc80d, 0x507f, 0xc80d, 0x21, 0 + .dw 0x50c0, 0xc80d, 0x50ff, 0xc80d, 0x21, 0 + .dw 0x5140, 0xc80d, 0x517f, 0xc80d, 0x21, 0 + .dw 0x51c0, 0xc80d, 0x51ff, 0xc80d, 0x21, 0 + .dw 0x5240, 0xc80d, 0x527f, 0xc80d, 0x21, 0 + .dw 0x52c0, 0xc80d, 0x52ff, 0xc80d, 0x21, 0 + .dw 0x5340, 0xc80d, 0x537f, 0xc80d, 0x21, 0 + .dw 0x53c0, 0xc80d, 0x53ff, 0xc80d, 0x21, 0 + .dw 0x5440, 0xc80d, 0x547f, 0xc80d, 0x21, 0 + .dw 0x54c0, 0xc80d, 0x54ff, 0xc80d, 0x21, 0 + .dw 0x5540, 0xc80d, 0x557f, 0xc80d, 0x21, 0 + .dw 0x55c0, 0xc80d, 0x55ff, 0xc80d, 0x21, 0 + .dw 0x5640, 0xc80d, 0x567f, 0xc80d, 0x21, 0 + .dw 0x56c0, 0xc80d, 0x56ff, 0xc80d, 0x21, 0 + .dw 0x5740, 0xc80d, 0x577f, 0xc80d, 0x21, 0 + .dw 0x57c0, 0xc80d, 0x57ff, 0xc80d, 0x21, 0 + .dw 0x5840, 0xc80d, 0x587f, 0xc80d, 0x21, 0 + .dw 0x58c0, 0xc80d, 0x58ff, 0xc80d, 0x21, 0 + .dw 0x5940, 0xc80d, 0x597f, 0xc80d, 0x21, 0 + .dw 0x59c0, 0xc80d, 0x5fff, 0xc80d, 0x21, 0 + .dw 0x6040, 0xc80d, 0x607f, 0xc80d, 0x21, 0 + .dw 0x60c0, 0xc80d, 0x60ff, 0xc80d, 0x21, 0 + .dw 0x6140, 0xc80d, 0x617f, 0xc80d, 0x21, 0 + .dw 0x61c0, 0xc80d, 0x61ff, 0xc80d, 0x21, 0 + .dw 0x6240, 0xc80d, 0x627f, 0xc80d, 0x21, 0 + .dw 0x62c0, 0xc80d, 0x62ff, 0xc80d, 0x21, 0 + .dw 0x6340, 0xc80d, 0x637f, 0xc80d, 0x21, 0 + .dw 0x63c0, 0xc80d, 0x63ff, 0xc80d, 0x21, 0 + .dw 0x6440, 0xc80d, 0x647f, 0xc80d, 0x21, 0 + .dw 0x64c0, 0xc80d, 0x64ff, 0xc80d, 0x21, 0 + .dw 0x6540, 0xc80d, 0x657f, 0xc80d, 0x21, 0 + .dw 0x65c0, 0xc80d, 0x65ff, 0xc80d, 0x21, 0 + .dw 0x6640, 0xc80d, 0x667f, 0xc80d, 0x21, 0 + .dw 0x66c0, 0xc80d, 0x66ff, 0xc80d, 0x21, 0 + .dw 0x6740, 0xc80d, 0x677f, 0xc80d, 0x21, 0 + .dw 0x67c0, 0xc80d, 0x67ff, 0xc80d, 0x21, 0 + .dw 0x6840, 0xc80d, 0x687f, 0xc80d, 0x21, 0 + .dw 0x68c0, 0xc80d, 0x68ff, 0xc80d, 0x21, 0 + .dw 0x6940, 0xc80d, 0x697f, 0xc80d, 0x21, 0 + .dw 0x69c0, 0xc80d, 0x69ff, 0xc80d, 0x21, 0 + .dw 0x6a40, 0xc80d, 0x6a7f, 0xc80d, 0x21, 0 + .dw 0x6ac0, 0xc80d, 0x6aff, 0xc80d, 0x21, 0 + .dw 0x6b40, 0xc80d, 0x6b7f, 0xc80d, 0x21, 0 + .dw 0x6bc0, 0xc80d, 0x6bff, 0xc80d, 0x21, 0 + .dw 0x6c40, 0xc80d, 0x6c7f, 0xc80d, 0x21, 0 + .dw 0x6cc0, 0xc80d, 0x6cff, 0xc80d, 0x21, 0 + .dw 0x6d40, 0xc80d, 0x6d7f, 0xc80d, 0x21, 0 + .dw 0x6dc0, 0xc80d, 0x6dff, 0xc80d, 0x21, 0 + .dw 0x6e40, 0xc80d, 0x6e7f, 0xc80d, 0x21, 0 + .dw 0x6ec0, 0xc80d, 0x6eff, 0xc80d, 0x21, 0 + .dw 0x6f40, 0xc80d, 0x6f7f, 0xc80d, 0x21, 0 + .dw 0x6fc0, 0xc80d, 0x6fff, 0xc80d, 0x21, 0 + .dw 0x7040, 0xc80d, 0x707f, 0xc80d, 0x21, 0 + .dw 0x70c0, 0xc80d, 0x70ff, 0xc80d, 0x21, 0 + .dw 0x7140, 0xc80d, 0x717f, 0xc80d, 0x21, 0 + .dw 0x71c0, 0xc80d, 0x71ff, 0xc80d, 0x21, 0 + .dw 0x7240, 0xc80d, 0x727f, 0xc80d, 0x21, 0 + .dw 0x72c0, 0xc80d, 0x72ff, 0xc80d, 0x21, 0 + .dw 0x7340, 0xc80d, 0x737f, 0xc80d, 0x21, 0 + .dw 0x73c0, 0xc80d, 0x73ff, 0xc80d, 0x21, 0 + .dw 0x7440, 0xc80d, 0x747f, 0xc80d, 0x21, 0 + .dw 0x74c0, 0xc80d, 0x74ff, 0xc80d, 0x21, 0 + .dw 0x7540, 0xc80d, 0x757f, 0xc80d, 0x21, 0 + .dw 0x75c0, 0xc80d, 0x75ff, 0xc80d, 0x21, 0 + .dw 0x7640, 0xc80d, 0x767f, 0xc80d, 0x21, 0 + .dw 0x76c0, 0xc80d, 0x76ff, 0xc80d, 0x21, 0 + .dw 0x7740, 0xc80d, 0x777f, 0xc80d, 0x21, 0 + .dw 0x77c0, 0xc80d, 0x77ff, 0xc80d, 0x21, 0 + .dw 0x7840, 0xc80d, 0x787f, 0xc80d, 0x21, 0 + .dw 0x78c0, 0xc80d, 0x78ff, 0xc80d, 0x21, 0 + .dw 0x7940, 0xc80d, 0x797f, 0xc80d, 0x21, 0 + .dw 0x79c0, 0xc80d, 0x7fff, 0xc80d, 0x21, 0 + .dw 0x8040, 0xc80d, 0x807f, 0xc80d, 0x21, 0 + .dw 0x80c0, 0xc80d, 0x80ff, 0xc80d, 0x21, 0 + .dw 0x8140, 0xc80d, 0x817f, 0xc80d, 0x21, 0 + .dw 0x81c0, 0xc80d, 0x81ff, 0xc80d, 0x21, 0 + .dw 0x8240, 0xc80d, 0x827f, 0xc80d, 0x21, 0 + .dw 0x82c0, 0xc80d, 0x82ff, 0xc80d, 0x21, 0 + .dw 0x8340, 0xc80d, 0x837f, 0xc80d, 0x21, 0 + .dw 0x83c0, 0xc80d, 0x83ff, 0xc80d, 0x21, 0 + .dw 0x8440, 0xc80d, 0x847f, 0xc80d, 0x21, 0 + .dw 0x84c0, 0xc80d, 0x84ff, 0xc80d, 0x21, 0 + .dw 0x8540, 0xc80d, 0x857f, 0xc80d, 0x21, 0 + .dw 0x85c0, 0xc80d, 0x85ff, 0xc80d, 0x21, 0 + .dw 0x8640, 0xc80d, 0x867f, 0xc80d, 0x21, 0 + .dw 0x86c0, 0xc80d, 0x86ff, 0xc80d, 0x21, 0 + .dw 0x8740, 0xc80d, 0x877f, 0xc80d, 0x21, 0 + .dw 0x87c0, 0xc80d, 0x87ff, 0xc80d, 0x21, 0 + .dw 0x8840, 0xc80d, 0x887f, 0xc80d, 0x21, 0 + .dw 0x88c0, 0xc80d, 0x88ff, 0xc80d, 0x21, 0 + .dw 0x8940, 0xc80d, 0x897f, 0xc80d, 0x21, 0 + .dw 0x89c0, 0xc80d, 0x89ff, 0xc80d, 0x21, 0 + .dw 0x8a40, 0xc80d, 0x8a7f, 0xc80d, 0x21, 0 + .dw 0x8ac0, 0xc80d, 0x8aff, 0xc80d, 0x21, 0 + .dw 0x8b40, 0xc80d, 0x8b7f, 0xc80d, 0x21, 0 + .dw 0x8bc0, 0xc80d, 0x8bff, 0xc80d, 0x21, 0 + .dw 0x8c40, 0xc80d, 0x8c7f, 0xc80d, 0x21, 0 + .dw 0x8cc0, 0xc80d, 0x8cff, 0xc80d, 0x21, 0 + .dw 0x8d40, 0xc80d, 0x8d7f, 0xc80d, 0x21, 0 + .dw 0x8dc0, 0xc80d, 0x8dff, 0xc80d, 0x21, 0 + .dw 0x8e40, 0xc80d, 0x8e7f, 0xc80d, 0x21, 0 + .dw 0x8ec0, 0xc80d, 0x8eff, 0xc80d, 0x21, 0 + .dw 0x8f40, 0xc80d, 0x8f7f, 0xc80d, 0x21, 0 + .dw 0x8fc0, 0xc80d, 0x8fff, 0xc80d, 0x21, 0 + .dw 0x9040, 0xc80d, 0x907f, 0xc80d, 0x21, 0 + .dw 0x90c0, 0xc80d, 0x90ff, 0xc80d, 0x21, 0 + .dw 0x9140, 0xc80d, 0x917f, 0xc80d, 0x21, 0 + .dw 0x91c0, 0xc80d, 0x91ff, 0xc80d, 0x21, 0 + .dw 0x9240, 0xc80d, 0x927f, 0xc80d, 0x21, 0 + .dw 0x92c0, 0xc80d, 0x92ff, 0xc80d, 0x21, 0 + .dw 0x9340, 0xc80d, 0x937f, 0xc80d, 0x21, 0 + .dw 0x93c0, 0xc80d, 0x93ff, 0xc80d, 0x21, 0 + .dw 0x9440, 0xc80d, 0x947f, 0xc80d, 0x21, 0 + .dw 0x94c0, 0xc80d, 0x94ff, 0xc80d, 0x21, 0 + .dw 0x9540, 0xc80d, 0x957f, 0xc80d, 0x21, 0 + .dw 0x95c0, 0xc80d, 0x95ff, 0xc80d, 0x21, 0 + .dw 0x9640, 0xc80d, 0x967f, 0xc80d, 0x21, 0 + .dw 0x96c0, 0xc80d, 0x96ff, 0xc80d, 0x21, 0 + .dw 0x9740, 0xc80d, 0x977f, 0xc80d, 0x21, 0 + .dw 0x97c0, 0xc80d, 0x97ff, 0xc80d, 0x21, 0 + .dw 0x9840, 0xc80d, 0x987f, 0xc80d, 0x21, 0 + .dw 0x98c0, 0xc80d, 0x98ff, 0xc80d, 0x21, 0 + .dw 0x9940, 0xc80d, 0x997f, 0xc80d, 0x21, 0 + .dw 0x99c0, 0xc80d, 0x9fff, 0xc80d, 0x21, 0 + .dw 0xa040, 0xc80d, 0xa07f, 0xc80d, 0x21, 0 + .dw 0xa0c0, 0xc80d, 0xa0ff, 0xc80d, 0x21, 0 + .dw 0xa140, 0xc80d, 0xa17f, 0xc80d, 0x21, 0 + .dw 0xa1c0, 0xc80d, 0xa1ff, 0xc80d, 0x21, 0 + .dw 0xa240, 0xc80d, 0xa27f, 0xc80d, 0x21, 0 + .dw 0xa2c0, 0xc80d, 0xa2ff, 0xc80d, 0x21, 0 + .dw 0xa340, 0xc80d, 0xa37f, 0xc80d, 0x21, 0 + .dw 0xa3c0, 0xc80d, 0xa3ff, 0xc80d, 0x21, 0 + .dw 0xa440, 0xc80d, 0xa47f, 0xc80d, 0x21, 0 + .dw 0xa4c0, 0xc80d, 0xa4ff, 0xc80d, 0x21, 0 + .dw 0xa540, 0xc80d, 0xa57f, 0xc80d, 0x21, 0 + .dw 0xa5c0, 0xc80d, 0xa5ff, 0xc80d, 0x21, 0 + .dw 0xa640, 0xc80d, 0xa67f, 0xc80d, 0x21, 0 + .dw 0xa6c0, 0xc80d, 0xa6ff, 0xc80d, 0x21, 0 + .dw 0xa740, 0xc80d, 0xa77f, 0xc80d, 0x21, 0 + .dw 0xa7c0, 0xc80d, 0xa7ff, 0xc80d, 0x21, 0 + .dw 0xa840, 0xc80d, 0xa87f, 0xc80d, 0x21, 0 + .dw 0xa8c0, 0xc80d, 0xa8ff, 0xc80d, 0x21, 0 + .dw 0xa940, 0xc80d, 0xa97f, 0xc80d, 0x21, 0 + .dw 0xa9c0, 0xc80d, 0xa9ff, 0xc80d, 0x21, 0 + .dw 0xaa40, 0xc80d, 0xaa7f, 0xc80d, 0x21, 0 + .dw 0xaac0, 0xc80d, 0xaaff, 0xc80d, 0x21, 0 + .dw 0xab40, 0xc80d, 0xab7f, 0xc80d, 0x21, 0 + .dw 0xabc0, 0xc80d, 0xabff, 0xc80d, 0x21, 0 + .dw 0xac40, 0xc80d, 0xac7f, 0xc80d, 0x21, 0 + .dw 0xacc0, 0xc80d, 0xacff, 0xc80d, 0x21, 0 + .dw 0xad40, 0xc80d, 0xad7f, 0xc80d, 0x21, 0 + .dw 0xadc0, 0xc80d, 0xadff, 0xc80d, 0x21, 0 + .dw 0xae40, 0xc80d, 0xae7f, 0xc80d, 0x21, 0 + .dw 0xaec0, 0xc80d, 0xaeff, 0xc80d, 0x21, 0 + .dw 0xaf40, 0xc80d, 0xaf7f, 0xc80d, 0x21, 0 + .dw 0xafc0, 0xc80d, 0xafff, 0xc80d, 0x21, 0 + .dw 0xb040, 0xc80d, 0xb07f, 0xc80d, 0x21, 0 + .dw 0xb0c0, 0xc80d, 0xb0ff, 0xc80d, 0x21, 0 + .dw 0xb140, 0xc80d, 0xb17f, 0xc80d, 0x21, 0 + .dw 0xb1c0, 0xc80d, 0xb1ff, 0xc80d, 0x21, 0 + .dw 0xb240, 0xc80d, 0xb27f, 0xc80d, 0x21, 0 + .dw 0xb2c0, 0xc80d, 0xb2ff, 0xc80d, 0x21, 0 + .dw 0xb340, 0xc80d, 0xb37f, 0xc80d, 0x21, 0 + .dw 0xb3c0, 0xc80d, 0xb3ff, 0xc80d, 0x21, 0 + .dw 0xb440, 0xc80d, 0xb47f, 0xc80d, 0x21, 0 + .dw 0xb4c0, 0xc80d, 0xb4ff, 0xc80d, 0x21, 0 + .dw 0xb540, 0xc80d, 0xb57f, 0xc80d, 0x21, 0 + .dw 0xb5c0, 0xc80d, 0xb5ff, 0xc80d, 0x21, 0 + .dw 0xb640, 0xc80d, 0xb67f, 0xc80d, 0x21, 0 + .dw 0xb6c0, 0xc80d, 0xb6ff, 0xc80d, 0x21, 0 + .dw 0xb740, 0xc80d, 0xb77f, 0xc80d, 0x21, 0 + .dw 0xb7c0, 0xc80d, 0xb7ff, 0xc80d, 0x21, 0 + .dw 0xb840, 0xc80d, 0xb87f, 0xc80d, 0x21, 0 + .dw 0xb8c0, 0xc80d, 0xb8ff, 0xc80d, 0x21, 0 + .dw 0xb940, 0xc80d, 0xb97f, 0xc80d, 0x21, 0 + .dw 0xb9c0, 0xc80d, 0xbfff, 0xc80d, 0x21, 0 + .dw 0xc040, 0xc80d, 0xc07f, 0xc80d, 0x21, 0 + .dw 0xc0c0, 0xc80d, 0xc0ff, 0xc80d, 0x21, 0 + .dw 0xc140, 0xc80d, 0xc17f, 0xc80d, 0x21, 0 + .dw 0xc1c0, 0xc80d, 0xc1ff, 0xc80d, 0x21, 0 + .dw 0xc240, 0xc80d, 0xc27f, 0xc80d, 0x21, 0 + .dw 0xc2c0, 0xc80d, 0xc2ff, 0xc80d, 0x21, 0 + .dw 0xc340, 0xc80d, 0xc37f, 0xc80d, 0x21, 0 + .dw 0xc3c0, 0xc80d, 0xc3ff, 0xc80d, 0x21, 0 + .dw 0xc440, 0xc80d, 0xc47f, 0xc80d, 0x21, 0 + .dw 0xc4c0, 0xc80d, 0xc4ff, 0xc80d, 0x21, 0 + .dw 0xc540, 0xc80d, 0xc57f, 0xc80d, 0x21, 0 + .dw 0xc5c0, 0xc80d, 0xc5ff, 0xc80d, 0x21, 0 + .dw 0xc640, 0xc80d, 0xc67f, 0xc80d, 0x21, 0 + .dw 0xc6c0, 0xc80d, 0xc6ff, 0xc80d, 0x21, 0 + .dw 0xc740, 0xc80d, 0xc77f, 0xc80d, 0x21, 0 + .dw 0xc7c0, 0xc80d, 0xc7ff, 0xc80d, 0x21, 0 + .dw 0xc840, 0xc80d, 0xc87f, 0xc80d, 0x21, 0 + .dw 0xc8c0, 0xc80d, 0xc8ff, 0xc80d, 0x21, 0 + .dw 0xc940, 0xc80d, 0xc97f, 0xc80d, 0x21, 0 + .dw 0xc9c0, 0xc80d, 0xc9ff, 0xc80d, 0x21, 0 + .dw 0xca40, 0xc80d, 0xca7f, 0xc80d, 0x21, 0 + .dw 0xcac0, 0xc80d, 0xcaff, 0xc80d, 0x21, 0 + .dw 0xcb40, 0xc80d, 0xcb7f, 0xc80d, 0x21, 0 + .dw 0xcbc0, 0xc80d, 0xcbff, 0xc80d, 0x21, 0 + .dw 0xcc40, 0xc80d, 0xcc7f, 0xc80d, 0x21, 0 + .dw 0xccc0, 0xc80d, 0xccff, 0xc80d, 0x21, 0 + .dw 0xcd40, 0xc80d, 0xcd7f, 0xc80d, 0x21, 0 + .dw 0xcdc0, 0xc80d, 0xcdff, 0xc80d, 0x21, 0 + .dw 0xce40, 0xc80d, 0xce7f, 0xc80d, 0x21, 0 + .dw 0xcec0, 0xc80d, 0xceff, 0xc80d, 0x21, 0 + .dw 0xcf40, 0xc80d, 0xcf7f, 0xc80d, 0x21, 0 + .dw 0xcfc0, 0xc80d, 0xcfff, 0xc80d, 0x21, 0 + .dw 0xd040, 0xc80d, 0xd07f, 0xc80d, 0x21, 0 + .dw 0xd0c0, 0xc80d, 0xd0ff, 0xc80d, 0x21, 0 + .dw 0xd140, 0xc80d, 0xd17f, 0xc80d, 0x21, 0 + .dw 0xd1c0, 0xc80d, 0xd1ff, 0xc80d, 0x21, 0 + .dw 0xd240, 0xc80d, 0xd27f, 0xc80d, 0x21, 0 + .dw 0xd2c0, 0xc80d, 0xd2ff, 0xc80d, 0x21, 0 + .dw 0xd340, 0xc80d, 0xd37f, 0xc80d, 0x21, 0 + .dw 0xd3c0, 0xc80d, 0xd3ff, 0xc80d, 0x21, 0 + .dw 0xd440, 0xc80d, 0xd47f, 0xc80d, 0x21, 0 + .dw 0xd4c0, 0xc80d, 0xd4ff, 0xc80d, 0x21, 0 + .dw 0xd540, 0xc80d, 0xd57f, 0xc80d, 0x21, 0 + .dw 0xd5c0, 0xc80d, 0xd5ff, 0xc80d, 0x21, 0 + .dw 0xd640, 0xc80d, 0xd67f, 0xc80d, 0x21, 0 + .dw 0xd6c0, 0xc80d, 0xd6ff, 0xc80d, 0x21, 0 + .dw 0xd740, 0xc80d, 0xd77f, 0xc80d, 0x21, 0 + .dw 0xd7c0, 0xc80d, 0xd7ff, 0xc80d, 0x21, 0 + .dw 0xd840, 0xc80d, 0xd87f, 0xc80d, 0x21, 0 + .dw 0xd8c0, 0xc80d, 0xd8ff, 0xc80d, 0x21, 0 + .dw 0xd940, 0xc80d, 0xd97f, 0xc80d, 0x21, 0 + .dw 0xd9c0, 0xc80d, 0xdfff, 0xc80d, 0x21, 0 + .dw 0xe040, 0xc80d, 0xe07f, 0xc80d, 0x21, 0 + .dw 0xe0c0, 0xc80d, 0xe0ff, 0xc80d, 0x21, 0 + .dw 0xe140, 0xc80d, 0xe17f, 0xc80d, 0x21, 0 + .dw 0xe1c0, 0xc80d, 0xe1ff, 0xc80d, 0x21, 0 + .dw 0xe240, 0xc80d, 0xe27f, 0xc80d, 0x21, 0 + .dw 0xe2c0, 0xc80d, 0xe2ff, 0xc80d, 0x21, 0 + .dw 0xe340, 0xc80d, 0xe37f, 0xc80d, 0x21, 0 + .dw 0xe3c0, 0xc80d, 0xe3ff, 0xc80d, 0x21, 0 + .dw 0xe440, 0xc80d, 0xe47f, 0xc80d, 0x21, 0 + .dw 0xe4c0, 0xc80d, 0xe4ff, 0xc80d, 0x21, 0 + .dw 0xe540, 0xc80d, 0xe57f, 0xc80d, 0x21, 0 + .dw 0xe5c0, 0xc80d, 0xe5ff, 0xc80d, 0x21, 0 + .dw 0xe640, 0xc80d, 0xe67f, 0xc80d, 0x21, 0 + .dw 0xe6c0, 0xc80d, 0xe6ff, 0xc80d, 0x21, 0 + .dw 0xe740, 0xc80d, 0xe77f, 0xc80d, 0x21, 0 + .dw 0xe7c0, 0xc80d, 0xe7ff, 0xc80d, 0x21, 0 + .dw 0xe840, 0xc80d, 0xe87f, 0xc80d, 0x21, 0 + .dw 0xe8c0, 0xc80d, 0xe8ff, 0xc80d, 0x21, 0 + .dw 0xe940, 0xc80d, 0xe97f, 0xc80d, 0x21, 0 + .dw 0xe9c0, 0xc80d, 0xe9ff, 0xc80d, 0x21, 0 + .dw 0xea40, 0xc80d, 0xea7f, 0xc80d, 0x21, 0 + .dw 0xeac0, 0xc80d, 0xeaff, 0xc80d, 0x21, 0 + .dw 0xeb40, 0xc80d, 0xeb7f, 0xc80d, 0x21, 0 + .dw 0xebc0, 0xc80d, 0xebff, 0xc80d, 0x21, 0 + .dw 0xec40, 0xc80d, 0xec7f, 0xc80d, 0x21, 0 + .dw 0xecc0, 0xc80d, 0xecff, 0xc80d, 0x21, 0 + .dw 0xed40, 0xc80d, 0xed7f, 0xc80d, 0x21, 0 + .dw 0xedc0, 0xc80d, 0xedff, 0xc80d, 0x21, 0 + .dw 0xee40, 0xc80d, 0xee7f, 0xc80d, 0x21, 0 + .dw 0xeec0, 0xc80d, 0xeeff, 0xc80d, 0x21, 0 + .dw 0xef40, 0xc80d, 0xef7f, 0xc80d, 0x21, 0 + .dw 0xefc0, 0xc80d, 0xefff, 0xc80d, 0x21, 0 + .dw 0xf040, 0xc80d, 0xf07f, 0xc80d, 0x21, 0 + .dw 0xf0c0, 0xc80d, 0xf0ff, 0xc80d, 0x21, 0 + .dw 0xf140, 0xc80d, 0xf17f, 0xc80d, 0x21, 0 + .dw 0xf1c0, 0xc80d, 0xf1ff, 0xc80d, 0x21, 0 + .dw 0xf240, 0xc80d, 0xf27f, 0xc80d, 0x21, 0 + .dw 0xf2c0, 0xc80d, 0xf2ff, 0xc80d, 0x21, 0 + .dw 0xf340, 0xc80d, 0xf37f, 0xc80d, 0x21, 0 + .dw 0xf3c0, 0xc80d, 0xf3ff, 0xc80d, 0x21, 0 + .dw 0xf440, 0xc80d, 0xf47f, 0xc80d, 0x21, 0 + .dw 0xf4c0, 0xc80d, 0xf4ff, 0xc80d, 0x21, 0 + .dw 0xf540, 0xc80d, 0xf57f, 0xc80d, 0x21, 0 + .dw 0xf5c0, 0xc80d, 0xf5ff, 0xc80d, 0x21, 0 + .dw 0xf640, 0xc80d, 0xf67f, 0xc80d, 0x21, 0 + .dw 0xf6c0, 0xc80d, 0xf6ff, 0xc80d, 0x21, 0 + .dw 0xf740, 0xc80d, 0xf77f, 0xc80d, 0x21, 0 + .dw 0xf7c0, 0xc80d, 0xf7ff, 0xc80d, 0x21, 0 + .dw 0xf840, 0xc80d, 0xf87f, 0xc80d, 0x21, 0 + .dw 0xf8c0, 0xc80d, 0xf8ff, 0xc80d, 0x21, 0 + .dw 0xf940, 0xc80d, 0xf97f, 0xc80d, 0x21, 0 + .dw 0xf9c0, 0xc80d, 0xffff, 0xc80d, 0x21, 0 + .dw 0x0040, 0xc80e, 0x007f, 0xc80e, 0x21, 0 + .dw 0x00c0, 0xc80e, 0x00ff, 0xc80e, 0x21, 0 + .dw 0x0140, 0xc80e, 0x017f, 0xc80e, 0x21, 0 + .dw 0x01c0, 0xc80e, 0x01ff, 0xc80e, 0x21, 0 + .dw 0x0240, 0xc80e, 0x027f, 0xc80e, 0x21, 0 + .dw 0x02c0, 0xc80e, 0x02ff, 0xc80e, 0x21, 0 + .dw 0x0340, 0xc80e, 0x037f, 0xc80e, 0x21, 0 + .dw 0x03c0, 0xc80e, 0x03ff, 0xc80e, 0x21, 0 + .dw 0x0440, 0xc80e, 0x047f, 0xc80e, 0x21, 0 + .dw 0x04c0, 0xc80e, 0x04ff, 0xc80e, 0x21, 0 + .dw 0x0540, 0xc80e, 0x057f, 0xc80e, 0x21, 0 + .dw 0x05c0, 0xc80e, 0x05ff, 0xc80e, 0x21, 0 + .dw 0x0640, 0xc80e, 0x067f, 0xc80e, 0x21, 0 + .dw 0x06c0, 0xc80e, 0x06ff, 0xc80e, 0x21, 0 + .dw 0x0740, 0xc80e, 0x077f, 0xc80e, 0x21, 0 + .dw 0x07c0, 0xc80e, 0x07ff, 0xc80e, 0x21, 0 + .dw 0x0840, 0xc80e, 0x087f, 0xc80e, 0x21, 0 + .dw 0x08c0, 0xc80e, 0x08ff, 0xc80e, 0x21, 0 + .dw 0x0940, 0xc80e, 0x097f, 0xc80e, 0x21, 0 + .dw 0x09c0, 0xc80e, 0x09ff, 0xc80e, 0x21, 0 + .dw 0x0a40, 0xc80e, 0x0a7f, 0xc80e, 0x21, 0 + .dw 0x0ac0, 0xc80e, 0x0aff, 0xc80e, 0x21, 0 + .dw 0x0b40, 0xc80e, 0x0b7f, 0xc80e, 0x21, 0 + .dw 0x0bc0, 0xc80e, 0x0bff, 0xc80e, 0x21, 0 + .dw 0x0c40, 0xc80e, 0x0c7f, 0xc80e, 0x21, 0 + .dw 0x0cc0, 0xc80e, 0x0cff, 0xc80e, 0x21, 0 + .dw 0x0d40, 0xc80e, 0x0d7f, 0xc80e, 0x21, 0 + .dw 0x0dc0, 0xc80e, 0x0dff, 0xc80e, 0x21, 0 + .dw 0x0e40, 0xc80e, 0x0e7f, 0xc80e, 0x21, 0 + .dw 0x0ec0, 0xc80e, 0x0eff, 0xc80e, 0x21, 0 + .dw 0x0f40, 0xc80e, 0x0f7f, 0xc80e, 0x21, 0 + .dw 0x0fc0, 0xc80e, 0x0fff, 0xc80e, 0x21, 0 + .dw 0x1040, 0xc80e, 0x107f, 0xc80e, 0x21, 0 + .dw 0x10c0, 0xc80e, 0x10ff, 0xc80e, 0x21, 0 + .dw 0x1140, 0xc80e, 0x117f, 0xc80e, 0x21, 0 + .dw 0x11c0, 0xc80e, 0x11ff, 0xc80e, 0x21, 0 + .dw 0x1240, 0xc80e, 0x127f, 0xc80e, 0x21, 0 + .dw 0x12c0, 0xc80e, 0x12ff, 0xc80e, 0x21, 0 + .dw 0x1340, 0xc80e, 0x137f, 0xc80e, 0x21, 0 + .dw 0x13c0, 0xc80e, 0x13ff, 0xc80e, 0x21, 0 + .dw 0x1440, 0xc80e, 0x147f, 0xc80e, 0x21, 0 + .dw 0x14c0, 0xc80e, 0x14ff, 0xc80e, 0x21, 0 + .dw 0x1540, 0xc80e, 0x157f, 0xc80e, 0x21, 0 + .dw 0x15c0, 0xc80e, 0x15ff, 0xc80e, 0x21, 0 + .dw 0x1640, 0xc80e, 0x167f, 0xc80e, 0x21, 0 + .dw 0x16c0, 0xc80e, 0x16ff, 0xc80e, 0x21, 0 + .dw 0x1740, 0xc80e, 0x177f, 0xc80e, 0x21, 0 + .dw 0x17c0, 0xc80e, 0x17ff, 0xc80e, 0x21, 0 + .dw 0x1840, 0xc80e, 0x187f, 0xc80e, 0x21, 0 + .dw 0x18c0, 0xc80e, 0x18ff, 0xc80e, 0x21, 0 + .dw 0x1940, 0xc80e, 0x197f, 0xc80e, 0x21, 0 + .dw 0x19c0, 0xc80e, 0x1fff, 0xc80e, 0x21, 0 + .dw 0x2040, 0xc80e, 0x207f, 0xc80e, 0x21, 0 + .dw 0x20c0, 0xc80e, 0x20ff, 0xc80e, 0x21, 0 + .dw 0x2140, 0xc80e, 0x217f, 0xc80e, 0x21, 0 + .dw 0x21c0, 0xc80e, 0x21ff, 0xc80e, 0x21, 0 + .dw 0x2240, 0xc80e, 0x227f, 0xc80e, 0x21, 0 + .dw 0x22c0, 0xc80e, 0x22ff, 0xc80e, 0x21, 0 + .dw 0x2340, 0xc80e, 0x237f, 0xc80e, 0x21, 0 + .dw 0x23c0, 0xc80e, 0x23ff, 0xc80e, 0x21, 0 + .dw 0x2440, 0xc80e, 0x247f, 0xc80e, 0x21, 0 + .dw 0x24c0, 0xc80e, 0x24ff, 0xc80e, 0x21, 0 + .dw 0x2540, 0xc80e, 0x257f, 0xc80e, 0x21, 0 + .dw 0x25c0, 0xc80e, 0x25ff, 0xc80e, 0x21, 0 + .dw 0x2640, 0xc80e, 0x267f, 0xc80e, 0x21, 0 + .dw 0x26c0, 0xc80e, 0x26ff, 0xc80e, 0x21, 0 + .dw 0x2740, 0xc80e, 0x277f, 0xc80e, 0x21, 0 + .dw 0x27c0, 0xc80e, 0x27ff, 0xc80e, 0x21, 0 + .dw 0x2840, 0xc80e, 0x287f, 0xc80e, 0x21, 0 + .dw 0x28c0, 0xc80e, 0x28ff, 0xc80e, 0x21, 0 + .dw 0x2940, 0xc80e, 0x297f, 0xc80e, 0x21, 0 + .dw 0x29c0, 0xc80e, 0x29ff, 0xc80e, 0x21, 0 + .dw 0x2a40, 0xc80e, 0x2a7f, 0xc80e, 0x21, 0 + .dw 0x2ac0, 0xc80e, 0x2aff, 0xc80e, 0x21, 0 + .dw 0x2b40, 0xc80e, 0x2b7f, 0xc80e, 0x21, 0 + .dw 0x2bc0, 0xc80e, 0x2bff, 0xc80e, 0x21, 0 + .dw 0x2c40, 0xc80e, 0x2c7f, 0xc80e, 0x21, 0 + .dw 0x2cc0, 0xc80e, 0x2cff, 0xc80e, 0x21, 0 + .dw 0x2d40, 0xc80e, 0x2d7f, 0xc80e, 0x21, 0 + .dw 0x2dc0, 0xc80e, 0x2dff, 0xc80e, 0x21, 0 + .dw 0x2e40, 0xc80e, 0x2e7f, 0xc80e, 0x21, 0 + .dw 0x2ec0, 0xc80e, 0x2eff, 0xc80e, 0x21, 0 + .dw 0x2f40, 0xc80e, 0x2f7f, 0xc80e, 0x21, 0 + .dw 0x2fc0, 0xc80e, 0x2fff, 0xc80e, 0x21, 0 + .dw 0x3040, 0xc80e, 0x307f, 0xc80e, 0x21, 0 + .dw 0x30c0, 0xc80e, 0x30ff, 0xc80e, 0x21, 0 + .dw 0x3140, 0xc80e, 0x317f, 0xc80e, 0x21, 0 + .dw 0x31c0, 0xc80e, 0x31ff, 0xc80e, 0x21, 0 + .dw 0x3240, 0xc80e, 0x327f, 0xc80e, 0x21, 0 + .dw 0x32c0, 0xc80e, 0x32ff, 0xc80e, 0x21, 0 + .dw 0x3340, 0xc80e, 0x337f, 0xc80e, 0x21, 0 + .dw 0x33c0, 0xc80e, 0x33ff, 0xc80e, 0x21, 0 + .dw 0x3440, 0xc80e, 0x347f, 0xc80e, 0x21, 0 + .dw 0x34c0, 0xc80e, 0x34ff, 0xc80e, 0x21, 0 + .dw 0x3540, 0xc80e, 0x357f, 0xc80e, 0x21, 0 + .dw 0x35c0, 0xc80e, 0x35ff, 0xc80e, 0x21, 0 + .dw 0x3640, 0xc80e, 0x367f, 0xc80e, 0x21, 0 + .dw 0x36c0, 0xc80e, 0x36ff, 0xc80e, 0x21, 0 + .dw 0x3740, 0xc80e, 0x377f, 0xc80e, 0x21, 0 + .dw 0x37c0, 0xc80e, 0x37ff, 0xc80e, 0x21, 0 + .dw 0x3840, 0xc80e, 0x387f, 0xc80e, 0x21, 0 + .dw 0x38c0, 0xc80e, 0x38ff, 0xc80e, 0x21, 0 + .dw 0x3940, 0xc80e, 0x397f, 0xc80e, 0x21, 0 + .dw 0x39c0, 0xc80e, 0x3fff, 0xc80e, 0x21, 0 + .dw 0x4040, 0xc80e, 0x407f, 0xc80e, 0x21, 0 + .dw 0x40c0, 0xc80e, 0x40ff, 0xc80e, 0x21, 0 + .dw 0x4140, 0xc80e, 0x417f, 0xc80e, 0x21, 0 + .dw 0x41c0, 0xc80e, 0x41ff, 0xc80e, 0x21, 0 + .dw 0x4240, 0xc80e, 0x427f, 0xc80e, 0x21, 0 + .dw 0x42c0, 0xc80e, 0x42ff, 0xc80e, 0x21, 0 + .dw 0x4340, 0xc80e, 0x437f, 0xc80e, 0x21, 0 + .dw 0x43c0, 0xc80e, 0x43ff, 0xc80e, 0x21, 0 + .dw 0x4440, 0xc80e, 0x447f, 0xc80e, 0x21, 0 + .dw 0x44c0, 0xc80e, 0x44ff, 0xc80e, 0x21, 0 + .dw 0x4540, 0xc80e, 0x457f, 0xc80e, 0x21, 0 + .dw 0x45c0, 0xc80e, 0x45ff, 0xc80e, 0x21, 0 + .dw 0x4640, 0xc80e, 0x467f, 0xc80e, 0x21, 0 + .dw 0x46c0, 0xc80e, 0x46ff, 0xc80e, 0x21, 0 + .dw 0x4740, 0xc80e, 0x477f, 0xc80e, 0x21, 0 + .dw 0x47c0, 0xc80e, 0x47ff, 0xc80e, 0x21, 0 + .dw 0x4840, 0xc80e, 0x487f, 0xc80e, 0x21, 0 + .dw 0x48c0, 0xc80e, 0x48ff, 0xc80e, 0x21, 0 + .dw 0x4940, 0xc80e, 0x497f, 0xc80e, 0x21, 0 + .dw 0x49c0, 0xc80e, 0x49ff, 0xc80e, 0x21, 0 + .dw 0x4a40, 0xc80e, 0x4a7f, 0xc80e, 0x21, 0 + .dw 0x4ac0, 0xc80e, 0x4aff, 0xc80e, 0x21, 0 + .dw 0x4b40, 0xc80e, 0x4b7f, 0xc80e, 0x21, 0 + .dw 0x4bc0, 0xc80e, 0x4bff, 0xc80e, 0x21, 0 + .dw 0x4c40, 0xc80e, 0x4c7f, 0xc80e, 0x21, 0 + .dw 0x4cc0, 0xc80e, 0x4cff, 0xc80e, 0x21, 0 + .dw 0x4d40, 0xc80e, 0x4d7f, 0xc80e, 0x21, 0 + .dw 0x4dc0, 0xc80e, 0x4dff, 0xc80e, 0x21, 0 + .dw 0x4e40, 0xc80e, 0x4e7f, 0xc80e, 0x21, 0 + .dw 0x4ec0, 0xc80e, 0x4eff, 0xc80e, 0x21, 0 + .dw 0x4f40, 0xc80e, 0x4f7f, 0xc80e, 0x21, 0 + .dw 0x4fc0, 0xc80e, 0x4fff, 0xc80e, 0x21, 0 + .dw 0x5040, 0xc80e, 0x507f, 0xc80e, 0x21, 0 + .dw 0x50c0, 0xc80e, 0x50ff, 0xc80e, 0x21, 0 + .dw 0x5140, 0xc80e, 0x517f, 0xc80e, 0x21, 0 + .dw 0x51c0, 0xc80e, 0x51ff, 0xc80e, 0x21, 0 + .dw 0x5240, 0xc80e, 0x527f, 0xc80e, 0x21, 0 + .dw 0x52c0, 0xc80e, 0x52ff, 0xc80e, 0x21, 0 + .dw 0x5340, 0xc80e, 0x537f, 0xc80e, 0x21, 0 + .dw 0x53c0, 0xc80e, 0x53ff, 0xc80e, 0x21, 0 + .dw 0x5440, 0xc80e, 0x547f, 0xc80e, 0x21, 0 + .dw 0x54c0, 0xc80e, 0x54ff, 0xc80e, 0x21, 0 + .dw 0x5540, 0xc80e, 0x557f, 0xc80e, 0x21, 0 + .dw 0x55c0, 0xc80e, 0x55ff, 0xc80e, 0x21, 0 + .dw 0x5640, 0xc80e, 0x567f, 0xc80e, 0x21, 0 + .dw 0x56c0, 0xc80e, 0x56ff, 0xc80e, 0x21, 0 + .dw 0x5740, 0xc80e, 0x577f, 0xc80e, 0x21, 0 + .dw 0x57c0, 0xc80e, 0x57ff, 0xc80e, 0x21, 0 + .dw 0x5840, 0xc80e, 0x587f, 0xc80e, 0x21, 0 + .dw 0x58c0, 0xc80e, 0x58ff, 0xc80e, 0x21, 0 + .dw 0x5940, 0xc80e, 0x597f, 0xc80e, 0x21, 0 + .dw 0x59c0, 0xc80e, 0x5fff, 0xc80e, 0x21, 0 + .dw 0x6040, 0xc80e, 0x607f, 0xc80e, 0x21, 0 + .dw 0x60c0, 0xc80e, 0x60ff, 0xc80e, 0x21, 0 + .dw 0x6140, 0xc80e, 0x617f, 0xc80e, 0x21, 0 + .dw 0x61c0, 0xc80e, 0x61ff, 0xc80e, 0x21, 0 + .dw 0x6240, 0xc80e, 0x627f, 0xc80e, 0x21, 0 + .dw 0x62c0, 0xc80e, 0x62ff, 0xc80e, 0x21, 0 + .dw 0x6340, 0xc80e, 0x637f, 0xc80e, 0x21, 0 + .dw 0x63c0, 0xc80e, 0x63ff, 0xc80e, 0x21, 0 + .dw 0x6440, 0xc80e, 0x647f, 0xc80e, 0x21, 0 + .dw 0x64c0, 0xc80e, 0x64ff, 0xc80e, 0x21, 0 + .dw 0x6540, 0xc80e, 0x657f, 0xc80e, 0x21, 0 + .dw 0x65c0, 0xc80e, 0x65ff, 0xc80e, 0x21, 0 + .dw 0x6640, 0xc80e, 0x667f, 0xc80e, 0x21, 0 + .dw 0x66c0, 0xc80e, 0x66ff, 0xc80e, 0x21, 0 + .dw 0x6740, 0xc80e, 0x677f, 0xc80e, 0x21, 0 + .dw 0x67c0, 0xc80e, 0x67ff, 0xc80e, 0x21, 0 + .dw 0x6840, 0xc80e, 0x687f, 0xc80e, 0x21, 0 + .dw 0x68c0, 0xc80e, 0x68ff, 0xc80e, 0x21, 0 + .dw 0x6940, 0xc80e, 0x697f, 0xc80e, 0x21, 0 + .dw 0x69c0, 0xc80e, 0x69ff, 0xc80e, 0x21, 0 + .dw 0x6a40, 0xc80e, 0x6a7f, 0xc80e, 0x21, 0 + .dw 0x6ac0, 0xc80e, 0x6aff, 0xc80e, 0x21, 0 + .dw 0x6b40, 0xc80e, 0x6b7f, 0xc80e, 0x21, 0 + .dw 0x6bc0, 0xc80e, 0x6bff, 0xc80e, 0x21, 0 + .dw 0x6c40, 0xc80e, 0x6c7f, 0xc80e, 0x21, 0 + .dw 0x6cc0, 0xc80e, 0x6cff, 0xc80e, 0x21, 0 + .dw 0x6d40, 0xc80e, 0x6d7f, 0xc80e, 0x21, 0 + .dw 0x6dc0, 0xc80e, 0x6dff, 0xc80e, 0x21, 0 + .dw 0x6e40, 0xc80e, 0x6e7f, 0xc80e, 0x21, 0 + .dw 0x6ec0, 0xc80e, 0x6eff, 0xc80e, 0x21, 0 + .dw 0x6f40, 0xc80e, 0x6f7f, 0xc80e, 0x21, 0 + .dw 0x6fc0, 0xc80e, 0x6fff, 0xc80e, 0x21, 0 + .dw 0x7040, 0xc80e, 0x707f, 0xc80e, 0x21, 0 + .dw 0x70c0, 0xc80e, 0x70ff, 0xc80e, 0x21, 0 + .dw 0x7140, 0xc80e, 0x717f, 0xc80e, 0x21, 0 + .dw 0x71c0, 0xc80e, 0x71ff, 0xc80e, 0x21, 0 + .dw 0x7240, 0xc80e, 0x727f, 0xc80e, 0x21, 0 + .dw 0x72c0, 0xc80e, 0x72ff, 0xc80e, 0x21, 0 + .dw 0x7340, 0xc80e, 0x737f, 0xc80e, 0x21, 0 + .dw 0x73c0, 0xc80e, 0x73ff, 0xc80e, 0x21, 0 + .dw 0x7440, 0xc80e, 0x747f, 0xc80e, 0x21, 0 + .dw 0x74c0, 0xc80e, 0x74ff, 0xc80e, 0x21, 0 + .dw 0x7540, 0xc80e, 0x757f, 0xc80e, 0x21, 0 + .dw 0x75c0, 0xc80e, 0x75ff, 0xc80e, 0x21, 0 + .dw 0x7640, 0xc80e, 0x767f, 0xc80e, 0x21, 0 + .dw 0x76c0, 0xc80e, 0x76ff, 0xc80e, 0x21, 0 + .dw 0x7740, 0xc80e, 0x777f, 0xc80e, 0x21, 0 + .dw 0x77c0, 0xc80e, 0x77ff, 0xc80e, 0x21, 0 + .dw 0x7840, 0xc80e, 0x787f, 0xc80e, 0x21, 0 + .dw 0x78c0, 0xc80e, 0x78ff, 0xc80e, 0x21, 0 + .dw 0x7940, 0xc80e, 0x797f, 0xc80e, 0x21, 0 + .dw 0x79c0, 0xc80e, 0x7fff, 0xc80e, 0x21, 0 + .dw 0x8040, 0xc80e, 0x807f, 0xc80e, 0x21, 0 + .dw 0x80c0, 0xc80e, 0x80ff, 0xc80e, 0x21, 0 + .dw 0x8140, 0xc80e, 0x817f, 0xc80e, 0x21, 0 + .dw 0x81c0, 0xc80e, 0x81ff, 0xc80e, 0x21, 0 + .dw 0x8240, 0xc80e, 0x827f, 0xc80e, 0x21, 0 + .dw 0x82c0, 0xc80e, 0x82ff, 0xc80e, 0x21, 0 + .dw 0x8340, 0xc80e, 0x837f, 0xc80e, 0x21, 0 + .dw 0x83c0, 0xc80e, 0x83ff, 0xc80e, 0x21, 0 + .dw 0x8440, 0xc80e, 0x847f, 0xc80e, 0x21, 0 + .dw 0x84c0, 0xc80e, 0x84ff, 0xc80e, 0x21, 0 + .dw 0x8540, 0xc80e, 0x857f, 0xc80e, 0x21, 0 + .dw 0x85c0, 0xc80e, 0x85ff, 0xc80e, 0x21, 0 + .dw 0x8640, 0xc80e, 0x867f, 0xc80e, 0x21, 0 + .dw 0x86c0, 0xc80e, 0x86ff, 0xc80e, 0x21, 0 + .dw 0x8740, 0xc80e, 0x877f, 0xc80e, 0x21, 0 + .dw 0x87c0, 0xc80e, 0x87ff, 0xc80e, 0x21, 0 + .dw 0x8840, 0xc80e, 0x887f, 0xc80e, 0x21, 0 + .dw 0x88c0, 0xc80e, 0x88ff, 0xc80e, 0x21, 0 + .dw 0x8940, 0xc80e, 0x897f, 0xc80e, 0x21, 0 + .dw 0x89c0, 0xc80e, 0x89ff, 0xc80e, 0x21, 0 + .dw 0x8a40, 0xc80e, 0x8a7f, 0xc80e, 0x21, 0 + .dw 0x8ac0, 0xc80e, 0x8aff, 0xc80e, 0x21, 0 + .dw 0x8b40, 0xc80e, 0x8b7f, 0xc80e, 0x21, 0 + .dw 0x8bc0, 0xc80e, 0x8bff, 0xc80e, 0x21, 0 + .dw 0x8c40, 0xc80e, 0x8c7f, 0xc80e, 0x21, 0 + .dw 0x8cc0, 0xc80e, 0x8cff, 0xc80e, 0x21, 0 + .dw 0x8d40, 0xc80e, 0x8d7f, 0xc80e, 0x21, 0 + .dw 0x8dc0, 0xc80e, 0x8dff, 0xc80e, 0x21, 0 + .dw 0x8e40, 0xc80e, 0x8e7f, 0xc80e, 0x21, 0 + .dw 0x8ec0, 0xc80e, 0x8eff, 0xc80e, 0x21, 0 + .dw 0x8f40, 0xc80e, 0x8f7f, 0xc80e, 0x21, 0 + .dw 0x8fc0, 0xc80e, 0x8fff, 0xc80e, 0x21, 0 + .dw 0x9040, 0xc80e, 0x907f, 0xc80e, 0x21, 0 + .dw 0x90c0, 0xc80e, 0x90ff, 0xc80e, 0x21, 0 + .dw 0x9140, 0xc80e, 0x917f, 0xc80e, 0x21, 0 + .dw 0x91c0, 0xc80e, 0x91ff, 0xc80e, 0x21, 0 + .dw 0x9240, 0xc80e, 0x927f, 0xc80e, 0x21, 0 + .dw 0x92c0, 0xc80e, 0x92ff, 0xc80e, 0x21, 0 + .dw 0x9340, 0xc80e, 0x937f, 0xc80e, 0x21, 0 + .dw 0x93c0, 0xc80e, 0x93ff, 0xc80e, 0x21, 0 + .dw 0x9440, 0xc80e, 0x947f, 0xc80e, 0x21, 0 + .dw 0x94c0, 0xc80e, 0x94ff, 0xc80e, 0x21, 0 + .dw 0x9540, 0xc80e, 0x957f, 0xc80e, 0x21, 0 + .dw 0x95c0, 0xc80e, 0x95ff, 0xc80e, 0x21, 0 + .dw 0x9640, 0xc80e, 0x967f, 0xc80e, 0x21, 0 + .dw 0x96c0, 0xc80e, 0x96ff, 0xc80e, 0x21, 0 + .dw 0x9740, 0xc80e, 0x977f, 0xc80e, 0x21, 0 + .dw 0x97c0, 0xc80e, 0x97ff, 0xc80e, 0x21, 0 + .dw 0x9840, 0xc80e, 0x987f, 0xc80e, 0x21, 0 + .dw 0x98c0, 0xc80e, 0x98ff, 0xc80e, 0x21, 0 + .dw 0x9940, 0xc80e, 0x997f, 0xc80e, 0x21, 0 + .dw 0x99c0, 0xc80e, 0x9fff, 0xc80e, 0x21, 0 + .dw 0xa040, 0xc80e, 0xa07f, 0xc80e, 0x21, 0 + .dw 0xa0c0, 0xc80e, 0xa0ff, 0xc80e, 0x21, 0 + .dw 0xa140, 0xc80e, 0xa17f, 0xc80e, 0x21, 0 + .dw 0xa1c0, 0xc80e, 0xa1ff, 0xc80e, 0x21, 0 + .dw 0xa240, 0xc80e, 0xa27f, 0xc80e, 0x21, 0 + .dw 0xa2c0, 0xc80e, 0xa2ff, 0xc80e, 0x21, 0 + .dw 0xa340, 0xc80e, 0xa37f, 0xc80e, 0x21, 0 + .dw 0xa3c0, 0xc80e, 0xa3ff, 0xc80e, 0x21, 0 + .dw 0xa440, 0xc80e, 0xa47f, 0xc80e, 0x21, 0 + .dw 0xa4c0, 0xc80e, 0xa4ff, 0xc80e, 0x21, 0 + .dw 0xa540, 0xc80e, 0xa57f, 0xc80e, 0x21, 0 + .dw 0xa5c0, 0xc80e, 0xa5ff, 0xc80e, 0x21, 0 + .dw 0xa640, 0xc80e, 0xa67f, 0xc80e, 0x21, 0 + .dw 0xa6c0, 0xc80e, 0xa6ff, 0xc80e, 0x21, 0 + .dw 0xa740, 0xc80e, 0xa77f, 0xc80e, 0x21, 0 + .dw 0xa7c0, 0xc80e, 0xa7ff, 0xc80e, 0x21, 0 + .dw 0xa840, 0xc80e, 0xa87f, 0xc80e, 0x21, 0 + .dw 0xa8c0, 0xc80e, 0xa8ff, 0xc80e, 0x21, 0 + .dw 0xa940, 0xc80e, 0xa97f, 0xc80e, 0x21, 0 + .dw 0xa9c0, 0xc80e, 0xa9ff, 0xc80e, 0x21, 0 + .dw 0xaa40, 0xc80e, 0xaa7f, 0xc80e, 0x21, 0 + .dw 0xaac0, 0xc80e, 0xaaff, 0xc80e, 0x21, 0 + .dw 0xab40, 0xc80e, 0xab7f, 0xc80e, 0x21, 0 + .dw 0xabc0, 0xc80e, 0xabff, 0xc80e, 0x21, 0 + .dw 0xac40, 0xc80e, 0xac7f, 0xc80e, 0x21, 0 + .dw 0xacc0, 0xc80e, 0xacff, 0xc80e, 0x21, 0 + .dw 0xad40, 0xc80e, 0xad7f, 0xc80e, 0x21, 0 + .dw 0xadc0, 0xc80e, 0xadff, 0xc80e, 0x21, 0 + .dw 0xae40, 0xc80e, 0xae7f, 0xc80e, 0x21, 0 + .dw 0xaec0, 0xc80e, 0xaeff, 0xc80e, 0x21, 0 + .dw 0xaf40, 0xc80e, 0xaf7f, 0xc80e, 0x21, 0 + .dw 0xafc0, 0xc80e, 0xafff, 0xc80e, 0x21, 0 + .dw 0xb040, 0xc80e, 0xb07f, 0xc80e, 0x21, 0 + .dw 0xb0c0, 0xc80e, 0xb0ff, 0xc80e, 0x21, 0 + .dw 0xb140, 0xc80e, 0xb17f, 0xc80e, 0x21, 0 + .dw 0xb1c0, 0xc80e, 0xb1ff, 0xc80e, 0x21, 0 + .dw 0xb240, 0xc80e, 0xb27f, 0xc80e, 0x21, 0 + .dw 0xb2c0, 0xc80e, 0xb2ff, 0xc80e, 0x21, 0 + .dw 0xb340, 0xc80e, 0xb37f, 0xc80e, 0x21, 0 + .dw 0xb3c0, 0xc80e, 0xb3ff, 0xc80e, 0x21, 0 + .dw 0xb440, 0xc80e, 0xb47f, 0xc80e, 0x21, 0 + .dw 0xb4c0, 0xc80e, 0xb4ff, 0xc80e, 0x21, 0 + .dw 0xb540, 0xc80e, 0xb57f, 0xc80e, 0x21, 0 + .dw 0xb5c0, 0xc80e, 0xb5ff, 0xc80e, 0x21, 0 + .dw 0xb640, 0xc80e, 0xb67f, 0xc80e, 0x21, 0 + .dw 0xb6c0, 0xc80e, 0xb6ff, 0xc80e, 0x21, 0 + .dw 0xb740, 0xc80e, 0xb77f, 0xc80e, 0x21, 0 + .dw 0xb7c0, 0xc80e, 0xb7ff, 0xc80e, 0x21, 0 + .dw 0xb840, 0xc80e, 0xb87f, 0xc80e, 0x21, 0 + .dw 0xb8c0, 0xc80e, 0xb8ff, 0xc80e, 0x21, 0 + .dw 0xb940, 0xc80e, 0xb97f, 0xc80e, 0x21, 0 + .dw 0xb9c0, 0xc80e, 0xbfff, 0xc80e, 0x21, 0 + .dw 0xc040, 0xc80e, 0xc07f, 0xc80e, 0x21, 0 + .dw 0xc0c0, 0xc80e, 0xc0ff, 0xc80e, 0x21, 0 + .dw 0xc140, 0xc80e, 0xc17f, 0xc80e, 0x21, 0 + .dw 0xc1c0, 0xc80e, 0xc1ff, 0xc80e, 0x21, 0 + .dw 0xc240, 0xc80e, 0xc27f, 0xc80e, 0x21, 0 + .dw 0xc2c0, 0xc80e, 0xc2ff, 0xc80e, 0x21, 0 + .dw 0xc340, 0xc80e, 0xc37f, 0xc80e, 0x21, 0 + .dw 0xc3c0, 0xc80e, 0xc3ff, 0xc80e, 0x21, 0 + .dw 0xc440, 0xc80e, 0xc47f, 0xc80e, 0x21, 0 + .dw 0xc4c0, 0xc80e, 0xc4ff, 0xc80e, 0x21, 0 + .dw 0xc540, 0xc80e, 0xc57f, 0xc80e, 0x21, 0 + .dw 0xc5c0, 0xc80e, 0xc5ff, 0xc80e, 0x21, 0 + .dw 0xc640, 0xc80e, 0xc67f, 0xc80e, 0x21, 0 + .dw 0xc6c0, 0xc80e, 0xc6ff, 0xc80e, 0x21, 0 + .dw 0xc740, 0xc80e, 0xc77f, 0xc80e, 0x21, 0 + .dw 0xc7c0, 0xc80e, 0xc7ff, 0xc80e, 0x21, 0 + .dw 0xc840, 0xc80e, 0xc87f, 0xc80e, 0x21, 0 + .dw 0xc8c0, 0xc80e, 0xc8ff, 0xc80e, 0x21, 0 + .dw 0xc940, 0xc80e, 0xc97f, 0xc80e, 0x21, 0 + .dw 0xc9c0, 0xc80e, 0xc9ff, 0xc80e, 0x21, 0 + .dw 0xca40, 0xc80e, 0xca7f, 0xc80e, 0x21, 0 + .dw 0xcac0, 0xc80e, 0xcaff, 0xc80e, 0x21, 0 + .dw 0xcb40, 0xc80e, 0xcb7f, 0xc80e, 0x21, 0 + .dw 0xcbc0, 0xc80e, 0xcbff, 0xc80e, 0x21, 0 + .dw 0xcc40, 0xc80e, 0xcc7f, 0xc80e, 0x21, 0 + .dw 0xccc0, 0xc80e, 0xccff, 0xc80e, 0x21, 0 + .dw 0xcd40, 0xc80e, 0xcd7f, 0xc80e, 0x21, 0 + .dw 0xcdc0, 0xc80e, 0xcdff, 0xc80e, 0x21, 0 + .dw 0xce40, 0xc80e, 0xce7f, 0xc80e, 0x21, 0 + .dw 0xcec0, 0xc80e, 0xceff, 0xc80e, 0x21, 0 + .dw 0xcf40, 0xc80e, 0xcf7f, 0xc80e, 0x21, 0 + .dw 0xcfc0, 0xc80e, 0xcfff, 0xc80e, 0x21, 0 + .dw 0xd040, 0xc80e, 0xd07f, 0xc80e, 0x21, 0 + .dw 0xd0c0, 0xc80e, 0xd0ff, 0xc80e, 0x21, 0 + .dw 0xd140, 0xc80e, 0xd17f, 0xc80e, 0x21, 0 + .dw 0xd1c0, 0xc80e, 0xd1ff, 0xc80e, 0x21, 0 + .dw 0xd240, 0xc80e, 0xd27f, 0xc80e, 0x21, 0 + .dw 0xd2c0, 0xc80e, 0xd2ff, 0xc80e, 0x21, 0 + .dw 0xd340, 0xc80e, 0xd37f, 0xc80e, 0x21, 0 + .dw 0xd3c0, 0xc80e, 0xd3ff, 0xc80e, 0x21, 0 + .dw 0xd440, 0xc80e, 0xd47f, 0xc80e, 0x21, 0 + .dw 0xd4c0, 0xc80e, 0xd4ff, 0xc80e, 0x21, 0 + .dw 0xd540, 0xc80e, 0xd57f, 0xc80e, 0x21, 0 + .dw 0xd5c0, 0xc80e, 0xd5ff, 0xc80e, 0x21, 0 + .dw 0xd640, 0xc80e, 0xd67f, 0xc80e, 0x21, 0 + .dw 0xd6c0, 0xc80e, 0xd6ff, 0xc80e, 0x21, 0 + .dw 0xd740, 0xc80e, 0xd77f, 0xc80e, 0x21, 0 + .dw 0xd7c0, 0xc80e, 0xd7ff, 0xc80e, 0x21, 0 + .dw 0xd840, 0xc80e, 0xd87f, 0xc80e, 0x21, 0 + .dw 0xd8c0, 0xc80e, 0xd8ff, 0xc80e, 0x21, 0 + .dw 0xd940, 0xc80e, 0xd97f, 0xc80e, 0x21, 0 + .dw 0xd9c0, 0xc80e, 0xdfff, 0xc80e, 0x21, 0 + .dw 0xe040, 0xc80e, 0xe07f, 0xc80e, 0x21, 0 + .dw 0xe0c0, 0xc80e, 0xe0ff, 0xc80e, 0x21, 0 + .dw 0xe140, 0xc80e, 0xe17f, 0xc80e, 0x21, 0 + .dw 0xe1c0, 0xc80e, 0xe1ff, 0xc80e, 0x21, 0 + .dw 0xe240, 0xc80e, 0xe27f, 0xc80e, 0x21, 0 + .dw 0xe2c0, 0xc80e, 0xe2ff, 0xc80e, 0x21, 0 + .dw 0xe340, 0xc80e, 0xe37f, 0xc80e, 0x21, 0 + .dw 0xe3c0, 0xc80e, 0xe3ff, 0xc80e, 0x21, 0 + .dw 0xe440, 0xc80e, 0xe47f, 0xc80e, 0x21, 0 + .dw 0xe4c0, 0xc80e, 0xe4ff, 0xc80e, 0x21, 0 + .dw 0xe540, 0xc80e, 0xe57f, 0xc80e, 0x21, 0 + .dw 0xe5c0, 0xc80e, 0xe5ff, 0xc80e, 0x21, 0 + .dw 0xe640, 0xc80e, 0xe67f, 0xc80e, 0x21, 0 + .dw 0xe6c0, 0xc80e, 0xe6ff, 0xc80e, 0x21, 0 + .dw 0xe740, 0xc80e, 0xe77f, 0xc80e, 0x21, 0 + .dw 0xe7c0, 0xc80e, 0xe7ff, 0xc80e, 0x21, 0 + .dw 0xe840, 0xc80e, 0xe87f, 0xc80e, 0x21, 0 + .dw 0xe8c0, 0xc80e, 0xe8ff, 0xc80e, 0x21, 0 + .dw 0xe940, 0xc80e, 0xe97f, 0xc80e, 0x21, 0 + .dw 0xe9c0, 0xc80e, 0xe9ff, 0xc80e, 0x21, 0 + .dw 0xea40, 0xc80e, 0xea7f, 0xc80e, 0x21, 0 + .dw 0xeac0, 0xc80e, 0xeaff, 0xc80e, 0x21, 0 + .dw 0xeb40, 0xc80e, 0xeb7f, 0xc80e, 0x21, 0 + .dw 0xebc0, 0xc80e, 0xebff, 0xc80e, 0x21, 0 + .dw 0xec40, 0xc80e, 0xec7f, 0xc80e, 0x21, 0 + .dw 0xecc0, 0xc80e, 0xecff, 0xc80e, 0x21, 0 + .dw 0xed40, 0xc80e, 0xed7f, 0xc80e, 0x21, 0 + .dw 0xedc0, 0xc80e, 0xedff, 0xc80e, 0x21, 0 + .dw 0xee40, 0xc80e, 0xee7f, 0xc80e, 0x21, 0 + .dw 0xeec0, 0xc80e, 0xeeff, 0xc80e, 0x21, 0 + .dw 0xef40, 0xc80e, 0xef7f, 0xc80e, 0x21, 0 + .dw 0xefc0, 0xc80e, 0xefff, 0xc80e, 0x21, 0 + .dw 0xf040, 0xc80e, 0xf07f, 0xc80e, 0x21, 0 + .dw 0xf0c0, 0xc80e, 0xf0ff, 0xc80e, 0x21, 0 + .dw 0xf140, 0xc80e, 0xf17f, 0xc80e, 0x21, 0 + .dw 0xf1c0, 0xc80e, 0xf1ff, 0xc80e, 0x21, 0 + .dw 0xf240, 0xc80e, 0xf27f, 0xc80e, 0x21, 0 + .dw 0xf2c0, 0xc80e, 0xf2ff, 0xc80e, 0x21, 0 + .dw 0xf340, 0xc80e, 0xf37f, 0xc80e, 0x21, 0 + .dw 0xf3c0, 0xc80e, 0xf3ff, 0xc80e, 0x21, 0 + .dw 0xf440, 0xc80e, 0xf47f, 0xc80e, 0x21, 0 + .dw 0xf4c0, 0xc80e, 0xf4ff, 0xc80e, 0x21, 0 + .dw 0xf540, 0xc80e, 0xf57f, 0xc80e, 0x21, 0 + .dw 0xf5c0, 0xc80e, 0xf5ff, 0xc80e, 0x21, 0 + .dw 0xf640, 0xc80e, 0xf67f, 0xc80e, 0x21, 0 + .dw 0xf6c0, 0xc80e, 0xf6ff, 0xc80e, 0x21, 0 + .dw 0xf740, 0xc80e, 0xf77f, 0xc80e, 0x21, 0 + .dw 0xf7c0, 0xc80e, 0xf7ff, 0xc80e, 0x21, 0 + .dw 0xf840, 0xc80e, 0xf87f, 0xc80e, 0x21, 0 + .dw 0xf8c0, 0xc80e, 0xf8ff, 0xc80e, 0x21, 0 + .dw 0xf940, 0xc80e, 0xf97f, 0xc80e, 0x21, 0 + .dw 0xf9c0, 0xc80e, 0xffff, 0xc80e, 0x21, 0 + .dw 0x0040, 0xc80f, 0x007f, 0xc80f, 0x21, 0 + .dw 0x00c0, 0xc80f, 0x00ff, 0xc80f, 0x21, 0 + .dw 0x0140, 0xc80f, 0x017f, 0xc80f, 0x21, 0 + .dw 0x01c0, 0xc80f, 0x01ff, 0xc80f, 0x21, 0 + .dw 0x0240, 0xc80f, 0x027f, 0xc80f, 0x21, 0 + .dw 0x02c0, 0xc80f, 0x02ff, 0xc80f, 0x21, 0 + .dw 0x0340, 0xc80f, 0x037f, 0xc80f, 0x21, 0 + .dw 0x03c0, 0xc80f, 0x03ff, 0xc80f, 0x21, 0 + .dw 0x0440, 0xc80f, 0x047f, 0xc80f, 0x21, 0 + .dw 0x04c0, 0xc80f, 0x04ff, 0xc80f, 0x21, 0 + .dw 0x0540, 0xc80f, 0x057f, 0xc80f, 0x21, 0 + .dw 0x05c0, 0xc80f, 0x05ff, 0xc80f, 0x21, 0 + .dw 0x0640, 0xc80f, 0x067f, 0xc80f, 0x21, 0 + .dw 0x06c0, 0xc80f, 0x06ff, 0xc80f, 0x21, 0 + .dw 0x0740, 0xc80f, 0x077f, 0xc80f, 0x21, 0 + .dw 0x07c0, 0xc80f, 0x07ff, 0xc80f, 0x21, 0 + .dw 0x0840, 0xc80f, 0x087f, 0xc80f, 0x21, 0 + .dw 0x08c0, 0xc80f, 0x08ff, 0xc80f, 0x21, 0 + .dw 0x0940, 0xc80f, 0x097f, 0xc80f, 0x21, 0 + .dw 0x09c0, 0xc80f, 0x09ff, 0xc80f, 0x21, 0 + .dw 0x0a40, 0xc80f, 0x0a7f, 0xc80f, 0x21, 0 + .dw 0x0ac0, 0xc80f, 0x0aff, 0xc80f, 0x21, 0 + .dw 0x0b40, 0xc80f, 0x0b7f, 0xc80f, 0x21, 0 + .dw 0x0bc0, 0xc80f, 0x0bff, 0xc80f, 0x21, 0 + .dw 0x0c40, 0xc80f, 0x0c7f, 0xc80f, 0x21, 0 + .dw 0x0cc0, 0xc80f, 0x0cff, 0xc80f, 0x21, 0 + .dw 0x0d40, 0xc80f, 0x0d7f, 0xc80f, 0x21, 0 + .dw 0x0dc0, 0xc80f, 0x0dff, 0xc80f, 0x21, 0 + .dw 0x0e40, 0xc80f, 0x0e7f, 0xc80f, 0x21, 0 + .dw 0x0ec0, 0xc80f, 0x0eff, 0xc80f, 0x21, 0 + .dw 0x0f40, 0xc80f, 0x0f7f, 0xc80f, 0x21, 0 + .dw 0x0fc0, 0xc80f, 0x0fff, 0xc80f, 0x21, 0 + .dw 0x1040, 0xc80f, 0x107f, 0xc80f, 0x21, 0 + .dw 0x10c0, 0xc80f, 0x10ff, 0xc80f, 0x21, 0 + .dw 0x1140, 0xc80f, 0x117f, 0xc80f, 0x21, 0 + .dw 0x11c0, 0xc80f, 0x11ff, 0xc80f, 0x21, 0 + .dw 0x1240, 0xc80f, 0x127f, 0xc80f, 0x21, 0 + .dw 0x12c0, 0xc80f, 0x12ff, 0xc80f, 0x21, 0 + .dw 0x1340, 0xc80f, 0x137f, 0xc80f, 0x21, 0 + .dw 0x13c0, 0xc80f, 0x13ff, 0xc80f, 0x21, 0 + .dw 0x1440, 0xc80f, 0x147f, 0xc80f, 0x21, 0 + .dw 0x14c0, 0xc80f, 0x14ff, 0xc80f, 0x21, 0 + .dw 0x1540, 0xc80f, 0x157f, 0xc80f, 0x21, 0 + .dw 0x15c0, 0xc80f, 0x15ff, 0xc80f, 0x21, 0 + .dw 0x1640, 0xc80f, 0x167f, 0xc80f, 0x21, 0 + .dw 0x16c0, 0xc80f, 0x16ff, 0xc80f, 0x21, 0 + .dw 0x1740, 0xc80f, 0x177f, 0xc80f, 0x21, 0 + .dw 0x17c0, 0xc80f, 0x17ff, 0xc80f, 0x21, 0 + .dw 0x1840, 0xc80f, 0x187f, 0xc80f, 0x21, 0 + .dw 0x18c0, 0xc80f, 0x18ff, 0xc80f, 0x21, 0 + .dw 0x1940, 0xc80f, 0x197f, 0xc80f, 0x21, 0 + .dw 0x19c0, 0xc80f, 0x1fff, 0xc80f, 0x21, 0 + .dw 0x2040, 0xc80f, 0x207f, 0xc80f, 0x21, 0 + .dw 0x20c0, 0xc80f, 0x20ff, 0xc80f, 0x21, 0 + .dw 0x2140, 0xc80f, 0x217f, 0xc80f, 0x21, 0 + .dw 0x21c0, 0xc80f, 0x21ff, 0xc80f, 0x21, 0 + .dw 0x2240, 0xc80f, 0x227f, 0xc80f, 0x21, 0 + .dw 0x22c0, 0xc80f, 0x22ff, 0xc80f, 0x21, 0 + .dw 0x2340, 0xc80f, 0x237f, 0xc80f, 0x21, 0 + .dw 0x23c0, 0xc80f, 0x23ff, 0xc80f, 0x21, 0 + .dw 0x2440, 0xc80f, 0x247f, 0xc80f, 0x21, 0 + .dw 0x24c0, 0xc80f, 0x24ff, 0xc80f, 0x21, 0 + .dw 0x2540, 0xc80f, 0x257f, 0xc80f, 0x21, 0 + .dw 0x25c0, 0xc80f, 0x25ff, 0xc80f, 0x21, 0 + .dw 0x2640, 0xc80f, 0x267f, 0xc80f, 0x21, 0 + .dw 0x26c0, 0xc80f, 0x26ff, 0xc80f, 0x21, 0 + .dw 0x2740, 0xc80f, 0x277f, 0xc80f, 0x21, 0 + .dw 0x27c0, 0xc80f, 0x27ff, 0xc80f, 0x21, 0 + .dw 0x2840, 0xc80f, 0x287f, 0xc80f, 0x21, 0 + .dw 0x28c0, 0xc80f, 0x28ff, 0xc80f, 0x21, 0 + .dw 0x2940, 0xc80f, 0x297f, 0xc80f, 0x21, 0 + .dw 0x29c0, 0xc80f, 0x29ff, 0xc80f, 0x21, 0 + .dw 0x2a40, 0xc80f, 0x2a7f, 0xc80f, 0x21, 0 + .dw 0x2ac0, 0xc80f, 0x2aff, 0xc80f, 0x21, 0 + .dw 0x2b40, 0xc80f, 0x2b7f, 0xc80f, 0x21, 0 + .dw 0x2bc0, 0xc80f, 0x2bff, 0xc80f, 0x21, 0 + .dw 0x2c40, 0xc80f, 0x2c7f, 0xc80f, 0x21, 0 + .dw 0x2cc0, 0xc80f, 0x2cff, 0xc80f, 0x21, 0 + .dw 0x2d40, 0xc80f, 0x2d7f, 0xc80f, 0x21, 0 + .dw 0x2dc0, 0xc80f, 0x2dff, 0xc80f, 0x21, 0 + .dw 0x2e40, 0xc80f, 0x2e7f, 0xc80f, 0x21, 0 + .dw 0x2ec0, 0xc80f, 0x2eff, 0xc80f, 0x21, 0 + .dw 0x2f40, 0xc80f, 0x2f7f, 0xc80f, 0x21, 0 + .dw 0x2fc0, 0xc80f, 0x2fff, 0xc80f, 0x21, 0 + .dw 0x3040, 0xc80f, 0x307f, 0xc80f, 0x21, 0 + .dw 0x30c0, 0xc80f, 0x30ff, 0xc80f, 0x21, 0 + .dw 0x3140, 0xc80f, 0x317f, 0xc80f, 0x21, 0 + .dw 0x31c0, 0xc80f, 0x31ff, 0xc80f, 0x21, 0 + .dw 0x3240, 0xc80f, 0x327f, 0xc80f, 0x21, 0 + .dw 0x32c0, 0xc80f, 0x32ff, 0xc80f, 0x21, 0 + .dw 0x3340, 0xc80f, 0x337f, 0xc80f, 0x21, 0 + .dw 0x33c0, 0xc80f, 0x33ff, 0xc80f, 0x21, 0 + .dw 0x3440, 0xc80f, 0x347f, 0xc80f, 0x21, 0 + .dw 0x34c0, 0xc80f, 0x34ff, 0xc80f, 0x21, 0 + .dw 0x3540, 0xc80f, 0x357f, 0xc80f, 0x21, 0 + .dw 0x35c0, 0xc80f, 0x35ff, 0xc80f, 0x21, 0 + .dw 0x3640, 0xc80f, 0x367f, 0xc80f, 0x21, 0 + .dw 0x36c0, 0xc80f, 0x36ff, 0xc80f, 0x21, 0 + .dw 0x3740, 0xc80f, 0x377f, 0xc80f, 0x21, 0 + .dw 0x37c0, 0xc80f, 0x37ff, 0xc80f, 0x21, 0 + .dw 0x3840, 0xc80f, 0x387f, 0xc80f, 0x21, 0 + .dw 0x38c0, 0xc80f, 0x38ff, 0xc80f, 0x21, 0 + .dw 0x3940, 0xc80f, 0x397f, 0xc80f, 0x21, 0 + .dw 0x39c0, 0xc80f, 0xffff, 0xc80f, 0x21, 0 + .dw 0x1a00, 0xc810, 0x1fff, 0xc810, 0x21, 0 + .dw 0x3a00, 0xc810, 0x3fff, 0xc810, 0x21, 0 + .dw 0x5a00, 0xc810, 0x5fff, 0xc810, 0x21, 0 + .dw 0x7a00, 0xc810, 0x7fff, 0xc810, 0x21, 0 + .dw 0x9a00, 0xc810, 0x9fff, 0xc810, 0x21, 0 + .dw 0xba00, 0xc810, 0xbfff, 0xc810, 0x21, 0 + .dw 0xda00, 0xc810, 0xdfff, 0xc810, 0x21, 0 + .dw 0xfa00, 0xc810, 0xffff, 0xc810, 0x21, 0 + .dw 0x1a00, 0xc811, 0x1fff, 0xc811, 0x21, 0 + .dw 0x3a00, 0xc811, 0x3fff, 0xc811, 0x21, 0 + .dw 0x5a00, 0xc811, 0x5fff, 0xc811, 0x21, 0 + .dw 0x7a00, 0xc811, 0x7fff, 0xc811, 0x21, 0 + .dw 0x9a00, 0xc811, 0x9fff, 0xc811, 0x21, 0 + .dw 0xba00, 0xc811, 0xbfff, 0xc811, 0x21, 0 + .dw 0xda00, 0xc811, 0xdfff, 0xc811, 0x21, 0 + .dw 0xfa00, 0xc811, 0xffff, 0xc811, 0x21, 0 + .dw 0x1a00, 0xc812, 0x1fff, 0xc812, 0x21, 0 + .dw 0x3a00, 0xc812, 0x3fff, 0xc812, 0x21, 0 + .dw 0x5a00, 0xc812, 0x5fff, 0xc812, 0x21, 0 + .dw 0x7a00, 0xc812, 0x7fff, 0xc812, 0x21, 0 + .dw 0x9a00, 0xc812, 0x9fff, 0xc812, 0x21, 0 + .dw 0xba00, 0xc812, 0xbfff, 0xc812, 0x21, 0 + .dw 0xda00, 0xc812, 0xdfff, 0xc812, 0x21, 0 + .dw 0xfa00, 0xc812, 0xffff, 0xc813, 0x21, 0 + .dw 0x1a00, 0xc814, 0x1fff, 0xc814, 0x21, 0 + .dw 0x3a00, 0xc814, 0x3fff, 0xc814, 0x21, 0 + .dw 0x5a00, 0xc814, 0x5fff, 0xc814, 0x21, 0 + .dw 0x7a00, 0xc814, 0x7fff, 0xc814, 0x21, 0 + .dw 0x9a00, 0xc814, 0x9fff, 0xc814, 0x21, 0 + .dw 0xba00, 0xc814, 0xbfff, 0xc814, 0x21, 0 + .dw 0xda00, 0xc814, 0xdfff, 0xc814, 0x21, 0 + .dw 0xfa00, 0xc814, 0xffff, 0xc814, 0x21, 0 + .dw 0x1a00, 0xc815, 0x1fff, 0xc815, 0x21, 0 + .dw 0x3a00, 0xc815, 0x3fff, 0xc815, 0x21, 0 + .dw 0x5a00, 0xc815, 0x5fff, 0xc815, 0x21, 0 + .dw 0x7a00, 0xc815, 0x7fff, 0xc815, 0x21, 0 + .dw 0x9a00, 0xc815, 0x9fff, 0xc815, 0x21, 0 + .dw 0xba00, 0xc815, 0xbfff, 0xc815, 0x21, 0 + .dw 0xda00, 0xc815, 0xdfff, 0xc815, 0x21, 0 + .dw 0xfa00, 0xc815, 0xffff, 0xc815, 0x21, 0 + .dw 0x1a00, 0xc816, 0x1fff, 0xc816, 0x21, 0 + .dw 0x3a00, 0xc816, 0x3fff, 0xc816, 0x21, 0 + .dw 0x5a00, 0xc816, 0x5fff, 0xc816, 0x21, 0 + .dw 0x7a00, 0xc816, 0x7fff, 0xc816, 0x21, 0 + .dw 0x9a00, 0xc816, 0x9fff, 0xc816, 0x21, 0 + .dw 0xba00, 0xc816, 0xbfff, 0xc816, 0x21, 0 + .dw 0xda00, 0xc816, 0xdfff, 0xc816, 0x21, 0 + .dw 0xfa00, 0xc816, 0xffff, 0xc816, 0x21, 0 + .dw 0x1a00, 0xc817, 0x1fff, 0xc817, 0x21, 0 + .dw 0x3a00, 0xc817, 0x1fff, 0xc818, 0x21, 0 + .dw 0x2040, 0xc818, 0x207f, 0xc818, 0x21, 0 + .dw 0x20c0, 0xc818, 0x20ff, 0xc818, 0x21, 0 + .dw 0x2140, 0xc818, 0x217f, 0xc818, 0x21, 0 + .dw 0x21c0, 0xc818, 0x21ff, 0xc818, 0x21, 0 + .dw 0x2240, 0xc818, 0x227f, 0xc818, 0x21, 0 + .dw 0x22c0, 0xc818, 0x22ff, 0xc818, 0x21, 0 + .dw 0x2340, 0xc818, 0x237f, 0xc818, 0x21, 0 + .dw 0x23c0, 0xc818, 0x23ff, 0xc818, 0x21, 0 + .dw 0x2440, 0xc818, 0x247f, 0xc818, 0x21, 0 + .dw 0x24c0, 0xc818, 0x24ff, 0xc818, 0x21, 0 + .dw 0x2540, 0xc818, 0x257f, 0xc818, 0x21, 0 + .dw 0x25c0, 0xc818, 0x25ff, 0xc818, 0x21, 0 + .dw 0x2640, 0xc818, 0x267f, 0xc818, 0x21, 0 + .dw 0x26c0, 0xc818, 0x26ff, 0xc818, 0x21, 0 + .dw 0x2740, 0xc818, 0x277f, 0xc818, 0x21, 0 + .dw 0x27c0, 0xc818, 0x27ff, 0xc818, 0x21, 0 + .dw 0x2840, 0xc818, 0x287f, 0xc818, 0x21, 0 + .dw 0x28c0, 0xc818, 0x28ff, 0xc818, 0x21, 0 + .dw 0x2940, 0xc818, 0x297f, 0xc818, 0x21, 0 + .dw 0x29c0, 0xc818, 0x29ff, 0xc818, 0x21, 0 + .dw 0x2a40, 0xc818, 0x2a7f, 0xc818, 0x21, 0 + .dw 0x2ac0, 0xc818, 0x2aff, 0xc818, 0x21, 0 + .dw 0x2b40, 0xc818, 0x2b7f, 0xc818, 0x21, 0 + .dw 0x2bc0, 0xc818, 0x2bff, 0xc818, 0x21, 0 + .dw 0x2c40, 0xc818, 0x2c7f, 0xc818, 0x21, 0 + .dw 0x2cc0, 0xc818, 0x2cff, 0xc818, 0x21, 0 + .dw 0x2d40, 0xc818, 0x2d7f, 0xc818, 0x21, 0 + .dw 0x2dc0, 0xc818, 0x2dff, 0xc818, 0x21, 0 + .dw 0x2e40, 0xc818, 0x2e7f, 0xc818, 0x21, 0 + .dw 0x2ec0, 0xc818, 0x2eff, 0xc818, 0x21, 0 + .dw 0x2f40, 0xc818, 0x2f7f, 0xc818, 0x21, 0 + .dw 0x2fc0, 0xc818, 0x2fff, 0xc818, 0x21, 0 + .dw 0x3040, 0xc818, 0x307f, 0xc818, 0x21, 0 + .dw 0x30c0, 0xc818, 0x30ff, 0xc818, 0x21, 0 + .dw 0x3140, 0xc818, 0x317f, 0xc818, 0x21, 0 + .dw 0x31c0, 0xc818, 0x31ff, 0xc818, 0x21, 0 + .dw 0x3240, 0xc818, 0x327f, 0xc818, 0x21, 0 + .dw 0x32c0, 0xc818, 0x32ff, 0xc818, 0x21, 0 + .dw 0x3340, 0xc818, 0x337f, 0xc818, 0x21, 0 + .dw 0x33c0, 0xc818, 0x33ff, 0xc818, 0x21, 0 + .dw 0x3440, 0xc818, 0x347f, 0xc818, 0x21, 0 + .dw 0x34c0, 0xc818, 0x34ff, 0xc818, 0x21, 0 + .dw 0x3540, 0xc818, 0x357f, 0xc818, 0x21, 0 + .dw 0x35c0, 0xc818, 0x35ff, 0xc818, 0x21, 0 + .dw 0x3640, 0xc818, 0x367f, 0xc818, 0x21, 0 + .dw 0x36c0, 0xc818, 0x36ff, 0xc818, 0x21, 0 + .dw 0x3740, 0xc818, 0x377f, 0xc818, 0x21, 0 + .dw 0x37c0, 0xc818, 0x37ff, 0xc818, 0x21, 0 + .dw 0x3840, 0xc818, 0x387f, 0xc818, 0x21, 0 + .dw 0x38c0, 0xc818, 0x38ff, 0xc818, 0x21, 0 + .dw 0x3940, 0xc818, 0x397f, 0xc818, 0x21, 0 + .dw 0x39c0, 0xc818, 0x5fff, 0xc818, 0x21, 0 + .dw 0x6040, 0xc818, 0x607f, 0xc818, 0x21, 0 + .dw 0x60c0, 0xc818, 0x60ff, 0xc818, 0x21, 0 + .dw 0x6140, 0xc818, 0x617f, 0xc818, 0x21, 0 + .dw 0x61c0, 0xc818, 0x61ff, 0xc818, 0x21, 0 + .dw 0x6240, 0xc818, 0x627f, 0xc818, 0x21, 0 + .dw 0x62c0, 0xc818, 0x62ff, 0xc818, 0x21, 0 + .dw 0x6340, 0xc818, 0x637f, 0xc818, 0x21, 0 + .dw 0x63c0, 0xc818, 0x63ff, 0xc818, 0x21, 0 + .dw 0x6440, 0xc818, 0x647f, 0xc818, 0x21, 0 + .dw 0x64c0, 0xc818, 0x64ff, 0xc818, 0x21, 0 + .dw 0x6540, 0xc818, 0x657f, 0xc818, 0x21, 0 + .dw 0x65c0, 0xc818, 0x65ff, 0xc818, 0x21, 0 + .dw 0x6640, 0xc818, 0x667f, 0xc818, 0x21, 0 + .dw 0x66c0, 0xc818, 0x66ff, 0xc818, 0x21, 0 + .dw 0x6740, 0xc818, 0x677f, 0xc818, 0x21, 0 + .dw 0x67c0, 0xc818, 0x67ff, 0xc818, 0x21, 0 + .dw 0x6840, 0xc818, 0x687f, 0xc818, 0x21, 0 + .dw 0x68c0, 0xc818, 0x68ff, 0xc818, 0x21, 0 + .dw 0x6940, 0xc818, 0x697f, 0xc818, 0x21, 0 + .dw 0x69c0, 0xc818, 0x69ff, 0xc818, 0x21, 0 + .dw 0x6a40, 0xc818, 0x6a7f, 0xc818, 0x21, 0 + .dw 0x6ac0, 0xc818, 0x6aff, 0xc818, 0x21, 0 + .dw 0x6b40, 0xc818, 0x6b7f, 0xc818, 0x21, 0 + .dw 0x6bc0, 0xc818, 0x6bff, 0xc818, 0x21, 0 + .dw 0x6c40, 0xc818, 0x6c7f, 0xc818, 0x21, 0 + .dw 0x6cc0, 0xc818, 0x6cff, 0xc818, 0x21, 0 + .dw 0x6d40, 0xc818, 0x6d7f, 0xc818, 0x21, 0 + .dw 0x6dc0, 0xc818, 0x6dff, 0xc818, 0x21, 0 + .dw 0x6e40, 0xc818, 0x6e7f, 0xc818, 0x21, 0 + .dw 0x6ec0, 0xc818, 0x6eff, 0xc818, 0x21, 0 + .dw 0x6f40, 0xc818, 0x6f7f, 0xc818, 0x21, 0 + .dw 0x6fc0, 0xc818, 0x6fff, 0xc818, 0x21, 0 + .dw 0x7040, 0xc818, 0x707f, 0xc818, 0x21, 0 + .dw 0x70c0, 0xc818, 0x70ff, 0xc818, 0x21, 0 + .dw 0x7140, 0xc818, 0x717f, 0xc818, 0x21, 0 + .dw 0x71c0, 0xc818, 0x71ff, 0xc818, 0x21, 0 + .dw 0x7240, 0xc818, 0x727f, 0xc818, 0x21, 0 + .dw 0x72c0, 0xc818, 0x72ff, 0xc818, 0x21, 0 + .dw 0x7340, 0xc818, 0x737f, 0xc818, 0x21, 0 + .dw 0x73c0, 0xc818, 0x73ff, 0xc818, 0x21, 0 + .dw 0x7440, 0xc818, 0x747f, 0xc818, 0x21, 0 + .dw 0x74c0, 0xc818, 0x74ff, 0xc818, 0x21, 0 + .dw 0x7540, 0xc818, 0x757f, 0xc818, 0x21, 0 + .dw 0x75c0, 0xc818, 0x75ff, 0xc818, 0x21, 0 + .dw 0x7640, 0xc818, 0x767f, 0xc818, 0x21, 0 + .dw 0x76c0, 0xc818, 0x76ff, 0xc818, 0x21, 0 + .dw 0x7740, 0xc818, 0x777f, 0xc818, 0x21, 0 + .dw 0x77c0, 0xc818, 0x77ff, 0xc818, 0x21, 0 + .dw 0x7840, 0xc818, 0x787f, 0xc818, 0x21, 0 + .dw 0x78c0, 0xc818, 0x78ff, 0xc818, 0x21, 0 + .dw 0x7940, 0xc818, 0x797f, 0xc818, 0x21, 0 + .dw 0x79c0, 0xc818, 0x9fff, 0xc818, 0x21, 0 + .dw 0xa040, 0xc818, 0xa07f, 0xc818, 0x21, 0 + .dw 0xa0c0, 0xc818, 0xa0ff, 0xc818, 0x21, 0 + .dw 0xa140, 0xc818, 0xa17f, 0xc818, 0x21, 0 + .dw 0xa1c0, 0xc818, 0xa1ff, 0xc818, 0x21, 0 + .dw 0xa240, 0xc818, 0xa27f, 0xc818, 0x21, 0 + .dw 0xa2c0, 0xc818, 0xa2ff, 0xc818, 0x21, 0 + .dw 0xa340, 0xc818, 0xa37f, 0xc818, 0x21, 0 + .dw 0xa3c0, 0xc818, 0xa3ff, 0xc818, 0x21, 0 + .dw 0xa440, 0xc818, 0xa47f, 0xc818, 0x21, 0 + .dw 0xa4c0, 0xc818, 0xa4ff, 0xc818, 0x21, 0 + .dw 0xa540, 0xc818, 0xa57f, 0xc818, 0x21, 0 + .dw 0xa5c0, 0xc818, 0xa5ff, 0xc818, 0x21, 0 + .dw 0xa640, 0xc818, 0xa67f, 0xc818, 0x21, 0 + .dw 0xa6c0, 0xc818, 0xa6ff, 0xc818, 0x21, 0 + .dw 0xa740, 0xc818, 0xa77f, 0xc818, 0x21, 0 + .dw 0xa7c0, 0xc818, 0xa7ff, 0xc818, 0x21, 0 + .dw 0xa840, 0xc818, 0xa87f, 0xc818, 0x21, 0 + .dw 0xa8c0, 0xc818, 0xa8ff, 0xc818, 0x21, 0 + .dw 0xa940, 0xc818, 0xa97f, 0xc818, 0x21, 0 + .dw 0xa9c0, 0xc818, 0xa9ff, 0xc818, 0x21, 0 + .dw 0xaa40, 0xc818, 0xaa7f, 0xc818, 0x21, 0 + .dw 0xaac0, 0xc818, 0xaaff, 0xc818, 0x21, 0 + .dw 0xab40, 0xc818, 0xab7f, 0xc818, 0x21, 0 + .dw 0xabc0, 0xc818, 0xabff, 0xc818, 0x21, 0 + .dw 0xac40, 0xc818, 0xac7f, 0xc818, 0x21, 0 + .dw 0xacc0, 0xc818, 0xacff, 0xc818, 0x21, 0 + .dw 0xad40, 0xc818, 0xad7f, 0xc818, 0x21, 0 + .dw 0xadc0, 0xc818, 0xadff, 0xc818, 0x21, 0 + .dw 0xae40, 0xc818, 0xae7f, 0xc818, 0x21, 0 + .dw 0xaec0, 0xc818, 0xaeff, 0xc818, 0x21, 0 + .dw 0xaf40, 0xc818, 0xaf7f, 0xc818, 0x21, 0 + .dw 0xafc0, 0xc818, 0xafff, 0xc818, 0x21, 0 + .dw 0xb040, 0xc818, 0xb07f, 0xc818, 0x21, 0 + .dw 0xb0c0, 0xc818, 0xb0ff, 0xc818, 0x21, 0 + .dw 0xb140, 0xc818, 0xb17f, 0xc818, 0x21, 0 + .dw 0xb1c0, 0xc818, 0xb1ff, 0xc818, 0x21, 0 + .dw 0xb240, 0xc818, 0xb27f, 0xc818, 0x21, 0 + .dw 0xb2c0, 0xc818, 0xb2ff, 0xc818, 0x21, 0 + .dw 0xb340, 0xc818, 0xb37f, 0xc818, 0x21, 0 + .dw 0xb3c0, 0xc818, 0xb3ff, 0xc818, 0x21, 0 + .dw 0xb440, 0xc818, 0xb47f, 0xc818, 0x21, 0 + .dw 0xb4c0, 0xc818, 0xb4ff, 0xc818, 0x21, 0 + .dw 0xb540, 0xc818, 0xb57f, 0xc818, 0x21, 0 + .dw 0xb5c0, 0xc818, 0xb5ff, 0xc818, 0x21, 0 + .dw 0xb640, 0xc818, 0xb67f, 0xc818, 0x21, 0 + .dw 0xb6c0, 0xc818, 0xb6ff, 0xc818, 0x21, 0 + .dw 0xb740, 0xc818, 0xb77f, 0xc818, 0x21, 0 + .dw 0xb7c0, 0xc818, 0xb7ff, 0xc818, 0x21, 0 + .dw 0xb840, 0xc818, 0xb87f, 0xc818, 0x21, 0 + .dw 0xb8c0, 0xc818, 0xb8ff, 0xc818, 0x21, 0 + .dw 0xb940, 0xc818, 0xb97f, 0xc818, 0x21, 0 + .dw 0xb9c0, 0xc818, 0xdfff, 0xc818, 0x21, 0 + .dw 0xe040, 0xc818, 0xe07f, 0xc818, 0x21, 0 + .dw 0xe0c0, 0xc818, 0xe0ff, 0xc818, 0x21, 0 + .dw 0xe140, 0xc818, 0xe17f, 0xc818, 0x21, 0 + .dw 0xe1c0, 0xc818, 0xe1ff, 0xc818, 0x21, 0 + .dw 0xe240, 0xc818, 0xe27f, 0xc818, 0x21, 0 + .dw 0xe2c0, 0xc818, 0xe2ff, 0xc818, 0x21, 0 + .dw 0xe340, 0xc818, 0xe37f, 0xc818, 0x21, 0 + .dw 0xe3c0, 0xc818, 0xe3ff, 0xc818, 0x21, 0 + .dw 0xe440, 0xc818, 0xe47f, 0xc818, 0x21, 0 + .dw 0xe4c0, 0xc818, 0xe4ff, 0xc818, 0x21, 0 + .dw 0xe540, 0xc818, 0xe57f, 0xc818, 0x21, 0 + .dw 0xe5c0, 0xc818, 0xe5ff, 0xc818, 0x21, 0 + .dw 0xe640, 0xc818, 0xe67f, 0xc818, 0x21, 0 + .dw 0xe6c0, 0xc818, 0xe6ff, 0xc818, 0x21, 0 + .dw 0xe740, 0xc818, 0xe77f, 0xc818, 0x21, 0 + .dw 0xe7c0, 0xc818, 0xe7ff, 0xc818, 0x21, 0 + .dw 0xe840, 0xc818, 0xe87f, 0xc818, 0x21, 0 + .dw 0xe8c0, 0xc818, 0xe8ff, 0xc818, 0x21, 0 + .dw 0xe940, 0xc818, 0xe97f, 0xc818, 0x21, 0 + .dw 0xe9c0, 0xc818, 0xe9ff, 0xc818, 0x21, 0 + .dw 0xea40, 0xc818, 0xea7f, 0xc818, 0x21, 0 + .dw 0xeac0, 0xc818, 0xeaff, 0xc818, 0x21, 0 + .dw 0xeb40, 0xc818, 0xeb7f, 0xc818, 0x21, 0 + .dw 0xebc0, 0xc818, 0xebff, 0xc818, 0x21, 0 + .dw 0xec40, 0xc818, 0xec7f, 0xc818, 0x21, 0 + .dw 0xecc0, 0xc818, 0xecff, 0xc818, 0x21, 0 + .dw 0xed40, 0xc818, 0xed7f, 0xc818, 0x21, 0 + .dw 0xedc0, 0xc818, 0xedff, 0xc818, 0x21, 0 + .dw 0xee40, 0xc818, 0xee7f, 0xc818, 0x21, 0 + .dw 0xeec0, 0xc818, 0xeeff, 0xc818, 0x21, 0 + .dw 0xef40, 0xc818, 0xef7f, 0xc818, 0x21, 0 + .dw 0xefc0, 0xc818, 0xefff, 0xc818, 0x21, 0 + .dw 0xf040, 0xc818, 0xf07f, 0xc818, 0x21, 0 + .dw 0xf0c0, 0xc818, 0xf0ff, 0xc818, 0x21, 0 + .dw 0xf140, 0xc818, 0xf17f, 0xc818, 0x21, 0 + .dw 0xf1c0, 0xc818, 0xf1ff, 0xc818, 0x21, 0 + .dw 0xf240, 0xc818, 0xf27f, 0xc818, 0x21, 0 + .dw 0xf2c0, 0xc818, 0xf2ff, 0xc818, 0x21, 0 + .dw 0xf340, 0xc818, 0xf37f, 0xc818, 0x21, 0 + .dw 0xf3c0, 0xc818, 0xf3ff, 0xc818, 0x21, 0 + .dw 0xf440, 0xc818, 0xf47f, 0xc818, 0x21, 0 + .dw 0xf4c0, 0xc818, 0xf4ff, 0xc818, 0x21, 0 + .dw 0xf540, 0xc818, 0xf57f, 0xc818, 0x21, 0 + .dw 0xf5c0, 0xc818, 0xf5ff, 0xc818, 0x21, 0 + .dw 0xf640, 0xc818, 0xf67f, 0xc818, 0x21, 0 + .dw 0xf6c0, 0xc818, 0xf6ff, 0xc818, 0x21, 0 + .dw 0xf740, 0xc818, 0xf77f, 0xc818, 0x21, 0 + .dw 0xf7c0, 0xc818, 0xf7ff, 0xc818, 0x21, 0 + .dw 0xf840, 0xc818, 0xf87f, 0xc818, 0x21, 0 + .dw 0xf8c0, 0xc818, 0xf8ff, 0xc818, 0x21, 0 + .dw 0xf940, 0xc818, 0xf97f, 0xc818, 0x21, 0 + .dw 0xf9c0, 0xc818, 0x1fff, 0xc819, 0x21, 0 + .dw 0x2040, 0xc819, 0x207f, 0xc819, 0x21, 0 + .dw 0x20c0, 0xc819, 0x20ff, 0xc819, 0x21, 0 + .dw 0x2140, 0xc819, 0x217f, 0xc819, 0x21, 0 + .dw 0x21c0, 0xc819, 0x21ff, 0xc819, 0x21, 0 + .dw 0x2240, 0xc819, 0x227f, 0xc819, 0x21, 0 + .dw 0x22c0, 0xc819, 0x22ff, 0xc819, 0x21, 0 + .dw 0x2340, 0xc819, 0x237f, 0xc819, 0x21, 0 + .dw 0x23c0, 0xc819, 0x23ff, 0xc819, 0x21, 0 + .dw 0x2440, 0xc819, 0x247f, 0xc819, 0x21, 0 + .dw 0x24c0, 0xc819, 0x24ff, 0xc819, 0x21, 0 + .dw 0x2540, 0xc819, 0x257f, 0xc819, 0x21, 0 + .dw 0x25c0, 0xc819, 0x25ff, 0xc819, 0x21, 0 + .dw 0x2640, 0xc819, 0x267f, 0xc819, 0x21, 0 + .dw 0x26c0, 0xc819, 0x26ff, 0xc819, 0x21, 0 + .dw 0x2740, 0xc819, 0x277f, 0xc819, 0x21, 0 + .dw 0x27c0, 0xc819, 0x27ff, 0xc819, 0x21, 0 + .dw 0x2840, 0xc819, 0x287f, 0xc819, 0x21, 0 + .dw 0x28c0, 0xc819, 0x28ff, 0xc819, 0x21, 0 + .dw 0x2940, 0xc819, 0x297f, 0xc819, 0x21, 0 + .dw 0x29c0, 0xc819, 0x29ff, 0xc819, 0x21, 0 + .dw 0x2a40, 0xc819, 0x2a7f, 0xc819, 0x21, 0 + .dw 0x2ac0, 0xc819, 0x2aff, 0xc819, 0x21, 0 + .dw 0x2b40, 0xc819, 0x2b7f, 0xc819, 0x21, 0 + .dw 0x2bc0, 0xc819, 0x2bff, 0xc819, 0x21, 0 + .dw 0x2c40, 0xc819, 0x2c7f, 0xc819, 0x21, 0 + .dw 0x2cc0, 0xc819, 0x2cff, 0xc819, 0x21, 0 + .dw 0x2d40, 0xc819, 0x2d7f, 0xc819, 0x21, 0 + .dw 0x2dc0, 0xc819, 0x2dff, 0xc819, 0x21, 0 + .dw 0x2e40, 0xc819, 0x2e7f, 0xc819, 0x21, 0 + .dw 0x2ec0, 0xc819, 0x2eff, 0xc819, 0x21, 0 + .dw 0x2f40, 0xc819, 0x2f7f, 0xc819, 0x21, 0 + .dw 0x2fc0, 0xc819, 0x2fff, 0xc819, 0x21, 0 + .dw 0x3040, 0xc819, 0x307f, 0xc819, 0x21, 0 + .dw 0x30c0, 0xc819, 0x30ff, 0xc819, 0x21, 0 + .dw 0x3140, 0xc819, 0x317f, 0xc819, 0x21, 0 + .dw 0x31c0, 0xc819, 0x31ff, 0xc819, 0x21, 0 + .dw 0x3240, 0xc819, 0x327f, 0xc819, 0x21, 0 + .dw 0x32c0, 0xc819, 0x32ff, 0xc819, 0x21, 0 + .dw 0x3340, 0xc819, 0x337f, 0xc819, 0x21, 0 + .dw 0x33c0, 0xc819, 0x33ff, 0xc819, 0x21, 0 + .dw 0x3440, 0xc819, 0x347f, 0xc819, 0x21, 0 + .dw 0x34c0, 0xc819, 0x34ff, 0xc819, 0x21, 0 + .dw 0x3540, 0xc819, 0x357f, 0xc819, 0x21, 0 + .dw 0x35c0, 0xc819, 0x35ff, 0xc819, 0x21, 0 + .dw 0x3640, 0xc819, 0x367f, 0xc819, 0x21, 0 + .dw 0x36c0, 0xc819, 0x36ff, 0xc819, 0x21, 0 + .dw 0x3740, 0xc819, 0x377f, 0xc819, 0x21, 0 + .dw 0x37c0, 0xc819, 0x37ff, 0xc819, 0x21, 0 + .dw 0x3840, 0xc819, 0x387f, 0xc819, 0x21, 0 + .dw 0x38c0, 0xc819, 0x38ff, 0xc819, 0x21, 0 + .dw 0x3940, 0xc819, 0x397f, 0xc819, 0x21, 0 + .dw 0x39c0, 0xc819, 0x5fff, 0xc819, 0x21, 0 + .dw 0x6040, 0xc819, 0x607f, 0xc819, 0x21, 0 + .dw 0x60c0, 0xc819, 0x60ff, 0xc819, 0x21, 0 + .dw 0x6140, 0xc819, 0x617f, 0xc819, 0x21, 0 + .dw 0x61c0, 0xc819, 0x61ff, 0xc819, 0x21, 0 + .dw 0x6240, 0xc819, 0x627f, 0xc819, 0x21, 0 + .dw 0x62c0, 0xc819, 0x62ff, 0xc819, 0x21, 0 + .dw 0x6340, 0xc819, 0x637f, 0xc819, 0x21, 0 + .dw 0x63c0, 0xc819, 0x63ff, 0xc819, 0x21, 0 + .dw 0x6440, 0xc819, 0x647f, 0xc819, 0x21, 0 + .dw 0x64c0, 0xc819, 0x64ff, 0xc819, 0x21, 0 + .dw 0x6540, 0xc819, 0x657f, 0xc819, 0x21, 0 + .dw 0x65c0, 0xc819, 0x65ff, 0xc819, 0x21, 0 + .dw 0x6640, 0xc819, 0x667f, 0xc819, 0x21, 0 + .dw 0x66c0, 0xc819, 0x66ff, 0xc819, 0x21, 0 + .dw 0x6740, 0xc819, 0x677f, 0xc819, 0x21, 0 + .dw 0x67c0, 0xc819, 0x67ff, 0xc819, 0x21, 0 + .dw 0x6840, 0xc819, 0x687f, 0xc819, 0x21, 0 + .dw 0x68c0, 0xc819, 0x68ff, 0xc819, 0x21, 0 + .dw 0x6940, 0xc819, 0x697f, 0xc819, 0x21, 0 + .dw 0x69c0, 0xc819, 0x69ff, 0xc819, 0x21, 0 + .dw 0x6a40, 0xc819, 0x6a7f, 0xc819, 0x21, 0 + .dw 0x6ac0, 0xc819, 0x6aff, 0xc819, 0x21, 0 + .dw 0x6b40, 0xc819, 0x6b7f, 0xc819, 0x21, 0 + .dw 0x6bc0, 0xc819, 0x6bff, 0xc819, 0x21, 0 + .dw 0x6c40, 0xc819, 0x6c7f, 0xc819, 0x21, 0 + .dw 0x6cc0, 0xc819, 0x6cff, 0xc819, 0x21, 0 + .dw 0x6d40, 0xc819, 0x6d7f, 0xc819, 0x21, 0 + .dw 0x6dc0, 0xc819, 0x6dff, 0xc819, 0x21, 0 + .dw 0x6e40, 0xc819, 0x6e7f, 0xc819, 0x21, 0 + .dw 0x6ec0, 0xc819, 0x6eff, 0xc819, 0x21, 0 + .dw 0x6f40, 0xc819, 0x6f7f, 0xc819, 0x21, 0 + .dw 0x6fc0, 0xc819, 0x6fff, 0xc819, 0x21, 0 + .dw 0x7040, 0xc819, 0x707f, 0xc819, 0x21, 0 + .dw 0x70c0, 0xc819, 0x70ff, 0xc819, 0x21, 0 + .dw 0x7140, 0xc819, 0x717f, 0xc819, 0x21, 0 + .dw 0x71c0, 0xc819, 0x71ff, 0xc819, 0x21, 0 + .dw 0x7240, 0xc819, 0x727f, 0xc819, 0x21, 0 + .dw 0x72c0, 0xc819, 0x72ff, 0xc819, 0x21, 0 + .dw 0x7340, 0xc819, 0x737f, 0xc819, 0x21, 0 + .dw 0x73c0, 0xc819, 0x73ff, 0xc819, 0x21, 0 + .dw 0x7440, 0xc819, 0x747f, 0xc819, 0x21, 0 + .dw 0x74c0, 0xc819, 0x74ff, 0xc819, 0x21, 0 + .dw 0x7540, 0xc819, 0x757f, 0xc819, 0x21, 0 + .dw 0x75c0, 0xc819, 0x75ff, 0xc819, 0x21, 0 + .dw 0x7640, 0xc819, 0x767f, 0xc819, 0x21, 0 + .dw 0x76c0, 0xc819, 0x76ff, 0xc819, 0x21, 0 + .dw 0x7740, 0xc819, 0x777f, 0xc819, 0x21, 0 + .dw 0x77c0, 0xc819, 0x77ff, 0xc819, 0x21, 0 + .dw 0x7840, 0xc819, 0x787f, 0xc819, 0x21, 0 + .dw 0x78c0, 0xc819, 0x78ff, 0xc819, 0x21, 0 + .dw 0x7940, 0xc819, 0x797f, 0xc819, 0x21, 0 + .dw 0x79c0, 0xc819, 0x9fff, 0xc819, 0x21, 0 + .dw 0xa040, 0xc819, 0xa07f, 0xc819, 0x21, 0 + .dw 0xa0c0, 0xc819, 0xa0ff, 0xc819, 0x21, 0 + .dw 0xa140, 0xc819, 0xa17f, 0xc819, 0x21, 0 + .dw 0xa1c0, 0xc819, 0xa1ff, 0xc819, 0x21, 0 + .dw 0xa240, 0xc819, 0xa27f, 0xc819, 0x21, 0 + .dw 0xa2c0, 0xc819, 0xa2ff, 0xc819, 0x21, 0 + .dw 0xa340, 0xc819, 0xa37f, 0xc819, 0x21, 0 + .dw 0xa3c0, 0xc819, 0xa3ff, 0xc819, 0x21, 0 + .dw 0xa440, 0xc819, 0xa47f, 0xc819, 0x21, 0 + .dw 0xa4c0, 0xc819, 0xa4ff, 0xc819, 0x21, 0 + .dw 0xa540, 0xc819, 0xa57f, 0xc819, 0x21, 0 + .dw 0xa5c0, 0xc819, 0xa5ff, 0xc819, 0x21, 0 + .dw 0xa640, 0xc819, 0xa67f, 0xc819, 0x21, 0 + .dw 0xa6c0, 0xc819, 0xa6ff, 0xc819, 0x21, 0 + .dw 0xa740, 0xc819, 0xa77f, 0xc819, 0x21, 0 + .dw 0xa7c0, 0xc819, 0xa7ff, 0xc819, 0x21, 0 + .dw 0xa840, 0xc819, 0xa87f, 0xc819, 0x21, 0 + .dw 0xa8c0, 0xc819, 0xa8ff, 0xc819, 0x21, 0 + .dw 0xa940, 0xc819, 0xa97f, 0xc819, 0x21, 0 + .dw 0xa9c0, 0xc819, 0xa9ff, 0xc819, 0x21, 0 + .dw 0xaa40, 0xc819, 0xaa7f, 0xc819, 0x21, 0 + .dw 0xaac0, 0xc819, 0xaaff, 0xc819, 0x21, 0 + .dw 0xab40, 0xc819, 0xab7f, 0xc819, 0x21, 0 + .dw 0xabc0, 0xc819, 0xabff, 0xc819, 0x21, 0 + .dw 0xac40, 0xc819, 0xac7f, 0xc819, 0x21, 0 + .dw 0xacc0, 0xc819, 0xacff, 0xc819, 0x21, 0 + .dw 0xad40, 0xc819, 0xad7f, 0xc819, 0x21, 0 + .dw 0xadc0, 0xc819, 0xadff, 0xc819, 0x21, 0 + .dw 0xae40, 0xc819, 0xae7f, 0xc819, 0x21, 0 + .dw 0xaec0, 0xc819, 0xaeff, 0xc819, 0x21, 0 + .dw 0xaf40, 0xc819, 0xaf7f, 0xc819, 0x21, 0 + .dw 0xafc0, 0xc819, 0xafff, 0xc819, 0x21, 0 + .dw 0xb040, 0xc819, 0xb07f, 0xc819, 0x21, 0 + .dw 0xb0c0, 0xc819, 0xb0ff, 0xc819, 0x21, 0 + .dw 0xb140, 0xc819, 0xb17f, 0xc819, 0x21, 0 + .dw 0xb1c0, 0xc819, 0xb1ff, 0xc819, 0x21, 0 + .dw 0xb240, 0xc819, 0xb27f, 0xc819, 0x21, 0 + .dw 0xb2c0, 0xc819, 0xb2ff, 0xc819, 0x21, 0 + .dw 0xb340, 0xc819, 0xb37f, 0xc819, 0x21, 0 + .dw 0xb3c0, 0xc819, 0xb3ff, 0xc819, 0x21, 0 + .dw 0xb440, 0xc819, 0xb47f, 0xc819, 0x21, 0 + .dw 0xb4c0, 0xc819, 0xb4ff, 0xc819, 0x21, 0 + .dw 0xb540, 0xc819, 0xb57f, 0xc819, 0x21, 0 + .dw 0xb5c0, 0xc819, 0xb5ff, 0xc819, 0x21, 0 + .dw 0xb640, 0xc819, 0xb67f, 0xc819, 0x21, 0 + .dw 0xb6c0, 0xc819, 0xb6ff, 0xc819, 0x21, 0 + .dw 0xb740, 0xc819, 0xb77f, 0xc819, 0x21, 0 + .dw 0xb7c0, 0xc819, 0xb7ff, 0xc819, 0x21, 0 + .dw 0xb840, 0xc819, 0xb87f, 0xc819, 0x21, 0 + .dw 0xb8c0, 0xc819, 0xb8ff, 0xc819, 0x21, 0 + .dw 0xb940, 0xc819, 0xb97f, 0xc819, 0x21, 0 + .dw 0xb9c0, 0xc819, 0xdfff, 0xc819, 0x21, 0 + .dw 0xe040, 0xc819, 0xe07f, 0xc819, 0x21, 0 + .dw 0xe0c0, 0xc819, 0xe0ff, 0xc819, 0x21, 0 + .dw 0xe140, 0xc819, 0xe17f, 0xc819, 0x21, 0 + .dw 0xe1c0, 0xc819, 0xe1ff, 0xc819, 0x21, 0 + .dw 0xe240, 0xc819, 0xe27f, 0xc819, 0x21, 0 + .dw 0xe2c0, 0xc819, 0xe2ff, 0xc819, 0x21, 0 + .dw 0xe340, 0xc819, 0xe37f, 0xc819, 0x21, 0 + .dw 0xe3c0, 0xc819, 0xe3ff, 0xc819, 0x21, 0 + .dw 0xe440, 0xc819, 0xe47f, 0xc819, 0x21, 0 + .dw 0xe4c0, 0xc819, 0xe4ff, 0xc819, 0x21, 0 + .dw 0xe540, 0xc819, 0xe57f, 0xc819, 0x21, 0 + .dw 0xe5c0, 0xc819, 0xe5ff, 0xc819, 0x21, 0 + .dw 0xe640, 0xc819, 0xe67f, 0xc819, 0x21, 0 + .dw 0xe6c0, 0xc819, 0xe6ff, 0xc819, 0x21, 0 + .dw 0xe740, 0xc819, 0xe77f, 0xc819, 0x21, 0 + .dw 0xe7c0, 0xc819, 0xe7ff, 0xc819, 0x21, 0 + .dw 0xe840, 0xc819, 0xe87f, 0xc819, 0x21, 0 + .dw 0xe8c0, 0xc819, 0xe8ff, 0xc819, 0x21, 0 + .dw 0xe940, 0xc819, 0xe97f, 0xc819, 0x21, 0 + .dw 0xe9c0, 0xc819, 0xe9ff, 0xc819, 0x21, 0 + .dw 0xea40, 0xc819, 0xea7f, 0xc819, 0x21, 0 + .dw 0xeac0, 0xc819, 0xeaff, 0xc819, 0x21, 0 + .dw 0xeb40, 0xc819, 0xeb7f, 0xc819, 0x21, 0 + .dw 0xebc0, 0xc819, 0xebff, 0xc819, 0x21, 0 + .dw 0xec40, 0xc819, 0xec7f, 0xc819, 0x21, 0 + .dw 0xecc0, 0xc819, 0xecff, 0xc819, 0x21, 0 + .dw 0xed40, 0xc819, 0xed7f, 0xc819, 0x21, 0 + .dw 0xedc0, 0xc819, 0xedff, 0xc819, 0x21, 0 + .dw 0xee40, 0xc819, 0xee7f, 0xc819, 0x21, 0 + .dw 0xeec0, 0xc819, 0xeeff, 0xc819, 0x21, 0 + .dw 0xef40, 0xc819, 0xef7f, 0xc819, 0x21, 0 + .dw 0xefc0, 0xc819, 0xefff, 0xc819, 0x21, 0 + .dw 0xf040, 0xc819, 0xf07f, 0xc819, 0x21, 0 + .dw 0xf0c0, 0xc819, 0xf0ff, 0xc819, 0x21, 0 + .dw 0xf140, 0xc819, 0xf17f, 0xc819, 0x21, 0 + .dw 0xf1c0, 0xc819, 0xf1ff, 0xc819, 0x21, 0 + .dw 0xf240, 0xc819, 0xf27f, 0xc819, 0x21, 0 + .dw 0xf2c0, 0xc819, 0xf2ff, 0xc819, 0x21, 0 + .dw 0xf340, 0xc819, 0xf37f, 0xc819, 0x21, 0 + .dw 0xf3c0, 0xc819, 0xf3ff, 0xc819, 0x21, 0 + .dw 0xf440, 0xc819, 0xf47f, 0xc819, 0x21, 0 + .dw 0xf4c0, 0xc819, 0xf4ff, 0xc819, 0x21, 0 + .dw 0xf540, 0xc819, 0xf57f, 0xc819, 0x21, 0 + .dw 0xf5c0, 0xc819, 0xf5ff, 0xc819, 0x21, 0 + .dw 0xf640, 0xc819, 0xf67f, 0xc819, 0x21, 0 + .dw 0xf6c0, 0xc819, 0xf6ff, 0xc819, 0x21, 0 + .dw 0xf740, 0xc819, 0xf77f, 0xc819, 0x21, 0 + .dw 0xf7c0, 0xc819, 0xf7ff, 0xc819, 0x21, 0 + .dw 0xf840, 0xc819, 0xf87f, 0xc819, 0x21, 0 + .dw 0xf8c0, 0xc819, 0xf8ff, 0xc819, 0x21, 0 + .dw 0xf940, 0xc819, 0xf97f, 0xc819, 0x21, 0 + .dw 0xf9c0, 0xc819, 0x1fff, 0xc81a, 0x21, 0 + .dw 0x2040, 0xc81a, 0x207f, 0xc81a, 0x21, 0 + .dw 0x20c0, 0xc81a, 0x20ff, 0xc81a, 0x21, 0 + .dw 0x2140, 0xc81a, 0x217f, 0xc81a, 0x21, 0 + .dw 0x21c0, 0xc81a, 0x21ff, 0xc81a, 0x21, 0 + .dw 0x2240, 0xc81a, 0x227f, 0xc81a, 0x21, 0 + .dw 0x22c0, 0xc81a, 0x22ff, 0xc81a, 0x21, 0 + .dw 0x2340, 0xc81a, 0x237f, 0xc81a, 0x21, 0 + .dw 0x23c0, 0xc81a, 0x23ff, 0xc81a, 0x21, 0 + .dw 0x2440, 0xc81a, 0x247f, 0xc81a, 0x21, 0 + .dw 0x24c0, 0xc81a, 0x24ff, 0xc81a, 0x21, 0 + .dw 0x2540, 0xc81a, 0x257f, 0xc81a, 0x21, 0 + .dw 0x25c0, 0xc81a, 0x25ff, 0xc81a, 0x21, 0 + .dw 0x2640, 0xc81a, 0x267f, 0xc81a, 0x21, 0 + .dw 0x26c0, 0xc81a, 0x26ff, 0xc81a, 0x21, 0 + .dw 0x2740, 0xc81a, 0x277f, 0xc81a, 0x21, 0 + .dw 0x27c0, 0xc81a, 0x27ff, 0xc81a, 0x21, 0 + .dw 0x2840, 0xc81a, 0x287f, 0xc81a, 0x21, 0 + .dw 0x28c0, 0xc81a, 0x28ff, 0xc81a, 0x21, 0 + .dw 0x2940, 0xc81a, 0x297f, 0xc81a, 0x21, 0 + .dw 0x29c0, 0xc81a, 0x29ff, 0xc81a, 0x21, 0 + .dw 0x2a40, 0xc81a, 0x2a7f, 0xc81a, 0x21, 0 + .dw 0x2ac0, 0xc81a, 0x2aff, 0xc81a, 0x21, 0 + .dw 0x2b40, 0xc81a, 0x2b7f, 0xc81a, 0x21, 0 + .dw 0x2bc0, 0xc81a, 0x2bff, 0xc81a, 0x21, 0 + .dw 0x2c40, 0xc81a, 0x2c7f, 0xc81a, 0x21, 0 + .dw 0x2cc0, 0xc81a, 0x2cff, 0xc81a, 0x21, 0 + .dw 0x2d40, 0xc81a, 0x2d7f, 0xc81a, 0x21, 0 + .dw 0x2dc0, 0xc81a, 0x2dff, 0xc81a, 0x21, 0 + .dw 0x2e40, 0xc81a, 0x2e7f, 0xc81a, 0x21, 0 + .dw 0x2ec0, 0xc81a, 0x2eff, 0xc81a, 0x21, 0 + .dw 0x2f40, 0xc81a, 0x2f7f, 0xc81a, 0x21, 0 + .dw 0x2fc0, 0xc81a, 0x2fff, 0xc81a, 0x21, 0 + .dw 0x3040, 0xc81a, 0x307f, 0xc81a, 0x21, 0 + .dw 0x30c0, 0xc81a, 0x30ff, 0xc81a, 0x21, 0 + .dw 0x3140, 0xc81a, 0x317f, 0xc81a, 0x21, 0 + .dw 0x31c0, 0xc81a, 0x31ff, 0xc81a, 0x21, 0 + .dw 0x3240, 0xc81a, 0x327f, 0xc81a, 0x21, 0 + .dw 0x32c0, 0xc81a, 0x32ff, 0xc81a, 0x21, 0 + .dw 0x3340, 0xc81a, 0x337f, 0xc81a, 0x21, 0 + .dw 0x33c0, 0xc81a, 0x33ff, 0xc81a, 0x21, 0 + .dw 0x3440, 0xc81a, 0x347f, 0xc81a, 0x21, 0 + .dw 0x34c0, 0xc81a, 0x34ff, 0xc81a, 0x21, 0 + .dw 0x3540, 0xc81a, 0x357f, 0xc81a, 0x21, 0 + .dw 0x35c0, 0xc81a, 0x35ff, 0xc81a, 0x21, 0 + .dw 0x3640, 0xc81a, 0x367f, 0xc81a, 0x21, 0 + .dw 0x36c0, 0xc81a, 0x36ff, 0xc81a, 0x21, 0 + .dw 0x3740, 0xc81a, 0x377f, 0xc81a, 0x21, 0 + .dw 0x37c0, 0xc81a, 0x37ff, 0xc81a, 0x21, 0 + .dw 0x3840, 0xc81a, 0x387f, 0xc81a, 0x21, 0 + .dw 0x38c0, 0xc81a, 0x38ff, 0xc81a, 0x21, 0 + .dw 0x3940, 0xc81a, 0x397f, 0xc81a, 0x21, 0 + .dw 0x39c0, 0xc81a, 0x5fff, 0xc81a, 0x21, 0 + .dw 0x6040, 0xc81a, 0x607f, 0xc81a, 0x21, 0 + .dw 0x60c0, 0xc81a, 0x60ff, 0xc81a, 0x21, 0 + .dw 0x6140, 0xc81a, 0x617f, 0xc81a, 0x21, 0 + .dw 0x61c0, 0xc81a, 0x61ff, 0xc81a, 0x21, 0 + .dw 0x6240, 0xc81a, 0x627f, 0xc81a, 0x21, 0 + .dw 0x62c0, 0xc81a, 0x62ff, 0xc81a, 0x21, 0 + .dw 0x6340, 0xc81a, 0x637f, 0xc81a, 0x21, 0 + .dw 0x63c0, 0xc81a, 0x63ff, 0xc81a, 0x21, 0 + .dw 0x6440, 0xc81a, 0x647f, 0xc81a, 0x21, 0 + .dw 0x64c0, 0xc81a, 0x64ff, 0xc81a, 0x21, 0 + .dw 0x6540, 0xc81a, 0x657f, 0xc81a, 0x21, 0 + .dw 0x65c0, 0xc81a, 0x65ff, 0xc81a, 0x21, 0 + .dw 0x6640, 0xc81a, 0x667f, 0xc81a, 0x21, 0 + .dw 0x66c0, 0xc81a, 0x66ff, 0xc81a, 0x21, 0 + .dw 0x6740, 0xc81a, 0x677f, 0xc81a, 0x21, 0 + .dw 0x67c0, 0xc81a, 0x67ff, 0xc81a, 0x21, 0 + .dw 0x6840, 0xc81a, 0x687f, 0xc81a, 0x21, 0 + .dw 0x68c0, 0xc81a, 0x68ff, 0xc81a, 0x21, 0 + .dw 0x6940, 0xc81a, 0x697f, 0xc81a, 0x21, 0 + .dw 0x69c0, 0xc81a, 0x69ff, 0xc81a, 0x21, 0 + .dw 0x6a40, 0xc81a, 0x6a7f, 0xc81a, 0x21, 0 + .dw 0x6ac0, 0xc81a, 0x6aff, 0xc81a, 0x21, 0 + .dw 0x6b40, 0xc81a, 0x6b7f, 0xc81a, 0x21, 0 + .dw 0x6bc0, 0xc81a, 0x6bff, 0xc81a, 0x21, 0 + .dw 0x6c40, 0xc81a, 0x6c7f, 0xc81a, 0x21, 0 + .dw 0x6cc0, 0xc81a, 0x6cff, 0xc81a, 0x21, 0 + .dw 0x6d40, 0xc81a, 0x6d7f, 0xc81a, 0x21, 0 + .dw 0x6dc0, 0xc81a, 0x6dff, 0xc81a, 0x21, 0 + .dw 0x6e40, 0xc81a, 0x6e7f, 0xc81a, 0x21, 0 + .dw 0x6ec0, 0xc81a, 0x6eff, 0xc81a, 0x21, 0 + .dw 0x6f40, 0xc81a, 0x6f7f, 0xc81a, 0x21, 0 + .dw 0x6fc0, 0xc81a, 0x6fff, 0xc81a, 0x21, 0 + .dw 0x7040, 0xc81a, 0x707f, 0xc81a, 0x21, 0 + .dw 0x70c0, 0xc81a, 0x70ff, 0xc81a, 0x21, 0 + .dw 0x7140, 0xc81a, 0x717f, 0xc81a, 0x21, 0 + .dw 0x71c0, 0xc81a, 0x71ff, 0xc81a, 0x21, 0 + .dw 0x7240, 0xc81a, 0x727f, 0xc81a, 0x21, 0 + .dw 0x72c0, 0xc81a, 0x72ff, 0xc81a, 0x21, 0 + .dw 0x7340, 0xc81a, 0x737f, 0xc81a, 0x21, 0 + .dw 0x73c0, 0xc81a, 0x73ff, 0xc81a, 0x21, 0 + .dw 0x7440, 0xc81a, 0x747f, 0xc81a, 0x21, 0 + .dw 0x74c0, 0xc81a, 0x74ff, 0xc81a, 0x21, 0 + .dw 0x7540, 0xc81a, 0x757f, 0xc81a, 0x21, 0 + .dw 0x75c0, 0xc81a, 0x75ff, 0xc81a, 0x21, 0 + .dw 0x7640, 0xc81a, 0x767f, 0xc81a, 0x21, 0 + .dw 0x76c0, 0xc81a, 0x76ff, 0xc81a, 0x21, 0 + .dw 0x7740, 0xc81a, 0x777f, 0xc81a, 0x21, 0 + .dw 0x77c0, 0xc81a, 0x77ff, 0xc81a, 0x21, 0 + .dw 0x7840, 0xc81a, 0x787f, 0xc81a, 0x21, 0 + .dw 0x78c0, 0xc81a, 0x78ff, 0xc81a, 0x21, 0 + .dw 0x7940, 0xc81a, 0x797f, 0xc81a, 0x21, 0 + .dw 0x79c0, 0xc81a, 0x9fff, 0xc81a, 0x21, 0 + .dw 0xa040, 0xc81a, 0xa07f, 0xc81a, 0x21, 0 + .dw 0xa0c0, 0xc81a, 0xa0ff, 0xc81a, 0x21, 0 + .dw 0xa140, 0xc81a, 0xa17f, 0xc81a, 0x21, 0 + .dw 0xa1c0, 0xc81a, 0xa1ff, 0xc81a, 0x21, 0 + .dw 0xa240, 0xc81a, 0xa27f, 0xc81a, 0x21, 0 + .dw 0xa2c0, 0xc81a, 0xa2ff, 0xc81a, 0x21, 0 + .dw 0xa340, 0xc81a, 0xa37f, 0xc81a, 0x21, 0 + .dw 0xa3c0, 0xc81a, 0xa3ff, 0xc81a, 0x21, 0 + .dw 0xa440, 0xc81a, 0xa47f, 0xc81a, 0x21, 0 + .dw 0xa4c0, 0xc81a, 0xa4ff, 0xc81a, 0x21, 0 + .dw 0xa540, 0xc81a, 0xa57f, 0xc81a, 0x21, 0 + .dw 0xa5c0, 0xc81a, 0xa5ff, 0xc81a, 0x21, 0 + .dw 0xa640, 0xc81a, 0xa67f, 0xc81a, 0x21, 0 + .dw 0xa6c0, 0xc81a, 0xa6ff, 0xc81a, 0x21, 0 + .dw 0xa740, 0xc81a, 0xa77f, 0xc81a, 0x21, 0 + .dw 0xa7c0, 0xc81a, 0xa7ff, 0xc81a, 0x21, 0 + .dw 0xa840, 0xc81a, 0xa87f, 0xc81a, 0x21, 0 + .dw 0xa8c0, 0xc81a, 0xa8ff, 0xc81a, 0x21, 0 + .dw 0xa940, 0xc81a, 0xa97f, 0xc81a, 0x21, 0 + .dw 0xa9c0, 0xc81a, 0xa9ff, 0xc81a, 0x21, 0 + .dw 0xaa40, 0xc81a, 0xaa7f, 0xc81a, 0x21, 0 + .dw 0xaac0, 0xc81a, 0xaaff, 0xc81a, 0x21, 0 + .dw 0xab40, 0xc81a, 0xab7f, 0xc81a, 0x21, 0 + .dw 0xabc0, 0xc81a, 0xabff, 0xc81a, 0x21, 0 + .dw 0xac40, 0xc81a, 0xac7f, 0xc81a, 0x21, 0 + .dw 0xacc0, 0xc81a, 0xacff, 0xc81a, 0x21, 0 + .dw 0xad40, 0xc81a, 0xad7f, 0xc81a, 0x21, 0 + .dw 0xadc0, 0xc81a, 0xadff, 0xc81a, 0x21, 0 + .dw 0xae40, 0xc81a, 0xae7f, 0xc81a, 0x21, 0 + .dw 0xaec0, 0xc81a, 0xaeff, 0xc81a, 0x21, 0 + .dw 0xaf40, 0xc81a, 0xaf7f, 0xc81a, 0x21, 0 + .dw 0xafc0, 0xc81a, 0xafff, 0xc81a, 0x21, 0 + .dw 0xb040, 0xc81a, 0xb07f, 0xc81a, 0x21, 0 + .dw 0xb0c0, 0xc81a, 0xb0ff, 0xc81a, 0x21, 0 + .dw 0xb140, 0xc81a, 0xb17f, 0xc81a, 0x21, 0 + .dw 0xb1c0, 0xc81a, 0xb1ff, 0xc81a, 0x21, 0 + .dw 0xb240, 0xc81a, 0xb27f, 0xc81a, 0x21, 0 + .dw 0xb2c0, 0xc81a, 0xb2ff, 0xc81a, 0x21, 0 + .dw 0xb340, 0xc81a, 0xb37f, 0xc81a, 0x21, 0 + .dw 0xb3c0, 0xc81a, 0xb3ff, 0xc81a, 0x21, 0 + .dw 0xb440, 0xc81a, 0xb47f, 0xc81a, 0x21, 0 + .dw 0xb4c0, 0xc81a, 0xb4ff, 0xc81a, 0x21, 0 + .dw 0xb540, 0xc81a, 0xb57f, 0xc81a, 0x21, 0 + .dw 0xb5c0, 0xc81a, 0xb5ff, 0xc81a, 0x21, 0 + .dw 0xb640, 0xc81a, 0xb67f, 0xc81a, 0x21, 0 + .dw 0xb6c0, 0xc81a, 0xb6ff, 0xc81a, 0x21, 0 + .dw 0xb740, 0xc81a, 0xb77f, 0xc81a, 0x21, 0 + .dw 0xb7c0, 0xc81a, 0xb7ff, 0xc81a, 0x21, 0 + .dw 0xb840, 0xc81a, 0xb87f, 0xc81a, 0x21, 0 + .dw 0xb8c0, 0xc81a, 0xb8ff, 0xc81a, 0x21, 0 + .dw 0xb940, 0xc81a, 0xb97f, 0xc81a, 0x21, 0 + .dw 0xb9c0, 0xc81a, 0xdfff, 0xc81a, 0x21, 0 + .dw 0xe040, 0xc81a, 0xe07f, 0xc81a, 0x21, 0 + .dw 0xe0c0, 0xc81a, 0xe0ff, 0xc81a, 0x21, 0 + .dw 0xe140, 0xc81a, 0xe17f, 0xc81a, 0x21, 0 + .dw 0xe1c0, 0xc81a, 0xe1ff, 0xc81a, 0x21, 0 + .dw 0xe240, 0xc81a, 0xe27f, 0xc81a, 0x21, 0 + .dw 0xe2c0, 0xc81a, 0xe2ff, 0xc81a, 0x21, 0 + .dw 0xe340, 0xc81a, 0xe37f, 0xc81a, 0x21, 0 + .dw 0xe3c0, 0xc81a, 0xe3ff, 0xc81a, 0x21, 0 + .dw 0xe440, 0xc81a, 0xe47f, 0xc81a, 0x21, 0 + .dw 0xe4c0, 0xc81a, 0xe4ff, 0xc81a, 0x21, 0 + .dw 0xe540, 0xc81a, 0xe57f, 0xc81a, 0x21, 0 + .dw 0xe5c0, 0xc81a, 0xe5ff, 0xc81a, 0x21, 0 + .dw 0xe640, 0xc81a, 0xe67f, 0xc81a, 0x21, 0 + .dw 0xe6c0, 0xc81a, 0xe6ff, 0xc81a, 0x21, 0 + .dw 0xe740, 0xc81a, 0xe77f, 0xc81a, 0x21, 0 + .dw 0xe7c0, 0xc81a, 0xe7ff, 0xc81a, 0x21, 0 + .dw 0xe840, 0xc81a, 0xe87f, 0xc81a, 0x21, 0 + .dw 0xe8c0, 0xc81a, 0xe8ff, 0xc81a, 0x21, 0 + .dw 0xe940, 0xc81a, 0xe97f, 0xc81a, 0x21, 0 + .dw 0xe9c0, 0xc81a, 0xe9ff, 0xc81a, 0x21, 0 + .dw 0xea40, 0xc81a, 0xea7f, 0xc81a, 0x21, 0 + .dw 0xeac0, 0xc81a, 0xeaff, 0xc81a, 0x21, 0 + .dw 0xeb40, 0xc81a, 0xeb7f, 0xc81a, 0x21, 0 + .dw 0xebc0, 0xc81a, 0xebff, 0xc81a, 0x21, 0 + .dw 0xec40, 0xc81a, 0xec7f, 0xc81a, 0x21, 0 + .dw 0xecc0, 0xc81a, 0xecff, 0xc81a, 0x21, 0 + .dw 0xed40, 0xc81a, 0xed7f, 0xc81a, 0x21, 0 + .dw 0xedc0, 0xc81a, 0xedff, 0xc81a, 0x21, 0 + .dw 0xee40, 0xc81a, 0xee7f, 0xc81a, 0x21, 0 + .dw 0xeec0, 0xc81a, 0xeeff, 0xc81a, 0x21, 0 + .dw 0xef40, 0xc81a, 0xef7f, 0xc81a, 0x21, 0 + .dw 0xefc0, 0xc81a, 0xefff, 0xc81a, 0x21, 0 + .dw 0xf040, 0xc81a, 0xf07f, 0xc81a, 0x21, 0 + .dw 0xf0c0, 0xc81a, 0xf0ff, 0xc81a, 0x21, 0 + .dw 0xf140, 0xc81a, 0xf17f, 0xc81a, 0x21, 0 + .dw 0xf1c0, 0xc81a, 0xf1ff, 0xc81a, 0x21, 0 + .dw 0xf240, 0xc81a, 0xf27f, 0xc81a, 0x21, 0 + .dw 0xf2c0, 0xc81a, 0xf2ff, 0xc81a, 0x21, 0 + .dw 0xf340, 0xc81a, 0xf37f, 0xc81a, 0x21, 0 + .dw 0xf3c0, 0xc81a, 0xf3ff, 0xc81a, 0x21, 0 + .dw 0xf440, 0xc81a, 0xf47f, 0xc81a, 0x21, 0 + .dw 0xf4c0, 0xc81a, 0xf4ff, 0xc81a, 0x21, 0 + .dw 0xf540, 0xc81a, 0xf57f, 0xc81a, 0x21, 0 + .dw 0xf5c0, 0xc81a, 0xf5ff, 0xc81a, 0x21, 0 + .dw 0xf640, 0xc81a, 0xf67f, 0xc81a, 0x21, 0 + .dw 0xf6c0, 0xc81a, 0xf6ff, 0xc81a, 0x21, 0 + .dw 0xf740, 0xc81a, 0xf77f, 0xc81a, 0x21, 0 + .dw 0xf7c0, 0xc81a, 0xf7ff, 0xc81a, 0x21, 0 + .dw 0xf840, 0xc81a, 0xf87f, 0xc81a, 0x21, 0 + .dw 0xf8c0, 0xc81a, 0xf8ff, 0xc81a, 0x21, 0 + .dw 0xf940, 0xc81a, 0xf97f, 0xc81a, 0x21, 0 + .dw 0xf9c0, 0xc81a, 0xffff, 0xc81b, 0x21, 0 + .dw 0x0040, 0xc81c, 0x007f, 0xc81c, 0x21, 0 + .dw 0x00c0, 0xc81c, 0x00ff, 0xc81c, 0x21, 0 + .dw 0x0140, 0xc81c, 0x017f, 0xc81c, 0x21, 0 + .dw 0x01c0, 0xc81c, 0x01ff, 0xc81c, 0x21, 0 + .dw 0x0240, 0xc81c, 0x027f, 0xc81c, 0x21, 0 + .dw 0x02c0, 0xc81c, 0x02ff, 0xc81c, 0x21, 0 + .dw 0x0340, 0xc81c, 0x037f, 0xc81c, 0x21, 0 + .dw 0x03c0, 0xc81c, 0x03ff, 0xc81c, 0x21, 0 + .dw 0x0440, 0xc81c, 0x047f, 0xc81c, 0x21, 0 + .dw 0x04c0, 0xc81c, 0x04ff, 0xc81c, 0x21, 0 + .dw 0x0540, 0xc81c, 0x057f, 0xc81c, 0x21, 0 + .dw 0x05c0, 0xc81c, 0x05ff, 0xc81c, 0x21, 0 + .dw 0x0640, 0xc81c, 0x067f, 0xc81c, 0x21, 0 + .dw 0x06c0, 0xc81c, 0x06ff, 0xc81c, 0x21, 0 + .dw 0x0740, 0xc81c, 0x077f, 0xc81c, 0x21, 0 + .dw 0x07c0, 0xc81c, 0x07ff, 0xc81c, 0x21, 0 + .dw 0x0840, 0xc81c, 0x087f, 0xc81c, 0x21, 0 + .dw 0x08c0, 0xc81c, 0x08ff, 0xc81c, 0x21, 0 + .dw 0x0940, 0xc81c, 0x097f, 0xc81c, 0x21, 0 + .dw 0x09c0, 0xc81c, 0x09ff, 0xc81c, 0x21, 0 + .dw 0x0a40, 0xc81c, 0x0a7f, 0xc81c, 0x21, 0 + .dw 0x0ac0, 0xc81c, 0x0aff, 0xc81c, 0x21, 0 + .dw 0x0b40, 0xc81c, 0x0b7f, 0xc81c, 0x21, 0 + .dw 0x0bc0, 0xc81c, 0x0bff, 0xc81c, 0x21, 0 + .dw 0x0c40, 0xc81c, 0x0c7f, 0xc81c, 0x21, 0 + .dw 0x0cc0, 0xc81c, 0x0cff, 0xc81c, 0x21, 0 + .dw 0x0d40, 0xc81c, 0x0d7f, 0xc81c, 0x21, 0 + .dw 0x0dc0, 0xc81c, 0x0dff, 0xc81c, 0x21, 0 + .dw 0x0e40, 0xc81c, 0x0e7f, 0xc81c, 0x21, 0 + .dw 0x0ec0, 0xc81c, 0x0eff, 0xc81c, 0x21, 0 + .dw 0x0f40, 0xc81c, 0x0f7f, 0xc81c, 0x21, 0 + .dw 0x0fc0, 0xc81c, 0x0fff, 0xc81c, 0x21, 0 + .dw 0x1040, 0xc81c, 0x107f, 0xc81c, 0x21, 0 + .dw 0x10c0, 0xc81c, 0x10ff, 0xc81c, 0x21, 0 + .dw 0x1140, 0xc81c, 0x117f, 0xc81c, 0x21, 0 + .dw 0x11c0, 0xc81c, 0x11ff, 0xc81c, 0x21, 0 + .dw 0x1240, 0xc81c, 0x127f, 0xc81c, 0x21, 0 + .dw 0x12c0, 0xc81c, 0x12ff, 0xc81c, 0x21, 0 + .dw 0x1340, 0xc81c, 0x137f, 0xc81c, 0x21, 0 + .dw 0x13c0, 0xc81c, 0x13ff, 0xc81c, 0x21, 0 + .dw 0x1440, 0xc81c, 0x147f, 0xc81c, 0x21, 0 + .dw 0x14c0, 0xc81c, 0x14ff, 0xc81c, 0x21, 0 + .dw 0x1540, 0xc81c, 0x157f, 0xc81c, 0x21, 0 + .dw 0x15c0, 0xc81c, 0x15ff, 0xc81c, 0x21, 0 + .dw 0x1640, 0xc81c, 0x167f, 0xc81c, 0x21, 0 + .dw 0x16c0, 0xc81c, 0x16ff, 0xc81c, 0x21, 0 + .dw 0x1740, 0xc81c, 0x177f, 0xc81c, 0x21, 0 + .dw 0x17c0, 0xc81c, 0x17ff, 0xc81c, 0x21, 0 + .dw 0x1840, 0xc81c, 0x187f, 0xc81c, 0x21, 0 + .dw 0x18c0, 0xc81c, 0x18ff, 0xc81c, 0x21, 0 + .dw 0x1940, 0xc81c, 0x197f, 0xc81c, 0x21, 0 + .dw 0x19c0, 0xc81c, 0x1fff, 0xc81c, 0x21, 0 + .dw 0x2040, 0xc81c, 0x207f, 0xc81c, 0x21, 0 + .dw 0x20c0, 0xc81c, 0x20ff, 0xc81c, 0x21, 0 + .dw 0x2140, 0xc81c, 0x217f, 0xc81c, 0x21, 0 + .dw 0x21c0, 0xc81c, 0x21ff, 0xc81c, 0x21, 0 + .dw 0x2240, 0xc81c, 0x227f, 0xc81c, 0x21, 0 + .dw 0x22c0, 0xc81c, 0x22ff, 0xc81c, 0x21, 0 + .dw 0x2340, 0xc81c, 0x237f, 0xc81c, 0x21, 0 + .dw 0x23c0, 0xc81c, 0x23ff, 0xc81c, 0x21, 0 + .dw 0x2440, 0xc81c, 0x247f, 0xc81c, 0x21, 0 + .dw 0x24c0, 0xc81c, 0x24ff, 0xc81c, 0x21, 0 + .dw 0x2540, 0xc81c, 0x257f, 0xc81c, 0x21, 0 + .dw 0x25c0, 0xc81c, 0x25ff, 0xc81c, 0x21, 0 + .dw 0x2640, 0xc81c, 0x267f, 0xc81c, 0x21, 0 + .dw 0x26c0, 0xc81c, 0x26ff, 0xc81c, 0x21, 0 + .dw 0x2740, 0xc81c, 0x277f, 0xc81c, 0x21, 0 + .dw 0x27c0, 0xc81c, 0x27ff, 0xc81c, 0x21, 0 + .dw 0x2840, 0xc81c, 0x287f, 0xc81c, 0x21, 0 + .dw 0x28c0, 0xc81c, 0x28ff, 0xc81c, 0x21, 0 + .dw 0x2940, 0xc81c, 0x297f, 0xc81c, 0x21, 0 + .dw 0x29c0, 0xc81c, 0x29ff, 0xc81c, 0x21, 0 + .dw 0x2a40, 0xc81c, 0x2a7f, 0xc81c, 0x21, 0 + .dw 0x2ac0, 0xc81c, 0x2aff, 0xc81c, 0x21, 0 + .dw 0x2b40, 0xc81c, 0x2b7f, 0xc81c, 0x21, 0 + .dw 0x2bc0, 0xc81c, 0x2bff, 0xc81c, 0x21, 0 + .dw 0x2c40, 0xc81c, 0x2c7f, 0xc81c, 0x21, 0 + .dw 0x2cc0, 0xc81c, 0x2cff, 0xc81c, 0x21, 0 + .dw 0x2d40, 0xc81c, 0x2d7f, 0xc81c, 0x21, 0 + .dw 0x2dc0, 0xc81c, 0x2dff, 0xc81c, 0x21, 0 + .dw 0x2e40, 0xc81c, 0x2e7f, 0xc81c, 0x21, 0 + .dw 0x2ec0, 0xc81c, 0x2eff, 0xc81c, 0x21, 0 + .dw 0x2f40, 0xc81c, 0x2f7f, 0xc81c, 0x21, 0 + .dw 0x2fc0, 0xc81c, 0x2fff, 0xc81c, 0x21, 0 + .dw 0x3040, 0xc81c, 0x307f, 0xc81c, 0x21, 0 + .dw 0x30c0, 0xc81c, 0x30ff, 0xc81c, 0x21, 0 + .dw 0x3140, 0xc81c, 0x317f, 0xc81c, 0x21, 0 + .dw 0x31c0, 0xc81c, 0x31ff, 0xc81c, 0x21, 0 + .dw 0x3240, 0xc81c, 0x327f, 0xc81c, 0x21, 0 + .dw 0x32c0, 0xc81c, 0x32ff, 0xc81c, 0x21, 0 + .dw 0x3340, 0xc81c, 0x337f, 0xc81c, 0x21, 0 + .dw 0x33c0, 0xc81c, 0x33ff, 0xc81c, 0x21, 0 + .dw 0x3440, 0xc81c, 0x347f, 0xc81c, 0x21, 0 + .dw 0x34c0, 0xc81c, 0x34ff, 0xc81c, 0x21, 0 + .dw 0x3540, 0xc81c, 0x357f, 0xc81c, 0x21, 0 + .dw 0x35c0, 0xc81c, 0x35ff, 0xc81c, 0x21, 0 + .dw 0x3640, 0xc81c, 0x367f, 0xc81c, 0x21, 0 + .dw 0x36c0, 0xc81c, 0x36ff, 0xc81c, 0x21, 0 + .dw 0x3740, 0xc81c, 0x377f, 0xc81c, 0x21, 0 + .dw 0x37c0, 0xc81c, 0x37ff, 0xc81c, 0x21, 0 + .dw 0x3840, 0xc81c, 0x387f, 0xc81c, 0x21, 0 + .dw 0x38c0, 0xc81c, 0x38ff, 0xc81c, 0x21, 0 + .dw 0x3940, 0xc81c, 0x397f, 0xc81c, 0x21, 0 + .dw 0x39c0, 0xc81c, 0x3fff, 0xc81c, 0x21, 0 + .dw 0x4040, 0xc81c, 0x407f, 0xc81c, 0x21, 0 + .dw 0x40c0, 0xc81c, 0x40ff, 0xc81c, 0x21, 0 + .dw 0x4140, 0xc81c, 0x417f, 0xc81c, 0x21, 0 + .dw 0x41c0, 0xc81c, 0x41ff, 0xc81c, 0x21, 0 + .dw 0x4240, 0xc81c, 0x427f, 0xc81c, 0x21, 0 + .dw 0x42c0, 0xc81c, 0x42ff, 0xc81c, 0x21, 0 + .dw 0x4340, 0xc81c, 0x437f, 0xc81c, 0x21, 0 + .dw 0x43c0, 0xc81c, 0x43ff, 0xc81c, 0x21, 0 + .dw 0x4440, 0xc81c, 0x447f, 0xc81c, 0x21, 0 + .dw 0x44c0, 0xc81c, 0x44ff, 0xc81c, 0x21, 0 + .dw 0x4540, 0xc81c, 0x457f, 0xc81c, 0x21, 0 + .dw 0x45c0, 0xc81c, 0x45ff, 0xc81c, 0x21, 0 + .dw 0x4640, 0xc81c, 0x467f, 0xc81c, 0x21, 0 + .dw 0x46c0, 0xc81c, 0x46ff, 0xc81c, 0x21, 0 + .dw 0x4740, 0xc81c, 0x477f, 0xc81c, 0x21, 0 + .dw 0x47c0, 0xc81c, 0x47ff, 0xc81c, 0x21, 0 + .dw 0x4840, 0xc81c, 0x487f, 0xc81c, 0x21, 0 + .dw 0x48c0, 0xc81c, 0x48ff, 0xc81c, 0x21, 0 + .dw 0x4940, 0xc81c, 0x497f, 0xc81c, 0x21, 0 + .dw 0x49c0, 0xc81c, 0x49ff, 0xc81c, 0x21, 0 + .dw 0x4a40, 0xc81c, 0x4a7f, 0xc81c, 0x21, 0 + .dw 0x4ac0, 0xc81c, 0x4aff, 0xc81c, 0x21, 0 + .dw 0x4b40, 0xc81c, 0x4b7f, 0xc81c, 0x21, 0 + .dw 0x4bc0, 0xc81c, 0x4bff, 0xc81c, 0x21, 0 + .dw 0x4c40, 0xc81c, 0x4c7f, 0xc81c, 0x21, 0 + .dw 0x4cc0, 0xc81c, 0x4cff, 0xc81c, 0x21, 0 + .dw 0x4d40, 0xc81c, 0x4d7f, 0xc81c, 0x21, 0 + .dw 0x4dc0, 0xc81c, 0x4dff, 0xc81c, 0x21, 0 + .dw 0x4e40, 0xc81c, 0x4e7f, 0xc81c, 0x21, 0 + .dw 0x4ec0, 0xc81c, 0x4eff, 0xc81c, 0x21, 0 + .dw 0x4f40, 0xc81c, 0x4f7f, 0xc81c, 0x21, 0 + .dw 0x4fc0, 0xc81c, 0x4fff, 0xc81c, 0x21, 0 + .dw 0x5040, 0xc81c, 0x507f, 0xc81c, 0x21, 0 + .dw 0x50c0, 0xc81c, 0x50ff, 0xc81c, 0x21, 0 + .dw 0x5140, 0xc81c, 0x517f, 0xc81c, 0x21, 0 + .dw 0x51c0, 0xc81c, 0x51ff, 0xc81c, 0x21, 0 + .dw 0x5240, 0xc81c, 0x527f, 0xc81c, 0x21, 0 + .dw 0x52c0, 0xc81c, 0x52ff, 0xc81c, 0x21, 0 + .dw 0x5340, 0xc81c, 0x537f, 0xc81c, 0x21, 0 + .dw 0x53c0, 0xc81c, 0x53ff, 0xc81c, 0x21, 0 + .dw 0x5440, 0xc81c, 0x547f, 0xc81c, 0x21, 0 + .dw 0x54c0, 0xc81c, 0x54ff, 0xc81c, 0x21, 0 + .dw 0x5540, 0xc81c, 0x557f, 0xc81c, 0x21, 0 + .dw 0x55c0, 0xc81c, 0x55ff, 0xc81c, 0x21, 0 + .dw 0x5640, 0xc81c, 0x567f, 0xc81c, 0x21, 0 + .dw 0x56c0, 0xc81c, 0x56ff, 0xc81c, 0x21, 0 + .dw 0x5740, 0xc81c, 0x577f, 0xc81c, 0x21, 0 + .dw 0x57c0, 0xc81c, 0x57ff, 0xc81c, 0x21, 0 + .dw 0x5840, 0xc81c, 0x587f, 0xc81c, 0x21, 0 + .dw 0x58c0, 0xc81c, 0x58ff, 0xc81c, 0x21, 0 + .dw 0x5940, 0xc81c, 0x597f, 0xc81c, 0x21, 0 + .dw 0x59c0, 0xc81c, 0x5fff, 0xc81c, 0x21, 0 + .dw 0x6040, 0xc81c, 0x607f, 0xc81c, 0x21, 0 + .dw 0x60c0, 0xc81c, 0x60ff, 0xc81c, 0x21, 0 + .dw 0x6140, 0xc81c, 0x617f, 0xc81c, 0x21, 0 + .dw 0x61c0, 0xc81c, 0x61ff, 0xc81c, 0x21, 0 + .dw 0x6240, 0xc81c, 0x627f, 0xc81c, 0x21, 0 + .dw 0x62c0, 0xc81c, 0x62ff, 0xc81c, 0x21, 0 + .dw 0x6340, 0xc81c, 0x637f, 0xc81c, 0x21, 0 + .dw 0x63c0, 0xc81c, 0x63ff, 0xc81c, 0x21, 0 + .dw 0x6440, 0xc81c, 0x647f, 0xc81c, 0x21, 0 + .dw 0x64c0, 0xc81c, 0x64ff, 0xc81c, 0x21, 0 + .dw 0x6540, 0xc81c, 0x657f, 0xc81c, 0x21, 0 + .dw 0x65c0, 0xc81c, 0x65ff, 0xc81c, 0x21, 0 + .dw 0x6640, 0xc81c, 0x667f, 0xc81c, 0x21, 0 + .dw 0x66c0, 0xc81c, 0x66ff, 0xc81c, 0x21, 0 + .dw 0x6740, 0xc81c, 0x677f, 0xc81c, 0x21, 0 + .dw 0x67c0, 0xc81c, 0x67ff, 0xc81c, 0x21, 0 + .dw 0x6840, 0xc81c, 0x687f, 0xc81c, 0x21, 0 + .dw 0x68c0, 0xc81c, 0x68ff, 0xc81c, 0x21, 0 + .dw 0x6940, 0xc81c, 0x697f, 0xc81c, 0x21, 0 + .dw 0x69c0, 0xc81c, 0x69ff, 0xc81c, 0x21, 0 + .dw 0x6a40, 0xc81c, 0x6a7f, 0xc81c, 0x21, 0 + .dw 0x6ac0, 0xc81c, 0x6aff, 0xc81c, 0x21, 0 + .dw 0x6b40, 0xc81c, 0x6b7f, 0xc81c, 0x21, 0 + .dw 0x6bc0, 0xc81c, 0x6bff, 0xc81c, 0x21, 0 + .dw 0x6c40, 0xc81c, 0x6c7f, 0xc81c, 0x21, 0 + .dw 0x6cc0, 0xc81c, 0x6cff, 0xc81c, 0x21, 0 + .dw 0x6d40, 0xc81c, 0x6d7f, 0xc81c, 0x21, 0 + .dw 0x6dc0, 0xc81c, 0x6dff, 0xc81c, 0x21, 0 + .dw 0x6e40, 0xc81c, 0x6e7f, 0xc81c, 0x21, 0 + .dw 0x6ec0, 0xc81c, 0x6eff, 0xc81c, 0x21, 0 + .dw 0x6f40, 0xc81c, 0x6f7f, 0xc81c, 0x21, 0 + .dw 0x6fc0, 0xc81c, 0x6fff, 0xc81c, 0x21, 0 + .dw 0x7040, 0xc81c, 0x707f, 0xc81c, 0x21, 0 + .dw 0x70c0, 0xc81c, 0x70ff, 0xc81c, 0x21, 0 + .dw 0x7140, 0xc81c, 0x717f, 0xc81c, 0x21, 0 + .dw 0x71c0, 0xc81c, 0x71ff, 0xc81c, 0x21, 0 + .dw 0x7240, 0xc81c, 0x727f, 0xc81c, 0x21, 0 + .dw 0x72c0, 0xc81c, 0x72ff, 0xc81c, 0x21, 0 + .dw 0x7340, 0xc81c, 0x737f, 0xc81c, 0x21, 0 + .dw 0x73c0, 0xc81c, 0x73ff, 0xc81c, 0x21, 0 + .dw 0x7440, 0xc81c, 0x747f, 0xc81c, 0x21, 0 + .dw 0x74c0, 0xc81c, 0x74ff, 0xc81c, 0x21, 0 + .dw 0x7540, 0xc81c, 0x757f, 0xc81c, 0x21, 0 + .dw 0x75c0, 0xc81c, 0x75ff, 0xc81c, 0x21, 0 + .dw 0x7640, 0xc81c, 0x767f, 0xc81c, 0x21, 0 + .dw 0x76c0, 0xc81c, 0x76ff, 0xc81c, 0x21, 0 + .dw 0x7740, 0xc81c, 0x777f, 0xc81c, 0x21, 0 + .dw 0x77c0, 0xc81c, 0x77ff, 0xc81c, 0x21, 0 + .dw 0x7840, 0xc81c, 0x787f, 0xc81c, 0x21, 0 + .dw 0x78c0, 0xc81c, 0x78ff, 0xc81c, 0x21, 0 + .dw 0x7940, 0xc81c, 0x797f, 0xc81c, 0x21, 0 + .dw 0x79c0, 0xc81c, 0x7fff, 0xc81c, 0x21, 0 + .dw 0x8040, 0xc81c, 0x807f, 0xc81c, 0x21, 0 + .dw 0x80c0, 0xc81c, 0x80ff, 0xc81c, 0x21, 0 + .dw 0x8140, 0xc81c, 0x817f, 0xc81c, 0x21, 0 + .dw 0x81c0, 0xc81c, 0x81ff, 0xc81c, 0x21, 0 + .dw 0x8240, 0xc81c, 0x827f, 0xc81c, 0x21, 0 + .dw 0x82c0, 0xc81c, 0x82ff, 0xc81c, 0x21, 0 + .dw 0x8340, 0xc81c, 0x837f, 0xc81c, 0x21, 0 + .dw 0x83c0, 0xc81c, 0x83ff, 0xc81c, 0x21, 0 + .dw 0x8440, 0xc81c, 0x847f, 0xc81c, 0x21, 0 + .dw 0x84c0, 0xc81c, 0x84ff, 0xc81c, 0x21, 0 + .dw 0x8540, 0xc81c, 0x857f, 0xc81c, 0x21, 0 + .dw 0x85c0, 0xc81c, 0x85ff, 0xc81c, 0x21, 0 + .dw 0x8640, 0xc81c, 0x867f, 0xc81c, 0x21, 0 + .dw 0x86c0, 0xc81c, 0x86ff, 0xc81c, 0x21, 0 + .dw 0x8740, 0xc81c, 0x877f, 0xc81c, 0x21, 0 + .dw 0x87c0, 0xc81c, 0x87ff, 0xc81c, 0x21, 0 + .dw 0x8840, 0xc81c, 0x887f, 0xc81c, 0x21, 0 + .dw 0x88c0, 0xc81c, 0x88ff, 0xc81c, 0x21, 0 + .dw 0x8940, 0xc81c, 0x897f, 0xc81c, 0x21, 0 + .dw 0x89c0, 0xc81c, 0x89ff, 0xc81c, 0x21, 0 + .dw 0x8a40, 0xc81c, 0x8a7f, 0xc81c, 0x21, 0 + .dw 0x8ac0, 0xc81c, 0x8aff, 0xc81c, 0x21, 0 + .dw 0x8b40, 0xc81c, 0x8b7f, 0xc81c, 0x21, 0 + .dw 0x8bc0, 0xc81c, 0x8bff, 0xc81c, 0x21, 0 + .dw 0x8c40, 0xc81c, 0x8c7f, 0xc81c, 0x21, 0 + .dw 0x8cc0, 0xc81c, 0x8cff, 0xc81c, 0x21, 0 + .dw 0x8d40, 0xc81c, 0x8d7f, 0xc81c, 0x21, 0 + .dw 0x8dc0, 0xc81c, 0x8dff, 0xc81c, 0x21, 0 + .dw 0x8e40, 0xc81c, 0x8e7f, 0xc81c, 0x21, 0 + .dw 0x8ec0, 0xc81c, 0x8eff, 0xc81c, 0x21, 0 + .dw 0x8f40, 0xc81c, 0x8f7f, 0xc81c, 0x21, 0 + .dw 0x8fc0, 0xc81c, 0x8fff, 0xc81c, 0x21, 0 + .dw 0x9040, 0xc81c, 0x907f, 0xc81c, 0x21, 0 + .dw 0x90c0, 0xc81c, 0x90ff, 0xc81c, 0x21, 0 + .dw 0x9140, 0xc81c, 0x917f, 0xc81c, 0x21, 0 + .dw 0x91c0, 0xc81c, 0x91ff, 0xc81c, 0x21, 0 + .dw 0x9240, 0xc81c, 0x927f, 0xc81c, 0x21, 0 + .dw 0x92c0, 0xc81c, 0x92ff, 0xc81c, 0x21, 0 + .dw 0x9340, 0xc81c, 0x937f, 0xc81c, 0x21, 0 + .dw 0x93c0, 0xc81c, 0x93ff, 0xc81c, 0x21, 0 + .dw 0x9440, 0xc81c, 0x947f, 0xc81c, 0x21, 0 + .dw 0x94c0, 0xc81c, 0x94ff, 0xc81c, 0x21, 0 + .dw 0x9540, 0xc81c, 0x957f, 0xc81c, 0x21, 0 + .dw 0x95c0, 0xc81c, 0x95ff, 0xc81c, 0x21, 0 + .dw 0x9640, 0xc81c, 0x967f, 0xc81c, 0x21, 0 + .dw 0x96c0, 0xc81c, 0x96ff, 0xc81c, 0x21, 0 + .dw 0x9740, 0xc81c, 0x977f, 0xc81c, 0x21, 0 + .dw 0x97c0, 0xc81c, 0x97ff, 0xc81c, 0x21, 0 + .dw 0x9840, 0xc81c, 0x987f, 0xc81c, 0x21, 0 + .dw 0x98c0, 0xc81c, 0x98ff, 0xc81c, 0x21, 0 + .dw 0x9940, 0xc81c, 0x997f, 0xc81c, 0x21, 0 + .dw 0x99c0, 0xc81c, 0x9fff, 0xc81c, 0x21, 0 + .dw 0xa040, 0xc81c, 0xa07f, 0xc81c, 0x21, 0 + .dw 0xa0c0, 0xc81c, 0xa0ff, 0xc81c, 0x21, 0 + .dw 0xa140, 0xc81c, 0xa17f, 0xc81c, 0x21, 0 + .dw 0xa1c0, 0xc81c, 0xa1ff, 0xc81c, 0x21, 0 + .dw 0xa240, 0xc81c, 0xa27f, 0xc81c, 0x21, 0 + .dw 0xa2c0, 0xc81c, 0xa2ff, 0xc81c, 0x21, 0 + .dw 0xa340, 0xc81c, 0xa37f, 0xc81c, 0x21, 0 + .dw 0xa3c0, 0xc81c, 0xa3ff, 0xc81c, 0x21, 0 + .dw 0xa440, 0xc81c, 0xa47f, 0xc81c, 0x21, 0 + .dw 0xa4c0, 0xc81c, 0xa4ff, 0xc81c, 0x21, 0 + .dw 0xa540, 0xc81c, 0xa57f, 0xc81c, 0x21, 0 + .dw 0xa5c0, 0xc81c, 0xa5ff, 0xc81c, 0x21, 0 + .dw 0xa640, 0xc81c, 0xa67f, 0xc81c, 0x21, 0 + .dw 0xa6c0, 0xc81c, 0xa6ff, 0xc81c, 0x21, 0 + .dw 0xa740, 0xc81c, 0xa77f, 0xc81c, 0x21, 0 + .dw 0xa7c0, 0xc81c, 0xa7ff, 0xc81c, 0x21, 0 + .dw 0xa840, 0xc81c, 0xa87f, 0xc81c, 0x21, 0 + .dw 0xa8c0, 0xc81c, 0xa8ff, 0xc81c, 0x21, 0 + .dw 0xa940, 0xc81c, 0xa97f, 0xc81c, 0x21, 0 + .dw 0xa9c0, 0xc81c, 0xa9ff, 0xc81c, 0x21, 0 + .dw 0xaa40, 0xc81c, 0xaa7f, 0xc81c, 0x21, 0 + .dw 0xaac0, 0xc81c, 0xaaff, 0xc81c, 0x21, 0 + .dw 0xab40, 0xc81c, 0xab7f, 0xc81c, 0x21, 0 + .dw 0xabc0, 0xc81c, 0xabff, 0xc81c, 0x21, 0 + .dw 0xac40, 0xc81c, 0xac7f, 0xc81c, 0x21, 0 + .dw 0xacc0, 0xc81c, 0xacff, 0xc81c, 0x21, 0 + .dw 0xad40, 0xc81c, 0xad7f, 0xc81c, 0x21, 0 + .dw 0xadc0, 0xc81c, 0xadff, 0xc81c, 0x21, 0 + .dw 0xae40, 0xc81c, 0xae7f, 0xc81c, 0x21, 0 + .dw 0xaec0, 0xc81c, 0xaeff, 0xc81c, 0x21, 0 + .dw 0xaf40, 0xc81c, 0xaf7f, 0xc81c, 0x21, 0 + .dw 0xafc0, 0xc81c, 0xafff, 0xc81c, 0x21, 0 + .dw 0xb040, 0xc81c, 0xb07f, 0xc81c, 0x21, 0 + .dw 0xb0c0, 0xc81c, 0xb0ff, 0xc81c, 0x21, 0 + .dw 0xb140, 0xc81c, 0xb17f, 0xc81c, 0x21, 0 + .dw 0xb1c0, 0xc81c, 0xb1ff, 0xc81c, 0x21, 0 + .dw 0xb240, 0xc81c, 0xb27f, 0xc81c, 0x21, 0 + .dw 0xb2c0, 0xc81c, 0xb2ff, 0xc81c, 0x21, 0 + .dw 0xb340, 0xc81c, 0xb37f, 0xc81c, 0x21, 0 + .dw 0xb3c0, 0xc81c, 0xb3ff, 0xc81c, 0x21, 0 + .dw 0xb440, 0xc81c, 0xb47f, 0xc81c, 0x21, 0 + .dw 0xb4c0, 0xc81c, 0xb4ff, 0xc81c, 0x21, 0 + .dw 0xb540, 0xc81c, 0xb57f, 0xc81c, 0x21, 0 + .dw 0xb5c0, 0xc81c, 0xb5ff, 0xc81c, 0x21, 0 + .dw 0xb640, 0xc81c, 0xb67f, 0xc81c, 0x21, 0 + .dw 0xb6c0, 0xc81c, 0xb6ff, 0xc81c, 0x21, 0 + .dw 0xb740, 0xc81c, 0xb77f, 0xc81c, 0x21, 0 + .dw 0xb7c0, 0xc81c, 0xb7ff, 0xc81c, 0x21, 0 + .dw 0xb840, 0xc81c, 0xb87f, 0xc81c, 0x21, 0 + .dw 0xb8c0, 0xc81c, 0xb8ff, 0xc81c, 0x21, 0 + .dw 0xb940, 0xc81c, 0xb97f, 0xc81c, 0x21, 0 + .dw 0xb9c0, 0xc81c, 0xbfff, 0xc81c, 0x21, 0 + .dw 0xc040, 0xc81c, 0xc07f, 0xc81c, 0x21, 0 + .dw 0xc0c0, 0xc81c, 0xc0ff, 0xc81c, 0x21, 0 + .dw 0xc140, 0xc81c, 0xc17f, 0xc81c, 0x21, 0 + .dw 0xc1c0, 0xc81c, 0xc1ff, 0xc81c, 0x21, 0 + .dw 0xc240, 0xc81c, 0xc27f, 0xc81c, 0x21, 0 + .dw 0xc2c0, 0xc81c, 0xc2ff, 0xc81c, 0x21, 0 + .dw 0xc340, 0xc81c, 0xc37f, 0xc81c, 0x21, 0 + .dw 0xc3c0, 0xc81c, 0xc3ff, 0xc81c, 0x21, 0 + .dw 0xc440, 0xc81c, 0xc47f, 0xc81c, 0x21, 0 + .dw 0xc4c0, 0xc81c, 0xc4ff, 0xc81c, 0x21, 0 + .dw 0xc540, 0xc81c, 0xc57f, 0xc81c, 0x21, 0 + .dw 0xc5c0, 0xc81c, 0xc5ff, 0xc81c, 0x21, 0 + .dw 0xc640, 0xc81c, 0xc67f, 0xc81c, 0x21, 0 + .dw 0xc6c0, 0xc81c, 0xc6ff, 0xc81c, 0x21, 0 + .dw 0xc740, 0xc81c, 0xc77f, 0xc81c, 0x21, 0 + .dw 0xc7c0, 0xc81c, 0xc7ff, 0xc81c, 0x21, 0 + .dw 0xc840, 0xc81c, 0xc87f, 0xc81c, 0x21, 0 + .dw 0xc8c0, 0xc81c, 0xc8ff, 0xc81c, 0x21, 0 + .dw 0xc940, 0xc81c, 0xc97f, 0xc81c, 0x21, 0 + .dw 0xc9c0, 0xc81c, 0xc9ff, 0xc81c, 0x21, 0 + .dw 0xca40, 0xc81c, 0xca7f, 0xc81c, 0x21, 0 + .dw 0xcac0, 0xc81c, 0xcaff, 0xc81c, 0x21, 0 + .dw 0xcb40, 0xc81c, 0xcb7f, 0xc81c, 0x21, 0 + .dw 0xcbc0, 0xc81c, 0xcbff, 0xc81c, 0x21, 0 + .dw 0xcc40, 0xc81c, 0xcc7f, 0xc81c, 0x21, 0 + .dw 0xccc0, 0xc81c, 0xccff, 0xc81c, 0x21, 0 + .dw 0xcd40, 0xc81c, 0xcd7f, 0xc81c, 0x21, 0 + .dw 0xcdc0, 0xc81c, 0xcdff, 0xc81c, 0x21, 0 + .dw 0xce40, 0xc81c, 0xce7f, 0xc81c, 0x21, 0 + .dw 0xcec0, 0xc81c, 0xceff, 0xc81c, 0x21, 0 + .dw 0xcf40, 0xc81c, 0xcf7f, 0xc81c, 0x21, 0 + .dw 0xcfc0, 0xc81c, 0xcfff, 0xc81c, 0x21, 0 + .dw 0xd040, 0xc81c, 0xd07f, 0xc81c, 0x21, 0 + .dw 0xd0c0, 0xc81c, 0xd0ff, 0xc81c, 0x21, 0 + .dw 0xd140, 0xc81c, 0xd17f, 0xc81c, 0x21, 0 + .dw 0xd1c0, 0xc81c, 0xd1ff, 0xc81c, 0x21, 0 + .dw 0xd240, 0xc81c, 0xd27f, 0xc81c, 0x21, 0 + .dw 0xd2c0, 0xc81c, 0xd2ff, 0xc81c, 0x21, 0 + .dw 0xd340, 0xc81c, 0xd37f, 0xc81c, 0x21, 0 + .dw 0xd3c0, 0xc81c, 0xd3ff, 0xc81c, 0x21, 0 + .dw 0xd440, 0xc81c, 0xd47f, 0xc81c, 0x21, 0 + .dw 0xd4c0, 0xc81c, 0xd4ff, 0xc81c, 0x21, 0 + .dw 0xd540, 0xc81c, 0xd57f, 0xc81c, 0x21, 0 + .dw 0xd5c0, 0xc81c, 0xd5ff, 0xc81c, 0x21, 0 + .dw 0xd640, 0xc81c, 0xd67f, 0xc81c, 0x21, 0 + .dw 0xd6c0, 0xc81c, 0xd6ff, 0xc81c, 0x21, 0 + .dw 0xd740, 0xc81c, 0xd77f, 0xc81c, 0x21, 0 + .dw 0xd7c0, 0xc81c, 0xd7ff, 0xc81c, 0x21, 0 + .dw 0xd840, 0xc81c, 0xd87f, 0xc81c, 0x21, 0 + .dw 0xd8c0, 0xc81c, 0xd8ff, 0xc81c, 0x21, 0 + .dw 0xd940, 0xc81c, 0xd97f, 0xc81c, 0x21, 0 + .dw 0xd9c0, 0xc81c, 0xdfff, 0xc81c, 0x21, 0 + .dw 0xe040, 0xc81c, 0xe07f, 0xc81c, 0x21, 0 + .dw 0xe0c0, 0xc81c, 0xe0ff, 0xc81c, 0x21, 0 + .dw 0xe140, 0xc81c, 0xe17f, 0xc81c, 0x21, 0 + .dw 0xe1c0, 0xc81c, 0xe1ff, 0xc81c, 0x21, 0 + .dw 0xe240, 0xc81c, 0xe27f, 0xc81c, 0x21, 0 + .dw 0xe2c0, 0xc81c, 0xe2ff, 0xc81c, 0x21, 0 + .dw 0xe340, 0xc81c, 0xe37f, 0xc81c, 0x21, 0 + .dw 0xe3c0, 0xc81c, 0xe3ff, 0xc81c, 0x21, 0 + .dw 0xe440, 0xc81c, 0xe47f, 0xc81c, 0x21, 0 + .dw 0xe4c0, 0xc81c, 0xe4ff, 0xc81c, 0x21, 0 + .dw 0xe540, 0xc81c, 0xe57f, 0xc81c, 0x21, 0 + .dw 0xe5c0, 0xc81c, 0xe5ff, 0xc81c, 0x21, 0 + .dw 0xe640, 0xc81c, 0xe67f, 0xc81c, 0x21, 0 + .dw 0xe6c0, 0xc81c, 0xe6ff, 0xc81c, 0x21, 0 + .dw 0xe740, 0xc81c, 0xe77f, 0xc81c, 0x21, 0 + .dw 0xe7c0, 0xc81c, 0xe7ff, 0xc81c, 0x21, 0 + .dw 0xe840, 0xc81c, 0xe87f, 0xc81c, 0x21, 0 + .dw 0xe8c0, 0xc81c, 0xe8ff, 0xc81c, 0x21, 0 + .dw 0xe940, 0xc81c, 0xe97f, 0xc81c, 0x21, 0 + .dw 0xe9c0, 0xc81c, 0xe9ff, 0xc81c, 0x21, 0 + .dw 0xea40, 0xc81c, 0xea7f, 0xc81c, 0x21, 0 + .dw 0xeac0, 0xc81c, 0xeaff, 0xc81c, 0x21, 0 + .dw 0xeb40, 0xc81c, 0xeb7f, 0xc81c, 0x21, 0 + .dw 0xebc0, 0xc81c, 0xebff, 0xc81c, 0x21, 0 + .dw 0xec40, 0xc81c, 0xec7f, 0xc81c, 0x21, 0 + .dw 0xecc0, 0xc81c, 0xecff, 0xc81c, 0x21, 0 + .dw 0xed40, 0xc81c, 0xed7f, 0xc81c, 0x21, 0 + .dw 0xedc0, 0xc81c, 0xedff, 0xc81c, 0x21, 0 + .dw 0xee40, 0xc81c, 0xee7f, 0xc81c, 0x21, 0 + .dw 0xeec0, 0xc81c, 0xeeff, 0xc81c, 0x21, 0 + .dw 0xef40, 0xc81c, 0xef7f, 0xc81c, 0x21, 0 + .dw 0xefc0, 0xc81c, 0xefff, 0xc81c, 0x21, 0 + .dw 0xf040, 0xc81c, 0xf07f, 0xc81c, 0x21, 0 + .dw 0xf0c0, 0xc81c, 0xf0ff, 0xc81c, 0x21, 0 + .dw 0xf140, 0xc81c, 0xf17f, 0xc81c, 0x21, 0 + .dw 0xf1c0, 0xc81c, 0xf1ff, 0xc81c, 0x21, 0 + .dw 0xf240, 0xc81c, 0xf27f, 0xc81c, 0x21, 0 + .dw 0xf2c0, 0xc81c, 0xf2ff, 0xc81c, 0x21, 0 + .dw 0xf340, 0xc81c, 0xf37f, 0xc81c, 0x21, 0 + .dw 0xf3c0, 0xc81c, 0xf3ff, 0xc81c, 0x21, 0 + .dw 0xf440, 0xc81c, 0xf47f, 0xc81c, 0x21, 0 + .dw 0xf4c0, 0xc81c, 0xf4ff, 0xc81c, 0x21, 0 + .dw 0xf540, 0xc81c, 0xf57f, 0xc81c, 0x21, 0 + .dw 0xf5c0, 0xc81c, 0xf5ff, 0xc81c, 0x21, 0 + .dw 0xf640, 0xc81c, 0xf67f, 0xc81c, 0x21, 0 + .dw 0xf6c0, 0xc81c, 0xf6ff, 0xc81c, 0x21, 0 + .dw 0xf740, 0xc81c, 0xf77f, 0xc81c, 0x21, 0 + .dw 0xf7c0, 0xc81c, 0xf7ff, 0xc81c, 0x21, 0 + .dw 0xf840, 0xc81c, 0xf87f, 0xc81c, 0x21, 0 + .dw 0xf8c0, 0xc81c, 0xf8ff, 0xc81c, 0x21, 0 + .dw 0xf940, 0xc81c, 0xf97f, 0xc81c, 0x21, 0 + .dw 0xf9c0, 0xc81c, 0xffff, 0xc81c, 0x21, 0 + .dw 0x0040, 0xc81d, 0x007f, 0xc81d, 0x21, 0 + .dw 0x00c0, 0xc81d, 0x00ff, 0xc81d, 0x21, 0 + .dw 0x0140, 0xc81d, 0x017f, 0xc81d, 0x21, 0 + .dw 0x01c0, 0xc81d, 0x01ff, 0xc81d, 0x21, 0 + .dw 0x0240, 0xc81d, 0x027f, 0xc81d, 0x21, 0 + .dw 0x02c0, 0xc81d, 0x02ff, 0xc81d, 0x21, 0 + .dw 0x0340, 0xc81d, 0x037f, 0xc81d, 0x21, 0 + .dw 0x03c0, 0xc81d, 0x03ff, 0xc81d, 0x21, 0 + .dw 0x0440, 0xc81d, 0x047f, 0xc81d, 0x21, 0 + .dw 0x04c0, 0xc81d, 0x04ff, 0xc81d, 0x21, 0 + .dw 0x0540, 0xc81d, 0x057f, 0xc81d, 0x21, 0 + .dw 0x05c0, 0xc81d, 0x05ff, 0xc81d, 0x21, 0 + .dw 0x0640, 0xc81d, 0x067f, 0xc81d, 0x21, 0 + .dw 0x06c0, 0xc81d, 0x06ff, 0xc81d, 0x21, 0 + .dw 0x0740, 0xc81d, 0x077f, 0xc81d, 0x21, 0 + .dw 0x07c0, 0xc81d, 0x07ff, 0xc81d, 0x21, 0 + .dw 0x0840, 0xc81d, 0x087f, 0xc81d, 0x21, 0 + .dw 0x08c0, 0xc81d, 0x08ff, 0xc81d, 0x21, 0 + .dw 0x0940, 0xc81d, 0x097f, 0xc81d, 0x21, 0 + .dw 0x09c0, 0xc81d, 0x09ff, 0xc81d, 0x21, 0 + .dw 0x0a40, 0xc81d, 0x0a7f, 0xc81d, 0x21, 0 + .dw 0x0ac0, 0xc81d, 0x0aff, 0xc81d, 0x21, 0 + .dw 0x0b40, 0xc81d, 0x0b7f, 0xc81d, 0x21, 0 + .dw 0x0bc0, 0xc81d, 0x0bff, 0xc81d, 0x21, 0 + .dw 0x0c40, 0xc81d, 0x0c7f, 0xc81d, 0x21, 0 + .dw 0x0cc0, 0xc81d, 0x0cff, 0xc81d, 0x21, 0 + .dw 0x0d40, 0xc81d, 0x0d7f, 0xc81d, 0x21, 0 + .dw 0x0dc0, 0xc81d, 0x0dff, 0xc81d, 0x21, 0 + .dw 0x0e40, 0xc81d, 0x0e7f, 0xc81d, 0x21, 0 + .dw 0x0ec0, 0xc81d, 0x0eff, 0xc81d, 0x21, 0 + .dw 0x0f40, 0xc81d, 0x0f7f, 0xc81d, 0x21, 0 + .dw 0x0fc0, 0xc81d, 0x0fff, 0xc81d, 0x21, 0 + .dw 0x1040, 0xc81d, 0x107f, 0xc81d, 0x21, 0 + .dw 0x10c0, 0xc81d, 0x10ff, 0xc81d, 0x21, 0 + .dw 0x1140, 0xc81d, 0x117f, 0xc81d, 0x21, 0 + .dw 0x11c0, 0xc81d, 0x11ff, 0xc81d, 0x21, 0 + .dw 0x1240, 0xc81d, 0x127f, 0xc81d, 0x21, 0 + .dw 0x12c0, 0xc81d, 0x12ff, 0xc81d, 0x21, 0 + .dw 0x1340, 0xc81d, 0x137f, 0xc81d, 0x21, 0 + .dw 0x13c0, 0xc81d, 0x13ff, 0xc81d, 0x21, 0 + .dw 0x1440, 0xc81d, 0x147f, 0xc81d, 0x21, 0 + .dw 0x14c0, 0xc81d, 0x14ff, 0xc81d, 0x21, 0 + .dw 0x1540, 0xc81d, 0x157f, 0xc81d, 0x21, 0 + .dw 0x15c0, 0xc81d, 0x15ff, 0xc81d, 0x21, 0 + .dw 0x1640, 0xc81d, 0x167f, 0xc81d, 0x21, 0 + .dw 0x16c0, 0xc81d, 0x16ff, 0xc81d, 0x21, 0 + .dw 0x1740, 0xc81d, 0x177f, 0xc81d, 0x21, 0 + .dw 0x17c0, 0xc81d, 0x17ff, 0xc81d, 0x21, 0 + .dw 0x1840, 0xc81d, 0x187f, 0xc81d, 0x21, 0 + .dw 0x18c0, 0xc81d, 0x18ff, 0xc81d, 0x21, 0 + .dw 0x1940, 0xc81d, 0x197f, 0xc81d, 0x21, 0 + .dw 0x19c0, 0xc81d, 0x1fff, 0xc81d, 0x21, 0 + .dw 0x2040, 0xc81d, 0x207f, 0xc81d, 0x21, 0 + .dw 0x20c0, 0xc81d, 0x20ff, 0xc81d, 0x21, 0 + .dw 0x2140, 0xc81d, 0x217f, 0xc81d, 0x21, 0 + .dw 0x21c0, 0xc81d, 0x21ff, 0xc81d, 0x21, 0 + .dw 0x2240, 0xc81d, 0x227f, 0xc81d, 0x21, 0 + .dw 0x22c0, 0xc81d, 0x22ff, 0xc81d, 0x21, 0 + .dw 0x2340, 0xc81d, 0x237f, 0xc81d, 0x21, 0 + .dw 0x23c0, 0xc81d, 0x23ff, 0xc81d, 0x21, 0 + .dw 0x2440, 0xc81d, 0x247f, 0xc81d, 0x21, 0 + .dw 0x24c0, 0xc81d, 0x24ff, 0xc81d, 0x21, 0 + .dw 0x2540, 0xc81d, 0x257f, 0xc81d, 0x21, 0 + .dw 0x25c0, 0xc81d, 0x25ff, 0xc81d, 0x21, 0 + .dw 0x2640, 0xc81d, 0x267f, 0xc81d, 0x21, 0 + .dw 0x26c0, 0xc81d, 0x26ff, 0xc81d, 0x21, 0 + .dw 0x2740, 0xc81d, 0x277f, 0xc81d, 0x21, 0 + .dw 0x27c0, 0xc81d, 0x27ff, 0xc81d, 0x21, 0 + .dw 0x2840, 0xc81d, 0x287f, 0xc81d, 0x21, 0 + .dw 0x28c0, 0xc81d, 0x28ff, 0xc81d, 0x21, 0 + .dw 0x2940, 0xc81d, 0x297f, 0xc81d, 0x21, 0 + .dw 0x29c0, 0xc81d, 0x29ff, 0xc81d, 0x21, 0 + .dw 0x2a40, 0xc81d, 0x2a7f, 0xc81d, 0x21, 0 + .dw 0x2ac0, 0xc81d, 0x2aff, 0xc81d, 0x21, 0 + .dw 0x2b40, 0xc81d, 0x2b7f, 0xc81d, 0x21, 0 + .dw 0x2bc0, 0xc81d, 0x2bff, 0xc81d, 0x21, 0 + .dw 0x2c40, 0xc81d, 0x2c7f, 0xc81d, 0x21, 0 + .dw 0x2cc0, 0xc81d, 0x2cff, 0xc81d, 0x21, 0 + .dw 0x2d40, 0xc81d, 0x2d7f, 0xc81d, 0x21, 0 + .dw 0x2dc0, 0xc81d, 0x2dff, 0xc81d, 0x21, 0 + .dw 0x2e40, 0xc81d, 0x2e7f, 0xc81d, 0x21, 0 + .dw 0x2ec0, 0xc81d, 0x2eff, 0xc81d, 0x21, 0 + .dw 0x2f40, 0xc81d, 0x2f7f, 0xc81d, 0x21, 0 + .dw 0x2fc0, 0xc81d, 0x2fff, 0xc81d, 0x21, 0 + .dw 0x3040, 0xc81d, 0x307f, 0xc81d, 0x21, 0 + .dw 0x30c0, 0xc81d, 0x30ff, 0xc81d, 0x21, 0 + .dw 0x3140, 0xc81d, 0x317f, 0xc81d, 0x21, 0 + .dw 0x31c0, 0xc81d, 0x31ff, 0xc81d, 0x21, 0 + .dw 0x3240, 0xc81d, 0x327f, 0xc81d, 0x21, 0 + .dw 0x32c0, 0xc81d, 0x32ff, 0xc81d, 0x21, 0 + .dw 0x3340, 0xc81d, 0x337f, 0xc81d, 0x21, 0 + .dw 0x33c0, 0xc81d, 0x33ff, 0xc81d, 0x21, 0 + .dw 0x3440, 0xc81d, 0x347f, 0xc81d, 0x21, 0 + .dw 0x34c0, 0xc81d, 0x34ff, 0xc81d, 0x21, 0 + .dw 0x3540, 0xc81d, 0x357f, 0xc81d, 0x21, 0 + .dw 0x35c0, 0xc81d, 0x35ff, 0xc81d, 0x21, 0 + .dw 0x3640, 0xc81d, 0x367f, 0xc81d, 0x21, 0 + .dw 0x36c0, 0xc81d, 0x36ff, 0xc81d, 0x21, 0 + .dw 0x3740, 0xc81d, 0x377f, 0xc81d, 0x21, 0 + .dw 0x37c0, 0xc81d, 0x37ff, 0xc81d, 0x21, 0 + .dw 0x3840, 0xc81d, 0x387f, 0xc81d, 0x21, 0 + .dw 0x38c0, 0xc81d, 0x38ff, 0xc81d, 0x21, 0 + .dw 0x3940, 0xc81d, 0x397f, 0xc81d, 0x21, 0 + .dw 0x39c0, 0xc81d, 0x3fff, 0xc81d, 0x21, 0 + .dw 0x4040, 0xc81d, 0x407f, 0xc81d, 0x21, 0 + .dw 0x40c0, 0xc81d, 0x40ff, 0xc81d, 0x21, 0 + .dw 0x4140, 0xc81d, 0x417f, 0xc81d, 0x21, 0 + .dw 0x41c0, 0xc81d, 0x41ff, 0xc81d, 0x21, 0 + .dw 0x4240, 0xc81d, 0x427f, 0xc81d, 0x21, 0 + .dw 0x42c0, 0xc81d, 0x42ff, 0xc81d, 0x21, 0 + .dw 0x4340, 0xc81d, 0x437f, 0xc81d, 0x21, 0 + .dw 0x43c0, 0xc81d, 0x43ff, 0xc81d, 0x21, 0 + .dw 0x4440, 0xc81d, 0x447f, 0xc81d, 0x21, 0 + .dw 0x44c0, 0xc81d, 0x44ff, 0xc81d, 0x21, 0 + .dw 0x4540, 0xc81d, 0x457f, 0xc81d, 0x21, 0 + .dw 0x45c0, 0xc81d, 0x45ff, 0xc81d, 0x21, 0 + .dw 0x4640, 0xc81d, 0x467f, 0xc81d, 0x21, 0 + .dw 0x46c0, 0xc81d, 0x46ff, 0xc81d, 0x21, 0 + .dw 0x4740, 0xc81d, 0x477f, 0xc81d, 0x21, 0 + .dw 0x47c0, 0xc81d, 0x47ff, 0xc81d, 0x21, 0 + .dw 0x4840, 0xc81d, 0x487f, 0xc81d, 0x21, 0 + .dw 0x48c0, 0xc81d, 0x48ff, 0xc81d, 0x21, 0 + .dw 0x4940, 0xc81d, 0x497f, 0xc81d, 0x21, 0 + .dw 0x49c0, 0xc81d, 0x49ff, 0xc81d, 0x21, 0 + .dw 0x4a40, 0xc81d, 0x4a7f, 0xc81d, 0x21, 0 + .dw 0x4ac0, 0xc81d, 0x4aff, 0xc81d, 0x21, 0 + .dw 0x4b40, 0xc81d, 0x4b7f, 0xc81d, 0x21, 0 + .dw 0x4bc0, 0xc81d, 0x4bff, 0xc81d, 0x21, 0 + .dw 0x4c40, 0xc81d, 0x4c7f, 0xc81d, 0x21, 0 + .dw 0x4cc0, 0xc81d, 0x4cff, 0xc81d, 0x21, 0 + .dw 0x4d40, 0xc81d, 0x4d7f, 0xc81d, 0x21, 0 + .dw 0x4dc0, 0xc81d, 0x4dff, 0xc81d, 0x21, 0 + .dw 0x4e40, 0xc81d, 0x4e7f, 0xc81d, 0x21, 0 + .dw 0x4ec0, 0xc81d, 0x4eff, 0xc81d, 0x21, 0 + .dw 0x4f40, 0xc81d, 0x4f7f, 0xc81d, 0x21, 0 + .dw 0x4fc0, 0xc81d, 0x4fff, 0xc81d, 0x21, 0 + .dw 0x5040, 0xc81d, 0x507f, 0xc81d, 0x21, 0 + .dw 0x50c0, 0xc81d, 0x50ff, 0xc81d, 0x21, 0 + .dw 0x5140, 0xc81d, 0x517f, 0xc81d, 0x21, 0 + .dw 0x51c0, 0xc81d, 0x51ff, 0xc81d, 0x21, 0 + .dw 0x5240, 0xc81d, 0x527f, 0xc81d, 0x21, 0 + .dw 0x52c0, 0xc81d, 0x52ff, 0xc81d, 0x21, 0 + .dw 0x5340, 0xc81d, 0x537f, 0xc81d, 0x21, 0 + .dw 0x53c0, 0xc81d, 0x53ff, 0xc81d, 0x21, 0 + .dw 0x5440, 0xc81d, 0x547f, 0xc81d, 0x21, 0 + .dw 0x54c0, 0xc81d, 0x54ff, 0xc81d, 0x21, 0 + .dw 0x5540, 0xc81d, 0x557f, 0xc81d, 0x21, 0 + .dw 0x55c0, 0xc81d, 0x55ff, 0xc81d, 0x21, 0 + .dw 0x5640, 0xc81d, 0x567f, 0xc81d, 0x21, 0 + .dw 0x56c0, 0xc81d, 0x56ff, 0xc81d, 0x21, 0 + .dw 0x5740, 0xc81d, 0x577f, 0xc81d, 0x21, 0 + .dw 0x57c0, 0xc81d, 0x57ff, 0xc81d, 0x21, 0 + .dw 0x5840, 0xc81d, 0x587f, 0xc81d, 0x21, 0 + .dw 0x58c0, 0xc81d, 0x58ff, 0xc81d, 0x21, 0 + .dw 0x5940, 0xc81d, 0x597f, 0xc81d, 0x21, 0 + .dw 0x59c0, 0xc81d, 0x5fff, 0xc81d, 0x21, 0 + .dw 0x6040, 0xc81d, 0x607f, 0xc81d, 0x21, 0 + .dw 0x60c0, 0xc81d, 0x60ff, 0xc81d, 0x21, 0 + .dw 0x6140, 0xc81d, 0x617f, 0xc81d, 0x21, 0 + .dw 0x61c0, 0xc81d, 0x61ff, 0xc81d, 0x21, 0 + .dw 0x6240, 0xc81d, 0x627f, 0xc81d, 0x21, 0 + .dw 0x62c0, 0xc81d, 0x62ff, 0xc81d, 0x21, 0 + .dw 0x6340, 0xc81d, 0x637f, 0xc81d, 0x21, 0 + .dw 0x63c0, 0xc81d, 0x63ff, 0xc81d, 0x21, 0 + .dw 0x6440, 0xc81d, 0x647f, 0xc81d, 0x21, 0 + .dw 0x64c0, 0xc81d, 0x64ff, 0xc81d, 0x21, 0 + .dw 0x6540, 0xc81d, 0x657f, 0xc81d, 0x21, 0 + .dw 0x65c0, 0xc81d, 0x65ff, 0xc81d, 0x21, 0 + .dw 0x6640, 0xc81d, 0x667f, 0xc81d, 0x21, 0 + .dw 0x66c0, 0xc81d, 0x66ff, 0xc81d, 0x21, 0 + .dw 0x6740, 0xc81d, 0x677f, 0xc81d, 0x21, 0 + .dw 0x67c0, 0xc81d, 0x67ff, 0xc81d, 0x21, 0 + .dw 0x6840, 0xc81d, 0x687f, 0xc81d, 0x21, 0 + .dw 0x68c0, 0xc81d, 0x68ff, 0xc81d, 0x21, 0 + .dw 0x6940, 0xc81d, 0x697f, 0xc81d, 0x21, 0 + .dw 0x69c0, 0xc81d, 0x69ff, 0xc81d, 0x21, 0 + .dw 0x6a40, 0xc81d, 0x6a7f, 0xc81d, 0x21, 0 + .dw 0x6ac0, 0xc81d, 0x6aff, 0xc81d, 0x21, 0 + .dw 0x6b40, 0xc81d, 0x6b7f, 0xc81d, 0x21, 0 + .dw 0x6bc0, 0xc81d, 0x6bff, 0xc81d, 0x21, 0 + .dw 0x6c40, 0xc81d, 0x6c7f, 0xc81d, 0x21, 0 + .dw 0x6cc0, 0xc81d, 0x6cff, 0xc81d, 0x21, 0 + .dw 0x6d40, 0xc81d, 0x6d7f, 0xc81d, 0x21, 0 + .dw 0x6dc0, 0xc81d, 0x6dff, 0xc81d, 0x21, 0 + .dw 0x6e40, 0xc81d, 0x6e7f, 0xc81d, 0x21, 0 + .dw 0x6ec0, 0xc81d, 0x6eff, 0xc81d, 0x21, 0 + .dw 0x6f40, 0xc81d, 0x6f7f, 0xc81d, 0x21, 0 + .dw 0x6fc0, 0xc81d, 0x6fff, 0xc81d, 0x21, 0 + .dw 0x7040, 0xc81d, 0x707f, 0xc81d, 0x21, 0 + .dw 0x70c0, 0xc81d, 0x70ff, 0xc81d, 0x21, 0 + .dw 0x7140, 0xc81d, 0x717f, 0xc81d, 0x21, 0 + .dw 0x71c0, 0xc81d, 0x71ff, 0xc81d, 0x21, 0 + .dw 0x7240, 0xc81d, 0x727f, 0xc81d, 0x21, 0 + .dw 0x72c0, 0xc81d, 0x72ff, 0xc81d, 0x21, 0 + .dw 0x7340, 0xc81d, 0x737f, 0xc81d, 0x21, 0 + .dw 0x73c0, 0xc81d, 0x73ff, 0xc81d, 0x21, 0 + .dw 0x7440, 0xc81d, 0x747f, 0xc81d, 0x21, 0 + .dw 0x74c0, 0xc81d, 0x74ff, 0xc81d, 0x21, 0 + .dw 0x7540, 0xc81d, 0x757f, 0xc81d, 0x21, 0 + .dw 0x75c0, 0xc81d, 0x75ff, 0xc81d, 0x21, 0 + .dw 0x7640, 0xc81d, 0x767f, 0xc81d, 0x21, 0 + .dw 0x76c0, 0xc81d, 0x76ff, 0xc81d, 0x21, 0 + .dw 0x7740, 0xc81d, 0x777f, 0xc81d, 0x21, 0 + .dw 0x77c0, 0xc81d, 0x77ff, 0xc81d, 0x21, 0 + .dw 0x7840, 0xc81d, 0x787f, 0xc81d, 0x21, 0 + .dw 0x78c0, 0xc81d, 0x78ff, 0xc81d, 0x21, 0 + .dw 0x7940, 0xc81d, 0x797f, 0xc81d, 0x21, 0 + .dw 0x79c0, 0xc81d, 0x7fff, 0xc81d, 0x21, 0 + .dw 0x8040, 0xc81d, 0x807f, 0xc81d, 0x21, 0 + .dw 0x80c0, 0xc81d, 0x80ff, 0xc81d, 0x21, 0 + .dw 0x8140, 0xc81d, 0x817f, 0xc81d, 0x21, 0 + .dw 0x81c0, 0xc81d, 0x81ff, 0xc81d, 0x21, 0 + .dw 0x8240, 0xc81d, 0x827f, 0xc81d, 0x21, 0 + .dw 0x82c0, 0xc81d, 0x82ff, 0xc81d, 0x21, 0 + .dw 0x8340, 0xc81d, 0x837f, 0xc81d, 0x21, 0 + .dw 0x83c0, 0xc81d, 0x83ff, 0xc81d, 0x21, 0 + .dw 0x8440, 0xc81d, 0x847f, 0xc81d, 0x21, 0 + .dw 0x84c0, 0xc81d, 0x84ff, 0xc81d, 0x21, 0 + .dw 0x8540, 0xc81d, 0x857f, 0xc81d, 0x21, 0 + .dw 0x85c0, 0xc81d, 0x85ff, 0xc81d, 0x21, 0 + .dw 0x8640, 0xc81d, 0x867f, 0xc81d, 0x21, 0 + .dw 0x86c0, 0xc81d, 0x86ff, 0xc81d, 0x21, 0 + .dw 0x8740, 0xc81d, 0x877f, 0xc81d, 0x21, 0 + .dw 0x87c0, 0xc81d, 0x87ff, 0xc81d, 0x21, 0 + .dw 0x8840, 0xc81d, 0x887f, 0xc81d, 0x21, 0 + .dw 0x88c0, 0xc81d, 0x88ff, 0xc81d, 0x21, 0 + .dw 0x8940, 0xc81d, 0x897f, 0xc81d, 0x21, 0 + .dw 0x89c0, 0xc81d, 0x89ff, 0xc81d, 0x21, 0 + .dw 0x8a40, 0xc81d, 0x8a7f, 0xc81d, 0x21, 0 + .dw 0x8ac0, 0xc81d, 0x8aff, 0xc81d, 0x21, 0 + .dw 0x8b40, 0xc81d, 0x8b7f, 0xc81d, 0x21, 0 + .dw 0x8bc0, 0xc81d, 0x8bff, 0xc81d, 0x21, 0 + .dw 0x8c40, 0xc81d, 0x8c7f, 0xc81d, 0x21, 0 + .dw 0x8cc0, 0xc81d, 0x8cff, 0xc81d, 0x21, 0 + .dw 0x8d40, 0xc81d, 0x8d7f, 0xc81d, 0x21, 0 + .dw 0x8dc0, 0xc81d, 0x8dff, 0xc81d, 0x21, 0 + .dw 0x8e40, 0xc81d, 0x8e7f, 0xc81d, 0x21, 0 + .dw 0x8ec0, 0xc81d, 0x8eff, 0xc81d, 0x21, 0 + .dw 0x8f40, 0xc81d, 0x8f7f, 0xc81d, 0x21, 0 + .dw 0x8fc0, 0xc81d, 0x8fff, 0xc81d, 0x21, 0 + .dw 0x9040, 0xc81d, 0x907f, 0xc81d, 0x21, 0 + .dw 0x90c0, 0xc81d, 0x90ff, 0xc81d, 0x21, 0 + .dw 0x9140, 0xc81d, 0x917f, 0xc81d, 0x21, 0 + .dw 0x91c0, 0xc81d, 0x91ff, 0xc81d, 0x21, 0 + .dw 0x9240, 0xc81d, 0x927f, 0xc81d, 0x21, 0 + .dw 0x92c0, 0xc81d, 0x92ff, 0xc81d, 0x21, 0 + .dw 0x9340, 0xc81d, 0x937f, 0xc81d, 0x21, 0 + .dw 0x93c0, 0xc81d, 0x93ff, 0xc81d, 0x21, 0 + .dw 0x9440, 0xc81d, 0x947f, 0xc81d, 0x21, 0 + .dw 0x94c0, 0xc81d, 0x94ff, 0xc81d, 0x21, 0 + .dw 0x9540, 0xc81d, 0x957f, 0xc81d, 0x21, 0 + .dw 0x95c0, 0xc81d, 0x95ff, 0xc81d, 0x21, 0 + .dw 0x9640, 0xc81d, 0x967f, 0xc81d, 0x21, 0 + .dw 0x96c0, 0xc81d, 0x96ff, 0xc81d, 0x21, 0 + .dw 0x9740, 0xc81d, 0x977f, 0xc81d, 0x21, 0 + .dw 0x97c0, 0xc81d, 0x97ff, 0xc81d, 0x21, 0 + .dw 0x9840, 0xc81d, 0x987f, 0xc81d, 0x21, 0 + .dw 0x98c0, 0xc81d, 0x98ff, 0xc81d, 0x21, 0 + .dw 0x9940, 0xc81d, 0x997f, 0xc81d, 0x21, 0 + .dw 0x99c0, 0xc81d, 0x9fff, 0xc81d, 0x21, 0 + .dw 0xa040, 0xc81d, 0xa07f, 0xc81d, 0x21, 0 + .dw 0xa0c0, 0xc81d, 0xa0ff, 0xc81d, 0x21, 0 + .dw 0xa140, 0xc81d, 0xa17f, 0xc81d, 0x21, 0 + .dw 0xa1c0, 0xc81d, 0xa1ff, 0xc81d, 0x21, 0 + .dw 0xa240, 0xc81d, 0xa27f, 0xc81d, 0x21, 0 + .dw 0xa2c0, 0xc81d, 0xa2ff, 0xc81d, 0x21, 0 + .dw 0xa340, 0xc81d, 0xa37f, 0xc81d, 0x21, 0 + .dw 0xa3c0, 0xc81d, 0xa3ff, 0xc81d, 0x21, 0 + .dw 0xa440, 0xc81d, 0xa47f, 0xc81d, 0x21, 0 + .dw 0xa4c0, 0xc81d, 0xa4ff, 0xc81d, 0x21, 0 + .dw 0xa540, 0xc81d, 0xa57f, 0xc81d, 0x21, 0 + .dw 0xa5c0, 0xc81d, 0xa5ff, 0xc81d, 0x21, 0 + .dw 0xa640, 0xc81d, 0xa67f, 0xc81d, 0x21, 0 + .dw 0xa6c0, 0xc81d, 0xa6ff, 0xc81d, 0x21, 0 + .dw 0xa740, 0xc81d, 0xa77f, 0xc81d, 0x21, 0 + .dw 0xa7c0, 0xc81d, 0xa7ff, 0xc81d, 0x21, 0 + .dw 0xa840, 0xc81d, 0xa87f, 0xc81d, 0x21, 0 + .dw 0xa8c0, 0xc81d, 0xa8ff, 0xc81d, 0x21, 0 + .dw 0xa940, 0xc81d, 0xa97f, 0xc81d, 0x21, 0 + .dw 0xa9c0, 0xc81d, 0xa9ff, 0xc81d, 0x21, 0 + .dw 0xaa40, 0xc81d, 0xaa7f, 0xc81d, 0x21, 0 + .dw 0xaac0, 0xc81d, 0xaaff, 0xc81d, 0x21, 0 + .dw 0xab40, 0xc81d, 0xab7f, 0xc81d, 0x21, 0 + .dw 0xabc0, 0xc81d, 0xabff, 0xc81d, 0x21, 0 + .dw 0xac40, 0xc81d, 0xac7f, 0xc81d, 0x21, 0 + .dw 0xacc0, 0xc81d, 0xacff, 0xc81d, 0x21, 0 + .dw 0xad40, 0xc81d, 0xad7f, 0xc81d, 0x21, 0 + .dw 0xadc0, 0xc81d, 0xadff, 0xc81d, 0x21, 0 + .dw 0xae40, 0xc81d, 0xae7f, 0xc81d, 0x21, 0 + .dw 0xaec0, 0xc81d, 0xaeff, 0xc81d, 0x21, 0 + .dw 0xaf40, 0xc81d, 0xaf7f, 0xc81d, 0x21, 0 + .dw 0xafc0, 0xc81d, 0xafff, 0xc81d, 0x21, 0 + .dw 0xb040, 0xc81d, 0xb07f, 0xc81d, 0x21, 0 + .dw 0xb0c0, 0xc81d, 0xb0ff, 0xc81d, 0x21, 0 + .dw 0xb140, 0xc81d, 0xb17f, 0xc81d, 0x21, 0 + .dw 0xb1c0, 0xc81d, 0xb1ff, 0xc81d, 0x21, 0 + .dw 0xb240, 0xc81d, 0xb27f, 0xc81d, 0x21, 0 + .dw 0xb2c0, 0xc81d, 0xb2ff, 0xc81d, 0x21, 0 + .dw 0xb340, 0xc81d, 0xb37f, 0xc81d, 0x21, 0 + .dw 0xb3c0, 0xc81d, 0xb3ff, 0xc81d, 0x21, 0 + .dw 0xb440, 0xc81d, 0xb47f, 0xc81d, 0x21, 0 + .dw 0xb4c0, 0xc81d, 0xb4ff, 0xc81d, 0x21, 0 + .dw 0xb540, 0xc81d, 0xb57f, 0xc81d, 0x21, 0 + .dw 0xb5c0, 0xc81d, 0xb5ff, 0xc81d, 0x21, 0 + .dw 0xb640, 0xc81d, 0xb67f, 0xc81d, 0x21, 0 + .dw 0xb6c0, 0xc81d, 0xb6ff, 0xc81d, 0x21, 0 + .dw 0xb740, 0xc81d, 0xb77f, 0xc81d, 0x21, 0 + .dw 0xb7c0, 0xc81d, 0xb7ff, 0xc81d, 0x21, 0 + .dw 0xb840, 0xc81d, 0xb87f, 0xc81d, 0x21, 0 + .dw 0xb8c0, 0xc81d, 0xb8ff, 0xc81d, 0x21, 0 + .dw 0xb940, 0xc81d, 0xb97f, 0xc81d, 0x21, 0 + .dw 0xb9c0, 0xc81d, 0xbfff, 0xc81d, 0x21, 0 + .dw 0xc040, 0xc81d, 0xc07f, 0xc81d, 0x21, 0 + .dw 0xc0c0, 0xc81d, 0xc0ff, 0xc81d, 0x21, 0 + .dw 0xc140, 0xc81d, 0xc17f, 0xc81d, 0x21, 0 + .dw 0xc1c0, 0xc81d, 0xc1ff, 0xc81d, 0x21, 0 + .dw 0xc240, 0xc81d, 0xc27f, 0xc81d, 0x21, 0 + .dw 0xc2c0, 0xc81d, 0xc2ff, 0xc81d, 0x21, 0 + .dw 0xc340, 0xc81d, 0xc37f, 0xc81d, 0x21, 0 + .dw 0xc3c0, 0xc81d, 0xc3ff, 0xc81d, 0x21, 0 + .dw 0xc440, 0xc81d, 0xc47f, 0xc81d, 0x21, 0 + .dw 0xc4c0, 0xc81d, 0xc4ff, 0xc81d, 0x21, 0 + .dw 0xc540, 0xc81d, 0xc57f, 0xc81d, 0x21, 0 + .dw 0xc5c0, 0xc81d, 0xc5ff, 0xc81d, 0x21, 0 + .dw 0xc640, 0xc81d, 0xc67f, 0xc81d, 0x21, 0 + .dw 0xc6c0, 0xc81d, 0xc6ff, 0xc81d, 0x21, 0 + .dw 0xc740, 0xc81d, 0xc77f, 0xc81d, 0x21, 0 + .dw 0xc7c0, 0xc81d, 0xc7ff, 0xc81d, 0x21, 0 + .dw 0xc840, 0xc81d, 0xc87f, 0xc81d, 0x21, 0 + .dw 0xc8c0, 0xc81d, 0xc8ff, 0xc81d, 0x21, 0 + .dw 0xc940, 0xc81d, 0xc97f, 0xc81d, 0x21, 0 + .dw 0xc9c0, 0xc81d, 0xc9ff, 0xc81d, 0x21, 0 + .dw 0xca40, 0xc81d, 0xca7f, 0xc81d, 0x21, 0 + .dw 0xcac0, 0xc81d, 0xcaff, 0xc81d, 0x21, 0 + .dw 0xcb40, 0xc81d, 0xcb7f, 0xc81d, 0x21, 0 + .dw 0xcbc0, 0xc81d, 0xcbff, 0xc81d, 0x21, 0 + .dw 0xcc40, 0xc81d, 0xcc7f, 0xc81d, 0x21, 0 + .dw 0xccc0, 0xc81d, 0xccff, 0xc81d, 0x21, 0 + .dw 0xcd40, 0xc81d, 0xcd7f, 0xc81d, 0x21, 0 + .dw 0xcdc0, 0xc81d, 0xcdff, 0xc81d, 0x21, 0 + .dw 0xce40, 0xc81d, 0xce7f, 0xc81d, 0x21, 0 + .dw 0xcec0, 0xc81d, 0xceff, 0xc81d, 0x21, 0 + .dw 0xcf40, 0xc81d, 0xcf7f, 0xc81d, 0x21, 0 + .dw 0xcfc0, 0xc81d, 0xcfff, 0xc81d, 0x21, 0 + .dw 0xd040, 0xc81d, 0xd07f, 0xc81d, 0x21, 0 + .dw 0xd0c0, 0xc81d, 0xd0ff, 0xc81d, 0x21, 0 + .dw 0xd140, 0xc81d, 0xd17f, 0xc81d, 0x21, 0 + .dw 0xd1c0, 0xc81d, 0xd1ff, 0xc81d, 0x21, 0 + .dw 0xd240, 0xc81d, 0xd27f, 0xc81d, 0x21, 0 + .dw 0xd2c0, 0xc81d, 0xd2ff, 0xc81d, 0x21, 0 + .dw 0xd340, 0xc81d, 0xd37f, 0xc81d, 0x21, 0 + .dw 0xd3c0, 0xc81d, 0xd3ff, 0xc81d, 0x21, 0 + .dw 0xd440, 0xc81d, 0xd47f, 0xc81d, 0x21, 0 + .dw 0xd4c0, 0xc81d, 0xd4ff, 0xc81d, 0x21, 0 + .dw 0xd540, 0xc81d, 0xd57f, 0xc81d, 0x21, 0 + .dw 0xd5c0, 0xc81d, 0xd5ff, 0xc81d, 0x21, 0 + .dw 0xd640, 0xc81d, 0xd67f, 0xc81d, 0x21, 0 + .dw 0xd6c0, 0xc81d, 0xd6ff, 0xc81d, 0x21, 0 + .dw 0xd740, 0xc81d, 0xd77f, 0xc81d, 0x21, 0 + .dw 0xd7c0, 0xc81d, 0xd7ff, 0xc81d, 0x21, 0 + .dw 0xd840, 0xc81d, 0xd87f, 0xc81d, 0x21, 0 + .dw 0xd8c0, 0xc81d, 0xd8ff, 0xc81d, 0x21, 0 + .dw 0xd940, 0xc81d, 0xd97f, 0xc81d, 0x21, 0 + .dw 0xd9c0, 0xc81d, 0xdfff, 0xc81d, 0x21, 0 + .dw 0xe040, 0xc81d, 0xe07f, 0xc81d, 0x21, 0 + .dw 0xe0c0, 0xc81d, 0xe0ff, 0xc81d, 0x21, 0 + .dw 0xe140, 0xc81d, 0xe17f, 0xc81d, 0x21, 0 + .dw 0xe1c0, 0xc81d, 0xe1ff, 0xc81d, 0x21, 0 + .dw 0xe240, 0xc81d, 0xe27f, 0xc81d, 0x21, 0 + .dw 0xe2c0, 0xc81d, 0xe2ff, 0xc81d, 0x21, 0 + .dw 0xe340, 0xc81d, 0xe37f, 0xc81d, 0x21, 0 + .dw 0xe3c0, 0xc81d, 0xe3ff, 0xc81d, 0x21, 0 + .dw 0xe440, 0xc81d, 0xe47f, 0xc81d, 0x21, 0 + .dw 0xe4c0, 0xc81d, 0xe4ff, 0xc81d, 0x21, 0 + .dw 0xe540, 0xc81d, 0xe57f, 0xc81d, 0x21, 0 + .dw 0xe5c0, 0xc81d, 0xe5ff, 0xc81d, 0x21, 0 + .dw 0xe640, 0xc81d, 0xe67f, 0xc81d, 0x21, 0 + .dw 0xe6c0, 0xc81d, 0xe6ff, 0xc81d, 0x21, 0 + .dw 0xe740, 0xc81d, 0xe77f, 0xc81d, 0x21, 0 + .dw 0xe7c0, 0xc81d, 0xe7ff, 0xc81d, 0x21, 0 + .dw 0xe840, 0xc81d, 0xe87f, 0xc81d, 0x21, 0 + .dw 0xe8c0, 0xc81d, 0xe8ff, 0xc81d, 0x21, 0 + .dw 0xe940, 0xc81d, 0xe97f, 0xc81d, 0x21, 0 + .dw 0xe9c0, 0xc81d, 0xe9ff, 0xc81d, 0x21, 0 + .dw 0xea40, 0xc81d, 0xea7f, 0xc81d, 0x21, 0 + .dw 0xeac0, 0xc81d, 0xeaff, 0xc81d, 0x21, 0 + .dw 0xeb40, 0xc81d, 0xeb7f, 0xc81d, 0x21, 0 + .dw 0xebc0, 0xc81d, 0xebff, 0xc81d, 0x21, 0 + .dw 0xec40, 0xc81d, 0xec7f, 0xc81d, 0x21, 0 + .dw 0xecc0, 0xc81d, 0xecff, 0xc81d, 0x21, 0 + .dw 0xed40, 0xc81d, 0xed7f, 0xc81d, 0x21, 0 + .dw 0xedc0, 0xc81d, 0xedff, 0xc81d, 0x21, 0 + .dw 0xee40, 0xc81d, 0xee7f, 0xc81d, 0x21, 0 + .dw 0xeec0, 0xc81d, 0xeeff, 0xc81d, 0x21, 0 + .dw 0xef40, 0xc81d, 0xef7f, 0xc81d, 0x21, 0 + .dw 0xefc0, 0xc81d, 0xefff, 0xc81d, 0x21, 0 + .dw 0xf040, 0xc81d, 0xf07f, 0xc81d, 0x21, 0 + .dw 0xf0c0, 0xc81d, 0xf0ff, 0xc81d, 0x21, 0 + .dw 0xf140, 0xc81d, 0xf17f, 0xc81d, 0x21, 0 + .dw 0xf1c0, 0xc81d, 0xf1ff, 0xc81d, 0x21, 0 + .dw 0xf240, 0xc81d, 0xf27f, 0xc81d, 0x21, 0 + .dw 0xf2c0, 0xc81d, 0xf2ff, 0xc81d, 0x21, 0 + .dw 0xf340, 0xc81d, 0xf37f, 0xc81d, 0x21, 0 + .dw 0xf3c0, 0xc81d, 0xf3ff, 0xc81d, 0x21, 0 + .dw 0xf440, 0xc81d, 0xf47f, 0xc81d, 0x21, 0 + .dw 0xf4c0, 0xc81d, 0xf4ff, 0xc81d, 0x21, 0 + .dw 0xf540, 0xc81d, 0xf57f, 0xc81d, 0x21, 0 + .dw 0xf5c0, 0xc81d, 0xf5ff, 0xc81d, 0x21, 0 + .dw 0xf640, 0xc81d, 0xf67f, 0xc81d, 0x21, 0 + .dw 0xf6c0, 0xc81d, 0xf6ff, 0xc81d, 0x21, 0 + .dw 0xf740, 0xc81d, 0xf77f, 0xc81d, 0x21, 0 + .dw 0xf7c0, 0xc81d, 0xf7ff, 0xc81d, 0x21, 0 + .dw 0xf840, 0xc81d, 0xf87f, 0xc81d, 0x21, 0 + .dw 0xf8c0, 0xc81d, 0xf8ff, 0xc81d, 0x21, 0 + .dw 0xf940, 0xc81d, 0xf97f, 0xc81d, 0x21, 0 + .dw 0xf9c0, 0xc81d, 0xffff, 0xc81d, 0x21, 0 + .dw 0x0040, 0xc81e, 0x007f, 0xc81e, 0x21, 0 + .dw 0x00c0, 0xc81e, 0x00ff, 0xc81e, 0x21, 0 + .dw 0x0140, 0xc81e, 0x017f, 0xc81e, 0x21, 0 + .dw 0x01c0, 0xc81e, 0x01ff, 0xc81e, 0x21, 0 + .dw 0x0240, 0xc81e, 0x027f, 0xc81e, 0x21, 0 + .dw 0x02c0, 0xc81e, 0x02ff, 0xc81e, 0x21, 0 + .dw 0x0340, 0xc81e, 0x037f, 0xc81e, 0x21, 0 + .dw 0x03c0, 0xc81e, 0x03ff, 0xc81e, 0x21, 0 + .dw 0x0440, 0xc81e, 0x047f, 0xc81e, 0x21, 0 + .dw 0x04c0, 0xc81e, 0x04ff, 0xc81e, 0x21, 0 + .dw 0x0540, 0xc81e, 0x057f, 0xc81e, 0x21, 0 + .dw 0x05c0, 0xc81e, 0x05ff, 0xc81e, 0x21, 0 + .dw 0x0640, 0xc81e, 0x067f, 0xc81e, 0x21, 0 + .dw 0x06c0, 0xc81e, 0x06ff, 0xc81e, 0x21, 0 + .dw 0x0740, 0xc81e, 0x077f, 0xc81e, 0x21, 0 + .dw 0x07c0, 0xc81e, 0x07ff, 0xc81e, 0x21, 0 + .dw 0x0840, 0xc81e, 0x087f, 0xc81e, 0x21, 0 + .dw 0x08c0, 0xc81e, 0x08ff, 0xc81e, 0x21, 0 + .dw 0x0940, 0xc81e, 0x097f, 0xc81e, 0x21, 0 + .dw 0x09c0, 0xc81e, 0x09ff, 0xc81e, 0x21, 0 + .dw 0x0a40, 0xc81e, 0x0a7f, 0xc81e, 0x21, 0 + .dw 0x0ac0, 0xc81e, 0x0aff, 0xc81e, 0x21, 0 + .dw 0x0b40, 0xc81e, 0x0b7f, 0xc81e, 0x21, 0 + .dw 0x0bc0, 0xc81e, 0x0bff, 0xc81e, 0x21, 0 + .dw 0x0c40, 0xc81e, 0x0c7f, 0xc81e, 0x21, 0 + .dw 0x0cc0, 0xc81e, 0x0cff, 0xc81e, 0x21, 0 + .dw 0x0d40, 0xc81e, 0x0d7f, 0xc81e, 0x21, 0 + .dw 0x0dc0, 0xc81e, 0x0dff, 0xc81e, 0x21, 0 + .dw 0x0e40, 0xc81e, 0x0e7f, 0xc81e, 0x21, 0 + .dw 0x0ec0, 0xc81e, 0x0eff, 0xc81e, 0x21, 0 + .dw 0x0f40, 0xc81e, 0x0f7f, 0xc81e, 0x21, 0 + .dw 0x0fc0, 0xc81e, 0x0fff, 0xc81e, 0x21, 0 + .dw 0x1040, 0xc81e, 0x107f, 0xc81e, 0x21, 0 + .dw 0x10c0, 0xc81e, 0x10ff, 0xc81e, 0x21, 0 + .dw 0x1140, 0xc81e, 0x117f, 0xc81e, 0x21, 0 + .dw 0x11c0, 0xc81e, 0x11ff, 0xc81e, 0x21, 0 + .dw 0x1240, 0xc81e, 0x127f, 0xc81e, 0x21, 0 + .dw 0x12c0, 0xc81e, 0x12ff, 0xc81e, 0x21, 0 + .dw 0x1340, 0xc81e, 0x137f, 0xc81e, 0x21, 0 + .dw 0x13c0, 0xc81e, 0x13ff, 0xc81e, 0x21, 0 + .dw 0x1440, 0xc81e, 0x147f, 0xc81e, 0x21, 0 + .dw 0x14c0, 0xc81e, 0x14ff, 0xc81e, 0x21, 0 + .dw 0x1540, 0xc81e, 0x157f, 0xc81e, 0x21, 0 + .dw 0x15c0, 0xc81e, 0x15ff, 0xc81e, 0x21, 0 + .dw 0x1640, 0xc81e, 0x167f, 0xc81e, 0x21, 0 + .dw 0x16c0, 0xc81e, 0x16ff, 0xc81e, 0x21, 0 + .dw 0x1740, 0xc81e, 0x177f, 0xc81e, 0x21, 0 + .dw 0x17c0, 0xc81e, 0x17ff, 0xc81e, 0x21, 0 + .dw 0x1840, 0xc81e, 0x187f, 0xc81e, 0x21, 0 + .dw 0x18c0, 0xc81e, 0x18ff, 0xc81e, 0x21, 0 + .dw 0x1940, 0xc81e, 0x197f, 0xc81e, 0x21, 0 + .dw 0x19c0, 0xc81e, 0x1fff, 0xc81e, 0x21, 0 + .dw 0x2040, 0xc81e, 0x207f, 0xc81e, 0x21, 0 + .dw 0x20c0, 0xc81e, 0x20ff, 0xc81e, 0x21, 0 + .dw 0x2140, 0xc81e, 0x217f, 0xc81e, 0x21, 0 + .dw 0x21c0, 0xc81e, 0x21ff, 0xc81e, 0x21, 0 + .dw 0x2240, 0xc81e, 0x227f, 0xc81e, 0x21, 0 + .dw 0x22c0, 0xc81e, 0x22ff, 0xc81e, 0x21, 0 + .dw 0x2340, 0xc81e, 0x237f, 0xc81e, 0x21, 0 + .dw 0x23c0, 0xc81e, 0x23ff, 0xc81e, 0x21, 0 + .dw 0x2440, 0xc81e, 0x247f, 0xc81e, 0x21, 0 + .dw 0x24c0, 0xc81e, 0x24ff, 0xc81e, 0x21, 0 + .dw 0x2540, 0xc81e, 0x257f, 0xc81e, 0x21, 0 + .dw 0x25c0, 0xc81e, 0x25ff, 0xc81e, 0x21, 0 + .dw 0x2640, 0xc81e, 0x267f, 0xc81e, 0x21, 0 + .dw 0x26c0, 0xc81e, 0x26ff, 0xc81e, 0x21, 0 + .dw 0x2740, 0xc81e, 0x277f, 0xc81e, 0x21, 0 + .dw 0x27c0, 0xc81e, 0x27ff, 0xc81e, 0x21, 0 + .dw 0x2840, 0xc81e, 0x287f, 0xc81e, 0x21, 0 + .dw 0x28c0, 0xc81e, 0x28ff, 0xc81e, 0x21, 0 + .dw 0x2940, 0xc81e, 0x297f, 0xc81e, 0x21, 0 + .dw 0x29c0, 0xc81e, 0x29ff, 0xc81e, 0x21, 0 + .dw 0x2a40, 0xc81e, 0x2a7f, 0xc81e, 0x21, 0 + .dw 0x2ac0, 0xc81e, 0x2aff, 0xc81e, 0x21, 0 + .dw 0x2b40, 0xc81e, 0x2b7f, 0xc81e, 0x21, 0 + .dw 0x2bc0, 0xc81e, 0x2bff, 0xc81e, 0x21, 0 + .dw 0x2c40, 0xc81e, 0x2c7f, 0xc81e, 0x21, 0 + .dw 0x2cc0, 0xc81e, 0x2cff, 0xc81e, 0x21, 0 + .dw 0x2d40, 0xc81e, 0x2d7f, 0xc81e, 0x21, 0 + .dw 0x2dc0, 0xc81e, 0x2dff, 0xc81e, 0x21, 0 + .dw 0x2e40, 0xc81e, 0x2e7f, 0xc81e, 0x21, 0 + .dw 0x2ec0, 0xc81e, 0x2eff, 0xc81e, 0x21, 0 + .dw 0x2f40, 0xc81e, 0x2f7f, 0xc81e, 0x21, 0 + .dw 0x2fc0, 0xc81e, 0x2fff, 0xc81e, 0x21, 0 + .dw 0x3040, 0xc81e, 0x307f, 0xc81e, 0x21, 0 + .dw 0x30c0, 0xc81e, 0x30ff, 0xc81e, 0x21, 0 + .dw 0x3140, 0xc81e, 0x317f, 0xc81e, 0x21, 0 + .dw 0x31c0, 0xc81e, 0x31ff, 0xc81e, 0x21, 0 + .dw 0x3240, 0xc81e, 0x327f, 0xc81e, 0x21, 0 + .dw 0x32c0, 0xc81e, 0x32ff, 0xc81e, 0x21, 0 + .dw 0x3340, 0xc81e, 0x337f, 0xc81e, 0x21, 0 + .dw 0x33c0, 0xc81e, 0x33ff, 0xc81e, 0x21, 0 + .dw 0x3440, 0xc81e, 0x347f, 0xc81e, 0x21, 0 + .dw 0x34c0, 0xc81e, 0x34ff, 0xc81e, 0x21, 0 + .dw 0x3540, 0xc81e, 0x357f, 0xc81e, 0x21, 0 + .dw 0x35c0, 0xc81e, 0x35ff, 0xc81e, 0x21, 0 + .dw 0x3640, 0xc81e, 0x367f, 0xc81e, 0x21, 0 + .dw 0x36c0, 0xc81e, 0x36ff, 0xc81e, 0x21, 0 + .dw 0x3740, 0xc81e, 0x377f, 0xc81e, 0x21, 0 + .dw 0x37c0, 0xc81e, 0x37ff, 0xc81e, 0x21, 0 + .dw 0x3840, 0xc81e, 0x387f, 0xc81e, 0x21, 0 + .dw 0x38c0, 0xc81e, 0x38ff, 0xc81e, 0x21, 0 + .dw 0x3940, 0xc81e, 0x397f, 0xc81e, 0x21, 0 + .dw 0x39c0, 0xc81e, 0x3fff, 0xc81e, 0x21, 0 + .dw 0x4040, 0xc81e, 0x407f, 0xc81e, 0x21, 0 + .dw 0x40c0, 0xc81e, 0x40ff, 0xc81e, 0x21, 0 + .dw 0x4140, 0xc81e, 0x417f, 0xc81e, 0x21, 0 + .dw 0x41c0, 0xc81e, 0x41ff, 0xc81e, 0x21, 0 + .dw 0x4240, 0xc81e, 0x427f, 0xc81e, 0x21, 0 + .dw 0x42c0, 0xc81e, 0x42ff, 0xc81e, 0x21, 0 + .dw 0x4340, 0xc81e, 0x437f, 0xc81e, 0x21, 0 + .dw 0x43c0, 0xc81e, 0x43ff, 0xc81e, 0x21, 0 + .dw 0x4440, 0xc81e, 0x447f, 0xc81e, 0x21, 0 + .dw 0x44c0, 0xc81e, 0x44ff, 0xc81e, 0x21, 0 + .dw 0x4540, 0xc81e, 0x457f, 0xc81e, 0x21, 0 + .dw 0x45c0, 0xc81e, 0x45ff, 0xc81e, 0x21, 0 + .dw 0x4640, 0xc81e, 0x467f, 0xc81e, 0x21, 0 + .dw 0x46c0, 0xc81e, 0x46ff, 0xc81e, 0x21, 0 + .dw 0x4740, 0xc81e, 0x477f, 0xc81e, 0x21, 0 + .dw 0x47c0, 0xc81e, 0x47ff, 0xc81e, 0x21, 0 + .dw 0x4840, 0xc81e, 0x487f, 0xc81e, 0x21, 0 + .dw 0x48c0, 0xc81e, 0x48ff, 0xc81e, 0x21, 0 + .dw 0x4940, 0xc81e, 0x497f, 0xc81e, 0x21, 0 + .dw 0x49c0, 0xc81e, 0x49ff, 0xc81e, 0x21, 0 + .dw 0x4a40, 0xc81e, 0x4a7f, 0xc81e, 0x21, 0 + .dw 0x4ac0, 0xc81e, 0x4aff, 0xc81e, 0x21, 0 + .dw 0x4b40, 0xc81e, 0x4b7f, 0xc81e, 0x21, 0 + .dw 0x4bc0, 0xc81e, 0x4bff, 0xc81e, 0x21, 0 + .dw 0x4c40, 0xc81e, 0x4c7f, 0xc81e, 0x21, 0 + .dw 0x4cc0, 0xc81e, 0x4cff, 0xc81e, 0x21, 0 + .dw 0x4d40, 0xc81e, 0x4d7f, 0xc81e, 0x21, 0 + .dw 0x4dc0, 0xc81e, 0x4dff, 0xc81e, 0x21, 0 + .dw 0x4e40, 0xc81e, 0x4e7f, 0xc81e, 0x21, 0 + .dw 0x4ec0, 0xc81e, 0x4eff, 0xc81e, 0x21, 0 + .dw 0x4f40, 0xc81e, 0x4f7f, 0xc81e, 0x21, 0 + .dw 0x4fc0, 0xc81e, 0x4fff, 0xc81e, 0x21, 0 + .dw 0x5040, 0xc81e, 0x507f, 0xc81e, 0x21, 0 + .dw 0x50c0, 0xc81e, 0x50ff, 0xc81e, 0x21, 0 + .dw 0x5140, 0xc81e, 0x517f, 0xc81e, 0x21, 0 + .dw 0x51c0, 0xc81e, 0x51ff, 0xc81e, 0x21, 0 + .dw 0x5240, 0xc81e, 0x527f, 0xc81e, 0x21, 0 + .dw 0x52c0, 0xc81e, 0x52ff, 0xc81e, 0x21, 0 + .dw 0x5340, 0xc81e, 0x537f, 0xc81e, 0x21, 0 + .dw 0x53c0, 0xc81e, 0x53ff, 0xc81e, 0x21, 0 + .dw 0x5440, 0xc81e, 0x547f, 0xc81e, 0x21, 0 + .dw 0x54c0, 0xc81e, 0x54ff, 0xc81e, 0x21, 0 + .dw 0x5540, 0xc81e, 0x557f, 0xc81e, 0x21, 0 + .dw 0x55c0, 0xc81e, 0x55ff, 0xc81e, 0x21, 0 + .dw 0x5640, 0xc81e, 0x567f, 0xc81e, 0x21, 0 + .dw 0x56c0, 0xc81e, 0x56ff, 0xc81e, 0x21, 0 + .dw 0x5740, 0xc81e, 0x577f, 0xc81e, 0x21, 0 + .dw 0x57c0, 0xc81e, 0x57ff, 0xc81e, 0x21, 0 + .dw 0x5840, 0xc81e, 0x587f, 0xc81e, 0x21, 0 + .dw 0x58c0, 0xc81e, 0x58ff, 0xc81e, 0x21, 0 + .dw 0x5940, 0xc81e, 0x597f, 0xc81e, 0x21, 0 + .dw 0x59c0, 0xc81e, 0x5fff, 0xc81e, 0x21, 0 + .dw 0x6040, 0xc81e, 0x607f, 0xc81e, 0x21, 0 + .dw 0x60c0, 0xc81e, 0x60ff, 0xc81e, 0x21, 0 + .dw 0x6140, 0xc81e, 0x617f, 0xc81e, 0x21, 0 + .dw 0x61c0, 0xc81e, 0x61ff, 0xc81e, 0x21, 0 + .dw 0x6240, 0xc81e, 0x627f, 0xc81e, 0x21, 0 + .dw 0x62c0, 0xc81e, 0x62ff, 0xc81e, 0x21, 0 + .dw 0x6340, 0xc81e, 0x637f, 0xc81e, 0x21, 0 + .dw 0x63c0, 0xc81e, 0x63ff, 0xc81e, 0x21, 0 + .dw 0x6440, 0xc81e, 0x647f, 0xc81e, 0x21, 0 + .dw 0x64c0, 0xc81e, 0x64ff, 0xc81e, 0x21, 0 + .dw 0x6540, 0xc81e, 0x657f, 0xc81e, 0x21, 0 + .dw 0x65c0, 0xc81e, 0x65ff, 0xc81e, 0x21, 0 + .dw 0x6640, 0xc81e, 0x667f, 0xc81e, 0x21, 0 + .dw 0x66c0, 0xc81e, 0x66ff, 0xc81e, 0x21, 0 + .dw 0x6740, 0xc81e, 0x677f, 0xc81e, 0x21, 0 + .dw 0x67c0, 0xc81e, 0x67ff, 0xc81e, 0x21, 0 + .dw 0x6840, 0xc81e, 0x687f, 0xc81e, 0x21, 0 + .dw 0x68c0, 0xc81e, 0x68ff, 0xc81e, 0x21, 0 + .dw 0x6940, 0xc81e, 0x697f, 0xc81e, 0x21, 0 + .dw 0x69c0, 0xc81e, 0x69ff, 0xc81e, 0x21, 0 + .dw 0x6a40, 0xc81e, 0x6a7f, 0xc81e, 0x21, 0 + .dw 0x6ac0, 0xc81e, 0x6aff, 0xc81e, 0x21, 0 + .dw 0x6b40, 0xc81e, 0x6b7f, 0xc81e, 0x21, 0 + .dw 0x6bc0, 0xc81e, 0x6bff, 0xc81e, 0x21, 0 + .dw 0x6c40, 0xc81e, 0x6c7f, 0xc81e, 0x21, 0 + .dw 0x6cc0, 0xc81e, 0x6cff, 0xc81e, 0x21, 0 + .dw 0x6d40, 0xc81e, 0x6d7f, 0xc81e, 0x21, 0 + .dw 0x6dc0, 0xc81e, 0x6dff, 0xc81e, 0x21, 0 + .dw 0x6e40, 0xc81e, 0x6e7f, 0xc81e, 0x21, 0 + .dw 0x6ec0, 0xc81e, 0x6eff, 0xc81e, 0x21, 0 + .dw 0x6f40, 0xc81e, 0x6f7f, 0xc81e, 0x21, 0 + .dw 0x6fc0, 0xc81e, 0x6fff, 0xc81e, 0x21, 0 + .dw 0x7040, 0xc81e, 0x707f, 0xc81e, 0x21, 0 + .dw 0x70c0, 0xc81e, 0x70ff, 0xc81e, 0x21, 0 + .dw 0x7140, 0xc81e, 0x717f, 0xc81e, 0x21, 0 + .dw 0x71c0, 0xc81e, 0x71ff, 0xc81e, 0x21, 0 + .dw 0x7240, 0xc81e, 0x727f, 0xc81e, 0x21, 0 + .dw 0x72c0, 0xc81e, 0x72ff, 0xc81e, 0x21, 0 + .dw 0x7340, 0xc81e, 0x737f, 0xc81e, 0x21, 0 + .dw 0x73c0, 0xc81e, 0x73ff, 0xc81e, 0x21, 0 + .dw 0x7440, 0xc81e, 0x747f, 0xc81e, 0x21, 0 + .dw 0x74c0, 0xc81e, 0x74ff, 0xc81e, 0x21, 0 + .dw 0x7540, 0xc81e, 0x757f, 0xc81e, 0x21, 0 + .dw 0x75c0, 0xc81e, 0x75ff, 0xc81e, 0x21, 0 + .dw 0x7640, 0xc81e, 0x767f, 0xc81e, 0x21, 0 + .dw 0x76c0, 0xc81e, 0x76ff, 0xc81e, 0x21, 0 + .dw 0x7740, 0xc81e, 0x777f, 0xc81e, 0x21, 0 + .dw 0x77c0, 0xc81e, 0x77ff, 0xc81e, 0x21, 0 + .dw 0x7840, 0xc81e, 0x787f, 0xc81e, 0x21, 0 + .dw 0x78c0, 0xc81e, 0x78ff, 0xc81e, 0x21, 0 + .dw 0x7940, 0xc81e, 0x797f, 0xc81e, 0x21, 0 + .dw 0x79c0, 0xc81e, 0x7fff, 0xc81e, 0x21, 0 + .dw 0x8040, 0xc81e, 0x807f, 0xc81e, 0x21, 0 + .dw 0x80c0, 0xc81e, 0x80ff, 0xc81e, 0x21, 0 + .dw 0x8140, 0xc81e, 0x817f, 0xc81e, 0x21, 0 + .dw 0x81c0, 0xc81e, 0x81ff, 0xc81e, 0x21, 0 + .dw 0x8240, 0xc81e, 0x827f, 0xc81e, 0x21, 0 + .dw 0x82c0, 0xc81e, 0x82ff, 0xc81e, 0x21, 0 + .dw 0x8340, 0xc81e, 0x837f, 0xc81e, 0x21, 0 + .dw 0x83c0, 0xc81e, 0x83ff, 0xc81e, 0x21, 0 + .dw 0x8440, 0xc81e, 0x847f, 0xc81e, 0x21, 0 + .dw 0x84c0, 0xc81e, 0x84ff, 0xc81e, 0x21, 0 + .dw 0x8540, 0xc81e, 0x857f, 0xc81e, 0x21, 0 + .dw 0x85c0, 0xc81e, 0x85ff, 0xc81e, 0x21, 0 + .dw 0x8640, 0xc81e, 0x867f, 0xc81e, 0x21, 0 + .dw 0x86c0, 0xc81e, 0x86ff, 0xc81e, 0x21, 0 + .dw 0x8740, 0xc81e, 0x877f, 0xc81e, 0x21, 0 + .dw 0x87c0, 0xc81e, 0x87ff, 0xc81e, 0x21, 0 + .dw 0x8840, 0xc81e, 0x887f, 0xc81e, 0x21, 0 + .dw 0x88c0, 0xc81e, 0x88ff, 0xc81e, 0x21, 0 + .dw 0x8940, 0xc81e, 0x897f, 0xc81e, 0x21, 0 + .dw 0x89c0, 0xc81e, 0x89ff, 0xc81e, 0x21, 0 + .dw 0x8a40, 0xc81e, 0x8a7f, 0xc81e, 0x21, 0 + .dw 0x8ac0, 0xc81e, 0x8aff, 0xc81e, 0x21, 0 + .dw 0x8b40, 0xc81e, 0x8b7f, 0xc81e, 0x21, 0 + .dw 0x8bc0, 0xc81e, 0x8bff, 0xc81e, 0x21, 0 + .dw 0x8c40, 0xc81e, 0x8c7f, 0xc81e, 0x21, 0 + .dw 0x8cc0, 0xc81e, 0x8cff, 0xc81e, 0x21, 0 + .dw 0x8d40, 0xc81e, 0x8d7f, 0xc81e, 0x21, 0 + .dw 0x8dc0, 0xc81e, 0x8dff, 0xc81e, 0x21, 0 + .dw 0x8e40, 0xc81e, 0x8e7f, 0xc81e, 0x21, 0 + .dw 0x8ec0, 0xc81e, 0x8eff, 0xc81e, 0x21, 0 + .dw 0x8f40, 0xc81e, 0x8f7f, 0xc81e, 0x21, 0 + .dw 0x8fc0, 0xc81e, 0x8fff, 0xc81e, 0x21, 0 + .dw 0x9040, 0xc81e, 0x907f, 0xc81e, 0x21, 0 + .dw 0x90c0, 0xc81e, 0x90ff, 0xc81e, 0x21, 0 + .dw 0x9140, 0xc81e, 0x917f, 0xc81e, 0x21, 0 + .dw 0x91c0, 0xc81e, 0x91ff, 0xc81e, 0x21, 0 + .dw 0x9240, 0xc81e, 0x927f, 0xc81e, 0x21, 0 + .dw 0x92c0, 0xc81e, 0x92ff, 0xc81e, 0x21, 0 + .dw 0x9340, 0xc81e, 0x937f, 0xc81e, 0x21, 0 + .dw 0x93c0, 0xc81e, 0x93ff, 0xc81e, 0x21, 0 + .dw 0x9440, 0xc81e, 0x947f, 0xc81e, 0x21, 0 + .dw 0x94c0, 0xc81e, 0x94ff, 0xc81e, 0x21, 0 + .dw 0x9540, 0xc81e, 0x957f, 0xc81e, 0x21, 0 + .dw 0x95c0, 0xc81e, 0x95ff, 0xc81e, 0x21, 0 + .dw 0x9640, 0xc81e, 0x967f, 0xc81e, 0x21, 0 + .dw 0x96c0, 0xc81e, 0x96ff, 0xc81e, 0x21, 0 + .dw 0x9740, 0xc81e, 0x977f, 0xc81e, 0x21, 0 + .dw 0x97c0, 0xc81e, 0x97ff, 0xc81e, 0x21, 0 + .dw 0x9840, 0xc81e, 0x987f, 0xc81e, 0x21, 0 + .dw 0x98c0, 0xc81e, 0x98ff, 0xc81e, 0x21, 0 + .dw 0x9940, 0xc81e, 0x997f, 0xc81e, 0x21, 0 + .dw 0x99c0, 0xc81e, 0x9fff, 0xc81e, 0x21, 0 + .dw 0xa040, 0xc81e, 0xa07f, 0xc81e, 0x21, 0 + .dw 0xa0c0, 0xc81e, 0xa0ff, 0xc81e, 0x21, 0 + .dw 0xa140, 0xc81e, 0xa17f, 0xc81e, 0x21, 0 + .dw 0xa1c0, 0xc81e, 0xa1ff, 0xc81e, 0x21, 0 + .dw 0xa240, 0xc81e, 0xa27f, 0xc81e, 0x21, 0 + .dw 0xa2c0, 0xc81e, 0xa2ff, 0xc81e, 0x21, 0 + .dw 0xa340, 0xc81e, 0xa37f, 0xc81e, 0x21, 0 + .dw 0xa3c0, 0xc81e, 0xa3ff, 0xc81e, 0x21, 0 + .dw 0xa440, 0xc81e, 0xa47f, 0xc81e, 0x21, 0 + .dw 0xa4c0, 0xc81e, 0xa4ff, 0xc81e, 0x21, 0 + .dw 0xa540, 0xc81e, 0xa57f, 0xc81e, 0x21, 0 + .dw 0xa5c0, 0xc81e, 0xa5ff, 0xc81e, 0x21, 0 + .dw 0xa640, 0xc81e, 0xa67f, 0xc81e, 0x21, 0 + .dw 0xa6c0, 0xc81e, 0xa6ff, 0xc81e, 0x21, 0 + .dw 0xa740, 0xc81e, 0xa77f, 0xc81e, 0x21, 0 + .dw 0xa7c0, 0xc81e, 0xa7ff, 0xc81e, 0x21, 0 + .dw 0xa840, 0xc81e, 0xa87f, 0xc81e, 0x21, 0 + .dw 0xa8c0, 0xc81e, 0xa8ff, 0xc81e, 0x21, 0 + .dw 0xa940, 0xc81e, 0xa97f, 0xc81e, 0x21, 0 + .dw 0xa9c0, 0xc81e, 0xa9ff, 0xc81e, 0x21, 0 + .dw 0xaa40, 0xc81e, 0xaa7f, 0xc81e, 0x21, 0 + .dw 0xaac0, 0xc81e, 0xaaff, 0xc81e, 0x21, 0 + .dw 0xab40, 0xc81e, 0xab7f, 0xc81e, 0x21, 0 + .dw 0xabc0, 0xc81e, 0xabff, 0xc81e, 0x21, 0 + .dw 0xac40, 0xc81e, 0xac7f, 0xc81e, 0x21, 0 + .dw 0xacc0, 0xc81e, 0xacff, 0xc81e, 0x21, 0 + .dw 0xad40, 0xc81e, 0xad7f, 0xc81e, 0x21, 0 + .dw 0xadc0, 0xc81e, 0xadff, 0xc81e, 0x21, 0 + .dw 0xae40, 0xc81e, 0xae7f, 0xc81e, 0x21, 0 + .dw 0xaec0, 0xc81e, 0xaeff, 0xc81e, 0x21, 0 + .dw 0xaf40, 0xc81e, 0xaf7f, 0xc81e, 0x21, 0 + .dw 0xafc0, 0xc81e, 0xafff, 0xc81e, 0x21, 0 + .dw 0xb040, 0xc81e, 0xb07f, 0xc81e, 0x21, 0 + .dw 0xb0c0, 0xc81e, 0xb0ff, 0xc81e, 0x21, 0 + .dw 0xb140, 0xc81e, 0xb17f, 0xc81e, 0x21, 0 + .dw 0xb1c0, 0xc81e, 0xb1ff, 0xc81e, 0x21, 0 + .dw 0xb240, 0xc81e, 0xb27f, 0xc81e, 0x21, 0 + .dw 0xb2c0, 0xc81e, 0xb2ff, 0xc81e, 0x21, 0 + .dw 0xb340, 0xc81e, 0xb37f, 0xc81e, 0x21, 0 + .dw 0xb3c0, 0xc81e, 0xb3ff, 0xc81e, 0x21, 0 + .dw 0xb440, 0xc81e, 0xb47f, 0xc81e, 0x21, 0 + .dw 0xb4c0, 0xc81e, 0xb4ff, 0xc81e, 0x21, 0 + .dw 0xb540, 0xc81e, 0xb57f, 0xc81e, 0x21, 0 + .dw 0xb5c0, 0xc81e, 0xb5ff, 0xc81e, 0x21, 0 + .dw 0xb640, 0xc81e, 0xb67f, 0xc81e, 0x21, 0 + .dw 0xb6c0, 0xc81e, 0xb6ff, 0xc81e, 0x21, 0 + .dw 0xb740, 0xc81e, 0xb77f, 0xc81e, 0x21, 0 + .dw 0xb7c0, 0xc81e, 0xb7ff, 0xc81e, 0x21, 0 + .dw 0xb840, 0xc81e, 0xb87f, 0xc81e, 0x21, 0 + .dw 0xb8c0, 0xc81e, 0xb8ff, 0xc81e, 0x21, 0 + .dw 0xb940, 0xc81e, 0xb97f, 0xc81e, 0x21, 0 + .dw 0xb9c0, 0xc81e, 0xbfff, 0xc81e, 0x21, 0 + .dw 0xc040, 0xc81e, 0xc07f, 0xc81e, 0x21, 0 + .dw 0xc0c0, 0xc81e, 0xc0ff, 0xc81e, 0x21, 0 + .dw 0xc140, 0xc81e, 0xc17f, 0xc81e, 0x21, 0 + .dw 0xc1c0, 0xc81e, 0xc1ff, 0xc81e, 0x21, 0 + .dw 0xc240, 0xc81e, 0xc27f, 0xc81e, 0x21, 0 + .dw 0xc2c0, 0xc81e, 0xc2ff, 0xc81e, 0x21, 0 + .dw 0xc340, 0xc81e, 0xc37f, 0xc81e, 0x21, 0 + .dw 0xc3c0, 0xc81e, 0xc3ff, 0xc81e, 0x21, 0 + .dw 0xc440, 0xc81e, 0xc47f, 0xc81e, 0x21, 0 + .dw 0xc4c0, 0xc81e, 0xc4ff, 0xc81e, 0x21, 0 + .dw 0xc540, 0xc81e, 0xc57f, 0xc81e, 0x21, 0 + .dw 0xc5c0, 0xc81e, 0xc5ff, 0xc81e, 0x21, 0 + .dw 0xc640, 0xc81e, 0xc67f, 0xc81e, 0x21, 0 + .dw 0xc6c0, 0xc81e, 0xc6ff, 0xc81e, 0x21, 0 + .dw 0xc740, 0xc81e, 0xc77f, 0xc81e, 0x21, 0 + .dw 0xc7c0, 0xc81e, 0xc7ff, 0xc81e, 0x21, 0 + .dw 0xc840, 0xc81e, 0xc87f, 0xc81e, 0x21, 0 + .dw 0xc8c0, 0xc81e, 0xc8ff, 0xc81e, 0x21, 0 + .dw 0xc940, 0xc81e, 0xc97f, 0xc81e, 0x21, 0 + .dw 0xc9c0, 0xc81e, 0xc9ff, 0xc81e, 0x21, 0 + .dw 0xca40, 0xc81e, 0xca7f, 0xc81e, 0x21, 0 + .dw 0xcac0, 0xc81e, 0xcaff, 0xc81e, 0x21, 0 + .dw 0xcb40, 0xc81e, 0xcb7f, 0xc81e, 0x21, 0 + .dw 0xcbc0, 0xc81e, 0xcbff, 0xc81e, 0x21, 0 + .dw 0xcc40, 0xc81e, 0xcc7f, 0xc81e, 0x21, 0 + .dw 0xccc0, 0xc81e, 0xccff, 0xc81e, 0x21, 0 + .dw 0xcd40, 0xc81e, 0xcd7f, 0xc81e, 0x21, 0 + .dw 0xcdc0, 0xc81e, 0xcdff, 0xc81e, 0x21, 0 + .dw 0xce40, 0xc81e, 0xce7f, 0xc81e, 0x21, 0 + .dw 0xcec0, 0xc81e, 0xceff, 0xc81e, 0x21, 0 + .dw 0xcf40, 0xc81e, 0xcf7f, 0xc81e, 0x21, 0 + .dw 0xcfc0, 0xc81e, 0xcfff, 0xc81e, 0x21, 0 + .dw 0xd040, 0xc81e, 0xd07f, 0xc81e, 0x21, 0 + .dw 0xd0c0, 0xc81e, 0xd0ff, 0xc81e, 0x21, 0 + .dw 0xd140, 0xc81e, 0xd17f, 0xc81e, 0x21, 0 + .dw 0xd1c0, 0xc81e, 0xd1ff, 0xc81e, 0x21, 0 + .dw 0xd240, 0xc81e, 0xd27f, 0xc81e, 0x21, 0 + .dw 0xd2c0, 0xc81e, 0xd2ff, 0xc81e, 0x21, 0 + .dw 0xd340, 0xc81e, 0xd37f, 0xc81e, 0x21, 0 + .dw 0xd3c0, 0xc81e, 0xd3ff, 0xc81e, 0x21, 0 + .dw 0xd440, 0xc81e, 0xd47f, 0xc81e, 0x21, 0 + .dw 0xd4c0, 0xc81e, 0xd4ff, 0xc81e, 0x21, 0 + .dw 0xd540, 0xc81e, 0xd57f, 0xc81e, 0x21, 0 + .dw 0xd5c0, 0xc81e, 0xd5ff, 0xc81e, 0x21, 0 + .dw 0xd640, 0xc81e, 0xd67f, 0xc81e, 0x21, 0 + .dw 0xd6c0, 0xc81e, 0xd6ff, 0xc81e, 0x21, 0 + .dw 0xd740, 0xc81e, 0xd77f, 0xc81e, 0x21, 0 + .dw 0xd7c0, 0xc81e, 0xd7ff, 0xc81e, 0x21, 0 + .dw 0xd840, 0xc81e, 0xd87f, 0xc81e, 0x21, 0 + .dw 0xd8c0, 0xc81e, 0xd8ff, 0xc81e, 0x21, 0 + .dw 0xd940, 0xc81e, 0xd97f, 0xc81e, 0x21, 0 + .dw 0xd9c0, 0xc81e, 0xdfff, 0xc81e, 0x21, 0 + .dw 0xe040, 0xc81e, 0xe07f, 0xc81e, 0x21, 0 + .dw 0xe0c0, 0xc81e, 0xe0ff, 0xc81e, 0x21, 0 + .dw 0xe140, 0xc81e, 0xe17f, 0xc81e, 0x21, 0 + .dw 0xe1c0, 0xc81e, 0xe1ff, 0xc81e, 0x21, 0 + .dw 0xe240, 0xc81e, 0xe27f, 0xc81e, 0x21, 0 + .dw 0xe2c0, 0xc81e, 0xe2ff, 0xc81e, 0x21, 0 + .dw 0xe340, 0xc81e, 0xe37f, 0xc81e, 0x21, 0 + .dw 0xe3c0, 0xc81e, 0xe3ff, 0xc81e, 0x21, 0 + .dw 0xe440, 0xc81e, 0xe47f, 0xc81e, 0x21, 0 + .dw 0xe4c0, 0xc81e, 0xe4ff, 0xc81e, 0x21, 0 + .dw 0xe540, 0xc81e, 0xe57f, 0xc81e, 0x21, 0 + .dw 0xe5c0, 0xc81e, 0xe5ff, 0xc81e, 0x21, 0 + .dw 0xe640, 0xc81e, 0xe67f, 0xc81e, 0x21, 0 + .dw 0xe6c0, 0xc81e, 0xe6ff, 0xc81e, 0x21, 0 + .dw 0xe740, 0xc81e, 0xe77f, 0xc81e, 0x21, 0 + .dw 0xe7c0, 0xc81e, 0xe7ff, 0xc81e, 0x21, 0 + .dw 0xe840, 0xc81e, 0xe87f, 0xc81e, 0x21, 0 + .dw 0xe8c0, 0xc81e, 0xe8ff, 0xc81e, 0x21, 0 + .dw 0xe940, 0xc81e, 0xe97f, 0xc81e, 0x21, 0 + .dw 0xe9c0, 0xc81e, 0xe9ff, 0xc81e, 0x21, 0 + .dw 0xea40, 0xc81e, 0xea7f, 0xc81e, 0x21, 0 + .dw 0xeac0, 0xc81e, 0xeaff, 0xc81e, 0x21, 0 + .dw 0xeb40, 0xc81e, 0xeb7f, 0xc81e, 0x21, 0 + .dw 0xebc0, 0xc81e, 0xebff, 0xc81e, 0x21, 0 + .dw 0xec40, 0xc81e, 0xec7f, 0xc81e, 0x21, 0 + .dw 0xecc0, 0xc81e, 0xecff, 0xc81e, 0x21, 0 + .dw 0xed40, 0xc81e, 0xed7f, 0xc81e, 0x21, 0 + .dw 0xedc0, 0xc81e, 0xedff, 0xc81e, 0x21, 0 + .dw 0xee40, 0xc81e, 0xee7f, 0xc81e, 0x21, 0 + .dw 0xeec0, 0xc81e, 0xeeff, 0xc81e, 0x21, 0 + .dw 0xef40, 0xc81e, 0xef7f, 0xc81e, 0x21, 0 + .dw 0xefc0, 0xc81e, 0xefff, 0xc81e, 0x21, 0 + .dw 0xf040, 0xc81e, 0xf07f, 0xc81e, 0x21, 0 + .dw 0xf0c0, 0xc81e, 0xf0ff, 0xc81e, 0x21, 0 + .dw 0xf140, 0xc81e, 0xf17f, 0xc81e, 0x21, 0 + .dw 0xf1c0, 0xc81e, 0xf1ff, 0xc81e, 0x21, 0 + .dw 0xf240, 0xc81e, 0xf27f, 0xc81e, 0x21, 0 + .dw 0xf2c0, 0xc81e, 0xf2ff, 0xc81e, 0x21, 0 + .dw 0xf340, 0xc81e, 0xf37f, 0xc81e, 0x21, 0 + .dw 0xf3c0, 0xc81e, 0xf3ff, 0xc81e, 0x21, 0 + .dw 0xf440, 0xc81e, 0xf47f, 0xc81e, 0x21, 0 + .dw 0xf4c0, 0xc81e, 0xf4ff, 0xc81e, 0x21, 0 + .dw 0xf540, 0xc81e, 0xf57f, 0xc81e, 0x21, 0 + .dw 0xf5c0, 0xc81e, 0xf5ff, 0xc81e, 0x21, 0 + .dw 0xf640, 0xc81e, 0xf67f, 0xc81e, 0x21, 0 + .dw 0xf6c0, 0xc81e, 0xf6ff, 0xc81e, 0x21, 0 + .dw 0xf740, 0xc81e, 0xf77f, 0xc81e, 0x21, 0 + .dw 0xf7c0, 0xc81e, 0xf7ff, 0xc81e, 0x21, 0 + .dw 0xf840, 0xc81e, 0xf87f, 0xc81e, 0x21, 0 + .dw 0xf8c0, 0xc81e, 0xf8ff, 0xc81e, 0x21, 0 + .dw 0xf940, 0xc81e, 0xf97f, 0xc81e, 0x21, 0 + .dw 0xf9c0, 0xc81e, 0xffff, 0xc81e, 0x21, 0 + .dw 0x0040, 0xc81f, 0x007f, 0xc81f, 0x21, 0 + .dw 0x00c0, 0xc81f, 0x00ff, 0xc81f, 0x21, 0 + .dw 0x0140, 0xc81f, 0x017f, 0xc81f, 0x21, 0 + .dw 0x01c0, 0xc81f, 0x01ff, 0xc81f, 0x21, 0 + .dw 0x0240, 0xc81f, 0x027f, 0xc81f, 0x21, 0 + .dw 0x02c0, 0xc81f, 0x02ff, 0xc81f, 0x21, 0 + .dw 0x0340, 0xc81f, 0x037f, 0xc81f, 0x21, 0 + .dw 0x03c0, 0xc81f, 0x03ff, 0xc81f, 0x21, 0 + .dw 0x0440, 0xc81f, 0x047f, 0xc81f, 0x21, 0 + .dw 0x04c0, 0xc81f, 0x04ff, 0xc81f, 0x21, 0 + .dw 0x0540, 0xc81f, 0x057f, 0xc81f, 0x21, 0 + .dw 0x05c0, 0xc81f, 0x05ff, 0xc81f, 0x21, 0 + .dw 0x0640, 0xc81f, 0x067f, 0xc81f, 0x21, 0 + .dw 0x06c0, 0xc81f, 0x06ff, 0xc81f, 0x21, 0 + .dw 0x0740, 0xc81f, 0x077f, 0xc81f, 0x21, 0 + .dw 0x07c0, 0xc81f, 0x07ff, 0xc81f, 0x21, 0 + .dw 0x0840, 0xc81f, 0x087f, 0xc81f, 0x21, 0 + .dw 0x08c0, 0xc81f, 0x08ff, 0xc81f, 0x21, 0 + .dw 0x0940, 0xc81f, 0x097f, 0xc81f, 0x21, 0 + .dw 0x09c0, 0xc81f, 0x09ff, 0xc81f, 0x21, 0 + .dw 0x0a40, 0xc81f, 0x0a7f, 0xc81f, 0x21, 0 + .dw 0x0ac0, 0xc81f, 0x0aff, 0xc81f, 0x21, 0 + .dw 0x0b40, 0xc81f, 0x0b7f, 0xc81f, 0x21, 0 + .dw 0x0bc0, 0xc81f, 0x0bff, 0xc81f, 0x21, 0 + .dw 0x0c40, 0xc81f, 0x0c7f, 0xc81f, 0x21, 0 + .dw 0x0cc0, 0xc81f, 0x0cff, 0xc81f, 0x21, 0 + .dw 0x0d40, 0xc81f, 0x0d7f, 0xc81f, 0x21, 0 + .dw 0x0dc0, 0xc81f, 0x0dff, 0xc81f, 0x21, 0 + .dw 0x0e40, 0xc81f, 0x0e7f, 0xc81f, 0x21, 0 + .dw 0x0ec0, 0xc81f, 0x0eff, 0xc81f, 0x21, 0 + .dw 0x0f40, 0xc81f, 0x0f7f, 0xc81f, 0x21, 0 + .dw 0x0fc0, 0xc81f, 0x0fff, 0xc81f, 0x21, 0 + .dw 0x1040, 0xc81f, 0x107f, 0xc81f, 0x21, 0 + .dw 0x10c0, 0xc81f, 0x10ff, 0xc81f, 0x21, 0 + .dw 0x1140, 0xc81f, 0x117f, 0xc81f, 0x21, 0 + .dw 0x11c0, 0xc81f, 0x11ff, 0xc81f, 0x21, 0 + .dw 0x1240, 0xc81f, 0x127f, 0xc81f, 0x21, 0 + .dw 0x12c0, 0xc81f, 0x12ff, 0xc81f, 0x21, 0 + .dw 0x1340, 0xc81f, 0x137f, 0xc81f, 0x21, 0 + .dw 0x13c0, 0xc81f, 0x13ff, 0xc81f, 0x21, 0 + .dw 0x1440, 0xc81f, 0x147f, 0xc81f, 0x21, 0 + .dw 0x14c0, 0xc81f, 0x14ff, 0xc81f, 0x21, 0 + .dw 0x1540, 0xc81f, 0x157f, 0xc81f, 0x21, 0 + .dw 0x15c0, 0xc81f, 0x15ff, 0xc81f, 0x21, 0 + .dw 0x1640, 0xc81f, 0x167f, 0xc81f, 0x21, 0 + .dw 0x16c0, 0xc81f, 0x16ff, 0xc81f, 0x21, 0 + .dw 0x1740, 0xc81f, 0x177f, 0xc81f, 0x21, 0 + .dw 0x17c0, 0xc81f, 0x17ff, 0xc81f, 0x21, 0 + .dw 0x1840, 0xc81f, 0x187f, 0xc81f, 0x21, 0 + .dw 0x18c0, 0xc81f, 0x18ff, 0xc81f, 0x21, 0 + .dw 0x1940, 0xc81f, 0x197f, 0xc81f, 0x21, 0 + .dw 0x19c0, 0xc81f, 0x1fff, 0xc81f, 0x21, 0 + .dw 0x2040, 0xc81f, 0x207f, 0xc81f, 0x21, 0 + .dw 0x20c0, 0xc81f, 0x20ff, 0xc81f, 0x21, 0 + .dw 0x2140, 0xc81f, 0x217f, 0xc81f, 0x21, 0 + .dw 0x21c0, 0xc81f, 0x21ff, 0xc81f, 0x21, 0 + .dw 0x2240, 0xc81f, 0x227f, 0xc81f, 0x21, 0 + .dw 0x22c0, 0xc81f, 0x22ff, 0xc81f, 0x21, 0 + .dw 0x2340, 0xc81f, 0x237f, 0xc81f, 0x21, 0 + .dw 0x23c0, 0xc81f, 0x23ff, 0xc81f, 0x21, 0 + .dw 0x2440, 0xc81f, 0x247f, 0xc81f, 0x21, 0 + .dw 0x24c0, 0xc81f, 0x24ff, 0xc81f, 0x21, 0 + .dw 0x2540, 0xc81f, 0x257f, 0xc81f, 0x21, 0 + .dw 0x25c0, 0xc81f, 0x25ff, 0xc81f, 0x21, 0 + .dw 0x2640, 0xc81f, 0x267f, 0xc81f, 0x21, 0 + .dw 0x26c0, 0xc81f, 0x26ff, 0xc81f, 0x21, 0 + .dw 0x2740, 0xc81f, 0x277f, 0xc81f, 0x21, 0 + .dw 0x27c0, 0xc81f, 0x27ff, 0xc81f, 0x21, 0 + .dw 0x2840, 0xc81f, 0x287f, 0xc81f, 0x21, 0 + .dw 0x28c0, 0xc81f, 0x28ff, 0xc81f, 0x21, 0 + .dw 0x2940, 0xc81f, 0x297f, 0xc81f, 0x21, 0 + .dw 0x29c0, 0xc81f, 0x29ff, 0xc81f, 0x21, 0 + .dw 0x2a40, 0xc81f, 0x2a7f, 0xc81f, 0x21, 0 + .dw 0x2ac0, 0xc81f, 0x2aff, 0xc81f, 0x21, 0 + .dw 0x2b40, 0xc81f, 0x2b7f, 0xc81f, 0x21, 0 + .dw 0x2bc0, 0xc81f, 0x2bff, 0xc81f, 0x21, 0 + .dw 0x2c40, 0xc81f, 0x2c7f, 0xc81f, 0x21, 0 + .dw 0x2cc0, 0xc81f, 0x2cff, 0xc81f, 0x21, 0 + .dw 0x2d40, 0xc81f, 0x2d7f, 0xc81f, 0x21, 0 + .dw 0x2dc0, 0xc81f, 0x2dff, 0xc81f, 0x21, 0 + .dw 0x2e40, 0xc81f, 0x2e7f, 0xc81f, 0x21, 0 + .dw 0x2ec0, 0xc81f, 0x2eff, 0xc81f, 0x21, 0 + .dw 0x2f40, 0xc81f, 0x2f7f, 0xc81f, 0x21, 0 + .dw 0x2fc0, 0xc81f, 0x2fff, 0xc81f, 0x21, 0 + .dw 0x3040, 0xc81f, 0x307f, 0xc81f, 0x21, 0 + .dw 0x30c0, 0xc81f, 0x30ff, 0xc81f, 0x21, 0 + .dw 0x3140, 0xc81f, 0x317f, 0xc81f, 0x21, 0 + .dw 0x31c0, 0xc81f, 0x31ff, 0xc81f, 0x21, 0 + .dw 0x3240, 0xc81f, 0x327f, 0xc81f, 0x21, 0 + .dw 0x32c0, 0xc81f, 0x32ff, 0xc81f, 0x21, 0 + .dw 0x3340, 0xc81f, 0x337f, 0xc81f, 0x21, 0 + .dw 0x33c0, 0xc81f, 0x33ff, 0xc81f, 0x21, 0 + .dw 0x3440, 0xc81f, 0x347f, 0xc81f, 0x21, 0 + .dw 0x34c0, 0xc81f, 0x34ff, 0xc81f, 0x21, 0 + .dw 0x3540, 0xc81f, 0x357f, 0xc81f, 0x21, 0 + .dw 0x35c0, 0xc81f, 0x35ff, 0xc81f, 0x21, 0 + .dw 0x3640, 0xc81f, 0x367f, 0xc81f, 0x21, 0 + .dw 0x36c0, 0xc81f, 0x36ff, 0xc81f, 0x21, 0 + .dw 0x3740, 0xc81f, 0x377f, 0xc81f, 0x21, 0 + .dw 0x37c0, 0xc81f, 0x37ff, 0xc81f, 0x21, 0 + .dw 0x3840, 0xc81f, 0x387f, 0xc81f, 0x21, 0 + .dw 0x38c0, 0xc81f, 0x38ff, 0xc81f, 0x21, 0 + .dw 0x3940, 0xc81f, 0x397f, 0xc81f, 0x21, 0 + .dw 0x39c0, 0xc81f, 0x1fff, 0xc820, 0x21, 0 + .dw 0x3a00, 0xc820, 0x5fff, 0xc820, 0x21, 0 + .dw 0x7a00, 0xc820, 0x9fff, 0xc820, 0x21, 0 + .dw 0xba00, 0xc820, 0xdfff, 0xc820, 0x21, 0 + .dw 0xfa00, 0xc820, 0x1fff, 0xc821, 0x21, 0 + .dw 0x3a00, 0xc821, 0x5fff, 0xc821, 0x21, 0 + .dw 0x7a00, 0xc821, 0x9fff, 0xc821, 0x21, 0 + .dw 0xba00, 0xc821, 0xdfff, 0xc821, 0x21, 0 + .dw 0xfa00, 0xc821, 0x1fff, 0xc822, 0x21, 0 + .dw 0x3a00, 0xc822, 0x5fff, 0xc822, 0x21, 0 + .dw 0x7a00, 0xc822, 0x9fff, 0xc822, 0x21, 0 + .dw 0xba00, 0xc822, 0xdfff, 0xc822, 0x21, 0 + .dw 0xfa00, 0xc822, 0x1fff, 0xc823, 0x21, 0 + .dw 0x3a00, 0xc823, 0xffff, 0xc823, 0x21, 0 + .dw 0x1a00, 0xc824, 0x1fff, 0xc824, 0x21, 0 + .dw 0x3a00, 0xc824, 0x3fff, 0xc824, 0x21, 0 + .dw 0x5a00, 0xc824, 0x5fff, 0xc824, 0x21, 0 + .dw 0x7a00, 0xc824, 0x7fff, 0xc824, 0x21, 0 + .dw 0x9a00, 0xc824, 0x9fff, 0xc824, 0x21, 0 + .dw 0xba00, 0xc824, 0xbfff, 0xc824, 0x21, 0 + .dw 0xda00, 0xc824, 0xdfff, 0xc824, 0x21, 0 + .dw 0xfa00, 0xc824, 0xffff, 0xc824, 0x21, 0 + .dw 0x1a00, 0xc825, 0x1fff, 0xc825, 0x21, 0 + .dw 0x3a00, 0xc825, 0x3fff, 0xc825, 0x21, 0 + .dw 0x5a00, 0xc825, 0x5fff, 0xc825, 0x21, 0 + .dw 0x7a00, 0xc825, 0x7fff, 0xc825, 0x21, 0 + .dw 0x9a00, 0xc825, 0x9fff, 0xc825, 0x21, 0 + .dw 0xba00, 0xc825, 0xbfff, 0xc825, 0x21, 0 + .dw 0xda00, 0xc825, 0xdfff, 0xc825, 0x21, 0 + .dw 0xfa00, 0xc825, 0xffff, 0xc825, 0x21, 0 + .dw 0x1a00, 0xc826, 0x1fff, 0xc826, 0x21, 0 + .dw 0x3a00, 0xc826, 0x3fff, 0xc826, 0x21, 0 + .dw 0x5a00, 0xc826, 0x5fff, 0xc826, 0x21, 0 + .dw 0x7a00, 0xc826, 0x7fff, 0xc826, 0x21, 0 + .dw 0x9a00, 0xc826, 0x9fff, 0xc826, 0x21, 0 + .dw 0xba00, 0xc826, 0xbfff, 0xc826, 0x21, 0 + .dw 0xda00, 0xc826, 0xdfff, 0xc826, 0x21, 0 + .dw 0xfa00, 0xc826, 0xffff, 0xc826, 0x21, 0 + .dw 0x1a00, 0xc827, 0x1fff, 0xc827, 0x21, 0 + .dw 0x3a00, 0xc827, 0x1fff, 0xc828, 0x21, 0 + .dw 0x2040, 0xc828, 0x207f, 0xc828, 0x21, 0 + .dw 0x20c0, 0xc828, 0x20ff, 0xc828, 0x21, 0 + .dw 0x2140, 0xc828, 0x217f, 0xc828, 0x21, 0 + .dw 0x21c0, 0xc828, 0x21ff, 0xc828, 0x21, 0 + .dw 0x2240, 0xc828, 0x227f, 0xc828, 0x21, 0 + .dw 0x22c0, 0xc828, 0x22ff, 0xc828, 0x21, 0 + .dw 0x2340, 0xc828, 0x237f, 0xc828, 0x21, 0 + .dw 0x23c0, 0xc828, 0x23ff, 0xc828, 0x21, 0 + .dw 0x2440, 0xc828, 0x247f, 0xc828, 0x21, 0 + .dw 0x24c0, 0xc828, 0x24ff, 0xc828, 0x21, 0 + .dw 0x2540, 0xc828, 0x257f, 0xc828, 0x21, 0 + .dw 0x25c0, 0xc828, 0x25ff, 0xc828, 0x21, 0 + .dw 0x2640, 0xc828, 0x267f, 0xc828, 0x21, 0 + .dw 0x26c0, 0xc828, 0x26ff, 0xc828, 0x21, 0 + .dw 0x2740, 0xc828, 0x277f, 0xc828, 0x21, 0 + .dw 0x27c0, 0xc828, 0x27ff, 0xc828, 0x21, 0 + .dw 0x2840, 0xc828, 0x287f, 0xc828, 0x21, 0 + .dw 0x28c0, 0xc828, 0x28ff, 0xc828, 0x21, 0 + .dw 0x2940, 0xc828, 0x297f, 0xc828, 0x21, 0 + .dw 0x29c0, 0xc828, 0x29ff, 0xc828, 0x21, 0 + .dw 0x2a40, 0xc828, 0x2a7f, 0xc828, 0x21, 0 + .dw 0x2ac0, 0xc828, 0x2aff, 0xc828, 0x21, 0 + .dw 0x2b40, 0xc828, 0x2b7f, 0xc828, 0x21, 0 + .dw 0x2bc0, 0xc828, 0x2bff, 0xc828, 0x21, 0 + .dw 0x2c40, 0xc828, 0x2c7f, 0xc828, 0x21, 0 + .dw 0x2cc0, 0xc828, 0x2cff, 0xc828, 0x21, 0 + .dw 0x2d40, 0xc828, 0x2d7f, 0xc828, 0x21, 0 + .dw 0x2dc0, 0xc828, 0x2dff, 0xc828, 0x21, 0 + .dw 0x2e40, 0xc828, 0x2e7f, 0xc828, 0x21, 0 + .dw 0x2ec0, 0xc828, 0x2eff, 0xc828, 0x21, 0 + .dw 0x2f40, 0xc828, 0x2f7f, 0xc828, 0x21, 0 + .dw 0x2fc0, 0xc828, 0x2fff, 0xc828, 0x21, 0 + .dw 0x3040, 0xc828, 0x307f, 0xc828, 0x21, 0 + .dw 0x30c0, 0xc828, 0x30ff, 0xc828, 0x21, 0 + .dw 0x3140, 0xc828, 0x317f, 0xc828, 0x21, 0 + .dw 0x31c0, 0xc828, 0x31ff, 0xc828, 0x21, 0 + .dw 0x3240, 0xc828, 0x327f, 0xc828, 0x21, 0 + .dw 0x32c0, 0xc828, 0x32ff, 0xc828, 0x21, 0 + .dw 0x3340, 0xc828, 0x337f, 0xc828, 0x21, 0 + .dw 0x33c0, 0xc828, 0x33ff, 0xc828, 0x21, 0 + .dw 0x3440, 0xc828, 0x347f, 0xc828, 0x21, 0 + .dw 0x34c0, 0xc828, 0x34ff, 0xc828, 0x21, 0 + .dw 0x3540, 0xc828, 0x357f, 0xc828, 0x21, 0 + .dw 0x35c0, 0xc828, 0x35ff, 0xc828, 0x21, 0 + .dw 0x3640, 0xc828, 0x367f, 0xc828, 0x21, 0 + .dw 0x36c0, 0xc828, 0x36ff, 0xc828, 0x21, 0 + .dw 0x3740, 0xc828, 0x377f, 0xc828, 0x21, 0 + .dw 0x37c0, 0xc828, 0x37ff, 0xc828, 0x21, 0 + .dw 0x3840, 0xc828, 0x387f, 0xc828, 0x21, 0 + .dw 0x38c0, 0xc828, 0x38ff, 0xc828, 0x21, 0 + .dw 0x3940, 0xc828, 0x397f, 0xc828, 0x21, 0 + .dw 0x39c0, 0xc828, 0x5fff, 0xc828, 0x21, 0 + .dw 0x6040, 0xc828, 0x607f, 0xc828, 0x21, 0 + .dw 0x60c0, 0xc828, 0x60ff, 0xc828, 0x21, 0 + .dw 0x6140, 0xc828, 0x617f, 0xc828, 0x21, 0 + .dw 0x61c0, 0xc828, 0x61ff, 0xc828, 0x21, 0 + .dw 0x6240, 0xc828, 0x627f, 0xc828, 0x21, 0 + .dw 0x62c0, 0xc828, 0x62ff, 0xc828, 0x21, 0 + .dw 0x6340, 0xc828, 0x637f, 0xc828, 0x21, 0 + .dw 0x63c0, 0xc828, 0x63ff, 0xc828, 0x21, 0 + .dw 0x6440, 0xc828, 0x647f, 0xc828, 0x21, 0 + .dw 0x64c0, 0xc828, 0x64ff, 0xc828, 0x21, 0 + .dw 0x6540, 0xc828, 0x657f, 0xc828, 0x21, 0 + .dw 0x65c0, 0xc828, 0x65ff, 0xc828, 0x21, 0 + .dw 0x6640, 0xc828, 0x667f, 0xc828, 0x21, 0 + .dw 0x66c0, 0xc828, 0x66ff, 0xc828, 0x21, 0 + .dw 0x6740, 0xc828, 0x677f, 0xc828, 0x21, 0 + .dw 0x67c0, 0xc828, 0x67ff, 0xc828, 0x21, 0 + .dw 0x6840, 0xc828, 0x687f, 0xc828, 0x21, 0 + .dw 0x68c0, 0xc828, 0x68ff, 0xc828, 0x21, 0 + .dw 0x6940, 0xc828, 0x697f, 0xc828, 0x21, 0 + .dw 0x69c0, 0xc828, 0x69ff, 0xc828, 0x21, 0 + .dw 0x6a40, 0xc828, 0x6a7f, 0xc828, 0x21, 0 + .dw 0x6ac0, 0xc828, 0x6aff, 0xc828, 0x21, 0 + .dw 0x6b40, 0xc828, 0x6b7f, 0xc828, 0x21, 0 + .dw 0x6bc0, 0xc828, 0x6bff, 0xc828, 0x21, 0 + .dw 0x6c40, 0xc828, 0x6c7f, 0xc828, 0x21, 0 + .dw 0x6cc0, 0xc828, 0x6cff, 0xc828, 0x21, 0 + .dw 0x6d40, 0xc828, 0x6d7f, 0xc828, 0x21, 0 + .dw 0x6dc0, 0xc828, 0x6dff, 0xc828, 0x21, 0 + .dw 0x6e40, 0xc828, 0x6e7f, 0xc828, 0x21, 0 + .dw 0x6ec0, 0xc828, 0x6eff, 0xc828, 0x21, 0 + .dw 0x6f40, 0xc828, 0x6f7f, 0xc828, 0x21, 0 + .dw 0x6fc0, 0xc828, 0x6fff, 0xc828, 0x21, 0 + .dw 0x7040, 0xc828, 0x707f, 0xc828, 0x21, 0 + .dw 0x70c0, 0xc828, 0x70ff, 0xc828, 0x21, 0 + .dw 0x7140, 0xc828, 0x717f, 0xc828, 0x21, 0 + .dw 0x71c0, 0xc828, 0x71ff, 0xc828, 0x21, 0 + .dw 0x7240, 0xc828, 0x727f, 0xc828, 0x21, 0 + .dw 0x72c0, 0xc828, 0x72ff, 0xc828, 0x21, 0 + .dw 0x7340, 0xc828, 0x737f, 0xc828, 0x21, 0 + .dw 0x73c0, 0xc828, 0x73ff, 0xc828, 0x21, 0 + .dw 0x7440, 0xc828, 0x747f, 0xc828, 0x21, 0 + .dw 0x74c0, 0xc828, 0x74ff, 0xc828, 0x21, 0 + .dw 0x7540, 0xc828, 0x757f, 0xc828, 0x21, 0 + .dw 0x75c0, 0xc828, 0x75ff, 0xc828, 0x21, 0 + .dw 0x7640, 0xc828, 0x767f, 0xc828, 0x21, 0 + .dw 0x76c0, 0xc828, 0x76ff, 0xc828, 0x21, 0 + .dw 0x7740, 0xc828, 0x777f, 0xc828, 0x21, 0 + .dw 0x77c0, 0xc828, 0x77ff, 0xc828, 0x21, 0 + .dw 0x7840, 0xc828, 0x787f, 0xc828, 0x21, 0 + .dw 0x78c0, 0xc828, 0x78ff, 0xc828, 0x21, 0 + .dw 0x7940, 0xc828, 0x797f, 0xc828, 0x21, 0 + .dw 0x79c0, 0xc828, 0x9fff, 0xc828, 0x21, 0 + .dw 0xa040, 0xc828, 0xa07f, 0xc828, 0x21, 0 + .dw 0xa0c0, 0xc828, 0xa0ff, 0xc828, 0x21, 0 + .dw 0xa140, 0xc828, 0xa17f, 0xc828, 0x21, 0 + .dw 0xa1c0, 0xc828, 0xa1ff, 0xc828, 0x21, 0 + .dw 0xa240, 0xc828, 0xa27f, 0xc828, 0x21, 0 + .dw 0xa2c0, 0xc828, 0xa2ff, 0xc828, 0x21, 0 + .dw 0xa340, 0xc828, 0xa37f, 0xc828, 0x21, 0 + .dw 0xa3c0, 0xc828, 0xa3ff, 0xc828, 0x21, 0 + .dw 0xa440, 0xc828, 0xa47f, 0xc828, 0x21, 0 + .dw 0xa4c0, 0xc828, 0xa4ff, 0xc828, 0x21, 0 + .dw 0xa540, 0xc828, 0xa57f, 0xc828, 0x21, 0 + .dw 0xa5c0, 0xc828, 0xa5ff, 0xc828, 0x21, 0 + .dw 0xa640, 0xc828, 0xa67f, 0xc828, 0x21, 0 + .dw 0xa6c0, 0xc828, 0xa6ff, 0xc828, 0x21, 0 + .dw 0xa740, 0xc828, 0xa77f, 0xc828, 0x21, 0 + .dw 0xa7c0, 0xc828, 0xa7ff, 0xc828, 0x21, 0 + .dw 0xa840, 0xc828, 0xa87f, 0xc828, 0x21, 0 + .dw 0xa8c0, 0xc828, 0xa8ff, 0xc828, 0x21, 0 + .dw 0xa940, 0xc828, 0xa97f, 0xc828, 0x21, 0 + .dw 0xa9c0, 0xc828, 0xa9ff, 0xc828, 0x21, 0 + .dw 0xaa40, 0xc828, 0xaa7f, 0xc828, 0x21, 0 + .dw 0xaac0, 0xc828, 0xaaff, 0xc828, 0x21, 0 + .dw 0xab40, 0xc828, 0xab7f, 0xc828, 0x21, 0 + .dw 0xabc0, 0xc828, 0xabff, 0xc828, 0x21, 0 + .dw 0xac40, 0xc828, 0xac7f, 0xc828, 0x21, 0 + .dw 0xacc0, 0xc828, 0xacff, 0xc828, 0x21, 0 + .dw 0xad40, 0xc828, 0xad7f, 0xc828, 0x21, 0 + .dw 0xadc0, 0xc828, 0xadff, 0xc828, 0x21, 0 + .dw 0xae40, 0xc828, 0xae7f, 0xc828, 0x21, 0 + .dw 0xaec0, 0xc828, 0xaeff, 0xc828, 0x21, 0 + .dw 0xaf40, 0xc828, 0xaf7f, 0xc828, 0x21, 0 + .dw 0xafc0, 0xc828, 0xafff, 0xc828, 0x21, 0 + .dw 0xb040, 0xc828, 0xb07f, 0xc828, 0x21, 0 + .dw 0xb0c0, 0xc828, 0xb0ff, 0xc828, 0x21, 0 + .dw 0xb140, 0xc828, 0xb17f, 0xc828, 0x21, 0 + .dw 0xb1c0, 0xc828, 0xb1ff, 0xc828, 0x21, 0 + .dw 0xb240, 0xc828, 0xb27f, 0xc828, 0x21, 0 + .dw 0xb2c0, 0xc828, 0xb2ff, 0xc828, 0x21, 0 + .dw 0xb340, 0xc828, 0xb37f, 0xc828, 0x21, 0 + .dw 0xb3c0, 0xc828, 0xb3ff, 0xc828, 0x21, 0 + .dw 0xb440, 0xc828, 0xb47f, 0xc828, 0x21, 0 + .dw 0xb4c0, 0xc828, 0xb4ff, 0xc828, 0x21, 0 + .dw 0xb540, 0xc828, 0xb57f, 0xc828, 0x21, 0 + .dw 0xb5c0, 0xc828, 0xb5ff, 0xc828, 0x21, 0 + .dw 0xb640, 0xc828, 0xb67f, 0xc828, 0x21, 0 + .dw 0xb6c0, 0xc828, 0xb6ff, 0xc828, 0x21, 0 + .dw 0xb740, 0xc828, 0xb77f, 0xc828, 0x21, 0 + .dw 0xb7c0, 0xc828, 0xb7ff, 0xc828, 0x21, 0 + .dw 0xb840, 0xc828, 0xb87f, 0xc828, 0x21, 0 + .dw 0xb8c0, 0xc828, 0xb8ff, 0xc828, 0x21, 0 + .dw 0xb940, 0xc828, 0xb97f, 0xc828, 0x21, 0 + .dw 0xb9c0, 0xc828, 0xdfff, 0xc828, 0x21, 0 + .dw 0xe040, 0xc828, 0xe07f, 0xc828, 0x21, 0 + .dw 0xe0c0, 0xc828, 0xe0ff, 0xc828, 0x21, 0 + .dw 0xe140, 0xc828, 0xe17f, 0xc828, 0x21, 0 + .dw 0xe1c0, 0xc828, 0xe1ff, 0xc828, 0x21, 0 + .dw 0xe240, 0xc828, 0xe27f, 0xc828, 0x21, 0 + .dw 0xe2c0, 0xc828, 0xe2ff, 0xc828, 0x21, 0 + .dw 0xe340, 0xc828, 0xe37f, 0xc828, 0x21, 0 + .dw 0xe3c0, 0xc828, 0xe3ff, 0xc828, 0x21, 0 + .dw 0xe440, 0xc828, 0xe47f, 0xc828, 0x21, 0 + .dw 0xe4c0, 0xc828, 0xe4ff, 0xc828, 0x21, 0 + .dw 0xe540, 0xc828, 0xe57f, 0xc828, 0x21, 0 + .dw 0xe5c0, 0xc828, 0xe5ff, 0xc828, 0x21, 0 + .dw 0xe640, 0xc828, 0xe67f, 0xc828, 0x21, 0 + .dw 0xe6c0, 0xc828, 0xe6ff, 0xc828, 0x21, 0 + .dw 0xe740, 0xc828, 0xe77f, 0xc828, 0x21, 0 + .dw 0xe7c0, 0xc828, 0xe7ff, 0xc828, 0x21, 0 + .dw 0xe840, 0xc828, 0xe87f, 0xc828, 0x21, 0 + .dw 0xe8c0, 0xc828, 0xe8ff, 0xc828, 0x21, 0 + .dw 0xe940, 0xc828, 0xe97f, 0xc828, 0x21, 0 + .dw 0xe9c0, 0xc828, 0xe9ff, 0xc828, 0x21, 0 + .dw 0xea40, 0xc828, 0xea7f, 0xc828, 0x21, 0 + .dw 0xeac0, 0xc828, 0xeaff, 0xc828, 0x21, 0 + .dw 0xeb40, 0xc828, 0xeb7f, 0xc828, 0x21, 0 + .dw 0xebc0, 0xc828, 0xebff, 0xc828, 0x21, 0 + .dw 0xec40, 0xc828, 0xec7f, 0xc828, 0x21, 0 + .dw 0xecc0, 0xc828, 0xecff, 0xc828, 0x21, 0 + .dw 0xed40, 0xc828, 0xed7f, 0xc828, 0x21, 0 + .dw 0xedc0, 0xc828, 0xedff, 0xc828, 0x21, 0 + .dw 0xee40, 0xc828, 0xee7f, 0xc828, 0x21, 0 + .dw 0xeec0, 0xc828, 0xeeff, 0xc828, 0x21, 0 + .dw 0xef40, 0xc828, 0xef7f, 0xc828, 0x21, 0 + .dw 0xefc0, 0xc828, 0xefff, 0xc828, 0x21, 0 + .dw 0xf040, 0xc828, 0xf07f, 0xc828, 0x21, 0 + .dw 0xf0c0, 0xc828, 0xf0ff, 0xc828, 0x21, 0 + .dw 0xf140, 0xc828, 0xf17f, 0xc828, 0x21, 0 + .dw 0xf1c0, 0xc828, 0xf1ff, 0xc828, 0x21, 0 + .dw 0xf240, 0xc828, 0xf27f, 0xc828, 0x21, 0 + .dw 0xf2c0, 0xc828, 0xf2ff, 0xc828, 0x21, 0 + .dw 0xf340, 0xc828, 0xf37f, 0xc828, 0x21, 0 + .dw 0xf3c0, 0xc828, 0xf3ff, 0xc828, 0x21, 0 + .dw 0xf440, 0xc828, 0xf47f, 0xc828, 0x21, 0 + .dw 0xf4c0, 0xc828, 0xf4ff, 0xc828, 0x21, 0 + .dw 0xf540, 0xc828, 0xf57f, 0xc828, 0x21, 0 + .dw 0xf5c0, 0xc828, 0xf5ff, 0xc828, 0x21, 0 + .dw 0xf640, 0xc828, 0xf67f, 0xc828, 0x21, 0 + .dw 0xf6c0, 0xc828, 0xf6ff, 0xc828, 0x21, 0 + .dw 0xf740, 0xc828, 0xf77f, 0xc828, 0x21, 0 + .dw 0xf7c0, 0xc828, 0xf7ff, 0xc828, 0x21, 0 + .dw 0xf840, 0xc828, 0xf87f, 0xc828, 0x21, 0 + .dw 0xf8c0, 0xc828, 0xf8ff, 0xc828, 0x21, 0 + .dw 0xf940, 0xc828, 0xf97f, 0xc828, 0x21, 0 + .dw 0xf9c0, 0xc828, 0x1fff, 0xc829, 0x21, 0 + .dw 0x2040, 0xc829, 0x207f, 0xc829, 0x21, 0 + .dw 0x20c0, 0xc829, 0x20ff, 0xc829, 0x21, 0 + .dw 0x2140, 0xc829, 0x217f, 0xc829, 0x21, 0 + .dw 0x21c0, 0xc829, 0x21ff, 0xc829, 0x21, 0 + .dw 0x2240, 0xc829, 0x227f, 0xc829, 0x21, 0 + .dw 0x22c0, 0xc829, 0x22ff, 0xc829, 0x21, 0 + .dw 0x2340, 0xc829, 0x237f, 0xc829, 0x21, 0 + .dw 0x23c0, 0xc829, 0x23ff, 0xc829, 0x21, 0 + .dw 0x2440, 0xc829, 0x247f, 0xc829, 0x21, 0 + .dw 0x24c0, 0xc829, 0x24ff, 0xc829, 0x21, 0 + .dw 0x2540, 0xc829, 0x257f, 0xc829, 0x21, 0 + .dw 0x25c0, 0xc829, 0x25ff, 0xc829, 0x21, 0 + .dw 0x2640, 0xc829, 0x267f, 0xc829, 0x21, 0 + .dw 0x26c0, 0xc829, 0x26ff, 0xc829, 0x21, 0 + .dw 0x2740, 0xc829, 0x277f, 0xc829, 0x21, 0 + .dw 0x27c0, 0xc829, 0x27ff, 0xc829, 0x21, 0 + .dw 0x2840, 0xc829, 0x287f, 0xc829, 0x21, 0 + .dw 0x28c0, 0xc829, 0x28ff, 0xc829, 0x21, 0 + .dw 0x2940, 0xc829, 0x297f, 0xc829, 0x21, 0 + .dw 0x29c0, 0xc829, 0x29ff, 0xc829, 0x21, 0 + .dw 0x2a40, 0xc829, 0x2a7f, 0xc829, 0x21, 0 + .dw 0x2ac0, 0xc829, 0x2aff, 0xc829, 0x21, 0 + .dw 0x2b40, 0xc829, 0x2b7f, 0xc829, 0x21, 0 + .dw 0x2bc0, 0xc829, 0x2bff, 0xc829, 0x21, 0 + .dw 0x2c40, 0xc829, 0x2c7f, 0xc829, 0x21, 0 + .dw 0x2cc0, 0xc829, 0x2cff, 0xc829, 0x21, 0 + .dw 0x2d40, 0xc829, 0x2d7f, 0xc829, 0x21, 0 + .dw 0x2dc0, 0xc829, 0x2dff, 0xc829, 0x21, 0 + .dw 0x2e40, 0xc829, 0x2e7f, 0xc829, 0x21, 0 + .dw 0x2ec0, 0xc829, 0x2eff, 0xc829, 0x21, 0 + .dw 0x2f40, 0xc829, 0x2f7f, 0xc829, 0x21, 0 + .dw 0x2fc0, 0xc829, 0x2fff, 0xc829, 0x21, 0 + .dw 0x3040, 0xc829, 0x307f, 0xc829, 0x21, 0 + .dw 0x30c0, 0xc829, 0x30ff, 0xc829, 0x21, 0 + .dw 0x3140, 0xc829, 0x317f, 0xc829, 0x21, 0 + .dw 0x31c0, 0xc829, 0x31ff, 0xc829, 0x21, 0 + .dw 0x3240, 0xc829, 0x327f, 0xc829, 0x21, 0 + .dw 0x32c0, 0xc829, 0x32ff, 0xc829, 0x21, 0 + .dw 0x3340, 0xc829, 0x337f, 0xc829, 0x21, 0 + .dw 0x33c0, 0xc829, 0x33ff, 0xc829, 0x21, 0 + .dw 0x3440, 0xc829, 0x347f, 0xc829, 0x21, 0 + .dw 0x34c0, 0xc829, 0x34ff, 0xc829, 0x21, 0 + .dw 0x3540, 0xc829, 0x357f, 0xc829, 0x21, 0 + .dw 0x35c0, 0xc829, 0x35ff, 0xc829, 0x21, 0 + .dw 0x3640, 0xc829, 0x367f, 0xc829, 0x21, 0 + .dw 0x36c0, 0xc829, 0x36ff, 0xc829, 0x21, 0 + .dw 0x3740, 0xc829, 0x377f, 0xc829, 0x21, 0 + .dw 0x37c0, 0xc829, 0x37ff, 0xc829, 0x21, 0 + .dw 0x3840, 0xc829, 0x387f, 0xc829, 0x21, 0 + .dw 0x38c0, 0xc829, 0x38ff, 0xc829, 0x21, 0 + .dw 0x3940, 0xc829, 0x397f, 0xc829, 0x21, 0 + .dw 0x39c0, 0xc829, 0x5fff, 0xc829, 0x21, 0 + .dw 0x6040, 0xc829, 0x607f, 0xc829, 0x21, 0 + .dw 0x60c0, 0xc829, 0x60ff, 0xc829, 0x21, 0 + .dw 0x6140, 0xc829, 0x617f, 0xc829, 0x21, 0 + .dw 0x61c0, 0xc829, 0x61ff, 0xc829, 0x21, 0 + .dw 0x6240, 0xc829, 0x627f, 0xc829, 0x21, 0 + .dw 0x62c0, 0xc829, 0x62ff, 0xc829, 0x21, 0 + .dw 0x6340, 0xc829, 0x637f, 0xc829, 0x21, 0 + .dw 0x63c0, 0xc829, 0x63ff, 0xc829, 0x21, 0 + .dw 0x6440, 0xc829, 0x647f, 0xc829, 0x21, 0 + .dw 0x64c0, 0xc829, 0x64ff, 0xc829, 0x21, 0 + .dw 0x6540, 0xc829, 0x657f, 0xc829, 0x21, 0 + .dw 0x65c0, 0xc829, 0x65ff, 0xc829, 0x21, 0 + .dw 0x6640, 0xc829, 0x667f, 0xc829, 0x21, 0 + .dw 0x66c0, 0xc829, 0x66ff, 0xc829, 0x21, 0 + .dw 0x6740, 0xc829, 0x677f, 0xc829, 0x21, 0 + .dw 0x67c0, 0xc829, 0x67ff, 0xc829, 0x21, 0 + .dw 0x6840, 0xc829, 0x687f, 0xc829, 0x21, 0 + .dw 0x68c0, 0xc829, 0x68ff, 0xc829, 0x21, 0 + .dw 0x6940, 0xc829, 0x697f, 0xc829, 0x21, 0 + .dw 0x69c0, 0xc829, 0x69ff, 0xc829, 0x21, 0 + .dw 0x6a40, 0xc829, 0x6a7f, 0xc829, 0x21, 0 + .dw 0x6ac0, 0xc829, 0x6aff, 0xc829, 0x21, 0 + .dw 0x6b40, 0xc829, 0x6b7f, 0xc829, 0x21, 0 + .dw 0x6bc0, 0xc829, 0x6bff, 0xc829, 0x21, 0 + .dw 0x6c40, 0xc829, 0x6c7f, 0xc829, 0x21, 0 + .dw 0x6cc0, 0xc829, 0x6cff, 0xc829, 0x21, 0 + .dw 0x6d40, 0xc829, 0x6d7f, 0xc829, 0x21, 0 + .dw 0x6dc0, 0xc829, 0x6dff, 0xc829, 0x21, 0 + .dw 0x6e40, 0xc829, 0x6e7f, 0xc829, 0x21, 0 + .dw 0x6ec0, 0xc829, 0x6eff, 0xc829, 0x21, 0 + .dw 0x6f40, 0xc829, 0x6f7f, 0xc829, 0x21, 0 + .dw 0x6fc0, 0xc829, 0x6fff, 0xc829, 0x21, 0 + .dw 0x7040, 0xc829, 0x707f, 0xc829, 0x21, 0 + .dw 0x70c0, 0xc829, 0x70ff, 0xc829, 0x21, 0 + .dw 0x7140, 0xc829, 0x717f, 0xc829, 0x21, 0 + .dw 0x71c0, 0xc829, 0x71ff, 0xc829, 0x21, 0 + .dw 0x7240, 0xc829, 0x727f, 0xc829, 0x21, 0 + .dw 0x72c0, 0xc829, 0x72ff, 0xc829, 0x21, 0 + .dw 0x7340, 0xc829, 0x737f, 0xc829, 0x21, 0 + .dw 0x73c0, 0xc829, 0x73ff, 0xc829, 0x21, 0 + .dw 0x7440, 0xc829, 0x747f, 0xc829, 0x21, 0 + .dw 0x74c0, 0xc829, 0x74ff, 0xc829, 0x21, 0 + .dw 0x7540, 0xc829, 0x757f, 0xc829, 0x21, 0 + .dw 0x75c0, 0xc829, 0x75ff, 0xc829, 0x21, 0 + .dw 0x7640, 0xc829, 0x767f, 0xc829, 0x21, 0 + .dw 0x76c0, 0xc829, 0x76ff, 0xc829, 0x21, 0 + .dw 0x7740, 0xc829, 0x777f, 0xc829, 0x21, 0 + .dw 0x77c0, 0xc829, 0x77ff, 0xc829, 0x21, 0 + .dw 0x7840, 0xc829, 0x787f, 0xc829, 0x21, 0 + .dw 0x78c0, 0xc829, 0x78ff, 0xc829, 0x21, 0 + .dw 0x7940, 0xc829, 0x797f, 0xc829, 0x21, 0 + .dw 0x79c0, 0xc829, 0x9fff, 0xc829, 0x21, 0 + .dw 0xa040, 0xc829, 0xa07f, 0xc829, 0x21, 0 + .dw 0xa0c0, 0xc829, 0xa0ff, 0xc829, 0x21, 0 + .dw 0xa140, 0xc829, 0xa17f, 0xc829, 0x21, 0 + .dw 0xa1c0, 0xc829, 0xa1ff, 0xc829, 0x21, 0 + .dw 0xa240, 0xc829, 0xa27f, 0xc829, 0x21, 0 + .dw 0xa2c0, 0xc829, 0xa2ff, 0xc829, 0x21, 0 + .dw 0xa340, 0xc829, 0xa37f, 0xc829, 0x21, 0 + .dw 0xa3c0, 0xc829, 0xa3ff, 0xc829, 0x21, 0 + .dw 0xa440, 0xc829, 0xa47f, 0xc829, 0x21, 0 + .dw 0xa4c0, 0xc829, 0xa4ff, 0xc829, 0x21, 0 + .dw 0xa540, 0xc829, 0xa57f, 0xc829, 0x21, 0 + .dw 0xa5c0, 0xc829, 0xa5ff, 0xc829, 0x21, 0 + .dw 0xa640, 0xc829, 0xa67f, 0xc829, 0x21, 0 + .dw 0xa6c0, 0xc829, 0xa6ff, 0xc829, 0x21, 0 + .dw 0xa740, 0xc829, 0xa77f, 0xc829, 0x21, 0 + .dw 0xa7c0, 0xc829, 0xa7ff, 0xc829, 0x21, 0 + .dw 0xa840, 0xc829, 0xa87f, 0xc829, 0x21, 0 + .dw 0xa8c0, 0xc829, 0xa8ff, 0xc829, 0x21, 0 + .dw 0xa940, 0xc829, 0xa97f, 0xc829, 0x21, 0 + .dw 0xa9c0, 0xc829, 0xa9ff, 0xc829, 0x21, 0 + .dw 0xaa40, 0xc829, 0xaa7f, 0xc829, 0x21, 0 + .dw 0xaac0, 0xc829, 0xaaff, 0xc829, 0x21, 0 + .dw 0xab40, 0xc829, 0xab7f, 0xc829, 0x21, 0 + .dw 0xabc0, 0xc829, 0xabff, 0xc829, 0x21, 0 + .dw 0xac40, 0xc829, 0xac7f, 0xc829, 0x21, 0 + .dw 0xacc0, 0xc829, 0xacff, 0xc829, 0x21, 0 + .dw 0xad40, 0xc829, 0xad7f, 0xc829, 0x21, 0 + .dw 0xadc0, 0xc829, 0xadff, 0xc829, 0x21, 0 + .dw 0xae40, 0xc829, 0xae7f, 0xc829, 0x21, 0 + .dw 0xaec0, 0xc829, 0xaeff, 0xc829, 0x21, 0 + .dw 0xaf40, 0xc829, 0xaf7f, 0xc829, 0x21, 0 + .dw 0xafc0, 0xc829, 0xafff, 0xc829, 0x21, 0 + .dw 0xb040, 0xc829, 0xb07f, 0xc829, 0x21, 0 + .dw 0xb0c0, 0xc829, 0xb0ff, 0xc829, 0x21, 0 + .dw 0xb140, 0xc829, 0xb17f, 0xc829, 0x21, 0 + .dw 0xb1c0, 0xc829, 0xb1ff, 0xc829, 0x21, 0 + .dw 0xb240, 0xc829, 0xb27f, 0xc829, 0x21, 0 + .dw 0xb2c0, 0xc829, 0xb2ff, 0xc829, 0x21, 0 + .dw 0xb340, 0xc829, 0xb37f, 0xc829, 0x21, 0 + .dw 0xb3c0, 0xc829, 0xb3ff, 0xc829, 0x21, 0 + .dw 0xb440, 0xc829, 0xb47f, 0xc829, 0x21, 0 + .dw 0xb4c0, 0xc829, 0xb4ff, 0xc829, 0x21, 0 + .dw 0xb540, 0xc829, 0xb57f, 0xc829, 0x21, 0 + .dw 0xb5c0, 0xc829, 0xb5ff, 0xc829, 0x21, 0 + .dw 0xb640, 0xc829, 0xb67f, 0xc829, 0x21, 0 + .dw 0xb6c0, 0xc829, 0xb6ff, 0xc829, 0x21, 0 + .dw 0xb740, 0xc829, 0xb77f, 0xc829, 0x21, 0 + .dw 0xb7c0, 0xc829, 0xb7ff, 0xc829, 0x21, 0 + .dw 0xb840, 0xc829, 0xb87f, 0xc829, 0x21, 0 + .dw 0xb8c0, 0xc829, 0xb8ff, 0xc829, 0x21, 0 + .dw 0xb940, 0xc829, 0xb97f, 0xc829, 0x21, 0 + .dw 0xb9c0, 0xc829, 0xdfff, 0xc829, 0x21, 0 + .dw 0xe040, 0xc829, 0xe07f, 0xc829, 0x21, 0 + .dw 0xe0c0, 0xc829, 0xe0ff, 0xc829, 0x21, 0 + .dw 0xe140, 0xc829, 0xe17f, 0xc829, 0x21, 0 + .dw 0xe1c0, 0xc829, 0xe1ff, 0xc829, 0x21, 0 + .dw 0xe240, 0xc829, 0xe27f, 0xc829, 0x21, 0 + .dw 0xe2c0, 0xc829, 0xe2ff, 0xc829, 0x21, 0 + .dw 0xe340, 0xc829, 0xe37f, 0xc829, 0x21, 0 + .dw 0xe3c0, 0xc829, 0xe3ff, 0xc829, 0x21, 0 + .dw 0xe440, 0xc829, 0xe47f, 0xc829, 0x21, 0 + .dw 0xe4c0, 0xc829, 0xe4ff, 0xc829, 0x21, 0 + .dw 0xe540, 0xc829, 0xe57f, 0xc829, 0x21, 0 + .dw 0xe5c0, 0xc829, 0xe5ff, 0xc829, 0x21, 0 + .dw 0xe640, 0xc829, 0xe67f, 0xc829, 0x21, 0 + .dw 0xe6c0, 0xc829, 0xe6ff, 0xc829, 0x21, 0 + .dw 0xe740, 0xc829, 0xe77f, 0xc829, 0x21, 0 + .dw 0xe7c0, 0xc829, 0xe7ff, 0xc829, 0x21, 0 + .dw 0xe840, 0xc829, 0xe87f, 0xc829, 0x21, 0 + .dw 0xe8c0, 0xc829, 0xe8ff, 0xc829, 0x21, 0 + .dw 0xe940, 0xc829, 0xe97f, 0xc829, 0x21, 0 + .dw 0xe9c0, 0xc829, 0xe9ff, 0xc829, 0x21, 0 + .dw 0xea40, 0xc829, 0xea7f, 0xc829, 0x21, 0 + .dw 0xeac0, 0xc829, 0xeaff, 0xc829, 0x21, 0 + .dw 0xeb40, 0xc829, 0xeb7f, 0xc829, 0x21, 0 + .dw 0xebc0, 0xc829, 0xebff, 0xc829, 0x21, 0 + .dw 0xec40, 0xc829, 0xec7f, 0xc829, 0x21, 0 + .dw 0xecc0, 0xc829, 0xecff, 0xc829, 0x21, 0 + .dw 0xed40, 0xc829, 0xed7f, 0xc829, 0x21, 0 + .dw 0xedc0, 0xc829, 0xedff, 0xc829, 0x21, 0 + .dw 0xee40, 0xc829, 0xee7f, 0xc829, 0x21, 0 + .dw 0xeec0, 0xc829, 0xeeff, 0xc829, 0x21, 0 + .dw 0xef40, 0xc829, 0xef7f, 0xc829, 0x21, 0 + .dw 0xefc0, 0xc829, 0xefff, 0xc829, 0x21, 0 + .dw 0xf040, 0xc829, 0xf07f, 0xc829, 0x21, 0 + .dw 0xf0c0, 0xc829, 0xf0ff, 0xc829, 0x21, 0 + .dw 0xf140, 0xc829, 0xf17f, 0xc829, 0x21, 0 + .dw 0xf1c0, 0xc829, 0xf1ff, 0xc829, 0x21, 0 + .dw 0xf240, 0xc829, 0xf27f, 0xc829, 0x21, 0 + .dw 0xf2c0, 0xc829, 0xf2ff, 0xc829, 0x21, 0 + .dw 0xf340, 0xc829, 0xf37f, 0xc829, 0x21, 0 + .dw 0xf3c0, 0xc829, 0xf3ff, 0xc829, 0x21, 0 + .dw 0xf440, 0xc829, 0xf47f, 0xc829, 0x21, 0 + .dw 0xf4c0, 0xc829, 0xf4ff, 0xc829, 0x21, 0 + .dw 0xf540, 0xc829, 0xf57f, 0xc829, 0x21, 0 + .dw 0xf5c0, 0xc829, 0xf5ff, 0xc829, 0x21, 0 + .dw 0xf640, 0xc829, 0xf67f, 0xc829, 0x21, 0 + .dw 0xf6c0, 0xc829, 0xf6ff, 0xc829, 0x21, 0 + .dw 0xf740, 0xc829, 0xf77f, 0xc829, 0x21, 0 + .dw 0xf7c0, 0xc829, 0xf7ff, 0xc829, 0x21, 0 + .dw 0xf840, 0xc829, 0xf87f, 0xc829, 0x21, 0 + .dw 0xf8c0, 0xc829, 0xf8ff, 0xc829, 0x21, 0 + .dw 0xf940, 0xc829, 0xf97f, 0xc829, 0x21, 0 + .dw 0xf9c0, 0xc829, 0x1fff, 0xc82a, 0x21, 0 + .dw 0x2040, 0xc82a, 0x207f, 0xc82a, 0x21, 0 + .dw 0x20c0, 0xc82a, 0x20ff, 0xc82a, 0x21, 0 + .dw 0x2140, 0xc82a, 0x217f, 0xc82a, 0x21, 0 + .dw 0x21c0, 0xc82a, 0x21ff, 0xc82a, 0x21, 0 + .dw 0x2240, 0xc82a, 0x227f, 0xc82a, 0x21, 0 + .dw 0x22c0, 0xc82a, 0x22ff, 0xc82a, 0x21, 0 + .dw 0x2340, 0xc82a, 0x237f, 0xc82a, 0x21, 0 + .dw 0x23c0, 0xc82a, 0x23ff, 0xc82a, 0x21, 0 + .dw 0x2440, 0xc82a, 0x247f, 0xc82a, 0x21, 0 + .dw 0x24c0, 0xc82a, 0x24ff, 0xc82a, 0x21, 0 + .dw 0x2540, 0xc82a, 0x257f, 0xc82a, 0x21, 0 + .dw 0x25c0, 0xc82a, 0x25ff, 0xc82a, 0x21, 0 + .dw 0x2640, 0xc82a, 0x267f, 0xc82a, 0x21, 0 + .dw 0x26c0, 0xc82a, 0x26ff, 0xc82a, 0x21, 0 + .dw 0x2740, 0xc82a, 0x277f, 0xc82a, 0x21, 0 + .dw 0x27c0, 0xc82a, 0x27ff, 0xc82a, 0x21, 0 + .dw 0x2840, 0xc82a, 0x287f, 0xc82a, 0x21, 0 + .dw 0x28c0, 0xc82a, 0x28ff, 0xc82a, 0x21, 0 + .dw 0x2940, 0xc82a, 0x297f, 0xc82a, 0x21, 0 + .dw 0x29c0, 0xc82a, 0x29ff, 0xc82a, 0x21, 0 + .dw 0x2a40, 0xc82a, 0x2a7f, 0xc82a, 0x21, 0 + .dw 0x2ac0, 0xc82a, 0x2aff, 0xc82a, 0x21, 0 + .dw 0x2b40, 0xc82a, 0x2b7f, 0xc82a, 0x21, 0 + .dw 0x2bc0, 0xc82a, 0x2bff, 0xc82a, 0x21, 0 + .dw 0x2c40, 0xc82a, 0x2c7f, 0xc82a, 0x21, 0 + .dw 0x2cc0, 0xc82a, 0x2cff, 0xc82a, 0x21, 0 + .dw 0x2d40, 0xc82a, 0x2d7f, 0xc82a, 0x21, 0 + .dw 0x2dc0, 0xc82a, 0x2dff, 0xc82a, 0x21, 0 + .dw 0x2e40, 0xc82a, 0x2e7f, 0xc82a, 0x21, 0 + .dw 0x2ec0, 0xc82a, 0x2eff, 0xc82a, 0x21, 0 + .dw 0x2f40, 0xc82a, 0x2f7f, 0xc82a, 0x21, 0 + .dw 0x2fc0, 0xc82a, 0x2fff, 0xc82a, 0x21, 0 + .dw 0x3040, 0xc82a, 0x307f, 0xc82a, 0x21, 0 + .dw 0x30c0, 0xc82a, 0x30ff, 0xc82a, 0x21, 0 + .dw 0x3140, 0xc82a, 0x317f, 0xc82a, 0x21, 0 + .dw 0x31c0, 0xc82a, 0x31ff, 0xc82a, 0x21, 0 + .dw 0x3240, 0xc82a, 0x327f, 0xc82a, 0x21, 0 + .dw 0x32c0, 0xc82a, 0x32ff, 0xc82a, 0x21, 0 + .dw 0x3340, 0xc82a, 0x337f, 0xc82a, 0x21, 0 + .dw 0x33c0, 0xc82a, 0x33ff, 0xc82a, 0x21, 0 + .dw 0x3440, 0xc82a, 0x347f, 0xc82a, 0x21, 0 + .dw 0x34c0, 0xc82a, 0x34ff, 0xc82a, 0x21, 0 + .dw 0x3540, 0xc82a, 0x357f, 0xc82a, 0x21, 0 + .dw 0x35c0, 0xc82a, 0x35ff, 0xc82a, 0x21, 0 + .dw 0x3640, 0xc82a, 0x367f, 0xc82a, 0x21, 0 + .dw 0x36c0, 0xc82a, 0x36ff, 0xc82a, 0x21, 0 + .dw 0x3740, 0xc82a, 0x377f, 0xc82a, 0x21, 0 + .dw 0x37c0, 0xc82a, 0x37ff, 0xc82a, 0x21, 0 + .dw 0x3840, 0xc82a, 0x387f, 0xc82a, 0x21, 0 + .dw 0x38c0, 0xc82a, 0x38ff, 0xc82a, 0x21, 0 + .dw 0x3940, 0xc82a, 0x397f, 0xc82a, 0x21, 0 + .dw 0x39c0, 0xc82a, 0x5fff, 0xc82a, 0x21, 0 + .dw 0x6040, 0xc82a, 0x607f, 0xc82a, 0x21, 0 + .dw 0x60c0, 0xc82a, 0x60ff, 0xc82a, 0x21, 0 + .dw 0x6140, 0xc82a, 0x617f, 0xc82a, 0x21, 0 + .dw 0x61c0, 0xc82a, 0x61ff, 0xc82a, 0x21, 0 + .dw 0x6240, 0xc82a, 0x627f, 0xc82a, 0x21, 0 + .dw 0x62c0, 0xc82a, 0x62ff, 0xc82a, 0x21, 0 + .dw 0x6340, 0xc82a, 0x637f, 0xc82a, 0x21, 0 + .dw 0x63c0, 0xc82a, 0x63ff, 0xc82a, 0x21, 0 + .dw 0x6440, 0xc82a, 0x647f, 0xc82a, 0x21, 0 + .dw 0x64c0, 0xc82a, 0x64ff, 0xc82a, 0x21, 0 + .dw 0x6540, 0xc82a, 0x657f, 0xc82a, 0x21, 0 + .dw 0x65c0, 0xc82a, 0x65ff, 0xc82a, 0x21, 0 + .dw 0x6640, 0xc82a, 0x667f, 0xc82a, 0x21, 0 + .dw 0x66c0, 0xc82a, 0x66ff, 0xc82a, 0x21, 0 + .dw 0x6740, 0xc82a, 0x677f, 0xc82a, 0x21, 0 + .dw 0x67c0, 0xc82a, 0x67ff, 0xc82a, 0x21, 0 + .dw 0x6840, 0xc82a, 0x687f, 0xc82a, 0x21, 0 + .dw 0x68c0, 0xc82a, 0x68ff, 0xc82a, 0x21, 0 + .dw 0x6940, 0xc82a, 0x697f, 0xc82a, 0x21, 0 + .dw 0x69c0, 0xc82a, 0x69ff, 0xc82a, 0x21, 0 + .dw 0x6a40, 0xc82a, 0x6a7f, 0xc82a, 0x21, 0 + .dw 0x6ac0, 0xc82a, 0x6aff, 0xc82a, 0x21, 0 + .dw 0x6b40, 0xc82a, 0x6b7f, 0xc82a, 0x21, 0 + .dw 0x6bc0, 0xc82a, 0x6bff, 0xc82a, 0x21, 0 + .dw 0x6c40, 0xc82a, 0x6c7f, 0xc82a, 0x21, 0 + .dw 0x6cc0, 0xc82a, 0x6cff, 0xc82a, 0x21, 0 + .dw 0x6d40, 0xc82a, 0x6d7f, 0xc82a, 0x21, 0 + .dw 0x6dc0, 0xc82a, 0x6dff, 0xc82a, 0x21, 0 + .dw 0x6e40, 0xc82a, 0x6e7f, 0xc82a, 0x21, 0 + .dw 0x6ec0, 0xc82a, 0x6eff, 0xc82a, 0x21, 0 + .dw 0x6f40, 0xc82a, 0x6f7f, 0xc82a, 0x21, 0 + .dw 0x6fc0, 0xc82a, 0x6fff, 0xc82a, 0x21, 0 + .dw 0x7040, 0xc82a, 0x707f, 0xc82a, 0x21, 0 + .dw 0x70c0, 0xc82a, 0x70ff, 0xc82a, 0x21, 0 + .dw 0x7140, 0xc82a, 0x717f, 0xc82a, 0x21, 0 + .dw 0x71c0, 0xc82a, 0x71ff, 0xc82a, 0x21, 0 + .dw 0x7240, 0xc82a, 0x727f, 0xc82a, 0x21, 0 + .dw 0x72c0, 0xc82a, 0x72ff, 0xc82a, 0x21, 0 + .dw 0x7340, 0xc82a, 0x737f, 0xc82a, 0x21, 0 + .dw 0x73c0, 0xc82a, 0x73ff, 0xc82a, 0x21, 0 + .dw 0x7440, 0xc82a, 0x747f, 0xc82a, 0x21, 0 + .dw 0x74c0, 0xc82a, 0x74ff, 0xc82a, 0x21, 0 + .dw 0x7540, 0xc82a, 0x757f, 0xc82a, 0x21, 0 + .dw 0x75c0, 0xc82a, 0x75ff, 0xc82a, 0x21, 0 + .dw 0x7640, 0xc82a, 0x767f, 0xc82a, 0x21, 0 + .dw 0x76c0, 0xc82a, 0x76ff, 0xc82a, 0x21, 0 + .dw 0x7740, 0xc82a, 0x777f, 0xc82a, 0x21, 0 + .dw 0x77c0, 0xc82a, 0x77ff, 0xc82a, 0x21, 0 + .dw 0x7840, 0xc82a, 0x787f, 0xc82a, 0x21, 0 + .dw 0x78c0, 0xc82a, 0x78ff, 0xc82a, 0x21, 0 + .dw 0x7940, 0xc82a, 0x797f, 0xc82a, 0x21, 0 + .dw 0x79c0, 0xc82a, 0x9fff, 0xc82a, 0x21, 0 + .dw 0xa040, 0xc82a, 0xa07f, 0xc82a, 0x21, 0 + .dw 0xa0c0, 0xc82a, 0xa0ff, 0xc82a, 0x21, 0 + .dw 0xa140, 0xc82a, 0xa17f, 0xc82a, 0x21, 0 + .dw 0xa1c0, 0xc82a, 0xa1ff, 0xc82a, 0x21, 0 + .dw 0xa240, 0xc82a, 0xa27f, 0xc82a, 0x21, 0 + .dw 0xa2c0, 0xc82a, 0xa2ff, 0xc82a, 0x21, 0 + .dw 0xa340, 0xc82a, 0xa37f, 0xc82a, 0x21, 0 + .dw 0xa3c0, 0xc82a, 0xa3ff, 0xc82a, 0x21, 0 + .dw 0xa440, 0xc82a, 0xa47f, 0xc82a, 0x21, 0 + .dw 0xa4c0, 0xc82a, 0xa4ff, 0xc82a, 0x21, 0 + .dw 0xa540, 0xc82a, 0xa57f, 0xc82a, 0x21, 0 + .dw 0xa5c0, 0xc82a, 0xa5ff, 0xc82a, 0x21, 0 + .dw 0xa640, 0xc82a, 0xa67f, 0xc82a, 0x21, 0 + .dw 0xa6c0, 0xc82a, 0xa6ff, 0xc82a, 0x21, 0 + .dw 0xa740, 0xc82a, 0xa77f, 0xc82a, 0x21, 0 + .dw 0xa7c0, 0xc82a, 0xa7ff, 0xc82a, 0x21, 0 + .dw 0xa840, 0xc82a, 0xa87f, 0xc82a, 0x21, 0 + .dw 0xa8c0, 0xc82a, 0xa8ff, 0xc82a, 0x21, 0 + .dw 0xa940, 0xc82a, 0xa97f, 0xc82a, 0x21, 0 + .dw 0xa9c0, 0xc82a, 0xa9ff, 0xc82a, 0x21, 0 + .dw 0xaa40, 0xc82a, 0xaa7f, 0xc82a, 0x21, 0 + .dw 0xaac0, 0xc82a, 0xaaff, 0xc82a, 0x21, 0 + .dw 0xab40, 0xc82a, 0xab7f, 0xc82a, 0x21, 0 + .dw 0xabc0, 0xc82a, 0xabff, 0xc82a, 0x21, 0 + .dw 0xac40, 0xc82a, 0xac7f, 0xc82a, 0x21, 0 + .dw 0xacc0, 0xc82a, 0xacff, 0xc82a, 0x21, 0 + .dw 0xad40, 0xc82a, 0xad7f, 0xc82a, 0x21, 0 + .dw 0xadc0, 0xc82a, 0xadff, 0xc82a, 0x21, 0 + .dw 0xae40, 0xc82a, 0xae7f, 0xc82a, 0x21, 0 + .dw 0xaec0, 0xc82a, 0xaeff, 0xc82a, 0x21, 0 + .dw 0xaf40, 0xc82a, 0xaf7f, 0xc82a, 0x21, 0 + .dw 0xafc0, 0xc82a, 0xafff, 0xc82a, 0x21, 0 + .dw 0xb040, 0xc82a, 0xb07f, 0xc82a, 0x21, 0 + .dw 0xb0c0, 0xc82a, 0xb0ff, 0xc82a, 0x21, 0 + .dw 0xb140, 0xc82a, 0xb17f, 0xc82a, 0x21, 0 + .dw 0xb1c0, 0xc82a, 0xb1ff, 0xc82a, 0x21, 0 + .dw 0xb240, 0xc82a, 0xb27f, 0xc82a, 0x21, 0 + .dw 0xb2c0, 0xc82a, 0xb2ff, 0xc82a, 0x21, 0 + .dw 0xb340, 0xc82a, 0xb37f, 0xc82a, 0x21, 0 + .dw 0xb3c0, 0xc82a, 0xb3ff, 0xc82a, 0x21, 0 + .dw 0xb440, 0xc82a, 0xb47f, 0xc82a, 0x21, 0 + .dw 0xb4c0, 0xc82a, 0xb4ff, 0xc82a, 0x21, 0 + .dw 0xb540, 0xc82a, 0xb57f, 0xc82a, 0x21, 0 + .dw 0xb5c0, 0xc82a, 0xb5ff, 0xc82a, 0x21, 0 + .dw 0xb640, 0xc82a, 0xb67f, 0xc82a, 0x21, 0 + .dw 0xb6c0, 0xc82a, 0xb6ff, 0xc82a, 0x21, 0 + .dw 0xb740, 0xc82a, 0xb77f, 0xc82a, 0x21, 0 + .dw 0xb7c0, 0xc82a, 0xb7ff, 0xc82a, 0x21, 0 + .dw 0xb840, 0xc82a, 0xb87f, 0xc82a, 0x21, 0 + .dw 0xb8c0, 0xc82a, 0xb8ff, 0xc82a, 0x21, 0 + .dw 0xb940, 0xc82a, 0xb97f, 0xc82a, 0x21, 0 + .dw 0xb9c0, 0xc82a, 0xdfff, 0xc82a, 0x21, 0 + .dw 0xe040, 0xc82a, 0xe07f, 0xc82a, 0x21, 0 + .dw 0xe0c0, 0xc82a, 0xe0ff, 0xc82a, 0x21, 0 + .dw 0xe140, 0xc82a, 0xe17f, 0xc82a, 0x21, 0 + .dw 0xe1c0, 0xc82a, 0xe1ff, 0xc82a, 0x21, 0 + .dw 0xe240, 0xc82a, 0xe27f, 0xc82a, 0x21, 0 + .dw 0xe2c0, 0xc82a, 0xe2ff, 0xc82a, 0x21, 0 + .dw 0xe340, 0xc82a, 0xe37f, 0xc82a, 0x21, 0 + .dw 0xe3c0, 0xc82a, 0xe3ff, 0xc82a, 0x21, 0 + .dw 0xe440, 0xc82a, 0xe47f, 0xc82a, 0x21, 0 + .dw 0xe4c0, 0xc82a, 0xe4ff, 0xc82a, 0x21, 0 + .dw 0xe540, 0xc82a, 0xe57f, 0xc82a, 0x21, 0 + .dw 0xe5c0, 0xc82a, 0xe5ff, 0xc82a, 0x21, 0 + .dw 0xe640, 0xc82a, 0xe67f, 0xc82a, 0x21, 0 + .dw 0xe6c0, 0xc82a, 0xe6ff, 0xc82a, 0x21, 0 + .dw 0xe740, 0xc82a, 0xe77f, 0xc82a, 0x21, 0 + .dw 0xe7c0, 0xc82a, 0xe7ff, 0xc82a, 0x21, 0 + .dw 0xe840, 0xc82a, 0xe87f, 0xc82a, 0x21, 0 + .dw 0xe8c0, 0xc82a, 0xe8ff, 0xc82a, 0x21, 0 + .dw 0xe940, 0xc82a, 0xe97f, 0xc82a, 0x21, 0 + .dw 0xe9c0, 0xc82a, 0xe9ff, 0xc82a, 0x21, 0 + .dw 0xea40, 0xc82a, 0xea7f, 0xc82a, 0x21, 0 + .dw 0xeac0, 0xc82a, 0xeaff, 0xc82a, 0x21, 0 + .dw 0xeb40, 0xc82a, 0xeb7f, 0xc82a, 0x21, 0 + .dw 0xebc0, 0xc82a, 0xebff, 0xc82a, 0x21, 0 + .dw 0xec40, 0xc82a, 0xec7f, 0xc82a, 0x21, 0 + .dw 0xecc0, 0xc82a, 0xecff, 0xc82a, 0x21, 0 + .dw 0xed40, 0xc82a, 0xed7f, 0xc82a, 0x21, 0 + .dw 0xedc0, 0xc82a, 0xedff, 0xc82a, 0x21, 0 + .dw 0xee40, 0xc82a, 0xee7f, 0xc82a, 0x21, 0 + .dw 0xeec0, 0xc82a, 0xeeff, 0xc82a, 0x21, 0 + .dw 0xef40, 0xc82a, 0xef7f, 0xc82a, 0x21, 0 + .dw 0xefc0, 0xc82a, 0xefff, 0xc82a, 0x21, 0 + .dw 0xf040, 0xc82a, 0xf07f, 0xc82a, 0x21, 0 + .dw 0xf0c0, 0xc82a, 0xf0ff, 0xc82a, 0x21, 0 + .dw 0xf140, 0xc82a, 0xf17f, 0xc82a, 0x21, 0 + .dw 0xf1c0, 0xc82a, 0xf1ff, 0xc82a, 0x21, 0 + .dw 0xf240, 0xc82a, 0xf27f, 0xc82a, 0x21, 0 + .dw 0xf2c0, 0xc82a, 0xf2ff, 0xc82a, 0x21, 0 + .dw 0xf340, 0xc82a, 0xf37f, 0xc82a, 0x21, 0 + .dw 0xf3c0, 0xc82a, 0xf3ff, 0xc82a, 0x21, 0 + .dw 0xf440, 0xc82a, 0xf47f, 0xc82a, 0x21, 0 + .dw 0xf4c0, 0xc82a, 0xf4ff, 0xc82a, 0x21, 0 + .dw 0xf540, 0xc82a, 0xf57f, 0xc82a, 0x21, 0 + .dw 0xf5c0, 0xc82a, 0xf5ff, 0xc82a, 0x21, 0 + .dw 0xf640, 0xc82a, 0xf67f, 0xc82a, 0x21, 0 + .dw 0xf6c0, 0xc82a, 0xf6ff, 0xc82a, 0x21, 0 + .dw 0xf740, 0xc82a, 0xf77f, 0xc82a, 0x21, 0 + .dw 0xf7c0, 0xc82a, 0xf7ff, 0xc82a, 0x21, 0 + .dw 0xf840, 0xc82a, 0xf87f, 0xc82a, 0x21, 0 + .dw 0xf8c0, 0xc82a, 0xf8ff, 0xc82a, 0x21, 0 + .dw 0xf940, 0xc82a, 0xf97f, 0xc82a, 0x21, 0 + .dw 0xf9c0, 0xc82a, 0x1fff, 0xc82b, 0x21, 0 + .dw 0x2040, 0xc82b, 0x207f, 0xc82b, 0x21, 0 + .dw 0x20c0, 0xc82b, 0x20ff, 0xc82b, 0x21, 0 + .dw 0x2140, 0xc82b, 0x217f, 0xc82b, 0x21, 0 + .dw 0x21c0, 0xc82b, 0x21ff, 0xc82b, 0x21, 0 + .dw 0x2240, 0xc82b, 0x227f, 0xc82b, 0x21, 0 + .dw 0x22c0, 0xc82b, 0x22ff, 0xc82b, 0x21, 0 + .dw 0x2340, 0xc82b, 0x237f, 0xc82b, 0x21, 0 + .dw 0x23c0, 0xc82b, 0x23ff, 0xc82b, 0x21, 0 + .dw 0x2440, 0xc82b, 0x247f, 0xc82b, 0x21, 0 + .dw 0x24c0, 0xc82b, 0x24ff, 0xc82b, 0x21, 0 + .dw 0x2540, 0xc82b, 0x257f, 0xc82b, 0x21, 0 + .dw 0x25c0, 0xc82b, 0x25ff, 0xc82b, 0x21, 0 + .dw 0x2640, 0xc82b, 0x267f, 0xc82b, 0x21, 0 + .dw 0x26c0, 0xc82b, 0x26ff, 0xc82b, 0x21, 0 + .dw 0x2740, 0xc82b, 0x277f, 0xc82b, 0x21, 0 + .dw 0x27c0, 0xc82b, 0x27ff, 0xc82b, 0x21, 0 + .dw 0x2840, 0xc82b, 0x287f, 0xc82b, 0x21, 0 + .dw 0x28c0, 0xc82b, 0x28ff, 0xc82b, 0x21, 0 + .dw 0x2940, 0xc82b, 0x297f, 0xc82b, 0x21, 0 + .dw 0x29c0, 0xc82b, 0x29ff, 0xc82b, 0x21, 0 + .dw 0x2a40, 0xc82b, 0x2a7f, 0xc82b, 0x21, 0 + .dw 0x2ac0, 0xc82b, 0x2aff, 0xc82b, 0x21, 0 + .dw 0x2b40, 0xc82b, 0x2b7f, 0xc82b, 0x21, 0 + .dw 0x2bc0, 0xc82b, 0x2bff, 0xc82b, 0x21, 0 + .dw 0x2c40, 0xc82b, 0x2c7f, 0xc82b, 0x21, 0 + .dw 0x2cc0, 0xc82b, 0x2cff, 0xc82b, 0x21, 0 + .dw 0x2d40, 0xc82b, 0x2d7f, 0xc82b, 0x21, 0 + .dw 0x2dc0, 0xc82b, 0x2dff, 0xc82b, 0x21, 0 + .dw 0x2e40, 0xc82b, 0x2e7f, 0xc82b, 0x21, 0 + .dw 0x2ec0, 0xc82b, 0x2eff, 0xc82b, 0x21, 0 + .dw 0x2f40, 0xc82b, 0x2f7f, 0xc82b, 0x21, 0 + .dw 0x2fc0, 0xc82b, 0x2fff, 0xc82b, 0x21, 0 + .dw 0x3040, 0xc82b, 0x307f, 0xc82b, 0x21, 0 + .dw 0x30c0, 0xc82b, 0x30ff, 0xc82b, 0x21, 0 + .dw 0x3140, 0xc82b, 0x317f, 0xc82b, 0x21, 0 + .dw 0x31c0, 0xc82b, 0x31ff, 0xc82b, 0x21, 0 + .dw 0x3240, 0xc82b, 0x327f, 0xc82b, 0x21, 0 + .dw 0x32c0, 0xc82b, 0x32ff, 0xc82b, 0x21, 0 + .dw 0x3340, 0xc82b, 0x337f, 0xc82b, 0x21, 0 + .dw 0x33c0, 0xc82b, 0x33ff, 0xc82b, 0x21, 0 + .dw 0x3440, 0xc82b, 0x347f, 0xc82b, 0x21, 0 + .dw 0x34c0, 0xc82b, 0x34ff, 0xc82b, 0x21, 0 + .dw 0x3540, 0xc82b, 0x357f, 0xc82b, 0x21, 0 + .dw 0x35c0, 0xc82b, 0x35ff, 0xc82b, 0x21, 0 + .dw 0x3640, 0xc82b, 0x367f, 0xc82b, 0x21, 0 + .dw 0x36c0, 0xc82b, 0x36ff, 0xc82b, 0x21, 0 + .dw 0x3740, 0xc82b, 0x377f, 0xc82b, 0x21, 0 + .dw 0x37c0, 0xc82b, 0x37ff, 0xc82b, 0x21, 0 + .dw 0x3840, 0xc82b, 0x387f, 0xc82b, 0x21, 0 + .dw 0x38c0, 0xc82b, 0x38ff, 0xc82b, 0x21, 0 + .dw 0x3940, 0xc82b, 0x397f, 0xc82b, 0x21, 0 + .dw 0x39c0, 0xc82b, 0xffff, 0xc82b, 0x21, 0 + .dw 0x0040, 0xc82c, 0x007f, 0xc82c, 0x21, 0 + .dw 0x00c0, 0xc82c, 0x00ff, 0xc82c, 0x21, 0 + .dw 0x0140, 0xc82c, 0x017f, 0xc82c, 0x21, 0 + .dw 0x01c0, 0xc82c, 0x01ff, 0xc82c, 0x21, 0 + .dw 0x0240, 0xc82c, 0x027f, 0xc82c, 0x21, 0 + .dw 0x02c0, 0xc82c, 0x02ff, 0xc82c, 0x21, 0 + .dw 0x0340, 0xc82c, 0x037f, 0xc82c, 0x21, 0 + .dw 0x03c0, 0xc82c, 0x03ff, 0xc82c, 0x21, 0 + .dw 0x0440, 0xc82c, 0x047f, 0xc82c, 0x21, 0 + .dw 0x04c0, 0xc82c, 0x04ff, 0xc82c, 0x21, 0 + .dw 0x0540, 0xc82c, 0x057f, 0xc82c, 0x21, 0 + .dw 0x05c0, 0xc82c, 0x05ff, 0xc82c, 0x21, 0 + .dw 0x0640, 0xc82c, 0x067f, 0xc82c, 0x21, 0 + .dw 0x06c0, 0xc82c, 0x06ff, 0xc82c, 0x21, 0 + .dw 0x0740, 0xc82c, 0x077f, 0xc82c, 0x21, 0 + .dw 0x07c0, 0xc82c, 0x07ff, 0xc82c, 0x21, 0 + .dw 0x0840, 0xc82c, 0x087f, 0xc82c, 0x21, 0 + .dw 0x08c0, 0xc82c, 0x08ff, 0xc82c, 0x21, 0 + .dw 0x0940, 0xc82c, 0x097f, 0xc82c, 0x21, 0 + .dw 0x09c0, 0xc82c, 0x09ff, 0xc82c, 0x21, 0 + .dw 0x0a40, 0xc82c, 0x0a7f, 0xc82c, 0x21, 0 + .dw 0x0ac0, 0xc82c, 0x0aff, 0xc82c, 0x21, 0 + .dw 0x0b40, 0xc82c, 0x0b7f, 0xc82c, 0x21, 0 + .dw 0x0bc0, 0xc82c, 0x0bff, 0xc82c, 0x21, 0 + .dw 0x0c40, 0xc82c, 0x0c7f, 0xc82c, 0x21, 0 + .dw 0x0cc0, 0xc82c, 0x0cff, 0xc82c, 0x21, 0 + .dw 0x0d40, 0xc82c, 0x0d7f, 0xc82c, 0x21, 0 + .dw 0x0dc0, 0xc82c, 0x0dff, 0xc82c, 0x21, 0 + .dw 0x0e40, 0xc82c, 0x0e7f, 0xc82c, 0x21, 0 + .dw 0x0ec0, 0xc82c, 0x0eff, 0xc82c, 0x21, 0 + .dw 0x0f40, 0xc82c, 0x0f7f, 0xc82c, 0x21, 0 + .dw 0x0fc0, 0xc82c, 0x0fff, 0xc82c, 0x21, 0 + .dw 0x1040, 0xc82c, 0x107f, 0xc82c, 0x21, 0 + .dw 0x10c0, 0xc82c, 0x10ff, 0xc82c, 0x21, 0 + .dw 0x1140, 0xc82c, 0x117f, 0xc82c, 0x21, 0 + .dw 0x11c0, 0xc82c, 0x11ff, 0xc82c, 0x21, 0 + .dw 0x1240, 0xc82c, 0x127f, 0xc82c, 0x21, 0 + .dw 0x12c0, 0xc82c, 0x12ff, 0xc82c, 0x21, 0 + .dw 0x1340, 0xc82c, 0x137f, 0xc82c, 0x21, 0 + .dw 0x13c0, 0xc82c, 0x13ff, 0xc82c, 0x21, 0 + .dw 0x1440, 0xc82c, 0x147f, 0xc82c, 0x21, 0 + .dw 0x14c0, 0xc82c, 0x14ff, 0xc82c, 0x21, 0 + .dw 0x1540, 0xc82c, 0x157f, 0xc82c, 0x21, 0 + .dw 0x15c0, 0xc82c, 0x15ff, 0xc82c, 0x21, 0 + .dw 0x1640, 0xc82c, 0x167f, 0xc82c, 0x21, 0 + .dw 0x16c0, 0xc82c, 0x16ff, 0xc82c, 0x21, 0 + .dw 0x1740, 0xc82c, 0x177f, 0xc82c, 0x21, 0 + .dw 0x17c0, 0xc82c, 0x17ff, 0xc82c, 0x21, 0 + .dw 0x1840, 0xc82c, 0x187f, 0xc82c, 0x21, 0 + .dw 0x18c0, 0xc82c, 0x18ff, 0xc82c, 0x21, 0 + .dw 0x1940, 0xc82c, 0x197f, 0xc82c, 0x21, 0 + .dw 0x19c0, 0xc82c, 0x1fff, 0xc82c, 0x21, 0 + .dw 0x2040, 0xc82c, 0x207f, 0xc82c, 0x21, 0 + .dw 0x20c0, 0xc82c, 0x20ff, 0xc82c, 0x21, 0 + .dw 0x2140, 0xc82c, 0x217f, 0xc82c, 0x21, 0 + .dw 0x21c0, 0xc82c, 0x21ff, 0xc82c, 0x21, 0 + .dw 0x2240, 0xc82c, 0x227f, 0xc82c, 0x21, 0 + .dw 0x22c0, 0xc82c, 0x22ff, 0xc82c, 0x21, 0 + .dw 0x2340, 0xc82c, 0x237f, 0xc82c, 0x21, 0 + .dw 0x23c0, 0xc82c, 0x23ff, 0xc82c, 0x21, 0 + .dw 0x2440, 0xc82c, 0x247f, 0xc82c, 0x21, 0 + .dw 0x24c0, 0xc82c, 0x24ff, 0xc82c, 0x21, 0 + .dw 0x2540, 0xc82c, 0x257f, 0xc82c, 0x21, 0 + .dw 0x25c0, 0xc82c, 0x25ff, 0xc82c, 0x21, 0 + .dw 0x2640, 0xc82c, 0x267f, 0xc82c, 0x21, 0 + .dw 0x26c0, 0xc82c, 0x26ff, 0xc82c, 0x21, 0 + .dw 0x2740, 0xc82c, 0x277f, 0xc82c, 0x21, 0 + .dw 0x27c0, 0xc82c, 0x27ff, 0xc82c, 0x21, 0 + .dw 0x2840, 0xc82c, 0x287f, 0xc82c, 0x21, 0 + .dw 0x28c0, 0xc82c, 0x28ff, 0xc82c, 0x21, 0 + .dw 0x2940, 0xc82c, 0x297f, 0xc82c, 0x21, 0 + .dw 0x29c0, 0xc82c, 0x29ff, 0xc82c, 0x21, 0 + .dw 0x2a40, 0xc82c, 0x2a7f, 0xc82c, 0x21, 0 + .dw 0x2ac0, 0xc82c, 0x2aff, 0xc82c, 0x21, 0 + .dw 0x2b40, 0xc82c, 0x2b7f, 0xc82c, 0x21, 0 + .dw 0x2bc0, 0xc82c, 0x2bff, 0xc82c, 0x21, 0 + .dw 0x2c40, 0xc82c, 0x2c7f, 0xc82c, 0x21, 0 + .dw 0x2cc0, 0xc82c, 0x2cff, 0xc82c, 0x21, 0 + .dw 0x2d40, 0xc82c, 0x2d7f, 0xc82c, 0x21, 0 + .dw 0x2dc0, 0xc82c, 0x2dff, 0xc82c, 0x21, 0 + .dw 0x2e40, 0xc82c, 0x2e7f, 0xc82c, 0x21, 0 + .dw 0x2ec0, 0xc82c, 0x2eff, 0xc82c, 0x21, 0 + .dw 0x2f40, 0xc82c, 0x2f7f, 0xc82c, 0x21, 0 + .dw 0x2fc0, 0xc82c, 0x2fff, 0xc82c, 0x21, 0 + .dw 0x3040, 0xc82c, 0x307f, 0xc82c, 0x21, 0 + .dw 0x30c0, 0xc82c, 0x30ff, 0xc82c, 0x21, 0 + .dw 0x3140, 0xc82c, 0x317f, 0xc82c, 0x21, 0 + .dw 0x31c0, 0xc82c, 0x31ff, 0xc82c, 0x21, 0 + .dw 0x3240, 0xc82c, 0x327f, 0xc82c, 0x21, 0 + .dw 0x32c0, 0xc82c, 0x32ff, 0xc82c, 0x21, 0 + .dw 0x3340, 0xc82c, 0x337f, 0xc82c, 0x21, 0 + .dw 0x33c0, 0xc82c, 0x33ff, 0xc82c, 0x21, 0 + .dw 0x3440, 0xc82c, 0x347f, 0xc82c, 0x21, 0 + .dw 0x34c0, 0xc82c, 0x34ff, 0xc82c, 0x21, 0 + .dw 0x3540, 0xc82c, 0x357f, 0xc82c, 0x21, 0 + .dw 0x35c0, 0xc82c, 0x35ff, 0xc82c, 0x21, 0 + .dw 0x3640, 0xc82c, 0x367f, 0xc82c, 0x21, 0 + .dw 0x36c0, 0xc82c, 0x36ff, 0xc82c, 0x21, 0 + .dw 0x3740, 0xc82c, 0x377f, 0xc82c, 0x21, 0 + .dw 0x37c0, 0xc82c, 0x37ff, 0xc82c, 0x21, 0 + .dw 0x3840, 0xc82c, 0x387f, 0xc82c, 0x21, 0 + .dw 0x38c0, 0xc82c, 0x38ff, 0xc82c, 0x21, 0 + .dw 0x3940, 0xc82c, 0x397f, 0xc82c, 0x21, 0 + .dw 0x39c0, 0xc82c, 0x3fff, 0xc82c, 0x21, 0 + .dw 0x4040, 0xc82c, 0x407f, 0xc82c, 0x21, 0 + .dw 0x40c0, 0xc82c, 0x40ff, 0xc82c, 0x21, 0 + .dw 0x4140, 0xc82c, 0x417f, 0xc82c, 0x21, 0 + .dw 0x41c0, 0xc82c, 0x41ff, 0xc82c, 0x21, 0 + .dw 0x4240, 0xc82c, 0x427f, 0xc82c, 0x21, 0 + .dw 0x42c0, 0xc82c, 0x42ff, 0xc82c, 0x21, 0 + .dw 0x4340, 0xc82c, 0x437f, 0xc82c, 0x21, 0 + .dw 0x43c0, 0xc82c, 0x43ff, 0xc82c, 0x21, 0 + .dw 0x4440, 0xc82c, 0x447f, 0xc82c, 0x21, 0 + .dw 0x44c0, 0xc82c, 0x44ff, 0xc82c, 0x21, 0 + .dw 0x4540, 0xc82c, 0x457f, 0xc82c, 0x21, 0 + .dw 0x45c0, 0xc82c, 0x45ff, 0xc82c, 0x21, 0 + .dw 0x4640, 0xc82c, 0x467f, 0xc82c, 0x21, 0 + .dw 0x46c0, 0xc82c, 0x46ff, 0xc82c, 0x21, 0 + .dw 0x4740, 0xc82c, 0x477f, 0xc82c, 0x21, 0 + .dw 0x47c0, 0xc82c, 0x47ff, 0xc82c, 0x21, 0 + .dw 0x4840, 0xc82c, 0x487f, 0xc82c, 0x21, 0 + .dw 0x48c0, 0xc82c, 0x48ff, 0xc82c, 0x21, 0 + .dw 0x4940, 0xc82c, 0x497f, 0xc82c, 0x21, 0 + .dw 0x49c0, 0xc82c, 0x49ff, 0xc82c, 0x21, 0 + .dw 0x4a40, 0xc82c, 0x4a7f, 0xc82c, 0x21, 0 + .dw 0x4ac0, 0xc82c, 0x4aff, 0xc82c, 0x21, 0 + .dw 0x4b40, 0xc82c, 0x4b7f, 0xc82c, 0x21, 0 + .dw 0x4bc0, 0xc82c, 0x4bff, 0xc82c, 0x21, 0 + .dw 0x4c40, 0xc82c, 0x4c7f, 0xc82c, 0x21, 0 + .dw 0x4cc0, 0xc82c, 0x4cff, 0xc82c, 0x21, 0 + .dw 0x4d40, 0xc82c, 0x4d7f, 0xc82c, 0x21, 0 + .dw 0x4dc0, 0xc82c, 0x4dff, 0xc82c, 0x21, 0 + .dw 0x4e40, 0xc82c, 0x4e7f, 0xc82c, 0x21, 0 + .dw 0x4ec0, 0xc82c, 0x4eff, 0xc82c, 0x21, 0 + .dw 0x4f40, 0xc82c, 0x4f7f, 0xc82c, 0x21, 0 + .dw 0x4fc0, 0xc82c, 0x4fff, 0xc82c, 0x21, 0 + .dw 0x5040, 0xc82c, 0x507f, 0xc82c, 0x21, 0 + .dw 0x50c0, 0xc82c, 0x50ff, 0xc82c, 0x21, 0 + .dw 0x5140, 0xc82c, 0x517f, 0xc82c, 0x21, 0 + .dw 0x51c0, 0xc82c, 0x51ff, 0xc82c, 0x21, 0 + .dw 0x5240, 0xc82c, 0x527f, 0xc82c, 0x21, 0 + .dw 0x52c0, 0xc82c, 0x52ff, 0xc82c, 0x21, 0 + .dw 0x5340, 0xc82c, 0x537f, 0xc82c, 0x21, 0 + .dw 0x53c0, 0xc82c, 0x53ff, 0xc82c, 0x21, 0 + .dw 0x5440, 0xc82c, 0x547f, 0xc82c, 0x21, 0 + .dw 0x54c0, 0xc82c, 0x54ff, 0xc82c, 0x21, 0 + .dw 0x5540, 0xc82c, 0x557f, 0xc82c, 0x21, 0 + .dw 0x55c0, 0xc82c, 0x55ff, 0xc82c, 0x21, 0 + .dw 0x5640, 0xc82c, 0x567f, 0xc82c, 0x21, 0 + .dw 0x56c0, 0xc82c, 0x56ff, 0xc82c, 0x21, 0 + .dw 0x5740, 0xc82c, 0x577f, 0xc82c, 0x21, 0 + .dw 0x57c0, 0xc82c, 0x57ff, 0xc82c, 0x21, 0 + .dw 0x5840, 0xc82c, 0x587f, 0xc82c, 0x21, 0 + .dw 0x58c0, 0xc82c, 0x58ff, 0xc82c, 0x21, 0 + .dw 0x5940, 0xc82c, 0x597f, 0xc82c, 0x21, 0 + .dw 0x59c0, 0xc82c, 0x5fff, 0xc82c, 0x21, 0 + .dw 0x6040, 0xc82c, 0x607f, 0xc82c, 0x21, 0 + .dw 0x60c0, 0xc82c, 0x60ff, 0xc82c, 0x21, 0 + .dw 0x6140, 0xc82c, 0x617f, 0xc82c, 0x21, 0 + .dw 0x61c0, 0xc82c, 0x61ff, 0xc82c, 0x21, 0 + .dw 0x6240, 0xc82c, 0x627f, 0xc82c, 0x21, 0 + .dw 0x62c0, 0xc82c, 0x62ff, 0xc82c, 0x21, 0 + .dw 0x6340, 0xc82c, 0x637f, 0xc82c, 0x21, 0 + .dw 0x63c0, 0xc82c, 0x63ff, 0xc82c, 0x21, 0 + .dw 0x6440, 0xc82c, 0x647f, 0xc82c, 0x21, 0 + .dw 0x64c0, 0xc82c, 0x64ff, 0xc82c, 0x21, 0 + .dw 0x6540, 0xc82c, 0x657f, 0xc82c, 0x21, 0 + .dw 0x65c0, 0xc82c, 0x65ff, 0xc82c, 0x21, 0 + .dw 0x6640, 0xc82c, 0x667f, 0xc82c, 0x21, 0 + .dw 0x66c0, 0xc82c, 0x66ff, 0xc82c, 0x21, 0 + .dw 0x6740, 0xc82c, 0x677f, 0xc82c, 0x21, 0 + .dw 0x67c0, 0xc82c, 0x67ff, 0xc82c, 0x21, 0 + .dw 0x6840, 0xc82c, 0x687f, 0xc82c, 0x21, 0 + .dw 0x68c0, 0xc82c, 0x68ff, 0xc82c, 0x21, 0 + .dw 0x6940, 0xc82c, 0x697f, 0xc82c, 0x21, 0 + .dw 0x69c0, 0xc82c, 0x69ff, 0xc82c, 0x21, 0 + .dw 0x6a40, 0xc82c, 0x6a7f, 0xc82c, 0x21, 0 + .dw 0x6ac0, 0xc82c, 0x6aff, 0xc82c, 0x21, 0 + .dw 0x6b40, 0xc82c, 0x6b7f, 0xc82c, 0x21, 0 + .dw 0x6bc0, 0xc82c, 0x6bff, 0xc82c, 0x21, 0 + .dw 0x6c40, 0xc82c, 0x6c7f, 0xc82c, 0x21, 0 + .dw 0x6cc0, 0xc82c, 0x6cff, 0xc82c, 0x21, 0 + .dw 0x6d40, 0xc82c, 0x6d7f, 0xc82c, 0x21, 0 + .dw 0x6dc0, 0xc82c, 0x6dff, 0xc82c, 0x21, 0 + .dw 0x6e40, 0xc82c, 0x6e7f, 0xc82c, 0x21, 0 + .dw 0x6ec0, 0xc82c, 0x6eff, 0xc82c, 0x21, 0 + .dw 0x6f40, 0xc82c, 0x6f7f, 0xc82c, 0x21, 0 + .dw 0x6fc0, 0xc82c, 0x6fff, 0xc82c, 0x21, 0 + .dw 0x7040, 0xc82c, 0x707f, 0xc82c, 0x21, 0 + .dw 0x70c0, 0xc82c, 0x70ff, 0xc82c, 0x21, 0 + .dw 0x7140, 0xc82c, 0x717f, 0xc82c, 0x21, 0 + .dw 0x71c0, 0xc82c, 0x71ff, 0xc82c, 0x21, 0 + .dw 0x7240, 0xc82c, 0x727f, 0xc82c, 0x21, 0 + .dw 0x72c0, 0xc82c, 0x72ff, 0xc82c, 0x21, 0 + .dw 0x7340, 0xc82c, 0x737f, 0xc82c, 0x21, 0 + .dw 0x73c0, 0xc82c, 0x73ff, 0xc82c, 0x21, 0 + .dw 0x7440, 0xc82c, 0x747f, 0xc82c, 0x21, 0 + .dw 0x74c0, 0xc82c, 0x74ff, 0xc82c, 0x21, 0 + .dw 0x7540, 0xc82c, 0x757f, 0xc82c, 0x21, 0 + .dw 0x75c0, 0xc82c, 0x75ff, 0xc82c, 0x21, 0 + .dw 0x7640, 0xc82c, 0x767f, 0xc82c, 0x21, 0 + .dw 0x76c0, 0xc82c, 0x76ff, 0xc82c, 0x21, 0 + .dw 0x7740, 0xc82c, 0x777f, 0xc82c, 0x21, 0 + .dw 0x77c0, 0xc82c, 0x77ff, 0xc82c, 0x21, 0 + .dw 0x7840, 0xc82c, 0x787f, 0xc82c, 0x21, 0 + .dw 0x78c0, 0xc82c, 0x78ff, 0xc82c, 0x21, 0 + .dw 0x7940, 0xc82c, 0x797f, 0xc82c, 0x21, 0 + .dw 0x79c0, 0xc82c, 0x7fff, 0xc82c, 0x21, 0 + .dw 0x8040, 0xc82c, 0x807f, 0xc82c, 0x21, 0 + .dw 0x80c0, 0xc82c, 0x80ff, 0xc82c, 0x21, 0 + .dw 0x8140, 0xc82c, 0x817f, 0xc82c, 0x21, 0 + .dw 0x81c0, 0xc82c, 0x81ff, 0xc82c, 0x21, 0 + .dw 0x8240, 0xc82c, 0x827f, 0xc82c, 0x21, 0 + .dw 0x82c0, 0xc82c, 0x82ff, 0xc82c, 0x21, 0 + .dw 0x8340, 0xc82c, 0x837f, 0xc82c, 0x21, 0 + .dw 0x83c0, 0xc82c, 0x83ff, 0xc82c, 0x21, 0 + .dw 0x8440, 0xc82c, 0x847f, 0xc82c, 0x21, 0 + .dw 0x84c0, 0xc82c, 0x84ff, 0xc82c, 0x21, 0 + .dw 0x8540, 0xc82c, 0x857f, 0xc82c, 0x21, 0 + .dw 0x85c0, 0xc82c, 0x85ff, 0xc82c, 0x21, 0 + .dw 0x8640, 0xc82c, 0x867f, 0xc82c, 0x21, 0 + .dw 0x86c0, 0xc82c, 0x86ff, 0xc82c, 0x21, 0 + .dw 0x8740, 0xc82c, 0x877f, 0xc82c, 0x21, 0 + .dw 0x87c0, 0xc82c, 0x87ff, 0xc82c, 0x21, 0 + .dw 0x8840, 0xc82c, 0x887f, 0xc82c, 0x21, 0 + .dw 0x88c0, 0xc82c, 0x88ff, 0xc82c, 0x21, 0 + .dw 0x8940, 0xc82c, 0x897f, 0xc82c, 0x21, 0 + .dw 0x89c0, 0xc82c, 0x89ff, 0xc82c, 0x21, 0 + .dw 0x8a40, 0xc82c, 0x8a7f, 0xc82c, 0x21, 0 + .dw 0x8ac0, 0xc82c, 0x8aff, 0xc82c, 0x21, 0 + .dw 0x8b40, 0xc82c, 0x8b7f, 0xc82c, 0x21, 0 + .dw 0x8bc0, 0xc82c, 0x8bff, 0xc82c, 0x21, 0 + .dw 0x8c40, 0xc82c, 0x8c7f, 0xc82c, 0x21, 0 + .dw 0x8cc0, 0xc82c, 0x8cff, 0xc82c, 0x21, 0 + .dw 0x8d40, 0xc82c, 0x8d7f, 0xc82c, 0x21, 0 + .dw 0x8dc0, 0xc82c, 0x8dff, 0xc82c, 0x21, 0 + .dw 0x8e40, 0xc82c, 0x8e7f, 0xc82c, 0x21, 0 + .dw 0x8ec0, 0xc82c, 0x8eff, 0xc82c, 0x21, 0 + .dw 0x8f40, 0xc82c, 0x8f7f, 0xc82c, 0x21, 0 + .dw 0x8fc0, 0xc82c, 0x8fff, 0xc82c, 0x21, 0 + .dw 0x9040, 0xc82c, 0x907f, 0xc82c, 0x21, 0 + .dw 0x90c0, 0xc82c, 0x90ff, 0xc82c, 0x21, 0 + .dw 0x9140, 0xc82c, 0x917f, 0xc82c, 0x21, 0 + .dw 0x91c0, 0xc82c, 0x91ff, 0xc82c, 0x21, 0 + .dw 0x9240, 0xc82c, 0x927f, 0xc82c, 0x21, 0 + .dw 0x92c0, 0xc82c, 0x92ff, 0xc82c, 0x21, 0 + .dw 0x9340, 0xc82c, 0x937f, 0xc82c, 0x21, 0 + .dw 0x93c0, 0xc82c, 0x93ff, 0xc82c, 0x21, 0 + .dw 0x9440, 0xc82c, 0x947f, 0xc82c, 0x21, 0 + .dw 0x94c0, 0xc82c, 0x94ff, 0xc82c, 0x21, 0 + .dw 0x9540, 0xc82c, 0x957f, 0xc82c, 0x21, 0 + .dw 0x95c0, 0xc82c, 0x95ff, 0xc82c, 0x21, 0 + .dw 0x9640, 0xc82c, 0x967f, 0xc82c, 0x21, 0 + .dw 0x96c0, 0xc82c, 0x96ff, 0xc82c, 0x21, 0 + .dw 0x9740, 0xc82c, 0x977f, 0xc82c, 0x21, 0 + .dw 0x97c0, 0xc82c, 0x97ff, 0xc82c, 0x21, 0 + .dw 0x9840, 0xc82c, 0x987f, 0xc82c, 0x21, 0 + .dw 0x98c0, 0xc82c, 0x98ff, 0xc82c, 0x21, 0 + .dw 0x9940, 0xc82c, 0x997f, 0xc82c, 0x21, 0 + .dw 0x99c0, 0xc82c, 0x9fff, 0xc82c, 0x21, 0 + .dw 0xa040, 0xc82c, 0xa07f, 0xc82c, 0x21, 0 + .dw 0xa0c0, 0xc82c, 0xa0ff, 0xc82c, 0x21, 0 + .dw 0xa140, 0xc82c, 0xa17f, 0xc82c, 0x21, 0 + .dw 0xa1c0, 0xc82c, 0xa1ff, 0xc82c, 0x21, 0 + .dw 0xa240, 0xc82c, 0xa27f, 0xc82c, 0x21, 0 + .dw 0xa2c0, 0xc82c, 0xa2ff, 0xc82c, 0x21, 0 + .dw 0xa340, 0xc82c, 0xa37f, 0xc82c, 0x21, 0 + .dw 0xa3c0, 0xc82c, 0xa3ff, 0xc82c, 0x21, 0 + .dw 0xa440, 0xc82c, 0xa47f, 0xc82c, 0x21, 0 + .dw 0xa4c0, 0xc82c, 0xa4ff, 0xc82c, 0x21, 0 + .dw 0xa540, 0xc82c, 0xa57f, 0xc82c, 0x21, 0 + .dw 0xa5c0, 0xc82c, 0xa5ff, 0xc82c, 0x21, 0 + .dw 0xa640, 0xc82c, 0xa67f, 0xc82c, 0x21, 0 + .dw 0xa6c0, 0xc82c, 0xa6ff, 0xc82c, 0x21, 0 + .dw 0xa740, 0xc82c, 0xa77f, 0xc82c, 0x21, 0 + .dw 0xa7c0, 0xc82c, 0xa7ff, 0xc82c, 0x21, 0 + .dw 0xa840, 0xc82c, 0xa87f, 0xc82c, 0x21, 0 + .dw 0xa8c0, 0xc82c, 0xa8ff, 0xc82c, 0x21, 0 + .dw 0xa940, 0xc82c, 0xa97f, 0xc82c, 0x21, 0 + .dw 0xa9c0, 0xc82c, 0xa9ff, 0xc82c, 0x21, 0 + .dw 0xaa40, 0xc82c, 0xaa7f, 0xc82c, 0x21, 0 + .dw 0xaac0, 0xc82c, 0xaaff, 0xc82c, 0x21, 0 + .dw 0xab40, 0xc82c, 0xab7f, 0xc82c, 0x21, 0 + .dw 0xabc0, 0xc82c, 0xabff, 0xc82c, 0x21, 0 + .dw 0xac40, 0xc82c, 0xac7f, 0xc82c, 0x21, 0 + .dw 0xacc0, 0xc82c, 0xacff, 0xc82c, 0x21, 0 + .dw 0xad40, 0xc82c, 0xad7f, 0xc82c, 0x21, 0 + .dw 0xadc0, 0xc82c, 0xadff, 0xc82c, 0x21, 0 + .dw 0xae40, 0xc82c, 0xae7f, 0xc82c, 0x21, 0 + .dw 0xaec0, 0xc82c, 0xaeff, 0xc82c, 0x21, 0 + .dw 0xaf40, 0xc82c, 0xaf7f, 0xc82c, 0x21, 0 + .dw 0xafc0, 0xc82c, 0xafff, 0xc82c, 0x21, 0 + .dw 0xb040, 0xc82c, 0xb07f, 0xc82c, 0x21, 0 + .dw 0xb0c0, 0xc82c, 0xb0ff, 0xc82c, 0x21, 0 + .dw 0xb140, 0xc82c, 0xb17f, 0xc82c, 0x21, 0 + .dw 0xb1c0, 0xc82c, 0xb1ff, 0xc82c, 0x21, 0 + .dw 0xb240, 0xc82c, 0xb27f, 0xc82c, 0x21, 0 + .dw 0xb2c0, 0xc82c, 0xb2ff, 0xc82c, 0x21, 0 + .dw 0xb340, 0xc82c, 0xb37f, 0xc82c, 0x21, 0 + .dw 0xb3c0, 0xc82c, 0xb3ff, 0xc82c, 0x21, 0 + .dw 0xb440, 0xc82c, 0xb47f, 0xc82c, 0x21, 0 + .dw 0xb4c0, 0xc82c, 0xb4ff, 0xc82c, 0x21, 0 + .dw 0xb540, 0xc82c, 0xb57f, 0xc82c, 0x21, 0 + .dw 0xb5c0, 0xc82c, 0xb5ff, 0xc82c, 0x21, 0 + .dw 0xb640, 0xc82c, 0xb67f, 0xc82c, 0x21, 0 + .dw 0xb6c0, 0xc82c, 0xb6ff, 0xc82c, 0x21, 0 + .dw 0xb740, 0xc82c, 0xb77f, 0xc82c, 0x21, 0 + .dw 0xb7c0, 0xc82c, 0xb7ff, 0xc82c, 0x21, 0 + .dw 0xb840, 0xc82c, 0xb87f, 0xc82c, 0x21, 0 + .dw 0xb8c0, 0xc82c, 0xb8ff, 0xc82c, 0x21, 0 + .dw 0xb940, 0xc82c, 0xb97f, 0xc82c, 0x21, 0 + .dw 0xb9c0, 0xc82c, 0xbfff, 0xc82c, 0x21, 0 + .dw 0xc040, 0xc82c, 0xc07f, 0xc82c, 0x21, 0 + .dw 0xc0c0, 0xc82c, 0xc0ff, 0xc82c, 0x21, 0 + .dw 0xc140, 0xc82c, 0xc17f, 0xc82c, 0x21, 0 + .dw 0xc1c0, 0xc82c, 0xc1ff, 0xc82c, 0x21, 0 + .dw 0xc240, 0xc82c, 0xc27f, 0xc82c, 0x21, 0 + .dw 0xc2c0, 0xc82c, 0xc2ff, 0xc82c, 0x21, 0 + .dw 0xc340, 0xc82c, 0xc37f, 0xc82c, 0x21, 0 + .dw 0xc3c0, 0xc82c, 0xc3ff, 0xc82c, 0x21, 0 + .dw 0xc440, 0xc82c, 0xc47f, 0xc82c, 0x21, 0 + .dw 0xc4c0, 0xc82c, 0xc4ff, 0xc82c, 0x21, 0 + .dw 0xc540, 0xc82c, 0xc57f, 0xc82c, 0x21, 0 + .dw 0xc5c0, 0xc82c, 0xc5ff, 0xc82c, 0x21, 0 + .dw 0xc640, 0xc82c, 0xc67f, 0xc82c, 0x21, 0 + .dw 0xc6c0, 0xc82c, 0xc6ff, 0xc82c, 0x21, 0 + .dw 0xc740, 0xc82c, 0xc77f, 0xc82c, 0x21, 0 + .dw 0xc7c0, 0xc82c, 0xc7ff, 0xc82c, 0x21, 0 + .dw 0xc840, 0xc82c, 0xc87f, 0xc82c, 0x21, 0 + .dw 0xc8c0, 0xc82c, 0xc8ff, 0xc82c, 0x21, 0 + .dw 0xc940, 0xc82c, 0xc97f, 0xc82c, 0x21, 0 + .dw 0xc9c0, 0xc82c, 0xc9ff, 0xc82c, 0x21, 0 + .dw 0xca40, 0xc82c, 0xca7f, 0xc82c, 0x21, 0 + .dw 0xcac0, 0xc82c, 0xcaff, 0xc82c, 0x21, 0 + .dw 0xcb40, 0xc82c, 0xcb7f, 0xc82c, 0x21, 0 + .dw 0xcbc0, 0xc82c, 0xcbff, 0xc82c, 0x21, 0 + .dw 0xcc40, 0xc82c, 0xcc7f, 0xc82c, 0x21, 0 + .dw 0xccc0, 0xc82c, 0xccff, 0xc82c, 0x21, 0 + .dw 0xcd40, 0xc82c, 0xcd7f, 0xc82c, 0x21, 0 + .dw 0xcdc0, 0xc82c, 0xcdff, 0xc82c, 0x21, 0 + .dw 0xce40, 0xc82c, 0xce7f, 0xc82c, 0x21, 0 + .dw 0xcec0, 0xc82c, 0xceff, 0xc82c, 0x21, 0 + .dw 0xcf40, 0xc82c, 0xcf7f, 0xc82c, 0x21, 0 + .dw 0xcfc0, 0xc82c, 0xcfff, 0xc82c, 0x21, 0 + .dw 0xd040, 0xc82c, 0xd07f, 0xc82c, 0x21, 0 + .dw 0xd0c0, 0xc82c, 0xd0ff, 0xc82c, 0x21, 0 + .dw 0xd140, 0xc82c, 0xd17f, 0xc82c, 0x21, 0 + .dw 0xd1c0, 0xc82c, 0xd1ff, 0xc82c, 0x21, 0 + .dw 0xd240, 0xc82c, 0xd27f, 0xc82c, 0x21, 0 + .dw 0xd2c0, 0xc82c, 0xd2ff, 0xc82c, 0x21, 0 + .dw 0xd340, 0xc82c, 0xd37f, 0xc82c, 0x21, 0 + .dw 0xd3c0, 0xc82c, 0xd3ff, 0xc82c, 0x21, 0 + .dw 0xd440, 0xc82c, 0xd47f, 0xc82c, 0x21, 0 + .dw 0xd4c0, 0xc82c, 0xd4ff, 0xc82c, 0x21, 0 + .dw 0xd540, 0xc82c, 0xd57f, 0xc82c, 0x21, 0 + .dw 0xd5c0, 0xc82c, 0xd5ff, 0xc82c, 0x21, 0 + .dw 0xd640, 0xc82c, 0xd67f, 0xc82c, 0x21, 0 + .dw 0xd6c0, 0xc82c, 0xd6ff, 0xc82c, 0x21, 0 + .dw 0xd740, 0xc82c, 0xd77f, 0xc82c, 0x21, 0 + .dw 0xd7c0, 0xc82c, 0xd7ff, 0xc82c, 0x21, 0 + .dw 0xd840, 0xc82c, 0xd87f, 0xc82c, 0x21, 0 + .dw 0xd8c0, 0xc82c, 0xd8ff, 0xc82c, 0x21, 0 + .dw 0xd940, 0xc82c, 0xd97f, 0xc82c, 0x21, 0 + .dw 0xd9c0, 0xc82c, 0xdfff, 0xc82c, 0x21, 0 + .dw 0xe040, 0xc82c, 0xe07f, 0xc82c, 0x21, 0 + .dw 0xe0c0, 0xc82c, 0xe0ff, 0xc82c, 0x21, 0 + .dw 0xe140, 0xc82c, 0xe17f, 0xc82c, 0x21, 0 + .dw 0xe1c0, 0xc82c, 0xe1ff, 0xc82c, 0x21, 0 + .dw 0xe240, 0xc82c, 0xe27f, 0xc82c, 0x21, 0 + .dw 0xe2c0, 0xc82c, 0xe2ff, 0xc82c, 0x21, 0 + .dw 0xe340, 0xc82c, 0xe37f, 0xc82c, 0x21, 0 + .dw 0xe3c0, 0xc82c, 0xe3ff, 0xc82c, 0x21, 0 + .dw 0xe440, 0xc82c, 0xe47f, 0xc82c, 0x21, 0 + .dw 0xe4c0, 0xc82c, 0xe4ff, 0xc82c, 0x21, 0 + .dw 0xe540, 0xc82c, 0xe57f, 0xc82c, 0x21, 0 + .dw 0xe5c0, 0xc82c, 0xe5ff, 0xc82c, 0x21, 0 + .dw 0xe640, 0xc82c, 0xe67f, 0xc82c, 0x21, 0 + .dw 0xe6c0, 0xc82c, 0xe6ff, 0xc82c, 0x21, 0 + .dw 0xe740, 0xc82c, 0xe77f, 0xc82c, 0x21, 0 + .dw 0xe7c0, 0xc82c, 0xe7ff, 0xc82c, 0x21, 0 + .dw 0xe840, 0xc82c, 0xe87f, 0xc82c, 0x21, 0 + .dw 0xe8c0, 0xc82c, 0xe8ff, 0xc82c, 0x21, 0 + .dw 0xe940, 0xc82c, 0xe97f, 0xc82c, 0x21, 0 + .dw 0xe9c0, 0xc82c, 0xe9ff, 0xc82c, 0x21, 0 + .dw 0xea40, 0xc82c, 0xea7f, 0xc82c, 0x21, 0 + .dw 0xeac0, 0xc82c, 0xeaff, 0xc82c, 0x21, 0 + .dw 0xeb40, 0xc82c, 0xeb7f, 0xc82c, 0x21, 0 + .dw 0xebc0, 0xc82c, 0xebff, 0xc82c, 0x21, 0 + .dw 0xec40, 0xc82c, 0xec7f, 0xc82c, 0x21, 0 + .dw 0xecc0, 0xc82c, 0xecff, 0xc82c, 0x21, 0 + .dw 0xed40, 0xc82c, 0xed7f, 0xc82c, 0x21, 0 + .dw 0xedc0, 0xc82c, 0xedff, 0xc82c, 0x21, 0 + .dw 0xee40, 0xc82c, 0xee7f, 0xc82c, 0x21, 0 + .dw 0xeec0, 0xc82c, 0xeeff, 0xc82c, 0x21, 0 + .dw 0xef40, 0xc82c, 0xef7f, 0xc82c, 0x21, 0 + .dw 0xefc0, 0xc82c, 0xefff, 0xc82c, 0x21, 0 + .dw 0xf040, 0xc82c, 0xf07f, 0xc82c, 0x21, 0 + .dw 0xf0c0, 0xc82c, 0xf0ff, 0xc82c, 0x21, 0 + .dw 0xf140, 0xc82c, 0xf17f, 0xc82c, 0x21, 0 + .dw 0xf1c0, 0xc82c, 0xf1ff, 0xc82c, 0x21, 0 + .dw 0xf240, 0xc82c, 0xf27f, 0xc82c, 0x21, 0 + .dw 0xf2c0, 0xc82c, 0xf2ff, 0xc82c, 0x21, 0 + .dw 0xf340, 0xc82c, 0xf37f, 0xc82c, 0x21, 0 + .dw 0xf3c0, 0xc82c, 0xf3ff, 0xc82c, 0x21, 0 + .dw 0xf440, 0xc82c, 0xf47f, 0xc82c, 0x21, 0 + .dw 0xf4c0, 0xc82c, 0xf4ff, 0xc82c, 0x21, 0 + .dw 0xf540, 0xc82c, 0xf57f, 0xc82c, 0x21, 0 + .dw 0xf5c0, 0xc82c, 0xf5ff, 0xc82c, 0x21, 0 + .dw 0xf640, 0xc82c, 0xf67f, 0xc82c, 0x21, 0 + .dw 0xf6c0, 0xc82c, 0xf6ff, 0xc82c, 0x21, 0 + .dw 0xf740, 0xc82c, 0xf77f, 0xc82c, 0x21, 0 + .dw 0xf7c0, 0xc82c, 0xf7ff, 0xc82c, 0x21, 0 + .dw 0xf840, 0xc82c, 0xf87f, 0xc82c, 0x21, 0 + .dw 0xf8c0, 0xc82c, 0xf8ff, 0xc82c, 0x21, 0 + .dw 0xf940, 0xc82c, 0xf97f, 0xc82c, 0x21, 0 + .dw 0xf9c0, 0xc82c, 0xffff, 0xc82c, 0x21, 0 + .dw 0x0040, 0xc82d, 0x007f, 0xc82d, 0x21, 0 + .dw 0x00c0, 0xc82d, 0x00ff, 0xc82d, 0x21, 0 + .dw 0x0140, 0xc82d, 0x017f, 0xc82d, 0x21, 0 + .dw 0x01c0, 0xc82d, 0x01ff, 0xc82d, 0x21, 0 + .dw 0x0240, 0xc82d, 0x027f, 0xc82d, 0x21, 0 + .dw 0x02c0, 0xc82d, 0x02ff, 0xc82d, 0x21, 0 + .dw 0x0340, 0xc82d, 0x037f, 0xc82d, 0x21, 0 + .dw 0x03c0, 0xc82d, 0x03ff, 0xc82d, 0x21, 0 + .dw 0x0440, 0xc82d, 0x047f, 0xc82d, 0x21, 0 + .dw 0x04c0, 0xc82d, 0x04ff, 0xc82d, 0x21, 0 + .dw 0x0540, 0xc82d, 0x057f, 0xc82d, 0x21, 0 + .dw 0x05c0, 0xc82d, 0x05ff, 0xc82d, 0x21, 0 + .dw 0x0640, 0xc82d, 0x067f, 0xc82d, 0x21, 0 + .dw 0x06c0, 0xc82d, 0x06ff, 0xc82d, 0x21, 0 + .dw 0x0740, 0xc82d, 0x077f, 0xc82d, 0x21, 0 + .dw 0x07c0, 0xc82d, 0x07ff, 0xc82d, 0x21, 0 + .dw 0x0840, 0xc82d, 0x087f, 0xc82d, 0x21, 0 + .dw 0x08c0, 0xc82d, 0x08ff, 0xc82d, 0x21, 0 + .dw 0x0940, 0xc82d, 0x097f, 0xc82d, 0x21, 0 + .dw 0x09c0, 0xc82d, 0x09ff, 0xc82d, 0x21, 0 + .dw 0x0a40, 0xc82d, 0x0a7f, 0xc82d, 0x21, 0 + .dw 0x0ac0, 0xc82d, 0x0aff, 0xc82d, 0x21, 0 + .dw 0x0b40, 0xc82d, 0x0b7f, 0xc82d, 0x21, 0 + .dw 0x0bc0, 0xc82d, 0x0bff, 0xc82d, 0x21, 0 + .dw 0x0c40, 0xc82d, 0x0c7f, 0xc82d, 0x21, 0 + .dw 0x0cc0, 0xc82d, 0x0cff, 0xc82d, 0x21, 0 + .dw 0x0d40, 0xc82d, 0x0d7f, 0xc82d, 0x21, 0 + .dw 0x0dc0, 0xc82d, 0x0dff, 0xc82d, 0x21, 0 + .dw 0x0e40, 0xc82d, 0x0e7f, 0xc82d, 0x21, 0 + .dw 0x0ec0, 0xc82d, 0x0eff, 0xc82d, 0x21, 0 + .dw 0x0f40, 0xc82d, 0x0f7f, 0xc82d, 0x21, 0 + .dw 0x0fc0, 0xc82d, 0x0fff, 0xc82d, 0x21, 0 + .dw 0x1040, 0xc82d, 0x107f, 0xc82d, 0x21, 0 + .dw 0x10c0, 0xc82d, 0x10ff, 0xc82d, 0x21, 0 + .dw 0x1140, 0xc82d, 0x117f, 0xc82d, 0x21, 0 + .dw 0x11c0, 0xc82d, 0x11ff, 0xc82d, 0x21, 0 + .dw 0x1240, 0xc82d, 0x127f, 0xc82d, 0x21, 0 + .dw 0x12c0, 0xc82d, 0x12ff, 0xc82d, 0x21, 0 + .dw 0x1340, 0xc82d, 0x137f, 0xc82d, 0x21, 0 + .dw 0x13c0, 0xc82d, 0x13ff, 0xc82d, 0x21, 0 + .dw 0x1440, 0xc82d, 0x147f, 0xc82d, 0x21, 0 + .dw 0x14c0, 0xc82d, 0x14ff, 0xc82d, 0x21, 0 + .dw 0x1540, 0xc82d, 0x157f, 0xc82d, 0x21, 0 + .dw 0x15c0, 0xc82d, 0x15ff, 0xc82d, 0x21, 0 + .dw 0x1640, 0xc82d, 0x167f, 0xc82d, 0x21, 0 + .dw 0x16c0, 0xc82d, 0x16ff, 0xc82d, 0x21, 0 + .dw 0x1740, 0xc82d, 0x177f, 0xc82d, 0x21, 0 + .dw 0x17c0, 0xc82d, 0x17ff, 0xc82d, 0x21, 0 + .dw 0x1840, 0xc82d, 0x187f, 0xc82d, 0x21, 0 + .dw 0x18c0, 0xc82d, 0x18ff, 0xc82d, 0x21, 0 + .dw 0x1940, 0xc82d, 0x197f, 0xc82d, 0x21, 0 + .dw 0x19c0, 0xc82d, 0x1fff, 0xc82d, 0x21, 0 + .dw 0x2040, 0xc82d, 0x207f, 0xc82d, 0x21, 0 + .dw 0x20c0, 0xc82d, 0x20ff, 0xc82d, 0x21, 0 + .dw 0x2140, 0xc82d, 0x217f, 0xc82d, 0x21, 0 + .dw 0x21c0, 0xc82d, 0x21ff, 0xc82d, 0x21, 0 + .dw 0x2240, 0xc82d, 0x227f, 0xc82d, 0x21, 0 + .dw 0x22c0, 0xc82d, 0x22ff, 0xc82d, 0x21, 0 + .dw 0x2340, 0xc82d, 0x237f, 0xc82d, 0x21, 0 + .dw 0x23c0, 0xc82d, 0x23ff, 0xc82d, 0x21, 0 + .dw 0x2440, 0xc82d, 0x247f, 0xc82d, 0x21, 0 + .dw 0x24c0, 0xc82d, 0x24ff, 0xc82d, 0x21, 0 + .dw 0x2540, 0xc82d, 0x257f, 0xc82d, 0x21, 0 + .dw 0x25c0, 0xc82d, 0x25ff, 0xc82d, 0x21, 0 + .dw 0x2640, 0xc82d, 0x267f, 0xc82d, 0x21, 0 + .dw 0x26c0, 0xc82d, 0x26ff, 0xc82d, 0x21, 0 + .dw 0x2740, 0xc82d, 0x277f, 0xc82d, 0x21, 0 + .dw 0x27c0, 0xc82d, 0x27ff, 0xc82d, 0x21, 0 + .dw 0x2840, 0xc82d, 0x287f, 0xc82d, 0x21, 0 + .dw 0x28c0, 0xc82d, 0x28ff, 0xc82d, 0x21, 0 + .dw 0x2940, 0xc82d, 0x297f, 0xc82d, 0x21, 0 + .dw 0x29c0, 0xc82d, 0x29ff, 0xc82d, 0x21, 0 + .dw 0x2a40, 0xc82d, 0x2a7f, 0xc82d, 0x21, 0 + .dw 0x2ac0, 0xc82d, 0x2aff, 0xc82d, 0x21, 0 + .dw 0x2b40, 0xc82d, 0x2b7f, 0xc82d, 0x21, 0 + .dw 0x2bc0, 0xc82d, 0x2bff, 0xc82d, 0x21, 0 + .dw 0x2c40, 0xc82d, 0x2c7f, 0xc82d, 0x21, 0 + .dw 0x2cc0, 0xc82d, 0x2cff, 0xc82d, 0x21, 0 + .dw 0x2d40, 0xc82d, 0x2d7f, 0xc82d, 0x21, 0 + .dw 0x2dc0, 0xc82d, 0x2dff, 0xc82d, 0x21, 0 + .dw 0x2e40, 0xc82d, 0x2e7f, 0xc82d, 0x21, 0 + .dw 0x2ec0, 0xc82d, 0x2eff, 0xc82d, 0x21, 0 + .dw 0x2f40, 0xc82d, 0x2f7f, 0xc82d, 0x21, 0 + .dw 0x2fc0, 0xc82d, 0x2fff, 0xc82d, 0x21, 0 + .dw 0x3040, 0xc82d, 0x307f, 0xc82d, 0x21, 0 + .dw 0x30c0, 0xc82d, 0x30ff, 0xc82d, 0x21, 0 + .dw 0x3140, 0xc82d, 0x317f, 0xc82d, 0x21, 0 + .dw 0x31c0, 0xc82d, 0x31ff, 0xc82d, 0x21, 0 + .dw 0x3240, 0xc82d, 0x327f, 0xc82d, 0x21, 0 + .dw 0x32c0, 0xc82d, 0x32ff, 0xc82d, 0x21, 0 + .dw 0x3340, 0xc82d, 0x337f, 0xc82d, 0x21, 0 + .dw 0x33c0, 0xc82d, 0x33ff, 0xc82d, 0x21, 0 + .dw 0x3440, 0xc82d, 0x347f, 0xc82d, 0x21, 0 + .dw 0x34c0, 0xc82d, 0x34ff, 0xc82d, 0x21, 0 + .dw 0x3540, 0xc82d, 0x357f, 0xc82d, 0x21, 0 + .dw 0x35c0, 0xc82d, 0x35ff, 0xc82d, 0x21, 0 + .dw 0x3640, 0xc82d, 0x367f, 0xc82d, 0x21, 0 + .dw 0x36c0, 0xc82d, 0x36ff, 0xc82d, 0x21, 0 + .dw 0x3740, 0xc82d, 0x377f, 0xc82d, 0x21, 0 + .dw 0x37c0, 0xc82d, 0x37ff, 0xc82d, 0x21, 0 + .dw 0x3840, 0xc82d, 0x387f, 0xc82d, 0x21, 0 + .dw 0x38c0, 0xc82d, 0x38ff, 0xc82d, 0x21, 0 + .dw 0x3940, 0xc82d, 0x397f, 0xc82d, 0x21, 0 + .dw 0x39c0, 0xc82d, 0x3fff, 0xc82d, 0x21, 0 + .dw 0x4040, 0xc82d, 0x407f, 0xc82d, 0x21, 0 + .dw 0x40c0, 0xc82d, 0x40ff, 0xc82d, 0x21, 0 + .dw 0x4140, 0xc82d, 0x417f, 0xc82d, 0x21, 0 + .dw 0x41c0, 0xc82d, 0x41ff, 0xc82d, 0x21, 0 + .dw 0x4240, 0xc82d, 0x427f, 0xc82d, 0x21, 0 + .dw 0x42c0, 0xc82d, 0x42ff, 0xc82d, 0x21, 0 + .dw 0x4340, 0xc82d, 0x437f, 0xc82d, 0x21, 0 + .dw 0x43c0, 0xc82d, 0x43ff, 0xc82d, 0x21, 0 + .dw 0x4440, 0xc82d, 0x447f, 0xc82d, 0x21, 0 + .dw 0x44c0, 0xc82d, 0x44ff, 0xc82d, 0x21, 0 + .dw 0x4540, 0xc82d, 0x457f, 0xc82d, 0x21, 0 + .dw 0x45c0, 0xc82d, 0x45ff, 0xc82d, 0x21, 0 + .dw 0x4640, 0xc82d, 0x467f, 0xc82d, 0x21, 0 + .dw 0x46c0, 0xc82d, 0x46ff, 0xc82d, 0x21, 0 + .dw 0x4740, 0xc82d, 0x477f, 0xc82d, 0x21, 0 + .dw 0x47c0, 0xc82d, 0x47ff, 0xc82d, 0x21, 0 + .dw 0x4840, 0xc82d, 0x487f, 0xc82d, 0x21, 0 + .dw 0x48c0, 0xc82d, 0x48ff, 0xc82d, 0x21, 0 + .dw 0x4940, 0xc82d, 0x497f, 0xc82d, 0x21, 0 + .dw 0x49c0, 0xc82d, 0x49ff, 0xc82d, 0x21, 0 + .dw 0x4a40, 0xc82d, 0x4a7f, 0xc82d, 0x21, 0 + .dw 0x4ac0, 0xc82d, 0x4aff, 0xc82d, 0x21, 0 + .dw 0x4b40, 0xc82d, 0x4b7f, 0xc82d, 0x21, 0 + .dw 0x4bc0, 0xc82d, 0x4bff, 0xc82d, 0x21, 0 + .dw 0x4c40, 0xc82d, 0x4c7f, 0xc82d, 0x21, 0 + .dw 0x4cc0, 0xc82d, 0x4cff, 0xc82d, 0x21, 0 + .dw 0x4d40, 0xc82d, 0x4d7f, 0xc82d, 0x21, 0 + .dw 0x4dc0, 0xc82d, 0x4dff, 0xc82d, 0x21, 0 + .dw 0x4e40, 0xc82d, 0x4e7f, 0xc82d, 0x21, 0 + .dw 0x4ec0, 0xc82d, 0x4eff, 0xc82d, 0x21, 0 + .dw 0x4f40, 0xc82d, 0x4f7f, 0xc82d, 0x21, 0 + .dw 0x4fc0, 0xc82d, 0x4fff, 0xc82d, 0x21, 0 + .dw 0x5040, 0xc82d, 0x507f, 0xc82d, 0x21, 0 + .dw 0x50c0, 0xc82d, 0x50ff, 0xc82d, 0x21, 0 + .dw 0x5140, 0xc82d, 0x517f, 0xc82d, 0x21, 0 + .dw 0x51c0, 0xc82d, 0x51ff, 0xc82d, 0x21, 0 + .dw 0x5240, 0xc82d, 0x527f, 0xc82d, 0x21, 0 + .dw 0x52c0, 0xc82d, 0x52ff, 0xc82d, 0x21, 0 + .dw 0x5340, 0xc82d, 0x537f, 0xc82d, 0x21, 0 + .dw 0x53c0, 0xc82d, 0x53ff, 0xc82d, 0x21, 0 + .dw 0x5440, 0xc82d, 0x547f, 0xc82d, 0x21, 0 + .dw 0x54c0, 0xc82d, 0x54ff, 0xc82d, 0x21, 0 + .dw 0x5540, 0xc82d, 0x557f, 0xc82d, 0x21, 0 + .dw 0x55c0, 0xc82d, 0x55ff, 0xc82d, 0x21, 0 + .dw 0x5640, 0xc82d, 0x567f, 0xc82d, 0x21, 0 + .dw 0x56c0, 0xc82d, 0x56ff, 0xc82d, 0x21, 0 + .dw 0x5740, 0xc82d, 0x577f, 0xc82d, 0x21, 0 + .dw 0x57c0, 0xc82d, 0x57ff, 0xc82d, 0x21, 0 + .dw 0x5840, 0xc82d, 0x587f, 0xc82d, 0x21, 0 + .dw 0x58c0, 0xc82d, 0x58ff, 0xc82d, 0x21, 0 + .dw 0x5940, 0xc82d, 0x597f, 0xc82d, 0x21, 0 + .dw 0x59c0, 0xc82d, 0x5fff, 0xc82d, 0x21, 0 + .dw 0x6040, 0xc82d, 0x607f, 0xc82d, 0x21, 0 + .dw 0x60c0, 0xc82d, 0x60ff, 0xc82d, 0x21, 0 + .dw 0x6140, 0xc82d, 0x617f, 0xc82d, 0x21, 0 + .dw 0x61c0, 0xc82d, 0x61ff, 0xc82d, 0x21, 0 + .dw 0x6240, 0xc82d, 0x627f, 0xc82d, 0x21, 0 + .dw 0x62c0, 0xc82d, 0x62ff, 0xc82d, 0x21, 0 + .dw 0x6340, 0xc82d, 0x637f, 0xc82d, 0x21, 0 + .dw 0x63c0, 0xc82d, 0x63ff, 0xc82d, 0x21, 0 + .dw 0x6440, 0xc82d, 0x647f, 0xc82d, 0x21, 0 + .dw 0x64c0, 0xc82d, 0x64ff, 0xc82d, 0x21, 0 + .dw 0x6540, 0xc82d, 0x657f, 0xc82d, 0x21, 0 + .dw 0x65c0, 0xc82d, 0x65ff, 0xc82d, 0x21, 0 + .dw 0x6640, 0xc82d, 0x667f, 0xc82d, 0x21, 0 + .dw 0x66c0, 0xc82d, 0x66ff, 0xc82d, 0x21, 0 + .dw 0x6740, 0xc82d, 0x677f, 0xc82d, 0x21, 0 + .dw 0x67c0, 0xc82d, 0x67ff, 0xc82d, 0x21, 0 + .dw 0x6840, 0xc82d, 0x687f, 0xc82d, 0x21, 0 + .dw 0x68c0, 0xc82d, 0x68ff, 0xc82d, 0x21, 0 + .dw 0x6940, 0xc82d, 0x697f, 0xc82d, 0x21, 0 + .dw 0x69c0, 0xc82d, 0x69ff, 0xc82d, 0x21, 0 + .dw 0x6a40, 0xc82d, 0x6a7f, 0xc82d, 0x21, 0 + .dw 0x6ac0, 0xc82d, 0x6aff, 0xc82d, 0x21, 0 + .dw 0x6b40, 0xc82d, 0x6b7f, 0xc82d, 0x21, 0 + .dw 0x6bc0, 0xc82d, 0x6bff, 0xc82d, 0x21, 0 + .dw 0x6c40, 0xc82d, 0x6c7f, 0xc82d, 0x21, 0 + .dw 0x6cc0, 0xc82d, 0x6cff, 0xc82d, 0x21, 0 + .dw 0x6d40, 0xc82d, 0x6d7f, 0xc82d, 0x21, 0 + .dw 0x6dc0, 0xc82d, 0x6dff, 0xc82d, 0x21, 0 + .dw 0x6e40, 0xc82d, 0x6e7f, 0xc82d, 0x21, 0 + .dw 0x6ec0, 0xc82d, 0x6eff, 0xc82d, 0x21, 0 + .dw 0x6f40, 0xc82d, 0x6f7f, 0xc82d, 0x21, 0 + .dw 0x6fc0, 0xc82d, 0x6fff, 0xc82d, 0x21, 0 + .dw 0x7040, 0xc82d, 0x707f, 0xc82d, 0x21, 0 + .dw 0x70c0, 0xc82d, 0x70ff, 0xc82d, 0x21, 0 + .dw 0x7140, 0xc82d, 0x717f, 0xc82d, 0x21, 0 + .dw 0x71c0, 0xc82d, 0x71ff, 0xc82d, 0x21, 0 + .dw 0x7240, 0xc82d, 0x727f, 0xc82d, 0x21, 0 + .dw 0x72c0, 0xc82d, 0x72ff, 0xc82d, 0x21, 0 + .dw 0x7340, 0xc82d, 0x737f, 0xc82d, 0x21, 0 + .dw 0x73c0, 0xc82d, 0x73ff, 0xc82d, 0x21, 0 + .dw 0x7440, 0xc82d, 0x747f, 0xc82d, 0x21, 0 + .dw 0x74c0, 0xc82d, 0x74ff, 0xc82d, 0x21, 0 + .dw 0x7540, 0xc82d, 0x757f, 0xc82d, 0x21, 0 + .dw 0x75c0, 0xc82d, 0x75ff, 0xc82d, 0x21, 0 + .dw 0x7640, 0xc82d, 0x767f, 0xc82d, 0x21, 0 + .dw 0x76c0, 0xc82d, 0x76ff, 0xc82d, 0x21, 0 + .dw 0x7740, 0xc82d, 0x777f, 0xc82d, 0x21, 0 + .dw 0x77c0, 0xc82d, 0x77ff, 0xc82d, 0x21, 0 + .dw 0x7840, 0xc82d, 0x787f, 0xc82d, 0x21, 0 + .dw 0x78c0, 0xc82d, 0x78ff, 0xc82d, 0x21, 0 + .dw 0x7940, 0xc82d, 0x797f, 0xc82d, 0x21, 0 + .dw 0x79c0, 0xc82d, 0x7fff, 0xc82d, 0x21, 0 + .dw 0x8040, 0xc82d, 0x807f, 0xc82d, 0x21, 0 + .dw 0x80c0, 0xc82d, 0x80ff, 0xc82d, 0x21, 0 + .dw 0x8140, 0xc82d, 0x817f, 0xc82d, 0x21, 0 + .dw 0x81c0, 0xc82d, 0x81ff, 0xc82d, 0x21, 0 + .dw 0x8240, 0xc82d, 0x827f, 0xc82d, 0x21, 0 + .dw 0x82c0, 0xc82d, 0x82ff, 0xc82d, 0x21, 0 + .dw 0x8340, 0xc82d, 0x837f, 0xc82d, 0x21, 0 + .dw 0x83c0, 0xc82d, 0x83ff, 0xc82d, 0x21, 0 + .dw 0x8440, 0xc82d, 0x847f, 0xc82d, 0x21, 0 + .dw 0x84c0, 0xc82d, 0x84ff, 0xc82d, 0x21, 0 + .dw 0x8540, 0xc82d, 0x857f, 0xc82d, 0x21, 0 + .dw 0x85c0, 0xc82d, 0x85ff, 0xc82d, 0x21, 0 + .dw 0x8640, 0xc82d, 0x867f, 0xc82d, 0x21, 0 + .dw 0x86c0, 0xc82d, 0x86ff, 0xc82d, 0x21, 0 + .dw 0x8740, 0xc82d, 0x877f, 0xc82d, 0x21, 0 + .dw 0x87c0, 0xc82d, 0x87ff, 0xc82d, 0x21, 0 + .dw 0x8840, 0xc82d, 0x887f, 0xc82d, 0x21, 0 + .dw 0x88c0, 0xc82d, 0x88ff, 0xc82d, 0x21, 0 + .dw 0x8940, 0xc82d, 0x897f, 0xc82d, 0x21, 0 + .dw 0x89c0, 0xc82d, 0x89ff, 0xc82d, 0x21, 0 + .dw 0x8a40, 0xc82d, 0x8a7f, 0xc82d, 0x21, 0 + .dw 0x8ac0, 0xc82d, 0x8aff, 0xc82d, 0x21, 0 + .dw 0x8b40, 0xc82d, 0x8b7f, 0xc82d, 0x21, 0 + .dw 0x8bc0, 0xc82d, 0x8bff, 0xc82d, 0x21, 0 + .dw 0x8c40, 0xc82d, 0x8c7f, 0xc82d, 0x21, 0 + .dw 0x8cc0, 0xc82d, 0x8cff, 0xc82d, 0x21, 0 + .dw 0x8d40, 0xc82d, 0x8d7f, 0xc82d, 0x21, 0 + .dw 0x8dc0, 0xc82d, 0x8dff, 0xc82d, 0x21, 0 + .dw 0x8e40, 0xc82d, 0x8e7f, 0xc82d, 0x21, 0 + .dw 0x8ec0, 0xc82d, 0x8eff, 0xc82d, 0x21, 0 + .dw 0x8f40, 0xc82d, 0x8f7f, 0xc82d, 0x21, 0 + .dw 0x8fc0, 0xc82d, 0x8fff, 0xc82d, 0x21, 0 + .dw 0x9040, 0xc82d, 0x907f, 0xc82d, 0x21, 0 + .dw 0x90c0, 0xc82d, 0x90ff, 0xc82d, 0x21, 0 + .dw 0x9140, 0xc82d, 0x917f, 0xc82d, 0x21, 0 + .dw 0x91c0, 0xc82d, 0x91ff, 0xc82d, 0x21, 0 + .dw 0x9240, 0xc82d, 0x927f, 0xc82d, 0x21, 0 + .dw 0x92c0, 0xc82d, 0x92ff, 0xc82d, 0x21, 0 + .dw 0x9340, 0xc82d, 0x937f, 0xc82d, 0x21, 0 + .dw 0x93c0, 0xc82d, 0x93ff, 0xc82d, 0x21, 0 + .dw 0x9440, 0xc82d, 0x947f, 0xc82d, 0x21, 0 + .dw 0x94c0, 0xc82d, 0x94ff, 0xc82d, 0x21, 0 + .dw 0x9540, 0xc82d, 0x957f, 0xc82d, 0x21, 0 + .dw 0x95c0, 0xc82d, 0x95ff, 0xc82d, 0x21, 0 + .dw 0x9640, 0xc82d, 0x967f, 0xc82d, 0x21, 0 + .dw 0x96c0, 0xc82d, 0x96ff, 0xc82d, 0x21, 0 + .dw 0x9740, 0xc82d, 0x977f, 0xc82d, 0x21, 0 + .dw 0x97c0, 0xc82d, 0x97ff, 0xc82d, 0x21, 0 + .dw 0x9840, 0xc82d, 0x987f, 0xc82d, 0x21, 0 + .dw 0x98c0, 0xc82d, 0x98ff, 0xc82d, 0x21, 0 + .dw 0x9940, 0xc82d, 0x997f, 0xc82d, 0x21, 0 + .dw 0x99c0, 0xc82d, 0x9fff, 0xc82d, 0x21, 0 + .dw 0xa040, 0xc82d, 0xa07f, 0xc82d, 0x21, 0 + .dw 0xa0c0, 0xc82d, 0xa0ff, 0xc82d, 0x21, 0 + .dw 0xa140, 0xc82d, 0xa17f, 0xc82d, 0x21, 0 + .dw 0xa1c0, 0xc82d, 0xa1ff, 0xc82d, 0x21, 0 + .dw 0xa240, 0xc82d, 0xa27f, 0xc82d, 0x21, 0 + .dw 0xa2c0, 0xc82d, 0xa2ff, 0xc82d, 0x21, 0 + .dw 0xa340, 0xc82d, 0xa37f, 0xc82d, 0x21, 0 + .dw 0xa3c0, 0xc82d, 0xa3ff, 0xc82d, 0x21, 0 + .dw 0xa440, 0xc82d, 0xa47f, 0xc82d, 0x21, 0 + .dw 0xa4c0, 0xc82d, 0xa4ff, 0xc82d, 0x21, 0 + .dw 0xa540, 0xc82d, 0xa57f, 0xc82d, 0x21, 0 + .dw 0xa5c0, 0xc82d, 0xa5ff, 0xc82d, 0x21, 0 + .dw 0xa640, 0xc82d, 0xa67f, 0xc82d, 0x21, 0 + .dw 0xa6c0, 0xc82d, 0xa6ff, 0xc82d, 0x21, 0 + .dw 0xa740, 0xc82d, 0xa77f, 0xc82d, 0x21, 0 + .dw 0xa7c0, 0xc82d, 0xa7ff, 0xc82d, 0x21, 0 + .dw 0xa840, 0xc82d, 0xa87f, 0xc82d, 0x21, 0 + .dw 0xa8c0, 0xc82d, 0xa8ff, 0xc82d, 0x21, 0 + .dw 0xa940, 0xc82d, 0xa97f, 0xc82d, 0x21, 0 + .dw 0xa9c0, 0xc82d, 0xa9ff, 0xc82d, 0x21, 0 + .dw 0xaa40, 0xc82d, 0xaa7f, 0xc82d, 0x21, 0 + .dw 0xaac0, 0xc82d, 0xaaff, 0xc82d, 0x21, 0 + .dw 0xab40, 0xc82d, 0xab7f, 0xc82d, 0x21, 0 + .dw 0xabc0, 0xc82d, 0xabff, 0xc82d, 0x21, 0 + .dw 0xac40, 0xc82d, 0xac7f, 0xc82d, 0x21, 0 + .dw 0xacc0, 0xc82d, 0xacff, 0xc82d, 0x21, 0 + .dw 0xad40, 0xc82d, 0xad7f, 0xc82d, 0x21, 0 + .dw 0xadc0, 0xc82d, 0xadff, 0xc82d, 0x21, 0 + .dw 0xae40, 0xc82d, 0xae7f, 0xc82d, 0x21, 0 + .dw 0xaec0, 0xc82d, 0xaeff, 0xc82d, 0x21, 0 + .dw 0xaf40, 0xc82d, 0xaf7f, 0xc82d, 0x21, 0 + .dw 0xafc0, 0xc82d, 0xafff, 0xc82d, 0x21, 0 + .dw 0xb040, 0xc82d, 0xb07f, 0xc82d, 0x21, 0 + .dw 0xb0c0, 0xc82d, 0xb0ff, 0xc82d, 0x21, 0 + .dw 0xb140, 0xc82d, 0xb17f, 0xc82d, 0x21, 0 + .dw 0xb1c0, 0xc82d, 0xb1ff, 0xc82d, 0x21, 0 + .dw 0xb240, 0xc82d, 0xb27f, 0xc82d, 0x21, 0 + .dw 0xb2c0, 0xc82d, 0xb2ff, 0xc82d, 0x21, 0 + .dw 0xb340, 0xc82d, 0xb37f, 0xc82d, 0x21, 0 + .dw 0xb3c0, 0xc82d, 0xb3ff, 0xc82d, 0x21, 0 + .dw 0xb440, 0xc82d, 0xb47f, 0xc82d, 0x21, 0 + .dw 0xb4c0, 0xc82d, 0xb4ff, 0xc82d, 0x21, 0 + .dw 0xb540, 0xc82d, 0xb57f, 0xc82d, 0x21, 0 + .dw 0xb5c0, 0xc82d, 0xb5ff, 0xc82d, 0x21, 0 + .dw 0xb640, 0xc82d, 0xb67f, 0xc82d, 0x21, 0 + .dw 0xb6c0, 0xc82d, 0xb6ff, 0xc82d, 0x21, 0 + .dw 0xb740, 0xc82d, 0xb77f, 0xc82d, 0x21, 0 + .dw 0xb7c0, 0xc82d, 0xb7ff, 0xc82d, 0x21, 0 + .dw 0xb840, 0xc82d, 0xb87f, 0xc82d, 0x21, 0 + .dw 0xb8c0, 0xc82d, 0xb8ff, 0xc82d, 0x21, 0 + .dw 0xb940, 0xc82d, 0xb97f, 0xc82d, 0x21, 0 + .dw 0xb9c0, 0xc82d, 0xbfff, 0xc82d, 0x21, 0 + .dw 0xc040, 0xc82d, 0xc07f, 0xc82d, 0x21, 0 + .dw 0xc0c0, 0xc82d, 0xc0ff, 0xc82d, 0x21, 0 + .dw 0xc140, 0xc82d, 0xc17f, 0xc82d, 0x21, 0 + .dw 0xc1c0, 0xc82d, 0xc1ff, 0xc82d, 0x21, 0 + .dw 0xc240, 0xc82d, 0xc27f, 0xc82d, 0x21, 0 + .dw 0xc2c0, 0xc82d, 0xc2ff, 0xc82d, 0x21, 0 + .dw 0xc340, 0xc82d, 0xc37f, 0xc82d, 0x21, 0 + .dw 0xc3c0, 0xc82d, 0xc3ff, 0xc82d, 0x21, 0 + .dw 0xc440, 0xc82d, 0xc47f, 0xc82d, 0x21, 0 + .dw 0xc4c0, 0xc82d, 0xc4ff, 0xc82d, 0x21, 0 + .dw 0xc540, 0xc82d, 0xc57f, 0xc82d, 0x21, 0 + .dw 0xc5c0, 0xc82d, 0xc5ff, 0xc82d, 0x21, 0 + .dw 0xc640, 0xc82d, 0xc67f, 0xc82d, 0x21, 0 + .dw 0xc6c0, 0xc82d, 0xc6ff, 0xc82d, 0x21, 0 + .dw 0xc740, 0xc82d, 0xc77f, 0xc82d, 0x21, 0 + .dw 0xc7c0, 0xc82d, 0xc7ff, 0xc82d, 0x21, 0 + .dw 0xc840, 0xc82d, 0xc87f, 0xc82d, 0x21, 0 + .dw 0xc8c0, 0xc82d, 0xc8ff, 0xc82d, 0x21, 0 + .dw 0xc940, 0xc82d, 0xc97f, 0xc82d, 0x21, 0 + .dw 0xc9c0, 0xc82d, 0xc9ff, 0xc82d, 0x21, 0 + .dw 0xca40, 0xc82d, 0xca7f, 0xc82d, 0x21, 0 + .dw 0xcac0, 0xc82d, 0xcaff, 0xc82d, 0x21, 0 + .dw 0xcb40, 0xc82d, 0xcb7f, 0xc82d, 0x21, 0 + .dw 0xcbc0, 0xc82d, 0xcbff, 0xc82d, 0x21, 0 + .dw 0xcc40, 0xc82d, 0xcc7f, 0xc82d, 0x21, 0 + .dw 0xccc0, 0xc82d, 0xccff, 0xc82d, 0x21, 0 + .dw 0xcd40, 0xc82d, 0xcd7f, 0xc82d, 0x21, 0 + .dw 0xcdc0, 0xc82d, 0xcdff, 0xc82d, 0x21, 0 + .dw 0xce40, 0xc82d, 0xce7f, 0xc82d, 0x21, 0 + .dw 0xcec0, 0xc82d, 0xceff, 0xc82d, 0x21, 0 + .dw 0xcf40, 0xc82d, 0xcf7f, 0xc82d, 0x21, 0 + .dw 0xcfc0, 0xc82d, 0xcfff, 0xc82d, 0x21, 0 + .dw 0xd040, 0xc82d, 0xd07f, 0xc82d, 0x21, 0 + .dw 0xd0c0, 0xc82d, 0xd0ff, 0xc82d, 0x21, 0 + .dw 0xd140, 0xc82d, 0xd17f, 0xc82d, 0x21, 0 + .dw 0xd1c0, 0xc82d, 0xd1ff, 0xc82d, 0x21, 0 + .dw 0xd240, 0xc82d, 0xd27f, 0xc82d, 0x21, 0 + .dw 0xd2c0, 0xc82d, 0xd2ff, 0xc82d, 0x21, 0 + .dw 0xd340, 0xc82d, 0xd37f, 0xc82d, 0x21, 0 + .dw 0xd3c0, 0xc82d, 0xd3ff, 0xc82d, 0x21, 0 + .dw 0xd440, 0xc82d, 0xd47f, 0xc82d, 0x21, 0 + .dw 0xd4c0, 0xc82d, 0xd4ff, 0xc82d, 0x21, 0 + .dw 0xd540, 0xc82d, 0xd57f, 0xc82d, 0x21, 0 + .dw 0xd5c0, 0xc82d, 0xd5ff, 0xc82d, 0x21, 0 + .dw 0xd640, 0xc82d, 0xd67f, 0xc82d, 0x21, 0 + .dw 0xd6c0, 0xc82d, 0xd6ff, 0xc82d, 0x21, 0 + .dw 0xd740, 0xc82d, 0xd77f, 0xc82d, 0x21, 0 + .dw 0xd7c0, 0xc82d, 0xd7ff, 0xc82d, 0x21, 0 + .dw 0xd840, 0xc82d, 0xd87f, 0xc82d, 0x21, 0 + .dw 0xd8c0, 0xc82d, 0xd8ff, 0xc82d, 0x21, 0 + .dw 0xd940, 0xc82d, 0xd97f, 0xc82d, 0x21, 0 + .dw 0xd9c0, 0xc82d, 0xdfff, 0xc82d, 0x21, 0 + .dw 0xe040, 0xc82d, 0xe07f, 0xc82d, 0x21, 0 + .dw 0xe0c0, 0xc82d, 0xe0ff, 0xc82d, 0x21, 0 + .dw 0xe140, 0xc82d, 0xe17f, 0xc82d, 0x21, 0 + .dw 0xe1c0, 0xc82d, 0xe1ff, 0xc82d, 0x21, 0 + .dw 0xe240, 0xc82d, 0xe27f, 0xc82d, 0x21, 0 + .dw 0xe2c0, 0xc82d, 0xe2ff, 0xc82d, 0x21, 0 + .dw 0xe340, 0xc82d, 0xe37f, 0xc82d, 0x21, 0 + .dw 0xe3c0, 0xc82d, 0xe3ff, 0xc82d, 0x21, 0 + .dw 0xe440, 0xc82d, 0xe47f, 0xc82d, 0x21, 0 + .dw 0xe4c0, 0xc82d, 0xe4ff, 0xc82d, 0x21, 0 + .dw 0xe540, 0xc82d, 0xe57f, 0xc82d, 0x21, 0 + .dw 0xe5c0, 0xc82d, 0xe5ff, 0xc82d, 0x21, 0 + .dw 0xe640, 0xc82d, 0xe67f, 0xc82d, 0x21, 0 + .dw 0xe6c0, 0xc82d, 0xe6ff, 0xc82d, 0x21, 0 + .dw 0xe740, 0xc82d, 0xe77f, 0xc82d, 0x21, 0 + .dw 0xe7c0, 0xc82d, 0xe7ff, 0xc82d, 0x21, 0 + .dw 0xe840, 0xc82d, 0xe87f, 0xc82d, 0x21, 0 + .dw 0xe8c0, 0xc82d, 0xe8ff, 0xc82d, 0x21, 0 + .dw 0xe940, 0xc82d, 0xe97f, 0xc82d, 0x21, 0 + .dw 0xe9c0, 0xc82d, 0xe9ff, 0xc82d, 0x21, 0 + .dw 0xea40, 0xc82d, 0xea7f, 0xc82d, 0x21, 0 + .dw 0xeac0, 0xc82d, 0xeaff, 0xc82d, 0x21, 0 + .dw 0xeb40, 0xc82d, 0xeb7f, 0xc82d, 0x21, 0 + .dw 0xebc0, 0xc82d, 0xebff, 0xc82d, 0x21, 0 + .dw 0xec40, 0xc82d, 0xec7f, 0xc82d, 0x21, 0 + .dw 0xecc0, 0xc82d, 0xecff, 0xc82d, 0x21, 0 + .dw 0xed40, 0xc82d, 0xed7f, 0xc82d, 0x21, 0 + .dw 0xedc0, 0xc82d, 0xedff, 0xc82d, 0x21, 0 + .dw 0xee40, 0xc82d, 0xee7f, 0xc82d, 0x21, 0 + .dw 0xeec0, 0xc82d, 0xeeff, 0xc82d, 0x21, 0 + .dw 0xef40, 0xc82d, 0xef7f, 0xc82d, 0x21, 0 + .dw 0xefc0, 0xc82d, 0xefff, 0xc82d, 0x21, 0 + .dw 0xf040, 0xc82d, 0xf07f, 0xc82d, 0x21, 0 + .dw 0xf0c0, 0xc82d, 0xf0ff, 0xc82d, 0x21, 0 + .dw 0xf140, 0xc82d, 0xf17f, 0xc82d, 0x21, 0 + .dw 0xf1c0, 0xc82d, 0xf1ff, 0xc82d, 0x21, 0 + .dw 0xf240, 0xc82d, 0xf27f, 0xc82d, 0x21, 0 + .dw 0xf2c0, 0xc82d, 0xf2ff, 0xc82d, 0x21, 0 + .dw 0xf340, 0xc82d, 0xf37f, 0xc82d, 0x21, 0 + .dw 0xf3c0, 0xc82d, 0xf3ff, 0xc82d, 0x21, 0 + .dw 0xf440, 0xc82d, 0xf47f, 0xc82d, 0x21, 0 + .dw 0xf4c0, 0xc82d, 0xf4ff, 0xc82d, 0x21, 0 + .dw 0xf540, 0xc82d, 0xf57f, 0xc82d, 0x21, 0 + .dw 0xf5c0, 0xc82d, 0xf5ff, 0xc82d, 0x21, 0 + .dw 0xf640, 0xc82d, 0xf67f, 0xc82d, 0x21, 0 + .dw 0xf6c0, 0xc82d, 0xf6ff, 0xc82d, 0x21, 0 + .dw 0xf740, 0xc82d, 0xf77f, 0xc82d, 0x21, 0 + .dw 0xf7c0, 0xc82d, 0xf7ff, 0xc82d, 0x21, 0 + .dw 0xf840, 0xc82d, 0xf87f, 0xc82d, 0x21, 0 + .dw 0xf8c0, 0xc82d, 0xf8ff, 0xc82d, 0x21, 0 + .dw 0xf940, 0xc82d, 0xf97f, 0xc82d, 0x21, 0 + .dw 0xf9c0, 0xc82d, 0xffff, 0xc82d, 0x21, 0 + .dw 0x0040, 0xc82e, 0x007f, 0xc82e, 0x21, 0 + .dw 0x00c0, 0xc82e, 0x00ff, 0xc82e, 0x21, 0 + .dw 0x0140, 0xc82e, 0x017f, 0xc82e, 0x21, 0 + .dw 0x01c0, 0xc82e, 0x01ff, 0xc82e, 0x21, 0 + .dw 0x0240, 0xc82e, 0x027f, 0xc82e, 0x21, 0 + .dw 0x02c0, 0xc82e, 0x02ff, 0xc82e, 0x21, 0 + .dw 0x0340, 0xc82e, 0x037f, 0xc82e, 0x21, 0 + .dw 0x03c0, 0xc82e, 0x03ff, 0xc82e, 0x21, 0 + .dw 0x0440, 0xc82e, 0x047f, 0xc82e, 0x21, 0 + .dw 0x04c0, 0xc82e, 0x04ff, 0xc82e, 0x21, 0 + .dw 0x0540, 0xc82e, 0x057f, 0xc82e, 0x21, 0 + .dw 0x05c0, 0xc82e, 0x05ff, 0xc82e, 0x21, 0 + .dw 0x0640, 0xc82e, 0x067f, 0xc82e, 0x21, 0 + .dw 0x06c0, 0xc82e, 0x06ff, 0xc82e, 0x21, 0 + .dw 0x0740, 0xc82e, 0x077f, 0xc82e, 0x21, 0 + .dw 0x07c0, 0xc82e, 0x07ff, 0xc82e, 0x21, 0 + .dw 0x0840, 0xc82e, 0x087f, 0xc82e, 0x21, 0 + .dw 0x08c0, 0xc82e, 0x08ff, 0xc82e, 0x21, 0 + .dw 0x0940, 0xc82e, 0x097f, 0xc82e, 0x21, 0 + .dw 0x09c0, 0xc82e, 0x09ff, 0xc82e, 0x21, 0 + .dw 0x0a40, 0xc82e, 0x0a7f, 0xc82e, 0x21, 0 + .dw 0x0ac0, 0xc82e, 0x0aff, 0xc82e, 0x21, 0 + .dw 0x0b40, 0xc82e, 0x0b7f, 0xc82e, 0x21, 0 + .dw 0x0bc0, 0xc82e, 0x0bff, 0xc82e, 0x21, 0 + .dw 0x0c40, 0xc82e, 0x0c7f, 0xc82e, 0x21, 0 + .dw 0x0cc0, 0xc82e, 0x0cff, 0xc82e, 0x21, 0 + .dw 0x0d40, 0xc82e, 0x0d7f, 0xc82e, 0x21, 0 + .dw 0x0dc0, 0xc82e, 0x0dff, 0xc82e, 0x21, 0 + .dw 0x0e40, 0xc82e, 0x0e7f, 0xc82e, 0x21, 0 + .dw 0x0ec0, 0xc82e, 0x0eff, 0xc82e, 0x21, 0 + .dw 0x0f40, 0xc82e, 0x0f7f, 0xc82e, 0x21, 0 + .dw 0x0fc0, 0xc82e, 0x0fff, 0xc82e, 0x21, 0 + .dw 0x1040, 0xc82e, 0x107f, 0xc82e, 0x21, 0 + .dw 0x10c0, 0xc82e, 0x10ff, 0xc82e, 0x21, 0 + .dw 0x1140, 0xc82e, 0x117f, 0xc82e, 0x21, 0 + .dw 0x11c0, 0xc82e, 0x11ff, 0xc82e, 0x21, 0 + .dw 0x1240, 0xc82e, 0x127f, 0xc82e, 0x21, 0 + .dw 0x12c0, 0xc82e, 0x12ff, 0xc82e, 0x21, 0 + .dw 0x1340, 0xc82e, 0x137f, 0xc82e, 0x21, 0 + .dw 0x13c0, 0xc82e, 0x13ff, 0xc82e, 0x21, 0 + .dw 0x1440, 0xc82e, 0x147f, 0xc82e, 0x21, 0 + .dw 0x14c0, 0xc82e, 0x14ff, 0xc82e, 0x21, 0 + .dw 0x1540, 0xc82e, 0x157f, 0xc82e, 0x21, 0 + .dw 0x15c0, 0xc82e, 0x15ff, 0xc82e, 0x21, 0 + .dw 0x1640, 0xc82e, 0x167f, 0xc82e, 0x21, 0 + .dw 0x16c0, 0xc82e, 0x16ff, 0xc82e, 0x21, 0 + .dw 0x1740, 0xc82e, 0x177f, 0xc82e, 0x21, 0 + .dw 0x17c0, 0xc82e, 0x17ff, 0xc82e, 0x21, 0 + .dw 0x1840, 0xc82e, 0x187f, 0xc82e, 0x21, 0 + .dw 0x18c0, 0xc82e, 0x18ff, 0xc82e, 0x21, 0 + .dw 0x1940, 0xc82e, 0x197f, 0xc82e, 0x21, 0 + .dw 0x19c0, 0xc82e, 0x1fff, 0xc82e, 0x21, 0 + .dw 0x2040, 0xc82e, 0x207f, 0xc82e, 0x21, 0 + .dw 0x20c0, 0xc82e, 0x20ff, 0xc82e, 0x21, 0 + .dw 0x2140, 0xc82e, 0x217f, 0xc82e, 0x21, 0 + .dw 0x21c0, 0xc82e, 0x21ff, 0xc82e, 0x21, 0 + .dw 0x2240, 0xc82e, 0x227f, 0xc82e, 0x21, 0 + .dw 0x22c0, 0xc82e, 0x22ff, 0xc82e, 0x21, 0 + .dw 0x2340, 0xc82e, 0x237f, 0xc82e, 0x21, 0 + .dw 0x23c0, 0xc82e, 0x23ff, 0xc82e, 0x21, 0 + .dw 0x2440, 0xc82e, 0x247f, 0xc82e, 0x21, 0 + .dw 0x24c0, 0xc82e, 0x24ff, 0xc82e, 0x21, 0 + .dw 0x2540, 0xc82e, 0x257f, 0xc82e, 0x21, 0 + .dw 0x25c0, 0xc82e, 0x25ff, 0xc82e, 0x21, 0 + .dw 0x2640, 0xc82e, 0x267f, 0xc82e, 0x21, 0 + .dw 0x26c0, 0xc82e, 0x26ff, 0xc82e, 0x21, 0 + .dw 0x2740, 0xc82e, 0x277f, 0xc82e, 0x21, 0 + .dw 0x27c0, 0xc82e, 0x27ff, 0xc82e, 0x21, 0 + .dw 0x2840, 0xc82e, 0x287f, 0xc82e, 0x21, 0 + .dw 0x28c0, 0xc82e, 0x28ff, 0xc82e, 0x21, 0 + .dw 0x2940, 0xc82e, 0x297f, 0xc82e, 0x21, 0 + .dw 0x29c0, 0xc82e, 0x29ff, 0xc82e, 0x21, 0 + .dw 0x2a40, 0xc82e, 0x2a7f, 0xc82e, 0x21, 0 + .dw 0x2ac0, 0xc82e, 0x2aff, 0xc82e, 0x21, 0 + .dw 0x2b40, 0xc82e, 0x2b7f, 0xc82e, 0x21, 0 + .dw 0x2bc0, 0xc82e, 0x2bff, 0xc82e, 0x21, 0 + .dw 0x2c40, 0xc82e, 0x2c7f, 0xc82e, 0x21, 0 + .dw 0x2cc0, 0xc82e, 0x2cff, 0xc82e, 0x21, 0 + .dw 0x2d40, 0xc82e, 0x2d7f, 0xc82e, 0x21, 0 + .dw 0x2dc0, 0xc82e, 0x2dff, 0xc82e, 0x21, 0 + .dw 0x2e40, 0xc82e, 0x2e7f, 0xc82e, 0x21, 0 + .dw 0x2ec0, 0xc82e, 0x2eff, 0xc82e, 0x21, 0 + .dw 0x2f40, 0xc82e, 0x2f7f, 0xc82e, 0x21, 0 + .dw 0x2fc0, 0xc82e, 0x2fff, 0xc82e, 0x21, 0 + .dw 0x3040, 0xc82e, 0x307f, 0xc82e, 0x21, 0 + .dw 0x30c0, 0xc82e, 0x30ff, 0xc82e, 0x21, 0 + .dw 0x3140, 0xc82e, 0x317f, 0xc82e, 0x21, 0 + .dw 0x31c0, 0xc82e, 0x31ff, 0xc82e, 0x21, 0 + .dw 0x3240, 0xc82e, 0x327f, 0xc82e, 0x21, 0 + .dw 0x32c0, 0xc82e, 0x32ff, 0xc82e, 0x21, 0 + .dw 0x3340, 0xc82e, 0x337f, 0xc82e, 0x21, 0 + .dw 0x33c0, 0xc82e, 0x33ff, 0xc82e, 0x21, 0 + .dw 0x3440, 0xc82e, 0x347f, 0xc82e, 0x21, 0 + .dw 0x34c0, 0xc82e, 0x34ff, 0xc82e, 0x21, 0 + .dw 0x3540, 0xc82e, 0x357f, 0xc82e, 0x21, 0 + .dw 0x35c0, 0xc82e, 0x35ff, 0xc82e, 0x21, 0 + .dw 0x3640, 0xc82e, 0x367f, 0xc82e, 0x21, 0 + .dw 0x36c0, 0xc82e, 0x36ff, 0xc82e, 0x21, 0 + .dw 0x3740, 0xc82e, 0x377f, 0xc82e, 0x21, 0 + .dw 0x37c0, 0xc82e, 0x37ff, 0xc82e, 0x21, 0 + .dw 0x3840, 0xc82e, 0x387f, 0xc82e, 0x21, 0 + .dw 0x38c0, 0xc82e, 0x38ff, 0xc82e, 0x21, 0 + .dw 0x3940, 0xc82e, 0x397f, 0xc82e, 0x21, 0 + .dw 0x39c0, 0xc82e, 0x3fff, 0xc82e, 0x21, 0 + .dw 0x4040, 0xc82e, 0x407f, 0xc82e, 0x21, 0 + .dw 0x40c0, 0xc82e, 0x40ff, 0xc82e, 0x21, 0 + .dw 0x4140, 0xc82e, 0x417f, 0xc82e, 0x21, 0 + .dw 0x41c0, 0xc82e, 0x41ff, 0xc82e, 0x21, 0 + .dw 0x4240, 0xc82e, 0x427f, 0xc82e, 0x21, 0 + .dw 0x42c0, 0xc82e, 0x42ff, 0xc82e, 0x21, 0 + .dw 0x4340, 0xc82e, 0x437f, 0xc82e, 0x21, 0 + .dw 0x43c0, 0xc82e, 0x43ff, 0xc82e, 0x21, 0 + .dw 0x4440, 0xc82e, 0x447f, 0xc82e, 0x21, 0 + .dw 0x44c0, 0xc82e, 0x44ff, 0xc82e, 0x21, 0 + .dw 0x4540, 0xc82e, 0x457f, 0xc82e, 0x21, 0 + .dw 0x45c0, 0xc82e, 0x45ff, 0xc82e, 0x21, 0 + .dw 0x4640, 0xc82e, 0x467f, 0xc82e, 0x21, 0 + .dw 0x46c0, 0xc82e, 0x46ff, 0xc82e, 0x21, 0 + .dw 0x4740, 0xc82e, 0x477f, 0xc82e, 0x21, 0 + .dw 0x47c0, 0xc82e, 0x47ff, 0xc82e, 0x21, 0 + .dw 0x4840, 0xc82e, 0x487f, 0xc82e, 0x21, 0 + .dw 0x48c0, 0xc82e, 0x48ff, 0xc82e, 0x21, 0 + .dw 0x4940, 0xc82e, 0x497f, 0xc82e, 0x21, 0 + .dw 0x49c0, 0xc82e, 0x49ff, 0xc82e, 0x21, 0 + .dw 0x4a40, 0xc82e, 0x4a7f, 0xc82e, 0x21, 0 + .dw 0x4ac0, 0xc82e, 0x4aff, 0xc82e, 0x21, 0 + .dw 0x4b40, 0xc82e, 0x4b7f, 0xc82e, 0x21, 0 + .dw 0x4bc0, 0xc82e, 0x4bff, 0xc82e, 0x21, 0 + .dw 0x4c40, 0xc82e, 0x4c7f, 0xc82e, 0x21, 0 + .dw 0x4cc0, 0xc82e, 0x4cff, 0xc82e, 0x21, 0 + .dw 0x4d40, 0xc82e, 0x4d7f, 0xc82e, 0x21, 0 + .dw 0x4dc0, 0xc82e, 0x4dff, 0xc82e, 0x21, 0 + .dw 0x4e40, 0xc82e, 0x4e7f, 0xc82e, 0x21, 0 + .dw 0x4ec0, 0xc82e, 0x4eff, 0xc82e, 0x21, 0 + .dw 0x4f40, 0xc82e, 0x4f7f, 0xc82e, 0x21, 0 + .dw 0x4fc0, 0xc82e, 0x4fff, 0xc82e, 0x21, 0 + .dw 0x5040, 0xc82e, 0x507f, 0xc82e, 0x21, 0 + .dw 0x50c0, 0xc82e, 0x50ff, 0xc82e, 0x21, 0 + .dw 0x5140, 0xc82e, 0x517f, 0xc82e, 0x21, 0 + .dw 0x51c0, 0xc82e, 0x51ff, 0xc82e, 0x21, 0 + .dw 0x5240, 0xc82e, 0x527f, 0xc82e, 0x21, 0 + .dw 0x52c0, 0xc82e, 0x52ff, 0xc82e, 0x21, 0 + .dw 0x5340, 0xc82e, 0x537f, 0xc82e, 0x21, 0 + .dw 0x53c0, 0xc82e, 0x53ff, 0xc82e, 0x21, 0 + .dw 0x5440, 0xc82e, 0x547f, 0xc82e, 0x21, 0 + .dw 0x54c0, 0xc82e, 0x54ff, 0xc82e, 0x21, 0 + .dw 0x5540, 0xc82e, 0x557f, 0xc82e, 0x21, 0 + .dw 0x55c0, 0xc82e, 0x55ff, 0xc82e, 0x21, 0 + .dw 0x5640, 0xc82e, 0x567f, 0xc82e, 0x21, 0 + .dw 0x56c0, 0xc82e, 0x56ff, 0xc82e, 0x21, 0 + .dw 0x5740, 0xc82e, 0x577f, 0xc82e, 0x21, 0 + .dw 0x57c0, 0xc82e, 0x57ff, 0xc82e, 0x21, 0 + .dw 0x5840, 0xc82e, 0x587f, 0xc82e, 0x21, 0 + .dw 0x58c0, 0xc82e, 0x58ff, 0xc82e, 0x21, 0 + .dw 0x5940, 0xc82e, 0x597f, 0xc82e, 0x21, 0 + .dw 0x59c0, 0xc82e, 0x5fff, 0xc82e, 0x21, 0 + .dw 0x6040, 0xc82e, 0x607f, 0xc82e, 0x21, 0 + .dw 0x60c0, 0xc82e, 0x60ff, 0xc82e, 0x21, 0 + .dw 0x6140, 0xc82e, 0x617f, 0xc82e, 0x21, 0 + .dw 0x61c0, 0xc82e, 0x61ff, 0xc82e, 0x21, 0 + .dw 0x6240, 0xc82e, 0x627f, 0xc82e, 0x21, 0 + .dw 0x62c0, 0xc82e, 0x62ff, 0xc82e, 0x21, 0 + .dw 0x6340, 0xc82e, 0x637f, 0xc82e, 0x21, 0 + .dw 0x63c0, 0xc82e, 0x63ff, 0xc82e, 0x21, 0 + .dw 0x6440, 0xc82e, 0x647f, 0xc82e, 0x21, 0 + .dw 0x64c0, 0xc82e, 0x64ff, 0xc82e, 0x21, 0 + .dw 0x6540, 0xc82e, 0x657f, 0xc82e, 0x21, 0 + .dw 0x65c0, 0xc82e, 0x65ff, 0xc82e, 0x21, 0 + .dw 0x6640, 0xc82e, 0x667f, 0xc82e, 0x21, 0 + .dw 0x66c0, 0xc82e, 0x66ff, 0xc82e, 0x21, 0 + .dw 0x6740, 0xc82e, 0x677f, 0xc82e, 0x21, 0 + .dw 0x67c0, 0xc82e, 0x67ff, 0xc82e, 0x21, 0 + .dw 0x6840, 0xc82e, 0x687f, 0xc82e, 0x21, 0 + .dw 0x68c0, 0xc82e, 0x68ff, 0xc82e, 0x21, 0 + .dw 0x6940, 0xc82e, 0x697f, 0xc82e, 0x21, 0 + .dw 0x69c0, 0xc82e, 0x69ff, 0xc82e, 0x21, 0 + .dw 0x6a40, 0xc82e, 0x6a7f, 0xc82e, 0x21, 0 + .dw 0x6ac0, 0xc82e, 0x6aff, 0xc82e, 0x21, 0 + .dw 0x6b40, 0xc82e, 0x6b7f, 0xc82e, 0x21, 0 + .dw 0x6bc0, 0xc82e, 0x6bff, 0xc82e, 0x21, 0 + .dw 0x6c40, 0xc82e, 0x6c7f, 0xc82e, 0x21, 0 + .dw 0x6cc0, 0xc82e, 0x6cff, 0xc82e, 0x21, 0 + .dw 0x6d40, 0xc82e, 0x6d7f, 0xc82e, 0x21, 0 + .dw 0x6dc0, 0xc82e, 0x6dff, 0xc82e, 0x21, 0 + .dw 0x6e40, 0xc82e, 0x6e7f, 0xc82e, 0x21, 0 + .dw 0x6ec0, 0xc82e, 0x6eff, 0xc82e, 0x21, 0 + .dw 0x6f40, 0xc82e, 0x6f7f, 0xc82e, 0x21, 0 + .dw 0x6fc0, 0xc82e, 0x6fff, 0xc82e, 0x21, 0 + .dw 0x7040, 0xc82e, 0x707f, 0xc82e, 0x21, 0 + .dw 0x70c0, 0xc82e, 0x70ff, 0xc82e, 0x21, 0 + .dw 0x7140, 0xc82e, 0x717f, 0xc82e, 0x21, 0 + .dw 0x71c0, 0xc82e, 0x71ff, 0xc82e, 0x21, 0 + .dw 0x7240, 0xc82e, 0x727f, 0xc82e, 0x21, 0 + .dw 0x72c0, 0xc82e, 0x72ff, 0xc82e, 0x21, 0 + .dw 0x7340, 0xc82e, 0x737f, 0xc82e, 0x21, 0 + .dw 0x73c0, 0xc82e, 0x73ff, 0xc82e, 0x21, 0 + .dw 0x7440, 0xc82e, 0x747f, 0xc82e, 0x21, 0 + .dw 0x74c0, 0xc82e, 0x74ff, 0xc82e, 0x21, 0 + .dw 0x7540, 0xc82e, 0x757f, 0xc82e, 0x21, 0 + .dw 0x75c0, 0xc82e, 0x75ff, 0xc82e, 0x21, 0 + .dw 0x7640, 0xc82e, 0x767f, 0xc82e, 0x21, 0 + .dw 0x76c0, 0xc82e, 0x76ff, 0xc82e, 0x21, 0 + .dw 0x7740, 0xc82e, 0x777f, 0xc82e, 0x21, 0 + .dw 0x77c0, 0xc82e, 0x77ff, 0xc82e, 0x21, 0 + .dw 0x7840, 0xc82e, 0x787f, 0xc82e, 0x21, 0 + .dw 0x78c0, 0xc82e, 0x78ff, 0xc82e, 0x21, 0 + .dw 0x7940, 0xc82e, 0x797f, 0xc82e, 0x21, 0 + .dw 0x79c0, 0xc82e, 0x7fff, 0xc82e, 0x21, 0 + .dw 0x8040, 0xc82e, 0x807f, 0xc82e, 0x21, 0 + .dw 0x80c0, 0xc82e, 0x80ff, 0xc82e, 0x21, 0 + .dw 0x8140, 0xc82e, 0x817f, 0xc82e, 0x21, 0 + .dw 0x81c0, 0xc82e, 0x81ff, 0xc82e, 0x21, 0 + .dw 0x8240, 0xc82e, 0x827f, 0xc82e, 0x21, 0 + .dw 0x82c0, 0xc82e, 0x82ff, 0xc82e, 0x21, 0 + .dw 0x8340, 0xc82e, 0x837f, 0xc82e, 0x21, 0 + .dw 0x83c0, 0xc82e, 0x83ff, 0xc82e, 0x21, 0 + .dw 0x8440, 0xc82e, 0x847f, 0xc82e, 0x21, 0 + .dw 0x84c0, 0xc82e, 0x84ff, 0xc82e, 0x21, 0 + .dw 0x8540, 0xc82e, 0x857f, 0xc82e, 0x21, 0 + .dw 0x85c0, 0xc82e, 0x85ff, 0xc82e, 0x21, 0 + .dw 0x8640, 0xc82e, 0x867f, 0xc82e, 0x21, 0 + .dw 0x86c0, 0xc82e, 0x86ff, 0xc82e, 0x21, 0 + .dw 0x8740, 0xc82e, 0x877f, 0xc82e, 0x21, 0 + .dw 0x87c0, 0xc82e, 0x87ff, 0xc82e, 0x21, 0 + .dw 0x8840, 0xc82e, 0x887f, 0xc82e, 0x21, 0 + .dw 0x88c0, 0xc82e, 0x88ff, 0xc82e, 0x21, 0 + .dw 0x8940, 0xc82e, 0x897f, 0xc82e, 0x21, 0 + .dw 0x89c0, 0xc82e, 0x89ff, 0xc82e, 0x21, 0 + .dw 0x8a40, 0xc82e, 0x8a7f, 0xc82e, 0x21, 0 + .dw 0x8ac0, 0xc82e, 0x8aff, 0xc82e, 0x21, 0 + .dw 0x8b40, 0xc82e, 0x8b7f, 0xc82e, 0x21, 0 + .dw 0x8bc0, 0xc82e, 0x8bff, 0xc82e, 0x21, 0 + .dw 0x8c40, 0xc82e, 0x8c7f, 0xc82e, 0x21, 0 + .dw 0x8cc0, 0xc82e, 0x8cff, 0xc82e, 0x21, 0 + .dw 0x8d40, 0xc82e, 0x8d7f, 0xc82e, 0x21, 0 + .dw 0x8dc0, 0xc82e, 0x8dff, 0xc82e, 0x21, 0 + .dw 0x8e40, 0xc82e, 0x8e7f, 0xc82e, 0x21, 0 + .dw 0x8ec0, 0xc82e, 0x8eff, 0xc82e, 0x21, 0 + .dw 0x8f40, 0xc82e, 0x8f7f, 0xc82e, 0x21, 0 + .dw 0x8fc0, 0xc82e, 0x8fff, 0xc82e, 0x21, 0 + .dw 0x9040, 0xc82e, 0x907f, 0xc82e, 0x21, 0 + .dw 0x90c0, 0xc82e, 0x90ff, 0xc82e, 0x21, 0 + .dw 0x9140, 0xc82e, 0x917f, 0xc82e, 0x21, 0 + .dw 0x91c0, 0xc82e, 0x91ff, 0xc82e, 0x21, 0 + .dw 0x9240, 0xc82e, 0x927f, 0xc82e, 0x21, 0 + .dw 0x92c0, 0xc82e, 0x92ff, 0xc82e, 0x21, 0 + .dw 0x9340, 0xc82e, 0x937f, 0xc82e, 0x21, 0 + .dw 0x93c0, 0xc82e, 0x93ff, 0xc82e, 0x21, 0 + .dw 0x9440, 0xc82e, 0x947f, 0xc82e, 0x21, 0 + .dw 0x94c0, 0xc82e, 0x94ff, 0xc82e, 0x21, 0 + .dw 0x9540, 0xc82e, 0x957f, 0xc82e, 0x21, 0 + .dw 0x95c0, 0xc82e, 0x95ff, 0xc82e, 0x21, 0 + .dw 0x9640, 0xc82e, 0x967f, 0xc82e, 0x21, 0 + .dw 0x96c0, 0xc82e, 0x96ff, 0xc82e, 0x21, 0 + .dw 0x9740, 0xc82e, 0x977f, 0xc82e, 0x21, 0 + .dw 0x97c0, 0xc82e, 0x97ff, 0xc82e, 0x21, 0 + .dw 0x9840, 0xc82e, 0x987f, 0xc82e, 0x21, 0 + .dw 0x98c0, 0xc82e, 0x98ff, 0xc82e, 0x21, 0 + .dw 0x9940, 0xc82e, 0x997f, 0xc82e, 0x21, 0 + .dw 0x99c0, 0xc82e, 0x9fff, 0xc82e, 0x21, 0 + .dw 0xa040, 0xc82e, 0xa07f, 0xc82e, 0x21, 0 + .dw 0xa0c0, 0xc82e, 0xa0ff, 0xc82e, 0x21, 0 + .dw 0xa140, 0xc82e, 0xa17f, 0xc82e, 0x21, 0 + .dw 0xa1c0, 0xc82e, 0xa1ff, 0xc82e, 0x21, 0 + .dw 0xa240, 0xc82e, 0xa27f, 0xc82e, 0x21, 0 + .dw 0xa2c0, 0xc82e, 0xa2ff, 0xc82e, 0x21, 0 + .dw 0xa340, 0xc82e, 0xa37f, 0xc82e, 0x21, 0 + .dw 0xa3c0, 0xc82e, 0xa3ff, 0xc82e, 0x21, 0 + .dw 0xa440, 0xc82e, 0xa47f, 0xc82e, 0x21, 0 + .dw 0xa4c0, 0xc82e, 0xa4ff, 0xc82e, 0x21, 0 + .dw 0xa540, 0xc82e, 0xa57f, 0xc82e, 0x21, 0 + .dw 0xa5c0, 0xc82e, 0xa5ff, 0xc82e, 0x21, 0 + .dw 0xa640, 0xc82e, 0xa67f, 0xc82e, 0x21, 0 + .dw 0xa6c0, 0xc82e, 0xa6ff, 0xc82e, 0x21, 0 + .dw 0xa740, 0xc82e, 0xa77f, 0xc82e, 0x21, 0 + .dw 0xa7c0, 0xc82e, 0xa7ff, 0xc82e, 0x21, 0 + .dw 0xa840, 0xc82e, 0xa87f, 0xc82e, 0x21, 0 + .dw 0xa8c0, 0xc82e, 0xa8ff, 0xc82e, 0x21, 0 + .dw 0xa940, 0xc82e, 0xa97f, 0xc82e, 0x21, 0 + .dw 0xa9c0, 0xc82e, 0xa9ff, 0xc82e, 0x21, 0 + .dw 0xaa40, 0xc82e, 0xaa7f, 0xc82e, 0x21, 0 + .dw 0xaac0, 0xc82e, 0xaaff, 0xc82e, 0x21, 0 + .dw 0xab40, 0xc82e, 0xab7f, 0xc82e, 0x21, 0 + .dw 0xabc0, 0xc82e, 0xabff, 0xc82e, 0x21, 0 + .dw 0xac40, 0xc82e, 0xac7f, 0xc82e, 0x21, 0 + .dw 0xacc0, 0xc82e, 0xacff, 0xc82e, 0x21, 0 + .dw 0xad40, 0xc82e, 0xad7f, 0xc82e, 0x21, 0 + .dw 0xadc0, 0xc82e, 0xadff, 0xc82e, 0x21, 0 + .dw 0xae40, 0xc82e, 0xae7f, 0xc82e, 0x21, 0 + .dw 0xaec0, 0xc82e, 0xaeff, 0xc82e, 0x21, 0 + .dw 0xaf40, 0xc82e, 0xaf7f, 0xc82e, 0x21, 0 + .dw 0xafc0, 0xc82e, 0xafff, 0xc82e, 0x21, 0 + .dw 0xb040, 0xc82e, 0xb07f, 0xc82e, 0x21, 0 + .dw 0xb0c0, 0xc82e, 0xb0ff, 0xc82e, 0x21, 0 + .dw 0xb140, 0xc82e, 0xb17f, 0xc82e, 0x21, 0 + .dw 0xb1c0, 0xc82e, 0xb1ff, 0xc82e, 0x21, 0 + .dw 0xb240, 0xc82e, 0xb27f, 0xc82e, 0x21, 0 + .dw 0xb2c0, 0xc82e, 0xb2ff, 0xc82e, 0x21, 0 + .dw 0xb340, 0xc82e, 0xb37f, 0xc82e, 0x21, 0 + .dw 0xb3c0, 0xc82e, 0xb3ff, 0xc82e, 0x21, 0 + .dw 0xb440, 0xc82e, 0xb47f, 0xc82e, 0x21, 0 + .dw 0xb4c0, 0xc82e, 0xb4ff, 0xc82e, 0x21, 0 + .dw 0xb540, 0xc82e, 0xb57f, 0xc82e, 0x21, 0 + .dw 0xb5c0, 0xc82e, 0xb5ff, 0xc82e, 0x21, 0 + .dw 0xb640, 0xc82e, 0xb67f, 0xc82e, 0x21, 0 + .dw 0xb6c0, 0xc82e, 0xb6ff, 0xc82e, 0x21, 0 + .dw 0xb740, 0xc82e, 0xb77f, 0xc82e, 0x21, 0 + .dw 0xb7c0, 0xc82e, 0xb7ff, 0xc82e, 0x21, 0 + .dw 0xb840, 0xc82e, 0xb87f, 0xc82e, 0x21, 0 + .dw 0xb8c0, 0xc82e, 0xb8ff, 0xc82e, 0x21, 0 + .dw 0xb940, 0xc82e, 0xb97f, 0xc82e, 0x21, 0 + .dw 0xb9c0, 0xc82e, 0xbfff, 0xc82e, 0x21, 0 + .dw 0xc040, 0xc82e, 0xc07f, 0xc82e, 0x21, 0 + .dw 0xc0c0, 0xc82e, 0xc0ff, 0xc82e, 0x21, 0 + .dw 0xc140, 0xc82e, 0xc17f, 0xc82e, 0x21, 0 + .dw 0xc1c0, 0xc82e, 0xc1ff, 0xc82e, 0x21, 0 + .dw 0xc240, 0xc82e, 0xc27f, 0xc82e, 0x21, 0 + .dw 0xc2c0, 0xc82e, 0xc2ff, 0xc82e, 0x21, 0 + .dw 0xc340, 0xc82e, 0xc37f, 0xc82e, 0x21, 0 + .dw 0xc3c0, 0xc82e, 0xc3ff, 0xc82e, 0x21, 0 + .dw 0xc440, 0xc82e, 0xc47f, 0xc82e, 0x21, 0 + .dw 0xc4c0, 0xc82e, 0xc4ff, 0xc82e, 0x21, 0 + .dw 0xc540, 0xc82e, 0xc57f, 0xc82e, 0x21, 0 + .dw 0xc5c0, 0xc82e, 0xc5ff, 0xc82e, 0x21, 0 + .dw 0xc640, 0xc82e, 0xc67f, 0xc82e, 0x21, 0 + .dw 0xc6c0, 0xc82e, 0xc6ff, 0xc82e, 0x21, 0 + .dw 0xc740, 0xc82e, 0xc77f, 0xc82e, 0x21, 0 + .dw 0xc7c0, 0xc82e, 0xc7ff, 0xc82e, 0x21, 0 + .dw 0xc840, 0xc82e, 0xc87f, 0xc82e, 0x21, 0 + .dw 0xc8c0, 0xc82e, 0xc8ff, 0xc82e, 0x21, 0 + .dw 0xc940, 0xc82e, 0xc97f, 0xc82e, 0x21, 0 + .dw 0xc9c0, 0xc82e, 0xc9ff, 0xc82e, 0x21, 0 + .dw 0xca40, 0xc82e, 0xca7f, 0xc82e, 0x21, 0 + .dw 0xcac0, 0xc82e, 0xcaff, 0xc82e, 0x21, 0 + .dw 0xcb40, 0xc82e, 0xcb7f, 0xc82e, 0x21, 0 + .dw 0xcbc0, 0xc82e, 0xcbff, 0xc82e, 0x21, 0 + .dw 0xcc40, 0xc82e, 0xcc7f, 0xc82e, 0x21, 0 + .dw 0xccc0, 0xc82e, 0xccff, 0xc82e, 0x21, 0 + .dw 0xcd40, 0xc82e, 0xcd7f, 0xc82e, 0x21, 0 + .dw 0xcdc0, 0xc82e, 0xcdff, 0xc82e, 0x21, 0 + .dw 0xce40, 0xc82e, 0xce7f, 0xc82e, 0x21, 0 + .dw 0xcec0, 0xc82e, 0xceff, 0xc82e, 0x21, 0 + .dw 0xcf40, 0xc82e, 0xcf7f, 0xc82e, 0x21, 0 + .dw 0xcfc0, 0xc82e, 0xcfff, 0xc82e, 0x21, 0 + .dw 0xd040, 0xc82e, 0xd07f, 0xc82e, 0x21, 0 + .dw 0xd0c0, 0xc82e, 0xd0ff, 0xc82e, 0x21, 0 + .dw 0xd140, 0xc82e, 0xd17f, 0xc82e, 0x21, 0 + .dw 0xd1c0, 0xc82e, 0xd1ff, 0xc82e, 0x21, 0 + .dw 0xd240, 0xc82e, 0xd27f, 0xc82e, 0x21, 0 + .dw 0xd2c0, 0xc82e, 0xd2ff, 0xc82e, 0x21, 0 + .dw 0xd340, 0xc82e, 0xd37f, 0xc82e, 0x21, 0 + .dw 0xd3c0, 0xc82e, 0xd3ff, 0xc82e, 0x21, 0 + .dw 0xd440, 0xc82e, 0xd47f, 0xc82e, 0x21, 0 + .dw 0xd4c0, 0xc82e, 0xd4ff, 0xc82e, 0x21, 0 + .dw 0xd540, 0xc82e, 0xd57f, 0xc82e, 0x21, 0 + .dw 0xd5c0, 0xc82e, 0xd5ff, 0xc82e, 0x21, 0 + .dw 0xd640, 0xc82e, 0xd67f, 0xc82e, 0x21, 0 + .dw 0xd6c0, 0xc82e, 0xd6ff, 0xc82e, 0x21, 0 + .dw 0xd740, 0xc82e, 0xd77f, 0xc82e, 0x21, 0 + .dw 0xd7c0, 0xc82e, 0xd7ff, 0xc82e, 0x21, 0 + .dw 0xd840, 0xc82e, 0xd87f, 0xc82e, 0x21, 0 + .dw 0xd8c0, 0xc82e, 0xd8ff, 0xc82e, 0x21, 0 + .dw 0xd940, 0xc82e, 0xd97f, 0xc82e, 0x21, 0 + .dw 0xd9c0, 0xc82e, 0xdfff, 0xc82e, 0x21, 0 + .dw 0xe040, 0xc82e, 0xe07f, 0xc82e, 0x21, 0 + .dw 0xe0c0, 0xc82e, 0xe0ff, 0xc82e, 0x21, 0 + .dw 0xe140, 0xc82e, 0xe17f, 0xc82e, 0x21, 0 + .dw 0xe1c0, 0xc82e, 0xe1ff, 0xc82e, 0x21, 0 + .dw 0xe240, 0xc82e, 0xe27f, 0xc82e, 0x21, 0 + .dw 0xe2c0, 0xc82e, 0xe2ff, 0xc82e, 0x21, 0 + .dw 0xe340, 0xc82e, 0xe37f, 0xc82e, 0x21, 0 + .dw 0xe3c0, 0xc82e, 0xe3ff, 0xc82e, 0x21, 0 + .dw 0xe440, 0xc82e, 0xe47f, 0xc82e, 0x21, 0 + .dw 0xe4c0, 0xc82e, 0xe4ff, 0xc82e, 0x21, 0 + .dw 0xe540, 0xc82e, 0xe57f, 0xc82e, 0x21, 0 + .dw 0xe5c0, 0xc82e, 0xe5ff, 0xc82e, 0x21, 0 + .dw 0xe640, 0xc82e, 0xe67f, 0xc82e, 0x21, 0 + .dw 0xe6c0, 0xc82e, 0xe6ff, 0xc82e, 0x21, 0 + .dw 0xe740, 0xc82e, 0xe77f, 0xc82e, 0x21, 0 + .dw 0xe7c0, 0xc82e, 0xe7ff, 0xc82e, 0x21, 0 + .dw 0xe840, 0xc82e, 0xe87f, 0xc82e, 0x21, 0 + .dw 0xe8c0, 0xc82e, 0xe8ff, 0xc82e, 0x21, 0 + .dw 0xe940, 0xc82e, 0xe97f, 0xc82e, 0x21, 0 + .dw 0xe9c0, 0xc82e, 0xe9ff, 0xc82e, 0x21, 0 + .dw 0xea40, 0xc82e, 0xea7f, 0xc82e, 0x21, 0 + .dw 0xeac0, 0xc82e, 0xeaff, 0xc82e, 0x21, 0 + .dw 0xeb40, 0xc82e, 0xeb7f, 0xc82e, 0x21, 0 + .dw 0xebc0, 0xc82e, 0xebff, 0xc82e, 0x21, 0 + .dw 0xec40, 0xc82e, 0xec7f, 0xc82e, 0x21, 0 + .dw 0xecc0, 0xc82e, 0xecff, 0xc82e, 0x21, 0 + .dw 0xed40, 0xc82e, 0xed7f, 0xc82e, 0x21, 0 + .dw 0xedc0, 0xc82e, 0xedff, 0xc82e, 0x21, 0 + .dw 0xee40, 0xc82e, 0xee7f, 0xc82e, 0x21, 0 + .dw 0xeec0, 0xc82e, 0xeeff, 0xc82e, 0x21, 0 + .dw 0xef40, 0xc82e, 0xef7f, 0xc82e, 0x21, 0 + .dw 0xefc0, 0xc82e, 0xefff, 0xc82e, 0x21, 0 + .dw 0xf040, 0xc82e, 0xf07f, 0xc82e, 0x21, 0 + .dw 0xf0c0, 0xc82e, 0xf0ff, 0xc82e, 0x21, 0 + .dw 0xf140, 0xc82e, 0xf17f, 0xc82e, 0x21, 0 + .dw 0xf1c0, 0xc82e, 0xf1ff, 0xc82e, 0x21, 0 + .dw 0xf240, 0xc82e, 0xf27f, 0xc82e, 0x21, 0 + .dw 0xf2c0, 0xc82e, 0xf2ff, 0xc82e, 0x21, 0 + .dw 0xf340, 0xc82e, 0xf37f, 0xc82e, 0x21, 0 + .dw 0xf3c0, 0xc82e, 0xf3ff, 0xc82e, 0x21, 0 + .dw 0xf440, 0xc82e, 0xf47f, 0xc82e, 0x21, 0 + .dw 0xf4c0, 0xc82e, 0xf4ff, 0xc82e, 0x21, 0 + .dw 0xf540, 0xc82e, 0xf57f, 0xc82e, 0x21, 0 + .dw 0xf5c0, 0xc82e, 0xf5ff, 0xc82e, 0x21, 0 + .dw 0xf640, 0xc82e, 0xf67f, 0xc82e, 0x21, 0 + .dw 0xf6c0, 0xc82e, 0xf6ff, 0xc82e, 0x21, 0 + .dw 0xf740, 0xc82e, 0xf77f, 0xc82e, 0x21, 0 + .dw 0xf7c0, 0xc82e, 0xf7ff, 0xc82e, 0x21, 0 + .dw 0xf840, 0xc82e, 0xf87f, 0xc82e, 0x21, 0 + .dw 0xf8c0, 0xc82e, 0xf8ff, 0xc82e, 0x21, 0 + .dw 0xf940, 0xc82e, 0xf97f, 0xc82e, 0x21, 0 + .dw 0xf9c0, 0xc82e, 0xffff, 0xc82e, 0x21, 0 + .dw 0x0040, 0xc82f, 0x007f, 0xc82f, 0x21, 0 + .dw 0x00c0, 0xc82f, 0x00ff, 0xc82f, 0x21, 0 + .dw 0x0140, 0xc82f, 0x017f, 0xc82f, 0x21, 0 + .dw 0x01c0, 0xc82f, 0x01ff, 0xc82f, 0x21, 0 + .dw 0x0240, 0xc82f, 0x027f, 0xc82f, 0x21, 0 + .dw 0x02c0, 0xc82f, 0x02ff, 0xc82f, 0x21, 0 + .dw 0x0340, 0xc82f, 0x037f, 0xc82f, 0x21, 0 + .dw 0x03c0, 0xc82f, 0x03ff, 0xc82f, 0x21, 0 + .dw 0x0440, 0xc82f, 0x047f, 0xc82f, 0x21, 0 + .dw 0x04c0, 0xc82f, 0x04ff, 0xc82f, 0x21, 0 + .dw 0x0540, 0xc82f, 0x057f, 0xc82f, 0x21, 0 + .dw 0x05c0, 0xc82f, 0x05ff, 0xc82f, 0x21, 0 + .dw 0x0640, 0xc82f, 0x067f, 0xc82f, 0x21, 0 + .dw 0x06c0, 0xc82f, 0x06ff, 0xc82f, 0x21, 0 + .dw 0x0740, 0xc82f, 0x077f, 0xc82f, 0x21, 0 + .dw 0x07c0, 0xc82f, 0x07ff, 0xc82f, 0x21, 0 + .dw 0x0840, 0xc82f, 0x087f, 0xc82f, 0x21, 0 + .dw 0x08c0, 0xc82f, 0x08ff, 0xc82f, 0x21, 0 + .dw 0x0940, 0xc82f, 0x097f, 0xc82f, 0x21, 0 + .dw 0x09c0, 0xc82f, 0x09ff, 0xc82f, 0x21, 0 + .dw 0x0a40, 0xc82f, 0x0a7f, 0xc82f, 0x21, 0 + .dw 0x0ac0, 0xc82f, 0x0aff, 0xc82f, 0x21, 0 + .dw 0x0b40, 0xc82f, 0x0b7f, 0xc82f, 0x21, 0 + .dw 0x0bc0, 0xc82f, 0x0bff, 0xc82f, 0x21, 0 + .dw 0x0c40, 0xc82f, 0x0c7f, 0xc82f, 0x21, 0 + .dw 0x0cc0, 0xc82f, 0x0cff, 0xc82f, 0x21, 0 + .dw 0x0d40, 0xc82f, 0x0d7f, 0xc82f, 0x21, 0 + .dw 0x0dc0, 0xc82f, 0x0dff, 0xc82f, 0x21, 0 + .dw 0x0e40, 0xc82f, 0x0e7f, 0xc82f, 0x21, 0 + .dw 0x0ec0, 0xc82f, 0x0eff, 0xc82f, 0x21, 0 + .dw 0x0f40, 0xc82f, 0x0f7f, 0xc82f, 0x21, 0 + .dw 0x0fc0, 0xc82f, 0x0fff, 0xc82f, 0x21, 0 + .dw 0x1040, 0xc82f, 0x107f, 0xc82f, 0x21, 0 + .dw 0x10c0, 0xc82f, 0x10ff, 0xc82f, 0x21, 0 + .dw 0x1140, 0xc82f, 0x117f, 0xc82f, 0x21, 0 + .dw 0x11c0, 0xc82f, 0x11ff, 0xc82f, 0x21, 0 + .dw 0x1240, 0xc82f, 0x127f, 0xc82f, 0x21, 0 + .dw 0x12c0, 0xc82f, 0x12ff, 0xc82f, 0x21, 0 + .dw 0x1340, 0xc82f, 0x137f, 0xc82f, 0x21, 0 + .dw 0x13c0, 0xc82f, 0x13ff, 0xc82f, 0x21, 0 + .dw 0x1440, 0xc82f, 0x147f, 0xc82f, 0x21, 0 + .dw 0x14c0, 0xc82f, 0x14ff, 0xc82f, 0x21, 0 + .dw 0x1540, 0xc82f, 0x157f, 0xc82f, 0x21, 0 + .dw 0x15c0, 0xc82f, 0x15ff, 0xc82f, 0x21, 0 + .dw 0x1640, 0xc82f, 0x167f, 0xc82f, 0x21, 0 + .dw 0x16c0, 0xc82f, 0x16ff, 0xc82f, 0x21, 0 + .dw 0x1740, 0xc82f, 0x177f, 0xc82f, 0x21, 0 + .dw 0x17c0, 0xc82f, 0x17ff, 0xc82f, 0x21, 0 + .dw 0x1840, 0xc82f, 0x187f, 0xc82f, 0x21, 0 + .dw 0x18c0, 0xc82f, 0x18ff, 0xc82f, 0x21, 0 + .dw 0x1940, 0xc82f, 0x197f, 0xc82f, 0x21, 0 + .dw 0x19c0, 0xc82f, 0x1fff, 0xc82f, 0x21, 0 + .dw 0x2040, 0xc82f, 0x207f, 0xc82f, 0x21, 0 + .dw 0x20c0, 0xc82f, 0x20ff, 0xc82f, 0x21, 0 + .dw 0x2140, 0xc82f, 0x217f, 0xc82f, 0x21, 0 + .dw 0x21c0, 0xc82f, 0x21ff, 0xc82f, 0x21, 0 + .dw 0x2240, 0xc82f, 0x227f, 0xc82f, 0x21, 0 + .dw 0x22c0, 0xc82f, 0x22ff, 0xc82f, 0x21, 0 + .dw 0x2340, 0xc82f, 0x237f, 0xc82f, 0x21, 0 + .dw 0x23c0, 0xc82f, 0x23ff, 0xc82f, 0x21, 0 + .dw 0x2440, 0xc82f, 0x247f, 0xc82f, 0x21, 0 + .dw 0x24c0, 0xc82f, 0x24ff, 0xc82f, 0x21, 0 + .dw 0x2540, 0xc82f, 0x257f, 0xc82f, 0x21, 0 + .dw 0x25c0, 0xc82f, 0x25ff, 0xc82f, 0x21, 0 + .dw 0x2640, 0xc82f, 0x267f, 0xc82f, 0x21, 0 + .dw 0x26c0, 0xc82f, 0x26ff, 0xc82f, 0x21, 0 + .dw 0x2740, 0xc82f, 0x277f, 0xc82f, 0x21, 0 + .dw 0x27c0, 0xc82f, 0x27ff, 0xc82f, 0x21, 0 + .dw 0x2840, 0xc82f, 0x287f, 0xc82f, 0x21, 0 + .dw 0x28c0, 0xc82f, 0x28ff, 0xc82f, 0x21, 0 + .dw 0x2940, 0xc82f, 0x297f, 0xc82f, 0x21, 0 + .dw 0x29c0, 0xc82f, 0x29ff, 0xc82f, 0x21, 0 + .dw 0x2a40, 0xc82f, 0x2a7f, 0xc82f, 0x21, 0 + .dw 0x2ac0, 0xc82f, 0x2aff, 0xc82f, 0x21, 0 + .dw 0x2b40, 0xc82f, 0x2b7f, 0xc82f, 0x21, 0 + .dw 0x2bc0, 0xc82f, 0x2bff, 0xc82f, 0x21, 0 + .dw 0x2c40, 0xc82f, 0x2c7f, 0xc82f, 0x21, 0 + .dw 0x2cc0, 0xc82f, 0x2cff, 0xc82f, 0x21, 0 + .dw 0x2d40, 0xc82f, 0x2d7f, 0xc82f, 0x21, 0 + .dw 0x2dc0, 0xc82f, 0x2dff, 0xc82f, 0x21, 0 + .dw 0x2e40, 0xc82f, 0x2e7f, 0xc82f, 0x21, 0 + .dw 0x2ec0, 0xc82f, 0x2eff, 0xc82f, 0x21, 0 + .dw 0x2f40, 0xc82f, 0x2f7f, 0xc82f, 0x21, 0 + .dw 0x2fc0, 0xc82f, 0x2fff, 0xc82f, 0x21, 0 + .dw 0x3040, 0xc82f, 0x307f, 0xc82f, 0x21, 0 + .dw 0x30c0, 0xc82f, 0x30ff, 0xc82f, 0x21, 0 + .dw 0x3140, 0xc82f, 0x317f, 0xc82f, 0x21, 0 + .dw 0x31c0, 0xc82f, 0x31ff, 0xc82f, 0x21, 0 + .dw 0x3240, 0xc82f, 0x327f, 0xc82f, 0x21, 0 + .dw 0x32c0, 0xc82f, 0x32ff, 0xc82f, 0x21, 0 + .dw 0x3340, 0xc82f, 0x337f, 0xc82f, 0x21, 0 + .dw 0x33c0, 0xc82f, 0x33ff, 0xc82f, 0x21, 0 + .dw 0x3440, 0xc82f, 0x347f, 0xc82f, 0x21, 0 + .dw 0x34c0, 0xc82f, 0x34ff, 0xc82f, 0x21, 0 + .dw 0x3540, 0xc82f, 0x357f, 0xc82f, 0x21, 0 + .dw 0x35c0, 0xc82f, 0x35ff, 0xc82f, 0x21, 0 + .dw 0x3640, 0xc82f, 0x367f, 0xc82f, 0x21, 0 + .dw 0x36c0, 0xc82f, 0x36ff, 0xc82f, 0x21, 0 + .dw 0x3740, 0xc82f, 0x377f, 0xc82f, 0x21, 0 + .dw 0x37c0, 0xc82f, 0x37ff, 0xc82f, 0x21, 0 + .dw 0x3840, 0xc82f, 0x387f, 0xc82f, 0x21, 0 + .dw 0x38c0, 0xc82f, 0x38ff, 0xc82f, 0x21, 0 + .dw 0x3940, 0xc82f, 0x397f, 0xc82f, 0x21, 0 + .dw 0x39c0, 0xc82f, 0x1fff, 0xc830, 0x21, 0 + .dw 0x3a00, 0xc830, 0x5fff, 0xc830, 0x21, 0 + .dw 0x7a00, 0xc830, 0x9fff, 0xc830, 0x21, 0 + .dw 0xba00, 0xc830, 0xdfff, 0xc830, 0x21, 0 + .dw 0xfa00, 0xc830, 0x1fff, 0xc831, 0x21, 0 + .dw 0x3a00, 0xc831, 0x5fff, 0xc831, 0x21, 0 + .dw 0x7a00, 0xc831, 0x9fff, 0xc831, 0x21, 0 + .dw 0xba00, 0xc831, 0xdfff, 0xc831, 0x21, 0 + .dw 0xfa00, 0xc831, 0x1fff, 0xc832, 0x21, 0 + .dw 0x3a00, 0xc832, 0x5fff, 0xc832, 0x21, 0 + .dw 0x7a00, 0xc832, 0x9fff, 0xc832, 0x21, 0 + .dw 0xba00, 0xc832, 0xdfff, 0xc832, 0x21, 0 + .dw 0xfa00, 0xc832, 0xffff, 0xc833, 0x21, 0 + .dw 0x1a00, 0xc834, 0x1fff, 0xc834, 0x21, 0 + .dw 0x3a00, 0xc834, 0x3fff, 0xc834, 0x21, 0 + .dw 0x5a00, 0xc834, 0x5fff, 0xc834, 0x21, 0 + .dw 0x7a00, 0xc834, 0x7fff, 0xc834, 0x21, 0 + .dw 0x9a00, 0xc834, 0x9fff, 0xc834, 0x21, 0 + .dw 0xba00, 0xc834, 0xbfff, 0xc834, 0x21, 0 + .dw 0xda00, 0xc834, 0xdfff, 0xc834, 0x21, 0 + .dw 0xfa00, 0xc834, 0xffff, 0xc834, 0x21, 0 + .dw 0x1a00, 0xc835, 0x1fff, 0xc835, 0x21, 0 + .dw 0x3a00, 0xc835, 0x3fff, 0xc835, 0x21, 0 + .dw 0x5a00, 0xc835, 0x5fff, 0xc835, 0x21, 0 + .dw 0x7a00, 0xc835, 0x7fff, 0xc835, 0x21, 0 + .dw 0x9a00, 0xc835, 0x9fff, 0xc835, 0x21, 0 + .dw 0xba00, 0xc835, 0xbfff, 0xc835, 0x21, 0 + .dw 0xda00, 0xc835, 0xdfff, 0xc835, 0x21, 0 + .dw 0xfa00, 0xc835, 0xffff, 0xc835, 0x21, 0 + .dw 0x1a00, 0xc836, 0x1fff, 0xc836, 0x21, 0 + .dw 0x3a00, 0xc836, 0x3fff, 0xc836, 0x21, 0 + .dw 0x5a00, 0xc836, 0x5fff, 0xc836, 0x21, 0 + .dw 0x7a00, 0xc836, 0x7fff, 0xc836, 0x21, 0 + .dw 0x9a00, 0xc836, 0x9fff, 0xc836, 0x21, 0 + .dw 0xba00, 0xc836, 0xbfff, 0xc836, 0x21, 0 + .dw 0xda00, 0xc836, 0xdfff, 0xc836, 0x21, 0 + .dw 0xfa00, 0xc836, 0xffff, 0xc836, 0x21, 0 + .dw 0x1a00, 0xc837, 0x1fff, 0xc837, 0x21, 0 + .dw 0x3a00, 0xc837, 0x1fff, 0xc838, 0x21, 0 + .dw 0x2040, 0xc838, 0x207f, 0xc838, 0x21, 0 + .dw 0x20c0, 0xc838, 0x20ff, 0xc838, 0x21, 0 + .dw 0x2140, 0xc838, 0x217f, 0xc838, 0x21, 0 + .dw 0x21c0, 0xc838, 0x21ff, 0xc838, 0x21, 0 + .dw 0x2240, 0xc838, 0x227f, 0xc838, 0x21, 0 + .dw 0x22c0, 0xc838, 0x22ff, 0xc838, 0x21, 0 + .dw 0x2340, 0xc838, 0x237f, 0xc838, 0x21, 0 + .dw 0x23c0, 0xc838, 0x23ff, 0xc838, 0x21, 0 + .dw 0x2440, 0xc838, 0x247f, 0xc838, 0x21, 0 + .dw 0x24c0, 0xc838, 0x24ff, 0xc838, 0x21, 0 + .dw 0x2540, 0xc838, 0x257f, 0xc838, 0x21, 0 + .dw 0x25c0, 0xc838, 0x25ff, 0xc838, 0x21, 0 + .dw 0x2640, 0xc838, 0x267f, 0xc838, 0x21, 0 + .dw 0x26c0, 0xc838, 0x26ff, 0xc838, 0x21, 0 + .dw 0x2740, 0xc838, 0x277f, 0xc838, 0x21, 0 + .dw 0x27c0, 0xc838, 0x27ff, 0xc838, 0x21, 0 + .dw 0x2840, 0xc838, 0x287f, 0xc838, 0x21, 0 + .dw 0x28c0, 0xc838, 0x28ff, 0xc838, 0x21, 0 + .dw 0x2940, 0xc838, 0x297f, 0xc838, 0x21, 0 + .dw 0x29c0, 0xc838, 0x29ff, 0xc838, 0x21, 0 + .dw 0x2a40, 0xc838, 0x2a7f, 0xc838, 0x21, 0 + .dw 0x2ac0, 0xc838, 0x2aff, 0xc838, 0x21, 0 + .dw 0x2b40, 0xc838, 0x2b7f, 0xc838, 0x21, 0 + .dw 0x2bc0, 0xc838, 0x2bff, 0xc838, 0x21, 0 + .dw 0x2c40, 0xc838, 0x2c7f, 0xc838, 0x21, 0 + .dw 0x2cc0, 0xc838, 0x2cff, 0xc838, 0x21, 0 + .dw 0x2d40, 0xc838, 0x2d7f, 0xc838, 0x21, 0 + .dw 0x2dc0, 0xc838, 0x2dff, 0xc838, 0x21, 0 + .dw 0x2e40, 0xc838, 0x2e7f, 0xc838, 0x21, 0 + .dw 0x2ec0, 0xc838, 0x2eff, 0xc838, 0x21, 0 + .dw 0x2f40, 0xc838, 0x2f7f, 0xc838, 0x21, 0 + .dw 0x2fc0, 0xc838, 0x2fff, 0xc838, 0x21, 0 + .dw 0x3040, 0xc838, 0x307f, 0xc838, 0x21, 0 + .dw 0x30c0, 0xc838, 0x30ff, 0xc838, 0x21, 0 + .dw 0x3140, 0xc838, 0x317f, 0xc838, 0x21, 0 + .dw 0x31c0, 0xc838, 0x31ff, 0xc838, 0x21, 0 + .dw 0x3240, 0xc838, 0x327f, 0xc838, 0x21, 0 + .dw 0x32c0, 0xc838, 0x32ff, 0xc838, 0x21, 0 + .dw 0x3340, 0xc838, 0x337f, 0xc838, 0x21, 0 + .dw 0x33c0, 0xc838, 0x33ff, 0xc838, 0x21, 0 + .dw 0x3440, 0xc838, 0x347f, 0xc838, 0x21, 0 + .dw 0x34c0, 0xc838, 0x34ff, 0xc838, 0x21, 0 + .dw 0x3540, 0xc838, 0x357f, 0xc838, 0x21, 0 + .dw 0x35c0, 0xc838, 0x35ff, 0xc838, 0x21, 0 + .dw 0x3640, 0xc838, 0x367f, 0xc838, 0x21, 0 + .dw 0x36c0, 0xc838, 0x36ff, 0xc838, 0x21, 0 + .dw 0x3740, 0xc838, 0x377f, 0xc838, 0x21, 0 + .dw 0x37c0, 0xc838, 0x37ff, 0xc838, 0x21, 0 + .dw 0x3840, 0xc838, 0x387f, 0xc838, 0x21, 0 + .dw 0x38c0, 0xc838, 0x38ff, 0xc838, 0x21, 0 + .dw 0x3940, 0xc838, 0x397f, 0xc838, 0x21, 0 + .dw 0x39c0, 0xc838, 0x5fff, 0xc838, 0x21, 0 + .dw 0x6040, 0xc838, 0x607f, 0xc838, 0x21, 0 + .dw 0x60c0, 0xc838, 0x60ff, 0xc838, 0x21, 0 + .dw 0x6140, 0xc838, 0x617f, 0xc838, 0x21, 0 + .dw 0x61c0, 0xc838, 0x61ff, 0xc838, 0x21, 0 + .dw 0x6240, 0xc838, 0x627f, 0xc838, 0x21, 0 + .dw 0x62c0, 0xc838, 0x62ff, 0xc838, 0x21, 0 + .dw 0x6340, 0xc838, 0x637f, 0xc838, 0x21, 0 + .dw 0x63c0, 0xc838, 0x63ff, 0xc838, 0x21, 0 + .dw 0x6440, 0xc838, 0x647f, 0xc838, 0x21, 0 + .dw 0x64c0, 0xc838, 0x64ff, 0xc838, 0x21, 0 + .dw 0x6540, 0xc838, 0x657f, 0xc838, 0x21, 0 + .dw 0x65c0, 0xc838, 0x65ff, 0xc838, 0x21, 0 + .dw 0x6640, 0xc838, 0x667f, 0xc838, 0x21, 0 + .dw 0x66c0, 0xc838, 0x66ff, 0xc838, 0x21, 0 + .dw 0x6740, 0xc838, 0x677f, 0xc838, 0x21, 0 + .dw 0x67c0, 0xc838, 0x67ff, 0xc838, 0x21, 0 + .dw 0x6840, 0xc838, 0x687f, 0xc838, 0x21, 0 + .dw 0x68c0, 0xc838, 0x68ff, 0xc838, 0x21, 0 + .dw 0x6940, 0xc838, 0x697f, 0xc838, 0x21, 0 + .dw 0x69c0, 0xc838, 0x69ff, 0xc838, 0x21, 0 + .dw 0x6a40, 0xc838, 0x6a7f, 0xc838, 0x21, 0 + .dw 0x6ac0, 0xc838, 0x6aff, 0xc838, 0x21, 0 + .dw 0x6b40, 0xc838, 0x6b7f, 0xc838, 0x21, 0 + .dw 0x6bc0, 0xc838, 0x6bff, 0xc838, 0x21, 0 + .dw 0x6c40, 0xc838, 0x6c7f, 0xc838, 0x21, 0 + .dw 0x6cc0, 0xc838, 0x6cff, 0xc838, 0x21, 0 + .dw 0x6d40, 0xc838, 0x6d7f, 0xc838, 0x21, 0 + .dw 0x6dc0, 0xc838, 0x6dff, 0xc838, 0x21, 0 + .dw 0x6e40, 0xc838, 0x6e7f, 0xc838, 0x21, 0 + .dw 0x6ec0, 0xc838, 0x6eff, 0xc838, 0x21, 0 + .dw 0x6f40, 0xc838, 0x6f7f, 0xc838, 0x21, 0 + .dw 0x6fc0, 0xc838, 0x6fff, 0xc838, 0x21, 0 + .dw 0x7040, 0xc838, 0x707f, 0xc838, 0x21, 0 + .dw 0x70c0, 0xc838, 0x70ff, 0xc838, 0x21, 0 + .dw 0x7140, 0xc838, 0x717f, 0xc838, 0x21, 0 + .dw 0x71c0, 0xc838, 0x71ff, 0xc838, 0x21, 0 + .dw 0x7240, 0xc838, 0x727f, 0xc838, 0x21, 0 + .dw 0x72c0, 0xc838, 0x72ff, 0xc838, 0x21, 0 + .dw 0x7340, 0xc838, 0x737f, 0xc838, 0x21, 0 + .dw 0x73c0, 0xc838, 0x73ff, 0xc838, 0x21, 0 + .dw 0x7440, 0xc838, 0x747f, 0xc838, 0x21, 0 + .dw 0x74c0, 0xc838, 0x74ff, 0xc838, 0x21, 0 + .dw 0x7540, 0xc838, 0x757f, 0xc838, 0x21, 0 + .dw 0x75c0, 0xc838, 0x75ff, 0xc838, 0x21, 0 + .dw 0x7640, 0xc838, 0x767f, 0xc838, 0x21, 0 + .dw 0x76c0, 0xc838, 0x76ff, 0xc838, 0x21, 0 + .dw 0x7740, 0xc838, 0x777f, 0xc838, 0x21, 0 + .dw 0x77c0, 0xc838, 0x77ff, 0xc838, 0x21, 0 + .dw 0x7840, 0xc838, 0x787f, 0xc838, 0x21, 0 + .dw 0x78c0, 0xc838, 0x78ff, 0xc838, 0x21, 0 + .dw 0x7940, 0xc838, 0x797f, 0xc838, 0x21, 0 + .dw 0x79c0, 0xc838, 0x9fff, 0xc838, 0x21, 0 + .dw 0xa040, 0xc838, 0xa07f, 0xc838, 0x21, 0 + .dw 0xa0c0, 0xc838, 0xa0ff, 0xc838, 0x21, 0 + .dw 0xa140, 0xc838, 0xa17f, 0xc838, 0x21, 0 + .dw 0xa1c0, 0xc838, 0xa1ff, 0xc838, 0x21, 0 + .dw 0xa240, 0xc838, 0xa27f, 0xc838, 0x21, 0 + .dw 0xa2c0, 0xc838, 0xa2ff, 0xc838, 0x21, 0 + .dw 0xa340, 0xc838, 0xa37f, 0xc838, 0x21, 0 + .dw 0xa3c0, 0xc838, 0xa3ff, 0xc838, 0x21, 0 + .dw 0xa440, 0xc838, 0xa47f, 0xc838, 0x21, 0 + .dw 0xa4c0, 0xc838, 0xa4ff, 0xc838, 0x21, 0 + .dw 0xa540, 0xc838, 0xa57f, 0xc838, 0x21, 0 + .dw 0xa5c0, 0xc838, 0xa5ff, 0xc838, 0x21, 0 + .dw 0xa640, 0xc838, 0xa67f, 0xc838, 0x21, 0 + .dw 0xa6c0, 0xc838, 0xa6ff, 0xc838, 0x21, 0 + .dw 0xa740, 0xc838, 0xa77f, 0xc838, 0x21, 0 + .dw 0xa7c0, 0xc838, 0xa7ff, 0xc838, 0x21, 0 + .dw 0xa840, 0xc838, 0xa87f, 0xc838, 0x21, 0 + .dw 0xa8c0, 0xc838, 0xa8ff, 0xc838, 0x21, 0 + .dw 0xa940, 0xc838, 0xa97f, 0xc838, 0x21, 0 + .dw 0xa9c0, 0xc838, 0xa9ff, 0xc838, 0x21, 0 + .dw 0xaa40, 0xc838, 0xaa7f, 0xc838, 0x21, 0 + .dw 0xaac0, 0xc838, 0xaaff, 0xc838, 0x21, 0 + .dw 0xab40, 0xc838, 0xab7f, 0xc838, 0x21, 0 + .dw 0xabc0, 0xc838, 0xabff, 0xc838, 0x21, 0 + .dw 0xac40, 0xc838, 0xac7f, 0xc838, 0x21, 0 + .dw 0xacc0, 0xc838, 0xacff, 0xc838, 0x21, 0 + .dw 0xad40, 0xc838, 0xad7f, 0xc838, 0x21, 0 + .dw 0xadc0, 0xc838, 0xadff, 0xc838, 0x21, 0 + .dw 0xae40, 0xc838, 0xae7f, 0xc838, 0x21, 0 + .dw 0xaec0, 0xc838, 0xaeff, 0xc838, 0x21, 0 + .dw 0xaf40, 0xc838, 0xaf7f, 0xc838, 0x21, 0 + .dw 0xafc0, 0xc838, 0xafff, 0xc838, 0x21, 0 + .dw 0xb040, 0xc838, 0xb07f, 0xc838, 0x21, 0 + .dw 0xb0c0, 0xc838, 0xb0ff, 0xc838, 0x21, 0 + .dw 0xb140, 0xc838, 0xb17f, 0xc838, 0x21, 0 + .dw 0xb1c0, 0xc838, 0xb1ff, 0xc838, 0x21, 0 + .dw 0xb240, 0xc838, 0xb27f, 0xc838, 0x21, 0 + .dw 0xb2c0, 0xc838, 0xb2ff, 0xc838, 0x21, 0 + .dw 0xb340, 0xc838, 0xb37f, 0xc838, 0x21, 0 + .dw 0xb3c0, 0xc838, 0xb3ff, 0xc838, 0x21, 0 + .dw 0xb440, 0xc838, 0xb47f, 0xc838, 0x21, 0 + .dw 0xb4c0, 0xc838, 0xb4ff, 0xc838, 0x21, 0 + .dw 0xb540, 0xc838, 0xb57f, 0xc838, 0x21, 0 + .dw 0xb5c0, 0xc838, 0xb5ff, 0xc838, 0x21, 0 + .dw 0xb640, 0xc838, 0xb67f, 0xc838, 0x21, 0 + .dw 0xb6c0, 0xc838, 0xb6ff, 0xc838, 0x21, 0 + .dw 0xb740, 0xc838, 0xb77f, 0xc838, 0x21, 0 + .dw 0xb7c0, 0xc838, 0xb7ff, 0xc838, 0x21, 0 + .dw 0xb840, 0xc838, 0xb87f, 0xc838, 0x21, 0 + .dw 0xb8c0, 0xc838, 0xb8ff, 0xc838, 0x21, 0 + .dw 0xb940, 0xc838, 0xb97f, 0xc838, 0x21, 0 + .dw 0xb9c0, 0xc838, 0xdfff, 0xc838, 0x21, 0 + .dw 0xe040, 0xc838, 0xe07f, 0xc838, 0x21, 0 + .dw 0xe0c0, 0xc838, 0xe0ff, 0xc838, 0x21, 0 + .dw 0xe140, 0xc838, 0xe17f, 0xc838, 0x21, 0 + .dw 0xe1c0, 0xc838, 0xe1ff, 0xc838, 0x21, 0 + .dw 0xe240, 0xc838, 0xe27f, 0xc838, 0x21, 0 + .dw 0xe2c0, 0xc838, 0xe2ff, 0xc838, 0x21, 0 + .dw 0xe340, 0xc838, 0xe37f, 0xc838, 0x21, 0 + .dw 0xe3c0, 0xc838, 0xe3ff, 0xc838, 0x21, 0 + .dw 0xe440, 0xc838, 0xe47f, 0xc838, 0x21, 0 + .dw 0xe4c0, 0xc838, 0xe4ff, 0xc838, 0x21, 0 + .dw 0xe540, 0xc838, 0xe57f, 0xc838, 0x21, 0 + .dw 0xe5c0, 0xc838, 0xe5ff, 0xc838, 0x21, 0 + .dw 0xe640, 0xc838, 0xe67f, 0xc838, 0x21, 0 + .dw 0xe6c0, 0xc838, 0xe6ff, 0xc838, 0x21, 0 + .dw 0xe740, 0xc838, 0xe77f, 0xc838, 0x21, 0 + .dw 0xe7c0, 0xc838, 0xe7ff, 0xc838, 0x21, 0 + .dw 0xe840, 0xc838, 0xe87f, 0xc838, 0x21, 0 + .dw 0xe8c0, 0xc838, 0xe8ff, 0xc838, 0x21, 0 + .dw 0xe940, 0xc838, 0xe97f, 0xc838, 0x21, 0 + .dw 0xe9c0, 0xc838, 0xe9ff, 0xc838, 0x21, 0 + .dw 0xea40, 0xc838, 0xea7f, 0xc838, 0x21, 0 + .dw 0xeac0, 0xc838, 0xeaff, 0xc838, 0x21, 0 + .dw 0xeb40, 0xc838, 0xeb7f, 0xc838, 0x21, 0 + .dw 0xebc0, 0xc838, 0xebff, 0xc838, 0x21, 0 + .dw 0xec40, 0xc838, 0xec7f, 0xc838, 0x21, 0 + .dw 0xecc0, 0xc838, 0xecff, 0xc838, 0x21, 0 + .dw 0xed40, 0xc838, 0xed7f, 0xc838, 0x21, 0 + .dw 0xedc0, 0xc838, 0xedff, 0xc838, 0x21, 0 + .dw 0xee40, 0xc838, 0xee7f, 0xc838, 0x21, 0 + .dw 0xeec0, 0xc838, 0xeeff, 0xc838, 0x21, 0 + .dw 0xef40, 0xc838, 0xef7f, 0xc838, 0x21, 0 + .dw 0xefc0, 0xc838, 0xefff, 0xc838, 0x21, 0 + .dw 0xf040, 0xc838, 0xf07f, 0xc838, 0x21, 0 + .dw 0xf0c0, 0xc838, 0xf0ff, 0xc838, 0x21, 0 + .dw 0xf140, 0xc838, 0xf17f, 0xc838, 0x21, 0 + .dw 0xf1c0, 0xc838, 0xf1ff, 0xc838, 0x21, 0 + .dw 0xf240, 0xc838, 0xf27f, 0xc838, 0x21, 0 + .dw 0xf2c0, 0xc838, 0xf2ff, 0xc838, 0x21, 0 + .dw 0xf340, 0xc838, 0xf37f, 0xc838, 0x21, 0 + .dw 0xf3c0, 0xc838, 0xf3ff, 0xc838, 0x21, 0 + .dw 0xf440, 0xc838, 0xf47f, 0xc838, 0x21, 0 + .dw 0xf4c0, 0xc838, 0xf4ff, 0xc838, 0x21, 0 + .dw 0xf540, 0xc838, 0xf57f, 0xc838, 0x21, 0 + .dw 0xf5c0, 0xc838, 0xf5ff, 0xc838, 0x21, 0 + .dw 0xf640, 0xc838, 0xf67f, 0xc838, 0x21, 0 + .dw 0xf6c0, 0xc838, 0xf6ff, 0xc838, 0x21, 0 + .dw 0xf740, 0xc838, 0xf77f, 0xc838, 0x21, 0 + .dw 0xf7c0, 0xc838, 0xf7ff, 0xc838, 0x21, 0 + .dw 0xf840, 0xc838, 0xf87f, 0xc838, 0x21, 0 + .dw 0xf8c0, 0xc838, 0xf8ff, 0xc838, 0x21, 0 + .dw 0xf940, 0xc838, 0xf97f, 0xc838, 0x21, 0 + .dw 0xf9c0, 0xc838, 0x1fff, 0xc839, 0x21, 0 + .dw 0x2040, 0xc839, 0x207f, 0xc839, 0x21, 0 + .dw 0x20c0, 0xc839, 0x20ff, 0xc839, 0x21, 0 + .dw 0x2140, 0xc839, 0x217f, 0xc839, 0x21, 0 + .dw 0x21c0, 0xc839, 0x21ff, 0xc839, 0x21, 0 + .dw 0x2240, 0xc839, 0x227f, 0xc839, 0x21, 0 + .dw 0x22c0, 0xc839, 0x22ff, 0xc839, 0x21, 0 + .dw 0x2340, 0xc839, 0x237f, 0xc839, 0x21, 0 + .dw 0x23c0, 0xc839, 0x23ff, 0xc839, 0x21, 0 + .dw 0x2440, 0xc839, 0x247f, 0xc839, 0x21, 0 + .dw 0x24c0, 0xc839, 0x24ff, 0xc839, 0x21, 0 + .dw 0x2540, 0xc839, 0x257f, 0xc839, 0x21, 0 + .dw 0x25c0, 0xc839, 0x25ff, 0xc839, 0x21, 0 + .dw 0x2640, 0xc839, 0x267f, 0xc839, 0x21, 0 + .dw 0x26c0, 0xc839, 0x26ff, 0xc839, 0x21, 0 + .dw 0x2740, 0xc839, 0x277f, 0xc839, 0x21, 0 + .dw 0x27c0, 0xc839, 0x27ff, 0xc839, 0x21, 0 + .dw 0x2840, 0xc839, 0x287f, 0xc839, 0x21, 0 + .dw 0x28c0, 0xc839, 0x28ff, 0xc839, 0x21, 0 + .dw 0x2940, 0xc839, 0x297f, 0xc839, 0x21, 0 + .dw 0x29c0, 0xc839, 0x29ff, 0xc839, 0x21, 0 + .dw 0x2a40, 0xc839, 0x2a7f, 0xc839, 0x21, 0 + .dw 0x2ac0, 0xc839, 0x2aff, 0xc839, 0x21, 0 + .dw 0x2b40, 0xc839, 0x2b7f, 0xc839, 0x21, 0 + .dw 0x2bc0, 0xc839, 0x2bff, 0xc839, 0x21, 0 + .dw 0x2c40, 0xc839, 0x2c7f, 0xc839, 0x21, 0 + .dw 0x2cc0, 0xc839, 0x2cff, 0xc839, 0x21, 0 + .dw 0x2d40, 0xc839, 0x2d7f, 0xc839, 0x21, 0 + .dw 0x2dc0, 0xc839, 0x2dff, 0xc839, 0x21, 0 + .dw 0x2e40, 0xc839, 0x2e7f, 0xc839, 0x21, 0 + .dw 0x2ec0, 0xc839, 0x2eff, 0xc839, 0x21, 0 + .dw 0x2f40, 0xc839, 0x2f7f, 0xc839, 0x21, 0 + .dw 0x2fc0, 0xc839, 0x2fff, 0xc839, 0x21, 0 + .dw 0x3040, 0xc839, 0x307f, 0xc839, 0x21, 0 + .dw 0x30c0, 0xc839, 0x30ff, 0xc839, 0x21, 0 + .dw 0x3140, 0xc839, 0x317f, 0xc839, 0x21, 0 + .dw 0x31c0, 0xc839, 0x31ff, 0xc839, 0x21, 0 + .dw 0x3240, 0xc839, 0x327f, 0xc839, 0x21, 0 + .dw 0x32c0, 0xc839, 0x32ff, 0xc839, 0x21, 0 + .dw 0x3340, 0xc839, 0x337f, 0xc839, 0x21, 0 + .dw 0x33c0, 0xc839, 0x33ff, 0xc839, 0x21, 0 + .dw 0x3440, 0xc839, 0x347f, 0xc839, 0x21, 0 + .dw 0x34c0, 0xc839, 0x34ff, 0xc839, 0x21, 0 + .dw 0x3540, 0xc839, 0x357f, 0xc839, 0x21, 0 + .dw 0x35c0, 0xc839, 0x35ff, 0xc839, 0x21, 0 + .dw 0x3640, 0xc839, 0x367f, 0xc839, 0x21, 0 + .dw 0x36c0, 0xc839, 0x36ff, 0xc839, 0x21, 0 + .dw 0x3740, 0xc839, 0x377f, 0xc839, 0x21, 0 + .dw 0x37c0, 0xc839, 0x37ff, 0xc839, 0x21, 0 + .dw 0x3840, 0xc839, 0x387f, 0xc839, 0x21, 0 + .dw 0x38c0, 0xc839, 0x38ff, 0xc839, 0x21, 0 + .dw 0x3940, 0xc839, 0x397f, 0xc839, 0x21, 0 + .dw 0x39c0, 0xc839, 0x5fff, 0xc839, 0x21, 0 + .dw 0x6040, 0xc839, 0x607f, 0xc839, 0x21, 0 + .dw 0x60c0, 0xc839, 0x60ff, 0xc839, 0x21, 0 + .dw 0x6140, 0xc839, 0x617f, 0xc839, 0x21, 0 + .dw 0x61c0, 0xc839, 0x61ff, 0xc839, 0x21, 0 + .dw 0x6240, 0xc839, 0x627f, 0xc839, 0x21, 0 + .dw 0x62c0, 0xc839, 0x62ff, 0xc839, 0x21, 0 + .dw 0x6340, 0xc839, 0x637f, 0xc839, 0x21, 0 + .dw 0x63c0, 0xc839, 0x63ff, 0xc839, 0x21, 0 + .dw 0x6440, 0xc839, 0x647f, 0xc839, 0x21, 0 + .dw 0x64c0, 0xc839, 0x64ff, 0xc839, 0x21, 0 + .dw 0x6540, 0xc839, 0x657f, 0xc839, 0x21, 0 + .dw 0x65c0, 0xc839, 0x65ff, 0xc839, 0x21, 0 + .dw 0x6640, 0xc839, 0x667f, 0xc839, 0x21, 0 + .dw 0x66c0, 0xc839, 0x66ff, 0xc839, 0x21, 0 + .dw 0x6740, 0xc839, 0x677f, 0xc839, 0x21, 0 + .dw 0x67c0, 0xc839, 0x67ff, 0xc839, 0x21, 0 + .dw 0x6840, 0xc839, 0x687f, 0xc839, 0x21, 0 + .dw 0x68c0, 0xc839, 0x68ff, 0xc839, 0x21, 0 + .dw 0x6940, 0xc839, 0x697f, 0xc839, 0x21, 0 + .dw 0x69c0, 0xc839, 0x69ff, 0xc839, 0x21, 0 + .dw 0x6a40, 0xc839, 0x6a7f, 0xc839, 0x21, 0 + .dw 0x6ac0, 0xc839, 0x6aff, 0xc839, 0x21, 0 + .dw 0x6b40, 0xc839, 0x6b7f, 0xc839, 0x21, 0 + .dw 0x6bc0, 0xc839, 0x6bff, 0xc839, 0x21, 0 + .dw 0x6c40, 0xc839, 0x6c7f, 0xc839, 0x21, 0 + .dw 0x6cc0, 0xc839, 0x6cff, 0xc839, 0x21, 0 + .dw 0x6d40, 0xc839, 0x6d7f, 0xc839, 0x21, 0 + .dw 0x6dc0, 0xc839, 0x6dff, 0xc839, 0x21, 0 + .dw 0x6e40, 0xc839, 0x6e7f, 0xc839, 0x21, 0 + .dw 0x6ec0, 0xc839, 0x6eff, 0xc839, 0x21, 0 + .dw 0x6f40, 0xc839, 0x6f7f, 0xc839, 0x21, 0 + .dw 0x6fc0, 0xc839, 0x6fff, 0xc839, 0x21, 0 + .dw 0x7040, 0xc839, 0x707f, 0xc839, 0x21, 0 + .dw 0x70c0, 0xc839, 0x70ff, 0xc839, 0x21, 0 + .dw 0x7140, 0xc839, 0x717f, 0xc839, 0x21, 0 + .dw 0x71c0, 0xc839, 0x71ff, 0xc839, 0x21, 0 + .dw 0x7240, 0xc839, 0x727f, 0xc839, 0x21, 0 + .dw 0x72c0, 0xc839, 0x72ff, 0xc839, 0x21, 0 + .dw 0x7340, 0xc839, 0x737f, 0xc839, 0x21, 0 + .dw 0x73c0, 0xc839, 0x73ff, 0xc839, 0x21, 0 + .dw 0x7440, 0xc839, 0x747f, 0xc839, 0x21, 0 + .dw 0x74c0, 0xc839, 0x74ff, 0xc839, 0x21, 0 + .dw 0x7540, 0xc839, 0x757f, 0xc839, 0x21, 0 + .dw 0x75c0, 0xc839, 0x75ff, 0xc839, 0x21, 0 + .dw 0x7640, 0xc839, 0x767f, 0xc839, 0x21, 0 + .dw 0x76c0, 0xc839, 0x76ff, 0xc839, 0x21, 0 + .dw 0x7740, 0xc839, 0x777f, 0xc839, 0x21, 0 + .dw 0x77c0, 0xc839, 0x77ff, 0xc839, 0x21, 0 + .dw 0x7840, 0xc839, 0x787f, 0xc839, 0x21, 0 + .dw 0x78c0, 0xc839, 0x78ff, 0xc839, 0x21, 0 + .dw 0x7940, 0xc839, 0x797f, 0xc839, 0x21, 0 + .dw 0x79c0, 0xc839, 0x9fff, 0xc839, 0x21, 0 + .dw 0xa040, 0xc839, 0xa07f, 0xc839, 0x21, 0 + .dw 0xa0c0, 0xc839, 0xa0ff, 0xc839, 0x21, 0 + .dw 0xa140, 0xc839, 0xa17f, 0xc839, 0x21, 0 + .dw 0xa1c0, 0xc839, 0xa1ff, 0xc839, 0x21, 0 + .dw 0xa240, 0xc839, 0xa27f, 0xc839, 0x21, 0 + .dw 0xa2c0, 0xc839, 0xa2ff, 0xc839, 0x21, 0 + .dw 0xa340, 0xc839, 0xa37f, 0xc839, 0x21, 0 + .dw 0xa3c0, 0xc839, 0xa3ff, 0xc839, 0x21, 0 + .dw 0xa440, 0xc839, 0xa47f, 0xc839, 0x21, 0 + .dw 0xa4c0, 0xc839, 0xa4ff, 0xc839, 0x21, 0 + .dw 0xa540, 0xc839, 0xa57f, 0xc839, 0x21, 0 + .dw 0xa5c0, 0xc839, 0xa5ff, 0xc839, 0x21, 0 + .dw 0xa640, 0xc839, 0xa67f, 0xc839, 0x21, 0 + .dw 0xa6c0, 0xc839, 0xa6ff, 0xc839, 0x21, 0 + .dw 0xa740, 0xc839, 0xa77f, 0xc839, 0x21, 0 + .dw 0xa7c0, 0xc839, 0xa7ff, 0xc839, 0x21, 0 + .dw 0xa840, 0xc839, 0xa87f, 0xc839, 0x21, 0 + .dw 0xa8c0, 0xc839, 0xa8ff, 0xc839, 0x21, 0 + .dw 0xa940, 0xc839, 0xa97f, 0xc839, 0x21, 0 + .dw 0xa9c0, 0xc839, 0xa9ff, 0xc839, 0x21, 0 + .dw 0xaa40, 0xc839, 0xaa7f, 0xc839, 0x21, 0 + .dw 0xaac0, 0xc839, 0xaaff, 0xc839, 0x21, 0 + .dw 0xab40, 0xc839, 0xab7f, 0xc839, 0x21, 0 + .dw 0xabc0, 0xc839, 0xabff, 0xc839, 0x21, 0 + .dw 0xac40, 0xc839, 0xac7f, 0xc839, 0x21, 0 + .dw 0xacc0, 0xc839, 0xacff, 0xc839, 0x21, 0 + .dw 0xad40, 0xc839, 0xad7f, 0xc839, 0x21, 0 + .dw 0xadc0, 0xc839, 0xadff, 0xc839, 0x21, 0 + .dw 0xae40, 0xc839, 0xae7f, 0xc839, 0x21, 0 + .dw 0xaec0, 0xc839, 0xaeff, 0xc839, 0x21, 0 + .dw 0xaf40, 0xc839, 0xaf7f, 0xc839, 0x21, 0 + .dw 0xafc0, 0xc839, 0xafff, 0xc839, 0x21, 0 + .dw 0xb040, 0xc839, 0xb07f, 0xc839, 0x21, 0 + .dw 0xb0c0, 0xc839, 0xb0ff, 0xc839, 0x21, 0 + .dw 0xb140, 0xc839, 0xb17f, 0xc839, 0x21, 0 + .dw 0xb1c0, 0xc839, 0xb1ff, 0xc839, 0x21, 0 + .dw 0xb240, 0xc839, 0xb27f, 0xc839, 0x21, 0 + .dw 0xb2c0, 0xc839, 0xb2ff, 0xc839, 0x21, 0 + .dw 0xb340, 0xc839, 0xb37f, 0xc839, 0x21, 0 + .dw 0xb3c0, 0xc839, 0xb3ff, 0xc839, 0x21, 0 + .dw 0xb440, 0xc839, 0xb47f, 0xc839, 0x21, 0 + .dw 0xb4c0, 0xc839, 0xb4ff, 0xc839, 0x21, 0 + .dw 0xb540, 0xc839, 0xb57f, 0xc839, 0x21, 0 + .dw 0xb5c0, 0xc839, 0xb5ff, 0xc839, 0x21, 0 + .dw 0xb640, 0xc839, 0xb67f, 0xc839, 0x21, 0 + .dw 0xb6c0, 0xc839, 0xb6ff, 0xc839, 0x21, 0 + .dw 0xb740, 0xc839, 0xb77f, 0xc839, 0x21, 0 + .dw 0xb7c0, 0xc839, 0xb7ff, 0xc839, 0x21, 0 + .dw 0xb840, 0xc839, 0xb87f, 0xc839, 0x21, 0 + .dw 0xb8c0, 0xc839, 0xb8ff, 0xc839, 0x21, 0 + .dw 0xb940, 0xc839, 0xb97f, 0xc839, 0x21, 0 + .dw 0xb9c0, 0xc839, 0xdfff, 0xc839, 0x21, 0 + .dw 0xe040, 0xc839, 0xe07f, 0xc839, 0x21, 0 + .dw 0xe0c0, 0xc839, 0xe0ff, 0xc839, 0x21, 0 + .dw 0xe140, 0xc839, 0xe17f, 0xc839, 0x21, 0 + .dw 0xe1c0, 0xc839, 0xe1ff, 0xc839, 0x21, 0 + .dw 0xe240, 0xc839, 0xe27f, 0xc839, 0x21, 0 + .dw 0xe2c0, 0xc839, 0xe2ff, 0xc839, 0x21, 0 + .dw 0xe340, 0xc839, 0xe37f, 0xc839, 0x21, 0 + .dw 0xe3c0, 0xc839, 0xe3ff, 0xc839, 0x21, 0 + .dw 0xe440, 0xc839, 0xe47f, 0xc839, 0x21, 0 + .dw 0xe4c0, 0xc839, 0xe4ff, 0xc839, 0x21, 0 + .dw 0xe540, 0xc839, 0xe57f, 0xc839, 0x21, 0 + .dw 0xe5c0, 0xc839, 0xe5ff, 0xc839, 0x21, 0 + .dw 0xe640, 0xc839, 0xe67f, 0xc839, 0x21, 0 + .dw 0xe6c0, 0xc839, 0xe6ff, 0xc839, 0x21, 0 + .dw 0xe740, 0xc839, 0xe77f, 0xc839, 0x21, 0 + .dw 0xe7c0, 0xc839, 0xe7ff, 0xc839, 0x21, 0 + .dw 0xe840, 0xc839, 0xe87f, 0xc839, 0x21, 0 + .dw 0xe8c0, 0xc839, 0xe8ff, 0xc839, 0x21, 0 + .dw 0xe940, 0xc839, 0xe97f, 0xc839, 0x21, 0 + .dw 0xe9c0, 0xc839, 0xe9ff, 0xc839, 0x21, 0 + .dw 0xea40, 0xc839, 0xea7f, 0xc839, 0x21, 0 + .dw 0xeac0, 0xc839, 0xeaff, 0xc839, 0x21, 0 + .dw 0xeb40, 0xc839, 0xeb7f, 0xc839, 0x21, 0 + .dw 0xebc0, 0xc839, 0xebff, 0xc839, 0x21, 0 + .dw 0xec40, 0xc839, 0xec7f, 0xc839, 0x21, 0 + .dw 0xecc0, 0xc839, 0xecff, 0xc839, 0x21, 0 + .dw 0xed40, 0xc839, 0xed7f, 0xc839, 0x21, 0 + .dw 0xedc0, 0xc839, 0xedff, 0xc839, 0x21, 0 + .dw 0xee40, 0xc839, 0xee7f, 0xc839, 0x21, 0 + .dw 0xeec0, 0xc839, 0xeeff, 0xc839, 0x21, 0 + .dw 0xef40, 0xc839, 0xef7f, 0xc839, 0x21, 0 + .dw 0xefc0, 0xc839, 0xefff, 0xc839, 0x21, 0 + .dw 0xf040, 0xc839, 0xf07f, 0xc839, 0x21, 0 + .dw 0xf0c0, 0xc839, 0xf0ff, 0xc839, 0x21, 0 + .dw 0xf140, 0xc839, 0xf17f, 0xc839, 0x21, 0 + .dw 0xf1c0, 0xc839, 0xf1ff, 0xc839, 0x21, 0 + .dw 0xf240, 0xc839, 0xf27f, 0xc839, 0x21, 0 + .dw 0xf2c0, 0xc839, 0xf2ff, 0xc839, 0x21, 0 + .dw 0xf340, 0xc839, 0xf37f, 0xc839, 0x21, 0 + .dw 0xf3c0, 0xc839, 0xf3ff, 0xc839, 0x21, 0 + .dw 0xf440, 0xc839, 0xf47f, 0xc839, 0x21, 0 + .dw 0xf4c0, 0xc839, 0xf4ff, 0xc839, 0x21, 0 + .dw 0xf540, 0xc839, 0xf57f, 0xc839, 0x21, 0 + .dw 0xf5c0, 0xc839, 0xf5ff, 0xc839, 0x21, 0 + .dw 0xf640, 0xc839, 0xf67f, 0xc839, 0x21, 0 + .dw 0xf6c0, 0xc839, 0xf6ff, 0xc839, 0x21, 0 + .dw 0xf740, 0xc839, 0xf77f, 0xc839, 0x21, 0 + .dw 0xf7c0, 0xc839, 0xf7ff, 0xc839, 0x21, 0 + .dw 0xf840, 0xc839, 0xf87f, 0xc839, 0x21, 0 + .dw 0xf8c0, 0xc839, 0xf8ff, 0xc839, 0x21, 0 + .dw 0xf940, 0xc839, 0xf97f, 0xc839, 0x21, 0 + .dw 0xf9c0, 0xc839, 0x1fff, 0xc83a, 0x21, 0 + .dw 0x2040, 0xc83a, 0x207f, 0xc83a, 0x21, 0 + .dw 0x20c0, 0xc83a, 0x20ff, 0xc83a, 0x21, 0 + .dw 0x2140, 0xc83a, 0x217f, 0xc83a, 0x21, 0 + .dw 0x21c0, 0xc83a, 0x21ff, 0xc83a, 0x21, 0 + .dw 0x2240, 0xc83a, 0x227f, 0xc83a, 0x21, 0 + .dw 0x22c0, 0xc83a, 0x22ff, 0xc83a, 0x21, 0 + .dw 0x2340, 0xc83a, 0x237f, 0xc83a, 0x21, 0 + .dw 0x23c0, 0xc83a, 0x23ff, 0xc83a, 0x21, 0 + .dw 0x2440, 0xc83a, 0x247f, 0xc83a, 0x21, 0 + .dw 0x24c0, 0xc83a, 0x24ff, 0xc83a, 0x21, 0 + .dw 0x2540, 0xc83a, 0x257f, 0xc83a, 0x21, 0 + .dw 0x25c0, 0xc83a, 0x25ff, 0xc83a, 0x21, 0 + .dw 0x2640, 0xc83a, 0x267f, 0xc83a, 0x21, 0 + .dw 0x26c0, 0xc83a, 0x26ff, 0xc83a, 0x21, 0 + .dw 0x2740, 0xc83a, 0x277f, 0xc83a, 0x21, 0 + .dw 0x27c0, 0xc83a, 0x27ff, 0xc83a, 0x21, 0 + .dw 0x2840, 0xc83a, 0x287f, 0xc83a, 0x21, 0 + .dw 0x28c0, 0xc83a, 0x28ff, 0xc83a, 0x21, 0 + .dw 0x2940, 0xc83a, 0x297f, 0xc83a, 0x21, 0 + .dw 0x29c0, 0xc83a, 0x29ff, 0xc83a, 0x21, 0 + .dw 0x2a40, 0xc83a, 0x2a7f, 0xc83a, 0x21, 0 + .dw 0x2ac0, 0xc83a, 0x2aff, 0xc83a, 0x21, 0 + .dw 0x2b40, 0xc83a, 0x2b7f, 0xc83a, 0x21, 0 + .dw 0x2bc0, 0xc83a, 0x2bff, 0xc83a, 0x21, 0 + .dw 0x2c40, 0xc83a, 0x2c7f, 0xc83a, 0x21, 0 + .dw 0x2cc0, 0xc83a, 0x2cff, 0xc83a, 0x21, 0 + .dw 0x2d40, 0xc83a, 0x2d7f, 0xc83a, 0x21, 0 + .dw 0x2dc0, 0xc83a, 0x2dff, 0xc83a, 0x21, 0 + .dw 0x2e40, 0xc83a, 0x2e7f, 0xc83a, 0x21, 0 + .dw 0x2ec0, 0xc83a, 0x2eff, 0xc83a, 0x21, 0 + .dw 0x2f40, 0xc83a, 0x2f7f, 0xc83a, 0x21, 0 + .dw 0x2fc0, 0xc83a, 0x2fff, 0xc83a, 0x21, 0 + .dw 0x3040, 0xc83a, 0x307f, 0xc83a, 0x21, 0 + .dw 0x30c0, 0xc83a, 0x30ff, 0xc83a, 0x21, 0 + .dw 0x3140, 0xc83a, 0x317f, 0xc83a, 0x21, 0 + .dw 0x31c0, 0xc83a, 0x31ff, 0xc83a, 0x21, 0 + .dw 0x3240, 0xc83a, 0x327f, 0xc83a, 0x21, 0 + .dw 0x32c0, 0xc83a, 0x32ff, 0xc83a, 0x21, 0 + .dw 0x3340, 0xc83a, 0x337f, 0xc83a, 0x21, 0 + .dw 0x33c0, 0xc83a, 0x33ff, 0xc83a, 0x21, 0 + .dw 0x3440, 0xc83a, 0x347f, 0xc83a, 0x21, 0 + .dw 0x34c0, 0xc83a, 0x34ff, 0xc83a, 0x21, 0 + .dw 0x3540, 0xc83a, 0x357f, 0xc83a, 0x21, 0 + .dw 0x35c0, 0xc83a, 0x35ff, 0xc83a, 0x21, 0 + .dw 0x3640, 0xc83a, 0x367f, 0xc83a, 0x21, 0 + .dw 0x36c0, 0xc83a, 0x36ff, 0xc83a, 0x21, 0 + .dw 0x3740, 0xc83a, 0x377f, 0xc83a, 0x21, 0 + .dw 0x37c0, 0xc83a, 0x37ff, 0xc83a, 0x21, 0 + .dw 0x3840, 0xc83a, 0x387f, 0xc83a, 0x21, 0 + .dw 0x38c0, 0xc83a, 0x38ff, 0xc83a, 0x21, 0 + .dw 0x3940, 0xc83a, 0x397f, 0xc83a, 0x21, 0 + .dw 0x39c0, 0xc83a, 0x5fff, 0xc83a, 0x21, 0 + .dw 0x6040, 0xc83a, 0x607f, 0xc83a, 0x21, 0 + .dw 0x60c0, 0xc83a, 0x60ff, 0xc83a, 0x21, 0 + .dw 0x6140, 0xc83a, 0x617f, 0xc83a, 0x21, 0 + .dw 0x61c0, 0xc83a, 0x61ff, 0xc83a, 0x21, 0 + .dw 0x6240, 0xc83a, 0x627f, 0xc83a, 0x21, 0 + .dw 0x62c0, 0xc83a, 0x62ff, 0xc83a, 0x21, 0 + .dw 0x6340, 0xc83a, 0x637f, 0xc83a, 0x21, 0 + .dw 0x63c0, 0xc83a, 0x63ff, 0xc83a, 0x21, 0 + .dw 0x6440, 0xc83a, 0x647f, 0xc83a, 0x21, 0 + .dw 0x64c0, 0xc83a, 0x64ff, 0xc83a, 0x21, 0 + .dw 0x6540, 0xc83a, 0x657f, 0xc83a, 0x21, 0 + .dw 0x65c0, 0xc83a, 0x65ff, 0xc83a, 0x21, 0 + .dw 0x6640, 0xc83a, 0x667f, 0xc83a, 0x21, 0 + .dw 0x66c0, 0xc83a, 0x66ff, 0xc83a, 0x21, 0 + .dw 0x6740, 0xc83a, 0x677f, 0xc83a, 0x21, 0 + .dw 0x67c0, 0xc83a, 0x67ff, 0xc83a, 0x21, 0 + .dw 0x6840, 0xc83a, 0x687f, 0xc83a, 0x21, 0 + .dw 0x68c0, 0xc83a, 0x68ff, 0xc83a, 0x21, 0 + .dw 0x6940, 0xc83a, 0x697f, 0xc83a, 0x21, 0 + .dw 0x69c0, 0xc83a, 0x69ff, 0xc83a, 0x21, 0 + .dw 0x6a40, 0xc83a, 0x6a7f, 0xc83a, 0x21, 0 + .dw 0x6ac0, 0xc83a, 0x6aff, 0xc83a, 0x21, 0 + .dw 0x6b40, 0xc83a, 0x6b7f, 0xc83a, 0x21, 0 + .dw 0x6bc0, 0xc83a, 0x6bff, 0xc83a, 0x21, 0 + .dw 0x6c40, 0xc83a, 0x6c7f, 0xc83a, 0x21, 0 + .dw 0x6cc0, 0xc83a, 0x6cff, 0xc83a, 0x21, 0 + .dw 0x6d40, 0xc83a, 0x6d7f, 0xc83a, 0x21, 0 + .dw 0x6dc0, 0xc83a, 0x6dff, 0xc83a, 0x21, 0 + .dw 0x6e40, 0xc83a, 0x6e7f, 0xc83a, 0x21, 0 + .dw 0x6ec0, 0xc83a, 0x6eff, 0xc83a, 0x21, 0 + .dw 0x6f40, 0xc83a, 0x6f7f, 0xc83a, 0x21, 0 + .dw 0x6fc0, 0xc83a, 0x6fff, 0xc83a, 0x21, 0 + .dw 0x7040, 0xc83a, 0x707f, 0xc83a, 0x21, 0 + .dw 0x70c0, 0xc83a, 0x70ff, 0xc83a, 0x21, 0 + .dw 0x7140, 0xc83a, 0x717f, 0xc83a, 0x21, 0 + .dw 0x71c0, 0xc83a, 0x71ff, 0xc83a, 0x21, 0 + .dw 0x7240, 0xc83a, 0x727f, 0xc83a, 0x21, 0 + .dw 0x72c0, 0xc83a, 0x72ff, 0xc83a, 0x21, 0 + .dw 0x7340, 0xc83a, 0x737f, 0xc83a, 0x21, 0 + .dw 0x73c0, 0xc83a, 0x73ff, 0xc83a, 0x21, 0 + .dw 0x7440, 0xc83a, 0x747f, 0xc83a, 0x21, 0 + .dw 0x74c0, 0xc83a, 0x74ff, 0xc83a, 0x21, 0 + .dw 0x7540, 0xc83a, 0x757f, 0xc83a, 0x21, 0 + .dw 0x75c0, 0xc83a, 0x75ff, 0xc83a, 0x21, 0 + .dw 0x7640, 0xc83a, 0x767f, 0xc83a, 0x21, 0 + .dw 0x76c0, 0xc83a, 0x76ff, 0xc83a, 0x21, 0 + .dw 0x7740, 0xc83a, 0x777f, 0xc83a, 0x21, 0 + .dw 0x77c0, 0xc83a, 0x77ff, 0xc83a, 0x21, 0 + .dw 0x7840, 0xc83a, 0x787f, 0xc83a, 0x21, 0 + .dw 0x78c0, 0xc83a, 0x78ff, 0xc83a, 0x21, 0 + .dw 0x7940, 0xc83a, 0x797f, 0xc83a, 0x21, 0 + .dw 0x79c0, 0xc83a, 0x9fff, 0xc83a, 0x21, 0 + .dw 0xa040, 0xc83a, 0xa07f, 0xc83a, 0x21, 0 + .dw 0xa0c0, 0xc83a, 0xa0ff, 0xc83a, 0x21, 0 + .dw 0xa140, 0xc83a, 0xa17f, 0xc83a, 0x21, 0 + .dw 0xa1c0, 0xc83a, 0xa1ff, 0xc83a, 0x21, 0 + .dw 0xa240, 0xc83a, 0xa27f, 0xc83a, 0x21, 0 + .dw 0xa2c0, 0xc83a, 0xa2ff, 0xc83a, 0x21, 0 + .dw 0xa340, 0xc83a, 0xa37f, 0xc83a, 0x21, 0 + .dw 0xa3c0, 0xc83a, 0xa3ff, 0xc83a, 0x21, 0 + .dw 0xa440, 0xc83a, 0xa47f, 0xc83a, 0x21, 0 + .dw 0xa4c0, 0xc83a, 0xa4ff, 0xc83a, 0x21, 0 + .dw 0xa540, 0xc83a, 0xa57f, 0xc83a, 0x21, 0 + .dw 0xa5c0, 0xc83a, 0xa5ff, 0xc83a, 0x21, 0 + .dw 0xa640, 0xc83a, 0xa67f, 0xc83a, 0x21, 0 + .dw 0xa6c0, 0xc83a, 0xa6ff, 0xc83a, 0x21, 0 + .dw 0xa740, 0xc83a, 0xa77f, 0xc83a, 0x21, 0 + .dw 0xa7c0, 0xc83a, 0xa7ff, 0xc83a, 0x21, 0 + .dw 0xa840, 0xc83a, 0xa87f, 0xc83a, 0x21, 0 + .dw 0xa8c0, 0xc83a, 0xa8ff, 0xc83a, 0x21, 0 + .dw 0xa940, 0xc83a, 0xa97f, 0xc83a, 0x21, 0 + .dw 0xa9c0, 0xc83a, 0xa9ff, 0xc83a, 0x21, 0 + .dw 0xaa40, 0xc83a, 0xaa7f, 0xc83a, 0x21, 0 + .dw 0xaac0, 0xc83a, 0xaaff, 0xc83a, 0x21, 0 + .dw 0xab40, 0xc83a, 0xab7f, 0xc83a, 0x21, 0 + .dw 0xabc0, 0xc83a, 0xabff, 0xc83a, 0x21, 0 + .dw 0xac40, 0xc83a, 0xac7f, 0xc83a, 0x21, 0 + .dw 0xacc0, 0xc83a, 0xacff, 0xc83a, 0x21, 0 + .dw 0xad40, 0xc83a, 0xad7f, 0xc83a, 0x21, 0 + .dw 0xadc0, 0xc83a, 0xadff, 0xc83a, 0x21, 0 + .dw 0xae40, 0xc83a, 0xae7f, 0xc83a, 0x21, 0 + .dw 0xaec0, 0xc83a, 0xaeff, 0xc83a, 0x21, 0 + .dw 0xaf40, 0xc83a, 0xaf7f, 0xc83a, 0x21, 0 + .dw 0xafc0, 0xc83a, 0xafff, 0xc83a, 0x21, 0 + .dw 0xb040, 0xc83a, 0xb07f, 0xc83a, 0x21, 0 + .dw 0xb0c0, 0xc83a, 0xb0ff, 0xc83a, 0x21, 0 + .dw 0xb140, 0xc83a, 0xb17f, 0xc83a, 0x21, 0 + .dw 0xb1c0, 0xc83a, 0xb1ff, 0xc83a, 0x21, 0 + .dw 0xb240, 0xc83a, 0xb27f, 0xc83a, 0x21, 0 + .dw 0xb2c0, 0xc83a, 0xb2ff, 0xc83a, 0x21, 0 + .dw 0xb340, 0xc83a, 0xb37f, 0xc83a, 0x21, 0 + .dw 0xb3c0, 0xc83a, 0xb3ff, 0xc83a, 0x21, 0 + .dw 0xb440, 0xc83a, 0xb47f, 0xc83a, 0x21, 0 + .dw 0xb4c0, 0xc83a, 0xb4ff, 0xc83a, 0x21, 0 + .dw 0xb540, 0xc83a, 0xb57f, 0xc83a, 0x21, 0 + .dw 0xb5c0, 0xc83a, 0xb5ff, 0xc83a, 0x21, 0 + .dw 0xb640, 0xc83a, 0xb67f, 0xc83a, 0x21, 0 + .dw 0xb6c0, 0xc83a, 0xb6ff, 0xc83a, 0x21, 0 + .dw 0xb740, 0xc83a, 0xb77f, 0xc83a, 0x21, 0 + .dw 0xb7c0, 0xc83a, 0xb7ff, 0xc83a, 0x21, 0 + .dw 0xb840, 0xc83a, 0xb87f, 0xc83a, 0x21, 0 + .dw 0xb8c0, 0xc83a, 0xb8ff, 0xc83a, 0x21, 0 + .dw 0xb940, 0xc83a, 0xb97f, 0xc83a, 0x21, 0 + .dw 0xb9c0, 0xc83a, 0xdfff, 0xc83a, 0x21, 0 + .dw 0xe040, 0xc83a, 0xe07f, 0xc83a, 0x21, 0 + .dw 0xe0c0, 0xc83a, 0xe0ff, 0xc83a, 0x21, 0 + .dw 0xe140, 0xc83a, 0xe17f, 0xc83a, 0x21, 0 + .dw 0xe1c0, 0xc83a, 0xe1ff, 0xc83a, 0x21, 0 + .dw 0xe240, 0xc83a, 0xe27f, 0xc83a, 0x21, 0 + .dw 0xe2c0, 0xc83a, 0xe2ff, 0xc83a, 0x21, 0 + .dw 0xe340, 0xc83a, 0xe37f, 0xc83a, 0x21, 0 + .dw 0xe3c0, 0xc83a, 0xe3ff, 0xc83a, 0x21, 0 + .dw 0xe440, 0xc83a, 0xe47f, 0xc83a, 0x21, 0 + .dw 0xe4c0, 0xc83a, 0xe4ff, 0xc83a, 0x21, 0 + .dw 0xe540, 0xc83a, 0xe57f, 0xc83a, 0x21, 0 + .dw 0xe5c0, 0xc83a, 0xe5ff, 0xc83a, 0x21, 0 + .dw 0xe640, 0xc83a, 0xe67f, 0xc83a, 0x21, 0 + .dw 0xe6c0, 0xc83a, 0xe6ff, 0xc83a, 0x21, 0 + .dw 0xe740, 0xc83a, 0xe77f, 0xc83a, 0x21, 0 + .dw 0xe7c0, 0xc83a, 0xe7ff, 0xc83a, 0x21, 0 + .dw 0xe840, 0xc83a, 0xe87f, 0xc83a, 0x21, 0 + .dw 0xe8c0, 0xc83a, 0xe8ff, 0xc83a, 0x21, 0 + .dw 0xe940, 0xc83a, 0xe97f, 0xc83a, 0x21, 0 + .dw 0xe9c0, 0xc83a, 0xe9ff, 0xc83a, 0x21, 0 + .dw 0xea40, 0xc83a, 0xea7f, 0xc83a, 0x21, 0 + .dw 0xeac0, 0xc83a, 0xeaff, 0xc83a, 0x21, 0 + .dw 0xeb40, 0xc83a, 0xeb7f, 0xc83a, 0x21, 0 + .dw 0xebc0, 0xc83a, 0xebff, 0xc83a, 0x21, 0 + .dw 0xec40, 0xc83a, 0xec7f, 0xc83a, 0x21, 0 + .dw 0xecc0, 0xc83a, 0xecff, 0xc83a, 0x21, 0 + .dw 0xed40, 0xc83a, 0xed7f, 0xc83a, 0x21, 0 + .dw 0xedc0, 0xc83a, 0xedff, 0xc83a, 0x21, 0 + .dw 0xee40, 0xc83a, 0xee7f, 0xc83a, 0x21, 0 + .dw 0xeec0, 0xc83a, 0xeeff, 0xc83a, 0x21, 0 + .dw 0xef40, 0xc83a, 0xef7f, 0xc83a, 0x21, 0 + .dw 0xefc0, 0xc83a, 0xefff, 0xc83a, 0x21, 0 + .dw 0xf040, 0xc83a, 0xf07f, 0xc83a, 0x21, 0 + .dw 0xf0c0, 0xc83a, 0xf0ff, 0xc83a, 0x21, 0 + .dw 0xf140, 0xc83a, 0xf17f, 0xc83a, 0x21, 0 + .dw 0xf1c0, 0xc83a, 0xf1ff, 0xc83a, 0x21, 0 + .dw 0xf240, 0xc83a, 0xf27f, 0xc83a, 0x21, 0 + .dw 0xf2c0, 0xc83a, 0xf2ff, 0xc83a, 0x21, 0 + .dw 0xf340, 0xc83a, 0xf37f, 0xc83a, 0x21, 0 + .dw 0xf3c0, 0xc83a, 0xf3ff, 0xc83a, 0x21, 0 + .dw 0xf440, 0xc83a, 0xf47f, 0xc83a, 0x21, 0 + .dw 0xf4c0, 0xc83a, 0xf4ff, 0xc83a, 0x21, 0 + .dw 0xf540, 0xc83a, 0xf57f, 0xc83a, 0x21, 0 + .dw 0xf5c0, 0xc83a, 0xf5ff, 0xc83a, 0x21, 0 + .dw 0xf640, 0xc83a, 0xf67f, 0xc83a, 0x21, 0 + .dw 0xf6c0, 0xc83a, 0xf6ff, 0xc83a, 0x21, 0 + .dw 0xf740, 0xc83a, 0xf77f, 0xc83a, 0x21, 0 + .dw 0xf7c0, 0xc83a, 0xf7ff, 0xc83a, 0x21, 0 + .dw 0xf840, 0xc83a, 0xf87f, 0xc83a, 0x21, 0 + .dw 0xf8c0, 0xc83a, 0xf8ff, 0xc83a, 0x21, 0 + .dw 0xf940, 0xc83a, 0xf97f, 0xc83a, 0x21, 0 + .dw 0xf9c0, 0xc83a, 0xffff, 0xc83b, 0x21, 0 + .dw 0x0040, 0xc83c, 0x007f, 0xc83c, 0x21, 0 + .dw 0x00c0, 0xc83c, 0x00ff, 0xc83c, 0x21, 0 + .dw 0x0140, 0xc83c, 0x017f, 0xc83c, 0x21, 0 + .dw 0x01c0, 0xc83c, 0x01ff, 0xc83c, 0x21, 0 + .dw 0x0240, 0xc83c, 0x027f, 0xc83c, 0x21, 0 + .dw 0x02c0, 0xc83c, 0x02ff, 0xc83c, 0x21, 0 + .dw 0x0340, 0xc83c, 0x037f, 0xc83c, 0x21, 0 + .dw 0x03c0, 0xc83c, 0x03ff, 0xc83c, 0x21, 0 + .dw 0x0440, 0xc83c, 0x047f, 0xc83c, 0x21, 0 + .dw 0x04c0, 0xc83c, 0x04ff, 0xc83c, 0x21, 0 + .dw 0x0540, 0xc83c, 0x057f, 0xc83c, 0x21, 0 + .dw 0x05c0, 0xc83c, 0x05ff, 0xc83c, 0x21, 0 + .dw 0x0640, 0xc83c, 0x067f, 0xc83c, 0x21, 0 + .dw 0x06c0, 0xc83c, 0x06ff, 0xc83c, 0x21, 0 + .dw 0x0740, 0xc83c, 0x077f, 0xc83c, 0x21, 0 + .dw 0x07c0, 0xc83c, 0x07ff, 0xc83c, 0x21, 0 + .dw 0x0840, 0xc83c, 0x087f, 0xc83c, 0x21, 0 + .dw 0x08c0, 0xc83c, 0x08ff, 0xc83c, 0x21, 0 + .dw 0x0940, 0xc83c, 0x097f, 0xc83c, 0x21, 0 + .dw 0x09c0, 0xc83c, 0x09ff, 0xc83c, 0x21, 0 + .dw 0x0a40, 0xc83c, 0x0a7f, 0xc83c, 0x21, 0 + .dw 0x0ac0, 0xc83c, 0x0aff, 0xc83c, 0x21, 0 + .dw 0x0b40, 0xc83c, 0x0b7f, 0xc83c, 0x21, 0 + .dw 0x0bc0, 0xc83c, 0x0bff, 0xc83c, 0x21, 0 + .dw 0x0c40, 0xc83c, 0x0c7f, 0xc83c, 0x21, 0 + .dw 0x0cc0, 0xc83c, 0x0cff, 0xc83c, 0x21, 0 + .dw 0x0d40, 0xc83c, 0x0d7f, 0xc83c, 0x21, 0 + .dw 0x0dc0, 0xc83c, 0x0dff, 0xc83c, 0x21, 0 + .dw 0x0e40, 0xc83c, 0x0e7f, 0xc83c, 0x21, 0 + .dw 0x0ec0, 0xc83c, 0x0eff, 0xc83c, 0x21, 0 + .dw 0x0f40, 0xc83c, 0x0f7f, 0xc83c, 0x21, 0 + .dw 0x0fc0, 0xc83c, 0x0fff, 0xc83c, 0x21, 0 + .dw 0x1040, 0xc83c, 0x107f, 0xc83c, 0x21, 0 + .dw 0x10c0, 0xc83c, 0x10ff, 0xc83c, 0x21, 0 + .dw 0x1140, 0xc83c, 0x117f, 0xc83c, 0x21, 0 + .dw 0x11c0, 0xc83c, 0x11ff, 0xc83c, 0x21, 0 + .dw 0x1240, 0xc83c, 0x127f, 0xc83c, 0x21, 0 + .dw 0x12c0, 0xc83c, 0x12ff, 0xc83c, 0x21, 0 + .dw 0x1340, 0xc83c, 0x137f, 0xc83c, 0x21, 0 + .dw 0x13c0, 0xc83c, 0x13ff, 0xc83c, 0x21, 0 + .dw 0x1440, 0xc83c, 0x147f, 0xc83c, 0x21, 0 + .dw 0x14c0, 0xc83c, 0x14ff, 0xc83c, 0x21, 0 + .dw 0x1540, 0xc83c, 0x157f, 0xc83c, 0x21, 0 + .dw 0x15c0, 0xc83c, 0x15ff, 0xc83c, 0x21, 0 + .dw 0x1640, 0xc83c, 0x167f, 0xc83c, 0x21, 0 + .dw 0x16c0, 0xc83c, 0x16ff, 0xc83c, 0x21, 0 + .dw 0x1740, 0xc83c, 0x177f, 0xc83c, 0x21, 0 + .dw 0x17c0, 0xc83c, 0x17ff, 0xc83c, 0x21, 0 + .dw 0x1840, 0xc83c, 0x187f, 0xc83c, 0x21, 0 + .dw 0x18c0, 0xc83c, 0x18ff, 0xc83c, 0x21, 0 + .dw 0x1940, 0xc83c, 0x197f, 0xc83c, 0x21, 0 + .dw 0x19c0, 0xc83c, 0x1fff, 0xc83c, 0x21, 0 + .dw 0x2040, 0xc83c, 0x207f, 0xc83c, 0x21, 0 + .dw 0x20c0, 0xc83c, 0x20ff, 0xc83c, 0x21, 0 + .dw 0x2140, 0xc83c, 0x217f, 0xc83c, 0x21, 0 + .dw 0x21c0, 0xc83c, 0x21ff, 0xc83c, 0x21, 0 + .dw 0x2240, 0xc83c, 0x227f, 0xc83c, 0x21, 0 + .dw 0x22c0, 0xc83c, 0x22ff, 0xc83c, 0x21, 0 + .dw 0x2340, 0xc83c, 0x237f, 0xc83c, 0x21, 0 + .dw 0x23c0, 0xc83c, 0x23ff, 0xc83c, 0x21, 0 + .dw 0x2440, 0xc83c, 0x247f, 0xc83c, 0x21, 0 + .dw 0x24c0, 0xc83c, 0x24ff, 0xc83c, 0x21, 0 + .dw 0x2540, 0xc83c, 0x257f, 0xc83c, 0x21, 0 + .dw 0x25c0, 0xc83c, 0x25ff, 0xc83c, 0x21, 0 + .dw 0x2640, 0xc83c, 0x267f, 0xc83c, 0x21, 0 + .dw 0x26c0, 0xc83c, 0x26ff, 0xc83c, 0x21, 0 + .dw 0x2740, 0xc83c, 0x277f, 0xc83c, 0x21, 0 + .dw 0x27c0, 0xc83c, 0x27ff, 0xc83c, 0x21, 0 + .dw 0x2840, 0xc83c, 0x287f, 0xc83c, 0x21, 0 + .dw 0x28c0, 0xc83c, 0x28ff, 0xc83c, 0x21, 0 + .dw 0x2940, 0xc83c, 0x297f, 0xc83c, 0x21, 0 + .dw 0x29c0, 0xc83c, 0x29ff, 0xc83c, 0x21, 0 + .dw 0x2a40, 0xc83c, 0x2a7f, 0xc83c, 0x21, 0 + .dw 0x2ac0, 0xc83c, 0x2aff, 0xc83c, 0x21, 0 + .dw 0x2b40, 0xc83c, 0x2b7f, 0xc83c, 0x21, 0 + .dw 0x2bc0, 0xc83c, 0x2bff, 0xc83c, 0x21, 0 + .dw 0x2c40, 0xc83c, 0x2c7f, 0xc83c, 0x21, 0 + .dw 0x2cc0, 0xc83c, 0x2cff, 0xc83c, 0x21, 0 + .dw 0x2d40, 0xc83c, 0x2d7f, 0xc83c, 0x21, 0 + .dw 0x2dc0, 0xc83c, 0x2dff, 0xc83c, 0x21, 0 + .dw 0x2e40, 0xc83c, 0x2e7f, 0xc83c, 0x21, 0 + .dw 0x2ec0, 0xc83c, 0x2eff, 0xc83c, 0x21, 0 + .dw 0x2f40, 0xc83c, 0x2f7f, 0xc83c, 0x21, 0 + .dw 0x2fc0, 0xc83c, 0x2fff, 0xc83c, 0x21, 0 + .dw 0x3040, 0xc83c, 0x307f, 0xc83c, 0x21, 0 + .dw 0x30c0, 0xc83c, 0x30ff, 0xc83c, 0x21, 0 + .dw 0x3140, 0xc83c, 0x317f, 0xc83c, 0x21, 0 + .dw 0x31c0, 0xc83c, 0x31ff, 0xc83c, 0x21, 0 + .dw 0x3240, 0xc83c, 0x327f, 0xc83c, 0x21, 0 + .dw 0x32c0, 0xc83c, 0x32ff, 0xc83c, 0x21, 0 + .dw 0x3340, 0xc83c, 0x337f, 0xc83c, 0x21, 0 + .dw 0x33c0, 0xc83c, 0x33ff, 0xc83c, 0x21, 0 + .dw 0x3440, 0xc83c, 0x347f, 0xc83c, 0x21, 0 + .dw 0x34c0, 0xc83c, 0x34ff, 0xc83c, 0x21, 0 + .dw 0x3540, 0xc83c, 0x357f, 0xc83c, 0x21, 0 + .dw 0x35c0, 0xc83c, 0x35ff, 0xc83c, 0x21, 0 + .dw 0x3640, 0xc83c, 0x367f, 0xc83c, 0x21, 0 + .dw 0x36c0, 0xc83c, 0x36ff, 0xc83c, 0x21, 0 + .dw 0x3740, 0xc83c, 0x377f, 0xc83c, 0x21, 0 + .dw 0x37c0, 0xc83c, 0x37ff, 0xc83c, 0x21, 0 + .dw 0x3840, 0xc83c, 0x387f, 0xc83c, 0x21, 0 + .dw 0x38c0, 0xc83c, 0x38ff, 0xc83c, 0x21, 0 + .dw 0x3940, 0xc83c, 0x397f, 0xc83c, 0x21, 0 + .dw 0x39c0, 0xc83c, 0x3fff, 0xc83c, 0x21, 0 + .dw 0x4040, 0xc83c, 0x407f, 0xc83c, 0x21, 0 + .dw 0x40c0, 0xc83c, 0x40ff, 0xc83c, 0x21, 0 + .dw 0x4140, 0xc83c, 0x417f, 0xc83c, 0x21, 0 + .dw 0x41c0, 0xc83c, 0x41ff, 0xc83c, 0x21, 0 + .dw 0x4240, 0xc83c, 0x427f, 0xc83c, 0x21, 0 + .dw 0x42c0, 0xc83c, 0x42ff, 0xc83c, 0x21, 0 + .dw 0x4340, 0xc83c, 0x437f, 0xc83c, 0x21, 0 + .dw 0x43c0, 0xc83c, 0x43ff, 0xc83c, 0x21, 0 + .dw 0x4440, 0xc83c, 0x447f, 0xc83c, 0x21, 0 + .dw 0x44c0, 0xc83c, 0x44ff, 0xc83c, 0x21, 0 + .dw 0x4540, 0xc83c, 0x457f, 0xc83c, 0x21, 0 + .dw 0x45c0, 0xc83c, 0x45ff, 0xc83c, 0x21, 0 + .dw 0x4640, 0xc83c, 0x467f, 0xc83c, 0x21, 0 + .dw 0x46c0, 0xc83c, 0x46ff, 0xc83c, 0x21, 0 + .dw 0x4740, 0xc83c, 0x477f, 0xc83c, 0x21, 0 + .dw 0x47c0, 0xc83c, 0x47ff, 0xc83c, 0x21, 0 + .dw 0x4840, 0xc83c, 0x487f, 0xc83c, 0x21, 0 + .dw 0x48c0, 0xc83c, 0x48ff, 0xc83c, 0x21, 0 + .dw 0x4940, 0xc83c, 0x497f, 0xc83c, 0x21, 0 + .dw 0x49c0, 0xc83c, 0x49ff, 0xc83c, 0x21, 0 + .dw 0x4a40, 0xc83c, 0x4a7f, 0xc83c, 0x21, 0 + .dw 0x4ac0, 0xc83c, 0x4aff, 0xc83c, 0x21, 0 + .dw 0x4b40, 0xc83c, 0x4b7f, 0xc83c, 0x21, 0 + .dw 0x4bc0, 0xc83c, 0x4bff, 0xc83c, 0x21, 0 + .dw 0x4c40, 0xc83c, 0x4c7f, 0xc83c, 0x21, 0 + .dw 0x4cc0, 0xc83c, 0x4cff, 0xc83c, 0x21, 0 + .dw 0x4d40, 0xc83c, 0x4d7f, 0xc83c, 0x21, 0 + .dw 0x4dc0, 0xc83c, 0x4dff, 0xc83c, 0x21, 0 + .dw 0x4e40, 0xc83c, 0x4e7f, 0xc83c, 0x21, 0 + .dw 0x4ec0, 0xc83c, 0x4eff, 0xc83c, 0x21, 0 + .dw 0x4f40, 0xc83c, 0x4f7f, 0xc83c, 0x21, 0 + .dw 0x4fc0, 0xc83c, 0x4fff, 0xc83c, 0x21, 0 + .dw 0x5040, 0xc83c, 0x507f, 0xc83c, 0x21, 0 + .dw 0x50c0, 0xc83c, 0x50ff, 0xc83c, 0x21, 0 + .dw 0x5140, 0xc83c, 0x517f, 0xc83c, 0x21, 0 + .dw 0x51c0, 0xc83c, 0x51ff, 0xc83c, 0x21, 0 + .dw 0x5240, 0xc83c, 0x527f, 0xc83c, 0x21, 0 + .dw 0x52c0, 0xc83c, 0x52ff, 0xc83c, 0x21, 0 + .dw 0x5340, 0xc83c, 0x537f, 0xc83c, 0x21, 0 + .dw 0x53c0, 0xc83c, 0x53ff, 0xc83c, 0x21, 0 + .dw 0x5440, 0xc83c, 0x547f, 0xc83c, 0x21, 0 + .dw 0x54c0, 0xc83c, 0x54ff, 0xc83c, 0x21, 0 + .dw 0x5540, 0xc83c, 0x557f, 0xc83c, 0x21, 0 + .dw 0x55c0, 0xc83c, 0x55ff, 0xc83c, 0x21, 0 + .dw 0x5640, 0xc83c, 0x567f, 0xc83c, 0x21, 0 + .dw 0x56c0, 0xc83c, 0x56ff, 0xc83c, 0x21, 0 + .dw 0x5740, 0xc83c, 0x577f, 0xc83c, 0x21, 0 + .dw 0x57c0, 0xc83c, 0x57ff, 0xc83c, 0x21, 0 + .dw 0x5840, 0xc83c, 0x587f, 0xc83c, 0x21, 0 + .dw 0x58c0, 0xc83c, 0x58ff, 0xc83c, 0x21, 0 + .dw 0x5940, 0xc83c, 0x597f, 0xc83c, 0x21, 0 + .dw 0x59c0, 0xc83c, 0x5fff, 0xc83c, 0x21, 0 + .dw 0x6040, 0xc83c, 0x607f, 0xc83c, 0x21, 0 + .dw 0x60c0, 0xc83c, 0x60ff, 0xc83c, 0x21, 0 + .dw 0x6140, 0xc83c, 0x617f, 0xc83c, 0x21, 0 + .dw 0x61c0, 0xc83c, 0x61ff, 0xc83c, 0x21, 0 + .dw 0x6240, 0xc83c, 0x627f, 0xc83c, 0x21, 0 + .dw 0x62c0, 0xc83c, 0x62ff, 0xc83c, 0x21, 0 + .dw 0x6340, 0xc83c, 0x637f, 0xc83c, 0x21, 0 + .dw 0x63c0, 0xc83c, 0x63ff, 0xc83c, 0x21, 0 + .dw 0x6440, 0xc83c, 0x647f, 0xc83c, 0x21, 0 + .dw 0x64c0, 0xc83c, 0x64ff, 0xc83c, 0x21, 0 + .dw 0x6540, 0xc83c, 0x657f, 0xc83c, 0x21, 0 + .dw 0x65c0, 0xc83c, 0x65ff, 0xc83c, 0x21, 0 + .dw 0x6640, 0xc83c, 0x667f, 0xc83c, 0x21, 0 + .dw 0x66c0, 0xc83c, 0x66ff, 0xc83c, 0x21, 0 + .dw 0x6740, 0xc83c, 0x677f, 0xc83c, 0x21, 0 + .dw 0x67c0, 0xc83c, 0x67ff, 0xc83c, 0x21, 0 + .dw 0x6840, 0xc83c, 0x687f, 0xc83c, 0x21, 0 + .dw 0x68c0, 0xc83c, 0x68ff, 0xc83c, 0x21, 0 + .dw 0x6940, 0xc83c, 0x697f, 0xc83c, 0x21, 0 + .dw 0x69c0, 0xc83c, 0x69ff, 0xc83c, 0x21, 0 + .dw 0x6a40, 0xc83c, 0x6a7f, 0xc83c, 0x21, 0 + .dw 0x6ac0, 0xc83c, 0x6aff, 0xc83c, 0x21, 0 + .dw 0x6b40, 0xc83c, 0x6b7f, 0xc83c, 0x21, 0 + .dw 0x6bc0, 0xc83c, 0x6bff, 0xc83c, 0x21, 0 + .dw 0x6c40, 0xc83c, 0x6c7f, 0xc83c, 0x21, 0 + .dw 0x6cc0, 0xc83c, 0x6cff, 0xc83c, 0x21, 0 + .dw 0x6d40, 0xc83c, 0x6d7f, 0xc83c, 0x21, 0 + .dw 0x6dc0, 0xc83c, 0x6dff, 0xc83c, 0x21, 0 + .dw 0x6e40, 0xc83c, 0x6e7f, 0xc83c, 0x21, 0 + .dw 0x6ec0, 0xc83c, 0x6eff, 0xc83c, 0x21, 0 + .dw 0x6f40, 0xc83c, 0x6f7f, 0xc83c, 0x21, 0 + .dw 0x6fc0, 0xc83c, 0x6fff, 0xc83c, 0x21, 0 + .dw 0x7040, 0xc83c, 0x707f, 0xc83c, 0x21, 0 + .dw 0x70c0, 0xc83c, 0x70ff, 0xc83c, 0x21, 0 + .dw 0x7140, 0xc83c, 0x717f, 0xc83c, 0x21, 0 + .dw 0x71c0, 0xc83c, 0x71ff, 0xc83c, 0x21, 0 + .dw 0x7240, 0xc83c, 0x727f, 0xc83c, 0x21, 0 + .dw 0x72c0, 0xc83c, 0x72ff, 0xc83c, 0x21, 0 + .dw 0x7340, 0xc83c, 0x737f, 0xc83c, 0x21, 0 + .dw 0x73c0, 0xc83c, 0x73ff, 0xc83c, 0x21, 0 + .dw 0x7440, 0xc83c, 0x747f, 0xc83c, 0x21, 0 + .dw 0x74c0, 0xc83c, 0x74ff, 0xc83c, 0x21, 0 + .dw 0x7540, 0xc83c, 0x757f, 0xc83c, 0x21, 0 + .dw 0x75c0, 0xc83c, 0x75ff, 0xc83c, 0x21, 0 + .dw 0x7640, 0xc83c, 0x767f, 0xc83c, 0x21, 0 + .dw 0x76c0, 0xc83c, 0x76ff, 0xc83c, 0x21, 0 + .dw 0x7740, 0xc83c, 0x777f, 0xc83c, 0x21, 0 + .dw 0x77c0, 0xc83c, 0x77ff, 0xc83c, 0x21, 0 + .dw 0x7840, 0xc83c, 0x787f, 0xc83c, 0x21, 0 + .dw 0x78c0, 0xc83c, 0x78ff, 0xc83c, 0x21, 0 + .dw 0x7940, 0xc83c, 0x797f, 0xc83c, 0x21, 0 + .dw 0x79c0, 0xc83c, 0x7fff, 0xc83c, 0x21, 0 + .dw 0x8040, 0xc83c, 0x807f, 0xc83c, 0x21, 0 + .dw 0x80c0, 0xc83c, 0x80ff, 0xc83c, 0x21, 0 + .dw 0x8140, 0xc83c, 0x817f, 0xc83c, 0x21, 0 + .dw 0x81c0, 0xc83c, 0x81ff, 0xc83c, 0x21, 0 + .dw 0x8240, 0xc83c, 0x827f, 0xc83c, 0x21, 0 + .dw 0x82c0, 0xc83c, 0x82ff, 0xc83c, 0x21, 0 + .dw 0x8340, 0xc83c, 0x837f, 0xc83c, 0x21, 0 + .dw 0x83c0, 0xc83c, 0x83ff, 0xc83c, 0x21, 0 + .dw 0x8440, 0xc83c, 0x847f, 0xc83c, 0x21, 0 + .dw 0x84c0, 0xc83c, 0x84ff, 0xc83c, 0x21, 0 + .dw 0x8540, 0xc83c, 0x857f, 0xc83c, 0x21, 0 + .dw 0x85c0, 0xc83c, 0x85ff, 0xc83c, 0x21, 0 + .dw 0x8640, 0xc83c, 0x867f, 0xc83c, 0x21, 0 + .dw 0x86c0, 0xc83c, 0x86ff, 0xc83c, 0x21, 0 + .dw 0x8740, 0xc83c, 0x877f, 0xc83c, 0x21, 0 + .dw 0x87c0, 0xc83c, 0x87ff, 0xc83c, 0x21, 0 + .dw 0x8840, 0xc83c, 0x887f, 0xc83c, 0x21, 0 + .dw 0x88c0, 0xc83c, 0x88ff, 0xc83c, 0x21, 0 + .dw 0x8940, 0xc83c, 0x897f, 0xc83c, 0x21, 0 + .dw 0x89c0, 0xc83c, 0x89ff, 0xc83c, 0x21, 0 + .dw 0x8a40, 0xc83c, 0x8a7f, 0xc83c, 0x21, 0 + .dw 0x8ac0, 0xc83c, 0x8aff, 0xc83c, 0x21, 0 + .dw 0x8b40, 0xc83c, 0x8b7f, 0xc83c, 0x21, 0 + .dw 0x8bc0, 0xc83c, 0x8bff, 0xc83c, 0x21, 0 + .dw 0x8c40, 0xc83c, 0x8c7f, 0xc83c, 0x21, 0 + .dw 0x8cc0, 0xc83c, 0x8cff, 0xc83c, 0x21, 0 + .dw 0x8d40, 0xc83c, 0x8d7f, 0xc83c, 0x21, 0 + .dw 0x8dc0, 0xc83c, 0x8dff, 0xc83c, 0x21, 0 + .dw 0x8e40, 0xc83c, 0x8e7f, 0xc83c, 0x21, 0 + .dw 0x8ec0, 0xc83c, 0x8eff, 0xc83c, 0x21, 0 + .dw 0x8f40, 0xc83c, 0x8f7f, 0xc83c, 0x21, 0 + .dw 0x8fc0, 0xc83c, 0x8fff, 0xc83c, 0x21, 0 + .dw 0x9040, 0xc83c, 0x907f, 0xc83c, 0x21, 0 + .dw 0x90c0, 0xc83c, 0x90ff, 0xc83c, 0x21, 0 + .dw 0x9140, 0xc83c, 0x917f, 0xc83c, 0x21, 0 + .dw 0x91c0, 0xc83c, 0x91ff, 0xc83c, 0x21, 0 + .dw 0x9240, 0xc83c, 0x927f, 0xc83c, 0x21, 0 + .dw 0x92c0, 0xc83c, 0x92ff, 0xc83c, 0x21, 0 + .dw 0x9340, 0xc83c, 0x937f, 0xc83c, 0x21, 0 + .dw 0x93c0, 0xc83c, 0x93ff, 0xc83c, 0x21, 0 + .dw 0x9440, 0xc83c, 0x947f, 0xc83c, 0x21, 0 + .dw 0x94c0, 0xc83c, 0x94ff, 0xc83c, 0x21, 0 + .dw 0x9540, 0xc83c, 0x957f, 0xc83c, 0x21, 0 + .dw 0x95c0, 0xc83c, 0x95ff, 0xc83c, 0x21, 0 + .dw 0x9640, 0xc83c, 0x967f, 0xc83c, 0x21, 0 + .dw 0x96c0, 0xc83c, 0x96ff, 0xc83c, 0x21, 0 + .dw 0x9740, 0xc83c, 0x977f, 0xc83c, 0x21, 0 + .dw 0x97c0, 0xc83c, 0x97ff, 0xc83c, 0x21, 0 + .dw 0x9840, 0xc83c, 0x987f, 0xc83c, 0x21, 0 + .dw 0x98c0, 0xc83c, 0x98ff, 0xc83c, 0x21, 0 + .dw 0x9940, 0xc83c, 0x997f, 0xc83c, 0x21, 0 + .dw 0x99c0, 0xc83c, 0x9fff, 0xc83c, 0x21, 0 + .dw 0xa040, 0xc83c, 0xa07f, 0xc83c, 0x21, 0 + .dw 0xa0c0, 0xc83c, 0xa0ff, 0xc83c, 0x21, 0 + .dw 0xa140, 0xc83c, 0xa17f, 0xc83c, 0x21, 0 + .dw 0xa1c0, 0xc83c, 0xa1ff, 0xc83c, 0x21, 0 + .dw 0xa240, 0xc83c, 0xa27f, 0xc83c, 0x21, 0 + .dw 0xa2c0, 0xc83c, 0xa2ff, 0xc83c, 0x21, 0 + .dw 0xa340, 0xc83c, 0xa37f, 0xc83c, 0x21, 0 + .dw 0xa3c0, 0xc83c, 0xa3ff, 0xc83c, 0x21, 0 + .dw 0xa440, 0xc83c, 0xa47f, 0xc83c, 0x21, 0 + .dw 0xa4c0, 0xc83c, 0xa4ff, 0xc83c, 0x21, 0 + .dw 0xa540, 0xc83c, 0xa57f, 0xc83c, 0x21, 0 + .dw 0xa5c0, 0xc83c, 0xa5ff, 0xc83c, 0x21, 0 + .dw 0xa640, 0xc83c, 0xa67f, 0xc83c, 0x21, 0 + .dw 0xa6c0, 0xc83c, 0xa6ff, 0xc83c, 0x21, 0 + .dw 0xa740, 0xc83c, 0xa77f, 0xc83c, 0x21, 0 + .dw 0xa7c0, 0xc83c, 0xa7ff, 0xc83c, 0x21, 0 + .dw 0xa840, 0xc83c, 0xa87f, 0xc83c, 0x21, 0 + .dw 0xa8c0, 0xc83c, 0xa8ff, 0xc83c, 0x21, 0 + .dw 0xa940, 0xc83c, 0xa97f, 0xc83c, 0x21, 0 + .dw 0xa9c0, 0xc83c, 0xa9ff, 0xc83c, 0x21, 0 + .dw 0xaa40, 0xc83c, 0xaa7f, 0xc83c, 0x21, 0 + .dw 0xaac0, 0xc83c, 0xaaff, 0xc83c, 0x21, 0 + .dw 0xab40, 0xc83c, 0xab7f, 0xc83c, 0x21, 0 + .dw 0xabc0, 0xc83c, 0xabff, 0xc83c, 0x21, 0 + .dw 0xac40, 0xc83c, 0xac7f, 0xc83c, 0x21, 0 + .dw 0xacc0, 0xc83c, 0xacff, 0xc83c, 0x21, 0 + .dw 0xad40, 0xc83c, 0xad7f, 0xc83c, 0x21, 0 + .dw 0xadc0, 0xc83c, 0xadff, 0xc83c, 0x21, 0 + .dw 0xae40, 0xc83c, 0xae7f, 0xc83c, 0x21, 0 + .dw 0xaec0, 0xc83c, 0xaeff, 0xc83c, 0x21, 0 + .dw 0xaf40, 0xc83c, 0xaf7f, 0xc83c, 0x21, 0 + .dw 0xafc0, 0xc83c, 0xafff, 0xc83c, 0x21, 0 + .dw 0xb040, 0xc83c, 0xb07f, 0xc83c, 0x21, 0 + .dw 0xb0c0, 0xc83c, 0xb0ff, 0xc83c, 0x21, 0 + .dw 0xb140, 0xc83c, 0xb17f, 0xc83c, 0x21, 0 + .dw 0xb1c0, 0xc83c, 0xb1ff, 0xc83c, 0x21, 0 + .dw 0xb240, 0xc83c, 0xb27f, 0xc83c, 0x21, 0 + .dw 0xb2c0, 0xc83c, 0xb2ff, 0xc83c, 0x21, 0 + .dw 0xb340, 0xc83c, 0xb37f, 0xc83c, 0x21, 0 + .dw 0xb3c0, 0xc83c, 0xb3ff, 0xc83c, 0x21, 0 + .dw 0xb440, 0xc83c, 0xb47f, 0xc83c, 0x21, 0 + .dw 0xb4c0, 0xc83c, 0xb4ff, 0xc83c, 0x21, 0 + .dw 0xb540, 0xc83c, 0xb57f, 0xc83c, 0x21, 0 + .dw 0xb5c0, 0xc83c, 0xb5ff, 0xc83c, 0x21, 0 + .dw 0xb640, 0xc83c, 0xb67f, 0xc83c, 0x21, 0 + .dw 0xb6c0, 0xc83c, 0xb6ff, 0xc83c, 0x21, 0 + .dw 0xb740, 0xc83c, 0xb77f, 0xc83c, 0x21, 0 + .dw 0xb7c0, 0xc83c, 0xb7ff, 0xc83c, 0x21, 0 + .dw 0xb840, 0xc83c, 0xb87f, 0xc83c, 0x21, 0 + .dw 0xb8c0, 0xc83c, 0xb8ff, 0xc83c, 0x21, 0 + .dw 0xb940, 0xc83c, 0xb97f, 0xc83c, 0x21, 0 + .dw 0xb9c0, 0xc83c, 0xbfff, 0xc83c, 0x21, 0 + .dw 0xc040, 0xc83c, 0xc07f, 0xc83c, 0x21, 0 + .dw 0xc0c0, 0xc83c, 0xc0ff, 0xc83c, 0x21, 0 + .dw 0xc140, 0xc83c, 0xc17f, 0xc83c, 0x21, 0 + .dw 0xc1c0, 0xc83c, 0xc1ff, 0xc83c, 0x21, 0 + .dw 0xc240, 0xc83c, 0xc27f, 0xc83c, 0x21, 0 + .dw 0xc2c0, 0xc83c, 0xc2ff, 0xc83c, 0x21, 0 + .dw 0xc340, 0xc83c, 0xc37f, 0xc83c, 0x21, 0 + .dw 0xc3c0, 0xc83c, 0xc3ff, 0xc83c, 0x21, 0 + .dw 0xc440, 0xc83c, 0xc47f, 0xc83c, 0x21, 0 + .dw 0xc4c0, 0xc83c, 0xc4ff, 0xc83c, 0x21, 0 + .dw 0xc540, 0xc83c, 0xc57f, 0xc83c, 0x21, 0 + .dw 0xc5c0, 0xc83c, 0xc5ff, 0xc83c, 0x21, 0 + .dw 0xc640, 0xc83c, 0xc67f, 0xc83c, 0x21, 0 + .dw 0xc6c0, 0xc83c, 0xc6ff, 0xc83c, 0x21, 0 + .dw 0xc740, 0xc83c, 0xc77f, 0xc83c, 0x21, 0 + .dw 0xc7c0, 0xc83c, 0xc7ff, 0xc83c, 0x21, 0 + .dw 0xc840, 0xc83c, 0xc87f, 0xc83c, 0x21, 0 + .dw 0xc8c0, 0xc83c, 0xc8ff, 0xc83c, 0x21, 0 + .dw 0xc940, 0xc83c, 0xc97f, 0xc83c, 0x21, 0 + .dw 0xc9c0, 0xc83c, 0xc9ff, 0xc83c, 0x21, 0 + .dw 0xca40, 0xc83c, 0xca7f, 0xc83c, 0x21, 0 + .dw 0xcac0, 0xc83c, 0xcaff, 0xc83c, 0x21, 0 + .dw 0xcb40, 0xc83c, 0xcb7f, 0xc83c, 0x21, 0 + .dw 0xcbc0, 0xc83c, 0xcbff, 0xc83c, 0x21, 0 + .dw 0xcc40, 0xc83c, 0xcc7f, 0xc83c, 0x21, 0 + .dw 0xccc0, 0xc83c, 0xccff, 0xc83c, 0x21, 0 + .dw 0xcd40, 0xc83c, 0xcd7f, 0xc83c, 0x21, 0 + .dw 0xcdc0, 0xc83c, 0xcdff, 0xc83c, 0x21, 0 + .dw 0xce40, 0xc83c, 0xce7f, 0xc83c, 0x21, 0 + .dw 0xcec0, 0xc83c, 0xceff, 0xc83c, 0x21, 0 + .dw 0xcf40, 0xc83c, 0xcf7f, 0xc83c, 0x21, 0 + .dw 0xcfc0, 0xc83c, 0xcfff, 0xc83c, 0x21, 0 + .dw 0xd040, 0xc83c, 0xd07f, 0xc83c, 0x21, 0 + .dw 0xd0c0, 0xc83c, 0xd0ff, 0xc83c, 0x21, 0 + .dw 0xd140, 0xc83c, 0xd17f, 0xc83c, 0x21, 0 + .dw 0xd1c0, 0xc83c, 0xd1ff, 0xc83c, 0x21, 0 + .dw 0xd240, 0xc83c, 0xd27f, 0xc83c, 0x21, 0 + .dw 0xd2c0, 0xc83c, 0xd2ff, 0xc83c, 0x21, 0 + .dw 0xd340, 0xc83c, 0xd37f, 0xc83c, 0x21, 0 + .dw 0xd3c0, 0xc83c, 0xd3ff, 0xc83c, 0x21, 0 + .dw 0xd440, 0xc83c, 0xd47f, 0xc83c, 0x21, 0 + .dw 0xd4c0, 0xc83c, 0xd4ff, 0xc83c, 0x21, 0 + .dw 0xd540, 0xc83c, 0xd57f, 0xc83c, 0x21, 0 + .dw 0xd5c0, 0xc83c, 0xd5ff, 0xc83c, 0x21, 0 + .dw 0xd640, 0xc83c, 0xd67f, 0xc83c, 0x21, 0 + .dw 0xd6c0, 0xc83c, 0xd6ff, 0xc83c, 0x21, 0 + .dw 0xd740, 0xc83c, 0xd77f, 0xc83c, 0x21, 0 + .dw 0xd7c0, 0xc83c, 0xd7ff, 0xc83c, 0x21, 0 + .dw 0xd840, 0xc83c, 0xd87f, 0xc83c, 0x21, 0 + .dw 0xd8c0, 0xc83c, 0xd8ff, 0xc83c, 0x21, 0 + .dw 0xd940, 0xc83c, 0xd97f, 0xc83c, 0x21, 0 + .dw 0xd9c0, 0xc83c, 0xdfff, 0xc83c, 0x21, 0 + .dw 0xe040, 0xc83c, 0xe07f, 0xc83c, 0x21, 0 + .dw 0xe0c0, 0xc83c, 0xe0ff, 0xc83c, 0x21, 0 + .dw 0xe140, 0xc83c, 0xe17f, 0xc83c, 0x21, 0 + .dw 0xe1c0, 0xc83c, 0xe1ff, 0xc83c, 0x21, 0 + .dw 0xe240, 0xc83c, 0xe27f, 0xc83c, 0x21, 0 + .dw 0xe2c0, 0xc83c, 0xe2ff, 0xc83c, 0x21, 0 + .dw 0xe340, 0xc83c, 0xe37f, 0xc83c, 0x21, 0 + .dw 0xe3c0, 0xc83c, 0xe3ff, 0xc83c, 0x21, 0 + .dw 0xe440, 0xc83c, 0xe47f, 0xc83c, 0x21, 0 + .dw 0xe4c0, 0xc83c, 0xe4ff, 0xc83c, 0x21, 0 + .dw 0xe540, 0xc83c, 0xe57f, 0xc83c, 0x21, 0 + .dw 0xe5c0, 0xc83c, 0xe5ff, 0xc83c, 0x21, 0 + .dw 0xe640, 0xc83c, 0xe67f, 0xc83c, 0x21, 0 + .dw 0xe6c0, 0xc83c, 0xe6ff, 0xc83c, 0x21, 0 + .dw 0xe740, 0xc83c, 0xe77f, 0xc83c, 0x21, 0 + .dw 0xe7c0, 0xc83c, 0xe7ff, 0xc83c, 0x21, 0 + .dw 0xe840, 0xc83c, 0xe87f, 0xc83c, 0x21, 0 + .dw 0xe8c0, 0xc83c, 0xe8ff, 0xc83c, 0x21, 0 + .dw 0xe940, 0xc83c, 0xe97f, 0xc83c, 0x21, 0 + .dw 0xe9c0, 0xc83c, 0xe9ff, 0xc83c, 0x21, 0 + .dw 0xea40, 0xc83c, 0xea7f, 0xc83c, 0x21, 0 + .dw 0xeac0, 0xc83c, 0xeaff, 0xc83c, 0x21, 0 + .dw 0xeb40, 0xc83c, 0xeb7f, 0xc83c, 0x21, 0 + .dw 0xebc0, 0xc83c, 0xebff, 0xc83c, 0x21, 0 + .dw 0xec40, 0xc83c, 0xec7f, 0xc83c, 0x21, 0 + .dw 0xecc0, 0xc83c, 0xecff, 0xc83c, 0x21, 0 + .dw 0xed40, 0xc83c, 0xed7f, 0xc83c, 0x21, 0 + .dw 0xedc0, 0xc83c, 0xedff, 0xc83c, 0x21, 0 + .dw 0xee40, 0xc83c, 0xee7f, 0xc83c, 0x21, 0 + .dw 0xeec0, 0xc83c, 0xeeff, 0xc83c, 0x21, 0 + .dw 0xef40, 0xc83c, 0xef7f, 0xc83c, 0x21, 0 + .dw 0xefc0, 0xc83c, 0xefff, 0xc83c, 0x21, 0 + .dw 0xf040, 0xc83c, 0xf07f, 0xc83c, 0x21, 0 + .dw 0xf0c0, 0xc83c, 0xf0ff, 0xc83c, 0x21, 0 + .dw 0xf140, 0xc83c, 0xf17f, 0xc83c, 0x21, 0 + .dw 0xf1c0, 0xc83c, 0xf1ff, 0xc83c, 0x21, 0 + .dw 0xf240, 0xc83c, 0xf27f, 0xc83c, 0x21, 0 + .dw 0xf2c0, 0xc83c, 0xf2ff, 0xc83c, 0x21, 0 + .dw 0xf340, 0xc83c, 0xf37f, 0xc83c, 0x21, 0 + .dw 0xf3c0, 0xc83c, 0xf3ff, 0xc83c, 0x21, 0 + .dw 0xf440, 0xc83c, 0xf47f, 0xc83c, 0x21, 0 + .dw 0xf4c0, 0xc83c, 0xf4ff, 0xc83c, 0x21, 0 + .dw 0xf540, 0xc83c, 0xf57f, 0xc83c, 0x21, 0 + .dw 0xf5c0, 0xc83c, 0xf5ff, 0xc83c, 0x21, 0 + .dw 0xf640, 0xc83c, 0xf67f, 0xc83c, 0x21, 0 + .dw 0xf6c0, 0xc83c, 0xf6ff, 0xc83c, 0x21, 0 + .dw 0xf740, 0xc83c, 0xf77f, 0xc83c, 0x21, 0 + .dw 0xf7c0, 0xc83c, 0xf7ff, 0xc83c, 0x21, 0 + .dw 0xf840, 0xc83c, 0xf87f, 0xc83c, 0x21, 0 + .dw 0xf8c0, 0xc83c, 0xf8ff, 0xc83c, 0x21, 0 + .dw 0xf940, 0xc83c, 0xf97f, 0xc83c, 0x21, 0 + .dw 0xf9c0, 0xc83c, 0xffff, 0xc83c, 0x21, 0 + .dw 0x0040, 0xc83d, 0x007f, 0xc83d, 0x21, 0 + .dw 0x00c0, 0xc83d, 0x00ff, 0xc83d, 0x21, 0 + .dw 0x0140, 0xc83d, 0x017f, 0xc83d, 0x21, 0 + .dw 0x01c0, 0xc83d, 0x01ff, 0xc83d, 0x21, 0 + .dw 0x0240, 0xc83d, 0x027f, 0xc83d, 0x21, 0 + .dw 0x02c0, 0xc83d, 0x02ff, 0xc83d, 0x21, 0 + .dw 0x0340, 0xc83d, 0x037f, 0xc83d, 0x21, 0 + .dw 0x03c0, 0xc83d, 0x03ff, 0xc83d, 0x21, 0 + .dw 0x0440, 0xc83d, 0x047f, 0xc83d, 0x21, 0 + .dw 0x04c0, 0xc83d, 0x04ff, 0xc83d, 0x21, 0 + .dw 0x0540, 0xc83d, 0x057f, 0xc83d, 0x21, 0 + .dw 0x05c0, 0xc83d, 0x05ff, 0xc83d, 0x21, 0 + .dw 0x0640, 0xc83d, 0x067f, 0xc83d, 0x21, 0 + .dw 0x06c0, 0xc83d, 0x06ff, 0xc83d, 0x21, 0 + .dw 0x0740, 0xc83d, 0x077f, 0xc83d, 0x21, 0 + .dw 0x07c0, 0xc83d, 0x07ff, 0xc83d, 0x21, 0 + .dw 0x0840, 0xc83d, 0x087f, 0xc83d, 0x21, 0 + .dw 0x08c0, 0xc83d, 0x08ff, 0xc83d, 0x21, 0 + .dw 0x0940, 0xc83d, 0x097f, 0xc83d, 0x21, 0 + .dw 0x09c0, 0xc83d, 0x09ff, 0xc83d, 0x21, 0 + .dw 0x0a40, 0xc83d, 0x0a7f, 0xc83d, 0x21, 0 + .dw 0x0ac0, 0xc83d, 0x0aff, 0xc83d, 0x21, 0 + .dw 0x0b40, 0xc83d, 0x0b7f, 0xc83d, 0x21, 0 + .dw 0x0bc0, 0xc83d, 0x0bff, 0xc83d, 0x21, 0 + .dw 0x0c40, 0xc83d, 0x0c7f, 0xc83d, 0x21, 0 + .dw 0x0cc0, 0xc83d, 0x0cff, 0xc83d, 0x21, 0 + .dw 0x0d40, 0xc83d, 0x0d7f, 0xc83d, 0x21, 0 + .dw 0x0dc0, 0xc83d, 0x0dff, 0xc83d, 0x21, 0 + .dw 0x0e40, 0xc83d, 0x0e7f, 0xc83d, 0x21, 0 + .dw 0x0ec0, 0xc83d, 0x0eff, 0xc83d, 0x21, 0 + .dw 0x0f40, 0xc83d, 0x0f7f, 0xc83d, 0x21, 0 + .dw 0x0fc0, 0xc83d, 0x0fff, 0xc83d, 0x21, 0 + .dw 0x1040, 0xc83d, 0x107f, 0xc83d, 0x21, 0 + .dw 0x10c0, 0xc83d, 0x10ff, 0xc83d, 0x21, 0 + .dw 0x1140, 0xc83d, 0x117f, 0xc83d, 0x21, 0 + .dw 0x11c0, 0xc83d, 0x11ff, 0xc83d, 0x21, 0 + .dw 0x1240, 0xc83d, 0x127f, 0xc83d, 0x21, 0 + .dw 0x12c0, 0xc83d, 0x12ff, 0xc83d, 0x21, 0 + .dw 0x1340, 0xc83d, 0x137f, 0xc83d, 0x21, 0 + .dw 0x13c0, 0xc83d, 0x13ff, 0xc83d, 0x21, 0 + .dw 0x1440, 0xc83d, 0x147f, 0xc83d, 0x21, 0 + .dw 0x14c0, 0xc83d, 0x14ff, 0xc83d, 0x21, 0 + .dw 0x1540, 0xc83d, 0x157f, 0xc83d, 0x21, 0 + .dw 0x15c0, 0xc83d, 0x15ff, 0xc83d, 0x21, 0 + .dw 0x1640, 0xc83d, 0x167f, 0xc83d, 0x21, 0 + .dw 0x16c0, 0xc83d, 0x16ff, 0xc83d, 0x21, 0 + .dw 0x1740, 0xc83d, 0x177f, 0xc83d, 0x21, 0 + .dw 0x17c0, 0xc83d, 0x17ff, 0xc83d, 0x21, 0 + .dw 0x1840, 0xc83d, 0x187f, 0xc83d, 0x21, 0 + .dw 0x18c0, 0xc83d, 0x18ff, 0xc83d, 0x21, 0 + .dw 0x1940, 0xc83d, 0x197f, 0xc83d, 0x21, 0 + .dw 0x19c0, 0xc83d, 0x1fff, 0xc83d, 0x21, 0 + .dw 0x2040, 0xc83d, 0x207f, 0xc83d, 0x21, 0 + .dw 0x20c0, 0xc83d, 0x20ff, 0xc83d, 0x21, 0 + .dw 0x2140, 0xc83d, 0x217f, 0xc83d, 0x21, 0 + .dw 0x21c0, 0xc83d, 0x21ff, 0xc83d, 0x21, 0 + .dw 0x2240, 0xc83d, 0x227f, 0xc83d, 0x21, 0 + .dw 0x22c0, 0xc83d, 0x22ff, 0xc83d, 0x21, 0 + .dw 0x2340, 0xc83d, 0x237f, 0xc83d, 0x21, 0 + .dw 0x23c0, 0xc83d, 0x23ff, 0xc83d, 0x21, 0 + .dw 0x2440, 0xc83d, 0x247f, 0xc83d, 0x21, 0 + .dw 0x24c0, 0xc83d, 0x24ff, 0xc83d, 0x21, 0 + .dw 0x2540, 0xc83d, 0x257f, 0xc83d, 0x21, 0 + .dw 0x25c0, 0xc83d, 0x25ff, 0xc83d, 0x21, 0 + .dw 0x2640, 0xc83d, 0x267f, 0xc83d, 0x21, 0 + .dw 0x26c0, 0xc83d, 0x26ff, 0xc83d, 0x21, 0 + .dw 0x2740, 0xc83d, 0x277f, 0xc83d, 0x21, 0 + .dw 0x27c0, 0xc83d, 0x27ff, 0xc83d, 0x21, 0 + .dw 0x2840, 0xc83d, 0x287f, 0xc83d, 0x21, 0 + .dw 0x28c0, 0xc83d, 0x28ff, 0xc83d, 0x21, 0 + .dw 0x2940, 0xc83d, 0x297f, 0xc83d, 0x21, 0 + .dw 0x29c0, 0xc83d, 0x29ff, 0xc83d, 0x21, 0 + .dw 0x2a40, 0xc83d, 0x2a7f, 0xc83d, 0x21, 0 + .dw 0x2ac0, 0xc83d, 0x2aff, 0xc83d, 0x21, 0 + .dw 0x2b40, 0xc83d, 0x2b7f, 0xc83d, 0x21, 0 + .dw 0x2bc0, 0xc83d, 0x2bff, 0xc83d, 0x21, 0 + .dw 0x2c40, 0xc83d, 0x2c7f, 0xc83d, 0x21, 0 + .dw 0x2cc0, 0xc83d, 0x2cff, 0xc83d, 0x21, 0 + .dw 0x2d40, 0xc83d, 0x2d7f, 0xc83d, 0x21, 0 + .dw 0x2dc0, 0xc83d, 0x2dff, 0xc83d, 0x21, 0 + .dw 0x2e40, 0xc83d, 0x2e7f, 0xc83d, 0x21, 0 + .dw 0x2ec0, 0xc83d, 0x2eff, 0xc83d, 0x21, 0 + .dw 0x2f40, 0xc83d, 0x2f7f, 0xc83d, 0x21, 0 + .dw 0x2fc0, 0xc83d, 0x2fff, 0xc83d, 0x21, 0 + .dw 0x3040, 0xc83d, 0x307f, 0xc83d, 0x21, 0 + .dw 0x30c0, 0xc83d, 0x30ff, 0xc83d, 0x21, 0 + .dw 0x3140, 0xc83d, 0x317f, 0xc83d, 0x21, 0 + .dw 0x31c0, 0xc83d, 0x31ff, 0xc83d, 0x21, 0 + .dw 0x3240, 0xc83d, 0x327f, 0xc83d, 0x21, 0 + .dw 0x32c0, 0xc83d, 0x32ff, 0xc83d, 0x21, 0 + .dw 0x3340, 0xc83d, 0x337f, 0xc83d, 0x21, 0 + .dw 0x33c0, 0xc83d, 0x33ff, 0xc83d, 0x21, 0 + .dw 0x3440, 0xc83d, 0x347f, 0xc83d, 0x21, 0 + .dw 0x34c0, 0xc83d, 0x34ff, 0xc83d, 0x21, 0 + .dw 0x3540, 0xc83d, 0x357f, 0xc83d, 0x21, 0 + .dw 0x35c0, 0xc83d, 0x35ff, 0xc83d, 0x21, 0 + .dw 0x3640, 0xc83d, 0x367f, 0xc83d, 0x21, 0 + .dw 0x36c0, 0xc83d, 0x36ff, 0xc83d, 0x21, 0 + .dw 0x3740, 0xc83d, 0x377f, 0xc83d, 0x21, 0 + .dw 0x37c0, 0xc83d, 0x37ff, 0xc83d, 0x21, 0 + .dw 0x3840, 0xc83d, 0x387f, 0xc83d, 0x21, 0 + .dw 0x38c0, 0xc83d, 0x38ff, 0xc83d, 0x21, 0 + .dw 0x3940, 0xc83d, 0x397f, 0xc83d, 0x21, 0 + .dw 0x39c0, 0xc83d, 0x3fff, 0xc83d, 0x21, 0 + .dw 0x4040, 0xc83d, 0x407f, 0xc83d, 0x21, 0 + .dw 0x40c0, 0xc83d, 0x40ff, 0xc83d, 0x21, 0 + .dw 0x4140, 0xc83d, 0x417f, 0xc83d, 0x21, 0 + .dw 0x41c0, 0xc83d, 0x41ff, 0xc83d, 0x21, 0 + .dw 0x4240, 0xc83d, 0x427f, 0xc83d, 0x21, 0 + .dw 0x42c0, 0xc83d, 0x42ff, 0xc83d, 0x21, 0 + .dw 0x4340, 0xc83d, 0x437f, 0xc83d, 0x21, 0 + .dw 0x43c0, 0xc83d, 0x43ff, 0xc83d, 0x21, 0 + .dw 0x4440, 0xc83d, 0x447f, 0xc83d, 0x21, 0 + .dw 0x44c0, 0xc83d, 0x44ff, 0xc83d, 0x21, 0 + .dw 0x4540, 0xc83d, 0x457f, 0xc83d, 0x21, 0 + .dw 0x45c0, 0xc83d, 0x45ff, 0xc83d, 0x21, 0 + .dw 0x4640, 0xc83d, 0x467f, 0xc83d, 0x21, 0 + .dw 0x46c0, 0xc83d, 0x46ff, 0xc83d, 0x21, 0 + .dw 0x4740, 0xc83d, 0x477f, 0xc83d, 0x21, 0 + .dw 0x47c0, 0xc83d, 0x47ff, 0xc83d, 0x21, 0 + .dw 0x4840, 0xc83d, 0x487f, 0xc83d, 0x21, 0 + .dw 0x48c0, 0xc83d, 0x48ff, 0xc83d, 0x21, 0 + .dw 0x4940, 0xc83d, 0x497f, 0xc83d, 0x21, 0 + .dw 0x49c0, 0xc83d, 0x49ff, 0xc83d, 0x21, 0 + .dw 0x4a40, 0xc83d, 0x4a7f, 0xc83d, 0x21, 0 + .dw 0x4ac0, 0xc83d, 0x4aff, 0xc83d, 0x21, 0 + .dw 0x4b40, 0xc83d, 0x4b7f, 0xc83d, 0x21, 0 + .dw 0x4bc0, 0xc83d, 0x4bff, 0xc83d, 0x21, 0 + .dw 0x4c40, 0xc83d, 0x4c7f, 0xc83d, 0x21, 0 + .dw 0x4cc0, 0xc83d, 0x4cff, 0xc83d, 0x21, 0 + .dw 0x4d40, 0xc83d, 0x4d7f, 0xc83d, 0x21, 0 + .dw 0x4dc0, 0xc83d, 0x4dff, 0xc83d, 0x21, 0 + .dw 0x4e40, 0xc83d, 0x4e7f, 0xc83d, 0x21, 0 + .dw 0x4ec0, 0xc83d, 0x4eff, 0xc83d, 0x21, 0 + .dw 0x4f40, 0xc83d, 0x4f7f, 0xc83d, 0x21, 0 + .dw 0x4fc0, 0xc83d, 0x4fff, 0xc83d, 0x21, 0 + .dw 0x5040, 0xc83d, 0x507f, 0xc83d, 0x21, 0 + .dw 0x50c0, 0xc83d, 0x50ff, 0xc83d, 0x21, 0 + .dw 0x5140, 0xc83d, 0x517f, 0xc83d, 0x21, 0 + .dw 0x51c0, 0xc83d, 0x51ff, 0xc83d, 0x21, 0 + .dw 0x5240, 0xc83d, 0x527f, 0xc83d, 0x21, 0 + .dw 0x52c0, 0xc83d, 0x52ff, 0xc83d, 0x21, 0 + .dw 0x5340, 0xc83d, 0x537f, 0xc83d, 0x21, 0 + .dw 0x53c0, 0xc83d, 0x53ff, 0xc83d, 0x21, 0 + .dw 0x5440, 0xc83d, 0x547f, 0xc83d, 0x21, 0 + .dw 0x54c0, 0xc83d, 0x54ff, 0xc83d, 0x21, 0 + .dw 0x5540, 0xc83d, 0x557f, 0xc83d, 0x21, 0 + .dw 0x55c0, 0xc83d, 0x55ff, 0xc83d, 0x21, 0 + .dw 0x5640, 0xc83d, 0x567f, 0xc83d, 0x21, 0 + .dw 0x56c0, 0xc83d, 0x56ff, 0xc83d, 0x21, 0 + .dw 0x5740, 0xc83d, 0x577f, 0xc83d, 0x21, 0 + .dw 0x57c0, 0xc83d, 0x57ff, 0xc83d, 0x21, 0 + .dw 0x5840, 0xc83d, 0x587f, 0xc83d, 0x21, 0 + .dw 0x58c0, 0xc83d, 0x58ff, 0xc83d, 0x21, 0 + .dw 0x5940, 0xc83d, 0x597f, 0xc83d, 0x21, 0 + .dw 0x59c0, 0xc83d, 0x5fff, 0xc83d, 0x21, 0 + .dw 0x6040, 0xc83d, 0x607f, 0xc83d, 0x21, 0 + .dw 0x60c0, 0xc83d, 0x60ff, 0xc83d, 0x21, 0 + .dw 0x6140, 0xc83d, 0x617f, 0xc83d, 0x21, 0 + .dw 0x61c0, 0xc83d, 0x61ff, 0xc83d, 0x21, 0 + .dw 0x6240, 0xc83d, 0x627f, 0xc83d, 0x21, 0 + .dw 0x62c0, 0xc83d, 0x62ff, 0xc83d, 0x21, 0 + .dw 0x6340, 0xc83d, 0x637f, 0xc83d, 0x21, 0 + .dw 0x63c0, 0xc83d, 0x63ff, 0xc83d, 0x21, 0 + .dw 0x6440, 0xc83d, 0x647f, 0xc83d, 0x21, 0 + .dw 0x64c0, 0xc83d, 0x64ff, 0xc83d, 0x21, 0 + .dw 0x6540, 0xc83d, 0x657f, 0xc83d, 0x21, 0 + .dw 0x65c0, 0xc83d, 0x65ff, 0xc83d, 0x21, 0 + .dw 0x6640, 0xc83d, 0x667f, 0xc83d, 0x21, 0 + .dw 0x66c0, 0xc83d, 0x66ff, 0xc83d, 0x21, 0 + .dw 0x6740, 0xc83d, 0x677f, 0xc83d, 0x21, 0 + .dw 0x67c0, 0xc83d, 0x67ff, 0xc83d, 0x21, 0 + .dw 0x6840, 0xc83d, 0x687f, 0xc83d, 0x21, 0 + .dw 0x68c0, 0xc83d, 0x68ff, 0xc83d, 0x21, 0 + .dw 0x6940, 0xc83d, 0x697f, 0xc83d, 0x21, 0 + .dw 0x69c0, 0xc83d, 0x69ff, 0xc83d, 0x21, 0 + .dw 0x6a40, 0xc83d, 0x6a7f, 0xc83d, 0x21, 0 + .dw 0x6ac0, 0xc83d, 0x6aff, 0xc83d, 0x21, 0 + .dw 0x6b40, 0xc83d, 0x6b7f, 0xc83d, 0x21, 0 + .dw 0x6bc0, 0xc83d, 0x6bff, 0xc83d, 0x21, 0 + .dw 0x6c40, 0xc83d, 0x6c7f, 0xc83d, 0x21, 0 + .dw 0x6cc0, 0xc83d, 0x6cff, 0xc83d, 0x21, 0 + .dw 0x6d40, 0xc83d, 0x6d7f, 0xc83d, 0x21, 0 + .dw 0x6dc0, 0xc83d, 0x6dff, 0xc83d, 0x21, 0 + .dw 0x6e40, 0xc83d, 0x6e7f, 0xc83d, 0x21, 0 + .dw 0x6ec0, 0xc83d, 0x6eff, 0xc83d, 0x21, 0 + .dw 0x6f40, 0xc83d, 0x6f7f, 0xc83d, 0x21, 0 + .dw 0x6fc0, 0xc83d, 0x6fff, 0xc83d, 0x21, 0 + .dw 0x7040, 0xc83d, 0x707f, 0xc83d, 0x21, 0 + .dw 0x70c0, 0xc83d, 0x70ff, 0xc83d, 0x21, 0 + .dw 0x7140, 0xc83d, 0x717f, 0xc83d, 0x21, 0 + .dw 0x71c0, 0xc83d, 0x71ff, 0xc83d, 0x21, 0 + .dw 0x7240, 0xc83d, 0x727f, 0xc83d, 0x21, 0 + .dw 0x72c0, 0xc83d, 0x72ff, 0xc83d, 0x21, 0 + .dw 0x7340, 0xc83d, 0x737f, 0xc83d, 0x21, 0 + .dw 0x73c0, 0xc83d, 0x73ff, 0xc83d, 0x21, 0 + .dw 0x7440, 0xc83d, 0x747f, 0xc83d, 0x21, 0 + .dw 0x74c0, 0xc83d, 0x74ff, 0xc83d, 0x21, 0 + .dw 0x7540, 0xc83d, 0x757f, 0xc83d, 0x21, 0 + .dw 0x75c0, 0xc83d, 0x75ff, 0xc83d, 0x21, 0 + .dw 0x7640, 0xc83d, 0x767f, 0xc83d, 0x21, 0 + .dw 0x76c0, 0xc83d, 0x76ff, 0xc83d, 0x21, 0 + .dw 0x7740, 0xc83d, 0x777f, 0xc83d, 0x21, 0 + .dw 0x77c0, 0xc83d, 0x77ff, 0xc83d, 0x21, 0 + .dw 0x7840, 0xc83d, 0x787f, 0xc83d, 0x21, 0 + .dw 0x78c0, 0xc83d, 0x78ff, 0xc83d, 0x21, 0 + .dw 0x7940, 0xc83d, 0x797f, 0xc83d, 0x21, 0 + .dw 0x79c0, 0xc83d, 0x7fff, 0xc83d, 0x21, 0 + .dw 0x8040, 0xc83d, 0x807f, 0xc83d, 0x21, 0 + .dw 0x80c0, 0xc83d, 0x80ff, 0xc83d, 0x21, 0 + .dw 0x8140, 0xc83d, 0x817f, 0xc83d, 0x21, 0 + .dw 0x81c0, 0xc83d, 0x81ff, 0xc83d, 0x21, 0 + .dw 0x8240, 0xc83d, 0x827f, 0xc83d, 0x21, 0 + .dw 0x82c0, 0xc83d, 0x82ff, 0xc83d, 0x21, 0 + .dw 0x8340, 0xc83d, 0x837f, 0xc83d, 0x21, 0 + .dw 0x83c0, 0xc83d, 0x83ff, 0xc83d, 0x21, 0 + .dw 0x8440, 0xc83d, 0x847f, 0xc83d, 0x21, 0 + .dw 0x84c0, 0xc83d, 0x84ff, 0xc83d, 0x21, 0 + .dw 0x8540, 0xc83d, 0x857f, 0xc83d, 0x21, 0 + .dw 0x85c0, 0xc83d, 0x85ff, 0xc83d, 0x21, 0 + .dw 0x8640, 0xc83d, 0x867f, 0xc83d, 0x21, 0 + .dw 0x86c0, 0xc83d, 0x86ff, 0xc83d, 0x21, 0 + .dw 0x8740, 0xc83d, 0x877f, 0xc83d, 0x21, 0 + .dw 0x87c0, 0xc83d, 0x87ff, 0xc83d, 0x21, 0 + .dw 0x8840, 0xc83d, 0x887f, 0xc83d, 0x21, 0 + .dw 0x88c0, 0xc83d, 0x88ff, 0xc83d, 0x21, 0 + .dw 0x8940, 0xc83d, 0x897f, 0xc83d, 0x21, 0 + .dw 0x89c0, 0xc83d, 0x89ff, 0xc83d, 0x21, 0 + .dw 0x8a40, 0xc83d, 0x8a7f, 0xc83d, 0x21, 0 + .dw 0x8ac0, 0xc83d, 0x8aff, 0xc83d, 0x21, 0 + .dw 0x8b40, 0xc83d, 0x8b7f, 0xc83d, 0x21, 0 + .dw 0x8bc0, 0xc83d, 0x8bff, 0xc83d, 0x21, 0 + .dw 0x8c40, 0xc83d, 0x8c7f, 0xc83d, 0x21, 0 + .dw 0x8cc0, 0xc83d, 0x8cff, 0xc83d, 0x21, 0 + .dw 0x8d40, 0xc83d, 0x8d7f, 0xc83d, 0x21, 0 + .dw 0x8dc0, 0xc83d, 0x8dff, 0xc83d, 0x21, 0 + .dw 0x8e40, 0xc83d, 0x8e7f, 0xc83d, 0x21, 0 + .dw 0x8ec0, 0xc83d, 0x8eff, 0xc83d, 0x21, 0 + .dw 0x8f40, 0xc83d, 0x8f7f, 0xc83d, 0x21, 0 + .dw 0x8fc0, 0xc83d, 0x8fff, 0xc83d, 0x21, 0 + .dw 0x9040, 0xc83d, 0x907f, 0xc83d, 0x21, 0 + .dw 0x90c0, 0xc83d, 0x90ff, 0xc83d, 0x21, 0 + .dw 0x9140, 0xc83d, 0x917f, 0xc83d, 0x21, 0 + .dw 0x91c0, 0xc83d, 0x91ff, 0xc83d, 0x21, 0 + .dw 0x9240, 0xc83d, 0x927f, 0xc83d, 0x21, 0 + .dw 0x92c0, 0xc83d, 0x92ff, 0xc83d, 0x21, 0 + .dw 0x9340, 0xc83d, 0x937f, 0xc83d, 0x21, 0 + .dw 0x93c0, 0xc83d, 0x93ff, 0xc83d, 0x21, 0 + .dw 0x9440, 0xc83d, 0x947f, 0xc83d, 0x21, 0 + .dw 0x94c0, 0xc83d, 0x94ff, 0xc83d, 0x21, 0 + .dw 0x9540, 0xc83d, 0x957f, 0xc83d, 0x21, 0 + .dw 0x95c0, 0xc83d, 0x95ff, 0xc83d, 0x21, 0 + .dw 0x9640, 0xc83d, 0x967f, 0xc83d, 0x21, 0 + .dw 0x96c0, 0xc83d, 0x96ff, 0xc83d, 0x21, 0 + .dw 0x9740, 0xc83d, 0x977f, 0xc83d, 0x21, 0 + .dw 0x97c0, 0xc83d, 0x97ff, 0xc83d, 0x21, 0 + .dw 0x9840, 0xc83d, 0x987f, 0xc83d, 0x21, 0 + .dw 0x98c0, 0xc83d, 0x98ff, 0xc83d, 0x21, 0 + .dw 0x9940, 0xc83d, 0x997f, 0xc83d, 0x21, 0 + .dw 0x99c0, 0xc83d, 0x9fff, 0xc83d, 0x21, 0 + .dw 0xa040, 0xc83d, 0xa07f, 0xc83d, 0x21, 0 + .dw 0xa0c0, 0xc83d, 0xa0ff, 0xc83d, 0x21, 0 + .dw 0xa140, 0xc83d, 0xa17f, 0xc83d, 0x21, 0 + .dw 0xa1c0, 0xc83d, 0xa1ff, 0xc83d, 0x21, 0 + .dw 0xa240, 0xc83d, 0xa27f, 0xc83d, 0x21, 0 + .dw 0xa2c0, 0xc83d, 0xa2ff, 0xc83d, 0x21, 0 + .dw 0xa340, 0xc83d, 0xa37f, 0xc83d, 0x21, 0 + .dw 0xa3c0, 0xc83d, 0xa3ff, 0xc83d, 0x21, 0 + .dw 0xa440, 0xc83d, 0xa47f, 0xc83d, 0x21, 0 + .dw 0xa4c0, 0xc83d, 0xa4ff, 0xc83d, 0x21, 0 + .dw 0xa540, 0xc83d, 0xa57f, 0xc83d, 0x21, 0 + .dw 0xa5c0, 0xc83d, 0xa5ff, 0xc83d, 0x21, 0 + .dw 0xa640, 0xc83d, 0xa67f, 0xc83d, 0x21, 0 + .dw 0xa6c0, 0xc83d, 0xa6ff, 0xc83d, 0x21, 0 + .dw 0xa740, 0xc83d, 0xa77f, 0xc83d, 0x21, 0 + .dw 0xa7c0, 0xc83d, 0xa7ff, 0xc83d, 0x21, 0 + .dw 0xa840, 0xc83d, 0xa87f, 0xc83d, 0x21, 0 + .dw 0xa8c0, 0xc83d, 0xa8ff, 0xc83d, 0x21, 0 + .dw 0xa940, 0xc83d, 0xa97f, 0xc83d, 0x21, 0 + .dw 0xa9c0, 0xc83d, 0xa9ff, 0xc83d, 0x21, 0 + .dw 0xaa40, 0xc83d, 0xaa7f, 0xc83d, 0x21, 0 + .dw 0xaac0, 0xc83d, 0xaaff, 0xc83d, 0x21, 0 + .dw 0xab40, 0xc83d, 0xab7f, 0xc83d, 0x21, 0 + .dw 0xabc0, 0xc83d, 0xabff, 0xc83d, 0x21, 0 + .dw 0xac40, 0xc83d, 0xac7f, 0xc83d, 0x21, 0 + .dw 0xacc0, 0xc83d, 0xacff, 0xc83d, 0x21, 0 + .dw 0xad40, 0xc83d, 0xad7f, 0xc83d, 0x21, 0 + .dw 0xadc0, 0xc83d, 0xadff, 0xc83d, 0x21, 0 + .dw 0xae40, 0xc83d, 0xae7f, 0xc83d, 0x21, 0 + .dw 0xaec0, 0xc83d, 0xaeff, 0xc83d, 0x21, 0 + .dw 0xaf40, 0xc83d, 0xaf7f, 0xc83d, 0x21, 0 + .dw 0xafc0, 0xc83d, 0xafff, 0xc83d, 0x21, 0 + .dw 0xb040, 0xc83d, 0xb07f, 0xc83d, 0x21, 0 + .dw 0xb0c0, 0xc83d, 0xb0ff, 0xc83d, 0x21, 0 + .dw 0xb140, 0xc83d, 0xb17f, 0xc83d, 0x21, 0 + .dw 0xb1c0, 0xc83d, 0xb1ff, 0xc83d, 0x21, 0 + .dw 0xb240, 0xc83d, 0xb27f, 0xc83d, 0x21, 0 + .dw 0xb2c0, 0xc83d, 0xb2ff, 0xc83d, 0x21, 0 + .dw 0xb340, 0xc83d, 0xb37f, 0xc83d, 0x21, 0 + .dw 0xb3c0, 0xc83d, 0xb3ff, 0xc83d, 0x21, 0 + .dw 0xb440, 0xc83d, 0xb47f, 0xc83d, 0x21, 0 + .dw 0xb4c0, 0xc83d, 0xb4ff, 0xc83d, 0x21, 0 + .dw 0xb540, 0xc83d, 0xb57f, 0xc83d, 0x21, 0 + .dw 0xb5c0, 0xc83d, 0xb5ff, 0xc83d, 0x21, 0 + .dw 0xb640, 0xc83d, 0xb67f, 0xc83d, 0x21, 0 + .dw 0xb6c0, 0xc83d, 0xb6ff, 0xc83d, 0x21, 0 + .dw 0xb740, 0xc83d, 0xb77f, 0xc83d, 0x21, 0 + .dw 0xb7c0, 0xc83d, 0xb7ff, 0xc83d, 0x21, 0 + .dw 0xb840, 0xc83d, 0xb87f, 0xc83d, 0x21, 0 + .dw 0xb8c0, 0xc83d, 0xb8ff, 0xc83d, 0x21, 0 + .dw 0xb940, 0xc83d, 0xb97f, 0xc83d, 0x21, 0 + .dw 0xb9c0, 0xc83d, 0xbfff, 0xc83d, 0x21, 0 + .dw 0xc040, 0xc83d, 0xc07f, 0xc83d, 0x21, 0 + .dw 0xc0c0, 0xc83d, 0xc0ff, 0xc83d, 0x21, 0 + .dw 0xc140, 0xc83d, 0xc17f, 0xc83d, 0x21, 0 + .dw 0xc1c0, 0xc83d, 0xc1ff, 0xc83d, 0x21, 0 + .dw 0xc240, 0xc83d, 0xc27f, 0xc83d, 0x21, 0 + .dw 0xc2c0, 0xc83d, 0xc2ff, 0xc83d, 0x21, 0 + .dw 0xc340, 0xc83d, 0xc37f, 0xc83d, 0x21, 0 + .dw 0xc3c0, 0xc83d, 0xc3ff, 0xc83d, 0x21, 0 + .dw 0xc440, 0xc83d, 0xc47f, 0xc83d, 0x21, 0 + .dw 0xc4c0, 0xc83d, 0xc4ff, 0xc83d, 0x21, 0 + .dw 0xc540, 0xc83d, 0xc57f, 0xc83d, 0x21, 0 + .dw 0xc5c0, 0xc83d, 0xc5ff, 0xc83d, 0x21, 0 + .dw 0xc640, 0xc83d, 0xc67f, 0xc83d, 0x21, 0 + .dw 0xc6c0, 0xc83d, 0xc6ff, 0xc83d, 0x21, 0 + .dw 0xc740, 0xc83d, 0xc77f, 0xc83d, 0x21, 0 + .dw 0xc7c0, 0xc83d, 0xc7ff, 0xc83d, 0x21, 0 + .dw 0xc840, 0xc83d, 0xc87f, 0xc83d, 0x21, 0 + .dw 0xc8c0, 0xc83d, 0xc8ff, 0xc83d, 0x21, 0 + .dw 0xc940, 0xc83d, 0xc97f, 0xc83d, 0x21, 0 + .dw 0xc9c0, 0xc83d, 0xc9ff, 0xc83d, 0x21, 0 + .dw 0xca40, 0xc83d, 0xca7f, 0xc83d, 0x21, 0 + .dw 0xcac0, 0xc83d, 0xcaff, 0xc83d, 0x21, 0 + .dw 0xcb40, 0xc83d, 0xcb7f, 0xc83d, 0x21, 0 + .dw 0xcbc0, 0xc83d, 0xcbff, 0xc83d, 0x21, 0 + .dw 0xcc40, 0xc83d, 0xcc7f, 0xc83d, 0x21, 0 + .dw 0xccc0, 0xc83d, 0xccff, 0xc83d, 0x21, 0 + .dw 0xcd40, 0xc83d, 0xcd7f, 0xc83d, 0x21, 0 + .dw 0xcdc0, 0xc83d, 0xcdff, 0xc83d, 0x21, 0 + .dw 0xce40, 0xc83d, 0xce7f, 0xc83d, 0x21, 0 + .dw 0xcec0, 0xc83d, 0xceff, 0xc83d, 0x21, 0 + .dw 0xcf40, 0xc83d, 0xcf7f, 0xc83d, 0x21, 0 + .dw 0xcfc0, 0xc83d, 0xcfff, 0xc83d, 0x21, 0 + .dw 0xd040, 0xc83d, 0xd07f, 0xc83d, 0x21, 0 + .dw 0xd0c0, 0xc83d, 0xd0ff, 0xc83d, 0x21, 0 + .dw 0xd140, 0xc83d, 0xd17f, 0xc83d, 0x21, 0 + .dw 0xd1c0, 0xc83d, 0xd1ff, 0xc83d, 0x21, 0 + .dw 0xd240, 0xc83d, 0xd27f, 0xc83d, 0x21, 0 + .dw 0xd2c0, 0xc83d, 0xd2ff, 0xc83d, 0x21, 0 + .dw 0xd340, 0xc83d, 0xd37f, 0xc83d, 0x21, 0 + .dw 0xd3c0, 0xc83d, 0xd3ff, 0xc83d, 0x21, 0 + .dw 0xd440, 0xc83d, 0xd47f, 0xc83d, 0x21, 0 + .dw 0xd4c0, 0xc83d, 0xd4ff, 0xc83d, 0x21, 0 + .dw 0xd540, 0xc83d, 0xd57f, 0xc83d, 0x21, 0 + .dw 0xd5c0, 0xc83d, 0xd5ff, 0xc83d, 0x21, 0 + .dw 0xd640, 0xc83d, 0xd67f, 0xc83d, 0x21, 0 + .dw 0xd6c0, 0xc83d, 0xd6ff, 0xc83d, 0x21, 0 + .dw 0xd740, 0xc83d, 0xd77f, 0xc83d, 0x21, 0 + .dw 0xd7c0, 0xc83d, 0xd7ff, 0xc83d, 0x21, 0 + .dw 0xd840, 0xc83d, 0xd87f, 0xc83d, 0x21, 0 + .dw 0xd8c0, 0xc83d, 0xd8ff, 0xc83d, 0x21, 0 + .dw 0xd940, 0xc83d, 0xd97f, 0xc83d, 0x21, 0 + .dw 0xd9c0, 0xc83d, 0xdfff, 0xc83d, 0x21, 0 + .dw 0xe040, 0xc83d, 0xe07f, 0xc83d, 0x21, 0 + .dw 0xe0c0, 0xc83d, 0xe0ff, 0xc83d, 0x21, 0 + .dw 0xe140, 0xc83d, 0xe17f, 0xc83d, 0x21, 0 + .dw 0xe1c0, 0xc83d, 0xe1ff, 0xc83d, 0x21, 0 + .dw 0xe240, 0xc83d, 0xe27f, 0xc83d, 0x21, 0 + .dw 0xe2c0, 0xc83d, 0xe2ff, 0xc83d, 0x21, 0 + .dw 0xe340, 0xc83d, 0xe37f, 0xc83d, 0x21, 0 + .dw 0xe3c0, 0xc83d, 0xe3ff, 0xc83d, 0x21, 0 + .dw 0xe440, 0xc83d, 0xe47f, 0xc83d, 0x21, 0 + .dw 0xe4c0, 0xc83d, 0xe4ff, 0xc83d, 0x21, 0 + .dw 0xe540, 0xc83d, 0xe57f, 0xc83d, 0x21, 0 + .dw 0xe5c0, 0xc83d, 0xe5ff, 0xc83d, 0x21, 0 + .dw 0xe640, 0xc83d, 0xe67f, 0xc83d, 0x21, 0 + .dw 0xe6c0, 0xc83d, 0xe6ff, 0xc83d, 0x21, 0 + .dw 0xe740, 0xc83d, 0xe77f, 0xc83d, 0x21, 0 + .dw 0xe7c0, 0xc83d, 0xe7ff, 0xc83d, 0x21, 0 + .dw 0xe840, 0xc83d, 0xe87f, 0xc83d, 0x21, 0 + .dw 0xe8c0, 0xc83d, 0xe8ff, 0xc83d, 0x21, 0 + .dw 0xe940, 0xc83d, 0xe97f, 0xc83d, 0x21, 0 + .dw 0xe9c0, 0xc83d, 0xe9ff, 0xc83d, 0x21, 0 + .dw 0xea40, 0xc83d, 0xea7f, 0xc83d, 0x21, 0 + .dw 0xeac0, 0xc83d, 0xeaff, 0xc83d, 0x21, 0 + .dw 0xeb40, 0xc83d, 0xeb7f, 0xc83d, 0x21, 0 + .dw 0xebc0, 0xc83d, 0xebff, 0xc83d, 0x21, 0 + .dw 0xec40, 0xc83d, 0xec7f, 0xc83d, 0x21, 0 + .dw 0xecc0, 0xc83d, 0xecff, 0xc83d, 0x21, 0 + .dw 0xed40, 0xc83d, 0xed7f, 0xc83d, 0x21, 0 + .dw 0xedc0, 0xc83d, 0xedff, 0xc83d, 0x21, 0 + .dw 0xee40, 0xc83d, 0xee7f, 0xc83d, 0x21, 0 + .dw 0xeec0, 0xc83d, 0xeeff, 0xc83d, 0x21, 0 + .dw 0xef40, 0xc83d, 0xef7f, 0xc83d, 0x21, 0 + .dw 0xefc0, 0xc83d, 0xefff, 0xc83d, 0x21, 0 + .dw 0xf040, 0xc83d, 0xf07f, 0xc83d, 0x21, 0 + .dw 0xf0c0, 0xc83d, 0xf0ff, 0xc83d, 0x21, 0 + .dw 0xf140, 0xc83d, 0xf17f, 0xc83d, 0x21, 0 + .dw 0xf1c0, 0xc83d, 0xf1ff, 0xc83d, 0x21, 0 + .dw 0xf240, 0xc83d, 0xf27f, 0xc83d, 0x21, 0 + .dw 0xf2c0, 0xc83d, 0xf2ff, 0xc83d, 0x21, 0 + .dw 0xf340, 0xc83d, 0xf37f, 0xc83d, 0x21, 0 + .dw 0xf3c0, 0xc83d, 0xf3ff, 0xc83d, 0x21, 0 + .dw 0xf440, 0xc83d, 0xf47f, 0xc83d, 0x21, 0 + .dw 0xf4c0, 0xc83d, 0xf4ff, 0xc83d, 0x21, 0 + .dw 0xf540, 0xc83d, 0xf57f, 0xc83d, 0x21, 0 + .dw 0xf5c0, 0xc83d, 0xf5ff, 0xc83d, 0x21, 0 + .dw 0xf640, 0xc83d, 0xf67f, 0xc83d, 0x21, 0 + .dw 0xf6c0, 0xc83d, 0xf6ff, 0xc83d, 0x21, 0 + .dw 0xf740, 0xc83d, 0xf77f, 0xc83d, 0x21, 0 + .dw 0xf7c0, 0xc83d, 0xf7ff, 0xc83d, 0x21, 0 + .dw 0xf840, 0xc83d, 0xf87f, 0xc83d, 0x21, 0 + .dw 0xf8c0, 0xc83d, 0xf8ff, 0xc83d, 0x21, 0 + .dw 0xf940, 0xc83d, 0xf97f, 0xc83d, 0x21, 0 + .dw 0xf9c0, 0xc83d, 0xffff, 0xc83d, 0x21, 0 + .dw 0x0040, 0xc83e, 0x007f, 0xc83e, 0x21, 0 + .dw 0x00c0, 0xc83e, 0x00ff, 0xc83e, 0x21, 0 + .dw 0x0140, 0xc83e, 0x017f, 0xc83e, 0x21, 0 + .dw 0x01c0, 0xc83e, 0x01ff, 0xc83e, 0x21, 0 + .dw 0x0240, 0xc83e, 0x027f, 0xc83e, 0x21, 0 + .dw 0x02c0, 0xc83e, 0x02ff, 0xc83e, 0x21, 0 + .dw 0x0340, 0xc83e, 0x037f, 0xc83e, 0x21, 0 + .dw 0x03c0, 0xc83e, 0x03ff, 0xc83e, 0x21, 0 + .dw 0x0440, 0xc83e, 0x047f, 0xc83e, 0x21, 0 + .dw 0x04c0, 0xc83e, 0x04ff, 0xc83e, 0x21, 0 + .dw 0x0540, 0xc83e, 0x057f, 0xc83e, 0x21, 0 + .dw 0x05c0, 0xc83e, 0x05ff, 0xc83e, 0x21, 0 + .dw 0x0640, 0xc83e, 0x067f, 0xc83e, 0x21, 0 + .dw 0x06c0, 0xc83e, 0x06ff, 0xc83e, 0x21, 0 + .dw 0x0740, 0xc83e, 0x077f, 0xc83e, 0x21, 0 + .dw 0x07c0, 0xc83e, 0x07ff, 0xc83e, 0x21, 0 + .dw 0x0840, 0xc83e, 0x087f, 0xc83e, 0x21, 0 + .dw 0x08c0, 0xc83e, 0x08ff, 0xc83e, 0x21, 0 + .dw 0x0940, 0xc83e, 0x097f, 0xc83e, 0x21, 0 + .dw 0x09c0, 0xc83e, 0x09ff, 0xc83e, 0x21, 0 + .dw 0x0a40, 0xc83e, 0x0a7f, 0xc83e, 0x21, 0 + .dw 0x0ac0, 0xc83e, 0x0aff, 0xc83e, 0x21, 0 + .dw 0x0b40, 0xc83e, 0x0b7f, 0xc83e, 0x21, 0 + .dw 0x0bc0, 0xc83e, 0x0bff, 0xc83e, 0x21, 0 + .dw 0x0c40, 0xc83e, 0x0c7f, 0xc83e, 0x21, 0 + .dw 0x0cc0, 0xc83e, 0x0cff, 0xc83e, 0x21, 0 + .dw 0x0d40, 0xc83e, 0x0d7f, 0xc83e, 0x21, 0 + .dw 0x0dc0, 0xc83e, 0x0dff, 0xc83e, 0x21, 0 + .dw 0x0e40, 0xc83e, 0x0e7f, 0xc83e, 0x21, 0 + .dw 0x0ec0, 0xc83e, 0x0eff, 0xc83e, 0x21, 0 + .dw 0x0f40, 0xc83e, 0x0f7f, 0xc83e, 0x21, 0 + .dw 0x0fc0, 0xc83e, 0x0fff, 0xc83e, 0x21, 0 + .dw 0x1040, 0xc83e, 0x107f, 0xc83e, 0x21, 0 + .dw 0x10c0, 0xc83e, 0x10ff, 0xc83e, 0x21, 0 + .dw 0x1140, 0xc83e, 0x117f, 0xc83e, 0x21, 0 + .dw 0x11c0, 0xc83e, 0x11ff, 0xc83e, 0x21, 0 + .dw 0x1240, 0xc83e, 0x127f, 0xc83e, 0x21, 0 + .dw 0x12c0, 0xc83e, 0x12ff, 0xc83e, 0x21, 0 + .dw 0x1340, 0xc83e, 0x137f, 0xc83e, 0x21, 0 + .dw 0x13c0, 0xc83e, 0x13ff, 0xc83e, 0x21, 0 + .dw 0x1440, 0xc83e, 0x147f, 0xc83e, 0x21, 0 + .dw 0x14c0, 0xc83e, 0x14ff, 0xc83e, 0x21, 0 + .dw 0x1540, 0xc83e, 0x157f, 0xc83e, 0x21, 0 + .dw 0x15c0, 0xc83e, 0x15ff, 0xc83e, 0x21, 0 + .dw 0x1640, 0xc83e, 0x167f, 0xc83e, 0x21, 0 + .dw 0x16c0, 0xc83e, 0x16ff, 0xc83e, 0x21, 0 + .dw 0x1740, 0xc83e, 0x177f, 0xc83e, 0x21, 0 + .dw 0x17c0, 0xc83e, 0x17ff, 0xc83e, 0x21, 0 + .dw 0x1840, 0xc83e, 0x187f, 0xc83e, 0x21, 0 + .dw 0x18c0, 0xc83e, 0x18ff, 0xc83e, 0x21, 0 + .dw 0x1940, 0xc83e, 0x197f, 0xc83e, 0x21, 0 + .dw 0x19c0, 0xc83e, 0x1fff, 0xc83e, 0x21, 0 + .dw 0x2040, 0xc83e, 0x207f, 0xc83e, 0x21, 0 + .dw 0x20c0, 0xc83e, 0x20ff, 0xc83e, 0x21, 0 + .dw 0x2140, 0xc83e, 0x217f, 0xc83e, 0x21, 0 + .dw 0x21c0, 0xc83e, 0x21ff, 0xc83e, 0x21, 0 + .dw 0x2240, 0xc83e, 0x227f, 0xc83e, 0x21, 0 + .dw 0x22c0, 0xc83e, 0x22ff, 0xc83e, 0x21, 0 + .dw 0x2340, 0xc83e, 0x237f, 0xc83e, 0x21, 0 + .dw 0x23c0, 0xc83e, 0x23ff, 0xc83e, 0x21, 0 + .dw 0x2440, 0xc83e, 0x247f, 0xc83e, 0x21, 0 + .dw 0x24c0, 0xc83e, 0x24ff, 0xc83e, 0x21, 0 + .dw 0x2540, 0xc83e, 0x257f, 0xc83e, 0x21, 0 + .dw 0x25c0, 0xc83e, 0x25ff, 0xc83e, 0x21, 0 + .dw 0x2640, 0xc83e, 0x267f, 0xc83e, 0x21, 0 + .dw 0x26c0, 0xc83e, 0x26ff, 0xc83e, 0x21, 0 + .dw 0x2740, 0xc83e, 0x277f, 0xc83e, 0x21, 0 + .dw 0x27c0, 0xc83e, 0x27ff, 0xc83e, 0x21, 0 + .dw 0x2840, 0xc83e, 0x287f, 0xc83e, 0x21, 0 + .dw 0x28c0, 0xc83e, 0x28ff, 0xc83e, 0x21, 0 + .dw 0x2940, 0xc83e, 0x297f, 0xc83e, 0x21, 0 + .dw 0x29c0, 0xc83e, 0x29ff, 0xc83e, 0x21, 0 + .dw 0x2a40, 0xc83e, 0x2a7f, 0xc83e, 0x21, 0 + .dw 0x2ac0, 0xc83e, 0x2aff, 0xc83e, 0x21, 0 + .dw 0x2b40, 0xc83e, 0x2b7f, 0xc83e, 0x21, 0 + .dw 0x2bc0, 0xc83e, 0x2bff, 0xc83e, 0x21, 0 + .dw 0x2c40, 0xc83e, 0x2c7f, 0xc83e, 0x21, 0 + .dw 0x2cc0, 0xc83e, 0x2cff, 0xc83e, 0x21, 0 + .dw 0x2d40, 0xc83e, 0x2d7f, 0xc83e, 0x21, 0 + .dw 0x2dc0, 0xc83e, 0x2dff, 0xc83e, 0x21, 0 + .dw 0x2e40, 0xc83e, 0x2e7f, 0xc83e, 0x21, 0 + .dw 0x2ec0, 0xc83e, 0x2eff, 0xc83e, 0x21, 0 + .dw 0x2f40, 0xc83e, 0x2f7f, 0xc83e, 0x21, 0 + .dw 0x2fc0, 0xc83e, 0x2fff, 0xc83e, 0x21, 0 + .dw 0x3040, 0xc83e, 0x307f, 0xc83e, 0x21, 0 + .dw 0x30c0, 0xc83e, 0x30ff, 0xc83e, 0x21, 0 + .dw 0x3140, 0xc83e, 0x317f, 0xc83e, 0x21, 0 + .dw 0x31c0, 0xc83e, 0x31ff, 0xc83e, 0x21, 0 + .dw 0x3240, 0xc83e, 0x327f, 0xc83e, 0x21, 0 + .dw 0x32c0, 0xc83e, 0x32ff, 0xc83e, 0x21, 0 + .dw 0x3340, 0xc83e, 0x337f, 0xc83e, 0x21, 0 + .dw 0x33c0, 0xc83e, 0x33ff, 0xc83e, 0x21, 0 + .dw 0x3440, 0xc83e, 0x347f, 0xc83e, 0x21, 0 + .dw 0x34c0, 0xc83e, 0x34ff, 0xc83e, 0x21, 0 + .dw 0x3540, 0xc83e, 0x357f, 0xc83e, 0x21, 0 + .dw 0x35c0, 0xc83e, 0x35ff, 0xc83e, 0x21, 0 + .dw 0x3640, 0xc83e, 0x367f, 0xc83e, 0x21, 0 + .dw 0x36c0, 0xc83e, 0x36ff, 0xc83e, 0x21, 0 + .dw 0x3740, 0xc83e, 0x377f, 0xc83e, 0x21, 0 + .dw 0x37c0, 0xc83e, 0x37ff, 0xc83e, 0x21, 0 + .dw 0x3840, 0xc83e, 0x387f, 0xc83e, 0x21, 0 + .dw 0x38c0, 0xc83e, 0x38ff, 0xc83e, 0x21, 0 + .dw 0x3940, 0xc83e, 0x397f, 0xc83e, 0x21, 0 + .dw 0x39c0, 0xc83e, 0x3fff, 0xc83e, 0x21, 0 + .dw 0x4040, 0xc83e, 0x407f, 0xc83e, 0x21, 0 + .dw 0x40c0, 0xc83e, 0x40ff, 0xc83e, 0x21, 0 + .dw 0x4140, 0xc83e, 0x417f, 0xc83e, 0x21, 0 + .dw 0x41c0, 0xc83e, 0x41ff, 0xc83e, 0x21, 0 + .dw 0x4240, 0xc83e, 0x427f, 0xc83e, 0x21, 0 + .dw 0x42c0, 0xc83e, 0x42ff, 0xc83e, 0x21, 0 + .dw 0x4340, 0xc83e, 0x437f, 0xc83e, 0x21, 0 + .dw 0x43c0, 0xc83e, 0x43ff, 0xc83e, 0x21, 0 + .dw 0x4440, 0xc83e, 0x447f, 0xc83e, 0x21, 0 + .dw 0x44c0, 0xc83e, 0x44ff, 0xc83e, 0x21, 0 + .dw 0x4540, 0xc83e, 0x457f, 0xc83e, 0x21, 0 + .dw 0x45c0, 0xc83e, 0x45ff, 0xc83e, 0x21, 0 + .dw 0x4640, 0xc83e, 0x467f, 0xc83e, 0x21, 0 + .dw 0x46c0, 0xc83e, 0x46ff, 0xc83e, 0x21, 0 + .dw 0x4740, 0xc83e, 0x477f, 0xc83e, 0x21, 0 + .dw 0x47c0, 0xc83e, 0x47ff, 0xc83e, 0x21, 0 + .dw 0x4840, 0xc83e, 0x487f, 0xc83e, 0x21, 0 + .dw 0x48c0, 0xc83e, 0x48ff, 0xc83e, 0x21, 0 + .dw 0x4940, 0xc83e, 0x497f, 0xc83e, 0x21, 0 + .dw 0x49c0, 0xc83e, 0x49ff, 0xc83e, 0x21, 0 + .dw 0x4a40, 0xc83e, 0x4a7f, 0xc83e, 0x21, 0 + .dw 0x4ac0, 0xc83e, 0x4aff, 0xc83e, 0x21, 0 + .dw 0x4b40, 0xc83e, 0x4b7f, 0xc83e, 0x21, 0 + .dw 0x4bc0, 0xc83e, 0x4bff, 0xc83e, 0x21, 0 + .dw 0x4c40, 0xc83e, 0x4c7f, 0xc83e, 0x21, 0 + .dw 0x4cc0, 0xc83e, 0x4cff, 0xc83e, 0x21, 0 + .dw 0x4d40, 0xc83e, 0x4d7f, 0xc83e, 0x21, 0 + .dw 0x4dc0, 0xc83e, 0x4dff, 0xc83e, 0x21, 0 + .dw 0x4e40, 0xc83e, 0x4e7f, 0xc83e, 0x21, 0 + .dw 0x4ec0, 0xc83e, 0x4eff, 0xc83e, 0x21, 0 + .dw 0x4f40, 0xc83e, 0x4f7f, 0xc83e, 0x21, 0 + .dw 0x4fc0, 0xc83e, 0x4fff, 0xc83e, 0x21, 0 + .dw 0x5040, 0xc83e, 0x507f, 0xc83e, 0x21, 0 + .dw 0x50c0, 0xc83e, 0x50ff, 0xc83e, 0x21, 0 + .dw 0x5140, 0xc83e, 0x517f, 0xc83e, 0x21, 0 + .dw 0x51c0, 0xc83e, 0x51ff, 0xc83e, 0x21, 0 + .dw 0x5240, 0xc83e, 0x527f, 0xc83e, 0x21, 0 + .dw 0x52c0, 0xc83e, 0x52ff, 0xc83e, 0x21, 0 + .dw 0x5340, 0xc83e, 0x537f, 0xc83e, 0x21, 0 + .dw 0x53c0, 0xc83e, 0x53ff, 0xc83e, 0x21, 0 + .dw 0x5440, 0xc83e, 0x547f, 0xc83e, 0x21, 0 + .dw 0x54c0, 0xc83e, 0x54ff, 0xc83e, 0x21, 0 + .dw 0x5540, 0xc83e, 0x557f, 0xc83e, 0x21, 0 + .dw 0x55c0, 0xc83e, 0x55ff, 0xc83e, 0x21, 0 + .dw 0x5640, 0xc83e, 0x567f, 0xc83e, 0x21, 0 + .dw 0x56c0, 0xc83e, 0x56ff, 0xc83e, 0x21, 0 + .dw 0x5740, 0xc83e, 0x577f, 0xc83e, 0x21, 0 + .dw 0x57c0, 0xc83e, 0x57ff, 0xc83e, 0x21, 0 + .dw 0x5840, 0xc83e, 0x587f, 0xc83e, 0x21, 0 + .dw 0x58c0, 0xc83e, 0x58ff, 0xc83e, 0x21, 0 + .dw 0x5940, 0xc83e, 0x597f, 0xc83e, 0x21, 0 + .dw 0x59c0, 0xc83e, 0x5fff, 0xc83e, 0x21, 0 + .dw 0x6040, 0xc83e, 0x607f, 0xc83e, 0x21, 0 + .dw 0x60c0, 0xc83e, 0x60ff, 0xc83e, 0x21, 0 + .dw 0x6140, 0xc83e, 0x617f, 0xc83e, 0x21, 0 + .dw 0x61c0, 0xc83e, 0x61ff, 0xc83e, 0x21, 0 + .dw 0x6240, 0xc83e, 0x627f, 0xc83e, 0x21, 0 + .dw 0x62c0, 0xc83e, 0x62ff, 0xc83e, 0x21, 0 + .dw 0x6340, 0xc83e, 0x637f, 0xc83e, 0x21, 0 + .dw 0x63c0, 0xc83e, 0x63ff, 0xc83e, 0x21, 0 + .dw 0x6440, 0xc83e, 0x647f, 0xc83e, 0x21, 0 + .dw 0x64c0, 0xc83e, 0x64ff, 0xc83e, 0x21, 0 + .dw 0x6540, 0xc83e, 0x657f, 0xc83e, 0x21, 0 + .dw 0x65c0, 0xc83e, 0x65ff, 0xc83e, 0x21, 0 + .dw 0x6640, 0xc83e, 0x667f, 0xc83e, 0x21, 0 + .dw 0x66c0, 0xc83e, 0x66ff, 0xc83e, 0x21, 0 + .dw 0x6740, 0xc83e, 0x677f, 0xc83e, 0x21, 0 + .dw 0x67c0, 0xc83e, 0x67ff, 0xc83e, 0x21, 0 + .dw 0x6840, 0xc83e, 0x687f, 0xc83e, 0x21, 0 + .dw 0x68c0, 0xc83e, 0x68ff, 0xc83e, 0x21, 0 + .dw 0x6940, 0xc83e, 0x697f, 0xc83e, 0x21, 0 + .dw 0x69c0, 0xc83e, 0x69ff, 0xc83e, 0x21, 0 + .dw 0x6a40, 0xc83e, 0x6a7f, 0xc83e, 0x21, 0 + .dw 0x6ac0, 0xc83e, 0x6aff, 0xc83e, 0x21, 0 + .dw 0x6b40, 0xc83e, 0x6b7f, 0xc83e, 0x21, 0 + .dw 0x6bc0, 0xc83e, 0x6bff, 0xc83e, 0x21, 0 + .dw 0x6c40, 0xc83e, 0x6c7f, 0xc83e, 0x21, 0 + .dw 0x6cc0, 0xc83e, 0x6cff, 0xc83e, 0x21, 0 + .dw 0x6d40, 0xc83e, 0x6d7f, 0xc83e, 0x21, 0 + .dw 0x6dc0, 0xc83e, 0x6dff, 0xc83e, 0x21, 0 + .dw 0x6e40, 0xc83e, 0x6e7f, 0xc83e, 0x21, 0 + .dw 0x6ec0, 0xc83e, 0x6eff, 0xc83e, 0x21, 0 + .dw 0x6f40, 0xc83e, 0x6f7f, 0xc83e, 0x21, 0 + .dw 0x6fc0, 0xc83e, 0x6fff, 0xc83e, 0x21, 0 + .dw 0x7040, 0xc83e, 0x707f, 0xc83e, 0x21, 0 + .dw 0x70c0, 0xc83e, 0x70ff, 0xc83e, 0x21, 0 + .dw 0x7140, 0xc83e, 0x717f, 0xc83e, 0x21, 0 + .dw 0x71c0, 0xc83e, 0x71ff, 0xc83e, 0x21, 0 + .dw 0x7240, 0xc83e, 0x727f, 0xc83e, 0x21, 0 + .dw 0x72c0, 0xc83e, 0x72ff, 0xc83e, 0x21, 0 + .dw 0x7340, 0xc83e, 0x737f, 0xc83e, 0x21, 0 + .dw 0x73c0, 0xc83e, 0x73ff, 0xc83e, 0x21, 0 + .dw 0x7440, 0xc83e, 0x747f, 0xc83e, 0x21, 0 + .dw 0x74c0, 0xc83e, 0x74ff, 0xc83e, 0x21, 0 + .dw 0x7540, 0xc83e, 0x757f, 0xc83e, 0x21, 0 + .dw 0x75c0, 0xc83e, 0x75ff, 0xc83e, 0x21, 0 + .dw 0x7640, 0xc83e, 0x767f, 0xc83e, 0x21, 0 + .dw 0x76c0, 0xc83e, 0x76ff, 0xc83e, 0x21, 0 + .dw 0x7740, 0xc83e, 0x777f, 0xc83e, 0x21, 0 + .dw 0x77c0, 0xc83e, 0x77ff, 0xc83e, 0x21, 0 + .dw 0x7840, 0xc83e, 0x787f, 0xc83e, 0x21, 0 + .dw 0x78c0, 0xc83e, 0x78ff, 0xc83e, 0x21, 0 + .dw 0x7940, 0xc83e, 0x797f, 0xc83e, 0x21, 0 + .dw 0x79c0, 0xc83e, 0x7fff, 0xc83e, 0x21, 0 + .dw 0x8040, 0xc83e, 0x807f, 0xc83e, 0x21, 0 + .dw 0x80c0, 0xc83e, 0x80ff, 0xc83e, 0x21, 0 + .dw 0x8140, 0xc83e, 0x817f, 0xc83e, 0x21, 0 + .dw 0x81c0, 0xc83e, 0x81ff, 0xc83e, 0x21, 0 + .dw 0x8240, 0xc83e, 0x827f, 0xc83e, 0x21, 0 + .dw 0x82c0, 0xc83e, 0x82ff, 0xc83e, 0x21, 0 + .dw 0x8340, 0xc83e, 0x837f, 0xc83e, 0x21, 0 + .dw 0x83c0, 0xc83e, 0x83ff, 0xc83e, 0x21, 0 + .dw 0x8440, 0xc83e, 0x847f, 0xc83e, 0x21, 0 + .dw 0x84c0, 0xc83e, 0x84ff, 0xc83e, 0x21, 0 + .dw 0x8540, 0xc83e, 0x857f, 0xc83e, 0x21, 0 + .dw 0x85c0, 0xc83e, 0x85ff, 0xc83e, 0x21, 0 + .dw 0x8640, 0xc83e, 0x867f, 0xc83e, 0x21, 0 + .dw 0x86c0, 0xc83e, 0x86ff, 0xc83e, 0x21, 0 + .dw 0x8740, 0xc83e, 0x877f, 0xc83e, 0x21, 0 + .dw 0x87c0, 0xc83e, 0x87ff, 0xc83e, 0x21, 0 + .dw 0x8840, 0xc83e, 0x887f, 0xc83e, 0x21, 0 + .dw 0x88c0, 0xc83e, 0x88ff, 0xc83e, 0x21, 0 + .dw 0x8940, 0xc83e, 0x897f, 0xc83e, 0x21, 0 + .dw 0x89c0, 0xc83e, 0x89ff, 0xc83e, 0x21, 0 + .dw 0x8a40, 0xc83e, 0x8a7f, 0xc83e, 0x21, 0 + .dw 0x8ac0, 0xc83e, 0x8aff, 0xc83e, 0x21, 0 + .dw 0x8b40, 0xc83e, 0x8b7f, 0xc83e, 0x21, 0 + .dw 0x8bc0, 0xc83e, 0x8bff, 0xc83e, 0x21, 0 + .dw 0x8c40, 0xc83e, 0x8c7f, 0xc83e, 0x21, 0 + .dw 0x8cc0, 0xc83e, 0x8cff, 0xc83e, 0x21, 0 + .dw 0x8d40, 0xc83e, 0x8d7f, 0xc83e, 0x21, 0 + .dw 0x8dc0, 0xc83e, 0x8dff, 0xc83e, 0x21, 0 + .dw 0x8e40, 0xc83e, 0x8e7f, 0xc83e, 0x21, 0 + .dw 0x8ec0, 0xc83e, 0x8eff, 0xc83e, 0x21, 0 + .dw 0x8f40, 0xc83e, 0x8f7f, 0xc83e, 0x21, 0 + .dw 0x8fc0, 0xc83e, 0x8fff, 0xc83e, 0x21, 0 + .dw 0x9040, 0xc83e, 0x907f, 0xc83e, 0x21, 0 + .dw 0x90c0, 0xc83e, 0x90ff, 0xc83e, 0x21, 0 + .dw 0x9140, 0xc83e, 0x917f, 0xc83e, 0x21, 0 + .dw 0x91c0, 0xc83e, 0x91ff, 0xc83e, 0x21, 0 + .dw 0x9240, 0xc83e, 0x927f, 0xc83e, 0x21, 0 + .dw 0x92c0, 0xc83e, 0x92ff, 0xc83e, 0x21, 0 + .dw 0x9340, 0xc83e, 0x937f, 0xc83e, 0x21, 0 + .dw 0x93c0, 0xc83e, 0x93ff, 0xc83e, 0x21, 0 + .dw 0x9440, 0xc83e, 0x947f, 0xc83e, 0x21, 0 + .dw 0x94c0, 0xc83e, 0x94ff, 0xc83e, 0x21, 0 + .dw 0x9540, 0xc83e, 0x957f, 0xc83e, 0x21, 0 + .dw 0x95c0, 0xc83e, 0x95ff, 0xc83e, 0x21, 0 + .dw 0x9640, 0xc83e, 0x967f, 0xc83e, 0x21, 0 + .dw 0x96c0, 0xc83e, 0x96ff, 0xc83e, 0x21, 0 + .dw 0x9740, 0xc83e, 0x977f, 0xc83e, 0x21, 0 + .dw 0x97c0, 0xc83e, 0x97ff, 0xc83e, 0x21, 0 + .dw 0x9840, 0xc83e, 0x987f, 0xc83e, 0x21, 0 + .dw 0x98c0, 0xc83e, 0x98ff, 0xc83e, 0x21, 0 + .dw 0x9940, 0xc83e, 0x997f, 0xc83e, 0x21, 0 + .dw 0x99c0, 0xc83e, 0x9fff, 0xc83e, 0x21, 0 + .dw 0xa040, 0xc83e, 0xa07f, 0xc83e, 0x21, 0 + .dw 0xa0c0, 0xc83e, 0xa0ff, 0xc83e, 0x21, 0 + .dw 0xa140, 0xc83e, 0xa17f, 0xc83e, 0x21, 0 + .dw 0xa1c0, 0xc83e, 0xa1ff, 0xc83e, 0x21, 0 + .dw 0xa240, 0xc83e, 0xa27f, 0xc83e, 0x21, 0 + .dw 0xa2c0, 0xc83e, 0xa2ff, 0xc83e, 0x21, 0 + .dw 0xa340, 0xc83e, 0xa37f, 0xc83e, 0x21, 0 + .dw 0xa3c0, 0xc83e, 0xa3ff, 0xc83e, 0x21, 0 + .dw 0xa440, 0xc83e, 0xa47f, 0xc83e, 0x21, 0 + .dw 0xa4c0, 0xc83e, 0xa4ff, 0xc83e, 0x21, 0 + .dw 0xa540, 0xc83e, 0xa57f, 0xc83e, 0x21, 0 + .dw 0xa5c0, 0xc83e, 0xa5ff, 0xc83e, 0x21, 0 + .dw 0xa640, 0xc83e, 0xa67f, 0xc83e, 0x21, 0 + .dw 0xa6c0, 0xc83e, 0xa6ff, 0xc83e, 0x21, 0 + .dw 0xa740, 0xc83e, 0xa77f, 0xc83e, 0x21, 0 + .dw 0xa7c0, 0xc83e, 0xa7ff, 0xc83e, 0x21, 0 + .dw 0xa840, 0xc83e, 0xa87f, 0xc83e, 0x21, 0 + .dw 0xa8c0, 0xc83e, 0xa8ff, 0xc83e, 0x21, 0 + .dw 0xa940, 0xc83e, 0xa97f, 0xc83e, 0x21, 0 + .dw 0xa9c0, 0xc83e, 0xa9ff, 0xc83e, 0x21, 0 + .dw 0xaa40, 0xc83e, 0xaa7f, 0xc83e, 0x21, 0 + .dw 0xaac0, 0xc83e, 0xaaff, 0xc83e, 0x21, 0 + .dw 0xab40, 0xc83e, 0xab7f, 0xc83e, 0x21, 0 + .dw 0xabc0, 0xc83e, 0xabff, 0xc83e, 0x21, 0 + .dw 0xac40, 0xc83e, 0xac7f, 0xc83e, 0x21, 0 + .dw 0xacc0, 0xc83e, 0xacff, 0xc83e, 0x21, 0 + .dw 0xad40, 0xc83e, 0xad7f, 0xc83e, 0x21, 0 + .dw 0xadc0, 0xc83e, 0xadff, 0xc83e, 0x21, 0 + .dw 0xae40, 0xc83e, 0xae7f, 0xc83e, 0x21, 0 + .dw 0xaec0, 0xc83e, 0xaeff, 0xc83e, 0x21, 0 + .dw 0xaf40, 0xc83e, 0xaf7f, 0xc83e, 0x21, 0 + .dw 0xafc0, 0xc83e, 0xafff, 0xc83e, 0x21, 0 + .dw 0xb040, 0xc83e, 0xb07f, 0xc83e, 0x21, 0 + .dw 0xb0c0, 0xc83e, 0xb0ff, 0xc83e, 0x21, 0 + .dw 0xb140, 0xc83e, 0xb17f, 0xc83e, 0x21, 0 + .dw 0xb1c0, 0xc83e, 0xb1ff, 0xc83e, 0x21, 0 + .dw 0xb240, 0xc83e, 0xb27f, 0xc83e, 0x21, 0 + .dw 0xb2c0, 0xc83e, 0xb2ff, 0xc83e, 0x21, 0 + .dw 0xb340, 0xc83e, 0xb37f, 0xc83e, 0x21, 0 + .dw 0xb3c0, 0xc83e, 0xb3ff, 0xc83e, 0x21, 0 + .dw 0xb440, 0xc83e, 0xb47f, 0xc83e, 0x21, 0 + .dw 0xb4c0, 0xc83e, 0xb4ff, 0xc83e, 0x21, 0 + .dw 0xb540, 0xc83e, 0xb57f, 0xc83e, 0x21, 0 + .dw 0xb5c0, 0xc83e, 0xb5ff, 0xc83e, 0x21, 0 + .dw 0xb640, 0xc83e, 0xb67f, 0xc83e, 0x21, 0 + .dw 0xb6c0, 0xc83e, 0xb6ff, 0xc83e, 0x21, 0 + .dw 0xb740, 0xc83e, 0xb77f, 0xc83e, 0x21, 0 + .dw 0xb7c0, 0xc83e, 0xb7ff, 0xc83e, 0x21, 0 + .dw 0xb840, 0xc83e, 0xb87f, 0xc83e, 0x21, 0 + .dw 0xb8c0, 0xc83e, 0xb8ff, 0xc83e, 0x21, 0 + .dw 0xb940, 0xc83e, 0xb97f, 0xc83e, 0x21, 0 + .dw 0xb9c0, 0xc83e, 0xbfff, 0xc83e, 0x21, 0 + .dw 0xc040, 0xc83e, 0xc07f, 0xc83e, 0x21, 0 + .dw 0xc0c0, 0xc83e, 0xc0ff, 0xc83e, 0x21, 0 + .dw 0xc140, 0xc83e, 0xc17f, 0xc83e, 0x21, 0 + .dw 0xc1c0, 0xc83e, 0xc1ff, 0xc83e, 0x21, 0 + .dw 0xc240, 0xc83e, 0xc27f, 0xc83e, 0x21, 0 + .dw 0xc2c0, 0xc83e, 0xc2ff, 0xc83e, 0x21, 0 + .dw 0xc340, 0xc83e, 0xc37f, 0xc83e, 0x21, 0 + .dw 0xc3c0, 0xc83e, 0xc3ff, 0xc83e, 0x21, 0 + .dw 0xc440, 0xc83e, 0xc47f, 0xc83e, 0x21, 0 + .dw 0xc4c0, 0xc83e, 0xc4ff, 0xc83e, 0x21, 0 + .dw 0xc540, 0xc83e, 0xc57f, 0xc83e, 0x21, 0 + .dw 0xc5c0, 0xc83e, 0xc5ff, 0xc83e, 0x21, 0 + .dw 0xc640, 0xc83e, 0xc67f, 0xc83e, 0x21, 0 + .dw 0xc6c0, 0xc83e, 0xc6ff, 0xc83e, 0x21, 0 + .dw 0xc740, 0xc83e, 0xc77f, 0xc83e, 0x21, 0 + .dw 0xc7c0, 0xc83e, 0xc7ff, 0xc83e, 0x21, 0 + .dw 0xc840, 0xc83e, 0xc87f, 0xc83e, 0x21, 0 + .dw 0xc8c0, 0xc83e, 0xc8ff, 0xc83e, 0x21, 0 + .dw 0xc940, 0xc83e, 0xc97f, 0xc83e, 0x21, 0 + .dw 0xc9c0, 0xc83e, 0xc9ff, 0xc83e, 0x21, 0 + .dw 0xca40, 0xc83e, 0xca7f, 0xc83e, 0x21, 0 + .dw 0xcac0, 0xc83e, 0xcaff, 0xc83e, 0x21, 0 + .dw 0xcb40, 0xc83e, 0xcb7f, 0xc83e, 0x21, 0 + .dw 0xcbc0, 0xc83e, 0xcbff, 0xc83e, 0x21, 0 + .dw 0xcc40, 0xc83e, 0xcc7f, 0xc83e, 0x21, 0 + .dw 0xccc0, 0xc83e, 0xccff, 0xc83e, 0x21, 0 + .dw 0xcd40, 0xc83e, 0xcd7f, 0xc83e, 0x21, 0 + .dw 0xcdc0, 0xc83e, 0xcdff, 0xc83e, 0x21, 0 + .dw 0xce40, 0xc83e, 0xce7f, 0xc83e, 0x21, 0 + .dw 0xcec0, 0xc83e, 0xceff, 0xc83e, 0x21, 0 + .dw 0xcf40, 0xc83e, 0xcf7f, 0xc83e, 0x21, 0 + .dw 0xcfc0, 0xc83e, 0xcfff, 0xc83e, 0x21, 0 + .dw 0xd040, 0xc83e, 0xd07f, 0xc83e, 0x21, 0 + .dw 0xd0c0, 0xc83e, 0xd0ff, 0xc83e, 0x21, 0 + .dw 0xd140, 0xc83e, 0xd17f, 0xc83e, 0x21, 0 + .dw 0xd1c0, 0xc83e, 0xd1ff, 0xc83e, 0x21, 0 + .dw 0xd240, 0xc83e, 0xd27f, 0xc83e, 0x21, 0 + .dw 0xd2c0, 0xc83e, 0xd2ff, 0xc83e, 0x21, 0 + .dw 0xd340, 0xc83e, 0xd37f, 0xc83e, 0x21, 0 + .dw 0xd3c0, 0xc83e, 0xd3ff, 0xc83e, 0x21, 0 + .dw 0xd440, 0xc83e, 0xd47f, 0xc83e, 0x21, 0 + .dw 0xd4c0, 0xc83e, 0xd4ff, 0xc83e, 0x21, 0 + .dw 0xd540, 0xc83e, 0xd57f, 0xc83e, 0x21, 0 + .dw 0xd5c0, 0xc83e, 0xd5ff, 0xc83e, 0x21, 0 + .dw 0xd640, 0xc83e, 0xd67f, 0xc83e, 0x21, 0 + .dw 0xd6c0, 0xc83e, 0xd6ff, 0xc83e, 0x21, 0 + .dw 0xd740, 0xc83e, 0xd77f, 0xc83e, 0x21, 0 + .dw 0xd7c0, 0xc83e, 0xd7ff, 0xc83e, 0x21, 0 + .dw 0xd840, 0xc83e, 0xd87f, 0xc83e, 0x21, 0 + .dw 0xd8c0, 0xc83e, 0xd8ff, 0xc83e, 0x21, 0 + .dw 0xd940, 0xc83e, 0xd97f, 0xc83e, 0x21, 0 + .dw 0xd9c0, 0xc83e, 0xdfff, 0xc83e, 0x21, 0 + .dw 0xe040, 0xc83e, 0xe07f, 0xc83e, 0x21, 0 + .dw 0xe0c0, 0xc83e, 0xe0ff, 0xc83e, 0x21, 0 + .dw 0xe140, 0xc83e, 0xe17f, 0xc83e, 0x21, 0 + .dw 0xe1c0, 0xc83e, 0xe1ff, 0xc83e, 0x21, 0 + .dw 0xe240, 0xc83e, 0xe27f, 0xc83e, 0x21, 0 + .dw 0xe2c0, 0xc83e, 0xe2ff, 0xc83e, 0x21, 0 + .dw 0xe340, 0xc83e, 0xe37f, 0xc83e, 0x21, 0 + .dw 0xe3c0, 0xc83e, 0xe3ff, 0xc83e, 0x21, 0 + .dw 0xe440, 0xc83e, 0xe47f, 0xc83e, 0x21, 0 + .dw 0xe4c0, 0xc83e, 0xe4ff, 0xc83e, 0x21, 0 + .dw 0xe540, 0xc83e, 0xe57f, 0xc83e, 0x21, 0 + .dw 0xe5c0, 0xc83e, 0xe5ff, 0xc83e, 0x21, 0 + .dw 0xe640, 0xc83e, 0xe67f, 0xc83e, 0x21, 0 + .dw 0xe6c0, 0xc83e, 0xe6ff, 0xc83e, 0x21, 0 + .dw 0xe740, 0xc83e, 0xe77f, 0xc83e, 0x21, 0 + .dw 0xe7c0, 0xc83e, 0xe7ff, 0xc83e, 0x21, 0 + .dw 0xe840, 0xc83e, 0xe87f, 0xc83e, 0x21, 0 + .dw 0xe8c0, 0xc83e, 0xe8ff, 0xc83e, 0x21, 0 + .dw 0xe940, 0xc83e, 0xe97f, 0xc83e, 0x21, 0 + .dw 0xe9c0, 0xc83e, 0xe9ff, 0xc83e, 0x21, 0 + .dw 0xea40, 0xc83e, 0xea7f, 0xc83e, 0x21, 0 + .dw 0xeac0, 0xc83e, 0xeaff, 0xc83e, 0x21, 0 + .dw 0xeb40, 0xc83e, 0xeb7f, 0xc83e, 0x21, 0 + .dw 0xebc0, 0xc83e, 0xebff, 0xc83e, 0x21, 0 + .dw 0xec40, 0xc83e, 0xec7f, 0xc83e, 0x21, 0 + .dw 0xecc0, 0xc83e, 0xecff, 0xc83e, 0x21, 0 + .dw 0xed40, 0xc83e, 0xed7f, 0xc83e, 0x21, 0 + .dw 0xedc0, 0xc83e, 0xedff, 0xc83e, 0x21, 0 + .dw 0xee40, 0xc83e, 0xee7f, 0xc83e, 0x21, 0 + .dw 0xeec0, 0xc83e, 0xeeff, 0xc83e, 0x21, 0 + .dw 0xef40, 0xc83e, 0xef7f, 0xc83e, 0x21, 0 + .dw 0xefc0, 0xc83e, 0xefff, 0xc83e, 0x21, 0 + .dw 0xf040, 0xc83e, 0xf07f, 0xc83e, 0x21, 0 + .dw 0xf0c0, 0xc83e, 0xf0ff, 0xc83e, 0x21, 0 + .dw 0xf140, 0xc83e, 0xf17f, 0xc83e, 0x21, 0 + .dw 0xf1c0, 0xc83e, 0xf1ff, 0xc83e, 0x21, 0 + .dw 0xf240, 0xc83e, 0xf27f, 0xc83e, 0x21, 0 + .dw 0xf2c0, 0xc83e, 0xf2ff, 0xc83e, 0x21, 0 + .dw 0xf340, 0xc83e, 0xf37f, 0xc83e, 0x21, 0 + .dw 0xf3c0, 0xc83e, 0xf3ff, 0xc83e, 0x21, 0 + .dw 0xf440, 0xc83e, 0xf47f, 0xc83e, 0x21, 0 + .dw 0xf4c0, 0xc83e, 0xf4ff, 0xc83e, 0x21, 0 + .dw 0xf540, 0xc83e, 0xf57f, 0xc83e, 0x21, 0 + .dw 0xf5c0, 0xc83e, 0xf5ff, 0xc83e, 0x21, 0 + .dw 0xf640, 0xc83e, 0xf67f, 0xc83e, 0x21, 0 + .dw 0xf6c0, 0xc83e, 0xf6ff, 0xc83e, 0x21, 0 + .dw 0xf740, 0xc83e, 0xf77f, 0xc83e, 0x21, 0 + .dw 0xf7c0, 0xc83e, 0xf7ff, 0xc83e, 0x21, 0 + .dw 0xf840, 0xc83e, 0xf87f, 0xc83e, 0x21, 0 + .dw 0xf8c0, 0xc83e, 0xf8ff, 0xc83e, 0x21, 0 + .dw 0xf940, 0xc83e, 0xf97f, 0xc83e, 0x21, 0 + .dw 0xf9c0, 0xc83e, 0xffff, 0xc83e, 0x21, 0 + .dw 0x0040, 0xc83f, 0x007f, 0xc83f, 0x21, 0 + .dw 0x00c0, 0xc83f, 0x00ff, 0xc83f, 0x21, 0 + .dw 0x0140, 0xc83f, 0x017f, 0xc83f, 0x21, 0 + .dw 0x01c0, 0xc83f, 0x01ff, 0xc83f, 0x21, 0 + .dw 0x0240, 0xc83f, 0x027f, 0xc83f, 0x21, 0 + .dw 0x02c0, 0xc83f, 0x02ff, 0xc83f, 0x21, 0 + .dw 0x0340, 0xc83f, 0x037f, 0xc83f, 0x21, 0 + .dw 0x03c0, 0xc83f, 0x03ff, 0xc83f, 0x21, 0 + .dw 0x0440, 0xc83f, 0x047f, 0xc83f, 0x21, 0 + .dw 0x04c0, 0xc83f, 0x04ff, 0xc83f, 0x21, 0 + .dw 0x0540, 0xc83f, 0x057f, 0xc83f, 0x21, 0 + .dw 0x05c0, 0xc83f, 0x05ff, 0xc83f, 0x21, 0 + .dw 0x0640, 0xc83f, 0x067f, 0xc83f, 0x21, 0 + .dw 0x06c0, 0xc83f, 0x06ff, 0xc83f, 0x21, 0 + .dw 0x0740, 0xc83f, 0x077f, 0xc83f, 0x21, 0 + .dw 0x07c0, 0xc83f, 0x07ff, 0xc83f, 0x21, 0 + .dw 0x0840, 0xc83f, 0x087f, 0xc83f, 0x21, 0 + .dw 0x08c0, 0xc83f, 0x08ff, 0xc83f, 0x21, 0 + .dw 0x0940, 0xc83f, 0x097f, 0xc83f, 0x21, 0 + .dw 0x09c0, 0xc83f, 0x09ff, 0xc83f, 0x21, 0 + .dw 0x0a40, 0xc83f, 0x0a7f, 0xc83f, 0x21, 0 + .dw 0x0ac0, 0xc83f, 0x0aff, 0xc83f, 0x21, 0 + .dw 0x0b40, 0xc83f, 0x0b7f, 0xc83f, 0x21, 0 + .dw 0x0bc0, 0xc83f, 0x0bff, 0xc83f, 0x21, 0 + .dw 0x0c40, 0xc83f, 0x0c7f, 0xc83f, 0x21, 0 + .dw 0x0cc0, 0xc83f, 0x0cff, 0xc83f, 0x21, 0 + .dw 0x0d40, 0xc83f, 0x0d7f, 0xc83f, 0x21, 0 + .dw 0x0dc0, 0xc83f, 0x0dff, 0xc83f, 0x21, 0 + .dw 0x0e40, 0xc83f, 0x0e7f, 0xc83f, 0x21, 0 + .dw 0x0ec0, 0xc83f, 0x0eff, 0xc83f, 0x21, 0 + .dw 0x0f40, 0xc83f, 0x0f7f, 0xc83f, 0x21, 0 + .dw 0x0fc0, 0xc83f, 0x0fff, 0xc83f, 0x21, 0 + .dw 0x1040, 0xc83f, 0x107f, 0xc83f, 0x21, 0 + .dw 0x10c0, 0xc83f, 0x10ff, 0xc83f, 0x21, 0 + .dw 0x1140, 0xc83f, 0x117f, 0xc83f, 0x21, 0 + .dw 0x11c0, 0xc83f, 0x11ff, 0xc83f, 0x21, 0 + .dw 0x1240, 0xc83f, 0x127f, 0xc83f, 0x21, 0 + .dw 0x12c0, 0xc83f, 0x12ff, 0xc83f, 0x21, 0 + .dw 0x1340, 0xc83f, 0x137f, 0xc83f, 0x21, 0 + .dw 0x13c0, 0xc83f, 0x13ff, 0xc83f, 0x21, 0 + .dw 0x1440, 0xc83f, 0x147f, 0xc83f, 0x21, 0 + .dw 0x14c0, 0xc83f, 0x14ff, 0xc83f, 0x21, 0 + .dw 0x1540, 0xc83f, 0x157f, 0xc83f, 0x21, 0 + .dw 0x15c0, 0xc83f, 0x15ff, 0xc83f, 0x21, 0 + .dw 0x1640, 0xc83f, 0x167f, 0xc83f, 0x21, 0 + .dw 0x16c0, 0xc83f, 0x16ff, 0xc83f, 0x21, 0 + .dw 0x1740, 0xc83f, 0x177f, 0xc83f, 0x21, 0 + .dw 0x17c0, 0xc83f, 0x17ff, 0xc83f, 0x21, 0 + .dw 0x1840, 0xc83f, 0x187f, 0xc83f, 0x21, 0 + .dw 0x18c0, 0xc83f, 0x18ff, 0xc83f, 0x21, 0 + .dw 0x1940, 0xc83f, 0x197f, 0xc83f, 0x21, 0 + .dw 0x19c0, 0xc83f, 0x1fff, 0xc83f, 0x21, 0 + .dw 0x2040, 0xc83f, 0x207f, 0xc83f, 0x21, 0 + .dw 0x20c0, 0xc83f, 0x20ff, 0xc83f, 0x21, 0 + .dw 0x2140, 0xc83f, 0x217f, 0xc83f, 0x21, 0 + .dw 0x21c0, 0xc83f, 0x21ff, 0xc83f, 0x21, 0 + .dw 0x2240, 0xc83f, 0x227f, 0xc83f, 0x21, 0 + .dw 0x22c0, 0xc83f, 0x22ff, 0xc83f, 0x21, 0 + .dw 0x2340, 0xc83f, 0x237f, 0xc83f, 0x21, 0 + .dw 0x23c0, 0xc83f, 0x23ff, 0xc83f, 0x21, 0 + .dw 0x2440, 0xc83f, 0x247f, 0xc83f, 0x21, 0 + .dw 0x24c0, 0xc83f, 0x24ff, 0xc83f, 0x21, 0 + .dw 0x2540, 0xc83f, 0x257f, 0xc83f, 0x21, 0 + .dw 0x25c0, 0xc83f, 0x25ff, 0xc83f, 0x21, 0 + .dw 0x2640, 0xc83f, 0x267f, 0xc83f, 0x21, 0 + .dw 0x26c0, 0xc83f, 0x26ff, 0xc83f, 0x21, 0 + .dw 0x2740, 0xc83f, 0x277f, 0xc83f, 0x21, 0 + .dw 0x27c0, 0xc83f, 0x27ff, 0xc83f, 0x21, 0 + .dw 0x2840, 0xc83f, 0x287f, 0xc83f, 0x21, 0 + .dw 0x28c0, 0xc83f, 0x28ff, 0xc83f, 0x21, 0 + .dw 0x2940, 0xc83f, 0x297f, 0xc83f, 0x21, 0 + .dw 0x29c0, 0xc83f, 0x29ff, 0xc83f, 0x21, 0 + .dw 0x2a40, 0xc83f, 0x2a7f, 0xc83f, 0x21, 0 + .dw 0x2ac0, 0xc83f, 0x2aff, 0xc83f, 0x21, 0 + .dw 0x2b40, 0xc83f, 0x2b7f, 0xc83f, 0x21, 0 + .dw 0x2bc0, 0xc83f, 0x2bff, 0xc83f, 0x21, 0 + .dw 0x2c40, 0xc83f, 0x2c7f, 0xc83f, 0x21, 0 + .dw 0x2cc0, 0xc83f, 0x2cff, 0xc83f, 0x21, 0 + .dw 0x2d40, 0xc83f, 0x2d7f, 0xc83f, 0x21, 0 + .dw 0x2dc0, 0xc83f, 0x2dff, 0xc83f, 0x21, 0 + .dw 0x2e40, 0xc83f, 0x2e7f, 0xc83f, 0x21, 0 + .dw 0x2ec0, 0xc83f, 0x2eff, 0xc83f, 0x21, 0 + .dw 0x2f40, 0xc83f, 0x2f7f, 0xc83f, 0x21, 0 + .dw 0x2fc0, 0xc83f, 0x2fff, 0xc83f, 0x21, 0 + .dw 0x3040, 0xc83f, 0x307f, 0xc83f, 0x21, 0 + .dw 0x30c0, 0xc83f, 0x30ff, 0xc83f, 0x21, 0 + .dw 0x3140, 0xc83f, 0x317f, 0xc83f, 0x21, 0 + .dw 0x31c0, 0xc83f, 0x31ff, 0xc83f, 0x21, 0 + .dw 0x3240, 0xc83f, 0x327f, 0xc83f, 0x21, 0 + .dw 0x32c0, 0xc83f, 0x32ff, 0xc83f, 0x21, 0 + .dw 0x3340, 0xc83f, 0x337f, 0xc83f, 0x21, 0 + .dw 0x33c0, 0xc83f, 0x33ff, 0xc83f, 0x21, 0 + .dw 0x3440, 0xc83f, 0x347f, 0xc83f, 0x21, 0 + .dw 0x34c0, 0xc83f, 0x34ff, 0xc83f, 0x21, 0 + .dw 0x3540, 0xc83f, 0x357f, 0xc83f, 0x21, 0 + .dw 0x35c0, 0xc83f, 0x35ff, 0xc83f, 0x21, 0 + .dw 0x3640, 0xc83f, 0x367f, 0xc83f, 0x21, 0 + .dw 0x36c0, 0xc83f, 0x36ff, 0xc83f, 0x21, 0 + .dw 0x3740, 0xc83f, 0x377f, 0xc83f, 0x21, 0 + .dw 0x37c0, 0xc83f, 0x37ff, 0xc83f, 0x21, 0 + .dw 0x3840, 0xc83f, 0x387f, 0xc83f, 0x21, 0 + .dw 0x38c0, 0xc83f, 0x38ff, 0xc83f, 0x21, 0 + .dw 0x3940, 0xc83f, 0x397f, 0xc83f, 0x21, 0 + .dw 0x39c0, 0xc83f, 0x1fff, 0xc840, 0x21, 0 + .dw 0x3a00, 0xc840, 0x5fff, 0xc840, 0x21, 0 + .dw 0x7a00, 0xc840, 0x9fff, 0xc840, 0x21, 0 + .dw 0xba00, 0xc840, 0xdfff, 0xc840, 0x21, 0 + .dw 0xfa00, 0xc840, 0x1fff, 0xc841, 0x21, 0 + .dw 0x3a00, 0xc841, 0x5fff, 0xc841, 0x21, 0 + .dw 0x7a00, 0xc841, 0x9fff, 0xc841, 0x21, 0 + .dw 0xba00, 0xc841, 0xdfff, 0xc841, 0x21, 0 + .dw 0xfa00, 0xc841, 0x1fff, 0xc842, 0x21, 0 + .dw 0x3a00, 0xc842, 0x5fff, 0xc842, 0x21, 0 + .dw 0x7a00, 0xc842, 0x9fff, 0xc842, 0x21, 0 + .dw 0xba00, 0xc842, 0xdfff, 0xc842, 0x21, 0 + .dw 0xfa00, 0xc842, 0x1fff, 0xc843, 0x21, 0 + .dw 0x3a00, 0xc843, 0xffff, 0xc843, 0x21, 0 + .dw 0x1a00, 0xc844, 0x1fff, 0xc844, 0x21, 0 + .dw 0x3a00, 0xc844, 0x3fff, 0xc844, 0x21, 0 + .dw 0x5a00, 0xc844, 0x5fff, 0xc844, 0x21, 0 + .dw 0x7a00, 0xc844, 0x7fff, 0xc844, 0x21, 0 + .dw 0x9a00, 0xc844, 0x9fff, 0xc844, 0x21, 0 + .dw 0xba00, 0xc844, 0xbfff, 0xc844, 0x21, 0 + .dw 0xda00, 0xc844, 0xdfff, 0xc844, 0x21, 0 + .dw 0xfa00, 0xc844, 0xffff, 0xc844, 0x21, 0 + .dw 0x1a00, 0xc845, 0x1fff, 0xc845, 0x21, 0 + .dw 0x3a00, 0xc845, 0x3fff, 0xc845, 0x21, 0 + .dw 0x5a00, 0xc845, 0x5fff, 0xc845, 0x21, 0 + .dw 0x7a00, 0xc845, 0x7fff, 0xc845, 0x21, 0 + .dw 0x9a00, 0xc845, 0x9fff, 0xc845, 0x21, 0 + .dw 0xba00, 0xc845, 0xbfff, 0xc845, 0x21, 0 + .dw 0xda00, 0xc845, 0xdfff, 0xc845, 0x21, 0 + .dw 0xfa00, 0xc845, 0xffff, 0xc845, 0x21, 0 + .dw 0x1a00, 0xc846, 0x1fff, 0xc846, 0x21, 0 + .dw 0x3a00, 0xc846, 0x3fff, 0xc846, 0x21, 0 + .dw 0x5a00, 0xc846, 0x5fff, 0xc846, 0x21, 0 + .dw 0x7a00, 0xc846, 0x7fff, 0xc846, 0x21, 0 + .dw 0x9a00, 0xc846, 0x9fff, 0xc846, 0x21, 0 + .dw 0xba00, 0xc846, 0xbfff, 0xc846, 0x21, 0 + .dw 0xda00, 0xc846, 0xdfff, 0xc846, 0x21, 0 + .dw 0xfa00, 0xc846, 0xffff, 0xc846, 0x21, 0 + .dw 0x1a00, 0xc847, 0x1fff, 0xc847, 0x21, 0 + .dw 0x3a00, 0xc847, 0x1fff, 0xc850, 0x21, 0 + .dw 0x3a00, 0xc850, 0x5fff, 0xc850, 0x21, 0 + .dw 0x7a00, 0xc850, 0x9fff, 0xc850, 0x21, 0 + .dw 0xba00, 0xc850, 0xdfff, 0xc850, 0x21, 0 + .dw 0xfa00, 0xc850, 0x1fff, 0xc851, 0x21, 0 + .dw 0x3a00, 0xc851, 0x5fff, 0xc851, 0x21, 0 + .dw 0x7a00, 0xc851, 0x9fff, 0xc851, 0x21, 0 + .dw 0xba00, 0xc851, 0xdfff, 0xc851, 0x21, 0 + .dw 0xfa00, 0xc851, 0x1fff, 0xc852, 0x21, 0 + .dw 0x3a00, 0xc852, 0x5fff, 0xc852, 0x21, 0 + .dw 0x7a00, 0xc852, 0x9fff, 0xc852, 0x21, 0 + .dw 0xba00, 0xc852, 0xdfff, 0xc852, 0x21, 0 + .dw 0xfa00, 0xc852, 0xffff, 0xc853, 0x21, 0 + .dw 0x1a00, 0xc854, 0x1fff, 0xc854, 0x21, 0 + .dw 0x3a00, 0xc854, 0x3fff, 0xc854, 0x21, 0 + .dw 0x5a00, 0xc854, 0x5fff, 0xc854, 0x21, 0 + .dw 0x7a00, 0xc854, 0x7fff, 0xc854, 0x21, 0 + .dw 0x9a00, 0xc854, 0x9fff, 0xc854, 0x21, 0 + .dw 0xba00, 0xc854, 0xbfff, 0xc854, 0x21, 0 + .dw 0xda00, 0xc854, 0xdfff, 0xc854, 0x21, 0 + .dw 0xfa00, 0xc854, 0xffff, 0xc854, 0x21, 0 + .dw 0x1a00, 0xc855, 0x1fff, 0xc855, 0x21, 0 + .dw 0x3a00, 0xc855, 0x3fff, 0xc855, 0x21, 0 + .dw 0x5a00, 0xc855, 0x5fff, 0xc855, 0x21, 0 + .dw 0x7a00, 0xc855, 0x7fff, 0xc855, 0x21, 0 + .dw 0x9a00, 0xc855, 0x9fff, 0xc855, 0x21, 0 + .dw 0xba00, 0xc855, 0xbfff, 0xc855, 0x21, 0 + .dw 0xda00, 0xc855, 0xdfff, 0xc855, 0x21, 0 + .dw 0xfa00, 0xc855, 0xffff, 0xc855, 0x21, 0 + .dw 0x1a00, 0xc856, 0x1fff, 0xc856, 0x21, 0 + .dw 0x3a00, 0xc856, 0x3fff, 0xc856, 0x21, 0 + .dw 0x5a00, 0xc856, 0x5fff, 0xc856, 0x21, 0 + .dw 0x7a00, 0xc856, 0x7fff, 0xc856, 0x21, 0 + .dw 0x9a00, 0xc856, 0x9fff, 0xc856, 0x21, 0 + .dw 0xba00, 0xc856, 0xbfff, 0xc856, 0x21, 0 + .dw 0xda00, 0xc856, 0xdfff, 0xc856, 0x21, 0 + .dw 0xfa00, 0xc856, 0xffff, 0xc856, 0x21, 0 + .dw 0x1a00, 0xc857, 0x1fff, 0xc857, 0x21, 0 + .dw 0x3a00, 0xc857, 0xffff, 0xc85f, 0x21, 0 + .dw 0x1a00, 0xc860, 0x3fff, 0xc860, 0x21, 0 + .dw 0x5a00, 0xc860, 0x7fff, 0xc860, 0x21, 0 + .dw 0x9a00, 0xc860, 0xbfff, 0xc860, 0x21, 0 + .dw 0xda00, 0xc860, 0xffff, 0xc860, 0x21, 0 + .dw 0x1a00, 0xc861, 0x3fff, 0xc861, 0x21, 0 + .dw 0x5a00, 0xc861, 0x7fff, 0xc861, 0x21, 0 + .dw 0x9a00, 0xc861, 0xbfff, 0xc861, 0x21, 0 + .dw 0xda00, 0xc861, 0xffff, 0xc861, 0x21, 0 + .dw 0x1a00, 0xc862, 0x3fff, 0xc862, 0x21, 0 + .dw 0x5a00, 0xc862, 0x7fff, 0xc862, 0x21, 0 + .dw 0x9a00, 0xc862, 0xbfff, 0xc862, 0x21, 0 + .dw 0xda00, 0xc862, 0xffff, 0xc862, 0x21, 0 + .dw 0x1a00, 0xc863, 0xffff, 0xc86f, 0x21, 0 + .dw 0x1a00, 0xc870, 0x3fff, 0xc870, 0x21, 0 + .dw 0x5a00, 0xc870, 0x7fff, 0xc870, 0x21, 0 + .dw 0x9a00, 0xc870, 0xbfff, 0xc870, 0x21, 0 + .dw 0xda00, 0xc870, 0xffff, 0xc870, 0x21, 0 + .dw 0x1a00, 0xc871, 0x3fff, 0xc871, 0x21, 0 + .dw 0x5a00, 0xc871, 0x7fff, 0xc871, 0x21, 0 + .dw 0x9a00, 0xc871, 0xbfff, 0xc871, 0x21, 0 + .dw 0xda00, 0xc871, 0xffff, 0xc871, 0x21, 0 + .dw 0x1a00, 0xc872, 0x3fff, 0xc872, 0x21, 0 + .dw 0x5a00, 0xc872, 0x7fff, 0xc872, 0x21, 0 + .dw 0x9a00, 0xc872, 0xbfff, 0xc872, 0x21, 0 + .dw 0xda00, 0xc872, 0xffff, 0xc87f, 0x21, 0 + .dw 0x1a00, 0xc880, 0x1fff, 0xc880, 0x21, 0 + .dw 0x3a00, 0xc880, 0x3fff, 0xc880, 0x21, 0 + .dw 0x5a00, 0xc880, 0x5fff, 0xc880, 0x21, 0 + .dw 0x7a00, 0xc880, 0x7fff, 0xc880, 0x21, 0 + .dw 0x9a00, 0xc880, 0x9fff, 0xc880, 0x21, 0 + .dw 0xba00, 0xc880, 0xbfff, 0xc880, 0x21, 0 + .dw 0xda00, 0xc880, 0xdfff, 0xc880, 0x21, 0 + .dw 0xfa00, 0xc880, 0xffff, 0xc880, 0x21, 0 + .dw 0x1a00, 0xc881, 0x1fff, 0xc881, 0x21, 0 + .dw 0x3a00, 0xc881, 0x3fff, 0xc881, 0x21, 0 + .dw 0x5a00, 0xc881, 0x5fff, 0xc881, 0x21, 0 + .dw 0x7a00, 0xc881, 0x7fff, 0xc881, 0x21, 0 + .dw 0x9a00, 0xc881, 0x9fff, 0xc881, 0x21, 0 + .dw 0xba00, 0xc881, 0xbfff, 0xc881, 0x21, 0 + .dw 0xda00, 0xc881, 0xdfff, 0xc881, 0x21, 0 + .dw 0xfa00, 0xc881, 0xffff, 0xc881, 0x21, 0 + .dw 0x1a00, 0xc882, 0x1fff, 0xc882, 0x21, 0 + .dw 0x3a00, 0xc882, 0x3fff, 0xc882, 0x21, 0 + .dw 0x5a00, 0xc882, 0x5fff, 0xc882, 0x21, 0 + .dw 0x7a00, 0xc882, 0x7fff, 0xc882, 0x21, 0 + .dw 0x9a00, 0xc882, 0x9fff, 0xc882, 0x21, 0 + .dw 0xba00, 0xc882, 0xbfff, 0xc882, 0x21, 0 + .dw 0xda00, 0xc882, 0xdfff, 0xc882, 0x21, 0 + .dw 0xfa00, 0xc882, 0xffff, 0xc882, 0x21, 0 + .dw 0x1a00, 0xc883, 0x1fff, 0xc883, 0x21, 0 + .dw 0x3a00, 0xc883, 0xffff, 0xc883, 0x21, 0 + .dw 0x1a00, 0xc884, 0x1fff, 0xc884, 0x21, 0 + .dw 0x3a00, 0xc884, 0x3fff, 0xc884, 0x21, 0 + .dw 0x5a00, 0xc884, 0x5fff, 0xc884, 0x21, 0 + .dw 0x7a00, 0xc884, 0x7fff, 0xc884, 0x21, 0 + .dw 0x9a00, 0xc884, 0x9fff, 0xc884, 0x21, 0 + .dw 0xba00, 0xc884, 0xbfff, 0xc884, 0x21, 0 + .dw 0xda00, 0xc884, 0xdfff, 0xc884, 0x21, 0 + .dw 0xfa00, 0xc884, 0xffff, 0xc884, 0x21, 0 + .dw 0x1a00, 0xc885, 0x1fff, 0xc885, 0x21, 0 + .dw 0x3a00, 0xc885, 0x3fff, 0xc885, 0x21, 0 + .dw 0x5a00, 0xc885, 0x5fff, 0xc885, 0x21, 0 + .dw 0x7a00, 0xc885, 0x7fff, 0xc885, 0x21, 0 + .dw 0x9a00, 0xc885, 0x9fff, 0xc885, 0x21, 0 + .dw 0xba00, 0xc885, 0xbfff, 0xc885, 0x21, 0 + .dw 0xda00, 0xc885, 0xdfff, 0xc885, 0x21, 0 + .dw 0xfa00, 0xc885, 0xffff, 0xc885, 0x21, 0 + .dw 0x1a00, 0xc886, 0x1fff, 0xc886, 0x21, 0 + .dw 0x3a00, 0xc886, 0x3fff, 0xc886, 0x21, 0 + .dw 0x5a00, 0xc886, 0x5fff, 0xc886, 0x21, 0 + .dw 0x7a00, 0xc886, 0x7fff, 0xc886, 0x21, 0 + .dw 0x9a00, 0xc886, 0x9fff, 0xc886, 0x21, 0 + .dw 0xba00, 0xc886, 0xbfff, 0xc886, 0x21, 0 + .dw 0xda00, 0xc886, 0xdfff, 0xc886, 0x21, 0 + .dw 0xfa00, 0xc886, 0xffff, 0xc886, 0x21, 0 + .dw 0x1a00, 0xc887, 0x1fff, 0xc887, 0x21, 0 + .dw 0x3a00, 0xc887, 0x1fff, 0xc888, 0x21, 0 + .dw 0x2040, 0xc888, 0x207f, 0xc888, 0x21, 0 + .dw 0x20c0, 0xc888, 0x20ff, 0xc888, 0x21, 0 + .dw 0x2140, 0xc888, 0x217f, 0xc888, 0x21, 0 + .dw 0x21c0, 0xc888, 0x21ff, 0xc888, 0x21, 0 + .dw 0x2240, 0xc888, 0x227f, 0xc888, 0x21, 0 + .dw 0x22c0, 0xc888, 0x22ff, 0xc888, 0x21, 0 + .dw 0x2340, 0xc888, 0x237f, 0xc888, 0x21, 0 + .dw 0x23c0, 0xc888, 0x23ff, 0xc888, 0x21, 0 + .dw 0x2440, 0xc888, 0x247f, 0xc888, 0x21, 0 + .dw 0x24c0, 0xc888, 0x24ff, 0xc888, 0x21, 0 + .dw 0x2540, 0xc888, 0x257f, 0xc888, 0x21, 0 + .dw 0x25c0, 0xc888, 0x25ff, 0xc888, 0x21, 0 + .dw 0x2640, 0xc888, 0x267f, 0xc888, 0x21, 0 + .dw 0x26c0, 0xc888, 0x26ff, 0xc888, 0x21, 0 + .dw 0x2740, 0xc888, 0x277f, 0xc888, 0x21, 0 + .dw 0x27c0, 0xc888, 0x27ff, 0xc888, 0x21, 0 + .dw 0x2840, 0xc888, 0x287f, 0xc888, 0x21, 0 + .dw 0x28c0, 0xc888, 0x28ff, 0xc888, 0x21, 0 + .dw 0x2940, 0xc888, 0x297f, 0xc888, 0x21, 0 + .dw 0x29c0, 0xc888, 0x29ff, 0xc888, 0x21, 0 + .dw 0x2a40, 0xc888, 0x2a7f, 0xc888, 0x21, 0 + .dw 0x2ac0, 0xc888, 0x2aff, 0xc888, 0x21, 0 + .dw 0x2b40, 0xc888, 0x2b7f, 0xc888, 0x21, 0 + .dw 0x2bc0, 0xc888, 0x2bff, 0xc888, 0x21, 0 + .dw 0x2c40, 0xc888, 0x2c7f, 0xc888, 0x21, 0 + .dw 0x2cc0, 0xc888, 0x2cff, 0xc888, 0x21, 0 + .dw 0x2d40, 0xc888, 0x2d7f, 0xc888, 0x21, 0 + .dw 0x2dc0, 0xc888, 0x2dff, 0xc888, 0x21, 0 + .dw 0x2e40, 0xc888, 0x2e7f, 0xc888, 0x21, 0 + .dw 0x2ec0, 0xc888, 0x2eff, 0xc888, 0x21, 0 + .dw 0x2f40, 0xc888, 0x2f7f, 0xc888, 0x21, 0 + .dw 0x2fc0, 0xc888, 0x2fff, 0xc888, 0x21, 0 + .dw 0x3040, 0xc888, 0x307f, 0xc888, 0x21, 0 + .dw 0x30c0, 0xc888, 0x30ff, 0xc888, 0x21, 0 + .dw 0x3140, 0xc888, 0x317f, 0xc888, 0x21, 0 + .dw 0x31c0, 0xc888, 0x31ff, 0xc888, 0x21, 0 + .dw 0x3240, 0xc888, 0x327f, 0xc888, 0x21, 0 + .dw 0x32c0, 0xc888, 0x32ff, 0xc888, 0x21, 0 + .dw 0x3340, 0xc888, 0x337f, 0xc888, 0x21, 0 + .dw 0x33c0, 0xc888, 0x33ff, 0xc888, 0x21, 0 + .dw 0x3440, 0xc888, 0x347f, 0xc888, 0x21, 0 + .dw 0x34c0, 0xc888, 0x34ff, 0xc888, 0x21, 0 + .dw 0x3540, 0xc888, 0x357f, 0xc888, 0x21, 0 + .dw 0x35c0, 0xc888, 0x35ff, 0xc888, 0x21, 0 + .dw 0x3640, 0xc888, 0x367f, 0xc888, 0x21, 0 + .dw 0x36c0, 0xc888, 0x36ff, 0xc888, 0x21, 0 + .dw 0x3740, 0xc888, 0x377f, 0xc888, 0x21, 0 + .dw 0x37c0, 0xc888, 0x37ff, 0xc888, 0x21, 0 + .dw 0x3840, 0xc888, 0x387f, 0xc888, 0x21, 0 + .dw 0x38c0, 0xc888, 0x38ff, 0xc888, 0x21, 0 + .dw 0x3940, 0xc888, 0x397f, 0xc888, 0x21, 0 + .dw 0x39c0, 0xc888, 0x5fff, 0xc888, 0x21, 0 + .dw 0x6040, 0xc888, 0x607f, 0xc888, 0x21, 0 + .dw 0x60c0, 0xc888, 0x60ff, 0xc888, 0x21, 0 + .dw 0x6140, 0xc888, 0x617f, 0xc888, 0x21, 0 + .dw 0x61c0, 0xc888, 0x61ff, 0xc888, 0x21, 0 + .dw 0x6240, 0xc888, 0x627f, 0xc888, 0x21, 0 + .dw 0x62c0, 0xc888, 0x62ff, 0xc888, 0x21, 0 + .dw 0x6340, 0xc888, 0x637f, 0xc888, 0x21, 0 + .dw 0x63c0, 0xc888, 0x63ff, 0xc888, 0x21, 0 + .dw 0x6440, 0xc888, 0x647f, 0xc888, 0x21, 0 + .dw 0x64c0, 0xc888, 0x64ff, 0xc888, 0x21, 0 + .dw 0x6540, 0xc888, 0x657f, 0xc888, 0x21, 0 + .dw 0x65c0, 0xc888, 0x65ff, 0xc888, 0x21, 0 + .dw 0x6640, 0xc888, 0x667f, 0xc888, 0x21, 0 + .dw 0x66c0, 0xc888, 0x66ff, 0xc888, 0x21, 0 + .dw 0x6740, 0xc888, 0x677f, 0xc888, 0x21, 0 + .dw 0x67c0, 0xc888, 0x67ff, 0xc888, 0x21, 0 + .dw 0x6840, 0xc888, 0x687f, 0xc888, 0x21, 0 + .dw 0x68c0, 0xc888, 0x68ff, 0xc888, 0x21, 0 + .dw 0x6940, 0xc888, 0x697f, 0xc888, 0x21, 0 + .dw 0x69c0, 0xc888, 0x69ff, 0xc888, 0x21, 0 + .dw 0x6a40, 0xc888, 0x6a7f, 0xc888, 0x21, 0 + .dw 0x6ac0, 0xc888, 0x6aff, 0xc888, 0x21, 0 + .dw 0x6b40, 0xc888, 0x6b7f, 0xc888, 0x21, 0 + .dw 0x6bc0, 0xc888, 0x6bff, 0xc888, 0x21, 0 + .dw 0x6c40, 0xc888, 0x6c7f, 0xc888, 0x21, 0 + .dw 0x6cc0, 0xc888, 0x6cff, 0xc888, 0x21, 0 + .dw 0x6d40, 0xc888, 0x6d7f, 0xc888, 0x21, 0 + .dw 0x6dc0, 0xc888, 0x6dff, 0xc888, 0x21, 0 + .dw 0x6e40, 0xc888, 0x6e7f, 0xc888, 0x21, 0 + .dw 0x6ec0, 0xc888, 0x6eff, 0xc888, 0x21, 0 + .dw 0x6f40, 0xc888, 0x6f7f, 0xc888, 0x21, 0 + .dw 0x6fc0, 0xc888, 0x6fff, 0xc888, 0x21, 0 + .dw 0x7040, 0xc888, 0x707f, 0xc888, 0x21, 0 + .dw 0x70c0, 0xc888, 0x70ff, 0xc888, 0x21, 0 + .dw 0x7140, 0xc888, 0x717f, 0xc888, 0x21, 0 + .dw 0x71c0, 0xc888, 0x71ff, 0xc888, 0x21, 0 + .dw 0x7240, 0xc888, 0x727f, 0xc888, 0x21, 0 + .dw 0x72c0, 0xc888, 0x72ff, 0xc888, 0x21, 0 + .dw 0x7340, 0xc888, 0x737f, 0xc888, 0x21, 0 + .dw 0x73c0, 0xc888, 0x73ff, 0xc888, 0x21, 0 + .dw 0x7440, 0xc888, 0x747f, 0xc888, 0x21, 0 + .dw 0x74c0, 0xc888, 0x74ff, 0xc888, 0x21, 0 + .dw 0x7540, 0xc888, 0x757f, 0xc888, 0x21, 0 + .dw 0x75c0, 0xc888, 0x75ff, 0xc888, 0x21, 0 + .dw 0x7640, 0xc888, 0x767f, 0xc888, 0x21, 0 + .dw 0x76c0, 0xc888, 0x76ff, 0xc888, 0x21, 0 + .dw 0x7740, 0xc888, 0x777f, 0xc888, 0x21, 0 + .dw 0x77c0, 0xc888, 0x77ff, 0xc888, 0x21, 0 + .dw 0x7840, 0xc888, 0x787f, 0xc888, 0x21, 0 + .dw 0x78c0, 0xc888, 0x78ff, 0xc888, 0x21, 0 + .dw 0x7940, 0xc888, 0x797f, 0xc888, 0x21, 0 + .dw 0x79c0, 0xc888, 0x9fff, 0xc888, 0x21, 0 + .dw 0xa040, 0xc888, 0xa07f, 0xc888, 0x21, 0 + .dw 0xa0c0, 0xc888, 0xa0ff, 0xc888, 0x21, 0 + .dw 0xa140, 0xc888, 0xa17f, 0xc888, 0x21, 0 + .dw 0xa1c0, 0xc888, 0xa1ff, 0xc888, 0x21, 0 + .dw 0xa240, 0xc888, 0xa27f, 0xc888, 0x21, 0 + .dw 0xa2c0, 0xc888, 0xa2ff, 0xc888, 0x21, 0 + .dw 0xa340, 0xc888, 0xa37f, 0xc888, 0x21, 0 + .dw 0xa3c0, 0xc888, 0xa3ff, 0xc888, 0x21, 0 + .dw 0xa440, 0xc888, 0xa47f, 0xc888, 0x21, 0 + .dw 0xa4c0, 0xc888, 0xa4ff, 0xc888, 0x21, 0 + .dw 0xa540, 0xc888, 0xa57f, 0xc888, 0x21, 0 + .dw 0xa5c0, 0xc888, 0xa5ff, 0xc888, 0x21, 0 + .dw 0xa640, 0xc888, 0xa67f, 0xc888, 0x21, 0 + .dw 0xa6c0, 0xc888, 0xa6ff, 0xc888, 0x21, 0 + .dw 0xa740, 0xc888, 0xa77f, 0xc888, 0x21, 0 + .dw 0xa7c0, 0xc888, 0xa7ff, 0xc888, 0x21, 0 + .dw 0xa840, 0xc888, 0xa87f, 0xc888, 0x21, 0 + .dw 0xa8c0, 0xc888, 0xa8ff, 0xc888, 0x21, 0 + .dw 0xa940, 0xc888, 0xa97f, 0xc888, 0x21, 0 + .dw 0xa9c0, 0xc888, 0xa9ff, 0xc888, 0x21, 0 + .dw 0xaa40, 0xc888, 0xaa7f, 0xc888, 0x21, 0 + .dw 0xaac0, 0xc888, 0xaaff, 0xc888, 0x21, 0 + .dw 0xab40, 0xc888, 0xab7f, 0xc888, 0x21, 0 + .dw 0xabc0, 0xc888, 0xabff, 0xc888, 0x21, 0 + .dw 0xac40, 0xc888, 0xac7f, 0xc888, 0x21, 0 + .dw 0xacc0, 0xc888, 0xacff, 0xc888, 0x21, 0 + .dw 0xad40, 0xc888, 0xad7f, 0xc888, 0x21, 0 + .dw 0xadc0, 0xc888, 0xadff, 0xc888, 0x21, 0 + .dw 0xae40, 0xc888, 0xae7f, 0xc888, 0x21, 0 + .dw 0xaec0, 0xc888, 0xaeff, 0xc888, 0x21, 0 + .dw 0xaf40, 0xc888, 0xaf7f, 0xc888, 0x21, 0 + .dw 0xafc0, 0xc888, 0xafff, 0xc888, 0x21, 0 + .dw 0xb040, 0xc888, 0xb07f, 0xc888, 0x21, 0 + .dw 0xb0c0, 0xc888, 0xb0ff, 0xc888, 0x21, 0 + .dw 0xb140, 0xc888, 0xb17f, 0xc888, 0x21, 0 + .dw 0xb1c0, 0xc888, 0xb1ff, 0xc888, 0x21, 0 + .dw 0xb240, 0xc888, 0xb27f, 0xc888, 0x21, 0 + .dw 0xb2c0, 0xc888, 0xb2ff, 0xc888, 0x21, 0 + .dw 0xb340, 0xc888, 0xb37f, 0xc888, 0x21, 0 + .dw 0xb3c0, 0xc888, 0xb3ff, 0xc888, 0x21, 0 + .dw 0xb440, 0xc888, 0xb47f, 0xc888, 0x21, 0 + .dw 0xb4c0, 0xc888, 0xb4ff, 0xc888, 0x21, 0 + .dw 0xb540, 0xc888, 0xb57f, 0xc888, 0x21, 0 + .dw 0xb5c0, 0xc888, 0xb5ff, 0xc888, 0x21, 0 + .dw 0xb640, 0xc888, 0xb67f, 0xc888, 0x21, 0 + .dw 0xb6c0, 0xc888, 0xb6ff, 0xc888, 0x21, 0 + .dw 0xb740, 0xc888, 0xb77f, 0xc888, 0x21, 0 + .dw 0xb7c0, 0xc888, 0xb7ff, 0xc888, 0x21, 0 + .dw 0xb840, 0xc888, 0xb87f, 0xc888, 0x21, 0 + .dw 0xb8c0, 0xc888, 0xb8ff, 0xc888, 0x21, 0 + .dw 0xb940, 0xc888, 0xb97f, 0xc888, 0x21, 0 + .dw 0xb9c0, 0xc888, 0xdfff, 0xc888, 0x21, 0 + .dw 0xe040, 0xc888, 0xe07f, 0xc888, 0x21, 0 + .dw 0xe0c0, 0xc888, 0xe0ff, 0xc888, 0x21, 0 + .dw 0xe140, 0xc888, 0xe17f, 0xc888, 0x21, 0 + .dw 0xe1c0, 0xc888, 0xe1ff, 0xc888, 0x21, 0 + .dw 0xe240, 0xc888, 0xe27f, 0xc888, 0x21, 0 + .dw 0xe2c0, 0xc888, 0xe2ff, 0xc888, 0x21, 0 + .dw 0xe340, 0xc888, 0xe37f, 0xc888, 0x21, 0 + .dw 0xe3c0, 0xc888, 0xe3ff, 0xc888, 0x21, 0 + .dw 0xe440, 0xc888, 0xe47f, 0xc888, 0x21, 0 + .dw 0xe4c0, 0xc888, 0xe4ff, 0xc888, 0x21, 0 + .dw 0xe540, 0xc888, 0xe57f, 0xc888, 0x21, 0 + .dw 0xe5c0, 0xc888, 0xe5ff, 0xc888, 0x21, 0 + .dw 0xe640, 0xc888, 0xe67f, 0xc888, 0x21, 0 + .dw 0xe6c0, 0xc888, 0xe6ff, 0xc888, 0x21, 0 + .dw 0xe740, 0xc888, 0xe77f, 0xc888, 0x21, 0 + .dw 0xe7c0, 0xc888, 0xe7ff, 0xc888, 0x21, 0 + .dw 0xe840, 0xc888, 0xe87f, 0xc888, 0x21, 0 + .dw 0xe8c0, 0xc888, 0xe8ff, 0xc888, 0x21, 0 + .dw 0xe940, 0xc888, 0xe97f, 0xc888, 0x21, 0 + .dw 0xe9c0, 0xc888, 0xe9ff, 0xc888, 0x21, 0 + .dw 0xea40, 0xc888, 0xea7f, 0xc888, 0x21, 0 + .dw 0xeac0, 0xc888, 0xeaff, 0xc888, 0x21, 0 + .dw 0xeb40, 0xc888, 0xeb7f, 0xc888, 0x21, 0 + .dw 0xebc0, 0xc888, 0xebff, 0xc888, 0x21, 0 + .dw 0xec40, 0xc888, 0xec7f, 0xc888, 0x21, 0 + .dw 0xecc0, 0xc888, 0xecff, 0xc888, 0x21, 0 + .dw 0xed40, 0xc888, 0xed7f, 0xc888, 0x21, 0 + .dw 0xedc0, 0xc888, 0xedff, 0xc888, 0x21, 0 + .dw 0xee40, 0xc888, 0xee7f, 0xc888, 0x21, 0 + .dw 0xeec0, 0xc888, 0xeeff, 0xc888, 0x21, 0 + .dw 0xef40, 0xc888, 0xef7f, 0xc888, 0x21, 0 + .dw 0xefc0, 0xc888, 0xefff, 0xc888, 0x21, 0 + .dw 0xf040, 0xc888, 0xf07f, 0xc888, 0x21, 0 + .dw 0xf0c0, 0xc888, 0xf0ff, 0xc888, 0x21, 0 + .dw 0xf140, 0xc888, 0xf17f, 0xc888, 0x21, 0 + .dw 0xf1c0, 0xc888, 0xf1ff, 0xc888, 0x21, 0 + .dw 0xf240, 0xc888, 0xf27f, 0xc888, 0x21, 0 + .dw 0xf2c0, 0xc888, 0xf2ff, 0xc888, 0x21, 0 + .dw 0xf340, 0xc888, 0xf37f, 0xc888, 0x21, 0 + .dw 0xf3c0, 0xc888, 0xf3ff, 0xc888, 0x21, 0 + .dw 0xf440, 0xc888, 0xf47f, 0xc888, 0x21, 0 + .dw 0xf4c0, 0xc888, 0xf4ff, 0xc888, 0x21, 0 + .dw 0xf540, 0xc888, 0xf57f, 0xc888, 0x21, 0 + .dw 0xf5c0, 0xc888, 0xf5ff, 0xc888, 0x21, 0 + .dw 0xf640, 0xc888, 0xf67f, 0xc888, 0x21, 0 + .dw 0xf6c0, 0xc888, 0xf6ff, 0xc888, 0x21, 0 + .dw 0xf740, 0xc888, 0xf77f, 0xc888, 0x21, 0 + .dw 0xf7c0, 0xc888, 0xf7ff, 0xc888, 0x21, 0 + .dw 0xf840, 0xc888, 0xf87f, 0xc888, 0x21, 0 + .dw 0xf8c0, 0xc888, 0xf8ff, 0xc888, 0x21, 0 + .dw 0xf940, 0xc888, 0xf97f, 0xc888, 0x21, 0 + .dw 0xf9c0, 0xc888, 0x1fff, 0xc889, 0x21, 0 + .dw 0x2040, 0xc889, 0x207f, 0xc889, 0x21, 0 + .dw 0x20c0, 0xc889, 0x20ff, 0xc889, 0x21, 0 + .dw 0x2140, 0xc889, 0x217f, 0xc889, 0x21, 0 + .dw 0x21c0, 0xc889, 0x21ff, 0xc889, 0x21, 0 + .dw 0x2240, 0xc889, 0x227f, 0xc889, 0x21, 0 + .dw 0x22c0, 0xc889, 0x22ff, 0xc889, 0x21, 0 + .dw 0x2340, 0xc889, 0x237f, 0xc889, 0x21, 0 + .dw 0x23c0, 0xc889, 0x23ff, 0xc889, 0x21, 0 + .dw 0x2440, 0xc889, 0x247f, 0xc889, 0x21, 0 + .dw 0x24c0, 0xc889, 0x24ff, 0xc889, 0x21, 0 + .dw 0x2540, 0xc889, 0x257f, 0xc889, 0x21, 0 + .dw 0x25c0, 0xc889, 0x25ff, 0xc889, 0x21, 0 + .dw 0x2640, 0xc889, 0x267f, 0xc889, 0x21, 0 + .dw 0x26c0, 0xc889, 0x26ff, 0xc889, 0x21, 0 + .dw 0x2740, 0xc889, 0x277f, 0xc889, 0x21, 0 + .dw 0x27c0, 0xc889, 0x27ff, 0xc889, 0x21, 0 + .dw 0x2840, 0xc889, 0x287f, 0xc889, 0x21, 0 + .dw 0x28c0, 0xc889, 0x28ff, 0xc889, 0x21, 0 + .dw 0x2940, 0xc889, 0x297f, 0xc889, 0x21, 0 + .dw 0x29c0, 0xc889, 0x29ff, 0xc889, 0x21, 0 + .dw 0x2a40, 0xc889, 0x2a7f, 0xc889, 0x21, 0 + .dw 0x2ac0, 0xc889, 0x2aff, 0xc889, 0x21, 0 + .dw 0x2b40, 0xc889, 0x2b7f, 0xc889, 0x21, 0 + .dw 0x2bc0, 0xc889, 0x2bff, 0xc889, 0x21, 0 + .dw 0x2c40, 0xc889, 0x2c7f, 0xc889, 0x21, 0 + .dw 0x2cc0, 0xc889, 0x2cff, 0xc889, 0x21, 0 + .dw 0x2d40, 0xc889, 0x2d7f, 0xc889, 0x21, 0 + .dw 0x2dc0, 0xc889, 0x2dff, 0xc889, 0x21, 0 + .dw 0x2e40, 0xc889, 0x2e7f, 0xc889, 0x21, 0 + .dw 0x2ec0, 0xc889, 0x2eff, 0xc889, 0x21, 0 + .dw 0x2f40, 0xc889, 0x2f7f, 0xc889, 0x21, 0 + .dw 0x2fc0, 0xc889, 0x2fff, 0xc889, 0x21, 0 + .dw 0x3040, 0xc889, 0x307f, 0xc889, 0x21, 0 + .dw 0x30c0, 0xc889, 0x30ff, 0xc889, 0x21, 0 + .dw 0x3140, 0xc889, 0x317f, 0xc889, 0x21, 0 + .dw 0x31c0, 0xc889, 0x31ff, 0xc889, 0x21, 0 + .dw 0x3240, 0xc889, 0x327f, 0xc889, 0x21, 0 + .dw 0x32c0, 0xc889, 0x32ff, 0xc889, 0x21, 0 + .dw 0x3340, 0xc889, 0x337f, 0xc889, 0x21, 0 + .dw 0x33c0, 0xc889, 0x33ff, 0xc889, 0x21, 0 + .dw 0x3440, 0xc889, 0x347f, 0xc889, 0x21, 0 + .dw 0x34c0, 0xc889, 0x34ff, 0xc889, 0x21, 0 + .dw 0x3540, 0xc889, 0x357f, 0xc889, 0x21, 0 + .dw 0x35c0, 0xc889, 0x35ff, 0xc889, 0x21, 0 + .dw 0x3640, 0xc889, 0x367f, 0xc889, 0x21, 0 + .dw 0x36c0, 0xc889, 0x36ff, 0xc889, 0x21, 0 + .dw 0x3740, 0xc889, 0x377f, 0xc889, 0x21, 0 + .dw 0x37c0, 0xc889, 0x37ff, 0xc889, 0x21, 0 + .dw 0x3840, 0xc889, 0x387f, 0xc889, 0x21, 0 + .dw 0x38c0, 0xc889, 0x38ff, 0xc889, 0x21, 0 + .dw 0x3940, 0xc889, 0x397f, 0xc889, 0x21, 0 + .dw 0x39c0, 0xc889, 0x5fff, 0xc889, 0x21, 0 + .dw 0x6040, 0xc889, 0x607f, 0xc889, 0x21, 0 + .dw 0x60c0, 0xc889, 0x60ff, 0xc889, 0x21, 0 + .dw 0x6140, 0xc889, 0x617f, 0xc889, 0x21, 0 + .dw 0x61c0, 0xc889, 0x61ff, 0xc889, 0x21, 0 + .dw 0x6240, 0xc889, 0x627f, 0xc889, 0x21, 0 + .dw 0x62c0, 0xc889, 0x62ff, 0xc889, 0x21, 0 + .dw 0x6340, 0xc889, 0x637f, 0xc889, 0x21, 0 + .dw 0x63c0, 0xc889, 0x63ff, 0xc889, 0x21, 0 + .dw 0x6440, 0xc889, 0x647f, 0xc889, 0x21, 0 + .dw 0x64c0, 0xc889, 0x64ff, 0xc889, 0x21, 0 + .dw 0x6540, 0xc889, 0x657f, 0xc889, 0x21, 0 + .dw 0x65c0, 0xc889, 0x65ff, 0xc889, 0x21, 0 + .dw 0x6640, 0xc889, 0x667f, 0xc889, 0x21, 0 + .dw 0x66c0, 0xc889, 0x66ff, 0xc889, 0x21, 0 + .dw 0x6740, 0xc889, 0x677f, 0xc889, 0x21, 0 + .dw 0x67c0, 0xc889, 0x67ff, 0xc889, 0x21, 0 + .dw 0x6840, 0xc889, 0x687f, 0xc889, 0x21, 0 + .dw 0x68c0, 0xc889, 0x68ff, 0xc889, 0x21, 0 + .dw 0x6940, 0xc889, 0x697f, 0xc889, 0x21, 0 + .dw 0x69c0, 0xc889, 0x69ff, 0xc889, 0x21, 0 + .dw 0x6a40, 0xc889, 0x6a7f, 0xc889, 0x21, 0 + .dw 0x6ac0, 0xc889, 0x6aff, 0xc889, 0x21, 0 + .dw 0x6b40, 0xc889, 0x6b7f, 0xc889, 0x21, 0 + .dw 0x6bc0, 0xc889, 0x6bff, 0xc889, 0x21, 0 + .dw 0x6c40, 0xc889, 0x6c7f, 0xc889, 0x21, 0 + .dw 0x6cc0, 0xc889, 0x6cff, 0xc889, 0x21, 0 + .dw 0x6d40, 0xc889, 0x6d7f, 0xc889, 0x21, 0 + .dw 0x6dc0, 0xc889, 0x6dff, 0xc889, 0x21, 0 + .dw 0x6e40, 0xc889, 0x6e7f, 0xc889, 0x21, 0 + .dw 0x6ec0, 0xc889, 0x6eff, 0xc889, 0x21, 0 + .dw 0x6f40, 0xc889, 0x6f7f, 0xc889, 0x21, 0 + .dw 0x6fc0, 0xc889, 0x6fff, 0xc889, 0x21, 0 + .dw 0x7040, 0xc889, 0x707f, 0xc889, 0x21, 0 + .dw 0x70c0, 0xc889, 0x70ff, 0xc889, 0x21, 0 + .dw 0x7140, 0xc889, 0x717f, 0xc889, 0x21, 0 + .dw 0x71c0, 0xc889, 0x71ff, 0xc889, 0x21, 0 + .dw 0x7240, 0xc889, 0x727f, 0xc889, 0x21, 0 + .dw 0x72c0, 0xc889, 0x72ff, 0xc889, 0x21, 0 + .dw 0x7340, 0xc889, 0x737f, 0xc889, 0x21, 0 + .dw 0x73c0, 0xc889, 0x73ff, 0xc889, 0x21, 0 + .dw 0x7440, 0xc889, 0x747f, 0xc889, 0x21, 0 + .dw 0x74c0, 0xc889, 0x74ff, 0xc889, 0x21, 0 + .dw 0x7540, 0xc889, 0x757f, 0xc889, 0x21, 0 + .dw 0x75c0, 0xc889, 0x75ff, 0xc889, 0x21, 0 + .dw 0x7640, 0xc889, 0x767f, 0xc889, 0x21, 0 + .dw 0x76c0, 0xc889, 0x76ff, 0xc889, 0x21, 0 + .dw 0x7740, 0xc889, 0x777f, 0xc889, 0x21, 0 + .dw 0x77c0, 0xc889, 0x77ff, 0xc889, 0x21, 0 + .dw 0x7840, 0xc889, 0x787f, 0xc889, 0x21, 0 + .dw 0x78c0, 0xc889, 0x78ff, 0xc889, 0x21, 0 + .dw 0x7940, 0xc889, 0x797f, 0xc889, 0x21, 0 + .dw 0x79c0, 0xc889, 0x9fff, 0xc889, 0x21, 0 + .dw 0xa040, 0xc889, 0xa07f, 0xc889, 0x21, 0 + .dw 0xa0c0, 0xc889, 0xa0ff, 0xc889, 0x21, 0 + .dw 0xa140, 0xc889, 0xa17f, 0xc889, 0x21, 0 + .dw 0xa1c0, 0xc889, 0xa1ff, 0xc889, 0x21, 0 + .dw 0xa240, 0xc889, 0xa27f, 0xc889, 0x21, 0 + .dw 0xa2c0, 0xc889, 0xa2ff, 0xc889, 0x21, 0 + .dw 0xa340, 0xc889, 0xa37f, 0xc889, 0x21, 0 + .dw 0xa3c0, 0xc889, 0xa3ff, 0xc889, 0x21, 0 + .dw 0xa440, 0xc889, 0xa47f, 0xc889, 0x21, 0 + .dw 0xa4c0, 0xc889, 0xa4ff, 0xc889, 0x21, 0 + .dw 0xa540, 0xc889, 0xa57f, 0xc889, 0x21, 0 + .dw 0xa5c0, 0xc889, 0xa5ff, 0xc889, 0x21, 0 + .dw 0xa640, 0xc889, 0xa67f, 0xc889, 0x21, 0 + .dw 0xa6c0, 0xc889, 0xa6ff, 0xc889, 0x21, 0 + .dw 0xa740, 0xc889, 0xa77f, 0xc889, 0x21, 0 + .dw 0xa7c0, 0xc889, 0xa7ff, 0xc889, 0x21, 0 + .dw 0xa840, 0xc889, 0xa87f, 0xc889, 0x21, 0 + .dw 0xa8c0, 0xc889, 0xa8ff, 0xc889, 0x21, 0 + .dw 0xa940, 0xc889, 0xa97f, 0xc889, 0x21, 0 + .dw 0xa9c0, 0xc889, 0xa9ff, 0xc889, 0x21, 0 + .dw 0xaa40, 0xc889, 0xaa7f, 0xc889, 0x21, 0 + .dw 0xaac0, 0xc889, 0xaaff, 0xc889, 0x21, 0 + .dw 0xab40, 0xc889, 0xab7f, 0xc889, 0x21, 0 + .dw 0xabc0, 0xc889, 0xabff, 0xc889, 0x21, 0 + .dw 0xac40, 0xc889, 0xac7f, 0xc889, 0x21, 0 + .dw 0xacc0, 0xc889, 0xacff, 0xc889, 0x21, 0 + .dw 0xad40, 0xc889, 0xad7f, 0xc889, 0x21, 0 + .dw 0xadc0, 0xc889, 0xadff, 0xc889, 0x21, 0 + .dw 0xae40, 0xc889, 0xae7f, 0xc889, 0x21, 0 + .dw 0xaec0, 0xc889, 0xaeff, 0xc889, 0x21, 0 + .dw 0xaf40, 0xc889, 0xaf7f, 0xc889, 0x21, 0 + .dw 0xafc0, 0xc889, 0xafff, 0xc889, 0x21, 0 + .dw 0xb040, 0xc889, 0xb07f, 0xc889, 0x21, 0 + .dw 0xb0c0, 0xc889, 0xb0ff, 0xc889, 0x21, 0 + .dw 0xb140, 0xc889, 0xb17f, 0xc889, 0x21, 0 + .dw 0xb1c0, 0xc889, 0xb1ff, 0xc889, 0x21, 0 + .dw 0xb240, 0xc889, 0xb27f, 0xc889, 0x21, 0 + .dw 0xb2c0, 0xc889, 0xb2ff, 0xc889, 0x21, 0 + .dw 0xb340, 0xc889, 0xb37f, 0xc889, 0x21, 0 + .dw 0xb3c0, 0xc889, 0xb3ff, 0xc889, 0x21, 0 + .dw 0xb440, 0xc889, 0xb47f, 0xc889, 0x21, 0 + .dw 0xb4c0, 0xc889, 0xb4ff, 0xc889, 0x21, 0 + .dw 0xb540, 0xc889, 0xb57f, 0xc889, 0x21, 0 + .dw 0xb5c0, 0xc889, 0xb5ff, 0xc889, 0x21, 0 + .dw 0xb640, 0xc889, 0xb67f, 0xc889, 0x21, 0 + .dw 0xb6c0, 0xc889, 0xb6ff, 0xc889, 0x21, 0 + .dw 0xb740, 0xc889, 0xb77f, 0xc889, 0x21, 0 + .dw 0xb7c0, 0xc889, 0xb7ff, 0xc889, 0x21, 0 + .dw 0xb840, 0xc889, 0xb87f, 0xc889, 0x21, 0 + .dw 0xb8c0, 0xc889, 0xb8ff, 0xc889, 0x21, 0 + .dw 0xb940, 0xc889, 0xb97f, 0xc889, 0x21, 0 + .dw 0xb9c0, 0xc889, 0xdfff, 0xc889, 0x21, 0 + .dw 0xe040, 0xc889, 0xe07f, 0xc889, 0x21, 0 + .dw 0xe0c0, 0xc889, 0xe0ff, 0xc889, 0x21, 0 + .dw 0xe140, 0xc889, 0xe17f, 0xc889, 0x21, 0 + .dw 0xe1c0, 0xc889, 0xe1ff, 0xc889, 0x21, 0 + .dw 0xe240, 0xc889, 0xe27f, 0xc889, 0x21, 0 + .dw 0xe2c0, 0xc889, 0xe2ff, 0xc889, 0x21, 0 + .dw 0xe340, 0xc889, 0xe37f, 0xc889, 0x21, 0 + .dw 0xe3c0, 0xc889, 0xe3ff, 0xc889, 0x21, 0 + .dw 0xe440, 0xc889, 0xe47f, 0xc889, 0x21, 0 + .dw 0xe4c0, 0xc889, 0xe4ff, 0xc889, 0x21, 0 + .dw 0xe540, 0xc889, 0xe57f, 0xc889, 0x21, 0 + .dw 0xe5c0, 0xc889, 0xe5ff, 0xc889, 0x21, 0 + .dw 0xe640, 0xc889, 0xe67f, 0xc889, 0x21, 0 + .dw 0xe6c0, 0xc889, 0xe6ff, 0xc889, 0x21, 0 + .dw 0xe740, 0xc889, 0xe77f, 0xc889, 0x21, 0 + .dw 0xe7c0, 0xc889, 0xe7ff, 0xc889, 0x21, 0 + .dw 0xe840, 0xc889, 0xe87f, 0xc889, 0x21, 0 + .dw 0xe8c0, 0xc889, 0xe8ff, 0xc889, 0x21, 0 + .dw 0xe940, 0xc889, 0xe97f, 0xc889, 0x21, 0 + .dw 0xe9c0, 0xc889, 0xe9ff, 0xc889, 0x21, 0 + .dw 0xea40, 0xc889, 0xea7f, 0xc889, 0x21, 0 + .dw 0xeac0, 0xc889, 0xeaff, 0xc889, 0x21, 0 + .dw 0xeb40, 0xc889, 0xeb7f, 0xc889, 0x21, 0 + .dw 0xebc0, 0xc889, 0xebff, 0xc889, 0x21, 0 + .dw 0xec40, 0xc889, 0xec7f, 0xc889, 0x21, 0 + .dw 0xecc0, 0xc889, 0xecff, 0xc889, 0x21, 0 + .dw 0xed40, 0xc889, 0xed7f, 0xc889, 0x21, 0 + .dw 0xedc0, 0xc889, 0xedff, 0xc889, 0x21, 0 + .dw 0xee40, 0xc889, 0xee7f, 0xc889, 0x21, 0 + .dw 0xeec0, 0xc889, 0xeeff, 0xc889, 0x21, 0 + .dw 0xef40, 0xc889, 0xef7f, 0xc889, 0x21, 0 + .dw 0xefc0, 0xc889, 0xefff, 0xc889, 0x21, 0 + .dw 0xf040, 0xc889, 0xf07f, 0xc889, 0x21, 0 + .dw 0xf0c0, 0xc889, 0xf0ff, 0xc889, 0x21, 0 + .dw 0xf140, 0xc889, 0xf17f, 0xc889, 0x21, 0 + .dw 0xf1c0, 0xc889, 0xf1ff, 0xc889, 0x21, 0 + .dw 0xf240, 0xc889, 0xf27f, 0xc889, 0x21, 0 + .dw 0xf2c0, 0xc889, 0xf2ff, 0xc889, 0x21, 0 + .dw 0xf340, 0xc889, 0xf37f, 0xc889, 0x21, 0 + .dw 0xf3c0, 0xc889, 0xf3ff, 0xc889, 0x21, 0 + .dw 0xf440, 0xc889, 0xf47f, 0xc889, 0x21, 0 + .dw 0xf4c0, 0xc889, 0xf4ff, 0xc889, 0x21, 0 + .dw 0xf540, 0xc889, 0xf57f, 0xc889, 0x21, 0 + .dw 0xf5c0, 0xc889, 0xf5ff, 0xc889, 0x21, 0 + .dw 0xf640, 0xc889, 0xf67f, 0xc889, 0x21, 0 + .dw 0xf6c0, 0xc889, 0xf6ff, 0xc889, 0x21, 0 + .dw 0xf740, 0xc889, 0xf77f, 0xc889, 0x21, 0 + .dw 0xf7c0, 0xc889, 0xf7ff, 0xc889, 0x21, 0 + .dw 0xf840, 0xc889, 0xf87f, 0xc889, 0x21, 0 + .dw 0xf8c0, 0xc889, 0xf8ff, 0xc889, 0x21, 0 + .dw 0xf940, 0xc889, 0xf97f, 0xc889, 0x21, 0 + .dw 0xf9c0, 0xc889, 0x1fff, 0xc88a, 0x21, 0 + .dw 0x2040, 0xc88a, 0x207f, 0xc88a, 0x21, 0 + .dw 0x20c0, 0xc88a, 0x20ff, 0xc88a, 0x21, 0 + .dw 0x2140, 0xc88a, 0x217f, 0xc88a, 0x21, 0 + .dw 0x21c0, 0xc88a, 0x21ff, 0xc88a, 0x21, 0 + .dw 0x2240, 0xc88a, 0x227f, 0xc88a, 0x21, 0 + .dw 0x22c0, 0xc88a, 0x22ff, 0xc88a, 0x21, 0 + .dw 0x2340, 0xc88a, 0x237f, 0xc88a, 0x21, 0 + .dw 0x23c0, 0xc88a, 0x23ff, 0xc88a, 0x21, 0 + .dw 0x2440, 0xc88a, 0x247f, 0xc88a, 0x21, 0 + .dw 0x24c0, 0xc88a, 0x24ff, 0xc88a, 0x21, 0 + .dw 0x2540, 0xc88a, 0x257f, 0xc88a, 0x21, 0 + .dw 0x25c0, 0xc88a, 0x25ff, 0xc88a, 0x21, 0 + .dw 0x2640, 0xc88a, 0x267f, 0xc88a, 0x21, 0 + .dw 0x26c0, 0xc88a, 0x26ff, 0xc88a, 0x21, 0 + .dw 0x2740, 0xc88a, 0x277f, 0xc88a, 0x21, 0 + .dw 0x27c0, 0xc88a, 0x27ff, 0xc88a, 0x21, 0 + .dw 0x2840, 0xc88a, 0x287f, 0xc88a, 0x21, 0 + .dw 0x28c0, 0xc88a, 0x28ff, 0xc88a, 0x21, 0 + .dw 0x2940, 0xc88a, 0x297f, 0xc88a, 0x21, 0 + .dw 0x29c0, 0xc88a, 0x29ff, 0xc88a, 0x21, 0 + .dw 0x2a40, 0xc88a, 0x2a7f, 0xc88a, 0x21, 0 + .dw 0x2ac0, 0xc88a, 0x2aff, 0xc88a, 0x21, 0 + .dw 0x2b40, 0xc88a, 0x2b7f, 0xc88a, 0x21, 0 + .dw 0x2bc0, 0xc88a, 0x2bff, 0xc88a, 0x21, 0 + .dw 0x2c40, 0xc88a, 0x2c7f, 0xc88a, 0x21, 0 + .dw 0x2cc0, 0xc88a, 0x2cff, 0xc88a, 0x21, 0 + .dw 0x2d40, 0xc88a, 0x2d7f, 0xc88a, 0x21, 0 + .dw 0x2dc0, 0xc88a, 0x2dff, 0xc88a, 0x21, 0 + .dw 0x2e40, 0xc88a, 0x2e7f, 0xc88a, 0x21, 0 + .dw 0x2ec0, 0xc88a, 0x2eff, 0xc88a, 0x21, 0 + .dw 0x2f40, 0xc88a, 0x2f7f, 0xc88a, 0x21, 0 + .dw 0x2fc0, 0xc88a, 0x2fff, 0xc88a, 0x21, 0 + .dw 0x3040, 0xc88a, 0x307f, 0xc88a, 0x21, 0 + .dw 0x30c0, 0xc88a, 0x30ff, 0xc88a, 0x21, 0 + .dw 0x3140, 0xc88a, 0x317f, 0xc88a, 0x21, 0 + .dw 0x31c0, 0xc88a, 0x31ff, 0xc88a, 0x21, 0 + .dw 0x3240, 0xc88a, 0x327f, 0xc88a, 0x21, 0 + .dw 0x32c0, 0xc88a, 0x32ff, 0xc88a, 0x21, 0 + .dw 0x3340, 0xc88a, 0x337f, 0xc88a, 0x21, 0 + .dw 0x33c0, 0xc88a, 0x33ff, 0xc88a, 0x21, 0 + .dw 0x3440, 0xc88a, 0x347f, 0xc88a, 0x21, 0 + .dw 0x34c0, 0xc88a, 0x34ff, 0xc88a, 0x21, 0 + .dw 0x3540, 0xc88a, 0x357f, 0xc88a, 0x21, 0 + .dw 0x35c0, 0xc88a, 0x35ff, 0xc88a, 0x21, 0 + .dw 0x3640, 0xc88a, 0x367f, 0xc88a, 0x21, 0 + .dw 0x36c0, 0xc88a, 0x36ff, 0xc88a, 0x21, 0 + .dw 0x3740, 0xc88a, 0x377f, 0xc88a, 0x21, 0 + .dw 0x37c0, 0xc88a, 0x37ff, 0xc88a, 0x21, 0 + .dw 0x3840, 0xc88a, 0x387f, 0xc88a, 0x21, 0 + .dw 0x38c0, 0xc88a, 0x38ff, 0xc88a, 0x21, 0 + .dw 0x3940, 0xc88a, 0x397f, 0xc88a, 0x21, 0 + .dw 0x39c0, 0xc88a, 0x5fff, 0xc88a, 0x21, 0 + .dw 0x6040, 0xc88a, 0x607f, 0xc88a, 0x21, 0 + .dw 0x60c0, 0xc88a, 0x60ff, 0xc88a, 0x21, 0 + .dw 0x6140, 0xc88a, 0x617f, 0xc88a, 0x21, 0 + .dw 0x61c0, 0xc88a, 0x61ff, 0xc88a, 0x21, 0 + .dw 0x6240, 0xc88a, 0x627f, 0xc88a, 0x21, 0 + .dw 0x62c0, 0xc88a, 0x62ff, 0xc88a, 0x21, 0 + .dw 0x6340, 0xc88a, 0x637f, 0xc88a, 0x21, 0 + .dw 0x63c0, 0xc88a, 0x63ff, 0xc88a, 0x21, 0 + .dw 0x6440, 0xc88a, 0x647f, 0xc88a, 0x21, 0 + .dw 0x64c0, 0xc88a, 0x64ff, 0xc88a, 0x21, 0 + .dw 0x6540, 0xc88a, 0x657f, 0xc88a, 0x21, 0 + .dw 0x65c0, 0xc88a, 0x65ff, 0xc88a, 0x21, 0 + .dw 0x6640, 0xc88a, 0x667f, 0xc88a, 0x21, 0 + .dw 0x66c0, 0xc88a, 0x66ff, 0xc88a, 0x21, 0 + .dw 0x6740, 0xc88a, 0x677f, 0xc88a, 0x21, 0 + .dw 0x67c0, 0xc88a, 0x67ff, 0xc88a, 0x21, 0 + .dw 0x6840, 0xc88a, 0x687f, 0xc88a, 0x21, 0 + .dw 0x68c0, 0xc88a, 0x68ff, 0xc88a, 0x21, 0 + .dw 0x6940, 0xc88a, 0x697f, 0xc88a, 0x21, 0 + .dw 0x69c0, 0xc88a, 0x69ff, 0xc88a, 0x21, 0 + .dw 0x6a40, 0xc88a, 0x6a7f, 0xc88a, 0x21, 0 + .dw 0x6ac0, 0xc88a, 0x6aff, 0xc88a, 0x21, 0 + .dw 0x6b40, 0xc88a, 0x6b7f, 0xc88a, 0x21, 0 + .dw 0x6bc0, 0xc88a, 0x6bff, 0xc88a, 0x21, 0 + .dw 0x6c40, 0xc88a, 0x6c7f, 0xc88a, 0x21, 0 + .dw 0x6cc0, 0xc88a, 0x6cff, 0xc88a, 0x21, 0 + .dw 0x6d40, 0xc88a, 0x6d7f, 0xc88a, 0x21, 0 + .dw 0x6dc0, 0xc88a, 0x6dff, 0xc88a, 0x21, 0 + .dw 0x6e40, 0xc88a, 0x6e7f, 0xc88a, 0x21, 0 + .dw 0x6ec0, 0xc88a, 0x6eff, 0xc88a, 0x21, 0 + .dw 0x6f40, 0xc88a, 0x6f7f, 0xc88a, 0x21, 0 + .dw 0x6fc0, 0xc88a, 0x6fff, 0xc88a, 0x21, 0 + .dw 0x7040, 0xc88a, 0x707f, 0xc88a, 0x21, 0 + .dw 0x70c0, 0xc88a, 0x70ff, 0xc88a, 0x21, 0 + .dw 0x7140, 0xc88a, 0x717f, 0xc88a, 0x21, 0 + .dw 0x71c0, 0xc88a, 0x71ff, 0xc88a, 0x21, 0 + .dw 0x7240, 0xc88a, 0x727f, 0xc88a, 0x21, 0 + .dw 0x72c0, 0xc88a, 0x72ff, 0xc88a, 0x21, 0 + .dw 0x7340, 0xc88a, 0x737f, 0xc88a, 0x21, 0 + .dw 0x73c0, 0xc88a, 0x73ff, 0xc88a, 0x21, 0 + .dw 0x7440, 0xc88a, 0x747f, 0xc88a, 0x21, 0 + .dw 0x74c0, 0xc88a, 0x74ff, 0xc88a, 0x21, 0 + .dw 0x7540, 0xc88a, 0x757f, 0xc88a, 0x21, 0 + .dw 0x75c0, 0xc88a, 0x75ff, 0xc88a, 0x21, 0 + .dw 0x7640, 0xc88a, 0x767f, 0xc88a, 0x21, 0 + .dw 0x76c0, 0xc88a, 0x76ff, 0xc88a, 0x21, 0 + .dw 0x7740, 0xc88a, 0x777f, 0xc88a, 0x21, 0 + .dw 0x77c0, 0xc88a, 0x77ff, 0xc88a, 0x21, 0 + .dw 0x7840, 0xc88a, 0x787f, 0xc88a, 0x21, 0 + .dw 0x78c0, 0xc88a, 0x78ff, 0xc88a, 0x21, 0 + .dw 0x7940, 0xc88a, 0x797f, 0xc88a, 0x21, 0 + .dw 0x79c0, 0xc88a, 0x9fff, 0xc88a, 0x21, 0 + .dw 0xa040, 0xc88a, 0xa07f, 0xc88a, 0x21, 0 + .dw 0xa0c0, 0xc88a, 0xa0ff, 0xc88a, 0x21, 0 + .dw 0xa140, 0xc88a, 0xa17f, 0xc88a, 0x21, 0 + .dw 0xa1c0, 0xc88a, 0xa1ff, 0xc88a, 0x21, 0 + .dw 0xa240, 0xc88a, 0xa27f, 0xc88a, 0x21, 0 + .dw 0xa2c0, 0xc88a, 0xa2ff, 0xc88a, 0x21, 0 + .dw 0xa340, 0xc88a, 0xa37f, 0xc88a, 0x21, 0 + .dw 0xa3c0, 0xc88a, 0xa3ff, 0xc88a, 0x21, 0 + .dw 0xa440, 0xc88a, 0xa47f, 0xc88a, 0x21, 0 + .dw 0xa4c0, 0xc88a, 0xa4ff, 0xc88a, 0x21, 0 + .dw 0xa540, 0xc88a, 0xa57f, 0xc88a, 0x21, 0 + .dw 0xa5c0, 0xc88a, 0xa5ff, 0xc88a, 0x21, 0 + .dw 0xa640, 0xc88a, 0xa67f, 0xc88a, 0x21, 0 + .dw 0xa6c0, 0xc88a, 0xa6ff, 0xc88a, 0x21, 0 + .dw 0xa740, 0xc88a, 0xa77f, 0xc88a, 0x21, 0 + .dw 0xa7c0, 0xc88a, 0xa7ff, 0xc88a, 0x21, 0 + .dw 0xa840, 0xc88a, 0xa87f, 0xc88a, 0x21, 0 + .dw 0xa8c0, 0xc88a, 0xa8ff, 0xc88a, 0x21, 0 + .dw 0xa940, 0xc88a, 0xa97f, 0xc88a, 0x21, 0 + .dw 0xa9c0, 0xc88a, 0xa9ff, 0xc88a, 0x21, 0 + .dw 0xaa40, 0xc88a, 0xaa7f, 0xc88a, 0x21, 0 + .dw 0xaac0, 0xc88a, 0xaaff, 0xc88a, 0x21, 0 + .dw 0xab40, 0xc88a, 0xab7f, 0xc88a, 0x21, 0 + .dw 0xabc0, 0xc88a, 0xabff, 0xc88a, 0x21, 0 + .dw 0xac40, 0xc88a, 0xac7f, 0xc88a, 0x21, 0 + .dw 0xacc0, 0xc88a, 0xacff, 0xc88a, 0x21, 0 + .dw 0xad40, 0xc88a, 0xad7f, 0xc88a, 0x21, 0 + .dw 0xadc0, 0xc88a, 0xadff, 0xc88a, 0x21, 0 + .dw 0xae40, 0xc88a, 0xae7f, 0xc88a, 0x21, 0 + .dw 0xaec0, 0xc88a, 0xaeff, 0xc88a, 0x21, 0 + .dw 0xaf40, 0xc88a, 0xaf7f, 0xc88a, 0x21, 0 + .dw 0xafc0, 0xc88a, 0xafff, 0xc88a, 0x21, 0 + .dw 0xb040, 0xc88a, 0xb07f, 0xc88a, 0x21, 0 + .dw 0xb0c0, 0xc88a, 0xb0ff, 0xc88a, 0x21, 0 + .dw 0xb140, 0xc88a, 0xb17f, 0xc88a, 0x21, 0 + .dw 0xb1c0, 0xc88a, 0xb1ff, 0xc88a, 0x21, 0 + .dw 0xb240, 0xc88a, 0xb27f, 0xc88a, 0x21, 0 + .dw 0xb2c0, 0xc88a, 0xb2ff, 0xc88a, 0x21, 0 + .dw 0xb340, 0xc88a, 0xb37f, 0xc88a, 0x21, 0 + .dw 0xb3c0, 0xc88a, 0xb3ff, 0xc88a, 0x21, 0 + .dw 0xb440, 0xc88a, 0xb47f, 0xc88a, 0x21, 0 + .dw 0xb4c0, 0xc88a, 0xb4ff, 0xc88a, 0x21, 0 + .dw 0xb540, 0xc88a, 0xb57f, 0xc88a, 0x21, 0 + .dw 0xb5c0, 0xc88a, 0xb5ff, 0xc88a, 0x21, 0 + .dw 0xb640, 0xc88a, 0xb67f, 0xc88a, 0x21, 0 + .dw 0xb6c0, 0xc88a, 0xb6ff, 0xc88a, 0x21, 0 + .dw 0xb740, 0xc88a, 0xb77f, 0xc88a, 0x21, 0 + .dw 0xb7c0, 0xc88a, 0xb7ff, 0xc88a, 0x21, 0 + .dw 0xb840, 0xc88a, 0xb87f, 0xc88a, 0x21, 0 + .dw 0xb8c0, 0xc88a, 0xb8ff, 0xc88a, 0x21, 0 + .dw 0xb940, 0xc88a, 0xb97f, 0xc88a, 0x21, 0 + .dw 0xb9c0, 0xc88a, 0xdfff, 0xc88a, 0x21, 0 + .dw 0xe040, 0xc88a, 0xe07f, 0xc88a, 0x21, 0 + .dw 0xe0c0, 0xc88a, 0xe0ff, 0xc88a, 0x21, 0 + .dw 0xe140, 0xc88a, 0xe17f, 0xc88a, 0x21, 0 + .dw 0xe1c0, 0xc88a, 0xe1ff, 0xc88a, 0x21, 0 + .dw 0xe240, 0xc88a, 0xe27f, 0xc88a, 0x21, 0 + .dw 0xe2c0, 0xc88a, 0xe2ff, 0xc88a, 0x21, 0 + .dw 0xe340, 0xc88a, 0xe37f, 0xc88a, 0x21, 0 + .dw 0xe3c0, 0xc88a, 0xe3ff, 0xc88a, 0x21, 0 + .dw 0xe440, 0xc88a, 0xe47f, 0xc88a, 0x21, 0 + .dw 0xe4c0, 0xc88a, 0xe4ff, 0xc88a, 0x21, 0 + .dw 0xe540, 0xc88a, 0xe57f, 0xc88a, 0x21, 0 + .dw 0xe5c0, 0xc88a, 0xe5ff, 0xc88a, 0x21, 0 + .dw 0xe640, 0xc88a, 0xe67f, 0xc88a, 0x21, 0 + .dw 0xe6c0, 0xc88a, 0xe6ff, 0xc88a, 0x21, 0 + .dw 0xe740, 0xc88a, 0xe77f, 0xc88a, 0x21, 0 + .dw 0xe7c0, 0xc88a, 0xe7ff, 0xc88a, 0x21, 0 + .dw 0xe840, 0xc88a, 0xe87f, 0xc88a, 0x21, 0 + .dw 0xe8c0, 0xc88a, 0xe8ff, 0xc88a, 0x21, 0 + .dw 0xe940, 0xc88a, 0xe97f, 0xc88a, 0x21, 0 + .dw 0xe9c0, 0xc88a, 0xe9ff, 0xc88a, 0x21, 0 + .dw 0xea40, 0xc88a, 0xea7f, 0xc88a, 0x21, 0 + .dw 0xeac0, 0xc88a, 0xeaff, 0xc88a, 0x21, 0 + .dw 0xeb40, 0xc88a, 0xeb7f, 0xc88a, 0x21, 0 + .dw 0xebc0, 0xc88a, 0xebff, 0xc88a, 0x21, 0 + .dw 0xec40, 0xc88a, 0xec7f, 0xc88a, 0x21, 0 + .dw 0xecc0, 0xc88a, 0xecff, 0xc88a, 0x21, 0 + .dw 0xed40, 0xc88a, 0xed7f, 0xc88a, 0x21, 0 + .dw 0xedc0, 0xc88a, 0xedff, 0xc88a, 0x21, 0 + .dw 0xee40, 0xc88a, 0xee7f, 0xc88a, 0x21, 0 + .dw 0xeec0, 0xc88a, 0xeeff, 0xc88a, 0x21, 0 + .dw 0xef40, 0xc88a, 0xef7f, 0xc88a, 0x21, 0 + .dw 0xefc0, 0xc88a, 0xefff, 0xc88a, 0x21, 0 + .dw 0xf040, 0xc88a, 0xf07f, 0xc88a, 0x21, 0 + .dw 0xf0c0, 0xc88a, 0xf0ff, 0xc88a, 0x21, 0 + .dw 0xf140, 0xc88a, 0xf17f, 0xc88a, 0x21, 0 + .dw 0xf1c0, 0xc88a, 0xf1ff, 0xc88a, 0x21, 0 + .dw 0xf240, 0xc88a, 0xf27f, 0xc88a, 0x21, 0 + .dw 0xf2c0, 0xc88a, 0xf2ff, 0xc88a, 0x21, 0 + .dw 0xf340, 0xc88a, 0xf37f, 0xc88a, 0x21, 0 + .dw 0xf3c0, 0xc88a, 0xf3ff, 0xc88a, 0x21, 0 + .dw 0xf440, 0xc88a, 0xf47f, 0xc88a, 0x21, 0 + .dw 0xf4c0, 0xc88a, 0xf4ff, 0xc88a, 0x21, 0 + .dw 0xf540, 0xc88a, 0xf57f, 0xc88a, 0x21, 0 + .dw 0xf5c0, 0xc88a, 0xf5ff, 0xc88a, 0x21, 0 + .dw 0xf640, 0xc88a, 0xf67f, 0xc88a, 0x21, 0 + .dw 0xf6c0, 0xc88a, 0xf6ff, 0xc88a, 0x21, 0 + .dw 0xf740, 0xc88a, 0xf77f, 0xc88a, 0x21, 0 + .dw 0xf7c0, 0xc88a, 0xf7ff, 0xc88a, 0x21, 0 + .dw 0xf840, 0xc88a, 0xf87f, 0xc88a, 0x21, 0 + .dw 0xf8c0, 0xc88a, 0xf8ff, 0xc88a, 0x21, 0 + .dw 0xf940, 0xc88a, 0xf97f, 0xc88a, 0x21, 0 + .dw 0xf9c0, 0xc88a, 0x1fff, 0xc88b, 0x21, 0 + .dw 0x2040, 0xc88b, 0x207f, 0xc88b, 0x21, 0 + .dw 0x20c0, 0xc88b, 0x20ff, 0xc88b, 0x21, 0 + .dw 0x2140, 0xc88b, 0x217f, 0xc88b, 0x21, 0 + .dw 0x21c0, 0xc88b, 0x21ff, 0xc88b, 0x21, 0 + .dw 0x2240, 0xc88b, 0x227f, 0xc88b, 0x21, 0 + .dw 0x22c0, 0xc88b, 0x22ff, 0xc88b, 0x21, 0 + .dw 0x2340, 0xc88b, 0x237f, 0xc88b, 0x21, 0 + .dw 0x23c0, 0xc88b, 0x23ff, 0xc88b, 0x21, 0 + .dw 0x2440, 0xc88b, 0x247f, 0xc88b, 0x21, 0 + .dw 0x24c0, 0xc88b, 0x24ff, 0xc88b, 0x21, 0 + .dw 0x2540, 0xc88b, 0x257f, 0xc88b, 0x21, 0 + .dw 0x25c0, 0xc88b, 0x25ff, 0xc88b, 0x21, 0 + .dw 0x2640, 0xc88b, 0x267f, 0xc88b, 0x21, 0 + .dw 0x26c0, 0xc88b, 0x26ff, 0xc88b, 0x21, 0 + .dw 0x2740, 0xc88b, 0x277f, 0xc88b, 0x21, 0 + .dw 0x27c0, 0xc88b, 0x27ff, 0xc88b, 0x21, 0 + .dw 0x2840, 0xc88b, 0x287f, 0xc88b, 0x21, 0 + .dw 0x28c0, 0xc88b, 0x28ff, 0xc88b, 0x21, 0 + .dw 0x2940, 0xc88b, 0x297f, 0xc88b, 0x21, 0 + .dw 0x29c0, 0xc88b, 0x29ff, 0xc88b, 0x21, 0 + .dw 0x2a40, 0xc88b, 0x2a7f, 0xc88b, 0x21, 0 + .dw 0x2ac0, 0xc88b, 0x2aff, 0xc88b, 0x21, 0 + .dw 0x2b40, 0xc88b, 0x2b7f, 0xc88b, 0x21, 0 + .dw 0x2bc0, 0xc88b, 0x2bff, 0xc88b, 0x21, 0 + .dw 0x2c40, 0xc88b, 0x2c7f, 0xc88b, 0x21, 0 + .dw 0x2cc0, 0xc88b, 0x2cff, 0xc88b, 0x21, 0 + .dw 0x2d40, 0xc88b, 0x2d7f, 0xc88b, 0x21, 0 + .dw 0x2dc0, 0xc88b, 0x2dff, 0xc88b, 0x21, 0 + .dw 0x2e40, 0xc88b, 0x2e7f, 0xc88b, 0x21, 0 + .dw 0x2ec0, 0xc88b, 0x2eff, 0xc88b, 0x21, 0 + .dw 0x2f40, 0xc88b, 0x2f7f, 0xc88b, 0x21, 0 + .dw 0x2fc0, 0xc88b, 0x2fff, 0xc88b, 0x21, 0 + .dw 0x3040, 0xc88b, 0x307f, 0xc88b, 0x21, 0 + .dw 0x30c0, 0xc88b, 0x30ff, 0xc88b, 0x21, 0 + .dw 0x3140, 0xc88b, 0x317f, 0xc88b, 0x21, 0 + .dw 0x31c0, 0xc88b, 0x31ff, 0xc88b, 0x21, 0 + .dw 0x3240, 0xc88b, 0x327f, 0xc88b, 0x21, 0 + .dw 0x32c0, 0xc88b, 0x32ff, 0xc88b, 0x21, 0 + .dw 0x3340, 0xc88b, 0x337f, 0xc88b, 0x21, 0 + .dw 0x33c0, 0xc88b, 0x33ff, 0xc88b, 0x21, 0 + .dw 0x3440, 0xc88b, 0x347f, 0xc88b, 0x21, 0 + .dw 0x34c0, 0xc88b, 0x34ff, 0xc88b, 0x21, 0 + .dw 0x3540, 0xc88b, 0x357f, 0xc88b, 0x21, 0 + .dw 0x35c0, 0xc88b, 0x35ff, 0xc88b, 0x21, 0 + .dw 0x3640, 0xc88b, 0x367f, 0xc88b, 0x21, 0 + .dw 0x36c0, 0xc88b, 0x36ff, 0xc88b, 0x21, 0 + .dw 0x3740, 0xc88b, 0x377f, 0xc88b, 0x21, 0 + .dw 0x37c0, 0xc88b, 0x37ff, 0xc88b, 0x21, 0 + .dw 0x3840, 0xc88b, 0x387f, 0xc88b, 0x21, 0 + .dw 0x38c0, 0xc88b, 0x38ff, 0xc88b, 0x21, 0 + .dw 0x3940, 0xc88b, 0x397f, 0xc88b, 0x21, 0 + .dw 0x39c0, 0xc88b, 0xffff, 0xc88b, 0x21, 0 + .dw 0x0040, 0xc88c, 0x007f, 0xc88c, 0x21, 0 + .dw 0x00c0, 0xc88c, 0x00ff, 0xc88c, 0x21, 0 + .dw 0x0140, 0xc88c, 0x017f, 0xc88c, 0x21, 0 + .dw 0x01c0, 0xc88c, 0x01ff, 0xc88c, 0x21, 0 + .dw 0x0240, 0xc88c, 0x027f, 0xc88c, 0x21, 0 + .dw 0x02c0, 0xc88c, 0x02ff, 0xc88c, 0x21, 0 + .dw 0x0340, 0xc88c, 0x037f, 0xc88c, 0x21, 0 + .dw 0x03c0, 0xc88c, 0x03ff, 0xc88c, 0x21, 0 + .dw 0x0440, 0xc88c, 0x047f, 0xc88c, 0x21, 0 + .dw 0x04c0, 0xc88c, 0x04ff, 0xc88c, 0x21, 0 + .dw 0x0540, 0xc88c, 0x057f, 0xc88c, 0x21, 0 + .dw 0x05c0, 0xc88c, 0x05ff, 0xc88c, 0x21, 0 + .dw 0x0640, 0xc88c, 0x067f, 0xc88c, 0x21, 0 + .dw 0x06c0, 0xc88c, 0x06ff, 0xc88c, 0x21, 0 + .dw 0x0740, 0xc88c, 0x077f, 0xc88c, 0x21, 0 + .dw 0x07c0, 0xc88c, 0x07ff, 0xc88c, 0x21, 0 + .dw 0x0840, 0xc88c, 0x087f, 0xc88c, 0x21, 0 + .dw 0x08c0, 0xc88c, 0x08ff, 0xc88c, 0x21, 0 + .dw 0x0940, 0xc88c, 0x097f, 0xc88c, 0x21, 0 + .dw 0x09c0, 0xc88c, 0x09ff, 0xc88c, 0x21, 0 + .dw 0x0a40, 0xc88c, 0x0a7f, 0xc88c, 0x21, 0 + .dw 0x0ac0, 0xc88c, 0x0aff, 0xc88c, 0x21, 0 + .dw 0x0b40, 0xc88c, 0x0b7f, 0xc88c, 0x21, 0 + .dw 0x0bc0, 0xc88c, 0x0bff, 0xc88c, 0x21, 0 + .dw 0x0c40, 0xc88c, 0x0c7f, 0xc88c, 0x21, 0 + .dw 0x0cc0, 0xc88c, 0x0cff, 0xc88c, 0x21, 0 + .dw 0x0d40, 0xc88c, 0x0d7f, 0xc88c, 0x21, 0 + .dw 0x0dc0, 0xc88c, 0x0dff, 0xc88c, 0x21, 0 + .dw 0x0e40, 0xc88c, 0x0e7f, 0xc88c, 0x21, 0 + .dw 0x0ec0, 0xc88c, 0x0eff, 0xc88c, 0x21, 0 + .dw 0x0f40, 0xc88c, 0x0f7f, 0xc88c, 0x21, 0 + .dw 0x0fc0, 0xc88c, 0x0fff, 0xc88c, 0x21, 0 + .dw 0x1040, 0xc88c, 0x107f, 0xc88c, 0x21, 0 + .dw 0x10c0, 0xc88c, 0x10ff, 0xc88c, 0x21, 0 + .dw 0x1140, 0xc88c, 0x117f, 0xc88c, 0x21, 0 + .dw 0x11c0, 0xc88c, 0x11ff, 0xc88c, 0x21, 0 + .dw 0x1240, 0xc88c, 0x127f, 0xc88c, 0x21, 0 + .dw 0x12c0, 0xc88c, 0x12ff, 0xc88c, 0x21, 0 + .dw 0x1340, 0xc88c, 0x137f, 0xc88c, 0x21, 0 + .dw 0x13c0, 0xc88c, 0x13ff, 0xc88c, 0x21, 0 + .dw 0x1440, 0xc88c, 0x147f, 0xc88c, 0x21, 0 + .dw 0x14c0, 0xc88c, 0x14ff, 0xc88c, 0x21, 0 + .dw 0x1540, 0xc88c, 0x157f, 0xc88c, 0x21, 0 + .dw 0x15c0, 0xc88c, 0x15ff, 0xc88c, 0x21, 0 + .dw 0x1640, 0xc88c, 0x167f, 0xc88c, 0x21, 0 + .dw 0x16c0, 0xc88c, 0x16ff, 0xc88c, 0x21, 0 + .dw 0x1740, 0xc88c, 0x177f, 0xc88c, 0x21, 0 + .dw 0x17c0, 0xc88c, 0x17ff, 0xc88c, 0x21, 0 + .dw 0x1840, 0xc88c, 0x187f, 0xc88c, 0x21, 0 + .dw 0x18c0, 0xc88c, 0x18ff, 0xc88c, 0x21, 0 + .dw 0x1940, 0xc88c, 0x197f, 0xc88c, 0x21, 0 + .dw 0x19c0, 0xc88c, 0x1fff, 0xc88c, 0x21, 0 + .dw 0x2040, 0xc88c, 0x207f, 0xc88c, 0x21, 0 + .dw 0x20c0, 0xc88c, 0x20ff, 0xc88c, 0x21, 0 + .dw 0x2140, 0xc88c, 0x217f, 0xc88c, 0x21, 0 + .dw 0x21c0, 0xc88c, 0x21ff, 0xc88c, 0x21, 0 + .dw 0x2240, 0xc88c, 0x227f, 0xc88c, 0x21, 0 + .dw 0x22c0, 0xc88c, 0x22ff, 0xc88c, 0x21, 0 + .dw 0x2340, 0xc88c, 0x237f, 0xc88c, 0x21, 0 + .dw 0x23c0, 0xc88c, 0x23ff, 0xc88c, 0x21, 0 + .dw 0x2440, 0xc88c, 0x247f, 0xc88c, 0x21, 0 + .dw 0x24c0, 0xc88c, 0x24ff, 0xc88c, 0x21, 0 + .dw 0x2540, 0xc88c, 0x257f, 0xc88c, 0x21, 0 + .dw 0x25c0, 0xc88c, 0x25ff, 0xc88c, 0x21, 0 + .dw 0x2640, 0xc88c, 0x267f, 0xc88c, 0x21, 0 + .dw 0x26c0, 0xc88c, 0x26ff, 0xc88c, 0x21, 0 + .dw 0x2740, 0xc88c, 0x277f, 0xc88c, 0x21, 0 + .dw 0x27c0, 0xc88c, 0x27ff, 0xc88c, 0x21, 0 + .dw 0x2840, 0xc88c, 0x287f, 0xc88c, 0x21, 0 + .dw 0x28c0, 0xc88c, 0x28ff, 0xc88c, 0x21, 0 + .dw 0x2940, 0xc88c, 0x297f, 0xc88c, 0x21, 0 + .dw 0x29c0, 0xc88c, 0x29ff, 0xc88c, 0x21, 0 + .dw 0x2a40, 0xc88c, 0x2a7f, 0xc88c, 0x21, 0 + .dw 0x2ac0, 0xc88c, 0x2aff, 0xc88c, 0x21, 0 + .dw 0x2b40, 0xc88c, 0x2b7f, 0xc88c, 0x21, 0 + .dw 0x2bc0, 0xc88c, 0x2bff, 0xc88c, 0x21, 0 + .dw 0x2c40, 0xc88c, 0x2c7f, 0xc88c, 0x21, 0 + .dw 0x2cc0, 0xc88c, 0x2cff, 0xc88c, 0x21, 0 + .dw 0x2d40, 0xc88c, 0x2d7f, 0xc88c, 0x21, 0 + .dw 0x2dc0, 0xc88c, 0x2dff, 0xc88c, 0x21, 0 + .dw 0x2e40, 0xc88c, 0x2e7f, 0xc88c, 0x21, 0 + .dw 0x2ec0, 0xc88c, 0x2eff, 0xc88c, 0x21, 0 + .dw 0x2f40, 0xc88c, 0x2f7f, 0xc88c, 0x21, 0 + .dw 0x2fc0, 0xc88c, 0x2fff, 0xc88c, 0x21, 0 + .dw 0x3040, 0xc88c, 0x307f, 0xc88c, 0x21, 0 + .dw 0x30c0, 0xc88c, 0x30ff, 0xc88c, 0x21, 0 + .dw 0x3140, 0xc88c, 0x317f, 0xc88c, 0x21, 0 + .dw 0x31c0, 0xc88c, 0x31ff, 0xc88c, 0x21, 0 + .dw 0x3240, 0xc88c, 0x327f, 0xc88c, 0x21, 0 + .dw 0x32c0, 0xc88c, 0x32ff, 0xc88c, 0x21, 0 + .dw 0x3340, 0xc88c, 0x337f, 0xc88c, 0x21, 0 + .dw 0x33c0, 0xc88c, 0x33ff, 0xc88c, 0x21, 0 + .dw 0x3440, 0xc88c, 0x347f, 0xc88c, 0x21, 0 + .dw 0x34c0, 0xc88c, 0x34ff, 0xc88c, 0x21, 0 + .dw 0x3540, 0xc88c, 0x357f, 0xc88c, 0x21, 0 + .dw 0x35c0, 0xc88c, 0x35ff, 0xc88c, 0x21, 0 + .dw 0x3640, 0xc88c, 0x367f, 0xc88c, 0x21, 0 + .dw 0x36c0, 0xc88c, 0x36ff, 0xc88c, 0x21, 0 + .dw 0x3740, 0xc88c, 0x377f, 0xc88c, 0x21, 0 + .dw 0x37c0, 0xc88c, 0x37ff, 0xc88c, 0x21, 0 + .dw 0x3840, 0xc88c, 0x387f, 0xc88c, 0x21, 0 + .dw 0x38c0, 0xc88c, 0x38ff, 0xc88c, 0x21, 0 + .dw 0x3940, 0xc88c, 0x397f, 0xc88c, 0x21, 0 + .dw 0x39c0, 0xc88c, 0x3fff, 0xc88c, 0x21, 0 + .dw 0x4040, 0xc88c, 0x407f, 0xc88c, 0x21, 0 + .dw 0x40c0, 0xc88c, 0x40ff, 0xc88c, 0x21, 0 + .dw 0x4140, 0xc88c, 0x417f, 0xc88c, 0x21, 0 + .dw 0x41c0, 0xc88c, 0x41ff, 0xc88c, 0x21, 0 + .dw 0x4240, 0xc88c, 0x427f, 0xc88c, 0x21, 0 + .dw 0x42c0, 0xc88c, 0x42ff, 0xc88c, 0x21, 0 + .dw 0x4340, 0xc88c, 0x437f, 0xc88c, 0x21, 0 + .dw 0x43c0, 0xc88c, 0x43ff, 0xc88c, 0x21, 0 + .dw 0x4440, 0xc88c, 0x447f, 0xc88c, 0x21, 0 + .dw 0x44c0, 0xc88c, 0x44ff, 0xc88c, 0x21, 0 + .dw 0x4540, 0xc88c, 0x457f, 0xc88c, 0x21, 0 + .dw 0x45c0, 0xc88c, 0x45ff, 0xc88c, 0x21, 0 + .dw 0x4640, 0xc88c, 0x467f, 0xc88c, 0x21, 0 + .dw 0x46c0, 0xc88c, 0x46ff, 0xc88c, 0x21, 0 + .dw 0x4740, 0xc88c, 0x477f, 0xc88c, 0x21, 0 + .dw 0x47c0, 0xc88c, 0x47ff, 0xc88c, 0x21, 0 + .dw 0x4840, 0xc88c, 0x487f, 0xc88c, 0x21, 0 + .dw 0x48c0, 0xc88c, 0x48ff, 0xc88c, 0x21, 0 + .dw 0x4940, 0xc88c, 0x497f, 0xc88c, 0x21, 0 + .dw 0x49c0, 0xc88c, 0x49ff, 0xc88c, 0x21, 0 + .dw 0x4a40, 0xc88c, 0x4a7f, 0xc88c, 0x21, 0 + .dw 0x4ac0, 0xc88c, 0x4aff, 0xc88c, 0x21, 0 + .dw 0x4b40, 0xc88c, 0x4b7f, 0xc88c, 0x21, 0 + .dw 0x4bc0, 0xc88c, 0x4bff, 0xc88c, 0x21, 0 + .dw 0x4c40, 0xc88c, 0x4c7f, 0xc88c, 0x21, 0 + .dw 0x4cc0, 0xc88c, 0x4cff, 0xc88c, 0x21, 0 + .dw 0x4d40, 0xc88c, 0x4d7f, 0xc88c, 0x21, 0 + .dw 0x4dc0, 0xc88c, 0x4dff, 0xc88c, 0x21, 0 + .dw 0x4e40, 0xc88c, 0x4e7f, 0xc88c, 0x21, 0 + .dw 0x4ec0, 0xc88c, 0x4eff, 0xc88c, 0x21, 0 + .dw 0x4f40, 0xc88c, 0x4f7f, 0xc88c, 0x21, 0 + .dw 0x4fc0, 0xc88c, 0x4fff, 0xc88c, 0x21, 0 + .dw 0x5040, 0xc88c, 0x507f, 0xc88c, 0x21, 0 + .dw 0x50c0, 0xc88c, 0x50ff, 0xc88c, 0x21, 0 + .dw 0x5140, 0xc88c, 0x517f, 0xc88c, 0x21, 0 + .dw 0x51c0, 0xc88c, 0x51ff, 0xc88c, 0x21, 0 + .dw 0x5240, 0xc88c, 0x527f, 0xc88c, 0x21, 0 + .dw 0x52c0, 0xc88c, 0x52ff, 0xc88c, 0x21, 0 + .dw 0x5340, 0xc88c, 0x537f, 0xc88c, 0x21, 0 + .dw 0x53c0, 0xc88c, 0x53ff, 0xc88c, 0x21, 0 + .dw 0x5440, 0xc88c, 0x547f, 0xc88c, 0x21, 0 + .dw 0x54c0, 0xc88c, 0x54ff, 0xc88c, 0x21, 0 + .dw 0x5540, 0xc88c, 0x557f, 0xc88c, 0x21, 0 + .dw 0x55c0, 0xc88c, 0x55ff, 0xc88c, 0x21, 0 + .dw 0x5640, 0xc88c, 0x567f, 0xc88c, 0x21, 0 + .dw 0x56c0, 0xc88c, 0x56ff, 0xc88c, 0x21, 0 + .dw 0x5740, 0xc88c, 0x577f, 0xc88c, 0x21, 0 + .dw 0x57c0, 0xc88c, 0x57ff, 0xc88c, 0x21, 0 + .dw 0x5840, 0xc88c, 0x587f, 0xc88c, 0x21, 0 + .dw 0x58c0, 0xc88c, 0x58ff, 0xc88c, 0x21, 0 + .dw 0x5940, 0xc88c, 0x597f, 0xc88c, 0x21, 0 + .dw 0x59c0, 0xc88c, 0x5fff, 0xc88c, 0x21, 0 + .dw 0x6040, 0xc88c, 0x607f, 0xc88c, 0x21, 0 + .dw 0x60c0, 0xc88c, 0x60ff, 0xc88c, 0x21, 0 + .dw 0x6140, 0xc88c, 0x617f, 0xc88c, 0x21, 0 + .dw 0x61c0, 0xc88c, 0x61ff, 0xc88c, 0x21, 0 + .dw 0x6240, 0xc88c, 0x627f, 0xc88c, 0x21, 0 + .dw 0x62c0, 0xc88c, 0x62ff, 0xc88c, 0x21, 0 + .dw 0x6340, 0xc88c, 0x637f, 0xc88c, 0x21, 0 + .dw 0x63c0, 0xc88c, 0x63ff, 0xc88c, 0x21, 0 + .dw 0x6440, 0xc88c, 0x647f, 0xc88c, 0x21, 0 + .dw 0x64c0, 0xc88c, 0x64ff, 0xc88c, 0x21, 0 + .dw 0x6540, 0xc88c, 0x657f, 0xc88c, 0x21, 0 + .dw 0x65c0, 0xc88c, 0x65ff, 0xc88c, 0x21, 0 + .dw 0x6640, 0xc88c, 0x667f, 0xc88c, 0x21, 0 + .dw 0x66c0, 0xc88c, 0x66ff, 0xc88c, 0x21, 0 + .dw 0x6740, 0xc88c, 0x677f, 0xc88c, 0x21, 0 + .dw 0x67c0, 0xc88c, 0x67ff, 0xc88c, 0x21, 0 + .dw 0x6840, 0xc88c, 0x687f, 0xc88c, 0x21, 0 + .dw 0x68c0, 0xc88c, 0x68ff, 0xc88c, 0x21, 0 + .dw 0x6940, 0xc88c, 0x697f, 0xc88c, 0x21, 0 + .dw 0x69c0, 0xc88c, 0x69ff, 0xc88c, 0x21, 0 + .dw 0x6a40, 0xc88c, 0x6a7f, 0xc88c, 0x21, 0 + .dw 0x6ac0, 0xc88c, 0x6aff, 0xc88c, 0x21, 0 + .dw 0x6b40, 0xc88c, 0x6b7f, 0xc88c, 0x21, 0 + .dw 0x6bc0, 0xc88c, 0x6bff, 0xc88c, 0x21, 0 + .dw 0x6c40, 0xc88c, 0x6c7f, 0xc88c, 0x21, 0 + .dw 0x6cc0, 0xc88c, 0x6cff, 0xc88c, 0x21, 0 + .dw 0x6d40, 0xc88c, 0x6d7f, 0xc88c, 0x21, 0 + .dw 0x6dc0, 0xc88c, 0x6dff, 0xc88c, 0x21, 0 + .dw 0x6e40, 0xc88c, 0x6e7f, 0xc88c, 0x21, 0 + .dw 0x6ec0, 0xc88c, 0x6eff, 0xc88c, 0x21, 0 + .dw 0x6f40, 0xc88c, 0x6f7f, 0xc88c, 0x21, 0 + .dw 0x6fc0, 0xc88c, 0x6fff, 0xc88c, 0x21, 0 + .dw 0x7040, 0xc88c, 0x707f, 0xc88c, 0x21, 0 + .dw 0x70c0, 0xc88c, 0x70ff, 0xc88c, 0x21, 0 + .dw 0x7140, 0xc88c, 0x717f, 0xc88c, 0x21, 0 + .dw 0x71c0, 0xc88c, 0x71ff, 0xc88c, 0x21, 0 + .dw 0x7240, 0xc88c, 0x727f, 0xc88c, 0x21, 0 + .dw 0x72c0, 0xc88c, 0x72ff, 0xc88c, 0x21, 0 + .dw 0x7340, 0xc88c, 0x737f, 0xc88c, 0x21, 0 + .dw 0x73c0, 0xc88c, 0x73ff, 0xc88c, 0x21, 0 + .dw 0x7440, 0xc88c, 0x747f, 0xc88c, 0x21, 0 + .dw 0x74c0, 0xc88c, 0x74ff, 0xc88c, 0x21, 0 + .dw 0x7540, 0xc88c, 0x757f, 0xc88c, 0x21, 0 + .dw 0x75c0, 0xc88c, 0x75ff, 0xc88c, 0x21, 0 + .dw 0x7640, 0xc88c, 0x767f, 0xc88c, 0x21, 0 + .dw 0x76c0, 0xc88c, 0x76ff, 0xc88c, 0x21, 0 + .dw 0x7740, 0xc88c, 0x777f, 0xc88c, 0x21, 0 + .dw 0x77c0, 0xc88c, 0x77ff, 0xc88c, 0x21, 0 + .dw 0x7840, 0xc88c, 0x787f, 0xc88c, 0x21, 0 + .dw 0x78c0, 0xc88c, 0x78ff, 0xc88c, 0x21, 0 + .dw 0x7940, 0xc88c, 0x797f, 0xc88c, 0x21, 0 + .dw 0x79c0, 0xc88c, 0x7fff, 0xc88c, 0x21, 0 + .dw 0x8040, 0xc88c, 0x807f, 0xc88c, 0x21, 0 + .dw 0x80c0, 0xc88c, 0x80ff, 0xc88c, 0x21, 0 + .dw 0x8140, 0xc88c, 0x817f, 0xc88c, 0x21, 0 + .dw 0x81c0, 0xc88c, 0x81ff, 0xc88c, 0x21, 0 + .dw 0x8240, 0xc88c, 0x827f, 0xc88c, 0x21, 0 + .dw 0x82c0, 0xc88c, 0x82ff, 0xc88c, 0x21, 0 + .dw 0x8340, 0xc88c, 0x837f, 0xc88c, 0x21, 0 + .dw 0x83c0, 0xc88c, 0x83ff, 0xc88c, 0x21, 0 + .dw 0x8440, 0xc88c, 0x847f, 0xc88c, 0x21, 0 + .dw 0x84c0, 0xc88c, 0x84ff, 0xc88c, 0x21, 0 + .dw 0x8540, 0xc88c, 0x857f, 0xc88c, 0x21, 0 + .dw 0x85c0, 0xc88c, 0x85ff, 0xc88c, 0x21, 0 + .dw 0x8640, 0xc88c, 0x867f, 0xc88c, 0x21, 0 + .dw 0x86c0, 0xc88c, 0x86ff, 0xc88c, 0x21, 0 + .dw 0x8740, 0xc88c, 0x877f, 0xc88c, 0x21, 0 + .dw 0x87c0, 0xc88c, 0x87ff, 0xc88c, 0x21, 0 + .dw 0x8840, 0xc88c, 0x887f, 0xc88c, 0x21, 0 + .dw 0x88c0, 0xc88c, 0x88ff, 0xc88c, 0x21, 0 + .dw 0x8940, 0xc88c, 0x897f, 0xc88c, 0x21, 0 + .dw 0x89c0, 0xc88c, 0x89ff, 0xc88c, 0x21, 0 + .dw 0x8a40, 0xc88c, 0x8a7f, 0xc88c, 0x21, 0 + .dw 0x8ac0, 0xc88c, 0x8aff, 0xc88c, 0x21, 0 + .dw 0x8b40, 0xc88c, 0x8b7f, 0xc88c, 0x21, 0 + .dw 0x8bc0, 0xc88c, 0x8bff, 0xc88c, 0x21, 0 + .dw 0x8c40, 0xc88c, 0x8c7f, 0xc88c, 0x21, 0 + .dw 0x8cc0, 0xc88c, 0x8cff, 0xc88c, 0x21, 0 + .dw 0x8d40, 0xc88c, 0x8d7f, 0xc88c, 0x21, 0 + .dw 0x8dc0, 0xc88c, 0x8dff, 0xc88c, 0x21, 0 + .dw 0x8e40, 0xc88c, 0x8e7f, 0xc88c, 0x21, 0 + .dw 0x8ec0, 0xc88c, 0x8eff, 0xc88c, 0x21, 0 + .dw 0x8f40, 0xc88c, 0x8f7f, 0xc88c, 0x21, 0 + .dw 0x8fc0, 0xc88c, 0x8fff, 0xc88c, 0x21, 0 + .dw 0x9040, 0xc88c, 0x907f, 0xc88c, 0x21, 0 + .dw 0x90c0, 0xc88c, 0x90ff, 0xc88c, 0x21, 0 + .dw 0x9140, 0xc88c, 0x917f, 0xc88c, 0x21, 0 + .dw 0x91c0, 0xc88c, 0x91ff, 0xc88c, 0x21, 0 + .dw 0x9240, 0xc88c, 0x927f, 0xc88c, 0x21, 0 + .dw 0x92c0, 0xc88c, 0x92ff, 0xc88c, 0x21, 0 + .dw 0x9340, 0xc88c, 0x937f, 0xc88c, 0x21, 0 + .dw 0x93c0, 0xc88c, 0x93ff, 0xc88c, 0x21, 0 + .dw 0x9440, 0xc88c, 0x947f, 0xc88c, 0x21, 0 + .dw 0x94c0, 0xc88c, 0x94ff, 0xc88c, 0x21, 0 + .dw 0x9540, 0xc88c, 0x957f, 0xc88c, 0x21, 0 + .dw 0x95c0, 0xc88c, 0x95ff, 0xc88c, 0x21, 0 + .dw 0x9640, 0xc88c, 0x967f, 0xc88c, 0x21, 0 + .dw 0x96c0, 0xc88c, 0x96ff, 0xc88c, 0x21, 0 + .dw 0x9740, 0xc88c, 0x977f, 0xc88c, 0x21, 0 + .dw 0x97c0, 0xc88c, 0x97ff, 0xc88c, 0x21, 0 + .dw 0x9840, 0xc88c, 0x987f, 0xc88c, 0x21, 0 + .dw 0x98c0, 0xc88c, 0x98ff, 0xc88c, 0x21, 0 + .dw 0x9940, 0xc88c, 0x997f, 0xc88c, 0x21, 0 + .dw 0x99c0, 0xc88c, 0x9fff, 0xc88c, 0x21, 0 + .dw 0xa040, 0xc88c, 0xa07f, 0xc88c, 0x21, 0 + .dw 0xa0c0, 0xc88c, 0xa0ff, 0xc88c, 0x21, 0 + .dw 0xa140, 0xc88c, 0xa17f, 0xc88c, 0x21, 0 + .dw 0xa1c0, 0xc88c, 0xa1ff, 0xc88c, 0x21, 0 + .dw 0xa240, 0xc88c, 0xa27f, 0xc88c, 0x21, 0 + .dw 0xa2c0, 0xc88c, 0xa2ff, 0xc88c, 0x21, 0 + .dw 0xa340, 0xc88c, 0xa37f, 0xc88c, 0x21, 0 + .dw 0xa3c0, 0xc88c, 0xa3ff, 0xc88c, 0x21, 0 + .dw 0xa440, 0xc88c, 0xa47f, 0xc88c, 0x21, 0 + .dw 0xa4c0, 0xc88c, 0xa4ff, 0xc88c, 0x21, 0 + .dw 0xa540, 0xc88c, 0xa57f, 0xc88c, 0x21, 0 + .dw 0xa5c0, 0xc88c, 0xa5ff, 0xc88c, 0x21, 0 + .dw 0xa640, 0xc88c, 0xa67f, 0xc88c, 0x21, 0 + .dw 0xa6c0, 0xc88c, 0xa6ff, 0xc88c, 0x21, 0 + .dw 0xa740, 0xc88c, 0xa77f, 0xc88c, 0x21, 0 + .dw 0xa7c0, 0xc88c, 0xa7ff, 0xc88c, 0x21, 0 + .dw 0xa840, 0xc88c, 0xa87f, 0xc88c, 0x21, 0 + .dw 0xa8c0, 0xc88c, 0xa8ff, 0xc88c, 0x21, 0 + .dw 0xa940, 0xc88c, 0xa97f, 0xc88c, 0x21, 0 + .dw 0xa9c0, 0xc88c, 0xa9ff, 0xc88c, 0x21, 0 + .dw 0xaa40, 0xc88c, 0xaa7f, 0xc88c, 0x21, 0 + .dw 0xaac0, 0xc88c, 0xaaff, 0xc88c, 0x21, 0 + .dw 0xab40, 0xc88c, 0xab7f, 0xc88c, 0x21, 0 + .dw 0xabc0, 0xc88c, 0xabff, 0xc88c, 0x21, 0 + .dw 0xac40, 0xc88c, 0xac7f, 0xc88c, 0x21, 0 + .dw 0xacc0, 0xc88c, 0xacff, 0xc88c, 0x21, 0 + .dw 0xad40, 0xc88c, 0xad7f, 0xc88c, 0x21, 0 + .dw 0xadc0, 0xc88c, 0xadff, 0xc88c, 0x21, 0 + .dw 0xae40, 0xc88c, 0xae7f, 0xc88c, 0x21, 0 + .dw 0xaec0, 0xc88c, 0xaeff, 0xc88c, 0x21, 0 + .dw 0xaf40, 0xc88c, 0xaf7f, 0xc88c, 0x21, 0 + .dw 0xafc0, 0xc88c, 0xafff, 0xc88c, 0x21, 0 + .dw 0xb040, 0xc88c, 0xb07f, 0xc88c, 0x21, 0 + .dw 0xb0c0, 0xc88c, 0xb0ff, 0xc88c, 0x21, 0 + .dw 0xb140, 0xc88c, 0xb17f, 0xc88c, 0x21, 0 + .dw 0xb1c0, 0xc88c, 0xb1ff, 0xc88c, 0x21, 0 + .dw 0xb240, 0xc88c, 0xb27f, 0xc88c, 0x21, 0 + .dw 0xb2c0, 0xc88c, 0xb2ff, 0xc88c, 0x21, 0 + .dw 0xb340, 0xc88c, 0xb37f, 0xc88c, 0x21, 0 + .dw 0xb3c0, 0xc88c, 0xb3ff, 0xc88c, 0x21, 0 + .dw 0xb440, 0xc88c, 0xb47f, 0xc88c, 0x21, 0 + .dw 0xb4c0, 0xc88c, 0xb4ff, 0xc88c, 0x21, 0 + .dw 0xb540, 0xc88c, 0xb57f, 0xc88c, 0x21, 0 + .dw 0xb5c0, 0xc88c, 0xb5ff, 0xc88c, 0x21, 0 + .dw 0xb640, 0xc88c, 0xb67f, 0xc88c, 0x21, 0 + .dw 0xb6c0, 0xc88c, 0xb6ff, 0xc88c, 0x21, 0 + .dw 0xb740, 0xc88c, 0xb77f, 0xc88c, 0x21, 0 + .dw 0xb7c0, 0xc88c, 0xb7ff, 0xc88c, 0x21, 0 + .dw 0xb840, 0xc88c, 0xb87f, 0xc88c, 0x21, 0 + .dw 0xb8c0, 0xc88c, 0xb8ff, 0xc88c, 0x21, 0 + .dw 0xb940, 0xc88c, 0xb97f, 0xc88c, 0x21, 0 + .dw 0xb9c0, 0xc88c, 0xbfff, 0xc88c, 0x21, 0 + .dw 0xc040, 0xc88c, 0xc07f, 0xc88c, 0x21, 0 + .dw 0xc0c0, 0xc88c, 0xc0ff, 0xc88c, 0x21, 0 + .dw 0xc140, 0xc88c, 0xc17f, 0xc88c, 0x21, 0 + .dw 0xc1c0, 0xc88c, 0xc1ff, 0xc88c, 0x21, 0 + .dw 0xc240, 0xc88c, 0xc27f, 0xc88c, 0x21, 0 + .dw 0xc2c0, 0xc88c, 0xc2ff, 0xc88c, 0x21, 0 + .dw 0xc340, 0xc88c, 0xc37f, 0xc88c, 0x21, 0 + .dw 0xc3c0, 0xc88c, 0xc3ff, 0xc88c, 0x21, 0 + .dw 0xc440, 0xc88c, 0xc47f, 0xc88c, 0x21, 0 + .dw 0xc4c0, 0xc88c, 0xc4ff, 0xc88c, 0x21, 0 + .dw 0xc540, 0xc88c, 0xc57f, 0xc88c, 0x21, 0 + .dw 0xc5c0, 0xc88c, 0xc5ff, 0xc88c, 0x21, 0 + .dw 0xc640, 0xc88c, 0xc67f, 0xc88c, 0x21, 0 + .dw 0xc6c0, 0xc88c, 0xc6ff, 0xc88c, 0x21, 0 + .dw 0xc740, 0xc88c, 0xc77f, 0xc88c, 0x21, 0 + .dw 0xc7c0, 0xc88c, 0xc7ff, 0xc88c, 0x21, 0 + .dw 0xc840, 0xc88c, 0xc87f, 0xc88c, 0x21, 0 + .dw 0xc8c0, 0xc88c, 0xc8ff, 0xc88c, 0x21, 0 + .dw 0xc940, 0xc88c, 0xc97f, 0xc88c, 0x21, 0 + .dw 0xc9c0, 0xc88c, 0xc9ff, 0xc88c, 0x21, 0 + .dw 0xca40, 0xc88c, 0xca7f, 0xc88c, 0x21, 0 + .dw 0xcac0, 0xc88c, 0xcaff, 0xc88c, 0x21, 0 + .dw 0xcb40, 0xc88c, 0xcb7f, 0xc88c, 0x21, 0 + .dw 0xcbc0, 0xc88c, 0xcbff, 0xc88c, 0x21, 0 + .dw 0xcc40, 0xc88c, 0xcc7f, 0xc88c, 0x21, 0 + .dw 0xccc0, 0xc88c, 0xccff, 0xc88c, 0x21, 0 + .dw 0xcd40, 0xc88c, 0xcd7f, 0xc88c, 0x21, 0 + .dw 0xcdc0, 0xc88c, 0xcdff, 0xc88c, 0x21, 0 + .dw 0xce40, 0xc88c, 0xce7f, 0xc88c, 0x21, 0 + .dw 0xcec0, 0xc88c, 0xceff, 0xc88c, 0x21, 0 + .dw 0xcf40, 0xc88c, 0xcf7f, 0xc88c, 0x21, 0 + .dw 0xcfc0, 0xc88c, 0xcfff, 0xc88c, 0x21, 0 + .dw 0xd040, 0xc88c, 0xd07f, 0xc88c, 0x21, 0 + .dw 0xd0c0, 0xc88c, 0xd0ff, 0xc88c, 0x21, 0 + .dw 0xd140, 0xc88c, 0xd17f, 0xc88c, 0x21, 0 + .dw 0xd1c0, 0xc88c, 0xd1ff, 0xc88c, 0x21, 0 + .dw 0xd240, 0xc88c, 0xd27f, 0xc88c, 0x21, 0 + .dw 0xd2c0, 0xc88c, 0xd2ff, 0xc88c, 0x21, 0 + .dw 0xd340, 0xc88c, 0xd37f, 0xc88c, 0x21, 0 + .dw 0xd3c0, 0xc88c, 0xd3ff, 0xc88c, 0x21, 0 + .dw 0xd440, 0xc88c, 0xd47f, 0xc88c, 0x21, 0 + .dw 0xd4c0, 0xc88c, 0xd4ff, 0xc88c, 0x21, 0 + .dw 0xd540, 0xc88c, 0xd57f, 0xc88c, 0x21, 0 + .dw 0xd5c0, 0xc88c, 0xd5ff, 0xc88c, 0x21, 0 + .dw 0xd640, 0xc88c, 0xd67f, 0xc88c, 0x21, 0 + .dw 0xd6c0, 0xc88c, 0xd6ff, 0xc88c, 0x21, 0 + .dw 0xd740, 0xc88c, 0xd77f, 0xc88c, 0x21, 0 + .dw 0xd7c0, 0xc88c, 0xd7ff, 0xc88c, 0x21, 0 + .dw 0xd840, 0xc88c, 0xd87f, 0xc88c, 0x21, 0 + .dw 0xd8c0, 0xc88c, 0xd8ff, 0xc88c, 0x21, 0 + .dw 0xd940, 0xc88c, 0xd97f, 0xc88c, 0x21, 0 + .dw 0xd9c0, 0xc88c, 0xdfff, 0xc88c, 0x21, 0 + .dw 0xe040, 0xc88c, 0xe07f, 0xc88c, 0x21, 0 + .dw 0xe0c0, 0xc88c, 0xe0ff, 0xc88c, 0x21, 0 + .dw 0xe140, 0xc88c, 0xe17f, 0xc88c, 0x21, 0 + .dw 0xe1c0, 0xc88c, 0xe1ff, 0xc88c, 0x21, 0 + .dw 0xe240, 0xc88c, 0xe27f, 0xc88c, 0x21, 0 + .dw 0xe2c0, 0xc88c, 0xe2ff, 0xc88c, 0x21, 0 + .dw 0xe340, 0xc88c, 0xe37f, 0xc88c, 0x21, 0 + .dw 0xe3c0, 0xc88c, 0xe3ff, 0xc88c, 0x21, 0 + .dw 0xe440, 0xc88c, 0xe47f, 0xc88c, 0x21, 0 + .dw 0xe4c0, 0xc88c, 0xe4ff, 0xc88c, 0x21, 0 + .dw 0xe540, 0xc88c, 0xe57f, 0xc88c, 0x21, 0 + .dw 0xe5c0, 0xc88c, 0xe5ff, 0xc88c, 0x21, 0 + .dw 0xe640, 0xc88c, 0xe67f, 0xc88c, 0x21, 0 + .dw 0xe6c0, 0xc88c, 0xe6ff, 0xc88c, 0x21, 0 + .dw 0xe740, 0xc88c, 0xe77f, 0xc88c, 0x21, 0 + .dw 0xe7c0, 0xc88c, 0xe7ff, 0xc88c, 0x21, 0 + .dw 0xe840, 0xc88c, 0xe87f, 0xc88c, 0x21, 0 + .dw 0xe8c0, 0xc88c, 0xe8ff, 0xc88c, 0x21, 0 + .dw 0xe940, 0xc88c, 0xe97f, 0xc88c, 0x21, 0 + .dw 0xe9c0, 0xc88c, 0xe9ff, 0xc88c, 0x21, 0 + .dw 0xea40, 0xc88c, 0xea7f, 0xc88c, 0x21, 0 + .dw 0xeac0, 0xc88c, 0xeaff, 0xc88c, 0x21, 0 + .dw 0xeb40, 0xc88c, 0xeb7f, 0xc88c, 0x21, 0 + .dw 0xebc0, 0xc88c, 0xebff, 0xc88c, 0x21, 0 + .dw 0xec40, 0xc88c, 0xec7f, 0xc88c, 0x21, 0 + .dw 0xecc0, 0xc88c, 0xecff, 0xc88c, 0x21, 0 + .dw 0xed40, 0xc88c, 0xed7f, 0xc88c, 0x21, 0 + .dw 0xedc0, 0xc88c, 0xedff, 0xc88c, 0x21, 0 + .dw 0xee40, 0xc88c, 0xee7f, 0xc88c, 0x21, 0 + .dw 0xeec0, 0xc88c, 0xeeff, 0xc88c, 0x21, 0 + .dw 0xef40, 0xc88c, 0xef7f, 0xc88c, 0x21, 0 + .dw 0xefc0, 0xc88c, 0xefff, 0xc88c, 0x21, 0 + .dw 0xf040, 0xc88c, 0xf07f, 0xc88c, 0x21, 0 + .dw 0xf0c0, 0xc88c, 0xf0ff, 0xc88c, 0x21, 0 + .dw 0xf140, 0xc88c, 0xf17f, 0xc88c, 0x21, 0 + .dw 0xf1c0, 0xc88c, 0xf1ff, 0xc88c, 0x21, 0 + .dw 0xf240, 0xc88c, 0xf27f, 0xc88c, 0x21, 0 + .dw 0xf2c0, 0xc88c, 0xf2ff, 0xc88c, 0x21, 0 + .dw 0xf340, 0xc88c, 0xf37f, 0xc88c, 0x21, 0 + .dw 0xf3c0, 0xc88c, 0xf3ff, 0xc88c, 0x21, 0 + .dw 0xf440, 0xc88c, 0xf47f, 0xc88c, 0x21, 0 + .dw 0xf4c0, 0xc88c, 0xf4ff, 0xc88c, 0x21, 0 + .dw 0xf540, 0xc88c, 0xf57f, 0xc88c, 0x21, 0 + .dw 0xf5c0, 0xc88c, 0xf5ff, 0xc88c, 0x21, 0 + .dw 0xf640, 0xc88c, 0xf67f, 0xc88c, 0x21, 0 + .dw 0xf6c0, 0xc88c, 0xf6ff, 0xc88c, 0x21, 0 + .dw 0xf740, 0xc88c, 0xf77f, 0xc88c, 0x21, 0 + .dw 0xf7c0, 0xc88c, 0xf7ff, 0xc88c, 0x21, 0 + .dw 0xf840, 0xc88c, 0xf87f, 0xc88c, 0x21, 0 + .dw 0xf8c0, 0xc88c, 0xf8ff, 0xc88c, 0x21, 0 + .dw 0xf940, 0xc88c, 0xf97f, 0xc88c, 0x21, 0 + .dw 0xf9c0, 0xc88c, 0xffff, 0xc88c, 0x21, 0 + .dw 0x0040, 0xc88d, 0x007f, 0xc88d, 0x21, 0 + .dw 0x00c0, 0xc88d, 0x00ff, 0xc88d, 0x21, 0 + .dw 0x0140, 0xc88d, 0x017f, 0xc88d, 0x21, 0 + .dw 0x01c0, 0xc88d, 0x01ff, 0xc88d, 0x21, 0 + .dw 0x0240, 0xc88d, 0x027f, 0xc88d, 0x21, 0 + .dw 0x02c0, 0xc88d, 0x02ff, 0xc88d, 0x21, 0 + .dw 0x0340, 0xc88d, 0x037f, 0xc88d, 0x21, 0 + .dw 0x03c0, 0xc88d, 0x03ff, 0xc88d, 0x21, 0 + .dw 0x0440, 0xc88d, 0x047f, 0xc88d, 0x21, 0 + .dw 0x04c0, 0xc88d, 0x04ff, 0xc88d, 0x21, 0 + .dw 0x0540, 0xc88d, 0x057f, 0xc88d, 0x21, 0 + .dw 0x05c0, 0xc88d, 0x05ff, 0xc88d, 0x21, 0 + .dw 0x0640, 0xc88d, 0x067f, 0xc88d, 0x21, 0 + .dw 0x06c0, 0xc88d, 0x06ff, 0xc88d, 0x21, 0 + .dw 0x0740, 0xc88d, 0x077f, 0xc88d, 0x21, 0 + .dw 0x07c0, 0xc88d, 0x07ff, 0xc88d, 0x21, 0 + .dw 0x0840, 0xc88d, 0x087f, 0xc88d, 0x21, 0 + .dw 0x08c0, 0xc88d, 0x08ff, 0xc88d, 0x21, 0 + .dw 0x0940, 0xc88d, 0x097f, 0xc88d, 0x21, 0 + .dw 0x09c0, 0xc88d, 0x09ff, 0xc88d, 0x21, 0 + .dw 0x0a40, 0xc88d, 0x0a7f, 0xc88d, 0x21, 0 + .dw 0x0ac0, 0xc88d, 0x0aff, 0xc88d, 0x21, 0 + .dw 0x0b40, 0xc88d, 0x0b7f, 0xc88d, 0x21, 0 + .dw 0x0bc0, 0xc88d, 0x0bff, 0xc88d, 0x21, 0 + .dw 0x0c40, 0xc88d, 0x0c7f, 0xc88d, 0x21, 0 + .dw 0x0cc0, 0xc88d, 0x0cff, 0xc88d, 0x21, 0 + .dw 0x0d40, 0xc88d, 0x0d7f, 0xc88d, 0x21, 0 + .dw 0x0dc0, 0xc88d, 0x0dff, 0xc88d, 0x21, 0 + .dw 0x0e40, 0xc88d, 0x0e7f, 0xc88d, 0x21, 0 + .dw 0x0ec0, 0xc88d, 0x0eff, 0xc88d, 0x21, 0 + .dw 0x0f40, 0xc88d, 0x0f7f, 0xc88d, 0x21, 0 + .dw 0x0fc0, 0xc88d, 0x0fff, 0xc88d, 0x21, 0 + .dw 0x1040, 0xc88d, 0x107f, 0xc88d, 0x21, 0 + .dw 0x10c0, 0xc88d, 0x10ff, 0xc88d, 0x21, 0 + .dw 0x1140, 0xc88d, 0x117f, 0xc88d, 0x21, 0 + .dw 0x11c0, 0xc88d, 0x11ff, 0xc88d, 0x21, 0 + .dw 0x1240, 0xc88d, 0x127f, 0xc88d, 0x21, 0 + .dw 0x12c0, 0xc88d, 0x12ff, 0xc88d, 0x21, 0 + .dw 0x1340, 0xc88d, 0x137f, 0xc88d, 0x21, 0 + .dw 0x13c0, 0xc88d, 0x13ff, 0xc88d, 0x21, 0 + .dw 0x1440, 0xc88d, 0x147f, 0xc88d, 0x21, 0 + .dw 0x14c0, 0xc88d, 0x14ff, 0xc88d, 0x21, 0 + .dw 0x1540, 0xc88d, 0x157f, 0xc88d, 0x21, 0 + .dw 0x15c0, 0xc88d, 0x15ff, 0xc88d, 0x21, 0 + .dw 0x1640, 0xc88d, 0x167f, 0xc88d, 0x21, 0 + .dw 0x16c0, 0xc88d, 0x16ff, 0xc88d, 0x21, 0 + .dw 0x1740, 0xc88d, 0x177f, 0xc88d, 0x21, 0 + .dw 0x17c0, 0xc88d, 0x17ff, 0xc88d, 0x21, 0 + .dw 0x1840, 0xc88d, 0x187f, 0xc88d, 0x21, 0 + .dw 0x18c0, 0xc88d, 0x18ff, 0xc88d, 0x21, 0 + .dw 0x1940, 0xc88d, 0x197f, 0xc88d, 0x21, 0 + .dw 0x19c0, 0xc88d, 0x1fff, 0xc88d, 0x21, 0 + .dw 0x2040, 0xc88d, 0x207f, 0xc88d, 0x21, 0 + .dw 0x20c0, 0xc88d, 0x20ff, 0xc88d, 0x21, 0 + .dw 0x2140, 0xc88d, 0x217f, 0xc88d, 0x21, 0 + .dw 0x21c0, 0xc88d, 0x21ff, 0xc88d, 0x21, 0 + .dw 0x2240, 0xc88d, 0x227f, 0xc88d, 0x21, 0 + .dw 0x22c0, 0xc88d, 0x22ff, 0xc88d, 0x21, 0 + .dw 0x2340, 0xc88d, 0x237f, 0xc88d, 0x21, 0 + .dw 0x23c0, 0xc88d, 0x23ff, 0xc88d, 0x21, 0 + .dw 0x2440, 0xc88d, 0x247f, 0xc88d, 0x21, 0 + .dw 0x24c0, 0xc88d, 0x24ff, 0xc88d, 0x21, 0 + .dw 0x2540, 0xc88d, 0x257f, 0xc88d, 0x21, 0 + .dw 0x25c0, 0xc88d, 0x25ff, 0xc88d, 0x21, 0 + .dw 0x2640, 0xc88d, 0x267f, 0xc88d, 0x21, 0 + .dw 0x26c0, 0xc88d, 0x26ff, 0xc88d, 0x21, 0 + .dw 0x2740, 0xc88d, 0x277f, 0xc88d, 0x21, 0 + .dw 0x27c0, 0xc88d, 0x27ff, 0xc88d, 0x21, 0 + .dw 0x2840, 0xc88d, 0x287f, 0xc88d, 0x21, 0 + .dw 0x28c0, 0xc88d, 0x28ff, 0xc88d, 0x21, 0 + .dw 0x2940, 0xc88d, 0x297f, 0xc88d, 0x21, 0 + .dw 0x29c0, 0xc88d, 0x29ff, 0xc88d, 0x21, 0 + .dw 0x2a40, 0xc88d, 0x2a7f, 0xc88d, 0x21, 0 + .dw 0x2ac0, 0xc88d, 0x2aff, 0xc88d, 0x21, 0 + .dw 0x2b40, 0xc88d, 0x2b7f, 0xc88d, 0x21, 0 + .dw 0x2bc0, 0xc88d, 0x2bff, 0xc88d, 0x21, 0 + .dw 0x2c40, 0xc88d, 0x2c7f, 0xc88d, 0x21, 0 + .dw 0x2cc0, 0xc88d, 0x2cff, 0xc88d, 0x21, 0 + .dw 0x2d40, 0xc88d, 0x2d7f, 0xc88d, 0x21, 0 + .dw 0x2dc0, 0xc88d, 0x2dff, 0xc88d, 0x21, 0 + .dw 0x2e40, 0xc88d, 0x2e7f, 0xc88d, 0x21, 0 + .dw 0x2ec0, 0xc88d, 0x2eff, 0xc88d, 0x21, 0 + .dw 0x2f40, 0xc88d, 0x2f7f, 0xc88d, 0x21, 0 + .dw 0x2fc0, 0xc88d, 0x2fff, 0xc88d, 0x21, 0 + .dw 0x3040, 0xc88d, 0x307f, 0xc88d, 0x21, 0 + .dw 0x30c0, 0xc88d, 0x30ff, 0xc88d, 0x21, 0 + .dw 0x3140, 0xc88d, 0x317f, 0xc88d, 0x21, 0 + .dw 0x31c0, 0xc88d, 0x31ff, 0xc88d, 0x21, 0 + .dw 0x3240, 0xc88d, 0x327f, 0xc88d, 0x21, 0 + .dw 0x32c0, 0xc88d, 0x32ff, 0xc88d, 0x21, 0 + .dw 0x3340, 0xc88d, 0x337f, 0xc88d, 0x21, 0 + .dw 0x33c0, 0xc88d, 0x33ff, 0xc88d, 0x21, 0 + .dw 0x3440, 0xc88d, 0x347f, 0xc88d, 0x21, 0 + .dw 0x34c0, 0xc88d, 0x34ff, 0xc88d, 0x21, 0 + .dw 0x3540, 0xc88d, 0x357f, 0xc88d, 0x21, 0 + .dw 0x35c0, 0xc88d, 0x35ff, 0xc88d, 0x21, 0 + .dw 0x3640, 0xc88d, 0x367f, 0xc88d, 0x21, 0 + .dw 0x36c0, 0xc88d, 0x36ff, 0xc88d, 0x21, 0 + .dw 0x3740, 0xc88d, 0x377f, 0xc88d, 0x21, 0 + .dw 0x37c0, 0xc88d, 0x37ff, 0xc88d, 0x21, 0 + .dw 0x3840, 0xc88d, 0x387f, 0xc88d, 0x21, 0 + .dw 0x38c0, 0xc88d, 0x38ff, 0xc88d, 0x21, 0 + .dw 0x3940, 0xc88d, 0x397f, 0xc88d, 0x21, 0 + .dw 0x39c0, 0xc88d, 0x3fff, 0xc88d, 0x21, 0 + .dw 0x4040, 0xc88d, 0x407f, 0xc88d, 0x21, 0 + .dw 0x40c0, 0xc88d, 0x40ff, 0xc88d, 0x21, 0 + .dw 0x4140, 0xc88d, 0x417f, 0xc88d, 0x21, 0 + .dw 0x41c0, 0xc88d, 0x41ff, 0xc88d, 0x21, 0 + .dw 0x4240, 0xc88d, 0x427f, 0xc88d, 0x21, 0 + .dw 0x42c0, 0xc88d, 0x42ff, 0xc88d, 0x21, 0 + .dw 0x4340, 0xc88d, 0x437f, 0xc88d, 0x21, 0 + .dw 0x43c0, 0xc88d, 0x43ff, 0xc88d, 0x21, 0 + .dw 0x4440, 0xc88d, 0x447f, 0xc88d, 0x21, 0 + .dw 0x44c0, 0xc88d, 0x44ff, 0xc88d, 0x21, 0 + .dw 0x4540, 0xc88d, 0x457f, 0xc88d, 0x21, 0 + .dw 0x45c0, 0xc88d, 0x45ff, 0xc88d, 0x21, 0 + .dw 0x4640, 0xc88d, 0x467f, 0xc88d, 0x21, 0 + .dw 0x46c0, 0xc88d, 0x46ff, 0xc88d, 0x21, 0 + .dw 0x4740, 0xc88d, 0x477f, 0xc88d, 0x21, 0 + .dw 0x47c0, 0xc88d, 0x47ff, 0xc88d, 0x21, 0 + .dw 0x4840, 0xc88d, 0x487f, 0xc88d, 0x21, 0 + .dw 0x48c0, 0xc88d, 0x48ff, 0xc88d, 0x21, 0 + .dw 0x4940, 0xc88d, 0x497f, 0xc88d, 0x21, 0 + .dw 0x49c0, 0xc88d, 0x49ff, 0xc88d, 0x21, 0 + .dw 0x4a40, 0xc88d, 0x4a7f, 0xc88d, 0x21, 0 + .dw 0x4ac0, 0xc88d, 0x4aff, 0xc88d, 0x21, 0 + .dw 0x4b40, 0xc88d, 0x4b7f, 0xc88d, 0x21, 0 + .dw 0x4bc0, 0xc88d, 0x4bff, 0xc88d, 0x21, 0 + .dw 0x4c40, 0xc88d, 0x4c7f, 0xc88d, 0x21, 0 + .dw 0x4cc0, 0xc88d, 0x4cff, 0xc88d, 0x21, 0 + .dw 0x4d40, 0xc88d, 0x4d7f, 0xc88d, 0x21, 0 + .dw 0x4dc0, 0xc88d, 0x4dff, 0xc88d, 0x21, 0 + .dw 0x4e40, 0xc88d, 0x4e7f, 0xc88d, 0x21, 0 + .dw 0x4ec0, 0xc88d, 0x4eff, 0xc88d, 0x21, 0 + .dw 0x4f40, 0xc88d, 0x4f7f, 0xc88d, 0x21, 0 + .dw 0x4fc0, 0xc88d, 0x4fff, 0xc88d, 0x21, 0 + .dw 0x5040, 0xc88d, 0x507f, 0xc88d, 0x21, 0 + .dw 0x50c0, 0xc88d, 0x50ff, 0xc88d, 0x21, 0 + .dw 0x5140, 0xc88d, 0x517f, 0xc88d, 0x21, 0 + .dw 0x51c0, 0xc88d, 0x51ff, 0xc88d, 0x21, 0 + .dw 0x5240, 0xc88d, 0x527f, 0xc88d, 0x21, 0 + .dw 0x52c0, 0xc88d, 0x52ff, 0xc88d, 0x21, 0 + .dw 0x5340, 0xc88d, 0x537f, 0xc88d, 0x21, 0 + .dw 0x53c0, 0xc88d, 0x53ff, 0xc88d, 0x21, 0 + .dw 0x5440, 0xc88d, 0x547f, 0xc88d, 0x21, 0 + .dw 0x54c0, 0xc88d, 0x54ff, 0xc88d, 0x21, 0 + .dw 0x5540, 0xc88d, 0x557f, 0xc88d, 0x21, 0 + .dw 0x55c0, 0xc88d, 0x55ff, 0xc88d, 0x21, 0 + .dw 0x5640, 0xc88d, 0x567f, 0xc88d, 0x21, 0 + .dw 0x56c0, 0xc88d, 0x56ff, 0xc88d, 0x21, 0 + .dw 0x5740, 0xc88d, 0x577f, 0xc88d, 0x21, 0 + .dw 0x57c0, 0xc88d, 0x57ff, 0xc88d, 0x21, 0 + .dw 0x5840, 0xc88d, 0x587f, 0xc88d, 0x21, 0 + .dw 0x58c0, 0xc88d, 0x58ff, 0xc88d, 0x21, 0 + .dw 0x5940, 0xc88d, 0x597f, 0xc88d, 0x21, 0 + .dw 0x59c0, 0xc88d, 0x5fff, 0xc88d, 0x21, 0 + .dw 0x6040, 0xc88d, 0x607f, 0xc88d, 0x21, 0 + .dw 0x60c0, 0xc88d, 0x60ff, 0xc88d, 0x21, 0 + .dw 0x6140, 0xc88d, 0x617f, 0xc88d, 0x21, 0 + .dw 0x61c0, 0xc88d, 0x61ff, 0xc88d, 0x21, 0 + .dw 0x6240, 0xc88d, 0x627f, 0xc88d, 0x21, 0 + .dw 0x62c0, 0xc88d, 0x62ff, 0xc88d, 0x21, 0 + .dw 0x6340, 0xc88d, 0x637f, 0xc88d, 0x21, 0 + .dw 0x63c0, 0xc88d, 0x63ff, 0xc88d, 0x21, 0 + .dw 0x6440, 0xc88d, 0x647f, 0xc88d, 0x21, 0 + .dw 0x64c0, 0xc88d, 0x64ff, 0xc88d, 0x21, 0 + .dw 0x6540, 0xc88d, 0x657f, 0xc88d, 0x21, 0 + .dw 0x65c0, 0xc88d, 0x65ff, 0xc88d, 0x21, 0 + .dw 0x6640, 0xc88d, 0x667f, 0xc88d, 0x21, 0 + .dw 0x66c0, 0xc88d, 0x66ff, 0xc88d, 0x21, 0 + .dw 0x6740, 0xc88d, 0x677f, 0xc88d, 0x21, 0 + .dw 0x67c0, 0xc88d, 0x67ff, 0xc88d, 0x21, 0 + .dw 0x6840, 0xc88d, 0x687f, 0xc88d, 0x21, 0 + .dw 0x68c0, 0xc88d, 0x68ff, 0xc88d, 0x21, 0 + .dw 0x6940, 0xc88d, 0x697f, 0xc88d, 0x21, 0 + .dw 0x69c0, 0xc88d, 0x69ff, 0xc88d, 0x21, 0 + .dw 0x6a40, 0xc88d, 0x6a7f, 0xc88d, 0x21, 0 + .dw 0x6ac0, 0xc88d, 0x6aff, 0xc88d, 0x21, 0 + .dw 0x6b40, 0xc88d, 0x6b7f, 0xc88d, 0x21, 0 + .dw 0x6bc0, 0xc88d, 0x6bff, 0xc88d, 0x21, 0 + .dw 0x6c40, 0xc88d, 0x6c7f, 0xc88d, 0x21, 0 + .dw 0x6cc0, 0xc88d, 0x6cff, 0xc88d, 0x21, 0 + .dw 0x6d40, 0xc88d, 0x6d7f, 0xc88d, 0x21, 0 + .dw 0x6dc0, 0xc88d, 0x6dff, 0xc88d, 0x21, 0 + .dw 0x6e40, 0xc88d, 0x6e7f, 0xc88d, 0x21, 0 + .dw 0x6ec0, 0xc88d, 0x6eff, 0xc88d, 0x21, 0 + .dw 0x6f40, 0xc88d, 0x6f7f, 0xc88d, 0x21, 0 + .dw 0x6fc0, 0xc88d, 0x6fff, 0xc88d, 0x21, 0 + .dw 0x7040, 0xc88d, 0x707f, 0xc88d, 0x21, 0 + .dw 0x70c0, 0xc88d, 0x70ff, 0xc88d, 0x21, 0 + .dw 0x7140, 0xc88d, 0x717f, 0xc88d, 0x21, 0 + .dw 0x71c0, 0xc88d, 0x71ff, 0xc88d, 0x21, 0 + .dw 0x7240, 0xc88d, 0x727f, 0xc88d, 0x21, 0 + .dw 0x72c0, 0xc88d, 0x72ff, 0xc88d, 0x21, 0 + .dw 0x7340, 0xc88d, 0x737f, 0xc88d, 0x21, 0 + .dw 0x73c0, 0xc88d, 0x73ff, 0xc88d, 0x21, 0 + .dw 0x7440, 0xc88d, 0x747f, 0xc88d, 0x21, 0 + .dw 0x74c0, 0xc88d, 0x74ff, 0xc88d, 0x21, 0 + .dw 0x7540, 0xc88d, 0x757f, 0xc88d, 0x21, 0 + .dw 0x75c0, 0xc88d, 0x75ff, 0xc88d, 0x21, 0 + .dw 0x7640, 0xc88d, 0x767f, 0xc88d, 0x21, 0 + .dw 0x76c0, 0xc88d, 0x76ff, 0xc88d, 0x21, 0 + .dw 0x7740, 0xc88d, 0x777f, 0xc88d, 0x21, 0 + .dw 0x77c0, 0xc88d, 0x77ff, 0xc88d, 0x21, 0 + .dw 0x7840, 0xc88d, 0x787f, 0xc88d, 0x21, 0 + .dw 0x78c0, 0xc88d, 0x78ff, 0xc88d, 0x21, 0 + .dw 0x7940, 0xc88d, 0x797f, 0xc88d, 0x21, 0 + .dw 0x79c0, 0xc88d, 0x7fff, 0xc88d, 0x21, 0 + .dw 0x8040, 0xc88d, 0x807f, 0xc88d, 0x21, 0 + .dw 0x80c0, 0xc88d, 0x80ff, 0xc88d, 0x21, 0 + .dw 0x8140, 0xc88d, 0x817f, 0xc88d, 0x21, 0 + .dw 0x81c0, 0xc88d, 0x81ff, 0xc88d, 0x21, 0 + .dw 0x8240, 0xc88d, 0x827f, 0xc88d, 0x21, 0 + .dw 0x82c0, 0xc88d, 0x82ff, 0xc88d, 0x21, 0 + .dw 0x8340, 0xc88d, 0x837f, 0xc88d, 0x21, 0 + .dw 0x83c0, 0xc88d, 0x83ff, 0xc88d, 0x21, 0 + .dw 0x8440, 0xc88d, 0x847f, 0xc88d, 0x21, 0 + .dw 0x84c0, 0xc88d, 0x84ff, 0xc88d, 0x21, 0 + .dw 0x8540, 0xc88d, 0x857f, 0xc88d, 0x21, 0 + .dw 0x85c0, 0xc88d, 0x85ff, 0xc88d, 0x21, 0 + .dw 0x8640, 0xc88d, 0x867f, 0xc88d, 0x21, 0 + .dw 0x86c0, 0xc88d, 0x86ff, 0xc88d, 0x21, 0 + .dw 0x8740, 0xc88d, 0x877f, 0xc88d, 0x21, 0 + .dw 0x87c0, 0xc88d, 0x87ff, 0xc88d, 0x21, 0 + .dw 0x8840, 0xc88d, 0x887f, 0xc88d, 0x21, 0 + .dw 0x88c0, 0xc88d, 0x88ff, 0xc88d, 0x21, 0 + .dw 0x8940, 0xc88d, 0x897f, 0xc88d, 0x21, 0 + .dw 0x89c0, 0xc88d, 0x89ff, 0xc88d, 0x21, 0 + .dw 0x8a40, 0xc88d, 0x8a7f, 0xc88d, 0x21, 0 + .dw 0x8ac0, 0xc88d, 0x8aff, 0xc88d, 0x21, 0 + .dw 0x8b40, 0xc88d, 0x8b7f, 0xc88d, 0x21, 0 + .dw 0x8bc0, 0xc88d, 0x8bff, 0xc88d, 0x21, 0 + .dw 0x8c40, 0xc88d, 0x8c7f, 0xc88d, 0x21, 0 + .dw 0x8cc0, 0xc88d, 0x8cff, 0xc88d, 0x21, 0 + .dw 0x8d40, 0xc88d, 0x8d7f, 0xc88d, 0x21, 0 + .dw 0x8dc0, 0xc88d, 0x8dff, 0xc88d, 0x21, 0 + .dw 0x8e40, 0xc88d, 0x8e7f, 0xc88d, 0x21, 0 + .dw 0x8ec0, 0xc88d, 0x8eff, 0xc88d, 0x21, 0 + .dw 0x8f40, 0xc88d, 0x8f7f, 0xc88d, 0x21, 0 + .dw 0x8fc0, 0xc88d, 0x8fff, 0xc88d, 0x21, 0 + .dw 0x9040, 0xc88d, 0x907f, 0xc88d, 0x21, 0 + .dw 0x90c0, 0xc88d, 0x90ff, 0xc88d, 0x21, 0 + .dw 0x9140, 0xc88d, 0x917f, 0xc88d, 0x21, 0 + .dw 0x91c0, 0xc88d, 0x91ff, 0xc88d, 0x21, 0 + .dw 0x9240, 0xc88d, 0x927f, 0xc88d, 0x21, 0 + .dw 0x92c0, 0xc88d, 0x92ff, 0xc88d, 0x21, 0 + .dw 0x9340, 0xc88d, 0x937f, 0xc88d, 0x21, 0 + .dw 0x93c0, 0xc88d, 0x93ff, 0xc88d, 0x21, 0 + .dw 0x9440, 0xc88d, 0x947f, 0xc88d, 0x21, 0 + .dw 0x94c0, 0xc88d, 0x94ff, 0xc88d, 0x21, 0 + .dw 0x9540, 0xc88d, 0x957f, 0xc88d, 0x21, 0 + .dw 0x95c0, 0xc88d, 0x95ff, 0xc88d, 0x21, 0 + .dw 0x9640, 0xc88d, 0x967f, 0xc88d, 0x21, 0 + .dw 0x96c0, 0xc88d, 0x96ff, 0xc88d, 0x21, 0 + .dw 0x9740, 0xc88d, 0x977f, 0xc88d, 0x21, 0 + .dw 0x97c0, 0xc88d, 0x97ff, 0xc88d, 0x21, 0 + .dw 0x9840, 0xc88d, 0x987f, 0xc88d, 0x21, 0 + .dw 0x98c0, 0xc88d, 0x98ff, 0xc88d, 0x21, 0 + .dw 0x9940, 0xc88d, 0x997f, 0xc88d, 0x21, 0 + .dw 0x99c0, 0xc88d, 0x9fff, 0xc88d, 0x21, 0 + .dw 0xa040, 0xc88d, 0xa07f, 0xc88d, 0x21, 0 + .dw 0xa0c0, 0xc88d, 0xa0ff, 0xc88d, 0x21, 0 + .dw 0xa140, 0xc88d, 0xa17f, 0xc88d, 0x21, 0 + .dw 0xa1c0, 0xc88d, 0xa1ff, 0xc88d, 0x21, 0 + .dw 0xa240, 0xc88d, 0xa27f, 0xc88d, 0x21, 0 + .dw 0xa2c0, 0xc88d, 0xa2ff, 0xc88d, 0x21, 0 + .dw 0xa340, 0xc88d, 0xa37f, 0xc88d, 0x21, 0 + .dw 0xa3c0, 0xc88d, 0xa3ff, 0xc88d, 0x21, 0 + .dw 0xa440, 0xc88d, 0xa47f, 0xc88d, 0x21, 0 + .dw 0xa4c0, 0xc88d, 0xa4ff, 0xc88d, 0x21, 0 + .dw 0xa540, 0xc88d, 0xa57f, 0xc88d, 0x21, 0 + .dw 0xa5c0, 0xc88d, 0xa5ff, 0xc88d, 0x21, 0 + .dw 0xa640, 0xc88d, 0xa67f, 0xc88d, 0x21, 0 + .dw 0xa6c0, 0xc88d, 0xa6ff, 0xc88d, 0x21, 0 + .dw 0xa740, 0xc88d, 0xa77f, 0xc88d, 0x21, 0 + .dw 0xa7c0, 0xc88d, 0xa7ff, 0xc88d, 0x21, 0 + .dw 0xa840, 0xc88d, 0xa87f, 0xc88d, 0x21, 0 + .dw 0xa8c0, 0xc88d, 0xa8ff, 0xc88d, 0x21, 0 + .dw 0xa940, 0xc88d, 0xa97f, 0xc88d, 0x21, 0 + .dw 0xa9c0, 0xc88d, 0xa9ff, 0xc88d, 0x21, 0 + .dw 0xaa40, 0xc88d, 0xaa7f, 0xc88d, 0x21, 0 + .dw 0xaac0, 0xc88d, 0xaaff, 0xc88d, 0x21, 0 + .dw 0xab40, 0xc88d, 0xab7f, 0xc88d, 0x21, 0 + .dw 0xabc0, 0xc88d, 0xabff, 0xc88d, 0x21, 0 + .dw 0xac40, 0xc88d, 0xac7f, 0xc88d, 0x21, 0 + .dw 0xacc0, 0xc88d, 0xacff, 0xc88d, 0x21, 0 + .dw 0xad40, 0xc88d, 0xad7f, 0xc88d, 0x21, 0 + .dw 0xadc0, 0xc88d, 0xadff, 0xc88d, 0x21, 0 + .dw 0xae40, 0xc88d, 0xae7f, 0xc88d, 0x21, 0 + .dw 0xaec0, 0xc88d, 0xaeff, 0xc88d, 0x21, 0 + .dw 0xaf40, 0xc88d, 0xaf7f, 0xc88d, 0x21, 0 + .dw 0xafc0, 0xc88d, 0xafff, 0xc88d, 0x21, 0 + .dw 0xb040, 0xc88d, 0xb07f, 0xc88d, 0x21, 0 + .dw 0xb0c0, 0xc88d, 0xb0ff, 0xc88d, 0x21, 0 + .dw 0xb140, 0xc88d, 0xb17f, 0xc88d, 0x21, 0 + .dw 0xb1c0, 0xc88d, 0xb1ff, 0xc88d, 0x21, 0 + .dw 0xb240, 0xc88d, 0xb27f, 0xc88d, 0x21, 0 + .dw 0xb2c0, 0xc88d, 0xb2ff, 0xc88d, 0x21, 0 + .dw 0xb340, 0xc88d, 0xb37f, 0xc88d, 0x21, 0 + .dw 0xb3c0, 0xc88d, 0xb3ff, 0xc88d, 0x21, 0 + .dw 0xb440, 0xc88d, 0xb47f, 0xc88d, 0x21, 0 + .dw 0xb4c0, 0xc88d, 0xb4ff, 0xc88d, 0x21, 0 + .dw 0xb540, 0xc88d, 0xb57f, 0xc88d, 0x21, 0 + .dw 0xb5c0, 0xc88d, 0xb5ff, 0xc88d, 0x21, 0 + .dw 0xb640, 0xc88d, 0xb67f, 0xc88d, 0x21, 0 + .dw 0xb6c0, 0xc88d, 0xb6ff, 0xc88d, 0x21, 0 + .dw 0xb740, 0xc88d, 0xb77f, 0xc88d, 0x21, 0 + .dw 0xb7c0, 0xc88d, 0xb7ff, 0xc88d, 0x21, 0 + .dw 0xb840, 0xc88d, 0xb87f, 0xc88d, 0x21, 0 + .dw 0xb8c0, 0xc88d, 0xb8ff, 0xc88d, 0x21, 0 + .dw 0xb940, 0xc88d, 0xb97f, 0xc88d, 0x21, 0 + .dw 0xb9c0, 0xc88d, 0xbfff, 0xc88d, 0x21, 0 + .dw 0xc040, 0xc88d, 0xc07f, 0xc88d, 0x21, 0 + .dw 0xc0c0, 0xc88d, 0xc0ff, 0xc88d, 0x21, 0 + .dw 0xc140, 0xc88d, 0xc17f, 0xc88d, 0x21, 0 + .dw 0xc1c0, 0xc88d, 0xc1ff, 0xc88d, 0x21, 0 + .dw 0xc240, 0xc88d, 0xc27f, 0xc88d, 0x21, 0 + .dw 0xc2c0, 0xc88d, 0xc2ff, 0xc88d, 0x21, 0 + .dw 0xc340, 0xc88d, 0xc37f, 0xc88d, 0x21, 0 + .dw 0xc3c0, 0xc88d, 0xc3ff, 0xc88d, 0x21, 0 + .dw 0xc440, 0xc88d, 0xc47f, 0xc88d, 0x21, 0 + .dw 0xc4c0, 0xc88d, 0xc4ff, 0xc88d, 0x21, 0 + .dw 0xc540, 0xc88d, 0xc57f, 0xc88d, 0x21, 0 + .dw 0xc5c0, 0xc88d, 0xc5ff, 0xc88d, 0x21, 0 + .dw 0xc640, 0xc88d, 0xc67f, 0xc88d, 0x21, 0 + .dw 0xc6c0, 0xc88d, 0xc6ff, 0xc88d, 0x21, 0 + .dw 0xc740, 0xc88d, 0xc77f, 0xc88d, 0x21, 0 + .dw 0xc7c0, 0xc88d, 0xc7ff, 0xc88d, 0x21, 0 + .dw 0xc840, 0xc88d, 0xc87f, 0xc88d, 0x21, 0 + .dw 0xc8c0, 0xc88d, 0xc8ff, 0xc88d, 0x21, 0 + .dw 0xc940, 0xc88d, 0xc97f, 0xc88d, 0x21, 0 + .dw 0xc9c0, 0xc88d, 0xc9ff, 0xc88d, 0x21, 0 + .dw 0xca40, 0xc88d, 0xca7f, 0xc88d, 0x21, 0 + .dw 0xcac0, 0xc88d, 0xcaff, 0xc88d, 0x21, 0 + .dw 0xcb40, 0xc88d, 0xcb7f, 0xc88d, 0x21, 0 + .dw 0xcbc0, 0xc88d, 0xcbff, 0xc88d, 0x21, 0 + .dw 0xcc40, 0xc88d, 0xcc7f, 0xc88d, 0x21, 0 + .dw 0xccc0, 0xc88d, 0xccff, 0xc88d, 0x21, 0 + .dw 0xcd40, 0xc88d, 0xcd7f, 0xc88d, 0x21, 0 + .dw 0xcdc0, 0xc88d, 0xcdff, 0xc88d, 0x21, 0 + .dw 0xce40, 0xc88d, 0xce7f, 0xc88d, 0x21, 0 + .dw 0xcec0, 0xc88d, 0xceff, 0xc88d, 0x21, 0 + .dw 0xcf40, 0xc88d, 0xcf7f, 0xc88d, 0x21, 0 + .dw 0xcfc0, 0xc88d, 0xcfff, 0xc88d, 0x21, 0 + .dw 0xd040, 0xc88d, 0xd07f, 0xc88d, 0x21, 0 + .dw 0xd0c0, 0xc88d, 0xd0ff, 0xc88d, 0x21, 0 + .dw 0xd140, 0xc88d, 0xd17f, 0xc88d, 0x21, 0 + .dw 0xd1c0, 0xc88d, 0xd1ff, 0xc88d, 0x21, 0 + .dw 0xd240, 0xc88d, 0xd27f, 0xc88d, 0x21, 0 + .dw 0xd2c0, 0xc88d, 0xd2ff, 0xc88d, 0x21, 0 + .dw 0xd340, 0xc88d, 0xd37f, 0xc88d, 0x21, 0 + .dw 0xd3c0, 0xc88d, 0xd3ff, 0xc88d, 0x21, 0 + .dw 0xd440, 0xc88d, 0xd47f, 0xc88d, 0x21, 0 + .dw 0xd4c0, 0xc88d, 0xd4ff, 0xc88d, 0x21, 0 + .dw 0xd540, 0xc88d, 0xd57f, 0xc88d, 0x21, 0 + .dw 0xd5c0, 0xc88d, 0xd5ff, 0xc88d, 0x21, 0 + .dw 0xd640, 0xc88d, 0xd67f, 0xc88d, 0x21, 0 + .dw 0xd6c0, 0xc88d, 0xd6ff, 0xc88d, 0x21, 0 + .dw 0xd740, 0xc88d, 0xd77f, 0xc88d, 0x21, 0 + .dw 0xd7c0, 0xc88d, 0xd7ff, 0xc88d, 0x21, 0 + .dw 0xd840, 0xc88d, 0xd87f, 0xc88d, 0x21, 0 + .dw 0xd8c0, 0xc88d, 0xd8ff, 0xc88d, 0x21, 0 + .dw 0xd940, 0xc88d, 0xd97f, 0xc88d, 0x21, 0 + .dw 0xd9c0, 0xc88d, 0xdfff, 0xc88d, 0x21, 0 + .dw 0xe040, 0xc88d, 0xe07f, 0xc88d, 0x21, 0 + .dw 0xe0c0, 0xc88d, 0xe0ff, 0xc88d, 0x21, 0 + .dw 0xe140, 0xc88d, 0xe17f, 0xc88d, 0x21, 0 + .dw 0xe1c0, 0xc88d, 0xe1ff, 0xc88d, 0x21, 0 + .dw 0xe240, 0xc88d, 0xe27f, 0xc88d, 0x21, 0 + .dw 0xe2c0, 0xc88d, 0xe2ff, 0xc88d, 0x21, 0 + .dw 0xe340, 0xc88d, 0xe37f, 0xc88d, 0x21, 0 + .dw 0xe3c0, 0xc88d, 0xe3ff, 0xc88d, 0x21, 0 + .dw 0xe440, 0xc88d, 0xe47f, 0xc88d, 0x21, 0 + .dw 0xe4c0, 0xc88d, 0xe4ff, 0xc88d, 0x21, 0 + .dw 0xe540, 0xc88d, 0xe57f, 0xc88d, 0x21, 0 + .dw 0xe5c0, 0xc88d, 0xe5ff, 0xc88d, 0x21, 0 + .dw 0xe640, 0xc88d, 0xe67f, 0xc88d, 0x21, 0 + .dw 0xe6c0, 0xc88d, 0xe6ff, 0xc88d, 0x21, 0 + .dw 0xe740, 0xc88d, 0xe77f, 0xc88d, 0x21, 0 + .dw 0xe7c0, 0xc88d, 0xe7ff, 0xc88d, 0x21, 0 + .dw 0xe840, 0xc88d, 0xe87f, 0xc88d, 0x21, 0 + .dw 0xe8c0, 0xc88d, 0xe8ff, 0xc88d, 0x21, 0 + .dw 0xe940, 0xc88d, 0xe97f, 0xc88d, 0x21, 0 + .dw 0xe9c0, 0xc88d, 0xe9ff, 0xc88d, 0x21, 0 + .dw 0xea40, 0xc88d, 0xea7f, 0xc88d, 0x21, 0 + .dw 0xeac0, 0xc88d, 0xeaff, 0xc88d, 0x21, 0 + .dw 0xeb40, 0xc88d, 0xeb7f, 0xc88d, 0x21, 0 + .dw 0xebc0, 0xc88d, 0xebff, 0xc88d, 0x21, 0 + .dw 0xec40, 0xc88d, 0xec7f, 0xc88d, 0x21, 0 + .dw 0xecc0, 0xc88d, 0xecff, 0xc88d, 0x21, 0 + .dw 0xed40, 0xc88d, 0xed7f, 0xc88d, 0x21, 0 + .dw 0xedc0, 0xc88d, 0xedff, 0xc88d, 0x21, 0 + .dw 0xee40, 0xc88d, 0xee7f, 0xc88d, 0x21, 0 + .dw 0xeec0, 0xc88d, 0xeeff, 0xc88d, 0x21, 0 + .dw 0xef40, 0xc88d, 0xef7f, 0xc88d, 0x21, 0 + .dw 0xefc0, 0xc88d, 0xefff, 0xc88d, 0x21, 0 + .dw 0xf040, 0xc88d, 0xf07f, 0xc88d, 0x21, 0 + .dw 0xf0c0, 0xc88d, 0xf0ff, 0xc88d, 0x21, 0 + .dw 0xf140, 0xc88d, 0xf17f, 0xc88d, 0x21, 0 + .dw 0xf1c0, 0xc88d, 0xf1ff, 0xc88d, 0x21, 0 + .dw 0xf240, 0xc88d, 0xf27f, 0xc88d, 0x21, 0 + .dw 0xf2c0, 0xc88d, 0xf2ff, 0xc88d, 0x21, 0 + .dw 0xf340, 0xc88d, 0xf37f, 0xc88d, 0x21, 0 + .dw 0xf3c0, 0xc88d, 0xf3ff, 0xc88d, 0x21, 0 + .dw 0xf440, 0xc88d, 0xf47f, 0xc88d, 0x21, 0 + .dw 0xf4c0, 0xc88d, 0xf4ff, 0xc88d, 0x21, 0 + .dw 0xf540, 0xc88d, 0xf57f, 0xc88d, 0x21, 0 + .dw 0xf5c0, 0xc88d, 0xf5ff, 0xc88d, 0x21, 0 + .dw 0xf640, 0xc88d, 0xf67f, 0xc88d, 0x21, 0 + .dw 0xf6c0, 0xc88d, 0xf6ff, 0xc88d, 0x21, 0 + .dw 0xf740, 0xc88d, 0xf77f, 0xc88d, 0x21, 0 + .dw 0xf7c0, 0xc88d, 0xf7ff, 0xc88d, 0x21, 0 + .dw 0xf840, 0xc88d, 0xf87f, 0xc88d, 0x21, 0 + .dw 0xf8c0, 0xc88d, 0xf8ff, 0xc88d, 0x21, 0 + .dw 0xf940, 0xc88d, 0xf97f, 0xc88d, 0x21, 0 + .dw 0xf9c0, 0xc88d, 0xffff, 0xc88d, 0x21, 0 + .dw 0x0040, 0xc88e, 0x007f, 0xc88e, 0x21, 0 + .dw 0x00c0, 0xc88e, 0x00ff, 0xc88e, 0x21, 0 + .dw 0x0140, 0xc88e, 0x017f, 0xc88e, 0x21, 0 + .dw 0x01c0, 0xc88e, 0x01ff, 0xc88e, 0x21, 0 + .dw 0x0240, 0xc88e, 0x027f, 0xc88e, 0x21, 0 + .dw 0x02c0, 0xc88e, 0x02ff, 0xc88e, 0x21, 0 + .dw 0x0340, 0xc88e, 0x037f, 0xc88e, 0x21, 0 + .dw 0x03c0, 0xc88e, 0x03ff, 0xc88e, 0x21, 0 + .dw 0x0440, 0xc88e, 0x047f, 0xc88e, 0x21, 0 + .dw 0x04c0, 0xc88e, 0x04ff, 0xc88e, 0x21, 0 + .dw 0x0540, 0xc88e, 0x057f, 0xc88e, 0x21, 0 + .dw 0x05c0, 0xc88e, 0x05ff, 0xc88e, 0x21, 0 + .dw 0x0640, 0xc88e, 0x067f, 0xc88e, 0x21, 0 + .dw 0x06c0, 0xc88e, 0x06ff, 0xc88e, 0x21, 0 + .dw 0x0740, 0xc88e, 0x077f, 0xc88e, 0x21, 0 + .dw 0x07c0, 0xc88e, 0x07ff, 0xc88e, 0x21, 0 + .dw 0x0840, 0xc88e, 0x087f, 0xc88e, 0x21, 0 + .dw 0x08c0, 0xc88e, 0x08ff, 0xc88e, 0x21, 0 + .dw 0x0940, 0xc88e, 0x097f, 0xc88e, 0x21, 0 + .dw 0x09c0, 0xc88e, 0x09ff, 0xc88e, 0x21, 0 + .dw 0x0a40, 0xc88e, 0x0a7f, 0xc88e, 0x21, 0 + .dw 0x0ac0, 0xc88e, 0x0aff, 0xc88e, 0x21, 0 + .dw 0x0b40, 0xc88e, 0x0b7f, 0xc88e, 0x21, 0 + .dw 0x0bc0, 0xc88e, 0x0bff, 0xc88e, 0x21, 0 + .dw 0x0c40, 0xc88e, 0x0c7f, 0xc88e, 0x21, 0 + .dw 0x0cc0, 0xc88e, 0x0cff, 0xc88e, 0x21, 0 + .dw 0x0d40, 0xc88e, 0x0d7f, 0xc88e, 0x21, 0 + .dw 0x0dc0, 0xc88e, 0x0dff, 0xc88e, 0x21, 0 + .dw 0x0e40, 0xc88e, 0x0e7f, 0xc88e, 0x21, 0 + .dw 0x0ec0, 0xc88e, 0x0eff, 0xc88e, 0x21, 0 + .dw 0x0f40, 0xc88e, 0x0f7f, 0xc88e, 0x21, 0 + .dw 0x0fc0, 0xc88e, 0x0fff, 0xc88e, 0x21, 0 + .dw 0x1040, 0xc88e, 0x107f, 0xc88e, 0x21, 0 + .dw 0x10c0, 0xc88e, 0x10ff, 0xc88e, 0x21, 0 + .dw 0x1140, 0xc88e, 0x117f, 0xc88e, 0x21, 0 + .dw 0x11c0, 0xc88e, 0x11ff, 0xc88e, 0x21, 0 + .dw 0x1240, 0xc88e, 0x127f, 0xc88e, 0x21, 0 + .dw 0x12c0, 0xc88e, 0x12ff, 0xc88e, 0x21, 0 + .dw 0x1340, 0xc88e, 0x137f, 0xc88e, 0x21, 0 + .dw 0x13c0, 0xc88e, 0x13ff, 0xc88e, 0x21, 0 + .dw 0x1440, 0xc88e, 0x147f, 0xc88e, 0x21, 0 + .dw 0x14c0, 0xc88e, 0x14ff, 0xc88e, 0x21, 0 + .dw 0x1540, 0xc88e, 0x157f, 0xc88e, 0x21, 0 + .dw 0x15c0, 0xc88e, 0x15ff, 0xc88e, 0x21, 0 + .dw 0x1640, 0xc88e, 0x167f, 0xc88e, 0x21, 0 + .dw 0x16c0, 0xc88e, 0x16ff, 0xc88e, 0x21, 0 + .dw 0x1740, 0xc88e, 0x177f, 0xc88e, 0x21, 0 + .dw 0x17c0, 0xc88e, 0x17ff, 0xc88e, 0x21, 0 + .dw 0x1840, 0xc88e, 0x187f, 0xc88e, 0x21, 0 + .dw 0x18c0, 0xc88e, 0x18ff, 0xc88e, 0x21, 0 + .dw 0x1940, 0xc88e, 0x197f, 0xc88e, 0x21, 0 + .dw 0x19c0, 0xc88e, 0x1fff, 0xc88e, 0x21, 0 + .dw 0x2040, 0xc88e, 0x207f, 0xc88e, 0x21, 0 + .dw 0x20c0, 0xc88e, 0x20ff, 0xc88e, 0x21, 0 + .dw 0x2140, 0xc88e, 0x217f, 0xc88e, 0x21, 0 + .dw 0x21c0, 0xc88e, 0x21ff, 0xc88e, 0x21, 0 + .dw 0x2240, 0xc88e, 0x227f, 0xc88e, 0x21, 0 + .dw 0x22c0, 0xc88e, 0x22ff, 0xc88e, 0x21, 0 + .dw 0x2340, 0xc88e, 0x237f, 0xc88e, 0x21, 0 + .dw 0x23c0, 0xc88e, 0x23ff, 0xc88e, 0x21, 0 + .dw 0x2440, 0xc88e, 0x247f, 0xc88e, 0x21, 0 + .dw 0x24c0, 0xc88e, 0x24ff, 0xc88e, 0x21, 0 + .dw 0x2540, 0xc88e, 0x257f, 0xc88e, 0x21, 0 + .dw 0x25c0, 0xc88e, 0x25ff, 0xc88e, 0x21, 0 + .dw 0x2640, 0xc88e, 0x267f, 0xc88e, 0x21, 0 + .dw 0x26c0, 0xc88e, 0x26ff, 0xc88e, 0x21, 0 + .dw 0x2740, 0xc88e, 0x277f, 0xc88e, 0x21, 0 + .dw 0x27c0, 0xc88e, 0x27ff, 0xc88e, 0x21, 0 + .dw 0x2840, 0xc88e, 0x287f, 0xc88e, 0x21, 0 + .dw 0x28c0, 0xc88e, 0x28ff, 0xc88e, 0x21, 0 + .dw 0x2940, 0xc88e, 0x297f, 0xc88e, 0x21, 0 + .dw 0x29c0, 0xc88e, 0x29ff, 0xc88e, 0x21, 0 + .dw 0x2a40, 0xc88e, 0x2a7f, 0xc88e, 0x21, 0 + .dw 0x2ac0, 0xc88e, 0x2aff, 0xc88e, 0x21, 0 + .dw 0x2b40, 0xc88e, 0x2b7f, 0xc88e, 0x21, 0 + .dw 0x2bc0, 0xc88e, 0x2bff, 0xc88e, 0x21, 0 + .dw 0x2c40, 0xc88e, 0x2c7f, 0xc88e, 0x21, 0 + .dw 0x2cc0, 0xc88e, 0x2cff, 0xc88e, 0x21, 0 + .dw 0x2d40, 0xc88e, 0x2d7f, 0xc88e, 0x21, 0 + .dw 0x2dc0, 0xc88e, 0x2dff, 0xc88e, 0x21, 0 + .dw 0x2e40, 0xc88e, 0x2e7f, 0xc88e, 0x21, 0 + .dw 0x2ec0, 0xc88e, 0x2eff, 0xc88e, 0x21, 0 + .dw 0x2f40, 0xc88e, 0x2f7f, 0xc88e, 0x21, 0 + .dw 0x2fc0, 0xc88e, 0x2fff, 0xc88e, 0x21, 0 + .dw 0x3040, 0xc88e, 0x307f, 0xc88e, 0x21, 0 + .dw 0x30c0, 0xc88e, 0x30ff, 0xc88e, 0x21, 0 + .dw 0x3140, 0xc88e, 0x317f, 0xc88e, 0x21, 0 + .dw 0x31c0, 0xc88e, 0x31ff, 0xc88e, 0x21, 0 + .dw 0x3240, 0xc88e, 0x327f, 0xc88e, 0x21, 0 + .dw 0x32c0, 0xc88e, 0x32ff, 0xc88e, 0x21, 0 + .dw 0x3340, 0xc88e, 0x337f, 0xc88e, 0x21, 0 + .dw 0x33c0, 0xc88e, 0x33ff, 0xc88e, 0x21, 0 + .dw 0x3440, 0xc88e, 0x347f, 0xc88e, 0x21, 0 + .dw 0x34c0, 0xc88e, 0x34ff, 0xc88e, 0x21, 0 + .dw 0x3540, 0xc88e, 0x357f, 0xc88e, 0x21, 0 + .dw 0x35c0, 0xc88e, 0x35ff, 0xc88e, 0x21, 0 + .dw 0x3640, 0xc88e, 0x367f, 0xc88e, 0x21, 0 + .dw 0x36c0, 0xc88e, 0x36ff, 0xc88e, 0x21, 0 + .dw 0x3740, 0xc88e, 0x377f, 0xc88e, 0x21, 0 + .dw 0x37c0, 0xc88e, 0x37ff, 0xc88e, 0x21, 0 + .dw 0x3840, 0xc88e, 0x387f, 0xc88e, 0x21, 0 + .dw 0x38c0, 0xc88e, 0x38ff, 0xc88e, 0x21, 0 + .dw 0x3940, 0xc88e, 0x397f, 0xc88e, 0x21, 0 + .dw 0x39c0, 0xc88e, 0x3fff, 0xc88e, 0x21, 0 + .dw 0x4040, 0xc88e, 0x407f, 0xc88e, 0x21, 0 + .dw 0x40c0, 0xc88e, 0x40ff, 0xc88e, 0x21, 0 + .dw 0x4140, 0xc88e, 0x417f, 0xc88e, 0x21, 0 + .dw 0x41c0, 0xc88e, 0x41ff, 0xc88e, 0x21, 0 + .dw 0x4240, 0xc88e, 0x427f, 0xc88e, 0x21, 0 + .dw 0x42c0, 0xc88e, 0x42ff, 0xc88e, 0x21, 0 + .dw 0x4340, 0xc88e, 0x437f, 0xc88e, 0x21, 0 + .dw 0x43c0, 0xc88e, 0x43ff, 0xc88e, 0x21, 0 + .dw 0x4440, 0xc88e, 0x447f, 0xc88e, 0x21, 0 + .dw 0x44c0, 0xc88e, 0x44ff, 0xc88e, 0x21, 0 + .dw 0x4540, 0xc88e, 0x457f, 0xc88e, 0x21, 0 + .dw 0x45c0, 0xc88e, 0x45ff, 0xc88e, 0x21, 0 + .dw 0x4640, 0xc88e, 0x467f, 0xc88e, 0x21, 0 + .dw 0x46c0, 0xc88e, 0x46ff, 0xc88e, 0x21, 0 + .dw 0x4740, 0xc88e, 0x477f, 0xc88e, 0x21, 0 + .dw 0x47c0, 0xc88e, 0x47ff, 0xc88e, 0x21, 0 + .dw 0x4840, 0xc88e, 0x487f, 0xc88e, 0x21, 0 + .dw 0x48c0, 0xc88e, 0x48ff, 0xc88e, 0x21, 0 + .dw 0x4940, 0xc88e, 0x497f, 0xc88e, 0x21, 0 + .dw 0x49c0, 0xc88e, 0x49ff, 0xc88e, 0x21, 0 + .dw 0x4a40, 0xc88e, 0x4a7f, 0xc88e, 0x21, 0 + .dw 0x4ac0, 0xc88e, 0x4aff, 0xc88e, 0x21, 0 + .dw 0x4b40, 0xc88e, 0x4b7f, 0xc88e, 0x21, 0 + .dw 0x4bc0, 0xc88e, 0x4bff, 0xc88e, 0x21, 0 + .dw 0x4c40, 0xc88e, 0x4c7f, 0xc88e, 0x21, 0 + .dw 0x4cc0, 0xc88e, 0x4cff, 0xc88e, 0x21, 0 + .dw 0x4d40, 0xc88e, 0x4d7f, 0xc88e, 0x21, 0 + .dw 0x4dc0, 0xc88e, 0x4dff, 0xc88e, 0x21, 0 + .dw 0x4e40, 0xc88e, 0x4e7f, 0xc88e, 0x21, 0 + .dw 0x4ec0, 0xc88e, 0x4eff, 0xc88e, 0x21, 0 + .dw 0x4f40, 0xc88e, 0x4f7f, 0xc88e, 0x21, 0 + .dw 0x4fc0, 0xc88e, 0x4fff, 0xc88e, 0x21, 0 + .dw 0x5040, 0xc88e, 0x507f, 0xc88e, 0x21, 0 + .dw 0x50c0, 0xc88e, 0x50ff, 0xc88e, 0x21, 0 + .dw 0x5140, 0xc88e, 0x517f, 0xc88e, 0x21, 0 + .dw 0x51c0, 0xc88e, 0x51ff, 0xc88e, 0x21, 0 + .dw 0x5240, 0xc88e, 0x527f, 0xc88e, 0x21, 0 + .dw 0x52c0, 0xc88e, 0x52ff, 0xc88e, 0x21, 0 + .dw 0x5340, 0xc88e, 0x537f, 0xc88e, 0x21, 0 + .dw 0x53c0, 0xc88e, 0x53ff, 0xc88e, 0x21, 0 + .dw 0x5440, 0xc88e, 0x547f, 0xc88e, 0x21, 0 + .dw 0x54c0, 0xc88e, 0x54ff, 0xc88e, 0x21, 0 + .dw 0x5540, 0xc88e, 0x557f, 0xc88e, 0x21, 0 + .dw 0x55c0, 0xc88e, 0x55ff, 0xc88e, 0x21, 0 + .dw 0x5640, 0xc88e, 0x567f, 0xc88e, 0x21, 0 + .dw 0x56c0, 0xc88e, 0x56ff, 0xc88e, 0x21, 0 + .dw 0x5740, 0xc88e, 0x577f, 0xc88e, 0x21, 0 + .dw 0x57c0, 0xc88e, 0x57ff, 0xc88e, 0x21, 0 + .dw 0x5840, 0xc88e, 0x587f, 0xc88e, 0x21, 0 + .dw 0x58c0, 0xc88e, 0x58ff, 0xc88e, 0x21, 0 + .dw 0x5940, 0xc88e, 0x597f, 0xc88e, 0x21, 0 + .dw 0x59c0, 0xc88e, 0x5fff, 0xc88e, 0x21, 0 + .dw 0x6040, 0xc88e, 0x607f, 0xc88e, 0x21, 0 + .dw 0x60c0, 0xc88e, 0x60ff, 0xc88e, 0x21, 0 + .dw 0x6140, 0xc88e, 0x617f, 0xc88e, 0x21, 0 + .dw 0x61c0, 0xc88e, 0x61ff, 0xc88e, 0x21, 0 + .dw 0x6240, 0xc88e, 0x627f, 0xc88e, 0x21, 0 + .dw 0x62c0, 0xc88e, 0x62ff, 0xc88e, 0x21, 0 + .dw 0x6340, 0xc88e, 0x637f, 0xc88e, 0x21, 0 + .dw 0x63c0, 0xc88e, 0x63ff, 0xc88e, 0x21, 0 + .dw 0x6440, 0xc88e, 0x647f, 0xc88e, 0x21, 0 + .dw 0x64c0, 0xc88e, 0x64ff, 0xc88e, 0x21, 0 + .dw 0x6540, 0xc88e, 0x657f, 0xc88e, 0x21, 0 + .dw 0x65c0, 0xc88e, 0x65ff, 0xc88e, 0x21, 0 + .dw 0x6640, 0xc88e, 0x667f, 0xc88e, 0x21, 0 + .dw 0x66c0, 0xc88e, 0x66ff, 0xc88e, 0x21, 0 + .dw 0x6740, 0xc88e, 0x677f, 0xc88e, 0x21, 0 + .dw 0x67c0, 0xc88e, 0x67ff, 0xc88e, 0x21, 0 + .dw 0x6840, 0xc88e, 0x687f, 0xc88e, 0x21, 0 + .dw 0x68c0, 0xc88e, 0x68ff, 0xc88e, 0x21, 0 + .dw 0x6940, 0xc88e, 0x697f, 0xc88e, 0x21, 0 + .dw 0x69c0, 0xc88e, 0x69ff, 0xc88e, 0x21, 0 + .dw 0x6a40, 0xc88e, 0x6a7f, 0xc88e, 0x21, 0 + .dw 0x6ac0, 0xc88e, 0x6aff, 0xc88e, 0x21, 0 + .dw 0x6b40, 0xc88e, 0x6b7f, 0xc88e, 0x21, 0 + .dw 0x6bc0, 0xc88e, 0x6bff, 0xc88e, 0x21, 0 + .dw 0x6c40, 0xc88e, 0x6c7f, 0xc88e, 0x21, 0 + .dw 0x6cc0, 0xc88e, 0x6cff, 0xc88e, 0x21, 0 + .dw 0x6d40, 0xc88e, 0x6d7f, 0xc88e, 0x21, 0 + .dw 0x6dc0, 0xc88e, 0x6dff, 0xc88e, 0x21, 0 + .dw 0x6e40, 0xc88e, 0x6e7f, 0xc88e, 0x21, 0 + .dw 0x6ec0, 0xc88e, 0x6eff, 0xc88e, 0x21, 0 + .dw 0x6f40, 0xc88e, 0x6f7f, 0xc88e, 0x21, 0 + .dw 0x6fc0, 0xc88e, 0x6fff, 0xc88e, 0x21, 0 + .dw 0x7040, 0xc88e, 0x707f, 0xc88e, 0x21, 0 + .dw 0x70c0, 0xc88e, 0x70ff, 0xc88e, 0x21, 0 + .dw 0x7140, 0xc88e, 0x717f, 0xc88e, 0x21, 0 + .dw 0x71c0, 0xc88e, 0x71ff, 0xc88e, 0x21, 0 + .dw 0x7240, 0xc88e, 0x727f, 0xc88e, 0x21, 0 + .dw 0x72c0, 0xc88e, 0x72ff, 0xc88e, 0x21, 0 + .dw 0x7340, 0xc88e, 0x737f, 0xc88e, 0x21, 0 + .dw 0x73c0, 0xc88e, 0x73ff, 0xc88e, 0x21, 0 + .dw 0x7440, 0xc88e, 0x747f, 0xc88e, 0x21, 0 + .dw 0x74c0, 0xc88e, 0x74ff, 0xc88e, 0x21, 0 + .dw 0x7540, 0xc88e, 0x757f, 0xc88e, 0x21, 0 + .dw 0x75c0, 0xc88e, 0x75ff, 0xc88e, 0x21, 0 + .dw 0x7640, 0xc88e, 0x767f, 0xc88e, 0x21, 0 + .dw 0x76c0, 0xc88e, 0x76ff, 0xc88e, 0x21, 0 + .dw 0x7740, 0xc88e, 0x777f, 0xc88e, 0x21, 0 + .dw 0x77c0, 0xc88e, 0x77ff, 0xc88e, 0x21, 0 + .dw 0x7840, 0xc88e, 0x787f, 0xc88e, 0x21, 0 + .dw 0x78c0, 0xc88e, 0x78ff, 0xc88e, 0x21, 0 + .dw 0x7940, 0xc88e, 0x797f, 0xc88e, 0x21, 0 + .dw 0x79c0, 0xc88e, 0x7fff, 0xc88e, 0x21, 0 + .dw 0x8040, 0xc88e, 0x807f, 0xc88e, 0x21, 0 + .dw 0x80c0, 0xc88e, 0x80ff, 0xc88e, 0x21, 0 + .dw 0x8140, 0xc88e, 0x817f, 0xc88e, 0x21, 0 + .dw 0x81c0, 0xc88e, 0x81ff, 0xc88e, 0x21, 0 + .dw 0x8240, 0xc88e, 0x827f, 0xc88e, 0x21, 0 + .dw 0x82c0, 0xc88e, 0x82ff, 0xc88e, 0x21, 0 + .dw 0x8340, 0xc88e, 0x837f, 0xc88e, 0x21, 0 + .dw 0x83c0, 0xc88e, 0x83ff, 0xc88e, 0x21, 0 + .dw 0x8440, 0xc88e, 0x847f, 0xc88e, 0x21, 0 + .dw 0x84c0, 0xc88e, 0x84ff, 0xc88e, 0x21, 0 + .dw 0x8540, 0xc88e, 0x857f, 0xc88e, 0x21, 0 + .dw 0x85c0, 0xc88e, 0x85ff, 0xc88e, 0x21, 0 + .dw 0x8640, 0xc88e, 0x867f, 0xc88e, 0x21, 0 + .dw 0x86c0, 0xc88e, 0x86ff, 0xc88e, 0x21, 0 + .dw 0x8740, 0xc88e, 0x877f, 0xc88e, 0x21, 0 + .dw 0x87c0, 0xc88e, 0x87ff, 0xc88e, 0x21, 0 + .dw 0x8840, 0xc88e, 0x887f, 0xc88e, 0x21, 0 + .dw 0x88c0, 0xc88e, 0x88ff, 0xc88e, 0x21, 0 + .dw 0x8940, 0xc88e, 0x897f, 0xc88e, 0x21, 0 + .dw 0x89c0, 0xc88e, 0x89ff, 0xc88e, 0x21, 0 + .dw 0x8a40, 0xc88e, 0x8a7f, 0xc88e, 0x21, 0 + .dw 0x8ac0, 0xc88e, 0x8aff, 0xc88e, 0x21, 0 + .dw 0x8b40, 0xc88e, 0x8b7f, 0xc88e, 0x21, 0 + .dw 0x8bc0, 0xc88e, 0x8bff, 0xc88e, 0x21, 0 + .dw 0x8c40, 0xc88e, 0x8c7f, 0xc88e, 0x21, 0 + .dw 0x8cc0, 0xc88e, 0x8cff, 0xc88e, 0x21, 0 + .dw 0x8d40, 0xc88e, 0x8d7f, 0xc88e, 0x21, 0 + .dw 0x8dc0, 0xc88e, 0x8dff, 0xc88e, 0x21, 0 + .dw 0x8e40, 0xc88e, 0x8e7f, 0xc88e, 0x21, 0 + .dw 0x8ec0, 0xc88e, 0x8eff, 0xc88e, 0x21, 0 + .dw 0x8f40, 0xc88e, 0x8f7f, 0xc88e, 0x21, 0 + .dw 0x8fc0, 0xc88e, 0x8fff, 0xc88e, 0x21, 0 + .dw 0x9040, 0xc88e, 0x907f, 0xc88e, 0x21, 0 + .dw 0x90c0, 0xc88e, 0x90ff, 0xc88e, 0x21, 0 + .dw 0x9140, 0xc88e, 0x917f, 0xc88e, 0x21, 0 + .dw 0x91c0, 0xc88e, 0x91ff, 0xc88e, 0x21, 0 + .dw 0x9240, 0xc88e, 0x927f, 0xc88e, 0x21, 0 + .dw 0x92c0, 0xc88e, 0x92ff, 0xc88e, 0x21, 0 + .dw 0x9340, 0xc88e, 0x937f, 0xc88e, 0x21, 0 + .dw 0x93c0, 0xc88e, 0x93ff, 0xc88e, 0x21, 0 + .dw 0x9440, 0xc88e, 0x947f, 0xc88e, 0x21, 0 + .dw 0x94c0, 0xc88e, 0x94ff, 0xc88e, 0x21, 0 + .dw 0x9540, 0xc88e, 0x957f, 0xc88e, 0x21, 0 + .dw 0x95c0, 0xc88e, 0x95ff, 0xc88e, 0x21, 0 + .dw 0x9640, 0xc88e, 0x967f, 0xc88e, 0x21, 0 + .dw 0x96c0, 0xc88e, 0x96ff, 0xc88e, 0x21, 0 + .dw 0x9740, 0xc88e, 0x977f, 0xc88e, 0x21, 0 + .dw 0x97c0, 0xc88e, 0x97ff, 0xc88e, 0x21, 0 + .dw 0x9840, 0xc88e, 0x987f, 0xc88e, 0x21, 0 + .dw 0x98c0, 0xc88e, 0x98ff, 0xc88e, 0x21, 0 + .dw 0x9940, 0xc88e, 0x997f, 0xc88e, 0x21, 0 + .dw 0x99c0, 0xc88e, 0x9fff, 0xc88e, 0x21, 0 + .dw 0xa040, 0xc88e, 0xa07f, 0xc88e, 0x21, 0 + .dw 0xa0c0, 0xc88e, 0xa0ff, 0xc88e, 0x21, 0 + .dw 0xa140, 0xc88e, 0xa17f, 0xc88e, 0x21, 0 + .dw 0xa1c0, 0xc88e, 0xa1ff, 0xc88e, 0x21, 0 + .dw 0xa240, 0xc88e, 0xa27f, 0xc88e, 0x21, 0 + .dw 0xa2c0, 0xc88e, 0xa2ff, 0xc88e, 0x21, 0 + .dw 0xa340, 0xc88e, 0xa37f, 0xc88e, 0x21, 0 + .dw 0xa3c0, 0xc88e, 0xa3ff, 0xc88e, 0x21, 0 + .dw 0xa440, 0xc88e, 0xa47f, 0xc88e, 0x21, 0 + .dw 0xa4c0, 0xc88e, 0xa4ff, 0xc88e, 0x21, 0 + .dw 0xa540, 0xc88e, 0xa57f, 0xc88e, 0x21, 0 + .dw 0xa5c0, 0xc88e, 0xa5ff, 0xc88e, 0x21, 0 + .dw 0xa640, 0xc88e, 0xa67f, 0xc88e, 0x21, 0 + .dw 0xa6c0, 0xc88e, 0xa6ff, 0xc88e, 0x21, 0 + .dw 0xa740, 0xc88e, 0xa77f, 0xc88e, 0x21, 0 + .dw 0xa7c0, 0xc88e, 0xa7ff, 0xc88e, 0x21, 0 + .dw 0xa840, 0xc88e, 0xa87f, 0xc88e, 0x21, 0 + .dw 0xa8c0, 0xc88e, 0xa8ff, 0xc88e, 0x21, 0 + .dw 0xa940, 0xc88e, 0xa97f, 0xc88e, 0x21, 0 + .dw 0xa9c0, 0xc88e, 0xa9ff, 0xc88e, 0x21, 0 + .dw 0xaa40, 0xc88e, 0xaa7f, 0xc88e, 0x21, 0 + .dw 0xaac0, 0xc88e, 0xaaff, 0xc88e, 0x21, 0 + .dw 0xab40, 0xc88e, 0xab7f, 0xc88e, 0x21, 0 + .dw 0xabc0, 0xc88e, 0xabff, 0xc88e, 0x21, 0 + .dw 0xac40, 0xc88e, 0xac7f, 0xc88e, 0x21, 0 + .dw 0xacc0, 0xc88e, 0xacff, 0xc88e, 0x21, 0 + .dw 0xad40, 0xc88e, 0xad7f, 0xc88e, 0x21, 0 + .dw 0xadc0, 0xc88e, 0xadff, 0xc88e, 0x21, 0 + .dw 0xae40, 0xc88e, 0xae7f, 0xc88e, 0x21, 0 + .dw 0xaec0, 0xc88e, 0xaeff, 0xc88e, 0x21, 0 + .dw 0xaf40, 0xc88e, 0xaf7f, 0xc88e, 0x21, 0 + .dw 0xafc0, 0xc88e, 0xafff, 0xc88e, 0x21, 0 + .dw 0xb040, 0xc88e, 0xb07f, 0xc88e, 0x21, 0 + .dw 0xb0c0, 0xc88e, 0xb0ff, 0xc88e, 0x21, 0 + .dw 0xb140, 0xc88e, 0xb17f, 0xc88e, 0x21, 0 + .dw 0xb1c0, 0xc88e, 0xb1ff, 0xc88e, 0x21, 0 + .dw 0xb240, 0xc88e, 0xb27f, 0xc88e, 0x21, 0 + .dw 0xb2c0, 0xc88e, 0xb2ff, 0xc88e, 0x21, 0 + .dw 0xb340, 0xc88e, 0xb37f, 0xc88e, 0x21, 0 + .dw 0xb3c0, 0xc88e, 0xb3ff, 0xc88e, 0x21, 0 + .dw 0xb440, 0xc88e, 0xb47f, 0xc88e, 0x21, 0 + .dw 0xb4c0, 0xc88e, 0xb4ff, 0xc88e, 0x21, 0 + .dw 0xb540, 0xc88e, 0xb57f, 0xc88e, 0x21, 0 + .dw 0xb5c0, 0xc88e, 0xb5ff, 0xc88e, 0x21, 0 + .dw 0xb640, 0xc88e, 0xb67f, 0xc88e, 0x21, 0 + .dw 0xb6c0, 0xc88e, 0xb6ff, 0xc88e, 0x21, 0 + .dw 0xb740, 0xc88e, 0xb77f, 0xc88e, 0x21, 0 + .dw 0xb7c0, 0xc88e, 0xb7ff, 0xc88e, 0x21, 0 + .dw 0xb840, 0xc88e, 0xb87f, 0xc88e, 0x21, 0 + .dw 0xb8c0, 0xc88e, 0xb8ff, 0xc88e, 0x21, 0 + .dw 0xb940, 0xc88e, 0xb97f, 0xc88e, 0x21, 0 + .dw 0xb9c0, 0xc88e, 0xbfff, 0xc88e, 0x21, 0 + .dw 0xc040, 0xc88e, 0xc07f, 0xc88e, 0x21, 0 + .dw 0xc0c0, 0xc88e, 0xc0ff, 0xc88e, 0x21, 0 + .dw 0xc140, 0xc88e, 0xc17f, 0xc88e, 0x21, 0 + .dw 0xc1c0, 0xc88e, 0xc1ff, 0xc88e, 0x21, 0 + .dw 0xc240, 0xc88e, 0xc27f, 0xc88e, 0x21, 0 + .dw 0xc2c0, 0xc88e, 0xc2ff, 0xc88e, 0x21, 0 + .dw 0xc340, 0xc88e, 0xc37f, 0xc88e, 0x21, 0 + .dw 0xc3c0, 0xc88e, 0xc3ff, 0xc88e, 0x21, 0 + .dw 0xc440, 0xc88e, 0xc47f, 0xc88e, 0x21, 0 + .dw 0xc4c0, 0xc88e, 0xc4ff, 0xc88e, 0x21, 0 + .dw 0xc540, 0xc88e, 0xc57f, 0xc88e, 0x21, 0 + .dw 0xc5c0, 0xc88e, 0xc5ff, 0xc88e, 0x21, 0 + .dw 0xc640, 0xc88e, 0xc67f, 0xc88e, 0x21, 0 + .dw 0xc6c0, 0xc88e, 0xc6ff, 0xc88e, 0x21, 0 + .dw 0xc740, 0xc88e, 0xc77f, 0xc88e, 0x21, 0 + .dw 0xc7c0, 0xc88e, 0xc7ff, 0xc88e, 0x21, 0 + .dw 0xc840, 0xc88e, 0xc87f, 0xc88e, 0x21, 0 + .dw 0xc8c0, 0xc88e, 0xc8ff, 0xc88e, 0x21, 0 + .dw 0xc940, 0xc88e, 0xc97f, 0xc88e, 0x21, 0 + .dw 0xc9c0, 0xc88e, 0xc9ff, 0xc88e, 0x21, 0 + .dw 0xca40, 0xc88e, 0xca7f, 0xc88e, 0x21, 0 + .dw 0xcac0, 0xc88e, 0xcaff, 0xc88e, 0x21, 0 + .dw 0xcb40, 0xc88e, 0xcb7f, 0xc88e, 0x21, 0 + .dw 0xcbc0, 0xc88e, 0xcbff, 0xc88e, 0x21, 0 + .dw 0xcc40, 0xc88e, 0xcc7f, 0xc88e, 0x21, 0 + .dw 0xccc0, 0xc88e, 0xccff, 0xc88e, 0x21, 0 + .dw 0xcd40, 0xc88e, 0xcd7f, 0xc88e, 0x21, 0 + .dw 0xcdc0, 0xc88e, 0xcdff, 0xc88e, 0x21, 0 + .dw 0xce40, 0xc88e, 0xce7f, 0xc88e, 0x21, 0 + .dw 0xcec0, 0xc88e, 0xceff, 0xc88e, 0x21, 0 + .dw 0xcf40, 0xc88e, 0xcf7f, 0xc88e, 0x21, 0 + .dw 0xcfc0, 0xc88e, 0xcfff, 0xc88e, 0x21, 0 + .dw 0xd040, 0xc88e, 0xd07f, 0xc88e, 0x21, 0 + .dw 0xd0c0, 0xc88e, 0xd0ff, 0xc88e, 0x21, 0 + .dw 0xd140, 0xc88e, 0xd17f, 0xc88e, 0x21, 0 + .dw 0xd1c0, 0xc88e, 0xd1ff, 0xc88e, 0x21, 0 + .dw 0xd240, 0xc88e, 0xd27f, 0xc88e, 0x21, 0 + .dw 0xd2c0, 0xc88e, 0xd2ff, 0xc88e, 0x21, 0 + .dw 0xd340, 0xc88e, 0xd37f, 0xc88e, 0x21, 0 + .dw 0xd3c0, 0xc88e, 0xd3ff, 0xc88e, 0x21, 0 + .dw 0xd440, 0xc88e, 0xd47f, 0xc88e, 0x21, 0 + .dw 0xd4c0, 0xc88e, 0xd4ff, 0xc88e, 0x21, 0 + .dw 0xd540, 0xc88e, 0xd57f, 0xc88e, 0x21, 0 + .dw 0xd5c0, 0xc88e, 0xd5ff, 0xc88e, 0x21, 0 + .dw 0xd640, 0xc88e, 0xd67f, 0xc88e, 0x21, 0 + .dw 0xd6c0, 0xc88e, 0xd6ff, 0xc88e, 0x21, 0 + .dw 0xd740, 0xc88e, 0xd77f, 0xc88e, 0x21, 0 + .dw 0xd7c0, 0xc88e, 0xd7ff, 0xc88e, 0x21, 0 + .dw 0xd840, 0xc88e, 0xd87f, 0xc88e, 0x21, 0 + .dw 0xd8c0, 0xc88e, 0xd8ff, 0xc88e, 0x21, 0 + .dw 0xd940, 0xc88e, 0xd97f, 0xc88e, 0x21, 0 + .dw 0xd9c0, 0xc88e, 0xdfff, 0xc88e, 0x21, 0 + .dw 0xe040, 0xc88e, 0xe07f, 0xc88e, 0x21, 0 + .dw 0xe0c0, 0xc88e, 0xe0ff, 0xc88e, 0x21, 0 + .dw 0xe140, 0xc88e, 0xe17f, 0xc88e, 0x21, 0 + .dw 0xe1c0, 0xc88e, 0xe1ff, 0xc88e, 0x21, 0 + .dw 0xe240, 0xc88e, 0xe27f, 0xc88e, 0x21, 0 + .dw 0xe2c0, 0xc88e, 0xe2ff, 0xc88e, 0x21, 0 + .dw 0xe340, 0xc88e, 0xe37f, 0xc88e, 0x21, 0 + .dw 0xe3c0, 0xc88e, 0xe3ff, 0xc88e, 0x21, 0 + .dw 0xe440, 0xc88e, 0xe47f, 0xc88e, 0x21, 0 + .dw 0xe4c0, 0xc88e, 0xe4ff, 0xc88e, 0x21, 0 + .dw 0xe540, 0xc88e, 0xe57f, 0xc88e, 0x21, 0 + .dw 0xe5c0, 0xc88e, 0xe5ff, 0xc88e, 0x21, 0 + .dw 0xe640, 0xc88e, 0xe67f, 0xc88e, 0x21, 0 + .dw 0xe6c0, 0xc88e, 0xe6ff, 0xc88e, 0x21, 0 + .dw 0xe740, 0xc88e, 0xe77f, 0xc88e, 0x21, 0 + .dw 0xe7c0, 0xc88e, 0xe7ff, 0xc88e, 0x21, 0 + .dw 0xe840, 0xc88e, 0xe87f, 0xc88e, 0x21, 0 + .dw 0xe8c0, 0xc88e, 0xe8ff, 0xc88e, 0x21, 0 + .dw 0xe940, 0xc88e, 0xe97f, 0xc88e, 0x21, 0 + .dw 0xe9c0, 0xc88e, 0xe9ff, 0xc88e, 0x21, 0 + .dw 0xea40, 0xc88e, 0xea7f, 0xc88e, 0x21, 0 + .dw 0xeac0, 0xc88e, 0xeaff, 0xc88e, 0x21, 0 + .dw 0xeb40, 0xc88e, 0xeb7f, 0xc88e, 0x21, 0 + .dw 0xebc0, 0xc88e, 0xebff, 0xc88e, 0x21, 0 + .dw 0xec40, 0xc88e, 0xec7f, 0xc88e, 0x21, 0 + .dw 0xecc0, 0xc88e, 0xecff, 0xc88e, 0x21, 0 + .dw 0xed40, 0xc88e, 0xed7f, 0xc88e, 0x21, 0 + .dw 0xedc0, 0xc88e, 0xedff, 0xc88e, 0x21, 0 + .dw 0xee40, 0xc88e, 0xee7f, 0xc88e, 0x21, 0 + .dw 0xeec0, 0xc88e, 0xeeff, 0xc88e, 0x21, 0 + .dw 0xef40, 0xc88e, 0xef7f, 0xc88e, 0x21, 0 + .dw 0xefc0, 0xc88e, 0xefff, 0xc88e, 0x21, 0 + .dw 0xf040, 0xc88e, 0xf07f, 0xc88e, 0x21, 0 + .dw 0xf0c0, 0xc88e, 0xf0ff, 0xc88e, 0x21, 0 + .dw 0xf140, 0xc88e, 0xf17f, 0xc88e, 0x21, 0 + .dw 0xf1c0, 0xc88e, 0xf1ff, 0xc88e, 0x21, 0 + .dw 0xf240, 0xc88e, 0xf27f, 0xc88e, 0x21, 0 + .dw 0xf2c0, 0xc88e, 0xf2ff, 0xc88e, 0x21, 0 + .dw 0xf340, 0xc88e, 0xf37f, 0xc88e, 0x21, 0 + .dw 0xf3c0, 0xc88e, 0xf3ff, 0xc88e, 0x21, 0 + .dw 0xf440, 0xc88e, 0xf47f, 0xc88e, 0x21, 0 + .dw 0xf4c0, 0xc88e, 0xf4ff, 0xc88e, 0x21, 0 + .dw 0xf540, 0xc88e, 0xf57f, 0xc88e, 0x21, 0 + .dw 0xf5c0, 0xc88e, 0xf5ff, 0xc88e, 0x21, 0 + .dw 0xf640, 0xc88e, 0xf67f, 0xc88e, 0x21, 0 + .dw 0xf6c0, 0xc88e, 0xf6ff, 0xc88e, 0x21, 0 + .dw 0xf740, 0xc88e, 0xf77f, 0xc88e, 0x21, 0 + .dw 0xf7c0, 0xc88e, 0xf7ff, 0xc88e, 0x21, 0 + .dw 0xf840, 0xc88e, 0xf87f, 0xc88e, 0x21, 0 + .dw 0xf8c0, 0xc88e, 0xf8ff, 0xc88e, 0x21, 0 + .dw 0xf940, 0xc88e, 0xf97f, 0xc88e, 0x21, 0 + .dw 0xf9c0, 0xc88e, 0xffff, 0xc88e, 0x21, 0 + .dw 0x0040, 0xc88f, 0x007f, 0xc88f, 0x21, 0 + .dw 0x00c0, 0xc88f, 0x00ff, 0xc88f, 0x21, 0 + .dw 0x0140, 0xc88f, 0x017f, 0xc88f, 0x21, 0 + .dw 0x01c0, 0xc88f, 0x01ff, 0xc88f, 0x21, 0 + .dw 0x0240, 0xc88f, 0x027f, 0xc88f, 0x21, 0 + .dw 0x02c0, 0xc88f, 0x02ff, 0xc88f, 0x21, 0 + .dw 0x0340, 0xc88f, 0x037f, 0xc88f, 0x21, 0 + .dw 0x03c0, 0xc88f, 0x03ff, 0xc88f, 0x21, 0 + .dw 0x0440, 0xc88f, 0x047f, 0xc88f, 0x21, 0 + .dw 0x04c0, 0xc88f, 0x04ff, 0xc88f, 0x21, 0 + .dw 0x0540, 0xc88f, 0x057f, 0xc88f, 0x21, 0 + .dw 0x05c0, 0xc88f, 0x05ff, 0xc88f, 0x21, 0 + .dw 0x0640, 0xc88f, 0x067f, 0xc88f, 0x21, 0 + .dw 0x06c0, 0xc88f, 0x06ff, 0xc88f, 0x21, 0 + .dw 0x0740, 0xc88f, 0x077f, 0xc88f, 0x21, 0 + .dw 0x07c0, 0xc88f, 0x07ff, 0xc88f, 0x21, 0 + .dw 0x0840, 0xc88f, 0x087f, 0xc88f, 0x21, 0 + .dw 0x08c0, 0xc88f, 0x08ff, 0xc88f, 0x21, 0 + .dw 0x0940, 0xc88f, 0x097f, 0xc88f, 0x21, 0 + .dw 0x09c0, 0xc88f, 0x09ff, 0xc88f, 0x21, 0 + .dw 0x0a40, 0xc88f, 0x0a7f, 0xc88f, 0x21, 0 + .dw 0x0ac0, 0xc88f, 0x0aff, 0xc88f, 0x21, 0 + .dw 0x0b40, 0xc88f, 0x0b7f, 0xc88f, 0x21, 0 + .dw 0x0bc0, 0xc88f, 0x0bff, 0xc88f, 0x21, 0 + .dw 0x0c40, 0xc88f, 0x0c7f, 0xc88f, 0x21, 0 + .dw 0x0cc0, 0xc88f, 0x0cff, 0xc88f, 0x21, 0 + .dw 0x0d40, 0xc88f, 0x0d7f, 0xc88f, 0x21, 0 + .dw 0x0dc0, 0xc88f, 0x0dff, 0xc88f, 0x21, 0 + .dw 0x0e40, 0xc88f, 0x0e7f, 0xc88f, 0x21, 0 + .dw 0x0ec0, 0xc88f, 0x0eff, 0xc88f, 0x21, 0 + .dw 0x0f40, 0xc88f, 0x0f7f, 0xc88f, 0x21, 0 + .dw 0x0fc0, 0xc88f, 0x0fff, 0xc88f, 0x21, 0 + .dw 0x1040, 0xc88f, 0x107f, 0xc88f, 0x21, 0 + .dw 0x10c0, 0xc88f, 0x10ff, 0xc88f, 0x21, 0 + .dw 0x1140, 0xc88f, 0x117f, 0xc88f, 0x21, 0 + .dw 0x11c0, 0xc88f, 0x11ff, 0xc88f, 0x21, 0 + .dw 0x1240, 0xc88f, 0x127f, 0xc88f, 0x21, 0 + .dw 0x12c0, 0xc88f, 0x12ff, 0xc88f, 0x21, 0 + .dw 0x1340, 0xc88f, 0x137f, 0xc88f, 0x21, 0 + .dw 0x13c0, 0xc88f, 0x13ff, 0xc88f, 0x21, 0 + .dw 0x1440, 0xc88f, 0x147f, 0xc88f, 0x21, 0 + .dw 0x14c0, 0xc88f, 0x14ff, 0xc88f, 0x21, 0 + .dw 0x1540, 0xc88f, 0x157f, 0xc88f, 0x21, 0 + .dw 0x15c0, 0xc88f, 0x15ff, 0xc88f, 0x21, 0 + .dw 0x1640, 0xc88f, 0x167f, 0xc88f, 0x21, 0 + .dw 0x16c0, 0xc88f, 0x16ff, 0xc88f, 0x21, 0 + .dw 0x1740, 0xc88f, 0x177f, 0xc88f, 0x21, 0 + .dw 0x17c0, 0xc88f, 0x17ff, 0xc88f, 0x21, 0 + .dw 0x1840, 0xc88f, 0x187f, 0xc88f, 0x21, 0 + .dw 0x18c0, 0xc88f, 0x18ff, 0xc88f, 0x21, 0 + .dw 0x1940, 0xc88f, 0x197f, 0xc88f, 0x21, 0 + .dw 0x19c0, 0xc88f, 0x1fff, 0xc88f, 0x21, 0 + .dw 0x2040, 0xc88f, 0x207f, 0xc88f, 0x21, 0 + .dw 0x20c0, 0xc88f, 0x20ff, 0xc88f, 0x21, 0 + .dw 0x2140, 0xc88f, 0x217f, 0xc88f, 0x21, 0 + .dw 0x21c0, 0xc88f, 0x21ff, 0xc88f, 0x21, 0 + .dw 0x2240, 0xc88f, 0x227f, 0xc88f, 0x21, 0 + .dw 0x22c0, 0xc88f, 0x22ff, 0xc88f, 0x21, 0 + .dw 0x2340, 0xc88f, 0x237f, 0xc88f, 0x21, 0 + .dw 0x23c0, 0xc88f, 0x23ff, 0xc88f, 0x21, 0 + .dw 0x2440, 0xc88f, 0x247f, 0xc88f, 0x21, 0 + .dw 0x24c0, 0xc88f, 0x24ff, 0xc88f, 0x21, 0 + .dw 0x2540, 0xc88f, 0x257f, 0xc88f, 0x21, 0 + .dw 0x25c0, 0xc88f, 0x25ff, 0xc88f, 0x21, 0 + .dw 0x2640, 0xc88f, 0x267f, 0xc88f, 0x21, 0 + .dw 0x26c0, 0xc88f, 0x26ff, 0xc88f, 0x21, 0 + .dw 0x2740, 0xc88f, 0x277f, 0xc88f, 0x21, 0 + .dw 0x27c0, 0xc88f, 0x27ff, 0xc88f, 0x21, 0 + .dw 0x2840, 0xc88f, 0x287f, 0xc88f, 0x21, 0 + .dw 0x28c0, 0xc88f, 0x28ff, 0xc88f, 0x21, 0 + .dw 0x2940, 0xc88f, 0x297f, 0xc88f, 0x21, 0 + .dw 0x29c0, 0xc88f, 0x29ff, 0xc88f, 0x21, 0 + .dw 0x2a40, 0xc88f, 0x2a7f, 0xc88f, 0x21, 0 + .dw 0x2ac0, 0xc88f, 0x2aff, 0xc88f, 0x21, 0 + .dw 0x2b40, 0xc88f, 0x2b7f, 0xc88f, 0x21, 0 + .dw 0x2bc0, 0xc88f, 0x2bff, 0xc88f, 0x21, 0 + .dw 0x2c40, 0xc88f, 0x2c7f, 0xc88f, 0x21, 0 + .dw 0x2cc0, 0xc88f, 0x2cff, 0xc88f, 0x21, 0 + .dw 0x2d40, 0xc88f, 0x2d7f, 0xc88f, 0x21, 0 + .dw 0x2dc0, 0xc88f, 0x2dff, 0xc88f, 0x21, 0 + .dw 0x2e40, 0xc88f, 0x2e7f, 0xc88f, 0x21, 0 + .dw 0x2ec0, 0xc88f, 0x2eff, 0xc88f, 0x21, 0 + .dw 0x2f40, 0xc88f, 0x2f7f, 0xc88f, 0x21, 0 + .dw 0x2fc0, 0xc88f, 0x2fff, 0xc88f, 0x21, 0 + .dw 0x3040, 0xc88f, 0x307f, 0xc88f, 0x21, 0 + .dw 0x30c0, 0xc88f, 0x30ff, 0xc88f, 0x21, 0 + .dw 0x3140, 0xc88f, 0x317f, 0xc88f, 0x21, 0 + .dw 0x31c0, 0xc88f, 0x31ff, 0xc88f, 0x21, 0 + .dw 0x3240, 0xc88f, 0x327f, 0xc88f, 0x21, 0 + .dw 0x32c0, 0xc88f, 0x32ff, 0xc88f, 0x21, 0 + .dw 0x3340, 0xc88f, 0x337f, 0xc88f, 0x21, 0 + .dw 0x33c0, 0xc88f, 0x33ff, 0xc88f, 0x21, 0 + .dw 0x3440, 0xc88f, 0x347f, 0xc88f, 0x21, 0 + .dw 0x34c0, 0xc88f, 0x34ff, 0xc88f, 0x21, 0 + .dw 0x3540, 0xc88f, 0x357f, 0xc88f, 0x21, 0 + .dw 0x35c0, 0xc88f, 0x35ff, 0xc88f, 0x21, 0 + .dw 0x3640, 0xc88f, 0x367f, 0xc88f, 0x21, 0 + .dw 0x36c0, 0xc88f, 0x36ff, 0xc88f, 0x21, 0 + .dw 0x3740, 0xc88f, 0x377f, 0xc88f, 0x21, 0 + .dw 0x37c0, 0xc88f, 0x37ff, 0xc88f, 0x21, 0 + .dw 0x3840, 0xc88f, 0x387f, 0xc88f, 0x21, 0 + .dw 0x38c0, 0xc88f, 0x38ff, 0xc88f, 0x21, 0 + .dw 0x3940, 0xc88f, 0x397f, 0xc88f, 0x21, 0 + .dw 0x39c0, 0xc88f, 0xffff, 0xc88f, 0x21, 0 + .dw 0x1a00, 0xc890, 0x1fff, 0xc890, 0x21, 0 + .dw 0x3a00, 0xc890, 0x3fff, 0xc890, 0x21, 0 + .dw 0x5a00, 0xc890, 0x5fff, 0xc890, 0x21, 0 + .dw 0x7a00, 0xc890, 0x7fff, 0xc890, 0x21, 0 + .dw 0x9a00, 0xc890, 0x9fff, 0xc890, 0x21, 0 + .dw 0xba00, 0xc890, 0xbfff, 0xc890, 0x21, 0 + .dw 0xda00, 0xc890, 0xdfff, 0xc890, 0x21, 0 + .dw 0xfa00, 0xc890, 0xffff, 0xc890, 0x21, 0 + .dw 0x1a00, 0xc891, 0x1fff, 0xc891, 0x21, 0 + .dw 0x3a00, 0xc891, 0x3fff, 0xc891, 0x21, 0 + .dw 0x5a00, 0xc891, 0x5fff, 0xc891, 0x21, 0 + .dw 0x7a00, 0xc891, 0x7fff, 0xc891, 0x21, 0 + .dw 0x9a00, 0xc891, 0x9fff, 0xc891, 0x21, 0 + .dw 0xba00, 0xc891, 0xbfff, 0xc891, 0x21, 0 + .dw 0xda00, 0xc891, 0xdfff, 0xc891, 0x21, 0 + .dw 0xfa00, 0xc891, 0xffff, 0xc891, 0x21, 0 + .dw 0x1a00, 0xc892, 0x1fff, 0xc892, 0x21, 0 + .dw 0x3a00, 0xc892, 0x3fff, 0xc892, 0x21, 0 + .dw 0x5a00, 0xc892, 0x5fff, 0xc892, 0x21, 0 + .dw 0x7a00, 0xc892, 0x7fff, 0xc892, 0x21, 0 + .dw 0x9a00, 0xc892, 0x9fff, 0xc892, 0x21, 0 + .dw 0xba00, 0xc892, 0xbfff, 0xc892, 0x21, 0 + .dw 0xda00, 0xc892, 0xdfff, 0xc892, 0x21, 0 + .dw 0xfa00, 0xc892, 0xffff, 0xc893, 0x21, 0 + .dw 0x1a00, 0xc894, 0x1fff, 0xc894, 0x21, 0 + .dw 0x3a00, 0xc894, 0x3fff, 0xc894, 0x21, 0 + .dw 0x5a00, 0xc894, 0x5fff, 0xc894, 0x21, 0 + .dw 0x7a00, 0xc894, 0x7fff, 0xc894, 0x21, 0 + .dw 0x9a00, 0xc894, 0x9fff, 0xc894, 0x21, 0 + .dw 0xba00, 0xc894, 0xbfff, 0xc894, 0x21, 0 + .dw 0xda00, 0xc894, 0xdfff, 0xc894, 0x21, 0 + .dw 0xfa00, 0xc894, 0xffff, 0xc894, 0x21, 0 + .dw 0x1a00, 0xc895, 0x1fff, 0xc895, 0x21, 0 + .dw 0x3a00, 0xc895, 0x3fff, 0xc895, 0x21, 0 + .dw 0x5a00, 0xc895, 0x5fff, 0xc895, 0x21, 0 + .dw 0x7a00, 0xc895, 0x7fff, 0xc895, 0x21, 0 + .dw 0x9a00, 0xc895, 0x9fff, 0xc895, 0x21, 0 + .dw 0xba00, 0xc895, 0xbfff, 0xc895, 0x21, 0 + .dw 0xda00, 0xc895, 0xdfff, 0xc895, 0x21, 0 + .dw 0xfa00, 0xc895, 0xffff, 0xc895, 0x21, 0 + .dw 0x1a00, 0xc896, 0x1fff, 0xc896, 0x21, 0 + .dw 0x3a00, 0xc896, 0x3fff, 0xc896, 0x21, 0 + .dw 0x5a00, 0xc896, 0x5fff, 0xc896, 0x21, 0 + .dw 0x7a00, 0xc896, 0x7fff, 0xc896, 0x21, 0 + .dw 0x9a00, 0xc896, 0x9fff, 0xc896, 0x21, 0 + .dw 0xba00, 0xc896, 0xbfff, 0xc896, 0x21, 0 + .dw 0xda00, 0xc896, 0xdfff, 0xc896, 0x21, 0 + .dw 0xfa00, 0xc896, 0xffff, 0xc896, 0x21, 0 + .dw 0x1a00, 0xc897, 0x1fff, 0xc897, 0x21, 0 + .dw 0x3a00, 0xc897, 0x1fff, 0xc898, 0x21, 0 + .dw 0x2040, 0xc898, 0x207f, 0xc898, 0x21, 0 + .dw 0x20c0, 0xc898, 0x20ff, 0xc898, 0x21, 0 + .dw 0x2140, 0xc898, 0x217f, 0xc898, 0x21, 0 + .dw 0x21c0, 0xc898, 0x21ff, 0xc898, 0x21, 0 + .dw 0x2240, 0xc898, 0x227f, 0xc898, 0x21, 0 + .dw 0x22c0, 0xc898, 0x22ff, 0xc898, 0x21, 0 + .dw 0x2340, 0xc898, 0x237f, 0xc898, 0x21, 0 + .dw 0x23c0, 0xc898, 0x23ff, 0xc898, 0x21, 0 + .dw 0x2440, 0xc898, 0x247f, 0xc898, 0x21, 0 + .dw 0x24c0, 0xc898, 0x24ff, 0xc898, 0x21, 0 + .dw 0x2540, 0xc898, 0x257f, 0xc898, 0x21, 0 + .dw 0x25c0, 0xc898, 0x25ff, 0xc898, 0x21, 0 + .dw 0x2640, 0xc898, 0x267f, 0xc898, 0x21, 0 + .dw 0x26c0, 0xc898, 0x26ff, 0xc898, 0x21, 0 + .dw 0x2740, 0xc898, 0x277f, 0xc898, 0x21, 0 + .dw 0x27c0, 0xc898, 0x27ff, 0xc898, 0x21, 0 + .dw 0x2840, 0xc898, 0x287f, 0xc898, 0x21, 0 + .dw 0x28c0, 0xc898, 0x28ff, 0xc898, 0x21, 0 + .dw 0x2940, 0xc898, 0x297f, 0xc898, 0x21, 0 + .dw 0x29c0, 0xc898, 0x29ff, 0xc898, 0x21, 0 + .dw 0x2a40, 0xc898, 0x2a7f, 0xc898, 0x21, 0 + .dw 0x2ac0, 0xc898, 0x2aff, 0xc898, 0x21, 0 + .dw 0x2b40, 0xc898, 0x2b7f, 0xc898, 0x21, 0 + .dw 0x2bc0, 0xc898, 0x2bff, 0xc898, 0x21, 0 + .dw 0x2c40, 0xc898, 0x2c7f, 0xc898, 0x21, 0 + .dw 0x2cc0, 0xc898, 0x2cff, 0xc898, 0x21, 0 + .dw 0x2d40, 0xc898, 0x2d7f, 0xc898, 0x21, 0 + .dw 0x2dc0, 0xc898, 0x2dff, 0xc898, 0x21, 0 + .dw 0x2e40, 0xc898, 0x2e7f, 0xc898, 0x21, 0 + .dw 0x2ec0, 0xc898, 0x2eff, 0xc898, 0x21, 0 + .dw 0x2f40, 0xc898, 0x2f7f, 0xc898, 0x21, 0 + .dw 0x2fc0, 0xc898, 0x2fff, 0xc898, 0x21, 0 + .dw 0x3040, 0xc898, 0x307f, 0xc898, 0x21, 0 + .dw 0x30c0, 0xc898, 0x30ff, 0xc898, 0x21, 0 + .dw 0x3140, 0xc898, 0x317f, 0xc898, 0x21, 0 + .dw 0x31c0, 0xc898, 0x31ff, 0xc898, 0x21, 0 + .dw 0x3240, 0xc898, 0x327f, 0xc898, 0x21, 0 + .dw 0x32c0, 0xc898, 0x32ff, 0xc898, 0x21, 0 + .dw 0x3340, 0xc898, 0x337f, 0xc898, 0x21, 0 + .dw 0x33c0, 0xc898, 0x33ff, 0xc898, 0x21, 0 + .dw 0x3440, 0xc898, 0x347f, 0xc898, 0x21, 0 + .dw 0x34c0, 0xc898, 0x34ff, 0xc898, 0x21, 0 + .dw 0x3540, 0xc898, 0x357f, 0xc898, 0x21, 0 + .dw 0x35c0, 0xc898, 0x35ff, 0xc898, 0x21, 0 + .dw 0x3640, 0xc898, 0x367f, 0xc898, 0x21, 0 + .dw 0x36c0, 0xc898, 0x36ff, 0xc898, 0x21, 0 + .dw 0x3740, 0xc898, 0x377f, 0xc898, 0x21, 0 + .dw 0x37c0, 0xc898, 0x37ff, 0xc898, 0x21, 0 + .dw 0x3840, 0xc898, 0x387f, 0xc898, 0x21, 0 + .dw 0x38c0, 0xc898, 0x38ff, 0xc898, 0x21, 0 + .dw 0x3940, 0xc898, 0x397f, 0xc898, 0x21, 0 + .dw 0x39c0, 0xc898, 0x5fff, 0xc898, 0x21, 0 + .dw 0x6040, 0xc898, 0x607f, 0xc898, 0x21, 0 + .dw 0x60c0, 0xc898, 0x60ff, 0xc898, 0x21, 0 + .dw 0x6140, 0xc898, 0x617f, 0xc898, 0x21, 0 + .dw 0x61c0, 0xc898, 0x61ff, 0xc898, 0x21, 0 + .dw 0x6240, 0xc898, 0x627f, 0xc898, 0x21, 0 + .dw 0x62c0, 0xc898, 0x62ff, 0xc898, 0x21, 0 + .dw 0x6340, 0xc898, 0x637f, 0xc898, 0x21, 0 + .dw 0x63c0, 0xc898, 0x63ff, 0xc898, 0x21, 0 + .dw 0x6440, 0xc898, 0x647f, 0xc898, 0x21, 0 + .dw 0x64c0, 0xc898, 0x64ff, 0xc898, 0x21, 0 + .dw 0x6540, 0xc898, 0x657f, 0xc898, 0x21, 0 + .dw 0x65c0, 0xc898, 0x65ff, 0xc898, 0x21, 0 + .dw 0x6640, 0xc898, 0x667f, 0xc898, 0x21, 0 + .dw 0x66c0, 0xc898, 0x66ff, 0xc898, 0x21, 0 + .dw 0x6740, 0xc898, 0x677f, 0xc898, 0x21, 0 + .dw 0x67c0, 0xc898, 0x67ff, 0xc898, 0x21, 0 + .dw 0x6840, 0xc898, 0x687f, 0xc898, 0x21, 0 + .dw 0x68c0, 0xc898, 0x68ff, 0xc898, 0x21, 0 + .dw 0x6940, 0xc898, 0x697f, 0xc898, 0x21, 0 + .dw 0x69c0, 0xc898, 0x69ff, 0xc898, 0x21, 0 + .dw 0x6a40, 0xc898, 0x6a7f, 0xc898, 0x21, 0 + .dw 0x6ac0, 0xc898, 0x6aff, 0xc898, 0x21, 0 + .dw 0x6b40, 0xc898, 0x6b7f, 0xc898, 0x21, 0 + .dw 0x6bc0, 0xc898, 0x6bff, 0xc898, 0x21, 0 + .dw 0x6c40, 0xc898, 0x6c7f, 0xc898, 0x21, 0 + .dw 0x6cc0, 0xc898, 0x6cff, 0xc898, 0x21, 0 + .dw 0x6d40, 0xc898, 0x6d7f, 0xc898, 0x21, 0 + .dw 0x6dc0, 0xc898, 0x6dff, 0xc898, 0x21, 0 + .dw 0x6e40, 0xc898, 0x6e7f, 0xc898, 0x21, 0 + .dw 0x6ec0, 0xc898, 0x6eff, 0xc898, 0x21, 0 + .dw 0x6f40, 0xc898, 0x6f7f, 0xc898, 0x21, 0 + .dw 0x6fc0, 0xc898, 0x6fff, 0xc898, 0x21, 0 + .dw 0x7040, 0xc898, 0x707f, 0xc898, 0x21, 0 + .dw 0x70c0, 0xc898, 0x70ff, 0xc898, 0x21, 0 + .dw 0x7140, 0xc898, 0x717f, 0xc898, 0x21, 0 + .dw 0x71c0, 0xc898, 0x71ff, 0xc898, 0x21, 0 + .dw 0x7240, 0xc898, 0x727f, 0xc898, 0x21, 0 + .dw 0x72c0, 0xc898, 0x72ff, 0xc898, 0x21, 0 + .dw 0x7340, 0xc898, 0x737f, 0xc898, 0x21, 0 + .dw 0x73c0, 0xc898, 0x73ff, 0xc898, 0x21, 0 + .dw 0x7440, 0xc898, 0x747f, 0xc898, 0x21, 0 + .dw 0x74c0, 0xc898, 0x74ff, 0xc898, 0x21, 0 + .dw 0x7540, 0xc898, 0x757f, 0xc898, 0x21, 0 + .dw 0x75c0, 0xc898, 0x75ff, 0xc898, 0x21, 0 + .dw 0x7640, 0xc898, 0x767f, 0xc898, 0x21, 0 + .dw 0x76c0, 0xc898, 0x76ff, 0xc898, 0x21, 0 + .dw 0x7740, 0xc898, 0x777f, 0xc898, 0x21, 0 + .dw 0x77c0, 0xc898, 0x77ff, 0xc898, 0x21, 0 + .dw 0x7840, 0xc898, 0x787f, 0xc898, 0x21, 0 + .dw 0x78c0, 0xc898, 0x78ff, 0xc898, 0x21, 0 + .dw 0x7940, 0xc898, 0x797f, 0xc898, 0x21, 0 + .dw 0x79c0, 0xc898, 0x9fff, 0xc898, 0x21, 0 + .dw 0xa040, 0xc898, 0xa07f, 0xc898, 0x21, 0 + .dw 0xa0c0, 0xc898, 0xa0ff, 0xc898, 0x21, 0 + .dw 0xa140, 0xc898, 0xa17f, 0xc898, 0x21, 0 + .dw 0xa1c0, 0xc898, 0xa1ff, 0xc898, 0x21, 0 + .dw 0xa240, 0xc898, 0xa27f, 0xc898, 0x21, 0 + .dw 0xa2c0, 0xc898, 0xa2ff, 0xc898, 0x21, 0 + .dw 0xa340, 0xc898, 0xa37f, 0xc898, 0x21, 0 + .dw 0xa3c0, 0xc898, 0xa3ff, 0xc898, 0x21, 0 + .dw 0xa440, 0xc898, 0xa47f, 0xc898, 0x21, 0 + .dw 0xa4c0, 0xc898, 0xa4ff, 0xc898, 0x21, 0 + .dw 0xa540, 0xc898, 0xa57f, 0xc898, 0x21, 0 + .dw 0xa5c0, 0xc898, 0xa5ff, 0xc898, 0x21, 0 + .dw 0xa640, 0xc898, 0xa67f, 0xc898, 0x21, 0 + .dw 0xa6c0, 0xc898, 0xa6ff, 0xc898, 0x21, 0 + .dw 0xa740, 0xc898, 0xa77f, 0xc898, 0x21, 0 + .dw 0xa7c0, 0xc898, 0xa7ff, 0xc898, 0x21, 0 + .dw 0xa840, 0xc898, 0xa87f, 0xc898, 0x21, 0 + .dw 0xa8c0, 0xc898, 0xa8ff, 0xc898, 0x21, 0 + .dw 0xa940, 0xc898, 0xa97f, 0xc898, 0x21, 0 + .dw 0xa9c0, 0xc898, 0xa9ff, 0xc898, 0x21, 0 + .dw 0xaa40, 0xc898, 0xaa7f, 0xc898, 0x21, 0 + .dw 0xaac0, 0xc898, 0xaaff, 0xc898, 0x21, 0 + .dw 0xab40, 0xc898, 0xab7f, 0xc898, 0x21, 0 + .dw 0xabc0, 0xc898, 0xabff, 0xc898, 0x21, 0 + .dw 0xac40, 0xc898, 0xac7f, 0xc898, 0x21, 0 + .dw 0xacc0, 0xc898, 0xacff, 0xc898, 0x21, 0 + .dw 0xad40, 0xc898, 0xad7f, 0xc898, 0x21, 0 + .dw 0xadc0, 0xc898, 0xadff, 0xc898, 0x21, 0 + .dw 0xae40, 0xc898, 0xae7f, 0xc898, 0x21, 0 + .dw 0xaec0, 0xc898, 0xaeff, 0xc898, 0x21, 0 + .dw 0xaf40, 0xc898, 0xaf7f, 0xc898, 0x21, 0 + .dw 0xafc0, 0xc898, 0xafff, 0xc898, 0x21, 0 + .dw 0xb040, 0xc898, 0xb07f, 0xc898, 0x21, 0 + .dw 0xb0c0, 0xc898, 0xb0ff, 0xc898, 0x21, 0 + .dw 0xb140, 0xc898, 0xb17f, 0xc898, 0x21, 0 + .dw 0xb1c0, 0xc898, 0xb1ff, 0xc898, 0x21, 0 + .dw 0xb240, 0xc898, 0xb27f, 0xc898, 0x21, 0 + .dw 0xb2c0, 0xc898, 0xb2ff, 0xc898, 0x21, 0 + .dw 0xb340, 0xc898, 0xb37f, 0xc898, 0x21, 0 + .dw 0xb3c0, 0xc898, 0xb3ff, 0xc898, 0x21, 0 + .dw 0xb440, 0xc898, 0xb47f, 0xc898, 0x21, 0 + .dw 0xb4c0, 0xc898, 0xb4ff, 0xc898, 0x21, 0 + .dw 0xb540, 0xc898, 0xb57f, 0xc898, 0x21, 0 + .dw 0xb5c0, 0xc898, 0xb5ff, 0xc898, 0x21, 0 + .dw 0xb640, 0xc898, 0xb67f, 0xc898, 0x21, 0 + .dw 0xb6c0, 0xc898, 0xb6ff, 0xc898, 0x21, 0 + .dw 0xb740, 0xc898, 0xb77f, 0xc898, 0x21, 0 + .dw 0xb7c0, 0xc898, 0xb7ff, 0xc898, 0x21, 0 + .dw 0xb840, 0xc898, 0xb87f, 0xc898, 0x21, 0 + .dw 0xb8c0, 0xc898, 0xb8ff, 0xc898, 0x21, 0 + .dw 0xb940, 0xc898, 0xb97f, 0xc898, 0x21, 0 + .dw 0xb9c0, 0xc898, 0xdfff, 0xc898, 0x21, 0 + .dw 0xe040, 0xc898, 0xe07f, 0xc898, 0x21, 0 + .dw 0xe0c0, 0xc898, 0xe0ff, 0xc898, 0x21, 0 + .dw 0xe140, 0xc898, 0xe17f, 0xc898, 0x21, 0 + .dw 0xe1c0, 0xc898, 0xe1ff, 0xc898, 0x21, 0 + .dw 0xe240, 0xc898, 0xe27f, 0xc898, 0x21, 0 + .dw 0xe2c0, 0xc898, 0xe2ff, 0xc898, 0x21, 0 + .dw 0xe340, 0xc898, 0xe37f, 0xc898, 0x21, 0 + .dw 0xe3c0, 0xc898, 0xe3ff, 0xc898, 0x21, 0 + .dw 0xe440, 0xc898, 0xe47f, 0xc898, 0x21, 0 + .dw 0xe4c0, 0xc898, 0xe4ff, 0xc898, 0x21, 0 + .dw 0xe540, 0xc898, 0xe57f, 0xc898, 0x21, 0 + .dw 0xe5c0, 0xc898, 0xe5ff, 0xc898, 0x21, 0 + .dw 0xe640, 0xc898, 0xe67f, 0xc898, 0x21, 0 + .dw 0xe6c0, 0xc898, 0xe6ff, 0xc898, 0x21, 0 + .dw 0xe740, 0xc898, 0xe77f, 0xc898, 0x21, 0 + .dw 0xe7c0, 0xc898, 0xe7ff, 0xc898, 0x21, 0 + .dw 0xe840, 0xc898, 0xe87f, 0xc898, 0x21, 0 + .dw 0xe8c0, 0xc898, 0xe8ff, 0xc898, 0x21, 0 + .dw 0xe940, 0xc898, 0xe97f, 0xc898, 0x21, 0 + .dw 0xe9c0, 0xc898, 0xe9ff, 0xc898, 0x21, 0 + .dw 0xea40, 0xc898, 0xea7f, 0xc898, 0x21, 0 + .dw 0xeac0, 0xc898, 0xeaff, 0xc898, 0x21, 0 + .dw 0xeb40, 0xc898, 0xeb7f, 0xc898, 0x21, 0 + .dw 0xebc0, 0xc898, 0xebff, 0xc898, 0x21, 0 + .dw 0xec40, 0xc898, 0xec7f, 0xc898, 0x21, 0 + .dw 0xecc0, 0xc898, 0xecff, 0xc898, 0x21, 0 + .dw 0xed40, 0xc898, 0xed7f, 0xc898, 0x21, 0 + .dw 0xedc0, 0xc898, 0xedff, 0xc898, 0x21, 0 + .dw 0xee40, 0xc898, 0xee7f, 0xc898, 0x21, 0 + .dw 0xeec0, 0xc898, 0xeeff, 0xc898, 0x21, 0 + .dw 0xef40, 0xc898, 0xef7f, 0xc898, 0x21, 0 + .dw 0xefc0, 0xc898, 0xefff, 0xc898, 0x21, 0 + .dw 0xf040, 0xc898, 0xf07f, 0xc898, 0x21, 0 + .dw 0xf0c0, 0xc898, 0xf0ff, 0xc898, 0x21, 0 + .dw 0xf140, 0xc898, 0xf17f, 0xc898, 0x21, 0 + .dw 0xf1c0, 0xc898, 0xf1ff, 0xc898, 0x21, 0 + .dw 0xf240, 0xc898, 0xf27f, 0xc898, 0x21, 0 + .dw 0xf2c0, 0xc898, 0xf2ff, 0xc898, 0x21, 0 + .dw 0xf340, 0xc898, 0xf37f, 0xc898, 0x21, 0 + .dw 0xf3c0, 0xc898, 0xf3ff, 0xc898, 0x21, 0 + .dw 0xf440, 0xc898, 0xf47f, 0xc898, 0x21, 0 + .dw 0xf4c0, 0xc898, 0xf4ff, 0xc898, 0x21, 0 + .dw 0xf540, 0xc898, 0xf57f, 0xc898, 0x21, 0 + .dw 0xf5c0, 0xc898, 0xf5ff, 0xc898, 0x21, 0 + .dw 0xf640, 0xc898, 0xf67f, 0xc898, 0x21, 0 + .dw 0xf6c0, 0xc898, 0xf6ff, 0xc898, 0x21, 0 + .dw 0xf740, 0xc898, 0xf77f, 0xc898, 0x21, 0 + .dw 0xf7c0, 0xc898, 0xf7ff, 0xc898, 0x21, 0 + .dw 0xf840, 0xc898, 0xf87f, 0xc898, 0x21, 0 + .dw 0xf8c0, 0xc898, 0xf8ff, 0xc898, 0x21, 0 + .dw 0xf940, 0xc898, 0xf97f, 0xc898, 0x21, 0 + .dw 0xf9c0, 0xc898, 0x1fff, 0xc899, 0x21, 0 + .dw 0x2040, 0xc899, 0x207f, 0xc899, 0x21, 0 + .dw 0x20c0, 0xc899, 0x20ff, 0xc899, 0x21, 0 + .dw 0x2140, 0xc899, 0x217f, 0xc899, 0x21, 0 + .dw 0x21c0, 0xc899, 0x21ff, 0xc899, 0x21, 0 + .dw 0x2240, 0xc899, 0x227f, 0xc899, 0x21, 0 + .dw 0x22c0, 0xc899, 0x22ff, 0xc899, 0x21, 0 + .dw 0x2340, 0xc899, 0x237f, 0xc899, 0x21, 0 + .dw 0x23c0, 0xc899, 0x23ff, 0xc899, 0x21, 0 + .dw 0x2440, 0xc899, 0x247f, 0xc899, 0x21, 0 + .dw 0x24c0, 0xc899, 0x24ff, 0xc899, 0x21, 0 + .dw 0x2540, 0xc899, 0x257f, 0xc899, 0x21, 0 + .dw 0x25c0, 0xc899, 0x25ff, 0xc899, 0x21, 0 + .dw 0x2640, 0xc899, 0x267f, 0xc899, 0x21, 0 + .dw 0x26c0, 0xc899, 0x26ff, 0xc899, 0x21, 0 + .dw 0x2740, 0xc899, 0x277f, 0xc899, 0x21, 0 + .dw 0x27c0, 0xc899, 0x27ff, 0xc899, 0x21, 0 + .dw 0x2840, 0xc899, 0x287f, 0xc899, 0x21, 0 + .dw 0x28c0, 0xc899, 0x28ff, 0xc899, 0x21, 0 + .dw 0x2940, 0xc899, 0x297f, 0xc899, 0x21, 0 + .dw 0x29c0, 0xc899, 0x29ff, 0xc899, 0x21, 0 + .dw 0x2a40, 0xc899, 0x2a7f, 0xc899, 0x21, 0 + .dw 0x2ac0, 0xc899, 0x2aff, 0xc899, 0x21, 0 + .dw 0x2b40, 0xc899, 0x2b7f, 0xc899, 0x21, 0 + .dw 0x2bc0, 0xc899, 0x2bff, 0xc899, 0x21, 0 + .dw 0x2c40, 0xc899, 0x2c7f, 0xc899, 0x21, 0 + .dw 0x2cc0, 0xc899, 0x2cff, 0xc899, 0x21, 0 + .dw 0x2d40, 0xc899, 0x2d7f, 0xc899, 0x21, 0 + .dw 0x2dc0, 0xc899, 0x2dff, 0xc899, 0x21, 0 + .dw 0x2e40, 0xc899, 0x2e7f, 0xc899, 0x21, 0 + .dw 0x2ec0, 0xc899, 0x2eff, 0xc899, 0x21, 0 + .dw 0x2f40, 0xc899, 0x2f7f, 0xc899, 0x21, 0 + .dw 0x2fc0, 0xc899, 0x2fff, 0xc899, 0x21, 0 + .dw 0x3040, 0xc899, 0x307f, 0xc899, 0x21, 0 + .dw 0x30c0, 0xc899, 0x30ff, 0xc899, 0x21, 0 + .dw 0x3140, 0xc899, 0x317f, 0xc899, 0x21, 0 + .dw 0x31c0, 0xc899, 0x31ff, 0xc899, 0x21, 0 + .dw 0x3240, 0xc899, 0x327f, 0xc899, 0x21, 0 + .dw 0x32c0, 0xc899, 0x32ff, 0xc899, 0x21, 0 + .dw 0x3340, 0xc899, 0x337f, 0xc899, 0x21, 0 + .dw 0x33c0, 0xc899, 0x33ff, 0xc899, 0x21, 0 + .dw 0x3440, 0xc899, 0x347f, 0xc899, 0x21, 0 + .dw 0x34c0, 0xc899, 0x34ff, 0xc899, 0x21, 0 + .dw 0x3540, 0xc899, 0x357f, 0xc899, 0x21, 0 + .dw 0x35c0, 0xc899, 0x35ff, 0xc899, 0x21, 0 + .dw 0x3640, 0xc899, 0x367f, 0xc899, 0x21, 0 + .dw 0x36c0, 0xc899, 0x36ff, 0xc899, 0x21, 0 + .dw 0x3740, 0xc899, 0x377f, 0xc899, 0x21, 0 + .dw 0x37c0, 0xc899, 0x37ff, 0xc899, 0x21, 0 + .dw 0x3840, 0xc899, 0x387f, 0xc899, 0x21, 0 + .dw 0x38c0, 0xc899, 0x38ff, 0xc899, 0x21, 0 + .dw 0x3940, 0xc899, 0x397f, 0xc899, 0x21, 0 + .dw 0x39c0, 0xc899, 0x5fff, 0xc899, 0x21, 0 + .dw 0x6040, 0xc899, 0x607f, 0xc899, 0x21, 0 + .dw 0x60c0, 0xc899, 0x60ff, 0xc899, 0x21, 0 + .dw 0x6140, 0xc899, 0x617f, 0xc899, 0x21, 0 + .dw 0x61c0, 0xc899, 0x61ff, 0xc899, 0x21, 0 + .dw 0x6240, 0xc899, 0x627f, 0xc899, 0x21, 0 + .dw 0x62c0, 0xc899, 0x62ff, 0xc899, 0x21, 0 + .dw 0x6340, 0xc899, 0x637f, 0xc899, 0x21, 0 + .dw 0x63c0, 0xc899, 0x63ff, 0xc899, 0x21, 0 + .dw 0x6440, 0xc899, 0x647f, 0xc899, 0x21, 0 + .dw 0x64c0, 0xc899, 0x64ff, 0xc899, 0x21, 0 + .dw 0x6540, 0xc899, 0x657f, 0xc899, 0x21, 0 + .dw 0x65c0, 0xc899, 0x65ff, 0xc899, 0x21, 0 + .dw 0x6640, 0xc899, 0x667f, 0xc899, 0x21, 0 + .dw 0x66c0, 0xc899, 0x66ff, 0xc899, 0x21, 0 + .dw 0x6740, 0xc899, 0x677f, 0xc899, 0x21, 0 + .dw 0x67c0, 0xc899, 0x67ff, 0xc899, 0x21, 0 + .dw 0x6840, 0xc899, 0x687f, 0xc899, 0x21, 0 + .dw 0x68c0, 0xc899, 0x68ff, 0xc899, 0x21, 0 + .dw 0x6940, 0xc899, 0x697f, 0xc899, 0x21, 0 + .dw 0x69c0, 0xc899, 0x69ff, 0xc899, 0x21, 0 + .dw 0x6a40, 0xc899, 0x6a7f, 0xc899, 0x21, 0 + .dw 0x6ac0, 0xc899, 0x6aff, 0xc899, 0x21, 0 + .dw 0x6b40, 0xc899, 0x6b7f, 0xc899, 0x21, 0 + .dw 0x6bc0, 0xc899, 0x6bff, 0xc899, 0x21, 0 + .dw 0x6c40, 0xc899, 0x6c7f, 0xc899, 0x21, 0 + .dw 0x6cc0, 0xc899, 0x6cff, 0xc899, 0x21, 0 + .dw 0x6d40, 0xc899, 0x6d7f, 0xc899, 0x21, 0 + .dw 0x6dc0, 0xc899, 0x6dff, 0xc899, 0x21, 0 + .dw 0x6e40, 0xc899, 0x6e7f, 0xc899, 0x21, 0 + .dw 0x6ec0, 0xc899, 0x6eff, 0xc899, 0x21, 0 + .dw 0x6f40, 0xc899, 0x6f7f, 0xc899, 0x21, 0 + .dw 0x6fc0, 0xc899, 0x6fff, 0xc899, 0x21, 0 + .dw 0x7040, 0xc899, 0x707f, 0xc899, 0x21, 0 + .dw 0x70c0, 0xc899, 0x70ff, 0xc899, 0x21, 0 + .dw 0x7140, 0xc899, 0x717f, 0xc899, 0x21, 0 + .dw 0x71c0, 0xc899, 0x71ff, 0xc899, 0x21, 0 + .dw 0x7240, 0xc899, 0x727f, 0xc899, 0x21, 0 + .dw 0x72c0, 0xc899, 0x72ff, 0xc899, 0x21, 0 + .dw 0x7340, 0xc899, 0x737f, 0xc899, 0x21, 0 + .dw 0x73c0, 0xc899, 0x73ff, 0xc899, 0x21, 0 + .dw 0x7440, 0xc899, 0x747f, 0xc899, 0x21, 0 + .dw 0x74c0, 0xc899, 0x74ff, 0xc899, 0x21, 0 + .dw 0x7540, 0xc899, 0x757f, 0xc899, 0x21, 0 + .dw 0x75c0, 0xc899, 0x75ff, 0xc899, 0x21, 0 + .dw 0x7640, 0xc899, 0x767f, 0xc899, 0x21, 0 + .dw 0x76c0, 0xc899, 0x76ff, 0xc899, 0x21, 0 + .dw 0x7740, 0xc899, 0x777f, 0xc899, 0x21, 0 + .dw 0x77c0, 0xc899, 0x77ff, 0xc899, 0x21, 0 + .dw 0x7840, 0xc899, 0x787f, 0xc899, 0x21, 0 + .dw 0x78c0, 0xc899, 0x78ff, 0xc899, 0x21, 0 + .dw 0x7940, 0xc899, 0x797f, 0xc899, 0x21, 0 + .dw 0x79c0, 0xc899, 0x9fff, 0xc899, 0x21, 0 + .dw 0xa040, 0xc899, 0xa07f, 0xc899, 0x21, 0 + .dw 0xa0c0, 0xc899, 0xa0ff, 0xc899, 0x21, 0 + .dw 0xa140, 0xc899, 0xa17f, 0xc899, 0x21, 0 + .dw 0xa1c0, 0xc899, 0xa1ff, 0xc899, 0x21, 0 + .dw 0xa240, 0xc899, 0xa27f, 0xc899, 0x21, 0 + .dw 0xa2c0, 0xc899, 0xa2ff, 0xc899, 0x21, 0 + .dw 0xa340, 0xc899, 0xa37f, 0xc899, 0x21, 0 + .dw 0xa3c0, 0xc899, 0xa3ff, 0xc899, 0x21, 0 + .dw 0xa440, 0xc899, 0xa47f, 0xc899, 0x21, 0 + .dw 0xa4c0, 0xc899, 0xa4ff, 0xc899, 0x21, 0 + .dw 0xa540, 0xc899, 0xa57f, 0xc899, 0x21, 0 + .dw 0xa5c0, 0xc899, 0xa5ff, 0xc899, 0x21, 0 + .dw 0xa640, 0xc899, 0xa67f, 0xc899, 0x21, 0 + .dw 0xa6c0, 0xc899, 0xa6ff, 0xc899, 0x21, 0 + .dw 0xa740, 0xc899, 0xa77f, 0xc899, 0x21, 0 + .dw 0xa7c0, 0xc899, 0xa7ff, 0xc899, 0x21, 0 + .dw 0xa840, 0xc899, 0xa87f, 0xc899, 0x21, 0 + .dw 0xa8c0, 0xc899, 0xa8ff, 0xc899, 0x21, 0 + .dw 0xa940, 0xc899, 0xa97f, 0xc899, 0x21, 0 + .dw 0xa9c0, 0xc899, 0xa9ff, 0xc899, 0x21, 0 + .dw 0xaa40, 0xc899, 0xaa7f, 0xc899, 0x21, 0 + .dw 0xaac0, 0xc899, 0xaaff, 0xc899, 0x21, 0 + .dw 0xab40, 0xc899, 0xab7f, 0xc899, 0x21, 0 + .dw 0xabc0, 0xc899, 0xabff, 0xc899, 0x21, 0 + .dw 0xac40, 0xc899, 0xac7f, 0xc899, 0x21, 0 + .dw 0xacc0, 0xc899, 0xacff, 0xc899, 0x21, 0 + .dw 0xad40, 0xc899, 0xad7f, 0xc899, 0x21, 0 + .dw 0xadc0, 0xc899, 0xadff, 0xc899, 0x21, 0 + .dw 0xae40, 0xc899, 0xae7f, 0xc899, 0x21, 0 + .dw 0xaec0, 0xc899, 0xaeff, 0xc899, 0x21, 0 + .dw 0xaf40, 0xc899, 0xaf7f, 0xc899, 0x21, 0 + .dw 0xafc0, 0xc899, 0xafff, 0xc899, 0x21, 0 + .dw 0xb040, 0xc899, 0xb07f, 0xc899, 0x21, 0 + .dw 0xb0c0, 0xc899, 0xb0ff, 0xc899, 0x21, 0 + .dw 0xb140, 0xc899, 0xb17f, 0xc899, 0x21, 0 + .dw 0xb1c0, 0xc899, 0xb1ff, 0xc899, 0x21, 0 + .dw 0xb240, 0xc899, 0xb27f, 0xc899, 0x21, 0 + .dw 0xb2c0, 0xc899, 0xb2ff, 0xc899, 0x21, 0 + .dw 0xb340, 0xc899, 0xb37f, 0xc899, 0x21, 0 + .dw 0xb3c0, 0xc899, 0xb3ff, 0xc899, 0x21, 0 + .dw 0xb440, 0xc899, 0xb47f, 0xc899, 0x21, 0 + .dw 0xb4c0, 0xc899, 0xb4ff, 0xc899, 0x21, 0 + .dw 0xb540, 0xc899, 0xb57f, 0xc899, 0x21, 0 + .dw 0xb5c0, 0xc899, 0xb5ff, 0xc899, 0x21, 0 + .dw 0xb640, 0xc899, 0xb67f, 0xc899, 0x21, 0 + .dw 0xb6c0, 0xc899, 0xb6ff, 0xc899, 0x21, 0 + .dw 0xb740, 0xc899, 0xb77f, 0xc899, 0x21, 0 + .dw 0xb7c0, 0xc899, 0xb7ff, 0xc899, 0x21, 0 + .dw 0xb840, 0xc899, 0xb87f, 0xc899, 0x21, 0 + .dw 0xb8c0, 0xc899, 0xb8ff, 0xc899, 0x21, 0 + .dw 0xb940, 0xc899, 0xb97f, 0xc899, 0x21, 0 + .dw 0xb9c0, 0xc899, 0xdfff, 0xc899, 0x21, 0 + .dw 0xe040, 0xc899, 0xe07f, 0xc899, 0x21, 0 + .dw 0xe0c0, 0xc899, 0xe0ff, 0xc899, 0x21, 0 + .dw 0xe140, 0xc899, 0xe17f, 0xc899, 0x21, 0 + .dw 0xe1c0, 0xc899, 0xe1ff, 0xc899, 0x21, 0 + .dw 0xe240, 0xc899, 0xe27f, 0xc899, 0x21, 0 + .dw 0xe2c0, 0xc899, 0xe2ff, 0xc899, 0x21, 0 + .dw 0xe340, 0xc899, 0xe37f, 0xc899, 0x21, 0 + .dw 0xe3c0, 0xc899, 0xe3ff, 0xc899, 0x21, 0 + .dw 0xe440, 0xc899, 0xe47f, 0xc899, 0x21, 0 + .dw 0xe4c0, 0xc899, 0xe4ff, 0xc899, 0x21, 0 + .dw 0xe540, 0xc899, 0xe57f, 0xc899, 0x21, 0 + .dw 0xe5c0, 0xc899, 0xe5ff, 0xc899, 0x21, 0 + .dw 0xe640, 0xc899, 0xe67f, 0xc899, 0x21, 0 + .dw 0xe6c0, 0xc899, 0xe6ff, 0xc899, 0x21, 0 + .dw 0xe740, 0xc899, 0xe77f, 0xc899, 0x21, 0 + .dw 0xe7c0, 0xc899, 0xe7ff, 0xc899, 0x21, 0 + .dw 0xe840, 0xc899, 0xe87f, 0xc899, 0x21, 0 + .dw 0xe8c0, 0xc899, 0xe8ff, 0xc899, 0x21, 0 + .dw 0xe940, 0xc899, 0xe97f, 0xc899, 0x21, 0 + .dw 0xe9c0, 0xc899, 0xe9ff, 0xc899, 0x21, 0 + .dw 0xea40, 0xc899, 0xea7f, 0xc899, 0x21, 0 + .dw 0xeac0, 0xc899, 0xeaff, 0xc899, 0x21, 0 + .dw 0xeb40, 0xc899, 0xeb7f, 0xc899, 0x21, 0 + .dw 0xebc0, 0xc899, 0xebff, 0xc899, 0x21, 0 + .dw 0xec40, 0xc899, 0xec7f, 0xc899, 0x21, 0 + .dw 0xecc0, 0xc899, 0xecff, 0xc899, 0x21, 0 + .dw 0xed40, 0xc899, 0xed7f, 0xc899, 0x21, 0 + .dw 0xedc0, 0xc899, 0xedff, 0xc899, 0x21, 0 + .dw 0xee40, 0xc899, 0xee7f, 0xc899, 0x21, 0 + .dw 0xeec0, 0xc899, 0xeeff, 0xc899, 0x21, 0 + .dw 0xef40, 0xc899, 0xef7f, 0xc899, 0x21, 0 + .dw 0xefc0, 0xc899, 0xefff, 0xc899, 0x21, 0 + .dw 0xf040, 0xc899, 0xf07f, 0xc899, 0x21, 0 + .dw 0xf0c0, 0xc899, 0xf0ff, 0xc899, 0x21, 0 + .dw 0xf140, 0xc899, 0xf17f, 0xc899, 0x21, 0 + .dw 0xf1c0, 0xc899, 0xf1ff, 0xc899, 0x21, 0 + .dw 0xf240, 0xc899, 0xf27f, 0xc899, 0x21, 0 + .dw 0xf2c0, 0xc899, 0xf2ff, 0xc899, 0x21, 0 + .dw 0xf340, 0xc899, 0xf37f, 0xc899, 0x21, 0 + .dw 0xf3c0, 0xc899, 0xf3ff, 0xc899, 0x21, 0 + .dw 0xf440, 0xc899, 0xf47f, 0xc899, 0x21, 0 + .dw 0xf4c0, 0xc899, 0xf4ff, 0xc899, 0x21, 0 + .dw 0xf540, 0xc899, 0xf57f, 0xc899, 0x21, 0 + .dw 0xf5c0, 0xc899, 0xf5ff, 0xc899, 0x21, 0 + .dw 0xf640, 0xc899, 0xf67f, 0xc899, 0x21, 0 + .dw 0xf6c0, 0xc899, 0xf6ff, 0xc899, 0x21, 0 + .dw 0xf740, 0xc899, 0xf77f, 0xc899, 0x21, 0 + .dw 0xf7c0, 0xc899, 0xf7ff, 0xc899, 0x21, 0 + .dw 0xf840, 0xc899, 0xf87f, 0xc899, 0x21, 0 + .dw 0xf8c0, 0xc899, 0xf8ff, 0xc899, 0x21, 0 + .dw 0xf940, 0xc899, 0xf97f, 0xc899, 0x21, 0 + .dw 0xf9c0, 0xc899, 0x1fff, 0xc89a, 0x21, 0 + .dw 0x2040, 0xc89a, 0x207f, 0xc89a, 0x21, 0 + .dw 0x20c0, 0xc89a, 0x20ff, 0xc89a, 0x21, 0 + .dw 0x2140, 0xc89a, 0x217f, 0xc89a, 0x21, 0 + .dw 0x21c0, 0xc89a, 0x21ff, 0xc89a, 0x21, 0 + .dw 0x2240, 0xc89a, 0x227f, 0xc89a, 0x21, 0 + .dw 0x22c0, 0xc89a, 0x22ff, 0xc89a, 0x21, 0 + .dw 0x2340, 0xc89a, 0x237f, 0xc89a, 0x21, 0 + .dw 0x23c0, 0xc89a, 0x23ff, 0xc89a, 0x21, 0 + .dw 0x2440, 0xc89a, 0x247f, 0xc89a, 0x21, 0 + .dw 0x24c0, 0xc89a, 0x24ff, 0xc89a, 0x21, 0 + .dw 0x2540, 0xc89a, 0x257f, 0xc89a, 0x21, 0 + .dw 0x25c0, 0xc89a, 0x25ff, 0xc89a, 0x21, 0 + .dw 0x2640, 0xc89a, 0x267f, 0xc89a, 0x21, 0 + .dw 0x26c0, 0xc89a, 0x26ff, 0xc89a, 0x21, 0 + .dw 0x2740, 0xc89a, 0x277f, 0xc89a, 0x21, 0 + .dw 0x27c0, 0xc89a, 0x27ff, 0xc89a, 0x21, 0 + .dw 0x2840, 0xc89a, 0x287f, 0xc89a, 0x21, 0 + .dw 0x28c0, 0xc89a, 0x28ff, 0xc89a, 0x21, 0 + .dw 0x2940, 0xc89a, 0x297f, 0xc89a, 0x21, 0 + .dw 0x29c0, 0xc89a, 0x29ff, 0xc89a, 0x21, 0 + .dw 0x2a40, 0xc89a, 0x2a7f, 0xc89a, 0x21, 0 + .dw 0x2ac0, 0xc89a, 0x2aff, 0xc89a, 0x21, 0 + .dw 0x2b40, 0xc89a, 0x2b7f, 0xc89a, 0x21, 0 + .dw 0x2bc0, 0xc89a, 0x2bff, 0xc89a, 0x21, 0 + .dw 0x2c40, 0xc89a, 0x2c7f, 0xc89a, 0x21, 0 + .dw 0x2cc0, 0xc89a, 0x2cff, 0xc89a, 0x21, 0 + .dw 0x2d40, 0xc89a, 0x2d7f, 0xc89a, 0x21, 0 + .dw 0x2dc0, 0xc89a, 0x2dff, 0xc89a, 0x21, 0 + .dw 0x2e40, 0xc89a, 0x2e7f, 0xc89a, 0x21, 0 + .dw 0x2ec0, 0xc89a, 0x2eff, 0xc89a, 0x21, 0 + .dw 0x2f40, 0xc89a, 0x2f7f, 0xc89a, 0x21, 0 + .dw 0x2fc0, 0xc89a, 0x2fff, 0xc89a, 0x21, 0 + .dw 0x3040, 0xc89a, 0x307f, 0xc89a, 0x21, 0 + .dw 0x30c0, 0xc89a, 0x30ff, 0xc89a, 0x21, 0 + .dw 0x3140, 0xc89a, 0x317f, 0xc89a, 0x21, 0 + .dw 0x31c0, 0xc89a, 0x31ff, 0xc89a, 0x21, 0 + .dw 0x3240, 0xc89a, 0x327f, 0xc89a, 0x21, 0 + .dw 0x32c0, 0xc89a, 0x32ff, 0xc89a, 0x21, 0 + .dw 0x3340, 0xc89a, 0x337f, 0xc89a, 0x21, 0 + .dw 0x33c0, 0xc89a, 0x33ff, 0xc89a, 0x21, 0 + .dw 0x3440, 0xc89a, 0x347f, 0xc89a, 0x21, 0 + .dw 0x34c0, 0xc89a, 0x34ff, 0xc89a, 0x21, 0 + .dw 0x3540, 0xc89a, 0x357f, 0xc89a, 0x21, 0 + .dw 0x35c0, 0xc89a, 0x35ff, 0xc89a, 0x21, 0 + .dw 0x3640, 0xc89a, 0x367f, 0xc89a, 0x21, 0 + .dw 0x36c0, 0xc89a, 0x36ff, 0xc89a, 0x21, 0 + .dw 0x3740, 0xc89a, 0x377f, 0xc89a, 0x21, 0 + .dw 0x37c0, 0xc89a, 0x37ff, 0xc89a, 0x21, 0 + .dw 0x3840, 0xc89a, 0x387f, 0xc89a, 0x21, 0 + .dw 0x38c0, 0xc89a, 0x38ff, 0xc89a, 0x21, 0 + .dw 0x3940, 0xc89a, 0x397f, 0xc89a, 0x21, 0 + .dw 0x39c0, 0xc89a, 0x5fff, 0xc89a, 0x21, 0 + .dw 0x6040, 0xc89a, 0x607f, 0xc89a, 0x21, 0 + .dw 0x60c0, 0xc89a, 0x60ff, 0xc89a, 0x21, 0 + .dw 0x6140, 0xc89a, 0x617f, 0xc89a, 0x21, 0 + .dw 0x61c0, 0xc89a, 0x61ff, 0xc89a, 0x21, 0 + .dw 0x6240, 0xc89a, 0x627f, 0xc89a, 0x21, 0 + .dw 0x62c0, 0xc89a, 0x62ff, 0xc89a, 0x21, 0 + .dw 0x6340, 0xc89a, 0x637f, 0xc89a, 0x21, 0 + .dw 0x63c0, 0xc89a, 0x63ff, 0xc89a, 0x21, 0 + .dw 0x6440, 0xc89a, 0x647f, 0xc89a, 0x21, 0 + .dw 0x64c0, 0xc89a, 0x64ff, 0xc89a, 0x21, 0 + .dw 0x6540, 0xc89a, 0x657f, 0xc89a, 0x21, 0 + .dw 0x65c0, 0xc89a, 0x65ff, 0xc89a, 0x21, 0 + .dw 0x6640, 0xc89a, 0x667f, 0xc89a, 0x21, 0 + .dw 0x66c0, 0xc89a, 0x66ff, 0xc89a, 0x21, 0 + .dw 0x6740, 0xc89a, 0x677f, 0xc89a, 0x21, 0 + .dw 0x67c0, 0xc89a, 0x67ff, 0xc89a, 0x21, 0 + .dw 0x6840, 0xc89a, 0x687f, 0xc89a, 0x21, 0 + .dw 0x68c0, 0xc89a, 0x68ff, 0xc89a, 0x21, 0 + .dw 0x6940, 0xc89a, 0x697f, 0xc89a, 0x21, 0 + .dw 0x69c0, 0xc89a, 0x69ff, 0xc89a, 0x21, 0 + .dw 0x6a40, 0xc89a, 0x6a7f, 0xc89a, 0x21, 0 + .dw 0x6ac0, 0xc89a, 0x6aff, 0xc89a, 0x21, 0 + .dw 0x6b40, 0xc89a, 0x6b7f, 0xc89a, 0x21, 0 + .dw 0x6bc0, 0xc89a, 0x6bff, 0xc89a, 0x21, 0 + .dw 0x6c40, 0xc89a, 0x6c7f, 0xc89a, 0x21, 0 + .dw 0x6cc0, 0xc89a, 0x6cff, 0xc89a, 0x21, 0 + .dw 0x6d40, 0xc89a, 0x6d7f, 0xc89a, 0x21, 0 + .dw 0x6dc0, 0xc89a, 0x6dff, 0xc89a, 0x21, 0 + .dw 0x6e40, 0xc89a, 0x6e7f, 0xc89a, 0x21, 0 + .dw 0x6ec0, 0xc89a, 0x6eff, 0xc89a, 0x21, 0 + .dw 0x6f40, 0xc89a, 0x6f7f, 0xc89a, 0x21, 0 + .dw 0x6fc0, 0xc89a, 0x6fff, 0xc89a, 0x21, 0 + .dw 0x7040, 0xc89a, 0x707f, 0xc89a, 0x21, 0 + .dw 0x70c0, 0xc89a, 0x70ff, 0xc89a, 0x21, 0 + .dw 0x7140, 0xc89a, 0x717f, 0xc89a, 0x21, 0 + .dw 0x71c0, 0xc89a, 0x71ff, 0xc89a, 0x21, 0 + .dw 0x7240, 0xc89a, 0x727f, 0xc89a, 0x21, 0 + .dw 0x72c0, 0xc89a, 0x72ff, 0xc89a, 0x21, 0 + .dw 0x7340, 0xc89a, 0x737f, 0xc89a, 0x21, 0 + .dw 0x73c0, 0xc89a, 0x73ff, 0xc89a, 0x21, 0 + .dw 0x7440, 0xc89a, 0x747f, 0xc89a, 0x21, 0 + .dw 0x74c0, 0xc89a, 0x74ff, 0xc89a, 0x21, 0 + .dw 0x7540, 0xc89a, 0x757f, 0xc89a, 0x21, 0 + .dw 0x75c0, 0xc89a, 0x75ff, 0xc89a, 0x21, 0 + .dw 0x7640, 0xc89a, 0x767f, 0xc89a, 0x21, 0 + .dw 0x76c0, 0xc89a, 0x76ff, 0xc89a, 0x21, 0 + .dw 0x7740, 0xc89a, 0x777f, 0xc89a, 0x21, 0 + .dw 0x77c0, 0xc89a, 0x77ff, 0xc89a, 0x21, 0 + .dw 0x7840, 0xc89a, 0x787f, 0xc89a, 0x21, 0 + .dw 0x78c0, 0xc89a, 0x78ff, 0xc89a, 0x21, 0 + .dw 0x7940, 0xc89a, 0x797f, 0xc89a, 0x21, 0 + .dw 0x79c0, 0xc89a, 0x9fff, 0xc89a, 0x21, 0 + .dw 0xa040, 0xc89a, 0xa07f, 0xc89a, 0x21, 0 + .dw 0xa0c0, 0xc89a, 0xa0ff, 0xc89a, 0x21, 0 + .dw 0xa140, 0xc89a, 0xa17f, 0xc89a, 0x21, 0 + .dw 0xa1c0, 0xc89a, 0xa1ff, 0xc89a, 0x21, 0 + .dw 0xa240, 0xc89a, 0xa27f, 0xc89a, 0x21, 0 + .dw 0xa2c0, 0xc89a, 0xa2ff, 0xc89a, 0x21, 0 + .dw 0xa340, 0xc89a, 0xa37f, 0xc89a, 0x21, 0 + .dw 0xa3c0, 0xc89a, 0xa3ff, 0xc89a, 0x21, 0 + .dw 0xa440, 0xc89a, 0xa47f, 0xc89a, 0x21, 0 + .dw 0xa4c0, 0xc89a, 0xa4ff, 0xc89a, 0x21, 0 + .dw 0xa540, 0xc89a, 0xa57f, 0xc89a, 0x21, 0 + .dw 0xa5c0, 0xc89a, 0xa5ff, 0xc89a, 0x21, 0 + .dw 0xa640, 0xc89a, 0xa67f, 0xc89a, 0x21, 0 + .dw 0xa6c0, 0xc89a, 0xa6ff, 0xc89a, 0x21, 0 + .dw 0xa740, 0xc89a, 0xa77f, 0xc89a, 0x21, 0 + .dw 0xa7c0, 0xc89a, 0xa7ff, 0xc89a, 0x21, 0 + .dw 0xa840, 0xc89a, 0xa87f, 0xc89a, 0x21, 0 + .dw 0xa8c0, 0xc89a, 0xa8ff, 0xc89a, 0x21, 0 + .dw 0xa940, 0xc89a, 0xa97f, 0xc89a, 0x21, 0 + .dw 0xa9c0, 0xc89a, 0xa9ff, 0xc89a, 0x21, 0 + .dw 0xaa40, 0xc89a, 0xaa7f, 0xc89a, 0x21, 0 + .dw 0xaac0, 0xc89a, 0xaaff, 0xc89a, 0x21, 0 + .dw 0xab40, 0xc89a, 0xab7f, 0xc89a, 0x21, 0 + .dw 0xabc0, 0xc89a, 0xabff, 0xc89a, 0x21, 0 + .dw 0xac40, 0xc89a, 0xac7f, 0xc89a, 0x21, 0 + .dw 0xacc0, 0xc89a, 0xacff, 0xc89a, 0x21, 0 + .dw 0xad40, 0xc89a, 0xad7f, 0xc89a, 0x21, 0 + .dw 0xadc0, 0xc89a, 0xadff, 0xc89a, 0x21, 0 + .dw 0xae40, 0xc89a, 0xae7f, 0xc89a, 0x21, 0 + .dw 0xaec0, 0xc89a, 0xaeff, 0xc89a, 0x21, 0 + .dw 0xaf40, 0xc89a, 0xaf7f, 0xc89a, 0x21, 0 + .dw 0xafc0, 0xc89a, 0xafff, 0xc89a, 0x21, 0 + .dw 0xb040, 0xc89a, 0xb07f, 0xc89a, 0x21, 0 + .dw 0xb0c0, 0xc89a, 0xb0ff, 0xc89a, 0x21, 0 + .dw 0xb140, 0xc89a, 0xb17f, 0xc89a, 0x21, 0 + .dw 0xb1c0, 0xc89a, 0xb1ff, 0xc89a, 0x21, 0 + .dw 0xb240, 0xc89a, 0xb27f, 0xc89a, 0x21, 0 + .dw 0xb2c0, 0xc89a, 0xb2ff, 0xc89a, 0x21, 0 + .dw 0xb340, 0xc89a, 0xb37f, 0xc89a, 0x21, 0 + .dw 0xb3c0, 0xc89a, 0xb3ff, 0xc89a, 0x21, 0 + .dw 0xb440, 0xc89a, 0xb47f, 0xc89a, 0x21, 0 + .dw 0xb4c0, 0xc89a, 0xb4ff, 0xc89a, 0x21, 0 + .dw 0xb540, 0xc89a, 0xb57f, 0xc89a, 0x21, 0 + .dw 0xb5c0, 0xc89a, 0xb5ff, 0xc89a, 0x21, 0 + .dw 0xb640, 0xc89a, 0xb67f, 0xc89a, 0x21, 0 + .dw 0xb6c0, 0xc89a, 0xb6ff, 0xc89a, 0x21, 0 + .dw 0xb740, 0xc89a, 0xb77f, 0xc89a, 0x21, 0 + .dw 0xb7c0, 0xc89a, 0xb7ff, 0xc89a, 0x21, 0 + .dw 0xb840, 0xc89a, 0xb87f, 0xc89a, 0x21, 0 + .dw 0xb8c0, 0xc89a, 0xb8ff, 0xc89a, 0x21, 0 + .dw 0xb940, 0xc89a, 0xb97f, 0xc89a, 0x21, 0 + .dw 0xb9c0, 0xc89a, 0xdfff, 0xc89a, 0x21, 0 + .dw 0xe040, 0xc89a, 0xe07f, 0xc89a, 0x21, 0 + .dw 0xe0c0, 0xc89a, 0xe0ff, 0xc89a, 0x21, 0 + .dw 0xe140, 0xc89a, 0xe17f, 0xc89a, 0x21, 0 + .dw 0xe1c0, 0xc89a, 0xe1ff, 0xc89a, 0x21, 0 + .dw 0xe240, 0xc89a, 0xe27f, 0xc89a, 0x21, 0 + .dw 0xe2c0, 0xc89a, 0xe2ff, 0xc89a, 0x21, 0 + .dw 0xe340, 0xc89a, 0xe37f, 0xc89a, 0x21, 0 + .dw 0xe3c0, 0xc89a, 0xe3ff, 0xc89a, 0x21, 0 + .dw 0xe440, 0xc89a, 0xe47f, 0xc89a, 0x21, 0 + .dw 0xe4c0, 0xc89a, 0xe4ff, 0xc89a, 0x21, 0 + .dw 0xe540, 0xc89a, 0xe57f, 0xc89a, 0x21, 0 + .dw 0xe5c0, 0xc89a, 0xe5ff, 0xc89a, 0x21, 0 + .dw 0xe640, 0xc89a, 0xe67f, 0xc89a, 0x21, 0 + .dw 0xe6c0, 0xc89a, 0xe6ff, 0xc89a, 0x21, 0 + .dw 0xe740, 0xc89a, 0xe77f, 0xc89a, 0x21, 0 + .dw 0xe7c0, 0xc89a, 0xe7ff, 0xc89a, 0x21, 0 + .dw 0xe840, 0xc89a, 0xe87f, 0xc89a, 0x21, 0 + .dw 0xe8c0, 0xc89a, 0xe8ff, 0xc89a, 0x21, 0 + .dw 0xe940, 0xc89a, 0xe97f, 0xc89a, 0x21, 0 + .dw 0xe9c0, 0xc89a, 0xe9ff, 0xc89a, 0x21, 0 + .dw 0xea40, 0xc89a, 0xea7f, 0xc89a, 0x21, 0 + .dw 0xeac0, 0xc89a, 0xeaff, 0xc89a, 0x21, 0 + .dw 0xeb40, 0xc89a, 0xeb7f, 0xc89a, 0x21, 0 + .dw 0xebc0, 0xc89a, 0xebff, 0xc89a, 0x21, 0 + .dw 0xec40, 0xc89a, 0xec7f, 0xc89a, 0x21, 0 + .dw 0xecc0, 0xc89a, 0xecff, 0xc89a, 0x21, 0 + .dw 0xed40, 0xc89a, 0xed7f, 0xc89a, 0x21, 0 + .dw 0xedc0, 0xc89a, 0xedff, 0xc89a, 0x21, 0 + .dw 0xee40, 0xc89a, 0xee7f, 0xc89a, 0x21, 0 + .dw 0xeec0, 0xc89a, 0xeeff, 0xc89a, 0x21, 0 + .dw 0xef40, 0xc89a, 0xef7f, 0xc89a, 0x21, 0 + .dw 0xefc0, 0xc89a, 0xefff, 0xc89a, 0x21, 0 + .dw 0xf040, 0xc89a, 0xf07f, 0xc89a, 0x21, 0 + .dw 0xf0c0, 0xc89a, 0xf0ff, 0xc89a, 0x21, 0 + .dw 0xf140, 0xc89a, 0xf17f, 0xc89a, 0x21, 0 + .dw 0xf1c0, 0xc89a, 0xf1ff, 0xc89a, 0x21, 0 + .dw 0xf240, 0xc89a, 0xf27f, 0xc89a, 0x21, 0 + .dw 0xf2c0, 0xc89a, 0xf2ff, 0xc89a, 0x21, 0 + .dw 0xf340, 0xc89a, 0xf37f, 0xc89a, 0x21, 0 + .dw 0xf3c0, 0xc89a, 0xf3ff, 0xc89a, 0x21, 0 + .dw 0xf440, 0xc89a, 0xf47f, 0xc89a, 0x21, 0 + .dw 0xf4c0, 0xc89a, 0xf4ff, 0xc89a, 0x21, 0 + .dw 0xf540, 0xc89a, 0xf57f, 0xc89a, 0x21, 0 + .dw 0xf5c0, 0xc89a, 0xf5ff, 0xc89a, 0x21, 0 + .dw 0xf640, 0xc89a, 0xf67f, 0xc89a, 0x21, 0 + .dw 0xf6c0, 0xc89a, 0xf6ff, 0xc89a, 0x21, 0 + .dw 0xf740, 0xc89a, 0xf77f, 0xc89a, 0x21, 0 + .dw 0xf7c0, 0xc89a, 0xf7ff, 0xc89a, 0x21, 0 + .dw 0xf840, 0xc89a, 0xf87f, 0xc89a, 0x21, 0 + .dw 0xf8c0, 0xc89a, 0xf8ff, 0xc89a, 0x21, 0 + .dw 0xf940, 0xc89a, 0xf97f, 0xc89a, 0x21, 0 + .dw 0xf9c0, 0xc89a, 0xffff, 0xc89b, 0x21, 0 + .dw 0x0040, 0xc89c, 0x007f, 0xc89c, 0x21, 0 + .dw 0x00c0, 0xc89c, 0x00ff, 0xc89c, 0x21, 0 + .dw 0x0140, 0xc89c, 0x017f, 0xc89c, 0x21, 0 + .dw 0x01c0, 0xc89c, 0x01ff, 0xc89c, 0x21, 0 + .dw 0x0240, 0xc89c, 0x027f, 0xc89c, 0x21, 0 + .dw 0x02c0, 0xc89c, 0x02ff, 0xc89c, 0x21, 0 + .dw 0x0340, 0xc89c, 0x037f, 0xc89c, 0x21, 0 + .dw 0x03c0, 0xc89c, 0x03ff, 0xc89c, 0x21, 0 + .dw 0x0440, 0xc89c, 0x047f, 0xc89c, 0x21, 0 + .dw 0x04c0, 0xc89c, 0x04ff, 0xc89c, 0x21, 0 + .dw 0x0540, 0xc89c, 0x057f, 0xc89c, 0x21, 0 + .dw 0x05c0, 0xc89c, 0x05ff, 0xc89c, 0x21, 0 + .dw 0x0640, 0xc89c, 0x067f, 0xc89c, 0x21, 0 + .dw 0x06c0, 0xc89c, 0x06ff, 0xc89c, 0x21, 0 + .dw 0x0740, 0xc89c, 0x077f, 0xc89c, 0x21, 0 + .dw 0x07c0, 0xc89c, 0x07ff, 0xc89c, 0x21, 0 + .dw 0x0840, 0xc89c, 0x087f, 0xc89c, 0x21, 0 + .dw 0x08c0, 0xc89c, 0x08ff, 0xc89c, 0x21, 0 + .dw 0x0940, 0xc89c, 0x097f, 0xc89c, 0x21, 0 + .dw 0x09c0, 0xc89c, 0x09ff, 0xc89c, 0x21, 0 + .dw 0x0a40, 0xc89c, 0x0a7f, 0xc89c, 0x21, 0 + .dw 0x0ac0, 0xc89c, 0x0aff, 0xc89c, 0x21, 0 + .dw 0x0b40, 0xc89c, 0x0b7f, 0xc89c, 0x21, 0 + .dw 0x0bc0, 0xc89c, 0x0bff, 0xc89c, 0x21, 0 + .dw 0x0c40, 0xc89c, 0x0c7f, 0xc89c, 0x21, 0 + .dw 0x0cc0, 0xc89c, 0x0cff, 0xc89c, 0x21, 0 + .dw 0x0d40, 0xc89c, 0x0d7f, 0xc89c, 0x21, 0 + .dw 0x0dc0, 0xc89c, 0x0dff, 0xc89c, 0x21, 0 + .dw 0x0e40, 0xc89c, 0x0e7f, 0xc89c, 0x21, 0 + .dw 0x0ec0, 0xc89c, 0x0eff, 0xc89c, 0x21, 0 + .dw 0x0f40, 0xc89c, 0x0f7f, 0xc89c, 0x21, 0 + .dw 0x0fc0, 0xc89c, 0x0fff, 0xc89c, 0x21, 0 + .dw 0x1040, 0xc89c, 0x107f, 0xc89c, 0x21, 0 + .dw 0x10c0, 0xc89c, 0x10ff, 0xc89c, 0x21, 0 + .dw 0x1140, 0xc89c, 0x117f, 0xc89c, 0x21, 0 + .dw 0x11c0, 0xc89c, 0x11ff, 0xc89c, 0x21, 0 + .dw 0x1240, 0xc89c, 0x127f, 0xc89c, 0x21, 0 + .dw 0x12c0, 0xc89c, 0x12ff, 0xc89c, 0x21, 0 + .dw 0x1340, 0xc89c, 0x137f, 0xc89c, 0x21, 0 + .dw 0x13c0, 0xc89c, 0x13ff, 0xc89c, 0x21, 0 + .dw 0x1440, 0xc89c, 0x147f, 0xc89c, 0x21, 0 + .dw 0x14c0, 0xc89c, 0x14ff, 0xc89c, 0x21, 0 + .dw 0x1540, 0xc89c, 0x157f, 0xc89c, 0x21, 0 + .dw 0x15c0, 0xc89c, 0x15ff, 0xc89c, 0x21, 0 + .dw 0x1640, 0xc89c, 0x167f, 0xc89c, 0x21, 0 + .dw 0x16c0, 0xc89c, 0x16ff, 0xc89c, 0x21, 0 + .dw 0x1740, 0xc89c, 0x177f, 0xc89c, 0x21, 0 + .dw 0x17c0, 0xc89c, 0x17ff, 0xc89c, 0x21, 0 + .dw 0x1840, 0xc89c, 0x187f, 0xc89c, 0x21, 0 + .dw 0x18c0, 0xc89c, 0x18ff, 0xc89c, 0x21, 0 + .dw 0x1940, 0xc89c, 0x197f, 0xc89c, 0x21, 0 + .dw 0x19c0, 0xc89c, 0x1fff, 0xc89c, 0x21, 0 + .dw 0x2040, 0xc89c, 0x207f, 0xc89c, 0x21, 0 + .dw 0x20c0, 0xc89c, 0x20ff, 0xc89c, 0x21, 0 + .dw 0x2140, 0xc89c, 0x217f, 0xc89c, 0x21, 0 + .dw 0x21c0, 0xc89c, 0x21ff, 0xc89c, 0x21, 0 + .dw 0x2240, 0xc89c, 0x227f, 0xc89c, 0x21, 0 + .dw 0x22c0, 0xc89c, 0x22ff, 0xc89c, 0x21, 0 + .dw 0x2340, 0xc89c, 0x237f, 0xc89c, 0x21, 0 + .dw 0x23c0, 0xc89c, 0x23ff, 0xc89c, 0x21, 0 + .dw 0x2440, 0xc89c, 0x247f, 0xc89c, 0x21, 0 + .dw 0x24c0, 0xc89c, 0x24ff, 0xc89c, 0x21, 0 + .dw 0x2540, 0xc89c, 0x257f, 0xc89c, 0x21, 0 + .dw 0x25c0, 0xc89c, 0x25ff, 0xc89c, 0x21, 0 + .dw 0x2640, 0xc89c, 0x267f, 0xc89c, 0x21, 0 + .dw 0x26c0, 0xc89c, 0x26ff, 0xc89c, 0x21, 0 + .dw 0x2740, 0xc89c, 0x277f, 0xc89c, 0x21, 0 + .dw 0x27c0, 0xc89c, 0x27ff, 0xc89c, 0x21, 0 + .dw 0x2840, 0xc89c, 0x287f, 0xc89c, 0x21, 0 + .dw 0x28c0, 0xc89c, 0x28ff, 0xc89c, 0x21, 0 + .dw 0x2940, 0xc89c, 0x297f, 0xc89c, 0x21, 0 + .dw 0x29c0, 0xc89c, 0x29ff, 0xc89c, 0x21, 0 + .dw 0x2a40, 0xc89c, 0x2a7f, 0xc89c, 0x21, 0 + .dw 0x2ac0, 0xc89c, 0x2aff, 0xc89c, 0x21, 0 + .dw 0x2b40, 0xc89c, 0x2b7f, 0xc89c, 0x21, 0 + .dw 0x2bc0, 0xc89c, 0x2bff, 0xc89c, 0x21, 0 + .dw 0x2c40, 0xc89c, 0x2c7f, 0xc89c, 0x21, 0 + .dw 0x2cc0, 0xc89c, 0x2cff, 0xc89c, 0x21, 0 + .dw 0x2d40, 0xc89c, 0x2d7f, 0xc89c, 0x21, 0 + .dw 0x2dc0, 0xc89c, 0x2dff, 0xc89c, 0x21, 0 + .dw 0x2e40, 0xc89c, 0x2e7f, 0xc89c, 0x21, 0 + .dw 0x2ec0, 0xc89c, 0x2eff, 0xc89c, 0x21, 0 + .dw 0x2f40, 0xc89c, 0x2f7f, 0xc89c, 0x21, 0 + .dw 0x2fc0, 0xc89c, 0x2fff, 0xc89c, 0x21, 0 + .dw 0x3040, 0xc89c, 0x307f, 0xc89c, 0x21, 0 + .dw 0x30c0, 0xc89c, 0x30ff, 0xc89c, 0x21, 0 + .dw 0x3140, 0xc89c, 0x317f, 0xc89c, 0x21, 0 + .dw 0x31c0, 0xc89c, 0x31ff, 0xc89c, 0x21, 0 + .dw 0x3240, 0xc89c, 0x327f, 0xc89c, 0x21, 0 + .dw 0x32c0, 0xc89c, 0x32ff, 0xc89c, 0x21, 0 + .dw 0x3340, 0xc89c, 0x337f, 0xc89c, 0x21, 0 + .dw 0x33c0, 0xc89c, 0x33ff, 0xc89c, 0x21, 0 + .dw 0x3440, 0xc89c, 0x347f, 0xc89c, 0x21, 0 + .dw 0x34c0, 0xc89c, 0x34ff, 0xc89c, 0x21, 0 + .dw 0x3540, 0xc89c, 0x357f, 0xc89c, 0x21, 0 + .dw 0x35c0, 0xc89c, 0x35ff, 0xc89c, 0x21, 0 + .dw 0x3640, 0xc89c, 0x367f, 0xc89c, 0x21, 0 + .dw 0x36c0, 0xc89c, 0x36ff, 0xc89c, 0x21, 0 + .dw 0x3740, 0xc89c, 0x377f, 0xc89c, 0x21, 0 + .dw 0x37c0, 0xc89c, 0x37ff, 0xc89c, 0x21, 0 + .dw 0x3840, 0xc89c, 0x387f, 0xc89c, 0x21, 0 + .dw 0x38c0, 0xc89c, 0x38ff, 0xc89c, 0x21, 0 + .dw 0x3940, 0xc89c, 0x397f, 0xc89c, 0x21, 0 + .dw 0x39c0, 0xc89c, 0x3fff, 0xc89c, 0x21, 0 + .dw 0x4040, 0xc89c, 0x407f, 0xc89c, 0x21, 0 + .dw 0x40c0, 0xc89c, 0x40ff, 0xc89c, 0x21, 0 + .dw 0x4140, 0xc89c, 0x417f, 0xc89c, 0x21, 0 + .dw 0x41c0, 0xc89c, 0x41ff, 0xc89c, 0x21, 0 + .dw 0x4240, 0xc89c, 0x427f, 0xc89c, 0x21, 0 + .dw 0x42c0, 0xc89c, 0x42ff, 0xc89c, 0x21, 0 + .dw 0x4340, 0xc89c, 0x437f, 0xc89c, 0x21, 0 + .dw 0x43c0, 0xc89c, 0x43ff, 0xc89c, 0x21, 0 + .dw 0x4440, 0xc89c, 0x447f, 0xc89c, 0x21, 0 + .dw 0x44c0, 0xc89c, 0x44ff, 0xc89c, 0x21, 0 + .dw 0x4540, 0xc89c, 0x457f, 0xc89c, 0x21, 0 + .dw 0x45c0, 0xc89c, 0x45ff, 0xc89c, 0x21, 0 + .dw 0x4640, 0xc89c, 0x467f, 0xc89c, 0x21, 0 + .dw 0x46c0, 0xc89c, 0x46ff, 0xc89c, 0x21, 0 + .dw 0x4740, 0xc89c, 0x477f, 0xc89c, 0x21, 0 + .dw 0x47c0, 0xc89c, 0x47ff, 0xc89c, 0x21, 0 + .dw 0x4840, 0xc89c, 0x487f, 0xc89c, 0x21, 0 + .dw 0x48c0, 0xc89c, 0x48ff, 0xc89c, 0x21, 0 + .dw 0x4940, 0xc89c, 0x497f, 0xc89c, 0x21, 0 + .dw 0x49c0, 0xc89c, 0x49ff, 0xc89c, 0x21, 0 + .dw 0x4a40, 0xc89c, 0x4a7f, 0xc89c, 0x21, 0 + .dw 0x4ac0, 0xc89c, 0x4aff, 0xc89c, 0x21, 0 + .dw 0x4b40, 0xc89c, 0x4b7f, 0xc89c, 0x21, 0 + .dw 0x4bc0, 0xc89c, 0x4bff, 0xc89c, 0x21, 0 + .dw 0x4c40, 0xc89c, 0x4c7f, 0xc89c, 0x21, 0 + .dw 0x4cc0, 0xc89c, 0x4cff, 0xc89c, 0x21, 0 + .dw 0x4d40, 0xc89c, 0x4d7f, 0xc89c, 0x21, 0 + .dw 0x4dc0, 0xc89c, 0x4dff, 0xc89c, 0x21, 0 + .dw 0x4e40, 0xc89c, 0x4e7f, 0xc89c, 0x21, 0 + .dw 0x4ec0, 0xc89c, 0x4eff, 0xc89c, 0x21, 0 + .dw 0x4f40, 0xc89c, 0x4f7f, 0xc89c, 0x21, 0 + .dw 0x4fc0, 0xc89c, 0x4fff, 0xc89c, 0x21, 0 + .dw 0x5040, 0xc89c, 0x507f, 0xc89c, 0x21, 0 + .dw 0x50c0, 0xc89c, 0x50ff, 0xc89c, 0x21, 0 + .dw 0x5140, 0xc89c, 0x517f, 0xc89c, 0x21, 0 + .dw 0x51c0, 0xc89c, 0x51ff, 0xc89c, 0x21, 0 + .dw 0x5240, 0xc89c, 0x527f, 0xc89c, 0x21, 0 + .dw 0x52c0, 0xc89c, 0x52ff, 0xc89c, 0x21, 0 + .dw 0x5340, 0xc89c, 0x537f, 0xc89c, 0x21, 0 + .dw 0x53c0, 0xc89c, 0x53ff, 0xc89c, 0x21, 0 + .dw 0x5440, 0xc89c, 0x547f, 0xc89c, 0x21, 0 + .dw 0x54c0, 0xc89c, 0x54ff, 0xc89c, 0x21, 0 + .dw 0x5540, 0xc89c, 0x557f, 0xc89c, 0x21, 0 + .dw 0x55c0, 0xc89c, 0x55ff, 0xc89c, 0x21, 0 + .dw 0x5640, 0xc89c, 0x567f, 0xc89c, 0x21, 0 + .dw 0x56c0, 0xc89c, 0x56ff, 0xc89c, 0x21, 0 + .dw 0x5740, 0xc89c, 0x577f, 0xc89c, 0x21, 0 + .dw 0x57c0, 0xc89c, 0x57ff, 0xc89c, 0x21, 0 + .dw 0x5840, 0xc89c, 0x587f, 0xc89c, 0x21, 0 + .dw 0x58c0, 0xc89c, 0x58ff, 0xc89c, 0x21, 0 + .dw 0x5940, 0xc89c, 0x597f, 0xc89c, 0x21, 0 + .dw 0x59c0, 0xc89c, 0x5fff, 0xc89c, 0x21, 0 + .dw 0x6040, 0xc89c, 0x607f, 0xc89c, 0x21, 0 + .dw 0x60c0, 0xc89c, 0x60ff, 0xc89c, 0x21, 0 + .dw 0x6140, 0xc89c, 0x617f, 0xc89c, 0x21, 0 + .dw 0x61c0, 0xc89c, 0x61ff, 0xc89c, 0x21, 0 + .dw 0x6240, 0xc89c, 0x627f, 0xc89c, 0x21, 0 + .dw 0x62c0, 0xc89c, 0x62ff, 0xc89c, 0x21, 0 + .dw 0x6340, 0xc89c, 0x637f, 0xc89c, 0x21, 0 + .dw 0x63c0, 0xc89c, 0x63ff, 0xc89c, 0x21, 0 + .dw 0x6440, 0xc89c, 0x647f, 0xc89c, 0x21, 0 + .dw 0x64c0, 0xc89c, 0x64ff, 0xc89c, 0x21, 0 + .dw 0x6540, 0xc89c, 0x657f, 0xc89c, 0x21, 0 + .dw 0x65c0, 0xc89c, 0x65ff, 0xc89c, 0x21, 0 + .dw 0x6640, 0xc89c, 0x667f, 0xc89c, 0x21, 0 + .dw 0x66c0, 0xc89c, 0x66ff, 0xc89c, 0x21, 0 + .dw 0x6740, 0xc89c, 0x677f, 0xc89c, 0x21, 0 + .dw 0x67c0, 0xc89c, 0x67ff, 0xc89c, 0x21, 0 + .dw 0x6840, 0xc89c, 0x687f, 0xc89c, 0x21, 0 + .dw 0x68c0, 0xc89c, 0x68ff, 0xc89c, 0x21, 0 + .dw 0x6940, 0xc89c, 0x697f, 0xc89c, 0x21, 0 + .dw 0x69c0, 0xc89c, 0x69ff, 0xc89c, 0x21, 0 + .dw 0x6a40, 0xc89c, 0x6a7f, 0xc89c, 0x21, 0 + .dw 0x6ac0, 0xc89c, 0x6aff, 0xc89c, 0x21, 0 + .dw 0x6b40, 0xc89c, 0x6b7f, 0xc89c, 0x21, 0 + .dw 0x6bc0, 0xc89c, 0x6bff, 0xc89c, 0x21, 0 + .dw 0x6c40, 0xc89c, 0x6c7f, 0xc89c, 0x21, 0 + .dw 0x6cc0, 0xc89c, 0x6cff, 0xc89c, 0x21, 0 + .dw 0x6d40, 0xc89c, 0x6d7f, 0xc89c, 0x21, 0 + .dw 0x6dc0, 0xc89c, 0x6dff, 0xc89c, 0x21, 0 + .dw 0x6e40, 0xc89c, 0x6e7f, 0xc89c, 0x21, 0 + .dw 0x6ec0, 0xc89c, 0x6eff, 0xc89c, 0x21, 0 + .dw 0x6f40, 0xc89c, 0x6f7f, 0xc89c, 0x21, 0 + .dw 0x6fc0, 0xc89c, 0x6fff, 0xc89c, 0x21, 0 + .dw 0x7040, 0xc89c, 0x707f, 0xc89c, 0x21, 0 + .dw 0x70c0, 0xc89c, 0x70ff, 0xc89c, 0x21, 0 + .dw 0x7140, 0xc89c, 0x717f, 0xc89c, 0x21, 0 + .dw 0x71c0, 0xc89c, 0x71ff, 0xc89c, 0x21, 0 + .dw 0x7240, 0xc89c, 0x727f, 0xc89c, 0x21, 0 + .dw 0x72c0, 0xc89c, 0x72ff, 0xc89c, 0x21, 0 + .dw 0x7340, 0xc89c, 0x737f, 0xc89c, 0x21, 0 + .dw 0x73c0, 0xc89c, 0x73ff, 0xc89c, 0x21, 0 + .dw 0x7440, 0xc89c, 0x747f, 0xc89c, 0x21, 0 + .dw 0x74c0, 0xc89c, 0x74ff, 0xc89c, 0x21, 0 + .dw 0x7540, 0xc89c, 0x757f, 0xc89c, 0x21, 0 + .dw 0x75c0, 0xc89c, 0x75ff, 0xc89c, 0x21, 0 + .dw 0x7640, 0xc89c, 0x767f, 0xc89c, 0x21, 0 + .dw 0x76c0, 0xc89c, 0x76ff, 0xc89c, 0x21, 0 + .dw 0x7740, 0xc89c, 0x777f, 0xc89c, 0x21, 0 + .dw 0x77c0, 0xc89c, 0x77ff, 0xc89c, 0x21, 0 + .dw 0x7840, 0xc89c, 0x787f, 0xc89c, 0x21, 0 + .dw 0x78c0, 0xc89c, 0x78ff, 0xc89c, 0x21, 0 + .dw 0x7940, 0xc89c, 0x797f, 0xc89c, 0x21, 0 + .dw 0x79c0, 0xc89c, 0x7fff, 0xc89c, 0x21, 0 + .dw 0x8040, 0xc89c, 0x807f, 0xc89c, 0x21, 0 + .dw 0x80c0, 0xc89c, 0x80ff, 0xc89c, 0x21, 0 + .dw 0x8140, 0xc89c, 0x817f, 0xc89c, 0x21, 0 + .dw 0x81c0, 0xc89c, 0x81ff, 0xc89c, 0x21, 0 + .dw 0x8240, 0xc89c, 0x827f, 0xc89c, 0x21, 0 + .dw 0x82c0, 0xc89c, 0x82ff, 0xc89c, 0x21, 0 + .dw 0x8340, 0xc89c, 0x837f, 0xc89c, 0x21, 0 + .dw 0x83c0, 0xc89c, 0x83ff, 0xc89c, 0x21, 0 + .dw 0x8440, 0xc89c, 0x847f, 0xc89c, 0x21, 0 + .dw 0x84c0, 0xc89c, 0x84ff, 0xc89c, 0x21, 0 + .dw 0x8540, 0xc89c, 0x857f, 0xc89c, 0x21, 0 + .dw 0x85c0, 0xc89c, 0x85ff, 0xc89c, 0x21, 0 + .dw 0x8640, 0xc89c, 0x867f, 0xc89c, 0x21, 0 + .dw 0x86c0, 0xc89c, 0x86ff, 0xc89c, 0x21, 0 + .dw 0x8740, 0xc89c, 0x877f, 0xc89c, 0x21, 0 + .dw 0x87c0, 0xc89c, 0x87ff, 0xc89c, 0x21, 0 + .dw 0x8840, 0xc89c, 0x887f, 0xc89c, 0x21, 0 + .dw 0x88c0, 0xc89c, 0x88ff, 0xc89c, 0x21, 0 + .dw 0x8940, 0xc89c, 0x897f, 0xc89c, 0x21, 0 + .dw 0x89c0, 0xc89c, 0x89ff, 0xc89c, 0x21, 0 + .dw 0x8a40, 0xc89c, 0x8a7f, 0xc89c, 0x21, 0 + .dw 0x8ac0, 0xc89c, 0x8aff, 0xc89c, 0x21, 0 + .dw 0x8b40, 0xc89c, 0x8b7f, 0xc89c, 0x21, 0 + .dw 0x8bc0, 0xc89c, 0x8bff, 0xc89c, 0x21, 0 + .dw 0x8c40, 0xc89c, 0x8c7f, 0xc89c, 0x21, 0 + .dw 0x8cc0, 0xc89c, 0x8cff, 0xc89c, 0x21, 0 + .dw 0x8d40, 0xc89c, 0x8d7f, 0xc89c, 0x21, 0 + .dw 0x8dc0, 0xc89c, 0x8dff, 0xc89c, 0x21, 0 + .dw 0x8e40, 0xc89c, 0x8e7f, 0xc89c, 0x21, 0 + .dw 0x8ec0, 0xc89c, 0x8eff, 0xc89c, 0x21, 0 + .dw 0x8f40, 0xc89c, 0x8f7f, 0xc89c, 0x21, 0 + .dw 0x8fc0, 0xc89c, 0x8fff, 0xc89c, 0x21, 0 + .dw 0x9040, 0xc89c, 0x907f, 0xc89c, 0x21, 0 + .dw 0x90c0, 0xc89c, 0x90ff, 0xc89c, 0x21, 0 + .dw 0x9140, 0xc89c, 0x917f, 0xc89c, 0x21, 0 + .dw 0x91c0, 0xc89c, 0x91ff, 0xc89c, 0x21, 0 + .dw 0x9240, 0xc89c, 0x927f, 0xc89c, 0x21, 0 + .dw 0x92c0, 0xc89c, 0x92ff, 0xc89c, 0x21, 0 + .dw 0x9340, 0xc89c, 0x937f, 0xc89c, 0x21, 0 + .dw 0x93c0, 0xc89c, 0x93ff, 0xc89c, 0x21, 0 + .dw 0x9440, 0xc89c, 0x947f, 0xc89c, 0x21, 0 + .dw 0x94c0, 0xc89c, 0x94ff, 0xc89c, 0x21, 0 + .dw 0x9540, 0xc89c, 0x957f, 0xc89c, 0x21, 0 + .dw 0x95c0, 0xc89c, 0x95ff, 0xc89c, 0x21, 0 + .dw 0x9640, 0xc89c, 0x967f, 0xc89c, 0x21, 0 + .dw 0x96c0, 0xc89c, 0x96ff, 0xc89c, 0x21, 0 + .dw 0x9740, 0xc89c, 0x977f, 0xc89c, 0x21, 0 + .dw 0x97c0, 0xc89c, 0x97ff, 0xc89c, 0x21, 0 + .dw 0x9840, 0xc89c, 0x987f, 0xc89c, 0x21, 0 + .dw 0x98c0, 0xc89c, 0x98ff, 0xc89c, 0x21, 0 + .dw 0x9940, 0xc89c, 0x997f, 0xc89c, 0x21, 0 + .dw 0x99c0, 0xc89c, 0x9fff, 0xc89c, 0x21, 0 + .dw 0xa040, 0xc89c, 0xa07f, 0xc89c, 0x21, 0 + .dw 0xa0c0, 0xc89c, 0xa0ff, 0xc89c, 0x21, 0 + .dw 0xa140, 0xc89c, 0xa17f, 0xc89c, 0x21, 0 + .dw 0xa1c0, 0xc89c, 0xa1ff, 0xc89c, 0x21, 0 + .dw 0xa240, 0xc89c, 0xa27f, 0xc89c, 0x21, 0 + .dw 0xa2c0, 0xc89c, 0xa2ff, 0xc89c, 0x21, 0 + .dw 0xa340, 0xc89c, 0xa37f, 0xc89c, 0x21, 0 + .dw 0xa3c0, 0xc89c, 0xa3ff, 0xc89c, 0x21, 0 + .dw 0xa440, 0xc89c, 0xa47f, 0xc89c, 0x21, 0 + .dw 0xa4c0, 0xc89c, 0xa4ff, 0xc89c, 0x21, 0 + .dw 0xa540, 0xc89c, 0xa57f, 0xc89c, 0x21, 0 + .dw 0xa5c0, 0xc89c, 0xa5ff, 0xc89c, 0x21, 0 + .dw 0xa640, 0xc89c, 0xa67f, 0xc89c, 0x21, 0 + .dw 0xa6c0, 0xc89c, 0xa6ff, 0xc89c, 0x21, 0 + .dw 0xa740, 0xc89c, 0xa77f, 0xc89c, 0x21, 0 + .dw 0xa7c0, 0xc89c, 0xa7ff, 0xc89c, 0x21, 0 + .dw 0xa840, 0xc89c, 0xa87f, 0xc89c, 0x21, 0 + .dw 0xa8c0, 0xc89c, 0xa8ff, 0xc89c, 0x21, 0 + .dw 0xa940, 0xc89c, 0xa97f, 0xc89c, 0x21, 0 + .dw 0xa9c0, 0xc89c, 0xa9ff, 0xc89c, 0x21, 0 + .dw 0xaa40, 0xc89c, 0xaa7f, 0xc89c, 0x21, 0 + .dw 0xaac0, 0xc89c, 0xaaff, 0xc89c, 0x21, 0 + .dw 0xab40, 0xc89c, 0xab7f, 0xc89c, 0x21, 0 + .dw 0xabc0, 0xc89c, 0xabff, 0xc89c, 0x21, 0 + .dw 0xac40, 0xc89c, 0xac7f, 0xc89c, 0x21, 0 + .dw 0xacc0, 0xc89c, 0xacff, 0xc89c, 0x21, 0 + .dw 0xad40, 0xc89c, 0xad7f, 0xc89c, 0x21, 0 + .dw 0xadc0, 0xc89c, 0xadff, 0xc89c, 0x21, 0 + .dw 0xae40, 0xc89c, 0xae7f, 0xc89c, 0x21, 0 + .dw 0xaec0, 0xc89c, 0xaeff, 0xc89c, 0x21, 0 + .dw 0xaf40, 0xc89c, 0xaf7f, 0xc89c, 0x21, 0 + .dw 0xafc0, 0xc89c, 0xafff, 0xc89c, 0x21, 0 + .dw 0xb040, 0xc89c, 0xb07f, 0xc89c, 0x21, 0 + .dw 0xb0c0, 0xc89c, 0xb0ff, 0xc89c, 0x21, 0 + .dw 0xb140, 0xc89c, 0xb17f, 0xc89c, 0x21, 0 + .dw 0xb1c0, 0xc89c, 0xb1ff, 0xc89c, 0x21, 0 + .dw 0xb240, 0xc89c, 0xb27f, 0xc89c, 0x21, 0 + .dw 0xb2c0, 0xc89c, 0xb2ff, 0xc89c, 0x21, 0 + .dw 0xb340, 0xc89c, 0xb37f, 0xc89c, 0x21, 0 + .dw 0xb3c0, 0xc89c, 0xb3ff, 0xc89c, 0x21, 0 + .dw 0xb440, 0xc89c, 0xb47f, 0xc89c, 0x21, 0 + .dw 0xb4c0, 0xc89c, 0xb4ff, 0xc89c, 0x21, 0 + .dw 0xb540, 0xc89c, 0xb57f, 0xc89c, 0x21, 0 + .dw 0xb5c0, 0xc89c, 0xb5ff, 0xc89c, 0x21, 0 + .dw 0xb640, 0xc89c, 0xb67f, 0xc89c, 0x21, 0 + .dw 0xb6c0, 0xc89c, 0xb6ff, 0xc89c, 0x21, 0 + .dw 0xb740, 0xc89c, 0xb77f, 0xc89c, 0x21, 0 + .dw 0xb7c0, 0xc89c, 0xb7ff, 0xc89c, 0x21, 0 + .dw 0xb840, 0xc89c, 0xb87f, 0xc89c, 0x21, 0 + .dw 0xb8c0, 0xc89c, 0xb8ff, 0xc89c, 0x21, 0 + .dw 0xb940, 0xc89c, 0xb97f, 0xc89c, 0x21, 0 + .dw 0xb9c0, 0xc89c, 0xbfff, 0xc89c, 0x21, 0 + .dw 0xc040, 0xc89c, 0xc07f, 0xc89c, 0x21, 0 + .dw 0xc0c0, 0xc89c, 0xc0ff, 0xc89c, 0x21, 0 + .dw 0xc140, 0xc89c, 0xc17f, 0xc89c, 0x21, 0 + .dw 0xc1c0, 0xc89c, 0xc1ff, 0xc89c, 0x21, 0 + .dw 0xc240, 0xc89c, 0xc27f, 0xc89c, 0x21, 0 + .dw 0xc2c0, 0xc89c, 0xc2ff, 0xc89c, 0x21, 0 + .dw 0xc340, 0xc89c, 0xc37f, 0xc89c, 0x21, 0 + .dw 0xc3c0, 0xc89c, 0xc3ff, 0xc89c, 0x21, 0 + .dw 0xc440, 0xc89c, 0xc47f, 0xc89c, 0x21, 0 + .dw 0xc4c0, 0xc89c, 0xc4ff, 0xc89c, 0x21, 0 + .dw 0xc540, 0xc89c, 0xc57f, 0xc89c, 0x21, 0 + .dw 0xc5c0, 0xc89c, 0xc5ff, 0xc89c, 0x21, 0 + .dw 0xc640, 0xc89c, 0xc67f, 0xc89c, 0x21, 0 + .dw 0xc6c0, 0xc89c, 0xc6ff, 0xc89c, 0x21, 0 + .dw 0xc740, 0xc89c, 0xc77f, 0xc89c, 0x21, 0 + .dw 0xc7c0, 0xc89c, 0xc7ff, 0xc89c, 0x21, 0 + .dw 0xc840, 0xc89c, 0xc87f, 0xc89c, 0x21, 0 + .dw 0xc8c0, 0xc89c, 0xc8ff, 0xc89c, 0x21, 0 + .dw 0xc940, 0xc89c, 0xc97f, 0xc89c, 0x21, 0 + .dw 0xc9c0, 0xc89c, 0xc9ff, 0xc89c, 0x21, 0 + .dw 0xca40, 0xc89c, 0xca7f, 0xc89c, 0x21, 0 + .dw 0xcac0, 0xc89c, 0xcaff, 0xc89c, 0x21, 0 + .dw 0xcb40, 0xc89c, 0xcb7f, 0xc89c, 0x21, 0 + .dw 0xcbc0, 0xc89c, 0xcbff, 0xc89c, 0x21, 0 + .dw 0xcc40, 0xc89c, 0xcc7f, 0xc89c, 0x21, 0 + .dw 0xccc0, 0xc89c, 0xccff, 0xc89c, 0x21, 0 + .dw 0xcd40, 0xc89c, 0xcd7f, 0xc89c, 0x21, 0 + .dw 0xcdc0, 0xc89c, 0xcdff, 0xc89c, 0x21, 0 + .dw 0xce40, 0xc89c, 0xce7f, 0xc89c, 0x21, 0 + .dw 0xcec0, 0xc89c, 0xceff, 0xc89c, 0x21, 0 + .dw 0xcf40, 0xc89c, 0xcf7f, 0xc89c, 0x21, 0 + .dw 0xcfc0, 0xc89c, 0xcfff, 0xc89c, 0x21, 0 + .dw 0xd040, 0xc89c, 0xd07f, 0xc89c, 0x21, 0 + .dw 0xd0c0, 0xc89c, 0xd0ff, 0xc89c, 0x21, 0 + .dw 0xd140, 0xc89c, 0xd17f, 0xc89c, 0x21, 0 + .dw 0xd1c0, 0xc89c, 0xd1ff, 0xc89c, 0x21, 0 + .dw 0xd240, 0xc89c, 0xd27f, 0xc89c, 0x21, 0 + .dw 0xd2c0, 0xc89c, 0xd2ff, 0xc89c, 0x21, 0 + .dw 0xd340, 0xc89c, 0xd37f, 0xc89c, 0x21, 0 + .dw 0xd3c0, 0xc89c, 0xd3ff, 0xc89c, 0x21, 0 + .dw 0xd440, 0xc89c, 0xd47f, 0xc89c, 0x21, 0 + .dw 0xd4c0, 0xc89c, 0xd4ff, 0xc89c, 0x21, 0 + .dw 0xd540, 0xc89c, 0xd57f, 0xc89c, 0x21, 0 + .dw 0xd5c0, 0xc89c, 0xd5ff, 0xc89c, 0x21, 0 + .dw 0xd640, 0xc89c, 0xd67f, 0xc89c, 0x21, 0 + .dw 0xd6c0, 0xc89c, 0xd6ff, 0xc89c, 0x21, 0 + .dw 0xd740, 0xc89c, 0xd77f, 0xc89c, 0x21, 0 + .dw 0xd7c0, 0xc89c, 0xd7ff, 0xc89c, 0x21, 0 + .dw 0xd840, 0xc89c, 0xd87f, 0xc89c, 0x21, 0 + .dw 0xd8c0, 0xc89c, 0xd8ff, 0xc89c, 0x21, 0 + .dw 0xd940, 0xc89c, 0xd97f, 0xc89c, 0x21, 0 + .dw 0xd9c0, 0xc89c, 0xdfff, 0xc89c, 0x21, 0 + .dw 0xe040, 0xc89c, 0xe07f, 0xc89c, 0x21, 0 + .dw 0xe0c0, 0xc89c, 0xe0ff, 0xc89c, 0x21, 0 + .dw 0xe140, 0xc89c, 0xe17f, 0xc89c, 0x21, 0 + .dw 0xe1c0, 0xc89c, 0xe1ff, 0xc89c, 0x21, 0 + .dw 0xe240, 0xc89c, 0xe27f, 0xc89c, 0x21, 0 + .dw 0xe2c0, 0xc89c, 0xe2ff, 0xc89c, 0x21, 0 + .dw 0xe340, 0xc89c, 0xe37f, 0xc89c, 0x21, 0 + .dw 0xe3c0, 0xc89c, 0xe3ff, 0xc89c, 0x21, 0 + .dw 0xe440, 0xc89c, 0xe47f, 0xc89c, 0x21, 0 + .dw 0xe4c0, 0xc89c, 0xe4ff, 0xc89c, 0x21, 0 + .dw 0xe540, 0xc89c, 0xe57f, 0xc89c, 0x21, 0 + .dw 0xe5c0, 0xc89c, 0xe5ff, 0xc89c, 0x21, 0 + .dw 0xe640, 0xc89c, 0xe67f, 0xc89c, 0x21, 0 + .dw 0xe6c0, 0xc89c, 0xe6ff, 0xc89c, 0x21, 0 + .dw 0xe740, 0xc89c, 0xe77f, 0xc89c, 0x21, 0 + .dw 0xe7c0, 0xc89c, 0xe7ff, 0xc89c, 0x21, 0 + .dw 0xe840, 0xc89c, 0xe87f, 0xc89c, 0x21, 0 + .dw 0xe8c0, 0xc89c, 0xe8ff, 0xc89c, 0x21, 0 + .dw 0xe940, 0xc89c, 0xe97f, 0xc89c, 0x21, 0 + .dw 0xe9c0, 0xc89c, 0xe9ff, 0xc89c, 0x21, 0 + .dw 0xea40, 0xc89c, 0xea7f, 0xc89c, 0x21, 0 + .dw 0xeac0, 0xc89c, 0xeaff, 0xc89c, 0x21, 0 + .dw 0xeb40, 0xc89c, 0xeb7f, 0xc89c, 0x21, 0 + .dw 0xebc0, 0xc89c, 0xebff, 0xc89c, 0x21, 0 + .dw 0xec40, 0xc89c, 0xec7f, 0xc89c, 0x21, 0 + .dw 0xecc0, 0xc89c, 0xecff, 0xc89c, 0x21, 0 + .dw 0xed40, 0xc89c, 0xed7f, 0xc89c, 0x21, 0 + .dw 0xedc0, 0xc89c, 0xedff, 0xc89c, 0x21, 0 + .dw 0xee40, 0xc89c, 0xee7f, 0xc89c, 0x21, 0 + .dw 0xeec0, 0xc89c, 0xeeff, 0xc89c, 0x21, 0 + .dw 0xef40, 0xc89c, 0xef7f, 0xc89c, 0x21, 0 + .dw 0xefc0, 0xc89c, 0xefff, 0xc89c, 0x21, 0 + .dw 0xf040, 0xc89c, 0xf07f, 0xc89c, 0x21, 0 + .dw 0xf0c0, 0xc89c, 0xf0ff, 0xc89c, 0x21, 0 + .dw 0xf140, 0xc89c, 0xf17f, 0xc89c, 0x21, 0 + .dw 0xf1c0, 0xc89c, 0xf1ff, 0xc89c, 0x21, 0 + .dw 0xf240, 0xc89c, 0xf27f, 0xc89c, 0x21, 0 + .dw 0xf2c0, 0xc89c, 0xf2ff, 0xc89c, 0x21, 0 + .dw 0xf340, 0xc89c, 0xf37f, 0xc89c, 0x21, 0 + .dw 0xf3c0, 0xc89c, 0xf3ff, 0xc89c, 0x21, 0 + .dw 0xf440, 0xc89c, 0xf47f, 0xc89c, 0x21, 0 + .dw 0xf4c0, 0xc89c, 0xf4ff, 0xc89c, 0x21, 0 + .dw 0xf540, 0xc89c, 0xf57f, 0xc89c, 0x21, 0 + .dw 0xf5c0, 0xc89c, 0xf5ff, 0xc89c, 0x21, 0 + .dw 0xf640, 0xc89c, 0xf67f, 0xc89c, 0x21, 0 + .dw 0xf6c0, 0xc89c, 0xf6ff, 0xc89c, 0x21, 0 + .dw 0xf740, 0xc89c, 0xf77f, 0xc89c, 0x21, 0 + .dw 0xf7c0, 0xc89c, 0xf7ff, 0xc89c, 0x21, 0 + .dw 0xf840, 0xc89c, 0xf87f, 0xc89c, 0x21, 0 + .dw 0xf8c0, 0xc89c, 0xf8ff, 0xc89c, 0x21, 0 + .dw 0xf940, 0xc89c, 0xf97f, 0xc89c, 0x21, 0 + .dw 0xf9c0, 0xc89c, 0xffff, 0xc89c, 0x21, 0 + .dw 0x0040, 0xc89d, 0x007f, 0xc89d, 0x21, 0 + .dw 0x00c0, 0xc89d, 0x00ff, 0xc89d, 0x21, 0 + .dw 0x0140, 0xc89d, 0x017f, 0xc89d, 0x21, 0 + .dw 0x01c0, 0xc89d, 0x01ff, 0xc89d, 0x21, 0 + .dw 0x0240, 0xc89d, 0x027f, 0xc89d, 0x21, 0 + .dw 0x02c0, 0xc89d, 0x02ff, 0xc89d, 0x21, 0 + .dw 0x0340, 0xc89d, 0x037f, 0xc89d, 0x21, 0 + .dw 0x03c0, 0xc89d, 0x03ff, 0xc89d, 0x21, 0 + .dw 0x0440, 0xc89d, 0x047f, 0xc89d, 0x21, 0 + .dw 0x04c0, 0xc89d, 0x04ff, 0xc89d, 0x21, 0 + .dw 0x0540, 0xc89d, 0x057f, 0xc89d, 0x21, 0 + .dw 0x05c0, 0xc89d, 0x05ff, 0xc89d, 0x21, 0 + .dw 0x0640, 0xc89d, 0x067f, 0xc89d, 0x21, 0 + .dw 0x06c0, 0xc89d, 0x06ff, 0xc89d, 0x21, 0 + .dw 0x0740, 0xc89d, 0x077f, 0xc89d, 0x21, 0 + .dw 0x07c0, 0xc89d, 0x07ff, 0xc89d, 0x21, 0 + .dw 0x0840, 0xc89d, 0x087f, 0xc89d, 0x21, 0 + .dw 0x08c0, 0xc89d, 0x08ff, 0xc89d, 0x21, 0 + .dw 0x0940, 0xc89d, 0x097f, 0xc89d, 0x21, 0 + .dw 0x09c0, 0xc89d, 0x09ff, 0xc89d, 0x21, 0 + .dw 0x0a40, 0xc89d, 0x0a7f, 0xc89d, 0x21, 0 + .dw 0x0ac0, 0xc89d, 0x0aff, 0xc89d, 0x21, 0 + .dw 0x0b40, 0xc89d, 0x0b7f, 0xc89d, 0x21, 0 + .dw 0x0bc0, 0xc89d, 0x0bff, 0xc89d, 0x21, 0 + .dw 0x0c40, 0xc89d, 0x0c7f, 0xc89d, 0x21, 0 + .dw 0x0cc0, 0xc89d, 0x0cff, 0xc89d, 0x21, 0 + .dw 0x0d40, 0xc89d, 0x0d7f, 0xc89d, 0x21, 0 + .dw 0x0dc0, 0xc89d, 0x0dff, 0xc89d, 0x21, 0 + .dw 0x0e40, 0xc89d, 0x0e7f, 0xc89d, 0x21, 0 + .dw 0x0ec0, 0xc89d, 0x0eff, 0xc89d, 0x21, 0 + .dw 0x0f40, 0xc89d, 0x0f7f, 0xc89d, 0x21, 0 + .dw 0x0fc0, 0xc89d, 0x0fff, 0xc89d, 0x21, 0 + .dw 0x1040, 0xc89d, 0x107f, 0xc89d, 0x21, 0 + .dw 0x10c0, 0xc89d, 0x10ff, 0xc89d, 0x21, 0 + .dw 0x1140, 0xc89d, 0x117f, 0xc89d, 0x21, 0 + .dw 0x11c0, 0xc89d, 0x11ff, 0xc89d, 0x21, 0 + .dw 0x1240, 0xc89d, 0x127f, 0xc89d, 0x21, 0 + .dw 0x12c0, 0xc89d, 0x12ff, 0xc89d, 0x21, 0 + .dw 0x1340, 0xc89d, 0x137f, 0xc89d, 0x21, 0 + .dw 0x13c0, 0xc89d, 0x13ff, 0xc89d, 0x21, 0 + .dw 0x1440, 0xc89d, 0x147f, 0xc89d, 0x21, 0 + .dw 0x14c0, 0xc89d, 0x14ff, 0xc89d, 0x21, 0 + .dw 0x1540, 0xc89d, 0x157f, 0xc89d, 0x21, 0 + .dw 0x15c0, 0xc89d, 0x15ff, 0xc89d, 0x21, 0 + .dw 0x1640, 0xc89d, 0x167f, 0xc89d, 0x21, 0 + .dw 0x16c0, 0xc89d, 0x16ff, 0xc89d, 0x21, 0 + .dw 0x1740, 0xc89d, 0x177f, 0xc89d, 0x21, 0 + .dw 0x17c0, 0xc89d, 0x17ff, 0xc89d, 0x21, 0 + .dw 0x1840, 0xc89d, 0x187f, 0xc89d, 0x21, 0 + .dw 0x18c0, 0xc89d, 0x18ff, 0xc89d, 0x21, 0 + .dw 0x1940, 0xc89d, 0x197f, 0xc89d, 0x21, 0 + .dw 0x19c0, 0xc89d, 0x1fff, 0xc89d, 0x21, 0 + .dw 0x2040, 0xc89d, 0x207f, 0xc89d, 0x21, 0 + .dw 0x20c0, 0xc89d, 0x20ff, 0xc89d, 0x21, 0 + .dw 0x2140, 0xc89d, 0x217f, 0xc89d, 0x21, 0 + .dw 0x21c0, 0xc89d, 0x21ff, 0xc89d, 0x21, 0 + .dw 0x2240, 0xc89d, 0x227f, 0xc89d, 0x21, 0 + .dw 0x22c0, 0xc89d, 0x22ff, 0xc89d, 0x21, 0 + .dw 0x2340, 0xc89d, 0x237f, 0xc89d, 0x21, 0 + .dw 0x23c0, 0xc89d, 0x23ff, 0xc89d, 0x21, 0 + .dw 0x2440, 0xc89d, 0x247f, 0xc89d, 0x21, 0 + .dw 0x24c0, 0xc89d, 0x24ff, 0xc89d, 0x21, 0 + .dw 0x2540, 0xc89d, 0x257f, 0xc89d, 0x21, 0 + .dw 0x25c0, 0xc89d, 0x25ff, 0xc89d, 0x21, 0 + .dw 0x2640, 0xc89d, 0x267f, 0xc89d, 0x21, 0 + .dw 0x26c0, 0xc89d, 0x26ff, 0xc89d, 0x21, 0 + .dw 0x2740, 0xc89d, 0x277f, 0xc89d, 0x21, 0 + .dw 0x27c0, 0xc89d, 0x27ff, 0xc89d, 0x21, 0 + .dw 0x2840, 0xc89d, 0x287f, 0xc89d, 0x21, 0 + .dw 0x28c0, 0xc89d, 0x28ff, 0xc89d, 0x21, 0 + .dw 0x2940, 0xc89d, 0x297f, 0xc89d, 0x21, 0 + .dw 0x29c0, 0xc89d, 0x29ff, 0xc89d, 0x21, 0 + .dw 0x2a40, 0xc89d, 0x2a7f, 0xc89d, 0x21, 0 + .dw 0x2ac0, 0xc89d, 0x2aff, 0xc89d, 0x21, 0 + .dw 0x2b40, 0xc89d, 0x2b7f, 0xc89d, 0x21, 0 + .dw 0x2bc0, 0xc89d, 0x2bff, 0xc89d, 0x21, 0 + .dw 0x2c40, 0xc89d, 0x2c7f, 0xc89d, 0x21, 0 + .dw 0x2cc0, 0xc89d, 0x2cff, 0xc89d, 0x21, 0 + .dw 0x2d40, 0xc89d, 0x2d7f, 0xc89d, 0x21, 0 + .dw 0x2dc0, 0xc89d, 0x2dff, 0xc89d, 0x21, 0 + .dw 0x2e40, 0xc89d, 0x2e7f, 0xc89d, 0x21, 0 + .dw 0x2ec0, 0xc89d, 0x2eff, 0xc89d, 0x21, 0 + .dw 0x2f40, 0xc89d, 0x2f7f, 0xc89d, 0x21, 0 + .dw 0x2fc0, 0xc89d, 0x2fff, 0xc89d, 0x21, 0 + .dw 0x3040, 0xc89d, 0x307f, 0xc89d, 0x21, 0 + .dw 0x30c0, 0xc89d, 0x30ff, 0xc89d, 0x21, 0 + .dw 0x3140, 0xc89d, 0x317f, 0xc89d, 0x21, 0 + .dw 0x31c0, 0xc89d, 0x31ff, 0xc89d, 0x21, 0 + .dw 0x3240, 0xc89d, 0x327f, 0xc89d, 0x21, 0 + .dw 0x32c0, 0xc89d, 0x32ff, 0xc89d, 0x21, 0 + .dw 0x3340, 0xc89d, 0x337f, 0xc89d, 0x21, 0 + .dw 0x33c0, 0xc89d, 0x33ff, 0xc89d, 0x21, 0 + .dw 0x3440, 0xc89d, 0x347f, 0xc89d, 0x21, 0 + .dw 0x34c0, 0xc89d, 0x34ff, 0xc89d, 0x21, 0 + .dw 0x3540, 0xc89d, 0x357f, 0xc89d, 0x21, 0 + .dw 0x35c0, 0xc89d, 0x35ff, 0xc89d, 0x21, 0 + .dw 0x3640, 0xc89d, 0x367f, 0xc89d, 0x21, 0 + .dw 0x36c0, 0xc89d, 0x36ff, 0xc89d, 0x21, 0 + .dw 0x3740, 0xc89d, 0x377f, 0xc89d, 0x21, 0 + .dw 0x37c0, 0xc89d, 0x37ff, 0xc89d, 0x21, 0 + .dw 0x3840, 0xc89d, 0x387f, 0xc89d, 0x21, 0 + .dw 0x38c0, 0xc89d, 0x38ff, 0xc89d, 0x21, 0 + .dw 0x3940, 0xc89d, 0x397f, 0xc89d, 0x21, 0 + .dw 0x39c0, 0xc89d, 0x3fff, 0xc89d, 0x21, 0 + .dw 0x4040, 0xc89d, 0x407f, 0xc89d, 0x21, 0 + .dw 0x40c0, 0xc89d, 0x40ff, 0xc89d, 0x21, 0 + .dw 0x4140, 0xc89d, 0x417f, 0xc89d, 0x21, 0 + .dw 0x41c0, 0xc89d, 0x41ff, 0xc89d, 0x21, 0 + .dw 0x4240, 0xc89d, 0x427f, 0xc89d, 0x21, 0 + .dw 0x42c0, 0xc89d, 0x42ff, 0xc89d, 0x21, 0 + .dw 0x4340, 0xc89d, 0x437f, 0xc89d, 0x21, 0 + .dw 0x43c0, 0xc89d, 0x43ff, 0xc89d, 0x21, 0 + .dw 0x4440, 0xc89d, 0x447f, 0xc89d, 0x21, 0 + .dw 0x44c0, 0xc89d, 0x44ff, 0xc89d, 0x21, 0 + .dw 0x4540, 0xc89d, 0x457f, 0xc89d, 0x21, 0 + .dw 0x45c0, 0xc89d, 0x45ff, 0xc89d, 0x21, 0 + .dw 0x4640, 0xc89d, 0x467f, 0xc89d, 0x21, 0 + .dw 0x46c0, 0xc89d, 0x46ff, 0xc89d, 0x21, 0 + .dw 0x4740, 0xc89d, 0x477f, 0xc89d, 0x21, 0 + .dw 0x47c0, 0xc89d, 0x47ff, 0xc89d, 0x21, 0 + .dw 0x4840, 0xc89d, 0x487f, 0xc89d, 0x21, 0 + .dw 0x48c0, 0xc89d, 0x48ff, 0xc89d, 0x21, 0 + .dw 0x4940, 0xc89d, 0x497f, 0xc89d, 0x21, 0 + .dw 0x49c0, 0xc89d, 0x49ff, 0xc89d, 0x21, 0 + .dw 0x4a40, 0xc89d, 0x4a7f, 0xc89d, 0x21, 0 + .dw 0x4ac0, 0xc89d, 0x4aff, 0xc89d, 0x21, 0 + .dw 0x4b40, 0xc89d, 0x4b7f, 0xc89d, 0x21, 0 + .dw 0x4bc0, 0xc89d, 0x4bff, 0xc89d, 0x21, 0 + .dw 0x4c40, 0xc89d, 0x4c7f, 0xc89d, 0x21, 0 + .dw 0x4cc0, 0xc89d, 0x4cff, 0xc89d, 0x21, 0 + .dw 0x4d40, 0xc89d, 0x4d7f, 0xc89d, 0x21, 0 + .dw 0x4dc0, 0xc89d, 0x4dff, 0xc89d, 0x21, 0 + .dw 0x4e40, 0xc89d, 0x4e7f, 0xc89d, 0x21, 0 + .dw 0x4ec0, 0xc89d, 0x4eff, 0xc89d, 0x21, 0 + .dw 0x4f40, 0xc89d, 0x4f7f, 0xc89d, 0x21, 0 + .dw 0x4fc0, 0xc89d, 0x4fff, 0xc89d, 0x21, 0 + .dw 0x5040, 0xc89d, 0x507f, 0xc89d, 0x21, 0 + .dw 0x50c0, 0xc89d, 0x50ff, 0xc89d, 0x21, 0 + .dw 0x5140, 0xc89d, 0x517f, 0xc89d, 0x21, 0 + .dw 0x51c0, 0xc89d, 0x51ff, 0xc89d, 0x21, 0 + .dw 0x5240, 0xc89d, 0x527f, 0xc89d, 0x21, 0 + .dw 0x52c0, 0xc89d, 0x52ff, 0xc89d, 0x21, 0 + .dw 0x5340, 0xc89d, 0x537f, 0xc89d, 0x21, 0 + .dw 0x53c0, 0xc89d, 0x53ff, 0xc89d, 0x21, 0 + .dw 0x5440, 0xc89d, 0x547f, 0xc89d, 0x21, 0 + .dw 0x54c0, 0xc89d, 0x54ff, 0xc89d, 0x21, 0 + .dw 0x5540, 0xc89d, 0x557f, 0xc89d, 0x21, 0 + .dw 0x55c0, 0xc89d, 0x55ff, 0xc89d, 0x21, 0 + .dw 0x5640, 0xc89d, 0x567f, 0xc89d, 0x21, 0 + .dw 0x56c0, 0xc89d, 0x56ff, 0xc89d, 0x21, 0 + .dw 0x5740, 0xc89d, 0x577f, 0xc89d, 0x21, 0 + .dw 0x57c0, 0xc89d, 0x57ff, 0xc89d, 0x21, 0 + .dw 0x5840, 0xc89d, 0x587f, 0xc89d, 0x21, 0 + .dw 0x58c0, 0xc89d, 0x58ff, 0xc89d, 0x21, 0 + .dw 0x5940, 0xc89d, 0x597f, 0xc89d, 0x21, 0 + .dw 0x59c0, 0xc89d, 0x5fff, 0xc89d, 0x21, 0 + .dw 0x6040, 0xc89d, 0x607f, 0xc89d, 0x21, 0 + .dw 0x60c0, 0xc89d, 0x60ff, 0xc89d, 0x21, 0 + .dw 0x6140, 0xc89d, 0x617f, 0xc89d, 0x21, 0 + .dw 0x61c0, 0xc89d, 0x61ff, 0xc89d, 0x21, 0 + .dw 0x6240, 0xc89d, 0x627f, 0xc89d, 0x21, 0 + .dw 0x62c0, 0xc89d, 0x62ff, 0xc89d, 0x21, 0 + .dw 0x6340, 0xc89d, 0x637f, 0xc89d, 0x21, 0 + .dw 0x63c0, 0xc89d, 0x63ff, 0xc89d, 0x21, 0 + .dw 0x6440, 0xc89d, 0x647f, 0xc89d, 0x21, 0 + .dw 0x64c0, 0xc89d, 0x64ff, 0xc89d, 0x21, 0 + .dw 0x6540, 0xc89d, 0x657f, 0xc89d, 0x21, 0 + .dw 0x65c0, 0xc89d, 0x65ff, 0xc89d, 0x21, 0 + .dw 0x6640, 0xc89d, 0x667f, 0xc89d, 0x21, 0 + .dw 0x66c0, 0xc89d, 0x66ff, 0xc89d, 0x21, 0 + .dw 0x6740, 0xc89d, 0x677f, 0xc89d, 0x21, 0 + .dw 0x67c0, 0xc89d, 0x67ff, 0xc89d, 0x21, 0 + .dw 0x6840, 0xc89d, 0x687f, 0xc89d, 0x21, 0 + .dw 0x68c0, 0xc89d, 0x68ff, 0xc89d, 0x21, 0 + .dw 0x6940, 0xc89d, 0x697f, 0xc89d, 0x21, 0 + .dw 0x69c0, 0xc89d, 0x69ff, 0xc89d, 0x21, 0 + .dw 0x6a40, 0xc89d, 0x6a7f, 0xc89d, 0x21, 0 + .dw 0x6ac0, 0xc89d, 0x6aff, 0xc89d, 0x21, 0 + .dw 0x6b40, 0xc89d, 0x6b7f, 0xc89d, 0x21, 0 + .dw 0x6bc0, 0xc89d, 0x6bff, 0xc89d, 0x21, 0 + .dw 0x6c40, 0xc89d, 0x6c7f, 0xc89d, 0x21, 0 + .dw 0x6cc0, 0xc89d, 0x6cff, 0xc89d, 0x21, 0 + .dw 0x6d40, 0xc89d, 0x6d7f, 0xc89d, 0x21, 0 + .dw 0x6dc0, 0xc89d, 0x6dff, 0xc89d, 0x21, 0 + .dw 0x6e40, 0xc89d, 0x6e7f, 0xc89d, 0x21, 0 + .dw 0x6ec0, 0xc89d, 0x6eff, 0xc89d, 0x21, 0 + .dw 0x6f40, 0xc89d, 0x6f7f, 0xc89d, 0x21, 0 + .dw 0x6fc0, 0xc89d, 0x6fff, 0xc89d, 0x21, 0 + .dw 0x7040, 0xc89d, 0x707f, 0xc89d, 0x21, 0 + .dw 0x70c0, 0xc89d, 0x70ff, 0xc89d, 0x21, 0 + .dw 0x7140, 0xc89d, 0x717f, 0xc89d, 0x21, 0 + .dw 0x71c0, 0xc89d, 0x71ff, 0xc89d, 0x21, 0 + .dw 0x7240, 0xc89d, 0x727f, 0xc89d, 0x21, 0 + .dw 0x72c0, 0xc89d, 0x72ff, 0xc89d, 0x21, 0 + .dw 0x7340, 0xc89d, 0x737f, 0xc89d, 0x21, 0 + .dw 0x73c0, 0xc89d, 0x73ff, 0xc89d, 0x21, 0 + .dw 0x7440, 0xc89d, 0x747f, 0xc89d, 0x21, 0 + .dw 0x74c0, 0xc89d, 0x74ff, 0xc89d, 0x21, 0 + .dw 0x7540, 0xc89d, 0x757f, 0xc89d, 0x21, 0 + .dw 0x75c0, 0xc89d, 0x75ff, 0xc89d, 0x21, 0 + .dw 0x7640, 0xc89d, 0x767f, 0xc89d, 0x21, 0 + .dw 0x76c0, 0xc89d, 0x76ff, 0xc89d, 0x21, 0 + .dw 0x7740, 0xc89d, 0x777f, 0xc89d, 0x21, 0 + .dw 0x77c0, 0xc89d, 0x77ff, 0xc89d, 0x21, 0 + .dw 0x7840, 0xc89d, 0x787f, 0xc89d, 0x21, 0 + .dw 0x78c0, 0xc89d, 0x78ff, 0xc89d, 0x21, 0 + .dw 0x7940, 0xc89d, 0x797f, 0xc89d, 0x21, 0 + .dw 0x79c0, 0xc89d, 0x7fff, 0xc89d, 0x21, 0 + .dw 0x8040, 0xc89d, 0x807f, 0xc89d, 0x21, 0 + .dw 0x80c0, 0xc89d, 0x80ff, 0xc89d, 0x21, 0 + .dw 0x8140, 0xc89d, 0x817f, 0xc89d, 0x21, 0 + .dw 0x81c0, 0xc89d, 0x81ff, 0xc89d, 0x21, 0 + .dw 0x8240, 0xc89d, 0x827f, 0xc89d, 0x21, 0 + .dw 0x82c0, 0xc89d, 0x82ff, 0xc89d, 0x21, 0 + .dw 0x8340, 0xc89d, 0x837f, 0xc89d, 0x21, 0 + .dw 0x83c0, 0xc89d, 0x83ff, 0xc89d, 0x21, 0 + .dw 0x8440, 0xc89d, 0x847f, 0xc89d, 0x21, 0 + .dw 0x84c0, 0xc89d, 0x84ff, 0xc89d, 0x21, 0 + .dw 0x8540, 0xc89d, 0x857f, 0xc89d, 0x21, 0 + .dw 0x85c0, 0xc89d, 0x85ff, 0xc89d, 0x21, 0 + .dw 0x8640, 0xc89d, 0x867f, 0xc89d, 0x21, 0 + .dw 0x86c0, 0xc89d, 0x86ff, 0xc89d, 0x21, 0 + .dw 0x8740, 0xc89d, 0x877f, 0xc89d, 0x21, 0 + .dw 0x87c0, 0xc89d, 0x87ff, 0xc89d, 0x21, 0 + .dw 0x8840, 0xc89d, 0x887f, 0xc89d, 0x21, 0 + .dw 0x88c0, 0xc89d, 0x88ff, 0xc89d, 0x21, 0 + .dw 0x8940, 0xc89d, 0x897f, 0xc89d, 0x21, 0 + .dw 0x89c0, 0xc89d, 0x89ff, 0xc89d, 0x21, 0 + .dw 0x8a40, 0xc89d, 0x8a7f, 0xc89d, 0x21, 0 + .dw 0x8ac0, 0xc89d, 0x8aff, 0xc89d, 0x21, 0 + .dw 0x8b40, 0xc89d, 0x8b7f, 0xc89d, 0x21, 0 + .dw 0x8bc0, 0xc89d, 0x8bff, 0xc89d, 0x21, 0 + .dw 0x8c40, 0xc89d, 0x8c7f, 0xc89d, 0x21, 0 + .dw 0x8cc0, 0xc89d, 0x8cff, 0xc89d, 0x21, 0 + .dw 0x8d40, 0xc89d, 0x8d7f, 0xc89d, 0x21, 0 + .dw 0x8dc0, 0xc89d, 0x8dff, 0xc89d, 0x21, 0 + .dw 0x8e40, 0xc89d, 0x8e7f, 0xc89d, 0x21, 0 + .dw 0x8ec0, 0xc89d, 0x8eff, 0xc89d, 0x21, 0 + .dw 0x8f40, 0xc89d, 0x8f7f, 0xc89d, 0x21, 0 + .dw 0x8fc0, 0xc89d, 0x8fff, 0xc89d, 0x21, 0 + .dw 0x9040, 0xc89d, 0x907f, 0xc89d, 0x21, 0 + .dw 0x90c0, 0xc89d, 0x90ff, 0xc89d, 0x21, 0 + .dw 0x9140, 0xc89d, 0x917f, 0xc89d, 0x21, 0 + .dw 0x91c0, 0xc89d, 0x91ff, 0xc89d, 0x21, 0 + .dw 0x9240, 0xc89d, 0x927f, 0xc89d, 0x21, 0 + .dw 0x92c0, 0xc89d, 0x92ff, 0xc89d, 0x21, 0 + .dw 0x9340, 0xc89d, 0x937f, 0xc89d, 0x21, 0 + .dw 0x93c0, 0xc89d, 0x93ff, 0xc89d, 0x21, 0 + .dw 0x9440, 0xc89d, 0x947f, 0xc89d, 0x21, 0 + .dw 0x94c0, 0xc89d, 0x94ff, 0xc89d, 0x21, 0 + .dw 0x9540, 0xc89d, 0x957f, 0xc89d, 0x21, 0 + .dw 0x95c0, 0xc89d, 0x95ff, 0xc89d, 0x21, 0 + .dw 0x9640, 0xc89d, 0x967f, 0xc89d, 0x21, 0 + .dw 0x96c0, 0xc89d, 0x96ff, 0xc89d, 0x21, 0 + .dw 0x9740, 0xc89d, 0x977f, 0xc89d, 0x21, 0 + .dw 0x97c0, 0xc89d, 0x97ff, 0xc89d, 0x21, 0 + .dw 0x9840, 0xc89d, 0x987f, 0xc89d, 0x21, 0 + .dw 0x98c0, 0xc89d, 0x98ff, 0xc89d, 0x21, 0 + .dw 0x9940, 0xc89d, 0x997f, 0xc89d, 0x21, 0 + .dw 0x99c0, 0xc89d, 0x9fff, 0xc89d, 0x21, 0 + .dw 0xa040, 0xc89d, 0xa07f, 0xc89d, 0x21, 0 + .dw 0xa0c0, 0xc89d, 0xa0ff, 0xc89d, 0x21, 0 + .dw 0xa140, 0xc89d, 0xa17f, 0xc89d, 0x21, 0 + .dw 0xa1c0, 0xc89d, 0xa1ff, 0xc89d, 0x21, 0 + .dw 0xa240, 0xc89d, 0xa27f, 0xc89d, 0x21, 0 + .dw 0xa2c0, 0xc89d, 0xa2ff, 0xc89d, 0x21, 0 + .dw 0xa340, 0xc89d, 0xa37f, 0xc89d, 0x21, 0 + .dw 0xa3c0, 0xc89d, 0xa3ff, 0xc89d, 0x21, 0 + .dw 0xa440, 0xc89d, 0xa47f, 0xc89d, 0x21, 0 + .dw 0xa4c0, 0xc89d, 0xa4ff, 0xc89d, 0x21, 0 + .dw 0xa540, 0xc89d, 0xa57f, 0xc89d, 0x21, 0 + .dw 0xa5c0, 0xc89d, 0xa5ff, 0xc89d, 0x21, 0 + .dw 0xa640, 0xc89d, 0xa67f, 0xc89d, 0x21, 0 + .dw 0xa6c0, 0xc89d, 0xa6ff, 0xc89d, 0x21, 0 + .dw 0xa740, 0xc89d, 0xa77f, 0xc89d, 0x21, 0 + .dw 0xa7c0, 0xc89d, 0xa7ff, 0xc89d, 0x21, 0 + .dw 0xa840, 0xc89d, 0xa87f, 0xc89d, 0x21, 0 + .dw 0xa8c0, 0xc89d, 0xa8ff, 0xc89d, 0x21, 0 + .dw 0xa940, 0xc89d, 0xa97f, 0xc89d, 0x21, 0 + .dw 0xa9c0, 0xc89d, 0xa9ff, 0xc89d, 0x21, 0 + .dw 0xaa40, 0xc89d, 0xaa7f, 0xc89d, 0x21, 0 + .dw 0xaac0, 0xc89d, 0xaaff, 0xc89d, 0x21, 0 + .dw 0xab40, 0xc89d, 0xab7f, 0xc89d, 0x21, 0 + .dw 0xabc0, 0xc89d, 0xabff, 0xc89d, 0x21, 0 + .dw 0xac40, 0xc89d, 0xac7f, 0xc89d, 0x21, 0 + .dw 0xacc0, 0xc89d, 0xacff, 0xc89d, 0x21, 0 + .dw 0xad40, 0xc89d, 0xad7f, 0xc89d, 0x21, 0 + .dw 0xadc0, 0xc89d, 0xadff, 0xc89d, 0x21, 0 + .dw 0xae40, 0xc89d, 0xae7f, 0xc89d, 0x21, 0 + .dw 0xaec0, 0xc89d, 0xaeff, 0xc89d, 0x21, 0 + .dw 0xaf40, 0xc89d, 0xaf7f, 0xc89d, 0x21, 0 + .dw 0xafc0, 0xc89d, 0xafff, 0xc89d, 0x21, 0 + .dw 0xb040, 0xc89d, 0xb07f, 0xc89d, 0x21, 0 + .dw 0xb0c0, 0xc89d, 0xb0ff, 0xc89d, 0x21, 0 + .dw 0xb140, 0xc89d, 0xb17f, 0xc89d, 0x21, 0 + .dw 0xb1c0, 0xc89d, 0xb1ff, 0xc89d, 0x21, 0 + .dw 0xb240, 0xc89d, 0xb27f, 0xc89d, 0x21, 0 + .dw 0xb2c0, 0xc89d, 0xb2ff, 0xc89d, 0x21, 0 + .dw 0xb340, 0xc89d, 0xb37f, 0xc89d, 0x21, 0 + .dw 0xb3c0, 0xc89d, 0xb3ff, 0xc89d, 0x21, 0 + .dw 0xb440, 0xc89d, 0xb47f, 0xc89d, 0x21, 0 + .dw 0xb4c0, 0xc89d, 0xb4ff, 0xc89d, 0x21, 0 + .dw 0xb540, 0xc89d, 0xb57f, 0xc89d, 0x21, 0 + .dw 0xb5c0, 0xc89d, 0xb5ff, 0xc89d, 0x21, 0 + .dw 0xb640, 0xc89d, 0xb67f, 0xc89d, 0x21, 0 + .dw 0xb6c0, 0xc89d, 0xb6ff, 0xc89d, 0x21, 0 + .dw 0xb740, 0xc89d, 0xb77f, 0xc89d, 0x21, 0 + .dw 0xb7c0, 0xc89d, 0xb7ff, 0xc89d, 0x21, 0 + .dw 0xb840, 0xc89d, 0xb87f, 0xc89d, 0x21, 0 + .dw 0xb8c0, 0xc89d, 0xb8ff, 0xc89d, 0x21, 0 + .dw 0xb940, 0xc89d, 0xb97f, 0xc89d, 0x21, 0 + .dw 0xb9c0, 0xc89d, 0xbfff, 0xc89d, 0x21, 0 + .dw 0xc040, 0xc89d, 0xc07f, 0xc89d, 0x21, 0 + .dw 0xc0c0, 0xc89d, 0xc0ff, 0xc89d, 0x21, 0 + .dw 0xc140, 0xc89d, 0xc17f, 0xc89d, 0x21, 0 + .dw 0xc1c0, 0xc89d, 0xc1ff, 0xc89d, 0x21, 0 + .dw 0xc240, 0xc89d, 0xc27f, 0xc89d, 0x21, 0 + .dw 0xc2c0, 0xc89d, 0xc2ff, 0xc89d, 0x21, 0 + .dw 0xc340, 0xc89d, 0xc37f, 0xc89d, 0x21, 0 + .dw 0xc3c0, 0xc89d, 0xc3ff, 0xc89d, 0x21, 0 + .dw 0xc440, 0xc89d, 0xc47f, 0xc89d, 0x21, 0 + .dw 0xc4c0, 0xc89d, 0xc4ff, 0xc89d, 0x21, 0 + .dw 0xc540, 0xc89d, 0xc57f, 0xc89d, 0x21, 0 + .dw 0xc5c0, 0xc89d, 0xc5ff, 0xc89d, 0x21, 0 + .dw 0xc640, 0xc89d, 0xc67f, 0xc89d, 0x21, 0 + .dw 0xc6c0, 0xc89d, 0xc6ff, 0xc89d, 0x21, 0 + .dw 0xc740, 0xc89d, 0xc77f, 0xc89d, 0x21, 0 + .dw 0xc7c0, 0xc89d, 0xc7ff, 0xc89d, 0x21, 0 + .dw 0xc840, 0xc89d, 0xc87f, 0xc89d, 0x21, 0 + .dw 0xc8c0, 0xc89d, 0xc8ff, 0xc89d, 0x21, 0 + .dw 0xc940, 0xc89d, 0xc97f, 0xc89d, 0x21, 0 + .dw 0xc9c0, 0xc89d, 0xc9ff, 0xc89d, 0x21, 0 + .dw 0xca40, 0xc89d, 0xca7f, 0xc89d, 0x21, 0 + .dw 0xcac0, 0xc89d, 0xcaff, 0xc89d, 0x21, 0 + .dw 0xcb40, 0xc89d, 0xcb7f, 0xc89d, 0x21, 0 + .dw 0xcbc0, 0xc89d, 0xcbff, 0xc89d, 0x21, 0 + .dw 0xcc40, 0xc89d, 0xcc7f, 0xc89d, 0x21, 0 + .dw 0xccc0, 0xc89d, 0xccff, 0xc89d, 0x21, 0 + .dw 0xcd40, 0xc89d, 0xcd7f, 0xc89d, 0x21, 0 + .dw 0xcdc0, 0xc89d, 0xcdff, 0xc89d, 0x21, 0 + .dw 0xce40, 0xc89d, 0xce7f, 0xc89d, 0x21, 0 + .dw 0xcec0, 0xc89d, 0xceff, 0xc89d, 0x21, 0 + .dw 0xcf40, 0xc89d, 0xcf7f, 0xc89d, 0x21, 0 + .dw 0xcfc0, 0xc89d, 0xcfff, 0xc89d, 0x21, 0 + .dw 0xd040, 0xc89d, 0xd07f, 0xc89d, 0x21, 0 + .dw 0xd0c0, 0xc89d, 0xd0ff, 0xc89d, 0x21, 0 + .dw 0xd140, 0xc89d, 0xd17f, 0xc89d, 0x21, 0 + .dw 0xd1c0, 0xc89d, 0xd1ff, 0xc89d, 0x21, 0 + .dw 0xd240, 0xc89d, 0xd27f, 0xc89d, 0x21, 0 + .dw 0xd2c0, 0xc89d, 0xd2ff, 0xc89d, 0x21, 0 + .dw 0xd340, 0xc89d, 0xd37f, 0xc89d, 0x21, 0 + .dw 0xd3c0, 0xc89d, 0xd3ff, 0xc89d, 0x21, 0 + .dw 0xd440, 0xc89d, 0xd47f, 0xc89d, 0x21, 0 + .dw 0xd4c0, 0xc89d, 0xd4ff, 0xc89d, 0x21, 0 + .dw 0xd540, 0xc89d, 0xd57f, 0xc89d, 0x21, 0 + .dw 0xd5c0, 0xc89d, 0xd5ff, 0xc89d, 0x21, 0 + .dw 0xd640, 0xc89d, 0xd67f, 0xc89d, 0x21, 0 + .dw 0xd6c0, 0xc89d, 0xd6ff, 0xc89d, 0x21, 0 + .dw 0xd740, 0xc89d, 0xd77f, 0xc89d, 0x21, 0 + .dw 0xd7c0, 0xc89d, 0xd7ff, 0xc89d, 0x21, 0 + .dw 0xd840, 0xc89d, 0xd87f, 0xc89d, 0x21, 0 + .dw 0xd8c0, 0xc89d, 0xd8ff, 0xc89d, 0x21, 0 + .dw 0xd940, 0xc89d, 0xd97f, 0xc89d, 0x21, 0 + .dw 0xd9c0, 0xc89d, 0xdfff, 0xc89d, 0x21, 0 + .dw 0xe040, 0xc89d, 0xe07f, 0xc89d, 0x21, 0 + .dw 0xe0c0, 0xc89d, 0xe0ff, 0xc89d, 0x21, 0 + .dw 0xe140, 0xc89d, 0xe17f, 0xc89d, 0x21, 0 + .dw 0xe1c0, 0xc89d, 0xe1ff, 0xc89d, 0x21, 0 + .dw 0xe240, 0xc89d, 0xe27f, 0xc89d, 0x21, 0 + .dw 0xe2c0, 0xc89d, 0xe2ff, 0xc89d, 0x21, 0 + .dw 0xe340, 0xc89d, 0xe37f, 0xc89d, 0x21, 0 + .dw 0xe3c0, 0xc89d, 0xe3ff, 0xc89d, 0x21, 0 + .dw 0xe440, 0xc89d, 0xe47f, 0xc89d, 0x21, 0 + .dw 0xe4c0, 0xc89d, 0xe4ff, 0xc89d, 0x21, 0 + .dw 0xe540, 0xc89d, 0xe57f, 0xc89d, 0x21, 0 + .dw 0xe5c0, 0xc89d, 0xe5ff, 0xc89d, 0x21, 0 + .dw 0xe640, 0xc89d, 0xe67f, 0xc89d, 0x21, 0 + .dw 0xe6c0, 0xc89d, 0xe6ff, 0xc89d, 0x21, 0 + .dw 0xe740, 0xc89d, 0xe77f, 0xc89d, 0x21, 0 + .dw 0xe7c0, 0xc89d, 0xe7ff, 0xc89d, 0x21, 0 + .dw 0xe840, 0xc89d, 0xe87f, 0xc89d, 0x21, 0 + .dw 0xe8c0, 0xc89d, 0xe8ff, 0xc89d, 0x21, 0 + .dw 0xe940, 0xc89d, 0xe97f, 0xc89d, 0x21, 0 + .dw 0xe9c0, 0xc89d, 0xe9ff, 0xc89d, 0x21, 0 + .dw 0xea40, 0xc89d, 0xea7f, 0xc89d, 0x21, 0 + .dw 0xeac0, 0xc89d, 0xeaff, 0xc89d, 0x21, 0 + .dw 0xeb40, 0xc89d, 0xeb7f, 0xc89d, 0x21, 0 + .dw 0xebc0, 0xc89d, 0xebff, 0xc89d, 0x21, 0 + .dw 0xec40, 0xc89d, 0xec7f, 0xc89d, 0x21, 0 + .dw 0xecc0, 0xc89d, 0xecff, 0xc89d, 0x21, 0 + .dw 0xed40, 0xc89d, 0xed7f, 0xc89d, 0x21, 0 + .dw 0xedc0, 0xc89d, 0xedff, 0xc89d, 0x21, 0 + .dw 0xee40, 0xc89d, 0xee7f, 0xc89d, 0x21, 0 + .dw 0xeec0, 0xc89d, 0xeeff, 0xc89d, 0x21, 0 + .dw 0xef40, 0xc89d, 0xef7f, 0xc89d, 0x21, 0 + .dw 0xefc0, 0xc89d, 0xefff, 0xc89d, 0x21, 0 + .dw 0xf040, 0xc89d, 0xf07f, 0xc89d, 0x21, 0 + .dw 0xf0c0, 0xc89d, 0xf0ff, 0xc89d, 0x21, 0 + .dw 0xf140, 0xc89d, 0xf17f, 0xc89d, 0x21, 0 + .dw 0xf1c0, 0xc89d, 0xf1ff, 0xc89d, 0x21, 0 + .dw 0xf240, 0xc89d, 0xf27f, 0xc89d, 0x21, 0 + .dw 0xf2c0, 0xc89d, 0xf2ff, 0xc89d, 0x21, 0 + .dw 0xf340, 0xc89d, 0xf37f, 0xc89d, 0x21, 0 + .dw 0xf3c0, 0xc89d, 0xf3ff, 0xc89d, 0x21, 0 + .dw 0xf440, 0xc89d, 0xf47f, 0xc89d, 0x21, 0 + .dw 0xf4c0, 0xc89d, 0xf4ff, 0xc89d, 0x21, 0 + .dw 0xf540, 0xc89d, 0xf57f, 0xc89d, 0x21, 0 + .dw 0xf5c0, 0xc89d, 0xf5ff, 0xc89d, 0x21, 0 + .dw 0xf640, 0xc89d, 0xf67f, 0xc89d, 0x21, 0 + .dw 0xf6c0, 0xc89d, 0xf6ff, 0xc89d, 0x21, 0 + .dw 0xf740, 0xc89d, 0xf77f, 0xc89d, 0x21, 0 + .dw 0xf7c0, 0xc89d, 0xf7ff, 0xc89d, 0x21, 0 + .dw 0xf840, 0xc89d, 0xf87f, 0xc89d, 0x21, 0 + .dw 0xf8c0, 0xc89d, 0xf8ff, 0xc89d, 0x21, 0 + .dw 0xf940, 0xc89d, 0xf97f, 0xc89d, 0x21, 0 + .dw 0xf9c0, 0xc89d, 0xffff, 0xc89d, 0x21, 0 + .dw 0x0040, 0xc89e, 0x007f, 0xc89e, 0x21, 0 + .dw 0x00c0, 0xc89e, 0x00ff, 0xc89e, 0x21, 0 + .dw 0x0140, 0xc89e, 0x017f, 0xc89e, 0x21, 0 + .dw 0x01c0, 0xc89e, 0x01ff, 0xc89e, 0x21, 0 + .dw 0x0240, 0xc89e, 0x027f, 0xc89e, 0x21, 0 + .dw 0x02c0, 0xc89e, 0x02ff, 0xc89e, 0x21, 0 + .dw 0x0340, 0xc89e, 0x037f, 0xc89e, 0x21, 0 + .dw 0x03c0, 0xc89e, 0x03ff, 0xc89e, 0x21, 0 + .dw 0x0440, 0xc89e, 0x047f, 0xc89e, 0x21, 0 + .dw 0x04c0, 0xc89e, 0x04ff, 0xc89e, 0x21, 0 + .dw 0x0540, 0xc89e, 0x057f, 0xc89e, 0x21, 0 + .dw 0x05c0, 0xc89e, 0x05ff, 0xc89e, 0x21, 0 + .dw 0x0640, 0xc89e, 0x067f, 0xc89e, 0x21, 0 + .dw 0x06c0, 0xc89e, 0x06ff, 0xc89e, 0x21, 0 + .dw 0x0740, 0xc89e, 0x077f, 0xc89e, 0x21, 0 + .dw 0x07c0, 0xc89e, 0x07ff, 0xc89e, 0x21, 0 + .dw 0x0840, 0xc89e, 0x087f, 0xc89e, 0x21, 0 + .dw 0x08c0, 0xc89e, 0x08ff, 0xc89e, 0x21, 0 + .dw 0x0940, 0xc89e, 0x097f, 0xc89e, 0x21, 0 + .dw 0x09c0, 0xc89e, 0x09ff, 0xc89e, 0x21, 0 + .dw 0x0a40, 0xc89e, 0x0a7f, 0xc89e, 0x21, 0 + .dw 0x0ac0, 0xc89e, 0x0aff, 0xc89e, 0x21, 0 + .dw 0x0b40, 0xc89e, 0x0b7f, 0xc89e, 0x21, 0 + .dw 0x0bc0, 0xc89e, 0x0bff, 0xc89e, 0x21, 0 + .dw 0x0c40, 0xc89e, 0x0c7f, 0xc89e, 0x21, 0 + .dw 0x0cc0, 0xc89e, 0x0cff, 0xc89e, 0x21, 0 + .dw 0x0d40, 0xc89e, 0x0d7f, 0xc89e, 0x21, 0 + .dw 0x0dc0, 0xc89e, 0x0dff, 0xc89e, 0x21, 0 + .dw 0x0e40, 0xc89e, 0x0e7f, 0xc89e, 0x21, 0 + .dw 0x0ec0, 0xc89e, 0x0eff, 0xc89e, 0x21, 0 + .dw 0x0f40, 0xc89e, 0x0f7f, 0xc89e, 0x21, 0 + .dw 0x0fc0, 0xc89e, 0x0fff, 0xc89e, 0x21, 0 + .dw 0x1040, 0xc89e, 0x107f, 0xc89e, 0x21, 0 + .dw 0x10c0, 0xc89e, 0x10ff, 0xc89e, 0x21, 0 + .dw 0x1140, 0xc89e, 0x117f, 0xc89e, 0x21, 0 + .dw 0x11c0, 0xc89e, 0x11ff, 0xc89e, 0x21, 0 + .dw 0x1240, 0xc89e, 0x127f, 0xc89e, 0x21, 0 + .dw 0x12c0, 0xc89e, 0x12ff, 0xc89e, 0x21, 0 + .dw 0x1340, 0xc89e, 0x137f, 0xc89e, 0x21, 0 + .dw 0x13c0, 0xc89e, 0x13ff, 0xc89e, 0x21, 0 + .dw 0x1440, 0xc89e, 0x147f, 0xc89e, 0x21, 0 + .dw 0x14c0, 0xc89e, 0x14ff, 0xc89e, 0x21, 0 + .dw 0x1540, 0xc89e, 0x157f, 0xc89e, 0x21, 0 + .dw 0x15c0, 0xc89e, 0x15ff, 0xc89e, 0x21, 0 + .dw 0x1640, 0xc89e, 0x167f, 0xc89e, 0x21, 0 + .dw 0x16c0, 0xc89e, 0x16ff, 0xc89e, 0x21, 0 + .dw 0x1740, 0xc89e, 0x177f, 0xc89e, 0x21, 0 + .dw 0x17c0, 0xc89e, 0x17ff, 0xc89e, 0x21, 0 + .dw 0x1840, 0xc89e, 0x187f, 0xc89e, 0x21, 0 + .dw 0x18c0, 0xc89e, 0x18ff, 0xc89e, 0x21, 0 + .dw 0x1940, 0xc89e, 0x197f, 0xc89e, 0x21, 0 + .dw 0x19c0, 0xc89e, 0x1fff, 0xc89e, 0x21, 0 + .dw 0x2040, 0xc89e, 0x207f, 0xc89e, 0x21, 0 + .dw 0x20c0, 0xc89e, 0x20ff, 0xc89e, 0x21, 0 + .dw 0x2140, 0xc89e, 0x217f, 0xc89e, 0x21, 0 + .dw 0x21c0, 0xc89e, 0x21ff, 0xc89e, 0x21, 0 + .dw 0x2240, 0xc89e, 0x227f, 0xc89e, 0x21, 0 + .dw 0x22c0, 0xc89e, 0x22ff, 0xc89e, 0x21, 0 + .dw 0x2340, 0xc89e, 0x237f, 0xc89e, 0x21, 0 + .dw 0x23c0, 0xc89e, 0x23ff, 0xc89e, 0x21, 0 + .dw 0x2440, 0xc89e, 0x247f, 0xc89e, 0x21, 0 + .dw 0x24c0, 0xc89e, 0x24ff, 0xc89e, 0x21, 0 + .dw 0x2540, 0xc89e, 0x257f, 0xc89e, 0x21, 0 + .dw 0x25c0, 0xc89e, 0x25ff, 0xc89e, 0x21, 0 + .dw 0x2640, 0xc89e, 0x267f, 0xc89e, 0x21, 0 + .dw 0x26c0, 0xc89e, 0x26ff, 0xc89e, 0x21, 0 + .dw 0x2740, 0xc89e, 0x277f, 0xc89e, 0x21, 0 + .dw 0x27c0, 0xc89e, 0x27ff, 0xc89e, 0x21, 0 + .dw 0x2840, 0xc89e, 0x287f, 0xc89e, 0x21, 0 + .dw 0x28c0, 0xc89e, 0x28ff, 0xc89e, 0x21, 0 + .dw 0x2940, 0xc89e, 0x297f, 0xc89e, 0x21, 0 + .dw 0x29c0, 0xc89e, 0x29ff, 0xc89e, 0x21, 0 + .dw 0x2a40, 0xc89e, 0x2a7f, 0xc89e, 0x21, 0 + .dw 0x2ac0, 0xc89e, 0x2aff, 0xc89e, 0x21, 0 + .dw 0x2b40, 0xc89e, 0x2b7f, 0xc89e, 0x21, 0 + .dw 0x2bc0, 0xc89e, 0x2bff, 0xc89e, 0x21, 0 + .dw 0x2c40, 0xc89e, 0x2c7f, 0xc89e, 0x21, 0 + .dw 0x2cc0, 0xc89e, 0x2cff, 0xc89e, 0x21, 0 + .dw 0x2d40, 0xc89e, 0x2d7f, 0xc89e, 0x21, 0 + .dw 0x2dc0, 0xc89e, 0x2dff, 0xc89e, 0x21, 0 + .dw 0x2e40, 0xc89e, 0x2e7f, 0xc89e, 0x21, 0 + .dw 0x2ec0, 0xc89e, 0x2eff, 0xc89e, 0x21, 0 + .dw 0x2f40, 0xc89e, 0x2f7f, 0xc89e, 0x21, 0 + .dw 0x2fc0, 0xc89e, 0x2fff, 0xc89e, 0x21, 0 + .dw 0x3040, 0xc89e, 0x307f, 0xc89e, 0x21, 0 + .dw 0x30c0, 0xc89e, 0x30ff, 0xc89e, 0x21, 0 + .dw 0x3140, 0xc89e, 0x317f, 0xc89e, 0x21, 0 + .dw 0x31c0, 0xc89e, 0x31ff, 0xc89e, 0x21, 0 + .dw 0x3240, 0xc89e, 0x327f, 0xc89e, 0x21, 0 + .dw 0x32c0, 0xc89e, 0x32ff, 0xc89e, 0x21, 0 + .dw 0x3340, 0xc89e, 0x337f, 0xc89e, 0x21, 0 + .dw 0x33c0, 0xc89e, 0x33ff, 0xc89e, 0x21, 0 + .dw 0x3440, 0xc89e, 0x347f, 0xc89e, 0x21, 0 + .dw 0x34c0, 0xc89e, 0x34ff, 0xc89e, 0x21, 0 + .dw 0x3540, 0xc89e, 0x357f, 0xc89e, 0x21, 0 + .dw 0x35c0, 0xc89e, 0x35ff, 0xc89e, 0x21, 0 + .dw 0x3640, 0xc89e, 0x367f, 0xc89e, 0x21, 0 + .dw 0x36c0, 0xc89e, 0x36ff, 0xc89e, 0x21, 0 + .dw 0x3740, 0xc89e, 0x377f, 0xc89e, 0x21, 0 + .dw 0x37c0, 0xc89e, 0x37ff, 0xc89e, 0x21, 0 + .dw 0x3840, 0xc89e, 0x387f, 0xc89e, 0x21, 0 + .dw 0x38c0, 0xc89e, 0x38ff, 0xc89e, 0x21, 0 + .dw 0x3940, 0xc89e, 0x397f, 0xc89e, 0x21, 0 + .dw 0x39c0, 0xc89e, 0x3fff, 0xc89e, 0x21, 0 + .dw 0x4040, 0xc89e, 0x407f, 0xc89e, 0x21, 0 + .dw 0x40c0, 0xc89e, 0x40ff, 0xc89e, 0x21, 0 + .dw 0x4140, 0xc89e, 0x417f, 0xc89e, 0x21, 0 + .dw 0x41c0, 0xc89e, 0x41ff, 0xc89e, 0x21, 0 + .dw 0x4240, 0xc89e, 0x427f, 0xc89e, 0x21, 0 + .dw 0x42c0, 0xc89e, 0x42ff, 0xc89e, 0x21, 0 + .dw 0x4340, 0xc89e, 0x437f, 0xc89e, 0x21, 0 + .dw 0x43c0, 0xc89e, 0x43ff, 0xc89e, 0x21, 0 + .dw 0x4440, 0xc89e, 0x447f, 0xc89e, 0x21, 0 + .dw 0x44c0, 0xc89e, 0x44ff, 0xc89e, 0x21, 0 + .dw 0x4540, 0xc89e, 0x457f, 0xc89e, 0x21, 0 + .dw 0x45c0, 0xc89e, 0x45ff, 0xc89e, 0x21, 0 + .dw 0x4640, 0xc89e, 0x467f, 0xc89e, 0x21, 0 + .dw 0x46c0, 0xc89e, 0x46ff, 0xc89e, 0x21, 0 + .dw 0x4740, 0xc89e, 0x477f, 0xc89e, 0x21, 0 + .dw 0x47c0, 0xc89e, 0x47ff, 0xc89e, 0x21, 0 + .dw 0x4840, 0xc89e, 0x487f, 0xc89e, 0x21, 0 + .dw 0x48c0, 0xc89e, 0x48ff, 0xc89e, 0x21, 0 + .dw 0x4940, 0xc89e, 0x497f, 0xc89e, 0x21, 0 + .dw 0x49c0, 0xc89e, 0x49ff, 0xc89e, 0x21, 0 + .dw 0x4a40, 0xc89e, 0x4a7f, 0xc89e, 0x21, 0 + .dw 0x4ac0, 0xc89e, 0x4aff, 0xc89e, 0x21, 0 + .dw 0x4b40, 0xc89e, 0x4b7f, 0xc89e, 0x21, 0 + .dw 0x4bc0, 0xc89e, 0x4bff, 0xc89e, 0x21, 0 + .dw 0x4c40, 0xc89e, 0x4c7f, 0xc89e, 0x21, 0 + .dw 0x4cc0, 0xc89e, 0x4cff, 0xc89e, 0x21, 0 + .dw 0x4d40, 0xc89e, 0x4d7f, 0xc89e, 0x21, 0 + .dw 0x4dc0, 0xc89e, 0x4dff, 0xc89e, 0x21, 0 + .dw 0x4e40, 0xc89e, 0x4e7f, 0xc89e, 0x21, 0 + .dw 0x4ec0, 0xc89e, 0x4eff, 0xc89e, 0x21, 0 + .dw 0x4f40, 0xc89e, 0x4f7f, 0xc89e, 0x21, 0 + .dw 0x4fc0, 0xc89e, 0x4fff, 0xc89e, 0x21, 0 + .dw 0x5040, 0xc89e, 0x507f, 0xc89e, 0x21, 0 + .dw 0x50c0, 0xc89e, 0x50ff, 0xc89e, 0x21, 0 + .dw 0x5140, 0xc89e, 0x517f, 0xc89e, 0x21, 0 + .dw 0x51c0, 0xc89e, 0x51ff, 0xc89e, 0x21, 0 + .dw 0x5240, 0xc89e, 0x527f, 0xc89e, 0x21, 0 + .dw 0x52c0, 0xc89e, 0x52ff, 0xc89e, 0x21, 0 + .dw 0x5340, 0xc89e, 0x537f, 0xc89e, 0x21, 0 + .dw 0x53c0, 0xc89e, 0x53ff, 0xc89e, 0x21, 0 + .dw 0x5440, 0xc89e, 0x547f, 0xc89e, 0x21, 0 + .dw 0x54c0, 0xc89e, 0x54ff, 0xc89e, 0x21, 0 + .dw 0x5540, 0xc89e, 0x557f, 0xc89e, 0x21, 0 + .dw 0x55c0, 0xc89e, 0x55ff, 0xc89e, 0x21, 0 + .dw 0x5640, 0xc89e, 0x567f, 0xc89e, 0x21, 0 + .dw 0x56c0, 0xc89e, 0x56ff, 0xc89e, 0x21, 0 + .dw 0x5740, 0xc89e, 0x577f, 0xc89e, 0x21, 0 + .dw 0x57c0, 0xc89e, 0x57ff, 0xc89e, 0x21, 0 + .dw 0x5840, 0xc89e, 0x587f, 0xc89e, 0x21, 0 + .dw 0x58c0, 0xc89e, 0x58ff, 0xc89e, 0x21, 0 + .dw 0x5940, 0xc89e, 0x597f, 0xc89e, 0x21, 0 + .dw 0x59c0, 0xc89e, 0x5fff, 0xc89e, 0x21, 0 + .dw 0x6040, 0xc89e, 0x607f, 0xc89e, 0x21, 0 + .dw 0x60c0, 0xc89e, 0x60ff, 0xc89e, 0x21, 0 + .dw 0x6140, 0xc89e, 0x617f, 0xc89e, 0x21, 0 + .dw 0x61c0, 0xc89e, 0x61ff, 0xc89e, 0x21, 0 + .dw 0x6240, 0xc89e, 0x627f, 0xc89e, 0x21, 0 + .dw 0x62c0, 0xc89e, 0x62ff, 0xc89e, 0x21, 0 + .dw 0x6340, 0xc89e, 0x637f, 0xc89e, 0x21, 0 + .dw 0x63c0, 0xc89e, 0x63ff, 0xc89e, 0x21, 0 + .dw 0x6440, 0xc89e, 0x647f, 0xc89e, 0x21, 0 + .dw 0x64c0, 0xc89e, 0x64ff, 0xc89e, 0x21, 0 + .dw 0x6540, 0xc89e, 0x657f, 0xc89e, 0x21, 0 + .dw 0x65c0, 0xc89e, 0x65ff, 0xc89e, 0x21, 0 + .dw 0x6640, 0xc89e, 0x667f, 0xc89e, 0x21, 0 + .dw 0x66c0, 0xc89e, 0x66ff, 0xc89e, 0x21, 0 + .dw 0x6740, 0xc89e, 0x677f, 0xc89e, 0x21, 0 + .dw 0x67c0, 0xc89e, 0x67ff, 0xc89e, 0x21, 0 + .dw 0x6840, 0xc89e, 0x687f, 0xc89e, 0x21, 0 + .dw 0x68c0, 0xc89e, 0x68ff, 0xc89e, 0x21, 0 + .dw 0x6940, 0xc89e, 0x697f, 0xc89e, 0x21, 0 + .dw 0x69c0, 0xc89e, 0x69ff, 0xc89e, 0x21, 0 + .dw 0x6a40, 0xc89e, 0x6a7f, 0xc89e, 0x21, 0 + .dw 0x6ac0, 0xc89e, 0x6aff, 0xc89e, 0x21, 0 + .dw 0x6b40, 0xc89e, 0x6b7f, 0xc89e, 0x21, 0 + .dw 0x6bc0, 0xc89e, 0x6bff, 0xc89e, 0x21, 0 + .dw 0x6c40, 0xc89e, 0x6c7f, 0xc89e, 0x21, 0 + .dw 0x6cc0, 0xc89e, 0x6cff, 0xc89e, 0x21, 0 + .dw 0x6d40, 0xc89e, 0x6d7f, 0xc89e, 0x21, 0 + .dw 0x6dc0, 0xc89e, 0x6dff, 0xc89e, 0x21, 0 + .dw 0x6e40, 0xc89e, 0x6e7f, 0xc89e, 0x21, 0 + .dw 0x6ec0, 0xc89e, 0x6eff, 0xc89e, 0x21, 0 + .dw 0x6f40, 0xc89e, 0x6f7f, 0xc89e, 0x21, 0 + .dw 0x6fc0, 0xc89e, 0x6fff, 0xc89e, 0x21, 0 + .dw 0x7040, 0xc89e, 0x707f, 0xc89e, 0x21, 0 + .dw 0x70c0, 0xc89e, 0x70ff, 0xc89e, 0x21, 0 + .dw 0x7140, 0xc89e, 0x717f, 0xc89e, 0x21, 0 + .dw 0x71c0, 0xc89e, 0x71ff, 0xc89e, 0x21, 0 + .dw 0x7240, 0xc89e, 0x727f, 0xc89e, 0x21, 0 + .dw 0x72c0, 0xc89e, 0x72ff, 0xc89e, 0x21, 0 + .dw 0x7340, 0xc89e, 0x737f, 0xc89e, 0x21, 0 + .dw 0x73c0, 0xc89e, 0x73ff, 0xc89e, 0x21, 0 + .dw 0x7440, 0xc89e, 0x747f, 0xc89e, 0x21, 0 + .dw 0x74c0, 0xc89e, 0x74ff, 0xc89e, 0x21, 0 + .dw 0x7540, 0xc89e, 0x757f, 0xc89e, 0x21, 0 + .dw 0x75c0, 0xc89e, 0x75ff, 0xc89e, 0x21, 0 + .dw 0x7640, 0xc89e, 0x767f, 0xc89e, 0x21, 0 + .dw 0x76c0, 0xc89e, 0x76ff, 0xc89e, 0x21, 0 + .dw 0x7740, 0xc89e, 0x777f, 0xc89e, 0x21, 0 + .dw 0x77c0, 0xc89e, 0x77ff, 0xc89e, 0x21, 0 + .dw 0x7840, 0xc89e, 0x787f, 0xc89e, 0x21, 0 + .dw 0x78c0, 0xc89e, 0x78ff, 0xc89e, 0x21, 0 + .dw 0x7940, 0xc89e, 0x797f, 0xc89e, 0x21, 0 + .dw 0x79c0, 0xc89e, 0x7fff, 0xc89e, 0x21, 0 + .dw 0x8040, 0xc89e, 0x807f, 0xc89e, 0x21, 0 + .dw 0x80c0, 0xc89e, 0x80ff, 0xc89e, 0x21, 0 + .dw 0x8140, 0xc89e, 0x817f, 0xc89e, 0x21, 0 + .dw 0x81c0, 0xc89e, 0x81ff, 0xc89e, 0x21, 0 + .dw 0x8240, 0xc89e, 0x827f, 0xc89e, 0x21, 0 + .dw 0x82c0, 0xc89e, 0x82ff, 0xc89e, 0x21, 0 + .dw 0x8340, 0xc89e, 0x837f, 0xc89e, 0x21, 0 + .dw 0x83c0, 0xc89e, 0x83ff, 0xc89e, 0x21, 0 + .dw 0x8440, 0xc89e, 0x847f, 0xc89e, 0x21, 0 + .dw 0x84c0, 0xc89e, 0x84ff, 0xc89e, 0x21, 0 + .dw 0x8540, 0xc89e, 0x857f, 0xc89e, 0x21, 0 + .dw 0x85c0, 0xc89e, 0x85ff, 0xc89e, 0x21, 0 + .dw 0x8640, 0xc89e, 0x867f, 0xc89e, 0x21, 0 + .dw 0x86c0, 0xc89e, 0x86ff, 0xc89e, 0x21, 0 + .dw 0x8740, 0xc89e, 0x877f, 0xc89e, 0x21, 0 + .dw 0x87c0, 0xc89e, 0x87ff, 0xc89e, 0x21, 0 + .dw 0x8840, 0xc89e, 0x887f, 0xc89e, 0x21, 0 + .dw 0x88c0, 0xc89e, 0x88ff, 0xc89e, 0x21, 0 + .dw 0x8940, 0xc89e, 0x897f, 0xc89e, 0x21, 0 + .dw 0x89c0, 0xc89e, 0x89ff, 0xc89e, 0x21, 0 + .dw 0x8a40, 0xc89e, 0x8a7f, 0xc89e, 0x21, 0 + .dw 0x8ac0, 0xc89e, 0x8aff, 0xc89e, 0x21, 0 + .dw 0x8b40, 0xc89e, 0x8b7f, 0xc89e, 0x21, 0 + .dw 0x8bc0, 0xc89e, 0x8bff, 0xc89e, 0x21, 0 + .dw 0x8c40, 0xc89e, 0x8c7f, 0xc89e, 0x21, 0 + .dw 0x8cc0, 0xc89e, 0x8cff, 0xc89e, 0x21, 0 + .dw 0x8d40, 0xc89e, 0x8d7f, 0xc89e, 0x21, 0 + .dw 0x8dc0, 0xc89e, 0x8dff, 0xc89e, 0x21, 0 + .dw 0x8e40, 0xc89e, 0x8e7f, 0xc89e, 0x21, 0 + .dw 0x8ec0, 0xc89e, 0x8eff, 0xc89e, 0x21, 0 + .dw 0x8f40, 0xc89e, 0x8f7f, 0xc89e, 0x21, 0 + .dw 0x8fc0, 0xc89e, 0x8fff, 0xc89e, 0x21, 0 + .dw 0x9040, 0xc89e, 0x907f, 0xc89e, 0x21, 0 + .dw 0x90c0, 0xc89e, 0x90ff, 0xc89e, 0x21, 0 + .dw 0x9140, 0xc89e, 0x917f, 0xc89e, 0x21, 0 + .dw 0x91c0, 0xc89e, 0x91ff, 0xc89e, 0x21, 0 + .dw 0x9240, 0xc89e, 0x927f, 0xc89e, 0x21, 0 + .dw 0x92c0, 0xc89e, 0x92ff, 0xc89e, 0x21, 0 + .dw 0x9340, 0xc89e, 0x937f, 0xc89e, 0x21, 0 + .dw 0x93c0, 0xc89e, 0x93ff, 0xc89e, 0x21, 0 + .dw 0x9440, 0xc89e, 0x947f, 0xc89e, 0x21, 0 + .dw 0x94c0, 0xc89e, 0x94ff, 0xc89e, 0x21, 0 + .dw 0x9540, 0xc89e, 0x957f, 0xc89e, 0x21, 0 + .dw 0x95c0, 0xc89e, 0x95ff, 0xc89e, 0x21, 0 + .dw 0x9640, 0xc89e, 0x967f, 0xc89e, 0x21, 0 + .dw 0x96c0, 0xc89e, 0x96ff, 0xc89e, 0x21, 0 + .dw 0x9740, 0xc89e, 0x977f, 0xc89e, 0x21, 0 + .dw 0x97c0, 0xc89e, 0x97ff, 0xc89e, 0x21, 0 + .dw 0x9840, 0xc89e, 0x987f, 0xc89e, 0x21, 0 + .dw 0x98c0, 0xc89e, 0x98ff, 0xc89e, 0x21, 0 + .dw 0x9940, 0xc89e, 0x997f, 0xc89e, 0x21, 0 + .dw 0x99c0, 0xc89e, 0x9fff, 0xc89e, 0x21, 0 + .dw 0xa040, 0xc89e, 0xa07f, 0xc89e, 0x21, 0 + .dw 0xa0c0, 0xc89e, 0xa0ff, 0xc89e, 0x21, 0 + .dw 0xa140, 0xc89e, 0xa17f, 0xc89e, 0x21, 0 + .dw 0xa1c0, 0xc89e, 0xa1ff, 0xc89e, 0x21, 0 + .dw 0xa240, 0xc89e, 0xa27f, 0xc89e, 0x21, 0 + .dw 0xa2c0, 0xc89e, 0xa2ff, 0xc89e, 0x21, 0 + .dw 0xa340, 0xc89e, 0xa37f, 0xc89e, 0x21, 0 + .dw 0xa3c0, 0xc89e, 0xa3ff, 0xc89e, 0x21, 0 + .dw 0xa440, 0xc89e, 0xa47f, 0xc89e, 0x21, 0 + .dw 0xa4c0, 0xc89e, 0xa4ff, 0xc89e, 0x21, 0 + .dw 0xa540, 0xc89e, 0xa57f, 0xc89e, 0x21, 0 + .dw 0xa5c0, 0xc89e, 0xa5ff, 0xc89e, 0x21, 0 + .dw 0xa640, 0xc89e, 0xa67f, 0xc89e, 0x21, 0 + .dw 0xa6c0, 0xc89e, 0xa6ff, 0xc89e, 0x21, 0 + .dw 0xa740, 0xc89e, 0xa77f, 0xc89e, 0x21, 0 + .dw 0xa7c0, 0xc89e, 0xa7ff, 0xc89e, 0x21, 0 + .dw 0xa840, 0xc89e, 0xa87f, 0xc89e, 0x21, 0 + .dw 0xa8c0, 0xc89e, 0xa8ff, 0xc89e, 0x21, 0 + .dw 0xa940, 0xc89e, 0xa97f, 0xc89e, 0x21, 0 + .dw 0xa9c0, 0xc89e, 0xa9ff, 0xc89e, 0x21, 0 + .dw 0xaa40, 0xc89e, 0xaa7f, 0xc89e, 0x21, 0 + .dw 0xaac0, 0xc89e, 0xaaff, 0xc89e, 0x21, 0 + .dw 0xab40, 0xc89e, 0xab7f, 0xc89e, 0x21, 0 + .dw 0xabc0, 0xc89e, 0xabff, 0xc89e, 0x21, 0 + .dw 0xac40, 0xc89e, 0xac7f, 0xc89e, 0x21, 0 + .dw 0xacc0, 0xc89e, 0xacff, 0xc89e, 0x21, 0 + .dw 0xad40, 0xc89e, 0xad7f, 0xc89e, 0x21, 0 + .dw 0xadc0, 0xc89e, 0xadff, 0xc89e, 0x21, 0 + .dw 0xae40, 0xc89e, 0xae7f, 0xc89e, 0x21, 0 + .dw 0xaec0, 0xc89e, 0xaeff, 0xc89e, 0x21, 0 + .dw 0xaf40, 0xc89e, 0xaf7f, 0xc89e, 0x21, 0 + .dw 0xafc0, 0xc89e, 0xafff, 0xc89e, 0x21, 0 + .dw 0xb040, 0xc89e, 0xb07f, 0xc89e, 0x21, 0 + .dw 0xb0c0, 0xc89e, 0xb0ff, 0xc89e, 0x21, 0 + .dw 0xb140, 0xc89e, 0xb17f, 0xc89e, 0x21, 0 + .dw 0xb1c0, 0xc89e, 0xb1ff, 0xc89e, 0x21, 0 + .dw 0xb240, 0xc89e, 0xb27f, 0xc89e, 0x21, 0 + .dw 0xb2c0, 0xc89e, 0xb2ff, 0xc89e, 0x21, 0 + .dw 0xb340, 0xc89e, 0xb37f, 0xc89e, 0x21, 0 + .dw 0xb3c0, 0xc89e, 0xb3ff, 0xc89e, 0x21, 0 + .dw 0xb440, 0xc89e, 0xb47f, 0xc89e, 0x21, 0 + .dw 0xb4c0, 0xc89e, 0xb4ff, 0xc89e, 0x21, 0 + .dw 0xb540, 0xc89e, 0xb57f, 0xc89e, 0x21, 0 + .dw 0xb5c0, 0xc89e, 0xb5ff, 0xc89e, 0x21, 0 + .dw 0xb640, 0xc89e, 0xb67f, 0xc89e, 0x21, 0 + .dw 0xb6c0, 0xc89e, 0xb6ff, 0xc89e, 0x21, 0 + .dw 0xb740, 0xc89e, 0xb77f, 0xc89e, 0x21, 0 + .dw 0xb7c0, 0xc89e, 0xb7ff, 0xc89e, 0x21, 0 + .dw 0xb840, 0xc89e, 0xb87f, 0xc89e, 0x21, 0 + .dw 0xb8c0, 0xc89e, 0xb8ff, 0xc89e, 0x21, 0 + .dw 0xb940, 0xc89e, 0xb97f, 0xc89e, 0x21, 0 + .dw 0xb9c0, 0xc89e, 0xbfff, 0xc89e, 0x21, 0 + .dw 0xc040, 0xc89e, 0xc07f, 0xc89e, 0x21, 0 + .dw 0xc0c0, 0xc89e, 0xc0ff, 0xc89e, 0x21, 0 + .dw 0xc140, 0xc89e, 0xc17f, 0xc89e, 0x21, 0 + .dw 0xc1c0, 0xc89e, 0xc1ff, 0xc89e, 0x21, 0 + .dw 0xc240, 0xc89e, 0xc27f, 0xc89e, 0x21, 0 + .dw 0xc2c0, 0xc89e, 0xc2ff, 0xc89e, 0x21, 0 + .dw 0xc340, 0xc89e, 0xc37f, 0xc89e, 0x21, 0 + .dw 0xc3c0, 0xc89e, 0xc3ff, 0xc89e, 0x21, 0 + .dw 0xc440, 0xc89e, 0xc47f, 0xc89e, 0x21, 0 + .dw 0xc4c0, 0xc89e, 0xc4ff, 0xc89e, 0x21, 0 + .dw 0xc540, 0xc89e, 0xc57f, 0xc89e, 0x21, 0 + .dw 0xc5c0, 0xc89e, 0xc5ff, 0xc89e, 0x21, 0 + .dw 0xc640, 0xc89e, 0xc67f, 0xc89e, 0x21, 0 + .dw 0xc6c0, 0xc89e, 0xc6ff, 0xc89e, 0x21, 0 + .dw 0xc740, 0xc89e, 0xc77f, 0xc89e, 0x21, 0 + .dw 0xc7c0, 0xc89e, 0xc7ff, 0xc89e, 0x21, 0 + .dw 0xc840, 0xc89e, 0xc87f, 0xc89e, 0x21, 0 + .dw 0xc8c0, 0xc89e, 0xc8ff, 0xc89e, 0x21, 0 + .dw 0xc940, 0xc89e, 0xc97f, 0xc89e, 0x21, 0 + .dw 0xc9c0, 0xc89e, 0xc9ff, 0xc89e, 0x21, 0 + .dw 0xca40, 0xc89e, 0xca7f, 0xc89e, 0x21, 0 + .dw 0xcac0, 0xc89e, 0xcaff, 0xc89e, 0x21, 0 + .dw 0xcb40, 0xc89e, 0xcb7f, 0xc89e, 0x21, 0 + .dw 0xcbc0, 0xc89e, 0xcbff, 0xc89e, 0x21, 0 + .dw 0xcc40, 0xc89e, 0xcc7f, 0xc89e, 0x21, 0 + .dw 0xccc0, 0xc89e, 0xccff, 0xc89e, 0x21, 0 + .dw 0xcd40, 0xc89e, 0xcd7f, 0xc89e, 0x21, 0 + .dw 0xcdc0, 0xc89e, 0xcdff, 0xc89e, 0x21, 0 + .dw 0xce40, 0xc89e, 0xce7f, 0xc89e, 0x21, 0 + .dw 0xcec0, 0xc89e, 0xceff, 0xc89e, 0x21, 0 + .dw 0xcf40, 0xc89e, 0xcf7f, 0xc89e, 0x21, 0 + .dw 0xcfc0, 0xc89e, 0xcfff, 0xc89e, 0x21, 0 + .dw 0xd040, 0xc89e, 0xd07f, 0xc89e, 0x21, 0 + .dw 0xd0c0, 0xc89e, 0xd0ff, 0xc89e, 0x21, 0 + .dw 0xd140, 0xc89e, 0xd17f, 0xc89e, 0x21, 0 + .dw 0xd1c0, 0xc89e, 0xd1ff, 0xc89e, 0x21, 0 + .dw 0xd240, 0xc89e, 0xd27f, 0xc89e, 0x21, 0 + .dw 0xd2c0, 0xc89e, 0xd2ff, 0xc89e, 0x21, 0 + .dw 0xd340, 0xc89e, 0xd37f, 0xc89e, 0x21, 0 + .dw 0xd3c0, 0xc89e, 0xd3ff, 0xc89e, 0x21, 0 + .dw 0xd440, 0xc89e, 0xd47f, 0xc89e, 0x21, 0 + .dw 0xd4c0, 0xc89e, 0xd4ff, 0xc89e, 0x21, 0 + .dw 0xd540, 0xc89e, 0xd57f, 0xc89e, 0x21, 0 + .dw 0xd5c0, 0xc89e, 0xd5ff, 0xc89e, 0x21, 0 + .dw 0xd640, 0xc89e, 0xd67f, 0xc89e, 0x21, 0 + .dw 0xd6c0, 0xc89e, 0xd6ff, 0xc89e, 0x21, 0 + .dw 0xd740, 0xc89e, 0xd77f, 0xc89e, 0x21, 0 + .dw 0xd7c0, 0xc89e, 0xd7ff, 0xc89e, 0x21, 0 + .dw 0xd840, 0xc89e, 0xd87f, 0xc89e, 0x21, 0 + .dw 0xd8c0, 0xc89e, 0xd8ff, 0xc89e, 0x21, 0 + .dw 0xd940, 0xc89e, 0xd97f, 0xc89e, 0x21, 0 + .dw 0xd9c0, 0xc89e, 0xdfff, 0xc89e, 0x21, 0 + .dw 0xe040, 0xc89e, 0xe07f, 0xc89e, 0x21, 0 + .dw 0xe0c0, 0xc89e, 0xe0ff, 0xc89e, 0x21, 0 + .dw 0xe140, 0xc89e, 0xe17f, 0xc89e, 0x21, 0 + .dw 0xe1c0, 0xc89e, 0xe1ff, 0xc89e, 0x21, 0 + .dw 0xe240, 0xc89e, 0xe27f, 0xc89e, 0x21, 0 + .dw 0xe2c0, 0xc89e, 0xe2ff, 0xc89e, 0x21, 0 + .dw 0xe340, 0xc89e, 0xe37f, 0xc89e, 0x21, 0 + .dw 0xe3c0, 0xc89e, 0xe3ff, 0xc89e, 0x21, 0 + .dw 0xe440, 0xc89e, 0xe47f, 0xc89e, 0x21, 0 + .dw 0xe4c0, 0xc89e, 0xe4ff, 0xc89e, 0x21, 0 + .dw 0xe540, 0xc89e, 0xe57f, 0xc89e, 0x21, 0 + .dw 0xe5c0, 0xc89e, 0xe5ff, 0xc89e, 0x21, 0 + .dw 0xe640, 0xc89e, 0xe67f, 0xc89e, 0x21, 0 + .dw 0xe6c0, 0xc89e, 0xe6ff, 0xc89e, 0x21, 0 + .dw 0xe740, 0xc89e, 0xe77f, 0xc89e, 0x21, 0 + .dw 0xe7c0, 0xc89e, 0xe7ff, 0xc89e, 0x21, 0 + .dw 0xe840, 0xc89e, 0xe87f, 0xc89e, 0x21, 0 + .dw 0xe8c0, 0xc89e, 0xe8ff, 0xc89e, 0x21, 0 + .dw 0xe940, 0xc89e, 0xe97f, 0xc89e, 0x21, 0 + .dw 0xe9c0, 0xc89e, 0xe9ff, 0xc89e, 0x21, 0 + .dw 0xea40, 0xc89e, 0xea7f, 0xc89e, 0x21, 0 + .dw 0xeac0, 0xc89e, 0xeaff, 0xc89e, 0x21, 0 + .dw 0xeb40, 0xc89e, 0xeb7f, 0xc89e, 0x21, 0 + .dw 0xebc0, 0xc89e, 0xebff, 0xc89e, 0x21, 0 + .dw 0xec40, 0xc89e, 0xec7f, 0xc89e, 0x21, 0 + .dw 0xecc0, 0xc89e, 0xecff, 0xc89e, 0x21, 0 + .dw 0xed40, 0xc89e, 0xed7f, 0xc89e, 0x21, 0 + .dw 0xedc0, 0xc89e, 0xedff, 0xc89e, 0x21, 0 + .dw 0xee40, 0xc89e, 0xee7f, 0xc89e, 0x21, 0 + .dw 0xeec0, 0xc89e, 0xeeff, 0xc89e, 0x21, 0 + .dw 0xef40, 0xc89e, 0xef7f, 0xc89e, 0x21, 0 + .dw 0xefc0, 0xc89e, 0xefff, 0xc89e, 0x21, 0 + .dw 0xf040, 0xc89e, 0xf07f, 0xc89e, 0x21, 0 + .dw 0xf0c0, 0xc89e, 0xf0ff, 0xc89e, 0x21, 0 + .dw 0xf140, 0xc89e, 0xf17f, 0xc89e, 0x21, 0 + .dw 0xf1c0, 0xc89e, 0xf1ff, 0xc89e, 0x21, 0 + .dw 0xf240, 0xc89e, 0xf27f, 0xc89e, 0x21, 0 + .dw 0xf2c0, 0xc89e, 0xf2ff, 0xc89e, 0x21, 0 + .dw 0xf340, 0xc89e, 0xf37f, 0xc89e, 0x21, 0 + .dw 0xf3c0, 0xc89e, 0xf3ff, 0xc89e, 0x21, 0 + .dw 0xf440, 0xc89e, 0xf47f, 0xc89e, 0x21, 0 + .dw 0xf4c0, 0xc89e, 0xf4ff, 0xc89e, 0x21, 0 + .dw 0xf540, 0xc89e, 0xf57f, 0xc89e, 0x21, 0 + .dw 0xf5c0, 0xc89e, 0xf5ff, 0xc89e, 0x21, 0 + .dw 0xf640, 0xc89e, 0xf67f, 0xc89e, 0x21, 0 + .dw 0xf6c0, 0xc89e, 0xf6ff, 0xc89e, 0x21, 0 + .dw 0xf740, 0xc89e, 0xf77f, 0xc89e, 0x21, 0 + .dw 0xf7c0, 0xc89e, 0xf7ff, 0xc89e, 0x21, 0 + .dw 0xf840, 0xc89e, 0xf87f, 0xc89e, 0x21, 0 + .dw 0xf8c0, 0xc89e, 0xf8ff, 0xc89e, 0x21, 0 + .dw 0xf940, 0xc89e, 0xf97f, 0xc89e, 0x21, 0 + .dw 0xf9c0, 0xc89e, 0xffff, 0xc89e, 0x21, 0 + .dw 0x0040, 0xc89f, 0x007f, 0xc89f, 0x21, 0 + .dw 0x00c0, 0xc89f, 0x00ff, 0xc89f, 0x21, 0 + .dw 0x0140, 0xc89f, 0x017f, 0xc89f, 0x21, 0 + .dw 0x01c0, 0xc89f, 0x01ff, 0xc89f, 0x21, 0 + .dw 0x0240, 0xc89f, 0x027f, 0xc89f, 0x21, 0 + .dw 0x02c0, 0xc89f, 0x02ff, 0xc89f, 0x21, 0 + .dw 0x0340, 0xc89f, 0x037f, 0xc89f, 0x21, 0 + .dw 0x03c0, 0xc89f, 0x03ff, 0xc89f, 0x21, 0 + .dw 0x0440, 0xc89f, 0x047f, 0xc89f, 0x21, 0 + .dw 0x04c0, 0xc89f, 0x04ff, 0xc89f, 0x21, 0 + .dw 0x0540, 0xc89f, 0x057f, 0xc89f, 0x21, 0 + .dw 0x05c0, 0xc89f, 0x05ff, 0xc89f, 0x21, 0 + .dw 0x0640, 0xc89f, 0x067f, 0xc89f, 0x21, 0 + .dw 0x06c0, 0xc89f, 0x06ff, 0xc89f, 0x21, 0 + .dw 0x0740, 0xc89f, 0x077f, 0xc89f, 0x21, 0 + .dw 0x07c0, 0xc89f, 0x07ff, 0xc89f, 0x21, 0 + .dw 0x0840, 0xc89f, 0x087f, 0xc89f, 0x21, 0 + .dw 0x08c0, 0xc89f, 0x08ff, 0xc89f, 0x21, 0 + .dw 0x0940, 0xc89f, 0x097f, 0xc89f, 0x21, 0 + .dw 0x09c0, 0xc89f, 0x09ff, 0xc89f, 0x21, 0 + .dw 0x0a40, 0xc89f, 0x0a7f, 0xc89f, 0x21, 0 + .dw 0x0ac0, 0xc89f, 0x0aff, 0xc89f, 0x21, 0 + .dw 0x0b40, 0xc89f, 0x0b7f, 0xc89f, 0x21, 0 + .dw 0x0bc0, 0xc89f, 0x0bff, 0xc89f, 0x21, 0 + .dw 0x0c40, 0xc89f, 0x0c7f, 0xc89f, 0x21, 0 + .dw 0x0cc0, 0xc89f, 0x0cff, 0xc89f, 0x21, 0 + .dw 0x0d40, 0xc89f, 0x0d7f, 0xc89f, 0x21, 0 + .dw 0x0dc0, 0xc89f, 0x0dff, 0xc89f, 0x21, 0 + .dw 0x0e40, 0xc89f, 0x0e7f, 0xc89f, 0x21, 0 + .dw 0x0ec0, 0xc89f, 0x0eff, 0xc89f, 0x21, 0 + .dw 0x0f40, 0xc89f, 0x0f7f, 0xc89f, 0x21, 0 + .dw 0x0fc0, 0xc89f, 0x0fff, 0xc89f, 0x21, 0 + .dw 0x1040, 0xc89f, 0x107f, 0xc89f, 0x21, 0 + .dw 0x10c0, 0xc89f, 0x10ff, 0xc89f, 0x21, 0 + .dw 0x1140, 0xc89f, 0x117f, 0xc89f, 0x21, 0 + .dw 0x11c0, 0xc89f, 0x11ff, 0xc89f, 0x21, 0 + .dw 0x1240, 0xc89f, 0x127f, 0xc89f, 0x21, 0 + .dw 0x12c0, 0xc89f, 0x12ff, 0xc89f, 0x21, 0 + .dw 0x1340, 0xc89f, 0x137f, 0xc89f, 0x21, 0 + .dw 0x13c0, 0xc89f, 0x13ff, 0xc89f, 0x21, 0 + .dw 0x1440, 0xc89f, 0x147f, 0xc89f, 0x21, 0 + .dw 0x14c0, 0xc89f, 0x14ff, 0xc89f, 0x21, 0 + .dw 0x1540, 0xc89f, 0x157f, 0xc89f, 0x21, 0 + .dw 0x15c0, 0xc89f, 0x15ff, 0xc89f, 0x21, 0 + .dw 0x1640, 0xc89f, 0x167f, 0xc89f, 0x21, 0 + .dw 0x16c0, 0xc89f, 0x16ff, 0xc89f, 0x21, 0 + .dw 0x1740, 0xc89f, 0x177f, 0xc89f, 0x21, 0 + .dw 0x17c0, 0xc89f, 0x17ff, 0xc89f, 0x21, 0 + .dw 0x1840, 0xc89f, 0x187f, 0xc89f, 0x21, 0 + .dw 0x18c0, 0xc89f, 0x18ff, 0xc89f, 0x21, 0 + .dw 0x1940, 0xc89f, 0x197f, 0xc89f, 0x21, 0 + .dw 0x19c0, 0xc89f, 0x1fff, 0xc89f, 0x21, 0 + .dw 0x2040, 0xc89f, 0x207f, 0xc89f, 0x21, 0 + .dw 0x20c0, 0xc89f, 0x20ff, 0xc89f, 0x21, 0 + .dw 0x2140, 0xc89f, 0x217f, 0xc89f, 0x21, 0 + .dw 0x21c0, 0xc89f, 0x21ff, 0xc89f, 0x21, 0 + .dw 0x2240, 0xc89f, 0x227f, 0xc89f, 0x21, 0 + .dw 0x22c0, 0xc89f, 0x22ff, 0xc89f, 0x21, 0 + .dw 0x2340, 0xc89f, 0x237f, 0xc89f, 0x21, 0 + .dw 0x23c0, 0xc89f, 0x23ff, 0xc89f, 0x21, 0 + .dw 0x2440, 0xc89f, 0x247f, 0xc89f, 0x21, 0 + .dw 0x24c0, 0xc89f, 0x24ff, 0xc89f, 0x21, 0 + .dw 0x2540, 0xc89f, 0x257f, 0xc89f, 0x21, 0 + .dw 0x25c0, 0xc89f, 0x25ff, 0xc89f, 0x21, 0 + .dw 0x2640, 0xc89f, 0x267f, 0xc89f, 0x21, 0 + .dw 0x26c0, 0xc89f, 0x26ff, 0xc89f, 0x21, 0 + .dw 0x2740, 0xc89f, 0x277f, 0xc89f, 0x21, 0 + .dw 0x27c0, 0xc89f, 0x27ff, 0xc89f, 0x21, 0 + .dw 0x2840, 0xc89f, 0x287f, 0xc89f, 0x21, 0 + .dw 0x28c0, 0xc89f, 0x28ff, 0xc89f, 0x21, 0 + .dw 0x2940, 0xc89f, 0x297f, 0xc89f, 0x21, 0 + .dw 0x29c0, 0xc89f, 0x29ff, 0xc89f, 0x21, 0 + .dw 0x2a40, 0xc89f, 0x2a7f, 0xc89f, 0x21, 0 + .dw 0x2ac0, 0xc89f, 0x2aff, 0xc89f, 0x21, 0 + .dw 0x2b40, 0xc89f, 0x2b7f, 0xc89f, 0x21, 0 + .dw 0x2bc0, 0xc89f, 0x2bff, 0xc89f, 0x21, 0 + .dw 0x2c40, 0xc89f, 0x2c7f, 0xc89f, 0x21, 0 + .dw 0x2cc0, 0xc89f, 0x2cff, 0xc89f, 0x21, 0 + .dw 0x2d40, 0xc89f, 0x2d7f, 0xc89f, 0x21, 0 + .dw 0x2dc0, 0xc89f, 0x2dff, 0xc89f, 0x21, 0 + .dw 0x2e40, 0xc89f, 0x2e7f, 0xc89f, 0x21, 0 + .dw 0x2ec0, 0xc89f, 0x2eff, 0xc89f, 0x21, 0 + .dw 0x2f40, 0xc89f, 0x2f7f, 0xc89f, 0x21, 0 + .dw 0x2fc0, 0xc89f, 0x2fff, 0xc89f, 0x21, 0 + .dw 0x3040, 0xc89f, 0x307f, 0xc89f, 0x21, 0 + .dw 0x30c0, 0xc89f, 0x30ff, 0xc89f, 0x21, 0 + .dw 0x3140, 0xc89f, 0x317f, 0xc89f, 0x21, 0 + .dw 0x31c0, 0xc89f, 0x31ff, 0xc89f, 0x21, 0 + .dw 0x3240, 0xc89f, 0x327f, 0xc89f, 0x21, 0 + .dw 0x32c0, 0xc89f, 0x32ff, 0xc89f, 0x21, 0 + .dw 0x3340, 0xc89f, 0x337f, 0xc89f, 0x21, 0 + .dw 0x33c0, 0xc89f, 0x33ff, 0xc89f, 0x21, 0 + .dw 0x3440, 0xc89f, 0x347f, 0xc89f, 0x21, 0 + .dw 0x34c0, 0xc89f, 0x34ff, 0xc89f, 0x21, 0 + .dw 0x3540, 0xc89f, 0x357f, 0xc89f, 0x21, 0 + .dw 0x35c0, 0xc89f, 0x35ff, 0xc89f, 0x21, 0 + .dw 0x3640, 0xc89f, 0x367f, 0xc89f, 0x21, 0 + .dw 0x36c0, 0xc89f, 0x36ff, 0xc89f, 0x21, 0 + .dw 0x3740, 0xc89f, 0x377f, 0xc89f, 0x21, 0 + .dw 0x37c0, 0xc89f, 0x37ff, 0xc89f, 0x21, 0 + .dw 0x3840, 0xc89f, 0x387f, 0xc89f, 0x21, 0 + .dw 0x38c0, 0xc89f, 0x38ff, 0xc89f, 0x21, 0 + .dw 0x3940, 0xc89f, 0x397f, 0xc89f, 0x21, 0 + .dw 0x39c0, 0xc89f, 0x1fff, 0xc8c0, 0x21, 0 + .dw 0x3a00, 0xc8c0, 0x5fff, 0xc8c0, 0x21, 0 + .dw 0x7a00, 0xc8c0, 0x9fff, 0xc8c0, 0x21, 0 + .dw 0xba00, 0xc8c0, 0xdfff, 0xc8c0, 0x21, 0 + .dw 0xfa00, 0xc8c0, 0x1fff, 0xc8c1, 0x21, 0 + .dw 0x3a00, 0xc8c1, 0x5fff, 0xc8c1, 0x21, 0 + .dw 0x7a00, 0xc8c1, 0x9fff, 0xc8c1, 0x21, 0 + .dw 0xba00, 0xc8c1, 0xdfff, 0xc8c1, 0x21, 0 + .dw 0xfa00, 0xc8c1, 0x1fff, 0xc8c2, 0x21, 0 + .dw 0x3a00, 0xc8c2, 0x5fff, 0xc8c2, 0x21, 0 + .dw 0x7a00, 0xc8c2, 0x9fff, 0xc8c2, 0x21, 0 + .dw 0xba00, 0xc8c2, 0xdfff, 0xc8c2, 0x21, 0 + .dw 0xfa00, 0xc8c2, 0x1fff, 0xc8c3, 0x21, 0 + .dw 0x3a00, 0xc8c3, 0xffff, 0xc8c3, 0x21, 0 + .dw 0x1a00, 0xc8c4, 0x1fff, 0xc8c4, 0x21, 0 + .dw 0x3a00, 0xc8c4, 0x3fff, 0xc8c4, 0x21, 0 + .dw 0x5a00, 0xc8c4, 0x5fff, 0xc8c4, 0x21, 0 + .dw 0x7a00, 0xc8c4, 0x7fff, 0xc8c4, 0x21, 0 + .dw 0x9a00, 0xc8c4, 0x9fff, 0xc8c4, 0x21, 0 + .dw 0xba00, 0xc8c4, 0xbfff, 0xc8c4, 0x21, 0 + .dw 0xda00, 0xc8c4, 0xdfff, 0xc8c4, 0x21, 0 + .dw 0xfa00, 0xc8c4, 0xffff, 0xc8c4, 0x21, 0 + .dw 0x1a00, 0xc8c5, 0x1fff, 0xc8c5, 0x21, 0 + .dw 0x3a00, 0xc8c5, 0x3fff, 0xc8c5, 0x21, 0 + .dw 0x5a00, 0xc8c5, 0x5fff, 0xc8c5, 0x21, 0 + .dw 0x7a00, 0xc8c5, 0x7fff, 0xc8c5, 0x21, 0 + .dw 0x9a00, 0xc8c5, 0x9fff, 0xc8c5, 0x21, 0 + .dw 0xba00, 0xc8c5, 0xbfff, 0xc8c5, 0x21, 0 + .dw 0xda00, 0xc8c5, 0xdfff, 0xc8c5, 0x21, 0 + .dw 0xfa00, 0xc8c5, 0xffff, 0xc8c5, 0x21, 0 + .dw 0x1a00, 0xc8c6, 0x1fff, 0xc8c6, 0x21, 0 + .dw 0x3a00, 0xc8c6, 0x3fff, 0xc8c6, 0x21, 0 + .dw 0x5a00, 0xc8c6, 0x5fff, 0xc8c6, 0x21, 0 + .dw 0x7a00, 0xc8c6, 0x7fff, 0xc8c6, 0x21, 0 + .dw 0x9a00, 0xc8c6, 0x9fff, 0xc8c6, 0x21, 0 + .dw 0xba00, 0xc8c6, 0xbfff, 0xc8c6, 0x21, 0 + .dw 0xda00, 0xc8c6, 0xdfff, 0xc8c6, 0x21, 0 + .dw 0xfa00, 0xc8c6, 0xffff, 0xc8c6, 0x21, 0 + .dw 0x1a00, 0xc8c7, 0x1fff, 0xc8c7, 0x21, 0 + .dw 0x3a00, 0xc8c7, 0x1fff, 0xc8d0, 0x21, 0 + .dw 0x3a00, 0xc8d0, 0x5fff, 0xc8d0, 0x21, 0 + .dw 0x7a00, 0xc8d0, 0x9fff, 0xc8d0, 0x21, 0 + .dw 0xba00, 0xc8d0, 0xdfff, 0xc8d0, 0x21, 0 + .dw 0xfa00, 0xc8d0, 0x1fff, 0xc8d1, 0x21, 0 + .dw 0x3a00, 0xc8d1, 0x5fff, 0xc8d1, 0x21, 0 + .dw 0x7a00, 0xc8d1, 0x9fff, 0xc8d1, 0x21, 0 + .dw 0xba00, 0xc8d1, 0xdfff, 0xc8d1, 0x21, 0 + .dw 0xfa00, 0xc8d1, 0x1fff, 0xc8d2, 0x21, 0 + .dw 0x3a00, 0xc8d2, 0x5fff, 0xc8d2, 0x21, 0 + .dw 0x7a00, 0xc8d2, 0x9fff, 0xc8d2, 0x21, 0 + .dw 0xba00, 0xc8d2, 0xdfff, 0xc8d2, 0x21, 0 + .dw 0xfa00, 0xc8d2, 0xffff, 0xc8d3, 0x21, 0 + .dw 0x1a00, 0xc8d4, 0x1fff, 0xc8d4, 0x21, 0 + .dw 0x3a00, 0xc8d4, 0x3fff, 0xc8d4, 0x21, 0 + .dw 0x5a00, 0xc8d4, 0x5fff, 0xc8d4, 0x21, 0 + .dw 0x7a00, 0xc8d4, 0x7fff, 0xc8d4, 0x21, 0 + .dw 0x9a00, 0xc8d4, 0x9fff, 0xc8d4, 0x21, 0 + .dw 0xba00, 0xc8d4, 0xbfff, 0xc8d4, 0x21, 0 + .dw 0xda00, 0xc8d4, 0xdfff, 0xc8d4, 0x21, 0 + .dw 0xfa00, 0xc8d4, 0xffff, 0xc8d4, 0x21, 0 + .dw 0x1a00, 0xc8d5, 0x1fff, 0xc8d5, 0x21, 0 + .dw 0x3a00, 0xc8d5, 0x3fff, 0xc8d5, 0x21, 0 + .dw 0x5a00, 0xc8d5, 0x5fff, 0xc8d5, 0x21, 0 + .dw 0x7a00, 0xc8d5, 0x7fff, 0xc8d5, 0x21, 0 + .dw 0x9a00, 0xc8d5, 0x9fff, 0xc8d5, 0x21, 0 + .dw 0xba00, 0xc8d5, 0xbfff, 0xc8d5, 0x21, 0 + .dw 0xda00, 0xc8d5, 0xdfff, 0xc8d5, 0x21, 0 + .dw 0xfa00, 0xc8d5, 0xffff, 0xc8d5, 0x21, 0 + .dw 0x1a00, 0xc8d6, 0x1fff, 0xc8d6, 0x21, 0 + .dw 0x3a00, 0xc8d6, 0x3fff, 0xc8d6, 0x21, 0 + .dw 0x5a00, 0xc8d6, 0x5fff, 0xc8d6, 0x21, 0 + .dw 0x7a00, 0xc8d6, 0x7fff, 0xc8d6, 0x21, 0 + .dw 0x9a00, 0xc8d6, 0x9fff, 0xc8d6, 0x21, 0 + .dw 0xba00, 0xc8d6, 0xbfff, 0xc8d6, 0x21, 0 + .dw 0xda00, 0xc8d6, 0xdfff, 0xc8d6, 0x21, 0 + .dw 0xfa00, 0xc8d6, 0xffff, 0xc8d6, 0x21, 0 + .dw 0x1a00, 0xc8d7, 0x1fff, 0xc8d7, 0x21, 0 + .dw 0x3a00, 0xc8d7, 0xffff, 0xc8ff, 0x21, 0 + .dw 0x1a00, 0xc900, 0x1fff, 0xc900, 0x21, 0 + .dw 0x3a00, 0xc900, 0x3fff, 0xc900, 0x21, 0 + .dw 0x5a00, 0xc900, 0x5fff, 0xc900, 0x21, 0 + .dw 0x7a00, 0xc900, 0x7fff, 0xc900, 0x21, 0 + .dw 0x9a00, 0xc900, 0x9fff, 0xc900, 0x21, 0 + .dw 0xba00, 0xc900, 0xbfff, 0xc900, 0x21, 0 + .dw 0xda00, 0xc900, 0xdfff, 0xc900, 0x21, 0 + .dw 0xfa00, 0xc900, 0xffff, 0xc900, 0x21, 0 + .dw 0x1a00, 0xc901, 0x1fff, 0xc901, 0x21, 0 + .dw 0x3a00, 0xc901, 0x3fff, 0xc901, 0x21, 0 + .dw 0x5a00, 0xc901, 0x5fff, 0xc901, 0x21, 0 + .dw 0x7a00, 0xc901, 0x7fff, 0xc901, 0x21, 0 + .dw 0x9a00, 0xc901, 0x9fff, 0xc901, 0x21, 0 + .dw 0xba00, 0xc901, 0xbfff, 0xc901, 0x21, 0 + .dw 0xda00, 0xc901, 0xdfff, 0xc901, 0x21, 0 + .dw 0xfa00, 0xc901, 0xffff, 0xc901, 0x21, 0 + .dw 0x1a00, 0xc902, 0x1fff, 0xc902, 0x21, 0 + .dw 0x3a00, 0xc902, 0x3fff, 0xc902, 0x21, 0 + .dw 0x5a00, 0xc902, 0x5fff, 0xc902, 0x21, 0 + .dw 0x7a00, 0xc902, 0x7fff, 0xc902, 0x21, 0 + .dw 0x9a00, 0xc902, 0x9fff, 0xc902, 0x21, 0 + .dw 0xba00, 0xc902, 0xbfff, 0xc902, 0x21, 0 + .dw 0xda00, 0xc902, 0xdfff, 0xc902, 0x21, 0 + .dw 0xfa00, 0xc902, 0xffff, 0xc902, 0x21, 0 + .dw 0x1a00, 0xc903, 0x1fff, 0xc903, 0x21, 0 + .dw 0x3a00, 0xc903, 0xffff, 0xc903, 0x21, 0 + .dw 0x1a00, 0xc904, 0x1fff, 0xc904, 0x21, 0 + .dw 0x3a00, 0xc904, 0x3fff, 0xc904, 0x21, 0 + .dw 0x5a00, 0xc904, 0x5fff, 0xc904, 0x21, 0 + .dw 0x7a00, 0xc904, 0x7fff, 0xc904, 0x21, 0 + .dw 0x9a00, 0xc904, 0x9fff, 0xc904, 0x21, 0 + .dw 0xba00, 0xc904, 0xbfff, 0xc904, 0x21, 0 + .dw 0xda00, 0xc904, 0xdfff, 0xc904, 0x21, 0 + .dw 0xfa00, 0xc904, 0xffff, 0xc904, 0x21, 0 + .dw 0x1a00, 0xc905, 0x1fff, 0xc905, 0x21, 0 + .dw 0x3a00, 0xc905, 0x3fff, 0xc905, 0x21, 0 + .dw 0x5a00, 0xc905, 0x5fff, 0xc905, 0x21, 0 + .dw 0x7a00, 0xc905, 0x7fff, 0xc905, 0x21, 0 + .dw 0x9a00, 0xc905, 0x9fff, 0xc905, 0x21, 0 + .dw 0xba00, 0xc905, 0xbfff, 0xc905, 0x21, 0 + .dw 0xda00, 0xc905, 0xdfff, 0xc905, 0x21, 0 + .dw 0xfa00, 0xc905, 0xffff, 0xc905, 0x21, 0 + .dw 0x1a00, 0xc906, 0x1fff, 0xc906, 0x21, 0 + .dw 0x3a00, 0xc906, 0x3fff, 0xc906, 0x21, 0 + .dw 0x5a00, 0xc906, 0x5fff, 0xc906, 0x21, 0 + .dw 0x7a00, 0xc906, 0x7fff, 0xc906, 0x21, 0 + .dw 0x9a00, 0xc906, 0x9fff, 0xc906, 0x21, 0 + .dw 0xba00, 0xc906, 0xbfff, 0xc906, 0x21, 0 + .dw 0xda00, 0xc906, 0xdfff, 0xc906, 0x21, 0 + .dw 0xfa00, 0xc906, 0xffff, 0xc906, 0x21, 0 + .dw 0x1a00, 0xc907, 0x1fff, 0xc907, 0x21, 0 + .dw 0x3a00, 0xc907, 0x1fff, 0xc908, 0x21, 0 + .dw 0x2040, 0xc908, 0x207f, 0xc908, 0x21, 0 + .dw 0x20c0, 0xc908, 0x20ff, 0xc908, 0x21, 0 + .dw 0x2140, 0xc908, 0x217f, 0xc908, 0x21, 0 + .dw 0x21c0, 0xc908, 0x21ff, 0xc908, 0x21, 0 + .dw 0x2240, 0xc908, 0x227f, 0xc908, 0x21, 0 + .dw 0x22c0, 0xc908, 0x22ff, 0xc908, 0x21, 0 + .dw 0x2340, 0xc908, 0x237f, 0xc908, 0x21, 0 + .dw 0x23c0, 0xc908, 0x23ff, 0xc908, 0x21, 0 + .dw 0x2440, 0xc908, 0x247f, 0xc908, 0x21, 0 + .dw 0x24c0, 0xc908, 0x24ff, 0xc908, 0x21, 0 + .dw 0x2540, 0xc908, 0x257f, 0xc908, 0x21, 0 + .dw 0x25c0, 0xc908, 0x25ff, 0xc908, 0x21, 0 + .dw 0x2640, 0xc908, 0x267f, 0xc908, 0x21, 0 + .dw 0x26c0, 0xc908, 0x26ff, 0xc908, 0x21, 0 + .dw 0x2740, 0xc908, 0x277f, 0xc908, 0x21, 0 + .dw 0x27c0, 0xc908, 0x27ff, 0xc908, 0x21, 0 + .dw 0x2840, 0xc908, 0x287f, 0xc908, 0x21, 0 + .dw 0x28c0, 0xc908, 0x28ff, 0xc908, 0x21, 0 + .dw 0x2940, 0xc908, 0x297f, 0xc908, 0x21, 0 + .dw 0x29c0, 0xc908, 0x29ff, 0xc908, 0x21, 0 + .dw 0x2a40, 0xc908, 0x2a7f, 0xc908, 0x21, 0 + .dw 0x2ac0, 0xc908, 0x2aff, 0xc908, 0x21, 0 + .dw 0x2b40, 0xc908, 0x2b7f, 0xc908, 0x21, 0 + .dw 0x2bc0, 0xc908, 0x2bff, 0xc908, 0x21, 0 + .dw 0x2c40, 0xc908, 0x2c7f, 0xc908, 0x21, 0 + .dw 0x2cc0, 0xc908, 0x2cff, 0xc908, 0x21, 0 + .dw 0x2d40, 0xc908, 0x2d7f, 0xc908, 0x21, 0 + .dw 0x2dc0, 0xc908, 0x2dff, 0xc908, 0x21, 0 + .dw 0x2e40, 0xc908, 0x2e7f, 0xc908, 0x21, 0 + .dw 0x2ec0, 0xc908, 0x2eff, 0xc908, 0x21, 0 + .dw 0x2f40, 0xc908, 0x2f7f, 0xc908, 0x21, 0 + .dw 0x2fc0, 0xc908, 0x2fff, 0xc908, 0x21, 0 + .dw 0x3040, 0xc908, 0x307f, 0xc908, 0x21, 0 + .dw 0x30c0, 0xc908, 0x30ff, 0xc908, 0x21, 0 + .dw 0x3140, 0xc908, 0x317f, 0xc908, 0x21, 0 + .dw 0x31c0, 0xc908, 0x31ff, 0xc908, 0x21, 0 + .dw 0x3240, 0xc908, 0x327f, 0xc908, 0x21, 0 + .dw 0x32c0, 0xc908, 0x32ff, 0xc908, 0x21, 0 + .dw 0x3340, 0xc908, 0x337f, 0xc908, 0x21, 0 + .dw 0x33c0, 0xc908, 0x33ff, 0xc908, 0x21, 0 + .dw 0x3440, 0xc908, 0x347f, 0xc908, 0x21, 0 + .dw 0x34c0, 0xc908, 0x34ff, 0xc908, 0x21, 0 + .dw 0x3540, 0xc908, 0x357f, 0xc908, 0x21, 0 + .dw 0x35c0, 0xc908, 0x35ff, 0xc908, 0x21, 0 + .dw 0x3640, 0xc908, 0x367f, 0xc908, 0x21, 0 + .dw 0x36c0, 0xc908, 0x36ff, 0xc908, 0x21, 0 + .dw 0x3740, 0xc908, 0x377f, 0xc908, 0x21, 0 + .dw 0x37c0, 0xc908, 0x37ff, 0xc908, 0x21, 0 + .dw 0x3840, 0xc908, 0x387f, 0xc908, 0x21, 0 + .dw 0x38c0, 0xc908, 0x38ff, 0xc908, 0x21, 0 + .dw 0x3940, 0xc908, 0x397f, 0xc908, 0x21, 0 + .dw 0x39c0, 0xc908, 0x5fff, 0xc908, 0x21, 0 + .dw 0x6040, 0xc908, 0x607f, 0xc908, 0x21, 0 + .dw 0x60c0, 0xc908, 0x60ff, 0xc908, 0x21, 0 + .dw 0x6140, 0xc908, 0x617f, 0xc908, 0x21, 0 + .dw 0x61c0, 0xc908, 0x61ff, 0xc908, 0x21, 0 + .dw 0x6240, 0xc908, 0x627f, 0xc908, 0x21, 0 + .dw 0x62c0, 0xc908, 0x62ff, 0xc908, 0x21, 0 + .dw 0x6340, 0xc908, 0x637f, 0xc908, 0x21, 0 + .dw 0x63c0, 0xc908, 0x63ff, 0xc908, 0x21, 0 + .dw 0x6440, 0xc908, 0x647f, 0xc908, 0x21, 0 + .dw 0x64c0, 0xc908, 0x64ff, 0xc908, 0x21, 0 + .dw 0x6540, 0xc908, 0x657f, 0xc908, 0x21, 0 + .dw 0x65c0, 0xc908, 0x65ff, 0xc908, 0x21, 0 + .dw 0x6640, 0xc908, 0x667f, 0xc908, 0x21, 0 + .dw 0x66c0, 0xc908, 0x66ff, 0xc908, 0x21, 0 + .dw 0x6740, 0xc908, 0x677f, 0xc908, 0x21, 0 + .dw 0x67c0, 0xc908, 0x67ff, 0xc908, 0x21, 0 + .dw 0x6840, 0xc908, 0x687f, 0xc908, 0x21, 0 + .dw 0x68c0, 0xc908, 0x68ff, 0xc908, 0x21, 0 + .dw 0x6940, 0xc908, 0x697f, 0xc908, 0x21, 0 + .dw 0x69c0, 0xc908, 0x69ff, 0xc908, 0x21, 0 + .dw 0x6a40, 0xc908, 0x6a7f, 0xc908, 0x21, 0 + .dw 0x6ac0, 0xc908, 0x6aff, 0xc908, 0x21, 0 + .dw 0x6b40, 0xc908, 0x6b7f, 0xc908, 0x21, 0 + .dw 0x6bc0, 0xc908, 0x6bff, 0xc908, 0x21, 0 + .dw 0x6c40, 0xc908, 0x6c7f, 0xc908, 0x21, 0 + .dw 0x6cc0, 0xc908, 0x6cff, 0xc908, 0x21, 0 + .dw 0x6d40, 0xc908, 0x6d7f, 0xc908, 0x21, 0 + .dw 0x6dc0, 0xc908, 0x6dff, 0xc908, 0x21, 0 + .dw 0x6e40, 0xc908, 0x6e7f, 0xc908, 0x21, 0 + .dw 0x6ec0, 0xc908, 0x6eff, 0xc908, 0x21, 0 + .dw 0x6f40, 0xc908, 0x6f7f, 0xc908, 0x21, 0 + .dw 0x6fc0, 0xc908, 0x6fff, 0xc908, 0x21, 0 + .dw 0x7040, 0xc908, 0x707f, 0xc908, 0x21, 0 + .dw 0x70c0, 0xc908, 0x70ff, 0xc908, 0x21, 0 + .dw 0x7140, 0xc908, 0x717f, 0xc908, 0x21, 0 + .dw 0x71c0, 0xc908, 0x71ff, 0xc908, 0x21, 0 + .dw 0x7240, 0xc908, 0x727f, 0xc908, 0x21, 0 + .dw 0x72c0, 0xc908, 0x72ff, 0xc908, 0x21, 0 + .dw 0x7340, 0xc908, 0x737f, 0xc908, 0x21, 0 + .dw 0x73c0, 0xc908, 0x73ff, 0xc908, 0x21, 0 + .dw 0x7440, 0xc908, 0x747f, 0xc908, 0x21, 0 + .dw 0x74c0, 0xc908, 0x74ff, 0xc908, 0x21, 0 + .dw 0x7540, 0xc908, 0x757f, 0xc908, 0x21, 0 + .dw 0x75c0, 0xc908, 0x75ff, 0xc908, 0x21, 0 + .dw 0x7640, 0xc908, 0x767f, 0xc908, 0x21, 0 + .dw 0x76c0, 0xc908, 0x76ff, 0xc908, 0x21, 0 + .dw 0x7740, 0xc908, 0x777f, 0xc908, 0x21, 0 + .dw 0x77c0, 0xc908, 0x77ff, 0xc908, 0x21, 0 + .dw 0x7840, 0xc908, 0x787f, 0xc908, 0x21, 0 + .dw 0x78c0, 0xc908, 0x78ff, 0xc908, 0x21, 0 + .dw 0x7940, 0xc908, 0x797f, 0xc908, 0x21, 0 + .dw 0x79c0, 0xc908, 0x9fff, 0xc908, 0x21, 0 + .dw 0xa040, 0xc908, 0xa07f, 0xc908, 0x21, 0 + .dw 0xa0c0, 0xc908, 0xa0ff, 0xc908, 0x21, 0 + .dw 0xa140, 0xc908, 0xa17f, 0xc908, 0x21, 0 + .dw 0xa1c0, 0xc908, 0xa1ff, 0xc908, 0x21, 0 + .dw 0xa240, 0xc908, 0xa27f, 0xc908, 0x21, 0 + .dw 0xa2c0, 0xc908, 0xa2ff, 0xc908, 0x21, 0 + .dw 0xa340, 0xc908, 0xa37f, 0xc908, 0x21, 0 + .dw 0xa3c0, 0xc908, 0xa3ff, 0xc908, 0x21, 0 + .dw 0xa440, 0xc908, 0xa47f, 0xc908, 0x21, 0 + .dw 0xa4c0, 0xc908, 0xa4ff, 0xc908, 0x21, 0 + .dw 0xa540, 0xc908, 0xa57f, 0xc908, 0x21, 0 + .dw 0xa5c0, 0xc908, 0xa5ff, 0xc908, 0x21, 0 + .dw 0xa640, 0xc908, 0xa67f, 0xc908, 0x21, 0 + .dw 0xa6c0, 0xc908, 0xa6ff, 0xc908, 0x21, 0 + .dw 0xa740, 0xc908, 0xa77f, 0xc908, 0x21, 0 + .dw 0xa7c0, 0xc908, 0xa7ff, 0xc908, 0x21, 0 + .dw 0xa840, 0xc908, 0xa87f, 0xc908, 0x21, 0 + .dw 0xa8c0, 0xc908, 0xa8ff, 0xc908, 0x21, 0 + .dw 0xa940, 0xc908, 0xa97f, 0xc908, 0x21, 0 + .dw 0xa9c0, 0xc908, 0xa9ff, 0xc908, 0x21, 0 + .dw 0xaa40, 0xc908, 0xaa7f, 0xc908, 0x21, 0 + .dw 0xaac0, 0xc908, 0xaaff, 0xc908, 0x21, 0 + .dw 0xab40, 0xc908, 0xab7f, 0xc908, 0x21, 0 + .dw 0xabc0, 0xc908, 0xabff, 0xc908, 0x21, 0 + .dw 0xac40, 0xc908, 0xac7f, 0xc908, 0x21, 0 + .dw 0xacc0, 0xc908, 0xacff, 0xc908, 0x21, 0 + .dw 0xad40, 0xc908, 0xad7f, 0xc908, 0x21, 0 + .dw 0xadc0, 0xc908, 0xadff, 0xc908, 0x21, 0 + .dw 0xae40, 0xc908, 0xae7f, 0xc908, 0x21, 0 + .dw 0xaec0, 0xc908, 0xaeff, 0xc908, 0x21, 0 + .dw 0xaf40, 0xc908, 0xaf7f, 0xc908, 0x21, 0 + .dw 0xafc0, 0xc908, 0xafff, 0xc908, 0x21, 0 + .dw 0xb040, 0xc908, 0xb07f, 0xc908, 0x21, 0 + .dw 0xb0c0, 0xc908, 0xb0ff, 0xc908, 0x21, 0 + .dw 0xb140, 0xc908, 0xb17f, 0xc908, 0x21, 0 + .dw 0xb1c0, 0xc908, 0xb1ff, 0xc908, 0x21, 0 + .dw 0xb240, 0xc908, 0xb27f, 0xc908, 0x21, 0 + .dw 0xb2c0, 0xc908, 0xb2ff, 0xc908, 0x21, 0 + .dw 0xb340, 0xc908, 0xb37f, 0xc908, 0x21, 0 + .dw 0xb3c0, 0xc908, 0xb3ff, 0xc908, 0x21, 0 + .dw 0xb440, 0xc908, 0xb47f, 0xc908, 0x21, 0 + .dw 0xb4c0, 0xc908, 0xb4ff, 0xc908, 0x21, 0 + .dw 0xb540, 0xc908, 0xb57f, 0xc908, 0x21, 0 + .dw 0xb5c0, 0xc908, 0xb5ff, 0xc908, 0x21, 0 + .dw 0xb640, 0xc908, 0xb67f, 0xc908, 0x21, 0 + .dw 0xb6c0, 0xc908, 0xb6ff, 0xc908, 0x21, 0 + .dw 0xb740, 0xc908, 0xb77f, 0xc908, 0x21, 0 + .dw 0xb7c0, 0xc908, 0xb7ff, 0xc908, 0x21, 0 + .dw 0xb840, 0xc908, 0xb87f, 0xc908, 0x21, 0 + .dw 0xb8c0, 0xc908, 0xb8ff, 0xc908, 0x21, 0 + .dw 0xb940, 0xc908, 0xb97f, 0xc908, 0x21, 0 + .dw 0xb9c0, 0xc908, 0xdfff, 0xc908, 0x21, 0 + .dw 0xe040, 0xc908, 0xe07f, 0xc908, 0x21, 0 + .dw 0xe0c0, 0xc908, 0xe0ff, 0xc908, 0x21, 0 + .dw 0xe140, 0xc908, 0xe17f, 0xc908, 0x21, 0 + .dw 0xe1c0, 0xc908, 0xe1ff, 0xc908, 0x21, 0 + .dw 0xe240, 0xc908, 0xe27f, 0xc908, 0x21, 0 + .dw 0xe2c0, 0xc908, 0xe2ff, 0xc908, 0x21, 0 + .dw 0xe340, 0xc908, 0xe37f, 0xc908, 0x21, 0 + .dw 0xe3c0, 0xc908, 0xe3ff, 0xc908, 0x21, 0 + .dw 0xe440, 0xc908, 0xe47f, 0xc908, 0x21, 0 + .dw 0xe4c0, 0xc908, 0xe4ff, 0xc908, 0x21, 0 + .dw 0xe540, 0xc908, 0xe57f, 0xc908, 0x21, 0 + .dw 0xe5c0, 0xc908, 0xe5ff, 0xc908, 0x21, 0 + .dw 0xe640, 0xc908, 0xe67f, 0xc908, 0x21, 0 + .dw 0xe6c0, 0xc908, 0xe6ff, 0xc908, 0x21, 0 + .dw 0xe740, 0xc908, 0xe77f, 0xc908, 0x21, 0 + .dw 0xe7c0, 0xc908, 0xe7ff, 0xc908, 0x21, 0 + .dw 0xe840, 0xc908, 0xe87f, 0xc908, 0x21, 0 + .dw 0xe8c0, 0xc908, 0xe8ff, 0xc908, 0x21, 0 + .dw 0xe940, 0xc908, 0xe97f, 0xc908, 0x21, 0 + .dw 0xe9c0, 0xc908, 0xe9ff, 0xc908, 0x21, 0 + .dw 0xea40, 0xc908, 0xea7f, 0xc908, 0x21, 0 + .dw 0xeac0, 0xc908, 0xeaff, 0xc908, 0x21, 0 + .dw 0xeb40, 0xc908, 0xeb7f, 0xc908, 0x21, 0 + .dw 0xebc0, 0xc908, 0xebff, 0xc908, 0x21, 0 + .dw 0xec40, 0xc908, 0xec7f, 0xc908, 0x21, 0 + .dw 0xecc0, 0xc908, 0xecff, 0xc908, 0x21, 0 + .dw 0xed40, 0xc908, 0xed7f, 0xc908, 0x21, 0 + .dw 0xedc0, 0xc908, 0xedff, 0xc908, 0x21, 0 + .dw 0xee40, 0xc908, 0xee7f, 0xc908, 0x21, 0 + .dw 0xeec0, 0xc908, 0xeeff, 0xc908, 0x21, 0 + .dw 0xef40, 0xc908, 0xef7f, 0xc908, 0x21, 0 + .dw 0xefc0, 0xc908, 0xefff, 0xc908, 0x21, 0 + .dw 0xf040, 0xc908, 0xf07f, 0xc908, 0x21, 0 + .dw 0xf0c0, 0xc908, 0xf0ff, 0xc908, 0x21, 0 + .dw 0xf140, 0xc908, 0xf17f, 0xc908, 0x21, 0 + .dw 0xf1c0, 0xc908, 0xf1ff, 0xc908, 0x21, 0 + .dw 0xf240, 0xc908, 0xf27f, 0xc908, 0x21, 0 + .dw 0xf2c0, 0xc908, 0xf2ff, 0xc908, 0x21, 0 + .dw 0xf340, 0xc908, 0xf37f, 0xc908, 0x21, 0 + .dw 0xf3c0, 0xc908, 0xf3ff, 0xc908, 0x21, 0 + .dw 0xf440, 0xc908, 0xf47f, 0xc908, 0x21, 0 + .dw 0xf4c0, 0xc908, 0xf4ff, 0xc908, 0x21, 0 + .dw 0xf540, 0xc908, 0xf57f, 0xc908, 0x21, 0 + .dw 0xf5c0, 0xc908, 0xf5ff, 0xc908, 0x21, 0 + .dw 0xf640, 0xc908, 0xf67f, 0xc908, 0x21, 0 + .dw 0xf6c0, 0xc908, 0xf6ff, 0xc908, 0x21, 0 + .dw 0xf740, 0xc908, 0xf77f, 0xc908, 0x21, 0 + .dw 0xf7c0, 0xc908, 0xf7ff, 0xc908, 0x21, 0 + .dw 0xf840, 0xc908, 0xf87f, 0xc908, 0x21, 0 + .dw 0xf8c0, 0xc908, 0xf8ff, 0xc908, 0x21, 0 + .dw 0xf940, 0xc908, 0xf97f, 0xc908, 0x21, 0 + .dw 0xf9c0, 0xc908, 0x1fff, 0xc909, 0x21, 0 + .dw 0x2040, 0xc909, 0x207f, 0xc909, 0x21, 0 + .dw 0x20c0, 0xc909, 0x20ff, 0xc909, 0x21, 0 + .dw 0x2140, 0xc909, 0x217f, 0xc909, 0x21, 0 + .dw 0x21c0, 0xc909, 0x21ff, 0xc909, 0x21, 0 + .dw 0x2240, 0xc909, 0x227f, 0xc909, 0x21, 0 + .dw 0x22c0, 0xc909, 0x22ff, 0xc909, 0x21, 0 + .dw 0x2340, 0xc909, 0x237f, 0xc909, 0x21, 0 + .dw 0x23c0, 0xc909, 0x23ff, 0xc909, 0x21, 0 + .dw 0x2440, 0xc909, 0x247f, 0xc909, 0x21, 0 + .dw 0x24c0, 0xc909, 0x24ff, 0xc909, 0x21, 0 + .dw 0x2540, 0xc909, 0x257f, 0xc909, 0x21, 0 + .dw 0x25c0, 0xc909, 0x25ff, 0xc909, 0x21, 0 + .dw 0x2640, 0xc909, 0x267f, 0xc909, 0x21, 0 + .dw 0x26c0, 0xc909, 0x26ff, 0xc909, 0x21, 0 + .dw 0x2740, 0xc909, 0x277f, 0xc909, 0x21, 0 + .dw 0x27c0, 0xc909, 0x27ff, 0xc909, 0x21, 0 + .dw 0x2840, 0xc909, 0x287f, 0xc909, 0x21, 0 + .dw 0x28c0, 0xc909, 0x28ff, 0xc909, 0x21, 0 + .dw 0x2940, 0xc909, 0x297f, 0xc909, 0x21, 0 + .dw 0x29c0, 0xc909, 0x29ff, 0xc909, 0x21, 0 + .dw 0x2a40, 0xc909, 0x2a7f, 0xc909, 0x21, 0 + .dw 0x2ac0, 0xc909, 0x2aff, 0xc909, 0x21, 0 + .dw 0x2b40, 0xc909, 0x2b7f, 0xc909, 0x21, 0 + .dw 0x2bc0, 0xc909, 0x2bff, 0xc909, 0x21, 0 + .dw 0x2c40, 0xc909, 0x2c7f, 0xc909, 0x21, 0 + .dw 0x2cc0, 0xc909, 0x2cff, 0xc909, 0x21, 0 + .dw 0x2d40, 0xc909, 0x2d7f, 0xc909, 0x21, 0 + .dw 0x2dc0, 0xc909, 0x2dff, 0xc909, 0x21, 0 + .dw 0x2e40, 0xc909, 0x2e7f, 0xc909, 0x21, 0 + .dw 0x2ec0, 0xc909, 0x2eff, 0xc909, 0x21, 0 + .dw 0x2f40, 0xc909, 0x2f7f, 0xc909, 0x21, 0 + .dw 0x2fc0, 0xc909, 0x2fff, 0xc909, 0x21, 0 + .dw 0x3040, 0xc909, 0x307f, 0xc909, 0x21, 0 + .dw 0x30c0, 0xc909, 0x30ff, 0xc909, 0x21, 0 + .dw 0x3140, 0xc909, 0x317f, 0xc909, 0x21, 0 + .dw 0x31c0, 0xc909, 0x31ff, 0xc909, 0x21, 0 + .dw 0x3240, 0xc909, 0x327f, 0xc909, 0x21, 0 + .dw 0x32c0, 0xc909, 0x32ff, 0xc909, 0x21, 0 + .dw 0x3340, 0xc909, 0x337f, 0xc909, 0x21, 0 + .dw 0x33c0, 0xc909, 0x33ff, 0xc909, 0x21, 0 + .dw 0x3440, 0xc909, 0x347f, 0xc909, 0x21, 0 + .dw 0x34c0, 0xc909, 0x34ff, 0xc909, 0x21, 0 + .dw 0x3540, 0xc909, 0x357f, 0xc909, 0x21, 0 + .dw 0x35c0, 0xc909, 0x35ff, 0xc909, 0x21, 0 + .dw 0x3640, 0xc909, 0x367f, 0xc909, 0x21, 0 + .dw 0x36c0, 0xc909, 0x36ff, 0xc909, 0x21, 0 + .dw 0x3740, 0xc909, 0x377f, 0xc909, 0x21, 0 + .dw 0x37c0, 0xc909, 0x37ff, 0xc909, 0x21, 0 + .dw 0x3840, 0xc909, 0x387f, 0xc909, 0x21, 0 + .dw 0x38c0, 0xc909, 0x38ff, 0xc909, 0x21, 0 + .dw 0x3940, 0xc909, 0x397f, 0xc909, 0x21, 0 + .dw 0x39c0, 0xc909, 0x5fff, 0xc909, 0x21, 0 + .dw 0x6040, 0xc909, 0x607f, 0xc909, 0x21, 0 + .dw 0x60c0, 0xc909, 0x60ff, 0xc909, 0x21, 0 + .dw 0x6140, 0xc909, 0x617f, 0xc909, 0x21, 0 + .dw 0x61c0, 0xc909, 0x61ff, 0xc909, 0x21, 0 + .dw 0x6240, 0xc909, 0x627f, 0xc909, 0x21, 0 + .dw 0x62c0, 0xc909, 0x62ff, 0xc909, 0x21, 0 + .dw 0x6340, 0xc909, 0x637f, 0xc909, 0x21, 0 + .dw 0x63c0, 0xc909, 0x63ff, 0xc909, 0x21, 0 + .dw 0x6440, 0xc909, 0x647f, 0xc909, 0x21, 0 + .dw 0x64c0, 0xc909, 0x64ff, 0xc909, 0x21, 0 + .dw 0x6540, 0xc909, 0x657f, 0xc909, 0x21, 0 + .dw 0x65c0, 0xc909, 0x65ff, 0xc909, 0x21, 0 + .dw 0x6640, 0xc909, 0x667f, 0xc909, 0x21, 0 + .dw 0x66c0, 0xc909, 0x66ff, 0xc909, 0x21, 0 + .dw 0x6740, 0xc909, 0x677f, 0xc909, 0x21, 0 + .dw 0x67c0, 0xc909, 0x67ff, 0xc909, 0x21, 0 + .dw 0x6840, 0xc909, 0x687f, 0xc909, 0x21, 0 + .dw 0x68c0, 0xc909, 0x68ff, 0xc909, 0x21, 0 + .dw 0x6940, 0xc909, 0x697f, 0xc909, 0x21, 0 + .dw 0x69c0, 0xc909, 0x69ff, 0xc909, 0x21, 0 + .dw 0x6a40, 0xc909, 0x6a7f, 0xc909, 0x21, 0 + .dw 0x6ac0, 0xc909, 0x6aff, 0xc909, 0x21, 0 + .dw 0x6b40, 0xc909, 0x6b7f, 0xc909, 0x21, 0 + .dw 0x6bc0, 0xc909, 0x6bff, 0xc909, 0x21, 0 + .dw 0x6c40, 0xc909, 0x6c7f, 0xc909, 0x21, 0 + .dw 0x6cc0, 0xc909, 0x6cff, 0xc909, 0x21, 0 + .dw 0x6d40, 0xc909, 0x6d7f, 0xc909, 0x21, 0 + .dw 0x6dc0, 0xc909, 0x6dff, 0xc909, 0x21, 0 + .dw 0x6e40, 0xc909, 0x6e7f, 0xc909, 0x21, 0 + .dw 0x6ec0, 0xc909, 0x6eff, 0xc909, 0x21, 0 + .dw 0x6f40, 0xc909, 0x6f7f, 0xc909, 0x21, 0 + .dw 0x6fc0, 0xc909, 0x6fff, 0xc909, 0x21, 0 + .dw 0x7040, 0xc909, 0x707f, 0xc909, 0x21, 0 + .dw 0x70c0, 0xc909, 0x70ff, 0xc909, 0x21, 0 + .dw 0x7140, 0xc909, 0x717f, 0xc909, 0x21, 0 + .dw 0x71c0, 0xc909, 0x71ff, 0xc909, 0x21, 0 + .dw 0x7240, 0xc909, 0x727f, 0xc909, 0x21, 0 + .dw 0x72c0, 0xc909, 0x72ff, 0xc909, 0x21, 0 + .dw 0x7340, 0xc909, 0x737f, 0xc909, 0x21, 0 + .dw 0x73c0, 0xc909, 0x73ff, 0xc909, 0x21, 0 + .dw 0x7440, 0xc909, 0x747f, 0xc909, 0x21, 0 + .dw 0x74c0, 0xc909, 0x74ff, 0xc909, 0x21, 0 + .dw 0x7540, 0xc909, 0x757f, 0xc909, 0x21, 0 + .dw 0x75c0, 0xc909, 0x75ff, 0xc909, 0x21, 0 + .dw 0x7640, 0xc909, 0x767f, 0xc909, 0x21, 0 + .dw 0x76c0, 0xc909, 0x76ff, 0xc909, 0x21, 0 + .dw 0x7740, 0xc909, 0x777f, 0xc909, 0x21, 0 + .dw 0x77c0, 0xc909, 0x77ff, 0xc909, 0x21, 0 + .dw 0x7840, 0xc909, 0x787f, 0xc909, 0x21, 0 + .dw 0x78c0, 0xc909, 0x78ff, 0xc909, 0x21, 0 + .dw 0x7940, 0xc909, 0x797f, 0xc909, 0x21, 0 + .dw 0x79c0, 0xc909, 0x9fff, 0xc909, 0x21, 0 + .dw 0xa040, 0xc909, 0xa07f, 0xc909, 0x21, 0 + .dw 0xa0c0, 0xc909, 0xa0ff, 0xc909, 0x21, 0 + .dw 0xa140, 0xc909, 0xa17f, 0xc909, 0x21, 0 + .dw 0xa1c0, 0xc909, 0xa1ff, 0xc909, 0x21, 0 + .dw 0xa240, 0xc909, 0xa27f, 0xc909, 0x21, 0 + .dw 0xa2c0, 0xc909, 0xa2ff, 0xc909, 0x21, 0 + .dw 0xa340, 0xc909, 0xa37f, 0xc909, 0x21, 0 + .dw 0xa3c0, 0xc909, 0xa3ff, 0xc909, 0x21, 0 + .dw 0xa440, 0xc909, 0xa47f, 0xc909, 0x21, 0 + .dw 0xa4c0, 0xc909, 0xa4ff, 0xc909, 0x21, 0 + .dw 0xa540, 0xc909, 0xa57f, 0xc909, 0x21, 0 + .dw 0xa5c0, 0xc909, 0xa5ff, 0xc909, 0x21, 0 + .dw 0xa640, 0xc909, 0xa67f, 0xc909, 0x21, 0 + .dw 0xa6c0, 0xc909, 0xa6ff, 0xc909, 0x21, 0 + .dw 0xa740, 0xc909, 0xa77f, 0xc909, 0x21, 0 + .dw 0xa7c0, 0xc909, 0xa7ff, 0xc909, 0x21, 0 + .dw 0xa840, 0xc909, 0xa87f, 0xc909, 0x21, 0 + .dw 0xa8c0, 0xc909, 0xa8ff, 0xc909, 0x21, 0 + .dw 0xa940, 0xc909, 0xa97f, 0xc909, 0x21, 0 + .dw 0xa9c0, 0xc909, 0xa9ff, 0xc909, 0x21, 0 + .dw 0xaa40, 0xc909, 0xaa7f, 0xc909, 0x21, 0 + .dw 0xaac0, 0xc909, 0xaaff, 0xc909, 0x21, 0 + .dw 0xab40, 0xc909, 0xab7f, 0xc909, 0x21, 0 + .dw 0xabc0, 0xc909, 0xabff, 0xc909, 0x21, 0 + .dw 0xac40, 0xc909, 0xac7f, 0xc909, 0x21, 0 + .dw 0xacc0, 0xc909, 0xacff, 0xc909, 0x21, 0 + .dw 0xad40, 0xc909, 0xad7f, 0xc909, 0x21, 0 + .dw 0xadc0, 0xc909, 0xadff, 0xc909, 0x21, 0 + .dw 0xae40, 0xc909, 0xae7f, 0xc909, 0x21, 0 + .dw 0xaec0, 0xc909, 0xaeff, 0xc909, 0x21, 0 + .dw 0xaf40, 0xc909, 0xaf7f, 0xc909, 0x21, 0 + .dw 0xafc0, 0xc909, 0xafff, 0xc909, 0x21, 0 + .dw 0xb040, 0xc909, 0xb07f, 0xc909, 0x21, 0 + .dw 0xb0c0, 0xc909, 0xb0ff, 0xc909, 0x21, 0 + .dw 0xb140, 0xc909, 0xb17f, 0xc909, 0x21, 0 + .dw 0xb1c0, 0xc909, 0xb1ff, 0xc909, 0x21, 0 + .dw 0xb240, 0xc909, 0xb27f, 0xc909, 0x21, 0 + .dw 0xb2c0, 0xc909, 0xb2ff, 0xc909, 0x21, 0 + .dw 0xb340, 0xc909, 0xb37f, 0xc909, 0x21, 0 + .dw 0xb3c0, 0xc909, 0xb3ff, 0xc909, 0x21, 0 + .dw 0xb440, 0xc909, 0xb47f, 0xc909, 0x21, 0 + .dw 0xb4c0, 0xc909, 0xb4ff, 0xc909, 0x21, 0 + .dw 0xb540, 0xc909, 0xb57f, 0xc909, 0x21, 0 + .dw 0xb5c0, 0xc909, 0xb5ff, 0xc909, 0x21, 0 + .dw 0xb640, 0xc909, 0xb67f, 0xc909, 0x21, 0 + .dw 0xb6c0, 0xc909, 0xb6ff, 0xc909, 0x21, 0 + .dw 0xb740, 0xc909, 0xb77f, 0xc909, 0x21, 0 + .dw 0xb7c0, 0xc909, 0xb7ff, 0xc909, 0x21, 0 + .dw 0xb840, 0xc909, 0xb87f, 0xc909, 0x21, 0 + .dw 0xb8c0, 0xc909, 0xb8ff, 0xc909, 0x21, 0 + .dw 0xb940, 0xc909, 0xb97f, 0xc909, 0x21, 0 + .dw 0xb9c0, 0xc909, 0xdfff, 0xc909, 0x21, 0 + .dw 0xe040, 0xc909, 0xe07f, 0xc909, 0x21, 0 + .dw 0xe0c0, 0xc909, 0xe0ff, 0xc909, 0x21, 0 + .dw 0xe140, 0xc909, 0xe17f, 0xc909, 0x21, 0 + .dw 0xe1c0, 0xc909, 0xe1ff, 0xc909, 0x21, 0 + .dw 0xe240, 0xc909, 0xe27f, 0xc909, 0x21, 0 + .dw 0xe2c0, 0xc909, 0xe2ff, 0xc909, 0x21, 0 + .dw 0xe340, 0xc909, 0xe37f, 0xc909, 0x21, 0 + .dw 0xe3c0, 0xc909, 0xe3ff, 0xc909, 0x21, 0 + .dw 0xe440, 0xc909, 0xe47f, 0xc909, 0x21, 0 + .dw 0xe4c0, 0xc909, 0xe4ff, 0xc909, 0x21, 0 + .dw 0xe540, 0xc909, 0xe57f, 0xc909, 0x21, 0 + .dw 0xe5c0, 0xc909, 0xe5ff, 0xc909, 0x21, 0 + .dw 0xe640, 0xc909, 0xe67f, 0xc909, 0x21, 0 + .dw 0xe6c0, 0xc909, 0xe6ff, 0xc909, 0x21, 0 + .dw 0xe740, 0xc909, 0xe77f, 0xc909, 0x21, 0 + .dw 0xe7c0, 0xc909, 0xe7ff, 0xc909, 0x21, 0 + .dw 0xe840, 0xc909, 0xe87f, 0xc909, 0x21, 0 + .dw 0xe8c0, 0xc909, 0xe8ff, 0xc909, 0x21, 0 + .dw 0xe940, 0xc909, 0xe97f, 0xc909, 0x21, 0 + .dw 0xe9c0, 0xc909, 0xe9ff, 0xc909, 0x21, 0 + .dw 0xea40, 0xc909, 0xea7f, 0xc909, 0x21, 0 + .dw 0xeac0, 0xc909, 0xeaff, 0xc909, 0x21, 0 + .dw 0xeb40, 0xc909, 0xeb7f, 0xc909, 0x21, 0 + .dw 0xebc0, 0xc909, 0xebff, 0xc909, 0x21, 0 + .dw 0xec40, 0xc909, 0xec7f, 0xc909, 0x21, 0 + .dw 0xecc0, 0xc909, 0xecff, 0xc909, 0x21, 0 + .dw 0xed40, 0xc909, 0xed7f, 0xc909, 0x21, 0 + .dw 0xedc0, 0xc909, 0xedff, 0xc909, 0x21, 0 + .dw 0xee40, 0xc909, 0xee7f, 0xc909, 0x21, 0 + .dw 0xeec0, 0xc909, 0xeeff, 0xc909, 0x21, 0 + .dw 0xef40, 0xc909, 0xef7f, 0xc909, 0x21, 0 + .dw 0xefc0, 0xc909, 0xefff, 0xc909, 0x21, 0 + .dw 0xf040, 0xc909, 0xf07f, 0xc909, 0x21, 0 + .dw 0xf0c0, 0xc909, 0xf0ff, 0xc909, 0x21, 0 + .dw 0xf140, 0xc909, 0xf17f, 0xc909, 0x21, 0 + .dw 0xf1c0, 0xc909, 0xf1ff, 0xc909, 0x21, 0 + .dw 0xf240, 0xc909, 0xf27f, 0xc909, 0x21, 0 + .dw 0xf2c0, 0xc909, 0xf2ff, 0xc909, 0x21, 0 + .dw 0xf340, 0xc909, 0xf37f, 0xc909, 0x21, 0 + .dw 0xf3c0, 0xc909, 0xf3ff, 0xc909, 0x21, 0 + .dw 0xf440, 0xc909, 0xf47f, 0xc909, 0x21, 0 + .dw 0xf4c0, 0xc909, 0xf4ff, 0xc909, 0x21, 0 + .dw 0xf540, 0xc909, 0xf57f, 0xc909, 0x21, 0 + .dw 0xf5c0, 0xc909, 0xf5ff, 0xc909, 0x21, 0 + .dw 0xf640, 0xc909, 0xf67f, 0xc909, 0x21, 0 + .dw 0xf6c0, 0xc909, 0xf6ff, 0xc909, 0x21, 0 + .dw 0xf740, 0xc909, 0xf77f, 0xc909, 0x21, 0 + .dw 0xf7c0, 0xc909, 0xf7ff, 0xc909, 0x21, 0 + .dw 0xf840, 0xc909, 0xf87f, 0xc909, 0x21, 0 + .dw 0xf8c0, 0xc909, 0xf8ff, 0xc909, 0x21, 0 + .dw 0xf940, 0xc909, 0xf97f, 0xc909, 0x21, 0 + .dw 0xf9c0, 0xc909, 0x1fff, 0xc90a, 0x21, 0 + .dw 0x2040, 0xc90a, 0x207f, 0xc90a, 0x21, 0 + .dw 0x20c0, 0xc90a, 0x20ff, 0xc90a, 0x21, 0 + .dw 0x2140, 0xc90a, 0x217f, 0xc90a, 0x21, 0 + .dw 0x21c0, 0xc90a, 0x21ff, 0xc90a, 0x21, 0 + .dw 0x2240, 0xc90a, 0x227f, 0xc90a, 0x21, 0 + .dw 0x22c0, 0xc90a, 0x22ff, 0xc90a, 0x21, 0 + .dw 0x2340, 0xc90a, 0x237f, 0xc90a, 0x21, 0 + .dw 0x23c0, 0xc90a, 0x23ff, 0xc90a, 0x21, 0 + .dw 0x2440, 0xc90a, 0x247f, 0xc90a, 0x21, 0 + .dw 0x24c0, 0xc90a, 0x24ff, 0xc90a, 0x21, 0 + .dw 0x2540, 0xc90a, 0x257f, 0xc90a, 0x21, 0 + .dw 0x25c0, 0xc90a, 0x25ff, 0xc90a, 0x21, 0 + .dw 0x2640, 0xc90a, 0x267f, 0xc90a, 0x21, 0 + .dw 0x26c0, 0xc90a, 0x26ff, 0xc90a, 0x21, 0 + .dw 0x2740, 0xc90a, 0x277f, 0xc90a, 0x21, 0 + .dw 0x27c0, 0xc90a, 0x27ff, 0xc90a, 0x21, 0 + .dw 0x2840, 0xc90a, 0x287f, 0xc90a, 0x21, 0 + .dw 0x28c0, 0xc90a, 0x28ff, 0xc90a, 0x21, 0 + .dw 0x2940, 0xc90a, 0x297f, 0xc90a, 0x21, 0 + .dw 0x29c0, 0xc90a, 0x29ff, 0xc90a, 0x21, 0 + .dw 0x2a40, 0xc90a, 0x2a7f, 0xc90a, 0x21, 0 + .dw 0x2ac0, 0xc90a, 0x2aff, 0xc90a, 0x21, 0 + .dw 0x2b40, 0xc90a, 0x2b7f, 0xc90a, 0x21, 0 + .dw 0x2bc0, 0xc90a, 0x2bff, 0xc90a, 0x21, 0 + .dw 0x2c40, 0xc90a, 0x2c7f, 0xc90a, 0x21, 0 + .dw 0x2cc0, 0xc90a, 0x2cff, 0xc90a, 0x21, 0 + .dw 0x2d40, 0xc90a, 0x2d7f, 0xc90a, 0x21, 0 + .dw 0x2dc0, 0xc90a, 0x2dff, 0xc90a, 0x21, 0 + .dw 0x2e40, 0xc90a, 0x2e7f, 0xc90a, 0x21, 0 + .dw 0x2ec0, 0xc90a, 0x2eff, 0xc90a, 0x21, 0 + .dw 0x2f40, 0xc90a, 0x2f7f, 0xc90a, 0x21, 0 + .dw 0x2fc0, 0xc90a, 0x2fff, 0xc90a, 0x21, 0 + .dw 0x3040, 0xc90a, 0x307f, 0xc90a, 0x21, 0 + .dw 0x30c0, 0xc90a, 0x30ff, 0xc90a, 0x21, 0 + .dw 0x3140, 0xc90a, 0x317f, 0xc90a, 0x21, 0 + .dw 0x31c0, 0xc90a, 0x31ff, 0xc90a, 0x21, 0 + .dw 0x3240, 0xc90a, 0x327f, 0xc90a, 0x21, 0 + .dw 0x32c0, 0xc90a, 0x32ff, 0xc90a, 0x21, 0 + .dw 0x3340, 0xc90a, 0x337f, 0xc90a, 0x21, 0 + .dw 0x33c0, 0xc90a, 0x33ff, 0xc90a, 0x21, 0 + .dw 0x3440, 0xc90a, 0x347f, 0xc90a, 0x21, 0 + .dw 0x34c0, 0xc90a, 0x34ff, 0xc90a, 0x21, 0 + .dw 0x3540, 0xc90a, 0x357f, 0xc90a, 0x21, 0 + .dw 0x35c0, 0xc90a, 0x35ff, 0xc90a, 0x21, 0 + .dw 0x3640, 0xc90a, 0x367f, 0xc90a, 0x21, 0 + .dw 0x36c0, 0xc90a, 0x36ff, 0xc90a, 0x21, 0 + .dw 0x3740, 0xc90a, 0x377f, 0xc90a, 0x21, 0 + .dw 0x37c0, 0xc90a, 0x37ff, 0xc90a, 0x21, 0 + .dw 0x3840, 0xc90a, 0x387f, 0xc90a, 0x21, 0 + .dw 0x38c0, 0xc90a, 0x38ff, 0xc90a, 0x21, 0 + .dw 0x3940, 0xc90a, 0x397f, 0xc90a, 0x21, 0 + .dw 0x39c0, 0xc90a, 0x5fff, 0xc90a, 0x21, 0 + .dw 0x6040, 0xc90a, 0x607f, 0xc90a, 0x21, 0 + .dw 0x60c0, 0xc90a, 0x60ff, 0xc90a, 0x21, 0 + .dw 0x6140, 0xc90a, 0x617f, 0xc90a, 0x21, 0 + .dw 0x61c0, 0xc90a, 0x61ff, 0xc90a, 0x21, 0 + .dw 0x6240, 0xc90a, 0x627f, 0xc90a, 0x21, 0 + .dw 0x62c0, 0xc90a, 0x62ff, 0xc90a, 0x21, 0 + .dw 0x6340, 0xc90a, 0x637f, 0xc90a, 0x21, 0 + .dw 0x63c0, 0xc90a, 0x63ff, 0xc90a, 0x21, 0 + .dw 0x6440, 0xc90a, 0x647f, 0xc90a, 0x21, 0 + .dw 0x64c0, 0xc90a, 0x64ff, 0xc90a, 0x21, 0 + .dw 0x6540, 0xc90a, 0x657f, 0xc90a, 0x21, 0 + .dw 0x65c0, 0xc90a, 0x65ff, 0xc90a, 0x21, 0 + .dw 0x6640, 0xc90a, 0x667f, 0xc90a, 0x21, 0 + .dw 0x66c0, 0xc90a, 0x66ff, 0xc90a, 0x21, 0 + .dw 0x6740, 0xc90a, 0x677f, 0xc90a, 0x21, 0 + .dw 0x67c0, 0xc90a, 0x67ff, 0xc90a, 0x21, 0 + .dw 0x6840, 0xc90a, 0x687f, 0xc90a, 0x21, 0 + .dw 0x68c0, 0xc90a, 0x68ff, 0xc90a, 0x21, 0 + .dw 0x6940, 0xc90a, 0x697f, 0xc90a, 0x21, 0 + .dw 0x69c0, 0xc90a, 0x69ff, 0xc90a, 0x21, 0 + .dw 0x6a40, 0xc90a, 0x6a7f, 0xc90a, 0x21, 0 + .dw 0x6ac0, 0xc90a, 0x6aff, 0xc90a, 0x21, 0 + .dw 0x6b40, 0xc90a, 0x6b7f, 0xc90a, 0x21, 0 + .dw 0x6bc0, 0xc90a, 0x6bff, 0xc90a, 0x21, 0 + .dw 0x6c40, 0xc90a, 0x6c7f, 0xc90a, 0x21, 0 + .dw 0x6cc0, 0xc90a, 0x6cff, 0xc90a, 0x21, 0 + .dw 0x6d40, 0xc90a, 0x6d7f, 0xc90a, 0x21, 0 + .dw 0x6dc0, 0xc90a, 0x6dff, 0xc90a, 0x21, 0 + .dw 0x6e40, 0xc90a, 0x6e7f, 0xc90a, 0x21, 0 + .dw 0x6ec0, 0xc90a, 0x6eff, 0xc90a, 0x21, 0 + .dw 0x6f40, 0xc90a, 0x6f7f, 0xc90a, 0x21, 0 + .dw 0x6fc0, 0xc90a, 0x6fff, 0xc90a, 0x21, 0 + .dw 0x7040, 0xc90a, 0x707f, 0xc90a, 0x21, 0 + .dw 0x70c0, 0xc90a, 0x70ff, 0xc90a, 0x21, 0 + .dw 0x7140, 0xc90a, 0x717f, 0xc90a, 0x21, 0 + .dw 0x71c0, 0xc90a, 0x71ff, 0xc90a, 0x21, 0 + .dw 0x7240, 0xc90a, 0x727f, 0xc90a, 0x21, 0 + .dw 0x72c0, 0xc90a, 0x72ff, 0xc90a, 0x21, 0 + .dw 0x7340, 0xc90a, 0x737f, 0xc90a, 0x21, 0 + .dw 0x73c0, 0xc90a, 0x73ff, 0xc90a, 0x21, 0 + .dw 0x7440, 0xc90a, 0x747f, 0xc90a, 0x21, 0 + .dw 0x74c0, 0xc90a, 0x74ff, 0xc90a, 0x21, 0 + .dw 0x7540, 0xc90a, 0x757f, 0xc90a, 0x21, 0 + .dw 0x75c0, 0xc90a, 0x75ff, 0xc90a, 0x21, 0 + .dw 0x7640, 0xc90a, 0x767f, 0xc90a, 0x21, 0 + .dw 0x76c0, 0xc90a, 0x76ff, 0xc90a, 0x21, 0 + .dw 0x7740, 0xc90a, 0x777f, 0xc90a, 0x21, 0 + .dw 0x77c0, 0xc90a, 0x77ff, 0xc90a, 0x21, 0 + .dw 0x7840, 0xc90a, 0x787f, 0xc90a, 0x21, 0 + .dw 0x78c0, 0xc90a, 0x78ff, 0xc90a, 0x21, 0 + .dw 0x7940, 0xc90a, 0x797f, 0xc90a, 0x21, 0 + .dw 0x79c0, 0xc90a, 0x9fff, 0xc90a, 0x21, 0 + .dw 0xa040, 0xc90a, 0xa07f, 0xc90a, 0x21, 0 + .dw 0xa0c0, 0xc90a, 0xa0ff, 0xc90a, 0x21, 0 + .dw 0xa140, 0xc90a, 0xa17f, 0xc90a, 0x21, 0 + .dw 0xa1c0, 0xc90a, 0xa1ff, 0xc90a, 0x21, 0 + .dw 0xa240, 0xc90a, 0xa27f, 0xc90a, 0x21, 0 + .dw 0xa2c0, 0xc90a, 0xa2ff, 0xc90a, 0x21, 0 + .dw 0xa340, 0xc90a, 0xa37f, 0xc90a, 0x21, 0 + .dw 0xa3c0, 0xc90a, 0xa3ff, 0xc90a, 0x21, 0 + .dw 0xa440, 0xc90a, 0xa47f, 0xc90a, 0x21, 0 + .dw 0xa4c0, 0xc90a, 0xa4ff, 0xc90a, 0x21, 0 + .dw 0xa540, 0xc90a, 0xa57f, 0xc90a, 0x21, 0 + .dw 0xa5c0, 0xc90a, 0xa5ff, 0xc90a, 0x21, 0 + .dw 0xa640, 0xc90a, 0xa67f, 0xc90a, 0x21, 0 + .dw 0xa6c0, 0xc90a, 0xa6ff, 0xc90a, 0x21, 0 + .dw 0xa740, 0xc90a, 0xa77f, 0xc90a, 0x21, 0 + .dw 0xa7c0, 0xc90a, 0xa7ff, 0xc90a, 0x21, 0 + .dw 0xa840, 0xc90a, 0xa87f, 0xc90a, 0x21, 0 + .dw 0xa8c0, 0xc90a, 0xa8ff, 0xc90a, 0x21, 0 + .dw 0xa940, 0xc90a, 0xa97f, 0xc90a, 0x21, 0 + .dw 0xa9c0, 0xc90a, 0xa9ff, 0xc90a, 0x21, 0 + .dw 0xaa40, 0xc90a, 0xaa7f, 0xc90a, 0x21, 0 + .dw 0xaac0, 0xc90a, 0xaaff, 0xc90a, 0x21, 0 + .dw 0xab40, 0xc90a, 0xab7f, 0xc90a, 0x21, 0 + .dw 0xabc0, 0xc90a, 0xabff, 0xc90a, 0x21, 0 + .dw 0xac40, 0xc90a, 0xac7f, 0xc90a, 0x21, 0 + .dw 0xacc0, 0xc90a, 0xacff, 0xc90a, 0x21, 0 + .dw 0xad40, 0xc90a, 0xad7f, 0xc90a, 0x21, 0 + .dw 0xadc0, 0xc90a, 0xadff, 0xc90a, 0x21, 0 + .dw 0xae40, 0xc90a, 0xae7f, 0xc90a, 0x21, 0 + .dw 0xaec0, 0xc90a, 0xaeff, 0xc90a, 0x21, 0 + .dw 0xaf40, 0xc90a, 0xaf7f, 0xc90a, 0x21, 0 + .dw 0xafc0, 0xc90a, 0xafff, 0xc90a, 0x21, 0 + .dw 0xb040, 0xc90a, 0xb07f, 0xc90a, 0x21, 0 + .dw 0xb0c0, 0xc90a, 0xb0ff, 0xc90a, 0x21, 0 + .dw 0xb140, 0xc90a, 0xb17f, 0xc90a, 0x21, 0 + .dw 0xb1c0, 0xc90a, 0xb1ff, 0xc90a, 0x21, 0 + .dw 0xb240, 0xc90a, 0xb27f, 0xc90a, 0x21, 0 + .dw 0xb2c0, 0xc90a, 0xb2ff, 0xc90a, 0x21, 0 + .dw 0xb340, 0xc90a, 0xb37f, 0xc90a, 0x21, 0 + .dw 0xb3c0, 0xc90a, 0xb3ff, 0xc90a, 0x21, 0 + .dw 0xb440, 0xc90a, 0xb47f, 0xc90a, 0x21, 0 + .dw 0xb4c0, 0xc90a, 0xb4ff, 0xc90a, 0x21, 0 + .dw 0xb540, 0xc90a, 0xb57f, 0xc90a, 0x21, 0 + .dw 0xb5c0, 0xc90a, 0xb5ff, 0xc90a, 0x21, 0 + .dw 0xb640, 0xc90a, 0xb67f, 0xc90a, 0x21, 0 + .dw 0xb6c0, 0xc90a, 0xb6ff, 0xc90a, 0x21, 0 + .dw 0xb740, 0xc90a, 0xb77f, 0xc90a, 0x21, 0 + .dw 0xb7c0, 0xc90a, 0xb7ff, 0xc90a, 0x21, 0 + .dw 0xb840, 0xc90a, 0xb87f, 0xc90a, 0x21, 0 + .dw 0xb8c0, 0xc90a, 0xb8ff, 0xc90a, 0x21, 0 + .dw 0xb940, 0xc90a, 0xb97f, 0xc90a, 0x21, 0 + .dw 0xb9c0, 0xc90a, 0xdfff, 0xc90a, 0x21, 0 + .dw 0xe040, 0xc90a, 0xe07f, 0xc90a, 0x21, 0 + .dw 0xe0c0, 0xc90a, 0xe0ff, 0xc90a, 0x21, 0 + .dw 0xe140, 0xc90a, 0xe17f, 0xc90a, 0x21, 0 + .dw 0xe1c0, 0xc90a, 0xe1ff, 0xc90a, 0x21, 0 + .dw 0xe240, 0xc90a, 0xe27f, 0xc90a, 0x21, 0 + .dw 0xe2c0, 0xc90a, 0xe2ff, 0xc90a, 0x21, 0 + .dw 0xe340, 0xc90a, 0xe37f, 0xc90a, 0x21, 0 + .dw 0xe3c0, 0xc90a, 0xe3ff, 0xc90a, 0x21, 0 + .dw 0xe440, 0xc90a, 0xe47f, 0xc90a, 0x21, 0 + .dw 0xe4c0, 0xc90a, 0xe4ff, 0xc90a, 0x21, 0 + .dw 0xe540, 0xc90a, 0xe57f, 0xc90a, 0x21, 0 + .dw 0xe5c0, 0xc90a, 0xe5ff, 0xc90a, 0x21, 0 + .dw 0xe640, 0xc90a, 0xe67f, 0xc90a, 0x21, 0 + .dw 0xe6c0, 0xc90a, 0xe6ff, 0xc90a, 0x21, 0 + .dw 0xe740, 0xc90a, 0xe77f, 0xc90a, 0x21, 0 + .dw 0xe7c0, 0xc90a, 0xe7ff, 0xc90a, 0x21, 0 + .dw 0xe840, 0xc90a, 0xe87f, 0xc90a, 0x21, 0 + .dw 0xe8c0, 0xc90a, 0xe8ff, 0xc90a, 0x21, 0 + .dw 0xe940, 0xc90a, 0xe97f, 0xc90a, 0x21, 0 + .dw 0xe9c0, 0xc90a, 0xe9ff, 0xc90a, 0x21, 0 + .dw 0xea40, 0xc90a, 0xea7f, 0xc90a, 0x21, 0 + .dw 0xeac0, 0xc90a, 0xeaff, 0xc90a, 0x21, 0 + .dw 0xeb40, 0xc90a, 0xeb7f, 0xc90a, 0x21, 0 + .dw 0xebc0, 0xc90a, 0xebff, 0xc90a, 0x21, 0 + .dw 0xec40, 0xc90a, 0xec7f, 0xc90a, 0x21, 0 + .dw 0xecc0, 0xc90a, 0xecff, 0xc90a, 0x21, 0 + .dw 0xed40, 0xc90a, 0xed7f, 0xc90a, 0x21, 0 + .dw 0xedc0, 0xc90a, 0xedff, 0xc90a, 0x21, 0 + .dw 0xee40, 0xc90a, 0xee7f, 0xc90a, 0x21, 0 + .dw 0xeec0, 0xc90a, 0xeeff, 0xc90a, 0x21, 0 + .dw 0xef40, 0xc90a, 0xef7f, 0xc90a, 0x21, 0 + .dw 0xefc0, 0xc90a, 0xefff, 0xc90a, 0x21, 0 + .dw 0xf040, 0xc90a, 0xf07f, 0xc90a, 0x21, 0 + .dw 0xf0c0, 0xc90a, 0xf0ff, 0xc90a, 0x21, 0 + .dw 0xf140, 0xc90a, 0xf17f, 0xc90a, 0x21, 0 + .dw 0xf1c0, 0xc90a, 0xf1ff, 0xc90a, 0x21, 0 + .dw 0xf240, 0xc90a, 0xf27f, 0xc90a, 0x21, 0 + .dw 0xf2c0, 0xc90a, 0xf2ff, 0xc90a, 0x21, 0 + .dw 0xf340, 0xc90a, 0xf37f, 0xc90a, 0x21, 0 + .dw 0xf3c0, 0xc90a, 0xf3ff, 0xc90a, 0x21, 0 + .dw 0xf440, 0xc90a, 0xf47f, 0xc90a, 0x21, 0 + .dw 0xf4c0, 0xc90a, 0xf4ff, 0xc90a, 0x21, 0 + .dw 0xf540, 0xc90a, 0xf57f, 0xc90a, 0x21, 0 + .dw 0xf5c0, 0xc90a, 0xf5ff, 0xc90a, 0x21, 0 + .dw 0xf640, 0xc90a, 0xf67f, 0xc90a, 0x21, 0 + .dw 0xf6c0, 0xc90a, 0xf6ff, 0xc90a, 0x21, 0 + .dw 0xf740, 0xc90a, 0xf77f, 0xc90a, 0x21, 0 + .dw 0xf7c0, 0xc90a, 0xf7ff, 0xc90a, 0x21, 0 + .dw 0xf840, 0xc90a, 0xf87f, 0xc90a, 0x21, 0 + .dw 0xf8c0, 0xc90a, 0xf8ff, 0xc90a, 0x21, 0 + .dw 0xf940, 0xc90a, 0xf97f, 0xc90a, 0x21, 0 + .dw 0xf9c0, 0xc90a, 0x1fff, 0xc90b, 0x21, 0 + .dw 0x2040, 0xc90b, 0x207f, 0xc90b, 0x21, 0 + .dw 0x20c0, 0xc90b, 0x20ff, 0xc90b, 0x21, 0 + .dw 0x2140, 0xc90b, 0x217f, 0xc90b, 0x21, 0 + .dw 0x21c0, 0xc90b, 0x21ff, 0xc90b, 0x21, 0 + .dw 0x2240, 0xc90b, 0x227f, 0xc90b, 0x21, 0 + .dw 0x22c0, 0xc90b, 0x22ff, 0xc90b, 0x21, 0 + .dw 0x2340, 0xc90b, 0x237f, 0xc90b, 0x21, 0 + .dw 0x23c0, 0xc90b, 0x23ff, 0xc90b, 0x21, 0 + .dw 0x2440, 0xc90b, 0x247f, 0xc90b, 0x21, 0 + .dw 0x24c0, 0xc90b, 0x24ff, 0xc90b, 0x21, 0 + .dw 0x2540, 0xc90b, 0x257f, 0xc90b, 0x21, 0 + .dw 0x25c0, 0xc90b, 0x25ff, 0xc90b, 0x21, 0 + .dw 0x2640, 0xc90b, 0x267f, 0xc90b, 0x21, 0 + .dw 0x26c0, 0xc90b, 0x26ff, 0xc90b, 0x21, 0 + .dw 0x2740, 0xc90b, 0x277f, 0xc90b, 0x21, 0 + .dw 0x27c0, 0xc90b, 0x27ff, 0xc90b, 0x21, 0 + .dw 0x2840, 0xc90b, 0x287f, 0xc90b, 0x21, 0 + .dw 0x28c0, 0xc90b, 0x28ff, 0xc90b, 0x21, 0 + .dw 0x2940, 0xc90b, 0x297f, 0xc90b, 0x21, 0 + .dw 0x29c0, 0xc90b, 0x29ff, 0xc90b, 0x21, 0 + .dw 0x2a40, 0xc90b, 0x2a7f, 0xc90b, 0x21, 0 + .dw 0x2ac0, 0xc90b, 0x2aff, 0xc90b, 0x21, 0 + .dw 0x2b40, 0xc90b, 0x2b7f, 0xc90b, 0x21, 0 + .dw 0x2bc0, 0xc90b, 0x2bff, 0xc90b, 0x21, 0 + .dw 0x2c40, 0xc90b, 0x2c7f, 0xc90b, 0x21, 0 + .dw 0x2cc0, 0xc90b, 0x2cff, 0xc90b, 0x21, 0 + .dw 0x2d40, 0xc90b, 0x2d7f, 0xc90b, 0x21, 0 + .dw 0x2dc0, 0xc90b, 0x2dff, 0xc90b, 0x21, 0 + .dw 0x2e40, 0xc90b, 0x2e7f, 0xc90b, 0x21, 0 + .dw 0x2ec0, 0xc90b, 0x2eff, 0xc90b, 0x21, 0 + .dw 0x2f40, 0xc90b, 0x2f7f, 0xc90b, 0x21, 0 + .dw 0x2fc0, 0xc90b, 0x2fff, 0xc90b, 0x21, 0 + .dw 0x3040, 0xc90b, 0x307f, 0xc90b, 0x21, 0 + .dw 0x30c0, 0xc90b, 0x30ff, 0xc90b, 0x21, 0 + .dw 0x3140, 0xc90b, 0x317f, 0xc90b, 0x21, 0 + .dw 0x31c0, 0xc90b, 0x31ff, 0xc90b, 0x21, 0 + .dw 0x3240, 0xc90b, 0x327f, 0xc90b, 0x21, 0 + .dw 0x32c0, 0xc90b, 0x32ff, 0xc90b, 0x21, 0 + .dw 0x3340, 0xc90b, 0x337f, 0xc90b, 0x21, 0 + .dw 0x33c0, 0xc90b, 0x33ff, 0xc90b, 0x21, 0 + .dw 0x3440, 0xc90b, 0x347f, 0xc90b, 0x21, 0 + .dw 0x34c0, 0xc90b, 0x34ff, 0xc90b, 0x21, 0 + .dw 0x3540, 0xc90b, 0x357f, 0xc90b, 0x21, 0 + .dw 0x35c0, 0xc90b, 0x35ff, 0xc90b, 0x21, 0 + .dw 0x3640, 0xc90b, 0x367f, 0xc90b, 0x21, 0 + .dw 0x36c0, 0xc90b, 0x36ff, 0xc90b, 0x21, 0 + .dw 0x3740, 0xc90b, 0x377f, 0xc90b, 0x21, 0 + .dw 0x37c0, 0xc90b, 0x37ff, 0xc90b, 0x21, 0 + .dw 0x3840, 0xc90b, 0x387f, 0xc90b, 0x21, 0 + .dw 0x38c0, 0xc90b, 0x38ff, 0xc90b, 0x21, 0 + .dw 0x3940, 0xc90b, 0x397f, 0xc90b, 0x21, 0 + .dw 0x39c0, 0xc90b, 0xffff, 0xc90b, 0x21, 0 + .dw 0x0040, 0xc90c, 0x007f, 0xc90c, 0x21, 0 + .dw 0x00c0, 0xc90c, 0x00ff, 0xc90c, 0x21, 0 + .dw 0x0140, 0xc90c, 0x017f, 0xc90c, 0x21, 0 + .dw 0x01c0, 0xc90c, 0x01ff, 0xc90c, 0x21, 0 + .dw 0x0240, 0xc90c, 0x027f, 0xc90c, 0x21, 0 + .dw 0x02c0, 0xc90c, 0x02ff, 0xc90c, 0x21, 0 + .dw 0x0340, 0xc90c, 0x037f, 0xc90c, 0x21, 0 + .dw 0x03c0, 0xc90c, 0x03ff, 0xc90c, 0x21, 0 + .dw 0x0440, 0xc90c, 0x047f, 0xc90c, 0x21, 0 + .dw 0x04c0, 0xc90c, 0x04ff, 0xc90c, 0x21, 0 + .dw 0x0540, 0xc90c, 0x057f, 0xc90c, 0x21, 0 + .dw 0x05c0, 0xc90c, 0x05ff, 0xc90c, 0x21, 0 + .dw 0x0640, 0xc90c, 0x067f, 0xc90c, 0x21, 0 + .dw 0x06c0, 0xc90c, 0x06ff, 0xc90c, 0x21, 0 + .dw 0x0740, 0xc90c, 0x077f, 0xc90c, 0x21, 0 + .dw 0x07c0, 0xc90c, 0x07ff, 0xc90c, 0x21, 0 + .dw 0x0840, 0xc90c, 0x087f, 0xc90c, 0x21, 0 + .dw 0x08c0, 0xc90c, 0x08ff, 0xc90c, 0x21, 0 + .dw 0x0940, 0xc90c, 0x097f, 0xc90c, 0x21, 0 + .dw 0x09c0, 0xc90c, 0x09ff, 0xc90c, 0x21, 0 + .dw 0x0a40, 0xc90c, 0x0a7f, 0xc90c, 0x21, 0 + .dw 0x0ac0, 0xc90c, 0x0aff, 0xc90c, 0x21, 0 + .dw 0x0b40, 0xc90c, 0x0b7f, 0xc90c, 0x21, 0 + .dw 0x0bc0, 0xc90c, 0x0bff, 0xc90c, 0x21, 0 + .dw 0x0c40, 0xc90c, 0x0c7f, 0xc90c, 0x21, 0 + .dw 0x0cc0, 0xc90c, 0x0cff, 0xc90c, 0x21, 0 + .dw 0x0d40, 0xc90c, 0x0d7f, 0xc90c, 0x21, 0 + .dw 0x0dc0, 0xc90c, 0x0dff, 0xc90c, 0x21, 0 + .dw 0x0e40, 0xc90c, 0x0e7f, 0xc90c, 0x21, 0 + .dw 0x0ec0, 0xc90c, 0x0eff, 0xc90c, 0x21, 0 + .dw 0x0f40, 0xc90c, 0x0f7f, 0xc90c, 0x21, 0 + .dw 0x0fc0, 0xc90c, 0x0fff, 0xc90c, 0x21, 0 + .dw 0x1040, 0xc90c, 0x107f, 0xc90c, 0x21, 0 + .dw 0x10c0, 0xc90c, 0x10ff, 0xc90c, 0x21, 0 + .dw 0x1140, 0xc90c, 0x117f, 0xc90c, 0x21, 0 + .dw 0x11c0, 0xc90c, 0x11ff, 0xc90c, 0x21, 0 + .dw 0x1240, 0xc90c, 0x127f, 0xc90c, 0x21, 0 + .dw 0x12c0, 0xc90c, 0x12ff, 0xc90c, 0x21, 0 + .dw 0x1340, 0xc90c, 0x137f, 0xc90c, 0x21, 0 + .dw 0x13c0, 0xc90c, 0x13ff, 0xc90c, 0x21, 0 + .dw 0x1440, 0xc90c, 0x147f, 0xc90c, 0x21, 0 + .dw 0x14c0, 0xc90c, 0x14ff, 0xc90c, 0x21, 0 + .dw 0x1540, 0xc90c, 0x157f, 0xc90c, 0x21, 0 + .dw 0x15c0, 0xc90c, 0x15ff, 0xc90c, 0x21, 0 + .dw 0x1640, 0xc90c, 0x167f, 0xc90c, 0x21, 0 + .dw 0x16c0, 0xc90c, 0x16ff, 0xc90c, 0x21, 0 + .dw 0x1740, 0xc90c, 0x177f, 0xc90c, 0x21, 0 + .dw 0x17c0, 0xc90c, 0x17ff, 0xc90c, 0x21, 0 + .dw 0x1840, 0xc90c, 0x187f, 0xc90c, 0x21, 0 + .dw 0x18c0, 0xc90c, 0x18ff, 0xc90c, 0x21, 0 + .dw 0x1940, 0xc90c, 0x197f, 0xc90c, 0x21, 0 + .dw 0x19c0, 0xc90c, 0x1fff, 0xc90c, 0x21, 0 + .dw 0x2040, 0xc90c, 0x207f, 0xc90c, 0x21, 0 + .dw 0x20c0, 0xc90c, 0x20ff, 0xc90c, 0x21, 0 + .dw 0x2140, 0xc90c, 0x217f, 0xc90c, 0x21, 0 + .dw 0x21c0, 0xc90c, 0x21ff, 0xc90c, 0x21, 0 + .dw 0x2240, 0xc90c, 0x227f, 0xc90c, 0x21, 0 + .dw 0x22c0, 0xc90c, 0x22ff, 0xc90c, 0x21, 0 + .dw 0x2340, 0xc90c, 0x237f, 0xc90c, 0x21, 0 + .dw 0x23c0, 0xc90c, 0x23ff, 0xc90c, 0x21, 0 + .dw 0x2440, 0xc90c, 0x247f, 0xc90c, 0x21, 0 + .dw 0x24c0, 0xc90c, 0x24ff, 0xc90c, 0x21, 0 + .dw 0x2540, 0xc90c, 0x257f, 0xc90c, 0x21, 0 + .dw 0x25c0, 0xc90c, 0x25ff, 0xc90c, 0x21, 0 + .dw 0x2640, 0xc90c, 0x267f, 0xc90c, 0x21, 0 + .dw 0x26c0, 0xc90c, 0x26ff, 0xc90c, 0x21, 0 + .dw 0x2740, 0xc90c, 0x277f, 0xc90c, 0x21, 0 + .dw 0x27c0, 0xc90c, 0x27ff, 0xc90c, 0x21, 0 + .dw 0x2840, 0xc90c, 0x287f, 0xc90c, 0x21, 0 + .dw 0x28c0, 0xc90c, 0x28ff, 0xc90c, 0x21, 0 + .dw 0x2940, 0xc90c, 0x297f, 0xc90c, 0x21, 0 + .dw 0x29c0, 0xc90c, 0x29ff, 0xc90c, 0x21, 0 + .dw 0x2a40, 0xc90c, 0x2a7f, 0xc90c, 0x21, 0 + .dw 0x2ac0, 0xc90c, 0x2aff, 0xc90c, 0x21, 0 + .dw 0x2b40, 0xc90c, 0x2b7f, 0xc90c, 0x21, 0 + .dw 0x2bc0, 0xc90c, 0x2bff, 0xc90c, 0x21, 0 + .dw 0x2c40, 0xc90c, 0x2c7f, 0xc90c, 0x21, 0 + .dw 0x2cc0, 0xc90c, 0x2cff, 0xc90c, 0x21, 0 + .dw 0x2d40, 0xc90c, 0x2d7f, 0xc90c, 0x21, 0 + .dw 0x2dc0, 0xc90c, 0x2dff, 0xc90c, 0x21, 0 + .dw 0x2e40, 0xc90c, 0x2e7f, 0xc90c, 0x21, 0 + .dw 0x2ec0, 0xc90c, 0x2eff, 0xc90c, 0x21, 0 + .dw 0x2f40, 0xc90c, 0x2f7f, 0xc90c, 0x21, 0 + .dw 0x2fc0, 0xc90c, 0x2fff, 0xc90c, 0x21, 0 + .dw 0x3040, 0xc90c, 0x307f, 0xc90c, 0x21, 0 + .dw 0x30c0, 0xc90c, 0x30ff, 0xc90c, 0x21, 0 + .dw 0x3140, 0xc90c, 0x317f, 0xc90c, 0x21, 0 + .dw 0x31c0, 0xc90c, 0x31ff, 0xc90c, 0x21, 0 + .dw 0x3240, 0xc90c, 0x327f, 0xc90c, 0x21, 0 + .dw 0x32c0, 0xc90c, 0x32ff, 0xc90c, 0x21, 0 + .dw 0x3340, 0xc90c, 0x337f, 0xc90c, 0x21, 0 + .dw 0x33c0, 0xc90c, 0x33ff, 0xc90c, 0x21, 0 + .dw 0x3440, 0xc90c, 0x347f, 0xc90c, 0x21, 0 + .dw 0x34c0, 0xc90c, 0x34ff, 0xc90c, 0x21, 0 + .dw 0x3540, 0xc90c, 0x357f, 0xc90c, 0x21, 0 + .dw 0x35c0, 0xc90c, 0x35ff, 0xc90c, 0x21, 0 + .dw 0x3640, 0xc90c, 0x367f, 0xc90c, 0x21, 0 + .dw 0x36c0, 0xc90c, 0x36ff, 0xc90c, 0x21, 0 + .dw 0x3740, 0xc90c, 0x377f, 0xc90c, 0x21, 0 + .dw 0x37c0, 0xc90c, 0x37ff, 0xc90c, 0x21, 0 + .dw 0x3840, 0xc90c, 0x387f, 0xc90c, 0x21, 0 + .dw 0x38c0, 0xc90c, 0x38ff, 0xc90c, 0x21, 0 + .dw 0x3940, 0xc90c, 0x397f, 0xc90c, 0x21, 0 + .dw 0x39c0, 0xc90c, 0x3fff, 0xc90c, 0x21, 0 + .dw 0x4040, 0xc90c, 0x407f, 0xc90c, 0x21, 0 + .dw 0x40c0, 0xc90c, 0x40ff, 0xc90c, 0x21, 0 + .dw 0x4140, 0xc90c, 0x417f, 0xc90c, 0x21, 0 + .dw 0x41c0, 0xc90c, 0x41ff, 0xc90c, 0x21, 0 + .dw 0x4240, 0xc90c, 0x427f, 0xc90c, 0x21, 0 + .dw 0x42c0, 0xc90c, 0x42ff, 0xc90c, 0x21, 0 + .dw 0x4340, 0xc90c, 0x437f, 0xc90c, 0x21, 0 + .dw 0x43c0, 0xc90c, 0x43ff, 0xc90c, 0x21, 0 + .dw 0x4440, 0xc90c, 0x447f, 0xc90c, 0x21, 0 + .dw 0x44c0, 0xc90c, 0x44ff, 0xc90c, 0x21, 0 + .dw 0x4540, 0xc90c, 0x457f, 0xc90c, 0x21, 0 + .dw 0x45c0, 0xc90c, 0x45ff, 0xc90c, 0x21, 0 + .dw 0x4640, 0xc90c, 0x467f, 0xc90c, 0x21, 0 + .dw 0x46c0, 0xc90c, 0x46ff, 0xc90c, 0x21, 0 + .dw 0x4740, 0xc90c, 0x477f, 0xc90c, 0x21, 0 + .dw 0x47c0, 0xc90c, 0x47ff, 0xc90c, 0x21, 0 + .dw 0x4840, 0xc90c, 0x487f, 0xc90c, 0x21, 0 + .dw 0x48c0, 0xc90c, 0x48ff, 0xc90c, 0x21, 0 + .dw 0x4940, 0xc90c, 0x497f, 0xc90c, 0x21, 0 + .dw 0x49c0, 0xc90c, 0x49ff, 0xc90c, 0x21, 0 + .dw 0x4a40, 0xc90c, 0x4a7f, 0xc90c, 0x21, 0 + .dw 0x4ac0, 0xc90c, 0x4aff, 0xc90c, 0x21, 0 + .dw 0x4b40, 0xc90c, 0x4b7f, 0xc90c, 0x21, 0 + .dw 0x4bc0, 0xc90c, 0x4bff, 0xc90c, 0x21, 0 + .dw 0x4c40, 0xc90c, 0x4c7f, 0xc90c, 0x21, 0 + .dw 0x4cc0, 0xc90c, 0x4cff, 0xc90c, 0x21, 0 + .dw 0x4d40, 0xc90c, 0x4d7f, 0xc90c, 0x21, 0 + .dw 0x4dc0, 0xc90c, 0x4dff, 0xc90c, 0x21, 0 + .dw 0x4e40, 0xc90c, 0x4e7f, 0xc90c, 0x21, 0 + .dw 0x4ec0, 0xc90c, 0x4eff, 0xc90c, 0x21, 0 + .dw 0x4f40, 0xc90c, 0x4f7f, 0xc90c, 0x21, 0 + .dw 0x4fc0, 0xc90c, 0x4fff, 0xc90c, 0x21, 0 + .dw 0x5040, 0xc90c, 0x507f, 0xc90c, 0x21, 0 + .dw 0x50c0, 0xc90c, 0x50ff, 0xc90c, 0x21, 0 + .dw 0x5140, 0xc90c, 0x517f, 0xc90c, 0x21, 0 + .dw 0x51c0, 0xc90c, 0x51ff, 0xc90c, 0x21, 0 + .dw 0x5240, 0xc90c, 0x527f, 0xc90c, 0x21, 0 + .dw 0x52c0, 0xc90c, 0x52ff, 0xc90c, 0x21, 0 + .dw 0x5340, 0xc90c, 0x537f, 0xc90c, 0x21, 0 + .dw 0x53c0, 0xc90c, 0x53ff, 0xc90c, 0x21, 0 + .dw 0x5440, 0xc90c, 0x547f, 0xc90c, 0x21, 0 + .dw 0x54c0, 0xc90c, 0x54ff, 0xc90c, 0x21, 0 + .dw 0x5540, 0xc90c, 0x557f, 0xc90c, 0x21, 0 + .dw 0x55c0, 0xc90c, 0x55ff, 0xc90c, 0x21, 0 + .dw 0x5640, 0xc90c, 0x567f, 0xc90c, 0x21, 0 + .dw 0x56c0, 0xc90c, 0x56ff, 0xc90c, 0x21, 0 + .dw 0x5740, 0xc90c, 0x577f, 0xc90c, 0x21, 0 + .dw 0x57c0, 0xc90c, 0x57ff, 0xc90c, 0x21, 0 + .dw 0x5840, 0xc90c, 0x587f, 0xc90c, 0x21, 0 + .dw 0x58c0, 0xc90c, 0x58ff, 0xc90c, 0x21, 0 + .dw 0x5940, 0xc90c, 0x597f, 0xc90c, 0x21, 0 + .dw 0x59c0, 0xc90c, 0x5fff, 0xc90c, 0x21, 0 + .dw 0x6040, 0xc90c, 0x607f, 0xc90c, 0x21, 0 + .dw 0x60c0, 0xc90c, 0x60ff, 0xc90c, 0x21, 0 + .dw 0x6140, 0xc90c, 0x617f, 0xc90c, 0x21, 0 + .dw 0x61c0, 0xc90c, 0x61ff, 0xc90c, 0x21, 0 + .dw 0x6240, 0xc90c, 0x627f, 0xc90c, 0x21, 0 + .dw 0x62c0, 0xc90c, 0x62ff, 0xc90c, 0x21, 0 + .dw 0x6340, 0xc90c, 0x637f, 0xc90c, 0x21, 0 + .dw 0x63c0, 0xc90c, 0x63ff, 0xc90c, 0x21, 0 + .dw 0x6440, 0xc90c, 0x647f, 0xc90c, 0x21, 0 + .dw 0x64c0, 0xc90c, 0x64ff, 0xc90c, 0x21, 0 + .dw 0x6540, 0xc90c, 0x657f, 0xc90c, 0x21, 0 + .dw 0x65c0, 0xc90c, 0x65ff, 0xc90c, 0x21, 0 + .dw 0x6640, 0xc90c, 0x667f, 0xc90c, 0x21, 0 + .dw 0x66c0, 0xc90c, 0x66ff, 0xc90c, 0x21, 0 + .dw 0x6740, 0xc90c, 0x677f, 0xc90c, 0x21, 0 + .dw 0x67c0, 0xc90c, 0x67ff, 0xc90c, 0x21, 0 + .dw 0x6840, 0xc90c, 0x687f, 0xc90c, 0x21, 0 + .dw 0x68c0, 0xc90c, 0x68ff, 0xc90c, 0x21, 0 + .dw 0x6940, 0xc90c, 0x697f, 0xc90c, 0x21, 0 + .dw 0x69c0, 0xc90c, 0x69ff, 0xc90c, 0x21, 0 + .dw 0x6a40, 0xc90c, 0x6a7f, 0xc90c, 0x21, 0 + .dw 0x6ac0, 0xc90c, 0x6aff, 0xc90c, 0x21, 0 + .dw 0x6b40, 0xc90c, 0x6b7f, 0xc90c, 0x21, 0 + .dw 0x6bc0, 0xc90c, 0x6bff, 0xc90c, 0x21, 0 + .dw 0x6c40, 0xc90c, 0x6c7f, 0xc90c, 0x21, 0 + .dw 0x6cc0, 0xc90c, 0x6cff, 0xc90c, 0x21, 0 + .dw 0x6d40, 0xc90c, 0x6d7f, 0xc90c, 0x21, 0 + .dw 0x6dc0, 0xc90c, 0x6dff, 0xc90c, 0x21, 0 + .dw 0x6e40, 0xc90c, 0x6e7f, 0xc90c, 0x21, 0 + .dw 0x6ec0, 0xc90c, 0x6eff, 0xc90c, 0x21, 0 + .dw 0x6f40, 0xc90c, 0x6f7f, 0xc90c, 0x21, 0 + .dw 0x6fc0, 0xc90c, 0x6fff, 0xc90c, 0x21, 0 + .dw 0x7040, 0xc90c, 0x707f, 0xc90c, 0x21, 0 + .dw 0x70c0, 0xc90c, 0x70ff, 0xc90c, 0x21, 0 + .dw 0x7140, 0xc90c, 0x717f, 0xc90c, 0x21, 0 + .dw 0x71c0, 0xc90c, 0x71ff, 0xc90c, 0x21, 0 + .dw 0x7240, 0xc90c, 0x727f, 0xc90c, 0x21, 0 + .dw 0x72c0, 0xc90c, 0x72ff, 0xc90c, 0x21, 0 + .dw 0x7340, 0xc90c, 0x737f, 0xc90c, 0x21, 0 + .dw 0x73c0, 0xc90c, 0x73ff, 0xc90c, 0x21, 0 + .dw 0x7440, 0xc90c, 0x747f, 0xc90c, 0x21, 0 + .dw 0x74c0, 0xc90c, 0x74ff, 0xc90c, 0x21, 0 + .dw 0x7540, 0xc90c, 0x757f, 0xc90c, 0x21, 0 + .dw 0x75c0, 0xc90c, 0x75ff, 0xc90c, 0x21, 0 + .dw 0x7640, 0xc90c, 0x767f, 0xc90c, 0x21, 0 + .dw 0x76c0, 0xc90c, 0x76ff, 0xc90c, 0x21, 0 + .dw 0x7740, 0xc90c, 0x777f, 0xc90c, 0x21, 0 + .dw 0x77c0, 0xc90c, 0x77ff, 0xc90c, 0x21, 0 + .dw 0x7840, 0xc90c, 0x787f, 0xc90c, 0x21, 0 + .dw 0x78c0, 0xc90c, 0x78ff, 0xc90c, 0x21, 0 + .dw 0x7940, 0xc90c, 0x797f, 0xc90c, 0x21, 0 + .dw 0x79c0, 0xc90c, 0x7fff, 0xc90c, 0x21, 0 + .dw 0x8040, 0xc90c, 0x807f, 0xc90c, 0x21, 0 + .dw 0x80c0, 0xc90c, 0x80ff, 0xc90c, 0x21, 0 + .dw 0x8140, 0xc90c, 0x817f, 0xc90c, 0x21, 0 + .dw 0x81c0, 0xc90c, 0x81ff, 0xc90c, 0x21, 0 + .dw 0x8240, 0xc90c, 0x827f, 0xc90c, 0x21, 0 + .dw 0x82c0, 0xc90c, 0x82ff, 0xc90c, 0x21, 0 + .dw 0x8340, 0xc90c, 0x837f, 0xc90c, 0x21, 0 + .dw 0x83c0, 0xc90c, 0x83ff, 0xc90c, 0x21, 0 + .dw 0x8440, 0xc90c, 0x847f, 0xc90c, 0x21, 0 + .dw 0x84c0, 0xc90c, 0x84ff, 0xc90c, 0x21, 0 + .dw 0x8540, 0xc90c, 0x857f, 0xc90c, 0x21, 0 + .dw 0x85c0, 0xc90c, 0x85ff, 0xc90c, 0x21, 0 + .dw 0x8640, 0xc90c, 0x867f, 0xc90c, 0x21, 0 + .dw 0x86c0, 0xc90c, 0x86ff, 0xc90c, 0x21, 0 + .dw 0x8740, 0xc90c, 0x877f, 0xc90c, 0x21, 0 + .dw 0x87c0, 0xc90c, 0x87ff, 0xc90c, 0x21, 0 + .dw 0x8840, 0xc90c, 0x887f, 0xc90c, 0x21, 0 + .dw 0x88c0, 0xc90c, 0x88ff, 0xc90c, 0x21, 0 + .dw 0x8940, 0xc90c, 0x897f, 0xc90c, 0x21, 0 + .dw 0x89c0, 0xc90c, 0x89ff, 0xc90c, 0x21, 0 + .dw 0x8a40, 0xc90c, 0x8a7f, 0xc90c, 0x21, 0 + .dw 0x8ac0, 0xc90c, 0x8aff, 0xc90c, 0x21, 0 + .dw 0x8b40, 0xc90c, 0x8b7f, 0xc90c, 0x21, 0 + .dw 0x8bc0, 0xc90c, 0x8bff, 0xc90c, 0x21, 0 + .dw 0x8c40, 0xc90c, 0x8c7f, 0xc90c, 0x21, 0 + .dw 0x8cc0, 0xc90c, 0x8cff, 0xc90c, 0x21, 0 + .dw 0x8d40, 0xc90c, 0x8d7f, 0xc90c, 0x21, 0 + .dw 0x8dc0, 0xc90c, 0x8dff, 0xc90c, 0x21, 0 + .dw 0x8e40, 0xc90c, 0x8e7f, 0xc90c, 0x21, 0 + .dw 0x8ec0, 0xc90c, 0x8eff, 0xc90c, 0x21, 0 + .dw 0x8f40, 0xc90c, 0x8f7f, 0xc90c, 0x21, 0 + .dw 0x8fc0, 0xc90c, 0x8fff, 0xc90c, 0x21, 0 + .dw 0x9040, 0xc90c, 0x907f, 0xc90c, 0x21, 0 + .dw 0x90c0, 0xc90c, 0x90ff, 0xc90c, 0x21, 0 + .dw 0x9140, 0xc90c, 0x917f, 0xc90c, 0x21, 0 + .dw 0x91c0, 0xc90c, 0x91ff, 0xc90c, 0x21, 0 + .dw 0x9240, 0xc90c, 0x927f, 0xc90c, 0x21, 0 + .dw 0x92c0, 0xc90c, 0x92ff, 0xc90c, 0x21, 0 + .dw 0x9340, 0xc90c, 0x937f, 0xc90c, 0x21, 0 + .dw 0x93c0, 0xc90c, 0x93ff, 0xc90c, 0x21, 0 + .dw 0x9440, 0xc90c, 0x947f, 0xc90c, 0x21, 0 + .dw 0x94c0, 0xc90c, 0x94ff, 0xc90c, 0x21, 0 + .dw 0x9540, 0xc90c, 0x957f, 0xc90c, 0x21, 0 + .dw 0x95c0, 0xc90c, 0x95ff, 0xc90c, 0x21, 0 + .dw 0x9640, 0xc90c, 0x967f, 0xc90c, 0x21, 0 + .dw 0x96c0, 0xc90c, 0x96ff, 0xc90c, 0x21, 0 + .dw 0x9740, 0xc90c, 0x977f, 0xc90c, 0x21, 0 + .dw 0x97c0, 0xc90c, 0x97ff, 0xc90c, 0x21, 0 + .dw 0x9840, 0xc90c, 0x987f, 0xc90c, 0x21, 0 + .dw 0x98c0, 0xc90c, 0x98ff, 0xc90c, 0x21, 0 + .dw 0x9940, 0xc90c, 0x997f, 0xc90c, 0x21, 0 + .dw 0x99c0, 0xc90c, 0x9fff, 0xc90c, 0x21, 0 + .dw 0xa040, 0xc90c, 0xa07f, 0xc90c, 0x21, 0 + .dw 0xa0c0, 0xc90c, 0xa0ff, 0xc90c, 0x21, 0 + .dw 0xa140, 0xc90c, 0xa17f, 0xc90c, 0x21, 0 + .dw 0xa1c0, 0xc90c, 0xa1ff, 0xc90c, 0x21, 0 + .dw 0xa240, 0xc90c, 0xa27f, 0xc90c, 0x21, 0 + .dw 0xa2c0, 0xc90c, 0xa2ff, 0xc90c, 0x21, 0 + .dw 0xa340, 0xc90c, 0xa37f, 0xc90c, 0x21, 0 + .dw 0xa3c0, 0xc90c, 0xa3ff, 0xc90c, 0x21, 0 + .dw 0xa440, 0xc90c, 0xa47f, 0xc90c, 0x21, 0 + .dw 0xa4c0, 0xc90c, 0xa4ff, 0xc90c, 0x21, 0 + .dw 0xa540, 0xc90c, 0xa57f, 0xc90c, 0x21, 0 + .dw 0xa5c0, 0xc90c, 0xa5ff, 0xc90c, 0x21, 0 + .dw 0xa640, 0xc90c, 0xa67f, 0xc90c, 0x21, 0 + .dw 0xa6c0, 0xc90c, 0xa6ff, 0xc90c, 0x21, 0 + .dw 0xa740, 0xc90c, 0xa77f, 0xc90c, 0x21, 0 + .dw 0xa7c0, 0xc90c, 0xa7ff, 0xc90c, 0x21, 0 + .dw 0xa840, 0xc90c, 0xa87f, 0xc90c, 0x21, 0 + .dw 0xa8c0, 0xc90c, 0xa8ff, 0xc90c, 0x21, 0 + .dw 0xa940, 0xc90c, 0xa97f, 0xc90c, 0x21, 0 + .dw 0xa9c0, 0xc90c, 0xa9ff, 0xc90c, 0x21, 0 + .dw 0xaa40, 0xc90c, 0xaa7f, 0xc90c, 0x21, 0 + .dw 0xaac0, 0xc90c, 0xaaff, 0xc90c, 0x21, 0 + .dw 0xab40, 0xc90c, 0xab7f, 0xc90c, 0x21, 0 + .dw 0xabc0, 0xc90c, 0xabff, 0xc90c, 0x21, 0 + .dw 0xac40, 0xc90c, 0xac7f, 0xc90c, 0x21, 0 + .dw 0xacc0, 0xc90c, 0xacff, 0xc90c, 0x21, 0 + .dw 0xad40, 0xc90c, 0xad7f, 0xc90c, 0x21, 0 + .dw 0xadc0, 0xc90c, 0xadff, 0xc90c, 0x21, 0 + .dw 0xae40, 0xc90c, 0xae7f, 0xc90c, 0x21, 0 + .dw 0xaec0, 0xc90c, 0xaeff, 0xc90c, 0x21, 0 + .dw 0xaf40, 0xc90c, 0xaf7f, 0xc90c, 0x21, 0 + .dw 0xafc0, 0xc90c, 0xafff, 0xc90c, 0x21, 0 + .dw 0xb040, 0xc90c, 0xb07f, 0xc90c, 0x21, 0 + .dw 0xb0c0, 0xc90c, 0xb0ff, 0xc90c, 0x21, 0 + .dw 0xb140, 0xc90c, 0xb17f, 0xc90c, 0x21, 0 + .dw 0xb1c0, 0xc90c, 0xb1ff, 0xc90c, 0x21, 0 + .dw 0xb240, 0xc90c, 0xb27f, 0xc90c, 0x21, 0 + .dw 0xb2c0, 0xc90c, 0xb2ff, 0xc90c, 0x21, 0 + .dw 0xb340, 0xc90c, 0xb37f, 0xc90c, 0x21, 0 + .dw 0xb3c0, 0xc90c, 0xb3ff, 0xc90c, 0x21, 0 + .dw 0xb440, 0xc90c, 0xb47f, 0xc90c, 0x21, 0 + .dw 0xb4c0, 0xc90c, 0xb4ff, 0xc90c, 0x21, 0 + .dw 0xb540, 0xc90c, 0xb57f, 0xc90c, 0x21, 0 + .dw 0xb5c0, 0xc90c, 0xb5ff, 0xc90c, 0x21, 0 + .dw 0xb640, 0xc90c, 0xb67f, 0xc90c, 0x21, 0 + .dw 0xb6c0, 0xc90c, 0xb6ff, 0xc90c, 0x21, 0 + .dw 0xb740, 0xc90c, 0xb77f, 0xc90c, 0x21, 0 + .dw 0xb7c0, 0xc90c, 0xb7ff, 0xc90c, 0x21, 0 + .dw 0xb840, 0xc90c, 0xb87f, 0xc90c, 0x21, 0 + .dw 0xb8c0, 0xc90c, 0xb8ff, 0xc90c, 0x21, 0 + .dw 0xb940, 0xc90c, 0xb97f, 0xc90c, 0x21, 0 + .dw 0xb9c0, 0xc90c, 0xbfff, 0xc90c, 0x21, 0 + .dw 0xc040, 0xc90c, 0xc07f, 0xc90c, 0x21, 0 + .dw 0xc0c0, 0xc90c, 0xc0ff, 0xc90c, 0x21, 0 + .dw 0xc140, 0xc90c, 0xc17f, 0xc90c, 0x21, 0 + .dw 0xc1c0, 0xc90c, 0xc1ff, 0xc90c, 0x21, 0 + .dw 0xc240, 0xc90c, 0xc27f, 0xc90c, 0x21, 0 + .dw 0xc2c0, 0xc90c, 0xc2ff, 0xc90c, 0x21, 0 + .dw 0xc340, 0xc90c, 0xc37f, 0xc90c, 0x21, 0 + .dw 0xc3c0, 0xc90c, 0xc3ff, 0xc90c, 0x21, 0 + .dw 0xc440, 0xc90c, 0xc47f, 0xc90c, 0x21, 0 + .dw 0xc4c0, 0xc90c, 0xc4ff, 0xc90c, 0x21, 0 + .dw 0xc540, 0xc90c, 0xc57f, 0xc90c, 0x21, 0 + .dw 0xc5c0, 0xc90c, 0xc5ff, 0xc90c, 0x21, 0 + .dw 0xc640, 0xc90c, 0xc67f, 0xc90c, 0x21, 0 + .dw 0xc6c0, 0xc90c, 0xc6ff, 0xc90c, 0x21, 0 + .dw 0xc740, 0xc90c, 0xc77f, 0xc90c, 0x21, 0 + .dw 0xc7c0, 0xc90c, 0xc7ff, 0xc90c, 0x21, 0 + .dw 0xc840, 0xc90c, 0xc87f, 0xc90c, 0x21, 0 + .dw 0xc8c0, 0xc90c, 0xc8ff, 0xc90c, 0x21, 0 + .dw 0xc940, 0xc90c, 0xc97f, 0xc90c, 0x21, 0 + .dw 0xc9c0, 0xc90c, 0xc9ff, 0xc90c, 0x21, 0 + .dw 0xca40, 0xc90c, 0xca7f, 0xc90c, 0x21, 0 + .dw 0xcac0, 0xc90c, 0xcaff, 0xc90c, 0x21, 0 + .dw 0xcb40, 0xc90c, 0xcb7f, 0xc90c, 0x21, 0 + .dw 0xcbc0, 0xc90c, 0xcbff, 0xc90c, 0x21, 0 + .dw 0xcc40, 0xc90c, 0xcc7f, 0xc90c, 0x21, 0 + .dw 0xccc0, 0xc90c, 0xccff, 0xc90c, 0x21, 0 + .dw 0xcd40, 0xc90c, 0xcd7f, 0xc90c, 0x21, 0 + .dw 0xcdc0, 0xc90c, 0xcdff, 0xc90c, 0x21, 0 + .dw 0xce40, 0xc90c, 0xce7f, 0xc90c, 0x21, 0 + .dw 0xcec0, 0xc90c, 0xceff, 0xc90c, 0x21, 0 + .dw 0xcf40, 0xc90c, 0xcf7f, 0xc90c, 0x21, 0 + .dw 0xcfc0, 0xc90c, 0xcfff, 0xc90c, 0x21, 0 + .dw 0xd040, 0xc90c, 0xd07f, 0xc90c, 0x21, 0 + .dw 0xd0c0, 0xc90c, 0xd0ff, 0xc90c, 0x21, 0 + .dw 0xd140, 0xc90c, 0xd17f, 0xc90c, 0x21, 0 + .dw 0xd1c0, 0xc90c, 0xd1ff, 0xc90c, 0x21, 0 + .dw 0xd240, 0xc90c, 0xd27f, 0xc90c, 0x21, 0 + .dw 0xd2c0, 0xc90c, 0xd2ff, 0xc90c, 0x21, 0 + .dw 0xd340, 0xc90c, 0xd37f, 0xc90c, 0x21, 0 + .dw 0xd3c0, 0xc90c, 0xd3ff, 0xc90c, 0x21, 0 + .dw 0xd440, 0xc90c, 0xd47f, 0xc90c, 0x21, 0 + .dw 0xd4c0, 0xc90c, 0xd4ff, 0xc90c, 0x21, 0 + .dw 0xd540, 0xc90c, 0xd57f, 0xc90c, 0x21, 0 + .dw 0xd5c0, 0xc90c, 0xd5ff, 0xc90c, 0x21, 0 + .dw 0xd640, 0xc90c, 0xd67f, 0xc90c, 0x21, 0 + .dw 0xd6c0, 0xc90c, 0xd6ff, 0xc90c, 0x21, 0 + .dw 0xd740, 0xc90c, 0xd77f, 0xc90c, 0x21, 0 + .dw 0xd7c0, 0xc90c, 0xd7ff, 0xc90c, 0x21, 0 + .dw 0xd840, 0xc90c, 0xd87f, 0xc90c, 0x21, 0 + .dw 0xd8c0, 0xc90c, 0xd8ff, 0xc90c, 0x21, 0 + .dw 0xd940, 0xc90c, 0xd97f, 0xc90c, 0x21, 0 + .dw 0xd9c0, 0xc90c, 0xdfff, 0xc90c, 0x21, 0 + .dw 0xe040, 0xc90c, 0xe07f, 0xc90c, 0x21, 0 + .dw 0xe0c0, 0xc90c, 0xe0ff, 0xc90c, 0x21, 0 + .dw 0xe140, 0xc90c, 0xe17f, 0xc90c, 0x21, 0 + .dw 0xe1c0, 0xc90c, 0xe1ff, 0xc90c, 0x21, 0 + .dw 0xe240, 0xc90c, 0xe27f, 0xc90c, 0x21, 0 + .dw 0xe2c0, 0xc90c, 0xe2ff, 0xc90c, 0x21, 0 + .dw 0xe340, 0xc90c, 0xe37f, 0xc90c, 0x21, 0 + .dw 0xe3c0, 0xc90c, 0xe3ff, 0xc90c, 0x21, 0 + .dw 0xe440, 0xc90c, 0xe47f, 0xc90c, 0x21, 0 + .dw 0xe4c0, 0xc90c, 0xe4ff, 0xc90c, 0x21, 0 + .dw 0xe540, 0xc90c, 0xe57f, 0xc90c, 0x21, 0 + .dw 0xe5c0, 0xc90c, 0xe5ff, 0xc90c, 0x21, 0 + .dw 0xe640, 0xc90c, 0xe67f, 0xc90c, 0x21, 0 + .dw 0xe6c0, 0xc90c, 0xe6ff, 0xc90c, 0x21, 0 + .dw 0xe740, 0xc90c, 0xe77f, 0xc90c, 0x21, 0 + .dw 0xe7c0, 0xc90c, 0xe7ff, 0xc90c, 0x21, 0 + .dw 0xe840, 0xc90c, 0xe87f, 0xc90c, 0x21, 0 + .dw 0xe8c0, 0xc90c, 0xe8ff, 0xc90c, 0x21, 0 + .dw 0xe940, 0xc90c, 0xe97f, 0xc90c, 0x21, 0 + .dw 0xe9c0, 0xc90c, 0xe9ff, 0xc90c, 0x21, 0 + .dw 0xea40, 0xc90c, 0xea7f, 0xc90c, 0x21, 0 + .dw 0xeac0, 0xc90c, 0xeaff, 0xc90c, 0x21, 0 + .dw 0xeb40, 0xc90c, 0xeb7f, 0xc90c, 0x21, 0 + .dw 0xebc0, 0xc90c, 0xebff, 0xc90c, 0x21, 0 + .dw 0xec40, 0xc90c, 0xec7f, 0xc90c, 0x21, 0 + .dw 0xecc0, 0xc90c, 0xecff, 0xc90c, 0x21, 0 + .dw 0xed40, 0xc90c, 0xed7f, 0xc90c, 0x21, 0 + .dw 0xedc0, 0xc90c, 0xedff, 0xc90c, 0x21, 0 + .dw 0xee40, 0xc90c, 0xee7f, 0xc90c, 0x21, 0 + .dw 0xeec0, 0xc90c, 0xeeff, 0xc90c, 0x21, 0 + .dw 0xef40, 0xc90c, 0xef7f, 0xc90c, 0x21, 0 + .dw 0xefc0, 0xc90c, 0xefff, 0xc90c, 0x21, 0 + .dw 0xf040, 0xc90c, 0xf07f, 0xc90c, 0x21, 0 + .dw 0xf0c0, 0xc90c, 0xf0ff, 0xc90c, 0x21, 0 + .dw 0xf140, 0xc90c, 0xf17f, 0xc90c, 0x21, 0 + .dw 0xf1c0, 0xc90c, 0xf1ff, 0xc90c, 0x21, 0 + .dw 0xf240, 0xc90c, 0xf27f, 0xc90c, 0x21, 0 + .dw 0xf2c0, 0xc90c, 0xf2ff, 0xc90c, 0x21, 0 + .dw 0xf340, 0xc90c, 0xf37f, 0xc90c, 0x21, 0 + .dw 0xf3c0, 0xc90c, 0xf3ff, 0xc90c, 0x21, 0 + .dw 0xf440, 0xc90c, 0xf47f, 0xc90c, 0x21, 0 + .dw 0xf4c0, 0xc90c, 0xf4ff, 0xc90c, 0x21, 0 + .dw 0xf540, 0xc90c, 0xf57f, 0xc90c, 0x21, 0 + .dw 0xf5c0, 0xc90c, 0xf5ff, 0xc90c, 0x21, 0 + .dw 0xf640, 0xc90c, 0xf67f, 0xc90c, 0x21, 0 + .dw 0xf6c0, 0xc90c, 0xf6ff, 0xc90c, 0x21, 0 + .dw 0xf740, 0xc90c, 0xf77f, 0xc90c, 0x21, 0 + .dw 0xf7c0, 0xc90c, 0xf7ff, 0xc90c, 0x21, 0 + .dw 0xf840, 0xc90c, 0xf87f, 0xc90c, 0x21, 0 + .dw 0xf8c0, 0xc90c, 0xf8ff, 0xc90c, 0x21, 0 + .dw 0xf940, 0xc90c, 0xf97f, 0xc90c, 0x21, 0 + .dw 0xf9c0, 0xc90c, 0xffff, 0xc90c, 0x21, 0 + .dw 0x0040, 0xc90d, 0x007f, 0xc90d, 0x21, 0 + .dw 0x00c0, 0xc90d, 0x00ff, 0xc90d, 0x21, 0 + .dw 0x0140, 0xc90d, 0x017f, 0xc90d, 0x21, 0 + .dw 0x01c0, 0xc90d, 0x01ff, 0xc90d, 0x21, 0 + .dw 0x0240, 0xc90d, 0x027f, 0xc90d, 0x21, 0 + .dw 0x02c0, 0xc90d, 0x02ff, 0xc90d, 0x21, 0 + .dw 0x0340, 0xc90d, 0x037f, 0xc90d, 0x21, 0 + .dw 0x03c0, 0xc90d, 0x03ff, 0xc90d, 0x21, 0 + .dw 0x0440, 0xc90d, 0x047f, 0xc90d, 0x21, 0 + .dw 0x04c0, 0xc90d, 0x04ff, 0xc90d, 0x21, 0 + .dw 0x0540, 0xc90d, 0x057f, 0xc90d, 0x21, 0 + .dw 0x05c0, 0xc90d, 0x05ff, 0xc90d, 0x21, 0 + .dw 0x0640, 0xc90d, 0x067f, 0xc90d, 0x21, 0 + .dw 0x06c0, 0xc90d, 0x06ff, 0xc90d, 0x21, 0 + .dw 0x0740, 0xc90d, 0x077f, 0xc90d, 0x21, 0 + .dw 0x07c0, 0xc90d, 0x07ff, 0xc90d, 0x21, 0 + .dw 0x0840, 0xc90d, 0x087f, 0xc90d, 0x21, 0 + .dw 0x08c0, 0xc90d, 0x08ff, 0xc90d, 0x21, 0 + .dw 0x0940, 0xc90d, 0x097f, 0xc90d, 0x21, 0 + .dw 0x09c0, 0xc90d, 0x09ff, 0xc90d, 0x21, 0 + .dw 0x0a40, 0xc90d, 0x0a7f, 0xc90d, 0x21, 0 + .dw 0x0ac0, 0xc90d, 0x0aff, 0xc90d, 0x21, 0 + .dw 0x0b40, 0xc90d, 0x0b7f, 0xc90d, 0x21, 0 + .dw 0x0bc0, 0xc90d, 0x0bff, 0xc90d, 0x21, 0 + .dw 0x0c40, 0xc90d, 0x0c7f, 0xc90d, 0x21, 0 + .dw 0x0cc0, 0xc90d, 0x0cff, 0xc90d, 0x21, 0 + .dw 0x0d40, 0xc90d, 0x0d7f, 0xc90d, 0x21, 0 + .dw 0x0dc0, 0xc90d, 0x0dff, 0xc90d, 0x21, 0 + .dw 0x0e40, 0xc90d, 0x0e7f, 0xc90d, 0x21, 0 + .dw 0x0ec0, 0xc90d, 0x0eff, 0xc90d, 0x21, 0 + .dw 0x0f40, 0xc90d, 0x0f7f, 0xc90d, 0x21, 0 + .dw 0x0fc0, 0xc90d, 0x0fff, 0xc90d, 0x21, 0 + .dw 0x1040, 0xc90d, 0x107f, 0xc90d, 0x21, 0 + .dw 0x10c0, 0xc90d, 0x10ff, 0xc90d, 0x21, 0 + .dw 0x1140, 0xc90d, 0x117f, 0xc90d, 0x21, 0 + .dw 0x11c0, 0xc90d, 0x11ff, 0xc90d, 0x21, 0 + .dw 0x1240, 0xc90d, 0x127f, 0xc90d, 0x21, 0 + .dw 0x12c0, 0xc90d, 0x12ff, 0xc90d, 0x21, 0 + .dw 0x1340, 0xc90d, 0x137f, 0xc90d, 0x21, 0 + .dw 0x13c0, 0xc90d, 0x13ff, 0xc90d, 0x21, 0 + .dw 0x1440, 0xc90d, 0x147f, 0xc90d, 0x21, 0 + .dw 0x14c0, 0xc90d, 0x14ff, 0xc90d, 0x21, 0 + .dw 0x1540, 0xc90d, 0x157f, 0xc90d, 0x21, 0 + .dw 0x15c0, 0xc90d, 0x15ff, 0xc90d, 0x21, 0 + .dw 0x1640, 0xc90d, 0x167f, 0xc90d, 0x21, 0 + .dw 0x16c0, 0xc90d, 0x16ff, 0xc90d, 0x21, 0 + .dw 0x1740, 0xc90d, 0x177f, 0xc90d, 0x21, 0 + .dw 0x17c0, 0xc90d, 0x17ff, 0xc90d, 0x21, 0 + .dw 0x1840, 0xc90d, 0x187f, 0xc90d, 0x21, 0 + .dw 0x18c0, 0xc90d, 0x18ff, 0xc90d, 0x21, 0 + .dw 0x1940, 0xc90d, 0x197f, 0xc90d, 0x21, 0 + .dw 0x19c0, 0xc90d, 0x1fff, 0xc90d, 0x21, 0 + .dw 0x2040, 0xc90d, 0x207f, 0xc90d, 0x21, 0 + .dw 0x20c0, 0xc90d, 0x20ff, 0xc90d, 0x21, 0 + .dw 0x2140, 0xc90d, 0x217f, 0xc90d, 0x21, 0 + .dw 0x21c0, 0xc90d, 0x21ff, 0xc90d, 0x21, 0 + .dw 0x2240, 0xc90d, 0x227f, 0xc90d, 0x21, 0 + .dw 0x22c0, 0xc90d, 0x22ff, 0xc90d, 0x21, 0 + .dw 0x2340, 0xc90d, 0x237f, 0xc90d, 0x21, 0 + .dw 0x23c0, 0xc90d, 0x23ff, 0xc90d, 0x21, 0 + .dw 0x2440, 0xc90d, 0x247f, 0xc90d, 0x21, 0 + .dw 0x24c0, 0xc90d, 0x24ff, 0xc90d, 0x21, 0 + .dw 0x2540, 0xc90d, 0x257f, 0xc90d, 0x21, 0 + .dw 0x25c0, 0xc90d, 0x25ff, 0xc90d, 0x21, 0 + .dw 0x2640, 0xc90d, 0x267f, 0xc90d, 0x21, 0 + .dw 0x26c0, 0xc90d, 0x26ff, 0xc90d, 0x21, 0 + .dw 0x2740, 0xc90d, 0x277f, 0xc90d, 0x21, 0 + .dw 0x27c0, 0xc90d, 0x27ff, 0xc90d, 0x21, 0 + .dw 0x2840, 0xc90d, 0x287f, 0xc90d, 0x21, 0 + .dw 0x28c0, 0xc90d, 0x28ff, 0xc90d, 0x21, 0 + .dw 0x2940, 0xc90d, 0x297f, 0xc90d, 0x21, 0 + .dw 0x29c0, 0xc90d, 0x29ff, 0xc90d, 0x21, 0 + .dw 0x2a40, 0xc90d, 0x2a7f, 0xc90d, 0x21, 0 + .dw 0x2ac0, 0xc90d, 0x2aff, 0xc90d, 0x21, 0 + .dw 0x2b40, 0xc90d, 0x2b7f, 0xc90d, 0x21, 0 + .dw 0x2bc0, 0xc90d, 0x2bff, 0xc90d, 0x21, 0 + .dw 0x2c40, 0xc90d, 0x2c7f, 0xc90d, 0x21, 0 + .dw 0x2cc0, 0xc90d, 0x2cff, 0xc90d, 0x21, 0 + .dw 0x2d40, 0xc90d, 0x2d7f, 0xc90d, 0x21, 0 + .dw 0x2dc0, 0xc90d, 0x2dff, 0xc90d, 0x21, 0 + .dw 0x2e40, 0xc90d, 0x2e7f, 0xc90d, 0x21, 0 + .dw 0x2ec0, 0xc90d, 0x2eff, 0xc90d, 0x21, 0 + .dw 0x2f40, 0xc90d, 0x2f7f, 0xc90d, 0x21, 0 + .dw 0x2fc0, 0xc90d, 0x2fff, 0xc90d, 0x21, 0 + .dw 0x3040, 0xc90d, 0x307f, 0xc90d, 0x21, 0 + .dw 0x30c0, 0xc90d, 0x30ff, 0xc90d, 0x21, 0 + .dw 0x3140, 0xc90d, 0x317f, 0xc90d, 0x21, 0 + .dw 0x31c0, 0xc90d, 0x31ff, 0xc90d, 0x21, 0 + .dw 0x3240, 0xc90d, 0x327f, 0xc90d, 0x21, 0 + .dw 0x32c0, 0xc90d, 0x32ff, 0xc90d, 0x21, 0 + .dw 0x3340, 0xc90d, 0x337f, 0xc90d, 0x21, 0 + .dw 0x33c0, 0xc90d, 0x33ff, 0xc90d, 0x21, 0 + .dw 0x3440, 0xc90d, 0x347f, 0xc90d, 0x21, 0 + .dw 0x34c0, 0xc90d, 0x34ff, 0xc90d, 0x21, 0 + .dw 0x3540, 0xc90d, 0x357f, 0xc90d, 0x21, 0 + .dw 0x35c0, 0xc90d, 0x35ff, 0xc90d, 0x21, 0 + .dw 0x3640, 0xc90d, 0x367f, 0xc90d, 0x21, 0 + .dw 0x36c0, 0xc90d, 0x36ff, 0xc90d, 0x21, 0 + .dw 0x3740, 0xc90d, 0x377f, 0xc90d, 0x21, 0 + .dw 0x37c0, 0xc90d, 0x37ff, 0xc90d, 0x21, 0 + .dw 0x3840, 0xc90d, 0x387f, 0xc90d, 0x21, 0 + .dw 0x38c0, 0xc90d, 0x38ff, 0xc90d, 0x21, 0 + .dw 0x3940, 0xc90d, 0x397f, 0xc90d, 0x21, 0 + .dw 0x39c0, 0xc90d, 0x3fff, 0xc90d, 0x21, 0 + .dw 0x4040, 0xc90d, 0x407f, 0xc90d, 0x21, 0 + .dw 0x40c0, 0xc90d, 0x40ff, 0xc90d, 0x21, 0 + .dw 0x4140, 0xc90d, 0x417f, 0xc90d, 0x21, 0 + .dw 0x41c0, 0xc90d, 0x41ff, 0xc90d, 0x21, 0 + .dw 0x4240, 0xc90d, 0x427f, 0xc90d, 0x21, 0 + .dw 0x42c0, 0xc90d, 0x42ff, 0xc90d, 0x21, 0 + .dw 0x4340, 0xc90d, 0x437f, 0xc90d, 0x21, 0 + .dw 0x43c0, 0xc90d, 0x43ff, 0xc90d, 0x21, 0 + .dw 0x4440, 0xc90d, 0x447f, 0xc90d, 0x21, 0 + .dw 0x44c0, 0xc90d, 0x44ff, 0xc90d, 0x21, 0 + .dw 0x4540, 0xc90d, 0x457f, 0xc90d, 0x21, 0 + .dw 0x45c0, 0xc90d, 0x45ff, 0xc90d, 0x21, 0 + .dw 0x4640, 0xc90d, 0x467f, 0xc90d, 0x21, 0 + .dw 0x46c0, 0xc90d, 0x46ff, 0xc90d, 0x21, 0 + .dw 0x4740, 0xc90d, 0x477f, 0xc90d, 0x21, 0 + .dw 0x47c0, 0xc90d, 0x47ff, 0xc90d, 0x21, 0 + .dw 0x4840, 0xc90d, 0x487f, 0xc90d, 0x21, 0 + .dw 0x48c0, 0xc90d, 0x48ff, 0xc90d, 0x21, 0 + .dw 0x4940, 0xc90d, 0x497f, 0xc90d, 0x21, 0 + .dw 0x49c0, 0xc90d, 0x49ff, 0xc90d, 0x21, 0 + .dw 0x4a40, 0xc90d, 0x4a7f, 0xc90d, 0x21, 0 + .dw 0x4ac0, 0xc90d, 0x4aff, 0xc90d, 0x21, 0 + .dw 0x4b40, 0xc90d, 0x4b7f, 0xc90d, 0x21, 0 + .dw 0x4bc0, 0xc90d, 0x4bff, 0xc90d, 0x21, 0 + .dw 0x4c40, 0xc90d, 0x4c7f, 0xc90d, 0x21, 0 + .dw 0x4cc0, 0xc90d, 0x4cff, 0xc90d, 0x21, 0 + .dw 0x4d40, 0xc90d, 0x4d7f, 0xc90d, 0x21, 0 + .dw 0x4dc0, 0xc90d, 0x4dff, 0xc90d, 0x21, 0 + .dw 0x4e40, 0xc90d, 0x4e7f, 0xc90d, 0x21, 0 + .dw 0x4ec0, 0xc90d, 0x4eff, 0xc90d, 0x21, 0 + .dw 0x4f40, 0xc90d, 0x4f7f, 0xc90d, 0x21, 0 + .dw 0x4fc0, 0xc90d, 0x4fff, 0xc90d, 0x21, 0 + .dw 0x5040, 0xc90d, 0x507f, 0xc90d, 0x21, 0 + .dw 0x50c0, 0xc90d, 0x50ff, 0xc90d, 0x21, 0 + .dw 0x5140, 0xc90d, 0x517f, 0xc90d, 0x21, 0 + .dw 0x51c0, 0xc90d, 0x51ff, 0xc90d, 0x21, 0 + .dw 0x5240, 0xc90d, 0x527f, 0xc90d, 0x21, 0 + .dw 0x52c0, 0xc90d, 0x52ff, 0xc90d, 0x21, 0 + .dw 0x5340, 0xc90d, 0x537f, 0xc90d, 0x21, 0 + .dw 0x53c0, 0xc90d, 0x53ff, 0xc90d, 0x21, 0 + .dw 0x5440, 0xc90d, 0x547f, 0xc90d, 0x21, 0 + .dw 0x54c0, 0xc90d, 0x54ff, 0xc90d, 0x21, 0 + .dw 0x5540, 0xc90d, 0x557f, 0xc90d, 0x21, 0 + .dw 0x55c0, 0xc90d, 0x55ff, 0xc90d, 0x21, 0 + .dw 0x5640, 0xc90d, 0x567f, 0xc90d, 0x21, 0 + .dw 0x56c0, 0xc90d, 0x56ff, 0xc90d, 0x21, 0 + .dw 0x5740, 0xc90d, 0x577f, 0xc90d, 0x21, 0 + .dw 0x57c0, 0xc90d, 0x57ff, 0xc90d, 0x21, 0 + .dw 0x5840, 0xc90d, 0x587f, 0xc90d, 0x21, 0 + .dw 0x58c0, 0xc90d, 0x58ff, 0xc90d, 0x21, 0 + .dw 0x5940, 0xc90d, 0x597f, 0xc90d, 0x21, 0 + .dw 0x59c0, 0xc90d, 0x5fff, 0xc90d, 0x21, 0 + .dw 0x6040, 0xc90d, 0x607f, 0xc90d, 0x21, 0 + .dw 0x60c0, 0xc90d, 0x60ff, 0xc90d, 0x21, 0 + .dw 0x6140, 0xc90d, 0x617f, 0xc90d, 0x21, 0 + .dw 0x61c0, 0xc90d, 0x61ff, 0xc90d, 0x21, 0 + .dw 0x6240, 0xc90d, 0x627f, 0xc90d, 0x21, 0 + .dw 0x62c0, 0xc90d, 0x62ff, 0xc90d, 0x21, 0 + .dw 0x6340, 0xc90d, 0x637f, 0xc90d, 0x21, 0 + .dw 0x63c0, 0xc90d, 0x63ff, 0xc90d, 0x21, 0 + .dw 0x6440, 0xc90d, 0x647f, 0xc90d, 0x21, 0 + .dw 0x64c0, 0xc90d, 0x64ff, 0xc90d, 0x21, 0 + .dw 0x6540, 0xc90d, 0x657f, 0xc90d, 0x21, 0 + .dw 0x65c0, 0xc90d, 0x65ff, 0xc90d, 0x21, 0 + .dw 0x6640, 0xc90d, 0x667f, 0xc90d, 0x21, 0 + .dw 0x66c0, 0xc90d, 0x66ff, 0xc90d, 0x21, 0 + .dw 0x6740, 0xc90d, 0x677f, 0xc90d, 0x21, 0 + .dw 0x67c0, 0xc90d, 0x67ff, 0xc90d, 0x21, 0 + .dw 0x6840, 0xc90d, 0x687f, 0xc90d, 0x21, 0 + .dw 0x68c0, 0xc90d, 0x68ff, 0xc90d, 0x21, 0 + .dw 0x6940, 0xc90d, 0x697f, 0xc90d, 0x21, 0 + .dw 0x69c0, 0xc90d, 0x69ff, 0xc90d, 0x21, 0 + .dw 0x6a40, 0xc90d, 0x6a7f, 0xc90d, 0x21, 0 + .dw 0x6ac0, 0xc90d, 0x6aff, 0xc90d, 0x21, 0 + .dw 0x6b40, 0xc90d, 0x6b7f, 0xc90d, 0x21, 0 + .dw 0x6bc0, 0xc90d, 0x6bff, 0xc90d, 0x21, 0 + .dw 0x6c40, 0xc90d, 0x6c7f, 0xc90d, 0x21, 0 + .dw 0x6cc0, 0xc90d, 0x6cff, 0xc90d, 0x21, 0 + .dw 0x6d40, 0xc90d, 0x6d7f, 0xc90d, 0x21, 0 + .dw 0x6dc0, 0xc90d, 0x6dff, 0xc90d, 0x21, 0 + .dw 0x6e40, 0xc90d, 0x6e7f, 0xc90d, 0x21, 0 + .dw 0x6ec0, 0xc90d, 0x6eff, 0xc90d, 0x21, 0 + .dw 0x6f40, 0xc90d, 0x6f7f, 0xc90d, 0x21, 0 + .dw 0x6fc0, 0xc90d, 0x6fff, 0xc90d, 0x21, 0 + .dw 0x7040, 0xc90d, 0x707f, 0xc90d, 0x21, 0 + .dw 0x70c0, 0xc90d, 0x70ff, 0xc90d, 0x21, 0 + .dw 0x7140, 0xc90d, 0x717f, 0xc90d, 0x21, 0 + .dw 0x71c0, 0xc90d, 0x71ff, 0xc90d, 0x21, 0 + .dw 0x7240, 0xc90d, 0x727f, 0xc90d, 0x21, 0 + .dw 0x72c0, 0xc90d, 0x72ff, 0xc90d, 0x21, 0 + .dw 0x7340, 0xc90d, 0x737f, 0xc90d, 0x21, 0 + .dw 0x73c0, 0xc90d, 0x73ff, 0xc90d, 0x21, 0 + .dw 0x7440, 0xc90d, 0x747f, 0xc90d, 0x21, 0 + .dw 0x74c0, 0xc90d, 0x74ff, 0xc90d, 0x21, 0 + .dw 0x7540, 0xc90d, 0x757f, 0xc90d, 0x21, 0 + .dw 0x75c0, 0xc90d, 0x75ff, 0xc90d, 0x21, 0 + .dw 0x7640, 0xc90d, 0x767f, 0xc90d, 0x21, 0 + .dw 0x76c0, 0xc90d, 0x76ff, 0xc90d, 0x21, 0 + .dw 0x7740, 0xc90d, 0x777f, 0xc90d, 0x21, 0 + .dw 0x77c0, 0xc90d, 0x77ff, 0xc90d, 0x21, 0 + .dw 0x7840, 0xc90d, 0x787f, 0xc90d, 0x21, 0 + .dw 0x78c0, 0xc90d, 0x78ff, 0xc90d, 0x21, 0 + .dw 0x7940, 0xc90d, 0x797f, 0xc90d, 0x21, 0 + .dw 0x79c0, 0xc90d, 0x7fff, 0xc90d, 0x21, 0 + .dw 0x8040, 0xc90d, 0x807f, 0xc90d, 0x21, 0 + .dw 0x80c0, 0xc90d, 0x80ff, 0xc90d, 0x21, 0 + .dw 0x8140, 0xc90d, 0x817f, 0xc90d, 0x21, 0 + .dw 0x81c0, 0xc90d, 0x81ff, 0xc90d, 0x21, 0 + .dw 0x8240, 0xc90d, 0x827f, 0xc90d, 0x21, 0 + .dw 0x82c0, 0xc90d, 0x82ff, 0xc90d, 0x21, 0 + .dw 0x8340, 0xc90d, 0x837f, 0xc90d, 0x21, 0 + .dw 0x83c0, 0xc90d, 0x83ff, 0xc90d, 0x21, 0 + .dw 0x8440, 0xc90d, 0x847f, 0xc90d, 0x21, 0 + .dw 0x84c0, 0xc90d, 0x84ff, 0xc90d, 0x21, 0 + .dw 0x8540, 0xc90d, 0x857f, 0xc90d, 0x21, 0 + .dw 0x85c0, 0xc90d, 0x85ff, 0xc90d, 0x21, 0 + .dw 0x8640, 0xc90d, 0x867f, 0xc90d, 0x21, 0 + .dw 0x86c0, 0xc90d, 0x86ff, 0xc90d, 0x21, 0 + .dw 0x8740, 0xc90d, 0x877f, 0xc90d, 0x21, 0 + .dw 0x87c0, 0xc90d, 0x87ff, 0xc90d, 0x21, 0 + .dw 0x8840, 0xc90d, 0x887f, 0xc90d, 0x21, 0 + .dw 0x88c0, 0xc90d, 0x88ff, 0xc90d, 0x21, 0 + .dw 0x8940, 0xc90d, 0x897f, 0xc90d, 0x21, 0 + .dw 0x89c0, 0xc90d, 0x89ff, 0xc90d, 0x21, 0 + .dw 0x8a40, 0xc90d, 0x8a7f, 0xc90d, 0x21, 0 + .dw 0x8ac0, 0xc90d, 0x8aff, 0xc90d, 0x21, 0 + .dw 0x8b40, 0xc90d, 0x8b7f, 0xc90d, 0x21, 0 + .dw 0x8bc0, 0xc90d, 0x8bff, 0xc90d, 0x21, 0 + .dw 0x8c40, 0xc90d, 0x8c7f, 0xc90d, 0x21, 0 + .dw 0x8cc0, 0xc90d, 0x8cff, 0xc90d, 0x21, 0 + .dw 0x8d40, 0xc90d, 0x8d7f, 0xc90d, 0x21, 0 + .dw 0x8dc0, 0xc90d, 0x8dff, 0xc90d, 0x21, 0 + .dw 0x8e40, 0xc90d, 0x8e7f, 0xc90d, 0x21, 0 + .dw 0x8ec0, 0xc90d, 0x8eff, 0xc90d, 0x21, 0 + .dw 0x8f40, 0xc90d, 0x8f7f, 0xc90d, 0x21, 0 + .dw 0x8fc0, 0xc90d, 0x8fff, 0xc90d, 0x21, 0 + .dw 0x9040, 0xc90d, 0x907f, 0xc90d, 0x21, 0 + .dw 0x90c0, 0xc90d, 0x90ff, 0xc90d, 0x21, 0 + .dw 0x9140, 0xc90d, 0x917f, 0xc90d, 0x21, 0 + .dw 0x91c0, 0xc90d, 0x91ff, 0xc90d, 0x21, 0 + .dw 0x9240, 0xc90d, 0x927f, 0xc90d, 0x21, 0 + .dw 0x92c0, 0xc90d, 0x92ff, 0xc90d, 0x21, 0 + .dw 0x9340, 0xc90d, 0x937f, 0xc90d, 0x21, 0 + .dw 0x93c0, 0xc90d, 0x93ff, 0xc90d, 0x21, 0 + .dw 0x9440, 0xc90d, 0x947f, 0xc90d, 0x21, 0 + .dw 0x94c0, 0xc90d, 0x94ff, 0xc90d, 0x21, 0 + .dw 0x9540, 0xc90d, 0x957f, 0xc90d, 0x21, 0 + .dw 0x95c0, 0xc90d, 0x95ff, 0xc90d, 0x21, 0 + .dw 0x9640, 0xc90d, 0x967f, 0xc90d, 0x21, 0 + .dw 0x96c0, 0xc90d, 0x96ff, 0xc90d, 0x21, 0 + .dw 0x9740, 0xc90d, 0x977f, 0xc90d, 0x21, 0 + .dw 0x97c0, 0xc90d, 0x97ff, 0xc90d, 0x21, 0 + .dw 0x9840, 0xc90d, 0x987f, 0xc90d, 0x21, 0 + .dw 0x98c0, 0xc90d, 0x98ff, 0xc90d, 0x21, 0 + .dw 0x9940, 0xc90d, 0x997f, 0xc90d, 0x21, 0 + .dw 0x99c0, 0xc90d, 0x9fff, 0xc90d, 0x21, 0 + .dw 0xa040, 0xc90d, 0xa07f, 0xc90d, 0x21, 0 + .dw 0xa0c0, 0xc90d, 0xa0ff, 0xc90d, 0x21, 0 + .dw 0xa140, 0xc90d, 0xa17f, 0xc90d, 0x21, 0 + .dw 0xa1c0, 0xc90d, 0xa1ff, 0xc90d, 0x21, 0 + .dw 0xa240, 0xc90d, 0xa27f, 0xc90d, 0x21, 0 + .dw 0xa2c0, 0xc90d, 0xa2ff, 0xc90d, 0x21, 0 + .dw 0xa340, 0xc90d, 0xa37f, 0xc90d, 0x21, 0 + .dw 0xa3c0, 0xc90d, 0xa3ff, 0xc90d, 0x21, 0 + .dw 0xa440, 0xc90d, 0xa47f, 0xc90d, 0x21, 0 + .dw 0xa4c0, 0xc90d, 0xa4ff, 0xc90d, 0x21, 0 + .dw 0xa540, 0xc90d, 0xa57f, 0xc90d, 0x21, 0 + .dw 0xa5c0, 0xc90d, 0xa5ff, 0xc90d, 0x21, 0 + .dw 0xa640, 0xc90d, 0xa67f, 0xc90d, 0x21, 0 + .dw 0xa6c0, 0xc90d, 0xa6ff, 0xc90d, 0x21, 0 + .dw 0xa740, 0xc90d, 0xa77f, 0xc90d, 0x21, 0 + .dw 0xa7c0, 0xc90d, 0xa7ff, 0xc90d, 0x21, 0 + .dw 0xa840, 0xc90d, 0xa87f, 0xc90d, 0x21, 0 + .dw 0xa8c0, 0xc90d, 0xa8ff, 0xc90d, 0x21, 0 + .dw 0xa940, 0xc90d, 0xa97f, 0xc90d, 0x21, 0 + .dw 0xa9c0, 0xc90d, 0xa9ff, 0xc90d, 0x21, 0 + .dw 0xaa40, 0xc90d, 0xaa7f, 0xc90d, 0x21, 0 + .dw 0xaac0, 0xc90d, 0xaaff, 0xc90d, 0x21, 0 + .dw 0xab40, 0xc90d, 0xab7f, 0xc90d, 0x21, 0 + .dw 0xabc0, 0xc90d, 0xabff, 0xc90d, 0x21, 0 + .dw 0xac40, 0xc90d, 0xac7f, 0xc90d, 0x21, 0 + .dw 0xacc0, 0xc90d, 0xacff, 0xc90d, 0x21, 0 + .dw 0xad40, 0xc90d, 0xad7f, 0xc90d, 0x21, 0 + .dw 0xadc0, 0xc90d, 0xadff, 0xc90d, 0x21, 0 + .dw 0xae40, 0xc90d, 0xae7f, 0xc90d, 0x21, 0 + .dw 0xaec0, 0xc90d, 0xaeff, 0xc90d, 0x21, 0 + .dw 0xaf40, 0xc90d, 0xaf7f, 0xc90d, 0x21, 0 + .dw 0xafc0, 0xc90d, 0xafff, 0xc90d, 0x21, 0 + .dw 0xb040, 0xc90d, 0xb07f, 0xc90d, 0x21, 0 + .dw 0xb0c0, 0xc90d, 0xb0ff, 0xc90d, 0x21, 0 + .dw 0xb140, 0xc90d, 0xb17f, 0xc90d, 0x21, 0 + .dw 0xb1c0, 0xc90d, 0xb1ff, 0xc90d, 0x21, 0 + .dw 0xb240, 0xc90d, 0xb27f, 0xc90d, 0x21, 0 + .dw 0xb2c0, 0xc90d, 0xb2ff, 0xc90d, 0x21, 0 + .dw 0xb340, 0xc90d, 0xb37f, 0xc90d, 0x21, 0 + .dw 0xb3c0, 0xc90d, 0xb3ff, 0xc90d, 0x21, 0 + .dw 0xb440, 0xc90d, 0xb47f, 0xc90d, 0x21, 0 + .dw 0xb4c0, 0xc90d, 0xb4ff, 0xc90d, 0x21, 0 + .dw 0xb540, 0xc90d, 0xb57f, 0xc90d, 0x21, 0 + .dw 0xb5c0, 0xc90d, 0xb5ff, 0xc90d, 0x21, 0 + .dw 0xb640, 0xc90d, 0xb67f, 0xc90d, 0x21, 0 + .dw 0xb6c0, 0xc90d, 0xb6ff, 0xc90d, 0x21, 0 + .dw 0xb740, 0xc90d, 0xb77f, 0xc90d, 0x21, 0 + .dw 0xb7c0, 0xc90d, 0xb7ff, 0xc90d, 0x21, 0 + .dw 0xb840, 0xc90d, 0xb87f, 0xc90d, 0x21, 0 + .dw 0xb8c0, 0xc90d, 0xb8ff, 0xc90d, 0x21, 0 + .dw 0xb940, 0xc90d, 0xb97f, 0xc90d, 0x21, 0 + .dw 0xb9c0, 0xc90d, 0xbfff, 0xc90d, 0x21, 0 + .dw 0xc040, 0xc90d, 0xc07f, 0xc90d, 0x21, 0 + .dw 0xc0c0, 0xc90d, 0xc0ff, 0xc90d, 0x21, 0 + .dw 0xc140, 0xc90d, 0xc17f, 0xc90d, 0x21, 0 + .dw 0xc1c0, 0xc90d, 0xc1ff, 0xc90d, 0x21, 0 + .dw 0xc240, 0xc90d, 0xc27f, 0xc90d, 0x21, 0 + .dw 0xc2c0, 0xc90d, 0xc2ff, 0xc90d, 0x21, 0 + .dw 0xc340, 0xc90d, 0xc37f, 0xc90d, 0x21, 0 + .dw 0xc3c0, 0xc90d, 0xc3ff, 0xc90d, 0x21, 0 + .dw 0xc440, 0xc90d, 0xc47f, 0xc90d, 0x21, 0 + .dw 0xc4c0, 0xc90d, 0xc4ff, 0xc90d, 0x21, 0 + .dw 0xc540, 0xc90d, 0xc57f, 0xc90d, 0x21, 0 + .dw 0xc5c0, 0xc90d, 0xc5ff, 0xc90d, 0x21, 0 + .dw 0xc640, 0xc90d, 0xc67f, 0xc90d, 0x21, 0 + .dw 0xc6c0, 0xc90d, 0xc6ff, 0xc90d, 0x21, 0 + .dw 0xc740, 0xc90d, 0xc77f, 0xc90d, 0x21, 0 + .dw 0xc7c0, 0xc90d, 0xc7ff, 0xc90d, 0x21, 0 + .dw 0xc840, 0xc90d, 0xc87f, 0xc90d, 0x21, 0 + .dw 0xc8c0, 0xc90d, 0xc8ff, 0xc90d, 0x21, 0 + .dw 0xc940, 0xc90d, 0xc97f, 0xc90d, 0x21, 0 + .dw 0xc9c0, 0xc90d, 0xc9ff, 0xc90d, 0x21, 0 + .dw 0xca40, 0xc90d, 0xca7f, 0xc90d, 0x21, 0 + .dw 0xcac0, 0xc90d, 0xcaff, 0xc90d, 0x21, 0 + .dw 0xcb40, 0xc90d, 0xcb7f, 0xc90d, 0x21, 0 + .dw 0xcbc0, 0xc90d, 0xcbff, 0xc90d, 0x21, 0 + .dw 0xcc40, 0xc90d, 0xcc7f, 0xc90d, 0x21, 0 + .dw 0xccc0, 0xc90d, 0xccff, 0xc90d, 0x21, 0 + .dw 0xcd40, 0xc90d, 0xcd7f, 0xc90d, 0x21, 0 + .dw 0xcdc0, 0xc90d, 0xcdff, 0xc90d, 0x21, 0 + .dw 0xce40, 0xc90d, 0xce7f, 0xc90d, 0x21, 0 + .dw 0xcec0, 0xc90d, 0xceff, 0xc90d, 0x21, 0 + .dw 0xcf40, 0xc90d, 0xcf7f, 0xc90d, 0x21, 0 + .dw 0xcfc0, 0xc90d, 0xcfff, 0xc90d, 0x21, 0 + .dw 0xd040, 0xc90d, 0xd07f, 0xc90d, 0x21, 0 + .dw 0xd0c0, 0xc90d, 0xd0ff, 0xc90d, 0x21, 0 + .dw 0xd140, 0xc90d, 0xd17f, 0xc90d, 0x21, 0 + .dw 0xd1c0, 0xc90d, 0xd1ff, 0xc90d, 0x21, 0 + .dw 0xd240, 0xc90d, 0xd27f, 0xc90d, 0x21, 0 + .dw 0xd2c0, 0xc90d, 0xd2ff, 0xc90d, 0x21, 0 + .dw 0xd340, 0xc90d, 0xd37f, 0xc90d, 0x21, 0 + .dw 0xd3c0, 0xc90d, 0xd3ff, 0xc90d, 0x21, 0 + .dw 0xd440, 0xc90d, 0xd47f, 0xc90d, 0x21, 0 + .dw 0xd4c0, 0xc90d, 0xd4ff, 0xc90d, 0x21, 0 + .dw 0xd540, 0xc90d, 0xd57f, 0xc90d, 0x21, 0 + .dw 0xd5c0, 0xc90d, 0xd5ff, 0xc90d, 0x21, 0 + .dw 0xd640, 0xc90d, 0xd67f, 0xc90d, 0x21, 0 + .dw 0xd6c0, 0xc90d, 0xd6ff, 0xc90d, 0x21, 0 + .dw 0xd740, 0xc90d, 0xd77f, 0xc90d, 0x21, 0 + .dw 0xd7c0, 0xc90d, 0xd7ff, 0xc90d, 0x21, 0 + .dw 0xd840, 0xc90d, 0xd87f, 0xc90d, 0x21, 0 + .dw 0xd8c0, 0xc90d, 0xd8ff, 0xc90d, 0x21, 0 + .dw 0xd940, 0xc90d, 0xd97f, 0xc90d, 0x21, 0 + .dw 0xd9c0, 0xc90d, 0xdfff, 0xc90d, 0x21, 0 + .dw 0xe040, 0xc90d, 0xe07f, 0xc90d, 0x21, 0 + .dw 0xe0c0, 0xc90d, 0xe0ff, 0xc90d, 0x21, 0 + .dw 0xe140, 0xc90d, 0xe17f, 0xc90d, 0x21, 0 + .dw 0xe1c0, 0xc90d, 0xe1ff, 0xc90d, 0x21, 0 + .dw 0xe240, 0xc90d, 0xe27f, 0xc90d, 0x21, 0 + .dw 0xe2c0, 0xc90d, 0xe2ff, 0xc90d, 0x21, 0 + .dw 0xe340, 0xc90d, 0xe37f, 0xc90d, 0x21, 0 + .dw 0xe3c0, 0xc90d, 0xe3ff, 0xc90d, 0x21, 0 + .dw 0xe440, 0xc90d, 0xe47f, 0xc90d, 0x21, 0 + .dw 0xe4c0, 0xc90d, 0xe4ff, 0xc90d, 0x21, 0 + .dw 0xe540, 0xc90d, 0xe57f, 0xc90d, 0x21, 0 + .dw 0xe5c0, 0xc90d, 0xe5ff, 0xc90d, 0x21, 0 + .dw 0xe640, 0xc90d, 0xe67f, 0xc90d, 0x21, 0 + .dw 0xe6c0, 0xc90d, 0xe6ff, 0xc90d, 0x21, 0 + .dw 0xe740, 0xc90d, 0xe77f, 0xc90d, 0x21, 0 + .dw 0xe7c0, 0xc90d, 0xe7ff, 0xc90d, 0x21, 0 + .dw 0xe840, 0xc90d, 0xe87f, 0xc90d, 0x21, 0 + .dw 0xe8c0, 0xc90d, 0xe8ff, 0xc90d, 0x21, 0 + .dw 0xe940, 0xc90d, 0xe97f, 0xc90d, 0x21, 0 + .dw 0xe9c0, 0xc90d, 0xe9ff, 0xc90d, 0x21, 0 + .dw 0xea40, 0xc90d, 0xea7f, 0xc90d, 0x21, 0 + .dw 0xeac0, 0xc90d, 0xeaff, 0xc90d, 0x21, 0 + .dw 0xeb40, 0xc90d, 0xeb7f, 0xc90d, 0x21, 0 + .dw 0xebc0, 0xc90d, 0xebff, 0xc90d, 0x21, 0 + .dw 0xec40, 0xc90d, 0xec7f, 0xc90d, 0x21, 0 + .dw 0xecc0, 0xc90d, 0xecff, 0xc90d, 0x21, 0 + .dw 0xed40, 0xc90d, 0xed7f, 0xc90d, 0x21, 0 + .dw 0xedc0, 0xc90d, 0xedff, 0xc90d, 0x21, 0 + .dw 0xee40, 0xc90d, 0xee7f, 0xc90d, 0x21, 0 + .dw 0xeec0, 0xc90d, 0xeeff, 0xc90d, 0x21, 0 + .dw 0xef40, 0xc90d, 0xef7f, 0xc90d, 0x21, 0 + .dw 0xefc0, 0xc90d, 0xefff, 0xc90d, 0x21, 0 + .dw 0xf040, 0xc90d, 0xf07f, 0xc90d, 0x21, 0 + .dw 0xf0c0, 0xc90d, 0xf0ff, 0xc90d, 0x21, 0 + .dw 0xf140, 0xc90d, 0xf17f, 0xc90d, 0x21, 0 + .dw 0xf1c0, 0xc90d, 0xf1ff, 0xc90d, 0x21, 0 + .dw 0xf240, 0xc90d, 0xf27f, 0xc90d, 0x21, 0 + .dw 0xf2c0, 0xc90d, 0xf2ff, 0xc90d, 0x21, 0 + .dw 0xf340, 0xc90d, 0xf37f, 0xc90d, 0x21, 0 + .dw 0xf3c0, 0xc90d, 0xf3ff, 0xc90d, 0x21, 0 + .dw 0xf440, 0xc90d, 0xf47f, 0xc90d, 0x21, 0 + .dw 0xf4c0, 0xc90d, 0xf4ff, 0xc90d, 0x21, 0 + .dw 0xf540, 0xc90d, 0xf57f, 0xc90d, 0x21, 0 + .dw 0xf5c0, 0xc90d, 0xf5ff, 0xc90d, 0x21, 0 + .dw 0xf640, 0xc90d, 0xf67f, 0xc90d, 0x21, 0 + .dw 0xf6c0, 0xc90d, 0xf6ff, 0xc90d, 0x21, 0 + .dw 0xf740, 0xc90d, 0xf77f, 0xc90d, 0x21, 0 + .dw 0xf7c0, 0xc90d, 0xf7ff, 0xc90d, 0x21, 0 + .dw 0xf840, 0xc90d, 0xf87f, 0xc90d, 0x21, 0 + .dw 0xf8c0, 0xc90d, 0xf8ff, 0xc90d, 0x21, 0 + .dw 0xf940, 0xc90d, 0xf97f, 0xc90d, 0x21, 0 + .dw 0xf9c0, 0xc90d, 0xffff, 0xc90d, 0x21, 0 + .dw 0x0040, 0xc90e, 0x007f, 0xc90e, 0x21, 0 + .dw 0x00c0, 0xc90e, 0x00ff, 0xc90e, 0x21, 0 + .dw 0x0140, 0xc90e, 0x017f, 0xc90e, 0x21, 0 + .dw 0x01c0, 0xc90e, 0x01ff, 0xc90e, 0x21, 0 + .dw 0x0240, 0xc90e, 0x027f, 0xc90e, 0x21, 0 + .dw 0x02c0, 0xc90e, 0x02ff, 0xc90e, 0x21, 0 + .dw 0x0340, 0xc90e, 0x037f, 0xc90e, 0x21, 0 + .dw 0x03c0, 0xc90e, 0x03ff, 0xc90e, 0x21, 0 + .dw 0x0440, 0xc90e, 0x047f, 0xc90e, 0x21, 0 + .dw 0x04c0, 0xc90e, 0x04ff, 0xc90e, 0x21, 0 + .dw 0x0540, 0xc90e, 0x057f, 0xc90e, 0x21, 0 + .dw 0x05c0, 0xc90e, 0x05ff, 0xc90e, 0x21, 0 + .dw 0x0640, 0xc90e, 0x067f, 0xc90e, 0x21, 0 + .dw 0x06c0, 0xc90e, 0x06ff, 0xc90e, 0x21, 0 + .dw 0x0740, 0xc90e, 0x077f, 0xc90e, 0x21, 0 + .dw 0x07c0, 0xc90e, 0x07ff, 0xc90e, 0x21, 0 + .dw 0x0840, 0xc90e, 0x087f, 0xc90e, 0x21, 0 + .dw 0x08c0, 0xc90e, 0x08ff, 0xc90e, 0x21, 0 + .dw 0x0940, 0xc90e, 0x097f, 0xc90e, 0x21, 0 + .dw 0x09c0, 0xc90e, 0x09ff, 0xc90e, 0x21, 0 + .dw 0x0a40, 0xc90e, 0x0a7f, 0xc90e, 0x21, 0 + .dw 0x0ac0, 0xc90e, 0x0aff, 0xc90e, 0x21, 0 + .dw 0x0b40, 0xc90e, 0x0b7f, 0xc90e, 0x21, 0 + .dw 0x0bc0, 0xc90e, 0x0bff, 0xc90e, 0x21, 0 + .dw 0x0c40, 0xc90e, 0x0c7f, 0xc90e, 0x21, 0 + .dw 0x0cc0, 0xc90e, 0x0cff, 0xc90e, 0x21, 0 + .dw 0x0d40, 0xc90e, 0x0d7f, 0xc90e, 0x21, 0 + .dw 0x0dc0, 0xc90e, 0x0dff, 0xc90e, 0x21, 0 + .dw 0x0e40, 0xc90e, 0x0e7f, 0xc90e, 0x21, 0 + .dw 0x0ec0, 0xc90e, 0x0eff, 0xc90e, 0x21, 0 + .dw 0x0f40, 0xc90e, 0x0f7f, 0xc90e, 0x21, 0 + .dw 0x0fc0, 0xc90e, 0x0fff, 0xc90e, 0x21, 0 + .dw 0x1040, 0xc90e, 0x107f, 0xc90e, 0x21, 0 + .dw 0x10c0, 0xc90e, 0x10ff, 0xc90e, 0x21, 0 + .dw 0x1140, 0xc90e, 0x117f, 0xc90e, 0x21, 0 + .dw 0x11c0, 0xc90e, 0x11ff, 0xc90e, 0x21, 0 + .dw 0x1240, 0xc90e, 0x127f, 0xc90e, 0x21, 0 + .dw 0x12c0, 0xc90e, 0x12ff, 0xc90e, 0x21, 0 + .dw 0x1340, 0xc90e, 0x137f, 0xc90e, 0x21, 0 + .dw 0x13c0, 0xc90e, 0x13ff, 0xc90e, 0x21, 0 + .dw 0x1440, 0xc90e, 0x147f, 0xc90e, 0x21, 0 + .dw 0x14c0, 0xc90e, 0x14ff, 0xc90e, 0x21, 0 + .dw 0x1540, 0xc90e, 0x157f, 0xc90e, 0x21, 0 + .dw 0x15c0, 0xc90e, 0x15ff, 0xc90e, 0x21, 0 + .dw 0x1640, 0xc90e, 0x167f, 0xc90e, 0x21, 0 + .dw 0x16c0, 0xc90e, 0x16ff, 0xc90e, 0x21, 0 + .dw 0x1740, 0xc90e, 0x177f, 0xc90e, 0x21, 0 + .dw 0x17c0, 0xc90e, 0x17ff, 0xc90e, 0x21, 0 + .dw 0x1840, 0xc90e, 0x187f, 0xc90e, 0x21, 0 + .dw 0x18c0, 0xc90e, 0x18ff, 0xc90e, 0x21, 0 + .dw 0x1940, 0xc90e, 0x197f, 0xc90e, 0x21, 0 + .dw 0x19c0, 0xc90e, 0x1fff, 0xc90e, 0x21, 0 + .dw 0x2040, 0xc90e, 0x207f, 0xc90e, 0x21, 0 + .dw 0x20c0, 0xc90e, 0x20ff, 0xc90e, 0x21, 0 + .dw 0x2140, 0xc90e, 0x217f, 0xc90e, 0x21, 0 + .dw 0x21c0, 0xc90e, 0x21ff, 0xc90e, 0x21, 0 + .dw 0x2240, 0xc90e, 0x227f, 0xc90e, 0x21, 0 + .dw 0x22c0, 0xc90e, 0x22ff, 0xc90e, 0x21, 0 + .dw 0x2340, 0xc90e, 0x237f, 0xc90e, 0x21, 0 + .dw 0x23c0, 0xc90e, 0x23ff, 0xc90e, 0x21, 0 + .dw 0x2440, 0xc90e, 0x247f, 0xc90e, 0x21, 0 + .dw 0x24c0, 0xc90e, 0x24ff, 0xc90e, 0x21, 0 + .dw 0x2540, 0xc90e, 0x257f, 0xc90e, 0x21, 0 + .dw 0x25c0, 0xc90e, 0x25ff, 0xc90e, 0x21, 0 + .dw 0x2640, 0xc90e, 0x267f, 0xc90e, 0x21, 0 + .dw 0x26c0, 0xc90e, 0x26ff, 0xc90e, 0x21, 0 + .dw 0x2740, 0xc90e, 0x277f, 0xc90e, 0x21, 0 + .dw 0x27c0, 0xc90e, 0x27ff, 0xc90e, 0x21, 0 + .dw 0x2840, 0xc90e, 0x287f, 0xc90e, 0x21, 0 + .dw 0x28c0, 0xc90e, 0x28ff, 0xc90e, 0x21, 0 + .dw 0x2940, 0xc90e, 0x297f, 0xc90e, 0x21, 0 + .dw 0x29c0, 0xc90e, 0x29ff, 0xc90e, 0x21, 0 + .dw 0x2a40, 0xc90e, 0x2a7f, 0xc90e, 0x21, 0 + .dw 0x2ac0, 0xc90e, 0x2aff, 0xc90e, 0x21, 0 + .dw 0x2b40, 0xc90e, 0x2b7f, 0xc90e, 0x21, 0 + .dw 0x2bc0, 0xc90e, 0x2bff, 0xc90e, 0x21, 0 + .dw 0x2c40, 0xc90e, 0x2c7f, 0xc90e, 0x21, 0 + .dw 0x2cc0, 0xc90e, 0x2cff, 0xc90e, 0x21, 0 + .dw 0x2d40, 0xc90e, 0x2d7f, 0xc90e, 0x21, 0 + .dw 0x2dc0, 0xc90e, 0x2dff, 0xc90e, 0x21, 0 + .dw 0x2e40, 0xc90e, 0x2e7f, 0xc90e, 0x21, 0 + .dw 0x2ec0, 0xc90e, 0x2eff, 0xc90e, 0x21, 0 + .dw 0x2f40, 0xc90e, 0x2f7f, 0xc90e, 0x21, 0 + .dw 0x2fc0, 0xc90e, 0x2fff, 0xc90e, 0x21, 0 + .dw 0x3040, 0xc90e, 0x307f, 0xc90e, 0x21, 0 + .dw 0x30c0, 0xc90e, 0x30ff, 0xc90e, 0x21, 0 + .dw 0x3140, 0xc90e, 0x317f, 0xc90e, 0x21, 0 + .dw 0x31c0, 0xc90e, 0x31ff, 0xc90e, 0x21, 0 + .dw 0x3240, 0xc90e, 0x327f, 0xc90e, 0x21, 0 + .dw 0x32c0, 0xc90e, 0x32ff, 0xc90e, 0x21, 0 + .dw 0x3340, 0xc90e, 0x337f, 0xc90e, 0x21, 0 + .dw 0x33c0, 0xc90e, 0x33ff, 0xc90e, 0x21, 0 + .dw 0x3440, 0xc90e, 0x347f, 0xc90e, 0x21, 0 + .dw 0x34c0, 0xc90e, 0x34ff, 0xc90e, 0x21, 0 + .dw 0x3540, 0xc90e, 0x357f, 0xc90e, 0x21, 0 + .dw 0x35c0, 0xc90e, 0x35ff, 0xc90e, 0x21, 0 + .dw 0x3640, 0xc90e, 0x367f, 0xc90e, 0x21, 0 + .dw 0x36c0, 0xc90e, 0x36ff, 0xc90e, 0x21, 0 + .dw 0x3740, 0xc90e, 0x377f, 0xc90e, 0x21, 0 + .dw 0x37c0, 0xc90e, 0x37ff, 0xc90e, 0x21, 0 + .dw 0x3840, 0xc90e, 0x387f, 0xc90e, 0x21, 0 + .dw 0x38c0, 0xc90e, 0x38ff, 0xc90e, 0x21, 0 + .dw 0x3940, 0xc90e, 0x397f, 0xc90e, 0x21, 0 + .dw 0x39c0, 0xc90e, 0x3fff, 0xc90e, 0x21, 0 + .dw 0x4040, 0xc90e, 0x407f, 0xc90e, 0x21, 0 + .dw 0x40c0, 0xc90e, 0x40ff, 0xc90e, 0x21, 0 + .dw 0x4140, 0xc90e, 0x417f, 0xc90e, 0x21, 0 + .dw 0x41c0, 0xc90e, 0x41ff, 0xc90e, 0x21, 0 + .dw 0x4240, 0xc90e, 0x427f, 0xc90e, 0x21, 0 + .dw 0x42c0, 0xc90e, 0x42ff, 0xc90e, 0x21, 0 + .dw 0x4340, 0xc90e, 0x437f, 0xc90e, 0x21, 0 + .dw 0x43c0, 0xc90e, 0x43ff, 0xc90e, 0x21, 0 + .dw 0x4440, 0xc90e, 0x447f, 0xc90e, 0x21, 0 + .dw 0x44c0, 0xc90e, 0x44ff, 0xc90e, 0x21, 0 + .dw 0x4540, 0xc90e, 0x457f, 0xc90e, 0x21, 0 + .dw 0x45c0, 0xc90e, 0x45ff, 0xc90e, 0x21, 0 + .dw 0x4640, 0xc90e, 0x467f, 0xc90e, 0x21, 0 + .dw 0x46c0, 0xc90e, 0x46ff, 0xc90e, 0x21, 0 + .dw 0x4740, 0xc90e, 0x477f, 0xc90e, 0x21, 0 + .dw 0x47c0, 0xc90e, 0x47ff, 0xc90e, 0x21, 0 + .dw 0x4840, 0xc90e, 0x487f, 0xc90e, 0x21, 0 + .dw 0x48c0, 0xc90e, 0x48ff, 0xc90e, 0x21, 0 + .dw 0x4940, 0xc90e, 0x497f, 0xc90e, 0x21, 0 + .dw 0x49c0, 0xc90e, 0x49ff, 0xc90e, 0x21, 0 + .dw 0x4a40, 0xc90e, 0x4a7f, 0xc90e, 0x21, 0 + .dw 0x4ac0, 0xc90e, 0x4aff, 0xc90e, 0x21, 0 + .dw 0x4b40, 0xc90e, 0x4b7f, 0xc90e, 0x21, 0 + .dw 0x4bc0, 0xc90e, 0x4bff, 0xc90e, 0x21, 0 + .dw 0x4c40, 0xc90e, 0x4c7f, 0xc90e, 0x21, 0 + .dw 0x4cc0, 0xc90e, 0x4cff, 0xc90e, 0x21, 0 + .dw 0x4d40, 0xc90e, 0x4d7f, 0xc90e, 0x21, 0 + .dw 0x4dc0, 0xc90e, 0x4dff, 0xc90e, 0x21, 0 + .dw 0x4e40, 0xc90e, 0x4e7f, 0xc90e, 0x21, 0 + .dw 0x4ec0, 0xc90e, 0x4eff, 0xc90e, 0x21, 0 + .dw 0x4f40, 0xc90e, 0x4f7f, 0xc90e, 0x21, 0 + .dw 0x4fc0, 0xc90e, 0x4fff, 0xc90e, 0x21, 0 + .dw 0x5040, 0xc90e, 0x507f, 0xc90e, 0x21, 0 + .dw 0x50c0, 0xc90e, 0x50ff, 0xc90e, 0x21, 0 + .dw 0x5140, 0xc90e, 0x517f, 0xc90e, 0x21, 0 + .dw 0x51c0, 0xc90e, 0x51ff, 0xc90e, 0x21, 0 + .dw 0x5240, 0xc90e, 0x527f, 0xc90e, 0x21, 0 + .dw 0x52c0, 0xc90e, 0x52ff, 0xc90e, 0x21, 0 + .dw 0x5340, 0xc90e, 0x537f, 0xc90e, 0x21, 0 + .dw 0x53c0, 0xc90e, 0x53ff, 0xc90e, 0x21, 0 + .dw 0x5440, 0xc90e, 0x547f, 0xc90e, 0x21, 0 + .dw 0x54c0, 0xc90e, 0x54ff, 0xc90e, 0x21, 0 + .dw 0x5540, 0xc90e, 0x557f, 0xc90e, 0x21, 0 + .dw 0x55c0, 0xc90e, 0x55ff, 0xc90e, 0x21, 0 + .dw 0x5640, 0xc90e, 0x567f, 0xc90e, 0x21, 0 + .dw 0x56c0, 0xc90e, 0x56ff, 0xc90e, 0x21, 0 + .dw 0x5740, 0xc90e, 0x577f, 0xc90e, 0x21, 0 + .dw 0x57c0, 0xc90e, 0x57ff, 0xc90e, 0x21, 0 + .dw 0x5840, 0xc90e, 0x587f, 0xc90e, 0x21, 0 + .dw 0x58c0, 0xc90e, 0x58ff, 0xc90e, 0x21, 0 + .dw 0x5940, 0xc90e, 0x597f, 0xc90e, 0x21, 0 + .dw 0x59c0, 0xc90e, 0x5fff, 0xc90e, 0x21, 0 + .dw 0x6040, 0xc90e, 0x607f, 0xc90e, 0x21, 0 + .dw 0x60c0, 0xc90e, 0x60ff, 0xc90e, 0x21, 0 + .dw 0x6140, 0xc90e, 0x617f, 0xc90e, 0x21, 0 + .dw 0x61c0, 0xc90e, 0x61ff, 0xc90e, 0x21, 0 + .dw 0x6240, 0xc90e, 0x627f, 0xc90e, 0x21, 0 + .dw 0x62c0, 0xc90e, 0x62ff, 0xc90e, 0x21, 0 + .dw 0x6340, 0xc90e, 0x637f, 0xc90e, 0x21, 0 + .dw 0x63c0, 0xc90e, 0x63ff, 0xc90e, 0x21, 0 + .dw 0x6440, 0xc90e, 0x647f, 0xc90e, 0x21, 0 + .dw 0x64c0, 0xc90e, 0x64ff, 0xc90e, 0x21, 0 + .dw 0x6540, 0xc90e, 0x657f, 0xc90e, 0x21, 0 + .dw 0x65c0, 0xc90e, 0x65ff, 0xc90e, 0x21, 0 + .dw 0x6640, 0xc90e, 0x667f, 0xc90e, 0x21, 0 + .dw 0x66c0, 0xc90e, 0x66ff, 0xc90e, 0x21, 0 + .dw 0x6740, 0xc90e, 0x677f, 0xc90e, 0x21, 0 + .dw 0x67c0, 0xc90e, 0x67ff, 0xc90e, 0x21, 0 + .dw 0x6840, 0xc90e, 0x687f, 0xc90e, 0x21, 0 + .dw 0x68c0, 0xc90e, 0x68ff, 0xc90e, 0x21, 0 + .dw 0x6940, 0xc90e, 0x697f, 0xc90e, 0x21, 0 + .dw 0x69c0, 0xc90e, 0x69ff, 0xc90e, 0x21, 0 + .dw 0x6a40, 0xc90e, 0x6a7f, 0xc90e, 0x21, 0 + .dw 0x6ac0, 0xc90e, 0x6aff, 0xc90e, 0x21, 0 + .dw 0x6b40, 0xc90e, 0x6b7f, 0xc90e, 0x21, 0 + .dw 0x6bc0, 0xc90e, 0x6bff, 0xc90e, 0x21, 0 + .dw 0x6c40, 0xc90e, 0x6c7f, 0xc90e, 0x21, 0 + .dw 0x6cc0, 0xc90e, 0x6cff, 0xc90e, 0x21, 0 + .dw 0x6d40, 0xc90e, 0x6d7f, 0xc90e, 0x21, 0 + .dw 0x6dc0, 0xc90e, 0x6dff, 0xc90e, 0x21, 0 + .dw 0x6e40, 0xc90e, 0x6e7f, 0xc90e, 0x21, 0 + .dw 0x6ec0, 0xc90e, 0x6eff, 0xc90e, 0x21, 0 + .dw 0x6f40, 0xc90e, 0x6f7f, 0xc90e, 0x21, 0 + .dw 0x6fc0, 0xc90e, 0x6fff, 0xc90e, 0x21, 0 + .dw 0x7040, 0xc90e, 0x707f, 0xc90e, 0x21, 0 + .dw 0x70c0, 0xc90e, 0x70ff, 0xc90e, 0x21, 0 + .dw 0x7140, 0xc90e, 0x717f, 0xc90e, 0x21, 0 + .dw 0x71c0, 0xc90e, 0x71ff, 0xc90e, 0x21, 0 + .dw 0x7240, 0xc90e, 0x727f, 0xc90e, 0x21, 0 + .dw 0x72c0, 0xc90e, 0x72ff, 0xc90e, 0x21, 0 + .dw 0x7340, 0xc90e, 0x737f, 0xc90e, 0x21, 0 + .dw 0x73c0, 0xc90e, 0x73ff, 0xc90e, 0x21, 0 + .dw 0x7440, 0xc90e, 0x747f, 0xc90e, 0x21, 0 + .dw 0x74c0, 0xc90e, 0x74ff, 0xc90e, 0x21, 0 + .dw 0x7540, 0xc90e, 0x757f, 0xc90e, 0x21, 0 + .dw 0x75c0, 0xc90e, 0x75ff, 0xc90e, 0x21, 0 + .dw 0x7640, 0xc90e, 0x767f, 0xc90e, 0x21, 0 + .dw 0x76c0, 0xc90e, 0x76ff, 0xc90e, 0x21, 0 + .dw 0x7740, 0xc90e, 0x777f, 0xc90e, 0x21, 0 + .dw 0x77c0, 0xc90e, 0x77ff, 0xc90e, 0x21, 0 + .dw 0x7840, 0xc90e, 0x787f, 0xc90e, 0x21, 0 + .dw 0x78c0, 0xc90e, 0x78ff, 0xc90e, 0x21, 0 + .dw 0x7940, 0xc90e, 0x797f, 0xc90e, 0x21, 0 + .dw 0x79c0, 0xc90e, 0x7fff, 0xc90e, 0x21, 0 + .dw 0x8040, 0xc90e, 0x807f, 0xc90e, 0x21, 0 + .dw 0x80c0, 0xc90e, 0x80ff, 0xc90e, 0x21, 0 + .dw 0x8140, 0xc90e, 0x817f, 0xc90e, 0x21, 0 + .dw 0x81c0, 0xc90e, 0x81ff, 0xc90e, 0x21, 0 + .dw 0x8240, 0xc90e, 0x827f, 0xc90e, 0x21, 0 + .dw 0x82c0, 0xc90e, 0x82ff, 0xc90e, 0x21, 0 + .dw 0x8340, 0xc90e, 0x837f, 0xc90e, 0x21, 0 + .dw 0x83c0, 0xc90e, 0x83ff, 0xc90e, 0x21, 0 + .dw 0x8440, 0xc90e, 0x847f, 0xc90e, 0x21, 0 + .dw 0x84c0, 0xc90e, 0x84ff, 0xc90e, 0x21, 0 + .dw 0x8540, 0xc90e, 0x857f, 0xc90e, 0x21, 0 + .dw 0x85c0, 0xc90e, 0x85ff, 0xc90e, 0x21, 0 + .dw 0x8640, 0xc90e, 0x867f, 0xc90e, 0x21, 0 + .dw 0x86c0, 0xc90e, 0x86ff, 0xc90e, 0x21, 0 + .dw 0x8740, 0xc90e, 0x877f, 0xc90e, 0x21, 0 + .dw 0x87c0, 0xc90e, 0x87ff, 0xc90e, 0x21, 0 + .dw 0x8840, 0xc90e, 0x887f, 0xc90e, 0x21, 0 + .dw 0x88c0, 0xc90e, 0x88ff, 0xc90e, 0x21, 0 + .dw 0x8940, 0xc90e, 0x897f, 0xc90e, 0x21, 0 + .dw 0x89c0, 0xc90e, 0x89ff, 0xc90e, 0x21, 0 + .dw 0x8a40, 0xc90e, 0x8a7f, 0xc90e, 0x21, 0 + .dw 0x8ac0, 0xc90e, 0x8aff, 0xc90e, 0x21, 0 + .dw 0x8b40, 0xc90e, 0x8b7f, 0xc90e, 0x21, 0 + .dw 0x8bc0, 0xc90e, 0x8bff, 0xc90e, 0x21, 0 + .dw 0x8c40, 0xc90e, 0x8c7f, 0xc90e, 0x21, 0 + .dw 0x8cc0, 0xc90e, 0x8cff, 0xc90e, 0x21, 0 + .dw 0x8d40, 0xc90e, 0x8d7f, 0xc90e, 0x21, 0 + .dw 0x8dc0, 0xc90e, 0x8dff, 0xc90e, 0x21, 0 + .dw 0x8e40, 0xc90e, 0x8e7f, 0xc90e, 0x21, 0 + .dw 0x8ec0, 0xc90e, 0x8eff, 0xc90e, 0x21, 0 + .dw 0x8f40, 0xc90e, 0x8f7f, 0xc90e, 0x21, 0 + .dw 0x8fc0, 0xc90e, 0x8fff, 0xc90e, 0x21, 0 + .dw 0x9040, 0xc90e, 0x907f, 0xc90e, 0x21, 0 + .dw 0x90c0, 0xc90e, 0x90ff, 0xc90e, 0x21, 0 + .dw 0x9140, 0xc90e, 0x917f, 0xc90e, 0x21, 0 + .dw 0x91c0, 0xc90e, 0x91ff, 0xc90e, 0x21, 0 + .dw 0x9240, 0xc90e, 0x927f, 0xc90e, 0x21, 0 + .dw 0x92c0, 0xc90e, 0x92ff, 0xc90e, 0x21, 0 + .dw 0x9340, 0xc90e, 0x937f, 0xc90e, 0x21, 0 + .dw 0x93c0, 0xc90e, 0x93ff, 0xc90e, 0x21, 0 + .dw 0x9440, 0xc90e, 0x947f, 0xc90e, 0x21, 0 + .dw 0x94c0, 0xc90e, 0x94ff, 0xc90e, 0x21, 0 + .dw 0x9540, 0xc90e, 0x957f, 0xc90e, 0x21, 0 + .dw 0x95c0, 0xc90e, 0x95ff, 0xc90e, 0x21, 0 + .dw 0x9640, 0xc90e, 0x967f, 0xc90e, 0x21, 0 + .dw 0x96c0, 0xc90e, 0x96ff, 0xc90e, 0x21, 0 + .dw 0x9740, 0xc90e, 0x977f, 0xc90e, 0x21, 0 + .dw 0x97c0, 0xc90e, 0x97ff, 0xc90e, 0x21, 0 + .dw 0x9840, 0xc90e, 0x987f, 0xc90e, 0x21, 0 + .dw 0x98c0, 0xc90e, 0x98ff, 0xc90e, 0x21, 0 + .dw 0x9940, 0xc90e, 0x997f, 0xc90e, 0x21, 0 + .dw 0x99c0, 0xc90e, 0x9fff, 0xc90e, 0x21, 0 + .dw 0xa040, 0xc90e, 0xa07f, 0xc90e, 0x21, 0 + .dw 0xa0c0, 0xc90e, 0xa0ff, 0xc90e, 0x21, 0 + .dw 0xa140, 0xc90e, 0xa17f, 0xc90e, 0x21, 0 + .dw 0xa1c0, 0xc90e, 0xa1ff, 0xc90e, 0x21, 0 + .dw 0xa240, 0xc90e, 0xa27f, 0xc90e, 0x21, 0 + .dw 0xa2c0, 0xc90e, 0xa2ff, 0xc90e, 0x21, 0 + .dw 0xa340, 0xc90e, 0xa37f, 0xc90e, 0x21, 0 + .dw 0xa3c0, 0xc90e, 0xa3ff, 0xc90e, 0x21, 0 + .dw 0xa440, 0xc90e, 0xa47f, 0xc90e, 0x21, 0 + .dw 0xa4c0, 0xc90e, 0xa4ff, 0xc90e, 0x21, 0 + .dw 0xa540, 0xc90e, 0xa57f, 0xc90e, 0x21, 0 + .dw 0xa5c0, 0xc90e, 0xa5ff, 0xc90e, 0x21, 0 + .dw 0xa640, 0xc90e, 0xa67f, 0xc90e, 0x21, 0 + .dw 0xa6c0, 0xc90e, 0xa6ff, 0xc90e, 0x21, 0 + .dw 0xa740, 0xc90e, 0xa77f, 0xc90e, 0x21, 0 + .dw 0xa7c0, 0xc90e, 0xa7ff, 0xc90e, 0x21, 0 + .dw 0xa840, 0xc90e, 0xa87f, 0xc90e, 0x21, 0 + .dw 0xa8c0, 0xc90e, 0xa8ff, 0xc90e, 0x21, 0 + .dw 0xa940, 0xc90e, 0xa97f, 0xc90e, 0x21, 0 + .dw 0xa9c0, 0xc90e, 0xa9ff, 0xc90e, 0x21, 0 + .dw 0xaa40, 0xc90e, 0xaa7f, 0xc90e, 0x21, 0 + .dw 0xaac0, 0xc90e, 0xaaff, 0xc90e, 0x21, 0 + .dw 0xab40, 0xc90e, 0xab7f, 0xc90e, 0x21, 0 + .dw 0xabc0, 0xc90e, 0xabff, 0xc90e, 0x21, 0 + .dw 0xac40, 0xc90e, 0xac7f, 0xc90e, 0x21, 0 + .dw 0xacc0, 0xc90e, 0xacff, 0xc90e, 0x21, 0 + .dw 0xad40, 0xc90e, 0xad7f, 0xc90e, 0x21, 0 + .dw 0xadc0, 0xc90e, 0xadff, 0xc90e, 0x21, 0 + .dw 0xae40, 0xc90e, 0xae7f, 0xc90e, 0x21, 0 + .dw 0xaec0, 0xc90e, 0xaeff, 0xc90e, 0x21, 0 + .dw 0xaf40, 0xc90e, 0xaf7f, 0xc90e, 0x21, 0 + .dw 0xafc0, 0xc90e, 0xafff, 0xc90e, 0x21, 0 + .dw 0xb040, 0xc90e, 0xb07f, 0xc90e, 0x21, 0 + .dw 0xb0c0, 0xc90e, 0xb0ff, 0xc90e, 0x21, 0 + .dw 0xb140, 0xc90e, 0xb17f, 0xc90e, 0x21, 0 + .dw 0xb1c0, 0xc90e, 0xb1ff, 0xc90e, 0x21, 0 + .dw 0xb240, 0xc90e, 0xb27f, 0xc90e, 0x21, 0 + .dw 0xb2c0, 0xc90e, 0xb2ff, 0xc90e, 0x21, 0 + .dw 0xb340, 0xc90e, 0xb37f, 0xc90e, 0x21, 0 + .dw 0xb3c0, 0xc90e, 0xb3ff, 0xc90e, 0x21, 0 + .dw 0xb440, 0xc90e, 0xb47f, 0xc90e, 0x21, 0 + .dw 0xb4c0, 0xc90e, 0xb4ff, 0xc90e, 0x21, 0 + .dw 0xb540, 0xc90e, 0xb57f, 0xc90e, 0x21, 0 + .dw 0xb5c0, 0xc90e, 0xb5ff, 0xc90e, 0x21, 0 + .dw 0xb640, 0xc90e, 0xb67f, 0xc90e, 0x21, 0 + .dw 0xb6c0, 0xc90e, 0xb6ff, 0xc90e, 0x21, 0 + .dw 0xb740, 0xc90e, 0xb77f, 0xc90e, 0x21, 0 + .dw 0xb7c0, 0xc90e, 0xb7ff, 0xc90e, 0x21, 0 + .dw 0xb840, 0xc90e, 0xb87f, 0xc90e, 0x21, 0 + .dw 0xb8c0, 0xc90e, 0xb8ff, 0xc90e, 0x21, 0 + .dw 0xb940, 0xc90e, 0xb97f, 0xc90e, 0x21, 0 + .dw 0xb9c0, 0xc90e, 0xbfff, 0xc90e, 0x21, 0 + .dw 0xc040, 0xc90e, 0xc07f, 0xc90e, 0x21, 0 + .dw 0xc0c0, 0xc90e, 0xc0ff, 0xc90e, 0x21, 0 + .dw 0xc140, 0xc90e, 0xc17f, 0xc90e, 0x21, 0 + .dw 0xc1c0, 0xc90e, 0xc1ff, 0xc90e, 0x21, 0 + .dw 0xc240, 0xc90e, 0xc27f, 0xc90e, 0x21, 0 + .dw 0xc2c0, 0xc90e, 0xc2ff, 0xc90e, 0x21, 0 + .dw 0xc340, 0xc90e, 0xc37f, 0xc90e, 0x21, 0 + .dw 0xc3c0, 0xc90e, 0xc3ff, 0xc90e, 0x21, 0 + .dw 0xc440, 0xc90e, 0xc47f, 0xc90e, 0x21, 0 + .dw 0xc4c0, 0xc90e, 0xc4ff, 0xc90e, 0x21, 0 + .dw 0xc540, 0xc90e, 0xc57f, 0xc90e, 0x21, 0 + .dw 0xc5c0, 0xc90e, 0xc5ff, 0xc90e, 0x21, 0 + .dw 0xc640, 0xc90e, 0xc67f, 0xc90e, 0x21, 0 + .dw 0xc6c0, 0xc90e, 0xc6ff, 0xc90e, 0x21, 0 + .dw 0xc740, 0xc90e, 0xc77f, 0xc90e, 0x21, 0 + .dw 0xc7c0, 0xc90e, 0xc7ff, 0xc90e, 0x21, 0 + .dw 0xc840, 0xc90e, 0xc87f, 0xc90e, 0x21, 0 + .dw 0xc8c0, 0xc90e, 0xc8ff, 0xc90e, 0x21, 0 + .dw 0xc940, 0xc90e, 0xc97f, 0xc90e, 0x21, 0 + .dw 0xc9c0, 0xc90e, 0xc9ff, 0xc90e, 0x21, 0 + .dw 0xca40, 0xc90e, 0xca7f, 0xc90e, 0x21, 0 + .dw 0xcac0, 0xc90e, 0xcaff, 0xc90e, 0x21, 0 + .dw 0xcb40, 0xc90e, 0xcb7f, 0xc90e, 0x21, 0 + .dw 0xcbc0, 0xc90e, 0xcbff, 0xc90e, 0x21, 0 + .dw 0xcc40, 0xc90e, 0xcc7f, 0xc90e, 0x21, 0 + .dw 0xccc0, 0xc90e, 0xccff, 0xc90e, 0x21, 0 + .dw 0xcd40, 0xc90e, 0xcd7f, 0xc90e, 0x21, 0 + .dw 0xcdc0, 0xc90e, 0xcdff, 0xc90e, 0x21, 0 + .dw 0xce40, 0xc90e, 0xce7f, 0xc90e, 0x21, 0 + .dw 0xcec0, 0xc90e, 0xceff, 0xc90e, 0x21, 0 + .dw 0xcf40, 0xc90e, 0xcf7f, 0xc90e, 0x21, 0 + .dw 0xcfc0, 0xc90e, 0xcfff, 0xc90e, 0x21, 0 + .dw 0xd040, 0xc90e, 0xd07f, 0xc90e, 0x21, 0 + .dw 0xd0c0, 0xc90e, 0xd0ff, 0xc90e, 0x21, 0 + .dw 0xd140, 0xc90e, 0xd17f, 0xc90e, 0x21, 0 + .dw 0xd1c0, 0xc90e, 0xd1ff, 0xc90e, 0x21, 0 + .dw 0xd240, 0xc90e, 0xd27f, 0xc90e, 0x21, 0 + .dw 0xd2c0, 0xc90e, 0xd2ff, 0xc90e, 0x21, 0 + .dw 0xd340, 0xc90e, 0xd37f, 0xc90e, 0x21, 0 + .dw 0xd3c0, 0xc90e, 0xd3ff, 0xc90e, 0x21, 0 + .dw 0xd440, 0xc90e, 0xd47f, 0xc90e, 0x21, 0 + .dw 0xd4c0, 0xc90e, 0xd4ff, 0xc90e, 0x21, 0 + .dw 0xd540, 0xc90e, 0xd57f, 0xc90e, 0x21, 0 + .dw 0xd5c0, 0xc90e, 0xd5ff, 0xc90e, 0x21, 0 + .dw 0xd640, 0xc90e, 0xd67f, 0xc90e, 0x21, 0 + .dw 0xd6c0, 0xc90e, 0xd6ff, 0xc90e, 0x21, 0 + .dw 0xd740, 0xc90e, 0xd77f, 0xc90e, 0x21, 0 + .dw 0xd7c0, 0xc90e, 0xd7ff, 0xc90e, 0x21, 0 + .dw 0xd840, 0xc90e, 0xd87f, 0xc90e, 0x21, 0 + .dw 0xd8c0, 0xc90e, 0xd8ff, 0xc90e, 0x21, 0 + .dw 0xd940, 0xc90e, 0xd97f, 0xc90e, 0x21, 0 + .dw 0xd9c0, 0xc90e, 0xdfff, 0xc90e, 0x21, 0 + .dw 0xe040, 0xc90e, 0xe07f, 0xc90e, 0x21, 0 + .dw 0xe0c0, 0xc90e, 0xe0ff, 0xc90e, 0x21, 0 + .dw 0xe140, 0xc90e, 0xe17f, 0xc90e, 0x21, 0 + .dw 0xe1c0, 0xc90e, 0xe1ff, 0xc90e, 0x21, 0 + .dw 0xe240, 0xc90e, 0xe27f, 0xc90e, 0x21, 0 + .dw 0xe2c0, 0xc90e, 0xe2ff, 0xc90e, 0x21, 0 + .dw 0xe340, 0xc90e, 0xe37f, 0xc90e, 0x21, 0 + .dw 0xe3c0, 0xc90e, 0xe3ff, 0xc90e, 0x21, 0 + .dw 0xe440, 0xc90e, 0xe47f, 0xc90e, 0x21, 0 + .dw 0xe4c0, 0xc90e, 0xe4ff, 0xc90e, 0x21, 0 + .dw 0xe540, 0xc90e, 0xe57f, 0xc90e, 0x21, 0 + .dw 0xe5c0, 0xc90e, 0xe5ff, 0xc90e, 0x21, 0 + .dw 0xe640, 0xc90e, 0xe67f, 0xc90e, 0x21, 0 + .dw 0xe6c0, 0xc90e, 0xe6ff, 0xc90e, 0x21, 0 + .dw 0xe740, 0xc90e, 0xe77f, 0xc90e, 0x21, 0 + .dw 0xe7c0, 0xc90e, 0xe7ff, 0xc90e, 0x21, 0 + .dw 0xe840, 0xc90e, 0xe87f, 0xc90e, 0x21, 0 + .dw 0xe8c0, 0xc90e, 0xe8ff, 0xc90e, 0x21, 0 + .dw 0xe940, 0xc90e, 0xe97f, 0xc90e, 0x21, 0 + .dw 0xe9c0, 0xc90e, 0xe9ff, 0xc90e, 0x21, 0 + .dw 0xea40, 0xc90e, 0xea7f, 0xc90e, 0x21, 0 + .dw 0xeac0, 0xc90e, 0xeaff, 0xc90e, 0x21, 0 + .dw 0xeb40, 0xc90e, 0xeb7f, 0xc90e, 0x21, 0 + .dw 0xebc0, 0xc90e, 0xebff, 0xc90e, 0x21, 0 + .dw 0xec40, 0xc90e, 0xec7f, 0xc90e, 0x21, 0 + .dw 0xecc0, 0xc90e, 0xecff, 0xc90e, 0x21, 0 + .dw 0xed40, 0xc90e, 0xed7f, 0xc90e, 0x21, 0 + .dw 0xedc0, 0xc90e, 0xedff, 0xc90e, 0x21, 0 + .dw 0xee40, 0xc90e, 0xee7f, 0xc90e, 0x21, 0 + .dw 0xeec0, 0xc90e, 0xeeff, 0xc90e, 0x21, 0 + .dw 0xef40, 0xc90e, 0xef7f, 0xc90e, 0x21, 0 + .dw 0xefc0, 0xc90e, 0xefff, 0xc90e, 0x21, 0 + .dw 0xf040, 0xc90e, 0xf07f, 0xc90e, 0x21, 0 + .dw 0xf0c0, 0xc90e, 0xf0ff, 0xc90e, 0x21, 0 + .dw 0xf140, 0xc90e, 0xf17f, 0xc90e, 0x21, 0 + .dw 0xf1c0, 0xc90e, 0xf1ff, 0xc90e, 0x21, 0 + .dw 0xf240, 0xc90e, 0xf27f, 0xc90e, 0x21, 0 + .dw 0xf2c0, 0xc90e, 0xf2ff, 0xc90e, 0x21, 0 + .dw 0xf340, 0xc90e, 0xf37f, 0xc90e, 0x21, 0 + .dw 0xf3c0, 0xc90e, 0xf3ff, 0xc90e, 0x21, 0 + .dw 0xf440, 0xc90e, 0xf47f, 0xc90e, 0x21, 0 + .dw 0xf4c0, 0xc90e, 0xf4ff, 0xc90e, 0x21, 0 + .dw 0xf540, 0xc90e, 0xf57f, 0xc90e, 0x21, 0 + .dw 0xf5c0, 0xc90e, 0xf5ff, 0xc90e, 0x21, 0 + .dw 0xf640, 0xc90e, 0xf67f, 0xc90e, 0x21, 0 + .dw 0xf6c0, 0xc90e, 0xf6ff, 0xc90e, 0x21, 0 + .dw 0xf740, 0xc90e, 0xf77f, 0xc90e, 0x21, 0 + .dw 0xf7c0, 0xc90e, 0xf7ff, 0xc90e, 0x21, 0 + .dw 0xf840, 0xc90e, 0xf87f, 0xc90e, 0x21, 0 + .dw 0xf8c0, 0xc90e, 0xf8ff, 0xc90e, 0x21, 0 + .dw 0xf940, 0xc90e, 0xf97f, 0xc90e, 0x21, 0 + .dw 0xf9c0, 0xc90e, 0xffff, 0xc90e, 0x21, 0 + .dw 0x0040, 0xc90f, 0x007f, 0xc90f, 0x21, 0 + .dw 0x00c0, 0xc90f, 0x00ff, 0xc90f, 0x21, 0 + .dw 0x0140, 0xc90f, 0x017f, 0xc90f, 0x21, 0 + .dw 0x01c0, 0xc90f, 0x01ff, 0xc90f, 0x21, 0 + .dw 0x0240, 0xc90f, 0x027f, 0xc90f, 0x21, 0 + .dw 0x02c0, 0xc90f, 0x02ff, 0xc90f, 0x21, 0 + .dw 0x0340, 0xc90f, 0x037f, 0xc90f, 0x21, 0 + .dw 0x03c0, 0xc90f, 0x03ff, 0xc90f, 0x21, 0 + .dw 0x0440, 0xc90f, 0x047f, 0xc90f, 0x21, 0 + .dw 0x04c0, 0xc90f, 0x04ff, 0xc90f, 0x21, 0 + .dw 0x0540, 0xc90f, 0x057f, 0xc90f, 0x21, 0 + .dw 0x05c0, 0xc90f, 0x05ff, 0xc90f, 0x21, 0 + .dw 0x0640, 0xc90f, 0x067f, 0xc90f, 0x21, 0 + .dw 0x06c0, 0xc90f, 0x06ff, 0xc90f, 0x21, 0 + .dw 0x0740, 0xc90f, 0x077f, 0xc90f, 0x21, 0 + .dw 0x07c0, 0xc90f, 0x07ff, 0xc90f, 0x21, 0 + .dw 0x0840, 0xc90f, 0x087f, 0xc90f, 0x21, 0 + .dw 0x08c0, 0xc90f, 0x08ff, 0xc90f, 0x21, 0 + .dw 0x0940, 0xc90f, 0x097f, 0xc90f, 0x21, 0 + .dw 0x09c0, 0xc90f, 0x09ff, 0xc90f, 0x21, 0 + .dw 0x0a40, 0xc90f, 0x0a7f, 0xc90f, 0x21, 0 + .dw 0x0ac0, 0xc90f, 0x0aff, 0xc90f, 0x21, 0 + .dw 0x0b40, 0xc90f, 0x0b7f, 0xc90f, 0x21, 0 + .dw 0x0bc0, 0xc90f, 0x0bff, 0xc90f, 0x21, 0 + .dw 0x0c40, 0xc90f, 0x0c7f, 0xc90f, 0x21, 0 + .dw 0x0cc0, 0xc90f, 0x0cff, 0xc90f, 0x21, 0 + .dw 0x0d40, 0xc90f, 0x0d7f, 0xc90f, 0x21, 0 + .dw 0x0dc0, 0xc90f, 0x0dff, 0xc90f, 0x21, 0 + .dw 0x0e40, 0xc90f, 0x0e7f, 0xc90f, 0x21, 0 + .dw 0x0ec0, 0xc90f, 0x0eff, 0xc90f, 0x21, 0 + .dw 0x0f40, 0xc90f, 0x0f7f, 0xc90f, 0x21, 0 + .dw 0x0fc0, 0xc90f, 0x0fff, 0xc90f, 0x21, 0 + .dw 0x1040, 0xc90f, 0x107f, 0xc90f, 0x21, 0 + .dw 0x10c0, 0xc90f, 0x10ff, 0xc90f, 0x21, 0 + .dw 0x1140, 0xc90f, 0x117f, 0xc90f, 0x21, 0 + .dw 0x11c0, 0xc90f, 0x11ff, 0xc90f, 0x21, 0 + .dw 0x1240, 0xc90f, 0x127f, 0xc90f, 0x21, 0 + .dw 0x12c0, 0xc90f, 0x12ff, 0xc90f, 0x21, 0 + .dw 0x1340, 0xc90f, 0x137f, 0xc90f, 0x21, 0 + .dw 0x13c0, 0xc90f, 0x13ff, 0xc90f, 0x21, 0 + .dw 0x1440, 0xc90f, 0x147f, 0xc90f, 0x21, 0 + .dw 0x14c0, 0xc90f, 0x14ff, 0xc90f, 0x21, 0 + .dw 0x1540, 0xc90f, 0x157f, 0xc90f, 0x21, 0 + .dw 0x15c0, 0xc90f, 0x15ff, 0xc90f, 0x21, 0 + .dw 0x1640, 0xc90f, 0x167f, 0xc90f, 0x21, 0 + .dw 0x16c0, 0xc90f, 0x16ff, 0xc90f, 0x21, 0 + .dw 0x1740, 0xc90f, 0x177f, 0xc90f, 0x21, 0 + .dw 0x17c0, 0xc90f, 0x17ff, 0xc90f, 0x21, 0 + .dw 0x1840, 0xc90f, 0x187f, 0xc90f, 0x21, 0 + .dw 0x18c0, 0xc90f, 0x18ff, 0xc90f, 0x21, 0 + .dw 0x1940, 0xc90f, 0x197f, 0xc90f, 0x21, 0 + .dw 0x19c0, 0xc90f, 0x1fff, 0xc90f, 0x21, 0 + .dw 0x2040, 0xc90f, 0x207f, 0xc90f, 0x21, 0 + .dw 0x20c0, 0xc90f, 0x20ff, 0xc90f, 0x21, 0 + .dw 0x2140, 0xc90f, 0x217f, 0xc90f, 0x21, 0 + .dw 0x21c0, 0xc90f, 0x21ff, 0xc90f, 0x21, 0 + .dw 0x2240, 0xc90f, 0x227f, 0xc90f, 0x21, 0 + .dw 0x22c0, 0xc90f, 0x22ff, 0xc90f, 0x21, 0 + .dw 0x2340, 0xc90f, 0x237f, 0xc90f, 0x21, 0 + .dw 0x23c0, 0xc90f, 0x23ff, 0xc90f, 0x21, 0 + .dw 0x2440, 0xc90f, 0x247f, 0xc90f, 0x21, 0 + .dw 0x24c0, 0xc90f, 0x24ff, 0xc90f, 0x21, 0 + .dw 0x2540, 0xc90f, 0x257f, 0xc90f, 0x21, 0 + .dw 0x25c0, 0xc90f, 0x25ff, 0xc90f, 0x21, 0 + .dw 0x2640, 0xc90f, 0x267f, 0xc90f, 0x21, 0 + .dw 0x26c0, 0xc90f, 0x26ff, 0xc90f, 0x21, 0 + .dw 0x2740, 0xc90f, 0x277f, 0xc90f, 0x21, 0 + .dw 0x27c0, 0xc90f, 0x27ff, 0xc90f, 0x21, 0 + .dw 0x2840, 0xc90f, 0x287f, 0xc90f, 0x21, 0 + .dw 0x28c0, 0xc90f, 0x28ff, 0xc90f, 0x21, 0 + .dw 0x2940, 0xc90f, 0x297f, 0xc90f, 0x21, 0 + .dw 0x29c0, 0xc90f, 0x29ff, 0xc90f, 0x21, 0 + .dw 0x2a40, 0xc90f, 0x2a7f, 0xc90f, 0x21, 0 + .dw 0x2ac0, 0xc90f, 0x2aff, 0xc90f, 0x21, 0 + .dw 0x2b40, 0xc90f, 0x2b7f, 0xc90f, 0x21, 0 + .dw 0x2bc0, 0xc90f, 0x2bff, 0xc90f, 0x21, 0 + .dw 0x2c40, 0xc90f, 0x2c7f, 0xc90f, 0x21, 0 + .dw 0x2cc0, 0xc90f, 0x2cff, 0xc90f, 0x21, 0 + .dw 0x2d40, 0xc90f, 0x2d7f, 0xc90f, 0x21, 0 + .dw 0x2dc0, 0xc90f, 0x2dff, 0xc90f, 0x21, 0 + .dw 0x2e40, 0xc90f, 0x2e7f, 0xc90f, 0x21, 0 + .dw 0x2ec0, 0xc90f, 0x2eff, 0xc90f, 0x21, 0 + .dw 0x2f40, 0xc90f, 0x2f7f, 0xc90f, 0x21, 0 + .dw 0x2fc0, 0xc90f, 0x2fff, 0xc90f, 0x21, 0 + .dw 0x3040, 0xc90f, 0x307f, 0xc90f, 0x21, 0 + .dw 0x30c0, 0xc90f, 0x30ff, 0xc90f, 0x21, 0 + .dw 0x3140, 0xc90f, 0x317f, 0xc90f, 0x21, 0 + .dw 0x31c0, 0xc90f, 0x31ff, 0xc90f, 0x21, 0 + .dw 0x3240, 0xc90f, 0x327f, 0xc90f, 0x21, 0 + .dw 0x32c0, 0xc90f, 0x32ff, 0xc90f, 0x21, 0 + .dw 0x3340, 0xc90f, 0x337f, 0xc90f, 0x21, 0 + .dw 0x33c0, 0xc90f, 0x33ff, 0xc90f, 0x21, 0 + .dw 0x3440, 0xc90f, 0x347f, 0xc90f, 0x21, 0 + .dw 0x34c0, 0xc90f, 0x34ff, 0xc90f, 0x21, 0 + .dw 0x3540, 0xc90f, 0x357f, 0xc90f, 0x21, 0 + .dw 0x35c0, 0xc90f, 0x35ff, 0xc90f, 0x21, 0 + .dw 0x3640, 0xc90f, 0x367f, 0xc90f, 0x21, 0 + .dw 0x36c0, 0xc90f, 0x36ff, 0xc90f, 0x21, 0 + .dw 0x3740, 0xc90f, 0x377f, 0xc90f, 0x21, 0 + .dw 0x37c0, 0xc90f, 0x37ff, 0xc90f, 0x21, 0 + .dw 0x3840, 0xc90f, 0x387f, 0xc90f, 0x21, 0 + .dw 0x38c0, 0xc90f, 0x38ff, 0xc90f, 0x21, 0 + .dw 0x3940, 0xc90f, 0x397f, 0xc90f, 0x21, 0 + .dw 0x39c0, 0xc90f, 0xffff, 0xc90f, 0x21, 0 + .dw 0x1a00, 0xc910, 0x1fff, 0xc910, 0x21, 0 + .dw 0x3a00, 0xc910, 0x3fff, 0xc910, 0x21, 0 + .dw 0x5a00, 0xc910, 0x5fff, 0xc910, 0x21, 0 + .dw 0x7a00, 0xc910, 0x7fff, 0xc910, 0x21, 0 + .dw 0x9a00, 0xc910, 0x9fff, 0xc910, 0x21, 0 + .dw 0xba00, 0xc910, 0xbfff, 0xc910, 0x21, 0 + .dw 0xda00, 0xc910, 0xdfff, 0xc910, 0x21, 0 + .dw 0xfa00, 0xc910, 0xffff, 0xc910, 0x21, 0 + .dw 0x1a00, 0xc911, 0x1fff, 0xc911, 0x21, 0 + .dw 0x3a00, 0xc911, 0x3fff, 0xc911, 0x21, 0 + .dw 0x5a00, 0xc911, 0x5fff, 0xc911, 0x21, 0 + .dw 0x7a00, 0xc911, 0x7fff, 0xc911, 0x21, 0 + .dw 0x9a00, 0xc911, 0x9fff, 0xc911, 0x21, 0 + .dw 0xba00, 0xc911, 0xbfff, 0xc911, 0x21, 0 + .dw 0xda00, 0xc911, 0xdfff, 0xc911, 0x21, 0 + .dw 0xfa00, 0xc911, 0xffff, 0xc911, 0x21, 0 + .dw 0x1a00, 0xc912, 0x1fff, 0xc912, 0x21, 0 + .dw 0x3a00, 0xc912, 0x3fff, 0xc912, 0x21, 0 + .dw 0x5a00, 0xc912, 0x5fff, 0xc912, 0x21, 0 + .dw 0x7a00, 0xc912, 0x7fff, 0xc912, 0x21, 0 + .dw 0x9a00, 0xc912, 0x9fff, 0xc912, 0x21, 0 + .dw 0xba00, 0xc912, 0xbfff, 0xc912, 0x21, 0 + .dw 0xda00, 0xc912, 0xdfff, 0xc912, 0x21, 0 + .dw 0xfa00, 0xc912, 0xffff, 0xc913, 0x21, 0 + .dw 0x1a00, 0xc914, 0x1fff, 0xc914, 0x21, 0 + .dw 0x3a00, 0xc914, 0x3fff, 0xc914, 0x21, 0 + .dw 0x5a00, 0xc914, 0x5fff, 0xc914, 0x21, 0 + .dw 0x7a00, 0xc914, 0x7fff, 0xc914, 0x21, 0 + .dw 0x9a00, 0xc914, 0x9fff, 0xc914, 0x21, 0 + .dw 0xba00, 0xc914, 0xbfff, 0xc914, 0x21, 0 + .dw 0xda00, 0xc914, 0xdfff, 0xc914, 0x21, 0 + .dw 0xfa00, 0xc914, 0xffff, 0xc914, 0x21, 0 + .dw 0x1a00, 0xc915, 0x1fff, 0xc915, 0x21, 0 + .dw 0x3a00, 0xc915, 0x3fff, 0xc915, 0x21, 0 + .dw 0x5a00, 0xc915, 0x5fff, 0xc915, 0x21, 0 + .dw 0x7a00, 0xc915, 0x7fff, 0xc915, 0x21, 0 + .dw 0x9a00, 0xc915, 0x9fff, 0xc915, 0x21, 0 + .dw 0xba00, 0xc915, 0xbfff, 0xc915, 0x21, 0 + .dw 0xda00, 0xc915, 0xdfff, 0xc915, 0x21, 0 + .dw 0xfa00, 0xc915, 0xffff, 0xc915, 0x21, 0 + .dw 0x1a00, 0xc916, 0x1fff, 0xc916, 0x21, 0 + .dw 0x3a00, 0xc916, 0x3fff, 0xc916, 0x21, 0 + .dw 0x5a00, 0xc916, 0x5fff, 0xc916, 0x21, 0 + .dw 0x7a00, 0xc916, 0x7fff, 0xc916, 0x21, 0 + .dw 0x9a00, 0xc916, 0x9fff, 0xc916, 0x21, 0 + .dw 0xba00, 0xc916, 0xbfff, 0xc916, 0x21, 0 + .dw 0xda00, 0xc916, 0xdfff, 0xc916, 0x21, 0 + .dw 0xfa00, 0xc916, 0xffff, 0xc916, 0x21, 0 + .dw 0x1a00, 0xc917, 0x1fff, 0xc917, 0x21, 0 + .dw 0x3a00, 0xc917, 0x1fff, 0xc918, 0x21, 0 + .dw 0x2040, 0xc918, 0x207f, 0xc918, 0x21, 0 + .dw 0x20c0, 0xc918, 0x20ff, 0xc918, 0x21, 0 + .dw 0x2140, 0xc918, 0x217f, 0xc918, 0x21, 0 + .dw 0x21c0, 0xc918, 0x21ff, 0xc918, 0x21, 0 + .dw 0x2240, 0xc918, 0x227f, 0xc918, 0x21, 0 + .dw 0x22c0, 0xc918, 0x22ff, 0xc918, 0x21, 0 + .dw 0x2340, 0xc918, 0x237f, 0xc918, 0x21, 0 + .dw 0x23c0, 0xc918, 0x23ff, 0xc918, 0x21, 0 + .dw 0x2440, 0xc918, 0x247f, 0xc918, 0x21, 0 + .dw 0x24c0, 0xc918, 0x24ff, 0xc918, 0x21, 0 + .dw 0x2540, 0xc918, 0x257f, 0xc918, 0x21, 0 + .dw 0x25c0, 0xc918, 0x25ff, 0xc918, 0x21, 0 + .dw 0x2640, 0xc918, 0x267f, 0xc918, 0x21, 0 + .dw 0x26c0, 0xc918, 0x26ff, 0xc918, 0x21, 0 + .dw 0x2740, 0xc918, 0x277f, 0xc918, 0x21, 0 + .dw 0x27c0, 0xc918, 0x27ff, 0xc918, 0x21, 0 + .dw 0x2840, 0xc918, 0x287f, 0xc918, 0x21, 0 + .dw 0x28c0, 0xc918, 0x28ff, 0xc918, 0x21, 0 + .dw 0x2940, 0xc918, 0x297f, 0xc918, 0x21, 0 + .dw 0x29c0, 0xc918, 0x29ff, 0xc918, 0x21, 0 + .dw 0x2a40, 0xc918, 0x2a7f, 0xc918, 0x21, 0 + .dw 0x2ac0, 0xc918, 0x2aff, 0xc918, 0x21, 0 + .dw 0x2b40, 0xc918, 0x2b7f, 0xc918, 0x21, 0 + .dw 0x2bc0, 0xc918, 0x2bff, 0xc918, 0x21, 0 + .dw 0x2c40, 0xc918, 0x2c7f, 0xc918, 0x21, 0 + .dw 0x2cc0, 0xc918, 0x2cff, 0xc918, 0x21, 0 + .dw 0x2d40, 0xc918, 0x2d7f, 0xc918, 0x21, 0 + .dw 0x2dc0, 0xc918, 0x2dff, 0xc918, 0x21, 0 + .dw 0x2e40, 0xc918, 0x2e7f, 0xc918, 0x21, 0 + .dw 0x2ec0, 0xc918, 0x2eff, 0xc918, 0x21, 0 + .dw 0x2f40, 0xc918, 0x2f7f, 0xc918, 0x21, 0 + .dw 0x2fc0, 0xc918, 0x2fff, 0xc918, 0x21, 0 + .dw 0x3040, 0xc918, 0x307f, 0xc918, 0x21, 0 + .dw 0x30c0, 0xc918, 0x30ff, 0xc918, 0x21, 0 + .dw 0x3140, 0xc918, 0x317f, 0xc918, 0x21, 0 + .dw 0x31c0, 0xc918, 0x31ff, 0xc918, 0x21, 0 + .dw 0x3240, 0xc918, 0x327f, 0xc918, 0x21, 0 + .dw 0x32c0, 0xc918, 0x32ff, 0xc918, 0x21, 0 + .dw 0x3340, 0xc918, 0x337f, 0xc918, 0x21, 0 + .dw 0x33c0, 0xc918, 0x33ff, 0xc918, 0x21, 0 + .dw 0x3440, 0xc918, 0x347f, 0xc918, 0x21, 0 + .dw 0x34c0, 0xc918, 0x34ff, 0xc918, 0x21, 0 + .dw 0x3540, 0xc918, 0x357f, 0xc918, 0x21, 0 + .dw 0x35c0, 0xc918, 0x35ff, 0xc918, 0x21, 0 + .dw 0x3640, 0xc918, 0x367f, 0xc918, 0x21, 0 + .dw 0x36c0, 0xc918, 0x36ff, 0xc918, 0x21, 0 + .dw 0x3740, 0xc918, 0x377f, 0xc918, 0x21, 0 + .dw 0x37c0, 0xc918, 0x37ff, 0xc918, 0x21, 0 + .dw 0x3840, 0xc918, 0x387f, 0xc918, 0x21, 0 + .dw 0x38c0, 0xc918, 0x38ff, 0xc918, 0x21, 0 + .dw 0x3940, 0xc918, 0x397f, 0xc918, 0x21, 0 + .dw 0x39c0, 0xc918, 0x5fff, 0xc918, 0x21, 0 + .dw 0x6040, 0xc918, 0x607f, 0xc918, 0x21, 0 + .dw 0x60c0, 0xc918, 0x60ff, 0xc918, 0x21, 0 + .dw 0x6140, 0xc918, 0x617f, 0xc918, 0x21, 0 + .dw 0x61c0, 0xc918, 0x61ff, 0xc918, 0x21, 0 + .dw 0x6240, 0xc918, 0x627f, 0xc918, 0x21, 0 + .dw 0x62c0, 0xc918, 0x62ff, 0xc918, 0x21, 0 + .dw 0x6340, 0xc918, 0x637f, 0xc918, 0x21, 0 + .dw 0x63c0, 0xc918, 0x63ff, 0xc918, 0x21, 0 + .dw 0x6440, 0xc918, 0x647f, 0xc918, 0x21, 0 + .dw 0x64c0, 0xc918, 0x64ff, 0xc918, 0x21, 0 + .dw 0x6540, 0xc918, 0x657f, 0xc918, 0x21, 0 + .dw 0x65c0, 0xc918, 0x65ff, 0xc918, 0x21, 0 + .dw 0x6640, 0xc918, 0x667f, 0xc918, 0x21, 0 + .dw 0x66c0, 0xc918, 0x66ff, 0xc918, 0x21, 0 + .dw 0x6740, 0xc918, 0x677f, 0xc918, 0x21, 0 + .dw 0x67c0, 0xc918, 0x67ff, 0xc918, 0x21, 0 + .dw 0x6840, 0xc918, 0x687f, 0xc918, 0x21, 0 + .dw 0x68c0, 0xc918, 0x68ff, 0xc918, 0x21, 0 + .dw 0x6940, 0xc918, 0x697f, 0xc918, 0x21, 0 + .dw 0x69c0, 0xc918, 0x69ff, 0xc918, 0x21, 0 + .dw 0x6a40, 0xc918, 0x6a7f, 0xc918, 0x21, 0 + .dw 0x6ac0, 0xc918, 0x6aff, 0xc918, 0x21, 0 + .dw 0x6b40, 0xc918, 0x6b7f, 0xc918, 0x21, 0 + .dw 0x6bc0, 0xc918, 0x6bff, 0xc918, 0x21, 0 + .dw 0x6c40, 0xc918, 0x6c7f, 0xc918, 0x21, 0 + .dw 0x6cc0, 0xc918, 0x6cff, 0xc918, 0x21, 0 + .dw 0x6d40, 0xc918, 0x6d7f, 0xc918, 0x21, 0 + .dw 0x6dc0, 0xc918, 0x6dff, 0xc918, 0x21, 0 + .dw 0x6e40, 0xc918, 0x6e7f, 0xc918, 0x21, 0 + .dw 0x6ec0, 0xc918, 0x6eff, 0xc918, 0x21, 0 + .dw 0x6f40, 0xc918, 0x6f7f, 0xc918, 0x21, 0 + .dw 0x6fc0, 0xc918, 0x6fff, 0xc918, 0x21, 0 + .dw 0x7040, 0xc918, 0x707f, 0xc918, 0x21, 0 + .dw 0x70c0, 0xc918, 0x70ff, 0xc918, 0x21, 0 + .dw 0x7140, 0xc918, 0x717f, 0xc918, 0x21, 0 + .dw 0x71c0, 0xc918, 0x71ff, 0xc918, 0x21, 0 + .dw 0x7240, 0xc918, 0x727f, 0xc918, 0x21, 0 + .dw 0x72c0, 0xc918, 0x72ff, 0xc918, 0x21, 0 + .dw 0x7340, 0xc918, 0x737f, 0xc918, 0x21, 0 + .dw 0x73c0, 0xc918, 0x73ff, 0xc918, 0x21, 0 + .dw 0x7440, 0xc918, 0x747f, 0xc918, 0x21, 0 + .dw 0x74c0, 0xc918, 0x74ff, 0xc918, 0x21, 0 + .dw 0x7540, 0xc918, 0x757f, 0xc918, 0x21, 0 + .dw 0x75c0, 0xc918, 0x75ff, 0xc918, 0x21, 0 + .dw 0x7640, 0xc918, 0x767f, 0xc918, 0x21, 0 + .dw 0x76c0, 0xc918, 0x76ff, 0xc918, 0x21, 0 + .dw 0x7740, 0xc918, 0x777f, 0xc918, 0x21, 0 + .dw 0x77c0, 0xc918, 0x77ff, 0xc918, 0x21, 0 + .dw 0x7840, 0xc918, 0x787f, 0xc918, 0x21, 0 + .dw 0x78c0, 0xc918, 0x78ff, 0xc918, 0x21, 0 + .dw 0x7940, 0xc918, 0x797f, 0xc918, 0x21, 0 + .dw 0x79c0, 0xc918, 0x9fff, 0xc918, 0x21, 0 + .dw 0xa040, 0xc918, 0xa07f, 0xc918, 0x21, 0 + .dw 0xa0c0, 0xc918, 0xa0ff, 0xc918, 0x21, 0 + .dw 0xa140, 0xc918, 0xa17f, 0xc918, 0x21, 0 + .dw 0xa1c0, 0xc918, 0xa1ff, 0xc918, 0x21, 0 + .dw 0xa240, 0xc918, 0xa27f, 0xc918, 0x21, 0 + .dw 0xa2c0, 0xc918, 0xa2ff, 0xc918, 0x21, 0 + .dw 0xa340, 0xc918, 0xa37f, 0xc918, 0x21, 0 + .dw 0xa3c0, 0xc918, 0xa3ff, 0xc918, 0x21, 0 + .dw 0xa440, 0xc918, 0xa47f, 0xc918, 0x21, 0 + .dw 0xa4c0, 0xc918, 0xa4ff, 0xc918, 0x21, 0 + .dw 0xa540, 0xc918, 0xa57f, 0xc918, 0x21, 0 + .dw 0xa5c0, 0xc918, 0xa5ff, 0xc918, 0x21, 0 + .dw 0xa640, 0xc918, 0xa67f, 0xc918, 0x21, 0 + .dw 0xa6c0, 0xc918, 0xa6ff, 0xc918, 0x21, 0 + .dw 0xa740, 0xc918, 0xa77f, 0xc918, 0x21, 0 + .dw 0xa7c0, 0xc918, 0xa7ff, 0xc918, 0x21, 0 + .dw 0xa840, 0xc918, 0xa87f, 0xc918, 0x21, 0 + .dw 0xa8c0, 0xc918, 0xa8ff, 0xc918, 0x21, 0 + .dw 0xa940, 0xc918, 0xa97f, 0xc918, 0x21, 0 + .dw 0xa9c0, 0xc918, 0xa9ff, 0xc918, 0x21, 0 + .dw 0xaa40, 0xc918, 0xaa7f, 0xc918, 0x21, 0 + .dw 0xaac0, 0xc918, 0xaaff, 0xc918, 0x21, 0 + .dw 0xab40, 0xc918, 0xab7f, 0xc918, 0x21, 0 + .dw 0xabc0, 0xc918, 0xabff, 0xc918, 0x21, 0 + .dw 0xac40, 0xc918, 0xac7f, 0xc918, 0x21, 0 + .dw 0xacc0, 0xc918, 0xacff, 0xc918, 0x21, 0 + .dw 0xad40, 0xc918, 0xad7f, 0xc918, 0x21, 0 + .dw 0xadc0, 0xc918, 0xadff, 0xc918, 0x21, 0 + .dw 0xae40, 0xc918, 0xae7f, 0xc918, 0x21, 0 + .dw 0xaec0, 0xc918, 0xaeff, 0xc918, 0x21, 0 + .dw 0xaf40, 0xc918, 0xaf7f, 0xc918, 0x21, 0 + .dw 0xafc0, 0xc918, 0xafff, 0xc918, 0x21, 0 + .dw 0xb040, 0xc918, 0xb07f, 0xc918, 0x21, 0 + .dw 0xb0c0, 0xc918, 0xb0ff, 0xc918, 0x21, 0 + .dw 0xb140, 0xc918, 0xb17f, 0xc918, 0x21, 0 + .dw 0xb1c0, 0xc918, 0xb1ff, 0xc918, 0x21, 0 + .dw 0xb240, 0xc918, 0xb27f, 0xc918, 0x21, 0 + .dw 0xb2c0, 0xc918, 0xb2ff, 0xc918, 0x21, 0 + .dw 0xb340, 0xc918, 0xb37f, 0xc918, 0x21, 0 + .dw 0xb3c0, 0xc918, 0xb3ff, 0xc918, 0x21, 0 + .dw 0xb440, 0xc918, 0xb47f, 0xc918, 0x21, 0 + .dw 0xb4c0, 0xc918, 0xb4ff, 0xc918, 0x21, 0 + .dw 0xb540, 0xc918, 0xb57f, 0xc918, 0x21, 0 + .dw 0xb5c0, 0xc918, 0xb5ff, 0xc918, 0x21, 0 + .dw 0xb640, 0xc918, 0xb67f, 0xc918, 0x21, 0 + .dw 0xb6c0, 0xc918, 0xb6ff, 0xc918, 0x21, 0 + .dw 0xb740, 0xc918, 0xb77f, 0xc918, 0x21, 0 + .dw 0xb7c0, 0xc918, 0xb7ff, 0xc918, 0x21, 0 + .dw 0xb840, 0xc918, 0xb87f, 0xc918, 0x21, 0 + .dw 0xb8c0, 0xc918, 0xb8ff, 0xc918, 0x21, 0 + .dw 0xb940, 0xc918, 0xb97f, 0xc918, 0x21, 0 + .dw 0xb9c0, 0xc918, 0xdfff, 0xc918, 0x21, 0 + .dw 0xe040, 0xc918, 0xe07f, 0xc918, 0x21, 0 + .dw 0xe0c0, 0xc918, 0xe0ff, 0xc918, 0x21, 0 + .dw 0xe140, 0xc918, 0xe17f, 0xc918, 0x21, 0 + .dw 0xe1c0, 0xc918, 0xe1ff, 0xc918, 0x21, 0 + .dw 0xe240, 0xc918, 0xe27f, 0xc918, 0x21, 0 + .dw 0xe2c0, 0xc918, 0xe2ff, 0xc918, 0x21, 0 + .dw 0xe340, 0xc918, 0xe37f, 0xc918, 0x21, 0 + .dw 0xe3c0, 0xc918, 0xe3ff, 0xc918, 0x21, 0 + .dw 0xe440, 0xc918, 0xe47f, 0xc918, 0x21, 0 + .dw 0xe4c0, 0xc918, 0xe4ff, 0xc918, 0x21, 0 + .dw 0xe540, 0xc918, 0xe57f, 0xc918, 0x21, 0 + .dw 0xe5c0, 0xc918, 0xe5ff, 0xc918, 0x21, 0 + .dw 0xe640, 0xc918, 0xe67f, 0xc918, 0x21, 0 + .dw 0xe6c0, 0xc918, 0xe6ff, 0xc918, 0x21, 0 + .dw 0xe740, 0xc918, 0xe77f, 0xc918, 0x21, 0 + .dw 0xe7c0, 0xc918, 0xe7ff, 0xc918, 0x21, 0 + .dw 0xe840, 0xc918, 0xe87f, 0xc918, 0x21, 0 + .dw 0xe8c0, 0xc918, 0xe8ff, 0xc918, 0x21, 0 + .dw 0xe940, 0xc918, 0xe97f, 0xc918, 0x21, 0 + .dw 0xe9c0, 0xc918, 0xe9ff, 0xc918, 0x21, 0 + .dw 0xea40, 0xc918, 0xea7f, 0xc918, 0x21, 0 + .dw 0xeac0, 0xc918, 0xeaff, 0xc918, 0x21, 0 + .dw 0xeb40, 0xc918, 0xeb7f, 0xc918, 0x21, 0 + .dw 0xebc0, 0xc918, 0xebff, 0xc918, 0x21, 0 + .dw 0xec40, 0xc918, 0xec7f, 0xc918, 0x21, 0 + .dw 0xecc0, 0xc918, 0xecff, 0xc918, 0x21, 0 + .dw 0xed40, 0xc918, 0xed7f, 0xc918, 0x21, 0 + .dw 0xedc0, 0xc918, 0xedff, 0xc918, 0x21, 0 + .dw 0xee40, 0xc918, 0xee7f, 0xc918, 0x21, 0 + .dw 0xeec0, 0xc918, 0xeeff, 0xc918, 0x21, 0 + .dw 0xef40, 0xc918, 0xef7f, 0xc918, 0x21, 0 + .dw 0xefc0, 0xc918, 0xefff, 0xc918, 0x21, 0 + .dw 0xf040, 0xc918, 0xf07f, 0xc918, 0x21, 0 + .dw 0xf0c0, 0xc918, 0xf0ff, 0xc918, 0x21, 0 + .dw 0xf140, 0xc918, 0xf17f, 0xc918, 0x21, 0 + .dw 0xf1c0, 0xc918, 0xf1ff, 0xc918, 0x21, 0 + .dw 0xf240, 0xc918, 0xf27f, 0xc918, 0x21, 0 + .dw 0xf2c0, 0xc918, 0xf2ff, 0xc918, 0x21, 0 + .dw 0xf340, 0xc918, 0xf37f, 0xc918, 0x21, 0 + .dw 0xf3c0, 0xc918, 0xf3ff, 0xc918, 0x21, 0 + .dw 0xf440, 0xc918, 0xf47f, 0xc918, 0x21, 0 + .dw 0xf4c0, 0xc918, 0xf4ff, 0xc918, 0x21, 0 + .dw 0xf540, 0xc918, 0xf57f, 0xc918, 0x21, 0 + .dw 0xf5c0, 0xc918, 0xf5ff, 0xc918, 0x21, 0 + .dw 0xf640, 0xc918, 0xf67f, 0xc918, 0x21, 0 + .dw 0xf6c0, 0xc918, 0xf6ff, 0xc918, 0x21, 0 + .dw 0xf740, 0xc918, 0xf77f, 0xc918, 0x21, 0 + .dw 0xf7c0, 0xc918, 0xf7ff, 0xc918, 0x21, 0 + .dw 0xf840, 0xc918, 0xf87f, 0xc918, 0x21, 0 + .dw 0xf8c0, 0xc918, 0xf8ff, 0xc918, 0x21, 0 + .dw 0xf940, 0xc918, 0xf97f, 0xc918, 0x21, 0 + .dw 0xf9c0, 0xc918, 0x1fff, 0xc919, 0x21, 0 + .dw 0x2040, 0xc919, 0x207f, 0xc919, 0x21, 0 + .dw 0x20c0, 0xc919, 0x20ff, 0xc919, 0x21, 0 + .dw 0x2140, 0xc919, 0x217f, 0xc919, 0x21, 0 + .dw 0x21c0, 0xc919, 0x21ff, 0xc919, 0x21, 0 + .dw 0x2240, 0xc919, 0x227f, 0xc919, 0x21, 0 + .dw 0x22c0, 0xc919, 0x22ff, 0xc919, 0x21, 0 + .dw 0x2340, 0xc919, 0x237f, 0xc919, 0x21, 0 + .dw 0x23c0, 0xc919, 0x23ff, 0xc919, 0x21, 0 + .dw 0x2440, 0xc919, 0x247f, 0xc919, 0x21, 0 + .dw 0x24c0, 0xc919, 0x24ff, 0xc919, 0x21, 0 + .dw 0x2540, 0xc919, 0x257f, 0xc919, 0x21, 0 + .dw 0x25c0, 0xc919, 0x25ff, 0xc919, 0x21, 0 + .dw 0x2640, 0xc919, 0x267f, 0xc919, 0x21, 0 + .dw 0x26c0, 0xc919, 0x26ff, 0xc919, 0x21, 0 + .dw 0x2740, 0xc919, 0x277f, 0xc919, 0x21, 0 + .dw 0x27c0, 0xc919, 0x27ff, 0xc919, 0x21, 0 + .dw 0x2840, 0xc919, 0x287f, 0xc919, 0x21, 0 + .dw 0x28c0, 0xc919, 0x28ff, 0xc919, 0x21, 0 + .dw 0x2940, 0xc919, 0x297f, 0xc919, 0x21, 0 + .dw 0x29c0, 0xc919, 0x29ff, 0xc919, 0x21, 0 + .dw 0x2a40, 0xc919, 0x2a7f, 0xc919, 0x21, 0 + .dw 0x2ac0, 0xc919, 0x2aff, 0xc919, 0x21, 0 + .dw 0x2b40, 0xc919, 0x2b7f, 0xc919, 0x21, 0 + .dw 0x2bc0, 0xc919, 0x2bff, 0xc919, 0x21, 0 + .dw 0x2c40, 0xc919, 0x2c7f, 0xc919, 0x21, 0 + .dw 0x2cc0, 0xc919, 0x2cff, 0xc919, 0x21, 0 + .dw 0x2d40, 0xc919, 0x2d7f, 0xc919, 0x21, 0 + .dw 0x2dc0, 0xc919, 0x2dff, 0xc919, 0x21, 0 + .dw 0x2e40, 0xc919, 0x2e7f, 0xc919, 0x21, 0 + .dw 0x2ec0, 0xc919, 0x2eff, 0xc919, 0x21, 0 + .dw 0x2f40, 0xc919, 0x2f7f, 0xc919, 0x21, 0 + .dw 0x2fc0, 0xc919, 0x2fff, 0xc919, 0x21, 0 + .dw 0x3040, 0xc919, 0x307f, 0xc919, 0x21, 0 + .dw 0x30c0, 0xc919, 0x30ff, 0xc919, 0x21, 0 + .dw 0x3140, 0xc919, 0x317f, 0xc919, 0x21, 0 + .dw 0x31c0, 0xc919, 0x31ff, 0xc919, 0x21, 0 + .dw 0x3240, 0xc919, 0x327f, 0xc919, 0x21, 0 + .dw 0x32c0, 0xc919, 0x32ff, 0xc919, 0x21, 0 + .dw 0x3340, 0xc919, 0x337f, 0xc919, 0x21, 0 + .dw 0x33c0, 0xc919, 0x33ff, 0xc919, 0x21, 0 + .dw 0x3440, 0xc919, 0x347f, 0xc919, 0x21, 0 + .dw 0x34c0, 0xc919, 0x34ff, 0xc919, 0x21, 0 + .dw 0x3540, 0xc919, 0x357f, 0xc919, 0x21, 0 + .dw 0x35c0, 0xc919, 0x35ff, 0xc919, 0x21, 0 + .dw 0x3640, 0xc919, 0x367f, 0xc919, 0x21, 0 + .dw 0x36c0, 0xc919, 0x36ff, 0xc919, 0x21, 0 + .dw 0x3740, 0xc919, 0x377f, 0xc919, 0x21, 0 + .dw 0x37c0, 0xc919, 0x37ff, 0xc919, 0x21, 0 + .dw 0x3840, 0xc919, 0x387f, 0xc919, 0x21, 0 + .dw 0x38c0, 0xc919, 0x38ff, 0xc919, 0x21, 0 + .dw 0x3940, 0xc919, 0x397f, 0xc919, 0x21, 0 + .dw 0x39c0, 0xc919, 0x5fff, 0xc919, 0x21, 0 + .dw 0x6040, 0xc919, 0x607f, 0xc919, 0x21, 0 + .dw 0x60c0, 0xc919, 0x60ff, 0xc919, 0x21, 0 + .dw 0x6140, 0xc919, 0x617f, 0xc919, 0x21, 0 + .dw 0x61c0, 0xc919, 0x61ff, 0xc919, 0x21, 0 + .dw 0x6240, 0xc919, 0x627f, 0xc919, 0x21, 0 + .dw 0x62c0, 0xc919, 0x62ff, 0xc919, 0x21, 0 + .dw 0x6340, 0xc919, 0x637f, 0xc919, 0x21, 0 + .dw 0x63c0, 0xc919, 0x63ff, 0xc919, 0x21, 0 + .dw 0x6440, 0xc919, 0x647f, 0xc919, 0x21, 0 + .dw 0x64c0, 0xc919, 0x64ff, 0xc919, 0x21, 0 + .dw 0x6540, 0xc919, 0x657f, 0xc919, 0x21, 0 + .dw 0x65c0, 0xc919, 0x65ff, 0xc919, 0x21, 0 + .dw 0x6640, 0xc919, 0x667f, 0xc919, 0x21, 0 + .dw 0x66c0, 0xc919, 0x66ff, 0xc919, 0x21, 0 + .dw 0x6740, 0xc919, 0x677f, 0xc919, 0x21, 0 + .dw 0x67c0, 0xc919, 0x67ff, 0xc919, 0x21, 0 + .dw 0x6840, 0xc919, 0x687f, 0xc919, 0x21, 0 + .dw 0x68c0, 0xc919, 0x68ff, 0xc919, 0x21, 0 + .dw 0x6940, 0xc919, 0x697f, 0xc919, 0x21, 0 + .dw 0x69c0, 0xc919, 0x69ff, 0xc919, 0x21, 0 + .dw 0x6a40, 0xc919, 0x6a7f, 0xc919, 0x21, 0 + .dw 0x6ac0, 0xc919, 0x6aff, 0xc919, 0x21, 0 + .dw 0x6b40, 0xc919, 0x6b7f, 0xc919, 0x21, 0 + .dw 0x6bc0, 0xc919, 0x6bff, 0xc919, 0x21, 0 + .dw 0x6c40, 0xc919, 0x6c7f, 0xc919, 0x21, 0 + .dw 0x6cc0, 0xc919, 0x6cff, 0xc919, 0x21, 0 + .dw 0x6d40, 0xc919, 0x6d7f, 0xc919, 0x21, 0 + .dw 0x6dc0, 0xc919, 0x6dff, 0xc919, 0x21, 0 + .dw 0x6e40, 0xc919, 0x6e7f, 0xc919, 0x21, 0 + .dw 0x6ec0, 0xc919, 0x6eff, 0xc919, 0x21, 0 + .dw 0x6f40, 0xc919, 0x6f7f, 0xc919, 0x21, 0 + .dw 0x6fc0, 0xc919, 0x6fff, 0xc919, 0x21, 0 + .dw 0x7040, 0xc919, 0x707f, 0xc919, 0x21, 0 + .dw 0x70c0, 0xc919, 0x70ff, 0xc919, 0x21, 0 + .dw 0x7140, 0xc919, 0x717f, 0xc919, 0x21, 0 + .dw 0x71c0, 0xc919, 0x71ff, 0xc919, 0x21, 0 + .dw 0x7240, 0xc919, 0x727f, 0xc919, 0x21, 0 + .dw 0x72c0, 0xc919, 0x72ff, 0xc919, 0x21, 0 + .dw 0x7340, 0xc919, 0x737f, 0xc919, 0x21, 0 + .dw 0x73c0, 0xc919, 0x73ff, 0xc919, 0x21, 0 + .dw 0x7440, 0xc919, 0x747f, 0xc919, 0x21, 0 + .dw 0x74c0, 0xc919, 0x74ff, 0xc919, 0x21, 0 + .dw 0x7540, 0xc919, 0x757f, 0xc919, 0x21, 0 + .dw 0x75c0, 0xc919, 0x75ff, 0xc919, 0x21, 0 + .dw 0x7640, 0xc919, 0x767f, 0xc919, 0x21, 0 + .dw 0x76c0, 0xc919, 0x76ff, 0xc919, 0x21, 0 + .dw 0x7740, 0xc919, 0x777f, 0xc919, 0x21, 0 + .dw 0x77c0, 0xc919, 0x77ff, 0xc919, 0x21, 0 + .dw 0x7840, 0xc919, 0x787f, 0xc919, 0x21, 0 + .dw 0x78c0, 0xc919, 0x78ff, 0xc919, 0x21, 0 + .dw 0x7940, 0xc919, 0x797f, 0xc919, 0x21, 0 + .dw 0x79c0, 0xc919, 0x9fff, 0xc919, 0x21, 0 + .dw 0xa040, 0xc919, 0xa07f, 0xc919, 0x21, 0 + .dw 0xa0c0, 0xc919, 0xa0ff, 0xc919, 0x21, 0 + .dw 0xa140, 0xc919, 0xa17f, 0xc919, 0x21, 0 + .dw 0xa1c0, 0xc919, 0xa1ff, 0xc919, 0x21, 0 + .dw 0xa240, 0xc919, 0xa27f, 0xc919, 0x21, 0 + .dw 0xa2c0, 0xc919, 0xa2ff, 0xc919, 0x21, 0 + .dw 0xa340, 0xc919, 0xa37f, 0xc919, 0x21, 0 + .dw 0xa3c0, 0xc919, 0xa3ff, 0xc919, 0x21, 0 + .dw 0xa440, 0xc919, 0xa47f, 0xc919, 0x21, 0 + .dw 0xa4c0, 0xc919, 0xa4ff, 0xc919, 0x21, 0 + .dw 0xa540, 0xc919, 0xa57f, 0xc919, 0x21, 0 + .dw 0xa5c0, 0xc919, 0xa5ff, 0xc919, 0x21, 0 + .dw 0xa640, 0xc919, 0xa67f, 0xc919, 0x21, 0 + .dw 0xa6c0, 0xc919, 0xa6ff, 0xc919, 0x21, 0 + .dw 0xa740, 0xc919, 0xa77f, 0xc919, 0x21, 0 + .dw 0xa7c0, 0xc919, 0xa7ff, 0xc919, 0x21, 0 + .dw 0xa840, 0xc919, 0xa87f, 0xc919, 0x21, 0 + .dw 0xa8c0, 0xc919, 0xa8ff, 0xc919, 0x21, 0 + .dw 0xa940, 0xc919, 0xa97f, 0xc919, 0x21, 0 + .dw 0xa9c0, 0xc919, 0xa9ff, 0xc919, 0x21, 0 + .dw 0xaa40, 0xc919, 0xaa7f, 0xc919, 0x21, 0 + .dw 0xaac0, 0xc919, 0xaaff, 0xc919, 0x21, 0 + .dw 0xab40, 0xc919, 0xab7f, 0xc919, 0x21, 0 + .dw 0xabc0, 0xc919, 0xabff, 0xc919, 0x21, 0 + .dw 0xac40, 0xc919, 0xac7f, 0xc919, 0x21, 0 + .dw 0xacc0, 0xc919, 0xacff, 0xc919, 0x21, 0 + .dw 0xad40, 0xc919, 0xad7f, 0xc919, 0x21, 0 + .dw 0xadc0, 0xc919, 0xadff, 0xc919, 0x21, 0 + .dw 0xae40, 0xc919, 0xae7f, 0xc919, 0x21, 0 + .dw 0xaec0, 0xc919, 0xaeff, 0xc919, 0x21, 0 + .dw 0xaf40, 0xc919, 0xaf7f, 0xc919, 0x21, 0 + .dw 0xafc0, 0xc919, 0xafff, 0xc919, 0x21, 0 + .dw 0xb040, 0xc919, 0xb07f, 0xc919, 0x21, 0 + .dw 0xb0c0, 0xc919, 0xb0ff, 0xc919, 0x21, 0 + .dw 0xb140, 0xc919, 0xb17f, 0xc919, 0x21, 0 + .dw 0xb1c0, 0xc919, 0xb1ff, 0xc919, 0x21, 0 + .dw 0xb240, 0xc919, 0xb27f, 0xc919, 0x21, 0 + .dw 0xb2c0, 0xc919, 0xb2ff, 0xc919, 0x21, 0 + .dw 0xb340, 0xc919, 0xb37f, 0xc919, 0x21, 0 + .dw 0xb3c0, 0xc919, 0xb3ff, 0xc919, 0x21, 0 + .dw 0xb440, 0xc919, 0xb47f, 0xc919, 0x21, 0 + .dw 0xb4c0, 0xc919, 0xb4ff, 0xc919, 0x21, 0 + .dw 0xb540, 0xc919, 0xb57f, 0xc919, 0x21, 0 + .dw 0xb5c0, 0xc919, 0xb5ff, 0xc919, 0x21, 0 + .dw 0xb640, 0xc919, 0xb67f, 0xc919, 0x21, 0 + .dw 0xb6c0, 0xc919, 0xb6ff, 0xc919, 0x21, 0 + .dw 0xb740, 0xc919, 0xb77f, 0xc919, 0x21, 0 + .dw 0xb7c0, 0xc919, 0xb7ff, 0xc919, 0x21, 0 + .dw 0xb840, 0xc919, 0xb87f, 0xc919, 0x21, 0 + .dw 0xb8c0, 0xc919, 0xb8ff, 0xc919, 0x21, 0 + .dw 0xb940, 0xc919, 0xb97f, 0xc919, 0x21, 0 + .dw 0xb9c0, 0xc919, 0xdfff, 0xc919, 0x21, 0 + .dw 0xe040, 0xc919, 0xe07f, 0xc919, 0x21, 0 + .dw 0xe0c0, 0xc919, 0xe0ff, 0xc919, 0x21, 0 + .dw 0xe140, 0xc919, 0xe17f, 0xc919, 0x21, 0 + .dw 0xe1c0, 0xc919, 0xe1ff, 0xc919, 0x21, 0 + .dw 0xe240, 0xc919, 0xe27f, 0xc919, 0x21, 0 + .dw 0xe2c0, 0xc919, 0xe2ff, 0xc919, 0x21, 0 + .dw 0xe340, 0xc919, 0xe37f, 0xc919, 0x21, 0 + .dw 0xe3c0, 0xc919, 0xe3ff, 0xc919, 0x21, 0 + .dw 0xe440, 0xc919, 0xe47f, 0xc919, 0x21, 0 + .dw 0xe4c0, 0xc919, 0xe4ff, 0xc919, 0x21, 0 + .dw 0xe540, 0xc919, 0xe57f, 0xc919, 0x21, 0 + .dw 0xe5c0, 0xc919, 0xe5ff, 0xc919, 0x21, 0 + .dw 0xe640, 0xc919, 0xe67f, 0xc919, 0x21, 0 + .dw 0xe6c0, 0xc919, 0xe6ff, 0xc919, 0x21, 0 + .dw 0xe740, 0xc919, 0xe77f, 0xc919, 0x21, 0 + .dw 0xe7c0, 0xc919, 0xe7ff, 0xc919, 0x21, 0 + .dw 0xe840, 0xc919, 0xe87f, 0xc919, 0x21, 0 + .dw 0xe8c0, 0xc919, 0xe8ff, 0xc919, 0x21, 0 + .dw 0xe940, 0xc919, 0xe97f, 0xc919, 0x21, 0 + .dw 0xe9c0, 0xc919, 0xe9ff, 0xc919, 0x21, 0 + .dw 0xea40, 0xc919, 0xea7f, 0xc919, 0x21, 0 + .dw 0xeac0, 0xc919, 0xeaff, 0xc919, 0x21, 0 + .dw 0xeb40, 0xc919, 0xeb7f, 0xc919, 0x21, 0 + .dw 0xebc0, 0xc919, 0xebff, 0xc919, 0x21, 0 + .dw 0xec40, 0xc919, 0xec7f, 0xc919, 0x21, 0 + .dw 0xecc0, 0xc919, 0xecff, 0xc919, 0x21, 0 + .dw 0xed40, 0xc919, 0xed7f, 0xc919, 0x21, 0 + .dw 0xedc0, 0xc919, 0xedff, 0xc919, 0x21, 0 + .dw 0xee40, 0xc919, 0xee7f, 0xc919, 0x21, 0 + .dw 0xeec0, 0xc919, 0xeeff, 0xc919, 0x21, 0 + .dw 0xef40, 0xc919, 0xef7f, 0xc919, 0x21, 0 + .dw 0xefc0, 0xc919, 0xefff, 0xc919, 0x21, 0 + .dw 0xf040, 0xc919, 0xf07f, 0xc919, 0x21, 0 + .dw 0xf0c0, 0xc919, 0xf0ff, 0xc919, 0x21, 0 + .dw 0xf140, 0xc919, 0xf17f, 0xc919, 0x21, 0 + .dw 0xf1c0, 0xc919, 0xf1ff, 0xc919, 0x21, 0 + .dw 0xf240, 0xc919, 0xf27f, 0xc919, 0x21, 0 + .dw 0xf2c0, 0xc919, 0xf2ff, 0xc919, 0x21, 0 + .dw 0xf340, 0xc919, 0xf37f, 0xc919, 0x21, 0 + .dw 0xf3c0, 0xc919, 0xf3ff, 0xc919, 0x21, 0 + .dw 0xf440, 0xc919, 0xf47f, 0xc919, 0x21, 0 + .dw 0xf4c0, 0xc919, 0xf4ff, 0xc919, 0x21, 0 + .dw 0xf540, 0xc919, 0xf57f, 0xc919, 0x21, 0 + .dw 0xf5c0, 0xc919, 0xf5ff, 0xc919, 0x21, 0 + .dw 0xf640, 0xc919, 0xf67f, 0xc919, 0x21, 0 + .dw 0xf6c0, 0xc919, 0xf6ff, 0xc919, 0x21, 0 + .dw 0xf740, 0xc919, 0xf77f, 0xc919, 0x21, 0 + .dw 0xf7c0, 0xc919, 0xf7ff, 0xc919, 0x21, 0 + .dw 0xf840, 0xc919, 0xf87f, 0xc919, 0x21, 0 + .dw 0xf8c0, 0xc919, 0xf8ff, 0xc919, 0x21, 0 + .dw 0xf940, 0xc919, 0xf97f, 0xc919, 0x21, 0 + .dw 0xf9c0, 0xc919, 0x1fff, 0xc91a, 0x21, 0 + .dw 0x2040, 0xc91a, 0x207f, 0xc91a, 0x21, 0 + .dw 0x20c0, 0xc91a, 0x20ff, 0xc91a, 0x21, 0 + .dw 0x2140, 0xc91a, 0x217f, 0xc91a, 0x21, 0 + .dw 0x21c0, 0xc91a, 0x21ff, 0xc91a, 0x21, 0 + .dw 0x2240, 0xc91a, 0x227f, 0xc91a, 0x21, 0 + .dw 0x22c0, 0xc91a, 0x22ff, 0xc91a, 0x21, 0 + .dw 0x2340, 0xc91a, 0x237f, 0xc91a, 0x21, 0 + .dw 0x23c0, 0xc91a, 0x23ff, 0xc91a, 0x21, 0 + .dw 0x2440, 0xc91a, 0x247f, 0xc91a, 0x21, 0 + .dw 0x24c0, 0xc91a, 0x24ff, 0xc91a, 0x21, 0 + .dw 0x2540, 0xc91a, 0x257f, 0xc91a, 0x21, 0 + .dw 0x25c0, 0xc91a, 0x25ff, 0xc91a, 0x21, 0 + .dw 0x2640, 0xc91a, 0x267f, 0xc91a, 0x21, 0 + .dw 0x26c0, 0xc91a, 0x26ff, 0xc91a, 0x21, 0 + .dw 0x2740, 0xc91a, 0x277f, 0xc91a, 0x21, 0 + .dw 0x27c0, 0xc91a, 0x27ff, 0xc91a, 0x21, 0 + .dw 0x2840, 0xc91a, 0x287f, 0xc91a, 0x21, 0 + .dw 0x28c0, 0xc91a, 0x28ff, 0xc91a, 0x21, 0 + .dw 0x2940, 0xc91a, 0x297f, 0xc91a, 0x21, 0 + .dw 0x29c0, 0xc91a, 0x29ff, 0xc91a, 0x21, 0 + .dw 0x2a40, 0xc91a, 0x2a7f, 0xc91a, 0x21, 0 + .dw 0x2ac0, 0xc91a, 0x2aff, 0xc91a, 0x21, 0 + .dw 0x2b40, 0xc91a, 0x2b7f, 0xc91a, 0x21, 0 + .dw 0x2bc0, 0xc91a, 0x2bff, 0xc91a, 0x21, 0 + .dw 0x2c40, 0xc91a, 0x2c7f, 0xc91a, 0x21, 0 + .dw 0x2cc0, 0xc91a, 0x2cff, 0xc91a, 0x21, 0 + .dw 0x2d40, 0xc91a, 0x2d7f, 0xc91a, 0x21, 0 + .dw 0x2dc0, 0xc91a, 0x2dff, 0xc91a, 0x21, 0 + .dw 0x2e40, 0xc91a, 0x2e7f, 0xc91a, 0x21, 0 + .dw 0x2ec0, 0xc91a, 0x2eff, 0xc91a, 0x21, 0 + .dw 0x2f40, 0xc91a, 0x2f7f, 0xc91a, 0x21, 0 + .dw 0x2fc0, 0xc91a, 0x2fff, 0xc91a, 0x21, 0 + .dw 0x3040, 0xc91a, 0x307f, 0xc91a, 0x21, 0 + .dw 0x30c0, 0xc91a, 0x30ff, 0xc91a, 0x21, 0 + .dw 0x3140, 0xc91a, 0x317f, 0xc91a, 0x21, 0 + .dw 0x31c0, 0xc91a, 0x31ff, 0xc91a, 0x21, 0 + .dw 0x3240, 0xc91a, 0x327f, 0xc91a, 0x21, 0 + .dw 0x32c0, 0xc91a, 0x32ff, 0xc91a, 0x21, 0 + .dw 0x3340, 0xc91a, 0x337f, 0xc91a, 0x21, 0 + .dw 0x33c0, 0xc91a, 0x33ff, 0xc91a, 0x21, 0 + .dw 0x3440, 0xc91a, 0x347f, 0xc91a, 0x21, 0 + .dw 0x34c0, 0xc91a, 0x34ff, 0xc91a, 0x21, 0 + .dw 0x3540, 0xc91a, 0x357f, 0xc91a, 0x21, 0 + .dw 0x35c0, 0xc91a, 0x35ff, 0xc91a, 0x21, 0 + .dw 0x3640, 0xc91a, 0x367f, 0xc91a, 0x21, 0 + .dw 0x36c0, 0xc91a, 0x36ff, 0xc91a, 0x21, 0 + .dw 0x3740, 0xc91a, 0x377f, 0xc91a, 0x21, 0 + .dw 0x37c0, 0xc91a, 0x37ff, 0xc91a, 0x21, 0 + .dw 0x3840, 0xc91a, 0x387f, 0xc91a, 0x21, 0 + .dw 0x38c0, 0xc91a, 0x38ff, 0xc91a, 0x21, 0 + .dw 0x3940, 0xc91a, 0x397f, 0xc91a, 0x21, 0 + .dw 0x39c0, 0xc91a, 0x5fff, 0xc91a, 0x21, 0 + .dw 0x6040, 0xc91a, 0x607f, 0xc91a, 0x21, 0 + .dw 0x60c0, 0xc91a, 0x60ff, 0xc91a, 0x21, 0 + .dw 0x6140, 0xc91a, 0x617f, 0xc91a, 0x21, 0 + .dw 0x61c0, 0xc91a, 0x61ff, 0xc91a, 0x21, 0 + .dw 0x6240, 0xc91a, 0x627f, 0xc91a, 0x21, 0 + .dw 0x62c0, 0xc91a, 0x62ff, 0xc91a, 0x21, 0 + .dw 0x6340, 0xc91a, 0x637f, 0xc91a, 0x21, 0 + .dw 0x63c0, 0xc91a, 0x63ff, 0xc91a, 0x21, 0 + .dw 0x6440, 0xc91a, 0x647f, 0xc91a, 0x21, 0 + .dw 0x64c0, 0xc91a, 0x64ff, 0xc91a, 0x21, 0 + .dw 0x6540, 0xc91a, 0x657f, 0xc91a, 0x21, 0 + .dw 0x65c0, 0xc91a, 0x65ff, 0xc91a, 0x21, 0 + .dw 0x6640, 0xc91a, 0x667f, 0xc91a, 0x21, 0 + .dw 0x66c0, 0xc91a, 0x66ff, 0xc91a, 0x21, 0 + .dw 0x6740, 0xc91a, 0x677f, 0xc91a, 0x21, 0 + .dw 0x67c0, 0xc91a, 0x67ff, 0xc91a, 0x21, 0 + .dw 0x6840, 0xc91a, 0x687f, 0xc91a, 0x21, 0 + .dw 0x68c0, 0xc91a, 0x68ff, 0xc91a, 0x21, 0 + .dw 0x6940, 0xc91a, 0x697f, 0xc91a, 0x21, 0 + .dw 0x69c0, 0xc91a, 0x69ff, 0xc91a, 0x21, 0 + .dw 0x6a40, 0xc91a, 0x6a7f, 0xc91a, 0x21, 0 + .dw 0x6ac0, 0xc91a, 0x6aff, 0xc91a, 0x21, 0 + .dw 0x6b40, 0xc91a, 0x6b7f, 0xc91a, 0x21, 0 + .dw 0x6bc0, 0xc91a, 0x6bff, 0xc91a, 0x21, 0 + .dw 0x6c40, 0xc91a, 0x6c7f, 0xc91a, 0x21, 0 + .dw 0x6cc0, 0xc91a, 0x6cff, 0xc91a, 0x21, 0 + .dw 0x6d40, 0xc91a, 0x6d7f, 0xc91a, 0x21, 0 + .dw 0x6dc0, 0xc91a, 0x6dff, 0xc91a, 0x21, 0 + .dw 0x6e40, 0xc91a, 0x6e7f, 0xc91a, 0x21, 0 + .dw 0x6ec0, 0xc91a, 0x6eff, 0xc91a, 0x21, 0 + .dw 0x6f40, 0xc91a, 0x6f7f, 0xc91a, 0x21, 0 + .dw 0x6fc0, 0xc91a, 0x6fff, 0xc91a, 0x21, 0 + .dw 0x7040, 0xc91a, 0x707f, 0xc91a, 0x21, 0 + .dw 0x70c0, 0xc91a, 0x70ff, 0xc91a, 0x21, 0 + .dw 0x7140, 0xc91a, 0x717f, 0xc91a, 0x21, 0 + .dw 0x71c0, 0xc91a, 0x71ff, 0xc91a, 0x21, 0 + .dw 0x7240, 0xc91a, 0x727f, 0xc91a, 0x21, 0 + .dw 0x72c0, 0xc91a, 0x72ff, 0xc91a, 0x21, 0 + .dw 0x7340, 0xc91a, 0x737f, 0xc91a, 0x21, 0 + .dw 0x73c0, 0xc91a, 0x73ff, 0xc91a, 0x21, 0 + .dw 0x7440, 0xc91a, 0x747f, 0xc91a, 0x21, 0 + .dw 0x74c0, 0xc91a, 0x74ff, 0xc91a, 0x21, 0 + .dw 0x7540, 0xc91a, 0x757f, 0xc91a, 0x21, 0 + .dw 0x75c0, 0xc91a, 0x75ff, 0xc91a, 0x21, 0 + .dw 0x7640, 0xc91a, 0x767f, 0xc91a, 0x21, 0 + .dw 0x76c0, 0xc91a, 0x76ff, 0xc91a, 0x21, 0 + .dw 0x7740, 0xc91a, 0x777f, 0xc91a, 0x21, 0 + .dw 0x77c0, 0xc91a, 0x77ff, 0xc91a, 0x21, 0 + .dw 0x7840, 0xc91a, 0x787f, 0xc91a, 0x21, 0 + .dw 0x78c0, 0xc91a, 0x78ff, 0xc91a, 0x21, 0 + .dw 0x7940, 0xc91a, 0x797f, 0xc91a, 0x21, 0 + .dw 0x79c0, 0xc91a, 0x9fff, 0xc91a, 0x21, 0 + .dw 0xa040, 0xc91a, 0xa07f, 0xc91a, 0x21, 0 + .dw 0xa0c0, 0xc91a, 0xa0ff, 0xc91a, 0x21, 0 + .dw 0xa140, 0xc91a, 0xa17f, 0xc91a, 0x21, 0 + .dw 0xa1c0, 0xc91a, 0xa1ff, 0xc91a, 0x21, 0 + .dw 0xa240, 0xc91a, 0xa27f, 0xc91a, 0x21, 0 + .dw 0xa2c0, 0xc91a, 0xa2ff, 0xc91a, 0x21, 0 + .dw 0xa340, 0xc91a, 0xa37f, 0xc91a, 0x21, 0 + .dw 0xa3c0, 0xc91a, 0xa3ff, 0xc91a, 0x21, 0 + .dw 0xa440, 0xc91a, 0xa47f, 0xc91a, 0x21, 0 + .dw 0xa4c0, 0xc91a, 0xa4ff, 0xc91a, 0x21, 0 + .dw 0xa540, 0xc91a, 0xa57f, 0xc91a, 0x21, 0 + .dw 0xa5c0, 0xc91a, 0xa5ff, 0xc91a, 0x21, 0 + .dw 0xa640, 0xc91a, 0xa67f, 0xc91a, 0x21, 0 + .dw 0xa6c0, 0xc91a, 0xa6ff, 0xc91a, 0x21, 0 + .dw 0xa740, 0xc91a, 0xa77f, 0xc91a, 0x21, 0 + .dw 0xa7c0, 0xc91a, 0xa7ff, 0xc91a, 0x21, 0 + .dw 0xa840, 0xc91a, 0xa87f, 0xc91a, 0x21, 0 + .dw 0xa8c0, 0xc91a, 0xa8ff, 0xc91a, 0x21, 0 + .dw 0xa940, 0xc91a, 0xa97f, 0xc91a, 0x21, 0 + .dw 0xa9c0, 0xc91a, 0xa9ff, 0xc91a, 0x21, 0 + .dw 0xaa40, 0xc91a, 0xaa7f, 0xc91a, 0x21, 0 + .dw 0xaac0, 0xc91a, 0xaaff, 0xc91a, 0x21, 0 + .dw 0xab40, 0xc91a, 0xab7f, 0xc91a, 0x21, 0 + .dw 0xabc0, 0xc91a, 0xabff, 0xc91a, 0x21, 0 + .dw 0xac40, 0xc91a, 0xac7f, 0xc91a, 0x21, 0 + .dw 0xacc0, 0xc91a, 0xacff, 0xc91a, 0x21, 0 + .dw 0xad40, 0xc91a, 0xad7f, 0xc91a, 0x21, 0 + .dw 0xadc0, 0xc91a, 0xadff, 0xc91a, 0x21, 0 + .dw 0xae40, 0xc91a, 0xae7f, 0xc91a, 0x21, 0 + .dw 0xaec0, 0xc91a, 0xaeff, 0xc91a, 0x21, 0 + .dw 0xaf40, 0xc91a, 0xaf7f, 0xc91a, 0x21, 0 + .dw 0xafc0, 0xc91a, 0xafff, 0xc91a, 0x21, 0 + .dw 0xb040, 0xc91a, 0xb07f, 0xc91a, 0x21, 0 + .dw 0xb0c0, 0xc91a, 0xb0ff, 0xc91a, 0x21, 0 + .dw 0xb140, 0xc91a, 0xb17f, 0xc91a, 0x21, 0 + .dw 0xb1c0, 0xc91a, 0xb1ff, 0xc91a, 0x21, 0 + .dw 0xb240, 0xc91a, 0xb27f, 0xc91a, 0x21, 0 + .dw 0xb2c0, 0xc91a, 0xb2ff, 0xc91a, 0x21, 0 + .dw 0xb340, 0xc91a, 0xb37f, 0xc91a, 0x21, 0 + .dw 0xb3c0, 0xc91a, 0xb3ff, 0xc91a, 0x21, 0 + .dw 0xb440, 0xc91a, 0xb47f, 0xc91a, 0x21, 0 + .dw 0xb4c0, 0xc91a, 0xb4ff, 0xc91a, 0x21, 0 + .dw 0xb540, 0xc91a, 0xb57f, 0xc91a, 0x21, 0 + .dw 0xb5c0, 0xc91a, 0xb5ff, 0xc91a, 0x21, 0 + .dw 0xb640, 0xc91a, 0xb67f, 0xc91a, 0x21, 0 + .dw 0xb6c0, 0xc91a, 0xb6ff, 0xc91a, 0x21, 0 + .dw 0xb740, 0xc91a, 0xb77f, 0xc91a, 0x21, 0 + .dw 0xb7c0, 0xc91a, 0xb7ff, 0xc91a, 0x21, 0 + .dw 0xb840, 0xc91a, 0xb87f, 0xc91a, 0x21, 0 + .dw 0xb8c0, 0xc91a, 0xb8ff, 0xc91a, 0x21, 0 + .dw 0xb940, 0xc91a, 0xb97f, 0xc91a, 0x21, 0 + .dw 0xb9c0, 0xc91a, 0xdfff, 0xc91a, 0x21, 0 + .dw 0xe040, 0xc91a, 0xe07f, 0xc91a, 0x21, 0 + .dw 0xe0c0, 0xc91a, 0xe0ff, 0xc91a, 0x21, 0 + .dw 0xe140, 0xc91a, 0xe17f, 0xc91a, 0x21, 0 + .dw 0xe1c0, 0xc91a, 0xe1ff, 0xc91a, 0x21, 0 + .dw 0xe240, 0xc91a, 0xe27f, 0xc91a, 0x21, 0 + .dw 0xe2c0, 0xc91a, 0xe2ff, 0xc91a, 0x21, 0 + .dw 0xe340, 0xc91a, 0xe37f, 0xc91a, 0x21, 0 + .dw 0xe3c0, 0xc91a, 0xe3ff, 0xc91a, 0x21, 0 + .dw 0xe440, 0xc91a, 0xe47f, 0xc91a, 0x21, 0 + .dw 0xe4c0, 0xc91a, 0xe4ff, 0xc91a, 0x21, 0 + .dw 0xe540, 0xc91a, 0xe57f, 0xc91a, 0x21, 0 + .dw 0xe5c0, 0xc91a, 0xe5ff, 0xc91a, 0x21, 0 + .dw 0xe640, 0xc91a, 0xe67f, 0xc91a, 0x21, 0 + .dw 0xe6c0, 0xc91a, 0xe6ff, 0xc91a, 0x21, 0 + .dw 0xe740, 0xc91a, 0xe77f, 0xc91a, 0x21, 0 + .dw 0xe7c0, 0xc91a, 0xe7ff, 0xc91a, 0x21, 0 + .dw 0xe840, 0xc91a, 0xe87f, 0xc91a, 0x21, 0 + .dw 0xe8c0, 0xc91a, 0xe8ff, 0xc91a, 0x21, 0 + .dw 0xe940, 0xc91a, 0xe97f, 0xc91a, 0x21, 0 + .dw 0xe9c0, 0xc91a, 0xe9ff, 0xc91a, 0x21, 0 + .dw 0xea40, 0xc91a, 0xea7f, 0xc91a, 0x21, 0 + .dw 0xeac0, 0xc91a, 0xeaff, 0xc91a, 0x21, 0 + .dw 0xeb40, 0xc91a, 0xeb7f, 0xc91a, 0x21, 0 + .dw 0xebc0, 0xc91a, 0xebff, 0xc91a, 0x21, 0 + .dw 0xec40, 0xc91a, 0xec7f, 0xc91a, 0x21, 0 + .dw 0xecc0, 0xc91a, 0xecff, 0xc91a, 0x21, 0 + .dw 0xed40, 0xc91a, 0xed7f, 0xc91a, 0x21, 0 + .dw 0xedc0, 0xc91a, 0xedff, 0xc91a, 0x21, 0 + .dw 0xee40, 0xc91a, 0xee7f, 0xc91a, 0x21, 0 + .dw 0xeec0, 0xc91a, 0xeeff, 0xc91a, 0x21, 0 + .dw 0xef40, 0xc91a, 0xef7f, 0xc91a, 0x21, 0 + .dw 0xefc0, 0xc91a, 0xefff, 0xc91a, 0x21, 0 + .dw 0xf040, 0xc91a, 0xf07f, 0xc91a, 0x21, 0 + .dw 0xf0c0, 0xc91a, 0xf0ff, 0xc91a, 0x21, 0 + .dw 0xf140, 0xc91a, 0xf17f, 0xc91a, 0x21, 0 + .dw 0xf1c0, 0xc91a, 0xf1ff, 0xc91a, 0x21, 0 + .dw 0xf240, 0xc91a, 0xf27f, 0xc91a, 0x21, 0 + .dw 0xf2c0, 0xc91a, 0xf2ff, 0xc91a, 0x21, 0 + .dw 0xf340, 0xc91a, 0xf37f, 0xc91a, 0x21, 0 + .dw 0xf3c0, 0xc91a, 0xf3ff, 0xc91a, 0x21, 0 + .dw 0xf440, 0xc91a, 0xf47f, 0xc91a, 0x21, 0 + .dw 0xf4c0, 0xc91a, 0xf4ff, 0xc91a, 0x21, 0 + .dw 0xf540, 0xc91a, 0xf57f, 0xc91a, 0x21, 0 + .dw 0xf5c0, 0xc91a, 0xf5ff, 0xc91a, 0x21, 0 + .dw 0xf640, 0xc91a, 0xf67f, 0xc91a, 0x21, 0 + .dw 0xf6c0, 0xc91a, 0xf6ff, 0xc91a, 0x21, 0 + .dw 0xf740, 0xc91a, 0xf77f, 0xc91a, 0x21, 0 + .dw 0xf7c0, 0xc91a, 0xf7ff, 0xc91a, 0x21, 0 + .dw 0xf840, 0xc91a, 0xf87f, 0xc91a, 0x21, 0 + .dw 0xf8c0, 0xc91a, 0xf8ff, 0xc91a, 0x21, 0 + .dw 0xf940, 0xc91a, 0xf97f, 0xc91a, 0x21, 0 + .dw 0xf9c0, 0xc91a, 0xffff, 0xc91b, 0x21, 0 + .dw 0x0040, 0xc91c, 0x007f, 0xc91c, 0x21, 0 + .dw 0x00c0, 0xc91c, 0x00ff, 0xc91c, 0x21, 0 + .dw 0x0140, 0xc91c, 0x017f, 0xc91c, 0x21, 0 + .dw 0x01c0, 0xc91c, 0x01ff, 0xc91c, 0x21, 0 + .dw 0x0240, 0xc91c, 0x027f, 0xc91c, 0x21, 0 + .dw 0x02c0, 0xc91c, 0x02ff, 0xc91c, 0x21, 0 + .dw 0x0340, 0xc91c, 0x037f, 0xc91c, 0x21, 0 + .dw 0x03c0, 0xc91c, 0x03ff, 0xc91c, 0x21, 0 + .dw 0x0440, 0xc91c, 0x047f, 0xc91c, 0x21, 0 + .dw 0x04c0, 0xc91c, 0x04ff, 0xc91c, 0x21, 0 + .dw 0x0540, 0xc91c, 0x057f, 0xc91c, 0x21, 0 + .dw 0x05c0, 0xc91c, 0x05ff, 0xc91c, 0x21, 0 + .dw 0x0640, 0xc91c, 0x067f, 0xc91c, 0x21, 0 + .dw 0x06c0, 0xc91c, 0x06ff, 0xc91c, 0x21, 0 + .dw 0x0740, 0xc91c, 0x077f, 0xc91c, 0x21, 0 + .dw 0x07c0, 0xc91c, 0x07ff, 0xc91c, 0x21, 0 + .dw 0x0840, 0xc91c, 0x087f, 0xc91c, 0x21, 0 + .dw 0x08c0, 0xc91c, 0x08ff, 0xc91c, 0x21, 0 + .dw 0x0940, 0xc91c, 0x097f, 0xc91c, 0x21, 0 + .dw 0x09c0, 0xc91c, 0x09ff, 0xc91c, 0x21, 0 + .dw 0x0a40, 0xc91c, 0x0a7f, 0xc91c, 0x21, 0 + .dw 0x0ac0, 0xc91c, 0x0aff, 0xc91c, 0x21, 0 + .dw 0x0b40, 0xc91c, 0x0b7f, 0xc91c, 0x21, 0 + .dw 0x0bc0, 0xc91c, 0x0bff, 0xc91c, 0x21, 0 + .dw 0x0c40, 0xc91c, 0x0c7f, 0xc91c, 0x21, 0 + .dw 0x0cc0, 0xc91c, 0x0cff, 0xc91c, 0x21, 0 + .dw 0x0d40, 0xc91c, 0x0d7f, 0xc91c, 0x21, 0 + .dw 0x0dc0, 0xc91c, 0x0dff, 0xc91c, 0x21, 0 + .dw 0x0e40, 0xc91c, 0x0e7f, 0xc91c, 0x21, 0 + .dw 0x0ec0, 0xc91c, 0x0eff, 0xc91c, 0x21, 0 + .dw 0x0f40, 0xc91c, 0x0f7f, 0xc91c, 0x21, 0 + .dw 0x0fc0, 0xc91c, 0x0fff, 0xc91c, 0x21, 0 + .dw 0x1040, 0xc91c, 0x107f, 0xc91c, 0x21, 0 + .dw 0x10c0, 0xc91c, 0x10ff, 0xc91c, 0x21, 0 + .dw 0x1140, 0xc91c, 0x117f, 0xc91c, 0x21, 0 + .dw 0x11c0, 0xc91c, 0x11ff, 0xc91c, 0x21, 0 + .dw 0x1240, 0xc91c, 0x127f, 0xc91c, 0x21, 0 + .dw 0x12c0, 0xc91c, 0x12ff, 0xc91c, 0x21, 0 + .dw 0x1340, 0xc91c, 0x137f, 0xc91c, 0x21, 0 + .dw 0x13c0, 0xc91c, 0x13ff, 0xc91c, 0x21, 0 + .dw 0x1440, 0xc91c, 0x147f, 0xc91c, 0x21, 0 + .dw 0x14c0, 0xc91c, 0x14ff, 0xc91c, 0x21, 0 + .dw 0x1540, 0xc91c, 0x157f, 0xc91c, 0x21, 0 + .dw 0x15c0, 0xc91c, 0x15ff, 0xc91c, 0x21, 0 + .dw 0x1640, 0xc91c, 0x167f, 0xc91c, 0x21, 0 + .dw 0x16c0, 0xc91c, 0x16ff, 0xc91c, 0x21, 0 + .dw 0x1740, 0xc91c, 0x177f, 0xc91c, 0x21, 0 + .dw 0x17c0, 0xc91c, 0x17ff, 0xc91c, 0x21, 0 + .dw 0x1840, 0xc91c, 0x187f, 0xc91c, 0x21, 0 + .dw 0x18c0, 0xc91c, 0x18ff, 0xc91c, 0x21, 0 + .dw 0x1940, 0xc91c, 0x197f, 0xc91c, 0x21, 0 + .dw 0x19c0, 0xc91c, 0x1fff, 0xc91c, 0x21, 0 + .dw 0x2040, 0xc91c, 0x207f, 0xc91c, 0x21, 0 + .dw 0x20c0, 0xc91c, 0x20ff, 0xc91c, 0x21, 0 + .dw 0x2140, 0xc91c, 0x217f, 0xc91c, 0x21, 0 + .dw 0x21c0, 0xc91c, 0x21ff, 0xc91c, 0x21, 0 + .dw 0x2240, 0xc91c, 0x227f, 0xc91c, 0x21, 0 + .dw 0x22c0, 0xc91c, 0x22ff, 0xc91c, 0x21, 0 + .dw 0x2340, 0xc91c, 0x237f, 0xc91c, 0x21, 0 + .dw 0x23c0, 0xc91c, 0x23ff, 0xc91c, 0x21, 0 + .dw 0x2440, 0xc91c, 0x247f, 0xc91c, 0x21, 0 + .dw 0x24c0, 0xc91c, 0x24ff, 0xc91c, 0x21, 0 + .dw 0x2540, 0xc91c, 0x257f, 0xc91c, 0x21, 0 + .dw 0x25c0, 0xc91c, 0x25ff, 0xc91c, 0x21, 0 + .dw 0x2640, 0xc91c, 0x267f, 0xc91c, 0x21, 0 + .dw 0x26c0, 0xc91c, 0x26ff, 0xc91c, 0x21, 0 + .dw 0x2740, 0xc91c, 0x277f, 0xc91c, 0x21, 0 + .dw 0x27c0, 0xc91c, 0x27ff, 0xc91c, 0x21, 0 + .dw 0x2840, 0xc91c, 0x287f, 0xc91c, 0x21, 0 + .dw 0x28c0, 0xc91c, 0x28ff, 0xc91c, 0x21, 0 + .dw 0x2940, 0xc91c, 0x297f, 0xc91c, 0x21, 0 + .dw 0x29c0, 0xc91c, 0x29ff, 0xc91c, 0x21, 0 + .dw 0x2a40, 0xc91c, 0x2a7f, 0xc91c, 0x21, 0 + .dw 0x2ac0, 0xc91c, 0x2aff, 0xc91c, 0x21, 0 + .dw 0x2b40, 0xc91c, 0x2b7f, 0xc91c, 0x21, 0 + .dw 0x2bc0, 0xc91c, 0x2bff, 0xc91c, 0x21, 0 + .dw 0x2c40, 0xc91c, 0x2c7f, 0xc91c, 0x21, 0 + .dw 0x2cc0, 0xc91c, 0x2cff, 0xc91c, 0x21, 0 + .dw 0x2d40, 0xc91c, 0x2d7f, 0xc91c, 0x21, 0 + .dw 0x2dc0, 0xc91c, 0x2dff, 0xc91c, 0x21, 0 + .dw 0x2e40, 0xc91c, 0x2e7f, 0xc91c, 0x21, 0 + .dw 0x2ec0, 0xc91c, 0x2eff, 0xc91c, 0x21, 0 + .dw 0x2f40, 0xc91c, 0x2f7f, 0xc91c, 0x21, 0 + .dw 0x2fc0, 0xc91c, 0x2fff, 0xc91c, 0x21, 0 + .dw 0x3040, 0xc91c, 0x307f, 0xc91c, 0x21, 0 + .dw 0x30c0, 0xc91c, 0x30ff, 0xc91c, 0x21, 0 + .dw 0x3140, 0xc91c, 0x317f, 0xc91c, 0x21, 0 + .dw 0x31c0, 0xc91c, 0x31ff, 0xc91c, 0x21, 0 + .dw 0x3240, 0xc91c, 0x327f, 0xc91c, 0x21, 0 + .dw 0x32c0, 0xc91c, 0x32ff, 0xc91c, 0x21, 0 + .dw 0x3340, 0xc91c, 0x337f, 0xc91c, 0x21, 0 + .dw 0x33c0, 0xc91c, 0x33ff, 0xc91c, 0x21, 0 + .dw 0x3440, 0xc91c, 0x347f, 0xc91c, 0x21, 0 + .dw 0x34c0, 0xc91c, 0x34ff, 0xc91c, 0x21, 0 + .dw 0x3540, 0xc91c, 0x357f, 0xc91c, 0x21, 0 + .dw 0x35c0, 0xc91c, 0x35ff, 0xc91c, 0x21, 0 + .dw 0x3640, 0xc91c, 0x367f, 0xc91c, 0x21, 0 + .dw 0x36c0, 0xc91c, 0x36ff, 0xc91c, 0x21, 0 + .dw 0x3740, 0xc91c, 0x377f, 0xc91c, 0x21, 0 + .dw 0x37c0, 0xc91c, 0x37ff, 0xc91c, 0x21, 0 + .dw 0x3840, 0xc91c, 0x387f, 0xc91c, 0x21, 0 + .dw 0x38c0, 0xc91c, 0x38ff, 0xc91c, 0x21, 0 + .dw 0x3940, 0xc91c, 0x397f, 0xc91c, 0x21, 0 + .dw 0x39c0, 0xc91c, 0x3fff, 0xc91c, 0x21, 0 + .dw 0x4040, 0xc91c, 0x407f, 0xc91c, 0x21, 0 + .dw 0x40c0, 0xc91c, 0x40ff, 0xc91c, 0x21, 0 + .dw 0x4140, 0xc91c, 0x417f, 0xc91c, 0x21, 0 + .dw 0x41c0, 0xc91c, 0x41ff, 0xc91c, 0x21, 0 + .dw 0x4240, 0xc91c, 0x427f, 0xc91c, 0x21, 0 + .dw 0x42c0, 0xc91c, 0x42ff, 0xc91c, 0x21, 0 + .dw 0x4340, 0xc91c, 0x437f, 0xc91c, 0x21, 0 + .dw 0x43c0, 0xc91c, 0x43ff, 0xc91c, 0x21, 0 + .dw 0x4440, 0xc91c, 0x447f, 0xc91c, 0x21, 0 + .dw 0x44c0, 0xc91c, 0x44ff, 0xc91c, 0x21, 0 + .dw 0x4540, 0xc91c, 0x457f, 0xc91c, 0x21, 0 + .dw 0x45c0, 0xc91c, 0x45ff, 0xc91c, 0x21, 0 + .dw 0x4640, 0xc91c, 0x467f, 0xc91c, 0x21, 0 + .dw 0x46c0, 0xc91c, 0x46ff, 0xc91c, 0x21, 0 + .dw 0x4740, 0xc91c, 0x477f, 0xc91c, 0x21, 0 + .dw 0x47c0, 0xc91c, 0x47ff, 0xc91c, 0x21, 0 + .dw 0x4840, 0xc91c, 0x487f, 0xc91c, 0x21, 0 + .dw 0x48c0, 0xc91c, 0x48ff, 0xc91c, 0x21, 0 + .dw 0x4940, 0xc91c, 0x497f, 0xc91c, 0x21, 0 + .dw 0x49c0, 0xc91c, 0x49ff, 0xc91c, 0x21, 0 + .dw 0x4a40, 0xc91c, 0x4a7f, 0xc91c, 0x21, 0 + .dw 0x4ac0, 0xc91c, 0x4aff, 0xc91c, 0x21, 0 + .dw 0x4b40, 0xc91c, 0x4b7f, 0xc91c, 0x21, 0 + .dw 0x4bc0, 0xc91c, 0x4bff, 0xc91c, 0x21, 0 + .dw 0x4c40, 0xc91c, 0x4c7f, 0xc91c, 0x21, 0 + .dw 0x4cc0, 0xc91c, 0x4cff, 0xc91c, 0x21, 0 + .dw 0x4d40, 0xc91c, 0x4d7f, 0xc91c, 0x21, 0 + .dw 0x4dc0, 0xc91c, 0x4dff, 0xc91c, 0x21, 0 + .dw 0x4e40, 0xc91c, 0x4e7f, 0xc91c, 0x21, 0 + .dw 0x4ec0, 0xc91c, 0x4eff, 0xc91c, 0x21, 0 + .dw 0x4f40, 0xc91c, 0x4f7f, 0xc91c, 0x21, 0 + .dw 0x4fc0, 0xc91c, 0x4fff, 0xc91c, 0x21, 0 + .dw 0x5040, 0xc91c, 0x507f, 0xc91c, 0x21, 0 + .dw 0x50c0, 0xc91c, 0x50ff, 0xc91c, 0x21, 0 + .dw 0x5140, 0xc91c, 0x517f, 0xc91c, 0x21, 0 + .dw 0x51c0, 0xc91c, 0x51ff, 0xc91c, 0x21, 0 + .dw 0x5240, 0xc91c, 0x527f, 0xc91c, 0x21, 0 + .dw 0x52c0, 0xc91c, 0x52ff, 0xc91c, 0x21, 0 + .dw 0x5340, 0xc91c, 0x537f, 0xc91c, 0x21, 0 + .dw 0x53c0, 0xc91c, 0x53ff, 0xc91c, 0x21, 0 + .dw 0x5440, 0xc91c, 0x547f, 0xc91c, 0x21, 0 + .dw 0x54c0, 0xc91c, 0x54ff, 0xc91c, 0x21, 0 + .dw 0x5540, 0xc91c, 0x557f, 0xc91c, 0x21, 0 + .dw 0x55c0, 0xc91c, 0x55ff, 0xc91c, 0x21, 0 + .dw 0x5640, 0xc91c, 0x567f, 0xc91c, 0x21, 0 + .dw 0x56c0, 0xc91c, 0x56ff, 0xc91c, 0x21, 0 + .dw 0x5740, 0xc91c, 0x577f, 0xc91c, 0x21, 0 + .dw 0x57c0, 0xc91c, 0x57ff, 0xc91c, 0x21, 0 + .dw 0x5840, 0xc91c, 0x587f, 0xc91c, 0x21, 0 + .dw 0x58c0, 0xc91c, 0x58ff, 0xc91c, 0x21, 0 + .dw 0x5940, 0xc91c, 0x597f, 0xc91c, 0x21, 0 + .dw 0x59c0, 0xc91c, 0x5fff, 0xc91c, 0x21, 0 + .dw 0x6040, 0xc91c, 0x607f, 0xc91c, 0x21, 0 + .dw 0x60c0, 0xc91c, 0x60ff, 0xc91c, 0x21, 0 + .dw 0x6140, 0xc91c, 0x617f, 0xc91c, 0x21, 0 + .dw 0x61c0, 0xc91c, 0x61ff, 0xc91c, 0x21, 0 + .dw 0x6240, 0xc91c, 0x627f, 0xc91c, 0x21, 0 + .dw 0x62c0, 0xc91c, 0x62ff, 0xc91c, 0x21, 0 + .dw 0x6340, 0xc91c, 0x637f, 0xc91c, 0x21, 0 + .dw 0x63c0, 0xc91c, 0x63ff, 0xc91c, 0x21, 0 + .dw 0x6440, 0xc91c, 0x647f, 0xc91c, 0x21, 0 + .dw 0x64c0, 0xc91c, 0x64ff, 0xc91c, 0x21, 0 + .dw 0x6540, 0xc91c, 0x657f, 0xc91c, 0x21, 0 + .dw 0x65c0, 0xc91c, 0x65ff, 0xc91c, 0x21, 0 + .dw 0x6640, 0xc91c, 0x667f, 0xc91c, 0x21, 0 + .dw 0x66c0, 0xc91c, 0x66ff, 0xc91c, 0x21, 0 + .dw 0x6740, 0xc91c, 0x677f, 0xc91c, 0x21, 0 + .dw 0x67c0, 0xc91c, 0x67ff, 0xc91c, 0x21, 0 + .dw 0x6840, 0xc91c, 0x687f, 0xc91c, 0x21, 0 + .dw 0x68c0, 0xc91c, 0x68ff, 0xc91c, 0x21, 0 + .dw 0x6940, 0xc91c, 0x697f, 0xc91c, 0x21, 0 + .dw 0x69c0, 0xc91c, 0x69ff, 0xc91c, 0x21, 0 + .dw 0x6a40, 0xc91c, 0x6a7f, 0xc91c, 0x21, 0 + .dw 0x6ac0, 0xc91c, 0x6aff, 0xc91c, 0x21, 0 + .dw 0x6b40, 0xc91c, 0x6b7f, 0xc91c, 0x21, 0 + .dw 0x6bc0, 0xc91c, 0x6bff, 0xc91c, 0x21, 0 + .dw 0x6c40, 0xc91c, 0x6c7f, 0xc91c, 0x21, 0 + .dw 0x6cc0, 0xc91c, 0x6cff, 0xc91c, 0x21, 0 + .dw 0x6d40, 0xc91c, 0x6d7f, 0xc91c, 0x21, 0 + .dw 0x6dc0, 0xc91c, 0x6dff, 0xc91c, 0x21, 0 + .dw 0x6e40, 0xc91c, 0x6e7f, 0xc91c, 0x21, 0 + .dw 0x6ec0, 0xc91c, 0x6eff, 0xc91c, 0x21, 0 + .dw 0x6f40, 0xc91c, 0x6f7f, 0xc91c, 0x21, 0 + .dw 0x6fc0, 0xc91c, 0x6fff, 0xc91c, 0x21, 0 + .dw 0x7040, 0xc91c, 0x707f, 0xc91c, 0x21, 0 + .dw 0x70c0, 0xc91c, 0x70ff, 0xc91c, 0x21, 0 + .dw 0x7140, 0xc91c, 0x717f, 0xc91c, 0x21, 0 + .dw 0x71c0, 0xc91c, 0x71ff, 0xc91c, 0x21, 0 + .dw 0x7240, 0xc91c, 0x727f, 0xc91c, 0x21, 0 + .dw 0x72c0, 0xc91c, 0x72ff, 0xc91c, 0x21, 0 + .dw 0x7340, 0xc91c, 0x737f, 0xc91c, 0x21, 0 + .dw 0x73c0, 0xc91c, 0x73ff, 0xc91c, 0x21, 0 + .dw 0x7440, 0xc91c, 0x747f, 0xc91c, 0x21, 0 + .dw 0x74c0, 0xc91c, 0x74ff, 0xc91c, 0x21, 0 + .dw 0x7540, 0xc91c, 0x757f, 0xc91c, 0x21, 0 + .dw 0x75c0, 0xc91c, 0x75ff, 0xc91c, 0x21, 0 + .dw 0x7640, 0xc91c, 0x767f, 0xc91c, 0x21, 0 + .dw 0x76c0, 0xc91c, 0x76ff, 0xc91c, 0x21, 0 + .dw 0x7740, 0xc91c, 0x777f, 0xc91c, 0x21, 0 + .dw 0x77c0, 0xc91c, 0x77ff, 0xc91c, 0x21, 0 + .dw 0x7840, 0xc91c, 0x787f, 0xc91c, 0x21, 0 + .dw 0x78c0, 0xc91c, 0x78ff, 0xc91c, 0x21, 0 + .dw 0x7940, 0xc91c, 0x797f, 0xc91c, 0x21, 0 + .dw 0x79c0, 0xc91c, 0x7fff, 0xc91c, 0x21, 0 + .dw 0x8040, 0xc91c, 0x807f, 0xc91c, 0x21, 0 + .dw 0x80c0, 0xc91c, 0x80ff, 0xc91c, 0x21, 0 + .dw 0x8140, 0xc91c, 0x817f, 0xc91c, 0x21, 0 + .dw 0x81c0, 0xc91c, 0x81ff, 0xc91c, 0x21, 0 + .dw 0x8240, 0xc91c, 0x827f, 0xc91c, 0x21, 0 + .dw 0x82c0, 0xc91c, 0x82ff, 0xc91c, 0x21, 0 + .dw 0x8340, 0xc91c, 0x837f, 0xc91c, 0x21, 0 + .dw 0x83c0, 0xc91c, 0x83ff, 0xc91c, 0x21, 0 + .dw 0x8440, 0xc91c, 0x847f, 0xc91c, 0x21, 0 + .dw 0x84c0, 0xc91c, 0x84ff, 0xc91c, 0x21, 0 + .dw 0x8540, 0xc91c, 0x857f, 0xc91c, 0x21, 0 + .dw 0x85c0, 0xc91c, 0x85ff, 0xc91c, 0x21, 0 + .dw 0x8640, 0xc91c, 0x867f, 0xc91c, 0x21, 0 + .dw 0x86c0, 0xc91c, 0x86ff, 0xc91c, 0x21, 0 + .dw 0x8740, 0xc91c, 0x877f, 0xc91c, 0x21, 0 + .dw 0x87c0, 0xc91c, 0x87ff, 0xc91c, 0x21, 0 + .dw 0x8840, 0xc91c, 0x887f, 0xc91c, 0x21, 0 + .dw 0x88c0, 0xc91c, 0x88ff, 0xc91c, 0x21, 0 + .dw 0x8940, 0xc91c, 0x897f, 0xc91c, 0x21, 0 + .dw 0x89c0, 0xc91c, 0x89ff, 0xc91c, 0x21, 0 + .dw 0x8a40, 0xc91c, 0x8a7f, 0xc91c, 0x21, 0 + .dw 0x8ac0, 0xc91c, 0x8aff, 0xc91c, 0x21, 0 + .dw 0x8b40, 0xc91c, 0x8b7f, 0xc91c, 0x21, 0 + .dw 0x8bc0, 0xc91c, 0x8bff, 0xc91c, 0x21, 0 + .dw 0x8c40, 0xc91c, 0x8c7f, 0xc91c, 0x21, 0 + .dw 0x8cc0, 0xc91c, 0x8cff, 0xc91c, 0x21, 0 + .dw 0x8d40, 0xc91c, 0x8d7f, 0xc91c, 0x21, 0 + .dw 0x8dc0, 0xc91c, 0x8dff, 0xc91c, 0x21, 0 + .dw 0x8e40, 0xc91c, 0x8e7f, 0xc91c, 0x21, 0 + .dw 0x8ec0, 0xc91c, 0x8eff, 0xc91c, 0x21, 0 + .dw 0x8f40, 0xc91c, 0x8f7f, 0xc91c, 0x21, 0 + .dw 0x8fc0, 0xc91c, 0x8fff, 0xc91c, 0x21, 0 + .dw 0x9040, 0xc91c, 0x907f, 0xc91c, 0x21, 0 + .dw 0x90c0, 0xc91c, 0x90ff, 0xc91c, 0x21, 0 + .dw 0x9140, 0xc91c, 0x917f, 0xc91c, 0x21, 0 + .dw 0x91c0, 0xc91c, 0x91ff, 0xc91c, 0x21, 0 + .dw 0x9240, 0xc91c, 0x927f, 0xc91c, 0x21, 0 + .dw 0x92c0, 0xc91c, 0x92ff, 0xc91c, 0x21, 0 + .dw 0x9340, 0xc91c, 0x937f, 0xc91c, 0x21, 0 + .dw 0x93c0, 0xc91c, 0x93ff, 0xc91c, 0x21, 0 + .dw 0x9440, 0xc91c, 0x947f, 0xc91c, 0x21, 0 + .dw 0x94c0, 0xc91c, 0x94ff, 0xc91c, 0x21, 0 + .dw 0x9540, 0xc91c, 0x957f, 0xc91c, 0x21, 0 + .dw 0x95c0, 0xc91c, 0x95ff, 0xc91c, 0x21, 0 + .dw 0x9640, 0xc91c, 0x967f, 0xc91c, 0x21, 0 + .dw 0x96c0, 0xc91c, 0x96ff, 0xc91c, 0x21, 0 + .dw 0x9740, 0xc91c, 0x977f, 0xc91c, 0x21, 0 + .dw 0x97c0, 0xc91c, 0x97ff, 0xc91c, 0x21, 0 + .dw 0x9840, 0xc91c, 0x987f, 0xc91c, 0x21, 0 + .dw 0x98c0, 0xc91c, 0x98ff, 0xc91c, 0x21, 0 + .dw 0x9940, 0xc91c, 0x997f, 0xc91c, 0x21, 0 + .dw 0x99c0, 0xc91c, 0x9fff, 0xc91c, 0x21, 0 + .dw 0xa040, 0xc91c, 0xa07f, 0xc91c, 0x21, 0 + .dw 0xa0c0, 0xc91c, 0xa0ff, 0xc91c, 0x21, 0 + .dw 0xa140, 0xc91c, 0xa17f, 0xc91c, 0x21, 0 + .dw 0xa1c0, 0xc91c, 0xa1ff, 0xc91c, 0x21, 0 + .dw 0xa240, 0xc91c, 0xa27f, 0xc91c, 0x21, 0 + .dw 0xa2c0, 0xc91c, 0xa2ff, 0xc91c, 0x21, 0 + .dw 0xa340, 0xc91c, 0xa37f, 0xc91c, 0x21, 0 + .dw 0xa3c0, 0xc91c, 0xa3ff, 0xc91c, 0x21, 0 + .dw 0xa440, 0xc91c, 0xa47f, 0xc91c, 0x21, 0 + .dw 0xa4c0, 0xc91c, 0xa4ff, 0xc91c, 0x21, 0 + .dw 0xa540, 0xc91c, 0xa57f, 0xc91c, 0x21, 0 + .dw 0xa5c0, 0xc91c, 0xa5ff, 0xc91c, 0x21, 0 + .dw 0xa640, 0xc91c, 0xa67f, 0xc91c, 0x21, 0 + .dw 0xa6c0, 0xc91c, 0xa6ff, 0xc91c, 0x21, 0 + .dw 0xa740, 0xc91c, 0xa77f, 0xc91c, 0x21, 0 + .dw 0xa7c0, 0xc91c, 0xa7ff, 0xc91c, 0x21, 0 + .dw 0xa840, 0xc91c, 0xa87f, 0xc91c, 0x21, 0 + .dw 0xa8c0, 0xc91c, 0xa8ff, 0xc91c, 0x21, 0 + .dw 0xa940, 0xc91c, 0xa97f, 0xc91c, 0x21, 0 + .dw 0xa9c0, 0xc91c, 0xa9ff, 0xc91c, 0x21, 0 + .dw 0xaa40, 0xc91c, 0xaa7f, 0xc91c, 0x21, 0 + .dw 0xaac0, 0xc91c, 0xaaff, 0xc91c, 0x21, 0 + .dw 0xab40, 0xc91c, 0xab7f, 0xc91c, 0x21, 0 + .dw 0xabc0, 0xc91c, 0xabff, 0xc91c, 0x21, 0 + .dw 0xac40, 0xc91c, 0xac7f, 0xc91c, 0x21, 0 + .dw 0xacc0, 0xc91c, 0xacff, 0xc91c, 0x21, 0 + .dw 0xad40, 0xc91c, 0xad7f, 0xc91c, 0x21, 0 + .dw 0xadc0, 0xc91c, 0xadff, 0xc91c, 0x21, 0 + .dw 0xae40, 0xc91c, 0xae7f, 0xc91c, 0x21, 0 + .dw 0xaec0, 0xc91c, 0xaeff, 0xc91c, 0x21, 0 + .dw 0xaf40, 0xc91c, 0xaf7f, 0xc91c, 0x21, 0 + .dw 0xafc0, 0xc91c, 0xafff, 0xc91c, 0x21, 0 + .dw 0xb040, 0xc91c, 0xb07f, 0xc91c, 0x21, 0 + .dw 0xb0c0, 0xc91c, 0xb0ff, 0xc91c, 0x21, 0 + .dw 0xb140, 0xc91c, 0xb17f, 0xc91c, 0x21, 0 + .dw 0xb1c0, 0xc91c, 0xb1ff, 0xc91c, 0x21, 0 + .dw 0xb240, 0xc91c, 0xb27f, 0xc91c, 0x21, 0 + .dw 0xb2c0, 0xc91c, 0xb2ff, 0xc91c, 0x21, 0 + .dw 0xb340, 0xc91c, 0xb37f, 0xc91c, 0x21, 0 + .dw 0xb3c0, 0xc91c, 0xb3ff, 0xc91c, 0x21, 0 + .dw 0xb440, 0xc91c, 0xb47f, 0xc91c, 0x21, 0 + .dw 0xb4c0, 0xc91c, 0xb4ff, 0xc91c, 0x21, 0 + .dw 0xb540, 0xc91c, 0xb57f, 0xc91c, 0x21, 0 + .dw 0xb5c0, 0xc91c, 0xb5ff, 0xc91c, 0x21, 0 + .dw 0xb640, 0xc91c, 0xb67f, 0xc91c, 0x21, 0 + .dw 0xb6c0, 0xc91c, 0xb6ff, 0xc91c, 0x21, 0 + .dw 0xb740, 0xc91c, 0xb77f, 0xc91c, 0x21, 0 + .dw 0xb7c0, 0xc91c, 0xb7ff, 0xc91c, 0x21, 0 + .dw 0xb840, 0xc91c, 0xb87f, 0xc91c, 0x21, 0 + .dw 0xb8c0, 0xc91c, 0xb8ff, 0xc91c, 0x21, 0 + .dw 0xb940, 0xc91c, 0xb97f, 0xc91c, 0x21, 0 + .dw 0xb9c0, 0xc91c, 0xbfff, 0xc91c, 0x21, 0 + .dw 0xc040, 0xc91c, 0xc07f, 0xc91c, 0x21, 0 + .dw 0xc0c0, 0xc91c, 0xc0ff, 0xc91c, 0x21, 0 + .dw 0xc140, 0xc91c, 0xc17f, 0xc91c, 0x21, 0 + .dw 0xc1c0, 0xc91c, 0xc1ff, 0xc91c, 0x21, 0 + .dw 0xc240, 0xc91c, 0xc27f, 0xc91c, 0x21, 0 + .dw 0xc2c0, 0xc91c, 0xc2ff, 0xc91c, 0x21, 0 + .dw 0xc340, 0xc91c, 0xc37f, 0xc91c, 0x21, 0 + .dw 0xc3c0, 0xc91c, 0xc3ff, 0xc91c, 0x21, 0 + .dw 0xc440, 0xc91c, 0xc47f, 0xc91c, 0x21, 0 + .dw 0xc4c0, 0xc91c, 0xc4ff, 0xc91c, 0x21, 0 + .dw 0xc540, 0xc91c, 0xc57f, 0xc91c, 0x21, 0 + .dw 0xc5c0, 0xc91c, 0xc5ff, 0xc91c, 0x21, 0 + .dw 0xc640, 0xc91c, 0xc67f, 0xc91c, 0x21, 0 + .dw 0xc6c0, 0xc91c, 0xc6ff, 0xc91c, 0x21, 0 + .dw 0xc740, 0xc91c, 0xc77f, 0xc91c, 0x21, 0 + .dw 0xc7c0, 0xc91c, 0xc7ff, 0xc91c, 0x21, 0 + .dw 0xc840, 0xc91c, 0xc87f, 0xc91c, 0x21, 0 + .dw 0xc8c0, 0xc91c, 0xc8ff, 0xc91c, 0x21, 0 + .dw 0xc940, 0xc91c, 0xc97f, 0xc91c, 0x21, 0 + .dw 0xc9c0, 0xc91c, 0xc9ff, 0xc91c, 0x21, 0 + .dw 0xca40, 0xc91c, 0xca7f, 0xc91c, 0x21, 0 + .dw 0xcac0, 0xc91c, 0xcaff, 0xc91c, 0x21, 0 + .dw 0xcb40, 0xc91c, 0xcb7f, 0xc91c, 0x21, 0 + .dw 0xcbc0, 0xc91c, 0xcbff, 0xc91c, 0x21, 0 + .dw 0xcc40, 0xc91c, 0xcc7f, 0xc91c, 0x21, 0 + .dw 0xccc0, 0xc91c, 0xccff, 0xc91c, 0x21, 0 + .dw 0xcd40, 0xc91c, 0xcd7f, 0xc91c, 0x21, 0 + .dw 0xcdc0, 0xc91c, 0xcdff, 0xc91c, 0x21, 0 + .dw 0xce40, 0xc91c, 0xce7f, 0xc91c, 0x21, 0 + .dw 0xcec0, 0xc91c, 0xceff, 0xc91c, 0x21, 0 + .dw 0xcf40, 0xc91c, 0xcf7f, 0xc91c, 0x21, 0 + .dw 0xcfc0, 0xc91c, 0xcfff, 0xc91c, 0x21, 0 + .dw 0xd040, 0xc91c, 0xd07f, 0xc91c, 0x21, 0 + .dw 0xd0c0, 0xc91c, 0xd0ff, 0xc91c, 0x21, 0 + .dw 0xd140, 0xc91c, 0xd17f, 0xc91c, 0x21, 0 + .dw 0xd1c0, 0xc91c, 0xd1ff, 0xc91c, 0x21, 0 + .dw 0xd240, 0xc91c, 0xd27f, 0xc91c, 0x21, 0 + .dw 0xd2c0, 0xc91c, 0xd2ff, 0xc91c, 0x21, 0 + .dw 0xd340, 0xc91c, 0xd37f, 0xc91c, 0x21, 0 + .dw 0xd3c0, 0xc91c, 0xd3ff, 0xc91c, 0x21, 0 + .dw 0xd440, 0xc91c, 0xd47f, 0xc91c, 0x21, 0 + .dw 0xd4c0, 0xc91c, 0xd4ff, 0xc91c, 0x21, 0 + .dw 0xd540, 0xc91c, 0xd57f, 0xc91c, 0x21, 0 + .dw 0xd5c0, 0xc91c, 0xd5ff, 0xc91c, 0x21, 0 + .dw 0xd640, 0xc91c, 0xd67f, 0xc91c, 0x21, 0 + .dw 0xd6c0, 0xc91c, 0xd6ff, 0xc91c, 0x21, 0 + .dw 0xd740, 0xc91c, 0xd77f, 0xc91c, 0x21, 0 + .dw 0xd7c0, 0xc91c, 0xd7ff, 0xc91c, 0x21, 0 + .dw 0xd840, 0xc91c, 0xd87f, 0xc91c, 0x21, 0 + .dw 0xd8c0, 0xc91c, 0xd8ff, 0xc91c, 0x21, 0 + .dw 0xd940, 0xc91c, 0xd97f, 0xc91c, 0x21, 0 + .dw 0xd9c0, 0xc91c, 0xdfff, 0xc91c, 0x21, 0 + .dw 0xe040, 0xc91c, 0xe07f, 0xc91c, 0x21, 0 + .dw 0xe0c0, 0xc91c, 0xe0ff, 0xc91c, 0x21, 0 + .dw 0xe140, 0xc91c, 0xe17f, 0xc91c, 0x21, 0 + .dw 0xe1c0, 0xc91c, 0xe1ff, 0xc91c, 0x21, 0 + .dw 0xe240, 0xc91c, 0xe27f, 0xc91c, 0x21, 0 + .dw 0xe2c0, 0xc91c, 0xe2ff, 0xc91c, 0x21, 0 + .dw 0xe340, 0xc91c, 0xe37f, 0xc91c, 0x21, 0 + .dw 0xe3c0, 0xc91c, 0xe3ff, 0xc91c, 0x21, 0 + .dw 0xe440, 0xc91c, 0xe47f, 0xc91c, 0x21, 0 + .dw 0xe4c0, 0xc91c, 0xe4ff, 0xc91c, 0x21, 0 + .dw 0xe540, 0xc91c, 0xe57f, 0xc91c, 0x21, 0 + .dw 0xe5c0, 0xc91c, 0xe5ff, 0xc91c, 0x21, 0 + .dw 0xe640, 0xc91c, 0xe67f, 0xc91c, 0x21, 0 + .dw 0xe6c0, 0xc91c, 0xe6ff, 0xc91c, 0x21, 0 + .dw 0xe740, 0xc91c, 0xe77f, 0xc91c, 0x21, 0 + .dw 0xe7c0, 0xc91c, 0xe7ff, 0xc91c, 0x21, 0 + .dw 0xe840, 0xc91c, 0xe87f, 0xc91c, 0x21, 0 + .dw 0xe8c0, 0xc91c, 0xe8ff, 0xc91c, 0x21, 0 + .dw 0xe940, 0xc91c, 0xe97f, 0xc91c, 0x21, 0 + .dw 0xe9c0, 0xc91c, 0xe9ff, 0xc91c, 0x21, 0 + .dw 0xea40, 0xc91c, 0xea7f, 0xc91c, 0x21, 0 + .dw 0xeac0, 0xc91c, 0xeaff, 0xc91c, 0x21, 0 + .dw 0xeb40, 0xc91c, 0xeb7f, 0xc91c, 0x21, 0 + .dw 0xebc0, 0xc91c, 0xebff, 0xc91c, 0x21, 0 + .dw 0xec40, 0xc91c, 0xec7f, 0xc91c, 0x21, 0 + .dw 0xecc0, 0xc91c, 0xecff, 0xc91c, 0x21, 0 + .dw 0xed40, 0xc91c, 0xed7f, 0xc91c, 0x21, 0 + .dw 0xedc0, 0xc91c, 0xedff, 0xc91c, 0x21, 0 + .dw 0xee40, 0xc91c, 0xee7f, 0xc91c, 0x21, 0 + .dw 0xeec0, 0xc91c, 0xeeff, 0xc91c, 0x21, 0 + .dw 0xef40, 0xc91c, 0xef7f, 0xc91c, 0x21, 0 + .dw 0xefc0, 0xc91c, 0xefff, 0xc91c, 0x21, 0 + .dw 0xf040, 0xc91c, 0xf07f, 0xc91c, 0x21, 0 + .dw 0xf0c0, 0xc91c, 0xf0ff, 0xc91c, 0x21, 0 + .dw 0xf140, 0xc91c, 0xf17f, 0xc91c, 0x21, 0 + .dw 0xf1c0, 0xc91c, 0xf1ff, 0xc91c, 0x21, 0 + .dw 0xf240, 0xc91c, 0xf27f, 0xc91c, 0x21, 0 + .dw 0xf2c0, 0xc91c, 0xf2ff, 0xc91c, 0x21, 0 + .dw 0xf340, 0xc91c, 0xf37f, 0xc91c, 0x21, 0 + .dw 0xf3c0, 0xc91c, 0xf3ff, 0xc91c, 0x21, 0 + .dw 0xf440, 0xc91c, 0xf47f, 0xc91c, 0x21, 0 + .dw 0xf4c0, 0xc91c, 0xf4ff, 0xc91c, 0x21, 0 + .dw 0xf540, 0xc91c, 0xf57f, 0xc91c, 0x21, 0 + .dw 0xf5c0, 0xc91c, 0xf5ff, 0xc91c, 0x21, 0 + .dw 0xf640, 0xc91c, 0xf67f, 0xc91c, 0x21, 0 + .dw 0xf6c0, 0xc91c, 0xf6ff, 0xc91c, 0x21, 0 + .dw 0xf740, 0xc91c, 0xf77f, 0xc91c, 0x21, 0 + .dw 0xf7c0, 0xc91c, 0xf7ff, 0xc91c, 0x21, 0 + .dw 0xf840, 0xc91c, 0xf87f, 0xc91c, 0x21, 0 + .dw 0xf8c0, 0xc91c, 0xf8ff, 0xc91c, 0x21, 0 + .dw 0xf940, 0xc91c, 0xf97f, 0xc91c, 0x21, 0 + .dw 0xf9c0, 0xc91c, 0xffff, 0xc91c, 0x21, 0 + .dw 0x0040, 0xc91d, 0x007f, 0xc91d, 0x21, 0 + .dw 0x00c0, 0xc91d, 0x00ff, 0xc91d, 0x21, 0 + .dw 0x0140, 0xc91d, 0x017f, 0xc91d, 0x21, 0 + .dw 0x01c0, 0xc91d, 0x01ff, 0xc91d, 0x21, 0 + .dw 0x0240, 0xc91d, 0x027f, 0xc91d, 0x21, 0 + .dw 0x02c0, 0xc91d, 0x02ff, 0xc91d, 0x21, 0 + .dw 0x0340, 0xc91d, 0x037f, 0xc91d, 0x21, 0 + .dw 0x03c0, 0xc91d, 0x03ff, 0xc91d, 0x21, 0 + .dw 0x0440, 0xc91d, 0x047f, 0xc91d, 0x21, 0 + .dw 0x04c0, 0xc91d, 0x04ff, 0xc91d, 0x21, 0 + .dw 0x0540, 0xc91d, 0x057f, 0xc91d, 0x21, 0 + .dw 0x05c0, 0xc91d, 0x05ff, 0xc91d, 0x21, 0 + .dw 0x0640, 0xc91d, 0x067f, 0xc91d, 0x21, 0 + .dw 0x06c0, 0xc91d, 0x06ff, 0xc91d, 0x21, 0 + .dw 0x0740, 0xc91d, 0x077f, 0xc91d, 0x21, 0 + .dw 0x07c0, 0xc91d, 0x07ff, 0xc91d, 0x21, 0 + .dw 0x0840, 0xc91d, 0x087f, 0xc91d, 0x21, 0 + .dw 0x08c0, 0xc91d, 0x08ff, 0xc91d, 0x21, 0 + .dw 0x0940, 0xc91d, 0x097f, 0xc91d, 0x21, 0 + .dw 0x09c0, 0xc91d, 0x09ff, 0xc91d, 0x21, 0 + .dw 0x0a40, 0xc91d, 0x0a7f, 0xc91d, 0x21, 0 + .dw 0x0ac0, 0xc91d, 0x0aff, 0xc91d, 0x21, 0 + .dw 0x0b40, 0xc91d, 0x0b7f, 0xc91d, 0x21, 0 + .dw 0x0bc0, 0xc91d, 0x0bff, 0xc91d, 0x21, 0 + .dw 0x0c40, 0xc91d, 0x0c7f, 0xc91d, 0x21, 0 + .dw 0x0cc0, 0xc91d, 0x0cff, 0xc91d, 0x21, 0 + .dw 0x0d40, 0xc91d, 0x0d7f, 0xc91d, 0x21, 0 + .dw 0x0dc0, 0xc91d, 0x0dff, 0xc91d, 0x21, 0 + .dw 0x0e40, 0xc91d, 0x0e7f, 0xc91d, 0x21, 0 + .dw 0x0ec0, 0xc91d, 0x0eff, 0xc91d, 0x21, 0 + .dw 0x0f40, 0xc91d, 0x0f7f, 0xc91d, 0x21, 0 + .dw 0x0fc0, 0xc91d, 0x0fff, 0xc91d, 0x21, 0 + .dw 0x1040, 0xc91d, 0x107f, 0xc91d, 0x21, 0 + .dw 0x10c0, 0xc91d, 0x10ff, 0xc91d, 0x21, 0 + .dw 0x1140, 0xc91d, 0x117f, 0xc91d, 0x21, 0 + .dw 0x11c0, 0xc91d, 0x11ff, 0xc91d, 0x21, 0 + .dw 0x1240, 0xc91d, 0x127f, 0xc91d, 0x21, 0 + .dw 0x12c0, 0xc91d, 0x12ff, 0xc91d, 0x21, 0 + .dw 0x1340, 0xc91d, 0x137f, 0xc91d, 0x21, 0 + .dw 0x13c0, 0xc91d, 0x13ff, 0xc91d, 0x21, 0 + .dw 0x1440, 0xc91d, 0x147f, 0xc91d, 0x21, 0 + .dw 0x14c0, 0xc91d, 0x14ff, 0xc91d, 0x21, 0 + .dw 0x1540, 0xc91d, 0x157f, 0xc91d, 0x21, 0 + .dw 0x15c0, 0xc91d, 0x15ff, 0xc91d, 0x21, 0 + .dw 0x1640, 0xc91d, 0x167f, 0xc91d, 0x21, 0 + .dw 0x16c0, 0xc91d, 0x16ff, 0xc91d, 0x21, 0 + .dw 0x1740, 0xc91d, 0x177f, 0xc91d, 0x21, 0 + .dw 0x17c0, 0xc91d, 0x17ff, 0xc91d, 0x21, 0 + .dw 0x1840, 0xc91d, 0x187f, 0xc91d, 0x21, 0 + .dw 0x18c0, 0xc91d, 0x18ff, 0xc91d, 0x21, 0 + .dw 0x1940, 0xc91d, 0x197f, 0xc91d, 0x21, 0 + .dw 0x19c0, 0xc91d, 0x1fff, 0xc91d, 0x21, 0 + .dw 0x2040, 0xc91d, 0x207f, 0xc91d, 0x21, 0 + .dw 0x20c0, 0xc91d, 0x20ff, 0xc91d, 0x21, 0 + .dw 0x2140, 0xc91d, 0x217f, 0xc91d, 0x21, 0 + .dw 0x21c0, 0xc91d, 0x21ff, 0xc91d, 0x21, 0 + .dw 0x2240, 0xc91d, 0x227f, 0xc91d, 0x21, 0 + .dw 0x22c0, 0xc91d, 0x22ff, 0xc91d, 0x21, 0 + .dw 0x2340, 0xc91d, 0x237f, 0xc91d, 0x21, 0 + .dw 0x23c0, 0xc91d, 0x23ff, 0xc91d, 0x21, 0 + .dw 0x2440, 0xc91d, 0x247f, 0xc91d, 0x21, 0 + .dw 0x24c0, 0xc91d, 0x24ff, 0xc91d, 0x21, 0 + .dw 0x2540, 0xc91d, 0x257f, 0xc91d, 0x21, 0 + .dw 0x25c0, 0xc91d, 0x25ff, 0xc91d, 0x21, 0 + .dw 0x2640, 0xc91d, 0x267f, 0xc91d, 0x21, 0 + .dw 0x26c0, 0xc91d, 0x26ff, 0xc91d, 0x21, 0 + .dw 0x2740, 0xc91d, 0x277f, 0xc91d, 0x21, 0 + .dw 0x27c0, 0xc91d, 0x27ff, 0xc91d, 0x21, 0 + .dw 0x2840, 0xc91d, 0x287f, 0xc91d, 0x21, 0 + .dw 0x28c0, 0xc91d, 0x28ff, 0xc91d, 0x21, 0 + .dw 0x2940, 0xc91d, 0x297f, 0xc91d, 0x21, 0 + .dw 0x29c0, 0xc91d, 0x29ff, 0xc91d, 0x21, 0 + .dw 0x2a40, 0xc91d, 0x2a7f, 0xc91d, 0x21, 0 + .dw 0x2ac0, 0xc91d, 0x2aff, 0xc91d, 0x21, 0 + .dw 0x2b40, 0xc91d, 0x2b7f, 0xc91d, 0x21, 0 + .dw 0x2bc0, 0xc91d, 0x2bff, 0xc91d, 0x21, 0 + .dw 0x2c40, 0xc91d, 0x2c7f, 0xc91d, 0x21, 0 + .dw 0x2cc0, 0xc91d, 0x2cff, 0xc91d, 0x21, 0 + .dw 0x2d40, 0xc91d, 0x2d7f, 0xc91d, 0x21, 0 + .dw 0x2dc0, 0xc91d, 0x2dff, 0xc91d, 0x21, 0 + .dw 0x2e40, 0xc91d, 0x2e7f, 0xc91d, 0x21, 0 + .dw 0x2ec0, 0xc91d, 0x2eff, 0xc91d, 0x21, 0 + .dw 0x2f40, 0xc91d, 0x2f7f, 0xc91d, 0x21, 0 + .dw 0x2fc0, 0xc91d, 0x2fff, 0xc91d, 0x21, 0 + .dw 0x3040, 0xc91d, 0x307f, 0xc91d, 0x21, 0 + .dw 0x30c0, 0xc91d, 0x30ff, 0xc91d, 0x21, 0 + .dw 0x3140, 0xc91d, 0x317f, 0xc91d, 0x21, 0 + .dw 0x31c0, 0xc91d, 0x31ff, 0xc91d, 0x21, 0 + .dw 0x3240, 0xc91d, 0x327f, 0xc91d, 0x21, 0 + .dw 0x32c0, 0xc91d, 0x32ff, 0xc91d, 0x21, 0 + .dw 0x3340, 0xc91d, 0x337f, 0xc91d, 0x21, 0 + .dw 0x33c0, 0xc91d, 0x33ff, 0xc91d, 0x21, 0 + .dw 0x3440, 0xc91d, 0x347f, 0xc91d, 0x21, 0 + .dw 0x34c0, 0xc91d, 0x34ff, 0xc91d, 0x21, 0 + .dw 0x3540, 0xc91d, 0x357f, 0xc91d, 0x21, 0 + .dw 0x35c0, 0xc91d, 0x35ff, 0xc91d, 0x21, 0 + .dw 0x3640, 0xc91d, 0x367f, 0xc91d, 0x21, 0 + .dw 0x36c0, 0xc91d, 0x36ff, 0xc91d, 0x21, 0 + .dw 0x3740, 0xc91d, 0x377f, 0xc91d, 0x21, 0 + .dw 0x37c0, 0xc91d, 0x37ff, 0xc91d, 0x21, 0 + .dw 0x3840, 0xc91d, 0x387f, 0xc91d, 0x21, 0 + .dw 0x38c0, 0xc91d, 0x38ff, 0xc91d, 0x21, 0 + .dw 0x3940, 0xc91d, 0x397f, 0xc91d, 0x21, 0 + .dw 0x39c0, 0xc91d, 0x3fff, 0xc91d, 0x21, 0 + .dw 0x4040, 0xc91d, 0x407f, 0xc91d, 0x21, 0 + .dw 0x40c0, 0xc91d, 0x40ff, 0xc91d, 0x21, 0 + .dw 0x4140, 0xc91d, 0x417f, 0xc91d, 0x21, 0 + .dw 0x41c0, 0xc91d, 0x41ff, 0xc91d, 0x21, 0 + .dw 0x4240, 0xc91d, 0x427f, 0xc91d, 0x21, 0 + .dw 0x42c0, 0xc91d, 0x42ff, 0xc91d, 0x21, 0 + .dw 0x4340, 0xc91d, 0x437f, 0xc91d, 0x21, 0 + .dw 0x43c0, 0xc91d, 0x43ff, 0xc91d, 0x21, 0 + .dw 0x4440, 0xc91d, 0x447f, 0xc91d, 0x21, 0 + .dw 0x44c0, 0xc91d, 0x44ff, 0xc91d, 0x21, 0 + .dw 0x4540, 0xc91d, 0x457f, 0xc91d, 0x21, 0 + .dw 0x45c0, 0xc91d, 0x45ff, 0xc91d, 0x21, 0 + .dw 0x4640, 0xc91d, 0x467f, 0xc91d, 0x21, 0 + .dw 0x46c0, 0xc91d, 0x46ff, 0xc91d, 0x21, 0 + .dw 0x4740, 0xc91d, 0x477f, 0xc91d, 0x21, 0 + .dw 0x47c0, 0xc91d, 0x47ff, 0xc91d, 0x21, 0 + .dw 0x4840, 0xc91d, 0x487f, 0xc91d, 0x21, 0 + .dw 0x48c0, 0xc91d, 0x48ff, 0xc91d, 0x21, 0 + .dw 0x4940, 0xc91d, 0x497f, 0xc91d, 0x21, 0 + .dw 0x49c0, 0xc91d, 0x49ff, 0xc91d, 0x21, 0 + .dw 0x4a40, 0xc91d, 0x4a7f, 0xc91d, 0x21, 0 + .dw 0x4ac0, 0xc91d, 0x4aff, 0xc91d, 0x21, 0 + .dw 0x4b40, 0xc91d, 0x4b7f, 0xc91d, 0x21, 0 + .dw 0x4bc0, 0xc91d, 0x4bff, 0xc91d, 0x21, 0 + .dw 0x4c40, 0xc91d, 0x4c7f, 0xc91d, 0x21, 0 + .dw 0x4cc0, 0xc91d, 0x4cff, 0xc91d, 0x21, 0 + .dw 0x4d40, 0xc91d, 0x4d7f, 0xc91d, 0x21, 0 + .dw 0x4dc0, 0xc91d, 0x4dff, 0xc91d, 0x21, 0 + .dw 0x4e40, 0xc91d, 0x4e7f, 0xc91d, 0x21, 0 + .dw 0x4ec0, 0xc91d, 0x4eff, 0xc91d, 0x21, 0 + .dw 0x4f40, 0xc91d, 0x4f7f, 0xc91d, 0x21, 0 + .dw 0x4fc0, 0xc91d, 0x4fff, 0xc91d, 0x21, 0 + .dw 0x5040, 0xc91d, 0x507f, 0xc91d, 0x21, 0 + .dw 0x50c0, 0xc91d, 0x50ff, 0xc91d, 0x21, 0 + .dw 0x5140, 0xc91d, 0x517f, 0xc91d, 0x21, 0 + .dw 0x51c0, 0xc91d, 0x51ff, 0xc91d, 0x21, 0 + .dw 0x5240, 0xc91d, 0x527f, 0xc91d, 0x21, 0 + .dw 0x52c0, 0xc91d, 0x52ff, 0xc91d, 0x21, 0 + .dw 0x5340, 0xc91d, 0x537f, 0xc91d, 0x21, 0 + .dw 0x53c0, 0xc91d, 0x53ff, 0xc91d, 0x21, 0 + .dw 0x5440, 0xc91d, 0x547f, 0xc91d, 0x21, 0 + .dw 0x54c0, 0xc91d, 0x54ff, 0xc91d, 0x21, 0 + .dw 0x5540, 0xc91d, 0x557f, 0xc91d, 0x21, 0 + .dw 0x55c0, 0xc91d, 0x55ff, 0xc91d, 0x21, 0 + .dw 0x5640, 0xc91d, 0x567f, 0xc91d, 0x21, 0 + .dw 0x56c0, 0xc91d, 0x56ff, 0xc91d, 0x21, 0 + .dw 0x5740, 0xc91d, 0x577f, 0xc91d, 0x21, 0 + .dw 0x57c0, 0xc91d, 0x57ff, 0xc91d, 0x21, 0 + .dw 0x5840, 0xc91d, 0x587f, 0xc91d, 0x21, 0 + .dw 0x58c0, 0xc91d, 0x58ff, 0xc91d, 0x21, 0 + .dw 0x5940, 0xc91d, 0x597f, 0xc91d, 0x21, 0 + .dw 0x59c0, 0xc91d, 0x5fff, 0xc91d, 0x21, 0 + .dw 0x6040, 0xc91d, 0x607f, 0xc91d, 0x21, 0 + .dw 0x60c0, 0xc91d, 0x60ff, 0xc91d, 0x21, 0 + .dw 0x6140, 0xc91d, 0x617f, 0xc91d, 0x21, 0 + .dw 0x61c0, 0xc91d, 0x61ff, 0xc91d, 0x21, 0 + .dw 0x6240, 0xc91d, 0x627f, 0xc91d, 0x21, 0 + .dw 0x62c0, 0xc91d, 0x62ff, 0xc91d, 0x21, 0 + .dw 0x6340, 0xc91d, 0x637f, 0xc91d, 0x21, 0 + .dw 0x63c0, 0xc91d, 0x63ff, 0xc91d, 0x21, 0 + .dw 0x6440, 0xc91d, 0x647f, 0xc91d, 0x21, 0 + .dw 0x64c0, 0xc91d, 0x64ff, 0xc91d, 0x21, 0 + .dw 0x6540, 0xc91d, 0x657f, 0xc91d, 0x21, 0 + .dw 0x65c0, 0xc91d, 0x65ff, 0xc91d, 0x21, 0 + .dw 0x6640, 0xc91d, 0x667f, 0xc91d, 0x21, 0 + .dw 0x66c0, 0xc91d, 0x66ff, 0xc91d, 0x21, 0 + .dw 0x6740, 0xc91d, 0x677f, 0xc91d, 0x21, 0 + .dw 0x67c0, 0xc91d, 0x67ff, 0xc91d, 0x21, 0 + .dw 0x6840, 0xc91d, 0x687f, 0xc91d, 0x21, 0 + .dw 0x68c0, 0xc91d, 0x68ff, 0xc91d, 0x21, 0 + .dw 0x6940, 0xc91d, 0x697f, 0xc91d, 0x21, 0 + .dw 0x69c0, 0xc91d, 0x69ff, 0xc91d, 0x21, 0 + .dw 0x6a40, 0xc91d, 0x6a7f, 0xc91d, 0x21, 0 + .dw 0x6ac0, 0xc91d, 0x6aff, 0xc91d, 0x21, 0 + .dw 0x6b40, 0xc91d, 0x6b7f, 0xc91d, 0x21, 0 + .dw 0x6bc0, 0xc91d, 0x6bff, 0xc91d, 0x21, 0 + .dw 0x6c40, 0xc91d, 0x6c7f, 0xc91d, 0x21, 0 + .dw 0x6cc0, 0xc91d, 0x6cff, 0xc91d, 0x21, 0 + .dw 0x6d40, 0xc91d, 0x6d7f, 0xc91d, 0x21, 0 + .dw 0x6dc0, 0xc91d, 0x6dff, 0xc91d, 0x21, 0 + .dw 0x6e40, 0xc91d, 0x6e7f, 0xc91d, 0x21, 0 + .dw 0x6ec0, 0xc91d, 0x6eff, 0xc91d, 0x21, 0 + .dw 0x6f40, 0xc91d, 0x6f7f, 0xc91d, 0x21, 0 + .dw 0x6fc0, 0xc91d, 0x6fff, 0xc91d, 0x21, 0 + .dw 0x7040, 0xc91d, 0x707f, 0xc91d, 0x21, 0 + .dw 0x70c0, 0xc91d, 0x70ff, 0xc91d, 0x21, 0 + .dw 0x7140, 0xc91d, 0x717f, 0xc91d, 0x21, 0 + .dw 0x71c0, 0xc91d, 0x71ff, 0xc91d, 0x21, 0 + .dw 0x7240, 0xc91d, 0x727f, 0xc91d, 0x21, 0 + .dw 0x72c0, 0xc91d, 0x72ff, 0xc91d, 0x21, 0 + .dw 0x7340, 0xc91d, 0x737f, 0xc91d, 0x21, 0 + .dw 0x73c0, 0xc91d, 0x73ff, 0xc91d, 0x21, 0 + .dw 0x7440, 0xc91d, 0x747f, 0xc91d, 0x21, 0 + .dw 0x74c0, 0xc91d, 0x74ff, 0xc91d, 0x21, 0 + .dw 0x7540, 0xc91d, 0x757f, 0xc91d, 0x21, 0 + .dw 0x75c0, 0xc91d, 0x75ff, 0xc91d, 0x21, 0 + .dw 0x7640, 0xc91d, 0x767f, 0xc91d, 0x21, 0 + .dw 0x76c0, 0xc91d, 0x76ff, 0xc91d, 0x21, 0 + .dw 0x7740, 0xc91d, 0x777f, 0xc91d, 0x21, 0 + .dw 0x77c0, 0xc91d, 0x77ff, 0xc91d, 0x21, 0 + .dw 0x7840, 0xc91d, 0x787f, 0xc91d, 0x21, 0 + .dw 0x78c0, 0xc91d, 0x78ff, 0xc91d, 0x21, 0 + .dw 0x7940, 0xc91d, 0x797f, 0xc91d, 0x21, 0 + .dw 0x79c0, 0xc91d, 0x7fff, 0xc91d, 0x21, 0 + .dw 0x8040, 0xc91d, 0x807f, 0xc91d, 0x21, 0 + .dw 0x80c0, 0xc91d, 0x80ff, 0xc91d, 0x21, 0 + .dw 0x8140, 0xc91d, 0x817f, 0xc91d, 0x21, 0 + .dw 0x81c0, 0xc91d, 0x81ff, 0xc91d, 0x21, 0 + .dw 0x8240, 0xc91d, 0x827f, 0xc91d, 0x21, 0 + .dw 0x82c0, 0xc91d, 0x82ff, 0xc91d, 0x21, 0 + .dw 0x8340, 0xc91d, 0x837f, 0xc91d, 0x21, 0 + .dw 0x83c0, 0xc91d, 0x83ff, 0xc91d, 0x21, 0 + .dw 0x8440, 0xc91d, 0x847f, 0xc91d, 0x21, 0 + .dw 0x84c0, 0xc91d, 0x84ff, 0xc91d, 0x21, 0 + .dw 0x8540, 0xc91d, 0x857f, 0xc91d, 0x21, 0 + .dw 0x85c0, 0xc91d, 0x85ff, 0xc91d, 0x21, 0 + .dw 0x8640, 0xc91d, 0x867f, 0xc91d, 0x21, 0 + .dw 0x86c0, 0xc91d, 0x86ff, 0xc91d, 0x21, 0 + .dw 0x8740, 0xc91d, 0x877f, 0xc91d, 0x21, 0 + .dw 0x87c0, 0xc91d, 0x87ff, 0xc91d, 0x21, 0 + .dw 0x8840, 0xc91d, 0x887f, 0xc91d, 0x21, 0 + .dw 0x88c0, 0xc91d, 0x88ff, 0xc91d, 0x21, 0 + .dw 0x8940, 0xc91d, 0x897f, 0xc91d, 0x21, 0 + .dw 0x89c0, 0xc91d, 0x89ff, 0xc91d, 0x21, 0 + .dw 0x8a40, 0xc91d, 0x8a7f, 0xc91d, 0x21, 0 + .dw 0x8ac0, 0xc91d, 0x8aff, 0xc91d, 0x21, 0 + .dw 0x8b40, 0xc91d, 0x8b7f, 0xc91d, 0x21, 0 + .dw 0x8bc0, 0xc91d, 0x8bff, 0xc91d, 0x21, 0 + .dw 0x8c40, 0xc91d, 0x8c7f, 0xc91d, 0x21, 0 + .dw 0x8cc0, 0xc91d, 0x8cff, 0xc91d, 0x21, 0 + .dw 0x8d40, 0xc91d, 0x8d7f, 0xc91d, 0x21, 0 + .dw 0x8dc0, 0xc91d, 0x8dff, 0xc91d, 0x21, 0 + .dw 0x8e40, 0xc91d, 0x8e7f, 0xc91d, 0x21, 0 + .dw 0x8ec0, 0xc91d, 0x8eff, 0xc91d, 0x21, 0 + .dw 0x8f40, 0xc91d, 0x8f7f, 0xc91d, 0x21, 0 + .dw 0x8fc0, 0xc91d, 0x8fff, 0xc91d, 0x21, 0 + .dw 0x9040, 0xc91d, 0x907f, 0xc91d, 0x21, 0 + .dw 0x90c0, 0xc91d, 0x90ff, 0xc91d, 0x21, 0 + .dw 0x9140, 0xc91d, 0x917f, 0xc91d, 0x21, 0 + .dw 0x91c0, 0xc91d, 0x91ff, 0xc91d, 0x21, 0 + .dw 0x9240, 0xc91d, 0x927f, 0xc91d, 0x21, 0 + .dw 0x92c0, 0xc91d, 0x92ff, 0xc91d, 0x21, 0 + .dw 0x9340, 0xc91d, 0x937f, 0xc91d, 0x21, 0 + .dw 0x93c0, 0xc91d, 0x93ff, 0xc91d, 0x21, 0 + .dw 0x9440, 0xc91d, 0x947f, 0xc91d, 0x21, 0 + .dw 0x94c0, 0xc91d, 0x94ff, 0xc91d, 0x21, 0 + .dw 0x9540, 0xc91d, 0x957f, 0xc91d, 0x21, 0 + .dw 0x95c0, 0xc91d, 0x95ff, 0xc91d, 0x21, 0 + .dw 0x9640, 0xc91d, 0x967f, 0xc91d, 0x21, 0 + .dw 0x96c0, 0xc91d, 0x96ff, 0xc91d, 0x21, 0 + .dw 0x9740, 0xc91d, 0x977f, 0xc91d, 0x21, 0 + .dw 0x97c0, 0xc91d, 0x97ff, 0xc91d, 0x21, 0 + .dw 0x9840, 0xc91d, 0x987f, 0xc91d, 0x21, 0 + .dw 0x98c0, 0xc91d, 0x98ff, 0xc91d, 0x21, 0 + .dw 0x9940, 0xc91d, 0x997f, 0xc91d, 0x21, 0 + .dw 0x99c0, 0xc91d, 0x9fff, 0xc91d, 0x21, 0 + .dw 0xa040, 0xc91d, 0xa07f, 0xc91d, 0x21, 0 + .dw 0xa0c0, 0xc91d, 0xa0ff, 0xc91d, 0x21, 0 + .dw 0xa140, 0xc91d, 0xa17f, 0xc91d, 0x21, 0 + .dw 0xa1c0, 0xc91d, 0xa1ff, 0xc91d, 0x21, 0 + .dw 0xa240, 0xc91d, 0xa27f, 0xc91d, 0x21, 0 + .dw 0xa2c0, 0xc91d, 0xa2ff, 0xc91d, 0x21, 0 + .dw 0xa340, 0xc91d, 0xa37f, 0xc91d, 0x21, 0 + .dw 0xa3c0, 0xc91d, 0xa3ff, 0xc91d, 0x21, 0 + .dw 0xa440, 0xc91d, 0xa47f, 0xc91d, 0x21, 0 + .dw 0xa4c0, 0xc91d, 0xa4ff, 0xc91d, 0x21, 0 + .dw 0xa540, 0xc91d, 0xa57f, 0xc91d, 0x21, 0 + .dw 0xa5c0, 0xc91d, 0xa5ff, 0xc91d, 0x21, 0 + .dw 0xa640, 0xc91d, 0xa67f, 0xc91d, 0x21, 0 + .dw 0xa6c0, 0xc91d, 0xa6ff, 0xc91d, 0x21, 0 + .dw 0xa740, 0xc91d, 0xa77f, 0xc91d, 0x21, 0 + .dw 0xa7c0, 0xc91d, 0xa7ff, 0xc91d, 0x21, 0 + .dw 0xa840, 0xc91d, 0xa87f, 0xc91d, 0x21, 0 + .dw 0xa8c0, 0xc91d, 0xa8ff, 0xc91d, 0x21, 0 + .dw 0xa940, 0xc91d, 0xa97f, 0xc91d, 0x21, 0 + .dw 0xa9c0, 0xc91d, 0xa9ff, 0xc91d, 0x21, 0 + .dw 0xaa40, 0xc91d, 0xaa7f, 0xc91d, 0x21, 0 + .dw 0xaac0, 0xc91d, 0xaaff, 0xc91d, 0x21, 0 + .dw 0xab40, 0xc91d, 0xab7f, 0xc91d, 0x21, 0 + .dw 0xabc0, 0xc91d, 0xabff, 0xc91d, 0x21, 0 + .dw 0xac40, 0xc91d, 0xac7f, 0xc91d, 0x21, 0 + .dw 0xacc0, 0xc91d, 0xacff, 0xc91d, 0x21, 0 + .dw 0xad40, 0xc91d, 0xad7f, 0xc91d, 0x21, 0 + .dw 0xadc0, 0xc91d, 0xadff, 0xc91d, 0x21, 0 + .dw 0xae40, 0xc91d, 0xae7f, 0xc91d, 0x21, 0 + .dw 0xaec0, 0xc91d, 0xaeff, 0xc91d, 0x21, 0 + .dw 0xaf40, 0xc91d, 0xaf7f, 0xc91d, 0x21, 0 + .dw 0xafc0, 0xc91d, 0xafff, 0xc91d, 0x21, 0 + .dw 0xb040, 0xc91d, 0xb07f, 0xc91d, 0x21, 0 + .dw 0xb0c0, 0xc91d, 0xb0ff, 0xc91d, 0x21, 0 + .dw 0xb140, 0xc91d, 0xb17f, 0xc91d, 0x21, 0 + .dw 0xb1c0, 0xc91d, 0xb1ff, 0xc91d, 0x21, 0 + .dw 0xb240, 0xc91d, 0xb27f, 0xc91d, 0x21, 0 + .dw 0xb2c0, 0xc91d, 0xb2ff, 0xc91d, 0x21, 0 + .dw 0xb340, 0xc91d, 0xb37f, 0xc91d, 0x21, 0 + .dw 0xb3c0, 0xc91d, 0xb3ff, 0xc91d, 0x21, 0 + .dw 0xb440, 0xc91d, 0xb47f, 0xc91d, 0x21, 0 + .dw 0xb4c0, 0xc91d, 0xb4ff, 0xc91d, 0x21, 0 + .dw 0xb540, 0xc91d, 0xb57f, 0xc91d, 0x21, 0 + .dw 0xb5c0, 0xc91d, 0xb5ff, 0xc91d, 0x21, 0 + .dw 0xb640, 0xc91d, 0xb67f, 0xc91d, 0x21, 0 + .dw 0xb6c0, 0xc91d, 0xb6ff, 0xc91d, 0x21, 0 + .dw 0xb740, 0xc91d, 0xb77f, 0xc91d, 0x21, 0 + .dw 0xb7c0, 0xc91d, 0xb7ff, 0xc91d, 0x21, 0 + .dw 0xb840, 0xc91d, 0xb87f, 0xc91d, 0x21, 0 + .dw 0xb8c0, 0xc91d, 0xb8ff, 0xc91d, 0x21, 0 + .dw 0xb940, 0xc91d, 0xb97f, 0xc91d, 0x21, 0 + .dw 0xb9c0, 0xc91d, 0xbfff, 0xc91d, 0x21, 0 + .dw 0xc040, 0xc91d, 0xc07f, 0xc91d, 0x21, 0 + .dw 0xc0c0, 0xc91d, 0xc0ff, 0xc91d, 0x21, 0 + .dw 0xc140, 0xc91d, 0xc17f, 0xc91d, 0x21, 0 + .dw 0xc1c0, 0xc91d, 0xc1ff, 0xc91d, 0x21, 0 + .dw 0xc240, 0xc91d, 0xc27f, 0xc91d, 0x21, 0 + .dw 0xc2c0, 0xc91d, 0xc2ff, 0xc91d, 0x21, 0 + .dw 0xc340, 0xc91d, 0xc37f, 0xc91d, 0x21, 0 + .dw 0xc3c0, 0xc91d, 0xc3ff, 0xc91d, 0x21, 0 + .dw 0xc440, 0xc91d, 0xc47f, 0xc91d, 0x21, 0 + .dw 0xc4c0, 0xc91d, 0xc4ff, 0xc91d, 0x21, 0 + .dw 0xc540, 0xc91d, 0xc57f, 0xc91d, 0x21, 0 + .dw 0xc5c0, 0xc91d, 0xc5ff, 0xc91d, 0x21, 0 + .dw 0xc640, 0xc91d, 0xc67f, 0xc91d, 0x21, 0 + .dw 0xc6c0, 0xc91d, 0xc6ff, 0xc91d, 0x21, 0 + .dw 0xc740, 0xc91d, 0xc77f, 0xc91d, 0x21, 0 + .dw 0xc7c0, 0xc91d, 0xc7ff, 0xc91d, 0x21, 0 + .dw 0xc840, 0xc91d, 0xc87f, 0xc91d, 0x21, 0 + .dw 0xc8c0, 0xc91d, 0xc8ff, 0xc91d, 0x21, 0 + .dw 0xc940, 0xc91d, 0xc97f, 0xc91d, 0x21, 0 + .dw 0xc9c0, 0xc91d, 0xc9ff, 0xc91d, 0x21, 0 + .dw 0xca40, 0xc91d, 0xca7f, 0xc91d, 0x21, 0 + .dw 0xcac0, 0xc91d, 0xcaff, 0xc91d, 0x21, 0 + .dw 0xcb40, 0xc91d, 0xcb7f, 0xc91d, 0x21, 0 + .dw 0xcbc0, 0xc91d, 0xcbff, 0xc91d, 0x21, 0 + .dw 0xcc40, 0xc91d, 0xcc7f, 0xc91d, 0x21, 0 + .dw 0xccc0, 0xc91d, 0xccff, 0xc91d, 0x21, 0 + .dw 0xcd40, 0xc91d, 0xcd7f, 0xc91d, 0x21, 0 + .dw 0xcdc0, 0xc91d, 0xcdff, 0xc91d, 0x21, 0 + .dw 0xce40, 0xc91d, 0xce7f, 0xc91d, 0x21, 0 + .dw 0xcec0, 0xc91d, 0xceff, 0xc91d, 0x21, 0 + .dw 0xcf40, 0xc91d, 0xcf7f, 0xc91d, 0x21, 0 + .dw 0xcfc0, 0xc91d, 0xcfff, 0xc91d, 0x21, 0 + .dw 0xd040, 0xc91d, 0xd07f, 0xc91d, 0x21, 0 + .dw 0xd0c0, 0xc91d, 0xd0ff, 0xc91d, 0x21, 0 + .dw 0xd140, 0xc91d, 0xd17f, 0xc91d, 0x21, 0 + .dw 0xd1c0, 0xc91d, 0xd1ff, 0xc91d, 0x21, 0 + .dw 0xd240, 0xc91d, 0xd27f, 0xc91d, 0x21, 0 + .dw 0xd2c0, 0xc91d, 0xd2ff, 0xc91d, 0x21, 0 + .dw 0xd340, 0xc91d, 0xd37f, 0xc91d, 0x21, 0 + .dw 0xd3c0, 0xc91d, 0xd3ff, 0xc91d, 0x21, 0 + .dw 0xd440, 0xc91d, 0xd47f, 0xc91d, 0x21, 0 + .dw 0xd4c0, 0xc91d, 0xd4ff, 0xc91d, 0x21, 0 + .dw 0xd540, 0xc91d, 0xd57f, 0xc91d, 0x21, 0 + .dw 0xd5c0, 0xc91d, 0xd5ff, 0xc91d, 0x21, 0 + .dw 0xd640, 0xc91d, 0xd67f, 0xc91d, 0x21, 0 + .dw 0xd6c0, 0xc91d, 0xd6ff, 0xc91d, 0x21, 0 + .dw 0xd740, 0xc91d, 0xd77f, 0xc91d, 0x21, 0 + .dw 0xd7c0, 0xc91d, 0xd7ff, 0xc91d, 0x21, 0 + .dw 0xd840, 0xc91d, 0xd87f, 0xc91d, 0x21, 0 + .dw 0xd8c0, 0xc91d, 0xd8ff, 0xc91d, 0x21, 0 + .dw 0xd940, 0xc91d, 0xd97f, 0xc91d, 0x21, 0 + .dw 0xd9c0, 0xc91d, 0xdfff, 0xc91d, 0x21, 0 + .dw 0xe040, 0xc91d, 0xe07f, 0xc91d, 0x21, 0 + .dw 0xe0c0, 0xc91d, 0xe0ff, 0xc91d, 0x21, 0 + .dw 0xe140, 0xc91d, 0xe17f, 0xc91d, 0x21, 0 + .dw 0xe1c0, 0xc91d, 0xe1ff, 0xc91d, 0x21, 0 + .dw 0xe240, 0xc91d, 0xe27f, 0xc91d, 0x21, 0 + .dw 0xe2c0, 0xc91d, 0xe2ff, 0xc91d, 0x21, 0 + .dw 0xe340, 0xc91d, 0xe37f, 0xc91d, 0x21, 0 + .dw 0xe3c0, 0xc91d, 0xe3ff, 0xc91d, 0x21, 0 + .dw 0xe440, 0xc91d, 0xe47f, 0xc91d, 0x21, 0 + .dw 0xe4c0, 0xc91d, 0xe4ff, 0xc91d, 0x21, 0 + .dw 0xe540, 0xc91d, 0xe57f, 0xc91d, 0x21, 0 + .dw 0xe5c0, 0xc91d, 0xe5ff, 0xc91d, 0x21, 0 + .dw 0xe640, 0xc91d, 0xe67f, 0xc91d, 0x21, 0 + .dw 0xe6c0, 0xc91d, 0xe6ff, 0xc91d, 0x21, 0 + .dw 0xe740, 0xc91d, 0xe77f, 0xc91d, 0x21, 0 + .dw 0xe7c0, 0xc91d, 0xe7ff, 0xc91d, 0x21, 0 + .dw 0xe840, 0xc91d, 0xe87f, 0xc91d, 0x21, 0 + .dw 0xe8c0, 0xc91d, 0xe8ff, 0xc91d, 0x21, 0 + .dw 0xe940, 0xc91d, 0xe97f, 0xc91d, 0x21, 0 + .dw 0xe9c0, 0xc91d, 0xe9ff, 0xc91d, 0x21, 0 + .dw 0xea40, 0xc91d, 0xea7f, 0xc91d, 0x21, 0 + .dw 0xeac0, 0xc91d, 0xeaff, 0xc91d, 0x21, 0 + .dw 0xeb40, 0xc91d, 0xeb7f, 0xc91d, 0x21, 0 + .dw 0xebc0, 0xc91d, 0xebff, 0xc91d, 0x21, 0 + .dw 0xec40, 0xc91d, 0xec7f, 0xc91d, 0x21, 0 + .dw 0xecc0, 0xc91d, 0xecff, 0xc91d, 0x21, 0 + .dw 0xed40, 0xc91d, 0xed7f, 0xc91d, 0x21, 0 + .dw 0xedc0, 0xc91d, 0xedff, 0xc91d, 0x21, 0 + .dw 0xee40, 0xc91d, 0xee7f, 0xc91d, 0x21, 0 + .dw 0xeec0, 0xc91d, 0xeeff, 0xc91d, 0x21, 0 + .dw 0xef40, 0xc91d, 0xef7f, 0xc91d, 0x21, 0 + .dw 0xefc0, 0xc91d, 0xefff, 0xc91d, 0x21, 0 + .dw 0xf040, 0xc91d, 0xf07f, 0xc91d, 0x21, 0 + .dw 0xf0c0, 0xc91d, 0xf0ff, 0xc91d, 0x21, 0 + .dw 0xf140, 0xc91d, 0xf17f, 0xc91d, 0x21, 0 + .dw 0xf1c0, 0xc91d, 0xf1ff, 0xc91d, 0x21, 0 + .dw 0xf240, 0xc91d, 0xf27f, 0xc91d, 0x21, 0 + .dw 0xf2c0, 0xc91d, 0xf2ff, 0xc91d, 0x21, 0 + .dw 0xf340, 0xc91d, 0xf37f, 0xc91d, 0x21, 0 + .dw 0xf3c0, 0xc91d, 0xf3ff, 0xc91d, 0x21, 0 + .dw 0xf440, 0xc91d, 0xf47f, 0xc91d, 0x21, 0 + .dw 0xf4c0, 0xc91d, 0xf4ff, 0xc91d, 0x21, 0 + .dw 0xf540, 0xc91d, 0xf57f, 0xc91d, 0x21, 0 + .dw 0xf5c0, 0xc91d, 0xf5ff, 0xc91d, 0x21, 0 + .dw 0xf640, 0xc91d, 0xf67f, 0xc91d, 0x21, 0 + .dw 0xf6c0, 0xc91d, 0xf6ff, 0xc91d, 0x21, 0 + .dw 0xf740, 0xc91d, 0xf77f, 0xc91d, 0x21, 0 + .dw 0xf7c0, 0xc91d, 0xf7ff, 0xc91d, 0x21, 0 + .dw 0xf840, 0xc91d, 0xf87f, 0xc91d, 0x21, 0 + .dw 0xf8c0, 0xc91d, 0xf8ff, 0xc91d, 0x21, 0 + .dw 0xf940, 0xc91d, 0xf97f, 0xc91d, 0x21, 0 + .dw 0xf9c0, 0xc91d, 0xffff, 0xc91d, 0x21, 0 + .dw 0x0040, 0xc91e, 0x007f, 0xc91e, 0x21, 0 + .dw 0x00c0, 0xc91e, 0x00ff, 0xc91e, 0x21, 0 + .dw 0x0140, 0xc91e, 0x017f, 0xc91e, 0x21, 0 + .dw 0x01c0, 0xc91e, 0x01ff, 0xc91e, 0x21, 0 + .dw 0x0240, 0xc91e, 0x027f, 0xc91e, 0x21, 0 + .dw 0x02c0, 0xc91e, 0x02ff, 0xc91e, 0x21, 0 + .dw 0x0340, 0xc91e, 0x037f, 0xc91e, 0x21, 0 + .dw 0x03c0, 0xc91e, 0x03ff, 0xc91e, 0x21, 0 + .dw 0x0440, 0xc91e, 0x047f, 0xc91e, 0x21, 0 + .dw 0x04c0, 0xc91e, 0x04ff, 0xc91e, 0x21, 0 + .dw 0x0540, 0xc91e, 0x057f, 0xc91e, 0x21, 0 + .dw 0x05c0, 0xc91e, 0x05ff, 0xc91e, 0x21, 0 + .dw 0x0640, 0xc91e, 0x067f, 0xc91e, 0x21, 0 + .dw 0x06c0, 0xc91e, 0x06ff, 0xc91e, 0x21, 0 + .dw 0x0740, 0xc91e, 0x077f, 0xc91e, 0x21, 0 + .dw 0x07c0, 0xc91e, 0x07ff, 0xc91e, 0x21, 0 + .dw 0x0840, 0xc91e, 0x087f, 0xc91e, 0x21, 0 + .dw 0x08c0, 0xc91e, 0x08ff, 0xc91e, 0x21, 0 + .dw 0x0940, 0xc91e, 0x097f, 0xc91e, 0x21, 0 + .dw 0x09c0, 0xc91e, 0x09ff, 0xc91e, 0x21, 0 + .dw 0x0a40, 0xc91e, 0x0a7f, 0xc91e, 0x21, 0 + .dw 0x0ac0, 0xc91e, 0x0aff, 0xc91e, 0x21, 0 + .dw 0x0b40, 0xc91e, 0x0b7f, 0xc91e, 0x21, 0 + .dw 0x0bc0, 0xc91e, 0x0bff, 0xc91e, 0x21, 0 + .dw 0x0c40, 0xc91e, 0x0c7f, 0xc91e, 0x21, 0 + .dw 0x0cc0, 0xc91e, 0x0cff, 0xc91e, 0x21, 0 + .dw 0x0d40, 0xc91e, 0x0d7f, 0xc91e, 0x21, 0 + .dw 0x0dc0, 0xc91e, 0x0dff, 0xc91e, 0x21, 0 + .dw 0x0e40, 0xc91e, 0x0e7f, 0xc91e, 0x21, 0 + .dw 0x0ec0, 0xc91e, 0x0eff, 0xc91e, 0x21, 0 + .dw 0x0f40, 0xc91e, 0x0f7f, 0xc91e, 0x21, 0 + .dw 0x0fc0, 0xc91e, 0x0fff, 0xc91e, 0x21, 0 + .dw 0x1040, 0xc91e, 0x107f, 0xc91e, 0x21, 0 + .dw 0x10c0, 0xc91e, 0x10ff, 0xc91e, 0x21, 0 + .dw 0x1140, 0xc91e, 0x117f, 0xc91e, 0x21, 0 + .dw 0x11c0, 0xc91e, 0x11ff, 0xc91e, 0x21, 0 + .dw 0x1240, 0xc91e, 0x127f, 0xc91e, 0x21, 0 + .dw 0x12c0, 0xc91e, 0x12ff, 0xc91e, 0x21, 0 + .dw 0x1340, 0xc91e, 0x137f, 0xc91e, 0x21, 0 + .dw 0x13c0, 0xc91e, 0x13ff, 0xc91e, 0x21, 0 + .dw 0x1440, 0xc91e, 0x147f, 0xc91e, 0x21, 0 + .dw 0x14c0, 0xc91e, 0x14ff, 0xc91e, 0x21, 0 + .dw 0x1540, 0xc91e, 0x157f, 0xc91e, 0x21, 0 + .dw 0x15c0, 0xc91e, 0x15ff, 0xc91e, 0x21, 0 + .dw 0x1640, 0xc91e, 0x167f, 0xc91e, 0x21, 0 + .dw 0x16c0, 0xc91e, 0x16ff, 0xc91e, 0x21, 0 + .dw 0x1740, 0xc91e, 0x177f, 0xc91e, 0x21, 0 + .dw 0x17c0, 0xc91e, 0x17ff, 0xc91e, 0x21, 0 + .dw 0x1840, 0xc91e, 0x187f, 0xc91e, 0x21, 0 + .dw 0x18c0, 0xc91e, 0x18ff, 0xc91e, 0x21, 0 + .dw 0x1940, 0xc91e, 0x197f, 0xc91e, 0x21, 0 + .dw 0x19c0, 0xc91e, 0x1fff, 0xc91e, 0x21, 0 + .dw 0x2040, 0xc91e, 0x207f, 0xc91e, 0x21, 0 + .dw 0x20c0, 0xc91e, 0x20ff, 0xc91e, 0x21, 0 + .dw 0x2140, 0xc91e, 0x217f, 0xc91e, 0x21, 0 + .dw 0x21c0, 0xc91e, 0x21ff, 0xc91e, 0x21, 0 + .dw 0x2240, 0xc91e, 0x227f, 0xc91e, 0x21, 0 + .dw 0x22c0, 0xc91e, 0x22ff, 0xc91e, 0x21, 0 + .dw 0x2340, 0xc91e, 0x237f, 0xc91e, 0x21, 0 + .dw 0x23c0, 0xc91e, 0x23ff, 0xc91e, 0x21, 0 + .dw 0x2440, 0xc91e, 0x247f, 0xc91e, 0x21, 0 + .dw 0x24c0, 0xc91e, 0x24ff, 0xc91e, 0x21, 0 + .dw 0x2540, 0xc91e, 0x257f, 0xc91e, 0x21, 0 + .dw 0x25c0, 0xc91e, 0x25ff, 0xc91e, 0x21, 0 + .dw 0x2640, 0xc91e, 0x267f, 0xc91e, 0x21, 0 + .dw 0x26c0, 0xc91e, 0x26ff, 0xc91e, 0x21, 0 + .dw 0x2740, 0xc91e, 0x277f, 0xc91e, 0x21, 0 + .dw 0x27c0, 0xc91e, 0x27ff, 0xc91e, 0x21, 0 + .dw 0x2840, 0xc91e, 0x287f, 0xc91e, 0x21, 0 + .dw 0x28c0, 0xc91e, 0x28ff, 0xc91e, 0x21, 0 + .dw 0x2940, 0xc91e, 0x297f, 0xc91e, 0x21, 0 + .dw 0x29c0, 0xc91e, 0x29ff, 0xc91e, 0x21, 0 + .dw 0x2a40, 0xc91e, 0x2a7f, 0xc91e, 0x21, 0 + .dw 0x2ac0, 0xc91e, 0x2aff, 0xc91e, 0x21, 0 + .dw 0x2b40, 0xc91e, 0x2b7f, 0xc91e, 0x21, 0 + .dw 0x2bc0, 0xc91e, 0x2bff, 0xc91e, 0x21, 0 + .dw 0x2c40, 0xc91e, 0x2c7f, 0xc91e, 0x21, 0 + .dw 0x2cc0, 0xc91e, 0x2cff, 0xc91e, 0x21, 0 + .dw 0x2d40, 0xc91e, 0x2d7f, 0xc91e, 0x21, 0 + .dw 0x2dc0, 0xc91e, 0x2dff, 0xc91e, 0x21, 0 + .dw 0x2e40, 0xc91e, 0x2e7f, 0xc91e, 0x21, 0 + .dw 0x2ec0, 0xc91e, 0x2eff, 0xc91e, 0x21, 0 + .dw 0x2f40, 0xc91e, 0x2f7f, 0xc91e, 0x21, 0 + .dw 0x2fc0, 0xc91e, 0x2fff, 0xc91e, 0x21, 0 + .dw 0x3040, 0xc91e, 0x307f, 0xc91e, 0x21, 0 + .dw 0x30c0, 0xc91e, 0x30ff, 0xc91e, 0x21, 0 + .dw 0x3140, 0xc91e, 0x317f, 0xc91e, 0x21, 0 + .dw 0x31c0, 0xc91e, 0x31ff, 0xc91e, 0x21, 0 + .dw 0x3240, 0xc91e, 0x327f, 0xc91e, 0x21, 0 + .dw 0x32c0, 0xc91e, 0x32ff, 0xc91e, 0x21, 0 + .dw 0x3340, 0xc91e, 0x337f, 0xc91e, 0x21, 0 + .dw 0x33c0, 0xc91e, 0x33ff, 0xc91e, 0x21, 0 + .dw 0x3440, 0xc91e, 0x347f, 0xc91e, 0x21, 0 + .dw 0x34c0, 0xc91e, 0x34ff, 0xc91e, 0x21, 0 + .dw 0x3540, 0xc91e, 0x357f, 0xc91e, 0x21, 0 + .dw 0x35c0, 0xc91e, 0x35ff, 0xc91e, 0x21, 0 + .dw 0x3640, 0xc91e, 0x367f, 0xc91e, 0x21, 0 + .dw 0x36c0, 0xc91e, 0x36ff, 0xc91e, 0x21, 0 + .dw 0x3740, 0xc91e, 0x377f, 0xc91e, 0x21, 0 + .dw 0x37c0, 0xc91e, 0x37ff, 0xc91e, 0x21, 0 + .dw 0x3840, 0xc91e, 0x387f, 0xc91e, 0x21, 0 + .dw 0x38c0, 0xc91e, 0x38ff, 0xc91e, 0x21, 0 + .dw 0x3940, 0xc91e, 0x397f, 0xc91e, 0x21, 0 + .dw 0x39c0, 0xc91e, 0x3fff, 0xc91e, 0x21, 0 + .dw 0x4040, 0xc91e, 0x407f, 0xc91e, 0x21, 0 + .dw 0x40c0, 0xc91e, 0x40ff, 0xc91e, 0x21, 0 + .dw 0x4140, 0xc91e, 0x417f, 0xc91e, 0x21, 0 + .dw 0x41c0, 0xc91e, 0x41ff, 0xc91e, 0x21, 0 + .dw 0x4240, 0xc91e, 0x427f, 0xc91e, 0x21, 0 + .dw 0x42c0, 0xc91e, 0x42ff, 0xc91e, 0x21, 0 + .dw 0x4340, 0xc91e, 0x437f, 0xc91e, 0x21, 0 + .dw 0x43c0, 0xc91e, 0x43ff, 0xc91e, 0x21, 0 + .dw 0x4440, 0xc91e, 0x447f, 0xc91e, 0x21, 0 + .dw 0x44c0, 0xc91e, 0x44ff, 0xc91e, 0x21, 0 + .dw 0x4540, 0xc91e, 0x457f, 0xc91e, 0x21, 0 + .dw 0x45c0, 0xc91e, 0x45ff, 0xc91e, 0x21, 0 + .dw 0x4640, 0xc91e, 0x467f, 0xc91e, 0x21, 0 + .dw 0x46c0, 0xc91e, 0x46ff, 0xc91e, 0x21, 0 + .dw 0x4740, 0xc91e, 0x477f, 0xc91e, 0x21, 0 + .dw 0x47c0, 0xc91e, 0x47ff, 0xc91e, 0x21, 0 + .dw 0x4840, 0xc91e, 0x487f, 0xc91e, 0x21, 0 + .dw 0x48c0, 0xc91e, 0x48ff, 0xc91e, 0x21, 0 + .dw 0x4940, 0xc91e, 0x497f, 0xc91e, 0x21, 0 + .dw 0x49c0, 0xc91e, 0x49ff, 0xc91e, 0x21, 0 + .dw 0x4a40, 0xc91e, 0x4a7f, 0xc91e, 0x21, 0 + .dw 0x4ac0, 0xc91e, 0x4aff, 0xc91e, 0x21, 0 + .dw 0x4b40, 0xc91e, 0x4b7f, 0xc91e, 0x21, 0 + .dw 0x4bc0, 0xc91e, 0x4bff, 0xc91e, 0x21, 0 + .dw 0x4c40, 0xc91e, 0x4c7f, 0xc91e, 0x21, 0 + .dw 0x4cc0, 0xc91e, 0x4cff, 0xc91e, 0x21, 0 + .dw 0x4d40, 0xc91e, 0x4d7f, 0xc91e, 0x21, 0 + .dw 0x4dc0, 0xc91e, 0x4dff, 0xc91e, 0x21, 0 + .dw 0x4e40, 0xc91e, 0x4e7f, 0xc91e, 0x21, 0 + .dw 0x4ec0, 0xc91e, 0x4eff, 0xc91e, 0x21, 0 + .dw 0x4f40, 0xc91e, 0x4f7f, 0xc91e, 0x21, 0 + .dw 0x4fc0, 0xc91e, 0x4fff, 0xc91e, 0x21, 0 + .dw 0x5040, 0xc91e, 0x507f, 0xc91e, 0x21, 0 + .dw 0x50c0, 0xc91e, 0x50ff, 0xc91e, 0x21, 0 + .dw 0x5140, 0xc91e, 0x517f, 0xc91e, 0x21, 0 + .dw 0x51c0, 0xc91e, 0x51ff, 0xc91e, 0x21, 0 + .dw 0x5240, 0xc91e, 0x527f, 0xc91e, 0x21, 0 + .dw 0x52c0, 0xc91e, 0x52ff, 0xc91e, 0x21, 0 + .dw 0x5340, 0xc91e, 0x537f, 0xc91e, 0x21, 0 + .dw 0x53c0, 0xc91e, 0x53ff, 0xc91e, 0x21, 0 + .dw 0x5440, 0xc91e, 0x547f, 0xc91e, 0x21, 0 + .dw 0x54c0, 0xc91e, 0x54ff, 0xc91e, 0x21, 0 + .dw 0x5540, 0xc91e, 0x557f, 0xc91e, 0x21, 0 + .dw 0x55c0, 0xc91e, 0x55ff, 0xc91e, 0x21, 0 + .dw 0x5640, 0xc91e, 0x567f, 0xc91e, 0x21, 0 + .dw 0x56c0, 0xc91e, 0x56ff, 0xc91e, 0x21, 0 + .dw 0x5740, 0xc91e, 0x577f, 0xc91e, 0x21, 0 + .dw 0x57c0, 0xc91e, 0x57ff, 0xc91e, 0x21, 0 + .dw 0x5840, 0xc91e, 0x587f, 0xc91e, 0x21, 0 + .dw 0x58c0, 0xc91e, 0x58ff, 0xc91e, 0x21, 0 + .dw 0x5940, 0xc91e, 0x597f, 0xc91e, 0x21, 0 + .dw 0x59c0, 0xc91e, 0x5fff, 0xc91e, 0x21, 0 + .dw 0x6040, 0xc91e, 0x607f, 0xc91e, 0x21, 0 + .dw 0x60c0, 0xc91e, 0x60ff, 0xc91e, 0x21, 0 + .dw 0x6140, 0xc91e, 0x617f, 0xc91e, 0x21, 0 + .dw 0x61c0, 0xc91e, 0x61ff, 0xc91e, 0x21, 0 + .dw 0x6240, 0xc91e, 0x627f, 0xc91e, 0x21, 0 + .dw 0x62c0, 0xc91e, 0x62ff, 0xc91e, 0x21, 0 + .dw 0x6340, 0xc91e, 0x637f, 0xc91e, 0x21, 0 + .dw 0x63c0, 0xc91e, 0x63ff, 0xc91e, 0x21, 0 + .dw 0x6440, 0xc91e, 0x647f, 0xc91e, 0x21, 0 + .dw 0x64c0, 0xc91e, 0x64ff, 0xc91e, 0x21, 0 + .dw 0x6540, 0xc91e, 0x657f, 0xc91e, 0x21, 0 + .dw 0x65c0, 0xc91e, 0x65ff, 0xc91e, 0x21, 0 + .dw 0x6640, 0xc91e, 0x667f, 0xc91e, 0x21, 0 + .dw 0x66c0, 0xc91e, 0x66ff, 0xc91e, 0x21, 0 + .dw 0x6740, 0xc91e, 0x677f, 0xc91e, 0x21, 0 + .dw 0x67c0, 0xc91e, 0x67ff, 0xc91e, 0x21, 0 + .dw 0x6840, 0xc91e, 0x687f, 0xc91e, 0x21, 0 + .dw 0x68c0, 0xc91e, 0x68ff, 0xc91e, 0x21, 0 + .dw 0x6940, 0xc91e, 0x697f, 0xc91e, 0x21, 0 + .dw 0x69c0, 0xc91e, 0x69ff, 0xc91e, 0x21, 0 + .dw 0x6a40, 0xc91e, 0x6a7f, 0xc91e, 0x21, 0 + .dw 0x6ac0, 0xc91e, 0x6aff, 0xc91e, 0x21, 0 + .dw 0x6b40, 0xc91e, 0x6b7f, 0xc91e, 0x21, 0 + .dw 0x6bc0, 0xc91e, 0x6bff, 0xc91e, 0x21, 0 + .dw 0x6c40, 0xc91e, 0x6c7f, 0xc91e, 0x21, 0 + .dw 0x6cc0, 0xc91e, 0x6cff, 0xc91e, 0x21, 0 + .dw 0x6d40, 0xc91e, 0x6d7f, 0xc91e, 0x21, 0 + .dw 0x6dc0, 0xc91e, 0x6dff, 0xc91e, 0x21, 0 + .dw 0x6e40, 0xc91e, 0x6e7f, 0xc91e, 0x21, 0 + .dw 0x6ec0, 0xc91e, 0x6eff, 0xc91e, 0x21, 0 + .dw 0x6f40, 0xc91e, 0x6f7f, 0xc91e, 0x21, 0 + .dw 0x6fc0, 0xc91e, 0x6fff, 0xc91e, 0x21, 0 + .dw 0x7040, 0xc91e, 0x707f, 0xc91e, 0x21, 0 + .dw 0x70c0, 0xc91e, 0x70ff, 0xc91e, 0x21, 0 + .dw 0x7140, 0xc91e, 0x717f, 0xc91e, 0x21, 0 + .dw 0x71c0, 0xc91e, 0x71ff, 0xc91e, 0x21, 0 + .dw 0x7240, 0xc91e, 0x727f, 0xc91e, 0x21, 0 + .dw 0x72c0, 0xc91e, 0x72ff, 0xc91e, 0x21, 0 + .dw 0x7340, 0xc91e, 0x737f, 0xc91e, 0x21, 0 + .dw 0x73c0, 0xc91e, 0x73ff, 0xc91e, 0x21, 0 + .dw 0x7440, 0xc91e, 0x747f, 0xc91e, 0x21, 0 + .dw 0x74c0, 0xc91e, 0x74ff, 0xc91e, 0x21, 0 + .dw 0x7540, 0xc91e, 0x757f, 0xc91e, 0x21, 0 + .dw 0x75c0, 0xc91e, 0x75ff, 0xc91e, 0x21, 0 + .dw 0x7640, 0xc91e, 0x767f, 0xc91e, 0x21, 0 + .dw 0x76c0, 0xc91e, 0x76ff, 0xc91e, 0x21, 0 + .dw 0x7740, 0xc91e, 0x777f, 0xc91e, 0x21, 0 + .dw 0x77c0, 0xc91e, 0x77ff, 0xc91e, 0x21, 0 + .dw 0x7840, 0xc91e, 0x787f, 0xc91e, 0x21, 0 + .dw 0x78c0, 0xc91e, 0x78ff, 0xc91e, 0x21, 0 + .dw 0x7940, 0xc91e, 0x797f, 0xc91e, 0x21, 0 + .dw 0x79c0, 0xc91e, 0x7fff, 0xc91e, 0x21, 0 + .dw 0x8040, 0xc91e, 0x807f, 0xc91e, 0x21, 0 + .dw 0x80c0, 0xc91e, 0x80ff, 0xc91e, 0x21, 0 + .dw 0x8140, 0xc91e, 0x817f, 0xc91e, 0x21, 0 + .dw 0x81c0, 0xc91e, 0x81ff, 0xc91e, 0x21, 0 + .dw 0x8240, 0xc91e, 0x827f, 0xc91e, 0x21, 0 + .dw 0x82c0, 0xc91e, 0x82ff, 0xc91e, 0x21, 0 + .dw 0x8340, 0xc91e, 0x837f, 0xc91e, 0x21, 0 + .dw 0x83c0, 0xc91e, 0x83ff, 0xc91e, 0x21, 0 + .dw 0x8440, 0xc91e, 0x847f, 0xc91e, 0x21, 0 + .dw 0x84c0, 0xc91e, 0x84ff, 0xc91e, 0x21, 0 + .dw 0x8540, 0xc91e, 0x857f, 0xc91e, 0x21, 0 + .dw 0x85c0, 0xc91e, 0x85ff, 0xc91e, 0x21, 0 + .dw 0x8640, 0xc91e, 0x867f, 0xc91e, 0x21, 0 + .dw 0x86c0, 0xc91e, 0x86ff, 0xc91e, 0x21, 0 + .dw 0x8740, 0xc91e, 0x877f, 0xc91e, 0x21, 0 + .dw 0x87c0, 0xc91e, 0x87ff, 0xc91e, 0x21, 0 + .dw 0x8840, 0xc91e, 0x887f, 0xc91e, 0x21, 0 + .dw 0x88c0, 0xc91e, 0x88ff, 0xc91e, 0x21, 0 + .dw 0x8940, 0xc91e, 0x897f, 0xc91e, 0x21, 0 + .dw 0x89c0, 0xc91e, 0x89ff, 0xc91e, 0x21, 0 + .dw 0x8a40, 0xc91e, 0x8a7f, 0xc91e, 0x21, 0 + .dw 0x8ac0, 0xc91e, 0x8aff, 0xc91e, 0x21, 0 + .dw 0x8b40, 0xc91e, 0x8b7f, 0xc91e, 0x21, 0 + .dw 0x8bc0, 0xc91e, 0x8bff, 0xc91e, 0x21, 0 + .dw 0x8c40, 0xc91e, 0x8c7f, 0xc91e, 0x21, 0 + .dw 0x8cc0, 0xc91e, 0x8cff, 0xc91e, 0x21, 0 + .dw 0x8d40, 0xc91e, 0x8d7f, 0xc91e, 0x21, 0 + .dw 0x8dc0, 0xc91e, 0x8dff, 0xc91e, 0x21, 0 + .dw 0x8e40, 0xc91e, 0x8e7f, 0xc91e, 0x21, 0 + .dw 0x8ec0, 0xc91e, 0x8eff, 0xc91e, 0x21, 0 + .dw 0x8f40, 0xc91e, 0x8f7f, 0xc91e, 0x21, 0 + .dw 0x8fc0, 0xc91e, 0x8fff, 0xc91e, 0x21, 0 + .dw 0x9040, 0xc91e, 0x907f, 0xc91e, 0x21, 0 + .dw 0x90c0, 0xc91e, 0x90ff, 0xc91e, 0x21, 0 + .dw 0x9140, 0xc91e, 0x917f, 0xc91e, 0x21, 0 + .dw 0x91c0, 0xc91e, 0x91ff, 0xc91e, 0x21, 0 + .dw 0x9240, 0xc91e, 0x927f, 0xc91e, 0x21, 0 + .dw 0x92c0, 0xc91e, 0x92ff, 0xc91e, 0x21, 0 + .dw 0x9340, 0xc91e, 0x937f, 0xc91e, 0x21, 0 + .dw 0x93c0, 0xc91e, 0x93ff, 0xc91e, 0x21, 0 + .dw 0x9440, 0xc91e, 0x947f, 0xc91e, 0x21, 0 + .dw 0x94c0, 0xc91e, 0x94ff, 0xc91e, 0x21, 0 + .dw 0x9540, 0xc91e, 0x957f, 0xc91e, 0x21, 0 + .dw 0x95c0, 0xc91e, 0x95ff, 0xc91e, 0x21, 0 + .dw 0x9640, 0xc91e, 0x967f, 0xc91e, 0x21, 0 + .dw 0x96c0, 0xc91e, 0x96ff, 0xc91e, 0x21, 0 + .dw 0x9740, 0xc91e, 0x977f, 0xc91e, 0x21, 0 + .dw 0x97c0, 0xc91e, 0x97ff, 0xc91e, 0x21, 0 + .dw 0x9840, 0xc91e, 0x987f, 0xc91e, 0x21, 0 + .dw 0x98c0, 0xc91e, 0x98ff, 0xc91e, 0x21, 0 + .dw 0x9940, 0xc91e, 0x997f, 0xc91e, 0x21, 0 + .dw 0x99c0, 0xc91e, 0x9fff, 0xc91e, 0x21, 0 + .dw 0xa040, 0xc91e, 0xa07f, 0xc91e, 0x21, 0 + .dw 0xa0c0, 0xc91e, 0xa0ff, 0xc91e, 0x21, 0 + .dw 0xa140, 0xc91e, 0xa17f, 0xc91e, 0x21, 0 + .dw 0xa1c0, 0xc91e, 0xa1ff, 0xc91e, 0x21, 0 + .dw 0xa240, 0xc91e, 0xa27f, 0xc91e, 0x21, 0 + .dw 0xa2c0, 0xc91e, 0xa2ff, 0xc91e, 0x21, 0 + .dw 0xa340, 0xc91e, 0xa37f, 0xc91e, 0x21, 0 + .dw 0xa3c0, 0xc91e, 0xa3ff, 0xc91e, 0x21, 0 + .dw 0xa440, 0xc91e, 0xa47f, 0xc91e, 0x21, 0 + .dw 0xa4c0, 0xc91e, 0xa4ff, 0xc91e, 0x21, 0 + .dw 0xa540, 0xc91e, 0xa57f, 0xc91e, 0x21, 0 + .dw 0xa5c0, 0xc91e, 0xa5ff, 0xc91e, 0x21, 0 + .dw 0xa640, 0xc91e, 0xa67f, 0xc91e, 0x21, 0 + .dw 0xa6c0, 0xc91e, 0xa6ff, 0xc91e, 0x21, 0 + .dw 0xa740, 0xc91e, 0xa77f, 0xc91e, 0x21, 0 + .dw 0xa7c0, 0xc91e, 0xa7ff, 0xc91e, 0x21, 0 + .dw 0xa840, 0xc91e, 0xa87f, 0xc91e, 0x21, 0 + .dw 0xa8c0, 0xc91e, 0xa8ff, 0xc91e, 0x21, 0 + .dw 0xa940, 0xc91e, 0xa97f, 0xc91e, 0x21, 0 + .dw 0xa9c0, 0xc91e, 0xa9ff, 0xc91e, 0x21, 0 + .dw 0xaa40, 0xc91e, 0xaa7f, 0xc91e, 0x21, 0 + .dw 0xaac0, 0xc91e, 0xaaff, 0xc91e, 0x21, 0 + .dw 0xab40, 0xc91e, 0xab7f, 0xc91e, 0x21, 0 + .dw 0xabc0, 0xc91e, 0xabff, 0xc91e, 0x21, 0 + .dw 0xac40, 0xc91e, 0xac7f, 0xc91e, 0x21, 0 + .dw 0xacc0, 0xc91e, 0xacff, 0xc91e, 0x21, 0 + .dw 0xad40, 0xc91e, 0xad7f, 0xc91e, 0x21, 0 + .dw 0xadc0, 0xc91e, 0xadff, 0xc91e, 0x21, 0 + .dw 0xae40, 0xc91e, 0xae7f, 0xc91e, 0x21, 0 + .dw 0xaec0, 0xc91e, 0xaeff, 0xc91e, 0x21, 0 + .dw 0xaf40, 0xc91e, 0xaf7f, 0xc91e, 0x21, 0 + .dw 0xafc0, 0xc91e, 0xafff, 0xc91e, 0x21, 0 + .dw 0xb040, 0xc91e, 0xb07f, 0xc91e, 0x21, 0 + .dw 0xb0c0, 0xc91e, 0xb0ff, 0xc91e, 0x21, 0 + .dw 0xb140, 0xc91e, 0xb17f, 0xc91e, 0x21, 0 + .dw 0xb1c0, 0xc91e, 0xb1ff, 0xc91e, 0x21, 0 + .dw 0xb240, 0xc91e, 0xb27f, 0xc91e, 0x21, 0 + .dw 0xb2c0, 0xc91e, 0xb2ff, 0xc91e, 0x21, 0 + .dw 0xb340, 0xc91e, 0xb37f, 0xc91e, 0x21, 0 + .dw 0xb3c0, 0xc91e, 0xb3ff, 0xc91e, 0x21, 0 + .dw 0xb440, 0xc91e, 0xb47f, 0xc91e, 0x21, 0 + .dw 0xb4c0, 0xc91e, 0xb4ff, 0xc91e, 0x21, 0 + .dw 0xb540, 0xc91e, 0xb57f, 0xc91e, 0x21, 0 + .dw 0xb5c0, 0xc91e, 0xb5ff, 0xc91e, 0x21, 0 + .dw 0xb640, 0xc91e, 0xb67f, 0xc91e, 0x21, 0 + .dw 0xb6c0, 0xc91e, 0xb6ff, 0xc91e, 0x21, 0 + .dw 0xb740, 0xc91e, 0xb77f, 0xc91e, 0x21, 0 + .dw 0xb7c0, 0xc91e, 0xb7ff, 0xc91e, 0x21, 0 + .dw 0xb840, 0xc91e, 0xb87f, 0xc91e, 0x21, 0 + .dw 0xb8c0, 0xc91e, 0xb8ff, 0xc91e, 0x21, 0 + .dw 0xb940, 0xc91e, 0xb97f, 0xc91e, 0x21, 0 + .dw 0xb9c0, 0xc91e, 0xbfff, 0xc91e, 0x21, 0 + .dw 0xc040, 0xc91e, 0xc07f, 0xc91e, 0x21, 0 + .dw 0xc0c0, 0xc91e, 0xc0ff, 0xc91e, 0x21, 0 + .dw 0xc140, 0xc91e, 0xc17f, 0xc91e, 0x21, 0 + .dw 0xc1c0, 0xc91e, 0xc1ff, 0xc91e, 0x21, 0 + .dw 0xc240, 0xc91e, 0xc27f, 0xc91e, 0x21, 0 + .dw 0xc2c0, 0xc91e, 0xc2ff, 0xc91e, 0x21, 0 + .dw 0xc340, 0xc91e, 0xc37f, 0xc91e, 0x21, 0 + .dw 0xc3c0, 0xc91e, 0xc3ff, 0xc91e, 0x21, 0 + .dw 0xc440, 0xc91e, 0xc47f, 0xc91e, 0x21, 0 + .dw 0xc4c0, 0xc91e, 0xc4ff, 0xc91e, 0x21, 0 + .dw 0xc540, 0xc91e, 0xc57f, 0xc91e, 0x21, 0 + .dw 0xc5c0, 0xc91e, 0xc5ff, 0xc91e, 0x21, 0 + .dw 0xc640, 0xc91e, 0xc67f, 0xc91e, 0x21, 0 + .dw 0xc6c0, 0xc91e, 0xc6ff, 0xc91e, 0x21, 0 + .dw 0xc740, 0xc91e, 0xc77f, 0xc91e, 0x21, 0 + .dw 0xc7c0, 0xc91e, 0xc7ff, 0xc91e, 0x21, 0 + .dw 0xc840, 0xc91e, 0xc87f, 0xc91e, 0x21, 0 + .dw 0xc8c0, 0xc91e, 0xc8ff, 0xc91e, 0x21, 0 + .dw 0xc940, 0xc91e, 0xc97f, 0xc91e, 0x21, 0 + .dw 0xc9c0, 0xc91e, 0xc9ff, 0xc91e, 0x21, 0 + .dw 0xca40, 0xc91e, 0xca7f, 0xc91e, 0x21, 0 + .dw 0xcac0, 0xc91e, 0xcaff, 0xc91e, 0x21, 0 + .dw 0xcb40, 0xc91e, 0xcb7f, 0xc91e, 0x21, 0 + .dw 0xcbc0, 0xc91e, 0xcbff, 0xc91e, 0x21, 0 + .dw 0xcc40, 0xc91e, 0xcc7f, 0xc91e, 0x21, 0 + .dw 0xccc0, 0xc91e, 0xccff, 0xc91e, 0x21, 0 + .dw 0xcd40, 0xc91e, 0xcd7f, 0xc91e, 0x21, 0 + .dw 0xcdc0, 0xc91e, 0xcdff, 0xc91e, 0x21, 0 + .dw 0xce40, 0xc91e, 0xce7f, 0xc91e, 0x21, 0 + .dw 0xcec0, 0xc91e, 0xceff, 0xc91e, 0x21, 0 + .dw 0xcf40, 0xc91e, 0xcf7f, 0xc91e, 0x21, 0 + .dw 0xcfc0, 0xc91e, 0xcfff, 0xc91e, 0x21, 0 + .dw 0xd040, 0xc91e, 0xd07f, 0xc91e, 0x21, 0 + .dw 0xd0c0, 0xc91e, 0xd0ff, 0xc91e, 0x21, 0 + .dw 0xd140, 0xc91e, 0xd17f, 0xc91e, 0x21, 0 + .dw 0xd1c0, 0xc91e, 0xd1ff, 0xc91e, 0x21, 0 + .dw 0xd240, 0xc91e, 0xd27f, 0xc91e, 0x21, 0 + .dw 0xd2c0, 0xc91e, 0xd2ff, 0xc91e, 0x21, 0 + .dw 0xd340, 0xc91e, 0xd37f, 0xc91e, 0x21, 0 + .dw 0xd3c0, 0xc91e, 0xd3ff, 0xc91e, 0x21, 0 + .dw 0xd440, 0xc91e, 0xd47f, 0xc91e, 0x21, 0 + .dw 0xd4c0, 0xc91e, 0xd4ff, 0xc91e, 0x21, 0 + .dw 0xd540, 0xc91e, 0xd57f, 0xc91e, 0x21, 0 + .dw 0xd5c0, 0xc91e, 0xd5ff, 0xc91e, 0x21, 0 + .dw 0xd640, 0xc91e, 0xd67f, 0xc91e, 0x21, 0 + .dw 0xd6c0, 0xc91e, 0xd6ff, 0xc91e, 0x21, 0 + .dw 0xd740, 0xc91e, 0xd77f, 0xc91e, 0x21, 0 + .dw 0xd7c0, 0xc91e, 0xd7ff, 0xc91e, 0x21, 0 + .dw 0xd840, 0xc91e, 0xd87f, 0xc91e, 0x21, 0 + .dw 0xd8c0, 0xc91e, 0xd8ff, 0xc91e, 0x21, 0 + .dw 0xd940, 0xc91e, 0xd97f, 0xc91e, 0x21, 0 + .dw 0xd9c0, 0xc91e, 0xdfff, 0xc91e, 0x21, 0 + .dw 0xe040, 0xc91e, 0xe07f, 0xc91e, 0x21, 0 + .dw 0xe0c0, 0xc91e, 0xe0ff, 0xc91e, 0x21, 0 + .dw 0xe140, 0xc91e, 0xe17f, 0xc91e, 0x21, 0 + .dw 0xe1c0, 0xc91e, 0xe1ff, 0xc91e, 0x21, 0 + .dw 0xe240, 0xc91e, 0xe27f, 0xc91e, 0x21, 0 + .dw 0xe2c0, 0xc91e, 0xe2ff, 0xc91e, 0x21, 0 + .dw 0xe340, 0xc91e, 0xe37f, 0xc91e, 0x21, 0 + .dw 0xe3c0, 0xc91e, 0xe3ff, 0xc91e, 0x21, 0 + .dw 0xe440, 0xc91e, 0xe47f, 0xc91e, 0x21, 0 + .dw 0xe4c0, 0xc91e, 0xe4ff, 0xc91e, 0x21, 0 + .dw 0xe540, 0xc91e, 0xe57f, 0xc91e, 0x21, 0 + .dw 0xe5c0, 0xc91e, 0xe5ff, 0xc91e, 0x21, 0 + .dw 0xe640, 0xc91e, 0xe67f, 0xc91e, 0x21, 0 + .dw 0xe6c0, 0xc91e, 0xe6ff, 0xc91e, 0x21, 0 + .dw 0xe740, 0xc91e, 0xe77f, 0xc91e, 0x21, 0 + .dw 0xe7c0, 0xc91e, 0xe7ff, 0xc91e, 0x21, 0 + .dw 0xe840, 0xc91e, 0xe87f, 0xc91e, 0x21, 0 + .dw 0xe8c0, 0xc91e, 0xe8ff, 0xc91e, 0x21, 0 + .dw 0xe940, 0xc91e, 0xe97f, 0xc91e, 0x21, 0 + .dw 0xe9c0, 0xc91e, 0xe9ff, 0xc91e, 0x21, 0 + .dw 0xea40, 0xc91e, 0xea7f, 0xc91e, 0x21, 0 + .dw 0xeac0, 0xc91e, 0xeaff, 0xc91e, 0x21, 0 + .dw 0xeb40, 0xc91e, 0xeb7f, 0xc91e, 0x21, 0 + .dw 0xebc0, 0xc91e, 0xebff, 0xc91e, 0x21, 0 + .dw 0xec40, 0xc91e, 0xec7f, 0xc91e, 0x21, 0 + .dw 0xecc0, 0xc91e, 0xecff, 0xc91e, 0x21, 0 + .dw 0xed40, 0xc91e, 0xed7f, 0xc91e, 0x21, 0 + .dw 0xedc0, 0xc91e, 0xedff, 0xc91e, 0x21, 0 + .dw 0xee40, 0xc91e, 0xee7f, 0xc91e, 0x21, 0 + .dw 0xeec0, 0xc91e, 0xeeff, 0xc91e, 0x21, 0 + .dw 0xef40, 0xc91e, 0xef7f, 0xc91e, 0x21, 0 + .dw 0xefc0, 0xc91e, 0xefff, 0xc91e, 0x21, 0 + .dw 0xf040, 0xc91e, 0xf07f, 0xc91e, 0x21, 0 + .dw 0xf0c0, 0xc91e, 0xf0ff, 0xc91e, 0x21, 0 + .dw 0xf140, 0xc91e, 0xf17f, 0xc91e, 0x21, 0 + .dw 0xf1c0, 0xc91e, 0xf1ff, 0xc91e, 0x21, 0 + .dw 0xf240, 0xc91e, 0xf27f, 0xc91e, 0x21, 0 + .dw 0xf2c0, 0xc91e, 0xf2ff, 0xc91e, 0x21, 0 + .dw 0xf340, 0xc91e, 0xf37f, 0xc91e, 0x21, 0 + .dw 0xf3c0, 0xc91e, 0xf3ff, 0xc91e, 0x21, 0 + .dw 0xf440, 0xc91e, 0xf47f, 0xc91e, 0x21, 0 + .dw 0xf4c0, 0xc91e, 0xf4ff, 0xc91e, 0x21, 0 + .dw 0xf540, 0xc91e, 0xf57f, 0xc91e, 0x21, 0 + .dw 0xf5c0, 0xc91e, 0xf5ff, 0xc91e, 0x21, 0 + .dw 0xf640, 0xc91e, 0xf67f, 0xc91e, 0x21, 0 + .dw 0xf6c0, 0xc91e, 0xf6ff, 0xc91e, 0x21, 0 + .dw 0xf740, 0xc91e, 0xf77f, 0xc91e, 0x21, 0 + .dw 0xf7c0, 0xc91e, 0xf7ff, 0xc91e, 0x21, 0 + .dw 0xf840, 0xc91e, 0xf87f, 0xc91e, 0x21, 0 + .dw 0xf8c0, 0xc91e, 0xf8ff, 0xc91e, 0x21, 0 + .dw 0xf940, 0xc91e, 0xf97f, 0xc91e, 0x21, 0 + .dw 0xf9c0, 0xc91e, 0xffff, 0xc91e, 0x21, 0 + .dw 0x0040, 0xc91f, 0x007f, 0xc91f, 0x21, 0 + .dw 0x00c0, 0xc91f, 0x00ff, 0xc91f, 0x21, 0 + .dw 0x0140, 0xc91f, 0x017f, 0xc91f, 0x21, 0 + .dw 0x01c0, 0xc91f, 0x01ff, 0xc91f, 0x21, 0 + .dw 0x0240, 0xc91f, 0x027f, 0xc91f, 0x21, 0 + .dw 0x02c0, 0xc91f, 0x02ff, 0xc91f, 0x21, 0 + .dw 0x0340, 0xc91f, 0x037f, 0xc91f, 0x21, 0 + .dw 0x03c0, 0xc91f, 0x03ff, 0xc91f, 0x21, 0 + .dw 0x0440, 0xc91f, 0x047f, 0xc91f, 0x21, 0 + .dw 0x04c0, 0xc91f, 0x04ff, 0xc91f, 0x21, 0 + .dw 0x0540, 0xc91f, 0x057f, 0xc91f, 0x21, 0 + .dw 0x05c0, 0xc91f, 0x05ff, 0xc91f, 0x21, 0 + .dw 0x0640, 0xc91f, 0x067f, 0xc91f, 0x21, 0 + .dw 0x06c0, 0xc91f, 0x06ff, 0xc91f, 0x21, 0 + .dw 0x0740, 0xc91f, 0x077f, 0xc91f, 0x21, 0 + .dw 0x07c0, 0xc91f, 0x07ff, 0xc91f, 0x21, 0 + .dw 0x0840, 0xc91f, 0x087f, 0xc91f, 0x21, 0 + .dw 0x08c0, 0xc91f, 0x08ff, 0xc91f, 0x21, 0 + .dw 0x0940, 0xc91f, 0x097f, 0xc91f, 0x21, 0 + .dw 0x09c0, 0xc91f, 0x09ff, 0xc91f, 0x21, 0 + .dw 0x0a40, 0xc91f, 0x0a7f, 0xc91f, 0x21, 0 + .dw 0x0ac0, 0xc91f, 0x0aff, 0xc91f, 0x21, 0 + .dw 0x0b40, 0xc91f, 0x0b7f, 0xc91f, 0x21, 0 + .dw 0x0bc0, 0xc91f, 0x0bff, 0xc91f, 0x21, 0 + .dw 0x0c40, 0xc91f, 0x0c7f, 0xc91f, 0x21, 0 + .dw 0x0cc0, 0xc91f, 0x0cff, 0xc91f, 0x21, 0 + .dw 0x0d40, 0xc91f, 0x0d7f, 0xc91f, 0x21, 0 + .dw 0x0dc0, 0xc91f, 0x0dff, 0xc91f, 0x21, 0 + .dw 0x0e40, 0xc91f, 0x0e7f, 0xc91f, 0x21, 0 + .dw 0x0ec0, 0xc91f, 0x0eff, 0xc91f, 0x21, 0 + .dw 0x0f40, 0xc91f, 0x0f7f, 0xc91f, 0x21, 0 + .dw 0x0fc0, 0xc91f, 0x0fff, 0xc91f, 0x21, 0 + .dw 0x1040, 0xc91f, 0x107f, 0xc91f, 0x21, 0 + .dw 0x10c0, 0xc91f, 0x10ff, 0xc91f, 0x21, 0 + .dw 0x1140, 0xc91f, 0x117f, 0xc91f, 0x21, 0 + .dw 0x11c0, 0xc91f, 0x11ff, 0xc91f, 0x21, 0 + .dw 0x1240, 0xc91f, 0x127f, 0xc91f, 0x21, 0 + .dw 0x12c0, 0xc91f, 0x12ff, 0xc91f, 0x21, 0 + .dw 0x1340, 0xc91f, 0x137f, 0xc91f, 0x21, 0 + .dw 0x13c0, 0xc91f, 0x13ff, 0xc91f, 0x21, 0 + .dw 0x1440, 0xc91f, 0x147f, 0xc91f, 0x21, 0 + .dw 0x14c0, 0xc91f, 0x14ff, 0xc91f, 0x21, 0 + .dw 0x1540, 0xc91f, 0x157f, 0xc91f, 0x21, 0 + .dw 0x15c0, 0xc91f, 0x15ff, 0xc91f, 0x21, 0 + .dw 0x1640, 0xc91f, 0x167f, 0xc91f, 0x21, 0 + .dw 0x16c0, 0xc91f, 0x16ff, 0xc91f, 0x21, 0 + .dw 0x1740, 0xc91f, 0x177f, 0xc91f, 0x21, 0 + .dw 0x17c0, 0xc91f, 0x17ff, 0xc91f, 0x21, 0 + .dw 0x1840, 0xc91f, 0x187f, 0xc91f, 0x21, 0 + .dw 0x18c0, 0xc91f, 0x18ff, 0xc91f, 0x21, 0 + .dw 0x1940, 0xc91f, 0x197f, 0xc91f, 0x21, 0 + .dw 0x19c0, 0xc91f, 0x1fff, 0xc91f, 0x21, 0 + .dw 0x2040, 0xc91f, 0x207f, 0xc91f, 0x21, 0 + .dw 0x20c0, 0xc91f, 0x20ff, 0xc91f, 0x21, 0 + .dw 0x2140, 0xc91f, 0x217f, 0xc91f, 0x21, 0 + .dw 0x21c0, 0xc91f, 0x21ff, 0xc91f, 0x21, 0 + .dw 0x2240, 0xc91f, 0x227f, 0xc91f, 0x21, 0 + .dw 0x22c0, 0xc91f, 0x22ff, 0xc91f, 0x21, 0 + .dw 0x2340, 0xc91f, 0x237f, 0xc91f, 0x21, 0 + .dw 0x23c0, 0xc91f, 0x23ff, 0xc91f, 0x21, 0 + .dw 0x2440, 0xc91f, 0x247f, 0xc91f, 0x21, 0 + .dw 0x24c0, 0xc91f, 0x24ff, 0xc91f, 0x21, 0 + .dw 0x2540, 0xc91f, 0x257f, 0xc91f, 0x21, 0 + .dw 0x25c0, 0xc91f, 0x25ff, 0xc91f, 0x21, 0 + .dw 0x2640, 0xc91f, 0x267f, 0xc91f, 0x21, 0 + .dw 0x26c0, 0xc91f, 0x26ff, 0xc91f, 0x21, 0 + .dw 0x2740, 0xc91f, 0x277f, 0xc91f, 0x21, 0 + .dw 0x27c0, 0xc91f, 0x27ff, 0xc91f, 0x21, 0 + .dw 0x2840, 0xc91f, 0x287f, 0xc91f, 0x21, 0 + .dw 0x28c0, 0xc91f, 0x28ff, 0xc91f, 0x21, 0 + .dw 0x2940, 0xc91f, 0x297f, 0xc91f, 0x21, 0 + .dw 0x29c0, 0xc91f, 0x29ff, 0xc91f, 0x21, 0 + .dw 0x2a40, 0xc91f, 0x2a7f, 0xc91f, 0x21, 0 + .dw 0x2ac0, 0xc91f, 0x2aff, 0xc91f, 0x21, 0 + .dw 0x2b40, 0xc91f, 0x2b7f, 0xc91f, 0x21, 0 + .dw 0x2bc0, 0xc91f, 0x2bff, 0xc91f, 0x21, 0 + .dw 0x2c40, 0xc91f, 0x2c7f, 0xc91f, 0x21, 0 + .dw 0x2cc0, 0xc91f, 0x2cff, 0xc91f, 0x21, 0 + .dw 0x2d40, 0xc91f, 0x2d7f, 0xc91f, 0x21, 0 + .dw 0x2dc0, 0xc91f, 0x2dff, 0xc91f, 0x21, 0 + .dw 0x2e40, 0xc91f, 0x2e7f, 0xc91f, 0x21, 0 + .dw 0x2ec0, 0xc91f, 0x2eff, 0xc91f, 0x21, 0 + .dw 0x2f40, 0xc91f, 0x2f7f, 0xc91f, 0x21, 0 + .dw 0x2fc0, 0xc91f, 0x2fff, 0xc91f, 0x21, 0 + .dw 0x3040, 0xc91f, 0x307f, 0xc91f, 0x21, 0 + .dw 0x30c0, 0xc91f, 0x30ff, 0xc91f, 0x21, 0 + .dw 0x3140, 0xc91f, 0x317f, 0xc91f, 0x21, 0 + .dw 0x31c0, 0xc91f, 0x31ff, 0xc91f, 0x21, 0 + .dw 0x3240, 0xc91f, 0x327f, 0xc91f, 0x21, 0 + .dw 0x32c0, 0xc91f, 0x32ff, 0xc91f, 0x21, 0 + .dw 0x3340, 0xc91f, 0x337f, 0xc91f, 0x21, 0 + .dw 0x33c0, 0xc91f, 0x33ff, 0xc91f, 0x21, 0 + .dw 0x3440, 0xc91f, 0x347f, 0xc91f, 0x21, 0 + .dw 0x34c0, 0xc91f, 0x34ff, 0xc91f, 0x21, 0 + .dw 0x3540, 0xc91f, 0x357f, 0xc91f, 0x21, 0 + .dw 0x35c0, 0xc91f, 0x35ff, 0xc91f, 0x21, 0 + .dw 0x3640, 0xc91f, 0x367f, 0xc91f, 0x21, 0 + .dw 0x36c0, 0xc91f, 0x36ff, 0xc91f, 0x21, 0 + .dw 0x3740, 0xc91f, 0x377f, 0xc91f, 0x21, 0 + .dw 0x37c0, 0xc91f, 0x37ff, 0xc91f, 0x21, 0 + .dw 0x3840, 0xc91f, 0x387f, 0xc91f, 0x21, 0 + .dw 0x38c0, 0xc91f, 0x38ff, 0xc91f, 0x21, 0 + .dw 0x3940, 0xc91f, 0x397f, 0xc91f, 0x21, 0 + .dw 0x39c0, 0xc91f, 0x1fff, 0xc920, 0x21, 0 + .dw 0x3a00, 0xc920, 0x5fff, 0xc920, 0x21, 0 + .dw 0x7a00, 0xc920, 0x9fff, 0xc920, 0x21, 0 + .dw 0xba00, 0xc920, 0xdfff, 0xc920, 0x21, 0 + .dw 0xfa00, 0xc920, 0x1fff, 0xc921, 0x21, 0 + .dw 0x3a00, 0xc921, 0x5fff, 0xc921, 0x21, 0 + .dw 0x7a00, 0xc921, 0x9fff, 0xc921, 0x21, 0 + .dw 0xba00, 0xc921, 0xdfff, 0xc921, 0x21, 0 + .dw 0xfa00, 0xc921, 0x1fff, 0xc922, 0x21, 0 + .dw 0x3a00, 0xc922, 0x5fff, 0xc922, 0x21, 0 + .dw 0x7a00, 0xc922, 0x9fff, 0xc922, 0x21, 0 + .dw 0xba00, 0xc922, 0xdfff, 0xc922, 0x21, 0 + .dw 0xfa00, 0xc922, 0x1fff, 0xc923, 0x21, 0 + .dw 0x3a00, 0xc923, 0xffff, 0xc923, 0x21, 0 + .dw 0x1a00, 0xc924, 0x1fff, 0xc924, 0x21, 0 + .dw 0x3a00, 0xc924, 0x3fff, 0xc924, 0x21, 0 + .dw 0x5a00, 0xc924, 0x5fff, 0xc924, 0x21, 0 + .dw 0x7a00, 0xc924, 0x7fff, 0xc924, 0x21, 0 + .dw 0x9a00, 0xc924, 0x9fff, 0xc924, 0x21, 0 + .dw 0xba00, 0xc924, 0xbfff, 0xc924, 0x21, 0 + .dw 0xda00, 0xc924, 0xdfff, 0xc924, 0x21, 0 + .dw 0xfa00, 0xc924, 0xffff, 0xc924, 0x21, 0 + .dw 0x1a00, 0xc925, 0x1fff, 0xc925, 0x21, 0 + .dw 0x3a00, 0xc925, 0x3fff, 0xc925, 0x21, 0 + .dw 0x5a00, 0xc925, 0x5fff, 0xc925, 0x21, 0 + .dw 0x7a00, 0xc925, 0x7fff, 0xc925, 0x21, 0 + .dw 0x9a00, 0xc925, 0x9fff, 0xc925, 0x21, 0 + .dw 0xba00, 0xc925, 0xbfff, 0xc925, 0x21, 0 + .dw 0xda00, 0xc925, 0xdfff, 0xc925, 0x21, 0 + .dw 0xfa00, 0xc925, 0xffff, 0xc925, 0x21, 0 + .dw 0x1a00, 0xc926, 0x1fff, 0xc926, 0x21, 0 + .dw 0x3a00, 0xc926, 0x3fff, 0xc926, 0x21, 0 + .dw 0x5a00, 0xc926, 0x5fff, 0xc926, 0x21, 0 + .dw 0x7a00, 0xc926, 0x7fff, 0xc926, 0x21, 0 + .dw 0x9a00, 0xc926, 0x9fff, 0xc926, 0x21, 0 + .dw 0xba00, 0xc926, 0xbfff, 0xc926, 0x21, 0 + .dw 0xda00, 0xc926, 0xdfff, 0xc926, 0x21, 0 + .dw 0xfa00, 0xc926, 0xffff, 0xc926, 0x21, 0 + .dw 0x1a00, 0xc927, 0x1fff, 0xc927, 0x21, 0 + .dw 0x3a00, 0xc927, 0x1fff, 0xc928, 0x21, 0 + .dw 0x2040, 0xc928, 0x207f, 0xc928, 0x21, 0 + .dw 0x20c0, 0xc928, 0x20ff, 0xc928, 0x21, 0 + .dw 0x2140, 0xc928, 0x217f, 0xc928, 0x21, 0 + .dw 0x21c0, 0xc928, 0x21ff, 0xc928, 0x21, 0 + .dw 0x2240, 0xc928, 0x227f, 0xc928, 0x21, 0 + .dw 0x22c0, 0xc928, 0x22ff, 0xc928, 0x21, 0 + .dw 0x2340, 0xc928, 0x237f, 0xc928, 0x21, 0 + .dw 0x23c0, 0xc928, 0x23ff, 0xc928, 0x21, 0 + .dw 0x2440, 0xc928, 0x247f, 0xc928, 0x21, 0 + .dw 0x24c0, 0xc928, 0x24ff, 0xc928, 0x21, 0 + .dw 0x2540, 0xc928, 0x257f, 0xc928, 0x21, 0 + .dw 0x25c0, 0xc928, 0x25ff, 0xc928, 0x21, 0 + .dw 0x2640, 0xc928, 0x267f, 0xc928, 0x21, 0 + .dw 0x26c0, 0xc928, 0x26ff, 0xc928, 0x21, 0 + .dw 0x2740, 0xc928, 0x277f, 0xc928, 0x21, 0 + .dw 0x27c0, 0xc928, 0x27ff, 0xc928, 0x21, 0 + .dw 0x2840, 0xc928, 0x287f, 0xc928, 0x21, 0 + .dw 0x28c0, 0xc928, 0x28ff, 0xc928, 0x21, 0 + .dw 0x2940, 0xc928, 0x297f, 0xc928, 0x21, 0 + .dw 0x29c0, 0xc928, 0x29ff, 0xc928, 0x21, 0 + .dw 0x2a40, 0xc928, 0x2a7f, 0xc928, 0x21, 0 + .dw 0x2ac0, 0xc928, 0x2aff, 0xc928, 0x21, 0 + .dw 0x2b40, 0xc928, 0x2b7f, 0xc928, 0x21, 0 + .dw 0x2bc0, 0xc928, 0x2bff, 0xc928, 0x21, 0 + .dw 0x2c40, 0xc928, 0x2c7f, 0xc928, 0x21, 0 + .dw 0x2cc0, 0xc928, 0x2cff, 0xc928, 0x21, 0 + .dw 0x2d40, 0xc928, 0x2d7f, 0xc928, 0x21, 0 + .dw 0x2dc0, 0xc928, 0x2dff, 0xc928, 0x21, 0 + .dw 0x2e40, 0xc928, 0x2e7f, 0xc928, 0x21, 0 + .dw 0x2ec0, 0xc928, 0x2eff, 0xc928, 0x21, 0 + .dw 0x2f40, 0xc928, 0x2f7f, 0xc928, 0x21, 0 + .dw 0x2fc0, 0xc928, 0x2fff, 0xc928, 0x21, 0 + .dw 0x3040, 0xc928, 0x307f, 0xc928, 0x21, 0 + .dw 0x30c0, 0xc928, 0x30ff, 0xc928, 0x21, 0 + .dw 0x3140, 0xc928, 0x317f, 0xc928, 0x21, 0 + .dw 0x31c0, 0xc928, 0x31ff, 0xc928, 0x21, 0 + .dw 0x3240, 0xc928, 0x327f, 0xc928, 0x21, 0 + .dw 0x32c0, 0xc928, 0x32ff, 0xc928, 0x21, 0 + .dw 0x3340, 0xc928, 0x337f, 0xc928, 0x21, 0 + .dw 0x33c0, 0xc928, 0x33ff, 0xc928, 0x21, 0 + .dw 0x3440, 0xc928, 0x347f, 0xc928, 0x21, 0 + .dw 0x34c0, 0xc928, 0x34ff, 0xc928, 0x21, 0 + .dw 0x3540, 0xc928, 0x357f, 0xc928, 0x21, 0 + .dw 0x35c0, 0xc928, 0x35ff, 0xc928, 0x21, 0 + .dw 0x3640, 0xc928, 0x367f, 0xc928, 0x21, 0 + .dw 0x36c0, 0xc928, 0x36ff, 0xc928, 0x21, 0 + .dw 0x3740, 0xc928, 0x377f, 0xc928, 0x21, 0 + .dw 0x37c0, 0xc928, 0x37ff, 0xc928, 0x21, 0 + .dw 0x3840, 0xc928, 0x387f, 0xc928, 0x21, 0 + .dw 0x38c0, 0xc928, 0x38ff, 0xc928, 0x21, 0 + .dw 0x3940, 0xc928, 0x397f, 0xc928, 0x21, 0 + .dw 0x39c0, 0xc928, 0x5fff, 0xc928, 0x21, 0 + .dw 0x6040, 0xc928, 0x607f, 0xc928, 0x21, 0 + .dw 0x60c0, 0xc928, 0x60ff, 0xc928, 0x21, 0 + .dw 0x6140, 0xc928, 0x617f, 0xc928, 0x21, 0 + .dw 0x61c0, 0xc928, 0x61ff, 0xc928, 0x21, 0 + .dw 0x6240, 0xc928, 0x627f, 0xc928, 0x21, 0 + .dw 0x62c0, 0xc928, 0x62ff, 0xc928, 0x21, 0 + .dw 0x6340, 0xc928, 0x637f, 0xc928, 0x21, 0 + .dw 0x63c0, 0xc928, 0x63ff, 0xc928, 0x21, 0 + .dw 0x6440, 0xc928, 0x647f, 0xc928, 0x21, 0 + .dw 0x64c0, 0xc928, 0x64ff, 0xc928, 0x21, 0 + .dw 0x6540, 0xc928, 0x657f, 0xc928, 0x21, 0 + .dw 0x65c0, 0xc928, 0x65ff, 0xc928, 0x21, 0 + .dw 0x6640, 0xc928, 0x667f, 0xc928, 0x21, 0 + .dw 0x66c0, 0xc928, 0x66ff, 0xc928, 0x21, 0 + .dw 0x6740, 0xc928, 0x677f, 0xc928, 0x21, 0 + .dw 0x67c0, 0xc928, 0x67ff, 0xc928, 0x21, 0 + .dw 0x6840, 0xc928, 0x687f, 0xc928, 0x21, 0 + .dw 0x68c0, 0xc928, 0x68ff, 0xc928, 0x21, 0 + .dw 0x6940, 0xc928, 0x697f, 0xc928, 0x21, 0 + .dw 0x69c0, 0xc928, 0x69ff, 0xc928, 0x21, 0 + .dw 0x6a40, 0xc928, 0x6a7f, 0xc928, 0x21, 0 + .dw 0x6ac0, 0xc928, 0x6aff, 0xc928, 0x21, 0 + .dw 0x6b40, 0xc928, 0x6b7f, 0xc928, 0x21, 0 + .dw 0x6bc0, 0xc928, 0x6bff, 0xc928, 0x21, 0 + .dw 0x6c40, 0xc928, 0x6c7f, 0xc928, 0x21, 0 + .dw 0x6cc0, 0xc928, 0x6cff, 0xc928, 0x21, 0 + .dw 0x6d40, 0xc928, 0x6d7f, 0xc928, 0x21, 0 + .dw 0x6dc0, 0xc928, 0x6dff, 0xc928, 0x21, 0 + .dw 0x6e40, 0xc928, 0x6e7f, 0xc928, 0x21, 0 + .dw 0x6ec0, 0xc928, 0x6eff, 0xc928, 0x21, 0 + .dw 0x6f40, 0xc928, 0x6f7f, 0xc928, 0x21, 0 + .dw 0x6fc0, 0xc928, 0x6fff, 0xc928, 0x21, 0 + .dw 0x7040, 0xc928, 0x707f, 0xc928, 0x21, 0 + .dw 0x70c0, 0xc928, 0x70ff, 0xc928, 0x21, 0 + .dw 0x7140, 0xc928, 0x717f, 0xc928, 0x21, 0 + .dw 0x71c0, 0xc928, 0x71ff, 0xc928, 0x21, 0 + .dw 0x7240, 0xc928, 0x727f, 0xc928, 0x21, 0 + .dw 0x72c0, 0xc928, 0x72ff, 0xc928, 0x21, 0 + .dw 0x7340, 0xc928, 0x737f, 0xc928, 0x21, 0 + .dw 0x73c0, 0xc928, 0x73ff, 0xc928, 0x21, 0 + .dw 0x7440, 0xc928, 0x747f, 0xc928, 0x21, 0 + .dw 0x74c0, 0xc928, 0x74ff, 0xc928, 0x21, 0 + .dw 0x7540, 0xc928, 0x757f, 0xc928, 0x21, 0 + .dw 0x75c0, 0xc928, 0x75ff, 0xc928, 0x21, 0 + .dw 0x7640, 0xc928, 0x767f, 0xc928, 0x21, 0 + .dw 0x76c0, 0xc928, 0x76ff, 0xc928, 0x21, 0 + .dw 0x7740, 0xc928, 0x777f, 0xc928, 0x21, 0 + .dw 0x77c0, 0xc928, 0x77ff, 0xc928, 0x21, 0 + .dw 0x7840, 0xc928, 0x787f, 0xc928, 0x21, 0 + .dw 0x78c0, 0xc928, 0x78ff, 0xc928, 0x21, 0 + .dw 0x7940, 0xc928, 0x797f, 0xc928, 0x21, 0 + .dw 0x79c0, 0xc928, 0x9fff, 0xc928, 0x21, 0 + .dw 0xa040, 0xc928, 0xa07f, 0xc928, 0x21, 0 + .dw 0xa0c0, 0xc928, 0xa0ff, 0xc928, 0x21, 0 + .dw 0xa140, 0xc928, 0xa17f, 0xc928, 0x21, 0 + .dw 0xa1c0, 0xc928, 0xa1ff, 0xc928, 0x21, 0 + .dw 0xa240, 0xc928, 0xa27f, 0xc928, 0x21, 0 + .dw 0xa2c0, 0xc928, 0xa2ff, 0xc928, 0x21, 0 + .dw 0xa340, 0xc928, 0xa37f, 0xc928, 0x21, 0 + .dw 0xa3c0, 0xc928, 0xa3ff, 0xc928, 0x21, 0 + .dw 0xa440, 0xc928, 0xa47f, 0xc928, 0x21, 0 + .dw 0xa4c0, 0xc928, 0xa4ff, 0xc928, 0x21, 0 + .dw 0xa540, 0xc928, 0xa57f, 0xc928, 0x21, 0 + .dw 0xa5c0, 0xc928, 0xa5ff, 0xc928, 0x21, 0 + .dw 0xa640, 0xc928, 0xa67f, 0xc928, 0x21, 0 + .dw 0xa6c0, 0xc928, 0xa6ff, 0xc928, 0x21, 0 + .dw 0xa740, 0xc928, 0xa77f, 0xc928, 0x21, 0 + .dw 0xa7c0, 0xc928, 0xa7ff, 0xc928, 0x21, 0 + .dw 0xa840, 0xc928, 0xa87f, 0xc928, 0x21, 0 + .dw 0xa8c0, 0xc928, 0xa8ff, 0xc928, 0x21, 0 + .dw 0xa940, 0xc928, 0xa97f, 0xc928, 0x21, 0 + .dw 0xa9c0, 0xc928, 0xa9ff, 0xc928, 0x21, 0 + .dw 0xaa40, 0xc928, 0xaa7f, 0xc928, 0x21, 0 + .dw 0xaac0, 0xc928, 0xaaff, 0xc928, 0x21, 0 + .dw 0xab40, 0xc928, 0xab7f, 0xc928, 0x21, 0 + .dw 0xabc0, 0xc928, 0xabff, 0xc928, 0x21, 0 + .dw 0xac40, 0xc928, 0xac7f, 0xc928, 0x21, 0 + .dw 0xacc0, 0xc928, 0xacff, 0xc928, 0x21, 0 + .dw 0xad40, 0xc928, 0xad7f, 0xc928, 0x21, 0 + .dw 0xadc0, 0xc928, 0xadff, 0xc928, 0x21, 0 + .dw 0xae40, 0xc928, 0xae7f, 0xc928, 0x21, 0 + .dw 0xaec0, 0xc928, 0xaeff, 0xc928, 0x21, 0 + .dw 0xaf40, 0xc928, 0xaf7f, 0xc928, 0x21, 0 + .dw 0xafc0, 0xc928, 0xafff, 0xc928, 0x21, 0 + .dw 0xb040, 0xc928, 0xb07f, 0xc928, 0x21, 0 + .dw 0xb0c0, 0xc928, 0xb0ff, 0xc928, 0x21, 0 + .dw 0xb140, 0xc928, 0xb17f, 0xc928, 0x21, 0 + .dw 0xb1c0, 0xc928, 0xb1ff, 0xc928, 0x21, 0 + .dw 0xb240, 0xc928, 0xb27f, 0xc928, 0x21, 0 + .dw 0xb2c0, 0xc928, 0xb2ff, 0xc928, 0x21, 0 + .dw 0xb340, 0xc928, 0xb37f, 0xc928, 0x21, 0 + .dw 0xb3c0, 0xc928, 0xb3ff, 0xc928, 0x21, 0 + .dw 0xb440, 0xc928, 0xb47f, 0xc928, 0x21, 0 + .dw 0xb4c0, 0xc928, 0xb4ff, 0xc928, 0x21, 0 + .dw 0xb540, 0xc928, 0xb57f, 0xc928, 0x21, 0 + .dw 0xb5c0, 0xc928, 0xb5ff, 0xc928, 0x21, 0 + .dw 0xb640, 0xc928, 0xb67f, 0xc928, 0x21, 0 + .dw 0xb6c0, 0xc928, 0xb6ff, 0xc928, 0x21, 0 + .dw 0xb740, 0xc928, 0xb77f, 0xc928, 0x21, 0 + .dw 0xb7c0, 0xc928, 0xb7ff, 0xc928, 0x21, 0 + .dw 0xb840, 0xc928, 0xb87f, 0xc928, 0x21, 0 + .dw 0xb8c0, 0xc928, 0xb8ff, 0xc928, 0x21, 0 + .dw 0xb940, 0xc928, 0xb97f, 0xc928, 0x21, 0 + .dw 0xb9c0, 0xc928, 0xdfff, 0xc928, 0x21, 0 + .dw 0xe040, 0xc928, 0xe07f, 0xc928, 0x21, 0 + .dw 0xe0c0, 0xc928, 0xe0ff, 0xc928, 0x21, 0 + .dw 0xe140, 0xc928, 0xe17f, 0xc928, 0x21, 0 + .dw 0xe1c0, 0xc928, 0xe1ff, 0xc928, 0x21, 0 + .dw 0xe240, 0xc928, 0xe27f, 0xc928, 0x21, 0 + .dw 0xe2c0, 0xc928, 0xe2ff, 0xc928, 0x21, 0 + .dw 0xe340, 0xc928, 0xe37f, 0xc928, 0x21, 0 + .dw 0xe3c0, 0xc928, 0xe3ff, 0xc928, 0x21, 0 + .dw 0xe440, 0xc928, 0xe47f, 0xc928, 0x21, 0 + .dw 0xe4c0, 0xc928, 0xe4ff, 0xc928, 0x21, 0 + .dw 0xe540, 0xc928, 0xe57f, 0xc928, 0x21, 0 + .dw 0xe5c0, 0xc928, 0xe5ff, 0xc928, 0x21, 0 + .dw 0xe640, 0xc928, 0xe67f, 0xc928, 0x21, 0 + .dw 0xe6c0, 0xc928, 0xe6ff, 0xc928, 0x21, 0 + .dw 0xe740, 0xc928, 0xe77f, 0xc928, 0x21, 0 + .dw 0xe7c0, 0xc928, 0xe7ff, 0xc928, 0x21, 0 + .dw 0xe840, 0xc928, 0xe87f, 0xc928, 0x21, 0 + .dw 0xe8c0, 0xc928, 0xe8ff, 0xc928, 0x21, 0 + .dw 0xe940, 0xc928, 0xe97f, 0xc928, 0x21, 0 + .dw 0xe9c0, 0xc928, 0xe9ff, 0xc928, 0x21, 0 + .dw 0xea40, 0xc928, 0xea7f, 0xc928, 0x21, 0 + .dw 0xeac0, 0xc928, 0xeaff, 0xc928, 0x21, 0 + .dw 0xeb40, 0xc928, 0xeb7f, 0xc928, 0x21, 0 + .dw 0xebc0, 0xc928, 0xebff, 0xc928, 0x21, 0 + .dw 0xec40, 0xc928, 0xec7f, 0xc928, 0x21, 0 + .dw 0xecc0, 0xc928, 0xecff, 0xc928, 0x21, 0 + .dw 0xed40, 0xc928, 0xed7f, 0xc928, 0x21, 0 + .dw 0xedc0, 0xc928, 0xedff, 0xc928, 0x21, 0 + .dw 0xee40, 0xc928, 0xee7f, 0xc928, 0x21, 0 + .dw 0xeec0, 0xc928, 0xeeff, 0xc928, 0x21, 0 + .dw 0xef40, 0xc928, 0xef7f, 0xc928, 0x21, 0 + .dw 0xefc0, 0xc928, 0xefff, 0xc928, 0x21, 0 + .dw 0xf040, 0xc928, 0xf07f, 0xc928, 0x21, 0 + .dw 0xf0c0, 0xc928, 0xf0ff, 0xc928, 0x21, 0 + .dw 0xf140, 0xc928, 0xf17f, 0xc928, 0x21, 0 + .dw 0xf1c0, 0xc928, 0xf1ff, 0xc928, 0x21, 0 + .dw 0xf240, 0xc928, 0xf27f, 0xc928, 0x21, 0 + .dw 0xf2c0, 0xc928, 0xf2ff, 0xc928, 0x21, 0 + .dw 0xf340, 0xc928, 0xf37f, 0xc928, 0x21, 0 + .dw 0xf3c0, 0xc928, 0xf3ff, 0xc928, 0x21, 0 + .dw 0xf440, 0xc928, 0xf47f, 0xc928, 0x21, 0 + .dw 0xf4c0, 0xc928, 0xf4ff, 0xc928, 0x21, 0 + .dw 0xf540, 0xc928, 0xf57f, 0xc928, 0x21, 0 + .dw 0xf5c0, 0xc928, 0xf5ff, 0xc928, 0x21, 0 + .dw 0xf640, 0xc928, 0xf67f, 0xc928, 0x21, 0 + .dw 0xf6c0, 0xc928, 0xf6ff, 0xc928, 0x21, 0 + .dw 0xf740, 0xc928, 0xf77f, 0xc928, 0x21, 0 + .dw 0xf7c0, 0xc928, 0xf7ff, 0xc928, 0x21, 0 + .dw 0xf840, 0xc928, 0xf87f, 0xc928, 0x21, 0 + .dw 0xf8c0, 0xc928, 0xf8ff, 0xc928, 0x21, 0 + .dw 0xf940, 0xc928, 0xf97f, 0xc928, 0x21, 0 + .dw 0xf9c0, 0xc928, 0x1fff, 0xc929, 0x21, 0 + .dw 0x2040, 0xc929, 0x207f, 0xc929, 0x21, 0 + .dw 0x20c0, 0xc929, 0x20ff, 0xc929, 0x21, 0 + .dw 0x2140, 0xc929, 0x217f, 0xc929, 0x21, 0 + .dw 0x21c0, 0xc929, 0x21ff, 0xc929, 0x21, 0 + .dw 0x2240, 0xc929, 0x227f, 0xc929, 0x21, 0 + .dw 0x22c0, 0xc929, 0x22ff, 0xc929, 0x21, 0 + .dw 0x2340, 0xc929, 0x237f, 0xc929, 0x21, 0 + .dw 0x23c0, 0xc929, 0x23ff, 0xc929, 0x21, 0 + .dw 0x2440, 0xc929, 0x247f, 0xc929, 0x21, 0 + .dw 0x24c0, 0xc929, 0x24ff, 0xc929, 0x21, 0 + .dw 0x2540, 0xc929, 0x257f, 0xc929, 0x21, 0 + .dw 0x25c0, 0xc929, 0x25ff, 0xc929, 0x21, 0 + .dw 0x2640, 0xc929, 0x267f, 0xc929, 0x21, 0 + .dw 0x26c0, 0xc929, 0x26ff, 0xc929, 0x21, 0 + .dw 0x2740, 0xc929, 0x277f, 0xc929, 0x21, 0 + .dw 0x27c0, 0xc929, 0x27ff, 0xc929, 0x21, 0 + .dw 0x2840, 0xc929, 0x287f, 0xc929, 0x21, 0 + .dw 0x28c0, 0xc929, 0x28ff, 0xc929, 0x21, 0 + .dw 0x2940, 0xc929, 0x297f, 0xc929, 0x21, 0 + .dw 0x29c0, 0xc929, 0x29ff, 0xc929, 0x21, 0 + .dw 0x2a40, 0xc929, 0x2a7f, 0xc929, 0x21, 0 + .dw 0x2ac0, 0xc929, 0x2aff, 0xc929, 0x21, 0 + .dw 0x2b40, 0xc929, 0x2b7f, 0xc929, 0x21, 0 + .dw 0x2bc0, 0xc929, 0x2bff, 0xc929, 0x21, 0 + .dw 0x2c40, 0xc929, 0x2c7f, 0xc929, 0x21, 0 + .dw 0x2cc0, 0xc929, 0x2cff, 0xc929, 0x21, 0 + .dw 0x2d40, 0xc929, 0x2d7f, 0xc929, 0x21, 0 + .dw 0x2dc0, 0xc929, 0x2dff, 0xc929, 0x21, 0 + .dw 0x2e40, 0xc929, 0x2e7f, 0xc929, 0x21, 0 + .dw 0x2ec0, 0xc929, 0x2eff, 0xc929, 0x21, 0 + .dw 0x2f40, 0xc929, 0x2f7f, 0xc929, 0x21, 0 + .dw 0x2fc0, 0xc929, 0x2fff, 0xc929, 0x21, 0 + .dw 0x3040, 0xc929, 0x307f, 0xc929, 0x21, 0 + .dw 0x30c0, 0xc929, 0x30ff, 0xc929, 0x21, 0 + .dw 0x3140, 0xc929, 0x317f, 0xc929, 0x21, 0 + .dw 0x31c0, 0xc929, 0x31ff, 0xc929, 0x21, 0 + .dw 0x3240, 0xc929, 0x327f, 0xc929, 0x21, 0 + .dw 0x32c0, 0xc929, 0x32ff, 0xc929, 0x21, 0 + .dw 0x3340, 0xc929, 0x337f, 0xc929, 0x21, 0 + .dw 0x33c0, 0xc929, 0x33ff, 0xc929, 0x21, 0 + .dw 0x3440, 0xc929, 0x347f, 0xc929, 0x21, 0 + .dw 0x34c0, 0xc929, 0x34ff, 0xc929, 0x21, 0 + .dw 0x3540, 0xc929, 0x357f, 0xc929, 0x21, 0 + .dw 0x35c0, 0xc929, 0x35ff, 0xc929, 0x21, 0 + .dw 0x3640, 0xc929, 0x367f, 0xc929, 0x21, 0 + .dw 0x36c0, 0xc929, 0x36ff, 0xc929, 0x21, 0 + .dw 0x3740, 0xc929, 0x377f, 0xc929, 0x21, 0 + .dw 0x37c0, 0xc929, 0x37ff, 0xc929, 0x21, 0 + .dw 0x3840, 0xc929, 0x387f, 0xc929, 0x21, 0 + .dw 0x38c0, 0xc929, 0x38ff, 0xc929, 0x21, 0 + .dw 0x3940, 0xc929, 0x397f, 0xc929, 0x21, 0 + .dw 0x39c0, 0xc929, 0x5fff, 0xc929, 0x21, 0 + .dw 0x6040, 0xc929, 0x607f, 0xc929, 0x21, 0 + .dw 0x60c0, 0xc929, 0x60ff, 0xc929, 0x21, 0 + .dw 0x6140, 0xc929, 0x617f, 0xc929, 0x21, 0 + .dw 0x61c0, 0xc929, 0x61ff, 0xc929, 0x21, 0 + .dw 0x6240, 0xc929, 0x627f, 0xc929, 0x21, 0 + .dw 0x62c0, 0xc929, 0x62ff, 0xc929, 0x21, 0 + .dw 0x6340, 0xc929, 0x637f, 0xc929, 0x21, 0 + .dw 0x63c0, 0xc929, 0x63ff, 0xc929, 0x21, 0 + .dw 0x6440, 0xc929, 0x647f, 0xc929, 0x21, 0 + .dw 0x64c0, 0xc929, 0x64ff, 0xc929, 0x21, 0 + .dw 0x6540, 0xc929, 0x657f, 0xc929, 0x21, 0 + .dw 0x65c0, 0xc929, 0x65ff, 0xc929, 0x21, 0 + .dw 0x6640, 0xc929, 0x667f, 0xc929, 0x21, 0 + .dw 0x66c0, 0xc929, 0x66ff, 0xc929, 0x21, 0 + .dw 0x6740, 0xc929, 0x677f, 0xc929, 0x21, 0 + .dw 0x67c0, 0xc929, 0x67ff, 0xc929, 0x21, 0 + .dw 0x6840, 0xc929, 0x687f, 0xc929, 0x21, 0 + .dw 0x68c0, 0xc929, 0x68ff, 0xc929, 0x21, 0 + .dw 0x6940, 0xc929, 0x697f, 0xc929, 0x21, 0 + .dw 0x69c0, 0xc929, 0x69ff, 0xc929, 0x21, 0 + .dw 0x6a40, 0xc929, 0x6a7f, 0xc929, 0x21, 0 + .dw 0x6ac0, 0xc929, 0x6aff, 0xc929, 0x21, 0 + .dw 0x6b40, 0xc929, 0x6b7f, 0xc929, 0x21, 0 + .dw 0x6bc0, 0xc929, 0x6bff, 0xc929, 0x21, 0 + .dw 0x6c40, 0xc929, 0x6c7f, 0xc929, 0x21, 0 + .dw 0x6cc0, 0xc929, 0x6cff, 0xc929, 0x21, 0 + .dw 0x6d40, 0xc929, 0x6d7f, 0xc929, 0x21, 0 + .dw 0x6dc0, 0xc929, 0x6dff, 0xc929, 0x21, 0 + .dw 0x6e40, 0xc929, 0x6e7f, 0xc929, 0x21, 0 + .dw 0x6ec0, 0xc929, 0x6eff, 0xc929, 0x21, 0 + .dw 0x6f40, 0xc929, 0x6f7f, 0xc929, 0x21, 0 + .dw 0x6fc0, 0xc929, 0x6fff, 0xc929, 0x21, 0 + .dw 0x7040, 0xc929, 0x707f, 0xc929, 0x21, 0 + .dw 0x70c0, 0xc929, 0x70ff, 0xc929, 0x21, 0 + .dw 0x7140, 0xc929, 0x717f, 0xc929, 0x21, 0 + .dw 0x71c0, 0xc929, 0x71ff, 0xc929, 0x21, 0 + .dw 0x7240, 0xc929, 0x727f, 0xc929, 0x21, 0 + .dw 0x72c0, 0xc929, 0x72ff, 0xc929, 0x21, 0 + .dw 0x7340, 0xc929, 0x737f, 0xc929, 0x21, 0 + .dw 0x73c0, 0xc929, 0x73ff, 0xc929, 0x21, 0 + .dw 0x7440, 0xc929, 0x747f, 0xc929, 0x21, 0 + .dw 0x74c0, 0xc929, 0x74ff, 0xc929, 0x21, 0 + .dw 0x7540, 0xc929, 0x757f, 0xc929, 0x21, 0 + .dw 0x75c0, 0xc929, 0x75ff, 0xc929, 0x21, 0 + .dw 0x7640, 0xc929, 0x767f, 0xc929, 0x21, 0 + .dw 0x76c0, 0xc929, 0x76ff, 0xc929, 0x21, 0 + .dw 0x7740, 0xc929, 0x777f, 0xc929, 0x21, 0 + .dw 0x77c0, 0xc929, 0x77ff, 0xc929, 0x21, 0 + .dw 0x7840, 0xc929, 0x787f, 0xc929, 0x21, 0 + .dw 0x78c0, 0xc929, 0x78ff, 0xc929, 0x21, 0 + .dw 0x7940, 0xc929, 0x797f, 0xc929, 0x21, 0 + .dw 0x79c0, 0xc929, 0x9fff, 0xc929, 0x21, 0 + .dw 0xa040, 0xc929, 0xa07f, 0xc929, 0x21, 0 + .dw 0xa0c0, 0xc929, 0xa0ff, 0xc929, 0x21, 0 + .dw 0xa140, 0xc929, 0xa17f, 0xc929, 0x21, 0 + .dw 0xa1c0, 0xc929, 0xa1ff, 0xc929, 0x21, 0 + .dw 0xa240, 0xc929, 0xa27f, 0xc929, 0x21, 0 + .dw 0xa2c0, 0xc929, 0xa2ff, 0xc929, 0x21, 0 + .dw 0xa340, 0xc929, 0xa37f, 0xc929, 0x21, 0 + .dw 0xa3c0, 0xc929, 0xa3ff, 0xc929, 0x21, 0 + .dw 0xa440, 0xc929, 0xa47f, 0xc929, 0x21, 0 + .dw 0xa4c0, 0xc929, 0xa4ff, 0xc929, 0x21, 0 + .dw 0xa540, 0xc929, 0xa57f, 0xc929, 0x21, 0 + .dw 0xa5c0, 0xc929, 0xa5ff, 0xc929, 0x21, 0 + .dw 0xa640, 0xc929, 0xa67f, 0xc929, 0x21, 0 + .dw 0xa6c0, 0xc929, 0xa6ff, 0xc929, 0x21, 0 + .dw 0xa740, 0xc929, 0xa77f, 0xc929, 0x21, 0 + .dw 0xa7c0, 0xc929, 0xa7ff, 0xc929, 0x21, 0 + .dw 0xa840, 0xc929, 0xa87f, 0xc929, 0x21, 0 + .dw 0xa8c0, 0xc929, 0xa8ff, 0xc929, 0x21, 0 + .dw 0xa940, 0xc929, 0xa97f, 0xc929, 0x21, 0 + .dw 0xa9c0, 0xc929, 0xa9ff, 0xc929, 0x21, 0 + .dw 0xaa40, 0xc929, 0xaa7f, 0xc929, 0x21, 0 + .dw 0xaac0, 0xc929, 0xaaff, 0xc929, 0x21, 0 + .dw 0xab40, 0xc929, 0xab7f, 0xc929, 0x21, 0 + .dw 0xabc0, 0xc929, 0xabff, 0xc929, 0x21, 0 + .dw 0xac40, 0xc929, 0xac7f, 0xc929, 0x21, 0 + .dw 0xacc0, 0xc929, 0xacff, 0xc929, 0x21, 0 + .dw 0xad40, 0xc929, 0xad7f, 0xc929, 0x21, 0 + .dw 0xadc0, 0xc929, 0xadff, 0xc929, 0x21, 0 + .dw 0xae40, 0xc929, 0xae7f, 0xc929, 0x21, 0 + .dw 0xaec0, 0xc929, 0xaeff, 0xc929, 0x21, 0 + .dw 0xaf40, 0xc929, 0xaf7f, 0xc929, 0x21, 0 + .dw 0xafc0, 0xc929, 0xafff, 0xc929, 0x21, 0 + .dw 0xb040, 0xc929, 0xb07f, 0xc929, 0x21, 0 + .dw 0xb0c0, 0xc929, 0xb0ff, 0xc929, 0x21, 0 + .dw 0xb140, 0xc929, 0xb17f, 0xc929, 0x21, 0 + .dw 0xb1c0, 0xc929, 0xb1ff, 0xc929, 0x21, 0 + .dw 0xb240, 0xc929, 0xb27f, 0xc929, 0x21, 0 + .dw 0xb2c0, 0xc929, 0xb2ff, 0xc929, 0x21, 0 + .dw 0xb340, 0xc929, 0xb37f, 0xc929, 0x21, 0 + .dw 0xb3c0, 0xc929, 0xb3ff, 0xc929, 0x21, 0 + .dw 0xb440, 0xc929, 0xb47f, 0xc929, 0x21, 0 + .dw 0xb4c0, 0xc929, 0xb4ff, 0xc929, 0x21, 0 + .dw 0xb540, 0xc929, 0xb57f, 0xc929, 0x21, 0 + .dw 0xb5c0, 0xc929, 0xb5ff, 0xc929, 0x21, 0 + .dw 0xb640, 0xc929, 0xb67f, 0xc929, 0x21, 0 + .dw 0xb6c0, 0xc929, 0xb6ff, 0xc929, 0x21, 0 + .dw 0xb740, 0xc929, 0xb77f, 0xc929, 0x21, 0 + .dw 0xb7c0, 0xc929, 0xb7ff, 0xc929, 0x21, 0 + .dw 0xb840, 0xc929, 0xb87f, 0xc929, 0x21, 0 + .dw 0xb8c0, 0xc929, 0xb8ff, 0xc929, 0x21, 0 + .dw 0xb940, 0xc929, 0xb97f, 0xc929, 0x21, 0 + .dw 0xb9c0, 0xc929, 0xdfff, 0xc929, 0x21, 0 + .dw 0xe040, 0xc929, 0xe07f, 0xc929, 0x21, 0 + .dw 0xe0c0, 0xc929, 0xe0ff, 0xc929, 0x21, 0 + .dw 0xe140, 0xc929, 0xe17f, 0xc929, 0x21, 0 + .dw 0xe1c0, 0xc929, 0xe1ff, 0xc929, 0x21, 0 + .dw 0xe240, 0xc929, 0xe27f, 0xc929, 0x21, 0 + .dw 0xe2c0, 0xc929, 0xe2ff, 0xc929, 0x21, 0 + .dw 0xe340, 0xc929, 0xe37f, 0xc929, 0x21, 0 + .dw 0xe3c0, 0xc929, 0xe3ff, 0xc929, 0x21, 0 + .dw 0xe440, 0xc929, 0xe47f, 0xc929, 0x21, 0 + .dw 0xe4c0, 0xc929, 0xe4ff, 0xc929, 0x21, 0 + .dw 0xe540, 0xc929, 0xe57f, 0xc929, 0x21, 0 + .dw 0xe5c0, 0xc929, 0xe5ff, 0xc929, 0x21, 0 + .dw 0xe640, 0xc929, 0xe67f, 0xc929, 0x21, 0 + .dw 0xe6c0, 0xc929, 0xe6ff, 0xc929, 0x21, 0 + .dw 0xe740, 0xc929, 0xe77f, 0xc929, 0x21, 0 + .dw 0xe7c0, 0xc929, 0xe7ff, 0xc929, 0x21, 0 + .dw 0xe840, 0xc929, 0xe87f, 0xc929, 0x21, 0 + .dw 0xe8c0, 0xc929, 0xe8ff, 0xc929, 0x21, 0 + .dw 0xe940, 0xc929, 0xe97f, 0xc929, 0x21, 0 + .dw 0xe9c0, 0xc929, 0xe9ff, 0xc929, 0x21, 0 + .dw 0xea40, 0xc929, 0xea7f, 0xc929, 0x21, 0 + .dw 0xeac0, 0xc929, 0xeaff, 0xc929, 0x21, 0 + .dw 0xeb40, 0xc929, 0xeb7f, 0xc929, 0x21, 0 + .dw 0xebc0, 0xc929, 0xebff, 0xc929, 0x21, 0 + .dw 0xec40, 0xc929, 0xec7f, 0xc929, 0x21, 0 + .dw 0xecc0, 0xc929, 0xecff, 0xc929, 0x21, 0 + .dw 0xed40, 0xc929, 0xed7f, 0xc929, 0x21, 0 + .dw 0xedc0, 0xc929, 0xedff, 0xc929, 0x21, 0 + .dw 0xee40, 0xc929, 0xee7f, 0xc929, 0x21, 0 + .dw 0xeec0, 0xc929, 0xeeff, 0xc929, 0x21, 0 + .dw 0xef40, 0xc929, 0xef7f, 0xc929, 0x21, 0 + .dw 0xefc0, 0xc929, 0xefff, 0xc929, 0x21, 0 + .dw 0xf040, 0xc929, 0xf07f, 0xc929, 0x21, 0 + .dw 0xf0c0, 0xc929, 0xf0ff, 0xc929, 0x21, 0 + .dw 0xf140, 0xc929, 0xf17f, 0xc929, 0x21, 0 + .dw 0xf1c0, 0xc929, 0xf1ff, 0xc929, 0x21, 0 + .dw 0xf240, 0xc929, 0xf27f, 0xc929, 0x21, 0 + .dw 0xf2c0, 0xc929, 0xf2ff, 0xc929, 0x21, 0 + .dw 0xf340, 0xc929, 0xf37f, 0xc929, 0x21, 0 + .dw 0xf3c0, 0xc929, 0xf3ff, 0xc929, 0x21, 0 + .dw 0xf440, 0xc929, 0xf47f, 0xc929, 0x21, 0 + .dw 0xf4c0, 0xc929, 0xf4ff, 0xc929, 0x21, 0 + .dw 0xf540, 0xc929, 0xf57f, 0xc929, 0x21, 0 + .dw 0xf5c0, 0xc929, 0xf5ff, 0xc929, 0x21, 0 + .dw 0xf640, 0xc929, 0xf67f, 0xc929, 0x21, 0 + .dw 0xf6c0, 0xc929, 0xf6ff, 0xc929, 0x21, 0 + .dw 0xf740, 0xc929, 0xf77f, 0xc929, 0x21, 0 + .dw 0xf7c0, 0xc929, 0xf7ff, 0xc929, 0x21, 0 + .dw 0xf840, 0xc929, 0xf87f, 0xc929, 0x21, 0 + .dw 0xf8c0, 0xc929, 0xf8ff, 0xc929, 0x21, 0 + .dw 0xf940, 0xc929, 0xf97f, 0xc929, 0x21, 0 + .dw 0xf9c0, 0xc929, 0x1fff, 0xc92a, 0x21, 0 + .dw 0x2040, 0xc92a, 0x207f, 0xc92a, 0x21, 0 + .dw 0x20c0, 0xc92a, 0x20ff, 0xc92a, 0x21, 0 + .dw 0x2140, 0xc92a, 0x217f, 0xc92a, 0x21, 0 + .dw 0x21c0, 0xc92a, 0x21ff, 0xc92a, 0x21, 0 + .dw 0x2240, 0xc92a, 0x227f, 0xc92a, 0x21, 0 + .dw 0x22c0, 0xc92a, 0x22ff, 0xc92a, 0x21, 0 + .dw 0x2340, 0xc92a, 0x237f, 0xc92a, 0x21, 0 + .dw 0x23c0, 0xc92a, 0x23ff, 0xc92a, 0x21, 0 + .dw 0x2440, 0xc92a, 0x247f, 0xc92a, 0x21, 0 + .dw 0x24c0, 0xc92a, 0x24ff, 0xc92a, 0x21, 0 + .dw 0x2540, 0xc92a, 0x257f, 0xc92a, 0x21, 0 + .dw 0x25c0, 0xc92a, 0x25ff, 0xc92a, 0x21, 0 + .dw 0x2640, 0xc92a, 0x267f, 0xc92a, 0x21, 0 + .dw 0x26c0, 0xc92a, 0x26ff, 0xc92a, 0x21, 0 + .dw 0x2740, 0xc92a, 0x277f, 0xc92a, 0x21, 0 + .dw 0x27c0, 0xc92a, 0x27ff, 0xc92a, 0x21, 0 + .dw 0x2840, 0xc92a, 0x287f, 0xc92a, 0x21, 0 + .dw 0x28c0, 0xc92a, 0x28ff, 0xc92a, 0x21, 0 + .dw 0x2940, 0xc92a, 0x297f, 0xc92a, 0x21, 0 + .dw 0x29c0, 0xc92a, 0x29ff, 0xc92a, 0x21, 0 + .dw 0x2a40, 0xc92a, 0x2a7f, 0xc92a, 0x21, 0 + .dw 0x2ac0, 0xc92a, 0x2aff, 0xc92a, 0x21, 0 + .dw 0x2b40, 0xc92a, 0x2b7f, 0xc92a, 0x21, 0 + .dw 0x2bc0, 0xc92a, 0x2bff, 0xc92a, 0x21, 0 + .dw 0x2c40, 0xc92a, 0x2c7f, 0xc92a, 0x21, 0 + .dw 0x2cc0, 0xc92a, 0x2cff, 0xc92a, 0x21, 0 + .dw 0x2d40, 0xc92a, 0x2d7f, 0xc92a, 0x21, 0 + .dw 0x2dc0, 0xc92a, 0x2dff, 0xc92a, 0x21, 0 + .dw 0x2e40, 0xc92a, 0x2e7f, 0xc92a, 0x21, 0 + .dw 0x2ec0, 0xc92a, 0x2eff, 0xc92a, 0x21, 0 + .dw 0x2f40, 0xc92a, 0x2f7f, 0xc92a, 0x21, 0 + .dw 0x2fc0, 0xc92a, 0x2fff, 0xc92a, 0x21, 0 + .dw 0x3040, 0xc92a, 0x307f, 0xc92a, 0x21, 0 + .dw 0x30c0, 0xc92a, 0x30ff, 0xc92a, 0x21, 0 + .dw 0x3140, 0xc92a, 0x317f, 0xc92a, 0x21, 0 + .dw 0x31c0, 0xc92a, 0x31ff, 0xc92a, 0x21, 0 + .dw 0x3240, 0xc92a, 0x327f, 0xc92a, 0x21, 0 + .dw 0x32c0, 0xc92a, 0x32ff, 0xc92a, 0x21, 0 + .dw 0x3340, 0xc92a, 0x337f, 0xc92a, 0x21, 0 + .dw 0x33c0, 0xc92a, 0x33ff, 0xc92a, 0x21, 0 + .dw 0x3440, 0xc92a, 0x347f, 0xc92a, 0x21, 0 + .dw 0x34c0, 0xc92a, 0x34ff, 0xc92a, 0x21, 0 + .dw 0x3540, 0xc92a, 0x357f, 0xc92a, 0x21, 0 + .dw 0x35c0, 0xc92a, 0x35ff, 0xc92a, 0x21, 0 + .dw 0x3640, 0xc92a, 0x367f, 0xc92a, 0x21, 0 + .dw 0x36c0, 0xc92a, 0x36ff, 0xc92a, 0x21, 0 + .dw 0x3740, 0xc92a, 0x377f, 0xc92a, 0x21, 0 + .dw 0x37c0, 0xc92a, 0x37ff, 0xc92a, 0x21, 0 + .dw 0x3840, 0xc92a, 0x387f, 0xc92a, 0x21, 0 + .dw 0x38c0, 0xc92a, 0x38ff, 0xc92a, 0x21, 0 + .dw 0x3940, 0xc92a, 0x397f, 0xc92a, 0x21, 0 + .dw 0x39c0, 0xc92a, 0x5fff, 0xc92a, 0x21, 0 + .dw 0x6040, 0xc92a, 0x607f, 0xc92a, 0x21, 0 + .dw 0x60c0, 0xc92a, 0x60ff, 0xc92a, 0x21, 0 + .dw 0x6140, 0xc92a, 0x617f, 0xc92a, 0x21, 0 + .dw 0x61c0, 0xc92a, 0x61ff, 0xc92a, 0x21, 0 + .dw 0x6240, 0xc92a, 0x627f, 0xc92a, 0x21, 0 + .dw 0x62c0, 0xc92a, 0x62ff, 0xc92a, 0x21, 0 + .dw 0x6340, 0xc92a, 0x637f, 0xc92a, 0x21, 0 + .dw 0x63c0, 0xc92a, 0x63ff, 0xc92a, 0x21, 0 + .dw 0x6440, 0xc92a, 0x647f, 0xc92a, 0x21, 0 + .dw 0x64c0, 0xc92a, 0x64ff, 0xc92a, 0x21, 0 + .dw 0x6540, 0xc92a, 0x657f, 0xc92a, 0x21, 0 + .dw 0x65c0, 0xc92a, 0x65ff, 0xc92a, 0x21, 0 + .dw 0x6640, 0xc92a, 0x667f, 0xc92a, 0x21, 0 + .dw 0x66c0, 0xc92a, 0x66ff, 0xc92a, 0x21, 0 + .dw 0x6740, 0xc92a, 0x677f, 0xc92a, 0x21, 0 + .dw 0x67c0, 0xc92a, 0x67ff, 0xc92a, 0x21, 0 + .dw 0x6840, 0xc92a, 0x687f, 0xc92a, 0x21, 0 + .dw 0x68c0, 0xc92a, 0x68ff, 0xc92a, 0x21, 0 + .dw 0x6940, 0xc92a, 0x697f, 0xc92a, 0x21, 0 + .dw 0x69c0, 0xc92a, 0x69ff, 0xc92a, 0x21, 0 + .dw 0x6a40, 0xc92a, 0x6a7f, 0xc92a, 0x21, 0 + .dw 0x6ac0, 0xc92a, 0x6aff, 0xc92a, 0x21, 0 + .dw 0x6b40, 0xc92a, 0x6b7f, 0xc92a, 0x21, 0 + .dw 0x6bc0, 0xc92a, 0x6bff, 0xc92a, 0x21, 0 + .dw 0x6c40, 0xc92a, 0x6c7f, 0xc92a, 0x21, 0 + .dw 0x6cc0, 0xc92a, 0x6cff, 0xc92a, 0x21, 0 + .dw 0x6d40, 0xc92a, 0x6d7f, 0xc92a, 0x21, 0 + .dw 0x6dc0, 0xc92a, 0x6dff, 0xc92a, 0x21, 0 + .dw 0x6e40, 0xc92a, 0x6e7f, 0xc92a, 0x21, 0 + .dw 0x6ec0, 0xc92a, 0x6eff, 0xc92a, 0x21, 0 + .dw 0x6f40, 0xc92a, 0x6f7f, 0xc92a, 0x21, 0 + .dw 0x6fc0, 0xc92a, 0x6fff, 0xc92a, 0x21, 0 + .dw 0x7040, 0xc92a, 0x707f, 0xc92a, 0x21, 0 + .dw 0x70c0, 0xc92a, 0x70ff, 0xc92a, 0x21, 0 + .dw 0x7140, 0xc92a, 0x717f, 0xc92a, 0x21, 0 + .dw 0x71c0, 0xc92a, 0x71ff, 0xc92a, 0x21, 0 + .dw 0x7240, 0xc92a, 0x727f, 0xc92a, 0x21, 0 + .dw 0x72c0, 0xc92a, 0x72ff, 0xc92a, 0x21, 0 + .dw 0x7340, 0xc92a, 0x737f, 0xc92a, 0x21, 0 + .dw 0x73c0, 0xc92a, 0x73ff, 0xc92a, 0x21, 0 + .dw 0x7440, 0xc92a, 0x747f, 0xc92a, 0x21, 0 + .dw 0x74c0, 0xc92a, 0x74ff, 0xc92a, 0x21, 0 + .dw 0x7540, 0xc92a, 0x757f, 0xc92a, 0x21, 0 + .dw 0x75c0, 0xc92a, 0x75ff, 0xc92a, 0x21, 0 + .dw 0x7640, 0xc92a, 0x767f, 0xc92a, 0x21, 0 + .dw 0x76c0, 0xc92a, 0x76ff, 0xc92a, 0x21, 0 + .dw 0x7740, 0xc92a, 0x777f, 0xc92a, 0x21, 0 + .dw 0x77c0, 0xc92a, 0x77ff, 0xc92a, 0x21, 0 + .dw 0x7840, 0xc92a, 0x787f, 0xc92a, 0x21, 0 + .dw 0x78c0, 0xc92a, 0x78ff, 0xc92a, 0x21, 0 + .dw 0x7940, 0xc92a, 0x797f, 0xc92a, 0x21, 0 + .dw 0x79c0, 0xc92a, 0x9fff, 0xc92a, 0x21, 0 + .dw 0xa040, 0xc92a, 0xa07f, 0xc92a, 0x21, 0 + .dw 0xa0c0, 0xc92a, 0xa0ff, 0xc92a, 0x21, 0 + .dw 0xa140, 0xc92a, 0xa17f, 0xc92a, 0x21, 0 + .dw 0xa1c0, 0xc92a, 0xa1ff, 0xc92a, 0x21, 0 + .dw 0xa240, 0xc92a, 0xa27f, 0xc92a, 0x21, 0 + .dw 0xa2c0, 0xc92a, 0xa2ff, 0xc92a, 0x21, 0 + .dw 0xa340, 0xc92a, 0xa37f, 0xc92a, 0x21, 0 + .dw 0xa3c0, 0xc92a, 0xa3ff, 0xc92a, 0x21, 0 + .dw 0xa440, 0xc92a, 0xa47f, 0xc92a, 0x21, 0 + .dw 0xa4c0, 0xc92a, 0xa4ff, 0xc92a, 0x21, 0 + .dw 0xa540, 0xc92a, 0xa57f, 0xc92a, 0x21, 0 + .dw 0xa5c0, 0xc92a, 0xa5ff, 0xc92a, 0x21, 0 + .dw 0xa640, 0xc92a, 0xa67f, 0xc92a, 0x21, 0 + .dw 0xa6c0, 0xc92a, 0xa6ff, 0xc92a, 0x21, 0 + .dw 0xa740, 0xc92a, 0xa77f, 0xc92a, 0x21, 0 + .dw 0xa7c0, 0xc92a, 0xa7ff, 0xc92a, 0x21, 0 + .dw 0xa840, 0xc92a, 0xa87f, 0xc92a, 0x21, 0 + .dw 0xa8c0, 0xc92a, 0xa8ff, 0xc92a, 0x21, 0 + .dw 0xa940, 0xc92a, 0xa97f, 0xc92a, 0x21, 0 + .dw 0xa9c0, 0xc92a, 0xa9ff, 0xc92a, 0x21, 0 + .dw 0xaa40, 0xc92a, 0xaa7f, 0xc92a, 0x21, 0 + .dw 0xaac0, 0xc92a, 0xaaff, 0xc92a, 0x21, 0 + .dw 0xab40, 0xc92a, 0xab7f, 0xc92a, 0x21, 0 + .dw 0xabc0, 0xc92a, 0xabff, 0xc92a, 0x21, 0 + .dw 0xac40, 0xc92a, 0xac7f, 0xc92a, 0x21, 0 + .dw 0xacc0, 0xc92a, 0xacff, 0xc92a, 0x21, 0 + .dw 0xad40, 0xc92a, 0xad7f, 0xc92a, 0x21, 0 + .dw 0xadc0, 0xc92a, 0xadff, 0xc92a, 0x21, 0 + .dw 0xae40, 0xc92a, 0xae7f, 0xc92a, 0x21, 0 + .dw 0xaec0, 0xc92a, 0xaeff, 0xc92a, 0x21, 0 + .dw 0xaf40, 0xc92a, 0xaf7f, 0xc92a, 0x21, 0 + .dw 0xafc0, 0xc92a, 0xafff, 0xc92a, 0x21, 0 + .dw 0xb040, 0xc92a, 0xb07f, 0xc92a, 0x21, 0 + .dw 0xb0c0, 0xc92a, 0xb0ff, 0xc92a, 0x21, 0 + .dw 0xb140, 0xc92a, 0xb17f, 0xc92a, 0x21, 0 + .dw 0xb1c0, 0xc92a, 0xb1ff, 0xc92a, 0x21, 0 + .dw 0xb240, 0xc92a, 0xb27f, 0xc92a, 0x21, 0 + .dw 0xb2c0, 0xc92a, 0xb2ff, 0xc92a, 0x21, 0 + .dw 0xb340, 0xc92a, 0xb37f, 0xc92a, 0x21, 0 + .dw 0xb3c0, 0xc92a, 0xb3ff, 0xc92a, 0x21, 0 + .dw 0xb440, 0xc92a, 0xb47f, 0xc92a, 0x21, 0 + .dw 0xb4c0, 0xc92a, 0xb4ff, 0xc92a, 0x21, 0 + .dw 0xb540, 0xc92a, 0xb57f, 0xc92a, 0x21, 0 + .dw 0xb5c0, 0xc92a, 0xb5ff, 0xc92a, 0x21, 0 + .dw 0xb640, 0xc92a, 0xb67f, 0xc92a, 0x21, 0 + .dw 0xb6c0, 0xc92a, 0xb6ff, 0xc92a, 0x21, 0 + .dw 0xb740, 0xc92a, 0xb77f, 0xc92a, 0x21, 0 + .dw 0xb7c0, 0xc92a, 0xb7ff, 0xc92a, 0x21, 0 + .dw 0xb840, 0xc92a, 0xb87f, 0xc92a, 0x21, 0 + .dw 0xb8c0, 0xc92a, 0xb8ff, 0xc92a, 0x21, 0 + .dw 0xb940, 0xc92a, 0xb97f, 0xc92a, 0x21, 0 + .dw 0xb9c0, 0xc92a, 0xdfff, 0xc92a, 0x21, 0 + .dw 0xe040, 0xc92a, 0xe07f, 0xc92a, 0x21, 0 + .dw 0xe0c0, 0xc92a, 0xe0ff, 0xc92a, 0x21, 0 + .dw 0xe140, 0xc92a, 0xe17f, 0xc92a, 0x21, 0 + .dw 0xe1c0, 0xc92a, 0xe1ff, 0xc92a, 0x21, 0 + .dw 0xe240, 0xc92a, 0xe27f, 0xc92a, 0x21, 0 + .dw 0xe2c0, 0xc92a, 0xe2ff, 0xc92a, 0x21, 0 + .dw 0xe340, 0xc92a, 0xe37f, 0xc92a, 0x21, 0 + .dw 0xe3c0, 0xc92a, 0xe3ff, 0xc92a, 0x21, 0 + .dw 0xe440, 0xc92a, 0xe47f, 0xc92a, 0x21, 0 + .dw 0xe4c0, 0xc92a, 0xe4ff, 0xc92a, 0x21, 0 + .dw 0xe540, 0xc92a, 0xe57f, 0xc92a, 0x21, 0 + .dw 0xe5c0, 0xc92a, 0xe5ff, 0xc92a, 0x21, 0 + .dw 0xe640, 0xc92a, 0xe67f, 0xc92a, 0x21, 0 + .dw 0xe6c0, 0xc92a, 0xe6ff, 0xc92a, 0x21, 0 + .dw 0xe740, 0xc92a, 0xe77f, 0xc92a, 0x21, 0 + .dw 0xe7c0, 0xc92a, 0xe7ff, 0xc92a, 0x21, 0 + .dw 0xe840, 0xc92a, 0xe87f, 0xc92a, 0x21, 0 + .dw 0xe8c0, 0xc92a, 0xe8ff, 0xc92a, 0x21, 0 + .dw 0xe940, 0xc92a, 0xe97f, 0xc92a, 0x21, 0 + .dw 0xe9c0, 0xc92a, 0xe9ff, 0xc92a, 0x21, 0 + .dw 0xea40, 0xc92a, 0xea7f, 0xc92a, 0x21, 0 + .dw 0xeac0, 0xc92a, 0xeaff, 0xc92a, 0x21, 0 + .dw 0xeb40, 0xc92a, 0xeb7f, 0xc92a, 0x21, 0 + .dw 0xebc0, 0xc92a, 0xebff, 0xc92a, 0x21, 0 + .dw 0xec40, 0xc92a, 0xec7f, 0xc92a, 0x21, 0 + .dw 0xecc0, 0xc92a, 0xecff, 0xc92a, 0x21, 0 + .dw 0xed40, 0xc92a, 0xed7f, 0xc92a, 0x21, 0 + .dw 0xedc0, 0xc92a, 0xedff, 0xc92a, 0x21, 0 + .dw 0xee40, 0xc92a, 0xee7f, 0xc92a, 0x21, 0 + .dw 0xeec0, 0xc92a, 0xeeff, 0xc92a, 0x21, 0 + .dw 0xef40, 0xc92a, 0xef7f, 0xc92a, 0x21, 0 + .dw 0xefc0, 0xc92a, 0xefff, 0xc92a, 0x21, 0 + .dw 0xf040, 0xc92a, 0xf07f, 0xc92a, 0x21, 0 + .dw 0xf0c0, 0xc92a, 0xf0ff, 0xc92a, 0x21, 0 + .dw 0xf140, 0xc92a, 0xf17f, 0xc92a, 0x21, 0 + .dw 0xf1c0, 0xc92a, 0xf1ff, 0xc92a, 0x21, 0 + .dw 0xf240, 0xc92a, 0xf27f, 0xc92a, 0x21, 0 + .dw 0xf2c0, 0xc92a, 0xf2ff, 0xc92a, 0x21, 0 + .dw 0xf340, 0xc92a, 0xf37f, 0xc92a, 0x21, 0 + .dw 0xf3c0, 0xc92a, 0xf3ff, 0xc92a, 0x21, 0 + .dw 0xf440, 0xc92a, 0xf47f, 0xc92a, 0x21, 0 + .dw 0xf4c0, 0xc92a, 0xf4ff, 0xc92a, 0x21, 0 + .dw 0xf540, 0xc92a, 0xf57f, 0xc92a, 0x21, 0 + .dw 0xf5c0, 0xc92a, 0xf5ff, 0xc92a, 0x21, 0 + .dw 0xf640, 0xc92a, 0xf67f, 0xc92a, 0x21, 0 + .dw 0xf6c0, 0xc92a, 0xf6ff, 0xc92a, 0x21, 0 + .dw 0xf740, 0xc92a, 0xf77f, 0xc92a, 0x21, 0 + .dw 0xf7c0, 0xc92a, 0xf7ff, 0xc92a, 0x21, 0 + .dw 0xf840, 0xc92a, 0xf87f, 0xc92a, 0x21, 0 + .dw 0xf8c0, 0xc92a, 0xf8ff, 0xc92a, 0x21, 0 + .dw 0xf940, 0xc92a, 0xf97f, 0xc92a, 0x21, 0 + .dw 0xf9c0, 0xc92a, 0x1fff, 0xc92b, 0x21, 0 + .dw 0x2040, 0xc92b, 0x207f, 0xc92b, 0x21, 0 + .dw 0x20c0, 0xc92b, 0x20ff, 0xc92b, 0x21, 0 + .dw 0x2140, 0xc92b, 0x217f, 0xc92b, 0x21, 0 + .dw 0x21c0, 0xc92b, 0x21ff, 0xc92b, 0x21, 0 + .dw 0x2240, 0xc92b, 0x227f, 0xc92b, 0x21, 0 + .dw 0x22c0, 0xc92b, 0x22ff, 0xc92b, 0x21, 0 + .dw 0x2340, 0xc92b, 0x237f, 0xc92b, 0x21, 0 + .dw 0x23c0, 0xc92b, 0x23ff, 0xc92b, 0x21, 0 + .dw 0x2440, 0xc92b, 0x247f, 0xc92b, 0x21, 0 + .dw 0x24c0, 0xc92b, 0x24ff, 0xc92b, 0x21, 0 + .dw 0x2540, 0xc92b, 0x257f, 0xc92b, 0x21, 0 + .dw 0x25c0, 0xc92b, 0x25ff, 0xc92b, 0x21, 0 + .dw 0x2640, 0xc92b, 0x267f, 0xc92b, 0x21, 0 + .dw 0x26c0, 0xc92b, 0x26ff, 0xc92b, 0x21, 0 + .dw 0x2740, 0xc92b, 0x277f, 0xc92b, 0x21, 0 + .dw 0x27c0, 0xc92b, 0x27ff, 0xc92b, 0x21, 0 + .dw 0x2840, 0xc92b, 0x287f, 0xc92b, 0x21, 0 + .dw 0x28c0, 0xc92b, 0x28ff, 0xc92b, 0x21, 0 + .dw 0x2940, 0xc92b, 0x297f, 0xc92b, 0x21, 0 + .dw 0x29c0, 0xc92b, 0x29ff, 0xc92b, 0x21, 0 + .dw 0x2a40, 0xc92b, 0x2a7f, 0xc92b, 0x21, 0 + .dw 0x2ac0, 0xc92b, 0x2aff, 0xc92b, 0x21, 0 + .dw 0x2b40, 0xc92b, 0x2b7f, 0xc92b, 0x21, 0 + .dw 0x2bc0, 0xc92b, 0x2bff, 0xc92b, 0x21, 0 + .dw 0x2c40, 0xc92b, 0x2c7f, 0xc92b, 0x21, 0 + .dw 0x2cc0, 0xc92b, 0x2cff, 0xc92b, 0x21, 0 + .dw 0x2d40, 0xc92b, 0x2d7f, 0xc92b, 0x21, 0 + .dw 0x2dc0, 0xc92b, 0x2dff, 0xc92b, 0x21, 0 + .dw 0x2e40, 0xc92b, 0x2e7f, 0xc92b, 0x21, 0 + .dw 0x2ec0, 0xc92b, 0x2eff, 0xc92b, 0x21, 0 + .dw 0x2f40, 0xc92b, 0x2f7f, 0xc92b, 0x21, 0 + .dw 0x2fc0, 0xc92b, 0x2fff, 0xc92b, 0x21, 0 + .dw 0x3040, 0xc92b, 0x307f, 0xc92b, 0x21, 0 + .dw 0x30c0, 0xc92b, 0x30ff, 0xc92b, 0x21, 0 + .dw 0x3140, 0xc92b, 0x317f, 0xc92b, 0x21, 0 + .dw 0x31c0, 0xc92b, 0x31ff, 0xc92b, 0x21, 0 + .dw 0x3240, 0xc92b, 0x327f, 0xc92b, 0x21, 0 + .dw 0x32c0, 0xc92b, 0x32ff, 0xc92b, 0x21, 0 + .dw 0x3340, 0xc92b, 0x337f, 0xc92b, 0x21, 0 + .dw 0x33c0, 0xc92b, 0x33ff, 0xc92b, 0x21, 0 + .dw 0x3440, 0xc92b, 0x347f, 0xc92b, 0x21, 0 + .dw 0x34c0, 0xc92b, 0x34ff, 0xc92b, 0x21, 0 + .dw 0x3540, 0xc92b, 0x357f, 0xc92b, 0x21, 0 + .dw 0x35c0, 0xc92b, 0x35ff, 0xc92b, 0x21, 0 + .dw 0x3640, 0xc92b, 0x367f, 0xc92b, 0x21, 0 + .dw 0x36c0, 0xc92b, 0x36ff, 0xc92b, 0x21, 0 + .dw 0x3740, 0xc92b, 0x377f, 0xc92b, 0x21, 0 + .dw 0x37c0, 0xc92b, 0x37ff, 0xc92b, 0x21, 0 + .dw 0x3840, 0xc92b, 0x387f, 0xc92b, 0x21, 0 + .dw 0x38c0, 0xc92b, 0x38ff, 0xc92b, 0x21, 0 + .dw 0x3940, 0xc92b, 0x397f, 0xc92b, 0x21, 0 + .dw 0x39c0, 0xc92b, 0xffff, 0xc92b, 0x21, 0 + .dw 0x0040, 0xc92c, 0x007f, 0xc92c, 0x21, 0 + .dw 0x00c0, 0xc92c, 0x00ff, 0xc92c, 0x21, 0 + .dw 0x0140, 0xc92c, 0x017f, 0xc92c, 0x21, 0 + .dw 0x01c0, 0xc92c, 0x01ff, 0xc92c, 0x21, 0 + .dw 0x0240, 0xc92c, 0x027f, 0xc92c, 0x21, 0 + .dw 0x02c0, 0xc92c, 0x02ff, 0xc92c, 0x21, 0 + .dw 0x0340, 0xc92c, 0x037f, 0xc92c, 0x21, 0 + .dw 0x03c0, 0xc92c, 0x03ff, 0xc92c, 0x21, 0 + .dw 0x0440, 0xc92c, 0x047f, 0xc92c, 0x21, 0 + .dw 0x04c0, 0xc92c, 0x04ff, 0xc92c, 0x21, 0 + .dw 0x0540, 0xc92c, 0x057f, 0xc92c, 0x21, 0 + .dw 0x05c0, 0xc92c, 0x05ff, 0xc92c, 0x21, 0 + .dw 0x0640, 0xc92c, 0x067f, 0xc92c, 0x21, 0 + .dw 0x06c0, 0xc92c, 0x06ff, 0xc92c, 0x21, 0 + .dw 0x0740, 0xc92c, 0x077f, 0xc92c, 0x21, 0 + .dw 0x07c0, 0xc92c, 0x07ff, 0xc92c, 0x21, 0 + .dw 0x0840, 0xc92c, 0x087f, 0xc92c, 0x21, 0 + .dw 0x08c0, 0xc92c, 0x08ff, 0xc92c, 0x21, 0 + .dw 0x0940, 0xc92c, 0x097f, 0xc92c, 0x21, 0 + .dw 0x09c0, 0xc92c, 0x09ff, 0xc92c, 0x21, 0 + .dw 0x0a40, 0xc92c, 0x0a7f, 0xc92c, 0x21, 0 + .dw 0x0ac0, 0xc92c, 0x0aff, 0xc92c, 0x21, 0 + .dw 0x0b40, 0xc92c, 0x0b7f, 0xc92c, 0x21, 0 + .dw 0x0bc0, 0xc92c, 0x0bff, 0xc92c, 0x21, 0 + .dw 0x0c40, 0xc92c, 0x0c7f, 0xc92c, 0x21, 0 + .dw 0x0cc0, 0xc92c, 0x0cff, 0xc92c, 0x21, 0 + .dw 0x0d40, 0xc92c, 0x0d7f, 0xc92c, 0x21, 0 + .dw 0x0dc0, 0xc92c, 0x0dff, 0xc92c, 0x21, 0 + .dw 0x0e40, 0xc92c, 0x0e7f, 0xc92c, 0x21, 0 + .dw 0x0ec0, 0xc92c, 0x0eff, 0xc92c, 0x21, 0 + .dw 0x0f40, 0xc92c, 0x0f7f, 0xc92c, 0x21, 0 + .dw 0x0fc0, 0xc92c, 0x0fff, 0xc92c, 0x21, 0 + .dw 0x1040, 0xc92c, 0x107f, 0xc92c, 0x21, 0 + .dw 0x10c0, 0xc92c, 0x10ff, 0xc92c, 0x21, 0 + .dw 0x1140, 0xc92c, 0x117f, 0xc92c, 0x21, 0 + .dw 0x11c0, 0xc92c, 0x11ff, 0xc92c, 0x21, 0 + .dw 0x1240, 0xc92c, 0x127f, 0xc92c, 0x21, 0 + .dw 0x12c0, 0xc92c, 0x12ff, 0xc92c, 0x21, 0 + .dw 0x1340, 0xc92c, 0x137f, 0xc92c, 0x21, 0 + .dw 0x13c0, 0xc92c, 0x13ff, 0xc92c, 0x21, 0 + .dw 0x1440, 0xc92c, 0x147f, 0xc92c, 0x21, 0 + .dw 0x14c0, 0xc92c, 0x14ff, 0xc92c, 0x21, 0 + .dw 0x1540, 0xc92c, 0x157f, 0xc92c, 0x21, 0 + .dw 0x15c0, 0xc92c, 0x15ff, 0xc92c, 0x21, 0 + .dw 0x1640, 0xc92c, 0x167f, 0xc92c, 0x21, 0 + .dw 0x16c0, 0xc92c, 0x16ff, 0xc92c, 0x21, 0 + .dw 0x1740, 0xc92c, 0x177f, 0xc92c, 0x21, 0 + .dw 0x17c0, 0xc92c, 0x17ff, 0xc92c, 0x21, 0 + .dw 0x1840, 0xc92c, 0x187f, 0xc92c, 0x21, 0 + .dw 0x18c0, 0xc92c, 0x18ff, 0xc92c, 0x21, 0 + .dw 0x1940, 0xc92c, 0x197f, 0xc92c, 0x21, 0 + .dw 0x19c0, 0xc92c, 0x1fff, 0xc92c, 0x21, 0 + .dw 0x2040, 0xc92c, 0x207f, 0xc92c, 0x21, 0 + .dw 0x20c0, 0xc92c, 0x20ff, 0xc92c, 0x21, 0 + .dw 0x2140, 0xc92c, 0x217f, 0xc92c, 0x21, 0 + .dw 0x21c0, 0xc92c, 0x21ff, 0xc92c, 0x21, 0 + .dw 0x2240, 0xc92c, 0x227f, 0xc92c, 0x21, 0 + .dw 0x22c0, 0xc92c, 0x22ff, 0xc92c, 0x21, 0 + .dw 0x2340, 0xc92c, 0x237f, 0xc92c, 0x21, 0 + .dw 0x23c0, 0xc92c, 0x23ff, 0xc92c, 0x21, 0 + .dw 0x2440, 0xc92c, 0x247f, 0xc92c, 0x21, 0 + .dw 0x24c0, 0xc92c, 0x24ff, 0xc92c, 0x21, 0 + .dw 0x2540, 0xc92c, 0x257f, 0xc92c, 0x21, 0 + .dw 0x25c0, 0xc92c, 0x25ff, 0xc92c, 0x21, 0 + .dw 0x2640, 0xc92c, 0x267f, 0xc92c, 0x21, 0 + .dw 0x26c0, 0xc92c, 0x26ff, 0xc92c, 0x21, 0 + .dw 0x2740, 0xc92c, 0x277f, 0xc92c, 0x21, 0 + .dw 0x27c0, 0xc92c, 0x27ff, 0xc92c, 0x21, 0 + .dw 0x2840, 0xc92c, 0x287f, 0xc92c, 0x21, 0 + .dw 0x28c0, 0xc92c, 0x28ff, 0xc92c, 0x21, 0 + .dw 0x2940, 0xc92c, 0x297f, 0xc92c, 0x21, 0 + .dw 0x29c0, 0xc92c, 0x29ff, 0xc92c, 0x21, 0 + .dw 0x2a40, 0xc92c, 0x2a7f, 0xc92c, 0x21, 0 + .dw 0x2ac0, 0xc92c, 0x2aff, 0xc92c, 0x21, 0 + .dw 0x2b40, 0xc92c, 0x2b7f, 0xc92c, 0x21, 0 + .dw 0x2bc0, 0xc92c, 0x2bff, 0xc92c, 0x21, 0 + .dw 0x2c40, 0xc92c, 0x2c7f, 0xc92c, 0x21, 0 + .dw 0x2cc0, 0xc92c, 0x2cff, 0xc92c, 0x21, 0 + .dw 0x2d40, 0xc92c, 0x2d7f, 0xc92c, 0x21, 0 + .dw 0x2dc0, 0xc92c, 0x2dff, 0xc92c, 0x21, 0 + .dw 0x2e40, 0xc92c, 0x2e7f, 0xc92c, 0x21, 0 + .dw 0x2ec0, 0xc92c, 0x2eff, 0xc92c, 0x21, 0 + .dw 0x2f40, 0xc92c, 0x2f7f, 0xc92c, 0x21, 0 + .dw 0x2fc0, 0xc92c, 0x2fff, 0xc92c, 0x21, 0 + .dw 0x3040, 0xc92c, 0x307f, 0xc92c, 0x21, 0 + .dw 0x30c0, 0xc92c, 0x30ff, 0xc92c, 0x21, 0 + .dw 0x3140, 0xc92c, 0x317f, 0xc92c, 0x21, 0 + .dw 0x31c0, 0xc92c, 0x31ff, 0xc92c, 0x21, 0 + .dw 0x3240, 0xc92c, 0x327f, 0xc92c, 0x21, 0 + .dw 0x32c0, 0xc92c, 0x32ff, 0xc92c, 0x21, 0 + .dw 0x3340, 0xc92c, 0x337f, 0xc92c, 0x21, 0 + .dw 0x33c0, 0xc92c, 0x33ff, 0xc92c, 0x21, 0 + .dw 0x3440, 0xc92c, 0x347f, 0xc92c, 0x21, 0 + .dw 0x34c0, 0xc92c, 0x34ff, 0xc92c, 0x21, 0 + .dw 0x3540, 0xc92c, 0x357f, 0xc92c, 0x21, 0 + .dw 0x35c0, 0xc92c, 0x35ff, 0xc92c, 0x21, 0 + .dw 0x3640, 0xc92c, 0x367f, 0xc92c, 0x21, 0 + .dw 0x36c0, 0xc92c, 0x36ff, 0xc92c, 0x21, 0 + .dw 0x3740, 0xc92c, 0x377f, 0xc92c, 0x21, 0 + .dw 0x37c0, 0xc92c, 0x37ff, 0xc92c, 0x21, 0 + .dw 0x3840, 0xc92c, 0x387f, 0xc92c, 0x21, 0 + .dw 0x38c0, 0xc92c, 0x38ff, 0xc92c, 0x21, 0 + .dw 0x3940, 0xc92c, 0x397f, 0xc92c, 0x21, 0 + .dw 0x39c0, 0xc92c, 0x3fff, 0xc92c, 0x21, 0 + .dw 0x4040, 0xc92c, 0x407f, 0xc92c, 0x21, 0 + .dw 0x40c0, 0xc92c, 0x40ff, 0xc92c, 0x21, 0 + .dw 0x4140, 0xc92c, 0x417f, 0xc92c, 0x21, 0 + .dw 0x41c0, 0xc92c, 0x41ff, 0xc92c, 0x21, 0 + .dw 0x4240, 0xc92c, 0x427f, 0xc92c, 0x21, 0 + .dw 0x42c0, 0xc92c, 0x42ff, 0xc92c, 0x21, 0 + .dw 0x4340, 0xc92c, 0x437f, 0xc92c, 0x21, 0 + .dw 0x43c0, 0xc92c, 0x43ff, 0xc92c, 0x21, 0 + .dw 0x4440, 0xc92c, 0x447f, 0xc92c, 0x21, 0 + .dw 0x44c0, 0xc92c, 0x44ff, 0xc92c, 0x21, 0 + .dw 0x4540, 0xc92c, 0x457f, 0xc92c, 0x21, 0 + .dw 0x45c0, 0xc92c, 0x45ff, 0xc92c, 0x21, 0 + .dw 0x4640, 0xc92c, 0x467f, 0xc92c, 0x21, 0 + .dw 0x46c0, 0xc92c, 0x46ff, 0xc92c, 0x21, 0 + .dw 0x4740, 0xc92c, 0x477f, 0xc92c, 0x21, 0 + .dw 0x47c0, 0xc92c, 0x47ff, 0xc92c, 0x21, 0 + .dw 0x4840, 0xc92c, 0x487f, 0xc92c, 0x21, 0 + .dw 0x48c0, 0xc92c, 0x48ff, 0xc92c, 0x21, 0 + .dw 0x4940, 0xc92c, 0x497f, 0xc92c, 0x21, 0 + .dw 0x49c0, 0xc92c, 0x49ff, 0xc92c, 0x21, 0 + .dw 0x4a40, 0xc92c, 0x4a7f, 0xc92c, 0x21, 0 + .dw 0x4ac0, 0xc92c, 0x4aff, 0xc92c, 0x21, 0 + .dw 0x4b40, 0xc92c, 0x4b7f, 0xc92c, 0x21, 0 + .dw 0x4bc0, 0xc92c, 0x4bff, 0xc92c, 0x21, 0 + .dw 0x4c40, 0xc92c, 0x4c7f, 0xc92c, 0x21, 0 + .dw 0x4cc0, 0xc92c, 0x4cff, 0xc92c, 0x21, 0 + .dw 0x4d40, 0xc92c, 0x4d7f, 0xc92c, 0x21, 0 + .dw 0x4dc0, 0xc92c, 0x4dff, 0xc92c, 0x21, 0 + .dw 0x4e40, 0xc92c, 0x4e7f, 0xc92c, 0x21, 0 + .dw 0x4ec0, 0xc92c, 0x4eff, 0xc92c, 0x21, 0 + .dw 0x4f40, 0xc92c, 0x4f7f, 0xc92c, 0x21, 0 + .dw 0x4fc0, 0xc92c, 0x4fff, 0xc92c, 0x21, 0 + .dw 0x5040, 0xc92c, 0x507f, 0xc92c, 0x21, 0 + .dw 0x50c0, 0xc92c, 0x50ff, 0xc92c, 0x21, 0 + .dw 0x5140, 0xc92c, 0x517f, 0xc92c, 0x21, 0 + .dw 0x51c0, 0xc92c, 0x51ff, 0xc92c, 0x21, 0 + .dw 0x5240, 0xc92c, 0x527f, 0xc92c, 0x21, 0 + .dw 0x52c0, 0xc92c, 0x52ff, 0xc92c, 0x21, 0 + .dw 0x5340, 0xc92c, 0x537f, 0xc92c, 0x21, 0 + .dw 0x53c0, 0xc92c, 0x53ff, 0xc92c, 0x21, 0 + .dw 0x5440, 0xc92c, 0x547f, 0xc92c, 0x21, 0 + .dw 0x54c0, 0xc92c, 0x54ff, 0xc92c, 0x21, 0 + .dw 0x5540, 0xc92c, 0x557f, 0xc92c, 0x21, 0 + .dw 0x55c0, 0xc92c, 0x55ff, 0xc92c, 0x21, 0 + .dw 0x5640, 0xc92c, 0x567f, 0xc92c, 0x21, 0 + .dw 0x56c0, 0xc92c, 0x56ff, 0xc92c, 0x21, 0 + .dw 0x5740, 0xc92c, 0x577f, 0xc92c, 0x21, 0 + .dw 0x57c0, 0xc92c, 0x57ff, 0xc92c, 0x21, 0 + .dw 0x5840, 0xc92c, 0x587f, 0xc92c, 0x21, 0 + .dw 0x58c0, 0xc92c, 0x58ff, 0xc92c, 0x21, 0 + .dw 0x5940, 0xc92c, 0x597f, 0xc92c, 0x21, 0 + .dw 0x59c0, 0xc92c, 0x5fff, 0xc92c, 0x21, 0 + .dw 0x6040, 0xc92c, 0x607f, 0xc92c, 0x21, 0 + .dw 0x60c0, 0xc92c, 0x60ff, 0xc92c, 0x21, 0 + .dw 0x6140, 0xc92c, 0x617f, 0xc92c, 0x21, 0 + .dw 0x61c0, 0xc92c, 0x61ff, 0xc92c, 0x21, 0 + .dw 0x6240, 0xc92c, 0x627f, 0xc92c, 0x21, 0 + .dw 0x62c0, 0xc92c, 0x62ff, 0xc92c, 0x21, 0 + .dw 0x6340, 0xc92c, 0x637f, 0xc92c, 0x21, 0 + .dw 0x63c0, 0xc92c, 0x63ff, 0xc92c, 0x21, 0 + .dw 0x6440, 0xc92c, 0x647f, 0xc92c, 0x21, 0 + .dw 0x64c0, 0xc92c, 0x64ff, 0xc92c, 0x21, 0 + .dw 0x6540, 0xc92c, 0x657f, 0xc92c, 0x21, 0 + .dw 0x65c0, 0xc92c, 0x65ff, 0xc92c, 0x21, 0 + .dw 0x6640, 0xc92c, 0x667f, 0xc92c, 0x21, 0 + .dw 0x66c0, 0xc92c, 0x66ff, 0xc92c, 0x21, 0 + .dw 0x6740, 0xc92c, 0x677f, 0xc92c, 0x21, 0 + .dw 0x67c0, 0xc92c, 0x67ff, 0xc92c, 0x21, 0 + .dw 0x6840, 0xc92c, 0x687f, 0xc92c, 0x21, 0 + .dw 0x68c0, 0xc92c, 0x68ff, 0xc92c, 0x21, 0 + .dw 0x6940, 0xc92c, 0x697f, 0xc92c, 0x21, 0 + .dw 0x69c0, 0xc92c, 0x69ff, 0xc92c, 0x21, 0 + .dw 0x6a40, 0xc92c, 0x6a7f, 0xc92c, 0x21, 0 + .dw 0x6ac0, 0xc92c, 0x6aff, 0xc92c, 0x21, 0 + .dw 0x6b40, 0xc92c, 0x6b7f, 0xc92c, 0x21, 0 + .dw 0x6bc0, 0xc92c, 0x6bff, 0xc92c, 0x21, 0 + .dw 0x6c40, 0xc92c, 0x6c7f, 0xc92c, 0x21, 0 + .dw 0x6cc0, 0xc92c, 0x6cff, 0xc92c, 0x21, 0 + .dw 0x6d40, 0xc92c, 0x6d7f, 0xc92c, 0x21, 0 + .dw 0x6dc0, 0xc92c, 0x6dff, 0xc92c, 0x21, 0 + .dw 0x6e40, 0xc92c, 0x6e7f, 0xc92c, 0x21, 0 + .dw 0x6ec0, 0xc92c, 0x6eff, 0xc92c, 0x21, 0 + .dw 0x6f40, 0xc92c, 0x6f7f, 0xc92c, 0x21, 0 + .dw 0x6fc0, 0xc92c, 0x6fff, 0xc92c, 0x21, 0 + .dw 0x7040, 0xc92c, 0x707f, 0xc92c, 0x21, 0 + .dw 0x70c0, 0xc92c, 0x70ff, 0xc92c, 0x21, 0 + .dw 0x7140, 0xc92c, 0x717f, 0xc92c, 0x21, 0 + .dw 0x71c0, 0xc92c, 0x71ff, 0xc92c, 0x21, 0 + .dw 0x7240, 0xc92c, 0x727f, 0xc92c, 0x21, 0 + .dw 0x72c0, 0xc92c, 0x72ff, 0xc92c, 0x21, 0 + .dw 0x7340, 0xc92c, 0x737f, 0xc92c, 0x21, 0 + .dw 0x73c0, 0xc92c, 0x73ff, 0xc92c, 0x21, 0 + .dw 0x7440, 0xc92c, 0x747f, 0xc92c, 0x21, 0 + .dw 0x74c0, 0xc92c, 0x74ff, 0xc92c, 0x21, 0 + .dw 0x7540, 0xc92c, 0x757f, 0xc92c, 0x21, 0 + .dw 0x75c0, 0xc92c, 0x75ff, 0xc92c, 0x21, 0 + .dw 0x7640, 0xc92c, 0x767f, 0xc92c, 0x21, 0 + .dw 0x76c0, 0xc92c, 0x76ff, 0xc92c, 0x21, 0 + .dw 0x7740, 0xc92c, 0x777f, 0xc92c, 0x21, 0 + .dw 0x77c0, 0xc92c, 0x77ff, 0xc92c, 0x21, 0 + .dw 0x7840, 0xc92c, 0x787f, 0xc92c, 0x21, 0 + .dw 0x78c0, 0xc92c, 0x78ff, 0xc92c, 0x21, 0 + .dw 0x7940, 0xc92c, 0x797f, 0xc92c, 0x21, 0 + .dw 0x79c0, 0xc92c, 0x7fff, 0xc92c, 0x21, 0 + .dw 0x8040, 0xc92c, 0x807f, 0xc92c, 0x21, 0 + .dw 0x80c0, 0xc92c, 0x80ff, 0xc92c, 0x21, 0 + .dw 0x8140, 0xc92c, 0x817f, 0xc92c, 0x21, 0 + .dw 0x81c0, 0xc92c, 0x81ff, 0xc92c, 0x21, 0 + .dw 0x8240, 0xc92c, 0x827f, 0xc92c, 0x21, 0 + .dw 0x82c0, 0xc92c, 0x82ff, 0xc92c, 0x21, 0 + .dw 0x8340, 0xc92c, 0x837f, 0xc92c, 0x21, 0 + .dw 0x83c0, 0xc92c, 0x83ff, 0xc92c, 0x21, 0 + .dw 0x8440, 0xc92c, 0x847f, 0xc92c, 0x21, 0 + .dw 0x84c0, 0xc92c, 0x84ff, 0xc92c, 0x21, 0 + .dw 0x8540, 0xc92c, 0x857f, 0xc92c, 0x21, 0 + .dw 0x85c0, 0xc92c, 0x85ff, 0xc92c, 0x21, 0 + .dw 0x8640, 0xc92c, 0x867f, 0xc92c, 0x21, 0 + .dw 0x86c0, 0xc92c, 0x86ff, 0xc92c, 0x21, 0 + .dw 0x8740, 0xc92c, 0x877f, 0xc92c, 0x21, 0 + .dw 0x87c0, 0xc92c, 0x87ff, 0xc92c, 0x21, 0 + .dw 0x8840, 0xc92c, 0x887f, 0xc92c, 0x21, 0 + .dw 0x88c0, 0xc92c, 0x88ff, 0xc92c, 0x21, 0 + .dw 0x8940, 0xc92c, 0x897f, 0xc92c, 0x21, 0 + .dw 0x89c0, 0xc92c, 0x89ff, 0xc92c, 0x21, 0 + .dw 0x8a40, 0xc92c, 0x8a7f, 0xc92c, 0x21, 0 + .dw 0x8ac0, 0xc92c, 0x8aff, 0xc92c, 0x21, 0 + .dw 0x8b40, 0xc92c, 0x8b7f, 0xc92c, 0x21, 0 + .dw 0x8bc0, 0xc92c, 0x8bff, 0xc92c, 0x21, 0 + .dw 0x8c40, 0xc92c, 0x8c7f, 0xc92c, 0x21, 0 + .dw 0x8cc0, 0xc92c, 0x8cff, 0xc92c, 0x21, 0 + .dw 0x8d40, 0xc92c, 0x8d7f, 0xc92c, 0x21, 0 + .dw 0x8dc0, 0xc92c, 0x8dff, 0xc92c, 0x21, 0 + .dw 0x8e40, 0xc92c, 0x8e7f, 0xc92c, 0x21, 0 + .dw 0x8ec0, 0xc92c, 0x8eff, 0xc92c, 0x21, 0 + .dw 0x8f40, 0xc92c, 0x8f7f, 0xc92c, 0x21, 0 + .dw 0x8fc0, 0xc92c, 0x8fff, 0xc92c, 0x21, 0 + .dw 0x9040, 0xc92c, 0x907f, 0xc92c, 0x21, 0 + .dw 0x90c0, 0xc92c, 0x90ff, 0xc92c, 0x21, 0 + .dw 0x9140, 0xc92c, 0x917f, 0xc92c, 0x21, 0 + .dw 0x91c0, 0xc92c, 0x91ff, 0xc92c, 0x21, 0 + .dw 0x9240, 0xc92c, 0x927f, 0xc92c, 0x21, 0 + .dw 0x92c0, 0xc92c, 0x92ff, 0xc92c, 0x21, 0 + .dw 0x9340, 0xc92c, 0x937f, 0xc92c, 0x21, 0 + .dw 0x93c0, 0xc92c, 0x93ff, 0xc92c, 0x21, 0 + .dw 0x9440, 0xc92c, 0x947f, 0xc92c, 0x21, 0 + .dw 0x94c0, 0xc92c, 0x94ff, 0xc92c, 0x21, 0 + .dw 0x9540, 0xc92c, 0x957f, 0xc92c, 0x21, 0 + .dw 0x95c0, 0xc92c, 0x95ff, 0xc92c, 0x21, 0 + .dw 0x9640, 0xc92c, 0x967f, 0xc92c, 0x21, 0 + .dw 0x96c0, 0xc92c, 0x96ff, 0xc92c, 0x21, 0 + .dw 0x9740, 0xc92c, 0x977f, 0xc92c, 0x21, 0 + .dw 0x97c0, 0xc92c, 0x97ff, 0xc92c, 0x21, 0 + .dw 0x9840, 0xc92c, 0x987f, 0xc92c, 0x21, 0 + .dw 0x98c0, 0xc92c, 0x98ff, 0xc92c, 0x21, 0 + .dw 0x9940, 0xc92c, 0x997f, 0xc92c, 0x21, 0 + .dw 0x99c0, 0xc92c, 0x9fff, 0xc92c, 0x21, 0 + .dw 0xa040, 0xc92c, 0xa07f, 0xc92c, 0x21, 0 + .dw 0xa0c0, 0xc92c, 0xa0ff, 0xc92c, 0x21, 0 + .dw 0xa140, 0xc92c, 0xa17f, 0xc92c, 0x21, 0 + .dw 0xa1c0, 0xc92c, 0xa1ff, 0xc92c, 0x21, 0 + .dw 0xa240, 0xc92c, 0xa27f, 0xc92c, 0x21, 0 + .dw 0xa2c0, 0xc92c, 0xa2ff, 0xc92c, 0x21, 0 + .dw 0xa340, 0xc92c, 0xa37f, 0xc92c, 0x21, 0 + .dw 0xa3c0, 0xc92c, 0xa3ff, 0xc92c, 0x21, 0 + .dw 0xa440, 0xc92c, 0xa47f, 0xc92c, 0x21, 0 + .dw 0xa4c0, 0xc92c, 0xa4ff, 0xc92c, 0x21, 0 + .dw 0xa540, 0xc92c, 0xa57f, 0xc92c, 0x21, 0 + .dw 0xa5c0, 0xc92c, 0xa5ff, 0xc92c, 0x21, 0 + .dw 0xa640, 0xc92c, 0xa67f, 0xc92c, 0x21, 0 + .dw 0xa6c0, 0xc92c, 0xa6ff, 0xc92c, 0x21, 0 + .dw 0xa740, 0xc92c, 0xa77f, 0xc92c, 0x21, 0 + .dw 0xa7c0, 0xc92c, 0xa7ff, 0xc92c, 0x21, 0 + .dw 0xa840, 0xc92c, 0xa87f, 0xc92c, 0x21, 0 + .dw 0xa8c0, 0xc92c, 0xa8ff, 0xc92c, 0x21, 0 + .dw 0xa940, 0xc92c, 0xa97f, 0xc92c, 0x21, 0 + .dw 0xa9c0, 0xc92c, 0xa9ff, 0xc92c, 0x21, 0 + .dw 0xaa40, 0xc92c, 0xaa7f, 0xc92c, 0x21, 0 + .dw 0xaac0, 0xc92c, 0xaaff, 0xc92c, 0x21, 0 + .dw 0xab40, 0xc92c, 0xab7f, 0xc92c, 0x21, 0 + .dw 0xabc0, 0xc92c, 0xabff, 0xc92c, 0x21, 0 + .dw 0xac40, 0xc92c, 0xac7f, 0xc92c, 0x21, 0 + .dw 0xacc0, 0xc92c, 0xacff, 0xc92c, 0x21, 0 + .dw 0xad40, 0xc92c, 0xad7f, 0xc92c, 0x21, 0 + .dw 0xadc0, 0xc92c, 0xadff, 0xc92c, 0x21, 0 + .dw 0xae40, 0xc92c, 0xae7f, 0xc92c, 0x21, 0 + .dw 0xaec0, 0xc92c, 0xaeff, 0xc92c, 0x21, 0 + .dw 0xaf40, 0xc92c, 0xaf7f, 0xc92c, 0x21, 0 + .dw 0xafc0, 0xc92c, 0xafff, 0xc92c, 0x21, 0 + .dw 0xb040, 0xc92c, 0xb07f, 0xc92c, 0x21, 0 + .dw 0xb0c0, 0xc92c, 0xb0ff, 0xc92c, 0x21, 0 + .dw 0xb140, 0xc92c, 0xb17f, 0xc92c, 0x21, 0 + .dw 0xb1c0, 0xc92c, 0xb1ff, 0xc92c, 0x21, 0 + .dw 0xb240, 0xc92c, 0xb27f, 0xc92c, 0x21, 0 + .dw 0xb2c0, 0xc92c, 0xb2ff, 0xc92c, 0x21, 0 + .dw 0xb340, 0xc92c, 0xb37f, 0xc92c, 0x21, 0 + .dw 0xb3c0, 0xc92c, 0xb3ff, 0xc92c, 0x21, 0 + .dw 0xb440, 0xc92c, 0xb47f, 0xc92c, 0x21, 0 + .dw 0xb4c0, 0xc92c, 0xb4ff, 0xc92c, 0x21, 0 + .dw 0xb540, 0xc92c, 0xb57f, 0xc92c, 0x21, 0 + .dw 0xb5c0, 0xc92c, 0xb5ff, 0xc92c, 0x21, 0 + .dw 0xb640, 0xc92c, 0xb67f, 0xc92c, 0x21, 0 + .dw 0xb6c0, 0xc92c, 0xb6ff, 0xc92c, 0x21, 0 + .dw 0xb740, 0xc92c, 0xb77f, 0xc92c, 0x21, 0 + .dw 0xb7c0, 0xc92c, 0xb7ff, 0xc92c, 0x21, 0 + .dw 0xb840, 0xc92c, 0xb87f, 0xc92c, 0x21, 0 + .dw 0xb8c0, 0xc92c, 0xb8ff, 0xc92c, 0x21, 0 + .dw 0xb940, 0xc92c, 0xb97f, 0xc92c, 0x21, 0 + .dw 0xb9c0, 0xc92c, 0xbfff, 0xc92c, 0x21, 0 + .dw 0xc040, 0xc92c, 0xc07f, 0xc92c, 0x21, 0 + .dw 0xc0c0, 0xc92c, 0xc0ff, 0xc92c, 0x21, 0 + .dw 0xc140, 0xc92c, 0xc17f, 0xc92c, 0x21, 0 + .dw 0xc1c0, 0xc92c, 0xc1ff, 0xc92c, 0x21, 0 + .dw 0xc240, 0xc92c, 0xc27f, 0xc92c, 0x21, 0 + .dw 0xc2c0, 0xc92c, 0xc2ff, 0xc92c, 0x21, 0 + .dw 0xc340, 0xc92c, 0xc37f, 0xc92c, 0x21, 0 + .dw 0xc3c0, 0xc92c, 0xc3ff, 0xc92c, 0x21, 0 + .dw 0xc440, 0xc92c, 0xc47f, 0xc92c, 0x21, 0 + .dw 0xc4c0, 0xc92c, 0xc4ff, 0xc92c, 0x21, 0 + .dw 0xc540, 0xc92c, 0xc57f, 0xc92c, 0x21, 0 + .dw 0xc5c0, 0xc92c, 0xc5ff, 0xc92c, 0x21, 0 + .dw 0xc640, 0xc92c, 0xc67f, 0xc92c, 0x21, 0 + .dw 0xc6c0, 0xc92c, 0xc6ff, 0xc92c, 0x21, 0 + .dw 0xc740, 0xc92c, 0xc77f, 0xc92c, 0x21, 0 + .dw 0xc7c0, 0xc92c, 0xc7ff, 0xc92c, 0x21, 0 + .dw 0xc840, 0xc92c, 0xc87f, 0xc92c, 0x21, 0 + .dw 0xc8c0, 0xc92c, 0xc8ff, 0xc92c, 0x21, 0 + .dw 0xc940, 0xc92c, 0xc97f, 0xc92c, 0x21, 0 + .dw 0xc9c0, 0xc92c, 0xc9ff, 0xc92c, 0x21, 0 + .dw 0xca40, 0xc92c, 0xca7f, 0xc92c, 0x21, 0 + .dw 0xcac0, 0xc92c, 0xcaff, 0xc92c, 0x21, 0 + .dw 0xcb40, 0xc92c, 0xcb7f, 0xc92c, 0x21, 0 + .dw 0xcbc0, 0xc92c, 0xcbff, 0xc92c, 0x21, 0 + .dw 0xcc40, 0xc92c, 0xcc7f, 0xc92c, 0x21, 0 + .dw 0xccc0, 0xc92c, 0xccff, 0xc92c, 0x21, 0 + .dw 0xcd40, 0xc92c, 0xcd7f, 0xc92c, 0x21, 0 + .dw 0xcdc0, 0xc92c, 0xcdff, 0xc92c, 0x21, 0 + .dw 0xce40, 0xc92c, 0xce7f, 0xc92c, 0x21, 0 + .dw 0xcec0, 0xc92c, 0xceff, 0xc92c, 0x21, 0 + .dw 0xcf40, 0xc92c, 0xcf7f, 0xc92c, 0x21, 0 + .dw 0xcfc0, 0xc92c, 0xcfff, 0xc92c, 0x21, 0 + .dw 0xd040, 0xc92c, 0xd07f, 0xc92c, 0x21, 0 + .dw 0xd0c0, 0xc92c, 0xd0ff, 0xc92c, 0x21, 0 + .dw 0xd140, 0xc92c, 0xd17f, 0xc92c, 0x21, 0 + .dw 0xd1c0, 0xc92c, 0xd1ff, 0xc92c, 0x21, 0 + .dw 0xd240, 0xc92c, 0xd27f, 0xc92c, 0x21, 0 + .dw 0xd2c0, 0xc92c, 0xd2ff, 0xc92c, 0x21, 0 + .dw 0xd340, 0xc92c, 0xd37f, 0xc92c, 0x21, 0 + .dw 0xd3c0, 0xc92c, 0xd3ff, 0xc92c, 0x21, 0 + .dw 0xd440, 0xc92c, 0xd47f, 0xc92c, 0x21, 0 + .dw 0xd4c0, 0xc92c, 0xd4ff, 0xc92c, 0x21, 0 + .dw 0xd540, 0xc92c, 0xd57f, 0xc92c, 0x21, 0 + .dw 0xd5c0, 0xc92c, 0xd5ff, 0xc92c, 0x21, 0 + .dw 0xd640, 0xc92c, 0xd67f, 0xc92c, 0x21, 0 + .dw 0xd6c0, 0xc92c, 0xd6ff, 0xc92c, 0x21, 0 + .dw 0xd740, 0xc92c, 0xd77f, 0xc92c, 0x21, 0 + .dw 0xd7c0, 0xc92c, 0xd7ff, 0xc92c, 0x21, 0 + .dw 0xd840, 0xc92c, 0xd87f, 0xc92c, 0x21, 0 + .dw 0xd8c0, 0xc92c, 0xd8ff, 0xc92c, 0x21, 0 + .dw 0xd940, 0xc92c, 0xd97f, 0xc92c, 0x21, 0 + .dw 0xd9c0, 0xc92c, 0xdfff, 0xc92c, 0x21, 0 + .dw 0xe040, 0xc92c, 0xe07f, 0xc92c, 0x21, 0 + .dw 0xe0c0, 0xc92c, 0xe0ff, 0xc92c, 0x21, 0 + .dw 0xe140, 0xc92c, 0xe17f, 0xc92c, 0x21, 0 + .dw 0xe1c0, 0xc92c, 0xe1ff, 0xc92c, 0x21, 0 + .dw 0xe240, 0xc92c, 0xe27f, 0xc92c, 0x21, 0 + .dw 0xe2c0, 0xc92c, 0xe2ff, 0xc92c, 0x21, 0 + .dw 0xe340, 0xc92c, 0xe37f, 0xc92c, 0x21, 0 + .dw 0xe3c0, 0xc92c, 0xe3ff, 0xc92c, 0x21, 0 + .dw 0xe440, 0xc92c, 0xe47f, 0xc92c, 0x21, 0 + .dw 0xe4c0, 0xc92c, 0xe4ff, 0xc92c, 0x21, 0 + .dw 0xe540, 0xc92c, 0xe57f, 0xc92c, 0x21, 0 + .dw 0xe5c0, 0xc92c, 0xe5ff, 0xc92c, 0x21, 0 + .dw 0xe640, 0xc92c, 0xe67f, 0xc92c, 0x21, 0 + .dw 0xe6c0, 0xc92c, 0xe6ff, 0xc92c, 0x21, 0 + .dw 0xe740, 0xc92c, 0xe77f, 0xc92c, 0x21, 0 + .dw 0xe7c0, 0xc92c, 0xe7ff, 0xc92c, 0x21, 0 + .dw 0xe840, 0xc92c, 0xe87f, 0xc92c, 0x21, 0 + .dw 0xe8c0, 0xc92c, 0xe8ff, 0xc92c, 0x21, 0 + .dw 0xe940, 0xc92c, 0xe97f, 0xc92c, 0x21, 0 + .dw 0xe9c0, 0xc92c, 0xe9ff, 0xc92c, 0x21, 0 + .dw 0xea40, 0xc92c, 0xea7f, 0xc92c, 0x21, 0 + .dw 0xeac0, 0xc92c, 0xeaff, 0xc92c, 0x21, 0 + .dw 0xeb40, 0xc92c, 0xeb7f, 0xc92c, 0x21, 0 + .dw 0xebc0, 0xc92c, 0xebff, 0xc92c, 0x21, 0 + .dw 0xec40, 0xc92c, 0xec7f, 0xc92c, 0x21, 0 + .dw 0xecc0, 0xc92c, 0xecff, 0xc92c, 0x21, 0 + .dw 0xed40, 0xc92c, 0xed7f, 0xc92c, 0x21, 0 + .dw 0xedc0, 0xc92c, 0xedff, 0xc92c, 0x21, 0 + .dw 0xee40, 0xc92c, 0xee7f, 0xc92c, 0x21, 0 + .dw 0xeec0, 0xc92c, 0xeeff, 0xc92c, 0x21, 0 + .dw 0xef40, 0xc92c, 0xef7f, 0xc92c, 0x21, 0 + .dw 0xefc0, 0xc92c, 0xefff, 0xc92c, 0x21, 0 + .dw 0xf040, 0xc92c, 0xf07f, 0xc92c, 0x21, 0 + .dw 0xf0c0, 0xc92c, 0xf0ff, 0xc92c, 0x21, 0 + .dw 0xf140, 0xc92c, 0xf17f, 0xc92c, 0x21, 0 + .dw 0xf1c0, 0xc92c, 0xf1ff, 0xc92c, 0x21, 0 + .dw 0xf240, 0xc92c, 0xf27f, 0xc92c, 0x21, 0 + .dw 0xf2c0, 0xc92c, 0xf2ff, 0xc92c, 0x21, 0 + .dw 0xf340, 0xc92c, 0xf37f, 0xc92c, 0x21, 0 + .dw 0xf3c0, 0xc92c, 0xf3ff, 0xc92c, 0x21, 0 + .dw 0xf440, 0xc92c, 0xf47f, 0xc92c, 0x21, 0 + .dw 0xf4c0, 0xc92c, 0xf4ff, 0xc92c, 0x21, 0 + .dw 0xf540, 0xc92c, 0xf57f, 0xc92c, 0x21, 0 + .dw 0xf5c0, 0xc92c, 0xf5ff, 0xc92c, 0x21, 0 + .dw 0xf640, 0xc92c, 0xf67f, 0xc92c, 0x21, 0 + .dw 0xf6c0, 0xc92c, 0xf6ff, 0xc92c, 0x21, 0 + .dw 0xf740, 0xc92c, 0xf77f, 0xc92c, 0x21, 0 + .dw 0xf7c0, 0xc92c, 0xf7ff, 0xc92c, 0x21, 0 + .dw 0xf840, 0xc92c, 0xf87f, 0xc92c, 0x21, 0 + .dw 0xf8c0, 0xc92c, 0xf8ff, 0xc92c, 0x21, 0 + .dw 0xf940, 0xc92c, 0xf97f, 0xc92c, 0x21, 0 + .dw 0xf9c0, 0xc92c, 0xffff, 0xc92c, 0x21, 0 + .dw 0x0040, 0xc92d, 0x007f, 0xc92d, 0x21, 0 + .dw 0x00c0, 0xc92d, 0x00ff, 0xc92d, 0x21, 0 + .dw 0x0140, 0xc92d, 0x017f, 0xc92d, 0x21, 0 + .dw 0x01c0, 0xc92d, 0x01ff, 0xc92d, 0x21, 0 + .dw 0x0240, 0xc92d, 0x027f, 0xc92d, 0x21, 0 + .dw 0x02c0, 0xc92d, 0x02ff, 0xc92d, 0x21, 0 + .dw 0x0340, 0xc92d, 0x037f, 0xc92d, 0x21, 0 + .dw 0x03c0, 0xc92d, 0x03ff, 0xc92d, 0x21, 0 + .dw 0x0440, 0xc92d, 0x047f, 0xc92d, 0x21, 0 + .dw 0x04c0, 0xc92d, 0x04ff, 0xc92d, 0x21, 0 + .dw 0x0540, 0xc92d, 0x057f, 0xc92d, 0x21, 0 + .dw 0x05c0, 0xc92d, 0x05ff, 0xc92d, 0x21, 0 + .dw 0x0640, 0xc92d, 0x067f, 0xc92d, 0x21, 0 + .dw 0x06c0, 0xc92d, 0x06ff, 0xc92d, 0x21, 0 + .dw 0x0740, 0xc92d, 0x077f, 0xc92d, 0x21, 0 + .dw 0x07c0, 0xc92d, 0x07ff, 0xc92d, 0x21, 0 + .dw 0x0840, 0xc92d, 0x087f, 0xc92d, 0x21, 0 + .dw 0x08c0, 0xc92d, 0x08ff, 0xc92d, 0x21, 0 + .dw 0x0940, 0xc92d, 0x097f, 0xc92d, 0x21, 0 + .dw 0x09c0, 0xc92d, 0x09ff, 0xc92d, 0x21, 0 + .dw 0x0a40, 0xc92d, 0x0a7f, 0xc92d, 0x21, 0 + .dw 0x0ac0, 0xc92d, 0x0aff, 0xc92d, 0x21, 0 + .dw 0x0b40, 0xc92d, 0x0b7f, 0xc92d, 0x21, 0 + .dw 0x0bc0, 0xc92d, 0x0bff, 0xc92d, 0x21, 0 + .dw 0x0c40, 0xc92d, 0x0c7f, 0xc92d, 0x21, 0 + .dw 0x0cc0, 0xc92d, 0x0cff, 0xc92d, 0x21, 0 + .dw 0x0d40, 0xc92d, 0x0d7f, 0xc92d, 0x21, 0 + .dw 0x0dc0, 0xc92d, 0x0dff, 0xc92d, 0x21, 0 + .dw 0x0e40, 0xc92d, 0x0e7f, 0xc92d, 0x21, 0 + .dw 0x0ec0, 0xc92d, 0x0eff, 0xc92d, 0x21, 0 + .dw 0x0f40, 0xc92d, 0x0f7f, 0xc92d, 0x21, 0 + .dw 0x0fc0, 0xc92d, 0x0fff, 0xc92d, 0x21, 0 + .dw 0x1040, 0xc92d, 0x107f, 0xc92d, 0x21, 0 + .dw 0x10c0, 0xc92d, 0x10ff, 0xc92d, 0x21, 0 + .dw 0x1140, 0xc92d, 0x117f, 0xc92d, 0x21, 0 + .dw 0x11c0, 0xc92d, 0x11ff, 0xc92d, 0x21, 0 + .dw 0x1240, 0xc92d, 0x127f, 0xc92d, 0x21, 0 + .dw 0x12c0, 0xc92d, 0x12ff, 0xc92d, 0x21, 0 + .dw 0x1340, 0xc92d, 0x137f, 0xc92d, 0x21, 0 + .dw 0x13c0, 0xc92d, 0x13ff, 0xc92d, 0x21, 0 + .dw 0x1440, 0xc92d, 0x147f, 0xc92d, 0x21, 0 + .dw 0x14c0, 0xc92d, 0x14ff, 0xc92d, 0x21, 0 + .dw 0x1540, 0xc92d, 0x157f, 0xc92d, 0x21, 0 + .dw 0x15c0, 0xc92d, 0x15ff, 0xc92d, 0x21, 0 + .dw 0x1640, 0xc92d, 0x167f, 0xc92d, 0x21, 0 + .dw 0x16c0, 0xc92d, 0x16ff, 0xc92d, 0x21, 0 + .dw 0x1740, 0xc92d, 0x177f, 0xc92d, 0x21, 0 + .dw 0x17c0, 0xc92d, 0x17ff, 0xc92d, 0x21, 0 + .dw 0x1840, 0xc92d, 0x187f, 0xc92d, 0x21, 0 + .dw 0x18c0, 0xc92d, 0x18ff, 0xc92d, 0x21, 0 + .dw 0x1940, 0xc92d, 0x197f, 0xc92d, 0x21, 0 + .dw 0x19c0, 0xc92d, 0x1fff, 0xc92d, 0x21, 0 + .dw 0x2040, 0xc92d, 0x207f, 0xc92d, 0x21, 0 + .dw 0x20c0, 0xc92d, 0x20ff, 0xc92d, 0x21, 0 + .dw 0x2140, 0xc92d, 0x217f, 0xc92d, 0x21, 0 + .dw 0x21c0, 0xc92d, 0x21ff, 0xc92d, 0x21, 0 + .dw 0x2240, 0xc92d, 0x227f, 0xc92d, 0x21, 0 + .dw 0x22c0, 0xc92d, 0x22ff, 0xc92d, 0x21, 0 + .dw 0x2340, 0xc92d, 0x237f, 0xc92d, 0x21, 0 + .dw 0x23c0, 0xc92d, 0x23ff, 0xc92d, 0x21, 0 + .dw 0x2440, 0xc92d, 0x247f, 0xc92d, 0x21, 0 + .dw 0x24c0, 0xc92d, 0x24ff, 0xc92d, 0x21, 0 + .dw 0x2540, 0xc92d, 0x257f, 0xc92d, 0x21, 0 + .dw 0x25c0, 0xc92d, 0x25ff, 0xc92d, 0x21, 0 + .dw 0x2640, 0xc92d, 0x267f, 0xc92d, 0x21, 0 + .dw 0x26c0, 0xc92d, 0x26ff, 0xc92d, 0x21, 0 + .dw 0x2740, 0xc92d, 0x277f, 0xc92d, 0x21, 0 + .dw 0x27c0, 0xc92d, 0x27ff, 0xc92d, 0x21, 0 + .dw 0x2840, 0xc92d, 0x287f, 0xc92d, 0x21, 0 + .dw 0x28c0, 0xc92d, 0x28ff, 0xc92d, 0x21, 0 + .dw 0x2940, 0xc92d, 0x297f, 0xc92d, 0x21, 0 + .dw 0x29c0, 0xc92d, 0x29ff, 0xc92d, 0x21, 0 + .dw 0x2a40, 0xc92d, 0x2a7f, 0xc92d, 0x21, 0 + .dw 0x2ac0, 0xc92d, 0x2aff, 0xc92d, 0x21, 0 + .dw 0x2b40, 0xc92d, 0x2b7f, 0xc92d, 0x21, 0 + .dw 0x2bc0, 0xc92d, 0x2bff, 0xc92d, 0x21, 0 + .dw 0x2c40, 0xc92d, 0x2c7f, 0xc92d, 0x21, 0 + .dw 0x2cc0, 0xc92d, 0x2cff, 0xc92d, 0x21, 0 + .dw 0x2d40, 0xc92d, 0x2d7f, 0xc92d, 0x21, 0 + .dw 0x2dc0, 0xc92d, 0x2dff, 0xc92d, 0x21, 0 + .dw 0x2e40, 0xc92d, 0x2e7f, 0xc92d, 0x21, 0 + .dw 0x2ec0, 0xc92d, 0x2eff, 0xc92d, 0x21, 0 + .dw 0x2f40, 0xc92d, 0x2f7f, 0xc92d, 0x21, 0 + .dw 0x2fc0, 0xc92d, 0x2fff, 0xc92d, 0x21, 0 + .dw 0x3040, 0xc92d, 0x307f, 0xc92d, 0x21, 0 + .dw 0x30c0, 0xc92d, 0x30ff, 0xc92d, 0x21, 0 + .dw 0x3140, 0xc92d, 0x317f, 0xc92d, 0x21, 0 + .dw 0x31c0, 0xc92d, 0x31ff, 0xc92d, 0x21, 0 + .dw 0x3240, 0xc92d, 0x327f, 0xc92d, 0x21, 0 + .dw 0x32c0, 0xc92d, 0x32ff, 0xc92d, 0x21, 0 + .dw 0x3340, 0xc92d, 0x337f, 0xc92d, 0x21, 0 + .dw 0x33c0, 0xc92d, 0x33ff, 0xc92d, 0x21, 0 + .dw 0x3440, 0xc92d, 0x347f, 0xc92d, 0x21, 0 + .dw 0x34c0, 0xc92d, 0x34ff, 0xc92d, 0x21, 0 + .dw 0x3540, 0xc92d, 0x357f, 0xc92d, 0x21, 0 + .dw 0x35c0, 0xc92d, 0x35ff, 0xc92d, 0x21, 0 + .dw 0x3640, 0xc92d, 0x367f, 0xc92d, 0x21, 0 + .dw 0x36c0, 0xc92d, 0x36ff, 0xc92d, 0x21, 0 + .dw 0x3740, 0xc92d, 0x377f, 0xc92d, 0x21, 0 + .dw 0x37c0, 0xc92d, 0x37ff, 0xc92d, 0x21, 0 + .dw 0x3840, 0xc92d, 0x387f, 0xc92d, 0x21, 0 + .dw 0x38c0, 0xc92d, 0x38ff, 0xc92d, 0x21, 0 + .dw 0x3940, 0xc92d, 0x397f, 0xc92d, 0x21, 0 + .dw 0x39c0, 0xc92d, 0x3fff, 0xc92d, 0x21, 0 + .dw 0x4040, 0xc92d, 0x407f, 0xc92d, 0x21, 0 + .dw 0x40c0, 0xc92d, 0x40ff, 0xc92d, 0x21, 0 + .dw 0x4140, 0xc92d, 0x417f, 0xc92d, 0x21, 0 + .dw 0x41c0, 0xc92d, 0x41ff, 0xc92d, 0x21, 0 + .dw 0x4240, 0xc92d, 0x427f, 0xc92d, 0x21, 0 + .dw 0x42c0, 0xc92d, 0x42ff, 0xc92d, 0x21, 0 + .dw 0x4340, 0xc92d, 0x437f, 0xc92d, 0x21, 0 + .dw 0x43c0, 0xc92d, 0x43ff, 0xc92d, 0x21, 0 + .dw 0x4440, 0xc92d, 0x447f, 0xc92d, 0x21, 0 + .dw 0x44c0, 0xc92d, 0x44ff, 0xc92d, 0x21, 0 + .dw 0x4540, 0xc92d, 0x457f, 0xc92d, 0x21, 0 + .dw 0x45c0, 0xc92d, 0x45ff, 0xc92d, 0x21, 0 + .dw 0x4640, 0xc92d, 0x467f, 0xc92d, 0x21, 0 + .dw 0x46c0, 0xc92d, 0x46ff, 0xc92d, 0x21, 0 + .dw 0x4740, 0xc92d, 0x477f, 0xc92d, 0x21, 0 + .dw 0x47c0, 0xc92d, 0x47ff, 0xc92d, 0x21, 0 + .dw 0x4840, 0xc92d, 0x487f, 0xc92d, 0x21, 0 + .dw 0x48c0, 0xc92d, 0x48ff, 0xc92d, 0x21, 0 + .dw 0x4940, 0xc92d, 0x497f, 0xc92d, 0x21, 0 + .dw 0x49c0, 0xc92d, 0x49ff, 0xc92d, 0x21, 0 + .dw 0x4a40, 0xc92d, 0x4a7f, 0xc92d, 0x21, 0 + .dw 0x4ac0, 0xc92d, 0x4aff, 0xc92d, 0x21, 0 + .dw 0x4b40, 0xc92d, 0x4b7f, 0xc92d, 0x21, 0 + .dw 0x4bc0, 0xc92d, 0x4bff, 0xc92d, 0x21, 0 + .dw 0x4c40, 0xc92d, 0x4c7f, 0xc92d, 0x21, 0 + .dw 0x4cc0, 0xc92d, 0x4cff, 0xc92d, 0x21, 0 + .dw 0x4d40, 0xc92d, 0x4d7f, 0xc92d, 0x21, 0 + .dw 0x4dc0, 0xc92d, 0x4dff, 0xc92d, 0x21, 0 + .dw 0x4e40, 0xc92d, 0x4e7f, 0xc92d, 0x21, 0 + .dw 0x4ec0, 0xc92d, 0x4eff, 0xc92d, 0x21, 0 + .dw 0x4f40, 0xc92d, 0x4f7f, 0xc92d, 0x21, 0 + .dw 0x4fc0, 0xc92d, 0x4fff, 0xc92d, 0x21, 0 + .dw 0x5040, 0xc92d, 0x507f, 0xc92d, 0x21, 0 + .dw 0x50c0, 0xc92d, 0x50ff, 0xc92d, 0x21, 0 + .dw 0x5140, 0xc92d, 0x517f, 0xc92d, 0x21, 0 + .dw 0x51c0, 0xc92d, 0x51ff, 0xc92d, 0x21, 0 + .dw 0x5240, 0xc92d, 0x527f, 0xc92d, 0x21, 0 + .dw 0x52c0, 0xc92d, 0x52ff, 0xc92d, 0x21, 0 + .dw 0x5340, 0xc92d, 0x537f, 0xc92d, 0x21, 0 + .dw 0x53c0, 0xc92d, 0x53ff, 0xc92d, 0x21, 0 + .dw 0x5440, 0xc92d, 0x547f, 0xc92d, 0x21, 0 + .dw 0x54c0, 0xc92d, 0x54ff, 0xc92d, 0x21, 0 + .dw 0x5540, 0xc92d, 0x557f, 0xc92d, 0x21, 0 + .dw 0x55c0, 0xc92d, 0x55ff, 0xc92d, 0x21, 0 + .dw 0x5640, 0xc92d, 0x567f, 0xc92d, 0x21, 0 + .dw 0x56c0, 0xc92d, 0x56ff, 0xc92d, 0x21, 0 + .dw 0x5740, 0xc92d, 0x577f, 0xc92d, 0x21, 0 + .dw 0x57c0, 0xc92d, 0x57ff, 0xc92d, 0x21, 0 + .dw 0x5840, 0xc92d, 0x587f, 0xc92d, 0x21, 0 + .dw 0x58c0, 0xc92d, 0x58ff, 0xc92d, 0x21, 0 + .dw 0x5940, 0xc92d, 0x597f, 0xc92d, 0x21, 0 + .dw 0x59c0, 0xc92d, 0x5fff, 0xc92d, 0x21, 0 + .dw 0x6040, 0xc92d, 0x607f, 0xc92d, 0x21, 0 + .dw 0x60c0, 0xc92d, 0x60ff, 0xc92d, 0x21, 0 + .dw 0x6140, 0xc92d, 0x617f, 0xc92d, 0x21, 0 + .dw 0x61c0, 0xc92d, 0x61ff, 0xc92d, 0x21, 0 + .dw 0x6240, 0xc92d, 0x627f, 0xc92d, 0x21, 0 + .dw 0x62c0, 0xc92d, 0x62ff, 0xc92d, 0x21, 0 + .dw 0x6340, 0xc92d, 0x637f, 0xc92d, 0x21, 0 + .dw 0x63c0, 0xc92d, 0x63ff, 0xc92d, 0x21, 0 + .dw 0x6440, 0xc92d, 0x647f, 0xc92d, 0x21, 0 + .dw 0x64c0, 0xc92d, 0x64ff, 0xc92d, 0x21, 0 + .dw 0x6540, 0xc92d, 0x657f, 0xc92d, 0x21, 0 + .dw 0x65c0, 0xc92d, 0x65ff, 0xc92d, 0x21, 0 + .dw 0x6640, 0xc92d, 0x667f, 0xc92d, 0x21, 0 + .dw 0x66c0, 0xc92d, 0x66ff, 0xc92d, 0x21, 0 + .dw 0x6740, 0xc92d, 0x677f, 0xc92d, 0x21, 0 + .dw 0x67c0, 0xc92d, 0x67ff, 0xc92d, 0x21, 0 + .dw 0x6840, 0xc92d, 0x687f, 0xc92d, 0x21, 0 + .dw 0x68c0, 0xc92d, 0x68ff, 0xc92d, 0x21, 0 + .dw 0x6940, 0xc92d, 0x697f, 0xc92d, 0x21, 0 + .dw 0x69c0, 0xc92d, 0x69ff, 0xc92d, 0x21, 0 + .dw 0x6a40, 0xc92d, 0x6a7f, 0xc92d, 0x21, 0 + .dw 0x6ac0, 0xc92d, 0x6aff, 0xc92d, 0x21, 0 + .dw 0x6b40, 0xc92d, 0x6b7f, 0xc92d, 0x21, 0 + .dw 0x6bc0, 0xc92d, 0x6bff, 0xc92d, 0x21, 0 + .dw 0x6c40, 0xc92d, 0x6c7f, 0xc92d, 0x21, 0 + .dw 0x6cc0, 0xc92d, 0x6cff, 0xc92d, 0x21, 0 + .dw 0x6d40, 0xc92d, 0x6d7f, 0xc92d, 0x21, 0 + .dw 0x6dc0, 0xc92d, 0x6dff, 0xc92d, 0x21, 0 + .dw 0x6e40, 0xc92d, 0x6e7f, 0xc92d, 0x21, 0 + .dw 0x6ec0, 0xc92d, 0x6eff, 0xc92d, 0x21, 0 + .dw 0x6f40, 0xc92d, 0x6f7f, 0xc92d, 0x21, 0 + .dw 0x6fc0, 0xc92d, 0x6fff, 0xc92d, 0x21, 0 + .dw 0x7040, 0xc92d, 0x707f, 0xc92d, 0x21, 0 + .dw 0x70c0, 0xc92d, 0x70ff, 0xc92d, 0x21, 0 + .dw 0x7140, 0xc92d, 0x717f, 0xc92d, 0x21, 0 + .dw 0x71c0, 0xc92d, 0x71ff, 0xc92d, 0x21, 0 + .dw 0x7240, 0xc92d, 0x727f, 0xc92d, 0x21, 0 + .dw 0x72c0, 0xc92d, 0x72ff, 0xc92d, 0x21, 0 + .dw 0x7340, 0xc92d, 0x737f, 0xc92d, 0x21, 0 + .dw 0x73c0, 0xc92d, 0x73ff, 0xc92d, 0x21, 0 + .dw 0x7440, 0xc92d, 0x747f, 0xc92d, 0x21, 0 + .dw 0x74c0, 0xc92d, 0x74ff, 0xc92d, 0x21, 0 + .dw 0x7540, 0xc92d, 0x757f, 0xc92d, 0x21, 0 + .dw 0x75c0, 0xc92d, 0x75ff, 0xc92d, 0x21, 0 + .dw 0x7640, 0xc92d, 0x767f, 0xc92d, 0x21, 0 + .dw 0x76c0, 0xc92d, 0x76ff, 0xc92d, 0x21, 0 + .dw 0x7740, 0xc92d, 0x777f, 0xc92d, 0x21, 0 + .dw 0x77c0, 0xc92d, 0x77ff, 0xc92d, 0x21, 0 + .dw 0x7840, 0xc92d, 0x787f, 0xc92d, 0x21, 0 + .dw 0x78c0, 0xc92d, 0x78ff, 0xc92d, 0x21, 0 + .dw 0x7940, 0xc92d, 0x797f, 0xc92d, 0x21, 0 + .dw 0x79c0, 0xc92d, 0x7fff, 0xc92d, 0x21, 0 + .dw 0x8040, 0xc92d, 0x807f, 0xc92d, 0x21, 0 + .dw 0x80c0, 0xc92d, 0x80ff, 0xc92d, 0x21, 0 + .dw 0x8140, 0xc92d, 0x817f, 0xc92d, 0x21, 0 + .dw 0x81c0, 0xc92d, 0x81ff, 0xc92d, 0x21, 0 + .dw 0x8240, 0xc92d, 0x827f, 0xc92d, 0x21, 0 + .dw 0x82c0, 0xc92d, 0x82ff, 0xc92d, 0x21, 0 + .dw 0x8340, 0xc92d, 0x837f, 0xc92d, 0x21, 0 + .dw 0x83c0, 0xc92d, 0x83ff, 0xc92d, 0x21, 0 + .dw 0x8440, 0xc92d, 0x847f, 0xc92d, 0x21, 0 + .dw 0x84c0, 0xc92d, 0x84ff, 0xc92d, 0x21, 0 + .dw 0x8540, 0xc92d, 0x857f, 0xc92d, 0x21, 0 + .dw 0x85c0, 0xc92d, 0x85ff, 0xc92d, 0x21, 0 + .dw 0x8640, 0xc92d, 0x867f, 0xc92d, 0x21, 0 + .dw 0x86c0, 0xc92d, 0x86ff, 0xc92d, 0x21, 0 + .dw 0x8740, 0xc92d, 0x877f, 0xc92d, 0x21, 0 + .dw 0x87c0, 0xc92d, 0x87ff, 0xc92d, 0x21, 0 + .dw 0x8840, 0xc92d, 0x887f, 0xc92d, 0x21, 0 + .dw 0x88c0, 0xc92d, 0x88ff, 0xc92d, 0x21, 0 + .dw 0x8940, 0xc92d, 0x897f, 0xc92d, 0x21, 0 + .dw 0x89c0, 0xc92d, 0x89ff, 0xc92d, 0x21, 0 + .dw 0x8a40, 0xc92d, 0x8a7f, 0xc92d, 0x21, 0 + .dw 0x8ac0, 0xc92d, 0x8aff, 0xc92d, 0x21, 0 + .dw 0x8b40, 0xc92d, 0x8b7f, 0xc92d, 0x21, 0 + .dw 0x8bc0, 0xc92d, 0x8bff, 0xc92d, 0x21, 0 + .dw 0x8c40, 0xc92d, 0x8c7f, 0xc92d, 0x21, 0 + .dw 0x8cc0, 0xc92d, 0x8cff, 0xc92d, 0x21, 0 + .dw 0x8d40, 0xc92d, 0x8d7f, 0xc92d, 0x21, 0 + .dw 0x8dc0, 0xc92d, 0x8dff, 0xc92d, 0x21, 0 + .dw 0x8e40, 0xc92d, 0x8e7f, 0xc92d, 0x21, 0 + .dw 0x8ec0, 0xc92d, 0x8eff, 0xc92d, 0x21, 0 + .dw 0x8f40, 0xc92d, 0x8f7f, 0xc92d, 0x21, 0 + .dw 0x8fc0, 0xc92d, 0x8fff, 0xc92d, 0x21, 0 + .dw 0x9040, 0xc92d, 0x907f, 0xc92d, 0x21, 0 + .dw 0x90c0, 0xc92d, 0x90ff, 0xc92d, 0x21, 0 + .dw 0x9140, 0xc92d, 0x917f, 0xc92d, 0x21, 0 + .dw 0x91c0, 0xc92d, 0x91ff, 0xc92d, 0x21, 0 + .dw 0x9240, 0xc92d, 0x927f, 0xc92d, 0x21, 0 + .dw 0x92c0, 0xc92d, 0x92ff, 0xc92d, 0x21, 0 + .dw 0x9340, 0xc92d, 0x937f, 0xc92d, 0x21, 0 + .dw 0x93c0, 0xc92d, 0x93ff, 0xc92d, 0x21, 0 + .dw 0x9440, 0xc92d, 0x947f, 0xc92d, 0x21, 0 + .dw 0x94c0, 0xc92d, 0x94ff, 0xc92d, 0x21, 0 + .dw 0x9540, 0xc92d, 0x957f, 0xc92d, 0x21, 0 + .dw 0x95c0, 0xc92d, 0x95ff, 0xc92d, 0x21, 0 + .dw 0x9640, 0xc92d, 0x967f, 0xc92d, 0x21, 0 + .dw 0x96c0, 0xc92d, 0x96ff, 0xc92d, 0x21, 0 + .dw 0x9740, 0xc92d, 0x977f, 0xc92d, 0x21, 0 + .dw 0x97c0, 0xc92d, 0x97ff, 0xc92d, 0x21, 0 + .dw 0x9840, 0xc92d, 0x987f, 0xc92d, 0x21, 0 + .dw 0x98c0, 0xc92d, 0x98ff, 0xc92d, 0x21, 0 + .dw 0x9940, 0xc92d, 0x997f, 0xc92d, 0x21, 0 + .dw 0x99c0, 0xc92d, 0x9fff, 0xc92d, 0x21, 0 + .dw 0xa040, 0xc92d, 0xa07f, 0xc92d, 0x21, 0 + .dw 0xa0c0, 0xc92d, 0xa0ff, 0xc92d, 0x21, 0 + .dw 0xa140, 0xc92d, 0xa17f, 0xc92d, 0x21, 0 + .dw 0xa1c0, 0xc92d, 0xa1ff, 0xc92d, 0x21, 0 + .dw 0xa240, 0xc92d, 0xa27f, 0xc92d, 0x21, 0 + .dw 0xa2c0, 0xc92d, 0xa2ff, 0xc92d, 0x21, 0 + .dw 0xa340, 0xc92d, 0xa37f, 0xc92d, 0x21, 0 + .dw 0xa3c0, 0xc92d, 0xa3ff, 0xc92d, 0x21, 0 + .dw 0xa440, 0xc92d, 0xa47f, 0xc92d, 0x21, 0 + .dw 0xa4c0, 0xc92d, 0xa4ff, 0xc92d, 0x21, 0 + .dw 0xa540, 0xc92d, 0xa57f, 0xc92d, 0x21, 0 + .dw 0xa5c0, 0xc92d, 0xa5ff, 0xc92d, 0x21, 0 + .dw 0xa640, 0xc92d, 0xa67f, 0xc92d, 0x21, 0 + .dw 0xa6c0, 0xc92d, 0xa6ff, 0xc92d, 0x21, 0 + .dw 0xa740, 0xc92d, 0xa77f, 0xc92d, 0x21, 0 + .dw 0xa7c0, 0xc92d, 0xa7ff, 0xc92d, 0x21, 0 + .dw 0xa840, 0xc92d, 0xa87f, 0xc92d, 0x21, 0 + .dw 0xa8c0, 0xc92d, 0xa8ff, 0xc92d, 0x21, 0 + .dw 0xa940, 0xc92d, 0xa97f, 0xc92d, 0x21, 0 + .dw 0xa9c0, 0xc92d, 0xa9ff, 0xc92d, 0x21, 0 + .dw 0xaa40, 0xc92d, 0xaa7f, 0xc92d, 0x21, 0 + .dw 0xaac0, 0xc92d, 0xaaff, 0xc92d, 0x21, 0 + .dw 0xab40, 0xc92d, 0xab7f, 0xc92d, 0x21, 0 + .dw 0xabc0, 0xc92d, 0xabff, 0xc92d, 0x21, 0 + .dw 0xac40, 0xc92d, 0xac7f, 0xc92d, 0x21, 0 + .dw 0xacc0, 0xc92d, 0xacff, 0xc92d, 0x21, 0 + .dw 0xad40, 0xc92d, 0xad7f, 0xc92d, 0x21, 0 + .dw 0xadc0, 0xc92d, 0xadff, 0xc92d, 0x21, 0 + .dw 0xae40, 0xc92d, 0xae7f, 0xc92d, 0x21, 0 + .dw 0xaec0, 0xc92d, 0xaeff, 0xc92d, 0x21, 0 + .dw 0xaf40, 0xc92d, 0xaf7f, 0xc92d, 0x21, 0 + .dw 0xafc0, 0xc92d, 0xafff, 0xc92d, 0x21, 0 + .dw 0xb040, 0xc92d, 0xb07f, 0xc92d, 0x21, 0 + .dw 0xb0c0, 0xc92d, 0xb0ff, 0xc92d, 0x21, 0 + .dw 0xb140, 0xc92d, 0xb17f, 0xc92d, 0x21, 0 + .dw 0xb1c0, 0xc92d, 0xb1ff, 0xc92d, 0x21, 0 + .dw 0xb240, 0xc92d, 0xb27f, 0xc92d, 0x21, 0 + .dw 0xb2c0, 0xc92d, 0xb2ff, 0xc92d, 0x21, 0 + .dw 0xb340, 0xc92d, 0xb37f, 0xc92d, 0x21, 0 + .dw 0xb3c0, 0xc92d, 0xb3ff, 0xc92d, 0x21, 0 + .dw 0xb440, 0xc92d, 0xb47f, 0xc92d, 0x21, 0 + .dw 0xb4c0, 0xc92d, 0xb4ff, 0xc92d, 0x21, 0 + .dw 0xb540, 0xc92d, 0xb57f, 0xc92d, 0x21, 0 + .dw 0xb5c0, 0xc92d, 0xb5ff, 0xc92d, 0x21, 0 + .dw 0xb640, 0xc92d, 0xb67f, 0xc92d, 0x21, 0 + .dw 0xb6c0, 0xc92d, 0xb6ff, 0xc92d, 0x21, 0 + .dw 0xb740, 0xc92d, 0xb77f, 0xc92d, 0x21, 0 + .dw 0xb7c0, 0xc92d, 0xb7ff, 0xc92d, 0x21, 0 + .dw 0xb840, 0xc92d, 0xb87f, 0xc92d, 0x21, 0 + .dw 0xb8c0, 0xc92d, 0xb8ff, 0xc92d, 0x21, 0 + .dw 0xb940, 0xc92d, 0xb97f, 0xc92d, 0x21, 0 + .dw 0xb9c0, 0xc92d, 0xbfff, 0xc92d, 0x21, 0 + .dw 0xc040, 0xc92d, 0xc07f, 0xc92d, 0x21, 0 + .dw 0xc0c0, 0xc92d, 0xc0ff, 0xc92d, 0x21, 0 + .dw 0xc140, 0xc92d, 0xc17f, 0xc92d, 0x21, 0 + .dw 0xc1c0, 0xc92d, 0xc1ff, 0xc92d, 0x21, 0 + .dw 0xc240, 0xc92d, 0xc27f, 0xc92d, 0x21, 0 + .dw 0xc2c0, 0xc92d, 0xc2ff, 0xc92d, 0x21, 0 + .dw 0xc340, 0xc92d, 0xc37f, 0xc92d, 0x21, 0 + .dw 0xc3c0, 0xc92d, 0xc3ff, 0xc92d, 0x21, 0 + .dw 0xc440, 0xc92d, 0xc47f, 0xc92d, 0x21, 0 + .dw 0xc4c0, 0xc92d, 0xc4ff, 0xc92d, 0x21, 0 + .dw 0xc540, 0xc92d, 0xc57f, 0xc92d, 0x21, 0 + .dw 0xc5c0, 0xc92d, 0xc5ff, 0xc92d, 0x21, 0 + .dw 0xc640, 0xc92d, 0xc67f, 0xc92d, 0x21, 0 + .dw 0xc6c0, 0xc92d, 0xc6ff, 0xc92d, 0x21, 0 + .dw 0xc740, 0xc92d, 0xc77f, 0xc92d, 0x21, 0 + .dw 0xc7c0, 0xc92d, 0xc7ff, 0xc92d, 0x21, 0 + .dw 0xc840, 0xc92d, 0xc87f, 0xc92d, 0x21, 0 + .dw 0xc8c0, 0xc92d, 0xc8ff, 0xc92d, 0x21, 0 + .dw 0xc940, 0xc92d, 0xc97f, 0xc92d, 0x21, 0 + .dw 0xc9c0, 0xc92d, 0xc9ff, 0xc92d, 0x21, 0 + .dw 0xca40, 0xc92d, 0xca7f, 0xc92d, 0x21, 0 + .dw 0xcac0, 0xc92d, 0xcaff, 0xc92d, 0x21, 0 + .dw 0xcb40, 0xc92d, 0xcb7f, 0xc92d, 0x21, 0 + .dw 0xcbc0, 0xc92d, 0xcbff, 0xc92d, 0x21, 0 + .dw 0xcc40, 0xc92d, 0xcc7f, 0xc92d, 0x21, 0 + .dw 0xccc0, 0xc92d, 0xccff, 0xc92d, 0x21, 0 + .dw 0xcd40, 0xc92d, 0xcd7f, 0xc92d, 0x21, 0 + .dw 0xcdc0, 0xc92d, 0xcdff, 0xc92d, 0x21, 0 + .dw 0xce40, 0xc92d, 0xce7f, 0xc92d, 0x21, 0 + .dw 0xcec0, 0xc92d, 0xceff, 0xc92d, 0x21, 0 + .dw 0xcf40, 0xc92d, 0xcf7f, 0xc92d, 0x21, 0 + .dw 0xcfc0, 0xc92d, 0xcfff, 0xc92d, 0x21, 0 + .dw 0xd040, 0xc92d, 0xd07f, 0xc92d, 0x21, 0 + .dw 0xd0c0, 0xc92d, 0xd0ff, 0xc92d, 0x21, 0 + .dw 0xd140, 0xc92d, 0xd17f, 0xc92d, 0x21, 0 + .dw 0xd1c0, 0xc92d, 0xd1ff, 0xc92d, 0x21, 0 + .dw 0xd240, 0xc92d, 0xd27f, 0xc92d, 0x21, 0 + .dw 0xd2c0, 0xc92d, 0xd2ff, 0xc92d, 0x21, 0 + .dw 0xd340, 0xc92d, 0xd37f, 0xc92d, 0x21, 0 + .dw 0xd3c0, 0xc92d, 0xd3ff, 0xc92d, 0x21, 0 + .dw 0xd440, 0xc92d, 0xd47f, 0xc92d, 0x21, 0 + .dw 0xd4c0, 0xc92d, 0xd4ff, 0xc92d, 0x21, 0 + .dw 0xd540, 0xc92d, 0xd57f, 0xc92d, 0x21, 0 + .dw 0xd5c0, 0xc92d, 0xd5ff, 0xc92d, 0x21, 0 + .dw 0xd640, 0xc92d, 0xd67f, 0xc92d, 0x21, 0 + .dw 0xd6c0, 0xc92d, 0xd6ff, 0xc92d, 0x21, 0 + .dw 0xd740, 0xc92d, 0xd77f, 0xc92d, 0x21, 0 + .dw 0xd7c0, 0xc92d, 0xd7ff, 0xc92d, 0x21, 0 + .dw 0xd840, 0xc92d, 0xd87f, 0xc92d, 0x21, 0 + .dw 0xd8c0, 0xc92d, 0xd8ff, 0xc92d, 0x21, 0 + .dw 0xd940, 0xc92d, 0xd97f, 0xc92d, 0x21, 0 + .dw 0xd9c0, 0xc92d, 0xdfff, 0xc92d, 0x21, 0 + .dw 0xe040, 0xc92d, 0xe07f, 0xc92d, 0x21, 0 + .dw 0xe0c0, 0xc92d, 0xe0ff, 0xc92d, 0x21, 0 + .dw 0xe140, 0xc92d, 0xe17f, 0xc92d, 0x21, 0 + .dw 0xe1c0, 0xc92d, 0xe1ff, 0xc92d, 0x21, 0 + .dw 0xe240, 0xc92d, 0xe27f, 0xc92d, 0x21, 0 + .dw 0xe2c0, 0xc92d, 0xe2ff, 0xc92d, 0x21, 0 + .dw 0xe340, 0xc92d, 0xe37f, 0xc92d, 0x21, 0 + .dw 0xe3c0, 0xc92d, 0xe3ff, 0xc92d, 0x21, 0 + .dw 0xe440, 0xc92d, 0xe47f, 0xc92d, 0x21, 0 + .dw 0xe4c0, 0xc92d, 0xe4ff, 0xc92d, 0x21, 0 + .dw 0xe540, 0xc92d, 0xe57f, 0xc92d, 0x21, 0 + .dw 0xe5c0, 0xc92d, 0xe5ff, 0xc92d, 0x21, 0 + .dw 0xe640, 0xc92d, 0xe67f, 0xc92d, 0x21, 0 + .dw 0xe6c0, 0xc92d, 0xe6ff, 0xc92d, 0x21, 0 + .dw 0xe740, 0xc92d, 0xe77f, 0xc92d, 0x21, 0 + .dw 0xe7c0, 0xc92d, 0xe7ff, 0xc92d, 0x21, 0 + .dw 0xe840, 0xc92d, 0xe87f, 0xc92d, 0x21, 0 + .dw 0xe8c0, 0xc92d, 0xe8ff, 0xc92d, 0x21, 0 + .dw 0xe940, 0xc92d, 0xe97f, 0xc92d, 0x21, 0 + .dw 0xe9c0, 0xc92d, 0xe9ff, 0xc92d, 0x21, 0 + .dw 0xea40, 0xc92d, 0xea7f, 0xc92d, 0x21, 0 + .dw 0xeac0, 0xc92d, 0xeaff, 0xc92d, 0x21, 0 + .dw 0xeb40, 0xc92d, 0xeb7f, 0xc92d, 0x21, 0 + .dw 0xebc0, 0xc92d, 0xebff, 0xc92d, 0x21, 0 + .dw 0xec40, 0xc92d, 0xec7f, 0xc92d, 0x21, 0 + .dw 0xecc0, 0xc92d, 0xecff, 0xc92d, 0x21, 0 + .dw 0xed40, 0xc92d, 0xed7f, 0xc92d, 0x21, 0 + .dw 0xedc0, 0xc92d, 0xedff, 0xc92d, 0x21, 0 + .dw 0xee40, 0xc92d, 0xee7f, 0xc92d, 0x21, 0 + .dw 0xeec0, 0xc92d, 0xeeff, 0xc92d, 0x21, 0 + .dw 0xef40, 0xc92d, 0xef7f, 0xc92d, 0x21, 0 + .dw 0xefc0, 0xc92d, 0xefff, 0xc92d, 0x21, 0 + .dw 0xf040, 0xc92d, 0xf07f, 0xc92d, 0x21, 0 + .dw 0xf0c0, 0xc92d, 0xf0ff, 0xc92d, 0x21, 0 + .dw 0xf140, 0xc92d, 0xf17f, 0xc92d, 0x21, 0 + .dw 0xf1c0, 0xc92d, 0xf1ff, 0xc92d, 0x21, 0 + .dw 0xf240, 0xc92d, 0xf27f, 0xc92d, 0x21, 0 + .dw 0xf2c0, 0xc92d, 0xf2ff, 0xc92d, 0x21, 0 + .dw 0xf340, 0xc92d, 0xf37f, 0xc92d, 0x21, 0 + .dw 0xf3c0, 0xc92d, 0xf3ff, 0xc92d, 0x21, 0 + .dw 0xf440, 0xc92d, 0xf47f, 0xc92d, 0x21, 0 + .dw 0xf4c0, 0xc92d, 0xf4ff, 0xc92d, 0x21, 0 + .dw 0xf540, 0xc92d, 0xf57f, 0xc92d, 0x21, 0 + .dw 0xf5c0, 0xc92d, 0xf5ff, 0xc92d, 0x21, 0 + .dw 0xf640, 0xc92d, 0xf67f, 0xc92d, 0x21, 0 + .dw 0xf6c0, 0xc92d, 0xf6ff, 0xc92d, 0x21, 0 + .dw 0xf740, 0xc92d, 0xf77f, 0xc92d, 0x21, 0 + .dw 0xf7c0, 0xc92d, 0xf7ff, 0xc92d, 0x21, 0 + .dw 0xf840, 0xc92d, 0xf87f, 0xc92d, 0x21, 0 + .dw 0xf8c0, 0xc92d, 0xf8ff, 0xc92d, 0x21, 0 + .dw 0xf940, 0xc92d, 0xf97f, 0xc92d, 0x21, 0 + .dw 0xf9c0, 0xc92d, 0xffff, 0xc92d, 0x21, 0 + .dw 0x0040, 0xc92e, 0x007f, 0xc92e, 0x21, 0 + .dw 0x00c0, 0xc92e, 0x00ff, 0xc92e, 0x21, 0 + .dw 0x0140, 0xc92e, 0x017f, 0xc92e, 0x21, 0 + .dw 0x01c0, 0xc92e, 0x01ff, 0xc92e, 0x21, 0 + .dw 0x0240, 0xc92e, 0x027f, 0xc92e, 0x21, 0 + .dw 0x02c0, 0xc92e, 0x02ff, 0xc92e, 0x21, 0 + .dw 0x0340, 0xc92e, 0x037f, 0xc92e, 0x21, 0 + .dw 0x03c0, 0xc92e, 0x03ff, 0xc92e, 0x21, 0 + .dw 0x0440, 0xc92e, 0x047f, 0xc92e, 0x21, 0 + .dw 0x04c0, 0xc92e, 0x04ff, 0xc92e, 0x21, 0 + .dw 0x0540, 0xc92e, 0x057f, 0xc92e, 0x21, 0 + .dw 0x05c0, 0xc92e, 0x05ff, 0xc92e, 0x21, 0 + .dw 0x0640, 0xc92e, 0x067f, 0xc92e, 0x21, 0 + .dw 0x06c0, 0xc92e, 0x06ff, 0xc92e, 0x21, 0 + .dw 0x0740, 0xc92e, 0x077f, 0xc92e, 0x21, 0 + .dw 0x07c0, 0xc92e, 0x07ff, 0xc92e, 0x21, 0 + .dw 0x0840, 0xc92e, 0x087f, 0xc92e, 0x21, 0 + .dw 0x08c0, 0xc92e, 0x08ff, 0xc92e, 0x21, 0 + .dw 0x0940, 0xc92e, 0x097f, 0xc92e, 0x21, 0 + .dw 0x09c0, 0xc92e, 0x09ff, 0xc92e, 0x21, 0 + .dw 0x0a40, 0xc92e, 0x0a7f, 0xc92e, 0x21, 0 + .dw 0x0ac0, 0xc92e, 0x0aff, 0xc92e, 0x21, 0 + .dw 0x0b40, 0xc92e, 0x0b7f, 0xc92e, 0x21, 0 + .dw 0x0bc0, 0xc92e, 0x0bff, 0xc92e, 0x21, 0 + .dw 0x0c40, 0xc92e, 0x0c7f, 0xc92e, 0x21, 0 + .dw 0x0cc0, 0xc92e, 0x0cff, 0xc92e, 0x21, 0 + .dw 0x0d40, 0xc92e, 0x0d7f, 0xc92e, 0x21, 0 + .dw 0x0dc0, 0xc92e, 0x0dff, 0xc92e, 0x21, 0 + .dw 0x0e40, 0xc92e, 0x0e7f, 0xc92e, 0x21, 0 + .dw 0x0ec0, 0xc92e, 0x0eff, 0xc92e, 0x21, 0 + .dw 0x0f40, 0xc92e, 0x0f7f, 0xc92e, 0x21, 0 + .dw 0x0fc0, 0xc92e, 0x0fff, 0xc92e, 0x21, 0 + .dw 0x1040, 0xc92e, 0x107f, 0xc92e, 0x21, 0 + .dw 0x10c0, 0xc92e, 0x10ff, 0xc92e, 0x21, 0 + .dw 0x1140, 0xc92e, 0x117f, 0xc92e, 0x21, 0 + .dw 0x11c0, 0xc92e, 0x11ff, 0xc92e, 0x21, 0 + .dw 0x1240, 0xc92e, 0x127f, 0xc92e, 0x21, 0 + .dw 0x12c0, 0xc92e, 0x12ff, 0xc92e, 0x21, 0 + .dw 0x1340, 0xc92e, 0x137f, 0xc92e, 0x21, 0 + .dw 0x13c0, 0xc92e, 0x13ff, 0xc92e, 0x21, 0 + .dw 0x1440, 0xc92e, 0x147f, 0xc92e, 0x21, 0 + .dw 0x14c0, 0xc92e, 0x14ff, 0xc92e, 0x21, 0 + .dw 0x1540, 0xc92e, 0x157f, 0xc92e, 0x21, 0 + .dw 0x15c0, 0xc92e, 0x15ff, 0xc92e, 0x21, 0 + .dw 0x1640, 0xc92e, 0x167f, 0xc92e, 0x21, 0 + .dw 0x16c0, 0xc92e, 0x16ff, 0xc92e, 0x21, 0 + .dw 0x1740, 0xc92e, 0x177f, 0xc92e, 0x21, 0 + .dw 0x17c0, 0xc92e, 0x17ff, 0xc92e, 0x21, 0 + .dw 0x1840, 0xc92e, 0x187f, 0xc92e, 0x21, 0 + .dw 0x18c0, 0xc92e, 0x18ff, 0xc92e, 0x21, 0 + .dw 0x1940, 0xc92e, 0x197f, 0xc92e, 0x21, 0 + .dw 0x19c0, 0xc92e, 0x1fff, 0xc92e, 0x21, 0 + .dw 0x2040, 0xc92e, 0x207f, 0xc92e, 0x21, 0 + .dw 0x20c0, 0xc92e, 0x20ff, 0xc92e, 0x21, 0 + .dw 0x2140, 0xc92e, 0x217f, 0xc92e, 0x21, 0 + .dw 0x21c0, 0xc92e, 0x21ff, 0xc92e, 0x21, 0 + .dw 0x2240, 0xc92e, 0x227f, 0xc92e, 0x21, 0 + .dw 0x22c0, 0xc92e, 0x22ff, 0xc92e, 0x21, 0 + .dw 0x2340, 0xc92e, 0x237f, 0xc92e, 0x21, 0 + .dw 0x23c0, 0xc92e, 0x23ff, 0xc92e, 0x21, 0 + .dw 0x2440, 0xc92e, 0x247f, 0xc92e, 0x21, 0 + .dw 0x24c0, 0xc92e, 0x24ff, 0xc92e, 0x21, 0 + .dw 0x2540, 0xc92e, 0x257f, 0xc92e, 0x21, 0 + .dw 0x25c0, 0xc92e, 0x25ff, 0xc92e, 0x21, 0 + .dw 0x2640, 0xc92e, 0x267f, 0xc92e, 0x21, 0 + .dw 0x26c0, 0xc92e, 0x26ff, 0xc92e, 0x21, 0 + .dw 0x2740, 0xc92e, 0x277f, 0xc92e, 0x21, 0 + .dw 0x27c0, 0xc92e, 0x27ff, 0xc92e, 0x21, 0 + .dw 0x2840, 0xc92e, 0x287f, 0xc92e, 0x21, 0 + .dw 0x28c0, 0xc92e, 0x28ff, 0xc92e, 0x21, 0 + .dw 0x2940, 0xc92e, 0x297f, 0xc92e, 0x21, 0 + .dw 0x29c0, 0xc92e, 0x29ff, 0xc92e, 0x21, 0 + .dw 0x2a40, 0xc92e, 0x2a7f, 0xc92e, 0x21, 0 + .dw 0x2ac0, 0xc92e, 0x2aff, 0xc92e, 0x21, 0 + .dw 0x2b40, 0xc92e, 0x2b7f, 0xc92e, 0x21, 0 + .dw 0x2bc0, 0xc92e, 0x2bff, 0xc92e, 0x21, 0 + .dw 0x2c40, 0xc92e, 0x2c7f, 0xc92e, 0x21, 0 + .dw 0x2cc0, 0xc92e, 0x2cff, 0xc92e, 0x21, 0 + .dw 0x2d40, 0xc92e, 0x2d7f, 0xc92e, 0x21, 0 + .dw 0x2dc0, 0xc92e, 0x2dff, 0xc92e, 0x21, 0 + .dw 0x2e40, 0xc92e, 0x2e7f, 0xc92e, 0x21, 0 + .dw 0x2ec0, 0xc92e, 0x2eff, 0xc92e, 0x21, 0 + .dw 0x2f40, 0xc92e, 0x2f7f, 0xc92e, 0x21, 0 + .dw 0x2fc0, 0xc92e, 0x2fff, 0xc92e, 0x21, 0 + .dw 0x3040, 0xc92e, 0x307f, 0xc92e, 0x21, 0 + .dw 0x30c0, 0xc92e, 0x30ff, 0xc92e, 0x21, 0 + .dw 0x3140, 0xc92e, 0x317f, 0xc92e, 0x21, 0 + .dw 0x31c0, 0xc92e, 0x31ff, 0xc92e, 0x21, 0 + .dw 0x3240, 0xc92e, 0x327f, 0xc92e, 0x21, 0 + .dw 0x32c0, 0xc92e, 0x32ff, 0xc92e, 0x21, 0 + .dw 0x3340, 0xc92e, 0x337f, 0xc92e, 0x21, 0 + .dw 0x33c0, 0xc92e, 0x33ff, 0xc92e, 0x21, 0 + .dw 0x3440, 0xc92e, 0x347f, 0xc92e, 0x21, 0 + .dw 0x34c0, 0xc92e, 0x34ff, 0xc92e, 0x21, 0 + .dw 0x3540, 0xc92e, 0x357f, 0xc92e, 0x21, 0 + .dw 0x35c0, 0xc92e, 0x35ff, 0xc92e, 0x21, 0 + .dw 0x3640, 0xc92e, 0x367f, 0xc92e, 0x21, 0 + .dw 0x36c0, 0xc92e, 0x36ff, 0xc92e, 0x21, 0 + .dw 0x3740, 0xc92e, 0x377f, 0xc92e, 0x21, 0 + .dw 0x37c0, 0xc92e, 0x37ff, 0xc92e, 0x21, 0 + .dw 0x3840, 0xc92e, 0x387f, 0xc92e, 0x21, 0 + .dw 0x38c0, 0xc92e, 0x38ff, 0xc92e, 0x21, 0 + .dw 0x3940, 0xc92e, 0x397f, 0xc92e, 0x21, 0 + .dw 0x39c0, 0xc92e, 0x3fff, 0xc92e, 0x21, 0 + .dw 0x4040, 0xc92e, 0x407f, 0xc92e, 0x21, 0 + .dw 0x40c0, 0xc92e, 0x40ff, 0xc92e, 0x21, 0 + .dw 0x4140, 0xc92e, 0x417f, 0xc92e, 0x21, 0 + .dw 0x41c0, 0xc92e, 0x41ff, 0xc92e, 0x21, 0 + .dw 0x4240, 0xc92e, 0x427f, 0xc92e, 0x21, 0 + .dw 0x42c0, 0xc92e, 0x42ff, 0xc92e, 0x21, 0 + .dw 0x4340, 0xc92e, 0x437f, 0xc92e, 0x21, 0 + .dw 0x43c0, 0xc92e, 0x43ff, 0xc92e, 0x21, 0 + .dw 0x4440, 0xc92e, 0x447f, 0xc92e, 0x21, 0 + .dw 0x44c0, 0xc92e, 0x44ff, 0xc92e, 0x21, 0 + .dw 0x4540, 0xc92e, 0x457f, 0xc92e, 0x21, 0 + .dw 0x45c0, 0xc92e, 0x45ff, 0xc92e, 0x21, 0 + .dw 0x4640, 0xc92e, 0x467f, 0xc92e, 0x21, 0 + .dw 0x46c0, 0xc92e, 0x46ff, 0xc92e, 0x21, 0 + .dw 0x4740, 0xc92e, 0x477f, 0xc92e, 0x21, 0 + .dw 0x47c0, 0xc92e, 0x47ff, 0xc92e, 0x21, 0 + .dw 0x4840, 0xc92e, 0x487f, 0xc92e, 0x21, 0 + .dw 0x48c0, 0xc92e, 0x48ff, 0xc92e, 0x21, 0 + .dw 0x4940, 0xc92e, 0x497f, 0xc92e, 0x21, 0 + .dw 0x49c0, 0xc92e, 0x49ff, 0xc92e, 0x21, 0 + .dw 0x4a40, 0xc92e, 0x4a7f, 0xc92e, 0x21, 0 + .dw 0x4ac0, 0xc92e, 0x4aff, 0xc92e, 0x21, 0 + .dw 0x4b40, 0xc92e, 0x4b7f, 0xc92e, 0x21, 0 + .dw 0x4bc0, 0xc92e, 0x4bff, 0xc92e, 0x21, 0 + .dw 0x4c40, 0xc92e, 0x4c7f, 0xc92e, 0x21, 0 + .dw 0x4cc0, 0xc92e, 0x4cff, 0xc92e, 0x21, 0 + .dw 0x4d40, 0xc92e, 0x4d7f, 0xc92e, 0x21, 0 + .dw 0x4dc0, 0xc92e, 0x4dff, 0xc92e, 0x21, 0 + .dw 0x4e40, 0xc92e, 0x4e7f, 0xc92e, 0x21, 0 + .dw 0x4ec0, 0xc92e, 0x4eff, 0xc92e, 0x21, 0 + .dw 0x4f40, 0xc92e, 0x4f7f, 0xc92e, 0x21, 0 + .dw 0x4fc0, 0xc92e, 0x4fff, 0xc92e, 0x21, 0 + .dw 0x5040, 0xc92e, 0x507f, 0xc92e, 0x21, 0 + .dw 0x50c0, 0xc92e, 0x50ff, 0xc92e, 0x21, 0 + .dw 0x5140, 0xc92e, 0x517f, 0xc92e, 0x21, 0 + .dw 0x51c0, 0xc92e, 0x51ff, 0xc92e, 0x21, 0 + .dw 0x5240, 0xc92e, 0x527f, 0xc92e, 0x21, 0 + .dw 0x52c0, 0xc92e, 0x52ff, 0xc92e, 0x21, 0 + .dw 0x5340, 0xc92e, 0x537f, 0xc92e, 0x21, 0 + .dw 0x53c0, 0xc92e, 0x53ff, 0xc92e, 0x21, 0 + .dw 0x5440, 0xc92e, 0x547f, 0xc92e, 0x21, 0 + .dw 0x54c0, 0xc92e, 0x54ff, 0xc92e, 0x21, 0 + .dw 0x5540, 0xc92e, 0x557f, 0xc92e, 0x21, 0 + .dw 0x55c0, 0xc92e, 0x55ff, 0xc92e, 0x21, 0 + .dw 0x5640, 0xc92e, 0x567f, 0xc92e, 0x21, 0 + .dw 0x56c0, 0xc92e, 0x56ff, 0xc92e, 0x21, 0 + .dw 0x5740, 0xc92e, 0x577f, 0xc92e, 0x21, 0 + .dw 0x57c0, 0xc92e, 0x57ff, 0xc92e, 0x21, 0 + .dw 0x5840, 0xc92e, 0x587f, 0xc92e, 0x21, 0 + .dw 0x58c0, 0xc92e, 0x58ff, 0xc92e, 0x21, 0 + .dw 0x5940, 0xc92e, 0x597f, 0xc92e, 0x21, 0 + .dw 0x59c0, 0xc92e, 0x5fff, 0xc92e, 0x21, 0 + .dw 0x6040, 0xc92e, 0x607f, 0xc92e, 0x21, 0 + .dw 0x60c0, 0xc92e, 0x60ff, 0xc92e, 0x21, 0 + .dw 0x6140, 0xc92e, 0x617f, 0xc92e, 0x21, 0 + .dw 0x61c0, 0xc92e, 0x61ff, 0xc92e, 0x21, 0 + .dw 0x6240, 0xc92e, 0x627f, 0xc92e, 0x21, 0 + .dw 0x62c0, 0xc92e, 0x62ff, 0xc92e, 0x21, 0 + .dw 0x6340, 0xc92e, 0x637f, 0xc92e, 0x21, 0 + .dw 0x63c0, 0xc92e, 0x63ff, 0xc92e, 0x21, 0 + .dw 0x6440, 0xc92e, 0x647f, 0xc92e, 0x21, 0 + .dw 0x64c0, 0xc92e, 0x64ff, 0xc92e, 0x21, 0 + .dw 0x6540, 0xc92e, 0x657f, 0xc92e, 0x21, 0 + .dw 0x65c0, 0xc92e, 0x65ff, 0xc92e, 0x21, 0 + .dw 0x6640, 0xc92e, 0x667f, 0xc92e, 0x21, 0 + .dw 0x66c0, 0xc92e, 0x66ff, 0xc92e, 0x21, 0 + .dw 0x6740, 0xc92e, 0x677f, 0xc92e, 0x21, 0 + .dw 0x67c0, 0xc92e, 0x67ff, 0xc92e, 0x21, 0 + .dw 0x6840, 0xc92e, 0x687f, 0xc92e, 0x21, 0 + .dw 0x68c0, 0xc92e, 0x68ff, 0xc92e, 0x21, 0 + .dw 0x6940, 0xc92e, 0x697f, 0xc92e, 0x21, 0 + .dw 0x69c0, 0xc92e, 0x69ff, 0xc92e, 0x21, 0 + .dw 0x6a40, 0xc92e, 0x6a7f, 0xc92e, 0x21, 0 + .dw 0x6ac0, 0xc92e, 0x6aff, 0xc92e, 0x21, 0 + .dw 0x6b40, 0xc92e, 0x6b7f, 0xc92e, 0x21, 0 + .dw 0x6bc0, 0xc92e, 0x6bff, 0xc92e, 0x21, 0 + .dw 0x6c40, 0xc92e, 0x6c7f, 0xc92e, 0x21, 0 + .dw 0x6cc0, 0xc92e, 0x6cff, 0xc92e, 0x21, 0 + .dw 0x6d40, 0xc92e, 0x6d7f, 0xc92e, 0x21, 0 + .dw 0x6dc0, 0xc92e, 0x6dff, 0xc92e, 0x21, 0 + .dw 0x6e40, 0xc92e, 0x6e7f, 0xc92e, 0x21, 0 + .dw 0x6ec0, 0xc92e, 0x6eff, 0xc92e, 0x21, 0 + .dw 0x6f40, 0xc92e, 0x6f7f, 0xc92e, 0x21, 0 + .dw 0x6fc0, 0xc92e, 0x6fff, 0xc92e, 0x21, 0 + .dw 0x7040, 0xc92e, 0x707f, 0xc92e, 0x21, 0 + .dw 0x70c0, 0xc92e, 0x70ff, 0xc92e, 0x21, 0 + .dw 0x7140, 0xc92e, 0x717f, 0xc92e, 0x21, 0 + .dw 0x71c0, 0xc92e, 0x71ff, 0xc92e, 0x21, 0 + .dw 0x7240, 0xc92e, 0x727f, 0xc92e, 0x21, 0 + .dw 0x72c0, 0xc92e, 0x72ff, 0xc92e, 0x21, 0 + .dw 0x7340, 0xc92e, 0x737f, 0xc92e, 0x21, 0 + .dw 0x73c0, 0xc92e, 0x73ff, 0xc92e, 0x21, 0 + .dw 0x7440, 0xc92e, 0x747f, 0xc92e, 0x21, 0 + .dw 0x74c0, 0xc92e, 0x74ff, 0xc92e, 0x21, 0 + .dw 0x7540, 0xc92e, 0x757f, 0xc92e, 0x21, 0 + .dw 0x75c0, 0xc92e, 0x75ff, 0xc92e, 0x21, 0 + .dw 0x7640, 0xc92e, 0x767f, 0xc92e, 0x21, 0 + .dw 0x76c0, 0xc92e, 0x76ff, 0xc92e, 0x21, 0 + .dw 0x7740, 0xc92e, 0x777f, 0xc92e, 0x21, 0 + .dw 0x77c0, 0xc92e, 0x77ff, 0xc92e, 0x21, 0 + .dw 0x7840, 0xc92e, 0x787f, 0xc92e, 0x21, 0 + .dw 0x78c0, 0xc92e, 0x78ff, 0xc92e, 0x21, 0 + .dw 0x7940, 0xc92e, 0x797f, 0xc92e, 0x21, 0 + .dw 0x79c0, 0xc92e, 0x7fff, 0xc92e, 0x21, 0 + .dw 0x8040, 0xc92e, 0x807f, 0xc92e, 0x21, 0 + .dw 0x80c0, 0xc92e, 0x80ff, 0xc92e, 0x21, 0 + .dw 0x8140, 0xc92e, 0x817f, 0xc92e, 0x21, 0 + .dw 0x81c0, 0xc92e, 0x81ff, 0xc92e, 0x21, 0 + .dw 0x8240, 0xc92e, 0x827f, 0xc92e, 0x21, 0 + .dw 0x82c0, 0xc92e, 0x82ff, 0xc92e, 0x21, 0 + .dw 0x8340, 0xc92e, 0x837f, 0xc92e, 0x21, 0 + .dw 0x83c0, 0xc92e, 0x83ff, 0xc92e, 0x21, 0 + .dw 0x8440, 0xc92e, 0x847f, 0xc92e, 0x21, 0 + .dw 0x84c0, 0xc92e, 0x84ff, 0xc92e, 0x21, 0 + .dw 0x8540, 0xc92e, 0x857f, 0xc92e, 0x21, 0 + .dw 0x85c0, 0xc92e, 0x85ff, 0xc92e, 0x21, 0 + .dw 0x8640, 0xc92e, 0x867f, 0xc92e, 0x21, 0 + .dw 0x86c0, 0xc92e, 0x86ff, 0xc92e, 0x21, 0 + .dw 0x8740, 0xc92e, 0x877f, 0xc92e, 0x21, 0 + .dw 0x87c0, 0xc92e, 0x87ff, 0xc92e, 0x21, 0 + .dw 0x8840, 0xc92e, 0x887f, 0xc92e, 0x21, 0 + .dw 0x88c0, 0xc92e, 0x88ff, 0xc92e, 0x21, 0 + .dw 0x8940, 0xc92e, 0x897f, 0xc92e, 0x21, 0 + .dw 0x89c0, 0xc92e, 0x89ff, 0xc92e, 0x21, 0 + .dw 0x8a40, 0xc92e, 0x8a7f, 0xc92e, 0x21, 0 + .dw 0x8ac0, 0xc92e, 0x8aff, 0xc92e, 0x21, 0 + .dw 0x8b40, 0xc92e, 0x8b7f, 0xc92e, 0x21, 0 + .dw 0x8bc0, 0xc92e, 0x8bff, 0xc92e, 0x21, 0 + .dw 0x8c40, 0xc92e, 0x8c7f, 0xc92e, 0x21, 0 + .dw 0x8cc0, 0xc92e, 0x8cff, 0xc92e, 0x21, 0 + .dw 0x8d40, 0xc92e, 0x8d7f, 0xc92e, 0x21, 0 + .dw 0x8dc0, 0xc92e, 0x8dff, 0xc92e, 0x21, 0 + .dw 0x8e40, 0xc92e, 0x8e7f, 0xc92e, 0x21, 0 + .dw 0x8ec0, 0xc92e, 0x8eff, 0xc92e, 0x21, 0 + .dw 0x8f40, 0xc92e, 0x8f7f, 0xc92e, 0x21, 0 + .dw 0x8fc0, 0xc92e, 0x8fff, 0xc92e, 0x21, 0 + .dw 0x9040, 0xc92e, 0x907f, 0xc92e, 0x21, 0 + .dw 0x90c0, 0xc92e, 0x90ff, 0xc92e, 0x21, 0 + .dw 0x9140, 0xc92e, 0x917f, 0xc92e, 0x21, 0 + .dw 0x91c0, 0xc92e, 0x91ff, 0xc92e, 0x21, 0 + .dw 0x9240, 0xc92e, 0x927f, 0xc92e, 0x21, 0 + .dw 0x92c0, 0xc92e, 0x92ff, 0xc92e, 0x21, 0 + .dw 0x9340, 0xc92e, 0x937f, 0xc92e, 0x21, 0 + .dw 0x93c0, 0xc92e, 0x93ff, 0xc92e, 0x21, 0 + .dw 0x9440, 0xc92e, 0x947f, 0xc92e, 0x21, 0 + .dw 0x94c0, 0xc92e, 0x94ff, 0xc92e, 0x21, 0 + .dw 0x9540, 0xc92e, 0x957f, 0xc92e, 0x21, 0 + .dw 0x95c0, 0xc92e, 0x95ff, 0xc92e, 0x21, 0 + .dw 0x9640, 0xc92e, 0x967f, 0xc92e, 0x21, 0 + .dw 0x96c0, 0xc92e, 0x96ff, 0xc92e, 0x21, 0 + .dw 0x9740, 0xc92e, 0x977f, 0xc92e, 0x21, 0 + .dw 0x97c0, 0xc92e, 0x97ff, 0xc92e, 0x21, 0 + .dw 0x9840, 0xc92e, 0x987f, 0xc92e, 0x21, 0 + .dw 0x98c0, 0xc92e, 0x98ff, 0xc92e, 0x21, 0 + .dw 0x9940, 0xc92e, 0x997f, 0xc92e, 0x21, 0 + .dw 0x99c0, 0xc92e, 0x9fff, 0xc92e, 0x21, 0 + .dw 0xa040, 0xc92e, 0xa07f, 0xc92e, 0x21, 0 + .dw 0xa0c0, 0xc92e, 0xa0ff, 0xc92e, 0x21, 0 + .dw 0xa140, 0xc92e, 0xa17f, 0xc92e, 0x21, 0 + .dw 0xa1c0, 0xc92e, 0xa1ff, 0xc92e, 0x21, 0 + .dw 0xa240, 0xc92e, 0xa27f, 0xc92e, 0x21, 0 + .dw 0xa2c0, 0xc92e, 0xa2ff, 0xc92e, 0x21, 0 + .dw 0xa340, 0xc92e, 0xa37f, 0xc92e, 0x21, 0 + .dw 0xa3c0, 0xc92e, 0xa3ff, 0xc92e, 0x21, 0 + .dw 0xa440, 0xc92e, 0xa47f, 0xc92e, 0x21, 0 + .dw 0xa4c0, 0xc92e, 0xa4ff, 0xc92e, 0x21, 0 + .dw 0xa540, 0xc92e, 0xa57f, 0xc92e, 0x21, 0 + .dw 0xa5c0, 0xc92e, 0xa5ff, 0xc92e, 0x21, 0 + .dw 0xa640, 0xc92e, 0xa67f, 0xc92e, 0x21, 0 + .dw 0xa6c0, 0xc92e, 0xa6ff, 0xc92e, 0x21, 0 + .dw 0xa740, 0xc92e, 0xa77f, 0xc92e, 0x21, 0 + .dw 0xa7c0, 0xc92e, 0xa7ff, 0xc92e, 0x21, 0 + .dw 0xa840, 0xc92e, 0xa87f, 0xc92e, 0x21, 0 + .dw 0xa8c0, 0xc92e, 0xa8ff, 0xc92e, 0x21, 0 + .dw 0xa940, 0xc92e, 0xa97f, 0xc92e, 0x21, 0 + .dw 0xa9c0, 0xc92e, 0xa9ff, 0xc92e, 0x21, 0 + .dw 0xaa40, 0xc92e, 0xaa7f, 0xc92e, 0x21, 0 + .dw 0xaac0, 0xc92e, 0xaaff, 0xc92e, 0x21, 0 + .dw 0xab40, 0xc92e, 0xab7f, 0xc92e, 0x21, 0 + .dw 0xabc0, 0xc92e, 0xabff, 0xc92e, 0x21, 0 + .dw 0xac40, 0xc92e, 0xac7f, 0xc92e, 0x21, 0 + .dw 0xacc0, 0xc92e, 0xacff, 0xc92e, 0x21, 0 + .dw 0xad40, 0xc92e, 0xad7f, 0xc92e, 0x21, 0 + .dw 0xadc0, 0xc92e, 0xadff, 0xc92e, 0x21, 0 + .dw 0xae40, 0xc92e, 0xae7f, 0xc92e, 0x21, 0 + .dw 0xaec0, 0xc92e, 0xaeff, 0xc92e, 0x21, 0 + .dw 0xaf40, 0xc92e, 0xaf7f, 0xc92e, 0x21, 0 + .dw 0xafc0, 0xc92e, 0xafff, 0xc92e, 0x21, 0 + .dw 0xb040, 0xc92e, 0xb07f, 0xc92e, 0x21, 0 + .dw 0xb0c0, 0xc92e, 0xb0ff, 0xc92e, 0x21, 0 + .dw 0xb140, 0xc92e, 0xb17f, 0xc92e, 0x21, 0 + .dw 0xb1c0, 0xc92e, 0xb1ff, 0xc92e, 0x21, 0 + .dw 0xb240, 0xc92e, 0xb27f, 0xc92e, 0x21, 0 + .dw 0xb2c0, 0xc92e, 0xb2ff, 0xc92e, 0x21, 0 + .dw 0xb340, 0xc92e, 0xb37f, 0xc92e, 0x21, 0 + .dw 0xb3c0, 0xc92e, 0xb3ff, 0xc92e, 0x21, 0 + .dw 0xb440, 0xc92e, 0xb47f, 0xc92e, 0x21, 0 + .dw 0xb4c0, 0xc92e, 0xb4ff, 0xc92e, 0x21, 0 + .dw 0xb540, 0xc92e, 0xb57f, 0xc92e, 0x21, 0 + .dw 0xb5c0, 0xc92e, 0xb5ff, 0xc92e, 0x21, 0 + .dw 0xb640, 0xc92e, 0xb67f, 0xc92e, 0x21, 0 + .dw 0xb6c0, 0xc92e, 0xb6ff, 0xc92e, 0x21, 0 + .dw 0xb740, 0xc92e, 0xb77f, 0xc92e, 0x21, 0 + .dw 0xb7c0, 0xc92e, 0xb7ff, 0xc92e, 0x21, 0 + .dw 0xb840, 0xc92e, 0xb87f, 0xc92e, 0x21, 0 + .dw 0xb8c0, 0xc92e, 0xb8ff, 0xc92e, 0x21, 0 + .dw 0xb940, 0xc92e, 0xb97f, 0xc92e, 0x21, 0 + .dw 0xb9c0, 0xc92e, 0xbfff, 0xc92e, 0x21, 0 + .dw 0xc040, 0xc92e, 0xc07f, 0xc92e, 0x21, 0 + .dw 0xc0c0, 0xc92e, 0xc0ff, 0xc92e, 0x21, 0 + .dw 0xc140, 0xc92e, 0xc17f, 0xc92e, 0x21, 0 + .dw 0xc1c0, 0xc92e, 0xc1ff, 0xc92e, 0x21, 0 + .dw 0xc240, 0xc92e, 0xc27f, 0xc92e, 0x21, 0 + .dw 0xc2c0, 0xc92e, 0xc2ff, 0xc92e, 0x21, 0 + .dw 0xc340, 0xc92e, 0xc37f, 0xc92e, 0x21, 0 + .dw 0xc3c0, 0xc92e, 0xc3ff, 0xc92e, 0x21, 0 + .dw 0xc440, 0xc92e, 0xc47f, 0xc92e, 0x21, 0 + .dw 0xc4c0, 0xc92e, 0xc4ff, 0xc92e, 0x21, 0 + .dw 0xc540, 0xc92e, 0xc57f, 0xc92e, 0x21, 0 + .dw 0xc5c0, 0xc92e, 0xc5ff, 0xc92e, 0x21, 0 + .dw 0xc640, 0xc92e, 0xc67f, 0xc92e, 0x21, 0 + .dw 0xc6c0, 0xc92e, 0xc6ff, 0xc92e, 0x21, 0 + .dw 0xc740, 0xc92e, 0xc77f, 0xc92e, 0x21, 0 + .dw 0xc7c0, 0xc92e, 0xc7ff, 0xc92e, 0x21, 0 + .dw 0xc840, 0xc92e, 0xc87f, 0xc92e, 0x21, 0 + .dw 0xc8c0, 0xc92e, 0xc8ff, 0xc92e, 0x21, 0 + .dw 0xc940, 0xc92e, 0xc97f, 0xc92e, 0x21, 0 + .dw 0xc9c0, 0xc92e, 0xc9ff, 0xc92e, 0x21, 0 + .dw 0xca40, 0xc92e, 0xca7f, 0xc92e, 0x21, 0 + .dw 0xcac0, 0xc92e, 0xcaff, 0xc92e, 0x21, 0 + .dw 0xcb40, 0xc92e, 0xcb7f, 0xc92e, 0x21, 0 + .dw 0xcbc0, 0xc92e, 0xcbff, 0xc92e, 0x21, 0 + .dw 0xcc40, 0xc92e, 0xcc7f, 0xc92e, 0x21, 0 + .dw 0xccc0, 0xc92e, 0xccff, 0xc92e, 0x21, 0 + .dw 0xcd40, 0xc92e, 0xcd7f, 0xc92e, 0x21, 0 + .dw 0xcdc0, 0xc92e, 0xcdff, 0xc92e, 0x21, 0 + .dw 0xce40, 0xc92e, 0xce7f, 0xc92e, 0x21, 0 + .dw 0xcec0, 0xc92e, 0xceff, 0xc92e, 0x21, 0 + .dw 0xcf40, 0xc92e, 0xcf7f, 0xc92e, 0x21, 0 + .dw 0xcfc0, 0xc92e, 0xcfff, 0xc92e, 0x21, 0 + .dw 0xd040, 0xc92e, 0xd07f, 0xc92e, 0x21, 0 + .dw 0xd0c0, 0xc92e, 0xd0ff, 0xc92e, 0x21, 0 + .dw 0xd140, 0xc92e, 0xd17f, 0xc92e, 0x21, 0 + .dw 0xd1c0, 0xc92e, 0xd1ff, 0xc92e, 0x21, 0 + .dw 0xd240, 0xc92e, 0xd27f, 0xc92e, 0x21, 0 + .dw 0xd2c0, 0xc92e, 0xd2ff, 0xc92e, 0x21, 0 + .dw 0xd340, 0xc92e, 0xd37f, 0xc92e, 0x21, 0 + .dw 0xd3c0, 0xc92e, 0xd3ff, 0xc92e, 0x21, 0 + .dw 0xd440, 0xc92e, 0xd47f, 0xc92e, 0x21, 0 + .dw 0xd4c0, 0xc92e, 0xd4ff, 0xc92e, 0x21, 0 + .dw 0xd540, 0xc92e, 0xd57f, 0xc92e, 0x21, 0 + .dw 0xd5c0, 0xc92e, 0xd5ff, 0xc92e, 0x21, 0 + .dw 0xd640, 0xc92e, 0xd67f, 0xc92e, 0x21, 0 + .dw 0xd6c0, 0xc92e, 0xd6ff, 0xc92e, 0x21, 0 + .dw 0xd740, 0xc92e, 0xd77f, 0xc92e, 0x21, 0 + .dw 0xd7c0, 0xc92e, 0xd7ff, 0xc92e, 0x21, 0 + .dw 0xd840, 0xc92e, 0xd87f, 0xc92e, 0x21, 0 + .dw 0xd8c0, 0xc92e, 0xd8ff, 0xc92e, 0x21, 0 + .dw 0xd940, 0xc92e, 0xd97f, 0xc92e, 0x21, 0 + .dw 0xd9c0, 0xc92e, 0xdfff, 0xc92e, 0x21, 0 + .dw 0xe040, 0xc92e, 0xe07f, 0xc92e, 0x21, 0 + .dw 0xe0c0, 0xc92e, 0xe0ff, 0xc92e, 0x21, 0 + .dw 0xe140, 0xc92e, 0xe17f, 0xc92e, 0x21, 0 + .dw 0xe1c0, 0xc92e, 0xe1ff, 0xc92e, 0x21, 0 + .dw 0xe240, 0xc92e, 0xe27f, 0xc92e, 0x21, 0 + .dw 0xe2c0, 0xc92e, 0xe2ff, 0xc92e, 0x21, 0 + .dw 0xe340, 0xc92e, 0xe37f, 0xc92e, 0x21, 0 + .dw 0xe3c0, 0xc92e, 0xe3ff, 0xc92e, 0x21, 0 + .dw 0xe440, 0xc92e, 0xe47f, 0xc92e, 0x21, 0 + .dw 0xe4c0, 0xc92e, 0xe4ff, 0xc92e, 0x21, 0 + .dw 0xe540, 0xc92e, 0xe57f, 0xc92e, 0x21, 0 + .dw 0xe5c0, 0xc92e, 0xe5ff, 0xc92e, 0x21, 0 + .dw 0xe640, 0xc92e, 0xe67f, 0xc92e, 0x21, 0 + .dw 0xe6c0, 0xc92e, 0xe6ff, 0xc92e, 0x21, 0 + .dw 0xe740, 0xc92e, 0xe77f, 0xc92e, 0x21, 0 + .dw 0xe7c0, 0xc92e, 0xe7ff, 0xc92e, 0x21, 0 + .dw 0xe840, 0xc92e, 0xe87f, 0xc92e, 0x21, 0 + .dw 0xe8c0, 0xc92e, 0xe8ff, 0xc92e, 0x21, 0 + .dw 0xe940, 0xc92e, 0xe97f, 0xc92e, 0x21, 0 + .dw 0xe9c0, 0xc92e, 0xe9ff, 0xc92e, 0x21, 0 + .dw 0xea40, 0xc92e, 0xea7f, 0xc92e, 0x21, 0 + .dw 0xeac0, 0xc92e, 0xeaff, 0xc92e, 0x21, 0 + .dw 0xeb40, 0xc92e, 0xeb7f, 0xc92e, 0x21, 0 + .dw 0xebc0, 0xc92e, 0xebff, 0xc92e, 0x21, 0 + .dw 0xec40, 0xc92e, 0xec7f, 0xc92e, 0x21, 0 + .dw 0xecc0, 0xc92e, 0xecff, 0xc92e, 0x21, 0 + .dw 0xed40, 0xc92e, 0xed7f, 0xc92e, 0x21, 0 + .dw 0xedc0, 0xc92e, 0xedff, 0xc92e, 0x21, 0 + .dw 0xee40, 0xc92e, 0xee7f, 0xc92e, 0x21, 0 + .dw 0xeec0, 0xc92e, 0xeeff, 0xc92e, 0x21, 0 + .dw 0xef40, 0xc92e, 0xef7f, 0xc92e, 0x21, 0 + .dw 0xefc0, 0xc92e, 0xefff, 0xc92e, 0x21, 0 + .dw 0xf040, 0xc92e, 0xf07f, 0xc92e, 0x21, 0 + .dw 0xf0c0, 0xc92e, 0xf0ff, 0xc92e, 0x21, 0 + .dw 0xf140, 0xc92e, 0xf17f, 0xc92e, 0x21, 0 + .dw 0xf1c0, 0xc92e, 0xf1ff, 0xc92e, 0x21, 0 + .dw 0xf240, 0xc92e, 0xf27f, 0xc92e, 0x21, 0 + .dw 0xf2c0, 0xc92e, 0xf2ff, 0xc92e, 0x21, 0 + .dw 0xf340, 0xc92e, 0xf37f, 0xc92e, 0x21, 0 + .dw 0xf3c0, 0xc92e, 0xf3ff, 0xc92e, 0x21, 0 + .dw 0xf440, 0xc92e, 0xf47f, 0xc92e, 0x21, 0 + .dw 0xf4c0, 0xc92e, 0xf4ff, 0xc92e, 0x21, 0 + .dw 0xf540, 0xc92e, 0xf57f, 0xc92e, 0x21, 0 + .dw 0xf5c0, 0xc92e, 0xf5ff, 0xc92e, 0x21, 0 + .dw 0xf640, 0xc92e, 0xf67f, 0xc92e, 0x21, 0 + .dw 0xf6c0, 0xc92e, 0xf6ff, 0xc92e, 0x21, 0 + .dw 0xf740, 0xc92e, 0xf77f, 0xc92e, 0x21, 0 + .dw 0xf7c0, 0xc92e, 0xf7ff, 0xc92e, 0x21, 0 + .dw 0xf840, 0xc92e, 0xf87f, 0xc92e, 0x21, 0 + .dw 0xf8c0, 0xc92e, 0xf8ff, 0xc92e, 0x21, 0 + .dw 0xf940, 0xc92e, 0xf97f, 0xc92e, 0x21, 0 + .dw 0xf9c0, 0xc92e, 0xffff, 0xc92e, 0x21, 0 + .dw 0x0040, 0xc92f, 0x007f, 0xc92f, 0x21, 0 + .dw 0x00c0, 0xc92f, 0x00ff, 0xc92f, 0x21, 0 + .dw 0x0140, 0xc92f, 0x017f, 0xc92f, 0x21, 0 + .dw 0x01c0, 0xc92f, 0x01ff, 0xc92f, 0x21, 0 + .dw 0x0240, 0xc92f, 0x027f, 0xc92f, 0x21, 0 + .dw 0x02c0, 0xc92f, 0x02ff, 0xc92f, 0x21, 0 + .dw 0x0340, 0xc92f, 0x037f, 0xc92f, 0x21, 0 + .dw 0x03c0, 0xc92f, 0x03ff, 0xc92f, 0x21, 0 + .dw 0x0440, 0xc92f, 0x047f, 0xc92f, 0x21, 0 + .dw 0x04c0, 0xc92f, 0x04ff, 0xc92f, 0x21, 0 + .dw 0x0540, 0xc92f, 0x057f, 0xc92f, 0x21, 0 + .dw 0x05c0, 0xc92f, 0x05ff, 0xc92f, 0x21, 0 + .dw 0x0640, 0xc92f, 0x067f, 0xc92f, 0x21, 0 + .dw 0x06c0, 0xc92f, 0x06ff, 0xc92f, 0x21, 0 + .dw 0x0740, 0xc92f, 0x077f, 0xc92f, 0x21, 0 + .dw 0x07c0, 0xc92f, 0x07ff, 0xc92f, 0x21, 0 + .dw 0x0840, 0xc92f, 0x087f, 0xc92f, 0x21, 0 + .dw 0x08c0, 0xc92f, 0x08ff, 0xc92f, 0x21, 0 + .dw 0x0940, 0xc92f, 0x097f, 0xc92f, 0x21, 0 + .dw 0x09c0, 0xc92f, 0x09ff, 0xc92f, 0x21, 0 + .dw 0x0a40, 0xc92f, 0x0a7f, 0xc92f, 0x21, 0 + .dw 0x0ac0, 0xc92f, 0x0aff, 0xc92f, 0x21, 0 + .dw 0x0b40, 0xc92f, 0x0b7f, 0xc92f, 0x21, 0 + .dw 0x0bc0, 0xc92f, 0x0bff, 0xc92f, 0x21, 0 + .dw 0x0c40, 0xc92f, 0x0c7f, 0xc92f, 0x21, 0 + .dw 0x0cc0, 0xc92f, 0x0cff, 0xc92f, 0x21, 0 + .dw 0x0d40, 0xc92f, 0x0d7f, 0xc92f, 0x21, 0 + .dw 0x0dc0, 0xc92f, 0x0dff, 0xc92f, 0x21, 0 + .dw 0x0e40, 0xc92f, 0x0e7f, 0xc92f, 0x21, 0 + .dw 0x0ec0, 0xc92f, 0x0eff, 0xc92f, 0x21, 0 + .dw 0x0f40, 0xc92f, 0x0f7f, 0xc92f, 0x21, 0 + .dw 0x0fc0, 0xc92f, 0x0fff, 0xc92f, 0x21, 0 + .dw 0x1040, 0xc92f, 0x107f, 0xc92f, 0x21, 0 + .dw 0x10c0, 0xc92f, 0x10ff, 0xc92f, 0x21, 0 + .dw 0x1140, 0xc92f, 0x117f, 0xc92f, 0x21, 0 + .dw 0x11c0, 0xc92f, 0x11ff, 0xc92f, 0x21, 0 + .dw 0x1240, 0xc92f, 0x127f, 0xc92f, 0x21, 0 + .dw 0x12c0, 0xc92f, 0x12ff, 0xc92f, 0x21, 0 + .dw 0x1340, 0xc92f, 0x137f, 0xc92f, 0x21, 0 + .dw 0x13c0, 0xc92f, 0x13ff, 0xc92f, 0x21, 0 + .dw 0x1440, 0xc92f, 0x147f, 0xc92f, 0x21, 0 + .dw 0x14c0, 0xc92f, 0x14ff, 0xc92f, 0x21, 0 + .dw 0x1540, 0xc92f, 0x157f, 0xc92f, 0x21, 0 + .dw 0x15c0, 0xc92f, 0x15ff, 0xc92f, 0x21, 0 + .dw 0x1640, 0xc92f, 0x167f, 0xc92f, 0x21, 0 + .dw 0x16c0, 0xc92f, 0x16ff, 0xc92f, 0x21, 0 + .dw 0x1740, 0xc92f, 0x177f, 0xc92f, 0x21, 0 + .dw 0x17c0, 0xc92f, 0x17ff, 0xc92f, 0x21, 0 + .dw 0x1840, 0xc92f, 0x187f, 0xc92f, 0x21, 0 + .dw 0x18c0, 0xc92f, 0x18ff, 0xc92f, 0x21, 0 + .dw 0x1940, 0xc92f, 0x197f, 0xc92f, 0x21, 0 + .dw 0x19c0, 0xc92f, 0x1fff, 0xc92f, 0x21, 0 + .dw 0x2040, 0xc92f, 0x207f, 0xc92f, 0x21, 0 + .dw 0x20c0, 0xc92f, 0x20ff, 0xc92f, 0x21, 0 + .dw 0x2140, 0xc92f, 0x217f, 0xc92f, 0x21, 0 + .dw 0x21c0, 0xc92f, 0x21ff, 0xc92f, 0x21, 0 + .dw 0x2240, 0xc92f, 0x227f, 0xc92f, 0x21, 0 + .dw 0x22c0, 0xc92f, 0x22ff, 0xc92f, 0x21, 0 + .dw 0x2340, 0xc92f, 0x237f, 0xc92f, 0x21, 0 + .dw 0x23c0, 0xc92f, 0x23ff, 0xc92f, 0x21, 0 + .dw 0x2440, 0xc92f, 0x247f, 0xc92f, 0x21, 0 + .dw 0x24c0, 0xc92f, 0x24ff, 0xc92f, 0x21, 0 + .dw 0x2540, 0xc92f, 0x257f, 0xc92f, 0x21, 0 + .dw 0x25c0, 0xc92f, 0x25ff, 0xc92f, 0x21, 0 + .dw 0x2640, 0xc92f, 0x267f, 0xc92f, 0x21, 0 + .dw 0x26c0, 0xc92f, 0x26ff, 0xc92f, 0x21, 0 + .dw 0x2740, 0xc92f, 0x277f, 0xc92f, 0x21, 0 + .dw 0x27c0, 0xc92f, 0x27ff, 0xc92f, 0x21, 0 + .dw 0x2840, 0xc92f, 0x287f, 0xc92f, 0x21, 0 + .dw 0x28c0, 0xc92f, 0x28ff, 0xc92f, 0x21, 0 + .dw 0x2940, 0xc92f, 0x297f, 0xc92f, 0x21, 0 + .dw 0x29c0, 0xc92f, 0x29ff, 0xc92f, 0x21, 0 + .dw 0x2a40, 0xc92f, 0x2a7f, 0xc92f, 0x21, 0 + .dw 0x2ac0, 0xc92f, 0x2aff, 0xc92f, 0x21, 0 + .dw 0x2b40, 0xc92f, 0x2b7f, 0xc92f, 0x21, 0 + .dw 0x2bc0, 0xc92f, 0x2bff, 0xc92f, 0x21, 0 + .dw 0x2c40, 0xc92f, 0x2c7f, 0xc92f, 0x21, 0 + .dw 0x2cc0, 0xc92f, 0x2cff, 0xc92f, 0x21, 0 + .dw 0x2d40, 0xc92f, 0x2d7f, 0xc92f, 0x21, 0 + .dw 0x2dc0, 0xc92f, 0x2dff, 0xc92f, 0x21, 0 + .dw 0x2e40, 0xc92f, 0x2e7f, 0xc92f, 0x21, 0 + .dw 0x2ec0, 0xc92f, 0x2eff, 0xc92f, 0x21, 0 + .dw 0x2f40, 0xc92f, 0x2f7f, 0xc92f, 0x21, 0 + .dw 0x2fc0, 0xc92f, 0x2fff, 0xc92f, 0x21, 0 + .dw 0x3040, 0xc92f, 0x307f, 0xc92f, 0x21, 0 + .dw 0x30c0, 0xc92f, 0x30ff, 0xc92f, 0x21, 0 + .dw 0x3140, 0xc92f, 0x317f, 0xc92f, 0x21, 0 + .dw 0x31c0, 0xc92f, 0x31ff, 0xc92f, 0x21, 0 + .dw 0x3240, 0xc92f, 0x327f, 0xc92f, 0x21, 0 + .dw 0x32c0, 0xc92f, 0x32ff, 0xc92f, 0x21, 0 + .dw 0x3340, 0xc92f, 0x337f, 0xc92f, 0x21, 0 + .dw 0x33c0, 0xc92f, 0x33ff, 0xc92f, 0x21, 0 + .dw 0x3440, 0xc92f, 0x347f, 0xc92f, 0x21, 0 + .dw 0x34c0, 0xc92f, 0x34ff, 0xc92f, 0x21, 0 + .dw 0x3540, 0xc92f, 0x357f, 0xc92f, 0x21, 0 + .dw 0x35c0, 0xc92f, 0x35ff, 0xc92f, 0x21, 0 + .dw 0x3640, 0xc92f, 0x367f, 0xc92f, 0x21, 0 + .dw 0x36c0, 0xc92f, 0x36ff, 0xc92f, 0x21, 0 + .dw 0x3740, 0xc92f, 0x377f, 0xc92f, 0x21, 0 + .dw 0x37c0, 0xc92f, 0x37ff, 0xc92f, 0x21, 0 + .dw 0x3840, 0xc92f, 0x387f, 0xc92f, 0x21, 0 + .dw 0x38c0, 0xc92f, 0x38ff, 0xc92f, 0x21, 0 + .dw 0x3940, 0xc92f, 0x397f, 0xc92f, 0x21, 0 + .dw 0x39c0, 0xc92f, 0x1fff, 0xc930, 0x21, 0 + .dw 0x3a00, 0xc930, 0x5fff, 0xc930, 0x21, 0 + .dw 0x7a00, 0xc930, 0x9fff, 0xc930, 0x21, 0 + .dw 0xba00, 0xc930, 0xdfff, 0xc930, 0x21, 0 + .dw 0xfa00, 0xc930, 0x1fff, 0xc931, 0x21, 0 + .dw 0x3a00, 0xc931, 0x5fff, 0xc931, 0x21, 0 + .dw 0x7a00, 0xc931, 0x9fff, 0xc931, 0x21, 0 + .dw 0xba00, 0xc931, 0xdfff, 0xc931, 0x21, 0 + .dw 0xfa00, 0xc931, 0x1fff, 0xc932, 0x21, 0 + .dw 0x3a00, 0xc932, 0x5fff, 0xc932, 0x21, 0 + .dw 0x7a00, 0xc932, 0x9fff, 0xc932, 0x21, 0 + .dw 0xba00, 0xc932, 0xdfff, 0xc932, 0x21, 0 + .dw 0xfa00, 0xc932, 0xffff, 0xc933, 0x21, 0 + .dw 0x1a00, 0xc934, 0x1fff, 0xc934, 0x21, 0 + .dw 0x3a00, 0xc934, 0x3fff, 0xc934, 0x21, 0 + .dw 0x5a00, 0xc934, 0x5fff, 0xc934, 0x21, 0 + .dw 0x7a00, 0xc934, 0x7fff, 0xc934, 0x21, 0 + .dw 0x9a00, 0xc934, 0x9fff, 0xc934, 0x21, 0 + .dw 0xba00, 0xc934, 0xbfff, 0xc934, 0x21, 0 + .dw 0xda00, 0xc934, 0xdfff, 0xc934, 0x21, 0 + .dw 0xfa00, 0xc934, 0xffff, 0xc934, 0x21, 0 + .dw 0x1a00, 0xc935, 0x1fff, 0xc935, 0x21, 0 + .dw 0x3a00, 0xc935, 0x3fff, 0xc935, 0x21, 0 + .dw 0x5a00, 0xc935, 0x5fff, 0xc935, 0x21, 0 + .dw 0x7a00, 0xc935, 0x7fff, 0xc935, 0x21, 0 + .dw 0x9a00, 0xc935, 0x9fff, 0xc935, 0x21, 0 + .dw 0xba00, 0xc935, 0xbfff, 0xc935, 0x21, 0 + .dw 0xda00, 0xc935, 0xdfff, 0xc935, 0x21, 0 + .dw 0xfa00, 0xc935, 0xffff, 0xc935, 0x21, 0 + .dw 0x1a00, 0xc936, 0x1fff, 0xc936, 0x21, 0 + .dw 0x3a00, 0xc936, 0x3fff, 0xc936, 0x21, 0 + .dw 0x5a00, 0xc936, 0x5fff, 0xc936, 0x21, 0 + .dw 0x7a00, 0xc936, 0x7fff, 0xc936, 0x21, 0 + .dw 0x9a00, 0xc936, 0x9fff, 0xc936, 0x21, 0 + .dw 0xba00, 0xc936, 0xbfff, 0xc936, 0x21, 0 + .dw 0xda00, 0xc936, 0xdfff, 0xc936, 0x21, 0 + .dw 0xfa00, 0xc936, 0xffff, 0xc936, 0x21, 0 + .dw 0x1a00, 0xc937, 0x1fff, 0xc937, 0x21, 0 + .dw 0x3a00, 0xc937, 0x1fff, 0xc938, 0x21, 0 + .dw 0x2040, 0xc938, 0x207f, 0xc938, 0x21, 0 + .dw 0x20c0, 0xc938, 0x20ff, 0xc938, 0x21, 0 + .dw 0x2140, 0xc938, 0x217f, 0xc938, 0x21, 0 + .dw 0x21c0, 0xc938, 0x21ff, 0xc938, 0x21, 0 + .dw 0x2240, 0xc938, 0x227f, 0xc938, 0x21, 0 + .dw 0x22c0, 0xc938, 0x22ff, 0xc938, 0x21, 0 + .dw 0x2340, 0xc938, 0x237f, 0xc938, 0x21, 0 + .dw 0x23c0, 0xc938, 0x23ff, 0xc938, 0x21, 0 + .dw 0x2440, 0xc938, 0x247f, 0xc938, 0x21, 0 + .dw 0x24c0, 0xc938, 0x24ff, 0xc938, 0x21, 0 + .dw 0x2540, 0xc938, 0x257f, 0xc938, 0x21, 0 + .dw 0x25c0, 0xc938, 0x25ff, 0xc938, 0x21, 0 + .dw 0x2640, 0xc938, 0x267f, 0xc938, 0x21, 0 + .dw 0x26c0, 0xc938, 0x26ff, 0xc938, 0x21, 0 + .dw 0x2740, 0xc938, 0x277f, 0xc938, 0x21, 0 + .dw 0x27c0, 0xc938, 0x27ff, 0xc938, 0x21, 0 + .dw 0x2840, 0xc938, 0x287f, 0xc938, 0x21, 0 + .dw 0x28c0, 0xc938, 0x28ff, 0xc938, 0x21, 0 + .dw 0x2940, 0xc938, 0x297f, 0xc938, 0x21, 0 + .dw 0x29c0, 0xc938, 0x29ff, 0xc938, 0x21, 0 + .dw 0x2a40, 0xc938, 0x2a7f, 0xc938, 0x21, 0 + .dw 0x2ac0, 0xc938, 0x2aff, 0xc938, 0x21, 0 + .dw 0x2b40, 0xc938, 0x2b7f, 0xc938, 0x21, 0 + .dw 0x2bc0, 0xc938, 0x2bff, 0xc938, 0x21, 0 + .dw 0x2c40, 0xc938, 0x2c7f, 0xc938, 0x21, 0 + .dw 0x2cc0, 0xc938, 0x2cff, 0xc938, 0x21, 0 + .dw 0x2d40, 0xc938, 0x2d7f, 0xc938, 0x21, 0 + .dw 0x2dc0, 0xc938, 0x2dff, 0xc938, 0x21, 0 + .dw 0x2e40, 0xc938, 0x2e7f, 0xc938, 0x21, 0 + .dw 0x2ec0, 0xc938, 0x2eff, 0xc938, 0x21, 0 + .dw 0x2f40, 0xc938, 0x2f7f, 0xc938, 0x21, 0 + .dw 0x2fc0, 0xc938, 0x2fff, 0xc938, 0x21, 0 + .dw 0x3040, 0xc938, 0x307f, 0xc938, 0x21, 0 + .dw 0x30c0, 0xc938, 0x30ff, 0xc938, 0x21, 0 + .dw 0x3140, 0xc938, 0x317f, 0xc938, 0x21, 0 + .dw 0x31c0, 0xc938, 0x31ff, 0xc938, 0x21, 0 + .dw 0x3240, 0xc938, 0x327f, 0xc938, 0x21, 0 + .dw 0x32c0, 0xc938, 0x32ff, 0xc938, 0x21, 0 + .dw 0x3340, 0xc938, 0x337f, 0xc938, 0x21, 0 + .dw 0x33c0, 0xc938, 0x33ff, 0xc938, 0x21, 0 + .dw 0x3440, 0xc938, 0x347f, 0xc938, 0x21, 0 + .dw 0x34c0, 0xc938, 0x34ff, 0xc938, 0x21, 0 + .dw 0x3540, 0xc938, 0x357f, 0xc938, 0x21, 0 + .dw 0x35c0, 0xc938, 0x35ff, 0xc938, 0x21, 0 + .dw 0x3640, 0xc938, 0x367f, 0xc938, 0x21, 0 + .dw 0x36c0, 0xc938, 0x36ff, 0xc938, 0x21, 0 + .dw 0x3740, 0xc938, 0x377f, 0xc938, 0x21, 0 + .dw 0x37c0, 0xc938, 0x37ff, 0xc938, 0x21, 0 + .dw 0x3840, 0xc938, 0x387f, 0xc938, 0x21, 0 + .dw 0x38c0, 0xc938, 0x38ff, 0xc938, 0x21, 0 + .dw 0x3940, 0xc938, 0x397f, 0xc938, 0x21, 0 + .dw 0x39c0, 0xc938, 0x5fff, 0xc938, 0x21, 0 + .dw 0x6040, 0xc938, 0x607f, 0xc938, 0x21, 0 + .dw 0x60c0, 0xc938, 0x60ff, 0xc938, 0x21, 0 + .dw 0x6140, 0xc938, 0x617f, 0xc938, 0x21, 0 + .dw 0x61c0, 0xc938, 0x61ff, 0xc938, 0x21, 0 + .dw 0x6240, 0xc938, 0x627f, 0xc938, 0x21, 0 + .dw 0x62c0, 0xc938, 0x62ff, 0xc938, 0x21, 0 + .dw 0x6340, 0xc938, 0x637f, 0xc938, 0x21, 0 + .dw 0x63c0, 0xc938, 0x63ff, 0xc938, 0x21, 0 + .dw 0x6440, 0xc938, 0x647f, 0xc938, 0x21, 0 + .dw 0x64c0, 0xc938, 0x64ff, 0xc938, 0x21, 0 + .dw 0x6540, 0xc938, 0x657f, 0xc938, 0x21, 0 + .dw 0x65c0, 0xc938, 0x65ff, 0xc938, 0x21, 0 + .dw 0x6640, 0xc938, 0x667f, 0xc938, 0x21, 0 + .dw 0x66c0, 0xc938, 0x66ff, 0xc938, 0x21, 0 + .dw 0x6740, 0xc938, 0x677f, 0xc938, 0x21, 0 + .dw 0x67c0, 0xc938, 0x67ff, 0xc938, 0x21, 0 + .dw 0x6840, 0xc938, 0x687f, 0xc938, 0x21, 0 + .dw 0x68c0, 0xc938, 0x68ff, 0xc938, 0x21, 0 + .dw 0x6940, 0xc938, 0x697f, 0xc938, 0x21, 0 + .dw 0x69c0, 0xc938, 0x69ff, 0xc938, 0x21, 0 + .dw 0x6a40, 0xc938, 0x6a7f, 0xc938, 0x21, 0 + .dw 0x6ac0, 0xc938, 0x6aff, 0xc938, 0x21, 0 + .dw 0x6b40, 0xc938, 0x6b7f, 0xc938, 0x21, 0 + .dw 0x6bc0, 0xc938, 0x6bff, 0xc938, 0x21, 0 + .dw 0x6c40, 0xc938, 0x6c7f, 0xc938, 0x21, 0 + .dw 0x6cc0, 0xc938, 0x6cff, 0xc938, 0x21, 0 + .dw 0x6d40, 0xc938, 0x6d7f, 0xc938, 0x21, 0 + .dw 0x6dc0, 0xc938, 0x6dff, 0xc938, 0x21, 0 + .dw 0x6e40, 0xc938, 0x6e7f, 0xc938, 0x21, 0 + .dw 0x6ec0, 0xc938, 0x6eff, 0xc938, 0x21, 0 + .dw 0x6f40, 0xc938, 0x6f7f, 0xc938, 0x21, 0 + .dw 0x6fc0, 0xc938, 0x6fff, 0xc938, 0x21, 0 + .dw 0x7040, 0xc938, 0x707f, 0xc938, 0x21, 0 + .dw 0x70c0, 0xc938, 0x70ff, 0xc938, 0x21, 0 + .dw 0x7140, 0xc938, 0x717f, 0xc938, 0x21, 0 + .dw 0x71c0, 0xc938, 0x71ff, 0xc938, 0x21, 0 + .dw 0x7240, 0xc938, 0x727f, 0xc938, 0x21, 0 + .dw 0x72c0, 0xc938, 0x72ff, 0xc938, 0x21, 0 + .dw 0x7340, 0xc938, 0x737f, 0xc938, 0x21, 0 + .dw 0x73c0, 0xc938, 0x73ff, 0xc938, 0x21, 0 + .dw 0x7440, 0xc938, 0x747f, 0xc938, 0x21, 0 + .dw 0x74c0, 0xc938, 0x74ff, 0xc938, 0x21, 0 + .dw 0x7540, 0xc938, 0x757f, 0xc938, 0x21, 0 + .dw 0x75c0, 0xc938, 0x75ff, 0xc938, 0x21, 0 + .dw 0x7640, 0xc938, 0x767f, 0xc938, 0x21, 0 + .dw 0x76c0, 0xc938, 0x76ff, 0xc938, 0x21, 0 + .dw 0x7740, 0xc938, 0x777f, 0xc938, 0x21, 0 + .dw 0x77c0, 0xc938, 0x77ff, 0xc938, 0x21, 0 + .dw 0x7840, 0xc938, 0x787f, 0xc938, 0x21, 0 + .dw 0x78c0, 0xc938, 0x78ff, 0xc938, 0x21, 0 + .dw 0x7940, 0xc938, 0x797f, 0xc938, 0x21, 0 + .dw 0x79c0, 0xc938, 0x9fff, 0xc938, 0x21, 0 + .dw 0xa040, 0xc938, 0xa07f, 0xc938, 0x21, 0 + .dw 0xa0c0, 0xc938, 0xa0ff, 0xc938, 0x21, 0 + .dw 0xa140, 0xc938, 0xa17f, 0xc938, 0x21, 0 + .dw 0xa1c0, 0xc938, 0xa1ff, 0xc938, 0x21, 0 + .dw 0xa240, 0xc938, 0xa27f, 0xc938, 0x21, 0 + .dw 0xa2c0, 0xc938, 0xa2ff, 0xc938, 0x21, 0 + .dw 0xa340, 0xc938, 0xa37f, 0xc938, 0x21, 0 + .dw 0xa3c0, 0xc938, 0xa3ff, 0xc938, 0x21, 0 + .dw 0xa440, 0xc938, 0xa47f, 0xc938, 0x21, 0 + .dw 0xa4c0, 0xc938, 0xa4ff, 0xc938, 0x21, 0 + .dw 0xa540, 0xc938, 0xa57f, 0xc938, 0x21, 0 + .dw 0xa5c0, 0xc938, 0xa5ff, 0xc938, 0x21, 0 + .dw 0xa640, 0xc938, 0xa67f, 0xc938, 0x21, 0 + .dw 0xa6c0, 0xc938, 0xa6ff, 0xc938, 0x21, 0 + .dw 0xa740, 0xc938, 0xa77f, 0xc938, 0x21, 0 + .dw 0xa7c0, 0xc938, 0xa7ff, 0xc938, 0x21, 0 + .dw 0xa840, 0xc938, 0xa87f, 0xc938, 0x21, 0 + .dw 0xa8c0, 0xc938, 0xa8ff, 0xc938, 0x21, 0 + .dw 0xa940, 0xc938, 0xa97f, 0xc938, 0x21, 0 + .dw 0xa9c0, 0xc938, 0xa9ff, 0xc938, 0x21, 0 + .dw 0xaa40, 0xc938, 0xaa7f, 0xc938, 0x21, 0 + .dw 0xaac0, 0xc938, 0xaaff, 0xc938, 0x21, 0 + .dw 0xab40, 0xc938, 0xab7f, 0xc938, 0x21, 0 + .dw 0xabc0, 0xc938, 0xabff, 0xc938, 0x21, 0 + .dw 0xac40, 0xc938, 0xac7f, 0xc938, 0x21, 0 + .dw 0xacc0, 0xc938, 0xacff, 0xc938, 0x21, 0 + .dw 0xad40, 0xc938, 0xad7f, 0xc938, 0x21, 0 + .dw 0xadc0, 0xc938, 0xadff, 0xc938, 0x21, 0 + .dw 0xae40, 0xc938, 0xae7f, 0xc938, 0x21, 0 + .dw 0xaec0, 0xc938, 0xaeff, 0xc938, 0x21, 0 + .dw 0xaf40, 0xc938, 0xaf7f, 0xc938, 0x21, 0 + .dw 0xafc0, 0xc938, 0xafff, 0xc938, 0x21, 0 + .dw 0xb040, 0xc938, 0xb07f, 0xc938, 0x21, 0 + .dw 0xb0c0, 0xc938, 0xb0ff, 0xc938, 0x21, 0 + .dw 0xb140, 0xc938, 0xb17f, 0xc938, 0x21, 0 + .dw 0xb1c0, 0xc938, 0xb1ff, 0xc938, 0x21, 0 + .dw 0xb240, 0xc938, 0xb27f, 0xc938, 0x21, 0 + .dw 0xb2c0, 0xc938, 0xb2ff, 0xc938, 0x21, 0 + .dw 0xb340, 0xc938, 0xb37f, 0xc938, 0x21, 0 + .dw 0xb3c0, 0xc938, 0xb3ff, 0xc938, 0x21, 0 + .dw 0xb440, 0xc938, 0xb47f, 0xc938, 0x21, 0 + .dw 0xb4c0, 0xc938, 0xb4ff, 0xc938, 0x21, 0 + .dw 0xb540, 0xc938, 0xb57f, 0xc938, 0x21, 0 + .dw 0xb5c0, 0xc938, 0xb5ff, 0xc938, 0x21, 0 + .dw 0xb640, 0xc938, 0xb67f, 0xc938, 0x21, 0 + .dw 0xb6c0, 0xc938, 0xb6ff, 0xc938, 0x21, 0 + .dw 0xb740, 0xc938, 0xb77f, 0xc938, 0x21, 0 + .dw 0xb7c0, 0xc938, 0xb7ff, 0xc938, 0x21, 0 + .dw 0xb840, 0xc938, 0xb87f, 0xc938, 0x21, 0 + .dw 0xb8c0, 0xc938, 0xb8ff, 0xc938, 0x21, 0 + .dw 0xb940, 0xc938, 0xb97f, 0xc938, 0x21, 0 + .dw 0xb9c0, 0xc938, 0xdfff, 0xc938, 0x21, 0 + .dw 0xe040, 0xc938, 0xe07f, 0xc938, 0x21, 0 + .dw 0xe0c0, 0xc938, 0xe0ff, 0xc938, 0x21, 0 + .dw 0xe140, 0xc938, 0xe17f, 0xc938, 0x21, 0 + .dw 0xe1c0, 0xc938, 0xe1ff, 0xc938, 0x21, 0 + .dw 0xe240, 0xc938, 0xe27f, 0xc938, 0x21, 0 + .dw 0xe2c0, 0xc938, 0xe2ff, 0xc938, 0x21, 0 + .dw 0xe340, 0xc938, 0xe37f, 0xc938, 0x21, 0 + .dw 0xe3c0, 0xc938, 0xe3ff, 0xc938, 0x21, 0 + .dw 0xe440, 0xc938, 0xe47f, 0xc938, 0x21, 0 + .dw 0xe4c0, 0xc938, 0xe4ff, 0xc938, 0x21, 0 + .dw 0xe540, 0xc938, 0xe57f, 0xc938, 0x21, 0 + .dw 0xe5c0, 0xc938, 0xe5ff, 0xc938, 0x21, 0 + .dw 0xe640, 0xc938, 0xe67f, 0xc938, 0x21, 0 + .dw 0xe6c0, 0xc938, 0xe6ff, 0xc938, 0x21, 0 + .dw 0xe740, 0xc938, 0xe77f, 0xc938, 0x21, 0 + .dw 0xe7c0, 0xc938, 0xe7ff, 0xc938, 0x21, 0 + .dw 0xe840, 0xc938, 0xe87f, 0xc938, 0x21, 0 + .dw 0xe8c0, 0xc938, 0xe8ff, 0xc938, 0x21, 0 + .dw 0xe940, 0xc938, 0xe97f, 0xc938, 0x21, 0 + .dw 0xe9c0, 0xc938, 0xe9ff, 0xc938, 0x21, 0 + .dw 0xea40, 0xc938, 0xea7f, 0xc938, 0x21, 0 + .dw 0xeac0, 0xc938, 0xeaff, 0xc938, 0x21, 0 + .dw 0xeb40, 0xc938, 0xeb7f, 0xc938, 0x21, 0 + .dw 0xebc0, 0xc938, 0xebff, 0xc938, 0x21, 0 + .dw 0xec40, 0xc938, 0xec7f, 0xc938, 0x21, 0 + .dw 0xecc0, 0xc938, 0xecff, 0xc938, 0x21, 0 + .dw 0xed40, 0xc938, 0xed7f, 0xc938, 0x21, 0 + .dw 0xedc0, 0xc938, 0xedff, 0xc938, 0x21, 0 + .dw 0xee40, 0xc938, 0xee7f, 0xc938, 0x21, 0 + .dw 0xeec0, 0xc938, 0xeeff, 0xc938, 0x21, 0 + .dw 0xef40, 0xc938, 0xef7f, 0xc938, 0x21, 0 + .dw 0xefc0, 0xc938, 0xefff, 0xc938, 0x21, 0 + .dw 0xf040, 0xc938, 0xf07f, 0xc938, 0x21, 0 + .dw 0xf0c0, 0xc938, 0xf0ff, 0xc938, 0x21, 0 + .dw 0xf140, 0xc938, 0xf17f, 0xc938, 0x21, 0 + .dw 0xf1c0, 0xc938, 0xf1ff, 0xc938, 0x21, 0 + .dw 0xf240, 0xc938, 0xf27f, 0xc938, 0x21, 0 + .dw 0xf2c0, 0xc938, 0xf2ff, 0xc938, 0x21, 0 + .dw 0xf340, 0xc938, 0xf37f, 0xc938, 0x21, 0 + .dw 0xf3c0, 0xc938, 0xf3ff, 0xc938, 0x21, 0 + .dw 0xf440, 0xc938, 0xf47f, 0xc938, 0x21, 0 + .dw 0xf4c0, 0xc938, 0xf4ff, 0xc938, 0x21, 0 + .dw 0xf540, 0xc938, 0xf57f, 0xc938, 0x21, 0 + .dw 0xf5c0, 0xc938, 0xf5ff, 0xc938, 0x21, 0 + .dw 0xf640, 0xc938, 0xf67f, 0xc938, 0x21, 0 + .dw 0xf6c0, 0xc938, 0xf6ff, 0xc938, 0x21, 0 + .dw 0xf740, 0xc938, 0xf77f, 0xc938, 0x21, 0 + .dw 0xf7c0, 0xc938, 0xf7ff, 0xc938, 0x21, 0 + .dw 0xf840, 0xc938, 0xf87f, 0xc938, 0x21, 0 + .dw 0xf8c0, 0xc938, 0xf8ff, 0xc938, 0x21, 0 + .dw 0xf940, 0xc938, 0xf97f, 0xc938, 0x21, 0 + .dw 0xf9c0, 0xc938, 0x1fff, 0xc939, 0x21, 0 + .dw 0x2040, 0xc939, 0x207f, 0xc939, 0x21, 0 + .dw 0x20c0, 0xc939, 0x20ff, 0xc939, 0x21, 0 + .dw 0x2140, 0xc939, 0x217f, 0xc939, 0x21, 0 + .dw 0x21c0, 0xc939, 0x21ff, 0xc939, 0x21, 0 + .dw 0x2240, 0xc939, 0x227f, 0xc939, 0x21, 0 + .dw 0x22c0, 0xc939, 0x22ff, 0xc939, 0x21, 0 + .dw 0x2340, 0xc939, 0x237f, 0xc939, 0x21, 0 + .dw 0x23c0, 0xc939, 0x23ff, 0xc939, 0x21, 0 + .dw 0x2440, 0xc939, 0x247f, 0xc939, 0x21, 0 + .dw 0x24c0, 0xc939, 0x24ff, 0xc939, 0x21, 0 + .dw 0x2540, 0xc939, 0x257f, 0xc939, 0x21, 0 + .dw 0x25c0, 0xc939, 0x25ff, 0xc939, 0x21, 0 + .dw 0x2640, 0xc939, 0x267f, 0xc939, 0x21, 0 + .dw 0x26c0, 0xc939, 0x26ff, 0xc939, 0x21, 0 + .dw 0x2740, 0xc939, 0x277f, 0xc939, 0x21, 0 + .dw 0x27c0, 0xc939, 0x27ff, 0xc939, 0x21, 0 + .dw 0x2840, 0xc939, 0x287f, 0xc939, 0x21, 0 + .dw 0x28c0, 0xc939, 0x28ff, 0xc939, 0x21, 0 + .dw 0x2940, 0xc939, 0x297f, 0xc939, 0x21, 0 + .dw 0x29c0, 0xc939, 0x29ff, 0xc939, 0x21, 0 + .dw 0x2a40, 0xc939, 0x2a7f, 0xc939, 0x21, 0 + .dw 0x2ac0, 0xc939, 0x2aff, 0xc939, 0x21, 0 + .dw 0x2b40, 0xc939, 0x2b7f, 0xc939, 0x21, 0 + .dw 0x2bc0, 0xc939, 0x2bff, 0xc939, 0x21, 0 + .dw 0x2c40, 0xc939, 0x2c7f, 0xc939, 0x21, 0 + .dw 0x2cc0, 0xc939, 0x2cff, 0xc939, 0x21, 0 + .dw 0x2d40, 0xc939, 0x2d7f, 0xc939, 0x21, 0 + .dw 0x2dc0, 0xc939, 0x2dff, 0xc939, 0x21, 0 + .dw 0x2e40, 0xc939, 0x2e7f, 0xc939, 0x21, 0 + .dw 0x2ec0, 0xc939, 0x2eff, 0xc939, 0x21, 0 + .dw 0x2f40, 0xc939, 0x2f7f, 0xc939, 0x21, 0 + .dw 0x2fc0, 0xc939, 0x2fff, 0xc939, 0x21, 0 + .dw 0x3040, 0xc939, 0x307f, 0xc939, 0x21, 0 + .dw 0x30c0, 0xc939, 0x30ff, 0xc939, 0x21, 0 + .dw 0x3140, 0xc939, 0x317f, 0xc939, 0x21, 0 + .dw 0x31c0, 0xc939, 0x31ff, 0xc939, 0x21, 0 + .dw 0x3240, 0xc939, 0x327f, 0xc939, 0x21, 0 + .dw 0x32c0, 0xc939, 0x32ff, 0xc939, 0x21, 0 + .dw 0x3340, 0xc939, 0x337f, 0xc939, 0x21, 0 + .dw 0x33c0, 0xc939, 0x33ff, 0xc939, 0x21, 0 + .dw 0x3440, 0xc939, 0x347f, 0xc939, 0x21, 0 + .dw 0x34c0, 0xc939, 0x34ff, 0xc939, 0x21, 0 + .dw 0x3540, 0xc939, 0x357f, 0xc939, 0x21, 0 + .dw 0x35c0, 0xc939, 0x35ff, 0xc939, 0x21, 0 + .dw 0x3640, 0xc939, 0x367f, 0xc939, 0x21, 0 + .dw 0x36c0, 0xc939, 0x36ff, 0xc939, 0x21, 0 + .dw 0x3740, 0xc939, 0x377f, 0xc939, 0x21, 0 + .dw 0x37c0, 0xc939, 0x37ff, 0xc939, 0x21, 0 + .dw 0x3840, 0xc939, 0x387f, 0xc939, 0x21, 0 + .dw 0x38c0, 0xc939, 0x38ff, 0xc939, 0x21, 0 + .dw 0x3940, 0xc939, 0x397f, 0xc939, 0x21, 0 + .dw 0x39c0, 0xc939, 0x5fff, 0xc939, 0x21, 0 + .dw 0x6040, 0xc939, 0x607f, 0xc939, 0x21, 0 + .dw 0x60c0, 0xc939, 0x60ff, 0xc939, 0x21, 0 + .dw 0x6140, 0xc939, 0x617f, 0xc939, 0x21, 0 + .dw 0x61c0, 0xc939, 0x61ff, 0xc939, 0x21, 0 + .dw 0x6240, 0xc939, 0x627f, 0xc939, 0x21, 0 + .dw 0x62c0, 0xc939, 0x62ff, 0xc939, 0x21, 0 + .dw 0x6340, 0xc939, 0x637f, 0xc939, 0x21, 0 + .dw 0x63c0, 0xc939, 0x63ff, 0xc939, 0x21, 0 + .dw 0x6440, 0xc939, 0x647f, 0xc939, 0x21, 0 + .dw 0x64c0, 0xc939, 0x64ff, 0xc939, 0x21, 0 + .dw 0x6540, 0xc939, 0x657f, 0xc939, 0x21, 0 + .dw 0x65c0, 0xc939, 0x65ff, 0xc939, 0x21, 0 + .dw 0x6640, 0xc939, 0x667f, 0xc939, 0x21, 0 + .dw 0x66c0, 0xc939, 0x66ff, 0xc939, 0x21, 0 + .dw 0x6740, 0xc939, 0x677f, 0xc939, 0x21, 0 + .dw 0x67c0, 0xc939, 0x67ff, 0xc939, 0x21, 0 + .dw 0x6840, 0xc939, 0x687f, 0xc939, 0x21, 0 + .dw 0x68c0, 0xc939, 0x68ff, 0xc939, 0x21, 0 + .dw 0x6940, 0xc939, 0x697f, 0xc939, 0x21, 0 + .dw 0x69c0, 0xc939, 0x69ff, 0xc939, 0x21, 0 + .dw 0x6a40, 0xc939, 0x6a7f, 0xc939, 0x21, 0 + .dw 0x6ac0, 0xc939, 0x6aff, 0xc939, 0x21, 0 + .dw 0x6b40, 0xc939, 0x6b7f, 0xc939, 0x21, 0 + .dw 0x6bc0, 0xc939, 0x6bff, 0xc939, 0x21, 0 + .dw 0x6c40, 0xc939, 0x6c7f, 0xc939, 0x21, 0 + .dw 0x6cc0, 0xc939, 0x6cff, 0xc939, 0x21, 0 + .dw 0x6d40, 0xc939, 0x6d7f, 0xc939, 0x21, 0 + .dw 0x6dc0, 0xc939, 0x6dff, 0xc939, 0x21, 0 + .dw 0x6e40, 0xc939, 0x6e7f, 0xc939, 0x21, 0 + .dw 0x6ec0, 0xc939, 0x6eff, 0xc939, 0x21, 0 + .dw 0x6f40, 0xc939, 0x6f7f, 0xc939, 0x21, 0 + .dw 0x6fc0, 0xc939, 0x6fff, 0xc939, 0x21, 0 + .dw 0x7040, 0xc939, 0x707f, 0xc939, 0x21, 0 + .dw 0x70c0, 0xc939, 0x70ff, 0xc939, 0x21, 0 + .dw 0x7140, 0xc939, 0x717f, 0xc939, 0x21, 0 + .dw 0x71c0, 0xc939, 0x71ff, 0xc939, 0x21, 0 + .dw 0x7240, 0xc939, 0x727f, 0xc939, 0x21, 0 + .dw 0x72c0, 0xc939, 0x72ff, 0xc939, 0x21, 0 + .dw 0x7340, 0xc939, 0x737f, 0xc939, 0x21, 0 + .dw 0x73c0, 0xc939, 0x73ff, 0xc939, 0x21, 0 + .dw 0x7440, 0xc939, 0x747f, 0xc939, 0x21, 0 + .dw 0x74c0, 0xc939, 0x74ff, 0xc939, 0x21, 0 + .dw 0x7540, 0xc939, 0x757f, 0xc939, 0x21, 0 + .dw 0x75c0, 0xc939, 0x75ff, 0xc939, 0x21, 0 + .dw 0x7640, 0xc939, 0x767f, 0xc939, 0x21, 0 + .dw 0x76c0, 0xc939, 0x76ff, 0xc939, 0x21, 0 + .dw 0x7740, 0xc939, 0x777f, 0xc939, 0x21, 0 + .dw 0x77c0, 0xc939, 0x77ff, 0xc939, 0x21, 0 + .dw 0x7840, 0xc939, 0x787f, 0xc939, 0x21, 0 + .dw 0x78c0, 0xc939, 0x78ff, 0xc939, 0x21, 0 + .dw 0x7940, 0xc939, 0x797f, 0xc939, 0x21, 0 + .dw 0x79c0, 0xc939, 0x9fff, 0xc939, 0x21, 0 + .dw 0xa040, 0xc939, 0xa07f, 0xc939, 0x21, 0 + .dw 0xa0c0, 0xc939, 0xa0ff, 0xc939, 0x21, 0 + .dw 0xa140, 0xc939, 0xa17f, 0xc939, 0x21, 0 + .dw 0xa1c0, 0xc939, 0xa1ff, 0xc939, 0x21, 0 + .dw 0xa240, 0xc939, 0xa27f, 0xc939, 0x21, 0 + .dw 0xa2c0, 0xc939, 0xa2ff, 0xc939, 0x21, 0 + .dw 0xa340, 0xc939, 0xa37f, 0xc939, 0x21, 0 + .dw 0xa3c0, 0xc939, 0xa3ff, 0xc939, 0x21, 0 + .dw 0xa440, 0xc939, 0xa47f, 0xc939, 0x21, 0 + .dw 0xa4c0, 0xc939, 0xa4ff, 0xc939, 0x21, 0 + .dw 0xa540, 0xc939, 0xa57f, 0xc939, 0x21, 0 + .dw 0xa5c0, 0xc939, 0xa5ff, 0xc939, 0x21, 0 + .dw 0xa640, 0xc939, 0xa67f, 0xc939, 0x21, 0 + .dw 0xa6c0, 0xc939, 0xa6ff, 0xc939, 0x21, 0 + .dw 0xa740, 0xc939, 0xa77f, 0xc939, 0x21, 0 + .dw 0xa7c0, 0xc939, 0xa7ff, 0xc939, 0x21, 0 + .dw 0xa840, 0xc939, 0xa87f, 0xc939, 0x21, 0 + .dw 0xa8c0, 0xc939, 0xa8ff, 0xc939, 0x21, 0 + .dw 0xa940, 0xc939, 0xa97f, 0xc939, 0x21, 0 + .dw 0xa9c0, 0xc939, 0xa9ff, 0xc939, 0x21, 0 + .dw 0xaa40, 0xc939, 0xaa7f, 0xc939, 0x21, 0 + .dw 0xaac0, 0xc939, 0xaaff, 0xc939, 0x21, 0 + .dw 0xab40, 0xc939, 0xab7f, 0xc939, 0x21, 0 + .dw 0xabc0, 0xc939, 0xabff, 0xc939, 0x21, 0 + .dw 0xac40, 0xc939, 0xac7f, 0xc939, 0x21, 0 + .dw 0xacc0, 0xc939, 0xacff, 0xc939, 0x21, 0 + .dw 0xad40, 0xc939, 0xad7f, 0xc939, 0x21, 0 + .dw 0xadc0, 0xc939, 0xadff, 0xc939, 0x21, 0 + .dw 0xae40, 0xc939, 0xae7f, 0xc939, 0x21, 0 + .dw 0xaec0, 0xc939, 0xaeff, 0xc939, 0x21, 0 + .dw 0xaf40, 0xc939, 0xaf7f, 0xc939, 0x21, 0 + .dw 0xafc0, 0xc939, 0xafff, 0xc939, 0x21, 0 + .dw 0xb040, 0xc939, 0xb07f, 0xc939, 0x21, 0 + .dw 0xb0c0, 0xc939, 0xb0ff, 0xc939, 0x21, 0 + .dw 0xb140, 0xc939, 0xb17f, 0xc939, 0x21, 0 + .dw 0xb1c0, 0xc939, 0xb1ff, 0xc939, 0x21, 0 + .dw 0xb240, 0xc939, 0xb27f, 0xc939, 0x21, 0 + .dw 0xb2c0, 0xc939, 0xb2ff, 0xc939, 0x21, 0 + .dw 0xb340, 0xc939, 0xb37f, 0xc939, 0x21, 0 + .dw 0xb3c0, 0xc939, 0xb3ff, 0xc939, 0x21, 0 + .dw 0xb440, 0xc939, 0xb47f, 0xc939, 0x21, 0 + .dw 0xb4c0, 0xc939, 0xb4ff, 0xc939, 0x21, 0 + .dw 0xb540, 0xc939, 0xb57f, 0xc939, 0x21, 0 + .dw 0xb5c0, 0xc939, 0xb5ff, 0xc939, 0x21, 0 + .dw 0xb640, 0xc939, 0xb67f, 0xc939, 0x21, 0 + .dw 0xb6c0, 0xc939, 0xb6ff, 0xc939, 0x21, 0 + .dw 0xb740, 0xc939, 0xb77f, 0xc939, 0x21, 0 + .dw 0xb7c0, 0xc939, 0xb7ff, 0xc939, 0x21, 0 + .dw 0xb840, 0xc939, 0xb87f, 0xc939, 0x21, 0 + .dw 0xb8c0, 0xc939, 0xb8ff, 0xc939, 0x21, 0 + .dw 0xb940, 0xc939, 0xb97f, 0xc939, 0x21, 0 + .dw 0xb9c0, 0xc939, 0xdfff, 0xc939, 0x21, 0 + .dw 0xe040, 0xc939, 0xe07f, 0xc939, 0x21, 0 + .dw 0xe0c0, 0xc939, 0xe0ff, 0xc939, 0x21, 0 + .dw 0xe140, 0xc939, 0xe17f, 0xc939, 0x21, 0 + .dw 0xe1c0, 0xc939, 0xe1ff, 0xc939, 0x21, 0 + .dw 0xe240, 0xc939, 0xe27f, 0xc939, 0x21, 0 + .dw 0xe2c0, 0xc939, 0xe2ff, 0xc939, 0x21, 0 + .dw 0xe340, 0xc939, 0xe37f, 0xc939, 0x21, 0 + .dw 0xe3c0, 0xc939, 0xe3ff, 0xc939, 0x21, 0 + .dw 0xe440, 0xc939, 0xe47f, 0xc939, 0x21, 0 + .dw 0xe4c0, 0xc939, 0xe4ff, 0xc939, 0x21, 0 + .dw 0xe540, 0xc939, 0xe57f, 0xc939, 0x21, 0 + .dw 0xe5c0, 0xc939, 0xe5ff, 0xc939, 0x21, 0 + .dw 0xe640, 0xc939, 0xe67f, 0xc939, 0x21, 0 + .dw 0xe6c0, 0xc939, 0xe6ff, 0xc939, 0x21, 0 + .dw 0xe740, 0xc939, 0xe77f, 0xc939, 0x21, 0 + .dw 0xe7c0, 0xc939, 0xe7ff, 0xc939, 0x21, 0 + .dw 0xe840, 0xc939, 0xe87f, 0xc939, 0x21, 0 + .dw 0xe8c0, 0xc939, 0xe8ff, 0xc939, 0x21, 0 + .dw 0xe940, 0xc939, 0xe97f, 0xc939, 0x21, 0 + .dw 0xe9c0, 0xc939, 0xe9ff, 0xc939, 0x21, 0 + .dw 0xea40, 0xc939, 0xea7f, 0xc939, 0x21, 0 + .dw 0xeac0, 0xc939, 0xeaff, 0xc939, 0x21, 0 + .dw 0xeb40, 0xc939, 0xeb7f, 0xc939, 0x21, 0 + .dw 0xebc0, 0xc939, 0xebff, 0xc939, 0x21, 0 + .dw 0xec40, 0xc939, 0xec7f, 0xc939, 0x21, 0 + .dw 0xecc0, 0xc939, 0xecff, 0xc939, 0x21, 0 + .dw 0xed40, 0xc939, 0xed7f, 0xc939, 0x21, 0 + .dw 0xedc0, 0xc939, 0xedff, 0xc939, 0x21, 0 + .dw 0xee40, 0xc939, 0xee7f, 0xc939, 0x21, 0 + .dw 0xeec0, 0xc939, 0xeeff, 0xc939, 0x21, 0 + .dw 0xef40, 0xc939, 0xef7f, 0xc939, 0x21, 0 + .dw 0xefc0, 0xc939, 0xefff, 0xc939, 0x21, 0 + .dw 0xf040, 0xc939, 0xf07f, 0xc939, 0x21, 0 + .dw 0xf0c0, 0xc939, 0xf0ff, 0xc939, 0x21, 0 + .dw 0xf140, 0xc939, 0xf17f, 0xc939, 0x21, 0 + .dw 0xf1c0, 0xc939, 0xf1ff, 0xc939, 0x21, 0 + .dw 0xf240, 0xc939, 0xf27f, 0xc939, 0x21, 0 + .dw 0xf2c0, 0xc939, 0xf2ff, 0xc939, 0x21, 0 + .dw 0xf340, 0xc939, 0xf37f, 0xc939, 0x21, 0 + .dw 0xf3c0, 0xc939, 0xf3ff, 0xc939, 0x21, 0 + .dw 0xf440, 0xc939, 0xf47f, 0xc939, 0x21, 0 + .dw 0xf4c0, 0xc939, 0xf4ff, 0xc939, 0x21, 0 + .dw 0xf540, 0xc939, 0xf57f, 0xc939, 0x21, 0 + .dw 0xf5c0, 0xc939, 0xf5ff, 0xc939, 0x21, 0 + .dw 0xf640, 0xc939, 0xf67f, 0xc939, 0x21, 0 + .dw 0xf6c0, 0xc939, 0xf6ff, 0xc939, 0x21, 0 + .dw 0xf740, 0xc939, 0xf77f, 0xc939, 0x21, 0 + .dw 0xf7c0, 0xc939, 0xf7ff, 0xc939, 0x21, 0 + .dw 0xf840, 0xc939, 0xf87f, 0xc939, 0x21, 0 + .dw 0xf8c0, 0xc939, 0xf8ff, 0xc939, 0x21, 0 + .dw 0xf940, 0xc939, 0xf97f, 0xc939, 0x21, 0 + .dw 0xf9c0, 0xc939, 0x1fff, 0xc93a, 0x21, 0 + .dw 0x2040, 0xc93a, 0x207f, 0xc93a, 0x21, 0 + .dw 0x20c0, 0xc93a, 0x20ff, 0xc93a, 0x21, 0 + .dw 0x2140, 0xc93a, 0x217f, 0xc93a, 0x21, 0 + .dw 0x21c0, 0xc93a, 0x21ff, 0xc93a, 0x21, 0 + .dw 0x2240, 0xc93a, 0x227f, 0xc93a, 0x21, 0 + .dw 0x22c0, 0xc93a, 0x22ff, 0xc93a, 0x21, 0 + .dw 0x2340, 0xc93a, 0x237f, 0xc93a, 0x21, 0 + .dw 0x23c0, 0xc93a, 0x23ff, 0xc93a, 0x21, 0 + .dw 0x2440, 0xc93a, 0x247f, 0xc93a, 0x21, 0 + .dw 0x24c0, 0xc93a, 0x24ff, 0xc93a, 0x21, 0 + .dw 0x2540, 0xc93a, 0x257f, 0xc93a, 0x21, 0 + .dw 0x25c0, 0xc93a, 0x25ff, 0xc93a, 0x21, 0 + .dw 0x2640, 0xc93a, 0x267f, 0xc93a, 0x21, 0 + .dw 0x26c0, 0xc93a, 0x26ff, 0xc93a, 0x21, 0 + .dw 0x2740, 0xc93a, 0x277f, 0xc93a, 0x21, 0 + .dw 0x27c0, 0xc93a, 0x27ff, 0xc93a, 0x21, 0 + .dw 0x2840, 0xc93a, 0x287f, 0xc93a, 0x21, 0 + .dw 0x28c0, 0xc93a, 0x28ff, 0xc93a, 0x21, 0 + .dw 0x2940, 0xc93a, 0x297f, 0xc93a, 0x21, 0 + .dw 0x29c0, 0xc93a, 0x29ff, 0xc93a, 0x21, 0 + .dw 0x2a40, 0xc93a, 0x2a7f, 0xc93a, 0x21, 0 + .dw 0x2ac0, 0xc93a, 0x2aff, 0xc93a, 0x21, 0 + .dw 0x2b40, 0xc93a, 0x2b7f, 0xc93a, 0x21, 0 + .dw 0x2bc0, 0xc93a, 0x2bff, 0xc93a, 0x21, 0 + .dw 0x2c40, 0xc93a, 0x2c7f, 0xc93a, 0x21, 0 + .dw 0x2cc0, 0xc93a, 0x2cff, 0xc93a, 0x21, 0 + .dw 0x2d40, 0xc93a, 0x2d7f, 0xc93a, 0x21, 0 + .dw 0x2dc0, 0xc93a, 0x2dff, 0xc93a, 0x21, 0 + .dw 0x2e40, 0xc93a, 0x2e7f, 0xc93a, 0x21, 0 + .dw 0x2ec0, 0xc93a, 0x2eff, 0xc93a, 0x21, 0 + .dw 0x2f40, 0xc93a, 0x2f7f, 0xc93a, 0x21, 0 + .dw 0x2fc0, 0xc93a, 0x2fff, 0xc93a, 0x21, 0 + .dw 0x3040, 0xc93a, 0x307f, 0xc93a, 0x21, 0 + .dw 0x30c0, 0xc93a, 0x30ff, 0xc93a, 0x21, 0 + .dw 0x3140, 0xc93a, 0x317f, 0xc93a, 0x21, 0 + .dw 0x31c0, 0xc93a, 0x31ff, 0xc93a, 0x21, 0 + .dw 0x3240, 0xc93a, 0x327f, 0xc93a, 0x21, 0 + .dw 0x32c0, 0xc93a, 0x32ff, 0xc93a, 0x21, 0 + .dw 0x3340, 0xc93a, 0x337f, 0xc93a, 0x21, 0 + .dw 0x33c0, 0xc93a, 0x33ff, 0xc93a, 0x21, 0 + .dw 0x3440, 0xc93a, 0x347f, 0xc93a, 0x21, 0 + .dw 0x34c0, 0xc93a, 0x34ff, 0xc93a, 0x21, 0 + .dw 0x3540, 0xc93a, 0x357f, 0xc93a, 0x21, 0 + .dw 0x35c0, 0xc93a, 0x35ff, 0xc93a, 0x21, 0 + .dw 0x3640, 0xc93a, 0x367f, 0xc93a, 0x21, 0 + .dw 0x36c0, 0xc93a, 0x36ff, 0xc93a, 0x21, 0 + .dw 0x3740, 0xc93a, 0x377f, 0xc93a, 0x21, 0 + .dw 0x37c0, 0xc93a, 0x37ff, 0xc93a, 0x21, 0 + .dw 0x3840, 0xc93a, 0x387f, 0xc93a, 0x21, 0 + .dw 0x38c0, 0xc93a, 0x38ff, 0xc93a, 0x21, 0 + .dw 0x3940, 0xc93a, 0x397f, 0xc93a, 0x21, 0 + .dw 0x39c0, 0xc93a, 0x5fff, 0xc93a, 0x21, 0 + .dw 0x6040, 0xc93a, 0x607f, 0xc93a, 0x21, 0 + .dw 0x60c0, 0xc93a, 0x60ff, 0xc93a, 0x21, 0 + .dw 0x6140, 0xc93a, 0x617f, 0xc93a, 0x21, 0 + .dw 0x61c0, 0xc93a, 0x61ff, 0xc93a, 0x21, 0 + .dw 0x6240, 0xc93a, 0x627f, 0xc93a, 0x21, 0 + .dw 0x62c0, 0xc93a, 0x62ff, 0xc93a, 0x21, 0 + .dw 0x6340, 0xc93a, 0x637f, 0xc93a, 0x21, 0 + .dw 0x63c0, 0xc93a, 0x63ff, 0xc93a, 0x21, 0 + .dw 0x6440, 0xc93a, 0x647f, 0xc93a, 0x21, 0 + .dw 0x64c0, 0xc93a, 0x64ff, 0xc93a, 0x21, 0 + .dw 0x6540, 0xc93a, 0x657f, 0xc93a, 0x21, 0 + .dw 0x65c0, 0xc93a, 0x65ff, 0xc93a, 0x21, 0 + .dw 0x6640, 0xc93a, 0x667f, 0xc93a, 0x21, 0 + .dw 0x66c0, 0xc93a, 0x66ff, 0xc93a, 0x21, 0 + .dw 0x6740, 0xc93a, 0x677f, 0xc93a, 0x21, 0 + .dw 0x67c0, 0xc93a, 0x67ff, 0xc93a, 0x21, 0 + .dw 0x6840, 0xc93a, 0x687f, 0xc93a, 0x21, 0 + .dw 0x68c0, 0xc93a, 0x68ff, 0xc93a, 0x21, 0 + .dw 0x6940, 0xc93a, 0x697f, 0xc93a, 0x21, 0 + .dw 0x69c0, 0xc93a, 0x69ff, 0xc93a, 0x21, 0 + .dw 0x6a40, 0xc93a, 0x6a7f, 0xc93a, 0x21, 0 + .dw 0x6ac0, 0xc93a, 0x6aff, 0xc93a, 0x21, 0 + .dw 0x6b40, 0xc93a, 0x6b7f, 0xc93a, 0x21, 0 + .dw 0x6bc0, 0xc93a, 0x6bff, 0xc93a, 0x21, 0 + .dw 0x6c40, 0xc93a, 0x6c7f, 0xc93a, 0x21, 0 + .dw 0x6cc0, 0xc93a, 0x6cff, 0xc93a, 0x21, 0 + .dw 0x6d40, 0xc93a, 0x6d7f, 0xc93a, 0x21, 0 + .dw 0x6dc0, 0xc93a, 0x6dff, 0xc93a, 0x21, 0 + .dw 0x6e40, 0xc93a, 0x6e7f, 0xc93a, 0x21, 0 + .dw 0x6ec0, 0xc93a, 0x6eff, 0xc93a, 0x21, 0 + .dw 0x6f40, 0xc93a, 0x6f7f, 0xc93a, 0x21, 0 + .dw 0x6fc0, 0xc93a, 0x6fff, 0xc93a, 0x21, 0 + .dw 0x7040, 0xc93a, 0x707f, 0xc93a, 0x21, 0 + .dw 0x70c0, 0xc93a, 0x70ff, 0xc93a, 0x21, 0 + .dw 0x7140, 0xc93a, 0x717f, 0xc93a, 0x21, 0 + .dw 0x71c0, 0xc93a, 0x71ff, 0xc93a, 0x21, 0 + .dw 0x7240, 0xc93a, 0x727f, 0xc93a, 0x21, 0 + .dw 0x72c0, 0xc93a, 0x72ff, 0xc93a, 0x21, 0 + .dw 0x7340, 0xc93a, 0x737f, 0xc93a, 0x21, 0 + .dw 0x73c0, 0xc93a, 0x73ff, 0xc93a, 0x21, 0 + .dw 0x7440, 0xc93a, 0x747f, 0xc93a, 0x21, 0 + .dw 0x74c0, 0xc93a, 0x74ff, 0xc93a, 0x21, 0 + .dw 0x7540, 0xc93a, 0x757f, 0xc93a, 0x21, 0 + .dw 0x75c0, 0xc93a, 0x75ff, 0xc93a, 0x21, 0 + .dw 0x7640, 0xc93a, 0x767f, 0xc93a, 0x21, 0 + .dw 0x76c0, 0xc93a, 0x76ff, 0xc93a, 0x21, 0 + .dw 0x7740, 0xc93a, 0x777f, 0xc93a, 0x21, 0 + .dw 0x77c0, 0xc93a, 0x77ff, 0xc93a, 0x21, 0 + .dw 0x7840, 0xc93a, 0x787f, 0xc93a, 0x21, 0 + .dw 0x78c0, 0xc93a, 0x78ff, 0xc93a, 0x21, 0 + .dw 0x7940, 0xc93a, 0x797f, 0xc93a, 0x21, 0 + .dw 0x79c0, 0xc93a, 0x9fff, 0xc93a, 0x21, 0 + .dw 0xa040, 0xc93a, 0xa07f, 0xc93a, 0x21, 0 + .dw 0xa0c0, 0xc93a, 0xa0ff, 0xc93a, 0x21, 0 + .dw 0xa140, 0xc93a, 0xa17f, 0xc93a, 0x21, 0 + .dw 0xa1c0, 0xc93a, 0xa1ff, 0xc93a, 0x21, 0 + .dw 0xa240, 0xc93a, 0xa27f, 0xc93a, 0x21, 0 + .dw 0xa2c0, 0xc93a, 0xa2ff, 0xc93a, 0x21, 0 + .dw 0xa340, 0xc93a, 0xa37f, 0xc93a, 0x21, 0 + .dw 0xa3c0, 0xc93a, 0xa3ff, 0xc93a, 0x21, 0 + .dw 0xa440, 0xc93a, 0xa47f, 0xc93a, 0x21, 0 + .dw 0xa4c0, 0xc93a, 0xa4ff, 0xc93a, 0x21, 0 + .dw 0xa540, 0xc93a, 0xa57f, 0xc93a, 0x21, 0 + .dw 0xa5c0, 0xc93a, 0xa5ff, 0xc93a, 0x21, 0 + .dw 0xa640, 0xc93a, 0xa67f, 0xc93a, 0x21, 0 + .dw 0xa6c0, 0xc93a, 0xa6ff, 0xc93a, 0x21, 0 + .dw 0xa740, 0xc93a, 0xa77f, 0xc93a, 0x21, 0 + .dw 0xa7c0, 0xc93a, 0xa7ff, 0xc93a, 0x21, 0 + .dw 0xa840, 0xc93a, 0xa87f, 0xc93a, 0x21, 0 + .dw 0xa8c0, 0xc93a, 0xa8ff, 0xc93a, 0x21, 0 + .dw 0xa940, 0xc93a, 0xa97f, 0xc93a, 0x21, 0 + .dw 0xa9c0, 0xc93a, 0xa9ff, 0xc93a, 0x21, 0 + .dw 0xaa40, 0xc93a, 0xaa7f, 0xc93a, 0x21, 0 + .dw 0xaac0, 0xc93a, 0xaaff, 0xc93a, 0x21, 0 + .dw 0xab40, 0xc93a, 0xab7f, 0xc93a, 0x21, 0 + .dw 0xabc0, 0xc93a, 0xabff, 0xc93a, 0x21, 0 + .dw 0xac40, 0xc93a, 0xac7f, 0xc93a, 0x21, 0 + .dw 0xacc0, 0xc93a, 0xacff, 0xc93a, 0x21, 0 + .dw 0xad40, 0xc93a, 0xad7f, 0xc93a, 0x21, 0 + .dw 0xadc0, 0xc93a, 0xadff, 0xc93a, 0x21, 0 + .dw 0xae40, 0xc93a, 0xae7f, 0xc93a, 0x21, 0 + .dw 0xaec0, 0xc93a, 0xaeff, 0xc93a, 0x21, 0 + .dw 0xaf40, 0xc93a, 0xaf7f, 0xc93a, 0x21, 0 + .dw 0xafc0, 0xc93a, 0xafff, 0xc93a, 0x21, 0 + .dw 0xb040, 0xc93a, 0xb07f, 0xc93a, 0x21, 0 + .dw 0xb0c0, 0xc93a, 0xb0ff, 0xc93a, 0x21, 0 + .dw 0xb140, 0xc93a, 0xb17f, 0xc93a, 0x21, 0 + .dw 0xb1c0, 0xc93a, 0xb1ff, 0xc93a, 0x21, 0 + .dw 0xb240, 0xc93a, 0xb27f, 0xc93a, 0x21, 0 + .dw 0xb2c0, 0xc93a, 0xb2ff, 0xc93a, 0x21, 0 + .dw 0xb340, 0xc93a, 0xb37f, 0xc93a, 0x21, 0 + .dw 0xb3c0, 0xc93a, 0xb3ff, 0xc93a, 0x21, 0 + .dw 0xb440, 0xc93a, 0xb47f, 0xc93a, 0x21, 0 + .dw 0xb4c0, 0xc93a, 0xb4ff, 0xc93a, 0x21, 0 + .dw 0xb540, 0xc93a, 0xb57f, 0xc93a, 0x21, 0 + .dw 0xb5c0, 0xc93a, 0xb5ff, 0xc93a, 0x21, 0 + .dw 0xb640, 0xc93a, 0xb67f, 0xc93a, 0x21, 0 + .dw 0xb6c0, 0xc93a, 0xb6ff, 0xc93a, 0x21, 0 + .dw 0xb740, 0xc93a, 0xb77f, 0xc93a, 0x21, 0 + .dw 0xb7c0, 0xc93a, 0xb7ff, 0xc93a, 0x21, 0 + .dw 0xb840, 0xc93a, 0xb87f, 0xc93a, 0x21, 0 + .dw 0xb8c0, 0xc93a, 0xb8ff, 0xc93a, 0x21, 0 + .dw 0xb940, 0xc93a, 0xb97f, 0xc93a, 0x21, 0 + .dw 0xb9c0, 0xc93a, 0xdfff, 0xc93a, 0x21, 0 + .dw 0xe040, 0xc93a, 0xe07f, 0xc93a, 0x21, 0 + .dw 0xe0c0, 0xc93a, 0xe0ff, 0xc93a, 0x21, 0 + .dw 0xe140, 0xc93a, 0xe17f, 0xc93a, 0x21, 0 + .dw 0xe1c0, 0xc93a, 0xe1ff, 0xc93a, 0x21, 0 + .dw 0xe240, 0xc93a, 0xe27f, 0xc93a, 0x21, 0 + .dw 0xe2c0, 0xc93a, 0xe2ff, 0xc93a, 0x21, 0 + .dw 0xe340, 0xc93a, 0xe37f, 0xc93a, 0x21, 0 + .dw 0xe3c0, 0xc93a, 0xe3ff, 0xc93a, 0x21, 0 + .dw 0xe440, 0xc93a, 0xe47f, 0xc93a, 0x21, 0 + .dw 0xe4c0, 0xc93a, 0xe4ff, 0xc93a, 0x21, 0 + .dw 0xe540, 0xc93a, 0xe57f, 0xc93a, 0x21, 0 + .dw 0xe5c0, 0xc93a, 0xe5ff, 0xc93a, 0x21, 0 + .dw 0xe640, 0xc93a, 0xe67f, 0xc93a, 0x21, 0 + .dw 0xe6c0, 0xc93a, 0xe6ff, 0xc93a, 0x21, 0 + .dw 0xe740, 0xc93a, 0xe77f, 0xc93a, 0x21, 0 + .dw 0xe7c0, 0xc93a, 0xe7ff, 0xc93a, 0x21, 0 + .dw 0xe840, 0xc93a, 0xe87f, 0xc93a, 0x21, 0 + .dw 0xe8c0, 0xc93a, 0xe8ff, 0xc93a, 0x21, 0 + .dw 0xe940, 0xc93a, 0xe97f, 0xc93a, 0x21, 0 + .dw 0xe9c0, 0xc93a, 0xe9ff, 0xc93a, 0x21, 0 + .dw 0xea40, 0xc93a, 0xea7f, 0xc93a, 0x21, 0 + .dw 0xeac0, 0xc93a, 0xeaff, 0xc93a, 0x21, 0 + .dw 0xeb40, 0xc93a, 0xeb7f, 0xc93a, 0x21, 0 + .dw 0xebc0, 0xc93a, 0xebff, 0xc93a, 0x21, 0 + .dw 0xec40, 0xc93a, 0xec7f, 0xc93a, 0x21, 0 + .dw 0xecc0, 0xc93a, 0xecff, 0xc93a, 0x21, 0 + .dw 0xed40, 0xc93a, 0xed7f, 0xc93a, 0x21, 0 + .dw 0xedc0, 0xc93a, 0xedff, 0xc93a, 0x21, 0 + .dw 0xee40, 0xc93a, 0xee7f, 0xc93a, 0x21, 0 + .dw 0xeec0, 0xc93a, 0xeeff, 0xc93a, 0x21, 0 + .dw 0xef40, 0xc93a, 0xef7f, 0xc93a, 0x21, 0 + .dw 0xefc0, 0xc93a, 0xefff, 0xc93a, 0x21, 0 + .dw 0xf040, 0xc93a, 0xf07f, 0xc93a, 0x21, 0 + .dw 0xf0c0, 0xc93a, 0xf0ff, 0xc93a, 0x21, 0 + .dw 0xf140, 0xc93a, 0xf17f, 0xc93a, 0x21, 0 + .dw 0xf1c0, 0xc93a, 0xf1ff, 0xc93a, 0x21, 0 + .dw 0xf240, 0xc93a, 0xf27f, 0xc93a, 0x21, 0 + .dw 0xf2c0, 0xc93a, 0xf2ff, 0xc93a, 0x21, 0 + .dw 0xf340, 0xc93a, 0xf37f, 0xc93a, 0x21, 0 + .dw 0xf3c0, 0xc93a, 0xf3ff, 0xc93a, 0x21, 0 + .dw 0xf440, 0xc93a, 0xf47f, 0xc93a, 0x21, 0 + .dw 0xf4c0, 0xc93a, 0xf4ff, 0xc93a, 0x21, 0 + .dw 0xf540, 0xc93a, 0xf57f, 0xc93a, 0x21, 0 + .dw 0xf5c0, 0xc93a, 0xf5ff, 0xc93a, 0x21, 0 + .dw 0xf640, 0xc93a, 0xf67f, 0xc93a, 0x21, 0 + .dw 0xf6c0, 0xc93a, 0xf6ff, 0xc93a, 0x21, 0 + .dw 0xf740, 0xc93a, 0xf77f, 0xc93a, 0x21, 0 + .dw 0xf7c0, 0xc93a, 0xf7ff, 0xc93a, 0x21, 0 + .dw 0xf840, 0xc93a, 0xf87f, 0xc93a, 0x21, 0 + .dw 0xf8c0, 0xc93a, 0xf8ff, 0xc93a, 0x21, 0 + .dw 0xf940, 0xc93a, 0xf97f, 0xc93a, 0x21, 0 + .dw 0xf9c0, 0xc93a, 0xffff, 0xc93b, 0x21, 0 + .dw 0x0040, 0xc93c, 0x007f, 0xc93c, 0x21, 0 + .dw 0x00c0, 0xc93c, 0x00ff, 0xc93c, 0x21, 0 + .dw 0x0140, 0xc93c, 0x017f, 0xc93c, 0x21, 0 + .dw 0x01c0, 0xc93c, 0x01ff, 0xc93c, 0x21, 0 + .dw 0x0240, 0xc93c, 0x027f, 0xc93c, 0x21, 0 + .dw 0x02c0, 0xc93c, 0x02ff, 0xc93c, 0x21, 0 + .dw 0x0340, 0xc93c, 0x037f, 0xc93c, 0x21, 0 + .dw 0x03c0, 0xc93c, 0x03ff, 0xc93c, 0x21, 0 + .dw 0x0440, 0xc93c, 0x047f, 0xc93c, 0x21, 0 + .dw 0x04c0, 0xc93c, 0x04ff, 0xc93c, 0x21, 0 + .dw 0x0540, 0xc93c, 0x057f, 0xc93c, 0x21, 0 + .dw 0x05c0, 0xc93c, 0x05ff, 0xc93c, 0x21, 0 + .dw 0x0640, 0xc93c, 0x067f, 0xc93c, 0x21, 0 + .dw 0x06c0, 0xc93c, 0x06ff, 0xc93c, 0x21, 0 + .dw 0x0740, 0xc93c, 0x077f, 0xc93c, 0x21, 0 + .dw 0x07c0, 0xc93c, 0x07ff, 0xc93c, 0x21, 0 + .dw 0x0840, 0xc93c, 0x087f, 0xc93c, 0x21, 0 + .dw 0x08c0, 0xc93c, 0x08ff, 0xc93c, 0x21, 0 + .dw 0x0940, 0xc93c, 0x097f, 0xc93c, 0x21, 0 + .dw 0x09c0, 0xc93c, 0x09ff, 0xc93c, 0x21, 0 + .dw 0x0a40, 0xc93c, 0x0a7f, 0xc93c, 0x21, 0 + .dw 0x0ac0, 0xc93c, 0x0aff, 0xc93c, 0x21, 0 + .dw 0x0b40, 0xc93c, 0x0b7f, 0xc93c, 0x21, 0 + .dw 0x0bc0, 0xc93c, 0x0bff, 0xc93c, 0x21, 0 + .dw 0x0c40, 0xc93c, 0x0c7f, 0xc93c, 0x21, 0 + .dw 0x0cc0, 0xc93c, 0x0cff, 0xc93c, 0x21, 0 + .dw 0x0d40, 0xc93c, 0x0d7f, 0xc93c, 0x21, 0 + .dw 0x0dc0, 0xc93c, 0x0dff, 0xc93c, 0x21, 0 + .dw 0x0e40, 0xc93c, 0x0e7f, 0xc93c, 0x21, 0 + .dw 0x0ec0, 0xc93c, 0x0eff, 0xc93c, 0x21, 0 + .dw 0x0f40, 0xc93c, 0x0f7f, 0xc93c, 0x21, 0 + .dw 0x0fc0, 0xc93c, 0x0fff, 0xc93c, 0x21, 0 + .dw 0x1040, 0xc93c, 0x107f, 0xc93c, 0x21, 0 + .dw 0x10c0, 0xc93c, 0x10ff, 0xc93c, 0x21, 0 + .dw 0x1140, 0xc93c, 0x117f, 0xc93c, 0x21, 0 + .dw 0x11c0, 0xc93c, 0x11ff, 0xc93c, 0x21, 0 + .dw 0x1240, 0xc93c, 0x127f, 0xc93c, 0x21, 0 + .dw 0x12c0, 0xc93c, 0x12ff, 0xc93c, 0x21, 0 + .dw 0x1340, 0xc93c, 0x137f, 0xc93c, 0x21, 0 + .dw 0x13c0, 0xc93c, 0x13ff, 0xc93c, 0x21, 0 + .dw 0x1440, 0xc93c, 0x147f, 0xc93c, 0x21, 0 + .dw 0x14c0, 0xc93c, 0x14ff, 0xc93c, 0x21, 0 + .dw 0x1540, 0xc93c, 0x157f, 0xc93c, 0x21, 0 + .dw 0x15c0, 0xc93c, 0x15ff, 0xc93c, 0x21, 0 + .dw 0x1640, 0xc93c, 0x167f, 0xc93c, 0x21, 0 + .dw 0x16c0, 0xc93c, 0x16ff, 0xc93c, 0x21, 0 + .dw 0x1740, 0xc93c, 0x177f, 0xc93c, 0x21, 0 + .dw 0x17c0, 0xc93c, 0x17ff, 0xc93c, 0x21, 0 + .dw 0x1840, 0xc93c, 0x187f, 0xc93c, 0x21, 0 + .dw 0x18c0, 0xc93c, 0x18ff, 0xc93c, 0x21, 0 + .dw 0x1940, 0xc93c, 0x197f, 0xc93c, 0x21, 0 + .dw 0x19c0, 0xc93c, 0x1fff, 0xc93c, 0x21, 0 + .dw 0x2040, 0xc93c, 0x207f, 0xc93c, 0x21, 0 + .dw 0x20c0, 0xc93c, 0x20ff, 0xc93c, 0x21, 0 + .dw 0x2140, 0xc93c, 0x217f, 0xc93c, 0x21, 0 + .dw 0x21c0, 0xc93c, 0x21ff, 0xc93c, 0x21, 0 + .dw 0x2240, 0xc93c, 0x227f, 0xc93c, 0x21, 0 + .dw 0x22c0, 0xc93c, 0x22ff, 0xc93c, 0x21, 0 + .dw 0x2340, 0xc93c, 0x237f, 0xc93c, 0x21, 0 + .dw 0x23c0, 0xc93c, 0x23ff, 0xc93c, 0x21, 0 + .dw 0x2440, 0xc93c, 0x247f, 0xc93c, 0x21, 0 + .dw 0x24c0, 0xc93c, 0x24ff, 0xc93c, 0x21, 0 + .dw 0x2540, 0xc93c, 0x257f, 0xc93c, 0x21, 0 + .dw 0x25c0, 0xc93c, 0x25ff, 0xc93c, 0x21, 0 + .dw 0x2640, 0xc93c, 0x267f, 0xc93c, 0x21, 0 + .dw 0x26c0, 0xc93c, 0x26ff, 0xc93c, 0x21, 0 + .dw 0x2740, 0xc93c, 0x277f, 0xc93c, 0x21, 0 + .dw 0x27c0, 0xc93c, 0x27ff, 0xc93c, 0x21, 0 + .dw 0x2840, 0xc93c, 0x287f, 0xc93c, 0x21, 0 + .dw 0x28c0, 0xc93c, 0x28ff, 0xc93c, 0x21, 0 + .dw 0x2940, 0xc93c, 0x297f, 0xc93c, 0x21, 0 + .dw 0x29c0, 0xc93c, 0x29ff, 0xc93c, 0x21, 0 + .dw 0x2a40, 0xc93c, 0x2a7f, 0xc93c, 0x21, 0 + .dw 0x2ac0, 0xc93c, 0x2aff, 0xc93c, 0x21, 0 + .dw 0x2b40, 0xc93c, 0x2b7f, 0xc93c, 0x21, 0 + .dw 0x2bc0, 0xc93c, 0x2bff, 0xc93c, 0x21, 0 + .dw 0x2c40, 0xc93c, 0x2c7f, 0xc93c, 0x21, 0 + .dw 0x2cc0, 0xc93c, 0x2cff, 0xc93c, 0x21, 0 + .dw 0x2d40, 0xc93c, 0x2d7f, 0xc93c, 0x21, 0 + .dw 0x2dc0, 0xc93c, 0x2dff, 0xc93c, 0x21, 0 + .dw 0x2e40, 0xc93c, 0x2e7f, 0xc93c, 0x21, 0 + .dw 0x2ec0, 0xc93c, 0x2eff, 0xc93c, 0x21, 0 + .dw 0x2f40, 0xc93c, 0x2f7f, 0xc93c, 0x21, 0 + .dw 0x2fc0, 0xc93c, 0x2fff, 0xc93c, 0x21, 0 + .dw 0x3040, 0xc93c, 0x307f, 0xc93c, 0x21, 0 + .dw 0x30c0, 0xc93c, 0x30ff, 0xc93c, 0x21, 0 + .dw 0x3140, 0xc93c, 0x317f, 0xc93c, 0x21, 0 + .dw 0x31c0, 0xc93c, 0x31ff, 0xc93c, 0x21, 0 + .dw 0x3240, 0xc93c, 0x327f, 0xc93c, 0x21, 0 + .dw 0x32c0, 0xc93c, 0x32ff, 0xc93c, 0x21, 0 + .dw 0x3340, 0xc93c, 0x337f, 0xc93c, 0x21, 0 + .dw 0x33c0, 0xc93c, 0x33ff, 0xc93c, 0x21, 0 + .dw 0x3440, 0xc93c, 0x347f, 0xc93c, 0x21, 0 + .dw 0x34c0, 0xc93c, 0x34ff, 0xc93c, 0x21, 0 + .dw 0x3540, 0xc93c, 0x357f, 0xc93c, 0x21, 0 + .dw 0x35c0, 0xc93c, 0x35ff, 0xc93c, 0x21, 0 + .dw 0x3640, 0xc93c, 0x367f, 0xc93c, 0x21, 0 + .dw 0x36c0, 0xc93c, 0x36ff, 0xc93c, 0x21, 0 + .dw 0x3740, 0xc93c, 0x377f, 0xc93c, 0x21, 0 + .dw 0x37c0, 0xc93c, 0x37ff, 0xc93c, 0x21, 0 + .dw 0x3840, 0xc93c, 0x387f, 0xc93c, 0x21, 0 + .dw 0x38c0, 0xc93c, 0x38ff, 0xc93c, 0x21, 0 + .dw 0x3940, 0xc93c, 0x397f, 0xc93c, 0x21, 0 + .dw 0x39c0, 0xc93c, 0x3fff, 0xc93c, 0x21, 0 + .dw 0x4040, 0xc93c, 0x407f, 0xc93c, 0x21, 0 + .dw 0x40c0, 0xc93c, 0x40ff, 0xc93c, 0x21, 0 + .dw 0x4140, 0xc93c, 0x417f, 0xc93c, 0x21, 0 + .dw 0x41c0, 0xc93c, 0x41ff, 0xc93c, 0x21, 0 + .dw 0x4240, 0xc93c, 0x427f, 0xc93c, 0x21, 0 + .dw 0x42c0, 0xc93c, 0x42ff, 0xc93c, 0x21, 0 + .dw 0x4340, 0xc93c, 0x437f, 0xc93c, 0x21, 0 + .dw 0x43c0, 0xc93c, 0x43ff, 0xc93c, 0x21, 0 + .dw 0x4440, 0xc93c, 0x447f, 0xc93c, 0x21, 0 + .dw 0x44c0, 0xc93c, 0x44ff, 0xc93c, 0x21, 0 + .dw 0x4540, 0xc93c, 0x457f, 0xc93c, 0x21, 0 + .dw 0x45c0, 0xc93c, 0x45ff, 0xc93c, 0x21, 0 + .dw 0x4640, 0xc93c, 0x467f, 0xc93c, 0x21, 0 + .dw 0x46c0, 0xc93c, 0x46ff, 0xc93c, 0x21, 0 + .dw 0x4740, 0xc93c, 0x477f, 0xc93c, 0x21, 0 + .dw 0x47c0, 0xc93c, 0x47ff, 0xc93c, 0x21, 0 + .dw 0x4840, 0xc93c, 0x487f, 0xc93c, 0x21, 0 + .dw 0x48c0, 0xc93c, 0x48ff, 0xc93c, 0x21, 0 + .dw 0x4940, 0xc93c, 0x497f, 0xc93c, 0x21, 0 + .dw 0x49c0, 0xc93c, 0x49ff, 0xc93c, 0x21, 0 + .dw 0x4a40, 0xc93c, 0x4a7f, 0xc93c, 0x21, 0 + .dw 0x4ac0, 0xc93c, 0x4aff, 0xc93c, 0x21, 0 + .dw 0x4b40, 0xc93c, 0x4b7f, 0xc93c, 0x21, 0 + .dw 0x4bc0, 0xc93c, 0x4bff, 0xc93c, 0x21, 0 + .dw 0x4c40, 0xc93c, 0x4c7f, 0xc93c, 0x21, 0 + .dw 0x4cc0, 0xc93c, 0x4cff, 0xc93c, 0x21, 0 + .dw 0x4d40, 0xc93c, 0x4d7f, 0xc93c, 0x21, 0 + .dw 0x4dc0, 0xc93c, 0x4dff, 0xc93c, 0x21, 0 + .dw 0x4e40, 0xc93c, 0x4e7f, 0xc93c, 0x21, 0 + .dw 0x4ec0, 0xc93c, 0x4eff, 0xc93c, 0x21, 0 + .dw 0x4f40, 0xc93c, 0x4f7f, 0xc93c, 0x21, 0 + .dw 0x4fc0, 0xc93c, 0x4fff, 0xc93c, 0x21, 0 + .dw 0x5040, 0xc93c, 0x507f, 0xc93c, 0x21, 0 + .dw 0x50c0, 0xc93c, 0x50ff, 0xc93c, 0x21, 0 + .dw 0x5140, 0xc93c, 0x517f, 0xc93c, 0x21, 0 + .dw 0x51c0, 0xc93c, 0x51ff, 0xc93c, 0x21, 0 + .dw 0x5240, 0xc93c, 0x527f, 0xc93c, 0x21, 0 + .dw 0x52c0, 0xc93c, 0x52ff, 0xc93c, 0x21, 0 + .dw 0x5340, 0xc93c, 0x537f, 0xc93c, 0x21, 0 + .dw 0x53c0, 0xc93c, 0x53ff, 0xc93c, 0x21, 0 + .dw 0x5440, 0xc93c, 0x547f, 0xc93c, 0x21, 0 + .dw 0x54c0, 0xc93c, 0x54ff, 0xc93c, 0x21, 0 + .dw 0x5540, 0xc93c, 0x557f, 0xc93c, 0x21, 0 + .dw 0x55c0, 0xc93c, 0x55ff, 0xc93c, 0x21, 0 + .dw 0x5640, 0xc93c, 0x567f, 0xc93c, 0x21, 0 + .dw 0x56c0, 0xc93c, 0x56ff, 0xc93c, 0x21, 0 + .dw 0x5740, 0xc93c, 0x577f, 0xc93c, 0x21, 0 + .dw 0x57c0, 0xc93c, 0x57ff, 0xc93c, 0x21, 0 + .dw 0x5840, 0xc93c, 0x587f, 0xc93c, 0x21, 0 + .dw 0x58c0, 0xc93c, 0x58ff, 0xc93c, 0x21, 0 + .dw 0x5940, 0xc93c, 0x597f, 0xc93c, 0x21, 0 + .dw 0x59c0, 0xc93c, 0x5fff, 0xc93c, 0x21, 0 + .dw 0x6040, 0xc93c, 0x607f, 0xc93c, 0x21, 0 + .dw 0x60c0, 0xc93c, 0x60ff, 0xc93c, 0x21, 0 + .dw 0x6140, 0xc93c, 0x617f, 0xc93c, 0x21, 0 + .dw 0x61c0, 0xc93c, 0x61ff, 0xc93c, 0x21, 0 + .dw 0x6240, 0xc93c, 0x627f, 0xc93c, 0x21, 0 + .dw 0x62c0, 0xc93c, 0x62ff, 0xc93c, 0x21, 0 + .dw 0x6340, 0xc93c, 0x637f, 0xc93c, 0x21, 0 + .dw 0x63c0, 0xc93c, 0x63ff, 0xc93c, 0x21, 0 + .dw 0x6440, 0xc93c, 0x647f, 0xc93c, 0x21, 0 + .dw 0x64c0, 0xc93c, 0x64ff, 0xc93c, 0x21, 0 + .dw 0x6540, 0xc93c, 0x657f, 0xc93c, 0x21, 0 + .dw 0x65c0, 0xc93c, 0x65ff, 0xc93c, 0x21, 0 + .dw 0x6640, 0xc93c, 0x667f, 0xc93c, 0x21, 0 + .dw 0x66c0, 0xc93c, 0x66ff, 0xc93c, 0x21, 0 + .dw 0x6740, 0xc93c, 0x677f, 0xc93c, 0x21, 0 + .dw 0x67c0, 0xc93c, 0x67ff, 0xc93c, 0x21, 0 + .dw 0x6840, 0xc93c, 0x687f, 0xc93c, 0x21, 0 + .dw 0x68c0, 0xc93c, 0x68ff, 0xc93c, 0x21, 0 + .dw 0x6940, 0xc93c, 0x697f, 0xc93c, 0x21, 0 + .dw 0x69c0, 0xc93c, 0x69ff, 0xc93c, 0x21, 0 + .dw 0x6a40, 0xc93c, 0x6a7f, 0xc93c, 0x21, 0 + .dw 0x6ac0, 0xc93c, 0x6aff, 0xc93c, 0x21, 0 + .dw 0x6b40, 0xc93c, 0x6b7f, 0xc93c, 0x21, 0 + .dw 0x6bc0, 0xc93c, 0x6bff, 0xc93c, 0x21, 0 + .dw 0x6c40, 0xc93c, 0x6c7f, 0xc93c, 0x21, 0 + .dw 0x6cc0, 0xc93c, 0x6cff, 0xc93c, 0x21, 0 + .dw 0x6d40, 0xc93c, 0x6d7f, 0xc93c, 0x21, 0 + .dw 0x6dc0, 0xc93c, 0x6dff, 0xc93c, 0x21, 0 + .dw 0x6e40, 0xc93c, 0x6e7f, 0xc93c, 0x21, 0 + .dw 0x6ec0, 0xc93c, 0x6eff, 0xc93c, 0x21, 0 + .dw 0x6f40, 0xc93c, 0x6f7f, 0xc93c, 0x21, 0 + .dw 0x6fc0, 0xc93c, 0x6fff, 0xc93c, 0x21, 0 + .dw 0x7040, 0xc93c, 0x707f, 0xc93c, 0x21, 0 + .dw 0x70c0, 0xc93c, 0x70ff, 0xc93c, 0x21, 0 + .dw 0x7140, 0xc93c, 0x717f, 0xc93c, 0x21, 0 + .dw 0x71c0, 0xc93c, 0x71ff, 0xc93c, 0x21, 0 + .dw 0x7240, 0xc93c, 0x727f, 0xc93c, 0x21, 0 + .dw 0x72c0, 0xc93c, 0x72ff, 0xc93c, 0x21, 0 + .dw 0x7340, 0xc93c, 0x737f, 0xc93c, 0x21, 0 + .dw 0x73c0, 0xc93c, 0x73ff, 0xc93c, 0x21, 0 + .dw 0x7440, 0xc93c, 0x747f, 0xc93c, 0x21, 0 + .dw 0x74c0, 0xc93c, 0x74ff, 0xc93c, 0x21, 0 + .dw 0x7540, 0xc93c, 0x757f, 0xc93c, 0x21, 0 + .dw 0x75c0, 0xc93c, 0x75ff, 0xc93c, 0x21, 0 + .dw 0x7640, 0xc93c, 0x767f, 0xc93c, 0x21, 0 + .dw 0x76c0, 0xc93c, 0x76ff, 0xc93c, 0x21, 0 + .dw 0x7740, 0xc93c, 0x777f, 0xc93c, 0x21, 0 + .dw 0x77c0, 0xc93c, 0x77ff, 0xc93c, 0x21, 0 + .dw 0x7840, 0xc93c, 0x787f, 0xc93c, 0x21, 0 + .dw 0x78c0, 0xc93c, 0x78ff, 0xc93c, 0x21, 0 + .dw 0x7940, 0xc93c, 0x797f, 0xc93c, 0x21, 0 + .dw 0x79c0, 0xc93c, 0x7fff, 0xc93c, 0x21, 0 + .dw 0x8040, 0xc93c, 0x807f, 0xc93c, 0x21, 0 + .dw 0x80c0, 0xc93c, 0x80ff, 0xc93c, 0x21, 0 + .dw 0x8140, 0xc93c, 0x817f, 0xc93c, 0x21, 0 + .dw 0x81c0, 0xc93c, 0x81ff, 0xc93c, 0x21, 0 + .dw 0x8240, 0xc93c, 0x827f, 0xc93c, 0x21, 0 + .dw 0x82c0, 0xc93c, 0x82ff, 0xc93c, 0x21, 0 + .dw 0x8340, 0xc93c, 0x837f, 0xc93c, 0x21, 0 + .dw 0x83c0, 0xc93c, 0x83ff, 0xc93c, 0x21, 0 + .dw 0x8440, 0xc93c, 0x847f, 0xc93c, 0x21, 0 + .dw 0x84c0, 0xc93c, 0x84ff, 0xc93c, 0x21, 0 + .dw 0x8540, 0xc93c, 0x857f, 0xc93c, 0x21, 0 + .dw 0x85c0, 0xc93c, 0x85ff, 0xc93c, 0x21, 0 + .dw 0x8640, 0xc93c, 0x867f, 0xc93c, 0x21, 0 + .dw 0x86c0, 0xc93c, 0x86ff, 0xc93c, 0x21, 0 + .dw 0x8740, 0xc93c, 0x877f, 0xc93c, 0x21, 0 + .dw 0x87c0, 0xc93c, 0x87ff, 0xc93c, 0x21, 0 + .dw 0x8840, 0xc93c, 0x887f, 0xc93c, 0x21, 0 + .dw 0x88c0, 0xc93c, 0x88ff, 0xc93c, 0x21, 0 + .dw 0x8940, 0xc93c, 0x897f, 0xc93c, 0x21, 0 + .dw 0x89c0, 0xc93c, 0x89ff, 0xc93c, 0x21, 0 + .dw 0x8a40, 0xc93c, 0x8a7f, 0xc93c, 0x21, 0 + .dw 0x8ac0, 0xc93c, 0x8aff, 0xc93c, 0x21, 0 + .dw 0x8b40, 0xc93c, 0x8b7f, 0xc93c, 0x21, 0 + .dw 0x8bc0, 0xc93c, 0x8bff, 0xc93c, 0x21, 0 + .dw 0x8c40, 0xc93c, 0x8c7f, 0xc93c, 0x21, 0 + .dw 0x8cc0, 0xc93c, 0x8cff, 0xc93c, 0x21, 0 + .dw 0x8d40, 0xc93c, 0x8d7f, 0xc93c, 0x21, 0 + .dw 0x8dc0, 0xc93c, 0x8dff, 0xc93c, 0x21, 0 + .dw 0x8e40, 0xc93c, 0x8e7f, 0xc93c, 0x21, 0 + .dw 0x8ec0, 0xc93c, 0x8eff, 0xc93c, 0x21, 0 + .dw 0x8f40, 0xc93c, 0x8f7f, 0xc93c, 0x21, 0 + .dw 0x8fc0, 0xc93c, 0x8fff, 0xc93c, 0x21, 0 + .dw 0x9040, 0xc93c, 0x907f, 0xc93c, 0x21, 0 + .dw 0x90c0, 0xc93c, 0x90ff, 0xc93c, 0x21, 0 + .dw 0x9140, 0xc93c, 0x917f, 0xc93c, 0x21, 0 + .dw 0x91c0, 0xc93c, 0x91ff, 0xc93c, 0x21, 0 + .dw 0x9240, 0xc93c, 0x927f, 0xc93c, 0x21, 0 + .dw 0x92c0, 0xc93c, 0x92ff, 0xc93c, 0x21, 0 + .dw 0x9340, 0xc93c, 0x937f, 0xc93c, 0x21, 0 + .dw 0x93c0, 0xc93c, 0x93ff, 0xc93c, 0x21, 0 + .dw 0x9440, 0xc93c, 0x947f, 0xc93c, 0x21, 0 + .dw 0x94c0, 0xc93c, 0x94ff, 0xc93c, 0x21, 0 + .dw 0x9540, 0xc93c, 0x957f, 0xc93c, 0x21, 0 + .dw 0x95c0, 0xc93c, 0x95ff, 0xc93c, 0x21, 0 + .dw 0x9640, 0xc93c, 0x967f, 0xc93c, 0x21, 0 + .dw 0x96c0, 0xc93c, 0x96ff, 0xc93c, 0x21, 0 + .dw 0x9740, 0xc93c, 0x977f, 0xc93c, 0x21, 0 + .dw 0x97c0, 0xc93c, 0x97ff, 0xc93c, 0x21, 0 + .dw 0x9840, 0xc93c, 0x987f, 0xc93c, 0x21, 0 + .dw 0x98c0, 0xc93c, 0x98ff, 0xc93c, 0x21, 0 + .dw 0x9940, 0xc93c, 0x997f, 0xc93c, 0x21, 0 + .dw 0x99c0, 0xc93c, 0x9fff, 0xc93c, 0x21, 0 + .dw 0xa040, 0xc93c, 0xa07f, 0xc93c, 0x21, 0 + .dw 0xa0c0, 0xc93c, 0xa0ff, 0xc93c, 0x21, 0 + .dw 0xa140, 0xc93c, 0xa17f, 0xc93c, 0x21, 0 + .dw 0xa1c0, 0xc93c, 0xa1ff, 0xc93c, 0x21, 0 + .dw 0xa240, 0xc93c, 0xa27f, 0xc93c, 0x21, 0 + .dw 0xa2c0, 0xc93c, 0xa2ff, 0xc93c, 0x21, 0 + .dw 0xa340, 0xc93c, 0xa37f, 0xc93c, 0x21, 0 + .dw 0xa3c0, 0xc93c, 0xa3ff, 0xc93c, 0x21, 0 + .dw 0xa440, 0xc93c, 0xa47f, 0xc93c, 0x21, 0 + .dw 0xa4c0, 0xc93c, 0xa4ff, 0xc93c, 0x21, 0 + .dw 0xa540, 0xc93c, 0xa57f, 0xc93c, 0x21, 0 + .dw 0xa5c0, 0xc93c, 0xa5ff, 0xc93c, 0x21, 0 + .dw 0xa640, 0xc93c, 0xa67f, 0xc93c, 0x21, 0 + .dw 0xa6c0, 0xc93c, 0xa6ff, 0xc93c, 0x21, 0 + .dw 0xa740, 0xc93c, 0xa77f, 0xc93c, 0x21, 0 + .dw 0xa7c0, 0xc93c, 0xa7ff, 0xc93c, 0x21, 0 + .dw 0xa840, 0xc93c, 0xa87f, 0xc93c, 0x21, 0 + .dw 0xa8c0, 0xc93c, 0xa8ff, 0xc93c, 0x21, 0 + .dw 0xa940, 0xc93c, 0xa97f, 0xc93c, 0x21, 0 + .dw 0xa9c0, 0xc93c, 0xa9ff, 0xc93c, 0x21, 0 + .dw 0xaa40, 0xc93c, 0xaa7f, 0xc93c, 0x21, 0 + .dw 0xaac0, 0xc93c, 0xaaff, 0xc93c, 0x21, 0 + .dw 0xab40, 0xc93c, 0xab7f, 0xc93c, 0x21, 0 + .dw 0xabc0, 0xc93c, 0xabff, 0xc93c, 0x21, 0 + .dw 0xac40, 0xc93c, 0xac7f, 0xc93c, 0x21, 0 + .dw 0xacc0, 0xc93c, 0xacff, 0xc93c, 0x21, 0 + .dw 0xad40, 0xc93c, 0xad7f, 0xc93c, 0x21, 0 + .dw 0xadc0, 0xc93c, 0xadff, 0xc93c, 0x21, 0 + .dw 0xae40, 0xc93c, 0xae7f, 0xc93c, 0x21, 0 + .dw 0xaec0, 0xc93c, 0xaeff, 0xc93c, 0x21, 0 + .dw 0xaf40, 0xc93c, 0xaf7f, 0xc93c, 0x21, 0 + .dw 0xafc0, 0xc93c, 0xafff, 0xc93c, 0x21, 0 + .dw 0xb040, 0xc93c, 0xb07f, 0xc93c, 0x21, 0 + .dw 0xb0c0, 0xc93c, 0xb0ff, 0xc93c, 0x21, 0 + .dw 0xb140, 0xc93c, 0xb17f, 0xc93c, 0x21, 0 + .dw 0xb1c0, 0xc93c, 0xb1ff, 0xc93c, 0x21, 0 + .dw 0xb240, 0xc93c, 0xb27f, 0xc93c, 0x21, 0 + .dw 0xb2c0, 0xc93c, 0xb2ff, 0xc93c, 0x21, 0 + .dw 0xb340, 0xc93c, 0xb37f, 0xc93c, 0x21, 0 + .dw 0xb3c0, 0xc93c, 0xb3ff, 0xc93c, 0x21, 0 + .dw 0xb440, 0xc93c, 0xb47f, 0xc93c, 0x21, 0 + .dw 0xb4c0, 0xc93c, 0xb4ff, 0xc93c, 0x21, 0 + .dw 0xb540, 0xc93c, 0xb57f, 0xc93c, 0x21, 0 + .dw 0xb5c0, 0xc93c, 0xb5ff, 0xc93c, 0x21, 0 + .dw 0xb640, 0xc93c, 0xb67f, 0xc93c, 0x21, 0 + .dw 0xb6c0, 0xc93c, 0xb6ff, 0xc93c, 0x21, 0 + .dw 0xb740, 0xc93c, 0xb77f, 0xc93c, 0x21, 0 + .dw 0xb7c0, 0xc93c, 0xb7ff, 0xc93c, 0x21, 0 + .dw 0xb840, 0xc93c, 0xb87f, 0xc93c, 0x21, 0 + .dw 0xb8c0, 0xc93c, 0xb8ff, 0xc93c, 0x21, 0 + .dw 0xb940, 0xc93c, 0xb97f, 0xc93c, 0x21, 0 + .dw 0xb9c0, 0xc93c, 0xbfff, 0xc93c, 0x21, 0 + .dw 0xc040, 0xc93c, 0xc07f, 0xc93c, 0x21, 0 + .dw 0xc0c0, 0xc93c, 0xc0ff, 0xc93c, 0x21, 0 + .dw 0xc140, 0xc93c, 0xc17f, 0xc93c, 0x21, 0 + .dw 0xc1c0, 0xc93c, 0xc1ff, 0xc93c, 0x21, 0 + .dw 0xc240, 0xc93c, 0xc27f, 0xc93c, 0x21, 0 + .dw 0xc2c0, 0xc93c, 0xc2ff, 0xc93c, 0x21, 0 + .dw 0xc340, 0xc93c, 0xc37f, 0xc93c, 0x21, 0 + .dw 0xc3c0, 0xc93c, 0xc3ff, 0xc93c, 0x21, 0 + .dw 0xc440, 0xc93c, 0xc47f, 0xc93c, 0x21, 0 + .dw 0xc4c0, 0xc93c, 0xc4ff, 0xc93c, 0x21, 0 + .dw 0xc540, 0xc93c, 0xc57f, 0xc93c, 0x21, 0 + .dw 0xc5c0, 0xc93c, 0xc5ff, 0xc93c, 0x21, 0 + .dw 0xc640, 0xc93c, 0xc67f, 0xc93c, 0x21, 0 + .dw 0xc6c0, 0xc93c, 0xc6ff, 0xc93c, 0x21, 0 + .dw 0xc740, 0xc93c, 0xc77f, 0xc93c, 0x21, 0 + .dw 0xc7c0, 0xc93c, 0xc7ff, 0xc93c, 0x21, 0 + .dw 0xc840, 0xc93c, 0xc87f, 0xc93c, 0x21, 0 + .dw 0xc8c0, 0xc93c, 0xc8ff, 0xc93c, 0x21, 0 + .dw 0xc940, 0xc93c, 0xc97f, 0xc93c, 0x21, 0 + .dw 0xc9c0, 0xc93c, 0xc9ff, 0xc93c, 0x21, 0 + .dw 0xca40, 0xc93c, 0xca7f, 0xc93c, 0x21, 0 + .dw 0xcac0, 0xc93c, 0xcaff, 0xc93c, 0x21, 0 + .dw 0xcb40, 0xc93c, 0xcb7f, 0xc93c, 0x21, 0 + .dw 0xcbc0, 0xc93c, 0xcbff, 0xc93c, 0x21, 0 + .dw 0xcc40, 0xc93c, 0xcc7f, 0xc93c, 0x21, 0 + .dw 0xccc0, 0xc93c, 0xccff, 0xc93c, 0x21, 0 + .dw 0xcd40, 0xc93c, 0xcd7f, 0xc93c, 0x21, 0 + .dw 0xcdc0, 0xc93c, 0xcdff, 0xc93c, 0x21, 0 + .dw 0xce40, 0xc93c, 0xce7f, 0xc93c, 0x21, 0 + .dw 0xcec0, 0xc93c, 0xceff, 0xc93c, 0x21, 0 + .dw 0xcf40, 0xc93c, 0xcf7f, 0xc93c, 0x21, 0 + .dw 0xcfc0, 0xc93c, 0xcfff, 0xc93c, 0x21, 0 + .dw 0xd040, 0xc93c, 0xd07f, 0xc93c, 0x21, 0 + .dw 0xd0c0, 0xc93c, 0xd0ff, 0xc93c, 0x21, 0 + .dw 0xd140, 0xc93c, 0xd17f, 0xc93c, 0x21, 0 + .dw 0xd1c0, 0xc93c, 0xd1ff, 0xc93c, 0x21, 0 + .dw 0xd240, 0xc93c, 0xd27f, 0xc93c, 0x21, 0 + .dw 0xd2c0, 0xc93c, 0xd2ff, 0xc93c, 0x21, 0 + .dw 0xd340, 0xc93c, 0xd37f, 0xc93c, 0x21, 0 + .dw 0xd3c0, 0xc93c, 0xd3ff, 0xc93c, 0x21, 0 + .dw 0xd440, 0xc93c, 0xd47f, 0xc93c, 0x21, 0 + .dw 0xd4c0, 0xc93c, 0xd4ff, 0xc93c, 0x21, 0 + .dw 0xd540, 0xc93c, 0xd57f, 0xc93c, 0x21, 0 + .dw 0xd5c0, 0xc93c, 0xd5ff, 0xc93c, 0x21, 0 + .dw 0xd640, 0xc93c, 0xd67f, 0xc93c, 0x21, 0 + .dw 0xd6c0, 0xc93c, 0xd6ff, 0xc93c, 0x21, 0 + .dw 0xd740, 0xc93c, 0xd77f, 0xc93c, 0x21, 0 + .dw 0xd7c0, 0xc93c, 0xd7ff, 0xc93c, 0x21, 0 + .dw 0xd840, 0xc93c, 0xd87f, 0xc93c, 0x21, 0 + .dw 0xd8c0, 0xc93c, 0xd8ff, 0xc93c, 0x21, 0 + .dw 0xd940, 0xc93c, 0xd97f, 0xc93c, 0x21, 0 + .dw 0xd9c0, 0xc93c, 0xdfff, 0xc93c, 0x21, 0 + .dw 0xe040, 0xc93c, 0xe07f, 0xc93c, 0x21, 0 + .dw 0xe0c0, 0xc93c, 0xe0ff, 0xc93c, 0x21, 0 + .dw 0xe140, 0xc93c, 0xe17f, 0xc93c, 0x21, 0 + .dw 0xe1c0, 0xc93c, 0xe1ff, 0xc93c, 0x21, 0 + .dw 0xe240, 0xc93c, 0xe27f, 0xc93c, 0x21, 0 + .dw 0xe2c0, 0xc93c, 0xe2ff, 0xc93c, 0x21, 0 + .dw 0xe340, 0xc93c, 0xe37f, 0xc93c, 0x21, 0 + .dw 0xe3c0, 0xc93c, 0xe3ff, 0xc93c, 0x21, 0 + .dw 0xe440, 0xc93c, 0xe47f, 0xc93c, 0x21, 0 + .dw 0xe4c0, 0xc93c, 0xe4ff, 0xc93c, 0x21, 0 + .dw 0xe540, 0xc93c, 0xe57f, 0xc93c, 0x21, 0 + .dw 0xe5c0, 0xc93c, 0xe5ff, 0xc93c, 0x21, 0 + .dw 0xe640, 0xc93c, 0xe67f, 0xc93c, 0x21, 0 + .dw 0xe6c0, 0xc93c, 0xe6ff, 0xc93c, 0x21, 0 + .dw 0xe740, 0xc93c, 0xe77f, 0xc93c, 0x21, 0 + .dw 0xe7c0, 0xc93c, 0xe7ff, 0xc93c, 0x21, 0 + .dw 0xe840, 0xc93c, 0xe87f, 0xc93c, 0x21, 0 + .dw 0xe8c0, 0xc93c, 0xe8ff, 0xc93c, 0x21, 0 + .dw 0xe940, 0xc93c, 0xe97f, 0xc93c, 0x21, 0 + .dw 0xe9c0, 0xc93c, 0xe9ff, 0xc93c, 0x21, 0 + .dw 0xea40, 0xc93c, 0xea7f, 0xc93c, 0x21, 0 + .dw 0xeac0, 0xc93c, 0xeaff, 0xc93c, 0x21, 0 + .dw 0xeb40, 0xc93c, 0xeb7f, 0xc93c, 0x21, 0 + .dw 0xebc0, 0xc93c, 0xebff, 0xc93c, 0x21, 0 + .dw 0xec40, 0xc93c, 0xec7f, 0xc93c, 0x21, 0 + .dw 0xecc0, 0xc93c, 0xecff, 0xc93c, 0x21, 0 + .dw 0xed40, 0xc93c, 0xed7f, 0xc93c, 0x21, 0 + .dw 0xedc0, 0xc93c, 0xedff, 0xc93c, 0x21, 0 + .dw 0xee40, 0xc93c, 0xee7f, 0xc93c, 0x21, 0 + .dw 0xeec0, 0xc93c, 0xeeff, 0xc93c, 0x21, 0 + .dw 0xef40, 0xc93c, 0xef7f, 0xc93c, 0x21, 0 + .dw 0xefc0, 0xc93c, 0xefff, 0xc93c, 0x21, 0 + .dw 0xf040, 0xc93c, 0xf07f, 0xc93c, 0x21, 0 + .dw 0xf0c0, 0xc93c, 0xf0ff, 0xc93c, 0x21, 0 + .dw 0xf140, 0xc93c, 0xf17f, 0xc93c, 0x21, 0 + .dw 0xf1c0, 0xc93c, 0xf1ff, 0xc93c, 0x21, 0 + .dw 0xf240, 0xc93c, 0xf27f, 0xc93c, 0x21, 0 + .dw 0xf2c0, 0xc93c, 0xf2ff, 0xc93c, 0x21, 0 + .dw 0xf340, 0xc93c, 0xf37f, 0xc93c, 0x21, 0 + .dw 0xf3c0, 0xc93c, 0xf3ff, 0xc93c, 0x21, 0 + .dw 0xf440, 0xc93c, 0xf47f, 0xc93c, 0x21, 0 + .dw 0xf4c0, 0xc93c, 0xf4ff, 0xc93c, 0x21, 0 + .dw 0xf540, 0xc93c, 0xf57f, 0xc93c, 0x21, 0 + .dw 0xf5c0, 0xc93c, 0xf5ff, 0xc93c, 0x21, 0 + .dw 0xf640, 0xc93c, 0xf67f, 0xc93c, 0x21, 0 + .dw 0xf6c0, 0xc93c, 0xf6ff, 0xc93c, 0x21, 0 + .dw 0xf740, 0xc93c, 0xf77f, 0xc93c, 0x21, 0 + .dw 0xf7c0, 0xc93c, 0xf7ff, 0xc93c, 0x21, 0 + .dw 0xf840, 0xc93c, 0xf87f, 0xc93c, 0x21, 0 + .dw 0xf8c0, 0xc93c, 0xf8ff, 0xc93c, 0x21, 0 + .dw 0xf940, 0xc93c, 0xf97f, 0xc93c, 0x21, 0 + .dw 0xf9c0, 0xc93c, 0xffff, 0xc93c, 0x21, 0 + .dw 0x0040, 0xc93d, 0x007f, 0xc93d, 0x21, 0 + .dw 0x00c0, 0xc93d, 0x00ff, 0xc93d, 0x21, 0 + .dw 0x0140, 0xc93d, 0x017f, 0xc93d, 0x21, 0 + .dw 0x01c0, 0xc93d, 0x01ff, 0xc93d, 0x21, 0 + .dw 0x0240, 0xc93d, 0x027f, 0xc93d, 0x21, 0 + .dw 0x02c0, 0xc93d, 0x02ff, 0xc93d, 0x21, 0 + .dw 0x0340, 0xc93d, 0x037f, 0xc93d, 0x21, 0 + .dw 0x03c0, 0xc93d, 0x03ff, 0xc93d, 0x21, 0 + .dw 0x0440, 0xc93d, 0x047f, 0xc93d, 0x21, 0 + .dw 0x04c0, 0xc93d, 0x04ff, 0xc93d, 0x21, 0 + .dw 0x0540, 0xc93d, 0x057f, 0xc93d, 0x21, 0 + .dw 0x05c0, 0xc93d, 0x05ff, 0xc93d, 0x21, 0 + .dw 0x0640, 0xc93d, 0x067f, 0xc93d, 0x21, 0 + .dw 0x06c0, 0xc93d, 0x06ff, 0xc93d, 0x21, 0 + .dw 0x0740, 0xc93d, 0x077f, 0xc93d, 0x21, 0 + .dw 0x07c0, 0xc93d, 0x07ff, 0xc93d, 0x21, 0 + .dw 0x0840, 0xc93d, 0x087f, 0xc93d, 0x21, 0 + .dw 0x08c0, 0xc93d, 0x08ff, 0xc93d, 0x21, 0 + .dw 0x0940, 0xc93d, 0x097f, 0xc93d, 0x21, 0 + .dw 0x09c0, 0xc93d, 0x09ff, 0xc93d, 0x21, 0 + .dw 0x0a40, 0xc93d, 0x0a7f, 0xc93d, 0x21, 0 + .dw 0x0ac0, 0xc93d, 0x0aff, 0xc93d, 0x21, 0 + .dw 0x0b40, 0xc93d, 0x0b7f, 0xc93d, 0x21, 0 + .dw 0x0bc0, 0xc93d, 0x0bff, 0xc93d, 0x21, 0 + .dw 0x0c40, 0xc93d, 0x0c7f, 0xc93d, 0x21, 0 + .dw 0x0cc0, 0xc93d, 0x0cff, 0xc93d, 0x21, 0 + .dw 0x0d40, 0xc93d, 0x0d7f, 0xc93d, 0x21, 0 + .dw 0x0dc0, 0xc93d, 0x0dff, 0xc93d, 0x21, 0 + .dw 0x0e40, 0xc93d, 0x0e7f, 0xc93d, 0x21, 0 + .dw 0x0ec0, 0xc93d, 0x0eff, 0xc93d, 0x21, 0 + .dw 0x0f40, 0xc93d, 0x0f7f, 0xc93d, 0x21, 0 + .dw 0x0fc0, 0xc93d, 0x0fff, 0xc93d, 0x21, 0 + .dw 0x1040, 0xc93d, 0x107f, 0xc93d, 0x21, 0 + .dw 0x10c0, 0xc93d, 0x10ff, 0xc93d, 0x21, 0 + .dw 0x1140, 0xc93d, 0x117f, 0xc93d, 0x21, 0 + .dw 0x11c0, 0xc93d, 0x11ff, 0xc93d, 0x21, 0 + .dw 0x1240, 0xc93d, 0x127f, 0xc93d, 0x21, 0 + .dw 0x12c0, 0xc93d, 0x12ff, 0xc93d, 0x21, 0 + .dw 0x1340, 0xc93d, 0x137f, 0xc93d, 0x21, 0 + .dw 0x13c0, 0xc93d, 0x13ff, 0xc93d, 0x21, 0 + .dw 0x1440, 0xc93d, 0x147f, 0xc93d, 0x21, 0 + .dw 0x14c0, 0xc93d, 0x14ff, 0xc93d, 0x21, 0 + .dw 0x1540, 0xc93d, 0x157f, 0xc93d, 0x21, 0 + .dw 0x15c0, 0xc93d, 0x15ff, 0xc93d, 0x21, 0 + .dw 0x1640, 0xc93d, 0x167f, 0xc93d, 0x21, 0 + .dw 0x16c0, 0xc93d, 0x16ff, 0xc93d, 0x21, 0 + .dw 0x1740, 0xc93d, 0x177f, 0xc93d, 0x21, 0 + .dw 0x17c0, 0xc93d, 0x17ff, 0xc93d, 0x21, 0 + .dw 0x1840, 0xc93d, 0x187f, 0xc93d, 0x21, 0 + .dw 0x18c0, 0xc93d, 0x18ff, 0xc93d, 0x21, 0 + .dw 0x1940, 0xc93d, 0x197f, 0xc93d, 0x21, 0 + .dw 0x19c0, 0xc93d, 0x1fff, 0xc93d, 0x21, 0 + .dw 0x2040, 0xc93d, 0x207f, 0xc93d, 0x21, 0 + .dw 0x20c0, 0xc93d, 0x20ff, 0xc93d, 0x21, 0 + .dw 0x2140, 0xc93d, 0x217f, 0xc93d, 0x21, 0 + .dw 0x21c0, 0xc93d, 0x21ff, 0xc93d, 0x21, 0 + .dw 0x2240, 0xc93d, 0x227f, 0xc93d, 0x21, 0 + .dw 0x22c0, 0xc93d, 0x22ff, 0xc93d, 0x21, 0 + .dw 0x2340, 0xc93d, 0x237f, 0xc93d, 0x21, 0 + .dw 0x23c0, 0xc93d, 0x23ff, 0xc93d, 0x21, 0 + .dw 0x2440, 0xc93d, 0x247f, 0xc93d, 0x21, 0 + .dw 0x24c0, 0xc93d, 0x24ff, 0xc93d, 0x21, 0 + .dw 0x2540, 0xc93d, 0x257f, 0xc93d, 0x21, 0 + .dw 0x25c0, 0xc93d, 0x25ff, 0xc93d, 0x21, 0 + .dw 0x2640, 0xc93d, 0x267f, 0xc93d, 0x21, 0 + .dw 0x26c0, 0xc93d, 0x26ff, 0xc93d, 0x21, 0 + .dw 0x2740, 0xc93d, 0x277f, 0xc93d, 0x21, 0 + .dw 0x27c0, 0xc93d, 0x27ff, 0xc93d, 0x21, 0 + .dw 0x2840, 0xc93d, 0x287f, 0xc93d, 0x21, 0 + .dw 0x28c0, 0xc93d, 0x28ff, 0xc93d, 0x21, 0 + .dw 0x2940, 0xc93d, 0x297f, 0xc93d, 0x21, 0 + .dw 0x29c0, 0xc93d, 0x29ff, 0xc93d, 0x21, 0 + .dw 0x2a40, 0xc93d, 0x2a7f, 0xc93d, 0x21, 0 + .dw 0x2ac0, 0xc93d, 0x2aff, 0xc93d, 0x21, 0 + .dw 0x2b40, 0xc93d, 0x2b7f, 0xc93d, 0x21, 0 + .dw 0x2bc0, 0xc93d, 0x2bff, 0xc93d, 0x21, 0 + .dw 0x2c40, 0xc93d, 0x2c7f, 0xc93d, 0x21, 0 + .dw 0x2cc0, 0xc93d, 0x2cff, 0xc93d, 0x21, 0 + .dw 0x2d40, 0xc93d, 0x2d7f, 0xc93d, 0x21, 0 + .dw 0x2dc0, 0xc93d, 0x2dff, 0xc93d, 0x21, 0 + .dw 0x2e40, 0xc93d, 0x2e7f, 0xc93d, 0x21, 0 + .dw 0x2ec0, 0xc93d, 0x2eff, 0xc93d, 0x21, 0 + .dw 0x2f40, 0xc93d, 0x2f7f, 0xc93d, 0x21, 0 + .dw 0x2fc0, 0xc93d, 0x2fff, 0xc93d, 0x21, 0 + .dw 0x3040, 0xc93d, 0x307f, 0xc93d, 0x21, 0 + .dw 0x30c0, 0xc93d, 0x30ff, 0xc93d, 0x21, 0 + .dw 0x3140, 0xc93d, 0x317f, 0xc93d, 0x21, 0 + .dw 0x31c0, 0xc93d, 0x31ff, 0xc93d, 0x21, 0 + .dw 0x3240, 0xc93d, 0x327f, 0xc93d, 0x21, 0 + .dw 0x32c0, 0xc93d, 0x32ff, 0xc93d, 0x21, 0 + .dw 0x3340, 0xc93d, 0x337f, 0xc93d, 0x21, 0 + .dw 0x33c0, 0xc93d, 0x33ff, 0xc93d, 0x21, 0 + .dw 0x3440, 0xc93d, 0x347f, 0xc93d, 0x21, 0 + .dw 0x34c0, 0xc93d, 0x34ff, 0xc93d, 0x21, 0 + .dw 0x3540, 0xc93d, 0x357f, 0xc93d, 0x21, 0 + .dw 0x35c0, 0xc93d, 0x35ff, 0xc93d, 0x21, 0 + .dw 0x3640, 0xc93d, 0x367f, 0xc93d, 0x21, 0 + .dw 0x36c0, 0xc93d, 0x36ff, 0xc93d, 0x21, 0 + .dw 0x3740, 0xc93d, 0x377f, 0xc93d, 0x21, 0 + .dw 0x37c0, 0xc93d, 0x37ff, 0xc93d, 0x21, 0 + .dw 0x3840, 0xc93d, 0x387f, 0xc93d, 0x21, 0 + .dw 0x38c0, 0xc93d, 0x38ff, 0xc93d, 0x21, 0 + .dw 0x3940, 0xc93d, 0x397f, 0xc93d, 0x21, 0 + .dw 0x39c0, 0xc93d, 0x3fff, 0xc93d, 0x21, 0 + .dw 0x4040, 0xc93d, 0x407f, 0xc93d, 0x21, 0 + .dw 0x40c0, 0xc93d, 0x40ff, 0xc93d, 0x21, 0 + .dw 0x4140, 0xc93d, 0x417f, 0xc93d, 0x21, 0 + .dw 0x41c0, 0xc93d, 0x41ff, 0xc93d, 0x21, 0 + .dw 0x4240, 0xc93d, 0x427f, 0xc93d, 0x21, 0 + .dw 0x42c0, 0xc93d, 0x42ff, 0xc93d, 0x21, 0 + .dw 0x4340, 0xc93d, 0x437f, 0xc93d, 0x21, 0 + .dw 0x43c0, 0xc93d, 0x43ff, 0xc93d, 0x21, 0 + .dw 0x4440, 0xc93d, 0x447f, 0xc93d, 0x21, 0 + .dw 0x44c0, 0xc93d, 0x44ff, 0xc93d, 0x21, 0 + .dw 0x4540, 0xc93d, 0x457f, 0xc93d, 0x21, 0 + .dw 0x45c0, 0xc93d, 0x45ff, 0xc93d, 0x21, 0 + .dw 0x4640, 0xc93d, 0x467f, 0xc93d, 0x21, 0 + .dw 0x46c0, 0xc93d, 0x46ff, 0xc93d, 0x21, 0 + .dw 0x4740, 0xc93d, 0x477f, 0xc93d, 0x21, 0 + .dw 0x47c0, 0xc93d, 0x47ff, 0xc93d, 0x21, 0 + .dw 0x4840, 0xc93d, 0x487f, 0xc93d, 0x21, 0 + .dw 0x48c0, 0xc93d, 0x48ff, 0xc93d, 0x21, 0 + .dw 0x4940, 0xc93d, 0x497f, 0xc93d, 0x21, 0 + .dw 0x49c0, 0xc93d, 0x49ff, 0xc93d, 0x21, 0 + .dw 0x4a40, 0xc93d, 0x4a7f, 0xc93d, 0x21, 0 + .dw 0x4ac0, 0xc93d, 0x4aff, 0xc93d, 0x21, 0 + .dw 0x4b40, 0xc93d, 0x4b7f, 0xc93d, 0x21, 0 + .dw 0x4bc0, 0xc93d, 0x4bff, 0xc93d, 0x21, 0 + .dw 0x4c40, 0xc93d, 0x4c7f, 0xc93d, 0x21, 0 + .dw 0x4cc0, 0xc93d, 0x4cff, 0xc93d, 0x21, 0 + .dw 0x4d40, 0xc93d, 0x4d7f, 0xc93d, 0x21, 0 + .dw 0x4dc0, 0xc93d, 0x4dff, 0xc93d, 0x21, 0 + .dw 0x4e40, 0xc93d, 0x4e7f, 0xc93d, 0x21, 0 + .dw 0x4ec0, 0xc93d, 0x4eff, 0xc93d, 0x21, 0 + .dw 0x4f40, 0xc93d, 0x4f7f, 0xc93d, 0x21, 0 + .dw 0x4fc0, 0xc93d, 0x4fff, 0xc93d, 0x21, 0 + .dw 0x5040, 0xc93d, 0x507f, 0xc93d, 0x21, 0 + .dw 0x50c0, 0xc93d, 0x50ff, 0xc93d, 0x21, 0 + .dw 0x5140, 0xc93d, 0x517f, 0xc93d, 0x21, 0 + .dw 0x51c0, 0xc93d, 0x51ff, 0xc93d, 0x21, 0 + .dw 0x5240, 0xc93d, 0x527f, 0xc93d, 0x21, 0 + .dw 0x52c0, 0xc93d, 0x52ff, 0xc93d, 0x21, 0 + .dw 0x5340, 0xc93d, 0x537f, 0xc93d, 0x21, 0 + .dw 0x53c0, 0xc93d, 0x53ff, 0xc93d, 0x21, 0 + .dw 0x5440, 0xc93d, 0x547f, 0xc93d, 0x21, 0 + .dw 0x54c0, 0xc93d, 0x54ff, 0xc93d, 0x21, 0 + .dw 0x5540, 0xc93d, 0x557f, 0xc93d, 0x21, 0 + .dw 0x55c0, 0xc93d, 0x55ff, 0xc93d, 0x21, 0 + .dw 0x5640, 0xc93d, 0x567f, 0xc93d, 0x21, 0 + .dw 0x56c0, 0xc93d, 0x56ff, 0xc93d, 0x21, 0 + .dw 0x5740, 0xc93d, 0x577f, 0xc93d, 0x21, 0 + .dw 0x57c0, 0xc93d, 0x57ff, 0xc93d, 0x21, 0 + .dw 0x5840, 0xc93d, 0x587f, 0xc93d, 0x21, 0 + .dw 0x58c0, 0xc93d, 0x58ff, 0xc93d, 0x21, 0 + .dw 0x5940, 0xc93d, 0x597f, 0xc93d, 0x21, 0 + .dw 0x59c0, 0xc93d, 0x5fff, 0xc93d, 0x21, 0 + .dw 0x6040, 0xc93d, 0x607f, 0xc93d, 0x21, 0 + .dw 0x60c0, 0xc93d, 0x60ff, 0xc93d, 0x21, 0 + .dw 0x6140, 0xc93d, 0x617f, 0xc93d, 0x21, 0 + .dw 0x61c0, 0xc93d, 0x61ff, 0xc93d, 0x21, 0 + .dw 0x6240, 0xc93d, 0x627f, 0xc93d, 0x21, 0 + .dw 0x62c0, 0xc93d, 0x62ff, 0xc93d, 0x21, 0 + .dw 0x6340, 0xc93d, 0x637f, 0xc93d, 0x21, 0 + .dw 0x63c0, 0xc93d, 0x63ff, 0xc93d, 0x21, 0 + .dw 0x6440, 0xc93d, 0x647f, 0xc93d, 0x21, 0 + .dw 0x64c0, 0xc93d, 0x64ff, 0xc93d, 0x21, 0 + .dw 0x6540, 0xc93d, 0x657f, 0xc93d, 0x21, 0 + .dw 0x65c0, 0xc93d, 0x65ff, 0xc93d, 0x21, 0 + .dw 0x6640, 0xc93d, 0x667f, 0xc93d, 0x21, 0 + .dw 0x66c0, 0xc93d, 0x66ff, 0xc93d, 0x21, 0 + .dw 0x6740, 0xc93d, 0x677f, 0xc93d, 0x21, 0 + .dw 0x67c0, 0xc93d, 0x67ff, 0xc93d, 0x21, 0 + .dw 0x6840, 0xc93d, 0x687f, 0xc93d, 0x21, 0 + .dw 0x68c0, 0xc93d, 0x68ff, 0xc93d, 0x21, 0 + .dw 0x6940, 0xc93d, 0x697f, 0xc93d, 0x21, 0 + .dw 0x69c0, 0xc93d, 0x69ff, 0xc93d, 0x21, 0 + .dw 0x6a40, 0xc93d, 0x6a7f, 0xc93d, 0x21, 0 + .dw 0x6ac0, 0xc93d, 0x6aff, 0xc93d, 0x21, 0 + .dw 0x6b40, 0xc93d, 0x6b7f, 0xc93d, 0x21, 0 + .dw 0x6bc0, 0xc93d, 0x6bff, 0xc93d, 0x21, 0 + .dw 0x6c40, 0xc93d, 0x6c7f, 0xc93d, 0x21, 0 + .dw 0x6cc0, 0xc93d, 0x6cff, 0xc93d, 0x21, 0 + .dw 0x6d40, 0xc93d, 0x6d7f, 0xc93d, 0x21, 0 + .dw 0x6dc0, 0xc93d, 0x6dff, 0xc93d, 0x21, 0 + .dw 0x6e40, 0xc93d, 0x6e7f, 0xc93d, 0x21, 0 + .dw 0x6ec0, 0xc93d, 0x6eff, 0xc93d, 0x21, 0 + .dw 0x6f40, 0xc93d, 0x6f7f, 0xc93d, 0x21, 0 + .dw 0x6fc0, 0xc93d, 0x6fff, 0xc93d, 0x21, 0 + .dw 0x7040, 0xc93d, 0x707f, 0xc93d, 0x21, 0 + .dw 0x70c0, 0xc93d, 0x70ff, 0xc93d, 0x21, 0 + .dw 0x7140, 0xc93d, 0x717f, 0xc93d, 0x21, 0 + .dw 0x71c0, 0xc93d, 0x71ff, 0xc93d, 0x21, 0 + .dw 0x7240, 0xc93d, 0x727f, 0xc93d, 0x21, 0 + .dw 0x72c0, 0xc93d, 0x72ff, 0xc93d, 0x21, 0 + .dw 0x7340, 0xc93d, 0x737f, 0xc93d, 0x21, 0 + .dw 0x73c0, 0xc93d, 0x73ff, 0xc93d, 0x21, 0 + .dw 0x7440, 0xc93d, 0x747f, 0xc93d, 0x21, 0 + .dw 0x74c0, 0xc93d, 0x74ff, 0xc93d, 0x21, 0 + .dw 0x7540, 0xc93d, 0x757f, 0xc93d, 0x21, 0 + .dw 0x75c0, 0xc93d, 0x75ff, 0xc93d, 0x21, 0 + .dw 0x7640, 0xc93d, 0x767f, 0xc93d, 0x21, 0 + .dw 0x76c0, 0xc93d, 0x76ff, 0xc93d, 0x21, 0 + .dw 0x7740, 0xc93d, 0x777f, 0xc93d, 0x21, 0 + .dw 0x77c0, 0xc93d, 0x77ff, 0xc93d, 0x21, 0 + .dw 0x7840, 0xc93d, 0x787f, 0xc93d, 0x21, 0 + .dw 0x78c0, 0xc93d, 0x78ff, 0xc93d, 0x21, 0 + .dw 0x7940, 0xc93d, 0x797f, 0xc93d, 0x21, 0 + .dw 0x79c0, 0xc93d, 0x7fff, 0xc93d, 0x21, 0 + .dw 0x8040, 0xc93d, 0x807f, 0xc93d, 0x21, 0 + .dw 0x80c0, 0xc93d, 0x80ff, 0xc93d, 0x21, 0 + .dw 0x8140, 0xc93d, 0x817f, 0xc93d, 0x21, 0 + .dw 0x81c0, 0xc93d, 0x81ff, 0xc93d, 0x21, 0 + .dw 0x8240, 0xc93d, 0x827f, 0xc93d, 0x21, 0 + .dw 0x82c0, 0xc93d, 0x82ff, 0xc93d, 0x21, 0 + .dw 0x8340, 0xc93d, 0x837f, 0xc93d, 0x21, 0 + .dw 0x83c0, 0xc93d, 0x83ff, 0xc93d, 0x21, 0 + .dw 0x8440, 0xc93d, 0x847f, 0xc93d, 0x21, 0 + .dw 0x84c0, 0xc93d, 0x84ff, 0xc93d, 0x21, 0 + .dw 0x8540, 0xc93d, 0x857f, 0xc93d, 0x21, 0 + .dw 0x85c0, 0xc93d, 0x85ff, 0xc93d, 0x21, 0 + .dw 0x8640, 0xc93d, 0x867f, 0xc93d, 0x21, 0 + .dw 0x86c0, 0xc93d, 0x86ff, 0xc93d, 0x21, 0 + .dw 0x8740, 0xc93d, 0x877f, 0xc93d, 0x21, 0 + .dw 0x87c0, 0xc93d, 0x87ff, 0xc93d, 0x21, 0 + .dw 0x8840, 0xc93d, 0x887f, 0xc93d, 0x21, 0 + .dw 0x88c0, 0xc93d, 0x88ff, 0xc93d, 0x21, 0 + .dw 0x8940, 0xc93d, 0x897f, 0xc93d, 0x21, 0 + .dw 0x89c0, 0xc93d, 0x89ff, 0xc93d, 0x21, 0 + .dw 0x8a40, 0xc93d, 0x8a7f, 0xc93d, 0x21, 0 + .dw 0x8ac0, 0xc93d, 0x8aff, 0xc93d, 0x21, 0 + .dw 0x8b40, 0xc93d, 0x8b7f, 0xc93d, 0x21, 0 + .dw 0x8bc0, 0xc93d, 0x8bff, 0xc93d, 0x21, 0 + .dw 0x8c40, 0xc93d, 0x8c7f, 0xc93d, 0x21, 0 + .dw 0x8cc0, 0xc93d, 0x8cff, 0xc93d, 0x21, 0 + .dw 0x8d40, 0xc93d, 0x8d7f, 0xc93d, 0x21, 0 + .dw 0x8dc0, 0xc93d, 0x8dff, 0xc93d, 0x21, 0 + .dw 0x8e40, 0xc93d, 0x8e7f, 0xc93d, 0x21, 0 + .dw 0x8ec0, 0xc93d, 0x8eff, 0xc93d, 0x21, 0 + .dw 0x8f40, 0xc93d, 0x8f7f, 0xc93d, 0x21, 0 + .dw 0x8fc0, 0xc93d, 0x8fff, 0xc93d, 0x21, 0 + .dw 0x9040, 0xc93d, 0x907f, 0xc93d, 0x21, 0 + .dw 0x90c0, 0xc93d, 0x90ff, 0xc93d, 0x21, 0 + .dw 0x9140, 0xc93d, 0x917f, 0xc93d, 0x21, 0 + .dw 0x91c0, 0xc93d, 0x91ff, 0xc93d, 0x21, 0 + .dw 0x9240, 0xc93d, 0x927f, 0xc93d, 0x21, 0 + .dw 0x92c0, 0xc93d, 0x92ff, 0xc93d, 0x21, 0 + .dw 0x9340, 0xc93d, 0x937f, 0xc93d, 0x21, 0 + .dw 0x93c0, 0xc93d, 0x93ff, 0xc93d, 0x21, 0 + .dw 0x9440, 0xc93d, 0x947f, 0xc93d, 0x21, 0 + .dw 0x94c0, 0xc93d, 0x94ff, 0xc93d, 0x21, 0 + .dw 0x9540, 0xc93d, 0x957f, 0xc93d, 0x21, 0 + .dw 0x95c0, 0xc93d, 0x95ff, 0xc93d, 0x21, 0 + .dw 0x9640, 0xc93d, 0x967f, 0xc93d, 0x21, 0 + .dw 0x96c0, 0xc93d, 0x96ff, 0xc93d, 0x21, 0 + .dw 0x9740, 0xc93d, 0x977f, 0xc93d, 0x21, 0 + .dw 0x97c0, 0xc93d, 0x97ff, 0xc93d, 0x21, 0 + .dw 0x9840, 0xc93d, 0x987f, 0xc93d, 0x21, 0 + .dw 0x98c0, 0xc93d, 0x98ff, 0xc93d, 0x21, 0 + .dw 0x9940, 0xc93d, 0x997f, 0xc93d, 0x21, 0 + .dw 0x99c0, 0xc93d, 0x9fff, 0xc93d, 0x21, 0 + .dw 0xa040, 0xc93d, 0xa07f, 0xc93d, 0x21, 0 + .dw 0xa0c0, 0xc93d, 0xa0ff, 0xc93d, 0x21, 0 + .dw 0xa140, 0xc93d, 0xa17f, 0xc93d, 0x21, 0 + .dw 0xa1c0, 0xc93d, 0xa1ff, 0xc93d, 0x21, 0 + .dw 0xa240, 0xc93d, 0xa27f, 0xc93d, 0x21, 0 + .dw 0xa2c0, 0xc93d, 0xa2ff, 0xc93d, 0x21, 0 + .dw 0xa340, 0xc93d, 0xa37f, 0xc93d, 0x21, 0 + .dw 0xa3c0, 0xc93d, 0xa3ff, 0xc93d, 0x21, 0 + .dw 0xa440, 0xc93d, 0xa47f, 0xc93d, 0x21, 0 + .dw 0xa4c0, 0xc93d, 0xa4ff, 0xc93d, 0x21, 0 + .dw 0xa540, 0xc93d, 0xa57f, 0xc93d, 0x21, 0 + .dw 0xa5c0, 0xc93d, 0xa5ff, 0xc93d, 0x21, 0 + .dw 0xa640, 0xc93d, 0xa67f, 0xc93d, 0x21, 0 + .dw 0xa6c0, 0xc93d, 0xa6ff, 0xc93d, 0x21, 0 + .dw 0xa740, 0xc93d, 0xa77f, 0xc93d, 0x21, 0 + .dw 0xa7c0, 0xc93d, 0xa7ff, 0xc93d, 0x21, 0 + .dw 0xa840, 0xc93d, 0xa87f, 0xc93d, 0x21, 0 + .dw 0xa8c0, 0xc93d, 0xa8ff, 0xc93d, 0x21, 0 + .dw 0xa940, 0xc93d, 0xa97f, 0xc93d, 0x21, 0 + .dw 0xa9c0, 0xc93d, 0xa9ff, 0xc93d, 0x21, 0 + .dw 0xaa40, 0xc93d, 0xaa7f, 0xc93d, 0x21, 0 + .dw 0xaac0, 0xc93d, 0xaaff, 0xc93d, 0x21, 0 + .dw 0xab40, 0xc93d, 0xab7f, 0xc93d, 0x21, 0 + .dw 0xabc0, 0xc93d, 0xabff, 0xc93d, 0x21, 0 + .dw 0xac40, 0xc93d, 0xac7f, 0xc93d, 0x21, 0 + .dw 0xacc0, 0xc93d, 0xacff, 0xc93d, 0x21, 0 + .dw 0xad40, 0xc93d, 0xad7f, 0xc93d, 0x21, 0 + .dw 0xadc0, 0xc93d, 0xadff, 0xc93d, 0x21, 0 + .dw 0xae40, 0xc93d, 0xae7f, 0xc93d, 0x21, 0 + .dw 0xaec0, 0xc93d, 0xaeff, 0xc93d, 0x21, 0 + .dw 0xaf40, 0xc93d, 0xaf7f, 0xc93d, 0x21, 0 + .dw 0xafc0, 0xc93d, 0xafff, 0xc93d, 0x21, 0 + .dw 0xb040, 0xc93d, 0xb07f, 0xc93d, 0x21, 0 + .dw 0xb0c0, 0xc93d, 0xb0ff, 0xc93d, 0x21, 0 + .dw 0xb140, 0xc93d, 0xb17f, 0xc93d, 0x21, 0 + .dw 0xb1c0, 0xc93d, 0xb1ff, 0xc93d, 0x21, 0 + .dw 0xb240, 0xc93d, 0xb27f, 0xc93d, 0x21, 0 + .dw 0xb2c0, 0xc93d, 0xb2ff, 0xc93d, 0x21, 0 + .dw 0xb340, 0xc93d, 0xb37f, 0xc93d, 0x21, 0 + .dw 0xb3c0, 0xc93d, 0xb3ff, 0xc93d, 0x21, 0 + .dw 0xb440, 0xc93d, 0xb47f, 0xc93d, 0x21, 0 + .dw 0xb4c0, 0xc93d, 0xb4ff, 0xc93d, 0x21, 0 + .dw 0xb540, 0xc93d, 0xb57f, 0xc93d, 0x21, 0 + .dw 0xb5c0, 0xc93d, 0xb5ff, 0xc93d, 0x21, 0 + .dw 0xb640, 0xc93d, 0xb67f, 0xc93d, 0x21, 0 + .dw 0xb6c0, 0xc93d, 0xb6ff, 0xc93d, 0x21, 0 + .dw 0xb740, 0xc93d, 0xb77f, 0xc93d, 0x21, 0 + .dw 0xb7c0, 0xc93d, 0xb7ff, 0xc93d, 0x21, 0 + .dw 0xb840, 0xc93d, 0xb87f, 0xc93d, 0x21, 0 + .dw 0xb8c0, 0xc93d, 0xb8ff, 0xc93d, 0x21, 0 + .dw 0xb940, 0xc93d, 0xb97f, 0xc93d, 0x21, 0 + .dw 0xb9c0, 0xc93d, 0xbfff, 0xc93d, 0x21, 0 + .dw 0xc040, 0xc93d, 0xc07f, 0xc93d, 0x21, 0 + .dw 0xc0c0, 0xc93d, 0xc0ff, 0xc93d, 0x21, 0 + .dw 0xc140, 0xc93d, 0xc17f, 0xc93d, 0x21, 0 + .dw 0xc1c0, 0xc93d, 0xc1ff, 0xc93d, 0x21, 0 + .dw 0xc240, 0xc93d, 0xc27f, 0xc93d, 0x21, 0 + .dw 0xc2c0, 0xc93d, 0xc2ff, 0xc93d, 0x21, 0 + .dw 0xc340, 0xc93d, 0xc37f, 0xc93d, 0x21, 0 + .dw 0xc3c0, 0xc93d, 0xc3ff, 0xc93d, 0x21, 0 + .dw 0xc440, 0xc93d, 0xc47f, 0xc93d, 0x21, 0 + .dw 0xc4c0, 0xc93d, 0xc4ff, 0xc93d, 0x21, 0 + .dw 0xc540, 0xc93d, 0xc57f, 0xc93d, 0x21, 0 + .dw 0xc5c0, 0xc93d, 0xc5ff, 0xc93d, 0x21, 0 + .dw 0xc640, 0xc93d, 0xc67f, 0xc93d, 0x21, 0 + .dw 0xc6c0, 0xc93d, 0xc6ff, 0xc93d, 0x21, 0 + .dw 0xc740, 0xc93d, 0xc77f, 0xc93d, 0x21, 0 + .dw 0xc7c0, 0xc93d, 0xc7ff, 0xc93d, 0x21, 0 + .dw 0xc840, 0xc93d, 0xc87f, 0xc93d, 0x21, 0 + .dw 0xc8c0, 0xc93d, 0xc8ff, 0xc93d, 0x21, 0 + .dw 0xc940, 0xc93d, 0xc97f, 0xc93d, 0x21, 0 + .dw 0xc9c0, 0xc93d, 0xc9ff, 0xc93d, 0x21, 0 + .dw 0xca40, 0xc93d, 0xca7f, 0xc93d, 0x21, 0 + .dw 0xcac0, 0xc93d, 0xcaff, 0xc93d, 0x21, 0 + .dw 0xcb40, 0xc93d, 0xcb7f, 0xc93d, 0x21, 0 + .dw 0xcbc0, 0xc93d, 0xcbff, 0xc93d, 0x21, 0 + .dw 0xcc40, 0xc93d, 0xcc7f, 0xc93d, 0x21, 0 + .dw 0xccc0, 0xc93d, 0xccff, 0xc93d, 0x21, 0 + .dw 0xcd40, 0xc93d, 0xcd7f, 0xc93d, 0x21, 0 + .dw 0xcdc0, 0xc93d, 0xcdff, 0xc93d, 0x21, 0 + .dw 0xce40, 0xc93d, 0xce7f, 0xc93d, 0x21, 0 + .dw 0xcec0, 0xc93d, 0xceff, 0xc93d, 0x21, 0 + .dw 0xcf40, 0xc93d, 0xcf7f, 0xc93d, 0x21, 0 + .dw 0xcfc0, 0xc93d, 0xcfff, 0xc93d, 0x21, 0 + .dw 0xd040, 0xc93d, 0xd07f, 0xc93d, 0x21, 0 + .dw 0xd0c0, 0xc93d, 0xd0ff, 0xc93d, 0x21, 0 + .dw 0xd140, 0xc93d, 0xd17f, 0xc93d, 0x21, 0 + .dw 0xd1c0, 0xc93d, 0xd1ff, 0xc93d, 0x21, 0 + .dw 0xd240, 0xc93d, 0xd27f, 0xc93d, 0x21, 0 + .dw 0xd2c0, 0xc93d, 0xd2ff, 0xc93d, 0x21, 0 + .dw 0xd340, 0xc93d, 0xd37f, 0xc93d, 0x21, 0 + .dw 0xd3c0, 0xc93d, 0xd3ff, 0xc93d, 0x21, 0 + .dw 0xd440, 0xc93d, 0xd47f, 0xc93d, 0x21, 0 + .dw 0xd4c0, 0xc93d, 0xd4ff, 0xc93d, 0x21, 0 + .dw 0xd540, 0xc93d, 0xd57f, 0xc93d, 0x21, 0 + .dw 0xd5c0, 0xc93d, 0xd5ff, 0xc93d, 0x21, 0 + .dw 0xd640, 0xc93d, 0xd67f, 0xc93d, 0x21, 0 + .dw 0xd6c0, 0xc93d, 0xd6ff, 0xc93d, 0x21, 0 + .dw 0xd740, 0xc93d, 0xd77f, 0xc93d, 0x21, 0 + .dw 0xd7c0, 0xc93d, 0xd7ff, 0xc93d, 0x21, 0 + .dw 0xd840, 0xc93d, 0xd87f, 0xc93d, 0x21, 0 + .dw 0xd8c0, 0xc93d, 0xd8ff, 0xc93d, 0x21, 0 + .dw 0xd940, 0xc93d, 0xd97f, 0xc93d, 0x21, 0 + .dw 0xd9c0, 0xc93d, 0xdfff, 0xc93d, 0x21, 0 + .dw 0xe040, 0xc93d, 0xe07f, 0xc93d, 0x21, 0 + .dw 0xe0c0, 0xc93d, 0xe0ff, 0xc93d, 0x21, 0 + .dw 0xe140, 0xc93d, 0xe17f, 0xc93d, 0x21, 0 + .dw 0xe1c0, 0xc93d, 0xe1ff, 0xc93d, 0x21, 0 + .dw 0xe240, 0xc93d, 0xe27f, 0xc93d, 0x21, 0 + .dw 0xe2c0, 0xc93d, 0xe2ff, 0xc93d, 0x21, 0 + .dw 0xe340, 0xc93d, 0xe37f, 0xc93d, 0x21, 0 + .dw 0xe3c0, 0xc93d, 0xe3ff, 0xc93d, 0x21, 0 + .dw 0xe440, 0xc93d, 0xe47f, 0xc93d, 0x21, 0 + .dw 0xe4c0, 0xc93d, 0xe4ff, 0xc93d, 0x21, 0 + .dw 0xe540, 0xc93d, 0xe57f, 0xc93d, 0x21, 0 + .dw 0xe5c0, 0xc93d, 0xe5ff, 0xc93d, 0x21, 0 + .dw 0xe640, 0xc93d, 0xe67f, 0xc93d, 0x21, 0 + .dw 0xe6c0, 0xc93d, 0xe6ff, 0xc93d, 0x21, 0 + .dw 0xe740, 0xc93d, 0xe77f, 0xc93d, 0x21, 0 + .dw 0xe7c0, 0xc93d, 0xe7ff, 0xc93d, 0x21, 0 + .dw 0xe840, 0xc93d, 0xe87f, 0xc93d, 0x21, 0 + .dw 0xe8c0, 0xc93d, 0xe8ff, 0xc93d, 0x21, 0 + .dw 0xe940, 0xc93d, 0xe97f, 0xc93d, 0x21, 0 + .dw 0xe9c0, 0xc93d, 0xe9ff, 0xc93d, 0x21, 0 + .dw 0xea40, 0xc93d, 0xea7f, 0xc93d, 0x21, 0 + .dw 0xeac0, 0xc93d, 0xeaff, 0xc93d, 0x21, 0 + .dw 0xeb40, 0xc93d, 0xeb7f, 0xc93d, 0x21, 0 + .dw 0xebc0, 0xc93d, 0xebff, 0xc93d, 0x21, 0 + .dw 0xec40, 0xc93d, 0xec7f, 0xc93d, 0x21, 0 + .dw 0xecc0, 0xc93d, 0xecff, 0xc93d, 0x21, 0 + .dw 0xed40, 0xc93d, 0xed7f, 0xc93d, 0x21, 0 + .dw 0xedc0, 0xc93d, 0xedff, 0xc93d, 0x21, 0 + .dw 0xee40, 0xc93d, 0xee7f, 0xc93d, 0x21, 0 + .dw 0xeec0, 0xc93d, 0xeeff, 0xc93d, 0x21, 0 + .dw 0xef40, 0xc93d, 0xef7f, 0xc93d, 0x21, 0 + .dw 0xefc0, 0xc93d, 0xefff, 0xc93d, 0x21, 0 + .dw 0xf040, 0xc93d, 0xf07f, 0xc93d, 0x21, 0 + .dw 0xf0c0, 0xc93d, 0xf0ff, 0xc93d, 0x21, 0 + .dw 0xf140, 0xc93d, 0xf17f, 0xc93d, 0x21, 0 + .dw 0xf1c0, 0xc93d, 0xf1ff, 0xc93d, 0x21, 0 + .dw 0xf240, 0xc93d, 0xf27f, 0xc93d, 0x21, 0 + .dw 0xf2c0, 0xc93d, 0xf2ff, 0xc93d, 0x21, 0 + .dw 0xf340, 0xc93d, 0xf37f, 0xc93d, 0x21, 0 + .dw 0xf3c0, 0xc93d, 0xf3ff, 0xc93d, 0x21, 0 + .dw 0xf440, 0xc93d, 0xf47f, 0xc93d, 0x21, 0 + .dw 0xf4c0, 0xc93d, 0xf4ff, 0xc93d, 0x21, 0 + .dw 0xf540, 0xc93d, 0xf57f, 0xc93d, 0x21, 0 + .dw 0xf5c0, 0xc93d, 0xf5ff, 0xc93d, 0x21, 0 + .dw 0xf640, 0xc93d, 0xf67f, 0xc93d, 0x21, 0 + .dw 0xf6c0, 0xc93d, 0xf6ff, 0xc93d, 0x21, 0 + .dw 0xf740, 0xc93d, 0xf77f, 0xc93d, 0x21, 0 + .dw 0xf7c0, 0xc93d, 0xf7ff, 0xc93d, 0x21, 0 + .dw 0xf840, 0xc93d, 0xf87f, 0xc93d, 0x21, 0 + .dw 0xf8c0, 0xc93d, 0xf8ff, 0xc93d, 0x21, 0 + .dw 0xf940, 0xc93d, 0xf97f, 0xc93d, 0x21, 0 + .dw 0xf9c0, 0xc93d, 0xffff, 0xc93d, 0x21, 0 + .dw 0x0040, 0xc93e, 0x007f, 0xc93e, 0x21, 0 + .dw 0x00c0, 0xc93e, 0x00ff, 0xc93e, 0x21, 0 + .dw 0x0140, 0xc93e, 0x017f, 0xc93e, 0x21, 0 + .dw 0x01c0, 0xc93e, 0x01ff, 0xc93e, 0x21, 0 + .dw 0x0240, 0xc93e, 0x027f, 0xc93e, 0x21, 0 + .dw 0x02c0, 0xc93e, 0x02ff, 0xc93e, 0x21, 0 + .dw 0x0340, 0xc93e, 0x037f, 0xc93e, 0x21, 0 + .dw 0x03c0, 0xc93e, 0x03ff, 0xc93e, 0x21, 0 + .dw 0x0440, 0xc93e, 0x047f, 0xc93e, 0x21, 0 + .dw 0x04c0, 0xc93e, 0x04ff, 0xc93e, 0x21, 0 + .dw 0x0540, 0xc93e, 0x057f, 0xc93e, 0x21, 0 + .dw 0x05c0, 0xc93e, 0x05ff, 0xc93e, 0x21, 0 + .dw 0x0640, 0xc93e, 0x067f, 0xc93e, 0x21, 0 + .dw 0x06c0, 0xc93e, 0x06ff, 0xc93e, 0x21, 0 + .dw 0x0740, 0xc93e, 0x077f, 0xc93e, 0x21, 0 + .dw 0x07c0, 0xc93e, 0x07ff, 0xc93e, 0x21, 0 + .dw 0x0840, 0xc93e, 0x087f, 0xc93e, 0x21, 0 + .dw 0x08c0, 0xc93e, 0x08ff, 0xc93e, 0x21, 0 + .dw 0x0940, 0xc93e, 0x097f, 0xc93e, 0x21, 0 + .dw 0x09c0, 0xc93e, 0x09ff, 0xc93e, 0x21, 0 + .dw 0x0a40, 0xc93e, 0x0a7f, 0xc93e, 0x21, 0 + .dw 0x0ac0, 0xc93e, 0x0aff, 0xc93e, 0x21, 0 + .dw 0x0b40, 0xc93e, 0x0b7f, 0xc93e, 0x21, 0 + .dw 0x0bc0, 0xc93e, 0x0bff, 0xc93e, 0x21, 0 + .dw 0x0c40, 0xc93e, 0x0c7f, 0xc93e, 0x21, 0 + .dw 0x0cc0, 0xc93e, 0x0cff, 0xc93e, 0x21, 0 + .dw 0x0d40, 0xc93e, 0x0d7f, 0xc93e, 0x21, 0 + .dw 0x0dc0, 0xc93e, 0x0dff, 0xc93e, 0x21, 0 + .dw 0x0e40, 0xc93e, 0x0e7f, 0xc93e, 0x21, 0 + .dw 0x0ec0, 0xc93e, 0x0eff, 0xc93e, 0x21, 0 + .dw 0x0f40, 0xc93e, 0x0f7f, 0xc93e, 0x21, 0 + .dw 0x0fc0, 0xc93e, 0x0fff, 0xc93e, 0x21, 0 + .dw 0x1040, 0xc93e, 0x107f, 0xc93e, 0x21, 0 + .dw 0x10c0, 0xc93e, 0x10ff, 0xc93e, 0x21, 0 + .dw 0x1140, 0xc93e, 0x117f, 0xc93e, 0x21, 0 + .dw 0x11c0, 0xc93e, 0x11ff, 0xc93e, 0x21, 0 + .dw 0x1240, 0xc93e, 0x127f, 0xc93e, 0x21, 0 + .dw 0x12c0, 0xc93e, 0x12ff, 0xc93e, 0x21, 0 + .dw 0x1340, 0xc93e, 0x137f, 0xc93e, 0x21, 0 + .dw 0x13c0, 0xc93e, 0x13ff, 0xc93e, 0x21, 0 + .dw 0x1440, 0xc93e, 0x147f, 0xc93e, 0x21, 0 + .dw 0x14c0, 0xc93e, 0x14ff, 0xc93e, 0x21, 0 + .dw 0x1540, 0xc93e, 0x157f, 0xc93e, 0x21, 0 + .dw 0x15c0, 0xc93e, 0x15ff, 0xc93e, 0x21, 0 + .dw 0x1640, 0xc93e, 0x167f, 0xc93e, 0x21, 0 + .dw 0x16c0, 0xc93e, 0x16ff, 0xc93e, 0x21, 0 + .dw 0x1740, 0xc93e, 0x177f, 0xc93e, 0x21, 0 + .dw 0x17c0, 0xc93e, 0x17ff, 0xc93e, 0x21, 0 + .dw 0x1840, 0xc93e, 0x187f, 0xc93e, 0x21, 0 + .dw 0x18c0, 0xc93e, 0x18ff, 0xc93e, 0x21, 0 + .dw 0x1940, 0xc93e, 0x197f, 0xc93e, 0x21, 0 + .dw 0x19c0, 0xc93e, 0x1fff, 0xc93e, 0x21, 0 + .dw 0x2040, 0xc93e, 0x207f, 0xc93e, 0x21, 0 + .dw 0x20c0, 0xc93e, 0x20ff, 0xc93e, 0x21, 0 + .dw 0x2140, 0xc93e, 0x217f, 0xc93e, 0x21, 0 + .dw 0x21c0, 0xc93e, 0x21ff, 0xc93e, 0x21, 0 + .dw 0x2240, 0xc93e, 0x227f, 0xc93e, 0x21, 0 + .dw 0x22c0, 0xc93e, 0x22ff, 0xc93e, 0x21, 0 + .dw 0x2340, 0xc93e, 0x237f, 0xc93e, 0x21, 0 + .dw 0x23c0, 0xc93e, 0x23ff, 0xc93e, 0x21, 0 + .dw 0x2440, 0xc93e, 0x247f, 0xc93e, 0x21, 0 + .dw 0x24c0, 0xc93e, 0x24ff, 0xc93e, 0x21, 0 + .dw 0x2540, 0xc93e, 0x257f, 0xc93e, 0x21, 0 + .dw 0x25c0, 0xc93e, 0x25ff, 0xc93e, 0x21, 0 + .dw 0x2640, 0xc93e, 0x267f, 0xc93e, 0x21, 0 + .dw 0x26c0, 0xc93e, 0x26ff, 0xc93e, 0x21, 0 + .dw 0x2740, 0xc93e, 0x277f, 0xc93e, 0x21, 0 + .dw 0x27c0, 0xc93e, 0x27ff, 0xc93e, 0x21, 0 + .dw 0x2840, 0xc93e, 0x287f, 0xc93e, 0x21, 0 + .dw 0x28c0, 0xc93e, 0x28ff, 0xc93e, 0x21, 0 + .dw 0x2940, 0xc93e, 0x297f, 0xc93e, 0x21, 0 + .dw 0x29c0, 0xc93e, 0x29ff, 0xc93e, 0x21, 0 + .dw 0x2a40, 0xc93e, 0x2a7f, 0xc93e, 0x21, 0 + .dw 0x2ac0, 0xc93e, 0x2aff, 0xc93e, 0x21, 0 + .dw 0x2b40, 0xc93e, 0x2b7f, 0xc93e, 0x21, 0 + .dw 0x2bc0, 0xc93e, 0x2bff, 0xc93e, 0x21, 0 + .dw 0x2c40, 0xc93e, 0x2c7f, 0xc93e, 0x21, 0 + .dw 0x2cc0, 0xc93e, 0x2cff, 0xc93e, 0x21, 0 + .dw 0x2d40, 0xc93e, 0x2d7f, 0xc93e, 0x21, 0 + .dw 0x2dc0, 0xc93e, 0x2dff, 0xc93e, 0x21, 0 + .dw 0x2e40, 0xc93e, 0x2e7f, 0xc93e, 0x21, 0 + .dw 0x2ec0, 0xc93e, 0x2eff, 0xc93e, 0x21, 0 + .dw 0x2f40, 0xc93e, 0x2f7f, 0xc93e, 0x21, 0 + .dw 0x2fc0, 0xc93e, 0x2fff, 0xc93e, 0x21, 0 + .dw 0x3040, 0xc93e, 0x307f, 0xc93e, 0x21, 0 + .dw 0x30c0, 0xc93e, 0x30ff, 0xc93e, 0x21, 0 + .dw 0x3140, 0xc93e, 0x317f, 0xc93e, 0x21, 0 + .dw 0x31c0, 0xc93e, 0x31ff, 0xc93e, 0x21, 0 + .dw 0x3240, 0xc93e, 0x327f, 0xc93e, 0x21, 0 + .dw 0x32c0, 0xc93e, 0x32ff, 0xc93e, 0x21, 0 + .dw 0x3340, 0xc93e, 0x337f, 0xc93e, 0x21, 0 + .dw 0x33c0, 0xc93e, 0x33ff, 0xc93e, 0x21, 0 + .dw 0x3440, 0xc93e, 0x347f, 0xc93e, 0x21, 0 + .dw 0x34c0, 0xc93e, 0x34ff, 0xc93e, 0x21, 0 + .dw 0x3540, 0xc93e, 0x357f, 0xc93e, 0x21, 0 + .dw 0x35c0, 0xc93e, 0x35ff, 0xc93e, 0x21, 0 + .dw 0x3640, 0xc93e, 0x367f, 0xc93e, 0x21, 0 + .dw 0x36c0, 0xc93e, 0x36ff, 0xc93e, 0x21, 0 + .dw 0x3740, 0xc93e, 0x377f, 0xc93e, 0x21, 0 + .dw 0x37c0, 0xc93e, 0x37ff, 0xc93e, 0x21, 0 + .dw 0x3840, 0xc93e, 0x387f, 0xc93e, 0x21, 0 + .dw 0x38c0, 0xc93e, 0x38ff, 0xc93e, 0x21, 0 + .dw 0x3940, 0xc93e, 0x397f, 0xc93e, 0x21, 0 + .dw 0x39c0, 0xc93e, 0x3fff, 0xc93e, 0x21, 0 + .dw 0x4040, 0xc93e, 0x407f, 0xc93e, 0x21, 0 + .dw 0x40c0, 0xc93e, 0x40ff, 0xc93e, 0x21, 0 + .dw 0x4140, 0xc93e, 0x417f, 0xc93e, 0x21, 0 + .dw 0x41c0, 0xc93e, 0x41ff, 0xc93e, 0x21, 0 + .dw 0x4240, 0xc93e, 0x427f, 0xc93e, 0x21, 0 + .dw 0x42c0, 0xc93e, 0x42ff, 0xc93e, 0x21, 0 + .dw 0x4340, 0xc93e, 0x437f, 0xc93e, 0x21, 0 + .dw 0x43c0, 0xc93e, 0x43ff, 0xc93e, 0x21, 0 + .dw 0x4440, 0xc93e, 0x447f, 0xc93e, 0x21, 0 + .dw 0x44c0, 0xc93e, 0x44ff, 0xc93e, 0x21, 0 + .dw 0x4540, 0xc93e, 0x457f, 0xc93e, 0x21, 0 + .dw 0x45c0, 0xc93e, 0x45ff, 0xc93e, 0x21, 0 + .dw 0x4640, 0xc93e, 0x467f, 0xc93e, 0x21, 0 + .dw 0x46c0, 0xc93e, 0x46ff, 0xc93e, 0x21, 0 + .dw 0x4740, 0xc93e, 0x477f, 0xc93e, 0x21, 0 + .dw 0x47c0, 0xc93e, 0x47ff, 0xc93e, 0x21, 0 + .dw 0x4840, 0xc93e, 0x487f, 0xc93e, 0x21, 0 + .dw 0x48c0, 0xc93e, 0x48ff, 0xc93e, 0x21, 0 + .dw 0x4940, 0xc93e, 0x497f, 0xc93e, 0x21, 0 + .dw 0x49c0, 0xc93e, 0x49ff, 0xc93e, 0x21, 0 + .dw 0x4a40, 0xc93e, 0x4a7f, 0xc93e, 0x21, 0 + .dw 0x4ac0, 0xc93e, 0x4aff, 0xc93e, 0x21, 0 + .dw 0x4b40, 0xc93e, 0x4b7f, 0xc93e, 0x21, 0 + .dw 0x4bc0, 0xc93e, 0x4bff, 0xc93e, 0x21, 0 + .dw 0x4c40, 0xc93e, 0x4c7f, 0xc93e, 0x21, 0 + .dw 0x4cc0, 0xc93e, 0x4cff, 0xc93e, 0x21, 0 + .dw 0x4d40, 0xc93e, 0x4d7f, 0xc93e, 0x21, 0 + .dw 0x4dc0, 0xc93e, 0x4dff, 0xc93e, 0x21, 0 + .dw 0x4e40, 0xc93e, 0x4e7f, 0xc93e, 0x21, 0 + .dw 0x4ec0, 0xc93e, 0x4eff, 0xc93e, 0x21, 0 + .dw 0x4f40, 0xc93e, 0x4f7f, 0xc93e, 0x21, 0 + .dw 0x4fc0, 0xc93e, 0x4fff, 0xc93e, 0x21, 0 + .dw 0x5040, 0xc93e, 0x507f, 0xc93e, 0x21, 0 + .dw 0x50c0, 0xc93e, 0x50ff, 0xc93e, 0x21, 0 + .dw 0x5140, 0xc93e, 0x517f, 0xc93e, 0x21, 0 + .dw 0x51c0, 0xc93e, 0x51ff, 0xc93e, 0x21, 0 + .dw 0x5240, 0xc93e, 0x527f, 0xc93e, 0x21, 0 + .dw 0x52c0, 0xc93e, 0x52ff, 0xc93e, 0x21, 0 + .dw 0x5340, 0xc93e, 0x537f, 0xc93e, 0x21, 0 + .dw 0x53c0, 0xc93e, 0x53ff, 0xc93e, 0x21, 0 + .dw 0x5440, 0xc93e, 0x547f, 0xc93e, 0x21, 0 + .dw 0x54c0, 0xc93e, 0x54ff, 0xc93e, 0x21, 0 + .dw 0x5540, 0xc93e, 0x557f, 0xc93e, 0x21, 0 + .dw 0x55c0, 0xc93e, 0x55ff, 0xc93e, 0x21, 0 + .dw 0x5640, 0xc93e, 0x567f, 0xc93e, 0x21, 0 + .dw 0x56c0, 0xc93e, 0x56ff, 0xc93e, 0x21, 0 + .dw 0x5740, 0xc93e, 0x577f, 0xc93e, 0x21, 0 + .dw 0x57c0, 0xc93e, 0x57ff, 0xc93e, 0x21, 0 + .dw 0x5840, 0xc93e, 0x587f, 0xc93e, 0x21, 0 + .dw 0x58c0, 0xc93e, 0x58ff, 0xc93e, 0x21, 0 + .dw 0x5940, 0xc93e, 0x597f, 0xc93e, 0x21, 0 + .dw 0x59c0, 0xc93e, 0x5fff, 0xc93e, 0x21, 0 + .dw 0x6040, 0xc93e, 0x607f, 0xc93e, 0x21, 0 + .dw 0x60c0, 0xc93e, 0x60ff, 0xc93e, 0x21, 0 + .dw 0x6140, 0xc93e, 0x617f, 0xc93e, 0x21, 0 + .dw 0x61c0, 0xc93e, 0x61ff, 0xc93e, 0x21, 0 + .dw 0x6240, 0xc93e, 0x627f, 0xc93e, 0x21, 0 + .dw 0x62c0, 0xc93e, 0x62ff, 0xc93e, 0x21, 0 + .dw 0x6340, 0xc93e, 0x637f, 0xc93e, 0x21, 0 + .dw 0x63c0, 0xc93e, 0x63ff, 0xc93e, 0x21, 0 + .dw 0x6440, 0xc93e, 0x647f, 0xc93e, 0x21, 0 + .dw 0x64c0, 0xc93e, 0x64ff, 0xc93e, 0x21, 0 + .dw 0x6540, 0xc93e, 0x657f, 0xc93e, 0x21, 0 + .dw 0x65c0, 0xc93e, 0x65ff, 0xc93e, 0x21, 0 + .dw 0x6640, 0xc93e, 0x667f, 0xc93e, 0x21, 0 + .dw 0x66c0, 0xc93e, 0x66ff, 0xc93e, 0x21, 0 + .dw 0x6740, 0xc93e, 0x677f, 0xc93e, 0x21, 0 + .dw 0x67c0, 0xc93e, 0x67ff, 0xc93e, 0x21, 0 + .dw 0x6840, 0xc93e, 0x687f, 0xc93e, 0x21, 0 + .dw 0x68c0, 0xc93e, 0x68ff, 0xc93e, 0x21, 0 + .dw 0x6940, 0xc93e, 0x697f, 0xc93e, 0x21, 0 + .dw 0x69c0, 0xc93e, 0x69ff, 0xc93e, 0x21, 0 + .dw 0x6a40, 0xc93e, 0x6a7f, 0xc93e, 0x21, 0 + .dw 0x6ac0, 0xc93e, 0x6aff, 0xc93e, 0x21, 0 + .dw 0x6b40, 0xc93e, 0x6b7f, 0xc93e, 0x21, 0 + .dw 0x6bc0, 0xc93e, 0x6bff, 0xc93e, 0x21, 0 + .dw 0x6c40, 0xc93e, 0x6c7f, 0xc93e, 0x21, 0 + .dw 0x6cc0, 0xc93e, 0x6cff, 0xc93e, 0x21, 0 + .dw 0x6d40, 0xc93e, 0x6d7f, 0xc93e, 0x21, 0 + .dw 0x6dc0, 0xc93e, 0x6dff, 0xc93e, 0x21, 0 + .dw 0x6e40, 0xc93e, 0x6e7f, 0xc93e, 0x21, 0 + .dw 0x6ec0, 0xc93e, 0x6eff, 0xc93e, 0x21, 0 + .dw 0x6f40, 0xc93e, 0x6f7f, 0xc93e, 0x21, 0 + .dw 0x6fc0, 0xc93e, 0x6fff, 0xc93e, 0x21, 0 + .dw 0x7040, 0xc93e, 0x707f, 0xc93e, 0x21, 0 + .dw 0x70c0, 0xc93e, 0x70ff, 0xc93e, 0x21, 0 + .dw 0x7140, 0xc93e, 0x717f, 0xc93e, 0x21, 0 + .dw 0x71c0, 0xc93e, 0x71ff, 0xc93e, 0x21, 0 + .dw 0x7240, 0xc93e, 0x727f, 0xc93e, 0x21, 0 + .dw 0x72c0, 0xc93e, 0x72ff, 0xc93e, 0x21, 0 + .dw 0x7340, 0xc93e, 0x737f, 0xc93e, 0x21, 0 + .dw 0x73c0, 0xc93e, 0x73ff, 0xc93e, 0x21, 0 + .dw 0x7440, 0xc93e, 0x747f, 0xc93e, 0x21, 0 + .dw 0x74c0, 0xc93e, 0x74ff, 0xc93e, 0x21, 0 + .dw 0x7540, 0xc93e, 0x757f, 0xc93e, 0x21, 0 + .dw 0x75c0, 0xc93e, 0x75ff, 0xc93e, 0x21, 0 + .dw 0x7640, 0xc93e, 0x767f, 0xc93e, 0x21, 0 + .dw 0x76c0, 0xc93e, 0x76ff, 0xc93e, 0x21, 0 + .dw 0x7740, 0xc93e, 0x777f, 0xc93e, 0x21, 0 + .dw 0x77c0, 0xc93e, 0x77ff, 0xc93e, 0x21, 0 + .dw 0x7840, 0xc93e, 0x787f, 0xc93e, 0x21, 0 + .dw 0x78c0, 0xc93e, 0x78ff, 0xc93e, 0x21, 0 + .dw 0x7940, 0xc93e, 0x797f, 0xc93e, 0x21, 0 + .dw 0x79c0, 0xc93e, 0x7fff, 0xc93e, 0x21, 0 + .dw 0x8040, 0xc93e, 0x807f, 0xc93e, 0x21, 0 + .dw 0x80c0, 0xc93e, 0x80ff, 0xc93e, 0x21, 0 + .dw 0x8140, 0xc93e, 0x817f, 0xc93e, 0x21, 0 + .dw 0x81c0, 0xc93e, 0x81ff, 0xc93e, 0x21, 0 + .dw 0x8240, 0xc93e, 0x827f, 0xc93e, 0x21, 0 + .dw 0x82c0, 0xc93e, 0x82ff, 0xc93e, 0x21, 0 + .dw 0x8340, 0xc93e, 0x837f, 0xc93e, 0x21, 0 + .dw 0x83c0, 0xc93e, 0x83ff, 0xc93e, 0x21, 0 + .dw 0x8440, 0xc93e, 0x847f, 0xc93e, 0x21, 0 + .dw 0x84c0, 0xc93e, 0x84ff, 0xc93e, 0x21, 0 + .dw 0x8540, 0xc93e, 0x857f, 0xc93e, 0x21, 0 + .dw 0x85c0, 0xc93e, 0x85ff, 0xc93e, 0x21, 0 + .dw 0x8640, 0xc93e, 0x867f, 0xc93e, 0x21, 0 + .dw 0x86c0, 0xc93e, 0x86ff, 0xc93e, 0x21, 0 + .dw 0x8740, 0xc93e, 0x877f, 0xc93e, 0x21, 0 + .dw 0x87c0, 0xc93e, 0x87ff, 0xc93e, 0x21, 0 + .dw 0x8840, 0xc93e, 0x887f, 0xc93e, 0x21, 0 + .dw 0x88c0, 0xc93e, 0x88ff, 0xc93e, 0x21, 0 + .dw 0x8940, 0xc93e, 0x897f, 0xc93e, 0x21, 0 + .dw 0x89c0, 0xc93e, 0x89ff, 0xc93e, 0x21, 0 + .dw 0x8a40, 0xc93e, 0x8a7f, 0xc93e, 0x21, 0 + .dw 0x8ac0, 0xc93e, 0x8aff, 0xc93e, 0x21, 0 + .dw 0x8b40, 0xc93e, 0x8b7f, 0xc93e, 0x21, 0 + .dw 0x8bc0, 0xc93e, 0x8bff, 0xc93e, 0x21, 0 + .dw 0x8c40, 0xc93e, 0x8c7f, 0xc93e, 0x21, 0 + .dw 0x8cc0, 0xc93e, 0x8cff, 0xc93e, 0x21, 0 + .dw 0x8d40, 0xc93e, 0x8d7f, 0xc93e, 0x21, 0 + .dw 0x8dc0, 0xc93e, 0x8dff, 0xc93e, 0x21, 0 + .dw 0x8e40, 0xc93e, 0x8e7f, 0xc93e, 0x21, 0 + .dw 0x8ec0, 0xc93e, 0x8eff, 0xc93e, 0x21, 0 + .dw 0x8f40, 0xc93e, 0x8f7f, 0xc93e, 0x21, 0 + .dw 0x8fc0, 0xc93e, 0x8fff, 0xc93e, 0x21, 0 + .dw 0x9040, 0xc93e, 0x907f, 0xc93e, 0x21, 0 + .dw 0x90c0, 0xc93e, 0x90ff, 0xc93e, 0x21, 0 + .dw 0x9140, 0xc93e, 0x917f, 0xc93e, 0x21, 0 + .dw 0x91c0, 0xc93e, 0x91ff, 0xc93e, 0x21, 0 + .dw 0x9240, 0xc93e, 0x927f, 0xc93e, 0x21, 0 + .dw 0x92c0, 0xc93e, 0x92ff, 0xc93e, 0x21, 0 + .dw 0x9340, 0xc93e, 0x937f, 0xc93e, 0x21, 0 + .dw 0x93c0, 0xc93e, 0x93ff, 0xc93e, 0x21, 0 + .dw 0x9440, 0xc93e, 0x947f, 0xc93e, 0x21, 0 + .dw 0x94c0, 0xc93e, 0x94ff, 0xc93e, 0x21, 0 + .dw 0x9540, 0xc93e, 0x957f, 0xc93e, 0x21, 0 + .dw 0x95c0, 0xc93e, 0x95ff, 0xc93e, 0x21, 0 + .dw 0x9640, 0xc93e, 0x967f, 0xc93e, 0x21, 0 + .dw 0x96c0, 0xc93e, 0x96ff, 0xc93e, 0x21, 0 + .dw 0x9740, 0xc93e, 0x977f, 0xc93e, 0x21, 0 + .dw 0x97c0, 0xc93e, 0x97ff, 0xc93e, 0x21, 0 + .dw 0x9840, 0xc93e, 0x987f, 0xc93e, 0x21, 0 + .dw 0x98c0, 0xc93e, 0x98ff, 0xc93e, 0x21, 0 + .dw 0x9940, 0xc93e, 0x997f, 0xc93e, 0x21, 0 + .dw 0x99c0, 0xc93e, 0x9fff, 0xc93e, 0x21, 0 + .dw 0xa040, 0xc93e, 0xa07f, 0xc93e, 0x21, 0 + .dw 0xa0c0, 0xc93e, 0xa0ff, 0xc93e, 0x21, 0 + .dw 0xa140, 0xc93e, 0xa17f, 0xc93e, 0x21, 0 + .dw 0xa1c0, 0xc93e, 0xa1ff, 0xc93e, 0x21, 0 + .dw 0xa240, 0xc93e, 0xa27f, 0xc93e, 0x21, 0 + .dw 0xa2c0, 0xc93e, 0xa2ff, 0xc93e, 0x21, 0 + .dw 0xa340, 0xc93e, 0xa37f, 0xc93e, 0x21, 0 + .dw 0xa3c0, 0xc93e, 0xa3ff, 0xc93e, 0x21, 0 + .dw 0xa440, 0xc93e, 0xa47f, 0xc93e, 0x21, 0 + .dw 0xa4c0, 0xc93e, 0xa4ff, 0xc93e, 0x21, 0 + .dw 0xa540, 0xc93e, 0xa57f, 0xc93e, 0x21, 0 + .dw 0xa5c0, 0xc93e, 0xa5ff, 0xc93e, 0x21, 0 + .dw 0xa640, 0xc93e, 0xa67f, 0xc93e, 0x21, 0 + .dw 0xa6c0, 0xc93e, 0xa6ff, 0xc93e, 0x21, 0 + .dw 0xa740, 0xc93e, 0xa77f, 0xc93e, 0x21, 0 + .dw 0xa7c0, 0xc93e, 0xa7ff, 0xc93e, 0x21, 0 + .dw 0xa840, 0xc93e, 0xa87f, 0xc93e, 0x21, 0 + .dw 0xa8c0, 0xc93e, 0xa8ff, 0xc93e, 0x21, 0 + .dw 0xa940, 0xc93e, 0xa97f, 0xc93e, 0x21, 0 + .dw 0xa9c0, 0xc93e, 0xa9ff, 0xc93e, 0x21, 0 + .dw 0xaa40, 0xc93e, 0xaa7f, 0xc93e, 0x21, 0 + .dw 0xaac0, 0xc93e, 0xaaff, 0xc93e, 0x21, 0 + .dw 0xab40, 0xc93e, 0xab7f, 0xc93e, 0x21, 0 + .dw 0xabc0, 0xc93e, 0xabff, 0xc93e, 0x21, 0 + .dw 0xac40, 0xc93e, 0xac7f, 0xc93e, 0x21, 0 + .dw 0xacc0, 0xc93e, 0xacff, 0xc93e, 0x21, 0 + .dw 0xad40, 0xc93e, 0xad7f, 0xc93e, 0x21, 0 + .dw 0xadc0, 0xc93e, 0xadff, 0xc93e, 0x21, 0 + .dw 0xae40, 0xc93e, 0xae7f, 0xc93e, 0x21, 0 + .dw 0xaec0, 0xc93e, 0xaeff, 0xc93e, 0x21, 0 + .dw 0xaf40, 0xc93e, 0xaf7f, 0xc93e, 0x21, 0 + .dw 0xafc0, 0xc93e, 0xafff, 0xc93e, 0x21, 0 + .dw 0xb040, 0xc93e, 0xb07f, 0xc93e, 0x21, 0 + .dw 0xb0c0, 0xc93e, 0xb0ff, 0xc93e, 0x21, 0 + .dw 0xb140, 0xc93e, 0xb17f, 0xc93e, 0x21, 0 + .dw 0xb1c0, 0xc93e, 0xb1ff, 0xc93e, 0x21, 0 + .dw 0xb240, 0xc93e, 0xb27f, 0xc93e, 0x21, 0 + .dw 0xb2c0, 0xc93e, 0xb2ff, 0xc93e, 0x21, 0 + .dw 0xb340, 0xc93e, 0xb37f, 0xc93e, 0x21, 0 + .dw 0xb3c0, 0xc93e, 0xb3ff, 0xc93e, 0x21, 0 + .dw 0xb440, 0xc93e, 0xb47f, 0xc93e, 0x21, 0 + .dw 0xb4c0, 0xc93e, 0xb4ff, 0xc93e, 0x21, 0 + .dw 0xb540, 0xc93e, 0xb57f, 0xc93e, 0x21, 0 + .dw 0xb5c0, 0xc93e, 0xb5ff, 0xc93e, 0x21, 0 + .dw 0xb640, 0xc93e, 0xb67f, 0xc93e, 0x21, 0 + .dw 0xb6c0, 0xc93e, 0xb6ff, 0xc93e, 0x21, 0 + .dw 0xb740, 0xc93e, 0xb77f, 0xc93e, 0x21, 0 + .dw 0xb7c0, 0xc93e, 0xb7ff, 0xc93e, 0x21, 0 + .dw 0xb840, 0xc93e, 0xb87f, 0xc93e, 0x21, 0 + .dw 0xb8c0, 0xc93e, 0xb8ff, 0xc93e, 0x21, 0 + .dw 0xb940, 0xc93e, 0xb97f, 0xc93e, 0x21, 0 + .dw 0xb9c0, 0xc93e, 0xbfff, 0xc93e, 0x21, 0 + .dw 0xc040, 0xc93e, 0xc07f, 0xc93e, 0x21, 0 + .dw 0xc0c0, 0xc93e, 0xc0ff, 0xc93e, 0x21, 0 + .dw 0xc140, 0xc93e, 0xc17f, 0xc93e, 0x21, 0 + .dw 0xc1c0, 0xc93e, 0xc1ff, 0xc93e, 0x21, 0 + .dw 0xc240, 0xc93e, 0xc27f, 0xc93e, 0x21, 0 + .dw 0xc2c0, 0xc93e, 0xc2ff, 0xc93e, 0x21, 0 + .dw 0xc340, 0xc93e, 0xc37f, 0xc93e, 0x21, 0 + .dw 0xc3c0, 0xc93e, 0xc3ff, 0xc93e, 0x21, 0 + .dw 0xc440, 0xc93e, 0xc47f, 0xc93e, 0x21, 0 + .dw 0xc4c0, 0xc93e, 0xc4ff, 0xc93e, 0x21, 0 + .dw 0xc540, 0xc93e, 0xc57f, 0xc93e, 0x21, 0 + .dw 0xc5c0, 0xc93e, 0xc5ff, 0xc93e, 0x21, 0 + .dw 0xc640, 0xc93e, 0xc67f, 0xc93e, 0x21, 0 + .dw 0xc6c0, 0xc93e, 0xc6ff, 0xc93e, 0x21, 0 + .dw 0xc740, 0xc93e, 0xc77f, 0xc93e, 0x21, 0 + .dw 0xc7c0, 0xc93e, 0xc7ff, 0xc93e, 0x21, 0 + .dw 0xc840, 0xc93e, 0xc87f, 0xc93e, 0x21, 0 + .dw 0xc8c0, 0xc93e, 0xc8ff, 0xc93e, 0x21, 0 + .dw 0xc940, 0xc93e, 0xc97f, 0xc93e, 0x21, 0 + .dw 0xc9c0, 0xc93e, 0xc9ff, 0xc93e, 0x21, 0 + .dw 0xca40, 0xc93e, 0xca7f, 0xc93e, 0x21, 0 + .dw 0xcac0, 0xc93e, 0xcaff, 0xc93e, 0x21, 0 + .dw 0xcb40, 0xc93e, 0xcb7f, 0xc93e, 0x21, 0 + .dw 0xcbc0, 0xc93e, 0xcbff, 0xc93e, 0x21, 0 + .dw 0xcc40, 0xc93e, 0xcc7f, 0xc93e, 0x21, 0 + .dw 0xccc0, 0xc93e, 0xccff, 0xc93e, 0x21, 0 + .dw 0xcd40, 0xc93e, 0xcd7f, 0xc93e, 0x21, 0 + .dw 0xcdc0, 0xc93e, 0xcdff, 0xc93e, 0x21, 0 + .dw 0xce40, 0xc93e, 0xce7f, 0xc93e, 0x21, 0 + .dw 0xcec0, 0xc93e, 0xceff, 0xc93e, 0x21, 0 + .dw 0xcf40, 0xc93e, 0xcf7f, 0xc93e, 0x21, 0 + .dw 0xcfc0, 0xc93e, 0xcfff, 0xc93e, 0x21, 0 + .dw 0xd040, 0xc93e, 0xd07f, 0xc93e, 0x21, 0 + .dw 0xd0c0, 0xc93e, 0xd0ff, 0xc93e, 0x21, 0 + .dw 0xd140, 0xc93e, 0xd17f, 0xc93e, 0x21, 0 + .dw 0xd1c0, 0xc93e, 0xd1ff, 0xc93e, 0x21, 0 + .dw 0xd240, 0xc93e, 0xd27f, 0xc93e, 0x21, 0 + .dw 0xd2c0, 0xc93e, 0xd2ff, 0xc93e, 0x21, 0 + .dw 0xd340, 0xc93e, 0xd37f, 0xc93e, 0x21, 0 + .dw 0xd3c0, 0xc93e, 0xd3ff, 0xc93e, 0x21, 0 + .dw 0xd440, 0xc93e, 0xd47f, 0xc93e, 0x21, 0 + .dw 0xd4c0, 0xc93e, 0xd4ff, 0xc93e, 0x21, 0 + .dw 0xd540, 0xc93e, 0xd57f, 0xc93e, 0x21, 0 + .dw 0xd5c0, 0xc93e, 0xd5ff, 0xc93e, 0x21, 0 + .dw 0xd640, 0xc93e, 0xd67f, 0xc93e, 0x21, 0 + .dw 0xd6c0, 0xc93e, 0xd6ff, 0xc93e, 0x21, 0 + .dw 0xd740, 0xc93e, 0xd77f, 0xc93e, 0x21, 0 + .dw 0xd7c0, 0xc93e, 0xd7ff, 0xc93e, 0x21, 0 + .dw 0xd840, 0xc93e, 0xd87f, 0xc93e, 0x21, 0 + .dw 0xd8c0, 0xc93e, 0xd8ff, 0xc93e, 0x21, 0 + .dw 0xd940, 0xc93e, 0xd97f, 0xc93e, 0x21, 0 + .dw 0xd9c0, 0xc93e, 0xdfff, 0xc93e, 0x21, 0 + .dw 0xe040, 0xc93e, 0xe07f, 0xc93e, 0x21, 0 + .dw 0xe0c0, 0xc93e, 0xe0ff, 0xc93e, 0x21, 0 + .dw 0xe140, 0xc93e, 0xe17f, 0xc93e, 0x21, 0 + .dw 0xe1c0, 0xc93e, 0xe1ff, 0xc93e, 0x21, 0 + .dw 0xe240, 0xc93e, 0xe27f, 0xc93e, 0x21, 0 + .dw 0xe2c0, 0xc93e, 0xe2ff, 0xc93e, 0x21, 0 + .dw 0xe340, 0xc93e, 0xe37f, 0xc93e, 0x21, 0 + .dw 0xe3c0, 0xc93e, 0xe3ff, 0xc93e, 0x21, 0 + .dw 0xe440, 0xc93e, 0xe47f, 0xc93e, 0x21, 0 + .dw 0xe4c0, 0xc93e, 0xe4ff, 0xc93e, 0x21, 0 + .dw 0xe540, 0xc93e, 0xe57f, 0xc93e, 0x21, 0 + .dw 0xe5c0, 0xc93e, 0xe5ff, 0xc93e, 0x21, 0 + .dw 0xe640, 0xc93e, 0xe67f, 0xc93e, 0x21, 0 + .dw 0xe6c0, 0xc93e, 0xe6ff, 0xc93e, 0x21, 0 + .dw 0xe740, 0xc93e, 0xe77f, 0xc93e, 0x21, 0 + .dw 0xe7c0, 0xc93e, 0xe7ff, 0xc93e, 0x21, 0 + .dw 0xe840, 0xc93e, 0xe87f, 0xc93e, 0x21, 0 + .dw 0xe8c0, 0xc93e, 0xe8ff, 0xc93e, 0x21, 0 + .dw 0xe940, 0xc93e, 0xe97f, 0xc93e, 0x21, 0 + .dw 0xe9c0, 0xc93e, 0xe9ff, 0xc93e, 0x21, 0 + .dw 0xea40, 0xc93e, 0xea7f, 0xc93e, 0x21, 0 + .dw 0xeac0, 0xc93e, 0xeaff, 0xc93e, 0x21, 0 + .dw 0xeb40, 0xc93e, 0xeb7f, 0xc93e, 0x21, 0 + .dw 0xebc0, 0xc93e, 0xebff, 0xc93e, 0x21, 0 + .dw 0xec40, 0xc93e, 0xec7f, 0xc93e, 0x21, 0 + .dw 0xecc0, 0xc93e, 0xecff, 0xc93e, 0x21, 0 + .dw 0xed40, 0xc93e, 0xed7f, 0xc93e, 0x21, 0 + .dw 0xedc0, 0xc93e, 0xedff, 0xc93e, 0x21, 0 + .dw 0xee40, 0xc93e, 0xee7f, 0xc93e, 0x21, 0 + .dw 0xeec0, 0xc93e, 0xeeff, 0xc93e, 0x21, 0 + .dw 0xef40, 0xc93e, 0xef7f, 0xc93e, 0x21, 0 + .dw 0xefc0, 0xc93e, 0xefff, 0xc93e, 0x21, 0 + .dw 0xf040, 0xc93e, 0xf07f, 0xc93e, 0x21, 0 + .dw 0xf0c0, 0xc93e, 0xf0ff, 0xc93e, 0x21, 0 + .dw 0xf140, 0xc93e, 0xf17f, 0xc93e, 0x21, 0 + .dw 0xf1c0, 0xc93e, 0xf1ff, 0xc93e, 0x21, 0 + .dw 0xf240, 0xc93e, 0xf27f, 0xc93e, 0x21, 0 + .dw 0xf2c0, 0xc93e, 0xf2ff, 0xc93e, 0x21, 0 + .dw 0xf340, 0xc93e, 0xf37f, 0xc93e, 0x21, 0 + .dw 0xf3c0, 0xc93e, 0xf3ff, 0xc93e, 0x21, 0 + .dw 0xf440, 0xc93e, 0xf47f, 0xc93e, 0x21, 0 + .dw 0xf4c0, 0xc93e, 0xf4ff, 0xc93e, 0x21, 0 + .dw 0xf540, 0xc93e, 0xf57f, 0xc93e, 0x21, 0 + .dw 0xf5c0, 0xc93e, 0xf5ff, 0xc93e, 0x21, 0 + .dw 0xf640, 0xc93e, 0xf67f, 0xc93e, 0x21, 0 + .dw 0xf6c0, 0xc93e, 0xf6ff, 0xc93e, 0x21, 0 + .dw 0xf740, 0xc93e, 0xf77f, 0xc93e, 0x21, 0 + .dw 0xf7c0, 0xc93e, 0xf7ff, 0xc93e, 0x21, 0 + .dw 0xf840, 0xc93e, 0xf87f, 0xc93e, 0x21, 0 + .dw 0xf8c0, 0xc93e, 0xf8ff, 0xc93e, 0x21, 0 + .dw 0xf940, 0xc93e, 0xf97f, 0xc93e, 0x21, 0 + .dw 0xf9c0, 0xc93e, 0xffff, 0xc93e, 0x21, 0 + .dw 0x0040, 0xc93f, 0x007f, 0xc93f, 0x21, 0 + .dw 0x00c0, 0xc93f, 0x00ff, 0xc93f, 0x21, 0 + .dw 0x0140, 0xc93f, 0x017f, 0xc93f, 0x21, 0 + .dw 0x01c0, 0xc93f, 0x01ff, 0xc93f, 0x21, 0 + .dw 0x0240, 0xc93f, 0x027f, 0xc93f, 0x21, 0 + .dw 0x02c0, 0xc93f, 0x02ff, 0xc93f, 0x21, 0 + .dw 0x0340, 0xc93f, 0x037f, 0xc93f, 0x21, 0 + .dw 0x03c0, 0xc93f, 0x03ff, 0xc93f, 0x21, 0 + .dw 0x0440, 0xc93f, 0x047f, 0xc93f, 0x21, 0 + .dw 0x04c0, 0xc93f, 0x04ff, 0xc93f, 0x21, 0 + .dw 0x0540, 0xc93f, 0x057f, 0xc93f, 0x21, 0 + .dw 0x05c0, 0xc93f, 0x05ff, 0xc93f, 0x21, 0 + .dw 0x0640, 0xc93f, 0x067f, 0xc93f, 0x21, 0 + .dw 0x06c0, 0xc93f, 0x06ff, 0xc93f, 0x21, 0 + .dw 0x0740, 0xc93f, 0x077f, 0xc93f, 0x21, 0 + .dw 0x07c0, 0xc93f, 0x07ff, 0xc93f, 0x21, 0 + .dw 0x0840, 0xc93f, 0x087f, 0xc93f, 0x21, 0 + .dw 0x08c0, 0xc93f, 0x08ff, 0xc93f, 0x21, 0 + .dw 0x0940, 0xc93f, 0x097f, 0xc93f, 0x21, 0 + .dw 0x09c0, 0xc93f, 0x09ff, 0xc93f, 0x21, 0 + .dw 0x0a40, 0xc93f, 0x0a7f, 0xc93f, 0x21, 0 + .dw 0x0ac0, 0xc93f, 0x0aff, 0xc93f, 0x21, 0 + .dw 0x0b40, 0xc93f, 0x0b7f, 0xc93f, 0x21, 0 + .dw 0x0bc0, 0xc93f, 0x0bff, 0xc93f, 0x21, 0 + .dw 0x0c40, 0xc93f, 0x0c7f, 0xc93f, 0x21, 0 + .dw 0x0cc0, 0xc93f, 0x0cff, 0xc93f, 0x21, 0 + .dw 0x0d40, 0xc93f, 0x0d7f, 0xc93f, 0x21, 0 + .dw 0x0dc0, 0xc93f, 0x0dff, 0xc93f, 0x21, 0 + .dw 0x0e40, 0xc93f, 0x0e7f, 0xc93f, 0x21, 0 + .dw 0x0ec0, 0xc93f, 0x0eff, 0xc93f, 0x21, 0 + .dw 0x0f40, 0xc93f, 0x0f7f, 0xc93f, 0x21, 0 + .dw 0x0fc0, 0xc93f, 0x0fff, 0xc93f, 0x21, 0 + .dw 0x1040, 0xc93f, 0x107f, 0xc93f, 0x21, 0 + .dw 0x10c0, 0xc93f, 0x10ff, 0xc93f, 0x21, 0 + .dw 0x1140, 0xc93f, 0x117f, 0xc93f, 0x21, 0 + .dw 0x11c0, 0xc93f, 0x11ff, 0xc93f, 0x21, 0 + .dw 0x1240, 0xc93f, 0x127f, 0xc93f, 0x21, 0 + .dw 0x12c0, 0xc93f, 0x12ff, 0xc93f, 0x21, 0 + .dw 0x1340, 0xc93f, 0x137f, 0xc93f, 0x21, 0 + .dw 0x13c0, 0xc93f, 0x13ff, 0xc93f, 0x21, 0 + .dw 0x1440, 0xc93f, 0x147f, 0xc93f, 0x21, 0 + .dw 0x14c0, 0xc93f, 0x14ff, 0xc93f, 0x21, 0 + .dw 0x1540, 0xc93f, 0x157f, 0xc93f, 0x21, 0 + .dw 0x15c0, 0xc93f, 0x15ff, 0xc93f, 0x21, 0 + .dw 0x1640, 0xc93f, 0x167f, 0xc93f, 0x21, 0 + .dw 0x16c0, 0xc93f, 0x16ff, 0xc93f, 0x21, 0 + .dw 0x1740, 0xc93f, 0x177f, 0xc93f, 0x21, 0 + .dw 0x17c0, 0xc93f, 0x17ff, 0xc93f, 0x21, 0 + .dw 0x1840, 0xc93f, 0x187f, 0xc93f, 0x21, 0 + .dw 0x18c0, 0xc93f, 0x18ff, 0xc93f, 0x21, 0 + .dw 0x1940, 0xc93f, 0x197f, 0xc93f, 0x21, 0 + .dw 0x19c0, 0xc93f, 0x1fff, 0xc93f, 0x21, 0 + .dw 0x2040, 0xc93f, 0x207f, 0xc93f, 0x21, 0 + .dw 0x20c0, 0xc93f, 0x20ff, 0xc93f, 0x21, 0 + .dw 0x2140, 0xc93f, 0x217f, 0xc93f, 0x21, 0 + .dw 0x21c0, 0xc93f, 0x21ff, 0xc93f, 0x21, 0 + .dw 0x2240, 0xc93f, 0x227f, 0xc93f, 0x21, 0 + .dw 0x22c0, 0xc93f, 0x22ff, 0xc93f, 0x21, 0 + .dw 0x2340, 0xc93f, 0x237f, 0xc93f, 0x21, 0 + .dw 0x23c0, 0xc93f, 0x23ff, 0xc93f, 0x21, 0 + .dw 0x2440, 0xc93f, 0x247f, 0xc93f, 0x21, 0 + .dw 0x24c0, 0xc93f, 0x24ff, 0xc93f, 0x21, 0 + .dw 0x2540, 0xc93f, 0x257f, 0xc93f, 0x21, 0 + .dw 0x25c0, 0xc93f, 0x25ff, 0xc93f, 0x21, 0 + .dw 0x2640, 0xc93f, 0x267f, 0xc93f, 0x21, 0 + .dw 0x26c0, 0xc93f, 0x26ff, 0xc93f, 0x21, 0 + .dw 0x2740, 0xc93f, 0x277f, 0xc93f, 0x21, 0 + .dw 0x27c0, 0xc93f, 0x27ff, 0xc93f, 0x21, 0 + .dw 0x2840, 0xc93f, 0x287f, 0xc93f, 0x21, 0 + .dw 0x28c0, 0xc93f, 0x28ff, 0xc93f, 0x21, 0 + .dw 0x2940, 0xc93f, 0x297f, 0xc93f, 0x21, 0 + .dw 0x29c0, 0xc93f, 0x29ff, 0xc93f, 0x21, 0 + .dw 0x2a40, 0xc93f, 0x2a7f, 0xc93f, 0x21, 0 + .dw 0x2ac0, 0xc93f, 0x2aff, 0xc93f, 0x21, 0 + .dw 0x2b40, 0xc93f, 0x2b7f, 0xc93f, 0x21, 0 + .dw 0x2bc0, 0xc93f, 0x2bff, 0xc93f, 0x21, 0 + .dw 0x2c40, 0xc93f, 0x2c7f, 0xc93f, 0x21, 0 + .dw 0x2cc0, 0xc93f, 0x2cff, 0xc93f, 0x21, 0 + .dw 0x2d40, 0xc93f, 0x2d7f, 0xc93f, 0x21, 0 + .dw 0x2dc0, 0xc93f, 0x2dff, 0xc93f, 0x21, 0 + .dw 0x2e40, 0xc93f, 0x2e7f, 0xc93f, 0x21, 0 + .dw 0x2ec0, 0xc93f, 0x2eff, 0xc93f, 0x21, 0 + .dw 0x2f40, 0xc93f, 0x2f7f, 0xc93f, 0x21, 0 + .dw 0x2fc0, 0xc93f, 0x2fff, 0xc93f, 0x21, 0 + .dw 0x3040, 0xc93f, 0x307f, 0xc93f, 0x21, 0 + .dw 0x30c0, 0xc93f, 0x30ff, 0xc93f, 0x21, 0 + .dw 0x3140, 0xc93f, 0x317f, 0xc93f, 0x21, 0 + .dw 0x31c0, 0xc93f, 0x31ff, 0xc93f, 0x21, 0 + .dw 0x3240, 0xc93f, 0x327f, 0xc93f, 0x21, 0 + .dw 0x32c0, 0xc93f, 0x32ff, 0xc93f, 0x21, 0 + .dw 0x3340, 0xc93f, 0x337f, 0xc93f, 0x21, 0 + .dw 0x33c0, 0xc93f, 0x33ff, 0xc93f, 0x21, 0 + .dw 0x3440, 0xc93f, 0x347f, 0xc93f, 0x21, 0 + .dw 0x34c0, 0xc93f, 0x34ff, 0xc93f, 0x21, 0 + .dw 0x3540, 0xc93f, 0x357f, 0xc93f, 0x21, 0 + .dw 0x35c0, 0xc93f, 0x35ff, 0xc93f, 0x21, 0 + .dw 0x3640, 0xc93f, 0x367f, 0xc93f, 0x21, 0 + .dw 0x36c0, 0xc93f, 0x36ff, 0xc93f, 0x21, 0 + .dw 0x3740, 0xc93f, 0x377f, 0xc93f, 0x21, 0 + .dw 0x37c0, 0xc93f, 0x37ff, 0xc93f, 0x21, 0 + .dw 0x3840, 0xc93f, 0x387f, 0xc93f, 0x21, 0 + .dw 0x38c0, 0xc93f, 0x38ff, 0xc93f, 0x21, 0 + .dw 0x3940, 0xc93f, 0x397f, 0xc93f, 0x21, 0 + .dw 0x39c0, 0xc93f, 0x1fff, 0xc960, 0x21, 0 + .dw 0x3a00, 0xc960, 0x5fff, 0xc960, 0x21, 0 + .dw 0x7a00, 0xc960, 0x9fff, 0xc960, 0x21, 0 + .dw 0xba00, 0xc960, 0xdfff, 0xc960, 0x21, 0 + .dw 0xfa00, 0xc960, 0x1fff, 0xc961, 0x21, 0 + .dw 0x3a00, 0xc961, 0x5fff, 0xc961, 0x21, 0 + .dw 0x7a00, 0xc961, 0x9fff, 0xc961, 0x21, 0 + .dw 0xba00, 0xc961, 0xdfff, 0xc961, 0x21, 0 + .dw 0xfa00, 0xc961, 0x1fff, 0xc962, 0x21, 0 + .dw 0x3a00, 0xc962, 0x5fff, 0xc962, 0x21, 0 + .dw 0x7a00, 0xc962, 0x9fff, 0xc962, 0x21, 0 + .dw 0xba00, 0xc962, 0xdfff, 0xc962, 0x21, 0 + .dw 0xfa00, 0xc962, 0x1fff, 0xc963, 0x21, 0 + .dw 0x3a00, 0xc963, 0xffff, 0xc963, 0x21, 0 + .dw 0x1a00, 0xc964, 0x1fff, 0xc964, 0x21, 0 + .dw 0x3a00, 0xc964, 0x3fff, 0xc964, 0x21, 0 + .dw 0x5a00, 0xc964, 0x5fff, 0xc964, 0x21, 0 + .dw 0x7a00, 0xc964, 0x7fff, 0xc964, 0x21, 0 + .dw 0x9a00, 0xc964, 0x9fff, 0xc964, 0x21, 0 + .dw 0xba00, 0xc964, 0xbfff, 0xc964, 0x21, 0 + .dw 0xda00, 0xc964, 0xdfff, 0xc964, 0x21, 0 + .dw 0xfa00, 0xc964, 0xffff, 0xc964, 0x21, 0 + .dw 0x1a00, 0xc965, 0x1fff, 0xc965, 0x21, 0 + .dw 0x3a00, 0xc965, 0x3fff, 0xc965, 0x21, 0 + .dw 0x5a00, 0xc965, 0x5fff, 0xc965, 0x21, 0 + .dw 0x7a00, 0xc965, 0x7fff, 0xc965, 0x21, 0 + .dw 0x9a00, 0xc965, 0x9fff, 0xc965, 0x21, 0 + .dw 0xba00, 0xc965, 0xbfff, 0xc965, 0x21, 0 + .dw 0xda00, 0xc965, 0xdfff, 0xc965, 0x21, 0 + .dw 0xfa00, 0xc965, 0xffff, 0xc965, 0x21, 0 + .dw 0x1a00, 0xc966, 0x1fff, 0xc966, 0x21, 0 + .dw 0x3a00, 0xc966, 0x3fff, 0xc966, 0x21, 0 + .dw 0x5a00, 0xc966, 0x5fff, 0xc966, 0x21, 0 + .dw 0x7a00, 0xc966, 0x7fff, 0xc966, 0x21, 0 + .dw 0x9a00, 0xc966, 0x9fff, 0xc966, 0x21, 0 + .dw 0xba00, 0xc966, 0xbfff, 0xc966, 0x21, 0 + .dw 0xda00, 0xc966, 0xdfff, 0xc966, 0x21, 0 + .dw 0xfa00, 0xc966, 0xffff, 0xc966, 0x21, 0 + .dw 0x1a00, 0xc967, 0x1fff, 0xc967, 0x21, 0 + .dw 0x3a00, 0xc967, 0x1fff, 0xc970, 0x21, 0 + .dw 0x3a00, 0xc970, 0x5fff, 0xc970, 0x21, 0 + .dw 0x7a00, 0xc970, 0x9fff, 0xc970, 0x21, 0 + .dw 0xba00, 0xc970, 0xdfff, 0xc970, 0x21, 0 + .dw 0xfa00, 0xc970, 0x1fff, 0xc971, 0x21, 0 + .dw 0x3a00, 0xc971, 0x5fff, 0xc971, 0x21, 0 + .dw 0x7a00, 0xc971, 0x9fff, 0xc971, 0x21, 0 + .dw 0xba00, 0xc971, 0xdfff, 0xc971, 0x21, 0 + .dw 0xfa00, 0xc971, 0x1fff, 0xc972, 0x21, 0 + .dw 0x3a00, 0xc972, 0x5fff, 0xc972, 0x21, 0 + .dw 0x7a00, 0xc972, 0x9fff, 0xc972, 0x21, 0 + .dw 0xba00, 0xc972, 0xdfff, 0xc972, 0x21, 0 + .dw 0xfa00, 0xc972, 0xffff, 0xc973, 0x21, 0 + .dw 0x1a00, 0xc974, 0x1fff, 0xc974, 0x21, 0 + .dw 0x3a00, 0xc974, 0x3fff, 0xc974, 0x21, 0 + .dw 0x5a00, 0xc974, 0x5fff, 0xc974, 0x21, 0 + .dw 0x7a00, 0xc974, 0x7fff, 0xc974, 0x21, 0 + .dw 0x9a00, 0xc974, 0x9fff, 0xc974, 0x21, 0 + .dw 0xba00, 0xc974, 0xbfff, 0xc974, 0x21, 0 + .dw 0xda00, 0xc974, 0xdfff, 0xc974, 0x21, 0 + .dw 0xfa00, 0xc974, 0xffff, 0xc974, 0x21, 0 + .dw 0x1a00, 0xc975, 0x1fff, 0xc975, 0x21, 0 + .dw 0x3a00, 0xc975, 0x3fff, 0xc975, 0x21, 0 + .dw 0x5a00, 0xc975, 0x5fff, 0xc975, 0x21, 0 + .dw 0x7a00, 0xc975, 0x7fff, 0xc975, 0x21, 0 + .dw 0x9a00, 0xc975, 0x9fff, 0xc975, 0x21, 0 + .dw 0xba00, 0xc975, 0xbfff, 0xc975, 0x21, 0 + .dw 0xda00, 0xc975, 0xdfff, 0xc975, 0x21, 0 + .dw 0xfa00, 0xc975, 0xffff, 0xc975, 0x21, 0 + .dw 0x1a00, 0xc976, 0x1fff, 0xc976, 0x21, 0 + .dw 0x3a00, 0xc976, 0x3fff, 0xc976, 0x21, 0 + .dw 0x5a00, 0xc976, 0x5fff, 0xc976, 0x21, 0 + .dw 0x7a00, 0xc976, 0x7fff, 0xc976, 0x21, 0 + .dw 0x9a00, 0xc976, 0x9fff, 0xc976, 0x21, 0 + .dw 0xba00, 0xc976, 0xbfff, 0xc976, 0x21, 0 + .dw 0xda00, 0xc976, 0xdfff, 0xc976, 0x21, 0 + .dw 0xfa00, 0xc976, 0xffff, 0xc976, 0x21, 0 + .dw 0x1a00, 0xc977, 0x1fff, 0xc977, 0x21, 0 + .dw 0x3a00, 0xc977, 0x1fff, 0xc980, 0x21, 0 + .dw 0x3a00, 0xc980, 0x5fff, 0xc980, 0x21, 0 + .dw 0x7a00, 0xc980, 0x9fff, 0xc980, 0x21, 0 + .dw 0xba00, 0xc980, 0xdfff, 0xc980, 0x21, 0 + .dw 0xfa00, 0xc980, 0x1fff, 0xc981, 0x21, 0 + .dw 0x3a00, 0xc981, 0x5fff, 0xc981, 0x21, 0 + .dw 0x7a00, 0xc981, 0x9fff, 0xc981, 0x21, 0 + .dw 0xba00, 0xc981, 0xdfff, 0xc981, 0x21, 0 + .dw 0xfa00, 0xc981, 0x1fff, 0xc982, 0x21, 0 + .dw 0x3a00, 0xc982, 0x5fff, 0xc982, 0x21, 0 + .dw 0x7a00, 0xc982, 0x9fff, 0xc982, 0x21, 0 + .dw 0xba00, 0xc982, 0xdfff, 0xc982, 0x21, 0 + .dw 0xfa00, 0xc982, 0x1fff, 0xc983, 0x21, 0 + .dw 0x3a00, 0xc983, 0xffff, 0xc983, 0x21, 0 + .dw 0x1a00, 0xc984, 0x1fff, 0xc984, 0x21, 0 + .dw 0x3a00, 0xc984, 0x3fff, 0xc984, 0x21, 0 + .dw 0x5a00, 0xc984, 0x5fff, 0xc984, 0x21, 0 + .dw 0x7a00, 0xc984, 0x7fff, 0xc984, 0x21, 0 + .dw 0x9a00, 0xc984, 0x9fff, 0xc984, 0x21, 0 + .dw 0xba00, 0xc984, 0xbfff, 0xc984, 0x21, 0 + .dw 0xda00, 0xc984, 0xdfff, 0xc984, 0x21, 0 + .dw 0xfa00, 0xc984, 0xffff, 0xc984, 0x21, 0 + .dw 0x1a00, 0xc985, 0x1fff, 0xc985, 0x21, 0 + .dw 0x3a00, 0xc985, 0x3fff, 0xc985, 0x21, 0 + .dw 0x5a00, 0xc985, 0x5fff, 0xc985, 0x21, 0 + .dw 0x7a00, 0xc985, 0x7fff, 0xc985, 0x21, 0 + .dw 0x9a00, 0xc985, 0x9fff, 0xc985, 0x21, 0 + .dw 0xba00, 0xc985, 0xbfff, 0xc985, 0x21, 0 + .dw 0xda00, 0xc985, 0xdfff, 0xc985, 0x21, 0 + .dw 0xfa00, 0xc985, 0xffff, 0xc985, 0x21, 0 + .dw 0x1a00, 0xc986, 0x1fff, 0xc986, 0x21, 0 + .dw 0x3a00, 0xc986, 0x3fff, 0xc986, 0x21, 0 + .dw 0x5a00, 0xc986, 0x5fff, 0xc986, 0x21, 0 + .dw 0x7a00, 0xc986, 0x7fff, 0xc986, 0x21, 0 + .dw 0x9a00, 0xc986, 0x9fff, 0xc986, 0x21, 0 + .dw 0xba00, 0xc986, 0xbfff, 0xc986, 0x21, 0 + .dw 0xda00, 0xc986, 0xdfff, 0xc986, 0x21, 0 + .dw 0xfa00, 0xc986, 0xffff, 0xc986, 0x21, 0 + .dw 0x1a00, 0xc987, 0x1fff, 0xc987, 0x21, 0 + .dw 0x3a00, 0xc987, 0x1fff, 0xc988, 0x21, 0 + .dw 0x2040, 0xc988, 0x207f, 0xc988, 0x21, 0 + .dw 0x20c0, 0xc988, 0x20ff, 0xc988, 0x21, 0 + .dw 0x2140, 0xc988, 0x217f, 0xc988, 0x21, 0 + .dw 0x21c0, 0xc988, 0x21ff, 0xc988, 0x21, 0 + .dw 0x2240, 0xc988, 0x227f, 0xc988, 0x21, 0 + .dw 0x22c0, 0xc988, 0x22ff, 0xc988, 0x21, 0 + .dw 0x2340, 0xc988, 0x237f, 0xc988, 0x21, 0 + .dw 0x23c0, 0xc988, 0x23ff, 0xc988, 0x21, 0 + .dw 0x2440, 0xc988, 0x247f, 0xc988, 0x21, 0 + .dw 0x24c0, 0xc988, 0x24ff, 0xc988, 0x21, 0 + .dw 0x2540, 0xc988, 0x257f, 0xc988, 0x21, 0 + .dw 0x25c0, 0xc988, 0x25ff, 0xc988, 0x21, 0 + .dw 0x2640, 0xc988, 0x267f, 0xc988, 0x21, 0 + .dw 0x26c0, 0xc988, 0x26ff, 0xc988, 0x21, 0 + .dw 0x2740, 0xc988, 0x277f, 0xc988, 0x21, 0 + .dw 0x27c0, 0xc988, 0x27ff, 0xc988, 0x21, 0 + .dw 0x2840, 0xc988, 0x287f, 0xc988, 0x21, 0 + .dw 0x28c0, 0xc988, 0x28ff, 0xc988, 0x21, 0 + .dw 0x2940, 0xc988, 0x297f, 0xc988, 0x21, 0 + .dw 0x29c0, 0xc988, 0x29ff, 0xc988, 0x21, 0 + .dw 0x2a40, 0xc988, 0x2a7f, 0xc988, 0x21, 0 + .dw 0x2ac0, 0xc988, 0x2aff, 0xc988, 0x21, 0 + .dw 0x2b40, 0xc988, 0x2b7f, 0xc988, 0x21, 0 + .dw 0x2bc0, 0xc988, 0x2bff, 0xc988, 0x21, 0 + .dw 0x2c40, 0xc988, 0x2c7f, 0xc988, 0x21, 0 + .dw 0x2cc0, 0xc988, 0x2cff, 0xc988, 0x21, 0 + .dw 0x2d40, 0xc988, 0x2d7f, 0xc988, 0x21, 0 + .dw 0x2dc0, 0xc988, 0x2dff, 0xc988, 0x21, 0 + .dw 0x2e40, 0xc988, 0x2e7f, 0xc988, 0x21, 0 + .dw 0x2ec0, 0xc988, 0x2eff, 0xc988, 0x21, 0 + .dw 0x2f40, 0xc988, 0x2f7f, 0xc988, 0x21, 0 + .dw 0x2fc0, 0xc988, 0x2fff, 0xc988, 0x21, 0 + .dw 0x3040, 0xc988, 0x307f, 0xc988, 0x21, 0 + .dw 0x30c0, 0xc988, 0x30ff, 0xc988, 0x21, 0 + .dw 0x3140, 0xc988, 0x317f, 0xc988, 0x21, 0 + .dw 0x31c0, 0xc988, 0x31ff, 0xc988, 0x21, 0 + .dw 0x3240, 0xc988, 0x327f, 0xc988, 0x21, 0 + .dw 0x32c0, 0xc988, 0x32ff, 0xc988, 0x21, 0 + .dw 0x3340, 0xc988, 0x337f, 0xc988, 0x21, 0 + .dw 0x33c0, 0xc988, 0x33ff, 0xc988, 0x21, 0 + .dw 0x3440, 0xc988, 0x347f, 0xc988, 0x21, 0 + .dw 0x34c0, 0xc988, 0x34ff, 0xc988, 0x21, 0 + .dw 0x3540, 0xc988, 0x357f, 0xc988, 0x21, 0 + .dw 0x35c0, 0xc988, 0x35ff, 0xc988, 0x21, 0 + .dw 0x3640, 0xc988, 0x367f, 0xc988, 0x21, 0 + .dw 0x36c0, 0xc988, 0x36ff, 0xc988, 0x21, 0 + .dw 0x3740, 0xc988, 0x377f, 0xc988, 0x21, 0 + .dw 0x37c0, 0xc988, 0x37ff, 0xc988, 0x21, 0 + .dw 0x3840, 0xc988, 0x387f, 0xc988, 0x21, 0 + .dw 0x38c0, 0xc988, 0x38ff, 0xc988, 0x21, 0 + .dw 0x3940, 0xc988, 0x397f, 0xc988, 0x21, 0 + .dw 0x39c0, 0xc988, 0x5fff, 0xc988, 0x21, 0 + .dw 0x6040, 0xc988, 0x607f, 0xc988, 0x21, 0 + .dw 0x60c0, 0xc988, 0x60ff, 0xc988, 0x21, 0 + .dw 0x6140, 0xc988, 0x617f, 0xc988, 0x21, 0 + .dw 0x61c0, 0xc988, 0x61ff, 0xc988, 0x21, 0 + .dw 0x6240, 0xc988, 0x627f, 0xc988, 0x21, 0 + .dw 0x62c0, 0xc988, 0x62ff, 0xc988, 0x21, 0 + .dw 0x6340, 0xc988, 0x637f, 0xc988, 0x21, 0 + .dw 0x63c0, 0xc988, 0x63ff, 0xc988, 0x21, 0 + .dw 0x6440, 0xc988, 0x647f, 0xc988, 0x21, 0 + .dw 0x64c0, 0xc988, 0x64ff, 0xc988, 0x21, 0 + .dw 0x6540, 0xc988, 0x657f, 0xc988, 0x21, 0 + .dw 0x65c0, 0xc988, 0x65ff, 0xc988, 0x21, 0 + .dw 0x6640, 0xc988, 0x667f, 0xc988, 0x21, 0 + .dw 0x66c0, 0xc988, 0x66ff, 0xc988, 0x21, 0 + .dw 0x6740, 0xc988, 0x677f, 0xc988, 0x21, 0 + .dw 0x67c0, 0xc988, 0x67ff, 0xc988, 0x21, 0 + .dw 0x6840, 0xc988, 0x687f, 0xc988, 0x21, 0 + .dw 0x68c0, 0xc988, 0x68ff, 0xc988, 0x21, 0 + .dw 0x6940, 0xc988, 0x697f, 0xc988, 0x21, 0 + .dw 0x69c0, 0xc988, 0x69ff, 0xc988, 0x21, 0 + .dw 0x6a40, 0xc988, 0x6a7f, 0xc988, 0x21, 0 + .dw 0x6ac0, 0xc988, 0x6aff, 0xc988, 0x21, 0 + .dw 0x6b40, 0xc988, 0x6b7f, 0xc988, 0x21, 0 + .dw 0x6bc0, 0xc988, 0x6bff, 0xc988, 0x21, 0 + .dw 0x6c40, 0xc988, 0x6c7f, 0xc988, 0x21, 0 + .dw 0x6cc0, 0xc988, 0x6cff, 0xc988, 0x21, 0 + .dw 0x6d40, 0xc988, 0x6d7f, 0xc988, 0x21, 0 + .dw 0x6dc0, 0xc988, 0x6dff, 0xc988, 0x21, 0 + .dw 0x6e40, 0xc988, 0x6e7f, 0xc988, 0x21, 0 + .dw 0x6ec0, 0xc988, 0x6eff, 0xc988, 0x21, 0 + .dw 0x6f40, 0xc988, 0x6f7f, 0xc988, 0x21, 0 + .dw 0x6fc0, 0xc988, 0x6fff, 0xc988, 0x21, 0 + .dw 0x7040, 0xc988, 0x707f, 0xc988, 0x21, 0 + .dw 0x70c0, 0xc988, 0x70ff, 0xc988, 0x21, 0 + .dw 0x7140, 0xc988, 0x717f, 0xc988, 0x21, 0 + .dw 0x71c0, 0xc988, 0x71ff, 0xc988, 0x21, 0 + .dw 0x7240, 0xc988, 0x727f, 0xc988, 0x21, 0 + .dw 0x72c0, 0xc988, 0x72ff, 0xc988, 0x21, 0 + .dw 0x7340, 0xc988, 0x737f, 0xc988, 0x21, 0 + .dw 0x73c0, 0xc988, 0x73ff, 0xc988, 0x21, 0 + .dw 0x7440, 0xc988, 0x747f, 0xc988, 0x21, 0 + .dw 0x74c0, 0xc988, 0x74ff, 0xc988, 0x21, 0 + .dw 0x7540, 0xc988, 0x757f, 0xc988, 0x21, 0 + .dw 0x75c0, 0xc988, 0x75ff, 0xc988, 0x21, 0 + .dw 0x7640, 0xc988, 0x767f, 0xc988, 0x21, 0 + .dw 0x76c0, 0xc988, 0x76ff, 0xc988, 0x21, 0 + .dw 0x7740, 0xc988, 0x777f, 0xc988, 0x21, 0 + .dw 0x77c0, 0xc988, 0x77ff, 0xc988, 0x21, 0 + .dw 0x7840, 0xc988, 0x787f, 0xc988, 0x21, 0 + .dw 0x78c0, 0xc988, 0x78ff, 0xc988, 0x21, 0 + .dw 0x7940, 0xc988, 0x797f, 0xc988, 0x21, 0 + .dw 0x79c0, 0xc988, 0x9fff, 0xc988, 0x21, 0 + .dw 0xa040, 0xc988, 0xa07f, 0xc988, 0x21, 0 + .dw 0xa0c0, 0xc988, 0xa0ff, 0xc988, 0x21, 0 + .dw 0xa140, 0xc988, 0xa17f, 0xc988, 0x21, 0 + .dw 0xa1c0, 0xc988, 0xa1ff, 0xc988, 0x21, 0 + .dw 0xa240, 0xc988, 0xa27f, 0xc988, 0x21, 0 + .dw 0xa2c0, 0xc988, 0xa2ff, 0xc988, 0x21, 0 + .dw 0xa340, 0xc988, 0xa37f, 0xc988, 0x21, 0 + .dw 0xa3c0, 0xc988, 0xa3ff, 0xc988, 0x21, 0 + .dw 0xa440, 0xc988, 0xa47f, 0xc988, 0x21, 0 + .dw 0xa4c0, 0xc988, 0xa4ff, 0xc988, 0x21, 0 + .dw 0xa540, 0xc988, 0xa57f, 0xc988, 0x21, 0 + .dw 0xa5c0, 0xc988, 0xa5ff, 0xc988, 0x21, 0 + .dw 0xa640, 0xc988, 0xa67f, 0xc988, 0x21, 0 + .dw 0xa6c0, 0xc988, 0xa6ff, 0xc988, 0x21, 0 + .dw 0xa740, 0xc988, 0xa77f, 0xc988, 0x21, 0 + .dw 0xa7c0, 0xc988, 0xa7ff, 0xc988, 0x21, 0 + .dw 0xa840, 0xc988, 0xa87f, 0xc988, 0x21, 0 + .dw 0xa8c0, 0xc988, 0xa8ff, 0xc988, 0x21, 0 + .dw 0xa940, 0xc988, 0xa97f, 0xc988, 0x21, 0 + .dw 0xa9c0, 0xc988, 0xa9ff, 0xc988, 0x21, 0 + .dw 0xaa40, 0xc988, 0xaa7f, 0xc988, 0x21, 0 + .dw 0xaac0, 0xc988, 0xaaff, 0xc988, 0x21, 0 + .dw 0xab40, 0xc988, 0xab7f, 0xc988, 0x21, 0 + .dw 0xabc0, 0xc988, 0xabff, 0xc988, 0x21, 0 + .dw 0xac40, 0xc988, 0xac7f, 0xc988, 0x21, 0 + .dw 0xacc0, 0xc988, 0xacff, 0xc988, 0x21, 0 + .dw 0xad40, 0xc988, 0xad7f, 0xc988, 0x21, 0 + .dw 0xadc0, 0xc988, 0xadff, 0xc988, 0x21, 0 + .dw 0xae40, 0xc988, 0xae7f, 0xc988, 0x21, 0 + .dw 0xaec0, 0xc988, 0xaeff, 0xc988, 0x21, 0 + .dw 0xaf40, 0xc988, 0xaf7f, 0xc988, 0x21, 0 + .dw 0xafc0, 0xc988, 0xafff, 0xc988, 0x21, 0 + .dw 0xb040, 0xc988, 0xb07f, 0xc988, 0x21, 0 + .dw 0xb0c0, 0xc988, 0xb0ff, 0xc988, 0x21, 0 + .dw 0xb140, 0xc988, 0xb17f, 0xc988, 0x21, 0 + .dw 0xb1c0, 0xc988, 0xb1ff, 0xc988, 0x21, 0 + .dw 0xb240, 0xc988, 0xb27f, 0xc988, 0x21, 0 + .dw 0xb2c0, 0xc988, 0xb2ff, 0xc988, 0x21, 0 + .dw 0xb340, 0xc988, 0xb37f, 0xc988, 0x21, 0 + .dw 0xb3c0, 0xc988, 0xb3ff, 0xc988, 0x21, 0 + .dw 0xb440, 0xc988, 0xb47f, 0xc988, 0x21, 0 + .dw 0xb4c0, 0xc988, 0xb4ff, 0xc988, 0x21, 0 + .dw 0xb540, 0xc988, 0xb57f, 0xc988, 0x21, 0 + .dw 0xb5c0, 0xc988, 0xb5ff, 0xc988, 0x21, 0 + .dw 0xb640, 0xc988, 0xb67f, 0xc988, 0x21, 0 + .dw 0xb6c0, 0xc988, 0xb6ff, 0xc988, 0x21, 0 + .dw 0xb740, 0xc988, 0xb77f, 0xc988, 0x21, 0 + .dw 0xb7c0, 0xc988, 0xb7ff, 0xc988, 0x21, 0 + .dw 0xb840, 0xc988, 0xb87f, 0xc988, 0x21, 0 + .dw 0xb8c0, 0xc988, 0xb8ff, 0xc988, 0x21, 0 + .dw 0xb940, 0xc988, 0xb97f, 0xc988, 0x21, 0 + .dw 0xb9c0, 0xc988, 0xdfff, 0xc988, 0x21, 0 + .dw 0xe040, 0xc988, 0xe07f, 0xc988, 0x21, 0 + .dw 0xe0c0, 0xc988, 0xe0ff, 0xc988, 0x21, 0 + .dw 0xe140, 0xc988, 0xe17f, 0xc988, 0x21, 0 + .dw 0xe1c0, 0xc988, 0xe1ff, 0xc988, 0x21, 0 + .dw 0xe240, 0xc988, 0xe27f, 0xc988, 0x21, 0 + .dw 0xe2c0, 0xc988, 0xe2ff, 0xc988, 0x21, 0 + .dw 0xe340, 0xc988, 0xe37f, 0xc988, 0x21, 0 + .dw 0xe3c0, 0xc988, 0xe3ff, 0xc988, 0x21, 0 + .dw 0xe440, 0xc988, 0xe47f, 0xc988, 0x21, 0 + .dw 0xe4c0, 0xc988, 0xe4ff, 0xc988, 0x21, 0 + .dw 0xe540, 0xc988, 0xe57f, 0xc988, 0x21, 0 + .dw 0xe5c0, 0xc988, 0xe5ff, 0xc988, 0x21, 0 + .dw 0xe640, 0xc988, 0xe67f, 0xc988, 0x21, 0 + .dw 0xe6c0, 0xc988, 0xe6ff, 0xc988, 0x21, 0 + .dw 0xe740, 0xc988, 0xe77f, 0xc988, 0x21, 0 + .dw 0xe7c0, 0xc988, 0xe7ff, 0xc988, 0x21, 0 + .dw 0xe840, 0xc988, 0xe87f, 0xc988, 0x21, 0 + .dw 0xe8c0, 0xc988, 0xe8ff, 0xc988, 0x21, 0 + .dw 0xe940, 0xc988, 0xe97f, 0xc988, 0x21, 0 + .dw 0xe9c0, 0xc988, 0xe9ff, 0xc988, 0x21, 0 + .dw 0xea40, 0xc988, 0xea7f, 0xc988, 0x21, 0 + .dw 0xeac0, 0xc988, 0xeaff, 0xc988, 0x21, 0 + .dw 0xeb40, 0xc988, 0xeb7f, 0xc988, 0x21, 0 + .dw 0xebc0, 0xc988, 0xebff, 0xc988, 0x21, 0 + .dw 0xec40, 0xc988, 0xec7f, 0xc988, 0x21, 0 + .dw 0xecc0, 0xc988, 0xecff, 0xc988, 0x21, 0 + .dw 0xed40, 0xc988, 0xed7f, 0xc988, 0x21, 0 + .dw 0xedc0, 0xc988, 0xedff, 0xc988, 0x21, 0 + .dw 0xee40, 0xc988, 0xee7f, 0xc988, 0x21, 0 + .dw 0xeec0, 0xc988, 0xeeff, 0xc988, 0x21, 0 + .dw 0xef40, 0xc988, 0xef7f, 0xc988, 0x21, 0 + .dw 0xefc0, 0xc988, 0xefff, 0xc988, 0x21, 0 + .dw 0xf040, 0xc988, 0xf07f, 0xc988, 0x21, 0 + .dw 0xf0c0, 0xc988, 0xf0ff, 0xc988, 0x21, 0 + .dw 0xf140, 0xc988, 0xf17f, 0xc988, 0x21, 0 + .dw 0xf1c0, 0xc988, 0xf1ff, 0xc988, 0x21, 0 + .dw 0xf240, 0xc988, 0xf27f, 0xc988, 0x21, 0 + .dw 0xf2c0, 0xc988, 0xf2ff, 0xc988, 0x21, 0 + .dw 0xf340, 0xc988, 0xf37f, 0xc988, 0x21, 0 + .dw 0xf3c0, 0xc988, 0xf3ff, 0xc988, 0x21, 0 + .dw 0xf440, 0xc988, 0xf47f, 0xc988, 0x21, 0 + .dw 0xf4c0, 0xc988, 0xf4ff, 0xc988, 0x21, 0 + .dw 0xf540, 0xc988, 0xf57f, 0xc988, 0x21, 0 + .dw 0xf5c0, 0xc988, 0xf5ff, 0xc988, 0x21, 0 + .dw 0xf640, 0xc988, 0xf67f, 0xc988, 0x21, 0 + .dw 0xf6c0, 0xc988, 0xf6ff, 0xc988, 0x21, 0 + .dw 0xf740, 0xc988, 0xf77f, 0xc988, 0x21, 0 + .dw 0xf7c0, 0xc988, 0xf7ff, 0xc988, 0x21, 0 + .dw 0xf840, 0xc988, 0xf87f, 0xc988, 0x21, 0 + .dw 0xf8c0, 0xc988, 0xf8ff, 0xc988, 0x21, 0 + .dw 0xf940, 0xc988, 0xf97f, 0xc988, 0x21, 0 + .dw 0xf9c0, 0xc988, 0x1fff, 0xc989, 0x21, 0 + .dw 0x2040, 0xc989, 0x207f, 0xc989, 0x21, 0 + .dw 0x20c0, 0xc989, 0x20ff, 0xc989, 0x21, 0 + .dw 0x2140, 0xc989, 0x217f, 0xc989, 0x21, 0 + .dw 0x21c0, 0xc989, 0x21ff, 0xc989, 0x21, 0 + .dw 0x2240, 0xc989, 0x227f, 0xc989, 0x21, 0 + .dw 0x22c0, 0xc989, 0x22ff, 0xc989, 0x21, 0 + .dw 0x2340, 0xc989, 0x237f, 0xc989, 0x21, 0 + .dw 0x23c0, 0xc989, 0x23ff, 0xc989, 0x21, 0 + .dw 0x2440, 0xc989, 0x247f, 0xc989, 0x21, 0 + .dw 0x24c0, 0xc989, 0x24ff, 0xc989, 0x21, 0 + .dw 0x2540, 0xc989, 0x257f, 0xc989, 0x21, 0 + .dw 0x25c0, 0xc989, 0x25ff, 0xc989, 0x21, 0 + .dw 0x2640, 0xc989, 0x267f, 0xc989, 0x21, 0 + .dw 0x26c0, 0xc989, 0x26ff, 0xc989, 0x21, 0 + .dw 0x2740, 0xc989, 0x277f, 0xc989, 0x21, 0 + .dw 0x27c0, 0xc989, 0x27ff, 0xc989, 0x21, 0 + .dw 0x2840, 0xc989, 0x287f, 0xc989, 0x21, 0 + .dw 0x28c0, 0xc989, 0x28ff, 0xc989, 0x21, 0 + .dw 0x2940, 0xc989, 0x297f, 0xc989, 0x21, 0 + .dw 0x29c0, 0xc989, 0x29ff, 0xc989, 0x21, 0 + .dw 0x2a40, 0xc989, 0x2a7f, 0xc989, 0x21, 0 + .dw 0x2ac0, 0xc989, 0x2aff, 0xc989, 0x21, 0 + .dw 0x2b40, 0xc989, 0x2b7f, 0xc989, 0x21, 0 + .dw 0x2bc0, 0xc989, 0x2bff, 0xc989, 0x21, 0 + .dw 0x2c40, 0xc989, 0x2c7f, 0xc989, 0x21, 0 + .dw 0x2cc0, 0xc989, 0x2cff, 0xc989, 0x21, 0 + .dw 0x2d40, 0xc989, 0x2d7f, 0xc989, 0x21, 0 + .dw 0x2dc0, 0xc989, 0x2dff, 0xc989, 0x21, 0 + .dw 0x2e40, 0xc989, 0x2e7f, 0xc989, 0x21, 0 + .dw 0x2ec0, 0xc989, 0x2eff, 0xc989, 0x21, 0 + .dw 0x2f40, 0xc989, 0x2f7f, 0xc989, 0x21, 0 + .dw 0x2fc0, 0xc989, 0x2fff, 0xc989, 0x21, 0 + .dw 0x3040, 0xc989, 0x307f, 0xc989, 0x21, 0 + .dw 0x30c0, 0xc989, 0x30ff, 0xc989, 0x21, 0 + .dw 0x3140, 0xc989, 0x317f, 0xc989, 0x21, 0 + .dw 0x31c0, 0xc989, 0x31ff, 0xc989, 0x21, 0 + .dw 0x3240, 0xc989, 0x327f, 0xc989, 0x21, 0 + .dw 0x32c0, 0xc989, 0x32ff, 0xc989, 0x21, 0 + .dw 0x3340, 0xc989, 0x337f, 0xc989, 0x21, 0 + .dw 0x33c0, 0xc989, 0x33ff, 0xc989, 0x21, 0 + .dw 0x3440, 0xc989, 0x347f, 0xc989, 0x21, 0 + .dw 0x34c0, 0xc989, 0x34ff, 0xc989, 0x21, 0 + .dw 0x3540, 0xc989, 0x357f, 0xc989, 0x21, 0 + .dw 0x35c0, 0xc989, 0x35ff, 0xc989, 0x21, 0 + .dw 0x3640, 0xc989, 0x367f, 0xc989, 0x21, 0 + .dw 0x36c0, 0xc989, 0x36ff, 0xc989, 0x21, 0 + .dw 0x3740, 0xc989, 0x377f, 0xc989, 0x21, 0 + .dw 0x37c0, 0xc989, 0x37ff, 0xc989, 0x21, 0 + .dw 0x3840, 0xc989, 0x387f, 0xc989, 0x21, 0 + .dw 0x38c0, 0xc989, 0x38ff, 0xc989, 0x21, 0 + .dw 0x3940, 0xc989, 0x397f, 0xc989, 0x21, 0 + .dw 0x39c0, 0xc989, 0x5fff, 0xc989, 0x21, 0 + .dw 0x6040, 0xc989, 0x607f, 0xc989, 0x21, 0 + .dw 0x60c0, 0xc989, 0x60ff, 0xc989, 0x21, 0 + .dw 0x6140, 0xc989, 0x617f, 0xc989, 0x21, 0 + .dw 0x61c0, 0xc989, 0x61ff, 0xc989, 0x21, 0 + .dw 0x6240, 0xc989, 0x627f, 0xc989, 0x21, 0 + .dw 0x62c0, 0xc989, 0x62ff, 0xc989, 0x21, 0 + .dw 0x6340, 0xc989, 0x637f, 0xc989, 0x21, 0 + .dw 0x63c0, 0xc989, 0x63ff, 0xc989, 0x21, 0 + .dw 0x6440, 0xc989, 0x647f, 0xc989, 0x21, 0 + .dw 0x64c0, 0xc989, 0x64ff, 0xc989, 0x21, 0 + .dw 0x6540, 0xc989, 0x657f, 0xc989, 0x21, 0 + .dw 0x65c0, 0xc989, 0x65ff, 0xc989, 0x21, 0 + .dw 0x6640, 0xc989, 0x667f, 0xc989, 0x21, 0 + .dw 0x66c0, 0xc989, 0x66ff, 0xc989, 0x21, 0 + .dw 0x6740, 0xc989, 0x677f, 0xc989, 0x21, 0 + .dw 0x67c0, 0xc989, 0x67ff, 0xc989, 0x21, 0 + .dw 0x6840, 0xc989, 0x687f, 0xc989, 0x21, 0 + .dw 0x68c0, 0xc989, 0x68ff, 0xc989, 0x21, 0 + .dw 0x6940, 0xc989, 0x697f, 0xc989, 0x21, 0 + .dw 0x69c0, 0xc989, 0x69ff, 0xc989, 0x21, 0 + .dw 0x6a40, 0xc989, 0x6a7f, 0xc989, 0x21, 0 + .dw 0x6ac0, 0xc989, 0x6aff, 0xc989, 0x21, 0 + .dw 0x6b40, 0xc989, 0x6b7f, 0xc989, 0x21, 0 + .dw 0x6bc0, 0xc989, 0x6bff, 0xc989, 0x21, 0 + .dw 0x6c40, 0xc989, 0x6c7f, 0xc989, 0x21, 0 + .dw 0x6cc0, 0xc989, 0x6cff, 0xc989, 0x21, 0 + .dw 0x6d40, 0xc989, 0x6d7f, 0xc989, 0x21, 0 + .dw 0x6dc0, 0xc989, 0x6dff, 0xc989, 0x21, 0 + .dw 0x6e40, 0xc989, 0x6e7f, 0xc989, 0x21, 0 + .dw 0x6ec0, 0xc989, 0x6eff, 0xc989, 0x21, 0 + .dw 0x6f40, 0xc989, 0x6f7f, 0xc989, 0x21, 0 + .dw 0x6fc0, 0xc989, 0x6fff, 0xc989, 0x21, 0 + .dw 0x7040, 0xc989, 0x707f, 0xc989, 0x21, 0 + .dw 0x70c0, 0xc989, 0x70ff, 0xc989, 0x21, 0 + .dw 0x7140, 0xc989, 0x717f, 0xc989, 0x21, 0 + .dw 0x71c0, 0xc989, 0x71ff, 0xc989, 0x21, 0 + .dw 0x7240, 0xc989, 0x727f, 0xc989, 0x21, 0 + .dw 0x72c0, 0xc989, 0x72ff, 0xc989, 0x21, 0 + .dw 0x7340, 0xc989, 0x737f, 0xc989, 0x21, 0 + .dw 0x73c0, 0xc989, 0x73ff, 0xc989, 0x21, 0 + .dw 0x7440, 0xc989, 0x747f, 0xc989, 0x21, 0 + .dw 0x74c0, 0xc989, 0x74ff, 0xc989, 0x21, 0 + .dw 0x7540, 0xc989, 0x757f, 0xc989, 0x21, 0 + .dw 0x75c0, 0xc989, 0x75ff, 0xc989, 0x21, 0 + .dw 0x7640, 0xc989, 0x767f, 0xc989, 0x21, 0 + .dw 0x76c0, 0xc989, 0x76ff, 0xc989, 0x21, 0 + .dw 0x7740, 0xc989, 0x777f, 0xc989, 0x21, 0 + .dw 0x77c0, 0xc989, 0x77ff, 0xc989, 0x21, 0 + .dw 0x7840, 0xc989, 0x787f, 0xc989, 0x21, 0 + .dw 0x78c0, 0xc989, 0x78ff, 0xc989, 0x21, 0 + .dw 0x7940, 0xc989, 0x797f, 0xc989, 0x21, 0 + .dw 0x79c0, 0xc989, 0x9fff, 0xc989, 0x21, 0 + .dw 0xa040, 0xc989, 0xa07f, 0xc989, 0x21, 0 + .dw 0xa0c0, 0xc989, 0xa0ff, 0xc989, 0x21, 0 + .dw 0xa140, 0xc989, 0xa17f, 0xc989, 0x21, 0 + .dw 0xa1c0, 0xc989, 0xa1ff, 0xc989, 0x21, 0 + .dw 0xa240, 0xc989, 0xa27f, 0xc989, 0x21, 0 + .dw 0xa2c0, 0xc989, 0xa2ff, 0xc989, 0x21, 0 + .dw 0xa340, 0xc989, 0xa37f, 0xc989, 0x21, 0 + .dw 0xa3c0, 0xc989, 0xa3ff, 0xc989, 0x21, 0 + .dw 0xa440, 0xc989, 0xa47f, 0xc989, 0x21, 0 + .dw 0xa4c0, 0xc989, 0xa4ff, 0xc989, 0x21, 0 + .dw 0xa540, 0xc989, 0xa57f, 0xc989, 0x21, 0 + .dw 0xa5c0, 0xc989, 0xa5ff, 0xc989, 0x21, 0 + .dw 0xa640, 0xc989, 0xa67f, 0xc989, 0x21, 0 + .dw 0xa6c0, 0xc989, 0xa6ff, 0xc989, 0x21, 0 + .dw 0xa740, 0xc989, 0xa77f, 0xc989, 0x21, 0 + .dw 0xa7c0, 0xc989, 0xa7ff, 0xc989, 0x21, 0 + .dw 0xa840, 0xc989, 0xa87f, 0xc989, 0x21, 0 + .dw 0xa8c0, 0xc989, 0xa8ff, 0xc989, 0x21, 0 + .dw 0xa940, 0xc989, 0xa97f, 0xc989, 0x21, 0 + .dw 0xa9c0, 0xc989, 0xa9ff, 0xc989, 0x21, 0 + .dw 0xaa40, 0xc989, 0xaa7f, 0xc989, 0x21, 0 + .dw 0xaac0, 0xc989, 0xaaff, 0xc989, 0x21, 0 + .dw 0xab40, 0xc989, 0xab7f, 0xc989, 0x21, 0 + .dw 0xabc0, 0xc989, 0xabff, 0xc989, 0x21, 0 + .dw 0xac40, 0xc989, 0xac7f, 0xc989, 0x21, 0 + .dw 0xacc0, 0xc989, 0xacff, 0xc989, 0x21, 0 + .dw 0xad40, 0xc989, 0xad7f, 0xc989, 0x21, 0 + .dw 0xadc0, 0xc989, 0xadff, 0xc989, 0x21, 0 + .dw 0xae40, 0xc989, 0xae7f, 0xc989, 0x21, 0 + .dw 0xaec0, 0xc989, 0xaeff, 0xc989, 0x21, 0 + .dw 0xaf40, 0xc989, 0xaf7f, 0xc989, 0x21, 0 + .dw 0xafc0, 0xc989, 0xafff, 0xc989, 0x21, 0 + .dw 0xb040, 0xc989, 0xb07f, 0xc989, 0x21, 0 + .dw 0xb0c0, 0xc989, 0xb0ff, 0xc989, 0x21, 0 + .dw 0xb140, 0xc989, 0xb17f, 0xc989, 0x21, 0 + .dw 0xb1c0, 0xc989, 0xb1ff, 0xc989, 0x21, 0 + .dw 0xb240, 0xc989, 0xb27f, 0xc989, 0x21, 0 + .dw 0xb2c0, 0xc989, 0xb2ff, 0xc989, 0x21, 0 + .dw 0xb340, 0xc989, 0xb37f, 0xc989, 0x21, 0 + .dw 0xb3c0, 0xc989, 0xb3ff, 0xc989, 0x21, 0 + .dw 0xb440, 0xc989, 0xb47f, 0xc989, 0x21, 0 + .dw 0xb4c0, 0xc989, 0xb4ff, 0xc989, 0x21, 0 + .dw 0xb540, 0xc989, 0xb57f, 0xc989, 0x21, 0 + .dw 0xb5c0, 0xc989, 0xb5ff, 0xc989, 0x21, 0 + .dw 0xb640, 0xc989, 0xb67f, 0xc989, 0x21, 0 + .dw 0xb6c0, 0xc989, 0xb6ff, 0xc989, 0x21, 0 + .dw 0xb740, 0xc989, 0xb77f, 0xc989, 0x21, 0 + .dw 0xb7c0, 0xc989, 0xb7ff, 0xc989, 0x21, 0 + .dw 0xb840, 0xc989, 0xb87f, 0xc989, 0x21, 0 + .dw 0xb8c0, 0xc989, 0xb8ff, 0xc989, 0x21, 0 + .dw 0xb940, 0xc989, 0xb97f, 0xc989, 0x21, 0 + .dw 0xb9c0, 0xc989, 0xdfff, 0xc989, 0x21, 0 + .dw 0xe040, 0xc989, 0xe07f, 0xc989, 0x21, 0 + .dw 0xe0c0, 0xc989, 0xe0ff, 0xc989, 0x21, 0 + .dw 0xe140, 0xc989, 0xe17f, 0xc989, 0x21, 0 + .dw 0xe1c0, 0xc989, 0xe1ff, 0xc989, 0x21, 0 + .dw 0xe240, 0xc989, 0xe27f, 0xc989, 0x21, 0 + .dw 0xe2c0, 0xc989, 0xe2ff, 0xc989, 0x21, 0 + .dw 0xe340, 0xc989, 0xe37f, 0xc989, 0x21, 0 + .dw 0xe3c0, 0xc989, 0xe3ff, 0xc989, 0x21, 0 + .dw 0xe440, 0xc989, 0xe47f, 0xc989, 0x21, 0 + .dw 0xe4c0, 0xc989, 0xe4ff, 0xc989, 0x21, 0 + .dw 0xe540, 0xc989, 0xe57f, 0xc989, 0x21, 0 + .dw 0xe5c0, 0xc989, 0xe5ff, 0xc989, 0x21, 0 + .dw 0xe640, 0xc989, 0xe67f, 0xc989, 0x21, 0 + .dw 0xe6c0, 0xc989, 0xe6ff, 0xc989, 0x21, 0 + .dw 0xe740, 0xc989, 0xe77f, 0xc989, 0x21, 0 + .dw 0xe7c0, 0xc989, 0xe7ff, 0xc989, 0x21, 0 + .dw 0xe840, 0xc989, 0xe87f, 0xc989, 0x21, 0 + .dw 0xe8c0, 0xc989, 0xe8ff, 0xc989, 0x21, 0 + .dw 0xe940, 0xc989, 0xe97f, 0xc989, 0x21, 0 + .dw 0xe9c0, 0xc989, 0xe9ff, 0xc989, 0x21, 0 + .dw 0xea40, 0xc989, 0xea7f, 0xc989, 0x21, 0 + .dw 0xeac0, 0xc989, 0xeaff, 0xc989, 0x21, 0 + .dw 0xeb40, 0xc989, 0xeb7f, 0xc989, 0x21, 0 + .dw 0xebc0, 0xc989, 0xebff, 0xc989, 0x21, 0 + .dw 0xec40, 0xc989, 0xec7f, 0xc989, 0x21, 0 + .dw 0xecc0, 0xc989, 0xecff, 0xc989, 0x21, 0 + .dw 0xed40, 0xc989, 0xed7f, 0xc989, 0x21, 0 + .dw 0xedc0, 0xc989, 0xedff, 0xc989, 0x21, 0 + .dw 0xee40, 0xc989, 0xee7f, 0xc989, 0x21, 0 + .dw 0xeec0, 0xc989, 0xeeff, 0xc989, 0x21, 0 + .dw 0xef40, 0xc989, 0xef7f, 0xc989, 0x21, 0 + .dw 0xefc0, 0xc989, 0xefff, 0xc989, 0x21, 0 + .dw 0xf040, 0xc989, 0xf07f, 0xc989, 0x21, 0 + .dw 0xf0c0, 0xc989, 0xf0ff, 0xc989, 0x21, 0 + .dw 0xf140, 0xc989, 0xf17f, 0xc989, 0x21, 0 + .dw 0xf1c0, 0xc989, 0xf1ff, 0xc989, 0x21, 0 + .dw 0xf240, 0xc989, 0xf27f, 0xc989, 0x21, 0 + .dw 0xf2c0, 0xc989, 0xf2ff, 0xc989, 0x21, 0 + .dw 0xf340, 0xc989, 0xf37f, 0xc989, 0x21, 0 + .dw 0xf3c0, 0xc989, 0xf3ff, 0xc989, 0x21, 0 + .dw 0xf440, 0xc989, 0xf47f, 0xc989, 0x21, 0 + .dw 0xf4c0, 0xc989, 0xf4ff, 0xc989, 0x21, 0 + .dw 0xf540, 0xc989, 0xf57f, 0xc989, 0x21, 0 + .dw 0xf5c0, 0xc989, 0xf5ff, 0xc989, 0x21, 0 + .dw 0xf640, 0xc989, 0xf67f, 0xc989, 0x21, 0 + .dw 0xf6c0, 0xc989, 0xf6ff, 0xc989, 0x21, 0 + .dw 0xf740, 0xc989, 0xf77f, 0xc989, 0x21, 0 + .dw 0xf7c0, 0xc989, 0xf7ff, 0xc989, 0x21, 0 + .dw 0xf840, 0xc989, 0xf87f, 0xc989, 0x21, 0 + .dw 0xf8c0, 0xc989, 0xf8ff, 0xc989, 0x21, 0 + .dw 0xf940, 0xc989, 0xf97f, 0xc989, 0x21, 0 + .dw 0xf9c0, 0xc989, 0x1fff, 0xc98a, 0x21, 0 + .dw 0x2040, 0xc98a, 0x207f, 0xc98a, 0x21, 0 + .dw 0x20c0, 0xc98a, 0x20ff, 0xc98a, 0x21, 0 + .dw 0x2140, 0xc98a, 0x217f, 0xc98a, 0x21, 0 + .dw 0x21c0, 0xc98a, 0x21ff, 0xc98a, 0x21, 0 + .dw 0x2240, 0xc98a, 0x227f, 0xc98a, 0x21, 0 + .dw 0x22c0, 0xc98a, 0x22ff, 0xc98a, 0x21, 0 + .dw 0x2340, 0xc98a, 0x237f, 0xc98a, 0x21, 0 + .dw 0x23c0, 0xc98a, 0x23ff, 0xc98a, 0x21, 0 + .dw 0x2440, 0xc98a, 0x247f, 0xc98a, 0x21, 0 + .dw 0x24c0, 0xc98a, 0x24ff, 0xc98a, 0x21, 0 + .dw 0x2540, 0xc98a, 0x257f, 0xc98a, 0x21, 0 + .dw 0x25c0, 0xc98a, 0x25ff, 0xc98a, 0x21, 0 + .dw 0x2640, 0xc98a, 0x267f, 0xc98a, 0x21, 0 + .dw 0x26c0, 0xc98a, 0x26ff, 0xc98a, 0x21, 0 + .dw 0x2740, 0xc98a, 0x277f, 0xc98a, 0x21, 0 + .dw 0x27c0, 0xc98a, 0x27ff, 0xc98a, 0x21, 0 + .dw 0x2840, 0xc98a, 0x287f, 0xc98a, 0x21, 0 + .dw 0x28c0, 0xc98a, 0x28ff, 0xc98a, 0x21, 0 + .dw 0x2940, 0xc98a, 0x297f, 0xc98a, 0x21, 0 + .dw 0x29c0, 0xc98a, 0x29ff, 0xc98a, 0x21, 0 + .dw 0x2a40, 0xc98a, 0x2a7f, 0xc98a, 0x21, 0 + .dw 0x2ac0, 0xc98a, 0x2aff, 0xc98a, 0x21, 0 + .dw 0x2b40, 0xc98a, 0x2b7f, 0xc98a, 0x21, 0 + .dw 0x2bc0, 0xc98a, 0x2bff, 0xc98a, 0x21, 0 + .dw 0x2c40, 0xc98a, 0x2c7f, 0xc98a, 0x21, 0 + .dw 0x2cc0, 0xc98a, 0x2cff, 0xc98a, 0x21, 0 + .dw 0x2d40, 0xc98a, 0x2d7f, 0xc98a, 0x21, 0 + .dw 0x2dc0, 0xc98a, 0x2dff, 0xc98a, 0x21, 0 + .dw 0x2e40, 0xc98a, 0x2e7f, 0xc98a, 0x21, 0 + .dw 0x2ec0, 0xc98a, 0x2eff, 0xc98a, 0x21, 0 + .dw 0x2f40, 0xc98a, 0x2f7f, 0xc98a, 0x21, 0 + .dw 0x2fc0, 0xc98a, 0x2fff, 0xc98a, 0x21, 0 + .dw 0x3040, 0xc98a, 0x307f, 0xc98a, 0x21, 0 + .dw 0x30c0, 0xc98a, 0x30ff, 0xc98a, 0x21, 0 + .dw 0x3140, 0xc98a, 0x317f, 0xc98a, 0x21, 0 + .dw 0x31c0, 0xc98a, 0x31ff, 0xc98a, 0x21, 0 + .dw 0x3240, 0xc98a, 0x327f, 0xc98a, 0x21, 0 + .dw 0x32c0, 0xc98a, 0x32ff, 0xc98a, 0x21, 0 + .dw 0x3340, 0xc98a, 0x337f, 0xc98a, 0x21, 0 + .dw 0x33c0, 0xc98a, 0x33ff, 0xc98a, 0x21, 0 + .dw 0x3440, 0xc98a, 0x347f, 0xc98a, 0x21, 0 + .dw 0x34c0, 0xc98a, 0x34ff, 0xc98a, 0x21, 0 + .dw 0x3540, 0xc98a, 0x357f, 0xc98a, 0x21, 0 + .dw 0x35c0, 0xc98a, 0x35ff, 0xc98a, 0x21, 0 + .dw 0x3640, 0xc98a, 0x367f, 0xc98a, 0x21, 0 + .dw 0x36c0, 0xc98a, 0x36ff, 0xc98a, 0x21, 0 + .dw 0x3740, 0xc98a, 0x377f, 0xc98a, 0x21, 0 + .dw 0x37c0, 0xc98a, 0x37ff, 0xc98a, 0x21, 0 + .dw 0x3840, 0xc98a, 0x387f, 0xc98a, 0x21, 0 + .dw 0x38c0, 0xc98a, 0x38ff, 0xc98a, 0x21, 0 + .dw 0x3940, 0xc98a, 0x397f, 0xc98a, 0x21, 0 + .dw 0x39c0, 0xc98a, 0x5fff, 0xc98a, 0x21, 0 + .dw 0x6040, 0xc98a, 0x607f, 0xc98a, 0x21, 0 + .dw 0x60c0, 0xc98a, 0x60ff, 0xc98a, 0x21, 0 + .dw 0x6140, 0xc98a, 0x617f, 0xc98a, 0x21, 0 + .dw 0x61c0, 0xc98a, 0x61ff, 0xc98a, 0x21, 0 + .dw 0x6240, 0xc98a, 0x627f, 0xc98a, 0x21, 0 + .dw 0x62c0, 0xc98a, 0x62ff, 0xc98a, 0x21, 0 + .dw 0x6340, 0xc98a, 0x637f, 0xc98a, 0x21, 0 + .dw 0x63c0, 0xc98a, 0x63ff, 0xc98a, 0x21, 0 + .dw 0x6440, 0xc98a, 0x647f, 0xc98a, 0x21, 0 + .dw 0x64c0, 0xc98a, 0x64ff, 0xc98a, 0x21, 0 + .dw 0x6540, 0xc98a, 0x657f, 0xc98a, 0x21, 0 + .dw 0x65c0, 0xc98a, 0x65ff, 0xc98a, 0x21, 0 + .dw 0x6640, 0xc98a, 0x667f, 0xc98a, 0x21, 0 + .dw 0x66c0, 0xc98a, 0x66ff, 0xc98a, 0x21, 0 + .dw 0x6740, 0xc98a, 0x677f, 0xc98a, 0x21, 0 + .dw 0x67c0, 0xc98a, 0x67ff, 0xc98a, 0x21, 0 + .dw 0x6840, 0xc98a, 0x687f, 0xc98a, 0x21, 0 + .dw 0x68c0, 0xc98a, 0x68ff, 0xc98a, 0x21, 0 + .dw 0x6940, 0xc98a, 0x697f, 0xc98a, 0x21, 0 + .dw 0x69c0, 0xc98a, 0x69ff, 0xc98a, 0x21, 0 + .dw 0x6a40, 0xc98a, 0x6a7f, 0xc98a, 0x21, 0 + .dw 0x6ac0, 0xc98a, 0x6aff, 0xc98a, 0x21, 0 + .dw 0x6b40, 0xc98a, 0x6b7f, 0xc98a, 0x21, 0 + .dw 0x6bc0, 0xc98a, 0x6bff, 0xc98a, 0x21, 0 + .dw 0x6c40, 0xc98a, 0x6c7f, 0xc98a, 0x21, 0 + .dw 0x6cc0, 0xc98a, 0x6cff, 0xc98a, 0x21, 0 + .dw 0x6d40, 0xc98a, 0x6d7f, 0xc98a, 0x21, 0 + .dw 0x6dc0, 0xc98a, 0x6dff, 0xc98a, 0x21, 0 + .dw 0x6e40, 0xc98a, 0x6e7f, 0xc98a, 0x21, 0 + .dw 0x6ec0, 0xc98a, 0x6eff, 0xc98a, 0x21, 0 + .dw 0x6f40, 0xc98a, 0x6f7f, 0xc98a, 0x21, 0 + .dw 0x6fc0, 0xc98a, 0x6fff, 0xc98a, 0x21, 0 + .dw 0x7040, 0xc98a, 0x707f, 0xc98a, 0x21, 0 + .dw 0x70c0, 0xc98a, 0x70ff, 0xc98a, 0x21, 0 + .dw 0x7140, 0xc98a, 0x717f, 0xc98a, 0x21, 0 + .dw 0x71c0, 0xc98a, 0x71ff, 0xc98a, 0x21, 0 + .dw 0x7240, 0xc98a, 0x727f, 0xc98a, 0x21, 0 + .dw 0x72c0, 0xc98a, 0x72ff, 0xc98a, 0x21, 0 + .dw 0x7340, 0xc98a, 0x737f, 0xc98a, 0x21, 0 + .dw 0x73c0, 0xc98a, 0x73ff, 0xc98a, 0x21, 0 + .dw 0x7440, 0xc98a, 0x747f, 0xc98a, 0x21, 0 + .dw 0x74c0, 0xc98a, 0x74ff, 0xc98a, 0x21, 0 + .dw 0x7540, 0xc98a, 0x757f, 0xc98a, 0x21, 0 + .dw 0x75c0, 0xc98a, 0x75ff, 0xc98a, 0x21, 0 + .dw 0x7640, 0xc98a, 0x767f, 0xc98a, 0x21, 0 + .dw 0x76c0, 0xc98a, 0x76ff, 0xc98a, 0x21, 0 + .dw 0x7740, 0xc98a, 0x777f, 0xc98a, 0x21, 0 + .dw 0x77c0, 0xc98a, 0x77ff, 0xc98a, 0x21, 0 + .dw 0x7840, 0xc98a, 0x787f, 0xc98a, 0x21, 0 + .dw 0x78c0, 0xc98a, 0x78ff, 0xc98a, 0x21, 0 + .dw 0x7940, 0xc98a, 0x797f, 0xc98a, 0x21, 0 + .dw 0x79c0, 0xc98a, 0x9fff, 0xc98a, 0x21, 0 + .dw 0xa040, 0xc98a, 0xa07f, 0xc98a, 0x21, 0 + .dw 0xa0c0, 0xc98a, 0xa0ff, 0xc98a, 0x21, 0 + .dw 0xa140, 0xc98a, 0xa17f, 0xc98a, 0x21, 0 + .dw 0xa1c0, 0xc98a, 0xa1ff, 0xc98a, 0x21, 0 + .dw 0xa240, 0xc98a, 0xa27f, 0xc98a, 0x21, 0 + .dw 0xa2c0, 0xc98a, 0xa2ff, 0xc98a, 0x21, 0 + .dw 0xa340, 0xc98a, 0xa37f, 0xc98a, 0x21, 0 + .dw 0xa3c0, 0xc98a, 0xa3ff, 0xc98a, 0x21, 0 + .dw 0xa440, 0xc98a, 0xa47f, 0xc98a, 0x21, 0 + .dw 0xa4c0, 0xc98a, 0xa4ff, 0xc98a, 0x21, 0 + .dw 0xa540, 0xc98a, 0xa57f, 0xc98a, 0x21, 0 + .dw 0xa5c0, 0xc98a, 0xa5ff, 0xc98a, 0x21, 0 + .dw 0xa640, 0xc98a, 0xa67f, 0xc98a, 0x21, 0 + .dw 0xa6c0, 0xc98a, 0xa6ff, 0xc98a, 0x21, 0 + .dw 0xa740, 0xc98a, 0xa77f, 0xc98a, 0x21, 0 + .dw 0xa7c0, 0xc98a, 0xa7ff, 0xc98a, 0x21, 0 + .dw 0xa840, 0xc98a, 0xa87f, 0xc98a, 0x21, 0 + .dw 0xa8c0, 0xc98a, 0xa8ff, 0xc98a, 0x21, 0 + .dw 0xa940, 0xc98a, 0xa97f, 0xc98a, 0x21, 0 + .dw 0xa9c0, 0xc98a, 0xa9ff, 0xc98a, 0x21, 0 + .dw 0xaa40, 0xc98a, 0xaa7f, 0xc98a, 0x21, 0 + .dw 0xaac0, 0xc98a, 0xaaff, 0xc98a, 0x21, 0 + .dw 0xab40, 0xc98a, 0xab7f, 0xc98a, 0x21, 0 + .dw 0xabc0, 0xc98a, 0xabff, 0xc98a, 0x21, 0 + .dw 0xac40, 0xc98a, 0xac7f, 0xc98a, 0x21, 0 + .dw 0xacc0, 0xc98a, 0xacff, 0xc98a, 0x21, 0 + .dw 0xad40, 0xc98a, 0xad7f, 0xc98a, 0x21, 0 + .dw 0xadc0, 0xc98a, 0xadff, 0xc98a, 0x21, 0 + .dw 0xae40, 0xc98a, 0xae7f, 0xc98a, 0x21, 0 + .dw 0xaec0, 0xc98a, 0xaeff, 0xc98a, 0x21, 0 + .dw 0xaf40, 0xc98a, 0xaf7f, 0xc98a, 0x21, 0 + .dw 0xafc0, 0xc98a, 0xafff, 0xc98a, 0x21, 0 + .dw 0xb040, 0xc98a, 0xb07f, 0xc98a, 0x21, 0 + .dw 0xb0c0, 0xc98a, 0xb0ff, 0xc98a, 0x21, 0 + .dw 0xb140, 0xc98a, 0xb17f, 0xc98a, 0x21, 0 + .dw 0xb1c0, 0xc98a, 0xb1ff, 0xc98a, 0x21, 0 + .dw 0xb240, 0xc98a, 0xb27f, 0xc98a, 0x21, 0 + .dw 0xb2c0, 0xc98a, 0xb2ff, 0xc98a, 0x21, 0 + .dw 0xb340, 0xc98a, 0xb37f, 0xc98a, 0x21, 0 + .dw 0xb3c0, 0xc98a, 0xb3ff, 0xc98a, 0x21, 0 + .dw 0xb440, 0xc98a, 0xb47f, 0xc98a, 0x21, 0 + .dw 0xb4c0, 0xc98a, 0xb4ff, 0xc98a, 0x21, 0 + .dw 0xb540, 0xc98a, 0xb57f, 0xc98a, 0x21, 0 + .dw 0xb5c0, 0xc98a, 0xb5ff, 0xc98a, 0x21, 0 + .dw 0xb640, 0xc98a, 0xb67f, 0xc98a, 0x21, 0 + .dw 0xb6c0, 0xc98a, 0xb6ff, 0xc98a, 0x21, 0 + .dw 0xb740, 0xc98a, 0xb77f, 0xc98a, 0x21, 0 + .dw 0xb7c0, 0xc98a, 0xb7ff, 0xc98a, 0x21, 0 + .dw 0xb840, 0xc98a, 0xb87f, 0xc98a, 0x21, 0 + .dw 0xb8c0, 0xc98a, 0xb8ff, 0xc98a, 0x21, 0 + .dw 0xb940, 0xc98a, 0xb97f, 0xc98a, 0x21, 0 + .dw 0xb9c0, 0xc98a, 0xdfff, 0xc98a, 0x21, 0 + .dw 0xe040, 0xc98a, 0xe07f, 0xc98a, 0x21, 0 + .dw 0xe0c0, 0xc98a, 0xe0ff, 0xc98a, 0x21, 0 + .dw 0xe140, 0xc98a, 0xe17f, 0xc98a, 0x21, 0 + .dw 0xe1c0, 0xc98a, 0xe1ff, 0xc98a, 0x21, 0 + .dw 0xe240, 0xc98a, 0xe27f, 0xc98a, 0x21, 0 + .dw 0xe2c0, 0xc98a, 0xe2ff, 0xc98a, 0x21, 0 + .dw 0xe340, 0xc98a, 0xe37f, 0xc98a, 0x21, 0 + .dw 0xe3c0, 0xc98a, 0xe3ff, 0xc98a, 0x21, 0 + .dw 0xe440, 0xc98a, 0xe47f, 0xc98a, 0x21, 0 + .dw 0xe4c0, 0xc98a, 0xe4ff, 0xc98a, 0x21, 0 + .dw 0xe540, 0xc98a, 0xe57f, 0xc98a, 0x21, 0 + .dw 0xe5c0, 0xc98a, 0xe5ff, 0xc98a, 0x21, 0 + .dw 0xe640, 0xc98a, 0xe67f, 0xc98a, 0x21, 0 + .dw 0xe6c0, 0xc98a, 0xe6ff, 0xc98a, 0x21, 0 + .dw 0xe740, 0xc98a, 0xe77f, 0xc98a, 0x21, 0 + .dw 0xe7c0, 0xc98a, 0xe7ff, 0xc98a, 0x21, 0 + .dw 0xe840, 0xc98a, 0xe87f, 0xc98a, 0x21, 0 + .dw 0xe8c0, 0xc98a, 0xe8ff, 0xc98a, 0x21, 0 + .dw 0xe940, 0xc98a, 0xe97f, 0xc98a, 0x21, 0 + .dw 0xe9c0, 0xc98a, 0xe9ff, 0xc98a, 0x21, 0 + .dw 0xea40, 0xc98a, 0xea7f, 0xc98a, 0x21, 0 + .dw 0xeac0, 0xc98a, 0xeaff, 0xc98a, 0x21, 0 + .dw 0xeb40, 0xc98a, 0xeb7f, 0xc98a, 0x21, 0 + .dw 0xebc0, 0xc98a, 0xebff, 0xc98a, 0x21, 0 + .dw 0xec40, 0xc98a, 0xec7f, 0xc98a, 0x21, 0 + .dw 0xecc0, 0xc98a, 0xecff, 0xc98a, 0x21, 0 + .dw 0xed40, 0xc98a, 0xed7f, 0xc98a, 0x21, 0 + .dw 0xedc0, 0xc98a, 0xedff, 0xc98a, 0x21, 0 + .dw 0xee40, 0xc98a, 0xee7f, 0xc98a, 0x21, 0 + .dw 0xeec0, 0xc98a, 0xeeff, 0xc98a, 0x21, 0 + .dw 0xef40, 0xc98a, 0xef7f, 0xc98a, 0x21, 0 + .dw 0xefc0, 0xc98a, 0xefff, 0xc98a, 0x21, 0 + .dw 0xf040, 0xc98a, 0xf07f, 0xc98a, 0x21, 0 + .dw 0xf0c0, 0xc98a, 0xf0ff, 0xc98a, 0x21, 0 + .dw 0xf140, 0xc98a, 0xf17f, 0xc98a, 0x21, 0 + .dw 0xf1c0, 0xc98a, 0xf1ff, 0xc98a, 0x21, 0 + .dw 0xf240, 0xc98a, 0xf27f, 0xc98a, 0x21, 0 + .dw 0xf2c0, 0xc98a, 0xf2ff, 0xc98a, 0x21, 0 + .dw 0xf340, 0xc98a, 0xf37f, 0xc98a, 0x21, 0 + .dw 0xf3c0, 0xc98a, 0xf3ff, 0xc98a, 0x21, 0 + .dw 0xf440, 0xc98a, 0xf47f, 0xc98a, 0x21, 0 + .dw 0xf4c0, 0xc98a, 0xf4ff, 0xc98a, 0x21, 0 + .dw 0xf540, 0xc98a, 0xf57f, 0xc98a, 0x21, 0 + .dw 0xf5c0, 0xc98a, 0xf5ff, 0xc98a, 0x21, 0 + .dw 0xf640, 0xc98a, 0xf67f, 0xc98a, 0x21, 0 + .dw 0xf6c0, 0xc98a, 0xf6ff, 0xc98a, 0x21, 0 + .dw 0xf740, 0xc98a, 0xf77f, 0xc98a, 0x21, 0 + .dw 0xf7c0, 0xc98a, 0xf7ff, 0xc98a, 0x21, 0 + .dw 0xf840, 0xc98a, 0xf87f, 0xc98a, 0x21, 0 + .dw 0xf8c0, 0xc98a, 0xf8ff, 0xc98a, 0x21, 0 + .dw 0xf940, 0xc98a, 0xf97f, 0xc98a, 0x21, 0 + .dw 0xf9c0, 0xc98a, 0x1fff, 0xc98b, 0x21, 0 + .dw 0x2040, 0xc98b, 0x207f, 0xc98b, 0x21, 0 + .dw 0x20c0, 0xc98b, 0x20ff, 0xc98b, 0x21, 0 + .dw 0x2140, 0xc98b, 0x217f, 0xc98b, 0x21, 0 + .dw 0x21c0, 0xc98b, 0x21ff, 0xc98b, 0x21, 0 + .dw 0x2240, 0xc98b, 0x227f, 0xc98b, 0x21, 0 + .dw 0x22c0, 0xc98b, 0x22ff, 0xc98b, 0x21, 0 + .dw 0x2340, 0xc98b, 0x237f, 0xc98b, 0x21, 0 + .dw 0x23c0, 0xc98b, 0x23ff, 0xc98b, 0x21, 0 + .dw 0x2440, 0xc98b, 0x247f, 0xc98b, 0x21, 0 + .dw 0x24c0, 0xc98b, 0x24ff, 0xc98b, 0x21, 0 + .dw 0x2540, 0xc98b, 0x257f, 0xc98b, 0x21, 0 + .dw 0x25c0, 0xc98b, 0x25ff, 0xc98b, 0x21, 0 + .dw 0x2640, 0xc98b, 0x267f, 0xc98b, 0x21, 0 + .dw 0x26c0, 0xc98b, 0x26ff, 0xc98b, 0x21, 0 + .dw 0x2740, 0xc98b, 0x277f, 0xc98b, 0x21, 0 + .dw 0x27c0, 0xc98b, 0x27ff, 0xc98b, 0x21, 0 + .dw 0x2840, 0xc98b, 0x287f, 0xc98b, 0x21, 0 + .dw 0x28c0, 0xc98b, 0x28ff, 0xc98b, 0x21, 0 + .dw 0x2940, 0xc98b, 0x297f, 0xc98b, 0x21, 0 + .dw 0x29c0, 0xc98b, 0x29ff, 0xc98b, 0x21, 0 + .dw 0x2a40, 0xc98b, 0x2a7f, 0xc98b, 0x21, 0 + .dw 0x2ac0, 0xc98b, 0x2aff, 0xc98b, 0x21, 0 + .dw 0x2b40, 0xc98b, 0x2b7f, 0xc98b, 0x21, 0 + .dw 0x2bc0, 0xc98b, 0x2bff, 0xc98b, 0x21, 0 + .dw 0x2c40, 0xc98b, 0x2c7f, 0xc98b, 0x21, 0 + .dw 0x2cc0, 0xc98b, 0x2cff, 0xc98b, 0x21, 0 + .dw 0x2d40, 0xc98b, 0x2d7f, 0xc98b, 0x21, 0 + .dw 0x2dc0, 0xc98b, 0x2dff, 0xc98b, 0x21, 0 + .dw 0x2e40, 0xc98b, 0x2e7f, 0xc98b, 0x21, 0 + .dw 0x2ec0, 0xc98b, 0x2eff, 0xc98b, 0x21, 0 + .dw 0x2f40, 0xc98b, 0x2f7f, 0xc98b, 0x21, 0 + .dw 0x2fc0, 0xc98b, 0x2fff, 0xc98b, 0x21, 0 + .dw 0x3040, 0xc98b, 0x307f, 0xc98b, 0x21, 0 + .dw 0x30c0, 0xc98b, 0x30ff, 0xc98b, 0x21, 0 + .dw 0x3140, 0xc98b, 0x317f, 0xc98b, 0x21, 0 + .dw 0x31c0, 0xc98b, 0x31ff, 0xc98b, 0x21, 0 + .dw 0x3240, 0xc98b, 0x327f, 0xc98b, 0x21, 0 + .dw 0x32c0, 0xc98b, 0x32ff, 0xc98b, 0x21, 0 + .dw 0x3340, 0xc98b, 0x337f, 0xc98b, 0x21, 0 + .dw 0x33c0, 0xc98b, 0x33ff, 0xc98b, 0x21, 0 + .dw 0x3440, 0xc98b, 0x347f, 0xc98b, 0x21, 0 + .dw 0x34c0, 0xc98b, 0x34ff, 0xc98b, 0x21, 0 + .dw 0x3540, 0xc98b, 0x357f, 0xc98b, 0x21, 0 + .dw 0x35c0, 0xc98b, 0x35ff, 0xc98b, 0x21, 0 + .dw 0x3640, 0xc98b, 0x367f, 0xc98b, 0x21, 0 + .dw 0x36c0, 0xc98b, 0x36ff, 0xc98b, 0x21, 0 + .dw 0x3740, 0xc98b, 0x377f, 0xc98b, 0x21, 0 + .dw 0x37c0, 0xc98b, 0x37ff, 0xc98b, 0x21, 0 + .dw 0x3840, 0xc98b, 0x387f, 0xc98b, 0x21, 0 + .dw 0x38c0, 0xc98b, 0x38ff, 0xc98b, 0x21, 0 + .dw 0x3940, 0xc98b, 0x397f, 0xc98b, 0x21, 0 + .dw 0x39c0, 0xc98b, 0xffff, 0xc98b, 0x21, 0 + .dw 0x0040, 0xc98c, 0x007f, 0xc98c, 0x21, 0 + .dw 0x00c0, 0xc98c, 0x00ff, 0xc98c, 0x21, 0 + .dw 0x0140, 0xc98c, 0x017f, 0xc98c, 0x21, 0 + .dw 0x01c0, 0xc98c, 0x01ff, 0xc98c, 0x21, 0 + .dw 0x0240, 0xc98c, 0x027f, 0xc98c, 0x21, 0 + .dw 0x02c0, 0xc98c, 0x02ff, 0xc98c, 0x21, 0 + .dw 0x0340, 0xc98c, 0x037f, 0xc98c, 0x21, 0 + .dw 0x03c0, 0xc98c, 0x03ff, 0xc98c, 0x21, 0 + .dw 0x0440, 0xc98c, 0x047f, 0xc98c, 0x21, 0 + .dw 0x04c0, 0xc98c, 0x04ff, 0xc98c, 0x21, 0 + .dw 0x0540, 0xc98c, 0x057f, 0xc98c, 0x21, 0 + .dw 0x05c0, 0xc98c, 0x05ff, 0xc98c, 0x21, 0 + .dw 0x0640, 0xc98c, 0x067f, 0xc98c, 0x21, 0 + .dw 0x06c0, 0xc98c, 0x06ff, 0xc98c, 0x21, 0 + .dw 0x0740, 0xc98c, 0x077f, 0xc98c, 0x21, 0 + .dw 0x07c0, 0xc98c, 0x07ff, 0xc98c, 0x21, 0 + .dw 0x0840, 0xc98c, 0x087f, 0xc98c, 0x21, 0 + .dw 0x08c0, 0xc98c, 0x08ff, 0xc98c, 0x21, 0 + .dw 0x0940, 0xc98c, 0x097f, 0xc98c, 0x21, 0 + .dw 0x09c0, 0xc98c, 0x09ff, 0xc98c, 0x21, 0 + .dw 0x0a40, 0xc98c, 0x0a7f, 0xc98c, 0x21, 0 + .dw 0x0ac0, 0xc98c, 0x0aff, 0xc98c, 0x21, 0 + .dw 0x0b40, 0xc98c, 0x0b7f, 0xc98c, 0x21, 0 + .dw 0x0bc0, 0xc98c, 0x0bff, 0xc98c, 0x21, 0 + .dw 0x0c40, 0xc98c, 0x0c7f, 0xc98c, 0x21, 0 + .dw 0x0cc0, 0xc98c, 0x0cff, 0xc98c, 0x21, 0 + .dw 0x0d40, 0xc98c, 0x0d7f, 0xc98c, 0x21, 0 + .dw 0x0dc0, 0xc98c, 0x0dff, 0xc98c, 0x21, 0 + .dw 0x0e40, 0xc98c, 0x0e7f, 0xc98c, 0x21, 0 + .dw 0x0ec0, 0xc98c, 0x0eff, 0xc98c, 0x21, 0 + .dw 0x0f40, 0xc98c, 0x0f7f, 0xc98c, 0x21, 0 + .dw 0x0fc0, 0xc98c, 0x0fff, 0xc98c, 0x21, 0 + .dw 0x1040, 0xc98c, 0x107f, 0xc98c, 0x21, 0 + .dw 0x10c0, 0xc98c, 0x10ff, 0xc98c, 0x21, 0 + .dw 0x1140, 0xc98c, 0x117f, 0xc98c, 0x21, 0 + .dw 0x11c0, 0xc98c, 0x11ff, 0xc98c, 0x21, 0 + .dw 0x1240, 0xc98c, 0x127f, 0xc98c, 0x21, 0 + .dw 0x12c0, 0xc98c, 0x12ff, 0xc98c, 0x21, 0 + .dw 0x1340, 0xc98c, 0x137f, 0xc98c, 0x21, 0 + .dw 0x13c0, 0xc98c, 0x13ff, 0xc98c, 0x21, 0 + .dw 0x1440, 0xc98c, 0x147f, 0xc98c, 0x21, 0 + .dw 0x14c0, 0xc98c, 0x14ff, 0xc98c, 0x21, 0 + .dw 0x1540, 0xc98c, 0x157f, 0xc98c, 0x21, 0 + .dw 0x15c0, 0xc98c, 0x15ff, 0xc98c, 0x21, 0 + .dw 0x1640, 0xc98c, 0x167f, 0xc98c, 0x21, 0 + .dw 0x16c0, 0xc98c, 0x16ff, 0xc98c, 0x21, 0 + .dw 0x1740, 0xc98c, 0x177f, 0xc98c, 0x21, 0 + .dw 0x17c0, 0xc98c, 0x17ff, 0xc98c, 0x21, 0 + .dw 0x1840, 0xc98c, 0x187f, 0xc98c, 0x21, 0 + .dw 0x18c0, 0xc98c, 0x18ff, 0xc98c, 0x21, 0 + .dw 0x1940, 0xc98c, 0x197f, 0xc98c, 0x21, 0 + .dw 0x19c0, 0xc98c, 0x1fff, 0xc98c, 0x21, 0 + .dw 0x2040, 0xc98c, 0x207f, 0xc98c, 0x21, 0 + .dw 0x20c0, 0xc98c, 0x20ff, 0xc98c, 0x21, 0 + .dw 0x2140, 0xc98c, 0x217f, 0xc98c, 0x21, 0 + .dw 0x21c0, 0xc98c, 0x21ff, 0xc98c, 0x21, 0 + .dw 0x2240, 0xc98c, 0x227f, 0xc98c, 0x21, 0 + .dw 0x22c0, 0xc98c, 0x22ff, 0xc98c, 0x21, 0 + .dw 0x2340, 0xc98c, 0x237f, 0xc98c, 0x21, 0 + .dw 0x23c0, 0xc98c, 0x23ff, 0xc98c, 0x21, 0 + .dw 0x2440, 0xc98c, 0x247f, 0xc98c, 0x21, 0 + .dw 0x24c0, 0xc98c, 0x24ff, 0xc98c, 0x21, 0 + .dw 0x2540, 0xc98c, 0x257f, 0xc98c, 0x21, 0 + .dw 0x25c0, 0xc98c, 0x25ff, 0xc98c, 0x21, 0 + .dw 0x2640, 0xc98c, 0x267f, 0xc98c, 0x21, 0 + .dw 0x26c0, 0xc98c, 0x26ff, 0xc98c, 0x21, 0 + .dw 0x2740, 0xc98c, 0x277f, 0xc98c, 0x21, 0 + .dw 0x27c0, 0xc98c, 0x27ff, 0xc98c, 0x21, 0 + .dw 0x2840, 0xc98c, 0x287f, 0xc98c, 0x21, 0 + .dw 0x28c0, 0xc98c, 0x28ff, 0xc98c, 0x21, 0 + .dw 0x2940, 0xc98c, 0x297f, 0xc98c, 0x21, 0 + .dw 0x29c0, 0xc98c, 0x29ff, 0xc98c, 0x21, 0 + .dw 0x2a40, 0xc98c, 0x2a7f, 0xc98c, 0x21, 0 + .dw 0x2ac0, 0xc98c, 0x2aff, 0xc98c, 0x21, 0 + .dw 0x2b40, 0xc98c, 0x2b7f, 0xc98c, 0x21, 0 + .dw 0x2bc0, 0xc98c, 0x2bff, 0xc98c, 0x21, 0 + .dw 0x2c40, 0xc98c, 0x2c7f, 0xc98c, 0x21, 0 + .dw 0x2cc0, 0xc98c, 0x2cff, 0xc98c, 0x21, 0 + .dw 0x2d40, 0xc98c, 0x2d7f, 0xc98c, 0x21, 0 + .dw 0x2dc0, 0xc98c, 0x2dff, 0xc98c, 0x21, 0 + .dw 0x2e40, 0xc98c, 0x2e7f, 0xc98c, 0x21, 0 + .dw 0x2ec0, 0xc98c, 0x2eff, 0xc98c, 0x21, 0 + .dw 0x2f40, 0xc98c, 0x2f7f, 0xc98c, 0x21, 0 + .dw 0x2fc0, 0xc98c, 0x2fff, 0xc98c, 0x21, 0 + .dw 0x3040, 0xc98c, 0x307f, 0xc98c, 0x21, 0 + .dw 0x30c0, 0xc98c, 0x30ff, 0xc98c, 0x21, 0 + .dw 0x3140, 0xc98c, 0x317f, 0xc98c, 0x21, 0 + .dw 0x31c0, 0xc98c, 0x31ff, 0xc98c, 0x21, 0 + .dw 0x3240, 0xc98c, 0x327f, 0xc98c, 0x21, 0 + .dw 0x32c0, 0xc98c, 0x32ff, 0xc98c, 0x21, 0 + .dw 0x3340, 0xc98c, 0x337f, 0xc98c, 0x21, 0 + .dw 0x33c0, 0xc98c, 0x33ff, 0xc98c, 0x21, 0 + .dw 0x3440, 0xc98c, 0x347f, 0xc98c, 0x21, 0 + .dw 0x34c0, 0xc98c, 0x34ff, 0xc98c, 0x21, 0 + .dw 0x3540, 0xc98c, 0x357f, 0xc98c, 0x21, 0 + .dw 0x35c0, 0xc98c, 0x35ff, 0xc98c, 0x21, 0 + .dw 0x3640, 0xc98c, 0x367f, 0xc98c, 0x21, 0 + .dw 0x36c0, 0xc98c, 0x36ff, 0xc98c, 0x21, 0 + .dw 0x3740, 0xc98c, 0x377f, 0xc98c, 0x21, 0 + .dw 0x37c0, 0xc98c, 0x37ff, 0xc98c, 0x21, 0 + .dw 0x3840, 0xc98c, 0x387f, 0xc98c, 0x21, 0 + .dw 0x38c0, 0xc98c, 0x38ff, 0xc98c, 0x21, 0 + .dw 0x3940, 0xc98c, 0x397f, 0xc98c, 0x21, 0 + .dw 0x39c0, 0xc98c, 0x3fff, 0xc98c, 0x21, 0 + .dw 0x4040, 0xc98c, 0x407f, 0xc98c, 0x21, 0 + .dw 0x40c0, 0xc98c, 0x40ff, 0xc98c, 0x21, 0 + .dw 0x4140, 0xc98c, 0x417f, 0xc98c, 0x21, 0 + .dw 0x41c0, 0xc98c, 0x41ff, 0xc98c, 0x21, 0 + .dw 0x4240, 0xc98c, 0x427f, 0xc98c, 0x21, 0 + .dw 0x42c0, 0xc98c, 0x42ff, 0xc98c, 0x21, 0 + .dw 0x4340, 0xc98c, 0x437f, 0xc98c, 0x21, 0 + .dw 0x43c0, 0xc98c, 0x43ff, 0xc98c, 0x21, 0 + .dw 0x4440, 0xc98c, 0x447f, 0xc98c, 0x21, 0 + .dw 0x44c0, 0xc98c, 0x44ff, 0xc98c, 0x21, 0 + .dw 0x4540, 0xc98c, 0x457f, 0xc98c, 0x21, 0 + .dw 0x45c0, 0xc98c, 0x45ff, 0xc98c, 0x21, 0 + .dw 0x4640, 0xc98c, 0x467f, 0xc98c, 0x21, 0 + .dw 0x46c0, 0xc98c, 0x46ff, 0xc98c, 0x21, 0 + .dw 0x4740, 0xc98c, 0x477f, 0xc98c, 0x21, 0 + .dw 0x47c0, 0xc98c, 0x47ff, 0xc98c, 0x21, 0 + .dw 0x4840, 0xc98c, 0x487f, 0xc98c, 0x21, 0 + .dw 0x48c0, 0xc98c, 0x48ff, 0xc98c, 0x21, 0 + .dw 0x4940, 0xc98c, 0x497f, 0xc98c, 0x21, 0 + .dw 0x49c0, 0xc98c, 0x49ff, 0xc98c, 0x21, 0 + .dw 0x4a40, 0xc98c, 0x4a7f, 0xc98c, 0x21, 0 + .dw 0x4ac0, 0xc98c, 0x4aff, 0xc98c, 0x21, 0 + .dw 0x4b40, 0xc98c, 0x4b7f, 0xc98c, 0x21, 0 + .dw 0x4bc0, 0xc98c, 0x4bff, 0xc98c, 0x21, 0 + .dw 0x4c40, 0xc98c, 0x4c7f, 0xc98c, 0x21, 0 + .dw 0x4cc0, 0xc98c, 0x4cff, 0xc98c, 0x21, 0 + .dw 0x4d40, 0xc98c, 0x4d7f, 0xc98c, 0x21, 0 + .dw 0x4dc0, 0xc98c, 0x4dff, 0xc98c, 0x21, 0 + .dw 0x4e40, 0xc98c, 0x4e7f, 0xc98c, 0x21, 0 + .dw 0x4ec0, 0xc98c, 0x4eff, 0xc98c, 0x21, 0 + .dw 0x4f40, 0xc98c, 0x4f7f, 0xc98c, 0x21, 0 + .dw 0x4fc0, 0xc98c, 0x4fff, 0xc98c, 0x21, 0 + .dw 0x5040, 0xc98c, 0x507f, 0xc98c, 0x21, 0 + .dw 0x50c0, 0xc98c, 0x50ff, 0xc98c, 0x21, 0 + .dw 0x5140, 0xc98c, 0x517f, 0xc98c, 0x21, 0 + .dw 0x51c0, 0xc98c, 0x51ff, 0xc98c, 0x21, 0 + .dw 0x5240, 0xc98c, 0x527f, 0xc98c, 0x21, 0 + .dw 0x52c0, 0xc98c, 0x52ff, 0xc98c, 0x21, 0 + .dw 0x5340, 0xc98c, 0x537f, 0xc98c, 0x21, 0 + .dw 0x53c0, 0xc98c, 0x53ff, 0xc98c, 0x21, 0 + .dw 0x5440, 0xc98c, 0x547f, 0xc98c, 0x21, 0 + .dw 0x54c0, 0xc98c, 0x54ff, 0xc98c, 0x21, 0 + .dw 0x5540, 0xc98c, 0x557f, 0xc98c, 0x21, 0 + .dw 0x55c0, 0xc98c, 0x55ff, 0xc98c, 0x21, 0 + .dw 0x5640, 0xc98c, 0x567f, 0xc98c, 0x21, 0 + .dw 0x56c0, 0xc98c, 0x56ff, 0xc98c, 0x21, 0 + .dw 0x5740, 0xc98c, 0x577f, 0xc98c, 0x21, 0 + .dw 0x57c0, 0xc98c, 0x57ff, 0xc98c, 0x21, 0 + .dw 0x5840, 0xc98c, 0x587f, 0xc98c, 0x21, 0 + .dw 0x58c0, 0xc98c, 0x58ff, 0xc98c, 0x21, 0 + .dw 0x5940, 0xc98c, 0x597f, 0xc98c, 0x21, 0 + .dw 0x59c0, 0xc98c, 0x5fff, 0xc98c, 0x21, 0 + .dw 0x6040, 0xc98c, 0x607f, 0xc98c, 0x21, 0 + .dw 0x60c0, 0xc98c, 0x60ff, 0xc98c, 0x21, 0 + .dw 0x6140, 0xc98c, 0x617f, 0xc98c, 0x21, 0 + .dw 0x61c0, 0xc98c, 0x61ff, 0xc98c, 0x21, 0 + .dw 0x6240, 0xc98c, 0x627f, 0xc98c, 0x21, 0 + .dw 0x62c0, 0xc98c, 0x62ff, 0xc98c, 0x21, 0 + .dw 0x6340, 0xc98c, 0x637f, 0xc98c, 0x21, 0 + .dw 0x63c0, 0xc98c, 0x63ff, 0xc98c, 0x21, 0 + .dw 0x6440, 0xc98c, 0x647f, 0xc98c, 0x21, 0 + .dw 0x64c0, 0xc98c, 0x64ff, 0xc98c, 0x21, 0 + .dw 0x6540, 0xc98c, 0x657f, 0xc98c, 0x21, 0 + .dw 0x65c0, 0xc98c, 0x65ff, 0xc98c, 0x21, 0 + .dw 0x6640, 0xc98c, 0x667f, 0xc98c, 0x21, 0 + .dw 0x66c0, 0xc98c, 0x66ff, 0xc98c, 0x21, 0 + .dw 0x6740, 0xc98c, 0x677f, 0xc98c, 0x21, 0 + .dw 0x67c0, 0xc98c, 0x67ff, 0xc98c, 0x21, 0 + .dw 0x6840, 0xc98c, 0x687f, 0xc98c, 0x21, 0 + .dw 0x68c0, 0xc98c, 0x68ff, 0xc98c, 0x21, 0 + .dw 0x6940, 0xc98c, 0x697f, 0xc98c, 0x21, 0 + .dw 0x69c0, 0xc98c, 0x69ff, 0xc98c, 0x21, 0 + .dw 0x6a40, 0xc98c, 0x6a7f, 0xc98c, 0x21, 0 + .dw 0x6ac0, 0xc98c, 0x6aff, 0xc98c, 0x21, 0 + .dw 0x6b40, 0xc98c, 0x6b7f, 0xc98c, 0x21, 0 + .dw 0x6bc0, 0xc98c, 0x6bff, 0xc98c, 0x21, 0 + .dw 0x6c40, 0xc98c, 0x6c7f, 0xc98c, 0x21, 0 + .dw 0x6cc0, 0xc98c, 0x6cff, 0xc98c, 0x21, 0 + .dw 0x6d40, 0xc98c, 0x6d7f, 0xc98c, 0x21, 0 + .dw 0x6dc0, 0xc98c, 0x6dff, 0xc98c, 0x21, 0 + .dw 0x6e40, 0xc98c, 0x6e7f, 0xc98c, 0x21, 0 + .dw 0x6ec0, 0xc98c, 0x6eff, 0xc98c, 0x21, 0 + .dw 0x6f40, 0xc98c, 0x6f7f, 0xc98c, 0x21, 0 + .dw 0x6fc0, 0xc98c, 0x6fff, 0xc98c, 0x21, 0 + .dw 0x7040, 0xc98c, 0x707f, 0xc98c, 0x21, 0 + .dw 0x70c0, 0xc98c, 0x70ff, 0xc98c, 0x21, 0 + .dw 0x7140, 0xc98c, 0x717f, 0xc98c, 0x21, 0 + .dw 0x71c0, 0xc98c, 0x71ff, 0xc98c, 0x21, 0 + .dw 0x7240, 0xc98c, 0x727f, 0xc98c, 0x21, 0 + .dw 0x72c0, 0xc98c, 0x72ff, 0xc98c, 0x21, 0 + .dw 0x7340, 0xc98c, 0x737f, 0xc98c, 0x21, 0 + .dw 0x73c0, 0xc98c, 0x73ff, 0xc98c, 0x21, 0 + .dw 0x7440, 0xc98c, 0x747f, 0xc98c, 0x21, 0 + .dw 0x74c0, 0xc98c, 0x74ff, 0xc98c, 0x21, 0 + .dw 0x7540, 0xc98c, 0x757f, 0xc98c, 0x21, 0 + .dw 0x75c0, 0xc98c, 0x75ff, 0xc98c, 0x21, 0 + .dw 0x7640, 0xc98c, 0x767f, 0xc98c, 0x21, 0 + .dw 0x76c0, 0xc98c, 0x76ff, 0xc98c, 0x21, 0 + .dw 0x7740, 0xc98c, 0x777f, 0xc98c, 0x21, 0 + .dw 0x77c0, 0xc98c, 0x77ff, 0xc98c, 0x21, 0 + .dw 0x7840, 0xc98c, 0x787f, 0xc98c, 0x21, 0 + .dw 0x78c0, 0xc98c, 0x78ff, 0xc98c, 0x21, 0 + .dw 0x7940, 0xc98c, 0x797f, 0xc98c, 0x21, 0 + .dw 0x79c0, 0xc98c, 0x7fff, 0xc98c, 0x21, 0 + .dw 0x8040, 0xc98c, 0x807f, 0xc98c, 0x21, 0 + .dw 0x80c0, 0xc98c, 0x80ff, 0xc98c, 0x21, 0 + .dw 0x8140, 0xc98c, 0x817f, 0xc98c, 0x21, 0 + .dw 0x81c0, 0xc98c, 0x81ff, 0xc98c, 0x21, 0 + .dw 0x8240, 0xc98c, 0x827f, 0xc98c, 0x21, 0 + .dw 0x82c0, 0xc98c, 0x82ff, 0xc98c, 0x21, 0 + .dw 0x8340, 0xc98c, 0x837f, 0xc98c, 0x21, 0 + .dw 0x83c0, 0xc98c, 0x83ff, 0xc98c, 0x21, 0 + .dw 0x8440, 0xc98c, 0x847f, 0xc98c, 0x21, 0 + .dw 0x84c0, 0xc98c, 0x84ff, 0xc98c, 0x21, 0 + .dw 0x8540, 0xc98c, 0x857f, 0xc98c, 0x21, 0 + .dw 0x85c0, 0xc98c, 0x85ff, 0xc98c, 0x21, 0 + .dw 0x8640, 0xc98c, 0x867f, 0xc98c, 0x21, 0 + .dw 0x86c0, 0xc98c, 0x86ff, 0xc98c, 0x21, 0 + .dw 0x8740, 0xc98c, 0x877f, 0xc98c, 0x21, 0 + .dw 0x87c0, 0xc98c, 0x87ff, 0xc98c, 0x21, 0 + .dw 0x8840, 0xc98c, 0x887f, 0xc98c, 0x21, 0 + .dw 0x88c0, 0xc98c, 0x88ff, 0xc98c, 0x21, 0 + .dw 0x8940, 0xc98c, 0x897f, 0xc98c, 0x21, 0 + .dw 0x89c0, 0xc98c, 0x89ff, 0xc98c, 0x21, 0 + .dw 0x8a40, 0xc98c, 0x8a7f, 0xc98c, 0x21, 0 + .dw 0x8ac0, 0xc98c, 0x8aff, 0xc98c, 0x21, 0 + .dw 0x8b40, 0xc98c, 0x8b7f, 0xc98c, 0x21, 0 + .dw 0x8bc0, 0xc98c, 0x8bff, 0xc98c, 0x21, 0 + .dw 0x8c40, 0xc98c, 0x8c7f, 0xc98c, 0x21, 0 + .dw 0x8cc0, 0xc98c, 0x8cff, 0xc98c, 0x21, 0 + .dw 0x8d40, 0xc98c, 0x8d7f, 0xc98c, 0x21, 0 + .dw 0x8dc0, 0xc98c, 0x8dff, 0xc98c, 0x21, 0 + .dw 0x8e40, 0xc98c, 0x8e7f, 0xc98c, 0x21, 0 + .dw 0x8ec0, 0xc98c, 0x8eff, 0xc98c, 0x21, 0 + .dw 0x8f40, 0xc98c, 0x8f7f, 0xc98c, 0x21, 0 + .dw 0x8fc0, 0xc98c, 0x8fff, 0xc98c, 0x21, 0 + .dw 0x9040, 0xc98c, 0x907f, 0xc98c, 0x21, 0 + .dw 0x90c0, 0xc98c, 0x90ff, 0xc98c, 0x21, 0 + .dw 0x9140, 0xc98c, 0x917f, 0xc98c, 0x21, 0 + .dw 0x91c0, 0xc98c, 0x91ff, 0xc98c, 0x21, 0 + .dw 0x9240, 0xc98c, 0x927f, 0xc98c, 0x21, 0 + .dw 0x92c0, 0xc98c, 0x92ff, 0xc98c, 0x21, 0 + .dw 0x9340, 0xc98c, 0x937f, 0xc98c, 0x21, 0 + .dw 0x93c0, 0xc98c, 0x93ff, 0xc98c, 0x21, 0 + .dw 0x9440, 0xc98c, 0x947f, 0xc98c, 0x21, 0 + .dw 0x94c0, 0xc98c, 0x94ff, 0xc98c, 0x21, 0 + .dw 0x9540, 0xc98c, 0x957f, 0xc98c, 0x21, 0 + .dw 0x95c0, 0xc98c, 0x95ff, 0xc98c, 0x21, 0 + .dw 0x9640, 0xc98c, 0x967f, 0xc98c, 0x21, 0 + .dw 0x96c0, 0xc98c, 0x96ff, 0xc98c, 0x21, 0 + .dw 0x9740, 0xc98c, 0x977f, 0xc98c, 0x21, 0 + .dw 0x97c0, 0xc98c, 0x97ff, 0xc98c, 0x21, 0 + .dw 0x9840, 0xc98c, 0x987f, 0xc98c, 0x21, 0 + .dw 0x98c0, 0xc98c, 0x98ff, 0xc98c, 0x21, 0 + .dw 0x9940, 0xc98c, 0x997f, 0xc98c, 0x21, 0 + .dw 0x99c0, 0xc98c, 0x9fff, 0xc98c, 0x21, 0 + .dw 0xa040, 0xc98c, 0xa07f, 0xc98c, 0x21, 0 + .dw 0xa0c0, 0xc98c, 0xa0ff, 0xc98c, 0x21, 0 + .dw 0xa140, 0xc98c, 0xa17f, 0xc98c, 0x21, 0 + .dw 0xa1c0, 0xc98c, 0xa1ff, 0xc98c, 0x21, 0 + .dw 0xa240, 0xc98c, 0xa27f, 0xc98c, 0x21, 0 + .dw 0xa2c0, 0xc98c, 0xa2ff, 0xc98c, 0x21, 0 + .dw 0xa340, 0xc98c, 0xa37f, 0xc98c, 0x21, 0 + .dw 0xa3c0, 0xc98c, 0xa3ff, 0xc98c, 0x21, 0 + .dw 0xa440, 0xc98c, 0xa47f, 0xc98c, 0x21, 0 + .dw 0xa4c0, 0xc98c, 0xa4ff, 0xc98c, 0x21, 0 + .dw 0xa540, 0xc98c, 0xa57f, 0xc98c, 0x21, 0 + .dw 0xa5c0, 0xc98c, 0xa5ff, 0xc98c, 0x21, 0 + .dw 0xa640, 0xc98c, 0xa67f, 0xc98c, 0x21, 0 + .dw 0xa6c0, 0xc98c, 0xa6ff, 0xc98c, 0x21, 0 + .dw 0xa740, 0xc98c, 0xa77f, 0xc98c, 0x21, 0 + .dw 0xa7c0, 0xc98c, 0xa7ff, 0xc98c, 0x21, 0 + .dw 0xa840, 0xc98c, 0xa87f, 0xc98c, 0x21, 0 + .dw 0xa8c0, 0xc98c, 0xa8ff, 0xc98c, 0x21, 0 + .dw 0xa940, 0xc98c, 0xa97f, 0xc98c, 0x21, 0 + .dw 0xa9c0, 0xc98c, 0xa9ff, 0xc98c, 0x21, 0 + .dw 0xaa40, 0xc98c, 0xaa7f, 0xc98c, 0x21, 0 + .dw 0xaac0, 0xc98c, 0xaaff, 0xc98c, 0x21, 0 + .dw 0xab40, 0xc98c, 0xab7f, 0xc98c, 0x21, 0 + .dw 0xabc0, 0xc98c, 0xabff, 0xc98c, 0x21, 0 + .dw 0xac40, 0xc98c, 0xac7f, 0xc98c, 0x21, 0 + .dw 0xacc0, 0xc98c, 0xacff, 0xc98c, 0x21, 0 + .dw 0xad40, 0xc98c, 0xad7f, 0xc98c, 0x21, 0 + .dw 0xadc0, 0xc98c, 0xadff, 0xc98c, 0x21, 0 + .dw 0xae40, 0xc98c, 0xae7f, 0xc98c, 0x21, 0 + .dw 0xaec0, 0xc98c, 0xaeff, 0xc98c, 0x21, 0 + .dw 0xaf40, 0xc98c, 0xaf7f, 0xc98c, 0x21, 0 + .dw 0xafc0, 0xc98c, 0xafff, 0xc98c, 0x21, 0 + .dw 0xb040, 0xc98c, 0xb07f, 0xc98c, 0x21, 0 + .dw 0xb0c0, 0xc98c, 0xb0ff, 0xc98c, 0x21, 0 + .dw 0xb140, 0xc98c, 0xb17f, 0xc98c, 0x21, 0 + .dw 0xb1c0, 0xc98c, 0xb1ff, 0xc98c, 0x21, 0 + .dw 0xb240, 0xc98c, 0xb27f, 0xc98c, 0x21, 0 + .dw 0xb2c0, 0xc98c, 0xb2ff, 0xc98c, 0x21, 0 + .dw 0xb340, 0xc98c, 0xb37f, 0xc98c, 0x21, 0 + .dw 0xb3c0, 0xc98c, 0xb3ff, 0xc98c, 0x21, 0 + .dw 0xb440, 0xc98c, 0xb47f, 0xc98c, 0x21, 0 + .dw 0xb4c0, 0xc98c, 0xb4ff, 0xc98c, 0x21, 0 + .dw 0xb540, 0xc98c, 0xb57f, 0xc98c, 0x21, 0 + .dw 0xb5c0, 0xc98c, 0xb5ff, 0xc98c, 0x21, 0 + .dw 0xb640, 0xc98c, 0xb67f, 0xc98c, 0x21, 0 + .dw 0xb6c0, 0xc98c, 0xb6ff, 0xc98c, 0x21, 0 + .dw 0xb740, 0xc98c, 0xb77f, 0xc98c, 0x21, 0 + .dw 0xb7c0, 0xc98c, 0xb7ff, 0xc98c, 0x21, 0 + .dw 0xb840, 0xc98c, 0xb87f, 0xc98c, 0x21, 0 + .dw 0xb8c0, 0xc98c, 0xb8ff, 0xc98c, 0x21, 0 + .dw 0xb940, 0xc98c, 0xb97f, 0xc98c, 0x21, 0 + .dw 0xb9c0, 0xc98c, 0xbfff, 0xc98c, 0x21, 0 + .dw 0xc040, 0xc98c, 0xc07f, 0xc98c, 0x21, 0 + .dw 0xc0c0, 0xc98c, 0xc0ff, 0xc98c, 0x21, 0 + .dw 0xc140, 0xc98c, 0xc17f, 0xc98c, 0x21, 0 + .dw 0xc1c0, 0xc98c, 0xc1ff, 0xc98c, 0x21, 0 + .dw 0xc240, 0xc98c, 0xc27f, 0xc98c, 0x21, 0 + .dw 0xc2c0, 0xc98c, 0xc2ff, 0xc98c, 0x21, 0 + .dw 0xc340, 0xc98c, 0xc37f, 0xc98c, 0x21, 0 + .dw 0xc3c0, 0xc98c, 0xc3ff, 0xc98c, 0x21, 0 + .dw 0xc440, 0xc98c, 0xc47f, 0xc98c, 0x21, 0 + .dw 0xc4c0, 0xc98c, 0xc4ff, 0xc98c, 0x21, 0 + .dw 0xc540, 0xc98c, 0xc57f, 0xc98c, 0x21, 0 + .dw 0xc5c0, 0xc98c, 0xc5ff, 0xc98c, 0x21, 0 + .dw 0xc640, 0xc98c, 0xc67f, 0xc98c, 0x21, 0 + .dw 0xc6c0, 0xc98c, 0xc6ff, 0xc98c, 0x21, 0 + .dw 0xc740, 0xc98c, 0xc77f, 0xc98c, 0x21, 0 + .dw 0xc7c0, 0xc98c, 0xc7ff, 0xc98c, 0x21, 0 + .dw 0xc840, 0xc98c, 0xc87f, 0xc98c, 0x21, 0 + .dw 0xc8c0, 0xc98c, 0xc8ff, 0xc98c, 0x21, 0 + .dw 0xc940, 0xc98c, 0xc97f, 0xc98c, 0x21, 0 + .dw 0xc9c0, 0xc98c, 0xc9ff, 0xc98c, 0x21, 0 + .dw 0xca40, 0xc98c, 0xca7f, 0xc98c, 0x21, 0 + .dw 0xcac0, 0xc98c, 0xcaff, 0xc98c, 0x21, 0 + .dw 0xcb40, 0xc98c, 0xcb7f, 0xc98c, 0x21, 0 + .dw 0xcbc0, 0xc98c, 0xcbff, 0xc98c, 0x21, 0 + .dw 0xcc40, 0xc98c, 0xcc7f, 0xc98c, 0x21, 0 + .dw 0xccc0, 0xc98c, 0xccff, 0xc98c, 0x21, 0 + .dw 0xcd40, 0xc98c, 0xcd7f, 0xc98c, 0x21, 0 + .dw 0xcdc0, 0xc98c, 0xcdff, 0xc98c, 0x21, 0 + .dw 0xce40, 0xc98c, 0xce7f, 0xc98c, 0x21, 0 + .dw 0xcec0, 0xc98c, 0xceff, 0xc98c, 0x21, 0 + .dw 0xcf40, 0xc98c, 0xcf7f, 0xc98c, 0x21, 0 + .dw 0xcfc0, 0xc98c, 0xcfff, 0xc98c, 0x21, 0 + .dw 0xd040, 0xc98c, 0xd07f, 0xc98c, 0x21, 0 + .dw 0xd0c0, 0xc98c, 0xd0ff, 0xc98c, 0x21, 0 + .dw 0xd140, 0xc98c, 0xd17f, 0xc98c, 0x21, 0 + .dw 0xd1c0, 0xc98c, 0xd1ff, 0xc98c, 0x21, 0 + .dw 0xd240, 0xc98c, 0xd27f, 0xc98c, 0x21, 0 + .dw 0xd2c0, 0xc98c, 0xd2ff, 0xc98c, 0x21, 0 + .dw 0xd340, 0xc98c, 0xd37f, 0xc98c, 0x21, 0 + .dw 0xd3c0, 0xc98c, 0xd3ff, 0xc98c, 0x21, 0 + .dw 0xd440, 0xc98c, 0xd47f, 0xc98c, 0x21, 0 + .dw 0xd4c0, 0xc98c, 0xd4ff, 0xc98c, 0x21, 0 + .dw 0xd540, 0xc98c, 0xd57f, 0xc98c, 0x21, 0 + .dw 0xd5c0, 0xc98c, 0xd5ff, 0xc98c, 0x21, 0 + .dw 0xd640, 0xc98c, 0xd67f, 0xc98c, 0x21, 0 + .dw 0xd6c0, 0xc98c, 0xd6ff, 0xc98c, 0x21, 0 + .dw 0xd740, 0xc98c, 0xd77f, 0xc98c, 0x21, 0 + .dw 0xd7c0, 0xc98c, 0xd7ff, 0xc98c, 0x21, 0 + .dw 0xd840, 0xc98c, 0xd87f, 0xc98c, 0x21, 0 + .dw 0xd8c0, 0xc98c, 0xd8ff, 0xc98c, 0x21, 0 + .dw 0xd940, 0xc98c, 0xd97f, 0xc98c, 0x21, 0 + .dw 0xd9c0, 0xc98c, 0xdfff, 0xc98c, 0x21, 0 + .dw 0xe040, 0xc98c, 0xe07f, 0xc98c, 0x21, 0 + .dw 0xe0c0, 0xc98c, 0xe0ff, 0xc98c, 0x21, 0 + .dw 0xe140, 0xc98c, 0xe17f, 0xc98c, 0x21, 0 + .dw 0xe1c0, 0xc98c, 0xe1ff, 0xc98c, 0x21, 0 + .dw 0xe240, 0xc98c, 0xe27f, 0xc98c, 0x21, 0 + .dw 0xe2c0, 0xc98c, 0xe2ff, 0xc98c, 0x21, 0 + .dw 0xe340, 0xc98c, 0xe37f, 0xc98c, 0x21, 0 + .dw 0xe3c0, 0xc98c, 0xe3ff, 0xc98c, 0x21, 0 + .dw 0xe440, 0xc98c, 0xe47f, 0xc98c, 0x21, 0 + .dw 0xe4c0, 0xc98c, 0xe4ff, 0xc98c, 0x21, 0 + .dw 0xe540, 0xc98c, 0xe57f, 0xc98c, 0x21, 0 + .dw 0xe5c0, 0xc98c, 0xe5ff, 0xc98c, 0x21, 0 + .dw 0xe640, 0xc98c, 0xe67f, 0xc98c, 0x21, 0 + .dw 0xe6c0, 0xc98c, 0xe6ff, 0xc98c, 0x21, 0 + .dw 0xe740, 0xc98c, 0xe77f, 0xc98c, 0x21, 0 + .dw 0xe7c0, 0xc98c, 0xe7ff, 0xc98c, 0x21, 0 + .dw 0xe840, 0xc98c, 0xe87f, 0xc98c, 0x21, 0 + .dw 0xe8c0, 0xc98c, 0xe8ff, 0xc98c, 0x21, 0 + .dw 0xe940, 0xc98c, 0xe97f, 0xc98c, 0x21, 0 + .dw 0xe9c0, 0xc98c, 0xe9ff, 0xc98c, 0x21, 0 + .dw 0xea40, 0xc98c, 0xea7f, 0xc98c, 0x21, 0 + .dw 0xeac0, 0xc98c, 0xeaff, 0xc98c, 0x21, 0 + .dw 0xeb40, 0xc98c, 0xeb7f, 0xc98c, 0x21, 0 + .dw 0xebc0, 0xc98c, 0xebff, 0xc98c, 0x21, 0 + .dw 0xec40, 0xc98c, 0xec7f, 0xc98c, 0x21, 0 + .dw 0xecc0, 0xc98c, 0xecff, 0xc98c, 0x21, 0 + .dw 0xed40, 0xc98c, 0xed7f, 0xc98c, 0x21, 0 + .dw 0xedc0, 0xc98c, 0xedff, 0xc98c, 0x21, 0 + .dw 0xee40, 0xc98c, 0xee7f, 0xc98c, 0x21, 0 + .dw 0xeec0, 0xc98c, 0xeeff, 0xc98c, 0x21, 0 + .dw 0xef40, 0xc98c, 0xef7f, 0xc98c, 0x21, 0 + .dw 0xefc0, 0xc98c, 0xefff, 0xc98c, 0x21, 0 + .dw 0xf040, 0xc98c, 0xf07f, 0xc98c, 0x21, 0 + .dw 0xf0c0, 0xc98c, 0xf0ff, 0xc98c, 0x21, 0 + .dw 0xf140, 0xc98c, 0xf17f, 0xc98c, 0x21, 0 + .dw 0xf1c0, 0xc98c, 0xf1ff, 0xc98c, 0x21, 0 + .dw 0xf240, 0xc98c, 0xf27f, 0xc98c, 0x21, 0 + .dw 0xf2c0, 0xc98c, 0xf2ff, 0xc98c, 0x21, 0 + .dw 0xf340, 0xc98c, 0xf37f, 0xc98c, 0x21, 0 + .dw 0xf3c0, 0xc98c, 0xf3ff, 0xc98c, 0x21, 0 + .dw 0xf440, 0xc98c, 0xf47f, 0xc98c, 0x21, 0 + .dw 0xf4c0, 0xc98c, 0xf4ff, 0xc98c, 0x21, 0 + .dw 0xf540, 0xc98c, 0xf57f, 0xc98c, 0x21, 0 + .dw 0xf5c0, 0xc98c, 0xf5ff, 0xc98c, 0x21, 0 + .dw 0xf640, 0xc98c, 0xf67f, 0xc98c, 0x21, 0 + .dw 0xf6c0, 0xc98c, 0xf6ff, 0xc98c, 0x21, 0 + .dw 0xf740, 0xc98c, 0xf77f, 0xc98c, 0x21, 0 + .dw 0xf7c0, 0xc98c, 0xf7ff, 0xc98c, 0x21, 0 + .dw 0xf840, 0xc98c, 0xf87f, 0xc98c, 0x21, 0 + .dw 0xf8c0, 0xc98c, 0xf8ff, 0xc98c, 0x21, 0 + .dw 0xf940, 0xc98c, 0xf97f, 0xc98c, 0x21, 0 + .dw 0xf9c0, 0xc98c, 0xffff, 0xc98c, 0x21, 0 + .dw 0x0040, 0xc98d, 0x007f, 0xc98d, 0x21, 0 + .dw 0x00c0, 0xc98d, 0x00ff, 0xc98d, 0x21, 0 + .dw 0x0140, 0xc98d, 0x017f, 0xc98d, 0x21, 0 + .dw 0x01c0, 0xc98d, 0x01ff, 0xc98d, 0x21, 0 + .dw 0x0240, 0xc98d, 0x027f, 0xc98d, 0x21, 0 + .dw 0x02c0, 0xc98d, 0x02ff, 0xc98d, 0x21, 0 + .dw 0x0340, 0xc98d, 0x037f, 0xc98d, 0x21, 0 + .dw 0x03c0, 0xc98d, 0x03ff, 0xc98d, 0x21, 0 + .dw 0x0440, 0xc98d, 0x047f, 0xc98d, 0x21, 0 + .dw 0x04c0, 0xc98d, 0x04ff, 0xc98d, 0x21, 0 + .dw 0x0540, 0xc98d, 0x057f, 0xc98d, 0x21, 0 + .dw 0x05c0, 0xc98d, 0x05ff, 0xc98d, 0x21, 0 + .dw 0x0640, 0xc98d, 0x067f, 0xc98d, 0x21, 0 + .dw 0x06c0, 0xc98d, 0x06ff, 0xc98d, 0x21, 0 + .dw 0x0740, 0xc98d, 0x077f, 0xc98d, 0x21, 0 + .dw 0x07c0, 0xc98d, 0x07ff, 0xc98d, 0x21, 0 + .dw 0x0840, 0xc98d, 0x087f, 0xc98d, 0x21, 0 + .dw 0x08c0, 0xc98d, 0x08ff, 0xc98d, 0x21, 0 + .dw 0x0940, 0xc98d, 0x097f, 0xc98d, 0x21, 0 + .dw 0x09c0, 0xc98d, 0x09ff, 0xc98d, 0x21, 0 + .dw 0x0a40, 0xc98d, 0x0a7f, 0xc98d, 0x21, 0 + .dw 0x0ac0, 0xc98d, 0x0aff, 0xc98d, 0x21, 0 + .dw 0x0b40, 0xc98d, 0x0b7f, 0xc98d, 0x21, 0 + .dw 0x0bc0, 0xc98d, 0x0bff, 0xc98d, 0x21, 0 + .dw 0x0c40, 0xc98d, 0x0c7f, 0xc98d, 0x21, 0 + .dw 0x0cc0, 0xc98d, 0x0cff, 0xc98d, 0x21, 0 + .dw 0x0d40, 0xc98d, 0x0d7f, 0xc98d, 0x21, 0 + .dw 0x0dc0, 0xc98d, 0x0dff, 0xc98d, 0x21, 0 + .dw 0x0e40, 0xc98d, 0x0e7f, 0xc98d, 0x21, 0 + .dw 0x0ec0, 0xc98d, 0x0eff, 0xc98d, 0x21, 0 + .dw 0x0f40, 0xc98d, 0x0f7f, 0xc98d, 0x21, 0 + .dw 0x0fc0, 0xc98d, 0x0fff, 0xc98d, 0x21, 0 + .dw 0x1040, 0xc98d, 0x107f, 0xc98d, 0x21, 0 + .dw 0x10c0, 0xc98d, 0x10ff, 0xc98d, 0x21, 0 + .dw 0x1140, 0xc98d, 0x117f, 0xc98d, 0x21, 0 + .dw 0x11c0, 0xc98d, 0x11ff, 0xc98d, 0x21, 0 + .dw 0x1240, 0xc98d, 0x127f, 0xc98d, 0x21, 0 + .dw 0x12c0, 0xc98d, 0x12ff, 0xc98d, 0x21, 0 + .dw 0x1340, 0xc98d, 0x137f, 0xc98d, 0x21, 0 + .dw 0x13c0, 0xc98d, 0x13ff, 0xc98d, 0x21, 0 + .dw 0x1440, 0xc98d, 0x147f, 0xc98d, 0x21, 0 + .dw 0x14c0, 0xc98d, 0x14ff, 0xc98d, 0x21, 0 + .dw 0x1540, 0xc98d, 0x157f, 0xc98d, 0x21, 0 + .dw 0x15c0, 0xc98d, 0x15ff, 0xc98d, 0x21, 0 + .dw 0x1640, 0xc98d, 0x167f, 0xc98d, 0x21, 0 + .dw 0x16c0, 0xc98d, 0x16ff, 0xc98d, 0x21, 0 + .dw 0x1740, 0xc98d, 0x177f, 0xc98d, 0x21, 0 + .dw 0x17c0, 0xc98d, 0x17ff, 0xc98d, 0x21, 0 + .dw 0x1840, 0xc98d, 0x187f, 0xc98d, 0x21, 0 + .dw 0x18c0, 0xc98d, 0x18ff, 0xc98d, 0x21, 0 + .dw 0x1940, 0xc98d, 0x197f, 0xc98d, 0x21, 0 + .dw 0x19c0, 0xc98d, 0x1fff, 0xc98d, 0x21, 0 + .dw 0x2040, 0xc98d, 0x207f, 0xc98d, 0x21, 0 + .dw 0x20c0, 0xc98d, 0x20ff, 0xc98d, 0x21, 0 + .dw 0x2140, 0xc98d, 0x217f, 0xc98d, 0x21, 0 + .dw 0x21c0, 0xc98d, 0x21ff, 0xc98d, 0x21, 0 + .dw 0x2240, 0xc98d, 0x227f, 0xc98d, 0x21, 0 + .dw 0x22c0, 0xc98d, 0x22ff, 0xc98d, 0x21, 0 + .dw 0x2340, 0xc98d, 0x237f, 0xc98d, 0x21, 0 + .dw 0x23c0, 0xc98d, 0x23ff, 0xc98d, 0x21, 0 + .dw 0x2440, 0xc98d, 0x247f, 0xc98d, 0x21, 0 + .dw 0x24c0, 0xc98d, 0x24ff, 0xc98d, 0x21, 0 + .dw 0x2540, 0xc98d, 0x257f, 0xc98d, 0x21, 0 + .dw 0x25c0, 0xc98d, 0x25ff, 0xc98d, 0x21, 0 + .dw 0x2640, 0xc98d, 0x267f, 0xc98d, 0x21, 0 + .dw 0x26c0, 0xc98d, 0x26ff, 0xc98d, 0x21, 0 + .dw 0x2740, 0xc98d, 0x277f, 0xc98d, 0x21, 0 + .dw 0x27c0, 0xc98d, 0x27ff, 0xc98d, 0x21, 0 + .dw 0x2840, 0xc98d, 0x287f, 0xc98d, 0x21, 0 + .dw 0x28c0, 0xc98d, 0x28ff, 0xc98d, 0x21, 0 + .dw 0x2940, 0xc98d, 0x297f, 0xc98d, 0x21, 0 + .dw 0x29c0, 0xc98d, 0x29ff, 0xc98d, 0x21, 0 + .dw 0x2a40, 0xc98d, 0x2a7f, 0xc98d, 0x21, 0 + .dw 0x2ac0, 0xc98d, 0x2aff, 0xc98d, 0x21, 0 + .dw 0x2b40, 0xc98d, 0x2b7f, 0xc98d, 0x21, 0 + .dw 0x2bc0, 0xc98d, 0x2bff, 0xc98d, 0x21, 0 + .dw 0x2c40, 0xc98d, 0x2c7f, 0xc98d, 0x21, 0 + .dw 0x2cc0, 0xc98d, 0x2cff, 0xc98d, 0x21, 0 + .dw 0x2d40, 0xc98d, 0x2d7f, 0xc98d, 0x21, 0 + .dw 0x2dc0, 0xc98d, 0x2dff, 0xc98d, 0x21, 0 + .dw 0x2e40, 0xc98d, 0x2e7f, 0xc98d, 0x21, 0 + .dw 0x2ec0, 0xc98d, 0x2eff, 0xc98d, 0x21, 0 + .dw 0x2f40, 0xc98d, 0x2f7f, 0xc98d, 0x21, 0 + .dw 0x2fc0, 0xc98d, 0x2fff, 0xc98d, 0x21, 0 + .dw 0x3040, 0xc98d, 0x307f, 0xc98d, 0x21, 0 + .dw 0x30c0, 0xc98d, 0x30ff, 0xc98d, 0x21, 0 + .dw 0x3140, 0xc98d, 0x317f, 0xc98d, 0x21, 0 + .dw 0x31c0, 0xc98d, 0x31ff, 0xc98d, 0x21, 0 + .dw 0x3240, 0xc98d, 0x327f, 0xc98d, 0x21, 0 + .dw 0x32c0, 0xc98d, 0x32ff, 0xc98d, 0x21, 0 + .dw 0x3340, 0xc98d, 0x337f, 0xc98d, 0x21, 0 + .dw 0x33c0, 0xc98d, 0x33ff, 0xc98d, 0x21, 0 + .dw 0x3440, 0xc98d, 0x347f, 0xc98d, 0x21, 0 + .dw 0x34c0, 0xc98d, 0x34ff, 0xc98d, 0x21, 0 + .dw 0x3540, 0xc98d, 0x357f, 0xc98d, 0x21, 0 + .dw 0x35c0, 0xc98d, 0x35ff, 0xc98d, 0x21, 0 + .dw 0x3640, 0xc98d, 0x367f, 0xc98d, 0x21, 0 + .dw 0x36c0, 0xc98d, 0x36ff, 0xc98d, 0x21, 0 + .dw 0x3740, 0xc98d, 0x377f, 0xc98d, 0x21, 0 + .dw 0x37c0, 0xc98d, 0x37ff, 0xc98d, 0x21, 0 + .dw 0x3840, 0xc98d, 0x387f, 0xc98d, 0x21, 0 + .dw 0x38c0, 0xc98d, 0x38ff, 0xc98d, 0x21, 0 + .dw 0x3940, 0xc98d, 0x397f, 0xc98d, 0x21, 0 + .dw 0x39c0, 0xc98d, 0x3fff, 0xc98d, 0x21, 0 + .dw 0x4040, 0xc98d, 0x407f, 0xc98d, 0x21, 0 + .dw 0x40c0, 0xc98d, 0x40ff, 0xc98d, 0x21, 0 + .dw 0x4140, 0xc98d, 0x417f, 0xc98d, 0x21, 0 + .dw 0x41c0, 0xc98d, 0x41ff, 0xc98d, 0x21, 0 + .dw 0x4240, 0xc98d, 0x427f, 0xc98d, 0x21, 0 + .dw 0x42c0, 0xc98d, 0x42ff, 0xc98d, 0x21, 0 + .dw 0x4340, 0xc98d, 0x437f, 0xc98d, 0x21, 0 + .dw 0x43c0, 0xc98d, 0x43ff, 0xc98d, 0x21, 0 + .dw 0x4440, 0xc98d, 0x447f, 0xc98d, 0x21, 0 + .dw 0x44c0, 0xc98d, 0x44ff, 0xc98d, 0x21, 0 + .dw 0x4540, 0xc98d, 0x457f, 0xc98d, 0x21, 0 + .dw 0x45c0, 0xc98d, 0x45ff, 0xc98d, 0x21, 0 + .dw 0x4640, 0xc98d, 0x467f, 0xc98d, 0x21, 0 + .dw 0x46c0, 0xc98d, 0x46ff, 0xc98d, 0x21, 0 + .dw 0x4740, 0xc98d, 0x477f, 0xc98d, 0x21, 0 + .dw 0x47c0, 0xc98d, 0x47ff, 0xc98d, 0x21, 0 + .dw 0x4840, 0xc98d, 0x487f, 0xc98d, 0x21, 0 + .dw 0x48c0, 0xc98d, 0x48ff, 0xc98d, 0x21, 0 + .dw 0x4940, 0xc98d, 0x497f, 0xc98d, 0x21, 0 + .dw 0x49c0, 0xc98d, 0x49ff, 0xc98d, 0x21, 0 + .dw 0x4a40, 0xc98d, 0x4a7f, 0xc98d, 0x21, 0 + .dw 0x4ac0, 0xc98d, 0x4aff, 0xc98d, 0x21, 0 + .dw 0x4b40, 0xc98d, 0x4b7f, 0xc98d, 0x21, 0 + .dw 0x4bc0, 0xc98d, 0x4bff, 0xc98d, 0x21, 0 + .dw 0x4c40, 0xc98d, 0x4c7f, 0xc98d, 0x21, 0 + .dw 0x4cc0, 0xc98d, 0x4cff, 0xc98d, 0x21, 0 + .dw 0x4d40, 0xc98d, 0x4d7f, 0xc98d, 0x21, 0 + .dw 0x4dc0, 0xc98d, 0x4dff, 0xc98d, 0x21, 0 + .dw 0x4e40, 0xc98d, 0x4e7f, 0xc98d, 0x21, 0 + .dw 0x4ec0, 0xc98d, 0x4eff, 0xc98d, 0x21, 0 + .dw 0x4f40, 0xc98d, 0x4f7f, 0xc98d, 0x21, 0 + .dw 0x4fc0, 0xc98d, 0x4fff, 0xc98d, 0x21, 0 + .dw 0x5040, 0xc98d, 0x507f, 0xc98d, 0x21, 0 + .dw 0x50c0, 0xc98d, 0x50ff, 0xc98d, 0x21, 0 + .dw 0x5140, 0xc98d, 0x517f, 0xc98d, 0x21, 0 + .dw 0x51c0, 0xc98d, 0x51ff, 0xc98d, 0x21, 0 + .dw 0x5240, 0xc98d, 0x527f, 0xc98d, 0x21, 0 + .dw 0x52c0, 0xc98d, 0x52ff, 0xc98d, 0x21, 0 + .dw 0x5340, 0xc98d, 0x537f, 0xc98d, 0x21, 0 + .dw 0x53c0, 0xc98d, 0x53ff, 0xc98d, 0x21, 0 + .dw 0x5440, 0xc98d, 0x547f, 0xc98d, 0x21, 0 + .dw 0x54c0, 0xc98d, 0x54ff, 0xc98d, 0x21, 0 + .dw 0x5540, 0xc98d, 0x557f, 0xc98d, 0x21, 0 + .dw 0x55c0, 0xc98d, 0x55ff, 0xc98d, 0x21, 0 + .dw 0x5640, 0xc98d, 0x567f, 0xc98d, 0x21, 0 + .dw 0x56c0, 0xc98d, 0x56ff, 0xc98d, 0x21, 0 + .dw 0x5740, 0xc98d, 0x577f, 0xc98d, 0x21, 0 + .dw 0x57c0, 0xc98d, 0x57ff, 0xc98d, 0x21, 0 + .dw 0x5840, 0xc98d, 0x587f, 0xc98d, 0x21, 0 + .dw 0x58c0, 0xc98d, 0x58ff, 0xc98d, 0x21, 0 + .dw 0x5940, 0xc98d, 0x597f, 0xc98d, 0x21, 0 + .dw 0x59c0, 0xc98d, 0x5fff, 0xc98d, 0x21, 0 + .dw 0x6040, 0xc98d, 0x607f, 0xc98d, 0x21, 0 + .dw 0x60c0, 0xc98d, 0x60ff, 0xc98d, 0x21, 0 + .dw 0x6140, 0xc98d, 0x617f, 0xc98d, 0x21, 0 + .dw 0x61c0, 0xc98d, 0x61ff, 0xc98d, 0x21, 0 + .dw 0x6240, 0xc98d, 0x627f, 0xc98d, 0x21, 0 + .dw 0x62c0, 0xc98d, 0x62ff, 0xc98d, 0x21, 0 + .dw 0x6340, 0xc98d, 0x637f, 0xc98d, 0x21, 0 + .dw 0x63c0, 0xc98d, 0x63ff, 0xc98d, 0x21, 0 + .dw 0x6440, 0xc98d, 0x647f, 0xc98d, 0x21, 0 + .dw 0x64c0, 0xc98d, 0x64ff, 0xc98d, 0x21, 0 + .dw 0x6540, 0xc98d, 0x657f, 0xc98d, 0x21, 0 + .dw 0x65c0, 0xc98d, 0x65ff, 0xc98d, 0x21, 0 + .dw 0x6640, 0xc98d, 0x667f, 0xc98d, 0x21, 0 + .dw 0x66c0, 0xc98d, 0x66ff, 0xc98d, 0x21, 0 + .dw 0x6740, 0xc98d, 0x677f, 0xc98d, 0x21, 0 + .dw 0x67c0, 0xc98d, 0x67ff, 0xc98d, 0x21, 0 + .dw 0x6840, 0xc98d, 0x687f, 0xc98d, 0x21, 0 + .dw 0x68c0, 0xc98d, 0x68ff, 0xc98d, 0x21, 0 + .dw 0x6940, 0xc98d, 0x697f, 0xc98d, 0x21, 0 + .dw 0x69c0, 0xc98d, 0x69ff, 0xc98d, 0x21, 0 + .dw 0x6a40, 0xc98d, 0x6a7f, 0xc98d, 0x21, 0 + .dw 0x6ac0, 0xc98d, 0x6aff, 0xc98d, 0x21, 0 + .dw 0x6b40, 0xc98d, 0x6b7f, 0xc98d, 0x21, 0 + .dw 0x6bc0, 0xc98d, 0x6bff, 0xc98d, 0x21, 0 + .dw 0x6c40, 0xc98d, 0x6c7f, 0xc98d, 0x21, 0 + .dw 0x6cc0, 0xc98d, 0x6cff, 0xc98d, 0x21, 0 + .dw 0x6d40, 0xc98d, 0x6d7f, 0xc98d, 0x21, 0 + .dw 0x6dc0, 0xc98d, 0x6dff, 0xc98d, 0x21, 0 + .dw 0x6e40, 0xc98d, 0x6e7f, 0xc98d, 0x21, 0 + .dw 0x6ec0, 0xc98d, 0x6eff, 0xc98d, 0x21, 0 + .dw 0x6f40, 0xc98d, 0x6f7f, 0xc98d, 0x21, 0 + .dw 0x6fc0, 0xc98d, 0x6fff, 0xc98d, 0x21, 0 + .dw 0x7040, 0xc98d, 0x707f, 0xc98d, 0x21, 0 + .dw 0x70c0, 0xc98d, 0x70ff, 0xc98d, 0x21, 0 + .dw 0x7140, 0xc98d, 0x717f, 0xc98d, 0x21, 0 + .dw 0x71c0, 0xc98d, 0x71ff, 0xc98d, 0x21, 0 + .dw 0x7240, 0xc98d, 0x727f, 0xc98d, 0x21, 0 + .dw 0x72c0, 0xc98d, 0x72ff, 0xc98d, 0x21, 0 + .dw 0x7340, 0xc98d, 0x737f, 0xc98d, 0x21, 0 + .dw 0x73c0, 0xc98d, 0x73ff, 0xc98d, 0x21, 0 + .dw 0x7440, 0xc98d, 0x747f, 0xc98d, 0x21, 0 + .dw 0x74c0, 0xc98d, 0x74ff, 0xc98d, 0x21, 0 + .dw 0x7540, 0xc98d, 0x757f, 0xc98d, 0x21, 0 + .dw 0x75c0, 0xc98d, 0x75ff, 0xc98d, 0x21, 0 + .dw 0x7640, 0xc98d, 0x767f, 0xc98d, 0x21, 0 + .dw 0x76c0, 0xc98d, 0x76ff, 0xc98d, 0x21, 0 + .dw 0x7740, 0xc98d, 0x777f, 0xc98d, 0x21, 0 + .dw 0x77c0, 0xc98d, 0x77ff, 0xc98d, 0x21, 0 + .dw 0x7840, 0xc98d, 0x787f, 0xc98d, 0x21, 0 + .dw 0x78c0, 0xc98d, 0x78ff, 0xc98d, 0x21, 0 + .dw 0x7940, 0xc98d, 0x797f, 0xc98d, 0x21, 0 + .dw 0x79c0, 0xc98d, 0x7fff, 0xc98d, 0x21, 0 + .dw 0x8040, 0xc98d, 0x807f, 0xc98d, 0x21, 0 + .dw 0x80c0, 0xc98d, 0x80ff, 0xc98d, 0x21, 0 + .dw 0x8140, 0xc98d, 0x817f, 0xc98d, 0x21, 0 + .dw 0x81c0, 0xc98d, 0x81ff, 0xc98d, 0x21, 0 + .dw 0x8240, 0xc98d, 0x827f, 0xc98d, 0x21, 0 + .dw 0x82c0, 0xc98d, 0x82ff, 0xc98d, 0x21, 0 + .dw 0x8340, 0xc98d, 0x837f, 0xc98d, 0x21, 0 + .dw 0x83c0, 0xc98d, 0x83ff, 0xc98d, 0x21, 0 + .dw 0x8440, 0xc98d, 0x847f, 0xc98d, 0x21, 0 + .dw 0x84c0, 0xc98d, 0x84ff, 0xc98d, 0x21, 0 + .dw 0x8540, 0xc98d, 0x857f, 0xc98d, 0x21, 0 + .dw 0x85c0, 0xc98d, 0x85ff, 0xc98d, 0x21, 0 + .dw 0x8640, 0xc98d, 0x867f, 0xc98d, 0x21, 0 + .dw 0x86c0, 0xc98d, 0x86ff, 0xc98d, 0x21, 0 + .dw 0x8740, 0xc98d, 0x877f, 0xc98d, 0x21, 0 + .dw 0x87c0, 0xc98d, 0x87ff, 0xc98d, 0x21, 0 + .dw 0x8840, 0xc98d, 0x887f, 0xc98d, 0x21, 0 + .dw 0x88c0, 0xc98d, 0x88ff, 0xc98d, 0x21, 0 + .dw 0x8940, 0xc98d, 0x897f, 0xc98d, 0x21, 0 + .dw 0x89c0, 0xc98d, 0x89ff, 0xc98d, 0x21, 0 + .dw 0x8a40, 0xc98d, 0x8a7f, 0xc98d, 0x21, 0 + .dw 0x8ac0, 0xc98d, 0x8aff, 0xc98d, 0x21, 0 + .dw 0x8b40, 0xc98d, 0x8b7f, 0xc98d, 0x21, 0 + .dw 0x8bc0, 0xc98d, 0x8bff, 0xc98d, 0x21, 0 + .dw 0x8c40, 0xc98d, 0x8c7f, 0xc98d, 0x21, 0 + .dw 0x8cc0, 0xc98d, 0x8cff, 0xc98d, 0x21, 0 + .dw 0x8d40, 0xc98d, 0x8d7f, 0xc98d, 0x21, 0 + .dw 0x8dc0, 0xc98d, 0x8dff, 0xc98d, 0x21, 0 + .dw 0x8e40, 0xc98d, 0x8e7f, 0xc98d, 0x21, 0 + .dw 0x8ec0, 0xc98d, 0x8eff, 0xc98d, 0x21, 0 + .dw 0x8f40, 0xc98d, 0x8f7f, 0xc98d, 0x21, 0 + .dw 0x8fc0, 0xc98d, 0x8fff, 0xc98d, 0x21, 0 + .dw 0x9040, 0xc98d, 0x907f, 0xc98d, 0x21, 0 + .dw 0x90c0, 0xc98d, 0x90ff, 0xc98d, 0x21, 0 + .dw 0x9140, 0xc98d, 0x917f, 0xc98d, 0x21, 0 + .dw 0x91c0, 0xc98d, 0x91ff, 0xc98d, 0x21, 0 + .dw 0x9240, 0xc98d, 0x927f, 0xc98d, 0x21, 0 + .dw 0x92c0, 0xc98d, 0x92ff, 0xc98d, 0x21, 0 + .dw 0x9340, 0xc98d, 0x937f, 0xc98d, 0x21, 0 + .dw 0x93c0, 0xc98d, 0x93ff, 0xc98d, 0x21, 0 + .dw 0x9440, 0xc98d, 0x947f, 0xc98d, 0x21, 0 + .dw 0x94c0, 0xc98d, 0x94ff, 0xc98d, 0x21, 0 + .dw 0x9540, 0xc98d, 0x957f, 0xc98d, 0x21, 0 + .dw 0x95c0, 0xc98d, 0x95ff, 0xc98d, 0x21, 0 + .dw 0x9640, 0xc98d, 0x967f, 0xc98d, 0x21, 0 + .dw 0x96c0, 0xc98d, 0x96ff, 0xc98d, 0x21, 0 + .dw 0x9740, 0xc98d, 0x977f, 0xc98d, 0x21, 0 + .dw 0x97c0, 0xc98d, 0x97ff, 0xc98d, 0x21, 0 + .dw 0x9840, 0xc98d, 0x987f, 0xc98d, 0x21, 0 + .dw 0x98c0, 0xc98d, 0x98ff, 0xc98d, 0x21, 0 + .dw 0x9940, 0xc98d, 0x997f, 0xc98d, 0x21, 0 + .dw 0x99c0, 0xc98d, 0x9fff, 0xc98d, 0x21, 0 + .dw 0xa040, 0xc98d, 0xa07f, 0xc98d, 0x21, 0 + .dw 0xa0c0, 0xc98d, 0xa0ff, 0xc98d, 0x21, 0 + .dw 0xa140, 0xc98d, 0xa17f, 0xc98d, 0x21, 0 + .dw 0xa1c0, 0xc98d, 0xa1ff, 0xc98d, 0x21, 0 + .dw 0xa240, 0xc98d, 0xa27f, 0xc98d, 0x21, 0 + .dw 0xa2c0, 0xc98d, 0xa2ff, 0xc98d, 0x21, 0 + .dw 0xa340, 0xc98d, 0xa37f, 0xc98d, 0x21, 0 + .dw 0xa3c0, 0xc98d, 0xa3ff, 0xc98d, 0x21, 0 + .dw 0xa440, 0xc98d, 0xa47f, 0xc98d, 0x21, 0 + .dw 0xa4c0, 0xc98d, 0xa4ff, 0xc98d, 0x21, 0 + .dw 0xa540, 0xc98d, 0xa57f, 0xc98d, 0x21, 0 + .dw 0xa5c0, 0xc98d, 0xa5ff, 0xc98d, 0x21, 0 + .dw 0xa640, 0xc98d, 0xa67f, 0xc98d, 0x21, 0 + .dw 0xa6c0, 0xc98d, 0xa6ff, 0xc98d, 0x21, 0 + .dw 0xa740, 0xc98d, 0xa77f, 0xc98d, 0x21, 0 + .dw 0xa7c0, 0xc98d, 0xa7ff, 0xc98d, 0x21, 0 + .dw 0xa840, 0xc98d, 0xa87f, 0xc98d, 0x21, 0 + .dw 0xa8c0, 0xc98d, 0xa8ff, 0xc98d, 0x21, 0 + .dw 0xa940, 0xc98d, 0xa97f, 0xc98d, 0x21, 0 + .dw 0xa9c0, 0xc98d, 0xa9ff, 0xc98d, 0x21, 0 + .dw 0xaa40, 0xc98d, 0xaa7f, 0xc98d, 0x21, 0 + .dw 0xaac0, 0xc98d, 0xaaff, 0xc98d, 0x21, 0 + .dw 0xab40, 0xc98d, 0xab7f, 0xc98d, 0x21, 0 + .dw 0xabc0, 0xc98d, 0xabff, 0xc98d, 0x21, 0 + .dw 0xac40, 0xc98d, 0xac7f, 0xc98d, 0x21, 0 + .dw 0xacc0, 0xc98d, 0xacff, 0xc98d, 0x21, 0 + .dw 0xad40, 0xc98d, 0xad7f, 0xc98d, 0x21, 0 + .dw 0xadc0, 0xc98d, 0xadff, 0xc98d, 0x21, 0 + .dw 0xae40, 0xc98d, 0xae7f, 0xc98d, 0x21, 0 + .dw 0xaec0, 0xc98d, 0xaeff, 0xc98d, 0x21, 0 + .dw 0xaf40, 0xc98d, 0xaf7f, 0xc98d, 0x21, 0 + .dw 0xafc0, 0xc98d, 0xafff, 0xc98d, 0x21, 0 + .dw 0xb040, 0xc98d, 0xb07f, 0xc98d, 0x21, 0 + .dw 0xb0c0, 0xc98d, 0xb0ff, 0xc98d, 0x21, 0 + .dw 0xb140, 0xc98d, 0xb17f, 0xc98d, 0x21, 0 + .dw 0xb1c0, 0xc98d, 0xb1ff, 0xc98d, 0x21, 0 + .dw 0xb240, 0xc98d, 0xb27f, 0xc98d, 0x21, 0 + .dw 0xb2c0, 0xc98d, 0xb2ff, 0xc98d, 0x21, 0 + .dw 0xb340, 0xc98d, 0xb37f, 0xc98d, 0x21, 0 + .dw 0xb3c0, 0xc98d, 0xb3ff, 0xc98d, 0x21, 0 + .dw 0xb440, 0xc98d, 0xb47f, 0xc98d, 0x21, 0 + .dw 0xb4c0, 0xc98d, 0xb4ff, 0xc98d, 0x21, 0 + .dw 0xb540, 0xc98d, 0xb57f, 0xc98d, 0x21, 0 + .dw 0xb5c0, 0xc98d, 0xb5ff, 0xc98d, 0x21, 0 + .dw 0xb640, 0xc98d, 0xb67f, 0xc98d, 0x21, 0 + .dw 0xb6c0, 0xc98d, 0xb6ff, 0xc98d, 0x21, 0 + .dw 0xb740, 0xc98d, 0xb77f, 0xc98d, 0x21, 0 + .dw 0xb7c0, 0xc98d, 0xb7ff, 0xc98d, 0x21, 0 + .dw 0xb840, 0xc98d, 0xb87f, 0xc98d, 0x21, 0 + .dw 0xb8c0, 0xc98d, 0xb8ff, 0xc98d, 0x21, 0 + .dw 0xb940, 0xc98d, 0xb97f, 0xc98d, 0x21, 0 + .dw 0xb9c0, 0xc98d, 0xbfff, 0xc98d, 0x21, 0 + .dw 0xc040, 0xc98d, 0xc07f, 0xc98d, 0x21, 0 + .dw 0xc0c0, 0xc98d, 0xc0ff, 0xc98d, 0x21, 0 + .dw 0xc140, 0xc98d, 0xc17f, 0xc98d, 0x21, 0 + .dw 0xc1c0, 0xc98d, 0xc1ff, 0xc98d, 0x21, 0 + .dw 0xc240, 0xc98d, 0xc27f, 0xc98d, 0x21, 0 + .dw 0xc2c0, 0xc98d, 0xc2ff, 0xc98d, 0x21, 0 + .dw 0xc340, 0xc98d, 0xc37f, 0xc98d, 0x21, 0 + .dw 0xc3c0, 0xc98d, 0xc3ff, 0xc98d, 0x21, 0 + .dw 0xc440, 0xc98d, 0xc47f, 0xc98d, 0x21, 0 + .dw 0xc4c0, 0xc98d, 0xc4ff, 0xc98d, 0x21, 0 + .dw 0xc540, 0xc98d, 0xc57f, 0xc98d, 0x21, 0 + .dw 0xc5c0, 0xc98d, 0xc5ff, 0xc98d, 0x21, 0 + .dw 0xc640, 0xc98d, 0xc67f, 0xc98d, 0x21, 0 + .dw 0xc6c0, 0xc98d, 0xc6ff, 0xc98d, 0x21, 0 + .dw 0xc740, 0xc98d, 0xc77f, 0xc98d, 0x21, 0 + .dw 0xc7c0, 0xc98d, 0xc7ff, 0xc98d, 0x21, 0 + .dw 0xc840, 0xc98d, 0xc87f, 0xc98d, 0x21, 0 + .dw 0xc8c0, 0xc98d, 0xc8ff, 0xc98d, 0x21, 0 + .dw 0xc940, 0xc98d, 0xc97f, 0xc98d, 0x21, 0 + .dw 0xc9c0, 0xc98d, 0xc9ff, 0xc98d, 0x21, 0 + .dw 0xca40, 0xc98d, 0xca7f, 0xc98d, 0x21, 0 + .dw 0xcac0, 0xc98d, 0xcaff, 0xc98d, 0x21, 0 + .dw 0xcb40, 0xc98d, 0xcb7f, 0xc98d, 0x21, 0 + .dw 0xcbc0, 0xc98d, 0xcbff, 0xc98d, 0x21, 0 + .dw 0xcc40, 0xc98d, 0xcc7f, 0xc98d, 0x21, 0 + .dw 0xccc0, 0xc98d, 0xccff, 0xc98d, 0x21, 0 + .dw 0xcd40, 0xc98d, 0xcd7f, 0xc98d, 0x21, 0 + .dw 0xcdc0, 0xc98d, 0xcdff, 0xc98d, 0x21, 0 + .dw 0xce40, 0xc98d, 0xce7f, 0xc98d, 0x21, 0 + .dw 0xcec0, 0xc98d, 0xceff, 0xc98d, 0x21, 0 + .dw 0xcf40, 0xc98d, 0xcf7f, 0xc98d, 0x21, 0 + .dw 0xcfc0, 0xc98d, 0xcfff, 0xc98d, 0x21, 0 + .dw 0xd040, 0xc98d, 0xd07f, 0xc98d, 0x21, 0 + .dw 0xd0c0, 0xc98d, 0xd0ff, 0xc98d, 0x21, 0 + .dw 0xd140, 0xc98d, 0xd17f, 0xc98d, 0x21, 0 + .dw 0xd1c0, 0xc98d, 0xd1ff, 0xc98d, 0x21, 0 + .dw 0xd240, 0xc98d, 0xd27f, 0xc98d, 0x21, 0 + .dw 0xd2c0, 0xc98d, 0xd2ff, 0xc98d, 0x21, 0 + .dw 0xd340, 0xc98d, 0xd37f, 0xc98d, 0x21, 0 + .dw 0xd3c0, 0xc98d, 0xd3ff, 0xc98d, 0x21, 0 + .dw 0xd440, 0xc98d, 0xd47f, 0xc98d, 0x21, 0 + .dw 0xd4c0, 0xc98d, 0xd4ff, 0xc98d, 0x21, 0 + .dw 0xd540, 0xc98d, 0xd57f, 0xc98d, 0x21, 0 + .dw 0xd5c0, 0xc98d, 0xd5ff, 0xc98d, 0x21, 0 + .dw 0xd640, 0xc98d, 0xd67f, 0xc98d, 0x21, 0 + .dw 0xd6c0, 0xc98d, 0xd6ff, 0xc98d, 0x21, 0 + .dw 0xd740, 0xc98d, 0xd77f, 0xc98d, 0x21, 0 + .dw 0xd7c0, 0xc98d, 0xd7ff, 0xc98d, 0x21, 0 + .dw 0xd840, 0xc98d, 0xd87f, 0xc98d, 0x21, 0 + .dw 0xd8c0, 0xc98d, 0xd8ff, 0xc98d, 0x21, 0 + .dw 0xd940, 0xc98d, 0xd97f, 0xc98d, 0x21, 0 + .dw 0xd9c0, 0xc98d, 0xdfff, 0xc98d, 0x21, 0 + .dw 0xe040, 0xc98d, 0xe07f, 0xc98d, 0x21, 0 + .dw 0xe0c0, 0xc98d, 0xe0ff, 0xc98d, 0x21, 0 + .dw 0xe140, 0xc98d, 0xe17f, 0xc98d, 0x21, 0 + .dw 0xe1c0, 0xc98d, 0xe1ff, 0xc98d, 0x21, 0 + .dw 0xe240, 0xc98d, 0xe27f, 0xc98d, 0x21, 0 + .dw 0xe2c0, 0xc98d, 0xe2ff, 0xc98d, 0x21, 0 + .dw 0xe340, 0xc98d, 0xe37f, 0xc98d, 0x21, 0 + .dw 0xe3c0, 0xc98d, 0xe3ff, 0xc98d, 0x21, 0 + .dw 0xe440, 0xc98d, 0xe47f, 0xc98d, 0x21, 0 + .dw 0xe4c0, 0xc98d, 0xe4ff, 0xc98d, 0x21, 0 + .dw 0xe540, 0xc98d, 0xe57f, 0xc98d, 0x21, 0 + .dw 0xe5c0, 0xc98d, 0xe5ff, 0xc98d, 0x21, 0 + .dw 0xe640, 0xc98d, 0xe67f, 0xc98d, 0x21, 0 + .dw 0xe6c0, 0xc98d, 0xe6ff, 0xc98d, 0x21, 0 + .dw 0xe740, 0xc98d, 0xe77f, 0xc98d, 0x21, 0 + .dw 0xe7c0, 0xc98d, 0xe7ff, 0xc98d, 0x21, 0 + .dw 0xe840, 0xc98d, 0xe87f, 0xc98d, 0x21, 0 + .dw 0xe8c0, 0xc98d, 0xe8ff, 0xc98d, 0x21, 0 + .dw 0xe940, 0xc98d, 0xe97f, 0xc98d, 0x21, 0 + .dw 0xe9c0, 0xc98d, 0xe9ff, 0xc98d, 0x21, 0 + .dw 0xea40, 0xc98d, 0xea7f, 0xc98d, 0x21, 0 + .dw 0xeac0, 0xc98d, 0xeaff, 0xc98d, 0x21, 0 + .dw 0xeb40, 0xc98d, 0xeb7f, 0xc98d, 0x21, 0 + .dw 0xebc0, 0xc98d, 0xebff, 0xc98d, 0x21, 0 + .dw 0xec40, 0xc98d, 0xec7f, 0xc98d, 0x21, 0 + .dw 0xecc0, 0xc98d, 0xecff, 0xc98d, 0x21, 0 + .dw 0xed40, 0xc98d, 0xed7f, 0xc98d, 0x21, 0 + .dw 0xedc0, 0xc98d, 0xedff, 0xc98d, 0x21, 0 + .dw 0xee40, 0xc98d, 0xee7f, 0xc98d, 0x21, 0 + .dw 0xeec0, 0xc98d, 0xeeff, 0xc98d, 0x21, 0 + .dw 0xef40, 0xc98d, 0xef7f, 0xc98d, 0x21, 0 + .dw 0xefc0, 0xc98d, 0xefff, 0xc98d, 0x21, 0 + .dw 0xf040, 0xc98d, 0xf07f, 0xc98d, 0x21, 0 + .dw 0xf0c0, 0xc98d, 0xf0ff, 0xc98d, 0x21, 0 + .dw 0xf140, 0xc98d, 0xf17f, 0xc98d, 0x21, 0 + .dw 0xf1c0, 0xc98d, 0xf1ff, 0xc98d, 0x21, 0 + .dw 0xf240, 0xc98d, 0xf27f, 0xc98d, 0x21, 0 + .dw 0xf2c0, 0xc98d, 0xf2ff, 0xc98d, 0x21, 0 + .dw 0xf340, 0xc98d, 0xf37f, 0xc98d, 0x21, 0 + .dw 0xf3c0, 0xc98d, 0xf3ff, 0xc98d, 0x21, 0 + .dw 0xf440, 0xc98d, 0xf47f, 0xc98d, 0x21, 0 + .dw 0xf4c0, 0xc98d, 0xf4ff, 0xc98d, 0x21, 0 + .dw 0xf540, 0xc98d, 0xf57f, 0xc98d, 0x21, 0 + .dw 0xf5c0, 0xc98d, 0xf5ff, 0xc98d, 0x21, 0 + .dw 0xf640, 0xc98d, 0xf67f, 0xc98d, 0x21, 0 + .dw 0xf6c0, 0xc98d, 0xf6ff, 0xc98d, 0x21, 0 + .dw 0xf740, 0xc98d, 0xf77f, 0xc98d, 0x21, 0 + .dw 0xf7c0, 0xc98d, 0xf7ff, 0xc98d, 0x21, 0 + .dw 0xf840, 0xc98d, 0xf87f, 0xc98d, 0x21, 0 + .dw 0xf8c0, 0xc98d, 0xf8ff, 0xc98d, 0x21, 0 + .dw 0xf940, 0xc98d, 0xf97f, 0xc98d, 0x21, 0 + .dw 0xf9c0, 0xc98d, 0xffff, 0xc98d, 0x21, 0 + .dw 0x0040, 0xc98e, 0x007f, 0xc98e, 0x21, 0 + .dw 0x00c0, 0xc98e, 0x00ff, 0xc98e, 0x21, 0 + .dw 0x0140, 0xc98e, 0x017f, 0xc98e, 0x21, 0 + .dw 0x01c0, 0xc98e, 0x01ff, 0xc98e, 0x21, 0 + .dw 0x0240, 0xc98e, 0x027f, 0xc98e, 0x21, 0 + .dw 0x02c0, 0xc98e, 0x02ff, 0xc98e, 0x21, 0 + .dw 0x0340, 0xc98e, 0x037f, 0xc98e, 0x21, 0 + .dw 0x03c0, 0xc98e, 0x03ff, 0xc98e, 0x21, 0 + .dw 0x0440, 0xc98e, 0x047f, 0xc98e, 0x21, 0 + .dw 0x04c0, 0xc98e, 0x04ff, 0xc98e, 0x21, 0 + .dw 0x0540, 0xc98e, 0x057f, 0xc98e, 0x21, 0 + .dw 0x05c0, 0xc98e, 0x05ff, 0xc98e, 0x21, 0 + .dw 0x0640, 0xc98e, 0x067f, 0xc98e, 0x21, 0 + .dw 0x06c0, 0xc98e, 0x06ff, 0xc98e, 0x21, 0 + .dw 0x0740, 0xc98e, 0x077f, 0xc98e, 0x21, 0 + .dw 0x07c0, 0xc98e, 0x07ff, 0xc98e, 0x21, 0 + .dw 0x0840, 0xc98e, 0x087f, 0xc98e, 0x21, 0 + .dw 0x08c0, 0xc98e, 0x08ff, 0xc98e, 0x21, 0 + .dw 0x0940, 0xc98e, 0x097f, 0xc98e, 0x21, 0 + .dw 0x09c0, 0xc98e, 0x09ff, 0xc98e, 0x21, 0 + .dw 0x0a40, 0xc98e, 0x0a7f, 0xc98e, 0x21, 0 + .dw 0x0ac0, 0xc98e, 0x0aff, 0xc98e, 0x21, 0 + .dw 0x0b40, 0xc98e, 0x0b7f, 0xc98e, 0x21, 0 + .dw 0x0bc0, 0xc98e, 0x0bff, 0xc98e, 0x21, 0 + .dw 0x0c40, 0xc98e, 0x0c7f, 0xc98e, 0x21, 0 + .dw 0x0cc0, 0xc98e, 0x0cff, 0xc98e, 0x21, 0 + .dw 0x0d40, 0xc98e, 0x0d7f, 0xc98e, 0x21, 0 + .dw 0x0dc0, 0xc98e, 0x0dff, 0xc98e, 0x21, 0 + .dw 0x0e40, 0xc98e, 0x0e7f, 0xc98e, 0x21, 0 + .dw 0x0ec0, 0xc98e, 0x0eff, 0xc98e, 0x21, 0 + .dw 0x0f40, 0xc98e, 0x0f7f, 0xc98e, 0x21, 0 + .dw 0x0fc0, 0xc98e, 0x0fff, 0xc98e, 0x21, 0 + .dw 0x1040, 0xc98e, 0x107f, 0xc98e, 0x21, 0 + .dw 0x10c0, 0xc98e, 0x10ff, 0xc98e, 0x21, 0 + .dw 0x1140, 0xc98e, 0x117f, 0xc98e, 0x21, 0 + .dw 0x11c0, 0xc98e, 0x11ff, 0xc98e, 0x21, 0 + .dw 0x1240, 0xc98e, 0x127f, 0xc98e, 0x21, 0 + .dw 0x12c0, 0xc98e, 0x12ff, 0xc98e, 0x21, 0 + .dw 0x1340, 0xc98e, 0x137f, 0xc98e, 0x21, 0 + .dw 0x13c0, 0xc98e, 0x13ff, 0xc98e, 0x21, 0 + .dw 0x1440, 0xc98e, 0x147f, 0xc98e, 0x21, 0 + .dw 0x14c0, 0xc98e, 0x14ff, 0xc98e, 0x21, 0 + .dw 0x1540, 0xc98e, 0x157f, 0xc98e, 0x21, 0 + .dw 0x15c0, 0xc98e, 0x15ff, 0xc98e, 0x21, 0 + .dw 0x1640, 0xc98e, 0x167f, 0xc98e, 0x21, 0 + .dw 0x16c0, 0xc98e, 0x16ff, 0xc98e, 0x21, 0 + .dw 0x1740, 0xc98e, 0x177f, 0xc98e, 0x21, 0 + .dw 0x17c0, 0xc98e, 0x17ff, 0xc98e, 0x21, 0 + .dw 0x1840, 0xc98e, 0x187f, 0xc98e, 0x21, 0 + .dw 0x18c0, 0xc98e, 0x18ff, 0xc98e, 0x21, 0 + .dw 0x1940, 0xc98e, 0x197f, 0xc98e, 0x21, 0 + .dw 0x19c0, 0xc98e, 0x1fff, 0xc98e, 0x21, 0 + .dw 0x2040, 0xc98e, 0x207f, 0xc98e, 0x21, 0 + .dw 0x20c0, 0xc98e, 0x20ff, 0xc98e, 0x21, 0 + .dw 0x2140, 0xc98e, 0x217f, 0xc98e, 0x21, 0 + .dw 0x21c0, 0xc98e, 0x21ff, 0xc98e, 0x21, 0 + .dw 0x2240, 0xc98e, 0x227f, 0xc98e, 0x21, 0 + .dw 0x22c0, 0xc98e, 0x22ff, 0xc98e, 0x21, 0 + .dw 0x2340, 0xc98e, 0x237f, 0xc98e, 0x21, 0 + .dw 0x23c0, 0xc98e, 0x23ff, 0xc98e, 0x21, 0 + .dw 0x2440, 0xc98e, 0x247f, 0xc98e, 0x21, 0 + .dw 0x24c0, 0xc98e, 0x24ff, 0xc98e, 0x21, 0 + .dw 0x2540, 0xc98e, 0x257f, 0xc98e, 0x21, 0 + .dw 0x25c0, 0xc98e, 0x25ff, 0xc98e, 0x21, 0 + .dw 0x2640, 0xc98e, 0x267f, 0xc98e, 0x21, 0 + .dw 0x26c0, 0xc98e, 0x26ff, 0xc98e, 0x21, 0 + .dw 0x2740, 0xc98e, 0x277f, 0xc98e, 0x21, 0 + .dw 0x27c0, 0xc98e, 0x27ff, 0xc98e, 0x21, 0 + .dw 0x2840, 0xc98e, 0x287f, 0xc98e, 0x21, 0 + .dw 0x28c0, 0xc98e, 0x28ff, 0xc98e, 0x21, 0 + .dw 0x2940, 0xc98e, 0x297f, 0xc98e, 0x21, 0 + .dw 0x29c0, 0xc98e, 0x29ff, 0xc98e, 0x21, 0 + .dw 0x2a40, 0xc98e, 0x2a7f, 0xc98e, 0x21, 0 + .dw 0x2ac0, 0xc98e, 0x2aff, 0xc98e, 0x21, 0 + .dw 0x2b40, 0xc98e, 0x2b7f, 0xc98e, 0x21, 0 + .dw 0x2bc0, 0xc98e, 0x2bff, 0xc98e, 0x21, 0 + .dw 0x2c40, 0xc98e, 0x2c7f, 0xc98e, 0x21, 0 + .dw 0x2cc0, 0xc98e, 0x2cff, 0xc98e, 0x21, 0 + .dw 0x2d40, 0xc98e, 0x2d7f, 0xc98e, 0x21, 0 + .dw 0x2dc0, 0xc98e, 0x2dff, 0xc98e, 0x21, 0 + .dw 0x2e40, 0xc98e, 0x2e7f, 0xc98e, 0x21, 0 + .dw 0x2ec0, 0xc98e, 0x2eff, 0xc98e, 0x21, 0 + .dw 0x2f40, 0xc98e, 0x2f7f, 0xc98e, 0x21, 0 + .dw 0x2fc0, 0xc98e, 0x2fff, 0xc98e, 0x21, 0 + .dw 0x3040, 0xc98e, 0x307f, 0xc98e, 0x21, 0 + .dw 0x30c0, 0xc98e, 0x30ff, 0xc98e, 0x21, 0 + .dw 0x3140, 0xc98e, 0x317f, 0xc98e, 0x21, 0 + .dw 0x31c0, 0xc98e, 0x31ff, 0xc98e, 0x21, 0 + .dw 0x3240, 0xc98e, 0x327f, 0xc98e, 0x21, 0 + .dw 0x32c0, 0xc98e, 0x32ff, 0xc98e, 0x21, 0 + .dw 0x3340, 0xc98e, 0x337f, 0xc98e, 0x21, 0 + .dw 0x33c0, 0xc98e, 0x33ff, 0xc98e, 0x21, 0 + .dw 0x3440, 0xc98e, 0x347f, 0xc98e, 0x21, 0 + .dw 0x34c0, 0xc98e, 0x34ff, 0xc98e, 0x21, 0 + .dw 0x3540, 0xc98e, 0x357f, 0xc98e, 0x21, 0 + .dw 0x35c0, 0xc98e, 0x35ff, 0xc98e, 0x21, 0 + .dw 0x3640, 0xc98e, 0x367f, 0xc98e, 0x21, 0 + .dw 0x36c0, 0xc98e, 0x36ff, 0xc98e, 0x21, 0 + .dw 0x3740, 0xc98e, 0x377f, 0xc98e, 0x21, 0 + .dw 0x37c0, 0xc98e, 0x37ff, 0xc98e, 0x21, 0 + .dw 0x3840, 0xc98e, 0x387f, 0xc98e, 0x21, 0 + .dw 0x38c0, 0xc98e, 0x38ff, 0xc98e, 0x21, 0 + .dw 0x3940, 0xc98e, 0x397f, 0xc98e, 0x21, 0 + .dw 0x39c0, 0xc98e, 0x3fff, 0xc98e, 0x21, 0 + .dw 0x4040, 0xc98e, 0x407f, 0xc98e, 0x21, 0 + .dw 0x40c0, 0xc98e, 0x40ff, 0xc98e, 0x21, 0 + .dw 0x4140, 0xc98e, 0x417f, 0xc98e, 0x21, 0 + .dw 0x41c0, 0xc98e, 0x41ff, 0xc98e, 0x21, 0 + .dw 0x4240, 0xc98e, 0x427f, 0xc98e, 0x21, 0 + .dw 0x42c0, 0xc98e, 0x42ff, 0xc98e, 0x21, 0 + .dw 0x4340, 0xc98e, 0x437f, 0xc98e, 0x21, 0 + .dw 0x43c0, 0xc98e, 0x43ff, 0xc98e, 0x21, 0 + .dw 0x4440, 0xc98e, 0x447f, 0xc98e, 0x21, 0 + .dw 0x44c0, 0xc98e, 0x44ff, 0xc98e, 0x21, 0 + .dw 0x4540, 0xc98e, 0x457f, 0xc98e, 0x21, 0 + .dw 0x45c0, 0xc98e, 0x45ff, 0xc98e, 0x21, 0 + .dw 0x4640, 0xc98e, 0x467f, 0xc98e, 0x21, 0 + .dw 0x46c0, 0xc98e, 0x46ff, 0xc98e, 0x21, 0 + .dw 0x4740, 0xc98e, 0x477f, 0xc98e, 0x21, 0 + .dw 0x47c0, 0xc98e, 0x47ff, 0xc98e, 0x21, 0 + .dw 0x4840, 0xc98e, 0x487f, 0xc98e, 0x21, 0 + .dw 0x48c0, 0xc98e, 0x48ff, 0xc98e, 0x21, 0 + .dw 0x4940, 0xc98e, 0x497f, 0xc98e, 0x21, 0 + .dw 0x49c0, 0xc98e, 0x49ff, 0xc98e, 0x21, 0 + .dw 0x4a40, 0xc98e, 0x4a7f, 0xc98e, 0x21, 0 + .dw 0x4ac0, 0xc98e, 0x4aff, 0xc98e, 0x21, 0 + .dw 0x4b40, 0xc98e, 0x4b7f, 0xc98e, 0x21, 0 + .dw 0x4bc0, 0xc98e, 0x4bff, 0xc98e, 0x21, 0 + .dw 0x4c40, 0xc98e, 0x4c7f, 0xc98e, 0x21, 0 + .dw 0x4cc0, 0xc98e, 0x4cff, 0xc98e, 0x21, 0 + .dw 0x4d40, 0xc98e, 0x4d7f, 0xc98e, 0x21, 0 + .dw 0x4dc0, 0xc98e, 0x4dff, 0xc98e, 0x21, 0 + .dw 0x4e40, 0xc98e, 0x4e7f, 0xc98e, 0x21, 0 + .dw 0x4ec0, 0xc98e, 0x4eff, 0xc98e, 0x21, 0 + .dw 0x4f40, 0xc98e, 0x4f7f, 0xc98e, 0x21, 0 + .dw 0x4fc0, 0xc98e, 0x4fff, 0xc98e, 0x21, 0 + .dw 0x5040, 0xc98e, 0x507f, 0xc98e, 0x21, 0 + .dw 0x50c0, 0xc98e, 0x50ff, 0xc98e, 0x21, 0 + .dw 0x5140, 0xc98e, 0x517f, 0xc98e, 0x21, 0 + .dw 0x51c0, 0xc98e, 0x51ff, 0xc98e, 0x21, 0 + .dw 0x5240, 0xc98e, 0x527f, 0xc98e, 0x21, 0 + .dw 0x52c0, 0xc98e, 0x52ff, 0xc98e, 0x21, 0 + .dw 0x5340, 0xc98e, 0x537f, 0xc98e, 0x21, 0 + .dw 0x53c0, 0xc98e, 0x53ff, 0xc98e, 0x21, 0 + .dw 0x5440, 0xc98e, 0x547f, 0xc98e, 0x21, 0 + .dw 0x54c0, 0xc98e, 0x54ff, 0xc98e, 0x21, 0 + .dw 0x5540, 0xc98e, 0x557f, 0xc98e, 0x21, 0 + .dw 0x55c0, 0xc98e, 0x55ff, 0xc98e, 0x21, 0 + .dw 0x5640, 0xc98e, 0x567f, 0xc98e, 0x21, 0 + .dw 0x56c0, 0xc98e, 0x56ff, 0xc98e, 0x21, 0 + .dw 0x5740, 0xc98e, 0x577f, 0xc98e, 0x21, 0 + .dw 0x57c0, 0xc98e, 0x57ff, 0xc98e, 0x21, 0 + .dw 0x5840, 0xc98e, 0x587f, 0xc98e, 0x21, 0 + .dw 0x58c0, 0xc98e, 0x58ff, 0xc98e, 0x21, 0 + .dw 0x5940, 0xc98e, 0x597f, 0xc98e, 0x21, 0 + .dw 0x59c0, 0xc98e, 0x5fff, 0xc98e, 0x21, 0 + .dw 0x6040, 0xc98e, 0x607f, 0xc98e, 0x21, 0 + .dw 0x60c0, 0xc98e, 0x60ff, 0xc98e, 0x21, 0 + .dw 0x6140, 0xc98e, 0x617f, 0xc98e, 0x21, 0 + .dw 0x61c0, 0xc98e, 0x61ff, 0xc98e, 0x21, 0 + .dw 0x6240, 0xc98e, 0x627f, 0xc98e, 0x21, 0 + .dw 0x62c0, 0xc98e, 0x62ff, 0xc98e, 0x21, 0 + .dw 0x6340, 0xc98e, 0x637f, 0xc98e, 0x21, 0 + .dw 0x63c0, 0xc98e, 0x63ff, 0xc98e, 0x21, 0 + .dw 0x6440, 0xc98e, 0x647f, 0xc98e, 0x21, 0 + .dw 0x64c0, 0xc98e, 0x64ff, 0xc98e, 0x21, 0 + .dw 0x6540, 0xc98e, 0x657f, 0xc98e, 0x21, 0 + .dw 0x65c0, 0xc98e, 0x65ff, 0xc98e, 0x21, 0 + .dw 0x6640, 0xc98e, 0x667f, 0xc98e, 0x21, 0 + .dw 0x66c0, 0xc98e, 0x66ff, 0xc98e, 0x21, 0 + .dw 0x6740, 0xc98e, 0x677f, 0xc98e, 0x21, 0 + .dw 0x67c0, 0xc98e, 0x67ff, 0xc98e, 0x21, 0 + .dw 0x6840, 0xc98e, 0x687f, 0xc98e, 0x21, 0 + .dw 0x68c0, 0xc98e, 0x68ff, 0xc98e, 0x21, 0 + .dw 0x6940, 0xc98e, 0x697f, 0xc98e, 0x21, 0 + .dw 0x69c0, 0xc98e, 0x69ff, 0xc98e, 0x21, 0 + .dw 0x6a40, 0xc98e, 0x6a7f, 0xc98e, 0x21, 0 + .dw 0x6ac0, 0xc98e, 0x6aff, 0xc98e, 0x21, 0 + .dw 0x6b40, 0xc98e, 0x6b7f, 0xc98e, 0x21, 0 + .dw 0x6bc0, 0xc98e, 0x6bff, 0xc98e, 0x21, 0 + .dw 0x6c40, 0xc98e, 0x6c7f, 0xc98e, 0x21, 0 + .dw 0x6cc0, 0xc98e, 0x6cff, 0xc98e, 0x21, 0 + .dw 0x6d40, 0xc98e, 0x6d7f, 0xc98e, 0x21, 0 + .dw 0x6dc0, 0xc98e, 0x6dff, 0xc98e, 0x21, 0 + .dw 0x6e40, 0xc98e, 0x6e7f, 0xc98e, 0x21, 0 + .dw 0x6ec0, 0xc98e, 0x6eff, 0xc98e, 0x21, 0 + .dw 0x6f40, 0xc98e, 0x6f7f, 0xc98e, 0x21, 0 + .dw 0x6fc0, 0xc98e, 0x6fff, 0xc98e, 0x21, 0 + .dw 0x7040, 0xc98e, 0x707f, 0xc98e, 0x21, 0 + .dw 0x70c0, 0xc98e, 0x70ff, 0xc98e, 0x21, 0 + .dw 0x7140, 0xc98e, 0x717f, 0xc98e, 0x21, 0 + .dw 0x71c0, 0xc98e, 0x71ff, 0xc98e, 0x21, 0 + .dw 0x7240, 0xc98e, 0x727f, 0xc98e, 0x21, 0 + .dw 0x72c0, 0xc98e, 0x72ff, 0xc98e, 0x21, 0 + .dw 0x7340, 0xc98e, 0x737f, 0xc98e, 0x21, 0 + .dw 0x73c0, 0xc98e, 0x73ff, 0xc98e, 0x21, 0 + .dw 0x7440, 0xc98e, 0x747f, 0xc98e, 0x21, 0 + .dw 0x74c0, 0xc98e, 0x74ff, 0xc98e, 0x21, 0 + .dw 0x7540, 0xc98e, 0x757f, 0xc98e, 0x21, 0 + .dw 0x75c0, 0xc98e, 0x75ff, 0xc98e, 0x21, 0 + .dw 0x7640, 0xc98e, 0x767f, 0xc98e, 0x21, 0 + .dw 0x76c0, 0xc98e, 0x76ff, 0xc98e, 0x21, 0 + .dw 0x7740, 0xc98e, 0x777f, 0xc98e, 0x21, 0 + .dw 0x77c0, 0xc98e, 0x77ff, 0xc98e, 0x21, 0 + .dw 0x7840, 0xc98e, 0x787f, 0xc98e, 0x21, 0 + .dw 0x78c0, 0xc98e, 0x78ff, 0xc98e, 0x21, 0 + .dw 0x7940, 0xc98e, 0x797f, 0xc98e, 0x21, 0 + .dw 0x79c0, 0xc98e, 0x7fff, 0xc98e, 0x21, 0 + .dw 0x8040, 0xc98e, 0x807f, 0xc98e, 0x21, 0 + .dw 0x80c0, 0xc98e, 0x80ff, 0xc98e, 0x21, 0 + .dw 0x8140, 0xc98e, 0x817f, 0xc98e, 0x21, 0 + .dw 0x81c0, 0xc98e, 0x81ff, 0xc98e, 0x21, 0 + .dw 0x8240, 0xc98e, 0x827f, 0xc98e, 0x21, 0 + .dw 0x82c0, 0xc98e, 0x82ff, 0xc98e, 0x21, 0 + .dw 0x8340, 0xc98e, 0x837f, 0xc98e, 0x21, 0 + .dw 0x83c0, 0xc98e, 0x83ff, 0xc98e, 0x21, 0 + .dw 0x8440, 0xc98e, 0x847f, 0xc98e, 0x21, 0 + .dw 0x84c0, 0xc98e, 0x84ff, 0xc98e, 0x21, 0 + .dw 0x8540, 0xc98e, 0x857f, 0xc98e, 0x21, 0 + .dw 0x85c0, 0xc98e, 0x85ff, 0xc98e, 0x21, 0 + .dw 0x8640, 0xc98e, 0x867f, 0xc98e, 0x21, 0 + .dw 0x86c0, 0xc98e, 0x86ff, 0xc98e, 0x21, 0 + .dw 0x8740, 0xc98e, 0x877f, 0xc98e, 0x21, 0 + .dw 0x87c0, 0xc98e, 0x87ff, 0xc98e, 0x21, 0 + .dw 0x8840, 0xc98e, 0x887f, 0xc98e, 0x21, 0 + .dw 0x88c0, 0xc98e, 0x88ff, 0xc98e, 0x21, 0 + .dw 0x8940, 0xc98e, 0x897f, 0xc98e, 0x21, 0 + .dw 0x89c0, 0xc98e, 0x89ff, 0xc98e, 0x21, 0 + .dw 0x8a40, 0xc98e, 0x8a7f, 0xc98e, 0x21, 0 + .dw 0x8ac0, 0xc98e, 0x8aff, 0xc98e, 0x21, 0 + .dw 0x8b40, 0xc98e, 0x8b7f, 0xc98e, 0x21, 0 + .dw 0x8bc0, 0xc98e, 0x8bff, 0xc98e, 0x21, 0 + .dw 0x8c40, 0xc98e, 0x8c7f, 0xc98e, 0x21, 0 + .dw 0x8cc0, 0xc98e, 0x8cff, 0xc98e, 0x21, 0 + .dw 0x8d40, 0xc98e, 0x8d7f, 0xc98e, 0x21, 0 + .dw 0x8dc0, 0xc98e, 0x8dff, 0xc98e, 0x21, 0 + .dw 0x8e40, 0xc98e, 0x8e7f, 0xc98e, 0x21, 0 + .dw 0x8ec0, 0xc98e, 0x8eff, 0xc98e, 0x21, 0 + .dw 0x8f40, 0xc98e, 0x8f7f, 0xc98e, 0x21, 0 + .dw 0x8fc0, 0xc98e, 0x8fff, 0xc98e, 0x21, 0 + .dw 0x9040, 0xc98e, 0x907f, 0xc98e, 0x21, 0 + .dw 0x90c0, 0xc98e, 0x90ff, 0xc98e, 0x21, 0 + .dw 0x9140, 0xc98e, 0x917f, 0xc98e, 0x21, 0 + .dw 0x91c0, 0xc98e, 0x91ff, 0xc98e, 0x21, 0 + .dw 0x9240, 0xc98e, 0x927f, 0xc98e, 0x21, 0 + .dw 0x92c0, 0xc98e, 0x92ff, 0xc98e, 0x21, 0 + .dw 0x9340, 0xc98e, 0x937f, 0xc98e, 0x21, 0 + .dw 0x93c0, 0xc98e, 0x93ff, 0xc98e, 0x21, 0 + .dw 0x9440, 0xc98e, 0x947f, 0xc98e, 0x21, 0 + .dw 0x94c0, 0xc98e, 0x94ff, 0xc98e, 0x21, 0 + .dw 0x9540, 0xc98e, 0x957f, 0xc98e, 0x21, 0 + .dw 0x95c0, 0xc98e, 0x95ff, 0xc98e, 0x21, 0 + .dw 0x9640, 0xc98e, 0x967f, 0xc98e, 0x21, 0 + .dw 0x96c0, 0xc98e, 0x96ff, 0xc98e, 0x21, 0 + .dw 0x9740, 0xc98e, 0x977f, 0xc98e, 0x21, 0 + .dw 0x97c0, 0xc98e, 0x97ff, 0xc98e, 0x21, 0 + .dw 0x9840, 0xc98e, 0x987f, 0xc98e, 0x21, 0 + .dw 0x98c0, 0xc98e, 0x98ff, 0xc98e, 0x21, 0 + .dw 0x9940, 0xc98e, 0x997f, 0xc98e, 0x21, 0 + .dw 0x99c0, 0xc98e, 0x9fff, 0xc98e, 0x21, 0 + .dw 0xa040, 0xc98e, 0xa07f, 0xc98e, 0x21, 0 + .dw 0xa0c0, 0xc98e, 0xa0ff, 0xc98e, 0x21, 0 + .dw 0xa140, 0xc98e, 0xa17f, 0xc98e, 0x21, 0 + .dw 0xa1c0, 0xc98e, 0xa1ff, 0xc98e, 0x21, 0 + .dw 0xa240, 0xc98e, 0xa27f, 0xc98e, 0x21, 0 + .dw 0xa2c0, 0xc98e, 0xa2ff, 0xc98e, 0x21, 0 + .dw 0xa340, 0xc98e, 0xa37f, 0xc98e, 0x21, 0 + .dw 0xa3c0, 0xc98e, 0xa3ff, 0xc98e, 0x21, 0 + .dw 0xa440, 0xc98e, 0xa47f, 0xc98e, 0x21, 0 + .dw 0xa4c0, 0xc98e, 0xa4ff, 0xc98e, 0x21, 0 + .dw 0xa540, 0xc98e, 0xa57f, 0xc98e, 0x21, 0 + .dw 0xa5c0, 0xc98e, 0xa5ff, 0xc98e, 0x21, 0 + .dw 0xa640, 0xc98e, 0xa67f, 0xc98e, 0x21, 0 + .dw 0xa6c0, 0xc98e, 0xa6ff, 0xc98e, 0x21, 0 + .dw 0xa740, 0xc98e, 0xa77f, 0xc98e, 0x21, 0 + .dw 0xa7c0, 0xc98e, 0xa7ff, 0xc98e, 0x21, 0 + .dw 0xa840, 0xc98e, 0xa87f, 0xc98e, 0x21, 0 + .dw 0xa8c0, 0xc98e, 0xa8ff, 0xc98e, 0x21, 0 + .dw 0xa940, 0xc98e, 0xa97f, 0xc98e, 0x21, 0 + .dw 0xa9c0, 0xc98e, 0xa9ff, 0xc98e, 0x21, 0 + .dw 0xaa40, 0xc98e, 0xaa7f, 0xc98e, 0x21, 0 + .dw 0xaac0, 0xc98e, 0xaaff, 0xc98e, 0x21, 0 + .dw 0xab40, 0xc98e, 0xab7f, 0xc98e, 0x21, 0 + .dw 0xabc0, 0xc98e, 0xabff, 0xc98e, 0x21, 0 + .dw 0xac40, 0xc98e, 0xac7f, 0xc98e, 0x21, 0 + .dw 0xacc0, 0xc98e, 0xacff, 0xc98e, 0x21, 0 + .dw 0xad40, 0xc98e, 0xad7f, 0xc98e, 0x21, 0 + .dw 0xadc0, 0xc98e, 0xadff, 0xc98e, 0x21, 0 + .dw 0xae40, 0xc98e, 0xae7f, 0xc98e, 0x21, 0 + .dw 0xaec0, 0xc98e, 0xaeff, 0xc98e, 0x21, 0 + .dw 0xaf40, 0xc98e, 0xaf7f, 0xc98e, 0x21, 0 + .dw 0xafc0, 0xc98e, 0xafff, 0xc98e, 0x21, 0 + .dw 0xb040, 0xc98e, 0xb07f, 0xc98e, 0x21, 0 + .dw 0xb0c0, 0xc98e, 0xb0ff, 0xc98e, 0x21, 0 + .dw 0xb140, 0xc98e, 0xb17f, 0xc98e, 0x21, 0 + .dw 0xb1c0, 0xc98e, 0xb1ff, 0xc98e, 0x21, 0 + .dw 0xb240, 0xc98e, 0xb27f, 0xc98e, 0x21, 0 + .dw 0xb2c0, 0xc98e, 0xb2ff, 0xc98e, 0x21, 0 + .dw 0xb340, 0xc98e, 0xb37f, 0xc98e, 0x21, 0 + .dw 0xb3c0, 0xc98e, 0xb3ff, 0xc98e, 0x21, 0 + .dw 0xb440, 0xc98e, 0xb47f, 0xc98e, 0x21, 0 + .dw 0xb4c0, 0xc98e, 0xb4ff, 0xc98e, 0x21, 0 + .dw 0xb540, 0xc98e, 0xb57f, 0xc98e, 0x21, 0 + .dw 0xb5c0, 0xc98e, 0xb5ff, 0xc98e, 0x21, 0 + .dw 0xb640, 0xc98e, 0xb67f, 0xc98e, 0x21, 0 + .dw 0xb6c0, 0xc98e, 0xb6ff, 0xc98e, 0x21, 0 + .dw 0xb740, 0xc98e, 0xb77f, 0xc98e, 0x21, 0 + .dw 0xb7c0, 0xc98e, 0xb7ff, 0xc98e, 0x21, 0 + .dw 0xb840, 0xc98e, 0xb87f, 0xc98e, 0x21, 0 + .dw 0xb8c0, 0xc98e, 0xb8ff, 0xc98e, 0x21, 0 + .dw 0xb940, 0xc98e, 0xb97f, 0xc98e, 0x21, 0 + .dw 0xb9c0, 0xc98e, 0xbfff, 0xc98e, 0x21, 0 + .dw 0xc040, 0xc98e, 0xc07f, 0xc98e, 0x21, 0 + .dw 0xc0c0, 0xc98e, 0xc0ff, 0xc98e, 0x21, 0 + .dw 0xc140, 0xc98e, 0xc17f, 0xc98e, 0x21, 0 + .dw 0xc1c0, 0xc98e, 0xc1ff, 0xc98e, 0x21, 0 + .dw 0xc240, 0xc98e, 0xc27f, 0xc98e, 0x21, 0 + .dw 0xc2c0, 0xc98e, 0xc2ff, 0xc98e, 0x21, 0 + .dw 0xc340, 0xc98e, 0xc37f, 0xc98e, 0x21, 0 + .dw 0xc3c0, 0xc98e, 0xc3ff, 0xc98e, 0x21, 0 + .dw 0xc440, 0xc98e, 0xc47f, 0xc98e, 0x21, 0 + .dw 0xc4c0, 0xc98e, 0xc4ff, 0xc98e, 0x21, 0 + .dw 0xc540, 0xc98e, 0xc57f, 0xc98e, 0x21, 0 + .dw 0xc5c0, 0xc98e, 0xc5ff, 0xc98e, 0x21, 0 + .dw 0xc640, 0xc98e, 0xc67f, 0xc98e, 0x21, 0 + .dw 0xc6c0, 0xc98e, 0xc6ff, 0xc98e, 0x21, 0 + .dw 0xc740, 0xc98e, 0xc77f, 0xc98e, 0x21, 0 + .dw 0xc7c0, 0xc98e, 0xc7ff, 0xc98e, 0x21, 0 + .dw 0xc840, 0xc98e, 0xc87f, 0xc98e, 0x21, 0 + .dw 0xc8c0, 0xc98e, 0xc8ff, 0xc98e, 0x21, 0 + .dw 0xc940, 0xc98e, 0xc97f, 0xc98e, 0x21, 0 + .dw 0xc9c0, 0xc98e, 0xc9ff, 0xc98e, 0x21, 0 + .dw 0xca40, 0xc98e, 0xca7f, 0xc98e, 0x21, 0 + .dw 0xcac0, 0xc98e, 0xcaff, 0xc98e, 0x21, 0 + .dw 0xcb40, 0xc98e, 0xcb7f, 0xc98e, 0x21, 0 + .dw 0xcbc0, 0xc98e, 0xcbff, 0xc98e, 0x21, 0 + .dw 0xcc40, 0xc98e, 0xcc7f, 0xc98e, 0x21, 0 + .dw 0xccc0, 0xc98e, 0xccff, 0xc98e, 0x21, 0 + .dw 0xcd40, 0xc98e, 0xcd7f, 0xc98e, 0x21, 0 + .dw 0xcdc0, 0xc98e, 0xcdff, 0xc98e, 0x21, 0 + .dw 0xce40, 0xc98e, 0xce7f, 0xc98e, 0x21, 0 + .dw 0xcec0, 0xc98e, 0xceff, 0xc98e, 0x21, 0 + .dw 0xcf40, 0xc98e, 0xcf7f, 0xc98e, 0x21, 0 + .dw 0xcfc0, 0xc98e, 0xcfff, 0xc98e, 0x21, 0 + .dw 0xd040, 0xc98e, 0xd07f, 0xc98e, 0x21, 0 + .dw 0xd0c0, 0xc98e, 0xd0ff, 0xc98e, 0x21, 0 + .dw 0xd140, 0xc98e, 0xd17f, 0xc98e, 0x21, 0 + .dw 0xd1c0, 0xc98e, 0xd1ff, 0xc98e, 0x21, 0 + .dw 0xd240, 0xc98e, 0xd27f, 0xc98e, 0x21, 0 + .dw 0xd2c0, 0xc98e, 0xd2ff, 0xc98e, 0x21, 0 + .dw 0xd340, 0xc98e, 0xd37f, 0xc98e, 0x21, 0 + .dw 0xd3c0, 0xc98e, 0xd3ff, 0xc98e, 0x21, 0 + .dw 0xd440, 0xc98e, 0xd47f, 0xc98e, 0x21, 0 + .dw 0xd4c0, 0xc98e, 0xd4ff, 0xc98e, 0x21, 0 + .dw 0xd540, 0xc98e, 0xd57f, 0xc98e, 0x21, 0 + .dw 0xd5c0, 0xc98e, 0xd5ff, 0xc98e, 0x21, 0 + .dw 0xd640, 0xc98e, 0xd67f, 0xc98e, 0x21, 0 + .dw 0xd6c0, 0xc98e, 0xd6ff, 0xc98e, 0x21, 0 + .dw 0xd740, 0xc98e, 0xd77f, 0xc98e, 0x21, 0 + .dw 0xd7c0, 0xc98e, 0xd7ff, 0xc98e, 0x21, 0 + .dw 0xd840, 0xc98e, 0xd87f, 0xc98e, 0x21, 0 + .dw 0xd8c0, 0xc98e, 0xd8ff, 0xc98e, 0x21, 0 + .dw 0xd940, 0xc98e, 0xd97f, 0xc98e, 0x21, 0 + .dw 0xd9c0, 0xc98e, 0xdfff, 0xc98e, 0x21, 0 + .dw 0xe040, 0xc98e, 0xe07f, 0xc98e, 0x21, 0 + .dw 0xe0c0, 0xc98e, 0xe0ff, 0xc98e, 0x21, 0 + .dw 0xe140, 0xc98e, 0xe17f, 0xc98e, 0x21, 0 + .dw 0xe1c0, 0xc98e, 0xe1ff, 0xc98e, 0x21, 0 + .dw 0xe240, 0xc98e, 0xe27f, 0xc98e, 0x21, 0 + .dw 0xe2c0, 0xc98e, 0xe2ff, 0xc98e, 0x21, 0 + .dw 0xe340, 0xc98e, 0xe37f, 0xc98e, 0x21, 0 + .dw 0xe3c0, 0xc98e, 0xe3ff, 0xc98e, 0x21, 0 + .dw 0xe440, 0xc98e, 0xe47f, 0xc98e, 0x21, 0 + .dw 0xe4c0, 0xc98e, 0xe4ff, 0xc98e, 0x21, 0 + .dw 0xe540, 0xc98e, 0xe57f, 0xc98e, 0x21, 0 + .dw 0xe5c0, 0xc98e, 0xe5ff, 0xc98e, 0x21, 0 + .dw 0xe640, 0xc98e, 0xe67f, 0xc98e, 0x21, 0 + .dw 0xe6c0, 0xc98e, 0xe6ff, 0xc98e, 0x21, 0 + .dw 0xe740, 0xc98e, 0xe77f, 0xc98e, 0x21, 0 + .dw 0xe7c0, 0xc98e, 0xe7ff, 0xc98e, 0x21, 0 + .dw 0xe840, 0xc98e, 0xe87f, 0xc98e, 0x21, 0 + .dw 0xe8c0, 0xc98e, 0xe8ff, 0xc98e, 0x21, 0 + .dw 0xe940, 0xc98e, 0xe97f, 0xc98e, 0x21, 0 + .dw 0xe9c0, 0xc98e, 0xe9ff, 0xc98e, 0x21, 0 + .dw 0xea40, 0xc98e, 0xea7f, 0xc98e, 0x21, 0 + .dw 0xeac0, 0xc98e, 0xeaff, 0xc98e, 0x21, 0 + .dw 0xeb40, 0xc98e, 0xeb7f, 0xc98e, 0x21, 0 + .dw 0xebc0, 0xc98e, 0xebff, 0xc98e, 0x21, 0 + .dw 0xec40, 0xc98e, 0xec7f, 0xc98e, 0x21, 0 + .dw 0xecc0, 0xc98e, 0xecff, 0xc98e, 0x21, 0 + .dw 0xed40, 0xc98e, 0xed7f, 0xc98e, 0x21, 0 + .dw 0xedc0, 0xc98e, 0xedff, 0xc98e, 0x21, 0 + .dw 0xee40, 0xc98e, 0xee7f, 0xc98e, 0x21, 0 + .dw 0xeec0, 0xc98e, 0xeeff, 0xc98e, 0x21, 0 + .dw 0xef40, 0xc98e, 0xef7f, 0xc98e, 0x21, 0 + .dw 0xefc0, 0xc98e, 0xefff, 0xc98e, 0x21, 0 + .dw 0xf040, 0xc98e, 0xf07f, 0xc98e, 0x21, 0 + .dw 0xf0c0, 0xc98e, 0xf0ff, 0xc98e, 0x21, 0 + .dw 0xf140, 0xc98e, 0xf17f, 0xc98e, 0x21, 0 + .dw 0xf1c0, 0xc98e, 0xf1ff, 0xc98e, 0x21, 0 + .dw 0xf240, 0xc98e, 0xf27f, 0xc98e, 0x21, 0 + .dw 0xf2c0, 0xc98e, 0xf2ff, 0xc98e, 0x21, 0 + .dw 0xf340, 0xc98e, 0xf37f, 0xc98e, 0x21, 0 + .dw 0xf3c0, 0xc98e, 0xf3ff, 0xc98e, 0x21, 0 + .dw 0xf440, 0xc98e, 0xf47f, 0xc98e, 0x21, 0 + .dw 0xf4c0, 0xc98e, 0xf4ff, 0xc98e, 0x21, 0 + .dw 0xf540, 0xc98e, 0xf57f, 0xc98e, 0x21, 0 + .dw 0xf5c0, 0xc98e, 0xf5ff, 0xc98e, 0x21, 0 + .dw 0xf640, 0xc98e, 0xf67f, 0xc98e, 0x21, 0 + .dw 0xf6c0, 0xc98e, 0xf6ff, 0xc98e, 0x21, 0 + .dw 0xf740, 0xc98e, 0xf77f, 0xc98e, 0x21, 0 + .dw 0xf7c0, 0xc98e, 0xf7ff, 0xc98e, 0x21, 0 + .dw 0xf840, 0xc98e, 0xf87f, 0xc98e, 0x21, 0 + .dw 0xf8c0, 0xc98e, 0xf8ff, 0xc98e, 0x21, 0 + .dw 0xf940, 0xc98e, 0xf97f, 0xc98e, 0x21, 0 + .dw 0xf9c0, 0xc98e, 0xffff, 0xc98e, 0x21, 0 + .dw 0x0040, 0xc98f, 0x007f, 0xc98f, 0x21, 0 + .dw 0x00c0, 0xc98f, 0x00ff, 0xc98f, 0x21, 0 + .dw 0x0140, 0xc98f, 0x017f, 0xc98f, 0x21, 0 + .dw 0x01c0, 0xc98f, 0x01ff, 0xc98f, 0x21, 0 + .dw 0x0240, 0xc98f, 0x027f, 0xc98f, 0x21, 0 + .dw 0x02c0, 0xc98f, 0x02ff, 0xc98f, 0x21, 0 + .dw 0x0340, 0xc98f, 0x037f, 0xc98f, 0x21, 0 + .dw 0x03c0, 0xc98f, 0x03ff, 0xc98f, 0x21, 0 + .dw 0x0440, 0xc98f, 0x047f, 0xc98f, 0x21, 0 + .dw 0x04c0, 0xc98f, 0x04ff, 0xc98f, 0x21, 0 + .dw 0x0540, 0xc98f, 0x057f, 0xc98f, 0x21, 0 + .dw 0x05c0, 0xc98f, 0x05ff, 0xc98f, 0x21, 0 + .dw 0x0640, 0xc98f, 0x067f, 0xc98f, 0x21, 0 + .dw 0x06c0, 0xc98f, 0x06ff, 0xc98f, 0x21, 0 + .dw 0x0740, 0xc98f, 0x077f, 0xc98f, 0x21, 0 + .dw 0x07c0, 0xc98f, 0x07ff, 0xc98f, 0x21, 0 + .dw 0x0840, 0xc98f, 0x087f, 0xc98f, 0x21, 0 + .dw 0x08c0, 0xc98f, 0x08ff, 0xc98f, 0x21, 0 + .dw 0x0940, 0xc98f, 0x097f, 0xc98f, 0x21, 0 + .dw 0x09c0, 0xc98f, 0x09ff, 0xc98f, 0x21, 0 + .dw 0x0a40, 0xc98f, 0x0a7f, 0xc98f, 0x21, 0 + .dw 0x0ac0, 0xc98f, 0x0aff, 0xc98f, 0x21, 0 + .dw 0x0b40, 0xc98f, 0x0b7f, 0xc98f, 0x21, 0 + .dw 0x0bc0, 0xc98f, 0x0bff, 0xc98f, 0x21, 0 + .dw 0x0c40, 0xc98f, 0x0c7f, 0xc98f, 0x21, 0 + .dw 0x0cc0, 0xc98f, 0x0cff, 0xc98f, 0x21, 0 + .dw 0x0d40, 0xc98f, 0x0d7f, 0xc98f, 0x21, 0 + .dw 0x0dc0, 0xc98f, 0x0dff, 0xc98f, 0x21, 0 + .dw 0x0e40, 0xc98f, 0x0e7f, 0xc98f, 0x21, 0 + .dw 0x0ec0, 0xc98f, 0x0eff, 0xc98f, 0x21, 0 + .dw 0x0f40, 0xc98f, 0x0f7f, 0xc98f, 0x21, 0 + .dw 0x0fc0, 0xc98f, 0x0fff, 0xc98f, 0x21, 0 + .dw 0x1040, 0xc98f, 0x107f, 0xc98f, 0x21, 0 + .dw 0x10c0, 0xc98f, 0x10ff, 0xc98f, 0x21, 0 + .dw 0x1140, 0xc98f, 0x117f, 0xc98f, 0x21, 0 + .dw 0x11c0, 0xc98f, 0x11ff, 0xc98f, 0x21, 0 + .dw 0x1240, 0xc98f, 0x127f, 0xc98f, 0x21, 0 + .dw 0x12c0, 0xc98f, 0x12ff, 0xc98f, 0x21, 0 + .dw 0x1340, 0xc98f, 0x137f, 0xc98f, 0x21, 0 + .dw 0x13c0, 0xc98f, 0x13ff, 0xc98f, 0x21, 0 + .dw 0x1440, 0xc98f, 0x147f, 0xc98f, 0x21, 0 + .dw 0x14c0, 0xc98f, 0x14ff, 0xc98f, 0x21, 0 + .dw 0x1540, 0xc98f, 0x157f, 0xc98f, 0x21, 0 + .dw 0x15c0, 0xc98f, 0x15ff, 0xc98f, 0x21, 0 + .dw 0x1640, 0xc98f, 0x167f, 0xc98f, 0x21, 0 + .dw 0x16c0, 0xc98f, 0x16ff, 0xc98f, 0x21, 0 + .dw 0x1740, 0xc98f, 0x177f, 0xc98f, 0x21, 0 + .dw 0x17c0, 0xc98f, 0x17ff, 0xc98f, 0x21, 0 + .dw 0x1840, 0xc98f, 0x187f, 0xc98f, 0x21, 0 + .dw 0x18c0, 0xc98f, 0x18ff, 0xc98f, 0x21, 0 + .dw 0x1940, 0xc98f, 0x197f, 0xc98f, 0x21, 0 + .dw 0x19c0, 0xc98f, 0x1fff, 0xc98f, 0x21, 0 + .dw 0x2040, 0xc98f, 0x207f, 0xc98f, 0x21, 0 + .dw 0x20c0, 0xc98f, 0x20ff, 0xc98f, 0x21, 0 + .dw 0x2140, 0xc98f, 0x217f, 0xc98f, 0x21, 0 + .dw 0x21c0, 0xc98f, 0x21ff, 0xc98f, 0x21, 0 + .dw 0x2240, 0xc98f, 0x227f, 0xc98f, 0x21, 0 + .dw 0x22c0, 0xc98f, 0x22ff, 0xc98f, 0x21, 0 + .dw 0x2340, 0xc98f, 0x237f, 0xc98f, 0x21, 0 + .dw 0x23c0, 0xc98f, 0x23ff, 0xc98f, 0x21, 0 + .dw 0x2440, 0xc98f, 0x247f, 0xc98f, 0x21, 0 + .dw 0x24c0, 0xc98f, 0x24ff, 0xc98f, 0x21, 0 + .dw 0x2540, 0xc98f, 0x257f, 0xc98f, 0x21, 0 + .dw 0x25c0, 0xc98f, 0x25ff, 0xc98f, 0x21, 0 + .dw 0x2640, 0xc98f, 0x267f, 0xc98f, 0x21, 0 + .dw 0x26c0, 0xc98f, 0x26ff, 0xc98f, 0x21, 0 + .dw 0x2740, 0xc98f, 0x277f, 0xc98f, 0x21, 0 + .dw 0x27c0, 0xc98f, 0x27ff, 0xc98f, 0x21, 0 + .dw 0x2840, 0xc98f, 0x287f, 0xc98f, 0x21, 0 + .dw 0x28c0, 0xc98f, 0x28ff, 0xc98f, 0x21, 0 + .dw 0x2940, 0xc98f, 0x297f, 0xc98f, 0x21, 0 + .dw 0x29c0, 0xc98f, 0x29ff, 0xc98f, 0x21, 0 + .dw 0x2a40, 0xc98f, 0x2a7f, 0xc98f, 0x21, 0 + .dw 0x2ac0, 0xc98f, 0x2aff, 0xc98f, 0x21, 0 + .dw 0x2b40, 0xc98f, 0x2b7f, 0xc98f, 0x21, 0 + .dw 0x2bc0, 0xc98f, 0x2bff, 0xc98f, 0x21, 0 + .dw 0x2c40, 0xc98f, 0x2c7f, 0xc98f, 0x21, 0 + .dw 0x2cc0, 0xc98f, 0x2cff, 0xc98f, 0x21, 0 + .dw 0x2d40, 0xc98f, 0x2d7f, 0xc98f, 0x21, 0 + .dw 0x2dc0, 0xc98f, 0x2dff, 0xc98f, 0x21, 0 + .dw 0x2e40, 0xc98f, 0x2e7f, 0xc98f, 0x21, 0 + .dw 0x2ec0, 0xc98f, 0x2eff, 0xc98f, 0x21, 0 + .dw 0x2f40, 0xc98f, 0x2f7f, 0xc98f, 0x21, 0 + .dw 0x2fc0, 0xc98f, 0x2fff, 0xc98f, 0x21, 0 + .dw 0x3040, 0xc98f, 0x307f, 0xc98f, 0x21, 0 + .dw 0x30c0, 0xc98f, 0x30ff, 0xc98f, 0x21, 0 + .dw 0x3140, 0xc98f, 0x317f, 0xc98f, 0x21, 0 + .dw 0x31c0, 0xc98f, 0x31ff, 0xc98f, 0x21, 0 + .dw 0x3240, 0xc98f, 0x327f, 0xc98f, 0x21, 0 + .dw 0x32c0, 0xc98f, 0x32ff, 0xc98f, 0x21, 0 + .dw 0x3340, 0xc98f, 0x337f, 0xc98f, 0x21, 0 + .dw 0x33c0, 0xc98f, 0x33ff, 0xc98f, 0x21, 0 + .dw 0x3440, 0xc98f, 0x347f, 0xc98f, 0x21, 0 + .dw 0x34c0, 0xc98f, 0x34ff, 0xc98f, 0x21, 0 + .dw 0x3540, 0xc98f, 0x357f, 0xc98f, 0x21, 0 + .dw 0x35c0, 0xc98f, 0x35ff, 0xc98f, 0x21, 0 + .dw 0x3640, 0xc98f, 0x367f, 0xc98f, 0x21, 0 + .dw 0x36c0, 0xc98f, 0x36ff, 0xc98f, 0x21, 0 + .dw 0x3740, 0xc98f, 0x377f, 0xc98f, 0x21, 0 + .dw 0x37c0, 0xc98f, 0x37ff, 0xc98f, 0x21, 0 + .dw 0x3840, 0xc98f, 0x387f, 0xc98f, 0x21, 0 + .dw 0x38c0, 0xc98f, 0x38ff, 0xc98f, 0x21, 0 + .dw 0x3940, 0xc98f, 0x397f, 0xc98f, 0x21, 0 + .dw 0x39c0, 0xc98f, 0x1fff, 0xc990, 0x21, 0 + .dw 0x3a00, 0xc990, 0x5fff, 0xc990, 0x21, 0 + .dw 0x7a00, 0xc990, 0x9fff, 0xc990, 0x21, 0 + .dw 0xba00, 0xc990, 0xdfff, 0xc990, 0x21, 0 + .dw 0xfa00, 0xc990, 0x1fff, 0xc991, 0x21, 0 + .dw 0x3a00, 0xc991, 0x5fff, 0xc991, 0x21, 0 + .dw 0x7a00, 0xc991, 0x9fff, 0xc991, 0x21, 0 + .dw 0xba00, 0xc991, 0xdfff, 0xc991, 0x21, 0 + .dw 0xfa00, 0xc991, 0x1fff, 0xc992, 0x21, 0 + .dw 0x3a00, 0xc992, 0x5fff, 0xc992, 0x21, 0 + .dw 0x7a00, 0xc992, 0x9fff, 0xc992, 0x21, 0 + .dw 0xba00, 0xc992, 0xdfff, 0xc992, 0x21, 0 + .dw 0xfa00, 0xc992, 0xffff, 0xc993, 0x21, 0 + .dw 0x1a00, 0xc994, 0x1fff, 0xc994, 0x21, 0 + .dw 0x3a00, 0xc994, 0x3fff, 0xc994, 0x21, 0 + .dw 0x5a00, 0xc994, 0x5fff, 0xc994, 0x21, 0 + .dw 0x7a00, 0xc994, 0x7fff, 0xc994, 0x21, 0 + .dw 0x9a00, 0xc994, 0x9fff, 0xc994, 0x21, 0 + .dw 0xba00, 0xc994, 0xbfff, 0xc994, 0x21, 0 + .dw 0xda00, 0xc994, 0xdfff, 0xc994, 0x21, 0 + .dw 0xfa00, 0xc994, 0xffff, 0xc994, 0x21, 0 + .dw 0x1a00, 0xc995, 0x1fff, 0xc995, 0x21, 0 + .dw 0x3a00, 0xc995, 0x3fff, 0xc995, 0x21, 0 + .dw 0x5a00, 0xc995, 0x5fff, 0xc995, 0x21, 0 + .dw 0x7a00, 0xc995, 0x7fff, 0xc995, 0x21, 0 + .dw 0x9a00, 0xc995, 0x9fff, 0xc995, 0x21, 0 + .dw 0xba00, 0xc995, 0xbfff, 0xc995, 0x21, 0 + .dw 0xda00, 0xc995, 0xdfff, 0xc995, 0x21, 0 + .dw 0xfa00, 0xc995, 0xffff, 0xc995, 0x21, 0 + .dw 0x1a00, 0xc996, 0x1fff, 0xc996, 0x21, 0 + .dw 0x3a00, 0xc996, 0x3fff, 0xc996, 0x21, 0 + .dw 0x5a00, 0xc996, 0x5fff, 0xc996, 0x21, 0 + .dw 0x7a00, 0xc996, 0x7fff, 0xc996, 0x21, 0 + .dw 0x9a00, 0xc996, 0x9fff, 0xc996, 0x21, 0 + .dw 0xba00, 0xc996, 0xbfff, 0xc996, 0x21, 0 + .dw 0xda00, 0xc996, 0xdfff, 0xc996, 0x21, 0 + .dw 0xfa00, 0xc996, 0xffff, 0xc996, 0x21, 0 + .dw 0x1a00, 0xc997, 0x1fff, 0xc997, 0x21, 0 + .dw 0x3a00, 0xc997, 0x1fff, 0xc998, 0x21, 0 + .dw 0x2040, 0xc998, 0x207f, 0xc998, 0x21, 0 + .dw 0x20c0, 0xc998, 0x20ff, 0xc998, 0x21, 0 + .dw 0x2140, 0xc998, 0x217f, 0xc998, 0x21, 0 + .dw 0x21c0, 0xc998, 0x21ff, 0xc998, 0x21, 0 + .dw 0x2240, 0xc998, 0x227f, 0xc998, 0x21, 0 + .dw 0x22c0, 0xc998, 0x22ff, 0xc998, 0x21, 0 + .dw 0x2340, 0xc998, 0x237f, 0xc998, 0x21, 0 + .dw 0x23c0, 0xc998, 0x23ff, 0xc998, 0x21, 0 + .dw 0x2440, 0xc998, 0x247f, 0xc998, 0x21, 0 + .dw 0x24c0, 0xc998, 0x24ff, 0xc998, 0x21, 0 + .dw 0x2540, 0xc998, 0x257f, 0xc998, 0x21, 0 + .dw 0x25c0, 0xc998, 0x25ff, 0xc998, 0x21, 0 + .dw 0x2640, 0xc998, 0x267f, 0xc998, 0x21, 0 + .dw 0x26c0, 0xc998, 0x26ff, 0xc998, 0x21, 0 + .dw 0x2740, 0xc998, 0x277f, 0xc998, 0x21, 0 + .dw 0x27c0, 0xc998, 0x27ff, 0xc998, 0x21, 0 + .dw 0x2840, 0xc998, 0x287f, 0xc998, 0x21, 0 + .dw 0x28c0, 0xc998, 0x28ff, 0xc998, 0x21, 0 + .dw 0x2940, 0xc998, 0x297f, 0xc998, 0x21, 0 + .dw 0x29c0, 0xc998, 0x29ff, 0xc998, 0x21, 0 + .dw 0x2a40, 0xc998, 0x2a7f, 0xc998, 0x21, 0 + .dw 0x2ac0, 0xc998, 0x2aff, 0xc998, 0x21, 0 + .dw 0x2b40, 0xc998, 0x2b7f, 0xc998, 0x21, 0 + .dw 0x2bc0, 0xc998, 0x2bff, 0xc998, 0x21, 0 + .dw 0x2c40, 0xc998, 0x2c7f, 0xc998, 0x21, 0 + .dw 0x2cc0, 0xc998, 0x2cff, 0xc998, 0x21, 0 + .dw 0x2d40, 0xc998, 0x2d7f, 0xc998, 0x21, 0 + .dw 0x2dc0, 0xc998, 0x2dff, 0xc998, 0x21, 0 + .dw 0x2e40, 0xc998, 0x2e7f, 0xc998, 0x21, 0 + .dw 0x2ec0, 0xc998, 0x2eff, 0xc998, 0x21, 0 + .dw 0x2f40, 0xc998, 0x2f7f, 0xc998, 0x21, 0 + .dw 0x2fc0, 0xc998, 0x2fff, 0xc998, 0x21, 0 + .dw 0x3040, 0xc998, 0x307f, 0xc998, 0x21, 0 + .dw 0x30c0, 0xc998, 0x30ff, 0xc998, 0x21, 0 + .dw 0x3140, 0xc998, 0x317f, 0xc998, 0x21, 0 + .dw 0x31c0, 0xc998, 0x31ff, 0xc998, 0x21, 0 + .dw 0x3240, 0xc998, 0x327f, 0xc998, 0x21, 0 + .dw 0x32c0, 0xc998, 0x32ff, 0xc998, 0x21, 0 + .dw 0x3340, 0xc998, 0x337f, 0xc998, 0x21, 0 + .dw 0x33c0, 0xc998, 0x33ff, 0xc998, 0x21, 0 + .dw 0x3440, 0xc998, 0x347f, 0xc998, 0x21, 0 + .dw 0x34c0, 0xc998, 0x34ff, 0xc998, 0x21, 0 + .dw 0x3540, 0xc998, 0x357f, 0xc998, 0x21, 0 + .dw 0x35c0, 0xc998, 0x35ff, 0xc998, 0x21, 0 + .dw 0x3640, 0xc998, 0x367f, 0xc998, 0x21, 0 + .dw 0x36c0, 0xc998, 0x36ff, 0xc998, 0x21, 0 + .dw 0x3740, 0xc998, 0x377f, 0xc998, 0x21, 0 + .dw 0x37c0, 0xc998, 0x37ff, 0xc998, 0x21, 0 + .dw 0x3840, 0xc998, 0x387f, 0xc998, 0x21, 0 + .dw 0x38c0, 0xc998, 0x38ff, 0xc998, 0x21, 0 + .dw 0x3940, 0xc998, 0x397f, 0xc998, 0x21, 0 + .dw 0x39c0, 0xc998, 0x5fff, 0xc998, 0x21, 0 + .dw 0x6040, 0xc998, 0x607f, 0xc998, 0x21, 0 + .dw 0x60c0, 0xc998, 0x60ff, 0xc998, 0x21, 0 + .dw 0x6140, 0xc998, 0x617f, 0xc998, 0x21, 0 + .dw 0x61c0, 0xc998, 0x61ff, 0xc998, 0x21, 0 + .dw 0x6240, 0xc998, 0x627f, 0xc998, 0x21, 0 + .dw 0x62c0, 0xc998, 0x62ff, 0xc998, 0x21, 0 + .dw 0x6340, 0xc998, 0x637f, 0xc998, 0x21, 0 + .dw 0x63c0, 0xc998, 0x63ff, 0xc998, 0x21, 0 + .dw 0x6440, 0xc998, 0x647f, 0xc998, 0x21, 0 + .dw 0x64c0, 0xc998, 0x64ff, 0xc998, 0x21, 0 + .dw 0x6540, 0xc998, 0x657f, 0xc998, 0x21, 0 + .dw 0x65c0, 0xc998, 0x65ff, 0xc998, 0x21, 0 + .dw 0x6640, 0xc998, 0x667f, 0xc998, 0x21, 0 + .dw 0x66c0, 0xc998, 0x66ff, 0xc998, 0x21, 0 + .dw 0x6740, 0xc998, 0x677f, 0xc998, 0x21, 0 + .dw 0x67c0, 0xc998, 0x67ff, 0xc998, 0x21, 0 + .dw 0x6840, 0xc998, 0x687f, 0xc998, 0x21, 0 + .dw 0x68c0, 0xc998, 0x68ff, 0xc998, 0x21, 0 + .dw 0x6940, 0xc998, 0x697f, 0xc998, 0x21, 0 + .dw 0x69c0, 0xc998, 0x69ff, 0xc998, 0x21, 0 + .dw 0x6a40, 0xc998, 0x6a7f, 0xc998, 0x21, 0 + .dw 0x6ac0, 0xc998, 0x6aff, 0xc998, 0x21, 0 + .dw 0x6b40, 0xc998, 0x6b7f, 0xc998, 0x21, 0 + .dw 0x6bc0, 0xc998, 0x6bff, 0xc998, 0x21, 0 + .dw 0x6c40, 0xc998, 0x6c7f, 0xc998, 0x21, 0 + .dw 0x6cc0, 0xc998, 0x6cff, 0xc998, 0x21, 0 + .dw 0x6d40, 0xc998, 0x6d7f, 0xc998, 0x21, 0 + .dw 0x6dc0, 0xc998, 0x6dff, 0xc998, 0x21, 0 + .dw 0x6e40, 0xc998, 0x6e7f, 0xc998, 0x21, 0 + .dw 0x6ec0, 0xc998, 0x6eff, 0xc998, 0x21, 0 + .dw 0x6f40, 0xc998, 0x6f7f, 0xc998, 0x21, 0 + .dw 0x6fc0, 0xc998, 0x6fff, 0xc998, 0x21, 0 + .dw 0x7040, 0xc998, 0x707f, 0xc998, 0x21, 0 + .dw 0x70c0, 0xc998, 0x70ff, 0xc998, 0x21, 0 + .dw 0x7140, 0xc998, 0x717f, 0xc998, 0x21, 0 + .dw 0x71c0, 0xc998, 0x71ff, 0xc998, 0x21, 0 + .dw 0x7240, 0xc998, 0x727f, 0xc998, 0x21, 0 + .dw 0x72c0, 0xc998, 0x72ff, 0xc998, 0x21, 0 + .dw 0x7340, 0xc998, 0x737f, 0xc998, 0x21, 0 + .dw 0x73c0, 0xc998, 0x73ff, 0xc998, 0x21, 0 + .dw 0x7440, 0xc998, 0x747f, 0xc998, 0x21, 0 + .dw 0x74c0, 0xc998, 0x74ff, 0xc998, 0x21, 0 + .dw 0x7540, 0xc998, 0x757f, 0xc998, 0x21, 0 + .dw 0x75c0, 0xc998, 0x75ff, 0xc998, 0x21, 0 + .dw 0x7640, 0xc998, 0x767f, 0xc998, 0x21, 0 + .dw 0x76c0, 0xc998, 0x76ff, 0xc998, 0x21, 0 + .dw 0x7740, 0xc998, 0x777f, 0xc998, 0x21, 0 + .dw 0x77c0, 0xc998, 0x77ff, 0xc998, 0x21, 0 + .dw 0x7840, 0xc998, 0x787f, 0xc998, 0x21, 0 + .dw 0x78c0, 0xc998, 0x78ff, 0xc998, 0x21, 0 + .dw 0x7940, 0xc998, 0x797f, 0xc998, 0x21, 0 + .dw 0x79c0, 0xc998, 0x9fff, 0xc998, 0x21, 0 + .dw 0xa040, 0xc998, 0xa07f, 0xc998, 0x21, 0 + .dw 0xa0c0, 0xc998, 0xa0ff, 0xc998, 0x21, 0 + .dw 0xa140, 0xc998, 0xa17f, 0xc998, 0x21, 0 + .dw 0xa1c0, 0xc998, 0xa1ff, 0xc998, 0x21, 0 + .dw 0xa240, 0xc998, 0xa27f, 0xc998, 0x21, 0 + .dw 0xa2c0, 0xc998, 0xa2ff, 0xc998, 0x21, 0 + .dw 0xa340, 0xc998, 0xa37f, 0xc998, 0x21, 0 + .dw 0xa3c0, 0xc998, 0xa3ff, 0xc998, 0x21, 0 + .dw 0xa440, 0xc998, 0xa47f, 0xc998, 0x21, 0 + .dw 0xa4c0, 0xc998, 0xa4ff, 0xc998, 0x21, 0 + .dw 0xa540, 0xc998, 0xa57f, 0xc998, 0x21, 0 + .dw 0xa5c0, 0xc998, 0xa5ff, 0xc998, 0x21, 0 + .dw 0xa640, 0xc998, 0xa67f, 0xc998, 0x21, 0 + .dw 0xa6c0, 0xc998, 0xa6ff, 0xc998, 0x21, 0 + .dw 0xa740, 0xc998, 0xa77f, 0xc998, 0x21, 0 + .dw 0xa7c0, 0xc998, 0xa7ff, 0xc998, 0x21, 0 + .dw 0xa840, 0xc998, 0xa87f, 0xc998, 0x21, 0 + .dw 0xa8c0, 0xc998, 0xa8ff, 0xc998, 0x21, 0 + .dw 0xa940, 0xc998, 0xa97f, 0xc998, 0x21, 0 + .dw 0xa9c0, 0xc998, 0xa9ff, 0xc998, 0x21, 0 + .dw 0xaa40, 0xc998, 0xaa7f, 0xc998, 0x21, 0 + .dw 0xaac0, 0xc998, 0xaaff, 0xc998, 0x21, 0 + .dw 0xab40, 0xc998, 0xab7f, 0xc998, 0x21, 0 + .dw 0xabc0, 0xc998, 0xabff, 0xc998, 0x21, 0 + .dw 0xac40, 0xc998, 0xac7f, 0xc998, 0x21, 0 + .dw 0xacc0, 0xc998, 0xacff, 0xc998, 0x21, 0 + .dw 0xad40, 0xc998, 0xad7f, 0xc998, 0x21, 0 + .dw 0xadc0, 0xc998, 0xadff, 0xc998, 0x21, 0 + .dw 0xae40, 0xc998, 0xae7f, 0xc998, 0x21, 0 + .dw 0xaec0, 0xc998, 0xaeff, 0xc998, 0x21, 0 + .dw 0xaf40, 0xc998, 0xaf7f, 0xc998, 0x21, 0 + .dw 0xafc0, 0xc998, 0xafff, 0xc998, 0x21, 0 + .dw 0xb040, 0xc998, 0xb07f, 0xc998, 0x21, 0 + .dw 0xb0c0, 0xc998, 0xb0ff, 0xc998, 0x21, 0 + .dw 0xb140, 0xc998, 0xb17f, 0xc998, 0x21, 0 + .dw 0xb1c0, 0xc998, 0xb1ff, 0xc998, 0x21, 0 + .dw 0xb240, 0xc998, 0xb27f, 0xc998, 0x21, 0 + .dw 0xb2c0, 0xc998, 0xb2ff, 0xc998, 0x21, 0 + .dw 0xb340, 0xc998, 0xb37f, 0xc998, 0x21, 0 + .dw 0xb3c0, 0xc998, 0xb3ff, 0xc998, 0x21, 0 + .dw 0xb440, 0xc998, 0xb47f, 0xc998, 0x21, 0 + .dw 0xb4c0, 0xc998, 0xb4ff, 0xc998, 0x21, 0 + .dw 0xb540, 0xc998, 0xb57f, 0xc998, 0x21, 0 + .dw 0xb5c0, 0xc998, 0xb5ff, 0xc998, 0x21, 0 + .dw 0xb640, 0xc998, 0xb67f, 0xc998, 0x21, 0 + .dw 0xb6c0, 0xc998, 0xb6ff, 0xc998, 0x21, 0 + .dw 0xb740, 0xc998, 0xb77f, 0xc998, 0x21, 0 + .dw 0xb7c0, 0xc998, 0xb7ff, 0xc998, 0x21, 0 + .dw 0xb840, 0xc998, 0xb87f, 0xc998, 0x21, 0 + .dw 0xb8c0, 0xc998, 0xb8ff, 0xc998, 0x21, 0 + .dw 0xb940, 0xc998, 0xb97f, 0xc998, 0x21, 0 + .dw 0xb9c0, 0xc998, 0xdfff, 0xc998, 0x21, 0 + .dw 0xe040, 0xc998, 0xe07f, 0xc998, 0x21, 0 + .dw 0xe0c0, 0xc998, 0xe0ff, 0xc998, 0x21, 0 + .dw 0xe140, 0xc998, 0xe17f, 0xc998, 0x21, 0 + .dw 0xe1c0, 0xc998, 0xe1ff, 0xc998, 0x21, 0 + .dw 0xe240, 0xc998, 0xe27f, 0xc998, 0x21, 0 + .dw 0xe2c0, 0xc998, 0xe2ff, 0xc998, 0x21, 0 + .dw 0xe340, 0xc998, 0xe37f, 0xc998, 0x21, 0 + .dw 0xe3c0, 0xc998, 0xe3ff, 0xc998, 0x21, 0 + .dw 0xe440, 0xc998, 0xe47f, 0xc998, 0x21, 0 + .dw 0xe4c0, 0xc998, 0xe4ff, 0xc998, 0x21, 0 + .dw 0xe540, 0xc998, 0xe57f, 0xc998, 0x21, 0 + .dw 0xe5c0, 0xc998, 0xe5ff, 0xc998, 0x21, 0 + .dw 0xe640, 0xc998, 0xe67f, 0xc998, 0x21, 0 + .dw 0xe6c0, 0xc998, 0xe6ff, 0xc998, 0x21, 0 + .dw 0xe740, 0xc998, 0xe77f, 0xc998, 0x21, 0 + .dw 0xe7c0, 0xc998, 0xe7ff, 0xc998, 0x21, 0 + .dw 0xe840, 0xc998, 0xe87f, 0xc998, 0x21, 0 + .dw 0xe8c0, 0xc998, 0xe8ff, 0xc998, 0x21, 0 + .dw 0xe940, 0xc998, 0xe97f, 0xc998, 0x21, 0 + .dw 0xe9c0, 0xc998, 0xe9ff, 0xc998, 0x21, 0 + .dw 0xea40, 0xc998, 0xea7f, 0xc998, 0x21, 0 + .dw 0xeac0, 0xc998, 0xeaff, 0xc998, 0x21, 0 + .dw 0xeb40, 0xc998, 0xeb7f, 0xc998, 0x21, 0 + .dw 0xebc0, 0xc998, 0xebff, 0xc998, 0x21, 0 + .dw 0xec40, 0xc998, 0xec7f, 0xc998, 0x21, 0 + .dw 0xecc0, 0xc998, 0xecff, 0xc998, 0x21, 0 + .dw 0xed40, 0xc998, 0xed7f, 0xc998, 0x21, 0 + .dw 0xedc0, 0xc998, 0xedff, 0xc998, 0x21, 0 + .dw 0xee40, 0xc998, 0xee7f, 0xc998, 0x21, 0 + .dw 0xeec0, 0xc998, 0xeeff, 0xc998, 0x21, 0 + .dw 0xef40, 0xc998, 0xef7f, 0xc998, 0x21, 0 + .dw 0xefc0, 0xc998, 0xefff, 0xc998, 0x21, 0 + .dw 0xf040, 0xc998, 0xf07f, 0xc998, 0x21, 0 + .dw 0xf0c0, 0xc998, 0xf0ff, 0xc998, 0x21, 0 + .dw 0xf140, 0xc998, 0xf17f, 0xc998, 0x21, 0 + .dw 0xf1c0, 0xc998, 0xf1ff, 0xc998, 0x21, 0 + .dw 0xf240, 0xc998, 0xf27f, 0xc998, 0x21, 0 + .dw 0xf2c0, 0xc998, 0xf2ff, 0xc998, 0x21, 0 + .dw 0xf340, 0xc998, 0xf37f, 0xc998, 0x21, 0 + .dw 0xf3c0, 0xc998, 0xf3ff, 0xc998, 0x21, 0 + .dw 0xf440, 0xc998, 0xf47f, 0xc998, 0x21, 0 + .dw 0xf4c0, 0xc998, 0xf4ff, 0xc998, 0x21, 0 + .dw 0xf540, 0xc998, 0xf57f, 0xc998, 0x21, 0 + .dw 0xf5c0, 0xc998, 0xf5ff, 0xc998, 0x21, 0 + .dw 0xf640, 0xc998, 0xf67f, 0xc998, 0x21, 0 + .dw 0xf6c0, 0xc998, 0xf6ff, 0xc998, 0x21, 0 + .dw 0xf740, 0xc998, 0xf77f, 0xc998, 0x21, 0 + .dw 0xf7c0, 0xc998, 0xf7ff, 0xc998, 0x21, 0 + .dw 0xf840, 0xc998, 0xf87f, 0xc998, 0x21, 0 + .dw 0xf8c0, 0xc998, 0xf8ff, 0xc998, 0x21, 0 + .dw 0xf940, 0xc998, 0xf97f, 0xc998, 0x21, 0 + .dw 0xf9c0, 0xc998, 0x1fff, 0xc999, 0x21, 0 + .dw 0x2040, 0xc999, 0x207f, 0xc999, 0x21, 0 + .dw 0x20c0, 0xc999, 0x20ff, 0xc999, 0x21, 0 + .dw 0x2140, 0xc999, 0x217f, 0xc999, 0x21, 0 + .dw 0x21c0, 0xc999, 0x21ff, 0xc999, 0x21, 0 + .dw 0x2240, 0xc999, 0x227f, 0xc999, 0x21, 0 + .dw 0x22c0, 0xc999, 0x22ff, 0xc999, 0x21, 0 + .dw 0x2340, 0xc999, 0x237f, 0xc999, 0x21, 0 + .dw 0x23c0, 0xc999, 0x23ff, 0xc999, 0x21, 0 + .dw 0x2440, 0xc999, 0x247f, 0xc999, 0x21, 0 + .dw 0x24c0, 0xc999, 0x24ff, 0xc999, 0x21, 0 + .dw 0x2540, 0xc999, 0x257f, 0xc999, 0x21, 0 + .dw 0x25c0, 0xc999, 0x25ff, 0xc999, 0x21, 0 + .dw 0x2640, 0xc999, 0x267f, 0xc999, 0x21, 0 + .dw 0x26c0, 0xc999, 0x26ff, 0xc999, 0x21, 0 + .dw 0x2740, 0xc999, 0x277f, 0xc999, 0x21, 0 + .dw 0x27c0, 0xc999, 0x27ff, 0xc999, 0x21, 0 + .dw 0x2840, 0xc999, 0x287f, 0xc999, 0x21, 0 + .dw 0x28c0, 0xc999, 0x28ff, 0xc999, 0x21, 0 + .dw 0x2940, 0xc999, 0x297f, 0xc999, 0x21, 0 + .dw 0x29c0, 0xc999, 0x29ff, 0xc999, 0x21, 0 + .dw 0x2a40, 0xc999, 0x2a7f, 0xc999, 0x21, 0 + .dw 0x2ac0, 0xc999, 0x2aff, 0xc999, 0x21, 0 + .dw 0x2b40, 0xc999, 0x2b7f, 0xc999, 0x21, 0 + .dw 0x2bc0, 0xc999, 0x2bff, 0xc999, 0x21, 0 + .dw 0x2c40, 0xc999, 0x2c7f, 0xc999, 0x21, 0 + .dw 0x2cc0, 0xc999, 0x2cff, 0xc999, 0x21, 0 + .dw 0x2d40, 0xc999, 0x2d7f, 0xc999, 0x21, 0 + .dw 0x2dc0, 0xc999, 0x2dff, 0xc999, 0x21, 0 + .dw 0x2e40, 0xc999, 0x2e7f, 0xc999, 0x21, 0 + .dw 0x2ec0, 0xc999, 0x2eff, 0xc999, 0x21, 0 + .dw 0x2f40, 0xc999, 0x2f7f, 0xc999, 0x21, 0 + .dw 0x2fc0, 0xc999, 0x2fff, 0xc999, 0x21, 0 + .dw 0x3040, 0xc999, 0x307f, 0xc999, 0x21, 0 + .dw 0x30c0, 0xc999, 0x30ff, 0xc999, 0x21, 0 + .dw 0x3140, 0xc999, 0x317f, 0xc999, 0x21, 0 + .dw 0x31c0, 0xc999, 0x31ff, 0xc999, 0x21, 0 + .dw 0x3240, 0xc999, 0x327f, 0xc999, 0x21, 0 + .dw 0x32c0, 0xc999, 0x32ff, 0xc999, 0x21, 0 + .dw 0x3340, 0xc999, 0x337f, 0xc999, 0x21, 0 + .dw 0x33c0, 0xc999, 0x33ff, 0xc999, 0x21, 0 + .dw 0x3440, 0xc999, 0x347f, 0xc999, 0x21, 0 + .dw 0x34c0, 0xc999, 0x34ff, 0xc999, 0x21, 0 + .dw 0x3540, 0xc999, 0x357f, 0xc999, 0x21, 0 + .dw 0x35c0, 0xc999, 0x35ff, 0xc999, 0x21, 0 + .dw 0x3640, 0xc999, 0x367f, 0xc999, 0x21, 0 + .dw 0x36c0, 0xc999, 0x36ff, 0xc999, 0x21, 0 + .dw 0x3740, 0xc999, 0x377f, 0xc999, 0x21, 0 + .dw 0x37c0, 0xc999, 0x37ff, 0xc999, 0x21, 0 + .dw 0x3840, 0xc999, 0x387f, 0xc999, 0x21, 0 + .dw 0x38c0, 0xc999, 0x38ff, 0xc999, 0x21, 0 + .dw 0x3940, 0xc999, 0x397f, 0xc999, 0x21, 0 + .dw 0x39c0, 0xc999, 0x5fff, 0xc999, 0x21, 0 + .dw 0x6040, 0xc999, 0x607f, 0xc999, 0x21, 0 + .dw 0x60c0, 0xc999, 0x60ff, 0xc999, 0x21, 0 + .dw 0x6140, 0xc999, 0x617f, 0xc999, 0x21, 0 + .dw 0x61c0, 0xc999, 0x61ff, 0xc999, 0x21, 0 + .dw 0x6240, 0xc999, 0x627f, 0xc999, 0x21, 0 + .dw 0x62c0, 0xc999, 0x62ff, 0xc999, 0x21, 0 + .dw 0x6340, 0xc999, 0x637f, 0xc999, 0x21, 0 + .dw 0x63c0, 0xc999, 0x63ff, 0xc999, 0x21, 0 + .dw 0x6440, 0xc999, 0x647f, 0xc999, 0x21, 0 + .dw 0x64c0, 0xc999, 0x64ff, 0xc999, 0x21, 0 + .dw 0x6540, 0xc999, 0x657f, 0xc999, 0x21, 0 + .dw 0x65c0, 0xc999, 0x65ff, 0xc999, 0x21, 0 + .dw 0x6640, 0xc999, 0x667f, 0xc999, 0x21, 0 + .dw 0x66c0, 0xc999, 0x66ff, 0xc999, 0x21, 0 + .dw 0x6740, 0xc999, 0x677f, 0xc999, 0x21, 0 + .dw 0x67c0, 0xc999, 0x67ff, 0xc999, 0x21, 0 + .dw 0x6840, 0xc999, 0x687f, 0xc999, 0x21, 0 + .dw 0x68c0, 0xc999, 0x68ff, 0xc999, 0x21, 0 + .dw 0x6940, 0xc999, 0x697f, 0xc999, 0x21, 0 + .dw 0x69c0, 0xc999, 0x69ff, 0xc999, 0x21, 0 + .dw 0x6a40, 0xc999, 0x6a7f, 0xc999, 0x21, 0 + .dw 0x6ac0, 0xc999, 0x6aff, 0xc999, 0x21, 0 + .dw 0x6b40, 0xc999, 0x6b7f, 0xc999, 0x21, 0 + .dw 0x6bc0, 0xc999, 0x6bff, 0xc999, 0x21, 0 + .dw 0x6c40, 0xc999, 0x6c7f, 0xc999, 0x21, 0 + .dw 0x6cc0, 0xc999, 0x6cff, 0xc999, 0x21, 0 + .dw 0x6d40, 0xc999, 0x6d7f, 0xc999, 0x21, 0 + .dw 0x6dc0, 0xc999, 0x6dff, 0xc999, 0x21, 0 + .dw 0x6e40, 0xc999, 0x6e7f, 0xc999, 0x21, 0 + .dw 0x6ec0, 0xc999, 0x6eff, 0xc999, 0x21, 0 + .dw 0x6f40, 0xc999, 0x6f7f, 0xc999, 0x21, 0 + .dw 0x6fc0, 0xc999, 0x6fff, 0xc999, 0x21, 0 + .dw 0x7040, 0xc999, 0x707f, 0xc999, 0x21, 0 + .dw 0x70c0, 0xc999, 0x70ff, 0xc999, 0x21, 0 + .dw 0x7140, 0xc999, 0x717f, 0xc999, 0x21, 0 + .dw 0x71c0, 0xc999, 0x71ff, 0xc999, 0x21, 0 + .dw 0x7240, 0xc999, 0x727f, 0xc999, 0x21, 0 + .dw 0x72c0, 0xc999, 0x72ff, 0xc999, 0x21, 0 + .dw 0x7340, 0xc999, 0x737f, 0xc999, 0x21, 0 + .dw 0x73c0, 0xc999, 0x73ff, 0xc999, 0x21, 0 + .dw 0x7440, 0xc999, 0x747f, 0xc999, 0x21, 0 + .dw 0x74c0, 0xc999, 0x74ff, 0xc999, 0x21, 0 + .dw 0x7540, 0xc999, 0x757f, 0xc999, 0x21, 0 + .dw 0x75c0, 0xc999, 0x75ff, 0xc999, 0x21, 0 + .dw 0x7640, 0xc999, 0x767f, 0xc999, 0x21, 0 + .dw 0x76c0, 0xc999, 0x76ff, 0xc999, 0x21, 0 + .dw 0x7740, 0xc999, 0x777f, 0xc999, 0x21, 0 + .dw 0x77c0, 0xc999, 0x77ff, 0xc999, 0x21, 0 + .dw 0x7840, 0xc999, 0x787f, 0xc999, 0x21, 0 + .dw 0x78c0, 0xc999, 0x78ff, 0xc999, 0x21, 0 + .dw 0x7940, 0xc999, 0x797f, 0xc999, 0x21, 0 + .dw 0x79c0, 0xc999, 0x9fff, 0xc999, 0x21, 0 + .dw 0xa040, 0xc999, 0xa07f, 0xc999, 0x21, 0 + .dw 0xa0c0, 0xc999, 0xa0ff, 0xc999, 0x21, 0 + .dw 0xa140, 0xc999, 0xa17f, 0xc999, 0x21, 0 + .dw 0xa1c0, 0xc999, 0xa1ff, 0xc999, 0x21, 0 + .dw 0xa240, 0xc999, 0xa27f, 0xc999, 0x21, 0 + .dw 0xa2c0, 0xc999, 0xa2ff, 0xc999, 0x21, 0 + .dw 0xa340, 0xc999, 0xa37f, 0xc999, 0x21, 0 + .dw 0xa3c0, 0xc999, 0xa3ff, 0xc999, 0x21, 0 + .dw 0xa440, 0xc999, 0xa47f, 0xc999, 0x21, 0 + .dw 0xa4c0, 0xc999, 0xa4ff, 0xc999, 0x21, 0 + .dw 0xa540, 0xc999, 0xa57f, 0xc999, 0x21, 0 + .dw 0xa5c0, 0xc999, 0xa5ff, 0xc999, 0x21, 0 + .dw 0xa640, 0xc999, 0xa67f, 0xc999, 0x21, 0 + .dw 0xa6c0, 0xc999, 0xa6ff, 0xc999, 0x21, 0 + .dw 0xa740, 0xc999, 0xa77f, 0xc999, 0x21, 0 + .dw 0xa7c0, 0xc999, 0xa7ff, 0xc999, 0x21, 0 + .dw 0xa840, 0xc999, 0xa87f, 0xc999, 0x21, 0 + .dw 0xa8c0, 0xc999, 0xa8ff, 0xc999, 0x21, 0 + .dw 0xa940, 0xc999, 0xa97f, 0xc999, 0x21, 0 + .dw 0xa9c0, 0xc999, 0xa9ff, 0xc999, 0x21, 0 + .dw 0xaa40, 0xc999, 0xaa7f, 0xc999, 0x21, 0 + .dw 0xaac0, 0xc999, 0xaaff, 0xc999, 0x21, 0 + .dw 0xab40, 0xc999, 0xab7f, 0xc999, 0x21, 0 + .dw 0xabc0, 0xc999, 0xabff, 0xc999, 0x21, 0 + .dw 0xac40, 0xc999, 0xac7f, 0xc999, 0x21, 0 + .dw 0xacc0, 0xc999, 0xacff, 0xc999, 0x21, 0 + .dw 0xad40, 0xc999, 0xad7f, 0xc999, 0x21, 0 + .dw 0xadc0, 0xc999, 0xadff, 0xc999, 0x21, 0 + .dw 0xae40, 0xc999, 0xae7f, 0xc999, 0x21, 0 + .dw 0xaec0, 0xc999, 0xaeff, 0xc999, 0x21, 0 + .dw 0xaf40, 0xc999, 0xaf7f, 0xc999, 0x21, 0 + .dw 0xafc0, 0xc999, 0xafff, 0xc999, 0x21, 0 + .dw 0xb040, 0xc999, 0xb07f, 0xc999, 0x21, 0 + .dw 0xb0c0, 0xc999, 0xb0ff, 0xc999, 0x21, 0 + .dw 0xb140, 0xc999, 0xb17f, 0xc999, 0x21, 0 + .dw 0xb1c0, 0xc999, 0xb1ff, 0xc999, 0x21, 0 + .dw 0xb240, 0xc999, 0xb27f, 0xc999, 0x21, 0 + .dw 0xb2c0, 0xc999, 0xb2ff, 0xc999, 0x21, 0 + .dw 0xb340, 0xc999, 0xb37f, 0xc999, 0x21, 0 + .dw 0xb3c0, 0xc999, 0xb3ff, 0xc999, 0x21, 0 + .dw 0xb440, 0xc999, 0xb47f, 0xc999, 0x21, 0 + .dw 0xb4c0, 0xc999, 0xb4ff, 0xc999, 0x21, 0 + .dw 0xb540, 0xc999, 0xb57f, 0xc999, 0x21, 0 + .dw 0xb5c0, 0xc999, 0xb5ff, 0xc999, 0x21, 0 + .dw 0xb640, 0xc999, 0xb67f, 0xc999, 0x21, 0 + .dw 0xb6c0, 0xc999, 0xb6ff, 0xc999, 0x21, 0 + .dw 0xb740, 0xc999, 0xb77f, 0xc999, 0x21, 0 + .dw 0xb7c0, 0xc999, 0xb7ff, 0xc999, 0x21, 0 + .dw 0xb840, 0xc999, 0xb87f, 0xc999, 0x21, 0 + .dw 0xb8c0, 0xc999, 0xb8ff, 0xc999, 0x21, 0 + .dw 0xb940, 0xc999, 0xb97f, 0xc999, 0x21, 0 + .dw 0xb9c0, 0xc999, 0xdfff, 0xc999, 0x21, 0 + .dw 0xe040, 0xc999, 0xe07f, 0xc999, 0x21, 0 + .dw 0xe0c0, 0xc999, 0xe0ff, 0xc999, 0x21, 0 + .dw 0xe140, 0xc999, 0xe17f, 0xc999, 0x21, 0 + .dw 0xe1c0, 0xc999, 0xe1ff, 0xc999, 0x21, 0 + .dw 0xe240, 0xc999, 0xe27f, 0xc999, 0x21, 0 + .dw 0xe2c0, 0xc999, 0xe2ff, 0xc999, 0x21, 0 + .dw 0xe340, 0xc999, 0xe37f, 0xc999, 0x21, 0 + .dw 0xe3c0, 0xc999, 0xe3ff, 0xc999, 0x21, 0 + .dw 0xe440, 0xc999, 0xe47f, 0xc999, 0x21, 0 + .dw 0xe4c0, 0xc999, 0xe4ff, 0xc999, 0x21, 0 + .dw 0xe540, 0xc999, 0xe57f, 0xc999, 0x21, 0 + .dw 0xe5c0, 0xc999, 0xe5ff, 0xc999, 0x21, 0 + .dw 0xe640, 0xc999, 0xe67f, 0xc999, 0x21, 0 + .dw 0xe6c0, 0xc999, 0xe6ff, 0xc999, 0x21, 0 + .dw 0xe740, 0xc999, 0xe77f, 0xc999, 0x21, 0 + .dw 0xe7c0, 0xc999, 0xe7ff, 0xc999, 0x21, 0 + .dw 0xe840, 0xc999, 0xe87f, 0xc999, 0x21, 0 + .dw 0xe8c0, 0xc999, 0xe8ff, 0xc999, 0x21, 0 + .dw 0xe940, 0xc999, 0xe97f, 0xc999, 0x21, 0 + .dw 0xe9c0, 0xc999, 0xe9ff, 0xc999, 0x21, 0 + .dw 0xea40, 0xc999, 0xea7f, 0xc999, 0x21, 0 + .dw 0xeac0, 0xc999, 0xeaff, 0xc999, 0x21, 0 + .dw 0xeb40, 0xc999, 0xeb7f, 0xc999, 0x21, 0 + .dw 0xebc0, 0xc999, 0xebff, 0xc999, 0x21, 0 + .dw 0xec40, 0xc999, 0xec7f, 0xc999, 0x21, 0 + .dw 0xecc0, 0xc999, 0xecff, 0xc999, 0x21, 0 + .dw 0xed40, 0xc999, 0xed7f, 0xc999, 0x21, 0 + .dw 0xedc0, 0xc999, 0xedff, 0xc999, 0x21, 0 + .dw 0xee40, 0xc999, 0xee7f, 0xc999, 0x21, 0 + .dw 0xeec0, 0xc999, 0xeeff, 0xc999, 0x21, 0 + .dw 0xef40, 0xc999, 0xef7f, 0xc999, 0x21, 0 + .dw 0xefc0, 0xc999, 0xefff, 0xc999, 0x21, 0 + .dw 0xf040, 0xc999, 0xf07f, 0xc999, 0x21, 0 + .dw 0xf0c0, 0xc999, 0xf0ff, 0xc999, 0x21, 0 + .dw 0xf140, 0xc999, 0xf17f, 0xc999, 0x21, 0 + .dw 0xf1c0, 0xc999, 0xf1ff, 0xc999, 0x21, 0 + .dw 0xf240, 0xc999, 0xf27f, 0xc999, 0x21, 0 + .dw 0xf2c0, 0xc999, 0xf2ff, 0xc999, 0x21, 0 + .dw 0xf340, 0xc999, 0xf37f, 0xc999, 0x21, 0 + .dw 0xf3c0, 0xc999, 0xf3ff, 0xc999, 0x21, 0 + .dw 0xf440, 0xc999, 0xf47f, 0xc999, 0x21, 0 + .dw 0xf4c0, 0xc999, 0xf4ff, 0xc999, 0x21, 0 + .dw 0xf540, 0xc999, 0xf57f, 0xc999, 0x21, 0 + .dw 0xf5c0, 0xc999, 0xf5ff, 0xc999, 0x21, 0 + .dw 0xf640, 0xc999, 0xf67f, 0xc999, 0x21, 0 + .dw 0xf6c0, 0xc999, 0xf6ff, 0xc999, 0x21, 0 + .dw 0xf740, 0xc999, 0xf77f, 0xc999, 0x21, 0 + .dw 0xf7c0, 0xc999, 0xf7ff, 0xc999, 0x21, 0 + .dw 0xf840, 0xc999, 0xf87f, 0xc999, 0x21, 0 + .dw 0xf8c0, 0xc999, 0xf8ff, 0xc999, 0x21, 0 + .dw 0xf940, 0xc999, 0xf97f, 0xc999, 0x21, 0 + .dw 0xf9c0, 0xc999, 0x1fff, 0xc99a, 0x21, 0 + .dw 0x2040, 0xc99a, 0x207f, 0xc99a, 0x21, 0 + .dw 0x20c0, 0xc99a, 0x20ff, 0xc99a, 0x21, 0 + .dw 0x2140, 0xc99a, 0x217f, 0xc99a, 0x21, 0 + .dw 0x21c0, 0xc99a, 0x21ff, 0xc99a, 0x21, 0 + .dw 0x2240, 0xc99a, 0x227f, 0xc99a, 0x21, 0 + .dw 0x22c0, 0xc99a, 0x22ff, 0xc99a, 0x21, 0 + .dw 0x2340, 0xc99a, 0x237f, 0xc99a, 0x21, 0 + .dw 0x23c0, 0xc99a, 0x23ff, 0xc99a, 0x21, 0 + .dw 0x2440, 0xc99a, 0x247f, 0xc99a, 0x21, 0 + .dw 0x24c0, 0xc99a, 0x24ff, 0xc99a, 0x21, 0 + .dw 0x2540, 0xc99a, 0x257f, 0xc99a, 0x21, 0 + .dw 0x25c0, 0xc99a, 0x25ff, 0xc99a, 0x21, 0 + .dw 0x2640, 0xc99a, 0x267f, 0xc99a, 0x21, 0 + .dw 0x26c0, 0xc99a, 0x26ff, 0xc99a, 0x21, 0 + .dw 0x2740, 0xc99a, 0x277f, 0xc99a, 0x21, 0 + .dw 0x27c0, 0xc99a, 0x27ff, 0xc99a, 0x21, 0 + .dw 0x2840, 0xc99a, 0x287f, 0xc99a, 0x21, 0 + .dw 0x28c0, 0xc99a, 0x28ff, 0xc99a, 0x21, 0 + .dw 0x2940, 0xc99a, 0x297f, 0xc99a, 0x21, 0 + .dw 0x29c0, 0xc99a, 0x29ff, 0xc99a, 0x21, 0 + .dw 0x2a40, 0xc99a, 0x2a7f, 0xc99a, 0x21, 0 + .dw 0x2ac0, 0xc99a, 0x2aff, 0xc99a, 0x21, 0 + .dw 0x2b40, 0xc99a, 0x2b7f, 0xc99a, 0x21, 0 + .dw 0x2bc0, 0xc99a, 0x2bff, 0xc99a, 0x21, 0 + .dw 0x2c40, 0xc99a, 0x2c7f, 0xc99a, 0x21, 0 + .dw 0x2cc0, 0xc99a, 0x2cff, 0xc99a, 0x21, 0 + .dw 0x2d40, 0xc99a, 0x2d7f, 0xc99a, 0x21, 0 + .dw 0x2dc0, 0xc99a, 0x2dff, 0xc99a, 0x21, 0 + .dw 0x2e40, 0xc99a, 0x2e7f, 0xc99a, 0x21, 0 + .dw 0x2ec0, 0xc99a, 0x2eff, 0xc99a, 0x21, 0 + .dw 0x2f40, 0xc99a, 0x2f7f, 0xc99a, 0x21, 0 + .dw 0x2fc0, 0xc99a, 0x2fff, 0xc99a, 0x21, 0 + .dw 0x3040, 0xc99a, 0x307f, 0xc99a, 0x21, 0 + .dw 0x30c0, 0xc99a, 0x30ff, 0xc99a, 0x21, 0 + .dw 0x3140, 0xc99a, 0x317f, 0xc99a, 0x21, 0 + .dw 0x31c0, 0xc99a, 0x31ff, 0xc99a, 0x21, 0 + .dw 0x3240, 0xc99a, 0x327f, 0xc99a, 0x21, 0 + .dw 0x32c0, 0xc99a, 0x32ff, 0xc99a, 0x21, 0 + .dw 0x3340, 0xc99a, 0x337f, 0xc99a, 0x21, 0 + .dw 0x33c0, 0xc99a, 0x33ff, 0xc99a, 0x21, 0 + .dw 0x3440, 0xc99a, 0x347f, 0xc99a, 0x21, 0 + .dw 0x34c0, 0xc99a, 0x34ff, 0xc99a, 0x21, 0 + .dw 0x3540, 0xc99a, 0x357f, 0xc99a, 0x21, 0 + .dw 0x35c0, 0xc99a, 0x35ff, 0xc99a, 0x21, 0 + .dw 0x3640, 0xc99a, 0x367f, 0xc99a, 0x21, 0 + .dw 0x36c0, 0xc99a, 0x36ff, 0xc99a, 0x21, 0 + .dw 0x3740, 0xc99a, 0x377f, 0xc99a, 0x21, 0 + .dw 0x37c0, 0xc99a, 0x37ff, 0xc99a, 0x21, 0 + .dw 0x3840, 0xc99a, 0x387f, 0xc99a, 0x21, 0 + .dw 0x38c0, 0xc99a, 0x38ff, 0xc99a, 0x21, 0 + .dw 0x3940, 0xc99a, 0x397f, 0xc99a, 0x21, 0 + .dw 0x39c0, 0xc99a, 0x5fff, 0xc99a, 0x21, 0 + .dw 0x6040, 0xc99a, 0x607f, 0xc99a, 0x21, 0 + .dw 0x60c0, 0xc99a, 0x60ff, 0xc99a, 0x21, 0 + .dw 0x6140, 0xc99a, 0x617f, 0xc99a, 0x21, 0 + .dw 0x61c0, 0xc99a, 0x61ff, 0xc99a, 0x21, 0 + .dw 0x6240, 0xc99a, 0x627f, 0xc99a, 0x21, 0 + .dw 0x62c0, 0xc99a, 0x62ff, 0xc99a, 0x21, 0 + .dw 0x6340, 0xc99a, 0x637f, 0xc99a, 0x21, 0 + .dw 0x63c0, 0xc99a, 0x63ff, 0xc99a, 0x21, 0 + .dw 0x6440, 0xc99a, 0x647f, 0xc99a, 0x21, 0 + .dw 0x64c0, 0xc99a, 0x64ff, 0xc99a, 0x21, 0 + .dw 0x6540, 0xc99a, 0x657f, 0xc99a, 0x21, 0 + .dw 0x65c0, 0xc99a, 0x65ff, 0xc99a, 0x21, 0 + .dw 0x6640, 0xc99a, 0x667f, 0xc99a, 0x21, 0 + .dw 0x66c0, 0xc99a, 0x66ff, 0xc99a, 0x21, 0 + .dw 0x6740, 0xc99a, 0x677f, 0xc99a, 0x21, 0 + .dw 0x67c0, 0xc99a, 0x67ff, 0xc99a, 0x21, 0 + .dw 0x6840, 0xc99a, 0x687f, 0xc99a, 0x21, 0 + .dw 0x68c0, 0xc99a, 0x68ff, 0xc99a, 0x21, 0 + .dw 0x6940, 0xc99a, 0x697f, 0xc99a, 0x21, 0 + .dw 0x69c0, 0xc99a, 0x69ff, 0xc99a, 0x21, 0 + .dw 0x6a40, 0xc99a, 0x6a7f, 0xc99a, 0x21, 0 + .dw 0x6ac0, 0xc99a, 0x6aff, 0xc99a, 0x21, 0 + .dw 0x6b40, 0xc99a, 0x6b7f, 0xc99a, 0x21, 0 + .dw 0x6bc0, 0xc99a, 0x6bff, 0xc99a, 0x21, 0 + .dw 0x6c40, 0xc99a, 0x6c7f, 0xc99a, 0x21, 0 + .dw 0x6cc0, 0xc99a, 0x6cff, 0xc99a, 0x21, 0 + .dw 0x6d40, 0xc99a, 0x6d7f, 0xc99a, 0x21, 0 + .dw 0x6dc0, 0xc99a, 0x6dff, 0xc99a, 0x21, 0 + .dw 0x6e40, 0xc99a, 0x6e7f, 0xc99a, 0x21, 0 + .dw 0x6ec0, 0xc99a, 0x6eff, 0xc99a, 0x21, 0 + .dw 0x6f40, 0xc99a, 0x6f7f, 0xc99a, 0x21, 0 + .dw 0x6fc0, 0xc99a, 0x6fff, 0xc99a, 0x21, 0 + .dw 0x7040, 0xc99a, 0x707f, 0xc99a, 0x21, 0 + .dw 0x70c0, 0xc99a, 0x70ff, 0xc99a, 0x21, 0 + .dw 0x7140, 0xc99a, 0x717f, 0xc99a, 0x21, 0 + .dw 0x71c0, 0xc99a, 0x71ff, 0xc99a, 0x21, 0 + .dw 0x7240, 0xc99a, 0x727f, 0xc99a, 0x21, 0 + .dw 0x72c0, 0xc99a, 0x72ff, 0xc99a, 0x21, 0 + .dw 0x7340, 0xc99a, 0x737f, 0xc99a, 0x21, 0 + .dw 0x73c0, 0xc99a, 0x73ff, 0xc99a, 0x21, 0 + .dw 0x7440, 0xc99a, 0x747f, 0xc99a, 0x21, 0 + .dw 0x74c0, 0xc99a, 0x74ff, 0xc99a, 0x21, 0 + .dw 0x7540, 0xc99a, 0x757f, 0xc99a, 0x21, 0 + .dw 0x75c0, 0xc99a, 0x75ff, 0xc99a, 0x21, 0 + .dw 0x7640, 0xc99a, 0x767f, 0xc99a, 0x21, 0 + .dw 0x76c0, 0xc99a, 0x76ff, 0xc99a, 0x21, 0 + .dw 0x7740, 0xc99a, 0x777f, 0xc99a, 0x21, 0 + .dw 0x77c0, 0xc99a, 0x77ff, 0xc99a, 0x21, 0 + .dw 0x7840, 0xc99a, 0x787f, 0xc99a, 0x21, 0 + .dw 0x78c0, 0xc99a, 0x78ff, 0xc99a, 0x21, 0 + .dw 0x7940, 0xc99a, 0x797f, 0xc99a, 0x21, 0 + .dw 0x79c0, 0xc99a, 0x9fff, 0xc99a, 0x21, 0 + .dw 0xa040, 0xc99a, 0xa07f, 0xc99a, 0x21, 0 + .dw 0xa0c0, 0xc99a, 0xa0ff, 0xc99a, 0x21, 0 + .dw 0xa140, 0xc99a, 0xa17f, 0xc99a, 0x21, 0 + .dw 0xa1c0, 0xc99a, 0xa1ff, 0xc99a, 0x21, 0 + .dw 0xa240, 0xc99a, 0xa27f, 0xc99a, 0x21, 0 + .dw 0xa2c0, 0xc99a, 0xa2ff, 0xc99a, 0x21, 0 + .dw 0xa340, 0xc99a, 0xa37f, 0xc99a, 0x21, 0 + .dw 0xa3c0, 0xc99a, 0xa3ff, 0xc99a, 0x21, 0 + .dw 0xa440, 0xc99a, 0xa47f, 0xc99a, 0x21, 0 + .dw 0xa4c0, 0xc99a, 0xa4ff, 0xc99a, 0x21, 0 + .dw 0xa540, 0xc99a, 0xa57f, 0xc99a, 0x21, 0 + .dw 0xa5c0, 0xc99a, 0xa5ff, 0xc99a, 0x21, 0 + .dw 0xa640, 0xc99a, 0xa67f, 0xc99a, 0x21, 0 + .dw 0xa6c0, 0xc99a, 0xa6ff, 0xc99a, 0x21, 0 + .dw 0xa740, 0xc99a, 0xa77f, 0xc99a, 0x21, 0 + .dw 0xa7c0, 0xc99a, 0xa7ff, 0xc99a, 0x21, 0 + .dw 0xa840, 0xc99a, 0xa87f, 0xc99a, 0x21, 0 + .dw 0xa8c0, 0xc99a, 0xa8ff, 0xc99a, 0x21, 0 + .dw 0xa940, 0xc99a, 0xa97f, 0xc99a, 0x21, 0 + .dw 0xa9c0, 0xc99a, 0xa9ff, 0xc99a, 0x21, 0 + .dw 0xaa40, 0xc99a, 0xaa7f, 0xc99a, 0x21, 0 + .dw 0xaac0, 0xc99a, 0xaaff, 0xc99a, 0x21, 0 + .dw 0xab40, 0xc99a, 0xab7f, 0xc99a, 0x21, 0 + .dw 0xabc0, 0xc99a, 0xabff, 0xc99a, 0x21, 0 + .dw 0xac40, 0xc99a, 0xac7f, 0xc99a, 0x21, 0 + .dw 0xacc0, 0xc99a, 0xacff, 0xc99a, 0x21, 0 + .dw 0xad40, 0xc99a, 0xad7f, 0xc99a, 0x21, 0 + .dw 0xadc0, 0xc99a, 0xadff, 0xc99a, 0x21, 0 + .dw 0xae40, 0xc99a, 0xae7f, 0xc99a, 0x21, 0 + .dw 0xaec0, 0xc99a, 0xaeff, 0xc99a, 0x21, 0 + .dw 0xaf40, 0xc99a, 0xaf7f, 0xc99a, 0x21, 0 + .dw 0xafc0, 0xc99a, 0xafff, 0xc99a, 0x21, 0 + .dw 0xb040, 0xc99a, 0xb07f, 0xc99a, 0x21, 0 + .dw 0xb0c0, 0xc99a, 0xb0ff, 0xc99a, 0x21, 0 + .dw 0xb140, 0xc99a, 0xb17f, 0xc99a, 0x21, 0 + .dw 0xb1c0, 0xc99a, 0xb1ff, 0xc99a, 0x21, 0 + .dw 0xb240, 0xc99a, 0xb27f, 0xc99a, 0x21, 0 + .dw 0xb2c0, 0xc99a, 0xb2ff, 0xc99a, 0x21, 0 + .dw 0xb340, 0xc99a, 0xb37f, 0xc99a, 0x21, 0 + .dw 0xb3c0, 0xc99a, 0xb3ff, 0xc99a, 0x21, 0 + .dw 0xb440, 0xc99a, 0xb47f, 0xc99a, 0x21, 0 + .dw 0xb4c0, 0xc99a, 0xb4ff, 0xc99a, 0x21, 0 + .dw 0xb540, 0xc99a, 0xb57f, 0xc99a, 0x21, 0 + .dw 0xb5c0, 0xc99a, 0xb5ff, 0xc99a, 0x21, 0 + .dw 0xb640, 0xc99a, 0xb67f, 0xc99a, 0x21, 0 + .dw 0xb6c0, 0xc99a, 0xb6ff, 0xc99a, 0x21, 0 + .dw 0xb740, 0xc99a, 0xb77f, 0xc99a, 0x21, 0 + .dw 0xb7c0, 0xc99a, 0xb7ff, 0xc99a, 0x21, 0 + .dw 0xb840, 0xc99a, 0xb87f, 0xc99a, 0x21, 0 + .dw 0xb8c0, 0xc99a, 0xb8ff, 0xc99a, 0x21, 0 + .dw 0xb940, 0xc99a, 0xb97f, 0xc99a, 0x21, 0 + .dw 0xb9c0, 0xc99a, 0xdfff, 0xc99a, 0x21, 0 + .dw 0xe040, 0xc99a, 0xe07f, 0xc99a, 0x21, 0 + .dw 0xe0c0, 0xc99a, 0xe0ff, 0xc99a, 0x21, 0 + .dw 0xe140, 0xc99a, 0xe17f, 0xc99a, 0x21, 0 + .dw 0xe1c0, 0xc99a, 0xe1ff, 0xc99a, 0x21, 0 + .dw 0xe240, 0xc99a, 0xe27f, 0xc99a, 0x21, 0 + .dw 0xe2c0, 0xc99a, 0xe2ff, 0xc99a, 0x21, 0 + .dw 0xe340, 0xc99a, 0xe37f, 0xc99a, 0x21, 0 + .dw 0xe3c0, 0xc99a, 0xe3ff, 0xc99a, 0x21, 0 + .dw 0xe440, 0xc99a, 0xe47f, 0xc99a, 0x21, 0 + .dw 0xe4c0, 0xc99a, 0xe4ff, 0xc99a, 0x21, 0 + .dw 0xe540, 0xc99a, 0xe57f, 0xc99a, 0x21, 0 + .dw 0xe5c0, 0xc99a, 0xe5ff, 0xc99a, 0x21, 0 + .dw 0xe640, 0xc99a, 0xe67f, 0xc99a, 0x21, 0 + .dw 0xe6c0, 0xc99a, 0xe6ff, 0xc99a, 0x21, 0 + .dw 0xe740, 0xc99a, 0xe77f, 0xc99a, 0x21, 0 + .dw 0xe7c0, 0xc99a, 0xe7ff, 0xc99a, 0x21, 0 + .dw 0xe840, 0xc99a, 0xe87f, 0xc99a, 0x21, 0 + .dw 0xe8c0, 0xc99a, 0xe8ff, 0xc99a, 0x21, 0 + .dw 0xe940, 0xc99a, 0xe97f, 0xc99a, 0x21, 0 + .dw 0xe9c0, 0xc99a, 0xe9ff, 0xc99a, 0x21, 0 + .dw 0xea40, 0xc99a, 0xea7f, 0xc99a, 0x21, 0 + .dw 0xeac0, 0xc99a, 0xeaff, 0xc99a, 0x21, 0 + .dw 0xeb40, 0xc99a, 0xeb7f, 0xc99a, 0x21, 0 + .dw 0xebc0, 0xc99a, 0xebff, 0xc99a, 0x21, 0 + .dw 0xec40, 0xc99a, 0xec7f, 0xc99a, 0x21, 0 + .dw 0xecc0, 0xc99a, 0xecff, 0xc99a, 0x21, 0 + .dw 0xed40, 0xc99a, 0xed7f, 0xc99a, 0x21, 0 + .dw 0xedc0, 0xc99a, 0xedff, 0xc99a, 0x21, 0 + .dw 0xee40, 0xc99a, 0xee7f, 0xc99a, 0x21, 0 + .dw 0xeec0, 0xc99a, 0xeeff, 0xc99a, 0x21, 0 + .dw 0xef40, 0xc99a, 0xef7f, 0xc99a, 0x21, 0 + .dw 0xefc0, 0xc99a, 0xefff, 0xc99a, 0x21, 0 + .dw 0xf040, 0xc99a, 0xf07f, 0xc99a, 0x21, 0 + .dw 0xf0c0, 0xc99a, 0xf0ff, 0xc99a, 0x21, 0 + .dw 0xf140, 0xc99a, 0xf17f, 0xc99a, 0x21, 0 + .dw 0xf1c0, 0xc99a, 0xf1ff, 0xc99a, 0x21, 0 + .dw 0xf240, 0xc99a, 0xf27f, 0xc99a, 0x21, 0 + .dw 0xf2c0, 0xc99a, 0xf2ff, 0xc99a, 0x21, 0 + .dw 0xf340, 0xc99a, 0xf37f, 0xc99a, 0x21, 0 + .dw 0xf3c0, 0xc99a, 0xf3ff, 0xc99a, 0x21, 0 + .dw 0xf440, 0xc99a, 0xf47f, 0xc99a, 0x21, 0 + .dw 0xf4c0, 0xc99a, 0xf4ff, 0xc99a, 0x21, 0 + .dw 0xf540, 0xc99a, 0xf57f, 0xc99a, 0x21, 0 + .dw 0xf5c0, 0xc99a, 0xf5ff, 0xc99a, 0x21, 0 + .dw 0xf640, 0xc99a, 0xf67f, 0xc99a, 0x21, 0 + .dw 0xf6c0, 0xc99a, 0xf6ff, 0xc99a, 0x21, 0 + .dw 0xf740, 0xc99a, 0xf77f, 0xc99a, 0x21, 0 + .dw 0xf7c0, 0xc99a, 0xf7ff, 0xc99a, 0x21, 0 + .dw 0xf840, 0xc99a, 0xf87f, 0xc99a, 0x21, 0 + .dw 0xf8c0, 0xc99a, 0xf8ff, 0xc99a, 0x21, 0 + .dw 0xf940, 0xc99a, 0xf97f, 0xc99a, 0x21, 0 + .dw 0xf9c0, 0xc99a, 0xffff, 0xc99b, 0x21, 0 + .dw 0x0040, 0xc99c, 0x007f, 0xc99c, 0x21, 0 + .dw 0x00c0, 0xc99c, 0x00ff, 0xc99c, 0x21, 0 + .dw 0x0140, 0xc99c, 0x017f, 0xc99c, 0x21, 0 + .dw 0x01c0, 0xc99c, 0x01ff, 0xc99c, 0x21, 0 + .dw 0x0240, 0xc99c, 0x027f, 0xc99c, 0x21, 0 + .dw 0x02c0, 0xc99c, 0x02ff, 0xc99c, 0x21, 0 + .dw 0x0340, 0xc99c, 0x037f, 0xc99c, 0x21, 0 + .dw 0x03c0, 0xc99c, 0x03ff, 0xc99c, 0x21, 0 + .dw 0x0440, 0xc99c, 0x047f, 0xc99c, 0x21, 0 + .dw 0x04c0, 0xc99c, 0x04ff, 0xc99c, 0x21, 0 + .dw 0x0540, 0xc99c, 0x057f, 0xc99c, 0x21, 0 + .dw 0x05c0, 0xc99c, 0x05ff, 0xc99c, 0x21, 0 + .dw 0x0640, 0xc99c, 0x067f, 0xc99c, 0x21, 0 + .dw 0x06c0, 0xc99c, 0x06ff, 0xc99c, 0x21, 0 + .dw 0x0740, 0xc99c, 0x077f, 0xc99c, 0x21, 0 + .dw 0x07c0, 0xc99c, 0x07ff, 0xc99c, 0x21, 0 + .dw 0x0840, 0xc99c, 0x087f, 0xc99c, 0x21, 0 + .dw 0x08c0, 0xc99c, 0x08ff, 0xc99c, 0x21, 0 + .dw 0x0940, 0xc99c, 0x097f, 0xc99c, 0x21, 0 + .dw 0x09c0, 0xc99c, 0x09ff, 0xc99c, 0x21, 0 + .dw 0x0a40, 0xc99c, 0x0a7f, 0xc99c, 0x21, 0 + .dw 0x0ac0, 0xc99c, 0x0aff, 0xc99c, 0x21, 0 + .dw 0x0b40, 0xc99c, 0x0b7f, 0xc99c, 0x21, 0 + .dw 0x0bc0, 0xc99c, 0x0bff, 0xc99c, 0x21, 0 + .dw 0x0c40, 0xc99c, 0x0c7f, 0xc99c, 0x21, 0 + .dw 0x0cc0, 0xc99c, 0x0cff, 0xc99c, 0x21, 0 + .dw 0x0d40, 0xc99c, 0x0d7f, 0xc99c, 0x21, 0 + .dw 0x0dc0, 0xc99c, 0x0dff, 0xc99c, 0x21, 0 + .dw 0x0e40, 0xc99c, 0x0e7f, 0xc99c, 0x21, 0 + .dw 0x0ec0, 0xc99c, 0x0eff, 0xc99c, 0x21, 0 + .dw 0x0f40, 0xc99c, 0x0f7f, 0xc99c, 0x21, 0 + .dw 0x0fc0, 0xc99c, 0x0fff, 0xc99c, 0x21, 0 + .dw 0x1040, 0xc99c, 0x107f, 0xc99c, 0x21, 0 + .dw 0x10c0, 0xc99c, 0x10ff, 0xc99c, 0x21, 0 + .dw 0x1140, 0xc99c, 0x117f, 0xc99c, 0x21, 0 + .dw 0x11c0, 0xc99c, 0x11ff, 0xc99c, 0x21, 0 + .dw 0x1240, 0xc99c, 0x127f, 0xc99c, 0x21, 0 + .dw 0x12c0, 0xc99c, 0x12ff, 0xc99c, 0x21, 0 + .dw 0x1340, 0xc99c, 0x137f, 0xc99c, 0x21, 0 + .dw 0x13c0, 0xc99c, 0x13ff, 0xc99c, 0x21, 0 + .dw 0x1440, 0xc99c, 0x147f, 0xc99c, 0x21, 0 + .dw 0x14c0, 0xc99c, 0x14ff, 0xc99c, 0x21, 0 + .dw 0x1540, 0xc99c, 0x157f, 0xc99c, 0x21, 0 + .dw 0x15c0, 0xc99c, 0x15ff, 0xc99c, 0x21, 0 + .dw 0x1640, 0xc99c, 0x167f, 0xc99c, 0x21, 0 + .dw 0x16c0, 0xc99c, 0x16ff, 0xc99c, 0x21, 0 + .dw 0x1740, 0xc99c, 0x177f, 0xc99c, 0x21, 0 + .dw 0x17c0, 0xc99c, 0x17ff, 0xc99c, 0x21, 0 + .dw 0x1840, 0xc99c, 0x187f, 0xc99c, 0x21, 0 + .dw 0x18c0, 0xc99c, 0x18ff, 0xc99c, 0x21, 0 + .dw 0x1940, 0xc99c, 0x197f, 0xc99c, 0x21, 0 + .dw 0x19c0, 0xc99c, 0x1fff, 0xc99c, 0x21, 0 + .dw 0x2040, 0xc99c, 0x207f, 0xc99c, 0x21, 0 + .dw 0x20c0, 0xc99c, 0x20ff, 0xc99c, 0x21, 0 + .dw 0x2140, 0xc99c, 0x217f, 0xc99c, 0x21, 0 + .dw 0x21c0, 0xc99c, 0x21ff, 0xc99c, 0x21, 0 + .dw 0x2240, 0xc99c, 0x227f, 0xc99c, 0x21, 0 + .dw 0x22c0, 0xc99c, 0x22ff, 0xc99c, 0x21, 0 + .dw 0x2340, 0xc99c, 0x237f, 0xc99c, 0x21, 0 + .dw 0x23c0, 0xc99c, 0x23ff, 0xc99c, 0x21, 0 + .dw 0x2440, 0xc99c, 0x247f, 0xc99c, 0x21, 0 + .dw 0x24c0, 0xc99c, 0x24ff, 0xc99c, 0x21, 0 + .dw 0x2540, 0xc99c, 0x257f, 0xc99c, 0x21, 0 + .dw 0x25c0, 0xc99c, 0x25ff, 0xc99c, 0x21, 0 + .dw 0x2640, 0xc99c, 0x267f, 0xc99c, 0x21, 0 + .dw 0x26c0, 0xc99c, 0x26ff, 0xc99c, 0x21, 0 + .dw 0x2740, 0xc99c, 0x277f, 0xc99c, 0x21, 0 + .dw 0x27c0, 0xc99c, 0x27ff, 0xc99c, 0x21, 0 + .dw 0x2840, 0xc99c, 0x287f, 0xc99c, 0x21, 0 + .dw 0x28c0, 0xc99c, 0x28ff, 0xc99c, 0x21, 0 + .dw 0x2940, 0xc99c, 0x297f, 0xc99c, 0x21, 0 + .dw 0x29c0, 0xc99c, 0x29ff, 0xc99c, 0x21, 0 + .dw 0x2a40, 0xc99c, 0x2a7f, 0xc99c, 0x21, 0 + .dw 0x2ac0, 0xc99c, 0x2aff, 0xc99c, 0x21, 0 + .dw 0x2b40, 0xc99c, 0x2b7f, 0xc99c, 0x21, 0 + .dw 0x2bc0, 0xc99c, 0x2bff, 0xc99c, 0x21, 0 + .dw 0x2c40, 0xc99c, 0x2c7f, 0xc99c, 0x21, 0 + .dw 0x2cc0, 0xc99c, 0x2cff, 0xc99c, 0x21, 0 + .dw 0x2d40, 0xc99c, 0x2d7f, 0xc99c, 0x21, 0 + .dw 0x2dc0, 0xc99c, 0x2dff, 0xc99c, 0x21, 0 + .dw 0x2e40, 0xc99c, 0x2e7f, 0xc99c, 0x21, 0 + .dw 0x2ec0, 0xc99c, 0x2eff, 0xc99c, 0x21, 0 + .dw 0x2f40, 0xc99c, 0x2f7f, 0xc99c, 0x21, 0 + .dw 0x2fc0, 0xc99c, 0x2fff, 0xc99c, 0x21, 0 + .dw 0x3040, 0xc99c, 0x307f, 0xc99c, 0x21, 0 + .dw 0x30c0, 0xc99c, 0x30ff, 0xc99c, 0x21, 0 + .dw 0x3140, 0xc99c, 0x317f, 0xc99c, 0x21, 0 + .dw 0x31c0, 0xc99c, 0x31ff, 0xc99c, 0x21, 0 + .dw 0x3240, 0xc99c, 0x327f, 0xc99c, 0x21, 0 + .dw 0x32c0, 0xc99c, 0x32ff, 0xc99c, 0x21, 0 + .dw 0x3340, 0xc99c, 0x337f, 0xc99c, 0x21, 0 + .dw 0x33c0, 0xc99c, 0x33ff, 0xc99c, 0x21, 0 + .dw 0x3440, 0xc99c, 0x347f, 0xc99c, 0x21, 0 + .dw 0x34c0, 0xc99c, 0x34ff, 0xc99c, 0x21, 0 + .dw 0x3540, 0xc99c, 0x357f, 0xc99c, 0x21, 0 + .dw 0x35c0, 0xc99c, 0x35ff, 0xc99c, 0x21, 0 + .dw 0x3640, 0xc99c, 0x367f, 0xc99c, 0x21, 0 + .dw 0x36c0, 0xc99c, 0x36ff, 0xc99c, 0x21, 0 + .dw 0x3740, 0xc99c, 0x377f, 0xc99c, 0x21, 0 + .dw 0x37c0, 0xc99c, 0x37ff, 0xc99c, 0x21, 0 + .dw 0x3840, 0xc99c, 0x387f, 0xc99c, 0x21, 0 + .dw 0x38c0, 0xc99c, 0x38ff, 0xc99c, 0x21, 0 + .dw 0x3940, 0xc99c, 0x397f, 0xc99c, 0x21, 0 + .dw 0x39c0, 0xc99c, 0x3fff, 0xc99c, 0x21, 0 + .dw 0x4040, 0xc99c, 0x407f, 0xc99c, 0x21, 0 + .dw 0x40c0, 0xc99c, 0x40ff, 0xc99c, 0x21, 0 + .dw 0x4140, 0xc99c, 0x417f, 0xc99c, 0x21, 0 + .dw 0x41c0, 0xc99c, 0x41ff, 0xc99c, 0x21, 0 + .dw 0x4240, 0xc99c, 0x427f, 0xc99c, 0x21, 0 + .dw 0x42c0, 0xc99c, 0x42ff, 0xc99c, 0x21, 0 + .dw 0x4340, 0xc99c, 0x437f, 0xc99c, 0x21, 0 + .dw 0x43c0, 0xc99c, 0x43ff, 0xc99c, 0x21, 0 + .dw 0x4440, 0xc99c, 0x447f, 0xc99c, 0x21, 0 + .dw 0x44c0, 0xc99c, 0x44ff, 0xc99c, 0x21, 0 + .dw 0x4540, 0xc99c, 0x457f, 0xc99c, 0x21, 0 + .dw 0x45c0, 0xc99c, 0x45ff, 0xc99c, 0x21, 0 + .dw 0x4640, 0xc99c, 0x467f, 0xc99c, 0x21, 0 + .dw 0x46c0, 0xc99c, 0x46ff, 0xc99c, 0x21, 0 + .dw 0x4740, 0xc99c, 0x477f, 0xc99c, 0x21, 0 + .dw 0x47c0, 0xc99c, 0x47ff, 0xc99c, 0x21, 0 + .dw 0x4840, 0xc99c, 0x487f, 0xc99c, 0x21, 0 + .dw 0x48c0, 0xc99c, 0x48ff, 0xc99c, 0x21, 0 + .dw 0x4940, 0xc99c, 0x497f, 0xc99c, 0x21, 0 + .dw 0x49c0, 0xc99c, 0x49ff, 0xc99c, 0x21, 0 + .dw 0x4a40, 0xc99c, 0x4a7f, 0xc99c, 0x21, 0 + .dw 0x4ac0, 0xc99c, 0x4aff, 0xc99c, 0x21, 0 + .dw 0x4b40, 0xc99c, 0x4b7f, 0xc99c, 0x21, 0 + .dw 0x4bc0, 0xc99c, 0x4bff, 0xc99c, 0x21, 0 + .dw 0x4c40, 0xc99c, 0x4c7f, 0xc99c, 0x21, 0 + .dw 0x4cc0, 0xc99c, 0x4cff, 0xc99c, 0x21, 0 + .dw 0x4d40, 0xc99c, 0x4d7f, 0xc99c, 0x21, 0 + .dw 0x4dc0, 0xc99c, 0x4dff, 0xc99c, 0x21, 0 + .dw 0x4e40, 0xc99c, 0x4e7f, 0xc99c, 0x21, 0 + .dw 0x4ec0, 0xc99c, 0x4eff, 0xc99c, 0x21, 0 + .dw 0x4f40, 0xc99c, 0x4f7f, 0xc99c, 0x21, 0 + .dw 0x4fc0, 0xc99c, 0x4fff, 0xc99c, 0x21, 0 + .dw 0x5040, 0xc99c, 0x507f, 0xc99c, 0x21, 0 + .dw 0x50c0, 0xc99c, 0x50ff, 0xc99c, 0x21, 0 + .dw 0x5140, 0xc99c, 0x517f, 0xc99c, 0x21, 0 + .dw 0x51c0, 0xc99c, 0x51ff, 0xc99c, 0x21, 0 + .dw 0x5240, 0xc99c, 0x527f, 0xc99c, 0x21, 0 + .dw 0x52c0, 0xc99c, 0x52ff, 0xc99c, 0x21, 0 + .dw 0x5340, 0xc99c, 0x537f, 0xc99c, 0x21, 0 + .dw 0x53c0, 0xc99c, 0x53ff, 0xc99c, 0x21, 0 + .dw 0x5440, 0xc99c, 0x547f, 0xc99c, 0x21, 0 + .dw 0x54c0, 0xc99c, 0x54ff, 0xc99c, 0x21, 0 + .dw 0x5540, 0xc99c, 0x557f, 0xc99c, 0x21, 0 + .dw 0x55c0, 0xc99c, 0x55ff, 0xc99c, 0x21, 0 + .dw 0x5640, 0xc99c, 0x567f, 0xc99c, 0x21, 0 + .dw 0x56c0, 0xc99c, 0x56ff, 0xc99c, 0x21, 0 + .dw 0x5740, 0xc99c, 0x577f, 0xc99c, 0x21, 0 + .dw 0x57c0, 0xc99c, 0x57ff, 0xc99c, 0x21, 0 + .dw 0x5840, 0xc99c, 0x587f, 0xc99c, 0x21, 0 + .dw 0x58c0, 0xc99c, 0x58ff, 0xc99c, 0x21, 0 + .dw 0x5940, 0xc99c, 0x597f, 0xc99c, 0x21, 0 + .dw 0x59c0, 0xc99c, 0x5fff, 0xc99c, 0x21, 0 + .dw 0x6040, 0xc99c, 0x607f, 0xc99c, 0x21, 0 + .dw 0x60c0, 0xc99c, 0x60ff, 0xc99c, 0x21, 0 + .dw 0x6140, 0xc99c, 0x617f, 0xc99c, 0x21, 0 + .dw 0x61c0, 0xc99c, 0x61ff, 0xc99c, 0x21, 0 + .dw 0x6240, 0xc99c, 0x627f, 0xc99c, 0x21, 0 + .dw 0x62c0, 0xc99c, 0x62ff, 0xc99c, 0x21, 0 + .dw 0x6340, 0xc99c, 0x637f, 0xc99c, 0x21, 0 + .dw 0x63c0, 0xc99c, 0x63ff, 0xc99c, 0x21, 0 + .dw 0x6440, 0xc99c, 0x647f, 0xc99c, 0x21, 0 + .dw 0x64c0, 0xc99c, 0x64ff, 0xc99c, 0x21, 0 + .dw 0x6540, 0xc99c, 0x657f, 0xc99c, 0x21, 0 + .dw 0x65c0, 0xc99c, 0x65ff, 0xc99c, 0x21, 0 + .dw 0x6640, 0xc99c, 0x667f, 0xc99c, 0x21, 0 + .dw 0x66c0, 0xc99c, 0x66ff, 0xc99c, 0x21, 0 + .dw 0x6740, 0xc99c, 0x677f, 0xc99c, 0x21, 0 + .dw 0x67c0, 0xc99c, 0x67ff, 0xc99c, 0x21, 0 + .dw 0x6840, 0xc99c, 0x687f, 0xc99c, 0x21, 0 + .dw 0x68c0, 0xc99c, 0x68ff, 0xc99c, 0x21, 0 + .dw 0x6940, 0xc99c, 0x697f, 0xc99c, 0x21, 0 + .dw 0x69c0, 0xc99c, 0x69ff, 0xc99c, 0x21, 0 + .dw 0x6a40, 0xc99c, 0x6a7f, 0xc99c, 0x21, 0 + .dw 0x6ac0, 0xc99c, 0x6aff, 0xc99c, 0x21, 0 + .dw 0x6b40, 0xc99c, 0x6b7f, 0xc99c, 0x21, 0 + .dw 0x6bc0, 0xc99c, 0x6bff, 0xc99c, 0x21, 0 + .dw 0x6c40, 0xc99c, 0x6c7f, 0xc99c, 0x21, 0 + .dw 0x6cc0, 0xc99c, 0x6cff, 0xc99c, 0x21, 0 + .dw 0x6d40, 0xc99c, 0x6d7f, 0xc99c, 0x21, 0 + .dw 0x6dc0, 0xc99c, 0x6dff, 0xc99c, 0x21, 0 + .dw 0x6e40, 0xc99c, 0x6e7f, 0xc99c, 0x21, 0 + .dw 0x6ec0, 0xc99c, 0x6eff, 0xc99c, 0x21, 0 + .dw 0x6f40, 0xc99c, 0x6f7f, 0xc99c, 0x21, 0 + .dw 0x6fc0, 0xc99c, 0x6fff, 0xc99c, 0x21, 0 + .dw 0x7040, 0xc99c, 0x707f, 0xc99c, 0x21, 0 + .dw 0x70c0, 0xc99c, 0x70ff, 0xc99c, 0x21, 0 + .dw 0x7140, 0xc99c, 0x717f, 0xc99c, 0x21, 0 + .dw 0x71c0, 0xc99c, 0x71ff, 0xc99c, 0x21, 0 + .dw 0x7240, 0xc99c, 0x727f, 0xc99c, 0x21, 0 + .dw 0x72c0, 0xc99c, 0x72ff, 0xc99c, 0x21, 0 + .dw 0x7340, 0xc99c, 0x737f, 0xc99c, 0x21, 0 + .dw 0x73c0, 0xc99c, 0x73ff, 0xc99c, 0x21, 0 + .dw 0x7440, 0xc99c, 0x747f, 0xc99c, 0x21, 0 + .dw 0x74c0, 0xc99c, 0x74ff, 0xc99c, 0x21, 0 + .dw 0x7540, 0xc99c, 0x757f, 0xc99c, 0x21, 0 + .dw 0x75c0, 0xc99c, 0x75ff, 0xc99c, 0x21, 0 + .dw 0x7640, 0xc99c, 0x767f, 0xc99c, 0x21, 0 + .dw 0x76c0, 0xc99c, 0x76ff, 0xc99c, 0x21, 0 + .dw 0x7740, 0xc99c, 0x777f, 0xc99c, 0x21, 0 + .dw 0x77c0, 0xc99c, 0x77ff, 0xc99c, 0x21, 0 + .dw 0x7840, 0xc99c, 0x787f, 0xc99c, 0x21, 0 + .dw 0x78c0, 0xc99c, 0x78ff, 0xc99c, 0x21, 0 + .dw 0x7940, 0xc99c, 0x797f, 0xc99c, 0x21, 0 + .dw 0x79c0, 0xc99c, 0x7fff, 0xc99c, 0x21, 0 + .dw 0x8040, 0xc99c, 0x807f, 0xc99c, 0x21, 0 + .dw 0x80c0, 0xc99c, 0x80ff, 0xc99c, 0x21, 0 + .dw 0x8140, 0xc99c, 0x817f, 0xc99c, 0x21, 0 + .dw 0x81c0, 0xc99c, 0x81ff, 0xc99c, 0x21, 0 + .dw 0x8240, 0xc99c, 0x827f, 0xc99c, 0x21, 0 + .dw 0x82c0, 0xc99c, 0x82ff, 0xc99c, 0x21, 0 + .dw 0x8340, 0xc99c, 0x837f, 0xc99c, 0x21, 0 + .dw 0x83c0, 0xc99c, 0x83ff, 0xc99c, 0x21, 0 + .dw 0x8440, 0xc99c, 0x847f, 0xc99c, 0x21, 0 + .dw 0x84c0, 0xc99c, 0x84ff, 0xc99c, 0x21, 0 + .dw 0x8540, 0xc99c, 0x857f, 0xc99c, 0x21, 0 + .dw 0x85c0, 0xc99c, 0x85ff, 0xc99c, 0x21, 0 + .dw 0x8640, 0xc99c, 0x867f, 0xc99c, 0x21, 0 + .dw 0x86c0, 0xc99c, 0x86ff, 0xc99c, 0x21, 0 + .dw 0x8740, 0xc99c, 0x877f, 0xc99c, 0x21, 0 + .dw 0x87c0, 0xc99c, 0x87ff, 0xc99c, 0x21, 0 + .dw 0x8840, 0xc99c, 0x887f, 0xc99c, 0x21, 0 + .dw 0x88c0, 0xc99c, 0x88ff, 0xc99c, 0x21, 0 + .dw 0x8940, 0xc99c, 0x897f, 0xc99c, 0x21, 0 + .dw 0x89c0, 0xc99c, 0x89ff, 0xc99c, 0x21, 0 + .dw 0x8a40, 0xc99c, 0x8a7f, 0xc99c, 0x21, 0 + .dw 0x8ac0, 0xc99c, 0x8aff, 0xc99c, 0x21, 0 + .dw 0x8b40, 0xc99c, 0x8b7f, 0xc99c, 0x21, 0 + .dw 0x8bc0, 0xc99c, 0x8bff, 0xc99c, 0x21, 0 + .dw 0x8c40, 0xc99c, 0x8c7f, 0xc99c, 0x21, 0 + .dw 0x8cc0, 0xc99c, 0x8cff, 0xc99c, 0x21, 0 + .dw 0x8d40, 0xc99c, 0x8d7f, 0xc99c, 0x21, 0 + .dw 0x8dc0, 0xc99c, 0x8dff, 0xc99c, 0x21, 0 + .dw 0x8e40, 0xc99c, 0x8e7f, 0xc99c, 0x21, 0 + .dw 0x8ec0, 0xc99c, 0x8eff, 0xc99c, 0x21, 0 + .dw 0x8f40, 0xc99c, 0x8f7f, 0xc99c, 0x21, 0 + .dw 0x8fc0, 0xc99c, 0x8fff, 0xc99c, 0x21, 0 + .dw 0x9040, 0xc99c, 0x907f, 0xc99c, 0x21, 0 + .dw 0x90c0, 0xc99c, 0x90ff, 0xc99c, 0x21, 0 + .dw 0x9140, 0xc99c, 0x917f, 0xc99c, 0x21, 0 + .dw 0x91c0, 0xc99c, 0x91ff, 0xc99c, 0x21, 0 + .dw 0x9240, 0xc99c, 0x927f, 0xc99c, 0x21, 0 + .dw 0x92c0, 0xc99c, 0x92ff, 0xc99c, 0x21, 0 + .dw 0x9340, 0xc99c, 0x937f, 0xc99c, 0x21, 0 + .dw 0x93c0, 0xc99c, 0x93ff, 0xc99c, 0x21, 0 + .dw 0x9440, 0xc99c, 0x947f, 0xc99c, 0x21, 0 + .dw 0x94c0, 0xc99c, 0x94ff, 0xc99c, 0x21, 0 + .dw 0x9540, 0xc99c, 0x957f, 0xc99c, 0x21, 0 + .dw 0x95c0, 0xc99c, 0x95ff, 0xc99c, 0x21, 0 + .dw 0x9640, 0xc99c, 0x967f, 0xc99c, 0x21, 0 + .dw 0x96c0, 0xc99c, 0x96ff, 0xc99c, 0x21, 0 + .dw 0x9740, 0xc99c, 0x977f, 0xc99c, 0x21, 0 + .dw 0x97c0, 0xc99c, 0x97ff, 0xc99c, 0x21, 0 + .dw 0x9840, 0xc99c, 0x987f, 0xc99c, 0x21, 0 + .dw 0x98c0, 0xc99c, 0x98ff, 0xc99c, 0x21, 0 + .dw 0x9940, 0xc99c, 0x997f, 0xc99c, 0x21, 0 + .dw 0x99c0, 0xc99c, 0x9fff, 0xc99c, 0x21, 0 + .dw 0xa040, 0xc99c, 0xa07f, 0xc99c, 0x21, 0 + .dw 0xa0c0, 0xc99c, 0xa0ff, 0xc99c, 0x21, 0 + .dw 0xa140, 0xc99c, 0xa17f, 0xc99c, 0x21, 0 + .dw 0xa1c0, 0xc99c, 0xa1ff, 0xc99c, 0x21, 0 + .dw 0xa240, 0xc99c, 0xa27f, 0xc99c, 0x21, 0 + .dw 0xa2c0, 0xc99c, 0xa2ff, 0xc99c, 0x21, 0 + .dw 0xa340, 0xc99c, 0xa37f, 0xc99c, 0x21, 0 + .dw 0xa3c0, 0xc99c, 0xa3ff, 0xc99c, 0x21, 0 + .dw 0xa440, 0xc99c, 0xa47f, 0xc99c, 0x21, 0 + .dw 0xa4c0, 0xc99c, 0xa4ff, 0xc99c, 0x21, 0 + .dw 0xa540, 0xc99c, 0xa57f, 0xc99c, 0x21, 0 + .dw 0xa5c0, 0xc99c, 0xa5ff, 0xc99c, 0x21, 0 + .dw 0xa640, 0xc99c, 0xa67f, 0xc99c, 0x21, 0 + .dw 0xa6c0, 0xc99c, 0xa6ff, 0xc99c, 0x21, 0 + .dw 0xa740, 0xc99c, 0xa77f, 0xc99c, 0x21, 0 + .dw 0xa7c0, 0xc99c, 0xa7ff, 0xc99c, 0x21, 0 + .dw 0xa840, 0xc99c, 0xa87f, 0xc99c, 0x21, 0 + .dw 0xa8c0, 0xc99c, 0xa8ff, 0xc99c, 0x21, 0 + .dw 0xa940, 0xc99c, 0xa97f, 0xc99c, 0x21, 0 + .dw 0xa9c0, 0xc99c, 0xa9ff, 0xc99c, 0x21, 0 + .dw 0xaa40, 0xc99c, 0xaa7f, 0xc99c, 0x21, 0 + .dw 0xaac0, 0xc99c, 0xaaff, 0xc99c, 0x21, 0 + .dw 0xab40, 0xc99c, 0xab7f, 0xc99c, 0x21, 0 + .dw 0xabc0, 0xc99c, 0xabff, 0xc99c, 0x21, 0 + .dw 0xac40, 0xc99c, 0xac7f, 0xc99c, 0x21, 0 + .dw 0xacc0, 0xc99c, 0xacff, 0xc99c, 0x21, 0 + .dw 0xad40, 0xc99c, 0xad7f, 0xc99c, 0x21, 0 + .dw 0xadc0, 0xc99c, 0xadff, 0xc99c, 0x21, 0 + .dw 0xae40, 0xc99c, 0xae7f, 0xc99c, 0x21, 0 + .dw 0xaec0, 0xc99c, 0xaeff, 0xc99c, 0x21, 0 + .dw 0xaf40, 0xc99c, 0xaf7f, 0xc99c, 0x21, 0 + .dw 0xafc0, 0xc99c, 0xafff, 0xc99c, 0x21, 0 + .dw 0xb040, 0xc99c, 0xb07f, 0xc99c, 0x21, 0 + .dw 0xb0c0, 0xc99c, 0xb0ff, 0xc99c, 0x21, 0 + .dw 0xb140, 0xc99c, 0xb17f, 0xc99c, 0x21, 0 + .dw 0xb1c0, 0xc99c, 0xb1ff, 0xc99c, 0x21, 0 + .dw 0xb240, 0xc99c, 0xb27f, 0xc99c, 0x21, 0 + .dw 0xb2c0, 0xc99c, 0xb2ff, 0xc99c, 0x21, 0 + .dw 0xb340, 0xc99c, 0xb37f, 0xc99c, 0x21, 0 + .dw 0xb3c0, 0xc99c, 0xb3ff, 0xc99c, 0x21, 0 + .dw 0xb440, 0xc99c, 0xb47f, 0xc99c, 0x21, 0 + .dw 0xb4c0, 0xc99c, 0xb4ff, 0xc99c, 0x21, 0 + .dw 0xb540, 0xc99c, 0xb57f, 0xc99c, 0x21, 0 + .dw 0xb5c0, 0xc99c, 0xb5ff, 0xc99c, 0x21, 0 + .dw 0xb640, 0xc99c, 0xb67f, 0xc99c, 0x21, 0 + .dw 0xb6c0, 0xc99c, 0xb6ff, 0xc99c, 0x21, 0 + .dw 0xb740, 0xc99c, 0xb77f, 0xc99c, 0x21, 0 + .dw 0xb7c0, 0xc99c, 0xb7ff, 0xc99c, 0x21, 0 + .dw 0xb840, 0xc99c, 0xb87f, 0xc99c, 0x21, 0 + .dw 0xb8c0, 0xc99c, 0xb8ff, 0xc99c, 0x21, 0 + .dw 0xb940, 0xc99c, 0xb97f, 0xc99c, 0x21, 0 + .dw 0xb9c0, 0xc99c, 0xbfff, 0xc99c, 0x21, 0 + .dw 0xc040, 0xc99c, 0xc07f, 0xc99c, 0x21, 0 + .dw 0xc0c0, 0xc99c, 0xc0ff, 0xc99c, 0x21, 0 + .dw 0xc140, 0xc99c, 0xc17f, 0xc99c, 0x21, 0 + .dw 0xc1c0, 0xc99c, 0xc1ff, 0xc99c, 0x21, 0 + .dw 0xc240, 0xc99c, 0xc27f, 0xc99c, 0x21, 0 + .dw 0xc2c0, 0xc99c, 0xc2ff, 0xc99c, 0x21, 0 + .dw 0xc340, 0xc99c, 0xc37f, 0xc99c, 0x21, 0 + .dw 0xc3c0, 0xc99c, 0xc3ff, 0xc99c, 0x21, 0 + .dw 0xc440, 0xc99c, 0xc47f, 0xc99c, 0x21, 0 + .dw 0xc4c0, 0xc99c, 0xc4ff, 0xc99c, 0x21, 0 + .dw 0xc540, 0xc99c, 0xc57f, 0xc99c, 0x21, 0 + .dw 0xc5c0, 0xc99c, 0xc5ff, 0xc99c, 0x21, 0 + .dw 0xc640, 0xc99c, 0xc67f, 0xc99c, 0x21, 0 + .dw 0xc6c0, 0xc99c, 0xc6ff, 0xc99c, 0x21, 0 + .dw 0xc740, 0xc99c, 0xc77f, 0xc99c, 0x21, 0 + .dw 0xc7c0, 0xc99c, 0xc7ff, 0xc99c, 0x21, 0 + .dw 0xc840, 0xc99c, 0xc87f, 0xc99c, 0x21, 0 + .dw 0xc8c0, 0xc99c, 0xc8ff, 0xc99c, 0x21, 0 + .dw 0xc940, 0xc99c, 0xc97f, 0xc99c, 0x21, 0 + .dw 0xc9c0, 0xc99c, 0xc9ff, 0xc99c, 0x21, 0 + .dw 0xca40, 0xc99c, 0xca7f, 0xc99c, 0x21, 0 + .dw 0xcac0, 0xc99c, 0xcaff, 0xc99c, 0x21, 0 + .dw 0xcb40, 0xc99c, 0xcb7f, 0xc99c, 0x21, 0 + .dw 0xcbc0, 0xc99c, 0xcbff, 0xc99c, 0x21, 0 + .dw 0xcc40, 0xc99c, 0xcc7f, 0xc99c, 0x21, 0 + .dw 0xccc0, 0xc99c, 0xccff, 0xc99c, 0x21, 0 + .dw 0xcd40, 0xc99c, 0xcd7f, 0xc99c, 0x21, 0 + .dw 0xcdc0, 0xc99c, 0xcdff, 0xc99c, 0x21, 0 + .dw 0xce40, 0xc99c, 0xce7f, 0xc99c, 0x21, 0 + .dw 0xcec0, 0xc99c, 0xceff, 0xc99c, 0x21, 0 + .dw 0xcf40, 0xc99c, 0xcf7f, 0xc99c, 0x21, 0 + .dw 0xcfc0, 0xc99c, 0xcfff, 0xc99c, 0x21, 0 + .dw 0xd040, 0xc99c, 0xd07f, 0xc99c, 0x21, 0 + .dw 0xd0c0, 0xc99c, 0xd0ff, 0xc99c, 0x21, 0 + .dw 0xd140, 0xc99c, 0xd17f, 0xc99c, 0x21, 0 + .dw 0xd1c0, 0xc99c, 0xd1ff, 0xc99c, 0x21, 0 + .dw 0xd240, 0xc99c, 0xd27f, 0xc99c, 0x21, 0 + .dw 0xd2c0, 0xc99c, 0xd2ff, 0xc99c, 0x21, 0 + .dw 0xd340, 0xc99c, 0xd37f, 0xc99c, 0x21, 0 + .dw 0xd3c0, 0xc99c, 0xd3ff, 0xc99c, 0x21, 0 + .dw 0xd440, 0xc99c, 0xd47f, 0xc99c, 0x21, 0 + .dw 0xd4c0, 0xc99c, 0xd4ff, 0xc99c, 0x21, 0 + .dw 0xd540, 0xc99c, 0xd57f, 0xc99c, 0x21, 0 + .dw 0xd5c0, 0xc99c, 0xd5ff, 0xc99c, 0x21, 0 + .dw 0xd640, 0xc99c, 0xd67f, 0xc99c, 0x21, 0 + .dw 0xd6c0, 0xc99c, 0xd6ff, 0xc99c, 0x21, 0 + .dw 0xd740, 0xc99c, 0xd77f, 0xc99c, 0x21, 0 + .dw 0xd7c0, 0xc99c, 0xd7ff, 0xc99c, 0x21, 0 + .dw 0xd840, 0xc99c, 0xd87f, 0xc99c, 0x21, 0 + .dw 0xd8c0, 0xc99c, 0xd8ff, 0xc99c, 0x21, 0 + .dw 0xd940, 0xc99c, 0xd97f, 0xc99c, 0x21, 0 + .dw 0xd9c0, 0xc99c, 0xdfff, 0xc99c, 0x21, 0 + .dw 0xe040, 0xc99c, 0xe07f, 0xc99c, 0x21, 0 + .dw 0xe0c0, 0xc99c, 0xe0ff, 0xc99c, 0x21, 0 + .dw 0xe140, 0xc99c, 0xe17f, 0xc99c, 0x21, 0 + .dw 0xe1c0, 0xc99c, 0xe1ff, 0xc99c, 0x21, 0 + .dw 0xe240, 0xc99c, 0xe27f, 0xc99c, 0x21, 0 + .dw 0xe2c0, 0xc99c, 0xe2ff, 0xc99c, 0x21, 0 + .dw 0xe340, 0xc99c, 0xe37f, 0xc99c, 0x21, 0 + .dw 0xe3c0, 0xc99c, 0xe3ff, 0xc99c, 0x21, 0 + .dw 0xe440, 0xc99c, 0xe47f, 0xc99c, 0x21, 0 + .dw 0xe4c0, 0xc99c, 0xe4ff, 0xc99c, 0x21, 0 + .dw 0xe540, 0xc99c, 0xe57f, 0xc99c, 0x21, 0 + .dw 0xe5c0, 0xc99c, 0xe5ff, 0xc99c, 0x21, 0 + .dw 0xe640, 0xc99c, 0xe67f, 0xc99c, 0x21, 0 + .dw 0xe6c0, 0xc99c, 0xe6ff, 0xc99c, 0x21, 0 + .dw 0xe740, 0xc99c, 0xe77f, 0xc99c, 0x21, 0 + .dw 0xe7c0, 0xc99c, 0xe7ff, 0xc99c, 0x21, 0 + .dw 0xe840, 0xc99c, 0xe87f, 0xc99c, 0x21, 0 + .dw 0xe8c0, 0xc99c, 0xe8ff, 0xc99c, 0x21, 0 + .dw 0xe940, 0xc99c, 0xe97f, 0xc99c, 0x21, 0 + .dw 0xe9c0, 0xc99c, 0xe9ff, 0xc99c, 0x21, 0 + .dw 0xea40, 0xc99c, 0xea7f, 0xc99c, 0x21, 0 + .dw 0xeac0, 0xc99c, 0xeaff, 0xc99c, 0x21, 0 + .dw 0xeb40, 0xc99c, 0xeb7f, 0xc99c, 0x21, 0 + .dw 0xebc0, 0xc99c, 0xebff, 0xc99c, 0x21, 0 + .dw 0xec40, 0xc99c, 0xec7f, 0xc99c, 0x21, 0 + .dw 0xecc0, 0xc99c, 0xecff, 0xc99c, 0x21, 0 + .dw 0xed40, 0xc99c, 0xed7f, 0xc99c, 0x21, 0 + .dw 0xedc0, 0xc99c, 0xedff, 0xc99c, 0x21, 0 + .dw 0xee40, 0xc99c, 0xee7f, 0xc99c, 0x21, 0 + .dw 0xeec0, 0xc99c, 0xeeff, 0xc99c, 0x21, 0 + .dw 0xef40, 0xc99c, 0xef7f, 0xc99c, 0x21, 0 + .dw 0xefc0, 0xc99c, 0xefff, 0xc99c, 0x21, 0 + .dw 0xf040, 0xc99c, 0xf07f, 0xc99c, 0x21, 0 + .dw 0xf0c0, 0xc99c, 0xf0ff, 0xc99c, 0x21, 0 + .dw 0xf140, 0xc99c, 0xf17f, 0xc99c, 0x21, 0 + .dw 0xf1c0, 0xc99c, 0xf1ff, 0xc99c, 0x21, 0 + .dw 0xf240, 0xc99c, 0xf27f, 0xc99c, 0x21, 0 + .dw 0xf2c0, 0xc99c, 0xf2ff, 0xc99c, 0x21, 0 + .dw 0xf340, 0xc99c, 0xf37f, 0xc99c, 0x21, 0 + .dw 0xf3c0, 0xc99c, 0xf3ff, 0xc99c, 0x21, 0 + .dw 0xf440, 0xc99c, 0xf47f, 0xc99c, 0x21, 0 + .dw 0xf4c0, 0xc99c, 0xf4ff, 0xc99c, 0x21, 0 + .dw 0xf540, 0xc99c, 0xf57f, 0xc99c, 0x21, 0 + .dw 0xf5c0, 0xc99c, 0xf5ff, 0xc99c, 0x21, 0 + .dw 0xf640, 0xc99c, 0xf67f, 0xc99c, 0x21, 0 + .dw 0xf6c0, 0xc99c, 0xf6ff, 0xc99c, 0x21, 0 + .dw 0xf740, 0xc99c, 0xf77f, 0xc99c, 0x21, 0 + .dw 0xf7c0, 0xc99c, 0xf7ff, 0xc99c, 0x21, 0 + .dw 0xf840, 0xc99c, 0xf87f, 0xc99c, 0x21, 0 + .dw 0xf8c0, 0xc99c, 0xf8ff, 0xc99c, 0x21, 0 + .dw 0xf940, 0xc99c, 0xf97f, 0xc99c, 0x21, 0 + .dw 0xf9c0, 0xc99c, 0xffff, 0xc99c, 0x21, 0 + .dw 0x0040, 0xc99d, 0x007f, 0xc99d, 0x21, 0 + .dw 0x00c0, 0xc99d, 0x00ff, 0xc99d, 0x21, 0 + .dw 0x0140, 0xc99d, 0x017f, 0xc99d, 0x21, 0 + .dw 0x01c0, 0xc99d, 0x01ff, 0xc99d, 0x21, 0 + .dw 0x0240, 0xc99d, 0x027f, 0xc99d, 0x21, 0 + .dw 0x02c0, 0xc99d, 0x02ff, 0xc99d, 0x21, 0 + .dw 0x0340, 0xc99d, 0x037f, 0xc99d, 0x21, 0 + .dw 0x03c0, 0xc99d, 0x03ff, 0xc99d, 0x21, 0 + .dw 0x0440, 0xc99d, 0x047f, 0xc99d, 0x21, 0 + .dw 0x04c0, 0xc99d, 0x04ff, 0xc99d, 0x21, 0 + .dw 0x0540, 0xc99d, 0x057f, 0xc99d, 0x21, 0 + .dw 0x05c0, 0xc99d, 0x05ff, 0xc99d, 0x21, 0 + .dw 0x0640, 0xc99d, 0x067f, 0xc99d, 0x21, 0 + .dw 0x06c0, 0xc99d, 0x06ff, 0xc99d, 0x21, 0 + .dw 0x0740, 0xc99d, 0x077f, 0xc99d, 0x21, 0 + .dw 0x07c0, 0xc99d, 0x07ff, 0xc99d, 0x21, 0 + .dw 0x0840, 0xc99d, 0x087f, 0xc99d, 0x21, 0 + .dw 0x08c0, 0xc99d, 0x08ff, 0xc99d, 0x21, 0 + .dw 0x0940, 0xc99d, 0x097f, 0xc99d, 0x21, 0 + .dw 0x09c0, 0xc99d, 0x09ff, 0xc99d, 0x21, 0 + .dw 0x0a40, 0xc99d, 0x0a7f, 0xc99d, 0x21, 0 + .dw 0x0ac0, 0xc99d, 0x0aff, 0xc99d, 0x21, 0 + .dw 0x0b40, 0xc99d, 0x0b7f, 0xc99d, 0x21, 0 + .dw 0x0bc0, 0xc99d, 0x0bff, 0xc99d, 0x21, 0 + .dw 0x0c40, 0xc99d, 0x0c7f, 0xc99d, 0x21, 0 + .dw 0x0cc0, 0xc99d, 0x0cff, 0xc99d, 0x21, 0 + .dw 0x0d40, 0xc99d, 0x0d7f, 0xc99d, 0x21, 0 + .dw 0x0dc0, 0xc99d, 0x0dff, 0xc99d, 0x21, 0 + .dw 0x0e40, 0xc99d, 0x0e7f, 0xc99d, 0x21, 0 + .dw 0x0ec0, 0xc99d, 0x0eff, 0xc99d, 0x21, 0 + .dw 0x0f40, 0xc99d, 0x0f7f, 0xc99d, 0x21, 0 + .dw 0x0fc0, 0xc99d, 0x0fff, 0xc99d, 0x21, 0 + .dw 0x1040, 0xc99d, 0x107f, 0xc99d, 0x21, 0 + .dw 0x10c0, 0xc99d, 0x10ff, 0xc99d, 0x21, 0 + .dw 0x1140, 0xc99d, 0x117f, 0xc99d, 0x21, 0 + .dw 0x11c0, 0xc99d, 0x11ff, 0xc99d, 0x21, 0 + .dw 0x1240, 0xc99d, 0x127f, 0xc99d, 0x21, 0 + .dw 0x12c0, 0xc99d, 0x12ff, 0xc99d, 0x21, 0 + .dw 0x1340, 0xc99d, 0x137f, 0xc99d, 0x21, 0 + .dw 0x13c0, 0xc99d, 0x13ff, 0xc99d, 0x21, 0 + .dw 0x1440, 0xc99d, 0x147f, 0xc99d, 0x21, 0 + .dw 0x14c0, 0xc99d, 0x14ff, 0xc99d, 0x21, 0 + .dw 0x1540, 0xc99d, 0x157f, 0xc99d, 0x21, 0 + .dw 0x15c0, 0xc99d, 0x15ff, 0xc99d, 0x21, 0 + .dw 0x1640, 0xc99d, 0x167f, 0xc99d, 0x21, 0 + .dw 0x16c0, 0xc99d, 0x16ff, 0xc99d, 0x21, 0 + .dw 0x1740, 0xc99d, 0x177f, 0xc99d, 0x21, 0 + .dw 0x17c0, 0xc99d, 0x17ff, 0xc99d, 0x21, 0 + .dw 0x1840, 0xc99d, 0x187f, 0xc99d, 0x21, 0 + .dw 0x18c0, 0xc99d, 0x18ff, 0xc99d, 0x21, 0 + .dw 0x1940, 0xc99d, 0x197f, 0xc99d, 0x21, 0 + .dw 0x19c0, 0xc99d, 0x1fff, 0xc99d, 0x21, 0 + .dw 0x2040, 0xc99d, 0x207f, 0xc99d, 0x21, 0 + .dw 0x20c0, 0xc99d, 0x20ff, 0xc99d, 0x21, 0 + .dw 0x2140, 0xc99d, 0x217f, 0xc99d, 0x21, 0 + .dw 0x21c0, 0xc99d, 0x21ff, 0xc99d, 0x21, 0 + .dw 0x2240, 0xc99d, 0x227f, 0xc99d, 0x21, 0 + .dw 0x22c0, 0xc99d, 0x22ff, 0xc99d, 0x21, 0 + .dw 0x2340, 0xc99d, 0x237f, 0xc99d, 0x21, 0 + .dw 0x23c0, 0xc99d, 0x23ff, 0xc99d, 0x21, 0 + .dw 0x2440, 0xc99d, 0x247f, 0xc99d, 0x21, 0 + .dw 0x24c0, 0xc99d, 0x24ff, 0xc99d, 0x21, 0 + .dw 0x2540, 0xc99d, 0x257f, 0xc99d, 0x21, 0 + .dw 0x25c0, 0xc99d, 0x25ff, 0xc99d, 0x21, 0 + .dw 0x2640, 0xc99d, 0x267f, 0xc99d, 0x21, 0 + .dw 0x26c0, 0xc99d, 0x26ff, 0xc99d, 0x21, 0 + .dw 0x2740, 0xc99d, 0x277f, 0xc99d, 0x21, 0 + .dw 0x27c0, 0xc99d, 0x27ff, 0xc99d, 0x21, 0 + .dw 0x2840, 0xc99d, 0x287f, 0xc99d, 0x21, 0 + .dw 0x28c0, 0xc99d, 0x28ff, 0xc99d, 0x21, 0 + .dw 0x2940, 0xc99d, 0x297f, 0xc99d, 0x21, 0 + .dw 0x29c0, 0xc99d, 0x29ff, 0xc99d, 0x21, 0 + .dw 0x2a40, 0xc99d, 0x2a7f, 0xc99d, 0x21, 0 + .dw 0x2ac0, 0xc99d, 0x2aff, 0xc99d, 0x21, 0 + .dw 0x2b40, 0xc99d, 0x2b7f, 0xc99d, 0x21, 0 + .dw 0x2bc0, 0xc99d, 0x2bff, 0xc99d, 0x21, 0 + .dw 0x2c40, 0xc99d, 0x2c7f, 0xc99d, 0x21, 0 + .dw 0x2cc0, 0xc99d, 0x2cff, 0xc99d, 0x21, 0 + .dw 0x2d40, 0xc99d, 0x2d7f, 0xc99d, 0x21, 0 + .dw 0x2dc0, 0xc99d, 0x2dff, 0xc99d, 0x21, 0 + .dw 0x2e40, 0xc99d, 0x2e7f, 0xc99d, 0x21, 0 + .dw 0x2ec0, 0xc99d, 0x2eff, 0xc99d, 0x21, 0 + .dw 0x2f40, 0xc99d, 0x2f7f, 0xc99d, 0x21, 0 + .dw 0x2fc0, 0xc99d, 0x2fff, 0xc99d, 0x21, 0 + .dw 0x3040, 0xc99d, 0x307f, 0xc99d, 0x21, 0 + .dw 0x30c0, 0xc99d, 0x30ff, 0xc99d, 0x21, 0 + .dw 0x3140, 0xc99d, 0x317f, 0xc99d, 0x21, 0 + .dw 0x31c0, 0xc99d, 0x31ff, 0xc99d, 0x21, 0 + .dw 0x3240, 0xc99d, 0x327f, 0xc99d, 0x21, 0 + .dw 0x32c0, 0xc99d, 0x32ff, 0xc99d, 0x21, 0 + .dw 0x3340, 0xc99d, 0x337f, 0xc99d, 0x21, 0 + .dw 0x33c0, 0xc99d, 0x33ff, 0xc99d, 0x21, 0 + .dw 0x3440, 0xc99d, 0x347f, 0xc99d, 0x21, 0 + .dw 0x34c0, 0xc99d, 0x34ff, 0xc99d, 0x21, 0 + .dw 0x3540, 0xc99d, 0x357f, 0xc99d, 0x21, 0 + .dw 0x35c0, 0xc99d, 0x35ff, 0xc99d, 0x21, 0 + .dw 0x3640, 0xc99d, 0x367f, 0xc99d, 0x21, 0 + .dw 0x36c0, 0xc99d, 0x36ff, 0xc99d, 0x21, 0 + .dw 0x3740, 0xc99d, 0x377f, 0xc99d, 0x21, 0 + .dw 0x37c0, 0xc99d, 0x37ff, 0xc99d, 0x21, 0 + .dw 0x3840, 0xc99d, 0x387f, 0xc99d, 0x21, 0 + .dw 0x38c0, 0xc99d, 0x38ff, 0xc99d, 0x21, 0 + .dw 0x3940, 0xc99d, 0x397f, 0xc99d, 0x21, 0 + .dw 0x39c0, 0xc99d, 0x3fff, 0xc99d, 0x21, 0 + .dw 0x4040, 0xc99d, 0x407f, 0xc99d, 0x21, 0 + .dw 0x40c0, 0xc99d, 0x40ff, 0xc99d, 0x21, 0 + .dw 0x4140, 0xc99d, 0x417f, 0xc99d, 0x21, 0 + .dw 0x41c0, 0xc99d, 0x41ff, 0xc99d, 0x21, 0 + .dw 0x4240, 0xc99d, 0x427f, 0xc99d, 0x21, 0 + .dw 0x42c0, 0xc99d, 0x42ff, 0xc99d, 0x21, 0 + .dw 0x4340, 0xc99d, 0x437f, 0xc99d, 0x21, 0 + .dw 0x43c0, 0xc99d, 0x43ff, 0xc99d, 0x21, 0 + .dw 0x4440, 0xc99d, 0x447f, 0xc99d, 0x21, 0 + .dw 0x44c0, 0xc99d, 0x44ff, 0xc99d, 0x21, 0 + .dw 0x4540, 0xc99d, 0x457f, 0xc99d, 0x21, 0 + .dw 0x45c0, 0xc99d, 0x45ff, 0xc99d, 0x21, 0 + .dw 0x4640, 0xc99d, 0x467f, 0xc99d, 0x21, 0 + .dw 0x46c0, 0xc99d, 0x46ff, 0xc99d, 0x21, 0 + .dw 0x4740, 0xc99d, 0x477f, 0xc99d, 0x21, 0 + .dw 0x47c0, 0xc99d, 0x47ff, 0xc99d, 0x21, 0 + .dw 0x4840, 0xc99d, 0x487f, 0xc99d, 0x21, 0 + .dw 0x48c0, 0xc99d, 0x48ff, 0xc99d, 0x21, 0 + .dw 0x4940, 0xc99d, 0x497f, 0xc99d, 0x21, 0 + .dw 0x49c0, 0xc99d, 0x49ff, 0xc99d, 0x21, 0 + .dw 0x4a40, 0xc99d, 0x4a7f, 0xc99d, 0x21, 0 + .dw 0x4ac0, 0xc99d, 0x4aff, 0xc99d, 0x21, 0 + .dw 0x4b40, 0xc99d, 0x4b7f, 0xc99d, 0x21, 0 + .dw 0x4bc0, 0xc99d, 0x4bff, 0xc99d, 0x21, 0 + .dw 0x4c40, 0xc99d, 0x4c7f, 0xc99d, 0x21, 0 + .dw 0x4cc0, 0xc99d, 0x4cff, 0xc99d, 0x21, 0 + .dw 0x4d40, 0xc99d, 0x4d7f, 0xc99d, 0x21, 0 + .dw 0x4dc0, 0xc99d, 0x4dff, 0xc99d, 0x21, 0 + .dw 0x4e40, 0xc99d, 0x4e7f, 0xc99d, 0x21, 0 + .dw 0x4ec0, 0xc99d, 0x4eff, 0xc99d, 0x21, 0 + .dw 0x4f40, 0xc99d, 0x4f7f, 0xc99d, 0x21, 0 + .dw 0x4fc0, 0xc99d, 0x4fff, 0xc99d, 0x21, 0 + .dw 0x5040, 0xc99d, 0x507f, 0xc99d, 0x21, 0 + .dw 0x50c0, 0xc99d, 0x50ff, 0xc99d, 0x21, 0 + .dw 0x5140, 0xc99d, 0x517f, 0xc99d, 0x21, 0 + .dw 0x51c0, 0xc99d, 0x51ff, 0xc99d, 0x21, 0 + .dw 0x5240, 0xc99d, 0x527f, 0xc99d, 0x21, 0 + .dw 0x52c0, 0xc99d, 0x52ff, 0xc99d, 0x21, 0 + .dw 0x5340, 0xc99d, 0x537f, 0xc99d, 0x21, 0 + .dw 0x53c0, 0xc99d, 0x53ff, 0xc99d, 0x21, 0 + .dw 0x5440, 0xc99d, 0x547f, 0xc99d, 0x21, 0 + .dw 0x54c0, 0xc99d, 0x54ff, 0xc99d, 0x21, 0 + .dw 0x5540, 0xc99d, 0x557f, 0xc99d, 0x21, 0 + .dw 0x55c0, 0xc99d, 0x55ff, 0xc99d, 0x21, 0 + .dw 0x5640, 0xc99d, 0x567f, 0xc99d, 0x21, 0 + .dw 0x56c0, 0xc99d, 0x56ff, 0xc99d, 0x21, 0 + .dw 0x5740, 0xc99d, 0x577f, 0xc99d, 0x21, 0 + .dw 0x57c0, 0xc99d, 0x57ff, 0xc99d, 0x21, 0 + .dw 0x5840, 0xc99d, 0x587f, 0xc99d, 0x21, 0 + .dw 0x58c0, 0xc99d, 0x58ff, 0xc99d, 0x21, 0 + .dw 0x5940, 0xc99d, 0x597f, 0xc99d, 0x21, 0 + .dw 0x59c0, 0xc99d, 0x5fff, 0xc99d, 0x21, 0 + .dw 0x6040, 0xc99d, 0x607f, 0xc99d, 0x21, 0 + .dw 0x60c0, 0xc99d, 0x60ff, 0xc99d, 0x21, 0 + .dw 0x6140, 0xc99d, 0x617f, 0xc99d, 0x21, 0 + .dw 0x61c0, 0xc99d, 0x61ff, 0xc99d, 0x21, 0 + .dw 0x6240, 0xc99d, 0x627f, 0xc99d, 0x21, 0 + .dw 0x62c0, 0xc99d, 0x62ff, 0xc99d, 0x21, 0 + .dw 0x6340, 0xc99d, 0x637f, 0xc99d, 0x21, 0 + .dw 0x63c0, 0xc99d, 0x63ff, 0xc99d, 0x21, 0 + .dw 0x6440, 0xc99d, 0x647f, 0xc99d, 0x21, 0 + .dw 0x64c0, 0xc99d, 0x64ff, 0xc99d, 0x21, 0 + .dw 0x6540, 0xc99d, 0x657f, 0xc99d, 0x21, 0 + .dw 0x65c0, 0xc99d, 0x65ff, 0xc99d, 0x21, 0 + .dw 0x6640, 0xc99d, 0x667f, 0xc99d, 0x21, 0 + .dw 0x66c0, 0xc99d, 0x66ff, 0xc99d, 0x21, 0 + .dw 0x6740, 0xc99d, 0x677f, 0xc99d, 0x21, 0 + .dw 0x67c0, 0xc99d, 0x67ff, 0xc99d, 0x21, 0 + .dw 0x6840, 0xc99d, 0x687f, 0xc99d, 0x21, 0 + .dw 0x68c0, 0xc99d, 0x68ff, 0xc99d, 0x21, 0 + .dw 0x6940, 0xc99d, 0x697f, 0xc99d, 0x21, 0 + .dw 0x69c0, 0xc99d, 0x69ff, 0xc99d, 0x21, 0 + .dw 0x6a40, 0xc99d, 0x6a7f, 0xc99d, 0x21, 0 + .dw 0x6ac0, 0xc99d, 0x6aff, 0xc99d, 0x21, 0 + .dw 0x6b40, 0xc99d, 0x6b7f, 0xc99d, 0x21, 0 + .dw 0x6bc0, 0xc99d, 0x6bff, 0xc99d, 0x21, 0 + .dw 0x6c40, 0xc99d, 0x6c7f, 0xc99d, 0x21, 0 + .dw 0x6cc0, 0xc99d, 0x6cff, 0xc99d, 0x21, 0 + .dw 0x6d40, 0xc99d, 0x6d7f, 0xc99d, 0x21, 0 + .dw 0x6dc0, 0xc99d, 0x6dff, 0xc99d, 0x21, 0 + .dw 0x6e40, 0xc99d, 0x6e7f, 0xc99d, 0x21, 0 + .dw 0x6ec0, 0xc99d, 0x6eff, 0xc99d, 0x21, 0 + .dw 0x6f40, 0xc99d, 0x6f7f, 0xc99d, 0x21, 0 + .dw 0x6fc0, 0xc99d, 0x6fff, 0xc99d, 0x21, 0 + .dw 0x7040, 0xc99d, 0x707f, 0xc99d, 0x21, 0 + .dw 0x70c0, 0xc99d, 0x70ff, 0xc99d, 0x21, 0 + .dw 0x7140, 0xc99d, 0x717f, 0xc99d, 0x21, 0 + .dw 0x71c0, 0xc99d, 0x71ff, 0xc99d, 0x21, 0 + .dw 0x7240, 0xc99d, 0x727f, 0xc99d, 0x21, 0 + .dw 0x72c0, 0xc99d, 0x72ff, 0xc99d, 0x21, 0 + .dw 0x7340, 0xc99d, 0x737f, 0xc99d, 0x21, 0 + .dw 0x73c0, 0xc99d, 0x73ff, 0xc99d, 0x21, 0 + .dw 0x7440, 0xc99d, 0x747f, 0xc99d, 0x21, 0 + .dw 0x74c0, 0xc99d, 0x74ff, 0xc99d, 0x21, 0 + .dw 0x7540, 0xc99d, 0x757f, 0xc99d, 0x21, 0 + .dw 0x75c0, 0xc99d, 0x75ff, 0xc99d, 0x21, 0 + .dw 0x7640, 0xc99d, 0x767f, 0xc99d, 0x21, 0 + .dw 0x76c0, 0xc99d, 0x76ff, 0xc99d, 0x21, 0 + .dw 0x7740, 0xc99d, 0x777f, 0xc99d, 0x21, 0 + .dw 0x77c0, 0xc99d, 0x77ff, 0xc99d, 0x21, 0 + .dw 0x7840, 0xc99d, 0x787f, 0xc99d, 0x21, 0 + .dw 0x78c0, 0xc99d, 0x78ff, 0xc99d, 0x21, 0 + .dw 0x7940, 0xc99d, 0x797f, 0xc99d, 0x21, 0 + .dw 0x79c0, 0xc99d, 0x7fff, 0xc99d, 0x21, 0 + .dw 0x8040, 0xc99d, 0x807f, 0xc99d, 0x21, 0 + .dw 0x80c0, 0xc99d, 0x80ff, 0xc99d, 0x21, 0 + .dw 0x8140, 0xc99d, 0x817f, 0xc99d, 0x21, 0 + .dw 0x81c0, 0xc99d, 0x81ff, 0xc99d, 0x21, 0 + .dw 0x8240, 0xc99d, 0x827f, 0xc99d, 0x21, 0 + .dw 0x82c0, 0xc99d, 0x82ff, 0xc99d, 0x21, 0 + .dw 0x8340, 0xc99d, 0x837f, 0xc99d, 0x21, 0 + .dw 0x83c0, 0xc99d, 0x83ff, 0xc99d, 0x21, 0 + .dw 0x8440, 0xc99d, 0x847f, 0xc99d, 0x21, 0 + .dw 0x84c0, 0xc99d, 0x84ff, 0xc99d, 0x21, 0 + .dw 0x8540, 0xc99d, 0x857f, 0xc99d, 0x21, 0 + .dw 0x85c0, 0xc99d, 0x85ff, 0xc99d, 0x21, 0 + .dw 0x8640, 0xc99d, 0x867f, 0xc99d, 0x21, 0 + .dw 0x86c0, 0xc99d, 0x86ff, 0xc99d, 0x21, 0 + .dw 0x8740, 0xc99d, 0x877f, 0xc99d, 0x21, 0 + .dw 0x87c0, 0xc99d, 0x87ff, 0xc99d, 0x21, 0 + .dw 0x8840, 0xc99d, 0x887f, 0xc99d, 0x21, 0 + .dw 0x88c0, 0xc99d, 0x88ff, 0xc99d, 0x21, 0 + .dw 0x8940, 0xc99d, 0x897f, 0xc99d, 0x21, 0 + .dw 0x89c0, 0xc99d, 0x89ff, 0xc99d, 0x21, 0 + .dw 0x8a40, 0xc99d, 0x8a7f, 0xc99d, 0x21, 0 + .dw 0x8ac0, 0xc99d, 0x8aff, 0xc99d, 0x21, 0 + .dw 0x8b40, 0xc99d, 0x8b7f, 0xc99d, 0x21, 0 + .dw 0x8bc0, 0xc99d, 0x8bff, 0xc99d, 0x21, 0 + .dw 0x8c40, 0xc99d, 0x8c7f, 0xc99d, 0x21, 0 + .dw 0x8cc0, 0xc99d, 0x8cff, 0xc99d, 0x21, 0 + .dw 0x8d40, 0xc99d, 0x8d7f, 0xc99d, 0x21, 0 + .dw 0x8dc0, 0xc99d, 0x8dff, 0xc99d, 0x21, 0 + .dw 0x8e40, 0xc99d, 0x8e7f, 0xc99d, 0x21, 0 + .dw 0x8ec0, 0xc99d, 0x8eff, 0xc99d, 0x21, 0 + .dw 0x8f40, 0xc99d, 0x8f7f, 0xc99d, 0x21, 0 + .dw 0x8fc0, 0xc99d, 0x8fff, 0xc99d, 0x21, 0 + .dw 0x9040, 0xc99d, 0x907f, 0xc99d, 0x21, 0 + .dw 0x90c0, 0xc99d, 0x90ff, 0xc99d, 0x21, 0 + .dw 0x9140, 0xc99d, 0x917f, 0xc99d, 0x21, 0 + .dw 0x91c0, 0xc99d, 0x91ff, 0xc99d, 0x21, 0 + .dw 0x9240, 0xc99d, 0x927f, 0xc99d, 0x21, 0 + .dw 0x92c0, 0xc99d, 0x92ff, 0xc99d, 0x21, 0 + .dw 0x9340, 0xc99d, 0x937f, 0xc99d, 0x21, 0 + .dw 0x93c0, 0xc99d, 0x93ff, 0xc99d, 0x21, 0 + .dw 0x9440, 0xc99d, 0x947f, 0xc99d, 0x21, 0 + .dw 0x94c0, 0xc99d, 0x94ff, 0xc99d, 0x21, 0 + .dw 0x9540, 0xc99d, 0x957f, 0xc99d, 0x21, 0 + .dw 0x95c0, 0xc99d, 0x95ff, 0xc99d, 0x21, 0 + .dw 0x9640, 0xc99d, 0x967f, 0xc99d, 0x21, 0 + .dw 0x96c0, 0xc99d, 0x96ff, 0xc99d, 0x21, 0 + .dw 0x9740, 0xc99d, 0x977f, 0xc99d, 0x21, 0 + .dw 0x97c0, 0xc99d, 0x97ff, 0xc99d, 0x21, 0 + .dw 0x9840, 0xc99d, 0x987f, 0xc99d, 0x21, 0 + .dw 0x98c0, 0xc99d, 0x98ff, 0xc99d, 0x21, 0 + .dw 0x9940, 0xc99d, 0x997f, 0xc99d, 0x21, 0 + .dw 0x99c0, 0xc99d, 0x9fff, 0xc99d, 0x21, 0 + .dw 0xa040, 0xc99d, 0xa07f, 0xc99d, 0x21, 0 + .dw 0xa0c0, 0xc99d, 0xa0ff, 0xc99d, 0x21, 0 + .dw 0xa140, 0xc99d, 0xa17f, 0xc99d, 0x21, 0 + .dw 0xa1c0, 0xc99d, 0xa1ff, 0xc99d, 0x21, 0 + .dw 0xa240, 0xc99d, 0xa27f, 0xc99d, 0x21, 0 + .dw 0xa2c0, 0xc99d, 0xa2ff, 0xc99d, 0x21, 0 + .dw 0xa340, 0xc99d, 0xa37f, 0xc99d, 0x21, 0 + .dw 0xa3c0, 0xc99d, 0xa3ff, 0xc99d, 0x21, 0 + .dw 0xa440, 0xc99d, 0xa47f, 0xc99d, 0x21, 0 + .dw 0xa4c0, 0xc99d, 0xa4ff, 0xc99d, 0x21, 0 + .dw 0xa540, 0xc99d, 0xa57f, 0xc99d, 0x21, 0 + .dw 0xa5c0, 0xc99d, 0xa5ff, 0xc99d, 0x21, 0 + .dw 0xa640, 0xc99d, 0xa67f, 0xc99d, 0x21, 0 + .dw 0xa6c0, 0xc99d, 0xa6ff, 0xc99d, 0x21, 0 + .dw 0xa740, 0xc99d, 0xa77f, 0xc99d, 0x21, 0 + .dw 0xa7c0, 0xc99d, 0xa7ff, 0xc99d, 0x21, 0 + .dw 0xa840, 0xc99d, 0xa87f, 0xc99d, 0x21, 0 + .dw 0xa8c0, 0xc99d, 0xa8ff, 0xc99d, 0x21, 0 + .dw 0xa940, 0xc99d, 0xa97f, 0xc99d, 0x21, 0 + .dw 0xa9c0, 0xc99d, 0xa9ff, 0xc99d, 0x21, 0 + .dw 0xaa40, 0xc99d, 0xaa7f, 0xc99d, 0x21, 0 + .dw 0xaac0, 0xc99d, 0xaaff, 0xc99d, 0x21, 0 + .dw 0xab40, 0xc99d, 0xab7f, 0xc99d, 0x21, 0 + .dw 0xabc0, 0xc99d, 0xabff, 0xc99d, 0x21, 0 + .dw 0xac40, 0xc99d, 0xac7f, 0xc99d, 0x21, 0 + .dw 0xacc0, 0xc99d, 0xacff, 0xc99d, 0x21, 0 + .dw 0xad40, 0xc99d, 0xad7f, 0xc99d, 0x21, 0 + .dw 0xadc0, 0xc99d, 0xadff, 0xc99d, 0x21, 0 + .dw 0xae40, 0xc99d, 0xae7f, 0xc99d, 0x21, 0 + .dw 0xaec0, 0xc99d, 0xaeff, 0xc99d, 0x21, 0 + .dw 0xaf40, 0xc99d, 0xaf7f, 0xc99d, 0x21, 0 + .dw 0xafc0, 0xc99d, 0xafff, 0xc99d, 0x21, 0 + .dw 0xb040, 0xc99d, 0xb07f, 0xc99d, 0x21, 0 + .dw 0xb0c0, 0xc99d, 0xb0ff, 0xc99d, 0x21, 0 + .dw 0xb140, 0xc99d, 0xb17f, 0xc99d, 0x21, 0 + .dw 0xb1c0, 0xc99d, 0xb1ff, 0xc99d, 0x21, 0 + .dw 0xb240, 0xc99d, 0xb27f, 0xc99d, 0x21, 0 + .dw 0xb2c0, 0xc99d, 0xb2ff, 0xc99d, 0x21, 0 + .dw 0xb340, 0xc99d, 0xb37f, 0xc99d, 0x21, 0 + .dw 0xb3c0, 0xc99d, 0xb3ff, 0xc99d, 0x21, 0 + .dw 0xb440, 0xc99d, 0xb47f, 0xc99d, 0x21, 0 + .dw 0xb4c0, 0xc99d, 0xb4ff, 0xc99d, 0x21, 0 + .dw 0xb540, 0xc99d, 0xb57f, 0xc99d, 0x21, 0 + .dw 0xb5c0, 0xc99d, 0xb5ff, 0xc99d, 0x21, 0 + .dw 0xb640, 0xc99d, 0xb67f, 0xc99d, 0x21, 0 + .dw 0xb6c0, 0xc99d, 0xb6ff, 0xc99d, 0x21, 0 + .dw 0xb740, 0xc99d, 0xb77f, 0xc99d, 0x21, 0 + .dw 0xb7c0, 0xc99d, 0xb7ff, 0xc99d, 0x21, 0 + .dw 0xb840, 0xc99d, 0xb87f, 0xc99d, 0x21, 0 + .dw 0xb8c0, 0xc99d, 0xb8ff, 0xc99d, 0x21, 0 + .dw 0xb940, 0xc99d, 0xb97f, 0xc99d, 0x21, 0 + .dw 0xb9c0, 0xc99d, 0xbfff, 0xc99d, 0x21, 0 + .dw 0xc040, 0xc99d, 0xc07f, 0xc99d, 0x21, 0 + .dw 0xc0c0, 0xc99d, 0xc0ff, 0xc99d, 0x21, 0 + .dw 0xc140, 0xc99d, 0xc17f, 0xc99d, 0x21, 0 + .dw 0xc1c0, 0xc99d, 0xc1ff, 0xc99d, 0x21, 0 + .dw 0xc240, 0xc99d, 0xc27f, 0xc99d, 0x21, 0 + .dw 0xc2c0, 0xc99d, 0xc2ff, 0xc99d, 0x21, 0 + .dw 0xc340, 0xc99d, 0xc37f, 0xc99d, 0x21, 0 + .dw 0xc3c0, 0xc99d, 0xc3ff, 0xc99d, 0x21, 0 + .dw 0xc440, 0xc99d, 0xc47f, 0xc99d, 0x21, 0 + .dw 0xc4c0, 0xc99d, 0xc4ff, 0xc99d, 0x21, 0 + .dw 0xc540, 0xc99d, 0xc57f, 0xc99d, 0x21, 0 + .dw 0xc5c0, 0xc99d, 0xc5ff, 0xc99d, 0x21, 0 + .dw 0xc640, 0xc99d, 0xc67f, 0xc99d, 0x21, 0 + .dw 0xc6c0, 0xc99d, 0xc6ff, 0xc99d, 0x21, 0 + .dw 0xc740, 0xc99d, 0xc77f, 0xc99d, 0x21, 0 + .dw 0xc7c0, 0xc99d, 0xc7ff, 0xc99d, 0x21, 0 + .dw 0xc840, 0xc99d, 0xc87f, 0xc99d, 0x21, 0 + .dw 0xc8c0, 0xc99d, 0xc8ff, 0xc99d, 0x21, 0 + .dw 0xc940, 0xc99d, 0xc97f, 0xc99d, 0x21, 0 + .dw 0xc9c0, 0xc99d, 0xc9ff, 0xc99d, 0x21, 0 + .dw 0xca40, 0xc99d, 0xca7f, 0xc99d, 0x21, 0 + .dw 0xcac0, 0xc99d, 0xcaff, 0xc99d, 0x21, 0 + .dw 0xcb40, 0xc99d, 0xcb7f, 0xc99d, 0x21, 0 + .dw 0xcbc0, 0xc99d, 0xcbff, 0xc99d, 0x21, 0 + .dw 0xcc40, 0xc99d, 0xcc7f, 0xc99d, 0x21, 0 + .dw 0xccc0, 0xc99d, 0xccff, 0xc99d, 0x21, 0 + .dw 0xcd40, 0xc99d, 0xcd7f, 0xc99d, 0x21, 0 + .dw 0xcdc0, 0xc99d, 0xcdff, 0xc99d, 0x21, 0 + .dw 0xce40, 0xc99d, 0xce7f, 0xc99d, 0x21, 0 + .dw 0xcec0, 0xc99d, 0xceff, 0xc99d, 0x21, 0 + .dw 0xcf40, 0xc99d, 0xcf7f, 0xc99d, 0x21, 0 + .dw 0xcfc0, 0xc99d, 0xcfff, 0xc99d, 0x21, 0 + .dw 0xd040, 0xc99d, 0xd07f, 0xc99d, 0x21, 0 + .dw 0xd0c0, 0xc99d, 0xd0ff, 0xc99d, 0x21, 0 + .dw 0xd140, 0xc99d, 0xd17f, 0xc99d, 0x21, 0 + .dw 0xd1c0, 0xc99d, 0xd1ff, 0xc99d, 0x21, 0 + .dw 0xd240, 0xc99d, 0xd27f, 0xc99d, 0x21, 0 + .dw 0xd2c0, 0xc99d, 0xd2ff, 0xc99d, 0x21, 0 + .dw 0xd340, 0xc99d, 0xd37f, 0xc99d, 0x21, 0 + .dw 0xd3c0, 0xc99d, 0xd3ff, 0xc99d, 0x21, 0 + .dw 0xd440, 0xc99d, 0xd47f, 0xc99d, 0x21, 0 + .dw 0xd4c0, 0xc99d, 0xd4ff, 0xc99d, 0x21, 0 + .dw 0xd540, 0xc99d, 0xd57f, 0xc99d, 0x21, 0 + .dw 0xd5c0, 0xc99d, 0xd5ff, 0xc99d, 0x21, 0 + .dw 0xd640, 0xc99d, 0xd67f, 0xc99d, 0x21, 0 + .dw 0xd6c0, 0xc99d, 0xd6ff, 0xc99d, 0x21, 0 + .dw 0xd740, 0xc99d, 0xd77f, 0xc99d, 0x21, 0 + .dw 0xd7c0, 0xc99d, 0xd7ff, 0xc99d, 0x21, 0 + .dw 0xd840, 0xc99d, 0xd87f, 0xc99d, 0x21, 0 + .dw 0xd8c0, 0xc99d, 0xd8ff, 0xc99d, 0x21, 0 + .dw 0xd940, 0xc99d, 0xd97f, 0xc99d, 0x21, 0 + .dw 0xd9c0, 0xc99d, 0xdfff, 0xc99d, 0x21, 0 + .dw 0xe040, 0xc99d, 0xe07f, 0xc99d, 0x21, 0 + .dw 0xe0c0, 0xc99d, 0xe0ff, 0xc99d, 0x21, 0 + .dw 0xe140, 0xc99d, 0xe17f, 0xc99d, 0x21, 0 + .dw 0xe1c0, 0xc99d, 0xe1ff, 0xc99d, 0x21, 0 + .dw 0xe240, 0xc99d, 0xe27f, 0xc99d, 0x21, 0 + .dw 0xe2c0, 0xc99d, 0xe2ff, 0xc99d, 0x21, 0 + .dw 0xe340, 0xc99d, 0xe37f, 0xc99d, 0x21, 0 + .dw 0xe3c0, 0xc99d, 0xe3ff, 0xc99d, 0x21, 0 + .dw 0xe440, 0xc99d, 0xe47f, 0xc99d, 0x21, 0 + .dw 0xe4c0, 0xc99d, 0xe4ff, 0xc99d, 0x21, 0 + .dw 0xe540, 0xc99d, 0xe57f, 0xc99d, 0x21, 0 + .dw 0xe5c0, 0xc99d, 0xe5ff, 0xc99d, 0x21, 0 + .dw 0xe640, 0xc99d, 0xe67f, 0xc99d, 0x21, 0 + .dw 0xe6c0, 0xc99d, 0xe6ff, 0xc99d, 0x21, 0 + .dw 0xe740, 0xc99d, 0xe77f, 0xc99d, 0x21, 0 + .dw 0xe7c0, 0xc99d, 0xe7ff, 0xc99d, 0x21, 0 + .dw 0xe840, 0xc99d, 0xe87f, 0xc99d, 0x21, 0 + .dw 0xe8c0, 0xc99d, 0xe8ff, 0xc99d, 0x21, 0 + .dw 0xe940, 0xc99d, 0xe97f, 0xc99d, 0x21, 0 + .dw 0xe9c0, 0xc99d, 0xe9ff, 0xc99d, 0x21, 0 + .dw 0xea40, 0xc99d, 0xea7f, 0xc99d, 0x21, 0 + .dw 0xeac0, 0xc99d, 0xeaff, 0xc99d, 0x21, 0 + .dw 0xeb40, 0xc99d, 0xeb7f, 0xc99d, 0x21, 0 + .dw 0xebc0, 0xc99d, 0xebff, 0xc99d, 0x21, 0 + .dw 0xec40, 0xc99d, 0xec7f, 0xc99d, 0x21, 0 + .dw 0xecc0, 0xc99d, 0xecff, 0xc99d, 0x21, 0 + .dw 0xed40, 0xc99d, 0xed7f, 0xc99d, 0x21, 0 + .dw 0xedc0, 0xc99d, 0xedff, 0xc99d, 0x21, 0 + .dw 0xee40, 0xc99d, 0xee7f, 0xc99d, 0x21, 0 + .dw 0xeec0, 0xc99d, 0xeeff, 0xc99d, 0x21, 0 + .dw 0xef40, 0xc99d, 0xef7f, 0xc99d, 0x21, 0 + .dw 0xefc0, 0xc99d, 0xefff, 0xc99d, 0x21, 0 + .dw 0xf040, 0xc99d, 0xf07f, 0xc99d, 0x21, 0 + .dw 0xf0c0, 0xc99d, 0xf0ff, 0xc99d, 0x21, 0 + .dw 0xf140, 0xc99d, 0xf17f, 0xc99d, 0x21, 0 + .dw 0xf1c0, 0xc99d, 0xf1ff, 0xc99d, 0x21, 0 + .dw 0xf240, 0xc99d, 0xf27f, 0xc99d, 0x21, 0 + .dw 0xf2c0, 0xc99d, 0xf2ff, 0xc99d, 0x21, 0 + .dw 0xf340, 0xc99d, 0xf37f, 0xc99d, 0x21, 0 + .dw 0xf3c0, 0xc99d, 0xf3ff, 0xc99d, 0x21, 0 + .dw 0xf440, 0xc99d, 0xf47f, 0xc99d, 0x21, 0 + .dw 0xf4c0, 0xc99d, 0xf4ff, 0xc99d, 0x21, 0 + .dw 0xf540, 0xc99d, 0xf57f, 0xc99d, 0x21, 0 + .dw 0xf5c0, 0xc99d, 0xf5ff, 0xc99d, 0x21, 0 + .dw 0xf640, 0xc99d, 0xf67f, 0xc99d, 0x21, 0 + .dw 0xf6c0, 0xc99d, 0xf6ff, 0xc99d, 0x21, 0 + .dw 0xf740, 0xc99d, 0xf77f, 0xc99d, 0x21, 0 + .dw 0xf7c0, 0xc99d, 0xf7ff, 0xc99d, 0x21, 0 + .dw 0xf840, 0xc99d, 0xf87f, 0xc99d, 0x21, 0 + .dw 0xf8c0, 0xc99d, 0xf8ff, 0xc99d, 0x21, 0 + .dw 0xf940, 0xc99d, 0xf97f, 0xc99d, 0x21, 0 + .dw 0xf9c0, 0xc99d, 0xffff, 0xc99d, 0x21, 0 + .dw 0x0040, 0xc99e, 0x007f, 0xc99e, 0x21, 0 + .dw 0x00c0, 0xc99e, 0x00ff, 0xc99e, 0x21, 0 + .dw 0x0140, 0xc99e, 0x017f, 0xc99e, 0x21, 0 + .dw 0x01c0, 0xc99e, 0x01ff, 0xc99e, 0x21, 0 + .dw 0x0240, 0xc99e, 0x027f, 0xc99e, 0x21, 0 + .dw 0x02c0, 0xc99e, 0x02ff, 0xc99e, 0x21, 0 + .dw 0x0340, 0xc99e, 0x037f, 0xc99e, 0x21, 0 + .dw 0x03c0, 0xc99e, 0x03ff, 0xc99e, 0x21, 0 + .dw 0x0440, 0xc99e, 0x047f, 0xc99e, 0x21, 0 + .dw 0x04c0, 0xc99e, 0x04ff, 0xc99e, 0x21, 0 + .dw 0x0540, 0xc99e, 0x057f, 0xc99e, 0x21, 0 + .dw 0x05c0, 0xc99e, 0x05ff, 0xc99e, 0x21, 0 + .dw 0x0640, 0xc99e, 0x067f, 0xc99e, 0x21, 0 + .dw 0x06c0, 0xc99e, 0x06ff, 0xc99e, 0x21, 0 + .dw 0x0740, 0xc99e, 0x077f, 0xc99e, 0x21, 0 + .dw 0x07c0, 0xc99e, 0x07ff, 0xc99e, 0x21, 0 + .dw 0x0840, 0xc99e, 0x087f, 0xc99e, 0x21, 0 + .dw 0x08c0, 0xc99e, 0x08ff, 0xc99e, 0x21, 0 + .dw 0x0940, 0xc99e, 0x097f, 0xc99e, 0x21, 0 + .dw 0x09c0, 0xc99e, 0x09ff, 0xc99e, 0x21, 0 + .dw 0x0a40, 0xc99e, 0x0a7f, 0xc99e, 0x21, 0 + .dw 0x0ac0, 0xc99e, 0x0aff, 0xc99e, 0x21, 0 + .dw 0x0b40, 0xc99e, 0x0b7f, 0xc99e, 0x21, 0 + .dw 0x0bc0, 0xc99e, 0x0bff, 0xc99e, 0x21, 0 + .dw 0x0c40, 0xc99e, 0x0c7f, 0xc99e, 0x21, 0 + .dw 0x0cc0, 0xc99e, 0x0cff, 0xc99e, 0x21, 0 + .dw 0x0d40, 0xc99e, 0x0d7f, 0xc99e, 0x21, 0 + .dw 0x0dc0, 0xc99e, 0x0dff, 0xc99e, 0x21, 0 + .dw 0x0e40, 0xc99e, 0x0e7f, 0xc99e, 0x21, 0 + .dw 0x0ec0, 0xc99e, 0x0eff, 0xc99e, 0x21, 0 + .dw 0x0f40, 0xc99e, 0x0f7f, 0xc99e, 0x21, 0 + .dw 0x0fc0, 0xc99e, 0x0fff, 0xc99e, 0x21, 0 + .dw 0x1040, 0xc99e, 0x107f, 0xc99e, 0x21, 0 + .dw 0x10c0, 0xc99e, 0x10ff, 0xc99e, 0x21, 0 + .dw 0x1140, 0xc99e, 0x117f, 0xc99e, 0x21, 0 + .dw 0x11c0, 0xc99e, 0x11ff, 0xc99e, 0x21, 0 + .dw 0x1240, 0xc99e, 0x127f, 0xc99e, 0x21, 0 + .dw 0x12c0, 0xc99e, 0x12ff, 0xc99e, 0x21, 0 + .dw 0x1340, 0xc99e, 0x137f, 0xc99e, 0x21, 0 + .dw 0x13c0, 0xc99e, 0x13ff, 0xc99e, 0x21, 0 + .dw 0x1440, 0xc99e, 0x147f, 0xc99e, 0x21, 0 + .dw 0x14c0, 0xc99e, 0x14ff, 0xc99e, 0x21, 0 + .dw 0x1540, 0xc99e, 0x157f, 0xc99e, 0x21, 0 + .dw 0x15c0, 0xc99e, 0x15ff, 0xc99e, 0x21, 0 + .dw 0x1640, 0xc99e, 0x167f, 0xc99e, 0x21, 0 + .dw 0x16c0, 0xc99e, 0x16ff, 0xc99e, 0x21, 0 + .dw 0x1740, 0xc99e, 0x177f, 0xc99e, 0x21, 0 + .dw 0x17c0, 0xc99e, 0x17ff, 0xc99e, 0x21, 0 + .dw 0x1840, 0xc99e, 0x187f, 0xc99e, 0x21, 0 + .dw 0x18c0, 0xc99e, 0x18ff, 0xc99e, 0x21, 0 + .dw 0x1940, 0xc99e, 0x197f, 0xc99e, 0x21, 0 + .dw 0x19c0, 0xc99e, 0x1fff, 0xc99e, 0x21, 0 + .dw 0x2040, 0xc99e, 0x207f, 0xc99e, 0x21, 0 + .dw 0x20c0, 0xc99e, 0x20ff, 0xc99e, 0x21, 0 + .dw 0x2140, 0xc99e, 0x217f, 0xc99e, 0x21, 0 + .dw 0x21c0, 0xc99e, 0x21ff, 0xc99e, 0x21, 0 + .dw 0x2240, 0xc99e, 0x227f, 0xc99e, 0x21, 0 + .dw 0x22c0, 0xc99e, 0x22ff, 0xc99e, 0x21, 0 + .dw 0x2340, 0xc99e, 0x237f, 0xc99e, 0x21, 0 + .dw 0x23c0, 0xc99e, 0x23ff, 0xc99e, 0x21, 0 + .dw 0x2440, 0xc99e, 0x247f, 0xc99e, 0x21, 0 + .dw 0x24c0, 0xc99e, 0x24ff, 0xc99e, 0x21, 0 + .dw 0x2540, 0xc99e, 0x257f, 0xc99e, 0x21, 0 + .dw 0x25c0, 0xc99e, 0x25ff, 0xc99e, 0x21, 0 + .dw 0x2640, 0xc99e, 0x267f, 0xc99e, 0x21, 0 + .dw 0x26c0, 0xc99e, 0x26ff, 0xc99e, 0x21, 0 + .dw 0x2740, 0xc99e, 0x277f, 0xc99e, 0x21, 0 + .dw 0x27c0, 0xc99e, 0x27ff, 0xc99e, 0x21, 0 + .dw 0x2840, 0xc99e, 0x287f, 0xc99e, 0x21, 0 + .dw 0x28c0, 0xc99e, 0x28ff, 0xc99e, 0x21, 0 + .dw 0x2940, 0xc99e, 0x297f, 0xc99e, 0x21, 0 + .dw 0x29c0, 0xc99e, 0x29ff, 0xc99e, 0x21, 0 + .dw 0x2a40, 0xc99e, 0x2a7f, 0xc99e, 0x21, 0 + .dw 0x2ac0, 0xc99e, 0x2aff, 0xc99e, 0x21, 0 + .dw 0x2b40, 0xc99e, 0x2b7f, 0xc99e, 0x21, 0 + .dw 0x2bc0, 0xc99e, 0x2bff, 0xc99e, 0x21, 0 + .dw 0x2c40, 0xc99e, 0x2c7f, 0xc99e, 0x21, 0 + .dw 0x2cc0, 0xc99e, 0x2cff, 0xc99e, 0x21, 0 + .dw 0x2d40, 0xc99e, 0x2d7f, 0xc99e, 0x21, 0 + .dw 0x2dc0, 0xc99e, 0x2dff, 0xc99e, 0x21, 0 + .dw 0x2e40, 0xc99e, 0x2e7f, 0xc99e, 0x21, 0 + .dw 0x2ec0, 0xc99e, 0x2eff, 0xc99e, 0x21, 0 + .dw 0x2f40, 0xc99e, 0x2f7f, 0xc99e, 0x21, 0 + .dw 0x2fc0, 0xc99e, 0x2fff, 0xc99e, 0x21, 0 + .dw 0x3040, 0xc99e, 0x307f, 0xc99e, 0x21, 0 + .dw 0x30c0, 0xc99e, 0x30ff, 0xc99e, 0x21, 0 + .dw 0x3140, 0xc99e, 0x317f, 0xc99e, 0x21, 0 + .dw 0x31c0, 0xc99e, 0x31ff, 0xc99e, 0x21, 0 + .dw 0x3240, 0xc99e, 0x327f, 0xc99e, 0x21, 0 + .dw 0x32c0, 0xc99e, 0x32ff, 0xc99e, 0x21, 0 + .dw 0x3340, 0xc99e, 0x337f, 0xc99e, 0x21, 0 + .dw 0x33c0, 0xc99e, 0x33ff, 0xc99e, 0x21, 0 + .dw 0x3440, 0xc99e, 0x347f, 0xc99e, 0x21, 0 + .dw 0x34c0, 0xc99e, 0x34ff, 0xc99e, 0x21, 0 + .dw 0x3540, 0xc99e, 0x357f, 0xc99e, 0x21, 0 + .dw 0x35c0, 0xc99e, 0x35ff, 0xc99e, 0x21, 0 + .dw 0x3640, 0xc99e, 0x367f, 0xc99e, 0x21, 0 + .dw 0x36c0, 0xc99e, 0x36ff, 0xc99e, 0x21, 0 + .dw 0x3740, 0xc99e, 0x377f, 0xc99e, 0x21, 0 + .dw 0x37c0, 0xc99e, 0x37ff, 0xc99e, 0x21, 0 + .dw 0x3840, 0xc99e, 0x387f, 0xc99e, 0x21, 0 + .dw 0x38c0, 0xc99e, 0x38ff, 0xc99e, 0x21, 0 + .dw 0x3940, 0xc99e, 0x397f, 0xc99e, 0x21, 0 + .dw 0x39c0, 0xc99e, 0x3fff, 0xc99e, 0x21, 0 + .dw 0x4040, 0xc99e, 0x407f, 0xc99e, 0x21, 0 + .dw 0x40c0, 0xc99e, 0x40ff, 0xc99e, 0x21, 0 + .dw 0x4140, 0xc99e, 0x417f, 0xc99e, 0x21, 0 + .dw 0x41c0, 0xc99e, 0x41ff, 0xc99e, 0x21, 0 + .dw 0x4240, 0xc99e, 0x427f, 0xc99e, 0x21, 0 + .dw 0x42c0, 0xc99e, 0x42ff, 0xc99e, 0x21, 0 + .dw 0x4340, 0xc99e, 0x437f, 0xc99e, 0x21, 0 + .dw 0x43c0, 0xc99e, 0x43ff, 0xc99e, 0x21, 0 + .dw 0x4440, 0xc99e, 0x447f, 0xc99e, 0x21, 0 + .dw 0x44c0, 0xc99e, 0x44ff, 0xc99e, 0x21, 0 + .dw 0x4540, 0xc99e, 0x457f, 0xc99e, 0x21, 0 + .dw 0x45c0, 0xc99e, 0x45ff, 0xc99e, 0x21, 0 + .dw 0x4640, 0xc99e, 0x467f, 0xc99e, 0x21, 0 + .dw 0x46c0, 0xc99e, 0x46ff, 0xc99e, 0x21, 0 + .dw 0x4740, 0xc99e, 0x477f, 0xc99e, 0x21, 0 + .dw 0x47c0, 0xc99e, 0x47ff, 0xc99e, 0x21, 0 + .dw 0x4840, 0xc99e, 0x487f, 0xc99e, 0x21, 0 + .dw 0x48c0, 0xc99e, 0x48ff, 0xc99e, 0x21, 0 + .dw 0x4940, 0xc99e, 0x497f, 0xc99e, 0x21, 0 + .dw 0x49c0, 0xc99e, 0x49ff, 0xc99e, 0x21, 0 + .dw 0x4a40, 0xc99e, 0x4a7f, 0xc99e, 0x21, 0 + .dw 0x4ac0, 0xc99e, 0x4aff, 0xc99e, 0x21, 0 + .dw 0x4b40, 0xc99e, 0x4b7f, 0xc99e, 0x21, 0 + .dw 0x4bc0, 0xc99e, 0x4bff, 0xc99e, 0x21, 0 + .dw 0x4c40, 0xc99e, 0x4c7f, 0xc99e, 0x21, 0 + .dw 0x4cc0, 0xc99e, 0x4cff, 0xc99e, 0x21, 0 + .dw 0x4d40, 0xc99e, 0x4d7f, 0xc99e, 0x21, 0 + .dw 0x4dc0, 0xc99e, 0x4dff, 0xc99e, 0x21, 0 + .dw 0x4e40, 0xc99e, 0x4e7f, 0xc99e, 0x21, 0 + .dw 0x4ec0, 0xc99e, 0x4eff, 0xc99e, 0x21, 0 + .dw 0x4f40, 0xc99e, 0x4f7f, 0xc99e, 0x21, 0 + .dw 0x4fc0, 0xc99e, 0x4fff, 0xc99e, 0x21, 0 + .dw 0x5040, 0xc99e, 0x507f, 0xc99e, 0x21, 0 + .dw 0x50c0, 0xc99e, 0x50ff, 0xc99e, 0x21, 0 + .dw 0x5140, 0xc99e, 0x517f, 0xc99e, 0x21, 0 + .dw 0x51c0, 0xc99e, 0x51ff, 0xc99e, 0x21, 0 + .dw 0x5240, 0xc99e, 0x527f, 0xc99e, 0x21, 0 + .dw 0x52c0, 0xc99e, 0x52ff, 0xc99e, 0x21, 0 + .dw 0x5340, 0xc99e, 0x537f, 0xc99e, 0x21, 0 + .dw 0x53c0, 0xc99e, 0x53ff, 0xc99e, 0x21, 0 + .dw 0x5440, 0xc99e, 0x547f, 0xc99e, 0x21, 0 + .dw 0x54c0, 0xc99e, 0x54ff, 0xc99e, 0x21, 0 + .dw 0x5540, 0xc99e, 0x557f, 0xc99e, 0x21, 0 + .dw 0x55c0, 0xc99e, 0x55ff, 0xc99e, 0x21, 0 + .dw 0x5640, 0xc99e, 0x567f, 0xc99e, 0x21, 0 + .dw 0x56c0, 0xc99e, 0x56ff, 0xc99e, 0x21, 0 + .dw 0x5740, 0xc99e, 0x577f, 0xc99e, 0x21, 0 + .dw 0x57c0, 0xc99e, 0x57ff, 0xc99e, 0x21, 0 + .dw 0x5840, 0xc99e, 0x587f, 0xc99e, 0x21, 0 + .dw 0x58c0, 0xc99e, 0x58ff, 0xc99e, 0x21, 0 + .dw 0x5940, 0xc99e, 0x597f, 0xc99e, 0x21, 0 + .dw 0x59c0, 0xc99e, 0x5fff, 0xc99e, 0x21, 0 + .dw 0x6040, 0xc99e, 0x607f, 0xc99e, 0x21, 0 + .dw 0x60c0, 0xc99e, 0x60ff, 0xc99e, 0x21, 0 + .dw 0x6140, 0xc99e, 0x617f, 0xc99e, 0x21, 0 + .dw 0x61c0, 0xc99e, 0x61ff, 0xc99e, 0x21, 0 + .dw 0x6240, 0xc99e, 0x627f, 0xc99e, 0x21, 0 + .dw 0x62c0, 0xc99e, 0x62ff, 0xc99e, 0x21, 0 + .dw 0x6340, 0xc99e, 0x637f, 0xc99e, 0x21, 0 + .dw 0x63c0, 0xc99e, 0x63ff, 0xc99e, 0x21, 0 + .dw 0x6440, 0xc99e, 0x647f, 0xc99e, 0x21, 0 + .dw 0x64c0, 0xc99e, 0x64ff, 0xc99e, 0x21, 0 + .dw 0x6540, 0xc99e, 0x657f, 0xc99e, 0x21, 0 + .dw 0x65c0, 0xc99e, 0x65ff, 0xc99e, 0x21, 0 + .dw 0x6640, 0xc99e, 0x667f, 0xc99e, 0x21, 0 + .dw 0x66c0, 0xc99e, 0x66ff, 0xc99e, 0x21, 0 + .dw 0x6740, 0xc99e, 0x677f, 0xc99e, 0x21, 0 + .dw 0x67c0, 0xc99e, 0x67ff, 0xc99e, 0x21, 0 + .dw 0x6840, 0xc99e, 0x687f, 0xc99e, 0x21, 0 + .dw 0x68c0, 0xc99e, 0x68ff, 0xc99e, 0x21, 0 + .dw 0x6940, 0xc99e, 0x697f, 0xc99e, 0x21, 0 + .dw 0x69c0, 0xc99e, 0x69ff, 0xc99e, 0x21, 0 + .dw 0x6a40, 0xc99e, 0x6a7f, 0xc99e, 0x21, 0 + .dw 0x6ac0, 0xc99e, 0x6aff, 0xc99e, 0x21, 0 + .dw 0x6b40, 0xc99e, 0x6b7f, 0xc99e, 0x21, 0 + .dw 0x6bc0, 0xc99e, 0x6bff, 0xc99e, 0x21, 0 + .dw 0x6c40, 0xc99e, 0x6c7f, 0xc99e, 0x21, 0 + .dw 0x6cc0, 0xc99e, 0x6cff, 0xc99e, 0x21, 0 + .dw 0x6d40, 0xc99e, 0x6d7f, 0xc99e, 0x21, 0 + .dw 0x6dc0, 0xc99e, 0x6dff, 0xc99e, 0x21, 0 + .dw 0x6e40, 0xc99e, 0x6e7f, 0xc99e, 0x21, 0 + .dw 0x6ec0, 0xc99e, 0x6eff, 0xc99e, 0x21, 0 + .dw 0x6f40, 0xc99e, 0x6f7f, 0xc99e, 0x21, 0 + .dw 0x6fc0, 0xc99e, 0x6fff, 0xc99e, 0x21, 0 + .dw 0x7040, 0xc99e, 0x707f, 0xc99e, 0x21, 0 + .dw 0x70c0, 0xc99e, 0x70ff, 0xc99e, 0x21, 0 + .dw 0x7140, 0xc99e, 0x717f, 0xc99e, 0x21, 0 + .dw 0x71c0, 0xc99e, 0x71ff, 0xc99e, 0x21, 0 + .dw 0x7240, 0xc99e, 0x727f, 0xc99e, 0x21, 0 + .dw 0x72c0, 0xc99e, 0x72ff, 0xc99e, 0x21, 0 + .dw 0x7340, 0xc99e, 0x737f, 0xc99e, 0x21, 0 + .dw 0x73c0, 0xc99e, 0x73ff, 0xc99e, 0x21, 0 + .dw 0x7440, 0xc99e, 0x747f, 0xc99e, 0x21, 0 + .dw 0x74c0, 0xc99e, 0x74ff, 0xc99e, 0x21, 0 + .dw 0x7540, 0xc99e, 0x757f, 0xc99e, 0x21, 0 + .dw 0x75c0, 0xc99e, 0x75ff, 0xc99e, 0x21, 0 + .dw 0x7640, 0xc99e, 0x767f, 0xc99e, 0x21, 0 + .dw 0x76c0, 0xc99e, 0x76ff, 0xc99e, 0x21, 0 + .dw 0x7740, 0xc99e, 0x777f, 0xc99e, 0x21, 0 + .dw 0x77c0, 0xc99e, 0x77ff, 0xc99e, 0x21, 0 + .dw 0x7840, 0xc99e, 0x787f, 0xc99e, 0x21, 0 + .dw 0x78c0, 0xc99e, 0x78ff, 0xc99e, 0x21, 0 + .dw 0x7940, 0xc99e, 0x797f, 0xc99e, 0x21, 0 + .dw 0x79c0, 0xc99e, 0x7fff, 0xc99e, 0x21, 0 + .dw 0x8040, 0xc99e, 0x807f, 0xc99e, 0x21, 0 + .dw 0x80c0, 0xc99e, 0x80ff, 0xc99e, 0x21, 0 + .dw 0x8140, 0xc99e, 0x817f, 0xc99e, 0x21, 0 + .dw 0x81c0, 0xc99e, 0x81ff, 0xc99e, 0x21, 0 + .dw 0x8240, 0xc99e, 0x827f, 0xc99e, 0x21, 0 + .dw 0x82c0, 0xc99e, 0x82ff, 0xc99e, 0x21, 0 + .dw 0x8340, 0xc99e, 0x837f, 0xc99e, 0x21, 0 + .dw 0x83c0, 0xc99e, 0x83ff, 0xc99e, 0x21, 0 + .dw 0x8440, 0xc99e, 0x847f, 0xc99e, 0x21, 0 + .dw 0x84c0, 0xc99e, 0x84ff, 0xc99e, 0x21, 0 + .dw 0x8540, 0xc99e, 0x857f, 0xc99e, 0x21, 0 + .dw 0x85c0, 0xc99e, 0x85ff, 0xc99e, 0x21, 0 + .dw 0x8640, 0xc99e, 0x867f, 0xc99e, 0x21, 0 + .dw 0x86c0, 0xc99e, 0x86ff, 0xc99e, 0x21, 0 + .dw 0x8740, 0xc99e, 0x877f, 0xc99e, 0x21, 0 + .dw 0x87c0, 0xc99e, 0x87ff, 0xc99e, 0x21, 0 + .dw 0x8840, 0xc99e, 0x887f, 0xc99e, 0x21, 0 + .dw 0x88c0, 0xc99e, 0x88ff, 0xc99e, 0x21, 0 + .dw 0x8940, 0xc99e, 0x897f, 0xc99e, 0x21, 0 + .dw 0x89c0, 0xc99e, 0x89ff, 0xc99e, 0x21, 0 + .dw 0x8a40, 0xc99e, 0x8a7f, 0xc99e, 0x21, 0 + .dw 0x8ac0, 0xc99e, 0x8aff, 0xc99e, 0x21, 0 + .dw 0x8b40, 0xc99e, 0x8b7f, 0xc99e, 0x21, 0 + .dw 0x8bc0, 0xc99e, 0x8bff, 0xc99e, 0x21, 0 + .dw 0x8c40, 0xc99e, 0x8c7f, 0xc99e, 0x21, 0 + .dw 0x8cc0, 0xc99e, 0x8cff, 0xc99e, 0x21, 0 + .dw 0x8d40, 0xc99e, 0x8d7f, 0xc99e, 0x21, 0 + .dw 0x8dc0, 0xc99e, 0x8dff, 0xc99e, 0x21, 0 + .dw 0x8e40, 0xc99e, 0x8e7f, 0xc99e, 0x21, 0 + .dw 0x8ec0, 0xc99e, 0x8eff, 0xc99e, 0x21, 0 + .dw 0x8f40, 0xc99e, 0x8f7f, 0xc99e, 0x21, 0 + .dw 0x8fc0, 0xc99e, 0x8fff, 0xc99e, 0x21, 0 + .dw 0x9040, 0xc99e, 0x907f, 0xc99e, 0x21, 0 + .dw 0x90c0, 0xc99e, 0x90ff, 0xc99e, 0x21, 0 + .dw 0x9140, 0xc99e, 0x917f, 0xc99e, 0x21, 0 + .dw 0x91c0, 0xc99e, 0x91ff, 0xc99e, 0x21, 0 + .dw 0x9240, 0xc99e, 0x927f, 0xc99e, 0x21, 0 + .dw 0x92c0, 0xc99e, 0x92ff, 0xc99e, 0x21, 0 + .dw 0x9340, 0xc99e, 0x937f, 0xc99e, 0x21, 0 + .dw 0x93c0, 0xc99e, 0x93ff, 0xc99e, 0x21, 0 + .dw 0x9440, 0xc99e, 0x947f, 0xc99e, 0x21, 0 + .dw 0x94c0, 0xc99e, 0x94ff, 0xc99e, 0x21, 0 + .dw 0x9540, 0xc99e, 0x957f, 0xc99e, 0x21, 0 + .dw 0x95c0, 0xc99e, 0x95ff, 0xc99e, 0x21, 0 + .dw 0x9640, 0xc99e, 0x967f, 0xc99e, 0x21, 0 + .dw 0x96c0, 0xc99e, 0x96ff, 0xc99e, 0x21, 0 + .dw 0x9740, 0xc99e, 0x977f, 0xc99e, 0x21, 0 + .dw 0x97c0, 0xc99e, 0x97ff, 0xc99e, 0x21, 0 + .dw 0x9840, 0xc99e, 0x987f, 0xc99e, 0x21, 0 + .dw 0x98c0, 0xc99e, 0x98ff, 0xc99e, 0x21, 0 + .dw 0x9940, 0xc99e, 0x997f, 0xc99e, 0x21, 0 + .dw 0x99c0, 0xc99e, 0x9fff, 0xc99e, 0x21, 0 + .dw 0xa040, 0xc99e, 0xa07f, 0xc99e, 0x21, 0 + .dw 0xa0c0, 0xc99e, 0xa0ff, 0xc99e, 0x21, 0 + .dw 0xa140, 0xc99e, 0xa17f, 0xc99e, 0x21, 0 + .dw 0xa1c0, 0xc99e, 0xa1ff, 0xc99e, 0x21, 0 + .dw 0xa240, 0xc99e, 0xa27f, 0xc99e, 0x21, 0 + .dw 0xa2c0, 0xc99e, 0xa2ff, 0xc99e, 0x21, 0 + .dw 0xa340, 0xc99e, 0xa37f, 0xc99e, 0x21, 0 + .dw 0xa3c0, 0xc99e, 0xa3ff, 0xc99e, 0x21, 0 + .dw 0xa440, 0xc99e, 0xa47f, 0xc99e, 0x21, 0 + .dw 0xa4c0, 0xc99e, 0xa4ff, 0xc99e, 0x21, 0 + .dw 0xa540, 0xc99e, 0xa57f, 0xc99e, 0x21, 0 + .dw 0xa5c0, 0xc99e, 0xa5ff, 0xc99e, 0x21, 0 + .dw 0xa640, 0xc99e, 0xa67f, 0xc99e, 0x21, 0 + .dw 0xa6c0, 0xc99e, 0xa6ff, 0xc99e, 0x21, 0 + .dw 0xa740, 0xc99e, 0xa77f, 0xc99e, 0x21, 0 + .dw 0xa7c0, 0xc99e, 0xa7ff, 0xc99e, 0x21, 0 + .dw 0xa840, 0xc99e, 0xa87f, 0xc99e, 0x21, 0 + .dw 0xa8c0, 0xc99e, 0xa8ff, 0xc99e, 0x21, 0 + .dw 0xa940, 0xc99e, 0xa97f, 0xc99e, 0x21, 0 + .dw 0xa9c0, 0xc99e, 0xa9ff, 0xc99e, 0x21, 0 + .dw 0xaa40, 0xc99e, 0xaa7f, 0xc99e, 0x21, 0 + .dw 0xaac0, 0xc99e, 0xaaff, 0xc99e, 0x21, 0 + .dw 0xab40, 0xc99e, 0xab7f, 0xc99e, 0x21, 0 + .dw 0xabc0, 0xc99e, 0xabff, 0xc99e, 0x21, 0 + .dw 0xac40, 0xc99e, 0xac7f, 0xc99e, 0x21, 0 + .dw 0xacc0, 0xc99e, 0xacff, 0xc99e, 0x21, 0 + .dw 0xad40, 0xc99e, 0xad7f, 0xc99e, 0x21, 0 + .dw 0xadc0, 0xc99e, 0xadff, 0xc99e, 0x21, 0 + .dw 0xae40, 0xc99e, 0xae7f, 0xc99e, 0x21, 0 + .dw 0xaec0, 0xc99e, 0xaeff, 0xc99e, 0x21, 0 + .dw 0xaf40, 0xc99e, 0xaf7f, 0xc99e, 0x21, 0 + .dw 0xafc0, 0xc99e, 0xafff, 0xc99e, 0x21, 0 + .dw 0xb040, 0xc99e, 0xb07f, 0xc99e, 0x21, 0 + .dw 0xb0c0, 0xc99e, 0xb0ff, 0xc99e, 0x21, 0 + .dw 0xb140, 0xc99e, 0xb17f, 0xc99e, 0x21, 0 + .dw 0xb1c0, 0xc99e, 0xb1ff, 0xc99e, 0x21, 0 + .dw 0xb240, 0xc99e, 0xb27f, 0xc99e, 0x21, 0 + .dw 0xb2c0, 0xc99e, 0xb2ff, 0xc99e, 0x21, 0 + .dw 0xb340, 0xc99e, 0xb37f, 0xc99e, 0x21, 0 + .dw 0xb3c0, 0xc99e, 0xb3ff, 0xc99e, 0x21, 0 + .dw 0xb440, 0xc99e, 0xb47f, 0xc99e, 0x21, 0 + .dw 0xb4c0, 0xc99e, 0xb4ff, 0xc99e, 0x21, 0 + .dw 0xb540, 0xc99e, 0xb57f, 0xc99e, 0x21, 0 + .dw 0xb5c0, 0xc99e, 0xb5ff, 0xc99e, 0x21, 0 + .dw 0xb640, 0xc99e, 0xb67f, 0xc99e, 0x21, 0 + .dw 0xb6c0, 0xc99e, 0xb6ff, 0xc99e, 0x21, 0 + .dw 0xb740, 0xc99e, 0xb77f, 0xc99e, 0x21, 0 + .dw 0xb7c0, 0xc99e, 0xb7ff, 0xc99e, 0x21, 0 + .dw 0xb840, 0xc99e, 0xb87f, 0xc99e, 0x21, 0 + .dw 0xb8c0, 0xc99e, 0xb8ff, 0xc99e, 0x21, 0 + .dw 0xb940, 0xc99e, 0xb97f, 0xc99e, 0x21, 0 + .dw 0xb9c0, 0xc99e, 0xbfff, 0xc99e, 0x21, 0 + .dw 0xc040, 0xc99e, 0xc07f, 0xc99e, 0x21, 0 + .dw 0xc0c0, 0xc99e, 0xc0ff, 0xc99e, 0x21, 0 + .dw 0xc140, 0xc99e, 0xc17f, 0xc99e, 0x21, 0 + .dw 0xc1c0, 0xc99e, 0xc1ff, 0xc99e, 0x21, 0 + .dw 0xc240, 0xc99e, 0xc27f, 0xc99e, 0x21, 0 + .dw 0xc2c0, 0xc99e, 0xc2ff, 0xc99e, 0x21, 0 + .dw 0xc340, 0xc99e, 0xc37f, 0xc99e, 0x21, 0 + .dw 0xc3c0, 0xc99e, 0xc3ff, 0xc99e, 0x21, 0 + .dw 0xc440, 0xc99e, 0xc47f, 0xc99e, 0x21, 0 + .dw 0xc4c0, 0xc99e, 0xc4ff, 0xc99e, 0x21, 0 + .dw 0xc540, 0xc99e, 0xc57f, 0xc99e, 0x21, 0 + .dw 0xc5c0, 0xc99e, 0xc5ff, 0xc99e, 0x21, 0 + .dw 0xc640, 0xc99e, 0xc67f, 0xc99e, 0x21, 0 + .dw 0xc6c0, 0xc99e, 0xc6ff, 0xc99e, 0x21, 0 + .dw 0xc740, 0xc99e, 0xc77f, 0xc99e, 0x21, 0 + .dw 0xc7c0, 0xc99e, 0xc7ff, 0xc99e, 0x21, 0 + .dw 0xc840, 0xc99e, 0xc87f, 0xc99e, 0x21, 0 + .dw 0xc8c0, 0xc99e, 0xc8ff, 0xc99e, 0x21, 0 + .dw 0xc940, 0xc99e, 0xc97f, 0xc99e, 0x21, 0 + .dw 0xc9c0, 0xc99e, 0xc9ff, 0xc99e, 0x21, 0 + .dw 0xca40, 0xc99e, 0xca7f, 0xc99e, 0x21, 0 + .dw 0xcac0, 0xc99e, 0xcaff, 0xc99e, 0x21, 0 + .dw 0xcb40, 0xc99e, 0xcb7f, 0xc99e, 0x21, 0 + .dw 0xcbc0, 0xc99e, 0xcbff, 0xc99e, 0x21, 0 + .dw 0xcc40, 0xc99e, 0xcc7f, 0xc99e, 0x21, 0 + .dw 0xccc0, 0xc99e, 0xccff, 0xc99e, 0x21, 0 + .dw 0xcd40, 0xc99e, 0xcd7f, 0xc99e, 0x21, 0 + .dw 0xcdc0, 0xc99e, 0xcdff, 0xc99e, 0x21, 0 + .dw 0xce40, 0xc99e, 0xce7f, 0xc99e, 0x21, 0 + .dw 0xcec0, 0xc99e, 0xceff, 0xc99e, 0x21, 0 + .dw 0xcf40, 0xc99e, 0xcf7f, 0xc99e, 0x21, 0 + .dw 0xcfc0, 0xc99e, 0xcfff, 0xc99e, 0x21, 0 + .dw 0xd040, 0xc99e, 0xd07f, 0xc99e, 0x21, 0 + .dw 0xd0c0, 0xc99e, 0xd0ff, 0xc99e, 0x21, 0 + .dw 0xd140, 0xc99e, 0xd17f, 0xc99e, 0x21, 0 + .dw 0xd1c0, 0xc99e, 0xd1ff, 0xc99e, 0x21, 0 + .dw 0xd240, 0xc99e, 0xd27f, 0xc99e, 0x21, 0 + .dw 0xd2c0, 0xc99e, 0xd2ff, 0xc99e, 0x21, 0 + .dw 0xd340, 0xc99e, 0xd37f, 0xc99e, 0x21, 0 + .dw 0xd3c0, 0xc99e, 0xd3ff, 0xc99e, 0x21, 0 + .dw 0xd440, 0xc99e, 0xd47f, 0xc99e, 0x21, 0 + .dw 0xd4c0, 0xc99e, 0xd4ff, 0xc99e, 0x21, 0 + .dw 0xd540, 0xc99e, 0xd57f, 0xc99e, 0x21, 0 + .dw 0xd5c0, 0xc99e, 0xd5ff, 0xc99e, 0x21, 0 + .dw 0xd640, 0xc99e, 0xd67f, 0xc99e, 0x21, 0 + .dw 0xd6c0, 0xc99e, 0xd6ff, 0xc99e, 0x21, 0 + .dw 0xd740, 0xc99e, 0xd77f, 0xc99e, 0x21, 0 + .dw 0xd7c0, 0xc99e, 0xd7ff, 0xc99e, 0x21, 0 + .dw 0xd840, 0xc99e, 0xd87f, 0xc99e, 0x21, 0 + .dw 0xd8c0, 0xc99e, 0xd8ff, 0xc99e, 0x21, 0 + .dw 0xd940, 0xc99e, 0xd97f, 0xc99e, 0x21, 0 + .dw 0xd9c0, 0xc99e, 0xdfff, 0xc99e, 0x21, 0 + .dw 0xe040, 0xc99e, 0xe07f, 0xc99e, 0x21, 0 + .dw 0xe0c0, 0xc99e, 0xe0ff, 0xc99e, 0x21, 0 + .dw 0xe140, 0xc99e, 0xe17f, 0xc99e, 0x21, 0 + .dw 0xe1c0, 0xc99e, 0xe1ff, 0xc99e, 0x21, 0 + .dw 0xe240, 0xc99e, 0xe27f, 0xc99e, 0x21, 0 + .dw 0xe2c0, 0xc99e, 0xe2ff, 0xc99e, 0x21, 0 + .dw 0xe340, 0xc99e, 0xe37f, 0xc99e, 0x21, 0 + .dw 0xe3c0, 0xc99e, 0xe3ff, 0xc99e, 0x21, 0 + .dw 0xe440, 0xc99e, 0xe47f, 0xc99e, 0x21, 0 + .dw 0xe4c0, 0xc99e, 0xe4ff, 0xc99e, 0x21, 0 + .dw 0xe540, 0xc99e, 0xe57f, 0xc99e, 0x21, 0 + .dw 0xe5c0, 0xc99e, 0xe5ff, 0xc99e, 0x21, 0 + .dw 0xe640, 0xc99e, 0xe67f, 0xc99e, 0x21, 0 + .dw 0xe6c0, 0xc99e, 0xe6ff, 0xc99e, 0x21, 0 + .dw 0xe740, 0xc99e, 0xe77f, 0xc99e, 0x21, 0 + .dw 0xe7c0, 0xc99e, 0xe7ff, 0xc99e, 0x21, 0 + .dw 0xe840, 0xc99e, 0xe87f, 0xc99e, 0x21, 0 + .dw 0xe8c0, 0xc99e, 0xe8ff, 0xc99e, 0x21, 0 + .dw 0xe940, 0xc99e, 0xe97f, 0xc99e, 0x21, 0 + .dw 0xe9c0, 0xc99e, 0xe9ff, 0xc99e, 0x21, 0 + .dw 0xea40, 0xc99e, 0xea7f, 0xc99e, 0x21, 0 + .dw 0xeac0, 0xc99e, 0xeaff, 0xc99e, 0x21, 0 + .dw 0xeb40, 0xc99e, 0xeb7f, 0xc99e, 0x21, 0 + .dw 0xebc0, 0xc99e, 0xebff, 0xc99e, 0x21, 0 + .dw 0xec40, 0xc99e, 0xec7f, 0xc99e, 0x21, 0 + .dw 0xecc0, 0xc99e, 0xecff, 0xc99e, 0x21, 0 + .dw 0xed40, 0xc99e, 0xed7f, 0xc99e, 0x21, 0 + .dw 0xedc0, 0xc99e, 0xedff, 0xc99e, 0x21, 0 + .dw 0xee40, 0xc99e, 0xee7f, 0xc99e, 0x21, 0 + .dw 0xeec0, 0xc99e, 0xeeff, 0xc99e, 0x21, 0 + .dw 0xef40, 0xc99e, 0xef7f, 0xc99e, 0x21, 0 + .dw 0xefc0, 0xc99e, 0xefff, 0xc99e, 0x21, 0 + .dw 0xf040, 0xc99e, 0xf07f, 0xc99e, 0x21, 0 + .dw 0xf0c0, 0xc99e, 0xf0ff, 0xc99e, 0x21, 0 + .dw 0xf140, 0xc99e, 0xf17f, 0xc99e, 0x21, 0 + .dw 0xf1c0, 0xc99e, 0xf1ff, 0xc99e, 0x21, 0 + .dw 0xf240, 0xc99e, 0xf27f, 0xc99e, 0x21, 0 + .dw 0xf2c0, 0xc99e, 0xf2ff, 0xc99e, 0x21, 0 + .dw 0xf340, 0xc99e, 0xf37f, 0xc99e, 0x21, 0 + .dw 0xf3c0, 0xc99e, 0xf3ff, 0xc99e, 0x21, 0 + .dw 0xf440, 0xc99e, 0xf47f, 0xc99e, 0x21, 0 + .dw 0xf4c0, 0xc99e, 0xf4ff, 0xc99e, 0x21, 0 + .dw 0xf540, 0xc99e, 0xf57f, 0xc99e, 0x21, 0 + .dw 0xf5c0, 0xc99e, 0xf5ff, 0xc99e, 0x21, 0 + .dw 0xf640, 0xc99e, 0xf67f, 0xc99e, 0x21, 0 + .dw 0xf6c0, 0xc99e, 0xf6ff, 0xc99e, 0x21, 0 + .dw 0xf740, 0xc99e, 0xf77f, 0xc99e, 0x21, 0 + .dw 0xf7c0, 0xc99e, 0xf7ff, 0xc99e, 0x21, 0 + .dw 0xf840, 0xc99e, 0xf87f, 0xc99e, 0x21, 0 + .dw 0xf8c0, 0xc99e, 0xf8ff, 0xc99e, 0x21, 0 + .dw 0xf940, 0xc99e, 0xf97f, 0xc99e, 0x21, 0 + .dw 0xf9c0, 0xc99e, 0xffff, 0xc99e, 0x21, 0 + .dw 0x0040, 0xc99f, 0x007f, 0xc99f, 0x21, 0 + .dw 0x00c0, 0xc99f, 0x00ff, 0xc99f, 0x21, 0 + .dw 0x0140, 0xc99f, 0x017f, 0xc99f, 0x21, 0 + .dw 0x01c0, 0xc99f, 0x01ff, 0xc99f, 0x21, 0 + .dw 0x0240, 0xc99f, 0x027f, 0xc99f, 0x21, 0 + .dw 0x02c0, 0xc99f, 0x02ff, 0xc99f, 0x21, 0 + .dw 0x0340, 0xc99f, 0x037f, 0xc99f, 0x21, 0 + .dw 0x03c0, 0xc99f, 0x03ff, 0xc99f, 0x21, 0 + .dw 0x0440, 0xc99f, 0x047f, 0xc99f, 0x21, 0 + .dw 0x04c0, 0xc99f, 0x04ff, 0xc99f, 0x21, 0 + .dw 0x0540, 0xc99f, 0x057f, 0xc99f, 0x21, 0 + .dw 0x05c0, 0xc99f, 0x05ff, 0xc99f, 0x21, 0 + .dw 0x0640, 0xc99f, 0x067f, 0xc99f, 0x21, 0 + .dw 0x06c0, 0xc99f, 0x06ff, 0xc99f, 0x21, 0 + .dw 0x0740, 0xc99f, 0x077f, 0xc99f, 0x21, 0 + .dw 0x07c0, 0xc99f, 0x07ff, 0xc99f, 0x21, 0 + .dw 0x0840, 0xc99f, 0x087f, 0xc99f, 0x21, 0 + .dw 0x08c0, 0xc99f, 0x08ff, 0xc99f, 0x21, 0 + .dw 0x0940, 0xc99f, 0x097f, 0xc99f, 0x21, 0 + .dw 0x09c0, 0xc99f, 0x09ff, 0xc99f, 0x21, 0 + .dw 0x0a40, 0xc99f, 0x0a7f, 0xc99f, 0x21, 0 + .dw 0x0ac0, 0xc99f, 0x0aff, 0xc99f, 0x21, 0 + .dw 0x0b40, 0xc99f, 0x0b7f, 0xc99f, 0x21, 0 + .dw 0x0bc0, 0xc99f, 0x0bff, 0xc99f, 0x21, 0 + .dw 0x0c40, 0xc99f, 0x0c7f, 0xc99f, 0x21, 0 + .dw 0x0cc0, 0xc99f, 0x0cff, 0xc99f, 0x21, 0 + .dw 0x0d40, 0xc99f, 0x0d7f, 0xc99f, 0x21, 0 + .dw 0x0dc0, 0xc99f, 0x0dff, 0xc99f, 0x21, 0 + .dw 0x0e40, 0xc99f, 0x0e7f, 0xc99f, 0x21, 0 + .dw 0x0ec0, 0xc99f, 0x0eff, 0xc99f, 0x21, 0 + .dw 0x0f40, 0xc99f, 0x0f7f, 0xc99f, 0x21, 0 + .dw 0x0fc0, 0xc99f, 0x0fff, 0xc99f, 0x21, 0 + .dw 0x1040, 0xc99f, 0x107f, 0xc99f, 0x21, 0 + .dw 0x10c0, 0xc99f, 0x10ff, 0xc99f, 0x21, 0 + .dw 0x1140, 0xc99f, 0x117f, 0xc99f, 0x21, 0 + .dw 0x11c0, 0xc99f, 0x11ff, 0xc99f, 0x21, 0 + .dw 0x1240, 0xc99f, 0x127f, 0xc99f, 0x21, 0 + .dw 0x12c0, 0xc99f, 0x12ff, 0xc99f, 0x21, 0 + .dw 0x1340, 0xc99f, 0x137f, 0xc99f, 0x21, 0 + .dw 0x13c0, 0xc99f, 0x13ff, 0xc99f, 0x21, 0 + .dw 0x1440, 0xc99f, 0x147f, 0xc99f, 0x21, 0 + .dw 0x14c0, 0xc99f, 0x14ff, 0xc99f, 0x21, 0 + .dw 0x1540, 0xc99f, 0x157f, 0xc99f, 0x21, 0 + .dw 0x15c0, 0xc99f, 0x15ff, 0xc99f, 0x21, 0 + .dw 0x1640, 0xc99f, 0x167f, 0xc99f, 0x21, 0 + .dw 0x16c0, 0xc99f, 0x16ff, 0xc99f, 0x21, 0 + .dw 0x1740, 0xc99f, 0x177f, 0xc99f, 0x21, 0 + .dw 0x17c0, 0xc99f, 0x17ff, 0xc99f, 0x21, 0 + .dw 0x1840, 0xc99f, 0x187f, 0xc99f, 0x21, 0 + .dw 0x18c0, 0xc99f, 0x18ff, 0xc99f, 0x21, 0 + .dw 0x1940, 0xc99f, 0x197f, 0xc99f, 0x21, 0 + .dw 0x19c0, 0xc99f, 0x1fff, 0xc99f, 0x21, 0 + .dw 0x2040, 0xc99f, 0x207f, 0xc99f, 0x21, 0 + .dw 0x20c0, 0xc99f, 0x20ff, 0xc99f, 0x21, 0 + .dw 0x2140, 0xc99f, 0x217f, 0xc99f, 0x21, 0 + .dw 0x21c0, 0xc99f, 0x21ff, 0xc99f, 0x21, 0 + .dw 0x2240, 0xc99f, 0x227f, 0xc99f, 0x21, 0 + .dw 0x22c0, 0xc99f, 0x22ff, 0xc99f, 0x21, 0 + .dw 0x2340, 0xc99f, 0x237f, 0xc99f, 0x21, 0 + .dw 0x23c0, 0xc99f, 0x23ff, 0xc99f, 0x21, 0 + .dw 0x2440, 0xc99f, 0x247f, 0xc99f, 0x21, 0 + .dw 0x24c0, 0xc99f, 0x24ff, 0xc99f, 0x21, 0 + .dw 0x2540, 0xc99f, 0x257f, 0xc99f, 0x21, 0 + .dw 0x25c0, 0xc99f, 0x25ff, 0xc99f, 0x21, 0 + .dw 0x2640, 0xc99f, 0x267f, 0xc99f, 0x21, 0 + .dw 0x26c0, 0xc99f, 0x26ff, 0xc99f, 0x21, 0 + .dw 0x2740, 0xc99f, 0x277f, 0xc99f, 0x21, 0 + .dw 0x27c0, 0xc99f, 0x27ff, 0xc99f, 0x21, 0 + .dw 0x2840, 0xc99f, 0x287f, 0xc99f, 0x21, 0 + .dw 0x28c0, 0xc99f, 0x28ff, 0xc99f, 0x21, 0 + .dw 0x2940, 0xc99f, 0x297f, 0xc99f, 0x21, 0 + .dw 0x29c0, 0xc99f, 0x29ff, 0xc99f, 0x21, 0 + .dw 0x2a40, 0xc99f, 0x2a7f, 0xc99f, 0x21, 0 + .dw 0x2ac0, 0xc99f, 0x2aff, 0xc99f, 0x21, 0 + .dw 0x2b40, 0xc99f, 0x2b7f, 0xc99f, 0x21, 0 + .dw 0x2bc0, 0xc99f, 0x2bff, 0xc99f, 0x21, 0 + .dw 0x2c40, 0xc99f, 0x2c7f, 0xc99f, 0x21, 0 + .dw 0x2cc0, 0xc99f, 0x2cff, 0xc99f, 0x21, 0 + .dw 0x2d40, 0xc99f, 0x2d7f, 0xc99f, 0x21, 0 + .dw 0x2dc0, 0xc99f, 0x2dff, 0xc99f, 0x21, 0 + .dw 0x2e40, 0xc99f, 0x2e7f, 0xc99f, 0x21, 0 + .dw 0x2ec0, 0xc99f, 0x2eff, 0xc99f, 0x21, 0 + .dw 0x2f40, 0xc99f, 0x2f7f, 0xc99f, 0x21, 0 + .dw 0x2fc0, 0xc99f, 0x2fff, 0xc99f, 0x21, 0 + .dw 0x3040, 0xc99f, 0x307f, 0xc99f, 0x21, 0 + .dw 0x30c0, 0xc99f, 0x30ff, 0xc99f, 0x21, 0 + .dw 0x3140, 0xc99f, 0x317f, 0xc99f, 0x21, 0 + .dw 0x31c0, 0xc99f, 0x31ff, 0xc99f, 0x21, 0 + .dw 0x3240, 0xc99f, 0x327f, 0xc99f, 0x21, 0 + .dw 0x32c0, 0xc99f, 0x32ff, 0xc99f, 0x21, 0 + .dw 0x3340, 0xc99f, 0x337f, 0xc99f, 0x21, 0 + .dw 0x33c0, 0xc99f, 0x33ff, 0xc99f, 0x21, 0 + .dw 0x3440, 0xc99f, 0x347f, 0xc99f, 0x21, 0 + .dw 0x34c0, 0xc99f, 0x34ff, 0xc99f, 0x21, 0 + .dw 0x3540, 0xc99f, 0x357f, 0xc99f, 0x21, 0 + .dw 0x35c0, 0xc99f, 0x35ff, 0xc99f, 0x21, 0 + .dw 0x3640, 0xc99f, 0x367f, 0xc99f, 0x21, 0 + .dw 0x36c0, 0xc99f, 0x36ff, 0xc99f, 0x21, 0 + .dw 0x3740, 0xc99f, 0x377f, 0xc99f, 0x21, 0 + .dw 0x37c0, 0xc99f, 0x37ff, 0xc99f, 0x21, 0 + .dw 0x3840, 0xc99f, 0x387f, 0xc99f, 0x21, 0 + .dw 0x38c0, 0xc99f, 0x38ff, 0xc99f, 0x21, 0 + .dw 0x3940, 0xc99f, 0x397f, 0xc99f, 0x21, 0 + .dw 0x39c0, 0xc99f, 0x1fff, 0xca00, 0x21, 0 + .dw 0x2800, 0xca00, 0xffff, 0xca03, 0x21, 0 + .dw 0x0200, 0xca04, 0x1fff, 0xca04, 0x21, 0 + .dw 0x2800, 0xca04, 0x3fff, 0xca04, 0x21, 0 + .dw 0x4200, 0xca04, 0x5fff, 0xca04, 0x21, 0 + .dw 0x6800, 0xca04, 0x7fff, 0xca04, 0x21, 0 + .dw 0x8200, 0xca04, 0x9fff, 0xca04, 0x21, 0 + .dw 0xa800, 0xca04, 0xbfff, 0xca04, 0x21, 0 + .dw 0xc200, 0xca04, 0xdfff, 0xca04, 0x21, 0 + .dw 0xe800, 0xca04, 0x1fff, 0xca08, 0x21, 0 + .dw 0x2040, 0xca08, 0x207f, 0xca08, 0x21, 0 + .dw 0x20c0, 0xca08, 0x20ff, 0xca08, 0x21, 0 + .dw 0x2140, 0xca08, 0x217f, 0xca08, 0x21, 0 + .dw 0x21c0, 0xca08, 0x21ff, 0xca08, 0x21, 0 + .dw 0x2240, 0xca08, 0x227f, 0xca08, 0x21, 0 + .dw 0x22c0, 0xca08, 0x22ff, 0xca08, 0x21, 0 + .dw 0x2340, 0xca08, 0x237f, 0xca08, 0x21, 0 + .dw 0x23c0, 0xca08, 0x23ff, 0xca08, 0x21, 0 + .dw 0x2440, 0xca08, 0x247f, 0xca08, 0x21, 0 + .dw 0x24c0, 0xca08, 0x24ff, 0xca08, 0x21, 0 + .dw 0x2540, 0xca08, 0x257f, 0xca08, 0x21, 0 + .dw 0x25c0, 0xca08, 0x25ff, 0xca08, 0x21, 0 + .dw 0x2640, 0xca08, 0x267f, 0xca08, 0x21, 0 + .dw 0x26c0, 0xca08, 0x26ff, 0xca08, 0x21, 0 + .dw 0x2740, 0xca08, 0x277f, 0xca08, 0x21, 0 + .dw 0x27c0, 0xca08, 0xffff, 0xca0b, 0x21, 0 + .dw 0x0040, 0xca0c, 0x007f, 0xca0c, 0x21, 0 + .dw 0x00c0, 0xca0c, 0x00ff, 0xca0c, 0x21, 0 + .dw 0x0140, 0xca0c, 0x017f, 0xca0c, 0x21, 0 + .dw 0x01c0, 0xca0c, 0x1fff, 0xca0c, 0x21, 0 + .dw 0x2040, 0xca0c, 0x207f, 0xca0c, 0x21, 0 + .dw 0x20c0, 0xca0c, 0x20ff, 0xca0c, 0x21, 0 + .dw 0x2140, 0xca0c, 0x217f, 0xca0c, 0x21, 0 + .dw 0x21c0, 0xca0c, 0x21ff, 0xca0c, 0x21, 0 + .dw 0x2240, 0xca0c, 0x227f, 0xca0c, 0x21, 0 + .dw 0x22c0, 0xca0c, 0x22ff, 0xca0c, 0x21, 0 + .dw 0x2340, 0xca0c, 0x237f, 0xca0c, 0x21, 0 + .dw 0x23c0, 0xca0c, 0x23ff, 0xca0c, 0x21, 0 + .dw 0x2440, 0xca0c, 0x247f, 0xca0c, 0x21, 0 + .dw 0x24c0, 0xca0c, 0x24ff, 0xca0c, 0x21, 0 + .dw 0x2540, 0xca0c, 0x257f, 0xca0c, 0x21, 0 + .dw 0x25c0, 0xca0c, 0x25ff, 0xca0c, 0x21, 0 + .dw 0x2640, 0xca0c, 0x267f, 0xca0c, 0x21, 0 + .dw 0x26c0, 0xca0c, 0x26ff, 0xca0c, 0x21, 0 + .dw 0x2740, 0xca0c, 0x277f, 0xca0c, 0x21, 0 + .dw 0x27c0, 0xca0c, 0x3fff, 0xca0c, 0x21, 0 + .dw 0x4040, 0xca0c, 0x407f, 0xca0c, 0x21, 0 + .dw 0x40c0, 0xca0c, 0x40ff, 0xca0c, 0x21, 0 + .dw 0x4140, 0xca0c, 0x417f, 0xca0c, 0x21, 0 + .dw 0x41c0, 0xca0c, 0x5fff, 0xca0c, 0x21, 0 + .dw 0x6040, 0xca0c, 0x607f, 0xca0c, 0x21, 0 + .dw 0x60c0, 0xca0c, 0x60ff, 0xca0c, 0x21, 0 + .dw 0x6140, 0xca0c, 0x617f, 0xca0c, 0x21, 0 + .dw 0x61c0, 0xca0c, 0x61ff, 0xca0c, 0x21, 0 + .dw 0x6240, 0xca0c, 0x627f, 0xca0c, 0x21, 0 + .dw 0x62c0, 0xca0c, 0x62ff, 0xca0c, 0x21, 0 + .dw 0x6340, 0xca0c, 0x637f, 0xca0c, 0x21, 0 + .dw 0x63c0, 0xca0c, 0x63ff, 0xca0c, 0x21, 0 + .dw 0x6440, 0xca0c, 0x647f, 0xca0c, 0x21, 0 + .dw 0x64c0, 0xca0c, 0x64ff, 0xca0c, 0x21, 0 + .dw 0x6540, 0xca0c, 0x657f, 0xca0c, 0x21, 0 + .dw 0x65c0, 0xca0c, 0x65ff, 0xca0c, 0x21, 0 + .dw 0x6640, 0xca0c, 0x667f, 0xca0c, 0x21, 0 + .dw 0x66c0, 0xca0c, 0x66ff, 0xca0c, 0x21, 0 + .dw 0x6740, 0xca0c, 0x677f, 0xca0c, 0x21, 0 + .dw 0x67c0, 0xca0c, 0x7fff, 0xca0c, 0x21, 0 + .dw 0x8040, 0xca0c, 0x807f, 0xca0c, 0x21, 0 + .dw 0x80c0, 0xca0c, 0x80ff, 0xca0c, 0x21, 0 + .dw 0x8140, 0xca0c, 0x817f, 0xca0c, 0x21, 0 + .dw 0x81c0, 0xca0c, 0x9fff, 0xca0c, 0x21, 0 + .dw 0xa040, 0xca0c, 0xa07f, 0xca0c, 0x21, 0 + .dw 0xa0c0, 0xca0c, 0xa0ff, 0xca0c, 0x21, 0 + .dw 0xa140, 0xca0c, 0xa17f, 0xca0c, 0x21, 0 + .dw 0xa1c0, 0xca0c, 0xa1ff, 0xca0c, 0x21, 0 + .dw 0xa240, 0xca0c, 0xa27f, 0xca0c, 0x21, 0 + .dw 0xa2c0, 0xca0c, 0xa2ff, 0xca0c, 0x21, 0 + .dw 0xa340, 0xca0c, 0xa37f, 0xca0c, 0x21, 0 + .dw 0xa3c0, 0xca0c, 0xa3ff, 0xca0c, 0x21, 0 + .dw 0xa440, 0xca0c, 0xa47f, 0xca0c, 0x21, 0 + .dw 0xa4c0, 0xca0c, 0xa4ff, 0xca0c, 0x21, 0 + .dw 0xa540, 0xca0c, 0xa57f, 0xca0c, 0x21, 0 + .dw 0xa5c0, 0xca0c, 0xa5ff, 0xca0c, 0x21, 0 + .dw 0xa640, 0xca0c, 0xa67f, 0xca0c, 0x21, 0 + .dw 0xa6c0, 0xca0c, 0xa6ff, 0xca0c, 0x21, 0 + .dw 0xa740, 0xca0c, 0xa77f, 0xca0c, 0x21, 0 + .dw 0xa7c0, 0xca0c, 0xbfff, 0xca0c, 0x21, 0 + .dw 0xc040, 0xca0c, 0xc07f, 0xca0c, 0x21, 0 + .dw 0xc0c0, 0xca0c, 0xc0ff, 0xca0c, 0x21, 0 + .dw 0xc140, 0xca0c, 0xc17f, 0xca0c, 0x21, 0 + .dw 0xc1c0, 0xca0c, 0xdfff, 0xca0c, 0x21, 0 + .dw 0xe040, 0xca0c, 0xe07f, 0xca0c, 0x21, 0 + .dw 0xe0c0, 0xca0c, 0xe0ff, 0xca0c, 0x21, 0 + .dw 0xe140, 0xca0c, 0xe17f, 0xca0c, 0x21, 0 + .dw 0xe1c0, 0xca0c, 0xe1ff, 0xca0c, 0x21, 0 + .dw 0xe240, 0xca0c, 0xe27f, 0xca0c, 0x21, 0 + .dw 0xe2c0, 0xca0c, 0xe2ff, 0xca0c, 0x21, 0 + .dw 0xe340, 0xca0c, 0xe37f, 0xca0c, 0x21, 0 + .dw 0xe3c0, 0xca0c, 0xe3ff, 0xca0c, 0x21, 0 + .dw 0xe440, 0xca0c, 0xe47f, 0xca0c, 0x21, 0 + .dw 0xe4c0, 0xca0c, 0xe4ff, 0xca0c, 0x21, 0 + .dw 0xe540, 0xca0c, 0xe57f, 0xca0c, 0x21, 0 + .dw 0xe5c0, 0xca0c, 0xe5ff, 0xca0c, 0x21, 0 + .dw 0xe640, 0xca0c, 0xe67f, 0xca0c, 0x21, 0 + .dw 0xe6c0, 0xca0c, 0xe6ff, 0xca0c, 0x21, 0 + .dw 0xe740, 0xca0c, 0xe77f, 0xca0c, 0x21, 0 + .dw 0xe7c0, 0xca0c, 0xffff, 0xca13, 0x21, 0 + .dw 0x0200, 0xca14, 0x1fff, 0xca14, 0x21, 0 + .dw 0x2800, 0xca14, 0x3fff, 0xca14, 0x21, 0 + .dw 0x4200, 0xca14, 0x5fff, 0xca14, 0x21, 0 + .dw 0x6800, 0xca14, 0x7fff, 0xca14, 0x21, 0 + .dw 0x8200, 0xca14, 0x9fff, 0xca14, 0x21, 0 + .dw 0xa800, 0xca14, 0xbfff, 0xca14, 0x21, 0 + .dw 0xc200, 0xca14, 0xdfff, 0xca14, 0x21, 0 + .dw 0xe800, 0xca14, 0xffff, 0xca1b, 0x21, 0 + .dw 0x0040, 0xca1c, 0x007f, 0xca1c, 0x21, 0 + .dw 0x00c0, 0xca1c, 0x00ff, 0xca1c, 0x21, 0 + .dw 0x0140, 0xca1c, 0x017f, 0xca1c, 0x21, 0 + .dw 0x01c0, 0xca1c, 0x1fff, 0xca1c, 0x21, 0 + .dw 0x2040, 0xca1c, 0x207f, 0xca1c, 0x21, 0 + .dw 0x20c0, 0xca1c, 0x20ff, 0xca1c, 0x21, 0 + .dw 0x2140, 0xca1c, 0x217f, 0xca1c, 0x21, 0 + .dw 0x21c0, 0xca1c, 0x21ff, 0xca1c, 0x21, 0 + .dw 0x2240, 0xca1c, 0x227f, 0xca1c, 0x21, 0 + .dw 0x22c0, 0xca1c, 0x22ff, 0xca1c, 0x21, 0 + .dw 0x2340, 0xca1c, 0x237f, 0xca1c, 0x21, 0 + .dw 0x23c0, 0xca1c, 0x23ff, 0xca1c, 0x21, 0 + .dw 0x2440, 0xca1c, 0x247f, 0xca1c, 0x21, 0 + .dw 0x24c0, 0xca1c, 0x24ff, 0xca1c, 0x21, 0 + .dw 0x2540, 0xca1c, 0x257f, 0xca1c, 0x21, 0 + .dw 0x25c0, 0xca1c, 0x25ff, 0xca1c, 0x21, 0 + .dw 0x2640, 0xca1c, 0x267f, 0xca1c, 0x21, 0 + .dw 0x26c0, 0xca1c, 0x26ff, 0xca1c, 0x21, 0 + .dw 0x2740, 0xca1c, 0x277f, 0xca1c, 0x21, 0 + .dw 0x27c0, 0xca1c, 0x3fff, 0xca1c, 0x21, 0 + .dw 0x4040, 0xca1c, 0x407f, 0xca1c, 0x21, 0 + .dw 0x40c0, 0xca1c, 0x40ff, 0xca1c, 0x21, 0 + .dw 0x4140, 0xca1c, 0x417f, 0xca1c, 0x21, 0 + .dw 0x41c0, 0xca1c, 0x5fff, 0xca1c, 0x21, 0 + .dw 0x6040, 0xca1c, 0x607f, 0xca1c, 0x21, 0 + .dw 0x60c0, 0xca1c, 0x60ff, 0xca1c, 0x21, 0 + .dw 0x6140, 0xca1c, 0x617f, 0xca1c, 0x21, 0 + .dw 0x61c0, 0xca1c, 0x61ff, 0xca1c, 0x21, 0 + .dw 0x6240, 0xca1c, 0x627f, 0xca1c, 0x21, 0 + .dw 0x62c0, 0xca1c, 0x62ff, 0xca1c, 0x21, 0 + .dw 0x6340, 0xca1c, 0x637f, 0xca1c, 0x21, 0 + .dw 0x63c0, 0xca1c, 0x63ff, 0xca1c, 0x21, 0 + .dw 0x6440, 0xca1c, 0x647f, 0xca1c, 0x21, 0 + .dw 0x64c0, 0xca1c, 0x64ff, 0xca1c, 0x21, 0 + .dw 0x6540, 0xca1c, 0x657f, 0xca1c, 0x21, 0 + .dw 0x65c0, 0xca1c, 0x65ff, 0xca1c, 0x21, 0 + .dw 0x6640, 0xca1c, 0x667f, 0xca1c, 0x21, 0 + .dw 0x66c0, 0xca1c, 0x66ff, 0xca1c, 0x21, 0 + .dw 0x6740, 0xca1c, 0x677f, 0xca1c, 0x21, 0 + .dw 0x67c0, 0xca1c, 0x7fff, 0xca1c, 0x21, 0 + .dw 0x8040, 0xca1c, 0x807f, 0xca1c, 0x21, 0 + .dw 0x80c0, 0xca1c, 0x80ff, 0xca1c, 0x21, 0 + .dw 0x8140, 0xca1c, 0x817f, 0xca1c, 0x21, 0 + .dw 0x81c0, 0xca1c, 0x9fff, 0xca1c, 0x21, 0 + .dw 0xa040, 0xca1c, 0xa07f, 0xca1c, 0x21, 0 + .dw 0xa0c0, 0xca1c, 0xa0ff, 0xca1c, 0x21, 0 + .dw 0xa140, 0xca1c, 0xa17f, 0xca1c, 0x21, 0 + .dw 0xa1c0, 0xca1c, 0xa1ff, 0xca1c, 0x21, 0 + .dw 0xa240, 0xca1c, 0xa27f, 0xca1c, 0x21, 0 + .dw 0xa2c0, 0xca1c, 0xa2ff, 0xca1c, 0x21, 0 + .dw 0xa340, 0xca1c, 0xa37f, 0xca1c, 0x21, 0 + .dw 0xa3c0, 0xca1c, 0xa3ff, 0xca1c, 0x21, 0 + .dw 0xa440, 0xca1c, 0xa47f, 0xca1c, 0x21, 0 + .dw 0xa4c0, 0xca1c, 0xa4ff, 0xca1c, 0x21, 0 + .dw 0xa540, 0xca1c, 0xa57f, 0xca1c, 0x21, 0 + .dw 0xa5c0, 0xca1c, 0xa5ff, 0xca1c, 0x21, 0 + .dw 0xa640, 0xca1c, 0xa67f, 0xca1c, 0x21, 0 + .dw 0xa6c0, 0xca1c, 0xa6ff, 0xca1c, 0x21, 0 + .dw 0xa740, 0xca1c, 0xa77f, 0xca1c, 0x21, 0 + .dw 0xa7c0, 0xca1c, 0xbfff, 0xca1c, 0x21, 0 + .dw 0xc040, 0xca1c, 0xc07f, 0xca1c, 0x21, 0 + .dw 0xc0c0, 0xca1c, 0xc0ff, 0xca1c, 0x21, 0 + .dw 0xc140, 0xca1c, 0xc17f, 0xca1c, 0x21, 0 + .dw 0xc1c0, 0xca1c, 0xdfff, 0xca1c, 0x21, 0 + .dw 0xe040, 0xca1c, 0xe07f, 0xca1c, 0x21, 0 + .dw 0xe0c0, 0xca1c, 0xe0ff, 0xca1c, 0x21, 0 + .dw 0xe140, 0xca1c, 0xe17f, 0xca1c, 0x21, 0 + .dw 0xe1c0, 0xca1c, 0xe1ff, 0xca1c, 0x21, 0 + .dw 0xe240, 0xca1c, 0xe27f, 0xca1c, 0x21, 0 + .dw 0xe2c0, 0xca1c, 0xe2ff, 0xca1c, 0x21, 0 + .dw 0xe340, 0xca1c, 0xe37f, 0xca1c, 0x21, 0 + .dw 0xe3c0, 0xca1c, 0xe3ff, 0xca1c, 0x21, 0 + .dw 0xe440, 0xca1c, 0xe47f, 0xca1c, 0x21, 0 + .dw 0xe4c0, 0xca1c, 0xe4ff, 0xca1c, 0x21, 0 + .dw 0xe540, 0xca1c, 0xe57f, 0xca1c, 0x21, 0 + .dw 0xe5c0, 0xca1c, 0xe5ff, 0xca1c, 0x21, 0 + .dw 0xe640, 0xca1c, 0xe67f, 0xca1c, 0x21, 0 + .dw 0xe6c0, 0xca1c, 0xe6ff, 0xca1c, 0x21, 0 + .dw 0xe740, 0xca1c, 0xe77f, 0xca1c, 0x21, 0 + .dw 0xe7c0, 0xca1c, 0x1fff, 0xca20, 0x21, 0 + .dw 0x2800, 0xca20, 0xffff, 0xca23, 0x21, 0 + .dw 0x0200, 0xca24, 0x1fff, 0xca24, 0x21, 0 + .dw 0x2800, 0xca24, 0x3fff, 0xca24, 0x21, 0 + .dw 0x4200, 0xca24, 0x5fff, 0xca24, 0x21, 0 + .dw 0x6800, 0xca24, 0x7fff, 0xca24, 0x21, 0 + .dw 0x8200, 0xca24, 0x9fff, 0xca24, 0x21, 0 + .dw 0xa800, 0xca24, 0xbfff, 0xca24, 0x21, 0 + .dw 0xc200, 0xca24, 0xdfff, 0xca24, 0x21, 0 + .dw 0xe800, 0xca24, 0x1fff, 0xca28, 0x21, 0 + .dw 0x2040, 0xca28, 0x207f, 0xca28, 0x21, 0 + .dw 0x20c0, 0xca28, 0x20ff, 0xca28, 0x21, 0 + .dw 0x2140, 0xca28, 0x217f, 0xca28, 0x21, 0 + .dw 0x21c0, 0xca28, 0x21ff, 0xca28, 0x21, 0 + .dw 0x2240, 0xca28, 0x227f, 0xca28, 0x21, 0 + .dw 0x22c0, 0xca28, 0x22ff, 0xca28, 0x21, 0 + .dw 0x2340, 0xca28, 0x237f, 0xca28, 0x21, 0 + .dw 0x23c0, 0xca28, 0x23ff, 0xca28, 0x21, 0 + .dw 0x2440, 0xca28, 0x247f, 0xca28, 0x21, 0 + .dw 0x24c0, 0xca28, 0x24ff, 0xca28, 0x21, 0 + .dw 0x2540, 0xca28, 0x257f, 0xca28, 0x21, 0 + .dw 0x25c0, 0xca28, 0x25ff, 0xca28, 0x21, 0 + .dw 0x2640, 0xca28, 0x267f, 0xca28, 0x21, 0 + .dw 0x26c0, 0xca28, 0x26ff, 0xca28, 0x21, 0 + .dw 0x2740, 0xca28, 0x277f, 0xca28, 0x21, 0 + .dw 0x27c0, 0xca28, 0xffff, 0xca2b, 0x21, 0 + .dw 0x0040, 0xca2c, 0x007f, 0xca2c, 0x21, 0 + .dw 0x00c0, 0xca2c, 0x00ff, 0xca2c, 0x21, 0 + .dw 0x0140, 0xca2c, 0x017f, 0xca2c, 0x21, 0 + .dw 0x01c0, 0xca2c, 0x1fff, 0xca2c, 0x21, 0 + .dw 0x2040, 0xca2c, 0x207f, 0xca2c, 0x21, 0 + .dw 0x20c0, 0xca2c, 0x20ff, 0xca2c, 0x21, 0 + .dw 0x2140, 0xca2c, 0x217f, 0xca2c, 0x21, 0 + .dw 0x21c0, 0xca2c, 0x21ff, 0xca2c, 0x21, 0 + .dw 0x2240, 0xca2c, 0x227f, 0xca2c, 0x21, 0 + .dw 0x22c0, 0xca2c, 0x22ff, 0xca2c, 0x21, 0 + .dw 0x2340, 0xca2c, 0x237f, 0xca2c, 0x21, 0 + .dw 0x23c0, 0xca2c, 0x23ff, 0xca2c, 0x21, 0 + .dw 0x2440, 0xca2c, 0x247f, 0xca2c, 0x21, 0 + .dw 0x24c0, 0xca2c, 0x24ff, 0xca2c, 0x21, 0 + .dw 0x2540, 0xca2c, 0x257f, 0xca2c, 0x21, 0 + .dw 0x25c0, 0xca2c, 0x25ff, 0xca2c, 0x21, 0 + .dw 0x2640, 0xca2c, 0x267f, 0xca2c, 0x21, 0 + .dw 0x26c0, 0xca2c, 0x26ff, 0xca2c, 0x21, 0 + .dw 0x2740, 0xca2c, 0x277f, 0xca2c, 0x21, 0 + .dw 0x27c0, 0xca2c, 0x3fff, 0xca2c, 0x21, 0 + .dw 0x4040, 0xca2c, 0x407f, 0xca2c, 0x21, 0 + .dw 0x40c0, 0xca2c, 0x40ff, 0xca2c, 0x21, 0 + .dw 0x4140, 0xca2c, 0x417f, 0xca2c, 0x21, 0 + .dw 0x41c0, 0xca2c, 0x5fff, 0xca2c, 0x21, 0 + .dw 0x6040, 0xca2c, 0x607f, 0xca2c, 0x21, 0 + .dw 0x60c0, 0xca2c, 0x60ff, 0xca2c, 0x21, 0 + .dw 0x6140, 0xca2c, 0x617f, 0xca2c, 0x21, 0 + .dw 0x61c0, 0xca2c, 0x61ff, 0xca2c, 0x21, 0 + .dw 0x6240, 0xca2c, 0x627f, 0xca2c, 0x21, 0 + .dw 0x62c0, 0xca2c, 0x62ff, 0xca2c, 0x21, 0 + .dw 0x6340, 0xca2c, 0x637f, 0xca2c, 0x21, 0 + .dw 0x63c0, 0xca2c, 0x63ff, 0xca2c, 0x21, 0 + .dw 0x6440, 0xca2c, 0x647f, 0xca2c, 0x21, 0 + .dw 0x64c0, 0xca2c, 0x64ff, 0xca2c, 0x21, 0 + .dw 0x6540, 0xca2c, 0x657f, 0xca2c, 0x21, 0 + .dw 0x65c0, 0xca2c, 0x65ff, 0xca2c, 0x21, 0 + .dw 0x6640, 0xca2c, 0x667f, 0xca2c, 0x21, 0 + .dw 0x66c0, 0xca2c, 0x66ff, 0xca2c, 0x21, 0 + .dw 0x6740, 0xca2c, 0x677f, 0xca2c, 0x21, 0 + .dw 0x67c0, 0xca2c, 0x7fff, 0xca2c, 0x21, 0 + .dw 0x8040, 0xca2c, 0x807f, 0xca2c, 0x21, 0 + .dw 0x80c0, 0xca2c, 0x80ff, 0xca2c, 0x21, 0 + .dw 0x8140, 0xca2c, 0x817f, 0xca2c, 0x21, 0 + .dw 0x81c0, 0xca2c, 0x9fff, 0xca2c, 0x21, 0 + .dw 0xa040, 0xca2c, 0xa07f, 0xca2c, 0x21, 0 + .dw 0xa0c0, 0xca2c, 0xa0ff, 0xca2c, 0x21, 0 + .dw 0xa140, 0xca2c, 0xa17f, 0xca2c, 0x21, 0 + .dw 0xa1c0, 0xca2c, 0xa1ff, 0xca2c, 0x21, 0 + .dw 0xa240, 0xca2c, 0xa27f, 0xca2c, 0x21, 0 + .dw 0xa2c0, 0xca2c, 0xa2ff, 0xca2c, 0x21, 0 + .dw 0xa340, 0xca2c, 0xa37f, 0xca2c, 0x21, 0 + .dw 0xa3c0, 0xca2c, 0xa3ff, 0xca2c, 0x21, 0 + .dw 0xa440, 0xca2c, 0xa47f, 0xca2c, 0x21, 0 + .dw 0xa4c0, 0xca2c, 0xa4ff, 0xca2c, 0x21, 0 + .dw 0xa540, 0xca2c, 0xa57f, 0xca2c, 0x21, 0 + .dw 0xa5c0, 0xca2c, 0xa5ff, 0xca2c, 0x21, 0 + .dw 0xa640, 0xca2c, 0xa67f, 0xca2c, 0x21, 0 + .dw 0xa6c0, 0xca2c, 0xa6ff, 0xca2c, 0x21, 0 + .dw 0xa740, 0xca2c, 0xa77f, 0xca2c, 0x21, 0 + .dw 0xa7c0, 0xca2c, 0xbfff, 0xca2c, 0x21, 0 + .dw 0xc040, 0xca2c, 0xc07f, 0xca2c, 0x21, 0 + .dw 0xc0c0, 0xca2c, 0xc0ff, 0xca2c, 0x21, 0 + .dw 0xc140, 0xca2c, 0xc17f, 0xca2c, 0x21, 0 + .dw 0xc1c0, 0xca2c, 0xdfff, 0xca2c, 0x21, 0 + .dw 0xe040, 0xca2c, 0xe07f, 0xca2c, 0x21, 0 + .dw 0xe0c0, 0xca2c, 0xe0ff, 0xca2c, 0x21, 0 + .dw 0xe140, 0xca2c, 0xe17f, 0xca2c, 0x21, 0 + .dw 0xe1c0, 0xca2c, 0xe1ff, 0xca2c, 0x21, 0 + .dw 0xe240, 0xca2c, 0xe27f, 0xca2c, 0x21, 0 + .dw 0xe2c0, 0xca2c, 0xe2ff, 0xca2c, 0x21, 0 + .dw 0xe340, 0xca2c, 0xe37f, 0xca2c, 0x21, 0 + .dw 0xe3c0, 0xca2c, 0xe3ff, 0xca2c, 0x21, 0 + .dw 0xe440, 0xca2c, 0xe47f, 0xca2c, 0x21, 0 + .dw 0xe4c0, 0xca2c, 0xe4ff, 0xca2c, 0x21, 0 + .dw 0xe540, 0xca2c, 0xe57f, 0xca2c, 0x21, 0 + .dw 0xe5c0, 0xca2c, 0xe5ff, 0xca2c, 0x21, 0 + .dw 0xe640, 0xca2c, 0xe67f, 0xca2c, 0x21, 0 + .dw 0xe6c0, 0xca2c, 0xe6ff, 0xca2c, 0x21, 0 + .dw 0xe740, 0xca2c, 0xe77f, 0xca2c, 0x21, 0 + .dw 0xe7c0, 0xca2c, 0xffff, 0xca33, 0x21, 0 + .dw 0x0200, 0xca34, 0x1fff, 0xca34, 0x21, 0 + .dw 0x2800, 0xca34, 0x3fff, 0xca34, 0x21, 0 + .dw 0x4200, 0xca34, 0x5fff, 0xca34, 0x21, 0 + .dw 0x6800, 0xca34, 0x7fff, 0xca34, 0x21, 0 + .dw 0x8200, 0xca34, 0x9fff, 0xca34, 0x21, 0 + .dw 0xa800, 0xca34, 0xbfff, 0xca34, 0x21, 0 + .dw 0xc200, 0xca34, 0xdfff, 0xca34, 0x21, 0 + .dw 0xe800, 0xca34, 0xffff, 0xca3b, 0x21, 0 + .dw 0x0040, 0xca3c, 0x007f, 0xca3c, 0x21, 0 + .dw 0x00c0, 0xca3c, 0x00ff, 0xca3c, 0x21, 0 + .dw 0x0140, 0xca3c, 0x017f, 0xca3c, 0x21, 0 + .dw 0x01c0, 0xca3c, 0x1fff, 0xca3c, 0x21, 0 + .dw 0x2040, 0xca3c, 0x207f, 0xca3c, 0x21, 0 + .dw 0x20c0, 0xca3c, 0x20ff, 0xca3c, 0x21, 0 + .dw 0x2140, 0xca3c, 0x217f, 0xca3c, 0x21, 0 + .dw 0x21c0, 0xca3c, 0x21ff, 0xca3c, 0x21, 0 + .dw 0x2240, 0xca3c, 0x227f, 0xca3c, 0x21, 0 + .dw 0x22c0, 0xca3c, 0x22ff, 0xca3c, 0x21, 0 + .dw 0x2340, 0xca3c, 0x237f, 0xca3c, 0x21, 0 + .dw 0x23c0, 0xca3c, 0x23ff, 0xca3c, 0x21, 0 + .dw 0x2440, 0xca3c, 0x247f, 0xca3c, 0x21, 0 + .dw 0x24c0, 0xca3c, 0x24ff, 0xca3c, 0x21, 0 + .dw 0x2540, 0xca3c, 0x257f, 0xca3c, 0x21, 0 + .dw 0x25c0, 0xca3c, 0x25ff, 0xca3c, 0x21, 0 + .dw 0x2640, 0xca3c, 0x267f, 0xca3c, 0x21, 0 + .dw 0x26c0, 0xca3c, 0x26ff, 0xca3c, 0x21, 0 + .dw 0x2740, 0xca3c, 0x277f, 0xca3c, 0x21, 0 + .dw 0x27c0, 0xca3c, 0x3fff, 0xca3c, 0x21, 0 + .dw 0x4040, 0xca3c, 0x407f, 0xca3c, 0x21, 0 + .dw 0x40c0, 0xca3c, 0x40ff, 0xca3c, 0x21, 0 + .dw 0x4140, 0xca3c, 0x417f, 0xca3c, 0x21, 0 + .dw 0x41c0, 0xca3c, 0x5fff, 0xca3c, 0x21, 0 + .dw 0x6040, 0xca3c, 0x607f, 0xca3c, 0x21, 0 + .dw 0x60c0, 0xca3c, 0x60ff, 0xca3c, 0x21, 0 + .dw 0x6140, 0xca3c, 0x617f, 0xca3c, 0x21, 0 + .dw 0x61c0, 0xca3c, 0x61ff, 0xca3c, 0x21, 0 + .dw 0x6240, 0xca3c, 0x627f, 0xca3c, 0x21, 0 + .dw 0x62c0, 0xca3c, 0x62ff, 0xca3c, 0x21, 0 + .dw 0x6340, 0xca3c, 0x637f, 0xca3c, 0x21, 0 + .dw 0x63c0, 0xca3c, 0x63ff, 0xca3c, 0x21, 0 + .dw 0x6440, 0xca3c, 0x647f, 0xca3c, 0x21, 0 + .dw 0x64c0, 0xca3c, 0x64ff, 0xca3c, 0x21, 0 + .dw 0x6540, 0xca3c, 0x657f, 0xca3c, 0x21, 0 + .dw 0x65c0, 0xca3c, 0x65ff, 0xca3c, 0x21, 0 + .dw 0x6640, 0xca3c, 0x667f, 0xca3c, 0x21, 0 + .dw 0x66c0, 0xca3c, 0x66ff, 0xca3c, 0x21, 0 + .dw 0x6740, 0xca3c, 0x677f, 0xca3c, 0x21, 0 + .dw 0x67c0, 0xca3c, 0x7fff, 0xca3c, 0x21, 0 + .dw 0x8040, 0xca3c, 0x807f, 0xca3c, 0x21, 0 + .dw 0x80c0, 0xca3c, 0x80ff, 0xca3c, 0x21, 0 + .dw 0x8140, 0xca3c, 0x817f, 0xca3c, 0x21, 0 + .dw 0x81c0, 0xca3c, 0x9fff, 0xca3c, 0x21, 0 + .dw 0xa040, 0xca3c, 0xa07f, 0xca3c, 0x21, 0 + .dw 0xa0c0, 0xca3c, 0xa0ff, 0xca3c, 0x21, 0 + .dw 0xa140, 0xca3c, 0xa17f, 0xca3c, 0x21, 0 + .dw 0xa1c0, 0xca3c, 0xa1ff, 0xca3c, 0x21, 0 + .dw 0xa240, 0xca3c, 0xa27f, 0xca3c, 0x21, 0 + .dw 0xa2c0, 0xca3c, 0xa2ff, 0xca3c, 0x21, 0 + .dw 0xa340, 0xca3c, 0xa37f, 0xca3c, 0x21, 0 + .dw 0xa3c0, 0xca3c, 0xa3ff, 0xca3c, 0x21, 0 + .dw 0xa440, 0xca3c, 0xa47f, 0xca3c, 0x21, 0 + .dw 0xa4c0, 0xca3c, 0xa4ff, 0xca3c, 0x21, 0 + .dw 0xa540, 0xca3c, 0xa57f, 0xca3c, 0x21, 0 + .dw 0xa5c0, 0xca3c, 0xa5ff, 0xca3c, 0x21, 0 + .dw 0xa640, 0xca3c, 0xa67f, 0xca3c, 0x21, 0 + .dw 0xa6c0, 0xca3c, 0xa6ff, 0xca3c, 0x21, 0 + .dw 0xa740, 0xca3c, 0xa77f, 0xca3c, 0x21, 0 + .dw 0xa7c0, 0xca3c, 0xbfff, 0xca3c, 0x21, 0 + .dw 0xc040, 0xca3c, 0xc07f, 0xca3c, 0x21, 0 + .dw 0xc0c0, 0xca3c, 0xc0ff, 0xca3c, 0x21, 0 + .dw 0xc140, 0xca3c, 0xc17f, 0xca3c, 0x21, 0 + .dw 0xc1c0, 0xca3c, 0xdfff, 0xca3c, 0x21, 0 + .dw 0xe040, 0xca3c, 0xe07f, 0xca3c, 0x21, 0 + .dw 0xe0c0, 0xca3c, 0xe0ff, 0xca3c, 0x21, 0 + .dw 0xe140, 0xca3c, 0xe17f, 0xca3c, 0x21, 0 + .dw 0xe1c0, 0xca3c, 0xe1ff, 0xca3c, 0x21, 0 + .dw 0xe240, 0xca3c, 0xe27f, 0xca3c, 0x21, 0 + .dw 0xe2c0, 0xca3c, 0xe2ff, 0xca3c, 0x21, 0 + .dw 0xe340, 0xca3c, 0xe37f, 0xca3c, 0x21, 0 + .dw 0xe3c0, 0xca3c, 0xe3ff, 0xca3c, 0x21, 0 + .dw 0xe440, 0xca3c, 0xe47f, 0xca3c, 0x21, 0 + .dw 0xe4c0, 0xca3c, 0xe4ff, 0xca3c, 0x21, 0 + .dw 0xe540, 0xca3c, 0xe57f, 0xca3c, 0x21, 0 + .dw 0xe5c0, 0xca3c, 0xe5ff, 0xca3c, 0x21, 0 + .dw 0xe640, 0xca3c, 0xe67f, 0xca3c, 0x21, 0 + .dw 0xe6c0, 0xca3c, 0xe6ff, 0xca3c, 0x21, 0 + .dw 0xe740, 0xca3c, 0xe77f, 0xca3c, 0x21, 0 + .dw 0xe7c0, 0xca3c, 0x1fff, 0xca40, 0x21, 0 + .dw 0x2800, 0xca40, 0xffff, 0xca43, 0x21, 0 + .dw 0x0200, 0xca44, 0x1fff, 0xca44, 0x21, 0 + .dw 0x2800, 0xca44, 0x3fff, 0xca44, 0x21, 0 + .dw 0x4200, 0xca44, 0x5fff, 0xca44, 0x21, 0 + .dw 0x6800, 0xca44, 0x7fff, 0xca44, 0x21, 0 + .dw 0x8200, 0xca44, 0x9fff, 0xca44, 0x21, 0 + .dw 0xa800, 0xca44, 0xbfff, 0xca44, 0x21, 0 + .dw 0xc200, 0xca44, 0xdfff, 0xca44, 0x21, 0 + .dw 0xe800, 0xca44, 0xffff, 0xca53, 0x21, 0 + .dw 0x0200, 0xca54, 0x1fff, 0xca54, 0x21, 0 + .dw 0x2800, 0xca54, 0x3fff, 0xca54, 0x21, 0 + .dw 0x4200, 0xca54, 0x5fff, 0xca54, 0x21, 0 + .dw 0x6800, 0xca54, 0x7fff, 0xca54, 0x21, 0 + .dw 0x8200, 0xca54, 0x9fff, 0xca54, 0x21, 0 + .dw 0xa800, 0xca54, 0xbfff, 0xca54, 0x21, 0 + .dw 0xc200, 0xca54, 0xdfff, 0xca54, 0x21, 0 + .dw 0xe800, 0xca54, 0x1fff, 0xca80, 0x21, 0 + .dw 0x2800, 0xca80, 0xffff, 0xca83, 0x21, 0 + .dw 0x0200, 0xca84, 0x1fff, 0xca84, 0x21, 0 + .dw 0x2800, 0xca84, 0x3fff, 0xca84, 0x21, 0 + .dw 0x4200, 0xca84, 0x5fff, 0xca84, 0x21, 0 + .dw 0x6800, 0xca84, 0x7fff, 0xca84, 0x21, 0 + .dw 0x8200, 0xca84, 0x9fff, 0xca84, 0x21, 0 + .dw 0xa800, 0xca84, 0xbfff, 0xca84, 0x21, 0 + .dw 0xc200, 0xca84, 0xdfff, 0xca84, 0x21, 0 + .dw 0xe800, 0xca84, 0x1fff, 0xca88, 0x21, 0 + .dw 0x2040, 0xca88, 0x207f, 0xca88, 0x21, 0 + .dw 0x20c0, 0xca88, 0x20ff, 0xca88, 0x21, 0 + .dw 0x2140, 0xca88, 0x217f, 0xca88, 0x21, 0 + .dw 0x21c0, 0xca88, 0x21ff, 0xca88, 0x21, 0 + .dw 0x2240, 0xca88, 0x227f, 0xca88, 0x21, 0 + .dw 0x22c0, 0xca88, 0x22ff, 0xca88, 0x21, 0 + .dw 0x2340, 0xca88, 0x237f, 0xca88, 0x21, 0 + .dw 0x23c0, 0xca88, 0x23ff, 0xca88, 0x21, 0 + .dw 0x2440, 0xca88, 0x247f, 0xca88, 0x21, 0 + .dw 0x24c0, 0xca88, 0x24ff, 0xca88, 0x21, 0 + .dw 0x2540, 0xca88, 0x257f, 0xca88, 0x21, 0 + .dw 0x25c0, 0xca88, 0x25ff, 0xca88, 0x21, 0 + .dw 0x2640, 0xca88, 0x267f, 0xca88, 0x21, 0 + .dw 0x26c0, 0xca88, 0x26ff, 0xca88, 0x21, 0 + .dw 0x2740, 0xca88, 0x277f, 0xca88, 0x21, 0 + .dw 0x27c0, 0xca88, 0xffff, 0xca8b, 0x21, 0 + .dw 0x0040, 0xca8c, 0x007f, 0xca8c, 0x21, 0 + .dw 0x00c0, 0xca8c, 0x00ff, 0xca8c, 0x21, 0 + .dw 0x0140, 0xca8c, 0x017f, 0xca8c, 0x21, 0 + .dw 0x01c0, 0xca8c, 0x1fff, 0xca8c, 0x21, 0 + .dw 0x2040, 0xca8c, 0x207f, 0xca8c, 0x21, 0 + .dw 0x20c0, 0xca8c, 0x20ff, 0xca8c, 0x21, 0 + .dw 0x2140, 0xca8c, 0x217f, 0xca8c, 0x21, 0 + .dw 0x21c0, 0xca8c, 0x21ff, 0xca8c, 0x21, 0 + .dw 0x2240, 0xca8c, 0x227f, 0xca8c, 0x21, 0 + .dw 0x22c0, 0xca8c, 0x22ff, 0xca8c, 0x21, 0 + .dw 0x2340, 0xca8c, 0x237f, 0xca8c, 0x21, 0 + .dw 0x23c0, 0xca8c, 0x23ff, 0xca8c, 0x21, 0 + .dw 0x2440, 0xca8c, 0x247f, 0xca8c, 0x21, 0 + .dw 0x24c0, 0xca8c, 0x24ff, 0xca8c, 0x21, 0 + .dw 0x2540, 0xca8c, 0x257f, 0xca8c, 0x21, 0 + .dw 0x25c0, 0xca8c, 0x25ff, 0xca8c, 0x21, 0 + .dw 0x2640, 0xca8c, 0x267f, 0xca8c, 0x21, 0 + .dw 0x26c0, 0xca8c, 0x26ff, 0xca8c, 0x21, 0 + .dw 0x2740, 0xca8c, 0x277f, 0xca8c, 0x21, 0 + .dw 0x27c0, 0xca8c, 0x3fff, 0xca8c, 0x21, 0 + .dw 0x4040, 0xca8c, 0x407f, 0xca8c, 0x21, 0 + .dw 0x40c0, 0xca8c, 0x40ff, 0xca8c, 0x21, 0 + .dw 0x4140, 0xca8c, 0x417f, 0xca8c, 0x21, 0 + .dw 0x41c0, 0xca8c, 0x5fff, 0xca8c, 0x21, 0 + .dw 0x6040, 0xca8c, 0x607f, 0xca8c, 0x21, 0 + .dw 0x60c0, 0xca8c, 0x60ff, 0xca8c, 0x21, 0 + .dw 0x6140, 0xca8c, 0x617f, 0xca8c, 0x21, 0 + .dw 0x61c0, 0xca8c, 0x61ff, 0xca8c, 0x21, 0 + .dw 0x6240, 0xca8c, 0x627f, 0xca8c, 0x21, 0 + .dw 0x62c0, 0xca8c, 0x62ff, 0xca8c, 0x21, 0 + .dw 0x6340, 0xca8c, 0x637f, 0xca8c, 0x21, 0 + .dw 0x63c0, 0xca8c, 0x63ff, 0xca8c, 0x21, 0 + .dw 0x6440, 0xca8c, 0x647f, 0xca8c, 0x21, 0 + .dw 0x64c0, 0xca8c, 0x64ff, 0xca8c, 0x21, 0 + .dw 0x6540, 0xca8c, 0x657f, 0xca8c, 0x21, 0 + .dw 0x65c0, 0xca8c, 0x65ff, 0xca8c, 0x21, 0 + .dw 0x6640, 0xca8c, 0x667f, 0xca8c, 0x21, 0 + .dw 0x66c0, 0xca8c, 0x66ff, 0xca8c, 0x21, 0 + .dw 0x6740, 0xca8c, 0x677f, 0xca8c, 0x21, 0 + .dw 0x67c0, 0xca8c, 0x7fff, 0xca8c, 0x21, 0 + .dw 0x8040, 0xca8c, 0x807f, 0xca8c, 0x21, 0 + .dw 0x80c0, 0xca8c, 0x80ff, 0xca8c, 0x21, 0 + .dw 0x8140, 0xca8c, 0x817f, 0xca8c, 0x21, 0 + .dw 0x81c0, 0xca8c, 0x9fff, 0xca8c, 0x21, 0 + .dw 0xa040, 0xca8c, 0xa07f, 0xca8c, 0x21, 0 + .dw 0xa0c0, 0xca8c, 0xa0ff, 0xca8c, 0x21, 0 + .dw 0xa140, 0xca8c, 0xa17f, 0xca8c, 0x21, 0 + .dw 0xa1c0, 0xca8c, 0xa1ff, 0xca8c, 0x21, 0 + .dw 0xa240, 0xca8c, 0xa27f, 0xca8c, 0x21, 0 + .dw 0xa2c0, 0xca8c, 0xa2ff, 0xca8c, 0x21, 0 + .dw 0xa340, 0xca8c, 0xa37f, 0xca8c, 0x21, 0 + .dw 0xa3c0, 0xca8c, 0xa3ff, 0xca8c, 0x21, 0 + .dw 0xa440, 0xca8c, 0xa47f, 0xca8c, 0x21, 0 + .dw 0xa4c0, 0xca8c, 0xa4ff, 0xca8c, 0x21, 0 + .dw 0xa540, 0xca8c, 0xa57f, 0xca8c, 0x21, 0 + .dw 0xa5c0, 0xca8c, 0xa5ff, 0xca8c, 0x21, 0 + .dw 0xa640, 0xca8c, 0xa67f, 0xca8c, 0x21, 0 + .dw 0xa6c0, 0xca8c, 0xa6ff, 0xca8c, 0x21, 0 + .dw 0xa740, 0xca8c, 0xa77f, 0xca8c, 0x21, 0 + .dw 0xa7c0, 0xca8c, 0xbfff, 0xca8c, 0x21, 0 + .dw 0xc040, 0xca8c, 0xc07f, 0xca8c, 0x21, 0 + .dw 0xc0c0, 0xca8c, 0xc0ff, 0xca8c, 0x21, 0 + .dw 0xc140, 0xca8c, 0xc17f, 0xca8c, 0x21, 0 + .dw 0xc1c0, 0xca8c, 0xdfff, 0xca8c, 0x21, 0 + .dw 0xe040, 0xca8c, 0xe07f, 0xca8c, 0x21, 0 + .dw 0xe0c0, 0xca8c, 0xe0ff, 0xca8c, 0x21, 0 + .dw 0xe140, 0xca8c, 0xe17f, 0xca8c, 0x21, 0 + .dw 0xe1c0, 0xca8c, 0xe1ff, 0xca8c, 0x21, 0 + .dw 0xe240, 0xca8c, 0xe27f, 0xca8c, 0x21, 0 + .dw 0xe2c0, 0xca8c, 0xe2ff, 0xca8c, 0x21, 0 + .dw 0xe340, 0xca8c, 0xe37f, 0xca8c, 0x21, 0 + .dw 0xe3c0, 0xca8c, 0xe3ff, 0xca8c, 0x21, 0 + .dw 0xe440, 0xca8c, 0xe47f, 0xca8c, 0x21, 0 + .dw 0xe4c0, 0xca8c, 0xe4ff, 0xca8c, 0x21, 0 + .dw 0xe540, 0xca8c, 0xe57f, 0xca8c, 0x21, 0 + .dw 0xe5c0, 0xca8c, 0xe5ff, 0xca8c, 0x21, 0 + .dw 0xe640, 0xca8c, 0xe67f, 0xca8c, 0x21, 0 + .dw 0xe6c0, 0xca8c, 0xe6ff, 0xca8c, 0x21, 0 + .dw 0xe740, 0xca8c, 0xe77f, 0xca8c, 0x21, 0 + .dw 0xe7c0, 0xca8c, 0xffff, 0xca93, 0x21, 0 + .dw 0x0200, 0xca94, 0x1fff, 0xca94, 0x21, 0 + .dw 0x2800, 0xca94, 0x3fff, 0xca94, 0x21, 0 + .dw 0x4200, 0xca94, 0x5fff, 0xca94, 0x21, 0 + .dw 0x6800, 0xca94, 0x7fff, 0xca94, 0x21, 0 + .dw 0x8200, 0xca94, 0x9fff, 0xca94, 0x21, 0 + .dw 0xa800, 0xca94, 0xbfff, 0xca94, 0x21, 0 + .dw 0xc200, 0xca94, 0xdfff, 0xca94, 0x21, 0 + .dw 0xe800, 0xca94, 0xffff, 0xca9b, 0x21, 0 + .dw 0x0040, 0xca9c, 0x007f, 0xca9c, 0x21, 0 + .dw 0x00c0, 0xca9c, 0x00ff, 0xca9c, 0x21, 0 + .dw 0x0140, 0xca9c, 0x017f, 0xca9c, 0x21, 0 + .dw 0x01c0, 0xca9c, 0x1fff, 0xca9c, 0x21, 0 + .dw 0x2040, 0xca9c, 0x207f, 0xca9c, 0x21, 0 + .dw 0x20c0, 0xca9c, 0x20ff, 0xca9c, 0x21, 0 + .dw 0x2140, 0xca9c, 0x217f, 0xca9c, 0x21, 0 + .dw 0x21c0, 0xca9c, 0x21ff, 0xca9c, 0x21, 0 + .dw 0x2240, 0xca9c, 0x227f, 0xca9c, 0x21, 0 + .dw 0x22c0, 0xca9c, 0x22ff, 0xca9c, 0x21, 0 + .dw 0x2340, 0xca9c, 0x237f, 0xca9c, 0x21, 0 + .dw 0x23c0, 0xca9c, 0x23ff, 0xca9c, 0x21, 0 + .dw 0x2440, 0xca9c, 0x247f, 0xca9c, 0x21, 0 + .dw 0x24c0, 0xca9c, 0x24ff, 0xca9c, 0x21, 0 + .dw 0x2540, 0xca9c, 0x257f, 0xca9c, 0x21, 0 + .dw 0x25c0, 0xca9c, 0x25ff, 0xca9c, 0x21, 0 + .dw 0x2640, 0xca9c, 0x267f, 0xca9c, 0x21, 0 + .dw 0x26c0, 0xca9c, 0x26ff, 0xca9c, 0x21, 0 + .dw 0x2740, 0xca9c, 0x277f, 0xca9c, 0x21, 0 + .dw 0x27c0, 0xca9c, 0x3fff, 0xca9c, 0x21, 0 + .dw 0x4040, 0xca9c, 0x407f, 0xca9c, 0x21, 0 + .dw 0x40c0, 0xca9c, 0x40ff, 0xca9c, 0x21, 0 + .dw 0x4140, 0xca9c, 0x417f, 0xca9c, 0x21, 0 + .dw 0x41c0, 0xca9c, 0x5fff, 0xca9c, 0x21, 0 + .dw 0x6040, 0xca9c, 0x607f, 0xca9c, 0x21, 0 + .dw 0x60c0, 0xca9c, 0x60ff, 0xca9c, 0x21, 0 + .dw 0x6140, 0xca9c, 0x617f, 0xca9c, 0x21, 0 + .dw 0x61c0, 0xca9c, 0x61ff, 0xca9c, 0x21, 0 + .dw 0x6240, 0xca9c, 0x627f, 0xca9c, 0x21, 0 + .dw 0x62c0, 0xca9c, 0x62ff, 0xca9c, 0x21, 0 + .dw 0x6340, 0xca9c, 0x637f, 0xca9c, 0x21, 0 + .dw 0x63c0, 0xca9c, 0x63ff, 0xca9c, 0x21, 0 + .dw 0x6440, 0xca9c, 0x647f, 0xca9c, 0x21, 0 + .dw 0x64c0, 0xca9c, 0x64ff, 0xca9c, 0x21, 0 + .dw 0x6540, 0xca9c, 0x657f, 0xca9c, 0x21, 0 + .dw 0x65c0, 0xca9c, 0x65ff, 0xca9c, 0x21, 0 + .dw 0x6640, 0xca9c, 0x667f, 0xca9c, 0x21, 0 + .dw 0x66c0, 0xca9c, 0x66ff, 0xca9c, 0x21, 0 + .dw 0x6740, 0xca9c, 0x677f, 0xca9c, 0x21, 0 + .dw 0x67c0, 0xca9c, 0x7fff, 0xca9c, 0x21, 0 + .dw 0x8040, 0xca9c, 0x807f, 0xca9c, 0x21, 0 + .dw 0x80c0, 0xca9c, 0x80ff, 0xca9c, 0x21, 0 + .dw 0x8140, 0xca9c, 0x817f, 0xca9c, 0x21, 0 + .dw 0x81c0, 0xca9c, 0x9fff, 0xca9c, 0x21, 0 + .dw 0xa040, 0xca9c, 0xa07f, 0xca9c, 0x21, 0 + .dw 0xa0c0, 0xca9c, 0xa0ff, 0xca9c, 0x21, 0 + .dw 0xa140, 0xca9c, 0xa17f, 0xca9c, 0x21, 0 + .dw 0xa1c0, 0xca9c, 0xa1ff, 0xca9c, 0x21, 0 + .dw 0xa240, 0xca9c, 0xa27f, 0xca9c, 0x21, 0 + .dw 0xa2c0, 0xca9c, 0xa2ff, 0xca9c, 0x21, 0 + .dw 0xa340, 0xca9c, 0xa37f, 0xca9c, 0x21, 0 + .dw 0xa3c0, 0xca9c, 0xa3ff, 0xca9c, 0x21, 0 + .dw 0xa440, 0xca9c, 0xa47f, 0xca9c, 0x21, 0 + .dw 0xa4c0, 0xca9c, 0xa4ff, 0xca9c, 0x21, 0 + .dw 0xa540, 0xca9c, 0xa57f, 0xca9c, 0x21, 0 + .dw 0xa5c0, 0xca9c, 0xa5ff, 0xca9c, 0x21, 0 + .dw 0xa640, 0xca9c, 0xa67f, 0xca9c, 0x21, 0 + .dw 0xa6c0, 0xca9c, 0xa6ff, 0xca9c, 0x21, 0 + .dw 0xa740, 0xca9c, 0xa77f, 0xca9c, 0x21, 0 + .dw 0xa7c0, 0xca9c, 0xbfff, 0xca9c, 0x21, 0 + .dw 0xc040, 0xca9c, 0xc07f, 0xca9c, 0x21, 0 + .dw 0xc0c0, 0xca9c, 0xc0ff, 0xca9c, 0x21, 0 + .dw 0xc140, 0xca9c, 0xc17f, 0xca9c, 0x21, 0 + .dw 0xc1c0, 0xca9c, 0xdfff, 0xca9c, 0x21, 0 + .dw 0xe040, 0xca9c, 0xe07f, 0xca9c, 0x21, 0 + .dw 0xe0c0, 0xca9c, 0xe0ff, 0xca9c, 0x21, 0 + .dw 0xe140, 0xca9c, 0xe17f, 0xca9c, 0x21, 0 + .dw 0xe1c0, 0xca9c, 0xe1ff, 0xca9c, 0x21, 0 + .dw 0xe240, 0xca9c, 0xe27f, 0xca9c, 0x21, 0 + .dw 0xe2c0, 0xca9c, 0xe2ff, 0xca9c, 0x21, 0 + .dw 0xe340, 0xca9c, 0xe37f, 0xca9c, 0x21, 0 + .dw 0xe3c0, 0xca9c, 0xe3ff, 0xca9c, 0x21, 0 + .dw 0xe440, 0xca9c, 0xe47f, 0xca9c, 0x21, 0 + .dw 0xe4c0, 0xca9c, 0xe4ff, 0xca9c, 0x21, 0 + .dw 0xe540, 0xca9c, 0xe57f, 0xca9c, 0x21, 0 + .dw 0xe5c0, 0xca9c, 0xe5ff, 0xca9c, 0x21, 0 + .dw 0xe640, 0xca9c, 0xe67f, 0xca9c, 0x21, 0 + .dw 0xe6c0, 0xca9c, 0xe6ff, 0xca9c, 0x21, 0 + .dw 0xe740, 0xca9c, 0xe77f, 0xca9c, 0x21, 0 + .dw 0xe7c0, 0xca9c, 0x1fff, 0xcac0, 0x21, 0 + .dw 0x2800, 0xcac0, 0xffff, 0xcac3, 0x21, 0 + .dw 0x0200, 0xcac4, 0x1fff, 0xcac4, 0x21, 0 + .dw 0x2800, 0xcac4, 0x3fff, 0xcac4, 0x21, 0 + .dw 0x4200, 0xcac4, 0x5fff, 0xcac4, 0x21, 0 + .dw 0x6800, 0xcac4, 0x7fff, 0xcac4, 0x21, 0 + .dw 0x8200, 0xcac4, 0x9fff, 0xcac4, 0x21, 0 + .dw 0xa800, 0xcac4, 0xbfff, 0xcac4, 0x21, 0 + .dw 0xc200, 0xcac4, 0xdfff, 0xcac4, 0x21, 0 + .dw 0xe800, 0xcac4, 0xffff, 0xcad3, 0x21, 0 + .dw 0x0200, 0xcad4, 0x1fff, 0xcad4, 0x21, 0 + .dw 0x2800, 0xcad4, 0x3fff, 0xcad4, 0x21, 0 + .dw 0x4200, 0xcad4, 0x5fff, 0xcad4, 0x21, 0 + .dw 0x6800, 0xcad4, 0x7fff, 0xcad4, 0x21, 0 + .dw 0x8200, 0xcad4, 0x9fff, 0xcad4, 0x21, 0 + .dw 0xa800, 0xcad4, 0xbfff, 0xcad4, 0x21, 0 + .dw 0xc200, 0xcad4, 0xdfff, 0xcad4, 0x21, 0 + .dw 0xe800, 0xcad4, 0x1fff, 0xcb00, 0x21, 0 + .dw 0x2800, 0xcb00, 0xffff, 0xcb03, 0x21, 0 + .dw 0x0200, 0xcb04, 0x1fff, 0xcb04, 0x21, 0 + .dw 0x2800, 0xcb04, 0x3fff, 0xcb04, 0x21, 0 + .dw 0x4200, 0xcb04, 0x5fff, 0xcb04, 0x21, 0 + .dw 0x6800, 0xcb04, 0x7fff, 0xcb04, 0x21, 0 + .dw 0x8200, 0xcb04, 0x9fff, 0xcb04, 0x21, 0 + .dw 0xa800, 0xcb04, 0xbfff, 0xcb04, 0x21, 0 + .dw 0xc200, 0xcb04, 0xdfff, 0xcb04, 0x21, 0 + .dw 0xe800, 0xcb04, 0x1fff, 0xcb08, 0x21, 0 + .dw 0x2040, 0xcb08, 0x207f, 0xcb08, 0x21, 0 + .dw 0x20c0, 0xcb08, 0x20ff, 0xcb08, 0x21, 0 + .dw 0x2140, 0xcb08, 0x217f, 0xcb08, 0x21, 0 + .dw 0x21c0, 0xcb08, 0x21ff, 0xcb08, 0x21, 0 + .dw 0x2240, 0xcb08, 0x227f, 0xcb08, 0x21, 0 + .dw 0x22c0, 0xcb08, 0x22ff, 0xcb08, 0x21, 0 + .dw 0x2340, 0xcb08, 0x237f, 0xcb08, 0x21, 0 + .dw 0x23c0, 0xcb08, 0x23ff, 0xcb08, 0x21, 0 + .dw 0x2440, 0xcb08, 0x247f, 0xcb08, 0x21, 0 + .dw 0x24c0, 0xcb08, 0x24ff, 0xcb08, 0x21, 0 + .dw 0x2540, 0xcb08, 0x257f, 0xcb08, 0x21, 0 + .dw 0x25c0, 0xcb08, 0x25ff, 0xcb08, 0x21, 0 + .dw 0x2640, 0xcb08, 0x267f, 0xcb08, 0x21, 0 + .dw 0x26c0, 0xcb08, 0x26ff, 0xcb08, 0x21, 0 + .dw 0x2740, 0xcb08, 0x277f, 0xcb08, 0x21, 0 + .dw 0x27c0, 0xcb08, 0xffff, 0xcb0b, 0x21, 0 + .dw 0x0040, 0xcb0c, 0x007f, 0xcb0c, 0x21, 0 + .dw 0x00c0, 0xcb0c, 0x00ff, 0xcb0c, 0x21, 0 + .dw 0x0140, 0xcb0c, 0x017f, 0xcb0c, 0x21, 0 + .dw 0x01c0, 0xcb0c, 0x1fff, 0xcb0c, 0x21, 0 + .dw 0x2040, 0xcb0c, 0x207f, 0xcb0c, 0x21, 0 + .dw 0x20c0, 0xcb0c, 0x20ff, 0xcb0c, 0x21, 0 + .dw 0x2140, 0xcb0c, 0x217f, 0xcb0c, 0x21, 0 + .dw 0x21c0, 0xcb0c, 0x21ff, 0xcb0c, 0x21, 0 + .dw 0x2240, 0xcb0c, 0x227f, 0xcb0c, 0x21, 0 + .dw 0x22c0, 0xcb0c, 0x22ff, 0xcb0c, 0x21, 0 + .dw 0x2340, 0xcb0c, 0x237f, 0xcb0c, 0x21, 0 + .dw 0x23c0, 0xcb0c, 0x23ff, 0xcb0c, 0x21, 0 + .dw 0x2440, 0xcb0c, 0x247f, 0xcb0c, 0x21, 0 + .dw 0x24c0, 0xcb0c, 0x24ff, 0xcb0c, 0x21, 0 + .dw 0x2540, 0xcb0c, 0x257f, 0xcb0c, 0x21, 0 + .dw 0x25c0, 0xcb0c, 0x25ff, 0xcb0c, 0x21, 0 + .dw 0x2640, 0xcb0c, 0x267f, 0xcb0c, 0x21, 0 + .dw 0x26c0, 0xcb0c, 0x26ff, 0xcb0c, 0x21, 0 + .dw 0x2740, 0xcb0c, 0x277f, 0xcb0c, 0x21, 0 + .dw 0x27c0, 0xcb0c, 0x3fff, 0xcb0c, 0x21, 0 + .dw 0x4040, 0xcb0c, 0x407f, 0xcb0c, 0x21, 0 + .dw 0x40c0, 0xcb0c, 0x40ff, 0xcb0c, 0x21, 0 + .dw 0x4140, 0xcb0c, 0x417f, 0xcb0c, 0x21, 0 + .dw 0x41c0, 0xcb0c, 0x5fff, 0xcb0c, 0x21, 0 + .dw 0x6040, 0xcb0c, 0x607f, 0xcb0c, 0x21, 0 + .dw 0x60c0, 0xcb0c, 0x60ff, 0xcb0c, 0x21, 0 + .dw 0x6140, 0xcb0c, 0x617f, 0xcb0c, 0x21, 0 + .dw 0x61c0, 0xcb0c, 0x61ff, 0xcb0c, 0x21, 0 + .dw 0x6240, 0xcb0c, 0x627f, 0xcb0c, 0x21, 0 + .dw 0x62c0, 0xcb0c, 0x62ff, 0xcb0c, 0x21, 0 + .dw 0x6340, 0xcb0c, 0x637f, 0xcb0c, 0x21, 0 + .dw 0x63c0, 0xcb0c, 0x63ff, 0xcb0c, 0x21, 0 + .dw 0x6440, 0xcb0c, 0x647f, 0xcb0c, 0x21, 0 + .dw 0x64c0, 0xcb0c, 0x64ff, 0xcb0c, 0x21, 0 + .dw 0x6540, 0xcb0c, 0x657f, 0xcb0c, 0x21, 0 + .dw 0x65c0, 0xcb0c, 0x65ff, 0xcb0c, 0x21, 0 + .dw 0x6640, 0xcb0c, 0x667f, 0xcb0c, 0x21, 0 + .dw 0x66c0, 0xcb0c, 0x66ff, 0xcb0c, 0x21, 0 + .dw 0x6740, 0xcb0c, 0x677f, 0xcb0c, 0x21, 0 + .dw 0x67c0, 0xcb0c, 0x7fff, 0xcb0c, 0x21, 0 + .dw 0x8040, 0xcb0c, 0x807f, 0xcb0c, 0x21, 0 + .dw 0x80c0, 0xcb0c, 0x80ff, 0xcb0c, 0x21, 0 + .dw 0x8140, 0xcb0c, 0x817f, 0xcb0c, 0x21, 0 + .dw 0x81c0, 0xcb0c, 0x9fff, 0xcb0c, 0x21, 0 + .dw 0xa040, 0xcb0c, 0xa07f, 0xcb0c, 0x21, 0 + .dw 0xa0c0, 0xcb0c, 0xa0ff, 0xcb0c, 0x21, 0 + .dw 0xa140, 0xcb0c, 0xa17f, 0xcb0c, 0x21, 0 + .dw 0xa1c0, 0xcb0c, 0xa1ff, 0xcb0c, 0x21, 0 + .dw 0xa240, 0xcb0c, 0xa27f, 0xcb0c, 0x21, 0 + .dw 0xa2c0, 0xcb0c, 0xa2ff, 0xcb0c, 0x21, 0 + .dw 0xa340, 0xcb0c, 0xa37f, 0xcb0c, 0x21, 0 + .dw 0xa3c0, 0xcb0c, 0xa3ff, 0xcb0c, 0x21, 0 + .dw 0xa440, 0xcb0c, 0xa47f, 0xcb0c, 0x21, 0 + .dw 0xa4c0, 0xcb0c, 0xa4ff, 0xcb0c, 0x21, 0 + .dw 0xa540, 0xcb0c, 0xa57f, 0xcb0c, 0x21, 0 + .dw 0xa5c0, 0xcb0c, 0xa5ff, 0xcb0c, 0x21, 0 + .dw 0xa640, 0xcb0c, 0xa67f, 0xcb0c, 0x21, 0 + .dw 0xa6c0, 0xcb0c, 0xa6ff, 0xcb0c, 0x21, 0 + .dw 0xa740, 0xcb0c, 0xa77f, 0xcb0c, 0x21, 0 + .dw 0xa7c0, 0xcb0c, 0xbfff, 0xcb0c, 0x21, 0 + .dw 0xc040, 0xcb0c, 0xc07f, 0xcb0c, 0x21, 0 + .dw 0xc0c0, 0xcb0c, 0xc0ff, 0xcb0c, 0x21, 0 + .dw 0xc140, 0xcb0c, 0xc17f, 0xcb0c, 0x21, 0 + .dw 0xc1c0, 0xcb0c, 0xdfff, 0xcb0c, 0x21, 0 + .dw 0xe040, 0xcb0c, 0xe07f, 0xcb0c, 0x21, 0 + .dw 0xe0c0, 0xcb0c, 0xe0ff, 0xcb0c, 0x21, 0 + .dw 0xe140, 0xcb0c, 0xe17f, 0xcb0c, 0x21, 0 + .dw 0xe1c0, 0xcb0c, 0xe1ff, 0xcb0c, 0x21, 0 + .dw 0xe240, 0xcb0c, 0xe27f, 0xcb0c, 0x21, 0 + .dw 0xe2c0, 0xcb0c, 0xe2ff, 0xcb0c, 0x21, 0 + .dw 0xe340, 0xcb0c, 0xe37f, 0xcb0c, 0x21, 0 + .dw 0xe3c0, 0xcb0c, 0xe3ff, 0xcb0c, 0x21, 0 + .dw 0xe440, 0xcb0c, 0xe47f, 0xcb0c, 0x21, 0 + .dw 0xe4c0, 0xcb0c, 0xe4ff, 0xcb0c, 0x21, 0 + .dw 0xe540, 0xcb0c, 0xe57f, 0xcb0c, 0x21, 0 + .dw 0xe5c0, 0xcb0c, 0xe5ff, 0xcb0c, 0x21, 0 + .dw 0xe640, 0xcb0c, 0xe67f, 0xcb0c, 0x21, 0 + .dw 0xe6c0, 0xcb0c, 0xe6ff, 0xcb0c, 0x21, 0 + .dw 0xe740, 0xcb0c, 0xe77f, 0xcb0c, 0x21, 0 + .dw 0xe7c0, 0xcb0c, 0xffff, 0xcb13, 0x21, 0 + .dw 0x0200, 0xcb14, 0x1fff, 0xcb14, 0x21, 0 + .dw 0x2800, 0xcb14, 0x3fff, 0xcb14, 0x21, 0 + .dw 0x4200, 0xcb14, 0x5fff, 0xcb14, 0x21, 0 + .dw 0x6800, 0xcb14, 0x7fff, 0xcb14, 0x21, 0 + .dw 0x8200, 0xcb14, 0x9fff, 0xcb14, 0x21, 0 + .dw 0xa800, 0xcb14, 0xbfff, 0xcb14, 0x21, 0 + .dw 0xc200, 0xcb14, 0xdfff, 0xcb14, 0x21, 0 + .dw 0xe800, 0xcb14, 0xffff, 0xcb1b, 0x21, 0 + .dw 0x0040, 0xcb1c, 0x007f, 0xcb1c, 0x21, 0 + .dw 0x00c0, 0xcb1c, 0x00ff, 0xcb1c, 0x21, 0 + .dw 0x0140, 0xcb1c, 0x017f, 0xcb1c, 0x21, 0 + .dw 0x01c0, 0xcb1c, 0x1fff, 0xcb1c, 0x21, 0 + .dw 0x2040, 0xcb1c, 0x207f, 0xcb1c, 0x21, 0 + .dw 0x20c0, 0xcb1c, 0x20ff, 0xcb1c, 0x21, 0 + .dw 0x2140, 0xcb1c, 0x217f, 0xcb1c, 0x21, 0 + .dw 0x21c0, 0xcb1c, 0x21ff, 0xcb1c, 0x21, 0 + .dw 0x2240, 0xcb1c, 0x227f, 0xcb1c, 0x21, 0 + .dw 0x22c0, 0xcb1c, 0x22ff, 0xcb1c, 0x21, 0 + .dw 0x2340, 0xcb1c, 0x237f, 0xcb1c, 0x21, 0 + .dw 0x23c0, 0xcb1c, 0x23ff, 0xcb1c, 0x21, 0 + .dw 0x2440, 0xcb1c, 0x247f, 0xcb1c, 0x21, 0 + .dw 0x24c0, 0xcb1c, 0x24ff, 0xcb1c, 0x21, 0 + .dw 0x2540, 0xcb1c, 0x257f, 0xcb1c, 0x21, 0 + .dw 0x25c0, 0xcb1c, 0x25ff, 0xcb1c, 0x21, 0 + .dw 0x2640, 0xcb1c, 0x267f, 0xcb1c, 0x21, 0 + .dw 0x26c0, 0xcb1c, 0x26ff, 0xcb1c, 0x21, 0 + .dw 0x2740, 0xcb1c, 0x277f, 0xcb1c, 0x21, 0 + .dw 0x27c0, 0xcb1c, 0x3fff, 0xcb1c, 0x21, 0 + .dw 0x4040, 0xcb1c, 0x407f, 0xcb1c, 0x21, 0 + .dw 0x40c0, 0xcb1c, 0x40ff, 0xcb1c, 0x21, 0 + .dw 0x4140, 0xcb1c, 0x417f, 0xcb1c, 0x21, 0 + .dw 0x41c0, 0xcb1c, 0x5fff, 0xcb1c, 0x21, 0 + .dw 0x6040, 0xcb1c, 0x607f, 0xcb1c, 0x21, 0 + .dw 0x60c0, 0xcb1c, 0x60ff, 0xcb1c, 0x21, 0 + .dw 0x6140, 0xcb1c, 0x617f, 0xcb1c, 0x21, 0 + .dw 0x61c0, 0xcb1c, 0x61ff, 0xcb1c, 0x21, 0 + .dw 0x6240, 0xcb1c, 0x627f, 0xcb1c, 0x21, 0 + .dw 0x62c0, 0xcb1c, 0x62ff, 0xcb1c, 0x21, 0 + .dw 0x6340, 0xcb1c, 0x637f, 0xcb1c, 0x21, 0 + .dw 0x63c0, 0xcb1c, 0x63ff, 0xcb1c, 0x21, 0 + .dw 0x6440, 0xcb1c, 0x647f, 0xcb1c, 0x21, 0 + .dw 0x64c0, 0xcb1c, 0x64ff, 0xcb1c, 0x21, 0 + .dw 0x6540, 0xcb1c, 0x657f, 0xcb1c, 0x21, 0 + .dw 0x65c0, 0xcb1c, 0x65ff, 0xcb1c, 0x21, 0 + .dw 0x6640, 0xcb1c, 0x667f, 0xcb1c, 0x21, 0 + .dw 0x66c0, 0xcb1c, 0x66ff, 0xcb1c, 0x21, 0 + .dw 0x6740, 0xcb1c, 0x677f, 0xcb1c, 0x21, 0 + .dw 0x67c0, 0xcb1c, 0x7fff, 0xcb1c, 0x21, 0 + .dw 0x8040, 0xcb1c, 0x807f, 0xcb1c, 0x21, 0 + .dw 0x80c0, 0xcb1c, 0x80ff, 0xcb1c, 0x21, 0 + .dw 0x8140, 0xcb1c, 0x817f, 0xcb1c, 0x21, 0 + .dw 0x81c0, 0xcb1c, 0x9fff, 0xcb1c, 0x21, 0 + .dw 0xa040, 0xcb1c, 0xa07f, 0xcb1c, 0x21, 0 + .dw 0xa0c0, 0xcb1c, 0xa0ff, 0xcb1c, 0x21, 0 + .dw 0xa140, 0xcb1c, 0xa17f, 0xcb1c, 0x21, 0 + .dw 0xa1c0, 0xcb1c, 0xa1ff, 0xcb1c, 0x21, 0 + .dw 0xa240, 0xcb1c, 0xa27f, 0xcb1c, 0x21, 0 + .dw 0xa2c0, 0xcb1c, 0xa2ff, 0xcb1c, 0x21, 0 + .dw 0xa340, 0xcb1c, 0xa37f, 0xcb1c, 0x21, 0 + .dw 0xa3c0, 0xcb1c, 0xa3ff, 0xcb1c, 0x21, 0 + .dw 0xa440, 0xcb1c, 0xa47f, 0xcb1c, 0x21, 0 + .dw 0xa4c0, 0xcb1c, 0xa4ff, 0xcb1c, 0x21, 0 + .dw 0xa540, 0xcb1c, 0xa57f, 0xcb1c, 0x21, 0 + .dw 0xa5c0, 0xcb1c, 0xa5ff, 0xcb1c, 0x21, 0 + .dw 0xa640, 0xcb1c, 0xa67f, 0xcb1c, 0x21, 0 + .dw 0xa6c0, 0xcb1c, 0xa6ff, 0xcb1c, 0x21, 0 + .dw 0xa740, 0xcb1c, 0xa77f, 0xcb1c, 0x21, 0 + .dw 0xa7c0, 0xcb1c, 0xbfff, 0xcb1c, 0x21, 0 + .dw 0xc040, 0xcb1c, 0xc07f, 0xcb1c, 0x21, 0 + .dw 0xc0c0, 0xcb1c, 0xc0ff, 0xcb1c, 0x21, 0 + .dw 0xc140, 0xcb1c, 0xc17f, 0xcb1c, 0x21, 0 + .dw 0xc1c0, 0xcb1c, 0xdfff, 0xcb1c, 0x21, 0 + .dw 0xe040, 0xcb1c, 0xe07f, 0xcb1c, 0x21, 0 + .dw 0xe0c0, 0xcb1c, 0xe0ff, 0xcb1c, 0x21, 0 + .dw 0xe140, 0xcb1c, 0xe17f, 0xcb1c, 0x21, 0 + .dw 0xe1c0, 0xcb1c, 0xe1ff, 0xcb1c, 0x21, 0 + .dw 0xe240, 0xcb1c, 0xe27f, 0xcb1c, 0x21, 0 + .dw 0xe2c0, 0xcb1c, 0xe2ff, 0xcb1c, 0x21, 0 + .dw 0xe340, 0xcb1c, 0xe37f, 0xcb1c, 0x21, 0 + .dw 0xe3c0, 0xcb1c, 0xe3ff, 0xcb1c, 0x21, 0 + .dw 0xe440, 0xcb1c, 0xe47f, 0xcb1c, 0x21, 0 + .dw 0xe4c0, 0xcb1c, 0xe4ff, 0xcb1c, 0x21, 0 + .dw 0xe540, 0xcb1c, 0xe57f, 0xcb1c, 0x21, 0 + .dw 0xe5c0, 0xcb1c, 0xe5ff, 0xcb1c, 0x21, 0 + .dw 0xe640, 0xcb1c, 0xe67f, 0xcb1c, 0x21, 0 + .dw 0xe6c0, 0xcb1c, 0xe6ff, 0xcb1c, 0x21, 0 + .dw 0xe740, 0xcb1c, 0xe77f, 0xcb1c, 0x21, 0 + .dw 0xe7c0, 0xcb1c, 0x1fff, 0xcb20, 0x21, 0 + .dw 0x2800, 0xcb20, 0xffff, 0xcb23, 0x21, 0 + .dw 0x0200, 0xcb24, 0x1fff, 0xcb24, 0x21, 0 + .dw 0x2800, 0xcb24, 0x3fff, 0xcb24, 0x21, 0 + .dw 0x4200, 0xcb24, 0x5fff, 0xcb24, 0x21, 0 + .dw 0x6800, 0xcb24, 0x7fff, 0xcb24, 0x21, 0 + .dw 0x8200, 0xcb24, 0x9fff, 0xcb24, 0x21, 0 + .dw 0xa800, 0xcb24, 0xbfff, 0xcb24, 0x21, 0 + .dw 0xc200, 0xcb24, 0xdfff, 0xcb24, 0x21, 0 + .dw 0xe800, 0xcb24, 0x1fff, 0xcb28, 0x21, 0 + .dw 0x2040, 0xcb28, 0x207f, 0xcb28, 0x21, 0 + .dw 0x20c0, 0xcb28, 0x20ff, 0xcb28, 0x21, 0 + .dw 0x2140, 0xcb28, 0x217f, 0xcb28, 0x21, 0 + .dw 0x21c0, 0xcb28, 0x21ff, 0xcb28, 0x21, 0 + .dw 0x2240, 0xcb28, 0x227f, 0xcb28, 0x21, 0 + .dw 0x22c0, 0xcb28, 0x22ff, 0xcb28, 0x21, 0 + .dw 0x2340, 0xcb28, 0x237f, 0xcb28, 0x21, 0 + .dw 0x23c0, 0xcb28, 0x23ff, 0xcb28, 0x21, 0 + .dw 0x2440, 0xcb28, 0x247f, 0xcb28, 0x21, 0 + .dw 0x24c0, 0xcb28, 0x24ff, 0xcb28, 0x21, 0 + .dw 0x2540, 0xcb28, 0x257f, 0xcb28, 0x21, 0 + .dw 0x25c0, 0xcb28, 0x25ff, 0xcb28, 0x21, 0 + .dw 0x2640, 0xcb28, 0x267f, 0xcb28, 0x21, 0 + .dw 0x26c0, 0xcb28, 0x26ff, 0xcb28, 0x21, 0 + .dw 0x2740, 0xcb28, 0x277f, 0xcb28, 0x21, 0 + .dw 0x27c0, 0xcb28, 0xffff, 0xcb2b, 0x21, 0 + .dw 0x0040, 0xcb2c, 0x007f, 0xcb2c, 0x21, 0 + .dw 0x00c0, 0xcb2c, 0x00ff, 0xcb2c, 0x21, 0 + .dw 0x0140, 0xcb2c, 0x017f, 0xcb2c, 0x21, 0 + .dw 0x01c0, 0xcb2c, 0x1fff, 0xcb2c, 0x21, 0 + .dw 0x2040, 0xcb2c, 0x207f, 0xcb2c, 0x21, 0 + .dw 0x20c0, 0xcb2c, 0x20ff, 0xcb2c, 0x21, 0 + .dw 0x2140, 0xcb2c, 0x217f, 0xcb2c, 0x21, 0 + .dw 0x21c0, 0xcb2c, 0x21ff, 0xcb2c, 0x21, 0 + .dw 0x2240, 0xcb2c, 0x227f, 0xcb2c, 0x21, 0 + .dw 0x22c0, 0xcb2c, 0x22ff, 0xcb2c, 0x21, 0 + .dw 0x2340, 0xcb2c, 0x237f, 0xcb2c, 0x21, 0 + .dw 0x23c0, 0xcb2c, 0x23ff, 0xcb2c, 0x21, 0 + .dw 0x2440, 0xcb2c, 0x247f, 0xcb2c, 0x21, 0 + .dw 0x24c0, 0xcb2c, 0x24ff, 0xcb2c, 0x21, 0 + .dw 0x2540, 0xcb2c, 0x257f, 0xcb2c, 0x21, 0 + .dw 0x25c0, 0xcb2c, 0x25ff, 0xcb2c, 0x21, 0 + .dw 0x2640, 0xcb2c, 0x267f, 0xcb2c, 0x21, 0 + .dw 0x26c0, 0xcb2c, 0x26ff, 0xcb2c, 0x21, 0 + .dw 0x2740, 0xcb2c, 0x277f, 0xcb2c, 0x21, 0 + .dw 0x27c0, 0xcb2c, 0x3fff, 0xcb2c, 0x21, 0 + .dw 0x4040, 0xcb2c, 0x407f, 0xcb2c, 0x21, 0 + .dw 0x40c0, 0xcb2c, 0x40ff, 0xcb2c, 0x21, 0 + .dw 0x4140, 0xcb2c, 0x417f, 0xcb2c, 0x21, 0 + .dw 0x41c0, 0xcb2c, 0x5fff, 0xcb2c, 0x21, 0 + .dw 0x6040, 0xcb2c, 0x607f, 0xcb2c, 0x21, 0 + .dw 0x60c0, 0xcb2c, 0x60ff, 0xcb2c, 0x21, 0 + .dw 0x6140, 0xcb2c, 0x617f, 0xcb2c, 0x21, 0 + .dw 0x61c0, 0xcb2c, 0x61ff, 0xcb2c, 0x21, 0 + .dw 0x6240, 0xcb2c, 0x627f, 0xcb2c, 0x21, 0 + .dw 0x62c0, 0xcb2c, 0x62ff, 0xcb2c, 0x21, 0 + .dw 0x6340, 0xcb2c, 0x637f, 0xcb2c, 0x21, 0 + .dw 0x63c0, 0xcb2c, 0x63ff, 0xcb2c, 0x21, 0 + .dw 0x6440, 0xcb2c, 0x647f, 0xcb2c, 0x21, 0 + .dw 0x64c0, 0xcb2c, 0x64ff, 0xcb2c, 0x21, 0 + .dw 0x6540, 0xcb2c, 0x657f, 0xcb2c, 0x21, 0 + .dw 0x65c0, 0xcb2c, 0x65ff, 0xcb2c, 0x21, 0 + .dw 0x6640, 0xcb2c, 0x667f, 0xcb2c, 0x21, 0 + .dw 0x66c0, 0xcb2c, 0x66ff, 0xcb2c, 0x21, 0 + .dw 0x6740, 0xcb2c, 0x677f, 0xcb2c, 0x21, 0 + .dw 0x67c0, 0xcb2c, 0x7fff, 0xcb2c, 0x21, 0 + .dw 0x8040, 0xcb2c, 0x807f, 0xcb2c, 0x21, 0 + .dw 0x80c0, 0xcb2c, 0x80ff, 0xcb2c, 0x21, 0 + .dw 0x8140, 0xcb2c, 0x817f, 0xcb2c, 0x21, 0 + .dw 0x81c0, 0xcb2c, 0x9fff, 0xcb2c, 0x21, 0 + .dw 0xa040, 0xcb2c, 0xa07f, 0xcb2c, 0x21, 0 + .dw 0xa0c0, 0xcb2c, 0xa0ff, 0xcb2c, 0x21, 0 + .dw 0xa140, 0xcb2c, 0xa17f, 0xcb2c, 0x21, 0 + .dw 0xa1c0, 0xcb2c, 0xa1ff, 0xcb2c, 0x21, 0 + .dw 0xa240, 0xcb2c, 0xa27f, 0xcb2c, 0x21, 0 + .dw 0xa2c0, 0xcb2c, 0xa2ff, 0xcb2c, 0x21, 0 + .dw 0xa340, 0xcb2c, 0xa37f, 0xcb2c, 0x21, 0 + .dw 0xa3c0, 0xcb2c, 0xa3ff, 0xcb2c, 0x21, 0 + .dw 0xa440, 0xcb2c, 0xa47f, 0xcb2c, 0x21, 0 + .dw 0xa4c0, 0xcb2c, 0xa4ff, 0xcb2c, 0x21, 0 + .dw 0xa540, 0xcb2c, 0xa57f, 0xcb2c, 0x21, 0 + .dw 0xa5c0, 0xcb2c, 0xa5ff, 0xcb2c, 0x21, 0 + .dw 0xa640, 0xcb2c, 0xa67f, 0xcb2c, 0x21, 0 + .dw 0xa6c0, 0xcb2c, 0xa6ff, 0xcb2c, 0x21, 0 + .dw 0xa740, 0xcb2c, 0xa77f, 0xcb2c, 0x21, 0 + .dw 0xa7c0, 0xcb2c, 0xbfff, 0xcb2c, 0x21, 0 + .dw 0xc040, 0xcb2c, 0xc07f, 0xcb2c, 0x21, 0 + .dw 0xc0c0, 0xcb2c, 0xc0ff, 0xcb2c, 0x21, 0 + .dw 0xc140, 0xcb2c, 0xc17f, 0xcb2c, 0x21, 0 + .dw 0xc1c0, 0xcb2c, 0xdfff, 0xcb2c, 0x21, 0 + .dw 0xe040, 0xcb2c, 0xe07f, 0xcb2c, 0x21, 0 + .dw 0xe0c0, 0xcb2c, 0xe0ff, 0xcb2c, 0x21, 0 + .dw 0xe140, 0xcb2c, 0xe17f, 0xcb2c, 0x21, 0 + .dw 0xe1c0, 0xcb2c, 0xe1ff, 0xcb2c, 0x21, 0 + .dw 0xe240, 0xcb2c, 0xe27f, 0xcb2c, 0x21, 0 + .dw 0xe2c0, 0xcb2c, 0xe2ff, 0xcb2c, 0x21, 0 + .dw 0xe340, 0xcb2c, 0xe37f, 0xcb2c, 0x21, 0 + .dw 0xe3c0, 0xcb2c, 0xe3ff, 0xcb2c, 0x21, 0 + .dw 0xe440, 0xcb2c, 0xe47f, 0xcb2c, 0x21, 0 + .dw 0xe4c0, 0xcb2c, 0xe4ff, 0xcb2c, 0x21, 0 + .dw 0xe540, 0xcb2c, 0xe57f, 0xcb2c, 0x21, 0 + .dw 0xe5c0, 0xcb2c, 0xe5ff, 0xcb2c, 0x21, 0 + .dw 0xe640, 0xcb2c, 0xe67f, 0xcb2c, 0x21, 0 + .dw 0xe6c0, 0xcb2c, 0xe6ff, 0xcb2c, 0x21, 0 + .dw 0xe740, 0xcb2c, 0xe77f, 0xcb2c, 0x21, 0 + .dw 0xe7c0, 0xcb2c, 0xffff, 0xcb33, 0x21, 0 + .dw 0x0200, 0xcb34, 0x1fff, 0xcb34, 0x21, 0 + .dw 0x2800, 0xcb34, 0x3fff, 0xcb34, 0x21, 0 + .dw 0x4200, 0xcb34, 0x5fff, 0xcb34, 0x21, 0 + .dw 0x6800, 0xcb34, 0x7fff, 0xcb34, 0x21, 0 + .dw 0x8200, 0xcb34, 0x9fff, 0xcb34, 0x21, 0 + .dw 0xa800, 0xcb34, 0xbfff, 0xcb34, 0x21, 0 + .dw 0xc200, 0xcb34, 0xdfff, 0xcb34, 0x21, 0 + .dw 0xe800, 0xcb34, 0xffff, 0xcb3b, 0x21, 0 + .dw 0x0040, 0xcb3c, 0x007f, 0xcb3c, 0x21, 0 + .dw 0x00c0, 0xcb3c, 0x00ff, 0xcb3c, 0x21, 0 + .dw 0x0140, 0xcb3c, 0x017f, 0xcb3c, 0x21, 0 + .dw 0x01c0, 0xcb3c, 0x1fff, 0xcb3c, 0x21, 0 + .dw 0x2040, 0xcb3c, 0x207f, 0xcb3c, 0x21, 0 + .dw 0x20c0, 0xcb3c, 0x20ff, 0xcb3c, 0x21, 0 + .dw 0x2140, 0xcb3c, 0x217f, 0xcb3c, 0x21, 0 + .dw 0x21c0, 0xcb3c, 0x21ff, 0xcb3c, 0x21, 0 + .dw 0x2240, 0xcb3c, 0x227f, 0xcb3c, 0x21, 0 + .dw 0x22c0, 0xcb3c, 0x22ff, 0xcb3c, 0x21, 0 + .dw 0x2340, 0xcb3c, 0x237f, 0xcb3c, 0x21, 0 + .dw 0x23c0, 0xcb3c, 0x23ff, 0xcb3c, 0x21, 0 + .dw 0x2440, 0xcb3c, 0x247f, 0xcb3c, 0x21, 0 + .dw 0x24c0, 0xcb3c, 0x24ff, 0xcb3c, 0x21, 0 + .dw 0x2540, 0xcb3c, 0x257f, 0xcb3c, 0x21, 0 + .dw 0x25c0, 0xcb3c, 0x25ff, 0xcb3c, 0x21, 0 + .dw 0x2640, 0xcb3c, 0x267f, 0xcb3c, 0x21, 0 + .dw 0x26c0, 0xcb3c, 0x26ff, 0xcb3c, 0x21, 0 + .dw 0x2740, 0xcb3c, 0x277f, 0xcb3c, 0x21, 0 + .dw 0x27c0, 0xcb3c, 0x3fff, 0xcb3c, 0x21, 0 + .dw 0x4040, 0xcb3c, 0x407f, 0xcb3c, 0x21, 0 + .dw 0x40c0, 0xcb3c, 0x40ff, 0xcb3c, 0x21, 0 + .dw 0x4140, 0xcb3c, 0x417f, 0xcb3c, 0x21, 0 + .dw 0x41c0, 0xcb3c, 0x5fff, 0xcb3c, 0x21, 0 + .dw 0x6040, 0xcb3c, 0x607f, 0xcb3c, 0x21, 0 + .dw 0x60c0, 0xcb3c, 0x60ff, 0xcb3c, 0x21, 0 + .dw 0x6140, 0xcb3c, 0x617f, 0xcb3c, 0x21, 0 + .dw 0x61c0, 0xcb3c, 0x61ff, 0xcb3c, 0x21, 0 + .dw 0x6240, 0xcb3c, 0x627f, 0xcb3c, 0x21, 0 + .dw 0x62c0, 0xcb3c, 0x62ff, 0xcb3c, 0x21, 0 + .dw 0x6340, 0xcb3c, 0x637f, 0xcb3c, 0x21, 0 + .dw 0x63c0, 0xcb3c, 0x63ff, 0xcb3c, 0x21, 0 + .dw 0x6440, 0xcb3c, 0x647f, 0xcb3c, 0x21, 0 + .dw 0x64c0, 0xcb3c, 0x64ff, 0xcb3c, 0x21, 0 + .dw 0x6540, 0xcb3c, 0x657f, 0xcb3c, 0x21, 0 + .dw 0x65c0, 0xcb3c, 0x65ff, 0xcb3c, 0x21, 0 + .dw 0x6640, 0xcb3c, 0x667f, 0xcb3c, 0x21, 0 + .dw 0x66c0, 0xcb3c, 0x66ff, 0xcb3c, 0x21, 0 + .dw 0x6740, 0xcb3c, 0x677f, 0xcb3c, 0x21, 0 + .dw 0x67c0, 0xcb3c, 0x7fff, 0xcb3c, 0x21, 0 + .dw 0x8040, 0xcb3c, 0x807f, 0xcb3c, 0x21, 0 + .dw 0x80c0, 0xcb3c, 0x80ff, 0xcb3c, 0x21, 0 + .dw 0x8140, 0xcb3c, 0x817f, 0xcb3c, 0x21, 0 + .dw 0x81c0, 0xcb3c, 0x9fff, 0xcb3c, 0x21, 0 + .dw 0xa040, 0xcb3c, 0xa07f, 0xcb3c, 0x21, 0 + .dw 0xa0c0, 0xcb3c, 0xa0ff, 0xcb3c, 0x21, 0 + .dw 0xa140, 0xcb3c, 0xa17f, 0xcb3c, 0x21, 0 + .dw 0xa1c0, 0xcb3c, 0xa1ff, 0xcb3c, 0x21, 0 + .dw 0xa240, 0xcb3c, 0xa27f, 0xcb3c, 0x21, 0 + .dw 0xa2c0, 0xcb3c, 0xa2ff, 0xcb3c, 0x21, 0 + .dw 0xa340, 0xcb3c, 0xa37f, 0xcb3c, 0x21, 0 + .dw 0xa3c0, 0xcb3c, 0xa3ff, 0xcb3c, 0x21, 0 + .dw 0xa440, 0xcb3c, 0xa47f, 0xcb3c, 0x21, 0 + .dw 0xa4c0, 0xcb3c, 0xa4ff, 0xcb3c, 0x21, 0 + .dw 0xa540, 0xcb3c, 0xa57f, 0xcb3c, 0x21, 0 + .dw 0xa5c0, 0xcb3c, 0xa5ff, 0xcb3c, 0x21, 0 + .dw 0xa640, 0xcb3c, 0xa67f, 0xcb3c, 0x21, 0 + .dw 0xa6c0, 0xcb3c, 0xa6ff, 0xcb3c, 0x21, 0 + .dw 0xa740, 0xcb3c, 0xa77f, 0xcb3c, 0x21, 0 + .dw 0xa7c0, 0xcb3c, 0xbfff, 0xcb3c, 0x21, 0 + .dw 0xc040, 0xcb3c, 0xc07f, 0xcb3c, 0x21, 0 + .dw 0xc0c0, 0xcb3c, 0xc0ff, 0xcb3c, 0x21, 0 + .dw 0xc140, 0xcb3c, 0xc17f, 0xcb3c, 0x21, 0 + .dw 0xc1c0, 0xcb3c, 0xdfff, 0xcb3c, 0x21, 0 + .dw 0xe040, 0xcb3c, 0xe07f, 0xcb3c, 0x21, 0 + .dw 0xe0c0, 0xcb3c, 0xe0ff, 0xcb3c, 0x21, 0 + .dw 0xe140, 0xcb3c, 0xe17f, 0xcb3c, 0x21, 0 + .dw 0xe1c0, 0xcb3c, 0xe1ff, 0xcb3c, 0x21, 0 + .dw 0xe240, 0xcb3c, 0xe27f, 0xcb3c, 0x21, 0 + .dw 0xe2c0, 0xcb3c, 0xe2ff, 0xcb3c, 0x21, 0 + .dw 0xe340, 0xcb3c, 0xe37f, 0xcb3c, 0x21, 0 + .dw 0xe3c0, 0xcb3c, 0xe3ff, 0xcb3c, 0x21, 0 + .dw 0xe440, 0xcb3c, 0xe47f, 0xcb3c, 0x21, 0 + .dw 0xe4c0, 0xcb3c, 0xe4ff, 0xcb3c, 0x21, 0 + .dw 0xe540, 0xcb3c, 0xe57f, 0xcb3c, 0x21, 0 + .dw 0xe5c0, 0xcb3c, 0xe5ff, 0xcb3c, 0x21, 0 + .dw 0xe640, 0xcb3c, 0xe67f, 0xcb3c, 0x21, 0 + .dw 0xe6c0, 0xcb3c, 0xe6ff, 0xcb3c, 0x21, 0 + .dw 0xe740, 0xcb3c, 0xe77f, 0xcb3c, 0x21, 0 + .dw 0xe7c0, 0xcb3c, 0x1fff, 0xcb60, 0x21, 0 + .dw 0x2800, 0xcb60, 0xffff, 0xcb63, 0x21, 0 + .dw 0x0200, 0xcb64, 0x1fff, 0xcb64, 0x21, 0 + .dw 0x2800, 0xcb64, 0x3fff, 0xcb64, 0x21, 0 + .dw 0x4200, 0xcb64, 0x5fff, 0xcb64, 0x21, 0 + .dw 0x6800, 0xcb64, 0x7fff, 0xcb64, 0x21, 0 + .dw 0x8200, 0xcb64, 0x9fff, 0xcb64, 0x21, 0 + .dw 0xa800, 0xcb64, 0xbfff, 0xcb64, 0x21, 0 + .dw 0xc200, 0xcb64, 0xdfff, 0xcb64, 0x21, 0 + .dw 0xe800, 0xcb64, 0xffff, 0xcb73, 0x21, 0 + .dw 0x0200, 0xcb74, 0x1fff, 0xcb74, 0x21, 0 + .dw 0x2800, 0xcb74, 0x3fff, 0xcb74, 0x21, 0 + .dw 0x4200, 0xcb74, 0x5fff, 0xcb74, 0x21, 0 + .dw 0x6800, 0xcb74, 0x7fff, 0xcb74, 0x21, 0 + .dw 0x8200, 0xcb74, 0x9fff, 0xcb74, 0x21, 0 + .dw 0xa800, 0xcb74, 0xbfff, 0xcb74, 0x21, 0 + .dw 0xc200, 0xcb74, 0xdfff, 0xcb74, 0x21, 0 + .dw 0xe800, 0xcb74, 0x1fff, 0xcb80, 0x21, 0 + .dw 0x2800, 0xcb80, 0xffff, 0xcb83, 0x21, 0 + .dw 0x0200, 0xcb84, 0x1fff, 0xcb84, 0x21, 0 + .dw 0x2800, 0xcb84, 0x3fff, 0xcb84, 0x21, 0 + .dw 0x4200, 0xcb84, 0x5fff, 0xcb84, 0x21, 0 + .dw 0x6800, 0xcb84, 0x7fff, 0xcb84, 0x21, 0 + .dw 0x8200, 0xcb84, 0x9fff, 0xcb84, 0x21, 0 + .dw 0xa800, 0xcb84, 0xbfff, 0xcb84, 0x21, 0 + .dw 0xc200, 0xcb84, 0xdfff, 0xcb84, 0x21, 0 + .dw 0xe800, 0xcb84, 0x1fff, 0xcb88, 0x21, 0 + .dw 0x2040, 0xcb88, 0x207f, 0xcb88, 0x21, 0 + .dw 0x20c0, 0xcb88, 0x20ff, 0xcb88, 0x21, 0 + .dw 0x2140, 0xcb88, 0x217f, 0xcb88, 0x21, 0 + .dw 0x21c0, 0xcb88, 0x21ff, 0xcb88, 0x21, 0 + .dw 0x2240, 0xcb88, 0x227f, 0xcb88, 0x21, 0 + .dw 0x22c0, 0xcb88, 0x22ff, 0xcb88, 0x21, 0 + .dw 0x2340, 0xcb88, 0x237f, 0xcb88, 0x21, 0 + .dw 0x23c0, 0xcb88, 0x23ff, 0xcb88, 0x21, 0 + .dw 0x2440, 0xcb88, 0x247f, 0xcb88, 0x21, 0 + .dw 0x24c0, 0xcb88, 0x24ff, 0xcb88, 0x21, 0 + .dw 0x2540, 0xcb88, 0x257f, 0xcb88, 0x21, 0 + .dw 0x25c0, 0xcb88, 0x25ff, 0xcb88, 0x21, 0 + .dw 0x2640, 0xcb88, 0x267f, 0xcb88, 0x21, 0 + .dw 0x26c0, 0xcb88, 0x26ff, 0xcb88, 0x21, 0 + .dw 0x2740, 0xcb88, 0x277f, 0xcb88, 0x21, 0 + .dw 0x27c0, 0xcb88, 0xffff, 0xcb8b, 0x21, 0 + .dw 0x0040, 0xcb8c, 0x007f, 0xcb8c, 0x21, 0 + .dw 0x00c0, 0xcb8c, 0x00ff, 0xcb8c, 0x21, 0 + .dw 0x0140, 0xcb8c, 0x017f, 0xcb8c, 0x21, 0 + .dw 0x01c0, 0xcb8c, 0x1fff, 0xcb8c, 0x21, 0 + .dw 0x2040, 0xcb8c, 0x207f, 0xcb8c, 0x21, 0 + .dw 0x20c0, 0xcb8c, 0x20ff, 0xcb8c, 0x21, 0 + .dw 0x2140, 0xcb8c, 0x217f, 0xcb8c, 0x21, 0 + .dw 0x21c0, 0xcb8c, 0x21ff, 0xcb8c, 0x21, 0 + .dw 0x2240, 0xcb8c, 0x227f, 0xcb8c, 0x21, 0 + .dw 0x22c0, 0xcb8c, 0x22ff, 0xcb8c, 0x21, 0 + .dw 0x2340, 0xcb8c, 0x237f, 0xcb8c, 0x21, 0 + .dw 0x23c0, 0xcb8c, 0x23ff, 0xcb8c, 0x21, 0 + .dw 0x2440, 0xcb8c, 0x247f, 0xcb8c, 0x21, 0 + .dw 0x24c0, 0xcb8c, 0x24ff, 0xcb8c, 0x21, 0 + .dw 0x2540, 0xcb8c, 0x257f, 0xcb8c, 0x21, 0 + .dw 0x25c0, 0xcb8c, 0x25ff, 0xcb8c, 0x21, 0 + .dw 0x2640, 0xcb8c, 0x267f, 0xcb8c, 0x21, 0 + .dw 0x26c0, 0xcb8c, 0x26ff, 0xcb8c, 0x21, 0 + .dw 0x2740, 0xcb8c, 0x277f, 0xcb8c, 0x21, 0 + .dw 0x27c0, 0xcb8c, 0x3fff, 0xcb8c, 0x21, 0 + .dw 0x4040, 0xcb8c, 0x407f, 0xcb8c, 0x21, 0 + .dw 0x40c0, 0xcb8c, 0x40ff, 0xcb8c, 0x21, 0 + .dw 0x4140, 0xcb8c, 0x417f, 0xcb8c, 0x21, 0 + .dw 0x41c0, 0xcb8c, 0x5fff, 0xcb8c, 0x21, 0 + .dw 0x6040, 0xcb8c, 0x607f, 0xcb8c, 0x21, 0 + .dw 0x60c0, 0xcb8c, 0x60ff, 0xcb8c, 0x21, 0 + .dw 0x6140, 0xcb8c, 0x617f, 0xcb8c, 0x21, 0 + .dw 0x61c0, 0xcb8c, 0x61ff, 0xcb8c, 0x21, 0 + .dw 0x6240, 0xcb8c, 0x627f, 0xcb8c, 0x21, 0 + .dw 0x62c0, 0xcb8c, 0x62ff, 0xcb8c, 0x21, 0 + .dw 0x6340, 0xcb8c, 0x637f, 0xcb8c, 0x21, 0 + .dw 0x63c0, 0xcb8c, 0x63ff, 0xcb8c, 0x21, 0 + .dw 0x6440, 0xcb8c, 0x647f, 0xcb8c, 0x21, 0 + .dw 0x64c0, 0xcb8c, 0x64ff, 0xcb8c, 0x21, 0 + .dw 0x6540, 0xcb8c, 0x657f, 0xcb8c, 0x21, 0 + .dw 0x65c0, 0xcb8c, 0x65ff, 0xcb8c, 0x21, 0 + .dw 0x6640, 0xcb8c, 0x667f, 0xcb8c, 0x21, 0 + .dw 0x66c0, 0xcb8c, 0x66ff, 0xcb8c, 0x21, 0 + .dw 0x6740, 0xcb8c, 0x677f, 0xcb8c, 0x21, 0 + .dw 0x67c0, 0xcb8c, 0x7fff, 0xcb8c, 0x21, 0 + .dw 0x8040, 0xcb8c, 0x807f, 0xcb8c, 0x21, 0 + .dw 0x80c0, 0xcb8c, 0x80ff, 0xcb8c, 0x21, 0 + .dw 0x8140, 0xcb8c, 0x817f, 0xcb8c, 0x21, 0 + .dw 0x81c0, 0xcb8c, 0x9fff, 0xcb8c, 0x21, 0 + .dw 0xa040, 0xcb8c, 0xa07f, 0xcb8c, 0x21, 0 + .dw 0xa0c0, 0xcb8c, 0xa0ff, 0xcb8c, 0x21, 0 + .dw 0xa140, 0xcb8c, 0xa17f, 0xcb8c, 0x21, 0 + .dw 0xa1c0, 0xcb8c, 0xa1ff, 0xcb8c, 0x21, 0 + .dw 0xa240, 0xcb8c, 0xa27f, 0xcb8c, 0x21, 0 + .dw 0xa2c0, 0xcb8c, 0xa2ff, 0xcb8c, 0x21, 0 + .dw 0xa340, 0xcb8c, 0xa37f, 0xcb8c, 0x21, 0 + .dw 0xa3c0, 0xcb8c, 0xa3ff, 0xcb8c, 0x21, 0 + .dw 0xa440, 0xcb8c, 0xa47f, 0xcb8c, 0x21, 0 + .dw 0xa4c0, 0xcb8c, 0xa4ff, 0xcb8c, 0x21, 0 + .dw 0xa540, 0xcb8c, 0xa57f, 0xcb8c, 0x21, 0 + .dw 0xa5c0, 0xcb8c, 0xa5ff, 0xcb8c, 0x21, 0 + .dw 0xa640, 0xcb8c, 0xa67f, 0xcb8c, 0x21, 0 + .dw 0xa6c0, 0xcb8c, 0xa6ff, 0xcb8c, 0x21, 0 + .dw 0xa740, 0xcb8c, 0xa77f, 0xcb8c, 0x21, 0 + .dw 0xa7c0, 0xcb8c, 0xbfff, 0xcb8c, 0x21, 0 + .dw 0xc040, 0xcb8c, 0xc07f, 0xcb8c, 0x21, 0 + .dw 0xc0c0, 0xcb8c, 0xc0ff, 0xcb8c, 0x21, 0 + .dw 0xc140, 0xcb8c, 0xc17f, 0xcb8c, 0x21, 0 + .dw 0xc1c0, 0xcb8c, 0xdfff, 0xcb8c, 0x21, 0 + .dw 0xe040, 0xcb8c, 0xe07f, 0xcb8c, 0x21, 0 + .dw 0xe0c0, 0xcb8c, 0xe0ff, 0xcb8c, 0x21, 0 + .dw 0xe140, 0xcb8c, 0xe17f, 0xcb8c, 0x21, 0 + .dw 0xe1c0, 0xcb8c, 0xe1ff, 0xcb8c, 0x21, 0 + .dw 0xe240, 0xcb8c, 0xe27f, 0xcb8c, 0x21, 0 + .dw 0xe2c0, 0xcb8c, 0xe2ff, 0xcb8c, 0x21, 0 + .dw 0xe340, 0xcb8c, 0xe37f, 0xcb8c, 0x21, 0 + .dw 0xe3c0, 0xcb8c, 0xe3ff, 0xcb8c, 0x21, 0 + .dw 0xe440, 0xcb8c, 0xe47f, 0xcb8c, 0x21, 0 + .dw 0xe4c0, 0xcb8c, 0xe4ff, 0xcb8c, 0x21, 0 + .dw 0xe540, 0xcb8c, 0xe57f, 0xcb8c, 0x21, 0 + .dw 0xe5c0, 0xcb8c, 0xe5ff, 0xcb8c, 0x21, 0 + .dw 0xe640, 0xcb8c, 0xe67f, 0xcb8c, 0x21, 0 + .dw 0xe6c0, 0xcb8c, 0xe6ff, 0xcb8c, 0x21, 0 + .dw 0xe740, 0xcb8c, 0xe77f, 0xcb8c, 0x21, 0 + .dw 0xe7c0, 0xcb8c, 0xffff, 0xcb93, 0x21, 0 + .dw 0x0200, 0xcb94, 0x1fff, 0xcb94, 0x21, 0 + .dw 0x2800, 0xcb94, 0x3fff, 0xcb94, 0x21, 0 + .dw 0x4200, 0xcb94, 0x5fff, 0xcb94, 0x21, 0 + .dw 0x6800, 0xcb94, 0x7fff, 0xcb94, 0x21, 0 + .dw 0x8200, 0xcb94, 0x9fff, 0xcb94, 0x21, 0 + .dw 0xa800, 0xcb94, 0xbfff, 0xcb94, 0x21, 0 + .dw 0xc200, 0xcb94, 0xdfff, 0xcb94, 0x21, 0 + .dw 0xe800, 0xcb94, 0xffff, 0xcb9b, 0x21, 0 + .dw 0x0040, 0xcb9c, 0x007f, 0xcb9c, 0x21, 0 + .dw 0x00c0, 0xcb9c, 0x00ff, 0xcb9c, 0x21, 0 + .dw 0x0140, 0xcb9c, 0x017f, 0xcb9c, 0x21, 0 + .dw 0x01c0, 0xcb9c, 0x1fff, 0xcb9c, 0x21, 0 + .dw 0x2040, 0xcb9c, 0x207f, 0xcb9c, 0x21, 0 + .dw 0x20c0, 0xcb9c, 0x20ff, 0xcb9c, 0x21, 0 + .dw 0x2140, 0xcb9c, 0x217f, 0xcb9c, 0x21, 0 + .dw 0x21c0, 0xcb9c, 0x21ff, 0xcb9c, 0x21, 0 + .dw 0x2240, 0xcb9c, 0x227f, 0xcb9c, 0x21, 0 + .dw 0x22c0, 0xcb9c, 0x22ff, 0xcb9c, 0x21, 0 + .dw 0x2340, 0xcb9c, 0x237f, 0xcb9c, 0x21, 0 + .dw 0x23c0, 0xcb9c, 0x23ff, 0xcb9c, 0x21, 0 + .dw 0x2440, 0xcb9c, 0x247f, 0xcb9c, 0x21, 0 + .dw 0x24c0, 0xcb9c, 0x24ff, 0xcb9c, 0x21, 0 + .dw 0x2540, 0xcb9c, 0x257f, 0xcb9c, 0x21, 0 + .dw 0x25c0, 0xcb9c, 0x25ff, 0xcb9c, 0x21, 0 + .dw 0x2640, 0xcb9c, 0x267f, 0xcb9c, 0x21, 0 + .dw 0x26c0, 0xcb9c, 0x26ff, 0xcb9c, 0x21, 0 + .dw 0x2740, 0xcb9c, 0x277f, 0xcb9c, 0x21, 0 + .dw 0x27c0, 0xcb9c, 0x3fff, 0xcb9c, 0x21, 0 + .dw 0x4040, 0xcb9c, 0x407f, 0xcb9c, 0x21, 0 + .dw 0x40c0, 0xcb9c, 0x40ff, 0xcb9c, 0x21, 0 + .dw 0x4140, 0xcb9c, 0x417f, 0xcb9c, 0x21, 0 + .dw 0x41c0, 0xcb9c, 0x5fff, 0xcb9c, 0x21, 0 + .dw 0x6040, 0xcb9c, 0x607f, 0xcb9c, 0x21, 0 + .dw 0x60c0, 0xcb9c, 0x60ff, 0xcb9c, 0x21, 0 + .dw 0x6140, 0xcb9c, 0x617f, 0xcb9c, 0x21, 0 + .dw 0x61c0, 0xcb9c, 0x61ff, 0xcb9c, 0x21, 0 + .dw 0x6240, 0xcb9c, 0x627f, 0xcb9c, 0x21, 0 + .dw 0x62c0, 0xcb9c, 0x62ff, 0xcb9c, 0x21, 0 + .dw 0x6340, 0xcb9c, 0x637f, 0xcb9c, 0x21, 0 + .dw 0x63c0, 0xcb9c, 0x63ff, 0xcb9c, 0x21, 0 + .dw 0x6440, 0xcb9c, 0x647f, 0xcb9c, 0x21, 0 + .dw 0x64c0, 0xcb9c, 0x64ff, 0xcb9c, 0x21, 0 + .dw 0x6540, 0xcb9c, 0x657f, 0xcb9c, 0x21, 0 + .dw 0x65c0, 0xcb9c, 0x65ff, 0xcb9c, 0x21, 0 + .dw 0x6640, 0xcb9c, 0x667f, 0xcb9c, 0x21, 0 + .dw 0x66c0, 0xcb9c, 0x66ff, 0xcb9c, 0x21, 0 + .dw 0x6740, 0xcb9c, 0x677f, 0xcb9c, 0x21, 0 + .dw 0x67c0, 0xcb9c, 0x7fff, 0xcb9c, 0x21, 0 + .dw 0x8040, 0xcb9c, 0x807f, 0xcb9c, 0x21, 0 + .dw 0x80c0, 0xcb9c, 0x80ff, 0xcb9c, 0x21, 0 + .dw 0x8140, 0xcb9c, 0x817f, 0xcb9c, 0x21, 0 + .dw 0x81c0, 0xcb9c, 0x9fff, 0xcb9c, 0x21, 0 + .dw 0xa040, 0xcb9c, 0xa07f, 0xcb9c, 0x21, 0 + .dw 0xa0c0, 0xcb9c, 0xa0ff, 0xcb9c, 0x21, 0 + .dw 0xa140, 0xcb9c, 0xa17f, 0xcb9c, 0x21, 0 + .dw 0xa1c0, 0xcb9c, 0xa1ff, 0xcb9c, 0x21, 0 + .dw 0xa240, 0xcb9c, 0xa27f, 0xcb9c, 0x21, 0 + .dw 0xa2c0, 0xcb9c, 0xa2ff, 0xcb9c, 0x21, 0 + .dw 0xa340, 0xcb9c, 0xa37f, 0xcb9c, 0x21, 0 + .dw 0xa3c0, 0xcb9c, 0xa3ff, 0xcb9c, 0x21, 0 + .dw 0xa440, 0xcb9c, 0xa47f, 0xcb9c, 0x21, 0 + .dw 0xa4c0, 0xcb9c, 0xa4ff, 0xcb9c, 0x21, 0 + .dw 0xa540, 0xcb9c, 0xa57f, 0xcb9c, 0x21, 0 + .dw 0xa5c0, 0xcb9c, 0xa5ff, 0xcb9c, 0x21, 0 + .dw 0xa640, 0xcb9c, 0xa67f, 0xcb9c, 0x21, 0 + .dw 0xa6c0, 0xcb9c, 0xa6ff, 0xcb9c, 0x21, 0 + .dw 0xa740, 0xcb9c, 0xa77f, 0xcb9c, 0x21, 0 + .dw 0xa7c0, 0xcb9c, 0xbfff, 0xcb9c, 0x21, 0 + .dw 0xc040, 0xcb9c, 0xc07f, 0xcb9c, 0x21, 0 + .dw 0xc0c0, 0xcb9c, 0xc0ff, 0xcb9c, 0x21, 0 + .dw 0xc140, 0xcb9c, 0xc17f, 0xcb9c, 0x21, 0 + .dw 0xc1c0, 0xcb9c, 0xdfff, 0xcb9c, 0x21, 0 + .dw 0xe040, 0xcb9c, 0xe07f, 0xcb9c, 0x21, 0 + .dw 0xe0c0, 0xcb9c, 0xe0ff, 0xcb9c, 0x21, 0 + .dw 0xe140, 0xcb9c, 0xe17f, 0xcb9c, 0x21, 0 + .dw 0xe1c0, 0xcb9c, 0xe1ff, 0xcb9c, 0x21, 0 + .dw 0xe240, 0xcb9c, 0xe27f, 0xcb9c, 0x21, 0 + .dw 0xe2c0, 0xcb9c, 0xe2ff, 0xcb9c, 0x21, 0 + .dw 0xe340, 0xcb9c, 0xe37f, 0xcb9c, 0x21, 0 + .dw 0xe3c0, 0xcb9c, 0xe3ff, 0xcb9c, 0x21, 0 + .dw 0xe440, 0xcb9c, 0xe47f, 0xcb9c, 0x21, 0 + .dw 0xe4c0, 0xcb9c, 0xe4ff, 0xcb9c, 0x21, 0 + .dw 0xe540, 0xcb9c, 0xe57f, 0xcb9c, 0x21, 0 + .dw 0xe5c0, 0xcb9c, 0xe5ff, 0xcb9c, 0x21, 0 + .dw 0xe640, 0xcb9c, 0xe67f, 0xcb9c, 0x21, 0 + .dw 0xe6c0, 0xcb9c, 0xe6ff, 0xcb9c, 0x21, 0 + .dw 0xe740, 0xcb9c, 0xe77f, 0xcb9c, 0x21, 0 + .dw 0xe7c0, 0xcb9c, 0xffff, 0xcbff, 0x21, 0 + .dw 0x0000, 0xcc01, 0x003f, 0xcc01, 0x22, 0 + .dw 0x0240, 0xcc01, 0x027f, 0xcc01, 0x22, 0 + .dw 0x0480, 0xcc01, 0x04bf, 0xcc01, 0x22, 0 + .dw 0x06c0, 0xcc01, 0x06ff, 0xcc01, 0x22, 0 + .dw 0x0900, 0xcc01, 0x093f, 0xcc01, 0x22, 0 + .dw 0x0b40, 0xcc01, 0x0b7f, 0xcc01, 0x22, 0 + .dw 0x0d80, 0xcc01, 0x0dbf, 0xcc01, 0x22, 0 + .dw 0x0fc0, 0xcc01, 0x103f, 0xcc01, 0x22, 0 + .dw 0x1240, 0xcc01, 0x127f, 0xcc01, 0x22, 0 + .dw 0x1480, 0xcc01, 0x14bf, 0xcc01, 0x22, 0 + .dw 0x16c0, 0xcc01, 0x16ff, 0xcc01, 0x22, 0 + .dw 0x1900, 0xcc01, 0x193f, 0xcc01, 0x22, 0 + .dw 0x1b40, 0xcc01, 0x1b7f, 0xcc01, 0x22, 0 + .dw 0x1d80, 0xcc01, 0x1dbf, 0xcc01, 0x22, 0 + .dw 0x1fc0, 0xcc01, 0x203f, 0xcc01, 0x22, 0 + .dw 0x2240, 0xcc01, 0x227f, 0xcc01, 0x22, 0 + .dw 0x2480, 0xcc01, 0x24bf, 0xcc01, 0x22, 0 + .dw 0x26c0, 0xcc01, 0x26ff, 0xcc01, 0x22, 0 + .dw 0x2900, 0xcc01, 0x293f, 0xcc01, 0x22, 0 + .dw 0x2b40, 0xcc01, 0x2b7f, 0xcc01, 0x22, 0 + .dw 0x2d80, 0xcc01, 0x2dbf, 0xcc01, 0x22, 0 + .dw 0x2fc0, 0xcc01, 0x303f, 0xcc01, 0x22, 0 + .dw 0x3240, 0xcc01, 0x327f, 0xcc01, 0x22, 0 + .dw 0x3480, 0xcc01, 0x34bf, 0xcc01, 0x22, 0 + .dw 0x36c0, 0xcc01, 0x36ff, 0xcc01, 0x22, 0 + .dw 0x3900, 0xcc01, 0x393f, 0xcc01, 0x22, 0 + .dw 0x3b40, 0xcc01, 0x3b7f, 0xcc01, 0x22, 0 + .dw 0x3d80, 0xcc01, 0x3dbf, 0xcc01, 0x22, 0 + .dw 0x3fc0, 0xcc01, 0x3fff, 0xcc01, 0x22, 0 + .dw 0x4000, 0xcc01, 0x7fff, 0xcc01, 0x21, 0 + .dw 0x8000, 0xcc01, 0x803f, 0xcc01, 0x22, 0 + .dw 0x8240, 0xcc01, 0x827f, 0xcc01, 0x22, 0 + .dw 0x8480, 0xcc01, 0x84bf, 0xcc01, 0x22, 0 + .dw 0x86c0, 0xcc01, 0x86ff, 0xcc01, 0x22, 0 + .dw 0x8900, 0xcc01, 0x893f, 0xcc01, 0x22, 0 + .dw 0x8b40, 0xcc01, 0x8b7f, 0xcc01, 0x22, 0 + .dw 0x8d80, 0xcc01, 0x8dbf, 0xcc01, 0x22, 0 + .dw 0x8fc0, 0xcc01, 0x903f, 0xcc01, 0x22, 0 + .dw 0x9240, 0xcc01, 0x927f, 0xcc01, 0x22, 0 + .dw 0x9480, 0xcc01, 0x94bf, 0xcc01, 0x22, 0 + .dw 0x96c0, 0xcc01, 0x96ff, 0xcc01, 0x22, 0 + .dw 0x9900, 0xcc01, 0x993f, 0xcc01, 0x22, 0 + .dw 0x9b40, 0xcc01, 0x9b7f, 0xcc01, 0x22, 0 + .dw 0x9d80, 0xcc01, 0x9dbf, 0xcc01, 0x22, 0 + .dw 0x9fc0, 0xcc01, 0xa03f, 0xcc01, 0x22, 0 + .dw 0xa240, 0xcc01, 0xa27f, 0xcc01, 0x22, 0 + .dw 0xa480, 0xcc01, 0xa4bf, 0xcc01, 0x22, 0 + .dw 0xa6c0, 0xcc01, 0xa6ff, 0xcc01, 0x22, 0 + .dw 0xa900, 0xcc01, 0xa93f, 0xcc01, 0x22, 0 + .dw 0xab40, 0xcc01, 0xab7f, 0xcc01, 0x22, 0 + .dw 0xad80, 0xcc01, 0xadbf, 0xcc01, 0x22, 0 + .dw 0xafc0, 0xcc01, 0xb03f, 0xcc01, 0x22, 0 + .dw 0xb240, 0xcc01, 0xb27f, 0xcc01, 0x22, 0 + .dw 0xb480, 0xcc01, 0xb4bf, 0xcc01, 0x22, 0 + .dw 0xb6c0, 0xcc01, 0xb6ff, 0xcc01, 0x22, 0 + .dw 0xb900, 0xcc01, 0xb93f, 0xcc01, 0x22, 0 + .dw 0xbb40, 0xcc01, 0xbb7f, 0xcc01, 0x22, 0 + .dw 0xbd80, 0xcc01, 0xbdbf, 0xcc01, 0x22, 0 + .dw 0xbfc0, 0xcc01, 0xc03f, 0xcc01, 0x22, 0 + .dw 0xc240, 0xcc01, 0xc27f, 0xcc01, 0x22, 0 + .dw 0xc480, 0xcc01, 0xc4bf, 0xcc01, 0x22, 0 + .dw 0xc6c0, 0xcc01, 0xc6ff, 0xcc01, 0x22, 0 + .dw 0xc900, 0xcc01, 0xc93f, 0xcc01, 0x22, 0 + .dw 0xcb40, 0xcc01, 0xcb7f, 0xcc01, 0x22, 0 + .dw 0xcd80, 0xcc01, 0xcdbf, 0xcc01, 0x22, 0 + .dw 0xcfc0, 0xcc01, 0xd03f, 0xcc01, 0x22, 0 + .dw 0xd240, 0xcc01, 0xd27f, 0xcc01, 0x22, 0 + .dw 0xd480, 0xcc01, 0xd4bf, 0xcc01, 0x22, 0 + .dw 0xd6c0, 0xcc01, 0xd6ff, 0xcc01, 0x22, 0 + .dw 0xd900, 0xcc01, 0xd93f, 0xcc01, 0x22, 0 + .dw 0xdb40, 0xcc01, 0xdb7f, 0xcc01, 0x22, 0 + .dw 0xdd80, 0xcc01, 0xddbf, 0xcc01, 0x22, 0 + .dw 0xdfc0, 0xcc01, 0xe03f, 0xcc01, 0x22, 0 + .dw 0xe240, 0xcc01, 0xe27f, 0xcc01, 0x22, 0 + .dw 0xe480, 0xcc01, 0xe4bf, 0xcc01, 0x22, 0 + .dw 0xe6c0, 0xcc01, 0xe6ff, 0xcc01, 0x22, 0 + .dw 0xe900, 0xcc01, 0xe93f, 0xcc01, 0x22, 0 + .dw 0xeb40, 0xcc01, 0xeb7f, 0xcc01, 0x22, 0 + .dw 0xed80, 0xcc01, 0xedbf, 0xcc01, 0x22, 0 + .dw 0xefc0, 0xcc01, 0xf03f, 0xcc01, 0x22, 0 + .dw 0xf240, 0xcc01, 0xf27f, 0xcc01, 0x22, 0 + .dw 0xf480, 0xcc01, 0xf4bf, 0xcc01, 0x22, 0 + .dw 0xf6c0, 0xcc01, 0xf6ff, 0xcc01, 0x22, 0 + .dw 0xf900, 0xcc01, 0xf93f, 0xcc01, 0x22, 0 + .dw 0xfb40, 0xcc01, 0xfb7f, 0xcc01, 0x22, 0 + .dw 0xfd80, 0xcc01, 0xfdbf, 0xcc01, 0x22, 0 + .dw 0xffc0, 0xcc01, 0xffff, 0xcc01, 0x22, 0 + .dw 0x1000, 0xcc02, 0x1fff, 0xcc02, 0x21, 0 + .dw 0x3000, 0xcc02, 0x3fff, 0xcc02, 0x21, 0 + .dw 0x5000, 0xcc02, 0x5fff, 0xcc02, 0x21, 0 + .dw 0x7000, 0xcc02, 0x7fff, 0xcc02, 0x21, 0 + .dw 0x9000, 0xcc02, 0x9fff, 0xcc02, 0x21, 0 + .dw 0xb000, 0xcc02, 0xbfff, 0xcc02, 0x21, 0 + .dw 0xd000, 0xcc02, 0xdfff, 0xcc02, 0x21, 0 + .dw 0xf000, 0xcc02, 0xffff, 0xcc02, 0x21, 0 + .dw 0x1000, 0xcc03, 0x1fff, 0xcc03, 0x21, 0 + .dw 0x3000, 0xcc03, 0x3fff, 0xcc03, 0x21, 0 + .dw 0x5000, 0xcc03, 0x5fff, 0xcc03, 0x21, 0 + .dw 0x7000, 0xcc03, 0x7fff, 0xcc03, 0x21, 0 + .dw 0x9000, 0xcc03, 0x9fff, 0xcc03, 0x21, 0 + .dw 0xb000, 0xcc03, 0xbfff, 0xcc03, 0x21, 0 + .dw 0xd000, 0xcc03, 0xdfff, 0xcc03, 0x21, 0 + .dw 0xf000, 0xcc03, 0xffff, 0xcc03, 0x21, 0 + .dw 0x1000, 0xcc04, 0x1fff, 0xcc04, 0x21, 0 + .dw 0x3000, 0xcc04, 0x3fff, 0xcc04, 0x21, 0 + .dw 0x5000, 0xcc04, 0x5fff, 0xcc04, 0x21, 0 + .dw 0x7000, 0xcc04, 0x7fff, 0xcc04, 0x21, 0 + .dw 0x8000, 0xcc04, 0x803f, 0xcc04, 0x22, 0 + .dw 0x8240, 0xcc04, 0x827f, 0xcc04, 0x22, 0 + .dw 0x8480, 0xcc04, 0x84bf, 0xcc04, 0x22, 0 + .dw 0x86c0, 0xcc04, 0x86ff, 0xcc04, 0x22, 0 + .dw 0x8900, 0xcc04, 0x893f, 0xcc04, 0x22, 0 + .dw 0x8b40, 0xcc04, 0x8b7f, 0xcc04, 0x22, 0 + .dw 0x8d80, 0xcc04, 0x8dbf, 0xcc04, 0x22, 0 + .dw 0x8fc0, 0xcc04, 0x8fff, 0xcc04, 0x22, 0 + .dw 0x9000, 0xcc04, 0x9fff, 0xcc04, 0x21, 0 + .dw 0xa000, 0xcc04, 0xa03f, 0xcc04, 0x22, 0 + .dw 0xa240, 0xcc04, 0xa27f, 0xcc04, 0x22, 0 + .dw 0xa480, 0xcc04, 0xa4bf, 0xcc04, 0x22, 0 + .dw 0xa6c0, 0xcc04, 0xa6ff, 0xcc04, 0x22, 0 + .dw 0xa900, 0xcc04, 0xa93f, 0xcc04, 0x22, 0 + .dw 0xab40, 0xcc04, 0xab7f, 0xcc04, 0x22, 0 + .dw 0xad80, 0xcc04, 0xadbf, 0xcc04, 0x22, 0 + .dw 0xafc0, 0xcc04, 0xafff, 0xcc04, 0x22, 0 + .dw 0xb000, 0xcc04, 0xffff, 0xcc04, 0x21, 0 + .dw 0x1000, 0xcc05, 0x3fff, 0xcc05, 0x21, 0 + .dw 0x5000, 0xcc05, 0x8fff, 0xcc05, 0x21, 0 + .dw 0xa000, 0xcc05, 0xcfff, 0xcc05, 0x21, 0 + .dw 0xe000, 0xcc05, 0xffff, 0xcc05, 0x21, 0 + .dw 0x1000, 0xcc06, 0x3fff, 0xcc06, 0x21, 0 + .dw 0x5000, 0xcc06, 0x7fff, 0xcc06, 0x21, 0 + .dw 0x9000, 0xcc06, 0xffff, 0xcc06, 0x21, 0 + .dw 0x1000, 0xcc07, 0x3fff, 0xcc07, 0x21, 0 + .dw 0x5000, 0xcc07, 0x7fff, 0xcc07, 0x21, 0 + .dw 0x9000, 0xcc07, 0xbfff, 0xcc07, 0x21, 0 + .dw 0xd000, 0xcc07, 0xdfff, 0xcc07, 0x21, 0 + .dw 0xf000, 0xcc07, 0xffff, 0xcc07, 0x21, 0 + .dw 0x1000, 0xcc08, 0x1fff, 0xcc08, 0x21, 0 + .dw 0x3000, 0xcc08, 0x3fff, 0xcc08, 0x21, 0 + .dw 0x5000, 0xcc08, 0x5fff, 0xcc08, 0x21, 0 + .dw 0x7000, 0xcc08, 0x7fff, 0xcc08, 0x21, 0 + .dw 0x9000, 0xcc08, 0x9fff, 0xcc08, 0x21, 0 + .dw 0xb000, 0xcc08, 0xbfff, 0xcc08, 0x21, 0 + .dw 0xd000, 0xcc08, 0xdfff, 0xcc08, 0x21, 0 + .dw 0xf000, 0xcc08, 0xffff, 0xcc08, 0x21, 0 + .dw 0x1000, 0xcc09, 0x1fff, 0xcc09, 0x21, 0 + .dw 0x3000, 0xcc09, 0x3fff, 0xcc09, 0x21, 0 + .dw 0x5000, 0xcc09, 0x7fff, 0xcc09, 0x21, 0 + .dw 0x9000, 0xcc09, 0x9fff, 0xcc09, 0x21, 0 + .dw 0xb000, 0xcc09, 0xbfff, 0xcc09, 0x21, 0 + .dw 0xd000, 0xcc09, 0xffff, 0xcc09, 0x21, 0 + .dw 0x1000, 0xcc0a, 0x3fff, 0xcc0a, 0x21, 0 + .dw 0x5000, 0xcc0a, 0xffff, 0xcc0a, 0x21, 0 + .dw 0x1000, 0xcc0b, 0x3fff, 0xcc0b, 0x21, 0 + .dw 0x5000, 0xcc0b, 0x7fff, 0xcc0b, 0x21, 0 + .dw 0x9000, 0xcc0b, 0x9fff, 0xcc0b, 0x21, 0 + .dw 0xb000, 0xcc0b, 0xbfff, 0xcc0b, 0x21, 0 + .dw 0xd000, 0xcc0b, 0xdfff, 0xcc0b, 0x21, 0 + .dw 0xf000, 0xcc0b, 0xffff, 0xcc0b, 0x21, 0 + .dw 0x1000, 0xcc0c, 0x3fff, 0xcc0c, 0x21, 0 + .dw 0x4000, 0xcc0c, 0x403f, 0xcc0c, 0x22, 0 + .dw 0x4240, 0xcc0c, 0x427f, 0xcc0c, 0x22, 0 + .dw 0x4480, 0xcc0c, 0x44bf, 0xcc0c, 0x22, 0 + .dw 0x46c0, 0xcc0c, 0x46ff, 0xcc0c, 0x22, 0 + .dw 0x4900, 0xcc0c, 0x493f, 0xcc0c, 0x22, 0 + .dw 0x4b40, 0xcc0c, 0x4b7f, 0xcc0c, 0x22, 0 + .dw 0x4d80, 0xcc0c, 0x4dbf, 0xcc0c, 0x22, 0 + .dw 0x4fc0, 0xcc0c, 0x4fff, 0xcc0c, 0x22, 0 + .dw 0x5000, 0xcc0c, 0xbfff, 0xcc0c, 0x21, 0 + .dw 0xd000, 0xcc0c, 0xffff, 0xcc0c, 0x21, 0 + .dw 0x0000, 0xcc0d, 0x0fff, 0xcc0d, 0x22, 0 + .dw 0x1000, 0xcc0d, 0x3fff, 0xcc0d, 0x21, 0 + .dw 0x4000, 0xcc0d, 0x4fff, 0xcc0d, 0x22, 0 + .dw 0x5000, 0xcc0d, 0x7fff, 0xcc0d, 0x21, 0 + .dw 0x8000, 0xcc0d, 0x8fff, 0xcc0d, 0x22, 0 + .dw 0x9000, 0xcc0d, 0xbfff, 0xcc0d, 0x21, 0 + .dw 0xc000, 0xcc0d, 0xcfff, 0xcc0d, 0x22, 0 + .dw 0xd000, 0xcc0d, 0xffff, 0xcc0d, 0x21, 0 + .dw 0x1000, 0xcc0e, 0x3fff, 0xcc0e, 0x21, 0 + .dw 0x5000, 0xcc0e, 0xbfff, 0xcc0e, 0x21, 0 + .dw 0xd000, 0xcc0e, 0xbfff, 0xcc0f, 0x21, 0 + .dw 0xd000, 0xcc0f, 0xffff, 0xcc0f, 0x21, 0 + .dw 0x1000, 0xcc10, 0x3fff, 0xcc10, 0x21, 0 + .dw 0x5000, 0xcc10, 0xbfff, 0xcc10, 0x21, 0 + .dw 0xd000, 0xcc10, 0xffff, 0xcc10, 0x21, 0 + .dw 0x0000, 0xcc11, 0x003f, 0xcc11, 0x22, 0 + .dw 0x0240, 0xcc11, 0x027f, 0xcc11, 0x22, 0 + .dw 0x0480, 0xcc11, 0x04bf, 0xcc11, 0x22, 0 + .dw 0x06c0, 0xcc11, 0x06ff, 0xcc11, 0x22, 0 + .dw 0x0900, 0xcc11, 0x093f, 0xcc11, 0x22, 0 + .dw 0x0b40, 0xcc11, 0x0b7f, 0xcc11, 0x22, 0 + .dw 0x0d80, 0xcc11, 0x0dbf, 0xcc11, 0x22, 0 + .dw 0x0fc0, 0xcc11, 0x0fff, 0xcc11, 0x22, 0 + .dw 0x1000, 0xcc11, 0x1fff, 0xcc11, 0x21, 0 + .dw 0x2000, 0xcc11, 0x203f, 0xcc11, 0x22, 0 + .dw 0x2240, 0xcc11, 0x227f, 0xcc11, 0x22, 0 + .dw 0x2480, 0xcc11, 0x24bf, 0xcc11, 0x22, 0 + .dw 0x26c0, 0xcc11, 0x26ff, 0xcc11, 0x22, 0 + .dw 0x2900, 0xcc11, 0x293f, 0xcc11, 0x22, 0 + .dw 0x2b40, 0xcc11, 0x2b7f, 0xcc11, 0x22, 0 + .dw 0x2d80, 0xcc11, 0x2dbf, 0xcc11, 0x22, 0 + .dw 0x2fc0, 0xcc11, 0x2fff, 0xcc11, 0x22, 0 + .dw 0x3000, 0xcc11, 0x3fff, 0xcc11, 0x21, 0 + .dw 0x4000, 0xcc11, 0x403f, 0xcc11, 0x22, 0 + .dw 0x4240, 0xcc11, 0x427f, 0xcc11, 0x22, 0 + .dw 0x4480, 0xcc11, 0x44bf, 0xcc11, 0x22, 0 + .dw 0x46c0, 0xcc11, 0x46ff, 0xcc11, 0x22, 0 + .dw 0x4900, 0xcc11, 0x493f, 0xcc11, 0x22, 0 + .dw 0x4b40, 0xcc11, 0x4b7f, 0xcc11, 0x22, 0 + .dw 0x4d80, 0xcc11, 0x4dbf, 0xcc11, 0x22, 0 + .dw 0x4fc0, 0xcc11, 0x4fff, 0xcc11, 0x22, 0 + .dw 0x5000, 0xcc11, 0x5fff, 0xcc11, 0x21, 0 + .dw 0x6000, 0xcc11, 0x603f, 0xcc11, 0x22, 0 + .dw 0x6240, 0xcc11, 0x627f, 0xcc11, 0x22, 0 + .dw 0x6480, 0xcc11, 0x64bf, 0xcc11, 0x22, 0 + .dw 0x66c0, 0xcc11, 0x66ff, 0xcc11, 0x22, 0 + .dw 0x6900, 0xcc11, 0x693f, 0xcc11, 0x22, 0 + .dw 0x6b40, 0xcc11, 0x6b7f, 0xcc11, 0x22, 0 + .dw 0x6d80, 0xcc11, 0x6dbf, 0xcc11, 0x22, 0 + .dw 0x6fc0, 0xcc11, 0x6fff, 0xcc11, 0x22, 0 + .dw 0x7000, 0xcc11, 0xffff, 0xcc11, 0x21, 0 + .dw 0x0001, 0xcc12, 0x0001, 0xcc12, 0x21, 0 + .dw 0x0003, 0xcc12, 0x000f, 0xcc12, 0x21, 0 + .dw 0x0011, 0xcc12, 0x0011, 0xcc12, 0x21, 0 + .dw 0x0013, 0xcc12, 0x003f, 0xcc12, 0x21, 0 + .dw 0x0041, 0xcc12, 0x0041, 0xcc12, 0x21, 0 + .dw 0x0043, 0xcc12, 0x004f, 0xcc12, 0x21, 0 + .dw 0x0051, 0xcc12, 0x0051, 0xcc12, 0x21, 0 + .dw 0x0053, 0xcc12, 0x007f, 0xcc12, 0x21, 0 + .dw 0x0081, 0xcc12, 0x0081, 0xcc12, 0x21, 0 + .dw 0x0083, 0xcc12, 0x008f, 0xcc12, 0x21, 0 + .dw 0x0091, 0xcc12, 0x0091, 0xcc12, 0x21, 0 + .dw 0x0093, 0xcc12, 0x00bf, 0xcc12, 0x21, 0 + .dw 0x00c1, 0xcc12, 0x00c1, 0xcc12, 0x21, 0 + .dw 0x00c3, 0xcc12, 0x00cf, 0xcc12, 0x21, 0 + .dw 0x00d1, 0xcc12, 0x00d1, 0xcc12, 0x21, 0 + .dw 0x00d3, 0xcc12, 0x00ff, 0xcc12, 0x21, 0 + .dw 0x0101, 0xcc12, 0x0101, 0xcc12, 0x21, 0 + .dw 0x0103, 0xcc12, 0x010f, 0xcc12, 0x21, 0 + .dw 0x0111, 0xcc12, 0x0111, 0xcc12, 0x21, 0 + .dw 0x0113, 0xcc12, 0x013f, 0xcc12, 0x21, 0 + .dw 0x0141, 0xcc12, 0x0141, 0xcc12, 0x21, 0 + .dw 0x0143, 0xcc12, 0x014f, 0xcc12, 0x21, 0 + .dw 0x0151, 0xcc12, 0x0151, 0xcc12, 0x21, 0 + .dw 0x0153, 0xcc12, 0x017f, 0xcc12, 0x21, 0 + .dw 0x0181, 0xcc12, 0x0181, 0xcc12, 0x21, 0 + .dw 0x0183, 0xcc12, 0x018f, 0xcc12, 0x21, 0 + .dw 0x0191, 0xcc12, 0x0191, 0xcc12, 0x21, 0 + .dw 0x0193, 0xcc12, 0x01bf, 0xcc12, 0x21, 0 + .dw 0x01c1, 0xcc12, 0x01c1, 0xcc12, 0x21, 0 + .dw 0x01c3, 0xcc12, 0x01cf, 0xcc12, 0x21, 0 + .dw 0x01d1, 0xcc12, 0x01d1, 0xcc12, 0x21, 0 + .dw 0x01d3, 0xcc12, 0x01ff, 0xcc12, 0x21, 0 + .dw 0x0201, 0xcc12, 0x0201, 0xcc12, 0x21, 0 + .dw 0x0203, 0xcc12, 0x020f, 0xcc12, 0x21, 0 + .dw 0x0211, 0xcc12, 0x0211, 0xcc12, 0x21, 0 + .dw 0x0213, 0xcc12, 0x023f, 0xcc12, 0x21, 0 + .dw 0x0241, 0xcc12, 0x0241, 0xcc12, 0x21, 0 + .dw 0x0243, 0xcc12, 0x024f, 0xcc12, 0x21, 0 + .dw 0x0251, 0xcc12, 0x0251, 0xcc12, 0x21, 0 + .dw 0x0253, 0xcc12, 0x027f, 0xcc12, 0x21, 0 + .dw 0x0281, 0xcc12, 0x0281, 0xcc12, 0x21, 0 + .dw 0x0283, 0xcc12, 0x028f, 0xcc12, 0x21, 0 + .dw 0x0291, 0xcc12, 0x0291, 0xcc12, 0x21, 0 + .dw 0x0293, 0xcc12, 0x02bf, 0xcc12, 0x21, 0 + .dw 0x02c1, 0xcc12, 0x02c1, 0xcc12, 0x21, 0 + .dw 0x02c3, 0xcc12, 0x02cf, 0xcc12, 0x21, 0 + .dw 0x02d1, 0xcc12, 0x02d1, 0xcc12, 0x21, 0 + .dw 0x02d3, 0xcc12, 0x02ff, 0xcc12, 0x21, 0 + .dw 0x0301, 0xcc12, 0x0301, 0xcc12, 0x21, 0 + .dw 0x0303, 0xcc12, 0x030f, 0xcc12, 0x21, 0 + .dw 0x0311, 0xcc12, 0x0311, 0xcc12, 0x21, 0 + .dw 0x0313, 0xcc12, 0x033f, 0xcc12, 0x21, 0 + .dw 0x0341, 0xcc12, 0x0341, 0xcc12, 0x21, 0 + .dw 0x0343, 0xcc12, 0x034f, 0xcc12, 0x21, 0 + .dw 0x0351, 0xcc12, 0x0351, 0xcc12, 0x21, 0 + .dw 0x0353, 0xcc12, 0x037f, 0xcc12, 0x21, 0 + .dw 0x0381, 0xcc12, 0x0381, 0xcc12, 0x21, 0 + .dw 0x0383, 0xcc12, 0x038f, 0xcc12, 0x21, 0 + .dw 0x0391, 0xcc12, 0x0391, 0xcc12, 0x21, 0 + .dw 0x0393, 0xcc12, 0x03bf, 0xcc12, 0x21, 0 + .dw 0x03c1, 0xcc12, 0x03c1, 0xcc12, 0x21, 0 + .dw 0x03c3, 0xcc12, 0x03cf, 0xcc12, 0x21, 0 + .dw 0x03d1, 0xcc12, 0x03d1, 0xcc12, 0x21, 0 + .dw 0x03d3, 0xcc12, 0x03ff, 0xcc12, 0x21, 0 + .dw 0x0401, 0xcc12, 0x0401, 0xcc12, 0x21, 0 + .dw 0x0403, 0xcc12, 0x040f, 0xcc12, 0x21, 0 + .dw 0x0411, 0xcc12, 0x0411, 0xcc12, 0x21, 0 + .dw 0x0413, 0xcc12, 0x043f, 0xcc12, 0x21, 0 + .dw 0x0441, 0xcc12, 0x0441, 0xcc12, 0x21, 0 + .dw 0x0443, 0xcc12, 0x044f, 0xcc12, 0x21, 0 + .dw 0x0451, 0xcc12, 0x0451, 0xcc12, 0x21, 0 + .dw 0x0453, 0xcc12, 0x047f, 0xcc12, 0x21, 0 + .dw 0x0481, 0xcc12, 0x0481, 0xcc12, 0x21, 0 + .dw 0x0483, 0xcc12, 0x048f, 0xcc12, 0x21, 0 + .dw 0x0491, 0xcc12, 0x0491, 0xcc12, 0x21, 0 + .dw 0x0493, 0xcc12, 0x04bf, 0xcc12, 0x21, 0 + .dw 0x04c1, 0xcc12, 0x04c1, 0xcc12, 0x21, 0 + .dw 0x04c3, 0xcc12, 0x04cf, 0xcc12, 0x21, 0 + .dw 0x04d1, 0xcc12, 0x04d1, 0xcc12, 0x21, 0 + .dw 0x04d3, 0xcc12, 0x04ff, 0xcc12, 0x21, 0 + .dw 0x0501, 0xcc12, 0x0501, 0xcc12, 0x21, 0 + .dw 0x0503, 0xcc12, 0x050f, 0xcc12, 0x21, 0 + .dw 0x0511, 0xcc12, 0x0511, 0xcc12, 0x21, 0 + .dw 0x0513, 0xcc12, 0x053f, 0xcc12, 0x21, 0 + .dw 0x0541, 0xcc12, 0x0541, 0xcc12, 0x21, 0 + .dw 0x0543, 0xcc12, 0x054f, 0xcc12, 0x21, 0 + .dw 0x0551, 0xcc12, 0x0551, 0xcc12, 0x21, 0 + .dw 0x0553, 0xcc12, 0x057f, 0xcc12, 0x21, 0 + .dw 0x0581, 0xcc12, 0x0581, 0xcc12, 0x21, 0 + .dw 0x0583, 0xcc12, 0x058f, 0xcc12, 0x21, 0 + .dw 0x0591, 0xcc12, 0x0591, 0xcc12, 0x21, 0 + .dw 0x0593, 0xcc12, 0x05bf, 0xcc12, 0x21, 0 + .dw 0x05c1, 0xcc12, 0x05c1, 0xcc12, 0x21, 0 + .dw 0x05c3, 0xcc12, 0x05cf, 0xcc12, 0x21, 0 + .dw 0x05d1, 0xcc12, 0x05d1, 0xcc12, 0x21, 0 + .dw 0x05d3, 0xcc12, 0x05ff, 0xcc12, 0x21, 0 + .dw 0x0601, 0xcc12, 0x0601, 0xcc12, 0x21, 0 + .dw 0x0603, 0xcc12, 0x060f, 0xcc12, 0x21, 0 + .dw 0x0611, 0xcc12, 0x0611, 0xcc12, 0x21, 0 + .dw 0x0613, 0xcc12, 0x063f, 0xcc12, 0x21, 0 + .dw 0x0641, 0xcc12, 0x0641, 0xcc12, 0x21, 0 + .dw 0x0643, 0xcc12, 0x064f, 0xcc12, 0x21, 0 + .dw 0x0651, 0xcc12, 0x0651, 0xcc12, 0x21, 0 + .dw 0x0653, 0xcc12, 0x067f, 0xcc12, 0x21, 0 + .dw 0x0681, 0xcc12, 0x0681, 0xcc12, 0x21, 0 + .dw 0x0683, 0xcc12, 0x068f, 0xcc12, 0x21, 0 + .dw 0x0691, 0xcc12, 0x0691, 0xcc12, 0x21, 0 + .dw 0x0693, 0xcc12, 0x06bf, 0xcc12, 0x21, 0 + .dw 0x06c1, 0xcc12, 0x06c1, 0xcc12, 0x21, 0 + .dw 0x06c3, 0xcc12, 0x06cf, 0xcc12, 0x21, 0 + .dw 0x06d1, 0xcc12, 0x06d1, 0xcc12, 0x21, 0 + .dw 0x06d3, 0xcc12, 0x06ff, 0xcc12, 0x21, 0 + .dw 0x0701, 0xcc12, 0x0701, 0xcc12, 0x21, 0 + .dw 0x0703, 0xcc12, 0x070f, 0xcc12, 0x21, 0 + .dw 0x0711, 0xcc12, 0x0711, 0xcc12, 0x21, 0 + .dw 0x0713, 0xcc12, 0x073f, 0xcc12, 0x21, 0 + .dw 0x0741, 0xcc12, 0x0741, 0xcc12, 0x21, 0 + .dw 0x0743, 0xcc12, 0x074f, 0xcc12, 0x21, 0 + .dw 0x0751, 0xcc12, 0x0751, 0xcc12, 0x21, 0 + .dw 0x0753, 0xcc12, 0x077f, 0xcc12, 0x21, 0 + .dw 0x0781, 0xcc12, 0x0781, 0xcc12, 0x21, 0 + .dw 0x0783, 0xcc12, 0x078f, 0xcc12, 0x21, 0 + .dw 0x0791, 0xcc12, 0x0791, 0xcc12, 0x21, 0 + .dw 0x0793, 0xcc12, 0x07bf, 0xcc12, 0x21, 0 + .dw 0x07c1, 0xcc12, 0x07c1, 0xcc12, 0x21, 0 + .dw 0x07c3, 0xcc12, 0x07cf, 0xcc12, 0x21, 0 + .dw 0x07d1, 0xcc12, 0x07d1, 0xcc12, 0x21, 0 + .dw 0x07d3, 0xcc12, 0x07ff, 0xcc12, 0x21, 0 + .dw 0x0801, 0xcc12, 0x0801, 0xcc12, 0x21, 0 + .dw 0x0803, 0xcc12, 0x080f, 0xcc12, 0x21, 0 + .dw 0x0811, 0xcc12, 0x0811, 0xcc12, 0x21, 0 + .dw 0x0813, 0xcc12, 0x083f, 0xcc12, 0x21, 0 + .dw 0x0841, 0xcc12, 0x0841, 0xcc12, 0x21, 0 + .dw 0x0843, 0xcc12, 0x084f, 0xcc12, 0x21, 0 + .dw 0x0851, 0xcc12, 0x0851, 0xcc12, 0x21, 0 + .dw 0x0853, 0xcc12, 0x087f, 0xcc12, 0x21, 0 + .dw 0x0881, 0xcc12, 0x0881, 0xcc12, 0x21, 0 + .dw 0x0883, 0xcc12, 0x088f, 0xcc12, 0x21, 0 + .dw 0x0891, 0xcc12, 0x0891, 0xcc12, 0x21, 0 + .dw 0x0893, 0xcc12, 0x08bf, 0xcc12, 0x21, 0 + .dw 0x08c1, 0xcc12, 0x08c1, 0xcc12, 0x21, 0 + .dw 0x08c3, 0xcc12, 0x08cf, 0xcc12, 0x21, 0 + .dw 0x08d1, 0xcc12, 0x08d1, 0xcc12, 0x21, 0 + .dw 0x08d3, 0xcc12, 0x08ff, 0xcc12, 0x21, 0 + .dw 0x0901, 0xcc12, 0x0901, 0xcc12, 0x21, 0 + .dw 0x0903, 0xcc12, 0x090f, 0xcc12, 0x21, 0 + .dw 0x0911, 0xcc12, 0x0911, 0xcc12, 0x21, 0 + .dw 0x0913, 0xcc12, 0x093f, 0xcc12, 0x21, 0 + .dw 0x0941, 0xcc12, 0x0941, 0xcc12, 0x21, 0 + .dw 0x0943, 0xcc12, 0x094f, 0xcc12, 0x21, 0 + .dw 0x0951, 0xcc12, 0x0951, 0xcc12, 0x21, 0 + .dw 0x0953, 0xcc12, 0x097f, 0xcc12, 0x21, 0 + .dw 0x0981, 0xcc12, 0x0981, 0xcc12, 0x21, 0 + .dw 0x0983, 0xcc12, 0x098f, 0xcc12, 0x21, 0 + .dw 0x0991, 0xcc12, 0x0991, 0xcc12, 0x21, 0 + .dw 0x0993, 0xcc12, 0x09bf, 0xcc12, 0x21, 0 + .dw 0x09c1, 0xcc12, 0x09c1, 0xcc12, 0x21, 0 + .dw 0x09c3, 0xcc12, 0x09cf, 0xcc12, 0x21, 0 + .dw 0x09d1, 0xcc12, 0x09d1, 0xcc12, 0x21, 0 + .dw 0x09d3, 0xcc12, 0x09ff, 0xcc12, 0x21, 0 + .dw 0x0a01, 0xcc12, 0x0a01, 0xcc12, 0x21, 0 + .dw 0x0a03, 0xcc12, 0x0a0f, 0xcc12, 0x21, 0 + .dw 0x0a11, 0xcc12, 0x0a11, 0xcc12, 0x21, 0 + .dw 0x0a13, 0xcc12, 0x0a3f, 0xcc12, 0x21, 0 + .dw 0x0a41, 0xcc12, 0x0a41, 0xcc12, 0x21, 0 + .dw 0x0a43, 0xcc12, 0x0a4f, 0xcc12, 0x21, 0 + .dw 0x0a51, 0xcc12, 0x0a51, 0xcc12, 0x21, 0 + .dw 0x0a53, 0xcc12, 0x0a7f, 0xcc12, 0x21, 0 + .dw 0x0a81, 0xcc12, 0x0a81, 0xcc12, 0x21, 0 + .dw 0x0a83, 0xcc12, 0x0a8f, 0xcc12, 0x21, 0 + .dw 0x0a91, 0xcc12, 0x0a91, 0xcc12, 0x21, 0 + .dw 0x0a93, 0xcc12, 0x0abf, 0xcc12, 0x21, 0 + .dw 0x0ac1, 0xcc12, 0x0ac1, 0xcc12, 0x21, 0 + .dw 0x0ac3, 0xcc12, 0x0acf, 0xcc12, 0x21, 0 + .dw 0x0ad1, 0xcc12, 0x0ad1, 0xcc12, 0x21, 0 + .dw 0x0ad3, 0xcc12, 0x0aff, 0xcc12, 0x21, 0 + .dw 0x0b01, 0xcc12, 0x0b01, 0xcc12, 0x21, 0 + .dw 0x0b03, 0xcc12, 0x0b0f, 0xcc12, 0x21, 0 + .dw 0x0b11, 0xcc12, 0x0b11, 0xcc12, 0x21, 0 + .dw 0x0b13, 0xcc12, 0x0b3f, 0xcc12, 0x21, 0 + .dw 0x0b41, 0xcc12, 0x0b41, 0xcc12, 0x21, 0 + .dw 0x0b43, 0xcc12, 0x0b4f, 0xcc12, 0x21, 0 + .dw 0x0b51, 0xcc12, 0x0b51, 0xcc12, 0x21, 0 + .dw 0x0b53, 0xcc12, 0x0b7f, 0xcc12, 0x21, 0 + .dw 0x0b81, 0xcc12, 0x0b81, 0xcc12, 0x21, 0 + .dw 0x0b83, 0xcc12, 0x0b8f, 0xcc12, 0x21, 0 + .dw 0x0b91, 0xcc12, 0x0b91, 0xcc12, 0x21, 0 + .dw 0x0b93, 0xcc12, 0x0bbf, 0xcc12, 0x21, 0 + .dw 0x0bc1, 0xcc12, 0x0bc1, 0xcc12, 0x21, 0 + .dw 0x0bc3, 0xcc12, 0x0bcf, 0xcc12, 0x21, 0 + .dw 0x0bd1, 0xcc12, 0x0bd1, 0xcc12, 0x21, 0 + .dw 0x0bd3, 0xcc12, 0x0bff, 0xcc12, 0x21, 0 + .dw 0x0c01, 0xcc12, 0x0c01, 0xcc12, 0x21, 0 + .dw 0x0c03, 0xcc12, 0x0c0f, 0xcc12, 0x21, 0 + .dw 0x0c11, 0xcc12, 0x0c11, 0xcc12, 0x21, 0 + .dw 0x0c13, 0xcc12, 0x0c3f, 0xcc12, 0x21, 0 + .dw 0x0c41, 0xcc12, 0x0c41, 0xcc12, 0x21, 0 + .dw 0x0c43, 0xcc12, 0x0c4f, 0xcc12, 0x21, 0 + .dw 0x0c51, 0xcc12, 0x0c51, 0xcc12, 0x21, 0 + .dw 0x0c53, 0xcc12, 0x0c7f, 0xcc12, 0x21, 0 + .dw 0x0c81, 0xcc12, 0x0c81, 0xcc12, 0x21, 0 + .dw 0x0c83, 0xcc12, 0x0c8f, 0xcc12, 0x21, 0 + .dw 0x0c91, 0xcc12, 0x0c91, 0xcc12, 0x21, 0 + .dw 0x0c93, 0xcc12, 0x0cbf, 0xcc12, 0x21, 0 + .dw 0x0cc1, 0xcc12, 0x0cc1, 0xcc12, 0x21, 0 + .dw 0x0cc3, 0xcc12, 0x0ccf, 0xcc12, 0x21, 0 + .dw 0x0cd1, 0xcc12, 0x0cd1, 0xcc12, 0x21, 0 + .dw 0x0cd3, 0xcc12, 0x0cff, 0xcc12, 0x21, 0 + .dw 0x0d01, 0xcc12, 0x0d01, 0xcc12, 0x21, 0 + .dw 0x0d03, 0xcc12, 0x0d0f, 0xcc12, 0x21, 0 + .dw 0x0d11, 0xcc12, 0x0d11, 0xcc12, 0x21, 0 + .dw 0x0d13, 0xcc12, 0x0d3f, 0xcc12, 0x21, 0 + .dw 0x0d41, 0xcc12, 0x0d41, 0xcc12, 0x21, 0 + .dw 0x0d43, 0xcc12, 0x0d4f, 0xcc12, 0x21, 0 + .dw 0x0d51, 0xcc12, 0x0d51, 0xcc12, 0x21, 0 + .dw 0x0d53, 0xcc12, 0x0d7f, 0xcc12, 0x21, 0 + .dw 0x0d81, 0xcc12, 0x0d81, 0xcc12, 0x21, 0 + .dw 0x0d83, 0xcc12, 0x0d8f, 0xcc12, 0x21, 0 + .dw 0x0d91, 0xcc12, 0x0d91, 0xcc12, 0x21, 0 + .dw 0x0d93, 0xcc12, 0x0dbf, 0xcc12, 0x21, 0 + .dw 0x0dc1, 0xcc12, 0x0dc1, 0xcc12, 0x21, 0 + .dw 0x0dc3, 0xcc12, 0x0dcf, 0xcc12, 0x21, 0 + .dw 0x0dd1, 0xcc12, 0x0dd1, 0xcc12, 0x21, 0 + .dw 0x0dd3, 0xcc12, 0x0dff, 0xcc12, 0x21, 0 + .dw 0x0e01, 0xcc12, 0x0e01, 0xcc12, 0x21, 0 + .dw 0x0e03, 0xcc12, 0x0e0f, 0xcc12, 0x21, 0 + .dw 0x0e11, 0xcc12, 0x0e11, 0xcc12, 0x21, 0 + .dw 0x0e13, 0xcc12, 0x0e3f, 0xcc12, 0x21, 0 + .dw 0x0e41, 0xcc12, 0x0e41, 0xcc12, 0x21, 0 + .dw 0x0e43, 0xcc12, 0x0e4f, 0xcc12, 0x21, 0 + .dw 0x0e51, 0xcc12, 0x0e51, 0xcc12, 0x21, 0 + .dw 0x0e53, 0xcc12, 0x0e7f, 0xcc12, 0x21, 0 + .dw 0x0e81, 0xcc12, 0x0e81, 0xcc12, 0x21, 0 + .dw 0x0e83, 0xcc12, 0x0e8f, 0xcc12, 0x21, 0 + .dw 0x0e91, 0xcc12, 0x0e91, 0xcc12, 0x21, 0 + .dw 0x0e93, 0xcc12, 0x0ebf, 0xcc12, 0x21, 0 + .dw 0x0ec1, 0xcc12, 0x0ec1, 0xcc12, 0x21, 0 + .dw 0x0ec3, 0xcc12, 0x0ecf, 0xcc12, 0x21, 0 + .dw 0x0ed1, 0xcc12, 0x0ed1, 0xcc12, 0x21, 0 + .dw 0x0ed3, 0xcc12, 0x0eff, 0xcc12, 0x21, 0 + .dw 0x0f01, 0xcc12, 0x0f01, 0xcc12, 0x21, 0 + .dw 0x0f03, 0xcc12, 0x0f0f, 0xcc12, 0x21, 0 + .dw 0x0f11, 0xcc12, 0x0f11, 0xcc12, 0x21, 0 + .dw 0x0f13, 0xcc12, 0x0f3f, 0xcc12, 0x21, 0 + .dw 0x0f41, 0xcc12, 0x0f41, 0xcc12, 0x21, 0 + .dw 0x0f43, 0xcc12, 0x0f4f, 0xcc12, 0x21, 0 + .dw 0x0f51, 0xcc12, 0x0f51, 0xcc12, 0x21, 0 + .dw 0x0f53, 0xcc12, 0x0f7f, 0xcc12, 0x21, 0 + .dw 0x0f81, 0xcc12, 0x0f81, 0xcc12, 0x21, 0 + .dw 0x0f83, 0xcc12, 0x0f8f, 0xcc12, 0x21, 0 + .dw 0x0f91, 0xcc12, 0x0f91, 0xcc12, 0x21, 0 + .dw 0x0f93, 0xcc12, 0x0fbf, 0xcc12, 0x21, 0 + .dw 0x0fc1, 0xcc12, 0x0fc1, 0xcc12, 0x21, 0 + .dw 0x0fc3, 0xcc12, 0x0fcf, 0xcc12, 0x21, 0 + .dw 0x0fd1, 0xcc12, 0x0fd1, 0xcc12, 0x21, 0 + .dw 0x0fd3, 0xcc12, 0x1fff, 0xcc12, 0x21, 0 + .dw 0x2001, 0xcc12, 0x2001, 0xcc12, 0x21, 0 + .dw 0x2003, 0xcc12, 0x200f, 0xcc12, 0x21, 0 + .dw 0x2011, 0xcc12, 0x2011, 0xcc12, 0x21, 0 + .dw 0x2013, 0xcc12, 0x203f, 0xcc12, 0x21, 0 + .dw 0x2041, 0xcc12, 0x2041, 0xcc12, 0x21, 0 + .dw 0x2043, 0xcc12, 0x204f, 0xcc12, 0x21, 0 + .dw 0x2051, 0xcc12, 0x2051, 0xcc12, 0x21, 0 + .dw 0x2053, 0xcc12, 0x207f, 0xcc12, 0x21, 0 + .dw 0x2081, 0xcc12, 0x2081, 0xcc12, 0x21, 0 + .dw 0x2083, 0xcc12, 0x208f, 0xcc12, 0x21, 0 + .dw 0x2091, 0xcc12, 0x2091, 0xcc12, 0x21, 0 + .dw 0x2093, 0xcc12, 0x20bf, 0xcc12, 0x21, 0 + .dw 0x20c1, 0xcc12, 0x20c1, 0xcc12, 0x21, 0 + .dw 0x20c3, 0xcc12, 0x20cf, 0xcc12, 0x21, 0 + .dw 0x20d1, 0xcc12, 0x20d1, 0xcc12, 0x21, 0 + .dw 0x20d3, 0xcc12, 0x20ff, 0xcc12, 0x21, 0 + .dw 0x2101, 0xcc12, 0x2101, 0xcc12, 0x21, 0 + .dw 0x2103, 0xcc12, 0x210f, 0xcc12, 0x21, 0 + .dw 0x2111, 0xcc12, 0x2111, 0xcc12, 0x21, 0 + .dw 0x2113, 0xcc12, 0x213f, 0xcc12, 0x21, 0 + .dw 0x2141, 0xcc12, 0x2141, 0xcc12, 0x21, 0 + .dw 0x2143, 0xcc12, 0x214f, 0xcc12, 0x21, 0 + .dw 0x2151, 0xcc12, 0x2151, 0xcc12, 0x21, 0 + .dw 0x2153, 0xcc12, 0x217f, 0xcc12, 0x21, 0 + .dw 0x2181, 0xcc12, 0x2181, 0xcc12, 0x21, 0 + .dw 0x2183, 0xcc12, 0x218f, 0xcc12, 0x21, 0 + .dw 0x2191, 0xcc12, 0x2191, 0xcc12, 0x21, 0 + .dw 0x2193, 0xcc12, 0x21bf, 0xcc12, 0x21, 0 + .dw 0x21c1, 0xcc12, 0x21c1, 0xcc12, 0x21, 0 + .dw 0x21c3, 0xcc12, 0x21cf, 0xcc12, 0x21, 0 + .dw 0x21d1, 0xcc12, 0x21d1, 0xcc12, 0x21, 0 + .dw 0x21d3, 0xcc12, 0x21ff, 0xcc12, 0x21, 0 + .dw 0x2201, 0xcc12, 0x2201, 0xcc12, 0x21, 0 + .dw 0x2203, 0xcc12, 0x220f, 0xcc12, 0x21, 0 + .dw 0x2211, 0xcc12, 0x2211, 0xcc12, 0x21, 0 + .dw 0x2213, 0xcc12, 0x223f, 0xcc12, 0x21, 0 + .dw 0x2241, 0xcc12, 0x2241, 0xcc12, 0x21, 0 + .dw 0x2243, 0xcc12, 0x224f, 0xcc12, 0x21, 0 + .dw 0x2251, 0xcc12, 0x2251, 0xcc12, 0x21, 0 + .dw 0x2253, 0xcc12, 0x227f, 0xcc12, 0x21, 0 + .dw 0x2281, 0xcc12, 0x2281, 0xcc12, 0x21, 0 + .dw 0x2283, 0xcc12, 0x228f, 0xcc12, 0x21, 0 + .dw 0x2291, 0xcc12, 0x2291, 0xcc12, 0x21, 0 + .dw 0x2293, 0xcc12, 0x22bf, 0xcc12, 0x21, 0 + .dw 0x22c1, 0xcc12, 0x22c1, 0xcc12, 0x21, 0 + .dw 0x22c3, 0xcc12, 0x22cf, 0xcc12, 0x21, 0 + .dw 0x22d1, 0xcc12, 0x22d1, 0xcc12, 0x21, 0 + .dw 0x22d3, 0xcc12, 0x22ff, 0xcc12, 0x21, 0 + .dw 0x2301, 0xcc12, 0x2301, 0xcc12, 0x21, 0 + .dw 0x2303, 0xcc12, 0x230f, 0xcc12, 0x21, 0 + .dw 0x2311, 0xcc12, 0x2311, 0xcc12, 0x21, 0 + .dw 0x2313, 0xcc12, 0x233f, 0xcc12, 0x21, 0 + .dw 0x2341, 0xcc12, 0x2341, 0xcc12, 0x21, 0 + .dw 0x2343, 0xcc12, 0x234f, 0xcc12, 0x21, 0 + .dw 0x2351, 0xcc12, 0x2351, 0xcc12, 0x21, 0 + .dw 0x2353, 0xcc12, 0x237f, 0xcc12, 0x21, 0 + .dw 0x2381, 0xcc12, 0x2381, 0xcc12, 0x21, 0 + .dw 0x2383, 0xcc12, 0x238f, 0xcc12, 0x21, 0 + .dw 0x2391, 0xcc12, 0x2391, 0xcc12, 0x21, 0 + .dw 0x2393, 0xcc12, 0x23bf, 0xcc12, 0x21, 0 + .dw 0x23c1, 0xcc12, 0x23c1, 0xcc12, 0x21, 0 + .dw 0x23c3, 0xcc12, 0x23cf, 0xcc12, 0x21, 0 + .dw 0x23d1, 0xcc12, 0x23d1, 0xcc12, 0x21, 0 + .dw 0x23d3, 0xcc12, 0x23ff, 0xcc12, 0x21, 0 + .dw 0x2401, 0xcc12, 0x2401, 0xcc12, 0x21, 0 + .dw 0x2403, 0xcc12, 0x240f, 0xcc12, 0x21, 0 + .dw 0x2411, 0xcc12, 0x2411, 0xcc12, 0x21, 0 + .dw 0x2413, 0xcc12, 0x243f, 0xcc12, 0x21, 0 + .dw 0x2441, 0xcc12, 0x2441, 0xcc12, 0x21, 0 + .dw 0x2443, 0xcc12, 0x244f, 0xcc12, 0x21, 0 + .dw 0x2451, 0xcc12, 0x2451, 0xcc12, 0x21, 0 + .dw 0x2453, 0xcc12, 0x247f, 0xcc12, 0x21, 0 + .dw 0x2481, 0xcc12, 0x2481, 0xcc12, 0x21, 0 + .dw 0x2483, 0xcc12, 0x248f, 0xcc12, 0x21, 0 + .dw 0x2491, 0xcc12, 0x2491, 0xcc12, 0x21, 0 + .dw 0x2493, 0xcc12, 0x24bf, 0xcc12, 0x21, 0 + .dw 0x24c1, 0xcc12, 0x24c1, 0xcc12, 0x21, 0 + .dw 0x24c3, 0xcc12, 0x24cf, 0xcc12, 0x21, 0 + .dw 0x24d1, 0xcc12, 0x24d1, 0xcc12, 0x21, 0 + .dw 0x24d3, 0xcc12, 0x24ff, 0xcc12, 0x21, 0 + .dw 0x2501, 0xcc12, 0x2501, 0xcc12, 0x21, 0 + .dw 0x2503, 0xcc12, 0x250f, 0xcc12, 0x21, 0 + .dw 0x2511, 0xcc12, 0x2511, 0xcc12, 0x21, 0 + .dw 0x2513, 0xcc12, 0x253f, 0xcc12, 0x21, 0 + .dw 0x2541, 0xcc12, 0x2541, 0xcc12, 0x21, 0 + .dw 0x2543, 0xcc12, 0x254f, 0xcc12, 0x21, 0 + .dw 0x2551, 0xcc12, 0x2551, 0xcc12, 0x21, 0 + .dw 0x2553, 0xcc12, 0x257f, 0xcc12, 0x21, 0 + .dw 0x2581, 0xcc12, 0x2581, 0xcc12, 0x21, 0 + .dw 0x2583, 0xcc12, 0x258f, 0xcc12, 0x21, 0 + .dw 0x2591, 0xcc12, 0x2591, 0xcc12, 0x21, 0 + .dw 0x2593, 0xcc12, 0x25bf, 0xcc12, 0x21, 0 + .dw 0x25c1, 0xcc12, 0x25c1, 0xcc12, 0x21, 0 + .dw 0x25c3, 0xcc12, 0x25cf, 0xcc12, 0x21, 0 + .dw 0x25d1, 0xcc12, 0x25d1, 0xcc12, 0x21, 0 + .dw 0x25d3, 0xcc12, 0x25ff, 0xcc12, 0x21, 0 + .dw 0x2601, 0xcc12, 0x2601, 0xcc12, 0x21, 0 + .dw 0x2603, 0xcc12, 0x260f, 0xcc12, 0x21, 0 + .dw 0x2611, 0xcc12, 0x2611, 0xcc12, 0x21, 0 + .dw 0x2613, 0xcc12, 0x263f, 0xcc12, 0x21, 0 + .dw 0x2641, 0xcc12, 0x2641, 0xcc12, 0x21, 0 + .dw 0x2643, 0xcc12, 0x264f, 0xcc12, 0x21, 0 + .dw 0x2651, 0xcc12, 0x2651, 0xcc12, 0x21, 0 + .dw 0x2653, 0xcc12, 0x267f, 0xcc12, 0x21, 0 + .dw 0x2681, 0xcc12, 0x2681, 0xcc12, 0x21, 0 + .dw 0x2683, 0xcc12, 0x268f, 0xcc12, 0x21, 0 + .dw 0x2691, 0xcc12, 0x2691, 0xcc12, 0x21, 0 + .dw 0x2693, 0xcc12, 0x26bf, 0xcc12, 0x21, 0 + .dw 0x26c1, 0xcc12, 0x26c1, 0xcc12, 0x21, 0 + .dw 0x26c3, 0xcc12, 0x26cf, 0xcc12, 0x21, 0 + .dw 0x26d1, 0xcc12, 0x26d1, 0xcc12, 0x21, 0 + .dw 0x26d3, 0xcc12, 0x26ff, 0xcc12, 0x21, 0 + .dw 0x2701, 0xcc12, 0x2701, 0xcc12, 0x21, 0 + .dw 0x2703, 0xcc12, 0x270f, 0xcc12, 0x21, 0 + .dw 0x2711, 0xcc12, 0x2711, 0xcc12, 0x21, 0 + .dw 0x2713, 0xcc12, 0x273f, 0xcc12, 0x21, 0 + .dw 0x2741, 0xcc12, 0x2741, 0xcc12, 0x21, 0 + .dw 0x2743, 0xcc12, 0x274f, 0xcc12, 0x21, 0 + .dw 0x2751, 0xcc12, 0x2751, 0xcc12, 0x21, 0 + .dw 0x2753, 0xcc12, 0x277f, 0xcc12, 0x21, 0 + .dw 0x2781, 0xcc12, 0x2781, 0xcc12, 0x21, 0 + .dw 0x2783, 0xcc12, 0x278f, 0xcc12, 0x21, 0 + .dw 0x2791, 0xcc12, 0x2791, 0xcc12, 0x21, 0 + .dw 0x2793, 0xcc12, 0x27bf, 0xcc12, 0x21, 0 + .dw 0x27c1, 0xcc12, 0x27c1, 0xcc12, 0x21, 0 + .dw 0x27c3, 0xcc12, 0x27cf, 0xcc12, 0x21, 0 + .dw 0x27d1, 0xcc12, 0x27d1, 0xcc12, 0x21, 0 + .dw 0x27d3, 0xcc12, 0x27ff, 0xcc12, 0x21, 0 + .dw 0x2801, 0xcc12, 0x2801, 0xcc12, 0x21, 0 + .dw 0x2803, 0xcc12, 0x280f, 0xcc12, 0x21, 0 + .dw 0x2811, 0xcc12, 0x2811, 0xcc12, 0x21, 0 + .dw 0x2813, 0xcc12, 0x283f, 0xcc12, 0x21, 0 + .dw 0x2841, 0xcc12, 0x2841, 0xcc12, 0x21, 0 + .dw 0x2843, 0xcc12, 0x284f, 0xcc12, 0x21, 0 + .dw 0x2851, 0xcc12, 0x2851, 0xcc12, 0x21, 0 + .dw 0x2853, 0xcc12, 0x287f, 0xcc12, 0x21, 0 + .dw 0x2881, 0xcc12, 0x2881, 0xcc12, 0x21, 0 + .dw 0x2883, 0xcc12, 0x288f, 0xcc12, 0x21, 0 + .dw 0x2891, 0xcc12, 0x2891, 0xcc12, 0x21, 0 + .dw 0x2893, 0xcc12, 0x28bf, 0xcc12, 0x21, 0 + .dw 0x28c1, 0xcc12, 0x28c1, 0xcc12, 0x21, 0 + .dw 0x28c3, 0xcc12, 0x28cf, 0xcc12, 0x21, 0 + .dw 0x28d1, 0xcc12, 0x28d1, 0xcc12, 0x21, 0 + .dw 0x28d3, 0xcc12, 0x28ff, 0xcc12, 0x21, 0 + .dw 0x2901, 0xcc12, 0x2901, 0xcc12, 0x21, 0 + .dw 0x2903, 0xcc12, 0x290f, 0xcc12, 0x21, 0 + .dw 0x2911, 0xcc12, 0x2911, 0xcc12, 0x21, 0 + .dw 0x2913, 0xcc12, 0x293f, 0xcc12, 0x21, 0 + .dw 0x2941, 0xcc12, 0x2941, 0xcc12, 0x21, 0 + .dw 0x2943, 0xcc12, 0x294f, 0xcc12, 0x21, 0 + .dw 0x2951, 0xcc12, 0x2951, 0xcc12, 0x21, 0 + .dw 0x2953, 0xcc12, 0x297f, 0xcc12, 0x21, 0 + .dw 0x2981, 0xcc12, 0x2981, 0xcc12, 0x21, 0 + .dw 0x2983, 0xcc12, 0x298f, 0xcc12, 0x21, 0 + .dw 0x2991, 0xcc12, 0x2991, 0xcc12, 0x21, 0 + .dw 0x2993, 0xcc12, 0x29bf, 0xcc12, 0x21, 0 + .dw 0x29c1, 0xcc12, 0x29c1, 0xcc12, 0x21, 0 + .dw 0x29c3, 0xcc12, 0x29cf, 0xcc12, 0x21, 0 + .dw 0x29d1, 0xcc12, 0x29d1, 0xcc12, 0x21, 0 + .dw 0x29d3, 0xcc12, 0x29ff, 0xcc12, 0x21, 0 + .dw 0x2a01, 0xcc12, 0x2a01, 0xcc12, 0x21, 0 + .dw 0x2a03, 0xcc12, 0x2a0f, 0xcc12, 0x21, 0 + .dw 0x2a11, 0xcc12, 0x2a11, 0xcc12, 0x21, 0 + .dw 0x2a13, 0xcc12, 0x2a3f, 0xcc12, 0x21, 0 + .dw 0x2a41, 0xcc12, 0x2a41, 0xcc12, 0x21, 0 + .dw 0x2a43, 0xcc12, 0x2a4f, 0xcc12, 0x21, 0 + .dw 0x2a51, 0xcc12, 0x2a51, 0xcc12, 0x21, 0 + .dw 0x2a53, 0xcc12, 0x2a7f, 0xcc12, 0x21, 0 + .dw 0x2a81, 0xcc12, 0x2a81, 0xcc12, 0x21, 0 + .dw 0x2a83, 0xcc12, 0x2a8f, 0xcc12, 0x21, 0 + .dw 0x2a91, 0xcc12, 0x2a91, 0xcc12, 0x21, 0 + .dw 0x2a93, 0xcc12, 0x2abf, 0xcc12, 0x21, 0 + .dw 0x2ac1, 0xcc12, 0x2ac1, 0xcc12, 0x21, 0 + .dw 0x2ac3, 0xcc12, 0x2acf, 0xcc12, 0x21, 0 + .dw 0x2ad1, 0xcc12, 0x2ad1, 0xcc12, 0x21, 0 + .dw 0x2ad3, 0xcc12, 0x2aff, 0xcc12, 0x21, 0 + .dw 0x2b01, 0xcc12, 0x2b01, 0xcc12, 0x21, 0 + .dw 0x2b03, 0xcc12, 0x2b0f, 0xcc12, 0x21, 0 + .dw 0x2b11, 0xcc12, 0x2b11, 0xcc12, 0x21, 0 + .dw 0x2b13, 0xcc12, 0x2b3f, 0xcc12, 0x21, 0 + .dw 0x2b41, 0xcc12, 0x2b41, 0xcc12, 0x21, 0 + .dw 0x2b43, 0xcc12, 0x2b4f, 0xcc12, 0x21, 0 + .dw 0x2b51, 0xcc12, 0x2b51, 0xcc12, 0x21, 0 + .dw 0x2b53, 0xcc12, 0x2b7f, 0xcc12, 0x21, 0 + .dw 0x2b81, 0xcc12, 0x2b81, 0xcc12, 0x21, 0 + .dw 0x2b83, 0xcc12, 0x2b8f, 0xcc12, 0x21, 0 + .dw 0x2b91, 0xcc12, 0x2b91, 0xcc12, 0x21, 0 + .dw 0x2b93, 0xcc12, 0x2bbf, 0xcc12, 0x21, 0 + .dw 0x2bc1, 0xcc12, 0x2bc1, 0xcc12, 0x21, 0 + .dw 0x2bc3, 0xcc12, 0x2bcf, 0xcc12, 0x21, 0 + .dw 0x2bd1, 0xcc12, 0x2bd1, 0xcc12, 0x21, 0 + .dw 0x2bd3, 0xcc12, 0x2bff, 0xcc12, 0x21, 0 + .dw 0x2c01, 0xcc12, 0x2c01, 0xcc12, 0x21, 0 + .dw 0x2c03, 0xcc12, 0x2c0f, 0xcc12, 0x21, 0 + .dw 0x2c11, 0xcc12, 0x2c11, 0xcc12, 0x21, 0 + .dw 0x2c13, 0xcc12, 0x2c3f, 0xcc12, 0x21, 0 + .dw 0x2c41, 0xcc12, 0x2c41, 0xcc12, 0x21, 0 + .dw 0x2c43, 0xcc12, 0x2c4f, 0xcc12, 0x21, 0 + .dw 0x2c51, 0xcc12, 0x2c51, 0xcc12, 0x21, 0 + .dw 0x2c53, 0xcc12, 0x2c7f, 0xcc12, 0x21, 0 + .dw 0x2c81, 0xcc12, 0x2c81, 0xcc12, 0x21, 0 + .dw 0x2c83, 0xcc12, 0x2c8f, 0xcc12, 0x21, 0 + .dw 0x2c91, 0xcc12, 0x2c91, 0xcc12, 0x21, 0 + .dw 0x2c93, 0xcc12, 0x2cbf, 0xcc12, 0x21, 0 + .dw 0x2cc1, 0xcc12, 0x2cc1, 0xcc12, 0x21, 0 + .dw 0x2cc3, 0xcc12, 0x2ccf, 0xcc12, 0x21, 0 + .dw 0x2cd1, 0xcc12, 0x2cd1, 0xcc12, 0x21, 0 + .dw 0x2cd3, 0xcc12, 0x2cff, 0xcc12, 0x21, 0 + .dw 0x2d01, 0xcc12, 0x2d01, 0xcc12, 0x21, 0 + .dw 0x2d03, 0xcc12, 0x2d0f, 0xcc12, 0x21, 0 + .dw 0x2d11, 0xcc12, 0x2d11, 0xcc12, 0x21, 0 + .dw 0x2d13, 0xcc12, 0x2d3f, 0xcc12, 0x21, 0 + .dw 0x2d41, 0xcc12, 0x2d41, 0xcc12, 0x21, 0 + .dw 0x2d43, 0xcc12, 0x2d4f, 0xcc12, 0x21, 0 + .dw 0x2d51, 0xcc12, 0x2d51, 0xcc12, 0x21, 0 + .dw 0x2d53, 0xcc12, 0x2d7f, 0xcc12, 0x21, 0 + .dw 0x2d81, 0xcc12, 0x2d81, 0xcc12, 0x21, 0 + .dw 0x2d83, 0xcc12, 0x2d8f, 0xcc12, 0x21, 0 + .dw 0x2d91, 0xcc12, 0x2d91, 0xcc12, 0x21, 0 + .dw 0x2d93, 0xcc12, 0x2dbf, 0xcc12, 0x21, 0 + .dw 0x2dc1, 0xcc12, 0x2dc1, 0xcc12, 0x21, 0 + .dw 0x2dc3, 0xcc12, 0x2dcf, 0xcc12, 0x21, 0 + .dw 0x2dd1, 0xcc12, 0x2dd1, 0xcc12, 0x21, 0 + .dw 0x2dd3, 0xcc12, 0x2dff, 0xcc12, 0x21, 0 + .dw 0x2e01, 0xcc12, 0x2e01, 0xcc12, 0x21, 0 + .dw 0x2e03, 0xcc12, 0x2e0f, 0xcc12, 0x21, 0 + .dw 0x2e11, 0xcc12, 0x2e11, 0xcc12, 0x21, 0 + .dw 0x2e13, 0xcc12, 0x2e3f, 0xcc12, 0x21, 0 + .dw 0x2e41, 0xcc12, 0x2e41, 0xcc12, 0x21, 0 + .dw 0x2e43, 0xcc12, 0x2e4f, 0xcc12, 0x21, 0 + .dw 0x2e51, 0xcc12, 0x2e51, 0xcc12, 0x21, 0 + .dw 0x2e53, 0xcc12, 0x2e7f, 0xcc12, 0x21, 0 + .dw 0x2e81, 0xcc12, 0x2e81, 0xcc12, 0x21, 0 + .dw 0x2e83, 0xcc12, 0x2e8f, 0xcc12, 0x21, 0 + .dw 0x2e91, 0xcc12, 0x2e91, 0xcc12, 0x21, 0 + .dw 0x2e93, 0xcc12, 0x2ebf, 0xcc12, 0x21, 0 + .dw 0x2ec1, 0xcc12, 0x2ec1, 0xcc12, 0x21, 0 + .dw 0x2ec3, 0xcc12, 0x2ecf, 0xcc12, 0x21, 0 + .dw 0x2ed1, 0xcc12, 0x2ed1, 0xcc12, 0x21, 0 + .dw 0x2ed3, 0xcc12, 0x2eff, 0xcc12, 0x21, 0 + .dw 0x2f01, 0xcc12, 0x2f01, 0xcc12, 0x21, 0 + .dw 0x2f03, 0xcc12, 0x2f0f, 0xcc12, 0x21, 0 + .dw 0x2f11, 0xcc12, 0x2f11, 0xcc12, 0x21, 0 + .dw 0x2f13, 0xcc12, 0x2f3f, 0xcc12, 0x21, 0 + .dw 0x2f41, 0xcc12, 0x2f41, 0xcc12, 0x21, 0 + .dw 0x2f43, 0xcc12, 0x2f4f, 0xcc12, 0x21, 0 + .dw 0x2f51, 0xcc12, 0x2f51, 0xcc12, 0x21, 0 + .dw 0x2f53, 0xcc12, 0x2f7f, 0xcc12, 0x21, 0 + .dw 0x2f81, 0xcc12, 0x2f81, 0xcc12, 0x21, 0 + .dw 0x2f83, 0xcc12, 0x2f8f, 0xcc12, 0x21, 0 + .dw 0x2f91, 0xcc12, 0x2f91, 0xcc12, 0x21, 0 + .dw 0x2f93, 0xcc12, 0x2fbf, 0xcc12, 0x21, 0 + .dw 0x2fc1, 0xcc12, 0x2fc1, 0xcc12, 0x21, 0 + .dw 0x2fc3, 0xcc12, 0x2fcf, 0xcc12, 0x21, 0 + .dw 0x2fd1, 0xcc12, 0x2fd1, 0xcc12, 0x21, 0 + .dw 0x2fd3, 0xcc12, 0xbfff, 0xcc12, 0x21, 0 + .dw 0xd000, 0xcc12, 0xffff, 0xcc13, 0x21, 0 + .dw 0x0001, 0xcc14, 0x0001, 0xcc14, 0x21, 0 + .dw 0x0003, 0xcc14, 0x000f, 0xcc14, 0x21, 0 + .dw 0x0011, 0xcc14, 0x0011, 0xcc14, 0x21, 0 + .dw 0x0013, 0xcc14, 0x003f, 0xcc14, 0x21, 0 + .dw 0x0041, 0xcc14, 0x0041, 0xcc14, 0x21, 0 + .dw 0x0043, 0xcc14, 0x004f, 0xcc14, 0x21, 0 + .dw 0x0051, 0xcc14, 0x0051, 0xcc14, 0x21, 0 + .dw 0x0053, 0xcc14, 0x007f, 0xcc14, 0x21, 0 + .dw 0x0081, 0xcc14, 0x0081, 0xcc14, 0x21, 0 + .dw 0x0083, 0xcc14, 0x008f, 0xcc14, 0x21, 0 + .dw 0x0091, 0xcc14, 0x0091, 0xcc14, 0x21, 0 + .dw 0x0093, 0xcc14, 0x00bf, 0xcc14, 0x21, 0 + .dw 0x00c1, 0xcc14, 0x00c1, 0xcc14, 0x21, 0 + .dw 0x00c3, 0xcc14, 0x00cf, 0xcc14, 0x21, 0 + .dw 0x00d1, 0xcc14, 0x00d1, 0xcc14, 0x21, 0 + .dw 0x00d3, 0xcc14, 0x00ff, 0xcc14, 0x21, 0 + .dw 0x0101, 0xcc14, 0x0101, 0xcc14, 0x21, 0 + .dw 0x0103, 0xcc14, 0x010f, 0xcc14, 0x21, 0 + .dw 0x0111, 0xcc14, 0x0111, 0xcc14, 0x21, 0 + .dw 0x0113, 0xcc14, 0x013f, 0xcc14, 0x21, 0 + .dw 0x0141, 0xcc14, 0x0141, 0xcc14, 0x21, 0 + .dw 0x0143, 0xcc14, 0x014f, 0xcc14, 0x21, 0 + .dw 0x0151, 0xcc14, 0x0151, 0xcc14, 0x21, 0 + .dw 0x0153, 0xcc14, 0x017f, 0xcc14, 0x21, 0 + .dw 0x0181, 0xcc14, 0x0181, 0xcc14, 0x21, 0 + .dw 0x0183, 0xcc14, 0x018f, 0xcc14, 0x21, 0 + .dw 0x0191, 0xcc14, 0x0191, 0xcc14, 0x21, 0 + .dw 0x0193, 0xcc14, 0x01bf, 0xcc14, 0x21, 0 + .dw 0x01c1, 0xcc14, 0x01c1, 0xcc14, 0x21, 0 + .dw 0x01c3, 0xcc14, 0x01cf, 0xcc14, 0x21, 0 + .dw 0x01d1, 0xcc14, 0x01d1, 0xcc14, 0x21, 0 + .dw 0x01d3, 0xcc14, 0x01ff, 0xcc14, 0x21, 0 + .dw 0x0201, 0xcc14, 0x0201, 0xcc14, 0x21, 0 + .dw 0x0203, 0xcc14, 0x020f, 0xcc14, 0x21, 0 + .dw 0x0211, 0xcc14, 0x0211, 0xcc14, 0x21, 0 + .dw 0x0213, 0xcc14, 0x023f, 0xcc14, 0x21, 0 + .dw 0x0241, 0xcc14, 0x0241, 0xcc14, 0x21, 0 + .dw 0x0243, 0xcc14, 0x024f, 0xcc14, 0x21, 0 + .dw 0x0251, 0xcc14, 0x0251, 0xcc14, 0x21, 0 + .dw 0x0253, 0xcc14, 0x027f, 0xcc14, 0x21, 0 + .dw 0x0281, 0xcc14, 0x0281, 0xcc14, 0x21, 0 + .dw 0x0283, 0xcc14, 0x028f, 0xcc14, 0x21, 0 + .dw 0x0291, 0xcc14, 0x0291, 0xcc14, 0x21, 0 + .dw 0x0293, 0xcc14, 0x02bf, 0xcc14, 0x21, 0 + .dw 0x02c1, 0xcc14, 0x02c1, 0xcc14, 0x21, 0 + .dw 0x02c3, 0xcc14, 0x02cf, 0xcc14, 0x21, 0 + .dw 0x02d1, 0xcc14, 0x02d1, 0xcc14, 0x21, 0 + .dw 0x02d3, 0xcc14, 0x02ff, 0xcc14, 0x21, 0 + .dw 0x0301, 0xcc14, 0x0301, 0xcc14, 0x21, 0 + .dw 0x0303, 0xcc14, 0x030f, 0xcc14, 0x21, 0 + .dw 0x0311, 0xcc14, 0x0311, 0xcc14, 0x21, 0 + .dw 0x0313, 0xcc14, 0x033f, 0xcc14, 0x21, 0 + .dw 0x0341, 0xcc14, 0x0341, 0xcc14, 0x21, 0 + .dw 0x0343, 0xcc14, 0x034f, 0xcc14, 0x21, 0 + .dw 0x0351, 0xcc14, 0x0351, 0xcc14, 0x21, 0 + .dw 0x0353, 0xcc14, 0x037f, 0xcc14, 0x21, 0 + .dw 0x0381, 0xcc14, 0x0381, 0xcc14, 0x21, 0 + .dw 0x0383, 0xcc14, 0x038f, 0xcc14, 0x21, 0 + .dw 0x0391, 0xcc14, 0x0391, 0xcc14, 0x21, 0 + .dw 0x0393, 0xcc14, 0x03bf, 0xcc14, 0x21, 0 + .dw 0x03c1, 0xcc14, 0x03c1, 0xcc14, 0x21, 0 + .dw 0x03c3, 0xcc14, 0x03cf, 0xcc14, 0x21, 0 + .dw 0x03d1, 0xcc14, 0x03d1, 0xcc14, 0x21, 0 + .dw 0x03d3, 0xcc14, 0x03ff, 0xcc14, 0x21, 0 + .dw 0x0401, 0xcc14, 0x0401, 0xcc14, 0x21, 0 + .dw 0x0403, 0xcc14, 0x040f, 0xcc14, 0x21, 0 + .dw 0x0411, 0xcc14, 0x0411, 0xcc14, 0x21, 0 + .dw 0x0413, 0xcc14, 0x043f, 0xcc14, 0x21, 0 + .dw 0x0441, 0xcc14, 0x0441, 0xcc14, 0x21, 0 + .dw 0x0443, 0xcc14, 0x044f, 0xcc14, 0x21, 0 + .dw 0x0451, 0xcc14, 0x0451, 0xcc14, 0x21, 0 + .dw 0x0453, 0xcc14, 0x047f, 0xcc14, 0x21, 0 + .dw 0x0481, 0xcc14, 0x0481, 0xcc14, 0x21, 0 + .dw 0x0483, 0xcc14, 0x048f, 0xcc14, 0x21, 0 + .dw 0x0491, 0xcc14, 0x0491, 0xcc14, 0x21, 0 + .dw 0x0493, 0xcc14, 0x04bf, 0xcc14, 0x21, 0 + .dw 0x04c1, 0xcc14, 0x04c1, 0xcc14, 0x21, 0 + .dw 0x04c3, 0xcc14, 0x04cf, 0xcc14, 0x21, 0 + .dw 0x04d1, 0xcc14, 0x04d1, 0xcc14, 0x21, 0 + .dw 0x04d3, 0xcc14, 0x04ff, 0xcc14, 0x21, 0 + .dw 0x0501, 0xcc14, 0x0501, 0xcc14, 0x21, 0 + .dw 0x0503, 0xcc14, 0x050f, 0xcc14, 0x21, 0 + .dw 0x0511, 0xcc14, 0x0511, 0xcc14, 0x21, 0 + .dw 0x0513, 0xcc14, 0x053f, 0xcc14, 0x21, 0 + .dw 0x0541, 0xcc14, 0x0541, 0xcc14, 0x21, 0 + .dw 0x0543, 0xcc14, 0x054f, 0xcc14, 0x21, 0 + .dw 0x0551, 0xcc14, 0x0551, 0xcc14, 0x21, 0 + .dw 0x0553, 0xcc14, 0x057f, 0xcc14, 0x21, 0 + .dw 0x0581, 0xcc14, 0x0581, 0xcc14, 0x21, 0 + .dw 0x0583, 0xcc14, 0x058f, 0xcc14, 0x21, 0 + .dw 0x0591, 0xcc14, 0x0591, 0xcc14, 0x21, 0 + .dw 0x0593, 0xcc14, 0x05bf, 0xcc14, 0x21, 0 + .dw 0x05c1, 0xcc14, 0x05c1, 0xcc14, 0x21, 0 + .dw 0x05c3, 0xcc14, 0x05cf, 0xcc14, 0x21, 0 + .dw 0x05d1, 0xcc14, 0x05d1, 0xcc14, 0x21, 0 + .dw 0x05d3, 0xcc14, 0x05ff, 0xcc14, 0x21, 0 + .dw 0x0601, 0xcc14, 0x0601, 0xcc14, 0x21, 0 + .dw 0x0603, 0xcc14, 0x060f, 0xcc14, 0x21, 0 + .dw 0x0611, 0xcc14, 0x0611, 0xcc14, 0x21, 0 + .dw 0x0613, 0xcc14, 0x063f, 0xcc14, 0x21, 0 + .dw 0x0641, 0xcc14, 0x0641, 0xcc14, 0x21, 0 + .dw 0x0643, 0xcc14, 0x064f, 0xcc14, 0x21, 0 + .dw 0x0651, 0xcc14, 0x0651, 0xcc14, 0x21, 0 + .dw 0x0653, 0xcc14, 0x067f, 0xcc14, 0x21, 0 + .dw 0x0681, 0xcc14, 0x0681, 0xcc14, 0x21, 0 + .dw 0x0683, 0xcc14, 0x068f, 0xcc14, 0x21, 0 + .dw 0x0691, 0xcc14, 0x0691, 0xcc14, 0x21, 0 + .dw 0x0693, 0xcc14, 0x06bf, 0xcc14, 0x21, 0 + .dw 0x06c1, 0xcc14, 0x06c1, 0xcc14, 0x21, 0 + .dw 0x06c3, 0xcc14, 0x06cf, 0xcc14, 0x21, 0 + .dw 0x06d1, 0xcc14, 0x06d1, 0xcc14, 0x21, 0 + .dw 0x06d3, 0xcc14, 0x06ff, 0xcc14, 0x21, 0 + .dw 0x0701, 0xcc14, 0x0701, 0xcc14, 0x21, 0 + .dw 0x0703, 0xcc14, 0x070f, 0xcc14, 0x21, 0 + .dw 0x0711, 0xcc14, 0x0711, 0xcc14, 0x21, 0 + .dw 0x0713, 0xcc14, 0x073f, 0xcc14, 0x21, 0 + .dw 0x0741, 0xcc14, 0x0741, 0xcc14, 0x21, 0 + .dw 0x0743, 0xcc14, 0x074f, 0xcc14, 0x21, 0 + .dw 0x0751, 0xcc14, 0x0751, 0xcc14, 0x21, 0 + .dw 0x0753, 0xcc14, 0x077f, 0xcc14, 0x21, 0 + .dw 0x0781, 0xcc14, 0x0781, 0xcc14, 0x21, 0 + .dw 0x0783, 0xcc14, 0x078f, 0xcc14, 0x21, 0 + .dw 0x0791, 0xcc14, 0x0791, 0xcc14, 0x21, 0 + .dw 0x0793, 0xcc14, 0x07bf, 0xcc14, 0x21, 0 + .dw 0x07c1, 0xcc14, 0x07c1, 0xcc14, 0x21, 0 + .dw 0x07c3, 0xcc14, 0x07cf, 0xcc14, 0x21, 0 + .dw 0x07d1, 0xcc14, 0x07d1, 0xcc14, 0x21, 0 + .dw 0x07d3, 0xcc14, 0x07ff, 0xcc14, 0x21, 0 + .dw 0x0801, 0xcc14, 0x0801, 0xcc14, 0x21, 0 + .dw 0x0803, 0xcc14, 0x080f, 0xcc14, 0x21, 0 + .dw 0x0811, 0xcc14, 0x0811, 0xcc14, 0x21, 0 + .dw 0x0813, 0xcc14, 0x083f, 0xcc14, 0x21, 0 + .dw 0x0841, 0xcc14, 0x0841, 0xcc14, 0x21, 0 + .dw 0x0843, 0xcc14, 0x084f, 0xcc14, 0x21, 0 + .dw 0x0851, 0xcc14, 0x0851, 0xcc14, 0x21, 0 + .dw 0x0853, 0xcc14, 0x087f, 0xcc14, 0x21, 0 + .dw 0x0881, 0xcc14, 0x0881, 0xcc14, 0x21, 0 + .dw 0x0883, 0xcc14, 0x088f, 0xcc14, 0x21, 0 + .dw 0x0891, 0xcc14, 0x0891, 0xcc14, 0x21, 0 + .dw 0x0893, 0xcc14, 0x08bf, 0xcc14, 0x21, 0 + .dw 0x08c1, 0xcc14, 0x08c1, 0xcc14, 0x21, 0 + .dw 0x08c3, 0xcc14, 0x08cf, 0xcc14, 0x21, 0 + .dw 0x08d1, 0xcc14, 0x08d1, 0xcc14, 0x21, 0 + .dw 0x08d3, 0xcc14, 0x08ff, 0xcc14, 0x21, 0 + .dw 0x0901, 0xcc14, 0x0901, 0xcc14, 0x21, 0 + .dw 0x0903, 0xcc14, 0x090f, 0xcc14, 0x21, 0 + .dw 0x0911, 0xcc14, 0x0911, 0xcc14, 0x21, 0 + .dw 0x0913, 0xcc14, 0x093f, 0xcc14, 0x21, 0 + .dw 0x0941, 0xcc14, 0x0941, 0xcc14, 0x21, 0 + .dw 0x0943, 0xcc14, 0x094f, 0xcc14, 0x21, 0 + .dw 0x0951, 0xcc14, 0x0951, 0xcc14, 0x21, 0 + .dw 0x0953, 0xcc14, 0x097f, 0xcc14, 0x21, 0 + .dw 0x0981, 0xcc14, 0x0981, 0xcc14, 0x21, 0 + .dw 0x0983, 0xcc14, 0x098f, 0xcc14, 0x21, 0 + .dw 0x0991, 0xcc14, 0x0991, 0xcc14, 0x21, 0 + .dw 0x0993, 0xcc14, 0x09bf, 0xcc14, 0x21, 0 + .dw 0x09c1, 0xcc14, 0x09c1, 0xcc14, 0x21, 0 + .dw 0x09c3, 0xcc14, 0x09cf, 0xcc14, 0x21, 0 + .dw 0x09d1, 0xcc14, 0x09d1, 0xcc14, 0x21, 0 + .dw 0x09d3, 0xcc14, 0x09ff, 0xcc14, 0x21, 0 + .dw 0x0a01, 0xcc14, 0x0a01, 0xcc14, 0x21, 0 + .dw 0x0a03, 0xcc14, 0x0a0f, 0xcc14, 0x21, 0 + .dw 0x0a11, 0xcc14, 0x0a11, 0xcc14, 0x21, 0 + .dw 0x0a13, 0xcc14, 0x0a3f, 0xcc14, 0x21, 0 + .dw 0x0a41, 0xcc14, 0x0a41, 0xcc14, 0x21, 0 + .dw 0x0a43, 0xcc14, 0x0a4f, 0xcc14, 0x21, 0 + .dw 0x0a51, 0xcc14, 0x0a51, 0xcc14, 0x21, 0 + .dw 0x0a53, 0xcc14, 0x0a7f, 0xcc14, 0x21, 0 + .dw 0x0a81, 0xcc14, 0x0a81, 0xcc14, 0x21, 0 + .dw 0x0a83, 0xcc14, 0x0a8f, 0xcc14, 0x21, 0 + .dw 0x0a91, 0xcc14, 0x0a91, 0xcc14, 0x21, 0 + .dw 0x0a93, 0xcc14, 0x0abf, 0xcc14, 0x21, 0 + .dw 0x0ac1, 0xcc14, 0x0ac1, 0xcc14, 0x21, 0 + .dw 0x0ac3, 0xcc14, 0x0acf, 0xcc14, 0x21, 0 + .dw 0x0ad1, 0xcc14, 0x0ad1, 0xcc14, 0x21, 0 + .dw 0x0ad3, 0xcc14, 0x0aff, 0xcc14, 0x21, 0 + .dw 0x0b01, 0xcc14, 0x0b01, 0xcc14, 0x21, 0 + .dw 0x0b03, 0xcc14, 0x0b0f, 0xcc14, 0x21, 0 + .dw 0x0b11, 0xcc14, 0x0b11, 0xcc14, 0x21, 0 + .dw 0x0b13, 0xcc14, 0x0b3f, 0xcc14, 0x21, 0 + .dw 0x0b41, 0xcc14, 0x0b41, 0xcc14, 0x21, 0 + .dw 0x0b43, 0xcc14, 0x0b4f, 0xcc14, 0x21, 0 + .dw 0x0b51, 0xcc14, 0x0b51, 0xcc14, 0x21, 0 + .dw 0x0b53, 0xcc14, 0x0b7f, 0xcc14, 0x21, 0 + .dw 0x0b81, 0xcc14, 0x0b81, 0xcc14, 0x21, 0 + .dw 0x0b83, 0xcc14, 0x0b8f, 0xcc14, 0x21, 0 + .dw 0x0b91, 0xcc14, 0x0b91, 0xcc14, 0x21, 0 + .dw 0x0b93, 0xcc14, 0x0bbf, 0xcc14, 0x21, 0 + .dw 0x0bc1, 0xcc14, 0x0bc1, 0xcc14, 0x21, 0 + .dw 0x0bc3, 0xcc14, 0x0bcf, 0xcc14, 0x21, 0 + .dw 0x0bd1, 0xcc14, 0x0bd1, 0xcc14, 0x21, 0 + .dw 0x0bd3, 0xcc14, 0x0bff, 0xcc14, 0x21, 0 + .dw 0x0c01, 0xcc14, 0x0c01, 0xcc14, 0x21, 0 + .dw 0x0c03, 0xcc14, 0x0c0f, 0xcc14, 0x21, 0 + .dw 0x0c11, 0xcc14, 0x0c11, 0xcc14, 0x21, 0 + .dw 0x0c13, 0xcc14, 0x0c3f, 0xcc14, 0x21, 0 + .dw 0x0c41, 0xcc14, 0x0c41, 0xcc14, 0x21, 0 + .dw 0x0c43, 0xcc14, 0x0c4f, 0xcc14, 0x21, 0 + .dw 0x0c51, 0xcc14, 0x0c51, 0xcc14, 0x21, 0 + .dw 0x0c53, 0xcc14, 0x0c7f, 0xcc14, 0x21, 0 + .dw 0x0c81, 0xcc14, 0x0c81, 0xcc14, 0x21, 0 + .dw 0x0c83, 0xcc14, 0x0c8f, 0xcc14, 0x21, 0 + .dw 0x0c91, 0xcc14, 0x0c91, 0xcc14, 0x21, 0 + .dw 0x0c93, 0xcc14, 0x0cbf, 0xcc14, 0x21, 0 + .dw 0x0cc1, 0xcc14, 0x0cc1, 0xcc14, 0x21, 0 + .dw 0x0cc3, 0xcc14, 0x0ccf, 0xcc14, 0x21, 0 + .dw 0x0cd1, 0xcc14, 0x0cd1, 0xcc14, 0x21, 0 + .dw 0x0cd3, 0xcc14, 0x0cff, 0xcc14, 0x21, 0 + .dw 0x0d01, 0xcc14, 0x0d01, 0xcc14, 0x21, 0 + .dw 0x0d03, 0xcc14, 0x0d0f, 0xcc14, 0x21, 0 + .dw 0x0d11, 0xcc14, 0x0d11, 0xcc14, 0x21, 0 + .dw 0x0d13, 0xcc14, 0x0d3f, 0xcc14, 0x21, 0 + .dw 0x0d41, 0xcc14, 0x0d41, 0xcc14, 0x21, 0 + .dw 0x0d43, 0xcc14, 0x0d4f, 0xcc14, 0x21, 0 + .dw 0x0d51, 0xcc14, 0x0d51, 0xcc14, 0x21, 0 + .dw 0x0d53, 0xcc14, 0x0d7f, 0xcc14, 0x21, 0 + .dw 0x0d81, 0xcc14, 0x0d81, 0xcc14, 0x21, 0 + .dw 0x0d83, 0xcc14, 0x0d8f, 0xcc14, 0x21, 0 + .dw 0x0d91, 0xcc14, 0x0d91, 0xcc14, 0x21, 0 + .dw 0x0d93, 0xcc14, 0x0dbf, 0xcc14, 0x21, 0 + .dw 0x0dc1, 0xcc14, 0x0dc1, 0xcc14, 0x21, 0 + .dw 0x0dc3, 0xcc14, 0x0dcf, 0xcc14, 0x21, 0 + .dw 0x0dd1, 0xcc14, 0x0dd1, 0xcc14, 0x21, 0 + .dw 0x0dd3, 0xcc14, 0x0dff, 0xcc14, 0x21, 0 + .dw 0x0e01, 0xcc14, 0x0e01, 0xcc14, 0x21, 0 + .dw 0x0e03, 0xcc14, 0x0e0f, 0xcc14, 0x21, 0 + .dw 0x0e11, 0xcc14, 0x0e11, 0xcc14, 0x21, 0 + .dw 0x0e13, 0xcc14, 0x0e3f, 0xcc14, 0x21, 0 + .dw 0x0e41, 0xcc14, 0x0e41, 0xcc14, 0x21, 0 + .dw 0x0e43, 0xcc14, 0x0e4f, 0xcc14, 0x21, 0 + .dw 0x0e51, 0xcc14, 0x0e51, 0xcc14, 0x21, 0 + .dw 0x0e53, 0xcc14, 0x0e7f, 0xcc14, 0x21, 0 + .dw 0x0e81, 0xcc14, 0x0e81, 0xcc14, 0x21, 0 + .dw 0x0e83, 0xcc14, 0x0e8f, 0xcc14, 0x21, 0 + .dw 0x0e91, 0xcc14, 0x0e91, 0xcc14, 0x21, 0 + .dw 0x0e93, 0xcc14, 0x0ebf, 0xcc14, 0x21, 0 + .dw 0x0ec1, 0xcc14, 0x0ec1, 0xcc14, 0x21, 0 + .dw 0x0ec3, 0xcc14, 0x0ecf, 0xcc14, 0x21, 0 + .dw 0x0ed1, 0xcc14, 0x0ed1, 0xcc14, 0x21, 0 + .dw 0x0ed3, 0xcc14, 0x0eff, 0xcc14, 0x21, 0 + .dw 0x0f01, 0xcc14, 0x0f01, 0xcc14, 0x21, 0 + .dw 0x0f03, 0xcc14, 0x0f0f, 0xcc14, 0x21, 0 + .dw 0x0f11, 0xcc14, 0x0f11, 0xcc14, 0x21, 0 + .dw 0x0f13, 0xcc14, 0x0f3f, 0xcc14, 0x21, 0 + .dw 0x0f41, 0xcc14, 0x0f41, 0xcc14, 0x21, 0 + .dw 0x0f43, 0xcc14, 0x0f4f, 0xcc14, 0x21, 0 + .dw 0x0f51, 0xcc14, 0x0f51, 0xcc14, 0x21, 0 + .dw 0x0f53, 0xcc14, 0x0f7f, 0xcc14, 0x21, 0 + .dw 0x0f81, 0xcc14, 0x0f81, 0xcc14, 0x21, 0 + .dw 0x0f83, 0xcc14, 0x0f8f, 0xcc14, 0x21, 0 + .dw 0x0f91, 0xcc14, 0x0f91, 0xcc14, 0x21, 0 + .dw 0x0f93, 0xcc14, 0x0fbf, 0xcc14, 0x21, 0 + .dw 0x0fc1, 0xcc14, 0x0fc1, 0xcc14, 0x21, 0 + .dw 0x0fc3, 0xcc14, 0x0fcf, 0xcc14, 0x21, 0 + .dw 0x0fd1, 0xcc14, 0x0fd1, 0xcc14, 0x21, 0 + .dw 0x0fd3, 0xcc14, 0x1fff, 0xcc14, 0x21, 0 + .dw 0x2001, 0xcc14, 0x2001, 0xcc14, 0x21, 0 + .dw 0x2003, 0xcc14, 0x200f, 0xcc14, 0x21, 0 + .dw 0x2011, 0xcc14, 0x2011, 0xcc14, 0x21, 0 + .dw 0x2013, 0xcc14, 0x203f, 0xcc14, 0x21, 0 + .dw 0x2041, 0xcc14, 0x2041, 0xcc14, 0x21, 0 + .dw 0x2043, 0xcc14, 0x204f, 0xcc14, 0x21, 0 + .dw 0x2051, 0xcc14, 0x2051, 0xcc14, 0x21, 0 + .dw 0x2053, 0xcc14, 0x207f, 0xcc14, 0x21, 0 + .dw 0x2081, 0xcc14, 0x2081, 0xcc14, 0x21, 0 + .dw 0x2083, 0xcc14, 0x208f, 0xcc14, 0x21, 0 + .dw 0x2091, 0xcc14, 0x2091, 0xcc14, 0x21, 0 + .dw 0x2093, 0xcc14, 0x20bf, 0xcc14, 0x21, 0 + .dw 0x20c1, 0xcc14, 0x20c1, 0xcc14, 0x21, 0 + .dw 0x20c3, 0xcc14, 0x20cf, 0xcc14, 0x21, 0 + .dw 0x20d1, 0xcc14, 0x20d1, 0xcc14, 0x21, 0 + .dw 0x20d3, 0xcc14, 0x20ff, 0xcc14, 0x21, 0 + .dw 0x2101, 0xcc14, 0x2101, 0xcc14, 0x21, 0 + .dw 0x2103, 0xcc14, 0x210f, 0xcc14, 0x21, 0 + .dw 0x2111, 0xcc14, 0x2111, 0xcc14, 0x21, 0 + .dw 0x2113, 0xcc14, 0x213f, 0xcc14, 0x21, 0 + .dw 0x2141, 0xcc14, 0x2141, 0xcc14, 0x21, 0 + .dw 0x2143, 0xcc14, 0x214f, 0xcc14, 0x21, 0 + .dw 0x2151, 0xcc14, 0x2151, 0xcc14, 0x21, 0 + .dw 0x2153, 0xcc14, 0x217f, 0xcc14, 0x21, 0 + .dw 0x2181, 0xcc14, 0x2181, 0xcc14, 0x21, 0 + .dw 0x2183, 0xcc14, 0x218f, 0xcc14, 0x21, 0 + .dw 0x2191, 0xcc14, 0x2191, 0xcc14, 0x21, 0 + .dw 0x2193, 0xcc14, 0x21bf, 0xcc14, 0x21, 0 + .dw 0x21c1, 0xcc14, 0x21c1, 0xcc14, 0x21, 0 + .dw 0x21c3, 0xcc14, 0x21cf, 0xcc14, 0x21, 0 + .dw 0x21d1, 0xcc14, 0x21d1, 0xcc14, 0x21, 0 + .dw 0x21d3, 0xcc14, 0x21ff, 0xcc14, 0x21, 0 + .dw 0x2201, 0xcc14, 0x2201, 0xcc14, 0x21, 0 + .dw 0x2203, 0xcc14, 0x220f, 0xcc14, 0x21, 0 + .dw 0x2211, 0xcc14, 0x2211, 0xcc14, 0x21, 0 + .dw 0x2213, 0xcc14, 0x223f, 0xcc14, 0x21, 0 + .dw 0x2241, 0xcc14, 0x2241, 0xcc14, 0x21, 0 + .dw 0x2243, 0xcc14, 0x224f, 0xcc14, 0x21, 0 + .dw 0x2251, 0xcc14, 0x2251, 0xcc14, 0x21, 0 + .dw 0x2253, 0xcc14, 0x227f, 0xcc14, 0x21, 0 + .dw 0x2281, 0xcc14, 0x2281, 0xcc14, 0x21, 0 + .dw 0x2283, 0xcc14, 0x228f, 0xcc14, 0x21, 0 + .dw 0x2291, 0xcc14, 0x2291, 0xcc14, 0x21, 0 + .dw 0x2293, 0xcc14, 0x22bf, 0xcc14, 0x21, 0 + .dw 0x22c1, 0xcc14, 0x22c1, 0xcc14, 0x21, 0 + .dw 0x22c3, 0xcc14, 0x22cf, 0xcc14, 0x21, 0 + .dw 0x22d1, 0xcc14, 0x22d1, 0xcc14, 0x21, 0 + .dw 0x22d3, 0xcc14, 0x22ff, 0xcc14, 0x21, 0 + .dw 0x2301, 0xcc14, 0x2301, 0xcc14, 0x21, 0 + .dw 0x2303, 0xcc14, 0x230f, 0xcc14, 0x21, 0 + .dw 0x2311, 0xcc14, 0x2311, 0xcc14, 0x21, 0 + .dw 0x2313, 0xcc14, 0x233f, 0xcc14, 0x21, 0 + .dw 0x2341, 0xcc14, 0x2341, 0xcc14, 0x21, 0 + .dw 0x2343, 0xcc14, 0x234f, 0xcc14, 0x21, 0 + .dw 0x2351, 0xcc14, 0x2351, 0xcc14, 0x21, 0 + .dw 0x2353, 0xcc14, 0x237f, 0xcc14, 0x21, 0 + .dw 0x2381, 0xcc14, 0x2381, 0xcc14, 0x21, 0 + .dw 0x2383, 0xcc14, 0x238f, 0xcc14, 0x21, 0 + .dw 0x2391, 0xcc14, 0x2391, 0xcc14, 0x21, 0 + .dw 0x2393, 0xcc14, 0x23bf, 0xcc14, 0x21, 0 + .dw 0x23c1, 0xcc14, 0x23c1, 0xcc14, 0x21, 0 + .dw 0x23c3, 0xcc14, 0x23cf, 0xcc14, 0x21, 0 + .dw 0x23d1, 0xcc14, 0x23d1, 0xcc14, 0x21, 0 + .dw 0x23d3, 0xcc14, 0x23ff, 0xcc14, 0x21, 0 + .dw 0x2401, 0xcc14, 0x2401, 0xcc14, 0x21, 0 + .dw 0x2403, 0xcc14, 0x240f, 0xcc14, 0x21, 0 + .dw 0x2411, 0xcc14, 0x2411, 0xcc14, 0x21, 0 + .dw 0x2413, 0xcc14, 0x243f, 0xcc14, 0x21, 0 + .dw 0x2441, 0xcc14, 0x2441, 0xcc14, 0x21, 0 + .dw 0x2443, 0xcc14, 0x244f, 0xcc14, 0x21, 0 + .dw 0x2451, 0xcc14, 0x2451, 0xcc14, 0x21, 0 + .dw 0x2453, 0xcc14, 0x247f, 0xcc14, 0x21, 0 + .dw 0x2481, 0xcc14, 0x2481, 0xcc14, 0x21, 0 + .dw 0x2483, 0xcc14, 0x248f, 0xcc14, 0x21, 0 + .dw 0x2491, 0xcc14, 0x2491, 0xcc14, 0x21, 0 + .dw 0x2493, 0xcc14, 0x24bf, 0xcc14, 0x21, 0 + .dw 0x24c1, 0xcc14, 0x24c1, 0xcc14, 0x21, 0 + .dw 0x24c3, 0xcc14, 0x24cf, 0xcc14, 0x21, 0 + .dw 0x24d1, 0xcc14, 0x24d1, 0xcc14, 0x21, 0 + .dw 0x24d3, 0xcc14, 0x24ff, 0xcc14, 0x21, 0 + .dw 0x2501, 0xcc14, 0x2501, 0xcc14, 0x21, 0 + .dw 0x2503, 0xcc14, 0x250f, 0xcc14, 0x21, 0 + .dw 0x2511, 0xcc14, 0x2511, 0xcc14, 0x21, 0 + .dw 0x2513, 0xcc14, 0x253f, 0xcc14, 0x21, 0 + .dw 0x2541, 0xcc14, 0x2541, 0xcc14, 0x21, 0 + .dw 0x2543, 0xcc14, 0x254f, 0xcc14, 0x21, 0 + .dw 0x2551, 0xcc14, 0x2551, 0xcc14, 0x21, 0 + .dw 0x2553, 0xcc14, 0x257f, 0xcc14, 0x21, 0 + .dw 0x2581, 0xcc14, 0x2581, 0xcc14, 0x21, 0 + .dw 0x2583, 0xcc14, 0x258f, 0xcc14, 0x21, 0 + .dw 0x2591, 0xcc14, 0x2591, 0xcc14, 0x21, 0 + .dw 0x2593, 0xcc14, 0x25bf, 0xcc14, 0x21, 0 + .dw 0x25c1, 0xcc14, 0x25c1, 0xcc14, 0x21, 0 + .dw 0x25c3, 0xcc14, 0x25cf, 0xcc14, 0x21, 0 + .dw 0x25d1, 0xcc14, 0x25d1, 0xcc14, 0x21, 0 + .dw 0x25d3, 0xcc14, 0x25ff, 0xcc14, 0x21, 0 + .dw 0x2601, 0xcc14, 0x2601, 0xcc14, 0x21, 0 + .dw 0x2603, 0xcc14, 0x260f, 0xcc14, 0x21, 0 + .dw 0x2611, 0xcc14, 0x2611, 0xcc14, 0x21, 0 + .dw 0x2613, 0xcc14, 0x263f, 0xcc14, 0x21, 0 + .dw 0x2641, 0xcc14, 0x2641, 0xcc14, 0x21, 0 + .dw 0x2643, 0xcc14, 0x264f, 0xcc14, 0x21, 0 + .dw 0x2651, 0xcc14, 0x2651, 0xcc14, 0x21, 0 + .dw 0x2653, 0xcc14, 0x267f, 0xcc14, 0x21, 0 + .dw 0x2681, 0xcc14, 0x2681, 0xcc14, 0x21, 0 + .dw 0x2683, 0xcc14, 0x268f, 0xcc14, 0x21, 0 + .dw 0x2691, 0xcc14, 0x2691, 0xcc14, 0x21, 0 + .dw 0x2693, 0xcc14, 0x26bf, 0xcc14, 0x21, 0 + .dw 0x26c1, 0xcc14, 0x26c1, 0xcc14, 0x21, 0 + .dw 0x26c3, 0xcc14, 0x26cf, 0xcc14, 0x21, 0 + .dw 0x26d1, 0xcc14, 0x26d1, 0xcc14, 0x21, 0 + .dw 0x26d3, 0xcc14, 0x26ff, 0xcc14, 0x21, 0 + .dw 0x2701, 0xcc14, 0x2701, 0xcc14, 0x21, 0 + .dw 0x2703, 0xcc14, 0x270f, 0xcc14, 0x21, 0 + .dw 0x2711, 0xcc14, 0x2711, 0xcc14, 0x21, 0 + .dw 0x2713, 0xcc14, 0x273f, 0xcc14, 0x21, 0 + .dw 0x2741, 0xcc14, 0x2741, 0xcc14, 0x21, 0 + .dw 0x2743, 0xcc14, 0x274f, 0xcc14, 0x21, 0 + .dw 0x2751, 0xcc14, 0x2751, 0xcc14, 0x21, 0 + .dw 0x2753, 0xcc14, 0x277f, 0xcc14, 0x21, 0 + .dw 0x2781, 0xcc14, 0x2781, 0xcc14, 0x21, 0 + .dw 0x2783, 0xcc14, 0x278f, 0xcc14, 0x21, 0 + .dw 0x2791, 0xcc14, 0x2791, 0xcc14, 0x21, 0 + .dw 0x2793, 0xcc14, 0x27bf, 0xcc14, 0x21, 0 + .dw 0x27c1, 0xcc14, 0x27c1, 0xcc14, 0x21, 0 + .dw 0x27c3, 0xcc14, 0x27cf, 0xcc14, 0x21, 0 + .dw 0x27d1, 0xcc14, 0x27d1, 0xcc14, 0x21, 0 + .dw 0x27d3, 0xcc14, 0x27ff, 0xcc14, 0x21, 0 + .dw 0x2801, 0xcc14, 0x2801, 0xcc14, 0x21, 0 + .dw 0x2803, 0xcc14, 0x280f, 0xcc14, 0x21, 0 + .dw 0x2811, 0xcc14, 0x2811, 0xcc14, 0x21, 0 + .dw 0x2813, 0xcc14, 0x283f, 0xcc14, 0x21, 0 + .dw 0x2841, 0xcc14, 0x2841, 0xcc14, 0x21, 0 + .dw 0x2843, 0xcc14, 0x284f, 0xcc14, 0x21, 0 + .dw 0x2851, 0xcc14, 0x2851, 0xcc14, 0x21, 0 + .dw 0x2853, 0xcc14, 0x287f, 0xcc14, 0x21, 0 + .dw 0x2881, 0xcc14, 0x2881, 0xcc14, 0x21, 0 + .dw 0x2883, 0xcc14, 0x288f, 0xcc14, 0x21, 0 + .dw 0x2891, 0xcc14, 0x2891, 0xcc14, 0x21, 0 + .dw 0x2893, 0xcc14, 0x28bf, 0xcc14, 0x21, 0 + .dw 0x28c1, 0xcc14, 0x28c1, 0xcc14, 0x21, 0 + .dw 0x28c3, 0xcc14, 0x28cf, 0xcc14, 0x21, 0 + .dw 0x28d1, 0xcc14, 0x28d1, 0xcc14, 0x21, 0 + .dw 0x28d3, 0xcc14, 0x28ff, 0xcc14, 0x21, 0 + .dw 0x2901, 0xcc14, 0x2901, 0xcc14, 0x21, 0 + .dw 0x2903, 0xcc14, 0x290f, 0xcc14, 0x21, 0 + .dw 0x2911, 0xcc14, 0x2911, 0xcc14, 0x21, 0 + .dw 0x2913, 0xcc14, 0x293f, 0xcc14, 0x21, 0 + .dw 0x2941, 0xcc14, 0x2941, 0xcc14, 0x21, 0 + .dw 0x2943, 0xcc14, 0x294f, 0xcc14, 0x21, 0 + .dw 0x2951, 0xcc14, 0x2951, 0xcc14, 0x21, 0 + .dw 0x2953, 0xcc14, 0x297f, 0xcc14, 0x21, 0 + .dw 0x2981, 0xcc14, 0x2981, 0xcc14, 0x21, 0 + .dw 0x2983, 0xcc14, 0x298f, 0xcc14, 0x21, 0 + .dw 0x2991, 0xcc14, 0x2991, 0xcc14, 0x21, 0 + .dw 0x2993, 0xcc14, 0x29bf, 0xcc14, 0x21, 0 + .dw 0x29c1, 0xcc14, 0x29c1, 0xcc14, 0x21, 0 + .dw 0x29c3, 0xcc14, 0x29cf, 0xcc14, 0x21, 0 + .dw 0x29d1, 0xcc14, 0x29d1, 0xcc14, 0x21, 0 + .dw 0x29d3, 0xcc14, 0x29ff, 0xcc14, 0x21, 0 + .dw 0x2a01, 0xcc14, 0x2a01, 0xcc14, 0x21, 0 + .dw 0x2a03, 0xcc14, 0x2a0f, 0xcc14, 0x21, 0 + .dw 0x2a11, 0xcc14, 0x2a11, 0xcc14, 0x21, 0 + .dw 0x2a13, 0xcc14, 0x2a3f, 0xcc14, 0x21, 0 + .dw 0x2a41, 0xcc14, 0x2a41, 0xcc14, 0x21, 0 + .dw 0x2a43, 0xcc14, 0x2a4f, 0xcc14, 0x21, 0 + .dw 0x2a51, 0xcc14, 0x2a51, 0xcc14, 0x21, 0 + .dw 0x2a53, 0xcc14, 0x2a7f, 0xcc14, 0x21, 0 + .dw 0x2a81, 0xcc14, 0x2a81, 0xcc14, 0x21, 0 + .dw 0x2a83, 0xcc14, 0x2a8f, 0xcc14, 0x21, 0 + .dw 0x2a91, 0xcc14, 0x2a91, 0xcc14, 0x21, 0 + .dw 0x2a93, 0xcc14, 0x2abf, 0xcc14, 0x21, 0 + .dw 0x2ac1, 0xcc14, 0x2ac1, 0xcc14, 0x21, 0 + .dw 0x2ac3, 0xcc14, 0x2acf, 0xcc14, 0x21, 0 + .dw 0x2ad1, 0xcc14, 0x2ad1, 0xcc14, 0x21, 0 + .dw 0x2ad3, 0xcc14, 0x2aff, 0xcc14, 0x21, 0 + .dw 0x2b01, 0xcc14, 0x2b01, 0xcc14, 0x21, 0 + .dw 0x2b03, 0xcc14, 0x2b0f, 0xcc14, 0x21, 0 + .dw 0x2b11, 0xcc14, 0x2b11, 0xcc14, 0x21, 0 + .dw 0x2b13, 0xcc14, 0x2b3f, 0xcc14, 0x21, 0 + .dw 0x2b41, 0xcc14, 0x2b41, 0xcc14, 0x21, 0 + .dw 0x2b43, 0xcc14, 0x2b4f, 0xcc14, 0x21, 0 + .dw 0x2b51, 0xcc14, 0x2b51, 0xcc14, 0x21, 0 + .dw 0x2b53, 0xcc14, 0x2b7f, 0xcc14, 0x21, 0 + .dw 0x2b81, 0xcc14, 0x2b81, 0xcc14, 0x21, 0 + .dw 0x2b83, 0xcc14, 0x2b8f, 0xcc14, 0x21, 0 + .dw 0x2b91, 0xcc14, 0x2b91, 0xcc14, 0x21, 0 + .dw 0x2b93, 0xcc14, 0x2bbf, 0xcc14, 0x21, 0 + .dw 0x2bc1, 0xcc14, 0x2bc1, 0xcc14, 0x21, 0 + .dw 0x2bc3, 0xcc14, 0x2bcf, 0xcc14, 0x21, 0 + .dw 0x2bd1, 0xcc14, 0x2bd1, 0xcc14, 0x21, 0 + .dw 0x2bd3, 0xcc14, 0x2bff, 0xcc14, 0x21, 0 + .dw 0x2c01, 0xcc14, 0x2c01, 0xcc14, 0x21, 0 + .dw 0x2c03, 0xcc14, 0x2c0f, 0xcc14, 0x21, 0 + .dw 0x2c11, 0xcc14, 0x2c11, 0xcc14, 0x21, 0 + .dw 0x2c13, 0xcc14, 0x2c3f, 0xcc14, 0x21, 0 + .dw 0x2c41, 0xcc14, 0x2c41, 0xcc14, 0x21, 0 + .dw 0x2c43, 0xcc14, 0x2c4f, 0xcc14, 0x21, 0 + .dw 0x2c51, 0xcc14, 0x2c51, 0xcc14, 0x21, 0 + .dw 0x2c53, 0xcc14, 0x2c7f, 0xcc14, 0x21, 0 + .dw 0x2c81, 0xcc14, 0x2c81, 0xcc14, 0x21, 0 + .dw 0x2c83, 0xcc14, 0x2c8f, 0xcc14, 0x21, 0 + .dw 0x2c91, 0xcc14, 0x2c91, 0xcc14, 0x21, 0 + .dw 0x2c93, 0xcc14, 0x2cbf, 0xcc14, 0x21, 0 + .dw 0x2cc1, 0xcc14, 0x2cc1, 0xcc14, 0x21, 0 + .dw 0x2cc3, 0xcc14, 0x2ccf, 0xcc14, 0x21, 0 + .dw 0x2cd1, 0xcc14, 0x2cd1, 0xcc14, 0x21, 0 + .dw 0x2cd3, 0xcc14, 0x2cff, 0xcc14, 0x21, 0 + .dw 0x2d01, 0xcc14, 0x2d01, 0xcc14, 0x21, 0 + .dw 0x2d03, 0xcc14, 0x2d0f, 0xcc14, 0x21, 0 + .dw 0x2d11, 0xcc14, 0x2d11, 0xcc14, 0x21, 0 + .dw 0x2d13, 0xcc14, 0x2d3f, 0xcc14, 0x21, 0 + .dw 0x2d41, 0xcc14, 0x2d41, 0xcc14, 0x21, 0 + .dw 0x2d43, 0xcc14, 0x2d4f, 0xcc14, 0x21, 0 + .dw 0x2d51, 0xcc14, 0x2d51, 0xcc14, 0x21, 0 + .dw 0x2d53, 0xcc14, 0x2d7f, 0xcc14, 0x21, 0 + .dw 0x2d81, 0xcc14, 0x2d81, 0xcc14, 0x21, 0 + .dw 0x2d83, 0xcc14, 0x2d8f, 0xcc14, 0x21, 0 + .dw 0x2d91, 0xcc14, 0x2d91, 0xcc14, 0x21, 0 + .dw 0x2d93, 0xcc14, 0x2dbf, 0xcc14, 0x21, 0 + .dw 0x2dc1, 0xcc14, 0x2dc1, 0xcc14, 0x21, 0 + .dw 0x2dc3, 0xcc14, 0x2dcf, 0xcc14, 0x21, 0 + .dw 0x2dd1, 0xcc14, 0x2dd1, 0xcc14, 0x21, 0 + .dw 0x2dd3, 0xcc14, 0x2dff, 0xcc14, 0x21, 0 + .dw 0x2e01, 0xcc14, 0x2e01, 0xcc14, 0x21, 0 + .dw 0x2e03, 0xcc14, 0x2e0f, 0xcc14, 0x21, 0 + .dw 0x2e11, 0xcc14, 0x2e11, 0xcc14, 0x21, 0 + .dw 0x2e13, 0xcc14, 0x2e3f, 0xcc14, 0x21, 0 + .dw 0x2e41, 0xcc14, 0x2e41, 0xcc14, 0x21, 0 + .dw 0x2e43, 0xcc14, 0x2e4f, 0xcc14, 0x21, 0 + .dw 0x2e51, 0xcc14, 0x2e51, 0xcc14, 0x21, 0 + .dw 0x2e53, 0xcc14, 0x2e7f, 0xcc14, 0x21, 0 + .dw 0x2e81, 0xcc14, 0x2e81, 0xcc14, 0x21, 0 + .dw 0x2e83, 0xcc14, 0x2e8f, 0xcc14, 0x21, 0 + .dw 0x2e91, 0xcc14, 0x2e91, 0xcc14, 0x21, 0 + .dw 0x2e93, 0xcc14, 0x2ebf, 0xcc14, 0x21, 0 + .dw 0x2ec1, 0xcc14, 0x2ec1, 0xcc14, 0x21, 0 + .dw 0x2ec3, 0xcc14, 0x2ecf, 0xcc14, 0x21, 0 + .dw 0x2ed1, 0xcc14, 0x2ed1, 0xcc14, 0x21, 0 + .dw 0x2ed3, 0xcc14, 0x2eff, 0xcc14, 0x21, 0 + .dw 0x2f01, 0xcc14, 0x2f01, 0xcc14, 0x21, 0 + .dw 0x2f03, 0xcc14, 0x2f0f, 0xcc14, 0x21, 0 + .dw 0x2f11, 0xcc14, 0x2f11, 0xcc14, 0x21, 0 + .dw 0x2f13, 0xcc14, 0x2f3f, 0xcc14, 0x21, 0 + .dw 0x2f41, 0xcc14, 0x2f41, 0xcc14, 0x21, 0 + .dw 0x2f43, 0xcc14, 0x2f4f, 0xcc14, 0x21, 0 + .dw 0x2f51, 0xcc14, 0x2f51, 0xcc14, 0x21, 0 + .dw 0x2f53, 0xcc14, 0x2f7f, 0xcc14, 0x21, 0 + .dw 0x2f81, 0xcc14, 0x2f81, 0xcc14, 0x21, 0 + .dw 0x2f83, 0xcc14, 0x2f8f, 0xcc14, 0x21, 0 + .dw 0x2f91, 0xcc14, 0x2f91, 0xcc14, 0x21, 0 + .dw 0x2f93, 0xcc14, 0x2fbf, 0xcc14, 0x21, 0 + .dw 0x2fc1, 0xcc14, 0x2fc1, 0xcc14, 0x21, 0 + .dw 0x2fc3, 0xcc14, 0x2fcf, 0xcc14, 0x21, 0 + .dw 0x2fd1, 0xcc14, 0x2fd1, 0xcc14, 0x21, 0 + .dw 0x2fd3, 0xcc14, 0x3fff, 0xcc14, 0x21, 0 + .dw 0x4001, 0xcc14, 0x4001, 0xcc14, 0x21, 0 + .dw 0x4003, 0xcc14, 0x400f, 0xcc14, 0x21, 0 + .dw 0x4011, 0xcc14, 0x4011, 0xcc14, 0x21, 0 + .dw 0x4013, 0xcc14, 0x403f, 0xcc14, 0x21, 0 + .dw 0x4041, 0xcc14, 0x4041, 0xcc14, 0x21, 0 + .dw 0x4043, 0xcc14, 0x404f, 0xcc14, 0x21, 0 + .dw 0x4051, 0xcc14, 0x4051, 0xcc14, 0x21, 0 + .dw 0x4053, 0xcc14, 0x407f, 0xcc14, 0x21, 0 + .dw 0x4081, 0xcc14, 0x4081, 0xcc14, 0x21, 0 + .dw 0x4083, 0xcc14, 0x408f, 0xcc14, 0x21, 0 + .dw 0x4091, 0xcc14, 0x4091, 0xcc14, 0x21, 0 + .dw 0x4093, 0xcc14, 0x40bf, 0xcc14, 0x21, 0 + .dw 0x40c1, 0xcc14, 0x40c1, 0xcc14, 0x21, 0 + .dw 0x40c3, 0xcc14, 0x40cf, 0xcc14, 0x21, 0 + .dw 0x40d1, 0xcc14, 0x40d1, 0xcc14, 0x21, 0 + .dw 0x40d3, 0xcc14, 0x40ff, 0xcc14, 0x21, 0 + .dw 0x4101, 0xcc14, 0x4101, 0xcc14, 0x21, 0 + .dw 0x4103, 0xcc14, 0x410f, 0xcc14, 0x21, 0 + .dw 0x4111, 0xcc14, 0x4111, 0xcc14, 0x21, 0 + .dw 0x4113, 0xcc14, 0x413f, 0xcc14, 0x21, 0 + .dw 0x4141, 0xcc14, 0x4141, 0xcc14, 0x21, 0 + .dw 0x4143, 0xcc14, 0x414f, 0xcc14, 0x21, 0 + .dw 0x4151, 0xcc14, 0x4151, 0xcc14, 0x21, 0 + .dw 0x4153, 0xcc14, 0x417f, 0xcc14, 0x21, 0 + .dw 0x4181, 0xcc14, 0x4181, 0xcc14, 0x21, 0 + .dw 0x4183, 0xcc14, 0x418f, 0xcc14, 0x21, 0 + .dw 0x4191, 0xcc14, 0x4191, 0xcc14, 0x21, 0 + .dw 0x4193, 0xcc14, 0x41bf, 0xcc14, 0x21, 0 + .dw 0x41c1, 0xcc14, 0x41c1, 0xcc14, 0x21, 0 + .dw 0x41c3, 0xcc14, 0x41cf, 0xcc14, 0x21, 0 + .dw 0x41d1, 0xcc14, 0x41d1, 0xcc14, 0x21, 0 + .dw 0x41d3, 0xcc14, 0x41ff, 0xcc14, 0x21, 0 + .dw 0x4201, 0xcc14, 0x4201, 0xcc14, 0x21, 0 + .dw 0x4203, 0xcc14, 0x420f, 0xcc14, 0x21, 0 + .dw 0x4211, 0xcc14, 0x4211, 0xcc14, 0x21, 0 + .dw 0x4213, 0xcc14, 0x423f, 0xcc14, 0x21, 0 + .dw 0x4241, 0xcc14, 0x4241, 0xcc14, 0x21, 0 + .dw 0x4243, 0xcc14, 0x424f, 0xcc14, 0x21, 0 + .dw 0x4251, 0xcc14, 0x4251, 0xcc14, 0x21, 0 + .dw 0x4253, 0xcc14, 0x427f, 0xcc14, 0x21, 0 + .dw 0x4281, 0xcc14, 0x4281, 0xcc14, 0x21, 0 + .dw 0x4283, 0xcc14, 0x428f, 0xcc14, 0x21, 0 + .dw 0x4291, 0xcc14, 0x4291, 0xcc14, 0x21, 0 + .dw 0x4293, 0xcc14, 0x42bf, 0xcc14, 0x21, 0 + .dw 0x42c1, 0xcc14, 0x42c1, 0xcc14, 0x21, 0 + .dw 0x42c3, 0xcc14, 0x42cf, 0xcc14, 0x21, 0 + .dw 0x42d1, 0xcc14, 0x42d1, 0xcc14, 0x21, 0 + .dw 0x42d3, 0xcc14, 0x42ff, 0xcc14, 0x21, 0 + .dw 0x4301, 0xcc14, 0x4301, 0xcc14, 0x21, 0 + .dw 0x4303, 0xcc14, 0x430f, 0xcc14, 0x21, 0 + .dw 0x4311, 0xcc14, 0x4311, 0xcc14, 0x21, 0 + .dw 0x4313, 0xcc14, 0x433f, 0xcc14, 0x21, 0 + .dw 0x4341, 0xcc14, 0x4341, 0xcc14, 0x21, 0 + .dw 0x4343, 0xcc14, 0x434f, 0xcc14, 0x21, 0 + .dw 0x4351, 0xcc14, 0x4351, 0xcc14, 0x21, 0 + .dw 0x4353, 0xcc14, 0x437f, 0xcc14, 0x21, 0 + .dw 0x4381, 0xcc14, 0x4381, 0xcc14, 0x21, 0 + .dw 0x4383, 0xcc14, 0x438f, 0xcc14, 0x21, 0 + .dw 0x4391, 0xcc14, 0x4391, 0xcc14, 0x21, 0 + .dw 0x4393, 0xcc14, 0x43bf, 0xcc14, 0x21, 0 + .dw 0x43c1, 0xcc14, 0x43c1, 0xcc14, 0x21, 0 + .dw 0x43c3, 0xcc14, 0x43cf, 0xcc14, 0x21, 0 + .dw 0x43d1, 0xcc14, 0x43d1, 0xcc14, 0x21, 0 + .dw 0x43d3, 0xcc14, 0x43ff, 0xcc14, 0x21, 0 + .dw 0x4401, 0xcc14, 0x4401, 0xcc14, 0x21, 0 + .dw 0x4403, 0xcc14, 0x440f, 0xcc14, 0x21, 0 + .dw 0x4411, 0xcc14, 0x4411, 0xcc14, 0x21, 0 + .dw 0x4413, 0xcc14, 0x443f, 0xcc14, 0x21, 0 + .dw 0x4441, 0xcc14, 0x4441, 0xcc14, 0x21, 0 + .dw 0x4443, 0xcc14, 0x444f, 0xcc14, 0x21, 0 + .dw 0x4451, 0xcc14, 0x4451, 0xcc14, 0x21, 0 + .dw 0x4453, 0xcc14, 0x447f, 0xcc14, 0x21, 0 + .dw 0x4481, 0xcc14, 0x4481, 0xcc14, 0x21, 0 + .dw 0x4483, 0xcc14, 0x448f, 0xcc14, 0x21, 0 + .dw 0x4491, 0xcc14, 0x4491, 0xcc14, 0x21, 0 + .dw 0x4493, 0xcc14, 0x44bf, 0xcc14, 0x21, 0 + .dw 0x44c1, 0xcc14, 0x44c1, 0xcc14, 0x21, 0 + .dw 0x44c3, 0xcc14, 0x44cf, 0xcc14, 0x21, 0 + .dw 0x44d1, 0xcc14, 0x44d1, 0xcc14, 0x21, 0 + .dw 0x44d3, 0xcc14, 0x44ff, 0xcc14, 0x21, 0 + .dw 0x4501, 0xcc14, 0x4501, 0xcc14, 0x21, 0 + .dw 0x4503, 0xcc14, 0x450f, 0xcc14, 0x21, 0 + .dw 0x4511, 0xcc14, 0x4511, 0xcc14, 0x21, 0 + .dw 0x4513, 0xcc14, 0x453f, 0xcc14, 0x21, 0 + .dw 0x4541, 0xcc14, 0x4541, 0xcc14, 0x21, 0 + .dw 0x4543, 0xcc14, 0x454f, 0xcc14, 0x21, 0 + .dw 0x4551, 0xcc14, 0x4551, 0xcc14, 0x21, 0 + .dw 0x4553, 0xcc14, 0x457f, 0xcc14, 0x21, 0 + .dw 0x4581, 0xcc14, 0x4581, 0xcc14, 0x21, 0 + .dw 0x4583, 0xcc14, 0x458f, 0xcc14, 0x21, 0 + .dw 0x4591, 0xcc14, 0x4591, 0xcc14, 0x21, 0 + .dw 0x4593, 0xcc14, 0x45bf, 0xcc14, 0x21, 0 + .dw 0x45c1, 0xcc14, 0x45c1, 0xcc14, 0x21, 0 + .dw 0x45c3, 0xcc14, 0x45cf, 0xcc14, 0x21, 0 + .dw 0x45d1, 0xcc14, 0x45d1, 0xcc14, 0x21, 0 + .dw 0x45d3, 0xcc14, 0x45ff, 0xcc14, 0x21, 0 + .dw 0x4601, 0xcc14, 0x4601, 0xcc14, 0x21, 0 + .dw 0x4603, 0xcc14, 0x460f, 0xcc14, 0x21, 0 + .dw 0x4611, 0xcc14, 0x4611, 0xcc14, 0x21, 0 + .dw 0x4613, 0xcc14, 0x463f, 0xcc14, 0x21, 0 + .dw 0x4641, 0xcc14, 0x4641, 0xcc14, 0x21, 0 + .dw 0x4643, 0xcc14, 0x464f, 0xcc14, 0x21, 0 + .dw 0x4651, 0xcc14, 0x4651, 0xcc14, 0x21, 0 + .dw 0x4653, 0xcc14, 0x467f, 0xcc14, 0x21, 0 + .dw 0x4681, 0xcc14, 0x4681, 0xcc14, 0x21, 0 + .dw 0x4683, 0xcc14, 0x468f, 0xcc14, 0x21, 0 + .dw 0x4691, 0xcc14, 0x4691, 0xcc14, 0x21, 0 + .dw 0x4693, 0xcc14, 0x46bf, 0xcc14, 0x21, 0 + .dw 0x46c1, 0xcc14, 0x46c1, 0xcc14, 0x21, 0 + .dw 0x46c3, 0xcc14, 0x46cf, 0xcc14, 0x21, 0 + .dw 0x46d1, 0xcc14, 0x46d1, 0xcc14, 0x21, 0 + .dw 0x46d3, 0xcc14, 0x46ff, 0xcc14, 0x21, 0 + .dw 0x4701, 0xcc14, 0x4701, 0xcc14, 0x21, 0 + .dw 0x4703, 0xcc14, 0x470f, 0xcc14, 0x21, 0 + .dw 0x4711, 0xcc14, 0x4711, 0xcc14, 0x21, 0 + .dw 0x4713, 0xcc14, 0x473f, 0xcc14, 0x21, 0 + .dw 0x4741, 0xcc14, 0x4741, 0xcc14, 0x21, 0 + .dw 0x4743, 0xcc14, 0x474f, 0xcc14, 0x21, 0 + .dw 0x4751, 0xcc14, 0x4751, 0xcc14, 0x21, 0 + .dw 0x4753, 0xcc14, 0x477f, 0xcc14, 0x21, 0 + .dw 0x4781, 0xcc14, 0x4781, 0xcc14, 0x21, 0 + .dw 0x4783, 0xcc14, 0x478f, 0xcc14, 0x21, 0 + .dw 0x4791, 0xcc14, 0x4791, 0xcc14, 0x21, 0 + .dw 0x4793, 0xcc14, 0x47bf, 0xcc14, 0x21, 0 + .dw 0x47c1, 0xcc14, 0x47c1, 0xcc14, 0x21, 0 + .dw 0x47c3, 0xcc14, 0x47cf, 0xcc14, 0x21, 0 + .dw 0x47d1, 0xcc14, 0x47d1, 0xcc14, 0x21, 0 + .dw 0x47d3, 0xcc14, 0x47ff, 0xcc14, 0x21, 0 + .dw 0x4801, 0xcc14, 0x4801, 0xcc14, 0x21, 0 + .dw 0x4803, 0xcc14, 0x480f, 0xcc14, 0x21, 0 + .dw 0x4811, 0xcc14, 0x4811, 0xcc14, 0x21, 0 + .dw 0x4813, 0xcc14, 0x483f, 0xcc14, 0x21, 0 + .dw 0x4841, 0xcc14, 0x4841, 0xcc14, 0x21, 0 + .dw 0x4843, 0xcc14, 0x484f, 0xcc14, 0x21, 0 + .dw 0x4851, 0xcc14, 0x4851, 0xcc14, 0x21, 0 + .dw 0x4853, 0xcc14, 0x487f, 0xcc14, 0x21, 0 + .dw 0x4881, 0xcc14, 0x4881, 0xcc14, 0x21, 0 + .dw 0x4883, 0xcc14, 0x488f, 0xcc14, 0x21, 0 + .dw 0x4891, 0xcc14, 0x4891, 0xcc14, 0x21, 0 + .dw 0x4893, 0xcc14, 0x48bf, 0xcc14, 0x21, 0 + .dw 0x48c1, 0xcc14, 0x48c1, 0xcc14, 0x21, 0 + .dw 0x48c3, 0xcc14, 0x48cf, 0xcc14, 0x21, 0 + .dw 0x48d1, 0xcc14, 0x48d1, 0xcc14, 0x21, 0 + .dw 0x48d3, 0xcc14, 0x48ff, 0xcc14, 0x21, 0 + .dw 0x4901, 0xcc14, 0x4901, 0xcc14, 0x21, 0 + .dw 0x4903, 0xcc14, 0x490f, 0xcc14, 0x21, 0 + .dw 0x4911, 0xcc14, 0x4911, 0xcc14, 0x21, 0 + .dw 0x4913, 0xcc14, 0x493f, 0xcc14, 0x21, 0 + .dw 0x4941, 0xcc14, 0x4941, 0xcc14, 0x21, 0 + .dw 0x4943, 0xcc14, 0x494f, 0xcc14, 0x21, 0 + .dw 0x4951, 0xcc14, 0x4951, 0xcc14, 0x21, 0 + .dw 0x4953, 0xcc14, 0x497f, 0xcc14, 0x21, 0 + .dw 0x4981, 0xcc14, 0x4981, 0xcc14, 0x21, 0 + .dw 0x4983, 0xcc14, 0x498f, 0xcc14, 0x21, 0 + .dw 0x4991, 0xcc14, 0x4991, 0xcc14, 0x21, 0 + .dw 0x4993, 0xcc14, 0x49bf, 0xcc14, 0x21, 0 + .dw 0x49c1, 0xcc14, 0x49c1, 0xcc14, 0x21, 0 + .dw 0x49c3, 0xcc14, 0x49cf, 0xcc14, 0x21, 0 + .dw 0x49d1, 0xcc14, 0x49d1, 0xcc14, 0x21, 0 + .dw 0x49d3, 0xcc14, 0x49ff, 0xcc14, 0x21, 0 + .dw 0x4a01, 0xcc14, 0x4a01, 0xcc14, 0x21, 0 + .dw 0x4a03, 0xcc14, 0x4a0f, 0xcc14, 0x21, 0 + .dw 0x4a11, 0xcc14, 0x4a11, 0xcc14, 0x21, 0 + .dw 0x4a13, 0xcc14, 0x4a3f, 0xcc14, 0x21, 0 + .dw 0x4a41, 0xcc14, 0x4a41, 0xcc14, 0x21, 0 + .dw 0x4a43, 0xcc14, 0x4a4f, 0xcc14, 0x21, 0 + .dw 0x4a51, 0xcc14, 0x4a51, 0xcc14, 0x21, 0 + .dw 0x4a53, 0xcc14, 0x4a7f, 0xcc14, 0x21, 0 + .dw 0x4a81, 0xcc14, 0x4a81, 0xcc14, 0x21, 0 + .dw 0x4a83, 0xcc14, 0x4a8f, 0xcc14, 0x21, 0 + .dw 0x4a91, 0xcc14, 0x4a91, 0xcc14, 0x21, 0 + .dw 0x4a93, 0xcc14, 0x4abf, 0xcc14, 0x21, 0 + .dw 0x4ac1, 0xcc14, 0x4ac1, 0xcc14, 0x21, 0 + .dw 0x4ac3, 0xcc14, 0x4acf, 0xcc14, 0x21, 0 + .dw 0x4ad1, 0xcc14, 0x4ad1, 0xcc14, 0x21, 0 + .dw 0x4ad3, 0xcc14, 0x4aff, 0xcc14, 0x21, 0 + .dw 0x4b01, 0xcc14, 0x4b01, 0xcc14, 0x21, 0 + .dw 0x4b03, 0xcc14, 0x4b0f, 0xcc14, 0x21, 0 + .dw 0x4b11, 0xcc14, 0x4b11, 0xcc14, 0x21, 0 + .dw 0x4b13, 0xcc14, 0x4b3f, 0xcc14, 0x21, 0 + .dw 0x4b41, 0xcc14, 0x4b41, 0xcc14, 0x21, 0 + .dw 0x4b43, 0xcc14, 0x4b4f, 0xcc14, 0x21, 0 + .dw 0x4b51, 0xcc14, 0x4b51, 0xcc14, 0x21, 0 + .dw 0x4b53, 0xcc14, 0x4b7f, 0xcc14, 0x21, 0 + .dw 0x4b81, 0xcc14, 0x4b81, 0xcc14, 0x21, 0 + .dw 0x4b83, 0xcc14, 0x4b8f, 0xcc14, 0x21, 0 + .dw 0x4b91, 0xcc14, 0x4b91, 0xcc14, 0x21, 0 + .dw 0x4b93, 0xcc14, 0x4bbf, 0xcc14, 0x21, 0 + .dw 0x4bc1, 0xcc14, 0x4bc1, 0xcc14, 0x21, 0 + .dw 0x4bc3, 0xcc14, 0x4bcf, 0xcc14, 0x21, 0 + .dw 0x4bd1, 0xcc14, 0x4bd1, 0xcc14, 0x21, 0 + .dw 0x4bd3, 0xcc14, 0x4bff, 0xcc14, 0x21, 0 + .dw 0x4c01, 0xcc14, 0x4c01, 0xcc14, 0x21, 0 + .dw 0x4c03, 0xcc14, 0x4c0f, 0xcc14, 0x21, 0 + .dw 0x4c11, 0xcc14, 0x4c11, 0xcc14, 0x21, 0 + .dw 0x4c13, 0xcc14, 0x4c3f, 0xcc14, 0x21, 0 + .dw 0x4c41, 0xcc14, 0x4c41, 0xcc14, 0x21, 0 + .dw 0x4c43, 0xcc14, 0x4c4f, 0xcc14, 0x21, 0 + .dw 0x4c51, 0xcc14, 0x4c51, 0xcc14, 0x21, 0 + .dw 0x4c53, 0xcc14, 0x4c7f, 0xcc14, 0x21, 0 + .dw 0x4c81, 0xcc14, 0x4c81, 0xcc14, 0x21, 0 + .dw 0x4c83, 0xcc14, 0x4c8f, 0xcc14, 0x21, 0 + .dw 0x4c91, 0xcc14, 0x4c91, 0xcc14, 0x21, 0 + .dw 0x4c93, 0xcc14, 0x4cbf, 0xcc14, 0x21, 0 + .dw 0x4cc1, 0xcc14, 0x4cc1, 0xcc14, 0x21, 0 + .dw 0x4cc3, 0xcc14, 0x4ccf, 0xcc14, 0x21, 0 + .dw 0x4cd1, 0xcc14, 0x4cd1, 0xcc14, 0x21, 0 + .dw 0x4cd3, 0xcc14, 0x4cff, 0xcc14, 0x21, 0 + .dw 0x4d01, 0xcc14, 0x4d01, 0xcc14, 0x21, 0 + .dw 0x4d03, 0xcc14, 0x4d0f, 0xcc14, 0x21, 0 + .dw 0x4d11, 0xcc14, 0x4d11, 0xcc14, 0x21, 0 + .dw 0x4d13, 0xcc14, 0x4d3f, 0xcc14, 0x21, 0 + .dw 0x4d41, 0xcc14, 0x4d41, 0xcc14, 0x21, 0 + .dw 0x4d43, 0xcc14, 0x4d4f, 0xcc14, 0x21, 0 + .dw 0x4d51, 0xcc14, 0x4d51, 0xcc14, 0x21, 0 + .dw 0x4d53, 0xcc14, 0x4d7f, 0xcc14, 0x21, 0 + .dw 0x4d81, 0xcc14, 0x4d81, 0xcc14, 0x21, 0 + .dw 0x4d83, 0xcc14, 0x4d8f, 0xcc14, 0x21, 0 + .dw 0x4d91, 0xcc14, 0x4d91, 0xcc14, 0x21, 0 + .dw 0x4d93, 0xcc14, 0x4dbf, 0xcc14, 0x21, 0 + .dw 0x4dc1, 0xcc14, 0x4dc1, 0xcc14, 0x21, 0 + .dw 0x4dc3, 0xcc14, 0x4dcf, 0xcc14, 0x21, 0 + .dw 0x4dd1, 0xcc14, 0x4dd1, 0xcc14, 0x21, 0 + .dw 0x4dd3, 0xcc14, 0x4dff, 0xcc14, 0x21, 0 + .dw 0x4e01, 0xcc14, 0x4e01, 0xcc14, 0x21, 0 + .dw 0x4e03, 0xcc14, 0x4e0f, 0xcc14, 0x21, 0 + .dw 0x4e11, 0xcc14, 0x4e11, 0xcc14, 0x21, 0 + .dw 0x4e13, 0xcc14, 0x4e3f, 0xcc14, 0x21, 0 + .dw 0x4e41, 0xcc14, 0x4e41, 0xcc14, 0x21, 0 + .dw 0x4e43, 0xcc14, 0x4e4f, 0xcc14, 0x21, 0 + .dw 0x4e51, 0xcc14, 0x4e51, 0xcc14, 0x21, 0 + .dw 0x4e53, 0xcc14, 0x4e7f, 0xcc14, 0x21, 0 + .dw 0x4e81, 0xcc14, 0x4e81, 0xcc14, 0x21, 0 + .dw 0x4e83, 0xcc14, 0x4e8f, 0xcc14, 0x21, 0 + .dw 0x4e91, 0xcc14, 0x4e91, 0xcc14, 0x21, 0 + .dw 0x4e93, 0xcc14, 0x4ebf, 0xcc14, 0x21, 0 + .dw 0x4ec1, 0xcc14, 0x4ec1, 0xcc14, 0x21, 0 + .dw 0x4ec3, 0xcc14, 0x4ecf, 0xcc14, 0x21, 0 + .dw 0x4ed1, 0xcc14, 0x4ed1, 0xcc14, 0x21, 0 + .dw 0x4ed3, 0xcc14, 0x4eff, 0xcc14, 0x21, 0 + .dw 0x4f01, 0xcc14, 0x4f01, 0xcc14, 0x21, 0 + .dw 0x4f03, 0xcc14, 0x4f0f, 0xcc14, 0x21, 0 + .dw 0x4f11, 0xcc14, 0x4f11, 0xcc14, 0x21, 0 + .dw 0x4f13, 0xcc14, 0x4f3f, 0xcc14, 0x21, 0 + .dw 0x4f41, 0xcc14, 0x4f41, 0xcc14, 0x21, 0 + .dw 0x4f43, 0xcc14, 0x4f4f, 0xcc14, 0x21, 0 + .dw 0x4f51, 0xcc14, 0x4f51, 0xcc14, 0x21, 0 + .dw 0x4f53, 0xcc14, 0x4f7f, 0xcc14, 0x21, 0 + .dw 0x4f81, 0xcc14, 0x4f81, 0xcc14, 0x21, 0 + .dw 0x4f83, 0xcc14, 0x4f8f, 0xcc14, 0x21, 0 + .dw 0x4f91, 0xcc14, 0x4f91, 0xcc14, 0x21, 0 + .dw 0x4f93, 0xcc14, 0x4fbf, 0xcc14, 0x21, 0 + .dw 0x4fc1, 0xcc14, 0x4fc1, 0xcc14, 0x21, 0 + .dw 0x4fc3, 0xcc14, 0x4fcf, 0xcc14, 0x21, 0 + .dw 0x4fd1, 0xcc14, 0x4fd1, 0xcc14, 0x21, 0 + .dw 0x4fd3, 0xcc14, 0x5fff, 0xcc14, 0x21, 0 + .dw 0x6001, 0xcc14, 0x6001, 0xcc14, 0x21, 0 + .dw 0x6003, 0xcc14, 0x600f, 0xcc14, 0x21, 0 + .dw 0x6011, 0xcc14, 0x6011, 0xcc14, 0x21, 0 + .dw 0x6013, 0xcc14, 0x603f, 0xcc14, 0x21, 0 + .dw 0x6041, 0xcc14, 0x6041, 0xcc14, 0x21, 0 + .dw 0x6043, 0xcc14, 0x604f, 0xcc14, 0x21, 0 + .dw 0x6051, 0xcc14, 0x6051, 0xcc14, 0x21, 0 + .dw 0x6053, 0xcc14, 0x607f, 0xcc14, 0x21, 0 + .dw 0x6081, 0xcc14, 0x6081, 0xcc14, 0x21, 0 + .dw 0x6083, 0xcc14, 0x608f, 0xcc14, 0x21, 0 + .dw 0x6091, 0xcc14, 0x6091, 0xcc14, 0x21, 0 + .dw 0x6093, 0xcc14, 0x60bf, 0xcc14, 0x21, 0 + .dw 0x60c1, 0xcc14, 0x60c1, 0xcc14, 0x21, 0 + .dw 0x60c3, 0xcc14, 0x60cf, 0xcc14, 0x21, 0 + .dw 0x60d1, 0xcc14, 0x60d1, 0xcc14, 0x21, 0 + .dw 0x60d3, 0xcc14, 0x60ff, 0xcc14, 0x21, 0 + .dw 0x6101, 0xcc14, 0x6101, 0xcc14, 0x21, 0 + .dw 0x6103, 0xcc14, 0x610f, 0xcc14, 0x21, 0 + .dw 0x6111, 0xcc14, 0x6111, 0xcc14, 0x21, 0 + .dw 0x6113, 0xcc14, 0x613f, 0xcc14, 0x21, 0 + .dw 0x6141, 0xcc14, 0x6141, 0xcc14, 0x21, 0 + .dw 0x6143, 0xcc14, 0x614f, 0xcc14, 0x21, 0 + .dw 0x6151, 0xcc14, 0x6151, 0xcc14, 0x21, 0 + .dw 0x6153, 0xcc14, 0x617f, 0xcc14, 0x21, 0 + .dw 0x6181, 0xcc14, 0x6181, 0xcc14, 0x21, 0 + .dw 0x6183, 0xcc14, 0x618f, 0xcc14, 0x21, 0 + .dw 0x6191, 0xcc14, 0x6191, 0xcc14, 0x21, 0 + .dw 0x6193, 0xcc14, 0x61bf, 0xcc14, 0x21, 0 + .dw 0x61c1, 0xcc14, 0x61c1, 0xcc14, 0x21, 0 + .dw 0x61c3, 0xcc14, 0x61cf, 0xcc14, 0x21, 0 + .dw 0x61d1, 0xcc14, 0x61d1, 0xcc14, 0x21, 0 + .dw 0x61d3, 0xcc14, 0x61ff, 0xcc14, 0x21, 0 + .dw 0x6201, 0xcc14, 0x6201, 0xcc14, 0x21, 0 + .dw 0x6203, 0xcc14, 0x620f, 0xcc14, 0x21, 0 + .dw 0x6211, 0xcc14, 0x6211, 0xcc14, 0x21, 0 + .dw 0x6213, 0xcc14, 0x623f, 0xcc14, 0x21, 0 + .dw 0x6241, 0xcc14, 0x6241, 0xcc14, 0x21, 0 + .dw 0x6243, 0xcc14, 0x624f, 0xcc14, 0x21, 0 + .dw 0x6251, 0xcc14, 0x6251, 0xcc14, 0x21, 0 + .dw 0x6253, 0xcc14, 0x627f, 0xcc14, 0x21, 0 + .dw 0x6281, 0xcc14, 0x6281, 0xcc14, 0x21, 0 + .dw 0x6283, 0xcc14, 0x628f, 0xcc14, 0x21, 0 + .dw 0x6291, 0xcc14, 0x6291, 0xcc14, 0x21, 0 + .dw 0x6293, 0xcc14, 0x62bf, 0xcc14, 0x21, 0 + .dw 0x62c1, 0xcc14, 0x62c1, 0xcc14, 0x21, 0 + .dw 0x62c3, 0xcc14, 0x62cf, 0xcc14, 0x21, 0 + .dw 0x62d1, 0xcc14, 0x62d1, 0xcc14, 0x21, 0 + .dw 0x62d3, 0xcc14, 0x62ff, 0xcc14, 0x21, 0 + .dw 0x6301, 0xcc14, 0x6301, 0xcc14, 0x21, 0 + .dw 0x6303, 0xcc14, 0x630f, 0xcc14, 0x21, 0 + .dw 0x6311, 0xcc14, 0x6311, 0xcc14, 0x21, 0 + .dw 0x6313, 0xcc14, 0x633f, 0xcc14, 0x21, 0 + .dw 0x6341, 0xcc14, 0x6341, 0xcc14, 0x21, 0 + .dw 0x6343, 0xcc14, 0x634f, 0xcc14, 0x21, 0 + .dw 0x6351, 0xcc14, 0x6351, 0xcc14, 0x21, 0 + .dw 0x6353, 0xcc14, 0x637f, 0xcc14, 0x21, 0 + .dw 0x6381, 0xcc14, 0x6381, 0xcc14, 0x21, 0 + .dw 0x6383, 0xcc14, 0x638f, 0xcc14, 0x21, 0 + .dw 0x6391, 0xcc14, 0x6391, 0xcc14, 0x21, 0 + .dw 0x6393, 0xcc14, 0x63bf, 0xcc14, 0x21, 0 + .dw 0x63c1, 0xcc14, 0x63c1, 0xcc14, 0x21, 0 + .dw 0x63c3, 0xcc14, 0x63cf, 0xcc14, 0x21, 0 + .dw 0x63d1, 0xcc14, 0x63d1, 0xcc14, 0x21, 0 + .dw 0x63d3, 0xcc14, 0x63ff, 0xcc14, 0x21, 0 + .dw 0x6401, 0xcc14, 0x6401, 0xcc14, 0x21, 0 + .dw 0x6403, 0xcc14, 0x640f, 0xcc14, 0x21, 0 + .dw 0x6411, 0xcc14, 0x6411, 0xcc14, 0x21, 0 + .dw 0x6413, 0xcc14, 0x643f, 0xcc14, 0x21, 0 + .dw 0x6441, 0xcc14, 0x6441, 0xcc14, 0x21, 0 + .dw 0x6443, 0xcc14, 0x644f, 0xcc14, 0x21, 0 + .dw 0x6451, 0xcc14, 0x6451, 0xcc14, 0x21, 0 + .dw 0x6453, 0xcc14, 0x647f, 0xcc14, 0x21, 0 + .dw 0x6481, 0xcc14, 0x6481, 0xcc14, 0x21, 0 + .dw 0x6483, 0xcc14, 0x648f, 0xcc14, 0x21, 0 + .dw 0x6491, 0xcc14, 0x6491, 0xcc14, 0x21, 0 + .dw 0x6493, 0xcc14, 0x64bf, 0xcc14, 0x21, 0 + .dw 0x64c1, 0xcc14, 0x64c1, 0xcc14, 0x21, 0 + .dw 0x64c3, 0xcc14, 0x64cf, 0xcc14, 0x21, 0 + .dw 0x64d1, 0xcc14, 0x64d1, 0xcc14, 0x21, 0 + .dw 0x64d3, 0xcc14, 0x64ff, 0xcc14, 0x21, 0 + .dw 0x6501, 0xcc14, 0x6501, 0xcc14, 0x21, 0 + .dw 0x6503, 0xcc14, 0x650f, 0xcc14, 0x21, 0 + .dw 0x6511, 0xcc14, 0x6511, 0xcc14, 0x21, 0 + .dw 0x6513, 0xcc14, 0x653f, 0xcc14, 0x21, 0 + .dw 0x6541, 0xcc14, 0x6541, 0xcc14, 0x21, 0 + .dw 0x6543, 0xcc14, 0x654f, 0xcc14, 0x21, 0 + .dw 0x6551, 0xcc14, 0x6551, 0xcc14, 0x21, 0 + .dw 0x6553, 0xcc14, 0x657f, 0xcc14, 0x21, 0 + .dw 0x6581, 0xcc14, 0x6581, 0xcc14, 0x21, 0 + .dw 0x6583, 0xcc14, 0x658f, 0xcc14, 0x21, 0 + .dw 0x6591, 0xcc14, 0x6591, 0xcc14, 0x21, 0 + .dw 0x6593, 0xcc14, 0x65bf, 0xcc14, 0x21, 0 + .dw 0x65c1, 0xcc14, 0x65c1, 0xcc14, 0x21, 0 + .dw 0x65c3, 0xcc14, 0x65cf, 0xcc14, 0x21, 0 + .dw 0x65d1, 0xcc14, 0x65d1, 0xcc14, 0x21, 0 + .dw 0x65d3, 0xcc14, 0x65ff, 0xcc14, 0x21, 0 + .dw 0x6601, 0xcc14, 0x6601, 0xcc14, 0x21, 0 + .dw 0x6603, 0xcc14, 0x660f, 0xcc14, 0x21, 0 + .dw 0x6611, 0xcc14, 0x6611, 0xcc14, 0x21, 0 + .dw 0x6613, 0xcc14, 0x663f, 0xcc14, 0x21, 0 + .dw 0x6641, 0xcc14, 0x6641, 0xcc14, 0x21, 0 + .dw 0x6643, 0xcc14, 0x664f, 0xcc14, 0x21, 0 + .dw 0x6651, 0xcc14, 0x6651, 0xcc14, 0x21, 0 + .dw 0x6653, 0xcc14, 0x667f, 0xcc14, 0x21, 0 + .dw 0x6681, 0xcc14, 0x6681, 0xcc14, 0x21, 0 + .dw 0x6683, 0xcc14, 0x668f, 0xcc14, 0x21, 0 + .dw 0x6691, 0xcc14, 0x6691, 0xcc14, 0x21, 0 + .dw 0x6693, 0xcc14, 0x66bf, 0xcc14, 0x21, 0 + .dw 0x66c1, 0xcc14, 0x66c1, 0xcc14, 0x21, 0 + .dw 0x66c3, 0xcc14, 0x66cf, 0xcc14, 0x21, 0 + .dw 0x66d1, 0xcc14, 0x66d1, 0xcc14, 0x21, 0 + .dw 0x66d3, 0xcc14, 0x66ff, 0xcc14, 0x21, 0 + .dw 0x6701, 0xcc14, 0x6701, 0xcc14, 0x21, 0 + .dw 0x6703, 0xcc14, 0x670f, 0xcc14, 0x21, 0 + .dw 0x6711, 0xcc14, 0x6711, 0xcc14, 0x21, 0 + .dw 0x6713, 0xcc14, 0x673f, 0xcc14, 0x21, 0 + .dw 0x6741, 0xcc14, 0x6741, 0xcc14, 0x21, 0 + .dw 0x6743, 0xcc14, 0x674f, 0xcc14, 0x21, 0 + .dw 0x6751, 0xcc14, 0x6751, 0xcc14, 0x21, 0 + .dw 0x6753, 0xcc14, 0x677f, 0xcc14, 0x21, 0 + .dw 0x6781, 0xcc14, 0x6781, 0xcc14, 0x21, 0 + .dw 0x6783, 0xcc14, 0x678f, 0xcc14, 0x21, 0 + .dw 0x6791, 0xcc14, 0x6791, 0xcc14, 0x21, 0 + .dw 0x6793, 0xcc14, 0x67bf, 0xcc14, 0x21, 0 + .dw 0x67c1, 0xcc14, 0x67c1, 0xcc14, 0x21, 0 + .dw 0x67c3, 0xcc14, 0x67cf, 0xcc14, 0x21, 0 + .dw 0x67d1, 0xcc14, 0x67d1, 0xcc14, 0x21, 0 + .dw 0x67d3, 0xcc14, 0x67ff, 0xcc14, 0x21, 0 + .dw 0x6801, 0xcc14, 0x6801, 0xcc14, 0x21, 0 + .dw 0x6803, 0xcc14, 0x680f, 0xcc14, 0x21, 0 + .dw 0x6811, 0xcc14, 0x6811, 0xcc14, 0x21, 0 + .dw 0x6813, 0xcc14, 0x683f, 0xcc14, 0x21, 0 + .dw 0x6841, 0xcc14, 0x6841, 0xcc14, 0x21, 0 + .dw 0x6843, 0xcc14, 0x684f, 0xcc14, 0x21, 0 + .dw 0x6851, 0xcc14, 0x6851, 0xcc14, 0x21, 0 + .dw 0x6853, 0xcc14, 0x687f, 0xcc14, 0x21, 0 + .dw 0x6881, 0xcc14, 0x6881, 0xcc14, 0x21, 0 + .dw 0x6883, 0xcc14, 0x688f, 0xcc14, 0x21, 0 + .dw 0x6891, 0xcc14, 0x6891, 0xcc14, 0x21, 0 + .dw 0x6893, 0xcc14, 0x68bf, 0xcc14, 0x21, 0 + .dw 0x68c1, 0xcc14, 0x68c1, 0xcc14, 0x21, 0 + .dw 0x68c3, 0xcc14, 0x68cf, 0xcc14, 0x21, 0 + .dw 0x68d1, 0xcc14, 0x68d1, 0xcc14, 0x21, 0 + .dw 0x68d3, 0xcc14, 0x68ff, 0xcc14, 0x21, 0 + .dw 0x6901, 0xcc14, 0x6901, 0xcc14, 0x21, 0 + .dw 0x6903, 0xcc14, 0x690f, 0xcc14, 0x21, 0 + .dw 0x6911, 0xcc14, 0x6911, 0xcc14, 0x21, 0 + .dw 0x6913, 0xcc14, 0x693f, 0xcc14, 0x21, 0 + .dw 0x6941, 0xcc14, 0x6941, 0xcc14, 0x21, 0 + .dw 0x6943, 0xcc14, 0x694f, 0xcc14, 0x21, 0 + .dw 0x6951, 0xcc14, 0x6951, 0xcc14, 0x21, 0 + .dw 0x6953, 0xcc14, 0x697f, 0xcc14, 0x21, 0 + .dw 0x6981, 0xcc14, 0x6981, 0xcc14, 0x21, 0 + .dw 0x6983, 0xcc14, 0x698f, 0xcc14, 0x21, 0 + .dw 0x6991, 0xcc14, 0x6991, 0xcc14, 0x21, 0 + .dw 0x6993, 0xcc14, 0x69bf, 0xcc14, 0x21, 0 + .dw 0x69c1, 0xcc14, 0x69c1, 0xcc14, 0x21, 0 + .dw 0x69c3, 0xcc14, 0x69cf, 0xcc14, 0x21, 0 + .dw 0x69d1, 0xcc14, 0x69d1, 0xcc14, 0x21, 0 + .dw 0x69d3, 0xcc14, 0x69ff, 0xcc14, 0x21, 0 + .dw 0x6a01, 0xcc14, 0x6a01, 0xcc14, 0x21, 0 + .dw 0x6a03, 0xcc14, 0x6a0f, 0xcc14, 0x21, 0 + .dw 0x6a11, 0xcc14, 0x6a11, 0xcc14, 0x21, 0 + .dw 0x6a13, 0xcc14, 0x6a3f, 0xcc14, 0x21, 0 + .dw 0x6a41, 0xcc14, 0x6a41, 0xcc14, 0x21, 0 + .dw 0x6a43, 0xcc14, 0x6a4f, 0xcc14, 0x21, 0 + .dw 0x6a51, 0xcc14, 0x6a51, 0xcc14, 0x21, 0 + .dw 0x6a53, 0xcc14, 0x6a7f, 0xcc14, 0x21, 0 + .dw 0x6a81, 0xcc14, 0x6a81, 0xcc14, 0x21, 0 + .dw 0x6a83, 0xcc14, 0x6a8f, 0xcc14, 0x21, 0 + .dw 0x6a91, 0xcc14, 0x6a91, 0xcc14, 0x21, 0 + .dw 0x6a93, 0xcc14, 0x6abf, 0xcc14, 0x21, 0 + .dw 0x6ac1, 0xcc14, 0x6ac1, 0xcc14, 0x21, 0 + .dw 0x6ac3, 0xcc14, 0x6acf, 0xcc14, 0x21, 0 + .dw 0x6ad1, 0xcc14, 0x6ad1, 0xcc14, 0x21, 0 + .dw 0x6ad3, 0xcc14, 0x6aff, 0xcc14, 0x21, 0 + .dw 0x6b01, 0xcc14, 0x6b01, 0xcc14, 0x21, 0 + .dw 0x6b03, 0xcc14, 0x6b0f, 0xcc14, 0x21, 0 + .dw 0x6b11, 0xcc14, 0x6b11, 0xcc14, 0x21, 0 + .dw 0x6b13, 0xcc14, 0x6b3f, 0xcc14, 0x21, 0 + .dw 0x6b41, 0xcc14, 0x6b41, 0xcc14, 0x21, 0 + .dw 0x6b43, 0xcc14, 0x6b4f, 0xcc14, 0x21, 0 + .dw 0x6b51, 0xcc14, 0x6b51, 0xcc14, 0x21, 0 + .dw 0x6b53, 0xcc14, 0x6b7f, 0xcc14, 0x21, 0 + .dw 0x6b81, 0xcc14, 0x6b81, 0xcc14, 0x21, 0 + .dw 0x6b83, 0xcc14, 0x6b8f, 0xcc14, 0x21, 0 + .dw 0x6b91, 0xcc14, 0x6b91, 0xcc14, 0x21, 0 + .dw 0x6b93, 0xcc14, 0x6bbf, 0xcc14, 0x21, 0 + .dw 0x6bc1, 0xcc14, 0x6bc1, 0xcc14, 0x21, 0 + .dw 0x6bc3, 0xcc14, 0x6bcf, 0xcc14, 0x21, 0 + .dw 0x6bd1, 0xcc14, 0x6bd1, 0xcc14, 0x21, 0 + .dw 0x6bd3, 0xcc14, 0x6bff, 0xcc14, 0x21, 0 + .dw 0x6c01, 0xcc14, 0x6c01, 0xcc14, 0x21, 0 + .dw 0x6c03, 0xcc14, 0x6c0f, 0xcc14, 0x21, 0 + .dw 0x6c11, 0xcc14, 0x6c11, 0xcc14, 0x21, 0 + .dw 0x6c13, 0xcc14, 0x6c3f, 0xcc14, 0x21, 0 + .dw 0x6c41, 0xcc14, 0x6c41, 0xcc14, 0x21, 0 + .dw 0x6c43, 0xcc14, 0x6c4f, 0xcc14, 0x21, 0 + .dw 0x6c51, 0xcc14, 0x6c51, 0xcc14, 0x21, 0 + .dw 0x6c53, 0xcc14, 0x6c7f, 0xcc14, 0x21, 0 + .dw 0x6c81, 0xcc14, 0x6c81, 0xcc14, 0x21, 0 + .dw 0x6c83, 0xcc14, 0x6c8f, 0xcc14, 0x21, 0 + .dw 0x6c91, 0xcc14, 0x6c91, 0xcc14, 0x21, 0 + .dw 0x6c93, 0xcc14, 0x6cbf, 0xcc14, 0x21, 0 + .dw 0x6cc1, 0xcc14, 0x6cc1, 0xcc14, 0x21, 0 + .dw 0x6cc3, 0xcc14, 0x6ccf, 0xcc14, 0x21, 0 + .dw 0x6cd1, 0xcc14, 0x6cd1, 0xcc14, 0x21, 0 + .dw 0x6cd3, 0xcc14, 0x6cff, 0xcc14, 0x21, 0 + .dw 0x6d01, 0xcc14, 0x6d01, 0xcc14, 0x21, 0 + .dw 0x6d03, 0xcc14, 0x6d0f, 0xcc14, 0x21, 0 + .dw 0x6d11, 0xcc14, 0x6d11, 0xcc14, 0x21, 0 + .dw 0x6d13, 0xcc14, 0x6d3f, 0xcc14, 0x21, 0 + .dw 0x6d41, 0xcc14, 0x6d41, 0xcc14, 0x21, 0 + .dw 0x6d43, 0xcc14, 0x6d4f, 0xcc14, 0x21, 0 + .dw 0x6d51, 0xcc14, 0x6d51, 0xcc14, 0x21, 0 + .dw 0x6d53, 0xcc14, 0x6d7f, 0xcc14, 0x21, 0 + .dw 0x6d81, 0xcc14, 0x6d81, 0xcc14, 0x21, 0 + .dw 0x6d83, 0xcc14, 0x6d8f, 0xcc14, 0x21, 0 + .dw 0x6d91, 0xcc14, 0x6d91, 0xcc14, 0x21, 0 + .dw 0x6d93, 0xcc14, 0x6dbf, 0xcc14, 0x21, 0 + .dw 0x6dc1, 0xcc14, 0x6dc1, 0xcc14, 0x21, 0 + .dw 0x6dc3, 0xcc14, 0x6dcf, 0xcc14, 0x21, 0 + .dw 0x6dd1, 0xcc14, 0x6dd1, 0xcc14, 0x21, 0 + .dw 0x6dd3, 0xcc14, 0x6dff, 0xcc14, 0x21, 0 + .dw 0x6e01, 0xcc14, 0x6e01, 0xcc14, 0x21, 0 + .dw 0x6e03, 0xcc14, 0x6e0f, 0xcc14, 0x21, 0 + .dw 0x6e11, 0xcc14, 0x6e11, 0xcc14, 0x21, 0 + .dw 0x6e13, 0xcc14, 0x6e3f, 0xcc14, 0x21, 0 + .dw 0x6e41, 0xcc14, 0x6e41, 0xcc14, 0x21, 0 + .dw 0x6e43, 0xcc14, 0x6e4f, 0xcc14, 0x21, 0 + .dw 0x6e51, 0xcc14, 0x6e51, 0xcc14, 0x21, 0 + .dw 0x6e53, 0xcc14, 0x6e7f, 0xcc14, 0x21, 0 + .dw 0x6e81, 0xcc14, 0x6e81, 0xcc14, 0x21, 0 + .dw 0x6e83, 0xcc14, 0x6e8f, 0xcc14, 0x21, 0 + .dw 0x6e91, 0xcc14, 0x6e91, 0xcc14, 0x21, 0 + .dw 0x6e93, 0xcc14, 0x6ebf, 0xcc14, 0x21, 0 + .dw 0x6ec1, 0xcc14, 0x6ec1, 0xcc14, 0x21, 0 + .dw 0x6ec3, 0xcc14, 0x6ecf, 0xcc14, 0x21, 0 + .dw 0x6ed1, 0xcc14, 0x6ed1, 0xcc14, 0x21, 0 + .dw 0x6ed3, 0xcc14, 0x6eff, 0xcc14, 0x21, 0 + .dw 0x6f01, 0xcc14, 0x6f01, 0xcc14, 0x21, 0 + .dw 0x6f03, 0xcc14, 0x6f0f, 0xcc14, 0x21, 0 + .dw 0x6f11, 0xcc14, 0x6f11, 0xcc14, 0x21, 0 + .dw 0x6f13, 0xcc14, 0x6f3f, 0xcc14, 0x21, 0 + .dw 0x6f41, 0xcc14, 0x6f41, 0xcc14, 0x21, 0 + .dw 0x6f43, 0xcc14, 0x6f4f, 0xcc14, 0x21, 0 + .dw 0x6f51, 0xcc14, 0x6f51, 0xcc14, 0x21, 0 + .dw 0x6f53, 0xcc14, 0x6f7f, 0xcc14, 0x21, 0 + .dw 0x6f81, 0xcc14, 0x6f81, 0xcc14, 0x21, 0 + .dw 0x6f83, 0xcc14, 0x6f8f, 0xcc14, 0x21, 0 + .dw 0x6f91, 0xcc14, 0x6f91, 0xcc14, 0x21, 0 + .dw 0x6f93, 0xcc14, 0x6fbf, 0xcc14, 0x21, 0 + .dw 0x6fc1, 0xcc14, 0x6fc1, 0xcc14, 0x21, 0 + .dw 0x6fc3, 0xcc14, 0x6fcf, 0xcc14, 0x21, 0 + .dw 0x6fd1, 0xcc14, 0x6fd1, 0xcc14, 0x21, 0 + .dw 0x6fd3, 0xcc14, 0xffff, 0xcc14, 0x21, 0 + .dw 0x0000, 0xcc15, 0x0000, 0xcc15, 0x22, 0 + .dw 0x0001, 0xcc15, 0x0001, 0xcc15, 0x21, 0 + .dw 0x0002, 0xcc15, 0x0002, 0xcc15, 0x22, 0 + .dw 0x0003, 0xcc15, 0x000f, 0xcc15, 0x21, 0 + .dw 0x0010, 0xcc15, 0x0010, 0xcc15, 0x22, 0 + .dw 0x0011, 0xcc15, 0x0011, 0xcc15, 0x21, 0 + .dw 0x0012, 0xcc15, 0x0012, 0xcc15, 0x22, 0 + .dw 0x0013, 0xcc15, 0x003f, 0xcc15, 0x21, 0 + .dw 0x0041, 0xcc15, 0x0041, 0xcc15, 0x21, 0 + .dw 0x0043, 0xcc15, 0x004f, 0xcc15, 0x21, 0 + .dw 0x0051, 0xcc15, 0x0051, 0xcc15, 0x21, 0 + .dw 0x0053, 0xcc15, 0x007f, 0xcc15, 0x21, 0 + .dw 0x0081, 0xcc15, 0x0081, 0xcc15, 0x21, 0 + .dw 0x0083, 0xcc15, 0x008f, 0xcc15, 0x21, 0 + .dw 0x0091, 0xcc15, 0x0091, 0xcc15, 0x21, 0 + .dw 0x0093, 0xcc15, 0x00bf, 0xcc15, 0x21, 0 + .dw 0x00c1, 0xcc15, 0x00c1, 0xcc15, 0x21, 0 + .dw 0x00c3, 0xcc15, 0x00cf, 0xcc15, 0x21, 0 + .dw 0x00d1, 0xcc15, 0x00d1, 0xcc15, 0x21, 0 + .dw 0x00d3, 0xcc15, 0x00ff, 0xcc15, 0x21, 0 + .dw 0x0101, 0xcc15, 0x0101, 0xcc15, 0x21, 0 + .dw 0x0103, 0xcc15, 0x010f, 0xcc15, 0x21, 0 + .dw 0x0111, 0xcc15, 0x0111, 0xcc15, 0x21, 0 + .dw 0x0113, 0xcc15, 0x013f, 0xcc15, 0x21, 0 + .dw 0x0141, 0xcc15, 0x0141, 0xcc15, 0x21, 0 + .dw 0x0143, 0xcc15, 0x014f, 0xcc15, 0x21, 0 + .dw 0x0151, 0xcc15, 0x0151, 0xcc15, 0x21, 0 + .dw 0x0153, 0xcc15, 0x017f, 0xcc15, 0x21, 0 + .dw 0x0181, 0xcc15, 0x0181, 0xcc15, 0x21, 0 + .dw 0x0183, 0xcc15, 0x018f, 0xcc15, 0x21, 0 + .dw 0x0191, 0xcc15, 0x0191, 0xcc15, 0x21, 0 + .dw 0x0193, 0xcc15, 0x01bf, 0xcc15, 0x21, 0 + .dw 0x01c1, 0xcc15, 0x01c1, 0xcc15, 0x21, 0 + .dw 0x01c3, 0xcc15, 0x01cf, 0xcc15, 0x21, 0 + .dw 0x01d1, 0xcc15, 0x01d1, 0xcc15, 0x21, 0 + .dw 0x01d3, 0xcc15, 0x01ff, 0xcc15, 0x21, 0 + .dw 0x0201, 0xcc15, 0x0201, 0xcc15, 0x21, 0 + .dw 0x0203, 0xcc15, 0x020f, 0xcc15, 0x21, 0 + .dw 0x0211, 0xcc15, 0x0211, 0xcc15, 0x21, 0 + .dw 0x0213, 0xcc15, 0x023f, 0xcc15, 0x21, 0 + .dw 0x0240, 0xcc15, 0x0240, 0xcc15, 0x22, 0 + .dw 0x0241, 0xcc15, 0x0241, 0xcc15, 0x21, 0 + .dw 0x0242, 0xcc15, 0x0242, 0xcc15, 0x22, 0 + .dw 0x0243, 0xcc15, 0x024f, 0xcc15, 0x21, 0 + .dw 0x0250, 0xcc15, 0x0250, 0xcc15, 0x22, 0 + .dw 0x0251, 0xcc15, 0x0251, 0xcc15, 0x21, 0 + .dw 0x0252, 0xcc15, 0x0252, 0xcc15, 0x22, 0 + .dw 0x0253, 0xcc15, 0x027f, 0xcc15, 0x21, 0 + .dw 0x0281, 0xcc15, 0x0281, 0xcc15, 0x21, 0 + .dw 0x0283, 0xcc15, 0x028f, 0xcc15, 0x21, 0 + .dw 0x0291, 0xcc15, 0x0291, 0xcc15, 0x21, 0 + .dw 0x0293, 0xcc15, 0x02bf, 0xcc15, 0x21, 0 + .dw 0x02c1, 0xcc15, 0x02c1, 0xcc15, 0x21, 0 + .dw 0x02c3, 0xcc15, 0x02cf, 0xcc15, 0x21, 0 + .dw 0x02d1, 0xcc15, 0x02d1, 0xcc15, 0x21, 0 + .dw 0x02d3, 0xcc15, 0x02ff, 0xcc15, 0x21, 0 + .dw 0x0301, 0xcc15, 0x0301, 0xcc15, 0x21, 0 + .dw 0x0303, 0xcc15, 0x030f, 0xcc15, 0x21, 0 + .dw 0x0311, 0xcc15, 0x0311, 0xcc15, 0x21, 0 + .dw 0x0313, 0xcc15, 0x033f, 0xcc15, 0x21, 0 + .dw 0x0341, 0xcc15, 0x0341, 0xcc15, 0x21, 0 + .dw 0x0343, 0xcc15, 0x034f, 0xcc15, 0x21, 0 + .dw 0x0351, 0xcc15, 0x0351, 0xcc15, 0x21, 0 + .dw 0x0353, 0xcc15, 0x037f, 0xcc15, 0x21, 0 + .dw 0x0381, 0xcc15, 0x0381, 0xcc15, 0x21, 0 + .dw 0x0383, 0xcc15, 0x038f, 0xcc15, 0x21, 0 + .dw 0x0391, 0xcc15, 0x0391, 0xcc15, 0x21, 0 + .dw 0x0393, 0xcc15, 0x03bf, 0xcc15, 0x21, 0 + .dw 0x03c1, 0xcc15, 0x03c1, 0xcc15, 0x21, 0 + .dw 0x03c3, 0xcc15, 0x03cf, 0xcc15, 0x21, 0 + .dw 0x03d1, 0xcc15, 0x03d1, 0xcc15, 0x21, 0 + .dw 0x03d3, 0xcc15, 0x03ff, 0xcc15, 0x21, 0 + .dw 0x0401, 0xcc15, 0x0401, 0xcc15, 0x21, 0 + .dw 0x0403, 0xcc15, 0x040f, 0xcc15, 0x21, 0 + .dw 0x0411, 0xcc15, 0x0411, 0xcc15, 0x21, 0 + .dw 0x0413, 0xcc15, 0x043f, 0xcc15, 0x21, 0 + .dw 0x0441, 0xcc15, 0x0441, 0xcc15, 0x21, 0 + .dw 0x0443, 0xcc15, 0x044f, 0xcc15, 0x21, 0 + .dw 0x0451, 0xcc15, 0x0451, 0xcc15, 0x21, 0 + .dw 0x0453, 0xcc15, 0x047f, 0xcc15, 0x21, 0 + .dw 0x0480, 0xcc15, 0x0480, 0xcc15, 0x22, 0 + .dw 0x0481, 0xcc15, 0x0481, 0xcc15, 0x21, 0 + .dw 0x0482, 0xcc15, 0x0482, 0xcc15, 0x22, 0 + .dw 0x0483, 0xcc15, 0x048f, 0xcc15, 0x21, 0 + .dw 0x0490, 0xcc15, 0x0490, 0xcc15, 0x22, 0 + .dw 0x0491, 0xcc15, 0x0491, 0xcc15, 0x21, 0 + .dw 0x0492, 0xcc15, 0x0492, 0xcc15, 0x22, 0 + .dw 0x0493, 0xcc15, 0x04bf, 0xcc15, 0x21, 0 + .dw 0x04c1, 0xcc15, 0x04c1, 0xcc15, 0x21, 0 + .dw 0x04c3, 0xcc15, 0x04cf, 0xcc15, 0x21, 0 + .dw 0x04d1, 0xcc15, 0x04d1, 0xcc15, 0x21, 0 + .dw 0x04d3, 0xcc15, 0x04ff, 0xcc15, 0x21, 0 + .dw 0x0501, 0xcc15, 0x0501, 0xcc15, 0x21, 0 + .dw 0x0503, 0xcc15, 0x050f, 0xcc15, 0x21, 0 + .dw 0x0511, 0xcc15, 0x0511, 0xcc15, 0x21, 0 + .dw 0x0513, 0xcc15, 0x053f, 0xcc15, 0x21, 0 + .dw 0x0541, 0xcc15, 0x0541, 0xcc15, 0x21, 0 + .dw 0x0543, 0xcc15, 0x054f, 0xcc15, 0x21, 0 + .dw 0x0551, 0xcc15, 0x0551, 0xcc15, 0x21, 0 + .dw 0x0553, 0xcc15, 0x057f, 0xcc15, 0x21, 0 + .dw 0x0581, 0xcc15, 0x0581, 0xcc15, 0x21, 0 + .dw 0x0583, 0xcc15, 0x058f, 0xcc15, 0x21, 0 + .dw 0x0591, 0xcc15, 0x0591, 0xcc15, 0x21, 0 + .dw 0x0593, 0xcc15, 0x05bf, 0xcc15, 0x21, 0 + .dw 0x05c1, 0xcc15, 0x05c1, 0xcc15, 0x21, 0 + .dw 0x05c3, 0xcc15, 0x05cf, 0xcc15, 0x21, 0 + .dw 0x05d1, 0xcc15, 0x05d1, 0xcc15, 0x21, 0 + .dw 0x05d3, 0xcc15, 0x05ff, 0xcc15, 0x21, 0 + .dw 0x0601, 0xcc15, 0x0601, 0xcc15, 0x21, 0 + .dw 0x0603, 0xcc15, 0x060f, 0xcc15, 0x21, 0 + .dw 0x0611, 0xcc15, 0x0611, 0xcc15, 0x21, 0 + .dw 0x0613, 0xcc15, 0x063f, 0xcc15, 0x21, 0 + .dw 0x0641, 0xcc15, 0x0641, 0xcc15, 0x21, 0 + .dw 0x0643, 0xcc15, 0x064f, 0xcc15, 0x21, 0 + .dw 0x0651, 0xcc15, 0x0651, 0xcc15, 0x21, 0 + .dw 0x0653, 0xcc15, 0x067f, 0xcc15, 0x21, 0 + .dw 0x0681, 0xcc15, 0x0681, 0xcc15, 0x21, 0 + .dw 0x0683, 0xcc15, 0x068f, 0xcc15, 0x21, 0 + .dw 0x0691, 0xcc15, 0x0691, 0xcc15, 0x21, 0 + .dw 0x0693, 0xcc15, 0x06bf, 0xcc15, 0x21, 0 + .dw 0x06c0, 0xcc15, 0x06c0, 0xcc15, 0x22, 0 + .dw 0x06c1, 0xcc15, 0x06c1, 0xcc15, 0x21, 0 + .dw 0x06c2, 0xcc15, 0x06c2, 0xcc15, 0x22, 0 + .dw 0x06c3, 0xcc15, 0x06cf, 0xcc15, 0x21, 0 + .dw 0x06d0, 0xcc15, 0x06d0, 0xcc15, 0x22, 0 + .dw 0x06d1, 0xcc15, 0x06d1, 0xcc15, 0x21, 0 + .dw 0x06d2, 0xcc15, 0x06d2, 0xcc15, 0x22, 0 + .dw 0x06d3, 0xcc15, 0x06ff, 0xcc15, 0x21, 0 + .dw 0x0701, 0xcc15, 0x0701, 0xcc15, 0x21, 0 + .dw 0x0703, 0xcc15, 0x070f, 0xcc15, 0x21, 0 + .dw 0x0711, 0xcc15, 0x0711, 0xcc15, 0x21, 0 + .dw 0x0713, 0xcc15, 0x073f, 0xcc15, 0x21, 0 + .dw 0x0741, 0xcc15, 0x0741, 0xcc15, 0x21, 0 + .dw 0x0743, 0xcc15, 0x074f, 0xcc15, 0x21, 0 + .dw 0x0751, 0xcc15, 0x0751, 0xcc15, 0x21, 0 + .dw 0x0753, 0xcc15, 0x077f, 0xcc15, 0x21, 0 + .dw 0x0781, 0xcc15, 0x0781, 0xcc15, 0x21, 0 + .dw 0x0783, 0xcc15, 0x078f, 0xcc15, 0x21, 0 + .dw 0x0791, 0xcc15, 0x0791, 0xcc15, 0x21, 0 + .dw 0x0793, 0xcc15, 0x07bf, 0xcc15, 0x21, 0 + .dw 0x07c1, 0xcc15, 0x07c1, 0xcc15, 0x21, 0 + .dw 0x07c3, 0xcc15, 0x07cf, 0xcc15, 0x21, 0 + .dw 0x07d1, 0xcc15, 0x07d1, 0xcc15, 0x21, 0 + .dw 0x07d3, 0xcc15, 0x07ff, 0xcc15, 0x21, 0 + .dw 0x0801, 0xcc15, 0x0801, 0xcc15, 0x21, 0 + .dw 0x0803, 0xcc15, 0x080f, 0xcc15, 0x21, 0 + .dw 0x0811, 0xcc15, 0x0811, 0xcc15, 0x21, 0 + .dw 0x0813, 0xcc15, 0x083f, 0xcc15, 0x21, 0 + .dw 0x0841, 0xcc15, 0x0841, 0xcc15, 0x21, 0 + .dw 0x0843, 0xcc15, 0x084f, 0xcc15, 0x21, 0 + .dw 0x0851, 0xcc15, 0x0851, 0xcc15, 0x21, 0 + .dw 0x0853, 0xcc15, 0x087f, 0xcc15, 0x21, 0 + .dw 0x0881, 0xcc15, 0x0881, 0xcc15, 0x21, 0 + .dw 0x0883, 0xcc15, 0x088f, 0xcc15, 0x21, 0 + .dw 0x0891, 0xcc15, 0x0891, 0xcc15, 0x21, 0 + .dw 0x0893, 0xcc15, 0x08bf, 0xcc15, 0x21, 0 + .dw 0x08c1, 0xcc15, 0x08c1, 0xcc15, 0x21, 0 + .dw 0x08c3, 0xcc15, 0x08cf, 0xcc15, 0x21, 0 + .dw 0x08d1, 0xcc15, 0x08d1, 0xcc15, 0x21, 0 + .dw 0x08d3, 0xcc15, 0x08ff, 0xcc15, 0x21, 0 + .dw 0x0900, 0xcc15, 0x0900, 0xcc15, 0x22, 0 + .dw 0x0901, 0xcc15, 0x0901, 0xcc15, 0x21, 0 + .dw 0x0902, 0xcc15, 0x0902, 0xcc15, 0x22, 0 + .dw 0x0903, 0xcc15, 0x090f, 0xcc15, 0x21, 0 + .dw 0x0910, 0xcc15, 0x0910, 0xcc15, 0x22, 0 + .dw 0x0911, 0xcc15, 0x0911, 0xcc15, 0x21, 0 + .dw 0x0912, 0xcc15, 0x0912, 0xcc15, 0x22, 0 + .dw 0x0913, 0xcc15, 0x093f, 0xcc15, 0x21, 0 + .dw 0x0941, 0xcc15, 0x0941, 0xcc15, 0x21, 0 + .dw 0x0943, 0xcc15, 0x094f, 0xcc15, 0x21, 0 + .dw 0x0951, 0xcc15, 0x0951, 0xcc15, 0x21, 0 + .dw 0x0953, 0xcc15, 0x097f, 0xcc15, 0x21, 0 + .dw 0x0981, 0xcc15, 0x0981, 0xcc15, 0x21, 0 + .dw 0x0983, 0xcc15, 0x098f, 0xcc15, 0x21, 0 + .dw 0x0991, 0xcc15, 0x0991, 0xcc15, 0x21, 0 + .dw 0x0993, 0xcc15, 0x09bf, 0xcc15, 0x21, 0 + .dw 0x09c1, 0xcc15, 0x09c1, 0xcc15, 0x21, 0 + .dw 0x09c3, 0xcc15, 0x09cf, 0xcc15, 0x21, 0 + .dw 0x09d1, 0xcc15, 0x09d1, 0xcc15, 0x21, 0 + .dw 0x09d3, 0xcc15, 0x09ff, 0xcc15, 0x21, 0 + .dw 0x0a01, 0xcc15, 0x0a01, 0xcc15, 0x21, 0 + .dw 0x0a03, 0xcc15, 0x0a0f, 0xcc15, 0x21, 0 + .dw 0x0a11, 0xcc15, 0x0a11, 0xcc15, 0x21, 0 + .dw 0x0a13, 0xcc15, 0x0a3f, 0xcc15, 0x21, 0 + .dw 0x0a41, 0xcc15, 0x0a41, 0xcc15, 0x21, 0 + .dw 0x0a43, 0xcc15, 0x0a4f, 0xcc15, 0x21, 0 + .dw 0x0a51, 0xcc15, 0x0a51, 0xcc15, 0x21, 0 + .dw 0x0a53, 0xcc15, 0x0a7f, 0xcc15, 0x21, 0 + .dw 0x0a81, 0xcc15, 0x0a81, 0xcc15, 0x21, 0 + .dw 0x0a83, 0xcc15, 0x0a8f, 0xcc15, 0x21, 0 + .dw 0x0a91, 0xcc15, 0x0a91, 0xcc15, 0x21, 0 + .dw 0x0a93, 0xcc15, 0x0abf, 0xcc15, 0x21, 0 + .dw 0x0ac1, 0xcc15, 0x0ac1, 0xcc15, 0x21, 0 + .dw 0x0ac3, 0xcc15, 0x0acf, 0xcc15, 0x21, 0 + .dw 0x0ad1, 0xcc15, 0x0ad1, 0xcc15, 0x21, 0 + .dw 0x0ad3, 0xcc15, 0x0aff, 0xcc15, 0x21, 0 + .dw 0x0b01, 0xcc15, 0x0b01, 0xcc15, 0x21, 0 + .dw 0x0b03, 0xcc15, 0x0b0f, 0xcc15, 0x21, 0 + .dw 0x0b11, 0xcc15, 0x0b11, 0xcc15, 0x21, 0 + .dw 0x0b13, 0xcc15, 0x0b3f, 0xcc15, 0x21, 0 + .dw 0x0b40, 0xcc15, 0x0b40, 0xcc15, 0x22, 0 + .dw 0x0b41, 0xcc15, 0x0b41, 0xcc15, 0x21, 0 + .dw 0x0b42, 0xcc15, 0x0b42, 0xcc15, 0x22, 0 + .dw 0x0b43, 0xcc15, 0x0b4f, 0xcc15, 0x21, 0 + .dw 0x0b50, 0xcc15, 0x0b50, 0xcc15, 0x22, 0 + .dw 0x0b51, 0xcc15, 0x0b51, 0xcc15, 0x21, 0 + .dw 0x0b52, 0xcc15, 0x0b52, 0xcc15, 0x22, 0 + .dw 0x0b53, 0xcc15, 0x0b7f, 0xcc15, 0x21, 0 + .dw 0x0b81, 0xcc15, 0x0b81, 0xcc15, 0x21, 0 + .dw 0x0b83, 0xcc15, 0x0b8f, 0xcc15, 0x21, 0 + .dw 0x0b91, 0xcc15, 0x0b91, 0xcc15, 0x21, 0 + .dw 0x0b93, 0xcc15, 0x0bbf, 0xcc15, 0x21, 0 + .dw 0x0bc1, 0xcc15, 0x0bc1, 0xcc15, 0x21, 0 + .dw 0x0bc3, 0xcc15, 0x0bcf, 0xcc15, 0x21, 0 + .dw 0x0bd1, 0xcc15, 0x0bd1, 0xcc15, 0x21, 0 + .dw 0x0bd3, 0xcc15, 0x0bff, 0xcc15, 0x21, 0 + .dw 0x0c01, 0xcc15, 0x0c01, 0xcc15, 0x21, 0 + .dw 0x0c03, 0xcc15, 0x0c0f, 0xcc15, 0x21, 0 + .dw 0x0c11, 0xcc15, 0x0c11, 0xcc15, 0x21, 0 + .dw 0x0c13, 0xcc15, 0x0c3f, 0xcc15, 0x21, 0 + .dw 0x0c41, 0xcc15, 0x0c41, 0xcc15, 0x21, 0 + .dw 0x0c43, 0xcc15, 0x0c4f, 0xcc15, 0x21, 0 + .dw 0x0c51, 0xcc15, 0x0c51, 0xcc15, 0x21, 0 + .dw 0x0c53, 0xcc15, 0x0c7f, 0xcc15, 0x21, 0 + .dw 0x0c81, 0xcc15, 0x0c81, 0xcc15, 0x21, 0 + .dw 0x0c83, 0xcc15, 0x0c8f, 0xcc15, 0x21, 0 + .dw 0x0c91, 0xcc15, 0x0c91, 0xcc15, 0x21, 0 + .dw 0x0c93, 0xcc15, 0x0cbf, 0xcc15, 0x21, 0 + .dw 0x0cc1, 0xcc15, 0x0cc1, 0xcc15, 0x21, 0 + .dw 0x0cc3, 0xcc15, 0x0ccf, 0xcc15, 0x21, 0 + .dw 0x0cd1, 0xcc15, 0x0cd1, 0xcc15, 0x21, 0 + .dw 0x0cd3, 0xcc15, 0x0cff, 0xcc15, 0x21, 0 + .dw 0x0d01, 0xcc15, 0x0d01, 0xcc15, 0x21, 0 + .dw 0x0d03, 0xcc15, 0x0d0f, 0xcc15, 0x21, 0 + .dw 0x0d11, 0xcc15, 0x0d11, 0xcc15, 0x21, 0 + .dw 0x0d13, 0xcc15, 0x0d3f, 0xcc15, 0x21, 0 + .dw 0x0d41, 0xcc15, 0x0d41, 0xcc15, 0x21, 0 + .dw 0x0d43, 0xcc15, 0x0d4f, 0xcc15, 0x21, 0 + .dw 0x0d51, 0xcc15, 0x0d51, 0xcc15, 0x21, 0 + .dw 0x0d53, 0xcc15, 0x0d7f, 0xcc15, 0x21, 0 + .dw 0x0d80, 0xcc15, 0x0d80, 0xcc15, 0x22, 0 + .dw 0x0d81, 0xcc15, 0x0d81, 0xcc15, 0x21, 0 + .dw 0x0d82, 0xcc15, 0x0d82, 0xcc15, 0x22, 0 + .dw 0x0d83, 0xcc15, 0x0d8f, 0xcc15, 0x21, 0 + .dw 0x0d90, 0xcc15, 0x0d90, 0xcc15, 0x22, 0 + .dw 0x0d91, 0xcc15, 0x0d91, 0xcc15, 0x21, 0 + .dw 0x0d92, 0xcc15, 0x0d92, 0xcc15, 0x22, 0 + .dw 0x0d93, 0xcc15, 0x0dbf, 0xcc15, 0x21, 0 + .dw 0x0dc1, 0xcc15, 0x0dc1, 0xcc15, 0x21, 0 + .dw 0x0dc3, 0xcc15, 0x0dcf, 0xcc15, 0x21, 0 + .dw 0x0dd1, 0xcc15, 0x0dd1, 0xcc15, 0x21, 0 + .dw 0x0dd3, 0xcc15, 0x0dff, 0xcc15, 0x21, 0 + .dw 0x0e01, 0xcc15, 0x0e01, 0xcc15, 0x21, 0 + .dw 0x0e03, 0xcc15, 0x0e0f, 0xcc15, 0x21, 0 + .dw 0x0e11, 0xcc15, 0x0e11, 0xcc15, 0x21, 0 + .dw 0x0e13, 0xcc15, 0x0e3f, 0xcc15, 0x21, 0 + .dw 0x0e41, 0xcc15, 0x0e41, 0xcc15, 0x21, 0 + .dw 0x0e43, 0xcc15, 0x0e4f, 0xcc15, 0x21, 0 + .dw 0x0e51, 0xcc15, 0x0e51, 0xcc15, 0x21, 0 + .dw 0x0e53, 0xcc15, 0x0e7f, 0xcc15, 0x21, 0 + .dw 0x0e81, 0xcc15, 0x0e81, 0xcc15, 0x21, 0 + .dw 0x0e83, 0xcc15, 0x0e8f, 0xcc15, 0x21, 0 + .dw 0x0e91, 0xcc15, 0x0e91, 0xcc15, 0x21, 0 + .dw 0x0e93, 0xcc15, 0x0ebf, 0xcc15, 0x21, 0 + .dw 0x0ec1, 0xcc15, 0x0ec1, 0xcc15, 0x21, 0 + .dw 0x0ec3, 0xcc15, 0x0ecf, 0xcc15, 0x21, 0 + .dw 0x0ed1, 0xcc15, 0x0ed1, 0xcc15, 0x21, 0 + .dw 0x0ed3, 0xcc15, 0x0eff, 0xcc15, 0x21, 0 + .dw 0x0f01, 0xcc15, 0x0f01, 0xcc15, 0x21, 0 + .dw 0x0f03, 0xcc15, 0x0f0f, 0xcc15, 0x21, 0 + .dw 0x0f11, 0xcc15, 0x0f11, 0xcc15, 0x21, 0 + .dw 0x0f13, 0xcc15, 0x0f3f, 0xcc15, 0x21, 0 + .dw 0x0f41, 0xcc15, 0x0f41, 0xcc15, 0x21, 0 + .dw 0x0f43, 0xcc15, 0x0f4f, 0xcc15, 0x21, 0 + .dw 0x0f51, 0xcc15, 0x0f51, 0xcc15, 0x21, 0 + .dw 0x0f53, 0xcc15, 0x0f7f, 0xcc15, 0x21, 0 + .dw 0x0f81, 0xcc15, 0x0f81, 0xcc15, 0x21, 0 + .dw 0x0f83, 0xcc15, 0x0f8f, 0xcc15, 0x21, 0 + .dw 0x0f91, 0xcc15, 0x0f91, 0xcc15, 0x21, 0 + .dw 0x0f93, 0xcc15, 0x0fbf, 0xcc15, 0x21, 0 + .dw 0x0fc0, 0xcc15, 0x0fc0, 0xcc15, 0x22, 0 + .dw 0x0fc1, 0xcc15, 0x0fc1, 0xcc15, 0x21, 0 + .dw 0x0fc2, 0xcc15, 0x0fc2, 0xcc15, 0x22, 0 + .dw 0x0fc3, 0xcc15, 0x0fcf, 0xcc15, 0x21, 0 + .dw 0x0fd0, 0xcc15, 0x0fd0, 0xcc15, 0x22, 0 + .dw 0x0fd1, 0xcc15, 0x0fd1, 0xcc15, 0x21, 0 + .dw 0x0fd2, 0xcc15, 0x0fd2, 0xcc15, 0x22, 0 + .dw 0x0fd3, 0xcc15, 0x1fff, 0xcc15, 0x21, 0 + .dw 0x2000, 0xcc15, 0x2000, 0xcc15, 0x22, 0 + .dw 0x2001, 0xcc15, 0x2001, 0xcc15, 0x21, 0 + .dw 0x2002, 0xcc15, 0x2002, 0xcc15, 0x22, 0 + .dw 0x2003, 0xcc15, 0x200f, 0xcc15, 0x21, 0 + .dw 0x2010, 0xcc15, 0x2010, 0xcc15, 0x22, 0 + .dw 0x2011, 0xcc15, 0x2011, 0xcc15, 0x21, 0 + .dw 0x2012, 0xcc15, 0x2012, 0xcc15, 0x22, 0 + .dw 0x2013, 0xcc15, 0x203f, 0xcc15, 0x21, 0 + .dw 0x2041, 0xcc15, 0x2041, 0xcc15, 0x21, 0 + .dw 0x2043, 0xcc15, 0x204f, 0xcc15, 0x21, 0 + .dw 0x2051, 0xcc15, 0x2051, 0xcc15, 0x21, 0 + .dw 0x2053, 0xcc15, 0x207f, 0xcc15, 0x21, 0 + .dw 0x2081, 0xcc15, 0x2081, 0xcc15, 0x21, 0 + .dw 0x2083, 0xcc15, 0x208f, 0xcc15, 0x21, 0 + .dw 0x2091, 0xcc15, 0x2091, 0xcc15, 0x21, 0 + .dw 0x2093, 0xcc15, 0x20bf, 0xcc15, 0x21, 0 + .dw 0x20c1, 0xcc15, 0x20c1, 0xcc15, 0x21, 0 + .dw 0x20c3, 0xcc15, 0x20cf, 0xcc15, 0x21, 0 + .dw 0x20d1, 0xcc15, 0x20d1, 0xcc15, 0x21, 0 + .dw 0x20d3, 0xcc15, 0x20ff, 0xcc15, 0x21, 0 + .dw 0x2101, 0xcc15, 0x2101, 0xcc15, 0x21, 0 + .dw 0x2103, 0xcc15, 0x210f, 0xcc15, 0x21, 0 + .dw 0x2111, 0xcc15, 0x2111, 0xcc15, 0x21, 0 + .dw 0x2113, 0xcc15, 0x213f, 0xcc15, 0x21, 0 + .dw 0x2141, 0xcc15, 0x2141, 0xcc15, 0x21, 0 + .dw 0x2143, 0xcc15, 0x214f, 0xcc15, 0x21, 0 + .dw 0x2151, 0xcc15, 0x2151, 0xcc15, 0x21, 0 + .dw 0x2153, 0xcc15, 0x217f, 0xcc15, 0x21, 0 + .dw 0x2181, 0xcc15, 0x2181, 0xcc15, 0x21, 0 + .dw 0x2183, 0xcc15, 0x218f, 0xcc15, 0x21, 0 + .dw 0x2191, 0xcc15, 0x2191, 0xcc15, 0x21, 0 + .dw 0x2193, 0xcc15, 0x21bf, 0xcc15, 0x21, 0 + .dw 0x21c1, 0xcc15, 0x21c1, 0xcc15, 0x21, 0 + .dw 0x21c3, 0xcc15, 0x21cf, 0xcc15, 0x21, 0 + .dw 0x21d1, 0xcc15, 0x21d1, 0xcc15, 0x21, 0 + .dw 0x21d3, 0xcc15, 0x21ff, 0xcc15, 0x21, 0 + .dw 0x2201, 0xcc15, 0x2201, 0xcc15, 0x21, 0 + .dw 0x2203, 0xcc15, 0x220f, 0xcc15, 0x21, 0 + .dw 0x2211, 0xcc15, 0x2211, 0xcc15, 0x21, 0 + .dw 0x2213, 0xcc15, 0x223f, 0xcc15, 0x21, 0 + .dw 0x2240, 0xcc15, 0x2240, 0xcc15, 0x22, 0 + .dw 0x2241, 0xcc15, 0x2241, 0xcc15, 0x21, 0 + .dw 0x2242, 0xcc15, 0x2242, 0xcc15, 0x22, 0 + .dw 0x2243, 0xcc15, 0x224f, 0xcc15, 0x21, 0 + .dw 0x2250, 0xcc15, 0x2250, 0xcc15, 0x22, 0 + .dw 0x2251, 0xcc15, 0x2251, 0xcc15, 0x21, 0 + .dw 0x2252, 0xcc15, 0x2252, 0xcc15, 0x22, 0 + .dw 0x2253, 0xcc15, 0x227f, 0xcc15, 0x21, 0 + .dw 0x2281, 0xcc15, 0x2281, 0xcc15, 0x21, 0 + .dw 0x2283, 0xcc15, 0x228f, 0xcc15, 0x21, 0 + .dw 0x2291, 0xcc15, 0x2291, 0xcc15, 0x21, 0 + .dw 0x2293, 0xcc15, 0x22bf, 0xcc15, 0x21, 0 + .dw 0x22c1, 0xcc15, 0x22c1, 0xcc15, 0x21, 0 + .dw 0x22c3, 0xcc15, 0x22cf, 0xcc15, 0x21, 0 + .dw 0x22d1, 0xcc15, 0x22d1, 0xcc15, 0x21, 0 + .dw 0x22d3, 0xcc15, 0x22ff, 0xcc15, 0x21, 0 + .dw 0x2301, 0xcc15, 0x2301, 0xcc15, 0x21, 0 + .dw 0x2303, 0xcc15, 0x230f, 0xcc15, 0x21, 0 + .dw 0x2311, 0xcc15, 0x2311, 0xcc15, 0x21, 0 + .dw 0x2313, 0xcc15, 0x233f, 0xcc15, 0x21, 0 + .dw 0x2341, 0xcc15, 0x2341, 0xcc15, 0x21, 0 + .dw 0x2343, 0xcc15, 0x234f, 0xcc15, 0x21, 0 + .dw 0x2351, 0xcc15, 0x2351, 0xcc15, 0x21, 0 + .dw 0x2353, 0xcc15, 0x237f, 0xcc15, 0x21, 0 + .dw 0x2381, 0xcc15, 0x2381, 0xcc15, 0x21, 0 + .dw 0x2383, 0xcc15, 0x238f, 0xcc15, 0x21, 0 + .dw 0x2391, 0xcc15, 0x2391, 0xcc15, 0x21, 0 + .dw 0x2393, 0xcc15, 0x23bf, 0xcc15, 0x21, 0 + .dw 0x23c1, 0xcc15, 0x23c1, 0xcc15, 0x21, 0 + .dw 0x23c3, 0xcc15, 0x23cf, 0xcc15, 0x21, 0 + .dw 0x23d1, 0xcc15, 0x23d1, 0xcc15, 0x21, 0 + .dw 0x23d3, 0xcc15, 0x23ff, 0xcc15, 0x21, 0 + .dw 0x2401, 0xcc15, 0x2401, 0xcc15, 0x21, 0 + .dw 0x2403, 0xcc15, 0x240f, 0xcc15, 0x21, 0 + .dw 0x2411, 0xcc15, 0x2411, 0xcc15, 0x21, 0 + .dw 0x2413, 0xcc15, 0x243f, 0xcc15, 0x21, 0 + .dw 0x2441, 0xcc15, 0x2441, 0xcc15, 0x21, 0 + .dw 0x2443, 0xcc15, 0x244f, 0xcc15, 0x21, 0 + .dw 0x2451, 0xcc15, 0x2451, 0xcc15, 0x21, 0 + .dw 0x2453, 0xcc15, 0x247f, 0xcc15, 0x21, 0 + .dw 0x2480, 0xcc15, 0x2480, 0xcc15, 0x22, 0 + .dw 0x2481, 0xcc15, 0x2481, 0xcc15, 0x21, 0 + .dw 0x2482, 0xcc15, 0x2482, 0xcc15, 0x22, 0 + .dw 0x2483, 0xcc15, 0x248f, 0xcc15, 0x21, 0 + .dw 0x2490, 0xcc15, 0x2490, 0xcc15, 0x22, 0 + .dw 0x2491, 0xcc15, 0x2491, 0xcc15, 0x21, 0 + .dw 0x2492, 0xcc15, 0x2492, 0xcc15, 0x22, 0 + .dw 0x2493, 0xcc15, 0x24bf, 0xcc15, 0x21, 0 + .dw 0x24c1, 0xcc15, 0x24c1, 0xcc15, 0x21, 0 + .dw 0x24c3, 0xcc15, 0x24cf, 0xcc15, 0x21, 0 + .dw 0x24d1, 0xcc15, 0x24d1, 0xcc15, 0x21, 0 + .dw 0x24d3, 0xcc15, 0x24ff, 0xcc15, 0x21, 0 + .dw 0x2501, 0xcc15, 0x2501, 0xcc15, 0x21, 0 + .dw 0x2503, 0xcc15, 0x250f, 0xcc15, 0x21, 0 + .dw 0x2511, 0xcc15, 0x2511, 0xcc15, 0x21, 0 + .dw 0x2513, 0xcc15, 0x253f, 0xcc15, 0x21, 0 + .dw 0x2541, 0xcc15, 0x2541, 0xcc15, 0x21, 0 + .dw 0x2543, 0xcc15, 0x254f, 0xcc15, 0x21, 0 + .dw 0x2551, 0xcc15, 0x2551, 0xcc15, 0x21, 0 + .dw 0x2553, 0xcc15, 0x257f, 0xcc15, 0x21, 0 + .dw 0x2581, 0xcc15, 0x2581, 0xcc15, 0x21, 0 + .dw 0x2583, 0xcc15, 0x258f, 0xcc15, 0x21, 0 + .dw 0x2591, 0xcc15, 0x2591, 0xcc15, 0x21, 0 + .dw 0x2593, 0xcc15, 0x25bf, 0xcc15, 0x21, 0 + .dw 0x25c1, 0xcc15, 0x25c1, 0xcc15, 0x21, 0 + .dw 0x25c3, 0xcc15, 0x25cf, 0xcc15, 0x21, 0 + .dw 0x25d1, 0xcc15, 0x25d1, 0xcc15, 0x21, 0 + .dw 0x25d3, 0xcc15, 0x25ff, 0xcc15, 0x21, 0 + .dw 0x2601, 0xcc15, 0x2601, 0xcc15, 0x21, 0 + .dw 0x2603, 0xcc15, 0x260f, 0xcc15, 0x21, 0 + .dw 0x2611, 0xcc15, 0x2611, 0xcc15, 0x21, 0 + .dw 0x2613, 0xcc15, 0x263f, 0xcc15, 0x21, 0 + .dw 0x2641, 0xcc15, 0x2641, 0xcc15, 0x21, 0 + .dw 0x2643, 0xcc15, 0x264f, 0xcc15, 0x21, 0 + .dw 0x2651, 0xcc15, 0x2651, 0xcc15, 0x21, 0 + .dw 0x2653, 0xcc15, 0x267f, 0xcc15, 0x21, 0 + .dw 0x2681, 0xcc15, 0x2681, 0xcc15, 0x21, 0 + .dw 0x2683, 0xcc15, 0x268f, 0xcc15, 0x21, 0 + .dw 0x2691, 0xcc15, 0x2691, 0xcc15, 0x21, 0 + .dw 0x2693, 0xcc15, 0x26bf, 0xcc15, 0x21, 0 + .dw 0x26c0, 0xcc15, 0x26c0, 0xcc15, 0x22, 0 + .dw 0x26c1, 0xcc15, 0x26c1, 0xcc15, 0x21, 0 + .dw 0x26c2, 0xcc15, 0x26c2, 0xcc15, 0x22, 0 + .dw 0x26c3, 0xcc15, 0x26cf, 0xcc15, 0x21, 0 + .dw 0x26d0, 0xcc15, 0x26d0, 0xcc15, 0x22, 0 + .dw 0x26d1, 0xcc15, 0x26d1, 0xcc15, 0x21, 0 + .dw 0x26d2, 0xcc15, 0x26d2, 0xcc15, 0x22, 0 + .dw 0x26d3, 0xcc15, 0x26ff, 0xcc15, 0x21, 0 + .dw 0x2701, 0xcc15, 0x2701, 0xcc15, 0x21, 0 + .dw 0x2703, 0xcc15, 0x270f, 0xcc15, 0x21, 0 + .dw 0x2711, 0xcc15, 0x2711, 0xcc15, 0x21, 0 + .dw 0x2713, 0xcc15, 0x273f, 0xcc15, 0x21, 0 + .dw 0x2741, 0xcc15, 0x2741, 0xcc15, 0x21, 0 + .dw 0x2743, 0xcc15, 0x274f, 0xcc15, 0x21, 0 + .dw 0x2751, 0xcc15, 0x2751, 0xcc15, 0x21, 0 + .dw 0x2753, 0xcc15, 0x277f, 0xcc15, 0x21, 0 + .dw 0x2781, 0xcc15, 0x2781, 0xcc15, 0x21, 0 + .dw 0x2783, 0xcc15, 0x278f, 0xcc15, 0x21, 0 + .dw 0x2791, 0xcc15, 0x2791, 0xcc15, 0x21, 0 + .dw 0x2793, 0xcc15, 0x27bf, 0xcc15, 0x21, 0 + .dw 0x27c1, 0xcc15, 0x27c1, 0xcc15, 0x21, 0 + .dw 0x27c3, 0xcc15, 0x27cf, 0xcc15, 0x21, 0 + .dw 0x27d1, 0xcc15, 0x27d1, 0xcc15, 0x21, 0 + .dw 0x27d3, 0xcc15, 0x27ff, 0xcc15, 0x21, 0 + .dw 0x2801, 0xcc15, 0x2801, 0xcc15, 0x21, 0 + .dw 0x2803, 0xcc15, 0x280f, 0xcc15, 0x21, 0 + .dw 0x2811, 0xcc15, 0x2811, 0xcc15, 0x21, 0 + .dw 0x2813, 0xcc15, 0x283f, 0xcc15, 0x21, 0 + .dw 0x2841, 0xcc15, 0x2841, 0xcc15, 0x21, 0 + .dw 0x2843, 0xcc15, 0x284f, 0xcc15, 0x21, 0 + .dw 0x2851, 0xcc15, 0x2851, 0xcc15, 0x21, 0 + .dw 0x2853, 0xcc15, 0x287f, 0xcc15, 0x21, 0 + .dw 0x2881, 0xcc15, 0x2881, 0xcc15, 0x21, 0 + .dw 0x2883, 0xcc15, 0x288f, 0xcc15, 0x21, 0 + .dw 0x2891, 0xcc15, 0x2891, 0xcc15, 0x21, 0 + .dw 0x2893, 0xcc15, 0x28bf, 0xcc15, 0x21, 0 + .dw 0x28c1, 0xcc15, 0x28c1, 0xcc15, 0x21, 0 + .dw 0x28c3, 0xcc15, 0x28cf, 0xcc15, 0x21, 0 + .dw 0x28d1, 0xcc15, 0x28d1, 0xcc15, 0x21, 0 + .dw 0x28d3, 0xcc15, 0x28ff, 0xcc15, 0x21, 0 + .dw 0x2900, 0xcc15, 0x2900, 0xcc15, 0x22, 0 + .dw 0x2901, 0xcc15, 0x2901, 0xcc15, 0x21, 0 + .dw 0x2902, 0xcc15, 0x2902, 0xcc15, 0x22, 0 + .dw 0x2903, 0xcc15, 0x290f, 0xcc15, 0x21, 0 + .dw 0x2910, 0xcc15, 0x2910, 0xcc15, 0x22, 0 + .dw 0x2911, 0xcc15, 0x2911, 0xcc15, 0x21, 0 + .dw 0x2912, 0xcc15, 0x2912, 0xcc15, 0x22, 0 + .dw 0x2913, 0xcc15, 0x293f, 0xcc15, 0x21, 0 + .dw 0x2941, 0xcc15, 0x2941, 0xcc15, 0x21, 0 + .dw 0x2943, 0xcc15, 0x294f, 0xcc15, 0x21, 0 + .dw 0x2951, 0xcc15, 0x2951, 0xcc15, 0x21, 0 + .dw 0x2953, 0xcc15, 0x297f, 0xcc15, 0x21, 0 + .dw 0x2981, 0xcc15, 0x2981, 0xcc15, 0x21, 0 + .dw 0x2983, 0xcc15, 0x298f, 0xcc15, 0x21, 0 + .dw 0x2991, 0xcc15, 0x2991, 0xcc15, 0x21, 0 + .dw 0x2993, 0xcc15, 0x29bf, 0xcc15, 0x21, 0 + .dw 0x29c1, 0xcc15, 0x29c1, 0xcc15, 0x21, 0 + .dw 0x29c3, 0xcc15, 0x29cf, 0xcc15, 0x21, 0 + .dw 0x29d1, 0xcc15, 0x29d1, 0xcc15, 0x21, 0 + .dw 0x29d3, 0xcc15, 0x29ff, 0xcc15, 0x21, 0 + .dw 0x2a01, 0xcc15, 0x2a01, 0xcc15, 0x21, 0 + .dw 0x2a03, 0xcc15, 0x2a0f, 0xcc15, 0x21, 0 + .dw 0x2a11, 0xcc15, 0x2a11, 0xcc15, 0x21, 0 + .dw 0x2a13, 0xcc15, 0x2a3f, 0xcc15, 0x21, 0 + .dw 0x2a41, 0xcc15, 0x2a41, 0xcc15, 0x21, 0 + .dw 0x2a43, 0xcc15, 0x2a4f, 0xcc15, 0x21, 0 + .dw 0x2a51, 0xcc15, 0x2a51, 0xcc15, 0x21, 0 + .dw 0x2a53, 0xcc15, 0x2a7f, 0xcc15, 0x21, 0 + .dw 0x2a81, 0xcc15, 0x2a81, 0xcc15, 0x21, 0 + .dw 0x2a83, 0xcc15, 0x2a8f, 0xcc15, 0x21, 0 + .dw 0x2a91, 0xcc15, 0x2a91, 0xcc15, 0x21, 0 + .dw 0x2a93, 0xcc15, 0x2abf, 0xcc15, 0x21, 0 + .dw 0x2ac1, 0xcc15, 0x2ac1, 0xcc15, 0x21, 0 + .dw 0x2ac3, 0xcc15, 0x2acf, 0xcc15, 0x21, 0 + .dw 0x2ad1, 0xcc15, 0x2ad1, 0xcc15, 0x21, 0 + .dw 0x2ad3, 0xcc15, 0x2aff, 0xcc15, 0x21, 0 + .dw 0x2b01, 0xcc15, 0x2b01, 0xcc15, 0x21, 0 + .dw 0x2b03, 0xcc15, 0x2b0f, 0xcc15, 0x21, 0 + .dw 0x2b11, 0xcc15, 0x2b11, 0xcc15, 0x21, 0 + .dw 0x2b13, 0xcc15, 0x2b3f, 0xcc15, 0x21, 0 + .dw 0x2b40, 0xcc15, 0x2b40, 0xcc15, 0x22, 0 + .dw 0x2b41, 0xcc15, 0x2b41, 0xcc15, 0x21, 0 + .dw 0x2b42, 0xcc15, 0x2b42, 0xcc15, 0x22, 0 + .dw 0x2b43, 0xcc15, 0x2b4f, 0xcc15, 0x21, 0 + .dw 0x2b50, 0xcc15, 0x2b50, 0xcc15, 0x22, 0 + .dw 0x2b51, 0xcc15, 0x2b51, 0xcc15, 0x21, 0 + .dw 0x2b52, 0xcc15, 0x2b52, 0xcc15, 0x22, 0 + .dw 0x2b53, 0xcc15, 0x2b7f, 0xcc15, 0x21, 0 + .dw 0x2b81, 0xcc15, 0x2b81, 0xcc15, 0x21, 0 + .dw 0x2b83, 0xcc15, 0x2b8f, 0xcc15, 0x21, 0 + .dw 0x2b91, 0xcc15, 0x2b91, 0xcc15, 0x21, 0 + .dw 0x2b93, 0xcc15, 0x2bbf, 0xcc15, 0x21, 0 + .dw 0x2bc1, 0xcc15, 0x2bc1, 0xcc15, 0x21, 0 + .dw 0x2bc3, 0xcc15, 0x2bcf, 0xcc15, 0x21, 0 + .dw 0x2bd1, 0xcc15, 0x2bd1, 0xcc15, 0x21, 0 + .dw 0x2bd3, 0xcc15, 0x2bff, 0xcc15, 0x21, 0 + .dw 0x2c01, 0xcc15, 0x2c01, 0xcc15, 0x21, 0 + .dw 0x2c03, 0xcc15, 0x2c0f, 0xcc15, 0x21, 0 + .dw 0x2c11, 0xcc15, 0x2c11, 0xcc15, 0x21, 0 + .dw 0x2c13, 0xcc15, 0x2c3f, 0xcc15, 0x21, 0 + .dw 0x2c41, 0xcc15, 0x2c41, 0xcc15, 0x21, 0 + .dw 0x2c43, 0xcc15, 0x2c4f, 0xcc15, 0x21, 0 + .dw 0x2c51, 0xcc15, 0x2c51, 0xcc15, 0x21, 0 + .dw 0x2c53, 0xcc15, 0x2c7f, 0xcc15, 0x21, 0 + .dw 0x2c81, 0xcc15, 0x2c81, 0xcc15, 0x21, 0 + .dw 0x2c83, 0xcc15, 0x2c8f, 0xcc15, 0x21, 0 + .dw 0x2c91, 0xcc15, 0x2c91, 0xcc15, 0x21, 0 + .dw 0x2c93, 0xcc15, 0x2cbf, 0xcc15, 0x21, 0 + .dw 0x2cc1, 0xcc15, 0x2cc1, 0xcc15, 0x21, 0 + .dw 0x2cc3, 0xcc15, 0x2ccf, 0xcc15, 0x21, 0 + .dw 0x2cd1, 0xcc15, 0x2cd1, 0xcc15, 0x21, 0 + .dw 0x2cd3, 0xcc15, 0x2cff, 0xcc15, 0x21, 0 + .dw 0x2d01, 0xcc15, 0x2d01, 0xcc15, 0x21, 0 + .dw 0x2d03, 0xcc15, 0x2d0f, 0xcc15, 0x21, 0 + .dw 0x2d11, 0xcc15, 0x2d11, 0xcc15, 0x21, 0 + .dw 0x2d13, 0xcc15, 0x2d3f, 0xcc15, 0x21, 0 + .dw 0x2d41, 0xcc15, 0x2d41, 0xcc15, 0x21, 0 + .dw 0x2d43, 0xcc15, 0x2d4f, 0xcc15, 0x21, 0 + .dw 0x2d51, 0xcc15, 0x2d51, 0xcc15, 0x21, 0 + .dw 0x2d53, 0xcc15, 0x2d7f, 0xcc15, 0x21, 0 + .dw 0x2d80, 0xcc15, 0x2d80, 0xcc15, 0x22, 0 + .dw 0x2d81, 0xcc15, 0x2d81, 0xcc15, 0x21, 0 + .dw 0x2d82, 0xcc15, 0x2d82, 0xcc15, 0x22, 0 + .dw 0x2d83, 0xcc15, 0x2d8f, 0xcc15, 0x21, 0 + .dw 0x2d90, 0xcc15, 0x2d90, 0xcc15, 0x22, 0 + .dw 0x2d91, 0xcc15, 0x2d91, 0xcc15, 0x21, 0 + .dw 0x2d92, 0xcc15, 0x2d92, 0xcc15, 0x22, 0 + .dw 0x2d93, 0xcc15, 0x2dbf, 0xcc15, 0x21, 0 + .dw 0x2dc1, 0xcc15, 0x2dc1, 0xcc15, 0x21, 0 + .dw 0x2dc3, 0xcc15, 0x2dcf, 0xcc15, 0x21, 0 + .dw 0x2dd1, 0xcc15, 0x2dd1, 0xcc15, 0x21, 0 + .dw 0x2dd3, 0xcc15, 0x2dff, 0xcc15, 0x21, 0 + .dw 0x2e01, 0xcc15, 0x2e01, 0xcc15, 0x21, 0 + .dw 0x2e03, 0xcc15, 0x2e0f, 0xcc15, 0x21, 0 + .dw 0x2e11, 0xcc15, 0x2e11, 0xcc15, 0x21, 0 + .dw 0x2e13, 0xcc15, 0x2e3f, 0xcc15, 0x21, 0 + .dw 0x2e41, 0xcc15, 0x2e41, 0xcc15, 0x21, 0 + .dw 0x2e43, 0xcc15, 0x2e4f, 0xcc15, 0x21, 0 + .dw 0x2e51, 0xcc15, 0x2e51, 0xcc15, 0x21, 0 + .dw 0x2e53, 0xcc15, 0x2e7f, 0xcc15, 0x21, 0 + .dw 0x2e81, 0xcc15, 0x2e81, 0xcc15, 0x21, 0 + .dw 0x2e83, 0xcc15, 0x2e8f, 0xcc15, 0x21, 0 + .dw 0x2e91, 0xcc15, 0x2e91, 0xcc15, 0x21, 0 + .dw 0x2e93, 0xcc15, 0x2ebf, 0xcc15, 0x21, 0 + .dw 0x2ec1, 0xcc15, 0x2ec1, 0xcc15, 0x21, 0 + .dw 0x2ec3, 0xcc15, 0x2ecf, 0xcc15, 0x21, 0 + .dw 0x2ed1, 0xcc15, 0x2ed1, 0xcc15, 0x21, 0 + .dw 0x2ed3, 0xcc15, 0x2eff, 0xcc15, 0x21, 0 + .dw 0x2f01, 0xcc15, 0x2f01, 0xcc15, 0x21, 0 + .dw 0x2f03, 0xcc15, 0x2f0f, 0xcc15, 0x21, 0 + .dw 0x2f11, 0xcc15, 0x2f11, 0xcc15, 0x21, 0 + .dw 0x2f13, 0xcc15, 0x2f3f, 0xcc15, 0x21, 0 + .dw 0x2f41, 0xcc15, 0x2f41, 0xcc15, 0x21, 0 + .dw 0x2f43, 0xcc15, 0x2f4f, 0xcc15, 0x21, 0 + .dw 0x2f51, 0xcc15, 0x2f51, 0xcc15, 0x21, 0 + .dw 0x2f53, 0xcc15, 0x2f7f, 0xcc15, 0x21, 0 + .dw 0x2f81, 0xcc15, 0x2f81, 0xcc15, 0x21, 0 + .dw 0x2f83, 0xcc15, 0x2f8f, 0xcc15, 0x21, 0 + .dw 0x2f91, 0xcc15, 0x2f91, 0xcc15, 0x21, 0 + .dw 0x2f93, 0xcc15, 0x2fbf, 0xcc15, 0x21, 0 + .dw 0x2fc0, 0xcc15, 0x2fc0, 0xcc15, 0x22, 0 + .dw 0x2fc1, 0xcc15, 0x2fc1, 0xcc15, 0x21, 0 + .dw 0x2fc2, 0xcc15, 0x2fc2, 0xcc15, 0x22, 0 + .dw 0x2fc3, 0xcc15, 0x2fcf, 0xcc15, 0x21, 0 + .dw 0x2fd0, 0xcc15, 0x2fd0, 0xcc15, 0x22, 0 + .dw 0x2fd1, 0xcc15, 0x2fd1, 0xcc15, 0x21, 0 + .dw 0x2fd2, 0xcc15, 0x2fd2, 0xcc15, 0x22, 0 + .dw 0x2fd3, 0xcc15, 0x3fff, 0xcc15, 0x21, 0 + .dw 0x4000, 0xcc15, 0x4000, 0xcc15, 0x22, 0 + .dw 0x4001, 0xcc15, 0x4001, 0xcc15, 0x21, 0 + .dw 0x4002, 0xcc15, 0x4002, 0xcc15, 0x22, 0 + .dw 0x4003, 0xcc15, 0x400f, 0xcc15, 0x21, 0 + .dw 0x4010, 0xcc15, 0x4010, 0xcc15, 0x22, 0 + .dw 0x4011, 0xcc15, 0x4011, 0xcc15, 0x21, 0 + .dw 0x4012, 0xcc15, 0x4012, 0xcc15, 0x22, 0 + .dw 0x4013, 0xcc15, 0x403f, 0xcc15, 0x21, 0 + .dw 0x4041, 0xcc15, 0x4041, 0xcc15, 0x21, 0 + .dw 0x4043, 0xcc15, 0x404f, 0xcc15, 0x21, 0 + .dw 0x4051, 0xcc15, 0x4051, 0xcc15, 0x21, 0 + .dw 0x4053, 0xcc15, 0x407f, 0xcc15, 0x21, 0 + .dw 0x4081, 0xcc15, 0x4081, 0xcc15, 0x21, 0 + .dw 0x4083, 0xcc15, 0x408f, 0xcc15, 0x21, 0 + .dw 0x4091, 0xcc15, 0x4091, 0xcc15, 0x21, 0 + .dw 0x4093, 0xcc15, 0x40bf, 0xcc15, 0x21, 0 + .dw 0x40c1, 0xcc15, 0x40c1, 0xcc15, 0x21, 0 + .dw 0x40c3, 0xcc15, 0x40cf, 0xcc15, 0x21, 0 + .dw 0x40d1, 0xcc15, 0x40d1, 0xcc15, 0x21, 0 + .dw 0x40d3, 0xcc15, 0x40ff, 0xcc15, 0x21, 0 + .dw 0x4101, 0xcc15, 0x4101, 0xcc15, 0x21, 0 + .dw 0x4103, 0xcc15, 0x410f, 0xcc15, 0x21, 0 + .dw 0x4111, 0xcc15, 0x4111, 0xcc15, 0x21, 0 + .dw 0x4113, 0xcc15, 0x413f, 0xcc15, 0x21, 0 + .dw 0x4141, 0xcc15, 0x4141, 0xcc15, 0x21, 0 + .dw 0x4143, 0xcc15, 0x414f, 0xcc15, 0x21, 0 + .dw 0x4151, 0xcc15, 0x4151, 0xcc15, 0x21, 0 + .dw 0x4153, 0xcc15, 0x417f, 0xcc15, 0x21, 0 + .dw 0x4181, 0xcc15, 0x4181, 0xcc15, 0x21, 0 + .dw 0x4183, 0xcc15, 0x418f, 0xcc15, 0x21, 0 + .dw 0x4191, 0xcc15, 0x4191, 0xcc15, 0x21, 0 + .dw 0x4193, 0xcc15, 0x41bf, 0xcc15, 0x21, 0 + .dw 0x41c1, 0xcc15, 0x41c1, 0xcc15, 0x21, 0 + .dw 0x41c3, 0xcc15, 0x41cf, 0xcc15, 0x21, 0 + .dw 0x41d1, 0xcc15, 0x41d1, 0xcc15, 0x21, 0 + .dw 0x41d3, 0xcc15, 0x41ff, 0xcc15, 0x21, 0 + .dw 0x4201, 0xcc15, 0x4201, 0xcc15, 0x21, 0 + .dw 0x4203, 0xcc15, 0x420f, 0xcc15, 0x21, 0 + .dw 0x4211, 0xcc15, 0x4211, 0xcc15, 0x21, 0 + .dw 0x4213, 0xcc15, 0x423f, 0xcc15, 0x21, 0 + .dw 0x4240, 0xcc15, 0x4240, 0xcc15, 0x22, 0 + .dw 0x4241, 0xcc15, 0x4241, 0xcc15, 0x21, 0 + .dw 0x4242, 0xcc15, 0x4242, 0xcc15, 0x22, 0 + .dw 0x4243, 0xcc15, 0x424f, 0xcc15, 0x21, 0 + .dw 0x4250, 0xcc15, 0x4250, 0xcc15, 0x22, 0 + .dw 0x4251, 0xcc15, 0x4251, 0xcc15, 0x21, 0 + .dw 0x4252, 0xcc15, 0x4252, 0xcc15, 0x22, 0 + .dw 0x4253, 0xcc15, 0x427f, 0xcc15, 0x21, 0 + .dw 0x4281, 0xcc15, 0x4281, 0xcc15, 0x21, 0 + .dw 0x4283, 0xcc15, 0x428f, 0xcc15, 0x21, 0 + .dw 0x4291, 0xcc15, 0x4291, 0xcc15, 0x21, 0 + .dw 0x4293, 0xcc15, 0x42bf, 0xcc15, 0x21, 0 + .dw 0x42c1, 0xcc15, 0x42c1, 0xcc15, 0x21, 0 + .dw 0x42c3, 0xcc15, 0x42cf, 0xcc15, 0x21, 0 + .dw 0x42d1, 0xcc15, 0x42d1, 0xcc15, 0x21, 0 + .dw 0x42d3, 0xcc15, 0x42ff, 0xcc15, 0x21, 0 + .dw 0x4301, 0xcc15, 0x4301, 0xcc15, 0x21, 0 + .dw 0x4303, 0xcc15, 0x430f, 0xcc15, 0x21, 0 + .dw 0x4311, 0xcc15, 0x4311, 0xcc15, 0x21, 0 + .dw 0x4313, 0xcc15, 0x433f, 0xcc15, 0x21, 0 + .dw 0x4341, 0xcc15, 0x4341, 0xcc15, 0x21, 0 + .dw 0x4343, 0xcc15, 0x434f, 0xcc15, 0x21, 0 + .dw 0x4351, 0xcc15, 0x4351, 0xcc15, 0x21, 0 + .dw 0x4353, 0xcc15, 0x437f, 0xcc15, 0x21, 0 + .dw 0x4381, 0xcc15, 0x4381, 0xcc15, 0x21, 0 + .dw 0x4383, 0xcc15, 0x438f, 0xcc15, 0x21, 0 + .dw 0x4391, 0xcc15, 0x4391, 0xcc15, 0x21, 0 + .dw 0x4393, 0xcc15, 0x43bf, 0xcc15, 0x21, 0 + .dw 0x43c1, 0xcc15, 0x43c1, 0xcc15, 0x21, 0 + .dw 0x43c3, 0xcc15, 0x43cf, 0xcc15, 0x21, 0 + .dw 0x43d1, 0xcc15, 0x43d1, 0xcc15, 0x21, 0 + .dw 0x43d3, 0xcc15, 0x43ff, 0xcc15, 0x21, 0 + .dw 0x4401, 0xcc15, 0x4401, 0xcc15, 0x21, 0 + .dw 0x4403, 0xcc15, 0x440f, 0xcc15, 0x21, 0 + .dw 0x4411, 0xcc15, 0x4411, 0xcc15, 0x21, 0 + .dw 0x4413, 0xcc15, 0x443f, 0xcc15, 0x21, 0 + .dw 0x4441, 0xcc15, 0x4441, 0xcc15, 0x21, 0 + .dw 0x4443, 0xcc15, 0x444f, 0xcc15, 0x21, 0 + .dw 0x4451, 0xcc15, 0x4451, 0xcc15, 0x21, 0 + .dw 0x4453, 0xcc15, 0x447f, 0xcc15, 0x21, 0 + .dw 0x4480, 0xcc15, 0x4480, 0xcc15, 0x22, 0 + .dw 0x4481, 0xcc15, 0x4481, 0xcc15, 0x21, 0 + .dw 0x4482, 0xcc15, 0x4482, 0xcc15, 0x22, 0 + .dw 0x4483, 0xcc15, 0x448f, 0xcc15, 0x21, 0 + .dw 0x4490, 0xcc15, 0x4490, 0xcc15, 0x22, 0 + .dw 0x4491, 0xcc15, 0x4491, 0xcc15, 0x21, 0 + .dw 0x4492, 0xcc15, 0x4492, 0xcc15, 0x22, 0 + .dw 0x4493, 0xcc15, 0x44bf, 0xcc15, 0x21, 0 + .dw 0x44c1, 0xcc15, 0x44c1, 0xcc15, 0x21, 0 + .dw 0x44c3, 0xcc15, 0x44cf, 0xcc15, 0x21, 0 + .dw 0x44d1, 0xcc15, 0x44d1, 0xcc15, 0x21, 0 + .dw 0x44d3, 0xcc15, 0x44ff, 0xcc15, 0x21, 0 + .dw 0x4501, 0xcc15, 0x4501, 0xcc15, 0x21, 0 + .dw 0x4503, 0xcc15, 0x450f, 0xcc15, 0x21, 0 + .dw 0x4511, 0xcc15, 0x4511, 0xcc15, 0x21, 0 + .dw 0x4513, 0xcc15, 0x453f, 0xcc15, 0x21, 0 + .dw 0x4541, 0xcc15, 0x4541, 0xcc15, 0x21, 0 + .dw 0x4543, 0xcc15, 0x454f, 0xcc15, 0x21, 0 + .dw 0x4551, 0xcc15, 0x4551, 0xcc15, 0x21, 0 + .dw 0x4553, 0xcc15, 0x457f, 0xcc15, 0x21, 0 + .dw 0x4581, 0xcc15, 0x4581, 0xcc15, 0x21, 0 + .dw 0x4583, 0xcc15, 0x458f, 0xcc15, 0x21, 0 + .dw 0x4591, 0xcc15, 0x4591, 0xcc15, 0x21, 0 + .dw 0x4593, 0xcc15, 0x45bf, 0xcc15, 0x21, 0 + .dw 0x45c1, 0xcc15, 0x45c1, 0xcc15, 0x21, 0 + .dw 0x45c3, 0xcc15, 0x45cf, 0xcc15, 0x21, 0 + .dw 0x45d1, 0xcc15, 0x45d1, 0xcc15, 0x21, 0 + .dw 0x45d3, 0xcc15, 0x45ff, 0xcc15, 0x21, 0 + .dw 0x4601, 0xcc15, 0x4601, 0xcc15, 0x21, 0 + .dw 0x4603, 0xcc15, 0x460f, 0xcc15, 0x21, 0 + .dw 0x4611, 0xcc15, 0x4611, 0xcc15, 0x21, 0 + .dw 0x4613, 0xcc15, 0x463f, 0xcc15, 0x21, 0 + .dw 0x4641, 0xcc15, 0x4641, 0xcc15, 0x21, 0 + .dw 0x4643, 0xcc15, 0x464f, 0xcc15, 0x21, 0 + .dw 0x4651, 0xcc15, 0x4651, 0xcc15, 0x21, 0 + .dw 0x4653, 0xcc15, 0x467f, 0xcc15, 0x21, 0 + .dw 0x4681, 0xcc15, 0x4681, 0xcc15, 0x21, 0 + .dw 0x4683, 0xcc15, 0x468f, 0xcc15, 0x21, 0 + .dw 0x4691, 0xcc15, 0x4691, 0xcc15, 0x21, 0 + .dw 0x4693, 0xcc15, 0x46bf, 0xcc15, 0x21, 0 + .dw 0x46c0, 0xcc15, 0x46c0, 0xcc15, 0x22, 0 + .dw 0x46c1, 0xcc15, 0x46c1, 0xcc15, 0x21, 0 + .dw 0x46c2, 0xcc15, 0x46c2, 0xcc15, 0x22, 0 + .dw 0x46c3, 0xcc15, 0x46cf, 0xcc15, 0x21, 0 + .dw 0x46d0, 0xcc15, 0x46d0, 0xcc15, 0x22, 0 + .dw 0x46d1, 0xcc15, 0x46d1, 0xcc15, 0x21, 0 + .dw 0x46d2, 0xcc15, 0x46d2, 0xcc15, 0x22, 0 + .dw 0x46d3, 0xcc15, 0x46ff, 0xcc15, 0x21, 0 + .dw 0x4701, 0xcc15, 0x4701, 0xcc15, 0x21, 0 + .dw 0x4703, 0xcc15, 0x470f, 0xcc15, 0x21, 0 + .dw 0x4711, 0xcc15, 0x4711, 0xcc15, 0x21, 0 + .dw 0x4713, 0xcc15, 0x473f, 0xcc15, 0x21, 0 + .dw 0x4741, 0xcc15, 0x4741, 0xcc15, 0x21, 0 + .dw 0x4743, 0xcc15, 0x474f, 0xcc15, 0x21, 0 + .dw 0x4751, 0xcc15, 0x4751, 0xcc15, 0x21, 0 + .dw 0x4753, 0xcc15, 0x477f, 0xcc15, 0x21, 0 + .dw 0x4781, 0xcc15, 0x4781, 0xcc15, 0x21, 0 + .dw 0x4783, 0xcc15, 0x478f, 0xcc15, 0x21, 0 + .dw 0x4791, 0xcc15, 0x4791, 0xcc15, 0x21, 0 + .dw 0x4793, 0xcc15, 0x47bf, 0xcc15, 0x21, 0 + .dw 0x47c1, 0xcc15, 0x47c1, 0xcc15, 0x21, 0 + .dw 0x47c3, 0xcc15, 0x47cf, 0xcc15, 0x21, 0 + .dw 0x47d1, 0xcc15, 0x47d1, 0xcc15, 0x21, 0 + .dw 0x47d3, 0xcc15, 0x47ff, 0xcc15, 0x21, 0 + .dw 0x4801, 0xcc15, 0x4801, 0xcc15, 0x21, 0 + .dw 0x4803, 0xcc15, 0x480f, 0xcc15, 0x21, 0 + .dw 0x4811, 0xcc15, 0x4811, 0xcc15, 0x21, 0 + .dw 0x4813, 0xcc15, 0x483f, 0xcc15, 0x21, 0 + .dw 0x4841, 0xcc15, 0x4841, 0xcc15, 0x21, 0 + .dw 0x4843, 0xcc15, 0x484f, 0xcc15, 0x21, 0 + .dw 0x4851, 0xcc15, 0x4851, 0xcc15, 0x21, 0 + .dw 0x4853, 0xcc15, 0x487f, 0xcc15, 0x21, 0 + .dw 0x4881, 0xcc15, 0x4881, 0xcc15, 0x21, 0 + .dw 0x4883, 0xcc15, 0x488f, 0xcc15, 0x21, 0 + .dw 0x4891, 0xcc15, 0x4891, 0xcc15, 0x21, 0 + .dw 0x4893, 0xcc15, 0x48bf, 0xcc15, 0x21, 0 + .dw 0x48c1, 0xcc15, 0x48c1, 0xcc15, 0x21, 0 + .dw 0x48c3, 0xcc15, 0x48cf, 0xcc15, 0x21, 0 + .dw 0x48d1, 0xcc15, 0x48d1, 0xcc15, 0x21, 0 + .dw 0x48d3, 0xcc15, 0x48ff, 0xcc15, 0x21, 0 + .dw 0x4900, 0xcc15, 0x4900, 0xcc15, 0x22, 0 + .dw 0x4901, 0xcc15, 0x4901, 0xcc15, 0x21, 0 + .dw 0x4902, 0xcc15, 0x4902, 0xcc15, 0x22, 0 + .dw 0x4903, 0xcc15, 0x490f, 0xcc15, 0x21, 0 + .dw 0x4910, 0xcc15, 0x4910, 0xcc15, 0x22, 0 + .dw 0x4911, 0xcc15, 0x4911, 0xcc15, 0x21, 0 + .dw 0x4912, 0xcc15, 0x4912, 0xcc15, 0x22, 0 + .dw 0x4913, 0xcc15, 0x493f, 0xcc15, 0x21, 0 + .dw 0x4941, 0xcc15, 0x4941, 0xcc15, 0x21, 0 + .dw 0x4943, 0xcc15, 0x494f, 0xcc15, 0x21, 0 + .dw 0x4951, 0xcc15, 0x4951, 0xcc15, 0x21, 0 + .dw 0x4953, 0xcc15, 0x497f, 0xcc15, 0x21, 0 + .dw 0x4981, 0xcc15, 0x4981, 0xcc15, 0x21, 0 + .dw 0x4983, 0xcc15, 0x498f, 0xcc15, 0x21, 0 + .dw 0x4991, 0xcc15, 0x4991, 0xcc15, 0x21, 0 + .dw 0x4993, 0xcc15, 0x49bf, 0xcc15, 0x21, 0 + .dw 0x49c1, 0xcc15, 0x49c1, 0xcc15, 0x21, 0 + .dw 0x49c3, 0xcc15, 0x49cf, 0xcc15, 0x21, 0 + .dw 0x49d1, 0xcc15, 0x49d1, 0xcc15, 0x21, 0 + .dw 0x49d3, 0xcc15, 0x49ff, 0xcc15, 0x21, 0 + .dw 0x4a01, 0xcc15, 0x4a01, 0xcc15, 0x21, 0 + .dw 0x4a03, 0xcc15, 0x4a0f, 0xcc15, 0x21, 0 + .dw 0x4a11, 0xcc15, 0x4a11, 0xcc15, 0x21, 0 + .dw 0x4a13, 0xcc15, 0x4a3f, 0xcc15, 0x21, 0 + .dw 0x4a41, 0xcc15, 0x4a41, 0xcc15, 0x21, 0 + .dw 0x4a43, 0xcc15, 0x4a4f, 0xcc15, 0x21, 0 + .dw 0x4a51, 0xcc15, 0x4a51, 0xcc15, 0x21, 0 + .dw 0x4a53, 0xcc15, 0x4a7f, 0xcc15, 0x21, 0 + .dw 0x4a81, 0xcc15, 0x4a81, 0xcc15, 0x21, 0 + .dw 0x4a83, 0xcc15, 0x4a8f, 0xcc15, 0x21, 0 + .dw 0x4a91, 0xcc15, 0x4a91, 0xcc15, 0x21, 0 + .dw 0x4a93, 0xcc15, 0x4abf, 0xcc15, 0x21, 0 + .dw 0x4ac1, 0xcc15, 0x4ac1, 0xcc15, 0x21, 0 + .dw 0x4ac3, 0xcc15, 0x4acf, 0xcc15, 0x21, 0 + .dw 0x4ad1, 0xcc15, 0x4ad1, 0xcc15, 0x21, 0 + .dw 0x4ad3, 0xcc15, 0x4aff, 0xcc15, 0x21, 0 + .dw 0x4b01, 0xcc15, 0x4b01, 0xcc15, 0x21, 0 + .dw 0x4b03, 0xcc15, 0x4b0f, 0xcc15, 0x21, 0 + .dw 0x4b11, 0xcc15, 0x4b11, 0xcc15, 0x21, 0 + .dw 0x4b13, 0xcc15, 0x4b3f, 0xcc15, 0x21, 0 + .dw 0x4b40, 0xcc15, 0x4b40, 0xcc15, 0x22, 0 + .dw 0x4b41, 0xcc15, 0x4b41, 0xcc15, 0x21, 0 + .dw 0x4b42, 0xcc15, 0x4b42, 0xcc15, 0x22, 0 + .dw 0x4b43, 0xcc15, 0x4b4f, 0xcc15, 0x21, 0 + .dw 0x4b50, 0xcc15, 0x4b50, 0xcc15, 0x22, 0 + .dw 0x4b51, 0xcc15, 0x4b51, 0xcc15, 0x21, 0 + .dw 0x4b52, 0xcc15, 0x4b52, 0xcc15, 0x22, 0 + .dw 0x4b53, 0xcc15, 0x4b7f, 0xcc15, 0x21, 0 + .dw 0x4b81, 0xcc15, 0x4b81, 0xcc15, 0x21, 0 + .dw 0x4b83, 0xcc15, 0x4b8f, 0xcc15, 0x21, 0 + .dw 0x4b91, 0xcc15, 0x4b91, 0xcc15, 0x21, 0 + .dw 0x4b93, 0xcc15, 0x4bbf, 0xcc15, 0x21, 0 + .dw 0x4bc1, 0xcc15, 0x4bc1, 0xcc15, 0x21, 0 + .dw 0x4bc3, 0xcc15, 0x4bcf, 0xcc15, 0x21, 0 + .dw 0x4bd1, 0xcc15, 0x4bd1, 0xcc15, 0x21, 0 + .dw 0x4bd3, 0xcc15, 0x4bff, 0xcc15, 0x21, 0 + .dw 0x4c01, 0xcc15, 0x4c01, 0xcc15, 0x21, 0 + .dw 0x4c03, 0xcc15, 0x4c0f, 0xcc15, 0x21, 0 + .dw 0x4c11, 0xcc15, 0x4c11, 0xcc15, 0x21, 0 + .dw 0x4c13, 0xcc15, 0x4c3f, 0xcc15, 0x21, 0 + .dw 0x4c41, 0xcc15, 0x4c41, 0xcc15, 0x21, 0 + .dw 0x4c43, 0xcc15, 0x4c4f, 0xcc15, 0x21, 0 + .dw 0x4c51, 0xcc15, 0x4c51, 0xcc15, 0x21, 0 + .dw 0x4c53, 0xcc15, 0x4c7f, 0xcc15, 0x21, 0 + .dw 0x4c81, 0xcc15, 0x4c81, 0xcc15, 0x21, 0 + .dw 0x4c83, 0xcc15, 0x4c8f, 0xcc15, 0x21, 0 + .dw 0x4c91, 0xcc15, 0x4c91, 0xcc15, 0x21, 0 + .dw 0x4c93, 0xcc15, 0x4cbf, 0xcc15, 0x21, 0 + .dw 0x4cc1, 0xcc15, 0x4cc1, 0xcc15, 0x21, 0 + .dw 0x4cc3, 0xcc15, 0x4ccf, 0xcc15, 0x21, 0 + .dw 0x4cd1, 0xcc15, 0x4cd1, 0xcc15, 0x21, 0 + .dw 0x4cd3, 0xcc15, 0x4cff, 0xcc15, 0x21, 0 + .dw 0x4d01, 0xcc15, 0x4d01, 0xcc15, 0x21, 0 + .dw 0x4d03, 0xcc15, 0x4d0f, 0xcc15, 0x21, 0 + .dw 0x4d11, 0xcc15, 0x4d11, 0xcc15, 0x21, 0 + .dw 0x4d13, 0xcc15, 0x4d3f, 0xcc15, 0x21, 0 + .dw 0x4d41, 0xcc15, 0x4d41, 0xcc15, 0x21, 0 + .dw 0x4d43, 0xcc15, 0x4d4f, 0xcc15, 0x21, 0 + .dw 0x4d51, 0xcc15, 0x4d51, 0xcc15, 0x21, 0 + .dw 0x4d53, 0xcc15, 0x4d7f, 0xcc15, 0x21, 0 + .dw 0x4d80, 0xcc15, 0x4d80, 0xcc15, 0x22, 0 + .dw 0x4d81, 0xcc15, 0x4d81, 0xcc15, 0x21, 0 + .dw 0x4d82, 0xcc15, 0x4d82, 0xcc15, 0x22, 0 + .dw 0x4d83, 0xcc15, 0x4d8f, 0xcc15, 0x21, 0 + .dw 0x4d90, 0xcc15, 0x4d90, 0xcc15, 0x22, 0 + .dw 0x4d91, 0xcc15, 0x4d91, 0xcc15, 0x21, 0 + .dw 0x4d92, 0xcc15, 0x4d92, 0xcc15, 0x22, 0 + .dw 0x4d93, 0xcc15, 0x4dbf, 0xcc15, 0x21, 0 + .dw 0x4dc1, 0xcc15, 0x4dc1, 0xcc15, 0x21, 0 + .dw 0x4dc3, 0xcc15, 0x4dcf, 0xcc15, 0x21, 0 + .dw 0x4dd1, 0xcc15, 0x4dd1, 0xcc15, 0x21, 0 + .dw 0x4dd3, 0xcc15, 0x4dff, 0xcc15, 0x21, 0 + .dw 0x4e01, 0xcc15, 0x4e01, 0xcc15, 0x21, 0 + .dw 0x4e03, 0xcc15, 0x4e0f, 0xcc15, 0x21, 0 + .dw 0x4e11, 0xcc15, 0x4e11, 0xcc15, 0x21, 0 + .dw 0x4e13, 0xcc15, 0x4e3f, 0xcc15, 0x21, 0 + .dw 0x4e41, 0xcc15, 0x4e41, 0xcc15, 0x21, 0 + .dw 0x4e43, 0xcc15, 0x4e4f, 0xcc15, 0x21, 0 + .dw 0x4e51, 0xcc15, 0x4e51, 0xcc15, 0x21, 0 + .dw 0x4e53, 0xcc15, 0x4e7f, 0xcc15, 0x21, 0 + .dw 0x4e81, 0xcc15, 0x4e81, 0xcc15, 0x21, 0 + .dw 0x4e83, 0xcc15, 0x4e8f, 0xcc15, 0x21, 0 + .dw 0x4e91, 0xcc15, 0x4e91, 0xcc15, 0x21, 0 + .dw 0x4e93, 0xcc15, 0x4ebf, 0xcc15, 0x21, 0 + .dw 0x4ec1, 0xcc15, 0x4ec1, 0xcc15, 0x21, 0 + .dw 0x4ec3, 0xcc15, 0x4ecf, 0xcc15, 0x21, 0 + .dw 0x4ed1, 0xcc15, 0x4ed1, 0xcc15, 0x21, 0 + .dw 0x4ed3, 0xcc15, 0x4eff, 0xcc15, 0x21, 0 + .dw 0x4f01, 0xcc15, 0x4f01, 0xcc15, 0x21, 0 + .dw 0x4f03, 0xcc15, 0x4f0f, 0xcc15, 0x21, 0 + .dw 0x4f11, 0xcc15, 0x4f11, 0xcc15, 0x21, 0 + .dw 0x4f13, 0xcc15, 0x4f3f, 0xcc15, 0x21, 0 + .dw 0x4f41, 0xcc15, 0x4f41, 0xcc15, 0x21, 0 + .dw 0x4f43, 0xcc15, 0x4f4f, 0xcc15, 0x21, 0 + .dw 0x4f51, 0xcc15, 0x4f51, 0xcc15, 0x21, 0 + .dw 0x4f53, 0xcc15, 0x4f7f, 0xcc15, 0x21, 0 + .dw 0x4f81, 0xcc15, 0x4f81, 0xcc15, 0x21, 0 + .dw 0x4f83, 0xcc15, 0x4f8f, 0xcc15, 0x21, 0 + .dw 0x4f91, 0xcc15, 0x4f91, 0xcc15, 0x21, 0 + .dw 0x4f93, 0xcc15, 0x4fbf, 0xcc15, 0x21, 0 + .dw 0x4fc0, 0xcc15, 0x4fc0, 0xcc15, 0x22, 0 + .dw 0x4fc1, 0xcc15, 0x4fc1, 0xcc15, 0x21, 0 + .dw 0x4fc2, 0xcc15, 0x4fc2, 0xcc15, 0x22, 0 + .dw 0x4fc3, 0xcc15, 0x4fcf, 0xcc15, 0x21, 0 + .dw 0x4fd0, 0xcc15, 0x4fd0, 0xcc15, 0x22, 0 + .dw 0x4fd1, 0xcc15, 0x4fd1, 0xcc15, 0x21, 0 + .dw 0x4fd2, 0xcc15, 0x4fd2, 0xcc15, 0x22, 0 + .dw 0x4fd3, 0xcc15, 0x5fff, 0xcc15, 0x21, 0 + .dw 0x6000, 0xcc15, 0x6000, 0xcc15, 0x22, 0 + .dw 0x6001, 0xcc15, 0x6001, 0xcc15, 0x21, 0 + .dw 0x6002, 0xcc15, 0x6002, 0xcc15, 0x22, 0 + .dw 0x6003, 0xcc15, 0x600f, 0xcc15, 0x21, 0 + .dw 0x6010, 0xcc15, 0x6010, 0xcc15, 0x22, 0 + .dw 0x6011, 0xcc15, 0x6011, 0xcc15, 0x21, 0 + .dw 0x6012, 0xcc15, 0x6012, 0xcc15, 0x22, 0 + .dw 0x6013, 0xcc15, 0x603f, 0xcc15, 0x21, 0 + .dw 0x6041, 0xcc15, 0x6041, 0xcc15, 0x21, 0 + .dw 0x6043, 0xcc15, 0x604f, 0xcc15, 0x21, 0 + .dw 0x6051, 0xcc15, 0x6051, 0xcc15, 0x21, 0 + .dw 0x6053, 0xcc15, 0x607f, 0xcc15, 0x21, 0 + .dw 0x6081, 0xcc15, 0x6081, 0xcc15, 0x21, 0 + .dw 0x6083, 0xcc15, 0x608f, 0xcc15, 0x21, 0 + .dw 0x6091, 0xcc15, 0x6091, 0xcc15, 0x21, 0 + .dw 0x6093, 0xcc15, 0x60bf, 0xcc15, 0x21, 0 + .dw 0x60c1, 0xcc15, 0x60c1, 0xcc15, 0x21, 0 + .dw 0x60c3, 0xcc15, 0x60cf, 0xcc15, 0x21, 0 + .dw 0x60d1, 0xcc15, 0x60d1, 0xcc15, 0x21, 0 + .dw 0x60d3, 0xcc15, 0x60ff, 0xcc15, 0x21, 0 + .dw 0x6101, 0xcc15, 0x6101, 0xcc15, 0x21, 0 + .dw 0x6103, 0xcc15, 0x610f, 0xcc15, 0x21, 0 + .dw 0x6111, 0xcc15, 0x6111, 0xcc15, 0x21, 0 + .dw 0x6113, 0xcc15, 0x613f, 0xcc15, 0x21, 0 + .dw 0x6141, 0xcc15, 0x6141, 0xcc15, 0x21, 0 + .dw 0x6143, 0xcc15, 0x614f, 0xcc15, 0x21, 0 + .dw 0x6151, 0xcc15, 0x6151, 0xcc15, 0x21, 0 + .dw 0x6153, 0xcc15, 0x617f, 0xcc15, 0x21, 0 + .dw 0x6181, 0xcc15, 0x6181, 0xcc15, 0x21, 0 + .dw 0x6183, 0xcc15, 0x618f, 0xcc15, 0x21, 0 + .dw 0x6191, 0xcc15, 0x6191, 0xcc15, 0x21, 0 + .dw 0x6193, 0xcc15, 0x61bf, 0xcc15, 0x21, 0 + .dw 0x61c1, 0xcc15, 0x61c1, 0xcc15, 0x21, 0 + .dw 0x61c3, 0xcc15, 0x61cf, 0xcc15, 0x21, 0 + .dw 0x61d1, 0xcc15, 0x61d1, 0xcc15, 0x21, 0 + .dw 0x61d3, 0xcc15, 0x61ff, 0xcc15, 0x21, 0 + .dw 0x6201, 0xcc15, 0x6201, 0xcc15, 0x21, 0 + .dw 0x6203, 0xcc15, 0x620f, 0xcc15, 0x21, 0 + .dw 0x6211, 0xcc15, 0x6211, 0xcc15, 0x21, 0 + .dw 0x6213, 0xcc15, 0x623f, 0xcc15, 0x21, 0 + .dw 0x6240, 0xcc15, 0x6240, 0xcc15, 0x22, 0 + .dw 0x6241, 0xcc15, 0x6241, 0xcc15, 0x21, 0 + .dw 0x6242, 0xcc15, 0x6242, 0xcc15, 0x22, 0 + .dw 0x6243, 0xcc15, 0x624f, 0xcc15, 0x21, 0 + .dw 0x6250, 0xcc15, 0x6250, 0xcc15, 0x22, 0 + .dw 0x6251, 0xcc15, 0x6251, 0xcc15, 0x21, 0 + .dw 0x6252, 0xcc15, 0x6252, 0xcc15, 0x22, 0 + .dw 0x6253, 0xcc15, 0x627f, 0xcc15, 0x21, 0 + .dw 0x6281, 0xcc15, 0x6281, 0xcc15, 0x21, 0 + .dw 0x6283, 0xcc15, 0x628f, 0xcc15, 0x21, 0 + .dw 0x6291, 0xcc15, 0x6291, 0xcc15, 0x21, 0 + .dw 0x6293, 0xcc15, 0x62bf, 0xcc15, 0x21, 0 + .dw 0x62c1, 0xcc15, 0x62c1, 0xcc15, 0x21, 0 + .dw 0x62c3, 0xcc15, 0x62cf, 0xcc15, 0x21, 0 + .dw 0x62d1, 0xcc15, 0x62d1, 0xcc15, 0x21, 0 + .dw 0x62d3, 0xcc15, 0x62ff, 0xcc15, 0x21, 0 + .dw 0x6301, 0xcc15, 0x6301, 0xcc15, 0x21, 0 + .dw 0x6303, 0xcc15, 0x630f, 0xcc15, 0x21, 0 + .dw 0x6311, 0xcc15, 0x6311, 0xcc15, 0x21, 0 + .dw 0x6313, 0xcc15, 0x633f, 0xcc15, 0x21, 0 + .dw 0x6341, 0xcc15, 0x6341, 0xcc15, 0x21, 0 + .dw 0x6343, 0xcc15, 0x634f, 0xcc15, 0x21, 0 + .dw 0x6351, 0xcc15, 0x6351, 0xcc15, 0x21, 0 + .dw 0x6353, 0xcc15, 0x637f, 0xcc15, 0x21, 0 + .dw 0x6381, 0xcc15, 0x6381, 0xcc15, 0x21, 0 + .dw 0x6383, 0xcc15, 0x638f, 0xcc15, 0x21, 0 + .dw 0x6391, 0xcc15, 0x6391, 0xcc15, 0x21, 0 + .dw 0x6393, 0xcc15, 0x63bf, 0xcc15, 0x21, 0 + .dw 0x63c1, 0xcc15, 0x63c1, 0xcc15, 0x21, 0 + .dw 0x63c3, 0xcc15, 0x63cf, 0xcc15, 0x21, 0 + .dw 0x63d1, 0xcc15, 0x63d1, 0xcc15, 0x21, 0 + .dw 0x63d3, 0xcc15, 0x63ff, 0xcc15, 0x21, 0 + .dw 0x6401, 0xcc15, 0x6401, 0xcc15, 0x21, 0 + .dw 0x6403, 0xcc15, 0x640f, 0xcc15, 0x21, 0 + .dw 0x6411, 0xcc15, 0x6411, 0xcc15, 0x21, 0 + .dw 0x6413, 0xcc15, 0x643f, 0xcc15, 0x21, 0 + .dw 0x6441, 0xcc15, 0x6441, 0xcc15, 0x21, 0 + .dw 0x6443, 0xcc15, 0x644f, 0xcc15, 0x21, 0 + .dw 0x6451, 0xcc15, 0x6451, 0xcc15, 0x21, 0 + .dw 0x6453, 0xcc15, 0x647f, 0xcc15, 0x21, 0 + .dw 0x6480, 0xcc15, 0x6480, 0xcc15, 0x22, 0 + .dw 0x6481, 0xcc15, 0x6481, 0xcc15, 0x21, 0 + .dw 0x6482, 0xcc15, 0x6482, 0xcc15, 0x22, 0 + .dw 0x6483, 0xcc15, 0x648f, 0xcc15, 0x21, 0 + .dw 0x6490, 0xcc15, 0x6490, 0xcc15, 0x22, 0 + .dw 0x6491, 0xcc15, 0x6491, 0xcc15, 0x21, 0 + .dw 0x6492, 0xcc15, 0x6492, 0xcc15, 0x22, 0 + .dw 0x6493, 0xcc15, 0x64bf, 0xcc15, 0x21, 0 + .dw 0x64c1, 0xcc15, 0x64c1, 0xcc15, 0x21, 0 + .dw 0x64c3, 0xcc15, 0x64cf, 0xcc15, 0x21, 0 + .dw 0x64d1, 0xcc15, 0x64d1, 0xcc15, 0x21, 0 + .dw 0x64d3, 0xcc15, 0x64ff, 0xcc15, 0x21, 0 + .dw 0x6501, 0xcc15, 0x6501, 0xcc15, 0x21, 0 + .dw 0x6503, 0xcc15, 0x650f, 0xcc15, 0x21, 0 + .dw 0x6511, 0xcc15, 0x6511, 0xcc15, 0x21, 0 + .dw 0x6513, 0xcc15, 0x653f, 0xcc15, 0x21, 0 + .dw 0x6541, 0xcc15, 0x6541, 0xcc15, 0x21, 0 + .dw 0x6543, 0xcc15, 0x654f, 0xcc15, 0x21, 0 + .dw 0x6551, 0xcc15, 0x6551, 0xcc15, 0x21, 0 + .dw 0x6553, 0xcc15, 0x657f, 0xcc15, 0x21, 0 + .dw 0x6581, 0xcc15, 0x6581, 0xcc15, 0x21, 0 + .dw 0x6583, 0xcc15, 0x658f, 0xcc15, 0x21, 0 + .dw 0x6591, 0xcc15, 0x6591, 0xcc15, 0x21, 0 + .dw 0x6593, 0xcc15, 0x65bf, 0xcc15, 0x21, 0 + .dw 0x65c1, 0xcc15, 0x65c1, 0xcc15, 0x21, 0 + .dw 0x65c3, 0xcc15, 0x65cf, 0xcc15, 0x21, 0 + .dw 0x65d1, 0xcc15, 0x65d1, 0xcc15, 0x21, 0 + .dw 0x65d3, 0xcc15, 0x65ff, 0xcc15, 0x21, 0 + .dw 0x6601, 0xcc15, 0x6601, 0xcc15, 0x21, 0 + .dw 0x6603, 0xcc15, 0x660f, 0xcc15, 0x21, 0 + .dw 0x6611, 0xcc15, 0x6611, 0xcc15, 0x21, 0 + .dw 0x6613, 0xcc15, 0x663f, 0xcc15, 0x21, 0 + .dw 0x6641, 0xcc15, 0x6641, 0xcc15, 0x21, 0 + .dw 0x6643, 0xcc15, 0x664f, 0xcc15, 0x21, 0 + .dw 0x6651, 0xcc15, 0x6651, 0xcc15, 0x21, 0 + .dw 0x6653, 0xcc15, 0x667f, 0xcc15, 0x21, 0 + .dw 0x6681, 0xcc15, 0x6681, 0xcc15, 0x21, 0 + .dw 0x6683, 0xcc15, 0x668f, 0xcc15, 0x21, 0 + .dw 0x6691, 0xcc15, 0x6691, 0xcc15, 0x21, 0 + .dw 0x6693, 0xcc15, 0x66bf, 0xcc15, 0x21, 0 + .dw 0x66c0, 0xcc15, 0x66c0, 0xcc15, 0x22, 0 + .dw 0x66c1, 0xcc15, 0x66c1, 0xcc15, 0x21, 0 + .dw 0x66c2, 0xcc15, 0x66c2, 0xcc15, 0x22, 0 + .dw 0x66c3, 0xcc15, 0x66cf, 0xcc15, 0x21, 0 + .dw 0x66d0, 0xcc15, 0x66d0, 0xcc15, 0x22, 0 + .dw 0x66d1, 0xcc15, 0x66d1, 0xcc15, 0x21, 0 + .dw 0x66d2, 0xcc15, 0x66d2, 0xcc15, 0x22, 0 + .dw 0x66d3, 0xcc15, 0x66ff, 0xcc15, 0x21, 0 + .dw 0x6701, 0xcc15, 0x6701, 0xcc15, 0x21, 0 + .dw 0x6703, 0xcc15, 0x670f, 0xcc15, 0x21, 0 + .dw 0x6711, 0xcc15, 0x6711, 0xcc15, 0x21, 0 + .dw 0x6713, 0xcc15, 0x673f, 0xcc15, 0x21, 0 + .dw 0x6741, 0xcc15, 0x6741, 0xcc15, 0x21, 0 + .dw 0x6743, 0xcc15, 0x674f, 0xcc15, 0x21, 0 + .dw 0x6751, 0xcc15, 0x6751, 0xcc15, 0x21, 0 + .dw 0x6753, 0xcc15, 0x677f, 0xcc15, 0x21, 0 + .dw 0x6781, 0xcc15, 0x6781, 0xcc15, 0x21, 0 + .dw 0x6783, 0xcc15, 0x678f, 0xcc15, 0x21, 0 + .dw 0x6791, 0xcc15, 0x6791, 0xcc15, 0x21, 0 + .dw 0x6793, 0xcc15, 0x67bf, 0xcc15, 0x21, 0 + .dw 0x67c1, 0xcc15, 0x67c1, 0xcc15, 0x21, 0 + .dw 0x67c3, 0xcc15, 0x67cf, 0xcc15, 0x21, 0 + .dw 0x67d1, 0xcc15, 0x67d1, 0xcc15, 0x21, 0 + .dw 0x67d3, 0xcc15, 0x67ff, 0xcc15, 0x21, 0 + .dw 0x6801, 0xcc15, 0x6801, 0xcc15, 0x21, 0 + .dw 0x6803, 0xcc15, 0x680f, 0xcc15, 0x21, 0 + .dw 0x6811, 0xcc15, 0x6811, 0xcc15, 0x21, 0 + .dw 0x6813, 0xcc15, 0x683f, 0xcc15, 0x21, 0 + .dw 0x6841, 0xcc15, 0x6841, 0xcc15, 0x21, 0 + .dw 0x6843, 0xcc15, 0x684f, 0xcc15, 0x21, 0 + .dw 0x6851, 0xcc15, 0x6851, 0xcc15, 0x21, 0 + .dw 0x6853, 0xcc15, 0x687f, 0xcc15, 0x21, 0 + .dw 0x6881, 0xcc15, 0x6881, 0xcc15, 0x21, 0 + .dw 0x6883, 0xcc15, 0x688f, 0xcc15, 0x21, 0 + .dw 0x6891, 0xcc15, 0x6891, 0xcc15, 0x21, 0 + .dw 0x6893, 0xcc15, 0x68bf, 0xcc15, 0x21, 0 + .dw 0x68c1, 0xcc15, 0x68c1, 0xcc15, 0x21, 0 + .dw 0x68c3, 0xcc15, 0x68cf, 0xcc15, 0x21, 0 + .dw 0x68d1, 0xcc15, 0x68d1, 0xcc15, 0x21, 0 + .dw 0x68d3, 0xcc15, 0x68ff, 0xcc15, 0x21, 0 + .dw 0x6900, 0xcc15, 0x6900, 0xcc15, 0x22, 0 + .dw 0x6901, 0xcc15, 0x6901, 0xcc15, 0x21, 0 + .dw 0x6902, 0xcc15, 0x6902, 0xcc15, 0x22, 0 + .dw 0x6903, 0xcc15, 0x690f, 0xcc15, 0x21, 0 + .dw 0x6910, 0xcc15, 0x6910, 0xcc15, 0x22, 0 + .dw 0x6911, 0xcc15, 0x6911, 0xcc15, 0x21, 0 + .dw 0x6912, 0xcc15, 0x6912, 0xcc15, 0x22, 0 + .dw 0x6913, 0xcc15, 0x693f, 0xcc15, 0x21, 0 + .dw 0x6941, 0xcc15, 0x6941, 0xcc15, 0x21, 0 + .dw 0x6943, 0xcc15, 0x694f, 0xcc15, 0x21, 0 + .dw 0x6951, 0xcc15, 0x6951, 0xcc15, 0x21, 0 + .dw 0x6953, 0xcc15, 0x697f, 0xcc15, 0x21, 0 + .dw 0x6981, 0xcc15, 0x6981, 0xcc15, 0x21, 0 + .dw 0x6983, 0xcc15, 0x698f, 0xcc15, 0x21, 0 + .dw 0x6991, 0xcc15, 0x6991, 0xcc15, 0x21, 0 + .dw 0x6993, 0xcc15, 0x69bf, 0xcc15, 0x21, 0 + .dw 0x69c1, 0xcc15, 0x69c1, 0xcc15, 0x21, 0 + .dw 0x69c3, 0xcc15, 0x69cf, 0xcc15, 0x21, 0 + .dw 0x69d1, 0xcc15, 0x69d1, 0xcc15, 0x21, 0 + .dw 0x69d3, 0xcc15, 0x69ff, 0xcc15, 0x21, 0 + .dw 0x6a01, 0xcc15, 0x6a01, 0xcc15, 0x21, 0 + .dw 0x6a03, 0xcc15, 0x6a0f, 0xcc15, 0x21, 0 + .dw 0x6a11, 0xcc15, 0x6a11, 0xcc15, 0x21, 0 + .dw 0x6a13, 0xcc15, 0x6a3f, 0xcc15, 0x21, 0 + .dw 0x6a41, 0xcc15, 0x6a41, 0xcc15, 0x21, 0 + .dw 0x6a43, 0xcc15, 0x6a4f, 0xcc15, 0x21, 0 + .dw 0x6a51, 0xcc15, 0x6a51, 0xcc15, 0x21, 0 + .dw 0x6a53, 0xcc15, 0x6a7f, 0xcc15, 0x21, 0 + .dw 0x6a81, 0xcc15, 0x6a81, 0xcc15, 0x21, 0 + .dw 0x6a83, 0xcc15, 0x6a8f, 0xcc15, 0x21, 0 + .dw 0x6a91, 0xcc15, 0x6a91, 0xcc15, 0x21, 0 + .dw 0x6a93, 0xcc15, 0x6abf, 0xcc15, 0x21, 0 + .dw 0x6ac1, 0xcc15, 0x6ac1, 0xcc15, 0x21, 0 + .dw 0x6ac3, 0xcc15, 0x6acf, 0xcc15, 0x21, 0 + .dw 0x6ad1, 0xcc15, 0x6ad1, 0xcc15, 0x21, 0 + .dw 0x6ad3, 0xcc15, 0x6aff, 0xcc15, 0x21, 0 + .dw 0x6b01, 0xcc15, 0x6b01, 0xcc15, 0x21, 0 + .dw 0x6b03, 0xcc15, 0x6b0f, 0xcc15, 0x21, 0 + .dw 0x6b11, 0xcc15, 0x6b11, 0xcc15, 0x21, 0 + .dw 0x6b13, 0xcc15, 0x6b3f, 0xcc15, 0x21, 0 + .dw 0x6b40, 0xcc15, 0x6b40, 0xcc15, 0x22, 0 + .dw 0x6b41, 0xcc15, 0x6b41, 0xcc15, 0x21, 0 + .dw 0x6b42, 0xcc15, 0x6b42, 0xcc15, 0x22, 0 + .dw 0x6b43, 0xcc15, 0x6b4f, 0xcc15, 0x21, 0 + .dw 0x6b50, 0xcc15, 0x6b50, 0xcc15, 0x22, 0 + .dw 0x6b51, 0xcc15, 0x6b51, 0xcc15, 0x21, 0 + .dw 0x6b52, 0xcc15, 0x6b52, 0xcc15, 0x22, 0 + .dw 0x6b53, 0xcc15, 0x6b7f, 0xcc15, 0x21, 0 + .dw 0x6b81, 0xcc15, 0x6b81, 0xcc15, 0x21, 0 + .dw 0x6b83, 0xcc15, 0x6b8f, 0xcc15, 0x21, 0 + .dw 0x6b91, 0xcc15, 0x6b91, 0xcc15, 0x21, 0 + .dw 0x6b93, 0xcc15, 0x6bbf, 0xcc15, 0x21, 0 + .dw 0x6bc1, 0xcc15, 0x6bc1, 0xcc15, 0x21, 0 + .dw 0x6bc3, 0xcc15, 0x6bcf, 0xcc15, 0x21, 0 + .dw 0x6bd1, 0xcc15, 0x6bd1, 0xcc15, 0x21, 0 + .dw 0x6bd3, 0xcc15, 0x6bff, 0xcc15, 0x21, 0 + .dw 0x6c01, 0xcc15, 0x6c01, 0xcc15, 0x21, 0 + .dw 0x6c03, 0xcc15, 0x6c0f, 0xcc15, 0x21, 0 + .dw 0x6c11, 0xcc15, 0x6c11, 0xcc15, 0x21, 0 + .dw 0x6c13, 0xcc15, 0x6c3f, 0xcc15, 0x21, 0 + .dw 0x6c41, 0xcc15, 0x6c41, 0xcc15, 0x21, 0 + .dw 0x6c43, 0xcc15, 0x6c4f, 0xcc15, 0x21, 0 + .dw 0x6c51, 0xcc15, 0x6c51, 0xcc15, 0x21, 0 + .dw 0x6c53, 0xcc15, 0x6c7f, 0xcc15, 0x21, 0 + .dw 0x6c81, 0xcc15, 0x6c81, 0xcc15, 0x21, 0 + .dw 0x6c83, 0xcc15, 0x6c8f, 0xcc15, 0x21, 0 + .dw 0x6c91, 0xcc15, 0x6c91, 0xcc15, 0x21, 0 + .dw 0x6c93, 0xcc15, 0x6cbf, 0xcc15, 0x21, 0 + .dw 0x6cc1, 0xcc15, 0x6cc1, 0xcc15, 0x21, 0 + .dw 0x6cc3, 0xcc15, 0x6ccf, 0xcc15, 0x21, 0 + .dw 0x6cd1, 0xcc15, 0x6cd1, 0xcc15, 0x21, 0 + .dw 0x6cd3, 0xcc15, 0x6cff, 0xcc15, 0x21, 0 + .dw 0x6d01, 0xcc15, 0x6d01, 0xcc15, 0x21, 0 + .dw 0x6d03, 0xcc15, 0x6d0f, 0xcc15, 0x21, 0 + .dw 0x6d11, 0xcc15, 0x6d11, 0xcc15, 0x21, 0 + .dw 0x6d13, 0xcc15, 0x6d3f, 0xcc15, 0x21, 0 + .dw 0x6d41, 0xcc15, 0x6d41, 0xcc15, 0x21, 0 + .dw 0x6d43, 0xcc15, 0x6d4f, 0xcc15, 0x21, 0 + .dw 0x6d51, 0xcc15, 0x6d51, 0xcc15, 0x21, 0 + .dw 0x6d53, 0xcc15, 0x6d7f, 0xcc15, 0x21, 0 + .dw 0x6d80, 0xcc15, 0x6d80, 0xcc15, 0x22, 0 + .dw 0x6d81, 0xcc15, 0x6d81, 0xcc15, 0x21, 0 + .dw 0x6d82, 0xcc15, 0x6d82, 0xcc15, 0x22, 0 + .dw 0x6d83, 0xcc15, 0x6d8f, 0xcc15, 0x21, 0 + .dw 0x6d90, 0xcc15, 0x6d90, 0xcc15, 0x22, 0 + .dw 0x6d91, 0xcc15, 0x6d91, 0xcc15, 0x21, 0 + .dw 0x6d92, 0xcc15, 0x6d92, 0xcc15, 0x22, 0 + .dw 0x6d93, 0xcc15, 0x6dbf, 0xcc15, 0x21, 0 + .dw 0x6dc1, 0xcc15, 0x6dc1, 0xcc15, 0x21, 0 + .dw 0x6dc3, 0xcc15, 0x6dcf, 0xcc15, 0x21, 0 + .dw 0x6dd1, 0xcc15, 0x6dd1, 0xcc15, 0x21, 0 + .dw 0x6dd3, 0xcc15, 0x6dff, 0xcc15, 0x21, 0 + .dw 0x6e01, 0xcc15, 0x6e01, 0xcc15, 0x21, 0 + .dw 0x6e03, 0xcc15, 0x6e0f, 0xcc15, 0x21, 0 + .dw 0x6e11, 0xcc15, 0x6e11, 0xcc15, 0x21, 0 + .dw 0x6e13, 0xcc15, 0x6e3f, 0xcc15, 0x21, 0 + .dw 0x6e41, 0xcc15, 0x6e41, 0xcc15, 0x21, 0 + .dw 0x6e43, 0xcc15, 0x6e4f, 0xcc15, 0x21, 0 + .dw 0x6e51, 0xcc15, 0x6e51, 0xcc15, 0x21, 0 + .dw 0x6e53, 0xcc15, 0x6e7f, 0xcc15, 0x21, 0 + .dw 0x6e81, 0xcc15, 0x6e81, 0xcc15, 0x21, 0 + .dw 0x6e83, 0xcc15, 0x6e8f, 0xcc15, 0x21, 0 + .dw 0x6e91, 0xcc15, 0x6e91, 0xcc15, 0x21, 0 + .dw 0x6e93, 0xcc15, 0x6ebf, 0xcc15, 0x21, 0 + .dw 0x6ec1, 0xcc15, 0x6ec1, 0xcc15, 0x21, 0 + .dw 0x6ec3, 0xcc15, 0x6ecf, 0xcc15, 0x21, 0 + .dw 0x6ed1, 0xcc15, 0x6ed1, 0xcc15, 0x21, 0 + .dw 0x6ed3, 0xcc15, 0x6eff, 0xcc15, 0x21, 0 + .dw 0x6f01, 0xcc15, 0x6f01, 0xcc15, 0x21, 0 + .dw 0x6f03, 0xcc15, 0x6f0f, 0xcc15, 0x21, 0 + .dw 0x6f11, 0xcc15, 0x6f11, 0xcc15, 0x21, 0 + .dw 0x6f13, 0xcc15, 0x6f3f, 0xcc15, 0x21, 0 + .dw 0x6f41, 0xcc15, 0x6f41, 0xcc15, 0x21, 0 + .dw 0x6f43, 0xcc15, 0x6f4f, 0xcc15, 0x21, 0 + .dw 0x6f51, 0xcc15, 0x6f51, 0xcc15, 0x21, 0 + .dw 0x6f53, 0xcc15, 0x6f7f, 0xcc15, 0x21, 0 + .dw 0x6f81, 0xcc15, 0x6f81, 0xcc15, 0x21, 0 + .dw 0x6f83, 0xcc15, 0x6f8f, 0xcc15, 0x21, 0 + .dw 0x6f91, 0xcc15, 0x6f91, 0xcc15, 0x21, 0 + .dw 0x6f93, 0xcc15, 0x6fbf, 0xcc15, 0x21, 0 + .dw 0x6fc0, 0xcc15, 0x6fc0, 0xcc15, 0x22, 0 + .dw 0x6fc1, 0xcc15, 0x6fc1, 0xcc15, 0x21, 0 + .dw 0x6fc2, 0xcc15, 0x6fc2, 0xcc15, 0x22, 0 + .dw 0x6fc3, 0xcc15, 0x6fcf, 0xcc15, 0x21, 0 + .dw 0x6fd0, 0xcc15, 0x6fd0, 0xcc15, 0x22, 0 + .dw 0x6fd1, 0xcc15, 0x6fd1, 0xcc15, 0x21, 0 + .dw 0x6fd2, 0xcc15, 0x6fd2, 0xcc15, 0x22, 0 + .dw 0x6fd3, 0xcc15, 0xffff, 0xcc15, 0x21, 0 + .dw 0x0001, 0xcc16, 0x0001, 0xcc16, 0x21, 0 + .dw 0x0003, 0xcc16, 0x000f, 0xcc16, 0x21, 0 + .dw 0x0011, 0xcc16, 0x0011, 0xcc16, 0x21, 0 + .dw 0x0013, 0xcc16, 0x003f, 0xcc16, 0x21, 0 + .dw 0x0041, 0xcc16, 0x0041, 0xcc16, 0x21, 0 + .dw 0x0043, 0xcc16, 0x004f, 0xcc16, 0x21, 0 + .dw 0x0051, 0xcc16, 0x0051, 0xcc16, 0x21, 0 + .dw 0x0053, 0xcc16, 0x007f, 0xcc16, 0x21, 0 + .dw 0x0081, 0xcc16, 0x0081, 0xcc16, 0x21, 0 + .dw 0x0083, 0xcc16, 0x008f, 0xcc16, 0x21, 0 + .dw 0x0091, 0xcc16, 0x0091, 0xcc16, 0x21, 0 + .dw 0x0093, 0xcc16, 0x00bf, 0xcc16, 0x21, 0 + .dw 0x00c1, 0xcc16, 0x00c1, 0xcc16, 0x21, 0 + .dw 0x00c3, 0xcc16, 0x00cf, 0xcc16, 0x21, 0 + .dw 0x00d1, 0xcc16, 0x00d1, 0xcc16, 0x21, 0 + .dw 0x00d3, 0xcc16, 0x00ff, 0xcc16, 0x21, 0 + .dw 0x0101, 0xcc16, 0x0101, 0xcc16, 0x21, 0 + .dw 0x0103, 0xcc16, 0x010f, 0xcc16, 0x21, 0 + .dw 0x0111, 0xcc16, 0x0111, 0xcc16, 0x21, 0 + .dw 0x0113, 0xcc16, 0x013f, 0xcc16, 0x21, 0 + .dw 0x0141, 0xcc16, 0x0141, 0xcc16, 0x21, 0 + .dw 0x0143, 0xcc16, 0x014f, 0xcc16, 0x21, 0 + .dw 0x0151, 0xcc16, 0x0151, 0xcc16, 0x21, 0 + .dw 0x0153, 0xcc16, 0x017f, 0xcc16, 0x21, 0 + .dw 0x0181, 0xcc16, 0x0181, 0xcc16, 0x21, 0 + .dw 0x0183, 0xcc16, 0x018f, 0xcc16, 0x21, 0 + .dw 0x0191, 0xcc16, 0x0191, 0xcc16, 0x21, 0 + .dw 0x0193, 0xcc16, 0x01bf, 0xcc16, 0x21, 0 + .dw 0x01c1, 0xcc16, 0x01c1, 0xcc16, 0x21, 0 + .dw 0x01c3, 0xcc16, 0x01cf, 0xcc16, 0x21, 0 + .dw 0x01d1, 0xcc16, 0x01d1, 0xcc16, 0x21, 0 + .dw 0x01d3, 0xcc16, 0x01ff, 0xcc16, 0x21, 0 + .dw 0x0201, 0xcc16, 0x0201, 0xcc16, 0x21, 0 + .dw 0x0203, 0xcc16, 0x020f, 0xcc16, 0x21, 0 + .dw 0x0211, 0xcc16, 0x0211, 0xcc16, 0x21, 0 + .dw 0x0213, 0xcc16, 0x023f, 0xcc16, 0x21, 0 + .dw 0x0241, 0xcc16, 0x0241, 0xcc16, 0x21, 0 + .dw 0x0243, 0xcc16, 0x024f, 0xcc16, 0x21, 0 + .dw 0x0251, 0xcc16, 0x0251, 0xcc16, 0x21, 0 + .dw 0x0253, 0xcc16, 0x027f, 0xcc16, 0x21, 0 + .dw 0x0281, 0xcc16, 0x0281, 0xcc16, 0x21, 0 + .dw 0x0283, 0xcc16, 0x028f, 0xcc16, 0x21, 0 + .dw 0x0291, 0xcc16, 0x0291, 0xcc16, 0x21, 0 + .dw 0x0293, 0xcc16, 0x02bf, 0xcc16, 0x21, 0 + .dw 0x02c1, 0xcc16, 0x02c1, 0xcc16, 0x21, 0 + .dw 0x02c3, 0xcc16, 0x02cf, 0xcc16, 0x21, 0 + .dw 0x02d1, 0xcc16, 0x02d1, 0xcc16, 0x21, 0 + .dw 0x02d3, 0xcc16, 0x02ff, 0xcc16, 0x21, 0 + .dw 0x0301, 0xcc16, 0x0301, 0xcc16, 0x21, 0 + .dw 0x0303, 0xcc16, 0x030f, 0xcc16, 0x21, 0 + .dw 0x0311, 0xcc16, 0x0311, 0xcc16, 0x21, 0 + .dw 0x0313, 0xcc16, 0x033f, 0xcc16, 0x21, 0 + .dw 0x0341, 0xcc16, 0x0341, 0xcc16, 0x21, 0 + .dw 0x0343, 0xcc16, 0x034f, 0xcc16, 0x21, 0 + .dw 0x0351, 0xcc16, 0x0351, 0xcc16, 0x21, 0 + .dw 0x0353, 0xcc16, 0x037f, 0xcc16, 0x21, 0 + .dw 0x0381, 0xcc16, 0x0381, 0xcc16, 0x21, 0 + .dw 0x0383, 0xcc16, 0x038f, 0xcc16, 0x21, 0 + .dw 0x0391, 0xcc16, 0x0391, 0xcc16, 0x21, 0 + .dw 0x0393, 0xcc16, 0x03bf, 0xcc16, 0x21, 0 + .dw 0x03c1, 0xcc16, 0x03c1, 0xcc16, 0x21, 0 + .dw 0x03c3, 0xcc16, 0x03cf, 0xcc16, 0x21, 0 + .dw 0x03d1, 0xcc16, 0x03d1, 0xcc16, 0x21, 0 + .dw 0x03d3, 0xcc16, 0x03ff, 0xcc16, 0x21, 0 + .dw 0x0401, 0xcc16, 0x0401, 0xcc16, 0x21, 0 + .dw 0x0403, 0xcc16, 0x040f, 0xcc16, 0x21, 0 + .dw 0x0411, 0xcc16, 0x0411, 0xcc16, 0x21, 0 + .dw 0x0413, 0xcc16, 0x043f, 0xcc16, 0x21, 0 + .dw 0x0441, 0xcc16, 0x0441, 0xcc16, 0x21, 0 + .dw 0x0443, 0xcc16, 0x044f, 0xcc16, 0x21, 0 + .dw 0x0451, 0xcc16, 0x0451, 0xcc16, 0x21, 0 + .dw 0x0453, 0xcc16, 0x047f, 0xcc16, 0x21, 0 + .dw 0x0481, 0xcc16, 0x0481, 0xcc16, 0x21, 0 + .dw 0x0483, 0xcc16, 0x048f, 0xcc16, 0x21, 0 + .dw 0x0491, 0xcc16, 0x0491, 0xcc16, 0x21, 0 + .dw 0x0493, 0xcc16, 0x04bf, 0xcc16, 0x21, 0 + .dw 0x04c1, 0xcc16, 0x04c1, 0xcc16, 0x21, 0 + .dw 0x04c3, 0xcc16, 0x04cf, 0xcc16, 0x21, 0 + .dw 0x04d1, 0xcc16, 0x04d1, 0xcc16, 0x21, 0 + .dw 0x04d3, 0xcc16, 0x04ff, 0xcc16, 0x21, 0 + .dw 0x0501, 0xcc16, 0x0501, 0xcc16, 0x21, 0 + .dw 0x0503, 0xcc16, 0x050f, 0xcc16, 0x21, 0 + .dw 0x0511, 0xcc16, 0x0511, 0xcc16, 0x21, 0 + .dw 0x0513, 0xcc16, 0x053f, 0xcc16, 0x21, 0 + .dw 0x0541, 0xcc16, 0x0541, 0xcc16, 0x21, 0 + .dw 0x0543, 0xcc16, 0x054f, 0xcc16, 0x21, 0 + .dw 0x0551, 0xcc16, 0x0551, 0xcc16, 0x21, 0 + .dw 0x0553, 0xcc16, 0x057f, 0xcc16, 0x21, 0 + .dw 0x0581, 0xcc16, 0x0581, 0xcc16, 0x21, 0 + .dw 0x0583, 0xcc16, 0x058f, 0xcc16, 0x21, 0 + .dw 0x0591, 0xcc16, 0x0591, 0xcc16, 0x21, 0 + .dw 0x0593, 0xcc16, 0x05bf, 0xcc16, 0x21, 0 + .dw 0x05c1, 0xcc16, 0x05c1, 0xcc16, 0x21, 0 + .dw 0x05c3, 0xcc16, 0x05cf, 0xcc16, 0x21, 0 + .dw 0x05d1, 0xcc16, 0x05d1, 0xcc16, 0x21, 0 + .dw 0x05d3, 0xcc16, 0x05ff, 0xcc16, 0x21, 0 + .dw 0x0601, 0xcc16, 0x0601, 0xcc16, 0x21, 0 + .dw 0x0603, 0xcc16, 0x060f, 0xcc16, 0x21, 0 + .dw 0x0611, 0xcc16, 0x0611, 0xcc16, 0x21, 0 + .dw 0x0613, 0xcc16, 0x063f, 0xcc16, 0x21, 0 + .dw 0x0641, 0xcc16, 0x0641, 0xcc16, 0x21, 0 + .dw 0x0643, 0xcc16, 0x064f, 0xcc16, 0x21, 0 + .dw 0x0651, 0xcc16, 0x0651, 0xcc16, 0x21, 0 + .dw 0x0653, 0xcc16, 0x067f, 0xcc16, 0x21, 0 + .dw 0x0681, 0xcc16, 0x0681, 0xcc16, 0x21, 0 + .dw 0x0683, 0xcc16, 0x068f, 0xcc16, 0x21, 0 + .dw 0x0691, 0xcc16, 0x0691, 0xcc16, 0x21, 0 + .dw 0x0693, 0xcc16, 0x06bf, 0xcc16, 0x21, 0 + .dw 0x06c1, 0xcc16, 0x06c1, 0xcc16, 0x21, 0 + .dw 0x06c3, 0xcc16, 0x06cf, 0xcc16, 0x21, 0 + .dw 0x06d1, 0xcc16, 0x06d1, 0xcc16, 0x21, 0 + .dw 0x06d3, 0xcc16, 0x06ff, 0xcc16, 0x21, 0 + .dw 0x0701, 0xcc16, 0x0701, 0xcc16, 0x21, 0 + .dw 0x0703, 0xcc16, 0x070f, 0xcc16, 0x21, 0 + .dw 0x0711, 0xcc16, 0x0711, 0xcc16, 0x21, 0 + .dw 0x0713, 0xcc16, 0x073f, 0xcc16, 0x21, 0 + .dw 0x0741, 0xcc16, 0x0741, 0xcc16, 0x21, 0 + .dw 0x0743, 0xcc16, 0x074f, 0xcc16, 0x21, 0 + .dw 0x0751, 0xcc16, 0x0751, 0xcc16, 0x21, 0 + .dw 0x0753, 0xcc16, 0x077f, 0xcc16, 0x21, 0 + .dw 0x0781, 0xcc16, 0x0781, 0xcc16, 0x21, 0 + .dw 0x0783, 0xcc16, 0x078f, 0xcc16, 0x21, 0 + .dw 0x0791, 0xcc16, 0x0791, 0xcc16, 0x21, 0 + .dw 0x0793, 0xcc16, 0x07bf, 0xcc16, 0x21, 0 + .dw 0x07c1, 0xcc16, 0x07c1, 0xcc16, 0x21, 0 + .dw 0x07c3, 0xcc16, 0x07cf, 0xcc16, 0x21, 0 + .dw 0x07d1, 0xcc16, 0x07d1, 0xcc16, 0x21, 0 + .dw 0x07d3, 0xcc16, 0x07ff, 0xcc16, 0x21, 0 + .dw 0x0801, 0xcc16, 0x0801, 0xcc16, 0x21, 0 + .dw 0x0803, 0xcc16, 0x080f, 0xcc16, 0x21, 0 + .dw 0x0811, 0xcc16, 0x0811, 0xcc16, 0x21, 0 + .dw 0x0813, 0xcc16, 0x083f, 0xcc16, 0x21, 0 + .dw 0x0841, 0xcc16, 0x0841, 0xcc16, 0x21, 0 + .dw 0x0843, 0xcc16, 0x084f, 0xcc16, 0x21, 0 + .dw 0x0851, 0xcc16, 0x0851, 0xcc16, 0x21, 0 + .dw 0x0853, 0xcc16, 0x087f, 0xcc16, 0x21, 0 + .dw 0x0881, 0xcc16, 0x0881, 0xcc16, 0x21, 0 + .dw 0x0883, 0xcc16, 0x088f, 0xcc16, 0x21, 0 + .dw 0x0891, 0xcc16, 0x0891, 0xcc16, 0x21, 0 + .dw 0x0893, 0xcc16, 0x08bf, 0xcc16, 0x21, 0 + .dw 0x08c1, 0xcc16, 0x08c1, 0xcc16, 0x21, 0 + .dw 0x08c3, 0xcc16, 0x08cf, 0xcc16, 0x21, 0 + .dw 0x08d1, 0xcc16, 0x08d1, 0xcc16, 0x21, 0 + .dw 0x08d3, 0xcc16, 0x08ff, 0xcc16, 0x21, 0 + .dw 0x0901, 0xcc16, 0x0901, 0xcc16, 0x21, 0 + .dw 0x0903, 0xcc16, 0x090f, 0xcc16, 0x21, 0 + .dw 0x0911, 0xcc16, 0x0911, 0xcc16, 0x21, 0 + .dw 0x0913, 0xcc16, 0x093f, 0xcc16, 0x21, 0 + .dw 0x0941, 0xcc16, 0x0941, 0xcc16, 0x21, 0 + .dw 0x0943, 0xcc16, 0x094f, 0xcc16, 0x21, 0 + .dw 0x0951, 0xcc16, 0x0951, 0xcc16, 0x21, 0 + .dw 0x0953, 0xcc16, 0x097f, 0xcc16, 0x21, 0 + .dw 0x0981, 0xcc16, 0x0981, 0xcc16, 0x21, 0 + .dw 0x0983, 0xcc16, 0x098f, 0xcc16, 0x21, 0 + .dw 0x0991, 0xcc16, 0x0991, 0xcc16, 0x21, 0 + .dw 0x0993, 0xcc16, 0x09bf, 0xcc16, 0x21, 0 + .dw 0x09c1, 0xcc16, 0x09c1, 0xcc16, 0x21, 0 + .dw 0x09c3, 0xcc16, 0x09cf, 0xcc16, 0x21, 0 + .dw 0x09d1, 0xcc16, 0x09d1, 0xcc16, 0x21, 0 + .dw 0x09d3, 0xcc16, 0x09ff, 0xcc16, 0x21, 0 + .dw 0x0a01, 0xcc16, 0x0a01, 0xcc16, 0x21, 0 + .dw 0x0a03, 0xcc16, 0x0a0f, 0xcc16, 0x21, 0 + .dw 0x0a11, 0xcc16, 0x0a11, 0xcc16, 0x21, 0 + .dw 0x0a13, 0xcc16, 0x0a3f, 0xcc16, 0x21, 0 + .dw 0x0a41, 0xcc16, 0x0a41, 0xcc16, 0x21, 0 + .dw 0x0a43, 0xcc16, 0x0a4f, 0xcc16, 0x21, 0 + .dw 0x0a51, 0xcc16, 0x0a51, 0xcc16, 0x21, 0 + .dw 0x0a53, 0xcc16, 0x0a7f, 0xcc16, 0x21, 0 + .dw 0x0a81, 0xcc16, 0x0a81, 0xcc16, 0x21, 0 + .dw 0x0a83, 0xcc16, 0x0a8f, 0xcc16, 0x21, 0 + .dw 0x0a91, 0xcc16, 0x0a91, 0xcc16, 0x21, 0 + .dw 0x0a93, 0xcc16, 0x0abf, 0xcc16, 0x21, 0 + .dw 0x0ac1, 0xcc16, 0x0ac1, 0xcc16, 0x21, 0 + .dw 0x0ac3, 0xcc16, 0x0acf, 0xcc16, 0x21, 0 + .dw 0x0ad1, 0xcc16, 0x0ad1, 0xcc16, 0x21, 0 + .dw 0x0ad3, 0xcc16, 0x0aff, 0xcc16, 0x21, 0 + .dw 0x0b01, 0xcc16, 0x0b01, 0xcc16, 0x21, 0 + .dw 0x0b03, 0xcc16, 0x0b0f, 0xcc16, 0x21, 0 + .dw 0x0b11, 0xcc16, 0x0b11, 0xcc16, 0x21, 0 + .dw 0x0b13, 0xcc16, 0x0b3f, 0xcc16, 0x21, 0 + .dw 0x0b41, 0xcc16, 0x0b41, 0xcc16, 0x21, 0 + .dw 0x0b43, 0xcc16, 0x0b4f, 0xcc16, 0x21, 0 + .dw 0x0b51, 0xcc16, 0x0b51, 0xcc16, 0x21, 0 + .dw 0x0b53, 0xcc16, 0x0b7f, 0xcc16, 0x21, 0 + .dw 0x0b81, 0xcc16, 0x0b81, 0xcc16, 0x21, 0 + .dw 0x0b83, 0xcc16, 0x0b8f, 0xcc16, 0x21, 0 + .dw 0x0b91, 0xcc16, 0x0b91, 0xcc16, 0x21, 0 + .dw 0x0b93, 0xcc16, 0x0bbf, 0xcc16, 0x21, 0 + .dw 0x0bc1, 0xcc16, 0x0bc1, 0xcc16, 0x21, 0 + .dw 0x0bc3, 0xcc16, 0x0bcf, 0xcc16, 0x21, 0 + .dw 0x0bd1, 0xcc16, 0x0bd1, 0xcc16, 0x21, 0 + .dw 0x0bd3, 0xcc16, 0x0bff, 0xcc16, 0x21, 0 + .dw 0x0c01, 0xcc16, 0x0c01, 0xcc16, 0x21, 0 + .dw 0x0c03, 0xcc16, 0x0c0f, 0xcc16, 0x21, 0 + .dw 0x0c11, 0xcc16, 0x0c11, 0xcc16, 0x21, 0 + .dw 0x0c13, 0xcc16, 0x0c3f, 0xcc16, 0x21, 0 + .dw 0x0c41, 0xcc16, 0x0c41, 0xcc16, 0x21, 0 + .dw 0x0c43, 0xcc16, 0x0c4f, 0xcc16, 0x21, 0 + .dw 0x0c51, 0xcc16, 0x0c51, 0xcc16, 0x21, 0 + .dw 0x0c53, 0xcc16, 0x0c7f, 0xcc16, 0x21, 0 + .dw 0x0c81, 0xcc16, 0x0c81, 0xcc16, 0x21, 0 + .dw 0x0c83, 0xcc16, 0x0c8f, 0xcc16, 0x21, 0 + .dw 0x0c91, 0xcc16, 0x0c91, 0xcc16, 0x21, 0 + .dw 0x0c93, 0xcc16, 0x0cbf, 0xcc16, 0x21, 0 + .dw 0x0cc1, 0xcc16, 0x0cc1, 0xcc16, 0x21, 0 + .dw 0x0cc3, 0xcc16, 0x0ccf, 0xcc16, 0x21, 0 + .dw 0x0cd1, 0xcc16, 0x0cd1, 0xcc16, 0x21, 0 + .dw 0x0cd3, 0xcc16, 0x0cff, 0xcc16, 0x21, 0 + .dw 0x0d01, 0xcc16, 0x0d01, 0xcc16, 0x21, 0 + .dw 0x0d03, 0xcc16, 0x0d0f, 0xcc16, 0x21, 0 + .dw 0x0d11, 0xcc16, 0x0d11, 0xcc16, 0x21, 0 + .dw 0x0d13, 0xcc16, 0x0d3f, 0xcc16, 0x21, 0 + .dw 0x0d41, 0xcc16, 0x0d41, 0xcc16, 0x21, 0 + .dw 0x0d43, 0xcc16, 0x0d4f, 0xcc16, 0x21, 0 + .dw 0x0d51, 0xcc16, 0x0d51, 0xcc16, 0x21, 0 + .dw 0x0d53, 0xcc16, 0x0d7f, 0xcc16, 0x21, 0 + .dw 0x0d81, 0xcc16, 0x0d81, 0xcc16, 0x21, 0 + .dw 0x0d83, 0xcc16, 0x0d8f, 0xcc16, 0x21, 0 + .dw 0x0d91, 0xcc16, 0x0d91, 0xcc16, 0x21, 0 + .dw 0x0d93, 0xcc16, 0x0dbf, 0xcc16, 0x21, 0 + .dw 0x0dc1, 0xcc16, 0x0dc1, 0xcc16, 0x21, 0 + .dw 0x0dc3, 0xcc16, 0x0dcf, 0xcc16, 0x21, 0 + .dw 0x0dd1, 0xcc16, 0x0dd1, 0xcc16, 0x21, 0 + .dw 0x0dd3, 0xcc16, 0x0dff, 0xcc16, 0x21, 0 + .dw 0x0e01, 0xcc16, 0x0e01, 0xcc16, 0x21, 0 + .dw 0x0e03, 0xcc16, 0x0e0f, 0xcc16, 0x21, 0 + .dw 0x0e11, 0xcc16, 0x0e11, 0xcc16, 0x21, 0 + .dw 0x0e13, 0xcc16, 0x0e3f, 0xcc16, 0x21, 0 + .dw 0x0e41, 0xcc16, 0x0e41, 0xcc16, 0x21, 0 + .dw 0x0e43, 0xcc16, 0x0e4f, 0xcc16, 0x21, 0 + .dw 0x0e51, 0xcc16, 0x0e51, 0xcc16, 0x21, 0 + .dw 0x0e53, 0xcc16, 0x0e7f, 0xcc16, 0x21, 0 + .dw 0x0e81, 0xcc16, 0x0e81, 0xcc16, 0x21, 0 + .dw 0x0e83, 0xcc16, 0x0e8f, 0xcc16, 0x21, 0 + .dw 0x0e91, 0xcc16, 0x0e91, 0xcc16, 0x21, 0 + .dw 0x0e93, 0xcc16, 0x0ebf, 0xcc16, 0x21, 0 + .dw 0x0ec1, 0xcc16, 0x0ec1, 0xcc16, 0x21, 0 + .dw 0x0ec3, 0xcc16, 0x0ecf, 0xcc16, 0x21, 0 + .dw 0x0ed1, 0xcc16, 0x0ed1, 0xcc16, 0x21, 0 + .dw 0x0ed3, 0xcc16, 0x0eff, 0xcc16, 0x21, 0 + .dw 0x0f01, 0xcc16, 0x0f01, 0xcc16, 0x21, 0 + .dw 0x0f03, 0xcc16, 0x0f0f, 0xcc16, 0x21, 0 + .dw 0x0f11, 0xcc16, 0x0f11, 0xcc16, 0x21, 0 + .dw 0x0f13, 0xcc16, 0x0f3f, 0xcc16, 0x21, 0 + .dw 0x0f41, 0xcc16, 0x0f41, 0xcc16, 0x21, 0 + .dw 0x0f43, 0xcc16, 0x0f4f, 0xcc16, 0x21, 0 + .dw 0x0f51, 0xcc16, 0x0f51, 0xcc16, 0x21, 0 + .dw 0x0f53, 0xcc16, 0x0f7f, 0xcc16, 0x21, 0 + .dw 0x0f81, 0xcc16, 0x0f81, 0xcc16, 0x21, 0 + .dw 0x0f83, 0xcc16, 0x0f8f, 0xcc16, 0x21, 0 + .dw 0x0f91, 0xcc16, 0x0f91, 0xcc16, 0x21, 0 + .dw 0x0f93, 0xcc16, 0x0fbf, 0xcc16, 0x21, 0 + .dw 0x0fc1, 0xcc16, 0x0fc1, 0xcc16, 0x21, 0 + .dw 0x0fc3, 0xcc16, 0x0fcf, 0xcc16, 0x21, 0 + .dw 0x0fd1, 0xcc16, 0x0fd1, 0xcc16, 0x21, 0 + .dw 0x0fd3, 0xcc16, 0x1fff, 0xcc16, 0x21, 0 + .dw 0x2001, 0xcc16, 0x2001, 0xcc16, 0x21, 0 + .dw 0x2003, 0xcc16, 0x200f, 0xcc16, 0x21, 0 + .dw 0x2011, 0xcc16, 0x2011, 0xcc16, 0x21, 0 + .dw 0x2013, 0xcc16, 0x203f, 0xcc16, 0x21, 0 + .dw 0x2041, 0xcc16, 0x2041, 0xcc16, 0x21, 0 + .dw 0x2043, 0xcc16, 0x204f, 0xcc16, 0x21, 0 + .dw 0x2051, 0xcc16, 0x2051, 0xcc16, 0x21, 0 + .dw 0x2053, 0xcc16, 0x207f, 0xcc16, 0x21, 0 + .dw 0x2081, 0xcc16, 0x2081, 0xcc16, 0x21, 0 + .dw 0x2083, 0xcc16, 0x208f, 0xcc16, 0x21, 0 + .dw 0x2091, 0xcc16, 0x2091, 0xcc16, 0x21, 0 + .dw 0x2093, 0xcc16, 0x20bf, 0xcc16, 0x21, 0 + .dw 0x20c1, 0xcc16, 0x20c1, 0xcc16, 0x21, 0 + .dw 0x20c3, 0xcc16, 0x20cf, 0xcc16, 0x21, 0 + .dw 0x20d1, 0xcc16, 0x20d1, 0xcc16, 0x21, 0 + .dw 0x20d3, 0xcc16, 0x20ff, 0xcc16, 0x21, 0 + .dw 0x2101, 0xcc16, 0x2101, 0xcc16, 0x21, 0 + .dw 0x2103, 0xcc16, 0x210f, 0xcc16, 0x21, 0 + .dw 0x2111, 0xcc16, 0x2111, 0xcc16, 0x21, 0 + .dw 0x2113, 0xcc16, 0x213f, 0xcc16, 0x21, 0 + .dw 0x2141, 0xcc16, 0x2141, 0xcc16, 0x21, 0 + .dw 0x2143, 0xcc16, 0x214f, 0xcc16, 0x21, 0 + .dw 0x2151, 0xcc16, 0x2151, 0xcc16, 0x21, 0 + .dw 0x2153, 0xcc16, 0x217f, 0xcc16, 0x21, 0 + .dw 0x2181, 0xcc16, 0x2181, 0xcc16, 0x21, 0 + .dw 0x2183, 0xcc16, 0x218f, 0xcc16, 0x21, 0 + .dw 0x2191, 0xcc16, 0x2191, 0xcc16, 0x21, 0 + .dw 0x2193, 0xcc16, 0x21bf, 0xcc16, 0x21, 0 + .dw 0x21c1, 0xcc16, 0x21c1, 0xcc16, 0x21, 0 + .dw 0x21c3, 0xcc16, 0x21cf, 0xcc16, 0x21, 0 + .dw 0x21d1, 0xcc16, 0x21d1, 0xcc16, 0x21, 0 + .dw 0x21d3, 0xcc16, 0x21ff, 0xcc16, 0x21, 0 + .dw 0x2201, 0xcc16, 0x2201, 0xcc16, 0x21, 0 + .dw 0x2203, 0xcc16, 0x220f, 0xcc16, 0x21, 0 + .dw 0x2211, 0xcc16, 0x2211, 0xcc16, 0x21, 0 + .dw 0x2213, 0xcc16, 0x223f, 0xcc16, 0x21, 0 + .dw 0x2241, 0xcc16, 0x2241, 0xcc16, 0x21, 0 + .dw 0x2243, 0xcc16, 0x224f, 0xcc16, 0x21, 0 + .dw 0x2251, 0xcc16, 0x2251, 0xcc16, 0x21, 0 + .dw 0x2253, 0xcc16, 0x227f, 0xcc16, 0x21, 0 + .dw 0x2281, 0xcc16, 0x2281, 0xcc16, 0x21, 0 + .dw 0x2283, 0xcc16, 0x228f, 0xcc16, 0x21, 0 + .dw 0x2291, 0xcc16, 0x2291, 0xcc16, 0x21, 0 + .dw 0x2293, 0xcc16, 0x22bf, 0xcc16, 0x21, 0 + .dw 0x22c1, 0xcc16, 0x22c1, 0xcc16, 0x21, 0 + .dw 0x22c3, 0xcc16, 0x22cf, 0xcc16, 0x21, 0 + .dw 0x22d1, 0xcc16, 0x22d1, 0xcc16, 0x21, 0 + .dw 0x22d3, 0xcc16, 0x22ff, 0xcc16, 0x21, 0 + .dw 0x2301, 0xcc16, 0x2301, 0xcc16, 0x21, 0 + .dw 0x2303, 0xcc16, 0x230f, 0xcc16, 0x21, 0 + .dw 0x2311, 0xcc16, 0x2311, 0xcc16, 0x21, 0 + .dw 0x2313, 0xcc16, 0x233f, 0xcc16, 0x21, 0 + .dw 0x2341, 0xcc16, 0x2341, 0xcc16, 0x21, 0 + .dw 0x2343, 0xcc16, 0x234f, 0xcc16, 0x21, 0 + .dw 0x2351, 0xcc16, 0x2351, 0xcc16, 0x21, 0 + .dw 0x2353, 0xcc16, 0x237f, 0xcc16, 0x21, 0 + .dw 0x2381, 0xcc16, 0x2381, 0xcc16, 0x21, 0 + .dw 0x2383, 0xcc16, 0x238f, 0xcc16, 0x21, 0 + .dw 0x2391, 0xcc16, 0x2391, 0xcc16, 0x21, 0 + .dw 0x2393, 0xcc16, 0x23bf, 0xcc16, 0x21, 0 + .dw 0x23c1, 0xcc16, 0x23c1, 0xcc16, 0x21, 0 + .dw 0x23c3, 0xcc16, 0x23cf, 0xcc16, 0x21, 0 + .dw 0x23d1, 0xcc16, 0x23d1, 0xcc16, 0x21, 0 + .dw 0x23d3, 0xcc16, 0x23ff, 0xcc16, 0x21, 0 + .dw 0x2401, 0xcc16, 0x2401, 0xcc16, 0x21, 0 + .dw 0x2403, 0xcc16, 0x240f, 0xcc16, 0x21, 0 + .dw 0x2411, 0xcc16, 0x2411, 0xcc16, 0x21, 0 + .dw 0x2413, 0xcc16, 0x243f, 0xcc16, 0x21, 0 + .dw 0x2441, 0xcc16, 0x2441, 0xcc16, 0x21, 0 + .dw 0x2443, 0xcc16, 0x244f, 0xcc16, 0x21, 0 + .dw 0x2451, 0xcc16, 0x2451, 0xcc16, 0x21, 0 + .dw 0x2453, 0xcc16, 0x247f, 0xcc16, 0x21, 0 + .dw 0x2481, 0xcc16, 0x2481, 0xcc16, 0x21, 0 + .dw 0x2483, 0xcc16, 0x248f, 0xcc16, 0x21, 0 + .dw 0x2491, 0xcc16, 0x2491, 0xcc16, 0x21, 0 + .dw 0x2493, 0xcc16, 0x24bf, 0xcc16, 0x21, 0 + .dw 0x24c1, 0xcc16, 0x24c1, 0xcc16, 0x21, 0 + .dw 0x24c3, 0xcc16, 0x24cf, 0xcc16, 0x21, 0 + .dw 0x24d1, 0xcc16, 0x24d1, 0xcc16, 0x21, 0 + .dw 0x24d3, 0xcc16, 0x24ff, 0xcc16, 0x21, 0 + .dw 0x2501, 0xcc16, 0x2501, 0xcc16, 0x21, 0 + .dw 0x2503, 0xcc16, 0x250f, 0xcc16, 0x21, 0 + .dw 0x2511, 0xcc16, 0x2511, 0xcc16, 0x21, 0 + .dw 0x2513, 0xcc16, 0x253f, 0xcc16, 0x21, 0 + .dw 0x2541, 0xcc16, 0x2541, 0xcc16, 0x21, 0 + .dw 0x2543, 0xcc16, 0x254f, 0xcc16, 0x21, 0 + .dw 0x2551, 0xcc16, 0x2551, 0xcc16, 0x21, 0 + .dw 0x2553, 0xcc16, 0x257f, 0xcc16, 0x21, 0 + .dw 0x2581, 0xcc16, 0x2581, 0xcc16, 0x21, 0 + .dw 0x2583, 0xcc16, 0x258f, 0xcc16, 0x21, 0 + .dw 0x2591, 0xcc16, 0x2591, 0xcc16, 0x21, 0 + .dw 0x2593, 0xcc16, 0x25bf, 0xcc16, 0x21, 0 + .dw 0x25c1, 0xcc16, 0x25c1, 0xcc16, 0x21, 0 + .dw 0x25c3, 0xcc16, 0x25cf, 0xcc16, 0x21, 0 + .dw 0x25d1, 0xcc16, 0x25d1, 0xcc16, 0x21, 0 + .dw 0x25d3, 0xcc16, 0x25ff, 0xcc16, 0x21, 0 + .dw 0x2601, 0xcc16, 0x2601, 0xcc16, 0x21, 0 + .dw 0x2603, 0xcc16, 0x260f, 0xcc16, 0x21, 0 + .dw 0x2611, 0xcc16, 0x2611, 0xcc16, 0x21, 0 + .dw 0x2613, 0xcc16, 0x263f, 0xcc16, 0x21, 0 + .dw 0x2641, 0xcc16, 0x2641, 0xcc16, 0x21, 0 + .dw 0x2643, 0xcc16, 0x264f, 0xcc16, 0x21, 0 + .dw 0x2651, 0xcc16, 0x2651, 0xcc16, 0x21, 0 + .dw 0x2653, 0xcc16, 0x267f, 0xcc16, 0x21, 0 + .dw 0x2681, 0xcc16, 0x2681, 0xcc16, 0x21, 0 + .dw 0x2683, 0xcc16, 0x268f, 0xcc16, 0x21, 0 + .dw 0x2691, 0xcc16, 0x2691, 0xcc16, 0x21, 0 + .dw 0x2693, 0xcc16, 0x26bf, 0xcc16, 0x21, 0 + .dw 0x26c1, 0xcc16, 0x26c1, 0xcc16, 0x21, 0 + .dw 0x26c3, 0xcc16, 0x26cf, 0xcc16, 0x21, 0 + .dw 0x26d1, 0xcc16, 0x26d1, 0xcc16, 0x21, 0 + .dw 0x26d3, 0xcc16, 0x26ff, 0xcc16, 0x21, 0 + .dw 0x2701, 0xcc16, 0x2701, 0xcc16, 0x21, 0 + .dw 0x2703, 0xcc16, 0x270f, 0xcc16, 0x21, 0 + .dw 0x2711, 0xcc16, 0x2711, 0xcc16, 0x21, 0 + .dw 0x2713, 0xcc16, 0x273f, 0xcc16, 0x21, 0 + .dw 0x2741, 0xcc16, 0x2741, 0xcc16, 0x21, 0 + .dw 0x2743, 0xcc16, 0x274f, 0xcc16, 0x21, 0 + .dw 0x2751, 0xcc16, 0x2751, 0xcc16, 0x21, 0 + .dw 0x2753, 0xcc16, 0x277f, 0xcc16, 0x21, 0 + .dw 0x2781, 0xcc16, 0x2781, 0xcc16, 0x21, 0 + .dw 0x2783, 0xcc16, 0x278f, 0xcc16, 0x21, 0 + .dw 0x2791, 0xcc16, 0x2791, 0xcc16, 0x21, 0 + .dw 0x2793, 0xcc16, 0x27bf, 0xcc16, 0x21, 0 + .dw 0x27c1, 0xcc16, 0x27c1, 0xcc16, 0x21, 0 + .dw 0x27c3, 0xcc16, 0x27cf, 0xcc16, 0x21, 0 + .dw 0x27d1, 0xcc16, 0x27d1, 0xcc16, 0x21, 0 + .dw 0x27d3, 0xcc16, 0x27ff, 0xcc16, 0x21, 0 + .dw 0x2801, 0xcc16, 0x2801, 0xcc16, 0x21, 0 + .dw 0x2803, 0xcc16, 0x280f, 0xcc16, 0x21, 0 + .dw 0x2811, 0xcc16, 0x2811, 0xcc16, 0x21, 0 + .dw 0x2813, 0xcc16, 0x283f, 0xcc16, 0x21, 0 + .dw 0x2841, 0xcc16, 0x2841, 0xcc16, 0x21, 0 + .dw 0x2843, 0xcc16, 0x284f, 0xcc16, 0x21, 0 + .dw 0x2851, 0xcc16, 0x2851, 0xcc16, 0x21, 0 + .dw 0x2853, 0xcc16, 0x287f, 0xcc16, 0x21, 0 + .dw 0x2881, 0xcc16, 0x2881, 0xcc16, 0x21, 0 + .dw 0x2883, 0xcc16, 0x288f, 0xcc16, 0x21, 0 + .dw 0x2891, 0xcc16, 0x2891, 0xcc16, 0x21, 0 + .dw 0x2893, 0xcc16, 0x28bf, 0xcc16, 0x21, 0 + .dw 0x28c1, 0xcc16, 0x28c1, 0xcc16, 0x21, 0 + .dw 0x28c3, 0xcc16, 0x28cf, 0xcc16, 0x21, 0 + .dw 0x28d1, 0xcc16, 0x28d1, 0xcc16, 0x21, 0 + .dw 0x28d3, 0xcc16, 0x28ff, 0xcc16, 0x21, 0 + .dw 0x2901, 0xcc16, 0x2901, 0xcc16, 0x21, 0 + .dw 0x2903, 0xcc16, 0x290f, 0xcc16, 0x21, 0 + .dw 0x2911, 0xcc16, 0x2911, 0xcc16, 0x21, 0 + .dw 0x2913, 0xcc16, 0x293f, 0xcc16, 0x21, 0 + .dw 0x2941, 0xcc16, 0x2941, 0xcc16, 0x21, 0 + .dw 0x2943, 0xcc16, 0x294f, 0xcc16, 0x21, 0 + .dw 0x2951, 0xcc16, 0x2951, 0xcc16, 0x21, 0 + .dw 0x2953, 0xcc16, 0x297f, 0xcc16, 0x21, 0 + .dw 0x2981, 0xcc16, 0x2981, 0xcc16, 0x21, 0 + .dw 0x2983, 0xcc16, 0x298f, 0xcc16, 0x21, 0 + .dw 0x2991, 0xcc16, 0x2991, 0xcc16, 0x21, 0 + .dw 0x2993, 0xcc16, 0x29bf, 0xcc16, 0x21, 0 + .dw 0x29c1, 0xcc16, 0x29c1, 0xcc16, 0x21, 0 + .dw 0x29c3, 0xcc16, 0x29cf, 0xcc16, 0x21, 0 + .dw 0x29d1, 0xcc16, 0x29d1, 0xcc16, 0x21, 0 + .dw 0x29d3, 0xcc16, 0x29ff, 0xcc16, 0x21, 0 + .dw 0x2a01, 0xcc16, 0x2a01, 0xcc16, 0x21, 0 + .dw 0x2a03, 0xcc16, 0x2a0f, 0xcc16, 0x21, 0 + .dw 0x2a11, 0xcc16, 0x2a11, 0xcc16, 0x21, 0 + .dw 0x2a13, 0xcc16, 0x2a3f, 0xcc16, 0x21, 0 + .dw 0x2a41, 0xcc16, 0x2a41, 0xcc16, 0x21, 0 + .dw 0x2a43, 0xcc16, 0x2a4f, 0xcc16, 0x21, 0 + .dw 0x2a51, 0xcc16, 0x2a51, 0xcc16, 0x21, 0 + .dw 0x2a53, 0xcc16, 0x2a7f, 0xcc16, 0x21, 0 + .dw 0x2a81, 0xcc16, 0x2a81, 0xcc16, 0x21, 0 + .dw 0x2a83, 0xcc16, 0x2a8f, 0xcc16, 0x21, 0 + .dw 0x2a91, 0xcc16, 0x2a91, 0xcc16, 0x21, 0 + .dw 0x2a93, 0xcc16, 0x2abf, 0xcc16, 0x21, 0 + .dw 0x2ac1, 0xcc16, 0x2ac1, 0xcc16, 0x21, 0 + .dw 0x2ac3, 0xcc16, 0x2acf, 0xcc16, 0x21, 0 + .dw 0x2ad1, 0xcc16, 0x2ad1, 0xcc16, 0x21, 0 + .dw 0x2ad3, 0xcc16, 0x2aff, 0xcc16, 0x21, 0 + .dw 0x2b01, 0xcc16, 0x2b01, 0xcc16, 0x21, 0 + .dw 0x2b03, 0xcc16, 0x2b0f, 0xcc16, 0x21, 0 + .dw 0x2b11, 0xcc16, 0x2b11, 0xcc16, 0x21, 0 + .dw 0x2b13, 0xcc16, 0x2b3f, 0xcc16, 0x21, 0 + .dw 0x2b41, 0xcc16, 0x2b41, 0xcc16, 0x21, 0 + .dw 0x2b43, 0xcc16, 0x2b4f, 0xcc16, 0x21, 0 + .dw 0x2b51, 0xcc16, 0x2b51, 0xcc16, 0x21, 0 + .dw 0x2b53, 0xcc16, 0x2b7f, 0xcc16, 0x21, 0 + .dw 0x2b81, 0xcc16, 0x2b81, 0xcc16, 0x21, 0 + .dw 0x2b83, 0xcc16, 0x2b8f, 0xcc16, 0x21, 0 + .dw 0x2b91, 0xcc16, 0x2b91, 0xcc16, 0x21, 0 + .dw 0x2b93, 0xcc16, 0x2bbf, 0xcc16, 0x21, 0 + .dw 0x2bc1, 0xcc16, 0x2bc1, 0xcc16, 0x21, 0 + .dw 0x2bc3, 0xcc16, 0x2bcf, 0xcc16, 0x21, 0 + .dw 0x2bd1, 0xcc16, 0x2bd1, 0xcc16, 0x21, 0 + .dw 0x2bd3, 0xcc16, 0x2bff, 0xcc16, 0x21, 0 + .dw 0x2c01, 0xcc16, 0x2c01, 0xcc16, 0x21, 0 + .dw 0x2c03, 0xcc16, 0x2c0f, 0xcc16, 0x21, 0 + .dw 0x2c11, 0xcc16, 0x2c11, 0xcc16, 0x21, 0 + .dw 0x2c13, 0xcc16, 0x2c3f, 0xcc16, 0x21, 0 + .dw 0x2c41, 0xcc16, 0x2c41, 0xcc16, 0x21, 0 + .dw 0x2c43, 0xcc16, 0x2c4f, 0xcc16, 0x21, 0 + .dw 0x2c51, 0xcc16, 0x2c51, 0xcc16, 0x21, 0 + .dw 0x2c53, 0xcc16, 0x2c7f, 0xcc16, 0x21, 0 + .dw 0x2c81, 0xcc16, 0x2c81, 0xcc16, 0x21, 0 + .dw 0x2c83, 0xcc16, 0x2c8f, 0xcc16, 0x21, 0 + .dw 0x2c91, 0xcc16, 0x2c91, 0xcc16, 0x21, 0 + .dw 0x2c93, 0xcc16, 0x2cbf, 0xcc16, 0x21, 0 + .dw 0x2cc1, 0xcc16, 0x2cc1, 0xcc16, 0x21, 0 + .dw 0x2cc3, 0xcc16, 0x2ccf, 0xcc16, 0x21, 0 + .dw 0x2cd1, 0xcc16, 0x2cd1, 0xcc16, 0x21, 0 + .dw 0x2cd3, 0xcc16, 0x2cff, 0xcc16, 0x21, 0 + .dw 0x2d01, 0xcc16, 0x2d01, 0xcc16, 0x21, 0 + .dw 0x2d03, 0xcc16, 0x2d0f, 0xcc16, 0x21, 0 + .dw 0x2d11, 0xcc16, 0x2d11, 0xcc16, 0x21, 0 + .dw 0x2d13, 0xcc16, 0x2d3f, 0xcc16, 0x21, 0 + .dw 0x2d41, 0xcc16, 0x2d41, 0xcc16, 0x21, 0 + .dw 0x2d43, 0xcc16, 0x2d4f, 0xcc16, 0x21, 0 + .dw 0x2d51, 0xcc16, 0x2d51, 0xcc16, 0x21, 0 + .dw 0x2d53, 0xcc16, 0x2d7f, 0xcc16, 0x21, 0 + .dw 0x2d81, 0xcc16, 0x2d81, 0xcc16, 0x21, 0 + .dw 0x2d83, 0xcc16, 0x2d8f, 0xcc16, 0x21, 0 + .dw 0x2d91, 0xcc16, 0x2d91, 0xcc16, 0x21, 0 + .dw 0x2d93, 0xcc16, 0x2dbf, 0xcc16, 0x21, 0 + .dw 0x2dc1, 0xcc16, 0x2dc1, 0xcc16, 0x21, 0 + .dw 0x2dc3, 0xcc16, 0x2dcf, 0xcc16, 0x21, 0 + .dw 0x2dd1, 0xcc16, 0x2dd1, 0xcc16, 0x21, 0 + .dw 0x2dd3, 0xcc16, 0x2dff, 0xcc16, 0x21, 0 + .dw 0x2e01, 0xcc16, 0x2e01, 0xcc16, 0x21, 0 + .dw 0x2e03, 0xcc16, 0x2e0f, 0xcc16, 0x21, 0 + .dw 0x2e11, 0xcc16, 0x2e11, 0xcc16, 0x21, 0 + .dw 0x2e13, 0xcc16, 0x2e3f, 0xcc16, 0x21, 0 + .dw 0x2e41, 0xcc16, 0x2e41, 0xcc16, 0x21, 0 + .dw 0x2e43, 0xcc16, 0x2e4f, 0xcc16, 0x21, 0 + .dw 0x2e51, 0xcc16, 0x2e51, 0xcc16, 0x21, 0 + .dw 0x2e53, 0xcc16, 0x2e7f, 0xcc16, 0x21, 0 + .dw 0x2e81, 0xcc16, 0x2e81, 0xcc16, 0x21, 0 + .dw 0x2e83, 0xcc16, 0x2e8f, 0xcc16, 0x21, 0 + .dw 0x2e91, 0xcc16, 0x2e91, 0xcc16, 0x21, 0 + .dw 0x2e93, 0xcc16, 0x2ebf, 0xcc16, 0x21, 0 + .dw 0x2ec1, 0xcc16, 0x2ec1, 0xcc16, 0x21, 0 + .dw 0x2ec3, 0xcc16, 0x2ecf, 0xcc16, 0x21, 0 + .dw 0x2ed1, 0xcc16, 0x2ed1, 0xcc16, 0x21, 0 + .dw 0x2ed3, 0xcc16, 0x2eff, 0xcc16, 0x21, 0 + .dw 0x2f01, 0xcc16, 0x2f01, 0xcc16, 0x21, 0 + .dw 0x2f03, 0xcc16, 0x2f0f, 0xcc16, 0x21, 0 + .dw 0x2f11, 0xcc16, 0x2f11, 0xcc16, 0x21, 0 + .dw 0x2f13, 0xcc16, 0x2f3f, 0xcc16, 0x21, 0 + .dw 0x2f41, 0xcc16, 0x2f41, 0xcc16, 0x21, 0 + .dw 0x2f43, 0xcc16, 0x2f4f, 0xcc16, 0x21, 0 + .dw 0x2f51, 0xcc16, 0x2f51, 0xcc16, 0x21, 0 + .dw 0x2f53, 0xcc16, 0x2f7f, 0xcc16, 0x21, 0 + .dw 0x2f81, 0xcc16, 0x2f81, 0xcc16, 0x21, 0 + .dw 0x2f83, 0xcc16, 0x2f8f, 0xcc16, 0x21, 0 + .dw 0x2f91, 0xcc16, 0x2f91, 0xcc16, 0x21, 0 + .dw 0x2f93, 0xcc16, 0x2fbf, 0xcc16, 0x21, 0 + .dw 0x2fc1, 0xcc16, 0x2fc1, 0xcc16, 0x21, 0 + .dw 0x2fc3, 0xcc16, 0x2fcf, 0xcc16, 0x21, 0 + .dw 0x2fd1, 0xcc16, 0x2fd1, 0xcc16, 0x21, 0 + .dw 0x2fd3, 0xcc16, 0x3fff, 0xcc16, 0x21, 0 + .dw 0x4001, 0xcc16, 0x4001, 0xcc16, 0x21, 0 + .dw 0x4003, 0xcc16, 0x400f, 0xcc16, 0x21, 0 + .dw 0x4011, 0xcc16, 0x4011, 0xcc16, 0x21, 0 + .dw 0x4013, 0xcc16, 0x403f, 0xcc16, 0x21, 0 + .dw 0x4041, 0xcc16, 0x4041, 0xcc16, 0x21, 0 + .dw 0x4043, 0xcc16, 0x404f, 0xcc16, 0x21, 0 + .dw 0x4051, 0xcc16, 0x4051, 0xcc16, 0x21, 0 + .dw 0x4053, 0xcc16, 0x407f, 0xcc16, 0x21, 0 + .dw 0x4081, 0xcc16, 0x4081, 0xcc16, 0x21, 0 + .dw 0x4083, 0xcc16, 0x408f, 0xcc16, 0x21, 0 + .dw 0x4091, 0xcc16, 0x4091, 0xcc16, 0x21, 0 + .dw 0x4093, 0xcc16, 0x40bf, 0xcc16, 0x21, 0 + .dw 0x40c1, 0xcc16, 0x40c1, 0xcc16, 0x21, 0 + .dw 0x40c3, 0xcc16, 0x40cf, 0xcc16, 0x21, 0 + .dw 0x40d1, 0xcc16, 0x40d1, 0xcc16, 0x21, 0 + .dw 0x40d3, 0xcc16, 0x40ff, 0xcc16, 0x21, 0 + .dw 0x4101, 0xcc16, 0x4101, 0xcc16, 0x21, 0 + .dw 0x4103, 0xcc16, 0x410f, 0xcc16, 0x21, 0 + .dw 0x4111, 0xcc16, 0x4111, 0xcc16, 0x21, 0 + .dw 0x4113, 0xcc16, 0x413f, 0xcc16, 0x21, 0 + .dw 0x4141, 0xcc16, 0x4141, 0xcc16, 0x21, 0 + .dw 0x4143, 0xcc16, 0x414f, 0xcc16, 0x21, 0 + .dw 0x4151, 0xcc16, 0x4151, 0xcc16, 0x21, 0 + .dw 0x4153, 0xcc16, 0x417f, 0xcc16, 0x21, 0 + .dw 0x4181, 0xcc16, 0x4181, 0xcc16, 0x21, 0 + .dw 0x4183, 0xcc16, 0x418f, 0xcc16, 0x21, 0 + .dw 0x4191, 0xcc16, 0x4191, 0xcc16, 0x21, 0 + .dw 0x4193, 0xcc16, 0x41bf, 0xcc16, 0x21, 0 + .dw 0x41c1, 0xcc16, 0x41c1, 0xcc16, 0x21, 0 + .dw 0x41c3, 0xcc16, 0x41cf, 0xcc16, 0x21, 0 + .dw 0x41d1, 0xcc16, 0x41d1, 0xcc16, 0x21, 0 + .dw 0x41d3, 0xcc16, 0x41ff, 0xcc16, 0x21, 0 + .dw 0x4201, 0xcc16, 0x4201, 0xcc16, 0x21, 0 + .dw 0x4203, 0xcc16, 0x420f, 0xcc16, 0x21, 0 + .dw 0x4211, 0xcc16, 0x4211, 0xcc16, 0x21, 0 + .dw 0x4213, 0xcc16, 0x423f, 0xcc16, 0x21, 0 + .dw 0x4241, 0xcc16, 0x4241, 0xcc16, 0x21, 0 + .dw 0x4243, 0xcc16, 0x424f, 0xcc16, 0x21, 0 + .dw 0x4251, 0xcc16, 0x4251, 0xcc16, 0x21, 0 + .dw 0x4253, 0xcc16, 0x427f, 0xcc16, 0x21, 0 + .dw 0x4281, 0xcc16, 0x4281, 0xcc16, 0x21, 0 + .dw 0x4283, 0xcc16, 0x428f, 0xcc16, 0x21, 0 + .dw 0x4291, 0xcc16, 0x4291, 0xcc16, 0x21, 0 + .dw 0x4293, 0xcc16, 0x42bf, 0xcc16, 0x21, 0 + .dw 0x42c1, 0xcc16, 0x42c1, 0xcc16, 0x21, 0 + .dw 0x42c3, 0xcc16, 0x42cf, 0xcc16, 0x21, 0 + .dw 0x42d1, 0xcc16, 0x42d1, 0xcc16, 0x21, 0 + .dw 0x42d3, 0xcc16, 0x42ff, 0xcc16, 0x21, 0 + .dw 0x4301, 0xcc16, 0x4301, 0xcc16, 0x21, 0 + .dw 0x4303, 0xcc16, 0x430f, 0xcc16, 0x21, 0 + .dw 0x4311, 0xcc16, 0x4311, 0xcc16, 0x21, 0 + .dw 0x4313, 0xcc16, 0x433f, 0xcc16, 0x21, 0 + .dw 0x4341, 0xcc16, 0x4341, 0xcc16, 0x21, 0 + .dw 0x4343, 0xcc16, 0x434f, 0xcc16, 0x21, 0 + .dw 0x4351, 0xcc16, 0x4351, 0xcc16, 0x21, 0 + .dw 0x4353, 0xcc16, 0x437f, 0xcc16, 0x21, 0 + .dw 0x4381, 0xcc16, 0x4381, 0xcc16, 0x21, 0 + .dw 0x4383, 0xcc16, 0x438f, 0xcc16, 0x21, 0 + .dw 0x4391, 0xcc16, 0x4391, 0xcc16, 0x21, 0 + .dw 0x4393, 0xcc16, 0x43bf, 0xcc16, 0x21, 0 + .dw 0x43c1, 0xcc16, 0x43c1, 0xcc16, 0x21, 0 + .dw 0x43c3, 0xcc16, 0x43cf, 0xcc16, 0x21, 0 + .dw 0x43d1, 0xcc16, 0x43d1, 0xcc16, 0x21, 0 + .dw 0x43d3, 0xcc16, 0x43ff, 0xcc16, 0x21, 0 + .dw 0x4401, 0xcc16, 0x4401, 0xcc16, 0x21, 0 + .dw 0x4403, 0xcc16, 0x440f, 0xcc16, 0x21, 0 + .dw 0x4411, 0xcc16, 0x4411, 0xcc16, 0x21, 0 + .dw 0x4413, 0xcc16, 0x443f, 0xcc16, 0x21, 0 + .dw 0x4441, 0xcc16, 0x4441, 0xcc16, 0x21, 0 + .dw 0x4443, 0xcc16, 0x444f, 0xcc16, 0x21, 0 + .dw 0x4451, 0xcc16, 0x4451, 0xcc16, 0x21, 0 + .dw 0x4453, 0xcc16, 0x447f, 0xcc16, 0x21, 0 + .dw 0x4481, 0xcc16, 0x4481, 0xcc16, 0x21, 0 + .dw 0x4483, 0xcc16, 0x448f, 0xcc16, 0x21, 0 + .dw 0x4491, 0xcc16, 0x4491, 0xcc16, 0x21, 0 + .dw 0x4493, 0xcc16, 0x44bf, 0xcc16, 0x21, 0 + .dw 0x44c1, 0xcc16, 0x44c1, 0xcc16, 0x21, 0 + .dw 0x44c3, 0xcc16, 0x44cf, 0xcc16, 0x21, 0 + .dw 0x44d1, 0xcc16, 0x44d1, 0xcc16, 0x21, 0 + .dw 0x44d3, 0xcc16, 0x44ff, 0xcc16, 0x21, 0 + .dw 0x4501, 0xcc16, 0x4501, 0xcc16, 0x21, 0 + .dw 0x4503, 0xcc16, 0x450f, 0xcc16, 0x21, 0 + .dw 0x4511, 0xcc16, 0x4511, 0xcc16, 0x21, 0 + .dw 0x4513, 0xcc16, 0x453f, 0xcc16, 0x21, 0 + .dw 0x4541, 0xcc16, 0x4541, 0xcc16, 0x21, 0 + .dw 0x4543, 0xcc16, 0x454f, 0xcc16, 0x21, 0 + .dw 0x4551, 0xcc16, 0x4551, 0xcc16, 0x21, 0 + .dw 0x4553, 0xcc16, 0x457f, 0xcc16, 0x21, 0 + .dw 0x4581, 0xcc16, 0x4581, 0xcc16, 0x21, 0 + .dw 0x4583, 0xcc16, 0x458f, 0xcc16, 0x21, 0 + .dw 0x4591, 0xcc16, 0x4591, 0xcc16, 0x21, 0 + .dw 0x4593, 0xcc16, 0x45bf, 0xcc16, 0x21, 0 + .dw 0x45c1, 0xcc16, 0x45c1, 0xcc16, 0x21, 0 + .dw 0x45c3, 0xcc16, 0x45cf, 0xcc16, 0x21, 0 + .dw 0x45d1, 0xcc16, 0x45d1, 0xcc16, 0x21, 0 + .dw 0x45d3, 0xcc16, 0x45ff, 0xcc16, 0x21, 0 + .dw 0x4601, 0xcc16, 0x4601, 0xcc16, 0x21, 0 + .dw 0x4603, 0xcc16, 0x460f, 0xcc16, 0x21, 0 + .dw 0x4611, 0xcc16, 0x4611, 0xcc16, 0x21, 0 + .dw 0x4613, 0xcc16, 0x463f, 0xcc16, 0x21, 0 + .dw 0x4641, 0xcc16, 0x4641, 0xcc16, 0x21, 0 + .dw 0x4643, 0xcc16, 0x464f, 0xcc16, 0x21, 0 + .dw 0x4651, 0xcc16, 0x4651, 0xcc16, 0x21, 0 + .dw 0x4653, 0xcc16, 0x467f, 0xcc16, 0x21, 0 + .dw 0x4681, 0xcc16, 0x4681, 0xcc16, 0x21, 0 + .dw 0x4683, 0xcc16, 0x468f, 0xcc16, 0x21, 0 + .dw 0x4691, 0xcc16, 0x4691, 0xcc16, 0x21, 0 + .dw 0x4693, 0xcc16, 0x46bf, 0xcc16, 0x21, 0 + .dw 0x46c1, 0xcc16, 0x46c1, 0xcc16, 0x21, 0 + .dw 0x46c3, 0xcc16, 0x46cf, 0xcc16, 0x21, 0 + .dw 0x46d1, 0xcc16, 0x46d1, 0xcc16, 0x21, 0 + .dw 0x46d3, 0xcc16, 0x46ff, 0xcc16, 0x21, 0 + .dw 0x4701, 0xcc16, 0x4701, 0xcc16, 0x21, 0 + .dw 0x4703, 0xcc16, 0x470f, 0xcc16, 0x21, 0 + .dw 0x4711, 0xcc16, 0x4711, 0xcc16, 0x21, 0 + .dw 0x4713, 0xcc16, 0x473f, 0xcc16, 0x21, 0 + .dw 0x4741, 0xcc16, 0x4741, 0xcc16, 0x21, 0 + .dw 0x4743, 0xcc16, 0x474f, 0xcc16, 0x21, 0 + .dw 0x4751, 0xcc16, 0x4751, 0xcc16, 0x21, 0 + .dw 0x4753, 0xcc16, 0x477f, 0xcc16, 0x21, 0 + .dw 0x4781, 0xcc16, 0x4781, 0xcc16, 0x21, 0 + .dw 0x4783, 0xcc16, 0x478f, 0xcc16, 0x21, 0 + .dw 0x4791, 0xcc16, 0x4791, 0xcc16, 0x21, 0 + .dw 0x4793, 0xcc16, 0x47bf, 0xcc16, 0x21, 0 + .dw 0x47c1, 0xcc16, 0x47c1, 0xcc16, 0x21, 0 + .dw 0x47c3, 0xcc16, 0x47cf, 0xcc16, 0x21, 0 + .dw 0x47d1, 0xcc16, 0x47d1, 0xcc16, 0x21, 0 + .dw 0x47d3, 0xcc16, 0x47ff, 0xcc16, 0x21, 0 + .dw 0x4801, 0xcc16, 0x4801, 0xcc16, 0x21, 0 + .dw 0x4803, 0xcc16, 0x480f, 0xcc16, 0x21, 0 + .dw 0x4811, 0xcc16, 0x4811, 0xcc16, 0x21, 0 + .dw 0x4813, 0xcc16, 0x483f, 0xcc16, 0x21, 0 + .dw 0x4841, 0xcc16, 0x4841, 0xcc16, 0x21, 0 + .dw 0x4843, 0xcc16, 0x484f, 0xcc16, 0x21, 0 + .dw 0x4851, 0xcc16, 0x4851, 0xcc16, 0x21, 0 + .dw 0x4853, 0xcc16, 0x487f, 0xcc16, 0x21, 0 + .dw 0x4881, 0xcc16, 0x4881, 0xcc16, 0x21, 0 + .dw 0x4883, 0xcc16, 0x488f, 0xcc16, 0x21, 0 + .dw 0x4891, 0xcc16, 0x4891, 0xcc16, 0x21, 0 + .dw 0x4893, 0xcc16, 0x48bf, 0xcc16, 0x21, 0 + .dw 0x48c1, 0xcc16, 0x48c1, 0xcc16, 0x21, 0 + .dw 0x48c3, 0xcc16, 0x48cf, 0xcc16, 0x21, 0 + .dw 0x48d1, 0xcc16, 0x48d1, 0xcc16, 0x21, 0 + .dw 0x48d3, 0xcc16, 0x48ff, 0xcc16, 0x21, 0 + .dw 0x4901, 0xcc16, 0x4901, 0xcc16, 0x21, 0 + .dw 0x4903, 0xcc16, 0x490f, 0xcc16, 0x21, 0 + .dw 0x4911, 0xcc16, 0x4911, 0xcc16, 0x21, 0 + .dw 0x4913, 0xcc16, 0x493f, 0xcc16, 0x21, 0 + .dw 0x4941, 0xcc16, 0x4941, 0xcc16, 0x21, 0 + .dw 0x4943, 0xcc16, 0x494f, 0xcc16, 0x21, 0 + .dw 0x4951, 0xcc16, 0x4951, 0xcc16, 0x21, 0 + .dw 0x4953, 0xcc16, 0x497f, 0xcc16, 0x21, 0 + .dw 0x4981, 0xcc16, 0x4981, 0xcc16, 0x21, 0 + .dw 0x4983, 0xcc16, 0x498f, 0xcc16, 0x21, 0 + .dw 0x4991, 0xcc16, 0x4991, 0xcc16, 0x21, 0 + .dw 0x4993, 0xcc16, 0x49bf, 0xcc16, 0x21, 0 + .dw 0x49c1, 0xcc16, 0x49c1, 0xcc16, 0x21, 0 + .dw 0x49c3, 0xcc16, 0x49cf, 0xcc16, 0x21, 0 + .dw 0x49d1, 0xcc16, 0x49d1, 0xcc16, 0x21, 0 + .dw 0x49d3, 0xcc16, 0x49ff, 0xcc16, 0x21, 0 + .dw 0x4a01, 0xcc16, 0x4a01, 0xcc16, 0x21, 0 + .dw 0x4a03, 0xcc16, 0x4a0f, 0xcc16, 0x21, 0 + .dw 0x4a11, 0xcc16, 0x4a11, 0xcc16, 0x21, 0 + .dw 0x4a13, 0xcc16, 0x4a3f, 0xcc16, 0x21, 0 + .dw 0x4a41, 0xcc16, 0x4a41, 0xcc16, 0x21, 0 + .dw 0x4a43, 0xcc16, 0x4a4f, 0xcc16, 0x21, 0 + .dw 0x4a51, 0xcc16, 0x4a51, 0xcc16, 0x21, 0 + .dw 0x4a53, 0xcc16, 0x4a7f, 0xcc16, 0x21, 0 + .dw 0x4a81, 0xcc16, 0x4a81, 0xcc16, 0x21, 0 + .dw 0x4a83, 0xcc16, 0x4a8f, 0xcc16, 0x21, 0 + .dw 0x4a91, 0xcc16, 0x4a91, 0xcc16, 0x21, 0 + .dw 0x4a93, 0xcc16, 0x4abf, 0xcc16, 0x21, 0 + .dw 0x4ac1, 0xcc16, 0x4ac1, 0xcc16, 0x21, 0 + .dw 0x4ac3, 0xcc16, 0x4acf, 0xcc16, 0x21, 0 + .dw 0x4ad1, 0xcc16, 0x4ad1, 0xcc16, 0x21, 0 + .dw 0x4ad3, 0xcc16, 0x4aff, 0xcc16, 0x21, 0 + .dw 0x4b01, 0xcc16, 0x4b01, 0xcc16, 0x21, 0 + .dw 0x4b03, 0xcc16, 0x4b0f, 0xcc16, 0x21, 0 + .dw 0x4b11, 0xcc16, 0x4b11, 0xcc16, 0x21, 0 + .dw 0x4b13, 0xcc16, 0x4b3f, 0xcc16, 0x21, 0 + .dw 0x4b41, 0xcc16, 0x4b41, 0xcc16, 0x21, 0 + .dw 0x4b43, 0xcc16, 0x4b4f, 0xcc16, 0x21, 0 + .dw 0x4b51, 0xcc16, 0x4b51, 0xcc16, 0x21, 0 + .dw 0x4b53, 0xcc16, 0x4b7f, 0xcc16, 0x21, 0 + .dw 0x4b81, 0xcc16, 0x4b81, 0xcc16, 0x21, 0 + .dw 0x4b83, 0xcc16, 0x4b8f, 0xcc16, 0x21, 0 + .dw 0x4b91, 0xcc16, 0x4b91, 0xcc16, 0x21, 0 + .dw 0x4b93, 0xcc16, 0x4bbf, 0xcc16, 0x21, 0 + .dw 0x4bc1, 0xcc16, 0x4bc1, 0xcc16, 0x21, 0 + .dw 0x4bc3, 0xcc16, 0x4bcf, 0xcc16, 0x21, 0 + .dw 0x4bd1, 0xcc16, 0x4bd1, 0xcc16, 0x21, 0 + .dw 0x4bd3, 0xcc16, 0x4bff, 0xcc16, 0x21, 0 + .dw 0x4c01, 0xcc16, 0x4c01, 0xcc16, 0x21, 0 + .dw 0x4c03, 0xcc16, 0x4c0f, 0xcc16, 0x21, 0 + .dw 0x4c11, 0xcc16, 0x4c11, 0xcc16, 0x21, 0 + .dw 0x4c13, 0xcc16, 0x4c3f, 0xcc16, 0x21, 0 + .dw 0x4c41, 0xcc16, 0x4c41, 0xcc16, 0x21, 0 + .dw 0x4c43, 0xcc16, 0x4c4f, 0xcc16, 0x21, 0 + .dw 0x4c51, 0xcc16, 0x4c51, 0xcc16, 0x21, 0 + .dw 0x4c53, 0xcc16, 0x4c7f, 0xcc16, 0x21, 0 + .dw 0x4c81, 0xcc16, 0x4c81, 0xcc16, 0x21, 0 + .dw 0x4c83, 0xcc16, 0x4c8f, 0xcc16, 0x21, 0 + .dw 0x4c91, 0xcc16, 0x4c91, 0xcc16, 0x21, 0 + .dw 0x4c93, 0xcc16, 0x4cbf, 0xcc16, 0x21, 0 + .dw 0x4cc1, 0xcc16, 0x4cc1, 0xcc16, 0x21, 0 + .dw 0x4cc3, 0xcc16, 0x4ccf, 0xcc16, 0x21, 0 + .dw 0x4cd1, 0xcc16, 0x4cd1, 0xcc16, 0x21, 0 + .dw 0x4cd3, 0xcc16, 0x4cff, 0xcc16, 0x21, 0 + .dw 0x4d01, 0xcc16, 0x4d01, 0xcc16, 0x21, 0 + .dw 0x4d03, 0xcc16, 0x4d0f, 0xcc16, 0x21, 0 + .dw 0x4d11, 0xcc16, 0x4d11, 0xcc16, 0x21, 0 + .dw 0x4d13, 0xcc16, 0x4d3f, 0xcc16, 0x21, 0 + .dw 0x4d41, 0xcc16, 0x4d41, 0xcc16, 0x21, 0 + .dw 0x4d43, 0xcc16, 0x4d4f, 0xcc16, 0x21, 0 + .dw 0x4d51, 0xcc16, 0x4d51, 0xcc16, 0x21, 0 + .dw 0x4d53, 0xcc16, 0x4d7f, 0xcc16, 0x21, 0 + .dw 0x4d81, 0xcc16, 0x4d81, 0xcc16, 0x21, 0 + .dw 0x4d83, 0xcc16, 0x4d8f, 0xcc16, 0x21, 0 + .dw 0x4d91, 0xcc16, 0x4d91, 0xcc16, 0x21, 0 + .dw 0x4d93, 0xcc16, 0x4dbf, 0xcc16, 0x21, 0 + .dw 0x4dc1, 0xcc16, 0x4dc1, 0xcc16, 0x21, 0 + .dw 0x4dc3, 0xcc16, 0x4dcf, 0xcc16, 0x21, 0 + .dw 0x4dd1, 0xcc16, 0x4dd1, 0xcc16, 0x21, 0 + .dw 0x4dd3, 0xcc16, 0x4dff, 0xcc16, 0x21, 0 + .dw 0x4e01, 0xcc16, 0x4e01, 0xcc16, 0x21, 0 + .dw 0x4e03, 0xcc16, 0x4e0f, 0xcc16, 0x21, 0 + .dw 0x4e11, 0xcc16, 0x4e11, 0xcc16, 0x21, 0 + .dw 0x4e13, 0xcc16, 0x4e3f, 0xcc16, 0x21, 0 + .dw 0x4e41, 0xcc16, 0x4e41, 0xcc16, 0x21, 0 + .dw 0x4e43, 0xcc16, 0x4e4f, 0xcc16, 0x21, 0 + .dw 0x4e51, 0xcc16, 0x4e51, 0xcc16, 0x21, 0 + .dw 0x4e53, 0xcc16, 0x4e7f, 0xcc16, 0x21, 0 + .dw 0x4e81, 0xcc16, 0x4e81, 0xcc16, 0x21, 0 + .dw 0x4e83, 0xcc16, 0x4e8f, 0xcc16, 0x21, 0 + .dw 0x4e91, 0xcc16, 0x4e91, 0xcc16, 0x21, 0 + .dw 0x4e93, 0xcc16, 0x4ebf, 0xcc16, 0x21, 0 + .dw 0x4ec1, 0xcc16, 0x4ec1, 0xcc16, 0x21, 0 + .dw 0x4ec3, 0xcc16, 0x4ecf, 0xcc16, 0x21, 0 + .dw 0x4ed1, 0xcc16, 0x4ed1, 0xcc16, 0x21, 0 + .dw 0x4ed3, 0xcc16, 0x4eff, 0xcc16, 0x21, 0 + .dw 0x4f01, 0xcc16, 0x4f01, 0xcc16, 0x21, 0 + .dw 0x4f03, 0xcc16, 0x4f0f, 0xcc16, 0x21, 0 + .dw 0x4f11, 0xcc16, 0x4f11, 0xcc16, 0x21, 0 + .dw 0x4f13, 0xcc16, 0x4f3f, 0xcc16, 0x21, 0 + .dw 0x4f41, 0xcc16, 0x4f41, 0xcc16, 0x21, 0 + .dw 0x4f43, 0xcc16, 0x4f4f, 0xcc16, 0x21, 0 + .dw 0x4f51, 0xcc16, 0x4f51, 0xcc16, 0x21, 0 + .dw 0x4f53, 0xcc16, 0x4f7f, 0xcc16, 0x21, 0 + .dw 0x4f81, 0xcc16, 0x4f81, 0xcc16, 0x21, 0 + .dw 0x4f83, 0xcc16, 0x4f8f, 0xcc16, 0x21, 0 + .dw 0x4f91, 0xcc16, 0x4f91, 0xcc16, 0x21, 0 + .dw 0x4f93, 0xcc16, 0x4fbf, 0xcc16, 0x21, 0 + .dw 0x4fc1, 0xcc16, 0x4fc1, 0xcc16, 0x21, 0 + .dw 0x4fc3, 0xcc16, 0x4fcf, 0xcc16, 0x21, 0 + .dw 0x4fd1, 0xcc16, 0x4fd1, 0xcc16, 0x21, 0 + .dw 0x4fd3, 0xcc16, 0x5fff, 0xcc16, 0x21, 0 + .dw 0x6001, 0xcc16, 0x6001, 0xcc16, 0x21, 0 + .dw 0x6003, 0xcc16, 0x600f, 0xcc16, 0x21, 0 + .dw 0x6011, 0xcc16, 0x6011, 0xcc16, 0x21, 0 + .dw 0x6013, 0xcc16, 0x603f, 0xcc16, 0x21, 0 + .dw 0x6041, 0xcc16, 0x6041, 0xcc16, 0x21, 0 + .dw 0x6043, 0xcc16, 0x604f, 0xcc16, 0x21, 0 + .dw 0x6051, 0xcc16, 0x6051, 0xcc16, 0x21, 0 + .dw 0x6053, 0xcc16, 0x607f, 0xcc16, 0x21, 0 + .dw 0x6081, 0xcc16, 0x6081, 0xcc16, 0x21, 0 + .dw 0x6083, 0xcc16, 0x608f, 0xcc16, 0x21, 0 + .dw 0x6091, 0xcc16, 0x6091, 0xcc16, 0x21, 0 + .dw 0x6093, 0xcc16, 0x60bf, 0xcc16, 0x21, 0 + .dw 0x60c1, 0xcc16, 0x60c1, 0xcc16, 0x21, 0 + .dw 0x60c3, 0xcc16, 0x60cf, 0xcc16, 0x21, 0 + .dw 0x60d1, 0xcc16, 0x60d1, 0xcc16, 0x21, 0 + .dw 0x60d3, 0xcc16, 0x60ff, 0xcc16, 0x21, 0 + .dw 0x6101, 0xcc16, 0x6101, 0xcc16, 0x21, 0 + .dw 0x6103, 0xcc16, 0x610f, 0xcc16, 0x21, 0 + .dw 0x6111, 0xcc16, 0x6111, 0xcc16, 0x21, 0 + .dw 0x6113, 0xcc16, 0x613f, 0xcc16, 0x21, 0 + .dw 0x6141, 0xcc16, 0x6141, 0xcc16, 0x21, 0 + .dw 0x6143, 0xcc16, 0x614f, 0xcc16, 0x21, 0 + .dw 0x6151, 0xcc16, 0x6151, 0xcc16, 0x21, 0 + .dw 0x6153, 0xcc16, 0x617f, 0xcc16, 0x21, 0 + .dw 0x6181, 0xcc16, 0x6181, 0xcc16, 0x21, 0 + .dw 0x6183, 0xcc16, 0x618f, 0xcc16, 0x21, 0 + .dw 0x6191, 0xcc16, 0x6191, 0xcc16, 0x21, 0 + .dw 0x6193, 0xcc16, 0x61bf, 0xcc16, 0x21, 0 + .dw 0x61c1, 0xcc16, 0x61c1, 0xcc16, 0x21, 0 + .dw 0x61c3, 0xcc16, 0x61cf, 0xcc16, 0x21, 0 + .dw 0x61d1, 0xcc16, 0x61d1, 0xcc16, 0x21, 0 + .dw 0x61d3, 0xcc16, 0x61ff, 0xcc16, 0x21, 0 + .dw 0x6201, 0xcc16, 0x6201, 0xcc16, 0x21, 0 + .dw 0x6203, 0xcc16, 0x620f, 0xcc16, 0x21, 0 + .dw 0x6211, 0xcc16, 0x6211, 0xcc16, 0x21, 0 + .dw 0x6213, 0xcc16, 0x623f, 0xcc16, 0x21, 0 + .dw 0x6241, 0xcc16, 0x6241, 0xcc16, 0x21, 0 + .dw 0x6243, 0xcc16, 0x624f, 0xcc16, 0x21, 0 + .dw 0x6251, 0xcc16, 0x6251, 0xcc16, 0x21, 0 + .dw 0x6253, 0xcc16, 0x627f, 0xcc16, 0x21, 0 + .dw 0x6281, 0xcc16, 0x6281, 0xcc16, 0x21, 0 + .dw 0x6283, 0xcc16, 0x628f, 0xcc16, 0x21, 0 + .dw 0x6291, 0xcc16, 0x6291, 0xcc16, 0x21, 0 + .dw 0x6293, 0xcc16, 0x62bf, 0xcc16, 0x21, 0 + .dw 0x62c1, 0xcc16, 0x62c1, 0xcc16, 0x21, 0 + .dw 0x62c3, 0xcc16, 0x62cf, 0xcc16, 0x21, 0 + .dw 0x62d1, 0xcc16, 0x62d1, 0xcc16, 0x21, 0 + .dw 0x62d3, 0xcc16, 0x62ff, 0xcc16, 0x21, 0 + .dw 0x6301, 0xcc16, 0x6301, 0xcc16, 0x21, 0 + .dw 0x6303, 0xcc16, 0x630f, 0xcc16, 0x21, 0 + .dw 0x6311, 0xcc16, 0x6311, 0xcc16, 0x21, 0 + .dw 0x6313, 0xcc16, 0x633f, 0xcc16, 0x21, 0 + .dw 0x6341, 0xcc16, 0x6341, 0xcc16, 0x21, 0 + .dw 0x6343, 0xcc16, 0x634f, 0xcc16, 0x21, 0 + .dw 0x6351, 0xcc16, 0x6351, 0xcc16, 0x21, 0 + .dw 0x6353, 0xcc16, 0x637f, 0xcc16, 0x21, 0 + .dw 0x6381, 0xcc16, 0x6381, 0xcc16, 0x21, 0 + .dw 0x6383, 0xcc16, 0x638f, 0xcc16, 0x21, 0 + .dw 0x6391, 0xcc16, 0x6391, 0xcc16, 0x21, 0 + .dw 0x6393, 0xcc16, 0x63bf, 0xcc16, 0x21, 0 + .dw 0x63c1, 0xcc16, 0x63c1, 0xcc16, 0x21, 0 + .dw 0x63c3, 0xcc16, 0x63cf, 0xcc16, 0x21, 0 + .dw 0x63d1, 0xcc16, 0x63d1, 0xcc16, 0x21, 0 + .dw 0x63d3, 0xcc16, 0x63ff, 0xcc16, 0x21, 0 + .dw 0x6401, 0xcc16, 0x6401, 0xcc16, 0x21, 0 + .dw 0x6403, 0xcc16, 0x640f, 0xcc16, 0x21, 0 + .dw 0x6411, 0xcc16, 0x6411, 0xcc16, 0x21, 0 + .dw 0x6413, 0xcc16, 0x643f, 0xcc16, 0x21, 0 + .dw 0x6441, 0xcc16, 0x6441, 0xcc16, 0x21, 0 + .dw 0x6443, 0xcc16, 0x644f, 0xcc16, 0x21, 0 + .dw 0x6451, 0xcc16, 0x6451, 0xcc16, 0x21, 0 + .dw 0x6453, 0xcc16, 0x647f, 0xcc16, 0x21, 0 + .dw 0x6481, 0xcc16, 0x6481, 0xcc16, 0x21, 0 + .dw 0x6483, 0xcc16, 0x648f, 0xcc16, 0x21, 0 + .dw 0x6491, 0xcc16, 0x6491, 0xcc16, 0x21, 0 + .dw 0x6493, 0xcc16, 0x64bf, 0xcc16, 0x21, 0 + .dw 0x64c1, 0xcc16, 0x64c1, 0xcc16, 0x21, 0 + .dw 0x64c3, 0xcc16, 0x64cf, 0xcc16, 0x21, 0 + .dw 0x64d1, 0xcc16, 0x64d1, 0xcc16, 0x21, 0 + .dw 0x64d3, 0xcc16, 0x64ff, 0xcc16, 0x21, 0 + .dw 0x6501, 0xcc16, 0x6501, 0xcc16, 0x21, 0 + .dw 0x6503, 0xcc16, 0x650f, 0xcc16, 0x21, 0 + .dw 0x6511, 0xcc16, 0x6511, 0xcc16, 0x21, 0 + .dw 0x6513, 0xcc16, 0x653f, 0xcc16, 0x21, 0 + .dw 0x6541, 0xcc16, 0x6541, 0xcc16, 0x21, 0 + .dw 0x6543, 0xcc16, 0x654f, 0xcc16, 0x21, 0 + .dw 0x6551, 0xcc16, 0x6551, 0xcc16, 0x21, 0 + .dw 0x6553, 0xcc16, 0x657f, 0xcc16, 0x21, 0 + .dw 0x6581, 0xcc16, 0x6581, 0xcc16, 0x21, 0 + .dw 0x6583, 0xcc16, 0x658f, 0xcc16, 0x21, 0 + .dw 0x6591, 0xcc16, 0x6591, 0xcc16, 0x21, 0 + .dw 0x6593, 0xcc16, 0x65bf, 0xcc16, 0x21, 0 + .dw 0x65c1, 0xcc16, 0x65c1, 0xcc16, 0x21, 0 + .dw 0x65c3, 0xcc16, 0x65cf, 0xcc16, 0x21, 0 + .dw 0x65d1, 0xcc16, 0x65d1, 0xcc16, 0x21, 0 + .dw 0x65d3, 0xcc16, 0x65ff, 0xcc16, 0x21, 0 + .dw 0x6601, 0xcc16, 0x6601, 0xcc16, 0x21, 0 + .dw 0x6603, 0xcc16, 0x660f, 0xcc16, 0x21, 0 + .dw 0x6611, 0xcc16, 0x6611, 0xcc16, 0x21, 0 + .dw 0x6613, 0xcc16, 0x663f, 0xcc16, 0x21, 0 + .dw 0x6641, 0xcc16, 0x6641, 0xcc16, 0x21, 0 + .dw 0x6643, 0xcc16, 0x664f, 0xcc16, 0x21, 0 + .dw 0x6651, 0xcc16, 0x6651, 0xcc16, 0x21, 0 + .dw 0x6653, 0xcc16, 0x667f, 0xcc16, 0x21, 0 + .dw 0x6681, 0xcc16, 0x6681, 0xcc16, 0x21, 0 + .dw 0x6683, 0xcc16, 0x668f, 0xcc16, 0x21, 0 + .dw 0x6691, 0xcc16, 0x6691, 0xcc16, 0x21, 0 + .dw 0x6693, 0xcc16, 0x66bf, 0xcc16, 0x21, 0 + .dw 0x66c1, 0xcc16, 0x66c1, 0xcc16, 0x21, 0 + .dw 0x66c3, 0xcc16, 0x66cf, 0xcc16, 0x21, 0 + .dw 0x66d1, 0xcc16, 0x66d1, 0xcc16, 0x21, 0 + .dw 0x66d3, 0xcc16, 0x66ff, 0xcc16, 0x21, 0 + .dw 0x6701, 0xcc16, 0x6701, 0xcc16, 0x21, 0 + .dw 0x6703, 0xcc16, 0x670f, 0xcc16, 0x21, 0 + .dw 0x6711, 0xcc16, 0x6711, 0xcc16, 0x21, 0 + .dw 0x6713, 0xcc16, 0x673f, 0xcc16, 0x21, 0 + .dw 0x6741, 0xcc16, 0x6741, 0xcc16, 0x21, 0 + .dw 0x6743, 0xcc16, 0x674f, 0xcc16, 0x21, 0 + .dw 0x6751, 0xcc16, 0x6751, 0xcc16, 0x21, 0 + .dw 0x6753, 0xcc16, 0x677f, 0xcc16, 0x21, 0 + .dw 0x6781, 0xcc16, 0x6781, 0xcc16, 0x21, 0 + .dw 0x6783, 0xcc16, 0x678f, 0xcc16, 0x21, 0 + .dw 0x6791, 0xcc16, 0x6791, 0xcc16, 0x21, 0 + .dw 0x6793, 0xcc16, 0x67bf, 0xcc16, 0x21, 0 + .dw 0x67c1, 0xcc16, 0x67c1, 0xcc16, 0x21, 0 + .dw 0x67c3, 0xcc16, 0x67cf, 0xcc16, 0x21, 0 + .dw 0x67d1, 0xcc16, 0x67d1, 0xcc16, 0x21, 0 + .dw 0x67d3, 0xcc16, 0x67ff, 0xcc16, 0x21, 0 + .dw 0x6801, 0xcc16, 0x6801, 0xcc16, 0x21, 0 + .dw 0x6803, 0xcc16, 0x680f, 0xcc16, 0x21, 0 + .dw 0x6811, 0xcc16, 0x6811, 0xcc16, 0x21, 0 + .dw 0x6813, 0xcc16, 0x683f, 0xcc16, 0x21, 0 + .dw 0x6841, 0xcc16, 0x6841, 0xcc16, 0x21, 0 + .dw 0x6843, 0xcc16, 0x684f, 0xcc16, 0x21, 0 + .dw 0x6851, 0xcc16, 0x6851, 0xcc16, 0x21, 0 + .dw 0x6853, 0xcc16, 0x687f, 0xcc16, 0x21, 0 + .dw 0x6881, 0xcc16, 0x6881, 0xcc16, 0x21, 0 + .dw 0x6883, 0xcc16, 0x688f, 0xcc16, 0x21, 0 + .dw 0x6891, 0xcc16, 0x6891, 0xcc16, 0x21, 0 + .dw 0x6893, 0xcc16, 0x68bf, 0xcc16, 0x21, 0 + .dw 0x68c1, 0xcc16, 0x68c1, 0xcc16, 0x21, 0 + .dw 0x68c3, 0xcc16, 0x68cf, 0xcc16, 0x21, 0 + .dw 0x68d1, 0xcc16, 0x68d1, 0xcc16, 0x21, 0 + .dw 0x68d3, 0xcc16, 0x68ff, 0xcc16, 0x21, 0 + .dw 0x6901, 0xcc16, 0x6901, 0xcc16, 0x21, 0 + .dw 0x6903, 0xcc16, 0x690f, 0xcc16, 0x21, 0 + .dw 0x6911, 0xcc16, 0x6911, 0xcc16, 0x21, 0 + .dw 0x6913, 0xcc16, 0x693f, 0xcc16, 0x21, 0 + .dw 0x6941, 0xcc16, 0x6941, 0xcc16, 0x21, 0 + .dw 0x6943, 0xcc16, 0x694f, 0xcc16, 0x21, 0 + .dw 0x6951, 0xcc16, 0x6951, 0xcc16, 0x21, 0 + .dw 0x6953, 0xcc16, 0x697f, 0xcc16, 0x21, 0 + .dw 0x6981, 0xcc16, 0x6981, 0xcc16, 0x21, 0 + .dw 0x6983, 0xcc16, 0x698f, 0xcc16, 0x21, 0 + .dw 0x6991, 0xcc16, 0x6991, 0xcc16, 0x21, 0 + .dw 0x6993, 0xcc16, 0x69bf, 0xcc16, 0x21, 0 + .dw 0x69c1, 0xcc16, 0x69c1, 0xcc16, 0x21, 0 + .dw 0x69c3, 0xcc16, 0x69cf, 0xcc16, 0x21, 0 + .dw 0x69d1, 0xcc16, 0x69d1, 0xcc16, 0x21, 0 + .dw 0x69d3, 0xcc16, 0x69ff, 0xcc16, 0x21, 0 + .dw 0x6a01, 0xcc16, 0x6a01, 0xcc16, 0x21, 0 + .dw 0x6a03, 0xcc16, 0x6a0f, 0xcc16, 0x21, 0 + .dw 0x6a11, 0xcc16, 0x6a11, 0xcc16, 0x21, 0 + .dw 0x6a13, 0xcc16, 0x6a3f, 0xcc16, 0x21, 0 + .dw 0x6a41, 0xcc16, 0x6a41, 0xcc16, 0x21, 0 + .dw 0x6a43, 0xcc16, 0x6a4f, 0xcc16, 0x21, 0 + .dw 0x6a51, 0xcc16, 0x6a51, 0xcc16, 0x21, 0 + .dw 0x6a53, 0xcc16, 0x6a7f, 0xcc16, 0x21, 0 + .dw 0x6a81, 0xcc16, 0x6a81, 0xcc16, 0x21, 0 + .dw 0x6a83, 0xcc16, 0x6a8f, 0xcc16, 0x21, 0 + .dw 0x6a91, 0xcc16, 0x6a91, 0xcc16, 0x21, 0 + .dw 0x6a93, 0xcc16, 0x6abf, 0xcc16, 0x21, 0 + .dw 0x6ac1, 0xcc16, 0x6ac1, 0xcc16, 0x21, 0 + .dw 0x6ac3, 0xcc16, 0x6acf, 0xcc16, 0x21, 0 + .dw 0x6ad1, 0xcc16, 0x6ad1, 0xcc16, 0x21, 0 + .dw 0x6ad3, 0xcc16, 0x6aff, 0xcc16, 0x21, 0 + .dw 0x6b01, 0xcc16, 0x6b01, 0xcc16, 0x21, 0 + .dw 0x6b03, 0xcc16, 0x6b0f, 0xcc16, 0x21, 0 + .dw 0x6b11, 0xcc16, 0x6b11, 0xcc16, 0x21, 0 + .dw 0x6b13, 0xcc16, 0x6b3f, 0xcc16, 0x21, 0 + .dw 0x6b41, 0xcc16, 0x6b41, 0xcc16, 0x21, 0 + .dw 0x6b43, 0xcc16, 0x6b4f, 0xcc16, 0x21, 0 + .dw 0x6b51, 0xcc16, 0x6b51, 0xcc16, 0x21, 0 + .dw 0x6b53, 0xcc16, 0x6b7f, 0xcc16, 0x21, 0 + .dw 0x6b81, 0xcc16, 0x6b81, 0xcc16, 0x21, 0 + .dw 0x6b83, 0xcc16, 0x6b8f, 0xcc16, 0x21, 0 + .dw 0x6b91, 0xcc16, 0x6b91, 0xcc16, 0x21, 0 + .dw 0x6b93, 0xcc16, 0x6bbf, 0xcc16, 0x21, 0 + .dw 0x6bc1, 0xcc16, 0x6bc1, 0xcc16, 0x21, 0 + .dw 0x6bc3, 0xcc16, 0x6bcf, 0xcc16, 0x21, 0 + .dw 0x6bd1, 0xcc16, 0x6bd1, 0xcc16, 0x21, 0 + .dw 0x6bd3, 0xcc16, 0x6bff, 0xcc16, 0x21, 0 + .dw 0x6c01, 0xcc16, 0x6c01, 0xcc16, 0x21, 0 + .dw 0x6c03, 0xcc16, 0x6c0f, 0xcc16, 0x21, 0 + .dw 0x6c11, 0xcc16, 0x6c11, 0xcc16, 0x21, 0 + .dw 0x6c13, 0xcc16, 0x6c3f, 0xcc16, 0x21, 0 + .dw 0x6c41, 0xcc16, 0x6c41, 0xcc16, 0x21, 0 + .dw 0x6c43, 0xcc16, 0x6c4f, 0xcc16, 0x21, 0 + .dw 0x6c51, 0xcc16, 0x6c51, 0xcc16, 0x21, 0 + .dw 0x6c53, 0xcc16, 0x6c7f, 0xcc16, 0x21, 0 + .dw 0x6c81, 0xcc16, 0x6c81, 0xcc16, 0x21, 0 + .dw 0x6c83, 0xcc16, 0x6c8f, 0xcc16, 0x21, 0 + .dw 0x6c91, 0xcc16, 0x6c91, 0xcc16, 0x21, 0 + .dw 0x6c93, 0xcc16, 0x6cbf, 0xcc16, 0x21, 0 + .dw 0x6cc1, 0xcc16, 0x6cc1, 0xcc16, 0x21, 0 + .dw 0x6cc3, 0xcc16, 0x6ccf, 0xcc16, 0x21, 0 + .dw 0x6cd1, 0xcc16, 0x6cd1, 0xcc16, 0x21, 0 + .dw 0x6cd3, 0xcc16, 0x6cff, 0xcc16, 0x21, 0 + .dw 0x6d01, 0xcc16, 0x6d01, 0xcc16, 0x21, 0 + .dw 0x6d03, 0xcc16, 0x6d0f, 0xcc16, 0x21, 0 + .dw 0x6d11, 0xcc16, 0x6d11, 0xcc16, 0x21, 0 + .dw 0x6d13, 0xcc16, 0x6d3f, 0xcc16, 0x21, 0 + .dw 0x6d41, 0xcc16, 0x6d41, 0xcc16, 0x21, 0 + .dw 0x6d43, 0xcc16, 0x6d4f, 0xcc16, 0x21, 0 + .dw 0x6d51, 0xcc16, 0x6d51, 0xcc16, 0x21, 0 + .dw 0x6d53, 0xcc16, 0x6d7f, 0xcc16, 0x21, 0 + .dw 0x6d81, 0xcc16, 0x6d81, 0xcc16, 0x21, 0 + .dw 0x6d83, 0xcc16, 0x6d8f, 0xcc16, 0x21, 0 + .dw 0x6d91, 0xcc16, 0x6d91, 0xcc16, 0x21, 0 + .dw 0x6d93, 0xcc16, 0x6dbf, 0xcc16, 0x21, 0 + .dw 0x6dc1, 0xcc16, 0x6dc1, 0xcc16, 0x21, 0 + .dw 0x6dc3, 0xcc16, 0x6dcf, 0xcc16, 0x21, 0 + .dw 0x6dd1, 0xcc16, 0x6dd1, 0xcc16, 0x21, 0 + .dw 0x6dd3, 0xcc16, 0x6dff, 0xcc16, 0x21, 0 + .dw 0x6e01, 0xcc16, 0x6e01, 0xcc16, 0x21, 0 + .dw 0x6e03, 0xcc16, 0x6e0f, 0xcc16, 0x21, 0 + .dw 0x6e11, 0xcc16, 0x6e11, 0xcc16, 0x21, 0 + .dw 0x6e13, 0xcc16, 0x6e3f, 0xcc16, 0x21, 0 + .dw 0x6e41, 0xcc16, 0x6e41, 0xcc16, 0x21, 0 + .dw 0x6e43, 0xcc16, 0x6e4f, 0xcc16, 0x21, 0 + .dw 0x6e51, 0xcc16, 0x6e51, 0xcc16, 0x21, 0 + .dw 0x6e53, 0xcc16, 0x6e7f, 0xcc16, 0x21, 0 + .dw 0x6e81, 0xcc16, 0x6e81, 0xcc16, 0x21, 0 + .dw 0x6e83, 0xcc16, 0x6e8f, 0xcc16, 0x21, 0 + .dw 0x6e91, 0xcc16, 0x6e91, 0xcc16, 0x21, 0 + .dw 0x6e93, 0xcc16, 0x6ebf, 0xcc16, 0x21, 0 + .dw 0x6ec1, 0xcc16, 0x6ec1, 0xcc16, 0x21, 0 + .dw 0x6ec3, 0xcc16, 0x6ecf, 0xcc16, 0x21, 0 + .dw 0x6ed1, 0xcc16, 0x6ed1, 0xcc16, 0x21, 0 + .dw 0x6ed3, 0xcc16, 0x6eff, 0xcc16, 0x21, 0 + .dw 0x6f01, 0xcc16, 0x6f01, 0xcc16, 0x21, 0 + .dw 0x6f03, 0xcc16, 0x6f0f, 0xcc16, 0x21, 0 + .dw 0x6f11, 0xcc16, 0x6f11, 0xcc16, 0x21, 0 + .dw 0x6f13, 0xcc16, 0x6f3f, 0xcc16, 0x21, 0 + .dw 0x6f41, 0xcc16, 0x6f41, 0xcc16, 0x21, 0 + .dw 0x6f43, 0xcc16, 0x6f4f, 0xcc16, 0x21, 0 + .dw 0x6f51, 0xcc16, 0x6f51, 0xcc16, 0x21, 0 + .dw 0x6f53, 0xcc16, 0x6f7f, 0xcc16, 0x21, 0 + .dw 0x6f81, 0xcc16, 0x6f81, 0xcc16, 0x21, 0 + .dw 0x6f83, 0xcc16, 0x6f8f, 0xcc16, 0x21, 0 + .dw 0x6f91, 0xcc16, 0x6f91, 0xcc16, 0x21, 0 + .dw 0x6f93, 0xcc16, 0x6fbf, 0xcc16, 0x21, 0 + .dw 0x6fc1, 0xcc16, 0x6fc1, 0xcc16, 0x21, 0 + .dw 0x6fc3, 0xcc16, 0x6fcf, 0xcc16, 0x21, 0 + .dw 0x6fd1, 0xcc16, 0x6fd1, 0xcc16, 0x21, 0 + .dw 0x6fd3, 0xcc16, 0xffff, 0xcc16, 0x21, 0 + .dw 0x0001, 0xcc17, 0x0001, 0xcc17, 0x21, 0 + .dw 0x0003, 0xcc17, 0x000f, 0xcc17, 0x21, 0 + .dw 0x0011, 0xcc17, 0x0011, 0xcc17, 0x21, 0 + .dw 0x0013, 0xcc17, 0x003f, 0xcc17, 0x21, 0 + .dw 0x0041, 0xcc17, 0x0041, 0xcc17, 0x21, 0 + .dw 0x0043, 0xcc17, 0x004f, 0xcc17, 0x21, 0 + .dw 0x0051, 0xcc17, 0x0051, 0xcc17, 0x21, 0 + .dw 0x0053, 0xcc17, 0x007f, 0xcc17, 0x21, 0 + .dw 0x0081, 0xcc17, 0x0081, 0xcc17, 0x21, 0 + .dw 0x0083, 0xcc17, 0x008f, 0xcc17, 0x21, 0 + .dw 0x0091, 0xcc17, 0x0091, 0xcc17, 0x21, 0 + .dw 0x0093, 0xcc17, 0x00bf, 0xcc17, 0x21, 0 + .dw 0x00c1, 0xcc17, 0x00c1, 0xcc17, 0x21, 0 + .dw 0x00c3, 0xcc17, 0x00cf, 0xcc17, 0x21, 0 + .dw 0x00d1, 0xcc17, 0x00d1, 0xcc17, 0x21, 0 + .dw 0x00d3, 0xcc17, 0x00ff, 0xcc17, 0x21, 0 + .dw 0x0101, 0xcc17, 0x0101, 0xcc17, 0x21, 0 + .dw 0x0103, 0xcc17, 0x010f, 0xcc17, 0x21, 0 + .dw 0x0111, 0xcc17, 0x0111, 0xcc17, 0x21, 0 + .dw 0x0113, 0xcc17, 0x013f, 0xcc17, 0x21, 0 + .dw 0x0141, 0xcc17, 0x0141, 0xcc17, 0x21, 0 + .dw 0x0143, 0xcc17, 0x014f, 0xcc17, 0x21, 0 + .dw 0x0151, 0xcc17, 0x0151, 0xcc17, 0x21, 0 + .dw 0x0153, 0xcc17, 0x017f, 0xcc17, 0x21, 0 + .dw 0x0181, 0xcc17, 0x0181, 0xcc17, 0x21, 0 + .dw 0x0183, 0xcc17, 0x018f, 0xcc17, 0x21, 0 + .dw 0x0191, 0xcc17, 0x0191, 0xcc17, 0x21, 0 + .dw 0x0193, 0xcc17, 0x01bf, 0xcc17, 0x21, 0 + .dw 0x01c1, 0xcc17, 0x01c1, 0xcc17, 0x21, 0 + .dw 0x01c3, 0xcc17, 0x01cf, 0xcc17, 0x21, 0 + .dw 0x01d1, 0xcc17, 0x01d1, 0xcc17, 0x21, 0 + .dw 0x01d3, 0xcc17, 0x01ff, 0xcc17, 0x21, 0 + .dw 0x0201, 0xcc17, 0x0201, 0xcc17, 0x21, 0 + .dw 0x0203, 0xcc17, 0x020f, 0xcc17, 0x21, 0 + .dw 0x0211, 0xcc17, 0x0211, 0xcc17, 0x21, 0 + .dw 0x0213, 0xcc17, 0x023f, 0xcc17, 0x21, 0 + .dw 0x0241, 0xcc17, 0x0241, 0xcc17, 0x21, 0 + .dw 0x0243, 0xcc17, 0x024f, 0xcc17, 0x21, 0 + .dw 0x0251, 0xcc17, 0x0251, 0xcc17, 0x21, 0 + .dw 0x0253, 0xcc17, 0x027f, 0xcc17, 0x21, 0 + .dw 0x0281, 0xcc17, 0x0281, 0xcc17, 0x21, 0 + .dw 0x0283, 0xcc17, 0x028f, 0xcc17, 0x21, 0 + .dw 0x0291, 0xcc17, 0x0291, 0xcc17, 0x21, 0 + .dw 0x0293, 0xcc17, 0x02bf, 0xcc17, 0x21, 0 + .dw 0x02c1, 0xcc17, 0x02c1, 0xcc17, 0x21, 0 + .dw 0x02c3, 0xcc17, 0x02cf, 0xcc17, 0x21, 0 + .dw 0x02d1, 0xcc17, 0x02d1, 0xcc17, 0x21, 0 + .dw 0x02d3, 0xcc17, 0x02ff, 0xcc17, 0x21, 0 + .dw 0x0301, 0xcc17, 0x0301, 0xcc17, 0x21, 0 + .dw 0x0303, 0xcc17, 0x030f, 0xcc17, 0x21, 0 + .dw 0x0311, 0xcc17, 0x0311, 0xcc17, 0x21, 0 + .dw 0x0313, 0xcc17, 0x033f, 0xcc17, 0x21, 0 + .dw 0x0341, 0xcc17, 0x0341, 0xcc17, 0x21, 0 + .dw 0x0343, 0xcc17, 0x034f, 0xcc17, 0x21, 0 + .dw 0x0351, 0xcc17, 0x0351, 0xcc17, 0x21, 0 + .dw 0x0353, 0xcc17, 0x037f, 0xcc17, 0x21, 0 + .dw 0x0381, 0xcc17, 0x0381, 0xcc17, 0x21, 0 + .dw 0x0383, 0xcc17, 0x038f, 0xcc17, 0x21, 0 + .dw 0x0391, 0xcc17, 0x0391, 0xcc17, 0x21, 0 + .dw 0x0393, 0xcc17, 0x03bf, 0xcc17, 0x21, 0 + .dw 0x03c1, 0xcc17, 0x03c1, 0xcc17, 0x21, 0 + .dw 0x03c3, 0xcc17, 0x03cf, 0xcc17, 0x21, 0 + .dw 0x03d1, 0xcc17, 0x03d1, 0xcc17, 0x21, 0 + .dw 0x03d3, 0xcc17, 0x03ff, 0xcc17, 0x21, 0 + .dw 0x0401, 0xcc17, 0x0401, 0xcc17, 0x21, 0 + .dw 0x0403, 0xcc17, 0x040f, 0xcc17, 0x21, 0 + .dw 0x0411, 0xcc17, 0x0411, 0xcc17, 0x21, 0 + .dw 0x0413, 0xcc17, 0x043f, 0xcc17, 0x21, 0 + .dw 0x0441, 0xcc17, 0x0441, 0xcc17, 0x21, 0 + .dw 0x0443, 0xcc17, 0x044f, 0xcc17, 0x21, 0 + .dw 0x0451, 0xcc17, 0x0451, 0xcc17, 0x21, 0 + .dw 0x0453, 0xcc17, 0x047f, 0xcc17, 0x21, 0 + .dw 0x0481, 0xcc17, 0x0481, 0xcc17, 0x21, 0 + .dw 0x0483, 0xcc17, 0x048f, 0xcc17, 0x21, 0 + .dw 0x0491, 0xcc17, 0x0491, 0xcc17, 0x21, 0 + .dw 0x0493, 0xcc17, 0x04bf, 0xcc17, 0x21, 0 + .dw 0x04c1, 0xcc17, 0x04c1, 0xcc17, 0x21, 0 + .dw 0x04c3, 0xcc17, 0x04cf, 0xcc17, 0x21, 0 + .dw 0x04d1, 0xcc17, 0x04d1, 0xcc17, 0x21, 0 + .dw 0x04d3, 0xcc17, 0x04ff, 0xcc17, 0x21, 0 + .dw 0x0501, 0xcc17, 0x0501, 0xcc17, 0x21, 0 + .dw 0x0503, 0xcc17, 0x050f, 0xcc17, 0x21, 0 + .dw 0x0511, 0xcc17, 0x0511, 0xcc17, 0x21, 0 + .dw 0x0513, 0xcc17, 0x053f, 0xcc17, 0x21, 0 + .dw 0x0541, 0xcc17, 0x0541, 0xcc17, 0x21, 0 + .dw 0x0543, 0xcc17, 0x054f, 0xcc17, 0x21, 0 + .dw 0x0551, 0xcc17, 0x0551, 0xcc17, 0x21, 0 + .dw 0x0553, 0xcc17, 0x057f, 0xcc17, 0x21, 0 + .dw 0x0581, 0xcc17, 0x0581, 0xcc17, 0x21, 0 + .dw 0x0583, 0xcc17, 0x058f, 0xcc17, 0x21, 0 + .dw 0x0591, 0xcc17, 0x0591, 0xcc17, 0x21, 0 + .dw 0x0593, 0xcc17, 0x05bf, 0xcc17, 0x21, 0 + .dw 0x05c1, 0xcc17, 0x05c1, 0xcc17, 0x21, 0 + .dw 0x05c3, 0xcc17, 0x05cf, 0xcc17, 0x21, 0 + .dw 0x05d1, 0xcc17, 0x05d1, 0xcc17, 0x21, 0 + .dw 0x05d3, 0xcc17, 0x05ff, 0xcc17, 0x21, 0 + .dw 0x0601, 0xcc17, 0x0601, 0xcc17, 0x21, 0 + .dw 0x0603, 0xcc17, 0x060f, 0xcc17, 0x21, 0 + .dw 0x0611, 0xcc17, 0x0611, 0xcc17, 0x21, 0 + .dw 0x0613, 0xcc17, 0x063f, 0xcc17, 0x21, 0 + .dw 0x0641, 0xcc17, 0x0641, 0xcc17, 0x21, 0 + .dw 0x0643, 0xcc17, 0x064f, 0xcc17, 0x21, 0 + .dw 0x0651, 0xcc17, 0x0651, 0xcc17, 0x21, 0 + .dw 0x0653, 0xcc17, 0x067f, 0xcc17, 0x21, 0 + .dw 0x0681, 0xcc17, 0x0681, 0xcc17, 0x21, 0 + .dw 0x0683, 0xcc17, 0x068f, 0xcc17, 0x21, 0 + .dw 0x0691, 0xcc17, 0x0691, 0xcc17, 0x21, 0 + .dw 0x0693, 0xcc17, 0x06bf, 0xcc17, 0x21, 0 + .dw 0x06c1, 0xcc17, 0x06c1, 0xcc17, 0x21, 0 + .dw 0x06c3, 0xcc17, 0x06cf, 0xcc17, 0x21, 0 + .dw 0x06d1, 0xcc17, 0x06d1, 0xcc17, 0x21, 0 + .dw 0x06d3, 0xcc17, 0x06ff, 0xcc17, 0x21, 0 + .dw 0x0701, 0xcc17, 0x0701, 0xcc17, 0x21, 0 + .dw 0x0703, 0xcc17, 0x070f, 0xcc17, 0x21, 0 + .dw 0x0711, 0xcc17, 0x0711, 0xcc17, 0x21, 0 + .dw 0x0713, 0xcc17, 0x073f, 0xcc17, 0x21, 0 + .dw 0x0741, 0xcc17, 0x0741, 0xcc17, 0x21, 0 + .dw 0x0743, 0xcc17, 0x074f, 0xcc17, 0x21, 0 + .dw 0x0751, 0xcc17, 0x0751, 0xcc17, 0x21, 0 + .dw 0x0753, 0xcc17, 0x077f, 0xcc17, 0x21, 0 + .dw 0x0781, 0xcc17, 0x0781, 0xcc17, 0x21, 0 + .dw 0x0783, 0xcc17, 0x078f, 0xcc17, 0x21, 0 + .dw 0x0791, 0xcc17, 0x0791, 0xcc17, 0x21, 0 + .dw 0x0793, 0xcc17, 0x07bf, 0xcc17, 0x21, 0 + .dw 0x07c1, 0xcc17, 0x07c1, 0xcc17, 0x21, 0 + .dw 0x07c3, 0xcc17, 0x07cf, 0xcc17, 0x21, 0 + .dw 0x07d1, 0xcc17, 0x07d1, 0xcc17, 0x21, 0 + .dw 0x07d3, 0xcc17, 0x07ff, 0xcc17, 0x21, 0 + .dw 0x0801, 0xcc17, 0x0801, 0xcc17, 0x21, 0 + .dw 0x0803, 0xcc17, 0x080f, 0xcc17, 0x21, 0 + .dw 0x0811, 0xcc17, 0x0811, 0xcc17, 0x21, 0 + .dw 0x0813, 0xcc17, 0x083f, 0xcc17, 0x21, 0 + .dw 0x0841, 0xcc17, 0x0841, 0xcc17, 0x21, 0 + .dw 0x0843, 0xcc17, 0x084f, 0xcc17, 0x21, 0 + .dw 0x0851, 0xcc17, 0x0851, 0xcc17, 0x21, 0 + .dw 0x0853, 0xcc17, 0x087f, 0xcc17, 0x21, 0 + .dw 0x0881, 0xcc17, 0x0881, 0xcc17, 0x21, 0 + .dw 0x0883, 0xcc17, 0x088f, 0xcc17, 0x21, 0 + .dw 0x0891, 0xcc17, 0x0891, 0xcc17, 0x21, 0 + .dw 0x0893, 0xcc17, 0x08bf, 0xcc17, 0x21, 0 + .dw 0x08c1, 0xcc17, 0x08c1, 0xcc17, 0x21, 0 + .dw 0x08c3, 0xcc17, 0x08cf, 0xcc17, 0x21, 0 + .dw 0x08d1, 0xcc17, 0x08d1, 0xcc17, 0x21, 0 + .dw 0x08d3, 0xcc17, 0x08ff, 0xcc17, 0x21, 0 + .dw 0x0901, 0xcc17, 0x0901, 0xcc17, 0x21, 0 + .dw 0x0903, 0xcc17, 0x090f, 0xcc17, 0x21, 0 + .dw 0x0911, 0xcc17, 0x0911, 0xcc17, 0x21, 0 + .dw 0x0913, 0xcc17, 0x093f, 0xcc17, 0x21, 0 + .dw 0x0941, 0xcc17, 0x0941, 0xcc17, 0x21, 0 + .dw 0x0943, 0xcc17, 0x094f, 0xcc17, 0x21, 0 + .dw 0x0951, 0xcc17, 0x0951, 0xcc17, 0x21, 0 + .dw 0x0953, 0xcc17, 0x097f, 0xcc17, 0x21, 0 + .dw 0x0981, 0xcc17, 0x0981, 0xcc17, 0x21, 0 + .dw 0x0983, 0xcc17, 0x098f, 0xcc17, 0x21, 0 + .dw 0x0991, 0xcc17, 0x0991, 0xcc17, 0x21, 0 + .dw 0x0993, 0xcc17, 0x09bf, 0xcc17, 0x21, 0 + .dw 0x09c1, 0xcc17, 0x09c1, 0xcc17, 0x21, 0 + .dw 0x09c3, 0xcc17, 0x09cf, 0xcc17, 0x21, 0 + .dw 0x09d1, 0xcc17, 0x09d1, 0xcc17, 0x21, 0 + .dw 0x09d3, 0xcc17, 0x09ff, 0xcc17, 0x21, 0 + .dw 0x0a01, 0xcc17, 0x0a01, 0xcc17, 0x21, 0 + .dw 0x0a03, 0xcc17, 0x0a0f, 0xcc17, 0x21, 0 + .dw 0x0a11, 0xcc17, 0x0a11, 0xcc17, 0x21, 0 + .dw 0x0a13, 0xcc17, 0x0a3f, 0xcc17, 0x21, 0 + .dw 0x0a41, 0xcc17, 0x0a41, 0xcc17, 0x21, 0 + .dw 0x0a43, 0xcc17, 0x0a4f, 0xcc17, 0x21, 0 + .dw 0x0a51, 0xcc17, 0x0a51, 0xcc17, 0x21, 0 + .dw 0x0a53, 0xcc17, 0x0a7f, 0xcc17, 0x21, 0 + .dw 0x0a81, 0xcc17, 0x0a81, 0xcc17, 0x21, 0 + .dw 0x0a83, 0xcc17, 0x0a8f, 0xcc17, 0x21, 0 + .dw 0x0a91, 0xcc17, 0x0a91, 0xcc17, 0x21, 0 + .dw 0x0a93, 0xcc17, 0x0abf, 0xcc17, 0x21, 0 + .dw 0x0ac1, 0xcc17, 0x0ac1, 0xcc17, 0x21, 0 + .dw 0x0ac3, 0xcc17, 0x0acf, 0xcc17, 0x21, 0 + .dw 0x0ad1, 0xcc17, 0x0ad1, 0xcc17, 0x21, 0 + .dw 0x0ad3, 0xcc17, 0x0aff, 0xcc17, 0x21, 0 + .dw 0x0b01, 0xcc17, 0x0b01, 0xcc17, 0x21, 0 + .dw 0x0b03, 0xcc17, 0x0b0f, 0xcc17, 0x21, 0 + .dw 0x0b11, 0xcc17, 0x0b11, 0xcc17, 0x21, 0 + .dw 0x0b13, 0xcc17, 0x0b3f, 0xcc17, 0x21, 0 + .dw 0x0b41, 0xcc17, 0x0b41, 0xcc17, 0x21, 0 + .dw 0x0b43, 0xcc17, 0x0b4f, 0xcc17, 0x21, 0 + .dw 0x0b51, 0xcc17, 0x0b51, 0xcc17, 0x21, 0 + .dw 0x0b53, 0xcc17, 0x0b7f, 0xcc17, 0x21, 0 + .dw 0x0b81, 0xcc17, 0x0b81, 0xcc17, 0x21, 0 + .dw 0x0b83, 0xcc17, 0x0b8f, 0xcc17, 0x21, 0 + .dw 0x0b91, 0xcc17, 0x0b91, 0xcc17, 0x21, 0 + .dw 0x0b93, 0xcc17, 0x0bbf, 0xcc17, 0x21, 0 + .dw 0x0bc1, 0xcc17, 0x0bc1, 0xcc17, 0x21, 0 + .dw 0x0bc3, 0xcc17, 0x0bcf, 0xcc17, 0x21, 0 + .dw 0x0bd1, 0xcc17, 0x0bd1, 0xcc17, 0x21, 0 + .dw 0x0bd3, 0xcc17, 0x0bff, 0xcc17, 0x21, 0 + .dw 0x0c01, 0xcc17, 0x0c01, 0xcc17, 0x21, 0 + .dw 0x0c03, 0xcc17, 0x0c0f, 0xcc17, 0x21, 0 + .dw 0x0c11, 0xcc17, 0x0c11, 0xcc17, 0x21, 0 + .dw 0x0c13, 0xcc17, 0x0c3f, 0xcc17, 0x21, 0 + .dw 0x0c41, 0xcc17, 0x0c41, 0xcc17, 0x21, 0 + .dw 0x0c43, 0xcc17, 0x0c4f, 0xcc17, 0x21, 0 + .dw 0x0c51, 0xcc17, 0x0c51, 0xcc17, 0x21, 0 + .dw 0x0c53, 0xcc17, 0x0c7f, 0xcc17, 0x21, 0 + .dw 0x0c81, 0xcc17, 0x0c81, 0xcc17, 0x21, 0 + .dw 0x0c83, 0xcc17, 0x0c8f, 0xcc17, 0x21, 0 + .dw 0x0c91, 0xcc17, 0x0c91, 0xcc17, 0x21, 0 + .dw 0x0c93, 0xcc17, 0x0cbf, 0xcc17, 0x21, 0 + .dw 0x0cc1, 0xcc17, 0x0cc1, 0xcc17, 0x21, 0 + .dw 0x0cc3, 0xcc17, 0x0ccf, 0xcc17, 0x21, 0 + .dw 0x0cd1, 0xcc17, 0x0cd1, 0xcc17, 0x21, 0 + .dw 0x0cd3, 0xcc17, 0x0cff, 0xcc17, 0x21, 0 + .dw 0x0d01, 0xcc17, 0x0d01, 0xcc17, 0x21, 0 + .dw 0x0d03, 0xcc17, 0x0d0f, 0xcc17, 0x21, 0 + .dw 0x0d11, 0xcc17, 0x0d11, 0xcc17, 0x21, 0 + .dw 0x0d13, 0xcc17, 0x0d3f, 0xcc17, 0x21, 0 + .dw 0x0d41, 0xcc17, 0x0d41, 0xcc17, 0x21, 0 + .dw 0x0d43, 0xcc17, 0x0d4f, 0xcc17, 0x21, 0 + .dw 0x0d51, 0xcc17, 0x0d51, 0xcc17, 0x21, 0 + .dw 0x0d53, 0xcc17, 0x0d7f, 0xcc17, 0x21, 0 + .dw 0x0d81, 0xcc17, 0x0d81, 0xcc17, 0x21, 0 + .dw 0x0d83, 0xcc17, 0x0d8f, 0xcc17, 0x21, 0 + .dw 0x0d91, 0xcc17, 0x0d91, 0xcc17, 0x21, 0 + .dw 0x0d93, 0xcc17, 0x0dbf, 0xcc17, 0x21, 0 + .dw 0x0dc1, 0xcc17, 0x0dc1, 0xcc17, 0x21, 0 + .dw 0x0dc3, 0xcc17, 0x0dcf, 0xcc17, 0x21, 0 + .dw 0x0dd1, 0xcc17, 0x0dd1, 0xcc17, 0x21, 0 + .dw 0x0dd3, 0xcc17, 0x0dff, 0xcc17, 0x21, 0 + .dw 0x0e01, 0xcc17, 0x0e01, 0xcc17, 0x21, 0 + .dw 0x0e03, 0xcc17, 0x0e0f, 0xcc17, 0x21, 0 + .dw 0x0e11, 0xcc17, 0x0e11, 0xcc17, 0x21, 0 + .dw 0x0e13, 0xcc17, 0x0e3f, 0xcc17, 0x21, 0 + .dw 0x0e41, 0xcc17, 0x0e41, 0xcc17, 0x21, 0 + .dw 0x0e43, 0xcc17, 0x0e4f, 0xcc17, 0x21, 0 + .dw 0x0e51, 0xcc17, 0x0e51, 0xcc17, 0x21, 0 + .dw 0x0e53, 0xcc17, 0x0e7f, 0xcc17, 0x21, 0 + .dw 0x0e81, 0xcc17, 0x0e81, 0xcc17, 0x21, 0 + .dw 0x0e83, 0xcc17, 0x0e8f, 0xcc17, 0x21, 0 + .dw 0x0e91, 0xcc17, 0x0e91, 0xcc17, 0x21, 0 + .dw 0x0e93, 0xcc17, 0x0ebf, 0xcc17, 0x21, 0 + .dw 0x0ec1, 0xcc17, 0x0ec1, 0xcc17, 0x21, 0 + .dw 0x0ec3, 0xcc17, 0x0ecf, 0xcc17, 0x21, 0 + .dw 0x0ed1, 0xcc17, 0x0ed1, 0xcc17, 0x21, 0 + .dw 0x0ed3, 0xcc17, 0x0eff, 0xcc17, 0x21, 0 + .dw 0x0f01, 0xcc17, 0x0f01, 0xcc17, 0x21, 0 + .dw 0x0f03, 0xcc17, 0x0f0f, 0xcc17, 0x21, 0 + .dw 0x0f11, 0xcc17, 0x0f11, 0xcc17, 0x21, 0 + .dw 0x0f13, 0xcc17, 0x0f3f, 0xcc17, 0x21, 0 + .dw 0x0f41, 0xcc17, 0x0f41, 0xcc17, 0x21, 0 + .dw 0x0f43, 0xcc17, 0x0f4f, 0xcc17, 0x21, 0 + .dw 0x0f51, 0xcc17, 0x0f51, 0xcc17, 0x21, 0 + .dw 0x0f53, 0xcc17, 0x0f7f, 0xcc17, 0x21, 0 + .dw 0x0f81, 0xcc17, 0x0f81, 0xcc17, 0x21, 0 + .dw 0x0f83, 0xcc17, 0x0f8f, 0xcc17, 0x21, 0 + .dw 0x0f91, 0xcc17, 0x0f91, 0xcc17, 0x21, 0 + .dw 0x0f93, 0xcc17, 0x0fbf, 0xcc17, 0x21, 0 + .dw 0x0fc1, 0xcc17, 0x0fc1, 0xcc17, 0x21, 0 + .dw 0x0fc3, 0xcc17, 0x0fcf, 0xcc17, 0x21, 0 + .dw 0x0fd1, 0xcc17, 0x0fd1, 0xcc17, 0x21, 0 + .dw 0x0fd3, 0xcc17, 0x1fff, 0xcc17, 0x21, 0 + .dw 0x2001, 0xcc17, 0x2001, 0xcc17, 0x21, 0 + .dw 0x2003, 0xcc17, 0x200f, 0xcc17, 0x21, 0 + .dw 0x2011, 0xcc17, 0x2011, 0xcc17, 0x21, 0 + .dw 0x2013, 0xcc17, 0x203f, 0xcc17, 0x21, 0 + .dw 0x2041, 0xcc17, 0x2041, 0xcc17, 0x21, 0 + .dw 0x2043, 0xcc17, 0x204f, 0xcc17, 0x21, 0 + .dw 0x2051, 0xcc17, 0x2051, 0xcc17, 0x21, 0 + .dw 0x2053, 0xcc17, 0x207f, 0xcc17, 0x21, 0 + .dw 0x2081, 0xcc17, 0x2081, 0xcc17, 0x21, 0 + .dw 0x2083, 0xcc17, 0x208f, 0xcc17, 0x21, 0 + .dw 0x2091, 0xcc17, 0x2091, 0xcc17, 0x21, 0 + .dw 0x2093, 0xcc17, 0x20bf, 0xcc17, 0x21, 0 + .dw 0x20c1, 0xcc17, 0x20c1, 0xcc17, 0x21, 0 + .dw 0x20c3, 0xcc17, 0x20cf, 0xcc17, 0x21, 0 + .dw 0x20d1, 0xcc17, 0x20d1, 0xcc17, 0x21, 0 + .dw 0x20d3, 0xcc17, 0x20ff, 0xcc17, 0x21, 0 + .dw 0x2101, 0xcc17, 0x2101, 0xcc17, 0x21, 0 + .dw 0x2103, 0xcc17, 0x210f, 0xcc17, 0x21, 0 + .dw 0x2111, 0xcc17, 0x2111, 0xcc17, 0x21, 0 + .dw 0x2113, 0xcc17, 0x213f, 0xcc17, 0x21, 0 + .dw 0x2141, 0xcc17, 0x2141, 0xcc17, 0x21, 0 + .dw 0x2143, 0xcc17, 0x214f, 0xcc17, 0x21, 0 + .dw 0x2151, 0xcc17, 0x2151, 0xcc17, 0x21, 0 + .dw 0x2153, 0xcc17, 0x217f, 0xcc17, 0x21, 0 + .dw 0x2181, 0xcc17, 0x2181, 0xcc17, 0x21, 0 + .dw 0x2183, 0xcc17, 0x218f, 0xcc17, 0x21, 0 + .dw 0x2191, 0xcc17, 0x2191, 0xcc17, 0x21, 0 + .dw 0x2193, 0xcc17, 0x21bf, 0xcc17, 0x21, 0 + .dw 0x21c1, 0xcc17, 0x21c1, 0xcc17, 0x21, 0 + .dw 0x21c3, 0xcc17, 0x21cf, 0xcc17, 0x21, 0 + .dw 0x21d1, 0xcc17, 0x21d1, 0xcc17, 0x21, 0 + .dw 0x21d3, 0xcc17, 0x21ff, 0xcc17, 0x21, 0 + .dw 0x2201, 0xcc17, 0x2201, 0xcc17, 0x21, 0 + .dw 0x2203, 0xcc17, 0x220f, 0xcc17, 0x21, 0 + .dw 0x2211, 0xcc17, 0x2211, 0xcc17, 0x21, 0 + .dw 0x2213, 0xcc17, 0x223f, 0xcc17, 0x21, 0 + .dw 0x2241, 0xcc17, 0x2241, 0xcc17, 0x21, 0 + .dw 0x2243, 0xcc17, 0x224f, 0xcc17, 0x21, 0 + .dw 0x2251, 0xcc17, 0x2251, 0xcc17, 0x21, 0 + .dw 0x2253, 0xcc17, 0x227f, 0xcc17, 0x21, 0 + .dw 0x2281, 0xcc17, 0x2281, 0xcc17, 0x21, 0 + .dw 0x2283, 0xcc17, 0x228f, 0xcc17, 0x21, 0 + .dw 0x2291, 0xcc17, 0x2291, 0xcc17, 0x21, 0 + .dw 0x2293, 0xcc17, 0x22bf, 0xcc17, 0x21, 0 + .dw 0x22c1, 0xcc17, 0x22c1, 0xcc17, 0x21, 0 + .dw 0x22c3, 0xcc17, 0x22cf, 0xcc17, 0x21, 0 + .dw 0x22d1, 0xcc17, 0x22d1, 0xcc17, 0x21, 0 + .dw 0x22d3, 0xcc17, 0x22ff, 0xcc17, 0x21, 0 + .dw 0x2301, 0xcc17, 0x2301, 0xcc17, 0x21, 0 + .dw 0x2303, 0xcc17, 0x230f, 0xcc17, 0x21, 0 + .dw 0x2311, 0xcc17, 0x2311, 0xcc17, 0x21, 0 + .dw 0x2313, 0xcc17, 0x233f, 0xcc17, 0x21, 0 + .dw 0x2341, 0xcc17, 0x2341, 0xcc17, 0x21, 0 + .dw 0x2343, 0xcc17, 0x234f, 0xcc17, 0x21, 0 + .dw 0x2351, 0xcc17, 0x2351, 0xcc17, 0x21, 0 + .dw 0x2353, 0xcc17, 0x237f, 0xcc17, 0x21, 0 + .dw 0x2381, 0xcc17, 0x2381, 0xcc17, 0x21, 0 + .dw 0x2383, 0xcc17, 0x238f, 0xcc17, 0x21, 0 + .dw 0x2391, 0xcc17, 0x2391, 0xcc17, 0x21, 0 + .dw 0x2393, 0xcc17, 0x23bf, 0xcc17, 0x21, 0 + .dw 0x23c1, 0xcc17, 0x23c1, 0xcc17, 0x21, 0 + .dw 0x23c3, 0xcc17, 0x23cf, 0xcc17, 0x21, 0 + .dw 0x23d1, 0xcc17, 0x23d1, 0xcc17, 0x21, 0 + .dw 0x23d3, 0xcc17, 0x23ff, 0xcc17, 0x21, 0 + .dw 0x2401, 0xcc17, 0x2401, 0xcc17, 0x21, 0 + .dw 0x2403, 0xcc17, 0x240f, 0xcc17, 0x21, 0 + .dw 0x2411, 0xcc17, 0x2411, 0xcc17, 0x21, 0 + .dw 0x2413, 0xcc17, 0x243f, 0xcc17, 0x21, 0 + .dw 0x2441, 0xcc17, 0x2441, 0xcc17, 0x21, 0 + .dw 0x2443, 0xcc17, 0x244f, 0xcc17, 0x21, 0 + .dw 0x2451, 0xcc17, 0x2451, 0xcc17, 0x21, 0 + .dw 0x2453, 0xcc17, 0x247f, 0xcc17, 0x21, 0 + .dw 0x2481, 0xcc17, 0x2481, 0xcc17, 0x21, 0 + .dw 0x2483, 0xcc17, 0x248f, 0xcc17, 0x21, 0 + .dw 0x2491, 0xcc17, 0x2491, 0xcc17, 0x21, 0 + .dw 0x2493, 0xcc17, 0x24bf, 0xcc17, 0x21, 0 + .dw 0x24c1, 0xcc17, 0x24c1, 0xcc17, 0x21, 0 + .dw 0x24c3, 0xcc17, 0x24cf, 0xcc17, 0x21, 0 + .dw 0x24d1, 0xcc17, 0x24d1, 0xcc17, 0x21, 0 + .dw 0x24d3, 0xcc17, 0x24ff, 0xcc17, 0x21, 0 + .dw 0x2501, 0xcc17, 0x2501, 0xcc17, 0x21, 0 + .dw 0x2503, 0xcc17, 0x250f, 0xcc17, 0x21, 0 + .dw 0x2511, 0xcc17, 0x2511, 0xcc17, 0x21, 0 + .dw 0x2513, 0xcc17, 0x253f, 0xcc17, 0x21, 0 + .dw 0x2541, 0xcc17, 0x2541, 0xcc17, 0x21, 0 + .dw 0x2543, 0xcc17, 0x254f, 0xcc17, 0x21, 0 + .dw 0x2551, 0xcc17, 0x2551, 0xcc17, 0x21, 0 + .dw 0x2553, 0xcc17, 0x257f, 0xcc17, 0x21, 0 + .dw 0x2581, 0xcc17, 0x2581, 0xcc17, 0x21, 0 + .dw 0x2583, 0xcc17, 0x258f, 0xcc17, 0x21, 0 + .dw 0x2591, 0xcc17, 0x2591, 0xcc17, 0x21, 0 + .dw 0x2593, 0xcc17, 0x25bf, 0xcc17, 0x21, 0 + .dw 0x25c1, 0xcc17, 0x25c1, 0xcc17, 0x21, 0 + .dw 0x25c3, 0xcc17, 0x25cf, 0xcc17, 0x21, 0 + .dw 0x25d1, 0xcc17, 0x25d1, 0xcc17, 0x21, 0 + .dw 0x25d3, 0xcc17, 0x25ff, 0xcc17, 0x21, 0 + .dw 0x2601, 0xcc17, 0x2601, 0xcc17, 0x21, 0 + .dw 0x2603, 0xcc17, 0x260f, 0xcc17, 0x21, 0 + .dw 0x2611, 0xcc17, 0x2611, 0xcc17, 0x21, 0 + .dw 0x2613, 0xcc17, 0x263f, 0xcc17, 0x21, 0 + .dw 0x2641, 0xcc17, 0x2641, 0xcc17, 0x21, 0 + .dw 0x2643, 0xcc17, 0x264f, 0xcc17, 0x21, 0 + .dw 0x2651, 0xcc17, 0x2651, 0xcc17, 0x21, 0 + .dw 0x2653, 0xcc17, 0x267f, 0xcc17, 0x21, 0 + .dw 0x2681, 0xcc17, 0x2681, 0xcc17, 0x21, 0 + .dw 0x2683, 0xcc17, 0x268f, 0xcc17, 0x21, 0 + .dw 0x2691, 0xcc17, 0x2691, 0xcc17, 0x21, 0 + .dw 0x2693, 0xcc17, 0x26bf, 0xcc17, 0x21, 0 + .dw 0x26c1, 0xcc17, 0x26c1, 0xcc17, 0x21, 0 + .dw 0x26c3, 0xcc17, 0x26cf, 0xcc17, 0x21, 0 + .dw 0x26d1, 0xcc17, 0x26d1, 0xcc17, 0x21, 0 + .dw 0x26d3, 0xcc17, 0x26ff, 0xcc17, 0x21, 0 + .dw 0x2701, 0xcc17, 0x2701, 0xcc17, 0x21, 0 + .dw 0x2703, 0xcc17, 0x270f, 0xcc17, 0x21, 0 + .dw 0x2711, 0xcc17, 0x2711, 0xcc17, 0x21, 0 + .dw 0x2713, 0xcc17, 0x273f, 0xcc17, 0x21, 0 + .dw 0x2741, 0xcc17, 0x2741, 0xcc17, 0x21, 0 + .dw 0x2743, 0xcc17, 0x274f, 0xcc17, 0x21, 0 + .dw 0x2751, 0xcc17, 0x2751, 0xcc17, 0x21, 0 + .dw 0x2753, 0xcc17, 0x277f, 0xcc17, 0x21, 0 + .dw 0x2781, 0xcc17, 0x2781, 0xcc17, 0x21, 0 + .dw 0x2783, 0xcc17, 0x278f, 0xcc17, 0x21, 0 + .dw 0x2791, 0xcc17, 0x2791, 0xcc17, 0x21, 0 + .dw 0x2793, 0xcc17, 0x27bf, 0xcc17, 0x21, 0 + .dw 0x27c1, 0xcc17, 0x27c1, 0xcc17, 0x21, 0 + .dw 0x27c3, 0xcc17, 0x27cf, 0xcc17, 0x21, 0 + .dw 0x27d1, 0xcc17, 0x27d1, 0xcc17, 0x21, 0 + .dw 0x27d3, 0xcc17, 0x27ff, 0xcc17, 0x21, 0 + .dw 0x2801, 0xcc17, 0x2801, 0xcc17, 0x21, 0 + .dw 0x2803, 0xcc17, 0x280f, 0xcc17, 0x21, 0 + .dw 0x2811, 0xcc17, 0x2811, 0xcc17, 0x21, 0 + .dw 0x2813, 0xcc17, 0x283f, 0xcc17, 0x21, 0 + .dw 0x2841, 0xcc17, 0x2841, 0xcc17, 0x21, 0 + .dw 0x2843, 0xcc17, 0x284f, 0xcc17, 0x21, 0 + .dw 0x2851, 0xcc17, 0x2851, 0xcc17, 0x21, 0 + .dw 0x2853, 0xcc17, 0x287f, 0xcc17, 0x21, 0 + .dw 0x2881, 0xcc17, 0x2881, 0xcc17, 0x21, 0 + .dw 0x2883, 0xcc17, 0x288f, 0xcc17, 0x21, 0 + .dw 0x2891, 0xcc17, 0x2891, 0xcc17, 0x21, 0 + .dw 0x2893, 0xcc17, 0x28bf, 0xcc17, 0x21, 0 + .dw 0x28c1, 0xcc17, 0x28c1, 0xcc17, 0x21, 0 + .dw 0x28c3, 0xcc17, 0x28cf, 0xcc17, 0x21, 0 + .dw 0x28d1, 0xcc17, 0x28d1, 0xcc17, 0x21, 0 + .dw 0x28d3, 0xcc17, 0x28ff, 0xcc17, 0x21, 0 + .dw 0x2901, 0xcc17, 0x2901, 0xcc17, 0x21, 0 + .dw 0x2903, 0xcc17, 0x290f, 0xcc17, 0x21, 0 + .dw 0x2911, 0xcc17, 0x2911, 0xcc17, 0x21, 0 + .dw 0x2913, 0xcc17, 0x293f, 0xcc17, 0x21, 0 + .dw 0x2941, 0xcc17, 0x2941, 0xcc17, 0x21, 0 + .dw 0x2943, 0xcc17, 0x294f, 0xcc17, 0x21, 0 + .dw 0x2951, 0xcc17, 0x2951, 0xcc17, 0x21, 0 + .dw 0x2953, 0xcc17, 0x297f, 0xcc17, 0x21, 0 + .dw 0x2981, 0xcc17, 0x2981, 0xcc17, 0x21, 0 + .dw 0x2983, 0xcc17, 0x298f, 0xcc17, 0x21, 0 + .dw 0x2991, 0xcc17, 0x2991, 0xcc17, 0x21, 0 + .dw 0x2993, 0xcc17, 0x29bf, 0xcc17, 0x21, 0 + .dw 0x29c1, 0xcc17, 0x29c1, 0xcc17, 0x21, 0 + .dw 0x29c3, 0xcc17, 0x29cf, 0xcc17, 0x21, 0 + .dw 0x29d1, 0xcc17, 0x29d1, 0xcc17, 0x21, 0 + .dw 0x29d3, 0xcc17, 0x29ff, 0xcc17, 0x21, 0 + .dw 0x2a01, 0xcc17, 0x2a01, 0xcc17, 0x21, 0 + .dw 0x2a03, 0xcc17, 0x2a0f, 0xcc17, 0x21, 0 + .dw 0x2a11, 0xcc17, 0x2a11, 0xcc17, 0x21, 0 + .dw 0x2a13, 0xcc17, 0x2a3f, 0xcc17, 0x21, 0 + .dw 0x2a41, 0xcc17, 0x2a41, 0xcc17, 0x21, 0 + .dw 0x2a43, 0xcc17, 0x2a4f, 0xcc17, 0x21, 0 + .dw 0x2a51, 0xcc17, 0x2a51, 0xcc17, 0x21, 0 + .dw 0x2a53, 0xcc17, 0x2a7f, 0xcc17, 0x21, 0 + .dw 0x2a81, 0xcc17, 0x2a81, 0xcc17, 0x21, 0 + .dw 0x2a83, 0xcc17, 0x2a8f, 0xcc17, 0x21, 0 + .dw 0x2a91, 0xcc17, 0x2a91, 0xcc17, 0x21, 0 + .dw 0x2a93, 0xcc17, 0x2abf, 0xcc17, 0x21, 0 + .dw 0x2ac1, 0xcc17, 0x2ac1, 0xcc17, 0x21, 0 + .dw 0x2ac3, 0xcc17, 0x2acf, 0xcc17, 0x21, 0 + .dw 0x2ad1, 0xcc17, 0x2ad1, 0xcc17, 0x21, 0 + .dw 0x2ad3, 0xcc17, 0x2aff, 0xcc17, 0x21, 0 + .dw 0x2b01, 0xcc17, 0x2b01, 0xcc17, 0x21, 0 + .dw 0x2b03, 0xcc17, 0x2b0f, 0xcc17, 0x21, 0 + .dw 0x2b11, 0xcc17, 0x2b11, 0xcc17, 0x21, 0 + .dw 0x2b13, 0xcc17, 0x2b3f, 0xcc17, 0x21, 0 + .dw 0x2b41, 0xcc17, 0x2b41, 0xcc17, 0x21, 0 + .dw 0x2b43, 0xcc17, 0x2b4f, 0xcc17, 0x21, 0 + .dw 0x2b51, 0xcc17, 0x2b51, 0xcc17, 0x21, 0 + .dw 0x2b53, 0xcc17, 0x2b7f, 0xcc17, 0x21, 0 + .dw 0x2b81, 0xcc17, 0x2b81, 0xcc17, 0x21, 0 + .dw 0x2b83, 0xcc17, 0x2b8f, 0xcc17, 0x21, 0 + .dw 0x2b91, 0xcc17, 0x2b91, 0xcc17, 0x21, 0 + .dw 0x2b93, 0xcc17, 0x2bbf, 0xcc17, 0x21, 0 + .dw 0x2bc1, 0xcc17, 0x2bc1, 0xcc17, 0x21, 0 + .dw 0x2bc3, 0xcc17, 0x2bcf, 0xcc17, 0x21, 0 + .dw 0x2bd1, 0xcc17, 0x2bd1, 0xcc17, 0x21, 0 + .dw 0x2bd3, 0xcc17, 0x2bff, 0xcc17, 0x21, 0 + .dw 0x2c01, 0xcc17, 0x2c01, 0xcc17, 0x21, 0 + .dw 0x2c03, 0xcc17, 0x2c0f, 0xcc17, 0x21, 0 + .dw 0x2c11, 0xcc17, 0x2c11, 0xcc17, 0x21, 0 + .dw 0x2c13, 0xcc17, 0x2c3f, 0xcc17, 0x21, 0 + .dw 0x2c41, 0xcc17, 0x2c41, 0xcc17, 0x21, 0 + .dw 0x2c43, 0xcc17, 0x2c4f, 0xcc17, 0x21, 0 + .dw 0x2c51, 0xcc17, 0x2c51, 0xcc17, 0x21, 0 + .dw 0x2c53, 0xcc17, 0x2c7f, 0xcc17, 0x21, 0 + .dw 0x2c81, 0xcc17, 0x2c81, 0xcc17, 0x21, 0 + .dw 0x2c83, 0xcc17, 0x2c8f, 0xcc17, 0x21, 0 + .dw 0x2c91, 0xcc17, 0x2c91, 0xcc17, 0x21, 0 + .dw 0x2c93, 0xcc17, 0x2cbf, 0xcc17, 0x21, 0 + .dw 0x2cc1, 0xcc17, 0x2cc1, 0xcc17, 0x21, 0 + .dw 0x2cc3, 0xcc17, 0x2ccf, 0xcc17, 0x21, 0 + .dw 0x2cd1, 0xcc17, 0x2cd1, 0xcc17, 0x21, 0 + .dw 0x2cd3, 0xcc17, 0x2cff, 0xcc17, 0x21, 0 + .dw 0x2d01, 0xcc17, 0x2d01, 0xcc17, 0x21, 0 + .dw 0x2d03, 0xcc17, 0x2d0f, 0xcc17, 0x21, 0 + .dw 0x2d11, 0xcc17, 0x2d11, 0xcc17, 0x21, 0 + .dw 0x2d13, 0xcc17, 0x2d3f, 0xcc17, 0x21, 0 + .dw 0x2d41, 0xcc17, 0x2d41, 0xcc17, 0x21, 0 + .dw 0x2d43, 0xcc17, 0x2d4f, 0xcc17, 0x21, 0 + .dw 0x2d51, 0xcc17, 0x2d51, 0xcc17, 0x21, 0 + .dw 0x2d53, 0xcc17, 0x2d7f, 0xcc17, 0x21, 0 + .dw 0x2d81, 0xcc17, 0x2d81, 0xcc17, 0x21, 0 + .dw 0x2d83, 0xcc17, 0x2d8f, 0xcc17, 0x21, 0 + .dw 0x2d91, 0xcc17, 0x2d91, 0xcc17, 0x21, 0 + .dw 0x2d93, 0xcc17, 0x2dbf, 0xcc17, 0x21, 0 + .dw 0x2dc1, 0xcc17, 0x2dc1, 0xcc17, 0x21, 0 + .dw 0x2dc3, 0xcc17, 0x2dcf, 0xcc17, 0x21, 0 + .dw 0x2dd1, 0xcc17, 0x2dd1, 0xcc17, 0x21, 0 + .dw 0x2dd3, 0xcc17, 0x2dff, 0xcc17, 0x21, 0 + .dw 0x2e01, 0xcc17, 0x2e01, 0xcc17, 0x21, 0 + .dw 0x2e03, 0xcc17, 0x2e0f, 0xcc17, 0x21, 0 + .dw 0x2e11, 0xcc17, 0x2e11, 0xcc17, 0x21, 0 + .dw 0x2e13, 0xcc17, 0x2e3f, 0xcc17, 0x21, 0 + .dw 0x2e41, 0xcc17, 0x2e41, 0xcc17, 0x21, 0 + .dw 0x2e43, 0xcc17, 0x2e4f, 0xcc17, 0x21, 0 + .dw 0x2e51, 0xcc17, 0x2e51, 0xcc17, 0x21, 0 + .dw 0x2e53, 0xcc17, 0x2e7f, 0xcc17, 0x21, 0 + .dw 0x2e81, 0xcc17, 0x2e81, 0xcc17, 0x21, 0 + .dw 0x2e83, 0xcc17, 0x2e8f, 0xcc17, 0x21, 0 + .dw 0x2e91, 0xcc17, 0x2e91, 0xcc17, 0x21, 0 + .dw 0x2e93, 0xcc17, 0x2ebf, 0xcc17, 0x21, 0 + .dw 0x2ec1, 0xcc17, 0x2ec1, 0xcc17, 0x21, 0 + .dw 0x2ec3, 0xcc17, 0x2ecf, 0xcc17, 0x21, 0 + .dw 0x2ed1, 0xcc17, 0x2ed1, 0xcc17, 0x21, 0 + .dw 0x2ed3, 0xcc17, 0x2eff, 0xcc17, 0x21, 0 + .dw 0x2f01, 0xcc17, 0x2f01, 0xcc17, 0x21, 0 + .dw 0x2f03, 0xcc17, 0x2f0f, 0xcc17, 0x21, 0 + .dw 0x2f11, 0xcc17, 0x2f11, 0xcc17, 0x21, 0 + .dw 0x2f13, 0xcc17, 0x2f3f, 0xcc17, 0x21, 0 + .dw 0x2f41, 0xcc17, 0x2f41, 0xcc17, 0x21, 0 + .dw 0x2f43, 0xcc17, 0x2f4f, 0xcc17, 0x21, 0 + .dw 0x2f51, 0xcc17, 0x2f51, 0xcc17, 0x21, 0 + .dw 0x2f53, 0xcc17, 0x2f7f, 0xcc17, 0x21, 0 + .dw 0x2f81, 0xcc17, 0x2f81, 0xcc17, 0x21, 0 + .dw 0x2f83, 0xcc17, 0x2f8f, 0xcc17, 0x21, 0 + .dw 0x2f91, 0xcc17, 0x2f91, 0xcc17, 0x21, 0 + .dw 0x2f93, 0xcc17, 0x2fbf, 0xcc17, 0x21, 0 + .dw 0x2fc1, 0xcc17, 0x2fc1, 0xcc17, 0x21, 0 + .dw 0x2fc3, 0xcc17, 0x2fcf, 0xcc17, 0x21, 0 + .dw 0x2fd1, 0xcc17, 0x2fd1, 0xcc17, 0x21, 0 + .dw 0x2fd3, 0xcc17, 0xffff, 0xcc17, 0x21, 0 + .dw 0x1000, 0xcc18, 0x3fff, 0xcc18, 0x21, 0 + .dw 0x4000, 0xcc18, 0x4000, 0xcc18, 0x22, 0 + .dw 0x4001, 0xcc18, 0x4001, 0xcc18, 0x21, 0 + .dw 0x4002, 0xcc18, 0x4002, 0xcc18, 0x22, 0 + .dw 0x4003, 0xcc18, 0x400f, 0xcc18, 0x21, 0 + .dw 0x4010, 0xcc18, 0x4010, 0xcc18, 0x22, 0 + .dw 0x4011, 0xcc18, 0x4011, 0xcc18, 0x21, 0 + .dw 0x4012, 0xcc18, 0x4012, 0xcc18, 0x22, 0 + .dw 0x4013, 0xcc18, 0x403f, 0xcc18, 0x21, 0 + .dw 0x4041, 0xcc18, 0x4041, 0xcc18, 0x21, 0 + .dw 0x4043, 0xcc18, 0x404f, 0xcc18, 0x21, 0 + .dw 0x4051, 0xcc18, 0x4051, 0xcc18, 0x21, 0 + .dw 0x4053, 0xcc18, 0x407f, 0xcc18, 0x21, 0 + .dw 0x4081, 0xcc18, 0x4081, 0xcc18, 0x21, 0 + .dw 0x4083, 0xcc18, 0x408f, 0xcc18, 0x21, 0 + .dw 0x4091, 0xcc18, 0x4091, 0xcc18, 0x21, 0 + .dw 0x4093, 0xcc18, 0x40bf, 0xcc18, 0x21, 0 + .dw 0x40c1, 0xcc18, 0x40c1, 0xcc18, 0x21, 0 + .dw 0x40c3, 0xcc18, 0x40cf, 0xcc18, 0x21, 0 + .dw 0x40d1, 0xcc18, 0x40d1, 0xcc18, 0x21, 0 + .dw 0x40d3, 0xcc18, 0x40ff, 0xcc18, 0x21, 0 + .dw 0x4101, 0xcc18, 0x4101, 0xcc18, 0x21, 0 + .dw 0x4103, 0xcc18, 0x410f, 0xcc18, 0x21, 0 + .dw 0x4111, 0xcc18, 0x4111, 0xcc18, 0x21, 0 + .dw 0x4113, 0xcc18, 0x413f, 0xcc18, 0x21, 0 + .dw 0x4141, 0xcc18, 0x4141, 0xcc18, 0x21, 0 + .dw 0x4143, 0xcc18, 0x414f, 0xcc18, 0x21, 0 + .dw 0x4151, 0xcc18, 0x4151, 0xcc18, 0x21, 0 + .dw 0x4153, 0xcc18, 0x417f, 0xcc18, 0x21, 0 + .dw 0x4181, 0xcc18, 0x4181, 0xcc18, 0x21, 0 + .dw 0x4183, 0xcc18, 0x418f, 0xcc18, 0x21, 0 + .dw 0x4191, 0xcc18, 0x4191, 0xcc18, 0x21, 0 + .dw 0x4193, 0xcc18, 0x41bf, 0xcc18, 0x21, 0 + .dw 0x41c1, 0xcc18, 0x41c1, 0xcc18, 0x21, 0 + .dw 0x41c3, 0xcc18, 0x41cf, 0xcc18, 0x21, 0 + .dw 0x41d1, 0xcc18, 0x41d1, 0xcc18, 0x21, 0 + .dw 0x41d3, 0xcc18, 0x41ff, 0xcc18, 0x21, 0 + .dw 0x4201, 0xcc18, 0x4201, 0xcc18, 0x21, 0 + .dw 0x4203, 0xcc18, 0x420f, 0xcc18, 0x21, 0 + .dw 0x4211, 0xcc18, 0x4211, 0xcc18, 0x21, 0 + .dw 0x4213, 0xcc18, 0x423f, 0xcc18, 0x21, 0 + .dw 0x4240, 0xcc18, 0x4240, 0xcc18, 0x22, 0 + .dw 0x4241, 0xcc18, 0x4241, 0xcc18, 0x21, 0 + .dw 0x4242, 0xcc18, 0x4242, 0xcc18, 0x22, 0 + .dw 0x4243, 0xcc18, 0x424f, 0xcc18, 0x21, 0 + .dw 0x4250, 0xcc18, 0x4250, 0xcc18, 0x22, 0 + .dw 0x4251, 0xcc18, 0x4251, 0xcc18, 0x21, 0 + .dw 0x4252, 0xcc18, 0x4252, 0xcc18, 0x22, 0 + .dw 0x4253, 0xcc18, 0x427f, 0xcc18, 0x21, 0 + .dw 0x4281, 0xcc18, 0x4281, 0xcc18, 0x21, 0 + .dw 0x4283, 0xcc18, 0x428f, 0xcc18, 0x21, 0 + .dw 0x4291, 0xcc18, 0x4291, 0xcc18, 0x21, 0 + .dw 0x4293, 0xcc18, 0x42bf, 0xcc18, 0x21, 0 + .dw 0x42c1, 0xcc18, 0x42c1, 0xcc18, 0x21, 0 + .dw 0x42c3, 0xcc18, 0x42cf, 0xcc18, 0x21, 0 + .dw 0x42d1, 0xcc18, 0x42d1, 0xcc18, 0x21, 0 + .dw 0x42d3, 0xcc18, 0x42ff, 0xcc18, 0x21, 0 + .dw 0x4301, 0xcc18, 0x4301, 0xcc18, 0x21, 0 + .dw 0x4303, 0xcc18, 0x430f, 0xcc18, 0x21, 0 + .dw 0x4311, 0xcc18, 0x4311, 0xcc18, 0x21, 0 + .dw 0x4313, 0xcc18, 0x433f, 0xcc18, 0x21, 0 + .dw 0x4341, 0xcc18, 0x4341, 0xcc18, 0x21, 0 + .dw 0x4343, 0xcc18, 0x434f, 0xcc18, 0x21, 0 + .dw 0x4351, 0xcc18, 0x4351, 0xcc18, 0x21, 0 + .dw 0x4353, 0xcc18, 0x437f, 0xcc18, 0x21, 0 + .dw 0x4381, 0xcc18, 0x4381, 0xcc18, 0x21, 0 + .dw 0x4383, 0xcc18, 0x438f, 0xcc18, 0x21, 0 + .dw 0x4391, 0xcc18, 0x4391, 0xcc18, 0x21, 0 + .dw 0x4393, 0xcc18, 0x43bf, 0xcc18, 0x21, 0 + .dw 0x43c1, 0xcc18, 0x43c1, 0xcc18, 0x21, 0 + .dw 0x43c3, 0xcc18, 0x43cf, 0xcc18, 0x21, 0 + .dw 0x43d1, 0xcc18, 0x43d1, 0xcc18, 0x21, 0 + .dw 0x43d3, 0xcc18, 0x43ff, 0xcc18, 0x21, 0 + .dw 0x4401, 0xcc18, 0x4401, 0xcc18, 0x21, 0 + .dw 0x4403, 0xcc18, 0x440f, 0xcc18, 0x21, 0 + .dw 0x4411, 0xcc18, 0x4411, 0xcc18, 0x21, 0 + .dw 0x4413, 0xcc18, 0x443f, 0xcc18, 0x21, 0 + .dw 0x4441, 0xcc18, 0x4441, 0xcc18, 0x21, 0 + .dw 0x4443, 0xcc18, 0x444f, 0xcc18, 0x21, 0 + .dw 0x4451, 0xcc18, 0x4451, 0xcc18, 0x21, 0 + .dw 0x4453, 0xcc18, 0x447f, 0xcc18, 0x21, 0 + .dw 0x4480, 0xcc18, 0x4480, 0xcc18, 0x22, 0 + .dw 0x4481, 0xcc18, 0x4481, 0xcc18, 0x21, 0 + .dw 0x4482, 0xcc18, 0x4482, 0xcc18, 0x22, 0 + .dw 0x4483, 0xcc18, 0x448f, 0xcc18, 0x21, 0 + .dw 0x4490, 0xcc18, 0x4490, 0xcc18, 0x22, 0 + .dw 0x4491, 0xcc18, 0x4491, 0xcc18, 0x21, 0 + .dw 0x4492, 0xcc18, 0x4492, 0xcc18, 0x22, 0 + .dw 0x4493, 0xcc18, 0x44bf, 0xcc18, 0x21, 0 + .dw 0x44c1, 0xcc18, 0x44c1, 0xcc18, 0x21, 0 + .dw 0x44c3, 0xcc18, 0x44cf, 0xcc18, 0x21, 0 + .dw 0x44d1, 0xcc18, 0x44d1, 0xcc18, 0x21, 0 + .dw 0x44d3, 0xcc18, 0x44ff, 0xcc18, 0x21, 0 + .dw 0x4501, 0xcc18, 0x4501, 0xcc18, 0x21, 0 + .dw 0x4503, 0xcc18, 0x450f, 0xcc18, 0x21, 0 + .dw 0x4511, 0xcc18, 0x4511, 0xcc18, 0x21, 0 + .dw 0x4513, 0xcc18, 0x453f, 0xcc18, 0x21, 0 + .dw 0x4541, 0xcc18, 0x4541, 0xcc18, 0x21, 0 + .dw 0x4543, 0xcc18, 0x454f, 0xcc18, 0x21, 0 + .dw 0x4551, 0xcc18, 0x4551, 0xcc18, 0x21, 0 + .dw 0x4553, 0xcc18, 0x457f, 0xcc18, 0x21, 0 + .dw 0x4581, 0xcc18, 0x4581, 0xcc18, 0x21, 0 + .dw 0x4583, 0xcc18, 0x458f, 0xcc18, 0x21, 0 + .dw 0x4591, 0xcc18, 0x4591, 0xcc18, 0x21, 0 + .dw 0x4593, 0xcc18, 0x45bf, 0xcc18, 0x21, 0 + .dw 0x45c1, 0xcc18, 0x45c1, 0xcc18, 0x21, 0 + .dw 0x45c3, 0xcc18, 0x45cf, 0xcc18, 0x21, 0 + .dw 0x45d1, 0xcc18, 0x45d1, 0xcc18, 0x21, 0 + .dw 0x45d3, 0xcc18, 0x45ff, 0xcc18, 0x21, 0 + .dw 0x4601, 0xcc18, 0x4601, 0xcc18, 0x21, 0 + .dw 0x4603, 0xcc18, 0x460f, 0xcc18, 0x21, 0 + .dw 0x4611, 0xcc18, 0x4611, 0xcc18, 0x21, 0 + .dw 0x4613, 0xcc18, 0x463f, 0xcc18, 0x21, 0 + .dw 0x4641, 0xcc18, 0x4641, 0xcc18, 0x21, 0 + .dw 0x4643, 0xcc18, 0x464f, 0xcc18, 0x21, 0 + .dw 0x4651, 0xcc18, 0x4651, 0xcc18, 0x21, 0 + .dw 0x4653, 0xcc18, 0x467f, 0xcc18, 0x21, 0 + .dw 0x4681, 0xcc18, 0x4681, 0xcc18, 0x21, 0 + .dw 0x4683, 0xcc18, 0x468f, 0xcc18, 0x21, 0 + .dw 0x4691, 0xcc18, 0x4691, 0xcc18, 0x21, 0 + .dw 0x4693, 0xcc18, 0x46bf, 0xcc18, 0x21, 0 + .dw 0x46c0, 0xcc18, 0x46c0, 0xcc18, 0x22, 0 + .dw 0x46c1, 0xcc18, 0x46c1, 0xcc18, 0x21, 0 + .dw 0x46c2, 0xcc18, 0x46c2, 0xcc18, 0x22, 0 + .dw 0x46c3, 0xcc18, 0x46cf, 0xcc18, 0x21, 0 + .dw 0x46d0, 0xcc18, 0x46d0, 0xcc18, 0x22, 0 + .dw 0x46d1, 0xcc18, 0x46d1, 0xcc18, 0x21, 0 + .dw 0x46d2, 0xcc18, 0x46d2, 0xcc18, 0x22, 0 + .dw 0x46d3, 0xcc18, 0x46ff, 0xcc18, 0x21, 0 + .dw 0x4701, 0xcc18, 0x4701, 0xcc18, 0x21, 0 + .dw 0x4703, 0xcc18, 0x470f, 0xcc18, 0x21, 0 + .dw 0x4711, 0xcc18, 0x4711, 0xcc18, 0x21, 0 + .dw 0x4713, 0xcc18, 0x473f, 0xcc18, 0x21, 0 + .dw 0x4741, 0xcc18, 0x4741, 0xcc18, 0x21, 0 + .dw 0x4743, 0xcc18, 0x474f, 0xcc18, 0x21, 0 + .dw 0x4751, 0xcc18, 0x4751, 0xcc18, 0x21, 0 + .dw 0x4753, 0xcc18, 0x477f, 0xcc18, 0x21, 0 + .dw 0x4781, 0xcc18, 0x4781, 0xcc18, 0x21, 0 + .dw 0x4783, 0xcc18, 0x478f, 0xcc18, 0x21, 0 + .dw 0x4791, 0xcc18, 0x4791, 0xcc18, 0x21, 0 + .dw 0x4793, 0xcc18, 0x47bf, 0xcc18, 0x21, 0 + .dw 0x47c1, 0xcc18, 0x47c1, 0xcc18, 0x21, 0 + .dw 0x47c3, 0xcc18, 0x47cf, 0xcc18, 0x21, 0 + .dw 0x47d1, 0xcc18, 0x47d1, 0xcc18, 0x21, 0 + .dw 0x47d3, 0xcc18, 0x47ff, 0xcc18, 0x21, 0 + .dw 0x4801, 0xcc18, 0x4801, 0xcc18, 0x21, 0 + .dw 0x4803, 0xcc18, 0x480f, 0xcc18, 0x21, 0 + .dw 0x4811, 0xcc18, 0x4811, 0xcc18, 0x21, 0 + .dw 0x4813, 0xcc18, 0x483f, 0xcc18, 0x21, 0 + .dw 0x4841, 0xcc18, 0x4841, 0xcc18, 0x21, 0 + .dw 0x4843, 0xcc18, 0x484f, 0xcc18, 0x21, 0 + .dw 0x4851, 0xcc18, 0x4851, 0xcc18, 0x21, 0 + .dw 0x4853, 0xcc18, 0x487f, 0xcc18, 0x21, 0 + .dw 0x4881, 0xcc18, 0x4881, 0xcc18, 0x21, 0 + .dw 0x4883, 0xcc18, 0x488f, 0xcc18, 0x21, 0 + .dw 0x4891, 0xcc18, 0x4891, 0xcc18, 0x21, 0 + .dw 0x4893, 0xcc18, 0x48bf, 0xcc18, 0x21, 0 + .dw 0x48c1, 0xcc18, 0x48c1, 0xcc18, 0x21, 0 + .dw 0x48c3, 0xcc18, 0x48cf, 0xcc18, 0x21, 0 + .dw 0x48d1, 0xcc18, 0x48d1, 0xcc18, 0x21, 0 + .dw 0x48d3, 0xcc18, 0x48ff, 0xcc18, 0x21, 0 + .dw 0x4900, 0xcc18, 0x4900, 0xcc18, 0x22, 0 + .dw 0x4901, 0xcc18, 0x4901, 0xcc18, 0x21, 0 + .dw 0x4902, 0xcc18, 0x4902, 0xcc18, 0x22, 0 + .dw 0x4903, 0xcc18, 0x490f, 0xcc18, 0x21, 0 + .dw 0x4910, 0xcc18, 0x4910, 0xcc18, 0x22, 0 + .dw 0x4911, 0xcc18, 0x4911, 0xcc18, 0x21, 0 + .dw 0x4912, 0xcc18, 0x4912, 0xcc18, 0x22, 0 + .dw 0x4913, 0xcc18, 0x493f, 0xcc18, 0x21, 0 + .dw 0x4941, 0xcc18, 0x4941, 0xcc18, 0x21, 0 + .dw 0x4943, 0xcc18, 0x494f, 0xcc18, 0x21, 0 + .dw 0x4951, 0xcc18, 0x4951, 0xcc18, 0x21, 0 + .dw 0x4953, 0xcc18, 0x497f, 0xcc18, 0x21, 0 + .dw 0x4981, 0xcc18, 0x4981, 0xcc18, 0x21, 0 + .dw 0x4983, 0xcc18, 0x498f, 0xcc18, 0x21, 0 + .dw 0x4991, 0xcc18, 0x4991, 0xcc18, 0x21, 0 + .dw 0x4993, 0xcc18, 0x49bf, 0xcc18, 0x21, 0 + .dw 0x49c1, 0xcc18, 0x49c1, 0xcc18, 0x21, 0 + .dw 0x49c3, 0xcc18, 0x49cf, 0xcc18, 0x21, 0 + .dw 0x49d1, 0xcc18, 0x49d1, 0xcc18, 0x21, 0 + .dw 0x49d3, 0xcc18, 0x49ff, 0xcc18, 0x21, 0 + .dw 0x4a01, 0xcc18, 0x4a01, 0xcc18, 0x21, 0 + .dw 0x4a03, 0xcc18, 0x4a0f, 0xcc18, 0x21, 0 + .dw 0x4a11, 0xcc18, 0x4a11, 0xcc18, 0x21, 0 + .dw 0x4a13, 0xcc18, 0x4a3f, 0xcc18, 0x21, 0 + .dw 0x4a41, 0xcc18, 0x4a41, 0xcc18, 0x21, 0 + .dw 0x4a43, 0xcc18, 0x4a4f, 0xcc18, 0x21, 0 + .dw 0x4a51, 0xcc18, 0x4a51, 0xcc18, 0x21, 0 + .dw 0x4a53, 0xcc18, 0x4a7f, 0xcc18, 0x21, 0 + .dw 0x4a81, 0xcc18, 0x4a81, 0xcc18, 0x21, 0 + .dw 0x4a83, 0xcc18, 0x4a8f, 0xcc18, 0x21, 0 + .dw 0x4a91, 0xcc18, 0x4a91, 0xcc18, 0x21, 0 + .dw 0x4a93, 0xcc18, 0x4abf, 0xcc18, 0x21, 0 + .dw 0x4ac1, 0xcc18, 0x4ac1, 0xcc18, 0x21, 0 + .dw 0x4ac3, 0xcc18, 0x4acf, 0xcc18, 0x21, 0 + .dw 0x4ad1, 0xcc18, 0x4ad1, 0xcc18, 0x21, 0 + .dw 0x4ad3, 0xcc18, 0x4aff, 0xcc18, 0x21, 0 + .dw 0x4b01, 0xcc18, 0x4b01, 0xcc18, 0x21, 0 + .dw 0x4b03, 0xcc18, 0x4b0f, 0xcc18, 0x21, 0 + .dw 0x4b11, 0xcc18, 0x4b11, 0xcc18, 0x21, 0 + .dw 0x4b13, 0xcc18, 0x4b3f, 0xcc18, 0x21, 0 + .dw 0x4b40, 0xcc18, 0x4b40, 0xcc18, 0x22, 0 + .dw 0x4b41, 0xcc18, 0x4b41, 0xcc18, 0x21, 0 + .dw 0x4b42, 0xcc18, 0x4b42, 0xcc18, 0x22, 0 + .dw 0x4b43, 0xcc18, 0x4b4f, 0xcc18, 0x21, 0 + .dw 0x4b50, 0xcc18, 0x4b50, 0xcc18, 0x22, 0 + .dw 0x4b51, 0xcc18, 0x4b51, 0xcc18, 0x21, 0 + .dw 0x4b52, 0xcc18, 0x4b52, 0xcc18, 0x22, 0 + .dw 0x4b53, 0xcc18, 0x4b7f, 0xcc18, 0x21, 0 + .dw 0x4b81, 0xcc18, 0x4b81, 0xcc18, 0x21, 0 + .dw 0x4b83, 0xcc18, 0x4b8f, 0xcc18, 0x21, 0 + .dw 0x4b91, 0xcc18, 0x4b91, 0xcc18, 0x21, 0 + .dw 0x4b93, 0xcc18, 0x4bbf, 0xcc18, 0x21, 0 + .dw 0x4bc1, 0xcc18, 0x4bc1, 0xcc18, 0x21, 0 + .dw 0x4bc3, 0xcc18, 0x4bcf, 0xcc18, 0x21, 0 + .dw 0x4bd1, 0xcc18, 0x4bd1, 0xcc18, 0x21, 0 + .dw 0x4bd3, 0xcc18, 0x4bff, 0xcc18, 0x21, 0 + .dw 0x4c01, 0xcc18, 0x4c01, 0xcc18, 0x21, 0 + .dw 0x4c03, 0xcc18, 0x4c0f, 0xcc18, 0x21, 0 + .dw 0x4c11, 0xcc18, 0x4c11, 0xcc18, 0x21, 0 + .dw 0x4c13, 0xcc18, 0x4c3f, 0xcc18, 0x21, 0 + .dw 0x4c41, 0xcc18, 0x4c41, 0xcc18, 0x21, 0 + .dw 0x4c43, 0xcc18, 0x4c4f, 0xcc18, 0x21, 0 + .dw 0x4c51, 0xcc18, 0x4c51, 0xcc18, 0x21, 0 + .dw 0x4c53, 0xcc18, 0x4c7f, 0xcc18, 0x21, 0 + .dw 0x4c81, 0xcc18, 0x4c81, 0xcc18, 0x21, 0 + .dw 0x4c83, 0xcc18, 0x4c8f, 0xcc18, 0x21, 0 + .dw 0x4c91, 0xcc18, 0x4c91, 0xcc18, 0x21, 0 + .dw 0x4c93, 0xcc18, 0x4cbf, 0xcc18, 0x21, 0 + .dw 0x4cc1, 0xcc18, 0x4cc1, 0xcc18, 0x21, 0 + .dw 0x4cc3, 0xcc18, 0x4ccf, 0xcc18, 0x21, 0 + .dw 0x4cd1, 0xcc18, 0x4cd1, 0xcc18, 0x21, 0 + .dw 0x4cd3, 0xcc18, 0x4cff, 0xcc18, 0x21, 0 + .dw 0x4d01, 0xcc18, 0x4d01, 0xcc18, 0x21, 0 + .dw 0x4d03, 0xcc18, 0x4d0f, 0xcc18, 0x21, 0 + .dw 0x4d11, 0xcc18, 0x4d11, 0xcc18, 0x21, 0 + .dw 0x4d13, 0xcc18, 0x4d3f, 0xcc18, 0x21, 0 + .dw 0x4d41, 0xcc18, 0x4d41, 0xcc18, 0x21, 0 + .dw 0x4d43, 0xcc18, 0x4d4f, 0xcc18, 0x21, 0 + .dw 0x4d51, 0xcc18, 0x4d51, 0xcc18, 0x21, 0 + .dw 0x4d53, 0xcc18, 0x4d7f, 0xcc18, 0x21, 0 + .dw 0x4d80, 0xcc18, 0x4d80, 0xcc18, 0x22, 0 + .dw 0x4d81, 0xcc18, 0x4d81, 0xcc18, 0x21, 0 + .dw 0x4d82, 0xcc18, 0x4d82, 0xcc18, 0x22, 0 + .dw 0x4d83, 0xcc18, 0x4d8f, 0xcc18, 0x21, 0 + .dw 0x4d90, 0xcc18, 0x4d90, 0xcc18, 0x22, 0 + .dw 0x4d91, 0xcc18, 0x4d91, 0xcc18, 0x21, 0 + .dw 0x4d92, 0xcc18, 0x4d92, 0xcc18, 0x22, 0 + .dw 0x4d93, 0xcc18, 0x4dbf, 0xcc18, 0x21, 0 + .dw 0x4dc1, 0xcc18, 0x4dc1, 0xcc18, 0x21, 0 + .dw 0x4dc3, 0xcc18, 0x4dcf, 0xcc18, 0x21, 0 + .dw 0x4dd1, 0xcc18, 0x4dd1, 0xcc18, 0x21, 0 + .dw 0x4dd3, 0xcc18, 0x4dff, 0xcc18, 0x21, 0 + .dw 0x4e01, 0xcc18, 0x4e01, 0xcc18, 0x21, 0 + .dw 0x4e03, 0xcc18, 0x4e0f, 0xcc18, 0x21, 0 + .dw 0x4e11, 0xcc18, 0x4e11, 0xcc18, 0x21, 0 + .dw 0x4e13, 0xcc18, 0x4e3f, 0xcc18, 0x21, 0 + .dw 0x4e41, 0xcc18, 0x4e41, 0xcc18, 0x21, 0 + .dw 0x4e43, 0xcc18, 0x4e4f, 0xcc18, 0x21, 0 + .dw 0x4e51, 0xcc18, 0x4e51, 0xcc18, 0x21, 0 + .dw 0x4e53, 0xcc18, 0x4e7f, 0xcc18, 0x21, 0 + .dw 0x4e81, 0xcc18, 0x4e81, 0xcc18, 0x21, 0 + .dw 0x4e83, 0xcc18, 0x4e8f, 0xcc18, 0x21, 0 + .dw 0x4e91, 0xcc18, 0x4e91, 0xcc18, 0x21, 0 + .dw 0x4e93, 0xcc18, 0x4ebf, 0xcc18, 0x21, 0 + .dw 0x4ec1, 0xcc18, 0x4ec1, 0xcc18, 0x21, 0 + .dw 0x4ec3, 0xcc18, 0x4ecf, 0xcc18, 0x21, 0 + .dw 0x4ed1, 0xcc18, 0x4ed1, 0xcc18, 0x21, 0 + .dw 0x4ed3, 0xcc18, 0x4eff, 0xcc18, 0x21, 0 + .dw 0x4f01, 0xcc18, 0x4f01, 0xcc18, 0x21, 0 + .dw 0x4f03, 0xcc18, 0x4f0f, 0xcc18, 0x21, 0 + .dw 0x4f11, 0xcc18, 0x4f11, 0xcc18, 0x21, 0 + .dw 0x4f13, 0xcc18, 0x4f3f, 0xcc18, 0x21, 0 + .dw 0x4f41, 0xcc18, 0x4f41, 0xcc18, 0x21, 0 + .dw 0x4f43, 0xcc18, 0x4f4f, 0xcc18, 0x21, 0 + .dw 0x4f51, 0xcc18, 0x4f51, 0xcc18, 0x21, 0 + .dw 0x4f53, 0xcc18, 0x4f7f, 0xcc18, 0x21, 0 + .dw 0x4f81, 0xcc18, 0x4f81, 0xcc18, 0x21, 0 + .dw 0x4f83, 0xcc18, 0x4f8f, 0xcc18, 0x21, 0 + .dw 0x4f91, 0xcc18, 0x4f91, 0xcc18, 0x21, 0 + .dw 0x4f93, 0xcc18, 0x4fbf, 0xcc18, 0x21, 0 + .dw 0x4fc0, 0xcc18, 0x4fc0, 0xcc18, 0x22, 0 + .dw 0x4fc1, 0xcc18, 0x4fc1, 0xcc18, 0x21, 0 + .dw 0x4fc2, 0xcc18, 0x4fc2, 0xcc18, 0x22, 0 + .dw 0x4fc3, 0xcc18, 0x4fcf, 0xcc18, 0x21, 0 + .dw 0x4fd0, 0xcc18, 0x4fd0, 0xcc18, 0x22, 0 + .dw 0x4fd1, 0xcc18, 0x4fd1, 0xcc18, 0x21, 0 + .dw 0x4fd2, 0xcc18, 0x4fd2, 0xcc18, 0x22, 0 + .dw 0x4fd3, 0xcc18, 0x5fff, 0xcc18, 0x21, 0 + .dw 0x6000, 0xcc18, 0x6000, 0xcc18, 0x22, 0 + .dw 0x6001, 0xcc18, 0x6001, 0xcc18, 0x21, 0 + .dw 0x6002, 0xcc18, 0x6002, 0xcc18, 0x22, 0 + .dw 0x6003, 0xcc18, 0x600f, 0xcc18, 0x21, 0 + .dw 0x6010, 0xcc18, 0x6010, 0xcc18, 0x22, 0 + .dw 0x6011, 0xcc18, 0x6011, 0xcc18, 0x21, 0 + .dw 0x6012, 0xcc18, 0x6012, 0xcc18, 0x22, 0 + .dw 0x6013, 0xcc18, 0x603f, 0xcc18, 0x21, 0 + .dw 0x6041, 0xcc18, 0x6041, 0xcc18, 0x21, 0 + .dw 0x6043, 0xcc18, 0x604f, 0xcc18, 0x21, 0 + .dw 0x6051, 0xcc18, 0x6051, 0xcc18, 0x21, 0 + .dw 0x6053, 0xcc18, 0x607f, 0xcc18, 0x21, 0 + .dw 0x6081, 0xcc18, 0x6081, 0xcc18, 0x21, 0 + .dw 0x6083, 0xcc18, 0x608f, 0xcc18, 0x21, 0 + .dw 0x6091, 0xcc18, 0x6091, 0xcc18, 0x21, 0 + .dw 0x6093, 0xcc18, 0x60bf, 0xcc18, 0x21, 0 + .dw 0x60c1, 0xcc18, 0x60c1, 0xcc18, 0x21, 0 + .dw 0x60c3, 0xcc18, 0x60cf, 0xcc18, 0x21, 0 + .dw 0x60d1, 0xcc18, 0x60d1, 0xcc18, 0x21, 0 + .dw 0x60d3, 0xcc18, 0x60ff, 0xcc18, 0x21, 0 + .dw 0x6101, 0xcc18, 0x6101, 0xcc18, 0x21, 0 + .dw 0x6103, 0xcc18, 0x610f, 0xcc18, 0x21, 0 + .dw 0x6111, 0xcc18, 0x6111, 0xcc18, 0x21, 0 + .dw 0x6113, 0xcc18, 0x613f, 0xcc18, 0x21, 0 + .dw 0x6141, 0xcc18, 0x6141, 0xcc18, 0x21, 0 + .dw 0x6143, 0xcc18, 0x614f, 0xcc18, 0x21, 0 + .dw 0x6151, 0xcc18, 0x6151, 0xcc18, 0x21, 0 + .dw 0x6153, 0xcc18, 0x617f, 0xcc18, 0x21, 0 + .dw 0x6181, 0xcc18, 0x6181, 0xcc18, 0x21, 0 + .dw 0x6183, 0xcc18, 0x618f, 0xcc18, 0x21, 0 + .dw 0x6191, 0xcc18, 0x6191, 0xcc18, 0x21, 0 + .dw 0x6193, 0xcc18, 0x61bf, 0xcc18, 0x21, 0 + .dw 0x61c1, 0xcc18, 0x61c1, 0xcc18, 0x21, 0 + .dw 0x61c3, 0xcc18, 0x61cf, 0xcc18, 0x21, 0 + .dw 0x61d1, 0xcc18, 0x61d1, 0xcc18, 0x21, 0 + .dw 0x61d3, 0xcc18, 0x61ff, 0xcc18, 0x21, 0 + .dw 0x6201, 0xcc18, 0x6201, 0xcc18, 0x21, 0 + .dw 0x6203, 0xcc18, 0x620f, 0xcc18, 0x21, 0 + .dw 0x6211, 0xcc18, 0x6211, 0xcc18, 0x21, 0 + .dw 0x6213, 0xcc18, 0x623f, 0xcc18, 0x21, 0 + .dw 0x6240, 0xcc18, 0x6240, 0xcc18, 0x22, 0 + .dw 0x6241, 0xcc18, 0x6241, 0xcc18, 0x21, 0 + .dw 0x6242, 0xcc18, 0x6242, 0xcc18, 0x22, 0 + .dw 0x6243, 0xcc18, 0x624f, 0xcc18, 0x21, 0 + .dw 0x6250, 0xcc18, 0x6250, 0xcc18, 0x22, 0 + .dw 0x6251, 0xcc18, 0x6251, 0xcc18, 0x21, 0 + .dw 0x6252, 0xcc18, 0x6252, 0xcc18, 0x22, 0 + .dw 0x6253, 0xcc18, 0x627f, 0xcc18, 0x21, 0 + .dw 0x6281, 0xcc18, 0x6281, 0xcc18, 0x21, 0 + .dw 0x6283, 0xcc18, 0x628f, 0xcc18, 0x21, 0 + .dw 0x6291, 0xcc18, 0x6291, 0xcc18, 0x21, 0 + .dw 0x6293, 0xcc18, 0x62bf, 0xcc18, 0x21, 0 + .dw 0x62c1, 0xcc18, 0x62c1, 0xcc18, 0x21, 0 + .dw 0x62c3, 0xcc18, 0x62cf, 0xcc18, 0x21, 0 + .dw 0x62d1, 0xcc18, 0x62d1, 0xcc18, 0x21, 0 + .dw 0x62d3, 0xcc18, 0x62ff, 0xcc18, 0x21, 0 + .dw 0x6301, 0xcc18, 0x6301, 0xcc18, 0x21, 0 + .dw 0x6303, 0xcc18, 0x630f, 0xcc18, 0x21, 0 + .dw 0x6311, 0xcc18, 0x6311, 0xcc18, 0x21, 0 + .dw 0x6313, 0xcc18, 0x633f, 0xcc18, 0x21, 0 + .dw 0x6341, 0xcc18, 0x6341, 0xcc18, 0x21, 0 + .dw 0x6343, 0xcc18, 0x634f, 0xcc18, 0x21, 0 + .dw 0x6351, 0xcc18, 0x6351, 0xcc18, 0x21, 0 + .dw 0x6353, 0xcc18, 0x637f, 0xcc18, 0x21, 0 + .dw 0x6381, 0xcc18, 0x6381, 0xcc18, 0x21, 0 + .dw 0x6383, 0xcc18, 0x638f, 0xcc18, 0x21, 0 + .dw 0x6391, 0xcc18, 0x6391, 0xcc18, 0x21, 0 + .dw 0x6393, 0xcc18, 0x63bf, 0xcc18, 0x21, 0 + .dw 0x63c1, 0xcc18, 0x63c1, 0xcc18, 0x21, 0 + .dw 0x63c3, 0xcc18, 0x63cf, 0xcc18, 0x21, 0 + .dw 0x63d1, 0xcc18, 0x63d1, 0xcc18, 0x21, 0 + .dw 0x63d3, 0xcc18, 0x63ff, 0xcc18, 0x21, 0 + .dw 0x6401, 0xcc18, 0x6401, 0xcc18, 0x21, 0 + .dw 0x6403, 0xcc18, 0x640f, 0xcc18, 0x21, 0 + .dw 0x6411, 0xcc18, 0x6411, 0xcc18, 0x21, 0 + .dw 0x6413, 0xcc18, 0x643f, 0xcc18, 0x21, 0 + .dw 0x6441, 0xcc18, 0x6441, 0xcc18, 0x21, 0 + .dw 0x6443, 0xcc18, 0x644f, 0xcc18, 0x21, 0 + .dw 0x6451, 0xcc18, 0x6451, 0xcc18, 0x21, 0 + .dw 0x6453, 0xcc18, 0x647f, 0xcc18, 0x21, 0 + .dw 0x6480, 0xcc18, 0x6480, 0xcc18, 0x22, 0 + .dw 0x6481, 0xcc18, 0x6481, 0xcc18, 0x21, 0 + .dw 0x6482, 0xcc18, 0x6482, 0xcc18, 0x22, 0 + .dw 0x6483, 0xcc18, 0x648f, 0xcc18, 0x21, 0 + .dw 0x6490, 0xcc18, 0x6490, 0xcc18, 0x22, 0 + .dw 0x6491, 0xcc18, 0x6491, 0xcc18, 0x21, 0 + .dw 0x6492, 0xcc18, 0x6492, 0xcc18, 0x22, 0 + .dw 0x6493, 0xcc18, 0x64bf, 0xcc18, 0x21, 0 + .dw 0x64c1, 0xcc18, 0x64c1, 0xcc18, 0x21, 0 + .dw 0x64c3, 0xcc18, 0x64cf, 0xcc18, 0x21, 0 + .dw 0x64d1, 0xcc18, 0x64d1, 0xcc18, 0x21, 0 + .dw 0x64d3, 0xcc18, 0x64ff, 0xcc18, 0x21, 0 + .dw 0x6501, 0xcc18, 0x6501, 0xcc18, 0x21, 0 + .dw 0x6503, 0xcc18, 0x650f, 0xcc18, 0x21, 0 + .dw 0x6511, 0xcc18, 0x6511, 0xcc18, 0x21, 0 + .dw 0x6513, 0xcc18, 0x653f, 0xcc18, 0x21, 0 + .dw 0x6541, 0xcc18, 0x6541, 0xcc18, 0x21, 0 + .dw 0x6543, 0xcc18, 0x654f, 0xcc18, 0x21, 0 + .dw 0x6551, 0xcc18, 0x6551, 0xcc18, 0x21, 0 + .dw 0x6553, 0xcc18, 0x657f, 0xcc18, 0x21, 0 + .dw 0x6581, 0xcc18, 0x6581, 0xcc18, 0x21, 0 + .dw 0x6583, 0xcc18, 0x658f, 0xcc18, 0x21, 0 + .dw 0x6591, 0xcc18, 0x6591, 0xcc18, 0x21, 0 + .dw 0x6593, 0xcc18, 0x65bf, 0xcc18, 0x21, 0 + .dw 0x65c1, 0xcc18, 0x65c1, 0xcc18, 0x21, 0 + .dw 0x65c3, 0xcc18, 0x65cf, 0xcc18, 0x21, 0 + .dw 0x65d1, 0xcc18, 0x65d1, 0xcc18, 0x21, 0 + .dw 0x65d3, 0xcc18, 0x65ff, 0xcc18, 0x21, 0 + .dw 0x6601, 0xcc18, 0x6601, 0xcc18, 0x21, 0 + .dw 0x6603, 0xcc18, 0x660f, 0xcc18, 0x21, 0 + .dw 0x6611, 0xcc18, 0x6611, 0xcc18, 0x21, 0 + .dw 0x6613, 0xcc18, 0x663f, 0xcc18, 0x21, 0 + .dw 0x6641, 0xcc18, 0x6641, 0xcc18, 0x21, 0 + .dw 0x6643, 0xcc18, 0x664f, 0xcc18, 0x21, 0 + .dw 0x6651, 0xcc18, 0x6651, 0xcc18, 0x21, 0 + .dw 0x6653, 0xcc18, 0x667f, 0xcc18, 0x21, 0 + .dw 0x6681, 0xcc18, 0x6681, 0xcc18, 0x21, 0 + .dw 0x6683, 0xcc18, 0x668f, 0xcc18, 0x21, 0 + .dw 0x6691, 0xcc18, 0x6691, 0xcc18, 0x21, 0 + .dw 0x6693, 0xcc18, 0x66bf, 0xcc18, 0x21, 0 + .dw 0x66c0, 0xcc18, 0x66c0, 0xcc18, 0x22, 0 + .dw 0x66c1, 0xcc18, 0x66c1, 0xcc18, 0x21, 0 + .dw 0x66c2, 0xcc18, 0x66c2, 0xcc18, 0x22, 0 + .dw 0x66c3, 0xcc18, 0x66cf, 0xcc18, 0x21, 0 + .dw 0x66d0, 0xcc18, 0x66d0, 0xcc18, 0x22, 0 + .dw 0x66d1, 0xcc18, 0x66d1, 0xcc18, 0x21, 0 + .dw 0x66d2, 0xcc18, 0x66d2, 0xcc18, 0x22, 0 + .dw 0x66d3, 0xcc18, 0x66ff, 0xcc18, 0x21, 0 + .dw 0x6701, 0xcc18, 0x6701, 0xcc18, 0x21, 0 + .dw 0x6703, 0xcc18, 0x670f, 0xcc18, 0x21, 0 + .dw 0x6711, 0xcc18, 0x6711, 0xcc18, 0x21, 0 + .dw 0x6713, 0xcc18, 0x673f, 0xcc18, 0x21, 0 + .dw 0x6741, 0xcc18, 0x6741, 0xcc18, 0x21, 0 + .dw 0x6743, 0xcc18, 0x674f, 0xcc18, 0x21, 0 + .dw 0x6751, 0xcc18, 0x6751, 0xcc18, 0x21, 0 + .dw 0x6753, 0xcc18, 0x677f, 0xcc18, 0x21, 0 + .dw 0x6781, 0xcc18, 0x6781, 0xcc18, 0x21, 0 + .dw 0x6783, 0xcc18, 0x678f, 0xcc18, 0x21, 0 + .dw 0x6791, 0xcc18, 0x6791, 0xcc18, 0x21, 0 + .dw 0x6793, 0xcc18, 0x67bf, 0xcc18, 0x21, 0 + .dw 0x67c1, 0xcc18, 0x67c1, 0xcc18, 0x21, 0 + .dw 0x67c3, 0xcc18, 0x67cf, 0xcc18, 0x21, 0 + .dw 0x67d1, 0xcc18, 0x67d1, 0xcc18, 0x21, 0 + .dw 0x67d3, 0xcc18, 0x67ff, 0xcc18, 0x21, 0 + .dw 0x6801, 0xcc18, 0x6801, 0xcc18, 0x21, 0 + .dw 0x6803, 0xcc18, 0x680f, 0xcc18, 0x21, 0 + .dw 0x6811, 0xcc18, 0x6811, 0xcc18, 0x21, 0 + .dw 0x6813, 0xcc18, 0x683f, 0xcc18, 0x21, 0 + .dw 0x6841, 0xcc18, 0x6841, 0xcc18, 0x21, 0 + .dw 0x6843, 0xcc18, 0x684f, 0xcc18, 0x21, 0 + .dw 0x6851, 0xcc18, 0x6851, 0xcc18, 0x21, 0 + .dw 0x6853, 0xcc18, 0x687f, 0xcc18, 0x21, 0 + .dw 0x6881, 0xcc18, 0x6881, 0xcc18, 0x21, 0 + .dw 0x6883, 0xcc18, 0x688f, 0xcc18, 0x21, 0 + .dw 0x6891, 0xcc18, 0x6891, 0xcc18, 0x21, 0 + .dw 0x6893, 0xcc18, 0x68bf, 0xcc18, 0x21, 0 + .dw 0x68c1, 0xcc18, 0x68c1, 0xcc18, 0x21, 0 + .dw 0x68c3, 0xcc18, 0x68cf, 0xcc18, 0x21, 0 + .dw 0x68d1, 0xcc18, 0x68d1, 0xcc18, 0x21, 0 + .dw 0x68d3, 0xcc18, 0x68ff, 0xcc18, 0x21, 0 + .dw 0x6900, 0xcc18, 0x6900, 0xcc18, 0x22, 0 + .dw 0x6901, 0xcc18, 0x6901, 0xcc18, 0x21, 0 + .dw 0x6902, 0xcc18, 0x6902, 0xcc18, 0x22, 0 + .dw 0x6903, 0xcc18, 0x690f, 0xcc18, 0x21, 0 + .dw 0x6910, 0xcc18, 0x6910, 0xcc18, 0x22, 0 + .dw 0x6911, 0xcc18, 0x6911, 0xcc18, 0x21, 0 + .dw 0x6912, 0xcc18, 0x6912, 0xcc18, 0x22, 0 + .dw 0x6913, 0xcc18, 0x693f, 0xcc18, 0x21, 0 + .dw 0x6941, 0xcc18, 0x6941, 0xcc18, 0x21, 0 + .dw 0x6943, 0xcc18, 0x694f, 0xcc18, 0x21, 0 + .dw 0x6951, 0xcc18, 0x6951, 0xcc18, 0x21, 0 + .dw 0x6953, 0xcc18, 0x697f, 0xcc18, 0x21, 0 + .dw 0x6981, 0xcc18, 0x6981, 0xcc18, 0x21, 0 + .dw 0x6983, 0xcc18, 0x698f, 0xcc18, 0x21, 0 + .dw 0x6991, 0xcc18, 0x6991, 0xcc18, 0x21, 0 + .dw 0x6993, 0xcc18, 0x69bf, 0xcc18, 0x21, 0 + .dw 0x69c1, 0xcc18, 0x69c1, 0xcc18, 0x21, 0 + .dw 0x69c3, 0xcc18, 0x69cf, 0xcc18, 0x21, 0 + .dw 0x69d1, 0xcc18, 0x69d1, 0xcc18, 0x21, 0 + .dw 0x69d3, 0xcc18, 0x69ff, 0xcc18, 0x21, 0 + .dw 0x6a01, 0xcc18, 0x6a01, 0xcc18, 0x21, 0 + .dw 0x6a03, 0xcc18, 0x6a0f, 0xcc18, 0x21, 0 + .dw 0x6a11, 0xcc18, 0x6a11, 0xcc18, 0x21, 0 + .dw 0x6a13, 0xcc18, 0x6a3f, 0xcc18, 0x21, 0 + .dw 0x6a41, 0xcc18, 0x6a41, 0xcc18, 0x21, 0 + .dw 0x6a43, 0xcc18, 0x6a4f, 0xcc18, 0x21, 0 + .dw 0x6a51, 0xcc18, 0x6a51, 0xcc18, 0x21, 0 + .dw 0x6a53, 0xcc18, 0x6a7f, 0xcc18, 0x21, 0 + .dw 0x6a81, 0xcc18, 0x6a81, 0xcc18, 0x21, 0 + .dw 0x6a83, 0xcc18, 0x6a8f, 0xcc18, 0x21, 0 + .dw 0x6a91, 0xcc18, 0x6a91, 0xcc18, 0x21, 0 + .dw 0x6a93, 0xcc18, 0x6abf, 0xcc18, 0x21, 0 + .dw 0x6ac1, 0xcc18, 0x6ac1, 0xcc18, 0x21, 0 + .dw 0x6ac3, 0xcc18, 0x6acf, 0xcc18, 0x21, 0 + .dw 0x6ad1, 0xcc18, 0x6ad1, 0xcc18, 0x21, 0 + .dw 0x6ad3, 0xcc18, 0x6aff, 0xcc18, 0x21, 0 + .dw 0x6b01, 0xcc18, 0x6b01, 0xcc18, 0x21, 0 + .dw 0x6b03, 0xcc18, 0x6b0f, 0xcc18, 0x21, 0 + .dw 0x6b11, 0xcc18, 0x6b11, 0xcc18, 0x21, 0 + .dw 0x6b13, 0xcc18, 0x6b3f, 0xcc18, 0x21, 0 + .dw 0x6b40, 0xcc18, 0x6b40, 0xcc18, 0x22, 0 + .dw 0x6b41, 0xcc18, 0x6b41, 0xcc18, 0x21, 0 + .dw 0x6b42, 0xcc18, 0x6b42, 0xcc18, 0x22, 0 + .dw 0x6b43, 0xcc18, 0x6b4f, 0xcc18, 0x21, 0 + .dw 0x6b50, 0xcc18, 0x6b50, 0xcc18, 0x22, 0 + .dw 0x6b51, 0xcc18, 0x6b51, 0xcc18, 0x21, 0 + .dw 0x6b52, 0xcc18, 0x6b52, 0xcc18, 0x22, 0 + .dw 0x6b53, 0xcc18, 0x6b7f, 0xcc18, 0x21, 0 + .dw 0x6b81, 0xcc18, 0x6b81, 0xcc18, 0x21, 0 + .dw 0x6b83, 0xcc18, 0x6b8f, 0xcc18, 0x21, 0 + .dw 0x6b91, 0xcc18, 0x6b91, 0xcc18, 0x21, 0 + .dw 0x6b93, 0xcc18, 0x6bbf, 0xcc18, 0x21, 0 + .dw 0x6bc1, 0xcc18, 0x6bc1, 0xcc18, 0x21, 0 + .dw 0x6bc3, 0xcc18, 0x6bcf, 0xcc18, 0x21, 0 + .dw 0x6bd1, 0xcc18, 0x6bd1, 0xcc18, 0x21, 0 + .dw 0x6bd3, 0xcc18, 0x6bff, 0xcc18, 0x21, 0 + .dw 0x6c01, 0xcc18, 0x6c01, 0xcc18, 0x21, 0 + .dw 0x6c03, 0xcc18, 0x6c0f, 0xcc18, 0x21, 0 + .dw 0x6c11, 0xcc18, 0x6c11, 0xcc18, 0x21, 0 + .dw 0x6c13, 0xcc18, 0x6c3f, 0xcc18, 0x21, 0 + .dw 0x6c41, 0xcc18, 0x6c41, 0xcc18, 0x21, 0 + .dw 0x6c43, 0xcc18, 0x6c4f, 0xcc18, 0x21, 0 + .dw 0x6c51, 0xcc18, 0x6c51, 0xcc18, 0x21, 0 + .dw 0x6c53, 0xcc18, 0x6c7f, 0xcc18, 0x21, 0 + .dw 0x6c81, 0xcc18, 0x6c81, 0xcc18, 0x21, 0 + .dw 0x6c83, 0xcc18, 0x6c8f, 0xcc18, 0x21, 0 + .dw 0x6c91, 0xcc18, 0x6c91, 0xcc18, 0x21, 0 + .dw 0x6c93, 0xcc18, 0x6cbf, 0xcc18, 0x21, 0 + .dw 0x6cc1, 0xcc18, 0x6cc1, 0xcc18, 0x21, 0 + .dw 0x6cc3, 0xcc18, 0x6ccf, 0xcc18, 0x21, 0 + .dw 0x6cd1, 0xcc18, 0x6cd1, 0xcc18, 0x21, 0 + .dw 0x6cd3, 0xcc18, 0x6cff, 0xcc18, 0x21, 0 + .dw 0x6d01, 0xcc18, 0x6d01, 0xcc18, 0x21, 0 + .dw 0x6d03, 0xcc18, 0x6d0f, 0xcc18, 0x21, 0 + .dw 0x6d11, 0xcc18, 0x6d11, 0xcc18, 0x21, 0 + .dw 0x6d13, 0xcc18, 0x6d3f, 0xcc18, 0x21, 0 + .dw 0x6d41, 0xcc18, 0x6d41, 0xcc18, 0x21, 0 + .dw 0x6d43, 0xcc18, 0x6d4f, 0xcc18, 0x21, 0 + .dw 0x6d51, 0xcc18, 0x6d51, 0xcc18, 0x21, 0 + .dw 0x6d53, 0xcc18, 0x6d7f, 0xcc18, 0x21, 0 + .dw 0x6d80, 0xcc18, 0x6d80, 0xcc18, 0x22, 0 + .dw 0x6d81, 0xcc18, 0x6d81, 0xcc18, 0x21, 0 + .dw 0x6d82, 0xcc18, 0x6d82, 0xcc18, 0x22, 0 + .dw 0x6d83, 0xcc18, 0x6d8f, 0xcc18, 0x21, 0 + .dw 0x6d90, 0xcc18, 0x6d90, 0xcc18, 0x22, 0 + .dw 0x6d91, 0xcc18, 0x6d91, 0xcc18, 0x21, 0 + .dw 0x6d92, 0xcc18, 0x6d92, 0xcc18, 0x22, 0 + .dw 0x6d93, 0xcc18, 0x6dbf, 0xcc18, 0x21, 0 + .dw 0x6dc1, 0xcc18, 0x6dc1, 0xcc18, 0x21, 0 + .dw 0x6dc3, 0xcc18, 0x6dcf, 0xcc18, 0x21, 0 + .dw 0x6dd1, 0xcc18, 0x6dd1, 0xcc18, 0x21, 0 + .dw 0x6dd3, 0xcc18, 0x6dff, 0xcc18, 0x21, 0 + .dw 0x6e01, 0xcc18, 0x6e01, 0xcc18, 0x21, 0 + .dw 0x6e03, 0xcc18, 0x6e0f, 0xcc18, 0x21, 0 + .dw 0x6e11, 0xcc18, 0x6e11, 0xcc18, 0x21, 0 + .dw 0x6e13, 0xcc18, 0x6e3f, 0xcc18, 0x21, 0 + .dw 0x6e41, 0xcc18, 0x6e41, 0xcc18, 0x21, 0 + .dw 0x6e43, 0xcc18, 0x6e4f, 0xcc18, 0x21, 0 + .dw 0x6e51, 0xcc18, 0x6e51, 0xcc18, 0x21, 0 + .dw 0x6e53, 0xcc18, 0x6e7f, 0xcc18, 0x21, 0 + .dw 0x6e81, 0xcc18, 0x6e81, 0xcc18, 0x21, 0 + .dw 0x6e83, 0xcc18, 0x6e8f, 0xcc18, 0x21, 0 + .dw 0x6e91, 0xcc18, 0x6e91, 0xcc18, 0x21, 0 + .dw 0x6e93, 0xcc18, 0x6ebf, 0xcc18, 0x21, 0 + .dw 0x6ec1, 0xcc18, 0x6ec1, 0xcc18, 0x21, 0 + .dw 0x6ec3, 0xcc18, 0x6ecf, 0xcc18, 0x21, 0 + .dw 0x6ed1, 0xcc18, 0x6ed1, 0xcc18, 0x21, 0 + .dw 0x6ed3, 0xcc18, 0x6eff, 0xcc18, 0x21, 0 + .dw 0x6f01, 0xcc18, 0x6f01, 0xcc18, 0x21, 0 + .dw 0x6f03, 0xcc18, 0x6f0f, 0xcc18, 0x21, 0 + .dw 0x6f11, 0xcc18, 0x6f11, 0xcc18, 0x21, 0 + .dw 0x6f13, 0xcc18, 0x6f3f, 0xcc18, 0x21, 0 + .dw 0x6f41, 0xcc18, 0x6f41, 0xcc18, 0x21, 0 + .dw 0x6f43, 0xcc18, 0x6f4f, 0xcc18, 0x21, 0 + .dw 0x6f51, 0xcc18, 0x6f51, 0xcc18, 0x21, 0 + .dw 0x6f53, 0xcc18, 0x6f7f, 0xcc18, 0x21, 0 + .dw 0x6f81, 0xcc18, 0x6f81, 0xcc18, 0x21, 0 + .dw 0x6f83, 0xcc18, 0x6f8f, 0xcc18, 0x21, 0 + .dw 0x6f91, 0xcc18, 0x6f91, 0xcc18, 0x21, 0 + .dw 0x6f93, 0xcc18, 0x6fbf, 0xcc18, 0x21, 0 + .dw 0x6fc0, 0xcc18, 0x6fc0, 0xcc18, 0x22, 0 + .dw 0x6fc1, 0xcc18, 0x6fc1, 0xcc18, 0x21, 0 + .dw 0x6fc2, 0xcc18, 0x6fc2, 0xcc18, 0x22, 0 + .dw 0x6fc3, 0xcc18, 0x6fcf, 0xcc18, 0x21, 0 + .dw 0x6fd0, 0xcc18, 0x6fd0, 0xcc18, 0x22, 0 + .dw 0x6fd1, 0xcc18, 0x6fd1, 0xcc18, 0x21, 0 + .dw 0x6fd2, 0xcc18, 0x6fd2, 0xcc18, 0x22, 0 + .dw 0x6fd3, 0xcc18, 0xffff, 0xcc20, 0x21, 0 + .dw 0x0000, 0xcc21, 0x003f, 0xcc21, 0x22, 0 + .dw 0x0240, 0xcc21, 0x027f, 0xcc21, 0x22, 0 + .dw 0x0480, 0xcc21, 0x04bf, 0xcc21, 0x22, 0 + .dw 0x06c0, 0xcc21, 0x06ff, 0xcc21, 0x22, 0 + .dw 0x0900, 0xcc21, 0x093f, 0xcc21, 0x22, 0 + .dw 0x0b40, 0xcc21, 0x0b7f, 0xcc21, 0x22, 0 + .dw 0x0d80, 0xcc21, 0x0dbf, 0xcc21, 0x22, 0 + .dw 0x0fc0, 0xcc21, 0x103f, 0xcc21, 0x22, 0 + .dw 0x1240, 0xcc21, 0x127f, 0xcc21, 0x22, 0 + .dw 0x1480, 0xcc21, 0x14bf, 0xcc21, 0x22, 0 + .dw 0x16c0, 0xcc21, 0x16ff, 0xcc21, 0x22, 0 + .dw 0x1900, 0xcc21, 0x193f, 0xcc21, 0x22, 0 + .dw 0x1b40, 0xcc21, 0x1b7f, 0xcc21, 0x22, 0 + .dw 0x1d80, 0xcc21, 0x1dbf, 0xcc21, 0x22, 0 + .dw 0x1fc0, 0xcc21, 0x203f, 0xcc21, 0x22, 0 + .dw 0x2240, 0xcc21, 0x227f, 0xcc21, 0x22, 0 + .dw 0x2480, 0xcc21, 0x24bf, 0xcc21, 0x22, 0 + .dw 0x26c0, 0xcc21, 0x26ff, 0xcc21, 0x22, 0 + .dw 0x2900, 0xcc21, 0x293f, 0xcc21, 0x22, 0 + .dw 0x2b40, 0xcc21, 0x2b7f, 0xcc21, 0x22, 0 + .dw 0x2d80, 0xcc21, 0x2dbf, 0xcc21, 0x22, 0 + .dw 0x2fc0, 0xcc21, 0x303f, 0xcc21, 0x22, 0 + .dw 0x3240, 0xcc21, 0x327f, 0xcc21, 0x22, 0 + .dw 0x3480, 0xcc21, 0x34bf, 0xcc21, 0x22, 0 + .dw 0x36c0, 0xcc21, 0x36ff, 0xcc21, 0x22, 0 + .dw 0x3900, 0xcc21, 0x393f, 0xcc21, 0x22, 0 + .dw 0x3b40, 0xcc21, 0x3b7f, 0xcc21, 0x22, 0 + .dw 0x3d80, 0xcc21, 0x3dbf, 0xcc21, 0x22, 0 + .dw 0x3fc0, 0xcc21, 0x3fff, 0xcc21, 0x22, 0 + .dw 0x4000, 0xcc21, 0x7fff, 0xcc21, 0x21, 0 + .dw 0x8000, 0xcc21, 0x803f, 0xcc21, 0x22, 0 + .dw 0x8240, 0xcc21, 0x827f, 0xcc21, 0x22, 0 + .dw 0x8480, 0xcc21, 0x84bf, 0xcc21, 0x22, 0 + .dw 0x86c0, 0xcc21, 0x86ff, 0xcc21, 0x22, 0 + .dw 0x8900, 0xcc21, 0x893f, 0xcc21, 0x22, 0 + .dw 0x8b40, 0xcc21, 0x8b7f, 0xcc21, 0x22, 0 + .dw 0x8d80, 0xcc21, 0x8dbf, 0xcc21, 0x22, 0 + .dw 0x8fc0, 0xcc21, 0x903f, 0xcc21, 0x22, 0 + .dw 0x9240, 0xcc21, 0x927f, 0xcc21, 0x22, 0 + .dw 0x9480, 0xcc21, 0x94bf, 0xcc21, 0x22, 0 + .dw 0x96c0, 0xcc21, 0x96ff, 0xcc21, 0x22, 0 + .dw 0x9900, 0xcc21, 0x993f, 0xcc21, 0x22, 0 + .dw 0x9b40, 0xcc21, 0x9b7f, 0xcc21, 0x22, 0 + .dw 0x9d80, 0xcc21, 0x9dbf, 0xcc21, 0x22, 0 + .dw 0x9fc0, 0xcc21, 0xa03f, 0xcc21, 0x22, 0 + .dw 0xa240, 0xcc21, 0xa27f, 0xcc21, 0x22, 0 + .dw 0xa480, 0xcc21, 0xa4bf, 0xcc21, 0x22, 0 + .dw 0xa6c0, 0xcc21, 0xa6ff, 0xcc21, 0x22, 0 + .dw 0xa900, 0xcc21, 0xa93f, 0xcc21, 0x22, 0 + .dw 0xab40, 0xcc21, 0xab7f, 0xcc21, 0x22, 0 + .dw 0xad80, 0xcc21, 0xadbf, 0xcc21, 0x22, 0 + .dw 0xafc0, 0xcc21, 0xb03f, 0xcc21, 0x22, 0 + .dw 0xb240, 0xcc21, 0xb27f, 0xcc21, 0x22, 0 + .dw 0xb480, 0xcc21, 0xb4bf, 0xcc21, 0x22, 0 + .dw 0xb6c0, 0xcc21, 0xb6ff, 0xcc21, 0x22, 0 + .dw 0xb900, 0xcc21, 0xb93f, 0xcc21, 0x22, 0 + .dw 0xbb40, 0xcc21, 0xbb7f, 0xcc21, 0x22, 0 + .dw 0xbd80, 0xcc21, 0xbdbf, 0xcc21, 0x22, 0 + .dw 0xbfc0, 0xcc21, 0xc03f, 0xcc21, 0x22, 0 + .dw 0xc240, 0xcc21, 0xc27f, 0xcc21, 0x22, 0 + .dw 0xc480, 0xcc21, 0xc4bf, 0xcc21, 0x22, 0 + .dw 0xc6c0, 0xcc21, 0xc6ff, 0xcc21, 0x22, 0 + .dw 0xc900, 0xcc21, 0xc93f, 0xcc21, 0x22, 0 + .dw 0xcb40, 0xcc21, 0xcb7f, 0xcc21, 0x22, 0 + .dw 0xcd80, 0xcc21, 0xcdbf, 0xcc21, 0x22, 0 + .dw 0xcfc0, 0xcc21, 0xd03f, 0xcc21, 0x22, 0 + .dw 0xd240, 0xcc21, 0xd27f, 0xcc21, 0x22, 0 + .dw 0xd480, 0xcc21, 0xd4bf, 0xcc21, 0x22, 0 + .dw 0xd6c0, 0xcc21, 0xd6ff, 0xcc21, 0x22, 0 + .dw 0xd900, 0xcc21, 0xd93f, 0xcc21, 0x22, 0 + .dw 0xdb40, 0xcc21, 0xdb7f, 0xcc21, 0x22, 0 + .dw 0xdd80, 0xcc21, 0xddbf, 0xcc21, 0x22, 0 + .dw 0xdfc0, 0xcc21, 0xe03f, 0xcc21, 0x22, 0 + .dw 0xe240, 0xcc21, 0xe27f, 0xcc21, 0x22, 0 + .dw 0xe480, 0xcc21, 0xe4bf, 0xcc21, 0x22, 0 + .dw 0xe6c0, 0xcc21, 0xe6ff, 0xcc21, 0x22, 0 + .dw 0xe900, 0xcc21, 0xe93f, 0xcc21, 0x22, 0 + .dw 0xeb40, 0xcc21, 0xeb7f, 0xcc21, 0x22, 0 + .dw 0xed80, 0xcc21, 0xedbf, 0xcc21, 0x22, 0 + .dw 0xefc0, 0xcc21, 0xf03f, 0xcc21, 0x22, 0 + .dw 0xf240, 0xcc21, 0xf27f, 0xcc21, 0x22, 0 + .dw 0xf480, 0xcc21, 0xf4bf, 0xcc21, 0x22, 0 + .dw 0xf6c0, 0xcc21, 0xf6ff, 0xcc21, 0x22, 0 + .dw 0xf900, 0xcc21, 0xf93f, 0xcc21, 0x22, 0 + .dw 0xfb40, 0xcc21, 0xfb7f, 0xcc21, 0x22, 0 + .dw 0xfd80, 0xcc21, 0xfdbf, 0xcc21, 0x22, 0 + .dw 0xffc0, 0xcc21, 0xffff, 0xcc21, 0x22, 0 + .dw 0x1000, 0xcc22, 0x1fff, 0xcc22, 0x21, 0 + .dw 0x3000, 0xcc22, 0x3fff, 0xcc22, 0x21, 0 + .dw 0x5000, 0xcc22, 0x5fff, 0xcc22, 0x21, 0 + .dw 0x7000, 0xcc22, 0x7fff, 0xcc22, 0x21, 0 + .dw 0x9000, 0xcc22, 0x9fff, 0xcc22, 0x21, 0 + .dw 0xb000, 0xcc22, 0xbfff, 0xcc22, 0x21, 0 + .dw 0xd000, 0xcc22, 0xdfff, 0xcc22, 0x21, 0 + .dw 0xf000, 0xcc22, 0xffff, 0xcc22, 0x21, 0 + .dw 0x1000, 0xcc23, 0x1fff, 0xcc23, 0x21, 0 + .dw 0x3000, 0xcc23, 0x3fff, 0xcc23, 0x21, 0 + .dw 0x5000, 0xcc23, 0x5fff, 0xcc23, 0x21, 0 + .dw 0x7000, 0xcc23, 0x7fff, 0xcc23, 0x21, 0 + .dw 0x9000, 0xcc23, 0x9fff, 0xcc23, 0x21, 0 + .dw 0xb000, 0xcc23, 0xbfff, 0xcc23, 0x21, 0 + .dw 0xd000, 0xcc23, 0xdfff, 0xcc23, 0x21, 0 + .dw 0xf000, 0xcc23, 0xffff, 0xcc24, 0x21, 0 + .dw 0x1000, 0xcc25, 0x3fff, 0xcc25, 0x21, 0 + .dw 0x5000, 0xcc25, 0x8fff, 0xcc25, 0x21, 0 + .dw 0xa000, 0xcc25, 0xcfff, 0xcc25, 0x21, 0 + .dw 0xe000, 0xcc25, 0xffff, 0xcc28, 0x21, 0 + .dw 0x1000, 0xcc29, 0x7fff, 0xcc29, 0x21, 0 + .dw 0x9000, 0xcc29, 0xffff, 0xcc2a, 0x21, 0 + .dw 0x1000, 0xcc2b, 0x3fff, 0xcc2b, 0x21, 0 + .dw 0x5000, 0xcc2b, 0xbfff, 0xcc2c, 0x21, 0 + .dw 0xd000, 0xcc2c, 0xffff, 0xcc2d, 0x21, 0 + .dw 0x1000, 0xcc2e, 0x3fff, 0xcc2e, 0x21, 0 + .dw 0x5000, 0xcc2e, 0xffff, 0xcc2f, 0x21, 0 + .dw 0x1000, 0xcc30, 0x3fff, 0xcc30, 0x21, 0 + .dw 0x5000, 0xcc30, 0xffff, 0xcc35, 0x21, 0 + .dw 0x0001, 0xcc36, 0x0001, 0xcc36, 0x21, 0 + .dw 0x0003, 0xcc36, 0x000f, 0xcc36, 0x21, 0 + .dw 0x0011, 0xcc36, 0x0011, 0xcc36, 0x21, 0 + .dw 0x0013, 0xcc36, 0x003f, 0xcc36, 0x21, 0 + .dw 0x0041, 0xcc36, 0x0041, 0xcc36, 0x21, 0 + .dw 0x0043, 0xcc36, 0x004f, 0xcc36, 0x21, 0 + .dw 0x0051, 0xcc36, 0x0051, 0xcc36, 0x21, 0 + .dw 0x0053, 0xcc36, 0x007f, 0xcc36, 0x21, 0 + .dw 0x0081, 0xcc36, 0x0081, 0xcc36, 0x21, 0 + .dw 0x0083, 0xcc36, 0x008f, 0xcc36, 0x21, 0 + .dw 0x0091, 0xcc36, 0x0091, 0xcc36, 0x21, 0 + .dw 0x0093, 0xcc36, 0x00bf, 0xcc36, 0x21, 0 + .dw 0x00c1, 0xcc36, 0x00c1, 0xcc36, 0x21, 0 + .dw 0x00c3, 0xcc36, 0x00cf, 0xcc36, 0x21, 0 + .dw 0x00d1, 0xcc36, 0x00d1, 0xcc36, 0x21, 0 + .dw 0x00d3, 0xcc36, 0x00ff, 0xcc36, 0x21, 0 + .dw 0x0101, 0xcc36, 0x0101, 0xcc36, 0x21, 0 + .dw 0x0103, 0xcc36, 0x010f, 0xcc36, 0x21, 0 + .dw 0x0111, 0xcc36, 0x0111, 0xcc36, 0x21, 0 + .dw 0x0113, 0xcc36, 0x013f, 0xcc36, 0x21, 0 + .dw 0x0141, 0xcc36, 0x0141, 0xcc36, 0x21, 0 + .dw 0x0143, 0xcc36, 0x014f, 0xcc36, 0x21, 0 + .dw 0x0151, 0xcc36, 0x0151, 0xcc36, 0x21, 0 + .dw 0x0153, 0xcc36, 0x017f, 0xcc36, 0x21, 0 + .dw 0x0181, 0xcc36, 0x0181, 0xcc36, 0x21, 0 + .dw 0x0183, 0xcc36, 0x018f, 0xcc36, 0x21, 0 + .dw 0x0191, 0xcc36, 0x0191, 0xcc36, 0x21, 0 + .dw 0x0193, 0xcc36, 0x01bf, 0xcc36, 0x21, 0 + .dw 0x01c1, 0xcc36, 0x01c1, 0xcc36, 0x21, 0 + .dw 0x01c3, 0xcc36, 0x01cf, 0xcc36, 0x21, 0 + .dw 0x01d1, 0xcc36, 0x01d1, 0xcc36, 0x21, 0 + .dw 0x01d3, 0xcc36, 0x01ff, 0xcc36, 0x21, 0 + .dw 0x0201, 0xcc36, 0x0201, 0xcc36, 0x21, 0 + .dw 0x0203, 0xcc36, 0x020f, 0xcc36, 0x21, 0 + .dw 0x0211, 0xcc36, 0x0211, 0xcc36, 0x21, 0 + .dw 0x0213, 0xcc36, 0x023f, 0xcc36, 0x21, 0 + .dw 0x0241, 0xcc36, 0x0241, 0xcc36, 0x21, 0 + .dw 0x0243, 0xcc36, 0x024f, 0xcc36, 0x21, 0 + .dw 0x0251, 0xcc36, 0x0251, 0xcc36, 0x21, 0 + .dw 0x0253, 0xcc36, 0x027f, 0xcc36, 0x21, 0 + .dw 0x0281, 0xcc36, 0x0281, 0xcc36, 0x21, 0 + .dw 0x0283, 0xcc36, 0x028f, 0xcc36, 0x21, 0 + .dw 0x0291, 0xcc36, 0x0291, 0xcc36, 0x21, 0 + .dw 0x0293, 0xcc36, 0x02bf, 0xcc36, 0x21, 0 + .dw 0x02c1, 0xcc36, 0x02c1, 0xcc36, 0x21, 0 + .dw 0x02c3, 0xcc36, 0x02cf, 0xcc36, 0x21, 0 + .dw 0x02d1, 0xcc36, 0x02d1, 0xcc36, 0x21, 0 + .dw 0x02d3, 0xcc36, 0x02ff, 0xcc36, 0x21, 0 + .dw 0x0301, 0xcc36, 0x0301, 0xcc36, 0x21, 0 + .dw 0x0303, 0xcc36, 0x030f, 0xcc36, 0x21, 0 + .dw 0x0311, 0xcc36, 0x0311, 0xcc36, 0x21, 0 + .dw 0x0313, 0xcc36, 0x033f, 0xcc36, 0x21, 0 + .dw 0x0341, 0xcc36, 0x0341, 0xcc36, 0x21, 0 + .dw 0x0343, 0xcc36, 0x034f, 0xcc36, 0x21, 0 + .dw 0x0351, 0xcc36, 0x0351, 0xcc36, 0x21, 0 + .dw 0x0353, 0xcc36, 0x037f, 0xcc36, 0x21, 0 + .dw 0x0381, 0xcc36, 0x0381, 0xcc36, 0x21, 0 + .dw 0x0383, 0xcc36, 0x038f, 0xcc36, 0x21, 0 + .dw 0x0391, 0xcc36, 0x0391, 0xcc36, 0x21, 0 + .dw 0x0393, 0xcc36, 0x03bf, 0xcc36, 0x21, 0 + .dw 0x03c1, 0xcc36, 0x03c1, 0xcc36, 0x21, 0 + .dw 0x03c3, 0xcc36, 0x03cf, 0xcc36, 0x21, 0 + .dw 0x03d1, 0xcc36, 0x03d1, 0xcc36, 0x21, 0 + .dw 0x03d3, 0xcc36, 0x03ff, 0xcc36, 0x21, 0 + .dw 0x0401, 0xcc36, 0x0401, 0xcc36, 0x21, 0 + .dw 0x0403, 0xcc36, 0x040f, 0xcc36, 0x21, 0 + .dw 0x0411, 0xcc36, 0x0411, 0xcc36, 0x21, 0 + .dw 0x0413, 0xcc36, 0x043f, 0xcc36, 0x21, 0 + .dw 0x0441, 0xcc36, 0x0441, 0xcc36, 0x21, 0 + .dw 0x0443, 0xcc36, 0x044f, 0xcc36, 0x21, 0 + .dw 0x0451, 0xcc36, 0x0451, 0xcc36, 0x21, 0 + .dw 0x0453, 0xcc36, 0x047f, 0xcc36, 0x21, 0 + .dw 0x0481, 0xcc36, 0x0481, 0xcc36, 0x21, 0 + .dw 0x0483, 0xcc36, 0x048f, 0xcc36, 0x21, 0 + .dw 0x0491, 0xcc36, 0x0491, 0xcc36, 0x21, 0 + .dw 0x0493, 0xcc36, 0x04bf, 0xcc36, 0x21, 0 + .dw 0x04c1, 0xcc36, 0x04c1, 0xcc36, 0x21, 0 + .dw 0x04c3, 0xcc36, 0x04cf, 0xcc36, 0x21, 0 + .dw 0x04d1, 0xcc36, 0x04d1, 0xcc36, 0x21, 0 + .dw 0x04d3, 0xcc36, 0x04ff, 0xcc36, 0x21, 0 + .dw 0x0501, 0xcc36, 0x0501, 0xcc36, 0x21, 0 + .dw 0x0503, 0xcc36, 0x050f, 0xcc36, 0x21, 0 + .dw 0x0511, 0xcc36, 0x0511, 0xcc36, 0x21, 0 + .dw 0x0513, 0xcc36, 0x053f, 0xcc36, 0x21, 0 + .dw 0x0541, 0xcc36, 0x0541, 0xcc36, 0x21, 0 + .dw 0x0543, 0xcc36, 0x054f, 0xcc36, 0x21, 0 + .dw 0x0551, 0xcc36, 0x0551, 0xcc36, 0x21, 0 + .dw 0x0553, 0xcc36, 0x057f, 0xcc36, 0x21, 0 + .dw 0x0581, 0xcc36, 0x0581, 0xcc36, 0x21, 0 + .dw 0x0583, 0xcc36, 0x058f, 0xcc36, 0x21, 0 + .dw 0x0591, 0xcc36, 0x0591, 0xcc36, 0x21, 0 + .dw 0x0593, 0xcc36, 0x05bf, 0xcc36, 0x21, 0 + .dw 0x05c1, 0xcc36, 0x05c1, 0xcc36, 0x21, 0 + .dw 0x05c3, 0xcc36, 0x05cf, 0xcc36, 0x21, 0 + .dw 0x05d1, 0xcc36, 0x05d1, 0xcc36, 0x21, 0 + .dw 0x05d3, 0xcc36, 0x05ff, 0xcc36, 0x21, 0 + .dw 0x0601, 0xcc36, 0x0601, 0xcc36, 0x21, 0 + .dw 0x0603, 0xcc36, 0x060f, 0xcc36, 0x21, 0 + .dw 0x0611, 0xcc36, 0x0611, 0xcc36, 0x21, 0 + .dw 0x0613, 0xcc36, 0x063f, 0xcc36, 0x21, 0 + .dw 0x0641, 0xcc36, 0x0641, 0xcc36, 0x21, 0 + .dw 0x0643, 0xcc36, 0x064f, 0xcc36, 0x21, 0 + .dw 0x0651, 0xcc36, 0x0651, 0xcc36, 0x21, 0 + .dw 0x0653, 0xcc36, 0x067f, 0xcc36, 0x21, 0 + .dw 0x0681, 0xcc36, 0x0681, 0xcc36, 0x21, 0 + .dw 0x0683, 0xcc36, 0x068f, 0xcc36, 0x21, 0 + .dw 0x0691, 0xcc36, 0x0691, 0xcc36, 0x21, 0 + .dw 0x0693, 0xcc36, 0x06bf, 0xcc36, 0x21, 0 + .dw 0x06c1, 0xcc36, 0x06c1, 0xcc36, 0x21, 0 + .dw 0x06c3, 0xcc36, 0x06cf, 0xcc36, 0x21, 0 + .dw 0x06d1, 0xcc36, 0x06d1, 0xcc36, 0x21, 0 + .dw 0x06d3, 0xcc36, 0x06ff, 0xcc36, 0x21, 0 + .dw 0x0701, 0xcc36, 0x0701, 0xcc36, 0x21, 0 + .dw 0x0703, 0xcc36, 0x070f, 0xcc36, 0x21, 0 + .dw 0x0711, 0xcc36, 0x0711, 0xcc36, 0x21, 0 + .dw 0x0713, 0xcc36, 0x073f, 0xcc36, 0x21, 0 + .dw 0x0741, 0xcc36, 0x0741, 0xcc36, 0x21, 0 + .dw 0x0743, 0xcc36, 0x074f, 0xcc36, 0x21, 0 + .dw 0x0751, 0xcc36, 0x0751, 0xcc36, 0x21, 0 + .dw 0x0753, 0xcc36, 0x077f, 0xcc36, 0x21, 0 + .dw 0x0781, 0xcc36, 0x0781, 0xcc36, 0x21, 0 + .dw 0x0783, 0xcc36, 0x078f, 0xcc36, 0x21, 0 + .dw 0x0791, 0xcc36, 0x0791, 0xcc36, 0x21, 0 + .dw 0x0793, 0xcc36, 0x07bf, 0xcc36, 0x21, 0 + .dw 0x07c1, 0xcc36, 0x07c1, 0xcc36, 0x21, 0 + .dw 0x07c3, 0xcc36, 0x07cf, 0xcc36, 0x21, 0 + .dw 0x07d1, 0xcc36, 0x07d1, 0xcc36, 0x21, 0 + .dw 0x07d3, 0xcc36, 0x07ff, 0xcc36, 0x21, 0 + .dw 0x0801, 0xcc36, 0x0801, 0xcc36, 0x21, 0 + .dw 0x0803, 0xcc36, 0x080f, 0xcc36, 0x21, 0 + .dw 0x0811, 0xcc36, 0x0811, 0xcc36, 0x21, 0 + .dw 0x0813, 0xcc36, 0x083f, 0xcc36, 0x21, 0 + .dw 0x0841, 0xcc36, 0x0841, 0xcc36, 0x21, 0 + .dw 0x0843, 0xcc36, 0x084f, 0xcc36, 0x21, 0 + .dw 0x0851, 0xcc36, 0x0851, 0xcc36, 0x21, 0 + .dw 0x0853, 0xcc36, 0x087f, 0xcc36, 0x21, 0 + .dw 0x0881, 0xcc36, 0x0881, 0xcc36, 0x21, 0 + .dw 0x0883, 0xcc36, 0x088f, 0xcc36, 0x21, 0 + .dw 0x0891, 0xcc36, 0x0891, 0xcc36, 0x21, 0 + .dw 0x0893, 0xcc36, 0x08bf, 0xcc36, 0x21, 0 + .dw 0x08c1, 0xcc36, 0x08c1, 0xcc36, 0x21, 0 + .dw 0x08c3, 0xcc36, 0x08cf, 0xcc36, 0x21, 0 + .dw 0x08d1, 0xcc36, 0x08d1, 0xcc36, 0x21, 0 + .dw 0x08d3, 0xcc36, 0x08ff, 0xcc36, 0x21, 0 + .dw 0x0901, 0xcc36, 0x0901, 0xcc36, 0x21, 0 + .dw 0x0903, 0xcc36, 0x090f, 0xcc36, 0x21, 0 + .dw 0x0911, 0xcc36, 0x0911, 0xcc36, 0x21, 0 + .dw 0x0913, 0xcc36, 0x093f, 0xcc36, 0x21, 0 + .dw 0x0941, 0xcc36, 0x0941, 0xcc36, 0x21, 0 + .dw 0x0943, 0xcc36, 0x094f, 0xcc36, 0x21, 0 + .dw 0x0951, 0xcc36, 0x0951, 0xcc36, 0x21, 0 + .dw 0x0953, 0xcc36, 0x097f, 0xcc36, 0x21, 0 + .dw 0x0981, 0xcc36, 0x0981, 0xcc36, 0x21, 0 + .dw 0x0983, 0xcc36, 0x098f, 0xcc36, 0x21, 0 + .dw 0x0991, 0xcc36, 0x0991, 0xcc36, 0x21, 0 + .dw 0x0993, 0xcc36, 0x09bf, 0xcc36, 0x21, 0 + .dw 0x09c1, 0xcc36, 0x09c1, 0xcc36, 0x21, 0 + .dw 0x09c3, 0xcc36, 0x09cf, 0xcc36, 0x21, 0 + .dw 0x09d1, 0xcc36, 0x09d1, 0xcc36, 0x21, 0 + .dw 0x09d3, 0xcc36, 0x09ff, 0xcc36, 0x21, 0 + .dw 0x0a01, 0xcc36, 0x0a01, 0xcc36, 0x21, 0 + .dw 0x0a03, 0xcc36, 0x0a0f, 0xcc36, 0x21, 0 + .dw 0x0a11, 0xcc36, 0x0a11, 0xcc36, 0x21, 0 + .dw 0x0a13, 0xcc36, 0x0a3f, 0xcc36, 0x21, 0 + .dw 0x0a41, 0xcc36, 0x0a41, 0xcc36, 0x21, 0 + .dw 0x0a43, 0xcc36, 0x0a4f, 0xcc36, 0x21, 0 + .dw 0x0a51, 0xcc36, 0x0a51, 0xcc36, 0x21, 0 + .dw 0x0a53, 0xcc36, 0x0a7f, 0xcc36, 0x21, 0 + .dw 0x0a81, 0xcc36, 0x0a81, 0xcc36, 0x21, 0 + .dw 0x0a83, 0xcc36, 0x0a8f, 0xcc36, 0x21, 0 + .dw 0x0a91, 0xcc36, 0x0a91, 0xcc36, 0x21, 0 + .dw 0x0a93, 0xcc36, 0x0abf, 0xcc36, 0x21, 0 + .dw 0x0ac1, 0xcc36, 0x0ac1, 0xcc36, 0x21, 0 + .dw 0x0ac3, 0xcc36, 0x0acf, 0xcc36, 0x21, 0 + .dw 0x0ad1, 0xcc36, 0x0ad1, 0xcc36, 0x21, 0 + .dw 0x0ad3, 0xcc36, 0x0aff, 0xcc36, 0x21, 0 + .dw 0x0b01, 0xcc36, 0x0b01, 0xcc36, 0x21, 0 + .dw 0x0b03, 0xcc36, 0x0b0f, 0xcc36, 0x21, 0 + .dw 0x0b11, 0xcc36, 0x0b11, 0xcc36, 0x21, 0 + .dw 0x0b13, 0xcc36, 0x0b3f, 0xcc36, 0x21, 0 + .dw 0x0b41, 0xcc36, 0x0b41, 0xcc36, 0x21, 0 + .dw 0x0b43, 0xcc36, 0x0b4f, 0xcc36, 0x21, 0 + .dw 0x0b51, 0xcc36, 0x0b51, 0xcc36, 0x21, 0 + .dw 0x0b53, 0xcc36, 0x0b7f, 0xcc36, 0x21, 0 + .dw 0x0b81, 0xcc36, 0x0b81, 0xcc36, 0x21, 0 + .dw 0x0b83, 0xcc36, 0x0b8f, 0xcc36, 0x21, 0 + .dw 0x0b91, 0xcc36, 0x0b91, 0xcc36, 0x21, 0 + .dw 0x0b93, 0xcc36, 0x0bbf, 0xcc36, 0x21, 0 + .dw 0x0bc1, 0xcc36, 0x0bc1, 0xcc36, 0x21, 0 + .dw 0x0bc3, 0xcc36, 0x0bcf, 0xcc36, 0x21, 0 + .dw 0x0bd1, 0xcc36, 0x0bd1, 0xcc36, 0x21, 0 + .dw 0x0bd3, 0xcc36, 0x0bff, 0xcc36, 0x21, 0 + .dw 0x0c01, 0xcc36, 0x0c01, 0xcc36, 0x21, 0 + .dw 0x0c03, 0xcc36, 0x0c0f, 0xcc36, 0x21, 0 + .dw 0x0c11, 0xcc36, 0x0c11, 0xcc36, 0x21, 0 + .dw 0x0c13, 0xcc36, 0x0c3f, 0xcc36, 0x21, 0 + .dw 0x0c41, 0xcc36, 0x0c41, 0xcc36, 0x21, 0 + .dw 0x0c43, 0xcc36, 0x0c4f, 0xcc36, 0x21, 0 + .dw 0x0c51, 0xcc36, 0x0c51, 0xcc36, 0x21, 0 + .dw 0x0c53, 0xcc36, 0x0c7f, 0xcc36, 0x21, 0 + .dw 0x0c81, 0xcc36, 0x0c81, 0xcc36, 0x21, 0 + .dw 0x0c83, 0xcc36, 0x0c8f, 0xcc36, 0x21, 0 + .dw 0x0c91, 0xcc36, 0x0c91, 0xcc36, 0x21, 0 + .dw 0x0c93, 0xcc36, 0x0cbf, 0xcc36, 0x21, 0 + .dw 0x0cc1, 0xcc36, 0x0cc1, 0xcc36, 0x21, 0 + .dw 0x0cc3, 0xcc36, 0x0ccf, 0xcc36, 0x21, 0 + .dw 0x0cd1, 0xcc36, 0x0cd1, 0xcc36, 0x21, 0 + .dw 0x0cd3, 0xcc36, 0x0cff, 0xcc36, 0x21, 0 + .dw 0x0d01, 0xcc36, 0x0d01, 0xcc36, 0x21, 0 + .dw 0x0d03, 0xcc36, 0x0d0f, 0xcc36, 0x21, 0 + .dw 0x0d11, 0xcc36, 0x0d11, 0xcc36, 0x21, 0 + .dw 0x0d13, 0xcc36, 0x0d3f, 0xcc36, 0x21, 0 + .dw 0x0d41, 0xcc36, 0x0d41, 0xcc36, 0x21, 0 + .dw 0x0d43, 0xcc36, 0x0d4f, 0xcc36, 0x21, 0 + .dw 0x0d51, 0xcc36, 0x0d51, 0xcc36, 0x21, 0 + .dw 0x0d53, 0xcc36, 0x0d7f, 0xcc36, 0x21, 0 + .dw 0x0d81, 0xcc36, 0x0d81, 0xcc36, 0x21, 0 + .dw 0x0d83, 0xcc36, 0x0d8f, 0xcc36, 0x21, 0 + .dw 0x0d91, 0xcc36, 0x0d91, 0xcc36, 0x21, 0 + .dw 0x0d93, 0xcc36, 0x0dbf, 0xcc36, 0x21, 0 + .dw 0x0dc1, 0xcc36, 0x0dc1, 0xcc36, 0x21, 0 + .dw 0x0dc3, 0xcc36, 0x0dcf, 0xcc36, 0x21, 0 + .dw 0x0dd1, 0xcc36, 0x0dd1, 0xcc36, 0x21, 0 + .dw 0x0dd3, 0xcc36, 0x0dff, 0xcc36, 0x21, 0 + .dw 0x0e01, 0xcc36, 0x0e01, 0xcc36, 0x21, 0 + .dw 0x0e03, 0xcc36, 0x0e0f, 0xcc36, 0x21, 0 + .dw 0x0e11, 0xcc36, 0x0e11, 0xcc36, 0x21, 0 + .dw 0x0e13, 0xcc36, 0x0e3f, 0xcc36, 0x21, 0 + .dw 0x0e41, 0xcc36, 0x0e41, 0xcc36, 0x21, 0 + .dw 0x0e43, 0xcc36, 0x0e4f, 0xcc36, 0x21, 0 + .dw 0x0e51, 0xcc36, 0x0e51, 0xcc36, 0x21, 0 + .dw 0x0e53, 0xcc36, 0x0e7f, 0xcc36, 0x21, 0 + .dw 0x0e81, 0xcc36, 0x0e81, 0xcc36, 0x21, 0 + .dw 0x0e83, 0xcc36, 0x0e8f, 0xcc36, 0x21, 0 + .dw 0x0e91, 0xcc36, 0x0e91, 0xcc36, 0x21, 0 + .dw 0x0e93, 0xcc36, 0x0ebf, 0xcc36, 0x21, 0 + .dw 0x0ec1, 0xcc36, 0x0ec1, 0xcc36, 0x21, 0 + .dw 0x0ec3, 0xcc36, 0x0ecf, 0xcc36, 0x21, 0 + .dw 0x0ed1, 0xcc36, 0x0ed1, 0xcc36, 0x21, 0 + .dw 0x0ed3, 0xcc36, 0x0eff, 0xcc36, 0x21, 0 + .dw 0x0f01, 0xcc36, 0x0f01, 0xcc36, 0x21, 0 + .dw 0x0f03, 0xcc36, 0x0f0f, 0xcc36, 0x21, 0 + .dw 0x0f11, 0xcc36, 0x0f11, 0xcc36, 0x21, 0 + .dw 0x0f13, 0xcc36, 0x0f3f, 0xcc36, 0x21, 0 + .dw 0x0f41, 0xcc36, 0x0f41, 0xcc36, 0x21, 0 + .dw 0x0f43, 0xcc36, 0x0f4f, 0xcc36, 0x21, 0 + .dw 0x0f51, 0xcc36, 0x0f51, 0xcc36, 0x21, 0 + .dw 0x0f53, 0xcc36, 0x0f7f, 0xcc36, 0x21, 0 + .dw 0x0f81, 0xcc36, 0x0f81, 0xcc36, 0x21, 0 + .dw 0x0f83, 0xcc36, 0x0f8f, 0xcc36, 0x21, 0 + .dw 0x0f91, 0xcc36, 0x0f91, 0xcc36, 0x21, 0 + .dw 0x0f93, 0xcc36, 0x0fbf, 0xcc36, 0x21, 0 + .dw 0x0fc1, 0xcc36, 0x0fc1, 0xcc36, 0x21, 0 + .dw 0x0fc3, 0xcc36, 0x0fcf, 0xcc36, 0x21, 0 + .dw 0x0fd1, 0xcc36, 0x0fd1, 0xcc36, 0x21, 0 + .dw 0x0fd3, 0xcc36, 0x1fff, 0xcc36, 0x21, 0 + .dw 0x2001, 0xcc36, 0x2001, 0xcc36, 0x21, 0 + .dw 0x2003, 0xcc36, 0x200f, 0xcc36, 0x21, 0 + .dw 0x2011, 0xcc36, 0x2011, 0xcc36, 0x21, 0 + .dw 0x2013, 0xcc36, 0x203f, 0xcc36, 0x21, 0 + .dw 0x2041, 0xcc36, 0x2041, 0xcc36, 0x21, 0 + .dw 0x2043, 0xcc36, 0x204f, 0xcc36, 0x21, 0 + .dw 0x2051, 0xcc36, 0x2051, 0xcc36, 0x21, 0 + .dw 0x2053, 0xcc36, 0x207f, 0xcc36, 0x21, 0 + .dw 0x2081, 0xcc36, 0x2081, 0xcc36, 0x21, 0 + .dw 0x2083, 0xcc36, 0x208f, 0xcc36, 0x21, 0 + .dw 0x2091, 0xcc36, 0x2091, 0xcc36, 0x21, 0 + .dw 0x2093, 0xcc36, 0x20bf, 0xcc36, 0x21, 0 + .dw 0x20c1, 0xcc36, 0x20c1, 0xcc36, 0x21, 0 + .dw 0x20c3, 0xcc36, 0x20cf, 0xcc36, 0x21, 0 + .dw 0x20d1, 0xcc36, 0x20d1, 0xcc36, 0x21, 0 + .dw 0x20d3, 0xcc36, 0x20ff, 0xcc36, 0x21, 0 + .dw 0x2101, 0xcc36, 0x2101, 0xcc36, 0x21, 0 + .dw 0x2103, 0xcc36, 0x210f, 0xcc36, 0x21, 0 + .dw 0x2111, 0xcc36, 0x2111, 0xcc36, 0x21, 0 + .dw 0x2113, 0xcc36, 0x213f, 0xcc36, 0x21, 0 + .dw 0x2141, 0xcc36, 0x2141, 0xcc36, 0x21, 0 + .dw 0x2143, 0xcc36, 0x214f, 0xcc36, 0x21, 0 + .dw 0x2151, 0xcc36, 0x2151, 0xcc36, 0x21, 0 + .dw 0x2153, 0xcc36, 0x217f, 0xcc36, 0x21, 0 + .dw 0x2181, 0xcc36, 0x2181, 0xcc36, 0x21, 0 + .dw 0x2183, 0xcc36, 0x218f, 0xcc36, 0x21, 0 + .dw 0x2191, 0xcc36, 0x2191, 0xcc36, 0x21, 0 + .dw 0x2193, 0xcc36, 0x21bf, 0xcc36, 0x21, 0 + .dw 0x21c1, 0xcc36, 0x21c1, 0xcc36, 0x21, 0 + .dw 0x21c3, 0xcc36, 0x21cf, 0xcc36, 0x21, 0 + .dw 0x21d1, 0xcc36, 0x21d1, 0xcc36, 0x21, 0 + .dw 0x21d3, 0xcc36, 0x21ff, 0xcc36, 0x21, 0 + .dw 0x2201, 0xcc36, 0x2201, 0xcc36, 0x21, 0 + .dw 0x2203, 0xcc36, 0x220f, 0xcc36, 0x21, 0 + .dw 0x2211, 0xcc36, 0x2211, 0xcc36, 0x21, 0 + .dw 0x2213, 0xcc36, 0x223f, 0xcc36, 0x21, 0 + .dw 0x2241, 0xcc36, 0x2241, 0xcc36, 0x21, 0 + .dw 0x2243, 0xcc36, 0x224f, 0xcc36, 0x21, 0 + .dw 0x2251, 0xcc36, 0x2251, 0xcc36, 0x21, 0 + .dw 0x2253, 0xcc36, 0x227f, 0xcc36, 0x21, 0 + .dw 0x2281, 0xcc36, 0x2281, 0xcc36, 0x21, 0 + .dw 0x2283, 0xcc36, 0x228f, 0xcc36, 0x21, 0 + .dw 0x2291, 0xcc36, 0x2291, 0xcc36, 0x21, 0 + .dw 0x2293, 0xcc36, 0x22bf, 0xcc36, 0x21, 0 + .dw 0x22c1, 0xcc36, 0x22c1, 0xcc36, 0x21, 0 + .dw 0x22c3, 0xcc36, 0x22cf, 0xcc36, 0x21, 0 + .dw 0x22d1, 0xcc36, 0x22d1, 0xcc36, 0x21, 0 + .dw 0x22d3, 0xcc36, 0x22ff, 0xcc36, 0x21, 0 + .dw 0x2301, 0xcc36, 0x2301, 0xcc36, 0x21, 0 + .dw 0x2303, 0xcc36, 0x230f, 0xcc36, 0x21, 0 + .dw 0x2311, 0xcc36, 0x2311, 0xcc36, 0x21, 0 + .dw 0x2313, 0xcc36, 0x233f, 0xcc36, 0x21, 0 + .dw 0x2341, 0xcc36, 0x2341, 0xcc36, 0x21, 0 + .dw 0x2343, 0xcc36, 0x234f, 0xcc36, 0x21, 0 + .dw 0x2351, 0xcc36, 0x2351, 0xcc36, 0x21, 0 + .dw 0x2353, 0xcc36, 0x237f, 0xcc36, 0x21, 0 + .dw 0x2381, 0xcc36, 0x2381, 0xcc36, 0x21, 0 + .dw 0x2383, 0xcc36, 0x238f, 0xcc36, 0x21, 0 + .dw 0x2391, 0xcc36, 0x2391, 0xcc36, 0x21, 0 + .dw 0x2393, 0xcc36, 0x23bf, 0xcc36, 0x21, 0 + .dw 0x23c1, 0xcc36, 0x23c1, 0xcc36, 0x21, 0 + .dw 0x23c3, 0xcc36, 0x23cf, 0xcc36, 0x21, 0 + .dw 0x23d1, 0xcc36, 0x23d1, 0xcc36, 0x21, 0 + .dw 0x23d3, 0xcc36, 0x23ff, 0xcc36, 0x21, 0 + .dw 0x2401, 0xcc36, 0x2401, 0xcc36, 0x21, 0 + .dw 0x2403, 0xcc36, 0x240f, 0xcc36, 0x21, 0 + .dw 0x2411, 0xcc36, 0x2411, 0xcc36, 0x21, 0 + .dw 0x2413, 0xcc36, 0x243f, 0xcc36, 0x21, 0 + .dw 0x2441, 0xcc36, 0x2441, 0xcc36, 0x21, 0 + .dw 0x2443, 0xcc36, 0x244f, 0xcc36, 0x21, 0 + .dw 0x2451, 0xcc36, 0x2451, 0xcc36, 0x21, 0 + .dw 0x2453, 0xcc36, 0x247f, 0xcc36, 0x21, 0 + .dw 0x2481, 0xcc36, 0x2481, 0xcc36, 0x21, 0 + .dw 0x2483, 0xcc36, 0x248f, 0xcc36, 0x21, 0 + .dw 0x2491, 0xcc36, 0x2491, 0xcc36, 0x21, 0 + .dw 0x2493, 0xcc36, 0x24bf, 0xcc36, 0x21, 0 + .dw 0x24c1, 0xcc36, 0x24c1, 0xcc36, 0x21, 0 + .dw 0x24c3, 0xcc36, 0x24cf, 0xcc36, 0x21, 0 + .dw 0x24d1, 0xcc36, 0x24d1, 0xcc36, 0x21, 0 + .dw 0x24d3, 0xcc36, 0x24ff, 0xcc36, 0x21, 0 + .dw 0x2501, 0xcc36, 0x2501, 0xcc36, 0x21, 0 + .dw 0x2503, 0xcc36, 0x250f, 0xcc36, 0x21, 0 + .dw 0x2511, 0xcc36, 0x2511, 0xcc36, 0x21, 0 + .dw 0x2513, 0xcc36, 0x253f, 0xcc36, 0x21, 0 + .dw 0x2541, 0xcc36, 0x2541, 0xcc36, 0x21, 0 + .dw 0x2543, 0xcc36, 0x254f, 0xcc36, 0x21, 0 + .dw 0x2551, 0xcc36, 0x2551, 0xcc36, 0x21, 0 + .dw 0x2553, 0xcc36, 0x257f, 0xcc36, 0x21, 0 + .dw 0x2581, 0xcc36, 0x2581, 0xcc36, 0x21, 0 + .dw 0x2583, 0xcc36, 0x258f, 0xcc36, 0x21, 0 + .dw 0x2591, 0xcc36, 0x2591, 0xcc36, 0x21, 0 + .dw 0x2593, 0xcc36, 0x25bf, 0xcc36, 0x21, 0 + .dw 0x25c1, 0xcc36, 0x25c1, 0xcc36, 0x21, 0 + .dw 0x25c3, 0xcc36, 0x25cf, 0xcc36, 0x21, 0 + .dw 0x25d1, 0xcc36, 0x25d1, 0xcc36, 0x21, 0 + .dw 0x25d3, 0xcc36, 0x25ff, 0xcc36, 0x21, 0 + .dw 0x2601, 0xcc36, 0x2601, 0xcc36, 0x21, 0 + .dw 0x2603, 0xcc36, 0x260f, 0xcc36, 0x21, 0 + .dw 0x2611, 0xcc36, 0x2611, 0xcc36, 0x21, 0 + .dw 0x2613, 0xcc36, 0x263f, 0xcc36, 0x21, 0 + .dw 0x2641, 0xcc36, 0x2641, 0xcc36, 0x21, 0 + .dw 0x2643, 0xcc36, 0x264f, 0xcc36, 0x21, 0 + .dw 0x2651, 0xcc36, 0x2651, 0xcc36, 0x21, 0 + .dw 0x2653, 0xcc36, 0x267f, 0xcc36, 0x21, 0 + .dw 0x2681, 0xcc36, 0x2681, 0xcc36, 0x21, 0 + .dw 0x2683, 0xcc36, 0x268f, 0xcc36, 0x21, 0 + .dw 0x2691, 0xcc36, 0x2691, 0xcc36, 0x21, 0 + .dw 0x2693, 0xcc36, 0x26bf, 0xcc36, 0x21, 0 + .dw 0x26c1, 0xcc36, 0x26c1, 0xcc36, 0x21, 0 + .dw 0x26c3, 0xcc36, 0x26cf, 0xcc36, 0x21, 0 + .dw 0x26d1, 0xcc36, 0x26d1, 0xcc36, 0x21, 0 + .dw 0x26d3, 0xcc36, 0x26ff, 0xcc36, 0x21, 0 + .dw 0x2701, 0xcc36, 0x2701, 0xcc36, 0x21, 0 + .dw 0x2703, 0xcc36, 0x270f, 0xcc36, 0x21, 0 + .dw 0x2711, 0xcc36, 0x2711, 0xcc36, 0x21, 0 + .dw 0x2713, 0xcc36, 0x273f, 0xcc36, 0x21, 0 + .dw 0x2741, 0xcc36, 0x2741, 0xcc36, 0x21, 0 + .dw 0x2743, 0xcc36, 0x274f, 0xcc36, 0x21, 0 + .dw 0x2751, 0xcc36, 0x2751, 0xcc36, 0x21, 0 + .dw 0x2753, 0xcc36, 0x277f, 0xcc36, 0x21, 0 + .dw 0x2781, 0xcc36, 0x2781, 0xcc36, 0x21, 0 + .dw 0x2783, 0xcc36, 0x278f, 0xcc36, 0x21, 0 + .dw 0x2791, 0xcc36, 0x2791, 0xcc36, 0x21, 0 + .dw 0x2793, 0xcc36, 0x27bf, 0xcc36, 0x21, 0 + .dw 0x27c1, 0xcc36, 0x27c1, 0xcc36, 0x21, 0 + .dw 0x27c3, 0xcc36, 0x27cf, 0xcc36, 0x21, 0 + .dw 0x27d1, 0xcc36, 0x27d1, 0xcc36, 0x21, 0 + .dw 0x27d3, 0xcc36, 0x27ff, 0xcc36, 0x21, 0 + .dw 0x2801, 0xcc36, 0x2801, 0xcc36, 0x21, 0 + .dw 0x2803, 0xcc36, 0x280f, 0xcc36, 0x21, 0 + .dw 0x2811, 0xcc36, 0x2811, 0xcc36, 0x21, 0 + .dw 0x2813, 0xcc36, 0x283f, 0xcc36, 0x21, 0 + .dw 0x2841, 0xcc36, 0x2841, 0xcc36, 0x21, 0 + .dw 0x2843, 0xcc36, 0x284f, 0xcc36, 0x21, 0 + .dw 0x2851, 0xcc36, 0x2851, 0xcc36, 0x21, 0 + .dw 0x2853, 0xcc36, 0x287f, 0xcc36, 0x21, 0 + .dw 0x2881, 0xcc36, 0x2881, 0xcc36, 0x21, 0 + .dw 0x2883, 0xcc36, 0x288f, 0xcc36, 0x21, 0 + .dw 0x2891, 0xcc36, 0x2891, 0xcc36, 0x21, 0 + .dw 0x2893, 0xcc36, 0x28bf, 0xcc36, 0x21, 0 + .dw 0x28c1, 0xcc36, 0x28c1, 0xcc36, 0x21, 0 + .dw 0x28c3, 0xcc36, 0x28cf, 0xcc36, 0x21, 0 + .dw 0x28d1, 0xcc36, 0x28d1, 0xcc36, 0x21, 0 + .dw 0x28d3, 0xcc36, 0x28ff, 0xcc36, 0x21, 0 + .dw 0x2901, 0xcc36, 0x2901, 0xcc36, 0x21, 0 + .dw 0x2903, 0xcc36, 0x290f, 0xcc36, 0x21, 0 + .dw 0x2911, 0xcc36, 0x2911, 0xcc36, 0x21, 0 + .dw 0x2913, 0xcc36, 0x293f, 0xcc36, 0x21, 0 + .dw 0x2941, 0xcc36, 0x2941, 0xcc36, 0x21, 0 + .dw 0x2943, 0xcc36, 0x294f, 0xcc36, 0x21, 0 + .dw 0x2951, 0xcc36, 0x2951, 0xcc36, 0x21, 0 + .dw 0x2953, 0xcc36, 0x297f, 0xcc36, 0x21, 0 + .dw 0x2981, 0xcc36, 0x2981, 0xcc36, 0x21, 0 + .dw 0x2983, 0xcc36, 0x298f, 0xcc36, 0x21, 0 + .dw 0x2991, 0xcc36, 0x2991, 0xcc36, 0x21, 0 + .dw 0x2993, 0xcc36, 0x29bf, 0xcc36, 0x21, 0 + .dw 0x29c1, 0xcc36, 0x29c1, 0xcc36, 0x21, 0 + .dw 0x29c3, 0xcc36, 0x29cf, 0xcc36, 0x21, 0 + .dw 0x29d1, 0xcc36, 0x29d1, 0xcc36, 0x21, 0 + .dw 0x29d3, 0xcc36, 0x29ff, 0xcc36, 0x21, 0 + .dw 0x2a01, 0xcc36, 0x2a01, 0xcc36, 0x21, 0 + .dw 0x2a03, 0xcc36, 0x2a0f, 0xcc36, 0x21, 0 + .dw 0x2a11, 0xcc36, 0x2a11, 0xcc36, 0x21, 0 + .dw 0x2a13, 0xcc36, 0x2a3f, 0xcc36, 0x21, 0 + .dw 0x2a41, 0xcc36, 0x2a41, 0xcc36, 0x21, 0 + .dw 0x2a43, 0xcc36, 0x2a4f, 0xcc36, 0x21, 0 + .dw 0x2a51, 0xcc36, 0x2a51, 0xcc36, 0x21, 0 + .dw 0x2a53, 0xcc36, 0x2a7f, 0xcc36, 0x21, 0 + .dw 0x2a81, 0xcc36, 0x2a81, 0xcc36, 0x21, 0 + .dw 0x2a83, 0xcc36, 0x2a8f, 0xcc36, 0x21, 0 + .dw 0x2a91, 0xcc36, 0x2a91, 0xcc36, 0x21, 0 + .dw 0x2a93, 0xcc36, 0x2abf, 0xcc36, 0x21, 0 + .dw 0x2ac1, 0xcc36, 0x2ac1, 0xcc36, 0x21, 0 + .dw 0x2ac3, 0xcc36, 0x2acf, 0xcc36, 0x21, 0 + .dw 0x2ad1, 0xcc36, 0x2ad1, 0xcc36, 0x21, 0 + .dw 0x2ad3, 0xcc36, 0x2aff, 0xcc36, 0x21, 0 + .dw 0x2b01, 0xcc36, 0x2b01, 0xcc36, 0x21, 0 + .dw 0x2b03, 0xcc36, 0x2b0f, 0xcc36, 0x21, 0 + .dw 0x2b11, 0xcc36, 0x2b11, 0xcc36, 0x21, 0 + .dw 0x2b13, 0xcc36, 0x2b3f, 0xcc36, 0x21, 0 + .dw 0x2b41, 0xcc36, 0x2b41, 0xcc36, 0x21, 0 + .dw 0x2b43, 0xcc36, 0x2b4f, 0xcc36, 0x21, 0 + .dw 0x2b51, 0xcc36, 0x2b51, 0xcc36, 0x21, 0 + .dw 0x2b53, 0xcc36, 0x2b7f, 0xcc36, 0x21, 0 + .dw 0x2b81, 0xcc36, 0x2b81, 0xcc36, 0x21, 0 + .dw 0x2b83, 0xcc36, 0x2b8f, 0xcc36, 0x21, 0 + .dw 0x2b91, 0xcc36, 0x2b91, 0xcc36, 0x21, 0 + .dw 0x2b93, 0xcc36, 0x2bbf, 0xcc36, 0x21, 0 + .dw 0x2bc1, 0xcc36, 0x2bc1, 0xcc36, 0x21, 0 + .dw 0x2bc3, 0xcc36, 0x2bcf, 0xcc36, 0x21, 0 + .dw 0x2bd1, 0xcc36, 0x2bd1, 0xcc36, 0x21, 0 + .dw 0x2bd3, 0xcc36, 0x2bff, 0xcc36, 0x21, 0 + .dw 0x2c01, 0xcc36, 0x2c01, 0xcc36, 0x21, 0 + .dw 0x2c03, 0xcc36, 0x2c0f, 0xcc36, 0x21, 0 + .dw 0x2c11, 0xcc36, 0x2c11, 0xcc36, 0x21, 0 + .dw 0x2c13, 0xcc36, 0x2c3f, 0xcc36, 0x21, 0 + .dw 0x2c41, 0xcc36, 0x2c41, 0xcc36, 0x21, 0 + .dw 0x2c43, 0xcc36, 0x2c4f, 0xcc36, 0x21, 0 + .dw 0x2c51, 0xcc36, 0x2c51, 0xcc36, 0x21, 0 + .dw 0x2c53, 0xcc36, 0x2c7f, 0xcc36, 0x21, 0 + .dw 0x2c81, 0xcc36, 0x2c81, 0xcc36, 0x21, 0 + .dw 0x2c83, 0xcc36, 0x2c8f, 0xcc36, 0x21, 0 + .dw 0x2c91, 0xcc36, 0x2c91, 0xcc36, 0x21, 0 + .dw 0x2c93, 0xcc36, 0x2cbf, 0xcc36, 0x21, 0 + .dw 0x2cc1, 0xcc36, 0x2cc1, 0xcc36, 0x21, 0 + .dw 0x2cc3, 0xcc36, 0x2ccf, 0xcc36, 0x21, 0 + .dw 0x2cd1, 0xcc36, 0x2cd1, 0xcc36, 0x21, 0 + .dw 0x2cd3, 0xcc36, 0x2cff, 0xcc36, 0x21, 0 + .dw 0x2d01, 0xcc36, 0x2d01, 0xcc36, 0x21, 0 + .dw 0x2d03, 0xcc36, 0x2d0f, 0xcc36, 0x21, 0 + .dw 0x2d11, 0xcc36, 0x2d11, 0xcc36, 0x21, 0 + .dw 0x2d13, 0xcc36, 0x2d3f, 0xcc36, 0x21, 0 + .dw 0x2d41, 0xcc36, 0x2d41, 0xcc36, 0x21, 0 + .dw 0x2d43, 0xcc36, 0x2d4f, 0xcc36, 0x21, 0 + .dw 0x2d51, 0xcc36, 0x2d51, 0xcc36, 0x21, 0 + .dw 0x2d53, 0xcc36, 0x2d7f, 0xcc36, 0x21, 0 + .dw 0x2d81, 0xcc36, 0x2d81, 0xcc36, 0x21, 0 + .dw 0x2d83, 0xcc36, 0x2d8f, 0xcc36, 0x21, 0 + .dw 0x2d91, 0xcc36, 0x2d91, 0xcc36, 0x21, 0 + .dw 0x2d93, 0xcc36, 0x2dbf, 0xcc36, 0x21, 0 + .dw 0x2dc1, 0xcc36, 0x2dc1, 0xcc36, 0x21, 0 + .dw 0x2dc3, 0xcc36, 0x2dcf, 0xcc36, 0x21, 0 + .dw 0x2dd1, 0xcc36, 0x2dd1, 0xcc36, 0x21, 0 + .dw 0x2dd3, 0xcc36, 0x2dff, 0xcc36, 0x21, 0 + .dw 0x2e01, 0xcc36, 0x2e01, 0xcc36, 0x21, 0 + .dw 0x2e03, 0xcc36, 0x2e0f, 0xcc36, 0x21, 0 + .dw 0x2e11, 0xcc36, 0x2e11, 0xcc36, 0x21, 0 + .dw 0x2e13, 0xcc36, 0x2e3f, 0xcc36, 0x21, 0 + .dw 0x2e41, 0xcc36, 0x2e41, 0xcc36, 0x21, 0 + .dw 0x2e43, 0xcc36, 0x2e4f, 0xcc36, 0x21, 0 + .dw 0x2e51, 0xcc36, 0x2e51, 0xcc36, 0x21, 0 + .dw 0x2e53, 0xcc36, 0x2e7f, 0xcc36, 0x21, 0 + .dw 0x2e81, 0xcc36, 0x2e81, 0xcc36, 0x21, 0 + .dw 0x2e83, 0xcc36, 0x2e8f, 0xcc36, 0x21, 0 + .dw 0x2e91, 0xcc36, 0x2e91, 0xcc36, 0x21, 0 + .dw 0x2e93, 0xcc36, 0x2ebf, 0xcc36, 0x21, 0 + .dw 0x2ec1, 0xcc36, 0x2ec1, 0xcc36, 0x21, 0 + .dw 0x2ec3, 0xcc36, 0x2ecf, 0xcc36, 0x21, 0 + .dw 0x2ed1, 0xcc36, 0x2ed1, 0xcc36, 0x21, 0 + .dw 0x2ed3, 0xcc36, 0x2eff, 0xcc36, 0x21, 0 + .dw 0x2f01, 0xcc36, 0x2f01, 0xcc36, 0x21, 0 + .dw 0x2f03, 0xcc36, 0x2f0f, 0xcc36, 0x21, 0 + .dw 0x2f11, 0xcc36, 0x2f11, 0xcc36, 0x21, 0 + .dw 0x2f13, 0xcc36, 0x2f3f, 0xcc36, 0x21, 0 + .dw 0x2f41, 0xcc36, 0x2f41, 0xcc36, 0x21, 0 + .dw 0x2f43, 0xcc36, 0x2f4f, 0xcc36, 0x21, 0 + .dw 0x2f51, 0xcc36, 0x2f51, 0xcc36, 0x21, 0 + .dw 0x2f53, 0xcc36, 0x2f7f, 0xcc36, 0x21, 0 + .dw 0x2f81, 0xcc36, 0x2f81, 0xcc36, 0x21, 0 + .dw 0x2f83, 0xcc36, 0x2f8f, 0xcc36, 0x21, 0 + .dw 0x2f91, 0xcc36, 0x2f91, 0xcc36, 0x21, 0 + .dw 0x2f93, 0xcc36, 0x2fbf, 0xcc36, 0x21, 0 + .dw 0x2fc1, 0xcc36, 0x2fc1, 0xcc36, 0x21, 0 + .dw 0x2fc3, 0xcc36, 0x2fcf, 0xcc36, 0x21, 0 + .dw 0x2fd1, 0xcc36, 0x2fd1, 0xcc36, 0x21, 0 + .dw 0x2fd3, 0xcc36, 0x3fff, 0xcc36, 0x21, 0 + .dw 0x4001, 0xcc36, 0x4001, 0xcc36, 0x21, 0 + .dw 0x4003, 0xcc36, 0x400f, 0xcc36, 0x21, 0 + .dw 0x4011, 0xcc36, 0x4011, 0xcc36, 0x21, 0 + .dw 0x4013, 0xcc36, 0x403f, 0xcc36, 0x21, 0 + .dw 0x4041, 0xcc36, 0x4041, 0xcc36, 0x21, 0 + .dw 0x4043, 0xcc36, 0x404f, 0xcc36, 0x21, 0 + .dw 0x4051, 0xcc36, 0x4051, 0xcc36, 0x21, 0 + .dw 0x4053, 0xcc36, 0x407f, 0xcc36, 0x21, 0 + .dw 0x4081, 0xcc36, 0x4081, 0xcc36, 0x21, 0 + .dw 0x4083, 0xcc36, 0x408f, 0xcc36, 0x21, 0 + .dw 0x4091, 0xcc36, 0x4091, 0xcc36, 0x21, 0 + .dw 0x4093, 0xcc36, 0x40bf, 0xcc36, 0x21, 0 + .dw 0x40c1, 0xcc36, 0x40c1, 0xcc36, 0x21, 0 + .dw 0x40c3, 0xcc36, 0x40cf, 0xcc36, 0x21, 0 + .dw 0x40d1, 0xcc36, 0x40d1, 0xcc36, 0x21, 0 + .dw 0x40d3, 0xcc36, 0x40ff, 0xcc36, 0x21, 0 + .dw 0x4101, 0xcc36, 0x4101, 0xcc36, 0x21, 0 + .dw 0x4103, 0xcc36, 0x410f, 0xcc36, 0x21, 0 + .dw 0x4111, 0xcc36, 0x4111, 0xcc36, 0x21, 0 + .dw 0x4113, 0xcc36, 0x413f, 0xcc36, 0x21, 0 + .dw 0x4141, 0xcc36, 0x4141, 0xcc36, 0x21, 0 + .dw 0x4143, 0xcc36, 0x414f, 0xcc36, 0x21, 0 + .dw 0x4151, 0xcc36, 0x4151, 0xcc36, 0x21, 0 + .dw 0x4153, 0xcc36, 0x417f, 0xcc36, 0x21, 0 + .dw 0x4181, 0xcc36, 0x4181, 0xcc36, 0x21, 0 + .dw 0x4183, 0xcc36, 0x418f, 0xcc36, 0x21, 0 + .dw 0x4191, 0xcc36, 0x4191, 0xcc36, 0x21, 0 + .dw 0x4193, 0xcc36, 0x41bf, 0xcc36, 0x21, 0 + .dw 0x41c1, 0xcc36, 0x41c1, 0xcc36, 0x21, 0 + .dw 0x41c3, 0xcc36, 0x41cf, 0xcc36, 0x21, 0 + .dw 0x41d1, 0xcc36, 0x41d1, 0xcc36, 0x21, 0 + .dw 0x41d3, 0xcc36, 0x41ff, 0xcc36, 0x21, 0 + .dw 0x4201, 0xcc36, 0x4201, 0xcc36, 0x21, 0 + .dw 0x4203, 0xcc36, 0x420f, 0xcc36, 0x21, 0 + .dw 0x4211, 0xcc36, 0x4211, 0xcc36, 0x21, 0 + .dw 0x4213, 0xcc36, 0x423f, 0xcc36, 0x21, 0 + .dw 0x4241, 0xcc36, 0x4241, 0xcc36, 0x21, 0 + .dw 0x4243, 0xcc36, 0x424f, 0xcc36, 0x21, 0 + .dw 0x4251, 0xcc36, 0x4251, 0xcc36, 0x21, 0 + .dw 0x4253, 0xcc36, 0x427f, 0xcc36, 0x21, 0 + .dw 0x4281, 0xcc36, 0x4281, 0xcc36, 0x21, 0 + .dw 0x4283, 0xcc36, 0x428f, 0xcc36, 0x21, 0 + .dw 0x4291, 0xcc36, 0x4291, 0xcc36, 0x21, 0 + .dw 0x4293, 0xcc36, 0x42bf, 0xcc36, 0x21, 0 + .dw 0x42c1, 0xcc36, 0x42c1, 0xcc36, 0x21, 0 + .dw 0x42c3, 0xcc36, 0x42cf, 0xcc36, 0x21, 0 + .dw 0x42d1, 0xcc36, 0x42d1, 0xcc36, 0x21, 0 + .dw 0x42d3, 0xcc36, 0x42ff, 0xcc36, 0x21, 0 + .dw 0x4301, 0xcc36, 0x4301, 0xcc36, 0x21, 0 + .dw 0x4303, 0xcc36, 0x430f, 0xcc36, 0x21, 0 + .dw 0x4311, 0xcc36, 0x4311, 0xcc36, 0x21, 0 + .dw 0x4313, 0xcc36, 0x433f, 0xcc36, 0x21, 0 + .dw 0x4341, 0xcc36, 0x4341, 0xcc36, 0x21, 0 + .dw 0x4343, 0xcc36, 0x434f, 0xcc36, 0x21, 0 + .dw 0x4351, 0xcc36, 0x4351, 0xcc36, 0x21, 0 + .dw 0x4353, 0xcc36, 0x437f, 0xcc36, 0x21, 0 + .dw 0x4381, 0xcc36, 0x4381, 0xcc36, 0x21, 0 + .dw 0x4383, 0xcc36, 0x438f, 0xcc36, 0x21, 0 + .dw 0x4391, 0xcc36, 0x4391, 0xcc36, 0x21, 0 + .dw 0x4393, 0xcc36, 0x43bf, 0xcc36, 0x21, 0 + .dw 0x43c1, 0xcc36, 0x43c1, 0xcc36, 0x21, 0 + .dw 0x43c3, 0xcc36, 0x43cf, 0xcc36, 0x21, 0 + .dw 0x43d1, 0xcc36, 0x43d1, 0xcc36, 0x21, 0 + .dw 0x43d3, 0xcc36, 0x43ff, 0xcc36, 0x21, 0 + .dw 0x4401, 0xcc36, 0x4401, 0xcc36, 0x21, 0 + .dw 0x4403, 0xcc36, 0x440f, 0xcc36, 0x21, 0 + .dw 0x4411, 0xcc36, 0x4411, 0xcc36, 0x21, 0 + .dw 0x4413, 0xcc36, 0x443f, 0xcc36, 0x21, 0 + .dw 0x4441, 0xcc36, 0x4441, 0xcc36, 0x21, 0 + .dw 0x4443, 0xcc36, 0x444f, 0xcc36, 0x21, 0 + .dw 0x4451, 0xcc36, 0x4451, 0xcc36, 0x21, 0 + .dw 0x4453, 0xcc36, 0x447f, 0xcc36, 0x21, 0 + .dw 0x4481, 0xcc36, 0x4481, 0xcc36, 0x21, 0 + .dw 0x4483, 0xcc36, 0x448f, 0xcc36, 0x21, 0 + .dw 0x4491, 0xcc36, 0x4491, 0xcc36, 0x21, 0 + .dw 0x4493, 0xcc36, 0x44bf, 0xcc36, 0x21, 0 + .dw 0x44c1, 0xcc36, 0x44c1, 0xcc36, 0x21, 0 + .dw 0x44c3, 0xcc36, 0x44cf, 0xcc36, 0x21, 0 + .dw 0x44d1, 0xcc36, 0x44d1, 0xcc36, 0x21, 0 + .dw 0x44d3, 0xcc36, 0x44ff, 0xcc36, 0x21, 0 + .dw 0x4501, 0xcc36, 0x4501, 0xcc36, 0x21, 0 + .dw 0x4503, 0xcc36, 0x450f, 0xcc36, 0x21, 0 + .dw 0x4511, 0xcc36, 0x4511, 0xcc36, 0x21, 0 + .dw 0x4513, 0xcc36, 0x453f, 0xcc36, 0x21, 0 + .dw 0x4541, 0xcc36, 0x4541, 0xcc36, 0x21, 0 + .dw 0x4543, 0xcc36, 0x454f, 0xcc36, 0x21, 0 + .dw 0x4551, 0xcc36, 0x4551, 0xcc36, 0x21, 0 + .dw 0x4553, 0xcc36, 0x457f, 0xcc36, 0x21, 0 + .dw 0x4581, 0xcc36, 0x4581, 0xcc36, 0x21, 0 + .dw 0x4583, 0xcc36, 0x458f, 0xcc36, 0x21, 0 + .dw 0x4591, 0xcc36, 0x4591, 0xcc36, 0x21, 0 + .dw 0x4593, 0xcc36, 0x45bf, 0xcc36, 0x21, 0 + .dw 0x45c1, 0xcc36, 0x45c1, 0xcc36, 0x21, 0 + .dw 0x45c3, 0xcc36, 0x45cf, 0xcc36, 0x21, 0 + .dw 0x45d1, 0xcc36, 0x45d1, 0xcc36, 0x21, 0 + .dw 0x45d3, 0xcc36, 0x45ff, 0xcc36, 0x21, 0 + .dw 0x4601, 0xcc36, 0x4601, 0xcc36, 0x21, 0 + .dw 0x4603, 0xcc36, 0x460f, 0xcc36, 0x21, 0 + .dw 0x4611, 0xcc36, 0x4611, 0xcc36, 0x21, 0 + .dw 0x4613, 0xcc36, 0x463f, 0xcc36, 0x21, 0 + .dw 0x4641, 0xcc36, 0x4641, 0xcc36, 0x21, 0 + .dw 0x4643, 0xcc36, 0x464f, 0xcc36, 0x21, 0 + .dw 0x4651, 0xcc36, 0x4651, 0xcc36, 0x21, 0 + .dw 0x4653, 0xcc36, 0x467f, 0xcc36, 0x21, 0 + .dw 0x4681, 0xcc36, 0x4681, 0xcc36, 0x21, 0 + .dw 0x4683, 0xcc36, 0x468f, 0xcc36, 0x21, 0 + .dw 0x4691, 0xcc36, 0x4691, 0xcc36, 0x21, 0 + .dw 0x4693, 0xcc36, 0x46bf, 0xcc36, 0x21, 0 + .dw 0x46c1, 0xcc36, 0x46c1, 0xcc36, 0x21, 0 + .dw 0x46c3, 0xcc36, 0x46cf, 0xcc36, 0x21, 0 + .dw 0x46d1, 0xcc36, 0x46d1, 0xcc36, 0x21, 0 + .dw 0x46d3, 0xcc36, 0x46ff, 0xcc36, 0x21, 0 + .dw 0x4701, 0xcc36, 0x4701, 0xcc36, 0x21, 0 + .dw 0x4703, 0xcc36, 0x470f, 0xcc36, 0x21, 0 + .dw 0x4711, 0xcc36, 0x4711, 0xcc36, 0x21, 0 + .dw 0x4713, 0xcc36, 0x473f, 0xcc36, 0x21, 0 + .dw 0x4741, 0xcc36, 0x4741, 0xcc36, 0x21, 0 + .dw 0x4743, 0xcc36, 0x474f, 0xcc36, 0x21, 0 + .dw 0x4751, 0xcc36, 0x4751, 0xcc36, 0x21, 0 + .dw 0x4753, 0xcc36, 0x477f, 0xcc36, 0x21, 0 + .dw 0x4781, 0xcc36, 0x4781, 0xcc36, 0x21, 0 + .dw 0x4783, 0xcc36, 0x478f, 0xcc36, 0x21, 0 + .dw 0x4791, 0xcc36, 0x4791, 0xcc36, 0x21, 0 + .dw 0x4793, 0xcc36, 0x47bf, 0xcc36, 0x21, 0 + .dw 0x47c1, 0xcc36, 0x47c1, 0xcc36, 0x21, 0 + .dw 0x47c3, 0xcc36, 0x47cf, 0xcc36, 0x21, 0 + .dw 0x47d1, 0xcc36, 0x47d1, 0xcc36, 0x21, 0 + .dw 0x47d3, 0xcc36, 0x47ff, 0xcc36, 0x21, 0 + .dw 0x4801, 0xcc36, 0x4801, 0xcc36, 0x21, 0 + .dw 0x4803, 0xcc36, 0x480f, 0xcc36, 0x21, 0 + .dw 0x4811, 0xcc36, 0x4811, 0xcc36, 0x21, 0 + .dw 0x4813, 0xcc36, 0x483f, 0xcc36, 0x21, 0 + .dw 0x4841, 0xcc36, 0x4841, 0xcc36, 0x21, 0 + .dw 0x4843, 0xcc36, 0x484f, 0xcc36, 0x21, 0 + .dw 0x4851, 0xcc36, 0x4851, 0xcc36, 0x21, 0 + .dw 0x4853, 0xcc36, 0x487f, 0xcc36, 0x21, 0 + .dw 0x4881, 0xcc36, 0x4881, 0xcc36, 0x21, 0 + .dw 0x4883, 0xcc36, 0x488f, 0xcc36, 0x21, 0 + .dw 0x4891, 0xcc36, 0x4891, 0xcc36, 0x21, 0 + .dw 0x4893, 0xcc36, 0x48bf, 0xcc36, 0x21, 0 + .dw 0x48c1, 0xcc36, 0x48c1, 0xcc36, 0x21, 0 + .dw 0x48c3, 0xcc36, 0x48cf, 0xcc36, 0x21, 0 + .dw 0x48d1, 0xcc36, 0x48d1, 0xcc36, 0x21, 0 + .dw 0x48d3, 0xcc36, 0x48ff, 0xcc36, 0x21, 0 + .dw 0x4901, 0xcc36, 0x4901, 0xcc36, 0x21, 0 + .dw 0x4903, 0xcc36, 0x490f, 0xcc36, 0x21, 0 + .dw 0x4911, 0xcc36, 0x4911, 0xcc36, 0x21, 0 + .dw 0x4913, 0xcc36, 0x493f, 0xcc36, 0x21, 0 + .dw 0x4941, 0xcc36, 0x4941, 0xcc36, 0x21, 0 + .dw 0x4943, 0xcc36, 0x494f, 0xcc36, 0x21, 0 + .dw 0x4951, 0xcc36, 0x4951, 0xcc36, 0x21, 0 + .dw 0x4953, 0xcc36, 0x497f, 0xcc36, 0x21, 0 + .dw 0x4981, 0xcc36, 0x4981, 0xcc36, 0x21, 0 + .dw 0x4983, 0xcc36, 0x498f, 0xcc36, 0x21, 0 + .dw 0x4991, 0xcc36, 0x4991, 0xcc36, 0x21, 0 + .dw 0x4993, 0xcc36, 0x49bf, 0xcc36, 0x21, 0 + .dw 0x49c1, 0xcc36, 0x49c1, 0xcc36, 0x21, 0 + .dw 0x49c3, 0xcc36, 0x49cf, 0xcc36, 0x21, 0 + .dw 0x49d1, 0xcc36, 0x49d1, 0xcc36, 0x21, 0 + .dw 0x49d3, 0xcc36, 0x49ff, 0xcc36, 0x21, 0 + .dw 0x4a01, 0xcc36, 0x4a01, 0xcc36, 0x21, 0 + .dw 0x4a03, 0xcc36, 0x4a0f, 0xcc36, 0x21, 0 + .dw 0x4a11, 0xcc36, 0x4a11, 0xcc36, 0x21, 0 + .dw 0x4a13, 0xcc36, 0x4a3f, 0xcc36, 0x21, 0 + .dw 0x4a41, 0xcc36, 0x4a41, 0xcc36, 0x21, 0 + .dw 0x4a43, 0xcc36, 0x4a4f, 0xcc36, 0x21, 0 + .dw 0x4a51, 0xcc36, 0x4a51, 0xcc36, 0x21, 0 + .dw 0x4a53, 0xcc36, 0x4a7f, 0xcc36, 0x21, 0 + .dw 0x4a81, 0xcc36, 0x4a81, 0xcc36, 0x21, 0 + .dw 0x4a83, 0xcc36, 0x4a8f, 0xcc36, 0x21, 0 + .dw 0x4a91, 0xcc36, 0x4a91, 0xcc36, 0x21, 0 + .dw 0x4a93, 0xcc36, 0x4abf, 0xcc36, 0x21, 0 + .dw 0x4ac1, 0xcc36, 0x4ac1, 0xcc36, 0x21, 0 + .dw 0x4ac3, 0xcc36, 0x4acf, 0xcc36, 0x21, 0 + .dw 0x4ad1, 0xcc36, 0x4ad1, 0xcc36, 0x21, 0 + .dw 0x4ad3, 0xcc36, 0x4aff, 0xcc36, 0x21, 0 + .dw 0x4b01, 0xcc36, 0x4b01, 0xcc36, 0x21, 0 + .dw 0x4b03, 0xcc36, 0x4b0f, 0xcc36, 0x21, 0 + .dw 0x4b11, 0xcc36, 0x4b11, 0xcc36, 0x21, 0 + .dw 0x4b13, 0xcc36, 0x4b3f, 0xcc36, 0x21, 0 + .dw 0x4b41, 0xcc36, 0x4b41, 0xcc36, 0x21, 0 + .dw 0x4b43, 0xcc36, 0x4b4f, 0xcc36, 0x21, 0 + .dw 0x4b51, 0xcc36, 0x4b51, 0xcc36, 0x21, 0 + .dw 0x4b53, 0xcc36, 0x4b7f, 0xcc36, 0x21, 0 + .dw 0x4b81, 0xcc36, 0x4b81, 0xcc36, 0x21, 0 + .dw 0x4b83, 0xcc36, 0x4b8f, 0xcc36, 0x21, 0 + .dw 0x4b91, 0xcc36, 0x4b91, 0xcc36, 0x21, 0 + .dw 0x4b93, 0xcc36, 0x4bbf, 0xcc36, 0x21, 0 + .dw 0x4bc1, 0xcc36, 0x4bc1, 0xcc36, 0x21, 0 + .dw 0x4bc3, 0xcc36, 0x4bcf, 0xcc36, 0x21, 0 + .dw 0x4bd1, 0xcc36, 0x4bd1, 0xcc36, 0x21, 0 + .dw 0x4bd3, 0xcc36, 0x4bff, 0xcc36, 0x21, 0 + .dw 0x4c01, 0xcc36, 0x4c01, 0xcc36, 0x21, 0 + .dw 0x4c03, 0xcc36, 0x4c0f, 0xcc36, 0x21, 0 + .dw 0x4c11, 0xcc36, 0x4c11, 0xcc36, 0x21, 0 + .dw 0x4c13, 0xcc36, 0x4c3f, 0xcc36, 0x21, 0 + .dw 0x4c41, 0xcc36, 0x4c41, 0xcc36, 0x21, 0 + .dw 0x4c43, 0xcc36, 0x4c4f, 0xcc36, 0x21, 0 + .dw 0x4c51, 0xcc36, 0x4c51, 0xcc36, 0x21, 0 + .dw 0x4c53, 0xcc36, 0x4c7f, 0xcc36, 0x21, 0 + .dw 0x4c81, 0xcc36, 0x4c81, 0xcc36, 0x21, 0 + .dw 0x4c83, 0xcc36, 0x4c8f, 0xcc36, 0x21, 0 + .dw 0x4c91, 0xcc36, 0x4c91, 0xcc36, 0x21, 0 + .dw 0x4c93, 0xcc36, 0x4cbf, 0xcc36, 0x21, 0 + .dw 0x4cc1, 0xcc36, 0x4cc1, 0xcc36, 0x21, 0 + .dw 0x4cc3, 0xcc36, 0x4ccf, 0xcc36, 0x21, 0 + .dw 0x4cd1, 0xcc36, 0x4cd1, 0xcc36, 0x21, 0 + .dw 0x4cd3, 0xcc36, 0x4cff, 0xcc36, 0x21, 0 + .dw 0x4d01, 0xcc36, 0x4d01, 0xcc36, 0x21, 0 + .dw 0x4d03, 0xcc36, 0x4d0f, 0xcc36, 0x21, 0 + .dw 0x4d11, 0xcc36, 0x4d11, 0xcc36, 0x21, 0 + .dw 0x4d13, 0xcc36, 0x4d3f, 0xcc36, 0x21, 0 + .dw 0x4d41, 0xcc36, 0x4d41, 0xcc36, 0x21, 0 + .dw 0x4d43, 0xcc36, 0x4d4f, 0xcc36, 0x21, 0 + .dw 0x4d51, 0xcc36, 0x4d51, 0xcc36, 0x21, 0 + .dw 0x4d53, 0xcc36, 0x4d7f, 0xcc36, 0x21, 0 + .dw 0x4d81, 0xcc36, 0x4d81, 0xcc36, 0x21, 0 + .dw 0x4d83, 0xcc36, 0x4d8f, 0xcc36, 0x21, 0 + .dw 0x4d91, 0xcc36, 0x4d91, 0xcc36, 0x21, 0 + .dw 0x4d93, 0xcc36, 0x4dbf, 0xcc36, 0x21, 0 + .dw 0x4dc1, 0xcc36, 0x4dc1, 0xcc36, 0x21, 0 + .dw 0x4dc3, 0xcc36, 0x4dcf, 0xcc36, 0x21, 0 + .dw 0x4dd1, 0xcc36, 0x4dd1, 0xcc36, 0x21, 0 + .dw 0x4dd3, 0xcc36, 0x4dff, 0xcc36, 0x21, 0 + .dw 0x4e01, 0xcc36, 0x4e01, 0xcc36, 0x21, 0 + .dw 0x4e03, 0xcc36, 0x4e0f, 0xcc36, 0x21, 0 + .dw 0x4e11, 0xcc36, 0x4e11, 0xcc36, 0x21, 0 + .dw 0x4e13, 0xcc36, 0x4e3f, 0xcc36, 0x21, 0 + .dw 0x4e41, 0xcc36, 0x4e41, 0xcc36, 0x21, 0 + .dw 0x4e43, 0xcc36, 0x4e4f, 0xcc36, 0x21, 0 + .dw 0x4e51, 0xcc36, 0x4e51, 0xcc36, 0x21, 0 + .dw 0x4e53, 0xcc36, 0x4e7f, 0xcc36, 0x21, 0 + .dw 0x4e81, 0xcc36, 0x4e81, 0xcc36, 0x21, 0 + .dw 0x4e83, 0xcc36, 0x4e8f, 0xcc36, 0x21, 0 + .dw 0x4e91, 0xcc36, 0x4e91, 0xcc36, 0x21, 0 + .dw 0x4e93, 0xcc36, 0x4ebf, 0xcc36, 0x21, 0 + .dw 0x4ec1, 0xcc36, 0x4ec1, 0xcc36, 0x21, 0 + .dw 0x4ec3, 0xcc36, 0x4ecf, 0xcc36, 0x21, 0 + .dw 0x4ed1, 0xcc36, 0x4ed1, 0xcc36, 0x21, 0 + .dw 0x4ed3, 0xcc36, 0x4eff, 0xcc36, 0x21, 0 + .dw 0x4f01, 0xcc36, 0x4f01, 0xcc36, 0x21, 0 + .dw 0x4f03, 0xcc36, 0x4f0f, 0xcc36, 0x21, 0 + .dw 0x4f11, 0xcc36, 0x4f11, 0xcc36, 0x21, 0 + .dw 0x4f13, 0xcc36, 0x4f3f, 0xcc36, 0x21, 0 + .dw 0x4f41, 0xcc36, 0x4f41, 0xcc36, 0x21, 0 + .dw 0x4f43, 0xcc36, 0x4f4f, 0xcc36, 0x21, 0 + .dw 0x4f51, 0xcc36, 0x4f51, 0xcc36, 0x21, 0 + .dw 0x4f53, 0xcc36, 0x4f7f, 0xcc36, 0x21, 0 + .dw 0x4f81, 0xcc36, 0x4f81, 0xcc36, 0x21, 0 + .dw 0x4f83, 0xcc36, 0x4f8f, 0xcc36, 0x21, 0 + .dw 0x4f91, 0xcc36, 0x4f91, 0xcc36, 0x21, 0 + .dw 0x4f93, 0xcc36, 0x4fbf, 0xcc36, 0x21, 0 + .dw 0x4fc1, 0xcc36, 0x4fc1, 0xcc36, 0x21, 0 + .dw 0x4fc3, 0xcc36, 0x4fcf, 0xcc36, 0x21, 0 + .dw 0x4fd1, 0xcc36, 0x4fd1, 0xcc36, 0x21, 0 + .dw 0x4fd3, 0xcc36, 0x5fff, 0xcc36, 0x21, 0 + .dw 0x6001, 0xcc36, 0x6001, 0xcc36, 0x21, 0 + .dw 0x6003, 0xcc36, 0x600f, 0xcc36, 0x21, 0 + .dw 0x6011, 0xcc36, 0x6011, 0xcc36, 0x21, 0 + .dw 0x6013, 0xcc36, 0x603f, 0xcc36, 0x21, 0 + .dw 0x6041, 0xcc36, 0x6041, 0xcc36, 0x21, 0 + .dw 0x6043, 0xcc36, 0x604f, 0xcc36, 0x21, 0 + .dw 0x6051, 0xcc36, 0x6051, 0xcc36, 0x21, 0 + .dw 0x6053, 0xcc36, 0x607f, 0xcc36, 0x21, 0 + .dw 0x6081, 0xcc36, 0x6081, 0xcc36, 0x21, 0 + .dw 0x6083, 0xcc36, 0x608f, 0xcc36, 0x21, 0 + .dw 0x6091, 0xcc36, 0x6091, 0xcc36, 0x21, 0 + .dw 0x6093, 0xcc36, 0x60bf, 0xcc36, 0x21, 0 + .dw 0x60c1, 0xcc36, 0x60c1, 0xcc36, 0x21, 0 + .dw 0x60c3, 0xcc36, 0x60cf, 0xcc36, 0x21, 0 + .dw 0x60d1, 0xcc36, 0x60d1, 0xcc36, 0x21, 0 + .dw 0x60d3, 0xcc36, 0x60ff, 0xcc36, 0x21, 0 + .dw 0x6101, 0xcc36, 0x6101, 0xcc36, 0x21, 0 + .dw 0x6103, 0xcc36, 0x610f, 0xcc36, 0x21, 0 + .dw 0x6111, 0xcc36, 0x6111, 0xcc36, 0x21, 0 + .dw 0x6113, 0xcc36, 0x613f, 0xcc36, 0x21, 0 + .dw 0x6141, 0xcc36, 0x6141, 0xcc36, 0x21, 0 + .dw 0x6143, 0xcc36, 0x614f, 0xcc36, 0x21, 0 + .dw 0x6151, 0xcc36, 0x6151, 0xcc36, 0x21, 0 + .dw 0x6153, 0xcc36, 0x617f, 0xcc36, 0x21, 0 + .dw 0x6181, 0xcc36, 0x6181, 0xcc36, 0x21, 0 + .dw 0x6183, 0xcc36, 0x618f, 0xcc36, 0x21, 0 + .dw 0x6191, 0xcc36, 0x6191, 0xcc36, 0x21, 0 + .dw 0x6193, 0xcc36, 0x61bf, 0xcc36, 0x21, 0 + .dw 0x61c1, 0xcc36, 0x61c1, 0xcc36, 0x21, 0 + .dw 0x61c3, 0xcc36, 0x61cf, 0xcc36, 0x21, 0 + .dw 0x61d1, 0xcc36, 0x61d1, 0xcc36, 0x21, 0 + .dw 0x61d3, 0xcc36, 0x61ff, 0xcc36, 0x21, 0 + .dw 0x6201, 0xcc36, 0x6201, 0xcc36, 0x21, 0 + .dw 0x6203, 0xcc36, 0x620f, 0xcc36, 0x21, 0 + .dw 0x6211, 0xcc36, 0x6211, 0xcc36, 0x21, 0 + .dw 0x6213, 0xcc36, 0x623f, 0xcc36, 0x21, 0 + .dw 0x6241, 0xcc36, 0x6241, 0xcc36, 0x21, 0 + .dw 0x6243, 0xcc36, 0x624f, 0xcc36, 0x21, 0 + .dw 0x6251, 0xcc36, 0x6251, 0xcc36, 0x21, 0 + .dw 0x6253, 0xcc36, 0x627f, 0xcc36, 0x21, 0 + .dw 0x6281, 0xcc36, 0x6281, 0xcc36, 0x21, 0 + .dw 0x6283, 0xcc36, 0x628f, 0xcc36, 0x21, 0 + .dw 0x6291, 0xcc36, 0x6291, 0xcc36, 0x21, 0 + .dw 0x6293, 0xcc36, 0x62bf, 0xcc36, 0x21, 0 + .dw 0x62c1, 0xcc36, 0x62c1, 0xcc36, 0x21, 0 + .dw 0x62c3, 0xcc36, 0x62cf, 0xcc36, 0x21, 0 + .dw 0x62d1, 0xcc36, 0x62d1, 0xcc36, 0x21, 0 + .dw 0x62d3, 0xcc36, 0x62ff, 0xcc36, 0x21, 0 + .dw 0x6301, 0xcc36, 0x6301, 0xcc36, 0x21, 0 + .dw 0x6303, 0xcc36, 0x630f, 0xcc36, 0x21, 0 + .dw 0x6311, 0xcc36, 0x6311, 0xcc36, 0x21, 0 + .dw 0x6313, 0xcc36, 0x633f, 0xcc36, 0x21, 0 + .dw 0x6341, 0xcc36, 0x6341, 0xcc36, 0x21, 0 + .dw 0x6343, 0xcc36, 0x634f, 0xcc36, 0x21, 0 + .dw 0x6351, 0xcc36, 0x6351, 0xcc36, 0x21, 0 + .dw 0x6353, 0xcc36, 0x637f, 0xcc36, 0x21, 0 + .dw 0x6381, 0xcc36, 0x6381, 0xcc36, 0x21, 0 + .dw 0x6383, 0xcc36, 0x638f, 0xcc36, 0x21, 0 + .dw 0x6391, 0xcc36, 0x6391, 0xcc36, 0x21, 0 + .dw 0x6393, 0xcc36, 0x63bf, 0xcc36, 0x21, 0 + .dw 0x63c1, 0xcc36, 0x63c1, 0xcc36, 0x21, 0 + .dw 0x63c3, 0xcc36, 0x63cf, 0xcc36, 0x21, 0 + .dw 0x63d1, 0xcc36, 0x63d1, 0xcc36, 0x21, 0 + .dw 0x63d3, 0xcc36, 0x63ff, 0xcc36, 0x21, 0 + .dw 0x6401, 0xcc36, 0x6401, 0xcc36, 0x21, 0 + .dw 0x6403, 0xcc36, 0x640f, 0xcc36, 0x21, 0 + .dw 0x6411, 0xcc36, 0x6411, 0xcc36, 0x21, 0 + .dw 0x6413, 0xcc36, 0x643f, 0xcc36, 0x21, 0 + .dw 0x6441, 0xcc36, 0x6441, 0xcc36, 0x21, 0 + .dw 0x6443, 0xcc36, 0x644f, 0xcc36, 0x21, 0 + .dw 0x6451, 0xcc36, 0x6451, 0xcc36, 0x21, 0 + .dw 0x6453, 0xcc36, 0x647f, 0xcc36, 0x21, 0 + .dw 0x6481, 0xcc36, 0x6481, 0xcc36, 0x21, 0 + .dw 0x6483, 0xcc36, 0x648f, 0xcc36, 0x21, 0 + .dw 0x6491, 0xcc36, 0x6491, 0xcc36, 0x21, 0 + .dw 0x6493, 0xcc36, 0x64bf, 0xcc36, 0x21, 0 + .dw 0x64c1, 0xcc36, 0x64c1, 0xcc36, 0x21, 0 + .dw 0x64c3, 0xcc36, 0x64cf, 0xcc36, 0x21, 0 + .dw 0x64d1, 0xcc36, 0x64d1, 0xcc36, 0x21, 0 + .dw 0x64d3, 0xcc36, 0x64ff, 0xcc36, 0x21, 0 + .dw 0x6501, 0xcc36, 0x6501, 0xcc36, 0x21, 0 + .dw 0x6503, 0xcc36, 0x650f, 0xcc36, 0x21, 0 + .dw 0x6511, 0xcc36, 0x6511, 0xcc36, 0x21, 0 + .dw 0x6513, 0xcc36, 0x653f, 0xcc36, 0x21, 0 + .dw 0x6541, 0xcc36, 0x6541, 0xcc36, 0x21, 0 + .dw 0x6543, 0xcc36, 0x654f, 0xcc36, 0x21, 0 + .dw 0x6551, 0xcc36, 0x6551, 0xcc36, 0x21, 0 + .dw 0x6553, 0xcc36, 0x657f, 0xcc36, 0x21, 0 + .dw 0x6581, 0xcc36, 0x6581, 0xcc36, 0x21, 0 + .dw 0x6583, 0xcc36, 0x658f, 0xcc36, 0x21, 0 + .dw 0x6591, 0xcc36, 0x6591, 0xcc36, 0x21, 0 + .dw 0x6593, 0xcc36, 0x65bf, 0xcc36, 0x21, 0 + .dw 0x65c1, 0xcc36, 0x65c1, 0xcc36, 0x21, 0 + .dw 0x65c3, 0xcc36, 0x65cf, 0xcc36, 0x21, 0 + .dw 0x65d1, 0xcc36, 0x65d1, 0xcc36, 0x21, 0 + .dw 0x65d3, 0xcc36, 0x65ff, 0xcc36, 0x21, 0 + .dw 0x6601, 0xcc36, 0x6601, 0xcc36, 0x21, 0 + .dw 0x6603, 0xcc36, 0x660f, 0xcc36, 0x21, 0 + .dw 0x6611, 0xcc36, 0x6611, 0xcc36, 0x21, 0 + .dw 0x6613, 0xcc36, 0x663f, 0xcc36, 0x21, 0 + .dw 0x6641, 0xcc36, 0x6641, 0xcc36, 0x21, 0 + .dw 0x6643, 0xcc36, 0x664f, 0xcc36, 0x21, 0 + .dw 0x6651, 0xcc36, 0x6651, 0xcc36, 0x21, 0 + .dw 0x6653, 0xcc36, 0x667f, 0xcc36, 0x21, 0 + .dw 0x6681, 0xcc36, 0x6681, 0xcc36, 0x21, 0 + .dw 0x6683, 0xcc36, 0x668f, 0xcc36, 0x21, 0 + .dw 0x6691, 0xcc36, 0x6691, 0xcc36, 0x21, 0 + .dw 0x6693, 0xcc36, 0x66bf, 0xcc36, 0x21, 0 + .dw 0x66c1, 0xcc36, 0x66c1, 0xcc36, 0x21, 0 + .dw 0x66c3, 0xcc36, 0x66cf, 0xcc36, 0x21, 0 + .dw 0x66d1, 0xcc36, 0x66d1, 0xcc36, 0x21, 0 + .dw 0x66d3, 0xcc36, 0x66ff, 0xcc36, 0x21, 0 + .dw 0x6701, 0xcc36, 0x6701, 0xcc36, 0x21, 0 + .dw 0x6703, 0xcc36, 0x670f, 0xcc36, 0x21, 0 + .dw 0x6711, 0xcc36, 0x6711, 0xcc36, 0x21, 0 + .dw 0x6713, 0xcc36, 0x673f, 0xcc36, 0x21, 0 + .dw 0x6741, 0xcc36, 0x6741, 0xcc36, 0x21, 0 + .dw 0x6743, 0xcc36, 0x674f, 0xcc36, 0x21, 0 + .dw 0x6751, 0xcc36, 0x6751, 0xcc36, 0x21, 0 + .dw 0x6753, 0xcc36, 0x677f, 0xcc36, 0x21, 0 + .dw 0x6781, 0xcc36, 0x6781, 0xcc36, 0x21, 0 + .dw 0x6783, 0xcc36, 0x678f, 0xcc36, 0x21, 0 + .dw 0x6791, 0xcc36, 0x6791, 0xcc36, 0x21, 0 + .dw 0x6793, 0xcc36, 0x67bf, 0xcc36, 0x21, 0 + .dw 0x67c1, 0xcc36, 0x67c1, 0xcc36, 0x21, 0 + .dw 0x67c3, 0xcc36, 0x67cf, 0xcc36, 0x21, 0 + .dw 0x67d1, 0xcc36, 0x67d1, 0xcc36, 0x21, 0 + .dw 0x67d3, 0xcc36, 0x67ff, 0xcc36, 0x21, 0 + .dw 0x6801, 0xcc36, 0x6801, 0xcc36, 0x21, 0 + .dw 0x6803, 0xcc36, 0x680f, 0xcc36, 0x21, 0 + .dw 0x6811, 0xcc36, 0x6811, 0xcc36, 0x21, 0 + .dw 0x6813, 0xcc36, 0x683f, 0xcc36, 0x21, 0 + .dw 0x6841, 0xcc36, 0x6841, 0xcc36, 0x21, 0 + .dw 0x6843, 0xcc36, 0x684f, 0xcc36, 0x21, 0 + .dw 0x6851, 0xcc36, 0x6851, 0xcc36, 0x21, 0 + .dw 0x6853, 0xcc36, 0x687f, 0xcc36, 0x21, 0 + .dw 0x6881, 0xcc36, 0x6881, 0xcc36, 0x21, 0 + .dw 0x6883, 0xcc36, 0x688f, 0xcc36, 0x21, 0 + .dw 0x6891, 0xcc36, 0x6891, 0xcc36, 0x21, 0 + .dw 0x6893, 0xcc36, 0x68bf, 0xcc36, 0x21, 0 + .dw 0x68c1, 0xcc36, 0x68c1, 0xcc36, 0x21, 0 + .dw 0x68c3, 0xcc36, 0x68cf, 0xcc36, 0x21, 0 + .dw 0x68d1, 0xcc36, 0x68d1, 0xcc36, 0x21, 0 + .dw 0x68d3, 0xcc36, 0x68ff, 0xcc36, 0x21, 0 + .dw 0x6901, 0xcc36, 0x6901, 0xcc36, 0x21, 0 + .dw 0x6903, 0xcc36, 0x690f, 0xcc36, 0x21, 0 + .dw 0x6911, 0xcc36, 0x6911, 0xcc36, 0x21, 0 + .dw 0x6913, 0xcc36, 0x693f, 0xcc36, 0x21, 0 + .dw 0x6941, 0xcc36, 0x6941, 0xcc36, 0x21, 0 + .dw 0x6943, 0xcc36, 0x694f, 0xcc36, 0x21, 0 + .dw 0x6951, 0xcc36, 0x6951, 0xcc36, 0x21, 0 + .dw 0x6953, 0xcc36, 0x697f, 0xcc36, 0x21, 0 + .dw 0x6981, 0xcc36, 0x6981, 0xcc36, 0x21, 0 + .dw 0x6983, 0xcc36, 0x698f, 0xcc36, 0x21, 0 + .dw 0x6991, 0xcc36, 0x6991, 0xcc36, 0x21, 0 + .dw 0x6993, 0xcc36, 0x69bf, 0xcc36, 0x21, 0 + .dw 0x69c1, 0xcc36, 0x69c1, 0xcc36, 0x21, 0 + .dw 0x69c3, 0xcc36, 0x69cf, 0xcc36, 0x21, 0 + .dw 0x69d1, 0xcc36, 0x69d1, 0xcc36, 0x21, 0 + .dw 0x69d3, 0xcc36, 0x69ff, 0xcc36, 0x21, 0 + .dw 0x6a01, 0xcc36, 0x6a01, 0xcc36, 0x21, 0 + .dw 0x6a03, 0xcc36, 0x6a0f, 0xcc36, 0x21, 0 + .dw 0x6a11, 0xcc36, 0x6a11, 0xcc36, 0x21, 0 + .dw 0x6a13, 0xcc36, 0x6a3f, 0xcc36, 0x21, 0 + .dw 0x6a41, 0xcc36, 0x6a41, 0xcc36, 0x21, 0 + .dw 0x6a43, 0xcc36, 0x6a4f, 0xcc36, 0x21, 0 + .dw 0x6a51, 0xcc36, 0x6a51, 0xcc36, 0x21, 0 + .dw 0x6a53, 0xcc36, 0x6a7f, 0xcc36, 0x21, 0 + .dw 0x6a81, 0xcc36, 0x6a81, 0xcc36, 0x21, 0 + .dw 0x6a83, 0xcc36, 0x6a8f, 0xcc36, 0x21, 0 + .dw 0x6a91, 0xcc36, 0x6a91, 0xcc36, 0x21, 0 + .dw 0x6a93, 0xcc36, 0x6abf, 0xcc36, 0x21, 0 + .dw 0x6ac1, 0xcc36, 0x6ac1, 0xcc36, 0x21, 0 + .dw 0x6ac3, 0xcc36, 0x6acf, 0xcc36, 0x21, 0 + .dw 0x6ad1, 0xcc36, 0x6ad1, 0xcc36, 0x21, 0 + .dw 0x6ad3, 0xcc36, 0x6aff, 0xcc36, 0x21, 0 + .dw 0x6b01, 0xcc36, 0x6b01, 0xcc36, 0x21, 0 + .dw 0x6b03, 0xcc36, 0x6b0f, 0xcc36, 0x21, 0 + .dw 0x6b11, 0xcc36, 0x6b11, 0xcc36, 0x21, 0 + .dw 0x6b13, 0xcc36, 0x6b3f, 0xcc36, 0x21, 0 + .dw 0x6b41, 0xcc36, 0x6b41, 0xcc36, 0x21, 0 + .dw 0x6b43, 0xcc36, 0x6b4f, 0xcc36, 0x21, 0 + .dw 0x6b51, 0xcc36, 0x6b51, 0xcc36, 0x21, 0 + .dw 0x6b53, 0xcc36, 0x6b7f, 0xcc36, 0x21, 0 + .dw 0x6b81, 0xcc36, 0x6b81, 0xcc36, 0x21, 0 + .dw 0x6b83, 0xcc36, 0x6b8f, 0xcc36, 0x21, 0 + .dw 0x6b91, 0xcc36, 0x6b91, 0xcc36, 0x21, 0 + .dw 0x6b93, 0xcc36, 0x6bbf, 0xcc36, 0x21, 0 + .dw 0x6bc1, 0xcc36, 0x6bc1, 0xcc36, 0x21, 0 + .dw 0x6bc3, 0xcc36, 0x6bcf, 0xcc36, 0x21, 0 + .dw 0x6bd1, 0xcc36, 0x6bd1, 0xcc36, 0x21, 0 + .dw 0x6bd3, 0xcc36, 0x6bff, 0xcc36, 0x21, 0 + .dw 0x6c01, 0xcc36, 0x6c01, 0xcc36, 0x21, 0 + .dw 0x6c03, 0xcc36, 0x6c0f, 0xcc36, 0x21, 0 + .dw 0x6c11, 0xcc36, 0x6c11, 0xcc36, 0x21, 0 + .dw 0x6c13, 0xcc36, 0x6c3f, 0xcc36, 0x21, 0 + .dw 0x6c41, 0xcc36, 0x6c41, 0xcc36, 0x21, 0 + .dw 0x6c43, 0xcc36, 0x6c4f, 0xcc36, 0x21, 0 + .dw 0x6c51, 0xcc36, 0x6c51, 0xcc36, 0x21, 0 + .dw 0x6c53, 0xcc36, 0x6c7f, 0xcc36, 0x21, 0 + .dw 0x6c81, 0xcc36, 0x6c81, 0xcc36, 0x21, 0 + .dw 0x6c83, 0xcc36, 0x6c8f, 0xcc36, 0x21, 0 + .dw 0x6c91, 0xcc36, 0x6c91, 0xcc36, 0x21, 0 + .dw 0x6c93, 0xcc36, 0x6cbf, 0xcc36, 0x21, 0 + .dw 0x6cc1, 0xcc36, 0x6cc1, 0xcc36, 0x21, 0 + .dw 0x6cc3, 0xcc36, 0x6ccf, 0xcc36, 0x21, 0 + .dw 0x6cd1, 0xcc36, 0x6cd1, 0xcc36, 0x21, 0 + .dw 0x6cd3, 0xcc36, 0x6cff, 0xcc36, 0x21, 0 + .dw 0x6d01, 0xcc36, 0x6d01, 0xcc36, 0x21, 0 + .dw 0x6d03, 0xcc36, 0x6d0f, 0xcc36, 0x21, 0 + .dw 0x6d11, 0xcc36, 0x6d11, 0xcc36, 0x21, 0 + .dw 0x6d13, 0xcc36, 0x6d3f, 0xcc36, 0x21, 0 + .dw 0x6d41, 0xcc36, 0x6d41, 0xcc36, 0x21, 0 + .dw 0x6d43, 0xcc36, 0x6d4f, 0xcc36, 0x21, 0 + .dw 0x6d51, 0xcc36, 0x6d51, 0xcc36, 0x21, 0 + .dw 0x6d53, 0xcc36, 0x6d7f, 0xcc36, 0x21, 0 + .dw 0x6d81, 0xcc36, 0x6d81, 0xcc36, 0x21, 0 + .dw 0x6d83, 0xcc36, 0x6d8f, 0xcc36, 0x21, 0 + .dw 0x6d91, 0xcc36, 0x6d91, 0xcc36, 0x21, 0 + .dw 0x6d93, 0xcc36, 0x6dbf, 0xcc36, 0x21, 0 + .dw 0x6dc1, 0xcc36, 0x6dc1, 0xcc36, 0x21, 0 + .dw 0x6dc3, 0xcc36, 0x6dcf, 0xcc36, 0x21, 0 + .dw 0x6dd1, 0xcc36, 0x6dd1, 0xcc36, 0x21, 0 + .dw 0x6dd3, 0xcc36, 0x6dff, 0xcc36, 0x21, 0 + .dw 0x6e01, 0xcc36, 0x6e01, 0xcc36, 0x21, 0 + .dw 0x6e03, 0xcc36, 0x6e0f, 0xcc36, 0x21, 0 + .dw 0x6e11, 0xcc36, 0x6e11, 0xcc36, 0x21, 0 + .dw 0x6e13, 0xcc36, 0x6e3f, 0xcc36, 0x21, 0 + .dw 0x6e41, 0xcc36, 0x6e41, 0xcc36, 0x21, 0 + .dw 0x6e43, 0xcc36, 0x6e4f, 0xcc36, 0x21, 0 + .dw 0x6e51, 0xcc36, 0x6e51, 0xcc36, 0x21, 0 + .dw 0x6e53, 0xcc36, 0x6e7f, 0xcc36, 0x21, 0 + .dw 0x6e81, 0xcc36, 0x6e81, 0xcc36, 0x21, 0 + .dw 0x6e83, 0xcc36, 0x6e8f, 0xcc36, 0x21, 0 + .dw 0x6e91, 0xcc36, 0x6e91, 0xcc36, 0x21, 0 + .dw 0x6e93, 0xcc36, 0x6ebf, 0xcc36, 0x21, 0 + .dw 0x6ec1, 0xcc36, 0x6ec1, 0xcc36, 0x21, 0 + .dw 0x6ec3, 0xcc36, 0x6ecf, 0xcc36, 0x21, 0 + .dw 0x6ed1, 0xcc36, 0x6ed1, 0xcc36, 0x21, 0 + .dw 0x6ed3, 0xcc36, 0x6eff, 0xcc36, 0x21, 0 + .dw 0x6f01, 0xcc36, 0x6f01, 0xcc36, 0x21, 0 + .dw 0x6f03, 0xcc36, 0x6f0f, 0xcc36, 0x21, 0 + .dw 0x6f11, 0xcc36, 0x6f11, 0xcc36, 0x21, 0 + .dw 0x6f13, 0xcc36, 0x6f3f, 0xcc36, 0x21, 0 + .dw 0x6f41, 0xcc36, 0x6f41, 0xcc36, 0x21, 0 + .dw 0x6f43, 0xcc36, 0x6f4f, 0xcc36, 0x21, 0 + .dw 0x6f51, 0xcc36, 0x6f51, 0xcc36, 0x21, 0 + .dw 0x6f53, 0xcc36, 0x6f7f, 0xcc36, 0x21, 0 + .dw 0x6f81, 0xcc36, 0x6f81, 0xcc36, 0x21, 0 + .dw 0x6f83, 0xcc36, 0x6f8f, 0xcc36, 0x21, 0 + .dw 0x6f91, 0xcc36, 0x6f91, 0xcc36, 0x21, 0 + .dw 0x6f93, 0xcc36, 0x6fbf, 0xcc36, 0x21, 0 + .dw 0x6fc1, 0xcc36, 0x6fc1, 0xcc36, 0x21, 0 + .dw 0x6fc3, 0xcc36, 0x6fcf, 0xcc36, 0x21, 0 + .dw 0x6fd1, 0xcc36, 0x6fd1, 0xcc36, 0x21, 0 + .dw 0x6fd3, 0xcc36, 0xffff, 0xcc36, 0x21, 0 + .dw 0x0001, 0xcc37, 0x0001, 0xcc37, 0x21, 0 + .dw 0x0003, 0xcc37, 0x000f, 0xcc37, 0x21, 0 + .dw 0x0011, 0xcc37, 0x0011, 0xcc37, 0x21, 0 + .dw 0x0013, 0xcc37, 0x003f, 0xcc37, 0x21, 0 + .dw 0x0041, 0xcc37, 0x0041, 0xcc37, 0x21, 0 + .dw 0x0043, 0xcc37, 0x004f, 0xcc37, 0x21, 0 + .dw 0x0051, 0xcc37, 0x0051, 0xcc37, 0x21, 0 + .dw 0x0053, 0xcc37, 0x007f, 0xcc37, 0x21, 0 + .dw 0x0081, 0xcc37, 0x0081, 0xcc37, 0x21, 0 + .dw 0x0083, 0xcc37, 0x008f, 0xcc37, 0x21, 0 + .dw 0x0091, 0xcc37, 0x0091, 0xcc37, 0x21, 0 + .dw 0x0093, 0xcc37, 0x00bf, 0xcc37, 0x21, 0 + .dw 0x00c1, 0xcc37, 0x00c1, 0xcc37, 0x21, 0 + .dw 0x00c3, 0xcc37, 0x00cf, 0xcc37, 0x21, 0 + .dw 0x00d1, 0xcc37, 0x00d1, 0xcc37, 0x21, 0 + .dw 0x00d3, 0xcc37, 0x00ff, 0xcc37, 0x21, 0 + .dw 0x0101, 0xcc37, 0x0101, 0xcc37, 0x21, 0 + .dw 0x0103, 0xcc37, 0x010f, 0xcc37, 0x21, 0 + .dw 0x0111, 0xcc37, 0x0111, 0xcc37, 0x21, 0 + .dw 0x0113, 0xcc37, 0x013f, 0xcc37, 0x21, 0 + .dw 0x0141, 0xcc37, 0x0141, 0xcc37, 0x21, 0 + .dw 0x0143, 0xcc37, 0x014f, 0xcc37, 0x21, 0 + .dw 0x0151, 0xcc37, 0x0151, 0xcc37, 0x21, 0 + .dw 0x0153, 0xcc37, 0x017f, 0xcc37, 0x21, 0 + .dw 0x0181, 0xcc37, 0x0181, 0xcc37, 0x21, 0 + .dw 0x0183, 0xcc37, 0x018f, 0xcc37, 0x21, 0 + .dw 0x0191, 0xcc37, 0x0191, 0xcc37, 0x21, 0 + .dw 0x0193, 0xcc37, 0x01bf, 0xcc37, 0x21, 0 + .dw 0x01c1, 0xcc37, 0x01c1, 0xcc37, 0x21, 0 + .dw 0x01c3, 0xcc37, 0x01cf, 0xcc37, 0x21, 0 + .dw 0x01d1, 0xcc37, 0x01d1, 0xcc37, 0x21, 0 + .dw 0x01d3, 0xcc37, 0x01ff, 0xcc37, 0x21, 0 + .dw 0x0201, 0xcc37, 0x0201, 0xcc37, 0x21, 0 + .dw 0x0203, 0xcc37, 0x020f, 0xcc37, 0x21, 0 + .dw 0x0211, 0xcc37, 0x0211, 0xcc37, 0x21, 0 + .dw 0x0213, 0xcc37, 0x023f, 0xcc37, 0x21, 0 + .dw 0x0241, 0xcc37, 0x0241, 0xcc37, 0x21, 0 + .dw 0x0243, 0xcc37, 0x024f, 0xcc37, 0x21, 0 + .dw 0x0251, 0xcc37, 0x0251, 0xcc37, 0x21, 0 + .dw 0x0253, 0xcc37, 0x027f, 0xcc37, 0x21, 0 + .dw 0x0281, 0xcc37, 0x0281, 0xcc37, 0x21, 0 + .dw 0x0283, 0xcc37, 0x028f, 0xcc37, 0x21, 0 + .dw 0x0291, 0xcc37, 0x0291, 0xcc37, 0x21, 0 + .dw 0x0293, 0xcc37, 0x02bf, 0xcc37, 0x21, 0 + .dw 0x02c1, 0xcc37, 0x02c1, 0xcc37, 0x21, 0 + .dw 0x02c3, 0xcc37, 0x02cf, 0xcc37, 0x21, 0 + .dw 0x02d1, 0xcc37, 0x02d1, 0xcc37, 0x21, 0 + .dw 0x02d3, 0xcc37, 0x02ff, 0xcc37, 0x21, 0 + .dw 0x0301, 0xcc37, 0x0301, 0xcc37, 0x21, 0 + .dw 0x0303, 0xcc37, 0x030f, 0xcc37, 0x21, 0 + .dw 0x0311, 0xcc37, 0x0311, 0xcc37, 0x21, 0 + .dw 0x0313, 0xcc37, 0x033f, 0xcc37, 0x21, 0 + .dw 0x0341, 0xcc37, 0x0341, 0xcc37, 0x21, 0 + .dw 0x0343, 0xcc37, 0x034f, 0xcc37, 0x21, 0 + .dw 0x0351, 0xcc37, 0x0351, 0xcc37, 0x21, 0 + .dw 0x0353, 0xcc37, 0x037f, 0xcc37, 0x21, 0 + .dw 0x0381, 0xcc37, 0x0381, 0xcc37, 0x21, 0 + .dw 0x0383, 0xcc37, 0x038f, 0xcc37, 0x21, 0 + .dw 0x0391, 0xcc37, 0x0391, 0xcc37, 0x21, 0 + .dw 0x0393, 0xcc37, 0x03bf, 0xcc37, 0x21, 0 + .dw 0x03c1, 0xcc37, 0x03c1, 0xcc37, 0x21, 0 + .dw 0x03c3, 0xcc37, 0x03cf, 0xcc37, 0x21, 0 + .dw 0x03d1, 0xcc37, 0x03d1, 0xcc37, 0x21, 0 + .dw 0x03d3, 0xcc37, 0x03ff, 0xcc37, 0x21, 0 + .dw 0x0401, 0xcc37, 0x0401, 0xcc37, 0x21, 0 + .dw 0x0403, 0xcc37, 0x040f, 0xcc37, 0x21, 0 + .dw 0x0411, 0xcc37, 0x0411, 0xcc37, 0x21, 0 + .dw 0x0413, 0xcc37, 0x043f, 0xcc37, 0x21, 0 + .dw 0x0441, 0xcc37, 0x0441, 0xcc37, 0x21, 0 + .dw 0x0443, 0xcc37, 0x044f, 0xcc37, 0x21, 0 + .dw 0x0451, 0xcc37, 0x0451, 0xcc37, 0x21, 0 + .dw 0x0453, 0xcc37, 0x047f, 0xcc37, 0x21, 0 + .dw 0x0481, 0xcc37, 0x0481, 0xcc37, 0x21, 0 + .dw 0x0483, 0xcc37, 0x048f, 0xcc37, 0x21, 0 + .dw 0x0491, 0xcc37, 0x0491, 0xcc37, 0x21, 0 + .dw 0x0493, 0xcc37, 0x04bf, 0xcc37, 0x21, 0 + .dw 0x04c1, 0xcc37, 0x04c1, 0xcc37, 0x21, 0 + .dw 0x04c3, 0xcc37, 0x04cf, 0xcc37, 0x21, 0 + .dw 0x04d1, 0xcc37, 0x04d1, 0xcc37, 0x21, 0 + .dw 0x04d3, 0xcc37, 0x04ff, 0xcc37, 0x21, 0 + .dw 0x0501, 0xcc37, 0x0501, 0xcc37, 0x21, 0 + .dw 0x0503, 0xcc37, 0x050f, 0xcc37, 0x21, 0 + .dw 0x0511, 0xcc37, 0x0511, 0xcc37, 0x21, 0 + .dw 0x0513, 0xcc37, 0x053f, 0xcc37, 0x21, 0 + .dw 0x0541, 0xcc37, 0x0541, 0xcc37, 0x21, 0 + .dw 0x0543, 0xcc37, 0x054f, 0xcc37, 0x21, 0 + .dw 0x0551, 0xcc37, 0x0551, 0xcc37, 0x21, 0 + .dw 0x0553, 0xcc37, 0x057f, 0xcc37, 0x21, 0 + .dw 0x0581, 0xcc37, 0x0581, 0xcc37, 0x21, 0 + .dw 0x0583, 0xcc37, 0x058f, 0xcc37, 0x21, 0 + .dw 0x0591, 0xcc37, 0x0591, 0xcc37, 0x21, 0 + .dw 0x0593, 0xcc37, 0x05bf, 0xcc37, 0x21, 0 + .dw 0x05c1, 0xcc37, 0x05c1, 0xcc37, 0x21, 0 + .dw 0x05c3, 0xcc37, 0x05cf, 0xcc37, 0x21, 0 + .dw 0x05d1, 0xcc37, 0x05d1, 0xcc37, 0x21, 0 + .dw 0x05d3, 0xcc37, 0x05ff, 0xcc37, 0x21, 0 + .dw 0x0601, 0xcc37, 0x0601, 0xcc37, 0x21, 0 + .dw 0x0603, 0xcc37, 0x060f, 0xcc37, 0x21, 0 + .dw 0x0611, 0xcc37, 0x0611, 0xcc37, 0x21, 0 + .dw 0x0613, 0xcc37, 0x063f, 0xcc37, 0x21, 0 + .dw 0x0641, 0xcc37, 0x0641, 0xcc37, 0x21, 0 + .dw 0x0643, 0xcc37, 0x064f, 0xcc37, 0x21, 0 + .dw 0x0651, 0xcc37, 0x0651, 0xcc37, 0x21, 0 + .dw 0x0653, 0xcc37, 0x067f, 0xcc37, 0x21, 0 + .dw 0x0681, 0xcc37, 0x0681, 0xcc37, 0x21, 0 + .dw 0x0683, 0xcc37, 0x068f, 0xcc37, 0x21, 0 + .dw 0x0691, 0xcc37, 0x0691, 0xcc37, 0x21, 0 + .dw 0x0693, 0xcc37, 0x06bf, 0xcc37, 0x21, 0 + .dw 0x06c1, 0xcc37, 0x06c1, 0xcc37, 0x21, 0 + .dw 0x06c3, 0xcc37, 0x06cf, 0xcc37, 0x21, 0 + .dw 0x06d1, 0xcc37, 0x06d1, 0xcc37, 0x21, 0 + .dw 0x06d3, 0xcc37, 0x06ff, 0xcc37, 0x21, 0 + .dw 0x0701, 0xcc37, 0x0701, 0xcc37, 0x21, 0 + .dw 0x0703, 0xcc37, 0x070f, 0xcc37, 0x21, 0 + .dw 0x0711, 0xcc37, 0x0711, 0xcc37, 0x21, 0 + .dw 0x0713, 0xcc37, 0x073f, 0xcc37, 0x21, 0 + .dw 0x0741, 0xcc37, 0x0741, 0xcc37, 0x21, 0 + .dw 0x0743, 0xcc37, 0x074f, 0xcc37, 0x21, 0 + .dw 0x0751, 0xcc37, 0x0751, 0xcc37, 0x21, 0 + .dw 0x0753, 0xcc37, 0x077f, 0xcc37, 0x21, 0 + .dw 0x0781, 0xcc37, 0x0781, 0xcc37, 0x21, 0 + .dw 0x0783, 0xcc37, 0x078f, 0xcc37, 0x21, 0 + .dw 0x0791, 0xcc37, 0x0791, 0xcc37, 0x21, 0 + .dw 0x0793, 0xcc37, 0x07bf, 0xcc37, 0x21, 0 + .dw 0x07c1, 0xcc37, 0x07c1, 0xcc37, 0x21, 0 + .dw 0x07c3, 0xcc37, 0x07cf, 0xcc37, 0x21, 0 + .dw 0x07d1, 0xcc37, 0x07d1, 0xcc37, 0x21, 0 + .dw 0x07d3, 0xcc37, 0x07ff, 0xcc37, 0x21, 0 + .dw 0x0801, 0xcc37, 0x0801, 0xcc37, 0x21, 0 + .dw 0x0803, 0xcc37, 0x080f, 0xcc37, 0x21, 0 + .dw 0x0811, 0xcc37, 0x0811, 0xcc37, 0x21, 0 + .dw 0x0813, 0xcc37, 0x083f, 0xcc37, 0x21, 0 + .dw 0x0841, 0xcc37, 0x0841, 0xcc37, 0x21, 0 + .dw 0x0843, 0xcc37, 0x084f, 0xcc37, 0x21, 0 + .dw 0x0851, 0xcc37, 0x0851, 0xcc37, 0x21, 0 + .dw 0x0853, 0xcc37, 0x087f, 0xcc37, 0x21, 0 + .dw 0x0881, 0xcc37, 0x0881, 0xcc37, 0x21, 0 + .dw 0x0883, 0xcc37, 0x088f, 0xcc37, 0x21, 0 + .dw 0x0891, 0xcc37, 0x0891, 0xcc37, 0x21, 0 + .dw 0x0893, 0xcc37, 0x08bf, 0xcc37, 0x21, 0 + .dw 0x08c1, 0xcc37, 0x08c1, 0xcc37, 0x21, 0 + .dw 0x08c3, 0xcc37, 0x08cf, 0xcc37, 0x21, 0 + .dw 0x08d1, 0xcc37, 0x08d1, 0xcc37, 0x21, 0 + .dw 0x08d3, 0xcc37, 0x08ff, 0xcc37, 0x21, 0 + .dw 0x0901, 0xcc37, 0x0901, 0xcc37, 0x21, 0 + .dw 0x0903, 0xcc37, 0x090f, 0xcc37, 0x21, 0 + .dw 0x0911, 0xcc37, 0x0911, 0xcc37, 0x21, 0 + .dw 0x0913, 0xcc37, 0x093f, 0xcc37, 0x21, 0 + .dw 0x0941, 0xcc37, 0x0941, 0xcc37, 0x21, 0 + .dw 0x0943, 0xcc37, 0x094f, 0xcc37, 0x21, 0 + .dw 0x0951, 0xcc37, 0x0951, 0xcc37, 0x21, 0 + .dw 0x0953, 0xcc37, 0x097f, 0xcc37, 0x21, 0 + .dw 0x0981, 0xcc37, 0x0981, 0xcc37, 0x21, 0 + .dw 0x0983, 0xcc37, 0x098f, 0xcc37, 0x21, 0 + .dw 0x0991, 0xcc37, 0x0991, 0xcc37, 0x21, 0 + .dw 0x0993, 0xcc37, 0x09bf, 0xcc37, 0x21, 0 + .dw 0x09c1, 0xcc37, 0x09c1, 0xcc37, 0x21, 0 + .dw 0x09c3, 0xcc37, 0x09cf, 0xcc37, 0x21, 0 + .dw 0x09d1, 0xcc37, 0x09d1, 0xcc37, 0x21, 0 + .dw 0x09d3, 0xcc37, 0x09ff, 0xcc37, 0x21, 0 + .dw 0x0a01, 0xcc37, 0x0a01, 0xcc37, 0x21, 0 + .dw 0x0a03, 0xcc37, 0x0a0f, 0xcc37, 0x21, 0 + .dw 0x0a11, 0xcc37, 0x0a11, 0xcc37, 0x21, 0 + .dw 0x0a13, 0xcc37, 0x0a3f, 0xcc37, 0x21, 0 + .dw 0x0a41, 0xcc37, 0x0a41, 0xcc37, 0x21, 0 + .dw 0x0a43, 0xcc37, 0x0a4f, 0xcc37, 0x21, 0 + .dw 0x0a51, 0xcc37, 0x0a51, 0xcc37, 0x21, 0 + .dw 0x0a53, 0xcc37, 0x0a7f, 0xcc37, 0x21, 0 + .dw 0x0a81, 0xcc37, 0x0a81, 0xcc37, 0x21, 0 + .dw 0x0a83, 0xcc37, 0x0a8f, 0xcc37, 0x21, 0 + .dw 0x0a91, 0xcc37, 0x0a91, 0xcc37, 0x21, 0 + .dw 0x0a93, 0xcc37, 0x0abf, 0xcc37, 0x21, 0 + .dw 0x0ac1, 0xcc37, 0x0ac1, 0xcc37, 0x21, 0 + .dw 0x0ac3, 0xcc37, 0x0acf, 0xcc37, 0x21, 0 + .dw 0x0ad1, 0xcc37, 0x0ad1, 0xcc37, 0x21, 0 + .dw 0x0ad3, 0xcc37, 0x0aff, 0xcc37, 0x21, 0 + .dw 0x0b01, 0xcc37, 0x0b01, 0xcc37, 0x21, 0 + .dw 0x0b03, 0xcc37, 0x0b0f, 0xcc37, 0x21, 0 + .dw 0x0b11, 0xcc37, 0x0b11, 0xcc37, 0x21, 0 + .dw 0x0b13, 0xcc37, 0x0b3f, 0xcc37, 0x21, 0 + .dw 0x0b41, 0xcc37, 0x0b41, 0xcc37, 0x21, 0 + .dw 0x0b43, 0xcc37, 0x0b4f, 0xcc37, 0x21, 0 + .dw 0x0b51, 0xcc37, 0x0b51, 0xcc37, 0x21, 0 + .dw 0x0b53, 0xcc37, 0x0b7f, 0xcc37, 0x21, 0 + .dw 0x0b81, 0xcc37, 0x0b81, 0xcc37, 0x21, 0 + .dw 0x0b83, 0xcc37, 0x0b8f, 0xcc37, 0x21, 0 + .dw 0x0b91, 0xcc37, 0x0b91, 0xcc37, 0x21, 0 + .dw 0x0b93, 0xcc37, 0x0bbf, 0xcc37, 0x21, 0 + .dw 0x0bc1, 0xcc37, 0x0bc1, 0xcc37, 0x21, 0 + .dw 0x0bc3, 0xcc37, 0x0bcf, 0xcc37, 0x21, 0 + .dw 0x0bd1, 0xcc37, 0x0bd1, 0xcc37, 0x21, 0 + .dw 0x0bd3, 0xcc37, 0x0bff, 0xcc37, 0x21, 0 + .dw 0x0c01, 0xcc37, 0x0c01, 0xcc37, 0x21, 0 + .dw 0x0c03, 0xcc37, 0x0c0f, 0xcc37, 0x21, 0 + .dw 0x0c11, 0xcc37, 0x0c11, 0xcc37, 0x21, 0 + .dw 0x0c13, 0xcc37, 0x0c3f, 0xcc37, 0x21, 0 + .dw 0x0c41, 0xcc37, 0x0c41, 0xcc37, 0x21, 0 + .dw 0x0c43, 0xcc37, 0x0c4f, 0xcc37, 0x21, 0 + .dw 0x0c51, 0xcc37, 0x0c51, 0xcc37, 0x21, 0 + .dw 0x0c53, 0xcc37, 0x0c7f, 0xcc37, 0x21, 0 + .dw 0x0c81, 0xcc37, 0x0c81, 0xcc37, 0x21, 0 + .dw 0x0c83, 0xcc37, 0x0c8f, 0xcc37, 0x21, 0 + .dw 0x0c91, 0xcc37, 0x0c91, 0xcc37, 0x21, 0 + .dw 0x0c93, 0xcc37, 0x0cbf, 0xcc37, 0x21, 0 + .dw 0x0cc1, 0xcc37, 0x0cc1, 0xcc37, 0x21, 0 + .dw 0x0cc3, 0xcc37, 0x0ccf, 0xcc37, 0x21, 0 + .dw 0x0cd1, 0xcc37, 0x0cd1, 0xcc37, 0x21, 0 + .dw 0x0cd3, 0xcc37, 0x0cff, 0xcc37, 0x21, 0 + .dw 0x0d01, 0xcc37, 0x0d01, 0xcc37, 0x21, 0 + .dw 0x0d03, 0xcc37, 0x0d0f, 0xcc37, 0x21, 0 + .dw 0x0d11, 0xcc37, 0x0d11, 0xcc37, 0x21, 0 + .dw 0x0d13, 0xcc37, 0x0d3f, 0xcc37, 0x21, 0 + .dw 0x0d41, 0xcc37, 0x0d41, 0xcc37, 0x21, 0 + .dw 0x0d43, 0xcc37, 0x0d4f, 0xcc37, 0x21, 0 + .dw 0x0d51, 0xcc37, 0x0d51, 0xcc37, 0x21, 0 + .dw 0x0d53, 0xcc37, 0x0d7f, 0xcc37, 0x21, 0 + .dw 0x0d81, 0xcc37, 0x0d81, 0xcc37, 0x21, 0 + .dw 0x0d83, 0xcc37, 0x0d8f, 0xcc37, 0x21, 0 + .dw 0x0d91, 0xcc37, 0x0d91, 0xcc37, 0x21, 0 + .dw 0x0d93, 0xcc37, 0x0dbf, 0xcc37, 0x21, 0 + .dw 0x0dc1, 0xcc37, 0x0dc1, 0xcc37, 0x21, 0 + .dw 0x0dc3, 0xcc37, 0x0dcf, 0xcc37, 0x21, 0 + .dw 0x0dd1, 0xcc37, 0x0dd1, 0xcc37, 0x21, 0 + .dw 0x0dd3, 0xcc37, 0x0dff, 0xcc37, 0x21, 0 + .dw 0x0e01, 0xcc37, 0x0e01, 0xcc37, 0x21, 0 + .dw 0x0e03, 0xcc37, 0x0e0f, 0xcc37, 0x21, 0 + .dw 0x0e11, 0xcc37, 0x0e11, 0xcc37, 0x21, 0 + .dw 0x0e13, 0xcc37, 0x0e3f, 0xcc37, 0x21, 0 + .dw 0x0e41, 0xcc37, 0x0e41, 0xcc37, 0x21, 0 + .dw 0x0e43, 0xcc37, 0x0e4f, 0xcc37, 0x21, 0 + .dw 0x0e51, 0xcc37, 0x0e51, 0xcc37, 0x21, 0 + .dw 0x0e53, 0xcc37, 0x0e7f, 0xcc37, 0x21, 0 + .dw 0x0e81, 0xcc37, 0x0e81, 0xcc37, 0x21, 0 + .dw 0x0e83, 0xcc37, 0x0e8f, 0xcc37, 0x21, 0 + .dw 0x0e91, 0xcc37, 0x0e91, 0xcc37, 0x21, 0 + .dw 0x0e93, 0xcc37, 0x0ebf, 0xcc37, 0x21, 0 + .dw 0x0ec1, 0xcc37, 0x0ec1, 0xcc37, 0x21, 0 + .dw 0x0ec3, 0xcc37, 0x0ecf, 0xcc37, 0x21, 0 + .dw 0x0ed1, 0xcc37, 0x0ed1, 0xcc37, 0x21, 0 + .dw 0x0ed3, 0xcc37, 0x0eff, 0xcc37, 0x21, 0 + .dw 0x0f01, 0xcc37, 0x0f01, 0xcc37, 0x21, 0 + .dw 0x0f03, 0xcc37, 0x0f0f, 0xcc37, 0x21, 0 + .dw 0x0f11, 0xcc37, 0x0f11, 0xcc37, 0x21, 0 + .dw 0x0f13, 0xcc37, 0x0f3f, 0xcc37, 0x21, 0 + .dw 0x0f41, 0xcc37, 0x0f41, 0xcc37, 0x21, 0 + .dw 0x0f43, 0xcc37, 0x0f4f, 0xcc37, 0x21, 0 + .dw 0x0f51, 0xcc37, 0x0f51, 0xcc37, 0x21, 0 + .dw 0x0f53, 0xcc37, 0x0f7f, 0xcc37, 0x21, 0 + .dw 0x0f81, 0xcc37, 0x0f81, 0xcc37, 0x21, 0 + .dw 0x0f83, 0xcc37, 0x0f8f, 0xcc37, 0x21, 0 + .dw 0x0f91, 0xcc37, 0x0f91, 0xcc37, 0x21, 0 + .dw 0x0f93, 0xcc37, 0x0fbf, 0xcc37, 0x21, 0 + .dw 0x0fc1, 0xcc37, 0x0fc1, 0xcc37, 0x21, 0 + .dw 0x0fc3, 0xcc37, 0x0fcf, 0xcc37, 0x21, 0 + .dw 0x0fd1, 0xcc37, 0x0fd1, 0xcc37, 0x21, 0 + .dw 0x0fd3, 0xcc37, 0x1fff, 0xcc37, 0x21, 0 + .dw 0x2001, 0xcc37, 0x2001, 0xcc37, 0x21, 0 + .dw 0x2003, 0xcc37, 0x200f, 0xcc37, 0x21, 0 + .dw 0x2011, 0xcc37, 0x2011, 0xcc37, 0x21, 0 + .dw 0x2013, 0xcc37, 0x203f, 0xcc37, 0x21, 0 + .dw 0x2041, 0xcc37, 0x2041, 0xcc37, 0x21, 0 + .dw 0x2043, 0xcc37, 0x204f, 0xcc37, 0x21, 0 + .dw 0x2051, 0xcc37, 0x2051, 0xcc37, 0x21, 0 + .dw 0x2053, 0xcc37, 0x207f, 0xcc37, 0x21, 0 + .dw 0x2081, 0xcc37, 0x2081, 0xcc37, 0x21, 0 + .dw 0x2083, 0xcc37, 0x208f, 0xcc37, 0x21, 0 + .dw 0x2091, 0xcc37, 0x2091, 0xcc37, 0x21, 0 + .dw 0x2093, 0xcc37, 0x20bf, 0xcc37, 0x21, 0 + .dw 0x20c1, 0xcc37, 0x20c1, 0xcc37, 0x21, 0 + .dw 0x20c3, 0xcc37, 0x20cf, 0xcc37, 0x21, 0 + .dw 0x20d1, 0xcc37, 0x20d1, 0xcc37, 0x21, 0 + .dw 0x20d3, 0xcc37, 0x20ff, 0xcc37, 0x21, 0 + .dw 0x2101, 0xcc37, 0x2101, 0xcc37, 0x21, 0 + .dw 0x2103, 0xcc37, 0x210f, 0xcc37, 0x21, 0 + .dw 0x2111, 0xcc37, 0x2111, 0xcc37, 0x21, 0 + .dw 0x2113, 0xcc37, 0x213f, 0xcc37, 0x21, 0 + .dw 0x2141, 0xcc37, 0x2141, 0xcc37, 0x21, 0 + .dw 0x2143, 0xcc37, 0x214f, 0xcc37, 0x21, 0 + .dw 0x2151, 0xcc37, 0x2151, 0xcc37, 0x21, 0 + .dw 0x2153, 0xcc37, 0x217f, 0xcc37, 0x21, 0 + .dw 0x2181, 0xcc37, 0x2181, 0xcc37, 0x21, 0 + .dw 0x2183, 0xcc37, 0x218f, 0xcc37, 0x21, 0 + .dw 0x2191, 0xcc37, 0x2191, 0xcc37, 0x21, 0 + .dw 0x2193, 0xcc37, 0x21bf, 0xcc37, 0x21, 0 + .dw 0x21c1, 0xcc37, 0x21c1, 0xcc37, 0x21, 0 + .dw 0x21c3, 0xcc37, 0x21cf, 0xcc37, 0x21, 0 + .dw 0x21d1, 0xcc37, 0x21d1, 0xcc37, 0x21, 0 + .dw 0x21d3, 0xcc37, 0x21ff, 0xcc37, 0x21, 0 + .dw 0x2201, 0xcc37, 0x2201, 0xcc37, 0x21, 0 + .dw 0x2203, 0xcc37, 0x220f, 0xcc37, 0x21, 0 + .dw 0x2211, 0xcc37, 0x2211, 0xcc37, 0x21, 0 + .dw 0x2213, 0xcc37, 0x223f, 0xcc37, 0x21, 0 + .dw 0x2241, 0xcc37, 0x2241, 0xcc37, 0x21, 0 + .dw 0x2243, 0xcc37, 0x224f, 0xcc37, 0x21, 0 + .dw 0x2251, 0xcc37, 0x2251, 0xcc37, 0x21, 0 + .dw 0x2253, 0xcc37, 0x227f, 0xcc37, 0x21, 0 + .dw 0x2281, 0xcc37, 0x2281, 0xcc37, 0x21, 0 + .dw 0x2283, 0xcc37, 0x228f, 0xcc37, 0x21, 0 + .dw 0x2291, 0xcc37, 0x2291, 0xcc37, 0x21, 0 + .dw 0x2293, 0xcc37, 0x22bf, 0xcc37, 0x21, 0 + .dw 0x22c1, 0xcc37, 0x22c1, 0xcc37, 0x21, 0 + .dw 0x22c3, 0xcc37, 0x22cf, 0xcc37, 0x21, 0 + .dw 0x22d1, 0xcc37, 0x22d1, 0xcc37, 0x21, 0 + .dw 0x22d3, 0xcc37, 0x22ff, 0xcc37, 0x21, 0 + .dw 0x2301, 0xcc37, 0x2301, 0xcc37, 0x21, 0 + .dw 0x2303, 0xcc37, 0x230f, 0xcc37, 0x21, 0 + .dw 0x2311, 0xcc37, 0x2311, 0xcc37, 0x21, 0 + .dw 0x2313, 0xcc37, 0x233f, 0xcc37, 0x21, 0 + .dw 0x2341, 0xcc37, 0x2341, 0xcc37, 0x21, 0 + .dw 0x2343, 0xcc37, 0x234f, 0xcc37, 0x21, 0 + .dw 0x2351, 0xcc37, 0x2351, 0xcc37, 0x21, 0 + .dw 0x2353, 0xcc37, 0x237f, 0xcc37, 0x21, 0 + .dw 0x2381, 0xcc37, 0x2381, 0xcc37, 0x21, 0 + .dw 0x2383, 0xcc37, 0x238f, 0xcc37, 0x21, 0 + .dw 0x2391, 0xcc37, 0x2391, 0xcc37, 0x21, 0 + .dw 0x2393, 0xcc37, 0x23bf, 0xcc37, 0x21, 0 + .dw 0x23c1, 0xcc37, 0x23c1, 0xcc37, 0x21, 0 + .dw 0x23c3, 0xcc37, 0x23cf, 0xcc37, 0x21, 0 + .dw 0x23d1, 0xcc37, 0x23d1, 0xcc37, 0x21, 0 + .dw 0x23d3, 0xcc37, 0x23ff, 0xcc37, 0x21, 0 + .dw 0x2401, 0xcc37, 0x2401, 0xcc37, 0x21, 0 + .dw 0x2403, 0xcc37, 0x240f, 0xcc37, 0x21, 0 + .dw 0x2411, 0xcc37, 0x2411, 0xcc37, 0x21, 0 + .dw 0x2413, 0xcc37, 0x243f, 0xcc37, 0x21, 0 + .dw 0x2441, 0xcc37, 0x2441, 0xcc37, 0x21, 0 + .dw 0x2443, 0xcc37, 0x244f, 0xcc37, 0x21, 0 + .dw 0x2451, 0xcc37, 0x2451, 0xcc37, 0x21, 0 + .dw 0x2453, 0xcc37, 0x247f, 0xcc37, 0x21, 0 + .dw 0x2481, 0xcc37, 0x2481, 0xcc37, 0x21, 0 + .dw 0x2483, 0xcc37, 0x248f, 0xcc37, 0x21, 0 + .dw 0x2491, 0xcc37, 0x2491, 0xcc37, 0x21, 0 + .dw 0x2493, 0xcc37, 0x24bf, 0xcc37, 0x21, 0 + .dw 0x24c1, 0xcc37, 0x24c1, 0xcc37, 0x21, 0 + .dw 0x24c3, 0xcc37, 0x24cf, 0xcc37, 0x21, 0 + .dw 0x24d1, 0xcc37, 0x24d1, 0xcc37, 0x21, 0 + .dw 0x24d3, 0xcc37, 0x24ff, 0xcc37, 0x21, 0 + .dw 0x2501, 0xcc37, 0x2501, 0xcc37, 0x21, 0 + .dw 0x2503, 0xcc37, 0x250f, 0xcc37, 0x21, 0 + .dw 0x2511, 0xcc37, 0x2511, 0xcc37, 0x21, 0 + .dw 0x2513, 0xcc37, 0x253f, 0xcc37, 0x21, 0 + .dw 0x2541, 0xcc37, 0x2541, 0xcc37, 0x21, 0 + .dw 0x2543, 0xcc37, 0x254f, 0xcc37, 0x21, 0 + .dw 0x2551, 0xcc37, 0x2551, 0xcc37, 0x21, 0 + .dw 0x2553, 0xcc37, 0x257f, 0xcc37, 0x21, 0 + .dw 0x2581, 0xcc37, 0x2581, 0xcc37, 0x21, 0 + .dw 0x2583, 0xcc37, 0x258f, 0xcc37, 0x21, 0 + .dw 0x2591, 0xcc37, 0x2591, 0xcc37, 0x21, 0 + .dw 0x2593, 0xcc37, 0x25bf, 0xcc37, 0x21, 0 + .dw 0x25c1, 0xcc37, 0x25c1, 0xcc37, 0x21, 0 + .dw 0x25c3, 0xcc37, 0x25cf, 0xcc37, 0x21, 0 + .dw 0x25d1, 0xcc37, 0x25d1, 0xcc37, 0x21, 0 + .dw 0x25d3, 0xcc37, 0x25ff, 0xcc37, 0x21, 0 + .dw 0x2601, 0xcc37, 0x2601, 0xcc37, 0x21, 0 + .dw 0x2603, 0xcc37, 0x260f, 0xcc37, 0x21, 0 + .dw 0x2611, 0xcc37, 0x2611, 0xcc37, 0x21, 0 + .dw 0x2613, 0xcc37, 0x263f, 0xcc37, 0x21, 0 + .dw 0x2641, 0xcc37, 0x2641, 0xcc37, 0x21, 0 + .dw 0x2643, 0xcc37, 0x264f, 0xcc37, 0x21, 0 + .dw 0x2651, 0xcc37, 0x2651, 0xcc37, 0x21, 0 + .dw 0x2653, 0xcc37, 0x267f, 0xcc37, 0x21, 0 + .dw 0x2681, 0xcc37, 0x2681, 0xcc37, 0x21, 0 + .dw 0x2683, 0xcc37, 0x268f, 0xcc37, 0x21, 0 + .dw 0x2691, 0xcc37, 0x2691, 0xcc37, 0x21, 0 + .dw 0x2693, 0xcc37, 0x26bf, 0xcc37, 0x21, 0 + .dw 0x26c1, 0xcc37, 0x26c1, 0xcc37, 0x21, 0 + .dw 0x26c3, 0xcc37, 0x26cf, 0xcc37, 0x21, 0 + .dw 0x26d1, 0xcc37, 0x26d1, 0xcc37, 0x21, 0 + .dw 0x26d3, 0xcc37, 0x26ff, 0xcc37, 0x21, 0 + .dw 0x2701, 0xcc37, 0x2701, 0xcc37, 0x21, 0 + .dw 0x2703, 0xcc37, 0x270f, 0xcc37, 0x21, 0 + .dw 0x2711, 0xcc37, 0x2711, 0xcc37, 0x21, 0 + .dw 0x2713, 0xcc37, 0x273f, 0xcc37, 0x21, 0 + .dw 0x2741, 0xcc37, 0x2741, 0xcc37, 0x21, 0 + .dw 0x2743, 0xcc37, 0x274f, 0xcc37, 0x21, 0 + .dw 0x2751, 0xcc37, 0x2751, 0xcc37, 0x21, 0 + .dw 0x2753, 0xcc37, 0x277f, 0xcc37, 0x21, 0 + .dw 0x2781, 0xcc37, 0x2781, 0xcc37, 0x21, 0 + .dw 0x2783, 0xcc37, 0x278f, 0xcc37, 0x21, 0 + .dw 0x2791, 0xcc37, 0x2791, 0xcc37, 0x21, 0 + .dw 0x2793, 0xcc37, 0x27bf, 0xcc37, 0x21, 0 + .dw 0x27c1, 0xcc37, 0x27c1, 0xcc37, 0x21, 0 + .dw 0x27c3, 0xcc37, 0x27cf, 0xcc37, 0x21, 0 + .dw 0x27d1, 0xcc37, 0x27d1, 0xcc37, 0x21, 0 + .dw 0x27d3, 0xcc37, 0x27ff, 0xcc37, 0x21, 0 + .dw 0x2801, 0xcc37, 0x2801, 0xcc37, 0x21, 0 + .dw 0x2803, 0xcc37, 0x280f, 0xcc37, 0x21, 0 + .dw 0x2811, 0xcc37, 0x2811, 0xcc37, 0x21, 0 + .dw 0x2813, 0xcc37, 0x283f, 0xcc37, 0x21, 0 + .dw 0x2841, 0xcc37, 0x2841, 0xcc37, 0x21, 0 + .dw 0x2843, 0xcc37, 0x284f, 0xcc37, 0x21, 0 + .dw 0x2851, 0xcc37, 0x2851, 0xcc37, 0x21, 0 + .dw 0x2853, 0xcc37, 0x287f, 0xcc37, 0x21, 0 + .dw 0x2881, 0xcc37, 0x2881, 0xcc37, 0x21, 0 + .dw 0x2883, 0xcc37, 0x288f, 0xcc37, 0x21, 0 + .dw 0x2891, 0xcc37, 0x2891, 0xcc37, 0x21, 0 + .dw 0x2893, 0xcc37, 0x28bf, 0xcc37, 0x21, 0 + .dw 0x28c1, 0xcc37, 0x28c1, 0xcc37, 0x21, 0 + .dw 0x28c3, 0xcc37, 0x28cf, 0xcc37, 0x21, 0 + .dw 0x28d1, 0xcc37, 0x28d1, 0xcc37, 0x21, 0 + .dw 0x28d3, 0xcc37, 0x28ff, 0xcc37, 0x21, 0 + .dw 0x2901, 0xcc37, 0x2901, 0xcc37, 0x21, 0 + .dw 0x2903, 0xcc37, 0x290f, 0xcc37, 0x21, 0 + .dw 0x2911, 0xcc37, 0x2911, 0xcc37, 0x21, 0 + .dw 0x2913, 0xcc37, 0x293f, 0xcc37, 0x21, 0 + .dw 0x2941, 0xcc37, 0x2941, 0xcc37, 0x21, 0 + .dw 0x2943, 0xcc37, 0x294f, 0xcc37, 0x21, 0 + .dw 0x2951, 0xcc37, 0x2951, 0xcc37, 0x21, 0 + .dw 0x2953, 0xcc37, 0x297f, 0xcc37, 0x21, 0 + .dw 0x2981, 0xcc37, 0x2981, 0xcc37, 0x21, 0 + .dw 0x2983, 0xcc37, 0x298f, 0xcc37, 0x21, 0 + .dw 0x2991, 0xcc37, 0x2991, 0xcc37, 0x21, 0 + .dw 0x2993, 0xcc37, 0x29bf, 0xcc37, 0x21, 0 + .dw 0x29c1, 0xcc37, 0x29c1, 0xcc37, 0x21, 0 + .dw 0x29c3, 0xcc37, 0x29cf, 0xcc37, 0x21, 0 + .dw 0x29d1, 0xcc37, 0x29d1, 0xcc37, 0x21, 0 + .dw 0x29d3, 0xcc37, 0x29ff, 0xcc37, 0x21, 0 + .dw 0x2a01, 0xcc37, 0x2a01, 0xcc37, 0x21, 0 + .dw 0x2a03, 0xcc37, 0x2a0f, 0xcc37, 0x21, 0 + .dw 0x2a11, 0xcc37, 0x2a11, 0xcc37, 0x21, 0 + .dw 0x2a13, 0xcc37, 0x2a3f, 0xcc37, 0x21, 0 + .dw 0x2a41, 0xcc37, 0x2a41, 0xcc37, 0x21, 0 + .dw 0x2a43, 0xcc37, 0x2a4f, 0xcc37, 0x21, 0 + .dw 0x2a51, 0xcc37, 0x2a51, 0xcc37, 0x21, 0 + .dw 0x2a53, 0xcc37, 0x2a7f, 0xcc37, 0x21, 0 + .dw 0x2a81, 0xcc37, 0x2a81, 0xcc37, 0x21, 0 + .dw 0x2a83, 0xcc37, 0x2a8f, 0xcc37, 0x21, 0 + .dw 0x2a91, 0xcc37, 0x2a91, 0xcc37, 0x21, 0 + .dw 0x2a93, 0xcc37, 0x2abf, 0xcc37, 0x21, 0 + .dw 0x2ac1, 0xcc37, 0x2ac1, 0xcc37, 0x21, 0 + .dw 0x2ac3, 0xcc37, 0x2acf, 0xcc37, 0x21, 0 + .dw 0x2ad1, 0xcc37, 0x2ad1, 0xcc37, 0x21, 0 + .dw 0x2ad3, 0xcc37, 0x2aff, 0xcc37, 0x21, 0 + .dw 0x2b01, 0xcc37, 0x2b01, 0xcc37, 0x21, 0 + .dw 0x2b03, 0xcc37, 0x2b0f, 0xcc37, 0x21, 0 + .dw 0x2b11, 0xcc37, 0x2b11, 0xcc37, 0x21, 0 + .dw 0x2b13, 0xcc37, 0x2b3f, 0xcc37, 0x21, 0 + .dw 0x2b41, 0xcc37, 0x2b41, 0xcc37, 0x21, 0 + .dw 0x2b43, 0xcc37, 0x2b4f, 0xcc37, 0x21, 0 + .dw 0x2b51, 0xcc37, 0x2b51, 0xcc37, 0x21, 0 + .dw 0x2b53, 0xcc37, 0x2b7f, 0xcc37, 0x21, 0 + .dw 0x2b81, 0xcc37, 0x2b81, 0xcc37, 0x21, 0 + .dw 0x2b83, 0xcc37, 0x2b8f, 0xcc37, 0x21, 0 + .dw 0x2b91, 0xcc37, 0x2b91, 0xcc37, 0x21, 0 + .dw 0x2b93, 0xcc37, 0x2bbf, 0xcc37, 0x21, 0 + .dw 0x2bc1, 0xcc37, 0x2bc1, 0xcc37, 0x21, 0 + .dw 0x2bc3, 0xcc37, 0x2bcf, 0xcc37, 0x21, 0 + .dw 0x2bd1, 0xcc37, 0x2bd1, 0xcc37, 0x21, 0 + .dw 0x2bd3, 0xcc37, 0x2bff, 0xcc37, 0x21, 0 + .dw 0x2c01, 0xcc37, 0x2c01, 0xcc37, 0x21, 0 + .dw 0x2c03, 0xcc37, 0x2c0f, 0xcc37, 0x21, 0 + .dw 0x2c11, 0xcc37, 0x2c11, 0xcc37, 0x21, 0 + .dw 0x2c13, 0xcc37, 0x2c3f, 0xcc37, 0x21, 0 + .dw 0x2c41, 0xcc37, 0x2c41, 0xcc37, 0x21, 0 + .dw 0x2c43, 0xcc37, 0x2c4f, 0xcc37, 0x21, 0 + .dw 0x2c51, 0xcc37, 0x2c51, 0xcc37, 0x21, 0 + .dw 0x2c53, 0xcc37, 0x2c7f, 0xcc37, 0x21, 0 + .dw 0x2c81, 0xcc37, 0x2c81, 0xcc37, 0x21, 0 + .dw 0x2c83, 0xcc37, 0x2c8f, 0xcc37, 0x21, 0 + .dw 0x2c91, 0xcc37, 0x2c91, 0xcc37, 0x21, 0 + .dw 0x2c93, 0xcc37, 0x2cbf, 0xcc37, 0x21, 0 + .dw 0x2cc1, 0xcc37, 0x2cc1, 0xcc37, 0x21, 0 + .dw 0x2cc3, 0xcc37, 0x2ccf, 0xcc37, 0x21, 0 + .dw 0x2cd1, 0xcc37, 0x2cd1, 0xcc37, 0x21, 0 + .dw 0x2cd3, 0xcc37, 0x2cff, 0xcc37, 0x21, 0 + .dw 0x2d01, 0xcc37, 0x2d01, 0xcc37, 0x21, 0 + .dw 0x2d03, 0xcc37, 0x2d0f, 0xcc37, 0x21, 0 + .dw 0x2d11, 0xcc37, 0x2d11, 0xcc37, 0x21, 0 + .dw 0x2d13, 0xcc37, 0x2d3f, 0xcc37, 0x21, 0 + .dw 0x2d41, 0xcc37, 0x2d41, 0xcc37, 0x21, 0 + .dw 0x2d43, 0xcc37, 0x2d4f, 0xcc37, 0x21, 0 + .dw 0x2d51, 0xcc37, 0x2d51, 0xcc37, 0x21, 0 + .dw 0x2d53, 0xcc37, 0x2d7f, 0xcc37, 0x21, 0 + .dw 0x2d81, 0xcc37, 0x2d81, 0xcc37, 0x21, 0 + .dw 0x2d83, 0xcc37, 0x2d8f, 0xcc37, 0x21, 0 + .dw 0x2d91, 0xcc37, 0x2d91, 0xcc37, 0x21, 0 + .dw 0x2d93, 0xcc37, 0x2dbf, 0xcc37, 0x21, 0 + .dw 0x2dc1, 0xcc37, 0x2dc1, 0xcc37, 0x21, 0 + .dw 0x2dc3, 0xcc37, 0x2dcf, 0xcc37, 0x21, 0 + .dw 0x2dd1, 0xcc37, 0x2dd1, 0xcc37, 0x21, 0 + .dw 0x2dd3, 0xcc37, 0x2dff, 0xcc37, 0x21, 0 + .dw 0x2e01, 0xcc37, 0x2e01, 0xcc37, 0x21, 0 + .dw 0x2e03, 0xcc37, 0x2e0f, 0xcc37, 0x21, 0 + .dw 0x2e11, 0xcc37, 0x2e11, 0xcc37, 0x21, 0 + .dw 0x2e13, 0xcc37, 0x2e3f, 0xcc37, 0x21, 0 + .dw 0x2e41, 0xcc37, 0x2e41, 0xcc37, 0x21, 0 + .dw 0x2e43, 0xcc37, 0x2e4f, 0xcc37, 0x21, 0 + .dw 0x2e51, 0xcc37, 0x2e51, 0xcc37, 0x21, 0 + .dw 0x2e53, 0xcc37, 0x2e7f, 0xcc37, 0x21, 0 + .dw 0x2e81, 0xcc37, 0x2e81, 0xcc37, 0x21, 0 + .dw 0x2e83, 0xcc37, 0x2e8f, 0xcc37, 0x21, 0 + .dw 0x2e91, 0xcc37, 0x2e91, 0xcc37, 0x21, 0 + .dw 0x2e93, 0xcc37, 0x2ebf, 0xcc37, 0x21, 0 + .dw 0x2ec1, 0xcc37, 0x2ec1, 0xcc37, 0x21, 0 + .dw 0x2ec3, 0xcc37, 0x2ecf, 0xcc37, 0x21, 0 + .dw 0x2ed1, 0xcc37, 0x2ed1, 0xcc37, 0x21, 0 + .dw 0x2ed3, 0xcc37, 0x2eff, 0xcc37, 0x21, 0 + .dw 0x2f01, 0xcc37, 0x2f01, 0xcc37, 0x21, 0 + .dw 0x2f03, 0xcc37, 0x2f0f, 0xcc37, 0x21, 0 + .dw 0x2f11, 0xcc37, 0x2f11, 0xcc37, 0x21, 0 + .dw 0x2f13, 0xcc37, 0x2f3f, 0xcc37, 0x21, 0 + .dw 0x2f41, 0xcc37, 0x2f41, 0xcc37, 0x21, 0 + .dw 0x2f43, 0xcc37, 0x2f4f, 0xcc37, 0x21, 0 + .dw 0x2f51, 0xcc37, 0x2f51, 0xcc37, 0x21, 0 + .dw 0x2f53, 0xcc37, 0x2f7f, 0xcc37, 0x21, 0 + .dw 0x2f81, 0xcc37, 0x2f81, 0xcc37, 0x21, 0 + .dw 0x2f83, 0xcc37, 0x2f8f, 0xcc37, 0x21, 0 + .dw 0x2f91, 0xcc37, 0x2f91, 0xcc37, 0x21, 0 + .dw 0x2f93, 0xcc37, 0x2fbf, 0xcc37, 0x21, 0 + .dw 0x2fc1, 0xcc37, 0x2fc1, 0xcc37, 0x21, 0 + .dw 0x2fc3, 0xcc37, 0x2fcf, 0xcc37, 0x21, 0 + .dw 0x2fd1, 0xcc37, 0x2fd1, 0xcc37, 0x21, 0 + .dw 0x2fd3, 0xcc37, 0xffff, 0xcdff, 0x21, 0 + .dw 0x0040, 0xce00, 0x01ff, 0xce00, 0x21, 0 + .dw 0x0240, 0xce00, 0x03ff, 0xce00, 0x21, 0 + .dw 0x0440, 0xce00, 0x05ff, 0xce00, 0x21, 0 + .dw 0x0640, 0xce00, 0x07ff, 0xce00, 0x21, 0 + .dw 0x0840, 0xce00, 0x09ff, 0xce00, 0x21, 0 + .dw 0x0a40, 0xce00, 0x0bff, 0xce00, 0x21, 0 + .dw 0x0c40, 0xce00, 0x0dff, 0xce00, 0x21, 0 + .dw 0x0e40, 0xce00, 0x0fff, 0xce00, 0x21, 0 + .dw 0x1040, 0xce00, 0x11ff, 0xce00, 0x21, 0 + .dw 0x1240, 0xce00, 0x13ff, 0xce00, 0x21, 0 + .dw 0x1440, 0xce00, 0x15ff, 0xce00, 0x21, 0 + .dw 0x1640, 0xce00, 0x17ff, 0xce00, 0x21, 0 + .dw 0x1840, 0xce00, 0x19ff, 0xce00, 0x21, 0 + .dw 0x1a40, 0xce00, 0x1bff, 0xce00, 0x21, 0 + .dw 0x1c40, 0xce00, 0x1dff, 0xce00, 0x21, 0 + .dw 0x1e40, 0xce00, 0x1fff, 0xce00, 0x21, 0 + .dw 0x2040, 0xce00, 0x21ff, 0xce00, 0x21, 0 + .dw 0x2240, 0xce00, 0x23ff, 0xce00, 0x21, 0 + .dw 0x2440, 0xce00, 0x25ff, 0xce00, 0x21, 0 + .dw 0x2640, 0xce00, 0x27ff, 0xce00, 0x21, 0 + .dw 0x2840, 0xce00, 0x29ff, 0xce00, 0x21, 0 + .dw 0x2a40, 0xce00, 0x2bff, 0xce00, 0x21, 0 + .dw 0x2c40, 0xce00, 0x2dff, 0xce00, 0x21, 0 + .dw 0x2e40, 0xce00, 0x2fff, 0xce00, 0x21, 0 + .dw 0x3040, 0xce00, 0x31ff, 0xce00, 0x21, 0 + .dw 0x3240, 0xce00, 0x33ff, 0xce00, 0x21, 0 + .dw 0x3440, 0xce00, 0x35ff, 0xce00, 0x21, 0 + .dw 0x3640, 0xce00, 0x37ff, 0xce00, 0x21, 0 + .dw 0x3840, 0xce00, 0x39ff, 0xce00, 0x21, 0 + .dw 0x3a40, 0xce00, 0x3bff, 0xce00, 0x21, 0 + .dw 0x3c40, 0xce00, 0x3dff, 0xce00, 0x21, 0 + .dw 0x3e40, 0xce00, 0x3fff, 0xce00, 0x21, 0 + .dw 0x4040, 0xce00, 0x41ff, 0xce00, 0x21, 0 + .dw 0x4240, 0xce00, 0x43ff, 0xce00, 0x21, 0 + .dw 0x4440, 0xce00, 0x45ff, 0xce00, 0x21, 0 + .dw 0x4640, 0xce00, 0x47ff, 0xce00, 0x21, 0 + .dw 0x4840, 0xce00, 0x49ff, 0xce00, 0x21, 0 + .dw 0x4a40, 0xce00, 0x4bff, 0xce00, 0x21, 0 + .dw 0x4c40, 0xce00, 0x4dff, 0xce00, 0x21, 0 + .dw 0x4e40, 0xce00, 0x4fff, 0xce00, 0x21, 0 + .dw 0x5040, 0xce00, 0x51ff, 0xce00, 0x21, 0 + .dw 0x5240, 0xce00, 0x53ff, 0xce00, 0x21, 0 + .dw 0x5440, 0xce00, 0x55ff, 0xce00, 0x21, 0 + .dw 0x5640, 0xce00, 0x57ff, 0xce00, 0x21, 0 + .dw 0x5840, 0xce00, 0x59ff, 0xce00, 0x21, 0 + .dw 0x5a40, 0xce00, 0x5bff, 0xce00, 0x21, 0 + .dw 0x5c40, 0xce00, 0x5dff, 0xce00, 0x21, 0 + .dw 0x5e40, 0xce00, 0x5fff, 0xce00, 0x21, 0 + .dw 0x6040, 0xce00, 0x61ff, 0xce00, 0x21, 0 + .dw 0x6240, 0xce00, 0x63ff, 0xce00, 0x21, 0 + .dw 0x6440, 0xce00, 0x65ff, 0xce00, 0x21, 0 + .dw 0x6640, 0xce00, 0x67ff, 0xce00, 0x21, 0 + .dw 0x6840, 0xce00, 0x69ff, 0xce00, 0x21, 0 + .dw 0x6a40, 0xce00, 0x6bff, 0xce00, 0x21, 0 + .dw 0x6c40, 0xce00, 0x6dff, 0xce00, 0x21, 0 + .dw 0x6e40, 0xce00, 0x6fff, 0xce00, 0x21, 0 + .dw 0x7040, 0xce00, 0x71ff, 0xce00, 0x21, 0 + .dw 0x7240, 0xce00, 0x73ff, 0xce00, 0x21, 0 + .dw 0x7440, 0xce00, 0x75ff, 0xce00, 0x21, 0 + .dw 0x7640, 0xce00, 0x77ff, 0xce00, 0x21, 0 + .dw 0x7840, 0xce00, 0x79ff, 0xce00, 0x21, 0 + .dw 0x7a40, 0xce00, 0x7bff, 0xce00, 0x21, 0 + .dw 0x7c40, 0xce00, 0x7dff, 0xce00, 0x21, 0 + .dw 0x7e40, 0xce00, 0x7fff, 0xce00, 0x21, 0 + .dw 0x8040, 0xce00, 0x81ff, 0xce00, 0x21, 0 + .dw 0x8240, 0xce00, 0x83ff, 0xce00, 0x21, 0 + .dw 0x8440, 0xce00, 0x85ff, 0xce00, 0x21, 0 + .dw 0x8640, 0xce00, 0x87ff, 0xce00, 0x21, 0 + .dw 0x8840, 0xce00, 0x89ff, 0xce00, 0x21, 0 + .dw 0x8a40, 0xce00, 0x8bff, 0xce00, 0x21, 0 + .dw 0x8c40, 0xce00, 0x8dff, 0xce00, 0x21, 0 + .dw 0x8e40, 0xce00, 0x8fff, 0xce00, 0x21, 0 + .dw 0x9040, 0xce00, 0x91ff, 0xce00, 0x21, 0 + .dw 0x9240, 0xce00, 0x93ff, 0xce00, 0x21, 0 + .dw 0x9440, 0xce00, 0x95ff, 0xce00, 0x21, 0 + .dw 0x9640, 0xce00, 0x97ff, 0xce00, 0x21, 0 + .dw 0x9840, 0xce00, 0x99ff, 0xce00, 0x21, 0 + .dw 0x9a40, 0xce00, 0x9bff, 0xce00, 0x21, 0 + .dw 0x9c40, 0xce00, 0x9dff, 0xce00, 0x21, 0 + .dw 0x9e40, 0xce00, 0x9fff, 0xce00, 0x21, 0 + .dw 0xa040, 0xce00, 0xa1ff, 0xce00, 0x21, 0 + .dw 0xa240, 0xce00, 0xa3ff, 0xce00, 0x21, 0 + .dw 0xa440, 0xce00, 0xa5ff, 0xce00, 0x21, 0 + .dw 0xa640, 0xce00, 0xa7ff, 0xce00, 0x21, 0 + .dw 0xa840, 0xce00, 0xa9ff, 0xce00, 0x21, 0 + .dw 0xaa40, 0xce00, 0xabff, 0xce00, 0x21, 0 + .dw 0xac40, 0xce00, 0xadff, 0xce00, 0x21, 0 + .dw 0xae40, 0xce00, 0xafff, 0xce00, 0x21, 0 + .dw 0xb040, 0xce00, 0xb1ff, 0xce00, 0x21, 0 + .dw 0xb240, 0xce00, 0xb3ff, 0xce00, 0x21, 0 + .dw 0xb440, 0xce00, 0xb5ff, 0xce00, 0x21, 0 + .dw 0xb640, 0xce00, 0xb7ff, 0xce00, 0x21, 0 + .dw 0xb840, 0xce00, 0xb9ff, 0xce00, 0x21, 0 + .dw 0xba40, 0xce00, 0xbbff, 0xce00, 0x21, 0 + .dw 0xbc40, 0xce00, 0xbdff, 0xce00, 0x21, 0 + .dw 0xbe40, 0xce00, 0xffff, 0xce00, 0x21, 0 + .dw 0x0040, 0xce01, 0x01ff, 0xce01, 0x21, 0 + .dw 0x0240, 0xce01, 0x03ff, 0xce01, 0x21, 0 + .dw 0x0440, 0xce01, 0x05ff, 0xce01, 0x21, 0 + .dw 0x0640, 0xce01, 0x07ff, 0xce01, 0x21, 0 + .dw 0x0840, 0xce01, 0x09ff, 0xce01, 0x21, 0 + .dw 0x0a40, 0xce01, 0x0bff, 0xce01, 0x21, 0 + .dw 0x0c40, 0xce01, 0x0dff, 0xce01, 0x21, 0 + .dw 0x0e40, 0xce01, 0x3fff, 0xce01, 0x21, 0 + .dw 0x4040, 0xce01, 0x41ff, 0xce01, 0x21, 0 + .dw 0x4240, 0xce01, 0x43ff, 0xce01, 0x21, 0 + .dw 0x4440, 0xce01, 0x45ff, 0xce01, 0x21, 0 + .dw 0x4640, 0xce01, 0x47ff, 0xce01, 0x21, 0 + .dw 0x4840, 0xce01, 0x49ff, 0xce01, 0x21, 0 + .dw 0x4a40, 0xce01, 0x4bff, 0xce01, 0x21, 0 + .dw 0x4c40, 0xce01, 0x4dff, 0xce01, 0x21, 0 + .dw 0x4e40, 0xce01, 0x7fff, 0xce01, 0x21, 0 + .dw 0x8040, 0xce01, 0x81ff, 0xce01, 0x21, 0 + .dw 0x8240, 0xce01, 0x83ff, 0xce01, 0x21, 0 + .dw 0x8440, 0xce01, 0x85ff, 0xce01, 0x21, 0 + .dw 0x8640, 0xce01, 0x87ff, 0xce01, 0x21, 0 + .dw 0x8840, 0xce01, 0x89ff, 0xce01, 0x21, 0 + .dw 0x8a40, 0xce01, 0x8bff, 0xce01, 0x21, 0 + .dw 0x8c40, 0xce01, 0x8dff, 0xce01, 0x21, 0 + .dw 0x8e40, 0xce01, 0xffff, 0xce01, 0x21, 0 + .dw 0x0040, 0xce02, 0x01ff, 0xce02, 0x21, 0 + .dw 0x0240, 0xce02, 0x03ff, 0xce02, 0x21, 0 + .dw 0x0440, 0xce02, 0x05ff, 0xce02, 0x21, 0 + .dw 0x0640, 0xce02, 0x07ff, 0xce02, 0x21, 0 + .dw 0x0840, 0xce02, 0x09ff, 0xce02, 0x21, 0 + .dw 0x0a40, 0xce02, 0x0bff, 0xce02, 0x21, 0 + .dw 0x0c40, 0xce02, 0x0dff, 0xce02, 0x21, 0 + .dw 0x0e40, 0xce02, 0x3fff, 0xce02, 0x21, 0 + .dw 0x4040, 0xce02, 0x41ff, 0xce02, 0x21, 0 + .dw 0x4240, 0xce02, 0x43ff, 0xce02, 0x21, 0 + .dw 0x4440, 0xce02, 0x45ff, 0xce02, 0x21, 0 + .dw 0x4640, 0xce02, 0x47ff, 0xce02, 0x21, 0 + .dw 0x4840, 0xce02, 0x49ff, 0xce02, 0x21, 0 + .dw 0x4a40, 0xce02, 0x4bff, 0xce02, 0x21, 0 + .dw 0x4c40, 0xce02, 0x4dff, 0xce02, 0x21, 0 + .dw 0x4e40, 0xce02, 0x7fff, 0xce02, 0x21, 0 + .dw 0x8040, 0xce02, 0x81ff, 0xce02, 0x21, 0 + .dw 0x8240, 0xce02, 0x83ff, 0xce02, 0x21, 0 + .dw 0x8440, 0xce02, 0x85ff, 0xce02, 0x21, 0 + .dw 0x8640, 0xce02, 0x87ff, 0xce02, 0x21, 0 + .dw 0x8840, 0xce02, 0x89ff, 0xce02, 0x21, 0 + .dw 0x8a40, 0xce02, 0x8bff, 0xce02, 0x21, 0 + .dw 0x8c40, 0xce02, 0x8dff, 0xce02, 0x21, 0 + .dw 0x8e40, 0xce02, 0xbfff, 0xce02, 0x21, 0 + .dw 0xc040, 0xce02, 0xc1ff, 0xce02, 0x21, 0 + .dw 0xc240, 0xce02, 0xc3ff, 0xce02, 0x21, 0 + .dw 0xc440, 0xce02, 0xc5ff, 0xce02, 0x21, 0 + .dw 0xc640, 0xce02, 0xc7ff, 0xce02, 0x21, 0 + .dw 0xc840, 0xce02, 0xc9ff, 0xce02, 0x21, 0 + .dw 0xca40, 0xce02, 0xcbff, 0xce02, 0x21, 0 + .dw 0xcc40, 0xce02, 0xcdff, 0xce02, 0x21, 0 + .dw 0xce40, 0xce02, 0xffff, 0xce02, 0x21, 0 + .dw 0x0040, 0xce03, 0x01ff, 0xce03, 0x21, 0 + .dw 0x0240, 0xce03, 0x03ff, 0xce03, 0x21, 0 + .dw 0x0440, 0xce03, 0x05ff, 0xce03, 0x21, 0 + .dw 0x0640, 0xce03, 0x07ff, 0xce03, 0x21, 0 + .dw 0x0840, 0xce03, 0x09ff, 0xce03, 0x21, 0 + .dw 0x0a40, 0xce03, 0x0bff, 0xce03, 0x21, 0 + .dw 0x0c40, 0xce03, 0x0dff, 0xce03, 0x21, 0 + .dw 0x0e40, 0xce03, 0x0fff, 0xce03, 0x21, 0 + .dw 0x1040, 0xce03, 0x11ff, 0xce03, 0x21, 0 + .dw 0x1240, 0xce03, 0x13ff, 0xce03, 0x21, 0 + .dw 0x1440, 0xce03, 0x15ff, 0xce03, 0x21, 0 + .dw 0x1640, 0xce03, 0x17ff, 0xce03, 0x21, 0 + .dw 0x1840, 0xce03, 0x19ff, 0xce03, 0x21, 0 + .dw 0x1a40, 0xce03, 0x1bff, 0xce03, 0x21, 0 + .dw 0x1c40, 0xce03, 0x1dff, 0xce03, 0x21, 0 + .dw 0x1e40, 0xce03, 0x3fff, 0xce03, 0x21, 0 + .dw 0x4040, 0xce03, 0x41ff, 0xce03, 0x21, 0 + .dw 0x4240, 0xce03, 0x43ff, 0xce03, 0x21, 0 + .dw 0x4440, 0xce03, 0x45ff, 0xce03, 0x21, 0 + .dw 0x4640, 0xce03, 0x47ff, 0xce03, 0x21, 0 + .dw 0x4840, 0xce03, 0x49ff, 0xce03, 0x21, 0 + .dw 0x4a40, 0xce03, 0x4bff, 0xce03, 0x21, 0 + .dw 0x4c40, 0xce03, 0x4dff, 0xce03, 0x21, 0 + .dw 0x4e40, 0xce03, 0x4fff, 0xce03, 0x21, 0 + .dw 0x5040, 0xce03, 0x51ff, 0xce03, 0x21, 0 + .dw 0x5240, 0xce03, 0x53ff, 0xce03, 0x21, 0 + .dw 0x5440, 0xce03, 0x55ff, 0xce03, 0x21, 0 + .dw 0x5640, 0xce03, 0x57ff, 0xce03, 0x21, 0 + .dw 0x5840, 0xce03, 0x59ff, 0xce03, 0x21, 0 + .dw 0x5a40, 0xce03, 0x5bff, 0xce03, 0x21, 0 + .dw 0x5c40, 0xce03, 0x5dff, 0xce03, 0x21, 0 + .dw 0x5e40, 0xce03, 0x7fff, 0xce03, 0x21, 0 + .dw 0x8040, 0xce03, 0x81ff, 0xce03, 0x21, 0 + .dw 0x8240, 0xce03, 0x83ff, 0xce03, 0x21, 0 + .dw 0x8440, 0xce03, 0x85ff, 0xce03, 0x21, 0 + .dw 0x8640, 0xce03, 0x87ff, 0xce03, 0x21, 0 + .dw 0x8840, 0xce03, 0x89ff, 0xce03, 0x21, 0 + .dw 0x8a40, 0xce03, 0x8bff, 0xce03, 0x21, 0 + .dw 0x8c40, 0xce03, 0x8dff, 0xce03, 0x21, 0 + .dw 0x8e40, 0xce03, 0x8fff, 0xce03, 0x21, 0 + .dw 0x9040, 0xce03, 0x91ff, 0xce03, 0x21, 0 + .dw 0x9240, 0xce03, 0x93ff, 0xce03, 0x21, 0 + .dw 0x9440, 0xce03, 0x95ff, 0xce03, 0x21, 0 + .dw 0x9640, 0xce03, 0x97ff, 0xce03, 0x21, 0 + .dw 0x9840, 0xce03, 0x99ff, 0xce03, 0x21, 0 + .dw 0x9a40, 0xce03, 0x9bff, 0xce03, 0x21, 0 + .dw 0x9c40, 0xce03, 0x9dff, 0xce03, 0x21, 0 + .dw 0x9e40, 0xce03, 0xffff, 0xce03, 0x21, 0 + .dw 0x0040, 0xce04, 0x01ff, 0xce04, 0x21, 0 + .dw 0x0240, 0xce04, 0x03ff, 0xce04, 0x21, 0 + .dw 0x0440, 0xce04, 0x05ff, 0xce04, 0x21, 0 + .dw 0x0640, 0xce04, 0x07ff, 0xce04, 0x21, 0 + .dw 0x0840, 0xce04, 0x09ff, 0xce04, 0x21, 0 + .dw 0x0a40, 0xce04, 0x0bff, 0xce04, 0x21, 0 + .dw 0x0c40, 0xce04, 0x0dff, 0xce04, 0x21, 0 + .dw 0x0e40, 0xce04, 0x3fff, 0xce04, 0x21, 0 + .dw 0x4040, 0xce04, 0x41ff, 0xce04, 0x21, 0 + .dw 0x4240, 0xce04, 0x43ff, 0xce04, 0x21, 0 + .dw 0x4440, 0xce04, 0x45ff, 0xce04, 0x21, 0 + .dw 0x4640, 0xce04, 0x47ff, 0xce04, 0x21, 0 + .dw 0x4840, 0xce04, 0x49ff, 0xce04, 0x21, 0 + .dw 0x4a40, 0xce04, 0x4bff, 0xce04, 0x21, 0 + .dw 0x4c40, 0xce04, 0x4dff, 0xce04, 0x21, 0 + .dw 0x4e40, 0xce04, 0x7fff, 0xce04, 0x21, 0 + .dw 0x8040, 0xce04, 0x81ff, 0xce04, 0x21, 0 + .dw 0x8240, 0xce04, 0x83ff, 0xce04, 0x21, 0 + .dw 0x8440, 0xce04, 0x85ff, 0xce04, 0x21, 0 + .dw 0x8640, 0xce04, 0x87ff, 0xce04, 0x21, 0 + .dw 0x8840, 0xce04, 0x89ff, 0xce04, 0x21, 0 + .dw 0x8a40, 0xce04, 0x8bff, 0xce04, 0x21, 0 + .dw 0x8c40, 0xce04, 0x8dff, 0xce04, 0x21, 0 + .dw 0x8e40, 0xce04, 0xbfff, 0xce04, 0x21, 0 + .dw 0xc040, 0xce04, 0xc1ff, 0xce04, 0x21, 0 + .dw 0xc240, 0xce04, 0xc3ff, 0xce04, 0x21, 0 + .dw 0xc440, 0xce04, 0xc5ff, 0xce04, 0x21, 0 + .dw 0xc640, 0xce04, 0xc7ff, 0xce04, 0x21, 0 + .dw 0xc840, 0xce04, 0xc9ff, 0xce04, 0x21, 0 + .dw 0xca40, 0xce04, 0xcbff, 0xce04, 0x21, 0 + .dw 0xcc40, 0xce04, 0xcdff, 0xce04, 0x21, 0 + .dw 0xce40, 0xce04, 0xffff, 0xce04, 0x21, 0 + .dw 0x0040, 0xce05, 0x01ff, 0xce05, 0x21, 0 + .dw 0x0240, 0xce05, 0x03ff, 0xce05, 0x21, 0 + .dw 0x0440, 0xce05, 0x05ff, 0xce05, 0x21, 0 + .dw 0x0640, 0xce05, 0x07ff, 0xce05, 0x21, 0 + .dw 0x0840, 0xce05, 0x09ff, 0xce05, 0x21, 0 + .dw 0x0a40, 0xce05, 0x0bff, 0xce05, 0x21, 0 + .dw 0x0c40, 0xce05, 0x0dff, 0xce05, 0x21, 0 + .dw 0x0e40, 0xce05, 0x3fff, 0xce05, 0x21, 0 + .dw 0x4040, 0xce05, 0x41ff, 0xce05, 0x21, 0 + .dw 0x4240, 0xce05, 0x43ff, 0xce05, 0x21, 0 + .dw 0x4440, 0xce05, 0x45ff, 0xce05, 0x21, 0 + .dw 0x4640, 0xce05, 0x47ff, 0xce05, 0x21, 0 + .dw 0x4840, 0xce05, 0x49ff, 0xce05, 0x21, 0 + .dw 0x4a40, 0xce05, 0x4bff, 0xce05, 0x21, 0 + .dw 0x4c40, 0xce05, 0x4dff, 0xce05, 0x21, 0 + .dw 0x4e40, 0xce05, 0x7fff, 0xce05, 0x21, 0 + .dw 0x8040, 0xce05, 0x81ff, 0xce05, 0x21, 0 + .dw 0x8240, 0xce05, 0x83ff, 0xce05, 0x21, 0 + .dw 0x8440, 0xce05, 0x85ff, 0xce05, 0x21, 0 + .dw 0x8640, 0xce05, 0x87ff, 0xce05, 0x21, 0 + .dw 0x8840, 0xce05, 0x89ff, 0xce05, 0x21, 0 + .dw 0x8a40, 0xce05, 0x8bff, 0xce05, 0x21, 0 + .dw 0x8c40, 0xce05, 0x8dff, 0xce05, 0x21, 0 + .dw 0x8e40, 0xce05, 0xffff, 0xce05, 0x21, 0 + .dw 0x0040, 0xce06, 0x01ff, 0xce06, 0x21, 0 + .dw 0x0240, 0xce06, 0x03ff, 0xce06, 0x21, 0 + .dw 0x0440, 0xce06, 0x05ff, 0xce06, 0x21, 0 + .dw 0x0640, 0xce06, 0x07ff, 0xce06, 0x21, 0 + .dw 0x0840, 0xce06, 0x09ff, 0xce06, 0x21, 0 + .dw 0x0a40, 0xce06, 0x0bff, 0xce06, 0x21, 0 + .dw 0x0c40, 0xce06, 0x0dff, 0xce06, 0x21, 0 + .dw 0x0e40, 0xce06, 0x3fff, 0xce06, 0x21, 0 + .dw 0x4040, 0xce06, 0x41ff, 0xce06, 0x21, 0 + .dw 0x4240, 0xce06, 0x43ff, 0xce06, 0x21, 0 + .dw 0x4440, 0xce06, 0x45ff, 0xce06, 0x21, 0 + .dw 0x4640, 0xce06, 0x47ff, 0xce06, 0x21, 0 + .dw 0x4840, 0xce06, 0x49ff, 0xce06, 0x21, 0 + .dw 0x4a40, 0xce06, 0x4bff, 0xce06, 0x21, 0 + .dw 0x4c40, 0xce06, 0x4dff, 0xce06, 0x21, 0 + .dw 0x4e40, 0xce06, 0xbfff, 0xce06, 0x21, 0 + .dw 0xc040, 0xce06, 0xc1ff, 0xce06, 0x21, 0 + .dw 0xc240, 0xce06, 0xc3ff, 0xce06, 0x21, 0 + .dw 0xc440, 0xce06, 0xc5ff, 0xce06, 0x21, 0 + .dw 0xc640, 0xce06, 0xc7ff, 0xce06, 0x21, 0 + .dw 0xc840, 0xce06, 0xc9ff, 0xce06, 0x21, 0 + .dw 0xca40, 0xce06, 0xcbff, 0xce06, 0x21, 0 + .dw 0xcc40, 0xce06, 0xcdff, 0xce06, 0x21, 0 + .dw 0xce40, 0xce06, 0xffff, 0xce06, 0x21, 0 + .dw 0x0040, 0xce07, 0x01ff, 0xce07, 0x21, 0 + .dw 0x0240, 0xce07, 0x03ff, 0xce07, 0x21, 0 + .dw 0x0440, 0xce07, 0x05ff, 0xce07, 0x21, 0 + .dw 0x0640, 0xce07, 0x07ff, 0xce07, 0x21, 0 + .dw 0x0840, 0xce07, 0x09ff, 0xce07, 0x21, 0 + .dw 0x0a40, 0xce07, 0x0bff, 0xce07, 0x21, 0 + .dw 0x0c40, 0xce07, 0x0dff, 0xce07, 0x21, 0 + .dw 0x0e40, 0xce07, 0x3fff, 0xce07, 0x21, 0 + .dw 0x4040, 0xce07, 0x41ff, 0xce07, 0x21, 0 + .dw 0x4240, 0xce07, 0x43ff, 0xce07, 0x21, 0 + .dw 0x4440, 0xce07, 0x45ff, 0xce07, 0x21, 0 + .dw 0x4640, 0xce07, 0x47ff, 0xce07, 0x21, 0 + .dw 0x4840, 0xce07, 0x49ff, 0xce07, 0x21, 0 + .dw 0x4a40, 0xce07, 0x4bff, 0xce07, 0x21, 0 + .dw 0x4c40, 0xce07, 0x4dff, 0xce07, 0x21, 0 + .dw 0x4e40, 0xce07, 0x7fff, 0xce07, 0x21, 0 + .dw 0x8040, 0xce07, 0x81ff, 0xce07, 0x21, 0 + .dw 0x8240, 0xce07, 0x83ff, 0xce07, 0x21, 0 + .dw 0x8440, 0xce07, 0x85ff, 0xce07, 0x21, 0 + .dw 0x8640, 0xce07, 0x87ff, 0xce07, 0x21, 0 + .dw 0x8840, 0xce07, 0x89ff, 0xce07, 0x21, 0 + .dw 0x8a40, 0xce07, 0x8bff, 0xce07, 0x21, 0 + .dw 0x8c40, 0xce07, 0x8dff, 0xce07, 0x21, 0 + .dw 0x8e40, 0xce07, 0xbfff, 0xce07, 0x21, 0 + .dw 0xc040, 0xce07, 0xc1ff, 0xce07, 0x21, 0 + .dw 0xc240, 0xce07, 0xc3ff, 0xce07, 0x21, 0 + .dw 0xc440, 0xce07, 0xc5ff, 0xce07, 0x21, 0 + .dw 0xc640, 0xce07, 0xc7ff, 0xce07, 0x21, 0 + .dw 0xc840, 0xce07, 0xc9ff, 0xce07, 0x21, 0 + .dw 0xca40, 0xce07, 0xcbff, 0xce07, 0x21, 0 + .dw 0xcc40, 0xce07, 0xcdff, 0xce07, 0x21, 0 + .dw 0xce40, 0xce07, 0xffff, 0xce07, 0x21, 0 + .dw 0x0000, 0xce08, 0x0000, 0xce08, 0x22, 0 + .dw 0x0009, 0xce08, 0x0009, 0xce08, 0x22, 0 + .dw 0x0012, 0xce08, 0x0012, 0xce08, 0x22, 0 + .dw 0x001b, 0xce08, 0x001b, 0xce08, 0x22, 0 + .dw 0x0024, 0xce08, 0x0024, 0xce08, 0x22, 0 + .dw 0x002d, 0xce08, 0x002d, 0xce08, 0x22, 0 + .dw 0x0036, 0xce08, 0x0036, 0xce08, 0x22, 0 + .dw 0x003f, 0xce08, 0x003f, 0xce08, 0x22, 0 + .dw 0x0040, 0xce08, 0x01ff, 0xce08, 0x21, 0 + .dw 0x0200, 0xce08, 0x0200, 0xce08, 0x22, 0 + .dw 0x0209, 0xce08, 0x0209, 0xce08, 0x22, 0 + .dw 0x0212, 0xce08, 0x0212, 0xce08, 0x22, 0 + .dw 0x021b, 0xce08, 0x021b, 0xce08, 0x22, 0 + .dw 0x0224, 0xce08, 0x0224, 0xce08, 0x22, 0 + .dw 0x022d, 0xce08, 0x022d, 0xce08, 0x22, 0 + .dw 0x0236, 0xce08, 0x0236, 0xce08, 0x22, 0 + .dw 0x023f, 0xce08, 0x023f, 0xce08, 0x22, 0 + .dw 0x0240, 0xce08, 0x03ff, 0xce08, 0x21, 0 + .dw 0x0400, 0xce08, 0x0400, 0xce08, 0x22, 0 + .dw 0x0409, 0xce08, 0x0409, 0xce08, 0x22, 0 + .dw 0x0412, 0xce08, 0x0412, 0xce08, 0x22, 0 + .dw 0x041b, 0xce08, 0x041b, 0xce08, 0x22, 0 + .dw 0x0424, 0xce08, 0x0424, 0xce08, 0x22, 0 + .dw 0x042d, 0xce08, 0x042d, 0xce08, 0x22, 0 + .dw 0x0436, 0xce08, 0x0436, 0xce08, 0x22, 0 + .dw 0x043f, 0xce08, 0x043f, 0xce08, 0x22, 0 + .dw 0x0440, 0xce08, 0x05ff, 0xce08, 0x21, 0 + .dw 0x0600, 0xce08, 0x0600, 0xce08, 0x22, 0 + .dw 0x0609, 0xce08, 0x0609, 0xce08, 0x22, 0 + .dw 0x0612, 0xce08, 0x0612, 0xce08, 0x22, 0 + .dw 0x061b, 0xce08, 0x061b, 0xce08, 0x22, 0 + .dw 0x0624, 0xce08, 0x0624, 0xce08, 0x22, 0 + .dw 0x062d, 0xce08, 0x062d, 0xce08, 0x22, 0 + .dw 0x0636, 0xce08, 0x0636, 0xce08, 0x22, 0 + .dw 0x063f, 0xce08, 0x063f, 0xce08, 0x22, 0 + .dw 0x0640, 0xce08, 0x07ff, 0xce08, 0x21, 0 + .dw 0x0800, 0xce08, 0x0800, 0xce08, 0x22, 0 + .dw 0x0809, 0xce08, 0x0809, 0xce08, 0x22, 0 + .dw 0x0812, 0xce08, 0x0812, 0xce08, 0x22, 0 + .dw 0x081b, 0xce08, 0x081b, 0xce08, 0x22, 0 + .dw 0x0824, 0xce08, 0x0824, 0xce08, 0x22, 0 + .dw 0x082d, 0xce08, 0x082d, 0xce08, 0x22, 0 + .dw 0x0836, 0xce08, 0x0836, 0xce08, 0x22, 0 + .dw 0x083f, 0xce08, 0x083f, 0xce08, 0x22, 0 + .dw 0x0840, 0xce08, 0x09ff, 0xce08, 0x21, 0 + .dw 0x0a00, 0xce08, 0x0a00, 0xce08, 0x22, 0 + .dw 0x0a09, 0xce08, 0x0a09, 0xce08, 0x22, 0 + .dw 0x0a12, 0xce08, 0x0a12, 0xce08, 0x22, 0 + .dw 0x0a1b, 0xce08, 0x0a1b, 0xce08, 0x22, 0 + .dw 0x0a24, 0xce08, 0x0a24, 0xce08, 0x22, 0 + .dw 0x0a2d, 0xce08, 0x0a2d, 0xce08, 0x22, 0 + .dw 0x0a36, 0xce08, 0x0a36, 0xce08, 0x22, 0 + .dw 0x0a3f, 0xce08, 0x0a3f, 0xce08, 0x22, 0 + .dw 0x0a40, 0xce08, 0x0bff, 0xce08, 0x21, 0 + .dw 0x0c00, 0xce08, 0x0c00, 0xce08, 0x22, 0 + .dw 0x0c09, 0xce08, 0x0c09, 0xce08, 0x22, 0 + .dw 0x0c12, 0xce08, 0x0c12, 0xce08, 0x22, 0 + .dw 0x0c1b, 0xce08, 0x0c1b, 0xce08, 0x22, 0 + .dw 0x0c24, 0xce08, 0x0c24, 0xce08, 0x22, 0 + .dw 0x0c2d, 0xce08, 0x0c2d, 0xce08, 0x22, 0 + .dw 0x0c36, 0xce08, 0x0c36, 0xce08, 0x22, 0 + .dw 0x0c3f, 0xce08, 0x0c3f, 0xce08, 0x22, 0 + .dw 0x0c40, 0xce08, 0x0dff, 0xce08, 0x21, 0 + .dw 0x0e00, 0xce08, 0x0e00, 0xce08, 0x22, 0 + .dw 0x0e09, 0xce08, 0x0e09, 0xce08, 0x22, 0 + .dw 0x0e12, 0xce08, 0x0e12, 0xce08, 0x22, 0 + .dw 0x0e1b, 0xce08, 0x0e1b, 0xce08, 0x22, 0 + .dw 0x0e24, 0xce08, 0x0e24, 0xce08, 0x22, 0 + .dw 0x0e2d, 0xce08, 0x0e2d, 0xce08, 0x22, 0 + .dw 0x0e36, 0xce08, 0x0e36, 0xce08, 0x22, 0 + .dw 0x0e3f, 0xce08, 0x0e3f, 0xce08, 0x22, 0 + .dw 0x0e40, 0xce08, 0x3fff, 0xce08, 0x21, 0 + .dw 0x4000, 0xce08, 0x4000, 0xce08, 0x22, 0 + .dw 0x4009, 0xce08, 0x4009, 0xce08, 0x22, 0 + .dw 0x4012, 0xce08, 0x4012, 0xce08, 0x22, 0 + .dw 0x401b, 0xce08, 0x401b, 0xce08, 0x22, 0 + .dw 0x4024, 0xce08, 0x4024, 0xce08, 0x22, 0 + .dw 0x402d, 0xce08, 0x402d, 0xce08, 0x22, 0 + .dw 0x4036, 0xce08, 0x4036, 0xce08, 0x22, 0 + .dw 0x403f, 0xce08, 0x403f, 0xce08, 0x22, 0 + .dw 0x4040, 0xce08, 0x41ff, 0xce08, 0x21, 0 + .dw 0x4200, 0xce08, 0x4200, 0xce08, 0x22, 0 + .dw 0x4209, 0xce08, 0x4209, 0xce08, 0x22, 0 + .dw 0x4212, 0xce08, 0x4212, 0xce08, 0x22, 0 + .dw 0x421b, 0xce08, 0x421b, 0xce08, 0x22, 0 + .dw 0x4224, 0xce08, 0x4224, 0xce08, 0x22, 0 + .dw 0x422d, 0xce08, 0x422d, 0xce08, 0x22, 0 + .dw 0x4236, 0xce08, 0x4236, 0xce08, 0x22, 0 + .dw 0x423f, 0xce08, 0x423f, 0xce08, 0x22, 0 + .dw 0x4240, 0xce08, 0x43ff, 0xce08, 0x21, 0 + .dw 0x4400, 0xce08, 0x4400, 0xce08, 0x22, 0 + .dw 0x4409, 0xce08, 0x4409, 0xce08, 0x22, 0 + .dw 0x4412, 0xce08, 0x4412, 0xce08, 0x22, 0 + .dw 0x441b, 0xce08, 0x441b, 0xce08, 0x22, 0 + .dw 0x4424, 0xce08, 0x4424, 0xce08, 0x22, 0 + .dw 0x442d, 0xce08, 0x442d, 0xce08, 0x22, 0 + .dw 0x4436, 0xce08, 0x4436, 0xce08, 0x22, 0 + .dw 0x443f, 0xce08, 0x443f, 0xce08, 0x22, 0 + .dw 0x4440, 0xce08, 0x45ff, 0xce08, 0x21, 0 + .dw 0x4600, 0xce08, 0x4600, 0xce08, 0x22, 0 + .dw 0x4609, 0xce08, 0x4609, 0xce08, 0x22, 0 + .dw 0x4612, 0xce08, 0x4612, 0xce08, 0x22, 0 + .dw 0x461b, 0xce08, 0x461b, 0xce08, 0x22, 0 + .dw 0x4624, 0xce08, 0x4624, 0xce08, 0x22, 0 + .dw 0x462d, 0xce08, 0x462d, 0xce08, 0x22, 0 + .dw 0x4636, 0xce08, 0x4636, 0xce08, 0x22, 0 + .dw 0x463f, 0xce08, 0x463f, 0xce08, 0x22, 0 + .dw 0x4640, 0xce08, 0x47ff, 0xce08, 0x21, 0 + .dw 0x4800, 0xce08, 0x4800, 0xce08, 0x22, 0 + .dw 0x4809, 0xce08, 0x4809, 0xce08, 0x22, 0 + .dw 0x4812, 0xce08, 0x4812, 0xce08, 0x22, 0 + .dw 0x481b, 0xce08, 0x481b, 0xce08, 0x22, 0 + .dw 0x4824, 0xce08, 0x4824, 0xce08, 0x22, 0 + .dw 0x482d, 0xce08, 0x482d, 0xce08, 0x22, 0 + .dw 0x4836, 0xce08, 0x4836, 0xce08, 0x22, 0 + .dw 0x483f, 0xce08, 0x483f, 0xce08, 0x22, 0 + .dw 0x4840, 0xce08, 0x49ff, 0xce08, 0x21, 0 + .dw 0x4a00, 0xce08, 0x4a00, 0xce08, 0x22, 0 + .dw 0x4a09, 0xce08, 0x4a09, 0xce08, 0x22, 0 + .dw 0x4a12, 0xce08, 0x4a12, 0xce08, 0x22, 0 + .dw 0x4a1b, 0xce08, 0x4a1b, 0xce08, 0x22, 0 + .dw 0x4a24, 0xce08, 0x4a24, 0xce08, 0x22, 0 + .dw 0x4a2d, 0xce08, 0x4a2d, 0xce08, 0x22, 0 + .dw 0x4a36, 0xce08, 0x4a36, 0xce08, 0x22, 0 + .dw 0x4a3f, 0xce08, 0x4a3f, 0xce08, 0x22, 0 + .dw 0x4a40, 0xce08, 0x4bff, 0xce08, 0x21, 0 + .dw 0x4c00, 0xce08, 0x4c00, 0xce08, 0x22, 0 + .dw 0x4c09, 0xce08, 0x4c09, 0xce08, 0x22, 0 + .dw 0x4c12, 0xce08, 0x4c12, 0xce08, 0x22, 0 + .dw 0x4c1b, 0xce08, 0x4c1b, 0xce08, 0x22, 0 + .dw 0x4c24, 0xce08, 0x4c24, 0xce08, 0x22, 0 + .dw 0x4c2d, 0xce08, 0x4c2d, 0xce08, 0x22, 0 + .dw 0x4c36, 0xce08, 0x4c36, 0xce08, 0x22, 0 + .dw 0x4c3f, 0xce08, 0x4c3f, 0xce08, 0x22, 0 + .dw 0x4c40, 0xce08, 0x4dff, 0xce08, 0x21, 0 + .dw 0x4e00, 0xce08, 0x4e00, 0xce08, 0x22, 0 + .dw 0x4e09, 0xce08, 0x4e09, 0xce08, 0x22, 0 + .dw 0x4e12, 0xce08, 0x4e12, 0xce08, 0x22, 0 + .dw 0x4e1b, 0xce08, 0x4e1b, 0xce08, 0x22, 0 + .dw 0x4e24, 0xce08, 0x4e24, 0xce08, 0x22, 0 + .dw 0x4e2d, 0xce08, 0x4e2d, 0xce08, 0x22, 0 + .dw 0x4e36, 0xce08, 0x4e36, 0xce08, 0x22, 0 + .dw 0x4e3f, 0xce08, 0x4e3f, 0xce08, 0x22, 0 + .dw 0x4e40, 0xce08, 0xffff, 0xce08, 0x21, 0 + .dw 0x0040, 0xce09, 0x01ff, 0xce09, 0x21, 0 + .dw 0x0240, 0xce09, 0x03ff, 0xce09, 0x21, 0 + .dw 0x0440, 0xce09, 0x05ff, 0xce09, 0x21, 0 + .dw 0x0640, 0xce09, 0x07ff, 0xce09, 0x21, 0 + .dw 0x0840, 0xce09, 0x09ff, 0xce09, 0x21, 0 + .dw 0x0a40, 0xce09, 0x0bff, 0xce09, 0x21, 0 + .dw 0x0c40, 0xce09, 0x0dff, 0xce09, 0x21, 0 + .dw 0x0e40, 0xce09, 0x3fff, 0xce09, 0x21, 0 + .dw 0x4040, 0xce09, 0x41ff, 0xce09, 0x21, 0 + .dw 0x4240, 0xce09, 0x43ff, 0xce09, 0x21, 0 + .dw 0x4440, 0xce09, 0x45ff, 0xce09, 0x21, 0 + .dw 0x4640, 0xce09, 0x47ff, 0xce09, 0x21, 0 + .dw 0x4840, 0xce09, 0x49ff, 0xce09, 0x21, 0 + .dw 0x4a40, 0xce09, 0x4bff, 0xce09, 0x21, 0 + .dw 0x4c40, 0xce09, 0x4dff, 0xce09, 0x21, 0 + .dw 0x4e40, 0xce09, 0x7fff, 0xce09, 0x21, 0 + .dw 0x8040, 0xce09, 0x81ff, 0xce09, 0x21, 0 + .dw 0x8240, 0xce09, 0x83ff, 0xce09, 0x21, 0 + .dw 0x8440, 0xce09, 0x85ff, 0xce09, 0x21, 0 + .dw 0x8640, 0xce09, 0x87ff, 0xce09, 0x21, 0 + .dw 0x8840, 0xce09, 0x89ff, 0xce09, 0x21, 0 + .dw 0x8a40, 0xce09, 0x8bff, 0xce09, 0x21, 0 + .dw 0x8c40, 0xce09, 0x8dff, 0xce09, 0x21, 0 + .dw 0x8e40, 0xce09, 0xbfff, 0xce09, 0x21, 0 + .dw 0xc040, 0xce09, 0xc1ff, 0xce09, 0x21, 0 + .dw 0xc240, 0xce09, 0xc3ff, 0xce09, 0x21, 0 + .dw 0xc440, 0xce09, 0xc5ff, 0xce09, 0x21, 0 + .dw 0xc640, 0xce09, 0xc7ff, 0xce09, 0x21, 0 + .dw 0xc840, 0xce09, 0xc9ff, 0xce09, 0x21, 0 + .dw 0xca40, 0xce09, 0xcbff, 0xce09, 0x21, 0 + .dw 0xcc40, 0xce09, 0xcdff, 0xce09, 0x21, 0 + .dw 0xce40, 0xce09, 0xffff, 0xce09, 0x21, 0 + .dw 0x0040, 0xce0a, 0x01ff, 0xce0a, 0x21, 0 + .dw 0x0240, 0xce0a, 0x03ff, 0xce0a, 0x21, 0 + .dw 0x0440, 0xce0a, 0x05ff, 0xce0a, 0x21, 0 + .dw 0x0640, 0xce0a, 0x07ff, 0xce0a, 0x21, 0 + .dw 0x0840, 0xce0a, 0x09ff, 0xce0a, 0x21, 0 + .dw 0x0a40, 0xce0a, 0x0bff, 0xce0a, 0x21, 0 + .dw 0x0c40, 0xce0a, 0x0dff, 0xce0a, 0x21, 0 + .dw 0x0e40, 0xce0a, 0x3fff, 0xce0a, 0x21, 0 + .dw 0x4040, 0xce0a, 0x41ff, 0xce0a, 0x21, 0 + .dw 0x4240, 0xce0a, 0x43ff, 0xce0a, 0x21, 0 + .dw 0x4440, 0xce0a, 0x45ff, 0xce0a, 0x21, 0 + .dw 0x4640, 0xce0a, 0x47ff, 0xce0a, 0x21, 0 + .dw 0x4840, 0xce0a, 0x49ff, 0xce0a, 0x21, 0 + .dw 0x4a40, 0xce0a, 0x4bff, 0xce0a, 0x21, 0 + .dw 0x4c40, 0xce0a, 0x4dff, 0xce0a, 0x21, 0 + .dw 0x4e40, 0xce0a, 0x7fff, 0xce0a, 0x21, 0 + .dw 0x8040, 0xce0a, 0x81ff, 0xce0a, 0x21, 0 + .dw 0x8240, 0xce0a, 0x83ff, 0xce0a, 0x21, 0 + .dw 0x8440, 0xce0a, 0x85ff, 0xce0a, 0x21, 0 + .dw 0x8640, 0xce0a, 0x87ff, 0xce0a, 0x21, 0 + .dw 0x8840, 0xce0a, 0x89ff, 0xce0a, 0x21, 0 + .dw 0x8a40, 0xce0a, 0x8bff, 0xce0a, 0x21, 0 + .dw 0x8c40, 0xce0a, 0x8dff, 0xce0a, 0x21, 0 + .dw 0x8e40, 0xce0a, 0xbfff, 0xce0a, 0x21, 0 + .dw 0xc040, 0xce0a, 0xc1ff, 0xce0a, 0x21, 0 + .dw 0xc240, 0xce0a, 0xc3ff, 0xce0a, 0x21, 0 + .dw 0xc440, 0xce0a, 0xc5ff, 0xce0a, 0x21, 0 + .dw 0xc640, 0xce0a, 0xc7ff, 0xce0a, 0x21, 0 + .dw 0xc840, 0xce0a, 0xc9ff, 0xce0a, 0x21, 0 + .dw 0xca40, 0xce0a, 0xcbff, 0xce0a, 0x21, 0 + .dw 0xcc40, 0xce0a, 0xcdff, 0xce0a, 0x21, 0 + .dw 0xce40, 0xce0a, 0xffff, 0xce0a, 0x21, 0 + .dw 0x0040, 0xce0b, 0x01ff, 0xce0b, 0x21, 0 + .dw 0x0240, 0xce0b, 0x03ff, 0xce0b, 0x21, 0 + .dw 0x0440, 0xce0b, 0x05ff, 0xce0b, 0x21, 0 + .dw 0x0640, 0xce0b, 0x07ff, 0xce0b, 0x21, 0 + .dw 0x0840, 0xce0b, 0x09ff, 0xce0b, 0x21, 0 + .dw 0x0a40, 0xce0b, 0x0bff, 0xce0b, 0x21, 0 + .dw 0x0c40, 0xce0b, 0x0dff, 0xce0b, 0x21, 0 + .dw 0x0e40, 0xce0b, 0x3fff, 0xce0b, 0x21, 0 + .dw 0x4040, 0xce0b, 0x41ff, 0xce0b, 0x21, 0 + .dw 0x4240, 0xce0b, 0x43ff, 0xce0b, 0x21, 0 + .dw 0x4440, 0xce0b, 0x45ff, 0xce0b, 0x21, 0 + .dw 0x4640, 0xce0b, 0x47ff, 0xce0b, 0x21, 0 + .dw 0x4840, 0xce0b, 0x49ff, 0xce0b, 0x21, 0 + .dw 0x4a40, 0xce0b, 0x4bff, 0xce0b, 0x21, 0 + .dw 0x4c40, 0xce0b, 0x4dff, 0xce0b, 0x21, 0 + .dw 0x4e40, 0xce0b, 0xffff, 0xce0b, 0x21, 0 + .dw 0x0040, 0xce0c, 0x01ff, 0xce0c, 0x21, 0 + .dw 0x0240, 0xce0c, 0x03ff, 0xce0c, 0x21, 0 + .dw 0x0440, 0xce0c, 0x05ff, 0xce0c, 0x21, 0 + .dw 0x0640, 0xce0c, 0x07ff, 0xce0c, 0x21, 0 + .dw 0x0840, 0xce0c, 0x09ff, 0xce0c, 0x21, 0 + .dw 0x0a40, 0xce0c, 0x0bff, 0xce0c, 0x21, 0 + .dw 0x0c40, 0xce0c, 0x0dff, 0xce0c, 0x21, 0 + .dw 0x0e40, 0xce0c, 0x3fff, 0xce0c, 0x21, 0 + .dw 0x4040, 0xce0c, 0x41ff, 0xce0c, 0x21, 0 + .dw 0x4240, 0xce0c, 0x43ff, 0xce0c, 0x21, 0 + .dw 0x4440, 0xce0c, 0x45ff, 0xce0c, 0x21, 0 + .dw 0x4640, 0xce0c, 0x47ff, 0xce0c, 0x21, 0 + .dw 0x4840, 0xce0c, 0x49ff, 0xce0c, 0x21, 0 + .dw 0x4a40, 0xce0c, 0x4bff, 0xce0c, 0x21, 0 + .dw 0x4c40, 0xce0c, 0x4dff, 0xce0c, 0x21, 0 + .dw 0x4e40, 0xce0c, 0xffff, 0xce0c, 0x21, 0 + .dw 0x0040, 0xce0d, 0x01ff, 0xce0d, 0x21, 0 + .dw 0x0240, 0xce0d, 0x03ff, 0xce0d, 0x21, 0 + .dw 0x0440, 0xce0d, 0x05ff, 0xce0d, 0x21, 0 + .dw 0x0640, 0xce0d, 0x07ff, 0xce0d, 0x21, 0 + .dw 0x0840, 0xce0d, 0x09ff, 0xce0d, 0x21, 0 + .dw 0x0a40, 0xce0d, 0x0bff, 0xce0d, 0x21, 0 + .dw 0x0c40, 0xce0d, 0x0dff, 0xce0d, 0x21, 0 + .dw 0x0e40, 0xce0d, 0x3fff, 0xce0d, 0x21, 0 + .dw 0x4040, 0xce0d, 0x41ff, 0xce0d, 0x21, 0 + .dw 0x4240, 0xce0d, 0x43ff, 0xce0d, 0x21, 0 + .dw 0x4440, 0xce0d, 0x45ff, 0xce0d, 0x21, 0 + .dw 0x4640, 0xce0d, 0x47ff, 0xce0d, 0x21, 0 + .dw 0x4840, 0xce0d, 0x49ff, 0xce0d, 0x21, 0 + .dw 0x4a40, 0xce0d, 0x4bff, 0xce0d, 0x21, 0 + .dw 0x4c40, 0xce0d, 0x4dff, 0xce0d, 0x21, 0 + .dw 0x4e40, 0xce0d, 0x7fff, 0xce0d, 0x21, 0 + .dw 0x8040, 0xce0d, 0x81ff, 0xce0d, 0x21, 0 + .dw 0x8240, 0xce0d, 0x83ff, 0xce0d, 0x21, 0 + .dw 0x8440, 0xce0d, 0x85ff, 0xce0d, 0x21, 0 + .dw 0x8640, 0xce0d, 0x87ff, 0xce0d, 0x21, 0 + .dw 0x8840, 0xce0d, 0x89ff, 0xce0d, 0x21, 0 + .dw 0x8a40, 0xce0d, 0x8bff, 0xce0d, 0x21, 0 + .dw 0x8c40, 0xce0d, 0x8dff, 0xce0d, 0x21, 0 + .dw 0x8e40, 0xce0d, 0xffff, 0xce7f, 0x21, 0 + .dw 0xc000, 0xce80, 0xffff, 0xce80, 0x21, 0 + .dw 0x1000, 0xce81, 0x3fff, 0xce81, 0x21, 0 + .dw 0x5000, 0xce81, 0x7fff, 0xce81, 0x21, 0 + .dw 0x9000, 0xce81, 0xffff, 0xce81, 0x21, 0 + .dw 0x1000, 0xce82, 0x3fff, 0xce82, 0x21, 0 + .dw 0x5000, 0xce82, 0x7fff, 0xce82, 0x21, 0 + .dw 0x9000, 0xce82, 0xbfff, 0xce82, 0x21, 0 + .dw 0xd000, 0xce82, 0xffff, 0xce82, 0x21, 0 + .dw 0x2000, 0xce83, 0x3fff, 0xce83, 0x21, 0 + .dw 0x6000, 0xce83, 0x7fff, 0xce83, 0x21, 0 + .dw 0xa000, 0xce83, 0xffff, 0xffff, 0x21, 0 + .dw 0x0000, 0x0000, 0x0000, 0x0000, 0x00, 0 +.endm + + se_all_test diff --git a/sim/testsuite/bfin/se_all64bitg1opcodes.S b/sim/testsuite/bfin/se_all64bitg1opcodes.S new file mode 100644 index 0000000..aae10f0 --- /dev/null +++ b/sim/testsuite/bfin/se_all64bitg1opcodes.S @@ -0,0 +1,78 @@ +/* + * Blackfin testcase for testing illegal/legal 64-bit opcodes (group 1) + * from userspace. we track all instructions which cause some sort of + * exception when run from userspace, this is normally EXCAUSE : + * - 0x22 : illegal instruction combination + * and walk every instruction from 0x0000 to 0xffff + */ + +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + +#define SE_ALL_BITS 16 +#include "se_allopcodes.h" + +.macro se_all_load_insn + R2 = W[P5 + 4]; + R0 = R2; +.endm + +.macro se_all_next_insn + /* increment, and go again. */ + R0 = R2; + + R0 += 1; + /* finish once we hit the 32bit limit */ + imm32 R1, 0x10000; + CC = R1 == R0; + IF CC JUMP pass_lvl; + + W[P5 + 4] = R0; +.endm + +.macro se_all_insn_init + MNOP || NOP || NOP; +.endm +.macro se_all_insn_table + /* this table must be sorted, and end with zero */ + /* start end SEQSTAT */ + .dw 0x0001, 0x7fff, 0x22 + .dw 0x9040, 0x9040, 0x22 + .dw 0x9049, 0x9049, 0x22 + .dw 0x9052, 0x9052, 0x22 + .dw 0x905b, 0x905b, 0x22 + .dw 0x9064, 0x9064, 0x22 + .dw 0x906d, 0x906d, 0x22 + .dw 0x9076, 0x9076, 0x22 + .dw 0x907f, 0x907f, 0x22 + .dw 0x90c0, 0x90c0, 0x22 + .dw 0x90c9, 0x90c9, 0x22 + .dw 0x90d2, 0x90d2, 0x22 + .dw 0x90db, 0x90db, 0x22 + .dw 0x90e4, 0x90e4, 0x22 + .dw 0x90ed, 0x90ed, 0x22 + .dw 0x90f6, 0x90f6, 0x22 + .dw 0x90ff, 0x90ff, 0x22 + .dw 0x9180, 0x91ff, 0x22 + .dw 0x9380, 0x93ff, 0x22 + .dw 0x9580, 0x95ff, 0x22 + .dw 0x9640, 0x967f, 0x22 + .dw 0x96c0, 0x96ff, 0x22 + .dw 0x9740, 0x97ff, 0x22 + .dw 0x9980, 0x99ff, 0x22 + .dw 0x9a40, 0x9a7f, 0x22 + .dw 0x9ac0, 0x9aff, 0x22 + .dw 0x9b40, 0x9bff, 0x22 + .dw 0x9c60, 0x9c7f, 0x22 + .dw 0x9ce0, 0x9cff, 0x22 + .dw 0x9d60, 0x9d7f, 0x22 + .dw 0x9ef0, 0x9eff, 0x22 + .dw 0x9f70, 0x9f7f, 0x22 + .dw 0xc000, 0xffff, 0x22 + .dw 0x0000, 0x0000, 0x00 +.endm + + se_all_test diff --git a/sim/testsuite/bfin/se_all64bitg2opcodes.S b/sim/testsuite/bfin/se_all64bitg2opcodes.S new file mode 100644 index 0000000..99de3ac --- /dev/null +++ b/sim/testsuite/bfin/se_all64bitg2opcodes.S @@ -0,0 +1,53 @@ +/* + * Blackfin testcase for testing illegal/legal 64-bit opcodes (group 2) + * from userspace. we track all instructions which cause some sort of + * exception when run from userspace, this is normally EXCAUSE : + * - 0x22 : illegal instruction combination + * and walk every instruction from 0x0000 to 0xffff + */ + +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + +#define SE_ALL_BITS 16 +#include "se_allopcodes.h" + +.macro se_all_load_insn + R2 = W[P5 + 6]; + R0 = R2; +.endm + +.macro se_all_next_insn + /* increment, and go again. */ + R0 = R2; + + R0 += 1; + /* finish once we hit the 32bit limit */ + imm32 R1, 0x10000; + CC = R1 == R0; + IF CC JUMP pass_lvl; + + W[P5 + 6] = R0; +.endm + +.macro se_all_insn_init + MNOP || NOP || NOP; +.endm +.macro se_all_insn_table + /* this table must be sorted, and end with zero */ + /* start end SEQSTAT */ + .dw 0x0001, 0x9bff, 0x22 + .dw 0x9c60, 0x9c7f, 0x22 + .dw 0x9ce0, 0x9cff, 0x22 + .dw 0x9d60, 0x9d7f, 0x22 + .dw 0x9e60, 0x9e7f, 0x22 + .dw 0x9ee0, 0x9eff, 0x22 + .dw 0x9f60, 0x9f7f, 0x22 + .dw 0xa000, 0xffff, 0x22 + .dw 0x0000, 0x0000, 0x00 +.endm + + se_all_test diff --git a/sim/testsuite/bfin/se_allopcodes.h b/sim/testsuite/bfin/se_allopcodes.h new file mode 100644 index 0000000..796d5c4 --- /dev/null +++ b/sim/testsuite/bfin/se_allopcodes.h @@ -0,0 +1,239 @@ +/* + * set up pointers to valid data (32Meg), to reduce address violations + */ +.macro reset_dags + imm32 r0, 0x2000000; + l0 = 0; l1 = 0; l2 = 0; l3 = 0; + p0 = r0; p1 = r0; p2 = r0; p3 = r0; p4 = r0; p5 = r0; + usp = r0; fp = r0; + i0 = r0; i1 = r0; i2 = r0; i3 = r0; + b0 = r0; b1 = r0; b2 = r0; b3 = r0; +.endm + +#if SE_ALL_BITS == 32 +# define LOAD_PFX +#elif SE_ALL_BITS == 16 +# define LOAD_PFX W +#else +# error "Please define SE_ALL_BITS" +#endif + +/* + * execute a test of an opcode space. host test + * has to fill out a number of callbacks. + * + * se_all_insn_init + * the first insn to start executing + * se_all_insn_table + * the table of insn ranges and expected seqstat + * + * se_all_load_insn + * in: P5 + * out: R0, R2 + * scratch: R1 + * load current user insn via register P5 into R0. + * register R2 is available for caching with se_all_next_insn. + * se_all_load_table + * in: P1 + * out: R7, R6, R5 + * scratch: R1 + * load insn range/seqstat entry from table via register P1 + * R7: low range + * R6: high range + * R5: seqstat + * + * se_all_next_insn + * in: P5, R2 + * out: + * scratch: all but P5 + * advance current insn to next one for testing. register R2 + * is retained from se_all_load_insn. write out new insn to + * the location via register P5. + * + * se_all_new_insn_stub + * se_all_new_insn_log + * for handling of new insns ... generally not needed once done + */ +.macro se_all_test + start + + /* Set up exception handler */ + imm32 P4, EVT3; + loadsym R1, _evx; + [P4] = R1; + + /* set up the _location */ + loadsym P0, _location + loadsym P1, _table; + [P0] = P1; + + /* Enable single stepping */ + R0 = 1; + SYSCFG = R0; + + /* Lower to the code we want to single step through */ + loadsym P1, _usr; + RETI = P1; + + /* set up pointers to valid data (32Meg), to reduce address violations */ + reset_dags + + RTI; + +pass_lvl: + dbg_pass; +fail_lvl: + dbg_fail; + +_evx: + /* Make sure exception reason is as we expect */ + R3 = SEQSTAT; + R4 = 0x3f; + R3 = R3 & R4; + + /* find a match */ + loadsym P5, _usr; + loadsym P4, _location; + P1 = [P4]; + se_all_load_insn + +_match: + P2 = P1; + se_all_load_table + + /* is this the end of the table? */ + CC = R7 == 0; + IF CC jump _new_instruction; + + /* is the opcode (R0) greater than the 2nd entry in the table (R6) */ + /* if so look at the next line in the table */ + CC = R6 < R0; + if CC jump _match; + + /* is the opcode (R0) smaller than the first entry in the table (R7) */ + /* this means it's somewhere between the two lines, and should be legal */ + CC = R7 <= R0; + if !CC jump _legal_instruction; + + /* is the current EXCAUSE (R3), the same as the table (R5) */ + /* if not, fail */ + CC = R3 == R5 + if !CC jump fail_lvl; + +_match_done: + /* back up, and store the location to search next */ + [P4] = P2; + + /* it matches, so fall through */ + jump _next_instruction; + +_new_instruction: + /* The table is generated in memory and can be extracted: + (gdb) dump binary memory bin &table next_location + + 16bit: + $ od -j6 -x --width=4 bin | \ + awk '{ s=last; e=strtonum("0x"$2); \ + printf "\t.dw 0x%04x,\t0x%04x,\t\t0x%02x\n", \ + s, e-1, strtonum("0x"seq); \ + last=e; seq=$3}' + + 32bit: + $ od -j12 -x --width=8 bin | \ + awk '{ s=last; e=strtonum("0x"$3$2); \ + printf "\t.dw 0x%04x, 0x%04x,\t0x%04x, 0x%04x,\t\t0x%02x, 0\n", \ + and(s,0xffff), rshift(s,16), and(e-1,0xffff), rshift(e-1,16), \ + strtonum("0x"seq); \ + last=e; seq=$3}' + + This should be much faster than dumping over serial/jtag. */ + se_all_new_insn_stub + + /* output the insn (R0) and excause (R3) if diff from last */ + loadsym P0, _last_excause; + R2 = [P0]; + CC = R2 == R3; + IF CC jump _next_instruction; + [P0] = R3; + + se_all_new_insn_log + +_legal_instruction: + R4 = 0x10; + CC = R3 == R4; + IF !CC JUMP fail_lvl; + /* it wasn't in the list, and was a single step, so fall through */ + +_next_instruction: + se_all_next_insn + +.ifdef BFIN_JTAG + /* Make sure the opcode isn't in a write buffer */ + SSYNC; +.endif + + R1 = P5; + RETX = R1; + + /* set up pointers to valid data (32Meg), to reduce address violations */ + reset_dags + RETS = r0; + + RTX; + +.section .text.usr + .align 4 +_usr: + se_all_insn_init + loadsym P0, fail_lvl; + JUMP (P0); + +.data + .align 4; +_last_excause: + .dd 0xffff +_next_location: + .dd _table_end +_location: + .dd 0 +_table: + se_all_insn_table +_table_end: +.endm + +.macro se_all_load_table + R7 = LOAD_PFX[P1++]; + R6 = LOAD_PFX[P1++]; + R5 = LOAD_PFX[P1++]; +.endm + +#ifndef SE_ALL_NEW_INSN_STUB +.macro se_all_new_insn_stub + jump fail_lvl; +.endm +#endif + +.macro se_all_new_insn_log +.ifdef BFIN_JTAG_xxxxx + R1 = R0; +#if SE_ALL_BITS == 32 + R0 = 0x8; + call __emu_out; + R0 = R1; + call __emu_out; + R0 = R3; +#else + R0 = 0x4; + call __emu_out; + R0 = R1 << 16; + R0 = R0 | R3; +#endif + call __emu_out; +.else + loadsym P0, _next_location; + P1 = [P0]; + LOAD_PFX[P1++] = R0; + LOAD_PFX[P1++] = R3; + [P0] = P1; +.endif +.endm diff --git a/sim/testsuite/bfin/se_brtarget_stall.S b/sim/testsuite/bfin/se_brtarget_stall.S new file mode 100644 index 0000000..066602b --- /dev/null +++ b/sim/testsuite/bfin/se_brtarget_stall.S @@ -0,0 +1,462 @@ +//Original:/proj/frio/dv/testcases/seq/se_brtarget_stall/se_brtarget_stall.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000020 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + +///////////////////////////////////////////////////////////////////////////// +//////////////////////// CPLB Setup ///////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + // Setup CPLB for Data Memory starting at 0x00F0_0000; +WR_MMR(DCPLB_DATA0, 0x0003109d, p0, r0); // Page Size = 4MB + // CPLB_L1_CHLB = 1 + // CPLB_DIRTY = 1 + // CPLB_USER_RD = 1 + // CPLB_USER_WR = 1 + // CPLB_SUPV_WR = 1 + // CPLB_VALID = 1 + // + + // Setup CPLB Address to point to 0x00F0_0000 +WR_MMR_LABEL(DCPLB_ADDR0, data, p0, r0); + + // Enable CPLB's +WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1 + // ENDCPLB = 1 + // DMC = 11 + // Sync it! +CSYNC; + + + // Return to Supervisor Code +RAISE 15; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +NOP; + P0 = 0x0100 (Z); + P0.H = 0x00f0; +JUMP.S lab1; // Branch in EX1 + + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +lab1: + [ -- SP ] = ( R7:3 ); + P0 = 0x0200 (Z); + P0.H = 0x00f0; +RTI; +JUMP.S 8; // Branch in EX1 +NOP; +NOP; +NOP; + [ -- SP ] = ( R7:4 ); + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +data: +.section MEM_0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_0x00F00200,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_bug_ui.S b/sim/testsuite/bfin/se_bug_ui.S new file mode 100644 index 0000000..4922d97 --- /dev/null +++ b/sim/testsuite/bfin/se_bug_ui.S @@ -0,0 +1,296 @@ +//Original:/proj/frio/dv/testcases/seq/se_bug_ui/se_bug_ui.dsp +// Description: 16 bit special cases Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // count of UI's will be in r5, which was initialized to 0 by header + + .dw 0x41FD ; + .dw 0x41FE ; + .dw 0x41FF ; + .dw 0x9040 ; + .dw 0x9049 ; + .dw 0x9052 ; + .dw 0x905B ; + .dw 0x9064 ; + .dw 0x906D ; + .dw 0x9076 ; + .dw 0x907F ; + .dw 0x90C0 ; + .dw 0x90C9 ; + .dw 0x90D2 ; + .dw 0x90DB ; + .dw 0x90E4 ; + .dw 0x90ED ; + .dw 0x90F6 ; + .dw 0x90FF ; + .dw 0x9180 ; + + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +CHECKREG(r5, 20); // count of all 16 bit UI's. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 16 bit illegal opcode handler - skips bad instruction + + // handler MADE LEAN and destructive so test runs more quckly + // se_undefinedinstruction1.dsp tests using a "nice" handler + +// [--sp] = ASTAT; // save what we damage +// [--sp] = (r7 - r6); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + + R6 = 0x22; // Also accept illegal insn combo +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + +dbg_fail; + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + R7 += 2; // skip offending 16 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: +// (r7 - r6) = [sp++]; +// ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_bug_ui2.S b/sim/testsuite/bfin/se_bug_ui2.S new file mode 100644 index 0000000..5e0af4c --- /dev/null +++ b/sim/testsuite/bfin/se_bug_ui2.S @@ -0,0 +1,296 @@ +//Original:/proj/frio/dv/testcases/seq/se_bug_ui2/se_bug_ui2.dsp +// Description: 16 bit special cases Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // count of UI's will be in r5, which was initialized to 0 by header + +// .dw 0x41FD ; +// .dw 0x41FE ; +// .dw 0x41FF ; + .dw 0x9040 ; + .dw 0x9049 ; + .dw 0x9052 ; + .dw 0x905B ; + .dw 0x9064 ; + .dw 0x906D ; + .dw 0x9076 ; + .dw 0x907F ; + .dw 0x90C0 ; + .dw 0x90C9 ; + .dw 0x90D2 ; + .dw 0x90DB ; + .dw 0x90E4 ; + .dw 0x90ED ; + .dw 0x90F6 ; + .dw 0x90FF ; + .dw 0x9180 ; + + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +CHECKREG(r5, 17); // count of all 16 bit UI's. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 16 bit illegal opcode handler - skips bad instruction + + // handler MADE LEAN and destructive so test runs more quckly + // se_undefinedinstruction1.dsp tests using a "nice" handler + +// [--sp] = ASTAT; // save what we damage +// [--sp] = (r7 - r6); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + + R6 = 0x22; // Also accept illegal insn combo +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + +dbg_fail; + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + R7 += 2; // skip offending 16 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: +// (r7 - r6) = [sp++]; +// ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_bug_ui3.S b/sim/testsuite/bfin/se_bug_ui3.S new file mode 100644 index 0000000..3c0ff77 --- /dev/null +++ b/sim/testsuite/bfin/se_bug_ui3.S @@ -0,0 +1,300 @@ +//Original:/proj/frio/dv/testcases/seq/se_bug_ui3/se_bug_ui3.dsp +// Description: 32 bit special cases Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // count of UI's will be in r5, which was initialized to 0 by header + .dw 0xC0E0 ; + .dw 0x2000 ; + .dw 0xC140 ; + .dw 0x2000 ; + .dw 0xC1A0 ; + .dw 0x2000 ; + .dw 0xC1C0 ; + .dw 0x2000 ; + .dw 0xC1E0 ; + .dw 0x2000 ; + + .dw 0xC0E4 ; + .dw 0x0 ; + .dw 0xC144 ; + .dw 0x0 ; + .dw 0xC1A4 ; + .dw 0x0 ; + .dw 0xC1C4 ; + .dw 0x0 ; + .dw 0xC1E4 ; + .dw 0x0 ; + + .dw 0xC0E4 ; + .dw 0x2000 ; + .dw 0xC144 ; + .dw 0x2000 ; + .dw 0xC1A4 ; + .dw 0x2000 ; + .dw 0xC1C4 ; + .dw 0x2000 ; + .dw 0xC1E4 ; + .dw 0x2000 ; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +CHECKREG(r5, 15); // count of all 16 bit UI's. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 32 bit illegal opcode handler - skips bad instruction + + // handler MADE LEAN and destructive so test runs more quckly + // se_undefinedinstruction1.dsp tests using a "nice" handler + +// [--sp] = ASTAT; // save what we damage +// [--sp] = (r7 - r6); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF !CC JUMP OUT; // If EXCAUSE != 0x21 then leave + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + R7 += 4; // skip offending 32 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: +// (r7 - r6) = [sp++]; +// ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_cc2stat_haz.S b/sim/testsuite/bfin/se_cc2stat_haz.S new file mode 100644 index 0000000..7bb1a24 --- /dev/null +++ b/sim/testsuite/bfin/se_cc2stat_haz.S @@ -0,0 +1,632 @@ +//Original:/proj/frio/dv/testcases/seq/se_cc2stat_haz/se_cc2stat_haz.dsp +// Description: +// Verify CC hazards under the following condition: +// +// (1a) cc2stat (that modifies CC) followed by that uses CC +// (1b) same as (1a) but kill cc2stat instruction in WB +// +// (2a) cc2stat (that modifies CC) followed by conditional branch (predicted) +// (2b) same as (2a) but kill cc2stat instruction in WB +// +// (3a) cc2stat (that modifies CC) followed by conditional branch (mispredicted) +// (3b) same as (3a) but kill cc2stat instruction in WB +// +// (4a) cc2stat (that modifies CC) followed by testset +// (4b) same as (4a) but kill cc2stat instruction in WB +// +// (5a) cc2stat (that modifies CC) followed by dag instruction that modifies CC +// (5b) same as (5a) but kill cc2stat instruction in WB +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// ---------------------------------------------------------------- +// Include Files +// ---------------------------------------------------------------- + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +// ---------------------------------------------------------------- +// Defines +// ---------------------------------------------------------------- + +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_1 // +#endif + +// ---------------------------------------------------------------- +// Reset ISR +// - set the processor operating modes +// - initialize registers +// - etc ... +// ---------------------------------------------------------------- + +RST_ISR: + + // Initialize data registers + //INIT_R_REGS(0); + R7 = 0; + R6 = 0; + R5 = 0; + R4 = 0; + R3 = 0; + R2 = 0; + R1 = 0; + R0 = 0; + + // Initialize pointer registers +INIT_P_REGS(0); + + // Initialize address registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the address of the checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Inhibit events during MMR writes +CLI R1; + + // Setup user stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup kernel stack +LD32_LABEL(sp, KSTACK); + + // Setup frame pointer +FP = SP; + + // Setup event vector table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (EVT0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (EVT1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (EVT2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (EVT3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // EVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (EVT5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (EVT6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Set the EVT_OVERRIDE MMR +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + // Disable L1 data cache +WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0); + + // Mask interrupts (*) + R1 = -1; + + // Wait for MMR writes to finish +CSYNC; + + // Re-enable events +STI R1; + + // Reset accumulator registers + A0 = 0; + A1 = 0; + + // Reset loop counters to deterministic values + R0 = 0 (Z); + +LT0 = R0; +LB0 = R0; +LC0 = R0; +LT1 = R0; +LB1 = R0; +LC1 = R0; + + // Reset other internal regs +ASTAT = R0; +SYSCFG = R0; +RETS = R0; + + // Setup the test to run in USER mode +LD32_LABEL(r0, USER_CODE); +RETI = R0; + + // Setup the test to run in SUPERVISOR mode + // Comment the following line for a USER mode test +JUMP.S SUPERVISOR_CODE; +RTI; + +SUPERVISOR_CODE: + // Load IVG15 general handler (Int15) with MAIN_CODE +LD32_LABEL(p1, MAIN_CODE); + +LD32(p0, EVT15); + +CLI R1; + [ P0 ] = P1; +CSYNC; +STI R1; + + // Take Int15 which branch to MAIN_CODE after RTI +RAISE 15; +RTI; + +USER_CODE: + // Setup the stack pointer and the frame pointer +LD32_LABEL(sp, USTACK); +FP = SP; +JUMP.S MAIN_CODE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// ISR Table +// ---------------------------------------------------------------- + + +// ---------------------------------------------------------------- +// EMU ISR +// ---------------------------------------------------------------- + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// NMI ISR +// ---------------------------------------------------------------- + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// EXC ISR +// ---------------------------------------------------------------- + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// HWE ISR +// ---------------------------------------------------------------- + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// TMR ISR +// ---------------------------------------------------------------- + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV7 ISR +// ---------------------------------------------------------------- + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV8 ISR +// ---------------------------------------------------------------- + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV9 ISR +// ---------------------------------------------------------------- + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV10 ISR +// ---------------------------------------------------------------- + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV11 ISR +// ---------------------------------------------------------------- + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV12 ISR +// ---------------------------------------------------------------- + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV13 ISR +// ---------------------------------------------------------------- + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV14 ISR +// ---------------------------------------------------------------- + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV15 ISR +// ---------------------------------------------------------------- + + IGV15_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// Main Code +// ---------------------------------------------------------------- + + +MAIN_CODE: + // Enable interrupts in SUPERVISOR mode + // Comment the following line for a USER mode test + [ -- SP ] = RETI; + + // Start of the program code + R0 = 0; + R1 = 1; + R2 = 2; + + // Verify CC hazards under the following condition: + // + // (1a) cc2stat (that modifies CC) followed by that uses CC + A0 = 0; + A1 = R1; +CC = R0 < R2; +CC = AV0; + A0 = BXORSHIFT( A0 , A1, CC ); + R7 = CC; CHECKREG(R7, 0); + R6 = A0; CHECKREG(R6, 0); + R6 = A0.X; CHECKREG(R6, 0); + R7 = A1; CHECKREG(R7, 1); + R7 = A1.X; CHECKREG(R7, 0); + + // (1b) same as (1a) but kill cc2stat instruction in WB + A0 = R1; + A1 = R1; +CC = R0 < R2; +EXCPT 3; +CC = AV0; + A0 = BXORSHIFT( A0 , A1, CC ); + R7 = CC; CHECKREG(R7, 0); + R6 = A0; CHECKREG(R6, 3); + R6 = A0.X; CHECKREG(R6, 0); + R7 = A1; CHECKREG(R7, 1); + R7 = A1.X; CHECKREG(R7, 0); + + // (2a) cc2stat (that modifies CC) followed by conditional branch (predicted) + R3 = 0; + A0 = 0; + A1 = R1; +CC = R0 < R2; +CC = AV0; +IF !CC JUMP INC_R3_TO_10 (BP); + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; +INC_R3_TO_10: + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + + // (2b) same as (2a) but kill cc2stat instruction in WB + A0 = 0; + A1 = R1; +CC = R0 < R2; +EXCPT 3; +CC = AV0; +IF !CC JUMP INC_R3_TO_20 (BP); + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; +INC_R3_TO_20: + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + + // (3a) cc2stat (that modifies CC) followed by conditional branch (mispredicted) + A0 = 0; + A1 = R1; +CC = R0 < R2; +CC = AV0; +IF CC JUMP INC_R3_TO_20 (BP); + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + + // (3b) same as (3a) but kill cc2stat instruction in WB + A0 = 0; + A1 = R1; +CC = R0 < R2; +EXCPT 3; +CC = AV0; +IF CC JUMP INC_R3_TO_20 (BP); + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + +CHECKREG(r3, 60); + +dbg_pass; + + // (4a) cc2stat (that modifies CC) followed by testset +LD32(p0, DATA_ADDR_3); //LD32(p0, 0xff000000); +LD32(p1, DATA_ADDR_2); //LD32(p1, 0xffe00000); + [ P0 ] = R0; + + A0 = 0; + A1 = R1; +CC = R0 < R2; +CC = AV0; +QUERY_0: +TESTSET ( P0 ); +IF !CC JUMP QUERY_0; + [ P0 ] = R1; +CHECKMEM32(DATA_ADDR_3, 1); //CHECKMEM32(0xff000000, 1); + [ P0 ] = R0; +CHECKMEM32(DATA_ADDR_3, 0); //CHECKMEM32(0xff000000, 0); + + // (4b) same as (4a) but kill cc2stat instruction in WB + A0 = 0; + A1 = R1; +CC = R0 < R2; +EXCPT 3; +CC = AV0; +QUERY_1: +TESTSET ( P0 ); +IF !CC JUMP QUERY_1; + [ P0 ] = R2; +CHECKMEM32(DATA_ADDR_3, 2); //CHECKMEM32(0xff000000, 2); + [ P0 ] = R0; +CHECKMEM32(DATA_ADDR_3, 0); //CHECKMEM32(0xff000000, 0); + + // (5a) cc2stat (that modifies CC) followed by dag instruction that modifies CC + A0 = 0; + A1 = R1; +CC = R0 < R2; +CC = AV0; +CC = P0 < P1; + + // (5b) same as (5a) but kill cc2stat instruction in WB + A0 = 0; + A1 = R1; +CC = R0 < R2; +EXCPT 3; +CC = AV0; +CC = P0 < P1; + + +END: +dbg_pass; + +// ---------------------------------------------------------------- +// Data Segment +// - define kernel and user stacks +// ---------------------------------------------------------------- + +.data + DATA: + .space (STACKSIZE); + + .space (STACKSIZE); + KSTACK: + + .space (STACKSIZE); + USTACK: diff --git a/sim/testsuite/bfin/se_cc_kill.S b/sim/testsuite/bfin/se_cc_kill.S new file mode 100644 index 0000000..5d0aead --- /dev/null +++ b/sim/testsuite/bfin/se_cc_kill.S @@ -0,0 +1,480 @@ +//Original:/proj/frio/dv/testcases/seq/se_cc_kill/se_cc_kill.dsp +// Description: +// Verify CC kill under the following condition: +// +// (1) CC = AZ killed in WB +// (2) CC = AN killed in WB +// (3) CC = AC killed in WB +// (4) CC = AV0 killed in WB +// (5) CC = AV1 killed in WB +// (6) CC = AQ killed in WB +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// ---------------------------------------------------------------- +// Include Files +// ---------------------------------------------------------------- + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +// ---------------------------------------------------------------- +// Defines +// ---------------------------------------------------------------- + +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_1 // +#endif + + +// ---------------------------------------------------------------- +// Reset ISR +// - set the processor operating modes +// - initialize registers +// - etc ... +// ---------------------------------------------------------------- + +RST_ISR: + + // Initialize data registers + //INIT_R_REGS(0); + R7 = 0; + R6 = 0; + R5 = 0; + R4 = 0; + R3 = 0; + R2 = 0; + R1 = 0; + R0 = 0; + + // Initialize pointer registers +INIT_P_REGS(0); + + // Initialize address registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the address of the checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Inhibit events during MMR writes +CLI R1; + + // Setup user stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup kernel stack +LD32_LABEL(sp, KSTACK); + + // Setup frame pointer +FP = SP; + + // Setup event vector table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (EVT0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (EVT1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (EVT2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (EVT3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // EVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (EVT5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (EVT6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Set the EVT_OVERRIDE MMR +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + // Disable L1 data cache +WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0); + + // Mask interrupts (*) + R1 = -1; + + // Wait for MMR writes to finish +CSYNC; + + // Re-enable events +STI R1; + + // Reset loop counters to deterministic values + R0 = 0 (Z); + +LT0 = R0; +LB0 = R0; +LC0 = R0; +LT1 = R0; +LB1 = R0; +LC1 = R0; + + // Reset other internal regs +ASTAT = R0; +SYSCFG = R0; +RETS = R0; + + // Setup the test to run in USER mode +LD32_LABEL(r0, USER_CODE); +RETI = R0; + + // Setup the test to run in SUPERVISOR mode + // Comment the following line for a USER mode test +JUMP.S SUPERVISOR_CODE; +RTI; + +SUPERVISOR_CODE: + // Load IVG15 general handler (Int15) with MAIN_CODE +LD32_LABEL(p1, MAIN_CODE); + +LD32(p0, EVT15); + +CLI R1; + [ P0 ] = P1; +CSYNC; +STI R1; + + // Take Int15 which branch to MAIN_CODE after RTI +RAISE 15; +RTI; + +USER_CODE: + // Setup the stack pointer and the frame pointer +LD32_LABEL(sp, USTACK); +FP = SP; +JUMP.S MAIN_CODE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// ISR Table +// ---------------------------------------------------------------- + + +// ---------------------------------------------------------------- +// EMU ISR +// ---------------------------------------------------------------- + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// NMI ISR +// ---------------------------------------------------------------- + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// EXC ISR +// ---------------------------------------------------------------- + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// HWE ISR +// ---------------------------------------------------------------- + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// TMR ISR +// ---------------------------------------------------------------- + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV7 ISR +// ---------------------------------------------------------------- + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV8 ISR +// ---------------------------------------------------------------- + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV9 ISR +// ---------------------------------------------------------------- + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV10 ISR +// ---------------------------------------------------------------- + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV11 ISR +// ---------------------------------------------------------------- + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV12 ISR +// ---------------------------------------------------------------- + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV13 ISR +// ---------------------------------------------------------------- + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV14 ISR +// ---------------------------------------------------------------- + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV15 ISR +// ---------------------------------------------------------------- + + IGV15_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// Main Code +// ---------------------------------------------------------------- + + +MAIN_CODE: + // Enable interrupts in SUPERVISOR mode + // Comment the following line for a USER mode test + [ -- SP ] = RETI; + + // Start of the program code + + // Verify CC kill under the following condition: + + // (1) CC = AZ killed in WB +CC = R2 < R3; +EXCPT 3; +CC = AZ; + + // (2) CC = AN killed in WB +CC = R2 == R3; +EXCPT 3; +CC = AN; + + // (3) CC = AC killed in WB +CC = R2 < R3; +EXCPT 3; +CC = AC0; + + // (4) CC = AV0 killed in WB +CC = R2 == R3; +EXCPT 3; +CC = AV0; + + // (5) CC = AV1 killed in WB +CC = R2 == R3; +EXCPT 3; +CC = AV1; + + // (6) CC = AQ killed in WB +CC = R2 == R3; +EXCPT 3; +CC = AQ; + + +END: +dbg_pass; + +// ---------------------------------------------------------------- +// Data Segment +// - define kernel and user stacks +// ---------------------------------------------------------------- + +.data + DATA: + .space (STACKSIZE); + + .space (STACKSIZE); + KSTACK: + + .space (STACKSIZE); + USTACK: diff --git a/sim/testsuite/bfin/se_cof.S b/sim/testsuite/bfin/se_cof.S new file mode 100644 index 0000000..4802cce --- /dev/null +++ b/sim/testsuite/bfin/se_cof.S @@ -0,0 +1,424 @@ +//Original:/proj/frio/dv/testcases/seq/se_cof/se_cof.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +NOP; + //lz(p0) = 0x0004; + //h(p0) = 0xffe0; +LD32(p0, DMEM_CONTROL); +CSYNC; + R0 = [ P0 ]; // MMR load will Stall +JUMP.S lab1; // Branch in EX1 + + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +lab1: + [ -- SP ] = ( R7:3 ); +IF !CC JUMP 2; // Mispredicted branch; +NOP; +JUMP.S lab2; // Branch in EX1 +NOP; +NOP; +NOP; +NOP; + +lab2: +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_3 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_3 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_event_quad.S b/sim/testsuite/bfin/se_event_quad.S new file mode 100644 index 0000000..0a1611b --- /dev/null +++ b/sim/testsuite/bfin/se_event_quad.S @@ -0,0 +1,436 @@ +//Original:/proj/frio/dv/testcases/seq/se_event_quad/se_event_quad.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + + P0 = 0x5 (Z); + P1 = 0xa (Z); + + P2 = 0x0100 (Z); + P2.H = 0x00f0; + R0 = 0xf0f0 (Z); + R0.H = 0x0f0f; + +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; + +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_excpt_dagprotviol.S b/sim/testsuite/bfin/se_excpt_dagprotviol.S new file mode 100644 index 0000000..48e496b --- /dev/null +++ b/sim/testsuite/bfin/se_excpt_dagprotviol.S @@ -0,0 +1,281 @@ +//Original:/proj/frio/dv/testcases/seq/se_excpt_dagprotviol/se_excpt_dagprotviol.dsp +// Description: EXCPT instruction combined with DAG Misaligned Access +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x100 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +RETI = r0; // prevent Xs later on +RETX = r0; +RETN = r0; +RETE = r0; + + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +FP = SP; +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests +// [--sp] = RETI; // enable interrupts in supervisor mode + + R0 = 0; + R1 = -1; +LD32_LABEL(p1, USTACK); + P1 += 1; // misalign it + +EXCPT 2; // the RAISE should not prevent the EXCPT from being taken + R2 = [ P1 ]; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + +CHECKREG(r5, 2); // check the flag + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 instruction +CC = r7 == r6; +IF CC JUMP EXCPT2; + + R6 = 0x24; // EXCAUSE 0x24 means DAG misalign +CC = r7 == r6; +IF CC JUMP DGPROTVIOL; + +JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop + +EXCPT2: + R5 = 1; // Set a Flag +JUMP.S OUT; + +DGPROTVIOL: + R7 = RETX; // Fix up return address + + R7 += 2; // skip offending 16 bit instruction + +RETX = r7; // and put back in RETX + + R5 <<= 1; // Alter Global Flag + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_excpt_ifprotviol.S b/sim/testsuite/bfin/se_excpt_ifprotviol.S new file mode 100644 index 0000000..50207fc --- /dev/null +++ b/sim/testsuite/bfin/se_excpt_ifprotviol.S @@ -0,0 +1,280 @@ +//Original:/proj/frio/dv/testcases/seq/se_excpt_ifprotviol/se_excpt_ifprotviol.dsp +// Description: EXCPT instruction and IF Prot Viol priority +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x100 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +RETI = r0; // prevent Xs later on +RETX = r0; +RETN = r0; +RETE = r0; + + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +FP = SP; +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests +// [--sp] = RETI; // enable interrupts in supervisor mode + + R0 = 0; + R1 = -1; + + +EXCPT 2; // the RAISE should not prevent the EXCPT from being taken +RAISE 15; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + +CHECKREG(r5, 2); // check the flag + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 instruction +CC = r7 == r6; +IF CC JUMP EXCPT2; + + R6 = 0x2E; // EXCAUSE 0x2E means Illegal Use Supervisor Resource +CC = r7 == r6; +IF CC JUMP IFPROTVIOL; + +JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop + +EXCPT2: + R5 = 1; // Set a Flag +JUMP.S OUT; + +IFPROTVIOL: + R7 = RETX; // Fix up return address + + R7 += 2; // skip offending 16 bit instruction + +RETX = r7; // and put back in RETX + + R5 <<= 1; // Alter Global Flag + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_excpt_ssstep.S b/sim/testsuite/bfin/se_excpt_ssstep.S new file mode 100644 index 0000000..5cb5558 --- /dev/null +++ b/sim/testsuite/bfin/se_excpt_ssstep.S @@ -0,0 +1,290 @@ +//Original:/proj/frio/dv/testcases/seq/se_excpt_ssstep/se_excpt_ssstep.dsp +// Description: EXCPT instruction vs Single Step Exception Priority +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +//include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + + R0 = 1; + +SYSCFG = r0; // Enable Supervisor Single Step + +CHECK_INIT_DEF(p2); //CHECK_INIT(p2, 0x2000); + + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// + +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests +// [--sp] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + R0 = 0; + R0 = 0; + R0 = 0; + R0 = 0; + R0 = 0; +EXCPT 15; // single step shouldn't happen for this. + R0 = 0; + R0 = 0; + R0 = 0; + R0 = 0; + R0 = 0; + +EXCPT 3; // turn off single step via handler + +CHECKREG(r4, 1); // one EXCPT 15 instruction +CHECKREG(r5, 14); // 14 instructions are executed before we disable single step + + + // PUT YOUR TEST HERE! + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x10; // EXCAUSE 0x10 means Single Step +CC = r7 == r6; +IF CC JUMP SINGLESTEP (BP); // Go to Single Step Handler + + R6 = 15; // EXCAUSE 15 means EXCPT 15 instruction +CC = r7 == r6; +IF CC JUMP EXCPT15 (BP); + +SYSCFG = r0; // otherwise must be an EXCPT, so turn off singlestep + +JUMP.S OUT; + +EXCPT15: + R4 += 1; // R4 counts EXCPT 15s +JUMP.S OUT; + +SINGLESTEP: + R5 += 1; // R5 counts single step events + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_illegalcombination.S b/sim/testsuite/bfin/se_illegalcombination.S new file mode 100644 index 0000000..0fe5f27 --- /dev/null +++ b/sim/testsuite/bfin/se_illegalcombination.S @@ -0,0 +1,622 @@ +//Original:/proj/frio/dv/testcases/seq/se_illegalcombination/se_illegalcombination.dsp +// Description: Multi-issue Illegal Combinations +# mach: bfin +# sim: --environment operating +# xfail: "missing a few checks; hardware doesnt seem to match PRM?" bfin-* + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x100 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + A0 = 0; // reset accumulators + A1 = 0; + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // PUT YOUR TEST HERE! + +// Slot 0 can only be LDST LOAD with search instruction (2 instrs) + + + .dw 0xcc0d //(R0,R1)=SEARCH R2(GT)||[P0]=R3||NOP; + .dw 0x0210 + .dw 0x9303 + .dw 0x0000 +// (r0,r1) = search r2 gt, nop, r3 = [i0]; // nop supposedly ok +( R0 , R1 ) = SEARCH R2 (GT) || R4 = [ P0 ++ P1 ] || NOP; + +// only nop or dspLDST allowed in slot 1 (1 instr) + + // a0 = r0, nop, [p0] = r3; + .dw 0xCC09; // can't assemble + .dw 0x2000; + .dw 0x0000; + .dw 0x9303; + +// Slot 0 illegal opcodes (1 instr) + + // a0 = r0, raise 15, nop; + .dw 0xCC09; // can't assemble + .dw 0x2000; + .dw 0x009F; + .dw 0x0000; + +// multiissue with two stores (8 instrs) + + + .dw 0xcc09 //A0=R0||W[P3]=R5.L||[I0]=R4; + .dw 0x2000 + .dw 0x8b5b + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[I2]=R2||[I0]=R4; + .dw 0x2000 + .dw 0x9f12 + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[P3]=R0||[I0]=R4; + .dw 0x2000 + .dw 0x9318 + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[P3]=P0||[I0]=R4; + .dw 0x2000 + .dw 0x9358 + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[FP+-36]=R0||[I0]=R4; + .dw 0x2000 + .dw 0xbb70 + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[FP+-48]=P0||[I0]=R4; + .dw 0x2000 + .dw 0xbb48 + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[P3+0x20]=R1||[I0]=R4; + .dw 0x2000 + .dw 0xb219 + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[P3+0x20]=P1||[I0]=R4; + .dw 0x2000 + .dw 0xbe19 + .dw 0x9f04 + +// multiissue two instructions can't modify same ireg (6 instrs) + + + .dw 0xcc09 //A0=R0||I0+=M1(BREV)||R1.L=W[I0++]; + .dw 0x2000 + .dw 0x9ee4 + .dw 0x9c21 + + .dw 0xcc09 //A0=R0||I1-=M3||R0=[I1++M3]; + .dw 0x2000 + .dw 0x9e7d + .dw 0x9de8 + + .dw 0xcc09 //A0=R0||I2+=2||W[I2++]=R0.L; + .dw 0x2000 + .dw 0x9f62 + .dw 0x9e30 + + .dw 0xcc09 //A0=R0||I3-=4||[I3++M1]=R7; + .dw 0x2000 + .dw 0x9f6f + .dw 0x9fbf + + .dw 0xcc09 //A0=R0||R1.L=W[I1++]||W[I1++]=R2.L; + .dw 0x2000 + .dw 0x9c29 + .dw 0x9e2a + + .dw 0xcc09 //A0=R0||[I2++M3]=R7||R6=[I2++M0]; + .dw 0x2000 + .dw 0x9ff7 + .dw 0x9d96 + +// multiissue two instructions can't load same dreg (9 instrs) + + + .dw 0xcc09 //A0=R0||R0.L=W[P0++P2]||R0=[I0++]; + .dw 0x2000 + .dw 0x8210 + .dw 0x9c00 + + .dw 0xcc09 //A0=R0||R1=W[P0++P3](X)||R1.L=W[I2]; + .dw 0x2000 + .dw 0x8e58 + .dw 0x9d31 + + .dw 0xcc09 //A0=R0||R2=W[P0++P3](X)||R2=[I1++M3]; + .dw 0x2000 + .dw 0x8e98 + .dw 0x9dea + + .dw 0xcc09 //A0=R0||R3=[I0++]||R3=[I1++]; + .dw 0x2000 + .dw 0x9c03 + .dw 0x9c0b + + .dw 0xcc09 //A0=R0||R4.L=W[I2]||R4.L=W[I3]; + .dw 0x2000 + .dw 0x9d34 + .dw 0x9d3c + + .dw 0xcc09 //A0=R0||R5=[I1++M3]||R5.L=W[I2++]; + .dw 0x2000 + .dw 0x9ded + .dw 0x9c35 + + .dw 0xcc09 //A0=R0||R6=[P0]||R6=[I0++]; + .dw 0x2000 + .dw 0x9106 + .dw 0x9c06 + + .dw 0xcc09 //A0=R0||R7=[FP+-56]||R7.L=W[I1]; + .dw 0x2000 + .dw 0xb927 + .dw 0x9d2f + + .dw 0xcc09 //A0=R0||R0=W[P1+0x1e](X)||R0=[I0++]; + .dw 0x2000 + .dw 0xabc8 + .dw 0x9c00 + +// dsp32alu instructions with one dest and slot 0 multi with same dest (1 ins) + + + .dw 0xcc00 //R0=R2+|+R3||R0=W[P1+0x1e](X)||NOP; + .dw 0x0013 + .dw 0xabc8 + .dw 0x0000 + // other slot 0 dreg cases already covered + +// dsp32alu one dest and slot 1 multi with same dest (1 ins) + + + .dw 0xcc18 //R1=BYTEPACK(R4,R5)||NOP||R1.L=W[I2]; + .dw 0x0225 + .dw 0x0000 + .dw 0x9d31 + // other slot 1 dreg dest cases already covered + +// dsp32alu dual dests and slot 0 multi with either same dest (2 instrs) + + + .dw 0xcc18 //(R2,R3)=BYTEUNPACKR1:0||R2=W[P0++P3](X)||NOP; + .dw 0x4680 + .dw 0x8e98 + .dw 0x0000 + + .dw 0xcc01 //R2=R2+|+R3,R3=R2-|-R3||R3=[P3]||NOP; + .dw 0x0693 + .dw 0x911b + .dw 0x0000 + +// dsp32alu dual dests and slot 1 multi with either same dest (2 instrs) + + + .dw 0xcc18 //(R4,R5)=BYTEUNPACKR1:0||NOP||R4=[I1++M3]; + .dw 0x4b00 + .dw 0x0000 + .dw 0x9dec + + .dw 0xcc01 //R4=R2+|+R3,R5=R2-|-R3||NOP||R5.L=W[I2++]; + .dw 0x0b13 + .dw 0x0000 + .dw 0x9c35 + +// dsp32shift one dest and slot 0 multi with same dest (1 instruction) + + + .dw 0xce0d //R6=ALIGN8(R4,R5)||R6=[P0]||NOP; + .dw 0x0c2c + .dw 0x9106 + .dw 0x0000 + +// dsp32shift one dest and slot 1 multi with same dest (1 instruction) + + + .dw 0xce00 //R7.L=ASHIFTR0.HBYR7.L||NOP||R7.L=W[I1]; + .dw 0x1e38 + .dw 0x0000 + .dw 0x9d2f + +// dsp32shift two dests and slot 0 multi with either same dest (2 instrs) + + + .dw 0xce08 //BITMUX(R0,R1,A0)(ASR)||R0.L=W[P0++P2]||NOP; + .dw 0x0001 + .dw 0x8210 + .dw 0x0000 + + .dw 0xce08 //BITMUX(R2,R3,A0)(ASL)||R3=[I0++]||NOP; + .dw 0x4013 + .dw 0x9c03 + .dw 0x0000 + +// dsp32shift two dests and slot 1 multi with either same dest (2 instrs) + + + .dw 0xce08 //BITMUX(R4,R5,A0)(ASR)||NOP||R4.H=W[I3]; + .dw 0x0025 + .dw 0x0000 + .dw 0x9d5c + + .dw 0xce08 //BITMUX(R6,R7,A0)(ASL)||NOP||R7.L=W[I1]; + .dw 0x4037 + .dw 0x0000 + .dw 0x9d2f + +// dsp32shiftimm one dest and slot 0 with same dest (1 instr) + + + .dw 0xce80 //R1.L=R0.H<<0x7||R1=W[P0++P3](X)||NOP; + .dw 0x1238 + .dw 0x8e58 + .dw 0x0000 + +// dsp32shiftimm one dest and slot 1 with same dest (1 instr) + + + .dw 0xce81 //R5=R2<<0x9(V)||NOP||R5.L=W[I2++]; + .dw 0x0a4a + .dw 0x0000 + .dw 0x9c35 + +// dsp32mac one dest and slot 0 multi with same dest (1 inst) + + + .dw 0xc805 //A0+=R1.H*R0.L,R6.H=(A1+=R1.L*R0.H)||R6=W[P0++P3](X)||NOP; + .dw 0x4d88 + .dw 0x8f98 + .dw 0x0000 + +// dsp32mult one dest and slot 0 multi with same dest (1 inst) + + + .dw 0xca04 //R7.H=R3.L*R4.H||R7=[FP+-56]||NOP; + .dw 0x41dc + .dw 0xb927 + .dw 0x0000 + +// dsp32 mac one dest and slot 1 multi with same dest (1 inst) + + + .dw 0xc805 //A0+=R1.H*R0.L,R0.H=(A1+=R1.L*R0.H)||NOP||R0=[I0++]; + .dw 0x4c08 + .dw 0x0000 + .dw 0x9c00 + +// dsp32mult one dest and slot 1 multi with same dest (1 inst) + + + .dw 0xca04 //R1.H=R3.L*R4.H||NOP||R1.H=W[I1]; + .dw 0x405c + .dw 0x0000 + .dw 0x9d49 + +// dsp32mac write to register pair and slot 0 same dest - even (1 instr) + + + .dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||R2=W[P0++P3](X)||NOP; + .dw 0x6c88 + .dw 0x8e98 + .dw 0x0000 + +// dsp32mult write to register pair and slot 0 same dest - even (1 instr) + + + .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R4=[P0++P1]||NOP; + .dw 0x6508 + .dw 0x8108 + .dw 0x0000 + +// dsp32mac write to register pair and slot 1 same dest - even (1 instr) + + + .dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||NOP||R2=[I1++M3]; + .dw 0x6c88 + .dw 0x0000 + .dw 0x9dea + +// dsp32mult write to register pair and slot 1 same dest - even (1 instr) + + + .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R4=[I1++M3]; + .dw 0x6508 + .dw 0x0000 + .dw 0x9dec + +// dsp32mac write to register pair and slot 0 same dest - odd (1 instr) + + + .dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||R3=W[P0++P3](X)||NOP; + .dw 0x4c88 + .dw 0x8ed8 + .dw 0x0000 + +// dsp32mult write to register pair and slot 0 same dest - odd (1 instr) + + + .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R5=[P0++P1]||NOP; + .dw 0x6508 + .dw 0x8148 + .dw 0x0000 + +// dsp32mac write to register pair and slot 1 same dest - odd (1 instr) + + + .dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||NOP||R3=[I1++M3]; + .dw 0x4c88 + .dw 0x0000 + .dw 0x9deb + +// dsp32mult write to register pair and slot 1 same dest - odd (1 instr) + + + .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R5=[I1++M3]; + .dw 0x6508 + .dw 0x0000 + .dw 0x9ded + +// CHECKER + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x22; +CHECKREG(r5, 53); // count of all Illegal Combination Exceptions. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 16 bit illegal opcode handler - skips bad instruction + + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x22; // EXCAUSE 0x22 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP ILLEGALCOMBINATION; // If EXCAUSE != 0x22 then leave + +dbg_fail; +JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop + +ILLEGALCOMBINATION: + R7 = RETX; // Fix up return address + + R7 += 8; // skip offending 64 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_kill_wbbr.S b/sim/testsuite/bfin/se_kill_wbbr.S new file mode 100644 index 0000000..80ec7d1 --- /dev/null +++ b/sim/testsuite/bfin/se_kill_wbbr.S @@ -0,0 +1,422 @@ +//Original:/proj/frio/dv/testcases/seq/se_kill_wbbr/se_kill_wbbr.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Load RETS +LD32_LABEL(r0, USER_CODE); +RETS = R0; + + // Return to Supervisor Code +RAISE 2; +RAISE 5; +RAISE 6; +RAISE 7; +RAISE 8; +RAISE 9; +RAISE 10; +RAISE 11; +RAISE 12; +RAISE 13; +RAISE 14; +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; +IF !CC JUMP 2; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; +NOP; +IF !CC JUMP 2; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; +CSYNC; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; +NOP; +CSYNC; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; +SSYNC; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; +NOP; +SSYNC; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; +NOP; +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; +NOP; +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +RTI; +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +EXCPT 0x5; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_2 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_2 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.section MEM_(DATA_ADDR_2 + 0x110) //.data 0x00F00210,"aw" + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_kills2.S b/sim/testsuite/bfin/se_kills2.S new file mode 100644 index 0000000..73f9d28 --- /dev/null +++ b/sim/testsuite/bfin/se_kills2.S @@ -0,0 +1,148 @@ +//Original:/proj/frio/dv/testcases/seq/se_kills2/se_kills2.dsp +// Description: Test se_kill for all supported types of RTL1 instructions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(selfcheck.inc) +include(std.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +SP = 0 (Z); +SP.L = KSTACK; // setup the stack pointer +SP.H = KSTACK; +FP = SP; // and frame pointer + +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +ASTAT = r0; // reset sequencer registers + +// +// The Main Program +// + +START: + + // **** YOUR CODE GOES HERE **** + // CHECK_INIT(p0, 0xFF7FFFFC); // original +CHECK_INIT_DEF(p0); + + R0 = 0; + R1 = 1; + R2 = 2; + R3 = 3; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + P1 = 11; + // Assume CC is reset to 0. +IF !CC JUMP NEXT1; // following instruction should be killed +RAISE 13; + +NEXT1: + IF !CC JUMP NEXT2; +EXCPT 15; + +NEXT2: + IF !CC JUMP NEXT3; + ( R7:0, P5:0 ) = [ SP ++ ]; + +NEXT3: + IF !CC JUMP NEXT4; + [ -- SP ] = ( R7:0, P5:0 ); + +NEXT4: + IF !CC JUMP NEXT5; +EMUEXCPT; + +NEXT5: + IF !CC JUMP NEXT6; +.dd 0xFACEBABE + +NEXT6: + IF !CC JUMP NEXT7; +LINK 12; + +NEXT7: + IF !CC JUMP NEXT8; +UNLINK; + +NEXT8: + IF !CC JUMP NEXT9; +LSETUP (NEXT10, NEXT11) lc0 = p0; + +NEXT9: + IF !CC JUMP NEXT10; + +NEXT10: + IF !CC JUMP NEXT11; + +NEXT11: + IF !CC JUMP NEXT12; + +NEXT12: + IF !CC JUMP NEXT13; + +NEXT13: + IF !CC JUMP NEXT14; + +NEXT14: + IF !CC JUMP NEXT15; + +NEXT15: + IF !CC JUMP NEXT16; + +NEXT16: + +END: +CHECKREG(r0, 0); +CHECKREG(r1, 1); +CHECKREG(r2, 2); +CHECKREG(r3, 3); +CHECKREG(r4, 4); +CHECKREG(r5, 5); +CHECKREG(r6, 6); +CHECKREG(r7, 7); + +dbg_pass; // Call Endtest Macro + +//********************************************************************* +// +// Data Segment +// + +//.data 0xF0000000 +.data +DATA: + .space (0x010); // Some data space + +// Stack Segments + + .space (STACKSIZE); +KSTACK: diff --git a/sim/testsuite/bfin/se_loop_disable.S b/sim/testsuite/bfin/se_loop_disable.S new file mode 100644 index 0000000..3b84d8c --- /dev/null +++ b/sim/testsuite/bfin/se_loop_disable.S @@ -0,0 +1,408 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_disable/se_loop_disable.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + +LSETUP ( 1f , 1f ) LC0 = P1; +1:R7 += 1; +LSETUP ( 1f , 1f ) LC0 = P1; +1:R6 += 1; +LC0 = P0; +LD32_LABEL(r0, l0t); +LD32_LABEL(r1, l0b); +LT0 = r0; +LB0 = r1; +l0t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l0b:R2 += 2; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_3 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_( DATA_ADDR_3 + 100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.section MEM_( DATA_ADDR_3 + 110) //.data 0x00F00210,"aw" + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_kill.S b/sim/testsuite/bfin/se_loop_kill.S new file mode 100644 index 0000000..6a2b633 --- /dev/null +++ b/sim/testsuite/bfin/se_loop_kill.S @@ -0,0 +1,519 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_kill/se_loop_kill.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + P2 = 0x0200 (Z); + P2.H = 0x00F0; + [ -- SP ] = P0; + [ -- SP ] = P0; +SSYNC; + +LD32_LABEL(r0, l0t); +LD32_LABEL(r1, l0b); +LT0 = r0; +LB0 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 +NOP; +LC0 = P0; +l0t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l0b:R2 += 2; + +LD32_LABEL(r0, l2t); +LD32_LABEL(r1, l2b); +LT0 = r0; +LB0 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 when stalled +LC0 = [ SP ++ ]; +l2t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l2b:R2 += 2; + +LD32_LABEL(r0, l1t); +LD32_LABEL(r1, l1b); +LT1 = r0; +LB1 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 when stalled +LC1 = [ SP ++ ]; +l1t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l1b:R2 += 2; + +LD32_LABEL(r0, l3t); +LD32_LABEL(r1, l3b); +LT1 = r0; +LB1 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 +NOP; +LC1 = P0; +l3t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l3b:R2 += 2; + +EXCPT 0x6; // Will kill Lsetup in EX2 +NOP; +NOP; +LSETUP ( l1e , l1e ) LC0 = P1; +l1e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX2 +NOP; +NOP; +LSETUP ( m1e , m1e ) LC1 = P1; +m1e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 +NOP; +NOP; +NOP; +LSETUP ( l2e , l2e ) LC0 = P1; +l2e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 +NOP; +NOP; +NOP; +LSETUP ( m2e , m2e ) LC1 = P1; +m2e:R7 += 1; + +NOP; +NOP; +NOP; + +EXCPT 0x6; // Will kill Lsetup in EX2 when stalled + R0 = [ P2 ++ ]; +LSETUP ( l3e , l3e ) LC0 = P1; +l3e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX2 when stalled + R0 = [ P2 ++ ]; +LSETUP ( m3e , m3e ) LC1 = P1; +m3e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 when stalled + R0 = [ P2 ++ ]; +NOP; +LSETUP ( l4e , l4e ) LC0 = P1; +l4e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 when stalled + R0 = [ P2 ++ ]; +NOP; +LSETUP ( m4e , m4e ) LC1 = P1; +m4e:R7 += 1; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_0x00F00200,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_kill_01.S b/sim/testsuite/bfin/se_loop_kill_01.S new file mode 100644 index 0000000..55b6273 --- /dev/null +++ b/sim/testsuite/bfin/se_loop_kill_01.S @@ -0,0 +1,521 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_kill_01/se_loop_kill_01.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + P2 = 0x0200 (Z); + P2.H = 0x00F0; + [ -- SP ] = P0; + [ -- SP ] = P0; +SSYNC; + +LD32_LABEL(r0, l0t); +LD32_LABEL(r1, l0b); + [ -- SP ] = R0; + [ -- SP ] = R1; +SSYNC; +LB0 = [sp++]; +EXCPT 0x5; // Will kill mv2lc in EX3 +LC0 = P0; +LT0 = [sp++]; +l0t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l0b:R2 += 2; + +LD32_LABEL(r0, l2t); +LD32_LABEL(r1, l2b); +LT0 = r0; +LB0 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 when stalled +LC0 = [ SP ++ ]; +l2t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l2b:R2 += 2; + +LD32_LABEL(r0, l1t); +LD32_LABEL(r1, l1b); +LT1 = r0; +LB1 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 when stalled +LC1 = [ SP ++ ]; +l1t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l1b:R2 += 2; + +LD32_LABEL(r0, l3t); +LD32_LABEL(r1, l3b); +LT1 = r0; +LB1 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 +NOP; +LC1 = P0; +l3t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l3b:R2 += 2; + +EXCPT 0x6; // Will kill Lsetup in EX2 +NOP; +NOP; +LSETUP ( l1e , l1e ) LC0 = P1; +l1e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX2 +NOP; +NOP; +LSETUP ( m1e , m1e ) LC1 = P1; +m1e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 +NOP; +NOP; +NOP; +LSETUP ( l2e , l2e ) LC0 = P1; +l2e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 +NOP; +NOP; +NOP; +LSETUP ( m2e , m2e ) LC1 = P1; +m2e:R7 += 1; + +NOP; +NOP; +NOP; + +EXCPT 0x6; // Will kill Lsetup in EX2 when stalled + R0 = [ P2 ++ ]; +LSETUP ( l3e , l3e ) LC0 = P1; +l3e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX2 when stalled + R0 = [ P2 ++ ]; +LSETUP ( m3e , m3e ) LC1 = P1; +m3e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 when stalled + R0 = [ P2 ++ ]; +NOP; +LSETUP ( l4e , l4e ) LC0 = P1; +l4e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 when stalled + R0 = [ P2 ++ ]; +NOP; +LSETUP ( m4e , m4e ) LC1 = P1; +m4e:R7 += 1; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_0x00F00200,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_kill_dcr.S b/sim/testsuite/bfin/se_loop_kill_dcr.S new file mode 100644 index 0000000..13bf16a --- /dev/null +++ b/sim/testsuite/bfin/se_loop_kill_dcr.S @@ -0,0 +1,914 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr/se_loop_kill_dcr.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x1 (Z); + P1 = 0x2 (Z); + P2 = 0x3 (Z); + P3 = 0x4 (Z); + P4 = 0x5 (Z); + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (with Kill WB) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in WB +LSETUP ( L0T , L0T ) LC0 = P0; +EXCPT 0x5; +L0T:R0 += 5; + + // Kill Valid Dcr in EX3 +LSETUP ( L1T , L1B ) LC0 = P0; +EXCPT 0x5; +L1T:R0 += 5; +L1B:R1 += 4; + + // Kill Valid Dcr in EX2 +LSETUP ( L2T , L2B ) LC0 = P0; +EXCPT 0x5; +L2T:R0 += 5; + R1 += 4; +L2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( L3T , L3B ) LC0 = P0; +EXCPT 0x5; +L3T:R0 += 5; + R1 += 4; + R2 += 3; +L3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( L4T , L4B ) LC0 = P0; +EXCPT 0x5; +L4T:R0 += 5; + R1 += 4; + R2 += 3; + R3 += 2; +L4B:R4 += 1; + + // Kill Valid Dcr in WB, EX3 +LSETUP ( L5T , L5T ) LC0 = P1; +EXCPT 0x5; +L5T:R1 += 5; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( L6T , L6T ) LC0 = P1; +EXCPT 0x5; +NOP; +L6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( L7T , L7T ) LC0 = P1; +EXCPT 0x5; +NOP; +NOP; +L7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( L8T , L8T ) LC0 = P1; +EXCPT 0x5; +NOP; +NOP; +NOP; +L8T:R4 += 5; + + // Kill Valid Dcr in WB, EX3, EX2 +LSETUP ( L9T , L9T ) LC0 = P2; +EXCPT 0x5; +L9T:R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( LAT , LAT ) LC0 = P2; +EXCPT 0x5; +NOP; +LAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( LBT , LBT ) LC0 = P2; +EXCPT 0x5; +NOP; +NOP; +LBT: + R5 += 5; + + // Kill Valid Dcr in WB, EX3, EX2, EX1 +LSETUP ( LCT , LCT ) LC0 = P3; +EXCPT 0x5; +LCT: + R7 += 7; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( LDT , LDT ) LC0 = P3; +EXCPT 0x5; +NOP; +LDT: + R0 += 7; + + // Kill Valid Dcr in WB, EX3, EX2, EX1, AC +LSETUP ( LET , LET ) LC0 = P4; +EXCPT 0x5; +LET: + R1 += 1; + + // Kill Valid Dcr in WB, EX2 +LSETUP ( LFT , LFB ) LC0 = P1; +LFT: + EXCPT 0x5; +LFB: + R1 += 2; + + // Kill Valid Dcr in WB, EX1 +LSETUP ( LGT , LGB ) LC0 = P1; +LGT: + R2 += 3; +EXCPT 0x5; +LGB: + R1 += 2; + + // Kill Valid Dcr in WB, AC +LSETUP ( LHT , LHB ) LC0 = P1; +LHT: + R2 += 3; + R3 += 4; +EXCPT 0x5; +LHB: + R1 += 2; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( LIT , LIB ) LC0 = P1; +EXCPT 0x5; +LIT: + R2 += 1; +LIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( LJT , LJB ) LC0 = P1; +LJT: + EXCPT 0x5; + R2 += 1; +LJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( LKT , LKB ) LC0 = P1; +EXCPT 0x5; +NOP; +LKT: + R2 += 1; +LKB: + R1 += 2; + + // Kill Valid Dcr in WB, EX2, AC +LSETUP ( LLT , LLB ) LC0 = P2; +LLT: + EXCPT 0x5; +LLB: + R2 += 2; + + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (with Kill WB) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in WB +LSETUP ( M0T , M0T ) LC1 = P0; +EXCPT 0x5; +M0T:R0 += 5; + + // Kill Valid Dcr in EX3 +LSETUP ( M1T , M1B ) LC1 = P0; +EXCPT 0x5; +M1T:R0 += 5; +M1B:R1 += 4; + + // Kill Valid Dcr in EX2 +LSETUP ( M2T , M2B ) LC1 = P0; +EXCPT 0x5; +M2T:R0 += 5; + R1 += 4; +M2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( M3T , M3B ) LC1 = P0; +EXCPT 0x5; +M3T:R0 += 5; + R1 += 4; + R2 += 3; +M3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( M4T , M4B ) LC1 = P0; +EXCPT 0x5; +M4T:R0 += 5; + R1 += 4; + R2 += 3; + R3 += 2; +M4B:R4 += 1; + + // Kill Valid Dcr in WB, EX3 +LSETUP ( M5T , M5T ) LC1 = P1; +EXCPT 0x5; +M5T:R1 += 5; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( M6T , M6T ) LC1 = P1; +EXCPT 0x5; +NOP; +M6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( M7T , M7T ) LC1 = P1; +EXCPT 0x5; +NOP; +NOP; +M7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( M8T , M8T ) LC1 = P1; +EXCPT 0x5; +NOP; +NOP; +NOP; +M8T:R4 += 5; + + // Kill Valid Dcr in WB, EX3, EX2 +LSETUP ( M9T , M9T ) LC1 = P2; +EXCPT 0x5; +M9T:R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( MAT , MAT ) LC1 = P2; +EXCPT 0x5; +NOP; +MAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( MBT , MBT ) LC1 = P2; +EXCPT 0x5; +NOP; +NOP; +MBT: + R5 += 5; + + // Kill Valid Dcr in WB, EX3, EX2, EX1 +LSETUP ( MCT , MCT ) LC1 = P3; +EXCPT 0x5; +MCT: + R7 += 7; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( MDT , MDT ) LC1 = P3; +EXCPT 0x5; +NOP; +MDT: + R0 += 7; + + // Kill Valid Dcr in WB, EX3, EX2, EX1, AC +LSETUP ( MET , MET ) LC1 = P4; +EXCPT 0x5; +MET: + R1 += 1; + + // Kill Valid Dcr in WB, EX2 +LSETUP ( MFT , MFB ) LC1 = P1; +MFT: + EXCPT 0x5; +MFB: + R1 += 2; + + // Kill Valid Dcr in WB, EX1 +LSETUP ( MGT , MGB ) LC1 = P1; +MGT: + R2 += 3; +EXCPT 0x5; +MGB: + R1 += 2; + + // Kill Valid Dcr in WB, AC +LSETUP ( MHT , MHB ) LC1 = P1; +MHT: + R2 += 3; + R3 += 4; +EXCPT 0x5; +MHB: + R1 += 2; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( MIT , MIB ) LC1 = P1; +EXCPT 0x5; +MIT: + R2 += 1; +MIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( MJT , MJB ) LC1 = P1; +MJT: + EXCPT 0x5; + R2 += 1; +MJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( MKT , MKB ) LC1 = P1; +EXCPT 0x5; +NOP; +MKT: + R2 += 1; +MKB: + R1 += 2; + + // Kill Valid Dcr in WB, EX2, AC +LSETUP ( MLT , MLB ) LC1 = P2; +MLT: + EXCPT 0x5; +MLB: + R2 += 2; + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (with Kill EX3) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in EX3 +LSETUP ( N1T , N1T ) LC0 = P0; +CSYNC; +N1T:R0 += 5; + + // Kill Valid Dcr in EX2 +LSETUP ( N2T , N2B ) LC0 = P0; +CSYNC; +N2T:R0 += 5; +N2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( N3T , N3B ) LC0 = P0; +CSYNC; +N3T:R0 += 5; + R2 += 3; +N3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( N4T , N4B ) LC0 = P0; +CSYNC; +N4T:R0 += 5; + R2 += 3; + R3 += 2; +N4B:R4 += 1; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( N6T , N6T ) LC0 = P1; +CSYNC; +N6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( N7T , N7T ) LC0 = P1; +CSYNC; +NOP; +N7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( N8T , N8T ) LC0 = P1; +CSYNC; +NOP; +NOP; +N8T:R4 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( NAT , NAT ) LC0 = P2; +CSYNC; +NAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( NBT , NBT ) LC0 = P2; +CSYNC; +NOP; +NBT: + R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( NDT , NDT ) LC0 = P3; +CSYNC; +NDT: + R0 += 7; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( NIT , NIB ) LC0 = P1; +NIT: + CSYNC; +NIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( NJT , NJB ) LC0 = P1; +NJT: + R2 += 1; +CSYNC; +NJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( NKT , NKB ) LC0 = P1; +CSYNC; +NKT: + R2 += 1; +NKB: + R1 += 2; + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (with Kill EX3) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in EX3 +LSETUP ( O1T , O1T ) LC1 = P0; +CSYNC; +O1T:R0 += 5; + + // Kill Valid Dcr in EX2 +LSETUP ( O2T , O2B ) LC1 = P0; +CSYNC; +O2T:R0 += 5; +O2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( O3T , O3B ) LC1 = P0; +CSYNC; +O3T:R0 += 5; + R2 += 3; +O3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( O4T , O4B ) LC1 = P0; +CSYNC; +O4T:R0 += 5; + R2 += 3; + R3 += 2; +O4B:R4 += 1; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( O6T , O6T ) LC1 = P1; +CSYNC; +O6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( O7T , O7T ) LC1 = P1; +CSYNC; +NOP; +O7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( O8T , O8T ) LC1 = P1; +CSYNC; +NOP; +NOP; +O8T:R4 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( OAT , OAT ) LC1 = P2; +CSYNC; +OAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( OBT , OBT ) LC1 = P2; +CSYNC; +NOP; +OBT: + R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( ODT , ODT ) LC1 = P3; +CSYNC; +ODT: + R0 += 7; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( OIT , OIB ) LC1 = P1; +OIT: + CSYNC; +OIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( OJT , OJB ) LC1 = P1; +OJT: + R2 += 1; +CSYNC; +OJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( OKT , OKB ) LC1 = P1; +CSYNC; +OKT: + R2 += 1; +OKB: + R1 += 2; + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (with Kill AC) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in AC +LSETUP ( P4T , P4T ) LC0 = P0; +JUMP.S 2; +P4T:R0 += 5; + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (with Kill AC) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in AC +LSETUP ( Q4T , Q4T ) LC1 = P0; +JUMP.S 2; +Q4T:R0 += 5; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_kill_dcr_01.S b/sim/testsuite/bfin/se_loop_kill_dcr_01.S new file mode 100644 index 0000000..39a2e8d --- /dev/null +++ b/sim/testsuite/bfin/se_loop_kill_dcr_01.S @@ -0,0 +1,917 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr_01/se_loop_kill_dcr_01.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x1 (Z); + P1 = 0x2 (Z); + P2 = 0x3 (Z); + P3 = 0x4 (Z); + P4 = 0x5 (Z); + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (with Kill WB) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in WB +LSETUP ( L0T , L0T ) LC0 = P0; +EXCPT 0x5; +L0T:R0 += 5; + + // Kill Valid Dcr in EX3 +LSETUP ( L1T , L1B ) LC0 = P0; +EXCPT 0x5; +L1T:R0 += 5; +L1B:R1 += 4; + + // Kill Valid Dcr in EX2 +LSETUP ( L2T , L2B ) LC0 = P0; +EXCPT 0x5; +L2T:R0 += 5; + R1 += 4; +L2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( L3T , L3B ) LC0 = P0; +EXCPT 0x5; +L3T:R0 += 5; + R1 += 4; + R2 += 3; +L3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( L4T , L4B ) LC0 = P0; +EXCPT 0x5; +L4T:R0 += 5; + R1 += 4; + R2 += 3; + R3 += 2; +L4B:R4 += 1; + + // Kill Valid Dcr in WB, EX3 +LSETUP ( L5T , L5T ) LC0 = P1; +EXCPT 0x5; +L5T:R1 += 5; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( L6T , L6T ) LC0 = P1; +EXCPT 0x5; +NOP; +L6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( L7T , L7T ) LC0 = P1; +EXCPT 0x5; +NOP; +NOP; +L7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( L8T , L8T ) LC0 = P1; +EXCPT 0x5; +NOP; +NOP; +NOP; +L8T:R4 += 5; + + // Kill Valid Dcr in WB, EX3, EX2 +LSETUP ( L9T , L9T ) LC0 = P2; +EXCPT 0x5; +L9T:R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( LAT , LAT ) LC0 = P2; +EXCPT 0x5; +NOP; +LAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( LBT , LBT ) LC0 = P2; +EXCPT 0x5; +NOP; +NOP; +LBT: + R5 += 5; + + // Kill Valid Dcr in WB, EX3, EX2, EX1 +LSETUP ( LCT , LCT ) LC0 = P3; +EXCPT 0x5; +LCT: + R7 += 7; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( LDT , LDT ) LC0 = P3; +EXCPT 0x5; +NOP; +LDT: + R0 += 7; + + // Kill Valid Dcr in WB, EX3, EX2, EX1, AC +LSETUP ( LET , LET ) LC0 = P4; +EXCPT 0x5; +LET: + R1 += 1; + + // Kill Valid Dcr in WB, EX2 +LSETUP ( LFT , LFB ) LC0 = P1; +LFT: + EXCPT 0x5; +LFB: + R1 += 2; + + // Kill Valid Dcr in WB, EX1 +LSETUP ( LGT , LGB ) LC0 = P1; +LGT: + R2 += 3; +EXCPT 0x5; +LGB: + R1 += 2; + + // Kill Valid Dcr in WB, AC +LSETUP ( LHT , LHB ) LC0 = P1; +LHT: + R2 += 3; + R3 += 4; +EXCPT 0x5; +LHB: + R1 += 2; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( LIT , LIB ) LC0 = P1; +EXCPT 0x5; +LIT: + R2 += 1; +LIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( LJT , LJB ) LC0 = P1; +LJT: + EXCPT 0x5; + R2 += 1; +LJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( LKT , LKB ) LC0 = P1; +EXCPT 0x5; +NOP; +LKT: + R2 += 1; +LKB: + R1 += 2; + + // Kill Valid Dcr in WB, EX2, AC +LSETUP ( LLT , LLB ) LC0 = P2; +LLT: + EXCPT 0x5; +LLB: + R2 += 2; + + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (with Kill WB) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in WB +LSETUP ( M0T , M0T ) LC1 = P0; +EXCPT 0x5; +M0T:R0 += 5; + + // Kill Valid Dcr in EX3 +LSETUP ( M1T , M1B ) LC1 = P0; +EXCPT 0x5; +M1T:R0 += 5; +M1B:R1 += 4; + + // Kill Valid Dcr in EX2 +LSETUP ( M2T , M2B ) LC1 = P0; +EXCPT 0x5; +M2T:R0 += 5; + R1 += 4; +M2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( M3T , M3B ) LC1 = P0; +EXCPT 0x5; +M3T:R0 += 5; + R1 += 4; + R2 += 3; +M3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( M4T , M4B ) LC1 = P0; +EXCPT 0x5; +M4T:R0 += 5; + R1 += 4; + R2 += 3; + R3 += 2; +M4B:R4 += 1; + + // Kill Valid Dcr in WB, EX3 +LSETUP ( M5T , M5T ) LC1 = P1; +EXCPT 0x5; +M5T:R1 += 5; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( M6T , M6T ) LC1 = P1; +EXCPT 0x5; +NOP; +M6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( M7T , M7T ) LC1 = P1; +EXCPT 0x5; +NOP; +NOP; +M7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( M8T , M8T ) LC1 = P1; +EXCPT 0x5; +NOP; +NOP; +NOP; +M8T:R4 += 5; + + // Kill Valid Dcr in WB, EX3, EX2 +LSETUP ( M9T , M9T ) LC1 = P2; +EXCPT 0x5; +M9T:R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( MAT , MAT ) LC1 = P2; +EXCPT 0x5; +NOP; +MAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( MBT , MBT ) LC1 = P2; +EXCPT 0x5; +NOP; +NOP; +MBT: + R5 += 5; + + // Kill Valid Dcr in WB, EX3, EX2, EX1 +LSETUP ( MCT , MCT ) LC1 = P3; +EXCPT 0x5; +MCT: + R7 += 7; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( MDT , MDT ) LC1 = P3; +EXCPT 0x5; +NOP; +MDT: + R0 += 7; + + // Kill Valid Dcr in WB, EX3, EX2, EX1, AC +LSETUP ( MET , MET ) LC1 = P4; +EXCPT 0x5; +MET: + R1 += 1; + + // Kill Valid Dcr in WB, EX2 +LSETUP ( MFT , MFB ) LC1 = P1; +MFT: + EXCPT 0x5; +MFB: + R1 += 2; + + // Kill Valid Dcr in WB, EX1 +LSETUP ( MGT , MGB ) LC1 = P1; +MGT: + R2 += 3; +EXCPT 0x5; +MGB: + R1 += 2; + + // Kill Valid Dcr in WB, AC +LSETUP ( MHT , MHB ) LC1 = P1; +MHT: + R2 += 3; + R3 += 4; +EXCPT 0x5; +MHB: + R1 += 2; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( MIT , MIB ) LC1 = P1; +EXCPT 0x5; +MIT: + R2 += 1; +MIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( MJT , MJB ) LC1 = P1; +MJT: + EXCPT 0x5; + R2 += 1; +MJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( MKT , MKB ) LC1 = P1; +EXCPT 0x5; +NOP; +MKT: + R2 += 1; +MKB: + R1 += 2; + + // Kill Valid Dcr in WB, EX2, AC +LSETUP ( MLT , MLB ) LC1 = P2; +MLT: + EXCPT 0x5; +MLB: + R2 += 2; + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (with Kill EX3) +///////////////////////////////////////////////////////////////////////////// + + R0 = 1; +CC = R0; + + // Kill %Valid Dcr in EX3 +LSETUP ( N1T , N1T ) LC0 = P0; +IF CC JUMP 2; +N1T:R0 += 5; + + // Kill Valid Dcr in EX2 +LSETUP ( N2T , N2B ) LC0 = P0; +IF CC JUMP 2; +N2T:R0 += 5; +N2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( N3T , N3B ) LC0 = P0; +IF CC JUMP 2; +N3T:R0 += 5; + R2 += 3; +N3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( N4T , N4B ) LC0 = P0; +IF CC JUMP 2; +N4T:R0 += 5; + R2 += 3; + R3 += 2; +N4B:R4 += 1; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( N6T , N6T ) LC0 = P1; +IF CC JUMP 2; +N6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( N7T , N7T ) LC0 = P1; +IF CC JUMP 2; +NOP; +N7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( N8T , N8T ) LC0 = P1; +IF CC JUMP 2; +NOP; +NOP; +N8T:R4 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( NAT , NAT ) LC0 = P2; +IF CC JUMP 2; +NAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( NBT , NBT ) LC0 = P2; +IF CC JUMP 2; +NOP; +NBT: + R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( NDT , NDT ) LC0 = P3; +IF CC JUMP 2; +NDT: + R0 += 7; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( NIT , NIB ) LC0 = P1; +NIT: + IF CC JUMP 2; +NIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( NJT , NJB ) LC0 = P1; +NJT: + R2 += 1; +IF CC JUMP 2; +NJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( NKT , NKB ) LC0 = P1; +IF CC JUMP 2; +NKT: + R2 += 1; +NKB: + R1 += 2; + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (with Kill EX3) +///////////////////////////////////////////////////////////////////////////// + + // Kill %Valid Dcr in EX3 +LSETUP ( O1T , O1T ) LC1 = P0; +IF CC JUMP 2; +O1T:R0 += 5; + + // Kill Valid Dcr in EX2 +LSETUP ( O2T , O2B ) LC1 = P0; +IF CC JUMP 2; +O2T:R0 += 5; +O2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( O3T , O3B ) LC1 = P0; +IF CC JUMP 2; +O3T:R0 += 5; + R2 += 3; +O3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( O4T , O4B ) LC1 = P0; +IF CC JUMP 2; +O4T:R0 += 5; + R2 += 3; + R3 += 2; +O4B:R4 += 1; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( O6T , O6T ) LC1 = P1; +IF CC JUMP 2; +O6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( O7T , O7T ) LC1 = P1; +IF CC JUMP 2; +NOP; +O7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( O8T , O8T ) LC1 = P1; +IF CC JUMP 2; +NOP; +NOP; +O8T:R4 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( OAT , OAT ) LC1 = P2; +IF CC JUMP 2; +OAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( OBT , OBT ) LC1 = P2; +IF CC JUMP 2; +NOP; +OBT: + R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( ODT , ODT ) LC1 = P3; +IF CC JUMP 2; +ODT: + R0 += 7; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( OIT , OIB ) LC1 = P1; +OIT: + IF CC JUMP 2; +OIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( OJT , OJB ) LC1 = P1; +OJT: + R2 += 1; +IF CC JUMP 2; +OJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( OKT , OKB ) LC1 = P1; +IF CC JUMP 2; +OKT: + R2 += 1; +OKB: + R1 += 2; + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (with Kill AC) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in AC +LSETUP ( P4T , P4T ) LC0 = P0; +JUMP.S 2; +P4T:R0 += 5; + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (with Kill AC) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in AC +LSETUP ( Q4T , Q4T ) LC1 = P0; +JUMP.S 2; +Q4T:R0 += 5; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_lr.S b/sim/testsuite/bfin/se_loop_lr.S new file mode 100644 index 0000000..71e0308 --- /dev/null +++ b/sim/testsuite/bfin/se_loop_lr.S @@ -0,0 +1,507 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_lr/se_loop_lr.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + + +LD32_LABEL(r0, l1e); +LSETUP ( l1e , l1e ) LC0 = P1; +l1s:LT0 = R0; +l1e:[ -- SP ] = R7; + + +LD32_LABEL(r0, ls1); +LSETUP ( l2s , l2e ) LC0 = P0; +l2s:LB0 = R0; +ls1:R6 += 2; +l2e:[ -- SP ] = ( R7:5 ); + + +LD32_LABEL(r0, ls2); +LD32_LABEL(r1, ls3); +LSETUP ( l3s , l3e ) LC0 = P0; +l3s:LT0 = R0; +ls2:LB0 = R1; +ls3:R7 += 3; +l3e:[ -- SP ] = ( R7:5 ); + + +LD32_LABEL(r0, ls4); +LD32_LABEL(r1, ls5); +LSETUP ( l4s , l4e ) LC0 = P0; +l4s:LT0 = R0; +LB0 = r1; +ls4:R7 += 3; +ls5:R4 += 4; +l4e:[ -- SP ] = ( R7:4 ); + +LD32_LABEL(r0, ls6); +LD32_LABEL(r1, ls7); +LSETUP ( l5s , l5e ) LC0 = P0; +l5s:LB0 = R1; +LT0 = r0; +ls6:R7 += 3; + R4 += 4; + R5 += 3; +ls7:R6 += 3; +l5e:[ -- SP ] = ( R7:4 ); + +LD32_LABEL(r0, ls8); +LD32_LABEL(r1, ls9); +LSETUP ( l6s , l6e ) LC0 = P0; +l6s:R5 += 1; +LB0 = r1; +LT0 = r0; +ls8:R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +ls9:R7 += 5; +l6e:[ -- SP ] = ( R7:4 ); + + +NOP; +NOP; + +LD32_LABEL(r0, m1e); +LSETUP ( m1e , m1e ) LC1 = P1; +m1s:LT0 = R0; +m1e:[ -- SP ] = R7; + + +LD32_LABEL(r0, ms1); +LSETUP ( m2s , m2e ) LC1 = P0; +m2s:LB0 = R0; +ms1:R6 += 2; +m2e:[ -- SP ] = ( R7:5 ); + + +LD32_LABEL(r0, ms2); +LD32_LABEL(r1, ms3); +LSETUP ( m3s , m3e ) LC1 = P0; +m3s:LT0 = R0; +ms2:LB0 = R1; +ms3:R7 += 3; +m3e:[ -- SP ] = ( R7:5 ); + + +LD32_LABEL(r0, ms4); +LD32_LABEL(r1, ms5); +LSETUP ( m4s , m4e ) LC1 = P0; +m4s:LT0 = R0; +LB0 = r1; +ms4:R7 += 3; +ms5:R4 += 4; +m4e:[ -- SP ] = ( R7:4 ); + +LD32_LABEL(r0, ms6); +LD32_LABEL(r1, ms7); +LSETUP ( m5s , m5e ) LC1 = P0; +m5s:LB0 = R1; +LT0 = r0; +ms6:R7 += 3; + R4 += 4; + R5 += 3; +ms7:R6 += 3; +m5e:[ -- SP ] = ( R7:4 ); + +LD32_LABEL(r0, ms8); +LD32_LABEL(r1, ms9); +LSETUP ( m6s , m6e ) LC1 = P0; +m6s:R5 += 1; +LB0 = r1; +LT0 = r0; +ms8:R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +ms9:R7 += 5; +m6e:[ -- SP ] = ( R7:4 ); + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_mv2lb_stall.S b/sim/testsuite/bfin/se_loop_mv2lb_stall.S new file mode 100644 index 0000000..a3b2c24 --- /dev/null +++ b/sim/testsuite/bfin/se_loop_mv2lb_stall.S @@ -0,0 +1,612 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lb_stall/se_loop_mv2lb_stall.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + P2 = 0x0100 (Z); + P2.H = 0x00f0; + + // Loop 0 +LD32_LABEL(r0, L0T); +LD32_LABEL(r1, L0B); +LC0 = p1; +LT0 = r0; + R0 = [ P2 ++ ]; +LB0 = r1; +L0T:R3 += 4; + R2 += 3; + R4 += 5; + R5 += 6; + R6 += 7; +L0B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L1T); +LD32_LABEL(r1, L1B); +LT0 = r0; +LC0 = p1; + R0 = [ P2 ++ ]; +NOP; +LB0 = r1; +L1T:R4 += 5; + R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; +L1B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L2T); +LD32_LABEL(r1, L2B); +LT0 = r0; +LC0 = p1; + R0 = [ P2 ++ ]; +NOP; +NOP; +LB0 = r1; +L2T:R5 += 6; + R2 += 3; + R3 += 4; + R4 += 5; + R6 += 7; +L2B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L3T); +LD32_LABEL(r1, L3B); +LT0 = r0; +LC0 = p1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LB0 = r1; +L3T:R2 += 3; + R5 += 6; + R6 += 7; + R3 += 4; + R4 += 5; +L3B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L4T); +LD32_LABEL(r1, L4B); +LT0 = r0; +LC0 = p1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LB0 = r1; +L4T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +L4B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L5T); +LD32_LABEL(r1, L5B); + [ -- SP ] = R1; +SSYNC; +LT0 = r0; +LC0 = p0; + R0 = [ P2 ++ ]; +LB0 = [sp++]; +L5T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +L5B:R7 += 8; + + + // Loop 1 +LD32_LABEL(r0, M0T); +LD32_LABEL(r1, M0B); +LT1 = r0; +LC1 = p1; + R0 = [ P2 ++ ]; +LB1 = r1; +M0T:R3 += 4; + R2 += 3; + R4 += 5; + R5 += 6; + R6 += 7; +M0B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M1T); +LD32_LABEL(r1, M1B); +LT1 = r0; +LC1 = p1; + R0 = [ P2 ++ ]; +NOP; +LB1 = r1; +M1T:R4 += 5; + R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; +M1B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M2T); +LD32_LABEL(r1, M2B); +LT1 = r0; +LC1 = p1; + R0 = [ P2 ++ ]; +NOP; +NOP; +LB1 = r1; +M2T:R5 += 6; + R2 += 3; + R3 += 4; + R4 += 5; + R6 += 7; +M2B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M3T); +LD32_LABEL(r1, M3B); +LT1 = r0; +LC1 = p1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LB1 = r1; +M3T:R2 += 3; + R5 += 6; + R6 += 7; + R3 += 4; + R4 += 5; +M3B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M4T); +LD32_LABEL(r1, M4B); +LT1 = r0; +LC1 = p1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LB1 = r1; +M4T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +M4B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M5T); +LD32_LABEL(r1, M5B); + [ -- SP ] = R1; +SSYNC; +LT1 = r0; +LC1 = p0; + R0 = [ P2 ++ ]; +LB1 = [sp++]; +M5T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +M5B:R7 += 8; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_mv2lc.S b/sim/testsuite/bfin/se_loop_mv2lc.S new file mode 100644 index 0000000..69adeca --- /dev/null +++ b/sim/testsuite/bfin/se_loop_mv2lc.S @@ -0,0 +1,777 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lc/se_loop_mv2lc.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + + // Loop 0 +LD32_LABEL(r0, L0T); +LD32_LABEL(r1, L0B); +LT0 = r0; +LB0 = r1; + +LC0 = P0; +NOP; +JUMP.S 2; + +JUMP.S 6; +NOP; +LC0 = P0; +LC0 = P1; +L0T:R2 += 3; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; +L0B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, L1T); +LD32_LABEL(r1, L1B); +LT1 = r0; +LB1 = r1; + +LC1 = P0; +NOP; +JUMP.S 2; + +JUMP.S 6; +NOP; +LC1 = P0; +LC1 = P1; +L1T:R2 += 3; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; +L1B:R7 += 8; + + // Loop 0 +LSETUP ( L2T , L2T ) LC0 = P0; +NOP; +NOP; +NOP; +LC0 = P1; +L2T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +L2B:R7 += 6; + +LC0 = P1; +NOP; +NOP; +NOP; +LSETUP ( L3T , L3T ) LC0 = P0; +L3T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +L3B:R7 += 6; + +LSETUP ( L4T , L4B ) LC0 = P0; +NOP; +NOP; +LC0 = P1; +L4T:R2 += 1; +L4B:R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LC0 = P1; +NOP; +NOP; +LSETUP ( L5T , L5B ) LC0 = P0; +L5T:R2 += 1; +L5B:R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LSETUP ( L6T , L6B ) LC0 = P0; +NOP; +LC0 = P1; +L6T:R2 += 1; + R3 += 2; +L6B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LC0 = P1; +NOP; +LSETUP ( L7T , L7B ) LC0 = P0; +L7T:R2 += 1; + R3 += 2; +L7B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LSETUP ( L8T , L8B ) LC0 = P0; +LC0 = P1; +L8T:R2 += 1; + R3 += 2; + R4 += 3; +L8B:R5 += 4; + R6 += 5; + R7 += 6; + +LC0 = P1; +LSETUP ( L9T , L9B ) LC0 = P0; +L9T:R2 += 1; + R3 += 2; + R4 += 3; +L9B:R5 += 4; + R6 += 5; + R7 += 6; + + + // Loop 1 +LSETUP ( M2T , M2T ) LC1 = P0; +NOP; +NOP; +NOP; +LC1 = P1; +M2T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +M2B:R7 += 6; + +LC1 = P1; +NOP; +NOP; +NOP; +LSETUP ( M3T , M3T ) LC1 = P0; +M3T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +M3B:R7 += 6; + +LSETUP ( M4T , M4B ) LC1 = P0; +NOP; +NOP; +LC1 = P1; +M4T:R2 += 1; +M4B:R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LC1 = P1; +NOP; +NOP; +LSETUP ( M5T , M5B ) LC1 = P0; +M5T:R2 += 1; +M5B:R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LSETUP ( M6T , M6B ) LC1 = P0; +NOP; +LC1 = P1; +M6T:R2 += 1; + R3 += 2; +M6B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LC1 = P1; +NOP; +LSETUP ( M7T , M7B ) LC1 = P0; +M7T:R2 += 1; + R3 += 2; +M7B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LSETUP ( M8T , M8B ) LC1 = P0; +LC1 = P1; +M8T:R2 += 1; + R3 += 2; + R4 += 3; +M8B:R5 += 4; + R6 += 5; + R7 += 6; + +LC1 = P1; +LSETUP ( M9T , M9B ) LC1 = P0; +M9T:R2 += 1; + R3 += 2; + R4 += 3; +M9B:R5 += 4; + R6 += 5; + R7 += 6; + + // Loop 0 +LSETUP ( N2T , N2B ) LC0 = P0 >> 1; +NOP; +NOP; +NOP; +LC0 = P1; +N2T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +N2B:R7 += 6; + +LC0 = P1; +NOP; +NOP; +NOP; +LSETUP ( N3T , N3B ) LC0 = P0 >> 1; +N3T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +N3B:R7 += 6; + +LSETUP ( N4T , N4B ) LC0 = P0 >> 1; +NOP; +NOP; +LC0 = P1; +N4T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; +N4B:R6 += 5; + R7 += 6; + +LC0 = P1; +NOP; +NOP; +LSETUP ( N5T , N5B ) LC0 = P0 >> 1; +N5T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; +N5B:R6 += 5; + R7 += 6; + +LSETUP ( N6T , N6B ) LC0 = P0 >> 1; +NOP; +LC0 = P1; +N6T:R2 += 1; + R3 += 2; + R4 += 3; +N6B:R5 += 4; + R6 += 5; + R7 += 6; + +LC0 = P1; +NOP; +LSETUP ( N7T , N7B ) LC0 = P0 >> 1; +N7T:R2 += 1; + R3 += 2; + R4 += 3; +N7B:R5 += 4; + R6 += 5; + R7 += 6; + +LSETUP ( N8T , N8T ) LC0 = P0 >> 1; +LC0 = P1; +N8T:R2 += 1; + R3 += 2; +N8B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LC0 = P1; +LSETUP ( N9T , N9T ) LC0 = P0 >> 1; +N9T:R2 += 1; + R3 += 2; +N9B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + + + // Loop 1 +LSETUP ( O2T , O2B ) LC1 = P0 >> 1; +NOP; +NOP; +NOP; +LC1 = P1; +O2T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +O2B:R7 += 6; + +LC1 = P1; +NOP; +NOP; +NOP; +LSETUP ( O3T , O3B ) LC1 = P0 >> 1; +O3T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +O3B:R7 += 6; + +LSETUP ( O4T , O4B ) LC1 = P0 >> 1; +NOP; +NOP; +LC1 = P1; +O4T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; +O4B:R6 += 5; + R7 += 6; + +LC1 = P1; +NOP; +NOP; +LSETUP ( O5T , O5B ) LC1 = P0 >> 1; +O5T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; +O5B:R6 += 5; + R7 += 6; + +LSETUP ( O6T , O6B ) LC1 = P0 >> 1; +NOP; +LC1 = P1; +O6T:R2 += 1; + R3 += 2; + R4 += 3; +O6B:R5 += 4; + R6 += 5; + R7 += 6; + +LC1 = P1; +NOP; +LSETUP ( O7T , O7B ) LC1 = P0 >> 1; +O7T:R2 += 1; + R3 += 2; + R4 += 3; +O7B:R5 += 4; + R6 += 5; + R7 += 6; + +LSETUP ( O8T , O8T ) LC1 = P0 >> 1; +LC1 = P1; +O8T:R2 += 1; + R3 += 2; +O8B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LC1 = P1; +LSETUP ( O9T , O9T ) LC1 = P0 >> 1; +O9T:R2 += 1; + R3 += 2; +O9B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_mv2lc_stall.S b/sim/testsuite/bfin/se_loop_mv2lc_stall.S new file mode 100644 index 0000000..ecd98bf --- /dev/null +++ b/sim/testsuite/bfin/se_loop_mv2lc_stall.S @@ -0,0 +1,612 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lc_stall/se_loop_mv2lc_stall.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + P2 = 0x0100 (Z); + P2.H = 0x00f0; + + // 2 pushes of P0 onto the Stack; + [ -- SP ] = P0; + [ -- SP ] = P0; + + // Loop 0 +LD32_LABEL(r0, L0T); +LD32_LABEL(r1, L0B); +LT0 = r0; +LB0 = r1; + R0 = [ P2 ++ ]; +LC0 = p1; +L0T:R3 += 4; + R2 += 3; + R4 += 5; + R5 += 6; + R6 += 7; +L0B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L1T); +LD32_LABEL(r1, L1B); +LT0 = r0; +LB0 = r1; + R0 = [ P2 ++ ]; +NOP; +LC0 = p1; +L1T:R4 += 5; + R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; +L1B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L2T); +LD32_LABEL(r1, L2B); +LT0 = r0; +LB0 = r1; + R0 = [ P2 ++ ]; +NOP; +NOP; +LC0 = p1; +L2T:R5 += 6; + R2 += 3; + R3 += 4; + R4 += 5; + R6 += 7; +L2B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L3T); +LD32_LABEL(r1, L3B); +LT0 = r0; +LB0 = r1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LC0 = p1; +L3T:R2 += 3; + R5 += 6; + R6 += 7; + R3 += 4; + R4 += 5; +L3B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L4T); +LD32_LABEL(r1, L4B); +LT0 = r0; +LB0 = r1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LC0 = p1; +L4T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +L4B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L5T); +LD32_LABEL(r1, L5B); +LT0 = r0; +LB0 = r1; + R0 = [ P2 ++ ]; +LC0 = [sp++]; +L5T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +L5B:R7 += 8; + + + // Loop 1 +LD32_LABEL(r0, M0T); +LD32_LABEL(r1, M0B); +LT1 = r0; +LB1 = r1; + R0 = [ P2 ++ ]; +LC1 = p1; +M0T:R3 += 4; + R2 += 3; + R4 += 5; + R5 += 6; + R6 += 7; +M0B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M1T); +LD32_LABEL(r1, M1B); +LT1 = r0; +LB1 = r1; + R0 = [ P2 ++ ]; +NOP; +LC1 = p1; +M1T:R4 += 5; + R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; +M1B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M2T); +LD32_LABEL(r1, M2B); +LT1 = r0; +LB1 = r1; + R0 = [ P2 ++ ]; +NOP; +NOP; +LC1 = p1; +M2T:R5 += 6; + R2 += 3; + R3 += 4; + R4 += 5; + R6 += 7; +M2B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M3T); +LD32_LABEL(r1, M3B); +LT1 = r0; +LB1 = r1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LC1 = p1; +M3T:R2 += 3; + R5 += 6; + R6 += 7; + R3 += 4; + R4 += 5; +M3B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M4T); +LD32_LABEL(r1, M4B); +LT1 = r0; +LB1 = r1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LC1 = p1; +M4T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +M4B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M5T); +LD32_LABEL(r1, M5B); +LT1 = r0; +LB1 = r1; + R0 = [ P2 ++ ]; +LC1 = [sp++]; +M5T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +M5B:R7 += 8; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_mv2lt_stall.S b/sim/testsuite/bfin/se_loop_mv2lt_stall.S new file mode 100644 index 0000000..36d2d73 --- /dev/null +++ b/sim/testsuite/bfin/se_loop_mv2lt_stall.S @@ -0,0 +1,612 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lt_stall/se_loop_mv2lt_stall.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + P2 = 0x0100 (Z); + P2.H = 0x00f0; + + // Loop 0 +LD32_LABEL(r0, L0T); +LD32_LABEL(r1, L0B); +LC0 = p1; +LB0 = r1; + R5 = [ P2 ++ ]; +LT0 = r0; +L0T:R3 += 4; + R2 += 3; + R4 += 5; + R5 += 6; + R6 += 7; +L0B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L1T); +LD32_LABEL(r1, L1B); +LB0 = r1; +LC0 = p1; + R5 = [ P2 ++ ]; +NOP; +LT0 = r0; +L1T:R4 += 5; + R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; +L1B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L2T); +LD32_LABEL(r1, L2B); +LB0 = r1; +LC0 = p1; + R5 = [ P2 ++ ]; +NOP; +NOP; +LT0 = r0; +L2T:R5 += 6; + R2 += 3; + R3 += 4; + R4 += 5; + R6 += 7; +L2B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L3T); +LD32_LABEL(r1, L3B); +LB0 = r1; +LC0 = p1; + R5 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LT0 = r0; +L3T:R2 += 3; + R5 += 6; + R6 += 7; + R3 += 4; + R4 += 5; +L3B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L4T); +LD32_LABEL(r1, L4B); +LB0 = r1; +LC0 = p1; + R5 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LT0 = r0; +L4T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +L4B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L5T); +LD32_LABEL(r1, L5B); + [ -- SP ] = R0; +SSYNC; +LB0 = r1; +LC0 = p0; + R5 = [ P2 ++ ]; +LT0 = [sp++]; +L5T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +L5B:R7 += 8; + + + // Loop 1 +LD32_LABEL(r0, M0T); +LD32_LABEL(r1, M0B); +LB1 = r1; +LC1 = p1; + R5 = [ P2 ++ ]; +LT1 = r0; +M0T:R3 += 4; + R2 += 3; + R4 += 5; + R5 += 6; + R6 += 7; +M0B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M1T); +LD32_LABEL(r1, M1B); +LB1 = r1; +LC1 = p1; + R5 = [ P2 ++ ]; +NOP; +LT1 = r0; +M1T:R4 += 5; + R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; +M1B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M2T); +LD32_LABEL(r1, M2B); +LB1 = r1; +LC1 = p1; + R5 = [ P2 ++ ]; +NOP; +NOP; +LT1 = r0; +M2T:R5 += 6; + R2 += 3; + R3 += 4; + R4 += 5; + R6 += 7; +M2B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M3T); +LD32_LABEL(r1, M3B); +LB1 = r1; +LC1 = p1; + R5 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LT1 = r0; +M3T:R2 += 3; + R5 += 6; + R6 += 7; + R3 += 4; + R4 += 5; +M3B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M4T); +LD32_LABEL(r1, M4B); +LB1 = r1; +LC1 = p1; + R5 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LT1 = r0; +M4T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +M4B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M5T); +LD32_LABEL(r1, M5B); + [ -- SP ] = R0; +SSYNC; +LB1 = r1; +LC1 = p0; + R5 = [ P2 ++ ]; +LT1 = [sp++]; +M5T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +M5B:R7 += 8; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_nest_ppm.S b/sim/testsuite/bfin/se_loop_nest_ppm.S new file mode 100644 index 0000000..81613db --- /dev/null +++ b/sim/testsuite/bfin/se_loop_nest_ppm.S @@ -0,0 +1,442 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm/se_loop_nest_ppm.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x4 (Z); + +LSETUP ( l0s , l0s ) LC0 = P0; +LSETUP ( l0s , l0s ) LC1 = P1; +l0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( l1s , l1e ) LC0 = P0; +LSETUP ( l1e , l1e ) LC1 = P1; +l1s:R5 += 1; +l1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l2s , l2e ) LC0 = P0; +LSETUP ( l2e , l2e ) LC1 = P1; +l2s:R5 += 1; + R6 += 2; +l2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l3s , l3e ) LC0 = P0; +LSETUP ( l3e , l3e ) LC1 = P1; +l3s:R5 += 1; + R6 += 2; + R7 += 3; +l3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l4s , l4e ) LC0 = P0; +LSETUP ( l4e , l4e ) LC1 = P1; +l4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +l4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l5s , l5e ) LC0 = P0; +LSETUP ( l5e , l5e ) LC1 = P1; +l5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +l5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l6s , l6e ) LC0 = P0; +LSETUP ( l6e , l6e ) LC1 = P1; +l6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +l6e:[ -- SP ] = ( R7:4 ); + +NOP; +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_nest_ppm_1.S b/sim/testsuite/bfin/se_loop_nest_ppm_1.S new file mode 100644 index 0000000..6eab92f --- /dev/null +++ b/sim/testsuite/bfin/se_loop_nest_ppm_1.S @@ -0,0 +1,442 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_1/se_loop_nest_ppm_1.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x4 (Z); + +LSETUP ( l0s , l0s ) LC0 = P0; +LSETUP ( l0s , l0s ) LC1 = P1; +l0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( l1s , l1e ) LC0 = P0; +LSETUP ( l1s , l1e ) LC1 = P1; +l1s:R5 += 1; +l1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l2s , l2e ) LC0 = P0; +LSETUP ( l2s , l2e ) LC1 = P1; +l2s:R5 += 1; + R6 += 2; +l2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l3s , l3e ) LC0 = P0; +LSETUP ( l3s , l3e ) LC1 = P1; +l3s:R5 += 1; + R6 += 2; + R7 += 3; +l3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l4s , l4e ) LC0 = P0; +LSETUP ( l4s , l4e ) LC1 = P1; +l4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +l4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l5s , l5e ) LC0 = P0; +LSETUP ( l5s , l5e ) LC1 = P1; +l5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +l5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l6s , l6e ) LC1 = P0; +LSETUP ( l6s , l6e ) LC1 = P1; +l6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +l6e:[ -- SP ] = ( R7:4 ); + +NOP; +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_nest_ppm_2.S b/sim/testsuite/bfin/se_loop_nest_ppm_2.S new file mode 100644 index 0000000..bf842ed --- /dev/null +++ b/sim/testsuite/bfin/se_loop_nest_ppm_2.S @@ -0,0 +1,491 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_2/se_loop_nest_ppm_2.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + +// lsetup (l0s, l0s) lc0 = p0; +LSETUP ( l0s , l0s ) LC0 = P1; +l0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( l1s , l1e ) LC0 = P0; +LSETUP ( l1e , l1e ) LC0 = P1; +l1s:R5 += 1; +l1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l2s , l2e ) LC0 = P0; +LSETUP ( l2e , l2e ) LC0 = P1; +l2s:R5 += 1; + R6 += 2; +l2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l3s , l3e ) LC0 = P0; +LSETUP ( l3e , l3e ) LC0 = P1; +l3s:R5 += 1; + R6 += 2; + R7 += 3; +l3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l4s , l4e ) LC0 = P0; +LSETUP ( l4e , l4e ) LC0 = P1; +l4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +l4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l5s , l5e ) LC0 = P0; +LSETUP ( l5e , l5e ) LC0 = P1; +l5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +l5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l6s , l6e ) LC0 = P0; +LSETUP ( l6e , l6e ) LC0 = P1; +l6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +l6e:[ -- SP ] = ( R7:4 ); + +NOP; + +LSETUP ( m0s , m0s ) LC1 = P0; +LSETUP ( m0s , m0s ) LC1 = P1; +m0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( m1s , m1e ) LC1 = P0; +LSETUP ( m1e , m1e ) LC1 = P1; +m1s:R5 += 1; +m1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m2s , m2e ) LC1 = P0; +LSETUP ( m2e , m2e ) LC1 = P1; +m2s:R5 += 1; + R6 += 2; +m2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m3s , m3e ) LC1 = P0; +LSETUP ( m3e , m3e ) LC1 = P1; +m3s:R5 += 1; + R6 += 2; + R7 += 3; +m3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m4s , m4e ) LC1 = P0; +LSETUP ( m4e , m4e ) LC1 = P1; +m4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +m4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( m5s , m5e ) LC1 = P0; +LSETUP ( m5e , m5e ) LC1 = P1; +m5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +m5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( m6s , m6e ) LC1 = P0; +LSETUP ( m6e , m6e ) LC1 = P1; +m6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +m6e:[ -- SP ] = ( R7:4 ); +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_ppm.S b/sim/testsuite/bfin/se_loop_ppm.S new file mode 100644 index 0000000..b551baf --- /dev/null +++ b/sim/testsuite/bfin/se_loop_ppm.S @@ -0,0 +1,477 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_ppm/se_loop_ppm.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + +LSETUP ( l0s , l0s ) LC0 = P0; +l0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( l1s , l1e ) LC0 = P0; +l1s:R5 += 1; +l1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l2s , l2e ) LC0 = P0; +l2s:R5 += 1; + R6 += 2; +l2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l3s , l3e ) LC0 = P0; +l3s:R5 += 1; + R6 += 2; + R7 += 3; +l3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l4s , l4e ) LC0 = P0; +l4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +l4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l5s , l5e ) LC0 = P0; +l5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +l5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l6s , l6e ) LC1 = P0; +l6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +l6e:[ -- SP ] = ( R7:4 ); + +NOP; + +LSETUP ( m0s , m0s ) LC1 = P0; +m0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( m1s , m1e ) LC1 = P0; +m1s:R5 += 1; +m1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m2s , m2e ) LC1 = P0; +m2s:R5 += 1; + R6 += 2; +m2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m3s , m3e ) LC1 = P0; +m3s:R5 += 1; + R6 += 2; + R7 += 3; +m3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m4s , m4e ) LC1 = P0; +m4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +m4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( m5s , m5e ) LC1 = P0; +m5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +m5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( m6s , m6e ) LC1 = P0; +m6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +m6e:[ -- SP ] = ( R7:4 ); + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_ppm_1.S b/sim/testsuite/bfin/se_loop_ppm_1.S new file mode 100644 index 0000000..db8e2ca --- /dev/null +++ b/sim/testsuite/bfin/se_loop_ppm_1.S @@ -0,0 +1,519 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_ppm_1/se_loop_ppm_1.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + +LSETUP ( l0s , l0s ) LC0 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( l1s , l1e ) LC0 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l1s:R5 += 1; +l1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l2s , l2e ) LC0 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l2s:R5 += 1; + R6 += 2; +l2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l3s , l3e ) LC0 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l3s:R5 += 1; + R6 += 2; + R7 += 3; +l3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l4s , l4e ) LC0 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +l4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l5s , l5e ) LC0 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +l5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l6s , l6e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +l6e:[ -- SP ] = ( R7:4 ); + +NOP; + +LSETUP ( m0s , m0s ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( m1s , m1e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m1s:R5 += 1; +m1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m2s , m2e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m2s:R5 += 1; + R6 += 2; +m2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m3s , m3e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m3s:R5 += 1; + R6 += 2; + R7 += 3; +m3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m4s , m4e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +m4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( m5s , m5e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +m5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( m6s , m6e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +m6e:[ -- SP ] = ( R7:4 ); + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_loop_ppm_int.S b/sim/testsuite/bfin/se_loop_ppm_int.S new file mode 100644 index 0000000..eed16b4 --- /dev/null +++ b/sim/testsuite/bfin/se_loop_ppm_int.S @@ -0,0 +1,429 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_ppm_int/se_loop_ppm_int.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Sync it! +CSYNC; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; + + P0 = 0x5 (Z); + +LSETUP ( l0s , l0s ) LC0 = P0; +CSYNC; +l0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( l3s , l3e ) LC0 = P0; +l3s:[ -- SP ] = ( R7:5 ); + R6 += 2; + R7 += 3; +NOP; + +CSYNC; +NOP; +NOP; +NOP; +l3e:R5 += 1; + +NOP; + +LSETUP ( m0s , m0s ) LC1 = P0; +CSYNC; +m0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( m3s , m3e ) LC1 = P0; +m3s:[ -- SP ] = ( R7:5 ); + R6 += 2; + R7 += 3; +NOP; + +CSYNC; +NOP; +NOP; +NOP; +m3e:R5 += 1; + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_lsetup_kill.S b/sim/testsuite/bfin/se_lsetup_kill.S new file mode 100644 index 0000000..65d3441 --- /dev/null +++ b/sim/testsuite/bfin/se_lsetup_kill.S @@ -0,0 +1,776 @@ +//Original:/proj/frio/dv/testcases/seq/se_lsetup_kill/se_lsetup_kill.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0xa (Z); + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (Kill Lsetup in WB) +///////////////////////////////////////////////////////////////////////////// + +EXCPT 0x5; +LSETUP ( L0T , L0T ) LC0 = P0; +L0T:R0 += 5; + +EXCPT 0x5; +LSETUP ( L1T , L1B ) LC0 = P0; +L1T:R0 += 5; +L1B:R1 += 4; + +EXCPT 0x5; +LSETUP ( L2T , L2B ) LC0 = P0; +L2T:R0 += 5; + R1 += 4; +L2B:R2 += 3; + +EXCPT 0x5; +LSETUP ( L3T , L3B ) LC0 = P0; +L3T:R0 += 5; + R1 += 4; + R2 += 3; +L3B:R3 += 2; + +EXCPT 0x5; +LSETUP ( L4T , L4B ) LC0 = P0; +L4T:R0 += 5; + R1 += 4; + R2 += 3; + R3 += 2; +L4B:R4 += 1; + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (Kill Lsetup in WB) +///////////////////////////////////////////////////////////////////////////// + +EXCPT 0x5; +LSETUP ( M0T , M0T ) LC1 = P0; +M0T:R0 += 5; + +EXCPT 0x5; +LSETUP ( M1T , M1B ) LC1 = P0; +M1T:R0 += 5; +M1B:R1 += 4; + +EXCPT 0x5; +LSETUP ( M2T , M2B ) LC1 = P0; +M2T:R0 += 5; + R1 += 4; +M2B:R2 += 3; + +EXCPT 0x5; +LSETUP ( M3T , M3B ) LC1 = P0; +M3T:R0 += 5; + R1 += 4; + R2 += 3; +M3B:R3 += 2; + +EXCPT 0x5; +LSETUP ( M4T , M4B ) LC1 = P0; +M4T:R0 += 5; + R1 += 4; + R2 += 3; + R3 += 2; +M4B:R4 += 1; + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (Kill during the last iteration at each pipe stage) +///////////////////////////////////////////////////////////////////////////// + +LSETUP ( N0T , N0B ) LC0 = P1; +NOP; +N0T:R0 = LC0; +CC = R0 == 1; +IF !CC JUMP N0B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; +N0B:R2 += 3; + +LSETUP ( N1T , N1B ) LC0 = P1; +NOP; +N1T:R0 = LC0; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP N1B (BP); +EXCPT 0x5; +N1B:R2 += 3; + +LSETUP ( N2T , N2B ) LC0 = P1; +NOP; +N2T:R0 = LC0; +CC = R0 == 1; +IF !CC JUMP N2B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; +N2B:R2 += 3; + +LSETUP ( N3T , N3B ) LC0 = P1; +NOP; +N3T:R0 = LC0; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP N3B (BP); +EXCPT 0x5; + R3 += 4; +N3B:R2 += 3; + +LSETUP ( N4T , N4B ) LC0 = P1; +NOP; +N4T:R0 = LC0; +CC = R0 == 1; +IF !CC JUMP N4B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; +N4B:R2 += 3; + +LSETUP ( N5T , N5B ) LC0 = P1; +NOP; +N5T:R0 = LC0; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP N5B (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; +N5B:R2 += 3; + +LSETUP ( N6T , N6B ) LC0 = P1; +NOP; +N6T:R0 = LC0; +CC = R0 == 1; +IF !CC JUMP N6B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; +N6B:R2 += 3; + +LSETUP ( N7T , N7B ) LC0 = P1; +NOP; +N7T:R0 = LC0; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP N7B (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; +N7B:R2 += 3; + +LSETUP ( N8T , N8B ) LC0 = P1; +NOP; +N8T:R0 = LC0; +CC = R0 == 1; +IF !CC JUMP N8B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; +N8B:R2 += 3; + +LSETUP ( N9T , N9B ) LC0 = P1; +NOP; +N9T:R0 = LC0; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP N9B (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; +N9B:R2 += 3; + +LSETUP ( NAT , NAB ) LC0 = P1; +NOP; +NAT: + R0 = LC0; +CC = R0 == 1; +IF !CC JUMP NAB (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; +NAB: + R2 += 3; + +LSETUP ( NBT , NBB ) LC0 = P1; +NOP; +NBT: + R0 = LC0; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP NBB (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; +NBB: + R2 += 3; + + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (Kill during the last iteration at each pipe stage) +///////////////////////////////////////////////////////////////////////////// + +LSETUP ( O0T , O0B ) LC1 = P1; +NOP; +O0T:R0 = LC1; +CC = R0 == 1; +IF !CC JUMP O0B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; +O0B:R2 += 3; + +LSETUP ( O1T , O1B ) LC1 = P1; +NOP; +O1T:R0 = LC1; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP O1B (BP); +EXCPT 0x5; +O1B:R2 += 3; + +LSETUP ( O2T , O2B ) LC1 = P1; +NOP; +O2T:R0 = LC1; +CC = R0 == 1; +IF !CC JUMP O2B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; +O2B:R2 += 3; + +LSETUP ( O3T , O3B ) LC1 = P1; +NOP; +O3T:R0 = LC1; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP O3B (BP); +EXCPT 0x5; + R3 += 4; +O3B:R2 += 3; + +LSETUP ( O4T , O4B ) LC1 = P1; +NOP; +O4T:R0 = LC1; +CC = R0 == 1; +IF !CC JUMP O4B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; +O4B:R2 += 3; + +LSETUP ( O5T , O5B ) LC1 = P1; +NOP; +O5T:R0 = LC1; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP O5B (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; +O5B:R2 += 3; + +LSETUP ( O6T , O6B ) LC1 = P1; +NOP; +O6T:R0 = LC1; +CC = R0 == 1; +IF !CC JUMP O6B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; +O6B:R2 += 3; + +LSETUP ( O7T , O7B ) LC1 = P1; +NOP; +O7T:R0 = LC1; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP O7B (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; +O7B:R2 += 3; + +LSETUP ( O8T , O8B ) LC1 = P1; +NOP; +O8T:R0 = LC1; +CC = R0 == 1; +IF !CC JUMP O8B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; +O8B:R2 += 3; + +LSETUP ( O9T , O9B ) LC1 = P1; +NOP; +O9T:R0 = LC1; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP O9B (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; +O9B:R2 += 3; + +LSETUP ( OAT , OAB ) LC1 = P1; +NOP; +OAT: + R0 = LC1; +CC = R0 == 1; +IF !CC JUMP OAB (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; +OAB: + R2 += 3; + +LSETUP ( OBT , OBB ) LC1 = P1; +NOP; +OBT: + R0 = LC1; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP OBB (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; +OBB: + R2 += 3; + +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_misaligned_fetch.S b/sim/testsuite/bfin/se_misaligned_fetch.S new file mode 100644 index 0000000..2249243 --- /dev/null +++ b/sim/testsuite/bfin/se_misaligned_fetch.S @@ -0,0 +1,286 @@ +//Original:/proj/frio/dv/testcases/seq/se_misaligned_fetch/se_misaligned_fetch.dsp +// Description: attempt to fetch code from misaligned address +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers + +CLI R0; // hold off nonmaskables while writing EVTs + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; // wait for MMR writes +STI R0; // reenable events + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests +// [--sp] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + +LD32_LABEL(p1, TARGET); + + P1 += 1; // cause access to be misaligned + +JUMP ( P1 ); // should cause misaligned + + R1 += 1; + R1 += 1; + R1 += 1; + R1 += 1; + R1 += 1; + R1 += 1; + R1 += 1; + R1 += 1; + +TARGET: +NOP; +NOP; +NOP; + + // PUT YOUR TEST HERE! + + +END: +CHECKREG(r5, 0xFFFFFFFF); // handler sets this if reached + +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x2A; // EXCAUSE 0x2A means I-Fetch Misaligned Access +CC = r7 == r6; +IF CC JUMP IFETCHMISALIGNED; // If EXCAUSE != 0x2A then leave + +dbg_pass; // if the EXCAUSE is wrong the test will infinite loop + +IFETCHMISALIGNED: + R7 = P1; // Fix up return address +BITCLR(r7, 0); // Strip off errant LSB +RETX = r7; // and put back in RETX + + R5 = -1; // set flag to indicate success + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_more_ret_haz.S b/sim/testsuite/bfin/se_more_ret_haz.S new file mode 100644 index 0000000..c25ddca --- /dev/null +++ b/sim/testsuite/bfin/se_more_ret_haz.S @@ -0,0 +1,271 @@ +//Original:/proj/frio/dv/testcases/seq/se_more_ret_haz/se_more_ret_haz.dsp +// Description: Return insts following pop, move. +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +CLI R1; + +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; +STI R1; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// + +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +RAISE 2; + R2.L = 0xBAD; +CHECKREG(r2, 0); + +AFTER_RTN: +EXCPT 5; + R2.L = 0xBAD; +CHECKREG(r2, 0); + +AFTER_RTX: +RAISE 5; + R2.L = 0xBAD; +CHECKREG(r2, 0); + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R1.L = AFTER_RTN; + R1.H = AFTER_RTN; + [ -- SP ] = R1; +RETN = [ SP ++ ]; +RTN; + +XHANDLE: // Exception Handler 3 + R1.L = AFTER_RTX; + R1.H = AFTER_RTX; + [ -- SP ] = R1; +RETX = [ SP ++ ]; +RTX; + +HWHANDLE: // HW Error Handler 5 + R1.L = END; + R1.H = END; + [ -- SP ] = R1; +RETI = [ SP ++ ]; +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_mv2lp.S b/sim/testsuite/bfin/se_mv2lp.S new file mode 100644 index 0000000..09feafc --- /dev/null +++ b/sim/testsuite/bfin/se_mv2lp.S @@ -0,0 +1,481 @@ +//Original:/proj/frio/dv/testcases/seq/se_mv2lp/se_mv2lp.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_1 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + + P0 = 0x5 (Z); + P1 = 0xa (Z); + + P2 = 0x0100 (Z); + P2.H = 0x00f0; + +LD32_LABEL(r0, L0T); +LD32_LABEL(r1, L0B); +LSETUP ( L0T , L0B ) LC0 = P0; +L0T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + R0 += 2; + R1 += 2; +LT0 = R0; +LB0 = R1; +L0B:R7 += 6; + R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + +LD32_LABEL(r0, L1T); +LD32_LABEL(r1, L1B); +LSETUP ( L1T , L1B ) LC1 = P0; +L1T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + R0 += 2; + R1 += 2; +LT1 = R0; +LB1 = R1; +L1B:R7 += 6; + R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + +LD32_LABEL(r0, L2T); +LD32_LABEL(r1, L2B); +LSETUP ( L2T , L2B ) LC0 = P0; +L2T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + R0 += 2; + R1 += -2; +LT0 = R0; +LB0 = R1; + R7 += 6; + R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; +L2B:R6 += 5; + +LD32_LABEL(r0, L3T); +LD32_LABEL(r1, L3B); +LSETUP ( L3T , L3B ) LC1 = P0; +L3T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + R0 += 2; + R1 += -2; +LT1 = R0; +LB1 = R1; + R7 += 6; + R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; +L3B:R6 += 5; + +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_oneins_zoff.S b/sim/testsuite/bfin/se_oneins_zoff.S new file mode 100644 index 0000000..79259fc --- /dev/null +++ b/sim/testsuite/bfin/se_oneins_zoff.S @@ -0,0 +1,487 @@ +//Original:/proj/frio/dv/testcases/seq/se_oneins_zoff/se_oneins_zoff.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + + P0 = 0x5 (Z); + P1 = 0xa (Z); + + P2 = 0x0100 (Z); + P2.H = 0x00f0; + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (One instruction Zero-offset) +///////////////////////////////////////////////////////////////////////////// + + R0 = [ P2 ++ ]; +LSETUP ( L0T , L0T ) LC0 = P0; +L0T:R0 += 5; + + R1 = [ P2 ++ ]; +NOP; +LSETUP ( L1T , L1T ) LC0 = P0; +L1T:R1 += 5; + + R2 = [ P2 ++ ]; +NOP; +NOP; +LSETUP ( L2T , L2T ) LC0 = P0; +L2T:R2 += 5; + + R3 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LSETUP ( L3T , L3T ) LC0 = P0; +L3T:R3 += 5; + + R4 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LSETUP ( L4T , L4T ) LC0 = P0; +L4T:R4 += 5; + + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (One instruction Zero-offset) +///////////////////////////////////////////////////////////////////////////// + + R0 = [ P2 ++ ]; +LSETUP ( M0T , M0T ) LC1 = P0; +M0T:R0 += 5; + + R1 = [ P2 ++ ]; +NOP; +LSETUP ( M1T , M1T ) LC1 = P0; +M1T:R1 += 5; + + R2 = [ P2 ++ ]; +NOP; +NOP; +LSETUP ( M2T , M2T ) LC1 = P0; +M2T:R2 += 5; + + R3 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LSETUP ( M3T , M3T ) LC1 = P0; +M3T:R3 += 5; + + R4 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LSETUP ( M4T , M4T ) LC1 = P0; +M4T:R4 += 5; + + +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_popkill.S b/sim/testsuite/bfin/se_popkill.S new file mode 100644 index 0000000..550db19 --- /dev/null +++ b/sim/testsuite/bfin/se_popkill.S @@ -0,0 +1,566 @@ +//Original:/proj/frio/dv/testcases/seq/se_popkill/se_popkill.dsp +// Description: Kill pops to sysregs in WB +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_RST_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_RST_2 // +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + +///////////////////////////////////////////////////////////////////////////// +//////////////////////// CPLB Setup ///////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + // Setup CPLB for Data Memory starting at 0x00F0_0000; +WR_MMR(DCPLB_DATA0, DATA_ADDR_1, p0, r0); + //WR_MMR(DCPLB_DATA0, 0x00031005, p0, r0); // Page Size = 4MB + // CPLB_L1_CHLB = 1 + // CPLB_USER_RD = 1 + // CPLB_VALID = 1 + // + + // Setup CPLB Address to point to 0x00F0_0000 +WR_MMR(DCPLB_ADDR0, DATA_ADDR_2, p0, r0); + //WR_MMR(DCPLB_ADDR0, 0x00F00000, p0, r0); + + // Enable CPLB's +WR_MMR(DMEM_CONTROL, DATA_ADDR_3, p0, r0); + //WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1 + // ENDCPLB = 1 + // DMC = 11 + // Sync it! +CSYNC; + + + // Return to Supervisor Code +RAISE 15; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + + R3 = SEQSTAT; + R4 = RETX; + R4 += 8; +RETX = R4; +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +NOP; +ASTAT = R7; +RETS = R7; +LC0 = R7; +LB0 = R7; +LT0 = R7; +LC1 = R7; +LB1 = R7; +LT1 = R7; +CYCLES = R7; +CYCLES2 = R7; +SYSCFG = R7; +RETN = R7; +RETX = R7; +RETE = R7; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +EXCPT 1; +ASTAT = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 2; +RETS = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 3; +LC0 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 4; +LT0 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 5; +LB0 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 6; +LC1 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 7; +LB1 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 8; +LT1 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 9; +CYCLES = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 10; +CYCLES2 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 11; +SYSCFG = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 12; +RETI = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 13; +RETX = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 14; +RETN = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 15; +RETE = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; + +NOP; +NOP; +NOP; +NOP; + + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +// Define Kernal Stack +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +.section MEM_DATA_ADDR_2 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_regmv_usp_sysreg.S b/sim/testsuite/bfin/se_regmv_usp_sysreg.S new file mode 100644 index 0000000..9d776ac --- /dev/null +++ b/sim/testsuite/bfin/se_regmv_usp_sysreg.S @@ -0,0 +1,171 @@ +//Original:/proj/frio/dv/testcases/seq/se_regmv_usp_sysreg/se_regmv_usp_sysreg.dsp +// Description: RegMV USP to SYSREG +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(selfcheck.inc) +include(std.inc) +include(symtable.inc) + +//********************************************************************* + +BEGIN: + + // KLUDGE: from perl script must place cycles 2 write before cycles + // write, and cycles 2 read AFTER cycles read + + // PUT YOUR TEST HERE! + R0 = 0; +SP = R0; +SYSCFG = R0; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + + R0 = 0x59c4 (Z); + R0.H = 0x95a6; +USP = R0; +ASTAT = USP; + R1 = ASTAT; + + R0 = 0xd4a4 (Z); + R0.H = 0xd16c; +USP = R0; +RETS = USP; + R1 = RETS; +CHECKREG(r1, 3513570468); + + R0 = 0x2bca (Z); + R0.H = 0x6ad8; +USP = R0; +LC0 = USP; + R1 = LC0; +CHECKREG(r1, 1792551882); + + R0 = 0x6d4a (Z); + R0.H = 0xada2; +USP = R0; +LT0 = USP; + R1 = LT0; +CHECKREG(r1, 2913103178); + + R0 = 0x6b18 (Z); + R0.H = 0x931c; +USP = R0; +LB0 = USP; + R1 = LB0; +CHECKREG(r1, 2468113176); + + R0 = 0x62da (Z); + R0.H = 0x16ee; +USP = R0; +LC1 = USP; + R1 = LC1; +CHECKREG(r1, 384721626); + + R0 = 0x7c60 (Z); + R0.H = 0xf7c8; +USP = R0; +LT1 = USP; + R1 = LT1; +CHECKREG(r1, 4157111392); + + R0 = 0x182 (Z); + R0.H = 0x942; +USP = R0; +LB1 = USP; + R1 = LB1; +CHECKREG(r1, 155320706); + + R0 = 0xd5a2 (Z); + R0.H = 0x8782; +USP = R0; +CYCLES2 = USP; + // KLUDGE - moved read after that for cycles + + R0 = 0x297c (Z); + R0.H = 0x9d06; +USP = R0; +CYCLES = USP; + R1 = CYCLES; +CHECKREG(r1, 2634426748); + R1 = CYCLES2; // KLUDGE moved read after that for cycles +CHECKREG(r1, 2273498530); + + R0 = 0x8c66 (Z); + R0.H = 0x3d64; +USP = R0; +SEQSTAT = USP; + R1 = SEQSTAT; + + R0 = 0x3b8c (Z); + R0.H = 0xdcd4; +USP = R0; +SYSCFG = USP; + R1 = SYSCFG; + + R0 = 0xb1ae (Z); + R0.H = 0x6f6; +USP = R0; +RETI = USP; + R1 = RETI; +CHECKREG(r1, 116830638); + + R0 = 0x32b0 (Z); + R0.H = 0x9b7e; +USP = R0; +RETX = USP; + R1 = RETX; +CHECKREG(r1, 2608738992); + + R0 = 0xea72 (Z); + R0.H = 0x11ea; +USP = R0; +RETN = USP; + R1 = RETN; +CHECKREG(r1, 300608114); + + R0 = 0x2c58 (Z); + R0.H = 0xb13a; +USP = R0; +RETE = USP; + R1 = RETE; +CHECKREG(r1, 2973379672); + +// Sanity check +USP = R0; +USP = R1; +USP = R2; +USP = R3; +USP = R4; +USP = R5; +USP = R6; +USP = R7; +USP = P0; +USP = P1; +USP = P2; +USP = P3; +USP = P4; +USP = P5; +USP = SP; +USP = FP; +USP = A0.X; +USP = A0.W; +USP = A1.X; +USP = A1.W; +A0.X = USP; +A0.W = USP; +A1.X = USP; +A1.W = USP; + +END: +dbg_pass; // End the test + +//********************************************************************* diff --git a/sim/testsuite/bfin/se_rets_hazard.s b/sim/testsuite/bfin/se_rets_hazard.s new file mode 100644 index 0000000..7406e87 --- /dev/null +++ b/sim/testsuite/bfin/se_rets_hazard.s @@ -0,0 +1,55 @@ +//Original:/testcases/seq/se_rets_hazard/se_rets_hazard.dsp +# mach: bfin + +.include "testutils.inc" + start + + +BOOT: + FP = SP; // and frame pointer + + INIT_R_REGS 0; // initialize general purpose regs + + + + + ASTAT = r0; // reset sequencer registers + +// The Main Program + + +START: + loadsym r1, SUB1; + RETS = r1; + RTS; + +MID1: + CHECKREG r6, 0; // shouldn't be BAD + R6.L = 0xBAD2; // In case we come back to MID1 + loadsym P1, MID2; + CALL ( P1 ); + RTS; + +MID2: + loadsym R1, END; + RETS = r1; + [ -- SP ] = I0; + LINK 0; + I0 = FP; + UNLINK; + RTS; + +END: + + pass // Call Endtest Macro + +// Subroutines and Functions + +SUB1: // Code goes here + CHECKREG r7, 0; // should be if sub executed + R7.L = 0xBAD; // In case we come back to SUB1 + loadsym R2, MID1; + [ -- SP ] = R2; + RETS = [sp++]; + RTS; + R6.L = 0xBAD; diff --git a/sim/testsuite/bfin/se_rts_rti.S b/sim/testsuite/bfin/se_rts_rti.S new file mode 100644 index 0000000..8767d67 --- /dev/null +++ b/sim/testsuite/bfin/se_rts_rti.S @@ -0,0 +1,442 @@ +//Original:/proj/frio/dv/testcases/seq/se_rts_rti/se_rts_rti.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Load RETS +LD32_LABEL(r0, USER_CODE); +RETS = R0; + + // Return to Supervisor Code +RAISE 2; +RAISE 5; +RAISE 6; +RAISE 7; +RAISE 8; +RAISE 9; +RAISE 10; +RAISE 11; +RAISE 12; +RAISE 13; +RAISE 14; +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +EXCPT 0x5; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_ssstep_dagprotviol.S b/sim/testsuite/bfin/se_ssstep_dagprotviol.S new file mode 100644 index 0000000..bd4daf3 --- /dev/null +++ b/sim/testsuite/bfin/se_ssstep_dagprotviol.S @@ -0,0 +1,297 @@ +//Original:/proj/frio/dv/testcases/seq/se_ssstep_dagprotviol/se_ssstep_dagprotviol.dsp +// Description: prioritize DAG Protection Violation and Supervisor Single Step +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +RETS = r0; // prevent X's breaking LINK instruction + + R0 = 1; +SYSCFG = r0; // enable ssstep + + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests +// [--sp] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // PUT YOUR TEST HERE! + +NOP; + I0 += 2; + I1 += 2; + I2 += 2; + R7 = [ P0 ]; // cause DAG PROTECTION VIOLATION (p0 is an MMR) + I3 += 2; + + +EXCPT 2; // turn off SSSTEP + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + +CHECKREG(r5, 7); // check the flag (# SSSTEP) +CHECKREG(r4, 1); // check the flag (# illegal opcodes) + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 +CC = r7 == r6; +IF CC JUMP EXCPT2; + + R6 = 0x10; // EXCAUSE 0x10 means Single Step +CC = r7 == r6; +IF CC JUMP SSSTEP (BP); + + R6 = 0x23; // EXCAUSE 0x23 means DAG Protection Violation +CC = r7 == r6; +IF CC JUMP DAGPROTVIOL (BP); + +JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop + +EXCPT2: // turn off SSSTEP + R7 = 0; +SYSCFG = r7; +JUMP.S OUT; + +SSSTEP: + R5 += 1; // increment a counter +JUMP.S OUT; + +DAGPROTVIOL: + R7 = RETX; + R7 += 2; +RETX = R7; // skip offending instruction + + R4 += 1; // increment another counter + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1 //.data 0xE0000000,"aw" +DATA: + .space (0x10); + +DATADUMMY: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_ssync.S b/sim/testsuite/bfin/se_ssync.S new file mode 100644 index 0000000..e59f2f5 --- /dev/null +++ b/sim/testsuite/bfin/se_ssync.S @@ -0,0 +1,61 @@ +//Original:/proj/frio/dv/testcases/seq/se_ssync/se_ssync.dsp +// Description: Test SSYNC by writing a bunch of MMRs and verifying read +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif + +LD32(p0, EVT5); +LD32(r0, 0x55555555); +LD32(p1, EVT6); +LD32(r1, 0xAAAAAAAA); +LD32(p2, EVT7); +LD32(r2, 0xBABEFACE); +LD32(p3, EVT8); +LD32(r3, 0xCFCFCFCF); +LD32(p4, EVT9); +LD32(r4, 0xDEADBEEF); +LD32(p5, EVT10); +LD32(r5, 0xBAD1BAD1); + + [ P0 ] = R0; // write the MMRS + [ P1 ] = R1; + [ P2 ] = R2; + [ P3 ] = R3; + [ P4 ] = R4; + [ P5 ] = R5; + +SSYNC; // wait for it + + R7 = [ P5 ]; // read back MMRs + R6 = [ P4 ]; // should be updated + R5 = [ P3 ]; + R4 = [ P2 ]; + R3 = [ P1 ]; + R2 = [ P0 ]; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + +CHECKREG(r2, 0x55555555); +CHECKREG(r3, 0xAAAAAAAA); +CHECKREG(r4, 0xBABEFACE); +CHECKREG(r5, 0xCFCFCFCF); +CHECKREG(r6, 0xDEADBEEF); +CHECKREG(r7, 0xBAD1BAD1); + +dbg_pass; diff --git a/sim/testsuite/bfin/se_stall_if2.S b/sim/testsuite/bfin/se_stall_if2.S new file mode 100644 index 0000000..a6c939f --- /dev/null +++ b/sim/testsuite/bfin/se_stall_if2.S @@ -0,0 +1,458 @@ +//Original:/proj/frio/dv/testcases/seq/se_stall_if2/se_stall_if2.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + +///////////////////////////////////////////////////////////////////////////// +//////////////////////// CPLB Setup ///////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + // Setup CPLB for Data Memory starting at 0x00F0_0000; +WR_MMR(DCPLB_DATA0, 0x00031005, p0, r0); // Page Size = 4MB + // CPLB_L1_CHLB = 1 + // CPLB_USER_RD = 1 + // CPLB_VALID = 1 + // + + // Setup CPLB Address to point to 0x00F0_0000 +WR_MMR(DCPLB_ADDR0, 0x00F00000, p0, r0); + + // Enable CPLB's +WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1 + // ENDCPLB = 1 + // DMC = 11 + // Sync it! +CSYNC; + + + // Return to Supervisor Code +RAISE 15; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +NOP; + P0 = 0x0100 (Z); + P0.H = 0x00f0; + R0 = [ P0 ++ ]; +JUMP.S lab1; // Branch in EX1 + + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +lab1: + P0 = 0x0200 (Z); + P0.H = 0x00f0; +RTI; + R1 = [ P0 ++ ]; +JUMP.S 8; // Branch in EX1 +NOP; +NOP; +NOP; + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +// Define Kernal Stack +.section MEM_0xE0000000,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +.section MEM_0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_0x00F00200,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/bfin/se_undefinedinstruction1.S b/sim/testsuite/bfin/se_undefinedinstruction1.S new file mode 100644 index 0000000..5337a74 --- /dev/null +++ b/sim/testsuite/bfin/se_undefinedinstruction1.S @@ -0,0 +1,1102 @@ +//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction1/se_undefinedinstruction1.dsp +// Description: 16 bit "holes" Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + A0 = 0; // reset accumulators + A1 = 0; + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // count of UI's will be in r5, which was initialized to 0 by header + + + .dw 0x1 ; + .dw 0x2 ; + .dw 0x3 ; + .dw 0x4 ; + .dw 0x5 ; + .dw 0x6 ; + .dw 0x7 ; + .dw 0x8 ; + .dw 0x9 ; + .dw 0xA ; + .dw 0xB ; + .dw 0xC ; + .dw 0xD ; + .dw 0xE ; + .dw 0xF ; + .dw 0x15 ; + .dw 0x16 ; + .dw 0x17 ; + .dw 0x18 ; + .dw 0x19 ; + .dw 0x1A ; + .dw 0x1B ; + .dw 0x1C ; + .dw 0x1D ; + .dw 0x1E ; + .dw 0x1F ; + .dw 0x21 ; + .dw 0x22 ; + .dw 0x26 ; + .dw 0x27 ; // XXX: hardware doesnt trigger illegal exception ? + .dw 0x28 ; + .dw 0x29 ; + .dw 0x2A ; + .dw 0x2B ; + .dw 0x2C ; + .dw 0x2D ; + .dw 0x2E ; + .dw 0x2F ; + .dw 0x38 ; + .dw 0x39 ; + .dw 0x3A ; + .dw 0x3B ; + .dw 0x3C ; + .dw 0x3D ; + .dw 0x3E ; + .dw 0x3F ; + .dw 0x48 ; + .dw 0x49 ; + .dw 0x4A ; + .dw 0x4B ; + .dw 0x4C ; + .dw 0x4D ; + .dw 0x4E ; + .dw 0x4F ; + .dw 0x58 ; + .dw 0x59 ; + .dw 0x5A ; + .dw 0x5B ; + .dw 0x5C ; + .dw 0x5D ; + .dw 0x5E ; + .dw 0x5F ; + .dw 0x68 ; + .dw 0x69 ; + .dw 0x6A ; + .dw 0x6B ; + .dw 0x6C ; + .dw 0x6D ; + .dw 0x6E ; + .dw 0x6F ; + .dw 0x78 ; + .dw 0x79 ; + .dw 0x7A ; + .dw 0x7B ; + .dw 0x7C ; + .dw 0x7D ; + .dw 0x7E ; + .dw 0x7F ; + .dw 0x88 ; + .dw 0x89 ; + .dw 0x8A ; + .dw 0x8B ; + .dw 0x8C ; + .dw 0x8D ; + .dw 0x8E ; + .dw 0x8F ; + .dw 0xB8 ; + .dw 0xB9 ; + .dw 0xBA ; + .dw 0xBB ; + .dw 0xBC ; + .dw 0xBD ; + .dw 0xBE ; + .dw 0xBF ; + .dw 0xC0 ; + .dw 0xC1 ; + .dw 0xC2 ; + .dw 0xC3 ; + .dw 0xC4 ; + .dw 0xC5 ; + .dw 0xC6 ; + .dw 0xC7 ; + .dw 0xC8 ; + .dw 0xC9 ; + .dw 0xCA ; + .dw 0xCB ; + .dw 0xCC ; + .dw 0xCD ; + .dw 0xCE ; + .dw 0xCF ; + .dw 0xD0 ; + .dw 0xD1 ; + .dw 0xD2 ; + .dw 0xD3 ; + .dw 0xD4 ; + .dw 0xD5 ; + .dw 0xD6 ; + .dw 0xD7 ; + .dw 0xD8 ; + .dw 0xD9 ; + .dw 0xDA ; + .dw 0xDB ; + .dw 0xDC ; + .dw 0xDD ; + .dw 0xDE ; + .dw 0xDF ; + .dw 0xE0 ; + .dw 0xE1 ; + .dw 0xE2 ; + .dw 0xE3 ; + .dw 0xE4 ; + .dw 0xE5 ; + .dw 0xE6 ; + .dw 0xE7 ; + .dw 0xE8 ; + .dw 0xE9 ; + .dw 0xEA ; + .dw 0xEB ; + .dw 0xEC ; + .dw 0xED ; + .dw 0xEE ; + .dw 0xEF ; + .dw 0xF0 ; + .dw 0xF1 ; + .dw 0xF2 ; + .dw 0xF3 ; + .dw 0xF4 ; + .dw 0xF5 ; + .dw 0xF6 ; + .dw 0xF7 ; + .dw 0xF8 ; + .dw 0xF9 ; + .dw 0xFA ; + .dw 0xFB ; + .dw 0xFC ; + .dw 0xFD ; + .dw 0xFE ; + .dw 0xFF ; + .dw 0x220 ; + .dw 0x221 ; + .dw 0x222 ; + .dw 0x223 ; + .dw 0x224 ; + .dw 0x225 ; + .dw 0x226 ; + .dw 0x227 ; + .dw 0x228 ; + .dw 0x229 ; + .dw 0x22A ; + .dw 0x22B ; + .dw 0x22C ; + .dw 0x22D ; + .dw 0x22E ; + .dw 0x22F ; + .dw 0x230 ; + .dw 0x231 ; + .dw 0x232 ; + .dw 0x233 ; + .dw 0x234 ; + .dw 0x235 ; + .dw 0x236 ; + .dw 0x237 ; + .dw 0x238 ; + .dw 0x239 ; + .dw 0x23A ; + .dw 0x23B ; + .dw 0x23C ; + .dw 0x23D ; + .dw 0x23E ; + .dw 0x23F ; + .dw 0x280 ; + .dw 0x281 ; + .dw 0x282 ; + .dw 0x283 ; + .dw 0x284 ; + .dw 0x285 ; + .dw 0x286 ; + .dw 0x287 ; + .dw 0x288 ; + .dw 0x289 ; + .dw 0x28A ; + .dw 0x28B ; + .dw 0x28C ; + .dw 0x28D ; + .dw 0x28E ; + .dw 0x28F ; + .dw 0x290 ; + .dw 0x291 ; + .dw 0x292 ; + .dw 0x293 ; + .dw 0x294 ; + .dw 0x295 ; + .dw 0x296 ; + .dw 0x297 ; + .dw 0x298 ; + .dw 0x299 ; + .dw 0x29A ; + .dw 0x29B ; + .dw 0x29C ; + .dw 0x29D ; + .dw 0x29E ; + .dw 0x29F ; + .dw 0x2A0 ; + .dw 0x2A1 ; + .dw 0x2A2 ; + .dw 0x2A3 ; + .dw 0x2A4 ; + .dw 0x2A5 ; + .dw 0x2A6 ; + .dw 0x2A7 ; + .dw 0x2A8 ; + .dw 0x2A9 ; + .dw 0x2AA ; + .dw 0x2AB ; + .dw 0x2AC ; + .dw 0x2AD ; + .dw 0x2AE ; + .dw 0x2AF ; + .dw 0x2B0 ; + .dw 0x2B1 ; + .dw 0x2B2 ; + .dw 0x2B3 ; + .dw 0x2B4 ; + .dw 0x2B5 ; + .dw 0x2B6 ; + .dw 0x2B7 ; + .dw 0x2B8 ; + .dw 0x2B9 ; + .dw 0x2BA ; + .dw 0x2BB ; + .dw 0x2BC ; + .dw 0x2BD ; + .dw 0x2BE ; + .dw 0x2BF ; + .dw 0x2C0 ; + .dw 0x2C1 ; + .dw 0x2C2 ; + .dw 0x2C3 ; + .dw 0x2C4 ; + .dw 0x2C5 ; + .dw 0x2C6 ; + .dw 0x2C7 ; + .dw 0x2C8 ; + .dw 0x2C9 ; + .dw 0x2CA ; + .dw 0x2CB ; + .dw 0x2CC ; + .dw 0x2CD ; + .dw 0x2CE ; + .dw 0x2CF ; + .dw 0x2D0 ; + .dw 0x2D1 ; + .dw 0x2D2 ; + .dw 0x2D3 ; + .dw 0x2D4 ; + .dw 0x2D5 ; + .dw 0x2D6 ; + .dw 0x2D7 ; + .dw 0x2D8 ; + .dw 0x2D9 ; + .dw 0x2DA ; + .dw 0x2DB ; + .dw 0x2DC ; + .dw 0x2DD ; + .dw 0x2DE ; + .dw 0x2DF ; + .dw 0x2E0 ; + .dw 0x2E1 ; + .dw 0x2E2 ; + .dw 0x2E3 ; + .dw 0x2E4 ; + .dw 0x2E5 ; + .dw 0x2E6 ; + .dw 0x2E7 ; + .dw 0x2E8 ; + .dw 0x2E9 ; + .dw 0x2EA ; + .dw 0x2EB ; + .dw 0x2EC ; + .dw 0x2ED ; + .dw 0x2EE ; + .dw 0x2EF ; + .dw 0x2F0 ; + .dw 0x2F1 ; + .dw 0x2F2 ; + .dw 0x2F3 ; + .dw 0x2F4 ; + .dw 0x2F5 ; + .dw 0x2F6 ; + .dw 0x2F7 ; + .dw 0x2F8 ; + .dw 0x2F9 ; + .dw 0x2FA ; + .dw 0x2FB ; + .dw 0x2FC ; + .dw 0x2FD ; + .dw 0x2FE ; + .dw 0x2FF ; + .dw 0x4600 ; + .dw 0x4601 ; + .dw 0x4602 ; + .dw 0x4603 ; + .dw 0x4604 ; + .dw 0x4605 ; + .dw 0x4606 ; + .dw 0x4607 ; + .dw 0x4608 ; + .dw 0x4609 ; + .dw 0x460A ; + .dw 0x460B ; + .dw 0x460C ; + .dw 0x460D ; + .dw 0x460E ; + .dw 0x460F ; + .dw 0x4610 ; + .dw 0x4611 ; + .dw 0x4612 ; + .dw 0x4613 ; + .dw 0x4614 ; + .dw 0x4615 ; + .dw 0x4616 ; + .dw 0x4617 ; + .dw 0x4618 ; + .dw 0x4619 ; + .dw 0x461A ; + .dw 0x461B ; + .dw 0x461C ; + .dw 0x461D ; + .dw 0x461E ; + .dw 0x461F ; + .dw 0x4620 ; + .dw 0x4621 ; + .dw 0x4622 ; + .dw 0x4623 ; + .dw 0x4624 ; + .dw 0x4625 ; + .dw 0x4626 ; + .dw 0x4627 ; + .dw 0x4628 ; + .dw 0x4629 ; + .dw 0x462A ; + .dw 0x462B ; + .dw 0x462C ; + .dw 0x462D ; + .dw 0x462E ; + .dw 0x462F ; + .dw 0x4630 ; + .dw 0x4631 ; + .dw 0x4632 ; + .dw 0x4633 ; + .dw 0x4634 ; + .dw 0x4635 ; + .dw 0x4636 ; + .dw 0x4637 ; + .dw 0x4638 ; + .dw 0x4639 ; + .dw 0x463A ; + .dw 0x463B ; + .dw 0x463C ; + .dw 0x463D ; + .dw 0x463E ; + .dw 0x463F ; + .dw 0x4640 ; + .dw 0x4641 ; + .dw 0x4642 ; + .dw 0x4643 ; + .dw 0x4644 ; + .dw 0x4645 ; + .dw 0x4646 ; + .dw 0x4647 ; + .dw 0x4648 ; + .dw 0x4649 ; + .dw 0x464A ; + .dw 0x464B ; + .dw 0x464C ; + .dw 0x464D ; + .dw 0x464E ; + .dw 0x464F ; + .dw 0x4650 ; + .dw 0x4651 ; + .dw 0x4652 ; + .dw 0x4653 ; + .dw 0x4654 ; + .dw 0x4655 ; + .dw 0x4656 ; + .dw 0x4657 ; + .dw 0x4658 ; + .dw 0x4659 ; + .dw 0x465A ; + .dw 0x465B ; + .dw 0x465C ; + .dw 0x465D ; + .dw 0x465E ; + .dw 0x465F ; + .dw 0x4660 ; + .dw 0x4661 ; + .dw 0x4662 ; + .dw 0x4663 ; + .dw 0x4664 ; + .dw 0x4665 ; + .dw 0x4666 ; + .dw 0x4667 ; + .dw 0x4668 ; + .dw 0x4669 ; + .dw 0x466A ; + .dw 0x466B ; + .dw 0x466C ; + .dw 0x466D ; + .dw 0x466E ; + .dw 0x466F ; + .dw 0x4670 ; + .dw 0x4671 ; + .dw 0x4672 ; + .dw 0x4673 ; + .dw 0x4674 ; + .dw 0x4675 ; + .dw 0x4676 ; + .dw 0x4677 ; + .dw 0x4678 ; + .dw 0x4679 ; + .dw 0x467A ; + .dw 0x467B ; + .dw 0x467C ; + .dw 0x467D ; + .dw 0x467E ; + .dw 0x467F ; + .dw 0x4680 ; + .dw 0x4681 ; + .dw 0x4682 ; + .dw 0x4683 ; + .dw 0x4684 ; + .dw 0x4685 ; + .dw 0x4686 ; + .dw 0x4687 ; + .dw 0x4688 ; + .dw 0x4689 ; + .dw 0x468A ; + .dw 0x468B ; + .dw 0x468C ; + .dw 0x468D ; + .dw 0x468E ; + .dw 0x468F ; + .dw 0x4690 ; + .dw 0x4691 ; + .dw 0x4692 ; + .dw 0x4693 ; + .dw 0x4694 ; + .dw 0x4695 ; + .dw 0x4696 ; + .dw 0x4697 ; + .dw 0x4698 ; + .dw 0x4699 ; + .dw 0x469A ; + .dw 0x469B ; + .dw 0x469C ; + .dw 0x469D ; + .dw 0x469E ; + .dw 0x469F ; + .dw 0x46A0 ; + .dw 0x46A1 ; + .dw 0x46A2 ; + .dw 0x46A3 ; + .dw 0x46A4 ; + .dw 0x46A5 ; + .dw 0x46A6 ; + .dw 0x46A7 ; + .dw 0x46A8 ; + .dw 0x46A9 ; + .dw 0x46AA ; + .dw 0x46AB ; + .dw 0x46AC ; + .dw 0x46AD ; + .dw 0x46AE ; + .dw 0x46AF ; + .dw 0x46B0 ; + .dw 0x46B1 ; + .dw 0x46B2 ; + .dw 0x46B3 ; + .dw 0x46B4 ; + .dw 0x46B5 ; + .dw 0x46B6 ; + .dw 0x46B7 ; + .dw 0x46B8 ; + .dw 0x46B9 ; + .dw 0x46BA ; + .dw 0x46BB ; + .dw 0x46BC ; + .dw 0x46BD ; + .dw 0x46BE ; + .dw 0x46BF ; + .dw 0x46C0 ; + .dw 0x46C1 ; + .dw 0x46C2 ; + .dw 0x46C3 ; + .dw 0x46C4 ; + .dw 0x46C5 ; + .dw 0x46C6 ; + .dw 0x46C7 ; + .dw 0x46C8 ; + .dw 0x46C9 ; + .dw 0x46CA ; + .dw 0x46CB ; + .dw 0x46CC ; + .dw 0x46CD ; + .dw 0x46CE ; + .dw 0x46CF ; + .dw 0x46D0 ; + .dw 0x46D1 ; + .dw 0x46D2 ; + .dw 0x46D3 ; + .dw 0x46D4 ; + .dw 0x46D5 ; + .dw 0x46D6 ; + .dw 0x46D7 ; + .dw 0x46D8 ; + .dw 0x46D9 ; + .dw 0x46DA ; + .dw 0x46DB ; + .dw 0x46DC ; + .dw 0x46DD ; + .dw 0x46DE ; + .dw 0x46DF ; + .dw 0x46E0 ; + .dw 0x46E1 ; + .dw 0x46E2 ; + .dw 0x46E3 ; + .dw 0x46E4 ; + .dw 0x46E5 ; + .dw 0x46E6 ; + .dw 0x46E7 ; + .dw 0x46E8 ; + .dw 0x46E9 ; + .dw 0x46EA ; + .dw 0x46EB ; + .dw 0x46EC ; + .dw 0x46ED ; + .dw 0x46EE ; + .dw 0x46EF ; + .dw 0x46F0 ; + .dw 0x46F1 ; + .dw 0x46F2 ; + .dw 0x46F3 ; + .dw 0x46F4 ; + .dw 0x46F5 ; + .dw 0x46F6 ; + .dw 0x46F7 ; + .dw 0x46F8 ; + .dw 0x46F9 ; + .dw 0x46FA ; + .dw 0x46FB ; + .dw 0x46FC ; + .dw 0x46FD ; + .dw 0x46FE ; + .dw 0x46FF ; + .dw 0x4700 ; + .dw 0x4701 ; + .dw 0x4702 ; + .dw 0x4703 ; + .dw 0x4704 ; + .dw 0x4705 ; + .dw 0x4706 ; + .dw 0x4707 ; + .dw 0x4708 ; + .dw 0x4709 ; + .dw 0x470A ; + .dw 0x470B ; + .dw 0x470C ; + .dw 0x470D ; + .dw 0x470E ; + .dw 0x470F ; + .dw 0x4710 ; + .dw 0x4711 ; + .dw 0x4712 ; + .dw 0x4713 ; + .dw 0x4714 ; + .dw 0x4715 ; + .dw 0x4716 ; + .dw 0x4717 ; + .dw 0x4718 ; + .dw 0x4719 ; + .dw 0x471A ; + .dw 0x471B ; + .dw 0x471C ; + .dw 0x471D ; + .dw 0x471E ; + .dw 0x471F ; + .dw 0x4720 ; + .dw 0x4721 ; + .dw 0x4722 ; + .dw 0x4723 ; + .dw 0x4724 ; + .dw 0x4725 ; + .dw 0x4726 ; + .dw 0x4727 ; + .dw 0x4728 ; + .dw 0x4729 ; + .dw 0x472A ; + .dw 0x472B ; + .dw 0x472C ; + .dw 0x472D ; + .dw 0x472E ; + .dw 0x472F ; + .dw 0x4730 ; + .dw 0x4731 ; + .dw 0x4732 ; + .dw 0x4733 ; + .dw 0x4734 ; + .dw 0x4735 ; + .dw 0x4736 ; + .dw 0x4737 ; + .dw 0x4738 ; + .dw 0x4739 ; + .dw 0x473A ; + .dw 0x473B ; + .dw 0x473C ; + .dw 0x473D ; + .dw 0x473E ; + .dw 0x473F ; + .dw 0x4740 ; + .dw 0x4741 ; + .dw 0x4742 ; + .dw 0x4743 ; + .dw 0x4744 ; + .dw 0x4745 ; + .dw 0x4746 ; + .dw 0x4747 ; + .dw 0x4748 ; + .dw 0x4749 ; + .dw 0x474A ; + .dw 0x474B ; + .dw 0x474C ; + .dw 0x474D ; + .dw 0x474E ; + .dw 0x474F ; + .dw 0x4750 ; + .dw 0x4751 ; + .dw 0x4752 ; + .dw 0x4753 ; + .dw 0x4754 ; + .dw 0x4755 ; + .dw 0x4756 ; + .dw 0x4757 ; + .dw 0x4758 ; + .dw 0x4759 ; + .dw 0x475A ; + .dw 0x475B ; + .dw 0x475C ; + .dw 0x475D ; + .dw 0x475E ; + .dw 0x475F ; + .dw 0x4760 ; + .dw 0x4761 ; + .dw 0x4762 ; + .dw 0x4763 ; + .dw 0x4764 ; + .dw 0x4765 ; + .dw 0x4766 ; + .dw 0x4767 ; + .dw 0x4768 ; + .dw 0x4769 ; + .dw 0x476A ; + .dw 0x476B ; + .dw 0x476C ; + .dw 0x476D ; + .dw 0x476E ; + .dw 0x476F ; + .dw 0x4770 ; + .dw 0x4771 ; + .dw 0x4772 ; + .dw 0x4773 ; + .dw 0x4774 ; + .dw 0x4775 ; + .dw 0x4776 ; + .dw 0x4777 ; + .dw 0x4778 ; + .dw 0x4779 ; + .dw 0x477A ; + .dw 0x477B ; + .dw 0x477C ; + .dw 0x477D ; + .dw 0x477E ; + .dw 0x477F ; + .dw 0x4780 ; + .dw 0x4781 ; + .dw 0x4782 ; + .dw 0x4783 ; + .dw 0x4784 ; + .dw 0x4785 ; + .dw 0x4786 ; + .dw 0x4787 ; + .dw 0x4788 ; + .dw 0x4789 ; + .dw 0x478A ; + .dw 0x478B ; + .dw 0x478C ; + .dw 0x478D ; + .dw 0x478E ; + .dw 0x478F ; + .dw 0x4790 ; + .dw 0x4791 ; + .dw 0x4792 ; + .dw 0x4793 ; + .dw 0x4794 ; + .dw 0x4795 ; + .dw 0x4796 ; + .dw 0x4797 ; + .dw 0x4798 ; + .dw 0x4799 ; + .dw 0x479A ; + .dw 0x479B ; + .dw 0x479C ; + .dw 0x479D ; + .dw 0x479E ; + .dw 0x479F ; + .dw 0x47A0 ; + .dw 0x47A1 ; + .dw 0x47A2 ; + .dw 0x47A3 ; + .dw 0x47A4 ; + .dw 0x47A5 ; + .dw 0x47A6 ; + .dw 0x47A7 ; + .dw 0x47A8 ; + .dw 0x47A9 ; + .dw 0x47AA ; + .dw 0x47AB ; + .dw 0x47AC ; + .dw 0x47AD ; + .dw 0x47AE ; + .dw 0x47AF ; + .dw 0x47B0 ; + .dw 0x47B1 ; + .dw 0x47B2 ; + .dw 0x47B3 ; + .dw 0x47B4 ; + .dw 0x47B5 ; + .dw 0x47B6 ; + .dw 0x47B7 ; + .dw 0x47B8 ; + .dw 0x47B9 ; + .dw 0x47BA ; + .dw 0x47BB ; + .dw 0x47BC ; + .dw 0x47BD ; + .dw 0x47BE ; + .dw 0x47BF ; + .dw 0x47C0 ; + .dw 0x47C1 ; + .dw 0x47C2 ; + .dw 0x47C3 ; + .dw 0x47C4 ; + .dw 0x47C5 ; + .dw 0x47C6 ; + .dw 0x47C7 ; + .dw 0x47C8 ; + .dw 0x47C9 ; + .dw 0x47CA ; + .dw 0x47CB ; + .dw 0x47CC ; + .dw 0x47CD ; + .dw 0x47CE ; + .dw 0x47CF ; + .dw 0x47D0 ; + .dw 0x47D1 ; + .dw 0x47D2 ; + .dw 0x47D3 ; + .dw 0x47D4 ; + .dw 0x47D5 ; + .dw 0x47D6 ; + .dw 0x47D7 ; + .dw 0x47D8 ; + .dw 0x47D9 ; + .dw 0x47DA ; + .dw 0x47DB ; + .dw 0x47DC ; + .dw 0x47DD ; + .dw 0x47DE ; + .dw 0x47DF ; + .dw 0x47E0 ; + .dw 0x47E1 ; + .dw 0x47E2 ; + .dw 0x47E3 ; + .dw 0x47E4 ; + .dw 0x47E5 ; + .dw 0x47E6 ; + .dw 0x47E7 ; + .dw 0x47E8 ; + .dw 0x47E9 ; + .dw 0x47EA ; + .dw 0x47EB ; + .dw 0x47EC ; + .dw 0x47ED ; + .dw 0x47EE ; + .dw 0x47EF ; + .dw 0x47F0 ; + .dw 0x47F1 ; + .dw 0x47F2 ; + .dw 0x47F3 ; + .dw 0x47F4 ; + .dw 0x47F5 ; + .dw 0x47F6 ; + .dw 0x47F7 ; + .dw 0x47F8 ; + .dw 0x47F9 ; + .dw 0x47FA ; + .dw 0x47FB ; + .dw 0x47FC ; + .dw 0x47FD ; + .dw 0x47FE ; + .dw 0x47FF ; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +CHECKREG(r5, 830); // count of all 16 bit UI's. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 16 bit illegal opcode handler - skips bad instruction + + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + +JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + R7 += 2; // skip offending 16 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_undefinedinstruction2.S b/sim/testsuite/bfin/se_undefinedinstruction2.S new file mode 100644 index 0000000..d21e375 --- /dev/null +++ b/sim/testsuite/bfin/se_undefinedinstruction2.S @@ -0,0 +1,3147 @@ +//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction2/se_undefinedinstruction2.dsp +// Description: 16 bit special cases Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + A0 = 0; // reset accumulators + A1 = 0; + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); +r4 = p1; + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // count of UI's will be in r5, which was initialized to 0 by header + +// 16 bit special cases COUNT = 830 + .dw 0x10E ; + .dw 0x124 ; +.ifndef BFIN_HW + // XXX: hardware doesnt trigger illegal exception ? + .dw 0x125 ; +.endif + .dw 0x164 ; +.ifndef BFIN_HW + // XXX: hardware doesnt trigger illegal exception ? + .dw 0x165 ; +.endif + .dw 0x128 ; + .dw 0x129 ; + .dw 0x12A ; + .dw 0x12B ; + .dw 0x12C ; + .dw 0x12D ; + .dw 0x12E ; + .dw 0x12F ; + .dw 0x168 ; + .dw 0x169 ; + .dw 0x16A ; + .dw 0x16B ; + .dw 0x16C ; + .dw 0x16D ; + .dw 0x16E ; + .dw 0x16F ; +#if 0 + // EMUDAT = [SP++]; is valid + .dw 0x13F ; + // [SP++] = EMUDAT; is valid + .dw 0x17F ; +#endif + .dw 0x486 ; + .dw 0x487 ; + .dw 0x210 ; + .dw 0x211 ; + .dw 0x212 ; + .dw 0x213 ; + .dw 0x214 ; + .dw 0x215 ; + .dw 0x216 ; + .dw 0x217 ; + .dw 0x305 ; +#if 0 + // Not documented, but hardware takes them + // CC = + .dw 0x307 ; + .dw 0x308 ; + .dw 0x309 ; + .dw 0x30A ; + .dw 0x30B ; + .dw 0x30C ; + .dw 0x30D ; + .dw 0x30E ; + .dw 0x30F ; + .dw 0x310 ; + .dw 0x311 ; + .dw 0x312 ; + .dw 0x313 ; + .dw 0x314 ; + .dw 0x315 ; + .dw 0x316 ; + .dw 0x317 ; + .dw 0x318 ; + .dw 0x319 ; + .dw 0x31A ; + .dw 0x31B ; + .dw 0x31C ; + .dw 0x31D ; + .dw 0x31E ; + .dw 0x31F ; +#endif + .dw 0x325 ; +#if 0 + // Not documented, but hardware takes them + // CC |= + .dw 0x327 ; + .dw 0x328 ; + .dw 0x329 ; + .dw 0x32A ; + .dw 0x32B ; + .dw 0x32C ; + .dw 0x32D ; + .dw 0x32E ; + .dw 0x32F ; + .dw 0x330 ; + .dw 0x331 ; + .dw 0x332 ; + .dw 0x333 ; + .dw 0x334 ; + .dw 0x335 ; + .dw 0x336 ; + .dw 0x337 ; + .dw 0x338 ; + .dw 0x339 ; + .dw 0x33A ; + .dw 0x33B ; + .dw 0x33C ; + .dw 0x33D ; + .dw 0x33E ; + .dw 0x33F ; +#endif + .dw 0x345 ; +#if 0 + // Not documented, but hardware takes them + // CC &= + .dw 0x347 ; + .dw 0x348 ; + .dw 0x349 ; + .dw 0x34A ; + .dw 0x34B ; + .dw 0x34C ; + .dw 0x34D ; + .dw 0x34E ; + .dw 0x34F ; + .dw 0x350 ; + .dw 0x351 ; + .dw 0x352 ; + .dw 0x353 ; + .dw 0x354 ; + .dw 0x355 ; + .dw 0x356 ; + .dw 0x357 ; + .dw 0x358 ; + .dw 0x359 ; + .dw 0x35A ; + .dw 0x35B ; + .dw 0x35C ; + .dw 0x35D ; + .dw 0x35E ; + .dw 0x35F ; +#endif + .dw 0x365 ; +#if 0 + // Not documented, but hardware takes them + // CC ^= + .dw 0x367 ; + .dw 0x368 ; + .dw 0x369 ; + .dw 0x36A ; + .dw 0x36B ; + .dw 0x36C ; + .dw 0x36D ; + .dw 0x36E ; + .dw 0x36F ; + .dw 0x370 ; + .dw 0x371 ; + .dw 0x372 ; + .dw 0x373 ; + .dw 0x374 ; + .dw 0x375 ; + .dw 0x376 ; + .dw 0x377 ; + .dw 0x378 ; + .dw 0x379 ; + .dw 0x37A ; + .dw 0x37B ; + .dw 0x37C ; + .dw 0x37D ; + .dw 0x37E ; + .dw 0x37F ; +#endif + .dw 0x385 ; +#if 0 + // Not documented, but hardware takes them + // = CC + .dw 0x387 ; + .dw 0x388 ; + .dw 0x389 ; + .dw 0x38A ; + .dw 0x38B ; + .dw 0x38C ; + .dw 0x38D ; + .dw 0x38E ; + .dw 0x38F ; + .dw 0x390 ; + .dw 0x391 ; + .dw 0x392 ; + .dw 0x393 ; + .dw 0x394 ; + .dw 0x395 ; + .dw 0x396 ; + .dw 0x397 ; + .dw 0x398 ; + .dw 0x399 ; + .dw 0x39A ; + .dw 0x39B ; + .dw 0x39C ; + .dw 0x39D ; + .dw 0x39E ; + .dw 0x39F ; +#endif + .dw 0x3A5 ; +#if 0 + // Not documented, but hardware takes them + // |= CC + .dw 0x3A7 ; + .dw 0x3A8 ; + .dw 0x3A9 ; + .dw 0x3AA ; + .dw 0x3AB ; + .dw 0x3AC ; + .dw 0x3AD ; + .dw 0x3AE ; + .dw 0x3AF ; + .dw 0x3B0 ; + .dw 0x3B1 ; + .dw 0x3B2 ; + .dw 0x3B3 ; + .dw 0x3B4 ; + .dw 0x3B5 ; + .dw 0x3B6 ; + .dw 0x3B7 ; + .dw 0x3B8 ; + .dw 0x3B9 ; + .dw 0x3BA ; + .dw 0x3BB ; + .dw 0x3BC ; + .dw 0x3BD ; + .dw 0x3BE ; + .dw 0x3BF ; +#endif + .dw 0x3C5 ; +#if 0 + // Not documented, but hardware takes them + // &= CC + .dw 0x3C7 ; + .dw 0x3C8 ; + .dw 0x3C9 ; + .dw 0x3CA ; + .dw 0x3CB ; + .dw 0x3CC ; + .dw 0x3CD ; + .dw 0x3CE ; + .dw 0x3CF ; + .dw 0x3D0 ; + .dw 0x3D1 ; + .dw 0x3D2 ; + .dw 0x3D3 ; + .dw 0x3D4 ; + .dw 0x3D5 ; + .dw 0x3D6 ; + .dw 0x3D7 ; + .dw 0x3D8 ; + .dw 0x3D9 ; + .dw 0x3DA ; + .dw 0x3DB ; + .dw 0x3DC ; + .dw 0x3DD ; + .dw 0x3DE ; + .dw 0x3DF ; +#endif + .dw 0x3E5 ; +#if 0 + // Not documented, but hardware takes them + // ^= CC + .dw 0x3E7 ; + .dw 0x3E8 ; + .dw 0x3E9 ; + .dw 0x3EA ; + .dw 0x3EB ; + .dw 0x3EC ; + .dw 0x3ED ; + .dw 0x3EE ; + .dw 0x3EF ; + .dw 0x3F0 ; + .dw 0x3F1 ; + .dw 0x3F2 ; + .dw 0x3F3 ; + .dw 0x3F4 ; + .dw 0x3F5 ; + .dw 0x3F6 ; + .dw 0x3F7 ; + .dw 0x3F8 ; + .dw 0x3F9 ; + .dw 0x3FA ; + .dw 0x3FB ; + .dw 0x3FC ; + .dw 0x3FD ; + .dw 0x3FE ; + .dw 0x3FF ; +#endif + .dw 0x3A00 ; + .dw 0x3A01 ; + .dw 0x3A02 ; + .dw 0x3A03 ; + .dw 0x3A04 ; + .dw 0x3A05 ; + .dw 0x3A06 ; + .dw 0x3A07 ; + .dw 0x3A08 ; + .dw 0x3A09 ; + .dw 0x3A0A ; + .dw 0x3A0B ; + .dw 0x3A0C ; + .dw 0x3A0D ; + .dw 0x3A0E ; + .dw 0x3A0F ; + .dw 0x3A10 ; + .dw 0x3A11 ; + .dw 0x3A12 ; + .dw 0x3A13 ; + .dw 0x3A14 ; + .dw 0x3A15 ; + .dw 0x3A16 ; + .dw 0x3A17 ; + .dw 0x3A18 ; + .dw 0x3A19 ; + .dw 0x3A1A ; + .dw 0x3A1B ; + .dw 0x3A1C ; + .dw 0x3A1D ; + .dw 0x3A1E ; + .dw 0x3A1F ; + .dw 0x3A20 ; + .dw 0x3A21 ; + .dw 0x3A22 ; + .dw 0x3A23 ; + .dw 0x3A24 ; + .dw 0x3A25 ; + .dw 0x3A26 ; + .dw 0x3A27 ; + .dw 0x3A28 ; + .dw 0x3A29 ; + .dw 0x3A2A ; + .dw 0x3A2B ; + .dw 0x3A2C ; + .dw 0x3A2D ; + .dw 0x3A2E ; + .dw 0x3A2F ; + .dw 0x3A30 ; + .dw 0x3A31 ; + .dw 0x3A32 ; + .dw 0x3A33 ; + .dw 0x3A34 ; + .dw 0x3A35 ; + .dw 0x3A36 ; + .dw 0x3A37 ; + .dw 0x3A38 ; + .dw 0x3A39 ; + .dw 0x3A3A ; + .dw 0x3A3B ; + .dw 0x3A3C ; + .dw 0x3A3D ; + .dw 0x3A3E ; + .dw 0x3A3F ; + .dw 0x3A40 ; + .dw 0x3A41 ; + .dw 0x3A42 ; + .dw 0x3A43 ; + .dw 0x3A44 ; + .dw 0x3A45 ; + .dw 0x3A46 ; + .dw 0x3A47 ; + .dw 0x3A48 ; + .dw 0x3A49 ; + .dw 0x3A4A ; + .dw 0x3A4B ; + .dw 0x3A4C ; + .dw 0x3A4D ; + .dw 0x3A4E ; + .dw 0x3A4F ; + .dw 0x3A50 ; + .dw 0x3A51 ; + .dw 0x3A52 ; + .dw 0x3A53 ; + .dw 0x3A54 ; + .dw 0x3A55 ; + .dw 0x3A56 ; + .dw 0x3A57 ; + .dw 0x3A58 ; + .dw 0x3A59 ; + .dw 0x3A5A ; + .dw 0x3A5B ; + .dw 0x3A5C ; + .dw 0x3A5D ; + .dw 0x3A5E ; + .dw 0x3A5F ; + .dw 0x3A60 ; + .dw 0x3A61 ; + .dw 0x3A62 ; + .dw 0x3A63 ; + .dw 0x3A64 ; + .dw 0x3A65 ; + .dw 0x3A66 ; + .dw 0x3A67 ; + .dw 0x3A68 ; + .dw 0x3A69 ; + .dw 0x3A6A ; + .dw 0x3A6B ; + .dw 0x3A6C ; + .dw 0x3A6D ; + .dw 0x3A6E ; + .dw 0x3A6F ; + .dw 0x3A70 ; + .dw 0x3A71 ; + .dw 0x3A72 ; + .dw 0x3A73 ; + .dw 0x3A74 ; + .dw 0x3A75 ; + .dw 0x3A76 ; + .dw 0x3A77 ; + .dw 0x3A78 ; + .dw 0x3A79 ; + .dw 0x3A7A ; + .dw 0x3A7B ; + .dw 0x3A7C ; + .dw 0x3A7D ; + .dw 0x3A7E ; + .dw 0x3A7F ; + .dw 0x3A80 ; + .dw 0x3A81 ; + .dw 0x3A82 ; + .dw 0x3A83 ; + .dw 0x3A84 ; + .dw 0x3A85 ; + .dw 0x3A86 ; + .dw 0x3A87 ; + .dw 0x3A88 ; + .dw 0x3A89 ; + .dw 0x3A8A ; + .dw 0x3A8B ; + .dw 0x3A8C ; + .dw 0x3A8D ; + .dw 0x3A8E ; + .dw 0x3A8F ; + .dw 0x3A90 ; + .dw 0x3A91 ; + .dw 0x3A92 ; + .dw 0x3A93 ; + .dw 0x3A94 ; + .dw 0x3A95 ; + .dw 0x3A96 ; + .dw 0x3A97 ; + .dw 0x3A98 ; + .dw 0x3A99 ; + .dw 0x3A9A ; + .dw 0x3A9B ; + .dw 0x3A9C ; + .dw 0x3A9D ; + .dw 0x3A9E ; + .dw 0x3A9F ; + .dw 0x3AA0 ; + .dw 0x3AA1 ; + .dw 0x3AA2 ; + .dw 0x3AA3 ; + .dw 0x3AA4 ; + .dw 0x3AA5 ; + .dw 0x3AA6 ; + .dw 0x3AA7 ; + .dw 0x3AA8 ; + .dw 0x3AA9 ; + .dw 0x3AAA ; + .dw 0x3AAB ; + .dw 0x3AAC ; + .dw 0x3AAD ; + .dw 0x3AAE ; + .dw 0x3AAF ; + .dw 0x3AB0 ; + .dw 0x3AB1 ; + .dw 0x3AB2 ; + .dw 0x3AB3 ; + .dw 0x3AB4 ; + .dw 0x3AB5 ; + .dw 0x3AB6 ; + .dw 0x3AB7 ; + .dw 0x3AB8 ; + .dw 0x3AB9 ; + .dw 0x3ABA ; + .dw 0x3ABB ; + .dw 0x3ABC ; + .dw 0x3ABD ; + .dw 0x3ABE ; + .dw 0x3ABF ; + .dw 0x3AC0 ; + .dw 0x3AC1 ; + .dw 0x3AC2 ; + .dw 0x3AC3 ; + .dw 0x3AC4 ; + .dw 0x3AC5 ; + .dw 0x3AC6 ; + .dw 0x3AC7 ; + .dw 0x3AC8 ; + .dw 0x3AC9 ; + .dw 0x3ACA ; + .dw 0x3ACB ; + .dw 0x3ACC ; + .dw 0x3ACD ; + .dw 0x3ACE ; + .dw 0x3ACF ; + .dw 0x3AD0 ; + .dw 0x3AD1 ; + .dw 0x3AD2 ; + .dw 0x3AD3 ; + .dw 0x3AD4 ; + .dw 0x3AD5 ; + .dw 0x3AD6 ; + .dw 0x3AD7 ; + .dw 0x3AD8 ; + .dw 0x3AD9 ; + .dw 0x3ADA ; + .dw 0x3ADB ; + .dw 0x3ADC ; + .dw 0x3ADD ; + .dw 0x3ADE ; + .dw 0x3ADF ; + .dw 0x3AE0 ; + .dw 0x3AE1 ; + .dw 0x3AE2 ; + .dw 0x3AE3 ; + .dw 0x3AE4 ; + .dw 0x3AE5 ; + .dw 0x3AE6 ; + .dw 0x3AE7 ; + .dw 0x3AE8 ; + .dw 0x3AE9 ; + .dw 0x3AEA ; + .dw 0x3AEB ; + .dw 0x3AEC ; + .dw 0x3AED ; + .dw 0x3AEE ; + .dw 0x3AEF ; + .dw 0x3AF0 ; + .dw 0x3AF1 ; + .dw 0x3AF2 ; + .dw 0x3AF3 ; + .dw 0x3AF4 ; + .dw 0x3AF5 ; + .dw 0x3AF6 ; + .dw 0x3AF7 ; + .dw 0x3AF8 ; + .dw 0x3AF9 ; + .dw 0x3AFA ; + .dw 0x3AFB ; + .dw 0x3AFC ; + .dw 0x3AFD ; + .dw 0x3AFE ; + .dw 0x3AFF ; + .dw 0x3B00 ; + .dw 0x3B01 ; + .dw 0x3B02 ; + .dw 0x3B03 ; + .dw 0x3B04 ; + .dw 0x3B05 ; + .dw 0x3B06 ; + .dw 0x3B07 ; + .dw 0x3B08 ; + .dw 0x3B09 ; + .dw 0x3B0A ; + .dw 0x3B0B ; + .dw 0x3B0C ; + .dw 0x3B0D ; + .dw 0x3B0E ; + .dw 0x3B0F ; + .dw 0x3B10 ; + .dw 0x3B11 ; + .dw 0x3B12 ; + .dw 0x3B13 ; + .dw 0x3B14 ; + .dw 0x3B15 ; + .dw 0x3B16 ; + .dw 0x3B17 ; + .dw 0x3B18 ; + .dw 0x3B19 ; + .dw 0x3B1A ; + .dw 0x3B1B ; + .dw 0x3B1C ; + .dw 0x3B1D ; + .dw 0x3B1E ; + .dw 0x3B1F ; + .dw 0x3B20 ; + .dw 0x3B21 ; + .dw 0x3B22 ; + .dw 0x3B23 ; + .dw 0x3B24 ; + .dw 0x3B25 ; + .dw 0x3B26 ; + .dw 0x3B27 ; + .dw 0x3B28 ; + .dw 0x3B29 ; + .dw 0x3B2A ; + .dw 0x3B2B ; + .dw 0x3B2C ; + .dw 0x3B2D ; + .dw 0x3B2E ; + .dw 0x3B2F ; + .dw 0x3B30 ; + .dw 0x3B31 ; + .dw 0x3B32 ; + .dw 0x3B33 ; + .dw 0x3B34 ; + .dw 0x3B35 ; + .dw 0x3B36 ; + .dw 0x3B37 ; + .dw 0x3B38 ; + .dw 0x3B39 ; + .dw 0x3B3A ; + .dw 0x3B3B ; + .dw 0x3B3C ; + .dw 0x3B3D ; + .dw 0x3B3E ; + .dw 0x3B3F ; + .dw 0x3B40 ; + .dw 0x3B41 ; + .dw 0x3B42 ; + .dw 0x3B43 ; + .dw 0x3B44 ; + .dw 0x3B45 ; + .dw 0x3B46 ; + .dw 0x3B47 ; + .dw 0x3B48 ; + .dw 0x3B49 ; + .dw 0x3B4A ; + .dw 0x3B4B ; + .dw 0x3B4C ; + .dw 0x3B4D ; + .dw 0x3B4E ; + .dw 0x3B4F ; + .dw 0x3B50 ; + .dw 0x3B51 ; + .dw 0x3B52 ; + .dw 0x3B53 ; + .dw 0x3B54 ; + .dw 0x3B55 ; + .dw 0x3B56 ; + .dw 0x3B57 ; + .dw 0x3B58 ; + .dw 0x3B59 ; + .dw 0x3B5A ; + .dw 0x3B5B ; + .dw 0x3B5C ; + .dw 0x3B5D ; + .dw 0x3B5E ; + .dw 0x3B5F ; + .dw 0x3B60 ; + .dw 0x3B61 ; + .dw 0x3B62 ; + .dw 0x3B63 ; + .dw 0x3B64 ; + .dw 0x3B65 ; + .dw 0x3B66 ; + .dw 0x3B67 ; + .dw 0x3B68 ; + .dw 0x3B69 ; + .dw 0x3B6A ; + .dw 0x3B6B ; + .dw 0x3B6C ; + .dw 0x3B6D ; + .dw 0x3B6E ; + .dw 0x3B6F ; + .dw 0x3B70 ; + .dw 0x3B71 ; + .dw 0x3B72 ; + .dw 0x3B73 ; + .dw 0x3B74 ; + .dw 0x3B75 ; + .dw 0x3B76 ; + .dw 0x3B77 ; + .dw 0x3B78 ; + .dw 0x3B79 ; + .dw 0x3B7A ; + .dw 0x3B7B ; + .dw 0x3B7C ; + .dw 0x3B7D ; + .dw 0x3B7E ; + .dw 0x3B7F ; + .dw 0x3B80 ; + .dw 0x3B81 ; + .dw 0x3B82 ; + .dw 0x3B83 ; + .dw 0x3B84 ; + .dw 0x3B85 ; + .dw 0x3B86 ; + .dw 0x3B87 ; + .dw 0x3B88 ; + .dw 0x3B89 ; + .dw 0x3B8A ; + .dw 0x3B8B ; + .dw 0x3B8C ; + .dw 0x3B8D ; + .dw 0x3B8E ; + .dw 0x3B8F ; + .dw 0x3B90 ; + .dw 0x3B91 ; + .dw 0x3B92 ; + .dw 0x3B93 ; + .dw 0x3B94 ; + .dw 0x3B95 ; + .dw 0x3B96 ; + .dw 0x3B97 ; + .dw 0x3B98 ; + .dw 0x3B99 ; + .dw 0x3B9A ; + .dw 0x3B9B ; + .dw 0x3B9C ; + .dw 0x3B9D ; + .dw 0x3B9E ; + .dw 0x3B9F ; + .dw 0x3BA0 ; + .dw 0x3BA1 ; + .dw 0x3BA2 ; + .dw 0x3BA3 ; + .dw 0x3BA4 ; + .dw 0x3BA5 ; + .dw 0x3BA6 ; + .dw 0x3BA7 ; + .dw 0x3BA8 ; + .dw 0x3BA9 ; + .dw 0x3BAA ; + .dw 0x3BAB ; + .dw 0x3BAC ; + .dw 0x3BAD ; + .dw 0x3BAE ; + .dw 0x3BAF ; + .dw 0x3BB0 ; + .dw 0x3BB1 ; + .dw 0x3BB2 ; + .dw 0x3BB3 ; + .dw 0x3BB4 ; + .dw 0x3BB5 ; + .dw 0x3BB6 ; + .dw 0x3BB7 ; + .dw 0x3BB8 ; + .dw 0x3BB9 ; + .dw 0x3BBA ; + .dw 0x3BBB ; + .dw 0x3BBC ; + .dw 0x3BBD ; + .dw 0x3BBE ; + .dw 0x3BBF ; + .dw 0x3BC0 ; + .dw 0x3BC1 ; + .dw 0x3BC2 ; + .dw 0x3BC3 ; + .dw 0x3BC4 ; + .dw 0x3BC5 ; + .dw 0x3BC6 ; + .dw 0x3BC7 ; + .dw 0x3BC8 ; + .dw 0x3BC9 ; + .dw 0x3BCA ; + .dw 0x3BCB ; + .dw 0x3BCC ; + .dw 0x3BCD ; + .dw 0x3BCE ; + .dw 0x3BCF ; + .dw 0x3BD0 ; + .dw 0x3BD1 ; + .dw 0x3BD2 ; + .dw 0x3BD3 ; + .dw 0x3BD4 ; + .dw 0x3BD5 ; + .dw 0x3BD6 ; + .dw 0x3BD7 ; + .dw 0x3BD8 ; + .dw 0x3BD9 ; + .dw 0x3BDA ; + .dw 0x3BDB ; + .dw 0x3BDC ; + .dw 0x3BDD ; + .dw 0x3BDE ; + .dw 0x3BDF ; + .dw 0x3BE0 ; + .dw 0x3BE1 ; + .dw 0x3BE2 ; + .dw 0x3BE3 ; + .dw 0x3BE4 ; + .dw 0x3BE5 ; + .dw 0x3BE6 ; + .dw 0x3BE7 ; + .dw 0x3BE8 ; + .dw 0x3BE9 ; + .dw 0x3BEA ; + .dw 0x3BEB ; + .dw 0x3BEC ; + .dw 0x3BED ; + .dw 0x3BEE ; + .dw 0x3BEF ; + .dw 0x3BF0 ; + .dw 0x3BF1 ; + .dw 0x3BF2 ; + .dw 0x3BF3 ; + .dw 0x3BF4 ; + .dw 0x3BF5 ; + .dw 0x3BF6 ; + .dw 0x3BF7 ; + .dw 0x3BF8 ; + .dw 0x3BF9 ; + .dw 0x3BFA ; + .dw 0x3BFB ; + .dw 0x3BFC ; + .dw 0x3BFD ; + .dw 0x3BFE ; + .dw 0x3BFF ; + .dw 0x3140 ; + .dw 0x3141 ; + .dw 0x3142 ; + .dw 0x3143 ; + .dw 0x3144 ; + .dw 0x3145 ; + .dw 0x3146 ; + .dw 0x3147 ; + .dw 0x3148 ; + .dw 0x3149 ; + .dw 0x314A ; + .dw 0x314B ; + .dw 0x314C ; + .dw 0x314D ; + .dw 0x314E ; + .dw 0x314F ; + .dw 0x3150 ; + .dw 0x3151 ; + .dw 0x3152 ; + .dw 0x3153 ; + .dw 0x3154 ; + .dw 0x3155 ; + .dw 0x3156 ; + .dw 0x3157 ; + .dw 0x3158 ; + .dw 0x3159 ; + .dw 0x315A ; + .dw 0x315B ; + .dw 0x315C ; + .dw 0x315D ; + .dw 0x315E ; + .dw 0x315F ; + .dw 0x3160 ; + .dw 0x3161 ; + .dw 0x3162 ; + .dw 0x3163 ; + .dw 0x3164 ; + .dw 0x3165 ; + .dw 0x3166 ; + .dw 0x3167 ; + .dw 0x3168 ; + .dw 0x3169 ; + .dw 0x316A ; + .dw 0x316B ; + .dw 0x316C ; + .dw 0x316D ; + .dw 0x316E ; + .dw 0x316F ; + .dw 0x3170 ; + .dw 0x3171 ; + .dw 0x3172 ; + .dw 0x3173 ; + .dw 0x3174 ; + .dw 0x3175 ; + .dw 0x3176 ; + .dw 0x3177 ; + .dw 0x3178 ; + .dw 0x3179 ; + .dw 0x317A ; + .dw 0x317B ; + .dw 0x317C ; + .dw 0x317D ; + .dw 0x317E ; + .dw 0x317F ; + .dw 0x3340 ; + .dw 0x3341 ; + .dw 0x3342 ; + .dw 0x3343 ; + .dw 0x3344 ; + .dw 0x3345 ; + .dw 0x3346 ; + .dw 0x3347 ; + .dw 0x3348 ; + .dw 0x3349 ; + .dw 0x334A ; + .dw 0x334B ; + .dw 0x334C ; + .dw 0x334D ; + .dw 0x334E ; + .dw 0x334F ; + .dw 0x3350 ; + .dw 0x3351 ; + .dw 0x3352 ; + .dw 0x3353 ; + .dw 0x3354 ; + .dw 0x3355 ; + .dw 0x3356 ; + .dw 0x3357 ; + .dw 0x3358 ; + .dw 0x3359 ; + .dw 0x335A ; + .dw 0x335B ; + .dw 0x335C ; + .dw 0x335D ; + .dw 0x335E ; + .dw 0x335F ; + .dw 0x3360 ; + .dw 0x3361 ; + .dw 0x3362 ; + .dw 0x3363 ; + .dw 0x3364 ; + .dw 0x3365 ; + .dw 0x3366 ; + .dw 0x3367 ; + .dw 0x3368 ; + .dw 0x3369 ; + .dw 0x336A ; + .dw 0x336B ; + .dw 0x336C ; + .dw 0x336D ; + .dw 0x336E ; + .dw 0x336F ; + .dw 0x3370 ; + .dw 0x3371 ; + .dw 0x3372 ; + .dw 0x3373 ; + .dw 0x3374 ; + .dw 0x3375 ; + .dw 0x3376 ; + .dw 0x3377 ; + .dw 0x3378 ; + .dw 0x3379 ; + .dw 0x337A ; + .dw 0x337B ; + .dw 0x337C ; + .dw 0x337D ; + .dw 0x337E ; + .dw 0x337F ; + .dw 0x3540 ; + .dw 0x3541 ; + .dw 0x3542 ; + .dw 0x3543 ; + .dw 0x3544 ; + .dw 0x3545 ; + .dw 0x3546 ; + .dw 0x3547 ; + .dw 0x3548 ; + .dw 0x3549 ; + .dw 0x354A ; + .dw 0x354B ; + .dw 0x354C ; + .dw 0x354D ; + .dw 0x354E ; + .dw 0x354F ; + .dw 0x3550 ; + .dw 0x3551 ; + .dw 0x3552 ; + .dw 0x3553 ; + .dw 0x3554 ; + .dw 0x3555 ; + .dw 0x3556 ; + .dw 0x3557 ; + .dw 0x3558 ; + .dw 0x3559 ; + .dw 0x355A ; + .dw 0x355B ; + .dw 0x355C ; + .dw 0x355D ; + .dw 0x355E ; + .dw 0x355F ; + .dw 0x3560 ; + .dw 0x3561 ; + .dw 0x3562 ; + .dw 0x3563 ; + .dw 0x3564 ; + .dw 0x3565 ; + .dw 0x3566 ; + .dw 0x3567 ; + .dw 0x3568 ; + .dw 0x3569 ; + .dw 0x356A ; + .dw 0x356B ; + .dw 0x356C ; + .dw 0x356D ; + .dw 0x356E ; + .dw 0x356F ; + .dw 0x3570 ; + .dw 0x3571 ; + .dw 0x3572 ; + .dw 0x3573 ; + .dw 0x3574 ; + .dw 0x3575 ; + .dw 0x3576 ; + .dw 0x3577 ; + .dw 0x3578 ; + .dw 0x3579 ; + .dw 0x357A ; + .dw 0x357B ; + .dw 0x357C ; + .dw 0x357D ; + .dw 0x357E ; + .dw 0x357F ; + .dw 0x3740 ; + .dw 0x3741 ; + .dw 0x3742 ; + .dw 0x3743 ; + .dw 0x3744 ; + .dw 0x3745 ; + .dw 0x3746 ; + .dw 0x3747 ; + .dw 0x3748 ; + .dw 0x3749 ; + .dw 0x374A ; + .dw 0x374B ; + .dw 0x374C ; + .dw 0x374D ; + .dw 0x374E ; + .dw 0x374F ; + .dw 0x3750 ; + .dw 0x3751 ; + .dw 0x3752 ; + .dw 0x3753 ; + .dw 0x3754 ; + .dw 0x3755 ; + .dw 0x3756 ; + .dw 0x3757 ; + .dw 0x3758 ; + .dw 0x3759 ; + .dw 0x375A ; + .dw 0x375B ; + .dw 0x375C ; + .dw 0x375D ; + .dw 0x375E ; + .dw 0x375F ; + .dw 0x3760 ; + .dw 0x3761 ; + .dw 0x3762 ; + .dw 0x3763 ; + .dw 0x3764 ; + .dw 0x3765 ; + .dw 0x3766 ; + .dw 0x3767 ; + .dw 0x3768 ; + .dw 0x3769 ; + .dw 0x376A ; + .dw 0x376B ; + .dw 0x376C ; + .dw 0x376D ; + .dw 0x376E ; + .dw 0x376F ; + .dw 0x3770 ; + .dw 0x3771 ; + .dw 0x3772 ; + .dw 0x3773 ; + .dw 0x3774 ; + .dw 0x3775 ; + .dw 0x3776 ; + .dw 0x3777 ; + .dw 0x3778 ; + .dw 0x3779 ; + .dw 0x377A ; + .dw 0x377B ; + .dw 0x377C ; + .dw 0x377D ; + .dw 0x377E ; + .dw 0x377F ; + .dw 0x3940 ; + .dw 0x3941 ; + .dw 0x3942 ; + .dw 0x3943 ; + .dw 0x3944 ; + .dw 0x3945 ; + .dw 0x3946 ; + .dw 0x3947 ; + .dw 0x3948 ; + .dw 0x3949 ; + .dw 0x394A ; + .dw 0x394B ; + .dw 0x394C ; + .dw 0x394D ; + .dw 0x394E ; + .dw 0x394F ; + .dw 0x3950 ; + .dw 0x3951 ; + .dw 0x3952 ; + .dw 0x3953 ; + .dw 0x3954 ; + .dw 0x3955 ; + .dw 0x3956 ; + .dw 0x3957 ; + .dw 0x3958 ; + .dw 0x3959 ; + .dw 0x395A ; + .dw 0x395B ; + .dw 0x395C ; + .dw 0x395D ; + .dw 0x395E ; + .dw 0x395F ; + .dw 0x3960 ; + .dw 0x3961 ; + .dw 0x3962 ; + .dw 0x3963 ; + .dw 0x3964 ; + .dw 0x3965 ; + .dw 0x3966 ; + .dw 0x3967 ; + .dw 0x3968 ; + .dw 0x3969 ; + .dw 0x396A ; + .dw 0x396B ; + .dw 0x396C ; + .dw 0x396D ; + .dw 0x396E ; + .dw 0x396F ; + .dw 0x3970 ; + .dw 0x3971 ; + .dw 0x3972 ; + .dw 0x3973 ; + .dw 0x3974 ; + .dw 0x3975 ; + .dw 0x3976 ; + .dw 0x3977 ; + .dw 0x3978 ; + .dw 0x3979 ; + .dw 0x397A ; + .dw 0x397B ; + .dw 0x397C ; + .dw 0x397D ; + .dw 0x397E ; + .dw 0x397F ; + .dw 0x3D40 ; + .dw 0x3D41 ; + .dw 0x3D42 ; + .dw 0x3D43 ; + .dw 0x3D44 ; + .dw 0x3D45 ; + .dw 0x3D46 ; + .dw 0x3D47 ; + .dw 0x3D48 ; + .dw 0x3D49 ; + .dw 0x3D4A ; + .dw 0x3D4B ; + .dw 0x3D4C ; + .dw 0x3D4D ; + .dw 0x3D4E ; + .dw 0x3D4F ; + .dw 0x3D50 ; + .dw 0x3D51 ; + .dw 0x3D52 ; + .dw 0x3D53 ; + .dw 0x3D54 ; + .dw 0x3D55 ; + .dw 0x3D56 ; + .dw 0x3D57 ; + .dw 0x3D58 ; + .dw 0x3D59 ; + .dw 0x3D5A ; + .dw 0x3D5B ; + .dw 0x3D5C ; + .dw 0x3D5D ; + .dw 0x3D5E ; + .dw 0x3D5F ; + .dw 0x3D60 ; + .dw 0x3D61 ; + .dw 0x3D62 ; + .dw 0x3D63 ; + .dw 0x3D64 ; + .dw 0x3D65 ; + .dw 0x3D66 ; + .dw 0x3D67 ; + .dw 0x3D68 ; + .dw 0x3D69 ; + .dw 0x3D6A ; + .dw 0x3D6B ; + .dw 0x3D6C ; + .dw 0x3D6D ; + .dw 0x3D6E ; + .dw 0x3D6F ; + .dw 0x3D70 ; + .dw 0x3D71 ; + .dw 0x3D72 ; + .dw 0x3D73 ; + .dw 0x3D74 ; + .dw 0x3D75 ; + .dw 0x3D76 ; + .dw 0x3D77 ; + .dw 0x3D78 ; + .dw 0x3D79 ; + .dw 0x3D7A ; + .dw 0x3D7B ; + .dw 0x3D7C ; + .dw 0x3D7D ; + .dw 0x3D7E ; + .dw 0x3D7F ; + .dw 0x3F40 ; + .dw 0x3F41 ; + .dw 0x3F42 ; + .dw 0x3F43 ; + .dw 0x3F44 ; + .dw 0x3F45 ; + .dw 0x3F46 ; + .dw 0x3F47 ; + .dw 0x3F48 ; + .dw 0x3F49 ; + .dw 0x3F4A ; + .dw 0x3F4B ; + .dw 0x3F4C ; + .dw 0x3F4D ; + .dw 0x3F4E ; + .dw 0x3F4F ; + .dw 0x3F50 ; + .dw 0x3F51 ; + .dw 0x3F52 ; + .dw 0x3F53 ; + .dw 0x3F54 ; + .dw 0x3F55 ; + .dw 0x3F56 ; + .dw 0x3F57 ; + .dw 0x3F58 ; + .dw 0x3F59 ; + .dw 0x3F5A ; + .dw 0x3F5B ; + .dw 0x3F5C ; + .dw 0x3F5D ; + .dw 0x3F5E ; + .dw 0x3F5F ; + .dw 0x3F60 ; + .dw 0x3F61 ; + .dw 0x3F62 ; + .dw 0x3F63 ; + .dw 0x3F64 ; + .dw 0x3F65 ; + .dw 0x3F66 ; + .dw 0x3F67 ; + .dw 0x3F68 ; + .dw 0x3F69 ; + .dw 0x3F6A ; + .dw 0x3F6B ; + .dw 0x3F6C ; + .dw 0x3F6D ; + .dw 0x3F6E ; + .dw 0x3F6F ; + .dw 0x3F70 ; + .dw 0x3F71 ; + .dw 0x3F72 ; + .dw 0x3F73 ; + .dw 0x3F74 ; + .dw 0x3F75 ; + .dw 0x3F76 ; + .dw 0x3F77 ; + .dw 0x3F78 ; + .dw 0x3F79 ; + .dw 0x3F7A ; + .dw 0x3F7B ; + .dw 0x3F7C ; + .dw 0x3F7D ; + .dw 0x3F7E ; + .dw 0x3F7F ; + .dw 0x3104 ; + .dw 0x3105 ; + .dw 0x310C ; + .dw 0x310D ; + .dw 0x3114 ; + .dw 0x3115 ; + .dw 0x311C ; + .dw 0x311D ; + .dw 0x3124 ; + .dw 0x3125 ; + .dw 0x312C ; + .dw 0x312D ; + .dw 0x3134 ; + .dw 0x3135 ; + .dw 0x313C ; + .dw 0x313D ; + .dw 0x3304 ; + .dw 0x3305 ; + .dw 0x330C ; + .dw 0x330D ; + .dw 0x3314 ; + .dw 0x3315 ; + .dw 0x331C ; + .dw 0x331D ; + .dw 0x3324 ; + .dw 0x3325 ; + .dw 0x332C ; + .dw 0x332D ; + .dw 0x3334 ; + .dw 0x3335 ; + .dw 0x333C ; + .dw 0x333D ; + .dw 0x3504 ; + .dw 0x3505 ; + .dw 0x350C ; + .dw 0x350D ; + .dw 0x3514 ; + .dw 0x3515 ; + .dw 0x351C ; + .dw 0x351D ; + .dw 0x3524 ; + .dw 0x3525 ; + .dw 0x352C ; + .dw 0x352D ; + .dw 0x3534 ; + .dw 0x3535 ; + .dw 0x353C ; + .dw 0x353D ; + .dw 0x3704 ; + .dw 0x3705 ; + .dw 0x370C ; + .dw 0x370D ; + .dw 0x3714 ; + .dw 0x3715 ; + .dw 0x371C ; + .dw 0x371D ; + .dw 0x3724 ; + .dw 0x3725 ; + .dw 0x372C ; + .dw 0x372D ; + .dw 0x3734 ; + .dw 0x3735 ; + .dw 0x373C ; + .dw 0x373D ; + .dw 0x3904 ; + .dw 0x3905 ; + .dw 0x390C ; + .dw 0x390D ; + .dw 0x3914 ; + .dw 0x3915 ; + .dw 0x391C ; + .dw 0x391D ; + .dw 0x3924 ; + .dw 0x3925 ; + .dw 0x392C ; + .dw 0x392D ; + .dw 0x3934 ; + .dw 0x3935 ; + .dw 0x393C ; + .dw 0x393D ; + .dw 0x3D04 ; + .dw 0x3D05 ; + .dw 0x3D0C ; + .dw 0x3D0D ; + .dw 0x3D14 ; + .dw 0x3D15 ; + .dw 0x3D1C ; + .dw 0x3D1D ; + .dw 0x3D24 ; + .dw 0x3D25 ; + .dw 0x3D2C ; + .dw 0x3D2D ; + .dw 0x3D34 ; + .dw 0x3D35 ; + .dw 0x3D3C ; + .dw 0x3D3D ; + .dw 0x3F04 ; + .dw 0x3F05 ; + .dw 0x3F0C ; + .dw 0x3F0D ; + .dw 0x3F14 ; + .dw 0x3F15 ; + .dw 0x3F1C ; + .dw 0x3F1D ; + .dw 0x3F24 ; + .dw 0x3F25 ; + .dw 0x3F2C ; + .dw 0x3F2D ; + .dw 0x3F34 ; + .dw 0x3F35 ; + .dw 0x3F3C ; + .dw 0x3F3D ; + .dw 0x3820 ; + .dw 0x3821 ; + .dw 0x3822 ; + .dw 0x3823 ; + .dw 0x3824 ; + .dw 0x3825 ; + .dw 0x3826 ; + .dw 0x3827 ; + .dw 0x3828 ; + .dw 0x3829 ; + .dw 0x382A ; + .dw 0x382B ; + .dw 0x382C ; + .dw 0x382D ; + .dw 0x382E ; + .dw 0x382F ; + .dw 0x3860 ; + .dw 0x3861 ; + .dw 0x3862 ; + .dw 0x3863 ; + .dw 0x3864 ; + .dw 0x3865 ; + .dw 0x3866 ; + .dw 0x3867 ; + .dw 0x3868 ; + .dw 0x3869 ; + .dw 0x386A ; + .dw 0x386B ; + .dw 0x386C ; + .dw 0x386D ; + .dw 0x386E ; + .dw 0x386F ; + .dw 0x38A0 ; + .dw 0x38A1 ; + .dw 0x38A2 ; + .dw 0x38A3 ; + .dw 0x38A4 ; + .dw 0x38A5 ; + .dw 0x38A6 ; + .dw 0x38A7 ; + .dw 0x38A8 ; + .dw 0x38A9 ; + .dw 0x38AA ; + .dw 0x38AB ; + .dw 0x38AC ; + .dw 0x38AD ; + .dw 0x38AE ; + .dw 0x38AF ; + .dw 0x38E0 ; + .dw 0x38E1 ; + .dw 0x38E2 ; + .dw 0x38E3 ; + .dw 0x38E4 ; + .dw 0x38E5 ; + .dw 0x38E6 ; + .dw 0x38E7 ; + .dw 0x38E8 ; + .dw 0x38E9 ; + .dw 0x38EA ; + .dw 0x38EB ; + .dw 0x38EC ; + .dw 0x38ED ; + .dw 0x38EE ; + .dw 0x38EF ; + .dw 0x3920 ; + .dw 0x3921 ; + .dw 0x3922 ; + .dw 0x3923 ; + .dw 0x3924 ; + .dw 0x3925 ; + .dw 0x3926 ; + .dw 0x3927 ; + .dw 0x3928 ; + .dw 0x3929 ; + .dw 0x392A ; + .dw 0x392B ; + .dw 0x392C ; + .dw 0x392D ; + .dw 0x392E ; + .dw 0x392F ; + .dw 0x39A0 ; + .dw 0x39A1 ; + .dw 0x39A2 ; + .dw 0x39A3 ; + .dw 0x39A4 ; + .dw 0x39A5 ; + .dw 0x39A6 ; + .dw 0x39A7 ; + .dw 0x39A8 ; + .dw 0x39A9 ; + .dw 0x39AA ; + .dw 0x39AB ; + .dw 0x39AC ; + .dw 0x39AD ; + .dw 0x39AE ; + .dw 0x39AF ; + .dw 0x39E0 ; + .dw 0x39E1 ; + .dw 0x39E2 ; + .dw 0x39E3 ; + .dw 0x39E4 ; + .dw 0x39E5 ; + .dw 0x39E6 ; + .dw 0x39E7 ; + .dw 0x39E8 ; + .dw 0x39E9 ; + .dw 0x39EA ; + .dw 0x39EB ; + .dw 0x39EC ; + .dw 0x39ED ; + .dw 0x39EE ; + .dw 0x39EF ; +#if 0 + // EMUDAT = Dreg; is valid + .dw 0x3E38 ; + .dw 0x3E39 ; + .dw 0x3E3A ; + .dw 0x3E3B ; + .dw 0x3E3C ; + .dw 0x3E3D ; + .dw 0x3E3E ; + .dw 0x3E3F ; + // EMUDAT = Preg; is valid + .dw 0x3E78 ; + .dw 0x3E79 ; + .dw 0x3E7A ; + .dw 0x3E7B ; + .dw 0x3E7C ; + .dw 0x3E7D ; + .dw 0x3E7E ; + .dw 0x3E7F ; + // EMUDAT = Ireg; is valid + .dw 0x3EB8 ; + .dw 0x3EB9 ; + .dw 0x3EBA ; + .dw 0x3EBB ; + // EMUDAT = Mreg; is valid + .dw 0x3EBC ; + .dw 0x3EBD ; + .dw 0x3EBE ; + .dw 0x3EBF ; + // EMUDAT = Breg; is valid + .dw 0x3EF8 ; + .dw 0x3EF9 ; + .dw 0x3EFA ; + .dw 0x3EFB ; + // EMUDAT = Lreg; is valid + .dw 0x3EFC ; + .dw 0x3EFD ; + .dw 0x3EFE ; + .dw 0x3EFF ; + // EMUDAT = Areg; is valid + .dw 0x3F38 ; + .dw 0x3F39 ; + .dw 0x3F3A ; + .dw 0x3F3B ; +#endif + .dw 0x3F3C ; + .dw 0x3F3D ; +#if 0 + // EMUDAT = ASTAT; is valid + .dw 0x3F3E ; + // EMUDAT = RETS; is valid + .dw 0x3F3F ; + // EMUDAT = loopregs; is valid + .dw 0x3FB8 ; + .dw 0x3FB9 ; + .dw 0x3FBA ; + .dw 0x3FBB ; + .dw 0x3FBC ; + .dw 0x3FBD ; + // EMUDAT = cycles; is valid + .dw 0x3FBE ; + .dw 0x3FBF ; + // EMUDAT = USP; is valid + .dw 0x3FF8 ; + // EMUDAT = SEQSTAT; is valid + .dw 0x3FF9 ; + // EMUDAT = SYSCFG; is valid + .dw 0x3FFA ; + // EMDUAT = RET[IXNE]; is valid + .dw 0x3FFB ; + .dw 0x3FFC ; + .dw 0x3FFD ; + .dw 0x3FFE ; + // EMUDAT = EMUDAT; is valid + .dw 0x3FFF ; + // Dreg = EMUDAT; is valid + .dw 0x31C7 ; + .dw 0x31CF ; + .dw 0x31D7 ; + .dw 0x31DF ; +#if 0 + // R4 = EMUDAT; breaks the test + .dw 0x31E7 ; + // R5 = EMUDAT; breaks the test + .dw 0x31EF ; +#endif + .dw 0x31F7 ; + .dw 0x31FF ; + // Preg = EMUDAT; is valid + .dw 0x33C7 ; + .dw 0x33CF ; + .dw 0x33D7 ; + .dw 0x33DF ; + .dw 0x33E7 ; + .dw 0x33EF ; + .dw 0x33F7 ; + .dw 0x33FF ; + // Ireg = EMUDAT; is valid + .dw 0x35C7 ; + .dw 0x35CF ; + .dw 0x35D7 ; + .dw 0x35DF ; + // Mreg = EMUDAT; is valid + .dw 0x35E7 ; + .dw 0x35EF ; + .dw 0x35F7 ; + .dw 0x35FF ; + // EMUDAT = Breg; is valid + .dw 0x37C7 ; + .dw 0x37CF ; + .dw 0x37D7 ; + .dw 0x37DF ; + // EMUDAT = Lreg; is valid + .dw 0x37E7 ; + .dw 0x37EF ; + .dw 0x37F7 ; + .dw 0x37FF ; +#endif + .dw 0x39C7 ; + .dw 0x39CF ; + .dw 0x39D7 ; + .dw 0x39DF ; + .dw 0x39E7 ; + .dw 0x39EF ; +#if 0 + // ASTAT = EMUDAT; is valid + .dw 0x39F7 ; + // RETS = EMUDAT; is valid + .dw 0x39FF ; + // loopregs = EMUDAT; is valid + .dw 0x3DC7 ; + .dw 0x3DCF ; + .dw 0x3DD7 ; + .dw 0x3DDF ; + .dw 0x3DE7 ; + .dw 0x3DEF ; + // cycles = EMUDAT; is valid + .dw 0x3DF7 ; + .dw 0x3DFF ; + // USP = EMUDAT; is valid + .dw 0x3FC7 ; + // SEQSTAT = EMUDAT; is valid + .dw 0x3FCF ; + // SYSCFG = EMUDAT; is valid + .dw 0x3FD7 ; + // RET[IXNE] = EMUDAT; is valid + .dw 0x3FDF ; + .dw 0x3FE7 ; + .dw 0x3FEF ; + .dw 0x3FF7 ; + // EMUDAT = EMUDAT; is valid + .dw 0x3FFF ; +#endif + .dw 0x3D80 ; + .dw 0x3D81 ; + .dw 0x3D82 ; + .dw 0x3D83 ; + .dw 0x3D84 ; + .dw 0x3D85 ; + .dw 0x3D86 ; + .dw 0x3D87 ; + .dw 0x3D88 ; + .dw 0x3D89 ; + .dw 0x3D8A ; + .dw 0x3D8B ; + .dw 0x3D8C ; + .dw 0x3D8D ; + .dw 0x3D8E ; + .dw 0x3D8F ; + .dw 0x3D90 ; + .dw 0x3D91 ; + .dw 0x3D92 ; + .dw 0x3D93 ; + .dw 0x3D94 ; + .dw 0x3D95 ; + .dw 0x3D96 ; + .dw 0x3D97 ; + .dw 0x3D98 ; + .dw 0x3D99 ; + .dw 0x3D9A ; + .dw 0x3D9B ; + .dw 0x3D9C ; + .dw 0x3D9D ; + .dw 0x3D9E ; + .dw 0x3D9F ; + .dw 0x3DA0 ; + .dw 0x3DA1 ; + .dw 0x3DA2 ; + .dw 0x3DA3 ; + .dw 0x3DA4 ; + .dw 0x3DA5 ; + .dw 0x3DA6 ; + .dw 0x3DA7 ; + .dw 0x3DA8 ; + .dw 0x3DA9 ; + .dw 0x3DAA ; + .dw 0x3DAB ; + .dw 0x3DAC ; + .dw 0x3DAD ; + .dw 0x3DAE ; + .dw 0x3DAF ; + .dw 0x3DB0 ; + .dw 0x3DB1 ; + .dw 0x3DB2 ; + .dw 0x3DB3 ; + .dw 0x3DB4 ; + .dw 0x3DB5 ; + .dw 0x3DB6 ; + .dw 0x3DB7 ; + .dw 0x3DB8 ; + .dw 0x3DB9 ; + .dw 0x3DBA ; + .dw 0x3DBB ; + .dw 0x3DBC ; + .dw 0x3DBD ; + .dw 0x3DBE ; + .dw 0x3DBF ; + .dw 0x3DC1 ; + .dw 0x3DC2 ; + .dw 0x3DC3 ; + .dw 0x3DC4 ; + .dw 0x3DC5 ; + .dw 0x3DC6 ; +#if 0 + // loopregs = EMUDAT; is valid + .dw 0x3DC7 ; +#endif + .dw 0x3DC9 ; + .dw 0x3DCA ; + .dw 0x3DCB ; + .dw 0x3DCC ; + .dw 0x3DCD ; + .dw 0x3DCE ; +#if 0 + // loopregs = EMUDAT; is valid + .dw 0x3DCF ; +#endif + .dw 0x3DD1 ; + .dw 0x3DD2 ; + .dw 0x3DD3 ; + .dw 0x3DD4 ; + .dw 0x3DD5 ; + .dw 0x3DD6 ; +#if 0 + // loopregs = EMUDAT; is valid + .dw 0x3DD7 ; +#endif + .dw 0x3DD9 ; + .dw 0x3DDA ; + .dw 0x3DDB ; + .dw 0x3DDC ; + .dw 0x3DDD ; + .dw 0x3DDE ; +#if 0 + // loopregs = EMUDAT; is valid + .dw 0x3DDF ; +#endif + .dw 0x3DE1 ; + .dw 0x3DE2 ; + .dw 0x3DE3 ; + .dw 0x3DE4 ; + .dw 0x3DE5 ; + .dw 0x3DE6 ; +#if 0 + // loopregs = EMUDAT; is valid + .dw 0x3DE7 ; +#endif + .dw 0x3DE9 ; + .dw 0x3DEA ; + .dw 0x3DEB ; + .dw 0x3DEC ; + .dw 0x3DED ; + .dw 0x3DEE ; +#if 0 + // loopregs = EMUDAT; is valid + .dw 0x3DEF ; +#endif + .dw 0x3DF1 ; + .dw 0x3DF2 ; + .dw 0x3DF3 ; + .dw 0x3DF4 ; + .dw 0x3DF5 ; + .dw 0x3DF6 ; +#if 0 + // cycles = EMUDAT; is valid + .dw 0x3DF7 ; +#endif + .dw 0x3DF9 ; + .dw 0x3DFA ; + .dw 0x3DFB ; + .dw 0x3DFC ; + .dw 0x3DFD ; + .dw 0x3DFE ; +#if 0 + // cycles = EMUDAT; is valid + .dw 0x3DFF ; +#endif + .dw 0x3F88 ; + .dw 0x3F89 ; + .dw 0x3F8A ; + .dw 0x3F8B ; + .dw 0x3F8C ; + .dw 0x3F8D ; + .dw 0x3F8E ; + .dw 0x3F8F ; + .dw 0x3F90 ; + .dw 0x3F91 ; + .dw 0x3F92 ; + .dw 0x3F93 ; + .dw 0x3F94 ; + .dw 0x3F95 ; + .dw 0x3F96 ; + .dw 0x3F97 ; + .dw 0x3F98 ; + .dw 0x3F99 ; + .dw 0x3F9A ; + .dw 0x3F9B ; + .dw 0x3F9C ; + .dw 0x3F9D ; + .dw 0x3F9E ; + .dw 0x3F9F ; + .dw 0x3FA0 ; + .dw 0x3FA1 ; + .dw 0x3FA2 ; + .dw 0x3FA3 ; + .dw 0x3FA4 ; + .dw 0x3FA5 ; + .dw 0x3FA6 ; + .dw 0x3FA7 ; + .dw 0x3FA8 ; + .dw 0x3FA9 ; + .dw 0x3FAA ; + .dw 0x3FAB ; + .dw 0x3FAC ; + .dw 0x3FAD ; + .dw 0x3FAE ; + .dw 0x3FAF ; + .dw 0x3FB0 ; + .dw 0x3FB1 ; + .dw 0x3FB2 ; + .dw 0x3FB3 ; + .dw 0x3FB4 ; + .dw 0x3FB5 ; + .dw 0x3FB6 ; + .dw 0x3FB7 ; +#if 0 + // EMUDAT = loopregs; is valid + .dw 0x3FB8 ; + .dw 0x3FB9 ; + .dw 0x3FBA ; + .dw 0x3FBB ; + .dw 0x3FBC ; + .dw 0x3FBD ; + // EMUDAT = cycles; is valid + .dw 0x3FBE ; + .dw 0x3FBF ; +#endif + .dw 0x3FC9 ; + .dw 0x3FCA ; + .dw 0x3FCB ; + .dw 0x3FCC ; + .dw 0x3FCD ; + .dw 0x3FCE ; +#if 0 + // SEQSTAT = EMUDAT; is valid + .dw 0x3FCF ; +#endif + .dw 0x3FD1 ; + .dw 0x3FD2 ; + .dw 0x3FD3 ; + .dw 0x3FD4 ; + .dw 0x3FD5 ; + .dw 0x3FD6 ; +#if 0 + // SYSCFG = EMUDAT; is valid + .dw 0x3FD7 ; +#endif + .dw 0x3FD9 ; + .dw 0x3FDA ; + .dw 0x3FDB ; + .dw 0x3FDC ; + .dw 0x3FDD ; + .dw 0x3FDE ; +#if 0 + // RET[IXNE] = EMUDAT; is valid + .dw 0x3FDF ; +#endif + .dw 0x3FE1 ; + .dw 0x3FE2 ; + .dw 0x3FE3 ; + .dw 0x3FE4 ; + .dw 0x3FE5 ; + .dw 0x3FE6 ; +#if 0 + // RET[IXNE] = EMUDAT; is valid + .dw 0x3FE7 ; +#endif + .dw 0x3FE9 ; + .dw 0x3FEA ; + .dw 0x3FEB ; + .dw 0x3FEC ; + .dw 0x3FED ; + .dw 0x3FEE ; +#if 0 + // RET[IXNE] = EMUDAT; is valid + .dw 0x3FEF ; +#endif + .dw 0x3FF1 ; + .dw 0x3FF2 ; + .dw 0x3FF3 ; + .dw 0x3FF4 ; + .dw 0x3FF5 ; + .dw 0x3FF6 ; +#if 0 + // RET[IXNE] = EMUDAT; is valid + .dw 0x3FF7 ; + // EMUDAT = SEQSTAT; is valid + .dw 0x3FF9 ; + // EMUDAT = SYSCFG; is valid + .dw 0x3FFA ; + // EMDUAT = RET[IXNE]; is valid + .dw 0x3FFB ; + .dw 0x3FFC ; + .dw 0x3FFD ; + .dw 0x3FFE ; + // EMUDAT = EMUDAT; is valid + .dw 0x3FFF ; +#endif + .dw 0x39B0 ; + .dw 0x39B1 ; + .dw 0x39B2 ; + .dw 0x39B3 ; + .dw 0x39B4 ; + .dw 0x39B5 ; + .dw 0x39B6 ; + .dw 0x39B7 ; + .dw 0x39B8 ; + .dw 0x39B9 ; + .dw 0x39BA ; + .dw 0x39BB ; + .dw 0x39BC ; + .dw 0x39BD ; + .dw 0x39BE ; + .dw 0x39BF ; + .dw 0x39F1 ; + .dw 0x39F2 ; + .dw 0x39F3 ; + .dw 0x39F4 ; + .dw 0x39F5 ; + .dw 0x39F6 ; +#if 0 + // ASTAT = EMUDAT; is valid + .dw 0x39F7 ; +#endif + .dw 0x39F9 ; + .dw 0x39FA ; + .dw 0x39FB ; + .dw 0x39FC ; + .dw 0x39FD ; + .dw 0x39FE ; +#if 0 + // RETS = EMUDAT; is valid + .dw 0x39FF ; +#endif + .dw 0x3D06 ; + .dw 0x3D07 ; + .dw 0x3D0E ; + .dw 0x3D0F ; + .dw 0x3D16 ; + .dw 0x3D17 ; + .dw 0x3D1E ; + .dw 0x3D1F ; + .dw 0x3D26 ; + .dw 0x3D27 ; + .dw 0x3D2E ; + .dw 0x3D2F ; + .dw 0x3D36 ; + .dw 0x3D37 ; + .dw 0x3D3E ; + .dw 0x3D3F ; + .dw 0x3F0E ; + .dw 0x3F0F ; + .dw 0x3F16 ; + .dw 0x3F17 ; + .dw 0x3F1E ; + .dw 0x3F1F ; + .dw 0x3F26 ; + .dw 0x3F27 ; + .dw 0x3F2E ; + .dw 0x3F2F ; + .dw 0x3F36 ; + .dw 0x3F37 ; +#if 0 + // EMUDAT = ASTAT; is valid + .dw 0x3F3E ; + // EMUDAT = RETS; is valid + .dw 0x3F3F ; +#endif + .dw 0x3936 ; + .dw 0x3937 ; + .dw 0x393E ; + .dw 0x393F ; + .dw 0x3C80 ; + .dw 0x3C81 ; + .dw 0x3C82 ; + .dw 0x3C83 ; + .dw 0x3C84 ; + .dw 0x3C85 ; + .dw 0x3C86 ; + .dw 0x3C87 ; + .dw 0x3C88 ; + .dw 0x3C89 ; + .dw 0x3C8A ; + .dw 0x3C8B ; + .dw 0x3C8C ; + .dw 0x3C8D ; + .dw 0x3C8E ; + .dw 0x3C8F ; + .dw 0x3C90 ; + .dw 0x3C91 ; + .dw 0x3C92 ; + .dw 0x3C93 ; + .dw 0x3C94 ; + .dw 0x3C95 ; + .dw 0x3C96 ; + .dw 0x3C97 ; + .dw 0x3C98 ; + .dw 0x3C99 ; + .dw 0x3C9A ; + .dw 0x3C9B ; + .dw 0x3C9C ; + .dw 0x3C9D ; + .dw 0x3C9E ; + .dw 0x3C9F ; + .dw 0x3CA0 ; + .dw 0x3CA1 ; + .dw 0x3CA2 ; + .dw 0x3CA3 ; + .dw 0x3CA4 ; + .dw 0x3CA5 ; + .dw 0x3CA6 ; + .dw 0x3CA7 ; + .dw 0x3CA8 ; + .dw 0x3CA9 ; + .dw 0x3CAA ; + .dw 0x3CAB ; + .dw 0x3CAC ; + .dw 0x3CAD ; + .dw 0x3CAE ; + .dw 0x3CAF ; + .dw 0x3CB0 ; + .dw 0x3CB1 ; + .dw 0x3CB2 ; + .dw 0x3CB3 ; + .dw 0x3CB4 ; + .dw 0x3CB5 ; + .dw 0x3CB6 ; + .dw 0x3CB7 ; + .dw 0x3CB8 ; + .dw 0x3CB9 ; + .dw 0x3CBA ; + .dw 0x3CBB ; + .dw 0x3CBC ; + .dw 0x3CBD ; + .dw 0x3CBE ; + .dw 0x3CBF ; + .dw 0x3CC0 ; + .dw 0x3CC1 ; + .dw 0x3CC2 ; + .dw 0x3CC3 ; + .dw 0x3CC4 ; + .dw 0x3CC5 ; + .dw 0x3CC6 ; + .dw 0x3CC7 ; + .dw 0x3CC8 ; + .dw 0x3CC9 ; + .dw 0x3CCA ; + .dw 0x3CCB ; + .dw 0x3CCC ; + .dw 0x3CCD ; + .dw 0x3CCE ; + .dw 0x3CCF ; + .dw 0x3CD0 ; + .dw 0x3CD1 ; + .dw 0x3CD2 ; + .dw 0x3CD3 ; + .dw 0x3CD4 ; + .dw 0x3CD5 ; + .dw 0x3CD6 ; + .dw 0x3CD7 ; + .dw 0x3CD8 ; + .dw 0x3CD9 ; + .dw 0x3CDA ; + .dw 0x3CDB ; + .dw 0x3CDC ; + .dw 0x3CDD ; + .dw 0x3CDE ; + .dw 0x3CDF ; + .dw 0x3CE0 ; + .dw 0x3CE1 ; + .dw 0x3CE2 ; + .dw 0x3CE3 ; + .dw 0x3CE4 ; + .dw 0x3CE5 ; + .dw 0x3CE6 ; + .dw 0x3CE7 ; + .dw 0x3CE8 ; + .dw 0x3CE9 ; + .dw 0x3CEA ; + .dw 0x3CEB ; + .dw 0x3CEC ; + .dw 0x3CED ; + .dw 0x3CEE ; + .dw 0x3CEF ; + .dw 0x3CF0 ; + .dw 0x3CF1 ; + .dw 0x3CF2 ; + .dw 0x3CF3 ; + .dw 0x3CF4 ; + .dw 0x3CF5 ; + .dw 0x3CF6 ; + .dw 0x3CF7 ; + .dw 0x3CF8 ; + .dw 0x3CF9 ; + .dw 0x3CFA ; + .dw 0x3CFB ; + .dw 0x3CFC ; + .dw 0x3CFD ; + .dw 0x3CFE ; + .dw 0x3CFF ; + .dw 0x3E88 ; + .dw 0x3E89 ; + .dw 0x3E8A ; + .dw 0x3E8B ; + .dw 0x3E8C ; + .dw 0x3E8D ; + .dw 0x3E8E ; + .dw 0x3E8F ; + .dw 0x3E90 ; + .dw 0x3E91 ; + .dw 0x3E92 ; + .dw 0x3E93 ; + .dw 0x3E94 ; + .dw 0x3E95 ; + .dw 0x3E96 ; + .dw 0x3E97 ; + .dw 0x3E98 ; + .dw 0x3E99 ; + .dw 0x3E9A ; + .dw 0x3E9B ; + .dw 0x3E9C ; + .dw 0x3E9D ; + .dw 0x3E9E ; + .dw 0x3E9F ; + .dw 0x3EA0 ; + .dw 0x3EA1 ; + .dw 0x3EA2 ; + .dw 0x3EA3 ; + .dw 0x3EA4 ; + .dw 0x3EA5 ; + .dw 0x3EA6 ; + .dw 0x3EA7 ; + .dw 0x3EA8 ; + .dw 0x3EA9 ; + .dw 0x3EAA ; + .dw 0x3EAB ; + .dw 0x3EAC ; + .dw 0x3EAD ; + .dw 0x3EAE ; + .dw 0x3EAF ; + .dw 0x3EB0 ; + .dw 0x3EB1 ; + .dw 0x3EB2 ; + .dw 0x3EB3 ; + .dw 0x3EB4 ; + .dw 0x3EB5 ; + .dw 0x3EB6 ; + .dw 0x3EB7 ; +#if 0 + // EMUDAT = Ireg; is valid + .dw 0x3EB8 ; + .dw 0x3EB9 ; + .dw 0x3EBA ; + .dw 0x3EBB ; + // EMUDAT = Mreg; is valid + .dw 0x3EBC ; + .dw 0x3EBD ; + .dw 0x3EBE ; + .dw 0x3EBF ; +#endif + .dw 0x3EC8 ; + .dw 0x3EC9 ; + .dw 0x3ECA ; + .dw 0x3ECB ; + .dw 0x3ECC ; + .dw 0x3ECD ; + .dw 0x3ECE ; + .dw 0x3ECF ; + .dw 0x3ED0 ; + .dw 0x3ED1 ; + .dw 0x3ED2 ; + .dw 0x3ED3 ; + .dw 0x3ED4 ; + .dw 0x3ED5 ; + .dw 0x3ED6 ; + .dw 0x3ED7 ; + .dw 0x3ED8 ; + .dw 0x3ED9 ; + .dw 0x3EDA ; + .dw 0x3EDB ; + .dw 0x3EDC ; + .dw 0x3EDD ; + .dw 0x3EDE ; + .dw 0x3EDF ; + .dw 0x3EE0 ; + .dw 0x3EE1 ; + .dw 0x3EE2 ; + .dw 0x3EE3 ; + .dw 0x3EE4 ; + .dw 0x3EE5 ; + .dw 0x3EE6 ; + .dw 0x3EE7 ; + .dw 0x3EE8 ; + .dw 0x3EE9 ; + .dw 0x3EEA ; + .dw 0x3EEB ; + .dw 0x3EEC ; + .dw 0x3EED ; + .dw 0x3EEE ; + .dw 0x3EEF ; + .dw 0x3EF0 ; + .dw 0x3EF1 ; + .dw 0x3EF2 ; + .dw 0x3EF3 ; + .dw 0x3EF4 ; + .dw 0x3EF5 ; + .dw 0x3EF6 ; + .dw 0x3EF7 ; +#if 0 + // EMUDAT = Breg; is valid + .dw 0x3EF8 ; + .dw 0x3EF9 ; + .dw 0x3EFA ; + .dw 0x3EFB ; + // EMUDAT = Lreg; is valid + .dw 0x3EFC ; + .dw 0x3EFD ; + .dw 0x3EFE ; + .dw 0x3EFF ; +#endif + .dw 0x38B0 ; + .dw 0x38B1 ; + .dw 0x38B2 ; + .dw 0x38B3 ; + .dw 0x38B4 ; + .dw 0x38B5 ; + .dw 0x38B6 ; + .dw 0x38B7 ; + .dw 0x38B8 ; + .dw 0x38B9 ; + .dw 0x38BA ; + .dw 0x38BB ; + .dw 0x38BC ; + .dw 0x38BD ; + .dw 0x38BE ; + .dw 0x38BF ; + .dw 0x38F0 ; + .dw 0x38F1 ; + .dw 0x38F2 ; + .dw 0x38F3 ; + .dw 0x38F4 ; + .dw 0x38F5 ; + .dw 0x38F6 ; + .dw 0x38F7 ; + .dw 0x38F8 ; + .dw 0x38F9 ; + .dw 0x38FA ; + .dw 0x38FB ; + .dw 0x38FC ; + .dw 0x38FD ; + .dw 0x38FE ; + .dw 0x38FF ; +#if 0 + // Preg = sysreg; is valid + .dw 0x3380 ; + .dw 0x3381 ; + .dw 0x3382 ; + .dw 0x3383 ; + .dw 0x3384 ; + .dw 0x3385 ; + .dw 0x3386 ; + .dw 0x3387 ; + .dw 0x3388 ; + .dw 0x3389 ; + .dw 0x338A ; + .dw 0x338B ; + .dw 0x338C ; + .dw 0x338D ; + .dw 0x338E ; + .dw 0x338F ; + .dw 0x3390 ; + .dw 0x3391 ; + .dw 0x3392 ; + .dw 0x3393 ; + .dw 0x3394 ; + .dw 0x3395 ; + .dw 0x3396 ; + .dw 0x3397 ; + .dw 0x3398 ; + .dw 0x3399 ; + .dw 0x339A ; + .dw 0x339B ; + .dw 0x339C ; + .dw 0x339D ; + .dw 0x339E ; + .dw 0x339F ; + .dw 0x33A0 ; + .dw 0x33A1 ; + .dw 0x33A2 ; + .dw 0x33A3 ; + .dw 0x33A4 ; + .dw 0x33A5 ; + .dw 0x33A6 ; + .dw 0x33A7 ; + .dw 0x33A8 ; + .dw 0x33A9 ; + .dw 0x33AA ; + .dw 0x33AB ; + .dw 0x33AC ; + .dw 0x33AD ; + .dw 0x33AE ; + .dw 0x33AF ; + .dw 0x33B0 ; + .dw 0x33B1 ; + .dw 0x33B2 ; + .dw 0x33B3 ; + .dw 0x33B4 ; + .dw 0x33B5 ; + .dw 0x33B6 ; + .dw 0x33B7 ; + .dw 0x33B8 ; + .dw 0x33B9 ; + .dw 0x33BA ; + .dw 0x33BB ; + .dw 0x33BC ; + .dw 0x33BD ; + .dw 0x33BE ; + .dw 0x33BF ; + .dw 0x33C1 ; + .dw 0x33C2 ; + .dw 0x33C3 ; + .dw 0x33C4 ; + .dw 0x33C5 ; + .dw 0x33C6 ; + .dw 0x33C7 ; + .dw 0x33C9 ; + .dw 0x33CA ; + .dw 0x33CB ; + .dw 0x33CC ; + .dw 0x33CD ; + .dw 0x33CE ; + .dw 0x33CF ; + .dw 0x33D1 ; + .dw 0x33D2 ; + .dw 0x33D3 ; + .dw 0x33D4 ; + .dw 0x33D5 ; + .dw 0x33D6 ; + .dw 0x33D7 ; + .dw 0x33D9 ; + .dw 0x33DA ; + .dw 0x33DB ; + .dw 0x33DC ; + .dw 0x33DD ; + .dw 0x33DE ; + .dw 0x33DF ; + .dw 0x33E1 ; + .dw 0x33E2 ; + .dw 0x33E3 ; + .dw 0x33E4 ; + .dw 0x33E5 ; + .dw 0x33E6 ; + .dw 0x33E7 ; + .dw 0x33E9 ; + .dw 0x33EA ; + .dw 0x33EB ; + .dw 0x33EC ; + .dw 0x33ED ; + .dw 0x33EE ; + .dw 0x33EF ; + .dw 0x33F1 ; + .dw 0x33F2 ; + .dw 0x33F3 ; + .dw 0x33F4 ; + .dw 0x33F5 ; + .dw 0x33F6 ; + .dw 0x33F7 ; + .dw 0x33F9 ; + .dw 0x33FA ; + .dw 0x33FB ; + .dw 0x33FC ; + .dw 0x33FD ; + .dw 0x33FE ; + .dw 0x33FF ; + .dw 0x3306 ; + .dw 0x3307 ; + .dw 0x330E ; + .dw 0x330F ; + .dw 0x3316 ; + .dw 0x3317 ; + .dw 0x331E ; + .dw 0x331F ; + .dw 0x3326 ; + .dw 0x3327 ; + .dw 0x332E ; + .dw 0x332F ; + .dw 0x3336 ; + .dw 0x3337 ; + .dw 0x333E ; + .dw 0x333F ; +#endif + .dw 0x3580 ; + .dw 0x3581 ; + .dw 0x3582 ; + .dw 0x3583 ; + .dw 0x3584 ; + .dw 0x3585 ; + .dw 0x3586 ; + .dw 0x3587 ; + .dw 0x3588 ; + .dw 0x3589 ; + .dw 0x358A ; + .dw 0x358B ; + .dw 0x358C ; + .dw 0x358D ; + .dw 0x358E ; + .dw 0x358F ; + .dw 0x3590 ; + .dw 0x3591 ; + .dw 0x3592 ; + .dw 0x3593 ; + .dw 0x3594 ; + .dw 0x3595 ; + .dw 0x3596 ; + .dw 0x3597 ; + .dw 0x3598 ; + .dw 0x3599 ; + .dw 0x359A ; + .dw 0x359B ; + .dw 0x359C ; + .dw 0x359D ; + .dw 0x359E ; + .dw 0x359F ; + .dw 0x35A0 ; + .dw 0x35A1 ; + .dw 0x35A2 ; + .dw 0x35A3 ; + .dw 0x35A4 ; + .dw 0x35A5 ; + .dw 0x35A6 ; + .dw 0x35A7 ; + .dw 0x35A8 ; + .dw 0x35A9 ; + .dw 0x35AA ; + .dw 0x35AB ; + .dw 0x35AC ; + .dw 0x35AD ; + .dw 0x35AE ; + .dw 0x35AF ; + .dw 0x35B0 ; + .dw 0x35B1 ; + .dw 0x35B2 ; + .dw 0x35B3 ; + .dw 0x35B4 ; + .dw 0x35B5 ; + .dw 0x35B6 ; + .dw 0x35B7 ; + .dw 0x35B8 ; + .dw 0x35B9 ; + .dw 0x35BA ; + .dw 0x35BB ; + .dw 0x35BC ; + .dw 0x35BD ; + .dw 0x35BE ; + .dw 0x35BF ; + .dw 0x35C1 ; + .dw 0x35C2 ; + .dw 0x35C3 ; + .dw 0x35C4 ; + .dw 0x35C5 ; + .dw 0x35C6 ; +#if 0 + // Ireg = EMUDAT; is valid + .dw 0x35C7 ; +#endif + .dw 0x35C9 ; + .dw 0x35CA ; + .dw 0x35CB ; + .dw 0x35CC ; + .dw 0x35CD ; + .dw 0x35CE ; +#if 0 + // Ireg = EMUDAT; is valid + .dw 0x35CF ; +#endif + .dw 0x35D1 ; + .dw 0x35D2 ; + .dw 0x35D3 ; + .dw 0x35D4 ; + .dw 0x35D5 ; + .dw 0x35D6 ; +#if 0 + // Ireg = EMUDAT; is valid + .dw 0x35D7 ; +#endif + .dw 0x35D9 ; + .dw 0x35DA ; + .dw 0x35DB ; + .dw 0x35DC ; + .dw 0x35DD ; + .dw 0x35DE ; +#if 0 + // Ireg = EMUDAT; is valid + .dw 0x35DF ; +#endif + .dw 0x35E1 ; + .dw 0x35E2 ; + .dw 0x35E3 ; + .dw 0x35E4 ; + .dw 0x35E5 ; + .dw 0x35E6 ; +#if 0 + // Mreg = EMUDAT; is valid + .dw 0x35E7 ; +#endif + .dw 0x35E9 ; + .dw 0x35EA ; + .dw 0x35EB ; + .dw 0x35EC ; + .dw 0x35ED ; + .dw 0x35EE ; +#if 0 + // Mreg = EMUDAT; is valid + .dw 0x35EF ; +#endif + .dw 0x35F1 ; + .dw 0x35F2 ; + .dw 0x35F3 ; + .dw 0x35F4 ; + .dw 0x35F5 ; + .dw 0x35F6 ; +#if 0 + // Mreg = EMUDAT; is valid + .dw 0x35F7 ; +#endif + .dw 0x35F9 ; + .dw 0x35FA ; + .dw 0x35FB ; + .dw 0x35FC ; + .dw 0x35FD ; + .dw 0x35FE ; +#if 0 + // Mreg = EMUDAT; is valid + .dw 0x35FF ; +#endif + .dw 0x3780 ; + .dw 0x3781 ; + .dw 0x3782 ; + .dw 0x3783 ; + .dw 0x3784 ; + .dw 0x3785 ; + .dw 0x3786 ; + .dw 0x3787 ; + .dw 0x3788 ; + .dw 0x3789 ; + .dw 0x378A ; + .dw 0x378B ; + .dw 0x378C ; + .dw 0x378D ; + .dw 0x378E ; + .dw 0x378F ; + .dw 0x3790 ; + .dw 0x3791 ; + .dw 0x3792 ; + .dw 0x3793 ; + .dw 0x3794 ; + .dw 0x3795 ; + .dw 0x3796 ; + .dw 0x3797 ; + .dw 0x3798 ; + .dw 0x3799 ; + .dw 0x379A ; + .dw 0x379B ; + .dw 0x379C ; + .dw 0x379D ; + .dw 0x379E ; + .dw 0x379F ; + .dw 0x37A0 ; + .dw 0x37A1 ; + .dw 0x37A2 ; + .dw 0x37A3 ; + .dw 0x37A4 ; + .dw 0x37A5 ; + .dw 0x37A6 ; + .dw 0x37A7 ; + .dw 0x37A8 ; + .dw 0x37A9 ; + .dw 0x37AA ; + .dw 0x37AB ; + .dw 0x37AC ; + .dw 0x37AD ; + .dw 0x37AE ; + .dw 0x37AF ; + .dw 0x37B0 ; + .dw 0x37B1 ; + .dw 0x37B2 ; + .dw 0x37B3 ; + .dw 0x37B4 ; + .dw 0x37B5 ; + .dw 0x37B6 ; + .dw 0x37B7 ; + .dw 0x37B8 ; + .dw 0x37B9 ; + .dw 0x37BA ; + .dw 0x37BB ; + .dw 0x37BC ; + .dw 0x37BD ; + .dw 0x37BE ; + .dw 0x37BF ; + .dw 0x37C1 ; + .dw 0x37C2 ; + .dw 0x37C3 ; + .dw 0x37C4 ; + .dw 0x37C5 ; + .dw 0x37C6 ; +#if 0 + // EMUDAT = Breg; is valid + .dw 0x37C7 ; +#endif + .dw 0x37C9 ; + .dw 0x37CA ; + .dw 0x37CB ; + .dw 0x37CC ; + .dw 0x37CD ; + .dw 0x37CE ; +#if 0 + // EMUDAT = Breg; is valid + .dw 0x37CF ; +#endif + .dw 0x37D1 ; + .dw 0x37D2 ; + .dw 0x37D3 ; + .dw 0x37D4 ; + .dw 0x37D5 ; + .dw 0x37D6 ; +#if 0 + // EMUDAT = Breg; is valid + .dw 0x37D7 ; +#endif + .dw 0x37D9 ; + .dw 0x37DA ; + .dw 0x37DB ; + .dw 0x37DC ; + .dw 0x37DD ; + .dw 0x37DE ; +#if 0 + // EMUDAT = Breg; is valid + .dw 0x37DF ; +#endif + .dw 0x37E1 ; + .dw 0x37E2 ; + .dw 0x37E3 ; + .dw 0x37E4 ; + .dw 0x37E5 ; + .dw 0x37E6 ; +#if 0 + // EMUDAT = Lreg; is valid + .dw 0x37E7 ; +#endif + .dw 0x37E9 ; + .dw 0x37EA ; + .dw 0x37EB ; + .dw 0x37EC ; + .dw 0x37ED ; + .dw 0x37EE ; +#if 0 + // EMUDAT = Lreg; is valid + .dw 0x37EF ; +#endif + .dw 0x37F1 ; + .dw 0x37F2 ; + .dw 0x37F3 ; + .dw 0x37F4 ; + .dw 0x37F5 ; + .dw 0x37F6 ; +#if 0 + // EMUDAT = Lreg; is valid + .dw 0x37F7 ; +#endif + .dw 0x37F9 ; + .dw 0x37FA ; + .dw 0x37FB ; + .dw 0x37FC ; + .dw 0x37FD ; + .dw 0x37FE ; +#if 0 + // EMUDAT = Lreg; is valid + .dw 0x37FF ; +#endif + .dw 0x3506 ; + .dw 0x3507 ; + .dw 0x350E ; + .dw 0x350F ; + .dw 0x3516 ; + .dw 0x3517 ; + .dw 0x351E ; + .dw 0x351F ; + .dw 0x3526 ; + .dw 0x3527 ; + .dw 0x352E ; + .dw 0x352F ; + .dw 0x3536 ; + .dw 0x3537 ; + .dw 0x353E ; + .dw 0x353F ; + .dw 0x3706 ; + .dw 0x3707 ; + .dw 0x370E ; + .dw 0x370F ; + .dw 0x3716 ; + .dw 0x3717 ; + .dw 0x371E ; + .dw 0x371F ; + .dw 0x3726 ; + .dw 0x3727 ; + .dw 0x372E ; + .dw 0x372F ; + .dw 0x3736 ; + .dw 0x3737 ; + .dw 0x373E ; + .dw 0x373F ; + .dw 0x4180 ; + .dw 0x4181 ; + .dw 0x4182 ; + .dw 0x4183 ; + .dw 0x4184 ; + .dw 0x4185 ; + .dw 0x4186 ; + .dw 0x4187 ; + .dw 0x4188 ; + .dw 0x4189 ; + .dw 0x418A ; + .dw 0x418B ; + .dw 0x418C ; + .dw 0x418D ; + .dw 0x418E ; + .dw 0x418F ; + .dw 0x4190 ; + .dw 0x4191 ; + .dw 0x4192 ; + .dw 0x4193 ; + .dw 0x4194 ; + .dw 0x4195 ; + .dw 0x4196 ; + .dw 0x4197 ; + .dw 0x4198 ; + .dw 0x4199 ; + .dw 0x419A ; + .dw 0x419B ; + .dw 0x419C ; + .dw 0x419D ; + .dw 0x419E ; + .dw 0x419F ; + .dw 0x41A0 ; + .dw 0x41A1 ; + .dw 0x41A2 ; + .dw 0x41A3 ; + .dw 0x41A4 ; + .dw 0x41A5 ; + .dw 0x41A6 ; + .dw 0x41A7 ; + .dw 0x41A8 ; + .dw 0x41A9 ; + .dw 0x41AA ; + .dw 0x41AB ; + .dw 0x41AC ; + .dw 0x41AD ; + .dw 0x41AE ; + .dw 0x41AF ; + .dw 0x41B0 ; + .dw 0x41B1 ; + .dw 0x41B2 ; + .dw 0x41B3 ; + .dw 0x41B4 ; + .dw 0x41B5 ; + .dw 0x41B6 ; + .dw 0x41B7 ; + .dw 0x41B8 ; + .dw 0x41B9 ; + .dw 0x41BA ; + .dw 0x41BB ; + .dw 0x41BC ; + .dw 0x41BD ; + .dw 0x41BE ; + .dw 0x41BF ; + .dw 0x41C0 ; + .dw 0x41C1 ; + .dw 0x41C2 ; + .dw 0x41C3 ; + .dw 0x41C4 ; + .dw 0x41C5 ; + .dw 0x41C6 ; + .dw 0x41C7 ; + .dw 0x41C8 ; + .dw 0x41C9 ; + .dw 0x41CA ; + .dw 0x41CB ; + .dw 0x41CC ; + .dw 0x41CD ; + .dw 0x41CE ; + .dw 0x41CF ; + .dw 0x41D0 ; + .dw 0x41D1 ; + .dw 0x41D2 ; + .dw 0x41D3 ; + .dw 0x41D4 ; + .dw 0x41D5 ; + .dw 0x41D6 ; + .dw 0x41D7 ; + .dw 0x41D8 ; + .dw 0x41D9 ; + .dw 0x41DA ; + .dw 0x41DB ; + .dw 0x41DC ; + .dw 0x41DD ; + .dw 0x41DE ; + .dw 0x41DF ; + .dw 0x41E0 ; + .dw 0x41E1 ; + .dw 0x41E2 ; + .dw 0x41E3 ; + .dw 0x41E4 ; + .dw 0x41E5 ; + .dw 0x41E6 ; + .dw 0x41E7 ; + .dw 0x41E8 ; + .dw 0x41E9 ; + .dw 0x41EA ; + .dw 0x41EB ; + .dw 0x41EC ; + .dw 0x41ED ; + .dw 0x41EE ; + .dw 0x41EF ; + .dw 0x41F0 ; + .dw 0x41F1 ; + .dw 0x41F2 ; + .dw 0x41F3 ; + .dw 0x41F4 ; + .dw 0x41F5 ; + .dw 0x41F6 ; + .dw 0x41F7 ; + .dw 0x41F8 ; + .dw 0x41F9 ; + .dw 0x41FA ; + .dw 0x41FB ; + .dw 0x41FC ; + .dw 0x41FD ; + .dw 0x41FE ; + .dw 0x41FF ; +.ifndef BFIN_HW + // XXX: These cause double fault on hardware when run in IVG15 !? + .dw 0x9040 ; + .dw 0x9049 ; + .dw 0x9052 ; + .dw 0x905B ; + .dw 0x9064 ; + .dw 0x906D ; + .dw 0x9076 ; + .dw 0x907F ; + .dw 0x90C0 ; + .dw 0x90C9 ; + .dw 0x90D2 ; + .dw 0x90DB ; + .dw 0x90E4 ; + .dw 0x90ED ; + .dw 0x90F6 ; + .dw 0x90FF ; +.endif + .dw 0x9180 ; +// Starting 32bit s section COUNT = 3481 + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +.ifndef BFIN_HW +CHECKREG(r5, 2651 - 507); // count of all 16 bit UI's. +.else +CHECKREG(r5, 2651 - 524); // count of all 16 bit UI's. +.endif + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 16 bit illegal opcode handler - skips bad instruction + + // handler MADE LEAN and destructive so test runs more quckly + // se_undefinedinstruction1.dsp tests using a "nice" handler + +// [--sp] = ASTAT; // save what we damage +// [--sp] = (r7 - r6); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + + R6 = 0x22; // Also accept illegal insn combo +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + +dbg_fail; + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + r4 += 2; + CC = r4 == r7; + if !CC jump fail; + + R7 += 2; // skip offending 16 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: +// (r7 - r6) = [sp++]; +// ASTAT = [sp++]; + +RTX; +fail: +dbg_fail; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_undefinedinstruction3.S b/sim/testsuite/bfin/se_undefinedinstruction3.S new file mode 100644 index 0000000..0acfb88 --- /dev/null +++ b/sim/testsuite/bfin/se_undefinedinstruction3.S @@ -0,0 +1,6022 @@ +//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction3/se_undefinedinstruction3.dsp +// Description: 32 bit special cases Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating +# xfail: "missing checks in A0/A1 macfunc" bfin-* + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + A0 = 0; // reset accumulators + A1 = 0; + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // count of UI's will be in r5, which was initialized to 0 by header + + .dw 0xE802 ; + .dw 0xB3FD ; + .dw 0xE803 ; + .dw 0xD461 ; + .dw 0xE804 ; + .dw 0x36A1 ; + .dw 0xE805 ; + .dw 0x7FED ; + .dw 0xE806 ; + .dw 0xFEB3 ; + .dw 0xE807 ; + .dw 0x8785 ; + .dw 0xE808 ; + .dw 0x2F21 ; + .dw 0xE809 ; + .dw 0x2889 ; + .dw 0xE80A ; + .dw 0x96B7 ; + .dw 0xE80B ; + .dw 0x8357 ; + .dw 0xE80C ; + .dw 0x5D07 ; + .dw 0xE80D ; + .dw 0x13D5 ; + .dw 0xE80E ; + .dw 0x1C11 ; + .dw 0xE80F ; + .dw 0x19D3 ; + .dw 0xE810 ; + .dw 0xBF4B ; + .dw 0xE811 ; + .dw 0xEF89 ; + .dw 0xE812 ; + .dw 0x2BD ; + .dw 0xE813 ; + .dw 0x6FC5 ; + .dw 0xE814 ; + .dw 0x89F1 ; + .dw 0xE815 ; + .dw 0x1D13 ; + .dw 0xE816 ; + .dw 0xA03F ; + .dw 0xE817 ; + .dw 0x9681 ; + .dw 0xE818 ; + .dw 0x2961 ; + .dw 0xE819 ; + .dw 0xEE23 ; + .dw 0xE81A ; + .dw 0x7ABB ; + .dw 0xE81B ; + .dw 0x8927 ; + .dw 0xE81C ; + .dw 0x2343 ; + .dw 0xE81D ; + .dw 0x308F ; + .dw 0xE81E ; + .dw 0x718F ; + .dw 0xE81F ; + .dw 0xC549 ; + .dw 0xE820 ; + .dw 0x2CD3 ; + .dw 0xE821 ; + .dw 0x81D9 ; + .dw 0xE822 ; + .dw 0xD76B ; + .dw 0xE823 ; + .dw 0xB735 ; + .dw 0xE824 ; + .dw 0x4EBB ; + .dw 0xE825 ; + .dw 0x6223 ; + .dw 0xE826 ; + .dw 0x15EB ; + .dw 0xE827 ; + .dw 0xB19F ; + .dw 0xE828 ; + .dw 0x6E6B ; + .dw 0xE829 ; + .dw 0x7EA3 ; + .dw 0xE82A ; + .dw 0xF2A7 ; + .dw 0xE82B ; + .dw 0xA8E1 ; + .dw 0xE82C ; + .dw 0x14ED ; + .dw 0xE82D ; + .dw 0x2BA5 ; + .dw 0xE82E ; + .dw 0xDD5 ; + .dw 0xE82F ; + .dw 0x69AD ; + .dw 0xE830 ; + .dw 0xCB47 ; + .dw 0xE831 ; + .dw 0x85F7 ; + .dw 0xE832 ; + .dw 0xB25D ; + .dw 0xE833 ; + .dw 0x8351 ; + .dw 0xE834 ; + .dw 0xE445 ; + .dw 0xE835 ; + .dw 0x33E5 ; + .dw 0xE836 ; + .dw 0x8F6B ; + .dw 0xE837 ; + .dw 0x9D5B ; + .dw 0xE838 ; + .dw 0xBE1 ; + .dw 0xE839 ; + .dw 0x3DB9 ; + .dw 0xE83A ; + .dw 0x7391 ; + .dw 0xE83B ; + .dw 0x70E5 ; + .dw 0xE83C ; + .dw 0x7409 ; + .dw 0xE83D ; + .dw 0xF5A9 ; + .dw 0xE83E ; + .dw 0xA15B ; + .dw 0xE83F ; + .dw 0x1D3F ; + .dw 0xE840 ; + .dw 0xF709 ; + .dw 0xE841 ; + .dw 0x6751 ; + .dw 0xE842 ; + .dw 0xD565 ; + .dw 0xE843 ; + .dw 0x1035 ; + .dw 0xE844 ; + .dw 0x755 ; + .dw 0xE845 ; + .dw 0x46AD ; + .dw 0xE846 ; + .dw 0x95F3 ; + .dw 0xE847 ; + .dw 0x39B3 ; + .dw 0xE848 ; + .dw 0xC4EB ; + .dw 0xE849 ; + .dw 0xD693 ; + .dw 0xE84A ; + .dw 0xE40F ; + .dw 0xE84B ; + .dw 0xC30F ; + .dw 0xE84C ; + .dw 0x101F ; + .dw 0xE84D ; + .dw 0xBEA7 ; + .dw 0xE84E ; + .dw 0xE617 ; + .dw 0xE84F ; + .dw 0x1BD ; + .dw 0xE850 ; + .dw 0xF203 ; + .dw 0xE851 ; + .dw 0x48D5 ; + .dw 0xE852 ; + .dw 0xA3DD ; + .dw 0xE853 ; + .dw 0xDD7F ; + .dw 0xE854 ; + .dw 0x3233 ; + .dw 0xE855 ; + .dw 0xFE45 ; + .dw 0xE856 ; + .dw 0x6C3D ; + .dw 0xE857 ; + .dw 0x6225 ; + .dw 0xE858 ; + .dw 0x722F ; + .dw 0xE859 ; + .dw 0x1BDD ; + .dw 0xE85A ; + .dw 0xFC35 ; + .dw 0xE85B ; + .dw 0xB4C1 ; + .dw 0xE85C ; + .dw 0xA635 ; + .dw 0xE85D ; + .dw 0xD62D ; + .dw 0xE85E ; + .dw 0xFF7D ; + .dw 0xE85F ; + .dw 0x2463 ; + .dw 0xE860 ; + .dw 0x439B ; + .dw 0xE861 ; + .dw 0xE4EF ; + .dw 0xE862 ; + .dw 0x299 ; + .dw 0xE863 ; + .dw 0x8E4F ; + .dw 0xE864 ; + .dw 0xFCA1 ; + .dw 0xE865 ; + .dw 0x4DFD ; + .dw 0xE866 ; + .dw 0x6E7D ; + .dw 0xE867 ; + .dw 0xCDAF ; + .dw 0xE868 ; + .dw 0x61D1 ; + .dw 0xE869 ; + .dw 0xE7C7 ; + .dw 0xE86A ; + .dw 0xA59D ; + .dw 0xE86B ; + .dw 0x6ED7 ; + .dw 0xE86C ; + .dw 0x40CF ; + .dw 0xE86D ; + .dw 0x8B4B ; + .dw 0xE86E ; + .dw 0xDA83 ; + .dw 0xE86F ; + .dw 0x5DF1 ; + .dw 0xE870 ; + .dw 0x18B5 ; + .dw 0xE871 ; + .dw 0x6D91 ; + .dw 0xE872 ; + .dw 0xB7EF ; + .dw 0xE873 ; + .dw 0xC941 ; + .dw 0xE874 ; + .dw 0x7BE9 ; + .dw 0xE875 ; + .dw 0x98A3 ; + .dw 0xE876 ; + .dw 0x7269 ; + .dw 0xE877 ; + .dw 0xEECF ; + .dw 0xE878 ; + .dw 0xB77B ; + .dw 0xE879 ; + .dw 0xFBFD ; + .dw 0xE87A ; + .dw 0x5B59 ; + .dw 0xE87B ; + .dw 0xDAD ; + .dw 0xE87C ; + .dw 0x97F5 ; + .dw 0xE87D ; + .dw 0xC8B ; + .dw 0xE87E ; + .dw 0x8DA1 ; + .dw 0xE87F ; + .dw 0x32A5 ; + .dw 0xE880 ; + .dw 0xA3B7 ; + .dw 0xE881 ; + .dw 0x6C27 ; + .dw 0xE882 ; + .dw 0xCBB7 ; + .dw 0xE883 ; + .dw 0x1873 ; + .dw 0xE884 ; + .dw 0xA2CF ; + .dw 0xE885 ; + .dw 0x9083 ; + .dw 0xE886 ; + .dw 0x2737 ; + .dw 0xE887 ; + .dw 0xD383 ; + .dw 0xE888 ; + .dw 0xCC51 ; + .dw 0xE889 ; + .dw 0xE1AD ; + .dw 0xE88A ; + .dw 0x8A01 ; + .dw 0xE88B ; + .dw 0x8123 ; + .dw 0xE88C ; + .dw 0x712D ; + .dw 0xE88D ; + .dw 0x47FF ; + .dw 0xE88E ; + .dw 0xB8CD ; + .dw 0xE88F ; + .dw 0xB23B ; + .dw 0xE890 ; + .dw 0x7C89 ; + .dw 0xE891 ; + .dw 0xA19F ; + .dw 0xE892 ; + .dw 0xE745 ; + .dw 0xE893 ; + .dw 0xC985 ; + .dw 0xE894 ; + .dw 0xA199 ; + .dw 0xE895 ; + .dw 0x176F ; + .dw 0xE896 ; + .dw 0x759D ; + .dw 0xE897 ; + .dw 0x54B ; + .dw 0xE898 ; + .dw 0x8EF7 ; + .dw 0xE899 ; + .dw 0xC987 ; + .dw 0xE89A ; + .dw 0xEFAB ; + .dw 0xE89B ; + .dw 0x6C97 ; + .dw 0xE89C ; + .dw 0xFF7B ; + .dw 0xE89D ; + .dw 0xCB35 ; + .dw 0xE89E ; + .dw 0xE57B ; + .dw 0xE89F ; + .dw 0x57F1 ; + .dw 0xE8A0 ; + .dw 0x8F ; + .dw 0xE8A1 ; + .dw 0xE667 ; + .dw 0xE8A2 ; + .dw 0xB56F ; + .dw 0xE8A3 ; + .dw 0xCD93 ; + .dw 0xE8A4 ; + .dw 0x460F ; + .dw 0xE8A5 ; + .dw 0x1EAF ; + .dw 0xE8A6 ; + .dw 0xDFD1 ; + .dw 0xE8A7 ; + .dw 0x6921 ; + .dw 0xE8A8 ; + .dw 0xE397 ; + .dw 0xE8A9 ; + .dw 0x6BB9 ; + .dw 0xE8AA ; + .dw 0xFBEB ; + .dw 0xE8AB ; + .dw 0x6E7 ; + .dw 0xE8AC ; + .dw 0x4367 ; + .dw 0xE8AD ; + .dw 0xA337 ; + .dw 0xE8AE ; + .dw 0xE6A3 ; + .dw 0xE8AF ; + .dw 0xEA89 ; + .dw 0xE8B0 ; + .dw 0xB2B1 ; + .dw 0xE8B1 ; + .dw 0xA6D ; + .dw 0xE8B2 ; + .dw 0x428D ; + .dw 0xE8B3 ; + .dw 0x993D ; + .dw 0xE8B4 ; + .dw 0x5B73 ; + .dw 0xE8B5 ; + .dw 0x8717 ; + .dw 0xE8B6 ; + .dw 0xE189 ; + .dw 0xE8B7 ; + .dw 0x1F87 ; + .dw 0xE8B8 ; + .dw 0x3D3 ; + .dw 0xE8B9 ; + .dw 0xE7ED ; + .dw 0xE8BA ; + .dw 0x2FDB ; + .dw 0xE8BB ; + .dw 0xFA71 ; + .dw 0xE8BC ; + .dw 0x6AF7 ; + .dw 0xE8BD ; + .dw 0x3C97 ; + .dw 0xE8BE ; + .dw 0x38B9 ; + .dw 0xE8BF ; + .dw 0x5C3B ; + .dw 0xE8C0 ; + .dw 0x9B53 ; + .dw 0xE8C1 ; + .dw 0xB51F ; + .dw 0xE8C2 ; + .dw 0x5C73 ; + .dw 0xE8C3 ; + .dw 0x49D ; + .dw 0xE8C4 ; + .dw 0xA8F ; + .dw 0xE8C5 ; + .dw 0xF3 ; + .dw 0xE8C6 ; + .dw 0x4FFB ; + .dw 0xE8C7 ; + .dw 0x6479 ; + .dw 0xE8C8 ; + .dw 0xDED5 ; + .dw 0xE8C9 ; + .dw 0xA557 ; + .dw 0xE8CA ; + .dw 0x7E0D ; + .dw 0xE8CB ; + .dw 0x4513 ; + .dw 0xE8CC ; + .dw 0x31AF ; + .dw 0xE8CD ; + .dw 0x4361 ; + .dw 0xE8CE ; + .dw 0x61B5 ; + .dw 0xE8CF ; + .dw 0xAACB ; + .dw 0xE8D0 ; + .dw 0xA85B ; + .dw 0xE8D1 ; + .dw 0x4569 ; + .dw 0xE8D2 ; + .dw 0xF277 ; + .dw 0xE8D3 ; + .dw 0x2B57 ; + .dw 0xE8D4 ; + .dw 0x39A5 ; + .dw 0xE8D5 ; + .dw 0xEC0F ; + .dw 0xE8D6 ; + .dw 0xB9DF ; + .dw 0xE8D7 ; + .dw 0x6F75 ; + .dw 0xE8D8 ; + .dw 0x793F ; + .dw 0xE8D9 ; + .dw 0x32A1 ; + .dw 0xE8DA ; + .dw 0xAA99 ; + .dw 0xE8DB ; + .dw 0x1829 ; + .dw 0xE8DC ; + .dw 0x4097 ; + .dw 0xE8DD ; + .dw 0x8323 ; + .dw 0xE8DE ; + .dw 0x510B ; + .dw 0xE8DF ; + .dw 0xBF73 ; + .dw 0xE8E0 ; + .dw 0xD31 ; + .dw 0xE8E1 ; + .dw 0xB1BD ; + .dw 0xE8E2 ; + .dw 0x756F ; + .dw 0xE8E3 ; + .dw 0x4C83 ; + .dw 0xE8E4 ; + .dw 0xEC7F ; + .dw 0xE8E5 ; + .dw 0x37BB ; + .dw 0xE8E6 ; + .dw 0xC767 ; + .dw 0xE8E7 ; + .dw 0x5379 ; + .dw 0xE8E8 ; + .dw 0x4D39 ; + .dw 0xE8E9 ; + .dw 0x25F9 ; + .dw 0xE8EA ; + .dw 0xAB13 ; + .dw 0xE8EB ; + .dw 0xB895 ; + .dw 0xE8EC ; + .dw 0x8E35 ; + .dw 0xE8ED ; + .dw 0xC6EB ; + .dw 0xE8EE ; + .dw 0xBFB3 ; + .dw 0xE8EF ; + .dw 0x4EF3 ; + .dw 0xE8F0 ; + .dw 0xA2B9 ; + .dw 0xE8F1 ; + .dw 0x6807 ; + .dw 0xE8F2 ; + .dw 0x37B3 ; + .dw 0xE8F3 ; + .dw 0xAAC3 ; + .dw 0xE8F4 ; + .dw 0xA461 ; + .dw 0xE8F5 ; + .dw 0x42C3 ; + .dw 0xE8F6 ; + .dw 0x9A4B ; + .dw 0xE8F7 ; + .dw 0xDF03 ; + .dw 0xE8F8 ; + .dw 0xAA6B ; + .dw 0xE8F9 ; + .dw 0xFD0F ; + .dw 0xE8FA ; + .dw 0x695 ; + .dw 0xE8FB ; + .dw 0x5EB1 ; + .dw 0xE8FC ; + .dw 0xBE8D ; + .dw 0xE8FD ; + .dw 0xB949 ; + .dw 0xE8FE ; + .dw 0x9023 ; + .dw 0xE8FF ; + .dw 0xB987 ; + .dw 0xE900 ; + .dw 0x475B ; + .dw 0xE901 ; + .dw 0x2DB5 ; + .dw 0xE902 ; + .dw 0xCD17 ; + .dw 0xE903 ; + .dw 0x6C33 ; + .dw 0xE904 ; + .dw 0xC013 ; + .dw 0xE905 ; + .dw 0xBB77 ; + .dw 0xE906 ; + .dw 0x2DC3 ; + .dw 0xE907 ; + .dw 0x7C11 ; + .dw 0xE908 ; + .dw 0x15F7 ; + .dw 0xE909 ; + .dw 0xFD0F ; + .dw 0xE90A ; + .dw 0x35B1 ; + .dw 0xE90B ; + .dw 0x165D ; + .dw 0xE90C ; + .dw 0x8327 ; + .dw 0xE90D ; + .dw 0xC449 ; + .dw 0xE90E ; + .dw 0x2E4F ; + .dw 0xE90F ; + .dw 0xEAEF ; + .dw 0xE910 ; + .dw 0x3EFB ; + .dw 0xE911 ; + .dw 0xFFB3 ; + .dw 0xE912 ; + .dw 0x6AF3 ; + .dw 0xE913 ; + .dw 0x7A73 ; + .dw 0xE914 ; + .dw 0xDBD7 ; + .dw 0xE915 ; + .dw 0x7FA7 ; + .dw 0xE916 ; + .dw 0xB681 ; + .dw 0xE917 ; + .dw 0x1023 ; + .dw 0xE918 ; + .dw 0xAA85 ; + .dw 0xE919 ; + .dw 0x12A9 ; + .dw 0xE91A ; + .dw 0x27F ; + .dw 0xE91B ; + .dw 0x9EF7 ; + .dw 0xE91C ; + .dw 0xFB09 ; + .dw 0xE91D ; + .dw 0xF179 ; + .dw 0xE91E ; + .dw 0xEFAD ; + .dw 0xE91F ; + .dw 0x3A67 ; + .dw 0xE920 ; + .dw 0x9301 ; + .dw 0xE921 ; + .dw 0xF273 ; + .dw 0xE922 ; + .dw 0x4819 ; + .dw 0xE923 ; + .dw 0x629F ; + .dw 0xE924 ; + .dw 0x3177 ; + .dw 0xE925 ; + .dw 0x7C9B ; + .dw 0xE926 ; + .dw 0x2BD ; + .dw 0xE927 ; + .dw 0xDC33 ; + .dw 0xE928 ; + .dw 0x783B ; + .dw 0xE929 ; + .dw 0xB20B ; + .dw 0xE92A ; + .dw 0xE895 ; + .dw 0xE92B ; + .dw 0x4B5D ; + .dw 0xE92C ; + .dw 0x12B7 ; + .dw 0xE92D ; + .dw 0xC9E7 ; + .dw 0xE92E ; + .dw 0x7335 ; + .dw 0xE92F ; + .dw 0x4AB1 ; + .dw 0xE930 ; + .dw 0x7251 ; + .dw 0xE931 ; + .dw 0x11E1 ; + .dw 0xE932 ; + .dw 0xFCE3 ; + .dw 0xE933 ; + .dw 0x3557 ; + .dw 0xE934 ; + .dw 0xF837 ; + .dw 0xE935 ; + .dw 0x8F27 ; + .dw 0xE936 ; + .dw 0xDA2F ; + .dw 0xE937 ; + .dw 0x5CC3 ; + .dw 0xE938 ; + .dw 0xE4BD ; + .dw 0xE939 ; + .dw 0xB6DF ; + .dw 0xE93A ; + .dw 0x7509 ; + .dw 0xE93B ; + .dw 0xE1EB ; + .dw 0xE93C ; + .dw 0xE439 ; + .dw 0xE93D ; + .dw 0x3621 ; + .dw 0xE93E ; + .dw 0x15D ; + .dw 0xE93F ; + .dw 0xEA05 ; + .dw 0xE940 ; + .dw 0x9151 ; + .dw 0xE941 ; + .dw 0x4169 ; + .dw 0xE942 ; + .dw 0xE325 ; + .dw 0xE943 ; + .dw 0x66B5 ; + .dw 0xE944 ; + .dw 0xC4DD ; + .dw 0xE945 ; + .dw 0x6395 ; + .dw 0xE946 ; + .dw 0x5E09 ; + .dw 0xE947 ; + .dw 0x29CD ; + .dw 0xE948 ; + .dw 0xB35 ; + .dw 0xE949 ; + .dw 0x4459 ; + .dw 0xE94A ; + .dw 0xA671 ; + .dw 0xE94B ; + .dw 0x7C83 ; + .dw 0xE94C ; + .dw 0x1715 ; + .dw 0xE94D ; + .dw 0x5E37 ; + .dw 0xE94E ; + .dw 0xEC19 ; + .dw 0xE94F ; + .dw 0xF227 ; + .dw 0xE950 ; + .dw 0x89E9 ; + .dw 0xE951 ; + .dw 0x1BFD ; + .dw 0xE952 ; + .dw 0x7637 ; + .dw 0xE953 ; + .dw 0xAE5B ; + .dw 0xE954 ; + .dw 0xE9AF ; + .dw 0xE955 ; + .dw 0x55B5 ; + .dw 0xE956 ; + .dw 0x6905 ; + .dw 0xE957 ; + .dw 0xD6D3 ; + .dw 0xE958 ; + .dw 0x1C47 ; + .dw 0xE959 ; + .dw 0xA523 ; + .dw 0xE95A ; + .dw 0x4CE1 ; + .dw 0xE95B ; + .dw 0x687F ; + .dw 0xE95C ; + .dw 0x404F ; + .dw 0xE95D ; + .dw 0x89B5 ; + .dw 0xE95E ; + .dw 0xEEE1 ; + .dw 0xE95F ; + .dw 0x2851 ; + .dw 0xE960 ; + .dw 0x3B7D ; + .dw 0xE961 ; + .dw 0xD409 ; + .dw 0xE962 ; + .dw 0xB2ED ; + .dw 0xE963 ; + .dw 0xE767 ; + .dw 0xE964 ; + .dw 0xD673 ; + .dw 0xE965 ; + .dw 0x50D5 ; + .dw 0xE966 ; + .dw 0xEF57 ; + .dw 0xE967 ; + .dw 0xD2D1 ; + .dw 0xE968 ; + .dw 0xBE17 ; + .dw 0xE969 ; + .dw 0x2B6B ; + .dw 0xE96A ; + .dw 0x69F1 ; + .dw 0xE96B ; + .dw 0x6C1 ; + .dw 0xE96C ; + .dw 0x426F ; + .dw 0xE96D ; + .dw 0xFFA9 ; + .dw 0xE96E ; + .dw 0x8EA9 ; + .dw 0xE96F ; + .dw 0x1D41 ; + .dw 0xE970 ; + .dw 0x2AF5 ; + .dw 0xE971 ; + .dw 0x1379 ; + .dw 0xE972 ; + .dw 0x779D ; + .dw 0xE973 ; + .dw 0xF075 ; + .dw 0xE974 ; + .dw 0x7871 ; + .dw 0xE975 ; + .dw 0xAFC1 ; + .dw 0xE976 ; + .dw 0x5EB3 ; + .dw 0xE977 ; + .dw 0x4845 ; + .dw 0xE978 ; + .dw 0x6C4F ; + .dw 0xE979 ; + .dw 0x10E1 ; + .dw 0xE97A ; + .dw 0x90B7 ; + .dw 0xE97B ; + .dw 0xABA3 ; + .dw 0xE97C ; + .dw 0xAD7B ; + .dw 0xE97D ; + .dw 0xE6A3 ; + .dw 0xE97E ; + .dw 0x79E9 ; + .dw 0xE97F ; + .dw 0xD37 ; + .dw 0xE980 ; + .dw 0xE2B5 ; + .dw 0xE981 ; + .dw 0xDBBF ; + .dw 0xE982 ; + .dw 0xE41D ; + .dw 0xE983 ; + .dw 0x8BA3 ; + .dw 0xE984 ; + .dw 0x9A6B ; + .dw 0xE985 ; + .dw 0x1CCB ; + .dw 0xE986 ; + .dw 0xFE53 ; + .dw 0xE987 ; + .dw 0xFD2D ; + .dw 0xE988 ; + .dw 0xD811 ; + .dw 0xE989 ; + .dw 0x56B1 ; + .dw 0xE98A ; + .dw 0x45C9 ; + .dw 0xE98B ; + .dw 0x7F05 ; + .dw 0xE98C ; + .dw 0x1EF7 ; + .dw 0xE98D ; + .dw 0x24AF ; + .dw 0xE98E ; + .dw 0xE895 ; + .dw 0xE98F ; + .dw 0xBFF1 ; + .dw 0xE990 ; + .dw 0x52A5 ; + .dw 0xE991 ; + .dw 0x65C7 ; + .dw 0xE992 ; + .dw 0xB9C5 ; + .dw 0xE993 ; + .dw 0x3E8F ; + .dw 0xE994 ; + .dw 0x44AB ; + .dw 0xE995 ; + .dw 0x71BD ; + .dw 0xE996 ; + .dw 0x4EEB ; + .dw 0xE997 ; + .dw 0x3307 ; + .dw 0xE998 ; + .dw 0x4807 ; + .dw 0xE999 ; + .dw 0xA58B ; + .dw 0xE99A ; + .dw 0x5F3B ; + .dw 0xE99B ; + .dw 0x5C45 ; + .dw 0xE99C ; + .dw 0xA1EB ; + .dw 0xE99D ; + .dw 0x3F5B ; + .dw 0xE99E ; + .dw 0xFC25 ; + .dw 0xE99F ; + .dw 0x68AD ; + .dw 0xE9A0 ; + .dw 0x3029 ; + .dw 0xE9A1 ; + .dw 0x1FD ; + .dw 0xE9A2 ; + .dw 0xBB69 ; + .dw 0xE9A3 ; + .dw 0x3259 ; + .dw 0xE9A4 ; + .dw 0x1CF5 ; + .dw 0xE9A5 ; + .dw 0x97E5 ; + .dw 0xE9A6 ; + .dw 0x6AB1 ; + .dw 0xE9A7 ; + .dw 0x86D3 ; + .dw 0xE9A8 ; + .dw 0xF853 ; + .dw 0xE9A9 ; + .dw 0x2D9B ; + .dw 0xE9AA ; + .dw 0x64A5 ; + .dw 0xE9AB ; + .dw 0xB23F ; + .dw 0xE9AC ; + .dw 0xEDD ; + .dw 0xE9AD ; + .dw 0x3BB5 ; + .dw 0xE9AE ; + .dw 0x1F8F ; + .dw 0xE9AF ; + .dw 0x8627 ; + .dw 0xE9B0 ; + .dw 0x5627 ; + .dw 0xE9B1 ; + .dw 0xF853 ; + .dw 0xE9B2 ; + .dw 0xD5F ; + .dw 0xE9B3 ; + .dw 0x139F ; + .dw 0xE9B4 ; + .dw 0xC691 ; + .dw 0xE9B5 ; + .dw 0x6815 ; + .dw 0xE9B6 ; + .dw 0x655B ; + .dw 0xE9B7 ; + .dw 0xD10B ; + .dw 0xE9B8 ; + .dw 0x7A9D ; + .dw 0xE9B9 ; + .dw 0x868F ; + .dw 0xE9BA ; + .dw 0xEF1F ; + .dw 0xE9BB ; + .dw 0x6355 ; + .dw 0xE9BC ; + .dw 0x6BD3 ; + .dw 0xE9BD ; + .dw 0x7E4B ; + .dw 0xE9BE ; + .dw 0x6747 ; + .dw 0xE9BF ; + .dw 0xC29D ; + .dw 0xE9C0 ; + .dw 0x2507 ; + .dw 0xE9C1 ; + .dw 0x6833 ; + .dw 0xE9C2 ; + .dw 0x957F ; + .dw 0xE9C3 ; + .dw 0xF27B ; + .dw 0xE9C4 ; + .dw 0x4241 ; + .dw 0xE9C5 ; + .dw 0x8A97 ; + .dw 0xE9C6 ; + .dw 0xAC1D ; + .dw 0xE9C7 ; + .dw 0x5B1 ; + .dw 0xE9C8 ; + .dw 0x160B ; + .dw 0xE9C9 ; + .dw 0x8F99 ; + .dw 0xE9CA ; + .dw 0x939 ; + .dw 0xE9CB ; + .dw 0xA561 ; + .dw 0xE9CC ; + .dw 0x4C51 ; + .dw 0xE9CD ; + .dw 0xAB2D ; + .dw 0xE9CE ; + .dw 0xF143 ; + .dw 0xE9CF ; + .dw 0xD3CF ; + .dw 0xE9D0 ; + .dw 0xE2AD ; + .dw 0xE9D1 ; + .dw 0x288F ; + .dw 0xE9D2 ; + .dw 0x5B1D ; + .dw 0xE9D3 ; + .dw 0x228F ; + .dw 0xE9D4 ; + .dw 0x4E4D ; + .dw 0xE9D5 ; + .dw 0x573B ; + .dw 0xE9D6 ; + .dw 0x65B1 ; + .dw 0xE9D7 ; + .dw 0x143F ; + .dw 0xE9D8 ; + .dw 0x2743 ; + .dw 0xE9D9 ; + .dw 0x4F61 ; + .dw 0xE9DA ; + .dw 0x8F0F ; + .dw 0xE9DB ; + .dw 0xE1C5 ; + .dw 0xE9DC ; + .dw 0x315D ; + .dw 0xE9DD ; + .dw 0x85E7 ; + .dw 0xE9DE ; + .dw 0x44FB ; + .dw 0xE9DF ; + .dw 0x5AFB ; + .dw 0xE9E0 ; + .dw 0x1A81 ; + .dw 0xE9E1 ; + .dw 0xA7D3 ; + .dw 0xE9E2 ; + .dw 0xE70F ; + .dw 0xE9E3 ; + .dw 0x1AF7 ; + .dw 0xE9E4 ; + .dw 0xC67D ; + .dw 0xE9E5 ; + .dw 0xB54D ; + .dw 0xE9E6 ; + .dw 0xD24B ; + .dw 0xE9E7 ; + .dw 0xC7B7 ; + .dw 0xE9E8 ; + .dw 0x806B ; + .dw 0xE9E9 ; + .dw 0xD419 ; + .dw 0xE9EA ; + .dw 0x8E35 ; + .dw 0xE9EB ; + .dw 0x955B ; + .dw 0xE9EC ; + .dw 0xE981 ; + .dw 0xE9ED ; + .dw 0xD187 ; + .dw 0xE9EE ; + .dw 0xB365 ; + .dw 0xE9EF ; + .dw 0xC4DF ; + .dw 0xE9F0 ; + .dw 0xFD67 ; + .dw 0xE9F1 ; + .dw 0xCBEB ; + .dw 0xE9F2 ; + .dw 0xA3AD ; + .dw 0xE9F3 ; + .dw 0x5653 ; + .dw 0xE9F4 ; + .dw 0x415 ; + .dw 0xE9F5 ; + .dw 0xFB9F ; + .dw 0xE9F6 ; + .dw 0xABA3 ; + .dw 0xE9F7 ; + .dw 0xA695 ; + .dw 0xE9F8 ; + .dw 0xC929 ; + .dw 0xE9F9 ; + .dw 0x136F ; + .dw 0xE9FA ; + .dw 0xA5BF ; + .dw 0xE9FB ; + .dw 0x3083 ; + .dw 0xE9FC ; + .dw 0xF0BF ; + .dw 0xE9FD ; + .dw 0x309B ; + .dw 0xE9FE ; + .dw 0xB6F5 ; + .dw 0xE9FF ; + .dw 0x29B7 ; + .dw 0xEA00 ; + .dw 0xC1C5 ; + .dw 0xEA01 ; + .dw 0xD249 ; + .dw 0xEA02 ; + .dw 0x3CCB ; + .dw 0xEA03 ; + .dw 0x32BF ; + .dw 0xEA04 ; + .dw 0x3DDB ; + .dw 0xEA05 ; + .dw 0xD07B ; + .dw 0xEA06 ; + .dw 0x84EB ; + .dw 0xEA07 ; + .dw 0xD2D7 ; + .dw 0xEA08 ; + .dw 0xDEA3 ; + .dw 0xEA09 ; + .dw 0xCA8F ; + .dw 0xEA0A ; + .dw 0x6645 ; + .dw 0xEA0B ; + .dw 0xF71B ; + .dw 0xEA0C ; + .dw 0xD09F ; + .dw 0xEA0D ; + .dw 0x533 ; + .dw 0xEA0E ; + .dw 0x53A3 ; + .dw 0xEA0F ; + .dw 0x2D41 ; + .dw 0xEA10 ; + .dw 0x383 ; + .dw 0xEA11 ; + .dw 0x2FD7 ; + .dw 0xEA12 ; + .dw 0xFFBF ; + .dw 0xEA13 ; + .dw 0xD1DB ; + .dw 0xEA14 ; + .dw 0xE815 ; + .dw 0xEA15 ; + .dw 0x9B1 ; + .dw 0xEA16 ; + .dw 0x2ADB ; + .dw 0xEA17 ; + .dw 0xE9FB ; + .dw 0xEA18 ; + .dw 0x337F ; + .dw 0xEA19 ; + .dw 0x5E29 ; + .dw 0xEA1A ; + .dw 0xB1DD ; + .dw 0xEA1B ; + .dw 0xE07F ; + .dw 0xEA1C ; + .dw 0x8025 ; + .dw 0xEA1D ; + .dw 0x50DB ; + .dw 0xEA1E ; + .dw 0x76E3 ; + .dw 0xEA1F ; + .dw 0xDEBF ; + .dw 0xEA20 ; + .dw 0x2407 ; + .dw 0xEA21 ; + .dw 0x7107 ; + .dw 0xEA22 ; + .dw 0x3B5F ; + .dw 0xEA23 ; + .dw 0xF8C1 ; + .dw 0xEA24 ; + .dw 0x148B ; + .dw 0xEA25 ; + .dw 0x8C8D ; + .dw 0xEA26 ; + .dw 0x3A9 ; + .dw 0xEA27 ; + .dw 0xE4FF ; + .dw 0xEA28 ; + .dw 0x2FE3 ; + .dw 0xEA29 ; + .dw 0xBA69 ; + .dw 0xEA2A ; + .dw 0x1C1D ; + .dw 0xEA2B ; + .dw 0x7791 ; + .dw 0xEA2C ; + .dw 0xC3D9 ; + .dw 0xEA2D ; + .dw 0x94A1 ; + .dw 0xEA2E ; + .dw 0x57AD ; + .dw 0xEA2F ; + .dw 0x98EB ; + .dw 0xEA30 ; + .dw 0xAA33 ; + .dw 0xEA31 ; + .dw 0x19C3 ; + .dw 0xEA32 ; + .dw 0xA003 ; + .dw 0xEA33 ; + .dw 0xF015 ; + .dw 0xEA34 ; + .dw 0xD27F ; + .dw 0xEA35 ; + .dw 0x2DE1 ; + .dw 0xEA36 ; + .dw 0x6F0B ; + .dw 0xEA37 ; + .dw 0xF863 ; + .dw 0xEA38 ; + .dw 0x9173 ; + .dw 0xEA39 ; + .dw 0x32FD ; + .dw 0xEA3A ; + .dw 0x4A19 ; + .dw 0xEA3B ; + .dw 0xBAAB ; + .dw 0xEA3C ; + .dw 0x8DC1 ; + .dw 0xEA3D ; + .dw 0xB113 ; + .dw 0xEA3E ; + .dw 0xD677 ; + .dw 0xEA3F ; + .dw 0xE203 ; + .dw 0xEA40 ; + .dw 0xA271 ; + .dw 0xEA41 ; + .dw 0x857B ; + .dw 0xEA42 ; + .dw 0x9F7F ; + .dw 0xEA43 ; + .dw 0x63EF ; + .dw 0xEA44 ; + .dw 0x8EBB ; + .dw 0xEA45 ; + .dw 0x91F7 ; + .dw 0xEA46 ; + .dw 0x2639 ; + .dw 0xEA47 ; + .dw 0x7421 ; + .dw 0xEA48 ; + .dw 0xCB59 ; + .dw 0xEA49 ; + .dw 0x6317 ; + .dw 0xEA4A ; + .dw 0x5269 ; + .dw 0xEA4B ; + .dw 0xFBAF ; + .dw 0xEA4C ; + .dw 0x5D63 ; + .dw 0xEA4D ; + .dw 0xC63F ; + .dw 0xEA4E ; + .dw 0xDD33 ; + .dw 0xEA4F ; + .dw 0x4BC7 ; + .dw 0xEA50 ; + .dw 0xFEA7 ; + .dw 0xEA51 ; + .dw 0xC71F ; + .dw 0xEA52 ; + .dw 0xCD29 ; + .dw 0xEA53 ; + .dw 0x43F1 ; + .dw 0xEA54 ; + .dw 0x7383 ; + .dw 0xEA55 ; + .dw 0xC9D ; + .dw 0xEA56 ; + .dw 0x9BE5 ; + .dw 0xEA57 ; + .dw 0xA3BB ; + .dw 0xEA58 ; + .dw 0x6637 ; + .dw 0xEA59 ; + .dw 0xD5F ; + .dw 0xEA5A ; + .dw 0x1D23 ; + .dw 0xEA5B ; + .dw 0xBFF7 ; + .dw 0xEA5C ; + .dw 0x9FC3 ; + .dw 0xEA5D ; + .dw 0x13B5 ; + .dw 0xEA5E ; + .dw 0xBF5D ; + .dw 0xEA5F ; + .dw 0x5375 ; + .dw 0xEA60 ; + .dw 0xF639 ; + .dw 0xEA61 ; + .dw 0x8919 ; + .dw 0xEA62 ; + .dw 0x3DD9 ; + .dw 0xEA63 ; + .dw 0xA337 ; + .dw 0xEA64 ; + .dw 0xC89D ; + .dw 0xEA65 ; + .dw 0x8125 ; + .dw 0xEA66 ; + .dw 0x5C47 ; + .dw 0xEA67 ; + .dw 0xAE2B ; + .dw 0xEA68 ; + .dw 0x6035 ; + .dw 0xEA69 ; + .dw 0xFC07 ; + .dw 0xEA6A ; + .dw 0xC3DD ; + .dw 0xEA6B ; + .dw 0xA063 ; + .dw 0xEA6C ; + .dw 0xF69 ; + .dw 0xEA6D ; + .dw 0xD881 ; + .dw 0xEA6E ; + .dw 0x99E7 ; + .dw 0xEA6F ; + .dw 0x41C9 ; + .dw 0xEA70 ; + .dw 0x660F ; + .dw 0xEA71 ; + .dw 0xED5B ; + .dw 0xEA72 ; + .dw 0xE7E3 ; + .dw 0xEA73 ; + .dw 0x9861 ; + .dw 0xEA74 ; + .dw 0x534F ; + .dw 0xEA75 ; + .dw 0x4259 ; + .dw 0xEA76 ; + .dw 0x6D17 ; + .dw 0xEA77 ; + .dw 0x75F3 ; + .dw 0xEA78 ; + .dw 0x8CFB ; + .dw 0xEA79 ; + .dw 0xE0BD ; + .dw 0xEA7A ; + .dw 0xF1AD ; + .dw 0xEA7B ; + .dw 0x2951 ; + .dw 0xEA7C ; + .dw 0x1459 ; + .dw 0xEA7D ; + .dw 0x3331 ; + .dw 0xEA7E ; + .dw 0xB349 ; + .dw 0xEA7F ; + .dw 0xB03 ; + .dw 0xEA80 ; + .dw 0x308B ; + .dw 0xEA81 ; + .dw 0x6D4F ; + .dw 0xEA82 ; + .dw 0x31D ; + .dw 0xEA83 ; + .dw 0x1D8B ; + .dw 0xEA84 ; + .dw 0xB661 ; + .dw 0xEA85 ; + .dw 0xF289 ; + .dw 0xEA86 ; + .dw 0xAD87 ; + .dw 0xEA87 ; + .dw 0x790F ; + .dw 0xEA88 ; + .dw 0xF5AB ; + .dw 0xEA89 ; + .dw 0x34AD ; + .dw 0xEA8A ; + .dw 0x4327 ; + .dw 0xEA8B ; + .dw 0xBA9D ; + .dw 0xEA8C ; + .dw 0x241B ; + .dw 0xEA8D ; + .dw 0x1D5 ; + .dw 0xEA8E ; + .dw 0xDB77 ; + .dw 0xEA8F ; + .dw 0x2EE1 ; + .dw 0xEA90 ; + .dw 0x9D99 ; + .dw 0xEA91 ; + .dw 0xB9E5 ; + .dw 0xEA92 ; + .dw 0x68DD ; + .dw 0xEA93 ; + .dw 0xF053 ; + .dw 0xEA94 ; + .dw 0xD215 ; + .dw 0xEA95 ; + .dw 0x6383 ; + .dw 0xEA96 ; + .dw 0x3651 ; + .dw 0xEA97 ; + .dw 0xB0FD ; + .dw 0xEA98 ; + .dw 0x38ED ; + .dw 0xEA99 ; + .dw 0x1885 ; + .dw 0xEA9A ; + .dw 0xA665 ; + .dw 0xEA9B ; + .dw 0x67A9 ; + .dw 0xEA9C ; + .dw 0x21B5 ; + .dw 0xEA9D ; + .dw 0xC1F9 ; + .dw 0xEA9E ; + .dw 0xCBE7 ; + .dw 0xEA9F ; + .dw 0x989F ; + .dw 0xEAA0 ; + .dw 0xBA99 ; + .dw 0xEAA1 ; + .dw 0x9B8D ; + .dw 0xEAA2 ; + .dw 0xF3FB ; + .dw 0xEAA3 ; + .dw 0x71D9 ; + .dw 0xEAA4 ; + .dw 0x2435 ; + .dw 0xEAA5 ; + .dw 0x7693 ; + .dw 0xEAA6 ; + .dw 0xB9A7 ; + .dw 0xEAA7 ; + .dw 0x72BB ; + .dw 0xEAA8 ; + .dw 0xEAE7 ; + .dw 0xEAA9 ; + .dw 0x3475 ; + .dw 0xEAAA ; + .dw 0xBAF9 ; + .dw 0xEAAB ; + .dw 0xD74F ; + .dw 0xEAAC ; + .dw 0xBDAB ; + .dw 0xEAAD ; + .dw 0x70A9 ; + .dw 0xEAAE ; + .dw 0x8793 ; + .dw 0xEAAF ; + .dw 0x7EFD ; + .dw 0xEAB0 ; + .dw 0xBA75 ; + .dw 0xEAB1 ; + .dw 0xD231 ; + .dw 0xEAB2 ; + .dw 0xE0CB ; + .dw 0xEAB3 ; + .dw 0x86B9 ; + .dw 0xEAB4 ; + .dw 0x2805 ; + .dw 0xEAB5 ; + .dw 0xFC89 ; + .dw 0xEAB6 ; + .dw 0xE343 ; + .dw 0xEAB7 ; + .dw 0x4EC7 ; + .dw 0xEAB8 ; + .dw 0xF53F ; + .dw 0xEAB9 ; + .dw 0x982B ; + .dw 0xEABA ; + .dw 0x31FB ; + .dw 0xEABB ; + .dw 0x23F1 ; + .dw 0xEABC ; + .dw 0xD607 ; + .dw 0xEABD ; + .dw 0x6A79 ; + .dw 0xEABE ; + .dw 0xBAEB ; + .dw 0xEABF ; + .dw 0x4437 ; + .dw 0xEAC0 ; + .dw 0x5593 ; + .dw 0xEAC1 ; + .dw 0xF541 ; + .dw 0xEAC2 ; + .dw 0x2D23 ; + .dw 0xEAC3 ; + .dw 0x7711 ; + .dw 0xEAC4 ; + .dw 0xB64B ; + .dw 0xEAC5 ; + .dw 0x95B3 ; + .dw 0xEAC6 ; + .dw 0xB859 ; + .dw 0xEAC7 ; + .dw 0xF11F ; + .dw 0xEAC8 ; + .dw 0xF71B ; + .dw 0xEAC9 ; + .dw 0x9AD1 ; + .dw 0xEACA ; + .dw 0x2DFF ; + .dw 0xEACB ; + .dw 0xBB69 ; + .dw 0xEACC ; + .dw 0xD649 ; + .dw 0xEACD ; + .dw 0x4B71 ; + .dw 0xEACE ; + .dw 0x1BEB ; + .dw 0xEACF ; + .dw 0x560D ; + .dw 0xEAD0 ; + .dw 0x29D7 ; + .dw 0xEAD1 ; + .dw 0x53AD ; + .dw 0xEAD2 ; + .dw 0xF85B ; + .dw 0xEAD3 ; + .dw 0xCE81 ; + .dw 0xEAD4 ; + .dw 0x654F ; + .dw 0xEAD5 ; + .dw 0x91DF ; + .dw 0xEAD6 ; + .dw 0xF79D ; + .dw 0xEAD7 ; + .dw 0x143 ; + .dw 0xEAD8 ; + .dw 0xA521 ; + .dw 0xEAD9 ; + .dw 0xBB1B ; + .dw 0xEADA ; + .dw 0xA31F ; + .dw 0xEADB ; + .dw 0x3F17 ; + .dw 0xEADC ; + .dw 0x177D ; + .dw 0xEADD ; + .dw 0xCF23 ; + .dw 0xEADE ; + .dw 0xCA05 ; + .dw 0xEADF ; + .dw 0xDBD ; + .dw 0xEAE0 ; + .dw 0x1AA7 ; + .dw 0xEAE1 ; + .dw 0xD3DF ; + .dw 0xEAE2 ; + .dw 0xE347 ; + .dw 0xEAE3 ; + .dw 0x3C25 ; + .dw 0xEAE4 ; + .dw 0xE8D3 ; + .dw 0xEAE5 ; + .dw 0xD059 ; + .dw 0xEAE6 ; + .dw 0x7949 ; + .dw 0xEAE7 ; + .dw 0x22D ; + .dw 0xEAE8 ; + .dw 0x2975 ; + .dw 0xEAE9 ; + .dw 0x7F33 ; + .dw 0xEAEA ; + .dw 0xB6ED ; + .dw 0xEAEB ; + .dw 0x63D9 ; + .dw 0xEAEC ; + .dw 0x4025 ; + .dw 0xEAED ; + .dw 0xB09B ; + .dw 0xEAEE ; + .dw 0xAE2F ; + .dw 0xEAEF ; + .dw 0x9003 ; + .dw 0xEAF0 ; + .dw 0xB0EB ; + .dw 0xEAF1 ; + .dw 0xD3C7 ; + .dw 0xEAF2 ; + .dw 0x703D ; + .dw 0xEAF3 ; + .dw 0x729B ; + .dw 0xEAF4 ; + .dw 0x7221 ; + .dw 0xEAF5 ; + .dw 0x9FF1 ; + .dw 0xEAF6 ; + .dw 0x8F11 ; + .dw 0xEAF7 ; + .dw 0x325F ; + .dw 0xEAF8 ; + .dw 0x83C1 ; + .dw 0xEAF9 ; + .dw 0x54C7 ; + .dw 0xEAFA ; + .dw 0x2081 ; + .dw 0xEAFB ; + .dw 0xD20D ; + .dw 0xEAFC ; + .dw 0xA449 ; + .dw 0xEAFD ; + .dw 0x8A67 ; + .dw 0xEAFE ; + .dw 0xDAE1 ; + .dw 0xEAFF ; + .dw 0xAD1F ; + .dw 0xEB00 ; + .dw 0x7B07 ; + .dw 0xEB01 ; + .dw 0x8D3 ; + .dw 0xEB02 ; + .dw 0x6315 ; + .dw 0xEB03 ; + .dw 0x803 ; + .dw 0xEB04 ; + .dw 0xFFB ; + .dw 0xEB05 ; + .dw 0x9EF5 ; + .dw 0xEB06 ; + .dw 0x642B ; + .dw 0xEB07 ; + .dw 0x6BD5 ; + .dw 0xEB08 ; + .dw 0xE929 ; + .dw 0xEB09 ; + .dw 0x7107 ; + .dw 0xEB0A ; + .dw 0x8871 ; + .dw 0xEB0B ; + .dw 0x58F ; + .dw 0xEB0C ; + .dw 0xA56D ; + .dw 0xEB0D ; + .dw 0xB695 ; + .dw 0xEB0E ; + .dw 0xEC0F ; + .dw 0xEB0F ; + .dw 0xC0CD ; + .dw 0xEB10 ; + .dw 0x6CE3 ; + .dw 0xEB11 ; + .dw 0x5FF3 ; + .dw 0xEB12 ; + .dw 0x2123 ; + .dw 0xEB13 ; + .dw 0x55F9 ; + .dw 0xEB14 ; + .dw 0xEAB ; + .dw 0xEB15 ; + .dw 0x9B33 ; + .dw 0xEB16 ; + .dw 0x5D4D ; + .dw 0xEB17 ; + .dw 0x40D ; + .dw 0xEB18 ; + .dw 0x2451 ; + .dw 0xEB19 ; + .dw 0xB09F ; + .dw 0xEB1A ; + .dw 0xE8D1 ; + .dw 0xEB1B ; + .dw 0x2DC1 ; + .dw 0xEB1C ; + .dw 0x129B ; + .dw 0xEB1D ; + .dw 0x2EB5 ; + .dw 0xEB1E ; + .dw 0x6731 ; + .dw 0xEB1F ; + .dw 0x924D ; + .dw 0xEB20 ; + .dw 0x3FE3 ; + .dw 0xEB21 ; + .dw 0xDD91 ; + .dw 0xEB22 ; + .dw 0x113D ; + .dw 0xEB23 ; + .dw 0x599D ; + .dw 0xEB24 ; + .dw 0x57F7 ; + .dw 0xEB25 ; + .dw 0x71F7 ; + .dw 0xEB26 ; + .dw 0x78AD ; + .dw 0xEB27 ; + .dw 0xAC03 ; + .dw 0xEB28 ; + .dw 0xF563 ; + .dw 0xEB29 ; + .dw 0x77BF ; + .dw 0xEB2A ; + .dw 0xED3B ; + .dw 0xEB2B ; + .dw 0xD7D ; + .dw 0xEB2C ; + .dw 0x8855 ; + .dw 0xEB2D ; + .dw 0x6BD1 ; + .dw 0xEB2E ; + .dw 0x1B3D ; + .dw 0xEB2F ; + .dw 0x345D ; + .dw 0xEB30 ; + .dw 0xD2EF ; + .dw 0xEB31 ; + .dw 0x7D9D ; + .dw 0xEB32 ; + .dw 0xFBB9 ; + .dw 0xEB33 ; + .dw 0x938B ; + .dw 0xEB34 ; + .dw 0xD321 ; + .dw 0xEB35 ; + .dw 0xF011 ; + .dw 0xEB36 ; + .dw 0xAE01 ; + .dw 0xEB37 ; + .dw 0x503B ; + .dw 0xEB38 ; + .dw 0x7201 ; + .dw 0xEB39 ; + .dw 0x9215 ; + .dw 0xEB3A ; + .dw 0x52C1 ; + .dw 0xEB3B ; + .dw 0xDB23 ; + .dw 0xEB3C ; + .dw 0xD0A1 ; + .dw 0xEB3D ; + .dw 0x467B ; + .dw 0xEB3E ; + .dw 0x80A7 ; + .dw 0xEB3F ; + .dw 0xE539 ; + .dw 0xEB40 ; + .dw 0x8A6B ; + .dw 0xEB41 ; + .dw 0x1385 ; + .dw 0xEB42 ; + .dw 0x6A6F ; + .dw 0xEB43 ; + .dw 0xE7E1 ; + .dw 0xEB44 ; + .dw 0xC4F1 ; + .dw 0xEB45 ; + .dw 0xB1CF ; + .dw 0xEB46 ; + .dw 0x4E7F ; + .dw 0xEB47 ; + .dw 0xF8AD ; + .dw 0xEB48 ; + .dw 0x6553 ; + .dw 0xEB49 ; + .dw 0x12CB ; + .dw 0xEB4A ; + .dw 0x47FB ; + .dw 0xEB4B ; + .dw 0x2091 ; + .dw 0xEB4C ; + .dw 0x4307 ; + .dw 0xEB4D ; + .dw 0xD6C1 ; + .dw 0xEB4E ; + .dw 0x1967 ; + .dw 0xEB4F ; + .dw 0xEEA1 ; + .dw 0xEB50 ; + .dw 0xB03D ; + .dw 0xEB51 ; + .dw 0x2A37 ; + .dw 0xEB52 ; + .dw 0x8B3 ; + .dw 0xEB53 ; + .dw 0x7E3D ; + .dw 0xEB54 ; + .dw 0x2FAF ; + .dw 0xEB55 ; + .dw 0x2FD ; + .dw 0xEB56 ; + .dw 0x64DD ; + .dw 0xEB57 ; + .dw 0xA8D9 ; + .dw 0xEB58 ; + .dw 0xAFFF ; + .dw 0xEB59 ; + .dw 0x3495 ; + .dw 0xEB5A ; + .dw 0xCCFF ; + .dw 0xEB5B ; + .dw 0x9B25 ; + .dw 0xEB5C ; + .dw 0x248D ; + .dw 0xEB5D ; + .dw 0x542D ; + .dw 0xEB5E ; + .dw 0xD0F1 ; + .dw 0xEB5F ; + .dw 0x85D1 ; + .dw 0xEB60 ; + .dw 0xD3CD ; + .dw 0xEB61 ; + .dw 0xE423 ; + .dw 0xEB62 ; + .dw 0x35D ; + .dw 0xEB63 ; + .dw 0xA1BF ; + .dw 0xEB64 ; + .dw 0x331F ; + .dw 0xEB65 ; + .dw 0xBEED ; + .dw 0xEB66 ; + .dw 0x1551 ; + .dw 0xEB67 ; + .dw 0x3FBD ; + .dw 0xEB68 ; + .dw 0xA82B ; + .dw 0xEB69 ; + .dw 0x399B ; + .dw 0xEB6A ; + .dw 0x1361 ; + .dw 0xEB6B ; + .dw 0x1BBD ; + .dw 0xEB6C ; + .dw 0x7B9 ; + .dw 0xEB6D ; + .dw 0xF5D1 ; + .dw 0xEB6E ; + .dw 0x5C3D ; + .dw 0xEB6F ; + .dw 0xAB89 ; + .dw 0xEB70 ; + .dw 0x29FF ; + .dw 0xEB71 ; + .dw 0xDB33 ; + .dw 0xEB72 ; + .dw 0x68BF ; + .dw 0xEB73 ; + .dw 0xA105 ; + .dw 0xEB74 ; + .dw 0x6C87 ; + .dw 0xEB75 ; + .dw 0x3069 ; + .dw 0xEB76 ; + .dw 0xFD91 ; + .dw 0xEB77 ; + .dw 0x57D9 ; + .dw 0xEB78 ; + .dw 0x797D ; + .dw 0xEB79 ; + .dw 0x4B91 ; + .dw 0xEB7A ; + .dw 0xDE3B ; + .dw 0xEB7B ; + .dw 0x66B7 ; + .dw 0xEB7C ; + .dw 0x2C8F ; + .dw 0xEB7D ; + .dw 0xD239 ; + .dw 0xEB7E ; + .dw 0x99BF ; + .dw 0xEB7F ; + .dw 0xC07 ; + .dw 0xEB80 ; + .dw 0xED3B ; + .dw 0xEB81 ; + .dw 0xD7 ; + .dw 0xEB82 ; + .dw 0x88B3 ; + .dw 0xEB83 ; + .dw 0xAE29 ; + .dw 0xEB84 ; + .dw 0x56AD ; + .dw 0xEB85 ; + .dw 0xF1BF ; + .dw 0xEB86 ; + .dw 0x94D3 ; + .dw 0xEB87 ; + .dw 0x2727 ; + .dw 0xEB88 ; + .dw 0x851B ; + .dw 0xEB89 ; + .dw 0x5B9F ; + .dw 0xEB8A ; + .dw 0xE21F ; + .dw 0xEB8B ; + .dw 0x13EF ; + .dw 0xEB8C ; + .dw 0xE097 ; + .dw 0xEB8D ; + .dw 0xBF73 ; + .dw 0xEB8E ; + .dw 0xF16F ; + .dw 0xEB8F ; + .dw 0xDF07 ; + .dw 0xEB90 ; + .dw 0xBD65 ; + .dw 0xEB91 ; + .dw 0x7DFD ; + .dw 0xEB92 ; + .dw 0x548D ; + .dw 0xEB93 ; + .dw 0xBECD ; + .dw 0xEB94 ; + .dw 0xA9D7 ; + .dw 0xEB95 ; + .dw 0xCCC1 ; + .dw 0xEB96 ; + .dw 0x8BCD ; + .dw 0xEB97 ; + .dw 0x5F29 ; + .dw 0xEB98 ; + .dw 0xC1AB ; + .dw 0xEB99 ; + .dw 0x279 ; + .dw 0xEB9A ; + .dw 0x2525 ; + .dw 0xEB9B ; + .dw 0x6EC5 ; + .dw 0xEB9C ; + .dw 0xDED5 ; + .dw 0xEB9D ; + .dw 0x330D ; + .dw 0xEB9E ; + .dw 0xB4C3 ; + .dw 0xEB9F ; + .dw 0xC7C9 ; + .dw 0xEBA0 ; + .dw 0xFFE3 ; + .dw 0xEBA1 ; + .dw 0x9313 ; + .dw 0xEBA2 ; + .dw 0xBF25 ; + .dw 0xEBA3 ; + .dw 0x6C0F ; + .dw 0xEBA4 ; + .dw 0xBBCD ; + .dw 0xEBA5 ; + .dw 0x9AB9 ; + .dw 0xEBA6 ; + .dw 0x2CB7 ; + .dw 0xEBA7 ; + .dw 0xCDB ; + .dw 0xEBA8 ; + .dw 0x1B53 ; + .dw 0xEBA9 ; + .dw 0x6047 ; + .dw 0xEBAA ; + .dw 0x5EE3 ; + .dw 0xEBAB ; + .dw 0x5619 ; + .dw 0xEBAC ; + .dw 0xAFD3 ; + .dw 0xEBAD ; + .dw 0x2217 ; + .dw 0xEBAE ; + .dw 0x7EAF ; + .dw 0xEBAF ; + .dw 0xB50B ; + .dw 0xEBB0 ; + .dw 0x3F9D ; + .dw 0xEBB1 ; + .dw 0x7807 ; + .dw 0xEBB2 ; + .dw 0x1CCF ; + .dw 0xEBB3 ; + .dw 0xD28B ; + .dw 0xEBB4 ; + .dw 0xDFD3 ; + .dw 0xEBB5 ; + .dw 0x2477 ; + .dw 0xEBB6 ; + .dw 0xBB43 ; + .dw 0xEBB7 ; + .dw 0x78BB ; + .dw 0xEBB8 ; + .dw 0xD3B9 ; + .dw 0xEBB9 ; + .dw 0xFCBD ; + .dw 0xEBBA ; + .dw 0x586F ; + .dw 0xEBBB ; + .dw 0x1C45 ; + .dw 0xEBBC ; + .dw 0x993 ; + .dw 0xEBBD ; + .dw 0xE11D ; + .dw 0xEBBE ; + .dw 0x93A9 ; + .dw 0xEBBF ; + .dw 0xC109 ; + .dw 0xEBC0 ; + .dw 0x8CF7 ; + .dw 0xEBC1 ; + .dw 0x3C47 ; + .dw 0xEBC2 ; + .dw 0x8361 ; + .dw 0xEBC3 ; + .dw 0x725F ; + .dw 0xEBC4 ; + .dw 0xC6AF ; + .dw 0xEBC5 ; + .dw 0x249 ; + .dw 0xEBC6 ; + .dw 0xD4AB ; + .dw 0xEBC7 ; + .dw 0x6C7 ; + .dw 0xEBC8 ; + .dw 0xE201 ; + .dw 0xEBC9 ; + .dw 0xA703 ; + .dw 0xEBCA ; + .dw 0x4C5D ; + .dw 0xEBCB ; + .dw 0x6729 ; + .dw 0xEBCC ; + .dw 0x2F9B ; + .dw 0xEBCD ; + .dw 0x42D ; + .dw 0xEBCE ; + .dw 0x41A9 ; + .dw 0xEBCF ; + .dw 0x1183 ; + .dw 0xEBD0 ; + .dw 0xDDD9 ; + .dw 0xEBD1 ; + .dw 0xA6C1 ; + .dw 0xEBD2 ; + .dw 0x2A31 ; + .dw 0xEBD3 ; + .dw 0xF29 ; + .dw 0xEBD4 ; + .dw 0xDEA7 ; + .dw 0xEBD5 ; + .dw 0x7BFB ; + .dw 0xEBD6 ; + .dw 0xCFA1 ; + .dw 0xEBD7 ; + .dw 0x167D ; + .dw 0xEBD8 ; + .dw 0x52D5 ; + .dw 0xEBD9 ; + .dw 0x55CB ; + .dw 0xEBDA ; + .dw 0x46C5 ; + .dw 0xEBDB ; + .dw 0x1021 ; + .dw 0xEBDC ; + .dw 0x52F3 ; + .dw 0xEBDD ; + .dw 0x3ED7 ; + .dw 0xEBDE ; + .dw 0x4025 ; + .dw 0xEBDF ; + .dw 0xB7B5 ; + .dw 0xEBE0 ; + .dw 0x6DA7 ; + .dw 0xEBE1 ; + .dw 0x15E3 ; + .dw 0xEBE2 ; + .dw 0xCA17 ; + .dw 0xEBE3 ; + .dw 0x9009 ; + .dw 0xEBE4 ; + .dw 0xB381 ; + .dw 0xEBE5 ; + .dw 0x68DD ; + .dw 0xEBE6 ; + .dw 0x1C5F ; + .dw 0xEBE7 ; + .dw 0xE2DB ; + .dw 0xEBE8 ; + .dw 0xA857 ; + .dw 0xEBE9 ; + .dw 0x743 ; + .dw 0xEBEA ; + .dw 0x853D ; + .dw 0xEBEB ; + .dw 0x40F ; + .dw 0xEBEC ; + .dw 0xF221 ; + .dw 0xEBED ; + .dw 0x4425 ; + .dw 0xEBEE ; + .dw 0x1011 ; + .dw 0xEBEF ; + .dw 0x905F ; + .dw 0xEBF0 ; + .dw 0x1D49 ; + .dw 0xEBF1 ; + .dw 0x5F9B ; + .dw 0xEBF2 ; + .dw 0xFD67 ; + .dw 0xEBF3 ; + .dw 0xDF9B ; + .dw 0xEBF4 ; + .dw 0x4E83 ; + .dw 0xEBF5 ; + .dw 0xFBD ; + .dw 0xEBF6 ; + .dw 0xA497 ; + .dw 0xEBF7 ; + .dw 0x6261 ; + .dw 0xEBF8 ; + .dw 0x3A31 ; + .dw 0xEBF9 ; + .dw 0xA117 ; + .dw 0xEBFA ; + .dw 0xD6DB ; + .dw 0xEBFB ; + .dw 0x234D ; + .dw 0xEBFC ; + .dw 0x392B ; + .dw 0xEBFD ; + .dw 0xA6A9 ; + .dw 0xEBFE ; + .dw 0x5BE5 ; + .dw 0xEBFF ; + .dw 0x23BD ; + .dw 0xEC00 ; + .dw 0xD323 ; + .dw 0xEC01 ; + .dw 0xB157 ; + .dw 0xEC02 ; + .dw 0x9FF7 ; + .dw 0xEC03 ; + .dw 0xCBFF ; + .dw 0xEC04 ; + .dw 0x9675 ; + .dw 0xEC05 ; + .dw 0x6E9 ; + .dw 0xEC06 ; + .dw 0x2B83 ; + .dw 0xEC07 ; + .dw 0x2709 ; + .dw 0xEC08 ; + .dw 0x9585 ; + .dw 0xEC09 ; + .dw 0xD077 ; + .dw 0xEC0A ; + .dw 0xFC33 ; + .dw 0xEC0B ; + .dw 0x21BD ; + .dw 0xEC0C ; + .dw 0x6195 ; + .dw 0xEC0D ; + .dw 0xB86F ; + .dw 0xEC0E ; + .dw 0x5795 ; + .dw 0xEC0F ; + .dw 0x8591 ; + .dw 0xEC10 ; + .dw 0xDB1B ; + .dw 0xEC11 ; + .dw 0x7005 ; + .dw 0xEC12 ; + .dw 0x2F1F ; + .dw 0xEC13 ; + .dw 0xE6D1 ; + .dw 0xEC14 ; + .dw 0xAF9B ; + .dw 0xEC15 ; + .dw 0x142D ; + .dw 0xEC16 ; + .dw 0xADD5 ; + .dw 0xEC17 ; + .dw 0x3E55 ; + .dw 0xEC18 ; + .dw 0xDCFB ; + .dw 0xEC19 ; + .dw 0xEA0F ; + .dw 0xEC1A ; + .dw 0x75F ; + .dw 0xEC1B ; + .dw 0x66B9 ; + .dw 0xEC1C ; + .dw 0x1267 ; + .dw 0xEC1D ; + .dw 0x6B05 ; + .dw 0xEC1E ; + .dw 0x2099 ; + .dw 0xEC1F ; + .dw 0x3513 ; + .dw 0xEC20 ; + .dw 0x4699 ; + .dw 0xEC21 ; + .dw 0x1813 ; + .dw 0xEC22 ; + .dw 0x29B3 ; + .dw 0xEC23 ; + .dw 0x652F ; + .dw 0xEC24 ; + .dw 0x5BB9 ; + .dw 0xEC25 ; + .dw 0xCD9 ; + .dw 0xEC26 ; + .dw 0xC1C7 ; + .dw 0xEC27 ; + .dw 0x1141 ; + .dw 0xEC28 ; + .dw 0x28BB ; + .dw 0xEC29 ; + .dw 0xCA0D ; + .dw 0xEC2A ; + .dw 0xBBF1 ; + .dw 0xEC2B ; + .dw 0xED21 ; + .dw 0xEC2C ; + .dw 0xC027 ; + .dw 0xEC2D ; + .dw 0x2F7B ; + .dw 0xEC2E ; + .dw 0x1DE5 ; + .dw 0xEC2F ; + .dw 0xFD07 ; + .dw 0xEC30 ; + .dw 0x4C81 ; + .dw 0xEC31 ; + .dw 0x1D6F ; + .dw 0xEC32 ; + .dw 0x7009 ; + .dw 0xEC33 ; + .dw 0xFFB9 ; + .dw 0xEC34 ; + .dw 0x5A19 ; + .dw 0xEC35 ; + .dw 0xB5BB ; + .dw 0xEC36 ; + .dw 0xF70D ; + .dw 0xEC37 ; + .dw 0x4449 ; + .dw 0xEC38 ; + .dw 0xE667 ; + .dw 0xEC39 ; + .dw 0xB423 ; + .dw 0xEC3A ; + .dw 0xEF01 ; + .dw 0xEC3B ; + .dw 0x2353 ; + .dw 0xEC3C ; + .dw 0xCD9 ; + .dw 0xEC3D ; + .dw 0xD65D ; + .dw 0xEC3E ; + .dw 0x5FF1 ; + .dw 0xEC3F ; + .dw 0xD3A7 ; + .dw 0xEC40 ; + .dw 0xA93B ; + .dw 0xEC41 ; + .dw 0xCB87 ; + .dw 0xEC42 ; + .dw 0xA3F7 ; + .dw 0xEC43 ; + .dw 0xD28B ; + .dw 0xEC44 ; + .dw 0xC781 ; + .dw 0xEC45 ; + .dw 0xA31F ; + .dw 0xEC46 ; + .dw 0x36DD ; + .dw 0xEC47 ; + .dw 0x976F ; + .dw 0xEC48 ; + .dw 0x3927 ; + .dw 0xEC49 ; + .dw 0x3379 ; + .dw 0xEC4A ; + .dw 0xE725 ; + .dw 0xEC4B ; + .dw 0xCB2D ; + .dw 0xEC4C ; + .dw 0x2805 ; + .dw 0xEC4D ; + .dw 0x6FB9 ; + .dw 0xEC4E ; + .dw 0xB1 ; + .dw 0xEC4F ; + .dw 0xBAB1 ; + .dw 0xEC50 ; + .dw 0xFEAB ; + .dw 0xEC51 ; + .dw 0x2549 ; + .dw 0xEC52 ; + .dw 0x88D5 ; + .dw 0xEC53 ; + .dw 0x3D43 ; + .dw 0xEC54 ; + .dw 0x7E33 ; + .dw 0xEC55 ; + .dw 0x18D5 ; + .dw 0xEC56 ; + .dw 0x23EB ; + .dw 0xEC57 ; + .dw 0xC62F ; + .dw 0xEC58 ; + .dw 0x59A1 ; + .dw 0xEC59 ; + .dw 0xFAC1 ; + .dw 0xEC5A ; + .dw 0xBC71 ; + .dw 0xEC5B ; + .dw 0xDA0D ; + .dw 0xEC5C ; + .dw 0x2EB1 ; + .dw 0xEC5D ; + .dw 0x2B1D ; + .dw 0xEC5E ; + .dw 0x839D ; + .dw 0xEC5F ; + .dw 0x9F67 ; + .dw 0xEC60 ; + .dw 0x3437 ; + .dw 0xEC61 ; + .dw 0xC523 ; + .dw 0xEC62 ; + .dw 0x6377 ; + .dw 0xEC63 ; + .dw 0xC301 ; + .dw 0xEC64 ; + .dw 0x75F9 ; + .dw 0xEC65 ; + .dw 0xEA2B ; + .dw 0xEC66 ; + .dw 0x7A71 ; + .dw 0xEC67 ; + .dw 0x6789 ; + .dw 0xEC68 ; + .dw 0xF5F9 ; + .dw 0xEC69 ; + .dw 0xC429 ; + .dw 0xEC6A ; + .dw 0xB87F ; + .dw 0xEC6B ; + .dw 0x58CF ; + .dw 0xEC6C ; + .dw 0x8B61 ; + .dw 0xEC6D ; + .dw 0x3799 ; + .dw 0xEC6E ; + .dw 0x35AB ; + .dw 0xEC6F ; + .dw 0x3A81 ; + .dw 0xEC70 ; + .dw 0xD6C7 ; + .dw 0xEC71 ; + .dw 0xBD03 ; + .dw 0xEC72 ; + .dw 0x5A35 ; + .dw 0xEC73 ; + .dw 0xEA61 ; + .dw 0xEC74 ; + .dw 0x2415 ; + .dw 0xEC75 ; + .dw 0x59EF ; + .dw 0xEC76 ; + .dw 0x7023 ; + .dw 0xEC77 ; + .dw 0xCDF7 ; + .dw 0xEC78 ; + .dw 0x91D9 ; + .dw 0xEC79 ; + .dw 0x315D ; + .dw 0xEC7A ; + .dw 0xB661 ; + .dw 0xEC7B ; + .dw 0x43D3 ; + .dw 0xEC7C ; + .dw 0x561D ; + .dw 0xEC7D ; + .dw 0xA3B7 ; + .dw 0xEC7E ; + .dw 0x8D4F ; + .dw 0xEC7F ; + .dw 0xF043 ; + .dw 0xEC80 ; + .dw 0x78C1 ; + .dw 0xEC81 ; + .dw 0x7657 ; + .dw 0xEC82 ; + .dw 0xD4E1 ; + .dw 0xEC83 ; + .dw 0x1D81 ; + .dw 0xEC84 ; + .dw 0xDB51 ; + .dw 0xEC85 ; + .dw 0xFA6F ; + .dw 0xEC86 ; + .dw 0x1437 ; + .dw 0xEC87 ; + .dw 0xE779 ; + .dw 0xEC88 ; + .dw 0xE665 ; + .dw 0xEC89 ; + .dw 0xAB8B ; + .dw 0xEC8A ; + .dw 0x82AF ; + .dw 0xEC8B ; + .dw 0x6AF9 ; + .dw 0xEC8C ; + .dw 0xB46B ; + .dw 0xEC8D ; + .dw 0x3D89 ; + .dw 0xEC8E ; + .dw 0x8A81 ; + .dw 0xEC8F ; + .dw 0xB067 ; + .dw 0xEC90 ; + .dw 0x1207 ; + .dw 0xEC91 ; + .dw 0x920D ; + .dw 0xEC92 ; + .dw 0xDCD5 ; + .dw 0xEC93 ; + .dw 0x8A01 ; + .dw 0xEC94 ; + .dw 0x2BF3 ; + .dw 0xEC95 ; + .dw 0x8D77 ; + .dw 0xEC96 ; + .dw 0xAF63 ; + .dw 0xEC97 ; + .dw 0x1D8F ; + .dw 0xEC98 ; + .dw 0x4243 ; + .dw 0xEC99 ; + .dw 0x4363 ; + .dw 0xEC9A ; + .dw 0x3B7F ; + .dw 0xEC9B ; + .dw 0x519B ; + .dw 0xEC9C ; + .dw 0x394F ; + .dw 0xEC9D ; + .dw 0x729B ; + .dw 0xEC9E ; + .dw 0x16B5 ; + .dw 0xEC9F ; + .dw 0xD62B ; + .dw 0xECA0 ; + .dw 0x6005 ; + .dw 0xECA1 ; + .dw 0xC893 ; + .dw 0xECA2 ; + .dw 0x7CE7 ; + .dw 0xECA3 ; + .dw 0xFD ; + .dw 0xECA4 ; + .dw 0x43BD ; + .dw 0xECA5 ; + .dw 0xE457 ; + .dw 0xECA6 ; + .dw 0x23DD ; + .dw 0xECA7 ; + .dw 0x3533 ; + .dw 0xECA8 ; + .dw 0xE997 ; + .dw 0xECA9 ; + .dw 0x9113 ; + .dw 0xECAA ; + .dw 0xB065 ; + .dw 0xECAB ; + .dw 0xE99 ; + .dw 0xECAC ; + .dw 0x4551 ; + .dw 0xECAD ; + .dw 0x2FFD ; + .dw 0xECAE ; + .dw 0x64E1 ; + .dw 0xECAF ; + .dw 0x851 ; + .dw 0xECB0 ; + .dw 0x459B ; + .dw 0xECB1 ; + .dw 0xC9D5 ; + .dw 0xECB2 ; + .dw 0x2169 ; + .dw 0xECB3 ; + .dw 0xD715 ; + .dw 0xECB4 ; + .dw 0x4DF7 ; + .dw 0xECB5 ; + .dw 0xBFDB ; + .dw 0xECB6 ; + .dw 0x4D5B ; + .dw 0xECB7 ; + .dw 0x2EE7 ; + .dw 0xECB8 ; + .dw 0x760B ; + .dw 0xECB9 ; + .dw 0x9447 ; + .dw 0xECBA ; + .dw 0xC279 ; + .dw 0xECBB ; + .dw 0x2C4F ; + .dw 0xECBC ; + .dw 0x6675 ; + .dw 0xECBD ; + .dw 0xC23B ; + .dw 0xECBE ; + .dw 0x517F ; + .dw 0xECBF ; + .dw 0x1913 ; + .dw 0xECC0 ; + .dw 0x2B33 ; + .dw 0xECC1 ; + .dw 0x1D45 ; + .dw 0xECC2 ; + .dw 0xF835 ; + .dw 0xECC3 ; + .dw 0xC463 ; + .dw 0xECC4 ; + .dw 0xD369 ; + .dw 0xECC5 ; + .dw 0xB055 ; + .dw 0xECC6 ; + .dw 0x6115 ; + .dw 0xECC7 ; + .dw 0x26A7 ; + .dw 0xECC8 ; + .dw 0x36C1 ; + .dw 0xECC9 ; + .dw 0x942D ; + .dw 0xECCA ; + .dw 0xC453 ; + .dw 0xECCB ; + .dw 0x889F ; + .dw 0xECCC ; + .dw 0xB845 ; + .dw 0xECCD ; + .dw 0xB561 ; + .dw 0xECCE ; + .dw 0xC281 ; + .dw 0xECCF ; + .dw 0xE62F ; + .dw 0xECD0 ; + .dw 0x5EB3 ; + .dw 0xECD1 ; + .dw 0x1CF ; + .dw 0xECD2 ; + .dw 0x509F ; + .dw 0xECD3 ; + .dw 0xC48B ; + .dw 0xECD4 ; + .dw 0x1A57 ; + .dw 0xECD5 ; + .dw 0xF58F ; + .dw 0xECD6 ; + .dw 0x4DBD ; + .dw 0xECD7 ; + .dw 0x33F1 ; + .dw 0xECD8 ; + .dw 0x9061 ; + .dw 0xECD9 ; + .dw 0xFF75 ; + .dw 0xECDA ; + .dw 0xDA05 ; + .dw 0xECDB ; + .dw 0x34E5 ; + .dw 0xECDC ; + .dw 0x43C3 ; + .dw 0xECDD ; + .dw 0xB503 ; + .dw 0xECDE ; + .dw 0x75D ; + .dw 0xECDF ; + .dw 0x38E5 ; + .dw 0xECE0 ; + .dw 0x737F ; + .dw 0xECE1 ; + .dw 0x4DE1 ; + .dw 0xECE2 ; + .dw 0xFB7F ; + .dw 0xECE3 ; + .dw 0xF6A5 ; + .dw 0xECE4 ; + .dw 0x8687 ; + .dw 0xECE5 ; + .dw 0x5ED9 ; + .dw 0xECE6 ; + .dw 0x1B8B ; + .dw 0xECE7 ; + .dw 0x49C3 ; + .dw 0xECE8 ; + .dw 0x5D11 ; + .dw 0xECE9 ; + .dw 0x4C4B ; + .dw 0xECEA ; + .dw 0x5925 ; + .dw 0xECEB ; + .dw 0x55FD ; + .dw 0xECEC ; + .dw 0x5F77 ; + .dw 0xECED ; + .dw 0x6C29 ; + .dw 0xECEE ; + .dw 0x390B ; + .dw 0xECEF ; + .dw 0xA5F3 ; + .dw 0xECF0 ; + .dw 0xA27D ; + .dw 0xECF1 ; + .dw 0x4F69 ; + .dw 0xECF2 ; + .dw 0xAB29 ; + .dw 0xECF3 ; + .dw 0x7D53 ; + .dw 0xECF4 ; + .dw 0xF93F ; + .dw 0xECF5 ; + .dw 0x2B01 ; + .dw 0xECF6 ; + .dw 0x4C35 ; + .dw 0xECF7 ; + .dw 0x169B ; + .dw 0xECF8 ; + .dw 0x4C79 ; + .dw 0xECF9 ; + .dw 0xD85F ; + .dw 0xECFA ; + .dw 0x28CD ; + .dw 0xECFB ; + .dw 0x447 ; + .dw 0xECFC ; + .dw 0xF65 ; + .dw 0xECFD ; + .dw 0x6565 ; + .dw 0xECFE ; + .dw 0x99FF ; + .dw 0xECFF ; + .dw 0x6D95 ; + .dw 0xED00 ; + .dw 0x2A15 ; + .dw 0xED01 ; + .dw 0xABD3 ; + .dw 0xED02 ; + .dw 0x5373 ; + .dw 0xED03 ; + .dw 0x5EB1 ; + .dw 0xED04 ; + .dw 0x3145 ; + .dw 0xED05 ; + .dw 0xE853 ; + .dw 0xED06 ; + .dw 0x3AF3 ; + .dw 0xED07 ; + .dw 0xE477 ; + .dw 0xED08 ; + .dw 0x43BB ; + .dw 0xED09 ; + .dw 0xC8DF ; + .dw 0xED0A ; + .dw 0x218F ; + .dw 0xED0B ; + .dw 0x2BA1 ; + .dw 0xED0C ; + .dw 0x6515 ; + .dw 0xED0D ; + .dw 0xEAC1 ; + .dw 0xED0E ; + .dw 0xF631 ; + .dw 0xED0F ; + .dw 0x5B8B ; + .dw 0xED10 ; + .dw 0xAE2B ; + .dw 0xED11 ; + .dw 0x4011 ; + .dw 0xED12 ; + .dw 0x89B3 ; + .dw 0xED13 ; + .dw 0x645F ; + .dw 0xED14 ; + .dw 0x2AE1 ; + .dw 0xED15 ; + .dw 0x549F ; + .dw 0xED16 ; + .dw 0x7C77 ; + .dw 0xED17 ; + .dw 0x78D5 ; + .dw 0xED18 ; + .dw 0xBD7F ; + .dw 0xED19 ; + .dw 0xEA75 ; + .dw 0xED1A ; + .dw 0x6D83 ; + .dw 0xED1B ; + .dw 0x6B69 ; + .dw 0xED1C ; + .dw 0xDF8D ; + .dw 0xED1D ; + .dw 0xE5CF ; + .dw 0xED1E ; + .dw 0x317 ; + .dw 0xED1F ; + .dw 0xA713 ; + .dw 0xED20 ; + .dw 0x9825 ; + .dw 0xED21 ; + .dw 0x8F ; + .dw 0xED22 ; + .dw 0xE4C1 ; + .dw 0xED23 ; + .dw 0xFB79 ; + .dw 0xED24 ; + .dw 0x7FD5 ; + .dw 0xED25 ; + .dw 0x3D33 ; + .dw 0xED26 ; + .dw 0x3EFB ; + .dw 0xED27 ; + .dw 0xF4B5 ; + .dw 0xED28 ; + .dw 0x29EB ; + .dw 0xED29 ; + .dw 0x9155 ; + .dw 0xED2A ; + .dw 0xE83F ; + .dw 0xED2B ; + .dw 0xF67D ; + .dw 0xED2C ; + .dw 0xCB51 ; + .dw 0xED2D ; + .dw 0xBF9D ; + .dw 0xED2E ; + .dw 0xBFA5 ; + .dw 0xED2F ; + .dw 0xD2E9 ; + .dw 0xED30 ; + .dw 0x76EB ; + .dw 0xED31 ; + .dw 0xD939 ; + .dw 0xED32 ; + .dw 0x5CF1 ; + .dw 0xED33 ; + .dw 0x149F ; + .dw 0xED34 ; + .dw 0xC76B ; + .dw 0xED35 ; + .dw 0x5EDB ; + .dw 0xED36 ; + .dw 0xAA31 ; + .dw 0xED37 ; + .dw 0xB491 ; + .dw 0xED38 ; + .dw 0x4EA3 ; + .dw 0xED39 ; + .dw 0x7929 ; + .dw 0xED3A ; + .dw 0x7ED9 ; + .dw 0xED3B ; + .dw 0x733B ; + .dw 0xED3C ; + .dw 0xA269 ; + .dw 0xED3D ; + .dw 0x40B5 ; + .dw 0xED3E ; + .dw 0xD453 ; + .dw 0xED3F ; + .dw 0x8D4D ; + .dw 0xED40 ; + .dw 0x5EE3 ; + .dw 0xED41 ; + .dw 0x8D81 ; + .dw 0xED42 ; + .dw 0xAC19 ; + .dw 0xED43 ; + .dw 0x3EB ; + .dw 0xED44 ; + .dw 0xF667 ; + .dw 0xED45 ; + .dw 0x45E9 ; + .dw 0xED46 ; + .dw 0x3F53 ; + .dw 0xED47 ; + .dw 0x306B ; + .dw 0xED48 ; + .dw 0xA6D1 ; + .dw 0xED49 ; + .dw 0xA51F ; + .dw 0xED4A ; + .dw 0x8FE7 ; + .dw 0xED4B ; + .dw 0xDB7F ; + .dw 0xED4C ; + .dw 0x6C5B ; + .dw 0xED4D ; + .dw 0x7129 ; + .dw 0xED4E ; + .dw 0xF315 ; + .dw 0xED4F ; + .dw 0x8FFB ; + .dw 0xED50 ; + .dw 0x49F1 ; + .dw 0xED51 ; + .dw 0x9853 ; + .dw 0xED52 ; + .dw 0xAD8F ; + .dw 0xED53 ; + .dw 0x60FF ; + .dw 0xED54 ; + .dw 0xBF0F ; + .dw 0xED55 ; + .dw 0x2E27 ; + .dw 0xED56 ; + .dw 0x3913 ; + .dw 0xED57 ; + .dw 0xDBBF ; + .dw 0xED58 ; + .dw 0xC319 ; + .dw 0xED59 ; + .dw 0x3FE7 ; + .dw 0xED5A ; + .dw 0x4B7D ; + .dw 0xED5B ; + .dw 0x5CAB ; + .dw 0xED5C ; + .dw 0x1E2B ; + .dw 0xED5D ; + .dw 0x7885 ; + .dw 0xED5E ; + .dw 0x3761 ; + .dw 0xED5F ; + .dw 0x8033 ; + .dw 0xED60 ; + .dw 0x777B ; + .dw 0xED61 ; + .dw 0xC1B ; + .dw 0xED62 ; + .dw 0xBE2B ; + .dw 0xED63 ; + .dw 0xE6F9 ; + .dw 0xED64 ; + .dw 0xF12B ; + .dw 0xED65 ; + .dw 0xE2E3 ; + .dw 0xED66 ; + .dw 0xEBAB ; + .dw 0xED67 ; + .dw 0x58B ; + .dw 0xED68 ; + .dw 0xA99F ; + .dw 0xED69 ; + .dw 0x7BAD ; + .dw 0xED6A ; + .dw 0x1333 ; + .dw 0xED6B ; + .dw 0x3799 ; + .dw 0xED6C ; + .dw 0xFA61 ; + .dw 0xED6D ; + .dw 0x7DD7 ; + .dw 0xED6E ; + .dw 0x8631 ; + .dw 0xED6F ; + .dw 0xCEB1 ; + .dw 0xED70 ; + .dw 0xCC69 ; + .dw 0xED71 ; + .dw 0x72CB ; + .dw 0xED72 ; + .dw 0x1C41 ; + .dw 0xED73 ; + .dw 0x5475 ; + .dw 0xED74 ; + .dw 0xD9FD ; + .dw 0xED75 ; + .dw 0x9EEF ; + .dw 0xED76 ; + .dw 0x24CF ; + .dw 0xED77 ; + .dw 0xB84D ; + .dw 0xED78 ; + .dw 0x360D ; + .dw 0xED79 ; + .dw 0x7221 ; + .dw 0xED7A ; + .dw 0xDA1F ; + .dw 0xED7B ; + .dw 0xA0A9 ; + .dw 0xED7C ; + .dw 0xF103 ; + .dw 0xED7D ; + .dw 0x87AF ; + .dw 0xED7E ; + .dw 0xEDF7 ; + .dw 0xED7F ; + .dw 0x97B7 ; + .dw 0xED80 ; + .dw 0x331F ; + .dw 0xED81 ; + .dw 0xADCF ; + .dw 0xED82 ; + .dw 0x47A9 ; + .dw 0xED83 ; + .dw 0x4B91 ; + .dw 0xED84 ; + .dw 0xA44F ; + .dw 0xED85 ; + .dw 0xEC95 ; + .dw 0xED86 ; + .dw 0x8BB3 ; + .dw 0xED87 ; + .dw 0x9A03 ; + .dw 0xED88 ; + .dw 0x7985 ; + .dw 0xED89 ; + .dw 0x46F ; + .dw 0xED8A ; + .dw 0x84D7 ; + .dw 0xED8B ; + .dw 0x9FB9 ; + .dw 0xED8C ; + .dw 0xFF95 ; + .dw 0xED8D ; + .dw 0x5C17 ; + .dw 0xED8E ; + .dw 0x6A9 ; + .dw 0xED8F ; + .dw 0x82FD ; + .dw 0xED90 ; + .dw 0xFB83 ; + .dw 0xED91 ; + .dw 0xD613 ; + .dw 0xED92 ; + .dw 0x61B7 ; + .dw 0xED93 ; + .dw 0x31EB ; + .dw 0xED94 ; + .dw 0xB865 ; + .dw 0xED95 ; + .dw 0x85A5 ; + .dw 0xED96 ; + .dw 0x111 ; + .dw 0xED97 ; + .dw 0xCC2B ; + .dw 0xED98 ; + .dw 0x1AB1 ; + .dw 0xED99 ; + .dw 0xBB47 ; + .dw 0xED9A ; + .dw 0x496F ; + .dw 0xED9B ; + .dw 0xF027 ; + .dw 0xED9C ; + .dw 0x911F ; + .dw 0xED9D ; + .dw 0x60A1 ; + .dw 0xED9E ; + .dw 0x51BF ; + .dw 0xED9F ; + .dw 0xA3C7 ; + .dw 0xEDA0 ; + .dw 0x3AFD ; + .dw 0xEDA1 ; + .dw 0x1C09 ; + .dw 0xEDA2 ; + .dw 0x8D41 ; + .dw 0xEDA3 ; + .dw 0x10A3 ; + .dw 0xEDA4 ; + .dw 0x1C05 ; + .dw 0xEDA5 ; + .dw 0x336D ; + .dw 0xEDA6 ; + .dw 0xFF1D ; + .dw 0xEDA7 ; + .dw 0xCBC3 ; + .dw 0xEDA8 ; + .dw 0xB5B3 ; + .dw 0xEDA9 ; + .dw 0xA6D5 ; + .dw 0xEDAA ; + .dw 0xF7F ; + .dw 0xEDAB ; + .dw 0xE0D1 ; + .dw 0xEDAC ; + .dw 0xDE27 ; + .dw 0xEDAD ; + .dw 0x7A5B ; + .dw 0xEDAE ; + .dw 0x9A2D ; + .dw 0xEDAF ; + .dw 0x58CF ; + .dw 0xEDB0 ; + .dw 0x2C73 ; + .dw 0xEDB1 ; + .dw 0xA79B ; + .dw 0xEDB2 ; + .dw 0x4E9D ; + .dw 0xEDB3 ; + .dw 0x7457 ; + .dw 0xEDB4 ; + .dw 0xD275 ; + .dw 0xEDB5 ; + .dw 0xAEB9 ; + .dw 0xEDB6 ; + .dw 0xF98D ; + .dw 0xEDB7 ; + .dw 0x514B ; + .dw 0xEDB8 ; + .dw 0x3C33 ; + .dw 0xEDB9 ; + .dw 0x3EC9 ; + .dw 0xEDBA ; + .dw 0xD01D ; + .dw 0xEDBB ; + .dw 0x3413 ; + .dw 0xEDBC ; + .dw 0x4CB1 ; + .dw 0xEDBD ; + .dw 0xEDCF ; + .dw 0xEDBE ; + .dw 0x546B ; + .dw 0xEDBF ; + .dw 0x2C53 ; + .dw 0xEDC0 ; + .dw 0x9047 ; + .dw 0xEDC1 ; + .dw 0x783B ; + .dw 0xEDC2 ; + .dw 0xEBA3 ; + .dw 0xEDC3 ; + .dw 0x4D21 ; + .dw 0xEDC4 ; + .dw 0x3C7B ; + .dw 0xEDC5 ; + .dw 0x7FD9 ; + .dw 0xEDC6 ; + .dw 0xBD97 ; + .dw 0xEDC7 ; + .dw 0x30BD ; + .dw 0xEDC8 ; + .dw 0x5557 ; + .dw 0xEDC9 ; + .dw 0x424F ; + .dw 0xEDCA ; + .dw 0xF5DF ; + .dw 0xEDCB ; + .dw 0xFFCF ; + .dw 0xEDCC ; + .dw 0xD047 ; + .dw 0xEDCD ; + .dw 0x3F0F ; + .dw 0xEDCE ; + .dw 0xFE6F ; + .dw 0xEDCF ; + .dw 0xB415 ; + .dw 0xEDD0 ; + .dw 0xC65 ; + .dw 0xEDD1 ; + .dw 0x44D5 ; + .dw 0xEDD2 ; + .dw 0xCBA5 ; + .dw 0xEDD3 ; + .dw 0xCEA3 ; + .dw 0xEDD4 ; + .dw 0x785F ; + .dw 0xEDD5 ; + .dw 0xDE9B ; + .dw 0xEDD6 ; + .dw 0xD1F1 ; + .dw 0xEDD7 ; + .dw 0x399B ; + .dw 0xEDD8 ; + .dw 0xBDC5 ; + .dw 0xEDD9 ; + .dw 0x9815 ; + .dw 0xEDDA ; + .dw 0xBCDB ; + .dw 0xEDDB ; + .dw 0x8D5F ; + .dw 0xEDDC ; + .dw 0x49E9 ; + .dw 0xEDDD ; + .dw 0x11A7 ; + .dw 0xEDDE ; + .dw 0x7FAD ; + .dw 0xEDDF ; + .dw 0x714F ; + .dw 0xEDE0 ; + .dw 0x8C2D ; + .dw 0xEDE1 ; + .dw 0x5BD5 ; + .dw 0xEDE2 ; + .dw 0xD77F ; + .dw 0xEDE3 ; + .dw 0x4FF9 ; + .dw 0xEDE4 ; + .dw 0xC1E3 ; + .dw 0xEDE5 ; + .dw 0x924D ; + .dw 0xEDE6 ; + .dw 0xD6D1 ; + .dw 0xEDE7 ; + .dw 0x16E1 ; + .dw 0xEDE8 ; + .dw 0xA7A3 ; + .dw 0xEDE9 ; + .dw 0x2E4D ; + .dw 0xEDEA ; + .dw 0x92A7 ; + .dw 0xEDEB ; + .dw 0x39A3 ; + .dw 0xEDEC ; + .dw 0xE823 ; + .dw 0xEDED ; + .dw 0x8A5 ; + .dw 0xEDEE ; + .dw 0x891D ; + .dw 0xEDEF ; + .dw 0xB0BF ; + .dw 0xEDF0 ; + .dw 0xA089 ; + .dw 0xEDF1 ; + .dw 0x832D ; + .dw 0xEDF2 ; + .dw 0xD981 ; + .dw 0xEDF3 ; + .dw 0x2BC3 ; + .dw 0xEDF4 ; + .dw 0xD251 ; + .dw 0xEDF5 ; + .dw 0xD1BB ; + .dw 0xEDF6 ; + .dw 0xE5ED ; + .dw 0xEDF7 ; + .dw 0x2F0D ; + .dw 0xEDF8 ; + .dw 0x1A97 ; + .dw 0xEDF9 ; + .dw 0xDA9F ; + .dw 0xEDFA ; + .dw 0x7657 ; + .dw 0xEDFB ; + .dw 0x54F9 ; + .dw 0xEDFC ; + .dw 0x86F7 ; + .dw 0xEDFD ; + .dw 0xA697 ; + .dw 0xEDFE ; + .dw 0xF533 ; + .dw 0xEDFF ; + .dw 0x6AA5 ; + .dw 0xEE00 ; + .dw 0xDFDF ; + .dw 0xEE01 ; + .dw 0xD847 ; + .dw 0xEE02 ; + .dw 0xDD85 ; + .dw 0xEE03 ; + .dw 0xA01D ; + .dw 0xEE04 ; + .dw 0x406D ; + .dw 0xEE05 ; + .dw 0x2335 ; + .dw 0xEE06 ; + .dw 0xF27B ; + .dw 0xEE07 ; + .dw 0x841D ; + .dw 0xEE08 ; + .dw 0x53C7 ; + .dw 0xEE09 ; + .dw 0x3A3D ; + .dw 0xEE0A ; + .dw 0x5883 ; + .dw 0xEE0B ; + .dw 0x33F ; + .dw 0xEE0C ; + .dw 0xFED ; + .dw 0xEE0D ; + .dw 0x2D8D ; + .dw 0xEE0E ; + .dw 0x27E7 ; + .dw 0xEE0F ; + .dw 0x22BF ; + .dw 0xEE10 ; + .dw 0x4613 ; + .dw 0xEE11 ; + .dw 0xB015 ; + .dw 0xEE12 ; + .dw 0x90DF ; + .dw 0xEE13 ; + .dw 0xAEA7 ; + .dw 0xEE14 ; + .dw 0xE07F ; + .dw 0xEE15 ; + .dw 0x3C89 ; + .dw 0xEE16 ; + .dw 0x2931 ; + .dw 0xEE17 ; + .dw 0x938F ; + .dw 0xEE18 ; + .dw 0x25D9 ; + .dw 0xEE19 ; + .dw 0x91D5 ; + .dw 0xEE1A ; + .dw 0x7B41 ; + .dw 0xEE1B ; + .dw 0x1BD3 ; + .dw 0xEE1C ; + .dw 0xDA09 ; + .dw 0xEE1D ; + .dw 0x7F11 ; + .dw 0xEE1E ; + .dw 0x6EAD ; + .dw 0xEE1F ; + .dw 0xC849 ; + .dw 0xEE20 ; + .dw 0x948B ; + .dw 0xEE21 ; + .dw 0x7701 ; + .dw 0xEE22 ; + .dw 0xA265 ; + .dw 0xEE23 ; + .dw 0xFC7B ; + .dw 0xEE24 ; + .dw 0x2449 ; + .dw 0xEE25 ; + .dw 0xE305 ; + .dw 0xEE26 ; + .dw 0x5045 ; + .dw 0xEE27 ; + .dw 0x3661 ; + .dw 0xEE28 ; + .dw 0x58F3 ; + .dw 0xEE29 ; + .dw 0xAD93 ; + .dw 0xEE2A ; + .dw 0xD225 ; + .dw 0xEE2B ; + .dw 0x991 ; + .dw 0xEE2C ; + .dw 0x9D3 ; + .dw 0xEE2D ; + .dw 0xFC35 ; + .dw 0xEE2E ; + .dw 0x607D ; + .dw 0xEE2F ; + .dw 0x9603 ; + .dw 0xEE30 ; + .dw 0xB22F ; + .dw 0xEE31 ; + .dw 0x90FD ; + .dw 0xEE32 ; + .dw 0x226F ; + .dw 0xEE33 ; + .dw 0xB23D ; + .dw 0xEE34 ; + .dw 0x7B15 ; + .dw 0xEE35 ; + .dw 0xCB75 ; + .dw 0xEE36 ; + .dw 0x276D ; + .dw 0xEE37 ; + .dw 0x8111 ; + .dw 0xEE38 ; + .dw 0xAB9 ; + .dw 0xEE39 ; + .dw 0xC127 ; + .dw 0xEE3A ; + .dw 0x6249 ; + .dw 0xEE3B ; + .dw 0xAADB ; + .dw 0xEE3C ; + .dw 0xF151 ; + .dw 0xEE3D ; + .dw 0x6587 ; + .dw 0xEE3E ; + .dw 0x3DCB ; + .dw 0xEE3F ; + .dw 0xF229 ; + .dw 0xEE40 ; + .dw 0xB63 ; + .dw 0xEE41 ; + .dw 0x3973 ; + .dw 0xEE42 ; + .dw 0xE2D1 ; + .dw 0xEE43 ; + .dw 0x5C05 ; + .dw 0xEE44 ; + .dw 0xB1A5 ; + .dw 0xEE45 ; + .dw 0x7A29 ; + .dw 0xEE46 ; + .dw 0xC7E1 ; + .dw 0xEE47 ; + .dw 0xA39F ; + .dw 0xEE48 ; + .dw 0xE55 ; + .dw 0xEE49 ; + .dw 0x47BD ; + .dw 0xEE4A ; + .dw 0xA23F ; + .dw 0xEE4B ; + .dw 0x318B ; + .dw 0xEE4C ; + .dw 0x7007 ; + .dw 0xEE4D ; + .dw 0xBB11 ; + .dw 0xEE4E ; + .dw 0x508F ; + .dw 0xEE4F ; + .dw 0x4E7B ; + .dw 0xEE50 ; + .dw 0xF20F ; + .dw 0xEE51 ; + .dw 0x6353 ; + .dw 0xEE52 ; + .dw 0xD6E1 ; + .dw 0xEE53 ; + .dw 0xC975 ; + .dw 0xEE54 ; + .dw 0x5243 ; + .dw 0xEE55 ; + .dw 0x22EF ; + .dw 0xEE56 ; + .dw 0x453 ; + .dw 0xEE57 ; + .dw 0xC985 ; + .dw 0xEE58 ; + .dw 0x4C69 ; + .dw 0xEE59 ; + .dw 0xE403 ; + .dw 0xEE5A ; + .dw 0xDA1F ; + .dw 0xEE5B ; + .dw 0x301 ; + .dw 0xEE5C ; + .dw 0x52FF ; + .dw 0xEE5D ; + .dw 0x1C65 ; + .dw 0xEE5E ; + .dw 0x4C3F ; + .dw 0xEE5F ; + .dw 0x837 ; + .dw 0xEE60 ; + .dw 0xFD97 ; + .dw 0xEE61 ; + .dw 0x990D ; + .dw 0xEE62 ; + .dw 0x7377 ; + .dw 0xEE63 ; + .dw 0xEDA9 ; + .dw 0xEE64 ; + .dw 0x4B3 ; + .dw 0xEE65 ; + .dw 0x8913 ; + .dw 0xEE66 ; + .dw 0xC8FB ; + .dw 0xEE67 ; + .dw 0xF9C5 ; + .dw 0xEE68 ; + .dw 0x231D ; + .dw 0xEE69 ; + .dw 0x4029 ; + .dw 0xEE6A ; + .dw 0x837F ; + .dw 0xEE6B ; + .dw 0x981B ; + .dw 0xEE6C ; + .dw 0xB4B9 ; + .dw 0xEE6D ; + .dw 0xA88F ; + .dw 0xEE6E ; + .dw 0xADCF ; + .dw 0xEE6F ; + .dw 0x4819 ; + .dw 0xEE70 ; + .dw 0x6AE1 ; + .dw 0xEE71 ; + .dw 0xDC8B ; + .dw 0xEE72 ; + .dw 0xEE7 ; + .dw 0xEE73 ; + .dw 0xBF41 ; + .dw 0xEE74 ; + .dw 0xEE3D ; + .dw 0xEE75 ; + .dw 0xDF65 ; + .dw 0xEE76 ; + .dw 0x7B91 ; + .dw 0xEE77 ; + .dw 0xF6DB ; + .dw 0xEE78 ; + .dw 0xC619 ; + .dw 0xEE79 ; + .dw 0xEDDD ; + .dw 0xEE7A ; + .dw 0xA975 ; + .dw 0xEE7B ; + .dw 0x5D37 ; + .dw 0xEE7C ; + .dw 0x5D41 ; + .dw 0xEE7D ; + .dw 0x5E1D ; + .dw 0xEE7E ; + .dw 0x1BB5 ; + .dw 0xEE7F ; + .dw 0xE261 ; + .dw 0xEE80 ; + .dw 0x7C55 ; + .dw 0xEE81 ; + .dw 0x873F ; + .dw 0xEE82 ; + .dw 0x4107 ; + .dw 0xEE83 ; + .dw 0x1859 ; + .dw 0xEE84 ; + .dw 0x11A3 ; + .dw 0xEE85 ; + .dw 0xA833 ; + .dw 0xEE86 ; + .dw 0x5B47 ; + .dw 0xEE87 ; + .dw 0x1EC5 ; + .dw 0xEE88 ; + .dw 0x9E7F ; + .dw 0xEE89 ; + .dw 0x464B ; + .dw 0xEE8A ; + .dw 0x4895 ; + .dw 0xEE8B ; + .dw 0x9233 ; + .dw 0xEE8C ; + .dw 0x2219 ; + .dw 0xEE8D ; + .dw 0xFB1F ; + .dw 0xEE8E ; + .dw 0xC5E9 ; + .dw 0xEE8F ; + .dw 0x36CD ; + .dw 0xEE90 ; + .dw 0xD9D7 ; + .dw 0xEE91 ; + .dw 0x2A13 ; + .dw 0xEE92 ; + .dw 0x432F ; + .dw 0xEE93 ; + .dw 0x968F ; + .dw 0xEE94 ; + .dw 0xAF2F ; + .dw 0xEE95 ; + .dw 0x954B ; + .dw 0xEE96 ; + .dw 0xE0D7 ; + .dw 0xEE97 ; + .dw 0x4B01 ; + .dw 0xEE98 ; + .dw 0xAAF7 ; + .dw 0xEE99 ; + .dw 0x4A21 ; + .dw 0xEE9A ; + .dw 0xAEF9 ; + .dw 0xEE9B ; + .dw 0x2A6B ; + .dw 0xEE9C ; + .dw 0x4649 ; + .dw 0xEE9D ; + .dw 0xDD1F ; + .dw 0xEE9E ; + .dw 0xC5E1 ; + .dw 0xEE9F ; + .dw 0x1099 ; + .dw 0xEEA0 ; + .dw 0xF0CF ; + .dw 0xEEA1 ; + .dw 0x6D77 ; + .dw 0xEEA2 ; + .dw 0x5031 ; + .dw 0xEEA3 ; + .dw 0x7B03 ; + .dw 0xEEA4 ; + .dw 0xA4A3 ; + .dw 0xEEA5 ; + .dw 0x67FB ; + .dw 0xEEA6 ; + .dw 0x1E73 ; + .dw 0xEEA7 ; + .dw 0xB08D ; + .dw 0xEEA8 ; + .dw 0xDFA7 ; + .dw 0xEEA9 ; + .dw 0x818F ; + .dw 0xEEAA ; + .dw 0xDC33 ; + .dw 0xEEAB ; + .dw 0xACC1 ; + .dw 0xEEAC ; + .dw 0xDA55 ; + .dw 0xEEAD ; + .dw 0xE12F ; + .dw 0xEEAE ; + .dw 0x7E91 ; + .dw 0xEEAF ; + .dw 0x8685 ; + .dw 0xEEB0 ; + .dw 0x5421 ; + .dw 0xEEB1 ; + .dw 0xF15B ; + .dw 0xEEB2 ; + .dw 0x467 ; + .dw 0xEEB3 ; + .dw 0x8A51 ; + .dw 0xEEB4 ; + .dw 0xCD49 ; + .dw 0xEEB5 ; + .dw 0xD10F ; + .dw 0xEEB6 ; + .dw 0x1FD5 ; + .dw 0xEEB7 ; + .dw 0xBFE7 ; + .dw 0xEEB8 ; + .dw 0x8635 ; + .dw 0xEEB9 ; + .dw 0xDC43 ; + .dw 0xEEBA ; + .dw 0xE159 ; + .dw 0xEEBB ; + .dw 0x138F ; + .dw 0xEEBC ; + .dw 0x1C45 ; + .dw 0xEEBD ; + .dw 0x43DB ; + .dw 0xEEBE ; + .dw 0xFC71 ; + .dw 0xEEBF ; + .dw 0xDACD ; + .dw 0xEEC0 ; + .dw 0x1C35 ; + .dw 0xEEC1 ; + .dw 0x2D29 ; + .dw 0xEEC2 ; + .dw 0xBDA7 ; + .dw 0xEEC3 ; + .dw 0xEC97 ; + .dw 0xEEC4 ; + .dw 0x61E7 ; + .dw 0xEEC5 ; + .dw 0x50D7 ; + .dw 0xEEC6 ; + .dw 0x4A31 ; + .dw 0xEEC7 ; + .dw 0x50D ; + .dw 0xEEC8 ; + .dw 0x9DC7 ; + .dw 0xEEC9 ; + .dw 0x9169 ; + .dw 0xEECA ; + .dw 0x4105 ; + .dw 0xEECB ; + .dw 0xACB5 ; + .dw 0xEECC ; + .dw 0xD79F ; + .dw 0xEECD ; + .dw 0x8133 ; + .dw 0xEECE ; + .dw 0x5575 ; + .dw 0xEECF ; + .dw 0x5B31 ; + .dw 0xEED0 ; + .dw 0x46EF ; + .dw 0xEED1 ; + .dw 0x4FD1 ; + .dw 0xEED2 ; + .dw 0xFB45 ; + .dw 0xEED3 ; + .dw 0xD75 ; + .dw 0xEED4 ; + .dw 0x58BF ; + .dw 0xEED5 ; + .dw 0x171F ; + .dw 0xEED6 ; + .dw 0xBC3B ; + .dw 0xEED7 ; + .dw 0x77F ; + .dw 0xEED8 ; + .dw 0x3B03 ; + .dw 0xEED9 ; + .dw 0xFFAF ; + .dw 0xEEDA ; + .dw 0x4F4B ; + .dw 0xEEDB ; + .dw 0xF991 ; + .dw 0xEEDC ; + .dw 0xC569 ; + .dw 0xEEDD ; + .dw 0x34C1 ; + .dw 0xEEDE ; + .dw 0x915 ; + .dw 0xEEDF ; + .dw 0x40EF ; + .dw 0xEEE0 ; + .dw 0x17B5 ; + .dw 0xEEE1 ; + .dw 0x1FC3 ; + .dw 0xEEE2 ; + .dw 0xBE17 ; + .dw 0xEEE3 ; + .dw 0x7C07 ; + .dw 0xEEE4 ; + .dw 0xC599 ; + .dw 0xEEE5 ; + .dw 0xE339 ; + .dw 0xEEE6 ; + .dw 0xAE2D ; + .dw 0xEEE7 ; + .dw 0x2A37 ; + .dw 0xEEE8 ; + .dw 0xE80D ; + .dw 0xEEE9 ; + .dw 0x8D45 ; + .dw 0xEEEA ; + .dw 0x91BF ; + .dw 0xEEEB ; + .dw 0x8F01 ; + .dw 0xEEEC ; + .dw 0xEC27 ; + .dw 0xEEED ; + .dw 0xF997 ; + .dw 0xEEEE ; + .dw 0x6047 ; + .dw 0xEEEF ; + .dw 0x90C3 ; + .dw 0xEEF0 ; + .dw 0x776F ; + .dw 0xEEF1 ; + .dw 0xDAE9 ; + .dw 0xEEF2 ; + .dw 0xE873 ; + .dw 0xEEF3 ; + .dw 0xCAEB ; + .dw 0xEEF4 ; + .dw 0x39BD ; + .dw 0xEEF5 ; + .dw 0xE3EF ; + .dw 0xEEF6 ; + .dw 0xD1BB ; + .dw 0xEEF7 ; + .dw 0x8BB7 ; + .dw 0xEEF8 ; + .dw 0x48F ; + .dw 0xEEF9 ; + .dw 0x87D7 ; + .dw 0xEEFA ; + .dw 0x1F79 ; + .dw 0xEEFB ; + .dw 0xF563 ; + .dw 0xEEFC ; + .dw 0xFFE1 ; + .dw 0xEEFD ; + .dw 0x4A41 ; + .dw 0xEEFE ; + .dw 0xCD7F ; + .dw 0xEEFF ; + .dw 0xFAED ; + .dw 0xEF00 ; + .dw 0x5481 ; + .dw 0xEF01 ; + .dw 0x16B3 ; + .dw 0xEF02 ; + .dw 0x9E2F ; + .dw 0xEF03 ; + .dw 0x7041 ; + .dw 0xEF04 ; + .dw 0x23EF ; + .dw 0xEF05 ; + .dw 0x9791 ; + .dw 0xEF06 ; + .dw 0xB21B ; + .dw 0xEF07 ; + .dw 0xE5F9 ; + .dw 0xEF08 ; + .dw 0x25AD ; + .dw 0xEF09 ; + .dw 0x495 ; + .dw 0xEF0A ; + .dw 0x10F ; + .dw 0xEF0B ; + .dw 0x8895 ; + .dw 0xEF0C ; + .dw 0xC21B ; + .dw 0xEF0D ; + .dw 0x60CF ; + .dw 0xEF0E ; + .dw 0x4CB3 ; + .dw 0xEF0F ; + .dw 0xBB29 ; + .dw 0xEF10 ; + .dw 0x2D3 ; + .dw 0xEF11 ; + .dw 0xA00F ; + .dw 0xEF12 ; + .dw 0xA4A3 ; + .dw 0xEF13 ; + .dw 0xA5A5 ; + .dw 0xEF14 ; + .dw 0x3075 ; + .dw 0xEF15 ; + .dw 0xABEB ; + .dw 0xEF16 ; + .dw 0x1403 ; + .dw 0xEF17 ; + .dw 0x6E7F ; + .dw 0xEF18 ; + .dw 0x760B ; + .dw 0xEF19 ; + .dw 0xC02B ; + .dw 0xEF1A ; + .dw 0x9095 ; + .dw 0xEF1B ; + .dw 0x57F3 ; + .dw 0xEF1C ; + .dw 0x61DD ; + .dw 0xEF1D ; + .dw 0x16CB ; + .dw 0xEF1E ; + .dw 0xC35B ; + .dw 0xEF1F ; + .dw 0x78B7 ; + .dw 0xEF20 ; + .dw 0x9BC9 ; + .dw 0xEF21 ; + .dw 0x5B6D ; + .dw 0xEF22 ; + .dw 0xC2A3 ; + .dw 0xEF23 ; + .dw 0x4837 ; + .dw 0xEF24 ; + .dw 0xA915 ; + .dw 0xEF25 ; + .dw 0xDE4D ; + .dw 0xEF26 ; + .dw 0x55A9 ; + .dw 0xEF27 ; + .dw 0xB645 ; + .dw 0xEF28 ; + .dw 0x15D3 ; + .dw 0xEF29 ; + .dw 0xFEC9 ; + .dw 0xEF2A ; + .dw 0xD9A5 ; + .dw 0xEF2B ; + .dw 0x65D ; + .dw 0xEF2C ; + .dw 0xDBAD ; + .dw 0xEF2D ; + .dw 0xC547 ; + .dw 0xEF2E ; + .dw 0x606D ; + .dw 0xEF2F ; + .dw 0x2655 ; + .dw 0xEF30 ; + .dw 0x5E49 ; + .dw 0xEF31 ; + .dw 0x24B7 ; + .dw 0xEF32 ; + .dw 0x2087 ; + .dw 0xEF33 ; + .dw 0xB893 ; + .dw 0xEF34 ; + .dw 0xD515 ; + .dw 0xEF35 ; + .dw 0xDB85 ; + .dw 0xEF36 ; + .dw 0xCEC3 ; + .dw 0xEF37 ; + .dw 0x89C9 ; + .dw 0xEF38 ; + .dw 0x7AA7 ; + .dw 0xEF39 ; + .dw 0x6C1D ; + .dw 0xEF3A ; + .dw 0xF951 ; + .dw 0xEF3B ; + .dw 0xAA33 ; + .dw 0xEF3C ; + .dw 0x5991 ; + .dw 0xEF3D ; + .dw 0x24CF ; + .dw 0xEF3E ; + .dw 0xFC5D ; + .dw 0xEF3F ; + .dw 0xE23F ; + .dw 0xEF40 ; + .dw 0xEBB ; + .dw 0xEF41 ; + .dw 0xAF5D ; + .dw 0xEF42 ; + .dw 0xA823 ; + .dw 0xEF43 ; + .dw 0xBAD7 ; + .dw 0xEF44 ; + .dw 0x593D ; + .dw 0xEF45 ; + .dw 0x1FE1 ; + .dw 0xEF46 ; + .dw 0x3087 ; + .dw 0xEF47 ; + .dw 0xD109 ; + .dw 0xEF48 ; + .dw 0xCFAF ; + .dw 0xEF49 ; + .dw 0xFB51 ; + .dw 0xEF4A ; + .dw 0x7E31 ; + .dw 0xEF4B ; + .dw 0xAD4F ; + .dw 0xEF4C ; + .dw 0x930D ; + .dw 0xEF4D ; + .dw 0x2D71 ; + .dw 0xEF4E ; + .dw 0x7923 ; + .dw 0xEF4F ; + .dw 0xD635 ; + .dw 0xEF50 ; + .dw 0x5703 ; + .dw 0xEF51 ; + .dw 0x664D ; + .dw 0xEF52 ; + .dw 0x64CD ; + .dw 0xEF53 ; + .dw 0x56A1 ; + .dw 0xEF54 ; + .dw 0x97CF ; + .dw 0xEF55 ; + .dw 0xD72F ; + .dw 0xEF56 ; + .dw 0xE5AB ; + .dw 0xEF57 ; + .dw 0x6F85 ; + .dw 0xEF58 ; + .dw 0x5591 ; + .dw 0xEF59 ; + .dw 0xC719 ; + .dw 0xEF5A ; + .dw 0xC85B ; + .dw 0xEF5B ; + .dw 0xAD11 ; + .dw 0xEF5C ; + .dw 0x2D29 ; + .dw 0xEF5D ; + .dw 0xF6BD ; + .dw 0xEF5E ; + .dw 0x2233 ; + .dw 0xEF5F ; + .dw 0x1773 ; + .dw 0xEF60 ; + .dw 0x2689 ; + .dw 0xEF61 ; + .dw 0x4BF5 ; + .dw 0xEF62 ; + .dw 0xE35B ; + .dw 0xEF63 ; + .dw 0xB711 ; + .dw 0xEF64 ; + .dw 0x1095 ; + .dw 0xEF65 ; + .dw 0xBCBB ; + .dw 0xEF66 ; + .dw 0x7265 ; + .dw 0xEF67 ; + .dw 0x2437 ; + .dw 0xEF68 ; + .dw 0xC273 ; + .dw 0xEF69 ; + .dw 0xF19F ; + .dw 0xEF6A ; + .dw 0x6963 ; + .dw 0xEF6B ; + .dw 0x5A55 ; + .dw 0xEF6C ; + .dw 0x1A6B ; + .dw 0xEF6D ; + .dw 0x97BF ; + .dw 0xEF6E ; + .dw 0xC85 ; + .dw 0xEF6F ; + .dw 0x86BB ; + .dw 0xEF70 ; + .dw 0x1231 ; + .dw 0xEF71 ; + .dw 0xDA43 ; + .dw 0xEF72 ; + .dw 0x9225 ; + .dw 0xEF73 ; + .dw 0xAC5 ; + .dw 0xEF74 ; + .dw 0xC0D3 ; + .dw 0xEF75 ; + .dw 0xFB55 ; + .dw 0xEF76 ; + .dw 0xD46B ; + .dw 0xEF77 ; + .dw 0x69A1 ; + .dw 0xEF78 ; + .dw 0xA1FD ; + .dw 0xEF79 ; + .dw 0x8491 ; + .dw 0xEF7A ; + .dw 0x8463 ; + .dw 0xEF7B ; + .dw 0x597D ; + .dw 0xEF7C ; + .dw 0xFAD7 ; + .dw 0xEF7D ; + .dw 0x705 ; + .dw 0xEF7E ; + .dw 0x768D ; + .dw 0xEF7F ; + .dw 0xB045 ; + .dw 0xEF80 ; + .dw 0xB463 ; + .dw 0xEF81 ; + .dw 0xE2A7 ; + .dw 0xEF82 ; + .dw 0x20FF ; + .dw 0xEF83 ; + .dw 0x63D7 ; + .dw 0xEF84 ; + .dw 0x834F ; + .dw 0xEF85 ; + .dw 0xD4B ; + .dw 0xEF86 ; + .dw 0xE2F3 ; + .dw 0xEF87 ; + .dw 0x55BD ; + .dw 0xEF88 ; + .dw 0xB54F ; + .dw 0xEF89 ; + .dw 0x511F ; + .dw 0xEF8A ; + .dw 0x2DED ; + .dw 0xEF8B ; + .dw 0x2265 ; + .dw 0xEF8C ; + .dw 0x7BF5 ; + .dw 0xEF8D ; + .dw 0xFA9D ; + .dw 0xEF8E ; + .dw 0x2843 ; + .dw 0xEF8F ; + .dw 0xABD5 ; + .dw 0xEF90 ; + .dw 0xD03 ; + .dw 0xEF91 ; + .dw 0x6E0B ; + .dw 0xEF92 ; + .dw 0xE13F ; + .dw 0xEF93 ; + .dw 0x97E9 ; + .dw 0xEF94 ; + .dw 0x7051 ; + .dw 0xEF95 ; + .dw 0x9C69 ; + .dw 0xEF96 ; + .dw 0xAEB5 ; + .dw 0xEF97 ; + .dw 0x7A0D ; + .dw 0xEF98 ; + .dw 0x5315 ; + .dw 0xEF99 ; + .dw 0xCFF5 ; + .dw 0xEF9A ; + .dw 0xCC19 ; + .dw 0xEF9B ; + .dw 0xE069 ; + .dw 0xEF9C ; + .dw 0xB8C9 ; + .dw 0xEF9D ; + .dw 0xC815 ; + .dw 0xEF9E ; + .dw 0xD31B ; + .dw 0xEF9F ; + .dw 0xFCA3 ; + .dw 0xEFA0 ; + .dw 0xE179 ; + .dw 0xEFA1 ; + .dw 0x9CDF ; + .dw 0xEFA2 ; + .dw 0x25BB ; + .dw 0xEFA3 ; + .dw 0x2019 ; + .dw 0xEFA4 ; + .dw 0x3D9B ; + .dw 0xEFA5 ; + .dw 0x61FF ; + .dw 0xEFA6 ; + .dw 0xE1E3 ; + .dw 0xEFA7 ; + .dw 0xC38D ; + .dw 0xEFA8 ; + .dw 0xC773 ; + .dw 0xEFA9 ; + .dw 0x141 ; + .dw 0xEFAA ; + .dw 0x767D ; + .dw 0xEFAB ; + .dw 0x5269 ; + .dw 0xEFAC ; + .dw 0x99DB ; + .dw 0xEFAD ; + .dw 0x447D ; + .dw 0xEFAE ; + .dw 0x720D ; + .dw 0xEFAF ; + .dw 0x7173 ; + .dw 0xEFB0 ; + .dw 0x1CA7 ; + .dw 0xEFB1 ; + .dw 0x8711 ; + .dw 0xEFB2 ; + .dw 0xA2CB ; + .dw 0xEFB3 ; + .dw 0xF903 ; + .dw 0xEFB4 ; + .dw 0x9E77 ; + .dw 0xEFB5 ; + .dw 0x6DB ; + .dw 0xEFB6 ; + .dw 0x2035 ; + .dw 0xEFB7 ; + .dw 0x5ABB ; + .dw 0xEFB8 ; + .dw 0xB40F ; + .dw 0xEFB9 ; + .dw 0x4CB5 ; + .dw 0xEFBA ; + .dw 0x562D ; + .dw 0xEFBB ; + .dw 0xAAC3 ; + .dw 0xEFBC ; + .dw 0x3531 ; + .dw 0xEFBD ; + .dw 0xA461 ; + .dw 0xEFBE ; + .dw 0xA98F ; + .dw 0xEFBF ; + .dw 0x47F ; + .dw 0xEFC0 ; + .dw 0x2EF9 ; + .dw 0xEFC1 ; + .dw 0x1C0F ; + .dw 0xEFC2 ; + .dw 0xCE43 ; + .dw 0xEFC3 ; + .dw 0x82C5 ; + .dw 0xEFC4 ; + .dw 0xA3A9 ; + .dw 0xEFC5 ; + .dw 0x34B ; + .dw 0xEFC6 ; + .dw 0x66E3 ; + .dw 0xEFC7 ; + .dw 0x8395 ; + .dw 0xEFC8 ; + .dw 0x700D ; + .dw 0xEFC9 ; + .dw 0x6179 ; + .dw 0xEFCA ; + .dw 0x5C3 ; + .dw 0xEFCB ; + .dw 0x6F55 ; + .dw 0xEFCC ; + .dw 0x2E51 ; + .dw 0xEFCD ; + .dw 0x5BCF ; + .dw 0xEFCE ; + .dw 0x2795 ; + .dw 0xEFCF ; + .dw 0xBB87 ; + .dw 0xEFD0 ; + .dw 0x6E4F ; + .dw 0xEFD1 ; + .dw 0x2C7 ; + .dw 0xEFD2 ; + .dw 0x3F7B ; + .dw 0xEFD3 ; + .dw 0x60FD ; + .dw 0xEFD4 ; + .dw 0x1B77 ; + .dw 0xEFD5 ; + .dw 0x7F1B ; + .dw 0xEFD6 ; + .dw 0x6C9F ; + .dw 0xEFD7 ; + .dw 0x7D99 ; + .dw 0xEFD8 ; + .dw 0x6817 ; + .dw 0xEFD9 ; + .dw 0x163F ; + .dw 0xEFDA ; + .dw 0xF151 ; + .dw 0xEFDB ; + .dw 0x597D ; + .dw 0xEFDC ; + .dw 0x163F ; + .dw 0xEFDD ; + .dw 0xFE55 ; + .dw 0xEFDE ; + .dw 0x395 ; + .dw 0xEFDF ; + .dw 0x87C7 ; + .dw 0xEFE0 ; + .dw 0x7615 ; + .dw 0xEFE1 ; + .dw 0x79A7 ; + .dw 0xEFE2 ; + .dw 0xF45 ; + .dw 0xEFE3 ; + .dw 0x5ACB ; + .dw 0xEFE4 ; + .dw 0xF1A7 ; + .dw 0xEFE5 ; + .dw 0x319B ; + .dw 0xEFE6 ; + .dw 0x1A3 ; + .dw 0xEFE7 ; + .dw 0x63C5 ; + .dw 0xEFE8 ; + .dw 0x7E4F ; + .dw 0xEFE9 ; + .dw 0x4935 ; + .dw 0xEFEA ; + .dw 0xB66F ; + .dw 0xEFEB ; + .dw 0x3617 ; + .dw 0xEFEC ; + .dw 0xCB83 ; + .dw 0xEFED ; + .dw 0x1F03 ; + .dw 0xEFEE ; + .dw 0x1E89 ; + .dw 0xEFEF ; + .dw 0x25FF ; + .dw 0xEFF0 ; + .dw 0x872B ; + .dw 0xEFF1 ; + .dw 0x369D ; + .dw 0xEFF2 ; + .dw 0x37FB ; + .dw 0xEFF3 ; + .dw 0x3ACB ; + .dw 0xEFF4 ; + .dw 0x8F81 ; + .dw 0xEFF5 ; + .dw 0x4199 ; + .dw 0xEFF6 ; + .dw 0x6FA1 ; + .dw 0xEFF7 ; + .dw 0xC99 ; + .dw 0xEFF8 ; + .dw 0x6A5F ; + .dw 0xEFF9 ; + .dw 0xC007 ; + .dw 0xEFFA ; + .dw 0x8433 ; + .dw 0xEFFB ; + .dw 0xC585 ; + .dw 0xEFFC ; + .dw 0xDA23 ; + .dw 0xEFFD ; + .dw 0x3065 ; + .dw 0xEFFE ; + .dw 0x82E1 ; + .dw 0xEFFF ; + .dw 0xFE6D ; + .dw 0xC700 ; + .dw 0xE7FB ; + .dw 0xC701 ; + .dw 0x4717 ; + .dw 0xC702 ; + .dw 0xF573 ; + .dw 0xC703 ; + .dw 0xAF1D ; + .dw 0xC704 ; + .dw 0x3BC7 ; + .dw 0xC705 ; + .dw 0x2563 ; + .dw 0xC706 ; + .dw 0xD9D3 ; + .dw 0xC707 ; + .dw 0xEA0F ; + .dw 0xC708 ; + .dw 0x1969 ; + .dw 0xC709 ; + .dw 0x7E5 ; + .dw 0xC70A ; + .dw 0x7B31 ; + .dw 0xC70B ; + .dw 0x9BA1 ; + .dw 0xC70C ; + .dw 0xDBA3 ; + .dw 0xC70D ; + .dw 0x6489 ; + .dw 0xC70E ; + .dw 0xC499 ; + .dw 0xC70F ; + .dw 0x4CD ; + .dw 0xC710 ; + .dw 0x446B ; + .dw 0xC711 ; + .dw 0xF003 ; + .dw 0xC712 ; + .dw 0x24FF ; + .dw 0xC713 ; + .dw 0x295D ; + .dw 0xC714 ; + .dw 0x7AC3 ; + .dw 0xC715 ; + .dw 0x82C5 ; + .dw 0xC716 ; + .dw 0x9CED ; + .dw 0xC717 ; + .dw 0xE9A9 ; + .dw 0xC718 ; + .dw 0xE15 ; + .dw 0xC719 ; + .dw 0x557B ; + .dw 0xC71A ; + .dw 0xD83 ; + .dw 0xC71B ; + .dw 0xFFCD ; + .dw 0xC71C ; + .dw 0xD70B ; + .dw 0xC71D ; + .dw 0x8CFD ; + .dw 0xC71E ; + .dw 0x6121 ; + .dw 0xC71F ; + .dw 0x985F ; + .dw 0xC720 ; + .dw 0xDDD ; + .dw 0xC721 ; + .dw 0x8DCF ; + .dw 0xC722 ; + .dw 0xA579 ; + .dw 0xC723 ; + .dw 0xBEA9 ; + .dw 0xC724 ; + .dw 0x6E39 ; + .dw 0xC725 ; + .dw 0xF0F ; + .dw 0xC726 ; + .dw 0xAF23 ; + .dw 0xC727 ; + .dw 0x5461 ; + .dw 0xC728 ; + .dw 0xC08B ; + .dw 0xC729 ; + .dw 0x64F9 ; + .dw 0xC72A ; + .dw 0x5EBB ; + .dw 0xC72B ; + .dw 0xCCE3 ; + .dw 0xC72C ; + .dw 0xA0E1 ; + .dw 0xC72D ; + .dw 0xFAD1 ; + .dw 0xC72E ; + .dw 0x1F75 ; + .dw 0xC72F ; + .dw 0x63DF ; + .dw 0xC730 ; + .dw 0xDB3D ; + .dw 0xC731 ; + .dw 0x7469 ; + .dw 0xC732 ; + .dw 0xB735 ; + .dw 0xC733 ; + .dw 0x7A1 ; + .dw 0xC734 ; + .dw 0x356F ; + .dw 0xC735 ; + .dw 0x6F0F ; + .dw 0xC736 ; + .dw 0x2F ; + .dw 0xC737 ; + .dw 0xAEB9 ; + .dw 0xC738 ; + .dw 0xFE6D ; + .dw 0xC739 ; + .dw 0x5A0B ; + .dw 0xC73A ; + .dw 0xA3F1 ; + .dw 0xC73B ; + .dw 0x5143 ; + .dw 0xC73C ; + .dw 0x3B29 ; + .dw 0xC73D ; + .dw 0x5E91 ; + .dw 0xC73E ; + .dw 0x7007 ; + .dw 0xC73F ; + .dw 0x3D8D ; + .dw 0xC740 ; + .dw 0xC8EB ; + .dw 0xC741 ; + .dw 0xCF3F ; + .dw 0xC742 ; + .dw 0x5C0B ; + .dw 0xC743 ; + .dw 0x61 ; + .dw 0xC744 ; + .dw 0x4D2B ; + .dw 0xC745 ; + .dw 0x1713 ; + .dw 0xC746 ; + .dw 0xD945 ; + .dw 0xC747 ; + .dw 0x98AD ; + .dw 0xC748 ; + .dw 0x4AE3 ; + .dw 0xC749 ; + .dw 0x9FDF ; + .dw 0xC74A ; + .dw 0x83BB ; + .dw 0xC74B ; + .dw 0x2EC9 ; + .dw 0xC74C ; + .dw 0x356B ; + .dw 0xC74D ; + .dw 0xA84B ; + .dw 0xC74E ; + .dw 0xCCCD ; + .dw 0xC74F ; + .dw 0x727 ; + .dw 0xC750 ; + .dw 0xD8D1 ; + .dw 0xC751 ; + .dw 0x813F ; + .dw 0xC752 ; + .dw 0xB74F ; + .dw 0xC753 ; + .dw 0xE887 ; + .dw 0xC754 ; + .dw 0xEFB3 ; + .dw 0xC755 ; + .dw 0x2AE7 ; + .dw 0xC756 ; + .dw 0x3D1B ; + .dw 0xC757 ; + .dw 0xADBB ; + .dw 0xC758 ; + .dw 0x3E93 ; + .dw 0xC759 ; + .dw 0xC925 ; + .dw 0xC75A ; + .dw 0x762D ; + .dw 0xC75B ; + .dw 0x3AD7 ; + .dw 0xC75C ; + .dw 0xCAB ; + .dw 0xC75D ; + .dw 0xE78D ; + .dw 0xC75E ; + .dw 0x193F ; + .dw 0xC75F ; + .dw 0x8DE9 ; + .dw 0xC760 ; + .dw 0x5255 ; + .dw 0xC761 ; + .dw 0x4D7 ; + .dw 0xC762 ; + .dw 0x6DD7 ; + .dw 0xC763 ; + .dw 0x2333 ; + .dw 0xC764 ; + .dw 0x74CF ; + .dw 0xC765 ; + .dw 0x5DDB ; + .dw 0xC766 ; + .dw 0x47E5 ; + .dw 0xC767 ; + .dw 0x64E1 ; + .dw 0xC768 ; + .dw 0xE7A1 ; + .dw 0xC769 ; + .dw 0x700B ; + .dw 0xC76A ; + .dw 0x24E1 ; + .dw 0xC76B ; + .dw 0x5E49 ; + .dw 0xC76C ; + .dw 0x8B73 ; + .dw 0xC76D ; + .dw 0x2B65 ; + .dw 0xC76E ; + .dw 0x253 ; + .dw 0xC76F ; + .dw 0x6A93 ; + .dw 0xC770 ; + .dw 0x225B ; + .dw 0xC771 ; + .dw 0x4BF5 ; + .dw 0xC772 ; + .dw 0x5F9 ; + .dw 0xC773 ; + .dw 0x1701 ; + .dw 0xC774 ; + .dw 0xB1C3 ; + .dw 0xC775 ; + .dw 0xD2BD ; + .dw 0xC776 ; + .dw 0x8F5D ; + .dw 0xC777 ; + .dw 0xF09F ; + .dw 0xC778 ; + .dw 0x29B7 ; + .dw 0xC779 ; + .dw 0x163D ; + .dw 0xC77A ; + .dw 0xCAE9 ; + .dw 0xC77B ; + .dw 0x757B ; + .dw 0xC77C ; + .dw 0x29C5 ; + .dw 0xC77D ; + .dw 0x6263 ; + .dw 0xC77E ; + .dw 0x5E7D ; + .dw 0xC77F ; + .dw 0xE161 ; + .dw 0xC780 ; + .dw 0x3B49 ; + .dw 0xC781 ; + .dw 0xA005 ; + .dw 0xC782 ; + .dw 0x478D ; + .dw 0xC783 ; + .dw 0xE0F ; + .dw 0xC784 ; + .dw 0x5955 ; + .dw 0xC785 ; + .dw 0xFBD9 ; + .dw 0xC786 ; + .dw 0x82B7 ; + .dw 0xC787 ; + .dw 0x1EEF ; + .dw 0xC788 ; + .dw 0x1DF9 ; + .dw 0xC789 ; + .dw 0x4E9 ; + .dw 0xC78A ; + .dw 0x94DD ; + .dw 0xC78B ; + .dw 0x304D ; + .dw 0xC78C ; + .dw 0x6D27 ; + .dw 0xC78D ; + .dw 0x3A93 ; + .dw 0xC78E ; + .dw 0x8DB3 ; + .dw 0xC78F ; + .dw 0xC213 ; + .dw 0xC790 ; + .dw 0xF507 ; + .dw 0xC791 ; + .dw 0x81F9 ; + .dw 0xC792 ; + .dw 0x9BE7 ; + .dw 0xC793 ; + .dw 0x15FD ; + .dw 0xC794 ; + .dw 0x5BCB ; + .dw 0xC795 ; + .dw 0x7AFF ; + .dw 0xC796 ; + .dw 0xCAA9 ; + .dw 0xC797 ; + .dw 0x3951 ; + .dw 0xC798 ; + .dw 0x730D ; + .dw 0xC799 ; + .dw 0x2CBF ; + .dw 0xC79A ; + .dw 0xD3 ; + .dw 0xC79B ; + .dw 0xF21D ; + .dw 0xC79C ; + .dw 0x48A3 ; + .dw 0xC79D ; + .dw 0x183 ; + .dw 0xC79E ; + .dw 0xD96D ; + .dw 0xC79F ; + .dw 0x47E7 ; + .dw 0xC7A0 ; + .dw 0x6CF9 ; + .dw 0xC7A1 ; + .dw 0x8A3D ; + .dw 0xC7A2 ; + .dw 0x6DDD ; + .dw 0xC7A3 ; + .dw 0xDFE7 ; + .dw 0xC7A4 ; + .dw 0x46EB ; + .dw 0xC7A5 ; + .dw 0x17D ; + .dw 0xC7A6 ; + .dw 0xA96B ; + .dw 0xC7A7 ; + .dw 0xE4C5 ; + .dw 0xC7A8 ; + .dw 0xCD17 ; + .dw 0xC7A9 ; + .dw 0x5ED ; + .dw 0xC7AA ; + .dw 0x3E5F ; + .dw 0xC7AB ; + .dw 0xB1C9 ; + .dw 0xC7AC ; + .dw 0x7CBB ; + .dw 0xC7AD ; + .dw 0x8443 ; + .dw 0xC7AE ; + .dw 0xD4A1 ; + .dw 0xC7AF ; + .dw 0xF999 ; + .dw 0xC7B0 ; + .dw 0xE607 ; + .dw 0xC7B1 ; + .dw 0x48BF ; + .dw 0xC7B2 ; + .dw 0x89C7 ; + .dw 0xC7B3 ; + .dw 0xA06D ; + .dw 0xC7B4 ; + .dw 0xA5FD ; + .dw 0xC7B5 ; + .dw 0x3021 ; + .dw 0xC7B6 ; + .dw 0x5AAF ; + .dw 0xC7B7 ; + .dw 0x1C7 ; + .dw 0xC7B8 ; + .dw 0x25C1 ; + .dw 0xC7B9 ; + .dw 0x701F ; + .dw 0xC7BA ; + .dw 0x8E99 ; + .dw 0xC7BB ; + .dw 0xD9AF ; + .dw 0xC7BC ; + .dw 0xF775 ; + .dw 0xC7BD ; + .dw 0xEF5D ; + .dw 0xC7BE ; + .dw 0xBBC3 ; + .dw 0xC7BF ; + .dw 0x8969 ; + .dw 0xC7C0 ; + .dw 0x2895 ; + .dw 0xC7C1 ; + .dw 0x24ED ; + .dw 0xC7C2 ; + .dw 0x7D79 ; + .dw 0xC7C3 ; + .dw 0xEFA9 ; + .dw 0xC7C4 ; + .dw 0x61C3 ; + .dw 0xC7C5 ; + .dw 0x7737 ; + .dw 0xC7C6 ; + .dw 0x73AD ; + .dw 0xC7C7 ; + .dw 0x8C53 ; + .dw 0xC7C8 ; + .dw 0x2C2D ; + .dw 0xC7C9 ; + .dw 0x9283 ; + .dw 0xC7CA ; + .dw 0xA419 ; + .dw 0xC7CB ; + .dw 0x27AD ; + .dw 0xC7CC ; + .dw 0x345B ; + .dw 0xC7CD ; + .dw 0xAEE3 ; + .dw 0xC7CE ; + .dw 0xD4CB ; + .dw 0xC7CF ; + .dw 0xB513 ; + .dw 0xC7D0 ; + .dw 0xE289 ; + .dw 0xC7D1 ; + .dw 0x3DB5 ; + .dw 0xC7D2 ; + .dw 0xF849 ; + .dw 0xC7D3 ; + .dw 0xA93F ; + .dw 0xC7D4 ; + .dw 0x2087 ; + .dw 0xC7D5 ; + .dw 0xF68F ; + .dw 0xC7D6 ; + .dw 0x431B ; + .dw 0xC7D7 ; + .dw 0x7BEB ; + .dw 0xC7D8 ; + .dw 0xA503 ; + .dw 0xC7D9 ; + .dw 0xBBC9 ; + .dw 0xC7DA ; + .dw 0x2F1 ; + .dw 0xC7DB ; + .dw 0x8D1F ; + .dw 0xC7DC ; + .dw 0x9C6F ; + .dw 0xC7DD ; + .dw 0x4E61 ; + .dw 0xC7DE ; + .dw 0xCF2F ; + .dw 0xC7DF ; + .dw 0x25D7 ; + .dw 0xC7E0 ; + .dw 0x74B ; + .dw 0xC7E1 ; + .dw 0x4983 ; + .dw 0xC7E2 ; + .dw 0x2B0D ; + .dw 0xC7E3 ; + .dw 0xCC47 ; + .dw 0xC7E4 ; + .dw 0xA60D ; + .dw 0xC7E5 ; + .dw 0x5D77 ; + .dw 0xC7E6 ; + .dw 0x312F ; + .dw 0xC7E7 ; + .dw 0xA38B ; + .dw 0xC7E8 ; + .dw 0xCA6B ; + .dw 0xC7E9 ; + .dw 0x421D ; + .dw 0xC7EA ; + .dw 0x60B7 ; + .dw 0xC7EB ; + .dw 0xEE7 ; + .dw 0xC7EC ; + .dw 0xE637 ; + .dw 0xC7ED ; + .dw 0x58E7 ; + .dw 0xC7EE ; + .dw 0x23E1 ; + .dw 0xC7EF ; + .dw 0x5073 ; + .dw 0xC7F0 ; + .dw 0x2FC1 ; + .dw 0xC7F1 ; + .dw 0x7649 ; + .dw 0xC7F2 ; + .dw 0x281D ; + .dw 0xC7F3 ; + .dw 0x5B63 ; + .dw 0xC7F4 ; + .dw 0x339B ; + .dw 0xC7F5 ; + .dw 0xCABD ; + .dw 0xC7F6 ; + .dw 0x1FA1 ; + .dw 0xC7F7 ; + .dw 0x91B3 ; + .dw 0xC7F8 ; + .dw 0xAC07 ; + .dw 0xC7F9 ; + .dw 0x632F ; + .dw 0xC7FA ; + .dw 0x485 ; + .dw 0xC7FB ; + .dw 0xA55F ; + .dw 0xC7FC ; + .dw 0x75BD ; + .dw 0xC7FD ; + .dw 0x38FF ; + .dw 0xC7FE ; + .dw 0x755D ; + .dw 0xC7FF ; + .dw 0x5523 ; + .dw 0xE0C0 ; + .dw 0x0000 ; + .dw 0xE0A0 ; + .dw 0x8000 ; + .dw 0xE1A0 ; + .dw 0x0 ; + .dw 0xC401 ; + .dw 0x4000 ; + .dw 0xC404 ; + .dw 0xC000 ; + .dw 0xC406 ; + .dw 0xC000 ; + .dw 0xC407 ; + .dw 0xC000 ; + .dw 0xC40A ; + .dw 0x8000 ; + .dw 0xC40A ; + .dw 0xC000 ; + .dw 0xC40C ; + .dw 0x8000 ; + .dw 0xC40E ; + .dw 0x8000 ; + .dw 0xC40F ; + .dw 0x0 ; + .dw 0xC40F ; + .dw 0x4000 ; + .dw 0xC40F ; + .dw 0x8000 ; + .dw 0xC410 ; + .dw 0x8000 ; + .dw 0xC411 ; + .dw 0x8000 ; + .dw 0xC411 ; + .dw 0xC000 ; + .dw 0xC412 ; + .dw 0x4000 ; + .dw 0xC412 ; + .dw 0x8000 ; + .dw 0xC413 ; + .dw 0x0 ; + .dw 0xC413 ; + .dw 0x4000 ; + .dw 0xC413 ; + .dw 0x8000 ; + .dw 0xC413 ; + .dw 0xC000 ; + .dw 0xC414 ; + .dw 0x8000 ; + .dw 0xC414 ; + .dw 0xC000 ; + .dw 0xC415 ; + .dw 0x8000 ; + .dw 0xC415 ; + .dw 0xC000 ; + .dw 0xC418 ; + .dw 0x8000 ; + .dw 0xC418 ; + .dw 0xC000 ; + .dw 0xC417 ; + .dw 0x4000 ; + .dw 0xC417 ; + .dw 0x8000 ; + .dw 0xC417 ; + .dw 0xC000 ; + .dw 0xC419 ; + .dw 0x0 ; + .dw 0xC419 ; + .dw 0x4000 ; + .dw 0xC419 ; + .dw 0x8000 ; + .dw 0xC419 ; + .dw 0xC000 ; + .dw 0xC41A ; + .dw 0x0 ; + .dw 0xC41A ; + .dw 0x4000 ; + .dw 0xC41A ; + .dw 0x8000 ; + .dw 0xC41A ; + .dw 0xC000 ; + .dw 0xC41B ; + .dw 0x0 ; + .dw 0xC41B ; + .dw 0x4000 ; + .dw 0xC41B ; + .dw 0x8000 ; + .dw 0xC41B ; + .dw 0xC000 ; + .dw 0xC41C ; + .dw 0x0 ; + .dw 0xC41C ; + .dw 0x4000 ; + .dw 0xC41C ; + .dw 0x8000 ; + .dw 0xC41C ; + .dw 0xC000 ; + .dw 0xC41D ; + .dw 0x0 ; + .dw 0xC41D ; + .dw 0x4000 ; + .dw 0xC41D ; + .dw 0x8000 ; + .dw 0xC41D ; + .dw 0xC000 ; + .dw 0xC41E ; + .dw 0x0 ; + .dw 0xC41E ; + .dw 0x4000 ; + .dw 0xC41E ; + .dw 0x8000 ; + .dw 0xC41E ; + .dw 0xC000 ; + .dw 0xC41F ; + .dw 0x0 ; + .dw 0xC41F ; + .dw 0x4000 ; + .dw 0xC41F ; + .dw 0x8000 ; + .dw 0xC41F ; + .dw 0xC000 ; + .dw 0xC401 ; + .dw 0x0 ; + .dw 0xC401 ; + .dw 0x240 ; + .dw 0xC401 ; + .dw 0x480 ; + .dw 0xC401 ; + .dw 0x6C0 ; + .dw 0xC401 ; + .dw 0x900 ; + .dw 0xC401 ; + .dw 0xB40 ; + .dw 0xC401 ; + .dw 0xD80 ; + .dw 0xC401 ; + .dw 0xFC0 ; + .dw 0xC401 ; + .dw 0x8000 ; + .dw 0xC401 ; + .dw 0x8240 ; + .dw 0xC401 ; + .dw 0x8480 ; + .dw 0xC401 ; + .dw 0x86C0 ; + .dw 0xC401 ; + .dw 0x8900 ; + .dw 0xC401 ; + .dw 0x8B40 ; + .dw 0xC401 ; + .dw 0x8D80 ; + .dw 0xC401 ; + .dw 0x8FC0 ; + .dw 0xC401 ; + .dw 0xC000 ; + .dw 0xC401 ; + .dw 0xC240 ; + .dw 0xC401 ; + .dw 0xC480 ; + .dw 0xC401 ; + .dw 0xC6C0 ; + .dw 0xC401 ; + .dw 0xC900 ; + .dw 0xC401 ; + .dw 0xCB40 ; + .dw 0xC401 ; + .dw 0xCD80 ; + .dw 0xC401 ; + .dw 0xCFC0 ; + .dw 0xC404 ; + .dw 0x8000 ; + .dw 0xC404 ; + .dw 0x8240 ; + .dw 0xC404 ; + .dw 0x8480 ; + .dw 0xC404 ; + .dw 0x86C0 ; + .dw 0xC404 ; + .dw 0x8900 ; + .dw 0xC404 ; + .dw 0x8B40 ; + .dw 0xC404 ; + .dw 0x8D80 ; + .dw 0xC404 ; + .dw 0x8FC0 ; + .dw 0xC40C ; + .dw 0x4000 ; + .dw 0xC40C ; + .dw 0x4240 ; + .dw 0xC40C ; + .dw 0x4480 ; + .dw 0xC40C ; + .dw 0x46C0 ; + .dw 0xC40C ; + .dw 0x4900 ; + .dw 0xC40C ; + .dw 0x4B40 ; + .dw 0xC40C ; + .dw 0x4D80 ; + .dw 0xC40C ; + .dw 0x4FC0 ; + .dw 0xC40D ; + .dw 0x0 ; + .dw 0xC40D ; + .dw 0x240 ; + .dw 0xC40D ; + .dw 0x480 ; + .dw 0xC40D ; + .dw 0x6C0 ; + .dw 0xC40D ; + .dw 0x900 ; + .dw 0xC40D ; + .dw 0xB40 ; + .dw 0xC40D ; + .dw 0xD80 ; + .dw 0xC40D ; + .dw 0xFC0 ; + .dw 0xC40D ; + .dw 0x4000 ; + .dw 0xC40D ; + .dw 0x4240 ; + .dw 0xC40D ; + .dw 0x4480 ; + .dw 0xC40D ; + .dw 0x46C0 ; + .dw 0xC40D ; + .dw 0x4900 ; + .dw 0xC40D ; + .dw 0x4B40 ; + .dw 0xC40D ; + .dw 0x4D80 ; + .dw 0xC40D ; + .dw 0x4FC0 ; + .dw 0xC40D ; + .dw 0x8000 ; + .dw 0xC40D ; + .dw 0x8240 ; + .dw 0xC40D ; + .dw 0x8480 ; + .dw 0xC40D ; + .dw 0x86C0 ; + .dw 0xC40D ; + .dw 0x8900 ; + .dw 0xC40D ; + .dw 0x8B40 ; + .dw 0xC40D ; + .dw 0x8D80 ; + .dw 0xC40D ; + .dw 0x8FC0 ; + .dw 0xC40D ; + .dw 0xC000 ; + .dw 0xC40D ; + .dw 0xC240 ; + .dw 0xC40D ; + .dw 0xC480 ; + .dw 0xC40D ; + .dw 0xC6C0 ; + .dw 0xC40D ; + .dw 0xC900 ; + .dw 0xC40D ; + .dw 0xCB40 ; + .dw 0xC40D ; + .dw 0xCD80 ; + .dw 0xC40D ; + .dw 0xCFC0 ; + .dw 0xC411 ; + .dw 0x0 ; + .dw 0xC411 ; + .dw 0x240 ; + .dw 0xC411 ; + .dw 0x480 ; + .dw 0xC411 ; + .dw 0x6C0 ; + .dw 0xC411 ; + .dw 0x900 ; + .dw 0xC411 ; + .dw 0xB40 ; + .dw 0xC411 ; + .dw 0xD80 ; + .dw 0xC411 ; + .dw 0xFC0 ; + .dw 0xC411 ; + .dw 0x4000 ; + .dw 0xC411 ; + .dw 0x4240 ; + .dw 0xC411 ; + .dw 0x4480 ; + .dw 0xC411 ; + .dw 0x46C0 ; + .dw 0xC411 ; + .dw 0x4900 ; + .dw 0xC411 ; + .dw 0x4B40 ; + .dw 0xC411 ; + .dw 0x4D80 ; + .dw 0xC411 ; + .dw 0x4FC0 ; + .dw 0xC415 ; + .dw 0x0 ; + .dw 0xC415 ; + .dw 0x240 ; + .dw 0xC415 ; + .dw 0x480 ; + .dw 0xC415 ; + .dw 0x6C0 ; + .dw 0xC415 ; + .dw 0x900 ; + .dw 0xC415 ; + .dw 0xB40 ; + .dw 0xC415 ; + .dw 0xD80 ; + .dw 0xC415 ; + .dw 0xFC0 ; + .dw 0xC415 ; + .dw 0x4000 ; + .dw 0xC415 ; + .dw 0x4240 ; + .dw 0xC415 ; + .dw 0x4480 ; + .dw 0xC415 ; + .dw 0x46C0 ; + .dw 0xC415 ; + .dw 0x4900 ; + .dw 0xC415 ; + .dw 0x4B40 ; + .dw 0xC415 ; + .dw 0x4D80 ; + .dw 0xC415 ; + .dw 0x4FC0 ; + .dw 0xC418 ; + .dw 0x4000 ; + .dw 0xC418 ; + .dw 0x4240 ; + .dw 0xC418 ; + .dw 0x4480 ; + .dw 0xC418 ; + .dw 0x46C0 ; + .dw 0xC418 ; + .dw 0x4900 ; + .dw 0xC418 ; + .dw 0x4B40 ; + .dw 0xC418 ; + .dw 0x4D80 ; + .dw 0xC418 ; + .dw 0x4FC0 ; + .dw 0xC412 ; + .dw 0x9 ; + .dw 0xC412 ; + .dw 0x1B ; + .dw 0xC412 ; + .dw 0x24 ; + .dw 0xC412 ; + .dw 0x2D ; + .dw 0xC412 ; + .dw 0x36 ; + .dw 0xC412 ; + .dw 0x3F ; + .dw 0xC414 ; + .dw 0x9 ; + .dw 0xC414 ; + .dw 0x1B ; + .dw 0xC414 ; + .dw 0x24 ; + .dw 0xC414 ; + .dw 0x2D ; + .dw 0xC414 ; + .dw 0x36 ; + .dw 0xC414 ; + .dw 0x3F ; + .dw 0xC414 ; + .dw 0x4009 ; + .dw 0xC414 ; + .dw 0x401B ; + .dw 0xC414 ; + .dw 0x4024 ; + .dw 0xC414 ; + .dw 0x402D ; + .dw 0xC414 ; + .dw 0x4036 ; + .dw 0xC414 ; + .dw 0x403F ; + .dw 0xC415 ; + .dw 0x9 ; + .dw 0xC415 ; + .dw 0x1B ; + .dw 0xC415 ; + .dw 0x24 ; + .dw 0xC415 ; + .dw 0x2D ; + .dw 0xC415 ; + .dw 0x36 ; + .dw 0xC415 ; + .dw 0x3F ; + .dw 0xC415 ; + .dw 0x4009 ; + .dw 0xC415 ; + .dw 0x401B ; + .dw 0xC415 ; + .dw 0x4024 ; + .dw 0xC415 ; + .dw 0x402D ; + .dw 0xC415 ; + .dw 0x4036 ; + .dw 0xC415 ; + .dw 0x403F ; + .dw 0xC416 ; + .dw 0x9 ; + .dw 0xC416 ; + .dw 0x1B ; + .dw 0xC416 ; + .dw 0x24 ; + .dw 0xC416 ; + .dw 0x2D ; + .dw 0xC416 ; + .dw 0x36 ; + .dw 0xC416 ; + .dw 0x3F ; + .dw 0xC416 ; + .dw 0x4009 ; + .dw 0xC416 ; + .dw 0x401B ; + .dw 0xC416 ; + .dw 0x4024 ; + .dw 0xC416 ; + .dw 0x402D ; + .dw 0xC416 ; + .dw 0x4036 ; + .dw 0xC416 ; + .dw 0x403F ; + .dw 0xC416 ; + .dw 0x8009 ; + .dw 0xC416 ; + .dw 0x801B ; + .dw 0xC416 ; + .dw 0x8024 ; + .dw 0xC416 ; + .dw 0x802D ; + .dw 0xC416 ; + .dw 0x8036 ; + .dw 0xC416 ; + .dw 0x803F ; + .dw 0xC416 ; + .dw 0xC009 ; + .dw 0xC416 ; + .dw 0xC01B ; + .dw 0xC416 ; + .dw 0xC024 ; + .dw 0xC416 ; + .dw 0xC02D ; + .dw 0xC416 ; + .dw 0xC036 ; + .dw 0xC416 ; + .dw 0xC03F ; + .dw 0xC417 ; + .dw 0x9 ; + .dw 0xC417 ; + .dw 0x1B ; + .dw 0xC417 ; + .dw 0x24 ; + .dw 0xC417 ; + .dw 0x2D ; + .dw 0xC417 ; + .dw 0x36 ; + .dw 0xC417 ; + .dw 0x3F ; + .dw 0xC418 ; + .dw 0x4009 ; + .dw 0xC418 ; + .dw 0x401B ; + .dw 0xC418 ; + .dw 0x4024 ; + .dw 0xC418 ; + .dw 0x402D ; + .dw 0xC418 ; + .dw 0x4036 ; + .dw 0xC418 ; + .dw 0x403F ; + .dw 0xC600 ; + .dw 0xC000 ; + .dw 0xC601 ; + .dw 0xC000 ; + .dw 0xC603 ; + .dw 0xC000 ; + .dw 0xC605 ; + .dw 0xC000 ; + .dw 0xC608 ; + .dw 0xC000 ; + .dw 0xC60B ; + .dw 0xC000 ; + .dw 0xC60C ; + .dw 0xC000 ; + .dw 0xC60D ; + .dw 0xC000 ; + .dw 0xC606 ; + .dw 0x8000 ; + .dw 0xC608 ; + .dw 0x8000 ; + .dw 0xC60B ; + .dw 0x8000 ; + .dw 0xC60C ; + .dw 0x8000 ; + .dw 0xC60E ; + .dw 0x0 ; + .dw 0xC60E ; + .dw 0x4000 ; + .dw 0xC60E ; + .dw 0x8000 ; + .dw 0xC60E ; + .dw 0xC000 ; + .dw 0xC60F ; + .dw 0x0 ; + .dw 0xC60F ; + .dw 0x4000 ; + .dw 0xC60F ; + .dw 0x8000 ; + .dw 0xC60F ; + .dw 0xC000 ; + .dw 0xC610 ; + .dw 0x0 ; + .dw 0xC610 ; + .dw 0x4000 ; + .dw 0xC610 ; + .dw 0x8000 ; + .dw 0xC610 ; + .dw 0xC000 ; + .dw 0xC611 ; + .dw 0x0 ; + .dw 0xC611 ; + .dw 0x4000 ; + .dw 0xC611 ; + .dw 0x8000 ; + .dw 0xC611 ; + .dw 0xC000 ; + .dw 0xC612 ; + .dw 0x0 ; + .dw 0xC612 ; + .dw 0x4000 ; + .dw 0xC612 ; + .dw 0x8000 ; + .dw 0xC612 ; + .dw 0xC000 ; + .dw 0xC613 ; + .dw 0x0 ; + .dw 0xC613 ; + .dw 0x4000 ; + .dw 0xC613 ; + .dw 0x8000 ; + .dw 0xC613 ; + .dw 0xC000 ; + .dw 0xC614 ; + .dw 0x0 ; + .dw 0xC614 ; + .dw 0x4000 ; + .dw 0xC614 ; + .dw 0x8000 ; + .dw 0xC614 ; + .dw 0xC000 ; + .dw 0xC615 ; + .dw 0x0 ; + .dw 0xC615 ; + .dw 0x4000 ; + .dw 0xC615 ; + .dw 0x8000 ; + .dw 0xC615 ; + .dw 0xC000 ; + .dw 0xC616 ; + .dw 0x0 ; + .dw 0xC616 ; + .dw 0x4000 ; + .dw 0xC616 ; + .dw 0x8000 ; + .dw 0xC616 ; + .dw 0xC000 ; + .dw 0xC617 ; + .dw 0x0 ; + .dw 0xC617 ; + .dw 0x4000 ; + .dw 0xC617 ; + .dw 0x8000 ; + .dw 0xC617 ; + .dw 0xC000 ; + .dw 0xC618 ; + .dw 0x0 ; + .dw 0xC618 ; + .dw 0x4000 ; + .dw 0xC618 ; + .dw 0x8000 ; + .dw 0xC618 ; + .dw 0xC000 ; + .dw 0xC619 ; + .dw 0x0 ; + .dw 0xC619 ; + .dw 0x4000 ; + .dw 0xC619 ; + .dw 0x8000 ; + .dw 0xC619 ; + .dw 0xC000 ; + .dw 0xC61A ; + .dw 0x0 ; + .dw 0xC61A ; + .dw 0x4000 ; + .dw 0xC61A ; + .dw 0x8000 ; + .dw 0xC61A ; + .dw 0xC000 ; + .dw 0xC61B ; + .dw 0x0 ; + .dw 0xC61B ; + .dw 0x4000 ; + .dw 0xC61B ; + .dw 0x8000 ; + .dw 0xC61B ; + .dw 0xC000 ; + .dw 0xC61C ; + .dw 0x0 ; + .dw 0xC61C ; + .dw 0x4000 ; + .dw 0xC61C ; + .dw 0x8000 ; + .dw 0xC61C ; + .dw 0xC000 ; + .dw 0xC61D ; + .dw 0x0 ; + .dw 0xC61D ; + .dw 0x4000 ; + .dw 0xC61D ; + .dw 0x8000 ; + .dw 0xC61D ; + .dw 0xC000 ; + .dw 0xC61E ; + .dw 0x0 ; + .dw 0xC61E ; + .dw 0x4000 ; + .dw 0xC61E ; + .dw 0x8000 ; + .dw 0xC61E ; + .dw 0xC000 ; + .dw 0xC61F ; + .dw 0x0 ; + .dw 0xC61F ; + .dw 0x4000 ; + .dw 0xC61F ; + .dw 0x8000 ; + .dw 0xC61F ; + .dw 0xC000 ; + .dw 0xC608 ; + .dw 0x0 ; + .dw 0xC608 ; + .dw 0x9 ; + .dw 0xC608 ; + .dw 0x12 ; + .dw 0xC608 ; + .dw 0x1B ; + .dw 0xC608 ; + .dw 0x24 ; + .dw 0xC608 ; + .dw 0x2D ; + .dw 0xC608 ; + .dw 0x36 ; + .dw 0xC608 ; + .dw 0x3F ; + .dw 0xC608 ; + .dw 0x4000 ; + .dw 0xC608 ; + .dw 0x4009 ; + .dw 0xC608 ; + .dw 0x4012 ; + .dw 0xC608 ; + .dw 0x401B ; + .dw 0xC608 ; + .dw 0x4024 ; + .dw 0xC608 ; + .dw 0x402D ; + .dw 0xC608 ; + .dw 0x4036 ; + .dw 0xC608 ; + .dw 0x403F ; + .dw 0xC680 ; + .dw 0xC000 ; + .dw 0xC681 ; + .dw 0xC000 ; + .dw 0xC683 ; + .dw 0xC000 ; + .dw 0xC684 ; + .dw 0x0 ; + .dw 0xC684 ; + .dw 0x4000 ; + .dw 0xC684 ; + .dw 0x8000 ; + .dw 0xC684 ; + .dw 0xC000 ; + .dw 0xC685 ; + .dw 0x0 ; + .dw 0xC685 ; + .dw 0x4000 ; + .dw 0xC685 ; + .dw 0x8000 ; + .dw 0xC685 ; + .dw 0xC000 ; + .dw 0xC686 ; + .dw 0x0 ; + .dw 0xC686 ; + .dw 0x4000 ; + .dw 0xC686 ; + .dw 0x8000 ; + .dw 0xC686 ; + .dw 0xC000 ; + .dw 0xC687 ; + .dw 0x0 ; + .dw 0xC687 ; + .dw 0x4000 ; + .dw 0xC687 ; + .dw 0x8000 ; + .dw 0xC687 ; + .dw 0xC000 ; + .dw 0xC688 ; + .dw 0x0 ; + .dw 0xC688 ; + .dw 0x4000 ; + .dw 0xC688 ; + .dw 0x8000 ; + .dw 0xC688 ; + .dw 0xC000 ; + .dw 0xC689 ; + .dw 0x0 ; + .dw 0xC689 ; + .dw 0x4000 ; + .dw 0xC689 ; + .dw 0x8000 ; + .dw 0xC689 ; + .dw 0xC000 ; + .dw 0xC68A ; + .dw 0x0 ; + .dw 0xC68A ; + .dw 0x4000 ; + .dw 0xC68A ; + .dw 0x8000 ; + .dw 0xC68A ; + .dw 0xC000 ; + .dw 0xC68B ; + .dw 0x0 ; + .dw 0xC68B ; + .dw 0x4000 ; + .dw 0xC68B ; + .dw 0x8000 ; + .dw 0xC68B ; + .dw 0xC000 ; + .dw 0xC68C ; + .dw 0x0 ; + .dw 0xC68C ; + .dw 0x4000 ; + .dw 0xC68C ; + .dw 0x8000 ; + .dw 0xC68C ; + .dw 0xC000 ; + .dw 0xC68D ; + .dw 0x0 ; + .dw 0xC68D ; + .dw 0x4000 ; + .dw 0xC68D ; + .dw 0x8000 ; + .dw 0xC68D ; + .dw 0xC000 ; + .dw 0xC68E ; + .dw 0x0 ; + .dw 0xC68E ; + .dw 0x4000 ; + .dw 0xC68E ; + .dw 0x8000 ; + .dw 0xC68E ; + .dw 0xC000 ; + .dw 0xC68F ; + .dw 0x0 ; + .dw 0xC68F ; + .dw 0x4000 ; + .dw 0xC68F ; + .dw 0x8000 ; + .dw 0xC68F ; + .dw 0xC000 ; + .dw 0xC690 ; + .dw 0x0 ; + .dw 0xC690 ; + .dw 0x4000 ; + .dw 0xC690 ; + .dw 0x8000 ; + .dw 0xC690 ; + .dw 0xC000 ; + .dw 0xC691 ; + .dw 0x0 ; + .dw 0xC691 ; + .dw 0x4000 ; + .dw 0xC691 ; + .dw 0x8000 ; + .dw 0xC691 ; + .dw 0xC000 ; + .dw 0xC692 ; + .dw 0x0 ; + .dw 0xC692 ; + .dw 0x4000 ; + .dw 0xC692 ; + .dw 0x8000 ; + .dw 0xC692 ; + .dw 0xC000 ; + .dw 0xC693 ; + .dw 0x0 ; + .dw 0xC693 ; + .dw 0x4000 ; + .dw 0xC693 ; + .dw 0x8000 ; + .dw 0xC693 ; + .dw 0xC000 ; + .dw 0xC694 ; + .dw 0x0 ; + .dw 0xC694 ; + .dw 0x4000 ; + .dw 0xC694 ; + .dw 0x8000 ; + .dw 0xC694 ; + .dw 0xC000 ; + .dw 0xC695 ; + .dw 0x0 ; + .dw 0xC695 ; + .dw 0x4000 ; + .dw 0xC695 ; + .dw 0x8000 ; + .dw 0xC695 ; + .dw 0xC000 ; + .dw 0xC696 ; + .dw 0x0 ; + .dw 0xC696 ; + .dw 0x4000 ; + .dw 0xC696 ; + .dw 0x8000 ; + .dw 0xC696 ; + .dw 0xC000 ; + .dw 0xC697 ; + .dw 0x0 ; + .dw 0xC697 ; + .dw 0x4000 ; + .dw 0xC697 ; + .dw 0x8000 ; + .dw 0xC697 ; + .dw 0xC000 ; + .dw 0xC698 ; + .dw 0x0 ; + .dw 0xC698 ; + .dw 0x4000 ; + .dw 0xC698 ; + .dw 0x8000 ; + .dw 0xC698 ; + .dw 0xC000 ; + .dw 0xC699 ; + .dw 0x0 ; + .dw 0xC699 ; + .dw 0x4000 ; + .dw 0xC699 ; + .dw 0x8000 ; + .dw 0xC699 ; + .dw 0xC000 ; + .dw 0xC69A ; + .dw 0x0 ; + .dw 0xC69A ; + .dw 0x4000 ; + .dw 0xC69A ; + .dw 0x8000 ; + .dw 0xC69A ; + .dw 0xC000 ; + .dw 0xC69B ; + .dw 0x0 ; + .dw 0xC69B ; + .dw 0x4000 ; + .dw 0xC69B ; + .dw 0x8000 ; + .dw 0xC69B ; + .dw 0xC000 ; + .dw 0xC69C ; + .dw 0x0 ; + .dw 0xC69C ; + .dw 0x4000 ; + .dw 0xC69C ; + .dw 0x8000 ; + .dw 0xC69C ; + .dw 0xC000 ; + .dw 0xC69D ; + .dw 0x0 ; + .dw 0xC69D ; + .dw 0x4000 ; + .dw 0xC69D ; + .dw 0x8000 ; + .dw 0xC69D ; + .dw 0xC000 ; + .dw 0xC69E ; + .dw 0x0 ; + .dw 0xC69E ; + .dw 0x4000 ; + .dw 0xC69E ; + .dw 0x8000 ; + .dw 0xC69E ; + .dw 0xC000 ; + .dw 0xC69F ; + .dw 0x0 ; + .dw 0xC69F ; + .dw 0x4000 ; + .dw 0xC69F ; + .dw 0x8000 ; + .dw 0xC69F ; + .dw 0xC000 ; + .dw 0xC008 ; + .dw 0x0 ; + .dw 0xC008 ; + .dw 0x40 ; + .dw 0xC008 ; + .dw 0xC0 ; + .dw 0xC008 ; + .dw 0x140 ; + .dw 0xC008 ; + .dw 0x1C0 ; + .dw 0xC020 ; + .dw 0x0 ; + .dw 0xC040 ; + .dw 0x0 ; + .dw 0xC0A0 ; + .dw 0x0 ; + .dw 0xC0C0 ; + .dw 0x0 ; + .dw 0xC0E0 ; + .dw 0x0 ; + .dw 0xC120 ; + .dw 0x0 ; + .dw 0xC140 ; + .dw 0x0 ; + .dw 0xC160 ; + .dw 0x0 ; + .dw 0xC180 ; + .dw 0x0 ; + .dw 0xC1A0 ; + .dw 0x0 ; + .dw 0xC1C0 ; + .dw 0x0 ; + .dw 0xC1E0 ; + .dw 0x0 ; + .dw 0xC060 ; + .dw 0x2000 ; + .dw 0xC0E0 ; + .dw 0x2000 ; + .dw 0xC140 ; + .dw 0x2000 ; + .dw 0xC1A0 ; + .dw 0x2000 ; + .dw 0xC1C0 ; + .dw 0x2000 ; + .dw 0xC1E0 ; + .dw 0x2000 ; + .dw 0xC064 ; + .dw 0x0 ; + .dw 0xC0E4 ; + .dw 0x0 ; + .dw 0xC144 ; + .dw 0x0 ; + .dw 0xC1A4 ; + .dw 0x0 ; + .dw 0xC1C4 ; + .dw 0x0 ; + .dw 0xC1E4 ; + .dw 0x0 ; + .dw 0xC064 ; + .dw 0x2000 ; + .dw 0xC0E4 ; + .dw 0x2000 ; + .dw 0xC144 ; + .dw 0x2000 ; + .dw 0xC1A4 ; + .dw 0x2000 ; + .dw 0xC1C4 ; + .dw 0x2000 ; + .dw 0xC1E4 ; + .dw 0x2000 ; + .dw 0xC048 ; + .dw 0x2000 ; + .dw 0xC068 ; + .dw 0x2000 ; + .dw 0xC0A8 ; + .dw 0x2000 ; + .dw 0xC0C8 ; + .dw 0x2000 ; + .dw 0xC0E8 ; + .dw 0x2000 ; + .dw 0xC148 ; + .dw 0x2000 ; + .dw 0xC168 ; + .dw 0x2000 ; + .dw 0xC188 ; + .dw 0x2000 ; + .dw 0xC1A8 ; + .dw 0x2000 ; + .dw 0xC1C8 ; + .dw 0x2000 ; + .dw 0xC1E8 ; + .dw 0x2000 ; + .dw 0xC04C ; + .dw 0x0 ; + .dw 0xC06C ; + .dw 0x0 ; + .dw 0xC0AC ; + .dw 0x0 ; + .dw 0xC0CC ; + .dw 0x0 ; + .dw 0xC0EC ; + .dw 0x0 ; + .dw 0xC14C ; + .dw 0x0 ; + .dw 0xC16C ; + .dw 0x0 ; + .dw 0xC18C ; + .dw 0x0 ; + .dw 0xC1AC ; + .dw 0x0 ; + .dw 0xC1CC ; + .dw 0x0 ; + .dw 0xC1EC ; + .dw 0x0 ; + .dw 0xC04C ; + .dw 0x2000 ; + .dw 0xC06C ; + .dw 0x2000 ; + .dw 0xC0AC ; + .dw 0x2000 ; + .dw 0xC0CC ; + .dw 0x2000 ; + .dw 0xC0EC ; + .dw 0x2000 ; + .dw 0xC14C ; + .dw 0x2000 ; + .dw 0xC16C ; + .dw 0x2000 ; + .dw 0xC18C ; + .dw 0x2000 ; + .dw 0xC1AC ; + .dw 0x2000 ; + .dw 0xC1CC ; + .dw 0x2000 ; + .dw 0xC1EC ; + .dw 0x2000 ; + .dw 0xC20C ; + .dw 0x2040 ; + .dw 0xC20C ; + .dw 0x20C0 ; + .dw 0xC20C ; + .dw 0x2140 ; + .dw 0xC20C ; + .dw 0x21C0 ; + .dw 0xC248 ; + .dw 0x2000 ; + .dw 0xC268 ; + .dw 0x2000 ; + .dw 0xC2A8 ; + .dw 0x2000 ; + .dw 0xC2C8 ; + .dw 0x2000 ; + .dw 0xC2E8 ; + .dw 0x2000 ; + .dw 0xC348 ; + .dw 0x2000 ; + .dw 0xC368 ; + .dw 0x2000 ; + .dw 0xC388 ; + .dw 0x2000 ; + .dw 0xC3A8 ; + .dw 0x2000 ; + .dw 0xC3C8 ; + .dw 0x2000 ; + .dw 0xC3E8 ; + .dw 0x2000 ; + .dw 0xC24C ; + .dw 0x0 ; + .dw 0xC26C ; + .dw 0x0 ; + .dw 0xC2AC ; + .dw 0x0 ; + .dw 0xC2CC ; + .dw 0x0 ; + .dw 0xC2EC ; + .dw 0x0 ; + .dw 0xC34C ; + .dw 0x0 ; + .dw 0xC36C ; + .dw 0x0 ; + .dw 0xC38C ; + .dw 0x0 ; + .dw 0xC3AC ; + .dw 0x0 ; + .dw 0xC3CC ; + .dw 0x0 ; + .dw 0xC3EC ; + .dw 0x0 ; + .dw 0xC24C ; + .dw 0x2000 ; + .dw 0xC26C ; + .dw 0x2000 ; + .dw 0xC2AC ; + .dw 0x2000 ; + .dw 0xC2CC ; + .dw 0x2000 ; + .dw 0xC2EC ; + .dw 0x2000 ; + .dw 0xC34C ; + .dw 0x2000 ; + .dw 0xC36C ; + .dw 0x2000 ; + .dw 0xC38C ; + .dw 0x2000 ; + .dw 0xC3AC ; + .dw 0x2000 ; + .dw 0xC3CC ; + .dw 0x2000 ; + .dw 0xC3EC ; + .dw 0x2000 ; + .dw 0xC20D ; + .dw 0x2800 ; + .dw 0xC20E ; + .dw 0x2800 ; + .dw 0xC20F ; + .dw 0x2800 ; + .dw 0xC20D ; + .dw 0x3000 ; + .dw 0xC20E ; + .dw 0x3000 ; + .dw 0xC20F ; + .dw 0x3000 ; + .dw 0xC20D ; + .dw 0x3800 ; + .dw 0xC20E ; + .dw 0x3800 ; + .dw 0xC20F ; + .dw 0x3800 ; + .dw 0xC200 ; + .dw 0x0 ; + .dw 0xC264 ; + .dw 0x2000 ; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +CHECKREG(r5, 2871); // count of all 16 bit UI's. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 32 bit illegal opcode handler - skips bad instruction + + // handler MADE LEAN and destructive so test runs more quckly + // se_undefinedinstruction1.dsp tests using a "nice" handler + +// [--sp] = ASTAT; // save what we damage +// [--sp] = (r7 - r6); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + + // Also allow 0x22 for illegal instruction combinations (parallel) +R6 = 0x22; +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; + +dbg_fail; + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + R7 += 4; // skip offending 32 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: +// (r7 - r6) = [sp++]; +// ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_undefinedinstruction4.S b/sim/testsuite/bfin/se_undefinedinstruction4.S new file mode 100644 index 0000000..b212c37 --- /dev/null +++ b/sim/testsuite/bfin/se_undefinedinstruction4.S @@ -0,0 +1,1298 @@ +//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction4/se_undefinedinstruction4.dsp +// Description: 64 bit special cases Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + A0 = 0; // reset accumulators + A1 = 0; + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** +// Starting 64bit section COUNT = 6406 + .dw 0xCF00 ; + .dw 0xFA4D ; + .dw 0x4973 ; + .dw 0x434D ; + .dw 0xCF01 ; + .dw 0x3CAF ; + .dw 0xE7F7 ; + .dw 0xACAD ; + .dw 0xCF02 ; + .dw 0xC9A3 ; + .dw 0x705D ; + .dw 0x8EFF ; + .dw 0xCF03 ; + .dw 0x242D ; + .dw 0x26ED ; + .dw 0x1C67 ; + .dw 0xCF04 ; + .dw 0xBC83 ; + .dw 0x18BB ; + .dw 0xEF95 ; + .dw 0xCF05 ; + .dw 0xDFA7 ; + .dw 0x6AD9 ; + .dw 0x7FEF ; + .dw 0xCF06 ; + .dw 0x71F3 ; + .dw 0x19CB ; + .dw 0x1F69 ; + .dw 0xCF07 ; + .dw 0xA117 ; + .dw 0x23ED ; + .dw 0xE509 ; + .dw 0xCF08 ; + .dw 0x4DF9 ; + .dw 0x31C3 ; + .dw 0x5207 ; + .dw 0xCF09 ; + .dw 0xF35D ; + .dw 0x998F ; + .dw 0xC1A7 ; + .dw 0xCF0A ; + .dw 0xA7FF ; + .dw 0x73D ; + .dw 0x4ACB ; + .dw 0xCF0B ; + .dw 0xEE29 ; + .dw 0xAAE7 ; + .dw 0x3FD3 ; + .dw 0xCF0C ; + .dw 0xD3B5 ; + .dw 0x5549 ; + .dw 0xBCB7 ; + .dw 0xCF0D ; + .dw 0xF0B7 ; + .dw 0xB91B ; + .dw 0xC01F ; + .dw 0xCF0E ; + .dw 0xC169 ; + .dw 0x3D1F ; + .dw 0xB96B ; + .dw 0xCF0F ; + .dw 0x7CD3 ; + .dw 0xFD95 ; + .dw 0x2EA1 ; + .dw 0xCF10 ; + .dw 0x8907 ; + .dw 0x6013 ; + .dw 0x467D ; + .dw 0xCF11 ; + .dw 0x7F67 ; + .dw 0xFC1F ; + .dw 0x6611 ; + .dw 0xCF12 ; + .dw 0x1BB3 ; + .dw 0xCFE1 ; + .dw 0xF609 ; + .dw 0xCF13 ; + .dw 0x6AF1 ; + .dw 0xC229 ; + .dw 0x8009 ; + .dw 0xCF14 ; + .dw 0xF619 ; + .dw 0xF2C9 ; + .dw 0xF8C7 ; + .dw 0xCF15 ; + .dw 0xE413 ; + .dw 0x99F3 ; + .dw 0x7919 ; + .dw 0xCF16 ; + .dw 0x5E8B ; + .dw 0xCA1 ; + .dw 0xED71 ; + .dw 0xCF17 ; + .dw 0x3FBB ; + .dw 0x221B ; + .dw 0xDA89 ; + .dw 0xCF18 ; + .dw 0xDFED ; + .dw 0x1565 ; + .dw 0x12DB ; + .dw 0xCF19 ; + .dw 0x95FD ; + .dw 0xB71F ; + .dw 0xB9B ; + .dw 0xCF1A ; + .dw 0xAB8F ; + .dw 0xC14F ; + .dw 0xD777 ; + .dw 0xCF1B ; + .dw 0x9427 ; + .dw 0x2E69 ; + .dw 0x5F23 ; + .dw 0xCF1C ; + .dw 0xB9F1 ; + .dw 0xFE17 ; + .dw 0x6AA1 ; + .dw 0xCF1D ; + .dw 0x642B ; + .dw 0x676B ; + .dw 0xCA2B ; + .dw 0xCF1E ; + .dw 0x4399 ; + .dw 0x8C55 ; + .dw 0x5187 ; + .dw 0xCF1F ; + .dw 0xCED5 ; + .dw 0x9163 ; + .dw 0x4B95 ; + .dw 0xCF20 ; + .dw 0xE0F9 ; + .dw 0xA3AF ; + .dw 0x72EB ; + .dw 0xCF21 ; + .dw 0x120B ; + .dw 0x9161 ; + .dw 0x4C73 ; + .dw 0xCF22 ; + .dw 0xA97F ; + .dw 0x9BC3 ; + .dw 0xF2A9 ; + .dw 0xCF23 ; + .dw 0x9B6F ; + .dw 0x15F5 ; + .dw 0x83F3 ; + .dw 0xCF24 ; + .dw 0x67D3 ; + .dw 0x4385 ; + .dw 0xEF37 ; + .dw 0xCF25 ; + .dw 0xD3A3 ; + .dw 0xFB5B ; + .dw 0x119D ; + .dw 0xCF26 ; + .dw 0xCA67 ; + .dw 0xC3F5 ; + .dw 0x2109 ; + .dw 0xCF27 ; + .dw 0x459B ; + .dw 0xC69 ; + .dw 0x6BD3 ; + .dw 0xCF28 ; + .dw 0xBD4B ; + .dw 0x82E1 ; + .dw 0xDD07 ; + .dw 0xCF29 ; + .dw 0x9131 ; + .dw 0x4A0B ; + .dw 0x503B ; + .dw 0xCF2A ; + .dw 0x3383 ; + .dw 0x55B5 ; + .dw 0x7107 ; + .dw 0xCF2B ; + .dw 0x9F5D ; + .dw 0x14B3 ; + .dw 0xF6FF ; + .dw 0xCF2C ; + .dw 0xF3B1 ; + .dw 0x53DF ; + .dw 0x9A93 ; + .dw 0xCF2D ; + .dw 0x5A59 ; + .dw 0x3879 ; + .dw 0x41AD ; + .dw 0xCF2E ; + .dw 0xDD63 ; + .dw 0x9BEF ; + .dw 0x55B3 ; + .dw 0xCF2F ; + .dw 0x9B01 ; + .dw 0x563D ; + .dw 0x598B ; + .dw 0xCF30 ; + .dw 0xF1E3 ; + .dw 0x45E1 ; + .dw 0xD327 ; + .dw 0xCF31 ; + .dw 0xF0C7 ; + .dw 0xD19D ; + .dw 0x110D ; + .dw 0xCF32 ; + .dw 0x94B7 ; + .dw 0x68CF ; + .dw 0x6ADB ; + .dw 0xCF33 ; + .dw 0x4083 ; + .dw 0xAD23 ; + .dw 0x3F8B ; + .dw 0xCF34 ; + .dw 0x55D3 ; + .dw 0x6969 ; + .dw 0x38D9 ; + .dw 0xCF35 ; + .dw 0xD261 ; + .dw 0xF353 ; + .dw 0x1595 ; + .dw 0xCF36 ; + .dw 0x8897 ; + .dw 0x9A6D ; + .dw 0x2093 ; + .dw 0xCF37 ; + .dw 0x2673 ; + .dw 0xD509 ; + .dw 0xF435 ; + .dw 0xCF38 ; + .dw 0x5093 ; + .dw 0x6F8F ; + .dw 0x93D9 ; + .dw 0xCF39 ; + .dw 0xAAE1 ; + .dw 0xE2F1 ; + .dw 0x807F ; + .dw 0xCF3A ; + .dw 0x64D ; + .dw 0xFEF7 ; + .dw 0x103D ; + .dw 0xCF3B ; + .dw 0x1665 ; + .dw 0x1959 ; + .dw 0x608F ; + .dw 0xCF3C ; + .dw 0x43D9 ; + .dw 0x2CDD ; + .dw 0x2F3F ; + .dw 0xCF3D ; + .dw 0x950B ; + .dw 0x3B49 ; + .dw 0x2681 ; + .dw 0xCF3E ; + .dw 0xEA9D ; + .dw 0x8053 ; + .dw 0xC311 ; + .dw 0xCF3F ; + .dw 0x4D3 ; + .dw 0x9311 ; + .dw 0x498B ; + .dw 0xCF40 ; + .dw 0x6909 ; + .dw 0x27C3 ; + .dw 0x2B45 ; + .dw 0xCF41 ; + .dw 0x1347 ; + .dw 0xFC37 ; + .dw 0x8C9D ; + .dw 0xCF42 ; + .dw 0xD08F ; + .dw 0xFF4B ; + .dw 0x3223 ; + .dw 0xCF43 ; + .dw 0x485 ; + .dw 0x7C05 ; + .dw 0xB5BB ; + .dw 0xCF44 ; + .dw 0x49BB ; + .dw 0x5A71 ; + .dw 0xBD1B ; + .dw 0xCF45 ; + .dw 0x27D9 ; + .dw 0x39B ; + .dw 0xE099 ; + .dw 0xCF46 ; + .dw 0x85AF ; + .dw 0xC637 ; + .dw 0xC7EF ; + .dw 0xCF47 ; + .dw 0x5D7B ; + .dw 0x9FAF ; + .dw 0xE277 ; + .dw 0xCF48 ; + .dw 0x51C9 ; + .dw 0xD04B ; + .dw 0xE427 ; + .dw 0xCF49 ; + .dw 0x747B ; + .dw 0xB7F5 ; + .dw 0x4E5 ; + .dw 0xCF4A ; + .dw 0xCBDF ; + .dw 0xFB21 ; + .dw 0x2B5B ; + .dw 0xCF4B ; + .dw 0x6F59 ; + .dw 0x716D ; + .dw 0xB07B ; + .dw 0xCF4C ; + .dw 0x42CB ; + .dw 0x46CB ; + .dw 0x9CD5 ; + .dw 0xCF4D ; + .dw 0xC98B ; + .dw 0x2C5D ; + .dw 0x57FF ; + .dw 0xCF4E ; + .dw 0xF097 ; + .dw 0xF96D ; + .dw 0x9C45 ; + .dw 0xCF4F ; + .dw 0x8743 ; + .dw 0xD053 ; + .dw 0xF01F ; + .dw 0xCF50 ; + .dw 0xD12D ; + .dw 0x79ED ; + .dw 0x18D7 ; + .dw 0xCF51 ; + .dw 0xCB3 ; + .dw 0x860F ; + .dw 0x5F57 ; + .dw 0xCF52 ; + .dw 0x41B7 ; + .dw 0xFB03 ; + .dw 0x2985 ; + .dw 0xCF53 ; + .dw 0x514F ; + .dw 0x6F ; + .dw 0x74F1 ; + .dw 0xCF54 ; + .dw 0x32AF ; + .dw 0x4413 ; + .dw 0x4F1 ; + .dw 0xCF55 ; + .dw 0xDF13 ; + .dw 0xEB77 ; + .dw 0xFDC7 ; + .dw 0xCF56 ; + .dw 0xE7BF ; + .dw 0xF8FB ; + .dw 0x8881 ; + .dw 0xCF57 ; + .dw 0xD71 ; + .dw 0xE18B ; + .dw 0x58E1 ; + .dw 0xCF58 ; + .dw 0xE66B ; + .dw 0x396B ; + .dw 0x6441 ; + .dw 0xCF59 ; + .dw 0xEAE5 ; + .dw 0xC4B9 ; + .dw 0x5D65 ; + .dw 0xCF5A ; + .dw 0x2DA9 ; + .dw 0x2BBB ; + .dw 0xD621 ; + .dw 0xCF5B ; + .dw 0x2FD1 ; + .dw 0xEB81 ; + .dw 0x56F3 ; + .dw 0xCF5C ; + .dw 0x7E67 ; + .dw 0xE6E1 ; + .dw 0x907 ; + .dw 0xCF5D ; + .dw 0x40A3 ; + .dw 0x95B3 ; + .dw 0x3501 ; + .dw 0xCF5E ; + .dw 0xBE25 ; + .dw 0x12A5 ; + .dw 0x96D ; + .dw 0xCF5F ; + .dw 0x94C9 ; + .dw 0xF7F7 ; + .dw 0xA553 ; + .dw 0xCF60 ; + .dw 0xB291 ; + .dw 0x5C7D ; + .dw 0x32ED ; + .dw 0xCF61 ; + .dw 0xABB5 ; + .dw 0x3987 ; + .dw 0x90FB ; + .dw 0xCF62 ; + .dw 0xDE61 ; + .dw 0x6B43 ; + .dw 0x5F83 ; + .dw 0xCF63 ; + .dw 0xF03D ; + .dw 0x61AF ; + .dw 0x3713 ; + .dw 0xCF64 ; + .dw 0x854D ; + .dw 0x2B4B ; + .dw 0x5ACB ; + .dw 0xCF65 ; + .dw 0x669B ; + .dw 0xC7A9 ; + .dw 0xC7B5 ; + .dw 0xCF66 ; + .dw 0x2E5D ; + .dw 0xFFE5 ; + .dw 0x8929 ; + .dw 0xCF67 ; + .dw 0xA089 ; + .dw 0x8151 ; + .dw 0xCD41 ; + .dw 0xCF68 ; + .dw 0xC17F ; + .dw 0x7ECF ; + .dw 0xB3F9 ; + .dw 0xCF69 ; + .dw 0x1689 ; + .dw 0xEA61 ; + .dw 0xC17B ; + .dw 0xCF6A ; + .dw 0xF6A1 ; + .dw 0xB5D1 ; + .dw 0xE1D5 ; + .dw 0xCF6B ; + .dw 0x8CEB ; + .dw 0xFA5 ; + .dw 0xBF9B ; + .dw 0xCF6C ; + .dw 0x9A11 ; + .dw 0x79DB ; + .dw 0x6B09 ; + .dw 0xCF6D ; + .dw 0x769B ; + .dw 0xEED1 ; + .dw 0x3BE3 ; + .dw 0xCF6E ; + .dw 0x8B95 ; + .dw 0xC2E9 ; + .dw 0x782D ; + .dw 0xCF6F ; + .dw 0x3763 ; + .dw 0x756B ; + .dw 0xE4B1 ; + .dw 0xCF70 ; + .dw 0xB2F5 ; + .dw 0x7F09 ; + .dw 0x2A1B ; + .dw 0xCF71 ; + .dw 0x9A79 ; + .dw 0x5685 ; + .dw 0x30BF ; + .dw 0xCF72 ; + .dw 0xCE41 ; + .dw 0x72D1 ; + .dw 0x301B ; + .dw 0xCF73 ; + .dw 0xAA27 ; + .dw 0x909B ; + .dw 0x818D ; + .dw 0xCF74 ; + .dw 0x5BB9 ; + .dw 0x8C95 ; + .dw 0xEA9F ; + .dw 0xCF75 ; + .dw 0x3079 ; + .dw 0x3273 ; + .dw 0x87F ; + .dw 0xCF76 ; + .dw 0x5297 ; + .dw 0x639B ; + .dw 0xC64B ; + .dw 0xCF77 ; + .dw 0x6883 ; + .dw 0xF731 ; + .dw 0xA8DF ; + .dw 0xCF78 ; + .dw 0x4387 ; + .dw 0x53CB ; + .dw 0x9CA1 ; + .dw 0xCF79 ; + .dw 0xAB55 ; + .dw 0xF8B ; + .dw 0xC01D ; + .dw 0xCF7A ; + .dw 0x3335 ; + .dw 0xA1EB ; + .dw 0xFD35 ; + .dw 0xCF7B ; + .dw 0xB3D ; + .dw 0x3F6B ; + .dw 0xF1A1 ; + .dw 0xCF7C ; + .dw 0x6EA9 ; + .dw 0x33F3 ; + .dw 0xAB8B ; + .dw 0xCF7D ; + .dw 0xBB41 ; + .dw 0xBCB7 ; + .dw 0xAA7D ; + .dw 0xCF7E ; + .dw 0x1ABD ; + .dw 0x8C9F ; + .dw 0xBBA9 ; + .dw 0xCF7F ; + .dw 0xB089 ; + .dw 0x55A3 ; + .dw 0xED41 ; + .dw 0xCF80 ; + .dw 0xB59D ; + .dw 0xC0AD ; + .dw 0xE873 ; + .dw 0xCF81 ; + .dw 0xFEA7 ; + .dw 0xB265 ; + .dw 0xF55F ; + .dw 0xCF82 ; + .dw 0x8A87 ; + .dw 0xE7F9 ; + .dw 0x64D3 ; + .dw 0xCF83 ; + .dw 0xE769 ; + .dw 0x6783 ; + .dw 0x4547 ; + .dw 0xCF84 ; + .dw 0x9597 ; + .dw 0xFBE9 ; + .dw 0xE1DD ; + .dw 0xCF85 ; + .dw 0x5239 ; + .dw 0x6397 ; + .dw 0x99C1 ; + .dw 0xCF86 ; + .dw 0xE6FF ; + .dw 0x84B ; + .dw 0x31C7 ; + .dw 0xCF87 ; + .dw 0x3E93 ; + .dw 0x6CDD ; + .dw 0xE883 ; + .dw 0xCF88 ; + .dw 0x9A81 ; + .dw 0xEB3D ; + .dw 0x310B ; + .dw 0xCF89 ; + .dw 0xA8AF ; + .dw 0x405D ; + .dw 0xDFC7 ; + .dw 0xCF8A ; + .dw 0x515B ; + .dw 0x7C13 ; + .dw 0xD483 ; + .dw 0xCF8B ; + .dw 0x1EE3 ; + .dw 0xD5E9 ; + .dw 0x2FAD ; + .dw 0xCF8C ; + .dw 0x2A93 ; + .dw 0xB0E1 ; + .dw 0xC4C1 ; + .dw 0xCF8D ; + .dw 0xD1DD ; + .dw 0xB1E7 ; + .dw 0x1E29 ; + .dw 0xCF8E ; + .dw 0xD6ED ; + .dw 0x1DB1 ; + .dw 0x2C7F ; + .dw 0xCF8F ; + .dw 0x1935 ; + .dw 0x6711 ; + .dw 0x618D ; + .dw 0xCF90 ; + .dw 0xFB4D ; + .dw 0xD003 ; + .dw 0xB185 ; + .dw 0xCF91 ; + .dw 0x1969 ; + .dw 0xD80F ; + .dw 0xDD13 ; + .dw 0xCF92 ; + .dw 0xFDE7 ; + .dw 0xF487 ; + .dw 0x54AB ; + .dw 0xCF93 ; + .dw 0x4FDB ; + .dw 0xCA39 ; + .dw 0x7EAF ; + .dw 0xCF94 ; + .dw 0xF805 ; + .dw 0xC4BF ; + .dw 0x8F77 ; + .dw 0xCF95 ; + .dw 0x24E3 ; + .dw 0x5055 ; + .dw 0x491 ; + .dw 0xCF96 ; + .dw 0x37A9 ; + .dw 0xCD9D ; + .dw 0xD301 ; + .dw 0xCF97 ; + .dw 0x2379 ; + .dw 0xDD89 ; + .dw 0xBC7B ; + .dw 0xCF98 ; + .dw 0xE1F3 ; + .dw 0x977F ; + .dw 0xED8B ; + .dw 0xCF99 ; + .dw 0xF983 ; + .dw 0xCE75 ; + .dw 0x3E75 ; + .dw 0xCF9A ; + .dw 0x4081 ; + .dw 0xF3D5 ; + .dw 0x3185 ; + .dw 0xCF9B ; + .dw 0xCB77 ; + .dw 0x47AD ; + .dw 0x97E9 ; + .dw 0xCF9C ; + .dw 0x71AF ; + .dw 0x93E1 ; + .dw 0xE25B ; + .dw 0xCF9D ; + .dw 0x9139 ; + .dw 0xCE65 ; + .dw 0x33C3 ; + .dw 0xCF9E ; + .dw 0xF4F5 ; + .dw 0xEF8D ; + .dw 0xC8D5 ; + .dw 0xCF9F ; + .dw 0x1E1 ; + .dw 0x59A7 ; + .dw 0xE7A1 ; + .dw 0xCFA0 ; + .dw 0x4241 ; + .dw 0xCB25 ; + .dw 0x4265 ; + .dw 0xCFA1 ; + .dw 0xE769 ; + .dw 0x27E1 ; + .dw 0xCD97 ; + .dw 0xCFA2 ; + .dw 0xA491 ; + .dw 0xB5C1 ; + .dw 0x427 ; + .dw 0xCFA3 ; + .dw 0x6AD7 ; + .dw 0xC611 ; + .dw 0xD5AB ; + .dw 0xCFA4 ; + .dw 0x4DA9 ; + .dw 0x8A15 ; + .dw 0x83DD ; + .dw 0xCFA5 ; + .dw 0xE503 ; + .dw 0xCB71 ; + .dw 0x2189 ; + .dw 0xCFA6 ; + .dw 0x6A27 ; + .dw 0x2EBB ; + .dw 0xE6D9 ; + .dw 0xCFA7 ; + .dw 0xDF6B ; + .dw 0x35E5 ; + .dw 0x288D ; + .dw 0xCFA8 ; + .dw 0x42DD ; + .dw 0x6A67 ; + .dw 0xD7F1 ; + .dw 0xCFA9 ; + .dw 0x143B ; + .dw 0x70F9 ; + .dw 0x319D ; + .dw 0xCFAA ; + .dw 0x919B ; + .dw 0x7C3B ; + .dw 0x1B7B ; + .dw 0xCFAB ; + .dw 0x4413 ; + .dw 0x42CB ; + .dw 0xC3FF ; + .dw 0xCFAC ; + .dw 0x7D61 ; + .dw 0x27AB ; + .dw 0x818B ; + .dw 0xCFAD ; + .dw 0x839F ; + .dw 0x7FB1 ; + .dw 0x27A3 ; + .dw 0xCFAE ; + .dw 0x932D ; + .dw 0xE719 ; + .dw 0x5449 ; + .dw 0xCFAF ; + .dw 0x1289 ; + .dw 0xDED7 ; + .dw 0xC905 ; + .dw 0xCFB0 ; + .dw 0xE641 ; + .dw 0xDFAD ; + .dw 0xF1A5 ; + .dw 0xCFB1 ; + .dw 0xC0D1 ; + .dw 0xF7BD ; + .dw 0x3423 ; + .dw 0xCFB2 ; + .dw 0xAC39 ; + .dw 0xDC73 ; + .dw 0x4545 ; + .dw 0xCFB3 ; + .dw 0x3F39 ; + .dw 0xB1D9 ; + .dw 0x3DA7 ; + .dw 0xCFB4 ; + .dw 0x86A1 ; + .dw 0xE663 ; + .dw 0xB105 ; + .dw 0xCFB5 ; + .dw 0x52A1 ; + .dw 0xA52D ; + .dw 0xB8C7 ; + .dw 0xCFB6 ; + .dw 0x9D8B ; + .dw 0xE251 ; + .dw 0xFFB3 ; + .dw 0xCFB7 ; + .dw 0xA225 ; + .dw 0x7425 ; + .dw 0xA407 ; + .dw 0xCFB8 ; + .dw 0x13C3 ; + .dw 0xD553 ; + .dw 0x9F8F ; + .dw 0xCFB9 ; + .dw 0x9ABF ; + .dw 0x6487 ; + .dw 0xE63D ; + .dw 0xCFBA ; + .dw 0x971B ; + .dw 0xEBCD ; + .dw 0xF725 ; + .dw 0xCFBB ; + .dw 0x8B4F ; + .dw 0xCED3 ; + .dw 0x691B ; + .dw 0xCFBC ; + .dw 0x3C89 ; + .dw 0xFE7B ; + .dw 0x9105 ; + .dw 0xCFBD ; + .dw 0x86D9 ; + .dw 0xC0CD ; + .dw 0x75A5 ; + .dw 0xCFBE ; + .dw 0xD961 ; + .dw 0xF4C1 ; + .dw 0x7801 ; + .dw 0xCFBF ; + .dw 0xAAA3 ; + .dw 0xC993 ; + .dw 0x92C5 ; + .dw 0xCFC0 ; + .dw 0x8D ; + .dw 0xEAB5 ; + .dw 0xCF55 ; + .dw 0xCFC1 ; + .dw 0xF94D ; + .dw 0xB307 ; + .dw 0xA575 ; + .dw 0xCFC2 ; + .dw 0x140F ; + .dw 0x4CE7 ; + .dw 0xD78B ; + .dw 0xCFC3 ; + .dw 0xF359 ; + .dw 0x4DE7 ; + .dw 0x958B ; + .dw 0xCFC4 ; + .dw 0xD893 ; + .dw 0xBA3 ; + .dw 0x8A5D ; + .dw 0xCFC5 ; + .dw 0x5149 ; + .dw 0xCB4B ; + .dw 0x21E3 ; + .dw 0xCFC6 ; + .dw 0xA65 ; + .dw 0x7A85 ; + .dw 0x2571 ; + .dw 0xCFC7 ; + .dw 0xA2DF ; + .dw 0xC7F9 ; + .dw 0xB9AF ; + .dw 0xCFC8 ; + .dw 0xF8A3 ; + .dw 0x491D ; + .dw 0xBD37 ; + .dw 0xCFC9 ; + .dw 0xFA7B ; + .dw 0x8B45 ; + .dw 0xCD ; + .dw 0xCFCA ; + .dw 0x84F3 ; + .dw 0x1C97 ; + .dw 0xA6C7 ; + .dw 0xCFCB ; + .dw 0x1349 ; + .dw 0x6CD9 ; + .dw 0xF7E3 ; + .dw 0xCFCC ; + .dw 0x738D ; + .dw 0x9209 ; + .dw 0x90F9 ; + .dw 0xCFCD ; + .dw 0x6C31 ; + .dw 0x3A3D ; + .dw 0x7921 ; + .dw 0xCFCE ; + .dw 0x18E5 ; + .dw 0xB46F ; + .dw 0xE29B ; + .dw 0xCFCF ; + .dw 0x812D ; + .dw 0x2E4B ; + .dw 0xB56B ; + .dw 0xCFD0 ; + .dw 0x87E5 ; + .dw 0x18D5 ; + .dw 0xC509 ; + .dw 0xCFD1 ; + .dw 0x8005 ; + .dw 0xFAA1 ; + .dw 0x7DC1 ; + .dw 0xCFD2 ; + .dw 0xCCC5 ; + .dw 0xBEE7 ; + .dw 0x87FB ; + .dw 0xCFD3 ; + .dw 0x6D11 ; + .dw 0xE40B ; + .dw 0x47C5 ; + .dw 0xCFD4 ; + .dw 0xDE9F ; + .dw 0x6351 ; + .dw 0x24DB ; + .dw 0xCFD5 ; + .dw 0x8803 ; + .dw 0x690D ; + .dw 0xE3F5 ; + .dw 0xCFD6 ; + .dw 0x22C9 ; + .dw 0x505 ; + .dw 0xF573 ; + .dw 0xCFD7 ; + .dw 0xC055 ; + .dw 0xB295 ; + .dw 0xA7D3 ; + .dw 0xCFD8 ; + .dw 0x305 ; + .dw 0xD61D ; + .dw 0x933B ; + .dw 0xCFD9 ; + .dw 0xC59 ; + .dw 0x8CD1 ; + .dw 0x3D47 ; + .dw 0xCFDA ; + .dw 0x9095 ; + .dw 0x8C21 ; + .dw 0xAA23 ; + .dw 0xCFDB ; + .dw 0x5D97 ; + .dw 0x376F ; + .dw 0x3C85 ; + .dw 0xCFDC ; + .dw 0xDC49 ; + .dw 0xE393 ; + .dw 0xB31B ; + .dw 0xCFDD ; + .dw 0x9871 ; + .dw 0x61FF ; + .dw 0xCF1 ; + .dw 0xCFDE ; + .dw 0xEC8D ; + .dw 0xD8B ; + .dw 0x683D ; + .dw 0xCFDF ; + .dw 0x449D ; + .dw 0x82F5 ; + .dw 0x24FF ; + .dw 0xCFE0 ; + .dw 0x708D ; + .dw 0x8629 ; + .dw 0xB5D3 ; + .dw 0xCFE1 ; + .dw 0x7FA3 ; + .dw 0xC4EB ; + .dw 0x80C7 ; + .dw 0xCFE2 ; + .dw 0xD88F ; + .dw 0x5DBF ; + .dw 0x5113 ; + .dw 0xCFE3 ; + .dw 0xF1BD ; + .dw 0x6797 ; + .dw 0xEA3B ; + .dw 0xCFE4 ; + .dw 0xB965 ; + .dw 0x2E63 ; + .dw 0x56ED ; + .dw 0xCFE5 ; + .dw 0x15B ; + .dw 0x733 ; + .dw 0x5599 ; + .dw 0xCFE6 ; + .dw 0xB249 ; + .dw 0xAAFB ; + .dw 0xC29B ; + .dw 0xCFE7 ; + .dw 0x20C1 ; + .dw 0x26A9 ; + .dw 0x39 ; + .dw 0xCFE8 ; + .dw 0xD1E5 ; + .dw 0xCC2D ; + .dw 0x8D6D ; + .dw 0xCFE9 ; + .dw 0xB4C3 ; + .dw 0xF651 ; + .dw 0xF25 ; + .dw 0xCFEA ; + .dw 0x10F3 ; + .dw 0xFB75 ; + .dw 0x3E79 ; + .dw 0xCFEB ; + .dw 0x9B55 ; + .dw 0x2A7 ; + .dw 0xFEAB ; + .dw 0xCFEC ; + .dw 0x4623 ; + .dw 0x1BCD ; + .dw 0xFA9B ; + .dw 0xCFED ; + .dw 0xA3E3 ; + .dw 0x9B9B ; + .dw 0x2B6F ; + .dw 0xCFEE ; + .dw 0x58A9 ; + .dw 0xD303 ; + .dw 0x2287 ; + .dw 0xCFEF ; + .dw 0x3AF1 ; + .dw 0xBEFF ; + .dw 0xF90B ; + .dw 0xCFF0 ; + .dw 0xCC47 ; + .dw 0xDE4D ; + .dw 0x9E43 ; + .dw 0xCFF1 ; + .dw 0xFE51 ; + .dw 0x7DC7 ; + .dw 0x79BD ; + .dw 0xCFF2 ; + .dw 0x6B1D ; + .dw 0x6835 ; + .dw 0x7AD9 ; + .dw 0xCFF3 ; + .dw 0xC635 ; + .dw 0x955D ; + .dw 0xDE57 ; + .dw 0xCFF4 ; + .dw 0x2F0B ; + .dw 0x2555 ; + .dw 0xD887 ; + .dw 0xCFF5 ; + .dw 0xCB59 ; + .dw 0xAC01 ; + .dw 0x3CEB ; + .dw 0xCFF6 ; + .dw 0xFDF5 ; + .dw 0x510D ; + .dw 0xB54D ; + .dw 0xCFF7 ; + .dw 0xD1DB ; + .dw 0xA867 ; + .dw 0x482F ; + .dw 0xCFF8 ; + .dw 0xB1C9 ; + .dw 0x5AA7 ; + .dw 0x4121 ; + .dw 0xCFF9 ; + .dw 0x83A1 ; + .dw 0x5A65 ; + .dw 0x4161 ; + .dw 0xCFFA ; + .dw 0x9E7F ; + .dw 0xF1F ; + .dw 0x7E8F ; + .dw 0xCFFB ; + .dw 0x4D1F ; + .dw 0x7C11 ; + .dw 0xA17B ; + .dw 0xCFFC ; + .dw 0xB5FD ; + .dw 0x2AF7 ; + .dw 0x5C2B ; + .dw 0xCFFD ; + .dw 0xFA4F ; + .dw 0x580D ; + .dw 0x8E77 ; + .dw 0xCFFE ; + .dw 0xEB0B ; + .dw 0x633B ; + .dw 0x9099 ; + .dw 0xCFFF ; + .dw 0xE1A1 ; + .dw 0x7B5F ; + .dw 0xC9B ; +// COUNT = 6662 + + + + // count of UI's will be in r5, which was initialized to 0 by header + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +CHECKREG(r5, 256); // count of all 16 bit UI's. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 64 bit illegal opcode handler - skips bad instruction + + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + +dbg_fail; + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + R7 += 8; // skip offending 64 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/se_usermode_protviol.S b/sim/testsuite/bfin/se_usermode_protviol.S new file mode 100644 index 0000000..5e8a4cc --- /dev/null +++ b/sim/testsuite/bfin/se_usermode_protviol.S @@ -0,0 +1,317 @@ +//Original:/proj/frio/dv/testcases/seq/se_usermode_protviol/se_usermode_protviol.dsp +// Description: User mode "Illegal Use Supervsor Resource" Exceptions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x100 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +RETI = r0; // prevent Xs later on +RETX = r0; +RETN = r0; +RETE = r0; + + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +FP = SP; +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests +// [--sp] = RETI; // enable interrupts in supervisor mode + + R0 = 0; + R1 = -1; + +// the following instructions should EXCEPT + R6 = 0x2E; // EXCAUSE 0x2E means Illegal Use Supervidor Resource + +RAISE 15; +CLI R0; +STI r0; +// TESTSET (p0); // now allowed in user mode +r5 += 1; +// IDLE; // works in user mode + +USP = r1; +SEQSTAT = r1; +SYSCFG = r1; +RETI = r1; +RETX = r1; +RETN = r1; +RETE = r1; + + R2 = USP; + R2 = SEQSTAT; + R2 = SYSCFG; + R2 = RETI; + R2 = RETX; + R2 = RETN; + R2 = RETE; + + [ -- SP ] = USP; + [ -- SP ] = SEQSTAT; + [ -- SP ] = SYSCFG; + [ -- SP ] = RETI; + [ -- SP ] = RETX; + [ -- SP ] = RETN; + [ -- SP ] = RETE; + +SEQSTAT = [sp++]; +SYSCFG = [sp++]; +RETI = [sp++]; +RETX = [sp++]; +RETN = [sp++]; +RETE = [sp++]; + +RTX; +RTN; +RTI; +RTE; + + R6 = 0x22; // EXCAUSE 0x22 means Illegal Insn Combination +USP = [sp++]; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x2B; +CHECKREG(r5, 36); // count of all IF protection violations. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE +CC = r7 == r6; +IF CC JUMP IFETCHPROTVIOL; // If EXCAUSE != 0x2E then leave + +dbg_fail; // if the EXCAUSE is wrong the test will infinite loop + +IFETCHPROTVIOL: + R7 = RETX; // Fix up return address + R7 += 2; // skip instruction +RETX = r7; // and put back in RETX + + R5 += 1; // Count + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/bfin/seqstat.s b/sim/testsuite/bfin/seqstat.s new file mode 100644 index 0000000..45fad2c --- /dev/null +++ b/sim/testsuite/bfin/seqstat.s @@ -0,0 +1,25 @@ +# Blackfin testcase for SEQSTAT register +# mach: bfin + + .include "testutils.inc" + + .macro seqstat_test val:req + imm32 R0, \val + SEQSTAT = R0; + R1 = SEQSTAT; + CC = R7 == R1; + IF !CC JUMP 1f; + .endm + + start + + # Writes to SEQSTAT should be ignored + R7 = SEQSTAT; + + seqstat_test 0 + seqstat_test 0x1 + seqstat_test -1 + seqstat_test 0xab11cd22 + + pass +1: fail diff --git a/sim/testsuite/bfin/sign.s b/sim/testsuite/bfin/sign.s new file mode 100644 index 0000000..072263e --- /dev/null +++ b/sim/testsuite/bfin/sign.s @@ -0,0 +1,27 @@ +# Blackfin testcase for signbits +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_alu_signbits areg:req + \areg = 0; + R0 = 0x10 (Z); + \areg\().x = R0; + + imm32 r0, 0x60038; + + R0.L = SIGNBITS \areg; + + imm32 r1, 0x6fffa; + CC = R1 == R0; + if ! CC jump 1f; + .endm + + check_alu_signbits A0 + check_alu_signbits A1 + + pass +1: + fail diff --git a/sim/testsuite/bfin/simple0.s b/sim/testsuite/bfin/simple0.s new file mode 100644 index 0000000..956ce11 --- /dev/null +++ b/sim/testsuite/bfin/simple0.s @@ -0,0 +1,10 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 5; + R0 += -1; + DBGA ( R0.L , 4 ); + pass diff --git a/sim/testsuite/bfin/sri.s b/sim/testsuite/bfin/sri.s new file mode 100644 index 0000000..9f90abf --- /dev/null +++ b/sim/testsuite/bfin/sri.s @@ -0,0 +1,21 @@ +# Blackfin testcase for BITMUX +# mach: bfin + + .include "testutils.inc" + + start + + r0 = 0; + p2.l = 16; + +ilp: + BITMUX( R6 , R7, A0) (ASR); + p2 += -1; + cc=p2==0; + if !cc jump ilp; + A0 = A0 >> 8; + R0 = A0.w; + [ I1 ++ ] = R0; + nop; + + pass diff --git a/sim/testsuite/bfin/stk.s b/sim/testsuite/bfin/stk.s new file mode 100644 index 0000000..451a11e --- /dev/null +++ b/sim/testsuite/bfin/stk.s @@ -0,0 +1,78 @@ +# mach: bfin + +.include "testutils.inc" + start + + +// load up some registers. +// setup up a global pointer table and load some state. +// save the machine state and clear some of the values. +// then restore and assert some of the values to ensure that +// we maintain consitent machine state. + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = -7; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + + loadsym P0, a; + _DBG P0; + SP = P0; + FP = P0; + P1 = [ P0 ++ ]; + P2 = [ P0 ++ ]; + P0 += 4; + P4 = [ P0 ++ ]; + P5 = [ P0 ++ ]; + [ -- SP ] = ( R7:0, P5:0 ); + _DBG SP; + _DBG FP; + R0 = R0 ^ R0; + R1 = R1 ^ R1; + R2 = R2 ^ R2; + R4 = R4 ^ R4; + R5 = R5 ^ R5; + R6 = R6 ^ R6; + R7 = R7 ^ R7; + ( R7:0, P5:0 ) = [ SP ++ ]; + DBGA ( R0.L , 1 ); + DBGA ( R2.L , 3 ); + DBGA ( R7.L , 7 ); + R0 = SP; + loadsym R1, a; + CC = R0 == R1; + IF !CC JUMP abrt; + R0 = FP; + CC = R0 == R1; + CC = R0 == R1; + IF !CC JUMP abrt; + + pass +abrt: + fail + + .data +_gptab: + .dw 0x200 + .dw 0x000 + .dw 0x300 + .dw 0x400 + .dw 0x500 + .dw 0x600 + + .space (0x100) +a: + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 0xa diff --git a/sim/testsuite/bfin/stk2.s b/sim/testsuite/bfin/stk2.s new file mode 100644 index 0000000..d5cb975 --- /dev/null +++ b/sim/testsuite/bfin/stk2.s @@ -0,0 +1,107 @@ +// load up some registers. +// setup up a global pointer table and load some state. +// save the machine state and clear some of the values. +// then restore and assert some of the values to ensure that +// we maintain consitent machine state. +# mach: bfin + + +.include "testutils.inc" + start + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = -7; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + + loadsym P0, a; + P1.L = 0x1000; +//DBG P0; +//DBG P1; + SP = P0; + FP = P0; + + CALL try; + + P1 = [ P0 ++ ]; + P2 = [ P0 ++ ]; + P0 += 4; + P4 = [ P0 ++ ]; + P5 = [ P0 ++ ]; +// DBG; + [ -- SP ] = ( R7:0, P5:0 ); +// DBG SP; +// DBG FP; + R0 = R0 ^ R0; + R1 = R1 ^ R1; + R2 = R2 ^ R2; + R4 = R4 ^ R4; + R5 = R5 ^ R5; + R6 = R6 ^ R6; + R7 = R7 ^ R7; +// DBG; + ( R7:0, P5:0 ) = [ SP ++ ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 0xfff9 ); + DBGA ( R4.L , 4 ); + DBGA ( R5.L , 5 ); + DBGA ( R6.L , 6 ); + DBGA ( R7.L , 7 ); + + R0 = SP; + loadsym R1, a; + CC = R0 == R1; + IF !CC JUMP abrt; + R0 = FP; + CC = R0 == R1; + CC = R0 == R1; + IF !CC JUMP abrt; + pass +abrt: + fail + +try: + LINK 0; + [ -- SP ] = R7; + [ -- SP ] = R0; + R7 = 0x1234 (X); + [ -- SP ] = R7; + CALL bar; + SP += 4; + R0 = [ SP ++ ]; + R7 = [ SP ++ ]; + UNLINK; + RTS; + +bar: + R0 = [ SP ]; + DBGA ( R0.L , 0x1234 ); + RTS; + + .data +_gptab: + .dw 0x200 + .dw 0x000 + .dw 0x300 + .dw 0x400 + .dw 0x500 + .dw 0x600 + + .space (0x100) +a: + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 0xa diff --git a/sim/testsuite/bfin/stk3.s b/sim/testsuite/bfin/stk3.s new file mode 100644 index 0000000..131f8c5 --- /dev/null +++ b/sim/testsuite/bfin/stk3.s @@ -0,0 +1,106 @@ +// load up some registers. +// setup up a global pointer table and load some state. +// save the machine state and clear some of the values. +// then restore and assert some of the values to ensure that +// we maintain consitent machine state. + +# mach: bfin + +.include "testutils.inc" + start + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = -7; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + + loadsym P0, a; + P1.L = 0x1000; + _DBG P0; + _DBG P1; + SP = P0; + FP = P0; + + CALL try; + + P1 = [ P0 ++ ]; + P2 = [ P0 ++ ]; + P0 += 4; + P4 = [ P0 ++ ]; + P5 = [ P0 ++ ]; + [ -- SP ] = ( R7:0, P5:0 ); + _DBG SP; + _DBG FP; + R0 = R0 ^ R0; + R1 = R1 ^ R1; + R2 = R2 ^ R2; + R4 = R4 ^ R4; + R5 = R5 ^ R5; + R6 = R6 ^ R6; + R7 = R7 ^ R7; + ( R7:0, P5:0 ) = [ SP ++ ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 0xfff9); + DBGA ( R4.L , 4 ); + DBGA ( R5.L , 5 ); + DBGA ( R6.L , 6 ); + DBGA ( R7.L , 7 ); + R0 = SP; + loadsym R1, a; + CC = R0 == R1; + IF !CC JUMP abrt; + R0 = FP; + CC = R0 == R1; + CC = R0 == R1; + IF !CC JUMP abrt; + pass +abrt: + fail; + +try: + LINK 0; + [ -- SP ] = ( R7:0, P5:0 ); + R7 = 0x1234 (X); + [ -- SP ] = R7; + CALL bar; + SP += 4; + ( R7:0, P5:0 ) = [ SP ++ ]; + UNLINK; + RTS; + +bar: + LINK 0; + [ -- SP ] = ( R7:0, P5:0 ); + R0 = [ FP + 8 ]; + DBGA ( R0.L , 0x1234 ); + ( R7:0, P5:0 ) = [ SP ++ ]; + UNLINK; + RTS; + + .data +_gptab: + .dw 0x200 + .dw 0x000 + .dw 0x300 + .dw 0x400 + .dw 0x500 + .dw 0x600 + + .space (0x100) +a: + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 0xa diff --git a/sim/testsuite/bfin/stk4.s b/sim/testsuite/bfin/stk4.s new file mode 100644 index 0000000..797aa78 --- /dev/null +++ b/sim/testsuite/bfin/stk4.s @@ -0,0 +1,110 @@ +// load up some registers. +// setup up a global pointer table and load some state. +// save the machine state and clear some of the values. +// then restore and assert some of the values to ensure that +// we maintain consitent machine state. +# mach: bfin + +.include "testutils.inc" + start + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = -7; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + + loadsym P0, a; + P1.L = 0x1000; + _DBG P0; + _DBG P1; + SP = P0; + FP = P0; + + CALL try; + + P1 = [ P0 ++ ]; + P2 = [ P0 ++ ]; + P0 += 4; + P4 = [ P0 ++ ]; + P5 = [ P0 ++ ]; + [ -- SP ] = ( R7:0, P5:0 ); + _DBG SP; + _DBG FP; + R0 = R0 ^ R0; + R1 = R1 ^ R1; + R2 = R2 ^ R2; + R4 = R4 ^ R4; + R5 = R5 ^ R5; + R6 = R6 ^ R6; + R7 = R7 ^ R7; + ( R7:0, P5:0 ) = [ SP ++ ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 0xfff9 ); + DBGA ( R4.L , 4 ); + DBGA ( R5.L , 5 ); + DBGA ( R6.L , 6 ); + DBGA ( R7.L , 7 ); + R0 = SP; + loadsym R1, a; + CC = R0 == R1; + IF !CC JUMP abrt; + R0 = FP; + CC = R0 == R1; + CC = R0 == R1; + IF !CC JUMP abrt; + pass +abrt: + fail; + +try: + LINK 0; + [ -- SP ] = ( R7:0, P5:0 ); + R7 = 0x1234 (X); + [ -- SP ] = R7; + CALL bar; + R7 = [ SP ++ ]; + ( R7:0, P5:0 ) = [ SP ++ ]; + UNLINK; + RTS; + +bar: + LINK 0; + [ -- SP ] = ( R7:0, P5:0 ); + R0 = [ FP + 8 ]; + DBGA ( R0.L , 0x1234 ); + CALL foo; + ( R7:0, P5:0 ) = [ SP ++ ]; + UNLINK; + RTS; + +foo: + DBGA ( R0.L , 0x1234 ); + RTS; + + .data +_gptab: + .dw 0x200 + .dw 0x000 + .dw 0x300 + .dw 0x400 + .dw 0x500 + .dw 0x600 + + .space (0x100) +a: + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 0xa diff --git a/sim/testsuite/bfin/stk5.s b/sim/testsuite/bfin/stk5.s new file mode 100644 index 0000000..e3a8fca --- /dev/null +++ b/sim/testsuite/bfin/stk5.s @@ -0,0 +1,34 @@ +# mach: bfin + +.include "testutils.inc" + start + + SP += -12; + FP = SP; + CALL _foo; + + pass + + +_printf: + LINK 0; + [ -- SP ] = ( R7:7, P5:4 ); + R5 = [ FP + 8 ]; + DBGA ( R5.L , 0x1234 ); + R5 = [ FP + 12 ]; + DBGA ( R5.L , 0xdead ); + ( R7:7, P5:4 ) = [ SP ++ ]; + UNLINK; + RTS; + +_foo: + LINK 0; + R5 = 0xdead (Z); + [ -- SP ] = R5; + R5 = 0x1234 (X); + [ -- SP ] = R5; + CALL _printf; + P5 = 8; + SP = SP + P5; + UNLINK; + RTS; diff --git a/sim/testsuite/bfin/stk6.s b/sim/testsuite/bfin/stk6.s new file mode 100644 index 0000000..89a5e60 --- /dev/null +++ b/sim/testsuite/bfin/stk6.s @@ -0,0 +1,58 @@ +// setup a dummy stack and put values in memory 0,1,2,3...n +// then restore registers with pop instruction. +# mach: bfin + +.include "testutils.inc" + start + + SP += -12; + + P1 = SP; + R1 = 0; + P5.L = 0xdead; + SP += -((8+5)*4); // lets move the stack pointer and include the current location. i.e. 5 + P4 = (8+6); // 8 data registers and 6 pointer registers are being stored. + LSETUP ( ls0 , le0 ) LC0 = P4; +ls0: + R1 += 1; +le0: + [ P1-- ] = R1; + + ( R7:0, P5:0 ) = [ SP ++ ]; + + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 4 ); + DBGA ( R4.L , 5 ); + DBGA ( R5.L , 6 ); + DBGA ( R6.L , 7 ); + DBGA ( R7.L , 8 ); + R0 = P0; DBGA ( R0.L , 9 ); + R0 = P1; DBGA ( R0.L , 10 ); + R0 = P2; DBGA ( R0.L , 11 ); + R0 = P3; DBGA ( R0.L , 12 ); + R0 = P4; DBGA ( R0.L , 13 ); + R0 = P5; DBGA ( R0.L , 14 ); + R0 = 1; + + [ -- SP ] = ( R7:0, P5:0 ); + ( R7:0, P5:0 ) = [ SP ++ ]; + + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 4 ); + DBGA ( R4.L , 5 ); + DBGA ( R5.L , 6 ); + DBGA ( R6.L , 7 ); + DBGA ( R7.L , 8 ); + R0 = P0; DBGA ( R0.L , 9 ); + R0 = P1; DBGA ( R0.L , 10 ); + R0 = P2; DBGA ( R0.L , 11 ); + R0 = P3; DBGA ( R0.L , 12 ); + R0 = P4; DBGA ( R0.L , 13 ); + R0 = P5; DBGA ( R0.L , 14 ); + R0 = 1; + + pass diff --git a/sim/testsuite/bfin/syscfg.s b/sim/testsuite/bfin/syscfg.s new file mode 100644 index 0000000..05ebeec --- /dev/null +++ b/sim/testsuite/bfin/syscfg.s @@ -0,0 +1,25 @@ +# Blackfin testcase for SYSCFG register +# mach: bfin + + .include "testutils.inc" + + .macro syscfg_test val:req + imm32 R0, \val + R0 = SYSCFG; + SYSCFG = R0; + R1 = SYSCFG; + CC = R0 == R1; + IF !CC JUMP 1f; + .endm + + start + + syscfg_test 0 + syscfg_test 1 + syscfg_test -1 + syscfg_test 0x12345678 + # leave in sane state + syscfg_test 0x30 + + pass +1: fail diff --git a/sim/testsuite/bfin/tar10622.s b/sim/testsuite/bfin/tar10622.s new file mode 100644 index 0000000..c3c0a37 --- /dev/null +++ b/sim/testsuite/bfin/tar10622.s @@ -0,0 +1,20 @@ +# mach: bfin + +.include "testutils.inc" + start + + r2.l = 0x1234; + r2.h = 0xff90; + + r4=8; + i2=r2; + m2 = 4; + a0 = 0; + r1.l = (a0 += r4.l *r4.l) (IS) || I2 += m2 || nop; + + r0 = i2; + + dbga(r0.l, 0x1238); + dbga(r0.h, 0xff90); + + pass diff --git a/sim/testsuite/bfin/test-dma.h b/sim/testsuite/bfin/test-dma.h new file mode 100644 index 0000000..2227ff6 --- /dev/null +++ b/sim/testsuite/bfin/test-dma.h @@ -0,0 +1,28 @@ +struct bfin_dmasg { + bu32 next_desc_addr; + bu32 start_addr; + bu16 cfg; + bu16 x_count; + bs16 x_modify; + bu16 y_count; + bs16 y_modify; +} __attribute__((packed)); + +struct bfin_dma { + bu32 next_desc_ptr; + bu32 start_addr; + + bu16 BFIN_MMR_16 (config); + bu32 _pad0; + bu16 BFIN_MMR_16 (x_count); + bs16 BFIN_MMR_16 (x_modify); + bu16 BFIN_MMR_16 (y_count); + bs16 BFIN_MMR_16 (y_modify); + bu32 curr_desc_ptr, curr_addr; + bu16 BFIN_MMR_16 (irq_status); + bu16 BFIN_MMR_16 (peripheral_map); + bu16 BFIN_MMR_16 (curr_x_count); + bu32 _pad1; + bu16 BFIN_MMR_16 (curr_y_count); + bu32 _pad2; +}; diff --git a/sim/testsuite/bfin/test.h b/sim/testsuite/bfin/test.h new file mode 100644 index 0000000..38788f8 --- /dev/null +++ b/sim/testsuite/bfin/test.h @@ -0,0 +1,134 @@ +#ifndef __ASSEMBLER__ +typedef unsigned long bu32; +typedef long bs32; +typedef unsigned short bu16; +typedef short bs16; +typedef unsigned char bu8; +typedef char bs8; +#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) +#define BFIN_MMR_16(mmr) mmr, __pad_##mmr +#include "test-dma.h" +#else +#define __ADSPBF537__ /* XXX: Hack for .S files. */ +#endif +#ifndef __FDPIC__ +#include +#endif + +/* AZ AN AC0_COPY V_COPY CC AQ RND_MOD AC0 AC1 AV0 AV0S AV1 AV1S V VS */ + +#define _AZ (1 << 0) +#define _AN (1 << 1) +#define _AC0_COPY (1 << 2) +#define _V_COPY (1 << 3) +#define _CC (1 << 5) +#define _AQ (1 << 6) +#define _RND_MOD (1 << 8) +#define _AC0 (1 << 12) +#define _AC1 (1 << 13) +#define _AV0 (1 << 16) +#define _AV0S (1 << 17) +#define _AV1 (1 << 18) +#define _AV1S (1 << 19) +#define _V (1 << 24) +#define _VS (1 << 25) + +#define _SET 1 +#define _UNSET 0 + +#define PASS do { puts ("pass"); _exit (0); } while (0) +#define FAIL do { puts ("fail"); _exit (1); } while (0) +#define DBG_PASS do { asm volatile ("outc 'p'; outc 'a'; outc 's'; outc 's'; outc '\n'; hlt;"); } while (1) +#define DBG_FAIL do { asm volatile ("outc 'f'; outc 'a'; outc 'i'; outc 'l'; outc '\n'; abort;"); } while (1) + +#define HI(x) (((x) >> 16) & 0xffff) +#define LO(x) ((x) & 0xffff) + +#define INIT_R_REGS(val) init_r_regs val +#define INIT_P_REGS(val) init_p_regs val +#define INIT_B_REGS(val) init_b_regs val +#define INIT_I_REGS(val) init_i_regs val +#define INIT_L_REGS(val) init_l_regs val +#define INIT_M_REGS(val) init_m_regs val +#define include(...) +#define CHECK_INIT_DEF(...) nop; +#define CHECK_INIT(...) nop; +#define CHECKMEM32(...) +#define GEN_INT_INIT(...) nop; + +#define LD32_LABEL(reg, sym) loadsym reg, sym +#define LD32(reg, val) imm32 reg, val +#define CHECKREG(reg, val) CHECKREG reg, val +#define CHECKREG_SYM_JUMPLESS(reg, sym, scratch_reg) \ + loadsym scratch_reg, sym; \ + cc = reg == scratch_reg; \ + /* Need to avoid jumping for trace buffer. */ \ + if !cc jump fail_lvl; +#define CHECKREG_SYM(reg, sym, scratch_reg) \ + loadsym scratch_reg, sym; \ + cc = reg == scratch_reg; \ + if cc jump 9f; \ + dbg_fail; \ +9: + +#define WR_MMR(mmr, val, mmr_reg, val_reg) \ + imm32 mmr_reg, mmr; \ + imm32 val_reg, val; \ + [mmr_reg] = val_reg; +#define WR_MMR_LABEL(mmr, sym, mmr_reg, sym_reg) \ + loadsym sym_reg, sym; \ + imm32 mmr_reg, mmr; \ + [mmr_reg] = sym_reg; +#define RD_MMR(mmr, mmr_reg, val_reg) \ + imm32 mmr_reg, mmr; \ + val_reg = [mmr_reg]; + +/* Legacy CPLB bits */ +#define CPLB_L1_CACHABLE CPLB_L1_CHBL +#define CPLB_USER_RO CPLB_USER_RD + +#define DATA_ADDR_1 0xff800000 +#define DATA_ADDR_2 0xff900000 +#define DATA_ADDR_3 (DATA_ADDR_1 + 0x2000) + +/* The libgloss headers omit these defines. */ +#define EVT_OVERRIDE 0xFFE02100 +#define EVT_IMASK IMASK + +#define PAGE_SIZE_1K PAGE_SIZE_1KB +#define PAGE_SIZE_4K PAGE_SIZE_4KB +#define PAGE_SIZE_1M PAGE_SIZE_1MB +#define PAGE_SIZE_4M PAGE_SIZE_4MB + +#define CPLB_USER_RW (CPLB_USER_RD | CPLB_USER_WR) + +#define DMC_AB_SRAM 0x0 +#define DMC_AB_CACHE 0xc +#define DMC_ACACHE_BSRAM 0x8 + +#define CPLB_L1SRAM (1 << 5) +#define CPLB_DA0ACC (1 << 6) + +#define FAULT_CPLB0 (1 << 0) +#define FAULT_CPLB1 (1 << 1) +#define FAULT_CPLB2 (1 << 2) +#define FAULT_CPLB3 (1 << 3) +#define FAULT_CPLB4 (1 << 4) +#define FAULT_CPLB5 (1 << 5) +#define FAULT_CPLB6 (1 << 6) +#define FAULT_CPLB7 (1 << 7) +#define FAULT_CPLB8 (1 << 8) +#define FAULT_CPLB9 (1 << 9) +#define FAULT_CPLB10 (1 << 10) +#define FAULT_CPLB11 (1 << 11) +#define FAULT_CPLB12 (1 << 12) +#define FAULT_CPLB13 (1 << 13) +#define FAULT_CPLB14 (1 << 14) +#define FAULT_CPLB15 (1 << 15) +#define FAULT_READ (0 << 16) +#define FAULT_WRITE (1 << 16) +#define FAULT_USER (0 << 17) +#define FAULT_SUPV (1 << 17) +#define FAULT_DAG0 (0 << 18) +#define FAULT_DAG1 (1 << 18) +#define FAULT_ILLADDR (1 << 19) diff --git a/sim/testsuite/bfin/testset.s b/sim/testsuite/bfin/testset.s new file mode 100644 index 0000000..57eaa5c --- /dev/null +++ b/sim/testsuite/bfin/testset.s @@ -0,0 +1,73 @@ +# Blackfin testcase for playing with TESTSET +# mach: bfin + + .include "testutils.inc" + + start + + .macro _ts val:req + /* Load value to the external data storage */ + imm32 R0, \val + [P4] = R0; + FLUSHINV[P4]; + SSYNC; + mnop; + + imm32 R1, 0xdeadbeef + imm32 R2, 0xdeadbeef + + TESTSET (P4); + SSYNC; + mnop; + mnop; + + /* TESTSET will set CC based on low byte == 0 */ + .if \val & 0xff + if CC jump 1f; + .else + if ! CC jump 1f; + .endif + + /* Regardless of CC, the byte MSB is set to 1 */ + imm32 R1, \val | 0x80 + + /* Make sure the result is what we want */ + R2 = [P4]; + FLUSHINV[P4]; + SSYNC; + mnop; + CC = R2 == R1; + if ! CC jump 1f; + jump 2f; +1: fail +2: + .endm + .macro ts val:req + _ts \val + _ts ~(\val) + .endm + + loadsym P4, _data + + ts 0x00000000 + ts 0x00000011 + ts 0x11111111 + ts 0x11111101 + ts 0x11111110 + ts 0x111111bb + ts 0xaaaaaa00 + ts 0xabcd2222 + ts 0x000000bb + ts 0x55555555 + ts 0x5555550a + ts 0x00100010 + ts 0x00100100 + ts 0x33333000 + ts 0x000000aa + + pass + +.data +_data: +.long 0 +.size _data, .-_data diff --git a/sim/testsuite/bfin/testset2.s b/sim/testsuite/bfin/testset2.s new file mode 100644 index 0000000..66b50be --- /dev/null +++ b/sim/testsuite/bfin/testset2.s @@ -0,0 +1,37 @@ +// testset instruction +//TESTSET is an atomic test-and-set. +//If the lock was not set prior to the TESTSET, cc is set, the lock bit is set, +//and this processor gets the lock. If the lock was set +//prior to the TESTSET, cc is cleared, the lock bit is still set, +//but the processor fails to acquire the lock. +# mach: bfin + + .include "testutils.inc" + + start + + loadsym P0, datalabel; + + R0 = 0; + CC = R0; + R0 = B [ P0 ] (Z); + DBGA ( R0.L , 0 ); + TESTSET ( P0 ); + R0 = CC; + DBGA ( R0.L , 1 ); + R0 = B [ P0 ] (Z); + DBGA ( R0.L , 0x80 ); + + R0 = 0; + CC = R0; + TESTSET ( P0 ); + R0 = CC; + DBGA ( R0.L , 0 ); + R0 = B [ P0 ] (Z); + DBGA ( R0.L , 0x80 ); + + pass + + .data +datalabel: + .dw 0 diff --git a/sim/testsuite/bfin/testutils.inc b/sim/testsuite/bfin/testutils.inc new file mode 100644 index 0000000..991d167 --- /dev/null +++ b/sim/testsuite/bfin/testutils.inc @@ -0,0 +1,295 @@ +# R0 and P0 are used as tmps, consider them call clobbered by these macros. + +# To build for hardware, use: +# bfin-linux-uclibc-gcc -nostdlib -g -Wa,--defsym,BFIN_HOST=1 foo.s + +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .text + # Pad with EMUEXCPT to make sure "jump to 0" always fails +__panic: + .rep 0xf + .word 0x0025 + .endr + abort; + jump __panic; + + .global __pass +__pass: + write 1, _passmsg, 5 + exit 0 +.ifdef BFIN_JTAG +__emu_out: + /* DBGSTAT */ + imm32 P0 0xFFE05008; + +1: R7 = [P0]; + CC = BITTST (R7,0); + IF CC JUMP 1b; + + EMUDAT = R0; + RTS; +.endif + .global __fail +__fail: +.ifndef BFIN_HOST + P0.H = _rets; + P0.L = _rets; + R0 = RETS; + R0 += -4; + P1 = 8; + R2 = '9'; + LSETUP (1f, 3f) LC0 = P1; +1: + R1 = R0; + R1 >>= 28; + R1 += 0x30; + CC = R2 < R1; + IF !CC jump 2f; + R1 += 7; +2: + B[P0++] = R1; +3: + R0 <<= 4; + + write 1, _failmsg, 22 +.else + write 1, _failmsg, 5 +.endif + exit 1 + +.ifndef BFIN_HOST + .data +_failmsg: + .ascii "fail at PC=0x" +_rets: + .ascii "12345678\n" +_passmsg: + .ascii "pass\n" + .align 4 +_params: + .long 0 + .long 0 + .long 0 + .long 0 + + .text + .global __start +__start: +.else +.global ___uClibc_main; +___uClibc_main: +.global _main; +_main: +.endif + .endm + +# MACRO: system_call +# Make a libgloss/Linux system call + .macro system_call nr:req + P0 = \nr (X); + EXCPT 0; + .endm + +# MACRO: exit +# Quit the current test + .macro exit rc:req + R0 = \rc (X); +.ifndef BFIN_HOST + P0.H = _params; + P0.L = _params; + [P0] = R0; + R0 = P0; +.endif + system_call 1 + .endm + +# MACRO: pass +# Write 'pass' to stdout via syscalls and quit; +# meant for non-OS operating environments + .macro pass + CALL __pass; + .endm + +# MACRO: fail +# Write 'fail' to stdout via syscalls and quit; +# meant for non-OS operating environments + .macro fail + CALL __fail; + .endm + +# MACRO: write +# Just like the write() C function; uses system calls + .macro write fd:req, buf:req, count:req +.ifndef BFIN_HOST + P0.H = _params; + P0.L = _params; + R0 = \fd (X); + [P0] = R0; + R0.H = \buf; + R0.L = \buf; + [P0 + 4] = R0; + R0 = \count (X); + [P0 + 8] = R0; + R0 = P0; + system_call 5 +.endif + .endm + +# MACRO: outc_str +# Output a string using the debug OUTC insn + .macro outc_str ch:req, more:vararg + OUTC \ch; + .ifnb \more + outc_str \more + .endif + .endm + +# MACRO: dbg_pass +# Write 'pass' to stdout and quit (all via debug insns); +# meant for OS operating environments + .macro dbg_pass +.ifdef BFIN_JTAG + R0 = 6; + CALL __emu_out; + R0.L = 0x6170; /* 'p'=0x70 'a'=0x70 */ + R0.H = 0x7373; /* 's'=0x73 */ + CALL __emu_out; + + R0.L = 0x0A; /* newline */ + R0.H = 0x0000; + CALL __emu_out; +1: + EMUEXCPT; + JUMP 1b; +.else + outc_str 'p', 'a', 's', 's', '\n' + HLT; +.endif + .endm + +# MACRO: dbg_fail +# Write 'fail' to stdout and quit (all via debug insns); +# meant for OS operating environments + .macro dbg_fail +.ifdef BFIN_JTAG + R0 = 6; + CALL __emu_out; + R0.L = 0x6166; /* 'f'=0x66 'a'=0x61 */ + R0.H = 0x6c69; /* 'i'=0x69 'l'=0x6c */ + CALL __emu_out; + + R0.L = 0x0A; /* newline */ + R0.H = 0x0000; + CALL __emu_out; +1: + EMUEXCPT; + JUMP 1b; +.else + outc_str 'f', 'a', 'i', 'l', '\n' +.endif + ABORT; + .endm + +# MACRO: imm32 +# Load a 32bit immediate directly into a register + .macro imm32 reg:req, val:req + .if (\val) & ~0x7fff + \reg\().L = ((\val) & 0xffff); + \reg\().H = (((\val) >> 16) & 0xffff); + .else + \reg = \val; + .endif + .endm + +# MACRO: dmm32 +# Load a 32bit immediate indirectly into a register + .macro dmm32 reg:req, val:req + [--SP] = R0; + imm32 R0, \val + \reg = R0; + R0 = [SP++]; + .endm + +# MACRO: loadsym +# Load a symbol directly into a register +.ifndef BFIN_HOST + .macro loadsym reg:req, sym:req, offset=0 + \reg\().L = (\sym\() + \offset\()); + \reg\().H = (\sym\() + \offset\()); + .endm +.else + .macro loadsym reg:req, sym:req, offset=0 + [--SP] = R0; + R0 = [P3 + \sym\()@GOT17M4]; + .if \offset + [--SP] = R1; + R1 = \offset\() (Z); + R0 = R0 + R1; + R1 = [SP++]; + .endif + \reg = R0; + R0 = [SP++]; + .endm +.endif + +# MACRO: CHECKREG +# Use debug insns to verify the value of a register matches + .macro CHECKREG reg:req, val:req + DBGAL (\reg, ((\val) & 0xffff)); + DBGAH (\reg, (((\val) >> 16) & 0xffff)); + .endm + +# internal helper macros; ignore them + .macro __init_regs reg:req, max:req, x:req, val:req + .ifle (\x - \max) + imm32 \reg\()\x, \val + .endif + .endm + .macro _init_regs reg:req, max:req, val:req + __init_regs \reg, \max, 0, \val + __init_regs \reg, \max, 1, \val + __init_regs \reg, \max, 2, \val + __init_regs \reg, \max, 3, \val + __init_regs \reg, \max, 4, \val + __init_regs \reg, \max, 5, \val + __init_regs \reg, \max, 6, \val + __init_regs \reg, \max, 7, \val + .endm + +# MACRO: init_r_regs +# MACRO: init_p_regs +# MACRO: init_b_regs +# MACRO: init_i_regs +# MACRO: init_l_regs +# MACRO: init_m_regs +# Set the specified group of regs to the specified value + .macro init_r_regs val:req + _init_regs R, 7, \val + .endm + .macro init_p_regs val:req + _init_regs P, 5, \val + .endm + .macro init_b_regs val:req + _init_regs B, 3, \val + .endm + .macro init_i_regs val:req + _init_regs I, 3, \val + .endm + .macro init_l_regs val:req + _init_regs L, 3, \val + .endm + .macro init_m_regs val:req + _init_regs M, 3, \val + .endm + + // the test framework needs things to be quiet, so don't + // print things out by default. + .macro _DBG reg:req + //DBG \reg; + .endm + + .macro _DBGCMPLX reg:req + // + .endm diff --git a/sim/testsuite/bfin/unlink.S b/sim/testsuite/bfin/unlink.S new file mode 100644 index 0000000..978d39e --- /dev/null +++ b/sim/testsuite/bfin/unlink.S @@ -0,0 +1,68 @@ +# Blackfin testcase for unlink insn with any immediate value +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + /* Set up exception handler */ + imm32 P4, EVT3; + loadsym R1, _evx; + [P4] = R1; + + /* Lower to the code we want to single step through */ + loadsym P1, _usr; + RETI = P1; + + imm32 FP, 0x800000 + imm32 R0, 0x12345678; + [FP] = R0; + imm32 R0, 0x87654321; + [FP + 4] = R0; + + RTI; + +_usr: + imm32 FP, 0x800000 + + .byte 0x01, 0xe8 +.Linsn: + .byte 0, 0 + + imm32 R0, 0x12345678; + R1 = FP; + CC = R0 == R1; + IF !CC jump _fail; + + imm32 R0, 0x87654321; + R1 = RETS; + CC = R0 == R1; + IF !CC jump _fail; + + imm32 R0, 0x800008; + R1 = SP; + CC = R0 == R1; + IF !CC jump _fail; + + loadsym P0, .Linsn; + R0 = W[P0]; + R0 += 1; + W[P0] = R0; + SSYNC; + + R0 = R0.L; + CC = R0 == 0; + IF CC jump _pass; + jump _usr; + + .align 4; +_evx: + dbg_fail; + +_pass: + dbg_pass; + +_fail: + dbg_fail; diff --git a/sim/testsuite/bfin/up0.s b/sim/testsuite/bfin/up0.s new file mode 100644 index 0000000..ed705b8 --- /dev/null +++ b/sim/testsuite/bfin/up0.s @@ -0,0 +1,41 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 1; + DBGA ( R0.L , 1 ); + + R1.L = 2; + DBGA ( R1.L , 2 ); + + R2 = 3; + A0.x = R2; + R0 = A0.x; + DBGA ( R0.L , 3 ); + + P0 = 4; + R0 = P0; + DBGA ( R0.L , 4 ); + + R0 = 45; + R1 = 22; + A1 = R0.L * R1.L, A0 = R0.H * R1.H; + _DBG A1; + + loadsym I2, foo; + P0 = I2; + R0 = 0x0333 (X); + R3 = 0x0444 (X); + + R3.L = ( A0 = R0.L * R0.L ) || [ I2 ++ ] = R3 || NOP; + DBGA ( R3.L , 0x14 ); + R0 = [ P0 ]; + DBGA ( R0.L , 0x0444 ); + + pass + + .data +foo: + .space (0x10); diff --git a/sim/testsuite/bfin/usp.S b/sim/testsuite/bfin/usp.S new file mode 100644 index 0000000..e77ff52 --- /dev/null +++ b/sim/testsuite/bfin/usp.S @@ -0,0 +1,50 @@ +# Blackfin testcase for USP handling +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + imm32 R5, 0x44455566 + imm32 R6, 0x12345678 + imm32 R7, 0x9abcdef0 + + imm32 p0, EVT3; + loadsym r0, exception; + [p0] = r0; + + loadsym r0, usermode; + reti = r0; + + SP = R6; + USP = R7; + RTI; + +usermode: + # SP should now be USP + R1 = SP; + CC = R1 == R7; + IF !CC JUMP fail; + + # Now set SP to another value + SP = R5; + + # Move up to exception space + EXCPT 0; + +exception: + # SP should be the same as original, but USP should change + R1 = SP; + CC = R1 == R6; + IF !CC JUMP fail; + + R1 = USP; + CC = R1 == R5; + IF !CC JUMP fail; + + dbg_pass + +fail: + dbg_fail diff --git a/sim/testsuite/bfin/vec-abs-2.S b/sim/testsuite/bfin/vec-abs-2.S new file mode 100644 index 0000000..d171e83 --- /dev/null +++ b/sim/testsuite/bfin/vec-abs-2.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x0; + R0.L = 0x8000; + R1 = ABS R0 (V); + R7 = ASTAT; + R2.H = 0x0; + R2.L = 0x7fff; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN */ + R3.H = HI(_AN); + R3.L = LO(_AN); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ V V_COPY VS */ + R3.H = HI(_AZ|_V|_V_COPY|_VS); + R3.L = LO(_AZ|_V|_V_COPY|_VS); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/vec-abs-3.S b/sim/testsuite/bfin/vec-abs-3.S new file mode 100644 index 0000000..bf003a1 --- /dev/null +++ b/sim/testsuite/bfin/vec-abs-3.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x8000; + R0.L = 0x0; + R1 = ABS R0 (V); + R7 = ASTAT; + R2.H = 0x7fff; + R2.L = 0x0; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN */ + R3.H = HI(_AN); + R3.L = LO(_AN); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ V V_COPY VS */ + R3.H = HI(_AZ|_V|_V_COPY|_VS); + R3.L = LO(_AZ|_V|_V_COPY|_VS); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/vec-abs.S b/sim/testsuite/bfin/vec-abs.S new file mode 100644 index 0000000..97ec84f --- /dev/null +++ b/sim/testsuite/bfin/vec-abs.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x1234; + R0.L = 0xcdef; + R1 = ABS R0 (V); + R7 = ASTAT; + R2.H = 0x1234; + R2.L = 0x3211; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AN V V_COPY */ + R3.H = HI(_AZ|_AN|_V|_V_COPY); + R3.L = LO(_AZ|_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: */ + R3.H = HI(0); + R3.L = LO(0); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/vec-neg-2.S b/sim/testsuite/bfin/vec-neg-2.S new file mode 100644 index 0000000..9ea15ec --- /dev/null +++ b/sim/testsuite/bfin/vec-neg-2.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x0; + R0.L = 0x8000; + R1 = -R0 (V); + R7 = ASTAT; + R2.H = 0x0; + R2.L = 0x7fff; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN AC0 AC0_COPY */ + R3.H = HI(_AN|_AC0|_AC0_COPY); + R3.L = LO(_AN|_AC0|_AC0_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ V V_COPY VS AC1 */ + R3.H = HI(_AZ|_V|_V_COPY|_VS|_AC1); + R3.L = LO(_AZ|_V|_V_COPY|_VS|_AC1); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/vec-neg-3.S b/sim/testsuite/bfin/vec-neg-3.S new file mode 100644 index 0000000..d748213 --- /dev/null +++ b/sim/testsuite/bfin/vec-neg-3.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x8000; + R0.L = 0x0; + R1 = -R0 (V); + R7 = ASTAT; + R2.H = 0x7fff; + R2.L = 0x0; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN AC0 AC0_COPY */ + R3.H = HI(_AN|_AC1); + R3.L = LO(_AN|_AC1); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ V V_COPY VS AC1 */ + R3.H = HI(_AZ|_V|_V_COPY|_VS|_AC0|_AC0_COPY); + R3.L = LO(_AZ|_V|_V_COPY|_VS|_AC0|_AC0_COPY); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/vec-neg.S b/sim/testsuite/bfin/vec-neg.S new file mode 100644 index 0000000..1b9b076 --- /dev/null +++ b/sim/testsuite/bfin/vec-neg.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x1234; + R0.L = 0xcdef; + R1 = -R0 (V); + R7 = ASTAT; + R2.H = 0xedcc; + R2.L = 0x3211; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ V V_COPY AC0 AC0_COPY AC1 */ + R3.H = HI(_AZ|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_AZ|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AN */ + R3.H = HI(_AN); + R3.L = LO(_AN); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/bfin/vecadd.s b/sim/testsuite/bfin/vecadd.s new file mode 100644 index 0000000..7e568ec --- /dev/null +++ b/sim/testsuite/bfin/vecadd.s @@ -0,0 +1,65 @@ +# mach: bfin + +.include "testutils.inc" + start + +// create two short vectors v_a, v_b +// where each element of v_a is the index +// where each element of v_b is 128-index + R2 = 0; + loadsym P0, v_a; + loadsym P1, v_b; + P2 = 0; + R3 = 128 (X); + R0 = 0; + R1 = 128 (X); +L$1: + W [ P0 ++ ] = R0; + W [ P1 ++ ] = R1; + R0 += 1; + R1 += -1; + CC = R0 < R3; + IF CC JUMP L$1 (BP); + + loadsym P0, v_a; + loadsym P1, v_b; + + CALL vecadd; + + loadsym P0, v_c; + R2 = 0; + R3 = 128 (X); +L$3: + R0 = W [ P0 ++ ] (X); + DBGA ( R0.L , 128 ); + R2 += 1; + CC = R2 < R3; + IF CC JUMP L$3; + _DBG R6; + pass + +vecadd: + + loadsym I0, v_a; + loadsym I1, v_b; + loadsym I2, v_c; + + P5 = 128 (X); + LSETUP ( L$2 , L$2end ) LC0 = P5 >> 1; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; +L$2: + R2 = R0 +|+ R1 || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; +L$2end: + [ I2 ++ ] = R2; + + + RTS; + + .data +v_a: + .space (512); +v_b: + .space (512); +v_c: + .space (512); diff --git a/sim/testsuite/bfin/vit_max.s b/sim/testsuite/bfin/vit_max.s new file mode 100644 index 0000000..35eaa41 --- /dev/null +++ b/sim/testsuite/bfin/vit_max.s @@ -0,0 +1,57 @@ +# Blackfin testcase for VIT_MAX (taken from PRM) +# mach: bfin + + .include "testutils.inc" + + start + + imm32 R3, 0xFFFF0000 + imm32 R2, 0x0000FFFF + A0 = 0; + R5 = VIT_MAX (R3, R2) (ASL); + R4 = 0 (x); + CC = R5 == R4; + IF !CC JUMP 1f; + imm32 R6, 0x00000002 + R4 = A0; + CC = R4 == R6; + IF !CC JUMP 1f; + + imm32 R1, 0xFEEDBEEF + imm32 R0, 0xDEAF0000 + A0 = 0; + R7 = VIT_MAX (R1, R0) (ASR); + imm32 R4, 0xFEED0000 + CC = R4 == R7; + IF !CC JUMP 1f; + imm32 R6, 0x80000000 + R2 = A0.W; + CC = R2 == R6; + IF !CC JUMP 1f; + + imm32 R1, 0xFFFF0000 + A0 = 0; + R3.L = VIT_MAX (R1) (ASL); + R3 = R3.L; + R4 = 0 (x); + CC = R3 == R4; + IF !CC JUMP 1f; + R6 = A0.W; + CC = R6 == R4; + IF !CC JUMP 1f; + + imm32 R1, 0x1234FADE + imm32 R2, 0xFFFFFFFF + A0.W = R2; + R3.L = VIT_MAX (R1) (ASR); + R3 = R3.L; + imm32 R4 0x00001234 + CC = R4 == R3; + IF !CC JUMP 1f; + imm32 R7, 0xFFFFFFFF + R0 = A0.W; + CC = R7 == R0; + IF !CC JUMP 1f; + + pass +1: fail diff --git a/sim/testsuite/bfin/vit_max2.s b/sim/testsuite/bfin/vit_max2.s new file mode 100644 index 0000000..b7c6a0e --- /dev/null +++ b/sim/testsuite/bfin/vit_max2.s @@ -0,0 +1,53 @@ +# Blackfin testcase for parallel VIT_MAX (taken from PRM) +# mach: bfin + + .include "testutils.inc" + + start + + loadsym P0, scratch + + # Do parallel VIT_MAX's with stores to same reg; don't really + # care what the result is of VIT_MAX as long as it doesn't + # clobber the memory store. + + imm32 R1, 0xFFFF0000 + imm32 R2, 0x0000FFFF + imm32 R0, 0xFACE + R0 = VIT_MAX (R1, R2) (ASL) || W[P0] = R0.L; + imm32 R0, 0xFACE + R4 = W[P0]; + CC = R4 == R0; + IF !CC JUMP 1f; + + imm32 R5, 0xFEEDBEEF + imm32 R4, 0xDEAF0000 + imm32 R6, 0xFACE + R6 = VIT_MAX (R5, R4) (ASR) || W[P0] = R6.L; + imm32 R6, 0xFACE + R4 = W[P0]; + CC = R4 == R6; + IF !CC JUMP 1f; + + imm32 R3, 0xFFFF0000 + imm32 R1, 0xFACE + R1.L = VIT_MAX (R3) (ASL) || W[P0] = R1.L; + imm32 R1, 0xFACE + R4 = W[P0]; + CC = R4 == R1; + IF !CC JUMP 1f; + + imm32 R2, 0x1234FADE + imm32 R5, 0xFACE + R5.L = VIT_MAX (R2) (ASR) || W[P0] = R5.L; + imm32 R5, 0xFACE + R4 = W[P0]; + CC = R4 == R5; + IF !CC JUMP 1f; + + pass +1: fail + + .data +scratch: + .dw 0xffff diff --git a/sim/testsuite/bfin/viterbi2.s b/sim/testsuite/bfin/viterbi2.s new file mode 100644 index 0000000..6fb9ad0 --- /dev/null +++ b/sim/testsuite/bfin/viterbi2.s @@ -0,0 +1,254 @@ +# mach: bfin + +// The assembly program uses two instructions to speed the decoder inner loop: +// R6= VMAX/VMAX (R5, R4) A0>>2; +// R2 =H+L (SGN(R0)*R1); +// VMAX is a 2-way parallel comparison of four updated path metrics, resulting +// in 2 new path metrics as well as a 2 bit field indicating the selection +// results. This 2 bit field is shifted into accumulator A0. This instruction +// implements the selections of a complete butterfly for a rate 1/n system. +// The H+L(SGN) instruction is used to compute the branch metric used by each +// butterfly. It takes as input a pair of values representing the received +// symbol, and another pair of values which are +1 or -1. The latter come +// from a pre-computed table that holds all the branch metric information for +// a specific set of polynomials. As all symbols are assumed to be binary, +// distance metrics between a received symbol and a branch metric are computed +// by adding and subtracting the values of the symbol according to the +// transition of a branch. + +.include "testutils.inc" + start + + // 16 in bytes for M2 + // A few pointer initializations + // P2 points to decision history, where outputs are stored + loadsym P2, DecisionHistory + + // P4 holds address of APMFrom + loadsym P4, APMFrom; + + // P5 holds address of APMTo + loadsym P5, APMTo; + + // I0 points to precomputed d's + loadsym I0, BranchStorage; + + M2.L = 32; + + loadsym P0, InputData; + + // storage for all precomputed branch metrics + loadsym P1, BranchStorage; + + R6 = 0; R0 = 0; // inits + + R0.L = 0x0001; + R0.H = 0x0001; + [ P1 + 0 ] = R0; + R0.L = 0xffff; + R0.H = 0xffff; + [ P1 + 4 ] = R0; + R0.L = 0xffff; + R0.H = 0x0001; + [ P1 + 8 ] = R0; + R0.L = 0x0001; + R0.H = 0xffff; + [ P1 + 12 ] = R0; + R0.L = 0xffff; + R0.H = 0x0001; + [ P1 + 16 ] = R0; + R0.L = 0x0001; + R0.H = 0xffff; + [ P1 + 20 ] = R0; + R0.L = 0x0001; + R0.H = 0x0001; + [ P1 + 24 ] = R0; + R0.L = 0xffff; + R0.H = 0xffff; + [ P1 + 28 ] = R0; + R0.L = 0x0001; + R0.H = 0xffff; + [ P1 + 32 ] = R0; + R0.L = 0xffff; + R0.H = 0x0001; + [ P1 + 36 ] = R0; + R0.L = 0xffff; + R0.H = 0xffff; + [ P1 + 40 ] = R0; + R0.L = 0x0001; + R0.H = 0x0001; + [ P1 + 44 ] = R0; + R0.L = 0xffff; + R0.H = 0xffff; + [ P1 + 48 ] = R0; + R0.L = 0x0001; + R0.H = 0x0001; + [ P1 + 52 ] = R0; + R0.L = 0x0001; + R0.H = 0xffff; + [ P1 + 56 ] = R0; + R0.L = 0xffff; + R0.H = 0x0001; + [ P1 + 60 ] = R0; + + P1 = 18; + LSETUP ( L$0 , L$0end ) LC0 = P1; // SymNo loop start + +L$0: + + // Get a symbol and leave it resident in R1 + R1 = [ P0 ]; // R1=(InputData[SymNo*2+1] InputData[SymNo*2]) + P0 += 4; + + A0 = 0; + + // I0 points to precomputed D1, D0 + loadsym I0, BranchStorage; + + I1 = P4; // I1 points to APM[From] + I2 = P4; + I2 += M2; // I2 points to APM[From+16] + I3 = P5; // I3 points to APM[To] + + P1 = 16; + P1 += -1; + LSETUP ( L$1 , L$1end ) LC1 = P1; + + // APMFrom and APMTo are in alternate + // memory banks. + + R0 = [ I0 ++ ]; // load R0 = (D1 D0) + R3.L = W [ I1 ++ ]; // load RL3 = PM0 + // (R1 holds current symbol) + + R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L; // apply sum-on-sign instruction + R3.H = W [ I2 ++ ]; // now, R3 = (PM1 PM0) + +L$1: + R5 = R3 +|- R2 , R4 = R3 -|+ R2 || R0 = [ I0 ++ ] || NOP; + // R5 = (PM11 PM01) R4 = (PM10 PM00) + // and load next (D1 D0) + + R6 = VIT_MAX( R5 , R4 ) (ASR) || R3.L = W [ I1 ++ ] || NOP; + // do 2 ACS in parallel + // R6 = (nPM1 nPM0) and update to A0 + +L$1end: + + R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L || R3.H = W [ I2 ++ ] || [ I3 ++ ] = R6; + // store new path metrics in + // two consecutive locations + + R5 = R3 +|- R2 , R4 = R3 -|+ R2; + + R6 = VIT_MAX( R5 , R4 ) (ASR); + + [ I3 ++ ] = R6; + + R7 = A0.w; + [ P2 ] = R7; + P2 += 4; // store history + + FP = P4; // swap pointers From <--> To + P4 = P5; +L$0end: + P5 = FP; + + // check results + loadsym I0, DecisionHistory + + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x6ff2 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0xf99f ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x9909 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x6666 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x0096 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x6996 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x9309 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x0000 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0xffff ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0xffff ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0xf0ff ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0xcf00 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x9009 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x07f6 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x6004 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x6996 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x8338 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x3443 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x6bd6 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x6197 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x6c26 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x0990 ); + + pass + + .data + .align 8 +InputData: + .dw 0x0001 + .dw 0x0001 + .dw 0xffff + .dw 0xfffb + .dw 0x0005 + .dw 0x0001 + .dw 0xfffd + .dw 0xfffd + .dw 0x0005 + .dw 0x0001 + .dw 0x0001 + .dw 0x0001 + .dw 0xffff + .dw 0xfffb + .dw 0x0005 + .dw 0x0001 + .dw 0xfffd + .dw 0xfffd + .dw 0x0005 + .dw 0x0001 + + .align 8 +APMFrom: + .dw 0xc000 + .dw 0x0 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + + .align 8 +APMTo: + .space (32*8) + + .align 8 +BranchStorage: + .space (32*8) + + .align 8 +DecisionHistory: + .space (18*4) diff --git a/sim/testsuite/bfin/wtf.s b/sim/testsuite/bfin/wtf.s new file mode 100644 index 0000000..2ec8507 --- /dev/null +++ b/sim/testsuite/bfin/wtf.s @@ -0,0 +1,26 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym p0, foo; + r2 = p0; + r2 += 4; + [p0++]=p0; + loadsym i0, foo; + r0=[i0]; + R3 = P0; + CC = R2 == R3 + if ! CC jump _fail; + R3 = I0; + CC = R0 == R3; + if ! CC jump _fail; + +_halt0: + pass; +_fail: + fail; + + .data +foo: + .space (0x10) diff --git a/sim/testsuite/bfin/x1.s b/sim/testsuite/bfin/x1.s new file mode 100644 index 0000000..7ef1496 --- /dev/null +++ b/sim/testsuite/bfin/x1.s @@ -0,0 +1,79 @@ +# mach: bfin + +.include "testutils.inc" + start + + +// 0.5 + imm32 r0, 0x40004000; + imm32 r1, 0x40004000; + R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); + checkreg r2, 0x40004000; + checkreg r3, 0; + + imm32 r1, 0x10001000; + + R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); + checkreg r2, 0x28002800; + checkreg r3, 0x18001800; + + R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR); + checkreg r0, 0x20002000; + checkreg r1, 0x08000800; + + R0 = 1; + R0 <<= 15; + R1 = R0 << 16; + R0 = R0 | R1; + R1 = R0; + checkreg r0, 0x80008000; + checkreg r1, 0x80008000; + + R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); + checkreg r2, 0x80008000; + checkreg r3, 0x0; + + R4 = 0; + R2 = R2 +|+ R4, R3 = R2 -|- R4 (S , ASR); + checkreg r2, 0xc000c000; + checkreg r3, 0xc000c000; + + R2 = R2 +|+ R3, R3 = R2 -|- R3 (S , ASR); + checkreg r2, 0xc000c000; + checkreg r3, 0x0; + + R4 = R2 +|+ R2, R5 = R2 -|- R2 (ASL); + checkreg r4, 0x0 + checkreg r5, 0x0 + + R2 = R2 +|+ R2, R3 = R2 -|- R2 (S , ASL); + checkreg r2, 0x80008000; + checkreg r3, 0x0; + + +imm32 r0, 0x50004000; +imm32 r1, 0x40005000; +R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL); +checkreg r2, 0x7fff7fff; +checkreg r3, 0x2000e000; +R4 = R0 +|+ R1, R5 = R0 -|- R1 (ASL); +checkreg r4, 0x20002000 +checkreg r5, 0x2000e000 + +imm32 r0, 0x30001000; +imm32 r1, 0x10003000; +R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL); +checkreg r2, 0x7fff7fff; +checkreg r3, 0x4000c000; +R4 = R0 +|+ R1, R5 = R0 -|- R1 (ASL); +checkreg r4, 0x80008000 +checkreg r5, 0x4000c000 + +imm32 r0, 0x20001fff; +imm32 r1, 0x1fff2000; +R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL); +checkreg r2, 0x7ffe7ffe; +checkreg r3, 0x0002fffe; + + + pass diff --git a/sim/testsuite/bfin/zcall.s b/sim/testsuite/bfin/zcall.s new file mode 100644 index 0000000..bdb82c7 --- /dev/null +++ b/sim/testsuite/bfin/zcall.s @@ -0,0 +1,44 @@ +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + CALL _foo; + pass + +___main: + RTS; + +_m1: + LINK 0; + R7 = [ FP + 8 ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R7.L , 3 ); + UNLINK; + RTS; + +_m2: + LINK 0; + R7 = [ FP + 8 ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R7.L , 3 ); + [ -- SP ] = R7; + CALL _m1; + SP += 4; + UNLINK; + RTS; + +_foo: + LINK 0; + CALL ___main; + R7 = 3; + [ -- SP ] = R7; + R0 = 1; + R1 = 2; + CALL _m2; + SP += 4; + UNLINK; + RTS; diff --git a/sim/testsuite/bfin/zeroflagrnd.s b/sim/testsuite/bfin/zeroflagrnd.s new file mode 100644 index 0000000..1425c07 --- /dev/null +++ b/sim/testsuite/bfin/zeroflagrnd.s @@ -0,0 +1,37 @@ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT=R0; + + R0.L = -32768; + R0.H = -1; + R0.L = R0 (RND); + DBGA ( R0.L , 0 ); + + _DBG R0; +//R0 = ASTAT; +//DBG R0; +//DBGA ( R0.L , 0x1 ); + cc = az; + r0 = cc; + dbga( r0.l, 1); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + pass diff --git a/sim/testsuite/bpf/ChangeLog b/sim/testsuite/bpf/ChangeLog new file mode 100644 index 0000000..17dd79b --- /dev/null +++ b/sim/testsuite/bpf/ChangeLog @@ -0,0 +1,20 @@ +2020-09-08 David Faust + + * alu.s: Correct div and mod tests. + * alu32.s: Likewise. + +2020-08-04 David Faust + Jose E. Marchesi + + * allinsn.exp: New file. + * alu.s: Likewise. + * alu32.s: Likewise. + * endbe.s: Likewise. + * endle.s: Likewise. + * jmp.s: Likewise. + * jmp32.s: Likewise. + * ldabs.s: Likewise. + * mem.s: Likewise. + * mov.s: Likewise. + * testutils.inc: Likewise. + * xadd.s: Likewise. diff --git a/sim/testsuite/bpf/allinsn.exp b/sim/testsuite/bpf/allinsn.exp new file mode 100644 index 0000000..2cca770 --- /dev/null +++ b/sim/testsuite/bpf/allinsn.exp @@ -0,0 +1,26 @@ +# eBPF simulator testsuite + +if [istarget bpf-unknown-none] { + # all machines + set all_machs "bpf" + + global global_sim_options + if ![info exists global_sim_options] { + set global_sim_options "--memory-size=4Mb" + } + + global global_ld_options + if ![info exists global_ld_options] { + set global_ld_options "-Ttext=0x0" + } + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/bpf/alu.s b/sim/testsuite/bpf/alu.s new file mode 100644 index 0000000..4dc37b1 --- /dev/null +++ b/sim/testsuite/bpf/alu.s @@ -0,0 +1,121 @@ +# mach: bpf +# output: pass\nexit 0 (0x0)\n +;;; alu.s +;;; Tests for ALU64 BPF instructions in simulator + + .include "testutils.inc" + + .text + .global main + .type main, @function +main: + mov %r1, 0 + mov %r2, -1 + + ;; add + add %r1, 1 + add %r2, -1 + add %r1, %r2 + fail_ne %r1, -1 + + ;; sub + sub %r1, %r1 + fail_ne %r1, 0 + sub %r1, 10 + sub %r2, %r1 + fail_ne %r2, 8 + + ;; mul + mul %r2, %r2 ; r2 = 64 + mul %r2, 3 ; r2 = 192 + mov %r1, -3 + mul %r1, %r2 ; r1 = -576 + mul %r2, 0 + fail_ne %r1, -576 + fail_ne %r2, 0 + mul %r1, %r1 + mul %r1, %r1 + fail_ne %r1, 110075314176 + + ;; div + div %r2, %r1 + fail_ne %r2, 0 + div %r1, 10000 + fail_ne %r1, 11007531 + div %r1, %r1 + fail_ne %r1, 1 + + ;; div is unsigned + lddw %r1, -8 + div %r1, 2 + fail_ne %r1, 0x7ffffffffffffffc ; sign bits NOT maintained - large pos. + + ;; and + lddw %r1, 0xaaaaaaaa55555555 + and %r1, 0x55aaaaaa ; we still only have 32-bit imm. + fail_ne %r1, 0x0000000055000000 + lddw %r2, 0x5555555a5aaaaaaa + and %r2, %r1 + fail_ne %r2, 0x0000000050000000 + + ;; or + or %r2, 0xdeadbeef + fail_ne %r2, 0xffffffffdeadbeef ; 0xdeadbeef gets sign extended + lddw %r1, 0xdead00000000beef + lddw %r2, 0x0000123456780000 + or %r1, %r2 + fail_ne %r1, 0xdead12345678beef + + ;; lsh + mov %r1, 0xdeadbeef + lsh %r1, 11 + fail_ne %r1, 0xfffffef56df77800 ; because deadbeef gets sign ext. + mov %r2, 21 + lsh %r1, %r2 + fail_ne %r1, 0xdeadbeef00000000 + + ;; rsh + rsh %r1, 11 + fail_ne %r1, 0x001bd5b7dde00000 ; 0xdeadbeef 00000000 >> 0xb + rsh %r1, %r2 + fail_ne %r1, 0x00000000deadbeef + + ;; arsh + arsh %r1, 8 + fail_ne %r1, 0x0000000000deadbe + lsh %r1, 40 ; r1 = 0xdead be00 0000 0000 + arsh %r1, %r2 ; r1 arsh (r2 == 21) + fail_ne %r1, 0xfffffef56df00000 + + ;; mod + mov %r1, 1025 + mod %r1, 16 + fail_ne %r1, 1 + + ;; mod is unsigned + mov %r1, 1025 + mod %r1, -16 ; mod unsigned -> will treat as large positive + fail_ne %r1, 1025 + + mov %r1, -25 ; -25 is 0xff..ffe7 + mov %r2, 5 ; ... which when unsigned is a large positive + mod %r1, %r2 ; ... which is not evenly divisible by 5 + fail_ne %r1, 1 + + ;; xor + mov %r1, 0 + xor %r1, %r2 + fail_ne %r1, 5 + xor %r1, 0x7eadbeef + fail_ne %r1, 0x7eadbeea + xor %r1, %r1 + fail_ne %r1, 0 + + ;; neg + neg %r2 + fail_ne %r2, -5 + mov %r1, -1025 + neg %r1 + fail_ne %r1, 1025 + + pass diff --git a/sim/testsuite/bpf/alu32.s b/sim/testsuite/bpf/alu32.s new file mode 100644 index 0000000..e8d5062 --- /dev/null +++ b/sim/testsuite/bpf/alu32.s @@ -0,0 +1,110 @@ +# mach: bpf +# output: pass\nexit 0 (0x0)\n +;; alu32.s +;; Tests for ALU(32) BPF instructions in simulator + + .include "testutils.inc" + + .text + .global main + .type main, @function +main: + mov32 %r1, 10 ; r1 = 10 + mov32 %r2, -5 ; r2 = -5 + + ;; add + add32 %r1, 1 ; r1 += 1 (r1 = 11) + add32 %r2, -1 ; r2 += -1 (r2 = -6) + add32 %r1, %r2 ; r1 += r2 (r1 = 11 + -6 = 5) + fail_ne32 %r1, 5 + + ;; sub + sub32 %r1, 5 ; r1 -= 5 (r1 = 0) + sub32 %r1, -5 ; r1 -= -5 (r1 = 5) + sub32 %r1, %r2 ; r1 -= r2 (r1 = 5 - -6 = 11) + fail_ne32 %r1, 11 + + ;; mul + mul32 %r1, 2 ; r1 *= 2 (r1 = 22) + mul32 %r1, -2 ; r1 *= -2 (r1 = -44) + mul32 %r1, %r2 ; r1 *= r2 (r1 = -44 * -6 = 264) + fail_ne32 %r1, 264 + + ;; div + div32 %r1, 6 + mov32 %r2, 11 + div32 %r1, %r2 + fail_ne32 %r1, 4 + + ;; div is unsigned + mov32 %r1, -8 ; 0xfffffff8 + div32 %r1, 2 + fail_ne32 %r1, 0x7ffffffc ; sign bits are not preserved + + ;; and (bitwise) + mov32 %r1, 0xb ; r1 = (0xb = 0b1011) + mov32 %r2, 0x5 ; r2 = (0x5 = 0b0101) + and32 %r1, 0xa ; r1 &= (0xa = 0b1010) = (0b1010 = 0xa) + fail_ne32 %r1, 0xa + and32 %r1, %r2 ; r1 &= r2 = 0x0 + fail_ne32 %r1, 0x0 + + ;; or (bitwise) + or32 %r1, 0xb + or32 %r1, %r2 + fail_ne32 %r1, 0xf + + ;; lsh (left shift) + lsh32 %r1, 4 ; r1 <<= 4 (r1 = 0xf0) + mov32 %r2, 24 ; r2 = 24 + lsh32 %r1, %r2 + fail_ne32 %r1, 0xf0000000 + + ;; rsh (right logical shift) + rsh32 %r1, 2 + rsh32 %r1, %r2 + fail_ne32 %r1, 0x3c ; (0xf000 0000 >> 26) + + ;; arsh (right arithmetic shift) + arsh32 %r1, 1 + or32 %r1, 0x80000000 + mov32 %r2, 3 + arsh32 %r1, %r2 + fail_ne %r1, 0x00000000F0000003 + ; Note: make sure r1 is NOT sign-extended + ; i.e. upper-32 bits should be untouched + + ;; mod + mov32 %r1, 1025 + mod32 %r1, 16 + fail_ne32 %r1, 1 + + ;; mod is unsigned + mov32 %r1, 1025 + mod32 %r1, -16 ; when unsigned, much larger than 1025 + fail_ne32 %r1, 1025 + + mov32 %r1, -25 ; when unsigned, a large positive which is + mov32 %r2, 5 ; ... not evenly divisible by 5 + mod32 %r1, %r2 + fail_ne32 %r1, 1 + + ;; xor + xor32 %r1, %r2 + fail_ne32 %r1, 4 + xor32 %r1, 0xF000000F + fail_ne %r1, 0xF000000B ; Note: check for (bad) sign-extend + xor32 %r1, %r1 + fail_ne %r1, 0 + + ;; neg + mov32 %r1, -1 + mov32 %r2, 0x7fffffff + neg32 %r1 + neg32 %r2 + fail_ne32 %r1, 1 + fail_ne %r2, 0x80000001 ; Note: check for (bad) sign-extend + neg32 %r2 + fail_ne32 %r2, 0x7fffffff + + pass diff --git a/sim/testsuite/bpf/endbe.s b/sim/testsuite/bpf/endbe.s new file mode 100644 index 0000000..2f662ae --- /dev/null +++ b/sim/testsuite/bpf/endbe.s @@ -0,0 +1,46 @@ +# mach: bpf +# as: --EB +# ld: --EB +# sim: -E big +# output: pass\nexit 0 (0x0)\n +;;; endbe.s +;;; Tests for BPF endianness-conversion instructions in simulator +;;; running in BIG ENDIAN +;;; +;;; Both 'be' and 'le' ISAs have both endbe and endle instructions. + + .include "testutils.inc" + + .text + .global main + .type main, @function +main: + lddw %r1, 0x12345678deadbeef + endle %r1, 64 + fail_ne %r1, 0xefbeadde78563412 + endle %r1, 64 + fail_ne %r1, 0x12345678deadbeef + + ;; `bitsize` < 64 will truncate + endle %r1, 32 + fail_ne %r1, 0xefbeadde + endle %r1, 32 + fail_ne %r1, 0xdeadbeef + + endle %r1, 16 + fail_ne %r1, 0xefbe + endle %r1, 16 + fail_ne %r1, 0xbeef + + ;; endbe on be should be noop (except truncate) + lddw %r1, 0x12345678deadbeef + endbe %r1, 64 + fail_ne %r1, 0x12345678deadbeef + + endbe %r1, 32 + fail_ne %r1, 0xdeadbeef + + endbe %r1, 16 + fail_ne %r1, 0xbeef + + pass diff --git a/sim/testsuite/bpf/endle.s b/sim/testsuite/bpf/endle.s new file mode 100644 index 0000000..d8f5ceb --- /dev/null +++ b/sim/testsuite/bpf/endle.s @@ -0,0 +1,43 @@ +# mach: bpf +# output: pass\nexit 0 (0x0)\n +;;; endle.s +;;; Tests for BPF endianness-conversion instructions in simulator +;;; running in LITTLE ENDIAN +;;; +;;; Both 'be' and 'le' ISAs have both endbe and endle instructions. + + .include "testutils.inc" + + .text + .global main + .type main, @function +main: + lddw %r1, 0x12345678deadbeef + endbe %r1, 64 + fail_ne %r1, 0xefbeadde78563412 + endbe %r1, 64 + fail_ne %r1, 0x12345678deadbeef + + ;; `bitsize` < 64 will truncate + endbe %r1, 32 + fail_ne %r1, 0xefbeadde + endbe %r1, 32 + fail_ne %r1, 0xdeadbeef + + endbe %r1, 16 + fail_ne %r1, 0xefbe + endbe %r1, 16 + fail_ne %r1, 0xbeef + + ;; endle on le should be noop (except truncate) + lddw %r1, 0x12345678deadbeef + endle %r1, 64 + fail_ne %r1, 0x12345678deadbeef + + endle %r1, 32 + fail_ne %r1, 0xdeadbeef + + endle %r1, 16 + fail_ne %r1, 0xbeef + + pass diff --git a/sim/testsuite/bpf/jmp.s b/sim/testsuite/bpf/jmp.s new file mode 100644 index 0000000..5ab5de0 --- /dev/null +++ b/sim/testsuite/bpf/jmp.s @@ -0,0 +1,120 @@ +# mach: bpf +# output: pass\nexit 0 (0x0)\n +;;; jmp.s +;;; Tests for eBPF JMP instructions in simulator + + .include "testutils.inc" + + .text + .global main + .type main, @function +main: + mov %r1, 5 + mov %r2, 2 + mov %r3, 7 + mov %r4, -1 + + ;; ja - jump absolute (unconditional) + ja 2f +1: fail + +2: ;; jeq - jump eq + jeq %r1, 4, 1b ; no + jeq %r1, %r2, 1b ; no + jeq %r1, 5, 2f ; yes + fail +2: jeq %r1, %r1, 2f ; yes + fail + +2: ;; jgt - jump (unsigned) greater-than + jgt %r1, 6, 1b ; no + jgt %r1, -5, 1b ; no - unsigned + jgt %r1, %r4, 1b ; no - unsigned + jgt %r1, 4, 2f ; yes + fail +2: jgt %r1, %r2, 2f ; yes + fail + +2: ;; jge - jump (unsigned) greater-than-or-equal-to + jge %r1, 6, 1b ; no + jge %r1, 5, 2f ; yes + fail +2: jge %r1, %r3, 1b ; no + jge %r1, -5, 1b ; no - unsigned + jge %r1, %r2, 2f ; yes + fail + +2: ;; jlt - jump (unsigned) less-than + jlt %r1, 5, 1b ; no + jlt %r1, %r2, 1b ; no + jlt %r4, %r1, 1b ; no - unsigned + jlt %r1, 6, 2f ; yes + fail +2: + jlt %r1, %r3, 2f ; yes + fail + +2: ;; jle - jump (unsigned) less-than-or-equal-to + jle %r1, 4, 1b ; no + jle %r1, %r2, 1b ; no + jle %r4, %r1, 1b ; no + jle %r1, 5, 2f ; yes + fail +2: jle %r1, %r1, 2f ; yes + fail + +2: ;; jset - jump "test" (AND) + jset %r1, 2, 1b ; no (5 & 2 = 0) + jset %r1, %r2, 1b ; no (same) + jset %r1, 4, 2f ; yes (5 & 4 != 0) + fail + +2: ;; jne - jump not-equal-to + jne %r1, 5, 1b ; no + jne %r1, %r1, 1b ; no + jne %r1, 6, 2f ; yes + fail +2: jne %r1, %r4, 2f ; yes + fail + +2: ;; jsgt - jump (signed) greater-than + jsgt %r1, %r3, 1b ; no + jsgt %r1, %r1, 1b ; no + jsgt %r1, 5, 1b ; no + jsgt %r1, -4, 2f ; yes + fail +2: jsgt %r1, %r4, 2f ; yes + fail + +2: ;; jsge - jump (signed) greater-than-or-equal-to + jsge %r1, %r3, 1b ; no + jsge %r1, %r1, 2f ; yes + fail +2: jsge %r1, 7, 1b ; no + jsge %r1, -4, 2f ; yes + fail +2: jsge %r1, %r4, 2f ; yes + fail + +2: ;; jslt - jump (signed) less-than + jslt %r1, 5, 1b ; no + jslt %r1, %r2, 1b ; no + jslt %r4, %r1, 2f ; yes + fail +2: jslt %r1, 6, 2f ; yes + fail +2: jslt %r1, %r3, 2f ; yes + fail + +2: ;; jsle - jump (signed) less-than-or-equal-to + jsle %r1, 4, 1b ; no + jsle %r1, %r2, 1b ; no + jsle %r4, %r1, 2f ; yes + fail +2: jsle %r1, 5, 2f ; yes + fail +2: jsle %r1, %r3, 2f ; yes + fail + +2: + pass diff --git a/sim/testsuite/bpf/jmp32.s b/sim/testsuite/bpf/jmp32.s new file mode 100644 index 0000000..a6074cd --- /dev/null +++ b/sim/testsuite/bpf/jmp32.s @@ -0,0 +1,120 @@ +# mach: bpf +# output: pass\nexit 0 (0x0)\n +;;; jmp32.s +;;; Tests for eBPF JMP32 instructions in simulator + + .include "testutils.inc" + + .text + .global main + .type main, @function +main: + mov32 %r1, 5 + mov32 %r2, 2 + mov32 %r3, 7 + mov32 %r4, -1 + + ;; ja - jump absolute (unconditional) + ja 2f +1: fail + +2: ;; jeq - jump eq + jeq32 %r1, 4, 1b ; no + jeq32 %r1, %r2, 1b ; no + jeq32 %r1, 5, 2f ; yes + fail +2: jeq32 %r1, %r1, 2f ; yes + fail + +2: ;; jgt - jump (unsigned) greater-than + jgt32 %r1, 6, 1b ; no + jgt32 %r1, -5, 1b ; no - unsigned + jgt32 %r1, %r4, 1b ; no - unsigned + jgt32 %r1, 4, 2f ; yes + fail +2: jgt32 %r1, %r2, 2f ; yes + fail + +2: ;; jge - jump (unsigned) greater-than-or-equal-to + jge32 %r1, 6, 1b ; no + jge32 %r1, 5, 2f ; yes + fail +2: jge32 %r1, %r3, 1b ; no + jge32 %r1, -5, 1b ; no - unsigned + jge32 %r1, %r2, 2f ; yes + fail + +2: ;; jlt - jump (unsigned) less-than + jlt32 %r1, 5, 1b ; no + jlt32 %r1, %r2, 1b ; no + jlt32 %r4, %r1, 1b ; no - unsigned + jlt32 %r1, 6, 2f ; yes + fail +2: + jlt32 %r1, %r3, 2f ; yes + fail + +2: ;; jle - jump (unsigned) less-than-or-equal-to + jle32 %r1, 4, 1b ; no + jle32 %r1, %r2, 1b ; no + jle32 %r4, %r1, 1b ; no + jle32 %r1, 5, 2f ; yes + fail +2: jle32 %r1, %r1, 2f ; yes + fail + +2: ;; jset - jump "test" (AND) + jset32 %r1, 2, 1b ; no (5 & 2 = 0) + jset32 %r1, %r2, 1b ; no (same) + jset32 %r1, 4, 2f ; yes (5 & 4 != 0) + fail + +2: ;; jne - jump not-equal-to + jne32 %r1, 5, 1b ; no + jne32 %r1, %r1, 1b ; no + jne32 %r1, 6, 2f ; yes + fail +2: jne32 %r1, %r4, 2f ; yes + fail + +2: ;; jsgt - jump (signed) greater-than + jsgt32 %r1, %r3, 1b ; no + jsgt32 %r1, %r1, 1b ; no + jsgt32 %r1, 5, 1b ; no + jsgt32 %r1, -4, 2f ; yes + fail +2: jsgt32 %r1, %r4, 2f ; yes + fail + +2: ;; jsge - jump (signed) greater-than-or-equal-to + jsge32 %r1, %r3, 1b ; no + jsge32 %r1, %r1, 2f ; yes + fail +2: jsge32 %r1, 7, 1b ; no + jsge32 %r1, -4, 2f ; yes + fail +2: jsge32 %r1, %r4, 2f ; yes + fail + +2: ;; jslt - jump (signed) less-than + jslt32 %r1, 5, 1b ; no + jslt32 %r1, %r2, 1b ; no + jslt32 %r4, %r1, 2f ; yes + fail +2: jslt32 %r1, 6, 2f ; yes + fail +2: jslt32 %r1, %r3, 2f ; yes + fail + +2: ;; jsle - jump (signed) less-than-or-equal-to + jsle32 %r1, 4, 1b ; no + jsle32 %r1, %r2, 1b ; no + jsle32 %r4, %r1, 2f ; yes + fail +2: jsle32 %r1, 5, 2f ; yes + fail +2: jsle32 %r1, %r3, 2f ; yes + fail + +2: + pass diff --git a/sim/testsuite/bpf/ldabs.s b/sim/testsuite/bpf/ldabs.s new file mode 100644 index 0000000..ae777f1 --- /dev/null +++ b/sim/testsuite/bpf/ldabs.s @@ -0,0 +1,87 @@ +# mach: bpf +# sim: --skb-data-offset=0x20 +# output: pass\nexit 0 (0x0)\n +;;; ldabs.s +;;; Tests for non-generic BPF load instructions in simulator. +;;; These instructions (ld{abs,ind}{b,h,w,dw}) are used to access +;;; kernel socket data from BPF programs for high performance filters. +;;; +;;; Register r6 is an implicit input holding a pointer to a struct sk_buff. +;;; Register r0 is an implicit output, holding the fetched data. +;;; +;;; e.g. +;;; ldabsw means: +;;; r0 = ntohl (*(u32 *) (((struct sk_buff *)r6)->data + imm32)) +;;; +;;; ldindw means +;;; r0 = ntohl (*(u32 *) (((struct sk_buff *)r6)->data + src_reg + imm32)) + + .include "testutils.inc" + + .text + .global main + .type main, @function +main: + ;; R6 holds a pointer to a struct sk_buff, which we pretend + ;; exists at 0x1000 + mov %r6, 0x1000 + + ;; We configure skb-data-offset=0x20 + ;; This specifies offsetof(struct sk_buff, data), where the field 'data' + ;; is a pointer a data buffer, in this case at 0x2000 + stw [%r6+0x20], 0x2000 + + ;; Write the value 0x7eadbeef into memory at 0x2004 + ;; i.e. offset 4 within the data buffer pointed to by + ;; ((struct sk_buff *)r6)->data + stw [%r6+0x1004], 0xdeadbeef + + ;; Now load data[4] into r0 using the ldabsw instruction + ldabsw 0x4 + + ;; ...and compare to what we expect + fail_ne32 %r0, 0xdeadbeef + + ;; Repeat for a half-word (2-bytes) + sth [%r6+0x1008], 0x1234 + ldabsh 0x8 + fail_ne32 %r0, 0x1234 + + ;; Repeat for a single byte + stb [%r6+0x1010], 0x5a + ldabsb 0x10 + fail_ne32 %r0, 0x5a + + ;; Repeat for a double-word (8-byte) + ;; (note: fail_ne macro uses r0, so copy to another r1 to compare) + lddw %r2, 0x1234deadbeef5678 + stxdw [%r6+0x1018], %r2 + ldabsdw 0x18 + mov %r1, %r0 + fail_ne %r1, 0x1234deadbeef5678 + + ;; Now, we do the same for the indirect loads + mov %r7, 0x100 + stw [%r6+0x1100], 0xfeedbeef + + ldindw %r7, 0x0 + fail_ne32 %r0, 0xfeedbeef + + ;; half-word + sth [%r6+0x1104], 0x6789 + ldindh %r7, 0x4 + fail_ne32 %r0, 0x6789 + + ;; byte + stb [%r6+0x1108], 0x5f + ldindb %r7, 0x8 + fail_ne32 %r0, 0x5f + + ;; double-word + lddw %r2, 0xcafe12345678d00d + stxdw [%r6+0x1110], %r2 + ldinddw %r7, 0x10 + mov %r1, %r0 + fail_ne %r1, 0xcafe12345678d00d + + pass diff --git a/sim/testsuite/bpf/mem.s b/sim/testsuite/bpf/mem.s new file mode 100644 index 0000000..f9c6a19 --- /dev/null +++ b/sim/testsuite/bpf/mem.s @@ -0,0 +1,56 @@ +# mach: bpf +# output: pass\nexit 0 (0x0)\n +;;; mem.s +;;; Tests for BPF memory (ldx, stx, ..) instructions in simulator + + .include "testutils.inc" + + .text + .global main + .type main, @function +main: + lddw %r1, 0x1234deadbeef5678 + mov %r2, 0x1000 + + ;; basic store/load check + stxb [%r2+0], %r1 + stxh [%r2+2], %r1 + stxw [%r2+4], %r1 + stxdw [%r2+8], %r1 + + stb [%r2+16], 0x5a + sth [%r2+18], 0xcafe + stw [%r2+20], 0xbeefface + stdw [%r2+24], 0x7eadbeef + + ldxb %r1, [%r2+16] + fail_ne %r1, 0x5a + ldxh %r1, [%r2+18] + fail_ne %r1, 0xffffffffffffcafe + ldxw %r1, [%r2+20] + fail_ne %r1, 0xffffffffbeefface + ldxdw %r1, [%r2+24] + fail_ne %r1, 0x7eadbeef + + ldxb %r3, [%r2+0] + fail_ne %r3, 0x78 + ldxh %r3, [%r2+2] + fail_ne %r3, 0x5678 + ldxw %r3, [%r2+4] + fail_ne %r3, 0xffffffffbeef5678 + ldxdw %r3, [%r2+8] + fail_ne %r3, 0x1234deadbeef5678 + + ldxw %r4, [%r2+10] + fail_ne %r4, 0xffffffffdeadbeef + + ;; negative offsets + add %r2, 16 + ldxh %r5, [%r2+-14] + fail_ne %r5, 0x5678 + ldxw %r5, [%r2+-12] + fail_ne %r5, 0xffffffffbeef5678 + ldxdw %r5, [%r2+-8] + fail_ne %r5, 0x1234deadbeef5678 + + pass diff --git a/sim/testsuite/bpf/mov.s b/sim/testsuite/bpf/mov.s new file mode 100644 index 0000000..6665450 --- /dev/null +++ b/sim/testsuite/bpf/mov.s @@ -0,0 +1,54 @@ +# mach: bpf +# output: pass\nexit 0 (0x0)\n +;; mov.s +;; Tests for mov and mov32 instructions + + .include "testutils.inc" + + .text + .global main + .type main, @function +main: + ;; some basic sanity checks + mov32 %r1, 5 + fail_ne %r1, 5 + + mov32 %r2, %r1 + fail_ne %r2, 5 + + mov %r2, %r1 + fail_ne %r2, 5 + + mov %r1, -666 + fail_ne %r1, -666 + + ;; should NOT sign extend + mov32 %r1, -1 + fail_ne %r1, 0x00000000ffffffff + + ;; should sign extend + mov %r2, -1 + fail_ne %r2, 0xffffffffffffffff + + mov %r3, 0x80000000 + + ;; should NOT sign extend + mov32 %r4, %r3 + fail_ne %r4, 0x0000000080000000 + + ;; should sign extend + mov %r5, %r3 + fail_ne %r5, 0xffffffff80000000 + + mov32 %r1, -2147483648 + mov32 %r1, %r1 + fail_ne32 %r1, -2147483648 + + ;; casting shenanigans + mov %r1, %r1 + fail_ne %r1, +2147483648 + mov32 %r2, -1 + mov %r2, %r2 + fail_ne %r2, +4294967295 + + pass diff --git a/sim/testsuite/bpf/testutils.inc b/sim/testsuite/bpf/testutils.inc new file mode 100644 index 0000000..d3d6b17 --- /dev/null +++ b/sim/testsuite/bpf/testutils.inc @@ -0,0 +1,38 @@ + + ;; Print "pass\n" and 'exit 0' + .macro pass + .data +mpass: + .string "pass\n" + .text +_pass: + mov %r1, mpass ; point to "pass\n" string + mov %r2, 5 ; strlen mpass + call 7 ; printk + mov %r0, 0 ; + exit ; exit 0 + .endm + +;;; MACRO fail +;;; Exit with status 1 + .macro fail + mov %r0, 1 + exit + .endm + +;;; MACRO fail_ne32 +;;; Exit with status 1 if \reg32 != \val + .macro fail_ne32 reg val + jeq32 \reg, \val, 2 + mov %r0, 1 + exit + .endm + +;;; MACRO fail_ne +;;; Exit with status1 if \reg ne \val + .macro fail_ne reg val + lddw %r0, \val + jeq \reg, %r0, 2 + mov %r0, 1 + exit + .endm diff --git a/sim/testsuite/bpf/xadd.s b/sim/testsuite/bpf/xadd.s new file mode 100644 index 0000000..be60714 --- /dev/null +++ b/sim/testsuite/bpf/xadd.s @@ -0,0 +1,44 @@ +# mach: bpf +# output: pass\nexit 0 (0x0)\n +;;; xadd.s +;;; Tests for BPF atomic exchange-and-add instructions in simulator +;;; +;;; The xadd instructions (XADDW, XADDDW) operate on a memory location +;;; specified in $dst + offset16, atomically adding the value in $src. +;;; +;;; In the simulator, there isn't anything else happening. The atomic +;;; instructions are identical to a non-atomic load/add/store. + + .include "testutils.inc" + + .text + .global main + .type main, @function +main: + mov %r1, 0x1000 + mov %r2, 5 + + ;; basic xadd w + stw [%r1+0], 10 + xaddw [%r1+0], %r2 + ldxw %r3, [%r1+0] + fail_ne %r3, 15 + + ;; basic xadd dw + stdw [%r1+8], 42 + xadddw [%r1+8], %r2 + ldxdw %r3, [%r1+8] + fail_ne %r3, 47 + + ;; xadd w negative value + mov %r4, -1 + xaddw [%r1+0], %r4 + ldxw %r3, [%r1+0] + fail_ne %r3, 14 + + ;; xadd dw negative val + xadddw [%r1+8], %r4 + ldxdw %r3, [%r1+8] + fail_ne %r3, 46 + + pass diff --git a/sim/testsuite/cr16/ChangeLog b/sim/testsuite/cr16/ChangeLog new file mode 100644 index 0000000..4cb008b --- /dev/null +++ b/sim/testsuite/cr16/ChangeLog @@ -0,0 +1,51 @@ +2015-12-24 Mike Frysinger + + * allinsn.exp: Append --load-vma to global_sim_options. + * misc.exp: Likewise. + +2015-03-29 Mike Frysinger + + PR sim/12385 + * testutils.inc (START): Add _start symbol. + +2008-05-02 M R Swami Reddy + + * cbitb.cgs, cbitw.cgs, sbitb.cgs, sbitw.cgs, tbit.cgs, tbitb.cgs, + tbitw.cgs, hw-trap.ms, uread16.ms, uread32.ms: New testcases. + addb.cgs, addd.cgs, addi.cgs, andb.cgs, andd.cgs, andw.cgs, ashub.cgs, + ashub_i.cgs, ashud.cgs, ashud_i.cgs, ashuw.cgs, ashuw_i.cgs, cmpi.cgs, + cmpw.cgs, jlt.cgs, jump.cgs, loadd.cgs, loadw.cgs, lshb.cgs, lshb_i.cgs, + lshd.cgs, lshd_i.cgs, lshw.cgs, lshw_i.cgs, movb.cgs, movd.cgs, + movw.cgs, movxb.cgs, movxw.cgs, movzb.cgs, movzw.cgs, mulb.cgs, + muluw.cgs, mulw.cgs, orb.cgs, ord.cgs, orw.cgs, pop1.cgs, pop2.cgs, + pop3.cgs, popret1.cgs, popret2.cgs, popret3.cgs, push1.cgs, push2.cgs, + push3.cgs: Update testcase comment. + bnc8.cgs, bnc24.cgs and ret.cgs: Removed. + +2008-04-08 M R Swami Reddy + + * allinsn.exp: Remove target_alias and global_ld_options. + +2008-02-12 M R Swami Reddy + + * allinsn.exp, misc.exp: New files: Test scripts + testutils.inc: New file: Test macros. + addb.cgs, addd.cgs, addi.cgs, addw.cgs, andb.cgs, andd.cgs, andw.cgs, + ashub.cgs, ashub_i.cgs, ashud.cgs, ashud_i.cgs, ashuw.cgs, ashuw_i.cgs, + bal1_24.cgs, bal2_24.cgs, bcc.cgs, bcs.cgs, beq0b.cgs, beq0w.cgs, + beq.cgs, bge.cgs, bgt.cgs, bhi.cgs, bhs.cgs, bht.cgs, blo.cgs, bls.cgs, + blt.cgs, bnc24.cgs, bnc8.cgs, bne0b.cgs, bne0w.cgs, bne.cgs, br.cgs, + cmpb.cgs, cmpb_i.cgs, cmpd.cgs, cmpd_i.cgs, cmpi.cgs, cmpw.cgs, + cmpw_i.cgs, excp.cgs, hello.ms, jal.cgs, jcc.cgs, jcs.cgs, jeq.cgs, + jfc.cgs, jfs.cgs, jge.cgs, jgt.cgs, jhi.cgs, jhs.cgs, jlo.cgs, jls.cgs, + jlt.cgs, jne.cgs, jump.cgs, loadb.cgs, loadd.cgs, loadm.cgs, loadmp.cgs, + loadw.cgs, lprd-sprd.cgs, lpr-spr.cgs, lshb.cgs, lshb_i.cgs, lshd.cgs, + lshd_i.cgs, lshw.cgs, lshw_i.cgs, macqw.cgs, macsw.cgs, macuw.cgs, + movb.cgs, movd.cgs, movw.cgs, movxb.cgs, movxw.cgs, movzb.cgs, + movzw.cgs, mulb.cgs, mulsb.cgs, mulsw.cgs, muluw.cgs, mulw.cgs, + nop.cgs, orb.cgs, ord.cgs, orw.cgs, pop1.cgs, pop2.cgs, pop3.cgs, + popret1.cgs, popret2.cgs, popret3.cgs, push1.cgs, push2.cgs, push3.cgs, + ret.cgs, scc.cgs, scs.cgs, seq.cgs, sfc.cgs, sfs.cgs, sge.cgs, sgt.cgs, + shi.cgs, shs.cgs, slo.cgs, sls.cgs, slt.cgs, sne.cgs, storb.cgs, + stord.cgs, storw.cgs, subb.cgs, subd.cgs, subi.cgs, subw.cgs, + xorb.cgs, xord.cgs, xorw.cgs: New files diff --git a/sim/testsuite/cr16/addb.cgs b/sim/testsuite/cr16/addb.cgs new file mode 100644 index 0000000..272804a --- /dev/null +++ b/sim/testsuite/cr16/addb.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for addb $sr, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global add +add: + + movb $0x1234,r4 + movb $0x1234,r5 + addb r4, r5 + test_h_gr r5, 0x68 + + pass diff --git a/sim/testsuite/cr16/addd.cgs b/sim/testsuite/cr16/addd.cgs new file mode 100644 index 0000000..c13164d --- /dev/null +++ b/sim/testsuite/cr16/addd.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for addd $sr, regp +# mach(): cr16 + + .include "testutils.inc" + + start + + .global addd +addd: + + movd $0x12345678,(r4,r3) + addd $0x44444444,(r4,r3) + + test_h_grp "(r4,r3)", 0x56789abc + + pass diff --git a/sim/testsuite/cr16/addi.cgs b/sim/testsuite/cr16/addi.cgs new file mode 100644 index 0000000..dae8941 --- /dev/null +++ b/sim/testsuite/cr16/addi.cgs @@ -0,0 +1,30 @@ +# cr16 testcase for addi $imm8, $dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global addi +addi: + + movb $1, r4 + addb $2, r4 + + cmpb $3,r4 + bne not_ok + + movw $0x1234, r5 + addw $0x1234, r5 + test_h_gr r5, 0x2468 + + pass + + movd $0x12345678, (r5,r4) + addd $0x12345678, (r5,r4) + test_h_grp "(r5,r4)", 0x2468acf0 + + pass + +not_ok: + fail diff --git a/sim/testsuite/cr16/addw.cgs b/sim/testsuite/cr16/addw.cgs new file mode 100644 index 0000000..866349c --- /dev/null +++ b/sim/testsuite/cr16/addw.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for addw $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global addw +addw: + + movw $0x1234,r4 + addw $0x1234,r4 + + test_h_gr r4, 0x2468 + + pass diff --git a/sim/testsuite/cr16/allinsn.exp b/sim/testsuite/cr16/allinsn.exp new file mode 100644 index 0000000..852a673 --- /dev/null +++ b/sim/testsuite/cr16/allinsn.exp @@ -0,0 +1,31 @@ +# CR16 simulator testsuite. + +if [istarget cr16*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "cr16" + + global global_sim_options + if ![info exists global_sim_options] { + set global_sim_options "" + } + set saved_global_sim_options $global_sim_options + # The cr16 linker sets the default LMA base to 0, and all the code + # expects the VMA when running, so use that when running the tests. + set global_sim_options "$saved_global_sim_options --load-vma" + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } + + set global_sim_options $saved_global_sim_options +} diff --git a/sim/testsuite/cr16/andb.cgs b/sim/testsuite/cr16/andb.cgs new file mode 100644 index 0000000..bc201ad --- /dev/null +++ b/sim/testsuite/cr16/andb.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for and $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global and +and: + movb $3, r4 + movb $6, r5 + + andb r4,r5 + + test_h_gr r5, 2 + + pass diff --git a/sim/testsuite/cr16/andd.cgs b/sim/testsuite/cr16/andd.cgs new file mode 100644 index 0000000..8e72bae --- /dev/null +++ b/sim/testsuite/cr16/andd.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for and $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global and +and: + movd $0x33333333, (r4,r3) + movd $0x66666666, (r6,r5) + + andd (r4,r3), (r6,r5) + + test_h_grp "(r6,r5)", 0x22222222 + + pass diff --git a/sim/testsuite/cr16/andw.cgs b/sim/testsuite/cr16/andw.cgs new file mode 100644 index 0000000..d2d634a --- /dev/null +++ b/sim/testsuite/cr16/andw.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for and $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global and +and: + movw $3, r4 + movw $6, r5 + + andw r4, r5 + + test_h_gr r5, 2 + + pass diff --git a/sim/testsuite/cr16/ashub.cgs b/sim/testsuite/cr16/ashub.cgs new file mode 100644 index 0000000..ef3e94e --- /dev/null +++ b/sim/testsuite/cr16/ashub.cgs @@ -0,0 +1,26 @@ +# cr16 testcase for ashub $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ashub +ashub: + + movw $0x12f1, r4 + movw $4,r5 + ashub r5, r4 + + cmpw $0x1210, r4 + beq ok +not_ok: + fail +ok: + movw $0x12f1, r4 + movw $-4,r5 + ashub r5, r4 + + test_h_gr r4, 0x12ff + + pass diff --git a/sim/testsuite/cr16/ashub_i.cgs b/sim/testsuite/cr16/ashub_i.cgs new file mode 100644 index 0000000..b4765a4 --- /dev/null +++ b/sim/testsuite/cr16/ashub_i.cgs @@ -0,0 +1,24 @@ +# cr16 testcase for ashub $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ashub +ashub: + + movw $0x12f1, r4 + ashub $4, r4 + + cmpw $0x1210, r4 + beq ok +not_ok: + fail +ok: + movw $0x12f1, r4 + ashub $-4, r4 + + test_h_gr r4, 0x12ff + + pass diff --git a/sim/testsuite/cr16/ashud.cgs b/sim/testsuite/cr16/ashud.cgs new file mode 100644 index 0000000..c9511da --- /dev/null +++ b/sim/testsuite/cr16/ashud.cgs @@ -0,0 +1,26 @@ +# cr16 testcase for ashud $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ashud +ashud: + + movd $0xf1234567, (r4,r3) + movw $20,r5 + ashud r5, (r4,r3) + + cmpd $0x56700000, (r4,r3) + beq ok +not_ok: + fail +ok: + movd $0xf1234567, (r4,r3) + movw $-20,r5 + ashud r5, (r4,r3) + + test_h_grp "(r4,r3)", -238 + + pass diff --git a/sim/testsuite/cr16/ashud_i.cgs b/sim/testsuite/cr16/ashud_i.cgs new file mode 100644 index 0000000..3beb4e3 --- /dev/null +++ b/sim/testsuite/cr16/ashud_i.cgs @@ -0,0 +1,24 @@ +# cr16 testcase for ashud $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ashud +ashud: + + movd $0xf1234567, (r4,r3) + ashud $20, (r4,r3) + + cmpd $0x56700000, (r4,r3) + beq ok +not_ok: + fail +ok: + movd $0xf1234567, (r4,r3) + ashud $-20, (r4,r3) + + test_h_grp "(r4,r3)", -238 + + pass diff --git a/sim/testsuite/cr16/ashuw.cgs b/sim/testsuite/cr16/ashuw.cgs new file mode 100644 index 0000000..8f52e35 --- /dev/null +++ b/sim/testsuite/cr16/ashuw.cgs @@ -0,0 +1,26 @@ +# cr16 testcase for ashuw $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ashuw +ashuw: + + movw $0x1ff1, r4 + movw $12,r5 + ashuw r5, r4 + + cmpw $0x1000, r4 + beq ok +not_ok: + fail +ok: + movw $0x1ff1, r4 + movw $-12,r5 + ashuw r5, r4 + + test_h_gr r4, 0x1 + + pass diff --git a/sim/testsuite/cr16/ashuw_i.cgs b/sim/testsuite/cr16/ashuw_i.cgs new file mode 100644 index 0000000..9925914 --- /dev/null +++ b/sim/testsuite/cr16/ashuw_i.cgs @@ -0,0 +1,24 @@ +# cr16 testcase for ashuw $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ashuw +ashuw: + + movw $0x1ff1, r4 + ashuw $12, r4 + + cmpw $0x1000, r4 + beq ok +not_ok: + fail +ok: + movw $0x1ff1, r4 + ashuw $-12, r4 + + test_h_gr r4, 0x1 + + pass diff --git a/sim/testsuite/cr16/bal1_24.cgs b/sim/testsuite/cr16/bal1_24.cgs new file mode 100644 index 0000000..a174b31 --- /dev/null +++ b/sim/testsuite/cr16/bal1_24.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for bal $disp24 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bal24 +bal24: + bal (ra), ok + + fail + +ok: + pass diff --git a/sim/testsuite/cr16/bal2_24.cgs b/sim/testsuite/cr16/bal2_24.cgs new file mode 100644 index 0000000..37cda7f --- /dev/null +++ b/sim/testsuite/cr16/bal2_24.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for bal $disp24 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bal24 +bal24: + bal (r12), ok + + fail + +ok: + pass diff --git a/sim/testsuite/cr16/bcc.cgs b/sim/testsuite/cr16/bcc.cgs new file mode 100644 index 0000000..b0bee2b --- /dev/null +++ b/sim/testsuite/cr16/bcc.cgs @@ -0,0 +1,22 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $12, r4 + movw $10, r5 + cmpw r4, r5 + bcc ok +not_ok: + fail +ok: + movw $11, r5 + cmpw r4, r5 + beq not_ok + + pass diff --git a/sim/testsuite/cr16/bcs.cgs b/sim/testsuite/cr16/bcs.cgs new file mode 100644 index 0000000..0ba14b1 --- /dev/null +++ b/sim/testsuite/cr16/bcs.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for bcs disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bcs +bcs: + mvi_h_condbit 0 + movw $12, r4 + movw $10, r5 + subw r4, r5 + bcs ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/beq.cgs b/sim/testsuite/cr16/beq.cgs new file mode 100644 index 0000000..35ece27 --- /dev/null +++ b/sim/testsuite/cr16/beq.cgs @@ -0,0 +1,22 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $12, r4 + movw $12, r5 + cmpw r4, r5 + beq ok +not_ok: + fail +ok: + movw $11, r5 + cmpw r4, r5 + beq not_ok + + pass diff --git a/sim/testsuite/cr16/beq0b.cgs b/sim/testsuite/cr16/beq0b.cgs new file mode 100644 index 0000000..af6a26b --- /dev/null +++ b/sim/testsuite/cr16/beq0b.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for beq0b reg disp5 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq0b +beq0b: + mvi_h_condbit 0 + movw $0x1200, r4 + beq0b r4, 0x1a +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/beq0w.cgs b/sim/testsuite/cr16/beq0w.cgs new file mode 100644 index 0000000..b3805ac --- /dev/null +++ b/sim/testsuite/cr16/beq0w.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $0, r4 + beq0b r4, 0x1a +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/bge.cgs b/sim/testsuite/cr16/bge.cgs new file mode 100644 index 0000000..bb705e7 --- /dev/null +++ b/sim/testsuite/cr16/bge.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + bgt ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/bgt.cgs b/sim/testsuite/cr16/bgt.cgs new file mode 100644 index 0000000..bb705e7 --- /dev/null +++ b/sim/testsuite/cr16/bgt.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + bgt ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/bhi.cgs b/sim/testsuite/cr16/bhi.cgs new file mode 100644 index 0000000..9a88af7 --- /dev/null +++ b/sim/testsuite/cr16/bhi.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + bhi ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/bhs.cgs b/sim/testsuite/cr16/bhs.cgs new file mode 100644 index 0000000..97dcc55 --- /dev/null +++ b/sim/testsuite/cr16/bhs.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for bhi disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bhi +bhi: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + bhs ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/bht.cgs b/sim/testsuite/cr16/bht.cgs new file mode 100644 index 0000000..39912e2 --- /dev/null +++ b/sim/testsuite/cr16/bht.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + blt ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/blo.cgs b/sim/testsuite/cr16/blo.cgs new file mode 100644 index 0000000..39912e2 --- /dev/null +++ b/sim/testsuite/cr16/blo.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + blt ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/bls.cgs b/sim/testsuite/cr16/bls.cgs new file mode 100644 index 0000000..f394570 --- /dev/null +++ b/sim/testsuite/cr16/bls.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + bls ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/blt.cgs b/sim/testsuite/cr16/blt.cgs new file mode 100644 index 0000000..39912e2 --- /dev/null +++ b/sim/testsuite/cr16/blt.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for beq disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + blt ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/bne.cgs b/sim/testsuite/cr16/bne.cgs new file mode 100644 index 0000000..3740f24 --- /dev/null +++ b/sim/testsuite/cr16/bne.cgs @@ -0,0 +1,22 @@ +# cr16 testcase for bne disp16 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bne +bne: + movw $1, r4 + movw $2, r5 + cmpw r4,r5 + bne test0pass +test1fail: + fail + +test0pass: + movw $1, r5 + cmpw r4,r5 + bne test1fail + + pass diff --git a/sim/testsuite/cr16/bne0b.cgs b/sim/testsuite/cr16/bne0b.cgs new file mode 100644 index 0000000..63f3cad --- /dev/null +++ b/sim/testsuite/cr16/bne0b.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for bne0b reg disp5 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ne0b +bne0b: + mvi_h_condbit 0 + movw $0x1201, r4 + bne0b r4, 0x1a +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/bne0w.cgs b/sim/testsuite/cr16/bne0w.cgs new file mode 100644 index 0000000..f45e399 --- /dev/null +++ b/sim/testsuite/cr16/bne0w.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for bne0w reg disp5 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bne0w +bne0w: + mvi_h_condbit 0 + movw $1, r4 + bne0w r4, 0x1a +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/br.cgs b/sim/testsuite/cr16/br.cgs new file mode 100644 index 0000000..f7ba86d --- /dev/null +++ b/sim/testsuite/cr16/br.cgs @@ -0,0 +1,24 @@ +# cr16 testcase for bc $disp24 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global bc24 +bc24: + + mvi_h_condbit 0 + bne test0fail + br test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bne test1pass + fail +test1pass: + + pass + diff --git a/sim/testsuite/cr16/cbitb.cgs b/sim/testsuite/cr16/cbitb.cgs new file mode 100644 index 0000000..473fd71 --- /dev/null +++ b/sim/testsuite/cr16/cbitb.cgs @@ -0,0 +1,35 @@ +# cr16 testcase for cbitb $bit_pos, ABS/REGP/REG +# mach: cr16 + + .include "testutils.inc" + + start + + .global cbitb +cbitb: + cbitb $0,_y + loadw _y, r1 + cmpb $0xfe, r1 + beq ok1 +not_ok: + fail + +ok1: + movd $_y, (r1,r0) + cbitb $1,0(r1,r0) + loadw _y, r1 + cmpb $0xfc, r1 + beq ok2 + br not_ok +ok2: + + movw $_y, r1 + cbitb $2,0(r1) + loadw _y, r1 + cmpb $0xf8, r1 + beq ok3 + br not_ok +ok3: + pass + +_y: .word 0xff diff --git a/sim/testsuite/cr16/cbitw.cgs b/sim/testsuite/cr16/cbitw.cgs new file mode 100644 index 0000000..a97698c --- /dev/null +++ b/sim/testsuite/cr16/cbitw.cgs @@ -0,0 +1,35 @@ +# cr16 testcase for cbitw +# mach: cr16 + + .include "testutils.inc" + + start + + .global cbitw +cbitw: + cbitw $4,_y + loadw _y, r1 + cmpb $0xef, r1 + beq ok1 +not_ok: + fail + +ok1: + movd $_y, (r1,r0) + cbitw $5,0(r1,r0) + loadw _y, r1 + cmpb $0xcf, r1 + beq ok2 + br not_ok +ok2: + + movw $_y, r1 + cbitw $6,0(r1) + loadw _y, r1 + cmpb $0x8f, r1 + beq ok3 + br not_ok +ok3: + pass + +_y: .word 0xff diff --git a/sim/testsuite/cr16/cmpb.cgs b/sim/testsuite/cr16/cmpb.cgs new file mode 100644 index 0000000..50984bf --- /dev/null +++ b/sim/testsuite/cr16/cmpb.cgs @@ -0,0 +1,23 @@ +# cr16 testcase for cmpb reg1, reg2 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmpb +cmpb: + mvi_h_condbit 0 + movw $0x2311, r4 + movw $0x4211, r5 + cmpb r4,r5 + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + movw $0x4222, r5 + cmpb r4,r5 + beq not_ok + + pass diff --git a/sim/testsuite/cr16/cmpb_i.cgs b/sim/testsuite/cr16/cmpb_i.cgs new file mode 100644 index 0000000..591abe9 --- /dev/null +++ b/sim/testsuite/cr16/cmpb_i.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for cmpb $imm4, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmpb_i +cmpb_i: + mvi_h_condbit 0 + movw $0x2311, r4 + cmpb $0x4211, r4 + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + cmpb $0x4222,r4 + beq not_ok + + pass diff --git a/sim/testsuite/cr16/cmpd.cgs b/sim/testsuite/cr16/cmpd.cgs new file mode 100644 index 0000000..cc9e55d --- /dev/null +++ b/sim/testsuite/cr16/cmpd.cgs @@ -0,0 +1,23 @@ +# cr16 testcase for cmpd (regp), (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmpd +cmpd: + mvi_h_condbit 0 + movd $0x12345678, (r4,r3) + movd $0x12345678, (r6,r5) + cmpd (r4,r3), (r6,r5) + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + movd $0x12341234, (r6,r5) + cmpd (r4,r3), (r6,r5) + beq not_ok + + pass diff --git a/sim/testsuite/cr16/cmpd_i.cgs b/sim/testsuite/cr16/cmpd_i.cgs new file mode 100644 index 0000000..ad6018a --- /dev/null +++ b/sim/testsuite/cr16/cmpd_i.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for cmpb $imm32,(regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmpd_i +cmpd_i: + mvi_h_condbit 0 + movd $0x12345678, (r4,r3) + cmpd $0x12345678, (r4,r3) + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + cmpd $0x12341234, (r4,r3) + beq not_ok + + pass diff --git a/sim/testsuite/cr16/cmpi.cgs b/sim/testsuite/cr16/cmpi.cgs new file mode 100644 index 0000000..cff17e8 --- /dev/null +++ b/sim/testsuite/cr16/cmpi.cgs @@ -0,0 +1,23 @@ +# cr16 testcase for cmpi $imm16, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmpi +cmpi: + mvi_h_condbit 0 + movw $1, r4 + cmpw $1, r4 + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + movw $2, r4 + cmpw $2, r4 + bne not_ok + + + pass diff --git a/sim/testsuite/cr16/cmpw.cgs b/sim/testsuite/cr16/cmpw.cgs new file mode 100644 index 0000000..9d333fb --- /dev/null +++ b/sim/testsuite/cr16/cmpw.cgs @@ -0,0 +1,23 @@ +# cr16 testcase for cmp $imm, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmp +cmp: + mvi_h_condbit 0 + movw $0x1234, r4 + movw $0x1234, r5 + cmpb r4,r5 + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + movw $0x2222, r5 + cmpw r4,r5 + beq not_ok + + pass diff --git a/sim/testsuite/cr16/cmpw_i.cgs b/sim/testsuite/cr16/cmpw_i.cgs new file mode 100644 index 0000000..31f701c --- /dev/null +++ b/sim/testsuite/cr16/cmpw_i.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for cmpw_i $imm16, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global cmpw_i +cmpw_i: + mvi_h_condbit 0 + movw $0x1234, r4 + cmpw $0x1234, r4 + beq ok +not_ok: + fail +ok: + mvi_h_condbit 1 + cmpw $0x2222, r4 + beq not_ok + + pass diff --git a/sim/testsuite/cr16/excp.cgs b/sim/testsuite/cr16/excp.cgs new file mode 100644 index 0000000..82d445a --- /dev/null +++ b/sim/testsuite/cr16/excp.cgs @@ -0,0 +1,110 @@ +# cr16 testcase for excp uimm4 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global excp +excp: + pass # pass macro use the excp 8 + +## Test 1: bbpsw = 0, bpsw = 1, psw = 0 +# +# # bbsm = 0, bie = 0, bbcond = 0 +# movw $0, r4 +# lpr r4, cr8 +# +# # bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 +# movw $0xc100, r4 +# lpr r4, cr0 +# +# # bbpc = 0 +# movw $0, r4 +# mvtc r4, bbpc +# +# # bpc = 42 +# mvaddr_h_gr r4, 42 +# mvtc r4, bpc +# +# # Copy excp2_handler to excp area of memory. +# ld24 r0,#0x48 # address of excp 2 handler +# ld24 r1,#excp2_handler +# ld r2,@r1 +# st r2,@r0 +# # Set up return address. +# ld24 r5,#excp2_ret1 +# +#excp_insn1: +# excp 2 +# fail +# +#excp2_ret1: +# # test bbsm = 1, bbie = 1, bbcond = 1 +# mvfc r4, cr8 +# test_h_gr r4, 0xc1 +# +# # test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0 +# mvfc r4, cr0 +# test_h_gr r4, 0 +# +# # test bbpc = 42 +# mvfc r4, bbpc +# test_h_gr r4, 42 +# +# # test bpc = proper return address +# mvfc r4, bpc +# test_h_gr r4, excp_insn1 + 4 +# +## Test 2: bbpsw = 1, bpsw = 0, psw = 1 +# +# # bbsm = 1, bie = 1, bbcond = 1 +# mvi_h_gr r4, 0xc1 +# mvtc r4, cr8 +# +# # bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 +# mvi_h_gr r4, 0xc1 +# mvtc r4, cr0 +# +# # bbpc = 42 +# mvaddr_h_gr r4, 42 +# mvtc r4, bbpc +# +# # bpc = 0 +# mvaddr_h_gr r4, 0 +# mvtc r4, bpc +# +# # Set up return address. +# ld24 r5,#excp2_ret2 +# +#excp_insn2: +# excp #2 +# fail +# +#excp2_ret2: +# # test bbsm = 0, bbie = 0, bbcond = 0 +# mvfc r4, cr8 +# test_h_gr r4, 0 +# +# # test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0 +# mvfc r4, cr0 +# test_h_gr r4, 0xc180 +# +# # test bbpc = 0 +# mvfc r4, bbpc +# test_h_gr r4, 0 +# +# # test bpc = proper return address +# mvfc r4, bpc +# test_h_gr r4, excp_insn2 + 4 +# +# pass +# +# .data +# +## Don't use rte as it will undo the effects of excp we're testing. +# +# .p2align 2 +#excp2_handler: +# jmp r5 +# nop diff --git a/sim/testsuite/cr16/hello.ms b/sim/testsuite/cr16/hello.ms new file mode 100644 index 0000000..ab6c482 --- /dev/null +++ b/sim/testsuite/cr16/hello.ms @@ -0,0 +1,19 @@ +# output(): Hello world!\n +# mach(): cr16 + + .globl _start +_start: + +# write (hello world) + movw $1,r2 + movd $hello,(r4,r3) + loadw length,r5 + movw $0x404,r0 + excp 8 +# exit (0) + movw $0,r2 + movw $0x410,r0 + excp 8 + +length: .long 14 +hello: .ascii "Hello world!\r\n" diff --git a/sim/testsuite/cr16/hw-trap.ms b/sim/testsuite/cr16/hw-trap.ms new file mode 100644 index 0000000..8c8c185 --- /dev/null +++ b/sim/testsuite/cr16/hw-trap.ms @@ -0,0 +1,10 @@ +# mach(): cr16 + + .include "testutils.inc" + + start + +# perform trap + movw $0,r2 + movw $0x410,r0 + pass # the pass macro use the trap 8 diff --git a/sim/testsuite/cr16/jal.cgs b/sim/testsuite/cr16/jal.cgs new file mode 100644 index 0000000..106c864 --- /dev/null +++ b/sim/testsuite/cr16/jal.cgs @@ -0,0 +1,35 @@ +# cr16 testcase for jal $sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jal +jal: + movd $ok1, (r5, r4) + lshd $-1, (r5,r4) + jal (ra), (r5,r4) +not_ok: + fail +ok1: + movd $not_ok, (r7, r6) + lshd $-1, (r7,r6) + cmpd (r7,r6), (ra) + beq ok2 + br not_ok +ok2: + movd $ok3, (r5, r4) + lshd $-1, (r5,r4) + jal (r1,r0), (r5,r4) +not_ok1: + br not_ok +ok3: + movd $not_ok1, (r7, r6) + lshd $-1, (r7,r6) + cmpd (r7,r6), (r1,r0) + beq ok4 + br not_ok +ok4: + + pass diff --git a/sim/testsuite/cr16/jcc.cgs b/sim/testsuite/cr16/jcc.cgs new file mode 100644 index 0000000..84db77a --- /dev/null +++ b/sim/testsuite/cr16/jcc.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jcc (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jcc +jcc: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $12, r4 + movw $10, r5 + cmpw r4, r5 + jcc (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jcs.cgs b/sim/testsuite/cr16/jcs.cgs new file mode 100644 index 0000000..91d40a3 --- /dev/null +++ b/sim/testsuite/cr16/jcs.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jcs (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jcs +jcs: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $12, r4 + movw $10, r5 + subw r4, r5 + jcs (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jeq.cgs b/sim/testsuite/cr16/jeq.cgs new file mode 100644 index 0000000..824828d --- /dev/null +++ b/sim/testsuite/cr16/jeq.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jeq (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jeq +jeq: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $12, r4 + movw $12, r5 + cmpw r4, r5 + jeq (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jfc.cgs b/sim/testsuite/cr16/jfc.cgs new file mode 100644 index 0000000..0bf1c29 --- /dev/null +++ b/sim/testsuite/cr16/jfc.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jfc (repl) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jfc +jfc: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + subw r4, r5 + jfc (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jfs.cgs b/sim/testsuite/cr16/jfs.cgs new file mode 100644 index 0000000..c14f565 --- /dev/null +++ b/sim/testsuite/cr16/jfs.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jfs (repl) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jfs +jfs: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $0xaa, r4 + movw $0xaa, r5 + addb r4, r5 + jfs (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jge.cgs b/sim/testsuite/cr16/jge.cgs new file mode 100644 index 0000000..685ba4c --- /dev/null +++ b/sim/testsuite/cr16/jge.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jge (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jge +jge: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + jge (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jgt.cgs b/sim/testsuite/cr16/jgt.cgs new file mode 100644 index 0000000..e1bed75 --- /dev/null +++ b/sim/testsuite/cr16/jgt.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jgt (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jgt +jgt: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + jgt (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jhi.cgs b/sim/testsuite/cr16/jhi.cgs new file mode 100644 index 0000000..0959d1d --- /dev/null +++ b/sim/testsuite/cr16/jhi.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jeq (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jeq +jeq: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + jhi (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jhs.cgs b/sim/testsuite/cr16/jhs.cgs new file mode 100644 index 0000000..80a3944 --- /dev/null +++ b/sim/testsuite/cr16/jhs.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jhs (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jhs +jhs: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + subw r4, r5 + jhs (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jlo.cgs b/sim/testsuite/cr16/jlo.cgs new file mode 100644 index 0000000..cf00e3e --- /dev/null +++ b/sim/testsuite/cr16/jlo.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jlo (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jlo +jlo: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + jlo (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jls.cgs b/sim/testsuite/cr16/jls.cgs new file mode 100644 index 0000000..be50f74 --- /dev/null +++ b/sim/testsuite/cr16/jls.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jeq (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jeq +jeq: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + jls (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jlt.cgs b/sim/testsuite/cr16/jlt.cgs new file mode 100644 index 0000000..ca93cf1 --- /dev/null +++ b/sim/testsuite/cr16/jlt.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jlt (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jlt +jlt: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + jlt (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jne.cgs b/sim/testsuite/cr16/jne.cgs new file mode 100644 index 0000000..fb86889 --- /dev/null +++ b/sim/testsuite/cr16/jne.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for jne (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jne +jne: + movd $ok, (r7,r6) + lshd $-1, (r7,r6) + + mvi_h_condbit 0 + movw $0, r4 + movw $1, r5 + cmpw r4, r5 + jne (r7,r6) +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/jump.cgs b/sim/testsuite/cr16/jump.cgs new file mode 100644 index 0000000..df20c15 --- /dev/null +++ b/sim/testsuite/cr16/jump.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for jmp (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global jmp +jmp: + movd $ok1, (r4,r3) + jump (r4,r3) + fail +ok1: + movd $ok2, (r4,r3) + jump (r4,r3) + fail +ok2: + pass diff --git a/sim/testsuite/cr16/loadb.cgs b/sim/testsuite/cr16/loadb.cgs new file mode 100644 index 0000000..c591ec9 --- /dev/null +++ b/sim/testsuite/cr16/loadb.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for loadb $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ldb +ldb: + movd $data_loc, (r4,r3) + movw $0,r5 + + loadb 0(r4,r3),r5 + + test_h_gr r5, 0x78 # little endian processor + + pass + +data_loc: + .word 0x5678 + diff --git a/sim/testsuite/cr16/loadd.cgs b/sim/testsuite/cr16/loadd.cgs new file mode 100644 index 0000000..b6a851d --- /dev/null +++ b/sim/testsuite/cr16/loadd.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for loadd 0(regp),regp +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ldb +ldb: + movd $data_loc, (r4,r3) + movd $0,(r6,r5) + + loadd 0(r4,r3),(r6,r5) + + test_h_grp "(r6, r5)", 0x12345678 # little endian processor + + pass + +data_loc: + .long 0x12345678 + diff --git a/sim/testsuite/cr16/loadm.cgs b/sim/testsuite/cr16/loadm.cgs new file mode 100644 index 0000000..8bd6d11 --- /dev/null +++ b/sim/testsuite/cr16/loadm.cgs @@ -0,0 +1,41 @@ +# cr16 testcase for loadm count +# mach(): cr16 + + .include "testutils.inc" + + start + + .global loadm +loadm: + movw $0x1000, r0 + movw $0x12, r2 + storw r2, 0x1000 + movw $0x34, r3 + storw r3, 0x1002 + movw $0x56, r4 + storw r4, 0x1004 + movw $0x78, r5 + storw r5, 0x1006 + + loadm $4 + + cmpw $0x12,r2 + beq ok1 +not_ok: + fail +ok1: + cmpw $0x34,r3 + beq ok2 + br not_ok +ok2: + cmpw $0x56,r4 + beq ok3 + br not_ok +ok3: + cmpw $0x78,r5 + beq ok4 + br not_ok +ok4: + pass + pass + diff --git a/sim/testsuite/cr16/loadmp.cgs b/sim/testsuite/cr16/loadmp.cgs new file mode 100644 index 0000000..6003c3f --- /dev/null +++ b/sim/testsuite/cr16/loadmp.cgs @@ -0,0 +1,40 @@ +# cr16 testcase for loadmp count +# mach(): cr16 + + .include "testutils.inc" + + start + + .global loadmp +loadmp: + movd $0x1000, (r1,r0) + movw $0x12, r2 + storw r2, 0x1000 + movw $0x34, r3 + storw r3, 0x1002 + movw $0x56, r4 + storw r4, 0x1004 + movw $0x78, r5 + storw r5, 0x1006 + + loadmp $4 + + cmpw $0x12,r2 + beq ok1 +not_ok: + fail +ok1: + cmpw $0x34,r3 + beq ok2 + br not_ok +ok2: + cmpw $0x56,r4 + beq ok3 + br not_ok +ok3: + cmpw $0x78,r5 + beq ok4 + br not_ok +ok4: + pass + diff --git a/sim/testsuite/cr16/loadw.cgs b/sim/testsuite/cr16/loadw.cgs new file mode 100644 index 0000000..8faf616 --- /dev/null +++ b/sim/testsuite/cr16/loadw.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for loadw 0(regp), (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ldb +ldb: + movd $data_loc, (r4,r3) + movw $0,r5 + + loadw 0(r4,r3),r5 + + test_h_gr r5, 0x5678 # little endian processor + + pass + +data_loc: + .word 0x5678 + diff --git a/sim/testsuite/cr16/lpr-spr.cgs b/sim/testsuite/cr16/lpr-spr.cgs new file mode 100644 index 0000000..c2679ea --- /dev/null +++ b/sim/testsuite/cr16/lpr-spr.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for lpr reg, preg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lpr +lpr: + movw $0x1234,r3 + lpr r3, psr + + spr psr,r5 + + + test_h_gr r5, 0x1234 + + pass diff --git a/sim/testsuite/cr16/lprd-sprd.cgs b/sim/testsuite/cr16/lprd-sprd.cgs new file mode 100644 index 0000000..3df8de3 --- /dev/null +++ b/sim/testsuite/cr16/lprd-sprd.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for lprd reg, preg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lprd +lprd: + movd $0x12345678,(r4,r3) + lprd (r4,r3), psr + + sprd psr,(r6,r5) + + + test_h_grp "(r6,r5)", 0x12345678 + + pass diff --git a/sim/testsuite/cr16/lshb.cgs b/sim/testsuite/cr16/lshb.cgs new file mode 100644 index 0000000..59ddbba --- /dev/null +++ b/sim/testsuite/cr16/lshb.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for lshb count, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lshb +lshb: + movb $6, r4 + movb $1, r5 + lshb r5, r4 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/cr16/lshb_i.cgs b/sim/testsuite/cr16/lshb_i.cgs new file mode 100644 index 0000000..10d3085 --- /dev/null +++ b/sim/testsuite/cr16/lshb_i.cgs @@ -0,0 +1,14 @@ +# cr16 testcase for lshb_i $uimm5, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lshb_i +lshb_i: + movb $6,r4 + lshb $1, r4 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/cr16/lshd.cgs b/sim/testsuite/cr16/lshd.cgs new file mode 100644 index 0000000..e146ca1 --- /dev/null +++ b/sim/testsuite/cr16/lshd.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for lshd reg, regp +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lshd +lshd: + movd $0x12345678, (r4,r3) + movw $0x10, r5 + lshd r5, (r4,r3) + test_h_grp "(r4,r3)", 0x56780000 + + pass diff --git a/sim/testsuite/cr16/lshd_i.cgs b/sim/testsuite/cr16/lshd_i.cgs new file mode 100644 index 0000000..aa65933 --- /dev/null +++ b/sim/testsuite/cr16/lshd_i.cgs @@ -0,0 +1,14 @@ +# cr16 testcase for lshb_i $uimm5, regp +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lshb_i +lshb_i: + movd $0x12345678,(r4,r3) + lshd $16, (r4,r3) + test_h_grp "(r4,r3)", 0x56780000 + + pass diff --git a/sim/testsuite/cr16/lshw.cgs b/sim/testsuite/cr16/lshw.cgs new file mode 100644 index 0000000..a10edff --- /dev/null +++ b/sim/testsuite/cr16/lshw.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for lshw reg, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lshw +lshw: + movw $0x1234, r4 + movw $8, r5 + lshw r5, r4 + test_h_gr r4, 0x3400 + + pass diff --git a/sim/testsuite/cr16/lshw_i.cgs b/sim/testsuite/cr16/lshw_i.cgs new file mode 100644 index 0000000..9e94a5e --- /dev/null +++ b/sim/testsuite/cr16/lshw_i.cgs @@ -0,0 +1,14 @@ +# cr16 testcase for lshb_i $uimm4, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global lshb_i +lshb_i: + movw $0x1234,r4 + lshw $8, r4 + test_h_gr r4, 0x3400 + + pass diff --git a/sim/testsuite/cr16/macqw.cgs b/sim/testsuite/cr16/macqw.cgs new file mode 100644 index 0000000..4c6da4f --- /dev/null +++ b/sim/testsuite/cr16/macqw.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for macqw reg, (regp) +# mach(): cr16 + + .include "testutils.inc" + + start # REVIST to update testcase + + .global macqw +macqw: + movw $0x123,r3 + movw $0x456,r4 + macqw r3, r4, (r6,r5) + test_h_grp "(r6,r5)", 0x4edc2 + + pass diff --git a/sim/testsuite/cr16/macsw.cgs b/sim/testsuite/cr16/macsw.cgs new file mode 100644 index 0000000..8a0f227 --- /dev/null +++ b/sim/testsuite/cr16/macsw.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for macsw reg, (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global macsw # REVISIT to update this testcase +macsw: + movw $0x123,r3 + movw $0x456,r4 + macsw r3,r4, (r6,r5) + test_h_grp "(r6,r5)", 0x4edc2 + + pass diff --git a/sim/testsuite/cr16/macuw.cgs b/sim/testsuite/cr16/macuw.cgs new file mode 100644 index 0000000..ea4c3fc --- /dev/null +++ b/sim/testsuite/cr16/macuw.cgs @@ -0,0 +1,15 @@ +# cr16 testcase for macuw reg, reg, (regp) +# mach(): cr16 + + .include "testutils.inc" + + start # REVIST to update testcase + + .global macuw +macuw: + movw $0x123,r3 + movw $0x456,r4 + macuw r3, r4, (r6,r5) + test_h_grp "(r6,r5)", 0x4edc2 + + pass diff --git a/sim/testsuite/cr16/misc.exp b/sim/testsuite/cr16/misc.exp new file mode 100644 index 0000000..39dd3a4 --- /dev/null +++ b/sim/testsuite/cr16/misc.exp @@ -0,0 +1,31 @@ +# Miscellaneous CR16 simulator testcases + +if [istarget cr16*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "cr16" + + global global_sim_options + if ![info exists global_sim_options] { + set global_sim_options "" + } + set saved_global_sim_options $global_sim_options + # The cr16 linker sets the default LMA base to 0, and all the code + # expects the VMA when running, so use that when running the tests. + set global_sim_options "$saved_global_sim_options --load-vma" + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } + + set global_sim_options $saved_global_sim_options +} diff --git a/sim/testsuite/cr16/movb.cgs b/sim/testsuite/cr16/movb.cgs new file mode 100644 index 0000000..fc8fcba --- /dev/null +++ b/sim/testsuite/cr16/movb.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for movb $imm, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movb +movb: + movb $1, r4 + movb $0, r5 + + movb r4, r5 + + test_h_gr r5, 1 + + pass diff --git a/sim/testsuite/cr16/movd.cgs b/sim/testsuite/cr16/movd.cgs new file mode 100644 index 0000000..8b1b638 --- /dev/null +++ b/sim/testsuite/cr16/movd.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for movd $imm32, regp +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movd +movd: + movd $0x12345678, (r4,r3) + + movd (r4,r3), (r6,r5) + + test_h_grp "(r6,r5)", 0x12345678 + + pass diff --git a/sim/testsuite/cr16/movw.cgs b/sim/testsuite/cr16/movw.cgs new file mode 100644 index 0000000..e14afb0 --- /dev/null +++ b/sim/testsuite/cr16/movw.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for movw $imm16, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movw +movw: + movw $0x1234, r4 + + movw r4, r5 + + test_h_gr r5, 0x1234 + + pass diff --git a/sim/testsuite/cr16/movxb.cgs b/sim/testsuite/cr16/movxb.cgs new file mode 100644 index 0000000..3c356c9 --- /dev/null +++ b/sim/testsuite/cr16/movxb.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for movb $imm4, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movb +movb: + movb $0xf, r4 + movw $0x1234, r5 + + movxb r4, r5 + + test_h_gr r5, 0xf + + pass diff --git a/sim/testsuite/cr16/movxw.cgs b/sim/testsuite/cr16/movxw.cgs new file mode 100644 index 0000000..77dea80 --- /dev/null +++ b/sim/testsuite/cr16/movxw.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for movw reg, regp +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movw +movw: + movw $0x1234, r4 + movd $0, (r6,r5) + + movxw r4, (r6,r5) + + test_h_grp "(r6, r5)", 0x1234 + + pass diff --git a/sim/testsuite/cr16/movzb.cgs b/sim/testsuite/cr16/movzb.cgs new file mode 100644 index 0000000..acbe2b6 --- /dev/null +++ b/sim/testsuite/cr16/movzb.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for movzb reg, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movzb +movzb: + movw $0x120f, r4 + movw $0x1200, r5 + + movzb r4, r5 + + test_h_gr r5, 0xf + + pass diff --git a/sim/testsuite/cr16/movzw.cgs b/sim/testsuite/cr16/movzw.cgs new file mode 100644 index 0000000..93855e4 --- /dev/null +++ b/sim/testsuite/cr16/movzw.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for movzw reg, regp +# mach(): cr16 + + .include "testutils.inc" + + start + + .global movzw +movzw: + movb $0xff, r4 + movd $0x12345678,(r6, r5) + + movzw r4, (r6,r5) + + test_h_grp "(r6, r5)", 0xff + + pass diff --git a/sim/testsuite/cr16/mulb.cgs b/sim/testsuite/cr16/mulb.cgs new file mode 100644 index 0000000..c4b859f --- /dev/null +++ b/sim/testsuite/cr16/mulb.cgs @@ -0,0 +1,30 @@ +# cr16 testcase for mulb $imm4/imm16/reg,$reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global mulb +mulb: + movw $0x1234,r4 + movw $0x4567,r5 + + mulb r4, r5 + cmpb $0xec, r5 + beq ok1 +not_ok: + fail + +ok1: + movw $3,r4 + mulb $7,r4 + cmpb $21, r4 + beq ok + br not_ok +ok: + movw $3,r4 + mulb $0x1207, r4 + test_h_gr r4, 21 + + pass diff --git a/sim/testsuite/cr16/mulsb.cgs b/sim/testsuite/cr16/mulsb.cgs new file mode 100644 index 0000000..60912af --- /dev/null +++ b/sim/testsuite/cr16/mulsb.cgs @@ -0,0 +1,24 @@ +# cr16 testcase for mulsb $imm4/imm16/reg, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global mulsb +mulsb: + movw $-3,r4 + movw $7,r5 + + mulsb r4, r5 + cmpw $-21, r5 + beq ok1 +not_ok: + fail + +ok1: + movw $3,r4 + mulw $7, r4 + test_h_gr r4, 21 + + pass diff --git a/sim/testsuite/cr16/mulsw.cgs b/sim/testsuite/cr16/mulsw.cgs new file mode 100644 index 0000000..5bf5ac1 --- /dev/null +++ b/sim/testsuite/cr16/mulsw.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for mulsw reg, (regp) +# mach(): cr16 + + .include "testutils.inc" + + start + + .global mulsw +mulsw: + movw $0xfff,r4 # fix for 0xffff + movd $0xffffffff,(r6,r5) + + mulsw r4, (r6,r5) + test_h_grp "(r6,r5)", 0xfffff001 + + pass diff --git a/sim/testsuite/cr16/muluw.cgs b/sim/testsuite/cr16/muluw.cgs new file mode 100644 index 0000000..71f7ee0 --- /dev/null +++ b/sim/testsuite/cr16/muluw.cgs @@ -0,0 +1,16 @@ +# cr16 testcase for muluw reg, regp +# mach(): cr16 + + .include "testutils.inc" + + start + + .global muluw +muluw: + movw $0xfff,r4 # fix for 0xffff + movd $0xffffffff,(r6,r5) + + muluw r4, (r6,r5) + test_h_grp "(r6,r5)", 0xffef001 + + pass diff --git a/sim/testsuite/cr16/mulw.cgs b/sim/testsuite/cr16/mulw.cgs new file mode 100644 index 0000000..cbd4552 --- /dev/null +++ b/sim/testsuite/cr16/mulw.cgs @@ -0,0 +1,23 @@ +# cr16 testcase for mulw reg reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global mulw +mulw: + movw $0x1234,r4 + movw $0x1234,r5 + + mulw r4, r5 + cmpw $0x5a90, r5 + beq ok1 +not_ok: + fail + +ok1: + mulw $0x1234, r4 + test_h_gr r4, 0x5a90 + + pass diff --git a/sim/testsuite/cr16/nop.cgs b/sim/testsuite/cr16/nop.cgs new file mode 100644 index 0000000..e29fa93 --- /dev/null +++ b/sim/testsuite/cr16/nop.cgs @@ -0,0 +1,11 @@ +# cr16 testcase for nop +# mach(): cr16 + + .include "testutils.inc" + + start + + .global nop +nop: + nop + pass diff --git a/sim/testsuite/cr16/orb.cgs b/sim/testsuite/cr16/orb.cgs new file mode 100644 index 0000000..43ce26b --- /dev/null +++ b/sim/testsuite/cr16/orb.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for orb $imm, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global orb +orb: + movb $3, r4 + movb $6, r5 + + orb r4,r5 + + test_h_gr r5, 7 + + pass diff --git a/sim/testsuite/cr16/ord.cgs b/sim/testsuite/cr16/ord.cgs new file mode 100644 index 0000000..e682d3a --- /dev/null +++ b/sim/testsuite/cr16/ord.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for ord $imm32, regp +# mach(): cr16 + + .include "testutils.inc" + + start + + .global ord +ord: + movd $0x33333333, (r4,r3) + movd $0x66666666, (r6,r5) + + ord (r4,r3), (r6,r5) + + test_h_grp "(r6,r5)", 0x77777777 + + pass diff --git a/sim/testsuite/cr16/orw.cgs b/sim/testsuite/cr16/orw.cgs new file mode 100644 index 0000000..4c1b529 --- /dev/null +++ b/sim/testsuite/cr16/orw.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for orw reg, reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global orw +orw: + movw $3, r4 + movw $6, r5 + + orw r4, r5 + + test_h_gr r5, 7 + + pass diff --git a/sim/testsuite/cr16/pop1.cgs b/sim/testsuite/cr16/pop1.cgs new file mode 100644 index 0000000..cf2a02d --- /dev/null +++ b/sim/testsuite/cr16/pop1.cgs @@ -0,0 +1,42 @@ +# cr16 testcase for pop count reg RA insns. +# mach: cr16 + + .include "testutils.inc" + + start + + .global pop1 +pop1: + movd $0x1000, (sp) + movw $0x2f50, r3 + storw r3, 0x1000 + movw $0x107e, r3 + storw r3, 0x1002 + movw $0x35ec, r3 + storw r3, 0x1004 + + movd $0xabcd, (r3,r2) + stord (r3,r2), 0x1006 + + pop $3,r5, RA + + cmpw $0x2f50,r5 + beq ok1 + br not_ok +not_ok: + fail +ok1: + cmpw $0x107e,r6 + beq ok2 + br not_ok +ok2: + cmpw $0x35ec,r7 + beq ok3 + br not_ok + +ok3: + cmpd $0xabcd, (ra) + beq ok4 + br not_ok +ok4: + pass diff --git a/sim/testsuite/cr16/pop2.cgs b/sim/testsuite/cr16/pop2.cgs new file mode 100644 index 0000000..aa3a9ec --- /dev/null +++ b/sim/testsuite/cr16/pop2.cgs @@ -0,0 +1,35 @@ +# cr16 testcase for pop count reg insns. +# mach: cr16 + + .include "testutils.inc" + + start + + .global pop2 +pop2: + movd $0x1000, (sp) + movw $0x2f50, r3 + storw r3, 0x1000 + movw $0x107e, r3 + storw r3, 0x1002 + movw $0x35ec, r3 + storw r3, 0x1004 + + pop $3,r5 + + cmpw $0x2f50,r5 + beq ok1 + br not_ok +not_ok: + fail +ok1: + cmpw $0x107e,r6 + beq ok2 + br not_ok +ok2: + cmpw $0x35ec,r7 + beq ok3 + br not_ok + +ok3: + pass diff --git a/sim/testsuite/cr16/pop3.cgs b/sim/testsuite/cr16/pop3.cgs new file mode 100644 index 0000000..13478f1 --- /dev/null +++ b/sim/testsuite/cr16/pop3.cgs @@ -0,0 +1,24 @@ +# cr16 testcase for pop RA insns. +# mach: cr16 + + .include "testutils.inc" + + start + + .global pop3 +pop3: + movd $0x1006, (sp) + movd $0xabcd, (r3,r2) + stord (r3,r2), 0x1006 + pop RA + + + cmpd $0xabcd, (ra) + beq ok + br not_ok +not_ok: + fail +ok: + pass + + diff --git a/sim/testsuite/cr16/popret1.cgs b/sim/testsuite/cr16/popret1.cgs new file mode 100644 index 0000000..a34b0fb --- /dev/null +++ b/sim/testsuite/cr16/popret1.cgs @@ -0,0 +1,40 @@ +# cr16 testcase for popret count reg RA insns. +# mach: cr16 + + .include "testutils.inc" + + start + + .global popret1 +popret1: + movd $0x1000, (sp) + movw $0x2f50, r3 + storw r3, 0x1000 + movw $0x107e, r3 + storw r3, 0x1002 + movw $0x35ec, r3 + storw r3, 0x1004 + + movd $ok, (r3,r2) # jump to ok + lshd $-1, (r3,r2) + stord (r3,r2), 0x1006 + + popret $3,r5, RA + +ok: + cmpw $0x2f50,r5 + beq ok1 + br not_ok +not_ok: + fail +ok1: + cmpw $0x107e,r6 + beq ok2 + br not_ok +ok2: + cmpw $0x35ec,r7 + beq ok3 + br not_ok + +ok3: + pass diff --git a/sim/testsuite/cr16/popret2.cgs b/sim/testsuite/cr16/popret2.cgs new file mode 100644 index 0000000..5a7f905 --- /dev/null +++ b/sim/testsuite/cr16/popret2.cgs @@ -0,0 +1,40 @@ +# cr16 testcase for popret count reg insns. +# mach: cr16 + + .include "testutils.inc" + + start + + .global popret2 +popret2: + movd $0x1000, (sp) + movw $0x2f50, r3 + storw r3, 0x1000 + movw $0x107e, r3 + storw r3, 0x1002 + movw $0x35ec, r3 + storw r3, 0x1004 + + movd $ok, (ra) + lshd $-1, (ra) + stord (ra), 0x1006 + + popret $3,r5 + +ok: + cmpw $0x2f50,r5 + beq ok1 + br not_ok +not_ok: + fail +ok1: + cmpw $0x107e,r6 + beq ok2 + br not_ok +ok2: + cmpw $0x35ec,r7 + beq ok3 + br not_ok + +ok3: + pass diff --git a/sim/testsuite/cr16/popret3.cgs b/sim/testsuite/cr16/popret3.cgs new file mode 100644 index 0000000..31aaa9b --- /dev/null +++ b/sim/testsuite/cr16/popret3.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for popret RA insns. +# mach: cr16 + + .include "testutils.inc" + + start + + .global popret3 +popret3: + movd $0x1006, (sp) + movd $ok, (ra) + lshd $-1, (ra) + stord (ra), 0x1006 + popret RA + +ok: + pass diff --git a/sim/testsuite/cr16/push1.cgs b/sim/testsuite/cr16/push1.cgs new file mode 100644 index 0000000..12d50a6 --- /dev/null +++ b/sim/testsuite/cr16/push1.cgs @@ -0,0 +1,41 @@ +# cr16 testcase for push count reg RA insns. +# mach: cr16 + + .include "testutils.inc" + + start + + .global push1 +push1: + movd $0x100a, (sp) + movd $0xabcd, (ra) + movw $0x2f50, r5 + movw $0x107e, r6 + movw $0x35ed, r7 + push $3,r5,RA + + loadw 0x1000, r3 + cmpw r3,r5 + beq ok1 + br not_ok +not_ok: + fail +ok1: + loadw 0x1002, r3 + cmpw r3,r6 + beq ok2 + br not_ok +ok2: + loadw 0x1004, r3 + cmpw r3,r7 + beq ok3 + br not_ok + +ok3: + loadd 0x1006, (r3,r2) + cmpd (r3,r2), (ra) + beq ok4 + br not_ok + +ok4: + pass diff --git a/sim/testsuite/cr16/push2.cgs b/sim/testsuite/cr16/push2.cgs new file mode 100644 index 0000000..76c1a37 --- /dev/null +++ b/sim/testsuite/cr16/push2.cgs @@ -0,0 +1,36 @@ +# cr16 testcase for push count reg insns. +# mach: cr16 + + .include "testutils.inc" + + start + + .global push2 +push2: + movd $0x1006, (sp) + movw $0x2f50, r5 + movw $0x107e, r6 + movw $0x35ed, r7 + push $3,r5 + + loadw 0x1000, r3 + cmpw r3,r5 + beq ok1 + br not_ok +not_ok: + fail +ok1: + loadw 0x1002, r3 + cmpw r3,r6 + beq ok2 + br not_ok +ok2: + loadw 0x1004, r3 + cmpw r3,r7 + beq ok3 + br not_ok + +ok3: + pass + + diff --git a/sim/testsuite/cr16/push3.cgs b/sim/testsuite/cr16/push3.cgs new file mode 100644 index 0000000..f9f5c26 --- /dev/null +++ b/sim/testsuite/cr16/push3.cgs @@ -0,0 +1,24 @@ +# cr16 testcase for push RA insns. +# mach: cr16 + + .include "testutils.inc" + + start + + .global push1 +push1: + movd $0x1006, (sp) + movd $0xabcd, (ra) + push RA + + + loadd 0x1002, (r3,r2) + cmpd (r3,r2), (ra) + beq ok + br not_ok +not_ok: + fail +ok: + pass + + diff --git a/sim/testsuite/cr16/sbitb.cgs b/sim/testsuite/cr16/sbitb.cgs new file mode 100644 index 0000000..b98329c --- /dev/null +++ b/sim/testsuite/cr16/sbitb.cgs @@ -0,0 +1,35 @@ +# cr16 testcase for sbitb $count, reg/regp/mem +# mach: cr16 + + .include "testutils.inc" + + start + + .global sbitb +sbitb: + sbitb $0,_y + loadw _y, r1 + cmpb $0xf1, r1 + beq ok1 +not_ok: + fail + +ok1: + movd $_y, (r1,r0) + sbitb $1,0(r1,r0) + loadw _y, r1 + cmpb $0xf3, r1 + beq ok2 + br not_ok +ok2: + + movw $_y, r1 + sbitb $2,0(r1) + loadw _y, r1 + cmpb $0xf7, r1 + beq ok3 + br not_ok +ok3: + pass + +_y: .word 0xf0 diff --git a/sim/testsuite/cr16/sbitw.cgs b/sim/testsuite/cr16/sbitw.cgs new file mode 100644 index 0000000..2a9a828 --- /dev/null +++ b/sim/testsuite/cr16/sbitw.cgs @@ -0,0 +1,35 @@ +# cr16 testcase for sbitw +# mach: cr16 + + .include "testutils.inc" + + start + + .global sbitw +sbitw: + sbitw $4,_y + loadw _y, r1 + cmpb $0x1f, r1 + beq ok1 +not_ok: + fail + +ok1: + movd $_y, (r1,r0) + sbitw $5,0(r1,r0) + loadw _y, r1 + cmpb $0x3f, r1 + beq ok2 + br not_ok +ok2: + + movw $_y, r1 + sbitw $6,0(r1) + loadw _y, r1 + cmpb $0x7f, r1 + beq ok3 + br not_ok +ok3: + pass + +_y: .word 0x0f diff --git a/sim/testsuite/cr16/scc.cgs b/sim/testsuite/cr16/scc.cgs new file mode 100644 index 0000000..ac592e0 --- /dev/null +++ b/sim/testsuite/cr16/scc.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for scc reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global scc +scc: + mvi_h_condbit 0 + movw $12, r4 + movw $10, r5 + cmpw r4, r5 + scc r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/scs.cgs b/sim/testsuite/cr16/scs.cgs new file mode 100644 index 0000000..a34e094 --- /dev/null +++ b/sim/testsuite/cr16/scs.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for scs reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global scs +scs: + mvi_h_condbit 0 + movw $12, r4 + movw $10, r5 + subw r4, r5 + scs r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/seq.cgs b/sim/testsuite/cr16/seq.cgs new file mode 100644 index 0000000..1b4ad79 --- /dev/null +++ b/sim/testsuite/cr16/seq.cgs @@ -0,0 +1,20 @@ +# cr16 testcase for seq reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global seq +seq: + mvi_h_condbit 0 + movw $12, r4 + movw $12, r5 + cmpw r4, r5 + seq r3 + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/sfc.cgs b/sim/testsuite/cr16/sfc.cgs new file mode 100644 index 0000000..1221f8e --- /dev/null +++ b/sim/testsuite/cr16/sfc.cgs @@ -0,0 +1,20 @@ +# cr16 testcase for sfc rep +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sfc +sfc: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + subw r4, r5 + sfc r3 + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/sfs.cgs b/sim/testsuite/cr16/sfs.cgs new file mode 100644 index 0000000..5663bfb --- /dev/null +++ b/sim/testsuite/cr16/sfs.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for sfs reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sfs +sfs: + mvi_h_condbit 0 + movw $0xaa, r4 + movw $0xaa, r5 + addb r4, r5 + sfs r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/sge.cgs b/sim/testsuite/cr16/sge.cgs new file mode 100644 index 0000000..7a65658 --- /dev/null +++ b/sim/testsuite/cr16/sge.cgs @@ -0,0 +1,20 @@ +# cr16 testcase for sge reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sge +sge: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + sge r3 + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/sgt.cgs b/sim/testsuite/cr16/sgt.cgs new file mode 100644 index 0000000..cc47ea3 --- /dev/null +++ b/sim/testsuite/cr16/sgt.cgs @@ -0,0 +1,20 @@ +# cr16 testcase for sgt reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sgt +sgt: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + sgt r3 + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/shi.cgs b/sim/testsuite/cr16/shi.cgs new file mode 100644 index 0000000..5188a51 --- /dev/null +++ b/sim/testsuite/cr16/shi.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for shi reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global shi +shi: + mvi_h_condbit 0 + movw $2, r4 + movw $1, r5 + cmpw r4, r5 + shi r3 + + cmpw $1,r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/shs.cgs b/sim/testsuite/cr16/shs.cgs new file mode 100644 index 0000000..2a10324 --- /dev/null +++ b/sim/testsuite/cr16/shs.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for shs reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global shs +shs: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + subw r4, r5 + shs r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/slo.cgs b/sim/testsuite/cr16/slo.cgs new file mode 100644 index 0000000..4e9332a --- /dev/null +++ b/sim/testsuite/cr16/slo.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for slo reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global slo +slo: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + slo r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/sls.cgs b/sim/testsuite/cr16/sls.cgs new file mode 100644 index 0000000..aab309c --- /dev/null +++ b/sim/testsuite/cr16/sls.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for sls reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sls +sls: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + sls r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/slt.cgs b/sim/testsuite/cr16/slt.cgs new file mode 100644 index 0000000..a4fa1b5 --- /dev/null +++ b/sim/testsuite/cr16/slt.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for slt rep +# mach(): cr16 + + .include "testutils.inc" + + start + + .global slt +slt: + mvi_h_condbit 0 + movw $1, r4 + movw $2, r5 + cmpw r4, r5 + slt r3 + + cmpw $1,r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/sne.cgs b/sim/testsuite/cr16/sne.cgs new file mode 100644 index 0000000..0d2ccc5 --- /dev/null +++ b/sim/testsuite/cr16/sne.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for sne reg +# mach(): cr16 + + .include "testutils.inc" + + start + + .global sne +sne: + mvi_h_condbit 0 + movw $0, r4 + movw $1, r5 + cmpw r4, r5 + sne r3 + + cmpw $1, r3 + beq ok +not_ok: + fail +ok: + pass diff --git a/sim/testsuite/cr16/storb.cgs b/sim/testsuite/cr16/storb.cgs new file mode 100644 index 0000000..289055d --- /dev/null +++ b/sim/testsuite/cr16/storb.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for st $src1,@$src2 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global st +st: + movd $data_loc, (r4,r3) + movw $1,r5 + + storw r5, 0(r4,r3) + + loadw 0(r4,r3),r1 + test_h_gr r1, 1 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/cr16/stord.cgs b/sim/testsuite/cr16/stord.cgs new file mode 100644 index 0000000..64f40c1 --- /dev/null +++ b/sim/testsuite/cr16/stord.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for st $src1,@$src2 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global st +st: + movd $data_loc, (r4,r3) + movd $0x12345678, (r6,r5) + + stord (r6,r5),0(r4,r3) + + loadd 0(r4,r3), (r1,r0) + test_h_grp "( r1,r0)", 0x12345678 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/cr16/storw.cgs b/sim/testsuite/cr16/storw.cgs new file mode 100644 index 0000000..9287636 --- /dev/null +++ b/sim/testsuite/cr16/storw.cgs @@ -0,0 +1,21 @@ +# cr16 testcase for st $src1,@$src2 +# mach(): cr16 + + .include "testutils.inc" + + start + + .global st +st: + movd $data_loc, (r4,r3) + movw $0x1234,r5 + + storw r5,0(r4,r3) + + loadw 0(r4,r3),r1 + test_h_gr r1, 0x1234 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/cr16/subb.cgs b/sim/testsuite/cr16/subb.cgs new file mode 100644 index 0000000..6a893dd --- /dev/null +++ b/sim/testsuite/cr16/subb.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for subb $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global subb +subb: + + movb $7, r4 + movb $3, r5 + + subb r5, r4 + + test_h_gr r4, 4 + + pass diff --git a/sim/testsuite/cr16/subd.cgs b/sim/testsuite/cr16/subd.cgs new file mode 100644 index 0000000..2e2a334 --- /dev/null +++ b/sim/testsuite/cr16/subd.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for subd $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global subd +subd: + + movd $0x12345678, (r4,r3) + movd $0x11111111, (r6,r5) + + subd (r6,r5), (r4,r3) + + test_h_grp "(r4,r3)", 0x1234567 + + pass diff --git a/sim/testsuite/cr16/subi.cgs b/sim/testsuite/cr16/subi.cgs new file mode 100644 index 0000000..5d0fa1a --- /dev/null +++ b/sim/testsuite/cr16/subi.cgs @@ -0,0 +1,30 @@ +# cr16 testcase for addi #$simm8, $dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global addi +addi: + + movb $1, r4 + addb $2, r4 + + cmpb $3,r4 + bne not_ok + + movw $0x1234, r5 + addw $0x1234, r5 + test_h_gr r5, 0x2468 + + pass + + movd $0x12345678, (r5,r4) + addd $0x12345678, (r5,r4) + test_h_grp "(r5,r4)", 0x2468acf0 + + pass + +not_ok: + fail diff --git a/sim/testsuite/cr16/subw.cgs b/sim/testsuite/cr16/subw.cgs new file mode 100644 index 0000000..12a1229 --- /dev/null +++ b/sim/testsuite/cr16/subw.cgs @@ -0,0 +1,18 @@ +# cr16 testcase for subw $sr,$dr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global subw +subw: + + movw $0x1234, r4 + movw $0x1111, r5 + + subw r5, r4 + + test_h_gr r4, 0x123 + + pass diff --git a/sim/testsuite/cr16/tbit.cgs b/sim/testsuite/cr16/tbit.cgs new file mode 100644 index 0000000..ac1b7e2 --- /dev/null +++ b/sim/testsuite/cr16/tbit.cgs @@ -0,0 +1,31 @@ +# cr16 testcase for tbit +# mach: cr16 + + .include "testutils.inc" + + start + + .global tbit +tbit: + movw $0, r1 + lpr r1, psr + movw $0x7, r1 + tbit $0, r1 + spr psr, r1 + cmpb $0x20, r1 + beq ok1 +not_ok: + fail + +ok1: + movw $0, r1 + lpr r1, psr + movw $0xa, r1 + movw $0x1, r2 + tbit r2,r1 + spr psr, r1 + cmpb $0x20, r1 + beq ok2 + br not_ok +ok2: + pass diff --git a/sim/testsuite/cr16/tbitb.cgs b/sim/testsuite/cr16/tbitb.cgs new file mode 100644 index 0000000..57a8ab2 --- /dev/null +++ b/sim/testsuite/cr16/tbitb.cgs @@ -0,0 +1,33 @@ +# cr16 testcase for tbitb +# mach: cr16 + + .include "testutils.inc" + + start + + .global tbitb +tbitb: + movw $0, r1 + lpr r1, psr + movw $_y, r1 + tbitb $0, 0(r1) + spr psr, r1 + cmpb $0x20, r1 + beq ok1 +not_ok: + fail + +ok1: + movw $0, r1 + lpr r1, psr + movd $_y, (r1,r0) + tbitb $1,0(r1,r0) + spr psr, r1 + cmpb $0x20, r1 + beq ok2 + br not_ok +ok2: + + pass + +_y: .word 0xf7 diff --git a/sim/testsuite/cr16/tbitw.cgs b/sim/testsuite/cr16/tbitw.cgs new file mode 100644 index 0000000..018c73e --- /dev/null +++ b/sim/testsuite/cr16/tbitw.cgs @@ -0,0 +1,33 @@ +# cr16 testcase for tbitw +# mach: cr16 + + .include "testutils.inc" + + start + + .global tbitw +tbitw: + movw $0, r1 + lpr r1, psr + tbitw $0,_y + spr psr, r1 + cmpb $0x20, r1 + beq ok1 +not_ok: + fail + +ok1: + movw $0, r1 + lpr r1, psr + movd $_y, (r1,r0) + tbitw $1,0(r1,r0) + loadw _y, r1 + spr psr, r1 + cmpb $0x20, r1 + beq ok2 + br not_ok +ok2: + + pass + +_y: .word 0xf7 diff --git a/sim/testsuite/cr16/testutils.inc b/sim/testsuite/cr16/testutils.inc new file mode 100644 index 0000000..1b82dc6 --- /dev/null +++ b/sim/testsuite/cr16/testutils.inc @@ -0,0 +1,74 @@ +# r0-r5 are used as tmps, consider them call clobbered by these macros. + + .macro START + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + .global _START +_START: + .global _start +_start: + .endm + + .macro exit rc + movw $\rc,r2 + movw $0x410,r0 + excp 8 + .endm + + .macro pass + movw $1, r2 + movd $passmsg,(r4,r3) + movw $5, r5 + movw $0x404, r0 + excp 8 + exit 0 + .endm + + .macro fail + movw $1, r2 + movd $failmsg,(r4,r3) + movw $5, r5 + movw $0x404, r0 + excp 8 + exit 1 + .endm + +# Other macros know this only clobbers r0. + .macro test_h_gr reg, val + movw $\val,r0 + cmpw \reg, r0 + beq test_gr + fail +test_gr: + .endm + + .macro test_h_grp regp, val + movd $\val,(r1,r0) + cmpd \regp,(r1,r0) + beq test_grp + fail +test_grp: + .endm + + + .macro mvi_h_condbit val + movw $0, r0 + movw $\val, r1 + cmpw r0, r1 + .endm + + .macro test_h_condbit val + .if \val + br test_c1 + fail +test_c1: + .else + br test_c0 + fail +test_c0: + .endif + .endm diff --git a/sim/testsuite/cr16/uread16.ms b/sim/testsuite/cr16/uread16.ms new file mode 100644 index 0000000..54253b4 --- /dev/null +++ b/sim/testsuite/cr16/uread16.ms @@ -0,0 +1,17 @@ +# mach: cr16 + + .include "testutils.inc" + + start + + .global read16 +read16: + loadw foo,r1 + cmpw $42, r1 + beq ok + fail +ok: + pass + +foo: + .word 42 diff --git a/sim/testsuite/cr16/uread32.ms b/sim/testsuite/cr16/uread32.ms new file mode 100644 index 0000000..c2181e5 --- /dev/null +++ b/sim/testsuite/cr16/uread32.ms @@ -0,0 +1,17 @@ +# mach: cr16 + + .include "testutils.inc" + + start + + .global read32 +read32: + loadd foo, (r1,r0) + cmpd $0x12345678, (r1,r0) + beq ok + fail +ok: + pass + +foo: + .long 0x12345678 diff --git a/sim/testsuite/cr16/xorb.cgs b/sim/testsuite/cr16/xorb.cgs new file mode 100644 index 0000000..4ee4b2d --- /dev/null +++ b/sim/testsuite/cr16/xorb.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for xor $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global xor +xor: + movb $3, r4 + movb $6, r5 + + xorb r4,r5 + + test_h_gr r5, 5 + + pass diff --git a/sim/testsuite/cr16/xord.cgs b/sim/testsuite/cr16/xord.cgs new file mode 100644 index 0000000..3bbcac0 --- /dev/null +++ b/sim/testsuite/cr16/xord.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for xor $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global xor +xor: + movd $0x33333333, (r4,r3) + movd $0x66666666, (r6,r5) + + xord (r4,r3), (r6,r5) + + test_h_grp "(r6,r5)", 0x55555555 + + pass diff --git a/sim/testsuite/cr16/xorw.cgs b/sim/testsuite/cr16/xorw.cgs new file mode 100644 index 0000000..d82faa3 --- /dev/null +++ b/sim/testsuite/cr16/xorw.cgs @@ -0,0 +1,17 @@ +# cr16 testcase for xor $dr,$sr +# mach(): cr16 + + .include "testutils.inc" + + start + + .global xor +xor: + movw $3, r4 + movw $6, r5 + + xorw r4, r5 + + test_h_gr r5, 5 + + pass diff --git a/sim/testsuite/cris/ChangeLog b/sim/testsuite/cris/ChangeLog new file mode 100644 index 0000000..16c7c27 --- /dev/null +++ b/sim/testsuite/cris/ChangeLog @@ -0,0 +1,204 @@ +2021-01-15 Mike Frysinger + + * c/c.exp: Change sim_run return to return_code. Set status to + pass/fail based on return_code. + * hw/rv-n-cris/rvc.exp (sim_has_rv_and_cris): Compare return_code + to 0. + +2021-01-09 Mike Frysinger + + * readlink4.c (main): Change rindex to strrchr. + +2021-01-07 Mike Frysinger + + PR ld/13900 + * c/helloaout.c: Disable test + +2021-01-07 Mike Frysinger + + * c/c.exp [cris*-*-elf] (CFLAGS_FOR_TARGET): Add -sim. + +2021-01-07 Mike Frysinger + + * c/kill2.c: Include unistd.h. + * c/pipe1.c, c/sched1.c, c/sched2.c, c/sched3.c, c/sched4.c, + c/sig5.c, c/sig8.c: Likewise. + * c/openpf1.c (main): Change close to fclose. + * c/openpf2.c: Likewise. + +2016-01-04 Mike Frysinger + + * asm/opterr1.ms: Update expected output. + * asm/opterr2.ms: Likewise. + +2015-12-25 Mike Frysinger + + * asm/io1.ms: Update expected output. + +2015-12-25 Mike Frysinger + + * hw/rv-n-cris/rvc.exp (rvdummy): Set up sane default. + +2012-03-24 Mike Frysinger + + * c/clone5.c: Update output to ignore decoded signal string. + * c/fcntl1.c, c/kill2.c, c/kill3.c, c/mprotect1.c, c/pipe5.c, + c/readlink5.c, c/rtsigprocmask1.c, c/rtsigsuspend1.c, c/sig10.c, + c/sig11.c, c/sig3.c, c/sig4.c, c/sig5.c, c/sig6.c, c/sig7.c, + c/sig8.c, c/sigreturn1.c, c/sigreturn2.c, c/syscall1.c, + c/syscall2.c, c/syscall3.c, c/syscall4.c, c/sysctl2.c: Likewise. + +2012-03-21 Mike Frysinger + + * asm/addqpc.ms: Update output to ignore decoded signal string. + * asm/boundmv32.ms, asm/fidxd.ms, asm/fidxi.ms, asm/ftagd.ms, + asm/ftagi.ms, asm/halt.ms, asm/io6.ms, asm/io7.ms, asm/io8.ms, + asm/io9.ms, asm/movecpc.ms, asm/movempc.ms, asm/movepcb.ms, + asm/movepcd.ms, asm/movepcw.ms, asm/moveqpc.ms, asm/moverbpc.ms, + asm/moverdpc.ms, asm/moverpcb.ms, asm/moverpcw.ms, asm/moverwpc.ms, + asm/movppc.ms, asm/movrss.ms, asm/movscpc.ms, asm/movsmpc.ms, + asm/movsrpc.ms, asm/movssr.ms, asm/movucpc.ms, asm/movumpc.ms, + asm/movurpc.ms, asm/msteppc1.ms, asm/msteppc2.ms, asm/msteppc3.ms, + asm/rfg.ms, asm/sbfs.ms, asm/subqpc.ms: Likewise. + +2010-10-07 Hans-Peter Nilsson + + * c/seek3.c, c/seek4.c: New tests. + +2010-08-24 Hans-Peter Nilsson + + * asm/nonvcv32.ms: Neutralize changed &&-in-macro gas syntax. + +2009-01-18 Hans-Peter Nilsson + + * asm/opterr5.ms, asm/opterr4.ms, + asm/opterr3.ms, asm/bare3.ms: New tests. + +2009-01-06 Hans-Peter Nilsson + + * c/mmap5.c, c/mmap6.c, c/mmap7.c, + c/mmap8.c, c/hellodyn3.c: New tests. + +2009-01-03 Hans-Peter Nilsson + + * c/settls1.c: New test. + * c/exitg1.c, c/exitg2.c: New tests. + * c/uname1.c: New test. + * c/mmap1.c (MMAP_FLAGS): Default-define to + MAP_PRIVATE and use this macro in the mmap call. + * c/mmap4.c: New test. + * c/access1.c: New test. + * asm/pid1.ms: New test. + +2008-12-30 Hans-Peter Nilsson + + * asm/badarch1.ms: Tweak error message match. + + * asm/badarch1.ms, c/badldso1.c, + c/badldso2.c, c/badldso3.c, + c/helloaout.c, c/hellodyn.c, + c/hellodyn2.c, c/writev1.c, + c/writev2.c: New tests. + * c/c.exp: If compiler links libc.so when attempting to + link dynamically, create symlink named "lib" to the directory + where it is found. Handle new test-case option "dynamic". + + * asm/opterr1.ms, asm/opterr2.ms: Adjust for + differences in getopt_long error message quoting. + +2007-11-08 Hans-Peter Nilsson + + * asm/x0-v10.ms, asm/x0-v32.ms: Tweak + stack-pointer match pattern for 4K host environment. + +2007-10-22 Edgar E. Iglesias + Hans-Peter Nilsson + + * asm/testutils.inc (test_move_cc): Add missing call to + test_cc. + * asm/asr.ms: Correct expected condition code flags. + * asm/boundr.ms: Ditto. + * asm/dstep.ms: Ditto. + * asm/lsr.ms: Ditto. + * asm/movecr.ms: Ditto. + * asm/mover.ms: Ditto. + * asm/neg.ms: Ditto. Use test_cc, not test_move_cc. + * asm/op3.ms: Check the condition code flags after the insn + under test. + * asm/movecrt10.ms: Update expected number of simulated + cycles. + * asm/movecrt32.ms: Ditto. + * asm/jsr.ms: Don't use local label 8. + * asm/nonvcv32.ms: New test. + +2007-10-11 Jesper Nilsson + + * c/freopen2.c: Added testcase. + +2006-10-02 Hans-Peter Nilsson + Edgar E. Iglesias + + * c/clone5.c, c/mprotect1.c, + c/rtsigprocmask1.c, c/rtsigsuspend1.c, + c/sig7.c, c/sigreturn1.c, + c/sigreturn2.c, c/syscall1.c, + c/syscall2.c, c/sysctl2.c, c/fcntl1.c, + c/readlink2.c: Add code to print ENOSYS if syscall being + tested returns ENOSYS. Add early exit where needed. Change any + existing code to print "xyzzy", not "pass". + * asm/option3.ms, asm/option4.ms, + c/clone6.c, c/fcntl2.c, + c/mprotect2.c, c/readlink11.c, + c/rtsigprocmask2.c, c/rtsigsuspend2.c, + c/sig13.c, c/sigreturn3.c, + c/sigreturn4.c, c/syscall3.c, + c/syscall4.c, c/syscall5.c, + c/syscall6.c, c/syscall7.c, + c/syscall8.c, c/sysctl3.c: New tests. + +2006-09-30 Hans-Peter Nilsson + + * c/pipe2.c: Adjust expected output. + (process): Don't write as much to the pipe as to trig the + inordinate-amount test in the sim pipe machinery. Correct test of + write return-value; check only that pipemax bytes were + successfully written. For error-case, emit strerror as well. + (main): Add a second read. + +2006-04-08 Hans-Peter Nilsson + + * hw/rv-n-cris/irq6.ms: New test. + +2006-04-03 Hans-Peter Nilsson + + * hw: New directory for subdirectories with tests. + * hw/rv-n-cris: New directory with tests. + +2006-04-02 Hans-Peter Nilsson + + * asm/testutils.inc (test_h_mem): Use register prefix. + (testr_h_dr, test_h_dr, ldmem_h_gr, mvr_h_mem): Ditto. Correct + syntax. + + * asm/x0-v10.ms, asm/x0-v32.ms: Widen regexp for + stack pointer values. + +2006-02-23 Hans-Peter Nilsson + + * c/time2.c: New test. + +2006-01-10 Hans-Peter Nilsson + + * asm/x1-v10.ms, asm/x3-v10.ms, + asm/x7-v10.ms: Update expected cycle output. + +2005-12-06 Hans-Peter Nilsson + + * asm/movmp8.ms, asm/pcplus.ms: New tests. + * asm/movmp.ms: Do not write to P0, P4 or P8. + * asm/raw13.ms: Write to MOF instead of WZ (P4). + +2005-11-21 Hans-Peter Nilsson + + * asm, c: New directory with C and assembly tests for the CRIS + simulator. diff --git a/sim/testsuite/cris/asm/abs.ms b/sim/testsuite/cris/asm/abs.ms new file mode 100644 index 0000000..a428434 --- /dev/null +++ b/sim/testsuite/cris/asm/abs.ms @@ -0,0 +1,50 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n0\n80000000\n7fffffff\n2a\n1\nffff\n1f\n0\n + + .include "testutils.inc" + start + moveq -1,r3 + + abs r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq 0,r3 + dumpr3 ; 0 + + move.d 0x80000000,r4 + abs r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 80000000 + + move.d 0x7fffffff,r4 + abs r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 7fffffff + + move.d 42,r3 + abs r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2a + + moveq 1,r6 + abs r6,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xffff,r3 + abs r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -31,r5 + abs r5,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1f + + moveq 0,r5 + abs r5,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/addc.ms b/sim/testsuite/cris/asm/addc.ms new file mode 100644 index 0000000..8b7fa72 --- /dev/null +++ b/sim/testsuite/cris/asm/addc.ms @@ -0,0 +1,81 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n + + .include "testutils.inc" + start + moveq -1,r3 + add.d 2,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + add.d -1,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xffff,r3 + add.d 0xffff,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + + moveq -1,r3 + add.d -1,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + + move.d 0x78134452,r3 + add.d 0x5432f789,r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdb + + moveq -1,r3 + add.w 2,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff0001 + + moveq 2,r3 + add.w -1,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xffff,r3 + add.w 0xffff,r3 + test_cc 1 0 0 1 + dumpr3 ; fffe + + move.d 0xfedaffff,r3 + add.w 0xffff,r3 + test_cc 1 0 0 1 + dumpr3 ; fedafffe + + move.d 0x78134452,r3 + add.w 0xf789,r3 + test_cc 0 0 0 1 + dumpr3 ; 78133bdb + + moveq -1,r3 + add.b 2,r3 + test_cc 0 0 0 1 + dumpr3 ; ffffff01 + + moveq 2,r3 + add.b -1,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xff,r3 + add.b 0xff,r3 + test_cc 1 0 0 1 + dumpr3 ; fe + + move.d 0xfeda49ff,r3 + add.b 0xff,r3 + test_cc 1 0 0 1 + dumpr3 ; feda49fe + + move.d 0x78134452,r3 + add.b 0x89,r3 + test_cc 1 0 0 0 + dumpr3 ; 781344db + + quit diff --git a/sim/testsuite/cris/asm/addcpc.ms b/sim/testsuite/cris/asm/addcpc.ms new file mode 100644 index 0000000..0302fa2 --- /dev/null +++ b/sim/testsuite/cris/asm/addcpc.ms @@ -0,0 +1,35 @@ +# mach: crisv3 crisv8 crisv10 +# output: 2f\n31\n + +# Test that the special case add.d const,pc works. + + .include "testutils.inc" + start +x: + add.d y-y0,pc +y0: + quit + + .space 1000 + quit + quit + quit + quit + quit +z: + move.d 49,r3 + dumpr3 + quit + + .space 1000 + quit + quit + quit + quit + quit +y: + move.d 47,r3 + dumpr3 + add.d z-z0,pc +z0: + quit diff --git a/sim/testsuite/cris/asm/addcv32c.ms b/sim/testsuite/cris/asm/addcv32c.ms new file mode 100644 index 0000000..0264fae --- /dev/null +++ b/sim/testsuite/cris/asm/addcv32c.ms @@ -0,0 +1,50 @@ +# mach: crisv32 +# output: 0\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n + + .include "testutils.inc" + start + clearf cz + moveq 0,r3 + addc 0,r3 + test_cc 0 0 0 0 + dumpr3 ; 0 + + setf z + moveq 0,r3 + addc 0,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + setf cz + moveq 0,r3 + addc 0,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + clearf c + moveq -1,r3 + addc 2,r3 + test_cc 0 0 0 1 + dumpr3 ; 1+c + + moveq 2,r3 + addc -1,r3 + test_cc 0 0 0 1 + dumpr3 ; 2+c + + move.d 0xffff,r3 + addc 0xffff,r3 + test_cc 0 0 0 0 + dumpr3 ; 1ffff + + moveq -1,r3 + addc -1,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe+c + + move.d 0x78134452,r3 + addc 0x5432f789,r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdc + + quit diff --git a/sim/testsuite/cris/asm/addcv32m.ms b/sim/testsuite/cris/asm/addcv32m.ms new file mode 100644 index 0000000..13139b2 --- /dev/null +++ b/sim/testsuite/cris/asm/addcv32m.ms @@ -0,0 +1,69 @@ +# mach: crisv32 +# output: 0\n0\n1\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n + + .include "testutils.inc" + .data +x: + .dword 0,0,2,-1,0xffff,-1,0x5432f789 + + start + move.d x,r5 + clearf cz + moveq 0,r3 + addc [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 0 + + setf z + moveq 0,r3 + addc [r5],r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + setf c + moveq 0,r3 + addc [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + clearf c + moveq 0,r3 + addc [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 0 + + setf c + moveq 0,r3 + addc [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + clearf c + moveq -1,r3 + addc [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 1+c + + moveq 2,r3 + addc [r5],r3 + moveq 4,r6 + addi r6.b,r5 + test_cc 0 0 0 1 + dumpr3 ; 2+c + + move.d 0xffff,r3 + addc [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 1ffff + + moveq -1,r3 + addc [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe+c + + move.d 0x78134452,r3 + addc [r5+],r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdc + + quit diff --git a/sim/testsuite/cris/asm/addcv32r.ms b/sim/testsuite/cris/asm/addcv32r.ms new file mode 100644 index 0000000..20aeb12 --- /dev/null +++ b/sim/testsuite/cris/asm/addcv32r.ms @@ -0,0 +1,57 @@ +# mach: crisv32 +# output: 0\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n + + .include "testutils.inc" + start + clearf cz + moveq 0,r3 + moveq 0,r4 + addc r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 0 + + setf z + moveq 0,r3 + moveq 0,r4 + addc r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + setf cz + moveq 0,r3 + moveq 0,r4 + addc r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 2,r4 + addc r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 1+c + + moveq 2,r3 + moveq -1,r4 + addc r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 2+c + + move.d 0xffff,r4 + move.d r4,r3 + addc r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1ffff + + moveq -1,r4 + move.d r4,r3 + addc r4,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe+c + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + addc r4,r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdc + + quit diff --git a/sim/testsuite/cris/asm/addi.ms b/sim/testsuite/cris/asm/addi.ms new file mode 100644 index 0000000..2fa2723 --- /dev/null +++ b/sim/testsuite/cris/asm/addi.ms @@ -0,0 +1,57 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 0\n1\n2\n4\nbe02460f\n69d035a6\nc16c14d4\n + + .include "testutils.inc" + start + moveq 0,r3 + moveq 0,r4 + clearf zcvn + addi r4.b,r3 + test_cc 0 0 0 0 + dumpr3 ; 0 + + moveq 0,r3 + moveq 1,r4 + setf zcvn + addi r4.b,r3 + test_cc 1 1 1 1 + dumpr3 ; 1 + + moveq 0,r3 + moveq 1,r4 + setf cv + clearf zn + addi r4.w,r3 + test_cc 0 0 1 1 + dumpr3 ; 2 + + moveq 0,r3 + moveq 1,r4 + clearf cv + setf zn + addi r4.d,r3 + test_cc 1 1 0 0 + dumpr3 ; 4 + + move.d 0x12345678,r3 + move.d 0xabcdef97,r4 + clearf cn + setf zv + addi r4.b,r3 + test_cc 0 1 1 0 + dumpr3 ; be02460f + + move.d 0x12345678,r3 + move.d 0xabcdef97,r4 + setf cn + clearf zv + addi r4.w,r3 + test_cc 1 0 0 1 + dumpr3 ; 69d035a6 + + move.d 0x12345678,r3 + move.d 0xabcdef97,r4 + addi r4.d,r3 + dumpr3 ; c16c14d4 + + quit diff --git a/sim/testsuite/cris/asm/addiv32.ms b/sim/testsuite/cris/asm/addiv32.ms new file mode 100644 index 0000000..8040afc --- /dev/null +++ b/sim/testsuite/cris/asm/addiv32.ms @@ -0,0 +1,62 @@ +# mach: crisv32 +# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + + start + setf cv + moveq -1,r0 + move.d x-32768,r5 + move.d 32769,r6 + addi r6.b,r5,acr + test_cc 0 0 1 1 + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addu.w 32771,r5 + setf znvc + moveq -1,r8 + addi r8.w,r5,acr + test_cc 1 1 1 1 + move.d [acr],r3 + dumpr3 ; 4455aa77 + + moveq 5,r10 + clearf znvc + addi r10.b,acr,acr + test_cc 0 0 0 0 + move.d [acr],r3 + dumpr3 ; ee19ccff + + subq 1,r5 + move.d r5,r8 + subq 1,r8 + moveq 1,r9 + addi r9.d,r8,acr + test_cc 0 0 0 0 + movu.w [acr],r3 + dumpr3 ; ff22 + + moveq -2,r11 + addi r11.w,acr,acr + move.d [acr],r3 + dumpr3 ; 4455aa77 + + moveq 5,r9 + addi r9.d,acr,acr + subq 18,acr + move.d [acr],r3 + dumpr3 ; ff224455 + + move.d -76789888/4,r12 + addi r12.d,r5,acr + add.d 76789886,acr + move.d [acr],r3 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/cris/asm/addm.ms b/sim/testsuite/cris/asm/addm.ms new file mode 100644 index 0000000..c214e3a --- /dev/null +++ b/sim/testsuite/cris/asm/addm.ms @@ -0,0 +1,96 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n781344d0\n + + .include "testutils.inc" + .data +x: + .dword 2,-1,0xffff,-1,0x5432f789 + .word 2,-1,0xffff,0xf789 + .byte 2,0xff,0x89 + .byte 0x7e + + start + moveq -1,r3 + move.d x,r5 + add.d [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + add.d [r5],r3 + test_cc 0 0 0 1 + addq 4,r5 + dumpr3 ; 1 + + move.d 0xffff,r3 + add.d [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + + moveq -1,r3 + add.d [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + + move.d 0x78134452,r3 + add.d [r5+],r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdb + + moveq -1,r3 + add.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; ffff0001 + + moveq 2,r3 + add.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xffff,r3 + add.w [r5],r3 + test_cc 1 0 0 1 + dumpr3 ; fffe + + move.d 0xfedaffff,r3 + add.w [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; fedafffe + + move.d 0x78134452,r3 + add.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 78133bdb + + moveq -1,r3 + add.b [r5],r3 + test_cc 0 0 0 1 + addq 1,r5 + dumpr3 ; ffffff01 + + moveq 2,r3 + add.b [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xff,r3 + add.b [r5],r3 + test_cc 1 0 0 1 + dumpr3 ; fe + + move.d 0xfeda49ff,r3 + add.b [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; feda49fe + + move.d 0x78134452,r3 + add.b [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; 781344db + + move.d 0x78134452,r3 + add.b [r5],r3 + test_cc 1 0 1 0 + dumpr3 ; 781344d0 + + quit diff --git a/sim/testsuite/cris/asm/addoc.ms b/sim/testsuite/cris/asm/addoc.ms new file mode 100644 index 0000000..fe269d2 --- /dev/null +++ b/sim/testsuite/cris/asm/addoc.ms @@ -0,0 +1,44 @@ +# mach: crisv32 +# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + + start + moveq -1,r0 + move.d x-32768,r5 + addo.d 32769,r5,acr + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addu.w 32770,r5 + addo.w -1,r5,acr + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addo.d 5,acr,acr + move.d [acr],r3 + dumpr3 ; ee19ccff + + addo.b 3,r5,acr + movu.w [acr],r3 + dumpr3 ; ff22 + + addo.b -4,acr,acr + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addo.w 2,acr,acr + move.d [acr],r3 + dumpr3 ; ff224455 + + addo.d -76789887,r5,acr + add.d 76789885,acr + move.d [acr],r3 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/cris/asm/addom.ms b/sim/testsuite/cris/asm/addom.ms new file mode 100644 index 0000000..4e4ebb1 --- /dev/null +++ b/sim/testsuite/cris/asm/addom.ms @@ -0,0 +1,55 @@ +# mach: crisv32 +# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 +y: + .dword 32769 + .word -1 + .dword 5 + .byte 3,-4 + .word 2 + .dword -76789887 + + start + moveq -1,r0 + move.d x-32768,r5 + move.d y,r13 + addo.d [r13+],r5,acr + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addu.w 32770,r5 + addo.w [r13+],r5,acr + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addo.d [r13],acr,acr + addq 4,r13 + move.d [acr],r3 + dumpr3 ; ee19ccff + + addo.b [r13+],r5,acr + movu.w [acr],r3 + dumpr3 ; ff22 + + addo.b [r13],acr,acr + addq 1,r13 + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addo.w [r13],acr,acr + addq 2,r13 + move.d [acr],r3 + dumpr3 ; ff224455 + + addo.d [r13+],r5,acr + add.d 76789885,acr + move.d [acr],r3 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/cris/asm/addoq.ms b/sim/testsuite/cris/asm/addoq.ms new file mode 100644 index 0000000..f4b6083 --- /dev/null +++ b/sim/testsuite/cris/asm/addoq.ms @@ -0,0 +1,31 @@ +# mach: crisv32 +# output: ccff2244\n88ccee19\n55aa77ff\n19cc\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + start + moveq -1,r0 + move.d x+4,r5 + setf zvnc + addoq 0,r5,acr + test_cc 1 1 1 1 + move.d [acr],r3 + dumpr3 ; ccff2244 + setf zvnc + addoq 4,r5,acr + test_cc 1 1 1 1 + move.d [acr],r3 + dumpr3 ; 88ccee19 + clearf zvnc + addoq -8,acr,acr + test_cc 0 0 0 0 + move.d [acr],r3 + dumpr3 ; 55aa77ff + addoq 3,r5,acr + movu.w [acr],r3 + dumpr3 ; 19cc + quit diff --git a/sim/testsuite/cris/asm/addq.ms b/sim/testsuite/cris/asm/addq.ms new file mode 100644 index 0000000..6a27ac5 --- /dev/null +++ b/sim/testsuite/cris/asm/addq.ms @@ -0,0 +1,47 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n0\n1\n100\n10000\n47\n67\na6\n80000001\n + + .include "testutils.inc" + start + moveq -2,r3 + addq 1,r3 + test_cc 1 0 0 0 + dumpr3 + + addq 1,r3 + test_cc 0 1 0 1 + dumpr3 + + addq 1,r3 + test_cc 0 0 0 0 + dumpr3 + + move.d 0xff,r3 + addq 1,r3 + test_cc 0 0 0 0 + dumpr3 + + move.d 0xffff,r3 + addq 1,r3 + test_cc 0 0 0 0 + dumpr3 + + move.d 0x42,r3 + addq 5,r3 + test_cc 0 0 0 0 + dumpr3 + + addq 32,r3 + test_cc 0 0 0 0 + dumpr3 + + addq 63,r3 + test_cc 0 0 0 0 + dumpr3 + + move.d 0x7ffffffe,r3 + addq 3,r3 + test_cc 1 0 1 0 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/addqpc.ms b/sim/testsuite/cris/asm/addqpc.ms new file mode 100644 index 0000000..ba5a1ec --- /dev/null +++ b/sim/testsuite/cris/asm/addqpc.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + addq 1,pc + diff --git a/sim/testsuite/cris/asm/addr.ms b/sim/testsuite/cris/asm/addr.ms new file mode 100644 index 0000000..c1b9348 --- /dev/null +++ b/sim/testsuite/cris/asm/addr.ms @@ -0,0 +1,96 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + add.d r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + moveq -1,r4 + add.d r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xffff,r4 + move.d r4,r3 + add.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + + moveq -1,r4 + move.d r4,r3 + add.d r4,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + add.d r4,r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdb + + moveq -1,r3 + moveq 2,r4 + add.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff0001 + + moveq 2,r3 + moveq -1,r4 + add.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xffff,r4 + move.d r4,r3 + add.w r4,r3 + test_cc 1 0 0 1 + dumpr3 ; fffe + + move.d 0xfedaffff,r4 + move.d r4,r3 + add.w r4,r3 + test_cc 1 0 0 1 + dumpr3 ; fedafffe + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + add.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 78133bdb + + moveq -1,r3 + moveq 2,r4 + add.b r4,r3 + test_cc 0 0 0 1 + dumpr3 ; ffffff01 + + moveq 2,r3 + moveq -1,r4 + add.b r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xff,r4 + move.d r4,r3 + add.b r4,r3 + test_cc 1 0 0 1 + dumpr3 ; fe + + move.d 0xfeda49ff,r4 + move.d r4,r3 + add.b r4,r3 + test_cc 1 0 0 1 + dumpr3 ; feda49fe + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + add.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; 781344db + + quit diff --git a/sim/testsuite/cris/asm/addswpc.ms b/sim/testsuite/cris/asm/addswpc.ms new file mode 100644 index 0000000..a7ac754 --- /dev/null +++ b/sim/testsuite/cris/asm/addswpc.ms @@ -0,0 +1,61 @@ +# mach: crisv3 crisv8 crisv10 +# output: 7\n + +# Test that the special case adds.w [pc+rN.w],pc works. + + .include "testutils.inc" + start +x: + moveq 0,r3 + ba xy + moveq 5,r2 + +ok: + moveq 7,r3 + dumpr3 + quit + +xy: + adds.w [pc+r2.w],pc +y: + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word ok-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y +x0: + quit diff --git a/sim/testsuite/cris/asm/addxc.ms b/sim/testsuite/cris/asm/addxc.ms new file mode 100644 index 0000000..0e346df --- /dev/null +++ b/sim/testsuite/cris/asm/addxc.ms @@ -0,0 +1,91 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n + + .include "testutils.inc" + start + moveq 2,r3 + adds.b 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + adds.w 0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + addu.b 0xff,r3 + dumpr3 ; 101 + + moveq 2,r3 + move.d 0xffffffff,r4 + addu.w -1,r3 + test_cc 0 0 0 0 + dumpr3 ; 10001 + + move.d 0xffff,r3 + addu.b -1,r3 + test_cc 0 0 0 0 + dumpr3 ; 100fe + + move.d 0xffff,r3 + addu.w -1,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + + move.d 0xffff,r3 + adds.b 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; fffe + + move.d 0xffff,r3 + adds.w 0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; fffe + + moveq -1,r3 + adds.b 0xff,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + + moveq -1,r3 + adds.w 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; fe + + moveq -1,r3 + adds.w 0xffff,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + + move.d 0x78134452,r3 + addu.b 0x89,r3 + test_cc 0 0 0 0 + dumpr3 ; 781344db + + move.d 0x78134452,r3 + adds.b 0x89,r3 + test_cc 0 0 0 1 + dumpr3 ; 781343db + + move.d 0x78134452,r3 + addu.w 0xf789,r3 + test_cc 0 0 0 0 + dumpr3 ; 78143bdb + + move.d 0x78134452,r3 + adds.w 0xf789,r3 + test_cc 0 0 0 1 + dumpr3 ; 78133bdb + + move.d 0x7fffffee,r3 + addu.b 0xff,r3 + test_cc 1 0 1 0 + dumpr3 ; 800000ed + + move.d 0x1,r3 + adds.w 0xffff,r3 + test_cc 0 1 0 1 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/addxm.ms b/sim/testsuite/cris/asm/addxm.ms new file mode 100644 index 0000000..40ae9aa --- /dev/null +++ b/sim/testsuite/cris/asm/addxm.ms @@ -0,0 +1,106 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n + + .include "testutils.inc" + .data +x: + .byte 0xff + .word 0xffff + .word 0xff + .word 0xffff + .byte 0x89 + .word 0xf789 + .byte 0xff + .word 0xffff + + start + moveq 2,r3 + move.d x,r5 + adds.b [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + adds.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + subq 3,r5 + addu.b [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 101 + + moveq 2,r3 + addu.w [r5+],r3 + subq 3,r5 + test_cc 0 0 0 0 + dumpr3 ; 10001 + + move.d 0xffff,r3 + addu.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 100fe + + move.d 0xffff,r3 + addu.w [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + + move.d 0xffff,r3 + adds.b [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; fffe + + move.d 0xffff,r3 + adds.w [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; fffe + + moveq -1,r3 + adds.b [r5],r3 + test_cc 1 0 0 1 + addq 3,r5 + dumpr3 ; fffffffe + + moveq -1,r3 + adds.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; fe + + moveq -1,r3 + adds.w [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + + move.d 0x78134452,r3 + addu.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 781344db + + move.d 0x78134452,r3 + adds.b [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 781343db + + move.d 0x78134452,r3 + addu.w [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 78143bdb + + move.d 0x78134452,r3 + adds.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 78133bdb + + move.d 0x7fffffee,r3 + addu.b [r5+],r3 + test_cc 1 0 1 0 + dumpr3 ; 800000ed + + move.d 0x1,r3 + adds.w [r5+],r3 + test_cc 0 1 0 1 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/addxr.ms b/sim/testsuite/cris/asm/addxr.ms new file mode 100644 index 0000000..8234ac3 --- /dev/null +++ b/sim/testsuite/cris/asm/addxr.ms @@ -0,0 +1,93 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n + + .include "testutils.inc" + start + moveq 2,r3 + move.d 0xff,r4 + adds.b r4,r3 + dumpr3 ; 1 + + moveq 2,r3 + move.d 0xffff,r4 + adds.w r4,r3 + dumpr3 ; 1 + + moveq 2,r3 + move.d 0xffff,r4 + addu.b r4,r3 + dumpr3 ; 101 + + moveq 2,r3 + move.d 0xffffffff,r4 + addu.w r4,r3 + dumpr3 ; 10001 + + move.d 0xffff,r3 + move.d 0xffffffff,r4 + addu.b r4,r3 + dumpr3 ; 100fe + + move.d 0xffff,r3 + move.d 0xffffffff,r4 + addu.w r4,r3 + dumpr3 ; 1fffe + + move.d 0xffff,r3 + move.d 0xff,r4 + adds.b r4,r3 + dumpr3 ; fffe + + move.d 0xffff,r4 + move.d r4,r3 + adds.w r4,r3 + dumpr3 ; fffe + + moveq -1,r3 + move.d 0xff,r4 + adds.b r4,r3 + dumpr3 ; fffffffe + + moveq -1,r3 + move.d 0xff,r4 + adds.w r4,r3 + dumpr3 ; fe + + moveq -1,r3 + move.d 0xffff,r4 + adds.w r4,r3 + dumpr3 ; fffffffe + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + addu.b r4,r3 + dumpr3 ; 781344db + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + adds.b r4,r3 + dumpr3 ; 781343db + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + addu.w r4,r3 + dumpr3 ; 78143bdb + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + adds.w r4,r3 + dumpr3 ; 78133bdb + + move.d 0x7fffffee,r3 + move.d 0xff,r4 + addu.b r4,r3 + test_cc 1 0 1 0 + dumpr3 ; 800000ed + + move.d 0x1,r3 + move.d 0xffff,r4 + adds.w r4,r3 + test_cc 0 1 0 1 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/andc.ms b/sim/testsuite/cris/asm/andc.ms new file mode 100644 index 0000000..e800a0a --- /dev/null +++ b/sim/testsuite/cris/asm/andc.ms @@ -0,0 +1,80 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n + + .include "testutils.inc" + start + moveq -1,r3 + and.d 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + and.d -1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + and.d 0xffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r3 + and.d -1,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + and.d 0x5432f789,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 50124400 + + moveq -1,r3 + and.w 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0002 + + moveq 2,r3 + and.w -1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xfffff,r3 + and.w 0xffff,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffff + + move.d 0xfedaffaf,r3 + and.w 0xff5f,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fedaff0f + + move.d 0x78134452,r3 + and.w 0xf789,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134400 + + moveq -1,r3 + and.b 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffffff02 + + moveq 2,r3 + and.b -1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xfa7,r3 + and.b 0x5a,r3 + test_move_cc 0 0 0 0 + dumpr3 ; f02 + + move.d 0x78134453,r3 + and.b 0x89,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134401 + + and.b 0,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 78134400 + + quit diff --git a/sim/testsuite/cris/asm/andm.ms b/sim/testsuite/cris/asm/andm.ms new file mode 100644 index 0000000..4e1a34b --- /dev/null +++ b/sim/testsuite/cris/asm/andm.ms @@ -0,0 +1,90 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n + + .include "testutils.inc" + .data +x: + .dword 2,-1,0xffff,-1,0x5432f789 + .word 2,-1,0xffff,0xff5f,0xf789 + .byte 2,-1,0x5a,0x89,0 + + start + moveq -1,r3 + move.d x,r5 + and.d [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + and.d [r5],r3 + test_move_cc 0 0 0 0 + addq 4,r5 + dumpr3 ; 2 + + move.d 0xffff,r3 + and.d [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r3 + and.d [r5+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + and.d [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 50124400 + + moveq -1,r3 + and.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0002 + + moveq 2,r3 + and.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xfffff,r3 + and.w [r5],r3 + test_move_cc 1 0 0 0 + addq 2,r5 + dumpr3 ; fffff + + move.d 0xfedaffaf,r3 + and.w [r5+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; fedaff0f + + move.d 0x78134452,r3 + and.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134400 + + moveq -1,r3 + and.b [r5],r3 + test_move_cc 0 0 0 0 + addq 1,r5 + dumpr3 ; ffffff02 + + moveq 2,r3 + and.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xfa7,r3 + and.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; f02 + + move.d 0x78134453,r3 + and.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134401 + + and.b [r5],r3 + test_move_cc 0 1 0 0 + dumpr3 ; 78134400 + + quit diff --git a/sim/testsuite/cris/asm/andq.ms b/sim/testsuite/cris/asm/andq.ms new file mode 100644 index 0000000..e515b3e --- /dev/null +++ b/sim/testsuite/cris/asm/andq.ms @@ -0,0 +1,46 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\nffff\nffffffff\n1f\nffffffe0\n78134452\n0\n + + .include "testutils.inc" + start + moveq -1,r3 + andq 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + andq -1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + andq -1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r3 + andq -1,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + andq 31,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1f + + moveq -1,r3 + andq -32,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffe0 + + move.d 0x78134457,r3 + andq -14,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134452 + + moveq 0,r3 + andq -14,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/andr.ms b/sim/testsuite/cris/asm/andr.ms new file mode 100644 index 0000000..f5d90e2 --- /dev/null +++ b/sim/testsuite/cris/asm/andr.ms @@ -0,0 +1,95 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + and.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + moveq -1,r4 + and.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r4 + move.d r4,r3 + and.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r4 + move.d r4,r3 + and.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + and.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 50124400 + + moveq -1,r3 + moveq 2,r4 + and.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0002 + + moveq 2,r3 + moveq -1,r4 + and.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xfffff,r3 + move.d 0xffff,r4 + and.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffff + + move.d 0xfedaffaf,r3 + move.d 0xff5f,r4 + and.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fedaff0f + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + and.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134400 + + moveq -1,r3 + moveq 2,r4 + and.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffffff02 + + moveq 2,r3 + moveq -1,r4 + and.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0x5a,r4 + move.d 0xfa7,r3 + and.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; f02 + + move.d 0x5432f789,r4 + move.d 0x78134453,r3 + and.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134401 + + moveq 0,r7 + and.b r7,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 78134400 + + quit diff --git a/sim/testsuite/cris/asm/asm.exp b/sim/testsuite/cris/asm/asm.exp new file mode 100644 index 0000000..415bbf1 --- /dev/null +++ b/sim/testsuite/cris/asm/asm.exp @@ -0,0 +1,45 @@ +# Copyright (C) 2005-2021 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# Miscellaneous CRIS simulator testcases in assembly code. + +if [istarget cris*-*-*] { + global ASFLAGS_FOR_TARGET + # All machines we test and the corresponding assembler option. Needs + # update if we build the simulator for crisv0 crisv3 and crisv8 too. + + set combos {{"crisv10" "--march=v10 --no-mul-bug-abort"} + {"crisv32" "--march=v32"}} + + # We need to pass different assembler flags for each machine. + # Specifying it here rather than adding a specifier to each and every + # test-file is preferrable. + + foreach combo $combos { + set mach [lindex $combo 0] + set ASFLAGS_FOR_TARGET "[lindex $combo 1]" + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $mach + } + } +} diff --git a/sim/testsuite/cris/asm/asr.ms b/sim/testsuite/cris/asm/asr.ms new file mode 100644 index 0000000..066bc73 --- /dev/null +++ b/sim/testsuite/cris/asm/asr.ms @@ -0,0 +1,228 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n1\nffffffff\nffffffff\n5a67f\nffffffff\nffffffff\nffffffff\nf699fc67\nffffffff\n1\nffffffff\nffffffff\n5a67f\nda67ffff\nda67ffff\nda67ffff\nda67fc67\nffffffff\nffffffff\n1\nffffffff\nffffffff\n5a670007\nda67f1ff\nda67f1ff\nda67f1ff\nda67f1e7\nffffffff\nffffffff\n1\nffffffff\nffffffff\nffffffff\n5a67f1ff\n5a67f1f9\n0\n5a670000\n + + .include "testutils.inc" + start + moveq -1,r3 + asrq 0,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + asrq 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + asrq 31,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + asrq 15,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5a67f19f,r3 + asrq 12,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67f + + move.d 0xda67f19f,r3 + move.d 31,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0xda67f19f,r3 + move.d 32,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0xda67f19f,r3 + move.d 33,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0xda67f19f,r3 + move.d 66,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; f699fc67 + + moveq -1,r3 + moveq 0,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + asr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 31,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 15,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5a67f19f,r3 + moveq 12,r4 + asr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67f + + move.d 0xda67f19f,r3 + move.d 31,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67ffff + + move.d 0xda67f19f,r3 + move.d 32,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67ffff + + move.d 0xda67f19f,r3 + move.d 33,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67ffff + + move.d 0xda67f19f,r3 + move.d 66,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67fc67 + + moveq -1,r3 + moveq 0,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 1,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + asr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 31,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 15,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5a67719f,r3 + moveq 12,r4 + asr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a670007 + + move.d 0xda67f19f,r3 + move.d 31,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67f1ff + + move.d 0xda67f19f,r3 + move.d 32,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67f1ff + + move.d 0xda67f19f,r3 + move.d 33,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67f1ff + + move.d 0xda67f19f,r3 + move.d 66,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67f1e7 + + moveq -1,r3 + moveq 0,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 1,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + asr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 31,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 15,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 7,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5a67f19f,r3 + moveq 12,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 5a67f1ff + + move.d 0x5a67f19f,r3 + moveq 4,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 5a67f1f9 + + move.d 0x5a67f19f,r3 + asrq 31,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x5a67419f,r3 + moveq 16,r4 + asr.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 5a670000 + + quit diff --git a/sim/testsuite/cris/asm/ba.ms b/sim/testsuite/cris/asm/ba.ms new file mode 100644 index 0000000..1211962 --- /dev/null +++ b/sim/testsuite/cris/asm/ba.ms @@ -0,0 +1,93 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: a\n + + .include "testutils.inc" + + .if ..asm.arch.cris.v32 + .set smalloffset,0 + .set largeoffset,0 + .else + .set smalloffset,2 + .set largeoffset,4 + .endif + + start + moveq 0,r3 + +; Short forward branch. + ba 0f + addq 1,r3 + fail + +; Max short forward branch. +1: + ba 2f + addq 1,r3 + fail + +; Short backward branch. +0: + ba 1b + addq 1,r3 + fail + + .space 254-2+smalloffset+1b-.,0 + moveq 0,r3 + +2: +; Transit branch (long). + ba 3f + addq 1,r3 + fail + + moveq 0,r3 +4: +; Long forward branch. + ba 5f + addq 1,r3 + fail + + .space 256-2-smalloffset+4b-.,0 + + moveq 0,r3 + +; Max short backward branch. +3: + ba 4b + addq 1,r3 + fail + +5: +; Max long forward branch. + ba 6f + addq 1,r3 + fail + + .space 32766+largeoffset-2+5b-.,0 + + moveq 0,r3 +6: +; Transit branch. + ba 7f + addq 1,r3 + fail + + moveq 0,r3 +9: + dumpr3 + quit + +; Transit branch. + moveq 0,r3 +7: + ba 8f + addq 1,r3 + fail + + .space 32768-largeoffset+9b-.,0 + +8: +; Max long backward branch. + ba 9b + addq 1,r3 + fail diff --git a/sim/testsuite/cris/asm/badarch1.ms b/sim/testsuite/cris/asm/badarch1.ms new file mode 100644 index 0000000..3d0d812 --- /dev/null +++ b/sim/testsuite/cris/asm/badarch1.ms @@ -0,0 +1,5 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# xerror: +# output: *not a CRIS program* +# sim: /bin/sh + .include "nopv32t.ms" diff --git a/sim/testsuite/cris/asm/bare1.ms b/sim/testsuite/cris/asm/bare1.ms new file mode 100644 index 0000000..6c7d0d2 --- /dev/null +++ b/sim/testsuite/cris/asm/bare1.ms @@ -0,0 +1,24 @@ +# mach: crisv32 +# ld: --section-start=.text=0 +# output: 0\n0\n4\n42\n +# sim: --cris-naked + +; Check that we don't get signs of an initialized environment +; when --cris-naked. + + .include "testutils.inc" + .text + .global _start +_start: + nop + nop +start2: + move.d $r10,$r3 + dumpr3 + move.d $sp,$r3 + dumpr3 + lapc start2,$r3 + dumpr3 + move.d 0x42,$r3 + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/bare2.ms b/sim/testsuite/cris/asm/bare2.ms new file mode 100644 index 0000000..f30fd10 --- /dev/null +++ b/sim/testsuite/cris/asm/bare2.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# output: 0\n0\n4\n42\n +# sim: --cris-naked --target binary --architecture crisv32 +# ld: --oformat binary + +; Check that we can run a naked binary with the same expected +; results as an ELF "executable". + + .include "bare1.ms" diff --git a/sim/testsuite/cris/asm/bare3.ms b/sim/testsuite/cris/asm/bare3.ms new file mode 100644 index 0000000..103530d --- /dev/null +++ b/sim/testsuite/cris/asm/bare3.ms @@ -0,0 +1,41 @@ +# mach: crisv32 +# ld: -N --oformat binary --section-start=.text=0x10000000 +# sim: --architecture crisv32 --target binary --cris-program-offset=0x10000000 --cris-start-address=0x10000040 --cris-naked --memory-region 0x10000000,0x1000 + .include "testutils.inc" + +; Test that we can load a binary program at a non-zero address. +; Also serves to exercise the --cris-program-offset and +; --cris-start-address options. + +; Make sure starting at the first address does fail. + fail + +; ...and that we know an offset we can jump for it to work, and all we +; have to assume is that "fail" takes no more than 64 bytes. + .p2align 6 + ba _start + nop + +; + start +x: + +; Make sure we're loaded at the linked address. Since we're re-used +; in other tests, we have to provide for non-v32 as well. + .if ..asm.arch.cris.v32 + lapcq .,$r0 + .else + move.d $pc,$r0 + subq .-x,$r0 + .endif + + cmp.d x,$r0 + bne y + nop + pass +y: + fail + +; Make sure we have enough contents for the mapping. + .data + .fill 4096,1,0 diff --git a/sim/testsuite/cris/asm/bas.ms b/sim/testsuite/cris/asm/bas.ms new file mode 100644 index 0000000..084b5bf --- /dev/null +++ b/sim/testsuite/cris/asm/bas.ms @@ -0,0 +1,102 @@ +# mach: crisv32 +# output: 0\n0\n0\nfb349abc\n0\n12124243\n0\n0\neab5baad\n0\nefb37832\n + + .include "testutils.inc" + start +x: + setf zncv + bsr 0f + nop +0: + test_cc 1 1 1 1 + move srp,r3 + sub.d 0b,r3 + dumpr3 + + bas 1f,mof + moveq 0,r0 +6: + nop + quit + +2: + move srp,r3 + sub.d 3f,r3 + dumpr3 + move srp,r4 + subq 4,r4 + move.d [r4],r3 + dumpr3 + + basc 4f,mof + nop + .dword 0x12124243 +7: + nop + quit + +8: + move mof,r3 + sub.d 7f,r3 + dumpr3 + + move mof,r4 + subq 4,r4 + move.d [r4],r3 + dumpr3 + + jasc 9f,mof + nop + .dword 0xefb37832 +0: + quit + + quit +9: + move mof,r3 + sub.d 0b,r3 + dumpr3 + + move mof,r4 + subq 4,r4 + move.d [r4],r3 + dumpr3 + + quit + +4: + move mof,r3 + sub.d 7b,r3 + dumpr3 + move mof,r4 + subq 4,r4 + move.d [r4],r3 + dumpr3 + basc 5f,bz + moveq 0,r3 + .dword 0x7634aeba + quit + + .space 32770,0 +1: + move mof,r3 + sub.d 6b,r3 + dumpr3 + + bsrc 2b + nop + .dword 0xfb349abc +3: + + quit + +5: + move mof,r3 + sub.d 7b,r3 + dumpr3 + move.d 8b,r6 + jasc r6,mof + nop + .dword 0xeab5baad +7: + quit diff --git a/sim/testsuite/cris/asm/bccb.ms b/sim/testsuite/cris/asm/bccb.ms new file mode 100644 index 0000000..da5e415 --- /dev/null +++ b/sim/testsuite/cris/asm/bccb.ms @@ -0,0 +1,181 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1c\n + + .include "testutils.inc" + start + moveq 0,r3 + + clearf nzvc + setf nzv + bcc 0f + addq 1,r3 + fail + +0: + clearf nzvc + setf nzv + bcs dofail + addq 1,r3 + + clearf nzvc + setf ncv + bne 1f + addq 1,r3 + +dofail: + fail + +1: + clearf nzvc + setf ncv + beq dofail + addq 1,r3 + + clearf nzvc + setf ncz + bvc 2f + addq 1,r3 + fail + +2: + clearf nzvc + setf ncz + bvs dofail + addq 1,r3 + + clearf nzvc + setf vcz + bpl 3f + addq 1,r3 + fail + +3: + clearf nzvc + setf vcz + bmi dofail + addq 1,r3 + + clearf nzvc + setf nv + bls dofail + addq 1,r3 + + clearf nzvc + setf nv + bhi 4f + addq 1,r3 + fail + +4: + clearf nzvc + setf zc + bge 5f + addq 1,r3 + fail + +5: + clearf nzvc + setf zc + blt dofail + addq 1,r3 + + clearf nzvc + setf c + bgt 6f + addq 1,r3 + fail + +6: + clearf nzvc + setf c + ble dofail + addq 1,r3 + +;;;;;;;;;; + + setf nzvc + clearf nzv + bcc dofail + addq 1,r3 + + setf nzvc + clearf nzv + bcs 0f + addq 1,r3 + fail + +0: + setf nzvc + clearf ncv + bne dofail + addq 1,r3 + + setf nzvc + clearf ncv + beq 1f + addq 1,r3 + fail + +1: + setf nzvc + clearf ncz + bvc dofail + addq 1,r3 + + setf nzvc + clearf ncz + bvs 2f + addq 1,r3 + fail + +2: + setf nzvc + clearf vcz + bpl dofail + addq 1,r3 + + setf nzvc + clearf vcz + bmi 3f + addq 1,r3 + fail + +3: + setf nzvc + clearf nv + bls 4f + addq 1,r3 + fail + +4: + setf nzvc + clearf nv + bhi dofail + addq 1,r3 + + setf zvc + clearf nzc + bge dofail + addq 1,r3 + + setf nzc + clearf vzc + blt 5f + addq 1,r3 + fail + +5: + setf nzvc + clearf c + bgt dofail + addq 1,r3 + + setf nzvc + clearf c + ble 6f + addq 1,r3 + fail + +6: + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/bdapc.ms b/sim/testsuite/cris/asm/bdapc.ms new file mode 100644 index 0000000..cfedd8b --- /dev/null +++ b/sim/testsuite/cris/asm/bdapc.ms @@ -0,0 +1,57 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: 4455aa77\n4455aa77\nee19ccff\n88ccee19\nff22\n4455aa77\nff224455\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + .dword 0xb232765a + + start + moveq -1,r0 + moveq -1,r2 + move.d x-32768,r5 + move.d [r5+32769],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + addu.w 32770,r5 + bdap.w -1,r5 + move.d [r0],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + bdap.d 4,r5 + move.d [r2+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; ee19ccff + + bdap.b 2,r2 + move.d [r3],r3 + test_move_cc 1 0 0 0 + dumpr3 ; 88ccee19 + + bdap.b 3,r5 + movu.w [r4+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff22 + + bdap.b -4,r4 + move.d [r6+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + bdap.w 2,r6 + move.d [r3],r9 + test_move_cc 1 0 0 0 + dumpr3 ; ff224455 + + add.d 76789885,r5 + bdap.d -76789887,r5 + move.d [r3],r9 + test_move_cc 0 0 0 0 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/cris/asm/bdapm.ms b/sim/testsuite/cris/asm/bdapm.ms new file mode 100644 index 0000000..26bc4ad --- /dev/null +++ b/sim/testsuite/cris/asm/bdapm.ms @@ -0,0 +1,56 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 +y: + .dword 32769 + .word -1 + .dword 5 + .byte 3,-4 + .word 2 + .dword -76789887 + + start + moveq -1,r0 + move.d x-32768,r5 + move.d y,r13 + bdap.d [r13+],r5 + move.d [r3],r9 + test_move_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + addu.w 32770,r5 + bdap.w [r13+],r5 + move.d [r9+],r3 + dumpr3 ; 4455aa77 + + bdap.d [r13],r9 + move.d [r3],r7 + addq 4,r13 + dumpr3 ; ee19ccff + + bdap.b [r13+],r5 + movu.w [r7+],r3 + dumpr3 ; ff22 + + bdap.b [r13],r7 + move.d [r7+],r3 + addq 1,r13 + dumpr3 ; 4455aa77 + + bdap.w [r13],r7 + move.d [r3],r3 + addq 2,r13 + dumpr3 ; ff224455 + + add.d 76789885,r5 + bdap.d [r13+],r5 + move.d [r3],r9 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/cris/asm/bdapq.ms b/sim/testsuite/cris/asm/bdapq.ms new file mode 100644 index 0000000..a0ba406 --- /dev/null +++ b/sim/testsuite/cris/asm/bdapq.ms @@ -0,0 +1,29 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: ccff2244\n88ccee19\n55aa77ff\n19cc\n0\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + .dword 0 + start + moveq -1,r0 + move.d x+4,r5 + move.d [r5+0],r3 + test_move_cc 1 0 0 0 + dumpr3 ; ccff2244 + move.d [r5=r5+4],r3 + test_move_cc 1 0 0 0 + dumpr3 ; 88ccee19 + move.d [r5=r5-8],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 55aa77ff + movu.w [r5+7],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 19cc + move.d [r5+12],r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + quit diff --git a/sim/testsuite/cris/asm/bdapqpc.ms b/sim/testsuite/cris/asm/bdapqpc.ms new file mode 100644 index 0000000..f2209ef --- /dev/null +++ b/sim/testsuite/cris/asm/bdapqpc.ms @@ -0,0 +1,30 @@ +# mach: crisv3 crisv8 crisv10 +# output: aaeebb11\nde378218\n + +# Test that the special case "X [pc+I],Y" works, where I byte-sized. + + .include "testutils.inc" + start +x: +; FIXME: Gas bugs are making this a bit harder than necessary. +; move.d [pc+y-(.+2)],r3 + move.d [pc+8],r3 +yy: + jump zz + +y: + .dword 0xaaeebb11 +y2: + .dword 0xde378218 + +zz: + dumpr3 + jump z + quit + +; Check a negative offset. + .space 50 +z: + move.d [pc+y2-(.+2)],r3 + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/biap.ms b/sim/testsuite/cris/asm/biap.ms new file mode 100644 index 0000000..a51a918 --- /dev/null +++ b/sim/testsuite/cris/asm/biap.ms @@ -0,0 +1,56 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + + start + moveq -1,r0 + move.d x-32768,r5 + move.d 32769,r6 + move.d [r5+r6.b],r3 + test_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + addu.w 32771,r5 + moveq -1,r8 + move.d [r11=r5+r8.w],r3 + test_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + moveq 5,r10 + move.d [r11+r10.b],r3 + test_cc 1 0 0 0 + dumpr3 ; ee19ccff + + subq 1,r5 + move.d r5,r8 + subq 1,r8 + moveq 1,r9 + movu.w [r12=r8+r9.d],r3 + test_cc 0 0 0 0 + dumpr3 ; ff22 + + moveq -2,r11 + move.d [r13=r12+r11.w],r3 + test_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + subq 18,r13 + moveq 5,r9 + move.d [r13+r9.d],r3 + test_cc 1 0 0 0 + dumpr3 ; ff224455 + + move.d r5,r7 + add.d 76789886,r7 + move.d -76789888/4,r12 + move.d [r7+r12.d],r3 + test_cc 0 0 0 0 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/cris/asm/boundc.ms b/sim/testsuite/cris/asm/boundc.ms new file mode 100644 index 0000000..0b2be13 --- /dev/null +++ b/sim/testsuite/cris/asm/boundc.ms @@ -0,0 +1,101 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\nffff\nffffffff\n5432f789\n2\nffff\n2\nffff\nffff\nf789\n2\n2\nff\nff\nff\n89\n0\nff\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + bound.d 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + bound.d 0xffffffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + bound.d 0xffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r3 + bound.d 0xffffffff,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + bound.d 0x5432f789,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5432f789 + + moveq -1,r3 + bound.w 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq -1,r3 + bound.w 0xffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq 2,r3 + bound.w 0xffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + bound.w 0xffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0xfedaffff,r3 + bound.w 0xffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0x78134452,r3 + bound.w 0xf789,r3 + test_move_cc 0 0 0 0 + dumpr3 ; f789 + + moveq -1,r3 + bound.b 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + bound.b 0xff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq -1,r3 + bound.b 0xff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0xff,r3 + bound.b 0xff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0xfeda49ff,r3 + bound.b 0xff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0x78134452,r3 + bound.b 0x89,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 89 + + bound.w 0,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xffff,r3 + bound.b -1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + quit diff --git a/sim/testsuite/cris/asm/boundm.ms b/sim/testsuite/cris/asm/boundm.ms new file mode 100644 index 0000000..91019dd --- /dev/null +++ b/sim/testsuite/cris/asm/boundm.ms @@ -0,0 +1,105 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: 2\n2\nffff\nffffffff\n5432f789\n2\nffff\n2\nffff\nffff\nf789\n2\n2\nff\nff\nff\n89\n0\n + + .include "testutils.inc" + .data +x: + .dword 2,-1,0xffff,-1,0x5432f789 + .word 2,0xffff,0xf789 + .byte 2,0xff,0x89,0 + + start + move.d x,r5 + + moveq -1,r3 + moveq 2,r4 + bound.d [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + bound.d [r5],r3 + test_move_cc 0 0 0 0 + addq 4,r5 + dumpr3 ; 2 + + move.d 0xffff,r3 + bound.d [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r3 + bound.d [r5+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + bound.d [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5432f789 + + moveq -1,r3 + bound.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq -1,r3 + bound.w [r5],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq 2,r3 + bound.w [r5],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + bound.w [r5],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0xfedaffff,r3 + bound.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0x78134452,r3 + bound.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; f789 + + moveq -1,r3 + bound.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + bound.b [r5],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq -1,r3 + bound.b [r5],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0xff,r3 + bound.b [r5],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0xfeda49ff,r3 + bound.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0x78134452,r3 + bound.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 89 + + bound.b [r5],r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/boundmv32.ms b/sim/testsuite/cris/asm/boundmv32.ms new file mode 100644 index 0000000..560276e --- /dev/null +++ b/sim/testsuite/cris/asm/boundmv32.ms @@ -0,0 +1,15 @@ +# mach: crisv32 +# xerror: +# output: program stopped with signal 4 (*).\n + .include "testutils.inc" + +; Check that bound with a memory operand is invalid. + start + move.d 0f,r5 + move.d r5,r3 + .byte 0xd5,0x39 ; bound.d [r5],r3 -- we can't assemble it. + pass + +0: + .dword 0b + diff --git a/sim/testsuite/cris/asm/boundr.ms b/sim/testsuite/cris/asm/boundr.ms new file mode 100644 index 0000000..053c4ae --- /dev/null +++ b/sim/testsuite/cris/asm/boundr.ms @@ -0,0 +1,125 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\nffff\nffffffff\n5432f789\n2\n2\nffff\nffff\nffff\nf789\n2\n2\nff\nff\n89\nfeda4953\nfeda4962\n0\n0\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + bound.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + moveq -1,r4 + bound.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r4 + move.d r4,r3 + bound.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r4 + move.d r4,r3 + bound.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + bound.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5432f789 + + moveq -1,r3 + moveq 2,r4 + bound.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + moveq -1,r4 + bound.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq -1,r3 + bound.w r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0xffff,r4 + move.d r4,r3 + bound.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0xfedaffff,r4 + move.d r4,r3 + bound.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + bound.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; f789 + + moveq -1,r3 + moveq 2,r4 + bound.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + moveq -1,r4 + bound.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xff,r4 + move.d r4,r3 + bound.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0xfeda49ff,r4 + move.d r4,r3 + bound.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + bound.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 89 + + move.d 0xfeda4956,r3 + move.d 0xfeda4953,r4 + bound.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; feda4953 + + move.d 0xfeda4962,r3 + move.d 0xfeda4963,r4 + bound.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; feda4962 + + move.d 0xfeda4956,r3 + move.d 0,r4 + bound.d r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xfeda4956,r4 + move.d 0,r3 + bound.d r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/break.ms b/sim/testsuite/cris/asm/break.ms new file mode 100644 index 0000000..c1a7a96 --- /dev/null +++ b/sim/testsuite/cris/asm/break.ms @@ -0,0 +1,15 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# sim: --trace-core=on +# ld: --section-start=.text=0 +# output: read-2 exec:0x00000002 -> 0x05b0\nread-2 exec:0x00000004 -> 0xe93f\n + +; First test: Must exit gracefully. + + .include "testutils.inc" + +; This first insn isn't executed (it's a filler); it would fail +; ungracefully if executed. + + startnostack + setf + quit diff --git a/sim/testsuite/cris/asm/btst.ms b/sim/testsuite/cris/asm/btst.ms new file mode 100644 index 0000000..b63e8f2 --- /dev/null +++ b/sim/testsuite/cris/asm/btst.ms @@ -0,0 +1,87 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1111\n + + .include "testutils.inc" + start + clearf nzvc + moveq -1,r3 + .if ..asm.arch.cris.v32 + .else + setf vc + .endif + btstq 0,r3 + test_cc 1 0 0 0 + + moveq 2,r3 + btstq 1,r3 + test_cc 1 0 0 0 + + moveq 4,r3 + btstq 1,r3 + test_cc 0 1 0 0 + + moveq -1,r3 + btstq 31,r3 + test_cc 1 0 0 0 + + move.d 0x5a67f19f,r3 + btstq 12,r3 + test_cc 1 0 0 0 + + move.d 0xda67f19f,r3 + move.d 29,r4 + btst r4,r3 + test_cc 0 0 0 0 + + move.d 0xda67f19f,r3 + move.d 32,r4 + btst r4,r3 + test_cc 1 0 0 0 + + move.d 0xda67f191,r3 + move.d 33,r4 + btst r4,r3 + test_cc 0 0 0 0 + + moveq -1,r3 + moveq 0,r4 + btst r4,r3 + test_cc 1 0 0 0 + + moveq 2,r3 + moveq 1,r4 + btst r4,r3 + test_cc 1 0 0 0 + + moveq -1,r3 + moveq 31,r4 + btst r4,r3 + test_cc 1 0 0 0 + + moveq 4,r3 + btstq 1,r3 + test_cc 0 1 0 0 + + moveq -1,r3 + moveq 15,r4 + btst r4,r3 + test_cc 1 0 0 0 + + move.d 0x5a67f19f,r3 + moveq 12,r4 + btst r4,r3 + test_cc 1 0 0 0 + + move.d 0x5a678000,r3 + moveq 11,r4 + btst r4,r3 + test_cc 0 1 0 0 + + move.d 0x5a67f19f,r3 + btst r3,r3 + test_cc 0 0 0 0 + + move.d 0x1111,r3 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/ccr-v10.ms b/sim/testsuite/cris/asm/ccr-v10.ms new file mode 100644 index 0000000..39602f0 --- /dev/null +++ b/sim/testsuite/cris/asm/ccr-v10.ms @@ -0,0 +1,79 @@ +# mach: crisv10 +# output: ff\nff\n0\n0\n80\n40\n20\n10\n8\n4\n2\n1\n80\n40\n20\n10\n8\n4\n2\n1\n42\n + +; Check that flag settings affect ccr and dccr and vice versa. + + .include "testutils.inc" + start + clear.d r3 + setf mbixnzvc + move ccr,r3 + dumpr3 + + clear.d r3 + setf mbixnzvc + move dccr,r3 + dumpr3 + + clear.d r3 + clearf mbixnzvc + move ccr,r3 + dumpr3 + + clear.d r3 + clearf mbixnzvc + move dccr,r3 + dumpr3 + + .macro testfr BIT REG + clear.d r3 + clearf mbixnzvc + setf \BIT + move \REG,r3 + dumpr3 + .endm + + testfr m ccr + testfr b ccr + testfr i ccr + testfr x ccr + testfr n ccr + testfr z ccr + testfr v ccr + testfr c ccr + + testfr m dccr + testfr b dccr + testfr i dccr + testfr x dccr + testfr n dccr + testfr z dccr + testfr v dccr + testfr c dccr + +; Check only the nzvc bits; do the other bits in special tests as they're +; implemented. + .macro test_get_cc N Z V C + clearf znvc + move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccr + test_cc \N \Z \V \C + setf znvc + move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),dccr + test_cc \N \Z \V \C + move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4 + setf znvc + move r4,ccr + test_cc \N \Z \V \C + clearf znvc + move r4,dccr + test_cc \N \Z \V \C + .endm + + test_get_cc 1 0 0 0 + test_get_cc 0 1 0 0 + test_get_cc 0 0 1 0 + test_get_cc 0 0 0 1 + + move.d 0x42,r3 + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/ccs-v32.ms b/sim/testsuite/cris/asm/ccs-v32.ms new file mode 100644 index 0000000..8dc6026 --- /dev/null +++ b/sim/testsuite/cris/asm/ccs-v32.ms @@ -0,0 +1,73 @@ +# mach: crisv32 +# output: bf\n0\n80\n20\n10\n8\n4\n2\n1\n40\nfade040\n3ade0040\nfade040\n42\n + +; Check flag settings. + + .include "testutils.inc" + start + clear.d r3 + setf pixnzvc ; Setting U(ser mode) would restrict tests of other flags. + move ccs,r3 + dumpr3 + + clear.d r3 + clearf puixnzvc + move ccs,r3 + dumpr3 + + .macro testf BIT + clear.d r3 + clearf puixnzvc + setf \BIT + move ccs,r3 + dumpr3 + .endm + + testf p + testf i + testf x + testf n + testf z + testf v + testf c + testf u ; Can't test i-flag or clear u after this point. + + .macro test_get_cc N Z V C + clearf znvc + move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccs + test_cc \N \Z \V \C + setf znvc + move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccs + test_cc \N \Z \V \C + move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4 + setf znvc + move r4,ccs + test_cc \N \Z \V \C + clearf znvc + move r4,ccs + test_cc \N \Z \V \C + .endm + + test_get_cc 1 0 0 0 + test_get_cc 0 1 0 0 + test_get_cc 0 0 1 0 + test_get_cc 0 0 0 1 + +; Test that the U bit sticks. + move 0x0fade000,ccs + move ccs,r3 + dumpr3 + +; Check that the M and Q bits can't be set in user mode. + move 0xfade0000,ccs + move ccs,r3 + dumpr3 + + move 0x0fade000,ccs + move ccs,r3 + dumpr3 + + move.d 0x42,r3 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/clearfv10.ms b/sim/testsuite/cris/asm/clearfv10.ms new file mode 100644 index 0000000..d910842 --- /dev/null +++ b/sim/testsuite/cris/asm/clearfv10.ms @@ -0,0 +1,12 @@ +# mach: crisv10 +# output: ef\n + +; Check that "clearf x" doesn't trivially fail. + + .include "testutils.inc" + start + setf mbixnzvc + clearf x ; Actually, x would be cleared by almost-all other insns. + move dccr,r3 + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/clearfv32.ms b/sim/testsuite/cris/asm/clearfv32.ms new file mode 100644 index 0000000..b1dd3de --- /dev/null +++ b/sim/testsuite/cris/asm/clearfv32.ms @@ -0,0 +1,12 @@ +# mach: crisv32 +# output: ef\n + +; Check that "clearf x" doesn't trivially fail. + + .include "testutils.inc" + start + setf puixnzvc + clearf x ; Actually, x would be cleared by almost-all other insns. + move ccs,r3 + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/clrjmp1.ms b/sim/testsuite/cris/asm/clrjmp1.ms new file mode 100644 index 0000000..1a76e7f --- /dev/null +++ b/sim/testsuite/cris/asm/clrjmp1.ms @@ -0,0 +1,36 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffff00\n + +; A bug resulting in a non-effectual clear.b discovered running the GCC +; testsuite; jump actually wrote to p0. + + .include "testutils.inc" + + start + jump 1f + nop + .p2align 8 +1: + move.d y,r4 + + .if 0 == ..asm.arch.cris.v32 +; There was a bug causing this insn to set special register p0 +; (byte-clear) to 8 (low 8 bits of location after insn). + jump [r4+] + .endif + +1: + move.d 0f,r4 + +; The corresponding bug would cause this insn too, to set p0. + jump r4 + nop + quit +0: + moveq -1,r3 + clear.b r3 + dumpr3 + quit + +y: + .dword 1b diff --git a/sim/testsuite/cris/asm/cmpc.ms b/sim/testsuite/cris/asm/cmpc.ms new file mode 100644 index 0000000..8600f5f --- /dev/null +++ b/sim/testsuite/cris/asm/cmpc.ms @@ -0,0 +1,86 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649282\n + + .include "testutils.inc" + start + moveq -1,r3 + cmp.d -2,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + cmp.d 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + cmp.d -0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + moveq -1,r3 + cmp.d 1,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + cmp.d -0x5432f789,r3 + test_cc 1 0 1 1 + dumpr3 ; 78134452 + + moveq -1,r3 + cmp.w -2,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + cmp.w 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + cmp.w 1,r3 + test_cc 1 0 0 0 + dumpr3 ; ffff + + move.d 0xfedaffff,r3 + cmp.w 1,r3 + test_cc 1 0 0 0 + dumpr3 ; fedaffff + + move.d 0x78134452,r3 + cmp.w 0x877,r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + moveq -1,r3 + cmp.b -2,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + cmp.b 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xff,r3 + cmp.b 1,r3 + test_cc 1 0 0 0 + dumpr3 ; ff + + move.d 0xfeda49ff,r3 + cmp.b 1,r3 + test_cc 1 0 0 0 + dumpr3 ; feda49ff + + move.d 0x78134452,r3 + cmp.b 0x77,r3 + test_cc 1 0 0 1 + dumpr3 ; 78134452 + + move.d 0x85649282,r3 + cmp.b 0x82,r3 + test_cc 0 1 0 0 + dumpr3 ; 85649282 + + quit diff --git a/sim/testsuite/cris/asm/cmpm.ms b/sim/testsuite/cris/asm/cmpm.ms new file mode 100644 index 0000000..753f2d3 --- /dev/null +++ b/sim/testsuite/cris/asm/cmpm.ms @@ -0,0 +1,96 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649222\n + + .include "testutils.inc" + .data +x: + .dword -2,1,-0xffff,1,-0x5432f789 + .word -2,1,1,0x877 + .byte -2,1,0x77 + .byte 0x22 + + start + moveq -1,r3 + move.d x,r5 + cmp.d [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + cmp.d [r5],r3 + test_cc 0 0 0 0 + addq 4,r5 + dumpr3 ; 2 + + move.d 0xffff,r3 + cmp.d [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + moveq -1,r3 + cmp.d [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + cmp.d [r5+],r3 + test_cc 1 0 1 1 + dumpr3 ; 78134452 + + moveq -1,r3 + cmp.w [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + cmp.w [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + cmp.w [r5],r3 + test_cc 1 0 0 0 + dumpr3 ; ffff + + move.d 0xfedaffff,r3 + cmp.w [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; fedaffff + + move.d 0x78134452,r3 + cmp.w [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + moveq -1,r3 + cmp.b [r5],r3 + test_cc 0 0 0 0 + addq 1,r5 + dumpr3 ; ffffffff + + moveq 2,r3 + cmp.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xff,r3 + cmp.b [r5],r3 + test_cc 1 0 0 0 + dumpr3 ; ff + + move.d 0xfeda49ff,r3 + cmp.b [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; feda49ff + + move.d 0x78134452,r3 + cmp.b [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; 78134452 + + move.d 0x85649222,r3 + cmp.b [r5],r3 + test_cc 0 1 0 0 + dumpr3 ; 85649222 + + quit diff --git a/sim/testsuite/cris/asm/cmpq.ms b/sim/testsuite/cris/asm/cmpq.ms new file mode 100644 index 0000000..7e40be4 --- /dev/null +++ b/sim/testsuite/cris/asm/cmpq.ms @@ -0,0 +1,75 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1\n1f\n1f\nffffffe1\nffffffe1\nffffffe0\n0\n0\nffffffff\nffffffff\n10000\n100\n5678900\n + + .include "testutils.inc" + start + moveq 1,r3 + cmpq 1,r3 + test_cc 0 1 0 0 + dumpr3 ; 1 + + cmpq -1,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + cmpq 31,r3 + test_cc 1 0 0 1 + dumpr3 ; 1 + + moveq 31,r3 + cmpq 31,r3 + test_cc 0 1 0 0 + dumpr3 ; 1f + + cmpq -31,r3 + test_cc 0 0 0 1 + dumpr3 ; 1f + + movs.b -31,r3 + cmpq -31,r3 + test_cc 0 1 0 0 + dumpr3 ; ffffffe1 + + cmpq -32,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffe1 + + movs.b -32,r3 + cmpq -32,r3 + test_cc 0 1 0 0 + dumpr3 ; ffffffe0 + + moveq 0,r3 + cmpq 1,r3 + test_cc 1 0 0 1 + dumpr3 ; 0 + + cmpq -32,r3 + test_cc 0 0 0 1 + dumpr3 ; 0 + + moveq -1,r3 + cmpq 1,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffffff + + cmpq -1,r3 + test_cc 0 1 0 0 + dumpr3 ; ffffffff + + move.d 0x10000,r3 + cmpq 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 10000 + + move.d 0x100,r3 + cmpq 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 100 + + move.d 0x5678900,r3 + cmpq 7,r3 + test_cc 0 0 0 0 + dumpr3 ; 5678900 + + quit diff --git a/sim/testsuite/cris/asm/cmpr.ms b/sim/testsuite/cris/asm/cmpr.ms new file mode 100644 index 0000000..6730a00 --- /dev/null +++ b/sim/testsuite/cris/asm/cmpr.ms @@ -0,0 +1,102 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649222\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq -2,r4 + cmp.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + cmp.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + move.d -0xffff,r4 + cmp.d r4,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + moveq 1,r4 + moveq -1,r3 + cmp.d r4,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d -0x5432f789,r4 + move.d 0x78134452,r3 + cmp.d r4,r3 + test_cc 1 0 1 1 + dumpr3 ; 78134452 + + moveq -1,r3 + moveq -2,r4 + cmp.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + cmp.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + move.d -0xffff,r4 + cmp.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; ffff + + move.d 0xfedaffff,r3 + move.d -0xfedaffff,r4 + cmp.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fedaffff + + move.d -0x5432f789,r4 + move.d 0x78134452,r3 + cmp.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + moveq -1,r3 + moveq -2,r4 + cmp.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + cmp.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d -0xff,r4 + move.d 0xff,r3 + cmp.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; ff + + move.d -0xfeda49ff,r4 + move.d 0xfeda49ff,r3 + cmp.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; feda49ff + + move.d -0x5432f789,r4 + move.d 0x78134452,r3 + cmp.b r4,r3 + test_cc 1 0 0 1 + dumpr3 ; 78134452 + + move.d 0x85649222,r3 + move.d 0x77445622,r4 + cmp.b r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 85649222 + + quit diff --git a/sim/testsuite/cris/asm/cmpxc.ms b/sim/testsuite/cris/asm/cmpxc.ms new file mode 100644 index 0000000..d9acd8f --- /dev/null +++ b/sim/testsuite/cris/asm/cmpxc.ms @@ -0,0 +1,92 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\n2\n2\nffff\nffff\nffff\nffff\nffffffff\nffffffff\nffffffff\n78134452\n78134452\n78134452\n78134452\n4452\n80000032\n + + .include "testutils.inc" + start + moveq 2,r3 + cmps.b 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; 2 + + moveq 2,r3 + cmps.w 0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; 2 + + moveq 2,r3 + cmpu.b 0xff,r3 + test_cc 1 0 0 1 + dumpr3 ; 2 + + moveq 2,r3 + move.d 0xffffffff,r4 + cmpu.w -1,r3 + test_cc 1 0 0 1 + dumpr3 ; 2 + + move.d 0xffff,r3 + cmpu.b -1,r3 + test_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0xffff,r3 + cmpu.w -1,r3 + test_cc 0 1 0 0 + dumpr3 ; ffff + + move.d 0xffff,r3 + cmps.b 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + move.d 0xffff,r3 + cmps.w 0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + moveq -1,r3 + cmps.b 0xff,r3 + test_cc 0 1 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + cmps.w 0xff,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + cmps.w 0xffff,r3 + test_cc 0 1 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + cmpu.b 0x89,r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + move.d 0x78134452,r3 + cmps.b 0x89,r3 + test_cc 0 0 0 1 + dumpr3 ; 78134452 + + move.d 0x78134452,r3 + cmpu.w 0xf789,r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + move.d 0x78134452,r3 + cmps.w 0xf789,r3 + test_cc 0 0 0 1 + dumpr3 ; 78134452 + + move.d 0x4452,r3 + cmps.w 0x8002,r3 + test_cc 0 0 0 1 + dumpr3 ; 4452 + + move.d 0x80000032,r3 + cmpu.w 0x764,r3 + test_cc 0 0 1 0 + dumpr3 ; 80000032 + + quit diff --git a/sim/testsuite/cris/asm/cmpxm.ms b/sim/testsuite/cris/asm/cmpxm.ms new file mode 100644 index 0000000..6a87ab04 --- /dev/null +++ b/sim/testsuite/cris/asm/cmpxm.ms @@ -0,0 +1,106 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\n2\n2\nffff\nffff\nffff\nffff\nffffffff\nffffffff\nffffffff\n78134452\n78134452\n78134452\n78134452\n4452\n80000032\n + + .include "testutils.inc" + .data +x: + .byte 0xff + .word 0xffff + .word 0xff + .word 0xffff + .byte 0x89 + .word 0xf789 + .word 0x8002 + .word 0x764 + + start + moveq 2,r3 + move.d x,r5 + cmps.b [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 2 + + moveq 2,r3 + cmps.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 2 + + moveq 2,r3 + subq 3,r5 + cmpu.b [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; 2 + + moveq 2,r3 + cmpu.w [r5+],r3 + test_cc 1 0 0 1 + subq 3,r5 + dumpr3 ; 2 + + move.d 0xffff,r3 + cmpu.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0xffff,r3 + cmpu.w [r5],r3 + test_cc 0 1 0 0 + dumpr3 ; ffff + + move.d 0xffff,r3 + cmps.b [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + move.d 0xffff,r3 + cmps.w [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + moveq -1,r3 + cmps.b [r5],r3 + test_cc 0 1 0 0 + addq 3,r5 + dumpr3 ; ffffffff + + moveq -1,r3 + cmps.w [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + cmps.w [r5+],r3 + test_cc 0 1 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + cmpu.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + move.d 0x78134452,r3 + cmps.b [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 78134452 + + move.d 0x78134452,r3 + cmpu.w [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + move.d 0x78134452,r3 + cmps.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 78134452 + + move.d 0x4452,r3 + cmps.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 4452 + + move.d 0x80000032,r3 + cmpu.w [r5+],r3 + test_cc 0 0 1 0 + dumpr3 ; 80000032 + + quit diff --git a/sim/testsuite/cris/asm/dflags.ms b/sim/testsuite/cris/asm/dflags.ms new file mode 100644 index 0000000..2735014 --- /dev/null +++ b/sim/testsuite/cris/asm/dflags.ms @@ -0,0 +1,62 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 31\n + +; Check that flag settings in the delay slot for a conditional branch do +; not affect the branch. + + .include "testutils.inc" + + start + moveq 1,r3 + moveq 0,r4 + +; 8-bit branches. + + move.d r4,r4 + bne 0f + move.d r3,r3 + bne 1f + move.d r4,r4 + nop +0: + quit + +1: + move.d r3,r3 + beq 0b + move.d r4,r4 + beq 4f + move.d r3,r3 + nop + quit +4: + jump 2f + nop + .space 1000 + +; 16-bit branches + +2: + move.d r4,r4 + bne 0b + move.d r3,r3 + bne 3f + move.d r4,r4 + nop + quit + .space 1000 + +3: + move.d r3,r3 + beq 0b + move.d r4,r4 + beq 4f + move.d r3,r3 + nop + quit + .space 1000 + +4: + move.d 0x31,r3 + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/dip.ms b/sim/testsuite/cris/asm/dip.ms new file mode 100644 index 0000000..ff79f22 --- /dev/null +++ b/sim/testsuite/cris/asm/dip.ms @@ -0,0 +1,41 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: 4455aa77\nee19ccff\nb232765a\nff22\n5a88ccee\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + .dword 0xb232765a +y: + .dword x+12 + .dword x+5 + .dword x+9 + + start + moveq -1,r0 + moveq -1,r2 + move.d [x+1],r3 + test_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + move.d [x+6],r3 + test_cc 1 0 0 0 + dumpr3 ; ee19ccff + + move.d y,r8 + move.d [[r8+]],r3 + test_cc 1 0 0 0 + dumpr3 ; b232765a + + movu.w [[r8]],r3 + test_cc 0 0 0 0 + dumpr3 ; ff22 + addq 4,r8 + + move.d [[r8]],r3 + test_cc 0 0 0 0 + dumpr3 ; 5a88ccee + + quit diff --git a/sim/testsuite/cris/asm/dstep.ms b/sim/testsuite/cris/asm/dstep.ms new file mode 100644 index 0000000..8b32240 --- /dev/null +++ b/sim/testsuite/cris/asm/dstep.ms @@ -0,0 +1,42 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: fffffffc\n4\nffff\nfffffffe\n9bf3911b\n0\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + dstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffc + + moveq 2,r3 + moveq -1,r4 + dstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4 + + move.d 0xffff,r4 + move.d r4,r3 + dstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r4 + move.d r4,r3 + dstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + dstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 9bf3911b + + move.d 0xffff,r3 + move.d 0x1fffe,r4 + dstep r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/fidxd.ms b/sim/testsuite/cris/asm/fidxd.ms new file mode 100644 index 0000000..8158682 --- /dev/null +++ b/sim/testsuite/cris/asm/fidxd.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# xerror: +# output: FIDXD isn't implemented\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + fidxd [r3] + + quit diff --git a/sim/testsuite/cris/asm/fidxi.ms b/sim/testsuite/cris/asm/fidxi.ms new file mode 100644 index 0000000..1c41ed4 --- /dev/null +++ b/sim/testsuite/cris/asm/fidxi.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# xerror: +# output: FIDXI isn't implemented\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + fidxi [r5] + + quit diff --git a/sim/testsuite/cris/asm/ftagd.ms b/sim/testsuite/cris/asm/ftagd.ms new file mode 100644 index 0000000..74d4de3 --- /dev/null +++ b/sim/testsuite/cris/asm/ftagd.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# xerror: +# output: FTAGD isn't implemented\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + ftagd [r11] + + quit diff --git a/sim/testsuite/cris/asm/ftagi.ms b/sim/testsuite/cris/asm/ftagi.ms new file mode 100644 index 0000000..187d22d --- /dev/null +++ b/sim/testsuite/cris/asm/ftagi.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# xerror: +# output: FTAGI isn't implemented\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + ftagi [r8] + + quit diff --git a/sim/testsuite/cris/asm/halt.ms b/sim/testsuite/cris/asm/halt.ms new file mode 100644 index 0000000..fb4dcb0 --- /dev/null +++ b/sim/testsuite/cris/asm/halt.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# xerror: +# output: HALT isn't implemented\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + halt + + quit diff --git a/sim/testsuite/cris/asm/io1.ms b/sim/testsuite/cris/asm/io1.ms new file mode 100644 index 0000000..3d252ae --- /dev/null +++ b/sim/testsuite/cris/asm/io1.ms @@ -0,0 +1,8 @@ +# mach: crisv32 +# sim: --cris-900000xx --memory-region 0x90000000,0x10 +# xerror: +# output: /core/cris_900000xx: memory map 0:0x90000000..0x900000ff (256 bytes) overlaps 0:0x90000000..0x9000000f (16 bytes)\nQuit Simulator\n + +; Check that I/O region overlap is detected. + + .include "nopv32t.ms" diff --git a/sim/testsuite/cris/asm/io2.ms b/sim/testsuite/cris/asm/io2.ms new file mode 100644 index 0000000..f6341d3 --- /dev/null +++ b/sim/testsuite/cris/asm/io2.ms @@ -0,0 +1,18 @@ +# mach: crisv32 +# sim: --cris-900000xx +# xerror: +# output: b1e\n + +; Check correct "fail" exit. + + .include "testutils.inc" + start + move.d 0xb1e,$r3 + dumpr3 + move.d 0x90000008,$acr + move.d $acr,[$acr] + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/cris/asm/io3.ms b/sim/testsuite/cris/asm/io3.ms new file mode 100644 index 0000000..664dc61 --- /dev/null +++ b/sim/testsuite/cris/asm/io3.ms @@ -0,0 +1,17 @@ +# mach: crisv32 +# sim: --cris-900000xx +# output: ce11d0c\n + +; Check correct "pass" exit. + + .include "testutils.inc" + start + move.d 0x0ce11d0c,$r3 + dumpr3 + move.d 0x90000004,$acr + move.d $acr,[$acr] + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/cris/asm/io4.ms b/sim/testsuite/cris/asm/io4.ms new file mode 100644 index 0000000..f925dbd --- /dev/null +++ b/sim/testsuite/cris/asm/io4.ms @@ -0,0 +1,18 @@ +# mach: crisv32 +# xerror: +# output: b1e\n + +; Check correct "fail" exit. + + .include "testutils.inc" + start + move.d 0xb1e,$r3 + dumpr3 + moveq 1,$r9 + moveq 2,$r10 + break 13 + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/cris/asm/io5.ms b/sim/testsuite/cris/asm/io5.ms new file mode 100644 index 0000000..178a4d7 --- /dev/null +++ b/sim/testsuite/cris/asm/io5.ms @@ -0,0 +1,17 @@ +# mach: crisv32 +# output: ce11d0c\n + +; Check correct "pass" exit. + + .include "testutils.inc" + start + move.d 0x0ce11d0c,$r3 + dumpr3 + moveq 1,$r9 + moveq 0,$r10 + break 13 + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/cris/asm/io6.ms b/sim/testsuite/cris/asm/io6.ms new file mode 100644 index 0000000..3af3536 --- /dev/null +++ b/sim/testsuite/cris/asm/io6.ms @@ -0,0 +1,22 @@ +# mach: crisv32 +# ld: --section-start=.text=0 +# sim: --cris-900000xx +# xerror: +# output: b1e\n +# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n +# output: program stopped with signal 11 (*).\n + +; Check that invalid access to the simulator area is recognized. +; "FAIL" area. + + .include "testutils.inc" + start + move.d 0xb1e,$r3 + dumpr3 + move.d 0x90000008,$acr + clear.d [$acr] + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/cris/asm/io7.ms b/sim/testsuite/cris/asm/io7.ms new file mode 100644 index 0000000..84488e9 --- /dev/null +++ b/sim/testsuite/cris/asm/io7.ms @@ -0,0 +1,22 @@ +# mach: crisv32 +# ld: --section-start=.text=0 +# sim: --cris-900000xx +# xerror: +# output: ce11d0c\n +# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n +# output: program stopped with signal 11 (*).\n + +; Check that invalid access to the simulator area is recognized. +; "PASS" area. + + .include "testutils.inc" + start + move.d 0x0ce11d0c,$r3 + dumpr3 + move.d 0x90000004,$acr + clear.d [$acr] + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/cris/asm/io8.ms b/sim/testsuite/cris/asm/io8.ms new file mode 100644 index 0000000..49163fd --- /dev/null +++ b/sim/testsuite/cris/asm/io8.ms @@ -0,0 +1,21 @@ +# mach: crisv32 +# ld: --section-start=.text=0 +# xerror: +# output: b1e\n +# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n +# output: program stopped with signal 11 (*).\n + +; Check invalid access valid with --cris-900000xx. +; "FAIL" area. + + .include "testutils.inc" + start + move.d 0xb1e,$r3 + dumpr3 + move.d 0x90000008,$acr + move.d $acr,[$acr] + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/cris/asm/io9.ms b/sim/testsuite/cris/asm/io9.ms new file mode 100644 index 0000000..3b929a3 --- /dev/null +++ b/sim/testsuite/cris/asm/io9.ms @@ -0,0 +1,21 @@ +# mach: crisv32 +# ld: --section-start=.text=0 +# xerror: +# output: ce11d0c\n +# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n +# output: program stopped with signal 11 (*).\n + +; Check invalid access valid with --cris-900000xx. +; "PASS" area. + + .include "testutils.inc" + start + move.d 0x0ce11d0c,$r3 + dumpr3 + move.d 0x90000004,$acr + move.d $acr,[$acr] + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/cris/asm/jsr.ms b/sim/testsuite/cris/asm/jsr.ms new file mode 100644 index 0000000..c684fd3 --- /dev/null +++ b/sim/testsuite/cris/asm/jsr.ms @@ -0,0 +1,86 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 0\n0\n0\n0\n0\n0\n + +# Test that jsr Rn and jsr [PC+] work. + + .include "testutils.inc" + start +x: + move.d 0f,r6 + setf nzvc + jsr r6 + .if ..asm.arch.cris.v32 + nop + .endif +0: + test_move_cc 1 1 1 1 + move srp,r3 + sub.d 0b,r3 + dumpr3 + + move.d 1f,r0 + setf nzvc + jsr r0 + .if ..asm.arch.cris.v32 + moveq 0,r0 + .endif +6: + nop + quit + +2: + test_move_cc 0 0 0 0 + move srp,r3 + sub.d 3f,r3 + dumpr3 + jsr 4f + .if ..asm.arch.cris.v32 + nop + .endif +7: + nop + quit + +; Can't use local label 8 or 9, as they're used by test_move_cc. +y: + move srp,r3 + sub.d 7b,r3 + dumpr3 + quit + +4: + move srp,r3 + sub.d 7b,r3 + dumpr3 + move.d 5f,r3 + jump r3 + .if ..asm.arch.cris.v32 + moveq 0,r3 + .endif + quit + + .space 32770,0 +1: + test_move_cc 1 1 1 1 + move srp,r3 + sub.d 6b,r3 + dumpr3 + + clearf cznv + jsr 2b + .if ..asm.arch.cris.v32 + nop + .endif +3: + + quit + +5: + move srp,r3 + sub.d 7b,r3 + dumpr3 + jump y + .if ..asm.arch.cris.v32 + nop + .endif + quit diff --git a/sim/testsuite/cris/asm/jsrmv10.ms b/sim/testsuite/cris/asm/jsrmv10.ms new file mode 100644 index 0000000..fa9af06 --- /dev/null +++ b/sim/testsuite/cris/asm/jsrmv10.ms @@ -0,0 +1,40 @@ +# mach: crisv3 crisv8 crisv10 +# output: 23\n + +# Test that jsr [] records the correct return-address. + + .include "testutils.inc" + start +x: + moveq 0,r3 + jsr [z] + addq 1,r3 + nop + nop + nop + nop + nop + move.d w,r2 + jsr [r2] + addq 1,r3 + nop + nop + nop + nop + nop + dumpr3 ; 23 + quit +y: + ret + addq 1,r3 + quit + +v: + ret + addq 32,r3 + quit + +z: + .dword y +w: + .dword v diff --git a/sim/testsuite/cris/asm/jumpmp.ms b/sim/testsuite/cris/asm/jumpmp.ms new file mode 100644 index 0000000..dd21e9c --- /dev/null +++ b/sim/testsuite/cris/asm/jumpmp.ms @@ -0,0 +1,21 @@ +# mach: crisv3 crisv8 crisv10 +# output: bed0bed1\n + +# Test that jump indirect clears the "prefixed" +# bit. + + .include "testutils.inc" + .data +w: + .dword x1 +y: + .dword 0xbed0bed1 + + start +x: + move.d y,r3 + jump [w] +x1: + move.d [r3],r3 + dumpr3 ; bed0bed1 + quit diff --git a/sim/testsuite/cris/asm/jumppv32.ms b/sim/testsuite/cris/asm/jumppv32.ms new file mode 100644 index 0000000..c37f42d --- /dev/null +++ b/sim/testsuite/cris/asm/jumppv32.ms @@ -0,0 +1,28 @@ +# mach: crisv32 +# output: 2222\n + +# Test that jump Pd works. + + .include "testutils.inc" + start +x: + setf zvnc + move 0f,srp + test_cc 1 1 1 1 + jump srp + nop + quit + +0: + test_cc 1 1 1 1 + move 1f,mof + jump mof + nop + quit + + .space 32768,0 + quit +1: + move.d 0x2222,r3 + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/lapc.ms b/sim/testsuite/cris/asm/lapc.ms new file mode 100644 index 0000000..bacd881 --- /dev/null +++ b/sim/testsuite/cris/asm/lapc.ms @@ -0,0 +1,78 @@ +# mach: crisv32 +# output: 0\n0\nfffffffa\nfffffffe\nffffffda\n1e\n1e\n0\n + + .include "testutils.inc" + +; To accommodate dumpr3 with more than one instruction, keep it +; out of lapc operand ranges and difference calculations. + + start + lapc.d 0f,r3 +0: + sub.d .,r3 + dumpr3 ; 0 + + lapcq 0f,r3 +0: + sub.d .,r3 + dumpr3 ; 0 + + lapc.d .,r3 + sub.d .,r3 + dumpr3 ; fffffffa + + lapcq .,r3 + sub.d .,r3 + dumpr3 ; fffffffe + +0: + .rept 16 + nop + .endr + lapc.d 0b,r3 + sub.d .,r3 + dumpr3 ; ffffffda + + setf zcvn + lapc.d 0f,r3 + test_cc 1 1 1 1 + sub.d .,r3 + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop +0: + dumpr3 ; 1e +0: + lapcq 0f,r3 + sub.d 0b,r3 + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop +0: + dumpr3 ; 1e + clearf cn + setf zv +1: + lapcq .,r3 + test_cc 0 1 1 0 + sub.d 1b,r3 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/lsl.ms b/sim/testsuite/cris/asm/lsl.ms new file mode 100644 index 0000000..a2658b8 --- /dev/null +++ b/sim/testsuite/cris/asm/lsl.ms @@ -0,0 +1,217 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n4\n80000000\nffff8000\n7f19f000\n80000000\n0\n0\n699fc67c\nffffffff\n4\n80000000\nffff8000\n7f19f000\nda670000\nda670000\nda670000\nda67c67c\nffffffff\nfffafffe\n4\nffff0000\nffff8000\n5a67f000\nda67f100\nda67f100\nda67f100\nda67f17c\nfff3faff\nfff3fafe\n4\nffffff00\nffffff00\nffffff80\n5a67f100\n5a67f1f0\n + + .include "testutils.inc" + start + moveq -1,r3 + lslq 0,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + lslq 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4 + + moveq -1,r3 + lslq 31,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 80000000 + + moveq -1,r3 + lslq 15,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffff8000 + + move.d 0x5a67f19f,r3 + lslq 12,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 7f19f000 + + move.d 0xda67f19f,r3 + move.d 31,r4 + lsl.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 80000000 + + move.d 0xda67f19f,r3 + move.d 32,r4 + lsl.d r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xda67f19f,r3 + move.d 33,r4 + lsl.d r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xda67f19f,r3 + move.d 66,r4 + lsl.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 699fc67c + + moveq -1,r3 + moveq 0,r4 + lsl.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + lsl.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4 + + moveq -1,r3 + moveq 31,r4 + lsl.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 80000000 + + moveq -1,r3 + moveq 15,r4 + lsl.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffff8000 + + move.d 0x5a67f19f,r3 + moveq 12,r4 + lsl.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 7f19f000 + + move.d 0xda67f19f,r3 + move.d 31,r4 + lsl.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da670000 + + move.d 0xda67f19f,r3 + move.d 32,r4 + lsl.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da670000 + + move.d 0xda67f19f,r3 + move.d 33,r4 + lsl.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da670000 + + move.d 0xda67f19f,r3 + move.d 66,r4 + lsl.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67c67c + + moveq -1,r3 + moveq 0,r4 + lsl.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0xfffaffff,r3 + moveq 1,r4 + lsl.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffafffe + + moveq 2,r3 + moveq 1,r4 + lsl.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4 + + moveq -1,r3 + moveq 31,r4 + lsl.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; ffff0000 + + moveq -1,r3 + moveq 15,r4 + lsl.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffff8000 + + move.d 0x5a67f19f,r3 + moveq 12,r4 + lsl.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 5a67f000 + + move.d 0xda67f19f,r3 + move.d 31,r4 + lsl.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da67f100 + + move.d 0xda67f19f,r3 + move.d 32,r4 + lsl.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da67f100 + + move.d 0xda67f19f,r3 + move.d 33,r4 + lsl.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da67f100 + + move.d 0xda67f19f,r3 + move.d 66,r4 + lsl.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; da67f17c + + move.d 0xfff3faff,r3 + moveq 0,r4 + lsl.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fff3faff + + move.d 0xfff3faff,r3 + moveq 1,r4 + lsl.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fff3fafe + + moveq 2,r3 + moveq 1,r4 + lsl.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4 + + moveq -1,r3 + moveq 31,r4 + lsl.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + moveq 15,r4 + lsl.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + moveq 7,r4 + lsl.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffff80 + + move.d 0x5a67f19f,r3 + moveq 12,r4 + lsl.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 5a67f100 + + move.d 0x5a67f19f,r3 + moveq 4,r4 + lsl.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 5a67f1f0 + + quit diff --git a/sim/testsuite/cris/asm/lsr.ms b/sim/testsuite/cris/asm/lsr.ms new file mode 100644 index 0000000..a7c5d3d --- /dev/null +++ b/sim/testsuite/cris/asm/lsr.ms @@ -0,0 +1,217 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n1\n1\n1ffff\n5a67f\n1\n0\n0\n3699fc67\nffffffff\n1\n1\n1ffff\n5a67f\nda670000\nda670000\nda670000\nda673c67\nffffffff\nffff7fff\n1\nffff0000\nffff0001\n5a67000f\nda67f100\nda67f100\nda67f100\nda67f127\nffffffff\nffffff7f\n1\nffffff00\nffffff00\nffffff01\n5a67f100\n5a67f109\n + + .include "testutils.inc" + start + moveq -1,r3 + lsrq 0,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + lsrq 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + lsrq 31,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + lsrq 15,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1ffff + + move.d 0x5a67f19f,r3 + lsrq 12,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67f + + move.d 0xda67f19f,r3 + move.d 31,r4 + lsr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xda67f19f,r3 + move.d 32,r4 + lsr.d r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xda67f19f,r3 + move.d 33,r4 + lsr.d r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xda67f19f,r3 + move.d 66,r4 + lsr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3699fc67 + + moveq -1,r3 + moveq 0,r4 + lsr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + lsr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 31,r4 + lsr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 15,r4 + lsr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1ffff + + move.d 0x5a67f19f,r3 + moveq 12,r4 + lsr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67f + + move.d 0xda67f19f,r3 + move.d 31,r4 + lsr.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da670000 + + move.d 0xda67f19f,r3 + move.d 32,r4 + lsr.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da670000 + + move.d 0xda67f19f,r3 + move.d 33,r4 + lsr.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da670000 + + move.d 0xda67f19f,r3 + move.d 66,r4 + lsr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; da673c67 + + moveq -1,r3 + moveq 0,r4 + lsr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 1,r4 + lsr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff7fff + + moveq 2,r3 + moveq 1,r4 + lsr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 31,r4 + lsr.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; ffff0000 + + moveq -1,r3 + moveq 15,r4 + lsr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0001 + + move.d 0x5a67f19f,r3 + moveq 12,r4 + lsr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67000f + + move.d 0xda67f19f,r3 + move.d 31,r4 + lsr.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da67f100 + + move.d 0xda67f19f,r3 + move.d 32,r4 + lsr.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da67f100 + + move.d 0xda67f19f,r3 + move.d 33,r4 + lsr.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da67f100 + + move.d 0xda67f19f,r3 + move.d 66,r4 + lsr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; da67f127 + + moveq -1,r3 + moveq 0,r4 + lsr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 1,r4 + lsr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffffff7f + + moveq 2,r3 + moveq 1,r4 + lsr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 31,r4 + lsr.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + moveq 15,r4 + lsr.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + moveq 7,r4 + lsr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffffff01 + + move.d 0x5a67f19f,r3 + moveq 12,r4 + lsr.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 5a67f100 + + move.d 0x5a67f19f,r3 + moveq 4,r4 + lsr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67f109 + + quit diff --git a/sim/testsuite/cris/asm/lz.ms b/sim/testsuite/cris/asm/lz.ms new file mode 100644 index 0000000..8a4bb3c --- /dev/null +++ b/sim/testsuite/cris/asm/lz.ms @@ -0,0 +1,52 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 0\n20\n0\n1\n1\n1a\n1f\n10\n1e\n + + .include "testutils.inc" + start + moveq -1,r3 + + lz r3,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + moveq 0,r3 + lz r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 20 + + move.d 0x80000000,r4 + lz r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x40000000,r4 + lz r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0x7fffffff,r4 + lz r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 42,r3 + lz r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1a + + moveq 1,r6 + lz r6,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1f + + move.d 0xffff,r3 + lz r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 10 + + moveq 2,r5 + lz r5,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1e + + quit diff --git a/sim/testsuite/cris/asm/mcp.ms b/sim/testsuite/cris/asm/mcp.ms new file mode 100644 index 0000000..9aee39c --- /dev/null +++ b/sim/testsuite/cris/asm/mcp.ms @@ -0,0 +1,49 @@ +# mach: crisv32 +# output: fffffffe\n1\n1ffff\nfffffffe\ncc463bdc\n4c463bdc\n0\n + + .include "testutils.inc" + start + +; Set R, clear C. + move 0x100,ccs + moveq -5,r3 + move 2,mof + mcp mof,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + + moveq 2,r3 + move -1,srp + mcp srp,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move 0xffff,srp + move srp,r3 + mcp srp,r3 + test_cc 0 0 0 0 + dumpr3 ; 1ffff + + move -1,mof + move mof,r3 + mcp mof,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + + move 0x5432f789,mof + move.d 0x78134452,r3 + mcp mof,r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdc + + move 0x80000000,srp + mcp srp,r3 + test_cc 0 0 1 0 + dumpr3 ; 4c463bdc + + move 0xb3b9c423,srp + mcp srp,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/movdelsr1.ms b/sim/testsuite/cris/asm/movdelsr1.ms new file mode 100644 index 0000000..fe33d67 --- /dev/null +++ b/sim/testsuite/cris/asm/movdelsr1.ms @@ -0,0 +1,33 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: aa117acd\n +# output: eeaabb42\n + +; Bug with move to special register in delay slot, due to +; special flush-insn-cache simulator use. Ordinary move worked; +; special register caused branch to fail. + + .include "testutils.inc" + start + move -1,srp + + move.d 0xaa117acd,r1 + moveq 3,r9 + cmpq 1,r9 + bhi 0f + move.d r1,r3 + + fail +0: + dumpr3 + + move.d 0xeeaabb42,r1 + moveq 3,r9 + cmpq 1,r9 + bhi 0f + move r1,srp + + fail +0: + move srp,r3 + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/movecpc.ms b/sim/testsuite/cris/asm/movecpc.ms new file mode 100644 index 0000000..880a0f8 --- /dev/null +++ b/sim/testsuite/cris/asm/movecpc.ms @@ -0,0 +1,19 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register * PC is not implemented.\nprogram stopped with signal 5 (*).\n + +# We deliberately match both "read from" and "write to" above. + + .include "testutils.inc" + startnostack + moveq -1,r3 + move.b 0x42,pc + dumpr3 + + move.w 0x4321,pc + dumpr3 + + move.d 0x76543210,pc + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movecr.ms b/sim/testsuite/cris/asm/movecr.ms new file mode 100644 index 0000000..01bf7f0 --- /dev/null +++ b/sim/testsuite/cris/asm/movecr.ms @@ -0,0 +1,37 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n + +; Move constant byte, word, dword to register. Check that no extension is +; performed, that only part of the register is set. + + .include "testutils.inc" + startnostack + moveq -1,r3 + move.b 0x42,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r3 + move.b 0x94,r3 + test_move_cc 1 0 0 0 + dumpr3 + + moveq -1,r3 + move.w 0x4321,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r3 + move.w 0x9234,r3 + test_move_cc 1 0 0 0 + dumpr3 + + move.d 0x76543210,r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.w 0,r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movecrt10.ms b/sim/testsuite/cris/asm/movecrt10.ms new file mode 100644 index 0000000..d965bbc --- /dev/null +++ b/sim/testsuite/cris/asm/movecrt10.ms @@ -0,0 +1,17 @@ +#mach: crisv10 +#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n +#output: Basic clock cycles, total @: 82\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "movecr.ms" + +# This test-case is accidentally the same; gets the same cycle +# count as movecrt32.ms, but please keep them separate. diff --git a/sim/testsuite/cris/asm/movecrt32.ms b/sim/testsuite/cris/asm/movecrt32.ms new file mode 100644 index 0000000..75833a4 --- /dev/null +++ b/sim/testsuite/cris/asm/movecrt32.ms @@ -0,0 +1,14 @@ +#mach: crisv32 +#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n +#output: Basic clock cycles, total @: 82\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "movecr.ms" diff --git a/sim/testsuite/cris/asm/movect10.ms b/sim/testsuite/cris/asm/movect10.ms new file mode 100644 index 0000000..f1e3229e --- /dev/null +++ b/sim/testsuite/cris/asm/movect10.ms @@ -0,0 +1,18 @@ +#mach: crisv10 +#output: Basic clock cycles, total @: 3\n +#output: Memory source stall cycles: 1\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + + .include "testutils.inc" + startnostack + nop + move.d 0xff004567,r5 + break 15 diff --git a/sim/testsuite/cris/asm/movei.ms b/sim/testsuite/cris/asm/movei.ms new file mode 100644 index 0000000..8d55ae1 --- /dev/null +++ b/sim/testsuite/cris/asm/movei.ms @@ -0,0 +1,47 @@ +# mach: crisv32 +# output: fffffffe\n +# output: fffffffe\n + +; Check basic integral-write semantics regarding flags. + + .include "testutils.inc" + start + +; A write that works. Check that flags are set correspondingly. + move.d d,r4 + moveq -2,r5 + setf c + clearf p + move.d [r4],r3 + ax + move.d r5,[r4] + move.d [r4],r3 + + bcc 0f + nop + fail + +0: + dumpr3 ; fffffffe + +; A write that fails; check flags too. + move.d d,r4 + moveq 23,r5 + setf p + clearf c + move.d [r4],r3 + ax + move.d r5,[r4] + move.d [r4],r3 + + bcs 0f + nop + fail + +0: + dumpr3 ; fffffffe + quit + + .data +d: + .dword 42424242 diff --git a/sim/testsuite/cris/asm/movempc.ms b/sim/testsuite/cris/asm/movempc.ms new file mode 100644 index 0000000..cbbfcc1 --- /dev/null +++ b/sim/testsuite/cris/asm/movempc.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + move.d _start,r12 + move.d [r12],pc diff --git a/sim/testsuite/cris/asm/movemr.ms b/sim/testsuite/cris/asm/movemr.ms new file mode 100644 index 0000000..02f0085 --- /dev/null +++ b/sim/testsuite/cris/asm/movemr.ms @@ -0,0 +1,79 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 12345678\n10234567\n12345678\n12344567\n12344523\n76543210\nffffffaa\naa\n9911\nffff9911\n78\n56\n3456\n6712\n + + .include "testutils.inc" + start + + .data +mem1: + .dword 0x12345678 +mem2: + .word 0x4567 +mem3: + .byte 0x23 + .dword 0x76543210 + .byte 0xaa,0x11,0x99 + + .text + move.d mem1,r2 + move.d [r2],r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.d mem2,r3 + move.d [r3],r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.d mem1,r2 + move.d [r2+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.w [r2+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.b [r2+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.d [r2+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movs.b [r2],r3 + test_move_cc 1 0 0 0 + dumpr3 + + movu.b [r2+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.w [r2],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movs.w [r2+],r3 + test_move_cc 1 0 0 0 + dumpr3 + + move.d mem1,r13 + movs.b [r13+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.b [r13],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movs.w [r13+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.w [r13+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + quit + diff --git a/sim/testsuite/cris/asm/movemrv10.ms b/sim/testsuite/cris/asm/movemrv10.ms new file mode 100644 index 0000000..9fbb878 --- /dev/null +++ b/sim/testsuite/cris/asm/movemrv10.ms @@ -0,0 +1,101 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: 15\nffff1234\n2\n7\nb\n16\nf\n2\nf\nffffffef\n7\nfffffff4\nf\nfffffff2\nd\n10\nfffffff2\n8\nfffffff4\n + + .include "testutils.inc" + .data +x: + .dword 8,9,10,11 +y: + .dword -12,13,-14,15,16 + + start + moveq 7,r0 + moveq 2,r1 + move.d 0xffff1234,r2 + moveq 21,r3 + move.d x,r4 + setf zcvn + movem r2,[r4+] + test_cc 1 1 1 1 + subq 12,r4 + + dumpr3 ; 15 + + move.d [r4+],r3 + dumpr3 ; ffff1234 + + move.d [r4+],r3 + dumpr3 ; 2 + + move.d [r4+],r3 + dumpr3 ; 7 + + move.d [r4+],r3 + dumpr3 ; b + + subq 16,r4 + moveq 22,r0 + moveq 15,r1 + clearf zcvn + movem r0,[r4] + test_cc 0 0 0 0 + move.d [r4+],r3 + dumpr3 ; 16 + + move.d r1,r3 + dumpr3 ; f + + move.d [r4+],r3 + dumpr3 ; 2 + + moveq 10,r2 + moveq -17,r0 + clearf zc + setf vn + movem r1,[r4=r4-8] + test_cc 1 0 1 0 + move.d [r4+],r3 + dumpr3 ; f + + move.d [r4+],r3 + dumpr3 ; ffffffef + + move.d [r4+],r3 + dumpr3 ; 7 + + move.d y,r4 + setf zc + clearf vn + movem [r4+],r3 + test_cc 0 1 0 1 + dumpr3 ; fffffff4 + + move.d r0,r3 + dumpr3 ; f + + move.d r1,r3 + dumpr3 ; fffffff2 + + moveq -12,r1 + + move.d r2,r3 + dumpr3 ; d + + move.d [r4],r3 + dumpr3 ; 10 + + setf zcvn + movem [r5=r4-8],r0 + test_cc 1 1 1 1 + move.d r0,r3 + dumpr3 ; fffffff2 + + sub.d r5,r4 + move.d r4,r3 + dumpr3 ; 8 + + move.d r1,r3 + dumpr3 ; fffffff4 + + quit + diff --git a/sim/testsuite/cris/asm/movemrv32.ms b/sim/testsuite/cris/asm/movemrv32.ms new file mode 100644 index 0000000..15fcd4c --- /dev/null +++ b/sim/testsuite/cris/asm/movemrv32.ms @@ -0,0 +1,97 @@ +# mach: crisv32 +# output: 15\n7\n2\nffff1234\nb\n16\nf\n2\nffffffef\nf\nffff1234\nf\nfffffff4\nd\nfffffff2\n10\nfffffff2\nd\n + + .include "testutils.inc" + .data +x: + .dword 8,9,10,11 +y: + .dword -12,13,-14,15,16 + + start + moveq 7,r0 + moveq 2,r1 + move.d 0xffff1234,r2 + moveq 21,r3 + move.d x,r4 + setf zcvn + movem r2,[r4+] + test_cc 1 1 1 1 + subq 12,r4 + + dumpr3 ; 15 + + move.d [r4+],r3 + dumpr3 ; 7 + + move.d [r4+],r3 + dumpr3 ; 2 + + move.d [r4+],r3 + dumpr3 ; ffff1234 + + move.d [r4+],r3 + dumpr3 ; b + + subq 16,r4 + moveq 22,r0 + moveq 15,r1 + clearf zcvn + movem r0,[r4] + test_cc 0 0 0 0 + move.d [r4+],r3 + dumpr3 ; 16 + + move.d r1,r3 + dumpr3 ; f + + move.d [r4+],r3 + dumpr3 ; 2 + + subq 8,r4 + moveq 10,r2 + moveq -17,r0 + clearf zc + setf vn + movem r1,[r4] + test_cc 1 0 1 0 + move.d [r4+],r3 + dumpr3 ; ffffffef + + move.d [r4+],r3 + dumpr3 ; f + + move.d [r4+],r3 + dumpr3 ; ffff1234 + + move.d y,r4 + setf zc + clearf vn + movem [r4+],r3 + test_cc 0 1 0 1 + dumpr3 ; f + + move.d r0,r3 + dumpr3 ; fffffff4 + + move.d r1,r3 + dumpr3 ; d + + move.d r2,r3 + dumpr3 ; fffffff2 + + move.d [r4],r3 + dumpr3 ; 10 + + subq 8,r4 + setf zcvn + movem [r4+],r0 + test_cc 1 1 1 1 + move.d r0,r3 + dumpr3 ; fffffff2 + + move.d r1,r3 + dumpr3 ; d + + quit + diff --git a/sim/testsuite/cris/asm/movepcb.ms b/sim/testsuite/cris/asm/movepcb.ms new file mode 100644 index 0000000..b06932e --- /dev/null +++ b/sim/testsuite/cris/asm/movepcb.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + startnostack + setf + test.b pc + quit diff --git a/sim/testsuite/cris/asm/movepcd.ms b/sim/testsuite/cris/asm/movepcd.ms new file mode 100644 index 0000000..2ed0060 --- /dev/null +++ b/sim/testsuite/cris/asm/movepcd.ms @@ -0,0 +1,16 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register * PC is not implemented.\nprogram stopped with signal 5 (*).\n + +# Both source and dest contain PC for "test.d r" (move.d r,r). Ideally, +# the output message should say "read" of PC, but we allow PC as source in +# a move.d r,R insn, so there's no logical way to get that, short of a +# special pattern, which would be just too ugly. The output message says +# "write", but let's match "read" too so we won't fail if things suddenly +# improve. + + .include "testutils.inc" + startnostack + setf + test.d pc + quit diff --git a/sim/testsuite/cris/asm/movepcw.ms b/sim/testsuite/cris/asm/movepcw.ms new file mode 100644 index 0000000..0f3b6a2 --- /dev/null +++ b/sim/testsuite/cris/asm/movepcw.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + startnostack + setf + test.w pc + quit diff --git a/sim/testsuite/cris/asm/moveq.ms b/sim/testsuite/cris/asm/moveq.ms new file mode 100644 index 0000000..121cbda --- /dev/null +++ b/sim/testsuite/cris/asm/moveq.ms @@ -0,0 +1,15 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# sim: --trace-core=on +# ld: --section-start=.text=0 +# output: read-2 exec:0x00000002 -> 0x3262\nread-2 exec:0x00000004 -> 0xe93e\nffffffe2\nread-2 exec:0x00000006 -> 0x324d\nread-2 exec:0x00000008 -> 0xe93e\nd\nread-2 exec:0x0000000a -> 0xe93f\n + +; Output a positive and a negative number, set from moveq. + + .include "testutils.inc" + startnostack + moveq -30,r3 + dumpr3 + moveq 13,r3 + dumpr3 + quit + diff --git a/sim/testsuite/cris/asm/moveqpc.ms b/sim/testsuite/cris/asm/moveqpc.ms new file mode 100644 index 0000000..d5e856b --- /dev/null +++ b/sim/testsuite/cris/asm/moveqpc.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + startnostack + setf + moveq -30,pc + quit diff --git a/sim/testsuite/cris/asm/mover.ms b/sim/testsuite/cris/asm/mover.ms new file mode 100644 index 0000000..41a6474 --- /dev/null +++ b/sim/testsuite/cris/asm/mover.ms @@ -0,0 +1,29 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffff05\nffff0005\n5\nffffff00\n + +; Move between registers. Check that just the subreg is copied. + + .include "testutils.inc" + startnostack + moveq -30,r3 + moveq 5,r4 + move.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq -1,r3 + moveq 0,r4 + move.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit + diff --git a/sim/testsuite/cris/asm/moverbpc.ms b/sim/testsuite/cris/asm/moverbpc.ms new file mode 100644 index 0000000..b5ea388 --- /dev/null +++ b/sim/testsuite/cris/asm/moverbpc.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + startnostack + setf + move.d r5,pc + quit diff --git a/sim/testsuite/cris/asm/moverdpc.ms b/sim/testsuite/cris/asm/moverdpc.ms new file mode 100644 index 0000000..b5ea388 --- /dev/null +++ b/sim/testsuite/cris/asm/moverdpc.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + startnostack + setf + move.d r5,pc + quit diff --git a/sim/testsuite/cris/asm/moverm.ms b/sim/testsuite/cris/asm/moverm.ms new file mode 100644 index 0000000..be8126f --- /dev/null +++ b/sim/testsuite/cris/asm/moverm.ms @@ -0,0 +1,45 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 7823fec2\n10231879\n102318fe\n + + .include "testutils.inc" + start + + .data +mem1: + .dword 0x12345678 +mem2: + .word 0x4567 +mem3: + .byte 0x23 + .dword 0x76543210 + .byte 0xaa,0x11,0x99 + + .text + move.d mem1,r2 + move.d 0x7823fec2,r4 + setf nzvc + move.d r4,[r2+] + test_cc 1 1 1 1 + subq 4,r2 + move.d [r2],r3 + dumpr3 ; 7823fec2 + + move.d mem2,r3 + move.d 0x45231879,r4 + clearf nzvc + move.w r4,[r3] + test_cc 0 0 0 0 + move.d [r3],r3 + dumpr3 ; 10231879 + + move.d mem2,r2 + moveq -2,r4 + clearf nc + setf zv + move.b r4,[r2+] + test_cc 0 1 1 0 + subq 1,r2 + move.d [r2],r3 + dumpr3 ; 102318ff + + quit diff --git a/sim/testsuite/cris/asm/moverpcb.ms b/sim/testsuite/cris/asm/moverpcb.ms new file mode 100644 index 0000000..13e04b1 --- /dev/null +++ b/sim/testsuite/cris/asm/moverpcb.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + startnostack + setf + move.b pc,r5 + quit diff --git a/sim/testsuite/cris/asm/moverpcd.ms b/sim/testsuite/cris/asm/moverpcd.ms new file mode 100644 index 0000000..b7a54ea --- /dev/null +++ b/sim/testsuite/cris/asm/moverpcd.ms @@ -0,0 +1,13 @@ +# mach: crisv3 crisv8 crisv10 +# output: 4\n + +# Test that move.d pc,R works. + + .include "testutils.inc" + start +x: + move.d pc,r3 +y: + sub.d y-4,r3 + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/moverpcw.ms b/sim/testsuite/cris/asm/moverpcw.ms new file mode 100644 index 0000000..9b8f929 --- /dev/null +++ b/sim/testsuite/cris/asm/moverpcw.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + startnostack + setf + move.w pc,r2 + quit diff --git a/sim/testsuite/cris/asm/moverwpc.ms b/sim/testsuite/cris/asm/moverwpc.ms new file mode 100644 index 0000000..b5ea388 --- /dev/null +++ b/sim/testsuite/cris/asm/moverwpc.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + startnostack + setf + move.d r5,pc + quit diff --git a/sim/testsuite/cris/asm/movesmp.ms b/sim/testsuite/cris/asm/movesmp.ms new file mode 100644 index 0000000..a85dfc8 --- /dev/null +++ b/sim/testsuite/cris/asm/movesmp.ms @@ -0,0 +1,28 @@ +# mach: crisv3 crisv8 crisv10 +# output: bed0bed1\nabedab0d\nbed0bed1\n + +# Test that move to and from special register and memory clears the +# "prefixed" bit. + + .include "testutils.inc" + .data +w: + .dword 0 +y: + .dword 0xbed0bed1 +z: + .dword 0xabedab0d + + start +x: + move.d y,r3 + clear.d [w] + move.d [r3],r3 + dumpr3 ; bed0bed1 + move.d z,r3 + move [w+4],srp + move.d [r3],r3 + dumpr3 ; abedab0d + move srp,r3 + dumpr3 ; bed0bed1 + quit diff --git a/sim/testsuite/cris/asm/movmp.ms b/sim/testsuite/cris/asm/movmp.ms new file mode 100644 index 0000000..d864692 --- /dev/null +++ b/sim/testsuite/cris/asm/movmp.ms @@ -0,0 +1,127 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nbb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n + +# Test generic "move Ps,[]" and "move [],Pd" insns; the ones with +# functionality common to all models. + + .include "testutils.inc" + start + + .data +filler: + .byte 0xaa + .word 0x4433 + .dword 0x55778866 + .byte 0xcc + + .text +; Test that writing to zero-registers is a nop + .if 0 + ; We used to just ignore the writes, but now an error is emitted. We + ; keep the test-code but disabled, in case we need to change this again. + move 0xaa,p0 + move 0x4433,p4 + move 0x55774433,p8 + .endif + + moveq -1,r3 + setf zcvn + clear.b r3 + test_cc 1 1 1 1 + dumpr3 + + moveq -1,r3 + clearf zcvn + clear.w r3 + test_cc 0 0 0 0 + dumpr3 + + moveq -1,r3 + clear.d r3 + dumpr3 + +; "Write" using ordinary memory references too. + .if 0 ; See ".if 0" above. + move.d filler,r6 + move [r6],p0 + move [r6],p4 + move [r6],p8 + .endif + + moveq -1,r3 + clear.b r3 + dumpr3 + + moveq -1,r3 + clear.w r3 + dumpr3 + + moveq -1,r3 + clear.d r3 + dumpr3 + +; And postincremented. + .if 0 ; See ".if 0" above. + move [r6+],p0 + move [r6+],p4 + move [r6+],p8 + .endif + + moveq -1,r3 + clear.b r3 + dumpr3 + + moveq -1,r3 + clear.w r3 + dumpr3 + + moveq -1,r3 + clear.d r3 + dumpr3 + +; Now see that we can write to the registers too. + +; [PC+] + move.d filler,r9 + move 0xbb113344,srp + move srp,r3 + dumpr3 + +; [R+] + move [r9+],srp + move srp,r3 + dumpr3 + +; [R] + move [r9],srp + move srp,r3 + dumpr3 + +; And check writing to memory, clear and srp. + + move.d filler,r9 + move 0xabcde012,srp + setf zcvn + move srp,[r9+] + test_cc 1 1 1 1 + subq 4,r9 + move.d [r9],r3 + dumpr3 + + clearf zcvn + clear.b [r9] + test_cc 0 0 0 0 + move.d [r9],r3 + dumpr3 + + addq 2,r9 + clear.w [r9+] + subq 2,r9 + move.d [r9],r3 + dumpr3 + + clear.d [r9] + move.d [r9],r3 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movmp8.ms b/sim/testsuite/cris/asm/movmp8.ms new file mode 100644 index 0000000..ffb3854 --- /dev/null +++ b/sim/testsuite/cris/asm/movmp8.ms @@ -0,0 +1,33 @@ +# mach: crisv3 crisv8 crisv10 + +# Make sure that "move [$sp=$sp+16],$p8" works; used in Linux. + + .include "testutils.inc" + startnostack + move.d x,$sp + moveq 0,$r3 + move [$sp=$sp+16],$p8 + ; Z not changed. + bne 0f + nop + cmp.d x+16,$sp + bne 0f + nop + move $p8,$r3 + ; Z not changed. + bne 0f + ; P8 still 0. + test.d $r3 + bne 0f + nop + pass +0: + fail + + .data +x: + .dword 0xffffffff + .dword 0xffffffff + .dword 0xffffffff + .dword 0xffffffff + .dword 0xffffffff diff --git a/sim/testsuite/cris/asm/movpmv10.ms b/sim/testsuite/cris/asm/movpmv10.ms new file mode 100644 index 0000000..72dcee7 --- /dev/null +++ b/sim/testsuite/cris/asm/movpmv10.ms @@ -0,0 +1,35 @@ +# mach: crisv10 +# output: 1122330a\nbb113344\naa557711\n + +# Test v10-specific special registers. FIXME: ccr, irp, bar, brp, usp. + + .include "testutils.inc" + start + .data +store: + .dword 0x11223344 + .dword 0x77665544 + + .text + moveq -1,r3 + move.d store,r4 + clearf zcvn + move vr,[r4] + test_cc 0 0 0 0 + move [r4+],mof + move mof,r3 + dumpr3 + + moveq -1,r3 + move 0xbb113344,mof + move mof,r3 + dumpr3 + + move 0xaa557711,mof + setf zcvn + move mof,[r4] + test_cc 1 1 1 1 + move.d [r4],r3 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movpmv32.ms b/sim/testsuite/cris/asm/movpmv32.ms new file mode 100644 index 0000000..6d17338 --- /dev/null +++ b/sim/testsuite/cris/asm/movpmv32.ms @@ -0,0 +1,35 @@ +# mach: crisv32 +# output: 11223320\nbb113344\naa557711\n + +# Test v32-specific special registers. FIXME: more registers. + + .include "testutils.inc" + start + .data +store: + .dword 0x11223344 + .dword 0x77665544 + + .text + moveq -1,r3 + move.d store,r4 + move vr,[r4] + move [r4+],mof + move mof,r3 + dumpr3 + + moveq -1,r3 + clearf zcvn + move 0xbb113344,mof + test_cc 0 0 0 0 + move mof,r3 + dumpr3 + + setf zcvn + move 0xaa557711,mof + test_cc 1 1 1 1 + move mof,[r4] + move.d [r4],r3 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movppc.ms b/sim/testsuite/cris/asm/movppc.ms new file mode 100644 index 0000000..ee7e8d1 --- /dev/null +++ b/sim/testsuite/cris/asm/movppc.ms @@ -0,0 +1,7 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + move srp,[PC+] diff --git a/sim/testsuite/cris/asm/movpr.ms b/sim/testsuite/cris/asm/movpr.ms new file mode 100644 index 0000000..4279a73 --- /dev/null +++ b/sim/testsuite/cris/asm/movpr.ms @@ -0,0 +1,28 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffff00\nffff0000\n0\nbb113344\n + +# Test generic "move Ps,Rd" and "move Rs,Pd" insns; the ones with +# functionality common to all models. + + .include "testutils.inc" + start + moveq -1,r3 + clear.b r3 + dumpr3 + + moveq -1,r3 + clear.w r3 + dumpr3 + + moveq -1,r3 + clear.d r3 + dumpr3 + + moveq -1,r3 + move.d 0xbb113344,r4 + setf zcvn + move r4,srp + move srp,r3 + test_cc 1 1 1 1 + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/movprv10.ms b/sim/testsuite/cris/asm/movprv10.ms new file mode 100644 index 0000000..29a10b5 --- /dev/null +++ b/sim/testsuite/cris/asm/movprv10.ms @@ -0,0 +1,21 @@ +# mach: crisv10 +# output: ffffff0a\nbb113344\n + +# Test v10-specific special registers. FIXME: ccr, irp, bar, brp, usp. + + .include "testutils.inc" + start + moveq -1,r3 + setf zcvn + move vr,r3 + test_cc 1 1 1 1 + dumpr3 + + moveq -1,r3 + move.d 0xbb113344,r4 + clearf zcvn + move r4,mof + move mof,r3 + test_cc 0 0 0 0 + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/movprv32.ms b/sim/testsuite/cris/asm/movprv32.ms new file mode 100644 index 0000000..5a2f4dd --- /dev/null +++ b/sim/testsuite/cris/asm/movprv32.ms @@ -0,0 +1,21 @@ +# mach: crisv32 +# output: ffffff20\nbb113344\n + +# Test v32-specific special registers. FIXME: more registers. + + .include "testutils.inc" + start + moveq -1,r3 + setf zcvn + move vr,r3 + test_cc 1 1 1 1 + dumpr3 + + moveq -1,r3 + move.d 0xbb113344,r4 + clearf cvnz + move r4,mof + test_cc 0 0 0 0 + move mof,r3 + dumpr3 + quit diff --git a/sim/testsuite/cris/asm/movrss.ms b/sim/testsuite/cris/asm/movrss.ms new file mode 100644 index 0000000..42305f9 --- /dev/null +++ b/sim/testsuite/cris/asm/movrss.ms @@ -0,0 +1,8 @@ +# mach: crisv32 +# xerror: +# output: Write to support register is unimplemented\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + move R3,S0 + diff --git a/sim/testsuite/cris/asm/movscpc.ms b/sim/testsuite/cris/asm/movscpc.ms new file mode 100644 index 0000000..9861896 --- /dev/null +++ b/sim/testsuite/cris/asm/movscpc.ms @@ -0,0 +1,13 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + movs.b 0x42,pc + dumpr3 + + movs.w 0x4321,pc + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movscr.ms b/sim/testsuite/cris/asm/movscr.ms new file mode 100644 index 0000000..457cca8 --- /dev/null +++ b/sim/testsuite/cris/asm/movscr.ms @@ -0,0 +1,29 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 42\nffffff85\n7685\nffff8765\n0\n + +; Move constant byte, word, dword to register. Check that sign-extension +; is performed. + + .include "testutils.inc" + start + moveq -1,r3 + movs.b 0x42,r3 + dumpr3 + + movs.b 0x85,r3 + test_move_cc 1 0 0 0 + dumpr3 + + movs.w 0x7685,r3 + test_move_cc 0 0 0 0 + dumpr3 + + movs.w 0x8765,r3 + test_move_cc 1 0 0 0 + dumpr3 + + movs.w 0,r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movsm.ms b/sim/testsuite/cris/asm/movsm.ms new file mode 100644 index 0000000..59973d1 --- /dev/null +++ b/sim/testsuite/cris/asm/movsm.ms @@ -0,0 +1,44 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 5\nfffffff5\n5\nfffffff5\n0\n + +; Movs between registers. Check that sign-extension is performed and the +; full register is set. + + .include "testutils.inc" + + .data +x: + .byte 5,-11 + .word 5,-11 + .word 0 + + start + move.d x,r5 + + moveq -1,r3 + movs.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r3 + movs.b [r5],r3 + test_move_cc 1 0 0 0 + addq 1,r5 + dumpr3 + + moveq -1,r3 + movs.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r3 + movs.w [r5],r3 + test_move_cc 1 0 0 0 + addq 2,r5 + dumpr3 + + movs.w [r5],r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movsmpc.ms b/sim/testsuite/cris/asm/movsmpc.ms new file mode 100644 index 0000000..95f40ad --- /dev/null +++ b/sim/testsuite/cris/asm/movsmpc.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + move.d _start,r12 + movs.w [r12],pc diff --git a/sim/testsuite/cris/asm/movsr.ms b/sim/testsuite/cris/asm/movsr.ms new file mode 100644 index 0000000..283975f --- /dev/null +++ b/sim/testsuite/cris/asm/movsr.ms @@ -0,0 +1,46 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 5\nfffffff5\n5\nfffffff5\n0\n + +; Movs between registers. Check that sign-extension is performed and the +; full register is set. + + .include "testutils.inc" + start + moveq -1,r5 + moveq 5,r4 + move.b r4,r5 + moveq -1,r3 + movs.b r5,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r5 + moveq -11,r4 + move.b r4,r5 + moveq 0,r3 + movs.b r5,r3 + test_move_cc 1 0 0 0 + dumpr3 + + moveq -1,r5 + moveq 5,r4 + move.w r4,r5 + moveq -1,r3 + movs.w r5,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r5 + moveq -11,r4 + move.w r4,r5 + moveq 0,r3 + movs.w r5,r3 + test_move_cc 1 0 0 0 + dumpr3 + + moveq 0,r5 + movs.b r5,r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movsrpc.ms b/sim/testsuite/cris/asm/movsrpc.ms new file mode 100644 index 0000000..6971e37 --- /dev/null +++ b/sim/testsuite/cris/asm/movsrpc.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + setf + movs.w r0,pc + quit diff --git a/sim/testsuite/cris/asm/movssr.ms b/sim/testsuite/cris/asm/movssr.ms new file mode 100644 index 0000000..79e4fbd --- /dev/null +++ b/sim/testsuite/cris/asm/movssr.ms @@ -0,0 +1,8 @@ +# mach: crisv32 +# xerror: +# output: Read of support register is unimplemented\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + move S0,R3 + diff --git a/sim/testsuite/cris/asm/movucpc.ms b/sim/testsuite/cris/asm/movucpc.ms new file mode 100644 index 0000000..aec82d1 --- /dev/null +++ b/sim/testsuite/cris/asm/movucpc.ms @@ -0,0 +1,10 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + movu.w 0x4321,pc + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movucr.ms b/sim/testsuite/cris/asm/movucr.ms new file mode 100644 index 0000000..7508ff8 --- /dev/null +++ b/sim/testsuite/cris/asm/movucr.ms @@ -0,0 +1,33 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 42\n85\n7685\n8765\n0\n + +; Move constant byte, word, dword to register. Check that zero-extension +; is performed. + + .include "testutils.inc" + start + moveq -1,r3 + movu.b 0x42,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq -1,r3 + movu.b 0x85,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq -1,r3 + movu.w 0x7685,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq -1,r3 + movu.w 0x8765,r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.b 0,r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movum.ms b/sim/testsuite/cris/asm/movum.ms new file mode 100644 index 0000000..c6ea625 --- /dev/null +++ b/sim/testsuite/cris/asm/movum.ms @@ -0,0 +1,40 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 5\nf5\n5\nfff5\n0\n + +; Movu between registers. Check that zero-extension is performed and the +; full register is set. + + .include "testutils.inc" + + .data +x: + .byte 5,-11 + .word 5,-11 + .word 0 + + start + move.d x,r5 + + movu.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.b [r5],r3 + test_move_cc 0 0 0 0 + addq 1,r5 + dumpr3 + + movu.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.w [r5],r3 + test_move_cc 0 0 0 0 + addq 2,r5 + dumpr3 + + movu.w [r5],r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movumpc.ms b/sim/testsuite/cris/asm/movumpc.ms new file mode 100644 index 0000000..9bfc492 --- /dev/null +++ b/sim/testsuite/cris/asm/movumpc.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + move.d _start,r1 + movu.b [r1+],pc diff --git a/sim/testsuite/cris/asm/movur.ms b/sim/testsuite/cris/asm/movur.ms new file mode 100644 index 0000000..a46d54d --- /dev/null +++ b/sim/testsuite/cris/asm/movur.ms @@ -0,0 +1,45 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 5\nf5\n5\nfff5\n0\n + +; Movu between registers. Check that zero-extension is performed and the +; full register is set. + + .include "testutils.inc" + start + moveq -1,r5 + moveq 5,r4 + move.b r4,r5 + moveq -1,r3 + movu.b r5,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r5 + moveq -11,r4 + move.b r4,r5 + moveq -1,r3 + movu.b r5,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq -1,r5 + moveq 5,r4 + move.w r4,r5 + moveq -1,r3 + movu.w r5,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r5 + moveq -11,r4 + move.w r4,r5 + moveq -1,r3 + movu.w r5,r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.w 0,r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/movurpc.ms b/sim/testsuite/cris/asm/movurpc.ms new file mode 100644 index 0000000..3d75110 --- /dev/null +++ b/sim/testsuite/cris/asm/movurpc.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + setf + movu.b r3,pc + quit diff --git a/sim/testsuite/cris/asm/mstep.ms b/sim/testsuite/cris/asm/mstep.ms new file mode 100644 index 0000000..74aa20d --- /dev/null +++ b/sim/testsuite/cris/asm/mstep.ms @@ -0,0 +1,108 @@ +# mach: crisv3 crisv8 crisv10 +#output: fffffffe\n +#output: 3\n +#output: 1fffe\n +#output: 2fffd\n +#output: fffffffd\n +#output: ffffffff\n +#output: f02688a4\n +#output: 1fffe\n +#output: fffffffe\n +#output: fffffffe\n +#output: fffffff9\n +#output: 0\n +#output: 4459802d\n +#output: 4459802d\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + mstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffe + + moveq 2,r3 + moveq -1,r4 + mstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xffff,r4 + move.d r4,r3 + mstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1fffe + + move.d 0xffff,r4 + move.d r4,r3 + setf n + mstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2fffd + + moveq -1,r4 + move.d r4,r3 + mstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffd + + moveq -1,r3 + moveq 1,r4 + setf n + mstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + mstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; f02688a4 + + move.d 0xffff,r3 + move.d 0x1fffe,r4 + mstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1fffe + + move.d 0x7fffffff,r3 + moveq 5,r5 + mstep r5,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d 0x7fffffff,r3 + moveq 0,r5 + mstep r5,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d 0x7fffffff,r3 + moveq -5,r5 + mstep r5,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffff9 + + move.d 0x7fffffff,r3 + moveq 2,r5 + setf n + mstep r5,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + setf n + mstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4459802d + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + setf nc + mstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4459802d + + quit diff --git a/sim/testsuite/cris/asm/msteppc1.ms b/sim/testsuite/cris/asm/msteppc1.ms new file mode 100644 index 0000000..d21ffd7 --- /dev/null +++ b/sim/testsuite/cris/asm/msteppc1.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\n +# output: program stopped with signal 5 (*).\n + + .include "testutils.inc" + start + mstep pc,r2 diff --git a/sim/testsuite/cris/asm/msteppc2.ms b/sim/testsuite/cris/asm/msteppc2.ms new file mode 100644 index 0000000..69bfbaf --- /dev/null +++ b/sim/testsuite/cris/asm/msteppc2.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\n +# output: program stopped with signal 5 (*).\n + + .include "testutils.inc" + start + mstep r2,pc diff --git a/sim/testsuite/cris/asm/msteppc3.ms b/sim/testsuite/cris/asm/msteppc3.ms new file mode 100644 index 0000000..09e87a3 --- /dev/null +++ b/sim/testsuite/cris/asm/msteppc3.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\n +# output: program stopped with signal 5 (*).\n + + .include "testutils.inc" + start + mstep pc,pc diff --git a/sim/testsuite/cris/asm/mulv10.ms b/sim/testsuite/cris/asm/mulv10.ms new file mode 100644 index 0000000..43511f7 --- /dev/null +++ b/sim/testsuite/cris/asm/mulv10.ms @@ -0,0 +1,29 @@ +# mach: crisv8 crisv10 +# output: fffffffe\n +# output: ffffffff\n +# output: fffffffe\n +# output: 1\n + +; Check that carry is cleared on v8, v10. + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + setf c + muls.d r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 2,r4 + setf c + mulu.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; 1 + + quit diff --git a/sim/testsuite/cris/asm/mulv32.ms b/sim/testsuite/cris/asm/mulv32.ms new file mode 100644 index 0000000..6d2edcb --- /dev/null +++ b/sim/testsuite/cris/asm/mulv32.ms @@ -0,0 +1,51 @@ +# mach: crisv32 +# output: fffffffe\n +# output: ffffffff\n +# output: fffffffe\n +# output: 1\n +# output: fffffffe\n +# output: ffffffff\n +# output: fffffffe\n +# output: 1\n + +; Check that carry is not modified on v32. + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + setf c + muls.d r4,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 2,r4 + setf c + mulu.d r4,r3 + test_cc 0 0 1 1 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; 1 + + moveq -1,r3 + moveq 2,r4 + clearf c + muls.d r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 2,r4 + clearf c + mulu.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; 1 + + quit diff --git a/sim/testsuite/cris/asm/mulx.ms b/sim/testsuite/cris/asm/mulx.ms new file mode 100644 index 0000000..1fc6261 --- /dev/null +++ b/sim/testsuite/cris/asm/mulx.ms @@ -0,0 +1,246 @@ +# mach: crisv10 crisv32 +# output: fffffffe\nffffffff\nfffffffe\n1\nfffffffe\nffffffff\nfffffffe\n1\nfffe0001\n0\nfffe0001\n0\n1\n0\n1\nfffffffe\n193eade2\n277e3a49\n193eade2\n277e3a49\nfffffffe\nffffffff\n1fffe\n0\nfffffffe\nffffffff\n1fffe\n0\n1\n0\nfffe0001\n0\nfdbdade2\nffffffff\n420fade2\n0\nfffffffe\nffffffff\n1fe\n0\nfffffffe\nffffffff\n1fe\n0\n1\n0\nfe01\n0\n1\n0\nfe01\n0\nffffd9e2\nffffffff\n2be2\n0\n0\n0\n0\n0\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + muls.d r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 2,r4 + mulu.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; 1 + + moveq 2,r3 + moveq -1,r4 + muls.d r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq -1,r4 + mulu.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; 1 + + move.d 0xffff,r4 + move.d r4,r3 + muls.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; fffe0001 + move mof,r3 + dumpr3 ; 0 + + move.d 0xffff,r4 + move.d r4,r3 + mulu.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; fffe0001 + move mof,r3 + dumpr3 ; 0 + + moveq -1,r4 + move.d r4,r3 + muls.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + move mof,r3 + dumpr3 ; 0 + + moveq -1,r4 + move.d r4,r3 + mulu.d r4,r3 + test_cc 1 0 1 0 + dumpr3 ; 1 + move mof,r3 + dumpr3 ; fffffffe + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + muls.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; 193eade2 + move mof,r3 + dumpr3 ; 277e3a49 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + mulu.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; 193eade2 + move mof,r3 + dumpr3 ; 277e3a49 + + move.d 0xffff,r3 + moveq 2,r4 + muls.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 2,r4 + mulu.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + move mof,r3 + dumpr3 ; 0 + + moveq 2,r3 + move.d 0xffff,r4 + muls.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq -1,r4 + mulu.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + move mof,r3 + dumpr3 ; 0 + + move.d 0xffff,r4 + move.d r4,r3 + muls.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + move mof,r3 + dumpr3 ; 0 + + moveq -1,r4 + move.d r4,r3 + mulu.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; fffe0001 + move mof,r3 + dumpr3 ; 0 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + muls.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fdbdade2 + move mof,r3 + dumpr3 ; ffffffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + mulu.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 420fade2 + move mof,r3 + dumpr3 ; 0 + + move.d 0xff,r3 + moveq 2,r4 + muls.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 2,r4 + mulu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fe + move mof,r3 + dumpr3 ; 0 + + moveq 2,r3 + moveq -1,r4 + muls.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq -1,r4 + mulu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fe + move mof,r3 + dumpr3 ; 0 + + move.d 0xff,r4 + move.d r4,r3 + muls.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + move mof,r3 + dumpr3 ; 0 + + moveq -1,r4 + move.d r4,r3 + mulu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; fe01 + move mof,r3 + dumpr3 ; 0 + + move.d 0xfeda49ff,r4 + move.d r4,r3 + muls.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + move mof,r3 + dumpr3 ; 0 + + move.d 0xfeda49ff,r4 + move.d r4,r3 + mulu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; fe01 + move mof,r3 + dumpr3 ; 0 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + muls.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffd9e2 + move mof,r3 + dumpr3 ; ffffffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + mulu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 2be2 + move mof,r3 + dumpr3 ; 0 + + moveq 0,r3 + move.d 0xf87f4aeb,r4 + muls.d r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + move mof,r3 + dumpr3 ; 0 + + move.d 0xf87f4aeb,r3 + moveq 0,r4 + mulu.d r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + move mof,r3 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/neg.ms b/sim/testsuite/cris/asm/neg.ms new file mode 100644 index 0000000..0a922a6 --- /dev/null +++ b/sim/testsuite/cris/asm/neg.ms @@ -0,0 +1,102 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\nffffffff\n0\n80000000\n1\nba987655\nffff\nffff\n0\n89ab8000\nffff0001\n45677655\nff\nff\n0\n89abae80\nffffff01\n45678955\n + + .include "testutils.inc" + start + moveq 0,r3 + moveq 1,r4 + neg.d r4,r3 + test_cc 1 0 0 1 + dumpr3 ; ffffffff + + moveq 1,r3 + moveq 0,r4 + neg.d r3,r3 + test_cc 1 0 0 1 + dumpr3 ; ffffffff + + moveq 0,r3 + neg.d r3,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x80000000,r3 + neg.d r3,r3 + test_cc 1 0 1 1 + dumpr3 ; 80000000 + + moveq -1,r3 + neg.d r3,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0x456789ab,r3 + neg.d r3,r3 + test_cc 1 0 0 1 + dumpr3 ; ba987655 + + moveq 0,r3 + moveq 1,r4 + neg.w r4,r3 + test_cc 1 0 0 1 + dumpr3 ; ffff + + moveq 1,r3 + moveq 0,r4 + neg.w r3,r3 + test_cc 1 0 0 1 + dumpr3 ; ffff + + moveq 0,r3 + neg.w r3,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x89ab8000,r3 + neg.w r3,r3 + test_cc 1 0 1 1 + dumpr3 ; 89ab8000 + + moveq -1,r3 + neg.w r3,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff0001 + + move.d 0x456789ab,r3 + neg.w r3,r3 + test_cc 0 0 0 1 + dumpr3 ; 45677655 + + moveq 0,r3 + moveq 1,r4 + neg.b r4,r3 + test_cc 1 0 0 1 + dumpr3 ; ff + + moveq 1,r3 + moveq 0,r4 + neg.b r3,r3 + test_cc 1 0 0 1 + dumpr3 ; ff + + moveq 0,r3 + neg.b r3,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x89abae80,r3 + neg.b r3,r3 + test_cc 1 0 1 1 + dumpr3 ; 89abae80 + + moveq -1,r3 + neg.b r3,r3 + test_cc 0 0 0 1 + dumpr3 ; ffffff01 + + move.d 0x456789ab,r3 + neg.b r3,r3 + test_cc 0 0 0 1 + dumpr3 ; 45678955 + + quit diff --git a/sim/testsuite/cris/asm/nonvcv32.ms b/sim/testsuite/cris/asm/nonvcv32.ms new file mode 100644 index 0000000..98af367 --- /dev/null +++ b/sim/testsuite/cris/asm/nonvcv32.ms @@ -0,0 +1,167 @@ +# mach: crisv32 + + .include "testutils.inc" + +; Check for various non-arithmetic insns that C and V are not affected +; on v32 (where they were on v10), as the generic tests don't cover +; that; they are cleared before testing. + +; First, a macro testing that VC are unaffected, not counting previous +; register contents. + .macro nonvc0 insn op + move.d $r0,$r3 + setf vc + .ifnc \insn,swapnwbr + \insn \op,$r3 + .else + \insn $r3 + .endif + bcc 9f + nop + bvc 9f + nop + move.d $r0,$r3 + clearf vc + .ifnc \insn,swapnwbr + \insn \op,$r3 + .else + \insn $r3 + .endif + bcs 9f + nop + bvc 8f + nop +9: + fail +8: + .endm + +; Use the above, but initialize the non-parameter operand to a value. + .macro nonvc1 insn val op + move.d \val,$r0 + nonvc0 \insn,\op + .endm + +; Use the above, iterating over various values. + .macro nonvc2 insn op + .irp p,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000 + nonvc1 \insn,\p,\op + nonvc1 \insn,-\p,\op + .endr + .endm + + .macro nonvc2q insn op min=-63 max=63 + .if (\op >= \min) && (\op <= \max) + nonvc2 \insn,\op + .endif + .endm + +; The above, for each .b .w .d insn variant. + .macro nonvcbwd insn op + .irp s,.b,.w,.d + nonvc2 \insn\s,\op + .endr + .endm + +; For various insns with register, dword constant and memory operands. + .macro nonvcitermcd op=[$r4] + nonvc2 and.d,\op + nonvc2 move.d,\op + nonvc2 or.d,\op + .endm + +; Similar, for various insns with register, word constant and memory operands. + .macro nonvcitermcw op=[$r4] + nonvcitermcd \op + nonvc2 and.w,\op + nonvc2 move.w,\op + nonvc2 or.w,\op + nonvc2 movs.w,\op + nonvc2 movu.w,\op + .endm + +; Similar, for various insns with register, byte constant and memory operands. + .macro nonvcitermcb op=[$r4] + nonvcitermcw \op + nonvc2 and.b,\op + nonvc2 move.b,\op + nonvc2 or.b,\op + nonvc2 movs.b,\op + nonvc2 movu.b,\op + .endm + +; Similar, for insns with quick constant operands. + .macro nonvciterq op + nonvcitermcb \op + nonvc2 bound.b,\op + nonvc2q andq,\op,min=-32,max=31 + nonvc2q asrq,\op,min=0,max=31 + nonvc2q lsrq,\op,min=0,max=31 + nonvc2q orq,\op,min=-32,max=31 + nonvc2q moveq,\op,min=-32,max=31 + .endm + +; Similar, for insns with register operands. + .macro nonvciterr op + nonvcitermcb \op + nonvcbwd bound,\op + nonvc2 abs,\op + nonvcbwd asr,\op + nonvc2 dstep,\op + nonvcbwd lsr,\op + nonvcbwd lsl,\op + nonvc2 lz,\op + nonvc2 swapnwbr + nonvc2 xor,\op + .endm + +; Test all applicable constant, register and memory variants of a value. + .macro tst op +; Constants + .if (\op <= 31) && (\op >= -32) + nonvciterq \op + .elseif (\op <= 255) && (\op >= -128) + nonvcitermcb \op + nonvcbwd bound,\op + .elseif (\op <= 65535) && (\op >= -32767) + nonvcitermcw \op + nonvc2 bound.w,\op + nonvc2 bound.d,\op + .else + nonvcitermcd \op + nonvc2 bound.d,\op + .endif +; Registers + move.d \op,$r4 + nonvciterr $r4 +; Memory + nonvcitermcb [$r5] + addq 4,$r5 + .section .rodata + .dword \op + .previous + .endm + +; As above but negation too. + .macro tstpm op + tst \op + tst -\op + .endm + + +; Set up for the actual test. + + start + move.d c0,$r5 + + .section .rodata +c0: + .previous + +; Finally, test. + + .irp x,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000 + tstpm \x + .endr + + pass diff --git a/sim/testsuite/cris/asm/nopv10t.ms b/sim/testsuite/cris/asm/nopv10t.ms new file mode 100644 index 0000000..d96eaf0 --- /dev/null +++ b/sim/testsuite/cris/asm/nopv10t.ms @@ -0,0 +1,13 @@ +#mach: crisv0 crisv3 crisv8 crisv10 +#output: Basic clock cycles, total @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "nopv32t.ms" diff --git a/sim/testsuite/cris/asm/nopv32t.ms b/sim/testsuite/cris/asm/nopv32t.ms new file mode 100644 index 0000000..794d19b --- /dev/null +++ b/sim/testsuite/cris/asm/nopv32t.ms @@ -0,0 +1,21 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + .global _start +_start: + nop + nop + nop + nop + nop + break 15 diff --git a/sim/testsuite/cris/asm/nopv32t2.ms b/sim/testsuite/cris/asm/nopv32t2.ms new file mode 100644 index 0000000..760a539 --- /dev/null +++ b/sim/testsuite/cris/asm/nopv32t2.ms @@ -0,0 +1,13 @@ +#mach: crisv10 crisv32 +#output: Clock cycles including stall cycles for unaligned accesses @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=unaligned + .include "nopv32t.ms" diff --git a/sim/testsuite/cris/asm/nopv32t3.ms b/sim/testsuite/cris/asm/nopv32t3.ms new file mode 100644 index 0000000..d8b2351 --- /dev/null +++ b/sim/testsuite/cris/asm/nopv32t3.ms @@ -0,0 +1,13 @@ +#mach: crisv10 crisv32 +#output: Schedulable clock cycles, total @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=schedulable + .include "nopv32t.ms" diff --git a/sim/testsuite/cris/asm/nopv32t4.ms b/sim/testsuite/cris/asm/nopv32t4.ms new file mode 100644 index 0000000..98f336b --- /dev/null +++ b/sim/testsuite/cris/asm/nopv32t4.ms @@ -0,0 +1,13 @@ +#mach: crisv10 crisv32 +#output: All accounted clock cycles, total @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=all + .include "nopv32t.ms" diff --git a/sim/testsuite/cris/asm/not.ms b/sim/testsuite/cris/asm/not.ms new file mode 100644 index 0000000..4416bbc --- /dev/null +++ b/sim/testsuite/cris/asm/not.ms @@ -0,0 +1,31 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: fffffffe\nfffffffd\nffff0f00\n0\n87ecbbad\n + + .include "testutils.inc" + start + moveq 1,r3 + not r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffe + + moveq 2,r3 + not r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffd + + move.d 0xf0ff,r3 + not r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffff0f00 + + moveq -1,r3 + not r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x78134452,r3 + not r3 + test_move_cc 1 0 0 0 + dumpr3 ; 87ecbbad + + quit diff --git a/sim/testsuite/cris/asm/op3.ms b/sim/testsuite/cris/asm/op3.ms new file mode 100644 index 0000000..05e974c --- /dev/null +++ b/sim/testsuite/cris/asm/op3.ms @@ -0,0 +1,98 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: ee19cd0b\nee197761\nccff2244\n55aa77ff\nffffaa77\naa\n4243ab11\n424377ab\nfdedaaf0\n4242dd68\n4242dd68\n40025567\n57eb77ff\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + + start + move.d x,r10 + moveq 0,r3 + moveq 12,r4 + add.d [r10+6],r4,r3 + test_cc 1 0 0 0 + dumpr3 ; ee19cd0b + + move.d 0x1267,r7 + subu.w [r10+2],r3,r8 + test_cc 1 0 0 0 + move.d r8,r3 + dumpr3 ; ee197761 + + moveq 1,r8 + bound.d [r10+r8.d],r3,r5 + test_move_cc 1 0 0 0 + move.d r5,r3 + dumpr3 ; ccff2244 + +; Also applies to move insns. Bleah. + moveq 0,r5 + bdap 0,r10 + move.d [r3],r5 + test_move_cc 0 0 0 0 + dumpr3 ; 55aa77ff + + moveq 0,r5 + bdap 1,r10 + movs.w [r3],r5 + test_move_cc 1 0 0 0 + dumpr3 ; ffffaa77 + + moveq 0,r5 + bdap 2,r10 + movu.b [r3],r5 + test_move_cc 0 0 0 0 + dumpr3 ; aa + + move.d 0x42435567,r8 + bdap 2,r10 + adds.w [r3],r8 + test_cc 0 0 0 0 + dumpr3 ; 4243ab11 + + move.d 0x42435567,r8 + bdap 4,r10 + addu.w [r3],r8 + test_cc 0 0 0 0 + dumpr3 ; 424377ab + + move.d 0x42435567,r8 + bdap 1,r10 + sub.d [r3],r8 + test_cc 1 0 0 1 + dumpr3 ; fdedaaf0 + + move.d 0x42435567,r8 + bdap 0,r10 + subs.w [r3],r8 + test_cc 0 0 0 0 + dumpr3 ; 4242dd68 + + move.d 0x42435567,r8 + bdap 0,r10 + subu.w [r3],r8 + test_cc 0 0 0 0 + dumpr3 ; 4242dd68 + + move.d 0x42435567,r8 + bdap 0,r10 + and.d [r3],r8 + test_move_cc 0 0 0 0 + dumpr3 ; 40025567 + + move.d 0x42435567,r8 + bdap 0,r10 + or.d [r3],r8 + test_move_cc 0 0 0 0 + dumpr3 ; 57eb77ff + + move.d 0xc2435567,r8 + bdap 0,r10 + bound.d [r3],r8 + test_move_cc 0 0 0 0 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/cris/asm/opterr1.ms b/sim/testsuite/cris/asm/opterr1.ms new file mode 100644 index 0000000..409f58b --- /dev/null +++ b/sim/testsuite/cris/asm/opterr1.ms @@ -0,0 +1,5 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# xerror: +# output: *: unrecognized option [`']--cris-stats=xyz'\nUse --help for a complete list of options.\n +# sim: --cris-stats=xyz + .include "nopv32t.ms" diff --git a/sim/testsuite/cris/asm/opterr2.ms b/sim/testsuite/cris/asm/opterr2.ms new file mode 100644 index 0000000..084d61e --- /dev/null +++ b/sim/testsuite/cris/asm/opterr2.ms @@ -0,0 +1,5 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# xerror: +# output: *: unrecognized option [`']--cris-xyz'\nUse --help for a complete list of options.\n +# sim: --cris-xyz + .include "nopv32t.ms" diff --git a/sim/testsuite/cris/asm/opterr3.ms b/sim/testsuite/cris/asm/opterr3.ms new file mode 100644 index 0000000..8d602be --- /dev/null +++ b/sim/testsuite/cris/asm/opterr3.ms @@ -0,0 +1,10 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# ld: -N --oformat binary --section-start=.text=0x10000000 +# sim: --cris-naked --memory-mapfile +# xerror: +# output: Usage: run \[options\] program \[program args\]\n*\n +# progopts: --memory-region 0x10000000,0x1000 + .include "bare3.ms" + +; Check that we get an error for wrong usage, not a SEGV for lack of +; bfd when missing the program argument (can't use *only* mapped files). diff --git a/sim/testsuite/cris/asm/opterr4.ms b/sim/testsuite/cris/asm/opterr4.ms new file mode 100644 index 0000000..a4ffc6b --- /dev/null +++ b/sim/testsuite/cris/asm/opterr4.ms @@ -0,0 +1,7 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# xerror: +# output: Invalid option [`']--cris-start-address=x'\n +# sim: --cris-start-address=x + .include "nopv32t.ms" + +; Check that we recognize wrong usage of the --cris-start-address option. diff --git a/sim/testsuite/cris/asm/opterr5.ms b/sim/testsuite/cris/asm/opterr5.ms new file mode 100644 index 0000000..3d1b591 --- /dev/null +++ b/sim/testsuite/cris/asm/opterr5.ms @@ -0,0 +1,7 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# xerror: +# output: Invalid option [`']--cris-program-offset=x'\n +# sim: --cris-program-offset=x + .include "nopv32t.ms" + +; Check that we recognize wrong usage of the --cris-program-offset option. diff --git a/sim/testsuite/cris/asm/option1.ms b/sim/testsuite/cris/asm/option1.ms new file mode 100644 index 0000000..387a01f --- /dev/null +++ b/sim/testsuite/cris/asm/option1.ms @@ -0,0 +1,7 @@ +#mach: crisv0 crisv3 crisv8 crisv10 crisv32 +#sim: --cris-trace=foo +#xerror: +#output: Unknown option `--cris-trace=foo'\n + .include "testutils.inc" + start + fail diff --git a/sim/testsuite/cris/asm/option2.ms b/sim/testsuite/cris/asm/option2.ms new file mode 100644 index 0000000..4ac6a86 --- /dev/null +++ b/sim/testsuite/cris/asm/option2.ms @@ -0,0 +1,5 @@ +#mach: crisv0 crisv3 crisv8 crisv10 crisv32 +#sim: --sysroot=/non/exist/dir +#output: run: can't change directory to "/non/exist/dir"\n +#xerror: + .include "option1.ms" diff --git a/sim/testsuite/cris/asm/option3.ms b/sim/testsuite/cris/asm/option3.ms new file mode 100644 index 0000000..75ddb44 --- /dev/null +++ b/sim/testsuite/cris/asm/option3.ms @@ -0,0 +1,7 @@ +#mach: crisv0 crisv3 crisv8 crisv10 crisv32 +#sim: --cris-cycles=foo +#xerror: +#output: Unknown option `--cris-cycles=foo'\n + .include "testutils.inc" + start + fail diff --git a/sim/testsuite/cris/asm/option4.ms b/sim/testsuite/cris/asm/option4.ms new file mode 100644 index 0000000..e0bc691 --- /dev/null +++ b/sim/testsuite/cris/asm/option4.ms @@ -0,0 +1,7 @@ +#mach: crisv0 crisv3 crisv8 crisv10 crisv32 +#sim: --cris-unknown-syscall=foo +#xerror: +#output: Unknown option `--cris-unknown-syscall=foo'\n + .include "testutils.inc" + start + fail diff --git a/sim/testsuite/cris/asm/orc.ms b/sim/testsuite/cris/asm/orc.ms new file mode 100644 index 0000000..d8fbe70 --- /dev/null +++ b/sim/testsuite/cris/asm/orc.ms @@ -0,0 +1,71 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n + + .include "testutils.inc" + start + moveq 1,r3 + or.d 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + or.d 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xf0ff,r3 + or.d 0xff0f,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r3 + or.d -1,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + or.d 0x5432f789,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 7c33f7db + + move.d 0xffff0001,r3 + or.w 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0003 + + moveq 2,r3 + or.w 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xfedaffaf,r3 + or.w 0xff5f,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fedaffff + + move.d 0x78134452,r3 + or.w 0xf789,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 7813f7db + + moveq 1,r3 + or.b 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + or.b 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xfa3,r3 + or.b 0x4a,r3 + test_move_cc 1 0 0 0 + dumpr3 ; feb + + move.d 0x78134453,r3 + or.b 0x89,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 781344db + + quit diff --git a/sim/testsuite/cris/asm/orm.ms b/sim/testsuite/cris/asm/orm.ms new file mode 100644 index 0000000..f2bdaae --- /dev/null +++ b/sim/testsuite/cris/asm/orm.ms @@ -0,0 +1,75 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n + + .include "testutils.inc" + .data +x: + .dword 2,1,0xff0f,-1,0x5432f789 + .word 2,1,0xff5f,0xf789 + .byte 2,1,0x4a,0x89 + + start + moveq 1,r3 + move.d x,r5 + or.d [r5+],r3 + dumpr3 ; 3 + + moveq 2,r3 + or.d [r5],r3 + addq 4,r5 + dumpr3 ; 3 + + move.d 0xf0ff,r3 + or.d [r5+],r3 + dumpr3 ; ffff + + moveq -1,r3 + or.d [r5+],r3 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + or.d [r5+],r3 + dumpr3 ; 7c33f7db + + move.d 0xffff0001,r3 + or.w [r5+],r3 + dumpr3 ; ffff0003 + + moveq 2,r3 + or.w [r5],r3 + addq 2,r5 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xfedaffaf,r3 + or.w [r5+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; fedaffff + + move.d 0x78134452,r3 + or.w [r5+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; 7813f7db + + moveq 1,r3 + or.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + or.b [r5],r3 + addq 1,r5 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xfa3,r3 + or.b [r5+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; feb + + move.d 0x78134453,r3 + or.b [r5],r3 + test_move_cc 1 0 0 0 + dumpr3 ; 781344db + + quit diff --git a/sim/testsuite/cris/asm/orq.ms b/sim/testsuite/cris/asm/orq.ms new file mode 100644 index 0000000..905a961 --- /dev/null +++ b/sim/testsuite/cris/asm/orq.ms @@ -0,0 +1,41 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffffffff\nffffffff\n1f\nffffffe0\n7813445e\n + + .include "testutils.inc" + start + moveq 1,r3 + orq 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + orq 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xf0ff,r3 + orq -1,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 0,r3 + orq -1,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 0,r3 + orq 31,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1f + + moveq 0,r3 + orq -32,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffe0 + + move.d 0x78134452,r3 + orq 12,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 7813445e + + quit diff --git a/sim/testsuite/cris/asm/orr.ms b/sim/testsuite/cris/asm/orr.ms new file mode 100644 index 0000000..54d033b --- /dev/null +++ b/sim/testsuite/cris/asm/orr.ms @@ -0,0 +1,84 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n + + .include "testutils.inc" + start + moveq 1,r3 + moveq 2,r4 + or.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + moveq 1,r4 + or.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xff0f,r4 + move.d 0xf0ff,r3 + or.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r4 + move.d r4,r3 + or.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + or.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 7c33f7db + + move.d 0xffff0001,r3 + moveq 2,r4 + or.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0003 + + moveq 2,r3 + move.d 0xffff0001,r4 + or.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xfedaffaf,r3 + move.d 0xffffff5f,r4 + or.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fedaffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + or.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 7813f7db + + moveq 1,r3 + move.d 0xffffff02,r4 + or.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + moveq 1,r4 + or.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0x4a,r4 + move.d 0xfa3,r3 + or.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; feb + + move.d 0x5432f789,r4 + move.d 0x78134453,r3 + or.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 781344db + + quit diff --git a/sim/testsuite/cris/asm/pcplus.ms b/sim/testsuite/cris/asm/pcplus.ms new file mode 100644 index 0000000..99cd46a --- /dev/null +++ b/sim/testsuite/cris/asm/pcplus.ms @@ -0,0 +1,46 @@ +# mach: crisv0 crisv3 crisv8 crisv10 + +; Test that a forward as well as backward 32-bit "branch" expansion +; works including that the right offset is applied. + + .macro nop32 + .rept 32 + nop + .endr + .endm + + .include "testutils.inc" + start + jump start1 + fail + + nop32 + subq 63,$r10 +9: subq 1,$r10 + nop32 + jump 0f + + fail +0: move [$pc=$pc+1f-6-0b],$p0 + nop32 + fail + + .skip 32768,0 + + nop32 + subq 63,$r10 +1: + subq 1,$r10 + nop32 + test.d $r10 + bne 7f + nop + pass +7: + fail + +start1: + moveq 2,$r10 +0: move [$pc=$pc+9b-6-0b],$p0 + subq 63,$r10 + fail diff --git a/sim/testsuite/cris/asm/pid1.ms b/sim/testsuite/cris/asm/pid1.ms new file mode 100644 index 0000000..16e3489 --- /dev/null +++ b/sim/testsuite/cris/asm/pid1.ms @@ -0,0 +1,45 @@ +# mach: crisv32 +# output: 0\ncafebabe\nbaddbeef\necc0d00d\nc0ceface\npass\n + +; Check that the PID register has the right size, 32 bits: check +; immediate, to/from register and memory. (This has to be done in +; supervisor mode, so don't set u.) + + .include "testutils.inc" + .macro dumpid + move $pid,$r3 + dumpr3 + .endm + + start + moveq -1,$r3 + move 0,$pid + dumpid ; 0 + move 0xcafebabe,$pid + dumpid ; cafebabe + move.d 0xbaddbeef,$r2 + move $r2,$pid + dumpid ; baddbeef + move.d 0f,$r0 + move [$r0+],$pid + cmp.d 0f+4,$r0 + beq 1f + nop +dofail: + fail +0: + .dword 0xecc0d00d +0: + .dword 0xc0ceface +1: + dumpid ; ecc0d00d + move.d 0b,$r1 + move 0xc0ceface,$pid + move $pid,[$r1+] + cmp.d 0b+4,$r1 + bne dofail + subq 4,$r1 + nop + move.d [$r1],$r3 + dumpr3 ; c0ceface + pass diff --git a/sim/testsuite/cris/asm/raw1.ms b/sim/testsuite/cris/asm/raw1.ms new file mode 100644 index 0000000..fd2fcb2 --- /dev/null +++ b/sim/testsuite/cris/asm/raw1.ms @@ -0,0 +1,22 @@ +; Checking read-after-write: read-then-read unaffected. +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d [$r0],$r2 + move.d [$r1],$r4 + break 15 diff --git a/sim/testsuite/cris/asm/raw10.ms b/sim/testsuite/cris/asm/raw10.ms new file mode 100644 index 0000000..a9faee9 --- /dev/null +++ b/sim/testsuite/cris/asm/raw10.ms @@ -0,0 +1,22 @@ +; Checking read-after-write: swrite-then-read 2 cycles. +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + clear.d [$r0] + move [$r1],$srp + break 15 diff --git a/sim/testsuite/cris/asm/raw11.ms b/sim/testsuite/cris/asm/raw11.ms new file mode 100644 index 0000000..38bf274 --- /dev/null +++ b/sim/testsuite/cris/asm/raw11.ms @@ -0,0 +1,23 @@ +; Checking read-after-write: swrite-then-nop-read 2 cycles. +#mach: crisv32 +#output: Basic clock cycles, total @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + clear.d [$r0] + nop + move [$r1],$srp + break 15 diff --git a/sim/testsuite/cris/asm/raw12.ms b/sim/testsuite/cris/asm/raw12.ms new file mode 100644 index 0000000..d8ffa45 --- /dev/null +++ b/sim/testsuite/cris/asm/raw12.ms @@ -0,0 +1,24 @@ +; Checking read-after-write: swrite-then-nop-nop-read unaffected. +#mach: crisv32 +#output: Basic clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + clear.d [$r0] + nop + nop + move [$r1],$srp + break 15 diff --git a/sim/testsuite/cris/asm/raw13.ms b/sim/testsuite/cris/asm/raw13.ms new file mode 100644 index 0000000..e5e2e52 --- /dev/null +++ b/sim/testsuite/cris/asm/raw13.ms @@ -0,0 +1,22 @@ +; Checking read-after-write: write-MOF-then-read unaffected. +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move [$r0],$mof + move [$r1],$srp + break 15 diff --git a/sim/testsuite/cris/asm/raw14.ms b/sim/testsuite/cris/asm/raw14.ms new file mode 100644 index 0000000..f086328 --- /dev/null +++ b/sim/testsuite/cris/asm/raw14.ms @@ -0,0 +1,14 @@ +; Checking read-after-write: cycles included in "schedulable". +#mach: crisv32 +#output: Schedulable clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=schedulable + .include "raw4.ms" diff --git a/sim/testsuite/cris/asm/raw15.ms b/sim/testsuite/cris/asm/raw15.ms new file mode 100644 index 0000000..3f49067 --- /dev/null +++ b/sim/testsuite/cris/asm/raw15.ms @@ -0,0 +1,14 @@ +; Checking read-after-write: cycles included in "all". +#mach: crisv32 +#output: All accounted clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=all + .include "raw4.ms" diff --git a/sim/testsuite/cris/asm/raw16.ms b/sim/testsuite/cris/asm/raw16.ms new file mode 100644 index 0000000..07977cc --- /dev/null +++ b/sim/testsuite/cris/asm/raw16.ms @@ -0,0 +1,14 @@ +; Checking read-after-write: cycles included in "unaligned". +#mach: crisv32 +#output: Clock cycles including stall cycles for unaligned accesses @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=unaligned + .include "raw4.ms" diff --git a/sim/testsuite/cris/asm/raw17.ms b/sim/testsuite/cris/asm/raw17.ms new file mode 100644 index 0000000..07d18c5 --- /dev/null +++ b/sim/testsuite/cris/asm/raw17.ms @@ -0,0 +1,29 @@ +; Checking read-after-write: different read-after-write combinations. +#mach: crisv32 +#output: Basic clock cycles, total @: 11\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 8\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d $r1,[$r0] + move.d [$r1],$r2 + move.d [$r1],$r2 + clear.d [$r0] + move.d [$r1],$r2 + movem $r0,[$r1] + movem [$r1],$r0 + move $srp,[$r1] + move.d [$r1],$r0 + break 15 diff --git a/sim/testsuite/cris/asm/raw2.ms b/sim/testsuite/cris/asm/raw2.ms new file mode 100644 index 0000000..cbbc47d --- /dev/null +++ b/sim/testsuite/cris/asm/raw2.ms @@ -0,0 +1,22 @@ +; Checking read-after-write: write-then-write unaffected. +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d $r1,[$r0] + move.d $r0,[$r1] + break 15 diff --git a/sim/testsuite/cris/asm/raw3.ms b/sim/testsuite/cris/asm/raw3.ms new file mode 100644 index 0000000..1c9a86b --- /dev/null +++ b/sim/testsuite/cris/asm/raw3.ms @@ -0,0 +1,22 @@ +; Checking read-after-write: read-then-write unaffected. +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d [$r0],$r2 + move.d $r0,[$r1] + break 15 diff --git a/sim/testsuite/cris/asm/raw4.ms b/sim/testsuite/cris/asm/raw4.ms new file mode 100644 index 0000000..75a77e9 --- /dev/null +++ b/sim/testsuite/cris/asm/raw4.ms @@ -0,0 +1,22 @@ +; Checking read-after-write: write-then-read 2 cycles. +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d $r1,[$r0] + move.d [$r1],$r2 + break 15 diff --git a/sim/testsuite/cris/asm/raw5.ms b/sim/testsuite/cris/asm/raw5.ms new file mode 100644 index 0000000..670e143 --- /dev/null +++ b/sim/testsuite/cris/asm/raw5.ms @@ -0,0 +1,23 @@ +; Checking read-after-write: write-then-nop-read 2 cycles. +#mach: crisv32 +#output: Basic clock cycles, total @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d $r1,[$r0] + nop + move.d [$r1],$r2 + break 15 diff --git a/sim/testsuite/cris/asm/raw6.ms b/sim/testsuite/cris/asm/raw6.ms new file mode 100644 index 0000000..d6e6636 --- /dev/null +++ b/sim/testsuite/cris/asm/raw6.ms @@ -0,0 +1,24 @@ +; Checking read-after-write: write-then-nop-nop-read unaffected. +#mach: crisv32 +#output: Basic clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d $r1,[$r0] + nop + nop + move.d [$r1],$r2 + break 15 diff --git a/sim/testsuite/cris/asm/raw7.ms b/sim/testsuite/cris/asm/raw7.ms new file mode 100644 index 0000000..99da5f7 --- /dev/null +++ b/sim/testsuite/cris/asm/raw7.ms @@ -0,0 +1,25 @@ +; Checking read-after-write: movemwrite-then-read 2 cycles. +#mach: crisv32 +#ld: --section-start=.text=0 +#output: Basic clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 1\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4*11 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + nop + nop + movem $r10,[$r0] + move.d [$r1],$r2 + break 15 diff --git a/sim/testsuite/cris/asm/raw8.ms b/sim/testsuite/cris/asm/raw8.ms new file mode 100644 index 0000000..8e42b95 --- /dev/null +++ b/sim/testsuite/cris/asm/raw8.ms @@ -0,0 +1,26 @@ +; Checking read-after-write: movemwrite-then-nop-read 2 cycles. +#mach: crisv32 +#ld: --section-start=.text=0 +#output: Basic clock cycles, total @: 7\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 1\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4*11 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + nop + nop + movem $r10,[$r0] + nop + move.d [$r1],$r2 + break 15 diff --git a/sim/testsuite/cris/asm/raw9.ms b/sim/testsuite/cris/asm/raw9.ms new file mode 100644 index 0000000..5c3881e --- /dev/null +++ b/sim/testsuite/cris/asm/raw9.ms @@ -0,0 +1,27 @@ +; Checking read-after-write: movemwrite-then-nop-nop-read unaffected. +#mach: crisv32 +#ld: --section-start=.text=0 +#output: Basic clock cycles, total @: 8\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 1\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4*11 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + nop + nop + movem $r10,[$r0] + nop + nop + move.d [$r1],$r2 + break 15 diff --git a/sim/testsuite/cris/asm/ret.ms b/sim/testsuite/cris/asm/ret.ms new file mode 100644 index 0000000..578c5e1 --- /dev/null +++ b/sim/testsuite/cris/asm/ret.ms @@ -0,0 +1,25 @@ +# mach: crisv3 crisv8 crisv10 +# output: 3\n + +# Test that ret works. + + .include "testutils.inc" + start +x: + moveq 0,r3 + jsr z +w: + quit +y: + addq 1,r3 + dumpr3 + quit + +z: + addq 1,r3 + move srp,r2 + add.d y-w,r2 + move r2,srp + ret + addq 1,r3 + quit diff --git a/sim/testsuite/cris/asm/rfe.ms b/sim/testsuite/cris/asm/rfe.ms new file mode 100644 index 0000000..8d53778 --- /dev/null +++ b/sim/testsuite/cris/asm/rfe.ms @@ -0,0 +1,47 @@ +# mach: crisv32 +# output: 4000c3af\n40000020\n40000080\n40000000\n + +; Check that RFE affects CCS the right way. + + .include "testutils.inc" + start + +; Set SPC to 1 to disable single step exceptions when S flag is set. + move 1,spc + +; CCS: +; 31 24 23 16 15 8 7 0 +; +---+-----------+-------+-------+-----------+---+---------------+ +; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| +; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | +; +---+-----------+-------+-------+-----------+---+---------------+ + +; Clear S R P U I X N Z V C, set S1 R1 P1 (not U1) I1 X1 N1 Z1 V1 C1, +; clear S2 R2 P2 U2 N2 Z2 V2 C2, Q; set I2 X2 M: +; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 + move 0x430efc00,ccs + + test_cc 0 0 0 0 + + rfe + test_cc 1 1 1 1 + move ccs,r3 + dumpr3 ; 0x4000c3af + + rfe + test_cc 0 0 0 0 + move ccs,r3 + dumpr3 ; 0x40000020 + + rfe + test_cc 0 0 0 0 + move ccs,r3 + dumpr3 ; 0x40000080 + + or.w 0x100,r3 + move $r3,ccs + rfe + move ccs,r3 + dumpr3 ; 0x40000000 + + quit diff --git a/sim/testsuite/cris/asm/rfg.ms b/sim/testsuite/cris/asm/rfg.ms new file mode 100644 index 0000000..aa664b2 --- /dev/null +++ b/sim/testsuite/cris/asm/rfg.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# xerror: +# output: RFG isn't implemented\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + rfg + + quit diff --git a/sim/testsuite/cris/asm/rfn.ms b/sim/testsuite/cris/asm/rfn.ms new file mode 100644 index 0000000..8f12530 --- /dev/null +++ b/sim/testsuite/cris/asm/rfn.ms @@ -0,0 +1,53 @@ +# mach: crisv32 +# output: c008c1af\n40000220\n40000080\n40000000\n + +; Check that RFN affects CCS the right way. + + .include "testutils.inc" + start + +; Set SPC to 1 to disable single step exceptions when S flag is set. + move 1,spc + +; CCS: +; 31 24 23 16 15 8 7 0 +; +---+-----------+-------+-------+-----------+---+---------------+ +; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| +; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | +; +---+-----------+-------+-------+-----------+---+---------------+ + +; Clear S R P U I X N Z V C, set R1 P1 (not U1) I1 X1 N1 Z1 V1 C1, +; clear S1 R2 P2 U2 N2 Z2 V2 C2, set S2 I2 X2 Q, clear M: +; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 + move 0xa306fc00,ccs + + test_cc 0 0 0 0 + + rfn + test_cc 1 1 1 1 + move ccs,r3 + dumpr3 ; 0xc008c1af + + and.d 0x3fffffff,r3 + move r3,ccs + rfn + test_cc 0 0 0 0 + move ccs,r3 + dumpr3 ; 0x40000220 + + and.d 0x3fffffff,r3 + move r3,ccs + rfn + test_cc 0 0 0 0 + move ccs,r3 + dumpr3 ; 0x40000080 + + and.d 0x3fffffff,r3 + move r3,ccs + or.w 0x100,r3 + move r3,ccs + rfn + move ccs,r3 + dumpr3 ; 0x40000000 + + quit diff --git a/sim/testsuite/cris/asm/sbfs.ms b/sim/testsuite/cris/asm/sbfs.ms new file mode 100644 index 0000000..5714b52 --- /dev/null +++ b/sim/testsuite/cris/asm/sbfs.ms @@ -0,0 +1,7 @@ +# mach: crisv10 +# xerror: +# output: SBFS isn't implemented\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + sbfs [r10] diff --git a/sim/testsuite/cris/asm/scc.ms b/sim/testsuite/cris/asm/scc.ms new file mode 100644 index 0000000..5925f8a --- /dev/null +++ b/sim/testsuite/cris/asm/scc.ms @@ -0,0 +1,89 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n0\n1\n1\n0\n1\n0\n0\n1\n1\n0\n1\n1\n0\n + + .include "testutils.inc" + + start + clearf nzvc + scc r3 + dumpr3 ; 1 + scs r3 + dumpr3 ; 0 + sne r3 + dumpr3 ; 1 + seq r3 + dumpr3 ; 0 + svc r3 + dumpr3 ; 1 + svs r3 + dumpr3 ; 0 + spl r3 + dumpr3 ; 1 + smi r3 + dumpr3 ; 0 + sls r3 + dumpr3 ; 0 + shi r3 + dumpr3 ; 1 + sge r3 + dumpr3 ; 1 + slt r3 + dumpr3 ; 0 + sgt r3 + dumpr3 ; 1 + sle r3 + dumpr3 ; 0 + sa r3 + dumpr3 ; 1 + setf nzvc + scc r3 + dumpr3 ; 0 + scs r3 + dumpr3 ; 1 + sne r3 + dumpr3 ; 0 + svc r3 + dumpr3 ; 0 + svs r3 + dumpr3 ; 1 + spl r3 + dumpr3 ; 0 + smi r3 + dumpr3 ; 1 + sls r3 + dumpr3 ; 1 + shi r3 + dumpr3 ; 0 + sge r3 + dumpr3 ; 1 + slt r3 + dumpr3 ; 0 + sgt r3 + dumpr3 ; 0 + sle r3 + dumpr3 ; 1 + sa r3 + dumpr3 ; 1 + clearf n + sge r3 + dumpr3 ; 0 + slt r3 + dumpr3 ; 1 + + .if ..asm.arch.cris.v32 + setf p + ssb r3 + .else + moveq 1,r3 + .endif + dumpr3 ; 1 + + .if ..asm.arch.cris.v32 + clearf p + ssb r3 + .else + moveq 0,r3 + .endif + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/sfe.ms b/sim/testsuite/cris/asm/sfe.ms new file mode 100644 index 0000000..b4b8e7c --- /dev/null +++ b/sim/testsuite/cris/asm/sfe.ms @@ -0,0 +1,51 @@ +# mach: crisv32 +# output: 4000c800\nc3221800\nc8606400\n48606400\n419d8260\n + +; Check that SFE affects CCS the right way. + + .include "testutils.inc" + start + +; Set SPC to 1 to disable single step exceptions when S flag is set. + move 1,spc + +; CCS: +; 31 24 23 16 15 8 7 0 +; +---+-----------+-------+-------+-----------+---+---------------+ +; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| +; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | +; +---+-----------+-------+-------+-----------+---+---------------+ + + move 0x40000000,ccs + setf ixv + sfe + move ccs,r3 + dumpr3 ; 0x4000c800 + or.d 0x80000000,r3 + move r3,ccs + + setf pzv + sfe + move ccs,r3 + dumpr3 ; 0xc3221800 + + setf xnc + sfe + move ccs,r3 + dumpr3 ; 0xc8606400 + +; Clear Q, so we don't get S and Q at the same time when we set S. + lslq 1,r3 + lsrq 1,r3 + move r3,ccs + move ccs,r3 + dumpr3 ; 0x48606400 + + or.w 0x300,r3 + move r3,ccs + setf ui + sfe + move ccs,r3 + dumpr3 ; 0x419d8260 + + quit diff --git a/sim/testsuite/cris/asm/subc.ms b/sim/testsuite/cris/asm/subc.ms new file mode 100644 index 0000000..35d4e84 --- /dev/null +++ b/sim/testsuite/cris/asm/subc.ms @@ -0,0 +1,86 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n + + .include "testutils.inc" + start + moveq -1,r3 + sub.d -2,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + moveq 2,r3 + sub.d 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xffff,r3 + sub.d -0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; 1fffe + + moveq -1,r3 + sub.d 1,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d 0x78134452,r3 + sub.d -0x5432f789,r3 + test_cc 1 0 1 1 + dumpr3 ; cc463bdb + + moveq -1,r3 + sub.w -2,r3 + test_cc 0 0 0 0 + dumpr3 ; ffff0001 + + moveq 2,r3 + sub.w 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xffff,r3 + sub.w 1,r3 + test_cc 1 0 0 0 + dumpr3 ; fffe + + move.d 0xfedaffff,r3 + sub.w 1,r3 + test_cc 1 0 0 0 + dumpr3 ; fedafffe + + move.d 0x78134452,r3 + sub.w 0x877,r3 + test_cc 0 0 0 0 + dumpr3 ; 78133bdb + + moveq -1,r3 + sub.b -2,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffff01 + + moveq 2,r3 + sub.b 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xff,r3 + sub.b 1,r3 + test_cc 1 0 0 0 + dumpr3 ; fe + + move.d 0xfeda49ff,r3 + sub.b 1,r3 + test_cc 1 0 0 0 + dumpr3 ; feda49fe + + move.d 0x78134452,r3 + sub.b 0x77,r3 + test_cc 1 0 0 1 + dumpr3 ; 781344db + + move.d 0x85649282,r3 + sub.b 0x82,r3 + test_cc 0 1 0 0 + dumpr3 ; 85649200 + + quit diff --git a/sim/testsuite/cris/asm/subm.ms b/sim/testsuite/cris/asm/subm.ms new file mode 100644 index 0000000..d84f34a --- /dev/null +++ b/sim/testsuite/cris/asm/subm.ms @@ -0,0 +1,96 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n + + .include "testutils.inc" + .data +x: + .dword -2,1,-0xffff,1,-0x5432f789 + .word -2,1,1,0x877 + .byte -2,1,0x77 + .byte 0x22 + + start + moveq -1,r3 + move.d x,r5 + sub.d [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + moveq 2,r3 + sub.d [r5],r3 + test_cc 0 0 0 0 + addq 4,r5 + dumpr3 ; 1 + + move.d 0xffff,r3 + sub.d [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 1fffe + + moveq -1,r3 + sub.d [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d 0x78134452,r3 + sub.d [r5+],r3 + test_cc 1 0 1 1 + dumpr3 ; cc463bdb + + moveq -1,r3 + sub.w [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; ffff0001 + + moveq 2,r3 + sub.w [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xffff,r3 + sub.w [r5],r3 + test_cc 1 0 0 0 + dumpr3 ; fffe + + move.d 0xfedaffff,r3 + sub.w [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; fedafffe + + move.d 0x78134452,r3 + sub.w [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 78133bdb + + moveq -1,r3 + sub.b [r5],r3 + test_cc 0 0 0 0 + addq 1,r5 + dumpr3 ; ffffff01 + + moveq 2,r3 + sub.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xff,r3 + sub.b [r5],r3 + test_cc 1 0 0 0 + dumpr3 ; fe + + move.d 0xfeda49ff,r3 + sub.b [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; feda49fe + + move.d 0x78134452,r3 + sub.b [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; 781344db + + move.d 0x85649222,r3 + sub.b [r5],r3 + test_cc 0 1 0 0 + dumpr3 ; 85649200 + + quit diff --git a/sim/testsuite/cris/asm/subq.ms b/sim/testsuite/cris/asm/subq.ms new file mode 100644 index 0000000..7b09267 --- /dev/null +++ b/sim/testsuite/cris/asm/subq.ms @@ -0,0 +1,52 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 0\nffffffff\nfffffffe\nffff\nff\n56788f9\n56788d9\n567889a\n0\n7ffffffc\n + + .include "testutils.inc" + start + moveq 1,r3 + subq 1,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + subq 1,r3 + test_cc 1 0 0 1 + dumpr3 ; ffffffff + + subq 1,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d 0x10000,r3 + subq 1,r3 + test_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0x100,r3 + subq 1,r3 + test_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0x5678900,r3 + subq 7,r3 + test_cc 0 0 0 0 + dumpr3 ; 56788f9 + + subq 32,r3 + test_cc 0 0 0 0 + dumpr3 ; 56788d9 + + subq 63,r3 + test_cc 0 0 0 0 + dumpr3 ; 567889a + + move.d 34,r3 + subq 34,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x80000024,r3 + subq 40,r3 + test_cc 0 0 1 0 + dumpr3 ; 7ffffffc + + quit diff --git a/sim/testsuite/cris/asm/subqpc.ms b/sim/testsuite/cris/asm/subqpc.ms new file mode 100644 index 0000000..e2679a3 --- /dev/null +++ b/sim/testsuite/cris/asm/subqpc.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n + + .include "testutils.inc" + start + subq 31,pc + diff --git a/sim/testsuite/cris/asm/subr.ms b/sim/testsuite/cris/asm/subr.ms new file mode 100644 index 0000000..ea77b77 --- /dev/null +++ b/sim/testsuite/cris/asm/subr.ms @@ -0,0 +1,102 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq -2,r4 + sub.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + moveq 2,r3 + moveq 1,r4 + sub.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xffff,r3 + move.d -0xffff,r4 + sub.d r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 1fffe + + moveq 1,r4 + moveq -1,r3 + sub.d r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d -0x5432f789,r4 + move.d 0x78134452,r3 + sub.d r4,r3 + test_cc 1 0 1 1 + dumpr3 ; cc463bdb + + moveq -1,r3 + moveq -2,r4 + sub.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; ffff0001 + + moveq 2,r3 + moveq 1,r4 + sub.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xffff,r3 + move.d -0xffff,r4 + sub.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffe + + move.d 0xfedaffff,r3 + move.d -0xfedaffff,r4 + sub.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fedafffe + + move.d -0x5432f789,r4 + move.d 0x78134452,r3 + sub.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 78133bdb + + moveq -1,r3 + moveq -2,r4 + sub.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffff01 + + moveq 2,r3 + moveq 1,r4 + sub.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d -0xff,r4 + move.d 0xff,r3 + sub.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fe + + move.d -0xfeda49ff,r4 + move.d 0xfeda49ff,r3 + sub.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; feda49fe + + move.d -0x5432f789,r4 + move.d 0x78134452,r3 + sub.b r4,r3 + test_cc 1 0 0 1 + dumpr3 ; 781344db + + move.d 0x85649222,r3 + move.d 0x77445622,r4 + sub.b r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 85649200 + + quit diff --git a/sim/testsuite/cris/asm/subxc.ms b/sim/testsuite/cris/asm/subxc.ms new file mode 100644 index 0000000..bd76adb --- /dev/null +++ b/sim/testsuite/cris/asm/subxc.ms @@ -0,0 +1,92 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n + + .include "testutils.inc" + start + moveq 2,r3 + subs.b 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; 3 + + moveq 2,r3 + subs.w 0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; 3 + + moveq 2,r3 + subu.b 0xff,r3 + test_cc 1 0 0 1 + dumpr3 ; ffffff03 + + moveq 2,r3 + move.d 0xffffffff,r4 + subu.w -1,r3 + test_cc 1 0 0 1 + dumpr3 ; ffff0003 + + move.d 0xffff,r3 + subu.b -1,r3 + test_cc 0 0 0 0 + dumpr3 ; ff00 + + move.d 0xffff,r3 + subu.w -1,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xffff,r3 + subs.b 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; 10000 + + move.d 0xffff,r3 + subs.w 0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; 10000 + + moveq -1,r3 + subs.b 0xff,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + moveq -1,r3 + subs.w 0xff,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + subs.w 0xffff,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x78134452,r3 + subu.b 0x89,r3 + test_cc 0 0 0 0 + dumpr3 ; 781343c9 + + move.d 0x78134452,r3 + subs.b 0x89,r3 + test_cc 0 0 0 1 + dumpr3 ; 781344c9 + + move.d 0x78134452,r3 + subu.w 0xf789,r3 + test_cc 0 0 0 0 + dumpr3 ; 78124cc9 + + move.d 0x78134452,r3 + subs.w 0xf789,r3 + test_cc 0 0 0 1 + dumpr3 ; 78134cc9 + + move.d 0x4452,r3 + subs.w 0x8002,r3 + test_cc 0 0 0 1 + dumpr3 ; c450 + + move.d 0x80000032,r3 + subu.w 0x764,r3 + test_cc 0 0 1 0 + dumpr3 ; 7ffff8ce + + quit diff --git a/sim/testsuite/cris/asm/subxm.ms b/sim/testsuite/cris/asm/subxm.ms new file mode 100644 index 0000000..a4537d1 --- /dev/null +++ b/sim/testsuite/cris/asm/subxm.ms @@ -0,0 +1,106 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n + + .include "testutils.inc" + .data +x: + .byte 0xff + .word 0xffff + .word 0xff + .word 0xffff + .byte 0x89 + .word 0xf789 + .word 0x8002 + .word 0x764 + + start + moveq 2,r3 + move.d x,r5 + subs.b [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 3 + + moveq 2,r3 + subs.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 3 + + moveq 2,r3 + subq 3,r5 + subu.b [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; ffffff03 + + moveq 2,r3 + subu.w [r5+],r3 + test_cc 1 0 0 1 + subq 3,r5 + dumpr3 ; ffff0003 + + move.d 0xffff,r3 + subu.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; ff00 + + move.d 0xffff,r3 + subu.w [r5],r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xffff,r3 + subs.b [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; 10000 + + move.d 0xffff,r3 + subs.w [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; 10000 + + moveq -1,r3 + subs.b [r5],r3 + test_cc 0 1 0 0 + addq 3,r5 + dumpr3 ; 0 + + moveq -1,r3 + subs.w [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + subs.w [r5+],r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x78134452,r3 + subu.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 781343c9 + + move.d 0x78134452,r3 + subs.b [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 781344c9 + + move.d 0x78134452,r3 + subu.w [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 78124cc9 + + move.d 0x78134452,r3 + subs.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 78134cc9 + + move.d 0x4452,r3 + subs.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; c450 + + move.d 0x80000032,r3 + subu.w [r5+],r3 + test_cc 0 0 1 0 + dumpr3 ; 7ffff8ce + + quit diff --git a/sim/testsuite/cris/asm/subxr.ms b/sim/testsuite/cris/asm/subxr.ms new file mode 100644 index 0000000..e894596 --- /dev/null +++ b/sim/testsuite/cris/asm/subxr.ms @@ -0,0 +1,108 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n + + .include "testutils.inc" + start + moveq 2,r3 + move.d 0xff,r4 + subs.b r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 3 + + moveq 2,r3 + move.d 0xffff,r4 + subs.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 3 + + moveq 2,r3 + move.d 0xffff,r4 + subu.b r4,r3 + test_cc 1 0 0 1 + dumpr3 ; ffffff03 + + moveq 2,r3 + move.d 0xffffffff,r4 + subu.w r4,r3 + test_cc 1 0 0 1 + dumpr3 ; ffff0003 + + move.d 0xffff,r3 + move.d 0xffffffff,r4 + subu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; ff00 + + move.d 0xffff,r3 + move.d 0xffffffff,r4 + subu.w r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xffff,r3 + move.d 0xff,r4 + subs.b r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 10000 + + move.d 0xffff,r4 + move.d r4,r3 + subs.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 10000 + + moveq -1,r3 + move.d 0xff,r4 + subs.b r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + moveq -1,r3 + move.d 0xff,r4 + subs.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + move.d 0xffff,r4 + subs.w r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + subu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 781343c9 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + subs.b r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 781344c9 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + subu.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 78124cc9 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + subs.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 78134cc9 + + move.d 0x4452,r3 + move.d 0x78568002,r4 + subs.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; c450 + + move.d 0x80000032,r3 + move.d 0xffff0764,r4 + subu.w r4,r3 + test_cc 0 0 1 0 + dumpr3 ; 7ffff8ce + + quit diff --git a/sim/testsuite/cris/asm/swap.ms b/sim/testsuite/cris/asm/swap.ms new file mode 100644 index 0000000..de7ca49 --- /dev/null +++ b/sim/testsuite/cris/asm/swap.ms @@ -0,0 +1,87 @@ +# mach: crisv8 crisv10 crisv32 +# output: 1ec8224a\n13785244\nc81e4a22\n44527813\n224a1ec8\n52441378\n4a22c81e\n87ecbbad\ne137ddb5\nec87adbb\n37e1b5dd\nbbad87ec\nddb5e137\nadbbec87\nb5dd37e1\n0\n + + .include "testutils.inc" + start + move.d 0x78134452,r4 + move.d r4,r3 + swapr r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1ec8224a + + move.d r4,r3 + swapb r3 + test_move_cc 0 0 0 0 + dumpr3 ; 13785244 + + move.d r4,r3 + swapbr r3 + test_move_cc 1 0 0 0 + dumpr3 ; c81e4a22 + + move.d r4,r3 + swapw r3 + test_move_cc 0 0 0 0 + dumpr3 ; 44527813 + + move.d r4,r3 + swapwr r3 + test_move_cc 0 0 0 0 + dumpr3 ; 224a1ec8 + + move.d r4,r3 + swapwb r3 + test_move_cc 0 0 0 0 + dumpr3 ; 52441378 + + move.d r4,r3 + swapwbr r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4a22c81e + + move.d r4,r3 + swapn r3 + test_move_cc 1 0 0 0 + dumpr3 ; 87ecbbad + + move.d r4,r3 + swapnr r3 + test_move_cc 1 0 0 0 + dumpr3 ; e137ddb5 + + move.d r4,r3 + swapnb r3 + test_move_cc 1 0 0 0 + dumpr3 ; ec87adbb + + move.d r4,r3 + swapnbr r3 + test_move_cc 0 0 0 0 + dumpr3 ; 37e1b5dd + + move.d r4,r3 + swapnw r3 + test_move_cc 1 0 0 0 + dumpr3 ; bbad87ec + + move.d r4,r3 + swapnwr r3 + test_move_cc 1 0 0 0 + dumpr3 ; ddb5e137 + + move.d r4,r3 + swapnwb r3 + test_move_cc 1 0 0 0 + dumpr3 ; adbbec87 + + move.d r4,r3 + swapnwbr r3 + test_move_cc 1 0 0 0 + dumpr3 ; b5dd37e1 + + moveq -1,r3 + swapnwbr r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/cris/asm/tb.ms b/sim/testsuite/cris/asm/tb.ms new file mode 100644 index 0000000..eb6eaf9 --- /dev/null +++ b/sim/testsuite/cris/asm/tb.ms @@ -0,0 +1,72 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 54\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 18\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check branch penalties. It is assumed that the taken-counters +; in the bimodal branch-predictors start at 0, meaning two taken +; branches are required for a branch to be predicted as taken +; for each counter, from reset. None of these branches go +; to the end of a cache-line and none map to the same counter. + + .include "testutils.inc" + startnostack + ba 0f ; No penalty: always-taken condition not "predicted". + nop + nop +0: + setf c + bcs 0f ; Penalty 2 cycles. + nop + + nop +0: + clearf c + bcc 0f ; Penalty 2 cycles, though branch is a nop. + moveq 4,r0 ; Execute 5 times: + +0: + move.d r0,r0 + bne 0b ; Mispredicted 3 out of 5 times: penalty 3*2 cycles. + subq 1,r0 + +0: + beq 0f ; Not taken; no penalty. + nop + + nop +0: + +; (Almost) same insns, but with 16-bit bCC insns. + + ba 0f ; No penalty: always-taken condition not "predicted". + nop + .space 520 +0: + setf c + bcs 0f ; Penalty 2 cycles. + nop + + .space 520 +0: + moveq 4,r0 ; Execute 5 times: +0: + ba 1f + move.d r0,r0 ; Mispredicted 3 out of 5 times: + .space 520 +1: + bne 0b ; Penalty 3*2 cycles. + subq 1,r0 + + beq 0f ; Not taken; no penalty. + nop +0: + break 15 diff --git a/sim/testsuite/cris/asm/test.ms b/sim/testsuite/cris/asm/test.ms new file mode 100644 index 0000000..93c4f59 --- /dev/null +++ b/sim/testsuite/cris/asm/test.ms @@ -0,0 +1,80 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n + + .include "testutils.inc" + .data +x: + .dword 0,2,-1,0x80000000,0x5432f789 + .word 0,2,-1,0xffff,0xf789 + .byte 0,2,0xff,0x89 + + start + clearf nzvc + moveq -1,r3 + move.d x,r5 + setf vc + test.d [r5+] + test_cc 0 1 0 0 + + setf vc + test.d [r5] + test_cc 0 0 0 0 + + addq 4,r5 + + setf vc + test.d [r5+] + test_cc 1 0 0 0 + + setf vc + test.d [r5+] + test_cc 1 0 0 0 + + setf vc + test.d [r5+] + test_cc 0 0 0 0 + + setf vc + test.w [r5+] + test_cc 0 1 0 0 + + setf vc + test.w [r5] + test_cc 0 0 0 0 + + addq 2,r5 + + setf vc + test.w [r5+] + test_cc 1 0 0 0 + + setf vc + test.w [r5+] + test_cc 1 0 0 0 + + setf vc + test.w [r5+] + test_cc 1 0 0 0 + + setf vc + test.b [r5] + test_cc 0 1 0 0 + + addq 1,r5 + + setf vc + test.b [r5+] + test_cc 0 0 0 0 + + setf vc + test.b [r5+] + test_cc 1 0 0 0 + + setf vc + test.b [r5] + test_cc 1 0 0 0 + + moveq 1,r3 + dumpr3 + + quit diff --git a/sim/testsuite/cris/asm/testutils.inc b/sim/testsuite/cris/asm/testutils.inc new file mode 100644 index 0000000..962f4fc --- /dev/null +++ b/sim/testsuite/cris/asm/testutils.inc @@ -0,0 +1,361 @@ +; Copied from fr30 and modified. +; r9, r11-r13 are used as tmps, consider them call clobbered by these macros. +; +; Do not use the macro counter \@ in macros, there's a bug in +; gas 2.9.1 when it is also a line-separator. +; + + ; Don't require the $-prefix on registers. + .syntax no_register_prefix + + .macro startnostack + .data + .space 64,0 ; Simple stack +stackhi: +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + break 11 + .global _start +_start: + .endm + + .macro start + startnostack + move.d stackhi,sp + .endm + +; Exit with return code + .macro exit rc + move.d \rc,r10 + moveq 1,r9 ; == __NR_exit + break 13 + break 15 + .endm + +; Pass the test case + .macro pass + moveq 5,r12 + move.d passmsg,r11 + move.d 1,r10 + moveq 4,r9 ; == __NR_write + break 13 + exit 0 + .endm + +; Fail the testcase + .macro fail +; moveq 5,r12 +; move.d failmsg,r11 +; move.d 1,r10 +; moveq 4,r1 +; break 13 +; exit 1 + break 15 + .endm + + .macro quit + break 15 + .endm + + .macro dumpr3 + break 14 + .endm + +; Load an immediate value into a general register +; TODO: use minimal sized insn + .macro mvi_h_gr val reg + move.d \val,\reg + .endm + +; Load an immediate value into a dedicated register + .macro mvi_h_dr val reg + move.d \val,r9 + move.d r9,\reg + .endm + +; Load a general register into another general register + .macro mvr_h_gr src targ + move.d \src,\targ + .endm + +; Store an immediate into a word in memory + .macro mvi_h_mem val addr + mvi_h_gr \val r11 + mvr_h_mem r11,\addr + .endm + +; Store a register into a word in memory + .macro mvr_h_mem reg addr + move.d \addr,$r13 + move.d \reg,[$r13] + .endm + +; Store the current ps on the stack + .macro save_ps + .if ..asm.arch.cris.v32 + move ccs,acr ; Push will do a "subq" first. + push acr + .else + push dccr + .endif + .endm + +; Load a word value from memory + .macro ldmem_h_gr addr reg + move.d \addr,$r13 + move.d [$r13],\reg + .endm + +; Add 2 general registers + .macro add_h_gr reg1 reg2 + add.d \reg1,\reg2 + .endm + +; Increment a register by and immediate + .macro inci_h_gr inc reg + mvi_h_gr \inc,r11 + add.d r11,\reg + .endm + +; Test the value of an immediate against a general register + .macro test_h_gr val reg + cmp.d \val,\reg + beq 9f + nop + fail +9: + .endm + +; compare two general registers + .macro testr_h_gr reg1 reg2 + cmp.d \reg1,\reg2 + beq 9f + fail +9: + .endm + +; Test the value of an immediate against a dedicated register + .macro test_h_dr val reg + move \reg,$r12 + test_h_gr \val $r12 + .endm + +; Test the value of an general register against a dedicated register + .macro testr_h_dr gr dr + move \dr,$r12 + testr_h_gr \gr $r12 + .endm + +; Compare an immediate with word in memory + .macro test_h_mem val addr + ldmem_h_gr \addr $r12 + test_h_gr \val $r12 + .endm + +; Compare a general register with word in memory + .macro testr_h_mem reg addr + ldmem_h_gr \addr r12 + testr_h_gr \reg r12 + .endm + +; Set the condition codes +; The lower bits of the mask *are* nzvc, so we don't +; have to do anything strange. + .macro set_cc mask + move.w \mask,r13 + .if ..asm.arch.cris.v32 + move r13,ccs + .else + move r13,ccr + .endif + .endm + +; Set the stack mode +; .macro set_s_user +; orccr 0x20 +; .endm +; +; .macro set_s_system +; andccr 0x1f +; .endm +; +;; Test the stack mode +; .macro test_s_user +; mvr_h_gr ps,r9 +; mvi_h_gr 0x20,r11 +; and r11,r9 +; test_h_gr 0x20,r9 +; .endm +; +; .macro test_s_system +; mvr_h_gr ps,r9 +; mvi_h_gr 0x20,r11 +; and r11,r9 +; test_h_gr 0x0,r9 +; .endm + +; Set the interrupt bit +; ??? Do they mean "enable interrupts" or "disable interrupts"? +; Assuming enable here. + .macro set_i val + .if (\val == 1) + ei + .else + di + .endif + .endm + +; Test the stack mode +; .macro test_i val +; mvr_h_gr ps,r9 +; mvi_h_gr 0x10,r11 +; and r11,r9 +; .if (\val == 1) +; test_h_gr 0x10,r9 +; .else +; test_h_gr 0x0,r9 +; .endif +; .endm +; +;; Set the ilm +; .macro set_ilm val +; stilm \val +; .endm +; +;; Test the ilm +; .macro test_ilm val +; mvr_h_gr ps,r9 +; mvi_h_gr 0x1f0000,r11 +; and r11,r9 +; mvi_h_gr \val,r12 +; mvi_h_gr 0x1f,r11 +; and r11,r12 +; lsl 15,r12 +; lsl 1,r12 +; testr_h_gr r9,r12 +; .endm +; +; Test the condition codes + .macro test_cc N Z V C + .if \N + bpl 9f + nop + .else + bmi 9f + nop + .endif + .if \Z + bne 9f + nop + .else + beq 9f + nop + .endif + .if \V + bvc 9f + nop + .else + bvs 9f + nop + .endif + .if \C + bcc 9f + nop + .else + bcs 9f + nop + .endif + ba 8f + nop +9: + fail +8: + .endm + + .macro test_move_cc N Z V C + .if ..asm.arch.cris.v32 + ; V and C aren't affected on v32, so to re-use the test-cases, + ; we fake them cleared. There's a separate test, nonvcv32.ms + ; covering this omission. + clearf vc + test_cc \N \Z 0 0 + .else + test_cc \N \Z \V \C + .endif + .endm + +; Set the division bits +; .macro set_dbits val +; mvr_h_gr ps,r12 +; mvi_h_gr 0xfffff8ff,r11 +; and r11,r12 +; mvi_h_gr \val,r9 +; mvi_h_gr 3,r11 +; and r11,r9 +; lsl 9,r9 +; or r9,r12 +; mvr_h_gr r12,ps +; .endm +; +;; Test the division bits +; .macro test_dbits val +; mvr_h_gr ps,r9 +; lsr 9,r9 +; mvi_h_gr 3,r11 +; and r11,r9 +; test_h_gr \val,r9 +; .endm +; +; Save the return pointer + .macro save_rp + push srp + .ENDM + +; restore the return pointer + .macro restore_rp + pop srp + .endm + +; Ensure branch taken + .macro take_branch opcode + \opcode 9f + nop + fail +9: + .endm + + .macro take_branch_d opcode val + \opcode 9f + nop + move.d \val,r9 + fail +9: + test_h_gr \val,r9 + .endm + +; Ensure branch not taken + .macro no_branch opcode + \opcode 9f + nop + ba 8f + nop +9: + fail +8: + .endm + + .macro no_branch_d opcode val + \opcode 9f + move.d \val,r9 + nop + ba 8f + nop +9: + fail +8: + test_h_gr \val,r9 + .endm + diff --git a/sim/testsuite/cris/asm/tjmpsrv32-2.ms b/sim/testsuite/cris/asm/tjmpsrv32-2.ms new file mode 100644 index 0000000..dee0b29 --- /dev/null +++ b/sim/testsuite/cris/asm/tjmpsrv32-2.ms @@ -0,0 +1,55 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 37\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 6\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that we correctly account for that a "jas N,Pn", +; "jasc N,Pn", "bas N,Pn" and "basc N,Pn" sets the specific +; special register and causes a pipeline hazard. The amount +; of nops below is a bit inflated, in an attempt to make +; errors more discernible. For special registers, we just +; check SRP. + + .include "testutils.inc" + startnostack + move.d 0f,$r0 + jsr 0f + nop + nop + nop + jsrc 0f + nop + .dword -1 + nop + nop + jsr $r0 + nop + nop + nop + jsrc $r0 + nop + .dword -1 + nop + nop + bsr 0f + nop + nop + nop + bsrc 0f + nop + .dword -1 + nop + nop + break 15 + +0: + ret ; 1 cycle penalty. + nop diff --git a/sim/testsuite/cris/asm/tjmpsrv32.ms b/sim/testsuite/cris/asm/tjmpsrv32.ms new file mode 100644 index 0000000..1781c4f --- /dev/null +++ b/sim/testsuite/cris/asm/tjmpsrv32.ms @@ -0,0 +1,50 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 17\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 5\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that "ret"-type insns get the right number of penalty +; cycles for the special register source. + + .include "testutils.inc" + startnostack + move.d 1f,$r1 + move.d 0f,$r0 + move $r0,$mof + jump $mof ; 2 cycles penalty. + nop + +0: + move [$r1],$srp + nop + ret ; 1 cycle penalty. + nop + + break 15 + +0: + move 2f,$nrp + nop + nop + jump $nrp ; no penalty. + nop + + break 15 + +2: + move 3f,$srp ; 2 cycles penalty. + ret + nop + +3: + break 15 +1: + .dword 0b diff --git a/sim/testsuite/cris/asm/tjsrcv10.ms b/sim/testsuite/cris/asm/tjsrcv10.ms new file mode 100644 index 0000000..3bc6946 --- /dev/null +++ b/sim/testsuite/cris/asm/tjsrcv10.ms @@ -0,0 +1,29 @@ +#mach: crisv10 +#output: Basic clock cycles, total @: 6\n +#output: Memory source stall cycles: 1\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that the 4-byte-skip doesn't make the simulator barf. +; Nothing deeper. + + .include "testutils.inc" + startnostack + nop + move.d 0f,r5 + jsrc r5 + nop + .dword -1 +0: + jsrc 1f + nop + .dword -2 +1: + break 15 diff --git a/sim/testsuite/cris/asm/tjsrcv32.ms b/sim/testsuite/cris/asm/tjsrcv32.ms new file mode 100644 index 0000000..a777f01 --- /dev/null +++ b/sim/testsuite/cris/asm/tjsrcv32.ms @@ -0,0 +1,13 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 2\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "tjsrcv10.ms" diff --git a/sim/testsuite/cris/asm/tmemv10.ms b/sim/testsuite/cris/asm/tmemv10.ms new file mode 100644 index 0000000..40b32a9 --- /dev/null +++ b/sim/testsuite/cris/asm/tmemv10.ms @@ -0,0 +1,27 @@ +#mach: crisv10 +#output: Basic clock cycles, total @: 8\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that the memory indirection doesn't make the simulator barf. +; Nothing deeper. + + .include "testutils.inc" + startnostack + move.d 0f,r5 + move.d [r5],r4 + move.d [r5+],r3 + move.d [r5],r2 + break 15 + nop + .p2align 2 +0: + .dword 1,2,3 diff --git a/sim/testsuite/cris/asm/tmemv32.ms b/sim/testsuite/cris/asm/tmemv32.ms new file mode 100644 index 0000000..81ce211 --- /dev/null +++ b/sim/testsuite/cris/asm/tmemv32.ms @@ -0,0 +1,14 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 1\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + + .include "tmemv10.ms" diff --git a/sim/testsuite/cris/asm/tmulv10.ms b/sim/testsuite/cris/asm/tmulv10.ms new file mode 100644 index 0000000..3d855a2 --- /dev/null +++ b/sim/testsuite/cris/asm/tmulv10.ms @@ -0,0 +1,26 @@ +#mach: crisv10 +#output: Basic clock cycles, total @: 9\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that multiplications do not make the simulator barf. +; Nothing deeper. + + .include "testutils.inc" + startnostack + moveq 1,r3 + moveq 2,r1 + moveq 1,r0 + muls.d r0,r1 + muls.d r0,r3 + mulu.d r1,r3 + break 15 + nop diff --git a/sim/testsuite/cris/asm/tmulv32.ms b/sim/testsuite/cris/asm/tmulv32.ms new file mode 100644 index 0000000..3326054 --- /dev/null +++ b/sim/testsuite/cris/asm/tmulv32.ms @@ -0,0 +1,14 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 2\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + + .include "tmulv10.ms" diff --git a/sim/testsuite/cris/asm/tmvm1.ms b/sim/testsuite/cris/asm/tmvm1.ms new file mode 100644 index 0000000..c1c925d --- /dev/null +++ b/sim/testsuite/cris/asm/tmvm1.ms @@ -0,0 +1,53 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 18\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 6\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that movem to register followed by register write dword +; to one of the registers is logged as needing two stall cycles, +; regardless of size. + + .include "testutils.inc" + startnostack + move.d 0f,r5 + moveq 0,r8 + moveq 0,r9 + + movem [r5],r4 + move.d r8,r1 + addq 1,r1 ; 2 cycles. + + movem [r5],r4 + move.w r8,r1 + addq 1,r1 ; 2 cycles. + + movem [r5],r4 + move.b r8,r1 + addq 1,r1 ; 2 cycles. + + movem [r5],r4 + move.b r8,r1 + addq 1,r9 + + movem [r5],r4 + move.d r8,r1 + addq 1,r8 + + break 15 + + .data + .p2align 5 +0: + .dword 0b + .dword 0b + .dword 0b + .dword 0b + .dword 0b diff --git a/sim/testsuite/cris/asm/tmvm2.ms b/sim/testsuite/cris/asm/tmvm2.ms new file mode 100644 index 0000000..176d3cc --- /dev/null +++ b/sim/testsuite/cris/asm/tmvm2.ms @@ -0,0 +1,351 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: *\n +#output: Memory source stall cycles: 82\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 6\n +#output: Movem destination stall cycles: 880\n +#output: Movem address stall cycles: 4\n +#output: Multiplication source stall cycles: 18\n +#output: Jump source stall cycles: 6\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + + .include "testutils.inc" + +; Macros for testing correctness of movem destination stall +; cycles for various insn types. Beware: macro parameters can +; be comma or space-delimited. There are problems (i.e. bugs) +; with using space-delimited operands and operands with +; non-alphanumeric characters, like "[]-." so use comma for +; them. Lots of trouble passing empty parameters and parameters +; with comma. Ugh. FIXME: Report bugs, fix bugs, fix other +; shortcomings, fix that darn old macro-parameter-in-string. + +; Helper macro. Unfortunately I find no cleaner way to unify +; one and two-operand cases, the main problem being the comma +; operand delimiter clashing with macro operand delimiter. + .macro t_S_x_y S insn x y=none + movem [r7],r6 + .ifc \y,none + .ifc \S,none + \insn \x + .else + \insn\S \x + .endif + .else + .ifc \S,none + \insn \x,\y + .else + \insn\S \x,\y + .endif + .endif + nop + nop + nop + .endm + +; An insn-type that has a single register operand. The register +; may or may not be a source register for the insn. + .macro t_r insn + t_S_x_y none,\insn,r3 + t_S_x_y none,\insn,r8 + .endm + +; An insn-type that jumps to the destination of the register. + .macro t_r_j insn + move.d 0f,r7 + move.d 1f,r8 + move.d r8,r9 + nop + nop + nop + .section ".rodata" + .p2align 5 +0: + .dword 1f + .dword 1f + .dword 1f + .dword 1f + .dword 1f + .dword 1f + .dword 1f + .previous + t_r \insn +1: + .endm + +; An insn-type that has a size-modifier and two register +; operands. + .macro t_xr_r S insn + t_S_x_y \S \insn r3 r8 + t_S_x_y \S \insn r8 r3 + move.d r3,r9 + t_S_x_y \S \insn r4 r3 + t_S_x_y \S \insn r8 r9 + .endm + +; An insn-type that has two register operands. + .macro t_r_r insn + t_xr_r none \insn + .endm + +; An t_r_rx insn with a byte or word-size modifier. + .macro t_wbr_r insn + t_xr_r .b,\insn + t_xr_r .w,\insn + .endm + +; Ditto with a dword-size modifier. + .macro t_dwbr_r insn + t_xr_r .d,\insn + t_wbr_r \insn + .endm + +; An insn-type that has a size-modifier, a constant and a +; register operand. + .macro t_xc_r S insn + t_S_x_y \S \insn 24 r3 + move.d r3,r9 + t_S_x_y \S \insn 24 r8 + .endm + +; An insn-type that has a constant and a register operand. + .macro t_c_r insn + t_xc_r none \insn + .endm + +; An t_c_r insn with a byte or word-size modifier. + .macro t_wbc_r insn + t_xc_r .b,\insn + t_xc_r .w,\insn + .endm + +; Ditto with a dword-size modifier. + .macro t_dwbc_r insn + t_xc_r .d,\insn + t_wbc_r \insn + .endm + +; An insn-type that has size-modifier, a memory operand and a +; register operand. + .macro t_xm_r S insn + move.d 9b,r8 + t_S_x_y \S,\insn,[r4],r3 + move.d r3,r9 + t_S_x_y \S,\insn,[r8],r5 + move.d r5,r9 + t_S_x_y \S,\insn,[r3],r9 + t_S_x_y \S,\insn,[r8],r9 + .endm + +; Ditto, to memory. + .macro t_xr_m S insn + move.d 9b,r8 + t_S_x_y \S,\insn,r3,[r4] + t_S_x_y \S,\insn,r8,[r3] + t_S_x_y \S,\insn,r3,[r8] + t_S_x_y \S,\insn,r9,[r8] + .endm + +; An insn-type that has a memory operand and a register operand. + .macro t_m_r insn + t_xm_r none \insn + .endm + +; An t_m_r insn with a byte or word-size modifier. + .macro t_wbm_r insn + t_xm_r .b,\insn + t_xm_r .w,\insn + .endm + +; Ditto with a dword-size modifier. + .macro t_dwbm_r insn + t_xm_r .d,\insn + t_wbm_r \insn + .endm + +; Insn types of the regular type (r, c, m, size d w b). + .macro t_dwb insn + t_dwbr_r \insn + t_dwbc_r \insn + t_dwbm_r \insn + .endm + +; Similar, sizes w b. + .macro t_wb insn + t_wbr_r \insn + t_wbc_r \insn + t_wbm_r \insn + .endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + startnostack + +; Initialize registers so they don't contain unknowns. + + move.d 9f,r7 + move.d r7,r8 + moveq 0,r9 + +; Movem source area. Register contents must be valid +; addresses, aligned on a cache boundary. + .section ".rodata" + .p2align 5 +9: + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .previous + +; The actual tests. The numbers in the comments specify the +; number of movem destination stall cycles. Some of them may be +; filed as memory source address stalls, multiplication source +; stalls or jump source stalls, duly marked so. + + t_r_r abs ; 3+3 + + t_dwb add ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) + + t_r_r addc ; (3+3+3) + t_c_r addc ; 3 + t_m_r addc ; (3+3+3) (2 mem src) + + t_dwb move ; (3+3)+(3+3+3)*2+3*2+(3+3+3)*3 (6 mem src) + t_xr_m .b move ; 3+3+3 (2 mem src) + t_xr_m .w move ; 3+3+3 (2 mem src) + t_xr_m .d move ; 3+3+3 (2 mem src) + + t_S_x_y none addi r3.b r8 ; 3 + t_S_x_y none addi r8.w r3 ; 3 + t_S_x_y none addi r4.d r3 ; 3 + t_S_x_y none addi r8.w r9 + + ; Addo has three-operand syntax, so we have to expand (a useful + ; subset of) "t_dwb". + t_S_x_y none addi r3.b "r8,acr" ; 3 + t_S_x_y none addi r8.w "r3,acr" ; 3 + t_S_x_y none addi r4.d "r3,acr" ; 3 + t_S_x_y none addi r8.w "r9,acr" + + t_S_x_y .b addo 42 "r8,acr" + t_S_x_y .w addo 4200 "r3,acr" ; 3 + t_S_x_y .d addo 420000 "r3,acr" ; 3 + + move.d 9b,r8 + t_S_x_y .d,addo,[r4],"r3,acr" ; 3 (1 mem src) + t_S_x_y .b,addo,[r3],"r8,acr" ; 3 (1 mem src) + t_S_x_y .w,addo,[r8],"r3,acr" ; 3 + t_S_x_y .w,addo,[r8],"r9,acr" + + ; Similar for addoq. + t_S_x_y none addoq 42 "r8,acr" + t_S_x_y none addoq 42 "r3,acr" ; 3 + + t_c_r addq ; 3 + + t_wb adds ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) + t_wb addu ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) + + t_dwb and ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) + t_c_r andq ; 3 + + t_dwbr_r asr ; (3+3+3)*3 + t_c_r asrq ; 3 + + t_dwbr_r bound ; (3+3+3)*3 + t_dwbc_r bound ; 3*3 + + t_r_r btst ; (3+3+3) + t_c_r btstq ; 3 + + t_dwb cmp ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) + t_c_r cmpq ; 3 + + t_wbc_r cmps ; 3*2 + t_wbc_r cmpu ; 3*2 + t_wbm_r cmps ; (3+3+3)*2 (4 mem src) + t_wbm_r cmpu ; (3+3+3)*2 (4 mem src) + + t_r_r dstep ; (3+3+3) + + ; FIXME: idxd, fidxi, ftagd, ftagi when supported. + + t_r_j jsr ; 3 (2 jump src) + t_r_j jump ; 3 (2 jump src) + + t_c_r lapc.d + +; The "quick operand" must be in range [. to .+15*2] so we can't +; use t_c_r. + t_S_x_y none lapcq .+4 r3 + t_S_x_y none lapcq .+4 r8 + + t_dwbr_r lsl ; (3+3+3)*3 + t_c_r lslq ; 3 + + t_dwbr_r lsr ; (3+3+3)*3 + t_c_r lsrq ; 3 + + t_r_r lz ; 3+3 + + t_S_x_y none mcp srp r3 ; 3 + t_S_x_y none mcp srp r8 + + t_c_r moveq + + t_S_x_y none move srp r8 + t_S_x_y none move srp r3 + t_S_x_y none move r8 srp + t_S_x_y none move r3 srp ; 3 + +; FIXME: move supreg,Rd and move Rs,supreg when supported. + + t_wb movs ; (3+3)*2+0+(3+3)*2 (4 mem src) + t_wb movu ; (3+3)*2+0+(3+3)*2 (4 mem src) + + t_dwbr_r muls ; (3+3+3)*3 (9 mul src) + t_dwbr_r mulu ; (3+3+3)*3 (9 mul src) + + t_dwbr_r neg ; (3+3)*3 + + t_r not ; 3 cycles. + + t_dwb or ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) + t_c_r orq ; 3 + + t_r seq + + t_dwb sub ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) + t_c_r subq ; 3 + + t_wb subs ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) + t_wb subu ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) + + t_r swapw ; 3 cycles. + t_r swapnwbr ; 3 cycles. + + t_r_j jsrc ; 3 (2 jump src) + + t_r_r xor ; (3+3+3) + + move.d 9b,r7 + nop + nop + nop + t_xm_r none movem ; (3+3) (2 mem src, 1+1 movem addr) + ; As implied by the comment, all movem destination penalty + ; cycles (but one) are accounted for as memory source address + ; and movem source penalties. There are also two movem address + ; cache-line straddle penalties. + t_xr_m none movem ; (3+3+2+2) (2 mem, 6 movem src, +2 movem addr) + + break 15 diff --git a/sim/testsuite/cris/asm/tmvmrv10.ms b/sim/testsuite/cris/asm/tmvmrv10.ms new file mode 100644 index 0000000..66b9b1f --- /dev/null +++ b/sim/testsuite/cris/asm/tmvmrv10.ms @@ -0,0 +1,50 @@ +#mach: crisv10 +#output: Basic clock cycles, total @: 45\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that movem to register basically looks ok cycle-wise. +; Nothing deep. + + .include "testutils.inc" + startnostack + move.d 0f,r5 + moveq 0,r8 + moveq 0,r9 + +; Adapted from crisv32 movem-to-memory penalty examples many +; revisions ago. + + movem [r5],r4 + test.d [r3] ; 3 cycle penalty on v32 (2 memory source, 1 movem dest). + movem [r5],r4 + subq 1,r8 + test.d [r3] ; 2 cycle penalty on v32. + movem [r5],r4 + subq 1,r1 ; 3 cycle penalty on v32. + movem [r5],r4 + add.d r8,r9 + subq 1,r1 ; 2 cycle penalty on v32. + movem [r5],r4 + add.d r8,r9 + subq 1, r9 + subq 1, r1 ; 1 cycle penalty on v32. + break 15 + + .data + .p2align 5 +0: + .dword 0b + .dword 0b + .dword 0b + .dword 0b + .dword 0b + diff --git a/sim/testsuite/cris/asm/tmvmrv32.ms b/sim/testsuite/cris/asm/tmvmrv32.ms new file mode 100644 index 0000000..0501747 --- /dev/null +++ b/sim/testsuite/cris/asm/tmvmrv32.ms @@ -0,0 +1,14 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 17\n +#output: Memory source stall cycles: 1\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 10\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + + .include "tmvmrv10.ms" diff --git a/sim/testsuite/cris/asm/tmvrmv10.ms b/sim/testsuite/cris/asm/tmvrmv10.ms new file mode 100644 index 0000000..c782997 --- /dev/null +++ b/sim/testsuite/cris/asm/tmvrmv10.ms @@ -0,0 +1,40 @@ +#mach: crisv10 +#output: Basic clock cycles, total @: 31\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that movem to memory basically looks ok cycle-wise. +; Nothing deep. + + .include "testutils.inc" + startnostack + move.d 0f,r4 + moveq 0,r0 + moveq 1,r3 + moveq 2,r1 + moveq 1,r2 + movem r3,[r4] ; 2 cycles penalty for v32 + movem r3,[r4] ; 0 cycles penalty for v32 + moveq 1,r3 + nop + movem r3,[r4] ; 1 cycle penalty for v32 + moveq 1,r3 + nop + nop + movem r3,[r4] ; 0 cycles penalty for v32 + break 15 + + .data +0: + .dword 0 + .dword 0 + .dword 0 + .dword 0 diff --git a/sim/testsuite/cris/asm/tmvrmv32.ms b/sim/testsuite/cris/asm/tmvrmv32.ms new file mode 100644 index 0000000..339ab20 --- /dev/null +++ b/sim/testsuite/cris/asm/tmvrmv32.ms @@ -0,0 +1,14 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 14\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 3\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + + .include "tmvrmv10.ms" diff --git a/sim/testsuite/cris/asm/user.ms b/sim/testsuite/cris/asm/user.ms new file mode 100644 index 0000000..f6115bb --- /dev/null +++ b/sim/testsuite/cris/asm/user.ms @@ -0,0 +1,75 @@ +# mach: crisv32 +# output: 40\n40\n140\nabadefb0\n6543789c\n0\n0\n0\n0\n0\n0\n0\n0\n + +; Check for protected operations being NOP in user mode, for the +; parts implemented in this simulator. + + .include "testutils.inc" + start + move 0,ccs + move 0,usp + move 0,pid + move 0,srs + move 0,ebp + move 0,spc + setf u + +; Flag settings, besides what's tested in rfn.ms, rfe.ms and +; sfe.ms. + setf i + move ccs,r3 + dumpr3 ; 0x40 + + clearf u + move ccs,r3 + dumpr3 ; 0x40 + + move 0xc0000300,ccs + move ccs,r3 + dumpr3 ; 0x140 + +; R14==USP + move.d 0xabadefb0,r14 + nop + nop + nop + move usp,r3 + dumpr3 ; 0xabadefb0 + move 0x6543789c,usp + nop + nop + nop + move.d r14,r3 + dumpr3 ; 0x6543789c + +; We can't go back to kernel mode, so we can't check that R14 in +; kernel mode wasn't affected. + +; Moves to protected special registers. + .macro testsr reg,val=-1 + move \val,\reg + ; Registers shorter than dword will not affect the rest of the + ; general register when copied using a move insn. + clear.d r3 +; Three cycles are needed between move to protected register and +; read from it, to avoid reading undefined contents due to +; incomplete forwarding. + nop + nop + move \reg,r3 + dumpr3 + moveq \val,r3 + move r3,\reg + clear.d r3 + nop + nop + move \reg,r3 + dumpr3 + .endm + + testsr pid ; 0 0 + testsr srs,3 ; 0 0 + testsr ebp ; 0 0 + testsr spc ; 0 0 + + quit diff --git a/sim/testsuite/cris/asm/x0-v10.ms b/sim/testsuite/cris/asm/x0-v10.ms new file mode 100644 index 0000000..432819a --- /dev/null +++ b/sim/testsuite/cris/asm/x0-v10.ms @@ -0,0 +1,7 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 1\n +#sim: --cris-trace=basic + + .include "break.ms" diff --git a/sim/testsuite/cris/asm/x0-v32.ms b/sim/testsuite/cris/asm/x0-v32.ms new file mode 100644 index 0000000..bbcb0ec --- /dev/null +++ b/sim/testsuite/cris/asm/x0-v32.ms @@ -0,0 +1,7 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 0 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 1 0\n +#sim: --cris-trace=basic + + .include "break.ms" diff --git a/sim/testsuite/cris/asm/x1-v10.ms b/sim/testsuite/cris/asm/x1-v10.ms new file mode 100644 index 0000000..bfc4859 --- /dev/null +++ b/sim/testsuite/cris/asm/x1-v10.ms @@ -0,0 +1,10 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 2\n +#sim: --cris-trace=basic + +; With a "--cris-trace=all", cycles for the last line would be 3. + + .include "movect10.ms" diff --git a/sim/testsuite/cris/asm/x1-v32.ms b/sim/testsuite/cris/asm/x1-v32.ms new file mode 100644 index 0000000..d37cfdd --- /dev/null +++ b/sim/testsuite/cris/asm/x1-v32.ms @@ -0,0 +1,8 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 1 0\n +#sim: --cris-trace=basic + + .include "movect10.ms" diff --git a/sim/testsuite/cris/asm/x10-v10.ms b/sim/testsuite/cris/asm/x10-v10.ms new file mode 100644 index 0000000..4b7e4aa --- /dev/null +++ b/sim/testsuite/cris/asm/x10-v10.ms @@ -0,0 +1,21 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 3\n +#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#sim: --cris-trace=basic + +; Check that "add.d x,pc" gets 3 cycles. + + .include "testutils.inc" + startnostack + nop + nop + add.d 1f-0f,$pc +0: + nop +1: + nop + break 15 diff --git a/sim/testsuite/cris/asm/x2-v10.ms b/sim/testsuite/cris/asm/x2-v10.ms new file mode 100644 index 0000000..e2d5bbf --- /dev/null +++ b/sim/testsuite/cris/asm/x2-v10.ms @@ -0,0 +1,59 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n +#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n +#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n +#output: 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 16 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 18 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 1a 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 16 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 18 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 1a 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 16 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 18 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 1a 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 18 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 1a 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n +#output: 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n +#output: 1a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n +#output: 1c ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 1e ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 20 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 22 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 26 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 2\n +#output: 230 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 232 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 236 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 2\n +#output: 440 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 442 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 446 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 650 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 654 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 442 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 446 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 650 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 654 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 442 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 446 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 650 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 654 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 442 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 446 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 650 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 654 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 442 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n +#output: 446 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 2\n +#output: 650 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n +#output: 654 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 2\n +#output: 656 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 658 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 65a ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n + .include "tb.ms" diff --git a/sim/testsuite/cris/asm/x2-v32.ms b/sim/testsuite/cris/asm/x2-v32.ms new file mode 100644 index 0000000..0fdfcfd --- /dev/null +++ b/sim/testsuite/cris/asm/x2-v32.ms @@ -0,0 +1,59 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n +#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n +#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n +#output: 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 16 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 18 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1a 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 16 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 18 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1a 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 16 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 18 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1a 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 18 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1a 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 1a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 1c ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 1e ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 20 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 22 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 26 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 230 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 232 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 236 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 440 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 442 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 446 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 650 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n +#output: 654 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n +#output: 442 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 446 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 650 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 654 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 442 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 446 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 650 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 654 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 442 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 446 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 650 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 654 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 442 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 446 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 650 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 654 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 656 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 658 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 65a ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n + .include "tb.ms" diff --git a/sim/testsuite/cris/asm/x3-v10.ms b/sim/testsuite/cris/asm/x3-v10.ms new file mode 100644 index 0000000..fc54f3c --- /dev/null +++ b/sim/testsuite/cris/asm/x3-v10.ms @@ -0,0 +1,12 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 12 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 1e 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#sim: --cris-trace=basic + +; With a "--cris-trace=all", cycles for the third line would be 3. + + .include "tjsrcv10.ms" diff --git a/sim/testsuite/cris/asm/x3-v32.ms b/sim/testsuite/cris/asm/x3-v32.ms new file mode 100644 index 0000000..93a7436 --- /dev/null +++ b/sim/testsuite/cris/asm/x3-v32.ms @@ -0,0 +1,10 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 12 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1e 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#sim: --cris-trace=basic + + .include "tjsrcv10.ms" diff --git a/sim/testsuite/cris/asm/x4-v32.ms b/sim/testsuite/cris/asm/x4-v32.ms new file mode 100644 index 0000000..056c05c --- /dev/null +++ b/sim/testsuite/cris/asm/x4-v32.ms @@ -0,0 +1,23 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 8 0 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 10 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 12 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 14 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 16 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 18 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1a 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 24 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 26 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 28 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 2a 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 2e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 34 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 36 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 38 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#sim: --cris-trace=basic + + .include "tjmpsrv32.ms" diff --git a/sim/testsuite/cris/asm/x5-v10.ms b/sim/testsuite/cris/asm/x5-v10.ms new file mode 100644 index 0000000..ec5023e --- /dev/null +++ b/sim/testsuite/cris/asm/x5-v10.ms @@ -0,0 +1,9 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 8 0 0 0 0 0 14 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: a 0 0 0 0 1 14 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: c 0 0 0 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: e 0 0 2 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 2\n + .include "tmemv10.ms" diff --git a/sim/testsuite/cris/asm/x5-v32.ms b/sim/testsuite/cris/asm/x5-v32.ms new file mode 100644 index 0000000..62b3fca --- /dev/null +++ b/sim/testsuite/cris/asm/x5-v32.ms @@ -0,0 +1,9 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 8 0 0 0 0 0 14 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: a 0 0 0 0 1 14 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: c 0 0 0 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: e 0 0 2 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n + .include "tmemv10.ms" diff --git a/sim/testsuite/cris/asm/x6-v10.ms b/sim/testsuite/cris/asm/x6-v10.ms new file mode 100644 index 0000000..910daf8 --- /dev/null +++ b/sim/testsuite/cris/asm/x6-v10.ms @@ -0,0 +1,11 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 6 0 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 8 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: a 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: c 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: e 1 2 0 2 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n + .include "tmulv10.ms" diff --git a/sim/testsuite/cris/asm/x6-v32.ms b/sim/testsuite/cris/asm/x6-v32.ms new file mode 100644 index 0000000..19c5ada --- /dev/null +++ b/sim/testsuite/cris/asm/x6-v32.ms @@ -0,0 +1,11 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 6 0 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 8 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: a 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: c 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: e 1 2 0 2 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n + .include "tmulv10.ms" diff --git a/sim/testsuite/cris/asm/x7-v10.ms b/sim/testsuite/cris/asm/x7-v10.ms new file mode 100644 index 0000000..8b548ff --- /dev/null +++ b/sim/testsuite/cris/asm/x7-v10.ms @@ -0,0 +1,31 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: c 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 4\n +#output: e 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 10 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n +#output: 14 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n +#output: 18 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n +#output: 20 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 4\n +#sim: --cris-trace=basic + +; With a "--cris-trace=all", cycles for the third and last line would be 5. + +; Check that prefix+insn are traced as one. + + .include "testutils.inc" + startnostack + nop + move.d [0f],r3 + nop + moveq 0,r4 + move.d [r3+r4.b],r5 + move.d [r3+4],r5 + bdap.d 0,r3 + move.d [r3],r5 + break 15 + .p2align 2 +0: + .dword 0b + .dword 0b diff --git a/sim/testsuite/cris/asm/x7-v32.ms b/sim/testsuite/cris/asm/x7-v32.ms new file mode 100644 index 0000000..ea98ef0 --- /dev/null +++ b/sim/testsuite/cris/asm/x7-v32.ms @@ -0,0 +1,19 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvc 1 aa424243\n +#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 55212121\n +#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 1\n +#output: e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n + +; Check that trace with changing ACR works. + + .include "testutils.inc" + startnostack + move.d 0xaa424243,$acr + lsrq 1,$acr + moveq 1,$acr + clear.d $acr + break 15 + nop diff --git a/sim/testsuite/cris/asm/x8-v10.ms b/sim/testsuite/cris/asm/x8-v10.ms new file mode 100644 index 0000000..672cc21 --- /dev/null +++ b/sim/testsuite/cris/asm/x8-v10.ms @@ -0,0 +1,20 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 8 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: c 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: e 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#sim: --cris-trace=basic + +; Check that "jump [rN]" gets 2 cycles. + + .include "testutils.inc" + startnostack + move.d 0f,r5 + jump [r5] + break 15 +1: + nop + break 15 +0: + .dword 1b diff --git a/sim/testsuite/cris/asm/x9-v10.ms b/sim/testsuite/cris/asm/x9-v10.ms new file mode 100644 index 0000000..68472be --- /dev/null +++ b/sim/testsuite/cris/asm/x9-v10.ms @@ -0,0 +1,23 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 1\n +#output: 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 4\n +#output: 12 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 1\n +#sim: --cris-trace=basic + +; Check that "adds.w [$pc+$r9.w],$pc" gets 4 cycles. + + .include "testutils.inc" + startnostack + moveq 1,r9 + adds.w [$pc+$r9.w],$pc +0: + .word 1f-0b + .word 2f-0b + .word 1f-0b +1: + break 15 +2: + nop + break 15 diff --git a/sim/testsuite/cris/asm/xor.ms b/sim/testsuite/cris/asm/xor.ms new file mode 100644 index 0000000..2095dea --- /dev/null +++ b/sim/testsuite/cris/asm/xor.ms @@ -0,0 +1,47 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nff0\n0\n2c21b3db\n0\nffffffff\n + + .include "testutils.inc" + start + moveq 1,r3 + moveq 2,r4 + xor r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + moveq 1,r4 + xor r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xff0f,r4 + move.d 0xf0ff,r3 + xor r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff0 + + moveq -1,r4 + move.d r4,r3 + xor r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + xor r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2c21b3db + + moveq 0,r4 + moveq 0,r3 + xor r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x7fffffff,r3 + move.d 0x80000000,r4 + xor r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + quit diff --git a/sim/testsuite/cris/c/access1.c b/sim/testsuite/cris/c/access1.c new file mode 100644 index 0000000..ba9be34 --- /dev/null +++ b/sim/testsuite/cris/c/access1.c @@ -0,0 +1,16 @@ +/* Check access(2) trivially. Newlib doesn't have it. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include +int main (int argc, char **argv) +{ + if (access (argv[0], R_OK|W_OK|X_OK) == 0 + && access ("/dev/null", R_OK|W_OK) == 0 + && access ("/dev/null", X_OK) == -1 + && errno == EACCES) + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/append1.c b/sim/testsuite/cris/c/append1.c new file mode 100644 index 0000000..0acd59d --- /dev/null +++ b/sim/testsuite/cris/c/append1.c @@ -0,0 +1,51 @@ +/* Check regression of a bug uncovered by the libio tFile test (old + libstdc++, pre-gcc-3.x era), where appending to a file doesn't work. + The default open-flags-mapping does not match Linux/CRIS, so a + specific mapping is necessary. */ + +#include +#include +#include + +int +main (void) +{ + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt1[] + = "This is the first and only line of this file.\n"; + const char tsttxt2[] = "Now there is a second line.\n"; + char buf[sizeof (tsttxt1) + sizeof (tsttxt2) - 1] = ""; + + f = fopen (fname, "w+"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + f = fopen (fname, "a+"); + if (f == NULL + || fwrite (tsttxt2, 1, strlen (tsttxt2), f) != strlen (tsttxt2) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + f = fopen (fname, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != sizeof (buf) - 1 + || strncmp (buf, tsttxt1, strlen (tsttxt1)) != 0 + || strncmp (buf + strlen (tsttxt1), tsttxt2, strlen (tsttxt2)) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/badldso1.c b/sim/testsuite/cris/c/badldso1.c new file mode 100644 index 0000000..58caa8d --- /dev/null +++ b/sim/testsuite/cris/c/badldso1.c @@ -0,0 +1,7 @@ +/* +#notarget: cris*-*-elf +#dynamic: +#xerror: +#output: *: could not load ELF interpreter `*' for program `*'\n + */ +#include "hello.c" diff --git a/sim/testsuite/cris/c/badldso2.c b/sim/testsuite/cris/c/badldso2.c new file mode 100644 index 0000000..db28889 --- /dev/null +++ b/sim/testsuite/cris/c/badldso2.c @@ -0,0 +1,8 @@ +/* +#notarget: cris*-*-elf +#dynamic: +#xerror: +#cc: additional_flags=-Wl,-dynamic-linker,/dev/null +#output: *: could not load ELF interpreter `*' for program `*'\n + */ +#include "hello.c" diff --git a/sim/testsuite/cris/c/badldso3.c b/sim/testsuite/cris/c/badldso3.c new file mode 100644 index 0000000..3f9509b --- /dev/null +++ b/sim/testsuite/cris/c/badldso3.c @@ -0,0 +1,9 @@ +/* +#notarget: cris*-*-elf +#dynamic: +#xerror: +#cc: additional_flags=-Wl,-dynamic-linker,/compilercheck.x +#sim: --sysroot=@exedir@ +#output: *: could not load ELF interpreter `*' for program `*'\n + */ +#include "hello.c" diff --git a/sim/testsuite/cris/c/c.exp b/sim/testsuite/cris/c/c.exp new file mode 100644 index 0000000..08ea188 --- /dev/null +++ b/sim/testsuite/cris/c/c.exp @@ -0,0 +1,253 @@ +# Copyright (C) 2005-2021 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# Miscellaneous CRIS simulator testcases testing syscall sequences. + +if ![istarget cris*-*-*] { + return +} + +set CFLAGS_FOR_TARGET "-O2" +if [istarget cris-*-*] { + set mach "crisv10" +} { + set mach "crisv32" +} + +if [istarget cris*-*-elf] { + append CFLAGS_FOR_TARGET " -sim" +} + +# Using target_compile, since it is less noisy, +if { [target_compile $srcdir/$subdir/hello.c compilercheck.x \ + "executable" "" ] == "" } { + set has_cc 1 + + # Now check if we can link a program dynamically, and where + # libc.so is located. If it is, we provide a sym link to the + # directory (which must end in /lib) in [pwd], so /lib/ld.so.1 is + # found (which must reside along libc.so). We don't bother + # replacing the board ldflags like below as we don't care about + # detrimental effects on the executable from the specs and + # -static in the board ldflags, we just add -Bdynamic. + if [regexp "(.*/lib)/libc.so" \ + [target_compile $srcdir/$subdir/hello.c compilercheck.x \ + "executable" \ + "ldflags=-print-file-name=libc.so -Wl,-Bdynamic"] \ + xxx libcsodir] { + file delete lib + verbose -log "Creating link to $libcsodir in [pwd]" + file link lib $libcsodir + } +} { + verbose -log "Can't execute C compiler" + set has_cc 0 +} + +# Like istarget, except take a list of targets as a string. +proc anytarget { targets } { + set targetlist [split $targets] + set argc [llength $targetlist] + for { set i 0 } { $i < $argc } { incr i } { + if [istarget [lindex $targetlist $i]] { + return 1 + } + } + return 0 +} + +foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.c]] { + set orig_ldflags "" + + if ![runtest_file_p $runtests $src] { + continue + } + set testname "[file tail $src]" + + set opt_array [slurp_options $src] + if { $opt_array == -1 } { + unresolved $testname + return + } + + # And again, to simplify specifying tests. + if ![runtest_file_p $runtests $src] { + continue + } + + # Note absence of CC in results, but don't make a big fuss over it. + if { $has_cc == 0 } { + untested $testname + continue + } + + # Clear default options + set opts(cc) "" + set opts(sim) "" + set opts(output) "" + set opts(progoptions) "" + set opts(timeout) "" + set opts(mach) "" + set opts(xerror) "no" + set opts(dest) "$testname.x" + set opts(simenv) "" + set opts(kfail) "" + set opts(xfail) "" + set opts(target) "" + set opts(notarget) "" + set opts(dynamic) "" + + # Clear any machine specific options specified in a previous test case + if [info exists opts(sim,$mach)] { + unset opts(sim,$mach) + } + + foreach i $opt_array { + set opt_name [lindex $i 0] + set opt_machs [lindex $i 1] + set opt_val [lindex $i 2] + if ![info exists opts($opt_name)] { + perror "unknown option $opt_name in file $src" + unresolved $testname + return + } + + # Replace specific substitutions: + # @exedir@ is where the test-program is located. + regsub -all "@exedir@" $opt_val "[pwd]" opt_val + # @srcdir@ is where the source of the test-program is located. + regsub -all "@srcdir@" $opt_val "$srcdir/$subdir" opt_val + + # Multiple of these options concatenate, they don't override. + if { $opt_name == "output" || $opt_name == "progoptions" } { + set opt_val "$opts($opt_name)$opt_val" + } + + # Similar with "xfail", "kfail", "target" and "notarget", but + # arguments are space-separated. + if { $opt_name == "xfail" || $opt_name == "kfail" \ + || $opt_name == "target" || $opt_name == "notarget" } { + if { $opts($opt_name) != "" } { + set opt_val "$opts($opt_name) $opt_val" + } + } + + if { $opt_name == "dynamic" \ + && [info exists board_info([target_info name],ldflags)] } { + # Weed out -static from ldflags, but keep the original in + # $orig_ldflags. + set orig_ldflags $board_info([target_info name],ldflags) + set ldflags " $orig_ldflags " + regsub -all " -static " $ldflags " " ldflags + set board_info([target_info name],ldflags) $ldflags + } + + foreach m $opt_machs { + set opts($opt_name,$m) $opt_val + } + if { "$opt_machs" == "" } { + set opts($opt_name) $opt_val + } + } + + if { $opts(output) == "" } { + if { "$opts(xerror)" == "no" } { + set opts(output) "pass\n" + } else { + set opts(output) "fail\n" + } + } + + if { $opts(target) != "" && ![anytarget $opts(target)] } { + continue + } + + if { $opts(notarget) != "" && [anytarget $opts(notarget)] } { + continue + } + + # If no machine specific options, default to the general version. + if ![info exists opts(sim,$mach)] { + set opts(sim,$mach) $opts(sim) + } + + # Change \n sequences to newline chars. + regsub -all "\\\\n" $opts(output) "\n" opts(output) + + verbose -log "Compiling $src with $opts(cc)" + + set dest "$opts(dest)" + if { [sim_compile $src $dest "executable" "$opts(cc)" ] != "" } { + unresolved $testname + continue + } + + if { $orig_ldflags != "" } { + set board_info([target_info name],ldflags) $orig_ldflags + } + + verbose -log "Simulating $src with $opts(sim,$mach)" + + # Time to setup xfailures and kfailures. + if { "$opts(xfail)" != "" } { + verbose -log "xfail: $opts(xfail)" + # Using eval to make $opts(xfail) appear as individual + # arguments. + eval setup_xfail $opts(xfail) + } + if { "$opts(kfail)" != "" } { + verbose -log "kfail: $opts(kfail)" + eval setup_kfail $opts(kfail) + } + + set result [sim_run $dest "$opts(sim,$mach)" "$opts(progoptions)" \ + "" "$opts(simenv)"] + set return_code [lindex $result 0] + set output [lindex $result 1] + + set status fail + if { $return_code == 0 } { + set status pass + } + + if { "$status" == "pass" } { + if { "$opts(xerror)" == "no" } { + if [string match $opts(output) $output] { + pass "$mach $testname" + } else { + verbose -log "output: $output" 3 + verbose -log "pattern: $opts(output)" 3 + fail "$mach $testname (execution)" + } + } else { + verbose -log "`pass' return code when expecting failure" 3 + fail "$mach $testname (execution)" + } + } elseif { "$status" == "fail" } { + if { "$opts(xerror)" == "no" } { + fail "$mach $testname (execution)" + } else { + if [string match $opts(output) $output] { + pass "$mach $testname" + } else { + verbose -log "output: $output" 3 + verbose -log "pattern: $opts(output)" 3 + fail "$mach $testname (execution)" + } + } + } else { + $status "$mach $testname" + } +} diff --git a/sim/testsuite/cris/c/clone1.c b/sim/testsuite/cris/c/clone1.c new file mode 100644 index 0000000..163b186 --- /dev/null +++ b/sim/testsuite/cris/c/clone1.c @@ -0,0 +1,90 @@ +/* +#notarget: cris*-*-elf +#output: got: a\nthen: bc\nexit: 0\n +*/ + +/* This is a very limited subset of what ex1.c does; we just check that + thread creation (clone syscall) and pipe writes and reads work. */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int pip[2]; + +int +process (void *arg) +{ + char *s = arg; + if (write (pip[1], s+2, 1) != 1) abort (); + if (write (pip[1], s+1, 1) != 1) abort (); + if (write (pip[1], s, 1) != 1) abort (); + return 0; +} + +int +main (void) +{ + int retcode; + int pid; + int st; + long stack[16384]; + char buf[10] = {0}; + + retcode = pipe (pip); + + if (retcode != 0) + { + fprintf (stderr, "Bad pipe %d\n", retcode); + abort (); + } + + pid = clone (process, (char *) stack + sizeof (stack) - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "cba"); + if (pid <= 0) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + if ((retcode = read (pip[0], buf, 1)) != 1) + { + fprintf (stderr, "Bad read 1: %d\n", retcode); + abort (); + } + printf ("got: %c\n", buf[0]); + retcode = read (pip[0], buf, 2); + if (retcode == 1) + { + retcode = read (pip[0], buf+1, 1); + if (retcode != 1) + { + fprintf (stderr, "Bad read 1.5: %d\n", retcode); + abort (); + } + retcode = 2; + } + if (retcode != 2) + { + fprintf (stderr, "Bad read 2: %d\n", retcode); + abort (); + } + + printf ("then: %s\n", buf); + retcode = wait4 (-1, &st, WNOHANG | __WCLONE, NULL); + + if (retcode != pid || !WIFEXITED (st)) + { + fprintf (stderr, "Bad wait %d %x\n", retcode, st); + abort (); + } + + printf ("exit: %d\n", WEXITSTATUS (st)); + return 0; +} diff --git a/sim/testsuite/cris/c/clone2.c b/sim/testsuite/cris/c/clone2.c new file mode 100644 index 0000000..e433a77 --- /dev/null +++ b/sim/testsuite/cris/c/clone2.c @@ -0,0 +1,6 @@ +/* Make sure the thread system trivially works with trace output. +#notarget: cris*-*-elf +#sim: --cris-trace=basic --trace-file=@exedir@/clone2.tmp +#output: got: a\nthen: bc\nexit: 0\n +*/ +#include "clone1.c" diff --git a/sim/testsuite/cris/c/clone3.c b/sim/testsuite/cris/c/clone3.c new file mode 100644 index 0000000..0a97484 --- /dev/null +++ b/sim/testsuite/cris/c/clone3.c @@ -0,0 +1,45 @@ +/* Check that exiting from a parent thread does not kill the child. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int +process (void *arg) +{ + int i; + + for (i = 0; i < 50; i++) + if (sched_yield ()) + abort (); + + printf ("pass\n"); + return 0; +} + +int +main (void) +{ + int pid; + long stack[16384]; + + pid = clone (process, (char *) stack + sizeof (stack) - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "ab"); + if (pid <= 0) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + exit (0); +} diff --git a/sim/testsuite/cris/c/clone4.c b/sim/testsuite/cris/c/clone4.c new file mode 100644 index 0000000..81489dd --- /dev/null +++ b/sim/testsuite/cris/c/clone4.c @@ -0,0 +1,61 @@ +/* Check that TRT happens when we reach the #threads implementation limit. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int +process (void *arg) +{ + int i; + + for (i = 0; i < 500; i++) + if (sched_yield ()) + abort (); + + return 0; +} + +int +main (void) +{ + int pid; + int i; + int stacksize = 16384; + + for (i = 0; i < 1000; i++) + { + char *stack = malloc (stacksize); + if (stack == NULL) + abort (); + + pid = clone (process, (char *) stack + stacksize - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "ab"); + if (pid <= 0) + { + /* FIXME: Read sysconf instead of magic number. */ + if (i < 60) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + if (errno == EAGAIN) + { + printf ("pass\n"); + exit (0); + } + } + } + + abort (); +} diff --git a/sim/testsuite/cris/c/clone5.c b/sim/testsuite/cris/c/clone5.c new file mode 100644 index 0000000..9380a1e --- /dev/null +++ b/sim/testsuite/cris/c/clone5.c @@ -0,0 +1,35 @@ +/* Check that unimplemented clone syscalls get the right treatment. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented clone syscall * +#output: program stopped with signal 4 (*).\n +*/ + +#include +#include +#include +#include +#include +#include +#include + +int pip[2]; + +int +process (void *arg) +{ + return 0; +} + +int +main (void) +{ + int retcode; + long stack[16384]; + + retcode = clone (process, (char *) stack + sizeof (stack) - 64, 0, "cba"); + if (retcode == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + return 0; +} diff --git a/sim/testsuite/cris/c/clone6.c b/sim/testsuite/cris/c/clone6.c new file mode 100644 index 0000000..586b5c6 --- /dev/null +++ b/sim/testsuite/cris/c/clone6.c @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "clone5.c" diff --git a/sim/testsuite/cris/c/ex1.c b/sim/testsuite/cris/c/ex1.c new file mode 100644 index 0000000..2447319 --- /dev/null +++ b/sim/testsuite/cris/c/ex1.c @@ -0,0 +1,54 @@ +/* Compiler options: +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#output: Starting process a\naaaaaaaaStarting process b\nababbbbbbbbb + + The output will change depending on the exact syscall sequence per + thread, so will change with glibc versions. Prepare to modify; use + the latest glibc. + + This file is from glibc/linuxthreads, with the difference that the + number is 10, not 10000. */ + +/* Creates two threads, one printing 10000 "a"s, the other printing + 10000 "b"s. + Illustrates: thread creation, thread joining. */ + +#include +#include +#include +#include "pthread.h" + +static void * +process (void *arg) +{ + int i; + fprintf (stderr, "Starting process %s\n", (char *) arg); + for (i = 0; i < 10; i++) + { + write (1, (char *) arg, 1); + } + return NULL; +} + +int +main (void) +{ + int retcode; + pthread_t th_a, th_b; + void *retval; + + retcode = pthread_create (&th_a, NULL, process, (void *) "a"); + if (retcode != 0) + fprintf (stderr, "create a failed %d\n", retcode); + retcode = pthread_create (&th_b, NULL, process, (void *) "b"); + if (retcode != 0) + fprintf (stderr, "create b failed %d\n", retcode); + retcode = pthread_join (th_a, &retval); + if (retcode != 0) + fprintf (stderr, "join a failed %d\n", retcode); + retcode = pthread_join (th_b, &retval); + if (retcode != 0) + fprintf (stderr, "join b failed %d\n", retcode); + return 0; +} diff --git a/sim/testsuite/cris/c/exitg1.c b/sim/testsuite/cris/c/exitg1.c new file mode 100644 index 0000000..0b4c425 --- /dev/null +++ b/sim/testsuite/cris/c/exitg1.c @@ -0,0 +1,20 @@ +/* Check exit_group(2) trivially. Newlib doesn't have it and the + pre-v32 glibc requires updated headers we'd have to check or adjust + for. +#notarget: cris-*-* *-*-elf +#output: exit_group\n +*/ +#include +#include +#include +#include +#ifndef EXITVAL +#define EXITVAL 0 +#endif +int main (int argc, char **argv) +{ + printf ("exit_group\n"); + syscall (SYS_exit_group, EXITVAL); + printf ("failed\n"); + abort (); +} diff --git a/sim/testsuite/cris/c/exitg2.c b/sim/testsuite/cris/c/exitg2.c new file mode 100644 index 0000000..e222cc4 --- /dev/null +++ b/sim/testsuite/cris/c/exitg2.c @@ -0,0 +1,7 @@ +/* Check exit_group(2) trivially with non-zero status. +#notarget: cris-*-* *-*-elf +#output: exit_group\n +#xerror: +*/ +#define EXITVAL 1 +#include "exitg1.c" diff --git a/sim/testsuite/cris/c/fcntl1.c b/sim/testsuite/cris/c/fcntl1.c new file mode 100644 index 0000000..032f6b5 --- /dev/null +++ b/sim/testsuite/cris/c/fcntl1.c @@ -0,0 +1,19 @@ +/* Check that we get the expected message for unsupported fcntl calls. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented fcntl* +#output: program stopped with signal 4 (*).\n +*/ +#include +#include +#include +#include + +int main (void) +{ + int err = fcntl (1, 42); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/fcntl2.c b/sim/testsuite/cris/c/fcntl2.c new file mode 100644 index 0000000..fc9f95b --- /dev/null +++ b/sim/testsuite/cris/c/fcntl2.c @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "fcntl1.c" diff --git a/sim/testsuite/cris/c/fdopen1.c b/sim/testsuite/cris/c/fdopen1.c new file mode 100644 index 0000000..cdfe19a --- /dev/null +++ b/sim/testsuite/cris/c/fdopen1.c @@ -0,0 +1,54 @@ +/* Check that the syscalls implementing fdopen work trivially. */ + +#include +#include +#include +#include +#include + +void +perr (const char *s) +{ + perror (s); + exit (1); +} + +int +main (void) +{ + FILE *f; + int fd; + const char fname[] = "sk1test.dat"; + const char tsttxt1[] + = "This is the first and only line of this file.\n"; + char buf[sizeof (tsttxt1)] = ""; + + fd = open (fname, O_WRONLY|O_TRUNC|O_CREAT, S_IRWXU); + if (fd <= 0) + perr ("open-w"); + + f = fdopen (fd, "w"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1)) + perr ("fdopen or fwrite"); + + if (fclose (f) != 0) + perr ("fclose"); + + fd = open (fname, O_RDONLY); + if (fd <= 0) + perr ("open-r"); + + f = fdopen (fd, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != strlen (tsttxt1) + || strcmp (buf, tsttxt1) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/fdopen2.c b/sim/testsuite/cris/c/fdopen2.c new file mode 100644 index 0000000..6a59f36 --- /dev/null +++ b/sim/testsuite/cris/c/fdopen2.c @@ -0,0 +1,52 @@ +/* Check that the syscalls implementing fdopen work trivially. +#output: This is the first line of this test.\npass\n +*/ + +#include +#include +#include +#include +#include + +void +perr (const char *s) +{ + perror (s); + exit (1); +} + +int +main (void) +{ + FILE *f; + int fd; + const char fname[] = "sk1test.dat"; + const char tsttxt1[] + = "This is the first line of this test.\n"; + char buf[sizeof (tsttxt1)] = ""; + + /* Write a line to stdout. */ + f = fdopen (1, "w"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1)) + perr ("fdopen or fwrite"); + +#if 0 + /* Unfortunately we can't get < /dev/null to the simulator with + reasonable test-framework surgery. */ + + /* Try to read from stdin. Expect EOF. */ + f = fdopen (0, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != 0 + || feof (f) == 0 + || ferror (f) != 0) + { + printf ("fail\n"); + exit (1); + } +#endif + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/freopen1.c b/sim/testsuite/cris/c/freopen1.c new file mode 100644 index 0000000..0e0f28d --- /dev/null +++ b/sim/testsuite/cris/c/freopen1.c @@ -0,0 +1,49 @@ +/* Check that basic freopen functionality works. */ + +#include +#include +#include + +int +main (void) +{ + FILE *old_stderr; + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt[] + = "A random line of text, used to test correct freopen etc.\n"; + char buf[sizeof tsttxt] = ""; + + /* Like the freopen call in flex. */ + old_stderr = freopen (fname, "w+", stderr); + if (old_stderr == NULL + || fwrite (tsttxt, 1, strlen (tsttxt), stderr) != strlen (tsttxt) + || fclose (stderr) != 0) + { + printf ("fail\n"); + exit (1); + } + + /* Using "rb" to make this test similar to the use in genconf.c in + GhostScript. */ + f = fopen (fname, "rb"); + if (f == NULL + || fseek (f, 0L, SEEK_END) != 0 + || ftell (f) != strlen (tsttxt)) + { + printf ("fail\n"); + exit (1); + } + + rewind (f); + if (fread (buf, 1, strlen (tsttxt), f) != strlen (tsttxt) + || strcmp (buf, tsttxt) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/freopen2.c b/sim/testsuite/cris/c/freopen2.c new file mode 100644 index 0000000..3959607 --- /dev/null +++ b/sim/testsuite/cris/c/freopen2.c @@ -0,0 +1,40 @@ +/* Tests that stdin can be redirected from a normal file. */ +#include +#include +#include + +int +main (void) +{ + const char* fname = "freopen.dat"; + const char tsttxt[] + = "A random line of text, used to test correct freopen etc.\n"; + FILE* instream; + FILE *old_stderr; + char c1; + + /* Like the freopen call in flex. */ + old_stderr = freopen (fname, "w+", stderr); + if (old_stderr == NULL + || fwrite (tsttxt, 1, strlen (tsttxt), stderr) != strlen (tsttxt) + || fclose (stderr) != 0) + { + printf ("fail\n"); + exit (1); + } + + instream = freopen(fname, "r", stdin); + if (instream == NULL) { + printf("fail\n"); + exit(1); + } + + c1 = getc(instream); + if (c1 != 'A') { + printf("fail\n"); + exit(1); + } + + printf ("pass\n"); + exit(0); +} diff --git a/sim/testsuite/cris/c/ftruncate1.c b/sim/testsuite/cris/c/ftruncate1.c new file mode 100644 index 0000000..46b8756 --- /dev/null +++ b/sim/testsuite/cris/c/ftruncate1.c @@ -0,0 +1,52 @@ +/* Check that the ftruncate syscall works trivially. +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +void +perr (const char *s) +{ + perror (s); + exit (1); +} + +int +main (void) +{ + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt1[] + = "This is the first and only line of this file.\n"; + const char tsttxt2[] = "Now there is a second line.\n"; + char buf[sizeof (tsttxt1) + sizeof (tsttxt2) - 1] = ""; + + f = fopen (fname, "w+"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1)) + perr ("open or fwrite"); + + if (fflush (f) != 0) + perr ("fflush"); + + if (ftruncate (fileno (f), strlen(tsttxt1) - 20) != 0) + perr ("ftruncate"); + + if (fclose (f) != 0) + perr ("fclose"); + + f = fopen (fname, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != strlen (tsttxt1) - 20 + || strncmp (buf, tsttxt1, strlen (tsttxt1) - 20) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/ftruncate2.c b/sim/testsuite/cris/c/ftruncate2.c new file mode 100644 index 0000000..f1ef18c --- /dev/null +++ b/sim/testsuite/cris/c/ftruncate2.c @@ -0,0 +1,39 @@ +/* +#notarget: cris*-*-elf +*/ + +/* Check that we get a proper error indication if trying ftruncate on a + fd that is a pipe descriptor. */ + +#include +#include +#include +#include +int main (void) +{ + int pip[2]; + + if (pipe (pip) != 0) + { + perror ("pipe"); + abort (); + } + + if (ftruncate (pip[0], 20) == 0 || errno != EINVAL) + { + perror ("ftruncate 1"); + abort (); + } + + errno = 0; + + if (ftruncate (pip[1], 20) == 0 || errno != EINVAL) + { + perror ("ftruncate 2"); + abort (); + } + + printf ("pass\n"); + + exit (0); +} diff --git a/sim/testsuite/cris/c/getcwd1.c b/sim/testsuite/cris/c/getcwd1.c new file mode 100644 index 0000000..3838916 --- /dev/null +++ b/sim/testsuite/cris/c/getcwd1.c @@ -0,0 +1,18 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + if (getcwd ((void *) -1, 4096) != NULL + || errno != EFAULT) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/gettod.c b/sim/testsuite/cris/c/gettod.c new file mode 100644 index 0000000..18a000c --- /dev/null +++ b/sim/testsuite/cris/c/gettod.c @@ -0,0 +1,27 @@ +/* Basic time functionality test. */ +#include +#include +#include +#include +int +main (void) +{ + struct timeval t_m = {0, 0}; + time_t t; + + if ((t = time (NULL)) == (time_t) -1 + || gettimeofday (&t_m, NULL) != 0 + || t_m.tv_sec == 0 + + /* We assume there will be no delay between the time and + gettimeofday calls above, but allow a timer-tick to make the + seconds increase by one. */ + || (t != t_m.tv_sec && t+1 != t_m.tv_sec)) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/hello.c b/sim/testsuite/cris/c/hello.c new file mode 100644 index 0000000..fb403ba --- /dev/null +++ b/sim/testsuite/cris/c/hello.c @@ -0,0 +1,7 @@ +#include +#include +int main () +{ + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/helloaout.c b/sim/testsuite/cris/c/helloaout.c new file mode 100644 index 0000000..c71a658 --- /dev/null +++ b/sim/testsuite/cris/c/helloaout.c @@ -0,0 +1,14 @@ +/* Make sure we don't just assume ELF all over. (We have to jump + through hoops to get runnable a.out out of the ELF setup, and + having problems with a.out and discontinous section arrangements + doesn't help. Adjust as needed to get a.out which says "pass". If + necessary, move to the asm subdir. By design, it doesn't work with + CRIS v32.) + +NB: We'd rely on kfail, but that doesn't skip compilation, and that's where +the crash in ld happens to break the testcase. +#target: disabled-cris-*-elf +#kfail: ld/13900 cris-*-elf +#cc: ldflags=-Wl,-mcrisaout\ -sim\ -Ttext=0 +*/ +#include "hello.c" diff --git a/sim/testsuite/cris/c/hellodyn.c b/sim/testsuite/cris/c/hellodyn.c new file mode 100644 index 0000000..dc8042f --- /dev/null +++ b/sim/testsuite/cris/c/hellodyn.c @@ -0,0 +1,5 @@ +/* +#dynamic: +#sim: --sysroot=@exedir@ + */ +#include "hello.c" diff --git a/sim/testsuite/cris/c/hellodyn2.c b/sim/testsuite/cris/c/hellodyn2.c new file mode 100644 index 0000000..00f5369 --- /dev/null +++ b/sim/testsuite/cris/c/hellodyn2.c @@ -0,0 +1,5 @@ +/* +#dynamic: +#sim: --sysroot=@exedir@ --load-vma + */ +#include "hello.c" diff --git a/sim/testsuite/cris/c/hellodyn3.c b/sim/testsuite/cris/c/hellodyn3.c new file mode 100644 index 0000000..8ae3a4f --- /dev/null +++ b/sim/testsuite/cris/c/hellodyn3.c @@ -0,0 +1,9 @@ +/* Check that invoking ld.so as a program, invoking the main program, + works. Jump through a few hoops to avoid reading the host + ld.so.cache (having no absolute path specified for the executable + falls back on loading through the same mechanisms as a DSO). +#notarget: *-*-elf +#dynamic: +#sim: --sysroot=@exedir@ @exedir@/lib/ld.so.1 --library-path / + */ +#include "hello.c" diff --git a/sim/testsuite/cris/c/kill1.c b/sim/testsuite/cris/c/kill1.c new file mode 100644 index 0000000..e5c53a0 --- /dev/null +++ b/sim/testsuite/cris/c/kill1.c @@ -0,0 +1,30 @@ +/* Basic kill functionality test; fail killing init. Don't run as root. */ +#include +#include +#include +#include +#include +int +main (void) +{ + if (kill (1, SIGTERM) != -1 + || errno != EPERM) + { + printf ("fail\n"); + exit (1); + } + + errno = 0; + + if (kill (1, SIGABRT) != -1 + || errno != EPERM) + { + printf ("fail\n"); + exit (1); + } + + errno = 0; + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/kill2.c b/sim/testsuite/cris/c/kill2.c new file mode 100644 index 0000000..0a79db0 --- /dev/null +++ b/sim/testsuite/cris/c/kill2.c @@ -0,0 +1,18 @@ +/* Basic kill functionality test; suicide. +#xerror: +#output: program stopped with signal 6 (*).\n +*/ + +#include +#include +#include +#include +#include + +int +main (void) +{ + kill (getpid (), SIGABRT); + printf ("undead\n"); + exit (1); +} diff --git a/sim/testsuite/cris/c/kill3.c b/sim/testsuite/cris/c/kill3.c new file mode 100644 index 0000000..c0e2179 --- /dev/null +++ b/sim/testsuite/cris/c/kill3.c @@ -0,0 +1,16 @@ +/* Basic kill functionality test; suicide. +#xerror: +#output: program stopped with signal 6 (*).\n +*/ + +#include +#include +#include +#include +int +main (void) +{ + abort (); + printf ("undead\n"); + exit (1); +} diff --git a/sim/testsuite/cris/c/mapbrk.c b/sim/testsuite/cris/c/mapbrk.c new file mode 100644 index 0000000..1aff762 --- /dev/null +++ b/sim/testsuite/cris/c/mapbrk.c @@ -0,0 +1,39 @@ +#include +#include + +/* Basic sanity check that syscalls to implement malloc (brk, mmap2, + munmap) are trivially functional. */ + +int main () +{ + void *p1, *p2, *p3, *p4, *p5, *p6; + + if ((p1 = malloc (8100)) == NULL + || (p2 = malloc (16300)) == NULL + || (p3 = malloc (4000)) == NULL + || (p4 = malloc (500)) == NULL + || (p5 = malloc (1023*1024)) == NULL + || (p6 = malloc (8191*1024)) == NULL) + { + printf ("fail\n"); + exit (1); + } + + free (p1); + free (p2); + free (p3); + free (p4); + free (p5); + free (p6); + + p1 = malloc (64000); + if (p1 == NULL) + { + printf ("fail\n"); + exit (1); + } + free (p1); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/mmap1.c b/sim/testsuite/cris/c/mmap1.c new file mode 100644 index 0000000..9db94c1 --- /dev/null +++ b/sim/testsuite/cris/c/mmap1.c @@ -0,0 +1,52 @@ +/* +#notarget: cris*-*-elf +*/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int fd = open (argv[0], O_RDONLY); + struct stat sb; + int size; + void *a; + const char *str = "a string you'll only find in the program"; + + if (fd == -1) + { + perror ("open"); + abort (); + } + + if (fstat (fd, &sb) < 0) + { + perror ("fstat"); + abort (); + } + + size = sb.st_size; + + /* We want to test mmapping a size that isn't exactly a page. */ + if ((size & 8191) == 0) + size--; + +#ifndef MMAP_FLAGS +#define MMAP_FLAGS MAP_PRIVATE +#endif + + a = mmap (NULL, size, PROT_READ, MMAP_FLAGS, fd, 0); + + if (memmem (a, size, str, strlen (str) + 1) == NULL) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/mmap2.c b/sim/testsuite/cris/c/mmap2.c new file mode 100644 index 0000000..35139a0 --- /dev/null +++ b/sim/testsuite/cris/c/mmap2.c @@ -0,0 +1,48 @@ +/* +#notarget: cris*-*-elf +*/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int fd = open (argv[0], O_RDONLY); + struct stat sb; + int size; + void *a; + const char *str = "a string you'll only find in the program"; + + if (fd == -1) + { + perror ("open"); + abort (); + } + + if (fstat (fd, &sb) < 0) + { + perror ("fstat"); + abort (); + } + + size = sb.st_size; + + /* We want to test mmapping a size that isn't exactly a page. */ + if ((size & 8191) == 0) + size--; + + a = mmap (NULL, size, PROT_READ, MAP_SHARED, fd, 0); + + if (memmem (a, size, str, strlen (str) + 1) == NULL) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/mmap3.c b/sim/testsuite/cris/c/mmap3.c new file mode 100644 index 0000000..34401fa --- /dev/null +++ b/sim/testsuite/cris/c/mmap3.c @@ -0,0 +1,33 @@ +/* +#notarget: cris*-*-elf +*/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + volatile unsigned char *a; + + /* Check that we can map a non-multiple of a page and still get a full page. */ + a = mmap (NULL, 0x4c, PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (a == NULL || a == (unsigned char *) -1) + abort (); + + a[0] = 0xbe; + a[8191] = 0xef; + memset ((char *) a + 1, 0, 8190); + + if (a[0] != 0xbe || a[8191] != 0xef) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/mmap4.c b/sim/testsuite/cris/c/mmap4.c new file mode 100644 index 0000000..b3a66e4 --- /dev/null +++ b/sim/testsuite/cris/c/mmap4.c @@ -0,0 +1,5 @@ +/* Just check that MAP_DENYWRITE is "honored" (ignored). +#notarget: cris*-*-elf +*/ +#define MMAP_FLAGS (MAP_PRIVATE|MAP_DENYWRITE) +#include "mmap1.c" diff --git a/sim/testsuite/cris/c/mmap5.c b/sim/testsuite/cris/c/mmap5.c new file mode 100644 index 0000000..95f00c3 --- /dev/null +++ b/sim/testsuite/cris/c/mmap5.c @@ -0,0 +1,91 @@ +/* +#notarget: cris*-*-elf +*/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int fd = open (argv[0], O_RDONLY); + struct stat sb; + int size; + void *a; + void *b; + const char *str = "a string you'll only find in the program"; + + if (fd == -1) + { + perror ("open"); + abort (); + } + + if (fstat (fd, &sb) < 0) + { + perror ("fstat"); + abort (); + } + + size = 8192; +#ifdef MMAP_SIZE1 + size = MMAP_SIZE1; +#endif + +#ifndef MMAP_PROT1 +#define MMAP_PROT1 PROT_READ | PROT_WRITE | PROT_EXEC +#endif + +#ifndef MMAP_FLAGS1 +#define MMAP_FLAGS1 MAP_PRIVATE | MAP_ANONYMOUS +#endif + + /* Get a page, any page. */ + b = mmap (NULL, size, MMAP_PROT1, MMAP_FLAGS1, -1, 0); + if (b == MAP_FAILED) + abort (); + + /* Remember it, unmap it. */ +#ifndef NO_MUNMAP + if (munmap (b, size) != 0) + abort (); +#endif + +#ifdef MMAP_ADDR2 + b = MMAP_ADDR2; +#endif + +#ifndef MMAP_PROT2 +#define MMAP_PROT2 PROT_READ | PROT_EXEC +#endif + +#ifndef MMAP_FLAGS2 +#define MMAP_FLAGS2 MAP_DENYWRITE | MAP_FIXED | MAP_PRIVATE +#endif + + size = sb.st_size; +#ifdef MMAP_SIZE2 + size = MMAP_SIZE2; +#endif + +#define MMAP_TEST_BAD_ORIG \ + (a == MAP_FAILED || memmem (a, size, str, strlen (str) + 1) == NULL) +#ifndef MMAP_TEST_BAD +#define MMAP_TEST_BAD MMAP_TEST_BAD_ORIG +#endif + + /* Try mapping the now non-mapped page fixed. */ + a = mmap (b, size, MMAP_PROT2, MMAP_FLAGS2, fd, 0); + + if (MMAP_TEST_BAD) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/mmap6.c b/sim/testsuite/cris/c/mmap6.c new file mode 100644 index 0000000..929d9cc --- /dev/null +++ b/sim/testsuite/cris/c/mmap6.c @@ -0,0 +1,8 @@ +/* Check that mmapping specifying a previously mmapped address without + MAP_FIXED works; that we just don't get the same address. +#notarget: cris*-*-elf +*/ +#define NO_MUNMAP +#define MMAP_FLAGS2 MAP_PRIVATE +#define MMAP_TEST_BAD (a == b || MMAP_TEST_BAD_ORIG) +#include "mmap5.c" diff --git a/sim/testsuite/cris/c/mmap7.c b/sim/testsuite/cris/c/mmap7.c new file mode 100644 index 0000000..c4b14b0 --- /dev/null +++ b/sim/testsuite/cris/c/mmap7.c @@ -0,0 +1,14 @@ +/* Check that mmapping a page-aligned size, larger than the file, + works. + +#notarget: cris*-*-elf +*/ + +/* Make sure we get an address where the size fits. */ +#define MMAP_SIZE1 ((sb.st_size + 8192) & ~8191) + +/* If this ever fails because the file is a page-multiple, we'll deal + with that then. We want it larger than the file-size anyway. */ +#define MMAP_SIZE2 ((size + 8192) & ~8191) +#define MMAP_FLAGS2 MAP_DENYWRITE | MAP_PRIVATE | MAP_FIXED +#include "mmap5.c" diff --git a/sim/testsuite/cris/c/mmap8.c b/sim/testsuite/cris/c/mmap8.c new file mode 100644 index 0000000..0564c79 --- /dev/null +++ b/sim/testsuite/cris/c/mmap8.c @@ -0,0 +1,9 @@ +/* Check that mmapping 0 using MAP_FIXED works, both with/without + there being previously mmapped contents. +#notarget: cris*-*-elf +*/ +#define MMAP_FLAGS1 MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED +#define NO_MUNMAP +#define MMAP_SIZE2 8192 +#define MMAP_TEST_BAD (a != b || a != 0) +#include "mmap5.c" diff --git a/sim/testsuite/cris/c/mprotect1.c b/sim/testsuite/cris/c/mprotect1.c new file mode 100644 index 0000000..8dae50b --- /dev/null +++ b/sim/testsuite/cris/c/mprotect1.c @@ -0,0 +1,19 @@ +/* Check unimplemented-output for mprotect call. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented mprotect call (0x0, 0x2001, 0x4)\n +#output: program stopped with signal 4 (*).\n + */ +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int err = mprotect (0, 8193, PROT_EXEC); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/mprotect2.c b/sim/testsuite/cris/c/mprotect2.c new file mode 100644 index 0000000..4d83945 --- /dev/null +++ b/sim/testsuite/cris/c/mprotect2.c @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "mprotect1.c" diff --git a/sim/testsuite/cris/c/mremap.c b/sim/testsuite/cris/c/mremap.c new file mode 100644 index 0000000..e78a8a4 --- /dev/null +++ b/sim/testsuite/cris/c/mremap.c @@ -0,0 +1,31 @@ +#include +#include + +/* Sanity check that system calls for realloc works. Also tests a few + more cases for mmap2 and munmap. */ + +int main () +{ + void *p1, *p2; + + if ((p1 = malloc (8100)) == NULL + || (p1 = realloc (p1, 16300)) == NULL + || (p1 = realloc (p1, 4000)) == NULL + || (p1 = realloc (p1, 500)) == NULL + || (p1 = realloc (p1, 1023*1024)) == NULL + || (p1 = realloc (p1, 8191*1024)) == NULL + || (p1 = realloc (p1, 512*1024)) == NULL + || (p2 = malloc (1023*1024)) == NULL + || (p1 = realloc (p1, 1023*1024)) == NULL + || (p1 = realloc (p1, 8191*1024)) == NULL + || (p1 = realloc (p1, 512*1024)) == NULL) + { + printf ("fail\n"); + exit (1); + } + + free (p1); + free (p2); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/openpf1.c b/sim/testsuite/cris/c/openpf1.c new file mode 100644 index 0000000..e0d8e5c --- /dev/null +++ b/sim/testsuite/cris/c/openpf1.c @@ -0,0 +1,38 @@ +/* Check that --sysroot is applied to open(2). +#sim: --sysroot=@exedir@ + + We assume, with EXE being the name of the executable: + - The simulator executes with cwd the same directory where the executable + is located (so argv[0] contains a plain filename without directory + components). + - There's no /EXE on the host file system. */ + +#include +#include +#include +#include +int main (int argc, char *argv[]) +{ + char *fnam = argv[0]; + FILE *f; + if (argv[0][0] != '/') + { + fnam = malloc (strlen (argv[0]) + 2); + if (fnam == NULL) + abort (); + strcpy (fnam, "/"); + strcat (fnam, argv[0]); + } + + f = fopen (fnam, "rb"); + if (f == NULL) + abort (); + fclose (f); + + /* Cover another execution path. */ + if (fopen ("/nonexistent", "rb") != NULL + || errno != ENOENT) + abort (); + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/cris/c/openpf2.c b/sim/testsuite/cris/c/openpf2.c new file mode 100644 index 0000000..50337b1 --- /dev/null +++ b/sim/testsuite/cris/c/openpf2.c @@ -0,0 +1,16 @@ +/* Check that the simulator has chdir:ed to the --sysroot argument +#sim: --sysroot=@srcdir@ + (or that --sysroot is applied to relative file paths). */ + +#include +#include +#include +int main (int argc, char *argv[]) +{ + FILE *f = fopen ("openpf2.c", "rb"); + if (f == NULL) + abort (); + fclose (f); + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/cris/c/openpf3.c b/sim/testsuite/cris/c/openpf3.c new file mode 100644 index 0000000..557adee --- /dev/null +++ b/sim/testsuite/cris/c/openpf3.c @@ -0,0 +1,49 @@ +/* Basic file operations (rename, unlink); once without sysroot. We + also test that the simulator has chdir:ed to PREFIX, when defined. */ + +#include +#include +#include +#include +#include +#include + +#ifndef PREFIX +#define PREFIX +#endif + +void err (const char *s) +{ + perror (s); + abort (); +} + +int main (int argc, char *argv[]) +{ + FILE *f; + struct stat buf; + + unlink (PREFIX "testfoo2.tmp"); + + f = fopen ("testfoo1.tmp", "w"); + if (f == NULL) + err ("open"); + fclose (f); + + if (rename (PREFIX "testfoo1.tmp", PREFIX "testfoo2.tmp") != 0) + err ("rename"); + + if (stat (PREFIX "testfoo2.tmp", &buf) != 0 + || !S_ISREG (buf.st_mode)) + err ("stat 1"); + + if (stat ("testfoo2.tmp", &buf) != 0 + || !S_ISREG (buf.st_mode)) + err ("stat 2"); + + if (unlink (PREFIX "testfoo2.tmp") != 0) + err ("unlink"); + + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/cris/c/openpf4.c b/sim/testsuite/cris/c/openpf4.c new file mode 100644 index 0000000..d3fdcfe --- /dev/null +++ b/sim/testsuite/cris/c/openpf4.c @@ -0,0 +1,5 @@ +/* Basic file operations, now *with* sysroot. +#sim: --sysroot=@exedir@ +*/ +#define PREFIX "/" +#include "openpf3.c" diff --git a/sim/testsuite/cris/c/openpf5.c b/sim/testsuite/cris/c/openpf5.c new file mode 100644 index 0000000..1f86ea2 --- /dev/null +++ b/sim/testsuite/cris/c/openpf5.c @@ -0,0 +1,56 @@ +/* Check that TRT happens when error on too many opened files. +#notarget: cris*-*-elf +#sim: --sysroot=@exedir@ +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int i; + int filemax; + +#ifdef OPEN_MAX + filemax = OPEN_MAX; +#else + filemax = sysconf (_SC_OPEN_MAX); +#endif + + char *fn = malloc (strlen (argv[0]) + 2); + if (fn == NULL) + abort (); + strcpy (fn, "/"); + strcat (fn, argv[0]); + + for (i = 0; i < filemax + 1; i++) + { + if (open (fn, O_RDONLY) < 0) + { + /* Shouldn't happen too early. */ + if (i < filemax - 3 - 1) + { + fprintf (stderr, "i: %d\n", i); + abort (); + } + if (errno != EMFILE) + { + perror ("open"); + abort (); + } + goto ok; + } + } + abort (); + +ok: + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/pipe1.c b/sim/testsuite/cris/c/pipe1.c new file mode 100644 index 0000000..735974b --- /dev/null +++ b/sim/testsuite/cris/c/pipe1.c @@ -0,0 +1,48 @@ +/* Check for proper pipe semantics at corner cases. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int main (void) +{ + int i; + int filemax; + +#ifdef OPEN_MAX + filemax = OPEN_MAX; +#else + filemax = sysconf (_SC_OPEN_MAX); +#endif + + if (filemax < 10) + abort (); + + /* Check that pipes don't leak file descriptors. */ + for (i = 0; i < filemax * 10; i++) + { + int pip[2]; + if (pipe (pip) != 0) + { + perror ("pipe"); + abort (); + } + + if (close (pip[0]) != 0 || close (pip[1]) != 0) + { + perror ("close"); + abort (); + } + } + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/pipe2.c b/sim/testsuite/cris/c/pipe2.c new file mode 100644 index 0000000..18ccf38 --- /dev/null +++ b/sim/testsuite/cris/c/pipe2.c @@ -0,0 +1,143 @@ +/* Check that closing a pipe with a nonempty buffer works. +#notarget: cris*-*-elf +#output: got: a\ngot: b\nexit: 0\n +*/ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +int pip[2]; + +int pipemax; + +int +process (void *arg) +{ + char *s = arg; + int lots = pipemax + 256; + char *buf = malloc (lots); + int ret; + + if (buf == NULL) + abort (); + + *buf = *s; + + /* The first write should go straight through. */ + if (write (pip[1], buf, 1) != 1) + abort (); + + *buf = s[1]; + + /* The second write may or may not be successful for the whole + write, but should be successful for at least the pipemax part. + As linux/limits.h clamps PIPE_BUF to 4096, but the page size is + actually 8k, we can get away with that much. There should be no + error, though. Doing this on host shows that for + x86_64-unknown-linux-gnu (2.6.14-1.1656_FC4) pipemax * 10 can be + successfully written, perhaps for similar reasons. */ + ret = write (pip[1], buf, lots); + if (ret < pipemax) + { + fprintf (stderr, "ret: %d, %s, %d\n", ret, strerror (errno), pipemax); + fflush (0); + abort (); + } + + return 0; +} + +int +main (void) +{ + int retcode; + int pid; + int st = 0; + long stack[16384]; + char buf[1]; + + /* We need to turn this off because we don't want (to have to model) a + SIGPIPE resulting from the close. */ + if (signal (SIGPIPE, SIG_IGN) != SIG_DFL) + abort (); + + retcode = pipe (pip); + + if (retcode != 0) + { + fprintf (stderr, "Bad pipe %d\n", retcode); + abort (); + } + +#ifdef PIPE_MAX + pipemax = PIPE_MAX; +#else + pipemax = fpathconf (pip[1], _PC_PIPE_BUF); +#endif + + if (pipemax <= 0) + { + fprintf (stderr, "Bad pipemax %d\n", pipemax); + abort (); + } + + pid = clone (process, (char *) stack + sizeof (stack) - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "ab"); + if (pid <= 0) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + while ((retcode = read (pip[0], buf, 1)) == 0) + ; + + if (retcode != 1) + { + fprintf (stderr, "Bad read 1: %d\n", retcode); + abort (); + } + + printf ("got: %c\n", buf[0]); + + /* Need to read out something from the second write too before + closing, or the writer can get EPIPE. */ + while ((retcode = read (pip[0], buf, 1)) == 0) + ; + + if (retcode != 1) + { + fprintf (stderr, "Bad read 2: %d\n", retcode); + abort (); + } + + printf ("got: %c\n", buf[0]); + + if (close (pip[0]) != 0) + { + perror ("pip close"); + abort (); + } + + retcode = waitpid (pid, &st, __WALL); + + if (retcode != pid || !WIFEXITED (st)) + { + fprintf (stderr, "Bad wait %d:%d %x\n", pid, retcode, st); + perror ("errno"); + abort (); + } + + printf ("exit: %d\n", WEXITSTATUS (st)); + return 0; +} diff --git a/sim/testsuite/cris/c/pipe3.c b/sim/testsuite/cris/c/pipe3.c new file mode 100644 index 0000000..bf08a38 --- /dev/null +++ b/sim/testsuite/cris/c/pipe3.c @@ -0,0 +1,48 @@ +/* Check that TRT happens when error on pipe call. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + int i; + int filemax; + +#ifdef OPEN_MAX + filemax = OPEN_MAX; +#else + filemax = sysconf (_SC_OPEN_MAX); +#endif + + /* Check that TRT happens when error on pipe call. */ + for (i = 0; i < filemax + 1; i++) + { + int pip[2]; + if (pipe (pip) != 0) + { + /* Shouldn't happen too early. */ + if (i < filemax / 2 - 3 - 1) + { + fprintf (stderr, "i: %d\n", i); + abort (); + } + if (errno != EMFILE) + { + perror ("pipe"); + abort (); + } + goto ok; + } + } + abort (); + +ok: + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/pipe4.c b/sim/testsuite/cris/c/pipe4.c new file mode 100644 index 0000000..1cb309f --- /dev/null +++ b/sim/testsuite/cris/c/pipe4.c @@ -0,0 +1,66 @@ +/* Check that TRT happens for pipe corner cases. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include +#include +#include +#include + +void err (const char *s) +{ + perror (s); + abort (); +} + +int main (void) +{ + int pip[2]; + char c; + int pipemax; + + if (pipe (pip) != 0) + err ("pipe"); + +#ifdef PIPE_MAX + pipemax = PIPE_MAX; +#else + pipemax = fpathconf (pip[1], _PC_PIPE_BUF); +#endif + + if (pipemax <= 0) + { + fprintf (stderr, "Bad pipemax %d\n", pipemax); + abort (); + } + + /* Writing to wrong end of pipe. */ + if (write (pip[0], "argh", 1) != -1 + || errno != EBADF) + err ("write pipe"); + + errno = 0; + + /* Reading from wrong end of pipe. */ + if (read (pip[1], &c, 1) != -1 + || errno != EBADF) + err ("write pipe"); + + errno = 0; + + if (close (pip[0]) != 0) + err ("close"); + + if (signal (SIGPIPE, SIG_IGN) != SIG_DFL) + err ("signal"); + + /* Writing to pipe with closed read end. */ + if (write (pip[1], "argh", 1) != -1 + || errno != EPIPE) + err ("write closed"); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/pipe5.c b/sim/testsuite/cris/c/pipe5.c new file mode 100644 index 0000000..2b4d763 --- /dev/null +++ b/sim/testsuite/cris/c/pipe5.c @@ -0,0 +1,59 @@ +/* Check that TRT happens for pipe corner cases (for our definition of TRT). +#notarget: cris*-*-elf +#xerror: +#output: Terminating simulation due to writing pipe * from one single thread\n +#output: program stopped with signal 4 (*).\n +*/ +#include +#include +#include +#include +#include +#include +#include + +void err (const char *s) +{ + perror (s); + abort (); +} + +int main (void) +{ + int pip[2]; + int pipemax; + char *buf; + + if (pipe (pip) != 0) + err ("pipe"); + +#ifdef PIPE_MAX + pipemax = PIPE_MAX; +#else + pipemax = fpathconf (pip[1], _PC_PIPE_BUF); +#endif + + if (pipemax <= 0) + { + fprintf (stderr, "Bad pipemax %d\n", pipemax); + abort (); + } + + /* Writing an inordinate amount to the pipe. */ + buf = calloc (100 * pipemax, 1); + if (buf == NULL) + err ("calloc"); + + /* The following doesn't trig on host; writing more than PIPE_MAX to a + pipe with no reader makes the program hang. Neither does it trig + on target: we don't want to emulate the "hanging" (which would + happen with *any* amount written to a pipe with no reader if we'd + support it - but we don't). Better to abort the simulation with a + suitable message. */ + if (write (pip[1], buf, 100 * pipemax) != -1 + || errno != EFBIG) + err ("write mucho"); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/pipe6.c b/sim/testsuite/cris/c/pipe6.c new file mode 100644 index 0000000..a8830cc --- /dev/null +++ b/sim/testsuite/cris/c/pipe6.c @@ -0,0 +1,111 @@ +/* Check that writing an inordinate amount of data works (somewhat). +#notarget: cris*-*-elf +#output: got: a\nexit: 0\n + This test-case will *not* work on host (or for real): the first + pipemax+1 bytes will be successfully written. It's just for + exercising a rare execution path. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int pip[2]; + +int pipemax; + +int +process (void *arg) +{ + char *s = arg; + char *buf = calloc (pipemax * 100, 1); + int ret; + + if (buf == NULL) + abort (); + + *buf = *s; + + ret = write (pip[1], buf, pipemax * 100); + if (ret != -1 || errno != EFBIG) + { + perror ("write"); + abort (); + } + + return 0; +} + +int +main (void) +{ + int retcode; + int pid; + int st = 0; + long stack[16384]; + char buf[1]; + + retcode = pipe (pip); + + if (retcode != 0) + { + fprintf (stderr, "Bad pipe %d\n", retcode); + abort (); + } + +#ifdef PIPE_MAX + pipemax = PIPE_MAX; +#else + pipemax = fpathconf (pip[1], _PC_PIPE_BUF); +#endif + + if (pipemax <= 0) + { + fprintf (stderr, "Bad pipemax %d\n", pipemax); + abort (); + } + + pid = clone (process, (char *) stack + sizeof (stack) - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "ab"); + if (pid <= 0) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + while ((retcode = read (pip[0], buf, 1)) == 0) + ; + + if (retcode != 1) + { + fprintf (stderr, "Bad read 1: %d\n", retcode); + abort (); + } + + printf ("got: %c\n", buf[0]); + + if (close (pip[0]) != 0) + { + perror ("pip close"); + abort (); + } + + retcode = waitpid (pid, &st, __WALL); + + if (retcode != pid || !WIFEXITED (st)) + { + fprintf (stderr, "Bad wait %d:%d %x\n", pid, retcode, st); + perror ("errno"); + abort (); + } + + printf ("exit: %d\n", WEXITSTATUS (st)); + return 0; +} diff --git a/sim/testsuite/cris/c/pipe7.c b/sim/testsuite/cris/c/pipe7.c new file mode 100644 index 0000000..552ddb8 --- /dev/null +++ b/sim/testsuite/cris/c/pipe7.c @@ -0,0 +1,21 @@ +/* Check for proper pipe semantics at corner cases. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + if (pipe (NULL) != -1 + || errno != EFAULT) + { + perror ("pipe"); + abort (); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/readlink1.c b/sim/testsuite/cris/c/readlink1.c new file mode 100644 index 0000000..1898e8e --- /dev/null +++ b/sim/testsuite/cris/c/readlink1.c @@ -0,0 +1,20 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + char buf[1024]; + /* This depends on the test-setup, but it's unlikely that the program + is passed as a symlink, so supposedly safe. */ + if (readlink(argv[0], buf, sizeof (buf)) != -1 || errno != EINVAL) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/readlink10.c b/sim/testsuite/cris/c/readlink10.c new file mode 100644 index 0000000..2174408 --- /dev/null +++ b/sim/testsuite/cris/c/readlink10.c @@ -0,0 +1,18 @@ +/* Check that odd cases of readlink work. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + if (readlink("/proc/42/exe", NULL, 4096) != -1 + || errno != EFAULT) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/readlink11.c b/sim/testsuite/cris/c/readlink11.c new file mode 100644 index 0000000..05a332f --- /dev/null +++ b/sim/testsuite/cris/c/readlink11.c @@ -0,0 +1,9 @@ +/* As readlink5.c (sic), but specifying silent ENOSYS. +#notarget: cris*-*-elf +#dest: ./readlink11.c.x +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "readlink2.c" diff --git a/sim/testsuite/cris/c/readlink2.c b/sim/testsuite/cris/c/readlink2.c new file mode 100644 index 0000000..e5e9d94 --- /dev/null +++ b/sim/testsuite/cris/c/readlink2.c @@ -0,0 +1,80 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + char buf[1024]; + char buf2[1024]; + int err; + + /* This is a special feature handled in the simulator. The "42" + should be formed from getpid () if this was a real program. */ + err = readlink ("/proc/42/exe", buf, sizeof (buf)); + if (err < 0) + { + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); + } + + /* Don't use an abort in the following; it might cause the printf to + not make it all the way to output and make debugging more + difficult. */ + + /* We assume the program is called with no path, so we might need to + prepend it. */ + if (getcwd (buf2, sizeof (buf2)) != buf2) + { + perror ("getcwd"); + exit (1); + } + + if (argv[0][0] == '/') + { +#ifdef SYSROOTED + if (strchr (argv[0] + 1, '/') != NULL) + { + printf ("%s != %s\n", argv[0], strrchr (argv[0] + 1, '/')); + exit (1); + } +#endif + if (strcmp (argv[0], buf) != 0) + { + printf ("%s != %s\n", buf, argv[0]); + exit (1); + } + } + else if (argv[0][0] != '.') + { + if (buf2[strlen (buf2) - 1] != '/') + strcat (buf2, "/"); + strcat (buf2, argv[0]); + if (strcmp (buf2, buf) != 0) + { + printf ("%s != %s\n", buf, buf2); + exit (1); + } + } + else + { + strcat (buf2, argv[0] + 1); + if (strcmp (buf, buf2) != 0) + { + printf ("%s != %s\n", buf, buf2); + exit (1); + } + } + + printf ("pass\n"); + exit (0); +} + + diff --git a/sim/testsuite/cris/c/readlink3.c b/sim/testsuite/cris/c/readlink3.c new file mode 100644 index 0000000..94cff72 --- /dev/null +++ b/sim/testsuite/cris/c/readlink3.c @@ -0,0 +1,6 @@ +/* Simulator options: +#notarget: cris*-*-elf +#sim: --sysroot=@exedir@ +*/ +#define SYSROOTED 1 +#include "readlink2.c" diff --git a/sim/testsuite/cris/c/readlink4.c b/sim/testsuite/cris/c/readlink4.c new file mode 100644 index 0000000..028f3ee --- /dev/null +++ b/sim/testsuite/cris/c/readlink4.c @@ -0,0 +1,62 @@ +/* Check for corner case: readlink of too-long name. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +void bye (const char *s, int i) +{ + fprintf (stderr, "%s: %d\n", s, i); + fflush (NULL); + abort (); +} + +int main (int argc, char *argv[]) +{ + char *buf; + char buf2[1024]; + int max, i; + + /* We assume this limit is what we see in the simulator as well. */ +#ifdef PATH_MAX + max = PATH_MAX; +#else + max = pathconf (argv[0], _PC_PATH_MAX); +#endif + + max *= 10; + + if (max <= 0) + bye ("path_max", max); + + if ((buf = malloc (max + 1)) == NULL) + bye ("malloc", 0); + + strcat (buf, argv[0]); + + if (strrchr (buf, '/') == NULL) + strcat (buf, "./"); + + for (i = strrchr (buf, '/') - buf + 1; i < max; i++) + buf[i] = 'a'; + + buf [i] = 0; + + i = readlink (buf, buf2, sizeof (buf2) - 1); + if (i != -1) + bye ("i", i); + + if (errno != ENAMETOOLONG) + { + perror (buf); + bye ("errno", errno); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/readlink5.c b/sim/testsuite/cris/c/readlink5.c new file mode 100644 index 0000000..80f20da --- /dev/null +++ b/sim/testsuite/cris/c/readlink5.c @@ -0,0 +1,8 @@ +/* Check that unsupported readlink calls don't cause the simulator to abort. +#notarget: cris*-*-elf +#dest: ./readlink5.c.x +#xerror: +#output: Unimplemented readlink syscall (*)\n +#output: program stopped with signal 4 (*).\n +*/ +#include "readlink2.c" diff --git a/sim/testsuite/cris/c/readlink6.c b/sim/testsuite/cris/c/readlink6.c new file mode 100644 index 0000000..4bac20d --- /dev/null +++ b/sim/testsuite/cris/c/readlink6.c @@ -0,0 +1,5 @@ +/* Check that rare readlink calls don't cause the simulator to abort. +#notarget: cris*-*-elf +#dest: @exedir@/readlink6.c.x +*/ +#include "readlink2.c" diff --git a/sim/testsuite/cris/c/readlink7.c b/sim/testsuite/cris/c/readlink7.c new file mode 100644 index 0000000..9c2b3b7 --- /dev/null +++ b/sim/testsuite/cris/c/readlink7.c @@ -0,0 +1,6 @@ +/* Check that rare readlink calls don't cause the simulator to abort. +#notarget: cris*-*-elf +#simenv: env(-u\ PWD\ foo)=bar + FIXME: Need to unset PWD, but right now I won't bother tweaking the + generic parts of the testsuite machinery and instead abuse a flaw. */ +#include "readlink2.c" diff --git a/sim/testsuite/cris/c/readlink8.c b/sim/testsuite/cris/c/readlink8.c new file mode 100644 index 0000000..55f6fe8 --- /dev/null +++ b/sim/testsuite/cris/c/readlink8.c @@ -0,0 +1,8 @@ +/* Check that rare readlink calls don't cause the simulator to abort. +#notarget: cris*-*-elf +#sim: --sysroot=@exedir@ +#simenv: env(-u\ PWD\ foo)=bar + FIXME: Need to unset PWD, but right now I won't bother tweaking the + generic parts of the testsuite machinery and instead abuse a flaw. */ +#define SYSROOTED 1 +#include "readlink2.c" diff --git a/sim/testsuite/cris/c/readlink9.c b/sim/testsuite/cris/c/readlink9.c new file mode 100644 index 0000000..2788054 --- /dev/null +++ b/sim/testsuite/cris/c/readlink9.c @@ -0,0 +1,23 @@ +/* Check that odd cases of readlink work. +#notarget: cris*-*-elf +#cc: additional_flags=-DX="@exedir@" +*/ + +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + /* We assume that "sim/testsuite" isn't renamed to anything that + together with "/" is shorter than 7 characters. */ + char buf[7]; + + if (readlink("/proc/42/exe", buf, sizeof (buf)) != sizeof (buf) + || strncmp (buf, X, sizeof (buf)) != 0) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/rename2.c b/sim/testsuite/cris/c/rename2.c new file mode 100644 index 0000000..39387d1 --- /dev/null +++ b/sim/testsuite/cris/c/rename2.c @@ -0,0 +1,38 @@ +/* Test some execution paths for error cases. +#cc: additional_flags=-Wl,--section-start=.startup=0x8000 + The linker option is for sake of newlib, where the default program + layout starts at address 0. We need to change the layout so + there's no memory at 0, as all sim error checking is "lazy", + depending on lack of memory mapping. */ + +#include +#include +#include + +void err (const char *s) +{ + perror (s); + abort (); +} + +int main (int argc, char *argv[]) +{ + /* Avoid getting files with random characters due to errors + elsewhere. */ + if (argc != 1 + || (argv[0][0] != '.' && argv[0][0] != '/' && argv[0][0] != 'r')) + abort (); + + if (rename (argv[0], NULL) != -1 + || errno != EFAULT) + err ("rename 1 "); + + errno = 0; + + if (rename (NULL, argv[0]) != -1 + || errno != EFAULT) + err ("rename 2"); + + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/cris/c/rtsigprocmask1.c b/sim/testsuite/cris/c/rtsigprocmask1.c new file mode 100644 index 0000000..b76c338 --- /dev/null +++ b/sim/testsuite/cris/c/rtsigprocmask1.c @@ -0,0 +1,51 @@ +/* Compiler options: +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Unimplemented rt_sigprocmask syscall (0x3, 0x0, 0x3dff*\n +#output: program stopped with signal 4 (*).\n + + Testing a signal handler corner case. */ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int +main (void) +{ + int retcode; + pthread_t th_a; + void *retval; + sigset_t sigs; + + if (sigemptyset (&sigs) != 0) + abort (); + + retcode = pthread_create (&th_a, NULL, process, NULL); + if (retcode != 0) + abort (); + + /* An invalid parameter 1 should cause this to halt the simulator. */ + retcode + = pthread_sigmask (SIG_BLOCK + SIG_UNBLOCK + SIG_SETMASK, NULL, &sigs); + /* Direct return of the error number; i.e. not using -1 and errno, + is the actual documented behavior. */ + if (retcode == ENOSYS) + printf ("ENOSYS\n"); + + printf ("xyzzy\n"); + return 0; +} diff --git a/sim/testsuite/cris/c/rtsigprocmask2.c b/sim/testsuite/cris/c/rtsigprocmask2.c new file mode 100644 index 0000000..5026908 --- /dev/null +++ b/sim/testsuite/cris/c/rtsigprocmask2.c @@ -0,0 +1,9 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "rtsigprocmask1.c" diff --git a/sim/testsuite/cris/c/rtsigsuspend1.c b/sim/testsuite/cris/c/rtsigsuspend1.c new file mode 100644 index 0000000..66ca795 --- /dev/null +++ b/sim/testsuite/cris/c/rtsigsuspend1.c @@ -0,0 +1,21 @@ +/* Test that TRT happens for invalid rt_sigsuspend calls. Single-thread. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented rt_sigsuspend syscall arguments (0x1, 0x2)\n +#output: program stopped with signal 4 (*).\n +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + int err = syscall (SYS_rt_sigsuspend, 1, 2); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/rtsigsuspend2.c b/sim/testsuite/cris/c/rtsigsuspend2.c new file mode 100644 index 0000000..9ce165d --- /dev/null +++ b/sim/testsuite/cris/c/rtsigsuspend2.c @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "rtsigsuspend1.c" diff --git a/sim/testsuite/cris/c/sched1.c b/sim/testsuite/cris/c/sched1.c new file mode 100644 index 0000000..1b778f4 --- /dev/null +++ b/sim/testsuite/cris/c/sched1.c @@ -0,0 +1,16 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + if (sched_getscheduler (getpid ()) != SCHED_OTHER) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sched2.c b/sim/testsuite/cris/c/sched2.c new file mode 100644 index 0000000..f40a19a --- /dev/null +++ b/sim/testsuite/cris/c/sched2.c @@ -0,0 +1,20 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + struct sched_param sb; + memset (&sb, -1, sizeof sb); + if (sched_getparam (getpid (), &sb) != 0 + || sb.sched_priority != 0) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sched3.c b/sim/testsuite/cris/c/sched3.c new file mode 100644 index 0000000..2909a4b --- /dev/null +++ b/sim/testsuite/cris/c/sched3.c @@ -0,0 +1,25 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + struct sched_param sb; + sb.sched_priority = 0; + if (sched_setscheduler (getpid (), SCHED_OTHER, &sb) != 0 + || sb.sched_priority != 0) + abort (); + sb.sched_priority = 5; + if (sched_setscheduler (getpid (), SCHED_OTHER, &sb) != -1 + || errno != EINVAL + || sb.sched_priority != 5) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sched4.c b/sim/testsuite/cris/c/sched4.c new file mode 100644 index 0000000..df372f2 --- /dev/null +++ b/sim/testsuite/cris/c/sched4.c @@ -0,0 +1,25 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + struct sched_param sb; + sb.sched_priority = 0; + if (sched_setparam (getpid (), &sb) != 0 + || sb.sched_priority != 0) + abort (); + sb.sched_priority = 5; + if (sched_setparam (getpid (), &sb) == 0 + || errno != EINVAL + || sb.sched_priority != 5) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sched5.c b/sim/testsuite/cris/c/sched5.c new file mode 100644 index 0000000..ddfe14d --- /dev/null +++ b/sim/testsuite/cris/c/sched5.c @@ -0,0 +1,19 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +int main (void) +{ + int Min = sched_get_priority_min (SCHED_OTHER); + int Max = sched_get_priority_max (SCHED_OTHER); + if (Min != 0 || Max != 0) + { + fprintf (stderr, "min: %d, max: %d\n", Min, Max); + abort (); + } + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sched6.c b/sim/testsuite/cris/c/sched6.c new file mode 100644 index 0000000..d5adedc --- /dev/null +++ b/sim/testsuite/cris/c/sched6.c @@ -0,0 +1,15 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +int main (void) +{ + if (sched_yield () != 0) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sched7.c b/sim/testsuite/cris/c/sched7.c new file mode 100644 index 0000000..35d006b --- /dev/null +++ b/sim/testsuite/cris/c/sched7.c @@ -0,0 +1,17 @@ +/* Check corner error case: specifying invalid PID. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + if (sched_getscheduler (99) != -1 + || errno != ESRCH) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sched8.c b/sim/testsuite/cris/c/sched8.c new file mode 100644 index 0000000..cd3e06e --- /dev/null +++ b/sim/testsuite/cris/c/sched8.c @@ -0,0 +1,19 @@ +/* Check corner error case: specifying invalid PID. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include +#include + +int main (void) +{ + struct sched_param sb; + memset (&sb, -1, sizeof sb); + if (sched_getparam (99, &sb) != -1 + || errno != ESRCH) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sched9.c b/sim/testsuite/cris/c/sched9.c new file mode 100644 index 0000000..8499e43 --- /dev/null +++ b/sim/testsuite/cris/c/sched9.c @@ -0,0 +1,24 @@ +/* Check corner error case: specifying invalid scheduling policy. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + if (sched_get_priority_min (-1) != -1 + || errno != EINVAL) + abort (); + + errno = 0; + + if (sched_get_priority_max (-1) != -1 + || errno != EINVAL) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/seek1.c b/sim/testsuite/cris/c/seek1.c new file mode 100644 index 0000000..b22c8f9 --- /dev/null +++ b/sim/testsuite/cris/c/seek1.c @@ -0,0 +1,47 @@ +/* Check that basic (ll|f)seek sim functionality works. Also uses basic + file open/write functionality. */ +#include +#include +#include + +int +main (void) +{ + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt[] + = "A random line of text, used to test correct read, write and seek.\n"; + char buf[sizeof tsttxt] = ""; + + f = fopen (fname, "w"); + if (f == NULL + || fwrite (tsttxt, 1, strlen (tsttxt), f) != strlen (tsttxt) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + /* Using "rb" to make this test similar to the use in genconf.c in + GhostScript. */ + f = fopen (fname, "rb"); + if (f == NULL + || fseek (f, 0L, SEEK_END) != 0 + || ftell (f) != strlen (tsttxt)) + { + printf ("fail\n"); + exit (1); + } + + rewind (f); + if (fread (buf, 1, strlen (tsttxt), f) != strlen (tsttxt) + || strcmp (buf, tsttxt) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/seek2.c b/sim/testsuite/cris/c/seek2.c new file mode 100644 index 0000000..9c24dfb --- /dev/null +++ b/sim/testsuite/cris/c/seek2.c @@ -0,0 +1,4 @@ +/* Simulator options: +#sim: --sysroot=@exedir@/ +*/ +#include "seek1.c" diff --git a/sim/testsuite/cris/c/seek3.c b/sim/testsuite/cris/c/seek3.c new file mode 100644 index 0000000..5e7b578 --- /dev/null +++ b/sim/testsuite/cris/c/seek3.c @@ -0,0 +1,49 @@ +/* Check for a sim bug, whereby the position was always unsigned + (truncation instead of sign-extension for 64-bit hosts). */ +#include +#include +#include +#include +#include +#include +#include + +int +main (void) +{ + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt[] + = "A random line of text, used to test correct read, write and seek.\n"; + char buf[sizeof tsttxt] = ""; + const char correct[] = "correct"; + char buf2[sizeof correct] = {0}; + int fd; + + f = fopen (fname, "wb"); + if (f == NULL + || fwrite (tsttxt, 1, strlen (tsttxt), f) != strlen (tsttxt) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + /* We have to use file-descriptor calls instead of stream calls to + provoke the bug (for stream calls, the lseek call is canonicalized + to use SEEK_SET). */ + fd = open (fname, O_RDONLY); + if (fd < 0 + || read (fd, buf, strlen (tsttxt)) != strlen (tsttxt) + || strcmp (buf, tsttxt) != 0 + || lseek (fd, -30L, SEEK_CUR) != 36 + || read (fd, buf2, strlen (correct)) != strlen (correct) + || strcmp (buf2, correct) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/seek4.c b/sim/testsuite/cris/c/seek4.c new file mode 100644 index 0000000..16f3bb0 --- /dev/null +++ b/sim/testsuite/cris/c/seek4.c @@ -0,0 +1,44 @@ +/* Check for a sim bug, whereby an invalid seek (to a negative offset) + did not return an error. */ +#include +#include +#include +#include +#include +#include +#include +#include + +int +main (void) +{ + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt[] + = "A random line of text, used to test correct read, write and seek.\n"; + char buf[sizeof tsttxt] = ""; + int fd; + + f = fopen (fname, "wb"); + if (f == NULL + || fwrite (tsttxt, 1, strlen (tsttxt), f) != strlen (tsttxt) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + fd = open (fname, O_RDONLY); + if (fd < 0 + || lseek (fd, -1L, SEEK_CUR) != -1 + || errno != EINVAL + || read (fd, buf, strlen (tsttxt)) != strlen (tsttxt) + || strcmp (buf, tsttxt) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/setrlimit1.c b/sim/testsuite/cris/c/setrlimit1.c new file mode 100644 index 0000000..747f16c --- /dev/null +++ b/sim/testsuite/cris/c/setrlimit1.c @@ -0,0 +1,22 @@ +/* Check corner error case: specifying unimplemented resource. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include +#include +#include +#include + +int main (void) +{ + struct rlimit lim; + memset (&lim, 0, sizeof lim); + + if (setrlimit (RLIMIT_NPROC, &lim) != -1 + || errno != EINVAL) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/settls1.c b/sim/testsuite/cris/c/settls1.c new file mode 100644 index 0000000..bd55aa1 --- /dev/null +++ b/sim/testsuite/cris/c/settls1.c @@ -0,0 +1,49 @@ +/* Check that the syscall set_thread_area is supported and does the right thing. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +#ifndef SYS_set_thread_area +#define SYS_set_thread_area 243 +#endif + +int main (void) +{ + int ret; + + /* Check the error check that the low 8 bits must be 0. */ + ret = syscall (SYS_set_thread_area, 0xfeeb1ff0); + if (ret != -1 || errno != EINVAL) + { + perror ("tls1"); + abort (); + } + + ret = syscall (SYS_set_thread_area, 0xcafebe00); + if (ret != 0) + { + perror ("tls2"); + abort (); + } + + /* Check that we got the right result. */ +#ifdef __arch_v32 + asm ("move $pid,%0\n\tclear.b %0" : "=rm" (ret)); +#else + asm ("move $brp,%0" : "=rm" (ret)); +#endif + + if (ret != 0xcafebe00) + { + perror ("tls2"); + abort (); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sig1.c b/sim/testsuite/cris/c/sig1.c new file mode 100644 index 0000000..55499b7 --- /dev/null +++ b/sim/testsuite/cris/c/sig1.c @@ -0,0 +1,20 @@ +#include +#include +#include + +void +leave (int n) +{ + exit (0); +} + +int +main (void) +{ + /* Check that the sigaction syscall (for signal) is interpreted, though + possibly ignored. */ + signal (SIGFPE, leave); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sig10.c b/sim/testsuite/cris/c/sig10.c new file mode 100644 index 0000000..ef54832 --- /dev/null +++ b/sim/testsuite/cris/c/sig10.c @@ -0,0 +1,33 @@ +/* Check that TRT happens when trying to IGN an non-ignorable signal, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Exiting pid 42 due to signal 9\n +#output: program stopped with signal 4 (*).\n +*/ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + signal (SIGKILL, SIG_IGN); + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + kill (getpid (), SIGKILL); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sig11.c b/sim/testsuite/cris/c/sig11.c new file mode 100644 index 0000000..9c8aad7 --- /dev/null +++ b/sim/testsuite/cris/c/sig11.c @@ -0,0 +1,32 @@ +/* Check that TRT happens when getting a non-standard (realtime) signal, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Unimplemented signal: 77\n +#output: program stopped with signal 4 (*).\n +*/ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + kill (getpid (), 77); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sig12.c b/sim/testsuite/cris/c/sig12.c new file mode 100644 index 0000000..5a2e65f --- /dev/null +++ b/sim/testsuite/cris/c/sig12.c @@ -0,0 +1,38 @@ +/* Check that TRT happens for a signal sent to a non-existent process/thread, more than one thread. +#cc: additional_flags=-pthread +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + int i; + for (i = 0; i < 100; i++) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + int retcode; + void *retval; + + if (pthread_create (&th_a, NULL, process, (void *) "a") != 0) + abort (); + if (kill (getpid () - 1, SIGBUS) != -1 + || errno != ESRCH + || pthread_join (th_a, &retval) != 0) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sig13.c b/sim/testsuite/cris/c/sig13.c new file mode 100644 index 0000000..4d71752 --- /dev/null +++ b/sim/testsuite/cris/c/sig13.c @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "sig7.c" diff --git a/sim/testsuite/cris/c/sig2.c b/sim/testsuite/cris/c/sig2.c new file mode 100644 index 0000000..65596ef --- /dev/null +++ b/sim/testsuite/cris/c/sig2.c @@ -0,0 +1,32 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +/* Like sig1.c, but using sigaction. */ + +void +leave (int n, siginfo_t *info, void *x) +{ + abort (); +} + +int +main (void) +{ + struct sigaction sa; + sa.sa_sigaction = leave; + sa.sa_flags = SA_RESTART | SA_SIGINFO; + sigemptyset (&sa.sa_mask); + + /* Check that the sigaction syscall (for signal) is interpreted, though + possibly ignored. */ + if (sigaction (SIGFPE, &sa, NULL) != 0) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sig3.c b/sim/testsuite/cris/c/sig3.c new file mode 100644 index 0000000..91de227 --- /dev/null +++ b/sim/testsuite/cris/c/sig3.c @@ -0,0 +1,13 @@ +/* Check that TRT happens at an abort (3) call, single thread. +#xerror: +#output: program stopped with signal 6 (*).\n +*/ + +#include +#include +int main (void) +{ + abort (); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sig4.c b/sim/testsuite/cris/c/sig4.c new file mode 100644 index 0000000..57491f8 --- /dev/null +++ b/sim/testsuite/cris/c/sig4.c @@ -0,0 +1,30 @@ +/* Check that TRT happens at an abort (3) call, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Exiting pid 42 due to signal 6\n +#output: program stopped with signal 6 (*).\n +*/ + +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + abort (); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sig5.c b/sim/testsuite/cris/c/sig5.c new file mode 100644 index 0000000..f80da2b --- /dev/null +++ b/sim/testsuite/cris/c/sig5.c @@ -0,0 +1,18 @@ +/* Check that TRT happens for an uncaught non-abort signal, single thread. +#xerror: +#output: Unimplemented signal: 7\n +#output: program stopped with signal 4 (*).\n +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + kill (getpid (), SIGBUS); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sig6.c b/sim/testsuite/cris/c/sig6.c new file mode 100644 index 0000000..a1f5720 --- /dev/null +++ b/sim/testsuite/cris/c/sig6.c @@ -0,0 +1,32 @@ +/* Check that TRT happens at an non-abort non-caught signal, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Exiting pid 42 due to signal 7\n +#output: program stopped with signal 4 (*).\n +*/ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + kill (getpid (), SIGBUS); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sig7.c b/sim/testsuite/cris/c/sig7.c new file mode 100644 index 0000000..b04f7c8 --- /dev/null +++ b/sim/testsuite/cris/c/sig7.c @@ -0,0 +1,27 @@ +/* Check unsupported case of sigaction syscall. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented rt_sigaction syscall (0x8, 0x3df*\n +#output: program stopped with signal 4 (*).\n +*/ +#include +#include +#include +#include + +int +main (void) +{ + struct sigaction sa; + int err; + sa.sa_sigaction = NULL; + sa.sa_flags = SA_RESTART | SA_SIGINFO; + sigemptyset (&sa.sa_mask); + + err = sigaction (SIGFPE, &sa, NULL); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sig8.c b/sim/testsuite/cris/c/sig8.c new file mode 100644 index 0000000..ea2d7f5 --- /dev/null +++ b/sim/testsuite/cris/c/sig8.c @@ -0,0 +1,21 @@ +/* Check that TRT happens for an ignored catchable signal, single thread. +#xerror: +#output: Unimplemented signal: 14\n +#output: program stopped with signal 4 (*).\n + + Sure, it'd probably be better to support signals in single-thread too, + but that's on an as-need basis, and I don't have a need for it yet. */ + +#include +#include +#include +#include +#include + +int main (void) +{ + signal (SIGALRM, SIG_IGN); + kill (getpid (), SIGALRM); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sig9.c b/sim/testsuite/cris/c/sig9.c new file mode 100644 index 0000000..c86681b --- /dev/null +++ b/sim/testsuite/cris/c/sig9.c @@ -0,0 +1,36 @@ +/* Check that TRT happens at an non-abort ignored signal, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +*/ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + int i; + for (i = 0; i < 100; i++) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + int retcode; + void *retval; + signal (SIGALRM, SIG_IGN); + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + kill (getpid (), SIGALRM); + retcode = pthread_join (th_a, &retval); + if (retcode != 0 || retval != NULL) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sigreturn1.c b/sim/testsuite/cris/c/sigreturn1.c new file mode 100644 index 0000000..40fc852 --- /dev/null +++ b/sim/testsuite/cris/c/sigreturn1.c @@ -0,0 +1,21 @@ +/* Test that TRT happens for spurious sigreturn calls. Single-thread. +#notarget: cris*-*-elf +#xerror: +#output: Invalid sigreturn syscall: no signal handler active (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: program stopped with signal 4 (*).\n +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + int err = syscall (SYS_sigreturn, 1, 2, 3, 4, 5, 6); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sigreturn2.c b/sim/testsuite/cris/c/sigreturn2.c new file mode 100644 index 0000000..3848b5f --- /dev/null +++ b/sim/testsuite/cris/c/sigreturn2.c @@ -0,0 +1,38 @@ +/* Check that TRT happens for spurious sigreturn calls. Multiple threads. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Invalid sigreturn syscall: no signal handler active (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: program stopped with signal 4 (*).\n +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + { + int err = syscall (SYS_sigreturn, 1, 2, 3, 4, 5, 6); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + } + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sigreturn3.c b/sim/testsuite/cris/c/sigreturn3.c new file mode 100644 index 0000000..f5ed90f --- /dev/null +++ b/sim/testsuite/cris/c/sigreturn3.c @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "sigreturn1.c" diff --git a/sim/testsuite/cris/c/sigreturn4.c b/sim/testsuite/cris/c/sigreturn4.c new file mode 100644 index 0000000..456e312 --- /dev/null +++ b/sim/testsuite/cris/c/sigreturn4.c @@ -0,0 +1,9 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "sigreturn2.c" diff --git a/sim/testsuite/cris/c/sjlj.c b/sim/testsuite/cris/c/sjlj.c new file mode 100644 index 0000000..141faf6 --- /dev/null +++ b/sim/testsuite/cris/c/sjlj.c @@ -0,0 +1,34 @@ +/* Check that setjmp and longjmp stand a chance to work; that the used machine + primitives work in the simulator. */ + +#include +#include +#include + +extern void f (void); + +int ok = 0; +jmp_buf b; + +int +main () +{ + int ret = setjmp (b); + + if (ret == 42) + ok = 100; + else if (ret == 0) + f (); + + if (ok == 100) + printf ("pass\n"); + else + printf ("fail\n"); + exit (0); +} + +void +f (void) +{ + longjmp (b, 42); +} diff --git a/sim/testsuite/cris/c/sock1.c b/sim/testsuite/cris/c/sock1.c new file mode 100644 index 0000000..e59f673 --- /dev/null +++ b/sim/testsuite/cris/c/sock1.c @@ -0,0 +1,32 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +/* Check that socketcall is suitably stubbed. */ + +int main (void) +{ + int ret = socket (PF_INET, SOCK_STREAM, IPPROTO_TCP); + + if (ret != -1) + { + fprintf (stderr, "sock: %d\n", ret); + abort (); + } + + if (errno != ENOSYS) + { + perror ("unexpected"); + abort (); + } + + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/cris/c/stat1.c b/sim/testsuite/cris/c/stat1.c new file mode 100644 index 0000000..b5d14a3 --- /dev/null +++ b/sim/testsuite/cris/c/stat1.c @@ -0,0 +1,16 @@ +#include +#include +#include +#include +#include + +int main (void) +{ + struct stat buf; + + if (stat (".", &buf) != 0 + || !S_ISDIR (buf.st_mode)) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/stat2.c b/sim/testsuite/cris/c/stat2.c new file mode 100644 index 0000000..78c5c44 --- /dev/null +++ b/sim/testsuite/cris/c/stat2.c @@ -0,0 +1,20 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + struct stat buf; + + if (lstat (".", &buf) != 0 + || !S_ISDIR (buf.st_mode)) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/stat3.c b/sim/testsuite/cris/c/stat3.c new file mode 100644 index 0000000..a248ec0 --- /dev/null +++ b/sim/testsuite/cris/c/stat3.c @@ -0,0 +1,26 @@ +/* Simulator options: +#sim: --sysroot=@exedir@ +*/ +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + char path[1024] = "/"; + struct stat buf; + + strcat (path, argv[0]); + if (stat (".", &buf) != 0 + || !S_ISDIR (buf.st_mode)) + abort (); + if (stat (path, &buf) != 0 + || !S_ISREG (buf.st_mode)) + abort (); + printf ("pass\n"); + exit (0); +} + diff --git a/sim/testsuite/cris/c/stat4.c b/sim/testsuite/cris/c/stat4.c new file mode 100644 index 0000000..62415a3 --- /dev/null +++ b/sim/testsuite/cris/c/stat4.c @@ -0,0 +1,28 @@ +/* Simulator options: +#notarget: cris*-*-elf +#sim: --sysroot=@exedir@ +*/ + +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + char path[1024] = "/"; + struct stat buf; + + strcat (path, argv[0]); + if (lstat (".", &buf) != 0 + || !S_ISDIR (buf.st_mode)) + abort (); + if (lstat (path, &buf) != 0 + || !S_ISREG (buf.st_mode)) + abort (); + printf ("pass\n"); + exit (0); +} + diff --git a/sim/testsuite/cris/c/stat5.c b/sim/testsuite/cris/c/stat5.c new file mode 100644 index 0000000..41ab493 --- /dev/null +++ b/sim/testsuite/cris/c/stat5.c @@ -0,0 +1,20 @@ +/* Check that lstat:ing an nonexistent file works as expected. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + struct stat buf; + + if (lstat ("nonexistent", &buf) == 0 || errno != ENOENT) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/stat7.c b/sim/testsuite/cris/c/stat7.c new file mode 100644 index 0000000..cbd5282 --- /dev/null +++ b/sim/testsuite/cris/c/stat7.c @@ -0,0 +1,26 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + struct stat buf; + + /* From Linux, we get EFAULT. The simulator sends us EINVAL. */ + if (lstat (NULL, &buf) != -1 + || (errno != EINVAL && errno != EFAULT)) + { + perror ("lstat 1"); + abort (); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/stat8.c b/sim/testsuite/cris/c/stat8.c new file mode 100644 index 0000000..c7eb49f --- /dev/null +++ b/sim/testsuite/cris/c/stat8.c @@ -0,0 +1,26 @@ +/* For this test, we need to do the lstat syscall directly, or else + glibc gets a SEGV. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + int ret; + + /* From Linux, we get EFAULT. The simulator sends us EINVAL. */ + ret = syscall (SYS_lstat64, ".", NULL); + if (ret != -1 || (errno != EINVAL && errno != EFAULT)) + { + perror ("lstat"); + abort (); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/syscall1.c b/sim/testsuite/cris/c/syscall1.c new file mode 100644 index 0000000..84aacb6 --- /dev/null +++ b/sim/testsuite/cris/c/syscall1.c @@ -0,0 +1,22 @@ +/* Test unknown-syscall output. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented syscall: 166 (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: program stopped with signal 4 (*).\n +*/ + +#include +#include +#include +#include + +int main (void) +{ + /* The number 166 is chosen because there's a gap for that number in + the CRIS asm/unistd.h. */ + int err = syscall (166, 1, 2, 3, 4, 5, 6); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/syscall2.c b/sim/testsuite/cris/c/syscall2.c new file mode 100644 index 0000000..b4dbead --- /dev/null +++ b/sim/testsuite/cris/c/syscall2.c @@ -0,0 +1,23 @@ +/* Test unknown-syscall output. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented syscall: 0 (0x3, 0x2, 0x1, 0x4, 0x6, 0x5)\n +#output: program stopped with signal 4 (*).\n +*/ + +#include +#include +#include +#include + +int main (void) +{ + int err; + + /* Check special case of number 0 syscall. */ + err = syscall (0, 3, 2, 1, 4, 6, 5); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/syscall3.c b/sim/testsuite/cris/c/syscall3.c new file mode 100644 index 0000000..f4d02eb --- /dev/null +++ b/sim/testsuite/cris/c/syscall3.c @@ -0,0 +1,9 @@ +/* As the included file, just actually specifying the default. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=stop +#xerror: +#output: Unimplemented syscall: 166 (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: program stopped with signal 4 (*).\n +*/ + +#include "syscall1.c" diff --git a/sim/testsuite/cris/c/syscall4.c b/sim/testsuite/cris/c/syscall4.c new file mode 100644 index 0000000..ba01cfd --- /dev/null +++ b/sim/testsuite/cris/c/syscall4.c @@ -0,0 +1,9 @@ +/* As the included file, just actually specifying the default. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=stop +#xerror: +#output: Unimplemented syscall: 0 (0x3, 0x2, 0x1, 0x4, 0x6, 0x5)\n +#output: program stopped with signal 4 (*).\n +*/ + +#include "syscall2.c" diff --git a/sim/testsuite/cris/c/syscall5.c b/sim/testsuite/cris/c/syscall5.c new file mode 100644 index 0000000..2eac900 --- /dev/null +++ b/sim/testsuite/cris/c/syscall5.c @@ -0,0 +1,9 @@ +/* As the included file, but specifying ENOSYS with message. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys +#output: Unimplemented syscall: 166 (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "syscall1.c" diff --git a/sim/testsuite/cris/c/syscall6.c b/sim/testsuite/cris/c/syscall6.c new file mode 100644 index 0000000..91375df --- /dev/null +++ b/sim/testsuite/cris/c/syscall6.c @@ -0,0 +1,9 @@ +/* As the included file, but specifying ENOSYS with message. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys +#output: Unimplemented syscall: 0 (0x3, 0x2, 0x1, 0x4, 0x6, 0x5)\n +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "syscall2.c" diff --git a/sim/testsuite/cris/c/syscall7.c b/sim/testsuite/cris/c/syscall7.c new file mode 100644 index 0000000..0f1daf1 --- /dev/null +++ b/sim/testsuite/cris/c/syscall7.c @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "syscall1.c" diff --git a/sim/testsuite/cris/c/syscall8.c b/sim/testsuite/cris/c/syscall8.c new file mode 100644 index 0000000..c579436 --- /dev/null +++ b/sim/testsuite/cris/c/syscall8.c @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "syscall2.c" diff --git a/sim/testsuite/cris/c/sysctl1.c b/sim/testsuite/cris/c/sysctl1.c new file mode 100644 index 0000000..6646fac --- /dev/null +++ b/sim/testsuite/cris/c/sysctl1.c @@ -0,0 +1,38 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +/* I can't seem to include the right things, so we do it brute force. */ +int main (void) +{ + static int sysctl_args[] = { 1, 4 }; + size_t x = 8; + + struct __sysctl_args { + int *name; + int nlen; + void *oldval; + size_t *oldlenp; + void *newval; + size_t newlen; + unsigned long __unused[4]; + } scargs + = + { + sysctl_args, + sizeof (sysctl_args) / sizeof (sysctl_args[0]), + (void *) -1, &x, NULL, 0 + }; + + if (syscall (SYS__sysctl, &scargs) != -1 + || errno != EFAULT) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sysctl2.c b/sim/testsuite/cris/c/sysctl2.c new file mode 100644 index 0000000..f27c37c --- /dev/null +++ b/sim/testsuite/cris/c/sysctl2.c @@ -0,0 +1,41 @@ +/* Check error message for invalid sysctl call. +#xerror: +#output: Unimplemented _sysctl syscall *\n +#output: program stopped with signal 4 (*).\n +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + static int sysctl_args[] = { 99, 99 }; + size_t x = 8; + + struct __sysctl_args { + int *name; + int nlen; + void *oldval; + size_t *oldlenp; + void *newval; + size_t newlen; + unsigned long __unused[4]; + } scargs + = + { + sysctl_args, + sizeof (sysctl_args) / sizeof (sysctl_args[0]), + (void *) -1, &x, NULL, 0 + }; + + int err = syscall (SYS__sysctl, &scargs); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/sysctl3.c b/sim/testsuite/cris/c/sysctl3.c new file mode 100644 index 0000000..747e784 --- /dev/null +++ b/sim/testsuite/cris/c/sysctl3.c @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "sysctl2.c" diff --git a/sim/testsuite/cris/c/thread2.c b/sim/testsuite/cris/c/thread2.c new file mode 100644 index 0000000..c9ad2f9 --- /dev/null +++ b/sim/testsuite/cris/c/thread2.c @@ -0,0 +1,28 @@ +/* Compiler options: +#cc: additional_flags=-pthread +#notarget: cris*-*-elf + + A sanity check for syscalls resulting from + pthread_getschedparam and pthread_setschedparam. */ + +#include +#include +#include + +int main (void) +{ + struct sched_param param; + int policy; + + if (pthread_getschedparam (pthread_self (), &policy, ¶m) != 0 + || policy != SCHED_OTHER + || param.sched_priority != 0) + abort (); + + if (pthread_setschedparam (pthread_self (), SCHED_OTHER, ¶m) != 0 + || param.sched_priority != 0) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/thread3.c b/sim/testsuite/cris/c/thread3.c new file mode 100644 index 0000000..3b6945a --- /dev/null +++ b/sim/testsuite/cris/c/thread3.c @@ -0,0 +1,46 @@ +/* Compiler options: +#cc: additional_flags=-pthread +#notarget: cris*-*-elf + + To test sched_yield in the presencs of threads. Core from ex1.c. */ + +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + int i; + for (i = 0; i < 10; i++) + { + if (sched_yield () != 0) + abort (); + } + return NULL; +} + +int +main (void) +{ + int retcode; + pthread_t th_a, th_b; + void *retval; + + retcode = pthread_create (&th_a, NULL, process, (void *) "a"); + if (retcode != 0) + abort (); + retcode = pthread_create (&th_b, NULL, process, (void *) "b"); + if (retcode != 0) + abort (); + retcode = pthread_join (th_a, &retval); + if (retcode != 0) + abort (); + retcode = pthread_join (th_b, &retval); + if (retcode != 0) + abort (); + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/cris/c/thread4.c b/sim/testsuite/cris/c/thread4.c new file mode 100644 index 0000000..cfa2327 --- /dev/null +++ b/sim/testsuite/cris/c/thread4.c @@ -0,0 +1,50 @@ +/* Compiler options: +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#output: abb ok\n + + Testing a pthread corner case. Output will change with glibc + releases. */ + +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + int i; + + if (pthread_setcancelstate (PTHREAD_CANCEL_ENABLE, NULL) != 0) + abort (); + write (2, "a", 1); + for (i = 0; i < 10; i++) + { + sched_yield (); + pthread_testcancel (); + write (2, "b", 1); + } + return NULL; +} + +int +main (void) +{ + int retcode; + pthread_t th_a; + void *retval; + + retcode = pthread_create (&th_a, NULL, process, NULL); + sched_yield (); + sched_yield (); + sched_yield (); + sched_yield (); + retcode = pthread_cancel (th_a); + retcode = pthread_join (th_a, &retval); + if (retcode != 0) + abort (); + fprintf (stderr, " ok\n"); + return 0; +} diff --git a/sim/testsuite/cris/c/thread5.c b/sim/testsuite/cris/c/thread5.c new file mode 100644 index 0000000..494251f --- /dev/null +++ b/sim/testsuite/cris/c/thread5.c @@ -0,0 +1,77 @@ +/* Compiler options: +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#output: abbb ok\n + + Testing a signal handler corner case. */ + +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + write (2, "a", 1); + write (2, "b", 1); + write (2, "b", 1); + write (2, "b", 1); + return NULL; +} + +int ok = 0; +volatile int done = 0; + +void +sigusr1 (int signum) +{ + if (signum != SIGUSR1 || !ok) + abort (); + done = 1; +} + +int +main (void) +{ + int retcode; + pthread_t th_a; + void *retval; + sigset_t sigs; + + if (sigemptyset (&sigs) != 0) + abort (); + + retcode = pthread_create (&th_a, NULL, process, NULL); + if (retcode != 0) + abort (); + + if (signal (SIGUSR1, sigusr1) != SIG_DFL) + abort (); + if (pthread_sigmask (SIG_BLOCK, NULL, &sigs) != 0 + || sigaddset (&sigs, SIGUSR1) != 0 + || pthread_sigmask (SIG_BLOCK, &sigs, NULL) != 0) + abort (); + if (pthread_kill (pthread_self (), SIGUSR1) != 0 + || sched_yield () != 0 + || sched_yield () != 0 + || sched_yield () != 0) + abort (); + + ok = 1; + if (pthread_sigmask (SIG_UNBLOCK, NULL, &sigs) != 0 + || sigaddset (&sigs, SIGUSR1) != 0 + || pthread_sigmask (SIG_UNBLOCK, &sigs, NULL) != 0) + abort (); + + if (!done) + abort (); + + retcode = pthread_join (th_a, &retval); + if (retcode != 0) + abort (); + fprintf (stderr, " ok\n"); + return 0; +} diff --git a/sim/testsuite/cris/c/time1.c b/sim/testsuite/cris/c/time1.c new file mode 100644 index 0000000..3fcf0e1 --- /dev/null +++ b/sim/testsuite/cris/c/time1.c @@ -0,0 +1,46 @@ +/* Basic time functionality test: check that milliseconds are + incremented for each syscall (does not work on host). */ +#include +#include +#include +#include +#include + +void err (const char *s) +{ + perror (s); + abort (); +} + +int +main (void) +{ + struct timeval t_m = {0, 0}; + struct timezone t_z = {0, 0}; + struct timeval t_m1 = {0, 0}; + int i; + + if (gettimeofday (&t_m, &t_z) != 0) + err ("gettimeofday"); + + for (i = 1; i < 10000; i++) + if (gettimeofday (&t_m1, NULL) != 0) + err ("gettimeofday 1"); + else + if (t_m1.tv_sec * 1000000 + t_m1.tv_usec + != (t_m.tv_sec * 1000000 + t_m.tv_usec + i * 1000)) + { + fprintf (stderr, "t0 (%ld, %ld), i %d, t1 (%ld, %ld)\n", + t_m.tv_sec, t_m.tv_usec, i, t_m1.tv_sec, t_m1.tv_usec); + abort (); + } + + if (time (NULL) != t_m1.tv_sec) + { + fprintf (stderr, "time != gettod\n"); + abort (); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/time2.c b/sim/testsuite/cris/c/time2.c new file mode 100644 index 0000000..20b69b4 --- /dev/null +++ b/sim/testsuite/cris/c/time2.c @@ -0,0 +1,18 @@ +/* CB_SYS_time doesn't implement the Linux time syscall; the return + value isn't written to the argument. */ + +#include +#include +#include + +int +main (void) +{ + time_t x = (time_t) -1; + time_t t = time (&x); + + if (t == (time_t) -1 || t != x) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/truncate1.c b/sim/testsuite/cris/c/truncate1.c new file mode 100644 index 0000000..477dc3d --- /dev/null +++ b/sim/testsuite/cris/c/truncate1.c @@ -0,0 +1,49 @@ +/* Check that the truncate syscall works trivially. +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +#ifndef PREFIX +#define PREFIX +#endif +int +main (void) +{ + FILE *f; + const char fname[] = PREFIX "sk1test.dat"; + const char tsttxt1[] + = "This is the first and only line of this file.\n"; + const char tsttxt2[] = "Now there is a second line.\n"; + char buf[sizeof (tsttxt1) + sizeof (tsttxt2) - 1] = ""; + + f = fopen (fname, "w+"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + if (truncate (fname, strlen(tsttxt1) - 10) != 0) + { + perror ("truncate"); + exit (1); + } + + f = fopen (fname, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != strlen (tsttxt1) - 10 + || strncmp (buf, tsttxt1, strlen (tsttxt1) - 10) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/truncate2.c b/sim/testsuite/cris/c/truncate2.c new file mode 100644 index 0000000..a4c6470 --- /dev/null +++ b/sim/testsuite/cris/c/truncate2.c @@ -0,0 +1,6 @@ +/* +#sim: --sysroot=@exedir@ +#notarget: cris*-*-elf +*/ +#define PREFIX "/" +#include "truncate1.c" diff --git a/sim/testsuite/cris/c/ugetrlimit1.c b/sim/testsuite/cris/c/ugetrlimit1.c new file mode 100644 index 0000000..2a49b95 --- /dev/null +++ b/sim/testsuite/cris/c/ugetrlimit1.c @@ -0,0 +1,21 @@ +/* Check corner error case: specifying unimplemented resource. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + struct rlimit lim; + + if (getrlimit (RLIMIT_NPROC, &lim) != -1 + || errno != EINVAL) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/uname1.c b/sim/testsuite/cris/c/uname1.c new file mode 100644 index 0000000..83518d6 --- /dev/null +++ b/sim/testsuite/cris/c/uname1.c @@ -0,0 +1,21 @@ +/* Check that the right machine name appears in the uname result. +#notarget: *-*-elf +*/ +#include +#include +#include +int main (void) +{ + struct utsname buf; + if (uname (&buf) != 0 + || strcmp (buf.machine, +#ifdef __arch_v32 + "crisv32" +#else + "cris" +#endif + ) != 0) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/cris/c/writev1.c b/sim/testsuite/cris/c/writev1.c new file mode 100644 index 0000000..fad5b7f --- /dev/null +++ b/sim/testsuite/cris/c/writev1.c @@ -0,0 +1,25 @@ +/* Trivial test of writev. +#notarget: cris*-*-elf +#output: abcdefghijklmn\npass\n +*/ +#include +#include +#include + +#define X(x) {x, sizeof (x) -1} +struct iovec v[] = { + X("a"), + X("bcd"), + X("efghi"), + X("j"), + X("klmn\n"), +}; + +int main (void) +{ + if (writev (1, v, sizeof v / sizeof (v[0])) != 15) + abort (); + + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/cris/c/writev2.c b/sim/testsuite/cris/c/writev2.c new file mode 100644 index 0000000..5cb92b6 --- /dev/null +++ b/sim/testsuite/cris/c/writev2.c @@ -0,0 +1,28 @@ +/* Trivial test of failing writev: invalid file descriptor. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include + +#define X(x) {x, sizeof (x) -1} +struct iovec v[] = { + X("a"), + X("bcd"), + X("efghi"), + X("j"), + X("klmn\n"), +}; + +int main (void) +{ + if (writev (99, v, sizeof v / sizeof (v[0])) != -1 + /* The simulator write gives EINVAL instead of EBADF; let's + cope. */ + || (errno != EBADF && errno != EINVAL)) + abort (); + + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/cris/hw/rv-n-cris/host1.ms b/sim/testsuite/cris/hw/rv-n-cris/host1.ms new file mode 100644 index 0000000..c41f51f --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/host1.ms @@ -0,0 +1,8 @@ +#mach: crisv32 +#sim(crisv32): --hw-device "/rv/host localhost" + +# Check that we trivially resolve a hostname. + +#r @,@srcdir@/trivial4.r + + .include "trivial4.ms" diff --git a/sim/testsuite/cris/hw/rv-n-cris/irq1.ms b/sim/testsuite/cris/hw/rv-n-cris/irq1.ms new file mode 100644 index 0000000..f3e6f2e --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/irq1.ms @@ -0,0 +1,69 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0x4\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543211\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: := 0xeeff4455\n +#output: pass\n + +# Trivial test of interrupts. +# Locations of IRQ notifiers above depend on when the simulator is +# polled; adjustments may be needed (after checking that no poll is +# gone due to a bug!) + +#r W, +#r r,a8832,abcdef01 +#r I,4 +#r r,a8836,76543210 +#r r,a8836,76543211 +#r I,0 +#r r,a8830,eeff4455 + + .lcomm dummy,4 + + .include "testutils.inc" + start + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + test_h_mem 0xabcdef01 0xd0000032 + nop + nop + test_h_mem 0x76543210 0xd0000036 + ei + test_h_mem 0,dummy +wouldreturnhere: + nop +killme: + fail + +returnhere: + test_h_mem 0x76543211 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + pass + +irq0x33: + .if ..asm.arch.cris.v32 + test_h_dr wouldreturnhere,$erp + move returnhere,$erp + rete + rfe + .else + move $dccr,$r0 + test_h_dr wouldreturnhere,$irp + move returnhere,$irp + reti + move $r0,$dccr + .endif + + singlevec irqvec1,0x33,irq0x33 diff --git a/sim/testsuite/cris/hw/rv-n-cris/irq2.ms b/sim/testsuite/cris/hw/rv-n-cris/irq2.ms new file mode 100644 index 0000000..19709e4 --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/irq2.ms @@ -0,0 +1,44 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/rv/intmultiple 0xaa" +#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/rv/intmultiple 0xaa" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0xaa\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: := 0xeeff4455\n +#output: pass\n + +# Primarily to test multiple-int-bits set in dv-rv.c. + +#r W, +#r r,a8832,abcdef01 +#r I,6 +#r r,a8836,76543210 +#r I,0 +#r r,a8830,eeff4455 + + .lcomm dummy,4 + + .include "testutils.inc" + start + test_h_mem 0xabcdef01 0xd0000032 + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + ei + test_h_mem 0,dummy +killme: + fail + +irq0xea: + test_h_mem 0x76543210 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + pass + + singlevec irqvec1,0xea,irq0xea diff --git a/sim/testsuite/cris/hw/rv-n-cris/irq3.ms b/sim/testsuite/cris/hw/rv-n-cris/irq3.ms new file mode 100644 index 0000000..d96b6f5 --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/irq3.ms @@ -0,0 +1,46 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/rv/intmultiple 0xaa" +#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/rv/intmultiple 0xaa" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0xaa\n +#output: /rv: IRQ 0xaa\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: := 0xeeff4455\n +#output: pass\n + +# Much like irq2.ms, but modified to check same-int-port-value-twice. + +#r W, +#r r,a8832,abcdef01 +#r I,6 +#r I,6 +#r r,a8836,76543210 +#r I,0 +#r r,a8830,eeff4455 + + .lcomm dummy,4 + + .include "testutils.inc" + start + test_h_mem 0xabcdef01 0xd0000032 + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + ei + test_h_mem 0,dummy +killme: + fail + +irq0xea: + test_h_mem 0x76543210 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + pass + + singlevec irqvec1,0xea,irq0xea diff --git a/sim/testsuite/cris/hw/rv-n-cris/irq4.ms b/sim/testsuite/cris/hw/rv-n-cris/irq4.ms new file mode 100644 index 0000000..9e16b5c --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/irq4.ms @@ -0,0 +1,46 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int ignore_previous" +#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int ignore_previous" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0x4\n +#output: /rv: IRQ 0x8\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: := 0xeeff4455\n +#output: pass\n + +# Much like irq3.ms, but modified to test multiple-int ignore_previous. + +#r W, +#r r,a8832,abcdef01 +#r I,4 +#r I,8 +#r r,a8836,76543210 +#r I,0 +#r r,a8830,eeff4455 + + .lcomm dummy,4 + + .include "testutils.inc" + start + test_h_mem 0xabcdef01 0xd0000032 + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + ei + test_h_mem 0,dummy +killme: + fail + +irq0x34: + test_h_mem 0x76543210 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + pass + + singlevec irqvec1,0x34,irq0x34 diff --git a/sim/testsuite/cris/hw/rv-n-cris/irq5.ms b/sim/testsuite/cris/hw/rv-n-cris/irq5.ms new file mode 100644 index 0000000..4ecc5a6 --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/irq5.ms @@ -0,0 +1,46 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int 0xae" +#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int 0xae" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0x4\n +#output: /rv: IRQ 0x8\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: := 0xeeff4455\n +#output: pass\n + +# Much like irq4.ms, but modified to test vector case for multiple-int. + +#r W, +#r r,a8832,abcdef01 +#r I,4 +#r I,8 +#r r,a8836,76543210 +#r I,0 +#r r,a8830,eeff4455 + + .lcomm dummy,4 + + .include "testutils.inc" + start + test_h_mem 0xabcdef01 0xd0000032 + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + ei + test_h_mem 0,dummy +killme: + fail + +irq0xae: + test_h_mem 0x76543210 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + pass + + singlevec irqvec1,0xae,irq0xae diff --git a/sim/testsuite/cris/hw/rv-n-cris/irq6.ms b/sim/testsuite/cris/hw/rv-n-cris/irq6.ms new file mode 100644 index 0000000..9e40f4a --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/irq6.ms @@ -0,0 +1,99 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0x4\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: IRQ 0x8\n +#output: /rv: := 0xeeff4455\n +#output: /rv: REG R 0xd0000034\n +#output: /rv: := 0xdd001122\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0xaaeeff44\n +#output: /rv: REG R 0xd000003c\n +#output: /rv: := 0xff445511\n +#output: pass\n + +# Test two successive ints; that flags are disabled when an interrupt +# is taken, and then automatically (or by register restore) enabled at +# return. + +#r W, +#r r,a8832,abcdef01 +#r I,4 +#r r,a8836,76543210 +#r I,0 +#r I,8 +#r r,a8830,eeff4455 +#r r,a8834,dd001122 +#r r,a8838,aaeeff44 +#r r,a883c,ff445511 + + .lcomm dummy,4 + + .include "testutils.inc" + start + test_h_mem 0xabcdef01 0xd0000032 + moveq -1,$r4 + + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + + ei + test_h_mem 0,dummy + + ; Here after the first interrupt, or perhaps the second interrupt is + ; taken directly; leave it optional. Anyway, the second interrupt + ; should be taken no later than this branch. + test_h_mem 0,dummy + +killme: + fail + +irq0x33: + .if ..asm.arch.cris.v32 + ; Nothing needed to save flags - "shift" should happen, and back at rfe. + .else + ; The missing sim support for interrupt-excluding instructions is matched + ; by the flaw that sim doesn't service interrupts in straight code. + ; So, we can use a sequence that would work on actual hardware. + move $dccr,$r5 + di + .endif + + test_h_mem 0x76543210 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + test_h_mem 0xdd001122 0xd0000034 + moveq -22,$r4 + + .if ..asm.arch.cris.v32 + move irqvec2,$ebp + rete + rfe + .else + move irqvec2,$ibr + reti + move $r5,$dccr + .endif + + pass + +irq0x34: + test_h_mem 0xaaeeff44 0xd0000038 + test_h_mem 0xff445511 0xd000003c + cmpq -22,$r4 + bne killme + nop + pass + + singlevec irqvec1,0x33,irq0x33 + + singlevec irqvec2,0x34,irq0x34 diff --git a/sim/testsuite/cris/hw/rv-n-cris/mbox1.ms b/sim/testsuite/cris/hw/rv-n-cris/mbox1.ms new file mode 100644 index 0000000..ee0f54c --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/mbox1.ms @@ -0,0 +1,88 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: MBOX H 0x1001d..0x10037\n +#output: /rv: 0x10020: 12 23 34 56 79 8a bd de\n +#output: /rv: 0x10028: fb ad ba db ad 56 78 9a\n +#output: /rv: 0x10030: fd e1 23 45 66 54 32 1a\n +#output: /rv: -> 0x1001d..0x10027\n +#output: /rv: 0x10020: aa 55 77 88 32 10 ee cc\n +#output: /rv: MBOX P 0xfffd..0x1001f\n +#output: /rv: 0x10000: aa 55 12 23 34 56 79 8a\n +#output: /rv: 0x10008: bd de fb ad ba db ad 56\n +#output: /rv: 0x10010: 78 9a fd e1 23 45 66 54\n +#output: /rv: 0x10018: 32 1a ac cb be ed db ed\n +#output: /rv: -> 0xfffd..0x10017\n +#output: /rv: 0x10000: 11 22 56 78 ee dd 12 ab\n +#output: /rv: 0x10008: 55 aa ee 00 42 12 27 98\n +#output: /rv: 0x10010: 88 55 22 33 66 77 22 45\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0x76543211\n +#output: pass\n + +# Trivial test of mailbox commands. + +#r W, +#r i,1b000512233456798abddefbadbadbad56789afde123456654321a +#r o,0b0005aa5577883210eecc +#r i,230006aa5512233456798abddefbadbadbad56789afde123456654321aaccbbeeddbed +#r o,1b000511225678eedd12ab55aaee00421227988855223366772245 +#r r,a8838,76543211 + + .include "testutils.inc" + start + move.w 0x1b,$r0 + move.d 0x1001d,$r1 + move.w $r0,[$r1+] + moveq 5,$r0 + move.b $r0,[$r1] + mvi_h_mem 0x56342312 0x10020 + mvi_h_mem 0xdebd8a79 0x10024 + mvi_h_mem 0xdbbaadfb 0x10028 + mvi_h_mem 0x9a7856ad 0x1002c + mvi_h_mem 0x4523e1fd 0x10030 + mvi_h_mem 0x1a325466 0x10034 + + mvi_h_mem 0x1001d 0xc000f000 + + move.d 0x1001d,$r0 + movu.w [$r0+],$r1 + test_h_gr 0xb $r1 + movu.b [$r0],$r1 + test_h_gr 0x5 $r1 + test_h_mem 0x887755aa 0x10020 + test_h_mem 0xccee1032 0x10024 + + move.w 0x23,$r0 + move.d 0xfffd,$r1 + move.w $r0,[$r1+] + moveq 6,$r0 + move.b $r0,[$r1] + mvi_h_mem 0x231255aa 0x10000 + mvi_h_mem 0x8a795634 0x10004 + mvi_h_mem 0xadfbdebd 0x10008 + mvi_h_mem 0x56addbba 0x1000c + mvi_h_mem 0xe1fd9a78 0x10010 + mvi_h_mem 0x54664523 0x10014 + mvi_h_mem 0xcbac1a32 0x10018 + mvi_h_mem 0xeddbedbe 0x1001c + + mvi_h_mem 0xfffd 0xc000f000 + + move.d 0xfffd,$r0 + movu.w [$r0+],$r1 + test_h_gr 0x1b $r1 + movu.b [$r0],$r1 + test_h_gr 0x6 $r1 + test_h_mem 0x78562211 0x10000 + test_h_mem 0xab12ddee 0x10004 + test_h_mem 0x00eeaa55 0x10008 + test_h_mem 0x98271242 0x1000c + test_h_mem 0x33225588 0x10010 + test_h_mem 0x45227766 0x10014 + + test_h_mem 0x76543211 0xd0000038 + pass + + .fill 65536*2+128,1,0 diff --git a/sim/testsuite/cris/hw/rv-n-cris/mem1.ms b/sim/testsuite/cris/hw/rv-n-cris/mem1.ms new file mode 100644 index 0000000..ee5c4f5 --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/mem1.ms @@ -0,0 +1,100 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: DMA W 0x20020..0x2003f\n +#output: /rv: 0x20020: 12 23 34 56\n +#output: /rv: 0x20024: 79 8a bd de\n +#output: /rv: 0x20028: fb ad ba db\n +#output: /rv: 0x2002c: ad 56 78 9a\n +#output: /rv: 0x20030: fd e1 23 45\n +#output: /rv: 0x20034: 66 54 32 1a\n +#output: /rv: 0x20038: ac cb be ed\n +#output: /rv: 0x2003c: db ed aa da\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0x76543211\n +#output: /rv: DMA R 0x20000..0x2001f\n +#output: /rv: 0x20000: aa 55 12 23\n +#output: /rv: 0x20004: 34 56 79 8a\n +#output: /rv: 0x20008: bd de fb ad\n +#output: /rv: 0x2000c: ba db ad 56\n +#output: /rv: 0x20010: 78 9a fd e1\n +#output: /rv: 0x20014: 23 45 66 54\n +#output: /rv: 0x20018: 32 1a ac cb\n +#output: /rv: 0x2001c: be ed db ed\n +#output: /rv: IRQ 0x8\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0x76543212\n +#output: pass\n + +# Trivial test of DMA. + +# Locations of IRQ notifiers above depend on when the simulator is +# polled; adjustments may be needed (after checking that no poll is +# gone due to a bug!) + +#r W, +#r r,a8836,76543210 +#r s,e020,12233456798abddefbadbadbad56789afde123456654321aaccbbeeddbedaada +#r r,a8838,76543211 +#r l,e000,aa5512233456798abddefbadbadbad56789afde123456654321aaccbbeeddbed +#r I,8 +#r r,a8838,76543212 + + .include "testutils.inc" + start + test_h_mem 0x76543210 0xd0000036 + + move.d 0x2003f,$r1 + move.d 0x10000,$r3 +0: + test.b [$r1] + bne 1f + subq 1,$r3 + bne 0b + nop + +1: + test_h_mem 0x56342312 0x20020 + test_h_mem 0xdebd8a79 0x20024 + test_h_mem 0xdbbaadfb 0x20028 + test_h_mem 0x9a7856ad 0x2002c + test_h_mem 0x4523e1fd 0x20030 + test_h_mem 0x1a325466 0x20034 + test_h_mem 0xedbecbac 0x20038 + test_h_mem 0xdaaaeddb 0x2003c + + move.d 0x20020,$r0 + move.d 0x20000,$r1 + move.w 0x55aa,$r2 + move.w $r2,[r1+] + .rept 8 + move.d [$r0+],$r2 + move.d $r2,[$r1+] + .endr + + test_h_mem 0x76543211 0xd0000038 + + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + ei + move.d 0x100000,$r9 +0: + subq 1,$r9 + bne 0b + nop +killme: + fail + +irq0x34: + test_h_mem 0x76543212 0xd0000038 + pass + + .fill 65536*2+128,1,0 + + singlevec irqvec1,0x34,irq0x34 diff --git a/sim/testsuite/cris/hw/rv-n-cris/mem2.ms b/sim/testsuite/cris/hw/rv-n-cris/mem2.ms new file mode 100644 index 0000000..b676249 --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/mem2.ms @@ -0,0 +1,104 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: DMA W 0x20020..0x20043\n +#output: /rv: 0x20020: 12 23 34 56\n +#output: /rv: 0x20024: 79 8a bd de\n +#output: /rv: 0x20028: fb ad ba db\n +#output: /rv: 0x2002c: ad 56 78 9a\n +#output: /rv: 0x20030: fd e1 23 45\n +#output: /rv: 0x20034: 66 54 32 1a\n +#output: /rv: 0x20038: ac cb be ed\n +#output: /rv: 0x2003c: db ed aa da\n +#output: /rv: 0x20040: 00 aa bb cc\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0x76543211\n +#output: /rv: DMA R 0x20000..0x20023\n +#output: /rv: 0x20000: aa 55 12 23\n +#output: /rv: 0x20004: 34 56 79 8a\n +#output: /rv: 0x20008: bd de fb ad\n +#output: /rv: 0x2000c: ba db ad 56\n +#output: /rv: 0x20010: 78 9a fd e1\n +#output: /rv: 0x20014: 23 45 66 54\n +#output: /rv: 0x20018: 32 1a ac cb\n +#output: /rv: 0x2001c: be ed db ed\n +#output: /rv: 0x20020: aa da 00 aa\n +#output: /rv: IRQ 0x8\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0x76543212\n +#output: pass\n + +# This is a slight variation of mem1.ms just to trig the "buffer needs +# to be malloced for large request size" for the DMA request. + +# Locations of IRQ notifiers above depend on when the simulator is +# polled; adjustments may be needed (after checking that no poll is +# gone due to a bug!) + +#r W, +#r r,a8836,76543210 +#r s,e020,12233456798abddefbadbadbad56789afde123456654321aaccbbeeddbedaada00aabbcc +#r r,a8838,76543211 +#r l,e000,aa5512233456798abddefbadbadbad56789afde123456654321aaccbbeeddbedaada00aa +#r I,8 +#r r,a8838,76543212 + + .include "testutils.inc" + start + test_h_mem 0x76543210 0xd0000036 + + move.d 0x2003f,$r1 + move.d 0x10000,$r3 +0: + test.b [$r1] + bne 1f + subq 1,$r3 + bne 0b + nop + +1: + test_h_mem 0x56342312 0x20020 + test_h_mem 0xdebd8a79 0x20024 + test_h_mem 0xdbbaadfb 0x20028 + test_h_mem 0x9a7856ad 0x2002c + test_h_mem 0x4523e1fd 0x20030 + test_h_mem 0x1a325466 0x20034 + test_h_mem 0xedbecbac 0x20038 + test_h_mem 0xdaaaeddb 0x2003c + test_h_mem 0xccbbaa00 0x20040 + + move.d 0x20020,$r0 + move.d 0x20000,$r1 + move.w 0x55aa,$r2 + move.w $r2,[r1+] + .rept 9 + move.d [$r0+],$r2 + move.d $r2,[$r1+] + .endr + + test_h_mem 0x76543211 0xd0000038 + + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + ei + move.d 0x100000,$r9 +0: + subq 1,$r9 + bne 0b + nop +killme: + fail + +irq0x34: + test_h_mem 0x76543212 0xd0000038 + pass + + .fill 65536*2+128,1,0 + + singlevec irqvec1,0x34,irq0x34 diff --git a/sim/testsuite/cris/hw/rv-n-cris/poll1.ms b/sim/testsuite/cris/hw/rv-n-cris/poll1.ms new file mode 100644 index 0000000..baf1ed9 --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/poll1.ms @@ -0,0 +1,22 @@ +#mach: crisv32 +#sim(crisv32): --hw-device "/rv/dummy 0x12" + +# A variant of trivial2.ms to check that the right thing happens when +# we reach the poll function with a dummy device. + + .include "testutils.inc" + start + move.d 0xd0000000,$r0 + move.d [$r0+],$r3 + cmp.d 0x12121212,$r3 + beq ok + nop +bad: + fail +ok: + move.d 0x10000,$r10 +0: + bne 0b + subq 1,$r10 + + pass diff --git a/sim/testsuite/cris/hw/rv-n-cris/quit.s b/sim/testsuite/cris/hw/rv-n-cris/quit.s new file mode 100644 index 0000000..8c1d239 --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/quit.s @@ -0,0 +1,4 @@ +; Trivial target simulator program that just exits. + .include "testutils.inc" + startnostack + quit diff --git a/sim/testsuite/cris/hw/rv-n-cris/rvc.exp b/sim/testsuite/cris/hw/rv-n-cris/rvc.exp new file mode 100644 index 0000000..0f9ecec --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/rvc.exp @@ -0,0 +1,249 @@ +# Copyright (C) 2006-2021 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# Miscellaneous CRIS simulator testcases in assembly code, testing +# dv-rv.c and dv-cris.c functions. + +# Check whether dv-rv and dv-cris are present. + +proc sim_has_rv_and_cris {} { + global srcdir + global subdir + global SIMFLAGS + global global_as_options + global global_ld_options + global global_sim_options + + # We need to assemble and link a trivial program and pass that, in + # order to test successful exit. + + # A bit of duplication here for the assembling and linking part; + # what we want to do it to run the simulator without affecting the + # PASS/FAIL counters, and we can use e.g. run_sim_test for that. + + if ![info exists global_as_options] { + set global_as_options "" + } + if ![info exists global_ld_options] { + set global_ld_options "" + } + if ![info exists global_sim_options] { + set global_sim_options "" + } + + set comp_output [target_assemble $srcdir/$subdir/quit.s quit.o \ + "-I$srcdir/$subdir $global_as_options"] + + if ![string match "" $comp_output] { + verbose -log "$comp_output" 3 + fail "rv sim test setup (assembling)" + return 0 + } + + set comp_output [target_link quit.o quit.x "$global_ld_options"] + + if ![string match "" $comp_output] { + verbose -log "$comp_output" 3 + fail "rv sim test setup (linking)" + return 0 + } + + set result \ + [sim_run quit.x \ + "$global_sim_options --hw-device rv --hw-device cris --hw-info" \ + "" "" ""] + set return_code [lindex $result 0] + set output [lindex $result 1] + + if { $return_code == 0 } { + return 1 + } + + return 0 +} + +# Similar to slurp_options, but lines are fixed format "^#r ..." (not +# "^#{ws}*r:{ws}+" to avoid intruding on slurp_options syntax). Only +# trailing whitespace of the "..." is trimmed. Beware that lines +# including parameters may not contain ":". + +proc slurp_rv { file } { + if [catch { set f [open $file r] } x] { + #perror "couldn't open `$file': $x" + perror "$x" + return -1 + } + set rv_array {} + # whitespace expression + set ws {[ ]*} + # whitespace is ignored at the end of a line. + set pat "^#r (.*)$ws\$" + # Allow arbitrary lines until the first option is seen. + set seen_opt 0 + while { [gets $f line] != -1 } { + set line [string trim $line] + # Whitespace here is space-tab. + if [regexp $pat $line xxx cmd] { + # match! + lappend rv_array $cmd + set seen_opt 1 + } else { + if { $seen_opt } { + break + } + } + } + close $f + return $rv_array +} + +# The main test loop. + +if [istarget cris*-*-*] { + global ASFLAGS_FOR_TARGET + set has_rv_and_cris [sim_has_rv_and_cris] + global global_as_options + global global_ld_options + global global_sim_options + + set saved_global_sim_options $global_sim_options + set saved_global_ld_options $global_ld_options + + # See the logic in sim-defs.exp for more details. + set sim [board_info target sim] + if [string equal "" $sim] { + global objdir + global arch + set rvdummy "$objdir/../$arch/rvdummy" + } else { + set rvdummy "[file dirname [board_info target sim]]/rvdummy" + } + + # All machines we test and the corresponding assembler option. + # We'll only ever test v10 and higher here. + + set combos {{"crisv10" "--march=v10 --no-mul-bug-abort"} + {"crisv32" "--march=v32"}} + + # We need to pass different assembler flags for each machine. + # Specifying it here rather than adding a specifier to each and every + # test-file is preferrable. + + foreach combo $combos { + set mach [lindex $combo 0] + set ASFLAGS_FOR_TARGET "[lindex $combo 1]" + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + # Whoever runs the test should be alerted that not all + # testcases have been checked; that's why we do the loop + # and don't just return at the top. + if !$has_rv_and_cris { + untested $src + continue + } + + set sim_defaults "--hw-file $srcdir/$subdir/std.dev" + set ld_defaults "--section-start=.text=0" + + # We parse options an extra time besides in run_sim_test, + # to determine if our defaults should be overridden. + + set opt_array [slurp_options $src] + foreach i $opt_array { + set opt_name [lindex $i 0] + set opt_machs [lindex $i 1] + set opt_val [lindex $i 2] + + # Allow concatenating to the default options by + # specifying a mach. + if { $opt_name == "sim" && $opt_machs == "" } { + set sim_defaults "" + } + + if { $opt_name == "ld" && $opt_machs == "" } { + set ld_defaults "" + } + } + + set rvdummy_id -1 + set hostcmds [slurp_rv $src] + + if { $hostcmds != "" } { + # I guess we could ask to have rvdummy executed on a + # remote host, but it looks like too much trouble for + # a feature rarely used. + if [is_remote host] { + untested $src + continue + } + + set src_components [file split $src] + set rvfile "[lindex $src_components \ + [expr [llength $src_components] - 1]].r" + + if [catch { set f [open $rvfile w] } x] { + error "$x" + } { + set contents [join $hostcmds "\n"] + + # Make it possible to use files from the test + # source directory; expected with the @-command. + regsub -all "@srcdir@" $contents "$srcdir/$subdir" contents + + verbose "rv: $contents" 2 + puts $f $contents + close $f + } + + spawn -noecho $rvdummy "$rvfile" + if { $spawn_id < 0 } { + error "Couldn't spawn $rvdummy" + continue + } + set rvdummy_id $spawn_id + } + + # Unfortunately this seems like the only way to pass + # additional sim, ld etc. options to run_sim_test. + set global_sim_options "$saved_global_sim_options $sim_defaults" + set global_ld_options "$saved_global_ld_options $ld_defaults" + run_sim_test $src $mach + set global_sim_options $saved_global_sim_options + set global_ld_options $saved_global_ld_options + + # Stop the rvdummy, if it's still running. We need to + # wait on it anyway to avoid it turning into a zombie. + if { $rvdummy_id != -1 } { + close -i $rvdummy_id + wait -i $rvdummy_id + + # Gleaned from framework.exp, this seems an indicator + # to whether the test had expected outcome. If so, we + # want to remove the rv-file. + if { $exit_status == 0 } { + file delete $rvfile + } + } + } + } +} diff --git a/sim/testsuite/cris/hw/rv-n-cris/std.dev b/sim/testsuite/cris/hw/rv-n-cris/std.dev new file mode 100644 index 0000000..9fefcbb --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/std.dev @@ -0,0 +1,8 @@ +/rv/reg 0xd0000000 64 +/rv/remote-reg 0xa8800 +/rv/intnum 4 2 +/cris/vec-for-int 4 0x33 8 0x34 0xaa 0xea +/rv/mem 0x20000 0x400 +/rv/remote-mem 0xe000 +/rv/mbox 0xc000f000 +/rv > int int /cris diff --git a/sim/testsuite/cris/hw/rv-n-cris/testutils.inc b/sim/testsuite/cris/hw/rv-n-cris/testutils.inc new file mode 100644 index 0000000..e707abf --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/testutils.inc @@ -0,0 +1,22 @@ + .include "../../asm/testutils.inc" + +# Define an exception vector table "vecname" with a single +# vector number "n" as "entry", all others "other". +# V32 only needs 1<<10 alignment, earlier versions need 1<<16. + .macro singlevec vecname vecno entry other=killme + .section .text.exvec + .p2align 16 +\vecname: + .if (\vecno) + .rept \vecno + .dword \other + .endr + .endif + .dword \entry + .if (\vecno)-255 + .rept 256-(\vecno)-1 + .dword \other + .endr + .endif + .previous + .endm diff --git a/sim/testsuite/cris/hw/rv-n-cris/trivial1.ms b/sim/testsuite/cris/hw/rv-n-cris/trivial1.ms new file mode 100644 index 0000000..a219b04 --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/trivial1.ms @@ -0,0 +1,17 @@ +#mach: crisv32 +#sim(crisv32): --hw-info +#output: /\n +#output: /rv\n +#output: /rv/reg 0xd0000000 0x40\n +#output: /rv/remote-reg 0xa8800\n +#output: /rv/intnum 0x4 0x2\n +#output: /rv/mem 0x20000 0x400\n +#output: /rv/remote-mem 0xe000\n +#output: /rv/mbox 0xc000f000\n +#output: /rv > int int /cris\n +#output: /cris\n +#output: /cris/vec-for-int 0x4 0x33 0x8 0x34 0xaa 0xea\n + +# Test expected --hw-info output and startup paths of components. + + .include "quit.s" diff --git a/sim/testsuite/cris/hw/rv-n-cris/trivial2.ms b/sim/testsuite/cris/hw/rv-n-cris/trivial2.ms new file mode 100644 index 0000000..b633445 --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/trivial2.ms @@ -0,0 +1,21 @@ +#mach: crisv32 +#sim(crisv32): --hw-device "/rv/dummy 0x12" + +# Test dummy settings: set from value. + + .include "testutils.inc" + start + move.d 0xd0000000,$r0 + move.d [$r0+],$r3 + cmp.d 0x12121212,$r3 + beq ok + nop +bad: + fail +ok: + moveq -1,$r3 + move.d $r3,[$r0] + cmp.d [$r0],$r3 + bne bad + nop + pass diff --git a/sim/testsuite/cris/hw/rv-n-cris/trivial3.ms b/sim/testsuite/cris/hw/rv-n-cris/trivial3.ms new file mode 100644 index 0000000..1f23b49 --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/trivial3.ms @@ -0,0 +1,20 @@ +#mach: crisv32 +#sim(crisv32): --hw-device "/rv/dummy /dev/zero" + +# Test dummy settings: set from file. + + .include "testutils.inc" + start + move.d 0xd0000000,$r0 + move.d [$r0+],$r3 + beq ok + nop +bad: + fail +ok: + moveq -1,$r3 + move.d $r3,[$r0] + cmp.d [$r0],$r3 + bne bad + nop + pass diff --git a/sim/testsuite/cris/hw/rv-n-cris/trivial4.ms b/sim/testsuite/cris/hw/rv-n-cris/trivial4.ms new file mode 100644 index 0000000..6108160 --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/trivial4.ms @@ -0,0 +1,22 @@ +#mach: crisv32 +#r @,@srcdir@/trivial4.r + +# Test read and writes. + + .include "testutils.inc" + start + move.d 0xd0000032,$r0 + move.d [$r0+],$r3 + cmp.d 0xabcdef01,$r3 + beq ok + nop +bad: + fail +ok: + move.d 0xaabbccdd,$r3 + move.d $r3,[$r0] + move.d [$r0],$r3 + cmp.d 0x76543210,$r3 + bne bad + nop + pass diff --git a/sim/testsuite/cris/hw/rv-n-cris/trivial4.r b/sim/testsuite/cris/hw/rv-n-cris/trivial4.r new file mode 100644 index 0000000..b4896a0 --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/trivial4.r @@ -0,0 +1,4 @@ +W, +r,a8832,abcdef01 +w,a8836,aabbccdd +r,a8836,76543210 diff --git a/sim/testsuite/cris/hw/rv-n-cris/trivial5.ms b/sim/testsuite/cris/hw/rv-n-cris/trivial5.ms new file mode 100644 index 0000000..849f17e --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/trivial5.ms @@ -0,0 +1,16 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: REG W 0xd0000036 := 0xaabbccdd\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: pass\n + +# Test trace output for read and write. + +#r @,@srcdir@/trivial4.r + + .include "trivial4.ms" diff --git a/sim/testsuite/cris/hw/rv-n-cris/wd1.ms b/sim/testsuite/cris/hw/rv-n-cris/wd1.ms new file mode 100644 index 0000000..91af7fc --- /dev/null +++ b/sim/testsuite/cris/hw/rv-n-cris/wd1.ms @@ -0,0 +1,33 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/rv/watchdog-interval 1" +#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/rv/watchdog-interval 1" --hw-device "/rv/max-poll-ticks 1000" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: WD\n +#output: /rv: DMA W 0x20000..0x20003\n +#output: /rv: 0x20000: 01 02 03 04\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0x76543211\n +#output: pass\n + +#r W, +#r r,a8836,76543210 +#r W, +#r s,e000,01020304 +#r r,a8838,76543211 + + .include "testutils.inc" + start + mvi_h_mem 0 0x20000 + test_h_mem 0x76543210 0xd0000036 + + move.d 0x20000,$r1 +0: + test.b [$r1] + beq 0b + nop + test_h_mem 0x76543211 0xd0000038 + pass + + .fill 65536*2+128,1,0 diff --git a/sim/testsuite/d10v/ChangeLog b/sim/testsuite/d10v/ChangeLog new file mode 100644 index 0000000..5ca8910 --- /dev/null +++ b/sim/testsuite/d10v/ChangeLog @@ -0,0 +1,144 @@ +2021-01-15 Mike Frysinger + + * allinsn.exp: New file. + * configure, configure.ac, loop.s, Makefile.in: Deleted. + +2020-10-06 Andrew Burgess + + * configure: Regnerate. + * configure.ac (AC_CONFIG_AUX_DIR): Update. + +2015-03-30 Mike Frysinger + + * Makefile.in (RUNFLAGS_FOR_TARGET): Set to --environment operating. + +2009-08-22 Ralf Wildenhues + + * configure: Regenerate. + +2005-01-07 Andrew Cagney + + * configure.ac: Rename configure.in, require autoconf 2.59. + * configure: Re-generate. + +Tue Apr 18 16:32:07 2000 Andrew Cagney + + * t-rie-xx.s (test_rie_xx): New test. + * Makefile.in (TESTS): Update. + +Tue Feb 22 17:36:34 2000 Andrew Cagney + + * Makefile.in: Force d10v into operating mode. + +Mon Jan 3 00:17:28 2000 Andrew Cagney + + * t-ae-ld-d.s, t-ae-ld-i.s, t-ae-ld-id.s, t-ae-ld-im.s , + t-ae-ld-ip.s, t-ae-ld2w-d.s, t-ae-ld2w-i.s, t-ae-ld2w-id.s , + t-ae-ld2w-im.s, t-ae-ld2w-ip.s, t-ae-st-d.s, t-ae-st-i.s , + t-ae-st-id.s, t-ae-st-im.s, t-ae-st-ip.s, t-ae-st-is.s , + t-ae-st2w-d.s, t-ae-st2w-i.s, t-ae-st2w-id.s, t-ae-st2w-im.s , + t-ae-st2w-ip.s, t-ae-st2w-is.s: New tests. Check that an address + exception occures when a word/two-word load/store is not word + aligned. + * Makefile.in (TESTS): Update. + +Fri Oct 29 18:36:34 1999 Andrew Cagney + + * t-mvtc.s: Check that the user can not modify the DM bit in the + BPSW or DPSW. + +Thu Oct 28 01:47:26 1999 Andrew Cagney + + * t-mvtc.s: Update. Check that user can not modify DM bit. + +Wed Sep 8 19:34:55 MDT 1999 Diego Novillo + + * t-ld-st.s: New file. + * t-sac.s: New file. + * t-sachi.s: New file. + * t-slae.s: New file. + +1999-01-13 Jason Molenda (jsm@bugshack.cygnus.com) + + * t-sadd.s: New file. + * Makefile.in (TESTS): Add t-sadd. + +Mon Feb 16 09:20:57 1998 Andrew Cagney + + * t-macros.i (VEC_*): Define. + (DMAP_REG, DMAP_BASE, DMAP_MASK): Define. + (IMAP[01]_REG): Define. + + * t-rdt.s (test_tdt): New file. + + * t-dbt.s (test_dbt): New file. + + * Makefile.in (TESTS): Add t-rdt and t-dbt. + + +Fri Feb 13 16:21:13 1998 Andrew Cagney + + * t-sp.s: New test. + * Makefile.in (TESTS): Update. + +Wed Feb 11 17:58:50 1998 Andrew Cagney + + * t-macros.i: Update trap calls, func in r4, args in + r0... + (start): Force r0 to zero. + + * t-sub2w.s: Ditto. + +Tue Dec 9 10:41:44 1997 Andrew Cagney + + * t-rte.s (success): New file. + * Makefile.in: Update. + + * t-rep.s: Check rep repeats correct number of times. + +Fri Dec 5 10:11:18 1997 Andrew Cagney + + * t-mvtc.s: Check for stuck-zero in MOD_E, MOD_S. + + * t-trap.s: New file. + * Makefile.in (TESTS): Update. + +Thu Dec 4 16:56:55 1997 Andrew Cagney + + * t-macros.i: Add definitions for PSW bits. + + * t-mvtc.s: New file. + * Makefile.in (TESTS): Update. + +Wed Dec 3 16:35:24 1997 Andrew Cagney + + * t-rac.s: New files. + + * t-macros.i: Add macros for checking psw and 2w quantities. + + * Makefile.in (TESTS): Update. + +Tue Dec 2 11:01:36 1997 Andrew Cagney + + * t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s, t-sub.s: New + files. + + * Makefile.in: Update. + +Mon Nov 17 20:14:48 1997 Andrew Cagney + + * t-subi.s (test_subi): New file. + * Makefile.in: Update. + +Fri Nov 14 14:06:06 1997 Andrew Cagney + + * t-rep.s: New file. Test case of branch to RPT_E address. + +Mon Nov 10 19:21:26 1997 Andrew Cagney + + * t-macros.i (_start): New file. + * t-rachi.s: New file. + + * Makefile.in (RUN_FOR_TARGET): Look for simulator in d10v + directory. + diff --git a/sim/testsuite/d10v/allinsn.exp b/sim/testsuite/d10v/allinsn.exp new file mode 100644 index 0000000..123509a --- /dev/null +++ b/sim/testsuite/d10v/allinsn.exp @@ -0,0 +1,17 @@ +# d10v simulator testsuite. + +if [istarget d10v*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "d10v" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/d10v/exit47.s b/sim/testsuite/d10v/exit47.s new file mode 100644 index 0000000..8f2a6ee --- /dev/null +++ b/sim/testsuite/d10v/exit47.s @@ -0,0 +1,8 @@ +# mach: all +# status: 47 +# output: + +.include "t-macros.i" + + start + exit47 diff --git a/sim/testsuite/d10v/hello.s b/sim/testsuite/d10v/hello.s new file mode 100644 index 0000000..3e3557d --- /dev/null +++ b/sim/testsuite/d10v/hello.s @@ -0,0 +1,8 @@ +# mach: all +# output: Hello World!\n + + .include "t-macros.i" + + start + hello + exit0 diff --git a/sim/testsuite/d10v/t-ae-ld-d.s b/sim/testsuite/d10v/t-ae-ld-d.s new file mode 100644 index 0000000..511fbb0 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-ld-d.s @@ -0,0 +1,17 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ld r8,@0x4000 +test_ld: + ld r8,@0x4001 + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-ld-i.s b/sim/testsuite/d10v/t-ae-ld-i.s new file mode 100644 index 0000000..b9d10d1 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-ld-i.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ldi r10, #0x4000 + ld r8, @r10 + + ldi r10, #0x4001 +test_ld: + ld r8,@r10 + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-ld-id.s b/sim/testsuite/d10v/t-ae-ld-id.s new file mode 100644 index 0000000..ed86525 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-ld-id.s @@ -0,0 +1,19 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ldi r10, #0x4001 + ld r8, @(1,r10) + +test_ld: + ld r8,@(2,r10) + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-ld-im.s b/sim/testsuite/d10v/t-ae-ld-im.s new file mode 100644 index 0000000..42f8716 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-ld-im.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ldi r10, #0x4000 + ld r8, @r10- + + ldi r10, #0x4001 +test_ld: + ld r8,@r10- + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-ld-ip.s b/sim/testsuite/d10v/t-ae-ld-ip.s new file mode 100644 index 0000000..c163912 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-ld-ip.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ldi r10, #0x4000 + ld r8, @r10+ + + ldi r10, #0x4001 +test_ld: + ld r8,@r10+ + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-ld2w-d.s b/sim/testsuite/d10v/t-ae-ld2w-d.s new file mode 100644 index 0000000..1c81594 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-ld2w-d.s @@ -0,0 +1,17 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ld2w r8,@0x4000 +test_ld2w: + ld2w r8,@0x4001 + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-ld2w-i.s b/sim/testsuite/d10v/t-ae-ld2w-i.s new file mode 100644 index 0000000..9547870 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-ld2w-i.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ldi r10, #0x4000 + ld2w r8, @r10 + + ldi r10, #0x4001 +test_ld2w: + ld2w r8,@r10 + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-ld2w-id.s b/sim/testsuite/d10v/t-ae-ld2w-id.s new file mode 100644 index 0000000..2766388 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-ld2w-id.s @@ -0,0 +1,18 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ldi r10, #0x4001 + ld2w r8,@(1,r10) +test_ld2w: + ld2w r8,@(2,r10) + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-ld2w-im.s b/sim/testsuite/d10v/t-ae-ld2w-im.s new file mode 100644 index 0000000..c6946f3 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-ld2w-im.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ldi r10, #0x4000 + ld2w r8, @r10- + + ldi r10, #0x4001 +test_ld2w: + ld2w r8,@r10- + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-ld2w-ip.s b/sim/testsuite/d10v/t-ae-ld2w-ip.s new file mode 100644 index 0000000..6214853 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-ld2w-ip.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ldi r10, #0x4000 + ld2w r8, @r10+ + + ldi r10, #0x4001 +test_ld2w: + ld2w r8,@r10+ + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-st-d.s b/sim/testsuite/d10v/t-ae-st-d.s new file mode 100644 index 0000000..99bd724 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-st-d.s @@ -0,0 +1,17 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + st r8,@0x4000 +test_st: + st r8,@0x4001 + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-st-i.s b/sim/testsuite/d10v/t-ae-st-i.s new file mode 100644 index 0000000..5f0f9b4 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-st-i.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi r10,#0x4000 + st r8, @r10 + + ldi r10,#0x4001 +test_st: + st r8,@r10 + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-st-id.s b/sim/testsuite/d10v/t-ae-st-id.s new file mode 100644 index 0000000..9620fce --- /dev/null +++ b/sim/testsuite/d10v/t-ae-st-id.s @@ -0,0 +1,18 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi r10,#0x4001 + st r8, @(1,r10) +test_st: + st r8,@(2,r10) + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-st-im.s b/sim/testsuite/d10v/t-ae-st-im.s new file mode 100644 index 0000000..0318243 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-st-im.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi r10,#0x4000 + st r8, @r10- + + ldi r10,#0x4001 +test_st: + st r8,@r10- + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-st-ip.s b/sim/testsuite/d10v/t-ae-st-ip.s new file mode 100644 index 0000000..78d9a1d --- /dev/null +++ b/sim/testsuite/d10v/t-ae-st-ip.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi r10,#0x4000 + st r8, @r10+ + + ldi r10,#0x4001 +test_st: + st r8,@r10+ + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-st-is.s b/sim/testsuite/d10v/t-ae-st-is.s new file mode 100644 index 0000000..08e1d7e --- /dev/null +++ b/sim/testsuite/d10v/t-ae-st-is.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi sp,#0x4000 + st r8, @-SP + + ldi sp,#0x4001 +test_st: + st r8,@-SP + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-st2w-d.s b/sim/testsuite/d10v/t-ae-st2w-d.s new file mode 100644 index 0000000..6f07a99 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-st2w-d.s @@ -0,0 +1,17 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + st2w r8,@0x4000 +test_st2w: + st2w r8,@0x4001 + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-st2w-i.s b/sim/testsuite/d10v/t-ae-st2w-i.s new file mode 100644 index 0000000..a629b75 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-st2w-i.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi r10, #0x4000 + st2w r8, @r10 + + ldi r10, #0x4001 +test_st2w: + st2w r8,@r10 + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-st2w-id.s b/sim/testsuite/d10v/t-ae-st2w-id.s new file mode 100644 index 0000000..91f2319 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-st2w-id.s @@ -0,0 +1,18 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi r10, #0x4001 + st2w r8, @(1,r10) +test_st2w: + st2w r8,@(2,r10) + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-st2w-im.s b/sim/testsuite/d10v/t-ae-st2w-im.s new file mode 100644 index 0000000..f8cc7fb --- /dev/null +++ b/sim/testsuite/d10v/t-ae-st2w-im.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi r10, #0x4000 + st2w r8, @r10- + + ldi r10, #0x4001 +test_st2w: + st2w r8,@r10- + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-st2w-ip.s b/sim/testsuite/d10v/t-ae-st2w-ip.s new file mode 100644 index 0000000..63c5abd --- /dev/null +++ b/sim/testsuite/d10v/t-ae-st2w-ip.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi r10, #0x4000 + st2w r8, @r10+ + + ldi r10, #0x4001 +test_st2w: + st2w r8,@r10+ + nop + exit47 diff --git a/sim/testsuite/d10v/t-ae-st2w-is.s b/sim/testsuite/d10v/t-ae-st2w-is.s new file mode 100644 index 0000000..190ab42 --- /dev/null +++ b/sim/testsuite/d10v/t-ae-st2w-is.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi sp, #0x4004 + st2w r8, @-SP + + ldi sp, #0x4005 +test_st2w: + st2w r8,@-SP + nop + exit47 diff --git a/sim/testsuite/d10v/t-dbt.s b/sim/testsuite/d10v/t-dbt.s new file mode 100644 index 0000000..9b405b0 --- /dev/null +++ b/sim/testsuite/d10v/t-dbt.s @@ -0,0 +1,38 @@ +# mach: all +# output: +# sim: --environment operating +# as: -W + +.include "t-macros.i" + + start + + PSW_BITS = PSW_DM + +;;; Blat our DMAP registers so that they point at on-chip imem + + ldi r2, MAP_INSN | 0xf + st r2, @(DMAP_REG,r0) + ldi r2, MAP_INSN + st r2, @(IMAP1_REG,r0) + +;;; Patch the interrupt vector's dbt entry with a jmp to success + + ldi r4, #trap + ldi r5, (VEC_DBT & DMAP_MASK) + DMAP_BASE + ld2w r2, @(0,r4) + st2w r2, @(0,r5) + ld2w r2, @(4,r4) + st2w r2, @(4,r5) + +test_dbt: + dbt -> nop + exit47 + +success: + checkpsw2 1 PSW_BITS + exit0 + + .data +trap: ldi r1, success@word + jmp r1 diff --git a/sim/testsuite/d10v/t-ld-st.s b/sim/testsuite/d10v/t-ld-st.s new file mode 100644 index 0000000..4ae4f85 --- /dev/null +++ b/sim/testsuite/d10v/t-ld-st.s @@ -0,0 +1,36 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + ; Test ld and st + ld r4, @foo + check 1 r4 0xdead + + ldi r4, #0x2152 + st r4, @foo + ld r4, @foo + check 2 r4 0x2152 + + ; Test ld2w and st2w + ldi r4, #0xdead + st r4, @foo + ld2w r4, @foo + check2w2 3 r4 0xdead 0xf000 + + ldi r4, #0x2112 + ldi r5, #0x1984 + st2w r4, @foo + ld2w r4, @foo + check2w2 4 r4 0x2112 0x1984 + + .data + .align 2 +foo: .short 0xdead +bar: .short 0xf000 + .text + + exit0 diff --git a/sim/testsuite/d10v/t-mac.s b/sim/testsuite/d10v/t-mac.s new file mode 100644 index 0000000..1b6e660 --- /dev/null +++ b/sim/testsuite/d10v/t-mac.s @@ -0,0 +1,75 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + ;; clear FX + loadpsw2 0x8005 + loadacc2 a1 0x7f 0xffff 0xffff + load r8 0xffff + load r9 0x8001 +test_macu1: + MACU a1, r9, r8 + checkacc2 1 a1 0x80 0x8000 0x7FFE + + ;; set FX + loadpsw2 0x8085 + loadacc2 a1 0x7f 0xffff 0xffff + load r8 0xffff + load r9 0x8001 +test_macu2: + MACU a1, r9, r8 + checkacc2 2 a1 0x81 0x0000 0xfffd + + + + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, #0xffff + ldi r9, #0x7FFF +test_macsu1: + MACSU a1, r9, r8 + checkacc2 3 a1 0x80 0x7FFE 0x8000 + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, #0xffff + ldi r9, #0x7FFF +test_macsu2: + MACSU a1, r9, r8 + checkacc2 4 a1 0x80 0xfffd 0x0001 + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_macsu3: + MACSU a1, r9, r8 + checkacc2 5 a1 0x7F 0x8001 0x7FFE + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, #0xffff + ldi r9, #0x8001 +test_macsu4: + MACSU a1, r9, r8 + checkacc2 6 a1 0x7f 0x0002 0xFFFD + + exit0 + diff --git a/sim/testsuite/d10v/t-macros.i b/sim/testsuite/d10v/t-macros.i new file mode 100644 index 0000000..d6e155c --- /dev/null +++ b/sim/testsuite/d10v/t-macros.i @@ -0,0 +1,235 @@ +# mach: d10v +# output: +# sim: --environment operating + + .macro start + .text + .align 2 + .globl _start +_start: + ldi r0, 0 + .endm + + + .macro exit47 + ldi r4, 1 + ldi r0, 47 + trap 15 + .endm + + + .macro exit0 + ldi r4, 1 + ldi r0, 0 + trap 15 + .endm + + + .macro exit1 + ldi r4, 1 + ldi r0, 1 + trap 15 + .endm + + + .macro exit2 + ldi r4, 1 + ldi r0, 2 + trap 15 + .endm + + + .macro load reg val + ldi \reg, #\val + .endm + + + .macro load2w reg hi lo + ld2w \reg, @(1f,r0) + .data + .align 2 +1: .short \hi + .short \lo + .text + .endm + + + .macro check exit reg val + cmpeqi \reg, #\val + brf0t 1f +0: ldi r4, 1 + ldi r0, \exit + trap 15 +1: + .endm + + + .macro check2w2 exit reg hi lo + st2w \reg, @(1f,r0) + ld r2, @(1f, r0) + cmpeqi r2, #\hi + brf0f 0f + ld r2, @(1f + 2, r0) + cmpeqi r2, #\lo + brf0f 0f + bra 2f +0: ldi r4, 1 + ldi r0, \exit + trap 15 + .data + .align 2 +1: .long 0 + .text +2: + .endm + + + .macro loadacc2 acc guard hi lo + ldi r2, #\lo + mvtaclo r2, \acc + ldi r2, #\hi + mvtachi r2, \acc + ldi r2, #\guard + mvtacg r2, \acc + .endm + + + .macro checkacc2 exit acc guard hi lo + ldi r2, #\guard + mvfacg r3, \acc + cmpeq r2, r3 + brf0f 0f + ldi r2, #\hi + mvfachi r3, \acc + cmpeq r2, r3 + brf0f 0f + ldi r2, #\lo + mvfaclo r3, \acc + cmpeq r2, r3 + brf0f 0f + bra 4f +0: ldi r4, 1 + ldi r0, \exit + trap 15 +4: + .endm + + + .macro loadpsw2 val + ldi r2, #\val + mvtc r2, cr0 + .endm + + + .macro checkpsw2 exit val + mvfc r2, cr0 + cmpeqi r2, #\val + brf0t 1f + ldi r4, 1 + ldi r0, \exit + trap 15 +1: + .endm + + + .macro hello + ;; 4:write (1, string, strlen (string)) + ldi r4, 4 + ldi r0, 1 + ldi r1, 1f + ldi r2, 2f-1f-1 + trap 15 + .section .rodata +1: .string "Hello World!\n" +2: .align 2 + .text + .endm + + +;;; Blat our DMAP registers so that they point at on-chip imem + .macro point_dmap_at_imem + .text + ldi r2, MAP_INSN | 0xf + st r2, @(DMAP_REG,r0) + ldi r2, MAP_INSN + st r2, @(IMAP1_REG,r0) + .endm + +;;; Patch VEC so that it jumps back to code that checks PSW +;;; and then exits with success. + .macro check_interrupt vec psw src +;;; Patch the interrupt vector's AE entry with a jmp to success + .text + ldi r4, #1f + ldi r5, \vec + ;; + ld2w r2, @(0,r4) + st2w r2, @(0,r5) + ld2w r2, @(4,r4) + st2w r2, @(4,r5) + ;; + bra 9f + nop +;;; Code that gets patched into the interrupt vector + .data +1: ldi r1, 2f@word + jmp r1 +;;; Successfull trap jumps back to here + .text +;;; Verify the PSW +2: mvfc r2, cr0 + cmpeqi r2, #\psw + brf0t 3f + nop + exit1 +;;; Verify the original addr +3: mvfc r2, bpc + cmpeqi r2, #\src@word + brf0t 4f + exit2 +4: exit0 +;;; continue as normal +9: + .endm + + + PSW_SM = 0x8000 + PSW_01 = 0x4000 + PSW_EA = 0x2000 + PSW_DB = 0x1000 + PSW_DM = 0x0800 + PSW_IE = 0x0400 + PSW_RP = 0x0200 + PSW_MD = 0x0100 + PSW_FX = 0x0080 + PSW_ST = 0x0040 + PSW_10 = 0x0020 + PSW_11 = 0x0010 + PSW_F0 = 0x0008 + PSW_F1 = 0x0004 + PSW_14 = 0x0002 + PSW_C = 0x0001 + + +;;; + + DMAP_MASK = 0x3fff + DMAP_BASE = 0x8000 + DMAP_REG = 0xff04 + + IMAP0_REG = 0xff00 + IMAP1_REG = 0xff02 + + MAP_INSN = 0x1000 + +;;; + + VEC_RI = 0x3ff00 + VEC_BAE = 0x3ff04 + VEC_RIE = 0x3ff08 + VEC_AE = 0x3ff0c + VEC_TRAP = 0x3ff10 + VEC_DBT = 0x3ff50 + VEC_SDBT = 0x3fff4 + VEC_DBI = 0x3ff58 + VEC_EI = 0x3ff5c diff --git a/sim/testsuite/d10v/t-mod-ld-pre.s b/sim/testsuite/d10v/t-mod-ld-pre.s new file mode 100644 index 0000000..7d75af2 --- /dev/null +++ b/sim/testsuite/d10v/t-mod-ld-pre.s @@ -0,0 +1,126 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + mvfc r0, PSW || ldi.s r14, #0 + ldi.l r2, 0x100 ; MOD_E + ldi.l r3, 0x108 ; MOD_S + +test_mod_dec_ld: + mvtc r2, MOD_E || bseti r0, #7 + mvtc r3, MOD_S + mvtc r0, PSW ; modulo mode enable + mv r1,r3 ; r1=0x108 + ld r4, @r1- || nop ; r1=0x106 + ld r4, @r1- || nop ; r1=0x104 + ld r4, @r1- || nop ; r1=0x102 + ld r4, @r1- || nop ; r1=0x100 + ld r4, @r1- || nop ; r1=0x108 + ld r4, @r1- || nop ; r1=0x106 + + cmpeqi r1,#0x106 + brf0f _ERR ; branch to error + +test_mod_inc_ld: + mvtc r2, MOD_S + mvtc r3, MOD_E + mv r1,r2 ; r1=0x100 + ld r4, @r1+ || nop ; r1=0x102 + ld r4, @r1+ || nop ; r1=0x104 + ld r4, @r1+ || nop ; r1=0x106 + ld r4, @r1+ || nop ; r1=0x108 + ld r4, @r1+ || nop ; r1=0x100 + ld r4, @r1+ || nop ; r1=0x102 + + cmpeqi r1,#0x102 + brf0f _ERR + +test_mod_dec_ld2w: + mvtc r2, MOD_E + mvtc r3, MOD_S + mv r1,r3 ; r1=0x108 + ld2W r4, @r1- || nop ; r1=0x104 + ld2W r4, @r1- || nop ; r1=0x100 + ld2W r4, @r1- || nop ; r1=0x108 + ld2W r4, @r1- || nop ; r1=0x104 + + cmpeqi r1,#0x104 + brf0f _ERR ; <= branch to error + +test_mod_inc_ld2w: + mvtc r2, MOD_S + mvtc r3, MOD_E || BCLRI r0, #7 + mv r1,r2 ; r1=0x100 + ld2W r4, @r1+ || nop ; r1=0x104 + ld2W r4, @r1+ || nop ; r1=0x108 + ld2W r4, @r1+ || nop ; r1=0x100 + ld2W r4, @r1+ || nop ; r1=0x104 + + cmpeqi r1,#0x104 + brf0f _ERR + +test_mod_dec_ld_dis: + mvtc r0, PSW ; modulo mode disable + mvtc r2, MOD_E + mvtc r3, MOD_S + mv r1,r3 ; r1=0x108 + ld r4, @r1- || nop ; r1=0x106 + ld r4, @r1- || nop ; r1=0x104 + ld r4, @r1- || nop ; r1=0x102 + ld r4, @r1- || nop ; r1=0x100 + ld r4, @r1- || nop ; r1=0xFE + ld r4, @r1- || nop ; r1=0xFC + + cmpeqi r1,#0xFC + brf0f _ERR + +test_mod_inc_ld_dis: + mvtc r2, MOD_S + mvtc r3, MOD_E + mv r1,r2 ; r1=0x100 + ld r4, @r1+ || nop ; r1=0x102 + ld r4, @r1+ || nop ; r1=0x104 + ld r4, @r1+ || nop ; r1=0x106 + ld r4, @r1+ || nop ; r1=0x108 + ld r4, @r1+ || nop ; r1=0x10A + ld r4, @r1+ || nop ; r1=0x10C + + cmpeqi r1,#0x10C + brf0f _ERR + +test_mod_dec_ld2w_dis: + mvtc r2, MOD_E + mvtc r3, MOD_S + mv r1,r3 ; r1=0x108 + ld2W r4, @r1- || nop ; r1=0x104 + ld2W r4, @r1- || nop ; r1=0x100 + ld2W r4, @r1- || nop ; r1=0xFC + ld2W r4, @r1- || nop ; r1=0xF8 + + cmpeqi r1,#0xF8 + brf0f _ERR + + test_mod_inc_ld2w_dis: + mvtc r2, MOD_S + mvtc r3, MOD_E + mv r1,r2 ; r1=0x100 + ld2W r4, @r1+ || nop ; r1=0x104 + ld2W r4, @r1+ || nop ; r1=0x108 + ld2W r4, @r1+ || nop ; r1=0x10C + ld2W r4, @r1+ || nop ; r1=0x110 + + cmpeqi r1,#0x110 + brf0f _ERR + +_OK: + exit0 + +_ERR: + exit47 + + + diff --git a/sim/testsuite/d10v/t-msbu.s b/sim/testsuite/d10v/t-msbu.s new file mode 100644 index 0000000..93b65a5 --- /dev/null +++ b/sim/testsuite/d10v/t-msbu.s @@ -0,0 +1,32 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_msbu1: + MSBU a1, r9, r8 + checkacc2 1 a1 0X7F 0x7FFF 0x8000 + + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_msbu2: + MSBU a1, r9, r8 + checkacc2 2 a1 0X7E 0xFFFF 0x0001 + + exit0 diff --git a/sim/testsuite/d10v/t-mulxu.s b/sim/testsuite/d10v/t-mulxu.s new file mode 100644 index 0000000..b0c14b6 --- /dev/null +++ b/sim/testsuite/d10v/t-mulxu.s @@ -0,0 +1,32 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_mulxu1: + MULXU a1, r9, r8 + checkacc2 1 a1 0x00 0x8000 0x7FFF + + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_mulxu2: + MULXU a1, r9, r8 + checkacc2 2 a1 0x01 0x0000 0xFFFE + + exit0 diff --git a/sim/testsuite/d10v/t-mvtac.s b/sim/testsuite/d10v/t-mvtac.s new file mode 100644 index 0000000..dc73403 --- /dev/null +++ b/sim/testsuite/d10v/t-mvtac.s @@ -0,0 +1,23 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + ldi r8, 0xbeef + mvtaclo r8, a0 + checkacc2 1 a0 0xff 0xffff 0xbeef + + mvtacg r0, a0 + checkacc2 2 a0 0x00 0xffff 0xbeef + + ldi r8, 0xdead + mvtachi r8, a0 + checkacc2 3 a0 0xff 0xdead 0xbeef + + loadacc2 a1 0xfe 0xbeef 0xdead + checkacc2 4 a1 0xfe 0xbeef 0xdead + + exit0 diff --git a/sim/testsuite/d10v/t-mvtc.s b/sim/testsuite/d10v/t-mvtc.s new file mode 100644 index 0000000..0b463ae --- /dev/null +++ b/sim/testsuite/d10v/t-mvtc.s @@ -0,0 +1,134 @@ +# mach: all +# output: +# sim: --environment operating +# as: -W + +.include "t-macros.i" + + start + +;;; Try out each bit in the PSW + + loadpsw2 PSW_SM + checkpsw2 1 PSW_SM + + loadpsw2 PSW_01 + checkpsw2 2 0 ;; PSW_01 + + loadpsw2 PSW_EA + checkpsw2 3 PSW_EA + + loadpsw2 PSW_DB + checkpsw2 4 PSW_DB + + loadpsw2 PSW_DM + checkpsw2 5 0 ;; PSW_DM + + loadpsw2 PSW_IE + checkpsw2 6 PSW_IE + + loadpsw2 PSW_RP + checkpsw2 7 PSW_RP + + loadpsw2 PSW_MD + checkpsw2 8 PSW_MD + + loadpsw2 PSW_FX|PSW_ST + checkpsw2 9 PSW_FX|PSW_ST + + ;; loadpsw2 PSW_ST + ;; checkpsw2 10 + + loadpsw2 PSW_10 + checkpsw2 11 0 ;; PSW_10 + + loadpsw2 PSW_11 + checkpsw2 12 0 ;; PSW_11 + + loadpsw2 PSW_F0 + checkpsw2 13 PSW_F0 + + loadpsw2 PSW_F1 + checkpsw2 14 PSW_F1 + + loadpsw2 PSW_14 + checkpsw2 15 0 ;; PSW_14 + + loadpsw2 PSW_C + checkpsw2 16 PSW_C + + +;;; Check that bit 0 (LSB) of the MOD_E & MOD_S registers are stuck at ZERO. + + ldi r6, #0xdead + mvtc r6, cr10 + ldi r6, #0xbeef + mvtc r6, cr11 + + mvfc r7, cr10 + check 17 r7 0xdeac + mvfc r7, cr11 + check 18 r7 0xbeee + +;;; Check that certain bits of the PSW, DPSW and BPSW are hardwired to zero + +psw_ffff: + ldi r6, 0xffff + mvtc r6, psw + mvfc r7, psw + check 18 r7 0xb7cd + +bpsw_ffff: + ldi r6, 0xffff + mvtc r6, bpsw + mvfc r7, bpsw + check 18 r7 0xb7cd + +dpsw_ffff: + ldi r6, 0xffff + mvtc r6, dpsw + mvfc r7, dpsw + check 18 r7 0xb7cd + +;;; Another check. Very similar + +psw_dfff: + ldi r6, 0xdfff + mvtc r6, psw + mvfc r7, psw + check 18 r7 0x97cd + +bpsw_dfff: + ldi r6, 0xdfff + mvtc r6, bpsw + mvfc r7, bpsw + check 18 r7 0x97cd + +dpsw_dfff: + ldi r6, 0xdfff + mvtc r6, dpsw + mvfc r7, dpsw + check 18 r7 0x97cd + +;;; And again. + +psw_8005: + ldi r6, 0x8005 + mvtc r6, psw + mvfc r7, psw + check 18 r7 0x8005 + +bpsw_8005: + ldi r6, 0x8005 + mvtc r6, bpsw + mvfc r7, bpsw + check 18 r7 0x8005 + +dpsw_8005: + ldi r6, 0x8005 + mvtc r6, dpsw + mvfc r7, dpsw + check 18 r7 0x8005 + + + exit0 diff --git a/sim/testsuite/d10v/t-rac.s b/sim/testsuite/d10v/t-rac.s new file mode 100644 index 0000000..a452299 --- /dev/null +++ b/sim/testsuite/d10v/t-rac.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + ;; clear FX + loadpsw2 0x8004 + loadacc2 a0 0x80 0x0000 0x0000 + loadacc2 a1 0x00 0x0000 0x5000 + load r10 0x0123 + load r11 0x4567 +test_rac1: + RAC r10, a0, #-2 + checkpsw2 1 0x8008 + check2w2 2 r10 0x8000 0x0000 + + exit0 diff --git a/sim/testsuite/d10v/t-rachi.s b/sim/testsuite/d10v/t-rachi.s new file mode 100644 index 0000000..57589b5 --- /dev/null +++ b/sim/testsuite/d10v/t-rachi.s @@ -0,0 +1,32 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + loadacc2 a0 0x00 0x7FFF 0x8000 +test_rachi_1: + rachi r4, a0, 0 + check 1 r4 0x7FFF + + + loadacc2 a0 0xFF 0x8000 0x1000 +test_rachi_2: + rachi r4, a0, 0 + check 2 r4 0x8000 + + + loadacc2 a0 0x00 0x1000 0xA000 +test_rachi_3: + rachi r4, a0, 0 + check 3 r4 0x1001 + + + loadacc2 a0 0xFF 0xA000 0x7FFF +test_rachi_4: + rachi r4, a0, 0 + check 4 r4 0xa000 + + exit0 diff --git a/sim/testsuite/d10v/t-rdt.s b/sim/testsuite/d10v/t-rdt.s new file mode 100644 index 0000000..947da86 --- /dev/null +++ b/sim/testsuite/d10v/t-rdt.s @@ -0,0 +1,23 @@ +# mach: all +# output: +# sim: --environment operating +# as: -W + +.include "t-macros.i" + + start + + PSW_BITS = PSW_C|PSW_F0|PSW_F1 + + ldi r6, #success@word + mvtc r6, dpc + ldi r6, #PSW_BITS + mvtc r6, dpsw + +test_rdt: + RTD + exit47 + +success: + checkpsw2 1 PSW_BITS + exit0 diff --git a/sim/testsuite/d10v/t-rep.s b/sim/testsuite/d10v/t-rep.s new file mode 100644 index 0000000..433aff1 --- /dev/null +++ b/sim/testsuite/d10v/t-rep.s @@ -0,0 +1,49 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + + + ;; Check that the instruction @REP_E is executed when it + ;; is reached using a branch instruction + + ldi r2, 1 +test_rep_1: + rep r2, end_rep_1 + nop || nop + nop || nop + nop || nop + nop || nop + ldi r3, 46 + bra end_rep_1 + ldi r3, 42 +end_rep_1: + addi r3, 1 + + check 1 r3 47 + + + ;; Check that the loop is executed the correct number of times + + ldi r2, 10 + ldi r3, 0 + ldi r4, 0 +test_rep_2: + rep r2, end_rep_2 + nop || nop + nop || nop + nop || nop + nop || nop + nop || nop + addi r3, 1 +end_rep_2: + addi r4, 1 + + check 2 r3 10 + check 3 r4 10 + + exit0 diff --git a/sim/testsuite/d10v/t-rie-xx.s b/sim/testsuite/d10v/t-rie-xx.s new file mode 100644 index 0000000..fa6b4fc --- /dev/null +++ b/sim/testsuite/d10v/t-rie-xx.s @@ -0,0 +1,16 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_RIE&DMAP_MASK)+DMAP_BASE PSW_BITS test_rie_xx + +test_rie_xx: + .short 0xe120, 0x0000 ;; Example of RIE code + nop + exit47 diff --git a/sim/testsuite/d10v/t-rte.s b/sim/testsuite/d10v/t-rte.s new file mode 100644 index 0000000..392f118 --- /dev/null +++ b/sim/testsuite/d10v/t-rte.s @@ -0,0 +1,22 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = PSW_C|PSW_F0|PSW_F1 + + ldi r6, #success@word + mvtc r6, bpc + ldi r6, #PSW_BITS + mvtc r6, bpsw + +test_rte: + RTE + exit47 + +success: + checkpsw2 1 PSW_BITS + exit0 diff --git a/sim/testsuite/d10v/t-sac.s b/sim/testsuite/d10v/t-sac.s new file mode 100644 index 0000000..84c31d7 --- /dev/null +++ b/sim/testsuite/d10v/t-sac.s @@ -0,0 +1,27 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +test_sac_1: + loadacc2 a0 0x00 0xAFFF 0x0000 + sac r4, a0 + check 1 r4 0x7FFF + check 2 r5 0xFFFF + +test_sac_2: + loadacc2 a0 0xFF 0x7000 0x0000 + sac r4, a0 + check 3 r4 0x8000 + check 4 r5 0x0000 + +test_sac_3: + loadacc2 a0 0x00 0x1000 0xA000 + sac r4, a0 + check 5 r4 0x1000 + check 6 r5 0xA000 + + exit0 diff --git a/sim/testsuite/d10v/t-sachi.s b/sim/testsuite/d10v/t-sachi.s new file mode 100644 index 0000000..b9ed0e7 --- /dev/null +++ b/sim/testsuite/d10v/t-sachi.s @@ -0,0 +1,26 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +test_sachi_1: + loadacc2 a0 0x00 0xAFFF 0x0000 + sachi r4, a0 + check 1 r4 0x7FFF + + +test_sachi_2: + loadacc2 a0 0xFF 0x8000 0x1000 + sachi r4, a0 + check 2 r4 0x8000 + + +test_sachi_3: + loadacc2 a0 0x00 0x1000 0xA000 + sachi r4, a0 + check 3 r4 0x1000 + + exit0 diff --git a/sim/testsuite/d10v/t-sadd.s b/sim/testsuite/d10v/t-sadd.s new file mode 100644 index 0000000..fb463d9 --- /dev/null +++ b/sim/testsuite/d10v/t-sadd.s @@ -0,0 +1,42 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = PSW_FX|PSW_ST|PSW_SM + loadpsw2 PSW_BITS + + ;; Test normal sadd + + loadacc2 a0 0x00 0x7fff 0xffff + loadacc2 a1 0xff 0x8000 0x0000 + sadd a1, a0 + checkacc2 1 a0 0x00 0x7fff 0xffff + checkacc2 2 a1 0xff 0x8000 0x7fff + + ;; Test overflow + + loadacc2 a0 0x00 0x0000 0x0000 + loadacc2 a1 0x01 0x8000 0x0000 + sadd a1, a0 + checkacc2 3 a0 0x00 0x0000 0x0000 + checkacc2 4 a1 0x00 0x7fff 0xffff + + loadacc2 a0 0x00 0xffff 0xffff + loadacc2 a1 0x00 0xffff 0xffff + sadd a1, a0 + checkacc2 5 a1 0x00 0x7fff 0xffff + checkacc2 6 a0 0x00 0xffff 0xffff + + ;; Test underflow + + loadacc2 a0 0x00 0x0000 0x0000 + loadacc2 a1 0x80 0x8000 0x0000 + sadd a1, a0 + checkacc2 7 a0 0x00 0x0000 0x0000 + checkacc2 8 a1 0xff 0x8000 0x0000 + + exit0 diff --git a/sim/testsuite/d10v/t-slae.s b/sim/testsuite/d10v/t-slae.s new file mode 100644 index 0000000..8236fa2 --- /dev/null +++ b/sim/testsuite/d10v/t-slae.s @@ -0,0 +1,43 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +test_slae_1: + loadpsw2 PSW_ST|PSW_FX + loadacc2 a0 0x00 0x0AFF 0xF000 + ldi r0, 4 + slae a0, r0 + checkacc2 1 a0 0x00 0x7FFF 0xFFFF + +test_slae_2: + loadpsw2 PSW_ST|PSW_FX + loadacc2 a0 0xFF 0xF700 0x1000 + ldi r0, 4 + slae a0, r0 + checkacc2 2 a0 0xFF 0x8000 0x0000 + +test_slae_3: + loadpsw2 PSW_ST|PSW_FX + loadacc2 a0 0x00 0x0010 0xA000 + ldi r0, 4 + slae a0, r0 + checkacc2 3 a0 0x00 0x010A 0x0000 + +test_slae_4: + loadpsw2 0 + loadacc2 a0 0x00 0x0010 0xA000 + ldi r0, 4 + slae a0, r0 + checkacc2 4 a0 0x00 0x010A 0x0000 + +test_slae_5: + loadacc2 a0 0x00 0x0010 0xA000 + ldi r0, -4 + slae a0, r0 + checkacc2 4 a0 0x00 0x0001 0x0A00 + + exit0 diff --git a/sim/testsuite/d10v/t-sp.s b/sim/testsuite/d10v/t-sp.s new file mode 100644 index 0000000..df443b9 --- /dev/null +++ b/sim/testsuite/d10v/t-sp.s @@ -0,0 +1,21 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +;;; Read/Write values to SPU/SPI + + loadpsw2 0 + ldi sp, 0xdead + loadpsw2 PSW_SM + ldi sp, 0xbeef + + loadpsw2 0 + check 1 sp 0xdead + loadpsw2 PSW_SM + check 2 sp 0xbeef + + exit0 diff --git a/sim/testsuite/d10v/t-sub.s b/sim/testsuite/d10v/t-sub.s new file mode 100644 index 0000000..57b99e6 --- /dev/null +++ b/sim/testsuite/d10v/t-sub.s @@ -0,0 +1,46 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +;; The d10v implements negated addition for subtraction + + .macro check_sub s x y r c + ;; clear carry + ldi r6,#0x8004 + mvtc r6,cr0 + ;; subtract + ldi r10,#\x + ldi r11,#\y + sub r10, r11 + ;; verify result + ldi r12, #\r + cmpeq r10, r12 + brf0t 1f + ldi r6, 1 + ldi r2, #\s + trap 15 +1: + ;; verify carry + mvfc r6, cr0 + and3 r6, r6, #1 + cmpeqi r6, #\c + brf0t 1f + ldi r6, 1 + ldi r2, #\s + trap 15 +1: + .endm + +check_sub 1 0x0000 0x0000 0x0000 1 +check_sub 2 0x0000 0x0001 0xffff 0 +check_sub 3 0x0001 0x0000 0x0001 1 +check_sub 4 0x0001 0x0001 0x0000 1 +check_sub 5 0x0000 0x8000 0x8000 0 +check_sub 6 0x8000 0x0001 0x7fff 1 +check_sub 7 0x7fff 0x7fff 0x0000 1 + + exit0 diff --git a/sim/testsuite/d10v/t-sub2w.s b/sim/testsuite/d10v/t-sub2w.s new file mode 100644 index 0000000..5e8daee --- /dev/null +++ b/sim/testsuite/d10v/t-sub2w.s @@ -0,0 +1,61 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +;; The d10v implements negated addition for subtraction + + .macro check_sub2w s x y r c v + + ;; clear carry + ldi r6,#0x8004 + mvtc r6,cr0 + + ;; load opnds + ld2w r6, @(1f,r0) + ld2w r8, @(2f,r0) + .data +1: .long \x +2: .long \y + .text + + ;; subtract + SUB2W r6, r8 + + ;; verify result + ld2w r10, @(1f,r0) + .data +1: .long \r + .text + cmpeq r6, r10 + brf0f 2f + cmpeq r7, r11 + brf0t 3f +2: ldi r4, 1 + ldi r0, \s + trap 15 +3: + + ;; verify carry + mvfc r6, cr0 + and3 r6, r6, #1 + cmpeqi r6, #\c + brf0t 1f + ldi r4, 1 + ldi r0, \s + trap 15 +1: + .endm + +check_sub2w 1 0x00000000 0x00000000 0x00000000 1 0 +check_sub2w 2 0x00000000 0x00000001 0xffffffff 0 0 +check_sub2w 3 0x00000001 0x00000000 0x00000001 1 0 +check_sub2w 3 0x00000001 0x00000001 0x00000000 1 0 +check_sub2w 5 0x00000000 0x80000000 0x80000000 0 1 +check_sub2w 6 0x80000000 0x00000001 0x7fffffff 1 1 +check_sub2w 7 0x7fffffff 0x7fffffff 0x00000000 1 0 + + exit0 diff --git a/sim/testsuite/d10v/t-subi.s b/sim/testsuite/d10v/t-subi.s new file mode 100644 index 0000000..dd4b2be --- /dev/null +++ b/sim/testsuite/d10v/t-subi.s @@ -0,0 +1,43 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +;; The d10v implements negated addition for subtraction + + .macro check_subi s x y r c v + ;; clear carry + ldi r6,#0x8004 + mvtc r6,cr0 + ;; subtract + ldi r10,#\x + SUBI r10,#\y + ;; verify result + ldi r11, #\r + cmpeq r10, r11 + brf0t 1f + ldi r6, 1 + ldi r2, \s + trap 15 +1: + ;; verify carry + mvfc r6, cr0 + and3 r6, r6, #1 + cmpeqi r6, #\c + brf0t 1f + ldi r6, 1 + ldi r2, \s + trap 15 +1: + .endm + + check_subi 1 0000 0x0000 0xfff0 00 ;; 0 - 0x10 + check_subi 2 0x0000 0x0001 0xffff 0 0 + check_subi 3 0x0001 0x0000 0xfff1 0 0 + check_subi 4 0x0001 0x0001 0x0000 1 0 + check_subi 5 0x8000 0x0001 0x7fff 1 1 + + exit0 diff --git a/sim/testsuite/d10v/t-trap.s b/sim/testsuite/d10v/t-trap.s new file mode 100644 index 0000000..7e5336c --- /dev/null +++ b/sim/testsuite/d10v/t-trap.s @@ -0,0 +1,10 @@ +# mach: all +# status: 47 +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + exit47 diff --git a/sim/testsuite/frv/ChangeLog b/sim/testsuite/frv/ChangeLog new file mode 100644 index 0000000..66f027e --- /dev/null +++ b/sim/testsuite/frv/ChangeLog @@ -0,0 +1,82 @@ +2021-01-15 Mike Frysinger + + * cache.ms: New testcase from ../../frv-elf/. + * exit47.ms, grloop.ms, hello.ms: Likewise. + * misc.exp: New file. + +2004-03-01 Richard Sandiford + + * allinsn.exp (all_machs): Add fr405 and fr450. + * fr400/allinsn.exp (all_machs): Likewise. + * fr400/addss.cgs (mach): Change to "fr405 fr450". + * fr400/scutss.cgs (mach): Likewise. + * fr400/slass.cgs (mach): Likewise. + * fr400/smass.cgs (mach): Likewise. + * fr400/smsss.cgs (mach): Likewise. + * fr400/smu.cgs (mach): Likewise. + * fr400/subss.cgs (mach): Likewise. + * interrupts/fp_exception.cgs: Replace fmadds with .word. + * interrupts/fp_exception-fr550.cgs: Likewise. + * mqlclrhs.cgs: New test. + * mqlmths.cgs: New test. + * mqsllhi.cgs: New test. + * mqsrahi.cgs: New test. + +2004-03-01 Richard Sandiford + + * fr400/scutss.cgs: Fix tests to account for rounding. + Add some new ones. + +2004-03-01 Richard Sandiford + + * {rstb,rsth,rst,rstd,rstq}.cgs: Delete. + * {rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete. + +2003-10-10 Dave Brolley + + * testutils.inc (or_gr_immed): New macro. + * fp_exception-fr550.cgs: Write insns using + unaligned registers into the program in order to + cause the required exceptions. + * fp_exception.cgs: Ditto. + * regalign.cgs: Ditto. + +2003-10-06 Dave Brolley + + * fr550: New subdirectory. + * fr400/*.cgs: Add fr550 as appropriate. + * fr500/*.cgs: Add fr550 as appropriate. + * interrupts/*.cgs: Add fr550 as appropriate. + * interrupts/*-fr550.cgs: New test cases for fr550. + +2003-09-19 Michael Snyder + + * nldqi.cgs: Remove. This insn was never implemented + by Fujitsu. + +2003-09-19 Dave Brolley + + * rstqf.cgs: Use nldq instead of nldqi. + * rstq.cgs: Use nldq instead of nldqi. + +2003-09-11 Michael Snyder + + * movgs.cgs: Change lcr to spr[273], + which according to the comments seems to be the intent. + +2003-09-09 Dave Brolley + + * maddaccs.cgs: move to fr400 subdirectory. + * msubaccs.cgs: move to fr400 subdirectory. + * masaccs.cgs: move to fr400 subdirectory. + +2003-09-03 Michael Snyder + + * fr500/mclracc.cgs: Change mach to 'all', to be + consistent with other tests in the directory. + +2003-09-03 Michael Snyder + + * interrupts/Ipipe-fr400.cgs: New file. + * interrupts/Ipipe-fr500.cgs: New file. + * interrupts/Ipipe.cgs: Remove (replaced by above). diff --git a/sim/testsuite/frv/add.cgs b/sim/testsuite/frv/add.cgs new file mode 100644 index 0000000..54fdfd5 --- /dev/null +++ b/sim/testsuite/frv/add.cgs @@ -0,0 +1,23 @@ +# frv testcase for add $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + add gr7,gr8,gr8 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + add gr7,gr8,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + + add gr8,gr8,gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/frv/add.pcgs b/sim/testsuite/frv/add.pcgs new file mode 100644 index 0000000..cf49976 --- /dev/null +++ b/sim/testsuite/frv/add.pcgs @@ -0,0 +1,25 @@ +# frv parallel testcase for add $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + add.p gr7,gr8,gr8 + add gr7,gr8,gr9 + add.p gr7,gr8,gr10 + add gr7,gr8,gr11 + add.p gr7,gr8,gr12 + add gr7,gr8,gr13 + test_gr_immed 3,gr8 + test_gr_immed 3,gr9 + test_gr_immed 4,gr10 + test_gr_immed 4,gr11 + test_gr_immed 4,gr12 + test_gr_immed 4,gr13 + + pass diff --git a/sim/testsuite/frv/addcc.cgs b/sim/testsuite/frv/addcc.cgs new file mode 100644 index 0000000..d2e33d8 --- /dev/null +++ b/sim/testsuite/frv/addcc.cgs @@ -0,0 +1,36 @@ +# frv testcase for addcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addcc +addcc: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + addcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + addcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,0 ; Set mask opposite of expected + addcc gr8,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + addcc gr8,gr8,gr8,icc0; test zero, carry and overflow bits + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + + pass diff --git a/sim/testsuite/frv/addi.cgs b/sim/testsuite/frv/addi.cgs new file mode 100644 index 0000000..3d60c5d --- /dev/null +++ b/sim/testsuite/frv/addi.cgs @@ -0,0 +1,25 @@ +# frv testcase for addi $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global addi +addi: + set_gr_immed 4,gr8 + addi gr8,0,gr8 + test_gr_immed 4,gr8 + addi gr8,1,gr8 + test_gr_immed 5,gr8 + addi gr8,15,gr8 + test_gr_immed 20,gr8 + set_gr_limmed 0x7fff,0xffff,gr8 + addi gr8,1,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + addi gr8,0x7ff,gr8 + test_gr_limmed 0x8000,0x07ff,gr8 + addi gr8,-2048,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + + pass diff --git a/sim/testsuite/frv/addicc.cgs b/sim/testsuite/frv/addicc.cgs new file mode 100644 index 0000000..6f2a197 --- /dev/null +++ b/sim/testsuite/frv/addicc.cgs @@ -0,0 +1,30 @@ +# frv testcase for addicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addicc +addicc: + ; Test add $u4Ri + set_gr_immed 4,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + addicc gr8,0,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 4,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + addicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 5,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + addicc gr8,15,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 20,gr8 + set_gr_limmed 0x7fff,0xffff,gr8 ; test neg and overflow bits + set_icc 0x05,0 ; Set mask opposite of expected + addicc gr8,1,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + pass diff --git a/sim/testsuite/frv/addx.cgs b/sim/testsuite/frv/addx.cgs new file mode 100644 index 0000000..259a694 --- /dev/null +++ b/sim/testsuite/frv/addx.cgs @@ -0,0 +1,49 @@ +# frv testcase for addx $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addx +addx: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry bit is off + addx gr7,gr8,gr8,icc0 + test_icc 1 1 1 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x04,0 ; Make sure carry bit is off + addx gr7,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,0 ; Make sure carry bit is off + addx gr8,gr8,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Make sure carry bit is on + addx gr7,gr8,gr8,icc0 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 0,gr8 + set_icc 0x05,0 ; Make sure carry bit is on + addx gr7,gr8,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_icc 0x0b,0 ; Make sure carry bit is on + addx gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/frv/addxcc.cgs b/sim/testsuite/frv/addxcc.cgs new file mode 100644 index 0000000..230c047 --- /dev/null +++ b/sim/testsuite/frv/addxcc.cgs @@ -0,0 +1,49 @@ +# frv testcase for addxcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addxcc +addxcc: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry bit is off + addxcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x04,0 ; Make sure carry bit is off + addxcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,0 ; Make sure carry bit is off + addxcc gr8,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Make sure carry bit is on + addxcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 0,gr8 + set_icc 0x05,0 ; Make sure carry bit is on + addxcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_icc 0x0b,0 ; Make sure carry bit is on + addxcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/frv/addxi.cgs b/sim/testsuite/frv/addxi.cgs new file mode 100644 index 0000000..c36272a --- /dev/null +++ b/sim/testsuite/frv/addxi.cgs @@ -0,0 +1,46 @@ +# frv testcase for addxi $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addxi +addxi: + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry bit is off + addxi gr8,1,gr8,icc0 + test_icc 1 1 1 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x04,0 ; Make sure carry bit is off + addxi gr8,1,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xffff,0xff00,gr8 + set_icc 0x08,0 ; Make sure carry bit is off + addxi gr8,0x100,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Make sure carry bit is on + addxi gr8,1,gr8,icc0 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x05,0 ; Make sure carry bit is on + addxi gr8,0,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xffff,0xfeff,gr8 + set_icc 0x0b,0 ; Make sure carry bit is on + addxi gr8,0x100,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/frv/addxicc.cgs b/sim/testsuite/frv/addxicc.cgs new file mode 100644 index 0000000..831fec3 --- /dev/null +++ b/sim/testsuite/frv/addxicc.cgs @@ -0,0 +1,46 @@ +# frv testcase for addxicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addxicc +addxicc: + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry bit is off + addxicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x04,0 ; Make sure carry bit is off + addxicc gr8,1,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xffff,0xff00,gr8 + set_icc 0x08,0 ; Make sure carry bit is off + addxicc gr8,0x100,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Make sure carry bit is on + addxicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x05,0 ; Make sure carry bit is on + addxicc gr8,0,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xffff,0xfeff,gr8 + set_icc 0x0b,0 ; Make sure carry bit is on + addxicc gr8,0x100,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/frv/allinsn.exp b/sim/testsuite/frv/allinsn.exp new file mode 100644 index 0000000..b7f9fe2 --- /dev/null +++ b/sim/testsuite/frv/allinsn.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500 fr550 fr400 fr405 fr450" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/frv/and.cgs b/sim/testsuite/frv/and.cgs new file mode 100644 index 0000000..a1773f1 --- /dev/null +++ b/sim/testsuite/frv/and.cgs @@ -0,0 +1,29 @@ +# frv testcase for and $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global and +and: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + and gr7,gr8,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + and gr7,gr8,gr8 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + and gr7,gr8,gr8 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x0000,0xaaaa,gr8 + + pass diff --git a/sim/testsuite/frv/andcc.cgs b/sim/testsuite/frv/andcc.cgs new file mode 100644 index 0000000..a2a04d2 --- /dev/null +++ b/sim/testsuite/frv/andcc.cgs @@ -0,0 +1,29 @@ +# frv testcase for andcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global andcc +andcc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + andcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + andcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + andcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x0000,0xaaaa,gr8 + + pass diff --git a/sim/testsuite/frv/andcr.cgs b/sim/testsuite/frv/andcr.cgs new file mode 100644 index 0000000..9fbbaff --- /dev/null +++ b/sim/testsuite/frv/andcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for andcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global andcr +andcr: + set_spr_immed 0x1b1b,cccr + andcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc5,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc5,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc4,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc4,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc4,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + andcr cc4,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/andi.cgs b/sim/testsuite/frv/andi.cgs new file mode 100644 index 0000000..e9fdf75 --- /dev/null +++ b/sim/testsuite/frv/andi.cgs @@ -0,0 +1,26 @@ +# frv testcase for andi $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global andi +andi: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x0b,0 ; Set mask opposite of expected + andi gr7,0x555,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x04,0 ; Set mask opposite of expected + andi gr7,-2048,gr8 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xaaaa,0xa800,gr8 + + set_icc 0x0d,0 ; Set mask opposite of expected + andi gr7,-1,gr8 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + pass diff --git a/sim/testsuite/frv/andicc.cgs b/sim/testsuite/frv/andicc.cgs new file mode 100644 index 0000000..6508059 --- /dev/null +++ b/sim/testsuite/frv/andicc.cgs @@ -0,0 +1,26 @@ +# frv testcase for andicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global andicc +andicc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x0b,0 ; Set mask opposite of expected + andicc gr7,0x155,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x04,0 ; Set mask opposite of expected + andicc gr7,-512,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xaaaa,0xaa00,gr8 + + set_icc 0x05,0 ; Set mask opposite of expected + andicc gr7,-1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + pass diff --git a/sim/testsuite/frv/andncr.cgs b/sim/testsuite/frv/andncr.cgs new file mode 100644 index 0000000..31fd1f7 --- /dev/null +++ b/sim/testsuite/frv/andncr.cgs @@ -0,0 +1,59 @@ +# frv testcase for andncr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global andncr +andncr: + set_spr_immed 0x1b1b,cccr + andncr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc5,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + andncr cc5,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + andncr cc4,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc4,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc4,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc4,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/bar.cgs b/sim/testsuite/frv/bar.cgs new file mode 100644 index 0000000..df6a9ca --- /dev/null +++ b/sim/testsuite/frv/bar.cgs @@ -0,0 +1,12 @@ +# frv testcase for bar +# mach: all + + .include "testutils.inc" + + start + + .global bar +bar: + bar + + pass diff --git a/sim/testsuite/frv/bc.cgs b/sim/testsuite/frv/bc.cgs new file mode 100644 index 0000000..a5c612c --- /dev/null +++ b/sim/testsuite/frv/bc.cgs @@ -0,0 +1,61 @@ +# frv testcase for bc $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bc +bc: + set_icc 0x0 0 + bc icc0,0,bad + set_icc 0x1 1 + bc icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bc icc2,2,bad + set_icc 0x3 3 + bc icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bc icc0,0,bad + set_icc 0x5 1 + bc icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bc icc2,2,bad + set_icc 0x7 3 + bc icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + bc icc0,0,bad + set_icc 0x9 1 + bc icc1,1,oka + fail +oka: + set_icc 0xa 2 + bc icc2,2,bad + set_icc 0xb 3 + bc icc3,3,okc + fail +okc: + set_icc 0xc 0 + bc icc0,0,bad + set_icc 0xd 1 + bc icc1,1,oke + fail +oke: + set_icc 0xe 2 + bc icc2,2,bad + set_icc 0xf 3 + bc icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/bcclr.cgs b/sim/testsuite/frv/bcclr.cgs new file mode 100644 index 0000000..248be13 --- /dev/null +++ b/sim/testsuite/frv/bcclr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcclr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcclr +bcclr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcclr icc0,0,0 + + set_spr_addr ok2,lr + set_icc 0x1 1 + bcclr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bcclr icc2,0,2 + + set_spr_addr ok4,lr + set_icc 0x3 3 + bcclr icc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bcclr icc0,0,0 + + set_spr_addr ok6,lr + set_icc 0x5 1 + bcclr icc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bcclr icc2,0,2 + + set_spr_addr ok8,lr + set_icc 0x7 3 + bcclr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bcclr icc0,0,0 + + set_spr_addr oka,lr + set_icc 0x9 1 + bcclr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bcclr icc2,0,2 + + set_spr_addr okc,lr + set_icc 0xb 3 + bcclr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcclr icc0,0,0 + + set_spr_addr oke,lr + set_icc 0xd 1 + bcclr icc1,0,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bcclr icc2,0,2 + + set_spr_addr okg,lr + set_icc 0xf 3 + bcclr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcclr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcclr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcclr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcclr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcclr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcclr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcclr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcclr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcclr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcclr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bcclr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcclr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcclr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcclr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcclr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcclr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcclr icc0,1,0 + + set_icc 0x1 1 + bcclr icc1,1,1 + + set_icc 0x2 2 + bcclr icc2,1,2 + + set_icc 0x3 3 + bcclr icc3,1,3 + + set_icc 0x4 0 + bcclr icc0,1,0 + + set_icc 0x5 1 + bcclr icc1,1,1 + + set_icc 0x6 2 + bcclr icc2,1,2 + + set_icc 0x7 3 + bcclr icc3,1,3 + + set_icc 0x8 0 + bcclr icc0,1,0 + + set_icc 0x9 1 + bcclr icc1,1,1 + + set_icc 0xa 2 + bcclr icc2,1,2 + + set_icc 0xb 3 + bcclr icc3,1,3 + + set_icc 0xc 0 + bcclr icc0,1,0 + + set_icc 0xd 1 + bcclr icc1,1,1 + + set_icc 0xe 2 + bcclr icc2,1,2 + + set_icc 0xf 3 + bcclr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcclr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bceqlr.cgs b/sim/testsuite/frv/bceqlr.cgs new file mode 100644 index 0000000..bacabf4 --- /dev/null +++ b/sim/testsuite/frv/bceqlr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bceqlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bceqlr +bceqlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bceqlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bceqlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x2 2 + bceqlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bceqlr icc3,0,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bceqlr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bceqlr icc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bceqlr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bceqlr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bceqlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bceqlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xa 2 + bceqlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bceqlr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bceqlr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bceqlr icc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bceqlr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bceqlr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bceqlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bceqlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bceqlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bceqlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bceqlr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bceqlr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bceqlr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bceqlr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bceqlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bceqlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bceqlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bceqlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bceqlr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bceqlr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bceqlr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bceqlr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bceqlr icc0,1,0 + + set_icc 0x1 1 + bceqlr icc1,1,1 + + set_icc 0x2 2 + bceqlr icc2,1,2 + + set_icc 0x3 3 + bceqlr icc3,1,3 + + set_icc 0x4 0 + bceqlr icc0,1,0 + + set_icc 0x5 1 + bceqlr icc1,1,1 + + set_icc 0x6 2 + bceqlr icc2,1,2 + + set_icc 0x7 3 + bceqlr icc3,1,3 + + set_icc 0x8 0 + bceqlr icc0,1,0 + + set_icc 0x9 1 + bceqlr icc1,1,1 + + set_icc 0xa 2 + bceqlr icc2,1,2 + + set_icc 0xb 3 + bceqlr icc3,1,3 + + set_icc 0xc 0 + bceqlr icc0,1,0 + + set_icc 0xd 1 + bceqlr icc1,1,1 + + set_icc 0xe 2 + bceqlr icc2,1,2 + + set_icc 0xf 3 + bceqlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bceqlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bceqlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bceqlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bceqlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bceqlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bceqlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bceqlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bceqlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bceqlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bceqlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bceqlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bceqlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bceqlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bceqlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bceqlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bceqlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bcgelr.cgs b/sim/testsuite/frv/bcgelr.cgs new file mode 100644 index 0000000..72bd374 --- /dev/null +++ b/sim/testsuite/frv/bcgelr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcgelr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcgelr +bcgelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcgelr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcgelr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bcgelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bcgelr icc3,0,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bcgelr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bcgelr icc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bcgelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcgelr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x8 0 + bcgelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bcgelr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bcgelr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcgelr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcgelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcgelr icc1,0,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bcgelr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bcgelr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcgelr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcgelr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcgelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcgelr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcgelr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcgelr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcgelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcgelr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcgelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcgelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcgelr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcgelr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcgelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcgelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcgelr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcgelr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcgelr icc0,1,0 + + set_icc 0x1 1 + bcgelr icc1,1,1 + + set_icc 0x2 2 + bcgelr icc2,1,2 + + set_icc 0x3 3 + bcgelr icc3,1,3 + + set_icc 0x4 0 + bcgelr icc0,1,0 + + set_icc 0x5 1 + bcgelr icc1,1,1 + + set_icc 0x6 2 + bcgelr icc2,1,2 + + set_icc 0x7 3 + bcgelr icc3,1,3 + + set_icc 0x8 0 + bcgelr icc0,1,0 + + set_icc 0x9 1 + bcgelr icc1,1,1 + + set_icc 0xa 2 + bcgelr icc2,1,2 + + set_icc 0xb 3 + bcgelr icc3,1,3 + + set_icc 0xc 0 + bcgelr icc0,1,0 + + set_icc 0xd 1 + bcgelr icc1,1,1 + + set_icc 0xe 2 + bcgelr icc2,1,2 + + set_icc 0xf 3 + bcgelr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcgelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcgelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcgelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcgelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcgelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcgelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcgelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcgelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcgelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcgelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcgelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcgelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcgelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcgelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcgelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcgelr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bcgtlr.cgs b/sim/testsuite/frv/bcgtlr.cgs new file mode 100644 index 0000000..edffed8 --- /dev/null +++ b/sim/testsuite/frv/bcgtlr.cgs @@ -0,0 +1,284 @@ +# frv testcase for bcgtlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcgtlr +bcgtlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcgtlr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcgtlr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bcgtlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bcgtlr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bcgtlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcgtlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bcgtlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcgtlr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x8 0 + bcgtlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bcgtlr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bcgtlr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcgtlr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcgtlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcgtlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bcgtlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcgtlr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcgtlr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcgtlr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcgtlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcgtlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcgtlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcgtlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcgtlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcgtlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcgtlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcgtlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcgtlr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcgtlr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcgtlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcgtlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcgtlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcgtlr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcgtlr icc0,1,0 + + set_icc 0x1 1 + bcgtlr icc1,1,1 + + set_icc 0x2 2 + bcgtlr icc2,1,2 + + set_icc 0x3 3 + bcgtlr icc3,1,3 + + set_icc 0x4 0 + bcgtlr icc0,1,0 + + set_icc 0x5 1 + bcgtlr icc1,1,1 + + set_icc 0x6 2 + bcgtlr icc2,1,2 + + set_icc 0x7 3 + bcgtlr icc3,1,3 + + set_icc 0x8 0 + bcgtlr icc0,1,0 + + set_icc 0x9 1 + bcgtlr icc1,1,1 + + set_icc 0xa 2 + bcgtlr icc2,1,2 + + set_icc 0xb 3 + bcgtlr icc3,1,3 + + set_icc 0xc 0 + bcgtlr icc0,1,0 + + set_icc 0xd 1 + bcgtlr icc1,1,1 + + set_icc 0xe 2 + bcgtlr icc2,1,2 + + set_icc 0xf 3 + bcgtlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcgtlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcgtlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcgtlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcgtlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcgtlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcgtlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcgtlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcgtlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcgtlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcgtlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcgtlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcgtlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcgtlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcgtlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcgtlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcgtlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bchilr.cgs b/sim/testsuite/frv/bchilr.cgs new file mode 100644 index 0000000..ea7e2f4 --- /dev/null +++ b/sim/testsuite/frv/bchilr.cgs @@ -0,0 +1,284 @@ +# frv testcase for bchilr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bchilr +bchilr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bchilr icc0,0,0 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x1 1 + bchilr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bchilr icc2,0,2 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x3 3 + bchilr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bchilr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bchilr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bchilr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bchilr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bchilr icc0,0,0 + fail +ok9: + set_spr_addr bad,lr + set_icc 0x9 1 + bchilr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bchilr icc2,0,2 + fail +okb: + set_spr_addr bad,lr + set_icc 0xb 3 + bchilr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0xc 0 + bchilr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bchilr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bchilr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bchilr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bchilr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bchilr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bchilr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bchilr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bchilr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bchilr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bchilr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bchilr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bchilr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bchilr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bchilr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bchilr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bchilr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bchilr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bchilr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bchilr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bchilr icc0,1,0 + + set_icc 0x1 1 + bchilr icc1,1,1 + + set_icc 0x2 2 + bchilr icc2,1,2 + + set_icc 0x3 3 + bchilr icc3,1,3 + + set_icc 0x4 0 + bchilr icc0,1,0 + + set_icc 0x5 1 + bchilr icc1,1,1 + + set_icc 0x6 2 + bchilr icc2,1,2 + + set_icc 0x7 3 + bchilr icc3,1,3 + + set_icc 0x8 0 + bchilr icc0,1,0 + + set_icc 0x9 1 + bchilr icc1,1,1 + + set_icc 0xa 2 + bchilr icc2,1,2 + + set_icc 0xb 3 + bchilr icc3,1,3 + + set_icc 0xc 0 + bchilr icc0,1,0 + + set_icc 0xd 1 + bchilr icc1,1,1 + + set_icc 0xe 2 + bchilr icc2,1,2 + + set_icc 0xf 3 + bchilr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bchilr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bchilr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bchilr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bchilr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bchilr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bchilr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bchilr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bchilr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bchilr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bchilr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bchilr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bchilr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bchilr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bchilr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bchilr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bchilr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bclelr.cgs b/sim/testsuite/frv/bclelr.cgs new file mode 100644 index 0000000..6668c77 --- /dev/null +++ b/sim/testsuite/frv/bclelr.cgs @@ -0,0 +1,301 @@ +# frv testcase for bclelr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bclelr +bclelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bclelr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bclelr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bclelr icc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bclelr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bclelr icc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bclelr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bclelr icc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bclelr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bclelr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bclelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bclelr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bclelr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bclelr icc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bclelr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bclelr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bclelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bclelr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bclelr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bclelr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bclelr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bclelr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bclelr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bclelr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bclelr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bclelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bclelr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bclelr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bclelr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bclelr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bclelr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclelr icc0,1,0 + + set_icc 0x1 1 + bclelr icc1,1,1 + + set_icc 0x2 2 + bclelr icc2,1,2 + + set_icc 0x3 3 + bclelr icc3,1,3 + + set_icc 0x4 0 + bclelr icc0,1,0 + + set_icc 0x5 1 + bclelr icc1,1,1 + + set_icc 0x6 2 + bclelr icc2,1,2 + + set_icc 0x7 3 + bclelr icc3,1,3 + + set_icc 0x8 0 + bclelr icc0,1,0 + + set_icc 0x9 1 + bclelr icc1,1,1 + + set_icc 0xa 2 + bclelr icc2,1,2 + + set_icc 0xb 3 + bclelr icc3,1,3 + + set_icc 0xc 0 + bclelr icc0,1,0 + + set_icc 0xd 1 + bclelr icc1,1,1 + + set_icc 0xe 2 + bclelr icc2,1,2 + + set_icc 0xf 3 + bclelr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bclelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bclelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bclelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bclelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bclelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bclelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bclelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bclelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bclelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bclelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bclelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bclelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bclelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bclelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bclelr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bclr.cgs b/sim/testsuite/frv/bclr.cgs new file mode 100644 index 0000000..d36563b --- /dev/null +++ b/sim/testsuite/frv/bclr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bclr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bclr +bclr: + set_spr_addr bad,lr + set_icc 0x0 0 + bclr icc0,0 + + set_spr_addr ok2,lr + set_icc 0x1 1 + bclr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bclr icc2,2 + + set_spr_addr ok4,lr + set_icc 0x3 3 + bclr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bclr icc0,0 + + set_spr_addr ok6,lr + set_icc 0x5 1 + bclr icc1,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bclr icc2,2 + + set_spr_addr ok8,lr + set_icc 0x7 3 + bclr icc3,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bclr icc0,0 + + set_spr_addr oka,lr + set_icc 0x9 1 + bclr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bclr icc2,2 + + set_spr_addr okc,lr + set_icc 0xb 3 + bclr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bclr icc0,0 + + set_spr_addr oke,lr + set_icc 0xd 1 + bclr icc1,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bclr icc2,2 + + set_spr_addr okg,lr + set_icc 0xf 3 + bclr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/bclslr.cgs b/sim/testsuite/frv/bclslr.cgs new file mode 100644 index 0000000..37b91bc --- /dev/null +++ b/sim/testsuite/frv/bclslr.cgs @@ -0,0 +1,301 @@ +# frv testcase for bclslr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bclslr +bclslr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclslr icc0,0,0 + + set_spr_addr ok2,lr + set_icc 0x1 1 + bclslr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bclslr icc2,0,2 + + set_spr_addr ok4,lr + set_icc 0x3 3 + bclslr icc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bclslr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bclslr icc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bclslr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bclslr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bclslr icc0,0,0 + + set_spr_addr oka,lr + set_icc 0x9 1 + bclslr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bclslr icc2,0,2 + + set_spr_addr okc,lr + set_icc 0xb 3 + bclslr icc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bclslr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bclslr icc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bclslr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bclslr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclslr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bclslr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bclslr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bclslr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bclslr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bclslr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bclslr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bclslr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bclslr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bclslr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bclslr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bclslr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bclslr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bclslr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bclslr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bclslr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclslr icc0,1,0 + + set_icc 0x1 1 + bclslr icc1,1,1 + + set_icc 0x2 2 + bclslr icc2,1,2 + + set_icc 0x3 3 + bclslr icc3,1,3 + + set_icc 0x4 0 + bclslr icc0,1,0 + + set_icc 0x5 1 + bclslr icc1,1,1 + + set_icc 0x6 2 + bclslr icc2,1,2 + + set_icc 0x7 3 + bclslr icc3,1,3 + + set_icc 0x8 0 + bclslr icc0,1,0 + + set_icc 0x9 1 + bclslr icc1,1,1 + + set_icc 0xa 2 + bclslr icc2,1,2 + + set_icc 0xb 3 + bclslr icc3,1,3 + + set_icc 0xc 0 + bclslr icc0,1,0 + + set_icc 0xd 1 + bclslr icc1,1,1 + + set_icc 0xe 2 + bclslr icc2,1,2 + + set_icc 0xf 3 + bclslr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclslr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bclslr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bclslr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bclslr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bclslr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bclslr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bclslr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bclslr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bclslr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bclslr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bclslr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bclslr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bclslr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bclslr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bclslr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bclslr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bcltlr.cgs b/sim/testsuite/frv/bcltlr.cgs new file mode 100644 index 0000000..0ba6bfa --- /dev/null +++ b/sim/testsuite/frv/bcltlr.cgs @@ -0,0 +1,292 @@ +# frv testcase for bcltlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcltlr +bcltlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcltlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bcltlr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bcltlr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcltlr icc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bcltlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcltlr icc1,0,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bcltlr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bcltlr icc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bcltlr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcltlr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bcltlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bcltlr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bcltlr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bcltlr icc1,0,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bcltlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcltlr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcltlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bcltlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcltlr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcltlr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcltlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcltlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcltlr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcltlr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcltlr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcltlr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bcltlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bcltlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcltlr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcltlr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcltlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcltlr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcltlr icc0,1,0 + + set_icc 0x1 1 + bcltlr icc1,1,1 + + set_icc 0x2 2 + bcltlr icc2,1,2 + + set_icc 0x3 3 + bcltlr icc3,1,3 + + set_icc 0x4 0 + bcltlr icc0,1,0 + + set_icc 0x5 1 + bcltlr icc1,1,1 + + set_icc 0x6 2 + bcltlr icc2,1,2 + + set_icc 0x7 3 + bcltlr icc3,1,3 + + set_icc 0x8 0 + bcltlr icc0,1,0 + + set_icc 0x9 1 + bcltlr icc1,1,1 + + set_icc 0xa 2 + bcltlr icc2,1,2 + + set_icc 0xb 3 + bcltlr icc3,1,3 + + set_icc 0xc 0 + bcltlr icc0,1,0 + + set_icc 0xd 1 + bcltlr icc1,1,1 + + set_icc 0xe 2 + bcltlr icc2,1,2 + + set_icc 0xf 3 + bcltlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcltlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcltlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcltlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcltlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcltlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcltlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcltlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcltlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcltlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcltlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcltlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcltlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcltlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcltlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcltlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcltlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bcnclr.cgs b/sim/testsuite/frv/bcnclr.cgs new file mode 100644 index 0000000..51824a6 --- /dev/null +++ b/sim/testsuite/frv/bcnclr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcnclr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcnclr +bcnclr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcnclr icc0,0,0 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x1 1 + bcnclr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bcnclr icc2,0,2 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x3 3 + bcnclr icc3,0,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bcnclr icc0,0,0 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x5 1 + bcnclr icc1,0,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bcnclr icc2,0,2 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x7 3 + bcnclr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bcnclr icc0,0,0 + fail +ok9: + set_spr_addr bad,lr + set_icc 0x9 1 + bcnclr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bcnclr icc2,0,2 + fail +okb: + set_spr_addr bad,lr + set_icc 0xb 3 + bcnclr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bcnclr icc0,0,0 + fail +okd: + set_spr_addr bad,lr + set_icc 0xd 1 + bcnclr icc1,0,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bcnclr icc2,0,2 + fail +okf: + set_spr_addr bad,lr + set_icc 0xf 3 + bcnclr icc3,0,3 + + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcnclr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bcnclr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcnclr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcnclr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcnclr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcnclr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcnclr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcnclr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcnclr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcnclr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcnclr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bcnclr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcnclr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcnclr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcnclr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcnclr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnclr icc0,1,0 + + set_icc 0x1 1 + bcnclr icc1,1,1 + + set_icc 0x2 2 + bcnclr icc2,1,2 + + set_icc 0x3 3 + bcnclr icc3,1,3 + + set_icc 0x4 0 + bcnclr icc0,1,0 + + set_icc 0x5 1 + bcnclr icc1,1,1 + + set_icc 0x6 2 + bcnclr icc2,1,2 + + set_icc 0x7 3 + bcnclr icc3,1,3 + + set_icc 0x8 0 + bcnclr icc0,1,0 + + set_icc 0x9 1 + bcnclr icc1,1,1 + + set_icc 0xa 2 + bcnclr icc2,1,2 + + set_icc 0xb 3 + bcnclr icc3,1,3 + + set_icc 0xc 0 + bcnclr icc0,1,0 + + set_icc 0xd 1 + bcnclr icc1,1,1 + + set_icc 0xe 2 + bcnclr icc2,1,2 + + set_icc 0xf 3 + bcnclr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnclr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bcnelr.cgs b/sim/testsuite/frv/bcnelr.cgs new file mode 100644 index 0000000..55be2d3 --- /dev/null +++ b/sim/testsuite/frv/bcnelr.cgs @@ -0,0 +1,292 @@ +# frv testcase for bcnelr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcnelr +bcnelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcnelr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcnelr icc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bcnelr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcnelr icc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bcnelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcnelr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bcnelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcnelr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bcnelr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcnelr icc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bcnelr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcnelr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcnelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcnelr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bcnelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcnelr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcnelr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcnelr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcnelr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcnelr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcnelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcnelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcnelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcnelr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcnelr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcnelr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcnelr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcnelr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcnelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcnelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcnelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcnelr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnelr icc0,1,0 + + set_icc 0x1 1 + bcnelr icc1,1,1 + + set_icc 0x2 2 + bcnelr icc2,1,2 + + set_icc 0x3 3 + bcnelr icc3,1,3 + + set_icc 0x4 0 + bcnelr icc0,1,0 + + set_icc 0x5 1 + bcnelr icc1,1,1 + + set_icc 0x6 2 + bcnelr icc2,1,2 + + set_icc 0x7 3 + bcnelr icc3,1,3 + + set_icc 0x8 0 + bcnelr icc0,1,0 + + set_icc 0x9 1 + bcnelr icc1,1,1 + + set_icc 0xa 2 + bcnelr icc2,1,2 + + set_icc 0xb 3 + bcnelr icc3,1,3 + + set_icc 0xc 0 + bcnelr icc0,1,0 + + set_icc 0xd 1 + bcnelr icc1,1,1 + + set_icc 0xe 2 + bcnelr icc2,1,2 + + set_icc 0xf 3 + bcnelr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnelr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bcnlr.cgs b/sim/testsuite/frv/bcnlr.cgs new file mode 100644 index 0000000..8ddfcaa --- /dev/null +++ b/sim/testsuite/frv/bcnlr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcnlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcnlr +bcnlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bcnlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x2 2 + bcnlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bcnlr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bcnlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcnlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bcnlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcnlr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bcnlr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcnlr icc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bcnlr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcnlr icc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bcnlr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bcnlr icc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bcnlr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bcnlr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bcnlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcnlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcnlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcnlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcnlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcnlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcnlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcnlr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcnlr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcnlr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcnlr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcnlr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcnlr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcnlr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcnlr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnlr icc0,1,0 + + set_icc 0x1 1 + bcnlr icc1,1,1 + + set_icc 0x2 2 + bcnlr icc2,1,2 + + set_icc 0x3 3 + bcnlr icc3,1,3 + + set_icc 0x4 0 + bcnlr icc0,1,0 + + set_icc 0x5 1 + bcnlr icc1,1,1 + + set_icc 0x6 2 + bcnlr icc2,1,2 + + set_icc 0x7 3 + bcnlr icc3,1,3 + + set_icc 0x8 0 + bcnlr icc0,1,0 + + set_icc 0x9 1 + bcnlr icc1,1,1 + + set_icc 0xa 2 + bcnlr icc2,1,2 + + set_icc 0xb 3 + bcnlr icc3,1,3 + + set_icc 0xc 0 + bcnlr icc0,1,0 + + set_icc 0xd 1 + bcnlr icc1,1,1 + + set_icc 0xe 2 + bcnlr icc2,1,2 + + set_icc 0xf 3 + bcnlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bcnolr.cgs b/sim/testsuite/frv/bcnolr.cgs new file mode 100644 index 0000000..04f0b8d --- /dev/null +++ b/sim/testsuite/frv/bcnolr.cgs @@ -0,0 +1,246 @@ +# frv testcase for bcnolr +# mach: all + + .include "testutils.inc" + + start + + .global bcnolr +bcnolr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnolr + + set_icc 0x1 1 + bcnolr + + set_icc 0x2 2 + bcnolr + + set_icc 0x3 3 + bcnolr + + set_icc 0x4 0 + bcnolr + + set_icc 0x5 1 + bcnolr + + set_icc 0x6 2 + bcnolr + + set_icc 0x7 3 + bcnolr + + set_icc 0x8 0 + bcnolr + + set_icc 0x9 1 + bcnolr + + set_icc 0xa 2 + bcnolr + + set_icc 0xb 3 + bcnolr + + set_icc 0xc 0 + bcnolr + + set_icc 0xd 1 + bcnolr + + set_icc 0xe 2 + bcnolr + + set_icc 0xf 3 + bcnolr + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnolr + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnolr + + set_icc 0x1 1 + bcnolr + + set_icc 0x2 2 + bcnolr + + set_icc 0x3 3 + bcnolr + + set_icc 0x4 0 + bcnolr + + set_icc 0x5 1 + bcnolr + + set_icc 0x6 2 + bcnolr + + set_icc 0x7 3 + bcnolr + + set_icc 0x8 0 + bcnolr + + set_icc 0x9 1 + bcnolr + + set_icc 0xa 2 + bcnolr + + set_icc 0xb 3 + bcnolr + + set_icc 0xc 0 + bcnolr + + set_icc 0xd 1 + bcnolr + + set_icc 0xe 2 + bcnolr + + set_icc 0xf 3 + bcnolr + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnolr + + pass +bad: + fail diff --git a/sim/testsuite/frv/bcnvlr.cgs b/sim/testsuite/frv/bcnvlr.cgs new file mode 100644 index 0000000..2451557 --- /dev/null +++ b/sim/testsuite/frv/bcnvlr.cgs @@ -0,0 +1,292 @@ +# frv testcase for bcnvlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcnvlr +bcnvlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcnvlr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcnvlr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bcnvlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bcnvlr icc3,0,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bcnvlr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bcnvlr icc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bcnvlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcnvlr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bcnvlr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcnvlr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bcnvlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bcnvlr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bcnvlr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bcnvlr icc1,0,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bcnvlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcnvlr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcnvlr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcnvlr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcnvlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcnvlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcnvlr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcnvlr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcnvlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcnvlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcnvlr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcnvlr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bcnvlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bcnvlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcnvlr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcnvlr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcnvlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcnvlr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnvlr icc0,1,0 + + set_icc 0x1 1 + bcnvlr icc1,1,1 + + set_icc 0x2 2 + bcnvlr icc2,1,2 + + set_icc 0x3 3 + bcnvlr icc3,1,3 + + set_icc 0x4 0 + bcnvlr icc0,1,0 + + set_icc 0x5 1 + bcnvlr icc1,1,1 + + set_icc 0x6 2 + bcnvlr icc2,1,2 + + set_icc 0x7 3 + bcnvlr icc3,1,3 + + set_icc 0x8 0 + bcnvlr icc0,1,0 + + set_icc 0x9 1 + bcnvlr icc1,1,1 + + set_icc 0xa 2 + bcnvlr icc2,1,2 + + set_icc 0xb 3 + bcnvlr icc3,1,3 + + set_icc 0xc 0 + bcnvlr icc0,1,0 + + set_icc 0xd 1 + bcnvlr icc1,1,1 + + set_icc 0xe 2 + bcnvlr icc2,1,2 + + set_icc 0xf 3 + bcnvlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnvlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bcplr.cgs b/sim/testsuite/frv/bcplr.cgs new file mode 100644 index 0000000..fef3ccb --- /dev/null +++ b/sim/testsuite/frv/bcplr.cgs @@ -0,0 +1,292 @@ +# frv testcase for bcplr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcplr +bcplr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcplr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcplr icc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bcplr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcplr icc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bcplr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bcplr icc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bcplr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bcplr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bcplr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bcplr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xa 2 + bcplr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bcplr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0xc 0 + bcplr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcplr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bcplr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcplr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcplr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcplr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcplr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcplr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcplr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcplr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcplr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcplr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcplr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcplr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bcplr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bcplr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcplr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcplr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcplr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcplr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcplr icc0,1,0 + + set_icc 0x1 1 + bcplr icc1,1,1 + + set_icc 0x2 2 + bcplr icc2,1,2 + + set_icc 0x3 3 + bcplr icc3,1,3 + + set_icc 0x4 0 + bcplr icc0,1,0 + + set_icc 0x5 1 + bcplr icc1,1,1 + + set_icc 0x6 2 + bcplr icc2,1,2 + + set_icc 0x7 3 + bcplr icc3,1,3 + + set_icc 0x8 0 + bcplr icc0,1,0 + + set_icc 0x9 1 + bcplr icc1,1,1 + + set_icc 0xa 2 + bcplr icc2,1,2 + + set_icc 0xb 3 + bcplr icc3,1,3 + + set_icc 0xc 0 + bcplr icc0,1,0 + + set_icc 0xd 1 + bcplr icc1,1,1 + + set_icc 0xe 2 + bcplr icc2,1,2 + + set_icc 0xf 3 + bcplr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcplr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcplr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcplr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcplr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcplr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcplr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcplr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcplr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcplr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcplr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcplr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcplr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcplr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcplr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcplr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcplr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bcralr.cgs b/sim/testsuite/frv/bcralr.cgs new file mode 100644 index 0000000..612363d --- /dev/null +++ b/sim/testsuite/frv/bcralr.cgs @@ -0,0 +1,309 @@ +# frv testcase for bcralr $ccond +# mach: all + + .include "testutils.inc" + + start + + .global bcralr +bcralr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcralr 0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcralr 0 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bcralr 0 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcralr 0 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bcralr 0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bcralr 0 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bcralr 0 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bcralr 0 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bcralr 0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcralr 0 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bcralr 0 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcralr 0 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bcralr 0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bcralr 0 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bcralr 0 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bcralr 0 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcralr 1 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcralr 1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcralr 1 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcralr 1 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcralr 1 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcralr 1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcralr 1 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcralr 1 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcralr 1 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcralr 1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcralr 1 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcralr 1 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcralr 1 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcralr 1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcralr 1 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcralr 1 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcralr 1 + + set_icc 0x1 1 + bcralr 1 + + set_icc 0x2 2 + bcralr 1 + + set_icc 0x3 3 + bcralr 1 + + set_icc 0x4 0 + bcralr 1 + + set_icc 0x5 1 + bcralr 1 + + set_icc 0x6 2 + bcralr 1 + + set_icc 0x7 3 + bcralr 1 + + set_icc 0x8 0 + bcralr 1 + + set_icc 0x9 1 + bcralr 1 + + set_icc 0xa 2 + bcralr 1 + + set_icc 0xb 3 + bcralr 1 + + set_icc 0xc 0 + bcralr 1 + + set_icc 0xd 1 + bcralr 1 + + set_icc 0xe 2 + bcralr 1 + + set_icc 0xf 3 + bcralr 1 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcralr 0 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bctrlr.cgs b/sim/testsuite/frv/bctrlr.cgs new file mode 100644 index 0000000..b00cb97 --- /dev/null +++ b/sim/testsuite/frv/bctrlr.cgs @@ -0,0 +1,29 @@ +# frv testcase for bctrlr $ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bctrlr +bctrlr: + set_spr_addr bad,lr + set_spr_immed 1,lcr + bctrlr 0,0 + + set_spr_addr ok1,lr + set_spr_immed 2,lcr + bctrlr 0,0 + fail +ok1: + set_spr_addr bad,lr + set_spr_immed 2,lcr + bctrlr 1,0 + + set_spr_addr ok2,lr + bctrlr 1,0 + fail +ok2: + pass +bad: + fail diff --git a/sim/testsuite/frv/bcvlr.cgs b/sim/testsuite/frv/bcvlr.cgs new file mode 100644 index 0000000..b25d646 --- /dev/null +++ b/sim/testsuite/frv/bcvlr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcvlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcvlr +bcvlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcvlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bcvlr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bcvlr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcvlr icc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bcvlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcvlr icc1,0,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bcvlr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bcvlr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bcvlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bcvlr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bcvlr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcvlr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcvlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcvlr icc1,0,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bcvlr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bcvlr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcvlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bcvlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcvlr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcvlr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcvlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcvlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcvlr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcvlr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcvlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcvlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcvlr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcvlr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcvlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcvlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcvlr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcvlr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcvlr icc0,1,0 + + set_icc 0x1 1 + bcvlr icc1,1,1 + + set_icc 0x2 2 + bcvlr icc2,1,2 + + set_icc 0x3 3 + bcvlr icc3,1,3 + + set_icc 0x4 0 + bcvlr icc0,1,0 + + set_icc 0x5 1 + bcvlr icc1,1,1 + + set_icc 0x6 2 + bcvlr icc2,1,2 + + set_icc 0x7 3 + bcvlr icc3,1,3 + + set_icc 0x8 0 + bcvlr icc0,1,0 + + set_icc 0x9 1 + bcvlr icc1,1,1 + + set_icc 0xa 2 + bcvlr icc2,1,2 + + set_icc 0xb 3 + bcvlr icc3,1,3 + + set_icc 0xc 0 + bcvlr icc0,1,0 + + set_icc 0xd 1 + bcvlr icc1,1,1 + + set_icc 0xe 2 + bcvlr icc2,1,2 + + set_icc 0xf 3 + bcvlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcvlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/beq.cgs b/sim/testsuite/frv/beq.cgs new file mode 100644 index 0000000..b3706dc --- /dev/null +++ b/sim/testsuite/frv/beq.cgs @@ -0,0 +1,61 @@ +# frv testcase for beq $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global beq +beq: + set_icc 0x0 0 + beq icc0,0,bad + set_icc 0x1 1 + beq icc1,1,bad + set_icc 0x2 2 + beq icc2,2,bad + set_icc 0x3 3 + beq icc3,3,bad + set_icc 0x4 0 + beq icc0,0,ok1 + fail +ok1: + set_icc 0x5 1 + beq icc1,1,ok2 + fail +ok2: + set_icc 0x6 2 + beq icc2,2,ok3 + fail +ok3: + set_icc 0x7 3 + beq icc3,3,ok4 + fail +ok4: + set_icc 0x8 0 + beq icc0,0,bad + set_icc 0x9 1 + beq icc1,1,bad + set_icc 0xa 2 + beq icc2,2,bad + set_icc 0xb 3 + beq icc3,3,bad + set_icc 0xc 0 + beq icc0,0,ok5 + fail +ok5: + set_icc 0xd 1 + beq icc1,1,ok6 + fail +ok6: + set_icc 0xe 2 + beq icc2,2,ok7 + fail +ok7: + set_icc 0xf 3 + beq icc3,3,ok8 + fail +ok8: + + pass +bad: + fail diff --git a/sim/testsuite/frv/beqlr.cgs b/sim/testsuite/frv/beqlr.cgs new file mode 100644 index 0000000..772b9fa --- /dev/null +++ b/sim/testsuite/frv/beqlr.cgs @@ -0,0 +1,71 @@ +# frv testcase for beqlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global beqlr +beqlr: + set_spr_addr bad,lr + set_icc 0x0 0 + beqlr icc0,0 + set_icc 0x1 1 + beqlr icc1,1 + set_icc 0x2 2 + beqlr icc2,2 + set_icc 0x3 3 + beqlr icc3,3 + set_spr_addr ok1,lr + set_icc 0x4 0 + beqlr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x5 1 + beqlr icc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x6 2 + beqlr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x7 3 + beqlr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x8 0 + beqlr icc0,0 + set_icc 0x9 1 + beqlr icc1,1 + set_icc 0xa 2 + beqlr icc2,2 + set_icc 0xb 3 + beqlr icc3,3 + set_spr_addr ok5,lr + set_icc 0xc 0 + beqlr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0xd 1 + beqlr icc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0xe 2 + beqlr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0xf 3 + beqlr icc3,3 + fail +ok8: + + pass +bad: + fail diff --git a/sim/testsuite/frv/bge.cgs b/sim/testsuite/frv/bge.cgs new file mode 100644 index 0000000..7ebead7 --- /dev/null +++ b/sim/testsuite/frv/bge.cgs @@ -0,0 +1,61 @@ +# frv testcase for bge $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bge +bge: + set_icc 0x0 0 + bge icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bge icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bge icc2,2,bad + set_icc 0x3 3 + bge icc3,3,bad + set_icc 0x4 0 + bge icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bge icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bge icc2,2,bad + set_icc 0x7 3 + bge icc3,3,bad + set_icc 0x8 0 + bge icc0,0,bad + set_icc 0x9 1 + bge icc1,1,bad + set_icc 0xa 2 + bge icc2,2,okb + fail +okb: + set_icc 0xb 3 + bge icc3,3,okc + fail +okc: + set_icc 0xc 0 + bge icc0,0,bad + set_icc 0xd 1 + bge icc1,1,bad + set_icc 0xe 2 + bge icc2,2,okf + fail +okf: + set_icc 0xf 3 + bge icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/bgelr.cgs b/sim/testsuite/frv/bgelr.cgs new file mode 100644 index 0000000..806770a --- /dev/null +++ b/sim/testsuite/frv/bgelr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bgelr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bgelr +bgelr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bgelr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bgelr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bgelr icc2,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bgelr icc3,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bgelr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bgelr icc1,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bgelr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bgelr icc3,3 + + set_spr_addr bad,lr + set_icc 0x8 0 + bgelr icc0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bgelr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bgelr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bgelr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bgelr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bgelr icc1,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bgelr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bgelr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/bgt.cgs b/sim/testsuite/frv/bgt.cgs new file mode 100644 index 0000000..98b1b17 --- /dev/null +++ b/sim/testsuite/frv/bgt.cgs @@ -0,0 +1,53 @@ +# frv testcase for bgt $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bgt +bgt: + set_icc 0x0 0 + bgt icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bgt icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bgt icc2,2,bad + set_icc 0x3 3 + bgt icc3,3,bad + set_icc 0x4 0 + bgt icc0,0,bad + set_icc 0x5 1 + bgt icc1,1,bad + set_icc 0x6 2 + bgt icc2,2,bad + set_icc 0x7 3 + bgt icc3,3,bad + set_icc 0x8 0 + bgt icc0,0,bad + set_icc 0x9 1 + bgt icc1,1,bad + set_icc 0xa 2 + bgt icc2,2,okb + fail +okb: + set_icc 0xb 3 + bgt icc3,3,okc + fail +okc: + set_icc 0xc 0 + bgt icc0,0,bad + set_icc 0xd 1 + bgt icc1,1,bad + set_icc 0xe 2 + bgt icc2,2,bad + set_icc 0xf 3 + bgt icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/frv/bgtlr.cgs b/sim/testsuite/frv/bgtlr.cgs new file mode 100644 index 0000000..ad44a2c --- /dev/null +++ b/sim/testsuite/frv/bgtlr.cgs @@ -0,0 +1,80 @@ +# frv testcase for bgtlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bgtlr +bgtlr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bgtlr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bgtlr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bgtlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bgtlr icc3,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bgtlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bgtlr icc1,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bgtlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bgtlr icc3,3 + + set_spr_addr bad,lr + set_icc 0x8 0 + bgtlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bgtlr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bgtlr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bgtlr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bgtlr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bgtlr icc1,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bgtlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bgtlr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bhi.cgs b/sim/testsuite/frv/bhi.cgs new file mode 100644 index 0000000..a92c0c0 --- /dev/null +++ b/sim/testsuite/frv/bhi.cgs @@ -0,0 +1,53 @@ +# frv testcase for bhi $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bhi +bhi: + set_icc 0x0 0 + bhi icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bhi icc1,1,bad + set_icc 0x2 2 + bhi icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bhi icc3,3,bad + set_icc 0x4 0 + bhi icc0,0,bad + set_icc 0x5 1 + bhi icc1,1,bad + set_icc 0x6 2 + bhi icc2,2,bad + set_icc 0x7 3 + bhi icc3,3,bad + set_icc 0x8 0 + bhi icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bhi icc1,1,bad + set_icc 0xa 2 + bhi icc2,2,okb + fail +okb: + set_icc 0xb 3 + bhi icc3,3,bad + set_icc 0xc 0 + bhi icc0,0,bad + set_icc 0xd 1 + bhi icc1,1,bad + set_icc 0xe 2 + bhi icc2,2,bad + set_icc 0xf 3 + bhi icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/frv/bhilr.cgs b/sim/testsuite/frv/bhilr.cgs new file mode 100644 index 0000000..927643b --- /dev/null +++ b/sim/testsuite/frv/bhilr.cgs @@ -0,0 +1,80 @@ +# frv testcase for bhilr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bhilr +bhilr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bhilr icc0,0 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x1 1 + bhilr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bhilr icc2,2 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x3 3 + bhilr icc3,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bhilr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bhilr icc1,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bhilr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bhilr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bhilr icc0,0 + fail +ok9: + set_spr_addr bad,lr + set_icc 0x9 1 + bhilr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bhilr icc2,2 + fail +okb: + set_spr_addr bad,lr + set_icc 0xb 3 + bhilr icc3,3 + + set_spr_addr bad,lr + set_icc 0xc 0 + bhilr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bhilr icc1,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bhilr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bhilr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/ble.cgs b/sim/testsuite/frv/ble.cgs new file mode 100644 index 0000000..c358766 --- /dev/null +++ b/sim/testsuite/frv/ble.cgs @@ -0,0 +1,69 @@ +# frv testcase for ble $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global ble +ble: + set_icc 0x0 0 + ble icc0,0,bad + set_icc 0x1 1 + ble icc1,1,bad + set_icc 0x2 2 + ble icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + ble icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + ble icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + ble icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + ble icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + ble icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + ble icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + ble icc1,1,oka + fail +oka: + set_icc 0xa 2 + ble icc2,2,bad + set_icc 0xb 3 + ble icc3,3,bad + set_icc 0xc 0 + ble icc0,0,okd + fail +okd: + set_icc 0xd 1 + ble icc1,1,oke + fail +oke: + set_icc 0xe 2 + ble icc2,2,okf + fail +okf: + set_icc 0xf 3 + ble icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/blelr.cgs b/sim/testsuite/frv/blelr.cgs new file mode 100644 index 0000000..dbb8e84 --- /dev/null +++ b/sim/testsuite/frv/blelr.cgs @@ -0,0 +1,88 @@ +# frv testcase for blelr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global blelr +blelr: + set_spr_addr bad,lr + set_icc 0x0 0 + blelr icc0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + blelr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + blelr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + blelr icc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + blelr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + blelr icc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + blelr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + blelr icc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + blelr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + blelr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + blelr icc2,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + blelr icc3,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + blelr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + blelr icc1,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + blelr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + blelr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/bls.cgs b/sim/testsuite/frv/bls.cgs new file mode 100644 index 0000000..e868de6 --- /dev/null +++ b/sim/testsuite/frv/bls.cgs @@ -0,0 +1,69 @@ +# frv testcase for bls $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bls +bls: + set_icc 0x0 0 + bls icc0,0,bad + set_icc 0x1 1 + bls icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bls icc2,2,bad + set_icc 0x3 3 + bls icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bls icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bls icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bls icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + bls icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + bls icc0,0,bad + set_icc 0x9 1 + bls icc1,1,oka + fail +oka: + set_icc 0xa 2 + bls icc2,2,bad + set_icc 0xb 3 + bls icc3,3,okc + fail +okc: + set_icc 0xc 0 + bls icc0,0,okd + fail +okd: + set_icc 0xd 1 + bls icc1,1,oke + fail +oke: + set_icc 0xe 2 + bls icc2,2,okf + fail +okf: + set_icc 0xf 3 + bls icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/blslr.cgs b/sim/testsuite/frv/blslr.cgs new file mode 100644 index 0000000..5166c52 --- /dev/null +++ b/sim/testsuite/frv/blslr.cgs @@ -0,0 +1,88 @@ +# frv testcase for blslr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global blslr +blslr: + set_spr_addr bad,lr + set_icc 0x0 0 + blslr icc0,0 + + set_spr_addr ok2,lr + set_icc 0x1 1 + blslr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + blslr icc2,2 + + set_spr_addr ok4,lr + set_icc 0x3 3 + blslr icc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + blslr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + blslr icc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + blslr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + blslr icc3,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + blslr icc0,0 + + set_spr_addr oka,lr + set_icc 0x9 1 + blslr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + blslr icc2,2 + + set_spr_addr okc,lr + set_icc 0xb 3 + blslr icc3,3 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + blslr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + blslr icc1,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + blslr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + blslr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/blt.cgs b/sim/testsuite/frv/blt.cgs new file mode 100644 index 0000000..639f971 --- /dev/null +++ b/sim/testsuite/frv/blt.cgs @@ -0,0 +1,61 @@ +# frv testcase for blt $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global blt +blt: + set_icc 0x0 0 + blt icc0,0,bad + set_icc 0x1 1 + blt icc1,1,bad + set_icc 0x2 2 + blt icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + blt icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + blt icc0,0,bad + set_icc 0x5 1 + blt icc1,1,bad + set_icc 0x6 2 + blt icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + blt icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + blt icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + blt icc1,1,oka + fail +oka: + set_icc 0xa 2 + blt icc2,2,bad + set_icc 0xb 3 + blt icc3,3,bad + set_icc 0xc 0 + blt icc0,0,okd + fail +okd: + set_icc 0xd 1 + blt icc1,1,oke + fail +oke: + set_icc 0xe 2 + blt icc2,2,bad + set_icc 0xf 3 + blt icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/frv/bltlr.cgs b/sim/testsuite/frv/bltlr.cgs new file mode 100644 index 0000000..fcf04b5 --- /dev/null +++ b/sim/testsuite/frv/bltlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bltlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bltlr +bltlr: + set_spr_addr bad,lr + set_icc 0x0 0 + bltlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bltlr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bltlr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bltlr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bltlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bltlr icc1,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bltlr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bltlr icc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bltlr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bltlr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bltlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bltlr icc3,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bltlr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bltlr icc1,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bltlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bltlr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bn.cgs b/sim/testsuite/frv/bn.cgs new file mode 100644 index 0000000..e5ff397 --- /dev/null +++ b/sim/testsuite/frv/bn.cgs @@ -0,0 +1,61 @@ +# frv testcase for bn $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bn +bn: + set_icc 0x0 0 + bn icc0,0,bad + set_icc 0x1 1 + bn icc1,1,bad + set_icc 0x2 2 + bn icc2,2,bad + set_icc 0x3 3 + bn icc3,3,bad + set_icc 0x4 0 + bn icc0,0,bad + set_icc 0x5 1 + bn icc1,1,bad + set_icc 0x6 2 + bn icc2,2,bad + set_icc 0x7 3 + bn icc3,3,bad + set_icc 0x8 0 + bn icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bn icc1,1,oka + fail +oka: + set_icc 0xa 2 + bn icc2,2,okb + fail +okb: + set_icc 0xb 3 + bn icc3,3,okc + fail +okc: + set_icc 0xc 0 + bn icc0,0,okd + fail +okd: + set_icc 0xd 1 + bn icc1,1,oke + fail +oke: + set_icc 0xe 2 + bn icc2,2,okf + fail +okf: + set_icc 0xf 3 + bn icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/bnc.cgs b/sim/testsuite/frv/bnc.cgs new file mode 100644 index 0000000..6f14e6c --- /dev/null +++ b/sim/testsuite/frv/bnc.cgs @@ -0,0 +1,61 @@ +# frv testcase for bnc $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bnc +bnc: + set_icc 0x0 0 + bnc icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bnc icc1,1,bad + set_icc 0x2 2 + bnc icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bnc icc3,3,bad + set_icc 0x4 0 + bnc icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bnc icc1,1,bad + set_icc 0x6 2 + bnc icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + bnc icc3,3,bad + set_icc 0x8 0 + bnc icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bnc icc1,1,bad + set_icc 0xa 2 + bnc icc2,2,okb + fail +okb: + set_icc 0xb 3 + bnc icc3,3,bad + set_icc 0xc 0 + bnc icc0,0,okd + fail +okd: + set_icc 0xd 1 + bnc icc1,1,bad + set_icc 0xe 2 + bnc icc2,2,okf + fail +okf: + set_icc 0xf 3 + bnc icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/frv/bnclr.cgs b/sim/testsuite/frv/bnclr.cgs new file mode 100644 index 0000000..d24f8eb --- /dev/null +++ b/sim/testsuite/frv/bnclr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bnclr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bnclr +bnclr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bnclr icc0,0 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x1 1 + bnclr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bnclr icc2,2 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x3 3 + bnclr icc3,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bnclr icc0,0 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x5 1 + bnclr icc1,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bnclr icc2,2 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x7 3 + bnclr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bnclr icc0,0 + fail +ok9: + set_spr_addr bad,lr + set_icc 0x9 1 + bnclr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bnclr icc2,2 + fail +okb: + set_spr_addr bad,lr + set_icc 0xb 3 + bnclr icc3,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bnclr icc0,0 + fail +okd: + set_spr_addr bad,lr + set_icc 0xd 1 + bnclr icc1,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bnclr icc2,2 + fail +okf: + set_spr_addr bad,lr + set_icc 0xf 3 + bnclr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bne.cgs b/sim/testsuite/frv/bne.cgs new file mode 100644 index 0000000..f0f0894 --- /dev/null +++ b/sim/testsuite/frv/bne.cgs @@ -0,0 +1,61 @@ +# frv testcase for bne $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bne +bne: + set_icc 0x0 0 + bne icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bne icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bne icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bne icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bne icc0,0,bad + set_icc 0x5 1 + bne icc1,1,bad + set_icc 0x6 2 + bne icc2,2,bad + set_icc 0x7 3 + bne icc3,3,bad + set_icc 0x8 0 + bne icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bne icc1,1,oka + fail +oka: + set_icc 0xa 2 + bne icc2,2,okb + fail +okb: + set_icc 0xb 3 + bne icc3,3,okc + fail +okc: + set_icc 0xc 0 + bne icc0,0,bad + set_icc 0xd 1 + bne icc1,1,bad + set_icc 0xe 2 + bne icc2,2,bad + set_icc 0xf 3 + bne icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/frv/bnelr.cgs b/sim/testsuite/frv/bnelr.cgs new file mode 100644 index 0000000..7a477b8 --- /dev/null +++ b/sim/testsuite/frv/bnelr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bnelr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bnelr +bnelr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bnelr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bnelr icc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bnelr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bnelr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bnelr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bnelr icc1,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bnelr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bnelr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bnelr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bnelr icc1,1 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bnelr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bnelr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bnelr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bnelr icc1,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bnelr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bnelr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bnlr.cgs b/sim/testsuite/frv/bnlr.cgs new file mode 100644 index 0000000..de32b05 --- /dev/null +++ b/sim/testsuite/frv/bnlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bnlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bnlr +bnlr: + set_spr_addr bad,lr + set_icc 0x0 0 + bnlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bnlr icc1,1 + + set_spr_addr bad,lr + set_icc 0x2 2 + bnlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bnlr icc3,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bnlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bnlr icc1,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bnlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bnlr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bnlr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bnlr icc1,1 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bnlr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bnlr icc3,3 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bnlr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bnlr icc1,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bnlr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bnlr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/bno.cgs b/sim/testsuite/frv/bno.cgs new file mode 100644 index 0000000..005e422 --- /dev/null +++ b/sim/testsuite/frv/bno.cgs @@ -0,0 +1,45 @@ +# frv testcase for bno $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bno +bno: + set_icc 0x0 0 + bno + set_icc 0x1 1 + bno + set_icc 0x2 2 + bno + set_icc 0x3 3 + bno + set_icc 0x4 0 + bno + set_icc 0x5 1 + bno + set_icc 0x6 2 + bno + set_icc 0x7 3 + bno + set_icc 0x8 0 + bno + set_icc 0x9 1 + bno + set_icc 0xa 2 + bno + set_icc 0xb 3 + bno + set_icc 0xc 0 + bno + set_icc 0xd 1 + bno + set_icc 0xe 2 + bno + set_icc 0xf 3 + bno + + pass +bad: + fail diff --git a/sim/testsuite/frv/bnolr.cgs b/sim/testsuite/frv/bnolr.cgs new file mode 100644 index 0000000..ae69f6f --- /dev/null +++ b/sim/testsuite/frv/bnolr.cgs @@ -0,0 +1,61 @@ +# frv testcase for bnolr +# mach: all + + .include "testutils.inc" + + start + + .global bnolr +bnolr: + set_spr_addr bad,lr + set_icc 0x0 0 + bnolr + + set_icc 0x1 1 + bnolr + + set_icc 0x2 2 + bnolr + + set_icc 0x3 3 + bnolr + + set_icc 0x4 0 + bnolr + + set_icc 0x5 1 + bnolr + + set_icc 0x6 2 + bnolr + + set_icc 0x7 3 + bnolr + + set_icc 0x8 0 + bnolr + + set_icc 0x9 1 + bnolr + + set_icc 0xa 2 + bnolr + + set_icc 0xb 3 + bnolr + + set_icc 0xc 0 + bnolr + + set_icc 0xd 1 + bnolr + + set_icc 0xe 2 + bnolr + + set_icc 0xf 3 + bnolr + + pass +bad: + fail diff --git a/sim/testsuite/frv/bnv.cgs b/sim/testsuite/frv/bnv.cgs new file mode 100644 index 0000000..29ec57a --- /dev/null +++ b/sim/testsuite/frv/bnv.cgs @@ -0,0 +1,61 @@ +# frv testcase for bnv $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bnv +bnv: + set_icc 0x0 0 + bnv icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bnv icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bnv icc2,2,bad + set_icc 0x3 3 + bnv icc3,3,bad + set_icc 0x4 0 + bnv icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bnv icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bnv icc2,2,bad + set_icc 0x7 3 + bnv icc3,3,bad + set_icc 0x8 0 + bnv icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bnv icc1,1,oka + fail +oka: + set_icc 0xa 2 + bnv icc2,2,bad + set_icc 0xb 3 + bnv icc3,3,bad + set_icc 0xc 0 + bnv icc0,0,okd + fail +okd: + set_icc 0xd 1 + bnv icc1,1,oke + fail +oke: + set_icc 0xe 2 + bnv icc2,2,bad + set_icc 0xf 3 + bnv icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/frv/bnvlr.cgs b/sim/testsuite/frv/bnvlr.cgs new file mode 100644 index 0000000..de40f9c --- /dev/null +++ b/sim/testsuite/frv/bnvlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bnvlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bnvlr +bnvlr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bnvlr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bnvlr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bnvlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bnvlr icc3,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bnvlr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bnvlr icc1,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bnvlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bnvlr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bnvlr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bnvlr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bnvlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bnvlr icc3,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bnvlr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bnvlr icc1,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bnvlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bnvlr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bp.cgs b/sim/testsuite/frv/bp.cgs new file mode 100644 index 0000000..0bc1e7f --- /dev/null +++ b/sim/testsuite/frv/bp.cgs @@ -0,0 +1,61 @@ +# frv testcase for bp $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bp +bp: + set_icc 0x0 0 + bp icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bp icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bp icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bp icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bp icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bp icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bp icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + bp icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + bp icc0,0,bad + set_icc 0x9 1 + bp icc1,1,bad + set_icc 0xa 2 + bp icc2,2,bad + set_icc 0xb 3 + bp icc3,3,bad + set_icc 0xc 0 + bp icc0,0,bad + set_icc 0xd 1 + bp icc1,1,bad + set_icc 0xe 2 + bp icc2,2,bad + set_icc 0xf 3 + bp icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/frv/bplr.cgs b/sim/testsuite/frv/bplr.cgs new file mode 100644 index 0000000..2bd9bb6 --- /dev/null +++ b/sim/testsuite/frv/bplr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bplr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bplr +bplr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bplr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bplr icc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bplr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bplr icc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bplr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bplr icc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bplr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bplr icc3,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bplr icc0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bplr icc1,1 + + set_spr_addr bad,lr + set_icc 0xa 2 + bplr icc2,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bplr icc3,3 + + set_spr_addr bad,lr + set_icc 0xc 0 + bplr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bplr icc1,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bplr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bplr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/bra.cgs b/sim/testsuite/frv/bra.cgs new file mode 100644 index 0000000..e6b312b --- /dev/null +++ b/sim/testsuite/frv/bra.cgs @@ -0,0 +1,75 @@ +# frv testcase for bra $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bra +bra: + set_icc 0x0 0 + bra ok1 + fail +ok1: + set_icc 0x1 1 + bra ok2 + fail +ok2: + set_icc 0x2 2 + bra ok3 + fail +ok3: + set_icc 0x3 3 + bra ok4 + fail +ok4: + set_icc 0x4 0 + bra ok5 + fail +ok5: + set_icc 0x5 1 + bra ok6 + fail +ok6: + set_icc 0x6 2 + bra ok7 + fail +ok7: + set_icc 0x7 3 + bra ok8 + fail +ok8: + set_icc 0x8 0 + bra ok9 + fail +ok9: + set_icc 0x9 1 + bra oka + fail +oka: + set_icc 0xa 2 + bra okb + fail +okb: + set_icc 0xb 3 + bra okc + fail +okc: + set_icc 0xc 0 + bra okd + fail +okd: + set_icc 0xd 1 + bra oke + fail +oke: + set_icc 0xe 2 + bra okf + fail +okf: + set_icc 0xf 3 + bra okg + fail +okg: + + pass diff --git a/sim/testsuite/frv/bralr.cgs b/sim/testsuite/frv/bralr.cgs new file mode 100644 index 0000000..3928209 --- /dev/null +++ b/sim/testsuite/frv/bralr.cgs @@ -0,0 +1,91 @@ +# frv testcase for bralr +# mach: all + + .include "testutils.inc" + + start + + .global bralr +bralr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bralr + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bralr + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bralr + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bralr + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bralr + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bralr + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bralr + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bralr + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bralr + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bralr + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bralr + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bralr + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bralr + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bralr + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bralr + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bralr + fail +okg: + + pass diff --git a/sim/testsuite/frv/branch.pcgs b/sim/testsuite/frv/branch.pcgs new file mode 100644 index 0000000..013b0ba --- /dev/null +++ b/sim/testsuite/frv/branch.pcgs @@ -0,0 +1,63 @@ +# frv parallel testcase for branching +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global branch +branch: ; All insns in VLIW execute + setlos.p 1,gr1 + setlos 0,gr2 + setlos.p 0,gr3 + bra ok1 + setlos.p 2,gr2 + setlos 3,gr3 + fail +ok1: + test_gr_immed 1,gr1 + test_gr_immed 0,gr2 + test_gr_immed 0,gr3 + + ; 1st branch is taken + bra.p ok5 + bra ok4 + bra.p ok3 + bra ok2 + fail +ok2: + fail +ok3: + fail +ok4: + fail +ok5: + ; 1st true branch is taken + set_icc 0x4 1 + bne.p icc1,1,ok6 + blt icc1,1,ok7 + beq.p icc1,1,ok9 + ble icc1,1,ok8 + fail +ok6: + fail +ok7: + fail +ok8: + fail +ok9: + ; combination of the above + set_icc 0x4 1 + setlos.p 4,gr4 + setlos.p 0,gr5 + bne.p icc1,1,oka + beq icc1,1,okb + setlos 5,gr5 + fail +oka: + fail +okb: + test_gr_immed 4,gr4 + test_gr_immed 0,gr5 + + pass diff --git a/sim/testsuite/frv/break.cgs b/sim/testsuite/frv/break.cgs new file mode 100644 index 0000000..b2a61a0 --- /dev/null +++ b/sim/testsuite/frv/break.cgs @@ -0,0 +1,58 @@ +# FRV testcase for break +# mach: all + + .include "testutils.inc" + + start + + .global tra +tra: + ; Can't test break anymore in the user environment because it is the + ; debugger's breakpoint insn. Just pass this test for now. + pass + + + + + + set_gr_spr tbr,gr7 + and_gr_immed -4081,gr7 ; clear tbr.tt + inc_gr_immed 0xff0,gr7 ; break handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + + test_spr_bits 0x4,2,0x1,psr ; psr.s is set + test_spr_bits 0x1,0,0x0,psr ; psr.et is clear + set_spr_addr ok1,lr + break +ret: + or_spr_immed 0x00000001,psr ; turn on psr.et + and_spr_immed 0xfffffffb,psr ; turn off psr.s + test_spr_bits 0x4,2,0x0,psr ; psr.s is clear + test_spr_bits 0x1,0,0x1,psr ; psr.et is set + set_spr_addr ok0,lr + break +ret1: + test_spr_bits 0x4,2,0x0,psr ; psr.s is clear + test_spr_bits 0x1,0,0x1,psr ; psr.et is set + pass + + ; check interrupt for second break +ok0: test_spr_addr ret1,bpcsr + test_spr_bits 0x1000,12,0x0,bpsr ; bpsr.bs is clear + test_spr_bits 0x0001,0,0x1,bpsr ; bpsr.et is set + test_spr_bits 0x4,2,0x1,psr ; psr.s is set + test_spr_bits 0x1,0,0x0,psr ; psr.et is clear + rett 0 ; nop + rett 1 + + ; check interrupt for first break +ok1: test_spr_addr ret,bpcsr + test_spr_bits 0x1000,12,0x1,bpsr ; bpsr.bs is set + test_spr_bits 0x0001,0,0x0,bpsr ; bpsr.et is clear + test_spr_bits 0x4,2,0x1,psr ; psr.s is set + test_spr_bits 0x1,0,0x0,psr ; psr.et is clear + rett 0 ; nop + rett 1 + + diff --git a/sim/testsuite/frv/bv.cgs b/sim/testsuite/frv/bv.cgs new file mode 100644 index 0000000..e2f8174 --- /dev/null +++ b/sim/testsuite/frv/bv.cgs @@ -0,0 +1,61 @@ +# frv testcase for bv $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bv +bv: + set_icc 0x0 0 + bv icc0,0,bad + set_icc 0x1 1 + bv icc1,1,bad + set_icc 0x2 2 + bv icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bv icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bv icc0,0,bad + set_icc 0x5 1 + bv icc1,1,bad + set_icc 0x6 2 + bv icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + bv icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + bv icc0,0,bad + set_icc 0x9 1 + bv icc1,1,bad + set_icc 0xa 2 + bv icc2,2,okb + fail +okb: + set_icc 0xb 3 + bv icc3,3,okc + fail +okc: + set_icc 0xc 0 + bv icc0,0,bad + set_icc 0xd 1 + bv icc1,1,bad + set_icc 0xe 2 + bv icc2,2,okf + fail +okf: + set_icc 0xf 3 + bv icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/bvlr.cgs b/sim/testsuite/frv/bvlr.cgs new file mode 100644 index 0000000..b7ba9d8 --- /dev/null +++ b/sim/testsuite/frv/bvlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bvlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bvlr +bvlr: + set_spr_addr bad,lr + set_icc 0x0 0 + bvlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bvlr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bvlr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bvlr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bvlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bvlr icc1,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bvlr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bvlr icc3,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bvlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bvlr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bvlr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bvlr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bvlr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bvlr icc1,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bvlr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bvlr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/cache.ms b/sim/testsuite/frv/cache.ms new file mode 100644 index 0000000..5b93f01 --- /dev/null +++ b/sim/testsuite/frv/cache.ms @@ -0,0 +1,168 @@ +# mach: frv fr500 fr550 +# sim: --memory-region 0xff000000,4 --memory-region 0xfe000000,00404000 +# xfail: "crashes with bad write" frv-* + +; Exit with return code + + .macro exit rc + setlos.p #1,gr7 + setlos \rc,gr8 + tira gr0,#0 + .endm + +; Pass the test case + .macro pass +pass: + setlos.p #5,gr10 + setlos #1,gr8 + setlos #5,gr7 + sethi.p %hi(passmsg),gr9 + setlo %lo(passmsg),gr9 + tira gr0,#0 + exit #0 + .endm + +; Fail the testcase + .macro fail +fail\@: + setlos.p #5,gr10 + setlos #1,gr8 + setlos #5,gr7 + sethi.p %hi(failmsg),gr9 + setlo %lo(failmsg),gr9 + tira gr0,#0 + exit #1 + .endm + + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + + .text + .global _start +_start: + movsg hsr0,gr10 ; enable insn and data caches + sethi.p 0xc800,gr11 ; in copy-back mode + setlo 0x0000,gr11 + or gr10,gr11,gr10 + movgs gr10,hsr0 + + sethi.p 0x7,sp + setlo 0x0000,sp + + ; fill the cache + sethi.p %hi(done1),gr10 + setlo %lo(done1),gr10 + movgs gr10,lr + setlos.p 0x1000,gr10 + setlos 0x0,gr11 + movgs gr10,lcr +write1: st.p gr11,@(sp,gr11) + addi.p gr11,4,gr11 + bctrlr.p 1,0 + bra write1 +done1: + ; read it back + sethi.p %hi(done2),gr10 + setlo %lo(done2),gr10 + movgs gr10,lr + setlos.p 0x1000,gr10 + setlos 0x0,gr11 + movgs gr10,lcr +read1: ld @(sp,gr11),gr12 + cmp gr11,gr12,icc0 + bne icc0,1,fail + addi.p gr11,4,gr11 + bctrlr.p 1,0 + bra read1 +done2: + + ; fill the cache twice + sethi.p %hi(done3),gr10 + setlo %lo(done3),gr10 + movgs gr10,lr + setlos.p 0x2000,gr10 + setlos 0x0,gr11 + movgs gr10,lcr +write3: st.p gr11,@(sp,gr11) + addi.p gr11,4,gr11 + bctrlr.p 1,0 + bra write3 +done3: + ; read it back + sethi.p %hi(done4),gr10 + setlo %lo(done4),gr10 + movgs gr10,lr + setlos.p 0x2000,gr10 + setlos 0x0,gr11 + movgs gr10,lcr +read4: ld @(sp,gr11),gr12 + cmp gr11,gr12,icc0 + bne icc0,1,fail + addi.p gr11,4,gr11 + bctrlr.p 1,0 + bra read4 +done4: + ; read it back in reverse + sethi.p %hi(done5),gr10 + setlo %lo(done5),gr10 + movgs gr10,lr + setlos.p 0x2000,gr10 + setlos 0x7ffc,gr11 + movgs gr10,lcr +read5: ld @(sp,gr11),gr12 + cmp gr11,gr12,icc0 + bne icc0,1,fail + subi.p gr11,4,gr11 + bctrlr.p 1,0 + bra read5 +done5: + + ; access data and insns in non-cache areas + sethi.p 0x8038,gr11 ; bctrlr 0,0 + setlo 0x2000,gr11 + + sethi.p 0xff00,gr10 ; documented area + setlo 0x0000,gr10 + sti gr11,@(gr10,0) + jmpl @(gr10,gr0) + + ; enable RAM mode + movsg hsr0,gr10 + sethi.p 0x0040,gr12 + setlo 0x0000,gr12 + or gr10,gr12,gr10 + movgs gr10,hsr0 + + sethi.p 0xfe00,gr10 ; documented area + setlo 0x0400,gr10 + sti gr11,@(gr10,0) + jmpl @(gr10,gr0) + + sethi.p 0xfe40,gr10 ; documented area + setlo 0x0400,gr10 + sti gr11,@(gr10,0) + dcf @(gr10,gr0) + jmpl @(gr10,gr0) + + sethi.p 0x0007,gr10 ; non RAM area + setlo 0x0000,gr10 + sti gr11,@(gr10,0) + jmpl @(gr10,gr0) + + sethi.p 0xfe00,gr10 ; insn RAM area + setlo 0x0000,gr10 + sti gr11,@(gr10,0) + jmpl @(gr10,gr0) + + sethi.p 0xfe40,gr10 ; data RAM area + setlo 0x0000,gr10 + sti gr11,@(gr10,0) + dcf @(gr10,gr0) + jmpl @(gr10,gr0) + + pass +fail: + fail diff --git a/sim/testsuite/frv/cadd.cgs b/sim/testsuite/frv/cadd.cgs new file mode 100644 index 0000000..291b8fb --- /dev/null +++ b/sim/testsuite/frv/cadd.cgs @@ -0,0 +1,90 @@ +# frv testcase for cadd $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cadd +cadd: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc4,1 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc4,1 + test_gr_limmed 0x8000,0x0000,gr8 + + cadd gr8,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc4,0 + test_gr_immed 1,gr8 + + cadd gr8,gr8,gr8,cc4,0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc5,0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc5,0 + test_gr_limmed 0x8000,0x0000,gr8 + + cadd gr8,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc5,1 + test_gr_immed 1,gr8 + + cadd gr8,gr8,gr8,cc5,1 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc6,1 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc6,0 + test_gr_immed 1,gr8 + + cadd gr8,gr8,gr8,cc6,1 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc7,0 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc7,1 + test_gr_immed 1,gr8 + + cadd gr8,gr8,gr8,cc7,0 + test_gr_immed 1,gr8 + + pass diff --git a/sim/testsuite/frv/caddcc.cgs b/sim/testsuite/frv/caddcc.cgs new file mode 100644 index 0000000..ddfd41e --- /dev/null +++ b/sim/testsuite/frv/caddcc.cgs @@ -0,0 +1,163 @@ +# frv testcase for caddcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global caddcc +caddcc: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,0 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc4,1; test zero, carry and overflow bits + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_immed 1,gr8 + + set_icc 0x08,0 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc4,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc4,0; test zero, carry and overflow bits + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,1 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc5,0; test zero, carry and overflow bits + test_icc 0 1 1 1 icc1 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_immed 1,gr8 + + set_icc 0x08,1 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc5,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc5,1; test zero, carry and overflow bits + test_icc 1 0 0 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_immed 1,gr8 + + set_icc 0x08,2 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc6,1 + test_icc 1 0 0 0 icc2 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc6,1; test zero, carry and overflow bits + test_icc 1 0 0 0 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_immed 1,gr8 + + set_icc 0x08,3 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc7,1 + test_icc 1 0 0 0 icc3 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc7,1; test zero, carry and overflow bits + test_icc 1 0 0 0 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + + pass diff --git a/sim/testsuite/frv/call.cgs b/sim/testsuite/frv/call.cgs new file mode 100644 index 0000000..5f0d767 --- /dev/null +++ b/sim/testsuite/frv/call.cgs @@ -0,0 +1,17 @@ +# frv testcase for call $label24 +# mach: all + + .include "testutils.inc" + + start + + .global call +call: + set_spr_immed 0,lr + call ok1 +bad1: + fail +ok1: + test_spr_addr bad1,lr + + pass diff --git a/sim/testsuite/frv/call.pcgs b/sim/testsuite/frv/call.pcgs new file mode 100644 index 0000000..7f452c6 --- /dev/null +++ b/sim/testsuite/frv/call.pcgs @@ -0,0 +1,30 @@ +# frv parallel testcase for call $label24 +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global call +call: + set_spr_immed 0,lr + call ok1 +bad1: + fail +ok1: + test_spr_addr bad1,lr + + set_spr_immed 0,lr + setlos.p 0,gr5 + call.p ok2 + bra bad3 +bad2: + setlos 5,gr5 + fail +bad3: + fail +ok2: + test_spr_addr bad2,lr + test_gr_immed 0,gr5 + + pass diff --git a/sim/testsuite/frv/callil.cgs b/sim/testsuite/frv/callil.cgs new file mode 100644 index 0000000..eac63e8 --- /dev/null +++ b/sim/testsuite/frv/callil.cgs @@ -0,0 +1,26 @@ +# frv testcase for callil @($GRi,$d12),$LI +# mach: all + + .include "testutils.inc" + + start + + .global callil +callil: + set_gr_addr ok2,gr8 + inc_gr_immed -2047,gr8 + callil @(gr8,0x7ff) +bad2: + fail +ok2: + test_spr_addr bad2,lr + + set_gr_addr ok3,gr8 + inc_gr_immed 2048,gr8 + callil @(gr8,-2048) +bad3: + fail +ok3: + test_spr_addr bad3,lr + + pass diff --git a/sim/testsuite/frv/calll.cgs b/sim/testsuite/frv/calll.cgs new file mode 100644 index 0000000..eee73bc --- /dev/null +++ b/sim/testsuite/frv/calll.cgs @@ -0,0 +1,28 @@ +# frv testcase for calll @($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global calll +calll: + set_gr_addr ok2,gr8 + inc_gr_immed -4,gr8 + inc_gr_immed 4,gr9 + calll @(gr8,gr9) +bad2: + fail +ok2: + test_spr_addr bad2,lr + + set_gr_addr ok3,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + calll @(gr8,gr9) +bad3: + fail +ok3: + test_spr_addr bad3,lr + + pass diff --git a/sim/testsuite/frv/cand.cgs b/sim/testsuite/frv/cand.cgs new file mode 100644 index 0000000..6113593 --- /dev/null +++ b/sim/testsuite/frv/cand.cgs @@ -0,0 +1,126 @@ +# frv testcase for cand $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global cand +cand: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc0,1 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc4,1 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x0000,0xaaaa,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc0,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc4,0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc1,0 + test_icc 1 0 1 1 icc1 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 0 icc1 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc5,0 + test_icc 1 1 0 1 icc1 + test_gr_limmed 0x0000,0xaaaa,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc1,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 0 icc1 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc5,1 + test_icc 1 1 0 1 icc1 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,2 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc2,0 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,2 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 0 icc2 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc6,1 + test_icc 1 1 0 1 icc2 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,3 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc3,0 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,3 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 0 icc3 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc7,1 + test_icc 1 1 0 1 icc3 + test_gr_limmed 0x0000,0xffff,gr8 + + pass diff --git a/sim/testsuite/frv/candcc.cgs b/sim/testsuite/frv/candcc.cgs new file mode 100644 index 0000000..c16df73 --- /dev/null +++ b/sim/testsuite/frv/candcc.cgs @@ -0,0 +1,126 @@ +# frv testcase for candcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global candcc +candcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x0000,0xaaaa,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc4,0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 0 1 icc1 + test_gr_limmed 0x0000,0xaaaa,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 0 icc1 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc5,1 + test_icc 1 1 0 1 icc1 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,2 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,2 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 0 icc2 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc6,1 + test_icc 1 1 0 1 icc2 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,3 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,3 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 0 icc3 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc7,1 + test_icc 1 1 0 1 icc3 + test_gr_limmed 0x0000,0xffff,gr8 + + pass diff --git a/sim/testsuite/frv/ccalll.cgs b/sim/testsuite/frv/ccalll.cgs new file mode 100644 index 0000000..dcfd300 --- /dev/null +++ b/sim/testsuite/frv/ccalll.cgs @@ -0,0 +1,101 @@ +# frv testcase for ccalll @($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccalll +ccalll: + set_spr_immed 0x1b1b,cccr + + set_gr_addr ok2,gr8 + inc_gr_immed -4,gr8 + inc_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc0,1 +bad2: + fail +ok2: + test_spr_addr bad2,lr + + set_gr_addr ok3,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc4,1 +bad3: + fail +ok3: + test_spr_addr bad3,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc0,0 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc4,0 + test_spr_addr 0,lr + + set_gr_addr ok5,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc1,0 +bad5: + fail +ok5: + test_spr_addr bad5,lr + + set_gr_addr ok6,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc5,0 +bad6: + fail +ok6: + test_spr_addr bad6,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc1,1 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc5,1 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc2,1 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc6,0 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc3,0 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc7,1 + test_spr_addr 0,lr + + pass +bad: + fail + diff --git a/sim/testsuite/frv/cckc.cgs b/sim/testsuite/frv/cckc.cgs new file mode 100644 index 0000000..70eabee --- /dev/null +++ b/sim/testsuite/frv/cckc.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckc $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckc +cckc: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cckeq.cgs b/sim/testsuite/frv/cckeq.cgs new file mode 100644 index 0000000..2c86f18 --- /dev/null +++ b/sim/testsuite/frv/cckeq.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckeq $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckeq +cckeq: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cckge.cgs b/sim/testsuite/frv/cckge.cgs new file mode 100644 index 0000000..6938f1e --- /dev/null +++ b/sim/testsuite/frv/cckge.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckge $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckge +cckge: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cckgt.cgs b/sim/testsuite/frv/cckgt.cgs new file mode 100644 index 0000000..e0745dd --- /dev/null +++ b/sim/testsuite/frv/cckgt.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckgt $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckgt +cckgt: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cckhi.cgs b/sim/testsuite/frv/cckhi.cgs new file mode 100644 index 0000000..4741f5a --- /dev/null +++ b/sim/testsuite/frv/cckhi.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckhi $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckhi +cckhi: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cckle.cgs b/sim/testsuite/frv/cckle.cgs new file mode 100644 index 0000000..9d88214 --- /dev/null +++ b/sim/testsuite/frv/cckle.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckle $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckle +cckle: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cckls.cgs b/sim/testsuite/frv/cckls.cgs new file mode 100644 index 0000000..a78b779 --- /dev/null +++ b/sim/testsuite/frv/cckls.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckls $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckls +cckls: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/ccklt.cgs b/sim/testsuite/frv/ccklt.cgs new file mode 100644 index 0000000..c14c632 --- /dev/null +++ b/sim/testsuite/frv/ccklt.cgs @@ -0,0 +1,490 @@ +# frv testcase for ccklt $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccklt +ccklt: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cckn.cgs b/sim/testsuite/frv/cckn.cgs new file mode 100644 index 0000000..d423124 --- /dev/null +++ b/sim/testsuite/frv/cckn.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckn $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckn +cckn: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/ccknc.cgs b/sim/testsuite/frv/ccknc.cgs new file mode 100644 index 0000000..0478f27 --- /dev/null +++ b/sim/testsuite/frv/ccknc.cgs @@ -0,0 +1,490 @@ +# frv testcase for ccknc $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccknc +ccknc: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cckne.cgs b/sim/testsuite/frv/cckne.cgs new file mode 100644 index 0000000..d8af1e3 --- /dev/null +++ b/sim/testsuite/frv/cckne.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckne $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckne +cckne: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cckno.cgs b/sim/testsuite/frv/cckno.cgs new file mode 100644 index 0000000..8c3c927 --- /dev/null +++ b/sim/testsuite/frv/cckno.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckno $CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckno +cckno: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/ccknv.cgs b/sim/testsuite/frv/ccknv.cgs new file mode 100644 index 0000000..333edca --- /dev/null +++ b/sim/testsuite/frv/ccknv.cgs @@ -0,0 +1,490 @@ +# frv testcase for ccknv $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccknv +ccknv: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cckp.cgs b/sim/testsuite/frv/cckp.cgs new file mode 100644 index 0000000..53570d9 --- /dev/null +++ b/sim/testsuite/frv/cckp.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckp $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckp +cckp: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cckra.cgs b/sim/testsuite/frv/cckra.cgs new file mode 100644 index 0000000..c0b27fc --- /dev/null +++ b/sim/testsuite/frv/cckra.cgs @@ -0,0 +1,480 @@ +# frv testcase for cckra $CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckra +cckra: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cckv.cgs b/sim/testsuite/frv/cckv.cgs new file mode 100644 index 0000000..9ebb6e3 --- /dev/null +++ b/sim/testsuite/frv/cckv.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckv $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckv +cckv: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/ccmp.cgs b/sim/testsuite/frv/ccmp.cgs new file mode 100644 index 0000000..52d5310 --- /dev/null +++ b/sim/testsuite/frv/ccmp.cgs @@ -0,0 +1,134 @@ +# frv testcase for ccmp $GRi,$GRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccmp +ccmp: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc0,1 + test_icc 0 0 0 0 icc0 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc0,1 + test_icc 0 0 1 0 icc0 + + set_icc 0x0b,0 ; Set mask opposite of expected + ccmp gr8,gr8,cc4,1 + test_icc 0 1 0 0 icc0 + + set_gr_immed 0,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc4,1 + test_icc 1 0 0 1 icc0 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc0,0 + test_icc 1 1 1 1 icc0 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc0,0 + test_icc 1 1 0 1 icc0 + + set_icc 0x0b,0 ; Set mask opposite of expected + ccmp gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + + set_icc 0x06,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc4,0 + test_icc 0 1 1 0 icc0 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc1,0 + test_icc 0 0 0 0 icc1 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc1,0 + test_icc 0 0 1 0 icc1 + + set_icc 0x0b,1 ; Set mask opposite of expected + ccmp gr8,gr8,cc5,0 + test_icc 0 1 0 0 icc1 + + set_gr_immed 0,gr8 + set_icc 0x06,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc5,0 + test_icc 1 0 0 1 icc1 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc1,1 + test_icc 1 1 1 1 icc1 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc1,1 + test_icc 1 1 0 1 icc1 + + set_icc 0x0b,1 ; Set mask opposite of expected + ccmp gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + + set_icc 0x06,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc5,1 + test_icc 0 1 1 0 icc1 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + ccmp gr8,gr7,cc2,0 + test_icc 1 1 1 1 icc2 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + ccmp gr8,gr7,cc2,0 + test_icc 1 1 0 1 icc2 + + set_icc 0x0b,2 ; Set mask opposite of expected + ccmp gr8,gr8,cc6,1 + test_icc 1 0 1 1 icc2 + + set_icc 0x06,2 ; Set mask opposite of expected + ccmp gr8,gr7,cc6,1 + test_icc 0 1 1 0 icc2 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + ccmp gr8,gr7,cc3,0 + test_icc 1 1 1 1 icc3 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + ccmp gr8,gr7,cc3,0 + test_icc 1 1 0 1 icc3 + + set_icc 0x0b,3 ; Set mask opposite of expected + ccmp gr8,gr8,cc7,1 + test_icc 1 0 1 1 icc3 + + set_icc 0x06,3 ; Set mask opposite of expected + ccmp gr8,gr7,cc7,1 + test_icc 0 1 1 0 icc3 + + pass diff --git a/sim/testsuite/frv/cfabss.cgs b/sim/testsuite/frv/cfabss.cgs new file mode 100644 index 0000000..752a40b --- /dev/null +++ b/sim/testsuite/frv/cfabss.cgs @@ -0,0 +1,96 @@ +# frv testcase for cfabss $FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfabss +cfabss: + set_spr_immed 0x1b1b,cccr + + cfabss fr0,fr1,cc0,1 + test_fr_fr fr1,fr52 + cfabss fr8,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfabss fr12,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfabss fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + cfabss fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + cfabss fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + cfabss fr0,fr1,cc1,0 + test_fr_fr fr1,fr52 + cfabss fr8,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfabss fr12,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfabss fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + cfabss fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + cfabss fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfabss fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfabss fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfabss fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr24,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr28,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfabss fr0,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr24,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr28,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr52,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/frv/cfadds.cgs b/sim/testsuite/frv/cfadds.cgs new file mode 100644 index 0000000..158ac93 --- /dev/null +++ b/sim/testsuite/frv/cfadds.cgs @@ -0,0 +1,456 @@ +# frv testcase for cfadds $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfadds +cfadds: + set_spr_immed 0x1b1b,cccr + + cfadds fr16,fr0,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfadds fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr4 + cfadds fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr8 + cfadds fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr12 + cfadds fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr16,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfadds fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfadds fr16,fr32,fr1,cc0,1 + test_fr_fr fr1,fr32 + cfadds fr16,fr36,fr1,cc0,1 + test_fr_fr fr1,fr36 + cfadds fr16,fr40,fr1,cc0,1 + test_fr_fr fr1,fr40 + cfadds fr16,fr44,fr1,cc0,1 + test_fr_fr fr1,fr44 + cfadds fr16,fr48,fr1,cc0,1 + test_fr_fr fr1,fr48 + cfadds fr16,fr52,fr1,cc0,1 + test_fr_fr fr1,fr52 + + cfadds fr20,fr0,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfadds fr20,fr4,fr1,cc0,1 + test_fr_fr fr1,fr4 + cfadds fr20,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfadds fr20,fr12,fr1,cc4,1 + test_fr_fr fr1,fr12 + cfadds fr20,fr16,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr20,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr20,fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + cfadds fr20,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + cfadds fr20,fr32,fr1,cc4,1 + test_fr_fr fr1,fr32 + cfadds fr20,fr36,fr1,cc4,1 + test_fr_fr fr1,fr36 + cfadds fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr40 + cfadds fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr44 + cfadds fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr48 + cfadds fr20,fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + cfadds fr8,fr28,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr12,fr24,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr24,fr12,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfadds fr36,fr40,fr1,cc4,1 + test_fr_fr fr1,fr44 + + cfadds fr16,fr0,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfadds fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr4 + cfadds fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr8 + cfadds fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr12 + cfadds fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr16,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfadds fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfadds fr16,fr32,fr1,cc1,0 + test_fr_fr fr1,fr32 + cfadds fr16,fr36,fr1,cc1,0 + test_fr_fr fr1,fr36 + cfadds fr16,fr40,fr1,cc1,0 + test_fr_fr fr1,fr40 + cfadds fr16,fr44,fr1,cc1,0 + test_fr_fr fr1,fr44 + cfadds fr16,fr48,fr1,cc1,0 + test_fr_fr fr1,fr48 + cfadds fr16,fr52,fr1,cc1,0 + test_fr_fr fr1,fr52 + + cfadds fr20,fr0,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfadds fr20,fr4,fr1,cc1,0 + test_fr_fr fr1,fr4 + cfadds fr20,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfadds fr20,fr12,fr1,cc5,0 + test_fr_fr fr1,fr12 + cfadds fr20,fr16,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr20,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr20,fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + cfadds fr20,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + cfadds fr20,fr32,fr1,cc5,0 + test_fr_fr fr1,fr32 + cfadds fr20,fr36,fr1,cc5,0 + test_fr_fr fr1,fr36 + cfadds fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr40 + cfadds fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr44 + cfadds fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr48 + cfadds fr20,fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + cfadds fr8,fr28,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr12,fr24,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr24,fr12,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfadds fr36,fr40,fr1,cc5,0 + test_fr_fr fr1,fr44 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfadds fr16,fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr32,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr36,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr40,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr44,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr48,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr52,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr20,fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr12,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr16,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr8,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr12,fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr24,fr12,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr28,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr36,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfadds fr16,fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr32,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr36,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr40,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr44,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr48,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr52,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr20,fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr12,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr16,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr8,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr12,fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr24,fr12,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr28,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr36,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfadds fr16,fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr4,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr8,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr12,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr20,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr24,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr32,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr36,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr40,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr44,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr48,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr52,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr20,fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr4,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr8,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr12,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr16,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr24,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr28,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr32,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr36,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr44,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr48,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr8,fr28,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr12,fr24,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr24,fr12,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr28,fr8,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr36,fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfadds fr16,fr0,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr20,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr24,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr32,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr36,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr40,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr44,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr48,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr52,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr20,fr0,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr8,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr12,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr16,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr24,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr28,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr32,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr44,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr48,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr52,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr8,fr28,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr12,fr24,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr24,fr12,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr28,fr8,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr36,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass + + diff --git a/sim/testsuite/frv/cfckeq.cgs b/sim/testsuite/frv/cfckeq.cgs new file mode 100644 index 0000000..467568a --- /dev/null +++ b/sim/testsuite/frv/cfckeq.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckeq $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckeq +cfckeq: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfckge.cgs b/sim/testsuite/frv/cfckge.cgs new file mode 100644 index 0000000..ba2de95 --- /dev/null +++ b/sim/testsuite/frv/cfckge.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckge $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckge +cfckge: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfckgt.cgs b/sim/testsuite/frv/cfckgt.cgs new file mode 100644 index 0000000..7858c17 --- /dev/null +++ b/sim/testsuite/frv/cfckgt.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckgt $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckgt +cfckgt: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfckle.cgs b/sim/testsuite/frv/cfckle.cgs new file mode 100644 index 0000000..fb2b1b85 --- /dev/null +++ b/sim/testsuite/frv/cfckle.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckle $FCCi,$CCj_float$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckle +cfckle: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfcklg.cgs b/sim/testsuite/frv/cfcklg.cgs new file mode 100644 index 0000000..22deb52 --- /dev/null +++ b/sim/testsuite/frv/cfcklg.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfcklg $FCCi,$CCj_float$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfcklg +cfcklg: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfcklt.cgs b/sim/testsuite/frv/cfcklt.cgs new file mode 100644 index 0000000..ffabcd2 --- /dev/null +++ b/sim/testsuite/frv/cfcklt.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfcklt $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfcklt +cfcklt: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfckne.cgs b/sim/testsuite/frv/cfckne.cgs new file mode 100644 index 0000000..da6846f --- /dev/null +++ b/sim/testsuite/frv/cfckne.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckne $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckne +cfckne: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfckno.cgs b/sim/testsuite/frv/cfckno.cgs new file mode 100644 index 0000000..5681960 --- /dev/null +++ b/sim/testsuite/frv/cfckno.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckno $CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckno +cfckno: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfcko.cgs b/sim/testsuite/frv/cfcko.cgs new file mode 100644 index 0000000..ac55fc3 --- /dev/null +++ b/sim/testsuite/frv/cfcko.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfcko $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfcko +cfcko: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfckra.cgs b/sim/testsuite/frv/cfckra.cgs new file mode 100644 index 0000000..0cabd8f --- /dev/null +++ b/sim/testsuite/frv/cfckra.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckra $CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckra +cfckra: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfcku.cgs b/sim/testsuite/frv/cfcku.cgs new file mode 100644 index 0000000..0f56e7e --- /dev/null +++ b/sim/testsuite/frv/cfcku.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfcku $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfcku +cfcku: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfckue.cgs b/sim/testsuite/frv/cfckue.cgs new file mode 100644 index 0000000..447c2ba --- /dev/null +++ b/sim/testsuite/frv/cfckue.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckue $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckue +cfckue: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfckug.cgs b/sim/testsuite/frv/cfckug.cgs new file mode 100644 index 0000000..7442f84 --- /dev/null +++ b/sim/testsuite/frv/cfckug.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckug $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckug +cfckug: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfckuge.cgs b/sim/testsuite/frv/cfckuge.cgs new file mode 100644 index 0000000..8eaf92f --- /dev/null +++ b/sim/testsuite/frv/cfckuge.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckuge $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckuge +cfckuge: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfckul.cgs b/sim/testsuite/frv/cfckul.cgs new file mode 100644 index 0000000..5945a8a --- /dev/null +++ b/sim/testsuite/frv/cfckul.cgs @@ -0,0 +1,410 @@ +# frv testcase for cfckul $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckul +cfckul: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfckule.cgs b/sim/testsuite/frv/cfckule.cgs new file mode 100644 index 0000000..aaf655e --- /dev/null +++ b/sim/testsuite/frv/cfckule.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckule $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckule +cfckule: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/cfcmps.cgs b/sim/testsuite/frv/cfcmps.cgs new file mode 100644 index 0000000..168e618 --- /dev/null +++ b/sim/testsuite/frv/cfcmps.cgs @@ -0,0 +1,3542 @@ +# frv testcase for cfcmps $FRi,$FRj,$FCCi,$CCi,$cond_2 +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfcmps +cfcmps: + set_spr_immed 0x1b1b,cccr + + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc4,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc4,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc4,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc4,1 + test_fcc 0x8,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc4,1 + test_fcc 0x1,0 +; + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc5,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc5,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc5,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc5,0 + test_fcc 0x8,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc5,0 + test_fcc 0x1,0 +; + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc4,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc4,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc4,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc4,0 + test_fcc 0x7,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc4,0 + test_fcc 0xe,0 +; + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc5,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc5,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc5,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc5,1 + test_fcc 0x7,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc5,1 + test_fcc 0xe,0 +; + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc2,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc2,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc2,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc2,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc2,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc2,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc2,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc2,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc6,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc6,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc6,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc6,0 + test_fcc 0x7,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc6,1 + test_fcc 0xe,0 + + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc3,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc3,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc3,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc3,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc3,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc3,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc3,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc3,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc7,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc7,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc7,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc7,0 + test_fcc 0x7,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc7,1 + test_fcc 0xe,0 + + pass diff --git a/sim/testsuite/frv/cfdivs.cgs b/sim/testsuite/frv/cfdivs.cgs new file mode 100644 index 0000000..e776f80 --- /dev/null +++ b/sim/testsuite/frv/cfdivs.cgs @@ -0,0 +1,696 @@ +# frv testcase for cfdivs $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfdivs +cfdivs: + set_spr_immed 0x1b1b,cccr + + cfdivs fr0,fr28,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfdivs fr4,fr28,fr1,cc0,1 + test_fr_fr fr1,fr4 + cfdivs fr8,fr28,fr1,cc0,1 + test_fr_fr fr1,fr8 + cfdivs fr12,fr28,fr1,cc0,1 + test_fr_fr fr1,fr12 + cfdivs fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr24,fr28,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfdivs fr28,fr28,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfdivs fr32,fr28,fr1,cc0,1 + test_fr_fr fr1,fr32 + cfdivs fr36,fr28,fr1,cc0,1 + test_fr_fr fr1,fr36 + cfdivs fr40,fr28,fr1,cc0,1 + test_fr_fr fr1,fr40 + cfdivs fr44,fr28,fr1,cc0,1 + test_fr_fr fr1,fr44 + cfdivs fr48,fr28,fr1,cc0,1 + test_fr_fr fr1,fr48 + cfdivs fr52,fr28,fr1,cc0,1 + test_fr_fr fr1,fr52 + + cfdivs fr16,fr0,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr32,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr36,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr52,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfdivs fr20,fr0,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr4,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr8,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr12,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr24,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr28,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr32,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr36,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr52,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfdivs fr8,fr28,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfdivs fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + + cfdivs fr40,fr32,fr1,cc4,1 + test_fr_fr fr1,fr36 +; + cfdivs fr0,fr28,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfdivs fr4,fr28,fr1,cc1,0 + test_fr_fr fr1,fr4 + cfdivs fr8,fr28,fr1,cc1,0 + test_fr_fr fr1,fr8 + cfdivs fr12,fr28,fr1,cc1,0 + test_fr_fr fr1,fr12 + cfdivs fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr24,fr28,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfdivs fr28,fr28,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfdivs fr32,fr28,fr1,cc1,0 + test_fr_fr fr1,fr32 + cfdivs fr36,fr28,fr1,cc1,0 + test_fr_fr fr1,fr36 + cfdivs fr40,fr28,fr1,cc1,0 + test_fr_fr fr1,fr40 + cfdivs fr44,fr28,fr1,cc1,0 + test_fr_fr fr1,fr44 + cfdivs fr48,fr28,fr1,cc1,0 + test_fr_fr fr1,fr48 + cfdivs fr52,fr28,fr1,cc1,0 + test_fr_fr fr1,fr52 + + cfdivs fr16,fr0,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr32,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr36,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr52,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfdivs fr20,fr0,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr4,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr8,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr12,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr24,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr28,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr32,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr36,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr52,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfdivs fr8,fr28,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfdivs fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + + cfdivs fr40,fr32,fr1,cc5,0 + test_fr_fr fr1,fr36 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfdivs fr0,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr4,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr8,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr12,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr24,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr32,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr36,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr40,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr44,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr48,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr52,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr16,fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr20,fr0,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr4,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr12,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr8,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr40,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfdivs fr0,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr4,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr8,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr12,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr24,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr32,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr36,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr40,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr44,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr48,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr52,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr16,fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr20,fr0,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr4,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr12,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr8,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr40,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfdivs fr0,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr4,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr8,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr12,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr24,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr32,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr36,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr40,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr44,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr48,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr52,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr16,fr0,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr4,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr24,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr32,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr36,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr40,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr44,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr48,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr52,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr20,fr0,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr4,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr8,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr12,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr24,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr32,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr36,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr40,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr44,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr48,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr52,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr8,fr28,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr8,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr40,fr32,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfdivs fr0,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr4,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr8,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr12,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr24,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr32,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr36,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr40,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr44,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr48,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr52,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr16,fr0,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr24,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr32,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr44,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr48,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr52,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr20,fr0,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr4,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr8,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr12,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr24,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr32,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr44,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr48,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr52,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr8,fr28,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr8,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr40,fr32,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/frv/cfitos.cgs b/sim/testsuite/frv/cfitos.cgs new file mode 100644 index 0000000..b24184e --- /dev/null +++ b/sim/testsuite/frv/cfitos.cgs @@ -0,0 +1,88 @@ +# frv testcase for cfitos $FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfitos +cfitos: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc0,1 + test_fr_fr fr1,fr32 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc4,1 + test_fr_iimmed 0xce054904,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc1,0 + test_fr_fr fr1,fr32 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc5,0 + test_fr_iimmed 0xce054904,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc0,0 + test_fr_iimmed 0,fr1 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc0,0 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc1,1 + test_fr_iimmed 0,fr1 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc1,1 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc2,1 + test_fr_iimmed 0,fr1 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc2,0 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc3,0 + test_fr_iimmed 0,fr1 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc3,1 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/frv/cfmadds.cgs b/sim/testsuite/frv/cfmadds.cgs new file mode 100644 index 0000000..a30f7bf --- /dev/null +++ b/sim/testsuite/frv/cfmadds.cgs @@ -0,0 +1,627 @@ +# frv testcase for cfmadds $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfmadds +cfmadds: + set_spr_immed 0x1b1b,cccr + + set_fr_fr fr16,fr1 + cfmadds fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr40,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr44,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr48,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmadds fr20,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + cfmadds fr28,fr0,fr1,cc4,1 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + cfmadds fr28,fr4,fr1,cc4,1 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + cfmadds fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + cfmadds fr28,fr12,fr1,cc4,1 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + cfmadds fr28,fr16,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmadds fr28,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmadds fr28,fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + cfmadds fr28,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + cfmadds fr28,fr32,fr1,cc4,1 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + cfmadds fr28,fr36,fr1,cc4,1 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + cfmadds fr28,fr40,fr1,cc4,1 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + cfmadds fr28,fr44,fr1,cc4,1 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + cfmadds fr28,fr48,fr1,cc4,1 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + cfmadds fr28,fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + set_fr_fr fr36,fr1 + cfmadds fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr32 + cfmadds fr8,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + + set_fr_fr fr36,fr1 + cfmadds fr32,fr36,fr1,cc4,1 + test_fr_fr fr1,fr44 +; + set_fr_fr fr16,fr1 + cfmadds fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr40,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr44,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr48,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmadds fr20,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + cfmadds fr28,fr0,fr1,cc5,0 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + cfmadds fr28,fr4,fr1,cc5,0 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + cfmadds fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + cfmadds fr28,fr12,fr1,cc5,0 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + cfmadds fr28,fr16,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmadds fr28,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmadds fr28,fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + cfmadds fr28,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + cfmadds fr28,fr32,fr1,cc5,0 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + cfmadds fr28,fr36,fr1,cc5,0 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + cfmadds fr28,fr40,fr1,cc5,0 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + cfmadds fr28,fr44,fr1,cc5,0 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + cfmadds fr28,fr48,fr1,cc5,0 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + cfmadds fr28,fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + set_fr_fr fr36,fr1 + cfmadds fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr32 + cfmadds fr8,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + + set_fr_fr fr36,fr1 + cfmadds fr32,fr36,fr1,cc5,0 + test_fr_fr fr1,fr44 +; + set_fr_fr fr48,fr1 + cfmadds fr16,fr4,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr8,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr12,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr16,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr20,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr24,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr28,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr32,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr36,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr40,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr44,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr48,fr1,cc0,0 + test_fr_fr fr1,fr48 + + cfmadds fr20,fr4,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr8,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr12,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr16,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr20,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr24,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr28,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr32,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr36,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr40,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr44,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr48,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr0,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr4,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr8,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr12,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr16,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr20,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr24,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr28,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr32,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr40,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr44,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr48,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr52,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr8,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr8,fr28,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmadds fr32,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmadds fr16,fr4,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr8,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr12,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr16,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr20,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr24,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr28,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr32,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr36,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr40,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr44,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr48,fr1,cc1,1 + test_fr_fr fr1,fr48 + + cfmadds fr20,fr4,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr8,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr12,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr16,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr20,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr24,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr28,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr32,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr36,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr40,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr44,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr48,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr0,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr4,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr8,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr12,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr16,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr20,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr24,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr28,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr32,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr40,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr44,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr48,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr52,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr8,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr8,fr28,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmadds fr32,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmadds fr16,fr4,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr8,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr12,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr16,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr20,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr24,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr28,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr32,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr36,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr40,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr44,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr48,fr1,cc2,0 + test_fr_fr fr1,fr48 + + cfmadds fr20,fr4,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr8,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr12,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr16,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr20,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr24,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr28,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr32,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr36,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr40,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr44,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr48,fr1,cc6,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr0,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr4,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr8,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr12,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr16,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr20,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr24,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr28,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr32,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr36,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr40,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr44,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr48,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr52,fr1,cc6,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr8,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr8,fr28,fr1,cc6,0 + test_fr_fr fr1,fr48 + + cfmadds fr32,fr36,fr1,cc6,1 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmadds fr16,fr4,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr8,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr12,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr16,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr20,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr24,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr28,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr32,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr36,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr40,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr44,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr48,fr1,cc3,0 + test_fr_fr fr1,fr48 + + cfmadds fr20,fr4,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr8,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr12,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr16,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr20,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr24,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr28,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr32,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr36,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr40,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr44,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr48,fr1,cc7,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr0,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr4,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr8,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr12,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr16,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr20,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr24,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr28,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr32,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr36,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr40,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr44,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr48,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr52,fr1,cc7,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr8,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr8,fr28,fr1,cc7,0 + test_fr_fr fr1,fr48 + + cfmadds fr32,fr36,fr1,cc7,1 + test_fr_fr fr1,fr48 +; + pass diff --git a/sim/testsuite/frv/cfmas.cgs b/sim/testsuite/frv/cfmas.cgs new file mode 100644 index 0000000..8c0dc05 --- /dev/null +++ b/sim/testsuite/frv/cfmas.cgs @@ -0,0 +1,775 @@ +# frv testcase for cfmas $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global cfmas +cfmas: + set_spr_immed 0x1b1b,cccr + + cfmas fr16,fr4,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + cfmas fr16,fr8,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmas fr16,fr12,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + cfmas fr16,fr16,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr16,fr20,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr16,fr24,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + cfmas fr16,fr28,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmas fr16,fr32,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + cfmas fr16,fr36,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + cfmas fr16,fr40,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + cfmas fr16,fr44,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + cfmas fr16,fr48,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + cfmas fr20,fr4,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + cfmas fr20,fr8,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmas fr20,fr12,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + cfmas fr20,fr16,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr20,fr20,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr20,fr24,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + cfmas fr20,fr28,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmas fr20,fr32,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + cfmas fr20,fr36,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + cfmas fr20,fr40,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + cfmas fr20,fr44,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + cfmas fr20,fr48,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + cfmas fr28,fr0,fr2,cc4,1 + test_fr_fr fr2,fr0 + cfmas fr28,fr4,fr2,cc4,1 + test_fr_fr fr2,fr4 + cfmas fr28,fr8,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr28,fr12,fr2,cc4,1 + test_fr_fr fr2,fr12 + cfmas fr28,fr16,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmas fr28,fr20,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmas fr28,fr24,fr2,cc4,1 + test_fr_fr fr2,fr24 + cfmas fr28,fr28,fr2,cc4,1 + test_fr_fr fr2,fr28 + cfmas fr28,fr32,fr2,cc4,1 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + cfmas fr28,fr36,fr2,cc4,1 + test_fr_fr fr2,fr36 + cfmas fr28,fr40,fr2,cc4,1 + test_fr_fr fr2,fr40 + cfmas fr28,fr44,fr2,cc4,1 + test_fr_fr fr2,fr44 + cfmas fr28,fr48,fr2,cc4,1 + test_fr_fr fr2,fr48 + cfmas fr28,fr52,fr2,cc4,1 + test_fr_fr fr2,fr52 + + cfmas fr28,fr8,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr8,fr28,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + cfmas fr32,fr36,fr2,cc4,1 + test_fr_fr fr2,fr40 +; + cfmas fr16,fr4,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + cfmas fr16,fr8,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmas fr16,fr12,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + cfmas fr16,fr16,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr16,fr20,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr16,fr24,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + cfmas fr16,fr28,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmas fr16,fr32,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + cfmas fr16,fr36,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + cfmas fr16,fr40,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + cfmas fr16,fr44,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + cfmas fr16,fr48,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + cfmas fr20,fr4,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + cfmas fr20,fr8,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmas fr20,fr12,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + cfmas fr20,fr16,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr20,fr20,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr20,fr24,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + cfmas fr20,fr28,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmas fr20,fr32,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + cfmas fr20,fr36,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + cfmas fr20,fr40,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + cfmas fr20,fr44,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + cfmas fr20,fr48,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + cfmas fr28,fr0,fr2,cc5,0 + test_fr_fr fr2,fr0 + cfmas fr28,fr4,fr2,cc5,0 + test_fr_fr fr2,fr4 + cfmas fr28,fr8,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr28,fr12,fr2,cc5,0 + test_fr_fr fr2,fr12 + cfmas fr28,fr16,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmas fr28,fr20,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmas fr28,fr24,fr2,cc5,0 + test_fr_fr fr2,fr24 + cfmas fr28,fr28,fr2,cc5,0 + test_fr_fr fr2,fr28 + cfmas fr28,fr32,fr2,cc5,0 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + cfmas fr28,fr36,fr2,cc5,0 + test_fr_fr fr2,fr36 + cfmas fr28,fr40,fr2,cc5,0 + test_fr_fr fr2,fr40 + cfmas fr28,fr44,fr2,cc5,0 + test_fr_fr fr2,fr44 + cfmas fr28,fr48,fr2,cc5,0 + test_fr_fr fr2,fr48 + cfmas fr28,fr52,fr2,cc5,0 + test_fr_fr fr2,fr52 + + cfmas fr28,fr8,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr8,fr28,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + cfmas fr32,fr36,fr2,cc5,0 + test_fr_fr fr2,fr40 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmas fr16,fr4,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr8,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr12,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr16,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr20,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr24,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr28,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr32,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr36,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr40,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr44,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr48,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr20,fr4,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr8,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr12,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr16,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr20,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr24,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr20,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr32,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr40,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr44,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr48,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr28,fr0,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr4,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr8,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr12,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr16,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr20,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr24,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr32,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr40,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr44,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr48,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr52,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + + cfmas fr28,fr8,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr8,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr32,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmas fr16,fr4,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr8,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr12,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr16,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr20,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr24,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr28,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr32,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr36,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr40,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr44,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr48,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr20,fr4,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr8,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr12,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr16,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr20,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr24,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr20,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr32,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr40,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr44,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr48,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr28,fr0,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr4,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr8,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr12,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr16,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr20,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr24,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr32,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr40,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr44,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr48,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr52,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + + cfmas fr28,fr8,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr8,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr32,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmas fr16,fr4,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr8,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr12,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr16,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr20,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr24,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr28,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr32,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr36,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr40,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr44,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr48,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr20,fr4,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr8,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr12,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr16,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr20,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr24,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr20,fr28,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr32,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr36,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr40,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr44,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr48,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr28,fr0,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr4,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr8,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr12,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr16,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr20,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr24,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr28,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr32,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr36,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr40,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr44,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr48,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr52,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + + cfmas fr28,fr8,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr8,fr28,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr32,fr36,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmas fr16,fr4,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr8,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr12,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr16,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr20,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr24,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr28,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr32,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr36,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr40,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr44,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr48,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr20,fr4,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr8,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr12,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr16,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr20,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr24,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr20,fr28,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr32,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr36,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr40,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr44,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr48,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr28,fr0,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr4,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr8,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr12,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr16,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr20,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr24,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr28,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr32,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr36,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr40,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr44,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr48,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr52,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + + cfmas fr28,fr8,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr8,fr28,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr32,fr36,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + + pass diff --git a/sim/testsuite/frv/cfmovs.cgs b/sim/testsuite/frv/cfmovs.cgs new file mode 100644 index 0000000..310bac3 --- /dev/null +++ b/sim/testsuite/frv/cfmovs.cgs @@ -0,0 +1,216 @@ +# frv testcase for cfmovs $FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfmovs +cfmovs: + set_spr_immed 0x1b1b,cccr + + cfmovs fr0,fr1,cc0,1 + test_fr_fr fr0,fr1 + cfmovs fr4,fr1,cc0,1 + test_fr_fr fr4,fr1 + cfmovs fr8,fr1,cc0,1 + test_fr_fr fr8,fr1 + cfmovs fr12,fr1,cc0,1 + test_fr_fr fr12,fr1 + cfmovs fr16,fr1,cc0,1 + test_fr_fr fr16,fr1 + cfmovs fr20,fr1,cc0,1 + test_fr_fr fr20,fr1 + cfmovs fr24,fr1,cc0,1 + test_fr_fr fr24,fr1 + cfmovs fr28,fr1,cc0,1 + test_fr_fr fr28,fr1 + cfmovs fr32,fr1,cc4,1 + test_fr_fr fr32,fr1 + cfmovs fr36,fr1,cc4,1 + test_fr_fr fr36,fr1 + cfmovs fr40,fr1,cc4,1 + test_fr_fr fr40,fr1 + cfmovs fr44,fr1,cc4,1 + test_fr_fr fr44,fr1 + cfmovs fr48,fr1,cc4,1 + test_fr_fr fr48,fr1 + cfmovs fr52,fr1,cc4,1 + test_fr_fr fr52,fr1 + cfmovs fr56,fr1,cc4,1 + test_fr_iimmed 0x7fc00000,fr1 + cfmovs fr60,fr1,cc4,1 + test_fr_iimmed 0x7f800001,fr1 + + cfmovs fr0,fr1,cc1,0 + test_fr_fr fr0,fr1 + cfmovs fr4,fr1,cc1,0 + test_fr_fr fr4,fr1 + cfmovs fr8,fr1,cc1,0 + test_fr_fr fr8,fr1 + cfmovs fr12,fr1,cc1,0 + test_fr_fr fr12,fr1 + cfmovs fr16,fr1,cc1,0 + test_fr_fr fr16,fr1 + cfmovs fr20,fr1,cc1,0 + test_fr_fr fr20,fr1 + cfmovs fr24,fr1,cc1,0 + test_fr_fr fr24,fr1 + cfmovs fr28,fr1,cc1,0 + test_fr_fr fr28,fr1 + cfmovs fr32,fr1,cc5,0 + test_fr_fr fr32,fr1 + cfmovs fr36,fr1,cc5,0 + test_fr_fr fr36,fr1 + cfmovs fr40,fr1,cc5,0 + test_fr_fr fr40,fr1 + cfmovs fr44,fr1,cc5,0 + test_fr_fr fr44,fr1 + cfmovs fr48,fr1,cc5,0 + test_fr_fr fr48,fr1 + cfmovs fr52,fr1,cc5,0 + test_fr_fr fr52,fr1 + cfmovs fr56,fr1,cc5,0 + test_fr_iimmed 0x7fc00000,fr1 + cfmovs fr60,fr1,cc5,0 + test_fr_iimmed 0x7f800001,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmovs fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr56,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr60,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmovs fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr56,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr60,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmovs fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr4,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr8,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr12,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr20,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr24,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr32,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr36,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr44,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr48,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr56,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr60,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmovs fr0,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr4,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr8,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr12,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr20,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr24,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr32,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr36,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr40,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr44,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr48,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr52,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr56,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr60,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/frv/cfmss.cgs b/sim/testsuite/frv/cfmss.cgs new file mode 100644 index 0000000..c31fba3 --- /dev/null +++ b/sim/testsuite/frv/cfmss.cgs @@ -0,0 +1,697 @@ +# frv testcase for cfmss $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global cfmss +cfmss: + set_spr_immed 0x1b1b,cccr + + cfmss fr16,fr4,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr8,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr16,fr12,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr16,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr16,fr20,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr16,fr24,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr28,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmss fr16,fr32,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr36,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr40,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr44,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr48,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + cfmss fr20,fr4,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr8,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr20,fr12,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr16,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr20,fr20,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr20,fr24,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr28,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmss fr20,fr32,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr36,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr40,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr44,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr48,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + cfmss fr28,fr0,fr2,cc4,1 + test_fr_fr fr2,fr0 + cfmss fr28,fr4,fr2,cc4,1 + test_fr_fr fr2,fr4 + cfmss fr28,fr8,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + cfmss fr28,fr12,fr2,cc4,1 + test_fr_fr fr2,fr12 + cfmss fr28,fr16,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr28,fr20,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr28,fr24,fr2,cc4,1 + test_fr_fr fr2,fr24 + cfmss fr28,fr28,fr2,cc4,1 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + cfmss fr28,fr32,fr2,cc4,1 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + cfmss fr28,fr36,fr2,cc4,1 + test_fr_fr fr2,fr36 + cfmss fr28,fr40,fr2,cc4,1 + test_fr_fr fr2,fr40 + cfmss fr28,fr44,fr2,cc4,1 + test_fr_fr fr2,fr44 + cfmss fr28,fr48,fr2,cc4,1 + test_fr_fr fr2,fr48 + cfmss fr28,fr52,fr2,cc4,1 + test_fr_fr fr2,fr52 + + cfmss fr28,fr8,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + cfmss fr8,fr28,fr2,cc4,1 + test_fr_fr fr2,fr8 + + cfmss fr32,fr36,fr2,cc4,1 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 +; + cfmss fr16,fr4,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr8,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr16,fr12,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr16,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr16,fr20,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr16,fr24,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr28,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmss fr16,fr32,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr36,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr40,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr44,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr48,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + cfmss fr20,fr4,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr8,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr20,fr12,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr16,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr20,fr20,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr20,fr24,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr28,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmss fr20,fr32,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr36,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr40,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr44,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr48,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + cfmss fr28,fr0,fr2,cc5,0 + test_fr_fr fr2,fr0 + cfmss fr28,fr4,fr2,cc5,0 + test_fr_fr fr2,fr4 + cfmss fr28,fr8,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + cfmss fr28,fr12,fr2,cc5,0 + test_fr_fr fr2,fr12 + cfmss fr28,fr16,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr28,fr20,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr28,fr24,fr2,cc5,0 + test_fr_fr fr2,fr24 + cfmss fr28,fr28,fr2,cc5,0 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + cfmss fr28,fr32,fr2,cc5,0 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + cfmss fr28,fr36,fr2,cc5,0 + test_fr_fr fr2,fr36 + cfmss fr28,fr40,fr2,cc5,0 + test_fr_fr fr2,fr40 + cfmss fr28,fr44,fr2,cc5,0 + test_fr_fr fr2,fr44 + cfmss fr28,fr48,fr2,cc5,0 + test_fr_fr fr2,fr48 + cfmss fr28,fr52,fr2,cc5,0 + test_fr_fr fr2,fr52 + + cfmss fr28,fr8,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + cfmss fr8,fr28,fr2,cc5,0 + test_fr_fr fr2,fr8 + + cfmss fr32,fr36,fr2,cc5,0 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmss fr16,fr4,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr8,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr12,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr16,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr20,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr24,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr28,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr32,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr36,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr40,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr44,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr48,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr20,fr4,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr8,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr12,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr16,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr20,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr24,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr28,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr32,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr40,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr44,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr48,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr0,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr4,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr8,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr12,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr16,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr20,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr24,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr32,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr40,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr44,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr48,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr52,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr8,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr8,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr32,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmss fr16,fr4,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr8,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr12,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr16,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr20,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr24,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr28,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr32,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr36,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr40,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr44,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr48,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr20,fr4,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr8,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr12,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr16,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr20,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr24,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr28,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr32,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr40,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr44,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr48,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr0,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr4,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr8,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr12,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr16,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr20,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr24,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr32,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr40,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr44,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr48,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr52,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr8,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr8,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr32,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmss fr16,fr4,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr8,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr12,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr16,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr20,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr24,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr28,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr32,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr36,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr40,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr44,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr48,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr20,fr4,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr8,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr12,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr16,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr20,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr24,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr28,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr32,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr36,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr40,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr44,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr48,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr0,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr4,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr8,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr12,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr16,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr20,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr24,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr28,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr32,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr36,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr40,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr44,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr48,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr52,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr8,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr8,fr28,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr32,fr36,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmss fr16,fr4,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr8,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr12,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr16,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr20,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr24,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr28,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr32,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr36,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr40,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr44,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr48,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr20,fr4,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr8,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr12,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr16,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr20,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr24,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr28,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr32,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr36,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr40,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr44,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr48,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr0,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr4,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr8,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr12,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr16,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr20,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr24,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr28,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr32,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr36,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr40,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr44,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr48,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr52,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr8,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr8,fr28,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr32,fr36,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + pass diff --git a/sim/testsuite/frv/cfmsubs.cgs b/sim/testsuite/frv/cfmsubs.cgs new file mode 100644 index 0000000..bc74da4 --- /dev/null +++ b/sim/testsuite/frv/cfmsubs.cgs @@ -0,0 +1,629 @@ +# frv testcase for cfmsubs $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfmsubs +cfmsubs: + set_spr_immed 0x1b1b,cccr + + set_fr_fr fr16,fr1 + cfmsubs fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr40,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr44,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr48,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmsubs fr20,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + cfmsubs fr28,fr0,fr1,cc4,1 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr4,fr1,cc4,1 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr12,fr1,cc4,1 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr16,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr32,fr1,cc4,1 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr36,fr1,cc4,1 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr40,fr1,cc4,1 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr44,fr1,cc4,1 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr48,fr1,cc4,1 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + set_fr_fr fr32,fr1 + cfmsubs fr8,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + set_fr_fr fr36,fr1 + cfmsubs fr36,fr36,fr1,cc4,1 + test_fr_fr fr1,fr40 + + cfmsubs fr32,fr36,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 +; + set_fr_fr fr16,fr1 + cfmsubs fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr40,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr44,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr48,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmsubs fr20,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + cfmsubs fr28,fr0,fr1,cc5,0 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr4,fr1,cc5,0 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr12,fr1,cc5,0 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr16,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr32,fr1,cc5,0 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr36,fr1,cc5,0 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr40,fr1,cc5,0 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr44,fr1,cc5,0 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr48,fr1,cc5,0 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + set_fr_fr fr32,fr1 + cfmsubs fr8,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + set_fr_fr fr36,fr1 + cfmsubs fr36,fr36,fr1,cc5,0 + test_fr_fr fr1,fr40 + + cfmsubs fr32,fr36,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 +; + set_fr_fr fr48,fr1 + cfmsubs fr16,fr4,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr8,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr12,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr16,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr20,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr24,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr28,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr32,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr36,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr40,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr44,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr48,fr1,cc0,0 + test_fr_fr fr1,fr48 + + cfmsubs fr20,fr4,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr8,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr12,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr16,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr20,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr24,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr28,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr32,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr36,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr40,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr44,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr48,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmsubs fr28,fr0,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr4,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr8,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr12,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr16,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr20,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr24,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr28,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr32,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr40,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr44,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr48,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr52,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmsubs fr8,fr8,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr36,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmsubs fr32,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmsubs fr16,fr4,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr8,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr12,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr16,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr20,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr24,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr28,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr32,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr36,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr40,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr44,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr48,fr1,cc1,1 + test_fr_fr fr1,fr48 + + cfmsubs fr20,fr4,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr8,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr12,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr16,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr20,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr24,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr28,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr32,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr36,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr40,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr44,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr48,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmsubs fr28,fr0,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr4,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr8,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr12,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr16,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr20,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr24,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr28,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr32,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr40,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr44,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr48,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr52,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmsubs fr8,fr8,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr36,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmsubs fr32,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmsubs fr16,fr4,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr8,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr12,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr16,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr20,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr24,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr28,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr32,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr36,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr40,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr44,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr48,fr1,cc2,1 + test_fr_fr fr1,fr48 + + cfmsubs fr20,fr4,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr8,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr12,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr16,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr20,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr24,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr28,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr32,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr36,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr40,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr44,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr48,fr1,cc6,1 + test_fr_fr fr1,fr48 + + cfmsubs fr28,fr0,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr4,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr8,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr12,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr16,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr20,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr24,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr28,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr32,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr36,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr40,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr44,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr48,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr52,fr1,cc6,1 + test_fr_fr fr1,fr48 + + cfmsubs fr8,fr8,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr36,fr36,fr1,cc6,1 + test_fr_fr fr1,fr48 + + cfmsubs fr32,fr36,fr1,cc6,0 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmsubs fr16,fr4,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr8,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr12,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr16,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr20,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr24,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr28,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr32,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr36,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr40,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr44,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr48,fr1,cc3,1 + test_fr_fr fr1,fr48 + + cfmsubs fr20,fr4,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr8,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr12,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr16,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr20,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr24,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr28,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr32,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr36,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr40,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr44,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr48,fr1,cc7,1 + test_fr_fr fr1,fr48 + + cfmsubs fr28,fr0,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr4,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr8,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr12,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr16,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr20,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr24,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr28,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr32,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr36,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr40,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr44,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr48,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr52,fr1,cc7,1 + test_fr_fr fr1,fr48 + + cfmsubs fr8,fr8,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr36,fr36,fr1,cc7,1 + test_fr_fr fr1,fr48 + + cfmsubs fr32,fr36,fr1,cc7,0 + test_fr_fr fr1,fr48 +; + pass diff --git a/sim/testsuite/frv/cfmuls.cgs b/sim/testsuite/frv/cfmuls.cgs new file mode 100644 index 0000000..773c95a --- /dev/null +++ b/sim/testsuite/frv/cfmuls.cgs @@ -0,0 +1,696 @@ +# frv testcase for cfmuls $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfmuls +cfmuls: + set_spr_immed 0x1b1b,cccr + + cfmuls fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr40,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr44,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr48,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmuls fr20,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr36,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmuls fr28,fr0,fr1,cc4,1 + test_fr_fr fr1,fr0 + cfmuls fr28,fr4,fr1,cc4,1 + test_fr_fr fr1,fr4 + cfmuls fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfmuls fr28,fr12,fr1,cc4,1 + test_fr_fr fr1,fr12 + cfmuls fr28,fr16,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr28,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr28,fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + cfmuls fr28,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + cfmuls fr28,fr32,fr1,cc4,1 + test_fr_fr fr1,fr32 + cfmuls fr28,fr36,fr1,cc4,1 + test_fr_fr fr1,fr36 + cfmuls fr28,fr40,fr1,cc4,1 + test_fr_fr fr1,fr40 + cfmuls fr28,fr44,fr1,cc4,1 + test_fr_fr fr1,fr44 + cfmuls fr28,fr48,fr1,cc4,1 + test_fr_fr fr1,fr48 + cfmuls fr28,fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + cfmuls fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfmuls fr8,fr28,fr1,cc4,1 + test_fr_fr fr1,fr8 + + cfmuls fr32,fr36,fr1,cc4,1 + test_fr_fr fr1,fr40 +; + cfmuls fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr40,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr44,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr48,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmuls fr20,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr36,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmuls fr28,fr0,fr1,cc5,0 + test_fr_fr fr1,fr0 + cfmuls fr28,fr4,fr1,cc5,0 + test_fr_fr fr1,fr4 + cfmuls fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfmuls fr28,fr12,fr1,cc5,0 + test_fr_fr fr1,fr12 + cfmuls fr28,fr16,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr28,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr28,fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + cfmuls fr28,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + cfmuls fr28,fr32,fr1,cc5,0 + test_fr_fr fr1,fr32 + cfmuls fr28,fr36,fr1,cc5,0 + test_fr_fr fr1,fr36 + cfmuls fr28,fr40,fr1,cc5,0 + test_fr_fr fr1,fr40 + cfmuls fr28,fr44,fr1,cc5,0 + test_fr_fr fr1,fr44 + cfmuls fr28,fr48,fr1,cc5,0 + test_fr_fr fr1,fr48 + cfmuls fr28,fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + cfmuls fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfmuls fr8,fr28,fr1,cc5,0 + test_fr_fr fr1,fr8 + + cfmuls fr32,fr36,fr1,cc5,0 + test_fr_fr fr1,fr40 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmuls fr16,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr32,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr36,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr40,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr44,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr48,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr20,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr32,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr0,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr4,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr12,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr16,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr8,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr32,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmuls fr16,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr32,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr36,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr40,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr44,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr48,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr20,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr32,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr0,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr4,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr12,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr16,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr8,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr32,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmuls fr16,fr4,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr20,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr24,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr32,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr36,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr40,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr44,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr48,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr20,fr4,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr20,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr24,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr32,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr36,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr40,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr44,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr48,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr0,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr4,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr8,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr12,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr16,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr24,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr28,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr32,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr36,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr44,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr48,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr8,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr8,fr28,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr32,fr36,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmuls fr16,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr20,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr24,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr32,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr36,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr40,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr44,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr48,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr20,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr20,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr24,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr32,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr44,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr48,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr0,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr4,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr8,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr12,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr16,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr24,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr28,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr32,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr36,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr40,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr44,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr48,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr52,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr8,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr8,fr28,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr32,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/frv/cfnegs.cgs b/sim/testsuite/frv/cfnegs.cgs new file mode 100644 index 0000000..c1f2b25 --- /dev/null +++ b/sim/testsuite/frv/cfnegs.cgs @@ -0,0 +1,96 @@ +# frv testcase for cfnegs $FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfnegs +cfnegs: + set_spr_immed 0x1b1b,cccr + + cfnegs fr0,fr1,cc0,1 + test_fr_fr fr1,fr52 + cfnegs fr8,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfnegs fr12,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfnegs fr24,fr1,cc4,1 + test_fr_fr fr1,fr12 + cfnegs fr28,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfnegs fr52,fr1,cc4,1 + test_fr_fr fr1,fr0 + + cfnegs fr0,fr1,cc1,0 + test_fr_fr fr1,fr52 + cfnegs fr8,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfnegs fr12,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfnegs fr24,fr1,cc5,0 + test_fr_fr fr1,fr12 + cfnegs fr28,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfnegs fr52,fr1,cc5,0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfnegs fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfnegs fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfnegs fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr24,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr28,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfnegs fr0,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr24,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr28,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr52,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/frv/cfsqrts.cgs b/sim/testsuite/frv/cfsqrts.cgs new file mode 100644 index 0000000..ee7a9a5 --- /dev/null +++ b/sim/testsuite/frv/cfsqrts.cgs @@ -0,0 +1,60 @@ +# frv testcase for cfsqrts $FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfsqrts +cfsqrts: + set_spr_immed 0x1b1b,cccr + + cfsqrts fr44,fr1,cc0,1 ; 9.0 + test_fr_fr fr1,fr36 ; 3.0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc4,1 + test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 + + cfsqrts fr44,fr1,cc1,0 ; 9.0 + test_fr_fr fr1,fr36 ; 3.0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc5,0 + test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 + + set_fr_fr fr0,fr1 + cfsqrts fr44,fr1,cc0,0 ; 9.0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc4,0 + test_fr_iimmed 0x40490fdb,fr10 + + set_fr_fr fr0,fr1 + cfsqrts fr44,fr1,cc1,1 ; 9.0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc5,1 + test_fr_iimmed 0x40490fdb,fr10 + + set_fr_fr fr0,fr1 + cfsqrts fr44,fr1,cc2,0 ; 9.0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc6,1 + test_fr_iimmed 0x40490fdb,fr10 + + set_fr_fr fr0,fr1 + cfsqrts fr44,fr1,cc3,1 ; 9.0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc7,0 + test_fr_iimmed 0x40490fdb,fr10 + + pass diff --git a/sim/testsuite/frv/cfstoi.cgs b/sim/testsuite/frv/cfstoi.cgs new file mode 100644 index 0000000..9ba8d12 --- /dev/null +++ b/sim/testsuite/frv/cfstoi.cgs @@ -0,0 +1,83 @@ +# frv testcase for cfstoi $FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfstoi +cfstoi: + set_spr_immed 0x1b1b,cccr + + cfstoi fr16,fr1,cc0,1 + test_fr_iimmed 0,fr1 + cfstoi fr20,fr1,cc0,1 + test_fr_iimmed 0,fr1 + + cfstoi fr32,fr1,cc4,1 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xce05,0x4904,fr1 + cfstoi fr1,fr1,cc4,1 + test_fr_iimmed 0xdeadbf00,fr1 + + cfstoi fr16,fr1,cc1,0 + test_fr_iimmed 0,fr1 + cfstoi fr20,fr1,cc1,0 + test_fr_iimmed 0,fr1 + + cfstoi fr32,fr1,cc5,0 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xce05,0x4904,fr1 + cfstoi fr1,fr1,cc5,0 + test_fr_iimmed 0xdeadbf00,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfstoi fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfstoi fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr1,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfstoi fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr1,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfstoi fr20,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr32,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr1,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfstoi fr20,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr32,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr1,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/frv/cfsubs.cgs b/sim/testsuite/frv/cfsubs.cgs new file mode 100644 index 0000000..3bc7db1 --- /dev/null +++ b/sim/testsuite/frv/cfsubs.cgs @@ -0,0 +1,412 @@ +# frv testcase for cfsubs $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfsubs +cfsubs: + set_spr_immed 0x1b1b,cccr + + cfsubs fr0,fr16,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfsubs fr4,fr16,fr1,cc0,1 + test_fr_fr fr1,fr4 + cfsubs fr8,fr16,fr1,cc0,1 + test_fr_fr fr1,fr8 + cfsubs fr12,fr16,fr1,cc0,1 + test_fr_fr fr1,fr12 + cfsubs fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr20,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr24,fr16,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfsubs fr28,fr16,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfsubs fr32,fr16,fr1,cc0,1 + test_fr_fr fr1,fr32 + cfsubs fr36,fr16,fr1,cc0,1 + test_fr_fr fr1,fr36 + cfsubs fr40,fr16,fr1,cc0,1 + test_fr_fr fr1,fr40 + cfsubs fr44,fr16,fr1,cc0,1 + test_fr_fr fr1,fr44 + cfsubs fr48,fr16,fr1,cc0,1 + test_fr_fr fr1,fr48 + cfsubs fr52,fr16,fr1,cc0,1 + test_fr_fr fr1,fr52 + + cfsubs fr0,fr20,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfsubs fr4,fr20,fr1,cc4,1 + test_fr_fr fr1,fr4 + cfsubs fr8,fr20,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfsubs fr12,fr20,fr1,cc4,1 + test_fr_fr fr1,fr12 + cfsubs fr16,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr20,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr24,fr20,fr1,cc4,1 + test_fr_fr fr1,fr24 + cfsubs fr28,fr20,fr1,cc4,1 + test_fr_fr fr1,fr28 + cfsubs fr32,fr20,fr1,cc4,1 + test_fr_fr fr1,fr32 + cfsubs fr36,fr20,fr1,cc4,1 + test_fr_fr fr1,fr36 + cfsubs fr40,fr20,fr1,cc4,1 + test_fr_fr fr1,fr40 + cfsubs fr44,fr20,fr1,cc4,1 + test_fr_fr fr1,fr44 + cfsubs fr48,fr20,fr1,cc4,1 + test_fr_fr fr1,fr48 + cfsubs fr52,fr20,fr1,cc4,1 + test_fr_fr fr1,fr52 + + cfsubs fr32,fr36,fr1,cc4,1 + test_fr_fr fr1,fr8 + + cfsubs fr44,fr40,fr1,cc4,1 + test_fr_fr fr1,fr36 +; + cfsubs fr0,fr16,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfsubs fr4,fr16,fr1,cc1,0 + test_fr_fr fr1,fr4 + cfsubs fr8,fr16,fr1,cc1,0 + test_fr_fr fr1,fr8 + cfsubs fr12,fr16,fr1,cc1,0 + test_fr_fr fr1,fr12 + cfsubs fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr20,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr24,fr16,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfsubs fr28,fr16,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfsubs fr32,fr16,fr1,cc1,0 + test_fr_fr fr1,fr32 + cfsubs fr36,fr16,fr1,cc1,0 + test_fr_fr fr1,fr36 + cfsubs fr40,fr16,fr1,cc1,0 + test_fr_fr fr1,fr40 + cfsubs fr44,fr16,fr1,cc1,0 + test_fr_fr fr1,fr44 + cfsubs fr48,fr16,fr1,cc1,0 + test_fr_fr fr1,fr48 + cfsubs fr52,fr16,fr1,cc1,0 + test_fr_fr fr1,fr52 + + cfsubs fr0,fr20,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfsubs fr4,fr20,fr1,cc5,0 + test_fr_fr fr1,fr4 + cfsubs fr8,fr20,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfsubs fr12,fr20,fr1,cc5,0 + test_fr_fr fr1,fr12 + cfsubs fr16,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr20,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr24,fr20,fr1,cc5,0 + test_fr_fr fr1,fr24 + cfsubs fr28,fr20,fr1,cc5,0 + test_fr_fr fr1,fr28 + cfsubs fr32,fr20,fr1,cc5,0 + test_fr_fr fr1,fr32 + cfsubs fr36,fr20,fr1,cc5,0 + test_fr_fr fr1,fr36 + cfsubs fr40,fr20,fr1,cc5,0 + test_fr_fr fr1,fr40 + cfsubs fr44,fr20,fr1,cc5,0 + test_fr_fr fr1,fr44 + cfsubs fr48,fr20,fr1,cc5,0 + test_fr_fr fr1,fr48 + cfsubs fr52,fr20,fr1,cc5,0 + test_fr_fr fr1,fr52 + + cfsubs fr32,fr36,fr1,cc5,0 + test_fr_fr fr1,fr8 + + cfsubs fr44,fr40,fr1,cc5,0 + test_fr_fr fr1,fr36 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfsubs fr0,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr0,fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr32,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr44,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfsubs fr0,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr0,fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr32,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr44,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfsubs fr0,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr0,fr20,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr32,fr36,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr44,fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfsubs fr0,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr0,fr20,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr32,fr36,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr44,fr40,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + pass + + diff --git a/sim/testsuite/frv/cjmpl.cgs b/sim/testsuite/frv/cjmpl.cgs new file mode 100644 index 0000000..df7be86 --- /dev/null +++ b/sim/testsuite/frv/cjmpl.cgs @@ -0,0 +1,55 @@ +# frv testcase for cjmpl @($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cjmpl +cjmpl: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,lr + set_gr_addr ok1,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc0,1 + fail +ok1: + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc0,0 + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr ok4,gr8 + set_gr_immed 3,gr9 ; target gets aligned down + cjmpl @(gr8,gr9),cc1,0 + fail +ok4: + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc1,1 + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc2,0 + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc3,1 + test_spr_immed 0,lr + + pass +bad: + fail + diff --git a/sim/testsuite/frv/ckc.cgs b/sim/testsuite/frv/ckc.cgs new file mode 100644 index 0000000..a849dd4 --- /dev/null +++ b/sim/testsuite/frv/ckc.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckc $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckc +ckc: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/frv/ckeq.cgs b/sim/testsuite/frv/ckeq.cgs new file mode 100644 index 0000000..241dc9d --- /dev/null +++ b/sim/testsuite/frv/ckeq.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckeq $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckeq +ckeq: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/frv/ckge.cgs b/sim/testsuite/frv/ckge.cgs new file mode 100644 index 0000000..58eefd3 --- /dev/null +++ b/sim/testsuite/frv/ckge.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckge $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckge +ckge: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/frv/ckgt.cgs b/sim/testsuite/frv/ckgt.cgs new file mode 100644 index 0000000..7d4b6a8 --- /dev/null +++ b/sim/testsuite/frv/ckgt.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckgt $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckgt +ckgt: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckgt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckgt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckgt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckgt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/frv/ckhi.cgs b/sim/testsuite/frv/ckhi.cgs new file mode 100644 index 0000000..5c55937 --- /dev/null +++ b/sim/testsuite/frv/ckhi.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckhi $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckhi +ckhi: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckhi icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckhi icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckhi icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckhi icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/frv/ckle.cgs b/sim/testsuite/frv/ckle.cgs new file mode 100644 index 0000000..8a6f445 --- /dev/null +++ b/sim/testsuite/frv/ckle.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckle $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckle +ckle: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckle icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckle icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckle icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckle icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/frv/ckls.cgs b/sim/testsuite/frv/ckls.cgs new file mode 100644 index 0000000..ca5822f --- /dev/null +++ b/sim/testsuite/frv/ckls.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckls $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckls +ckls: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckls icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckls icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckls icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckls icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/frv/cklt.cgs b/sim/testsuite/frv/cklt.cgs new file mode 100644 index 0000000..f5848af --- /dev/null +++ b/sim/testsuite/frv/cklt.cgs @@ -0,0 +1,90 @@ +# frv testcase for cklt $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global cklt +cklt: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/frv/ckn.cgs b/sim/testsuite/frv/ckn.cgs new file mode 100644 index 0000000..073a2f1 --- /dev/null +++ b/sim/testsuite/frv/ckn.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckn $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckn +ckn: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/frv/cknc.cgs b/sim/testsuite/frv/cknc.cgs new file mode 100644 index 0000000..a1359a9 --- /dev/null +++ b/sim/testsuite/frv/cknc.cgs @@ -0,0 +1,90 @@ +# frv testcase for cknc $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global cknc +cknc: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/frv/ckne.cgs b/sim/testsuite/frv/ckne.cgs new file mode 100644 index 0000000..b9c2935 --- /dev/null +++ b/sim/testsuite/frv/ckne.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckne $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckne +ckne: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/frv/ckno.cgs b/sim/testsuite/frv/ckno.cgs new file mode 100644 index 0000000..e387b46 --- /dev/null +++ b/sim/testsuite/frv/ckno.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckno $CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckno +ckno: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/frv/cknv.cgs b/sim/testsuite/frv/cknv.cgs new file mode 100644 index 0000000..039eb7d --- /dev/null +++ b/sim/testsuite/frv/cknv.cgs @@ -0,0 +1,90 @@ +# frv testcase for cknv $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global cknv +cknv: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/frv/ckp.cgs b/sim/testsuite/frv/ckp.cgs new file mode 100644 index 0000000..49129ec --- /dev/null +++ b/sim/testsuite/frv/ckp.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckp $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckp +ckp: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/frv/ckra.cgs b/sim/testsuite/frv/ckra.cgs new file mode 100644 index 0000000..b542b10 --- /dev/null +++ b/sim/testsuite/frv/ckra.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckra $CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckra +ckra: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/frv/ckv.cgs b/sim/testsuite/frv/ckv.cgs new file mode 100644 index 0000000..338c286 --- /dev/null +++ b/sim/testsuite/frv/ckv.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckv $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckv +ckv: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/frv/cld.cgs b/sim/testsuite/frv/cld.cgs new file mode 100644 index 0000000..62e1324 --- /dev/null +++ b/sim/testsuite/frv/cld.cgs @@ -0,0 +1,126 @@ +# frv testcase for cld @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cld +cld: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/frv/cldbf.cgs b/sim/testsuite/frv/cldbf.cgs new file mode 100644 index 0000000..46d65ea --- /dev/null +++ b/sim/testsuite/frv/cldbf.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldbf @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldbf +cldbf: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0x00de,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0x00ad,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0x0000,0x0000,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0x00de,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0x00ad,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0x0000,0x0000,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + pass diff --git a/sim/testsuite/frv/cldbfu.cgs b/sim/testsuite/frv/cldbfu.cgs new file mode 100644 index 0000000..bde4ff1 --- /dev/null +++ b/sim/testsuite/frv/cldbfu.cgs @@ -0,0 +1,154 @@ +# frv testcase for cldbfu @($GRi,$GRj),$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldbfu +cldbfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0x00de,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0x00ad,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0x00de,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0x00ad,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/cldd.cgs b/sim/testsuite/frv/cldd.cgs new file mode 100644 index 0000000..709eba1 --- /dev/null +++ b/sim/testsuite/frv/cldd.cgs @@ -0,0 +1,168 @@ +# frv testcase for cldd @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldd +cldd: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + pass diff --git a/sim/testsuite/frv/clddf.cgs b/sim/testsuite/frv/clddf.cgs new file mode 100644 index 0000000..c5416ed --- /dev/null +++ b/sim/testsuite/frv/clddf.cgs @@ -0,0 +1,174 @@ +# frv testcase for clddf @($GRi,$GRj),$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global clddf +clddf: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + pass diff --git a/sim/testsuite/frv/clddfu.cgs b/sim/testsuite/frv/clddfu.cgs new file mode 100644 index 0000000..ab981aa --- /dev/null +++ b/sim/testsuite/frv/clddfu.cgs @@ -0,0 +1,212 @@ +# frv testcase for clddfu @($GRi,$GRj),$FRk,$CCi,$ccond +# mach: all + + .include "testutils.inc" + + start + + .global clddfu +clddfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/clddu.cgs b/sim/testsuite/frv/clddu.cgs new file mode 100644 index 0000000..91df6d8 --- /dev/null +++ b/sim/testsuite/frv/clddu.cgs @@ -0,0 +1,219 @@ +# frv testcase for clddu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global clddu +clddu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,gr8 + inc_gr_immed -12,gr8 + set_gr_immed 8,gr7 + clddu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + pass diff --git a/sim/testsuite/frv/cldf.cgs b/sim/testsuite/frv/cldf.cgs new file mode 100644 index 0000000..011a02a --- /dev/null +++ b/sim/testsuite/frv/cldf.cgs @@ -0,0 +1,126 @@ +# frv testcase for cldf @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldf +cldf: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + pass diff --git a/sim/testsuite/frv/cldfu.cgs b/sim/testsuite/frv/cldfu.cgs new file mode 100644 index 0000000..d4abef0 --- /dev/null +++ b/sim/testsuite/frv/cldfu.cgs @@ -0,0 +1,164 @@ +# frv testcase for cldfu @($GRi,$GRj),$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldfu +cldfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,gr20 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,gr20 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,gr20 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,gr20 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/cldhf.cgs b/sim/testsuite/frv/cldhf.cgs new file mode 100644 index 0000000..26972ed --- /dev/null +++ b/sim/testsuite/frv/cldhf.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldhf @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldhf +cldhf: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0xbeef,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0x0000,0x0000,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0xbeef,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0x0000,0x0000,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + pass diff --git a/sim/testsuite/frv/cldhfu.cgs b/sim/testsuite/frv/cldhfu.cgs new file mode 100644 index 0000000..062e398 --- /dev/null +++ b/sim/testsuite/frv/cldhfu.cgs @@ -0,0 +1,152 @@ +# frv testcase for cldhfu @($GRi,$GRj),$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldhfu +cldhfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0xbeef,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0xbeef,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/cldq.cgs b/sim/testsuite/frv/cldq.cgs new file mode 100644 index 0000000..bfb433b --- /dev/null +++ b/sim/testsuite/frv/cldq.cgs @@ -0,0 +1,276 @@ +# frv testcase for cldq @($GRi,$GRj),$GRk,$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global cldq +cldq: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + pass diff --git a/sim/testsuite/frv/cldqu.cgs b/sim/testsuite/frv/cldqu.cgs new file mode 100644 index 0000000..fa0949a --- /dev/null +++ b/sim/testsuite/frv/cldqu.cgs @@ -0,0 +1,318 @@ +# frv testcase for cldqu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global cldqu +cldqu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,gr20 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,gr20 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,gr20 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,gr20 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,gr20 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,gr20 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,gr20 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,gr20 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,gr8 + inc_gr_immed -28,gr8 + set_gr_immed 16,gr7 + cldqu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + pass diff --git a/sim/testsuite/frv/cldsb.cgs b/sim/testsuite/frv/cldsb.cgs new file mode 100644 index 0000000..ea8dd94 --- /dev/null +++ b/sim/testsuite/frv/cldsb.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldsb @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldsb +cldsb: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffde,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc4,1 + test_gr_immed 0,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xffde,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xffad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc5,0 + test_gr_immed 0,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/frv/cldsbu.cgs b/sim/testsuite/frv/cldsbu.cgs new file mode 100644 index 0000000..a4057f1 --- /dev/null +++ b/sim/testsuite/frv/cldsbu.cgs @@ -0,0 +1,162 @@ +# frv testcase for cldsbu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldsbu +cldsbu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffde,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + inc_gr_immed 4,gr9 + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xffde,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xffad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + inc_gr_immed 4,gr9 + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + inc_gr_immed 4,gr9 + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + inc_gr_immed 4,gr9 + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + set_gr_immed 1,gr7 + cldsbu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffad,gr8 + + pass + diff --git a/sim/testsuite/frv/cldsh.cgs b/sim/testsuite/frv/cldsh.cgs new file mode 100644 index 0000000..091d720 --- /dev/null +++ b/sim/testsuite/frv/cldsh.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldsh @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global cldsh +cldsh: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc4,1 + test_gr_immed 0,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc5,0 + test_gr_immed 0,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/frv/cldshu.cgs b/sim/testsuite/frv/cldshu.cgs new file mode 100644 index 0000000..491352e --- /dev/null +++ b/sim/testsuite/frv/cldshu.cgs @@ -0,0 +1,159 @@ +# frv testcase for cldshu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldshu +cldshu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + set_gr_immed 2,gr7 + cldshu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/cldu.cgs b/sim/testsuite/frv/cldu.cgs new file mode 100644 index 0000000..61cf606 --- /dev/null +++ b/sim/testsuite/frv/cldu.cgs @@ -0,0 +1,172 @@ +# frv testcase for cldu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldu +cldu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,gr9 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,gr9 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,gr9 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,gr9 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,gr9 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,gr9 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,gr9 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,gr9 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr7 + cldu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/cldub.cgs b/sim/testsuite/frv/cldub.cgs new file mode 100644 index 0000000..b1f0776 --- /dev/null +++ b/sim/testsuite/frv/cldub.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldub @($GRi,$GRj),$GRk,$cci,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldub +cldub: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00de,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00ad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x0000,0x0000,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0x00de,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0x00ad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x0000,0x0000,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/frv/cldubu.cgs b/sim/testsuite/frv/cldubu.cgs new file mode 100644 index 0000000..c9f9579 --- /dev/null +++ b/sim/testsuite/frv/cldubu.cgs @@ -0,0 +1,155 @@ +# frv testcase for cldubu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldubu +cldubu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00de,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00ad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x0000,0x0000,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0x00de,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0x00ad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x0000,0x0000,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + set_gr_immed 1,gr7 + cldubu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00ad,gr8 + + pass diff --git a/sim/testsuite/frv/clduh.cgs b/sim/testsuite/frv/clduh.cgs new file mode 100644 index 0000000..a9e505c --- /dev/null +++ b/sim/testsuite/frv/clduh.cgs @@ -0,0 +1,114 @@ +# frv testcase for clduh @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global clduh +clduh: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x0000,0x0000,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x0000,0x0000,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/frv/clduhu.cgs b/sim/testsuite/frv/clduhu.cgs new file mode 100644 index 0000000..80eb381 --- /dev/null +++ b/sim/testsuite/frv/clduhu.cgs @@ -0,0 +1,159 @@ +# frv testcase for clduhu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global clduhu +clduhu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x0000,0x0000,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x0000,0x0000,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + set_gr_immed 2,gr7 + clduhu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/clrfa.cgs b/sim/testsuite/frv/clrfa.cgs new file mode 100644 index 0000000..8bba605 --- /dev/null +++ b/sim/testsuite/frv/clrfa.cgs @@ -0,0 +1,27 @@ +# frv testcase for clrfa +# mach: frv + + .include "testutils.inc" + + start + + .global clrfa +clrfa: + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + or_spr_immed 0x00100000,fner1 + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + or_spr_immed 0x00200000,fner1 + nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 + or_spr_immed 0x00100000,fner0 + + clrfa + test_spr_immed 0x00000000,fner1 + test_spr_immed 0x00000000,fner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0,nesr2 + test_spr_immed 0,neear2 + + pass diff --git a/sim/testsuite/frv/clrfr.cgs b/sim/testsuite/frv/clrfr.cgs new file mode 100644 index 0000000..9112815 --- /dev/null +++ b/sim/testsuite/frv/clrfr.cgs @@ -0,0 +1,27 @@ +# frv testcase for clrfr $FRk +# mach: frv + + .include "testutils.inc" + + start + + .global clrfr +clrfr: + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + or_spr_immed 0x00100000,fner1 + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + or_spr_immed 0x00200000,fner1 + nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 + or_spr_immed 0x00100000,fner0 + + clrfr fr20 + test_spr_immed 0x00200000,fner1 + test_spr_immed 0x00100000,fner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xf4800801,nesr2 + test_spr_gr neear2,sp + + pass diff --git a/sim/testsuite/frv/clrga.cgs b/sim/testsuite/frv/clrga.cgs new file mode 100644 index 0000000..9e9a9a9 --- /dev/null +++ b/sim/testsuite/frv/clrga.cgs @@ -0,0 +1,27 @@ +# frv testcase for clrga +# mach: frv + + .include "testutils.inc" + + start + + .global clrga +clrga: + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + or_spr_immed 0x00100000,gner1 + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + or_spr_immed 0x00200000,gner1 + nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 + or_spr_immed 0x00100000,gner0 + + clrga + test_spr_immed 0x00000000,gner1 + test_spr_immed 0x00000000,gner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0,nesr2 + test_spr_immed 0,neear2 + + pass diff --git a/sim/testsuite/frv/clrgr.cgs b/sim/testsuite/frv/clrgr.cgs new file mode 100644 index 0000000..049b9e3 --- /dev/null +++ b/sim/testsuite/frv/clrgr.cgs @@ -0,0 +1,27 @@ +# frv testcase for clrgr $GRk +# mach: frv + + .include "testutils.inc" + + start + + .global clrgr +clrgr: + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + or_spr_immed 0x00100000,gner1 + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + or_spr_immed 0x00200000,gner1 + nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 + or_spr_immed 0x00100000,gner0 + + clrgr gr20 + test_spr_immed 0x00200000,gner1 + test_spr_immed 0x00100000,gner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xb4800801,nesr2 + test_spr_gr neear2,sp + + pass diff --git a/sim/testsuite/frv/cmaddhss.cgs b/sim/testsuite/frv/cmaddhss.cgs new file mode 100644 index 0000000..1f04e67 --- /dev/null +++ b/sim/testsuite/frv/cmaddhss.cgs @@ -0,0 +1,562 @@ +# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global maddhss +maddhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc4,1 + cmaddhss fr11,fr11,fr13,cc4,1 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc5,0 + cmaddhss fr11,fr11,fr13,cc5,0 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc4,0 + cmaddhss fr11,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc5,1 + cmaddhss fr11,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc6,1 + cmaddhss fr11,fr11,fr13,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc7,1 + cmaddhss fr11,fr11,fr13,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/frv/cmaddhus.cgs b/sim/testsuite/frv/cmaddhus.cgs new file mode 100644 index 0000000..76da81d --- /dev/null +++ b/sim/testsuite/frv/cmaddhus.cgs @@ -0,0 +1,496 @@ +# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmaddhus +cmaddhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc4,1 + cmaddhus fr11,fr11,fr13,cc4,1 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc5,0 + cmaddhus fr11,fr11,fr13,cc5,0 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc4,0 + cmaddhus fr11,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc5,1 + cmaddhus fr11,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc6,0 + cmaddhus fr11,fr11,fr13,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc7,0 + cmaddhus fr11,fr11,fr13,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/frv/cmand.cgs b/sim/testsuite/frv/cmand.cgs new file mode 100644 index 0000000..7ed9e4d --- /dev/null +++ b/sim/testsuite/frv/cmand.cgs @@ -0,0 +1,89 @@ +# frv testcase for cmand $FRinti,$FRintj,$FRintk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmand +cmand: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0xaaaa0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc4,1 + test_fr_iimmed 0x0000aaaa,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0xaaaa0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc5,0 + test_fr_iimmed 0x0000aaaa,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0xffff0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc4,0 + test_fr_iimmed 0x0000ffff,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0xffff0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc5,1 + test_fr_iimmed 0x0000ffff,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc2,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc2,1 + test_fr_iimmed 0xffff0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc6,0 + test_fr_iimmed 0x0000ffff,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc3,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc3,0 + test_fr_iimmed 0xffff0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc7,1 + test_fr_iimmed 0x0000ffff,fr8 + pass diff --git a/sim/testsuite/frv/cmbtoh.cgs b/sim/testsuite/frv/cmbtoh.cgs new file mode 100644 index 0000000..5e7c91a --- /dev/null +++ b/sim/testsuite/frv/cmbtoh.cgs @@ -0,0 +1,74 @@ +# frv testcase for cmbtoh $FRj,$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmbtoh +cmbtoh: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc0,1 + test_fr_limmed 0x00de,0x00ad,fr12 + test_fr_limmed 0x00be,0x00ef,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc4,1 + test_fr_limmed 0x0012,0x0034,fr12 + test_fr_limmed 0x0056,0x0078,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc1,0 + test_fr_limmed 0x00de,0x00ad,fr12 + test_fr_limmed 0x00be,0x00ef,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc5,0 + test_fr_limmed 0x0012,0x0034,fr12 + test_fr_limmed 0x0056,0x0078,fr13 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x2222,0x2222,fr13 + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc6,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc3,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc7,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + pass diff --git a/sim/testsuite/frv/cmbtohe.cgs b/sim/testsuite/frv/cmbtohe.cgs new file mode 100644 index 0000000..eb6b514 --- /dev/null +++ b/sim/testsuite/frv/cmbtohe.cgs @@ -0,0 +1,100 @@ +# frv testcase for cmbtohe $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + start + + .global cmbtohe +cmbtohe: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc0,1 + test_fr_limmed 0x00de,0x00de,fr12 + test_fr_limmed 0x00ad,0x00ad,fr13 + test_fr_limmed 0x00be,0x00be,fr14 + test_fr_limmed 0x00ef,0x00ef,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc4,1 + test_fr_limmed 0x0012,0x0012,fr12 + test_fr_limmed 0x0034,0x0034,fr13 + test_fr_limmed 0x0056,0x0056,fr14 + test_fr_limmed 0x0078,0x0078,fr15 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc1,0 + test_fr_limmed 0x00de,0x00de,fr12 + test_fr_limmed 0x00ad,0x00ad,fr13 + test_fr_limmed 0x00be,0x00be,fr14 + test_fr_limmed 0x00ef,0x00ef,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc5,0 + test_fr_limmed 0x0012,0x0012,fr12 + test_fr_limmed 0x0034,0x0034,fr13 + test_fr_limmed 0x0056,0x0056,fr14 + test_fr_limmed 0x0078,0x0078,fr15 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x2222,0x2222,fr13 + set_fr_iimmed 0x3333,0x3333,fr14 + set_fr_iimmed 0x4444,0x4444,fr15 + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc6,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc3,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc7,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + pass diff --git a/sim/testsuite/frv/cmcpxis.cgs b/sim/testsuite/frv/cmcpxis.cgs new file mode 100644 index 0000000..ded0300 --- /dev/null +++ b/sim/testsuite/frv/cmcpxis.cgs @@ -0,0 +1,971 @@ +# frv testcase for cmcpxis $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmcpxis +cmcpxis: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xc000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -9,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbfff,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8001,0x0000,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x8000,0x0000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xc000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -9,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbfff,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8001,0x0000,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x8000,0x0000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 +; + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/frv/cmcpxiu.cgs b/sim/testsuite/frv/cmcpxiu.cgs new file mode 100644 index 0000000..90a92bc --- /dev/null +++ b/sim/testsuite/frv/cmcpxiu.cgs @@ -0,0 +1,508 @@ +# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmcpxiu +cmcpxiu: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/frv/cmcpxrs.cgs b/sim/testsuite/frv/cmcpxrs.cgs new file mode 100644 index 0000000..ea1242c --- /dev/null +++ b/sim/testsuite/frv/cmcpxrs.cgs @@ -0,0 +1,649 @@ +# frv testcase for cmcpxrs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmcpxrs +cmcpxrs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ff0,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -3,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbff0,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8006,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8000,0x8000,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x7fff,0x8000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ff0,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -3,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbff0,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8006,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8000,0x8000,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x7fff,0x8000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 +; + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/frv/cmcpxru.cgs b/sim/testsuite/frv/cmcpxru.cgs new file mode 100644 index 0000000..f9217b6 --- /dev/null +++ b/sim/testsuite/frv/cmcpxru.cgs @@ -0,0 +1,544 @@ +# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmcpxru +cmcpxru: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 +; + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/frv/cmexpdhd.cgs b/sim/testsuite/frv/cmexpdhd.cgs new file mode 100644 index 0000000..33a3c00 --- /dev/null +++ b/sim/testsuite/frv/cmexpdhd.cgs @@ -0,0 +1,116 @@ +# frv testcase for cmexpdhd $FRi,$s6,$FRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmexpdhd +cmexpdhd: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc0,1 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + cmexpdhd fr10,1,fr12,cc0,1 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + cmexpdhd fr10,62,fr12,cc4,1 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + cmexpdhd fr10,63,fr12,cc4,1 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc1,0 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + cmexpdhd fr10,1,fr12,cc1,0 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + cmexpdhd fr10,62,fr12,cc5,0 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + cmexpdhd fr10,63,fr12,cc5,0 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x2222,0x2222,fr13 + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,1,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,62,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,63,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,1,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,62,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,63,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,1,fr12,cc2,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,62,fr12,cc6,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,63,fr12,cc6,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc3,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,1,fr12,cc3,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,62,fr12,cc7,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,63,fr12,cc7,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + pass diff --git a/sim/testsuite/frv/cmexpdhw.cgs b/sim/testsuite/frv/cmexpdhw.cgs new file mode 100644 index 0000000..330d404 --- /dev/null +++ b/sim/testsuite/frv/cmexpdhw.cgs @@ -0,0 +1,91 @@ +# frv testcase for cmexpdhw $FRi,$s6,$FRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmexpdhw +cmexpdhw: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc0,1 + test_fr_limmed 0xdead,0xdead,fr12 + + cmexpdhw fr10,1,fr12,cc0,1 + test_fr_limmed 0xbeef,0xbeef,fr12 + + cmexpdhw fr10,62,fr12,cc4,1 + test_fr_limmed 0xdead,0xdead,fr12 + + cmexpdhw fr10,63,fr12,cc4,1 + test_fr_limmed 0xbeef,0xbeef,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc1,0 + test_fr_limmed 0xdead,0xdead,fr12 + + cmexpdhw fr10,1,fr12,cc1,0 + test_fr_limmed 0xbeef,0xbeef,fr12 + + cmexpdhw fr10,62,fr12,cc5,0 + test_fr_limmed 0xdead,0xdead,fr12 + + cmexpdhw fr10,63,fr12,cc5,0 + test_fr_limmed 0xbeef,0xbeef,fr12 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,1,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,62,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,63,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,1,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,62,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,63,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,1,fr12,cc2,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,62,fr12,cc6,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,63,fr12,cc6,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc3,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,1,fr12,cc3,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,62,fr12,cc7,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,63,fr12,cc7,0 + test_fr_limmed 0x1111,0x1111,fr12 + + pass diff --git a/sim/testsuite/frv/cmhtob.cgs b/sim/testsuite/frv/cmhtob.cgs new file mode 100644 index 0000000..a3f00c5 --- /dev/null +++ b/sim/testsuite/frv/cmhtob.cgs @@ -0,0 +1,103 @@ +# frv testcase for cmhtob $FRj,$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmhtob +cmhtob: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc0,1 + test_fr_limmed 0xadef,0x3478,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc0,1 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc1,0 + test_fr_limmed 0xadef,0x3478,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc1,0 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc2,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc6,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc3,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc7,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc7,1 + test_fr_limmed 0x1111,0x1111,fr12 + + pass diff --git a/sim/testsuite/frv/cmmachs.cgs b/sim/testsuite/frv/cmmachs.cgs new file mode 100644 index 0000000..2131b7e --- /dev/null +++ b/sim/testsuite/frv/cmmachs.cgs @@ -0,0 +1,1631 @@ +# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmmachs +cmmachs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc4,1 +;;;;;;;;;;;; + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed -128,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed -128,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 ; saturation + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 +; + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/frv/cmmachu.cgs b/sim/testsuite/frv/cmmachu.cgs new file mode 100644 index 0000000..8948f15 --- /dev/null +++ b/sim/testsuite/frv/cmmachu.cgs @@ -0,0 +1,864 @@ +# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmmachu +cmmachu: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 +; + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + pass diff --git a/sim/testsuite/frv/cmmulhs.cgs b/sim/testsuite/frv/cmmulhs.cgs new file mode 100644 index 0000000..01ee598 --- /dev/null +++ b/sim/testsuite/frv/cmmulhs.cgs @@ -0,0 +1,814 @@ +# frv testcase for cmmulhs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmmulhs +cmmulhs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -2,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffe,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffe,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -2,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffe,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffe,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + pass diff --git a/sim/testsuite/frv/cmmulhu.cgs b/sim/testsuite/frv/cmmulhu.cgs new file mode 100644 index 0000000..9e8fbb8 --- /dev/null +++ b/sim/testsuite/frv/cmmulhu.cgs @@ -0,0 +1,460 @@ +# frv testcase for cmmulhu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmmulhu +cmmulhu: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x00010000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00010000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00010000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + pass diff --git a/sim/testsuite/frv/cmnot.cgs b/sim/testsuite/frv/cmnot.cgs new file mode 100644 index 0000000..cc93c01 --- /dev/null +++ b/sim/testsuite/frv/cmnot.cgs @@ -0,0 +1,60 @@ +# frv testcase for cmnot $FRintj,$FRintk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmnot +cmnot: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc0,1 + test_fr_iimmed 0x55555555,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc4,1 + test_fr_iimmed 0x21524110,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc1,0 + test_fr_iimmed 0x55555555,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc5,0 + test_fr_iimmed 0x21524110,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc0,0 + test_fr_iimmed 0xaaaaaaaa,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc4,0 + test_fr_iimmed 0xdeadbeef,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc1,1 + test_fr_iimmed 0xaaaaaaaa,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc5,1 + test_fr_iimmed 0xdeadbeef,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc2,0 + test_fr_iimmed 0xaaaaaaaa,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc6,1 + test_fr_iimmed 0xdeadbeef,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc3,0 + test_fr_iimmed 0xaaaaaaaa,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc7,1 + test_fr_iimmed 0xdeadbeef,fr7 + + pass diff --git a/sim/testsuite/frv/cmor.cgs b/sim/testsuite/frv/cmor.cgs new file mode 100644 index 0000000..ebdc5f2 --- /dev/null +++ b/sim/testsuite/frv/cmor.cgs @@ -0,0 +1,101 @@ +# frv testcase for cmor $FRinti,$FRintj,$FRintk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmor +cmor: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc4,1 + test_fr_iimmed 0xdeadbeef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc5,0 + test_fr_iimmed 0xdeadbeef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc4,0 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc5,1 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc2,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc2,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc6,0 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc3,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc3,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc7,1 + test_fr_iimmed 0x0000beef,fr8 + pass diff --git a/sim/testsuite/frv/cmov.cgs b/sim/testsuite/frv/cmov.cgs new file mode 100644 index 0000000..236bb20 --- /dev/null +++ b/sim/testsuite/frv/cmov.cgs @@ -0,0 +1,54 @@ +# frv testcase for cmov $GRi,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmov +cmov: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cmov gr7,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0xdeadbeef,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cmov gr7,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00007fff,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cmov gr7,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00007fff,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cmov gr7,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0xdeadbeef,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + cmov gr7,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0xdeadbeef,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + cmov gr7,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0xdeadbeef,gr8 + + pass diff --git a/sim/testsuite/frv/cmovfg.cgs b/sim/testsuite/frv/cmovfg.cgs new file mode 100644 index 0000000..4109842 --- /dev/null +++ b/sim/testsuite/frv/cmovfg.cgs @@ -0,0 +1,84 @@ +# frv testcase for cmovfg $FRk,$GRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmovfg +cmovfg: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc0,0 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc4,0 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc1,1 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc5,1 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc2,0 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc2,1 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc3,1 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc7,0 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/frv/cmovfgd.cgs b/sim/testsuite/frv/cmovfgd.cgs new file mode 100644 index 0000000..5d1757d --- /dev/null +++ b/sim/testsuite/frv/cmovfgd.cgs @@ -0,0 +1,132 @@ +# frv testcase for cmovfgd $FRk,$GRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmovfgd +cmovfgd: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc0,0 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc4,0 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc1,1 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc5,1 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc2,0 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc6,1 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc3,1 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc7,0 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + pass diff --git a/sim/testsuite/frv/cmovgf.cgs b/sim/testsuite/frv/cmovgf.cgs new file mode 100644 index 0000000..58ed1d8 --- /dev/null +++ b/sim/testsuite/frv/cmovgf.cgs @@ -0,0 +1,84 @@ +# frv testcase for cmovgf $GRj,$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmovgf +cmovgf: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc7,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + pass diff --git a/sim/testsuite/frv/cmovgfd.cgs b/sim/testsuite/frv/cmovgfd.cgs new file mode 100644 index 0000000..67bb272 --- /dev/null +++ b/sim/testsuite/frv/cmovgfd.cgs @@ -0,0 +1,132 @@ +# frv testcase for cmovgfd $GRj,$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmovgfd +cmovgfd: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc6,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc7,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + pass diff --git a/sim/testsuite/frv/cmp.cgs b/sim/testsuite/frv/cmp.cgs new file mode 100644 index 0000000..e6694c1 --- /dev/null +++ b/sim/testsuite/frv/cmp.cgs @@ -0,0 +1,31 @@ +# frv testcase for cmp $GRi,$GRj,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global cmp +cmp: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + cmp gr8,gr7,icc0 + test_icc 0 0 0 0 icc0 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + cmp gr8,gr7,icc0 + test_icc 0 0 1 0 icc0 + + set_icc 0x0b,0 ; Set mask opposite of expected + cmp gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + + set_gr_immed 0,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + cmp gr8,gr7,icc0 + test_icc 1 0 0 1 icc0 + + pass diff --git a/sim/testsuite/frv/cmpb.cgs b/sim/testsuite/frv/cmpb.cgs new file mode 100644 index 0000000..94b9836 --- /dev/null +++ b/sim/testsuite/frv/cmpb.cgs @@ -0,0 +1,41 @@ +# frv testcase for cmpb $GRi,$GRj,$ICCi_1 +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global cmpb +cmpb: + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xdead,0xbeef,gr8 + set_icc 0x00,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 1 1 1 1 icc0 + + set_gr_limmed 0x21ad,0xbeef,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 0 1 1 1 icc0 + + set_gr_limmed 0xde52,0xbeef,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 1 0 1 1 icc0 + + set_gr_limmed 0xdead,0x41ef,gr8 + set_icc 0x02,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 1 1 0 1 icc0 + + set_gr_limmed 0xdead,0xbe10,gr8 + set_icc 0x01,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 1 1 1 0 icc0 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + + pass diff --git a/sim/testsuite/frv/cmpba.cgs b/sim/testsuite/frv/cmpba.cgs new file mode 100644 index 0000000..160b9ef --- /dev/null +++ b/sim/testsuite/frv/cmpba.cgs @@ -0,0 +1,41 @@ +# frv testcase for cmpba $GRi,$GRj,$ICCi_1 +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global cmpba +cmpba: + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xdead,0xbeef,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0x21ad,0xbeef,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0xde52,0xbeef,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0xdead,0x41ef,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0xdead,0xbe10,gr8 + set_icc 0x03,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + + pass diff --git a/sim/testsuite/frv/cmpi.cgs b/sim/testsuite/frv/cmpi.cgs new file mode 100644 index 0000000..a8324db --- /dev/null +++ b/sim/testsuite/frv/cmpi.cgs @@ -0,0 +1,50 @@ +# frv testcase for cmpi $GRi,$s12,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global cmpi +cmpi: + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + cmpi gr8,1,icc0 + test_icc 0 0 0 0 icc0 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + cmpi gr8,1,icc0 + test_icc 0 0 1 0 icc0 + + set_gr_immed 0x1ff,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cmpi gr8,0x1ff,icc0 + test_icc 0 1 0 0 icc0 + + set_gr_immed 0,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + cmpi gr8,1,icc0 + test_icc 1 0 0 1 icc0 + + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpi gr8,-1,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + cmpi gr8,-1,icc0 + test_icc 1 0 0 1 icc0 + + set_gr_immed -512,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cmpi gr8,-512,icc0 + test_icc 0 1 0 0 icc0 + + set_gr_immed 0,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpi gr8,-1,icc0 + test_icc 0 0 0 1 icc0 + + pass diff --git a/sim/testsuite/frv/cmqmachs.cgs b/sim/testsuite/frv/cmqmachs.cgs new file mode 100644 index 0000000..4acd62a --- /dev/null +++ b/sim/testsuite/frv/cmqmachs.cgs @@ -0,0 +1,1268 @@ +# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmqmachs +cmqmachs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 +; + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/frv/cmqmachu.cgs b/sim/testsuite/frv/cmqmachu.cgs new file mode 100644 index 0000000..1be1389 --- /dev/null +++ b/sim/testsuite/frv/cmqmachu.cgs @@ -0,0 +1,876 @@ +# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmqmachu +cmqmachu: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 +; + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + pass diff --git a/sim/testsuite/frv/cmqmulhs.cgs b/sim/testsuite/frv/cmqmulhs.cgs new file mode 100644 index 0000000..b315737 --- /dev/null +++ b/sim/testsuite/frv/cmqmulhs.cgs @@ -0,0 +1,734 @@ +# frv testcase for cmqmulhs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmqmulhs +cmqmulhs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x0001,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -2,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -2,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffe,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffe,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xc000,0x8000,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xc000,0x8000,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x40000000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x40000000,acc3 + + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x0001,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -2,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -2,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffe,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffe,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xc000,0x8000,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xc000,0x8000,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x40000000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x40000000,acc3 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 +; + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + pass diff --git a/sim/testsuite/frv/cmqmulhu.cgs b/sim/testsuite/frv/cmqmulhu.cgs new file mode 100644 index 0000000..36f0c2f --- /dev/null +++ b/sim/testsuite/frv/cmqmulhu.cgs @@ -0,0 +1,464 @@ +# frv testcase for cmqmulhu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmqmulhu +cmqmulhu: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00010000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00010000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4000,0x0000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xfffe,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xfffe,0x0001,acc3 + + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00010000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00010000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4000,0x0000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xfffe,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xfffe,0x0001,acc3 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 +; + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + pass diff --git a/sim/testsuite/frv/cmsubhss.cgs b/sim/testsuite/frv/cmsubhss.cgs new file mode 100644 index 0000000..386b27d --- /dev/null +++ b/sim/testsuite/frv/cmsubhss.cgs @@ -0,0 +1,562 @@ +# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmsubhss +cmsubhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc4,1 + cmsubhss fr11,fr10,fr13,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc5,0 + cmsubhss fr11,fr10,fr13,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc4,0 + cmsubhss fr11,fr10,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc5,1 + cmsubhss fr11,fr10,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc6,1 + cmsubhss fr11,fr10,fr13,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc7,1 + cmsubhss fr11,fr10,fr13,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/frv/cmsubhus.cgs b/sim/testsuite/frv/cmsubhus.cgs new file mode 100644 index 0000000..2a8f343 --- /dev/null +++ b/sim/testsuite/frv/cmsubhus.cgs @@ -0,0 +1,442 @@ +# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmsubhus +cmsubhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc4,1 + cmsubhus fr10,fr11,fr13,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc5,0 + cmsubhus fr10,fr11,fr13,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc4,0 + cmsubhus fr10,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc5,1 + cmsubhus fr10,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc6,0 + cmsubhus fr10,fr11,fr13,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc7,0 + cmsubhus fr10,fr11,fr13,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/frv/cmxor.cgs b/sim/testsuite/frv/cmxor.cgs new file mode 100644 index 0000000..236e2fe --- /dev/null +++ b/sim/testsuite/frv/cmxor.cgs @@ -0,0 +1,132 @@ +# frv testcase for cmxor $FRinti,$FRintj,$FRintk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmxor +cmxor: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc4,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc4,1 + test_fr_iimmed 0xdeadbeef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc5,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc5,0 + test_fr_iimmed 0xdeadbeef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc4,0 + test_fr_iimmed 0xaaaaaaaa,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc4,0 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc5,1 + test_fr_iimmed 0xaaaaaaaa,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc5,1 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc2,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc2,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc6,0 + test_fr_iimmed 0xaaaaaaaa,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc6,1 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc3,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc3,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc7,0 + test_fr_iimmed 0xaaaaaaaa,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc7,1 + test_fr_iimmed 0x0000beef,fr8 + + pass diff --git a/sim/testsuite/frv/cnot.cgs b/sim/testsuite/frv/cnot.cgs new file mode 100644 index 0000000..3169887 --- /dev/null +++ b/sim/testsuite/frv/cnot.cgs @@ -0,0 +1,60 @@ +# frv testcase for cnot $GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global cnot +cnot: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc0,1 + test_gr_limmed 0x5555,0x5555,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc4,1 + test_gr_limmed 0x2152,0x4110,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc0,0 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc1,0 + test_gr_limmed 0x5555,0x5555,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc5,0 + test_gr_limmed 0x2152,0x4110,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc1,1 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc2,0 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc6,1 + test_gr_limmed 0xdead,0xbeef,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc3,0 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr7 + + pass diff --git a/sim/testsuite/frv/commitfa.cgs b/sim/testsuite/frv/commitfa.cgs new file mode 100644 index 0000000..8208cab --- /dev/null +++ b/sim/testsuite/frv/commitfa.cgs @@ -0,0 +1,61 @@ +# frv testcase for commitfa +# mach: frv + + .include "testutils.inc" + + start + + .global commitfa +commitfa: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x190,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0,gr15 + + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 + set_spr_immed 0x00000000,fner1 + set_spr_immed 0x00000000,fner0 + set_spr_addr bad,lr + commitfa ; should be nop + test_spr_immed 0x00000000,fner1 + test_spr_immed 0x00000000,fner0 + test_spr_immed 0xd4800001,nesr0 + test_spr_gr neear0,sp + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xf4800801,nesr2 + test_spr_gr neear2,sp + + or_spr_immed 0x00100000,fner1 + or_spr_immed 0x00200000,fner1 + or_spr_immed 0x00100000,fner0 + set_spr_addr ok,lr + set_gr_addr com1,gr16 +com1: commitfa + test_gr_immed 1,gr15 + + pass + +ok: test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr16 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear + test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear + test_spr_immed 0x00000000,fner1 + test_spr_immed 0x00000000,fner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0,nesr2 + test_spr_immed 0,neear2 + inc_gr_immed 1,gr15 + rett 0 + +bad: fail diff --git a/sim/testsuite/frv/commitfr.cgs b/sim/testsuite/frv/commitfr.cgs new file mode 100644 index 0000000..97491dc --- /dev/null +++ b/sim/testsuite/frv/commitfr.cgs @@ -0,0 +1,61 @@ +# frv testcase for commitfr $FRk +# mach: frv + + .include "testutils.inc" + + start + + .global commitfr +commitfr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x190,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0,gr15 + + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 + set_spr_immed 0x00000000,fner1 + set_spr_immed 0x00000000,fner0 + set_spr_addr bad,lr + commitfr fr20 ; should be nop + test_spr_immed 0x00000000,fner1 + test_spr_immed 0x00000000,fner0 + test_spr_immed 0xd4800001,nesr0 + test_spr_gr neear0,sp + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xf4800801,nesr2 + test_spr_gr neear2,sp + + or_spr_immed 0x00100000,fner1 + or_spr_immed 0x00200000,fner1 + or_spr_immed 0x00100000,fner0 + set_spr_addr ok,lr + set_gr_addr com1,gr16 +com1: commitfr fr20 + test_gr_immed 1,gr15 + + pass + +ok: test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr16 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear + test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear + test_spr_immed 0x00200000,fner1 + test_spr_immed 0x00100000,fner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xf4800801,nesr2 + test_spr_gr neear2,sp + inc_gr_immed 1,gr15 + rett 0 + +bad: fail diff --git a/sim/testsuite/frv/commitga.cgs b/sim/testsuite/frv/commitga.cgs new file mode 100644 index 0000000..57100b8 --- /dev/null +++ b/sim/testsuite/frv/commitga.cgs @@ -0,0 +1,62 @@ +# frv testcase for commitga +# mach: frv + + .include "testutils.inc" + + start + + .global commitga +commitga: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x190,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0,gr15 + + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 + set_spr_immed 0x00000000,gner1 + set_spr_immed 0x00000000,gner0 + set_spr_addr bad,lr + commitga ; should be a nop + test_gr_immed 0,gr15 + test_spr_immed 0x00000000,gner1 + test_spr_immed 0x00000000,gner0 + test_spr_immed 0x94800001,nesr0 + test_spr_gr neear0,sp + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xb4800801,nesr2 + test_spr_gr neear2,sp + + or_spr_immed 0x00100000,gner1 + or_spr_immed 0x00200000,gner1 + or_spr_immed 0x00100000,gner0 + set_spr_addr ok,lr + set_gr_addr com1,gr16 +com1: commitga + test_gr_immed 1,gr15 + + pass + +ok: test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr16 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear + test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear + test_spr_immed 0x00000000,gner1 + test_spr_immed 0x00000000,gner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0,nesr2 + test_spr_immed 0,neear0 + inc_gr_immed 1,gr15 + rett 0 + +bad: fail diff --git a/sim/testsuite/frv/commitgr.cgs b/sim/testsuite/frv/commitgr.cgs new file mode 100644 index 0000000..45553da --- /dev/null +++ b/sim/testsuite/frv/commitgr.cgs @@ -0,0 +1,62 @@ +# frv testcase for commitgr $GRk +# mach: frv + + .include "testutils.inc" + + start + + .global commitgr +commitgr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x190,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0,gr15 + + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 + set_spr_immed 0x00000000,gner1 + set_spr_immed 0x00000000,gner0 + set_spr_addr bad,lr + commitgr gr20 ; should only clear ne flags + test_gr_immed 0,gr15 + test_spr_immed 0x00000000,gner1 + test_spr_immed 0x00000000,gner0 + test_spr_immed 0x94800001,nesr0 + test_spr_gr neear0,sp + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xb4800801,nesr2 + test_spr_gr neear2,sp + + or_spr_immed 0x00100000,gner1 + or_spr_immed 0x00200000,gner1 + or_spr_immed 0x00100000,gner0 + set_spr_addr ok,lr + set_gr_addr com1,gr16 +com1: commitgr gr20 + test_gr_immed 1,gr15 + + pass + +ok: test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr16 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear + test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear + test_spr_immed 0x00200000,gner1 + test_spr_immed 0x00100000,gner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xb4800801,nesr2 + test_spr_gr neear2,sp + inc_gr_immed 1,gr15 + rett 0 + +bad: fail diff --git a/sim/testsuite/frv/cop1.cgs b/sim/testsuite/frv/cop1.cgs new file mode 100644 index 0000000..652e355 --- /dev/null +++ b/sim/testsuite/frv/cop1.cgs @@ -0,0 +1,14 @@ +# frv testcase for cop1 $s6_1,$CPRi,$CPRj,$CPRk +# mach: frv + + .include "testutils.inc" + + start + + .global cop1 +cop1: + cop1 0,cpr0,cpr15,cpr31 + cop1 31,cpr32,cpr45,cpr63 + cop1 -32,cpr32,cpr45,cpr63 + + pass diff --git a/sim/testsuite/frv/cop2.cgs b/sim/testsuite/frv/cop2.cgs new file mode 100644 index 0000000..858ed2b --- /dev/null +++ b/sim/testsuite/frv/cop2.cgs @@ -0,0 +1,14 @@ +# frv testcase for cop2 $s6_1,$CPRi,$CPRj,$CPRk +# mach: frv + + .include "testutils.inc" + + start + + .global cop2 +cop2: + cop2 0,cpr0,cpr15,cpr31 + cop2 31,cpr32,cpr45,cpr63 + cop2 -32,cpr32,cpr45,cpr63 + + pass diff --git a/sim/testsuite/frv/cor.cgs b/sim/testsuite/frv/cor.cgs new file mode 100644 index 0000000..ef19985 --- /dev/null +++ b/sim/testsuite/frv/cor.cgs @@ -0,0 +1,138 @@ +# frv testcase for cor $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cor +cor: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc0,1 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc4,1 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc0,0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc4,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc1,0 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc5,0 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc1,1 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc5,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc2,0 + test_icc 0 1 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc6,1 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc3,0 + test_icc 0 1 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc7,1 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/corcc.cgs b/sim/testsuite/frv/corcc.cgs new file mode 100644 index 0000000..5276658 --- /dev/null +++ b/sim/testsuite/frv/corcc.cgs @@ -0,0 +1,138 @@ +# frv testcase for corcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global corcc +corcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc6,1 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc7,1 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/cscan.cgs b/sim/testsuite/frv/cscan.cgs new file mode 100644 index 0000000..505bb5a --- /dev/null +++ b/sim/testsuite/frv/cscan.cgs @@ -0,0 +1,394 @@ +# frv testcase for cscan $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cscan +cscan: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0x5555,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0x5555,gr8 + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc4,1 + test_gr_immed 2,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc4,1 + test_gr_immed 16,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc4,1 + test_gr_immed 31,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc4,1 + test_gr_immed 7,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0x7fff,gr9 + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xaaaa,0xaaab,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaab,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5554,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5554,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc4,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc4,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc4,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc4,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc5,0 + test_gr_immed 2,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc5,0 + test_gr_immed 16,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc5,0 + test_gr_immed 31,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc5,0 + test_gr_immed 7,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0x7fff,gr9 + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xaaaa,0xaaab,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaab,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5554,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5554,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc5,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc5,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc5,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc5,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0x7fff,gr9 + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc2,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xaaaa,0xaaab,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc2,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaab,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc2,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5554,gr8 + cscan gr7,gr8,gr9,cc2,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5554,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc2,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc6,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc6,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc6,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc6,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0x7fff,gr9 + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc3,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xaaaa,0xaaab,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc3,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaab,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc3,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5554,gr8 + cscan gr7,gr8,gr9,cc3,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5554,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc3,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc7,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc7,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc7,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc7,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/frv/csdiv.cgs b/sim/testsuite/frv/csdiv.cgs new file mode 100644 index 0000000..c6bfb97 --- /dev/null +++ b/sim/testsuite/frv/csdiv.cgs @@ -0,0 +1,190 @@ +# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csdiv +csdiv: + set_spr_immed 0x1b1b,cccr + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e1,gr17 + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e1: csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e2,gr17 + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e2: csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed 2,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/csll.cgs b/sim/testsuite/frv/csll.cgs new file mode 100644 index 0000000..0186756 --- /dev/null +++ b/sim/testsuite/frv/csll.cgs @@ -0,0 +1,180 @@ +# frv testcase for csll $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csll +csll: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc0,1 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc0,1 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc0,0 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc4,0 + test_icc 0 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc1,0 + test_icc 1 1 0 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc1,0 + test_icc 1 1 1 1 icc1 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc1,1 + test_icc 1 1 0 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc5,1 + test_icc 0 1 1 1 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc2,0 + test_icc 1 1 0 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc6,1 + test_icc 0 1 1 1 icc2 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc3,0 + test_icc 1 1 0 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc7,1 + test_icc 0 1 1 1 icc3 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_immed 2,gr8 + + pass diff --git a/sim/testsuite/frv/csllcc.cgs b/sim/testsuite/frv/csllcc.cgs new file mode 100644 index 0000000..0c5b9af --- /dev/null +++ b/sim/testsuite/frv/csllcc.cgs @@ -0,0 +1,180 @@ +# frv testcase for csllcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csllcc +csllcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc4,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc4,1 + test_icc 0 1 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc4,0 + test_icc 0 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc5,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc5,0 + test_icc 0 1 1 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 0 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc5,1 + test_icc 0 1 1 1 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 0 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc6,1 + test_icc 0 1 1 1 icc2 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 0 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc7,1 + test_icc 0 1 1 1 icc3 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_immed 2,gr8 + + pass diff --git a/sim/testsuite/frv/csmul.cgs b/sim/testsuite/frv/csmul.cgs new file mode 100644 index 0000000..25346e7 --- /dev/null +++ b/sim/testsuite/frv/csmul.cgs @@ -0,0 +1,1044 @@ +# frv testcase for csmul $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csmul +csmul: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + pass diff --git a/sim/testsuite/frv/csmulcc.cgs b/sim/testsuite/frv/csmulcc.cgs new file mode 100644 index 0000000..26c7e66 --- /dev/null +++ b/sim/testsuite/frv/csmulcc.cgs @@ -0,0 +1,1380 @@ +# frv testcase for csmulcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csmulcc +csmulcc: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0xb,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x8,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0xf,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 1 icc0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x5,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x6,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x4,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0x9,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xa,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x4,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x5,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x6,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xf,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 0 0 0 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 0 0 1 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 0 1 0 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x3,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 0 1 1 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x4,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x5,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x6,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 1 0 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 1 1 icc0 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x8,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x9,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 1 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xa,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xb,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 1 0 0 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 1 0 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x0,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 0 0 0 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x1,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 0 0 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x2,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 0 1 0 icc0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x3,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x4,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 0 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x5,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0x6,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 1 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x8,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x9,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 1 icc0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xa,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xb,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0xb,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x8,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0xf,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 1 icc1 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x5,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 1 icc1 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x6,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 1 icc1 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x4,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0x9,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 1 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xa,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 1 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x4,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x5,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x6,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 1 icc1 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xf,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 1 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 0 0 0 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 0 0 1 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 0 1 0 icc1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x3,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 0 1 1 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x4,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x5,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x6,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 1 0 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 1 1 icc1 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x8,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x9,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 1 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xa,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xb,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 1 0 0 icc1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 1 0 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 1 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x0,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 0 0 0 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x1,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 0 0 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x2,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 0 1 0 icc1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x3,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 0 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x4,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 0 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x5,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0x6,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 1 0 icc1 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 1 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x8,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x9,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 1 icc1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xa,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xb,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 0 0 0 0 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 0 0 0 1 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 0 0 1 0 icc2 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x3,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 0 0 1 1 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x4,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 0 icc2 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x5,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 0 1 0 1 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x6,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 0 1 1 0 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0x7,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 0 1 1 1 icc2 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x8,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 1 0 0 0 icc2 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x9,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 1 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xa,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xb,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 1 0 1 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xc,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 1 1 0 0 icc2 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0xd,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 1 1 0 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xe,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 1 1 1 0 icc2 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 1 1 1 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x0,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 0 0 0 0 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x1,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 0 0 0 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x2,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 0 0 1 0 icc2 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x3,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 0 0 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x4,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 0 1 0 0 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x5,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0x6,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 0 1 1 0 icc2 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 0 1 1 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x8,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 1 0 0 0 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x9,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 1 icc2 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xa,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xb,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 0 0 0 0 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 0 0 0 1 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 0 0 1 0 icc3 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x3,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 0 0 1 1 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x4,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 0 icc3 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x5,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 0 1 0 1 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x6,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 0 1 1 0 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0x7,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 0 1 1 1 icc3 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x8,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 1 0 0 0 icc3 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x9,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 1 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xa,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xb,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 1 0 1 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xc,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 1 1 0 0 icc3 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0xd,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 1 1 0 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xe,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 1 1 1 0 icc3 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 1 1 1 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x0,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 0 0 0 0 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x1,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 0 0 0 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x2,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 0 0 1 0 icc3 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x3,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 0 0 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x4,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 0 1 0 0 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x5,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0x6,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 0 1 1 0 icc3 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 0 1 1 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x8,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 1 0 0 0 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x9,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 1 icc3 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xa,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xb,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + pass diff --git a/sim/testsuite/frv/csra.cgs b/sim/testsuite/frv/csra.cgs new file mode 100644 index 0000000..f59de05 --- /dev/null +++ b/sim/testsuite/frv/csra.cgs @@ -0,0 +1,180 @@ +# frv testcase for csra $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csra +csra: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc0,1 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc0,1 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc4,1 + test_icc 1 1 1 1 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc1,0 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc1,0 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc5,0 + test_icc 1 1 1 1 icc1 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc6,1 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc7,1 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x4000,0x0000,gr8 + + pass diff --git a/sim/testsuite/frv/csracc.cgs b/sim/testsuite/frv/csracc.cgs new file mode 100644 index 0000000..64d4cbf --- /dev/null +++ b/sim/testsuite/frv/csracc.cgs @@ -0,0 +1,180 @@ +# frv testcase for csracc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csracc +csracc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc0,1 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc1,0 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc6,1 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc7,1 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x4000,0x0000,gr8 + + pass diff --git a/sim/testsuite/frv/csrl.cgs b/sim/testsuite/frv/csrl.cgs new file mode 100644 index 0000000..7a71db4 --- /dev/null +++ b/sim/testsuite/frv/csrl.cgs @@ -0,0 +1,180 @@ +# frv testcase for csrl $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csrl +csrl: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc0,1 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc0,1 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc4,1 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc1,0 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc1,0 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc5,0 + test_icc 1 1 1 1 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc6,1 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc7,1 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x4000,0x0000,gr8 + + pass diff --git a/sim/testsuite/frv/csrlcc.cgs b/sim/testsuite/frv/csrlcc.cgs new file mode 100644 index 0000000..fb89456 --- /dev/null +++ b/sim/testsuite/frv/csrlcc.cgs @@ -0,0 +1,180 @@ +# frv testcase for csrlcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csrlcc +csrlcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc6,1 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc7,1 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x4000,0x0000,gr8 + + pass diff --git a/sim/testsuite/frv/cst.cgs b/sim/testsuite/frv/cst.cgs new file mode 100644 index 0000000..8244edf --- /dev/null +++ b/sim/testsuite/frv/cst.cgs @@ -0,0 +1,126 @@ +# frv testcase for cst $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global cst +cst: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xffff,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xeeee,0xffff,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xcccc,0xdddd,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xffff,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xeeee,0xffff,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xcccc,0xdddd,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + pass diff --git a/sim/testsuite/frv/cstb.cgs b/sim/testsuite/frv/cstb.cgs new file mode 100644 index 0000000..7b62558 --- /dev/null +++ b/sim/testsuite/frv/cstb.cgs @@ -0,0 +1,120 @@ +# frv testcase for cstb $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xeeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc4,1 + inc_gr_immed -4,sp + test_mem_limmed 0xffad,0xee00,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc4,0 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xeeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc5,0 + inc_gr_immed -4,sp + test_mem_limmed 0xffad,0xee00,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc5,1 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc6,0 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc7,1 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/cstbf.cgs b/sim/testsuite/frv/cstbf.cgs new file mode 100644 index 0000000..23e1ae4 --- /dev/null +++ b/sim/testsuite/frv/cstbf.cgs @@ -0,0 +1,120 @@ +# frv testcase for cstbf $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstbf +cstbf: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xaaef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffad,0xaabb,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xaaef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffad,0xaabb,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + pass diff --git a/sim/testsuite/frv/cstbfu.cgs b/sim/testsuite/frv/cstbfu.cgs new file mode 100644 index 0000000..01943be --- /dev/null +++ b/sim/testsuite/frv/cstbfu.cgs @@ -0,0 +1,152 @@ +# frv testcase for cstbfu $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstbfu +cstbfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,gr21 + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xaaef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 1,gr21 + inc_gr_immed 2,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffad,0xaabb,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,gr21 + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xaaef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 1,gr21 + inc_gr_immed 2,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffad,0xaabb,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + pass diff --git a/sim/testsuite/frv/cstbu.cgs b/sim/testsuite/frv/cstbu.cgs new file mode 100644 index 0000000..f8a9d0f --- /dev/null +++ b/sim/testsuite/frv/cstbu.cgs @@ -0,0 +1,152 @@ +# frv testcase for cstbu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstbu +cstbu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xbeef,sp + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xeeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed -1,gr7 + inc_gr_immed 2,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc4,1 + inc_gr_immed -4,sp + test_mem_limmed 0xffad,0xee00,gr21 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed -1,gr7 + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xbeef,sp + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xeeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed -1,gr7 + inc_gr_immed 2,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc5,0 + inc_gr_immed -4,sp + test_mem_limmed 0xffad,0xee00,gr21 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed -1,gr7 + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed -1,gr7 + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed -1,gr7 + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/cstd.cgs b/sim/testsuite/frv/cstd.cgs new file mode 100644 index 0000000..6904414 --- /dev/null +++ b/sim/testsuite/frv/cstd.cgs @@ -0,0 +1,221 @@ +# frv testcase for cstd $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global cstd +cstd: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + pass diff --git a/sim/testsuite/frv/cstdf.cgs b/sim/testsuite/frv/cstdf.cgs new file mode 100644 index 0000000..fabbe93 --- /dev/null +++ b/sim/testsuite/frv/cstdf.cgs @@ -0,0 +1,222 @@ +# frv testcase for cstdf $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstdf +cstdf: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc0,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc0,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xaaaa,0xaaaa,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbbbb,0xbbbb,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc4,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xcccc,0xcccc,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdddd,0xdddd,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc0,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc0,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc4,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc1,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc1,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xaaaa,0xaaaa,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbbbb,0xbbbb,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc5,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xcccc,0xcccc,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdddd,0xdddd,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc1,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc1,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc5,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc2,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc2,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc6,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc3,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc3,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc7,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + pass diff --git a/sim/testsuite/frv/cstdfu.cgs b/sim/testsuite/frv/cstdfu.cgs new file mode 100644 index 0000000..b489bc9 --- /dev/null +++ b/sim/testsuite/frv/cstdfu.cgs @@ -0,0 +1,248 @@ +# frv testcase for cstdfu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstdfu +cstdfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc0,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc0,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xaaaa,0xaaaa,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbbbb,0xbbbb,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc4,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xcccc,0xcccc,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdddd,0xdddd,gr22 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc0,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_gr sp,gr23 + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc0,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + inc_gr_immed 16,sp + set_gr_gr sp,gr23 + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc4,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc1,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc1,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xaaaa,0xaaaa,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbbbb,0xbbbb,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc5,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xcccc,0xcccc,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdddd,0xdddd,gr22 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc1,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_gr sp,gr23 + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc1,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + inc_gr_immed 16,sp + set_gr_gr sp,gr23 + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc5,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc2,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_gr sp,gr23 + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc2,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + inc_gr_immed 16,sp + set_gr_gr sp,gr23 + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc6,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc3,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_gr sp,gr23 + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc3,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + inc_gr_immed 16,sp + set_gr_gr sp,gr23 + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc7,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + pass diff --git a/sim/testsuite/frv/cstdu.cgs b/sim/testsuite/frv/cstdu.cgs new file mode 100644 index 0000000..a996ef6 --- /dev/null +++ b/sim/testsuite/frv/cstdu.cgs @@ -0,0 +1,251 @@ +# frv testcase for cstdu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstdu +cstdu: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_gr sp,gr22 + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_gr sp,gr22 + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_gr sp,gr22 + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_gr sp,gr22 + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_gr sp,gr22 + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_gr sp,gr22 + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_gr sp,gr22 + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_gr sp,gr22 + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_gr sp,gr22 + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_gr sp,gr22 + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_gr sp,gr22 + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_gr sp,gr22 + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + pass diff --git a/sim/testsuite/frv/cstf.cgs b/sim/testsuite/frv/cstf.cgs new file mode 100644 index 0000000..94c0f05 --- /dev/null +++ b/sim/testsuite/frv/cstf.cgs @@ -0,0 +1,126 @@ +# frv testcase for cstf $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstf +cstf: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xffff,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xeeee,0xeeee,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xdddd,0xdddd,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xffff,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xeeee,0xeeee,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xdddd,0xdddd,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + pass diff --git a/sim/testsuite/frv/cstfu.cgs b/sim/testsuite/frv/cstfu.cgs new file mode 100644 index 0000000..ee450c8 --- /dev/null +++ b/sim/testsuite/frv/cstfu.cgs @@ -0,0 +1,158 @@ +# frv testcase for cstfu $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstfu +cstfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xffff,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 4,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xdddd,0xdddd,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + inc_gr_immed -4,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + inc_gr_immed 8,gr21 + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xffff,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 4,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xdddd,0xdddd,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + inc_gr_immed -4,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + inc_gr_immed 8,gr21 + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + inc_gr_immed -4,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + inc_gr_immed 8,gr21 + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + inc_gr_immed -4,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + inc_gr_immed 8,gr21 + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + pass diff --git a/sim/testsuite/frv/csth.cgs b/sim/testsuite/frv/csth.cgs new file mode 100644 index 0000000..b9f743c --- /dev/null +++ b/sim/testsuite/frv/csth.cgs @@ -0,0 +1,120 @@ +# frv testcase for csth $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csth +csth: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xeeee,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc4,1 + inc_gr_immed -4,sp + test_mem_limmed 0xffff,0xdddd,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc4,0 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xeeee,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc5,0 + inc_gr_immed -4,sp + test_mem_limmed 0xffff,0xdddd,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc5,1 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc6,0 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc7,1 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/csthf.cgs b/sim/testsuite/frv/csthf.cgs new file mode 100644 index 0000000..21a64c8 --- /dev/null +++ b/sim/testsuite/frv/csthf.cgs @@ -0,0 +1,120 @@ +# frv testcase for csthf $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csthf +csthf: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xaaaa,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffff,0xbbbb,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xaaaa,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffff,0xbbbb,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + pass diff --git a/sim/testsuite/frv/csthfu.cgs b/sim/testsuite/frv/csthfu.cgs new file mode 100644 index 0000000..252ae7d --- /dev/null +++ b/sim/testsuite/frv/csthfu.cgs @@ -0,0 +1,150 @@ +# frv testcase for csthfu $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csthfu +csthfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,gr21 + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xaaaa,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffff,0xbbbb,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,gr21 + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xaaaa,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffff,0xbbbb,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + pass diff --git a/sim/testsuite/frv/csthu.cgs b/sim/testsuite/frv/csthu.cgs new file mode 100644 index 0000000..c7e2255 --- /dev/null +++ b/sim/testsuite/frv/csthu.cgs @@ -0,0 +1,150 @@ +# frv testcase for csthu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csthu +csthu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + set_gr_limmed 0xdead,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xeeee,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 2,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffff,0xdddd,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,gr20 + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + set_gr_limmed 0xdead,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xeeee,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 2,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffff,0xdddd,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/cstq.cgs b/sim/testsuite/frv/cstq.cgs new file mode 100644 index 0000000..6f18332 --- /dev/null +++ b/sim/testsuite/frv/cstq.cgs @@ -0,0 +1,355 @@ +# frv testcase for cstq $GRk,@($GRi,$GRj),$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global cstq +cstq: + set_spr_immed 0x1b1b,cccr + + set_gr_gr sp,gr22 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xbeef,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0x1111,0x1111,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x2222,0x2222,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x3333,0x3333,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x4444,0x4444,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xbeef,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0x1111,0x1111,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x2222,0x2222,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x3333,0x3333,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x4444,0x4444,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + pass diff --git a/sim/testsuite/frv/cstu.cgs b/sim/testsuite/frv/cstu.cgs new file mode 100644 index 0000000..81a5b82 --- /dev/null +++ b/sim/testsuite/frv/cstu.cgs @@ -0,0 +1,152 @@ +# frv testcase for cstu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstu +cstu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xffff,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xeeee,0xffff,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xcccc,0xdddd,gr21 + test_gr_gr sp,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_gr sp,gr20 + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 8,sp + set_gr_gr sp,gr20 + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xffff,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xeeee,0xffff,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xcccc,0xdddd,gr21 + test_gr_gr sp,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_gr sp,gr20 + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 8,sp + set_gr_gr sp,gr20 + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_gr sp,gr20 + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 8,sp + set_gr_gr sp,gr20 + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_gr sp,gr20 + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 8,sp + set_gr_gr sp,gr20 + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/csub.cgs b/sim/testsuite/frv/csub.cgs new file mode 100644 index 0000000..7d07c14 --- /dev/null +++ b/sim/testsuite/frv/csub.cgs @@ -0,0 +1,108 @@ +# frv testcase for csub $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csub +csub: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc4,1 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc4,1 + test_gr_limmed 0x7fff,0xffff,gr8 + + csub gr8,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + + csub gr8,gr7,gr8,cc4,1 + test_gr_immed -1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc4,0 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr8,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr7,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc5,0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc5,0 + test_gr_limmed 0x7fff,0xffff,gr8 + + csub gr8,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + + csub gr8,gr7,gr8,cc5,0 + test_gr_immed -1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc5,1 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr8,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr7,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc6,1 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc6,0 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr8,gr8,cc6,1 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr7,gr8,cc6,0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc7,0 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc7,1 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr8,gr8,cc7,0 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr7,gr8,cc7,1 + test_gr_limmed 0x8000,0x0000,gr8 + + pass diff --git a/sim/testsuite/frv/csubcc.cgs b/sim/testsuite/frv/csubcc.cgs new file mode 100644 index 0000000..64cd93b --- /dev/null +++ b/sim/testsuite/frv/csubcc.cgs @@ -0,0 +1,156 @@ +# frv testcase for csubcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csubcc +csubcc: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0b,0 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc4,1 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc4,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x0b,0 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc4,0 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 1 0 icc1 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0b,1 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc5,0 + test_icc 0 1 0 0 icc1 + test_gr_immed 0,gr8 + + set_icc 0x06,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc5,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x0b,1 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x06,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc5,1 + test_icc 0 1 1 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x0b,2 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc6,1 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x06,2 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc6,1 + test_icc 0 1 1 0 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x0b,3 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc7,1 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x06,3 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc7,1 + test_icc 0 1 1 0 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + pass diff --git a/sim/testsuite/frv/cswap.cgs b/sim/testsuite/frv/cswap.cgs new file mode 100644 index 0000000..19a51d5 --- /dev/null +++ b/sim/testsuite/frv/cswap.cgs @@ -0,0 +1,212 @@ +# frv testcase for cswap @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cswap +cswap: + set_spr_immed 0x1b1b,cccr + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xbeef,0xdead,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xbeef,0xdead,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + pass diff --git a/sim/testsuite/frv/cudiv.cgs b/sim/testsuite/frv/cudiv.cgs new file mode 100644 index 0000000..78f44ae --- /dev/null +++ b/sim/testsuite/frv/cudiv.cgs @@ -0,0 +1,96 @@ +# frv testcase for cudiv $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cudiv +cudiv: + set_spr_immed 0x1b1b,cccr + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc0,1 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc4,1 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc0,0 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x0000000c,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc4,0 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_limmed 0xfedc,0xba98,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc1,0 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc5,0 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc1,1 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x0000000c,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc5,1 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_limmed 0xfedc,0xba98,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc2,0 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x0000000c,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc6,1 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_limmed 0xfedc,0xba98,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc3,0 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x0000000c,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc7,1 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_limmed 0xfedc,0xba98,gr3 + + pass diff --git a/sim/testsuite/frv/cxor.cgs b/sim/testsuite/frv/cxor.cgs new file mode 100644 index 0000000..54a672d --- /dev/null +++ b/sim/testsuite/frv/cxor.cgs @@ -0,0 +1,180 @@ +# frv testcase for cxor $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cxor +cxor: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc0,1 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc4,1 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc0,0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc4,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc1,0 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 1 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc5,0 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc1,1 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc5,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc2,0 + test_icc 0 1 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,2 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc6,1 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc6,1 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc3,0 + test_icc 0 1 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,3 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc7,1 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc7,1 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/cxorcc.cgs b/sim/testsuite/frv/cxorcc.cgs new file mode 100644 index 0000000..86d917d --- /dev/null +++ b/sim/testsuite/frv/cxorcc.cgs @@ -0,0 +1,180 @@ +# frv testcase for cxorcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cxorcc +cxorcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,2 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc6,1 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc6,1 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,3 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc7,1 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc7,1 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/dcef.cgs b/sim/testsuite/frv/dcef.cgs new file mode 100644 index 0000000..74475ef --- /dev/null +++ b/sim/testsuite/frv/dcef.cgs @@ -0,0 +1,50 @@ +# frv testcase for dcef @(GRi,GRj),a +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global dcef +dcef: + and_spr_immed 0x7fffffff,hsr0 ; data cache only: copy-back mode + set_gr_addr doit,gr10 + set_gr_immed 0,gr11 + set_gr_immed 1,gr12 + set_gr_immed 2,gr13 + set_gr_immed 3,gr14 + + set_spr_addr ok1,lr + bra doit +ok1: test_gr_immed 1,gr11 + + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache + set_spr_addr ok2,lr + bra doit +ok2: test_gr_immed 2,gr11 ; still only added 1 + + set_gr_addr doit1,gr10 + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache + dcef @(gr10,gr0),1 ; flush data cache + set_spr_addr ok3,lr + bra doit1 +ok3: test_gr_immed 4,gr11 ; added 2 this time + + set_gr_addr doit2,gr10 + set_mem_immed 0x9600b00e,gr10 ; change to add gr11,gr14,gr11 in cache + dcef @(gr0,gr0),1 ; flush data cache + set_spr_addr ok4,lr + bra doit2 +ok4: test_gr_immed 7,gr11 ; added 3 this time + + pass + +doit: add gr11,gr12,gr11 + bralr + +doit1: add gr11,gr12,gr11 + bralr + +doit2: add gr11,gr12,gr11 + bralr + diff --git a/sim/testsuite/frv/dcei.cgs b/sim/testsuite/frv/dcei.cgs new file mode 100644 index 0000000..6254c06 --- /dev/null +++ b/sim/testsuite/frv/dcei.cgs @@ -0,0 +1,27 @@ +# frv testcase for dcei @(GRi,GRj),a +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global dcei +dcei: + or_spr_immed 0x08000000,hsr0 ; data cache: copy-back mode + + set_mem_immed 0xdeadbeef,sp + test_mem_immed 0xdeadbeef,sp + + flush_data_cache sp + set_mem_immed 0xbeefdead,sp + test_mem_immed 0xbeefdead,sp + + dcei @(sp,gr0),1 + test_mem_immed 0xdeadbeef,sp + + set_mem_immed 0xbeefdead,sp + test_mem_immed 0xbeefdead,sp + dcei @(gr0,gr0),1 + test_mem_immed 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/frv/dcf.cgs b/sim/testsuite/frv/dcf.cgs new file mode 100644 index 0000000..f6e670e --- /dev/null +++ b/sim/testsuite/frv/dcf.cgs @@ -0,0 +1,39 @@ +# FRV testcase for dcf @(GRi,GRj) +# mach: all + + .include "testutils.inc" + + start + + .global dcf +dcf: + and_spr_immed 0x7fffffff,hsr0 ; data cache only: copy-back mode + set_gr_addr doit,gr10 + set_gr_immed 0,gr11 + set_gr_immed 1,gr12 + set_gr_immed 2,gr13 + + set_spr_addr ok1,lr + bra doit +ok1: test_gr_immed 1,gr11 + + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache + set_spr_addr ok2,lr + bra doit +ok2: test_gr_immed 2,gr11 ; still only added 1 + + set_gr_addr doit1,gr10 + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache + dcf @(gr10,gr0) ; flush data cache + set_spr_addr ok3,lr + bra doit1 +ok3: test_gr_immed 4,gr11 ; added 2 this time + + pass + +doit: add gr11,gr12,gr11 + bralr + +doit1: add gr11,gr12,gr11 + bralr + diff --git a/sim/testsuite/frv/dci.cgs b/sim/testsuite/frv/dci.cgs new file mode 100644 index 0000000..de481c3 --- /dev/null +++ b/sim/testsuite/frv/dci.cgs @@ -0,0 +1,22 @@ +# FRV testcase for dci @(GRi,GRj) +# mach: all + + .include "testutils.inc" + + start + + .global dci +dci: + or_spr_immed 0x08000000,hsr0 ; data cache: copy-back mode + + set_mem_immed 0xdeadbeef,sp + test_mem_immed 0xdeadbeef,sp + + flush_data_cache sp + set_mem_immed 0xbeefdead,sp + test_mem_immed 0xbeefdead,sp + + dci @(sp,gr0) + test_mem_immed 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/frv/exit47.ms b/sim/testsuite/frv/exit47.ms new file mode 100644 index 0000000..53306e5 --- /dev/null +++ b/sim/testsuite/frv/exit47.ms @@ -0,0 +1,11 @@ +# mach: all +# status: 47 +# output: + + ;; Return with exit code 47. + + .global _start +_start: + setlos #47,gr8 + setlos #1,gr7 + tira gr0,#0 diff --git a/sim/testsuite/frv/fabsd.cgs b/sim/testsuite/frv/fabsd.cgs new file mode 100644 index 0000000..41a485e --- /dev/null +++ b/sim/testsuite/frv/fabsd.cgs @@ -0,0 +1,26 @@ +# frv testcase for fabsd $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fabsd +fabsd: + fabsd fr0,fr2 + test_dfr_dfr fr2,fr52 + fabsd fr8,fr2 + test_dfr_dfr fr2,fr28 + fabsd fr12,fr2 + test_dfr_dfr fr2,fr24 + fabsd fr24,fr2 + test_dfr_dfr fr2,fr24 + fabsd fr28,fr2 + test_dfr_dfr fr2,fr28 + fabsd fr52,fr2 + test_dfr_dfr fr2,fr52 + + pass diff --git a/sim/testsuite/frv/fabss.cgs b/sim/testsuite/frv/fabss.cgs new file mode 100644 index 0000000..f48514a --- /dev/null +++ b/sim/testsuite/frv/fabss.cgs @@ -0,0 +1,25 @@ +# frv testcase for fabss $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fabss +fabss: + fabss fr0,fr1 + test_fr_fr fr1,fr52 + fabss fr8,fr1 + test_fr_fr fr1,fr28 + fabss fr12,fr1 + test_fr_fr fr1,fr24 + fabss fr24,fr1 + test_fr_fr fr1,fr24 + fabss fr28,fr1 + test_fr_fr fr1,fr28 + fabss fr52,fr1 + test_fr_fr fr1,fr52 + + pass diff --git a/sim/testsuite/frv/faddd.cgs b/sim/testsuite/frv/faddd.cgs new file mode 100644 index 0000000..dbb6373 --- /dev/null +++ b/sim/testsuite/frv/faddd.cgs @@ -0,0 +1,93 @@ +# frv testcase for faddd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global faddd +faddd: + faddd fr16,fr0,fr2 + test_dfr_dfr fr2,fr0 + faddd fr16,fr4,fr2 + test_dfr_dfr fr2,fr4 + faddd fr16,fr8,fr2 + test_dfr_dfr fr2,fr8 + faddd fr16,fr12,fr2 + test_dfr_dfr fr2,fr12 + faddd fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr16,fr20,fr2 + test_dfr_dfr fr2,fr26 + test_dfr_dfr fr2,fr20 + faddd fr16,fr24,fr2 + test_dfr_dfr fr2,fr24 + faddd fr16,fr28,fr2 + test_dfr_dfr fr2,fr28 + faddd fr16,fr32,fr2 + test_dfr_dfr fr2,fr32 + faddd fr16,fr36,fr2 + test_dfr_dfr fr2,fr36 + faddd fr16,fr40,fr2 + test_dfr_dfr fr2,fr40 + faddd fr16,fr44,fr2 + test_dfr_dfr fr2,fr44 + faddd fr16,fr48,fr2 + test_dfr_dfr fr2,fr48 + faddd fr16,fr52,fr2 + test_dfr_dfr fr2,fr52 + + faddd fr20,fr0,fr2 + test_dfr_dfr fr2,fr0 + faddd fr20,fr4,fr2 + test_dfr_dfr fr2,fr4 + faddd fr20,fr8,fr2 + test_dfr_dfr fr2,fr8 + faddd fr20,fr12,fr2 + test_dfr_dfr fr2,fr12 + faddd fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr20,fr20,fr2 + test_dfr_dfr fr2,fr26 + test_dfr_dfr fr2,fr20 + faddd fr20,fr24,fr2 + test_dfr_dfr fr2,fr24 + faddd fr20,fr28,fr2 + test_dfr_dfr fr2,fr28 + faddd fr20,fr32,fr2 + test_dfr_dfr fr2,fr32 + faddd fr20,fr36,fr2 + test_dfr_dfr fr2,fr36 + faddd fr20,fr40,fr2 + test_dfr_dfr fr2,fr40 + faddd fr20,fr44,fr2 + test_dfr_dfr fr2,fr44 + faddd fr20,fr48,fr2 + test_dfr_dfr fr2,fr48 + faddd fr20,fr52,fr2 + test_dfr_dfr fr2,fr52 + + faddd fr8,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr12,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr24,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr28,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + faddd fr36,fr40,fr2 + test_dfr_dfr fr2,fr44 + + pass + + diff --git a/sim/testsuite/frv/fadds.cgs b/sim/testsuite/frv/fadds.cgs new file mode 100644 index 0000000..d741ac9 --- /dev/null +++ b/sim/testsuite/frv/fadds.cgs @@ -0,0 +1,92 @@ +# frv testcase for fadds $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fadds +fadds: + fadds fr16,fr0,fr1 + test_fr_fr fr1,fr0 + fadds fr16,fr4,fr1 + test_fr_fr fr1,fr4 + fadds fr16,fr8,fr1 + test_fr_fr fr1,fr8 + fadds fr16,fr12,fr1 + test_fr_fr fr1,fr12 + fadds fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr16,fr24,fr1 + test_fr_fr fr1,fr24 + fadds fr16,fr28,fr1 + test_fr_fr fr1,fr28 + fadds fr16,fr32,fr1 + test_fr_fr fr1,fr32 + fadds fr16,fr36,fr1 + test_fr_fr fr1,fr36 + fadds fr16,fr40,fr1 + test_fr_fr fr1,fr40 + fadds fr16,fr44,fr1 + test_fr_fr fr1,fr44 + fadds fr16,fr48,fr1 + test_fr_fr fr1,fr48 + fadds fr16,fr52,fr1 + test_fr_fr fr1,fr52 + + fadds fr20,fr0,fr1 + test_fr_fr fr1,fr0 + fadds fr20,fr4,fr1 + test_fr_fr fr1,fr4 + fadds fr20,fr8,fr1 + test_fr_fr fr1,fr8 + fadds fr20,fr12,fr1 + test_fr_fr fr1,fr12 + fadds fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr20,fr24,fr1 + test_fr_fr fr1,fr24 + fadds fr20,fr28,fr1 + test_fr_fr fr1,fr28 + fadds fr20,fr32,fr1 + test_fr_fr fr1,fr32 + fadds fr20,fr36,fr1 + test_fr_fr fr1,fr36 + fadds fr20,fr40,fr1 + test_fr_fr fr1,fr40 + fadds fr20,fr44,fr1 + test_fr_fr fr1,fr44 + fadds fr20,fr48,fr1 + test_fr_fr fr1,fr48 + fadds fr20,fr52,fr1 + test_fr_fr fr1,fr52 + + fadds fr8,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr12,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr24,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr28,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fadds fr36,fr40,fr1 + test_fr_fr fr1,fr44 + + pass + + diff --git a/sim/testsuite/frv/fbeq.cgs b/sim/testsuite/frv/fbeq.cgs new file mode 100644 index 0000000..e51b2c9 --- /dev/null +++ b/sim/testsuite/frv/fbeq.cgs @@ -0,0 +1,61 @@ +# frv testcase for fbeq $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbeq +fbeq: + set_fcc 0x0 0 + fbeq fcc0,0,bad + set_fcc 0x1 1 + fbeq fcc1,1,bad + set_fcc 0x2 2 + fbeq fcc2,2,bad + set_fcc 0x3 3 + fbeq fcc3,3,bad + set_fcc 0x4 0 + fbeq fcc0,0,bad + set_fcc 0x5 1 + fbeq fcc1,1,bad + set_fcc 0x6 2 + fbeq fcc2,2,bad + set_fcc 0x7 3 + fbeq fcc3,3,bad + set_fcc 0x8 0 + fbeq fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbeq fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbeq fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbeq fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbeq fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbeq fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbeq fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbeq fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbeqlr.cgs b/sim/testsuite/frv/fbeqlr.cgs new file mode 100644 index 0000000..af29cb9 --- /dev/null +++ b/sim/testsuite/frv/fbeqlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for fbeqlr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbeqlr +fbeqlr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbeqlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbeqlr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fbeqlr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fbeqlr fcc3,3 + + set_spr_addr bad,lr + set_fcc 0x4 0 + fbeqlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fbeqlr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0x6 2 + fbeqlr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0x7 3 + fbeqlr fcc3,3 + + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbeqlr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbeqlr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbeqlr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbeqlr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbeqlr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbeqlr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbeqlr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbeqlr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fbge.cgs b/sim/testsuite/frv/fbge.cgs new file mode 100644 index 0000000..a20029e --- /dev/null +++ b/sim/testsuite/frv/fbge.cgs @@ -0,0 +1,69 @@ +# frv testcase for fbge $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbge +fbge: + set_fcc 0x0 0 + fbge fcc0,0,bad + set_fcc 0x1 1 + fbge fcc1,1,bad + set_fcc 0x2 2 + fbge fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbge fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbge fcc0,0,bad + set_fcc 0x5 1 + fbge fcc1,1,bad + set_fcc 0x6 2 + fbge fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbge fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbge fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbge fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbge fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbge fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbge fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbge fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbge fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbge fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbgelr.cgs b/sim/testsuite/frv/fbgelr.cgs new file mode 100644 index 0000000..59e9410 --- /dev/null +++ b/sim/testsuite/frv/fbgelr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fbgelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbgelr +fbgelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbgelr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbgelr fcc1,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbgelr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbgelr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbgelr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fbgelr fcc1,1 + + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbgelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbgelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbgelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbgelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbgelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbgelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbgelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbgelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbgelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbgelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fbgt.cgs b/sim/testsuite/frv/fbgt.cgs new file mode 100644 index 0000000..7cc4ea7 --- /dev/null +++ b/sim/testsuite/frv/fbgt.cgs @@ -0,0 +1,61 @@ +# frv testcase for fbgt $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbgt +fbgt: + set_fcc 0x0 0 + fbgt fcc0,0,bad + set_fcc 0x1 1 + fbgt fcc1,1,bad + set_fcc 0x2 2 + fbgt fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbgt fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbgt fcc0,0,bad + set_fcc 0x5 1 + fbgt fcc1,1,bad + set_fcc 0x6 2 + fbgt fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbgt fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbgt fcc0,0,bad + set_fcc 0x9 1 + fbgt fcc1,1,bad + set_fcc 0xa 2 + fbgt fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbgt fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbgt fcc0,0,bad + set_fcc 0xd 1 + fbgt fcc1,1,bad + set_fcc 0xe 2 + fbgt fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbgt fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbgtlr.cgs b/sim/testsuite/frv/fbgtlr.cgs new file mode 100644 index 0000000..7e4a7a5 --- /dev/null +++ b/sim/testsuite/frv/fbgtlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for fbgtlr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbgtlr +fbgtlr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbgtlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbgtlr fcc1,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbgtlr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbgtlr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbgtlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fbgtlr fcc1,1 + + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbgtlr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbgtlr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbgtlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fbgtlr fcc1,1 + + set_spr_addr okb,lr + set_fcc 0xa 2 + fbgtlr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbgtlr fcc3,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fbgtlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0xd 1 + fbgtlr fcc1,1 + + set_spr_addr okf,lr + set_fcc 0xe 2 + fbgtlr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbgtlr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fble.cgs b/sim/testsuite/frv/fble.cgs new file mode 100644 index 0000000..e52936a --- /dev/null +++ b/sim/testsuite/frv/fble.cgs @@ -0,0 +1,69 @@ +# frv testcase for fble $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fble +fble: + set_fcc 0x0 0 + fble fcc0,0,bad + set_fcc 0x1 1 + fble fcc1,1,bad + set_fcc 0x2 2 + fble fcc2,2,bad + set_fcc 0x3 3 + fble fcc3,3,bad + set_fcc 0x4 0 + fble fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fble fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fble fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fble fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fble fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fble fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fble fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fble fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fble fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fble fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fble fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fble fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fblelr.cgs b/sim/testsuite/frv/fblelr.cgs new file mode 100644 index 0000000..92a47bc --- /dev/null +++ b/sim/testsuite/frv/fblelr.cgs @@ -0,0 +1,89 @@ +# frv testcase for fblelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fblelr +fblelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fblelr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fblelr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fblelr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fblelr fcc3,3 + + set_spr_addr ok5,lr + set_fcc 0x4 0 + fblelr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fblelr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fblelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fblelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fblelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fblelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fblelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fblelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fblelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fblelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fblelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fblelr fcc3,3 + fail +okg: + pass +bad: + fail + diff --git a/sim/testsuite/frv/fblg.cgs b/sim/testsuite/frv/fblg.cgs new file mode 100644 index 0000000..a16f802 --- /dev/null +++ b/sim/testsuite/frv/fblg.cgs @@ -0,0 +1,69 @@ +# frv testcase for fblg $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fblg +fblg: + set_fcc 0x0 0 + fblg fcc0,0,bad + set_fcc 0x1 1 + fblg fcc1,1,bad + set_fcc 0x2 2 + fblg fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fblg fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fblg fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fblg fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fblg fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fblg fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fblg fcc0,0,bad + set_fcc 0x9 1 + fblg fcc1,1,bad + set_fcc 0xa 2 + fblg fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fblg fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fblg fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fblg fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fblg fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fblg fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fblglr.cgs b/sim/testsuite/frv/fblglr.cgs new file mode 100644 index 0000000..e7a32b0 --- /dev/null +++ b/sim/testsuite/frv/fblglr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fblglr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fblglr +fblglr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fblglr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fblglr fcc1,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fblglr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fblglr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fblglr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fblglr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fblglr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fblglr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fblglr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fblglr fcc1,1 + + set_spr_addr okb,lr + set_fcc 0xa 2 + fblglr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fblglr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fblglr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fblglr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fblglr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fblglr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fblt.cgs b/sim/testsuite/frv/fblt.cgs new file mode 100644 index 0000000..ef7e5c7 --- /dev/null +++ b/sim/testsuite/frv/fblt.cgs @@ -0,0 +1,61 @@ +# frv testcase for fblt $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fblt +fblt: + set_fcc 0x0 0 + fblt fcc0,0,bad + set_fcc 0x1 1 + fblt fcc1,1,bad + set_fcc 0x2 2 + fblt fcc2,2,bad + set_fcc 0x3 3 + fblt fcc3,3,bad + set_fcc 0x4 0 + fblt fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fblt fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fblt fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fblt fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fblt fcc0,0,bad + set_fcc 0x9 1 + fblt fcc1,1,bad + set_fcc 0xa 2 + fblt fcc2,2,bad + set_fcc 0xb 3 + fblt fcc3,3,bad + set_fcc 0xc 0 + fblt fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fblt fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fblt fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fblt fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbltlr.cgs b/sim/testsuite/frv/fbltlr.cgs new file mode 100644 index 0000000..0a2c436 --- /dev/null +++ b/sim/testsuite/frv/fbltlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for fbltlr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbltlr +fbltlr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbltlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbltlr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fbltlr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fbltlr fcc3,3 + + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbltlr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbltlr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbltlr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbltlr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbltlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fbltlr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0xa 2 + fbltlr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0xb 3 + fbltlr fcc3,3 + + set_spr_addr okd,lr + set_fcc 0xc 0 + fbltlr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbltlr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbltlr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbltlr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fbne.cgs b/sim/testsuite/frv/fbne.cgs new file mode 100644 index 0000000..f376eea --- /dev/null +++ b/sim/testsuite/frv/fbne.cgs @@ -0,0 +1,73 @@ +# frv testcase for fbne $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbne +fbne: + set_fcc 0x0 0 + fbne fcc0,0,bad + set_fcc 0x1 1 + fbne fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbne fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbne fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbne fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fbne fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbne fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbne fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbne fcc0,0,bad + set_fcc 0x9 1 + fbne fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbne fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbne fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbne fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbne fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbne fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbne fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbnelr.cgs b/sim/testsuite/frv/fbnelr.cgs new file mode 100644 index 0000000..334d185 --- /dev/null +++ b/sim/testsuite/frv/fbnelr.cgs @@ -0,0 +1,90 @@ +# frv testcase for fbnelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbnelr +fbnelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbnelr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbnelr fcc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbnelr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbnelr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbnelr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbnelr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbnelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbnelr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbnelr fcc0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fbnelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbnelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbnelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbnelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbnelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbnelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbnelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fbno.cgs b/sim/testsuite/frv/fbno.cgs new file mode 100644 index 0000000..a3dc587 --- /dev/null +++ b/sim/testsuite/frv/fbno.cgs @@ -0,0 +1,45 @@ +# frv testcase for fbno $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbno +fbno: + set_fcc 0x0 0 + fbno + set_fcc 0x1 1 + fbno + set_fcc 0x2 2 + fbno + set_fcc 0x3 3 + fbno + set_fcc 0x4 0 + fbno + set_fcc 0x5 1 + fbno + set_fcc 0x6 2 + fbno + set_fcc 0x7 3 + fbno + set_fcc 0x8 0 + fbno + set_fcc 0x9 1 + fbno + set_fcc 0xa 2 + fbno + set_fcc 0xb 3 + fbno + set_fcc 0xc 0 + fbno + set_fcc 0xd 1 + fbno + set_fcc 0xe 2 + fbno + set_fcc 0xf 3 + fbno + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbnolr.cgs b/sim/testsuite/frv/fbnolr.cgs new file mode 100644 index 0000000..be5a0ef --- /dev/null +++ b/sim/testsuite/frv/fbnolr.cgs @@ -0,0 +1,47 @@ +# frv testcase for fbnolr +# mach: all + + .include "testutils.inc" + + start + + .global fbnolr +fbnolr: + set_spr_addr bad,lr + + set_fcc 0x0 0 + fbnolr + set_fcc 0x1 1 + fbnolr + set_fcc 0x2 2 + fbnolr + set_fcc 0x3 3 + fbnolr + set_fcc 0x4 0 + fbnolr + set_fcc 0x5 1 + fbnolr + set_fcc 0x6 2 + fbnolr + set_fcc 0x7 3 + fbnolr + set_fcc 0x8 0 + fbnolr + set_fcc 0x9 1 + fbnolr + set_fcc 0xa 2 + fbnolr + set_fcc 0xb 3 + fbnolr + set_fcc 0xc 0 + fbnolr + set_fcc 0xd 1 + fbnolr + set_fcc 0xe 2 + fbnolr + set_fcc 0xf 3 + fbnolr + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbo.cgs b/sim/testsuite/frv/fbo.cgs new file mode 100644 index 0000000..42062c9 --- /dev/null +++ b/sim/testsuite/frv/fbo.cgs @@ -0,0 +1,73 @@ +# frv testcase for fbo $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbo +fbo: + set_fcc 0x0 0 + fbo fcc0,0,bad + set_fcc 0x1 1 + fbo fcc1,1,bad + set_fcc 0x2 2 + fbo fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbo fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbo fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fbo fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbo fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbo fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbo fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbo fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbo fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbo fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbo fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbo fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbo fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbo fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbolr.cgs b/sim/testsuite/frv/fbolr.cgs new file mode 100644 index 0000000..2f9bfb3 --- /dev/null +++ b/sim/testsuite/frv/fbolr.cgs @@ -0,0 +1,90 @@ +# frv testcase for fbolr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbolr +fbolr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbolr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbolr fcc1,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbolr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbolr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbolr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbolr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbolr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbolr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbolr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbolr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbolr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbolr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbolr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbolr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbolr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbolr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fbra.cgs b/sim/testsuite/frv/fbra.cgs new file mode 100644 index 0000000..2f29308 --- /dev/null +++ b/sim/testsuite/frv/fbra.cgs @@ -0,0 +1,75 @@ +# frv testcase for fbra $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbra +fbra: + set_fcc 0x0 0 + fbra ok1 + fail +ok1: + set_fcc 0x1 1 + fbra ok2 + fail +ok2: + set_fcc 0x2 2 + fbra ok3 + fail +ok3: + set_fcc 0x3 3 + fbra ok4 + fail +ok4: + set_fcc 0x4 0 + fbra ok5 + fail +ok5: + set_fcc 0x5 1 + fbra ok6 + fail +ok6: + set_fcc 0x6 2 + fbra ok7 + fail +ok7: + set_fcc 0x7 3 + fbra ok8 + fail +ok8: + set_fcc 0x8 0 + fbra ok9 + fail +ok9: + set_fcc 0x9 1 + fbra oka + fail +oka: + set_fcc 0xa 2 + fbra okb + fail +okb: + set_fcc 0xb 3 + fbra okc + fail +okc: + set_fcc 0xc 0 + fbra okd + fail +okd: + set_fcc 0xd 1 + fbra oke + fail +oke: + set_fcc 0xe 2 + fbra okf + fail +okf: + set_fcc 0xf 3 + fbra okg + fail +okg: + + pass diff --git a/sim/testsuite/frv/fbralr.cgs b/sim/testsuite/frv/fbralr.cgs new file mode 100644 index 0000000..d57afc9 --- /dev/null +++ b/sim/testsuite/frv/fbralr.cgs @@ -0,0 +1,91 @@ +# frv testcase for fbralr +# mach: all + + .include "testutils.inc" + + start + + .global fbralr +fbralr: + set_spr_addr ok1,lr + set_fcc 0x0 0 + fbralr + fail +ok1: + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbralr + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbralr + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbralr + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbralr + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbralr + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbralr + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbralr + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbralr + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbralr + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbralr + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbralr + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbralr + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbralr + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbralr + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbralr + fail +okg: + + pass diff --git a/sim/testsuite/frv/fbu.cgs b/sim/testsuite/frv/fbu.cgs new file mode 100644 index 0000000..f397001 --- /dev/null +++ b/sim/testsuite/frv/fbu.cgs @@ -0,0 +1,61 @@ +# frv testcase for fbu $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbu +fbu: + set_fcc 0x0 0 + fbu fcc0,0,bad + set_fcc 0x1 1 + fbu fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbu fcc2,2,bad + set_fcc 0x3 3 + fbu fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbu fcc0,0,bad + set_fcc 0x5 1 + fbu fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbu fcc2,2,bad + set_fcc 0x7 3 + fbu fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbu fcc0,0,bad + set_fcc 0x9 1 + fbu fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbu fcc2,2,bad + set_fcc 0xb 3 + fbu fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbu fcc0,0,bad + set_fcc 0xd 1 + fbu fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbu fcc2,2,bad + set_fcc 0xf 3 + fbu fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbue.cgs b/sim/testsuite/frv/fbue.cgs new file mode 100644 index 0000000..dd1d636 --- /dev/null +++ b/sim/testsuite/frv/fbue.cgs @@ -0,0 +1,69 @@ +# frv testcase for fbue $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbue +fbue: + set_fcc 0x0 0 + fbue fcc0,0,bad + set_fcc 0x1 1 + fbue fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbue fcc2,2,bad + set_fcc 0x3 3 + fbue fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbue fcc0,0,bad + set_fcc 0x5 1 + fbue fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbue fcc2,2,bad + set_fcc 0x7 3 + fbue fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbue fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbue fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbue fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbue fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbue fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbue fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbue fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbue fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbuelr.cgs b/sim/testsuite/frv/fbuelr.cgs new file mode 100644 index 0000000..62ca6aa --- /dev/null +++ b/sim/testsuite/frv/fbuelr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fbuelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbuelr +fbuelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbuelr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbuelr fcc1,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fbuelr fcc2,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbuelr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbuelr fcc0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbuelr fcc1,1 + fail +ok6: + set_spr_addr bad,lr + set_fcc 0x6 2 + fbuelr fcc2,2 + + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbuelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbuelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbuelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbuelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbuelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbuelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbuelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbuelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbuelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fbug.cgs b/sim/testsuite/frv/fbug.cgs new file mode 100644 index 0000000..3a5ee01 --- /dev/null +++ b/sim/testsuite/frv/fbug.cgs @@ -0,0 +1,69 @@ +# frv testcase for fbug $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbug +fbug: + set_fcc 0x0 0 + fbug fcc0,0,bad + set_fcc 0x1 1 + fbug fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbug fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbug fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbug fcc0,0,bad + set_fcc 0x5 1 + fbug fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbug fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbug fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbug fcc0,0,bad + set_fcc 0x9 1 + fbug fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbug fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbug fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbug fcc0,0,bad + set_fcc 0xd 1 + fbug fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbug fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbug fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbuge.cgs b/sim/testsuite/frv/fbuge.cgs new file mode 100644 index 0000000..edbf7f8 --- /dev/null +++ b/sim/testsuite/frv/fbuge.cgs @@ -0,0 +1,73 @@ +# frv testcase for fbuge $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbuge +fbuge: + set_fcc 0x0 0 + fbuge fcc0,0,bad + set_fcc 0x1 1 + fbuge fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbuge fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbuge fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbuge fcc0,0,bad + set_fcc 0x5 1 + fbuge fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbuge fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbuge fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbuge fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbuge fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbuge fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbuge fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbuge fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbuge fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbuge fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbuge fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbugelr.cgs b/sim/testsuite/frv/fbugelr.cgs new file mode 100644 index 0000000..b1799c5 --- /dev/null +++ b/sim/testsuite/frv/fbugelr.cgs @@ -0,0 +1,90 @@ +# frv testcase for fbugelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbugelr +fbugelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbugelr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbugelr fcc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbugelr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbugelr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbugelr fcc0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbugelr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbugelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbugelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbugelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbugelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbugelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbugelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbugelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbugelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbugelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbugelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fbuglr.cgs b/sim/testsuite/frv/fbuglr.cgs new file mode 100644 index 0000000..d660a95 --- /dev/null +++ b/sim/testsuite/frv/fbuglr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fbuglr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbuglr +fbuglr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbuglr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbuglr fcc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbuglr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbuglr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbuglr fcc0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbuglr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbuglr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbuglr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbuglr fcc0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fbuglr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbuglr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbuglr fcc3,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fbuglr fcc0,0 + + set_spr_addr oke,lr + set_fcc 0xd 1 + fbuglr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbuglr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbuglr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fbul.cgs b/sim/testsuite/frv/fbul.cgs new file mode 100644 index 0000000..47b689d --- /dev/null +++ b/sim/testsuite/frv/fbul.cgs @@ -0,0 +1,69 @@ +# frv testcase for fbul $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbul +fbul: + set_fcc 0x0 0 + fbul fcc0,0,bad + set_fcc 0x1 1 + fbul fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbul fcc2,2,bad + set_fcc 0x3 3 + fbul fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbul fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fbul fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbul fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbul fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbul fcc0,0,bad + set_fcc 0x9 1 + fbul fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbul fcc2,2,bad + set_fcc 0xb 3 + fbul fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbul fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbul fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbul fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbul fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbule.cgs b/sim/testsuite/frv/fbule.cgs new file mode 100644 index 0000000..ad5f4e9 --- /dev/null +++ b/sim/testsuite/frv/fbule.cgs @@ -0,0 +1,73 @@ +# frv testcase for fbule $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbule +fbule: + set_fcc 0x0 0 + fbule fcc0,0,bad + set_fcc 0x1 1 + fbule fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbule fcc2,2,bad + set_fcc 0x3 3 + fbule fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbule fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fbule fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbule fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbule fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbule fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbule fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbule fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbule fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbule fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbule fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbule fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbule fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/frv/fbulelr.cgs b/sim/testsuite/frv/fbulelr.cgs new file mode 100644 index 0000000..f34d58c --- /dev/null +++ b/sim/testsuite/frv/fbulelr.cgs @@ -0,0 +1,90 @@ +# frv testcase for fbulelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbulelr +fbulelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbulelr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbulelr fcc1,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fbulelr fcc2,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbulelr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbulelr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbulelr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbulelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbulelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbulelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbulelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbulelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbulelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbulelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbulelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbulelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbulelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fbullr.cgs b/sim/testsuite/frv/fbullr.cgs new file mode 100644 index 0000000..2d5b251 --- /dev/null +++ b/sim/testsuite/frv/fbullr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fbullr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbullr +fbullr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbullr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbullr fcc1,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fbullr fcc2,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbullr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbullr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbullr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbullr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbullr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbullr fcc0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fbullr fcc1,1 + fail +oka: + set_spr_addr bad,lr + set_fcc 0xa 2 + fbullr fcc2,2 + + set_spr_addr okc,lr + set_fcc 0xb 3 + fbullr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbullr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbullr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbullr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbullr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fbulr.cgs b/sim/testsuite/frv/fbulr.cgs new file mode 100644 index 0000000..d8594bc --- /dev/null +++ b/sim/testsuite/frv/fbulr.cgs @@ -0,0 +1,84 @@ +# frv testcase for fbulr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbulr +fbulr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbulr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbulr fcc1,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fbulr fcc2,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbulr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbulr fcc0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbulr fcc1,1 + fail +ok6: + set_spr_addr bad,lr + set_fcc 0x6 2 + fbulr fcc2,2 + + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbulr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbulr fcc0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fbulr fcc1,1 + fail +oka: + set_spr_addr bad,lr + set_fcc 0xa 2 + fbulr fcc2,2 + + set_spr_addr okc,lr + set_fcc 0xb 3 + fbulr fcc3,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fbulr fcc0,0 + + set_spr_addr oke,lr + set_fcc 0xd 1 + fbulr fcc1,1 + fail +oke: + set_spr_addr bad,lr + set_fcc 0xe 2 + fbulr fcc2,2 + + set_spr_addr okg,lr + set_fcc 0xf 3 + fbulr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbeqlr.cgs b/sim/testsuite/frv/fcbeqlr.cgs new file mode 100644 index 0000000..b87e77f --- /dev/null +++ b/sim/testsuite/frv/fcbeqlr.cgs @@ -0,0 +1,262 @@ +# frv testcase for fcbeqlr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbeqlr +fcbeqlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbeqlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbeqlr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbeqlr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fcbeqlr fcc3,0,3 + + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbeqlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbeqlr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbeqlr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0x7 3 + fcbeqlr fcc3,0,3 + + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbeqlr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbeqlr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbeqlr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbeqlr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbeqlr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbeqlr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbeqlr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbeqlr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbeqlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbeqlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbeqlr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x3 3 + fcbeqlr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbeqlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbeqlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbeqlr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x7 3 + fcbeqlr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbeqlr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbeqlr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbeqlr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbeqlr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbeqlr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbeqlr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbeqlr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbeqlr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbeqlr fcc0,1,0 + set_fcc 0x1 1 + fcbeqlr fcc1,1,1 + set_fcc 0x2 2 + fcbeqlr fcc2,1,2 + set_fcc 0x3 3 + fcbeqlr fcc3,1,3 + set_fcc 0x4 0 + fcbeqlr fcc0,1,0 + set_fcc 0x5 1 + fcbeqlr fcc1,1,1 + set_fcc 0x6 2 + fcbeqlr fcc2,1,2 + set_fcc 0x7 3 + fcbeqlr fcc3,1,3 + set_fcc 0x8 0 + fcbeqlr fcc0,1,0 + set_fcc 0x9 1 + fcbeqlr fcc1,1,1 + set_fcc 0xa 2 + fcbeqlr fcc2,1,2 + set_fcc 0xb 3 + fcbeqlr fcc3,1,3 + set_fcc 0xc 0 + fcbeqlr fcc0,1,0 + set_fcc 0xd 1 + fcbeqlr fcc1,1,1 + set_fcc 0xe 2 + fcbeqlr fcc2,1,2 + set_fcc 0xf 3 + fcbeqlr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbeqlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbeqlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbeqlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbeqlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbeqlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbeqlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbeqlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbeqlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbeqlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbeqlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbeqlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbeqlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbeqlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbeqlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbeqlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbeqlr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbgelr.cgs b/sim/testsuite/frv/fcbgelr.cgs new file mode 100644 index 0000000..cc1b9d7 --- /dev/null +++ b/sim/testsuite/frv/fcbgelr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcbgelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbgelr +fcbgelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbgelr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbgelr fcc1,0,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbgelr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbgelr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbgelr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbgelr fcc1,0,1 + + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbgelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbgelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbgelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbgelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbgelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbgelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbgelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbgelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbgelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbgelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbgelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbgelr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbgelr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbgelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbgelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbgelr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbgelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbgelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbgelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbgelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbgelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbgelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbgelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbgelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbgelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbgelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbgelr fcc0,1,0 + set_fcc 0x1 1 + fcbgelr fcc1,1,1 + set_fcc 0x2 2 + fcbgelr fcc2,1,2 + set_fcc 0x3 3 + fcbgelr fcc3,1,3 + set_fcc 0x4 0 + fcbgelr fcc0,1,0 + set_fcc 0x5 1 + fcbgelr fcc1,1,1 + set_fcc 0x6 2 + fcbgelr fcc2,1,2 + set_fcc 0x7 3 + fcbgelr fcc3,1,3 + set_fcc 0x8 0 + fcbgelr fcc0,1,0 + set_fcc 0x9 1 + fcbgelr fcc1,1,1 + set_fcc 0xa 2 + fcbgelr fcc2,1,2 + set_fcc 0xb 3 + fcbgelr fcc3,1,3 + set_fcc 0xc 0 + fcbgelr fcc0,1,0 + set_fcc 0xd 1 + fcbgelr fcc1,1,1 + set_fcc 0xe 2 + fcbgelr fcc2,1,2 + set_fcc 0xf 3 + fcbgelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbgelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbgelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbgelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbgelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbgelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbgelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbgelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbgelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbgelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbgelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbgelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbgelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbgelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbgelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbgelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbgelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbgtlr.cgs b/sim/testsuite/frv/fcbgtlr.cgs new file mode 100644 index 0000000..76204e2 --- /dev/null +++ b/sim/testsuite/frv/fcbgtlr.cgs @@ -0,0 +1,262 @@ +# frv testcase for fcbgtlr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbgtlr +fcbgtlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbgtlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbgtlr fcc1,0,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbgtlr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbgtlr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbgtlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbgtlr fcc1,0,1 + + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbgtlr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbgtlr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbgtlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fcbgtlr fcc1,0,1 + + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbgtlr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbgtlr fcc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbgtlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0xd 1 + fcbgtlr fcc1,0,1 + + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbgtlr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbgtlr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbgtlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbgtlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbgtlr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbgtlr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbgtlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbgtlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbgtlr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbgtlr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbgtlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x9 1 + fcbgtlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbgtlr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbgtlr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbgtlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xd 1 + fcbgtlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbgtlr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbgtlr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbgtlr fcc0,1,0 + set_fcc 0x1 1 + fcbgtlr fcc1,1,1 + set_fcc 0x2 2 + fcbgtlr fcc2,1,2 + set_fcc 0x3 3 + fcbgtlr fcc3,1,3 + set_fcc 0x4 0 + fcbgtlr fcc0,1,0 + set_fcc 0x5 1 + fcbgtlr fcc1,1,1 + set_fcc 0x6 2 + fcbgtlr fcc2,1,2 + set_fcc 0x7 3 + fcbgtlr fcc3,1,3 + set_fcc 0x8 0 + fcbgtlr fcc0,1,0 + set_fcc 0x9 1 + fcbgtlr fcc1,1,1 + set_fcc 0xa 2 + fcbgtlr fcc2,1,2 + set_fcc 0xb 3 + fcbgtlr fcc3,1,3 + set_fcc 0xc 0 + fcbgtlr fcc0,1,0 + set_fcc 0xd 1 + fcbgtlr fcc1,1,1 + set_fcc 0xe 2 + fcbgtlr fcc2,1,2 + set_fcc 0xf 3 + fcbgtlr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbgtlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbgtlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbgtlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbgtlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbgtlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbgtlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbgtlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbgtlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbgtlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbgtlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbgtlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbgtlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbgtlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbgtlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbgtlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbgtlr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcblelr.cgs b/sim/testsuite/frv/fcblelr.cgs new file mode 100644 index 0000000..b9850d6 --- /dev/null +++ b/sim/testsuite/frv/fcblelr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcblelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcblelr +fcblelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcblelr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcblelr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fcblelr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fcblelr fcc3,0,3 + + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcblelr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcblelr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcblelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcblelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcblelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcblelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcblelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcblelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcblelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcblelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcblelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcblelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcblelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcblelr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcblelr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x3 3 + fcblelr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcblelr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcblelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcblelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcblelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcblelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcblelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcblelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcblelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcblelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcblelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcblelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcblelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcblelr fcc0,1,0 + set_fcc 0x1 1 + fcblelr fcc1,1,1 + set_fcc 0x2 2 + fcblelr fcc2,1,2 + set_fcc 0x3 3 + fcblelr fcc3,1,3 + set_fcc 0x4 0 + fcblelr fcc0,1,0 + set_fcc 0x5 1 + fcblelr fcc1,1,1 + set_fcc 0x6 2 + fcblelr fcc2,1,2 + set_fcc 0x7 3 + fcblelr fcc3,1,3 + set_fcc 0x8 0 + fcblelr fcc0,1,0 + set_fcc 0x9 1 + fcblelr fcc1,1,1 + set_fcc 0xa 2 + fcblelr fcc2,1,2 + set_fcc 0xb 3 + fcblelr fcc3,1,3 + set_fcc 0xc 0 + fcblelr fcc0,1,0 + set_fcc 0xd 1 + fcblelr fcc1,1,1 + set_fcc 0xe 2 + fcblelr fcc2,1,2 + set_fcc 0xf 3 + fcblelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcblelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcblelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcblelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcblelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcblelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcblelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcblelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcblelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcblelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcblelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcblelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcblelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcblelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcblelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcblelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcblelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcblglr.cgs b/sim/testsuite/frv/fcblglr.cgs new file mode 100644 index 0000000..e875d40 --- /dev/null +++ b/sim/testsuite/frv/fcblglr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcblglr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcblglr +fcblglr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcblglr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcblglr fcc1,0,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcblglr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcblglr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcblglr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcblglr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcblglr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcblglr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcblglr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fcblglr fcc1,0,1 + + set_spr_addr okb,lr + set_fcc 0xa 2 + fcblglr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcblglr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcblglr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcblglr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcblglr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcblglr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcblglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcblglr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcblglr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcblglr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcblglr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcblglr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcblglr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcblglr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcblglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x9 1 + fcblglr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcblglr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcblglr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcblglr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcblglr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcblglr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcblglr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcblglr fcc0,1,0 + set_fcc 0x1 1 + fcblglr fcc1,1,1 + set_fcc 0x2 2 + fcblglr fcc2,1,2 + set_fcc 0x3 3 + fcblglr fcc3,1,3 + set_fcc 0x4 0 + fcblglr fcc0,1,0 + set_fcc 0x5 1 + fcblglr fcc1,1,1 + set_fcc 0x6 2 + fcblglr fcc2,1,2 + set_fcc 0x7 3 + fcblglr fcc3,1,3 + set_fcc 0x8 0 + fcblglr fcc0,1,0 + set_fcc 0x9 1 + fcblglr fcc1,1,1 + set_fcc 0xa 2 + fcblglr fcc2,1,2 + set_fcc 0xb 3 + fcblglr fcc3,1,3 + set_fcc 0xc 0 + fcblglr fcc0,1,0 + set_fcc 0xd 1 + fcblglr fcc1,1,1 + set_fcc 0xe 2 + fcblglr fcc2,1,2 + set_fcc 0xf 3 + fcblglr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcblglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcblglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcblglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcblglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcblglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcblglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcblglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcblglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcblglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcblglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcblglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcblglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcblglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcblglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcblglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcblglr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbltlr.cgs b/sim/testsuite/frv/fcbltlr.cgs new file mode 100644 index 0000000..d15dd30 --- /dev/null +++ b/sim/testsuite/frv/fcbltlr.cgs @@ -0,0 +1,262 @@ +# frv testcase for fcbltlr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbltlr +fcbltlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbltlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbltlr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbltlr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fcbltlr fcc3,0,3 + + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbltlr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbltlr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbltlr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbltlr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbltlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fcbltlr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbltlr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0xb 3 + fcbltlr fcc3,0,3 + + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbltlr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbltlr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbltlr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbltlr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbltlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbltlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbltlr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x3 3 + fcbltlr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbltlr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbltlr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbltlr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbltlr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbltlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x9 1 + fcbltlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbltlr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xb 3 + fcbltlr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbltlr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbltlr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbltlr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbltlr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbltlr fcc0,1,0 + set_fcc 0x1 1 + fcbltlr fcc1,1,1 + set_fcc 0x2 2 + fcbltlr fcc2,1,2 + set_fcc 0x3 3 + fcbltlr fcc3,1,3 + set_fcc 0x4 0 + fcbltlr fcc0,1,0 + set_fcc 0x5 1 + fcbltlr fcc1,1,1 + set_fcc 0x6 2 + fcbltlr fcc2,1,2 + set_fcc 0x7 3 + fcbltlr fcc3,1,3 + set_fcc 0x8 0 + fcbltlr fcc0,1,0 + set_fcc 0x9 1 + fcbltlr fcc1,1,1 + set_fcc 0xa 2 + fcbltlr fcc2,1,2 + set_fcc 0xb 3 + fcbltlr fcc3,1,3 + set_fcc 0xc 0 + fcbltlr fcc0,1,0 + set_fcc 0xd 1 + fcbltlr fcc1,1,1 + set_fcc 0xe 2 + fcbltlr fcc2,1,2 + set_fcc 0xf 3 + fcbltlr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbltlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbltlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbltlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbltlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbltlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbltlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbltlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbltlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbltlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbltlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbltlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbltlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbltlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbltlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbltlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbltlr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbnelr.cgs b/sim/testsuite/frv/fcbnelr.cgs new file mode 100644 index 0000000..cb0aa26 --- /dev/null +++ b/sim/testsuite/frv/fcbnelr.cgs @@ -0,0 +1,274 @@ +# frv testcase for fcbnelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbnelr +fcbnelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbnelr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbnelr fcc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbnelr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbnelr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbnelr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbnelr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbnelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbnelr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbnelr fcc0,0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbnelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbnelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbnelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbnelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbnelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbnelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbnelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbnelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbnelr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbnelr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbnelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbnelr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbnelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbnelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbnelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbnelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbnelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbnelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbnelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbnelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbnelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbnelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbnelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbnelr fcc0,1,0 + set_fcc 0x1 1 + fcbnelr fcc1,1,1 + set_fcc 0x2 2 + fcbnelr fcc2,1,2 + set_fcc 0x3 3 + fcbnelr fcc3,1,3 + set_fcc 0x4 0 + fcbnelr fcc0,1,0 + set_fcc 0x5 1 + fcbnelr fcc1,1,1 + set_fcc 0x6 2 + fcbnelr fcc2,1,2 + set_fcc 0x7 3 + fcbnelr fcc3,1,3 + set_fcc 0x8 0 + fcbnelr fcc0,1,0 + set_fcc 0x9 1 + fcbnelr fcc1,1,1 + set_fcc 0xa 2 + fcbnelr fcc2,1,2 + set_fcc 0xb 3 + fcbnelr fcc3,1,3 + set_fcc 0xc 0 + fcbnelr fcc0,1,0 + set_fcc 0xd 1 + fcbnelr fcc1,1,1 + set_fcc 0xe 2 + fcbnelr fcc2,1,2 + set_fcc 0xf 3 + fcbnelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbnelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbnelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbnelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbnelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbnelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbnelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbnelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbnelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbnelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbnelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbnelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbnelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbnelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbnelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbnelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbnelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbnolr.cgs b/sim/testsuite/frv/fcbnolr.cgs new file mode 100644 index 0000000..3c1b73a --- /dev/null +++ b/sim/testsuite/frv/fcbnolr.cgs @@ -0,0 +1,185 @@ +# frv testcase for fcbnolr +# mach: all + + .include "testutils.inc" + + start + + .global fcbnolr +fcbnolr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + + set_fcc 0x0 0 + fcbnolr + set_fcc 0x1 1 + fcbnolr + set_fcc 0x2 2 + fcbnolr + set_fcc 0x3 3 + fcbnolr + set_fcc 0x4 0 + fcbnolr + set_fcc 0x5 1 + fcbnolr + set_fcc 0x6 2 + fcbnolr + set_fcc 0x7 3 + fcbnolr + set_fcc 0x8 0 + fcbnolr + set_fcc 0x9 1 + fcbnolr + set_fcc 0xa 2 + fcbnolr + set_fcc 0xb 3 + fcbnolr + set_fcc 0xc 0 + fcbnolr + set_fcc 0xd 1 + fcbnolr + set_fcc 0xe 2 + fcbnolr + set_fcc 0xf 3 + fcbnolr + + ; ccond is true + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbnolr + + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbnolr + set_fcc 0x1 1 + fcbnolr + set_fcc 0x2 2 + fcbnolr + set_fcc 0x3 3 + fcbnolr + set_fcc 0x4 0 + fcbnolr + set_fcc 0x5 1 + fcbnolr + set_fcc 0x6 2 + fcbnolr + set_fcc 0x7 3 + fcbnolr + set_fcc 0x8 0 + fcbnolr + set_fcc 0x9 1 + fcbnolr + set_fcc 0xa 2 + fcbnolr + set_fcc 0xb 3 + fcbnolr + set_fcc 0xc 0 + fcbnolr + set_fcc 0xd 1 + fcbnolr + set_fcc 0xe 2 + fcbnolr + set_fcc 0xf 3 + fcbnolr + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbnolr + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbolr.cgs b/sim/testsuite/frv/fcbolr.cgs new file mode 100644 index 0000000..31909f1 --- /dev/null +++ b/sim/testsuite/frv/fcbolr.cgs @@ -0,0 +1,274 @@ +# frv testcase for fcbolr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbolr +fcbolr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbolr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbolr fcc1,0,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbolr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbolr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbolr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbolr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbolr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbolr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbolr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbolr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbolr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbolr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbolr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbolr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbolr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbolr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbolr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbolr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbolr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbolr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbolr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbolr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbolr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbolr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbolr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbolr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbolr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbolr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbolr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbolr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbolr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbolr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbolr fcc0,1,0 + set_fcc 0x1 1 + fcbolr fcc1,1,1 + set_fcc 0x2 2 + fcbolr fcc2,1,2 + set_fcc 0x3 3 + fcbolr fcc3,1,3 + set_fcc 0x4 0 + fcbolr fcc0,1,0 + set_fcc 0x5 1 + fcbolr fcc1,1,1 + set_fcc 0x6 2 + fcbolr fcc2,1,2 + set_fcc 0x7 3 + fcbolr fcc3,1,3 + set_fcc 0x8 0 + fcbolr fcc0,1,0 + set_fcc 0x9 1 + fcbolr fcc1,1,1 + set_fcc 0xa 2 + fcbolr fcc2,1,2 + set_fcc 0xb 3 + fcbolr fcc3,1,3 + set_fcc 0xc 0 + fcbolr fcc0,1,0 + set_fcc 0xd 1 + fcbolr fcc1,1,1 + set_fcc 0xe 2 + fcbolr fcc2,1,2 + set_fcc 0xf 3 + fcbolr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbolr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbolr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbolr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbolr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbolr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbolr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbolr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbolr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbolr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbolr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbolr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbolr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbolr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbolr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbolr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbolr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbralr.cgs b/sim/testsuite/frv/fcbralr.cgs new file mode 100644 index 0000000..60359d8 --- /dev/null +++ b/sim/testsuite/frv/fcbralr.cgs @@ -0,0 +1,276 @@ +# frv testcase for fcbralr $ccond +# mach: all + + .include "testutils.inc" + + start + + .global fcbralr +fcbralr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_fcc 0x0 0 + fcbralr 0 + fail +ok1: + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbralr 0 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbralr 0 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbralr 0 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbralr 0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbralr 0 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbralr 0 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbralr 0 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbralr 0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbralr 0 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbralr 0 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbralr 0 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbralr 0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbralr 0 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbralr 0 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbralr 0 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_fcc 0x0 0 + fcbralr 1 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbralr 1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbralr 1 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbralr 1 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbralr 1 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbralr 1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbralr 1 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbralr 1 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbralr 1 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbralr 1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbralr 1 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbralr 1 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbralr 1 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbralr 1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbralr 1 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbralr 1 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbralr 1 + set_fcc 0x1 1 + fcbralr 1 + set_fcc 0x2 2 + fcbralr 1 + set_fcc 0x3 3 + fcbralr 1 + set_fcc 0x4 0 + fcbralr 1 + set_fcc 0x5 1 + fcbralr 1 + set_fcc 0x6 2 + fcbralr 1 + set_fcc 0x7 3 + fcbralr 1 + set_fcc 0x8 0 + fcbralr 1 + set_fcc 0x9 1 + fcbralr 1 + set_fcc 0xa 2 + fcbralr 1 + set_fcc 0xb 3 + fcbralr 1 + set_fcc 0xc 0 + fcbralr 1 + set_fcc 0xd 1 + fcbralr 1 + set_fcc 0xe 2 + fcbralr 1 + set_fcc 0xf 3 + fcbralr 1 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbralr 0 + + pass diff --git a/sim/testsuite/frv/fcbuelr.cgs b/sim/testsuite/frv/fcbuelr.cgs new file mode 100644 index 0000000..e102ee3 --- /dev/null +++ b/sim/testsuite/frv/fcbuelr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcbuelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbuelr +fcbuelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbuelr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbuelr fcc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbuelr fcc2,0,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbuelr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbuelr fcc0,0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbuelr fcc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbuelr fcc2,0,2 + + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbuelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbuelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbuelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbuelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbuelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbuelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbuelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbuelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbuelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbuelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbuelr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbuelr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbuelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbuelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbuelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbuelr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbuelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbuelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbuelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbuelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbuelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbuelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbuelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbuelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbuelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbuelr fcc0,1,0 + set_fcc 0x1 1 + fcbuelr fcc1,1,1 + set_fcc 0x2 2 + fcbuelr fcc2,1,2 + set_fcc 0x3 3 + fcbuelr fcc3,1,3 + set_fcc 0x4 0 + fcbuelr fcc0,1,0 + set_fcc 0x5 1 + fcbuelr fcc1,1,1 + set_fcc 0x6 2 + fcbuelr fcc2,1,2 + set_fcc 0x7 3 + fcbuelr fcc3,1,3 + set_fcc 0x8 0 + fcbuelr fcc0,1,0 + set_fcc 0x9 1 + fcbuelr fcc1,1,1 + set_fcc 0xa 2 + fcbuelr fcc2,1,2 + set_fcc 0xb 3 + fcbuelr fcc3,1,3 + set_fcc 0xc 0 + fcbuelr fcc0,1,0 + set_fcc 0xd 1 + fcbuelr fcc1,1,1 + set_fcc 0xe 2 + fcbuelr fcc2,1,2 + set_fcc 0xf 3 + fcbuelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbuelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbuelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbuelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbuelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbuelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbuelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbuelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbuelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbuelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbuelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbuelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbuelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbuelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbuelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbuelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbuelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbugelr.cgs b/sim/testsuite/frv/fcbugelr.cgs new file mode 100644 index 0000000..8ecd141 --- /dev/null +++ b/sim/testsuite/frv/fcbugelr.cgs @@ -0,0 +1,274 @@ +# frv testcase for fcbugelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbugelr +fcbugelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbugelr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbugelr fcc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbugelr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbugelr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbugelr fcc0,0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbugelr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbugelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbugelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbugelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbugelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbugelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbugelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbugelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbugelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbugelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbugelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbugelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbugelr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbugelr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbugelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbugelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbugelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbugelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbugelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbugelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbugelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbugelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbugelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbugelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbugelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbugelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbugelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbugelr fcc0,1,0 + set_fcc 0x1 1 + fcbugelr fcc1,1,1 + set_fcc 0x2 2 + fcbugelr fcc2,1,2 + set_fcc 0x3 3 + fcbugelr fcc3,1,3 + set_fcc 0x4 0 + fcbugelr fcc0,1,0 + set_fcc 0x5 1 + fcbugelr fcc1,1,1 + set_fcc 0x6 2 + fcbugelr fcc2,1,2 + set_fcc 0x7 3 + fcbugelr fcc3,1,3 + set_fcc 0x8 0 + fcbugelr fcc0,1,0 + set_fcc 0x9 1 + fcbugelr fcc1,1,1 + set_fcc 0xa 2 + fcbugelr fcc2,1,2 + set_fcc 0xb 3 + fcbugelr fcc3,1,3 + set_fcc 0xc 0 + fcbugelr fcc0,1,0 + set_fcc 0xd 1 + fcbugelr fcc1,1,1 + set_fcc 0xe 2 + fcbugelr fcc2,1,2 + set_fcc 0xf 3 + fcbugelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbugelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbugelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbugelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbugelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbugelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbugelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbugelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbugelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbugelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbugelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbugelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbugelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbugelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbugelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbugelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbugelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbuglr.cgs b/sim/testsuite/frv/fcbuglr.cgs new file mode 100644 index 0000000..d9470a8 --- /dev/null +++ b/sim/testsuite/frv/fcbuglr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcbuglr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbuglr +fcbuglr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbuglr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbuglr fcc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbuglr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbuglr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbuglr fcc0,0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbuglr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbuglr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbuglr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbuglr fcc0,0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbuglr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbuglr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbuglr fcc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbuglr fcc0,0,0 + + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbuglr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbuglr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbuglr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbuglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbuglr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbuglr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbuglr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbuglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbuglr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbuglr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbuglr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbuglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbuglr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbuglr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbuglr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbuglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbuglr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbuglr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbuglr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbuglr fcc0,1,0 + set_fcc 0x1 1 + fcbuglr fcc1,1,1 + set_fcc 0x2 2 + fcbuglr fcc2,1,2 + set_fcc 0x3 3 + fcbuglr fcc3,1,3 + set_fcc 0x4 0 + fcbuglr fcc0,1,0 + set_fcc 0x5 1 + fcbuglr fcc1,1,1 + set_fcc 0x6 2 + fcbuglr fcc2,1,2 + set_fcc 0x7 3 + fcbuglr fcc3,1,3 + set_fcc 0x8 0 + fcbuglr fcc0,1,0 + set_fcc 0x9 1 + fcbuglr fcc1,1,1 + set_fcc 0xa 2 + fcbuglr fcc2,1,2 + set_fcc 0xb 3 + fcbuglr fcc3,1,3 + set_fcc 0xc 0 + fcbuglr fcc0,1,0 + set_fcc 0xd 1 + fcbuglr fcc1,1,1 + set_fcc 0xe 2 + fcbuglr fcc2,1,2 + set_fcc 0xf 3 + fcbuglr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbuglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbuglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbuglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbuglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbuglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbuglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbuglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbuglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbuglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbuglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbuglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbuglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbuglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbuglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbuglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbuglr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbulelr.cgs b/sim/testsuite/frv/fcbulelr.cgs new file mode 100644 index 0000000..3f1da04 --- /dev/null +++ b/sim/testsuite/frv/fcbulelr.cgs @@ -0,0 +1,274 @@ +# frv testcase for fcbulelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbulelr +fcbulelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbulelr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbulelr fcc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbulelr fcc2,0,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbulelr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbulelr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbulelr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbulelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbulelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbulelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbulelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbulelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbulelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbulelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbulelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbulelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbulelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbulelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbulelr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbulelr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbulelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbulelr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbulelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbulelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbulelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbulelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbulelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbulelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbulelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbulelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbulelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbulelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbulelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbulelr fcc0,1,0 + set_fcc 0x1 1 + fcbulelr fcc1,1,1 + set_fcc 0x2 2 + fcbulelr fcc2,1,2 + set_fcc 0x3 3 + fcbulelr fcc3,1,3 + set_fcc 0x4 0 + fcbulelr fcc0,1,0 + set_fcc 0x5 1 + fcbulelr fcc1,1,1 + set_fcc 0x6 2 + fcbulelr fcc2,1,2 + set_fcc 0x7 3 + fcbulelr fcc3,1,3 + set_fcc 0x8 0 + fcbulelr fcc0,1,0 + set_fcc 0x9 1 + fcbulelr fcc1,1,1 + set_fcc 0xa 2 + fcbulelr fcc2,1,2 + set_fcc 0xb 3 + fcbulelr fcc3,1,3 + set_fcc 0xc 0 + fcbulelr fcc0,1,0 + set_fcc 0xd 1 + fcbulelr fcc1,1,1 + set_fcc 0xe 2 + fcbulelr fcc2,1,2 + set_fcc 0xf 3 + fcbulelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbulelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbulelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbulelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbulelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbulelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbulelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbulelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbulelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbulelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbulelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbulelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbulelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbulelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbulelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbulelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbulelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbullr.cgs b/sim/testsuite/frv/fcbullr.cgs new file mode 100644 index 0000000..1a87dde --- /dev/null +++ b/sim/testsuite/frv/fcbullr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcbullr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbullr +fcbullr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbullr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbullr fcc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbullr fcc2,0,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbullr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbullr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbullr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbullr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbullr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbullr fcc0,0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbullr fcc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbullr fcc2,0,2 + + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbullr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbullr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbullr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbullr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbullr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbullr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbullr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbullr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbullr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbullr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbullr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbullr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbullr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbullr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbullr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbullr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbullr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbullr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbullr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbullr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbullr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbullr fcc0,1,0 + set_fcc 0x1 1 + fcbullr fcc1,1,1 + set_fcc 0x2 2 + fcbullr fcc2,1,2 + set_fcc 0x3 3 + fcbullr fcc3,1,3 + set_fcc 0x4 0 + fcbullr fcc0,1,0 + set_fcc 0x5 1 + fcbullr fcc1,1,1 + set_fcc 0x6 2 + fcbullr fcc2,1,2 + set_fcc 0x7 3 + fcbullr fcc3,1,3 + set_fcc 0x8 0 + fcbullr fcc0,1,0 + set_fcc 0x9 1 + fcbullr fcc1,1,1 + set_fcc 0xa 2 + fcbullr fcc2,1,2 + set_fcc 0xb 3 + fcbullr fcc3,1,3 + set_fcc 0xc 0 + fcbullr fcc0,1,0 + set_fcc 0xd 1 + fcbullr fcc1,1,1 + set_fcc 0xe 2 + fcbullr fcc2,1,2 + set_fcc 0xf 3 + fcbullr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbullr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbullr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbullr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbullr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbullr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbullr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbullr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbullr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbullr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbullr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbullr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbullr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbullr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbullr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbullr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbullr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fcbulr.cgs b/sim/testsuite/frv/fcbulr.cgs new file mode 100644 index 0000000..c81dff3 --- /dev/null +++ b/sim/testsuite/frv/fcbulr.cgs @@ -0,0 +1,262 @@ +# frv testcase for fcbulr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbulr +fcbulr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbulr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbulr fcc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbulr fcc2,0,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbulr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbulr fcc0,0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbulr fcc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbulr fcc2,0,2 + + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbulr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbulr fcc0,0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbulr fcc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbulr fcc2,0,2 + + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbulr fcc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbulr fcc0,0,0 + + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbulr fcc1,0,1 + fail +oke: + set_spr_addr bad,lr + set_fcc 0xe 2 + fcbulr fcc2,0,2 + + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbulr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbulr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbulr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbulr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbulr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbulr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbulr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbulr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbulr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbulr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbulr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbulr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbulr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbulr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbulr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xe 2 + fcbulr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbulr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbulr fcc0,1,0 + set_fcc 0x1 1 + fcbulr fcc1,1,1 + set_fcc 0x2 2 + fcbulr fcc2,1,2 + set_fcc 0x3 3 + fcbulr fcc3,1,3 + set_fcc 0x4 0 + fcbulr fcc0,1,0 + set_fcc 0x5 1 + fcbulr fcc1,1,1 + set_fcc 0x6 2 + fcbulr fcc2,1,2 + set_fcc 0x7 3 + fcbulr fcc3,1,3 + set_fcc 0x8 0 + fcbulr fcc0,1,0 + set_fcc 0x9 1 + fcbulr fcc1,1,1 + set_fcc 0xa 2 + fcbulr fcc2,1,2 + set_fcc 0xb 3 + fcbulr fcc3,1,3 + set_fcc 0xc 0 + fcbulr fcc0,1,0 + set_fcc 0xd 1 + fcbulr fcc1,1,1 + set_fcc 0xe 2 + fcbulr fcc2,1,2 + set_fcc 0xf 3 + fcbulr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbulr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbulr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbulr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbulr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbulr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbulr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbulr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbulr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbulr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbulr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbulr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbulr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbulr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbulr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbulr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbulr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/frv/fckeq.cgs b/sim/testsuite/frv/fckeq.cgs new file mode 100644 index 0000000..572a86d --- /dev/null +++ b/sim/testsuite/frv/fckeq.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckeq $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckeq +fckeq: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fckge.cgs b/sim/testsuite/frv/fckge.cgs new file mode 100644 index 0000000..91a1efd --- /dev/null +++ b/sim/testsuite/frv/fckge.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckge $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckge +fckge: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fckgt.cgs b/sim/testsuite/frv/fckgt.cgs new file mode 100644 index 0000000..06715f9 --- /dev/null +++ b/sim/testsuite/frv/fckgt.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckgt $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckgt +fckgt: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fckle.cgs b/sim/testsuite/frv/fckle.cgs new file mode 100644 index 0000000..7d5e6da --- /dev/null +++ b/sim/testsuite/frv/fckle.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckle $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckle +fckle: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckle fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckle fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckle fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckle fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fcklg.cgs b/sim/testsuite/frv/fcklg.cgs new file mode 100644 index 0000000..f8df5a1 --- /dev/null +++ b/sim/testsuite/frv/fcklg.cgs @@ -0,0 +1,90 @@ +# frv testcase for fcklg $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fcklg +fcklg: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fcklg fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fcklg fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fcklg fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fcklg fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fcklt.cgs b/sim/testsuite/frv/fcklt.cgs new file mode 100644 index 0000000..14e5371 --- /dev/null +++ b/sim/testsuite/frv/fcklt.cgs @@ -0,0 +1,90 @@ +# frv testcase for fcklt $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fcklt +fcklt: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fckne.cgs b/sim/testsuite/frv/fckne.cgs new file mode 100644 index 0000000..774f837 --- /dev/null +++ b/sim/testsuite/frv/fckne.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckne $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckne +fckne: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckne fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckne fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fckno.cgs b/sim/testsuite/frv/fckno.cgs new file mode 100644 index 0000000..08513a2 --- /dev/null +++ b/sim/testsuite/frv/fckno.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckno $CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckno +fckno: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/frv/fcko.cgs b/sim/testsuite/frv/fcko.cgs new file mode 100644 index 0000000..06d5640 --- /dev/null +++ b/sim/testsuite/frv/fcko.cgs @@ -0,0 +1,90 @@ +# frv testcase for fcko $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fcko +fcko: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fcko fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fcko fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fckra.cgs b/sim/testsuite/frv/fckra.cgs new file mode 100644 index 0000000..a74b9fc --- /dev/null +++ b/sim/testsuite/frv/fckra.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckra $CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckra +fckra: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fcku.cgs b/sim/testsuite/frv/fcku.cgs new file mode 100644 index 0000000..9aaa635 --- /dev/null +++ b/sim/testsuite/frv/fcku.cgs @@ -0,0 +1,90 @@ +# frv testcase for fcku $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fcku +fcku: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fckue.cgs b/sim/testsuite/frv/fckue.cgs new file mode 100644 index 0000000..0bd7696 --- /dev/null +++ b/sim/testsuite/frv/fckue.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckue $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckue +fckue: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckue fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckue fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckue fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckue fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fckug.cgs b/sim/testsuite/frv/fckug.cgs new file mode 100644 index 0000000..f810335 --- /dev/null +++ b/sim/testsuite/frv/fckug.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckug $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckug +fckug: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckug fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckug fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckug fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckug fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fckuge.cgs b/sim/testsuite/frv/fckuge.cgs new file mode 100644 index 0000000..d812638 --- /dev/null +++ b/sim/testsuite/frv/fckuge.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckuge $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckuge +fckuge: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckuge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckuge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fckul.cgs b/sim/testsuite/frv/fckul.cgs new file mode 100644 index 0000000..2d30d92 --- /dev/null +++ b/sim/testsuite/frv/fckul.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckul $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckul +fckul: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckul fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckul fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckul fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckul fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fckule.cgs b/sim/testsuite/frv/fckule.cgs new file mode 100644 index 0000000..9830a66 --- /dev/null +++ b/sim/testsuite/frv/fckule.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckule $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckule +fckule: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckule fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckule fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/fcmpd.cgs b/sim/testsuite/frv/fcmpd.cgs new file mode 100644 index 0000000..5c86266 --- /dev/null +++ b/sim/testsuite/frv/fcmpd.cgs @@ -0,0 +1,601 @@ +# frv testcase for fcmpd $GRi,$GRj,$FCCi_2 +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fcmpd +fcmpd: + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr0,fr0,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr4,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr8,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr0,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr0,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr4,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr4,fr4,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr8,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr4,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr4,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr8,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr8,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr8,fr8,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr8,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr8,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr12,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr12,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr12,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr12,fr12,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr12,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr12,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr16,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr16,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr16,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr16,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr16,fr16,fcc0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr16,fr20,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr16,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr16,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr20,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr20,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr20,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr20,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr20,fr16,fcc0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr20,fr20,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr20,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr20,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr24,fr24,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr24,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr24,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr28,fr28,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr28,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr28,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr28,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr32,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr36,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr40,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr44,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr48,fr48,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr48,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr48,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr48,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr28,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr32,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr36,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr40,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr44,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr48,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr52,fr52,fcc0 + test_fcc 0x8,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr52,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr52,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr0,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr4,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr8,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr12,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr16,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr20,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr24,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr28,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr32,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr36,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr40,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr44,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr48,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr52,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr0,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr4,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr8,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr12,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr16,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr20,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr24,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr28,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr32,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr36,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr40,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr44,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr48,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr52,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr60,fcc0 + test_fcc 0x1,0 + + pass diff --git a/sim/testsuite/frv/fcmps.cgs b/sim/testsuite/frv/fcmps.cgs new file mode 100644 index 0000000..ea1ccc0 --- /dev/null +++ b/sim/testsuite/frv/fcmps.cgs @@ -0,0 +1,600 @@ +# frv testcase for fcmps $GRi,$GRj,$FCCi_2 +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fcmps +fcmps: + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr0,fr0,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr4,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr8,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr0,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr0,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr4,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr4,fr4,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr8,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr4,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr4,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr8,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr8,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr8,fr8,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr8,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr8,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr12,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr12,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr12,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr12,fr12,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr12,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr12,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr16,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr16,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr16,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr16,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr16,fr16,fcc0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr16,fr20,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr16,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr16,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr20,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr20,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr20,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr20,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr20,fr16,fcc0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr20,fr20,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr20,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr20,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr24,fr24,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr24,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr24,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr28,fr28,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr28,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr28,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr28,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr32,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr36,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr40,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr44,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr48,fr48,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr48,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr48,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr48,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr28,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr32,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr36,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr40,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr44,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr48,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr52,fr52,fcc0 + test_fcc 0x8,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr52,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr52,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr0,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr4,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr8,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr12,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr16,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr20,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr24,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr28,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr32,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr36,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr40,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr44,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr48,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr52,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr0,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr4,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr8,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr12,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr16,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr20,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr24,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr28,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr32,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr36,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr40,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr44,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr48,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr52,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr60,fcc0 + test_fcc 0x1,0 + + pass diff --git a/sim/testsuite/frv/fdabss.cgs b/sim/testsuite/frv/fdabss.cgs new file mode 100644 index 0000000..83d3e1c --- /dev/null +++ b/sim/testsuite/frv/fdabss.cgs @@ -0,0 +1,25 @@ +# frv testcase for fdabss $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdabss +fdabss: + set_fr_fr fr8,fr1 + fdabss fr0,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr28 + set_fr_fr fr24,fr13 + fdabss fr12,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + set_fr_fr fr52,fr29 + fdabss fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr52 + + pass diff --git a/sim/testsuite/frv/fdadds.cgs b/sim/testsuite/frv/fdadds.cgs new file mode 100644 index 0000000..ecfa56c --- /dev/null +++ b/sim/testsuite/frv/fdadds.cgs @@ -0,0 +1,134 @@ +# frv testcase for fdadds $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdadds +fdadds: + fdadds fr16,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdadds fr16,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdadds fr16,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdadds fr16,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdadds fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr16,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdadds fr16,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdadds fr16,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdadds fr16,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdadds fr16,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdadds fr16,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdadds fr16,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdadds fr16,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdadds fr20,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdadds fr20,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdadds fr20,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdadds fr20,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdadds fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr20,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdadds fr20,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdadds fr20,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdadds fr20,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdadds fr20,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdadds fr20,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdadds fr20,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdadds fr20,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdadds fr8,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr12,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr24,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr28,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdadds fr36,fr40,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + + pass + + diff --git a/sim/testsuite/frv/fdcmps.cgs b/sim/testsuite/frv/fdcmps.cgs new file mode 100644 index 0000000..397832c --- /dev/null +++ b/sim/testsuite/frv/fdcmps.cgs @@ -0,0 +1,985 @@ +# frv testcase for fdcmps $FRi,$FRj,$FCCi_2 +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdcmps +fdcmps: + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr0,fr0,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr4,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr8,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr0,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr0,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr4,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr4,fr4,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr8,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr4,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr4,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr8,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr8,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr8,fr8,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr8,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr8,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr12,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr12,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr12,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr12,fr12,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr12,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr12,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr16,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr16,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr16,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr16,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr16,fr16,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr16,fr20,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr16,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr16,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr20,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr20,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr20,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr20,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr20,fr16,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr20,fr20,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr20,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr20,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr24,fr24,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr24,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr24,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr28,fr28,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr28,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr28,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr28,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr32,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr36,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr40,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr44,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr48,fr48,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr48,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr48,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr48,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr28,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr32,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr36,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr40,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr44,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr48,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr52,fr52,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr52,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr52,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr0,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr4,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr8,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr12,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr16,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr20,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr24,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr28,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr32,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr36,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr40,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr44,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr48,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr52,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr0,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr4,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr8,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr12,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr16,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr20,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr24,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr28,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr32,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr36,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr40,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr44,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr48,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr52,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + pass diff --git a/sim/testsuite/frv/fddivs.cgs b/sim/testsuite/frv/fddivs.cgs new file mode 100644 index 0000000..ac423b2 --- /dev/null +++ b/sim/testsuite/frv/fddivs.cgs @@ -0,0 +1,195 @@ +# frv testcase for fddivs $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fddivs +fddivs: + fddivs fr0,fr28,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fddivs fr4,fr28,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fddivs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fddivs fr12,fr28,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fddivs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr24,fr28,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fddivs fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fddivs fr32,fr28,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fddivs fr36,fr28,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fddivs fr40,fr28,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fddivs fr44,fr28,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fddivs fr48,fr28,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fddivs fr52,fr28,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fddivs fr16,fr0,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr52,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fddivs fr20,fr0,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr52,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fddivs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fddivs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + + fddivs fr40,fr32,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + + pass + + diff --git a/sim/testsuite/frv/fditos.cgs b/sim/testsuite/frv/fditos.cgs new file mode 100644 index 0000000..412e8af --- /dev/null +++ b/sim/testsuite/frv/fditos.cgs @@ -0,0 +1,25 @@ +# frv testcase for fditos $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fditos +fditos: + set_fr_iimmed 0,0,fr2 + set_fr_iimmed 0x0000,0x0002,fr3 + fditos fr2,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + + set_fr_iimmed 0xdead,0xbeef,fr2 + set_fr_iimmed 0xdead,0xbeef,fr3 + fditos fr2,fr2 + test_fr_iimmed 0xce054904,fr2 + test_fr_iimmed 0xce054904,fr3 + + pass diff --git a/sim/testsuite/frv/fdivd.cgs b/sim/testsuite/frv/fdivd.cgs new file mode 100644 index 0000000..65222bb --- /dev/null +++ b/sim/testsuite/frv/fdivd.cgs @@ -0,0 +1,128 @@ +# frv testcase for fdivd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fdivd +fdivd: + fdivd fr0,fr28,fr2 + test_dfr_dfr fr2,fr0 + fdivd fr4,fr28,fr2 + test_dfr_dfr fr2,fr4 + fdivd fr8,fr28,fr2 + test_dfr_dfr fr2,fr8 + fdivd fr12,fr28,fr2 + test_dfr_dfr fr2,fr12 + fdivd fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr24,fr28,fr2 + test_dfr_dfr fr2,fr24 + fdivd fr28,fr28,fr2 + test_dfr_dfr fr2,fr28 + fdivd fr32,fr28,fr2 + test_dfr_dfr fr2,fr32 + fdivd fr36,fr28,fr2 + test_dfr_dfr fr2,fr36 + fdivd fr40,fr28,fr2 + test_dfr_dfr fr2,fr40 + fdivd fr44,fr28,fr2 + test_dfr_dfr fr2,fr44 + fdivd fr48,fr28,fr2 + test_dfr_dfr fr2,fr48 + fdivd fr52,fr28,fr2 + test_dfr_dfr fr2,fr52 + + fdivd fr16,fr0,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr52,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fdivd fr20,fr0,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr52,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fdivd fr8,fr28,fr2 + test_dfr_dfr fr2,fr8 + fdivd fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + + fdivd fr40,fr32,fr2 + test_dfr_dfr fr2,fr36 + + pass + + diff --git a/sim/testsuite/frv/fdivs.cgs b/sim/testsuite/frv/fdivs.cgs new file mode 100644 index 0000000..cf2bd4b --- /dev/null +++ b/sim/testsuite/frv/fdivs.cgs @@ -0,0 +1,127 @@ +# frv testcase for fdivs $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdivs +fdivs: + fdivs fr0,fr28,fr1 + test_fr_fr fr1,fr0 + fdivs fr4,fr28,fr1 + test_fr_fr fr1,fr4 + fdivs fr8,fr28,fr1 + test_fr_fr fr1,fr8 + fdivs fr12,fr28,fr1 + test_fr_fr fr1,fr12 + fdivs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr24,fr28,fr1 + test_fr_fr fr1,fr24 + fdivs fr28,fr28,fr1 + test_fr_fr fr1,fr28 + fdivs fr32,fr28,fr1 + test_fr_fr fr1,fr32 + fdivs fr36,fr28,fr1 + test_fr_fr fr1,fr36 + fdivs fr40,fr28,fr1 + test_fr_fr fr1,fr40 + fdivs fr44,fr28,fr1 + test_fr_fr fr1,fr44 + fdivs fr48,fr28,fr1 + test_fr_fr fr1,fr48 + fdivs fr52,fr28,fr1 + test_fr_fr fr1,fr52 + + fdivs fr16,fr0,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr52,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fdivs fr20,fr0,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr52,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fdivs fr8,fr28,fr1 + test_fr_fr fr1,fr8 + fdivs fr28,fr8,fr1 + test_fr_fr fr1,fr8 + + fdivs fr40,fr32,fr1 + test_fr_fr fr1,fr36 + + pass + + diff --git a/sim/testsuite/frv/fdmadds.cgs b/sim/testsuite/frv/fdmadds.cgs new file mode 100644 index 0000000..7035366 --- /dev/null +++ b/sim/testsuite/frv/fdmadds.cgs @@ -0,0 +1,226 @@ +# frv testcase for fdmadds $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdmadds +fdmadds: + fdmadds fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmadds fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + set_fr_fr fr36,fr2 + set_fr_fr fr36,fr3 + fdmadds fr28,fr8,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdmadds fr8,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + + set_fr_fr fr36,fr2 + set_fr_fr fr36,fr3 + fdmadds fr32,fr36,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + + pass diff --git a/sim/testsuite/frv/fdmas.cgs b/sim/testsuite/frv/fdmas.cgs new file mode 100644 index 0000000..a7162db --- /dev/null +++ b/sim/testsuite/frv/fdmas.cgs @@ -0,0 +1,265 @@ +# frv testcase for fdmas $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + load_float_constants2 + load_float_constants3 + + .global fdmas +fdmas: + fdmas fr16,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr4 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr4 + fdmas fr16,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + fdmas fr16,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr12 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr12 + fdmas fr16,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr16,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr16,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr24 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr24 + fdmas fr16,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmas fr16,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr32 + fdmas fr16,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr36 + fdmas fr16,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr40 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr40 + fdmas fr16,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr44 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr44 + fdmas fr16,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr48 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr48 + + fdmas fr20,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr4 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr4 + fdmas fr20,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + fdmas fr20,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr12 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr12 + fdmas fr20,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr20,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr20,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr24 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr24 + fdmas fr20,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmas fr20,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr32 + fdmas fr20,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr36 + fdmas fr20,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr40 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr40 + fdmas fr20,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr44 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr44 + fdmas fr20,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr48 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr48 + + fdmas fr28,fr0,fr60 + test_fr_fr fr60,fr0 + test_fr_fr fr62,fr0 + fdmas fr28,fr4,fr60 + test_fr_fr fr60,fr4 + test_fr_fr fr62,fr4 + fdmas fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr28,fr12,fr60 + test_fr_fr fr60,fr12 + test_fr_fr fr62,fr12 + fdmas fr28,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmas fr28,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmas fr28,fr24,fr60 + test_fr_fr fr60,fr24 + test_fr_fr fr62,fr24 + fdmas fr28,fr28,fr60 + test_fr_fr fr60,fr28 + test_fr_fr fr62,fr28 + fdmas fr28,fr32,fr60 + test_fr_fr fr60,fr32 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr32 + test_fr_fr fr63,fr36 + fdmas fr28,fr36,fr60 + test_fr_fr fr60,fr36 + test_fr_fr fr62,fr36 + fdmas fr28,fr40,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + fdmas fr28,fr44,fr60 + test_fr_fr fr60,fr44 + test_fr_fr fr62,fr44 + fdmas fr28,fr48,fr60 + test_fr_fr fr60,fr48 + test_fr_fr fr62,fr48 + fdmas fr28,fr52,fr60 + test_fr_fr fr60,fr52 + test_fr_fr fr62,fr52 + + fdmas fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr8,fr28,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + + fdmas fr32,fr36,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + + pass diff --git a/sim/testsuite/frv/fdmovs.cgs b/sim/testsuite/frv/fdmovs.cgs new file mode 100644 index 0000000..58e9607 --- /dev/null +++ b/sim/testsuite/frv/fdmovs.cgs @@ -0,0 +1,45 @@ +# frv testcase for fdmovs $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdmovs +fdmovs: + set_fr_fr fr4,fr1 + fdmovs fr0,fr2 + test_fr_fr fr0,fr2 + test_fr_fr fr4,fr3 + set_fr_fr fr12,fr9 + fdmovs fr8,fr2 + test_fr_fr fr8,fr2 + test_fr_fr fr12,fr3 + set_fr_fr fr20,fr17 + fdmovs fr16,fr2 + test_fr_fr fr16,fr2 + test_fr_fr fr20,fr3 + set_fr_fr fr28,fr25 + fdmovs fr24,fr2 + test_fr_fr fr24,fr2 + test_fr_fr fr28,fr3 + set_fr_fr fr36,fr33 + fdmovs fr32,fr2 + test_fr_fr fr32,fr2 + test_fr_fr fr36,fr3 + set_fr_fr fr44,fr41 + fdmovs fr40,fr2 + test_fr_fr fr40,fr2 + test_fr_fr fr44,fr3 + set_fr_fr fr52,fr49 + fdmovs fr48,fr2 + test_fr_fr fr48,fr2 + test_fr_fr fr52,fr3 + set_fr_fr fr60,fr57 + fdmovs fr56,fr2 + test_fr_iimmed 0x7fc00000,fr2 + test_fr_iimmed 0x7f800001,fr3 + + pass diff --git a/sim/testsuite/frv/fdmss.cgs b/sim/testsuite/frv/fdmss.cgs new file mode 100644 index 0000000..5457a1e --- /dev/null +++ b/sim/testsuite/frv/fdmss.cgs @@ -0,0 +1,235 @@ +# frv testcase for fdmss $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + load_float_constants2 + load_float_constants3 + + .global fdmss +fdmss: + fdmss fr16,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmss fr16,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmss fr16,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmss fr16,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + fdmss fr16,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + + fdmss fr20,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmss fr20,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmss fr20,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmss fr20,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + fdmss fr20,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + + fdmss fr28,fr0,fr60 + test_fr_fr fr60,fr0 + test_fr_fr fr62,fr0 + fdmss fr28,fr4,fr60 + test_fr_fr fr60,fr4 + test_fr_fr fr62,fr4 + fdmss fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr32 + fdmss fr28,fr12,fr60 + test_fr_fr fr60,fr12 + test_fr_fr fr62,fr12 + fdmss fr28,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmss fr28,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmss fr28,fr24,fr60 + test_fr_fr fr60,fr24 + test_fr_fr fr62,fr24 + fdmss fr28,fr28,fr60 + test_fr_fr fr60,fr28 + test_fr_fr fr61,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr62,fr28 + test_fr_fr fr63,fr20 + test_fr_fr fr63,fr16 + fdmss fr28,fr32,fr60 + test_fr_fr fr60,fr32 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr32 + test_fr_fr fr63,fr8 + fdmss fr28,fr36,fr60 + test_fr_fr fr60,fr36 + test_fr_fr fr62,fr36 + fdmss fr28,fr40,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + fdmss fr28,fr44,fr60 + test_fr_fr fr60,fr44 + test_fr_fr fr62,fr44 + fdmss fr28,fr48,fr60 + test_fr_fr fr60,fr48 + test_fr_fr fr62,fr48 + fdmss fr28,fr52,fr60 + test_fr_fr fr60,fr52 + test_fr_fr fr62,fr52 + + fdmss fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr32 + fdmss fr8,fr28,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr62,fr8 + + fdmss fr32,fr36,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr40 + test_fr_fr fr63,fr8 + + pass diff --git a/sim/testsuite/frv/fdmulcs.cgs b/sim/testsuite/frv/fdmulcs.cgs new file mode 100644 index 0000000..a7cb159 --- /dev/null +++ b/sim/testsuite/frv/fdmulcs.cgs @@ -0,0 +1,201 @@ +# frv testcase for fdmulcs $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdmulcs +fdmulcs: + fdmulcs fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmulcs fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr2,fr20 + fdmulcs fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmulcs fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdmulcs fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdmulcs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdmulcs fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdmulcs fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdmulcs fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdmulcs fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdmulcs fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdmulcs fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdmulcs fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdmulcs fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdmulcs fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdmulcs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdmulcs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + + fdmulcs fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + + set_fr_fr fr32,fr50 ; 2 + set_fr_fr fr28,fr51 ; 1 + set_fr_fr fr44,fr52 ; 9 + set_fr_fr fr36,fr53 ; 3 + fdmulcs fr50,fr52,fr54 ; 2*3, 1*9 + test_fr_fr fr54,fr40 ; 6 + test_fr_fr fr55,fr44 ; 9 + + pass diff --git a/sim/testsuite/frv/fdmuls.cgs b/sim/testsuite/frv/fdmuls.cgs new file mode 100644 index 0000000..2c2c05a --- /dev/null +++ b/sim/testsuite/frv/fdmuls.cgs @@ -0,0 +1,193 @@ +# frv testcase for fdmuls $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdmuls +fdmuls: + fdmuls fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmuls fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr2,fr20 + fdmuls fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmuls fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdmuls fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdmuls fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdmuls fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdmuls fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdmuls fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdmuls fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdmuls fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdmuls fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdmuls fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdmuls fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdmuls fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdmuls fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdmuls fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + + fdmuls fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + + pass diff --git a/sim/testsuite/frv/fdnegs.cgs b/sim/testsuite/frv/fdnegs.cgs new file mode 100644 index 0000000..db409cb --- /dev/null +++ b/sim/testsuite/frv/fdnegs.cgs @@ -0,0 +1,25 @@ +# frv testcase for fdnegs $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdnegs +fdnegs: + set_fr_fr fr8,fr1 + fdnegs fr0,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr28 + set_fr_fr fr24,fr13 + fdnegs fr12,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + set_fr_fr fr52,fr29 + fdnegs fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr0 + + pass diff --git a/sim/testsuite/frv/fdsads.cgs b/sim/testsuite/frv/fdsads.cgs new file mode 100644 index 0000000..123810d --- /dev/null +++ b/sim/testsuite/frv/fdsads.cgs @@ -0,0 +1,119 @@ +# frv testcase for fdsads $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdsads +fdsads: + fdsads fr16,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr52 + fdsads fr16,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr48 + fdsads fr16,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr28 + fdsads fr16,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr24 + fdsads fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsads fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsads fr16,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + fdsads fr16,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr8 + fdsads fr16,fr32,fr2 + test_fr_fr fr2,fr32 + fdsads fr16,fr36,fr2 + test_fr_fr fr2,fr36 + fdsads fr16,fr40,fr2 + test_fr_fr fr2,fr40 + fdsads fr16,fr44,fr2 + test_fr_fr fr2,fr44 + fdsads fr16,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr4 + fdsads fr16,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr0 + + fdsads fr20,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr52 + fdsads fr20,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr48 + fdsads fr20,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr28 + fdsads fr20,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr24 + fdsads fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsads fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsads fr20,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + fdsads fr20,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr8 + fdsads fr20,fr32,fr2 + test_fr_fr fr2,fr32 + fdsads fr20,fr36,fr2 + test_fr_fr fr2,fr36 + fdsads fr20,fr40,fr2 + test_fr_fr fr2,fr40 + fdsads fr20,fr44,fr2 + test_fr_fr fr2,fr44 + fdsads fr20,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr4 + fdsads fr20,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr0 + + fdsads fr8,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fdsads fr12,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fdsads fr24,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fdsads fr28,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_fr_fr fr3,fr32 + + fdsads fr36,fr40,fr2 + test_fr_fr fr2,fr44 + + pass + + diff --git a/sim/testsuite/frv/fdsqrts.cgs b/sim/testsuite/frv/fdsqrts.cgs new file mode 100644 index 0000000..6026b93 --- /dev/null +++ b/sim/testsuite/frv/fdsqrts.cgs @@ -0,0 +1,17 @@ +# frv testcase for fdsqrts $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdsqrts +fdsqrts: + set_fr_iimmed 0x4049,0x0fdb,fr45 ; 3.141592654 + fdsqrts fr44,fr2 ; 9.0 + test_fr_fr fr2,fr36 ; 3.0 + test_fr_iimmed 0x3fe2dfc5,fr3 ; 1.7724539 + + pass diff --git a/sim/testsuite/frv/fdstoi.cgs b/sim/testsuite/frv/fdstoi.cgs new file mode 100644 index 0000000..5c79e49 --- /dev/null +++ b/sim/testsuite/frv/fdstoi.cgs @@ -0,0 +1,23 @@ +# frv testcase for fdstoi $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdstoi +fdstoi: + set_fr_fr fr20,fr17 + fdstoi fr16,fr2 + test_fr_iimmed 0,fr2 + test_fr_iimmed 0,fr3 + + set_fr_iimmed 0xce05,0x4904,fr2 + set_fr_fr fr32,fr3 + fdstoi fr2,fr2 + test_fr_iimmed 0xdeadbf00,fr2 + test_fr_iimmed 0x00000002,fr3 + + pass diff --git a/sim/testsuite/frv/fdsubs.cgs b/sim/testsuite/frv/fdsubs.cgs new file mode 100644 index 0000000..93dae46 --- /dev/null +++ b/sim/testsuite/frv/fdsubs.cgs @@ -0,0 +1,117 @@ +# frv testcase for fdsubs $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdsubs +fdsubs: + fdsubs fr0,fr16,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdsubs fr4,fr16,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdsubs fr8,fr16,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdsubs fr12,fr16,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdsubs fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsubs fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsubs fr24,fr16,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdsubs fr28,fr16,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdsubs fr32,fr16,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdsubs fr36,fr16,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdsubs fr40,fr16,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdsubs fr44,fr16,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdsubs fr48,fr16,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdsubs fr52,fr16,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdsubs fr0,fr20,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdsubs fr4,fr20,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdsubs fr8,fr20,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdsubs fr12,fr20,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdsubs fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsubs fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsubs fr24,fr20,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdsubs fr28,fr20,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdsubs fr32,fr20,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdsubs fr36,fr20,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdsubs fr40,fr20,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdsubs fr44,fr20,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdsubs fr48,fr20,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdsubs fr52,fr20,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdsubs fr32,fr36,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + + fdsubs fr44,fr40,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + + pass + + diff --git a/sim/testsuite/frv/fdtoi.cgs b/sim/testsuite/frv/fdtoi.cgs new file mode 100644 index 0000000..1749852 --- /dev/null +++ b/sim/testsuite/frv/fdtoi.cgs @@ -0,0 +1,32 @@ +# frv testcase for fdtoi $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global fdtoi +fdtoi: + set_fr_iimmed 0,0,fr2 + set_fr_iimmed 0,0,fr3 + fdtoi fr2,fr2 + test_fr_iimmed 0,fr2 + + set_fr_iimmed 0x4000,0x0000,fr2 + set_fr_iimmed 0x0000,0x0000,fr3 + fdtoi fr2,fr2 + test_fr_iimmed 0x00000002,fr2 + + set_fr_iimmed 0xc1c0,0xa920,fr2 + set_fr_iimmed 0x8880,0x0000,fr3 + fdtoi fr2,fr2 + test_fr_iimmed 0xdeadbeef,fr2 + + set_gr_limmed 0x4031,0x0000,gr8 + set_gr_limmed 0x0000,0x0000,gr9 + movgfd gr8,fr0 + fdtoi fr0,fr0 + test_fr_iimmed 17,fr0 + + pass diff --git a/sim/testsuite/frv/fitod.cgs b/sim/testsuite/frv/fitod.cgs new file mode 100644 index 0000000..62ef1f2 --- /dev/null +++ b/sim/testsuite/frv/fitod.cgs @@ -0,0 +1,26 @@ +# frv testcase for fitod $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global fitod +fitod: + set_fr_iimmed 0,0,fr2 + fitod fr2,fr2 + test_fr_iimmed 0,fr2 + test_fr_iimmed 0,fr3 + + set_fr_iimmed 0x0000,0x0002,fr2 + fitod fr2,fr2 + test_fr_iimmed 0x40000000,fr2 + test_fr_iimmed 0x00000000,fr3 + + set_fr_iimmed 0xdead,0xbeef,fr2 + fitod fr2,fr2 + test_fr_iimmed 0xc1c0a920,fr2 + test_fr_iimmed 0x88800000,fr3 + + pass diff --git a/sim/testsuite/frv/fitos.cgs b/sim/testsuite/frv/fitos.cgs new file mode 100644 index 0000000..2afe290 --- /dev/null +++ b/sim/testsuite/frv/fitos.cgs @@ -0,0 +1,25 @@ +# frv testcase for fitos $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fitos +fitos: + set_fr_iimmed 0,0,fr1 + fitos fr1,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_iimmed 0x0000,0x0002,fr1 + fitos fr1,fr1 + test_fr_fr fr1,fr32 + + set_fr_iimmed 0xdead,0xbeef,fr1 + fitos fr1,fr1 + test_fr_iimmed 0xce054904,fr1 + + pass diff --git a/sim/testsuite/frv/fmad.cgs b/sim/testsuite/frv/fmad.cgs new file mode 100644 index 0000000..64fee9c --- /dev/null +++ b/sim/testsuite/frv/fmad.cgs @@ -0,0 +1,161 @@ +# frv testcase for fmad $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fmad +fmad: + fmad fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + fmad fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmad fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + fmad fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + fmad fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmad fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + fmad fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + fmad fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + fmad fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + fmad fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + fmad fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + fmad fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmad fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + fmad fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + fmad fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmad fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + fmad fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + fmad fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + fmad fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + fmad fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + fmad fr28,fr0,fr2 + test_fr_fr fr2,fr0 + fmad fr28,fr4,fr2 + test_fr_fr fr2,fr4 + fmad fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr28,fr12,fr2 + test_fr_fr fr2,fr12 + fmad fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmad fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmad fr28,fr24,fr2 + test_fr_fr fr2,fr24 + fmad fr28,fr28,fr2 + test_fr_fr fr2,fr28 + fmad fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + fmad fr28,fr36,fr2 + test_fr_fr fr2,fr36 + fmad fr28,fr40,fr2 + test_fr_fr fr2,fr40 + fmad fr28,fr44,fr2 + test_fr_fr fr2,fr44 + fmad fr28,fr48,fr2 + test_fr_fr fr2,fr48 + fmad fr28,fr52,fr2 + test_fr_fr fr2,fr52 + + fmad fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fmad fr32,fr36,fr2 + test_fr_fr fr2,fr40 + + pass diff --git a/sim/testsuite/frv/fmaddd.cgs b/sim/testsuite/frv/fmaddd.cgs new file mode 100644 index 0000000..bfa816f --- /dev/null +++ b/sim/testsuite/frv/fmaddd.cgs @@ -0,0 +1,143 @@ +# frv testcase for fmaddd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fmaddd +fmaddd: + set_dfr_dfr fr16,fr2 + fmaddd fr16,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fmaddd fr20,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr0,fr2 + test_dfr_dfr fr2,fr0 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr4,fr2 + test_dfr_dfr fr2,fr4 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr12,fr2 + test_dfr_dfr fr2,fr12 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr24,fr2 + test_dfr_dfr fr2,fr24 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr28,fr2 + test_dfr_dfr fr2,fr28 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr32,fr2 + test_dfr_dfr fr2,fr32 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr36,fr2 + test_dfr_dfr fr2,fr36 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr40,fr2 + test_dfr_dfr fr2,fr40 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr44,fr2 + test_dfr_dfr fr2,fr44 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr48,fr2 + test_dfr_dfr fr2,fr48 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr52,fr2 + test_dfr_dfr fr2,fr52 + + set_dfr_dfr fr36,fr2 + fmaddd fr28,fr8,fr2 + test_dfr_dfr fr2,fr32 + fmaddd fr8,fr28,fr2 + test_dfr_dfr fr2,fr28 + + set_dfr_dfr fr36,fr2 + fmaddd fr32,fr36,fr2 + test_dfr_dfr fr2,fr44 + + pass diff --git a/sim/testsuite/frv/fmadds.cgs b/sim/testsuite/frv/fmadds.cgs new file mode 100644 index 0000000..128c82a --- /dev/null +++ b/sim/testsuite/frv/fmadds.cgs @@ -0,0 +1,143 @@ +# frv testcase for fmadds $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fmadds +fmadds: + set_fr_fr fr16,fr1 + fmadds fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fmadds fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + fmadds fr28,fr0,fr1 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + fmadds fr28,fr4,fr1 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + fmadds fr28,fr8,fr1 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + fmadds fr28,fr12,fr1 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + fmadds fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + fmadds fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + fmadds fr28,fr24,fr1 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + fmadds fr28,fr28,fr1 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + fmadds fr28,fr32,fr1 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + fmadds fr28,fr36,fr1 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + fmadds fr28,fr40,fr1 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + fmadds fr28,fr44,fr1 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + fmadds fr28,fr48,fr1 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + fmadds fr28,fr52,fr1 + test_fr_fr fr1,fr52 + + set_fr_fr fr36,fr1 + fmadds fr28,fr8,fr1 + test_fr_fr fr1,fr32 + fmadds fr8,fr28,fr1 + test_fr_fr fr1,fr28 + + set_fr_fr fr36,fr1 + fmadds fr32,fr36,fr1 + test_fr_fr fr1,fr44 + + pass diff --git a/sim/testsuite/frv/fmas.cgs b/sim/testsuite/frv/fmas.cgs new file mode 100644 index 0000000..1e7b1df --- /dev/null +++ b/sim/testsuite/frv/fmas.cgs @@ -0,0 +1,161 @@ +# frv testcase for fmas $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fmas +fmas: + fmas fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + fmas fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmas fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + fmas fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + fmas fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmas fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + fmas fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + fmas fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + fmas fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + fmas fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + fmas fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + fmas fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmas fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + fmas fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + fmas fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmas fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + fmas fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + fmas fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + fmas fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + fmas fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + fmas fr28,fr0,fr2 + test_fr_fr fr2,fr0 + fmas fr28,fr4,fr2 + test_fr_fr fr2,fr4 + fmas fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr28,fr12,fr2 + test_fr_fr fr2,fr12 + fmas fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmas fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmas fr28,fr24,fr2 + test_fr_fr fr2,fr24 + fmas fr28,fr28,fr2 + test_fr_fr fr2,fr28 + fmas fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + fmas fr28,fr36,fr2 + test_fr_fr fr2,fr36 + fmas fr28,fr40,fr2 + test_fr_fr fr2,fr40 + fmas fr28,fr44,fr2 + test_fr_fr fr2,fr44 + fmas fr28,fr48,fr2 + test_fr_fr fr2,fr48 + fmas fr28,fr52,fr2 + test_fr_fr fr2,fr52 + + fmas fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fmas fr32,fr36,fr2 + test_fr_fr fr2,fr40 + + pass diff --git a/sim/testsuite/frv/fmovd.cgs b/sim/testsuite/frv/fmovd.cgs new file mode 100644 index 0000000..938faa2 --- /dev/null +++ b/sim/testsuite/frv/fmovd.cgs @@ -0,0 +1,48 @@ +# frv testcase for fmovd $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fmovd +fmovd: + fmovd fr0,fr2 + test_dfr_dfr fr0,fr2 + fmovd fr4,fr2 + test_dfr_dfr fr4,fr2 + fmovd fr8,fr2 + test_dfr_dfr fr8,fr2 + fmovd fr12,fr2 + test_dfr_dfr fr12,fr2 + fmovd fr16,fr2 + test_dfr_dfr fr16,fr2 + fmovd fr20,fr2 + test_dfr_dfr fr20,fr2 + fmovd fr24,fr2 + test_dfr_dfr fr24,fr2 + fmovd fr28,fr2 + test_dfr_dfr fr28,fr2 + fmovd fr32,fr2 + test_dfr_dfr fr32,fr2 + fmovd fr36,fr2 + test_dfr_dfr fr36,fr2 + fmovd fr40,fr2 + test_dfr_dfr fr40,fr2 + fmovd fr44,fr2 + test_dfr_dfr fr44,fr2 + fmovd fr48,fr2 + test_dfr_dfr fr48,fr2 + fmovd fr52,fr2 + test_dfr_dfr fr52,fr2 + fmovd fr56,fr2 + test_fr_iimmed 0x7ff80000,fr2 + test_fr_iimmed 0x00000000,fr3 + fmovd fr60,fr2 + test_fr_iimmed 0x7ff00000,fr2 + test_fr_iimmed 0x00000001,fr3 + + pass diff --git a/sim/testsuite/frv/fmovs.cgs b/sim/testsuite/frv/fmovs.cgs new file mode 100644 index 0000000..2a70277 --- /dev/null +++ b/sim/testsuite/frv/fmovs.cgs @@ -0,0 +1,45 @@ +# frv testcase for fmovs $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fmovs +fmovs: + fmovs fr0,fr1 + test_fr_fr fr0,fr1 + fmovs fr4,fr1 + test_fr_fr fr4,fr1 + fmovs fr8,fr1 + test_fr_fr fr8,fr1 + fmovs fr12,fr1 + test_fr_fr fr12,fr1 + fmovs fr16,fr1 + test_fr_fr fr16,fr1 + fmovs fr20,fr1 + test_fr_fr fr20,fr1 + fmovs fr24,fr1 + test_fr_fr fr24,fr1 + fmovs fr28,fr1 + test_fr_fr fr28,fr1 + fmovs fr32,fr1 + test_fr_fr fr32,fr1 + fmovs fr36,fr1 + test_fr_fr fr36,fr1 + fmovs fr40,fr1 + test_fr_fr fr40,fr1 + fmovs fr44,fr1 + test_fr_fr fr44,fr1 + fmovs fr48,fr1 + test_fr_fr fr48,fr1 + fmovs fr52,fr1 + test_fr_fr fr52,fr1 + fmovs fr56,fr1 + test_fr_iimmed 0x7fc00000,fr1 + fmovs fr60,fr1 + test_fr_iimmed 0x7f800001,fr1 + + pass diff --git a/sim/testsuite/frv/fmsd.cgs b/sim/testsuite/frv/fmsd.cgs new file mode 100644 index 0000000..cd2efbd --- /dev/null +++ b/sim/testsuite/frv/fmsd.cgs @@ -0,0 +1,146 @@ +# frv testcase for fmsd $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fmsd +fmsd: + fmsd fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmsd fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmsd fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmsd fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmsd fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + fmsd fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmsd fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmsd fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmsd fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmsd fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + fmsd fr28,fr0,fr2 + test_fr_fr fr2,fr0 + fmsd fr28,fr4,fr2 + test_fr_fr fr2,fr4 + fmsd fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + fmsd fr28,fr12,fr2 + test_fr_fr fr2,fr12 + fmsd fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmsd fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmsd fr28,fr24,fr2 + test_fr_fr fr2,fr24 + fmsd fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + fmsd fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + fmsd fr28,fr36,fr2 + test_fr_fr fr2,fr36 + fmsd fr28,fr40,fr2 + test_fr_fr fr2,fr40 + fmsd fr28,fr44,fr2 + test_fr_fr fr2,fr44 + fmsd fr28,fr48,fr2 + test_fr_fr fr2,fr48 + fmsd fr28,fr52,fr2 + test_fr_fr fr2,fr52 + + fmsd fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + fmsd fr8,fr28,fr2 + test_fr_fr fr2,fr8 + + fmsd fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 + + pass diff --git a/sim/testsuite/frv/fmss.cgs b/sim/testsuite/frv/fmss.cgs new file mode 100644 index 0000000..defe069 --- /dev/null +++ b/sim/testsuite/frv/fmss.cgs @@ -0,0 +1,146 @@ +# frv testcase for fmss $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fmss +fmss: + fmss fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmss fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmss fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmss fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmss fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + fmss fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmss fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmss fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmss fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmss fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + fmss fr28,fr0,fr2 + test_fr_fr fr2,fr0 + fmss fr28,fr4,fr2 + test_fr_fr fr2,fr4 + fmss fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + fmss fr28,fr12,fr2 + test_fr_fr fr2,fr12 + fmss fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmss fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmss fr28,fr24,fr2 + test_fr_fr fr2,fr24 + fmss fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + fmss fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + fmss fr28,fr36,fr2 + test_fr_fr fr2,fr36 + fmss fr28,fr40,fr2 + test_fr_fr fr2,fr40 + fmss fr28,fr44,fr2 + test_fr_fr fr2,fr44 + fmss fr28,fr48,fr2 + test_fr_fr fr2,fr48 + fmss fr28,fr52,fr2 + test_fr_fr fr2,fr52 + + fmss fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + fmss fr8,fr28,fr2 + test_fr_fr fr2,fr8 + + fmss fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 + + pass diff --git a/sim/testsuite/frv/fmsubd.cgs b/sim/testsuite/frv/fmsubd.cgs new file mode 100644 index 0000000..6b4c943 --- /dev/null +++ b/sim/testsuite/frv/fmsubd.cgs @@ -0,0 +1,144 @@ +# frv testcase for fmsubd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fmsubd +fmsubd: + set_dfr_dfr fr16,fr2 + fmsubd fr16,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fmsubd fr20,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr0,fr2 + test_dfr_dfr fr2,fr0 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr4,fr2 + test_dfr_dfr fr2,fr4 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr12,fr2 + test_dfr_dfr fr2,fr12 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr24,fr2 + test_dfr_dfr fr2,fr24 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr28,fr2 + test_dfr_dfr fr2,fr28 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr32,fr2 + test_dfr_dfr fr2,fr32 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr36,fr2 + test_dfr_dfr fr2,fr36 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr40,fr2 + test_dfr_dfr fr2,fr40 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr44,fr2 + test_dfr_dfr fr2,fr44 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr48,fr2 + test_dfr_dfr fr2,fr48 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr52,fr2 + test_dfr_dfr fr2,fr52 + + set_dfr_dfr fr32,fr2 + fmsubd fr8,fr8,fr2 + test_dfr_dfr fr2,fr8 + set_dfr_dfr fr36,fr2 + fmsubd fr36,fr36,fr2 + test_dfr_dfr fr2,fr40 + + fmsubd fr32,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + pass diff --git a/sim/testsuite/frv/fmsubs.cgs b/sim/testsuite/frv/fmsubs.cgs new file mode 100644 index 0000000..14a5bb3 --- /dev/null +++ b/sim/testsuite/frv/fmsubs.cgs @@ -0,0 +1,144 @@ +# frv testcase for fmsubs $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fmsubs +fmsubs: + set_fr_fr fr16,fr1 + fmsubs fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fmsubs fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + fmsubs fr28,fr0,fr1 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + fmsubs fr28,fr4,fr1 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + fmsubs fr28,fr8,fr1 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + fmsubs fr28,fr12,fr1 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + fmsubs fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + fmsubs fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + fmsubs fr28,fr24,fr1 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + fmsubs fr28,fr28,fr1 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + fmsubs fr28,fr32,fr1 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + fmsubs fr28,fr36,fr1 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + fmsubs fr28,fr40,fr1 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + fmsubs fr28,fr44,fr1 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + fmsubs fr28,fr48,fr1 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + fmsubs fr28,fr52,fr1 + test_fr_fr fr1,fr52 + + set_fr_fr fr32,fr1 + fmsubs fr8,fr8,fr1 + test_fr_fr fr1,fr8 + set_fr_fr fr36,fr1 + fmsubs fr36,fr36,fr1 + test_fr_fr fr1,fr40 + + fmsubs fr32,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + pass diff --git a/sim/testsuite/frv/fmuld.cgs b/sim/testsuite/frv/fmuld.cgs new file mode 100644 index 0000000..e06ca07 --- /dev/null +++ b/sim/testsuite/frv/fmuld.cgs @@ -0,0 +1,126 @@ +# frv testcase for fmuld $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fmuld +fmuld: + fmuld fr16,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fmuld fr20,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fmuld fr28,fr0,fr2 + test_dfr_dfr fr2,fr0 + fmuld fr28,fr4,fr2 + test_dfr_dfr fr2,fr4 + fmuld fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + fmuld fr28,fr12,fr2 + test_dfr_dfr fr2,fr12 + fmuld fr28,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr28,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr28,fr24,fr2 + test_dfr_dfr fr2,fr24 + fmuld fr28,fr28,fr2 + test_dfr_dfr fr2,fr28 + fmuld fr28,fr32,fr2 + test_dfr_dfr fr2,fr32 + fmuld fr28,fr36,fr2 + test_dfr_dfr fr2,fr36 + fmuld fr28,fr40,fr2 + test_dfr_dfr fr2,fr40 + fmuld fr28,fr44,fr2 + test_dfr_dfr fr2,fr44 + fmuld fr28,fr48,fr2 + test_dfr_dfr fr2,fr48 + fmuld fr28,fr52,fr2 + test_dfr_dfr fr2,fr52 + + fmuld fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + fmuld fr8,fr28,fr2 + test_dfr_dfr fr2,fr8 + + fmuld fr32,fr36,fr2 + test_dfr_dfr fr2,fr40 + + pass diff --git a/sim/testsuite/frv/fmuls.cgs b/sim/testsuite/frv/fmuls.cgs new file mode 100644 index 0000000..a92fa1e --- /dev/null +++ b/sim/testsuite/frv/fmuls.cgs @@ -0,0 +1,125 @@ +# frv testcase for fmuls $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fmuls +fmuls: + fmuls fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fmuls fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fmuls fr28,fr0,fr1 + test_fr_fr fr1,fr0 + fmuls fr28,fr4,fr1 + test_fr_fr fr1,fr4 + fmuls fr28,fr8,fr1 + test_fr_fr fr1,fr8 + fmuls fr28,fr12,fr1 + test_fr_fr fr1,fr12 + fmuls fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr28,fr24,fr1 + test_fr_fr fr1,fr24 + fmuls fr28,fr28,fr1 + test_fr_fr fr1,fr28 + fmuls fr28,fr32,fr1 + test_fr_fr fr1,fr32 + fmuls fr28,fr36,fr1 + test_fr_fr fr1,fr36 + fmuls fr28,fr40,fr1 + test_fr_fr fr1,fr40 + fmuls fr28,fr44,fr1 + test_fr_fr fr1,fr44 + fmuls fr28,fr48,fr1 + test_fr_fr fr1,fr48 + fmuls fr28,fr52,fr1 + test_fr_fr fr1,fr52 + + fmuls fr28,fr8,fr1 + test_fr_fr fr1,fr8 + fmuls fr8,fr28,fr1 + test_fr_fr fr1,fr8 + + fmuls fr32,fr36,fr1 + test_fr_fr fr1,fr40 + + pass diff --git a/sim/testsuite/frv/fnegd.cgs b/sim/testsuite/frv/fnegd.cgs new file mode 100644 index 0000000..c18721b --- /dev/null +++ b/sim/testsuite/frv/fnegd.cgs @@ -0,0 +1,26 @@ +# frv testcase for fnegd $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fnegd +fnegd: + fnegd fr0,fr2 + test_dfr_dfr fr2,fr52 + fnegd fr8,fr2 + test_dfr_dfr fr2,fr28 + fnegd fr12,fr2 + test_dfr_dfr fr2,fr24 + fnegd fr24,fr2 + test_dfr_dfr fr2,fr12 + fnegd fr28,fr2 + test_dfr_dfr fr2,fr8 + fnegd fr52,fr2 + test_dfr_dfr fr2,fr0 + + pass diff --git a/sim/testsuite/frv/fnegs.cgs b/sim/testsuite/frv/fnegs.cgs new file mode 100644 index 0000000..fdb8770 --- /dev/null +++ b/sim/testsuite/frv/fnegs.cgs @@ -0,0 +1,25 @@ +# frv testcase for fnegs $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fnegs +fnegs: + fnegs fr0,fr1 + test_fr_fr fr1,fr52 + fnegs fr8,fr1 + test_fr_fr fr1,fr28 + fnegs fr12,fr1 + test_fr_fr fr1,fr24 + fnegs fr24,fr1 + test_fr_fr fr1,fr12 + fnegs fr28,fr1 + test_fr_fr fr1,fr8 + fnegs fr52,fr1 + test_fr_fr fr1,fr0 + + pass diff --git a/sim/testsuite/frv/fnop.cgs b/sim/testsuite/frv/fnop.cgs new file mode 100644 index 0000000..5e48384 --- /dev/null +++ b/sim/testsuite/frv/fnop.cgs @@ -0,0 +1,12 @@ +# frv testcase for fnop +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global fnop +fnop: + fnop + + pass diff --git a/sim/testsuite/frv/fr400/addss.cgs b/sim/testsuite/frv/fr400/addss.cgs new file mode 100644 index 0000000..b108f50 --- /dev/null +++ b/sim/testsuite/frv/fr400/addss.cgs @@ -0,0 +1,36 @@ +# frv testcase for addss $GRi,$GRj,$GRk +# mach: fr405 fr450 + + .include "../testutils.inc" + + start + + .global add +add_nosaturate: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + addss gr7,gr8,gr8 + test_gr_immed 3,gr8 +add_saturate_pos: + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + addss gr7,gr8,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0x4000,0x0000,gr7 + set_gr_limmed 0x4000,0x0000,gr8 + addss gr7,gr8,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + +add_saturate_neg: + set_gr_limmed 0x8000,0x0000,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + addss gr7,gr8,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0001,gr7 + set_gr_limmed 0x8000,0x0001,gr8 + addss gr7,gr8,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + + pass diff --git a/sim/testsuite/frv/fr400/allinsn.exp b/sim/testsuite/frv/fr400/allinsn.exp new file mode 100644 index 0000000..b169761 --- /dev/null +++ b/sim/testsuite/frv/fr400/allinsn.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "fr400 fr405 fr450 fr550" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/frv/fr400/csdiv.cgs b/sim/testsuite/frv/fr400/csdiv.cgs new file mode 100644 index 0000000..9fa6d8c --- /dev/null +++ b/sim/testsuite/frv/fr400/csdiv.cgs @@ -0,0 +1,187 @@ +# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global csdiv +csdiv: + set_spr_immed 0x1b1b,cccr + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e1: csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e2: csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed 2,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/fr400/maddaccs.cgs b/sim/testsuite/frv/fr400/maddaccs.cgs new file mode 100644 index 0000000..98659c4 --- /dev/null +++ b/sim/testsuite/frv/fr400/maddaccs.cgs @@ -0,0 +1,131 @@ +# frv testcase for maddaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global maddaccs +maddaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0xdead,0xbeef,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0xbeef,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x2345,0x6789,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + maddaccs.p acc0,acc1 + maddaccs acc2,acc3 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/frv/fr400/masaccs.cgs b/sim/testsuite/frv/fr400/masaccs.cgs new file mode 100644 index 0000000..8fbde91 --- /dev/null +++ b/sim/testsuite/frv/fr400/masaccs.cgs @@ -0,0 +1,151 @@ +# frv testcase for masaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global masaccs +masaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0xdead,0xbeef,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0xbeef,0xdead,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0x4111,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x2345,0x6789,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xfffc,0x7ffd,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0003,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + masaccs.p acc0,acc0 + masaccs acc2,acc2 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + + pass diff --git a/sim/testsuite/frv/fr400/maveh.cgs b/sim/testsuite/frv/fr400/maveh.cgs new file mode 100644 index 0000000..445e121 --- /dev/null +++ b/sim/testsuite/frv/fr400/maveh.cgs @@ -0,0 +1,319 @@ +# frv testcase for maveh $FRi,$FRj,$FRj on fr400 machines +# mach: all + + .include "../testutils.inc" + + start + + .global maveh +maveh: + ; Test Rounding toward positive infinity via RDAV + or_spr_immed 0x20000000,msr0 + and_spr_immed 0xefffffff,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0002,0x0001,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0xffff,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef57,0xdf78,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf78,0xef57,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a3,0x33c5,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x091a,0x2b3c,fr12 + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x4000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + ; Test Rounding toward nearest via RD + or_spr_immed 0x10000000,msr0 + and_spr_immed 0x3fffffff,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0002,0x0001,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xffff,0xfffe,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef56,0xdf77,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf77,0xef56,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a3,0x33c5,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x091a,0x2b3c,fr12 + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x4000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xbfff,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xbfff,0xbfff,fr12 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + ; Test Rounding toward zero via RD + or_spr_immed 0x50000000,msr0 + and_spr_immed 0x7fffffff,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0000,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0xffff,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef57,0xdf78,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf78,0xef57,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a2,0x33c4,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0919,0x2b3b,fr12 + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x3fff,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + ; Test Rounding toward positive infinity via RD + or_spr_immed 0x90000000,msr0 + and_spr_immed 0xbfffffff,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0002,0x0001,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0xffff,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef57,0xdf78,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf78,0xef57,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a3,0x33c5,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x091a,0x2b3c,fr12 + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x4000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + ; Test Rounding toward negative infinity via RD + or_spr_immed 0xd0000000,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0000,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xffff,0xfffe,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef56,0xdf77,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf77,0xef56,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a2,0x33c4,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0919,0x2b3b,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x3fff,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xbfff,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xbfff,0xbfff,fr12 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + pass diff --git a/sim/testsuite/frv/fr400/mclracc.cgs b/sim/testsuite/frv/fr400/mclracc.cgs new file mode 100644 index 0000000..0297544 --- /dev/null +++ b/sim/testsuite/frv/fr400/mclracc.cgs @@ -0,0 +1,79 @@ +# frv testcase for mclracc $ACC40k,$A +# mach: all + + .include "../testutils.inc" + + start + + .global mclracc +mclracc: + set_accg_immed 0xff,accg0 + set_acc_immed -1,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed -1,acc1 + set_accg_immed 0xff,accg2 + set_acc_immed -1,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed -1,acc3 + + mclracc acc8,0 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -1,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + + mclracc acc8,1 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -1,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + + mclracc acc2,0 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + + mclracc acc3,1 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + mclracc acc0,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + mclracc acc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + pass diff --git a/sim/testsuite/frv/fr400/mhdseth.cgs b/sim/testsuite/frv/fr400/mhdseth.cgs new file mode 100644 index 0000000..b99c996 --- /dev/null +++ b/sim/testsuite/frv/fr400/mhdseth.cgs @@ -0,0 +1,22 @@ +# frv testcase for mhdseth $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhdseth +mhdseth: + set_fr_immed 0,fr1 + mhdseth 0,fr1 + test_fr_iimmed 0,fr1 + mhdseth 1,fr1 + test_fr_iimmed 0x08000800,fr1 + mhdseth 0xf,fr1 + test_fr_iimmed 0x78007800,fr1 + mhdseth -16,fr1 + test_fr_iimmed 0x80008000,fr1 + mhdseth -1,fr1 + test_fr_iimmed 0xf800f800,fr1 + + pass diff --git a/sim/testsuite/frv/fr400/mhdsets.cgs b/sim/testsuite/frv/fr400/mhdsets.cgs new file mode 100644 index 0000000..c495cb7 --- /dev/null +++ b/sim/testsuite/frv/fr400/mhdsets.cgs @@ -0,0 +1,20 @@ +# frv testcase for mhdsets $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhdsets +mhdsets: + set_fr_immed 0,fr1 + mhdsets 0,fr1 + test_fr_iimmed 0,fr1 + mhdsets 1,fr1 + test_fr_iimmed 0x00010001,fr1 + mhdsets 0x7ff,fr1 + test_fr_iimmed 0x07ff07ff,fr1 + mhdsets -2048,fr1 + test_fr_iimmed 0xf800f800,fr1 + + pass diff --git a/sim/testsuite/frv/fr400/mhsethih.cgs b/sim/testsuite/frv/fr400/mhsethih.cgs new file mode 100644 index 0000000..fed9d23 --- /dev/null +++ b/sim/testsuite/frv/fr400/mhsethih.cgs @@ -0,0 +1,22 @@ +# frv testcase for mhsethih $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhsethih +mhsethih: + set_fr_immed 0,fr1 + mhsethih 0,fr1 + test_fr_iimmed 0,fr1 + mhsethih 1,fr1 + test_fr_iimmed 0x08000000,fr1 + mhsethih 0xf,fr1 + test_fr_iimmed 0x78000000,fr1 + mhsethih -16,fr1 + test_fr_iimmed 0x80000000,fr1 + mhsethih -1,fr1 + test_fr_iimmed 0xf8000000,fr1 + + pass diff --git a/sim/testsuite/frv/fr400/mhsethis.cgs b/sim/testsuite/frv/fr400/mhsethis.cgs new file mode 100644 index 0000000..ade9102 --- /dev/null +++ b/sim/testsuite/frv/fr400/mhsethis.cgs @@ -0,0 +1,25 @@ +# frv testcase for mhsethis $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhsethis +mhsethis: + set_fr_immed 0,fr1 + mhsethis 0,fr1 + test_fr_iimmed 0,fr1 + mhsethis 1,fr1 + test_fr_iimmed 0x00010000,fr1 + mhsethis 0x7ff,fr1 + test_fr_iimmed 0x07ff0000,fr1 + mhsethis -2048,fr1 + test_fr_iimmed 0xf8000000,fr1 + + ; Try parallel set of hi and lo at the same time + mhsethis.p 1,fr1 + mhsetlos 2,fr1 + test_fr_iimmed 0x00010002,fr1 + + pass diff --git a/sim/testsuite/frv/fr400/mhsetloh.cgs b/sim/testsuite/frv/fr400/mhsetloh.cgs new file mode 100644 index 0000000..1dedb83 --- /dev/null +++ b/sim/testsuite/frv/fr400/mhsetloh.cgs @@ -0,0 +1,27 @@ +# frv testcase for mhsetloh $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhsetloh +mhsetloh: + set_fr_immed 0,fr1 + mhsetloh 0,fr1 + test_fr_iimmed 0,fr1 + mhsetloh 1,fr1 + test_fr_iimmed 0x0000800,fr1 + mhsetloh 0xf,fr1 + test_fr_iimmed 0x00007800,fr1 + mhsetloh -16,fr1 + test_fr_iimmed 0x00008000,fr1 + mhsetloh -1,fr1 + test_fr_iimmed 0x0000f800,fr1 + + ; Try parallel write to both hi and lo + mhsetloh.p 1,fr1 + mhsethih 0xf,fr1 + test_fr_iimmed 0x78000800,fr1 + + pass diff --git a/sim/testsuite/frv/fr400/mhsetlos.cgs b/sim/testsuite/frv/fr400/mhsetlos.cgs new file mode 100644 index 0000000..8e8839a --- /dev/null +++ b/sim/testsuite/frv/fr400/mhsetlos.cgs @@ -0,0 +1,25 @@ +# frv testcase for mhsetlos $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhsetlos +mhsetlos: + set_fr_immed 0,fr1 + mhsetlos 0,fr1 + test_fr_iimmed 0,fr1 + mhsetlos 1,fr1 + test_fr_iimmed 0x00000001,fr1 + mhsetlos 0x7ff,fr1 + test_fr_iimmed 0x000007ff,fr1 + mhsetlos -2048,fr1 + test_fr_iimmed 0x0000f800,fr1 + + ; Try parallel set of hi and lo at the same time + mhsethis.p 1,fr1 + mhsetlos 2,fr1 + test_fr_iimmed 0x00010002,fr1 + + pass diff --git a/sim/testsuite/frv/fr400/movgs.cgs b/sim/testsuite/frv/fr400/movgs.cgs new file mode 100644 index 0000000..4e22aab --- /dev/null +++ b/sim/testsuite/frv/fr400/movgs.cgs @@ -0,0 +1,50 @@ +# frv testcase for movgs $GRj,iacc0[hl] +# mach: fr400 + + .include "../testutils.inc" + + start + + .global movgs +IACC0H: + set_gr_limmed 0xdead,0xbeef,gr8 + and_spr_immed 0,iacc0h + movgs gr8,iacc0h + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0h +SPR280: + ; try alternate names for iacc0h + and_spr_immed 0,280 + movgs gr8,spr[280] ; iacc0h is spr number 280 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[280] + +IACC0L: + set_gr_limmed 0xdead,0xbeef,gr8 + and_spr_immed 0,iacc0l + movgs gr8,iacc0l + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0l +SPR281: + ; try alternate names for iacc0l + and_spr_immed 0,281 + movgs gr8,spr[281] ; iacc0l is spr number 281 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[281] + +IACC0L_SPR281: + ; try crossing between iacc0l and spr[281] + and_spr_immed 0,281 + and_spr_immed 0,iacc0l + movgs gr8,spr[281] ; iacc0l is spr number 281 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0l + +SPR280_IACC0H: + and_spr_immed 0,280 + and_spr_immed 0,iacc0h + movgs gr8,iacc0h ; iacc0h is spr number 280 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[280] + + pass diff --git a/sim/testsuite/frv/fr400/movsg.cgs b/sim/testsuite/frv/fr400/movsg.cgs new file mode 100644 index 0000000..3f9df25 --- /dev/null +++ b/sim/testsuite/frv/fr400/movsg.cgs @@ -0,0 +1,65 @@ +# frv testcase for movsg iacc0[hl],$GRj +# mach: fr400 + + .include "../testutils.inc" + + start + + .global movsg +Iacc0h: + set_spr_limmed 0xdead,0xbeef,iacc0h + set_gr_limmed 0,0,gr8 + movsg iacc0h,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0h +Iacc0l: + set_spr_limmed 0xdead,0xbeef,iacc0l + set_gr_limmed 0,0,gr8 + movsg iacc0l,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0l + +Spr280: + set_spr_limmed 0xdead,0xbeef,spr[280] + set_gr_limmed 0,0,gr8 + movsg spr[280],gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[280] +Spr281: + set_spr_limmed 0xdead,0xbeef,spr[281] + set_gr_limmed 0,0,gr8 + movsg spr[281],gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[281] + +Iacc0h_spr280: + set_spr_limmed 0xdead,0xbeef,spr[280] + set_spr_limmed 0xdead,0xbeef,iacc0h + set_gr_limmed 0,0,gr8 + movsg iacc0h,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[280] +Iacc0l_spr281: + set_spr_limmed 0xdead,0xbeef,spr[281] + set_spr_limmed 0xdead,0xbeef,iacc0l + set_gr_limmed 0,0,gr8 + movsg iacc0l,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[281] + +Spr280_iacc0h: + set_spr_limmed 0xdead,0xbeef,spr[280] + set_spr_limmed 0xdead,0xbeef,iacc0h + set_gr_limmed 0,0,gr8 + movsg spr[280],gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0h +Spr281_iacc0l: + set_spr_limmed 0xdead,0xbeef,spr[281] + set_spr_limmed 0xdead,0xbeef,iacc0l + set_gr_limmed 0,0,gr8 + movsg spr[281],gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0l + + pass diff --git a/sim/testsuite/frv/fr400/msubaccs.cgs b/sim/testsuite/frv/fr400/msubaccs.cgs new file mode 100644 index 0000000..f0aba1d --- /dev/null +++ b/sim/testsuite/frv/fr400/msubaccs.cgs @@ -0,0 +1,131 @@ +# frv testcase for msubaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global msubaccs +msubaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg3 + test_acc_limmed 0x4111,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffffffe,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000002,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0x00000000,acc3 + msubaccs.p acc0,acc1 + msubaccs acc2,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x8,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/frv/fr400/scutss.cgs b/sim/testsuite/frv/fr400/scutss.cgs new file mode 100644 index 0000000..f958de6 --- /dev/null +++ b/sim/testsuite/frv/fr400/scutss.cgs @@ -0,0 +1,664 @@ +# frv testcase for scutss $FRj,$FRk +# mach: fr405 fr450 + + .include "../testutils.inc" + + start + + .global scutss +scutss: + set_spr_immed 0xffffffe7,iacc0h + set_spr_immed 0x89abcdef,iacc0l + + set_gr_immed 0,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffe8,gr11 + + set_gr_immed 1,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffcf,gr11 + + set_gr_immed 2,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xff9e,gr11 + + set_gr_immed 3,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xff3c,gr11 + + set_gr_immed 4,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfe79,gr11 + + set_gr_immed 5,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfcf1,gr11 + + set_gr_immed 6,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xf9e2,gr11 + + set_gr_immed 7,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xf3c5,gr11 + + set_gr_immed 8,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xe78a,gr11 + + set_gr_immed 9,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xcf13,gr11 + + set_gr_immed 10,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0x9e27,gr11 + + set_gr_immed 11,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0x3c4d,gr11 + + set_gr_immed 12,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfffe,0x789b,gr11 + + set_gr_immed 13,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfffc,0xf135,gr11 + + set_gr_immed 14,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfff9,0xe26b,gr11 + + set_gr_immed 15,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfff3,0xc4d6,gr11 + + set_gr_immed 16,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffe7,0x89ac,gr11 + + set_gr_immed 17,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffcf,0x1358,gr11 + + set_gr_immed 18,gr10 + scutss gr10,gr11 + test_gr_limmed 0xff9e,0x26af,gr11 + + set_gr_immed 19,gr10 + scutss gr10,gr11 + test_gr_limmed 0xff3c,0x4d5e,gr11 + + set_gr_immed 20,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfe78,0x9abd,gr11 + + set_gr_immed 21,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfcf1,0x357a,gr11 + + set_gr_immed 22,gr10 + scutss gr10,gr11 + test_gr_limmed 0xf9e2,0x6af3,gr11 + + set_gr_immed 23,gr10 + scutss gr10,gr11 + test_gr_limmed 0xf3c4,0xd5e7,gr11 + + set_gr_immed 24,gr10 + scutss gr10,gr11 + test_gr_limmed 0xe789,0xabce,gr11 + + set_gr_immed 25,gr10 + scutss gr10,gr11 + test_gr_limmed 0xcf13,0x579c,gr11 + + set_gr_immed 26,gr10 + scutss gr10,gr11 + test_gr_limmed 0x9e26,0xaf38,gr11 + + set_gr_immed 27,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 28,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 29,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 30,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 31,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 32,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 33,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 34,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 35,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 36,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 37,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 38,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 39,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 40,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 41,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 42,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 43,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 44,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 45,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 46,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 47,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 48,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 49,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 50,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 51,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 52,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 53,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 54,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 55,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 56,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 57,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 58,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 59,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 60,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 61,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 62,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 63,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 64,gr10 ; same as -64 + scutss gr10,gr11 + test_gr_immed 0,gr11 + + set_gr_immed 128,gr10 ; same as 0 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffe8,gr11 + + .global scutss2 +scutss2: + set_spr_immed 0xe789abcd,iacc0h + set_spr_immed 0xefa5a5a5,iacc0l + + set_gr_limmed 0xffff,0xffff,gr10 ; -1 + scutss gr10,gr11 + test_gr_limmed 0xf3c4,0xd5e7,gr11 + + set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter) + scutss gr10,gr11 + test_gr_limmed 0xf9e2,0x6af3,gr11 + + set_gr_immed -3,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfcf1,0x357a,gr11 + + set_gr_immed -4,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfe78,0x9abd,gr11 + + set_gr_immed -5,gr10 + scutss gr10,gr11 + test_gr_limmed 0xff3c,0x4d5e,gr11 + + set_gr_immed -6,gr10 + scutss gr10,gr11 + test_gr_limmed 0xff9e,0x26af,gr11 + + set_gr_immed -7,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffcf,0x1358,gr11 + + set_gr_immed -8,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffe7,0x89ac,gr11 + + set_gr_immed -9,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfff3,0xc4d6,gr11 + + set_gr_immed -10,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfff9,0xe26b,gr11 + + set_gr_immed -11,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfffc,0xf135,gr11 + + set_gr_immed -12,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfffe,0x789b,gr11 + + set_gr_immed -13,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0x3c4d,gr11 + + set_gr_immed -14,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0x9e27,gr11 + + set_gr_immed -15,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xcf13,gr11 + + set_gr_immed -16,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xe78a,gr11 + + set_gr_immed -17,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xf3c5,gr11 + + set_gr_immed -18,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xf9e2,gr11 + + set_gr_immed -19,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfcf1,gr11 + + set_gr_immed -20,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfe79,gr11 + + set_gr_immed -21,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xff3c,gr11 + + set_gr_immed -22,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xff9e,gr11 + + set_gr_immed -23,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffcf,gr11 + + set_gr_immed -24,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffe8,gr11 + + set_gr_immed -25,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfff4,gr11 + + set_gr_immed -26,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfffa,gr11 + + set_gr_immed -27,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfffd,gr11 + + set_gr_immed -28,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfffe,gr11 + + set_gr_immed -29,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffff,gr11 + + set_gr_immed -30,gr10 + scutss gr10,gr11 + test_gr_immed 0,gr11 + + set_gr_immed -31,gr10 + scutss gr10,gr11 + test_gr_immed 0,gr11 + + set_gr_immed -32,gr10 + scutss gr10,gr11 + test_gr_immed 0,gr11 + + set_gr_limmed 0,64,gr10 ; same as -32 + scutss gr10,gr11 + test_gr_immed 0,gr11 + + set_spr_immed 0x6789abcd,iacc0h + set_spr_immed 0xefa5a5a5,iacc0l + + set_gr_limmed 0xffff,0xffff,gr10 + scutss gr10,gr11 + test_gr_limmed 0x33c4,0xd5e7,gr11 + + set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter) + scutss gr10,gr11 + test_gr_limmed 0x19e2,0x6af3,gr11 + + set_gr_immed -3,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0cf1,0x357a,gr11 + + set_gr_immed -4,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0678,0x9abd,gr11 + + set_gr_immed -5,gr10 + scutss gr10,gr11 + test_gr_limmed 0x033c,0x4d5e,gr11 + + set_gr_immed -6,gr10 + scutss gr10,gr11 + test_gr_limmed 0x019e,0x26af,gr11 + + set_gr_immed -7,gr10 + scutss gr10,gr11 + test_gr_limmed 0x00cf,0x1358,gr11 + + set_gr_immed -8,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0067,0x89ac,gr11 + + set_gr_immed -9,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0033,0xc4d6,gr11 + + set_gr_immed -10,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0019,0xe26b,gr11 + + set_gr_immed -11,gr10 + scutss gr10,gr11 + test_gr_limmed 0x000c,0xf135,gr11 + + set_gr_immed -12,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0006,0x789b,gr11 + + set_gr_immed -13,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0003,0x3c4d,gr11 + + set_gr_immed -14,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0001,0x9e27,gr11 + + set_gr_immed -15,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0xcf13,gr11 + + set_gr_immed -16,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x678a,gr11 + + set_gr_immed -17,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x33c5,gr11 + + set_gr_immed -18,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x19e2,gr11 + + set_gr_immed -19,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0cf1,gr11 + + set_gr_immed -20,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0679,gr11 + + set_gr_immed -21,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x033c,gr11 + + set_gr_immed -22,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x019e,gr11 + + set_gr_immed -23,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x00cf,gr11 + + set_gr_immed -24,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0068,gr11 + + set_gr_immed -25,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0034,gr11 + + set_gr_immed -26,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x001a,gr11 + + set_gr_immed -27,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x000d,gr11 + + set_gr_immed -28,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0006,gr11 + + set_gr_immed -29,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0003,gr11 + + set_gr_immed -30,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0002,gr11 + + set_gr_immed -31,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0001,gr11 + + set_gr_immed -32,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0000,gr11 + + set_gr_immed 64,gr10 ; same as -32 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0000,gr11 + + ; Examples from the customer (modified for iacc0) + set_spr_immed 0xffffffff,iacc0h + set_spr_immed 0xffe00000,iacc0l + + set_gr_limmed 0,16,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffe0,gr11 + + set_gr_limmed 0,17,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffc0,gr11 + + set_gr_limmed 0,18,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xff80,gr11 + + set_spr_immed 0,iacc0h + set_spr_immed 0x003fffff,iacc0l + + set_gr_limmed 0,40,gr10 + scutss gr10,gr11 + test_gr_limmed 0x3fff,0xff00,gr11 + + set_gr_limmed 0,41,gr10 + scutss gr10,gr11 + test_gr_limmed 0x7fff,0xfe00,gr11 + + set_spr_immed 0x7f,iacc0h + set_spr_immed 0xffe00000,iacc0l + + set_gr_limmed 0,40,gr10 + scutss gr10,gr11 + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated + + set_gr_limmed 0,41,gr10 + scutss gr10,gr11 + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated + + set_gr_limmed 0,42,gr10 + scutss gr10,gr11 + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated + + set_spr_immed 0x08,iacc0h + set_spr_immed 0x003fffff,iacc0l + + set_gr_limmed 0,40,gr10 + scutss gr10,gr11 + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated + + set_gr_limmed 0,41,gr10 + scutss gr10,gr11 + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated + + set_spr_immed 0xffffffff,iacc0h + set_spr_immed 0xefe00000,iacc0l + + set_gr_limmed 0,40,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 ; saturated + + set_gr_limmed 0,41,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 ; saturated + + set_gr_limmed 0,42,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 ; saturated + + set_spr_immed 0x80000000,iacc0h + set_spr_immed 0x003fffff,iacc0l + + set_gr_limmed 0,16,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 ; saturated + + set_gr_limmed 0,17,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 ; saturated + + set_spr_immed 0xaf5a5a5a,iacc0h + set_spr_immed 0x5a5a5a5a,iacc0l + + set_gr_limmed 0xffff,0xfffc,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfaf5,0xa5a6,gr11 + + set_spr_immed 0x2f5a5a5a,iacc0h + set_spr_immed 0x5a5a5a5a,iacc0l + + set_gr_limmed 0xffff,0xfff9,gr10 + scutss gr10,gr11 + test_gr_limmed 0x005e,0xb4b5,gr11 + +# From the manual + .global scutss3 +scutss3: + set_spr_immed 0xfffffedc,iacc0h + set_spr_immed 0xba987654,iacc0l + + set_gr_immed 16,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfedc,0xba98,gr11 + + set_gr_immed 12,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffed,0xcbaa,gr11 + + set_gr_immed -4,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffee,gr11 + + set_gr_immed 24,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + pass diff --git a/sim/testsuite/frv/fr400/sdiv.cgs b/sim/testsuite/frv/fr400/sdiv.cgs new file mode 100644 index 0000000..b9c03cf --- /dev/null +++ b/sim/testsuite/frv/fr400/sdiv.cgs @@ -0,0 +1,71 @@ +# frv testcase for sdiv $GRi,$GRj,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global sdiv +sdiv: + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + sdiv gr1,gr3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + sdiv gr1,gr3,gr2 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + sdiv gr1,gr3,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdiv gr1,gr3,gr2 ; overflow + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2; gr2 updated + + ; divide by zero + set_spr_addr ok2,lr + set_gr_immed 0xdeadbeef,gr2 +e2: sdiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 2,gr15 ; handler called + test_gr_immed 0xdeadbeef,gr2 ; gr2 not updated. + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/fr400/sdivi.cgs b/sim/testsuite/frv/fr400/sdivi.cgs new file mode 100644 index 0000000..fda573e --- /dev/null +++ b/sim/testsuite/frv/fr400/sdivi.cgs @@ -0,0 +1,70 @@ +# frv testcase for sdivi $GRi,$s12,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global sdivi +sdivi: + ; simple division 12 / 3 + set_gr_immed 12,gr1 + sdivi gr1,3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,0x7ff,gr2 + test_gr_limmed 0xffff,0xdb93,gr2 + + ; Random negative example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,-2048,gr2 + test_gr_immed 0x2468,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + sdivi gr1,-1,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdivi gr1,-1,gr2 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; divide by zero + set_spr_addr ok2,lr +e2: sdivi gr1,0,gr2 ; divide by zero + test_gr_immed 2,gr15 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/fr400/slass.cgs b/sim/testsuite/frv/fr400/slass.cgs new file mode 100644 index 0000000..3e8bcac --- /dev/null +++ b/sim/testsuite/frv/fr400/slass.cgs @@ -0,0 +1,104 @@ +# frv testcase for slass $GRi,$GRj,$GRk +# mach: fr405 fr450 + + .include "../testutils.inc" + + start + + .global sll +slass0: + set_gr_immed 0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + slass gr8,gr7,gr6 + test_gr_immed 2,gr8 + test_gr_immed 0,gr7 + test_gr_immed 2,gr6 +slass1: + set_gr_immed 1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + slass gr8,gr7,gr6 + test_gr_immed 2,gr8 + test_gr_immed 1,gr7 + test_gr_immed 4,gr6 + +slass2: + set_gr_immed 31,gr7 ; Shift 1 by 31 + set_gr_immed 1,gr8 + slass gr8,gr7,gr6 + test_gr_immed 1,gr8 + test_gr_immed 31,gr7 + test_gr_limmed 0x7fff,0xffff,gr6 + +slass3: + set_gr_immed 31,gr7 ; Shift -1 by 31 + set_gr_immed -1,gr8 + slass gr8,gr7,gr6 + test_gr_immed -1,gr8 + test_gr_immed 31,gr7 + test_gr_limmed 0x8000,0x0000,gr6 + +slass4: + set_gr_immed 14,gr7 ; Shift 0xffff0000 by 14 + set_gr_limmed 0xffff,0x0000,gr8 + slass gr8,gr7,gr6 + test_gr_limmed 0xffff,0x0000,gr8 + test_gr_immed 14,gr7 + test_gr_limmed 0xc000,0x0000,gr6 + +slass5: + set_gr_immed 15,gr7 ; Shift 0xffff0000 by 15 + set_gr_limmed 0xffff,0x0000,gr8 + slass gr8,gr7,gr6 + test_gr_limmed 0xffff,0x0000,gr8 + test_gr_immed 15,gr7 + test_gr_limmed 0x8000,0x0000,gr6 + +slass6: + set_gr_immed 20,gr7 ; Shift 0xffff0000 by 20 + set_gr_limmed 0xffff,0x0000,gr8 + slass gr8,gr7,gr6 + test_gr_limmed 0xffff,0x0000,gr8 + test_gr_immed 20,gr7 + test_gr_limmed 0x8000,0x0000,gr6 + +slass7: + set_gr_immed 14,gr7 ; Shift 0x0000ffff by 14 + set_gr_limmed 0x0000,0xffff,gr8 + slass gr8,gr7,gr6 + test_gr_limmed 0x0000,0xffff,gr8 + test_gr_immed 14,gr7 + test_gr_limmed 0x3fff,0xc000,gr6 + +slass8: + set_gr_immed 15,gr7 ; Shift 0x0000ffff by 15 + set_gr_limmed 0x0000,0xffff,gr8 + slass gr8,gr7,gr6 + test_gr_limmed 0x0000,0xffff,gr8 + test_gr_immed 15,gr7 + test_gr_limmed 0x7fff,0x8000,gr6 + +slass9: + set_gr_immed 20,gr7 ; Shift 0x0000ffff by 20 + set_gr_limmed 0x0000,0xffff,gr8 + slass gr8,gr7,gr6 + test_gr_limmed 0x0000,0xffff,gr8 + test_gr_immed 20,gr7 + test_gr_limmed 0x7fff,0xffff,gr6 + +slass10: + set_gr_immed 30,gr7 ; Shift 1 by 30 + set_gr_immed 1,gr8 + slass gr8,gr7,gr6 + test_gr_immed 1,gr8 + test_gr_immed 30,gr7 + test_gr_limmed 0x4000,0x0000,gr6 + +slass11: + set_gr_immed 30,gr7 ; Shift -1 by 30 + set_gr_immed -1,gr8 + slass gr8,gr7,gr6 + test_gr_immed -1,gr8 + test_gr_immed 30,gr7 + test_gr_limmed 0xc000,0000,gr6 + + pass diff --git a/sim/testsuite/frv/fr400/smass.cgs b/sim/testsuite/frv/fr400/smass.cgs new file mode 100644 index 0000000..4594ecd --- /dev/null +++ b/sim/testsuite/frv/fr400/smass.cgs @@ -0,0 +1,359 @@ +# frv testcase for smass $GRi,$GRj +# mach: fr405 fr450 + + .include "../testutils.inc" + + start + + .global smass +smass1: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 3,gr7 + test_gr_immed 2,gr8 + test_spr_immed 7,iacc0l ; result 3*2+1 + test_spr_immed 0,iacc0h +smass2: + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 1,gr7 + test_gr_immed 2,gr8 + test_spr_immed 3,iacc0l ; result 1*2+1 + test_spr_immed 0,iacc0h +smass3: + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 1,gr8 + test_gr_immed 2,gr7 + test_spr_immed 3,iacc0l ; result 2*1+1 + test_spr_immed 0,iacc0h +smass4: + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 2,gr8 + test_gr_immed 0,gr7 + test_spr_immed 1,iacc0l ; result 0*2+1 + test_spr_immed 0,iacc0h +smass5: + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr7 + test_spr_immed 1,iacc0l ; result 2*0+1 + test_spr_immed 0,iacc0h +smass6: + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 2,gr8 + test_gr_limmed 0x3fff,0xffff,gr7 + test_spr_limmed 0x7fff,0xffff,iacc0l ; 3fffffff*2+1 + test_spr_immed 0,iacc0h +smass7: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*2+1 + test_spr_immed 0,iacc0h +smass8: + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 4,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_immed 1,iacc0l ; 40000000*4+1 + test_spr_immed 1,iacc0h +smass9: + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_immed 0x00000002,iacc0l ; 7fffffff*7fffffff+1 + test_spr_limmed 0x3fff,0xffff,iacc0h +smass10: + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 2,gr8 + test_gr_immed -3,gr7 + test_spr_immed -5,iacc0l ; -3*2+1 + test_spr_immed -1,iacc0h +smass11: + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 3,gr7 + test_spr_immed -5,iacc0l ; 3*-2+1 + test_spr_immed -1,iacc0h +smass12: + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 1,gr7 + test_spr_immed -1,iacc0l ; 1*-2+1 + test_spr_immed -1,iacc0h +smass13: + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 1,gr8 + test_gr_immed -2,gr7 + test_spr_immed -1,iacc0l ; -2*1+1 + test_spr_immed -1,iacc0h +smass14: + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 0,gr7 + test_spr_immed 1,iacc0l ; 0*-2+1 + test_spr_immed 0,iacc0h +smass15: + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed -2,gr7 + test_spr_immed 1,iacc0l ; -2*0+1 + test_spr_immed 0,iacc0h +smass16: + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x2000,0x0001,gr7 + test_spr_limmed 0xbfff,0xffff,iacc0l ; 20000001*-2+1 + test_spr_limmed 0xffff,0xffff,iacc0h +smass17: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*-2+1 + test_spr_limmed 0xffff,0xffff,iacc0h +smass18: + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x4000,0x0001,gr7 + test_spr_limmed 0x7fff,0xffff,iacc0l ; 40000001*-2+1 + test_spr_limmed 0xffff,0xffff,iacc0h +smass19: + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -4,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x0000,0x0001,iacc0l ; 40000000*-4+1 + test_spr_limmed 0xffff,0xffff,iacc0h +smass20: + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x8000,0x0001,iacc0l ; 7fffffff*80000000+1 + test_spr_limmed 0xc000,0x0000,iacc0h +smass21: + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -3,gr7 + test_spr_immed 7,iacc0l ; -3*-2+1 + test_spr_immed 0,iacc0h +smass22: + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -1,gr7 + test_spr_immed 3,iacc0l ; -1*-2+1 + test_spr_immed 0,iacc0h +smass23: + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -1,gr8 + test_gr_immed -2,gr7 + test_spr_immed 3,iacc0l ; -2*-1+1 + test_spr_immed 0,iacc0h +smass24: + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0xc000,0x0001,gr7 + test_spr_limmed 0x7fff,0xffff,iacc0l ; c0000001*-2+1 + test_spr_immed 0,iacc0h +smass25: + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0xc000,0x0000,gr7 + test_spr_limmed 0x8000,0x0001,iacc0l ; c0000000*-2+1 + test_spr_immed 0,iacc0h +smass26: + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -4,gr8 + test_gr_limmed 0xc000,0x0000,gr7 + test_spr_immed 0x00000001,iacc0l ; c0000000*-4+1 + test_spr_immed 1,iacc0h +smass27: + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_limmed 0x8000,0x0001,gr7 + test_spr_immed 0x00000002,iacc0l ; 80000001*80000001+1 + test_spr_limmed 0x3fff,0xffff,iacc0h +smass28: + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr7 + test_spr_immed 0x00000001,iacc0l ; 80000000*80000000+1 + test_spr_limmed 0x4000,0x0000,iacc0h + +smass29: + set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos) + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_limmed 0xffff,0xfffe,iacc0l + set_spr_limmed 0x4000,0x0000,iacc0h + smass gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000fffffffe + +smass30: + set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos) + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_limmed 0xffff,0xffff,iacc0l + set_spr_limmed 0x4000,0x0000,iacc0h + smass gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000ffffffff + +smass31: + set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos) + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_limmed 0xffff,0xffff,iacc0l + set_spr_limmed 0x7fff,0xffff,iacc0h + smass gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x7fff,0xffff,iacc0h ; 7fffffffffffffff + +smass32: + set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg) + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_limmed 0x8000,0x0000,iacc0l + set_spr_limmed 0xbfff,0xffff,iacc0h + smass gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff80000000 + +smass33: + set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg) + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_limmed 0x7fff,0xffff,iacc0l + set_spr_limmed 0xbfff,0xffff,iacc0h + smass gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff + +smass34: + set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg) + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_limmed 0x0000,0x0000,iacc0l + set_spr_limmed 0x8000,0x0000,iacc0h + smass gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x8000,0x0000,iacc0h ; 8000000000000000 + + pass diff --git a/sim/testsuite/frv/fr400/smsss.cgs b/sim/testsuite/frv/fr400/smsss.cgs new file mode 100644 index 0000000..50876d8 --- /dev/null +++ b/sim/testsuite/frv/fr400/smsss.cgs @@ -0,0 +1,354 @@ +# frv testcase for smsss $GRi,$GRj +# mach: fr405 fr450 + + .include "../testutils.inc" + + start + + .global smsss +smsss1: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 7,iacc0l + smsss gr7,gr8 + test_gr_immed 3,gr7 + test_gr_immed 2,gr8 + test_spr_immed 1,iacc0l ; result 7-3*2 + test_spr_immed 0,iacc0h +smsss2: + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 3,iacc0l + smsss gr7,gr8 + test_gr_immed 1,gr7 + test_gr_immed 2,gr8 + test_spr_immed 1,iacc0l ; result 3-1*2 + test_spr_immed 0,iacc0h +smsss3: + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 3,iacc0l + smsss gr7,gr8 + test_gr_immed 1,gr8 + test_gr_immed 2,gr7 + test_spr_immed 1,iacc0l ; result 3-2*1 + test_spr_immed 0,iacc0h +smsss4: + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed 2,gr8 + test_gr_immed 0,gr7 + test_spr_immed 1,iacc0l ; result 1-0*2 + test_spr_immed 0,iacc0h +smsss5: + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr7 + test_spr_immed 1,iacc0l ; result 1-2*0 + test_spr_immed 0,iacc0h +smsss6: + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_spr_immed -1,iacc0h + set_spr_immed -1,iacc0l + smsss gr7,gr8 + test_gr_immed 2,gr8 + test_gr_limmed 0x3fff,0xffff,gr7 + test_spr_limmed 0x8000,0x0001,iacc0l ; -1-3fffffff*2 + test_spr_immed -1,iacc0h +smsss7: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_spr_immed -1,iacc0h + set_spr_limmed 0x8000,0x0001,iacc0l + smsss gr7,gr8 + test_gr_immed 2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_immed 1,iacc0l ; ffffffff80000001-40000000*2 + test_spr_immed -1,iacc0h +smsss8: + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_spr_immed -1,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed 4,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_immed 1,iacc0l ; ffffffff00000001-40000000*4 + test_spr_immed -2,iacc0h +smsss9: + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_limmed 0x7fff,0xffff,iacc0h + set_spr_immed -1,iacc0l + smsss gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xfffe,iacc0l ; 7fffffffffffffff-7fffffff*7fffffff + test_spr_limmed 0x4000,0x0000,iacc0h +smsss10: + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_spr_immed -1,iacc0h + set_spr_immed -5,iacc0l + smsss gr7,gr8 + test_gr_immed 2,gr8 + test_gr_immed -3,gr7 + test_spr_immed 1,iacc0l ; -5-(-3*2) + test_spr_immed 0,iacc0h +smsss11: + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_spr_immed -1,iacc0h + set_spr_immed -5,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 3,gr7 + test_spr_immed 1,iacc0l ; -5-(3*-2) + test_spr_immed 0,iacc0h +smsss12: + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_spr_immed -1,iacc0h + set_spr_immed -1,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 1,gr7 + test_spr_immed 1,iacc0l ; -1-(1*-2) + test_spr_immed 0,iacc0h +smsss13: + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_spr_immed -1,iacc0h + set_spr_immed -1,iacc0l + smsss gr7,gr8 + test_gr_immed 1,gr8 + test_gr_immed -2,gr7 + test_spr_immed 1,iacc0l ; -1-(-2*1) + test_spr_immed 0,iacc0h +smsss14: + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 0,gr7 + test_spr_immed 1,iacc0l ; 1-(0*-2) + test_spr_immed 0,iacc0h +smsss15: + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed -2,gr7 + test_spr_immed 1,iacc0l ; 1-(-2*0) + test_spr_immed 0,iacc0h +smsss16: + set_gr_limmed 0x2000,0x0000,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_limmed 0x3fff,0xffff,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x2000,0x0000,gr7 + test_spr_limmed 0x7fff,0xffff,iacc0l + test_spr_immed 0,iacc0h ; 3fffffff-20000001*-2 +smsss17: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x8000,0x0001,iacc0l ; 1-40000000*-2 + test_spr_immed 0,iacc0h +smsss18: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_spr_immed -1,iacc0h + set_spr_immed -1,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x7fff,0xffff,iacc0l + test_spr_immed 0,iacc0h ; -1-40000000*-2 +smsss19: + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed -4,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_immed 1,iacc0l ; 200000001-(40000000*-4) + test_spr_immed 1,iacc0h +smsss20: + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_limmed 0xbfff,0xffff,iacc0h + set_spr_limmed 0x0000,0x0001,iacc0l + smsss gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_immed 0,iacc0l ; bfffffff00000001-(7fffffff*7fffffff) + test_spr_limmed 0x8000,0x0000,iacc0h +smsss21: + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 7,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -3,gr7 + test_spr_immed 1,iacc0l ; 7-(-3*-2) + test_spr_immed 0,iacc0h +smsss22: + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 3,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -1,gr7 + test_spr_immed 1,iacc0l ; 3-(-1*-2) + test_spr_immed 0,iacc0h +smsss23: + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 3,iacc0l + smsss gr7,gr8 + test_gr_immed -1,gr8 + test_gr_immed -2,gr7 + test_spr_immed 1,iacc0l ; 3-(-2*-1) + test_spr_immed 0,iacc0h +smsss24: + set_gr_immed -32768,gr7 ; 31 bit result + set_gr_immed -32768,gr8 + set_spr_immed 0,iacc0h + set_spr_limmed 0xbfff,0xffff,iacc0l + smsss gr7,gr8 + test_gr_immed -32768,gr8 + test_gr_immed -32768,gr7 + test_spr_limmed 0x7fff,0xffff,iacc0l ; 7ffffffb-(-2*-2) + test_spr_immed 0,iacc0h +smsss25: + set_gr_immed 0xffff,gr7 ; 32 bit result + set_gr_immed 0xffff,gr8 + set_spr_immed 1,iacc0h + set_spr_limmed 0xfffe,0x0000,iacc0l + smsss gr7,gr8 + test_gr_immed 0xffff,gr8 + test_gr_immed 0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 1fffe0000-ffff*ffff + test_spr_immed 0,iacc0h +smsss26: + set_gr_limmed 0x0001,0x0000,gr7 ; 33 bit result + set_gr_limmed 0x0001,0x0000,gr8 + set_spr_immed 2,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_limmed 0x0001,0x0000,gr8 + test_gr_limmed 0x0001,0x0000,gr7 + test_spr_immed 1,iacc0l ; 0x200000001-0x10000*0x10000 + test_spr_immed 1,iacc0h +smsss27: + set_gr_immed -2,gr7 ; almost max positive result + set_gr_immed -2,gr8 + set_spr_limmed 0x7fff,0xffff,iacc0h + set_spr_limmed 0xffff,0xffff,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -2,gr7 + test_spr_limmed 0xffff,0xfffb,iacc0l ; maxpos - (-2*-2) + test_spr_limmed 0x7fff,0xffff,iacc0h +smsss28: + set_gr_immed 0,gr7 ; max positive result + set_gr_immed 0,gr8 + set_spr_limmed 0x7fff,0xffff,iacc0h + set_spr_limmed 0xffff,0xffff,iacc0l + smsss gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; maxpos-(0*0) + test_spr_limmed 0x7fff,0xffff,iacc0h +smsss29: + set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos) + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_limmed 0x4000,0x0000,iacc0h + set_spr_limmed 0x7fff,0xffff,iacc0l + smsss gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 400000007fffffff - + test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff +smsss30: + set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos) + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_limmed 0x4000,0x0000,iacc0h + set_spr_limmed 0x8000,0x0000,iacc0l + smsss gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 4000000080000000 - + test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff + +smsss31: + set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos) + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_limmed 0xffff,0xffff,iacc0l + set_spr_limmed 0x7fff,0xffff,iacc0h + smsss gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffffffffffff - + test_spr_limmed 0x7fff,0xffff,iacc0h ; 80000000*80000000 +smsss32: + set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg) + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_immed 1,iacc0l + set_spr_limmed 0xbfff,0xffff,iacc0h + smsss gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l ; bfffffff00000001 - + test_spr_limmed 0x8000,0x0000,iacc0h ; 0x7fffffff*0x7fffffff +smsss33: + set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg) + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_immed 0,iacc0l + set_spr_limmed 0xbfff,0xffff,iacc0h + smsss gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff +smsss34: + set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg) + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_limmed 0x0000,0x0000,iacc0l + set_spr_limmed 0x8000,0x0000,iacc0h + smsss gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l ; 8000000000000000- + test_spr_limmed 0x8000,0x0000,iacc0h ; 7fffffff*7fffffff+ + + pass diff --git a/sim/testsuite/frv/fr400/smu.cgs b/sim/testsuite/frv/fr400/smu.cgs new file mode 100644 index 0000000..eae788e --- /dev/null +++ b/sim/testsuite/frv/fr400/smu.cgs @@ -0,0 +1,237 @@ +# frv testcase for smu $GRi,$GRj +# mach: fr405 fr450 + + .include "../testutils.inc" + + start + + .global smu +smu1: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + smu gr7,gr8 + test_gr_immed 3,gr7 + test_gr_immed 2,gr8 + test_spr_immed 6,iacc0l + test_spr_immed 0,iacc0h +smu2: + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + smu gr7,gr8 + test_gr_immed 1,gr7 + test_gr_immed 2,gr8 + test_spr_immed 2,iacc0l + test_spr_immed 0,iacc0h +smu3: + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + smu gr7,gr8 + test_gr_immed 1,gr8 + test_gr_immed 2,gr7 + test_spr_immed 2,iacc0l + test_spr_immed 0,iacc0h +smu4: + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + smu gr7,gr8 + test_gr_immed 2,gr8 + test_gr_immed 0,gr7 + test_spr_immed 0,iacc0l + test_spr_immed 0,iacc0h +smu5: + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + smu gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr7 + test_spr_immed 0,iacc0l + test_spr_immed 0,iacc0h +smu6: + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + smu gr7,gr8 + test_gr_immed 2,gr8 + test_gr_limmed 0x3fff,0xffff,gr7 + test_spr_limmed 0x7fff,0xfffe,iacc0l + test_spr_immed 0,iacc0h +smu7: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + smu gr7,gr8 + test_gr_immed 2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x8000,0x0000,iacc0l + test_spr_immed 0,iacc0h +smu8: + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + smu gr7,gr8 + test_gr_immed 4,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_immed 0,iacc0l + test_spr_immed 1,iacc0h +smu9: + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + smu gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_immed 0x00000001,iacc0l + test_spr_limmed 0x3fff,0xffff,iacc0h +smu10: + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + smu gr7,gr8 + test_gr_immed 2,gr8 + test_gr_immed -3,gr7 + test_spr_immed -6,iacc0l + test_spr_immed -1,iacc0h +smu11: + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 3,gr7 + test_spr_immed -6,iacc0l + test_spr_immed -1,iacc0h +smu12: + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 1,gr7 + test_spr_immed -2,iacc0l + test_spr_immed -1,iacc0h +smu13: + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + smu gr7,gr8 + test_gr_immed 1,gr8 + test_gr_immed -2,gr7 + test_spr_immed -2,iacc0l + test_spr_immed -1,iacc0h +smu14: + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 0,gr7 + test_spr_immed 0,iacc0l + test_spr_immed 0,iacc0h +smu15: + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + smu gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed -2,gr7 + test_spr_immed 0,iacc0l + test_spr_immed 0,iacc0h +smu16: + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x2000,0x0001,gr7 + test_spr_limmed 0xbfff,0xfffe,iacc0l + test_spr_limmed 0xffff,0xffff,iacc0h +smu17: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x8000,0x0000,iacc0l + test_spr_limmed 0xffff,0xffff,iacc0h +smu18: + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x4000,0x0001,gr7 + test_spr_limmed 0x7fff,0xfffe,iacc0l + test_spr_limmed 0xffff,0xffff,iacc0h +smu19: + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + smu gr7,gr8 + test_gr_immed -4,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l + test_spr_limmed 0xffff,0xffff,iacc0h +smu20: + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + smu gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x8000,0x0000,iacc0l + test_spr_limmed 0xc000,0x0000,iacc0h +smu21: + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -3,gr7 + test_spr_immed 6,iacc0l + test_spr_immed 0,iacc0h +smu22: + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -1,gr7 + test_spr_immed 2,iacc0l + test_spr_immed 0,iacc0h +smu23: + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + smu gr7,gr8 + test_gr_immed -1,gr8 + test_gr_immed -2,gr7 + test_spr_immed 2,iacc0l + test_spr_immed 0,iacc0h +smu24: + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0xc000,0x0001,gr7 + test_spr_limmed 0x7fff,0xfffe,iacc0l + test_spr_immed 0,iacc0h +smu25: + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0xc000,0x0000,gr7 + test_spr_limmed 0x8000,0x0000,iacc0l + test_spr_immed 0,iacc0h +smu26: + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + smu gr7,gr8 + test_gr_immed -4,gr8 + test_gr_limmed 0xc000,0x0000,gr7 + test_spr_immed 0x00000000,iacc0l + test_spr_immed 1,iacc0h +smu27: + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + smu gr7,gr8 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_limmed 0x8000,0x0001,gr7 + test_spr_immed 0x00000001,iacc0l + test_spr_limmed 0x3fff,0xffff,iacc0h +smu28: + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + smu gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr7 + test_spr_immed 0x00000000,iacc0l + test_spr_limmed 0x4000,0x0000,iacc0h + + pass diff --git a/sim/testsuite/frv/fr400/subss.cgs b/sim/testsuite/frv/fr400/subss.cgs new file mode 100644 index 0000000..fcda589 --- /dev/null +++ b/sim/testsuite/frv/fr400/subss.cgs @@ -0,0 +1,43 @@ +# frv testcase for subss $GRi,$GRj,$GRk +# mach: fr405 fr450 + + .include "../testutils.inc" + + start + + .global sub +sub_no_saturate: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + subss gr8,gr7,gr8 + test_gr_immed 1,gr8 + + set_gr_immed 2,gr7 + set_gr_immed 1,gr8 + subss gr8,gr7,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + +sub_saturate_neg: + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + subss gr8,gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_limmed 0xffff,0xfff0,gr8 + subss gr8,gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + +sub_saturate_pos: + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + subss gr8,gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x0010,gr8 + set_gr_limmed 0x8000,0x0000,gr7 + subss gr8,gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + + + pass diff --git a/sim/testsuite/frv/fr400/udiv.cgs b/sim/testsuite/frv/fr400/udiv.cgs new file mode 100644 index 0000000..dd92bcd --- /dev/null +++ b/sim/testsuite/frv/fr400/udiv.cgs @@ -0,0 +1,46 @@ +# frv testcase for udiv $GRi,$GRj,$GRk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global udiv +udiv: + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + udiv gr3,gr2,gr3 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from udiv in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + udiv gr3,gr2,gr3 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr +e1: udiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/fr400/udivi.cgs b/sim/testsuite/frv/fr400/udivi.cgs new file mode 100644 index 0000000..69a7937 --- /dev/null +++ b/sim/testsuite/frv/fr400/udivi.cgs @@ -0,0 +1,47 @@ +# frv testcase for udivi $GRi,$s12,$GRk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global udivi +udivi: + ; simple division 12 / 3 + set_gr_immed 0x0000000c,gr3 + udivi gr3,3,gr3 + test_gr_immed 0x00000004,gr3 + + ; random example + set_gr_limmed 0xfedc,0xba98,gr3 + udivi gr3,0x7ff,gr3 + test_gr_limmed 0x001f,0xdf93,gr3 + + ; random example + set_gr_limmed 0xffff,0xffff,gr3 + udivi gr3,-2048,gr3 + test_gr_immed 1,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr +e1: udivi gr1,0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/fr500/allinsn.exp b/sim/testsuite/frv/fr500/allinsn.exp new file mode 100644 index 0000000..7d19259 --- /dev/null +++ b/sim/testsuite/frv/fr500/allinsn.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500 fr550" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/frv/fr500/cmqaddhss.cgs b/sim/testsuite/frv/fr500/cmqaddhss.cgs new file mode 100644 index 0000000..9c88620 --- /dev/null +++ b/sim/testsuite/frv/fr500/cmqaddhss.cgs @@ -0,0 +1,444 @@ +# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global cmqaddhss +cmqaddhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc4,1 + cmqaddhss fr12,fr12,fr16,cc4,1 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc5,0 + cmqaddhss fr12,fr12,fr16,cc5,0 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc4,0 + cmqaddhss fr12,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc5,1 + cmqaddhss fr12,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc6,1 + cmqaddhss fr12,fr12,fr16,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set +; + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc7,1 + cmqaddhss fr12,fr12,fr16,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/frv/fr500/cmqaddhus.cgs b/sim/testsuite/frv/fr500/cmqaddhus.cgs new file mode 100644 index 0000000..5b29c9a --- /dev/null +++ b/sim/testsuite/frv/fr500/cmqaddhus.cgs @@ -0,0 +1,360 @@ +# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global cmqaddhus +cmqaddhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc4,1 + cmqaddhus fr12,fr12,fr16,cc4,1 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc5,0 + cmqaddhus fr12,fr12,fr16,cc5,0 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc4,0 + cmqaddhus fr12,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc5,1 + cmqaddhus fr12,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc6,0 + cmqaddhus fr12,fr12,fr16,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc7,0 + cmqaddhus fr12,fr12,fr16,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/frv/fr500/cmqsubhss.cgs b/sim/testsuite/frv/fr500/cmqsubhss.cgs new file mode 100644 index 0000000..4dbee66 --- /dev/null +++ b/sim/testsuite/frv/fr500/cmqsubhss.cgs @@ -0,0 +1,448 @@ +# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global msubhss +msubhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc4,1 + cmqsubhss fr12,fr10,fr16,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc5,0 + cmqsubhss fr12,fr10,fr16,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc4,0 + cmqsubhss fr12,fr10,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc5,1 + cmqsubhss fr12,fr10,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc6,1 + cmqsubhss fr12,fr10,fr16,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc7,1 + cmqsubhss fr12,fr10,fr16,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/frv/fr500/cmqsubhus.cgs b/sim/testsuite/frv/fr500/cmqsubhus.cgs new file mode 100644 index 0000000..f60ae98 --- /dev/null +++ b/sim/testsuite/frv/fr500/cmqsubhus.cgs @@ -0,0 +1,370 @@ +# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global cmqsubhus +cmqsubhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc4,1 + cmqsubhus fr10,fr12,fr16,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc5,0 + cmqsubhus fr10,fr12,fr16,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc4,0 + cmqsubhus fr10,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_fr_limmed 0x4444,0x4444,fr17 + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc5,1 + cmqsubhus fr10,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_fr_limmed 0x4444,0x4444,fr17 + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc6,0 + cmqsubhus fr10,fr12,fr16,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_fr_limmed 0x4444,0x4444,fr17 +; + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc7,0 + cmqsubhus fr10,fr12,fr16,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_fr_limmed 0x4444,0x4444,fr17 + + pass diff --git a/sim/testsuite/frv/fr500/dcpl.cgs b/sim/testsuite/frv/fr500/dcpl.cgs new file mode 100644 index 0000000..c0c904c --- /dev/null +++ b/sim/testsuite/frv/fr500/dcpl.cgs @@ -0,0 +1,65 @@ +# FRV testcase for dcpl GRi,GRj,lock +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global dcpl +dcpl: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the data cache + set_gr_immed 0x70000,gr10 + dcpl gr10,gr0,1 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 1,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 63,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 64,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; Now write to another address which should be in the same set + ; the write should go through to memory, since all the lines in the + ; set are locked + inc_gr_immed 0x1000,gr10 + set_mem_immed 0xdeadbeef,gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Invalidate the data cache. Only the last value stored should have made + ; it through to memory + set_gr_immed 0x70000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0xdeadbeef,gr10 + + pass diff --git a/sim/testsuite/frv/fr500/dcul.cgs b/sim/testsuite/frv/fr500/dcul.cgs new file mode 100644 index 0000000..1c5bd93 --- /dev/null +++ b/sim/testsuite/frv/fr500/dcul.cgs @@ -0,0 +1,118 @@ +# FRV testcase for dcul GRi +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global dcul +dcul: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the data cache + set_gr_immed 0x70000,gr10 + lock_data_cache gr10 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 1,gr11 + lock_data_cache gr10 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 63,gr11 + lock_data_cache gr10 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 64,gr11 + lock_data_cache gr10 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; Now write to another address which should be in the same set + ; the write should go through to memory, since all the lines in the + ; set are locked + inc_gr_immed 0x1000,gr10 + set_mem_immed 0xdeadbeef,gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Invalidate the data cache. Only the last value stored should have made + ; it through to memory + set_gr_immed 0x70000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Now preload load and lock all the lines in set 0 of the data cache + ; again + set_gr_immed 0x70000,gr10 + lock_data_cache gr10 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 1,gr11 + lock_data_cache gr10 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 63,gr11 + lock_data_cache gr10 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 64,gr11 + lock_data_cache gr10 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; unlock one line + set_gr_immed 0x72000,gr10 + dcul gr10 + + ; Now write to another address which should be in the same set. + set_gr_immed 0x75000,gr10 + set_mem_immed 0xbeefdead,gr10 + + ; All of the stored values should be retrievable + + set_gr_immed 0x70000,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0x44444444,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0xdeadbeef,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0xbeefdead,gr10 + + pass diff --git a/sim/testsuite/frv/fr500/mclracc.cgs b/sim/testsuite/frv/fr500/mclracc.cgs new file mode 100644 index 0000000..43fcf75 --- /dev/null +++ b/sim/testsuite/frv/fr500/mclracc.cgs @@ -0,0 +1,79 @@ +# frv testcase for mclracc $ACC40k,$A +# mach: all + + .include "../testutils.inc" + + start + + .global mclracc +mclracc: + set_accg_immed 0xff,accg0 + set_acc_immed -1,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed -1,acc1 + set_accg_immed 0xff,accg3 + set_acc_immed -1,acc3 + set_accg_immed 0xff,accg7 + set_acc_immed -1,acc7 + + mclracc acc8,0 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + test_accg_immed 0xff,accg7 + test_acc_immed -1,acc7 + + mclracc acc8,1 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + test_accg_immed 0xff,accg7 + test_acc_immed -1,acc7 + + mclracc acc3,0 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0xff,accg7 + test_acc_immed -1,acc7 + + mclracc acc7,1 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0,accg7 + test_acc_immed 0,acc7 + + mclracc acc0,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0,accg7 + test_acc_immed 0,acc7 + + mclracc acc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0,accg7 + test_acc_immed 0,acc7 + + pass diff --git a/sim/testsuite/frv/fr500/mqaddhss.cgs b/sim/testsuite/frv/fr500/mqaddhss.cgs new file mode 100644 index 0000000..7183a3f --- /dev/null +++ b/sim/testsuite/frv/fr500/mqaddhss.cgs @@ -0,0 +1,79 @@ +# frv testcase for mqaddhss $FRi,$FRj,$FRj +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global mqaddhss +mqaddhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + mqaddhss.p fr10,fr10,fr14 + mqaddhss fr12,fr12,fr16 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr500/mqaddhus.cgs b/sim/testsuite/frv/fr500/mqaddhus.cgs new file mode 100644 index 0000000..9faa109 --- /dev/null +++ b/sim/testsuite/frv/fr500/mqaddhus.cgs @@ -0,0 +1,65 @@ +# frv testcase for mqaddhus $FRi,$FRj,$FRj +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global mqaddhus +mqaddhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + mqaddhus.p fr10,fr10,fr14 + mqaddhus fr12,fr12,fr16 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr500/mqsubhss.cgs b/sim/testsuite/frv/fr500/mqsubhss.cgs new file mode 100644 index 0000000..74d5a87 --- /dev/null +++ b/sim/testsuite/frv/fr500/mqsubhss.cgs @@ -0,0 +1,79 @@ +# frv testcase for mqsubhss $FRi,$FRj,$FRj +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global msubhss +msubhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + mqsubhss.p fr10,fr10,fr14 + mqsubhss fr12,fr10,fr16 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr500/mqsubhus.cgs b/sim/testsuite/frv/fr500/mqsubhus.cgs new file mode 100644 index 0000000..44aa7a9 --- /dev/null +++ b/sim/testsuite/frv/fr500/mqsubhus.cgs @@ -0,0 +1,66 @@ +# frv testcase for msubhus $FRi,$FRj,$FRj +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global msubhus +msubhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + mqsubhus.p fr10,fr10,fr14 + mqsubhus fr10,fr12,fr16 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr550/allinsn.exp b/sim/testsuite/frv/fr550/allinsn.exp new file mode 100644 index 0000000..1fe1795 --- /dev/null +++ b/sim/testsuite/frv/fr550/allinsn.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "fr550" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/frv/fr550/cmaddhss.cgs b/sim/testsuite/frv/fr550/cmaddhss.cgs new file mode 100644 index 0000000..174a3dc --- /dev/null +++ b/sim/testsuite/frv/fr550/cmaddhss.cgs @@ -0,0 +1,547 @@ +# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global maddhss +maddhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc4,1 + cmaddhss fr11,fr11,fr13,cc4,1 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc5,0 + cmaddhss fr11,fr11,fr13,cc5,0 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc4,0 + cmaddhss fr11,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc5,1 + cmaddhss fr11,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc6,1 + cmaddhss fr11,fr11,fr13,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc7,1 + cmaddhss fr11,fr11,fr13,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/frv/fr550/cmaddhus.cgs b/sim/testsuite/frv/fr550/cmaddhus.cgs new file mode 100644 index 0000000..40e1152 --- /dev/null +++ b/sim/testsuite/frv/fr550/cmaddhus.cgs @@ -0,0 +1,481 @@ +# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmaddhus +cmaddhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc4,1 + cmaddhus fr11,fr11,fr13,cc4,1 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc5,0 + cmaddhus fr11,fr11,fr13,cc5,0 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc4,0 + cmaddhus fr11,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc5,1 + cmaddhus fr11,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc6,0 + cmaddhus fr11,fr11,fr13,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc7,0 + cmaddhus fr11,fr11,fr13,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/frv/fr550/cmcpxiu.cgs b/sim/testsuite/frv/fr550/cmcpxiu.cgs new file mode 100644 index 0000000..341949b --- /dev/null +++ b/sim/testsuite/frv/fr550/cmcpxiu.cgs @@ -0,0 +1,492 @@ +# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmcpxiu +cmcpxiu: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/frv/fr550/cmcpxru.cgs b/sim/testsuite/frv/fr550/cmcpxru.cgs new file mode 100644 index 0000000..3eeb0a0 --- /dev/null +++ b/sim/testsuite/frv/fr550/cmcpxru.cgs @@ -0,0 +1,528 @@ +# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmcpxru +cmcpxru: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 +; + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/frv/fr550/cmmachs.cgs b/sim/testsuite/frv/fr550/cmmachs.cgs new file mode 100644 index 0000000..f716867 --- /dev/null +++ b/sim/testsuite/frv/fr550/cmmachs.cgs @@ -0,0 +1,1545 @@ +# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmmachs +cmmachs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_spr_immed 0x0,msr0 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc4,1 +;;;;;;;;;;;; + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed -128,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed -128,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_accg_immed 0x0,accg0 ; saturation + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 +; + ; Positive operands + set_spr_immed 0x0,msr0 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/frv/fr550/cmmachu.cgs b/sim/testsuite/frv/fr550/cmmachu.cgs new file mode 100644 index 0000000..176d1b1 --- /dev/null +++ b/sim/testsuite/frv/fr550/cmmachu.cgs @@ -0,0 +1,858 @@ +# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmmachu +cmmachu: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 +; + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + pass diff --git a/sim/testsuite/frv/fr550/cmqaddhss.cgs b/sim/testsuite/frv/fr550/cmqaddhss.cgs new file mode 100644 index 0000000..3d32bec --- /dev/null +++ b/sim/testsuite/frv/fr550/cmqaddhss.cgs @@ -0,0 +1,429 @@ +# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqaddhss +cmqaddhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc4,1 + cmqaddhss fr12,fr12,fr16,cc4,1 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc5,0 + cmqaddhss fr12,fr12,fr16,cc5,0 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc4,0 + cmqaddhss fr12,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc5,1 + cmqaddhss fr12,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc6,1 + cmqaddhss fr12,fr12,fr16,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set +; + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc7,1 + cmqaddhss fr12,fr12,fr16,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/frv/fr550/cmqaddhus.cgs b/sim/testsuite/frv/fr550/cmqaddhus.cgs new file mode 100644 index 0000000..4e25ba4 --- /dev/null +++ b/sim/testsuite/frv/fr550/cmqaddhus.cgs @@ -0,0 +1,345 @@ +# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqaddhus +cmqaddhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc4,1 + cmqaddhus fr12,fr12,fr16,cc4,1 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc5,0 + cmqaddhus fr12,fr12,fr16,cc5,0 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc4,0 + cmqaddhus fr12,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc5,1 + cmqaddhus fr12,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc6,0 + cmqaddhus fr12,fr12,fr16,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc7,0 + cmqaddhus fr12,fr12,fr16,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/frv/fr550/cmqmachs.cgs b/sim/testsuite/frv/fr550/cmqmachs.cgs new file mode 100644 index 0000000..0aee4f0 --- /dev/null +++ b/sim/testsuite/frv/fr550/cmqmachs.cgs @@ -0,0 +1,1262 @@ +# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqmachs +cmqmachs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 +; + ; Positive operands + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/frv/fr550/cmqmachu.cgs b/sim/testsuite/frv/fr550/cmqmachu.cgs new file mode 100644 index 0000000..8b880f8 --- /dev/null +++ b/sim/testsuite/frv/fr550/cmqmachu.cgs @@ -0,0 +1,870 @@ +# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqmachu +cmqmachu: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 +; + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + pass diff --git a/sim/testsuite/frv/fr550/cmqsubhss.cgs b/sim/testsuite/frv/fr550/cmqsubhss.cgs new file mode 100644 index 0000000..490b449 --- /dev/null +++ b/sim/testsuite/frv/fr550/cmqsubhss.cgs @@ -0,0 +1,429 @@ +# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global msubhss +msubhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc4,1 + cmqsubhss fr12,fr10,fr16,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc5,0 + cmqsubhss fr12,fr10,fr16,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf not set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc4,0 + cmqsubhss fr12,fr10,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc5,1 + cmqsubhss fr12,fr10,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc6,1 + cmqsubhss fr12,fr10,fr16,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc7,1 + cmqsubhss fr12,fr10,fr16,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/frv/fr550/cmqsubhus.cgs b/sim/testsuite/frv/fr550/cmqsubhus.cgs new file mode 100644 index 0000000..90bd89a --- /dev/null +++ b/sim/testsuite/frv/fr550/cmqsubhus.cgs @@ -0,0 +1,351 @@ +# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqsubhus +cmqsubhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc4,1 + cmqsubhus fr10,fr12,fr16,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc5,0 + cmqsubhus fr10,fr12,fr16,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc4,0 + cmqsubhus fr10,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_fr_limmed 0x4444,0x4444,fr17 + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc5,1 + cmqsubhus fr10,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_fr_limmed 0x4444,0x4444,fr17 + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc6,0 + cmqsubhus fr10,fr12,fr16,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_fr_limmed 0x4444,0x4444,fr17 +; + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc7,0 + cmqsubhus fr10,fr12,fr16,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_fr_limmed 0x4444,0x4444,fr17 + + pass diff --git a/sim/testsuite/frv/fr550/cmsubhss.cgs b/sim/testsuite/frv/fr550/cmsubhss.cgs new file mode 100644 index 0000000..9370d54 --- /dev/null +++ b/sim/testsuite/frv/fr550/cmsubhss.cgs @@ -0,0 +1,547 @@ +# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmsubhss +cmsubhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc4,1 + cmsubhss fr11,fr10,fr13,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc5,0 + cmsubhss fr11,fr10,fr13,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc4,0 + cmsubhss fr11,fr10,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc5,1 + cmsubhss fr11,fr10,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc6,1 + cmsubhss fr11,fr10,fr13,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc7,1 + cmsubhss fr11,fr10,fr13,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/frv/fr550/cmsubhus.cgs b/sim/testsuite/frv/fr550/cmsubhus.cgs new file mode 100644 index 0000000..5cf676b --- /dev/null +++ b/sim/testsuite/frv/fr550/cmsubhus.cgs @@ -0,0 +1,427 @@ +# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmsubhus +cmsubhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc4,1 + cmsubhus fr10,fr11,fr13,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc5,0 + cmsubhus fr10,fr11,fr13,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc4,0 + cmsubhus fr10,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc5,1 + cmsubhus fr10,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc6,0 + cmsubhus fr10,fr11,fr13,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc7,0 + cmsubhus fr10,fr11,fr13,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/frv/fr550/dcpl.cgs b/sim/testsuite/frv/fr550/dcpl.cgs new file mode 100644 index 0000000..93c659a --- /dev/null +++ b/sim/testsuite/frv/fr550/dcpl.cgs @@ -0,0 +1,65 @@ +# FRV testcase for dcpl GRi,GRj,lock +# mach: all + + .include "../testutils.inc" + + start + + .global dcpl +dcpl: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the data cache + set_gr_immed 0x70000,gr10 + dcpl gr10,gr0,1 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 1,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 63,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 64,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; Now write to another address which should be in the same set + ; the write should go through to memory, since all the lines in the + ; set are locked + inc_gr_immed 0x2000,gr10 + set_mem_immed 0xdeadbeef,gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Invalidate the data cache. Only the last value stored should have made + ; it through to memory + set_gr_immed 0x70000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0xdeadbeef,gr10 + + pass diff --git a/sim/testsuite/frv/fr550/dcul.cgs b/sim/testsuite/frv/fr550/dcul.cgs new file mode 100644 index 0000000..a3bd4be --- /dev/null +++ b/sim/testsuite/frv/fr550/dcul.cgs @@ -0,0 +1,118 @@ +# FRV testcase for dcul GRi +# mach: all + + .include "../testutils.inc" + + start + + .global dcul +dcul: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the data cache + set_gr_immed 0x70000,gr10 + lock_data_cache gr10 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 1,gr11 + lock_data_cache gr10 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 63,gr11 + lock_data_cache gr10 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 64,gr11 + lock_data_cache gr10 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; Now write to another address which should be in the same set + ; the write should go through to memory, since all the lines in the + ; set are locked + inc_gr_immed 0x2000,gr10 + set_mem_immed 0xdeadbeef,gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Invalidate the data cache. Only the last value stored should have made + ; it through to memory + set_gr_immed 0x70000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Now preload load and lock all the lines in set 0 of the data cache + ; again + set_gr_immed 0x70000,gr10 + lock_data_cache gr10 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 1,gr11 + lock_data_cache gr10 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 63,gr11 + lock_data_cache gr10 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 64,gr11 + lock_data_cache gr10 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; unlock one line + set_gr_immed 0x78000,gr10 + dcul gr10 + + ; Now write to another address which should be in the same set. + set_gr_immed 0x7a000,gr10 + set_mem_immed 0xbeefdead,gr10 + + ; All of the stored values should be retrievable + + set_gr_immed 0x70000,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x2000,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x2000,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x2000,gr10 + test_mem_immed 0x44444444,gr10 + + inc_gr_immed 0x2000,gr10 + test_mem_immed 0xdeadbeef,gr10 + + inc_gr_immed 0x2000,gr10 + test_mem_immed 0xbeefdead,gr10 + + pass diff --git a/sim/testsuite/frv/fr550/mabshs.cgs b/sim/testsuite/frv/fr550/mabshs.cgs new file mode 100644 index 0000000..9168df8 --- /dev/null +++ b/sim/testsuite/frv/fr550/mabshs.cgs @@ -0,0 +1,64 @@ +# frv testcase for mabshs $FRj,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mabshs +mabshs: + set_fr_iimmed 0x0000,0x0000,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x0000,0x0000,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0xffff,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x0001,0x0001,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7fff,0x8001,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7fff,0x8000,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8000,0x7fff,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + mabshs.p fr10,fr12 + mabshs fr11,fr13 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr550/maddaccs.cgs b/sim/testsuite/frv/fr550/maddaccs.cgs new file mode 100644 index 0000000..262a148 --- /dev/null +++ b/sim/testsuite/frv/fr550/maddaccs.cgs @@ -0,0 +1,128 @@ +# frv testcase for maddaccs $ACC40Si,$ACC40Sk +# mach: all + + .include "../testutils.inc" + + start + + .global maddaccs +maddaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0xdead,0xbeef,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0xbeef,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0x2345,0x6789,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg4 + set_acc_immed 0x00000001,acc4 + set_accg_immed 0x7f,accg5 + set_acc_immed 0xffffffff,acc5 + maddaccs.p acc0,acc1 + maddaccs acc4,acc5 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0x7f,accg5 + test_acc_limmed 0xffff,0xffff,acc5 + + pass diff --git a/sim/testsuite/frv/fr550/maddhss.cgs b/sim/testsuite/frv/fr550/maddhss.cgs new file mode 100644 index 0000000..8c5c714 --- /dev/null +++ b/sim/testsuite/frv/fr550/maddhss.cgs @@ -0,0 +1,97 @@ +# frv testcase for maddhss $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global maddhss +maddhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maddhss fr10,fr11,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maddhss.p fr10,fr10,fr12 + maddhss fr11,fr11,fr13 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr550/maddhus.cgs b/sim/testsuite/frv/fr550/maddhus.cgs new file mode 100644 index 0000000..93d06bd --- /dev/null +++ b/sim/testsuite/frv/fr550/maddhus.cgs @@ -0,0 +1,86 @@ +# frv testcase for maddhus $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global maddhus +maddhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + maddhus.p fr10,fr10,fr12 + maddhus fr11,fr11,fr13 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr550/masaccs.cgs b/sim/testsuite/frv/fr550/masaccs.cgs new file mode 100644 index 0000000..9595d16 --- /dev/null +++ b/sim/testsuite/frv/fr550/masaccs.cgs @@ -0,0 +1,148 @@ +# frv testcase for masaccs $ACC40Si,$ACC40Sk +# mach: all + + .include "../testutils.inc" + + start + + .global masaccs +masaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0xdead,0xbeef,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0xbeef,0xdead,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0x4111,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x2345,0x6789,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set + test_accg_immed 1,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xfffc,0x7ffd,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0003,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg4 + set_acc_immed 0x00000001,acc4 + set_accg_immed 0x7f,accg5 + set_acc_immed 0xffffffff,acc5 + masaccs.p acc0,acc0 + masaccs acc4,acc4 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg4 + test_acc_limmed 0xffff,0xffff,acc4 + test_accg_immed 0x80,accg5 + test_acc_limmed 0x0000,0x0002,acc5 + + pass diff --git a/sim/testsuite/frv/fr550/mdaddaccs.cgs b/sim/testsuite/frv/fr550/mdaddaccs.cgs new file mode 100644 index 0000000..92d23d0 --- /dev/null +++ b/sim/testsuite/frv/fr550/mdaddaccs.cgs @@ -0,0 +1,102 @@ +# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk +# mach: all + + .include "../testutils.inc" + + start + + .global mdaddaccs +mdaddaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdead,0xbeef,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0xbeef,0xdead,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x2345,0x6789,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xfffffffe,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/frv/fr550/mdasaccs.cgs b/sim/testsuite/frv/fr550/mdasaccs.cgs new file mode 100644 index 0000000..8821621 --- /dev/null +++ b/sim/testsuite/frv/fr550/mdasaccs.cgs @@ -0,0 +1,122 @@ +# frv testcase for mdasaccs $ACC40Si,$ACC40Sk +# mach: all + + .include "../testutils.inc" + + start + + .global mdasaccs +mdasaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xdead,0xbeef,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0xbeef,0xdead,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x4111,0xdead,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x2345,0x6789,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x1234,0x5677,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x1234,0x5679,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xfffffffe,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0xa,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffc,0x7ffd,acc1 + test_accg_immed 0x80,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0003,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + + pass diff --git a/sim/testsuite/frv/fr550/mdsubaccs.cgs b/sim/testsuite/frv/fr550/mdsubaccs.cgs new file mode 100644 index 0000000..1fe7498 --- /dev/null +++ b/sim/testsuite/frv/fr550/mdsubaccs.cgs @@ -0,0 +1,102 @@ +# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk +# mach: all + + .include "../testutils.inc" + + start + + .global mdsubaccs +mdsubaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg2 + test_acc_limmed 0x4111,0xdead,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg2 + test_acc_limmed 0x1234,0x5679,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffffffe,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x00000002,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0x00000000,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/frv/fr550/mmachs.cgs b/sim/testsuite/frv/fr550/mmachs.cgs new file mode 100644 index 0000000..9014076 --- /dev/null +++ b/sim/testsuite/frv/fr550/mmachs.cgs @@ -0,0 +1,259 @@ +# frv testcase for mmachs $GRi,$GRj,$ACCk +# mach: all + + .include "../testutils.inc" + + start + + .global mmachs +mmachs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmachs fr7,fr8,acc0 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/frv/fr550/mmachu.cgs b/sim/testsuite/frv/fr550/mmachu.cgs new file mode 100644 index 0000000..cd5c03c --- /dev/null +++ b/sim/testsuite/frv/fr550/mmachu.cgs @@ -0,0 +1,146 @@ +# frv testcase for mmachu $GRi,$GRj,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global mmachu +mmachu: + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + pass diff --git a/sim/testsuite/frv/fr550/mmrdhs.cgs b/sim/testsuite/frv/fr550/mmrdhs.cgs new file mode 100644 index 0000000..1aeb1b5 --- /dev/null +++ b/sim/testsuite/frv/fr550/mmrdhs.cgs @@ -0,0 +1,263 @@ +# frv testcase for mmrdhs $GRi,$GRj,$ACCk +# mach: all + + .include "../testutils.inc" + + start + + .global mmrdhs +mmrdhs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_immed -8,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x7ffa,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xfffe,0xfffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xfffe,0xfffa,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xbfff,0xfff9,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xbfff,0xfff9,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xbfff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xbfff,0xffff,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x0001,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x0001,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x0001,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x0001,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x4003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x4003,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0xc003,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4003,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x4003,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x3ffd,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x3ffb,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_immed 0xc0013ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xc0013ffa,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_immed 0x80013ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0x80013ffa,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 0xffff,1,fr7 + set_fr_iimmed 1,0xffff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x8000,0x0000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0,1,fr7 + set_fr_iimmed 1,1,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/frv/fr550/mmrdhu.cgs b/sim/testsuite/frv/fr550/mmrdhu.cgs new file mode 100644 index 0000000..99378bc --- /dev/null +++ b/sim/testsuite/frv/fr550/mmrdhu.cgs @@ -0,0 +1,151 @@ +# frv testcase for mmrdhu $GRi,$GRj,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global mmrdhu +mmrdhu: + set_accg_immed 0x80,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffffa,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffff8,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffff8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffff8,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffff8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0x7ffa,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xfffe,0xfffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffe,0xfffa,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xfffd,0xfffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffd,0xfffa,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xbffe,0xfff9,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xbffe,0xfff9,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0x7ffe,0xfff9,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0x7ffe,0xfff9,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7e,accg0 + test_acc_limmed 0x8000,0xfff8,acc0 + test_accg_immed 0x7e,accg1 + test_acc_limmed 0x8000,0xfff8,acc1 + + set_accg_immed 0,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0xffff,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/frv/fr550/mqaddhss.cgs b/sim/testsuite/frv/fr550/mqaddhss.cgs new file mode 100644 index 0000000..b0c7853 --- /dev/null +++ b/sim/testsuite/frv/fr550/mqaddhss.cgs @@ -0,0 +1,76 @@ +# frv testcase for mqaddhss $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global mqaddhss +mqaddhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + mqaddhss.p fr10,fr10,fr14 + mqaddhss fr12,fr12,fr16 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr550/mqaddhus.cgs b/sim/testsuite/frv/fr550/mqaddhus.cgs new file mode 100644 index 0000000..7f8b755 --- /dev/null +++ b/sim/testsuite/frv/fr550/mqaddhus.cgs @@ -0,0 +1,62 @@ +# frv testcase for mqaddhus $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global mqaddhus +mqaddhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + mqaddhus.p fr10,fr10,fr14 + mqaddhus fr12,fr12,fr16 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr550/mqmachs.cgs b/sim/testsuite/frv/fr550/mqmachs.cgs new file mode 100644 index 0000000..2f18620 --- /dev/null +++ b/sim/testsuite/frv/fr550/mqmachs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqmachs $GRi,$GRj,$ACCk +# mach: all + + .include "../testutils.inc" + + start + + .global mqmachs +mqmachs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/frv/fr550/mqmachu.cgs b/sim/testsuite/frv/fr550/mqmachu.cgs new file mode 100644 index 0000000..71cba98 --- /dev/null +++ b/sim/testsuite/frv/fr550/mqmachu.cgs @@ -0,0 +1,144 @@ +# frv testcase for mqmachu $GRi,$GRj,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global mqmachu +mqmachu: + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/frv/fr550/mqmacxhs.cgs b/sim/testsuite/frv/fr550/mqmacxhs.cgs new file mode 100644 index 0000000..aded33e --- /dev/null +++ b/sim/testsuite/frv/fr550/mqmacxhs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqmacxhs $GRi,$GRj,$ACCk +# mach: all + + .include "../testutils.inc" + + start + + .global mqmacxhs +mqmacxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 0xffff,1,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/frv/fr550/mqsubhss.cgs b/sim/testsuite/frv/fr550/mqsubhss.cgs new file mode 100644 index 0000000..a8936e9 --- /dev/null +++ b/sim/testsuite/frv/fr550/mqsubhss.cgs @@ -0,0 +1,76 @@ +# frv testcase for mqsubhss $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global msubhss +msubhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + mqsubhss.p fr10,fr10,fr14 + mqsubhss fr12,fr10,fr16 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr550/mqsubhus.cgs b/sim/testsuite/frv/fr550/mqsubhus.cgs new file mode 100644 index 0000000..fc92eb5 --- /dev/null +++ b/sim/testsuite/frv/fr550/mqsubhus.cgs @@ -0,0 +1,63 @@ +# frv testcase for msubhus $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global msubhus +msubhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + mqsubhus.p fr10,fr10,fr14 + mqsubhus fr10,fr12,fr16 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr550/mqxmachs.cgs b/sim/testsuite/frv/fr550/mqxmachs.cgs new file mode 100644 index 0000000..3c08e41 --- /dev/null +++ b/sim/testsuite/frv/fr550/mqxmachs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqxmachs $GRi,$GRj,$ACCk +# mach: all + + .include "../testutils.inc" + + start + + .global mqxmachs +mqxmachs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 6,acc2 + test_accg_immed 0,accg3 + test_acc_immed 6,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_immed 8,acc2 + test_accg_immed 0,accg3 + test_acc_immed 8,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8008,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7fff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7fff,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7ffd,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffb,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffb,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffb,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0008,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_immed 0x3fff0009,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fff0009,acc3 + test_accg_immed 0,accg0 + test_acc_immed 0x3fffbffd,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fffbffd,acc1 + + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/frv/fr550/mqxmacxhs.cgs b/sim/testsuite/frv/fr550/mqxmacxhs.cgs new file mode 100644 index 0000000..32b043b --- /dev/null +++ b/sim/testsuite/frv/fr550/mqxmacxhs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk +# mach: all + + .include "../testutils.inc" + + start + + .global mqxmacxhs +mqxmacxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 6,acc2 + test_accg_immed 0,accg3 + test_acc_immed 6,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_immed 8,acc2 + test_accg_immed 0,accg3 + test_acc_immed 8,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8008,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7fff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7fff,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7ffd,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffb,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffb,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffb,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0008,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_immed 0x3fff0009,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fff0009,acc3 + test_accg_immed 0,accg0 + test_acc_immed 0x3fffbffd,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fffbffd,acc1 + + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 0xffff,1,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/frv/fr550/msubaccs.cgs b/sim/testsuite/frv/fr550/msubaccs.cgs new file mode 100644 index 0000000..eeaf4a6 --- /dev/null +++ b/sim/testsuite/frv/fr550/msubaccs.cgs @@ -0,0 +1,128 @@ +# frv testcase for msubaccs $ACC40Si,$ACC40Sk +# mach: all + + .include "../testutils.inc" + + start + + .global msubaccs +msubaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg3 + test_acc_limmed 0x4111,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffffffe,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000002,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg4 + set_acc_immed 0x00000001,acc4 + set_accg_immed 0x80,accg5 + set_acc_immed 0x00000000,acc5 + msubaccs.p acc0,acc1 + msubaccs acc4,acc5 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg5 + test_acc_limmed 0xffff,0xffff,acc5 + + pass diff --git a/sim/testsuite/frv/fr550/msubhss.cgs b/sim/testsuite/frv/fr550/msubhss.cgs new file mode 100644 index 0000000..6beb676 --- /dev/null +++ b/sim/testsuite/frv/fr550/msubhss.cgs @@ -0,0 +1,97 @@ +# frv testcase for msubhss $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global msubhss +msubhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + msubhss.p fr10,fr10,fr12 + msubhss fr11,fr10,fr13 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr550/msubhus.cgs b/sim/testsuite/frv/fr550/msubhus.cgs new file mode 100644 index 0000000..5a3cd26 --- /dev/null +++ b/sim/testsuite/frv/fr550/msubhus.cgs @@ -0,0 +1,77 @@ +# frv testcase for msubhus $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global msubhus +msubhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + msubhus.p fr10,fr10,fr12 + msubhus fr10,fr11,fr13 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/fr550/mtrap.cgs b/sim/testsuite/frv/fr550/mtrap.cgs new file mode 100644 index 0000000..83dca7b --- /dev/null +++ b/sim/testsuite/frv/fr550/mtrap.cgs @@ -0,0 +1,50 @@ +# frv testcase for mp_exception +# mach: all + + .include "../testutils.inc" + + start + + .global mp_exception +mpx: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x0e0,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + set_gr_immed 0,gr5 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + mtrap ; generate interrupt + test_gr_immed 1,gr5 + + and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields + mcmpsh fr10,fr11,fcc0 ; no exception + test_spr_bits 0x7000,12,1,msr0; msr0.mtt is always set + mtrap ; nop + test_gr_immed 1,gr5 + + pass + +; exception handler +ok1: + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + inc_gr_immed 1,gr5 + rett 0 + fail diff --git a/sim/testsuite/frv/fr550/udiv.cgs b/sim/testsuite/frv/fr550/udiv.cgs new file mode 100644 index 0000000..05cbde4 --- /dev/null +++ b/sim/testsuite/frv/fr550/udiv.cgs @@ -0,0 +1,48 @@ +# frv testcase for udiv $GRi,$GRj,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global udiv +udiv: + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + udiv gr3,gr2,gr3 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from udiv in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + udiv gr3,gr2,gr3 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr + set_gr_addr e1,gr17 +e1: udiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/fr550/udivi.cgs b/sim/testsuite/frv/fr550/udivi.cgs new file mode 100644 index 0000000..d5ee1c4 --- /dev/null +++ b/sim/testsuite/frv/fr550/udivi.cgs @@ -0,0 +1,49 @@ +# frv testcase for udivi $GRi,$s12,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global udivi +udivi: + ; simple division 12 / 3 + set_gr_immed 0x0000000c,gr3 + udivi gr3,3,gr3 + test_gr_immed 0x00000004,gr3 + + ; random example + set_gr_limmed 0xfedc,0xba98,gr3 + udivi gr3,0x7ff,gr3 + test_gr_limmed 0x001f,0xdf93,gr3 + + ; random example + set_gr_limmed 0xffff,0xffff,gr3 + udivi gr3,-2048,gr3 + test_gr_immed 1,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr + set_gr_addr e1,gr17 +e1: udivi gr1,0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/fsqrtd.cgs b/sim/testsuite/frv/fsqrtd.cgs new file mode 100644 index 0000000..a428b01 --- /dev/null +++ b/sim/testsuite/frv/fsqrtd.cgs @@ -0,0 +1,22 @@ +# frv testcase for fsqrtd $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fsqrtd +fsqrtd: + fsqrtd fr44,fr2 ; 9.0 + test_dfr_dfr fr2,fr36 ; 3.0 + + set_fr_iimmed 0x4009,0x21fb,fr10 ; 3.141592654 + set_fr_iimmed 0x6000,0x0000,fr11 + fsqrtd fr10,fr10 + test_fr_iimmed 0x3ffc5bf8,fr10 ; 1.7724539 + test_fr_iimmed 0x9853a94d,fr11 + + pass diff --git a/sim/testsuite/frv/fsqrts.cgs b/sim/testsuite/frv/fsqrts.cgs new file mode 100644 index 0000000..e771c40 --- /dev/null +++ b/sim/testsuite/frv/fsqrts.cgs @@ -0,0 +1,19 @@ +# frv testcase for fsqrts $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fsqrts +fsqrts: + fsqrts fr44,fr1 ; 9.0 + test_fr_fr fr1,fr36 ; 3.0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + fsqrts fr10,fr10 + test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 + + pass diff --git a/sim/testsuite/frv/fstoi.cgs b/sim/testsuite/frv/fstoi.cgs new file mode 100644 index 0000000..0a90a2a --- /dev/null +++ b/sim/testsuite/frv/fstoi.cgs @@ -0,0 +1,24 @@ +# frv testcase for fstoi $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fstoi +fstoi: + fstoi fr16,fr1 + test_fr_iimmed 0,fr1 + fstoi fr20,fr1 + test_fr_iimmed 0,fr1 + + fstoi fr32,fr1 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xce05,0x4904,fr1 + fstoi fr1,fr1 + test_fr_iimmed 0xdeadbf00,fr1 + + pass diff --git a/sim/testsuite/frv/fsubd.cgs b/sim/testsuite/frv/fsubd.cgs new file mode 100644 index 0000000..fed2d04 --- /dev/null +++ b/sim/testsuite/frv/fsubd.cgs @@ -0,0 +1,83 @@ +# frv testcase for fsubd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fsubd +fsubd: + fsubd fr0,fr16,fr2 + test_dfr_dfr fr2,fr0 + fsubd fr4,fr16,fr2 + test_dfr_dfr fr2,fr4 + fsubd fr8,fr16,fr2 + test_dfr_dfr fr2,fr8 + fsubd fr12,fr16,fr2 + test_dfr_dfr fr2,fr12 + fsubd fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fsubd fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fsubd fr24,fr16,fr2 + test_dfr_dfr fr2,fr24 + fsubd fr28,fr16,fr2 + test_dfr_dfr fr2,fr28 + fsubd fr32,fr16,fr2 + test_dfr_dfr fr2,fr32 + fsubd fr36,fr16,fr2 + test_dfr_dfr fr2,fr36 + fsubd fr40,fr16,fr2 + test_dfr_dfr fr2,fr40 + fsubd fr44,fr16,fr2 + test_dfr_dfr fr2,fr44 + fsubd fr48,fr16,fr2 + test_dfr_dfr fr2,fr48 + fsubd fr52,fr16,fr2 + test_dfr_dfr fr2,fr52 + + fsubd fr0,fr20,fr2 + test_dfr_dfr fr2,fr0 + fsubd fr4,fr20,fr2 + test_dfr_dfr fr2,fr4 + fsubd fr8,fr20,fr2 + test_dfr_dfr fr2,fr8 + fsubd fr12,fr20,fr2 + test_dfr_dfr fr2,fr12 + fsubd fr16,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fsubd fr20,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fsubd fr24,fr20,fr2 + test_dfr_dfr fr2,fr24 + fsubd fr28,fr20,fr2 + test_dfr_dfr fr2,fr28 + fsubd fr32,fr20,fr2 + test_dfr_dfr fr2,fr32 + fsubd fr36,fr20,fr2 + test_dfr_dfr fr2,fr36 + fsubd fr40,fr20,fr2 + test_dfr_dfr fr2,fr40 + fsubd fr44,fr20,fr2 + test_dfr_dfr fr2,fr44 + fsubd fr48,fr20,fr2 + test_dfr_dfr fr2,fr48 + fsubd fr52,fr20,fr2 + test_dfr_dfr fr2,fr52 + + fsubd fr32,fr36,fr2 + test_dfr_dfr fr2,fr8 + + fsubd fr44,fr40,fr2 + test_dfr_dfr fr2,fr36 + + pass + + diff --git a/sim/testsuite/frv/fsubs.cgs b/sim/testsuite/frv/fsubs.cgs new file mode 100644 index 0000000..c1143ad --- /dev/null +++ b/sim/testsuite/frv/fsubs.cgs @@ -0,0 +1,82 @@ +# frv testcase for fsubs $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fsubs +fsubs: + fsubs fr0,fr16,fr1 + test_fr_fr fr1,fr0 + fsubs fr4,fr16,fr1 + test_fr_fr fr1,fr4 + fsubs fr8,fr16,fr1 + test_fr_fr fr1,fr8 + fsubs fr12,fr16,fr1 + test_fr_fr fr1,fr12 + fsubs fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fsubs fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fsubs fr24,fr16,fr1 + test_fr_fr fr1,fr24 + fsubs fr28,fr16,fr1 + test_fr_fr fr1,fr28 + fsubs fr32,fr16,fr1 + test_fr_fr fr1,fr32 + fsubs fr36,fr16,fr1 + test_fr_fr fr1,fr36 + fsubs fr40,fr16,fr1 + test_fr_fr fr1,fr40 + fsubs fr44,fr16,fr1 + test_fr_fr fr1,fr44 + fsubs fr48,fr16,fr1 + test_fr_fr fr1,fr48 + fsubs fr52,fr16,fr1 + test_fr_fr fr1,fr52 + + fsubs fr0,fr20,fr1 + test_fr_fr fr1,fr0 + fsubs fr4,fr20,fr1 + test_fr_fr fr1,fr4 + fsubs fr8,fr20,fr1 + test_fr_fr fr1,fr8 + fsubs fr12,fr20,fr1 + test_fr_fr fr1,fr12 + fsubs fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fsubs fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fsubs fr24,fr20,fr1 + test_fr_fr fr1,fr24 + fsubs fr28,fr20,fr1 + test_fr_fr fr1,fr28 + fsubs fr32,fr20,fr1 + test_fr_fr fr1,fr32 + fsubs fr36,fr20,fr1 + test_fr_fr fr1,fr36 + fsubs fr40,fr20,fr1 + test_fr_fr fr1,fr40 + fsubs fr44,fr20,fr1 + test_fr_fr fr1,fr44 + fsubs fr48,fr20,fr1 + test_fr_fr fr1,fr48 + fsubs fr52,fr20,fr1 + test_fr_fr fr1,fr52 + + fsubs fr32,fr36,fr1 + test_fr_fr fr1,fr8 + + fsubs fr44,fr40,fr1 + test_fr_fr fr1,fr36 + + pass + + diff --git a/sim/testsuite/frv/fteq.cgs b/sim/testsuite/frv/fteq.cgs new file mode 100644 index 0000000..020a887 --- /dev/null +++ b/sim/testsuite/frv/fteq.cgs @@ -0,0 +1,101 @@ +# frv testcase for fteq $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global fteq +fteq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x4 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x6 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x7 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftge.cgs b/sim/testsuite/frv/ftge.cgs new file mode 100644 index 0000000..eab7a06 --- /dev/null +++ b/sim/testsuite/frv/ftge.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftge $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftge +ftge: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftgt.cgs b/sim/testsuite/frv/ftgt.cgs new file mode 100644 index 0000000..9035fbc --- /dev/null +++ b/sim/testsuite/frv/ftgt.cgs @@ -0,0 +1,101 @@ +# frv testcase for ftgt $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftgt +ftgt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xd 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftieq.cgs b/sim/testsuite/frv/ftieq.cgs new file mode 100644 index 0000000..a5710ad --- /dev/null +++ b/sim/testsuite/frv/ftieq.cgs @@ -0,0 +1,100 @@ +# frv testcase for ftieq $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftieq +ftieq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x4 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x6 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x7 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftige.cgs b/sim/testsuite/frv/ftige.cgs new file mode 100644 index 0000000..5b58ce0 --- /dev/null +++ b/sim/testsuite/frv/ftige.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftige $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftige +ftige: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftigt.cgs b/sim/testsuite/frv/ftigt.cgs new file mode 100644 index 0000000..e31ead4 --- /dev/null +++ b/sim/testsuite/frv/ftigt.cgs @@ -0,0 +1,100 @@ +# frv testcase for ftigt $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftigt +ftigt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xd 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftile.cgs b/sim/testsuite/frv/ftile.cgs new file mode 100644 index 0000000..d13eeee --- /dev/null +++ b/sim/testsuite/frv/ftile.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftile $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftile +ftile: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftilg.cgs b/sim/testsuite/frv/ftilg.cgs new file mode 100644 index 0000000..26127d2 --- /dev/null +++ b/sim/testsuite/frv/ftilg.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftilg $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftilg +ftilg: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftilt.cgs b/sim/testsuite/frv/ftilt.cgs new file mode 100644 index 0000000..7a74d5b --- /dev/null +++ b/sim/testsuite/frv/ftilt.cgs @@ -0,0 +1,100 @@ +# frv testcase for ftilt $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftilt +ftilt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xa 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xb 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftine.cgs b/sim/testsuite/frv/ftine.cgs new file mode 100644 index 0000000..89aa5a6 --- /dev/null +++ b/sim/testsuite/frv/ftine.cgs @@ -0,0 +1,112 @@ +# frv testcase for ftine $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftine +ftine: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftino.cgs b/sim/testsuite/frv/ftino.cgs new file mode 100644 index 0000000..b08a571 --- /dev/null +++ b/sim/testsuite/frv/ftino.cgs @@ -0,0 +1,53 @@ +# frv testcase for ftino +# mach: all + + .include "testutils.inc" + + start + + .global ftinev +ftinev: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_gr_immed 0,gr7 + + set_fcc 0x0 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x1 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x2 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x3 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x4 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x5 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x6 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x7 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x8 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x9 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xa 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xb 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xc 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xd 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xe 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xf 0 + ftino ; should branch to tbr + (128 + 4)*16 + pass +bad: + fail diff --git a/sim/testsuite/frv/ftio.cgs b/sim/testsuite/frv/ftio.cgs new file mode 100644 index 0000000..083c170 --- /dev/null +++ b/sim/testsuite/frv/ftio.cgs @@ -0,0 +1,112 @@ +# frv testcase for ftio $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftio +ftio: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftira.cgs b/sim/testsuite/frv/ftira.cgs new file mode 100644 index 0000000..9382b2b --- /dev/null +++ b/sim/testsuite/frv/ftira.cgs @@ -0,0 +1,114 @@ +# frv testcase for ftira $GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftira +ftira: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_fcc 0x0 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass diff --git a/sim/testsuite/frv/ftiu.cgs b/sim/testsuite/frv/ftiu.cgs new file mode 100644 index 0000000..adc40be --- /dev/null +++ b/sim/testsuite/frv/ftiu.cgs @@ -0,0 +1,100 @@ +# frv testcase for ftiu $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiu +ftiu: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_fcc 0x6 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_fcc 0xa 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_fcc 0xe 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftiue.cgs b/sim/testsuite/frv/ftiue.cgs new file mode 100644 index 0000000..3111434 --- /dev/null +++ b/sim/testsuite/frv/ftiue.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftiue $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiue +ftiue: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_fcc 0x6 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftiug.cgs b/sim/testsuite/frv/ftiug.cgs new file mode 100644 index 0000000..9e16f89 --- /dev/null +++ b/sim/testsuite/frv/ftiug.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftiug $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiug +ftiug: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftiuge.cgs b/sim/testsuite/frv/ftiuge.cgs new file mode 100644 index 0000000..bda587e --- /dev/null +++ b/sim/testsuite/frv/ftiuge.cgs @@ -0,0 +1,112 @@ +# frv testcase for ftiuge $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiuge +ftiuge: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftiul.cgs b/sim/testsuite/frv/ftiul.cgs new file mode 100644 index 0000000..ee5e2ba --- /dev/null +++ b/sim/testsuite/frv/ftiul.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftiul $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiul +ftiul: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_fcc 0xa 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftle.cgs b/sim/testsuite/frv/ftle.cgs new file mode 100644 index 0000000..4ffa760 --- /dev/null +++ b/sim/testsuite/frv/ftle.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftle $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftle +ftle: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftlg.cgs b/sim/testsuite/frv/ftlg.cgs new file mode 100644 index 0000000..a72f502 --- /dev/null +++ b/sim/testsuite/frv/ftlg.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftlg $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftlg +ftlg: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftlt.cgs b/sim/testsuite/frv/ftlt.cgs new file mode 100644 index 0000000..c934313 --- /dev/null +++ b/sim/testsuite/frv/ftlt.cgs @@ -0,0 +1,101 @@ +# frv testcase for ftlt $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftlt +ftlt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xa 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xb 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftne.cgs b/sim/testsuite/frv/ftne.cgs new file mode 100644 index 0000000..03b9857 --- /dev/null +++ b/sim/testsuite/frv/ftne.cgs @@ -0,0 +1,113 @@ +# frv testcase for ftne $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftne +ftne: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftno.cgs b/sim/testsuite/frv/ftno.cgs new file mode 100644 index 0000000..bada522 --- /dev/null +++ b/sim/testsuite/frv/ftno.cgs @@ -0,0 +1,54 @@ +# frv testcase for ftno +# mach: all + + .include "testutils.inc" + + start + + .global ftnev +ftnev: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_fcc 0x0 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x1 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x2 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x3 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x4 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x5 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x6 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x7 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x8 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x9 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xa 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xb 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xc 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xd 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xe 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xf 0 + ftno ; should branch to tbr + (128 + 4)*16 + pass +bad: + fail diff --git a/sim/testsuite/frv/fto.cgs b/sim/testsuite/frv/fto.cgs new file mode 100644 index 0000000..82035f4 --- /dev/null +++ b/sim/testsuite/frv/fto.cgs @@ -0,0 +1,113 @@ +# frv testcase for fto $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global fto +fto: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftra.cgs b/sim/testsuite/frv/ftra.cgs new file mode 100644 index 0000000..7754f69 --- /dev/null +++ b/sim/testsuite/frv/ftra.cgs @@ -0,0 +1,115 @@ +# frv testcase for ftra $GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftra +ftra: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_fcc 0x0 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass diff --git a/sim/testsuite/frv/ftu.cgs b/sim/testsuite/frv/ftu.cgs new file mode 100644 index 0000000..354423b --- /dev/null +++ b/sim/testsuite/frv/ftu.cgs @@ -0,0 +1,101 @@ +# frv testcase for ftu $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftu +ftu: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_fcc 0x6 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_fcc 0xa 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_fcc 0xe 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftue.cgs b/sim/testsuite/frv/ftue.cgs new file mode 100644 index 0000000..564bb30 --- /dev/null +++ b/sim/testsuite/frv/ftue.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftue $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftue +ftue: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_fcc 0x6 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftug.cgs b/sim/testsuite/frv/ftug.cgs new file mode 100644 index 0000000..cc6a405 --- /dev/null +++ b/sim/testsuite/frv/ftug.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftug $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftug +ftug: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftuge.cgs b/sim/testsuite/frv/ftuge.cgs new file mode 100644 index 0000000..7c04eaf --- /dev/null +++ b/sim/testsuite/frv/ftuge.cgs @@ -0,0 +1,113 @@ +# frv testcase for ftuge $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftuge +ftuge: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftul.cgs b/sim/testsuite/frv/ftul.cgs new file mode 100644 index 0000000..b45ebb3 --- /dev/null +++ b/sim/testsuite/frv/ftul.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftul $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftul +ftul: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_fcc 0xa 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/ftule.cgs b/sim/testsuite/frv/ftule.cgs new file mode 100644 index 0000000..4a93260 --- /dev/null +++ b/sim/testsuite/frv/ftule.cgs @@ -0,0 +1,113 @@ +# frv testcase for ftule $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftule +ftule: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/grloop.ms b/sim/testsuite/frv/grloop.ms new file mode 100644 index 0000000..0060963 --- /dev/null +++ b/sim/testsuite/frv/grloop.ms @@ -0,0 +1,13 @@ +# mach: all +# output: + + .global _start +_start: + setlo 0x0400,gr10 +loop: + addicc gr10,-1,gr10,icc0 + bne icc0,0,loop +; exit (0) + setlos #0,gr8 + setlos #1,gr7 + tira gr0,#0 diff --git a/sim/testsuite/frv/hello.ms b/sim/testsuite/frv/hello.ms new file mode 100644 index 0000000..117e4a6 --- /dev/null +++ b/sim/testsuite/frv/hello.ms @@ -0,0 +1,19 @@ +# mach: all +# output: Hello World!\n + + .global _start +_start: + +; write (hello world) + setlos #14,gr10 + sethi %hi(hello),gr9 + setlo %lo(hello),gr9 + setlos #1,gr8 + setlos #5,gr7 + tira gr0,#0 +; exit (0) + setlos #0,gr8 + setlos #1,gr7 + tira gr0,#0 + +hello: .ascii "Hello World!\r\n" diff --git a/sim/testsuite/frv/icei.cgs b/sim/testsuite/frv/icei.cgs new file mode 100644 index 0000000..aac925b --- /dev/null +++ b/sim/testsuite/frv/icei.cgs @@ -0,0 +1,15 @@ +# frv testcase for icei @(GRi,GRj),a +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global icei +icei: + ; Can't really test this because of SCACHE implementation + set_gr_addr icei,gr10 + icei @(gr10,gr0),1 + icei @(gr10,gr0),1 + + pass diff --git a/sim/testsuite/frv/ici.cgs b/sim/testsuite/frv/ici.cgs new file mode 100644 index 0000000..8aeacae --- /dev/null +++ b/sim/testsuite/frv/ici.cgs @@ -0,0 +1,39 @@ +# FRV testcase for ici @(GRi,GRj) +# mach: all + + .include "testutils.inc" + + start + + .global ici +ici: + set_gr_immed 1234,gr2 + set_spr_addr ok1,lr + bra testit + +ok1: + ; Change the first insn to set gr1 to 1235 + ; but don't invalidate the insn cache + ; should have no effect + set_gr_mem testit,gr10 + ori gr10,1,gr10 + set_mem_gr gr10,testit + set_gr_addr testit,gr10 + dcf @(gr10,gr0) ; flush data cache + set_spr_addr ok2,lr + bra testit + +ok2: ; Now invalidate the insn cache. The new insn should take effect + ici @(gr10,gr0) + set_gr_immed 1235,gr2 + set_spr_addr ok3,lr + bra testit + +ok3: + pass + +testit: + setlos 1234,gr1 + test_gr_gr gr1,gr2 + bralr + fail diff --git a/sim/testsuite/frv/icpl.cgs b/sim/testsuite/frv/icpl.cgs new file mode 100644 index 0000000..b86ba35 --- /dev/null +++ b/sim/testsuite/frv/icpl.cgs @@ -0,0 +1,39 @@ +# FRV testcase for icpl GRi,GRj,lock +# mach: all + + .include "testutils.inc" + + start + + .global icpl + ; keep this at least 64 bytes away from doit2 + bra icpl +doit1: add gr11,gr12,gr11 + bralr + +icpl: + or_spr_immed 0x80000000,hsr0 ; insn cache: enable + and_spr_immed 0xbfffffff,hsr0 ; data cache: disable + set_gr_immed 0,gr11 + set_gr_immed 1,gr12 + set_gr_immed 2,gr13 + + set_gr_addr doit1,gr10 + icpl gr10,gr0,0 ; preload insns at doit1 + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 + + set_gr_addr doit2,gr10 + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 + + set_spr_addr ok1,lr + bra doit1 +ok1: test_gr_immed 1,gr11 ; used preloaded add of 1 + + set_spr_addr ok2,lr + bra doit2 +ok2: test_gr_immed 3,gr11 ; used changed add of 2 + + pass + +doit2: add gr11,gr12,gr11 + bralr diff --git a/sim/testsuite/frv/icul.cgs b/sim/testsuite/frv/icul.cgs new file mode 100644 index 0000000..b112f41 --- /dev/null +++ b/sim/testsuite/frv/icul.cgs @@ -0,0 +1,53 @@ +# FRV testcase for icul $GRi +# mach: all + + .include "testutils.inc" + + start + + .global icul +icul: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the insn cache + set_gr_immed 0x70000,gr10 + set_bctrlr_0_0 gr10 + lock_insn_cache gr10 + + inc_gr_immed 0x1000,gr10 + set_bctrlr_0_0 gr10 + lock_insn_cache gr10 + + inc_gr_immed 0x1000,gr10 + set_bctrlr_0_0 gr10 + lock_insn_cache gr10 + + inc_gr_immed 0x1000,gr10 + set_bctrlr_0_0 gr10 + lock_insn_cache gr10 + + ; execute the pre-loaded insn + set_gr_immed 0x70000,gr10 + calll @(gr10,gr0) ; should come right back + inc_gr_immed 0x1000,gr10 + calll @(gr10,gr0) ; should come right back + inc_gr_immed 0x1000,gr10 + calll @(gr10,gr0) ; should come right back + inc_gr_immed 0x1000,gr10 + calll @(gr10,gr0) ; should come right back + + ; Now execute another insn which would have gone into set 0. + inc_gr_immed 0x1000,gr10 + set_bctrlr_0_0 gr10 + set_spr_immed 128,lcr + calll @(gr10,gr0) ; should come right back + + ; Now unlock one of the lines and do it again + set_gr_immed 0x71000,gr10 + icul gr10 + calll @(gr10,gr0) ; should come right back + + inc_gr_immed 0x3000,gr10 + calll @(gr10,gr0) ; should come right back + + pass diff --git a/sim/testsuite/frv/interrupts.exp b/sim/testsuite/frv/interrupts.exp new file mode 100644 index 0000000..e31533e --- /dev/null +++ b/sim/testsuite/frv/interrupts.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500 fr550 fr400" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/interrupts/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/frv/interrupts/Ipipe-fr400.cgs b/sim/testsuite/frv/interrupts/Ipipe-fr400.cgs new file mode 100644 index 0000000..dad9f0e --- /dev/null +++ b/sim/testsuite/frv/interrupts/Ipipe-fr400.cgs @@ -0,0 +1,35 @@ +# frv testcase +# mach: fr400 + + .include "testutils.inc" + + start + + .global Ipipe +Ipipe: + ; Clear the packing bit of the insn at 'pack:'. We can't + ; simply use '.p' because the assembler will catch the error. + set_gr_mem pack,gr10 + and_gr_immed 0x7fffffff,gr10 + set_mem_gr gr10,pack + set_gr_addr pack,gr10 + flush_data_cache gr10 + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x070,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_spr_addr ok0,lr + set_psr_et 1 + +bundle: add.p gr1,gr1,gr1 +pack: add gr2,gr2,gr2 +bad: add gr3,gr3,gr3 + fail +ok0: + test_spr_immed 1,esfr1 + test_spr_bits 0x3f,0,0xb,esr0 + test_spr_addr bundle,epcr0 + + pass diff --git a/sim/testsuite/frv/interrupts/Ipipe-fr500.cgs b/sim/testsuite/frv/interrupts/Ipipe-fr500.cgs new file mode 100644 index 0000000..b4dd770 --- /dev/null +++ b/sim/testsuite/frv/interrupts/Ipipe-fr500.cgs @@ -0,0 +1,35 @@ +# frv testcase +# mach: fr500 + + .include "testutils.inc" + + start + + .global Ipipe +Ipipe: + ; Clear the packing bit of the insn at 'pack:'. We can't + ; simply use '.p' because the assembler will catch the error. + set_gr_mem pack,gr10 + and_gr_immed 0x7fffffff,gr10 + set_mem_gr gr10,pack + set_gr_addr pack,gr10 + flush_data_cache gr10 + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x070,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_spr_addr ok0,lr + set_psr_et 1 + + add.p gr1,gr1,gr1 +pack: add gr2,gr2,gr2 +bad: add gr3,gr3,gr3 + fail +ok0: + test_spr_immed 1,esfr1 + test_spr_bits 0x3f,0,0xb,esr0 + test_spr_addr bad,epcr0 + + pass diff --git a/sim/testsuite/frv/interrupts/badalign-fr550.cgs b/sim/testsuite/frv/interrupts/badalign-fr550.cgs new file mode 100644 index 0000000..6c0369b --- /dev/null +++ b/sim/testsuite/frv/interrupts/badalign-fr550.cgs @@ -0,0 +1,42 @@ +# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) +# mach: fr550 + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x100,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0xdeadbeef,gr17 + set_gr_immed 0,gr15 + inc_gr_immed 2,sp ; out of alignment + + test_spr_bits 1,0,0,isr ; ISR.EMAM always clear (not used) + sti gr17,@(sp,0) ; no exception + sti gr17,@(sp,4) ; no exception + ldi @(sp,0),gr18 ; stored at unaligned address + test_gr_immed 0xdeadbeef,gr18 + ldi @(sp,0),gr19 ; no exception + test_gr_immed 0xdeadbeef,gr19 + + and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM + sti gr17,@(sp,0) ; misaligned -- no exception + test_gr_immed 0,gr15 + + set_gr_gr sp,gr20 + set_gr_immed 1,gr21 + set_gr_immed 0x10101010,gr10 + nop.p + ldu @(sp,gr21),gr10 ; misaligned read no exception + test_gr_immed 0,gr15 ; handler was not called + test_gr_immed 0xadbeefde,gr10 ; gr10 updated + test_gr_immed 1,gr21 ; gr21 not updated + inc_gr_immed 1,gr20 + test_gr_gr gr20,sp ; sp updated + + pass diff --git a/sim/testsuite/frv/interrupts/badalign.cgs b/sim/testsuite/frv/interrupts/badalign.cgs new file mode 100644 index 0000000..b866021 --- /dev/null +++ b/sim/testsuite/frv/interrupts/badalign.cgs @@ -0,0 +1,73 @@ +# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) +# mach: fr500 frv + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x100,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + set_gr_immed 0xdeadbeef,gr17 + set_gr_immed 0,gr15 + inc_gr_immed 2,sp ; out of alignment + + test_spr_bits 1,0,1,isr ; mem_address_not_aligned is masked + sti gr17,@(sp,0) ; no exception + ldi @(sp,-2),gr18 ; stored at aligned address + test_gr_immed 0xdeadbeef,gr18 + ldi @(sp,0),gr19 ; no exception + test_gr_immed 0xdeadbeef,gr19 + + and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM + set_gr_addr bad1,gr16 +bad1: sti gr17,@(sp,0) ; misaligned write in slot I1 + test_gr_immed 1,gr15 + + set_gr_addr bad3,gr16 + set_gr_gr sp,gr20 + set_gr_immed 1,gr21 + set_gr_immed 0x10101010,gr10 +bad2: nop.p +bad3: ldu @(sp,gr21),gr10 ; misaligned read in slot I2 + test_gr_immed 2,gr15 ; handler was called + test_gr_immed 0x10101010,gr10 ; gr10 not updated + test_gr_immed 1,gr21 ; gr21 not updated + inc_gr_immed 1,gr20 + test_gr_gr gr20,sp ; sp updated + + pass + +; exception handler +ok1: + cmpi gr15,0,icc0 + bne icc0,0,load + ; handle interrupt on store + test_spr_immed 0x100,esfr1 ; esr8 is active + test_spr_gr epcr8,gr16 + test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid + test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set + test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set + test_spr_gr ear8,sp + test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set + test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3 + test_spr_gr edr3,gr17 ; edr3 is set + bra ret +load: + ; handle interrupt on load + test_spr_immed 0x200,esfr1 ; esr9 is active + test_spr_gr epcr9,gr16 + test_spr_bits 0x0001,0,0x1,esr9 ; esr9 is valid + test_spr_bits 0x003e,1,0xb,esr9 ; esr9.ec is set + test_spr_bits 0x0800,11,0x1,esr9 ; esr9.eav is set + test_spr_gr ear9,sp + test_spr_bits 0x1000,12,0x0,esr9 ; esr9.edv is not set +ret: + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/interrupts/compound-fr550.cgs b/sim/testsuite/frv/interrupts/compound-fr550.cgs new file mode 100644 index 0000000..7cd2278 --- /dev/null +++ b/sim/testsuite/frv/interrupts/compound-fr550.cgs @@ -0,0 +1,54 @@ +# frv testcase to generate compound exception +# mach: fr550 + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x200,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception + set_psr_et 1 + + set_gr_immed 0,gr15 + set_fr_iimmed 0x7f7f,0xffff,fr0 + set_fr_iimmed 0x0000,0x0000,fr1 + + and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned + set_gr_addr dividef,gr16 + set_gr_addr dividei,gr17 + set_gr_immed 0xdeadbeef,gr8 + inc_gr_immed 2,sp ; misalign +store: sti.p gr8,@(sp,0) ; misaligned - no exception +dividef:fdivs.p fr0,fr1,fr2 ; fp_exception +dividei:sdiv gr1,gr0,gr1 ; division exception + test_gr_immed 1,gr15 + + pass + +; exception handler +ok1: + ; check fp_exception + test_spr_immed 0x5,esfr1 ; esr2 and esr0 are active + test_spr_gr epcr2,gr16 + test_spr_bits 0x0001,0,0x1,esr2 ; esr2 is valid + test_spr_bits 0x003e,1,0xd,esr2 ; esr2.ec is set + test_spr_bits 0x0800,11,0x0,esr2 ; esr2.eav is clear + + ; check on fp_exception + test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear + + ; check interrupt on dividei + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/interrupts/compound.cgs b/sim/testsuite/frv/interrupts/compound.cgs new file mode 100644 index 0000000..2fd928e --- /dev/null +++ b/sim/testsuite/frv/interrupts/compound.cgs @@ -0,0 +1,66 @@ +# frv testcase to generate compound exception +# mach: fr500 frv + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x200,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception + set_psr_et 1 + + set_gr_immed 0,gr15 + set_fr_iimmed 0x7f7f,0xffff,fr0 + set_fr_iimmed 0x0000,0x0000,fr1 + + and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned + set_gr_addr store,gr16 + set_gr_addr dividei,gr17 + set_gr_immed 0xdeadbeef,gr8 + inc_gr_immed 2,sp ; misalign +store: sti.p gr8,@(sp,0) ; misaligned write +dividef:fdivs.p fr0,fr1,fr2 ; fp_exception +dividei:sdiv gr1,gr0,gr1 ; division exception + test_gr_immed 1,gr15 + + pass + +; exception handler +ok1: + ; check interrupt on store + test_spr_immed 0x102,esfr1 ; esr8 and esr1 are active + test_spr_gr epcr8,gr16 + test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid + test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set + test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set + test_spr_gr ear8,sp + test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set + test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3 + test_spr_gr edr3,gr8 ; edr3 is set + + ; check on fp_exception + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear + + test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set + test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set + test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set + test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set + test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set + test_spr_immed 0x05e40241,fqop2 ; fq2.opc + + ; check interrupt on dividei + test_spr_gr epcr1,gr17 + test_spr_bits 0x0001,0,0x1,esr1 ; esr1 is valid + test_spr_bits 0x003e,1,0x13,esr1 ; esr1.ec is set + + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/interrupts/data_store_error-fr550.cgs b/sim/testsuite/frv/interrupts/data_store_error-fr550.cgs new file mode 100644 index 0000000..3924adc --- /dev/null +++ b/sim/testsuite/frv/interrupts/data_store_error-fr550.cgs @@ -0,0 +1,53 @@ +# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) +# mach: fr550 +# sim(fr550): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010 + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x140,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + + set_spr_addr ok0,lr + set_gr_immed 0,gr16 + + set_gr_immed 0xdeadbeef,gr15 + set_gr_addr 0xfeff0600,gr17 +bad1: sti gr15,@(gr17,0) ; no interrupt + test_gr_immed 0,gr16 + + set_gr_immed 0xbeefdead,gr15 + set_gr_addr 0xfeff7ffc,gr17 +bad2: sti gr15,@(gr17,0) ; no interrupt + test_gr_immed 0,gr16 + + set_gr_immed 0xbeefbeef,gr15 + set_gr_addr 0xfe800000,gr17 +bad3: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 1,gr16 + + set_gr_immed 0xdeaddead,gr15 + set_gr_addr 0xfefefffc,gr17 +bad4: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 2,gr16 + + sti gr0,@(sp,0) ; no interrupt + test_gr_immed 2,gr16 + + pass +ok0: + ; check interrupts + test_spr_immed 0x4000,esfr1 ; esr14 is active + test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid + test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set + test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set + + addi gr16,1,gr16 + rett 0 + fail diff --git a/sim/testsuite/frv/interrupts/data_store_error.cgs b/sim/testsuite/frv/interrupts/data_store_error.cgs new file mode 100644 index 0000000..b967d0a --- /dev/null +++ b/sim/testsuite/frv/interrupts/data_store_error.cgs @@ -0,0 +1,53 @@ +# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) +# mach: fr500 +# sim(fr500): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010 + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x140,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + + set_spr_addr ok0,lr + set_gr_immed 0,gr16 + + set_gr_immed 0xdeadbeef,gr15 + set_gr_addr 0xfeff0600,gr17 +bad1: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 1,gr16 + + set_gr_immed 0xbeefdead,gr15 + set_gr_addr 0xfeff7ffc,gr17 +bad2: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 2,gr16 + + set_gr_immed 0xbeefbeef,gr15 + set_gr_addr 0xfe800000,gr17 +bad3: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 3,gr16 + + set_gr_immed 0xdeaddead,gr15 + set_gr_addr 0xfefefffc,gr17 +bad4: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 4,gr16 + + sti gr0,@(sp,0) ; no interrupt + test_gr_immed 4,gr16 + + pass +ok0: + ; check interrupts + test_spr_immed 0x4000,esfr1 ; esr14 is active + test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid + test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set + test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set + + addi gr16,1,gr16 + rett 0 + fail diff --git a/sim/testsuite/frv/interrupts/fp_exception-fr550.cgs b/sim/testsuite/frv/interrupts/fp_exception-fr550.cgs new file mode 100644 index 0000000..5d1c3f5 --- /dev/null +++ b/sim/testsuite/frv/interrupts/fp_exception-fr550.cgs @@ -0,0 +1,185 @@ +# frv testcase to generate fp_exception +# mach: fr550 + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global align +align: + ; clear the packing bit if the insn at 'pack:'. We can't simply use + ; '.p' because the assembler will catch the error. + set_gr_mem pack,gr10 + and_gr_immed 0x7fffffff,gr10 + set_mem_gr gr10,pack + set_gr_addr pack,gr10 + flush_data_cache gr10 + + ; Make the the source register number odd at badst. We can't simply + ; code an odd register number because the assembler will catch the + ; error. + set_gr_mem badst,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,badst + set_gr_addr badst,gr10 + flush_data_cache gr10 + + ; Make the the dest register number odd at badld. We can't simply + ; code an odd register number because the assembler will catch the + ; error. + set_gr_mem badld,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,badld + set_gr_addr badld,gr10 + flush_data_cache gr10 + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x070,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + inc_gr_immed 0x060,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + inc_gr_immed -4,sp ; for alignment + + set_gr_immed 0,gr20 ; PC increment + set_gr_immed 0,gr15 + + set_spr_addr ok3,lr + set_gr_immed 4,gr20 ; PC increment +badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 + test_gr_immed 1,gr15 + + set_spr_addr ok4,lr + set_gr_immed 8,gr20 ; PC increment + nop.p +badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 + test_gr_immed 2,gr15 + + set_spr_addr ok5,lr + set_gr_immed 20,gr20 ; PC increment + fnegs.p fr9,fr9 + fnegs.p fr9,fr10 + fnegs.p fr9,fr11 +pack: fnegs fr10,fr12 + fnegs fr10,fr13 ; packing violation + test_gr_immed 3,gr15 + + set_spr_addr ok1,lr + set_gr_immed 4,gr20 ; PC increment +bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented) + test_gr_immed 4,gr15 + + and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception + set_fr_iimmed 0x7f7f,0xffff,fr0 + set_fr_iimmed 0x0000,0x0000,fr1 + fdivs fr0,fr1,fr2 ; div/0 -- no exception + test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set + test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set + test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear + + set_spr_addr ok2,lr + set_gr_immed 0,gr20 ; PC increment + or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception + set_fr_iimmed 0xdead,0xbeef,fr2 +div0: fdivs fr0,fr1,fr2 ; fp_exception - div/0 + test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated + test_gr_immed 5,gr15 + + and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception + fsqrts fr32,fr2 ; inexact -- no exception + test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set + test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear + + set_fr_fr fr2,fr3 ; sqrt 2 + set_fr_iimmed 0xdead,0xbeef,fr2 + set_spr_addr ok6,lr + or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception +inxt1: fsqrts fr32,fr2 ; fp_exception - inexact + test_gr_immed 6,gr15 ; handler called + test_fr_fr fr2,fr3 ; fr2 updated + + set_fr_iimmed 0xdead,0xbeef,fr2 + set_spr_addr ok7,lr +inxt2: fsqrts fr32,fr2 ; fp_exception - inexact again + test_gr_immed 7,gr15 ; handler called + test_fr_fr fr2,fr3 ; fr2 updated + + pass + +; exception handler 1 -- illegal_instruction: bad insn +ok1: + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set + test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set + bra ret + +; exception handler 2 - fp_exception: divide by 0 +ok2: + test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set + + test_spr_immed 4,esfr1 ; esr2 active + test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set + test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set + test_spr_addr div0,epcr2 ; epcr2 is set + bra ret + +; exception handler 3 - illegal_instruction: register exception +ok3: + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set + test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set + bra ret + +; exception handler 4 - illegal_instruction: register exception +ok4: + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set + test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set + bra ret + +; exception handler 5 - illegal_instruction: sequence violation +ok5: + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set + test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set + bra ret + +; exception handler 6 - fp_exception: inexact +ok6: + test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set + + test_spr_immed 4,esfr1 ; esr2 active + test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set + test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set + test_spr_addr inxt1,epcr2 ; epcr2 is set + bra ret + +; exception handler 7 - fp_exception: inexact again +ok7: + test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set + + test_spr_immed 4,esfr1 ; esr2 active + test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set + test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set + test_spr_addr inxt2,epcr2 ; epcr2 is set + bra ret + +ret: + inc_gr_immed 1,gr15 + movsg pcsr,gr60 + add gr60,gr20,gr60 + movgs gr60,pcsr + rett 0 + fail + diff --git a/sim/testsuite/frv/interrupts/fp_exception.cgs b/sim/testsuite/frv/interrupts/fp_exception.cgs new file mode 100644 index 0000000..0109b53 --- /dev/null +++ b/sim/testsuite/frv/interrupts/fp_exception.cgs @@ -0,0 +1,209 @@ +# frv testcase to generate fp_exception +# mach: fr500 + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global align +align: + ; clear the packing bit if the insn at 'pack:'. We can't simply use + ; '.p' because the assembler will catch the error. + set_gr_mem pack,gr10 + and_gr_immed 0x7fffffff,gr10 + set_mem_gr gr10,pack + set_gr_addr pack,gr10 + flush_data_cache gr10 + + ; Make the the source register number odd at badst. We can't simply + ; code an odd register number because the assembler will catch the + ; error. + set_gr_mem badst,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,badst + set_gr_addr badst,gr10 + flush_data_cache gr10 + + ; Make the the dest register number odd at ld. We can't simply + ; code an odd register number because the assembler will catch the + ; error. + set_gr_mem badld,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,badld + set_gr_addr badld,gr10 + flush_data_cache gr10 + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x070,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + inc_gr_immed 0x060,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + inc_gr_immed -4,sp ; for alignment + + set_gr_immed 0,gr20 ; PC increment + set_gr_immed 0,gr15 + + set_spr_addr ok3,lr +badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 + test_gr_immed 1,gr15 + + set_spr_addr ok4,lr + nop.p +badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 + test_gr_immed 2,gr15 + + set_spr_addr ok5,lr + fnegs.p fr9,fr9 +pack: fnegs fr10,fr10 + fnegs fr10,fr11 ; packing violation + test_gr_immed 3,gr15 + + set_spr_addr ok1,lr + set_gr_immed 4,gr20 ; PC increment +bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented) + test_gr_immed 4,gr15 + + and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception + set_fr_iimmed 0x7f7f,0xffff,fr0 + set_fr_iimmed 0x0000,0x0000,fr1 + fdivs fr0,fr1,fr2 ; div/0 -- no exception + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set + test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set + test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear + and_spr_immed 0xffefffff,fsr0 ; Clear fsr0.qne + + set_spr_addr ok2,lr + set_gr_immed 0,gr20 ; PC increment + or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception + set_fr_iimmed 0xdead,0xbeef,fr2 + fdivs fr0,fr1,fr2 ; fp_exception - div/0 + test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated + test_gr_immed 5,gr15 + + and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception + fsqrts fr32,fr2 ; inexact -- no exception + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set + test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear + + set_fr_fr fr2,fr3 ; sqrt 2 + set_fr_iimmed 0xdead,0xbeef,fr2 + set_spr_addr ok6,lr + or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception + fsqrts fr32,fr2 ; fp_exception - inexact + test_gr_immed 6,gr15 ; handler called + test_fr_fr fr2,fr3 ; fr2 updated + + set_fr_iimmed 0xdead,0xbeef,fr2 + set_spr_addr ok7,lr + fsqrts fr32,fr2 ; fp_exception - inexact again + test_gr_immed 7,gr15 ; handler called + test_fr_fr fr2,fr3 ; fr2 updated + + pass + +; exception handler 1 -- bad insn +ok1: + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set + test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set + test_spr_addr bad,epcr0 + bra ret + +; exception handler 2 - fp_exception: divide by 0 +ok2: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set + + test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set + test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set + test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set + test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set + test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set + test_spr_immed 0x85e40241,fqop2 ; fq2.opc + bra ret + +; exception handler 3 - fp_exception: register exception +ok3: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear + + test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set + test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set + test_spr_bits 0x380,7,0x6,fqst2 ; fq2.ftt is set + test_spr_bits 0x7e,1,0x0,fqst2 ; fq2.cexc is set + test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set + test_spr_immed 0x83581000,fqop2 ; fq2.opc + bra ret + +; exception handler 4 - fp_exception: another register exception +ok4: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear + + test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set + test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set + test_spr_bits 0x380,7,0x6,fqst3 ; fq3.ftt is set + test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set + test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set + test_spr_immed 0x92ec1000,fqop3 ; fq3.opc + bra ret + +; exception handler 5 - fp_exception: sequence violation +ok5: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x4,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear + + test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set + test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set + test_spr_bits 0x380,7,0x4,fqst3 ; fq3.ftt is set + test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set + test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set + test_spr_immed 0x97e400ca,fqop3 ; fq3.opc + bra ret + +; exception handler 6 - fp_exception: inexact +ok6: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set + + test_spr_bits 0x80000000,31,0x0,fqst0 ; fq0.miv is set + test_spr_bits 0x18000,15,0x0,fqst0 ; fq0.sie is set + test_spr_bits 0x380,7,0x1,fqst0 ; fq0.ftt is set + test_spr_bits 0x7e,1,0x2,fqst0 ; fq0.cexc is set + test_spr_bits 0x1,0,0x1,fqst0 ; fq0.valid is set + test_spr_immed 0x85e40160,fqop0 ; fq0.opc + bra ret + +; exception handler 7 - fp_exception: inexact again +ok7: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set + + test_spr_bits 0x80000000,31,0x0,fqst1 ; fq1.miv is set + test_spr_bits 0x18000,15,0x0,fqst1 ; fq1.sie is set + test_spr_bits 0x380,7,0x1,fqst1 ; fq1.ftt is set + test_spr_bits 0x7e,1,0x2,fqst1 ; fq1.cexc is set + test_spr_bits 0x1,0,0x1,fqst1 ; fq1.valid is set + test_spr_immed 0x85e40160,fqop1 ; fq1.opc + bra ret + +ret: + inc_gr_immed 1,gr15 + movsg pcsr,gr60 + add gr60,gr20,gr60 + movgs gr60,pcsr + rett 0 + fail + diff --git a/sim/testsuite/frv/interrupts/illinsn.cgs b/sim/testsuite/frv/interrupts/illinsn.cgs new file mode 100644 index 0000000..fc44a8f --- /dev/null +++ b/sim/testsuite/frv/interrupts/illinsn.cgs @@ -0,0 +1,38 @@ +# FRV testcase +# mach: fr500 fr550 fr400 + + .include "testutils.inc" + + start + + .global tra +tra: + and_spr_immed 0x3fffffff,hsr0 ; no caches enabled + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x070,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + inc_gr_immed 0x790,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_psr_et 1 + set_spr_addr ok0,lr + + set_gr_addr ill1,gr7 + set_mem_immed 0x81f80000,gr7 ; unknown opcode: 7E +ill1: tira gr0,0 ; should be overridden +ill2: nop ; also illegal, but prev has priority +bad0: fail + + ; check interrupt +ok0: test_spr_addr ill1,pcsr + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3f,0,0xb,esr0 + movsg psr,gr28 + srli gr28,28,gr28 + subicc gr28,0x3,gr0,icc3 ; is fr550? + beq icc3,0,no_epcr + test_spr_addr ill1,epcr0 +no_epcr: + pass diff --git a/sim/testsuite/frv/interrupts/insn_access_error-fr550.cgs b/sim/testsuite/frv/interrupts/insn_access_error-fr550.cgs new file mode 100644 index 0000000..6c49299 --- /dev/null +++ b/sim/testsuite/frv/interrupts/insn_access_error-fr550.cgs @@ -0,0 +1,44 @@ +# frv testcase to generate insn_access_error interrupt +# mach: fr550 +# sim: --memory-region 0xfe800000,0x7f0500 --memory-region 0xfeff0540,0xfb00 + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x020,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + + set_spr_addr handler,lr + set_gr_immed 0,gr16 + + set_gr_addr ok0,gr8 + set_gr_addr 0xfe800000,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok0: + test_gr_immed 1,gr16 + + set_gr_addr ok1,gr8 + set_gr_addr 0xfefffffc,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok1: + test_gr_immed 2,gr16 + + pass +handler: + ; check interrupts + test_spr_immed 0x1,esfr1 ; esr0 is active +; test_spr_gr epcr0,gr17 ; epcr0 is not used + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set + + addi gr16,1,gr16 + movgs gr8,pcsr + rett 0 + fail diff --git a/sim/testsuite/frv/interrupts/insn_access_error.cgs b/sim/testsuite/frv/interrupts/insn_access_error.cgs new file mode 100644 index 0000000..11a9eaf --- /dev/null +++ b/sim/testsuite/frv/interrupts/insn_access_error.cgs @@ -0,0 +1,56 @@ +# frv testcase to generate insn_access_error interrupt +# mach: fr500 fr400 +# sim: --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0040 + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x020,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + + set_spr_addr handler,lr + set_gr_immed 0,gr16 + + set_gr_addr ok0,gr8 + set_gr_addr 0xfeff0600,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok0: + test_gr_immed 1,gr16 + + set_gr_addr ok1,gr8 + set_gr_addr 0xfeff7ffc,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok1: + test_gr_immed 2,gr16 + + set_gr_addr ok2,gr8 + set_gr_addr 0xfe800000,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok2: + test_gr_immed 3,gr16 + + set_gr_addr ok3,gr8 + set_gr_addr 0xfefefffc,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok3: + test_gr_immed 4,gr16 + + pass +handler: + ; check interrupts + test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr17 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set + + addi gr16,1,gr16 + movgs gr8,pcsr + rett 0 + fail diff --git a/sim/testsuite/frv/interrupts/mp_exception.cgs b/sim/testsuite/frv/interrupts/mp_exception.cgs new file mode 100644 index 0000000..3203acc --- /dev/null +++ b/sim/testsuite/frv/interrupts/mp_exception.cgs @@ -0,0 +1,289 @@ +# frv testcase for mp_exception +# mach: fr500 fr550 frv +# xerror: + +# This program no longer assembles because the assembler +# now detects the unaligned registers. For this reason +# this test is now marked as "xerror" and prints the +# expected message "fail" + + .include "testutils.inc" + + start + + .global mp_exception +mpx: +.if 1 + fail +.else + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mcmpsh fr10,fr11,fcc1 ; mp_exception: cr-not-aligned + test_spr_bits 0x7000,12,3,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf is set + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mcmpsh.p fr10,fr11,fcc0 ; no exception + mcmpsh fr10,fr11,fcc2 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mmulhs.p fr10,fr11,acc3 ; no exception + mmulhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mmulhu fr10,fr11,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mmulxhs.p fr10,fr11,acc3 ; no exception + mmulxhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mmulxhu fr10,fr11,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mmachs.p fr10,fr11,acc3 ; no exception + mmachs fr10,fr11,acc1 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mmachu fr10,fr11,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqaddhss.p fr10,fr12,fr17 ; mp_exception: register-not-aligned + mqaddhss fr10,fr12,fr14 ; no exception + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqaddhss.p fr10,fr12,fr14 ; no exception + mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqaddhss.p fr19,fr12,fr14 ; mp_exception: register-not-aligned + mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqaddhss fr10,fr12,fr14 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqmulhs.p fr10,fr11,acc3 ; no exception + mqmulhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmulhu fr10,fr11,acc0 ; mp_exception: register_not_aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmulhu fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqmulxhs.p fr10,fr11,acc3 ; no exception + mqmulxhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmulxhu fr10,fr11,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmulxhu fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqmachs.p fr10,fr12,acc3 ; no exception + mqmachs fr10,fr12,acc2 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned + mqmachu fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmachu.p fr10,fr12,acc0 ; no exception + mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned + mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmachu fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqcpxrs.p fr10,fr12,acc0 ; no exception + mqcpxrs fr10,fr12,acc1 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned + mqcpxru fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqcpxru.p fr10,fr12,acc0 ; no exception + mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned + mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqcpxru fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + pass +.endif diff --git a/sim/testsuite/frv/interrupts/privileged_instruction.cgs b/sim/testsuite/frv/interrupts/privileged_instruction.cgs new file mode 100644 index 0000000..9996236 --- /dev/null +++ b/sim/testsuite/frv/interrupts/privileged_instruction.cgs @@ -0,0 +1,54 @@ +# frv testcase to generate privileged_instruction interrupt +# mach: frv + + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x060,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + and_spr_immed 0xfffffffb,psr ; clear psr.s + + set_spr_addr handler,lr + set_gr_immed 0,gr16 + + set_gr_addr bad1,gr17 +bad1: rett 0 ; cause interrupt + test_gr_immed 1,gr16 + set_gr_addr bad2,gr17 +bad2: rei 0 ; cause interrupt + test_gr_immed 2,gr16 + set_gr_addr bad3,gr17 +bad3: witlb gr0,@(gr0,gr0) ; cause interrupt + test_gr_immed 3,gr16 + set_gr_addr bad4,gr17 +bad4: wdtlb gr0,@(gr0,gr0) ; cause interrupt + test_gr_immed 4,gr16 + set_gr_addr bad5,gr17 +bad5: itlbi @(gr0,gr0) ; cause interrupt + test_gr_immed 5,gr16 + set_gr_addr bad6,gr17 +bad6: dtlbi @(gr0,gr0) ; cause interrupt + test_gr_immed 6,gr16 + + pass +handler: + ; check interrupts + test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr17 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x4,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set + + addi gr16,1,gr16 + movsg pcsr,gr8 + addi gr8,4,gr8 + movgs gr8,pcsr + rett 0 + fail diff --git a/sim/testsuite/frv/interrupts/regalign.cgs b/sim/testsuite/frv/interrupts/regalign.cgs new file mode 100644 index 0000000..afa09b5 --- /dev/null +++ b/sim/testsuite/frv/interrupts/regalign.cgs @@ -0,0 +1,130 @@ +# frv testcase to generate interrupts for bad register alignment +# mach: frv + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x080,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + inc_gr_immed 0x050,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + + ; Make the the register number odd at bad[1-4], bad9 and bada. + ; We can't simply code an odd register number because the assembler + ; will catch the error. + set_gr_mem bad1,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,bad1 + set_gr_addr bad1,gr10 + flush_data_cache gr10 + set_gr_mem bad2,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,bad2 + set_gr_addr bad2,gr10 + flush_data_cache gr10 + set_gr_mem bad3,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,bad3 + set_gr_addr bad3,gr10 + flush_data_cache gr10 + set_gr_mem bad4,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,bad4 + set_gr_addr bad4,gr10 + flush_data_cache gr10 + set_gr_mem bad9,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,bad9 + set_gr_addr bad9,gr10 + flush_data_cache gr10 + set_gr_mem bada,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,bada + set_gr_addr bada,gr10 + flush_data_cache gr10 + + set_gr_immed 4,gr20 ; PC increment + set_gr_immed 0,gr15 + inc_gr_immed -12,sp ; for memory alignment + + set_gr_addr bad1,gr17 +bad1: stdi gr0,@(sp,0) ; misaligned reg + test_gr_immed 1,gr15 + + set_gr_addr bad2,gr17 +bad2: lddi @(sp,0),gr8 ; misaligned reg + test_gr_immed 2,gr15 + + set_gr_addr bad3,gr17 +bad3: stdc cpr0,@(sp,gr0) ; misaligned reg + test_gr_immed 3,gr15 + + set_gr_addr bad4,gr17 +bad4: lddc @(sp,gr0),cpr8 ; misaligned reg + test_gr_immed 4,gr15 + + set_gr_addr bad5,gr17 +bad5: stqi gr2,@(sp,0) ; misaligned reg + test_gr_immed 5,gr15 + + set_gr_addr bad6,gr17 +bad6: ldqi @(sp,0),gr10 ; misaligned reg + test_gr_immed 6,gr15 + + set_gr_addr bad7,gr17 +bad7: stqc cpr2,@(sp,gr0) ; misaligned reg + test_gr_immed 7,gr15 + + set_gr_addr bad8,gr17 +bad8: ldqc @(sp,gr0),cpr10 ; misaligned reg + test_gr_immed 8,gr15 + + set_gr_immed 0,gr20 ; PC increment + set_gr_addr bad9,gr17 +bad9: stdfi fr0,@(sp,0) ; misaligned reg + test_gr_immed 9,gr15 + + set_gr_addr bada,gr17 +bada: lddfi @(sp,0),fr8 ; misaligned reg + test_gr_immed 10,gr15 + + set_gr_addr badb,gr17 +badb: stqfi fr2,@(sp,0) ; misaligned reg + test_gr_immed 11,gr15 + + set_gr_addr badc,gr17 +badc: ldqfi @(sp,0),fr10 ; misaligned reg + test_gr_immed 12,gr15 + + pass + +; exception handler +ok1: + cmpi gr20,0,icc0 + beq icc0,0,float + + ; check register_exception + test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr17 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0xc,esr0 ; esr0.ec is set + test_spr_bits 0x00c0,6,0x1,esr0 ; esr0.rec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set + movsg pcsr,gr60 + add gr60,gr20,gr60 + movgs gr60,pcsr + bra ret +float: + ; check fp_exception + test_spr_immed 0,esfr1 ; no esr's active +ret: + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/interrupts/reset.cgs b/sim/testsuite/frv/interrupts/reset.cgs new file mode 100644 index 0000000..ff2035c --- /dev/null +++ b/sim/testsuite/frv/interrupts/reset.cgs @@ -0,0 +1,81 @@ +# frv testcase to generate reset interrupts +# mach: fr500 fr550 fr400 +# sim: --memory-region 0xff000000,64 + + .include "testutils.inc" + + start + + .global reset +reset: + and_spr_immed 0xfffffffb,psr ; turn off PSR.S + set_gr_immed 0xfeff0500,gr10 ; address of reset register + set_spr_immed 0x7fffffff,lcr + set_bctrlr_0_0 gr0 + +; Can't recover from hardware interrupt with enough state intact to verify it +; set_spr_addr ok1,lr +; set_mem_immed 0x3,gr10 ; cause hardware reset +; dcf @(gr10,gr0) ; Wait for store to happen +; fail +; +;ok1: ; reset should branch to reset address which should then branch here +; test_mem_immed 0x00000200,gr10 +; set_spr_addr ok2,lr +; set_mem_immed 0x2,gr10 ; cause hardware reset +; dcf @(gr10,gr0) ; Wait for store to happen +; fail +; +ok2: ; reset should branch to reset address which should then branch here +; test_mem_immed 0x00000200,gr10 + set_spr_addr ok3,lr + set_mem_immed 0x1,gr10 ; cause software reset + dcf @(gr10,gr0) ; Wait for store to happen + fail + +ok3: ; reset should branch to reset address which should then branch here + test_mem_immed 0x00000100,gr10 + test_spr_bits 0x4,2,1,psr ; psr.s is set + test_spr_bits 0x2,1,0,psr ; psr.ps not set + set_spr_addr bad,lr + set_mem_immed 0x0,gr10 ; no reset + test_mem_immed 0x0,gr10 + + ; now retest with HSR0.SA set + set_mem_immed 0,gr0 + set_gr_addr 0xff000000,gr11 + set_bctrlr_0_0 gr11 + or_spr_immed 0x00001000,hsr0 ; set HSR0.SA + +; Can't recover from hardware interrupt with enough state intact to verify it +; set_spr_addr ok4,lr +; dcf @(gr10,gr0) ; Wait for store to happen +; set_mem_immed 0x3,gr10 ; cause hardware reset +; fail +; +;ok4: ; reset should branch to reset address which should then branch here +; test_mem_immed 0x00000200,gr10 +; set_spr_addr ok5,lr +; set_mem_immed 0x2,gr10 ; cause hardware reset +; dcf @(gr10,gr0) ; Wait for store to happen +; fail +; +ok5: ; reset should branch to reset address which should then branch here +; test_mem_immed 0x00000200,gr10 + set_spr_addr ok6,lr + set_mem_immed 0x1,gr10 ; cause software reset + dcf @(gr10,gr0) ; Wait for store to happen + fail + +ok6: ; reset should branch to reset address which should then branch here + test_mem_immed 0x00000100,gr10 + test_spr_bits 0x4,2,1,psr ; psr.s is set + test_spr_bits 0x2,1,1,psr ; psr.ps is set + set_spr_addr bad,lr + set_mem_immed 0x0,gr10 ; no reset + test_mem_immed 0x0,gr10 + + pass + +bad: ; Should never get here + fail diff --git a/sim/testsuite/frv/interrupts/shadow_regs.cgs b/sim/testsuite/frv/interrupts/shadow_regs.cgs new file mode 100644 index 0000000..ee6bea4 --- /dev/null +++ b/sim/testsuite/frv/interrupts/shadow_regs.cgs @@ -0,0 +1,205 @@ +# FRV testcase for handling of shadow registers SR0-SR4 +# mach: frv + + .include "testutils.inc" + + start + + .global tra +tra: + test_spr_bits 0x800,11,1,psr ; PSR.ESR set + test_spr_bits 0x4,2,1,psr ; PSR.S set + + ; Set up exception handler for later + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + set_spr_immed 128,lcr + set_psr_et 1 + + set_gr_immed 0x11111111,gr4 ; SGR4-7 + set_gr_immed 0x22222222,gr5 + set_gr_immed 0x33333333,gr6 + set_gr_immed 0x44444444,gr7 + set_spr_immed 0x55555555,sr0 ; UGR4-7 + set_spr_immed 0x66666666,sr1 + set_spr_immed 0x77777777,sr2 + set_spr_immed 0x88888888,sr3 + + and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + set_spr_immed 0x55555555,sr0 ; SGR4-7 + set_spr_immed 0x66666666,sr1 + set_spr_immed 0x77777777,sr2 + set_spr_immed 0x88888888,sr3 + test_gr_immed 0x55555555,gr4 ; SGR4-7 + test_gr_immed 0x66666666,gr5 + test_gr_immed 0x77777777,gr6 + test_gr_immed 0x88888888,gr7 + test_spr_immed 0x55555555,sr0 ; SGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + set_gr_immed 0x11111111,gr4 ; SGR4-7 + set_gr_immed 0x22222222,gr5 + set_gr_immed 0x33333333,gr6 + set_gr_immed 0x44444444,gr7 + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + or_spr_immed 0x00000800,psr ; turn on PSR.ESR + test_gr_immed 0x11111111,gr4 ; SGR4-7 -- SR0-3 (UGR4-7) are undefined + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + + set_spr_immed 0x55555555,sr0 ; UGR4-7 + set_spr_immed 0x66666666,sr1 + set_spr_immed 0x77777777,sr2 + set_spr_immed 0x88888888,sr3 + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x55555555,sr0 ; UGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + and_spr_immed 0xfffffffb,psr ; turn off PSR.S + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + test_gr_immed 0x55555555,gr4 ; UGR4-7 + test_gr_immed 0x66666666,gr5 + test_gr_immed 0x77777777,gr6 + test_gr_immed 0x88888888,gr7 + + ; need to generate a trap to return to supervisor mode + set_spr_addr ok0,lr + tira gr0,4 ; should branch to tbr + (128 + 4)*16 + + test_spr_bits 0x800,11,0,psr ; PSR.ESR clear + test_spr_bits 0x4,2,0,psr ; PSR.S clear + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + set_gr_immed 0x55555555,gr4 ; SGR4-7 + set_gr_immed 0x66666666,gr5 + set_gr_immed 0x77777777,gr6 + set_gr_immed 0x88888888,gr7 + test_gr_immed 0x55555555,gr4 ; SGR4-7 + test_gr_immed 0x66666666,gr5 + test_gr_immed 0x77777777,gr6 + test_gr_immed 0x88888888,gr7 + test_spr_immed 0x55555555,sr0 ; SGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + set_gr_immed 0x11111111,gr4 ; SGR4-7 + set_gr_immed 0x22222222,gr5 + set_gr_immed 0x33333333,gr6 + set_gr_immed 0x44444444,gr7 + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + ; need to generate a trap to return to supervisor mode + set_spr_addr ok1,lr + tira gr0,4 ; should branch to tbr + (128 + 4)*16 + + pass + +ok0: ; exception handler should branch here the first time + test_spr_bits 0x800,11,1,psr ; PSR.ESR set + test_spr_bits 0x4,2,1,psr ; PSR.S set + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x55555555,sr0 ; UGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + rett 0 + fail + +ok1: ; exception handler should branch here the second time + test_spr_bits 0x800,11,0,psr ; PSR.ESR clear + test_spr_bits 0x4,2,1,psr ; PSR.S set + + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + set_spr_immed 0x55555555,sr0 ; SGR4-7 + set_spr_immed 0x66666666,sr1 + set_spr_immed 0x77777777,sr2 + set_spr_immed 0x88888888,sr3 + test_gr_immed 0x55555555,gr4 ; SGR4-7 + test_gr_immed 0x66666666,gr5 + test_gr_immed 0x77777777,gr6 + test_gr_immed 0x88888888,gr7 + test_spr_immed 0x55555555,sr0 ; SGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + set_gr_immed 0x11111111,gr4 ; SGR4-7 + set_gr_immed 0x22222222,gr5 + set_gr_immed 0x33333333,gr6 + set_gr_immed 0x44444444,gr7 + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + rett 0 + fail diff --git a/sim/testsuite/frv/interrupts/timer.cgs b/sim/testsuite/frv/interrupts/timer.cgs new file mode 100644 index 0000000..e9cebc2 --- /dev/null +++ b/sim/testsuite/frv/interrupts/timer.cgs @@ -0,0 +1,31 @@ +# frv testcase to generate timer interrupt for st $GRk,@($GRi,$GRj) +# mach: fr500 fr550 fr400 +# sim: --timer 200,14 + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x2e0,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 0x7fffffff,lcr + set_spr_addr ok1,lr + and_spr_immed 0xffffff87,psr ; enable external interrupts + or_spr_immed 0x00000069,psr ; enable external interrupts + + set_gr_immed 10,gr16 + set_gr_immed 0,gr15 + +again: cmp gr15,gr16,icc0 + blt icc0,0,again + + pass + +; exception handler +ok1: + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/jmpil.cgs b/sim/testsuite/frv/jmpil.cgs new file mode 100644 index 0000000..1d11067 --- /dev/null +++ b/sim/testsuite/frv/jmpil.cgs @@ -0,0 +1,17 @@ +# frv testcase for jmpil @($GRi,$d12) +# mach: all + + .include "testutils.inc" + + start + + .global jmpil +jmpil: + set_spr_immed 0,lr + set_gr_addr ok1,gr8 + jmpil @(gr8,2) ; target gets aligned down + fail +ok1: + test_spr_immed 0,lr + + pass diff --git a/sim/testsuite/frv/jmpl.cgs b/sim/testsuite/frv/jmpl.cgs new file mode 100644 index 0000000..9a58e60 --- /dev/null +++ b/sim/testsuite/frv/jmpl.cgs @@ -0,0 +1,18 @@ +# frv testcase for jmpl @($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global jmpl +jmpl: + set_spr_immed 0,lr + set_gr_addr ok1,gr8 + set_gr_immed 1,gr9 ; target gets aligned down + jmpl @(gr8,gr9) + fail +ok1: + test_spr_immed 0,lr + + pass diff --git a/sim/testsuite/frv/jmpl.pcgs b/sim/testsuite/frv/jmpl.pcgs new file mode 100644 index 0000000..2126820 --- /dev/null +++ b/sim/testsuite/frv/jmpl.pcgs @@ -0,0 +1,42 @@ +# frv parallel testcase for jmpl @($GRi,$GRj),$LI +# mach: all + + .include "testutils.inc" + + start + + .global jmpl +jmpl: + set_spr_immed 0,lr + set_gr_addr ok1,gr8 + set_gr_immed 0,gr9 + jmpl.p @(gr8,gr9) + setlos 10,gr10 + fail +ok1: + test_spr_immed 0,lr + test_gr_immed 10,gr10 + + set_gr_addr ok2,gr8 + inc_gr_immed -4,gr8 + inc_gr_immed 4,gr9 + calll.p @(gr8,gr9) + setlos 11,gr11 +bad2: + fail +ok2: + test_spr_addr bad2,lr + test_gr_immed 11,gr11 + + set_gr_addr ok3,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + setlos 12,gr12 + calll @(gr8,gr9) +bad3: + fail +ok3: + test_spr_addr bad3,lr + test_gr_immed 12,gr12 + + pass diff --git a/sim/testsuite/frv/ld.cgs b/sim/testsuite/frv/ld.cgs new file mode 100644 index 0000000..35206c2 --- /dev/null +++ b/sim/testsuite/frv/ld.cgs @@ -0,0 +1,29 @@ +# frv testcase for ld @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ld +ld: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + ld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + ld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/ldbf.cgs b/sim/testsuite/frv/ldbf.cgs new file mode 100644 index 0000000..52ac077 --- /dev/null +++ b/sim/testsuite/frv/ldbf.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldbf @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldbf +ldbf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + + set_gr_immed 1,gr7 + ldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + + pass diff --git a/sim/testsuite/frv/ldbfi.cgs b/sim/testsuite/frv/ldbfi.cgs new file mode 100644 index 0000000..7e91806 --- /dev/null +++ b/sim/testsuite/frv/ldbfi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldbfi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldbfi +ldbfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + ldbfi @(sp,0),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + + ldbfi @(sp,1),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + ldbfi @(sp,-1),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + + pass diff --git a/sim/testsuite/frv/ldbfu.cgs b/sim/testsuite/frv/ldbfu.cgs new file mode 100644 index 0000000..3cbfb91 --- /dev/null +++ b/sim/testsuite/frv/ldbfu.cgs @@ -0,0 +1,34 @@ +# frv testcase for ldbfu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldbfu +ldbfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + ldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/ldc.cgs b/sim/testsuite/frv/ldc.cgs new file mode 100644 index 0000000..4593c31 --- /dev/null +++ b/sim/testsuite/frv/ldc.cgs @@ -0,0 +1,30 @@ +# frv testcase for ldc @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldc +ldc: + set_mem_limmed 0xdead,0xbeef,sp + set_cpr_limmed 0xbeef,0xdead,cpr8 + + set_gr_immed 0,gr7 + ldc @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + + set_cpr_limmed 0xbeef,0xdead,cpr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldc @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + + set_cpr_limmed 0xbeef,0xdead,cpr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + ldc @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + + pass diff --git a/sim/testsuite/frv/ldcu.cgs b/sim/testsuite/frv/ldcu.cgs new file mode 100644 index 0000000..69890a8 --- /dev/null +++ b/sim/testsuite/frv/ldcu.cgs @@ -0,0 +1,34 @@ +# frv testcase for ldcu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldcu +ldcu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_cpr_limmed 0xbeef,0xdead,cpr8 + + set_gr_immed 0,gr7 + ldcu @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xbeef,0xdead,cpr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldcu @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xbeef,0xdead,cpr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + ldcu @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/ldd.cgs b/sim/testsuite/frv/ldd.cgs new file mode 100644 index 0000000..fa09d31 --- /dev/null +++ b/sim/testsuite/frv/ldd.cgs @@ -0,0 +1,43 @@ +# frv testcase for ldd @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldd +ldd: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + ldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + ldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + ldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + ; loading into gr0 should have no effect + ; gr1 is sp + set_gr_gr gr1,gr8 + ldd @(sp,gr7),gr0 + test_gr_immed 0,gr0 + test_gr_gr gr1,gr8 + pass diff --git a/sim/testsuite/frv/lddc.cgs b/sim/testsuite/frv/lddc.cgs new file mode 100644 index 0000000..e01a214 --- /dev/null +++ b/sim/testsuite/frv/lddc.cgs @@ -0,0 +1,45 @@ +# frv testcase for lddc @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global lddc +lddc: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + + set_gr_immed 0,gr7 + ; loading into cpr0 is business as usual + set_cpr_limmed 0xdead,0xbeef,cpr0 + set_cpr_limmed 0xbeef,0xdead,cpr1 + lddc @(sp,gr7),cpr0 + test_cpr_limmed 0xbeef,0xdead,cpr0 + test_cpr_limmed 0xdead,0xbeef,cpr1 + + lddc @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddc @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + lddc @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + + pass diff --git a/sim/testsuite/frv/lddcu.cgs b/sim/testsuite/frv/lddcu.cgs new file mode 100644 index 0000000..b4ed485 --- /dev/null +++ b/sim/testsuite/frv/lddcu.cgs @@ -0,0 +1,42 @@ +# frv testcase for lddcu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global lddcu +lddcu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + + set_gr_immed 0,gr7 + lddcu @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddcu @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + lddcu @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/lddf.cgs b/sim/testsuite/frv/lddf.cgs new file mode 100644 index 0000000..f7bae78 --- /dev/null +++ b/sim/testsuite/frv/lddf.cgs @@ -0,0 +1,46 @@ +# frv testcase for lddf @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddf +lddf: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + ; loading into fr0 is business as usual + set_fr_iimmed 0xdead,0xbeef,fr0 + set_fr_iimmed 0xbeef,0xdead,fr1 + lddf @(sp,gr7),fr0 + test_fr_limmed 0xbeef,0xdead,fr0 + test_fr_limmed 0xdead,0xbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + lddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + lddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + pass diff --git a/sim/testsuite/frv/lddfi.cgs b/sim/testsuite/frv/lddfi.cgs new file mode 100644 index 0000000..1eac916 --- /dev/null +++ b/sim/testsuite/frv/lddfi.cgs @@ -0,0 +1,34 @@ +# frv testcase for lddfi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddfi +lddfi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + lddfi @(sp,0),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + lddfi @(sp,8),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + lddfi @(sp,-8),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + pass diff --git a/sim/testsuite/frv/lddfu.cgs b/sim/testsuite/frv/lddfu.cgs new file mode 100644 index 0000000..cb4c86e --- /dev/null +++ b/sim/testsuite/frv/lddfu.cgs @@ -0,0 +1,41 @@ +# frv testcase for lddfu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddfu +lddfu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + lddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + lddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/lddi.cgs b/sim/testsuite/frv/lddi.cgs new file mode 100644 index 0000000..38ef2b4 --- /dev/null +++ b/sim/testsuite/frv/lddi.cgs @@ -0,0 +1,34 @@ +# frv testcase for lddi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddi +lddi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + lddi @(sp,0),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + lddi @(sp,8),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + lddi @(sp,-8),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + pass diff --git a/sim/testsuite/frv/lddu.cgs b/sim/testsuite/frv/lddu.cgs new file mode 100644 index 0000000..5b2ead1 --- /dev/null +++ b/sim/testsuite/frv/lddu.cgs @@ -0,0 +1,50 @@ +# frv testcase for lddu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddu +lddu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + lddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + lddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_gr_gr sp,gr8 + lddu @(gr8,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + pass diff --git a/sim/testsuite/frv/ldf.cgs b/sim/testsuite/frv/ldf.cgs new file mode 100644 index 0000000..996d72c --- /dev/null +++ b/sim/testsuite/frv/ldf.cgs @@ -0,0 +1,29 @@ +# frv testcase for ldf @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldf +ldf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + ldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/frv/ldfi.cgs b/sim/testsuite/frv/ldfi.cgs new file mode 100644 index 0000000..e5ea94d --- /dev/null +++ b/sim/testsuite/frv/ldfi.cgs @@ -0,0 +1,26 @@ +# frv testcase for ldfi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldfi +ldfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + ldfi @(sp,0),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + ldfi @(sp,4),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + ldfi @(sp,-4),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/frv/ldfu.cgs b/sim/testsuite/frv/ldfu.cgs new file mode 100644 index 0000000..08f67db --- /dev/null +++ b/sim/testsuite/frv/ldfu.cgs @@ -0,0 +1,33 @@ +# frv testcase for ldfu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldfu +ldfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + ldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/ldhf.cgs b/sim/testsuite/frv/ldhf.cgs new file mode 100644 index 0000000..8935ac7 --- /dev/null +++ b/sim/testsuite/frv/ldhf.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldhf @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldhf +ldhf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + + set_gr_immed 2,gr7 + ldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + ldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + + pass diff --git a/sim/testsuite/frv/ldhfi.cgs b/sim/testsuite/frv/ldhfi.cgs new file mode 100644 index 0000000..362ec50 --- /dev/null +++ b/sim/testsuite/frv/ldhfi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldhfi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldhfi +ldhfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + ldhfi @(sp,0),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + + ldhfi @(sp,2),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + ldhfi @(sp,-2),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + + pass diff --git a/sim/testsuite/frv/ldhfu.cgs b/sim/testsuite/frv/ldhfu.cgs new file mode 100644 index 0000000..0b342e1 --- /dev/null +++ b/sim/testsuite/frv/ldhfu.cgs @@ -0,0 +1,33 @@ +# frv testcase for ldhfu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldhfu +ldhfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + ldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + ldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/ldi.cgs b/sim/testsuite/frv/ldi.cgs new file mode 100644 index 0000000..f36b95d --- /dev/null +++ b/sim/testsuite/frv/ldi.cgs @@ -0,0 +1,26 @@ +# frv testcase for ldi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldi +ldi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + ldi @(sp,0),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + ldi @(sp,4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + ldi @(sp,-4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/ldq.cgs b/sim/testsuite/frv/ldq.cgs new file mode 100644 index 0000000..e61f1de --- /dev/null +++ b/sim/testsuite/frv/ldq.cgs @@ -0,0 +1,64 @@ +# frv testcase for ldq @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global ldq +ldq: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + ldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + ldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + ; loading into gr0 has no effect + ; gr1 is sp + set_gr_gr gr1,gr8 + set_gr_limmed 0x1234,0x5678,gr2 + set_gr_limmed 0x9abc,0xdef0,gr3 + ldq @(sp,gr7),gr0 + test_gr_immed 0,gr0 + test_gr_gr gr1,gr8 + set_gr_immed 0x12345678,gr2 + set_gr_immed 0x9abcdef0,gr3 + + pass diff --git a/sim/testsuite/frv/ldqc.cgs b/sim/testsuite/frv/ldqc.cgs new file mode 100644 index 0000000..64b6a6a --- /dev/null +++ b/sim/testsuite/frv/ldqc.cgs @@ -0,0 +1,60 @@ +# frv testcase for ldqc @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global ldqc +ldqc: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + + set_gr_immed 0,gr7 + ;loading into cpr0 is business as usual + ldqc @(sp,gr7),cpr0 + test_cpr_limmed 0x9abc,0xdef0,cpr0 + test_cpr_limmed 0x1234,0x5678,cpr1 + test_cpr_limmed 0xbeef,0xdead,cpr2 + test_cpr_limmed 0xdead,0xbeef,cpr3 + + ldqc @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqc @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + ldqc @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + + pass diff --git a/sim/testsuite/frv/ldqcu.cgs b/sim/testsuite/frv/ldqcu.cgs new file mode 100644 index 0000000..18d9246 --- /dev/null +++ b/sim/testsuite/frv/ldqcu.cgs @@ -0,0 +1,57 @@ +# frv testcase for ldqcu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global ldqcu +ldqcu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + + set_gr_immed 0,gr7 + ldqcu @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqcu @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + ldqcu @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/ldqf.cgs b/sim/testsuite/frv/ldqf.cgs new file mode 100644 index 0000000..66fb65c --- /dev/null +++ b/sim/testsuite/frv/ldqf.cgs @@ -0,0 +1,61 @@ +# frv testcase for ldqf @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqf +ldqf: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_immed 0,gr7 + ; loading into fr0 is business as usual + ldqf @(sp,gr7),fr0 + test_fr_limmed 0x9abc,0xdef0,fr0 + test_fr_limmed 0x1234,0x5678,fr1 + test_fr_limmed 0xbeef,0xdead,fr2 + test_fr_limmed 0xdead,0xbeef,fr3 + + ldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + ldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + pass diff --git a/sim/testsuite/frv/ldqfi.cgs b/sim/testsuite/frv/ldqfi.cgs new file mode 100644 index 0000000..28c3b1f --- /dev/null +++ b/sim/testsuite/frv/ldqfi.cgs @@ -0,0 +1,51 @@ +# frv testcase for ldqfi @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqfi +ldqfi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + ldqfi @(sp,0),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + ldqfi @(sp,16),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 32,sp + ldqfi @(sp,-16),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + pass diff --git a/sim/testsuite/frv/ldqfu.cgs b/sim/testsuite/frv/ldqfu.cgs new file mode 100644 index 0000000..7287958 --- /dev/null +++ b/sim/testsuite/frv/ldqfu.cgs @@ -0,0 +1,58 @@ +# frv testcase for ldqfu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqfu +ldqfu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_immed 0,gr7 + ldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + ldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/ldqi.cgs b/sim/testsuite/frv/ldqi.cgs new file mode 100644 index 0000000..64d66f2 --- /dev/null +++ b/sim/testsuite/frv/ldqi.cgs @@ -0,0 +1,51 @@ +# frv testcase for ldqi @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqi +ldqi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + ldqi @(sp,0),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + ldqi @(sp,16),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + ldqi @(sp,-16),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + pass diff --git a/sim/testsuite/frv/ldqu.cgs b/sim/testsuite/frv/ldqu.cgs new file mode 100644 index 0000000..263eae1 --- /dev/null +++ b/sim/testsuite/frv/ldqu.cgs @@ -0,0 +1,71 @@ +# frv testcase for ldqu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqu +ldqu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + ldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + ldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + set_gr_gr sp,gr8 + ldqu @(gr8,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + pass diff --git a/sim/testsuite/frv/ldsb.cgs b/sim/testsuite/frv/ldsb.cgs new file mode 100644 index 0000000..4b10639 --- /dev/null +++ b/sim/testsuite/frv/ldsb.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldsb @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldsb +ldsb: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + ldsb @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + + set_gr_immed 1,gr7 + ldsb @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldsb @(sp,gr7),gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/frv/ldsbi.cgs b/sim/testsuite/frv/ldsbi.cgs new file mode 100644 index 0000000..c90a129 --- /dev/null +++ b/sim/testsuite/frv/ldsbi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldsbi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldsbi +ldsbi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + ldsbi @(sp,0),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + + ldsbi @(sp,1),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + ldsbi @(sp,-1),gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/frv/ldsbu.cgs b/sim/testsuite/frv/ldsbu.cgs new file mode 100644 index 0000000..976cee8 --- /dev/null +++ b/sim/testsuite/frv/ldsbu.cgs @@ -0,0 +1,40 @@ +# frv testcase for ldsbu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldsbu +ldsbu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + ldsbu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + ldsbu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldsbu @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -3,sp + set_mem_limmed 0x0000,0x00da,sp + set_gr_immed 3,gr7 + ldsbu @(sp,gr7),sp + test_gr_limmed 0xffff,0xffda,sp + + pass diff --git a/sim/testsuite/frv/ldsh.cgs b/sim/testsuite/frv/ldsh.cgs new file mode 100644 index 0000000..c526f39 --- /dev/null +++ b/sim/testsuite/frv/ldsh.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldsh @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldsh +ldsh: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + ldsh @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + + set_gr_immed 2,gr7 + ldsh @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + ldsh @(sp,gr7),gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/frv/ldshi.cgs b/sim/testsuite/frv/ldshi.cgs new file mode 100644 index 0000000..69f99f1 --- /dev/null +++ b/sim/testsuite/frv/ldshi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldshi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldshi +ldshi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + ldshi @(sp,0),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + + ldshi @(sp,2),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + ldshi @(sp,-2),gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/frv/ldshu.cgs b/sim/testsuite/frv/ldshu.cgs new file mode 100644 index 0000000..f1b8c23 --- /dev/null +++ b/sim/testsuite/frv/ldshu.cgs @@ -0,0 +1,39 @@ +# frv testcase for ldshu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldshu +ldshu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + ldshu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + ldshu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + ldshu @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0x0000,0xdead,sp + set_gr_immed 2,gr7 + ldshu @(sp,gr7),sp + test_gr_limmed 0xffff,0xdead,sp + + pass diff --git a/sim/testsuite/frv/ldu.cgs b/sim/testsuite/frv/ldu.cgs new file mode 100644 index 0000000..b7f2e34 --- /dev/null +++ b/sim/testsuite/frv/ldu.cgs @@ -0,0 +1,39 @@ +# frv testcase for ldu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldu +ldu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + ldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + ldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldu @(sp,gr7),sp + test_gr_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/ldub.cgs b/sim/testsuite/frv/ldub.cgs new file mode 100644 index 0000000..1e19254 --- /dev/null +++ b/sim/testsuite/frv/ldub.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldub @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldub +ldub: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + ldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + + set_gr_immed 1,gr7 + ldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + pass diff --git a/sim/testsuite/frv/ldubi.cgs b/sim/testsuite/frv/ldubi.cgs new file mode 100644 index 0000000..4c40bee --- /dev/null +++ b/sim/testsuite/frv/ldubi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldubi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldubi +ldubi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + ldubi @(sp,0),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + + ldubi @(sp,1),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + ldubi @(sp,-1),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + pass diff --git a/sim/testsuite/frv/ldubu.cgs b/sim/testsuite/frv/ldubu.cgs new file mode 100644 index 0000000..8c99ab0 --- /dev/null +++ b/sim/testsuite/frv/ldubu.cgs @@ -0,0 +1,39 @@ +# frv testcase for ldubu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldubu +ldubu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + ldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + ldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + inc_gr_immed -3,sp + set_mem_limmed 0xffff,0xffda,sp + set_gr_immed 3,gr7 + ldubu @(sp,gr7),sp + test_gr_limmed 0x0000,0x00da,sp + + pass diff --git a/sim/testsuite/frv/lduh.cgs b/sim/testsuite/frv/lduh.cgs new file mode 100644 index 0000000..24c3bac --- /dev/null +++ b/sim/testsuite/frv/lduh.cgs @@ -0,0 +1,27 @@ +# frv testcase for lduh @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lduh +lduh: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + lduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + + set_gr_immed 2,gr7 + lduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + lduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + pass diff --git a/sim/testsuite/frv/lduhi.cgs b/sim/testsuite/frv/lduhi.cgs new file mode 100644 index 0000000..b9896d6 --- /dev/null +++ b/sim/testsuite/frv/lduhi.cgs @@ -0,0 +1,24 @@ +# frv testcase for lduhi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lduhi +lduhi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + lduhi @(sp,0),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + + lduhi @(sp,2),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + lduhi @(sp,-2),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + pass diff --git a/sim/testsuite/frv/lduhu.cgs b/sim/testsuite/frv/lduhu.cgs new file mode 100644 index 0000000..52faecf --- /dev/null +++ b/sim/testsuite/frv/lduhu.cgs @@ -0,0 +1,39 @@ +# frv testcase for lduhu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lduhu +lduhu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + lduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + lduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + lduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0xdead,sp + set_gr_immed 2,gr7 + lduhu @(sp,gr7),sp + test_gr_limmed 0x0000,0xdead,sp + + pass diff --git a/sim/testsuite/frv/lrbranch.pcgs b/sim/testsuite/frv/lrbranch.pcgs new file mode 100644 index 0000000..0ac1a75 --- /dev/null +++ b/sim/testsuite/frv/lrbranch.pcgs @@ -0,0 +1,51 @@ +# frv parallel testcase for lr branching +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global lrbranch +lrbranch: + ; Both conditions true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x4 0 + bcgelr.p icc0,0,0 + bra ok4 + fail +ok1: + test_spr_immed 127,LCR + + ; Only first condition true + set_spr_immed 128,lcr + set_spr_addr ok2,lr + set_icc 0x0 0 + bcgelr.p icc0,0,0 + bno + fail +ok2: + test_spr_immed 127,LCR + + ; Only second condition true + set_spr_immed 128,lcr + set_spr_addr ok3,lr + set_icc 0x8 0 + bcgelr.p icc0,0,0 + bra ok3 + fail +ok3: + test_spr_immed 127,LCR + + ; Both conditions false + set_spr_immed 128,lcr + set_spr_addr ok4,lr + set_icc 0x0 0 + bceqlr.p icc0,0,0 + bno + test_spr_immed 127,LCR + + pass + +ok4: + fail diff --git a/sim/testsuite/frv/mabshs.cgs b/sim/testsuite/frv/mabshs.cgs new file mode 100644 index 0000000..29b2532 --- /dev/null +++ b/sim/testsuite/frv/mabshs.cgs @@ -0,0 +1,67 @@ +# frv testcase for mabshs $FRj,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mabshs +mabshs: + set_fr_iimmed 0x0000,0x0000,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x0000,0x0000,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0xffff,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x0001,0x0001,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7fff,0x8001,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7fff,0x8000,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8000,0x7fff,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + mabshs.p fr10,fr12 + mabshs fr11,fr13 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/maddhss.cgs b/sim/testsuite/frv/maddhss.cgs new file mode 100644 index 0000000..289ecc77 --- /dev/null +++ b/sim/testsuite/frv/maddhss.cgs @@ -0,0 +1,100 @@ +# frv testcase for maddhss $FRi,$FRj,$FRj +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global maddhss +maddhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maddhss fr10,fr11,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maddhss.p fr10,fr10,fr12 + maddhss fr11,fr11,fr13 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/maddhus.cgs b/sim/testsuite/frv/maddhus.cgs new file mode 100644 index 0000000..fe96e69 --- /dev/null +++ b/sim/testsuite/frv/maddhus.cgs @@ -0,0 +1,89 @@ +# frv testcase for maddhus $FRi,$FRj,$FRj +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global maddhus +maddhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + maddhus.p fr10,fr10,fr12 + maddhus fr11,fr11,fr13 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/mand.cgs b/sim/testsuite/frv/mand.cgs new file mode 100644 index 0000000..c6aa993 --- /dev/null +++ b/sim/testsuite/frv/mand.cgs @@ -0,0 +1,23 @@ +# frv testcase for mand $FRinti,$FRintj,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mand +mand: + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + mand fr7,fr8,fr8 + test_fr_iimmed 0,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + mand fr7,fr8,fr8 + test_fr_iimmed 0xaaaa0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + mand fr7,fr8,fr8 + test_fr_iimmed 0x0000aaaa,fr8 + + pass diff --git a/sim/testsuite/frv/maveh.cgs b/sim/testsuite/frv/maveh.cgs new file mode 100644 index 0000000..d48ad72 --- /dev/null +++ b/sim/testsuite/frv/maveh.cgs @@ -0,0 +1,72 @@ +# frv testcase for maveh $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global maveh +maveh: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0000,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xffff,0xfffe,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef56,0xdf77,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf77,0xef56,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a2,0x33c4,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0919,0x2b3b,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x3fff,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xbfff,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xbfff,0xbfff,fr12 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + pass diff --git a/sim/testsuite/frv/mbtoh.cgs b/sim/testsuite/frv/mbtoh.cgs new file mode 100644 index 0000000..52895ad --- /dev/null +++ b/sim/testsuite/frv/mbtoh.cgs @@ -0,0 +1,20 @@ +# frv testcase for mbtoh $FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mbtoh +mbtoh: + set_fr_iimmed 0xdead,0xbeef,fr10 + mbtoh fr10,fr12 + test_fr_limmed 0x00de,0x00ad,fr12 + test_fr_limmed 0x00be,0x00ef,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + mbtoh fr10,fr12 + test_fr_limmed 0x0012,0x0034,fr12 + test_fr_limmed 0x0056,0x0078,fr13 + + pass diff --git a/sim/testsuite/frv/mbtohe.cgs b/sim/testsuite/frv/mbtohe.cgs new file mode 100644 index 0000000..1e978ec --- /dev/null +++ b/sim/testsuite/frv/mbtohe.cgs @@ -0,0 +1,24 @@ +# frv testcase for mbtohe $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + start + + .global mbtohe +mbtohe: + set_fr_iimmed 0xdead,0xbeef,fr10 + mbtohe fr10,fr12 + test_fr_limmed 0x00de,0x00de,fr12 + test_fr_limmed 0x00ad,0x00ad,fr13 + test_fr_limmed 0x00be,0x00be,fr14 + test_fr_limmed 0x00ef,0x00ef,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + mbtohe fr10,fr12 + test_fr_limmed 0x0012,0x0012,fr12 + test_fr_limmed 0x0034,0x0034,fr13 + test_fr_limmed 0x0056,0x0056,fr14 + test_fr_limmed 0x0078,0x0078,fr15 + + pass diff --git a/sim/testsuite/frv/mclracc.cgs b/sim/testsuite/frv/mclracc.cgs new file mode 100644 index 0000000..7972b9a --- /dev/null +++ b/sim/testsuite/frv/mclracc.cgs @@ -0,0 +1,79 @@ +# frv testcase for mclracc $ACC40k,$A +# mach: frv + + .include "testutils.inc" + + start + + .global mclracc +mclracc: + set_accg_immed 0xff,accg0 + set_acc_immed -1,acc0 + set_accg_immed 0xff,accg8 + set_acc_immed -1,acc8 + set_accg_immed 0xff,accg31 + set_acc_immed -1,acc31 + set_accg_immed 0xff,accg62 + set_acc_immed -1,acc62 + + mclracc acc63,0 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0xff,accg31 + test_acc_immed -1,acc31 + test_accg_immed 0xff,accg62 + test_acc_immed -1,acc62 + + mclracc acc63,1 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0xff,accg31 + test_acc_immed -1,acc31 + test_accg_immed 0xff,accg62 + test_acc_immed -1,acc62 + + mclracc acc31,0 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0,accg31 + test_acc_immed 0,acc31 + test_accg_immed 0xff,accg62 + test_acc_immed -1,acc62 + + mclracc acc62,1 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0,accg31 + test_acc_immed 0,acc31 + test_accg_immed 0,accg62 + test_acc_immed 0,acc62 + + mclracc acc0,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0,accg31 + test_acc_immed 0,acc31 + test_accg_immed 0,accg62 + test_acc_immed 0,acc62 + + mclracc acc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg8 + test_acc_immed 0,acc8 + test_accg_immed 0,accg31 + test_acc_immed 0,acc31 + test_accg_immed 0,accg62 + test_acc_immed 0,acc62 + + pass diff --git a/sim/testsuite/frv/mcmpsh.cgs b/sim/testsuite/frv/mcmpsh.cgs new file mode 100644 index 0000000..50e986d --- /dev/null +++ b/sim/testsuite/frv/mcmpsh.cgs @@ -0,0 +1,138 @@ +# frv testcase for mcmpsh $FRi,$FRj,$FCCk +# mach: all + + .include "testutils.inc" + + start + + .global mcmpsh +mcmpsh: + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + pass diff --git a/sim/testsuite/frv/mcmpuh.cgs b/sim/testsuite/frv/mcmpuh.cgs new file mode 100644 index 0000000..a6670b7 --- /dev/null +++ b/sim/testsuite/frv/mcmpuh.cgs @@ -0,0 +1,138 @@ +# frv testcase for mcmpuh $FRi,$FRj,$FCCk +# mach: all + + .include "testutils.inc" + + start + + .global mcmpuh +mcmpuh: + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + pass diff --git a/sim/testsuite/frv/mcop1.cgs b/sim/testsuite/frv/mcop1.cgs new file mode 100644 index 0000000..5405456 --- /dev/null +++ b/sim/testsuite/frv/mcop1.cgs @@ -0,0 +1,40 @@ +# frv testcase for mcop1 $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + start + + .global mcop1 +mcop1: + mcop1.p fr19,fr12,fr13 ; mp_exception: not-implemented + mcop1 fr20,fr14,fr18 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop1.p fr19,fr12,fr13 ; mp_exception: not-implemented + mcop1 fr20,fr14,fr18 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop1 fr19,fr12,fr13 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop1 fr19,fr12,fr13 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + pass diff --git a/sim/testsuite/frv/mcop2.cgs b/sim/testsuite/frv/mcop2.cgs new file mode 100644 index 0000000..f423a3e --- /dev/null +++ b/sim/testsuite/frv/mcop2.cgs @@ -0,0 +1,40 @@ +# frv testcase for mcop2 $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + start + + .global mcop2 +mcop2: + mcop2.p fr19,fr12,fr13 ; mp_exception: not-implemented + mcop2 fr20,fr14,fr18 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop2.p fr19,fr12,fr13 ; mp_exception: not-implemented + mcop2 fr20,fr14,fr18 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop2 fr19,fr12,fr13 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop2 fr19,fr12,fr13 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + pass diff --git a/sim/testsuite/frv/mcplhi.cgs b/sim/testsuite/frv/mcplhi.cgs new file mode 100644 index 0000000..d1a52eb --- /dev/null +++ b/sim/testsuite/frv/mcplhi.cgs @@ -0,0 +1,53 @@ +# frv testcase for mcplhi $FRi,$s6,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global mcplhi +mcplhi: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x0,fr10 ; Shift by 0 + test_fr_iimmed 0xdead5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x1,fr10 ; Shift by 1 + test_fr_iimmed 0xbd5b5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x4,fr10 ; Shift by 4 + test_fr_iimmed 0xeadf5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0xc,fr10 ; Shift by 12 + test_fr_iimmed 0xdeef5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0xf,fr10 ; Shift by 15 + test_fr_iimmed 0xbeef5678,fr10 + + ; test again with truncated shift values + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x10,fr10 ; Shift by 0 + test_fr_iimmed 0xdead5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x21,fr10 ; Shift by 1 + test_fr_iimmed 0xbd5b5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x34,fr10 ; Shift by 4 + test_fr_iimmed 0xeadf5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x1c,fr10 ; Shift by 12 + test_fr_iimmed 0xdeef5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x2f,fr10 ; Shift by 15 + test_fr_iimmed 0xbeef5678,fr10 + + pass diff --git a/sim/testsuite/frv/mcpli.cgs b/sim/testsuite/frv/mcpli.cgs new file mode 100644 index 0000000..b63ec67 --- /dev/null +++ b/sim/testsuite/frv/mcpli.cgs @@ -0,0 +1,61 @@ +# frv testcase for mcpli $FRi,$s6,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global mcpli +mcpli: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x0,fr10 ; Shift by 0 + test_fr_iimmed 0xdeadbeef,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x1,fr10 ; Shift by 1 + test_fr_iimmed 0xbd5b7ddf,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x4,fr10 ; Shift by 4 + test_fr_iimmed 0xeadbeefd,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0xc,fr10 ; Shift by 12 + test_fr_iimmed 0xdbeefead,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x1c,fr10 ; Shift by 28 + test_fr_iimmed 0xfeefdead,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x1f,fr10 ; Shift by 31 + test_fr_iimmed 0xbeefdead,fr10 + + ; test again with truncated shift values + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x20,fr10 ; Shift by 0 + test_fr_iimmed 0xdeadbeef,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x21,fr10 ; Shift by 1 + test_fr_iimmed 0xbd5b7ddf,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x24,fr10 ; Shift by 4 + test_fr_iimmed 0xeadbeefd,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x2c,fr10 ; Shift by 12 + test_fr_iimmed 0xdbeefead,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x3c,fr10 ; Shift by 28 + test_fr_iimmed 0xfeefdead,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x3f,fr10 ; Shift by 31 + test_fr_iimmed 0xbeefdead,fr10 + + pass diff --git a/sim/testsuite/frv/mcpxis.cgs b/sim/testsuite/frv/mcpxis.cgs new file mode 100644 index 0000000..c3dad01 --- /dev/null +++ b/sim/testsuite/frv/mcpxis.cgs @@ -0,0 +1,115 @@ +# frv testcase for mcpxis $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mcpxis +mcpxis: + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xc000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -9,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result + set_fr_iimmed 0xffff,0xfffe,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbfff,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8001,0x0000,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x8000,0x0000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + pass diff --git a/sim/testsuite/frv/mcpxiu.cgs b/sim/testsuite/frv/mcpxiu.cgs new file mode 100644 index 0000000..198f056 --- /dev/null +++ b/sim/testsuite/frv/mcpxiu.cgs @@ -0,0 +1,76 @@ +# frv testcase for mcpxiu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mcpxiu +mcpxiu: + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + pass diff --git a/sim/testsuite/frv/mcpxrs.cgs b/sim/testsuite/frv/mcpxrs.cgs new file mode 100644 index 0000000..1d62a96 --- /dev/null +++ b/sim/testsuite/frv/mcpxrs.cgs @@ -0,0 +1,115 @@ +# frv testcase for mcpxrs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mcpxrs +mcpxrs: + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ff0,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -3,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbff0,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8006,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8000,0x8000,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x7fff,0x8000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + pass diff --git a/sim/testsuite/frv/mcpxru.cgs b/sim/testsuite/frv/mcpxru.cgs new file mode 100644 index 0000000..8a54392 --- /dev/null +++ b/sim/testsuite/frv/mcpxru.cgs @@ -0,0 +1,94 @@ +# frv testcase for mcpxru $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mcpxru +mcpxru: + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + mcpxru fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxru fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxru fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + pass diff --git a/sim/testsuite/frv/mcut.cgs b/sim/testsuite/frv/mcut.cgs new file mode 100644 index 0000000..d6211ab --- /dev/null +++ b/sim/testsuite/frv/mcut.cgs @@ -0,0 +1,509 @@ +# frv testcase for mcut $ACC40i,$FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mcut +mcut: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + + set_fr_iimmed 0,0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + set_fr_iimmed 0,1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + set_fr_iimmed 0,2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + set_fr_iimmed 0,3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3c4d5e6f,fr11 + + set_fr_iimmed 0,4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x789abcde,fr11 + + set_fr_iimmed 0,5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf13579bd,fr11 + + set_fr_iimmed 0,6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe26af37b,fr11 + + set_fr_iimmed 0,7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xc4d5e6f7,fr11 + + set_fr_iimmed 0,8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x89abcdef,fr11 + + set_fr_iimmed 0,9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x13579bde,fr11 + + set_fr_iimmed 0,10,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x26af37bc,fr11 + + set_fr_iimmed 0,11,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x4d5e6f78,fr11 + + set_fr_iimmed 0,12,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x9abcdef0,fr11 + + set_fr_iimmed 0,13,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3579bde0,fr11 + + set_fr_iimmed 0,14,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x6af37bc0,fr11 + + set_fr_iimmed 0,15,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xd5e6f780,fr11 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xabcdef00,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x579bde00,fr11 + + set_fr_iimmed 0,18,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xaf37bc00,fr11 + + set_fr_iimmed 0,19,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x5e6f7800,fr11 + + set_fr_iimmed 0,20,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xbcdef000,fr11 + + set_fr_iimmed 0,21,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x79bde000,fr11 + + set_fr_iimmed 0,22,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf37bc000,fr11 + + set_fr_iimmed 0,23,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe6f78000,fr11 + + set_fr_iimmed 0,24,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xcdef0000,fr11 + + set_fr_iimmed 0,25,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x9bde0000,fr11 + + set_fr_iimmed 0,26,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x37bc0000,fr11 + + set_fr_iimmed 0,27,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x6f780000,fr11 + + set_fr_iimmed 0,28,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xdef00000,fr11 + + set_fr_iimmed 0,29,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xbde00000,fr11 + + set_fr_iimmed 0,30,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x7bc00000,fr11 + + set_fr_iimmed 0,31,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf7800000,fr11 + + set_fr_iimmed 0,31,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf7800000,fr11 + + set_fr_iimmed 0,64,fr10 ; same as 0 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + set_fr_iimmed 0xffff,0xffff,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf3c4d5e6,fr11 + + set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf9e26af3,fr11 + + set_fr_iimmed 0xffff,0xfffd,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfcf13579,fr11 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfe789abc,fr11 + + set_fr_iimmed 0xffff,0xfffb,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xff3c4d5e,fr11 + + set_fr_iimmed 0xffff,0xfffa,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xff9e26af,fr11 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffcf1357,fr11 + + set_fr_iimmed 0xffff,0xfff8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffe789ab,fr11 + + set_fr_iimmed 0xffff,0xfff7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfff3c4d5,fr11 + + set_fr_iimmed 0xffff,0xfff6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfff9e26a,fr11 + + set_fr_iimmed 0xffff,0xfff5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffcf135,fr11 + + set_fr_iimmed 0xffff,0xfff4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffe789a,fr11 + + set_fr_iimmed 0xffff,0xfff3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffff3c4d,fr11 + + set_fr_iimmed 0xffff,0xfff2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffff9e26,fr11 + + set_fr_iimmed 0xffff,0xfff1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffcf13,fr11 + + set_fr_iimmed 0xffff,0xfff0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffe789,fr11 + + set_fr_iimmed 0xffff,0xffef,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffff3c4,fr11 + + set_fr_iimmed 0xffff,0xffee,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffff9e2,fr11 + + set_fr_iimmed 0xffff,0xffed,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffcf1,fr11 + + set_fr_iimmed 0xffff,0xffec,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffe78,fr11 + + set_fr_iimmed 0xffff,0xffeb,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffff3c,fr11 + + set_fr_iimmed 0xffff,0xffea,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffff9e,fr11 + + set_fr_iimmed 0xffff,0xffe9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffcf,fr11 + + set_fr_iimmed 0xffff,0xffe8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffe7,fr11 + + set_fr_iimmed 0xffff,0xffe7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffff3,fr11 + + set_fr_iimmed 0xffff,0xffe6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffff9,fr11 + + set_fr_iimmed 0xffff,0xffe5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffffc,fr11 + + set_fr_iimmed 0xffff,0xffe4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffffe,fr11 + + set_fr_iimmed 0xffff,0xffe3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0,32,fr10 ; same as -32 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + + set_fr_iimmed 0xffff,0xffff,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x33c4d5e6,fr11 + + set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter + mcut acc0,fr10,fr11 + test_fr_iimmed 0x19e26af3,fr11 + + set_fr_iimmed 0xffff,0xfffd,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0cf13579,fr11 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x06789abc,fr11 + + set_fr_iimmed 0xffff,0xfffb,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x033c4d5e,fr11 + + set_fr_iimmed 0xffff,0xfffa,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x019e26af,fr11 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00cf1357,fr11 + + set_fr_iimmed 0xffff,0xfff8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x006789ab,fr11 + + set_fr_iimmed 0xffff,0xfff7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0033c4d5,fr11 + + set_fr_iimmed 0xffff,0xfff6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0019e26a,fr11 + + set_fr_iimmed 0xffff,0xfff5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x000cf135,fr11 + + set_fr_iimmed 0xffff,0xfff4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0006789a,fr11 + + set_fr_iimmed 0xffff,0xfff3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00033c4d,fr11 + + set_fr_iimmed 0xffff,0xfff2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00019e26,fr11 + + set_fr_iimmed 0xffff,0xfff1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0000cf13,fr11 + + set_fr_iimmed 0xffff,0xfff0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00006789,fr11 + + set_fr_iimmed 0xffff,0xffef,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x000033c4,fr11 + + set_fr_iimmed 0xffff,0xffee,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x000019e2,fr11 + + set_fr_iimmed 0xffff,0xffed,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000cf1,fr11 + + set_fr_iimmed 0xffff,0xffec,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000678,fr11 + + set_fr_iimmed 0xffff,0xffeb,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0000033c,fr11 + + set_fr_iimmed 0xffff,0xffea,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0000019e,fr11 + + set_fr_iimmed 0xffff,0xffe9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x000000cf,fr11 + + set_fr_iimmed 0xffff,0xffe8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000067,fr11 + + set_fr_iimmed 0xffff,0xffe7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000033,fr11 + + set_fr_iimmed 0xffff,0xffe6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000019,fr11 + + set_fr_iimmed 0xffff,0xffe5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0000000c,fr11 + + set_fr_iimmed 0xffff,0xffe4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000006,fr11 + + set_fr_iimmed 0xffff,0xffe3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000003,fr11 + + set_fr_iimmed 0xffff,0xffe2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000001,fr11 + + set_fr_iimmed 0xffff,0xffe1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + set_fr_iimmed 0xffff,0xffe0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + set_fr_iimmed 0,32,fr10 ; same as -32 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/frv/mcuti.cgs b/sim/testsuite/frv/mcuti.cgs new file mode 100644 index 0000000..e2e702f --- /dev/null +++ b/sim/testsuite/frv/mcuti.cgs @@ -0,0 +1,381 @@ +# frv testcase for mcuti $ACC40i,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mcuti +mcuti: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + + mcuti acc0,0,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + mcuti acc0,1,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + mcuti acc0,2,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + set_fr_iimmed 0,3,fr10 + mcuti acc0,3,fr11 + test_fr_iimmed 0x3c4d5e6f,fr11 + + mcuti acc0,4,fr11 + test_fr_iimmed 0x789abcde,fr11 + + mcuti acc0,5,fr11 + test_fr_iimmed 0xf13579bd,fr11 + + mcuti acc0,6,fr11 + test_fr_iimmed 0xe26af37b,fr11 + + mcuti acc0,7,fr11 + test_fr_iimmed 0xc4d5e6f7,fr11 + + mcuti acc0,8,fr11 + test_fr_iimmed 0x89abcdef,fr11 + + mcuti acc0,9,fr11 + test_fr_iimmed 0x13579bde,fr11 + + mcuti acc0,10,fr11 + test_fr_iimmed 0x26af37bc,fr11 + + mcuti acc0,11,fr11 + test_fr_iimmed 0x4d5e6f78,fr11 + + mcuti acc0,12,fr11 + test_fr_iimmed 0x9abcdef0,fr11 + + mcuti acc0,13,fr11 + test_fr_iimmed 0x3579bde0,fr11 + + mcuti acc0,14,fr11 + test_fr_iimmed 0x6af37bc0,fr11 + + mcuti acc0,15,fr11 + test_fr_iimmed 0xd5e6f780,fr11 + + mcuti acc0,16,fr11 + test_fr_iimmed 0xabcdef00,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0x579bde00,fr11 + + mcuti acc0,18,fr11 + test_fr_iimmed 0xaf37bc00,fr11 + + mcuti acc0,19,fr11 + test_fr_iimmed 0x5e6f7800,fr11 + + mcuti acc0,20,fr11 + test_fr_iimmed 0xbcdef000,fr11 + + mcuti acc0,21,fr11 + test_fr_iimmed 0x79bde000,fr11 + + mcuti acc0,22,fr11 + test_fr_iimmed 0xf37bc000,fr11 + + mcuti acc0,23,fr11 + test_fr_iimmed 0xe6f78000,fr11 + + mcuti acc0,24,fr11 + test_fr_iimmed 0xcdef0000,fr11 + + mcuti acc0,25,fr11 + test_fr_iimmed 0x9bde0000,fr11 + + mcuti acc0,26,fr11 + test_fr_iimmed 0x37bc0000,fr11 + + mcuti acc0,27,fr11 + test_fr_iimmed 0x6f780000,fr11 + + mcuti acc0,28,fr11 + test_fr_iimmed 0xdef00000,fr11 + + mcuti acc0,29,fr11 + test_fr_iimmed 0xbde00000,fr11 + + mcuti acc0,30,fr11 + test_fr_iimmed 0x7bc00000,fr11 + + mcuti acc0,31,fr11 + test_fr_iimmed 0xf7800000,fr11 + + mcuti acc0,-1,fr11 + test_fr_iimmed 0xf3c4d5e6,fr11 + + mcuti acc0,-2,fr11 + test_fr_iimmed 0xf9e26af3,fr11 + + mcuti acc0,-3,fr11 + test_fr_iimmed 0xfcf13579,fr11 + + mcuti acc0,-4,fr11 + test_fr_iimmed 0xfe789abc,fr11 + + mcuti acc0,-5,fr11 + test_fr_iimmed 0xff3c4d5e,fr11 + + mcuti acc0,-6,fr11 + test_fr_iimmed 0xff9e26af,fr11 + + mcuti acc0,-7,fr11 + test_fr_iimmed 0xffcf1357,fr11 + + mcuti acc0,-8,fr11 + test_fr_iimmed 0xffe789ab,fr11 + + mcuti acc0,-9,fr11 + test_fr_iimmed 0xfff3c4d5,fr11 + + mcuti acc0,-10,fr11 + test_fr_iimmed 0xfff9e26a,fr11 + + mcuti acc0,-11,fr11 + test_fr_iimmed 0xfffcf135,fr11 + + mcuti acc0,-12,fr11 + test_fr_iimmed 0xfffe789a,fr11 + + mcuti acc0,-13,fr11 + test_fr_iimmed 0xffff3c4d,fr11 + + mcuti acc0,-14,fr11 + test_fr_iimmed 0xffff9e26,fr11 + + mcuti acc0,-15,fr11 + test_fr_iimmed 0xffffcf13,fr11 + + mcuti acc0,-16,fr11 + test_fr_iimmed 0xffffe789,fr11 + + mcuti acc0,-17,fr11 + test_fr_iimmed 0xfffff3c4,fr11 + + mcuti acc0,-18,fr11 + test_fr_iimmed 0xfffff9e2,fr11 + + mcuti acc0,-19,fr11 + test_fr_iimmed 0xfffffcf1,fr11 + + mcuti acc0,-20,fr11 + test_fr_iimmed 0xfffffe78,fr11 + + mcuti acc0,-21,fr11 + test_fr_iimmed 0xffffff3c,fr11 + + mcuti acc0,-22,fr11 + test_fr_iimmed 0xffffff9e,fr11 + + mcuti acc0,-23,fr11 + test_fr_iimmed 0xffffffcf,fr11 + + mcuti acc0,-24,fr11 + test_fr_iimmed 0xffffffe7,fr11 + + mcuti acc0,-25,fr11 + test_fr_iimmed 0xfffffff3,fr11 + + mcuti acc0,-26,fr11 + test_fr_iimmed 0xfffffff9,fr11 + + mcuti acc0,-27,fr11 + test_fr_iimmed 0xfffffffc,fr11 + + mcuti acc0,-28,fr11 + test_fr_iimmed 0xfffffffe,fr11 + + mcuti acc0,-29,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcuti acc0,-30,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcuti acc0,-31,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcuti acc0,-32,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + + mcuti acc0,-1,fr11 + test_fr_iimmed 0x33c4d5e6,fr11 + + mcuti acc0,-2,fr11 + test_fr_iimmed 0x19e26af3,fr11 + + mcuti acc0,-3,fr11 + test_fr_iimmed 0x0cf13579,fr11 + + mcuti acc0,-4,fr11 + test_fr_iimmed 0x06789abc,fr11 + + mcuti acc0,-5,fr11 + test_fr_iimmed 0x033c4d5e,fr11 + + mcuti acc0,-6,fr11 + test_fr_iimmed 0x019e26af,fr11 + + mcuti acc0,-7,fr11 + test_fr_iimmed 0x00cf1357,fr11 + + mcuti acc0,-8,fr11 + test_fr_iimmed 0x006789ab,fr11 + + mcuti acc0,-9,fr11 + test_fr_iimmed 0x0033c4d5,fr11 + + mcuti acc0,-10,fr11 + test_fr_iimmed 0x0019e26a,fr11 + + mcuti acc0,-11,fr11 + test_fr_iimmed 0x000cf135,fr11 + + mcuti acc0,-12,fr11 + test_fr_iimmed 0x0006789a,fr11 + + mcuti acc0,-13,fr11 + test_fr_iimmed 0x00033c4d,fr11 + + mcuti acc0,-14,fr11 + test_fr_iimmed 0x00019e26,fr11 + + mcuti acc0,-15,fr11 + test_fr_iimmed 0x0000cf13,fr11 + + mcuti acc0,-16,fr11 + test_fr_iimmed 0x00006789,fr11 + + mcuti acc0,-17,fr11 + test_fr_iimmed 0x000033c4,fr11 + + mcuti acc0,-18,fr11 + test_fr_iimmed 0x000019e2,fr11 + + mcuti acc0,-19,fr11 + test_fr_iimmed 0x00000cf1,fr11 + + mcuti acc0,-20,fr11 + test_fr_iimmed 0x00000678,fr11 + + mcuti acc0,-21,fr11 + test_fr_iimmed 0x0000033c,fr11 + + mcuti acc0,-22,fr11 + test_fr_iimmed 0x0000019e,fr11 + + mcuti acc0,-23,fr11 + test_fr_iimmed 0x000000cf,fr11 + + mcuti acc0,-24,fr11 + test_fr_iimmed 0x00000067,fr11 + + mcuti acc0,-25,fr11 + test_fr_iimmed 0x00000033,fr11 + + mcuti acc0,-26,fr11 + test_fr_iimmed 0x00000019,fr11 + + mcuti acc0,-27,fr11 + test_fr_iimmed 0x0000000c,fr11 + + mcuti acc0,-28,fr11 + test_fr_iimmed 0x00000006,fr11 + + mcuti acc0,-29,fr11 + test_fr_iimmed 0x00000003,fr11 + + mcuti acc0,-30,fr11 + test_fr_iimmed 0x00000001,fr11 + + mcuti acc0,-31,fr11 + test_fr_iimmed 0x00000000,fr11 + + mcuti acc0,-32,fr11 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mcuti acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mcuti acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mcuti acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + mcuti acc0,-4,fr11 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + mcuti acc0,-7,fr11 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/frv/mcutss.cgs b/sim/testsuite/frv/mcutss.cgs new file mode 100644 index 0000000..efe3278 --- /dev/null +++ b/sim/testsuite/frv/mcutss.cgs @@ -0,0 +1,505 @@ +# frv testcase for mcutss $ACC40i,$FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mcutss +mcutss: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + + set_fr_iimmed 0,0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + set_fr_iimmed 0,1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + set_fr_iimmed 0,2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + set_fr_iimmed 0,3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,10,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,11,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,12,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,13,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,14,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,15,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,19,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,20,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,21,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,22,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,23,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,24,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,25,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,26,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,27,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,28,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,29,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,30,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,31,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,64,fr10 ; same as 0 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + set_fr_iimmed 0xffff,0xffff,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xf3c4d5e6,fr11 + + set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xf9e26af3,fr11 + + set_fr_iimmed 0xffff,0xfffd,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfcf13579,fr11 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfe789abc,fr11 + + set_fr_iimmed 0xffff,0xfffb,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xff3c4d5e,fr11 + + set_fr_iimmed 0xffff,0xfffa,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xff9e26af,fr11 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffcf1357,fr11 + + set_fr_iimmed 0xffff,0xfff8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffe789ab,fr11 + + set_fr_iimmed 0xffff,0xfff7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfff3c4d5,fr11 + + set_fr_iimmed 0xffff,0xfff6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfff9e26a,fr11 + + set_fr_iimmed 0xffff,0xfff5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffcf135,fr11 + + set_fr_iimmed 0xffff,0xfff4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffe789a,fr11 + + set_fr_iimmed 0xffff,0xfff3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffff3c4d,fr11 + + set_fr_iimmed 0xffff,0xfff2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffff9e26,fr11 + + set_fr_iimmed 0xffff,0xfff1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffcf13,fr11 + + set_fr_iimmed 0xffff,0xfff0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffe789,fr11 + + set_fr_iimmed 0xffff,0xffef,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffff3c4,fr11 + + set_fr_iimmed 0xffff,0xffee,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffff9e2,fr11 + + set_fr_iimmed 0xffff,0xffed,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffcf1,fr11 + + set_fr_iimmed 0xffff,0xffec,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffe78,fr11 + + set_fr_iimmed 0xffff,0xffeb,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffff3c,fr11 + + set_fr_iimmed 0xffff,0xffea,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffff9e,fr11 + + set_fr_iimmed 0xffff,0xffe9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffcf,fr11 + + set_fr_iimmed 0xffff,0xffe8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffe7,fr11 + + set_fr_iimmed 0xffff,0xffe7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffff3,fr11 + + set_fr_iimmed 0xffff,0xffe6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffff9,fr11 + + set_fr_iimmed 0xffff,0xffe5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffffc,fr11 + + set_fr_iimmed 0xffff,0xffe4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffffe,fr11 + + set_fr_iimmed 0xffff,0xffe3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0,32,fr10 ; same as -32 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + + set_fr_iimmed 0xffff,0xffff,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x33c4d5e6,fr11 + + set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x19e26af3,fr11 + + set_fr_iimmed 0xffff,0xfffd,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0cf13579,fr11 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x06789abc,fr11 + + set_fr_iimmed 0xffff,0xfffb,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x033c4d5e,fr11 + + set_fr_iimmed 0xffff,0xfffa,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x019e26af,fr11 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00cf1357,fr11 + + set_fr_iimmed 0xffff,0xfff8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x006789ab,fr11 + + set_fr_iimmed 0xffff,0xfff7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0033c4d5,fr11 + + set_fr_iimmed 0xffff,0xfff6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0019e26a,fr11 + + set_fr_iimmed 0xffff,0xfff5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x000cf135,fr11 + + set_fr_iimmed 0xffff,0xfff4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0006789a,fr11 + + set_fr_iimmed 0xffff,0xfff3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00033c4d,fr11 + + set_fr_iimmed 0xffff,0xfff2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00019e26,fr11 + + set_fr_iimmed 0xffff,0xfff1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0000cf13,fr11 + + set_fr_iimmed 0xffff,0xfff0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00006789,fr11 + + set_fr_iimmed 0xffff,0xffef,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x000033c4,fr11 + + set_fr_iimmed 0xffff,0xffee,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x000019e2,fr11 + + set_fr_iimmed 0xffff,0xffed,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000cf1,fr11 + + set_fr_iimmed 0xffff,0xffec,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000678,fr11 + + set_fr_iimmed 0xffff,0xffeb,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0000033c,fr11 + + set_fr_iimmed 0xffff,0xffea,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0000019e,fr11 + + set_fr_iimmed 0xffff,0xffe9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x000000cf,fr11 + + set_fr_iimmed 0xffff,0xffe8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000067,fr11 + + set_fr_iimmed 0xffff,0xffe7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000033,fr11 + + set_fr_iimmed 0xffff,0xffe6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000019,fr11 + + set_fr_iimmed 0xffff,0xffe5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0000000c,fr11 + + set_fr_iimmed 0xffff,0xffe4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000006,fr11 + + set_fr_iimmed 0xffff,0xffe3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000003,fr11 + + set_fr_iimmed 0xffff,0xffe2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000001,fr11 + + set_fr_iimmed 0xffff,0xffe1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + set_fr_iimmed 0xffff,0xffe0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + set_fr_iimmed 0,32,fr10 ; same as -32 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_fr_iimmed 0,18,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_fr_iimmed 0,18,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/frv/mcutssi.cgs b/sim/testsuite/frv/mcutssi.cgs new file mode 100644 index 0000000..739912f --- /dev/null +++ b/sim/testsuite/frv/mcutssi.cgs @@ -0,0 +1,380 @@ +# frv testcase for mcutssi $ACC40i,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mcutssi +mcutssi: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + + mcutssi acc0,0,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + mcutssi acc0,1,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + mcutssi acc0,2,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + mcutssi acc0,3,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,4,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,5,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,6,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,7,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,8,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,9,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,10,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,11,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,12,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,13,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,14,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,15,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,19,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,20,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,21,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,22,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,23,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,24,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,25,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,26,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,27,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,28,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,29,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,30,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,31,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,-1,fr11 + test_fr_iimmed 0xf3c4d5e6,fr11 + + mcutssi acc0,-2,fr11 + test_fr_iimmed 0xf9e26af3,fr11 + + mcutssi acc0,-3,fr11 + test_fr_iimmed 0xfcf13579,fr11 + + mcutssi acc0,-4,fr11 + test_fr_iimmed 0xfe789abc,fr11 + + mcutssi acc0,-5,fr11 + test_fr_iimmed 0xff3c4d5e,fr11 + + mcutssi acc0,-6,fr11 + test_fr_iimmed 0xff9e26af,fr11 + + mcutssi acc0,-7,fr11 + test_fr_iimmed 0xffcf1357,fr11 + + mcutssi acc0,-8,fr11 + test_fr_iimmed 0xffe789ab,fr11 + + mcutssi acc0,-9,fr11 + test_fr_iimmed 0xfff3c4d5,fr11 + + mcutssi acc0,-10,fr11 + test_fr_iimmed 0xfff9e26a,fr11 + + mcutssi acc0,-11,fr11 + test_fr_iimmed 0xfffcf135,fr11 + + mcutssi acc0,-12,fr11 + test_fr_iimmed 0xfffe789a,fr11 + + mcutssi acc0,-13,fr11 + test_fr_iimmed 0xffff3c4d,fr11 + + mcutssi acc0,-14,fr11 + test_fr_iimmed 0xffff9e26,fr11 + + mcutssi acc0,-15,fr11 + test_fr_iimmed 0xffffcf13,fr11 + + mcutssi acc0,-16,fr11 + test_fr_iimmed 0xffffe789,fr11 + + mcutssi acc0,-17,fr11 + test_fr_iimmed 0xfffff3c4,fr11 + + mcutssi acc0,-18,fr11 + test_fr_iimmed 0xfffff9e2,fr11 + + mcutssi acc0,-19,fr11 + test_fr_iimmed 0xfffffcf1,fr11 + + mcutssi acc0,-20,fr11 + test_fr_iimmed 0xfffffe78,fr11 + + mcutssi acc0,-21,fr11 + test_fr_iimmed 0xffffff3c,fr11 + + mcutssi acc0,-22,fr11 + test_fr_iimmed 0xffffff9e,fr11 + + mcutssi acc0,-23,fr11 + test_fr_iimmed 0xffffffcf,fr11 + + mcutssi acc0,-24,fr11 + test_fr_iimmed 0xffffffe7,fr11 + + mcutssi acc0,-25,fr11 + test_fr_iimmed 0xfffffff3,fr11 + + mcutssi acc0,-26,fr11 + test_fr_iimmed 0xfffffff9,fr11 + + mcutssi acc0,-27,fr11 + test_fr_iimmed 0xfffffffc,fr11 + + mcutssi acc0,-28,fr11 + test_fr_iimmed 0xfffffffe,fr11 + + mcutssi acc0,-29,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcutssi acc0,-30,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcutssi acc0,-31,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcutssi acc0,-32,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + + mcutssi acc0,-1,fr11 + test_fr_iimmed 0x33c4d5e6,fr11 + + mcutssi acc0,-2,fr11 + test_fr_iimmed 0x19e26af3,fr11 + + mcutssi acc0,-3,fr11 + test_fr_iimmed 0x0cf13579,fr11 + + mcutssi acc0,-4,fr11 + test_fr_iimmed 0x06789abc,fr11 + + mcutssi acc0,-5,fr11 + test_fr_iimmed 0x033c4d5e,fr11 + + mcutssi acc0,-6,fr11 + test_fr_iimmed 0x019e26af,fr11 + + mcutssi acc0,-7,fr11 + test_fr_iimmed 0x00cf1357,fr11 + + mcutssi acc0,-8,fr11 + test_fr_iimmed 0x006789ab,fr11 + + mcutssi acc0,-9,fr11 + test_fr_iimmed 0x0033c4d5,fr11 + + mcutssi acc0,-10,fr11 + test_fr_iimmed 0x0019e26a,fr11 + + mcutssi acc0,-11,fr11 + test_fr_iimmed 0x000cf135,fr11 + + mcutssi acc0,-12,fr11 + test_fr_iimmed 0x0006789a,fr11 + + mcutssi acc0,-13,fr11 + test_fr_iimmed 0x00033c4d,fr11 + + mcutssi acc0,-14,fr11 + test_fr_iimmed 0x00019e26,fr11 + + mcutssi acc0,-15,fr11 + test_fr_iimmed 0x0000cf13,fr11 + + mcutssi acc0,-16,fr11 + test_fr_iimmed 0x00006789,fr11 + + mcutssi acc0,-17,fr11 + test_fr_iimmed 0x000033c4,fr11 + + mcutssi acc0,-18,fr11 + test_fr_iimmed 0x000019e2,fr11 + + mcutssi acc0,-19,fr11 + test_fr_iimmed 0x00000cf1,fr11 + + mcutssi acc0,-20,fr11 + test_fr_iimmed 0x00000678,fr11 + + mcutssi acc0,-21,fr11 + test_fr_iimmed 0x0000033c,fr11 + + mcutssi acc0,-22,fr11 + test_fr_iimmed 0x0000019e,fr11 + + mcutssi acc0,-23,fr11 + test_fr_iimmed 0x000000cf,fr11 + + mcutssi acc0,-24,fr11 + test_fr_iimmed 0x00000067,fr11 + + mcutssi acc0,-25,fr11 + test_fr_iimmed 0x00000033,fr11 + + mcutssi acc0,-26,fr11 + test_fr_iimmed 0x00000019,fr11 + + mcutssi acc0,-27,fr11 + test_fr_iimmed 0x0000000c,fr11 + + mcutssi acc0,-28,fr11 + test_fr_iimmed 0x00000006,fr11 + + mcutssi acc0,-29,fr11 + test_fr_iimmed 0x00000003,fr11 + + mcutssi acc0,-30,fr11 + test_fr_iimmed 0x00000001,fr11 + + mcutssi acc0,-31,fr11 + test_fr_iimmed 0x00000000,fr11 + + mcutssi acc0,-32,fr11 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mcutssi acc0,17,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mcutssi acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mcutssi acc0,18,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + mcutssi acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + mcutssi acc0,-4,fr11 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + mcutssi acc0,-7,fr11 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/frv/mdaddaccs.cgs b/sim/testsuite/frv/mdaddaccs.cgs new file mode 100644 index 0000000..553c4a7 --- /dev/null +++ b/sim/testsuite/frv/mdaddaccs.cgs @@ -0,0 +1,102 @@ +# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mdaddaccs +mdaddaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdead,0xbeef,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0xbeef,0xdead,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x2345,0x6789,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xfffffffe,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/frv/mdasaccs.cgs b/sim/testsuite/frv/mdasaccs.cgs new file mode 100644 index 0000000..0535b62 --- /dev/null +++ b/sim/testsuite/frv/mdasaccs.cgs @@ -0,0 +1,122 @@ +# frv testcase for mdasaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mdasaccs +mdasaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xdead,0xbeef,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0xbeef,0xdead,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x4111,0xdead,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x2345,0x6789,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x1234,0x5677,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x1234,0x5679,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xfffffffe,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0xa,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffc,0x7ffd,acc1 + test_accg_immed 0x80,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0003,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + + pass diff --git a/sim/testsuite/frv/mdcutssi.cgs b/sim/testsuite/frv/mdcutssi.cgs new file mode 100644 index 0000000..8e5216c --- /dev/null +++ b/sim/testsuite/frv/mdcutssi.cgs @@ -0,0 +1,513 @@ +# frv testcase for mdcutssi $ACC40i,$s6,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global mdcutssi +mdcutssi: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + set_accg_immed 0xffffffe7,accg1 + set_acc_immed 0x89abcdef,acc1 + + mdcutssi acc0,0,fr10 + test_fr_iimmed 0xe789abcd,fr10 + test_fr_iimmed 0xe789abcd,fr11 + + mdcutssi acc0,1,fr10 + test_fr_iimmed 0xcf13579b,fr10 + test_fr_iimmed 0xcf13579b,fr11 + + mdcutssi acc0,2,fr10 + test_fr_iimmed 0x9e26af37,fr10 + test_fr_iimmed 0x9e26af37,fr11 + + mdcutssi acc0,3,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,4,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,5,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,6,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,7,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,8,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,9,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,10,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,11,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,12,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,13,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,14,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,15,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,18,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,19,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,20,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,21,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,22,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,23,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,24,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,25,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,26,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,27,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,28,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,29,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,30,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,31,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,-1,fr10 + test_fr_iimmed 0xf3c4d5e6,fr10 + test_fr_iimmed 0xf3c4d5e6,fr11 + + mdcutssi acc0,-2,fr10 + test_fr_iimmed 0xf9e26af3,fr10 + test_fr_iimmed 0xf9e26af3,fr11 + + mdcutssi acc0,-3,fr10 + test_fr_iimmed 0xfcf13579,fr10 + test_fr_iimmed 0xfcf13579,fr11 + + mdcutssi acc0,-4,fr10 + test_fr_iimmed 0xfe789abc,fr10 + test_fr_iimmed 0xfe789abc,fr11 + + mdcutssi acc0,-5,fr10 + test_fr_iimmed 0xff3c4d5e,fr10 + test_fr_iimmed 0xff3c4d5e,fr11 + + mdcutssi acc0,-6,fr10 + test_fr_iimmed 0xff9e26af,fr10 + test_fr_iimmed 0xff9e26af,fr11 + + mdcutssi acc0,-7,fr10 + test_fr_iimmed 0xffcf1357,fr10 + test_fr_iimmed 0xffcf1357,fr11 + + mdcutssi acc0,-8,fr10 + test_fr_iimmed 0xffe789ab,fr10 + test_fr_iimmed 0xffe789ab,fr11 + + mdcutssi acc0,-9,fr10 + test_fr_iimmed 0xfff3c4d5,fr10 + test_fr_iimmed 0xfff3c4d5,fr11 + + mdcutssi acc0,-10,fr10 + test_fr_iimmed 0xfff9e26a,fr10 + test_fr_iimmed 0xfff9e26a,fr11 + + mdcutssi acc0,-11,fr10 + test_fr_iimmed 0xfffcf135,fr10 + test_fr_iimmed 0xfffcf135,fr11 + + mdcutssi acc0,-12,fr10 + test_fr_iimmed 0xfffe789a,fr10 + test_fr_iimmed 0xfffe789a,fr11 + + mdcutssi acc0,-13,fr10 + test_fr_iimmed 0xffff3c4d,fr10 + test_fr_iimmed 0xffff3c4d,fr11 + + mdcutssi acc0,-14,fr10 + test_fr_iimmed 0xffff9e26,fr10 + test_fr_iimmed 0xffff9e26,fr11 + + mdcutssi acc0,-15,fr10 + test_fr_iimmed 0xffffcf13,fr10 + test_fr_iimmed 0xffffcf13,fr11 + + mdcutssi acc0,-16,fr10 + test_fr_iimmed 0xffffe789,fr10 + test_fr_iimmed 0xffffe789,fr11 + + mdcutssi acc0,-17,fr10 + test_fr_iimmed 0xfffff3c4,fr10 + test_fr_iimmed 0xfffff3c4,fr11 + + mdcutssi acc0,-18,fr10 + test_fr_iimmed 0xfffff9e2,fr10 + test_fr_iimmed 0xfffff9e2,fr11 + + mdcutssi acc0,-19,fr10 + test_fr_iimmed 0xfffffcf1,fr10 + test_fr_iimmed 0xfffffcf1,fr11 + + mdcutssi acc0,-20,fr10 + test_fr_iimmed 0xfffffe78,fr10 + test_fr_iimmed 0xfffffe78,fr11 + + mdcutssi acc0,-21,fr10 + test_fr_iimmed 0xffffff3c,fr10 + test_fr_iimmed 0xffffff3c,fr11 + + mdcutssi acc0,-22,fr10 + test_fr_iimmed 0xffffff9e,fr10 + test_fr_iimmed 0xffffff9e,fr11 + + mdcutssi acc0,-23,fr10 + test_fr_iimmed 0xffffffcf,fr10 + test_fr_iimmed 0xffffffcf,fr11 + + mdcutssi acc0,-24,fr10 + test_fr_iimmed 0xffffffe7,fr10 + test_fr_iimmed 0xffffffe7,fr11 + + mdcutssi acc0,-25,fr10 + test_fr_iimmed 0xfffffff3,fr10 + test_fr_iimmed 0xfffffff3,fr11 + + mdcutssi acc0,-26,fr10 + test_fr_iimmed 0xfffffff9,fr10 + test_fr_iimmed 0xfffffff9,fr11 + + mdcutssi acc0,-27,fr10 + test_fr_iimmed 0xfffffffc,fr10 + test_fr_iimmed 0xfffffffc,fr11 + + mdcutssi acc0,-28,fr10 + test_fr_iimmed 0xfffffffe,fr10 + test_fr_iimmed 0xfffffffe,fr11 + + mdcutssi acc0,-29,fr10 + test_fr_iimmed 0xffffffff,fr10 + test_fr_iimmed 0xffffffff,fr11 + + mdcutssi acc0,-30,fr10 + test_fr_iimmed 0xffffffff,fr10 + test_fr_iimmed 0xffffffff,fr11 + + mdcutssi acc0,-31,fr10 + test_fr_iimmed 0xffffffff,fr10 + test_fr_iimmed 0xffffffff,fr11 + + mdcutssi acc0,-32,fr10 + test_fr_iimmed 0xffffffff,fr10 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + set_accg_immed 0xffffff67,accg1 + set_acc_immed 0x89abcdef,acc1 + + mdcutssi acc0,-1,fr10 + test_fr_iimmed 0x33c4d5e6,fr10 + test_fr_iimmed 0x33c4d5e6,fr11 + + mdcutssi acc0,-2,fr10 + test_fr_iimmed 0x19e26af3,fr10 + test_fr_iimmed 0x19e26af3,fr11 + + mdcutssi acc0,-3,fr10 + test_fr_iimmed 0x0cf13579,fr10 + test_fr_iimmed 0x0cf13579,fr11 + + mdcutssi acc0,-4,fr10 + test_fr_iimmed 0x06789abc,fr10 + test_fr_iimmed 0x06789abc,fr11 + + mdcutssi acc0,-5,fr10 + test_fr_iimmed 0x033c4d5e,fr10 + test_fr_iimmed 0x033c4d5e,fr11 + + mdcutssi acc0,-6,fr10 + test_fr_iimmed 0x019e26af,fr10 + test_fr_iimmed 0x019e26af,fr11 + + mdcutssi acc0,-7,fr10 + test_fr_iimmed 0x00cf1357,fr10 + test_fr_iimmed 0x00cf1357,fr11 + + mdcutssi acc0,-8,fr10 + test_fr_iimmed 0x006789ab,fr10 + test_fr_iimmed 0x006789ab,fr11 + + mdcutssi acc0,-9,fr10 + test_fr_iimmed 0x0033c4d5,fr10 + test_fr_iimmed 0x0033c4d5,fr11 + + mdcutssi acc0,-10,fr10 + test_fr_iimmed 0x0019e26a,fr10 + test_fr_iimmed 0x0019e26a,fr11 + + mdcutssi acc0,-11,fr10 + test_fr_iimmed 0x000cf135,fr10 + test_fr_iimmed 0x000cf135,fr11 + + mdcutssi acc0,-12,fr10 + test_fr_iimmed 0x0006789a,fr10 + test_fr_iimmed 0x0006789a,fr11 + + mdcutssi acc0,-13,fr10 + test_fr_iimmed 0x00033c4d,fr10 + test_fr_iimmed 0x00033c4d,fr11 + + mdcutssi acc0,-14,fr10 + test_fr_iimmed 0x00019e26,fr10 + test_fr_iimmed 0x00019e26,fr11 + + mdcutssi acc0,-15,fr10 + test_fr_iimmed 0x0000cf13,fr10 + test_fr_iimmed 0x0000cf13,fr11 + + mdcutssi acc0,-16,fr10 + test_fr_iimmed 0x00006789,fr10 + test_fr_iimmed 0x00006789,fr11 + + mdcutssi acc0,-17,fr10 + test_fr_iimmed 0x000033c4,fr10 + test_fr_iimmed 0x000033c4,fr11 + + mdcutssi acc0,-18,fr10 + test_fr_iimmed 0x000019e2,fr10 + test_fr_iimmed 0x000019e2,fr11 + + mdcutssi acc0,-19,fr10 + test_fr_iimmed 0x00000cf1,fr10 + test_fr_iimmed 0x00000cf1,fr11 + + mdcutssi acc0,-20,fr10 + test_fr_iimmed 0x00000678,fr10 + test_fr_iimmed 0x00000678,fr11 + + mdcutssi acc0,-21,fr10 + test_fr_iimmed 0x0000033c,fr10 + test_fr_iimmed 0x0000033c,fr11 + + mdcutssi acc0,-22,fr10 + test_fr_iimmed 0x0000019e,fr10 + test_fr_iimmed 0x0000019e,fr11 + + mdcutssi acc0,-23,fr10 + test_fr_iimmed 0x000000cf,fr10 + test_fr_iimmed 0x000000cf,fr11 + + mdcutssi acc0,-24,fr10 + test_fr_iimmed 0x00000067,fr10 + test_fr_iimmed 0x00000067,fr11 + + mdcutssi acc0,-25,fr10 + test_fr_iimmed 0x00000033,fr10 + test_fr_iimmed 0x00000033,fr11 + + mdcutssi acc0,-26,fr10 + test_fr_iimmed 0x00000019,fr10 + test_fr_iimmed 0x00000019,fr11 + + mdcutssi acc0,-27,fr10 + test_fr_iimmed 0x0000000c,fr10 + test_fr_iimmed 0x0000000c,fr11 + + mdcutssi acc0,-28,fr10 + test_fr_iimmed 0x00000006,fr10 + test_fr_iimmed 0x00000006,fr11 + + mdcutssi acc0,-29,fr10 + test_fr_iimmed 0x00000003,fr10 + test_fr_iimmed 0x00000003,fr11 + + mdcutssi acc0,-30,fr10 + test_fr_iimmed 0x00000001,fr10 + test_fr_iimmed 0x00000001,fr11 + + mdcutssi acc0,-31,fr10 + test_fr_iimmed 0x00000000,fr10 + test_fr_iimmed 0x00000000,fr11 + + mdcutssi acc0,-32,fr10 + test_fr_iimmed 0x00000000,fr10 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + set_accg_immed 0xffffffff,accg1 + set_acc_immed 0xffe00000,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0xe0000000,fr10 + test_fr_iimmed 0xe0000000,fr11 + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0xc0000000,fr10 + test_fr_iimmed 0xc0000000,fr11 + + mdcutssi acc0,18,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x003fffff,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x3fffff00,fr10 + test_fr_iimmed 0x3fffff00,fr11 + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x7ffffe00,fr10 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffe00000,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mdcutssi acc0,18,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + set_accg_immed 0x08,accg1 + set_acc_immed 0x003fffff,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xefe00000,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + mdcutssi acc0,18,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0x003fffff,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + set_accg_immed 0xffffffaf,accg1 + set_acc_immed 0x5a5a5a5a,acc1 + + mdcutssi acc0,-4,fr10 + test_fr_iimmed 0xfaf5a5a5,fr10 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + set_accg_immed 0x0000002f,accg1 + set_acc_immed 0x5a5a5a5a,acc1 + + mdcutssi acc0,-7,fr10 + test_fr_iimmed 0x005eb4b4,fr10 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/frv/mdpackh.cgs b/sim/testsuite/frv/mdpackh.cgs new file mode 100644 index 0000000..cbd0bc8 --- /dev/null +++ b/sim/testsuite/frv/mdpackh.cgs @@ -0,0 +1,18 @@ +# frv testcase for mdpackh $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global mdpackh +mdpackh: + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0xaaaa,0xbbbb,fr11 + set_fr_iimmed 0x1234,0x5678,fr12 + set_fr_iimmed 0xcccc,0xdddd,fr13 + mdpackh fr10,fr12,fr14 + test_fr_limmed 0xbeef,0x5678,fr14 + test_fr_limmed 0xbbbb,0xdddd,fr15 + + pass diff --git a/sim/testsuite/frv/mdrotli.cgs b/sim/testsuite/frv/mdrotli.cgs new file mode 100644 index 0000000..1d2e183 --- /dev/null +++ b/sim/testsuite/frv/mdrotli.cgs @@ -0,0 +1,34 @@ +# frv testcase for mdrotli $FRi,$s6,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global mdrotli +mdrotli: + set_fr_iimmed 0,2,fr8 + set_fr_iimmed 0,2,fr9 + mdrotli fr8,-32,fr8 ; Shift by 0 + test_fr_iimmed 2,fr8 + test_fr_iimmed 2,fr9 + + set_fr_iimmed 0,2,fr8 + set_fr_iimmed 0,2,fr9 + mdrotli fr8,1,fr8 ; Shift by 1 + test_fr_iimmed 4,fr8 + test_fr_iimmed 4,fr9 + + set_fr_iimmed 0,1,fr8 + set_fr_iimmed 0,2,fr9 + mdrotli fr8,31,fr8 ; Shift by 31 + test_fr_iimmed 0x80000000,fr8 + test_fr_iimmed 1,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + mdrotli fr8,16,fr8 + test_fr_iimmed 0xbeefdead,fr8 + test_fr_iimmed 0xdeadbeef,fr9 + + pass diff --git a/sim/testsuite/frv/mdsubaccs.cgs b/sim/testsuite/frv/mdsubaccs.cgs new file mode 100644 index 0000000..73d2e2d --- /dev/null +++ b/sim/testsuite/frv/mdsubaccs.cgs @@ -0,0 +1,102 @@ +# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mdsubaccs +mdsubaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg2 + test_acc_limmed 0x4111,0xdead,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg2 + test_acc_limmed 0x1234,0x5679,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffffffe,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x00000002,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0x00000000,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/frv/mdunpackh.cgs b/sim/testsuite/frv/mdunpackh.cgs new file mode 100644 index 0000000..02870c8 --- /dev/null +++ b/sim/testsuite/frv/mdunpackh.cgs @@ -0,0 +1,26 @@ +# frv testcase for mdunpackh $FRi,$FRj +# mach: frv + + .include "testutils.inc" + + start + + .global mdunpackh +mdunpackh: + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + mdunpackh fr10,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + test_fr_limmed 0x1234,0x1234,fr14 + test_fr_limmed 0x5678,0x5678,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + mdunpackh fr10,fr12 + test_fr_limmed 0x1234,0x1234,fr12 + test_fr_limmed 0x5678,0x5678,fr13 + test_fr_limmed 0xdead,0xdead,fr14 + test_fr_limmed 0xbeef,0xbeef,fr15 + + pass diff --git a/sim/testsuite/frv/membar.cgs b/sim/testsuite/frv/membar.cgs new file mode 100644 index 0000000..aae1d1a --- /dev/null +++ b/sim/testsuite/frv/membar.cgs @@ -0,0 +1,12 @@ +# frv testcase for membar +# mach: all + + .include "testutils.inc" + + start + + .global membar +membar: + membar + + pass diff --git a/sim/testsuite/frv/mexpdhd.cgs b/sim/testsuite/frv/mexpdhd.cgs new file mode 100644 index 0000000..d5f95ce --- /dev/null +++ b/sim/testsuite/frv/mexpdhd.cgs @@ -0,0 +1,27 @@ +# frv testcase for mexpdhd $FRi,$s6,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global mexpdhd +mexpdhd: + set_fr_iimmed 0xdead,0xbeef,fr10 + mexpdhd fr10,0,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + mexpdhd fr10,1,fr12 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + mexpdhd fr10,62,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + mexpdhd fr10,63,fr12 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + pass diff --git a/sim/testsuite/frv/mexpdhw.cgs b/sim/testsuite/frv/mexpdhw.cgs new file mode 100644 index 0000000..a13b0f2 --- /dev/null +++ b/sim/testsuite/frv/mexpdhw.cgs @@ -0,0 +1,23 @@ +# frv testcase for mexpdhw $FRi,$s6,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global mexpdhw +mexpdhw: + set_fr_iimmed 0xdead,0xbeef,fr10 + mexpdhw fr10,0,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + + mexpdhw fr10,1,fr12 + test_fr_limmed 0xbeef,0xbeef,fr12 + + mexpdhw fr10,62,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + + mexpdhw fr10,63,fr12 + test_fr_limmed 0xbeef,0xbeef,fr12 + + pass diff --git a/sim/testsuite/frv/mhdseth.cgs b/sim/testsuite/frv/mhdseth.cgs new file mode 100644 index 0000000..7c09b2d --- /dev/null +++ b/sim/testsuite/frv/mhdseth.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhdseth $s5,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhdseth 0,fr1 + test_fr_limmed 0x06ad,0x06ef,fr1 + + mhdseth 1,fr1 + test_fr_limmed 0x0ead,0x0eef,fr1 + + mhdseth 0xf,fr1 + test_fr_limmed 0x7ead,0x7eef,fr1 + + mhdseth -16,fr1 + test_fr_limmed 0x86ad,0x86ef,fr1 + + mhdseth -1,fr1 + test_fr_limmed 0xfead,0xfeef,fr1 + + pass diff --git a/sim/testsuite/frv/mhdsets.cgs b/sim/testsuite/frv/mhdsets.cgs new file mode 100644 index 0000000..1f26814 --- /dev/null +++ b/sim/testsuite/frv/mhdsets.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhdsets $u12,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhdsets 0,fr1 + test_fr_limmed 0x0000,0x0000,fr1 + + mhdsets 1,fr1 + test_fr_limmed 0x0001,0x0001,fr1 + + mhdsets 0x07ff,fr1 + test_fr_limmed 0x07ff,0x07ff,fr1 + + mhdsets -2048,fr1 + test_fr_limmed 0xf800,0xf800,fr1 + + mhdsets -1,fr1 + test_fr_limmed 0xffff,0xffff,fr1 + + pass diff --git a/sim/testsuite/frv/mhsethih.cgs b/sim/testsuite/frv/mhsethih.cgs new file mode 100644 index 0000000..f05eb77 --- /dev/null +++ b/sim/testsuite/frv/mhsethih.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhsethih $s5,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhsethih 0,fr1 + test_fr_limmed 0x06ad,0xbeef,fr1 + + mhsethih 1,fr1 + test_fr_limmed 0x0ead,0xbeef,fr1 + + mhsethih 0xf,fr1 + test_fr_limmed 0x7ead,0xbeef,fr1 + + mhsethih -16,fr1 + test_fr_limmed 0x86ad,0xbeef,fr1 + + mhsethih -1,fr1 + test_fr_limmed 0xfead,0xbeef,fr1 + + pass diff --git a/sim/testsuite/frv/mhsethis.cgs b/sim/testsuite/frv/mhsethis.cgs new file mode 100644 index 0000000..cf89336 --- /dev/null +++ b/sim/testsuite/frv/mhsethis.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhsethis $u12,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhsethis 0,fr1 + test_fr_limmed 0x0000,0xbeef,fr1 + + mhsethis 1,fr1 + test_fr_limmed 0x0001,0xbeef,fr1 + + mhsethis 0x07ff,fr1 + test_fr_limmed 0x07ff,0xbeef,fr1 + + mhsethis -2048,fr1 + test_fr_limmed 0xf800,0xbeef,fr1 + + mhsethis -1,fr1 + test_fr_limmed 0xffff,0xbeef,fr1 + + pass diff --git a/sim/testsuite/frv/mhsetloh.cgs b/sim/testsuite/frv/mhsetloh.cgs new file mode 100644 index 0000000..930628d --- /dev/null +++ b/sim/testsuite/frv/mhsetloh.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhsetloh $s5,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhsetloh 0,fr1 + test_fr_limmed 0xdead,0x06ef,fr1 + + mhsetloh 1,fr1 + test_fr_limmed 0xdead,0x0eef,fr1 + + mhsetloh 0xf,fr1 + test_fr_limmed 0xdead,0x7eef,fr1 + + mhsetloh -16,fr1 + test_fr_limmed 0xdead,0x86ef,fr1 + + mhsetloh -1,fr1 + test_fr_limmed 0xdead,0xfeef,fr1 + + pass diff --git a/sim/testsuite/frv/mhsetlos.cgs b/sim/testsuite/frv/mhsetlos.cgs new file mode 100644 index 0000000..fb404a2 --- /dev/null +++ b/sim/testsuite/frv/mhsetlos.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhsetlos $u12,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhsetlos 0,fr1 + test_fr_limmed 0xdead,0x0000,fr1 + + mhsetlos 1,fr1 + test_fr_limmed 0xdead,0x0001,fr1 + + mhsetlos 0x07ff,fr1 + test_fr_limmed 0xdead,0x07ff,fr1 + + mhsetlos -2048,fr1 + test_fr_limmed 0xdead,0xf800,fr1 + + mhsetlos -1,fr1 + test_fr_limmed 0xdead,0xffff,fr1 + + pass diff --git a/sim/testsuite/frv/mhtob.cgs b/sim/testsuite/frv/mhtob.cgs new file mode 100644 index 0000000..efd83d7 --- /dev/null +++ b/sim/testsuite/frv/mhtob.cgs @@ -0,0 +1,25 @@ +# frv testcase for mhtob $FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mhtob +mhtob: + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + mhtob fr10,fr12 + test_fr_limmed 0xadef,0x3478,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 ; saturation + set_fr_iimmed 0x1234,0x5678,fr11 + mhtob fr10,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 ; saturation + set_fr_iimmed 0x10ad,0x80ef,fr11 + mhtob fr10,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + + pass diff --git a/sim/testsuite/frv/misc.exp b/sim/testsuite/frv/misc.exp new file mode 100644 index 0000000..4245a81 --- /dev/null +++ b/sim/testsuite/frv/misc.exp @@ -0,0 +1,19 @@ +# Miscellaneous FRV simulator testcases. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500 fr550 fr400 fr405 fr450" + set cpu_option -mcpu + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/frv/mmachs.cgs b/sim/testsuite/frv/mmachs.cgs new file mode 100644 index 0000000..0292161 --- /dev/null +++ b/sim/testsuite/frv/mmachs.cgs @@ -0,0 +1,259 @@ +# frv testcase for mmachs $GRi,$GRj,$ACCk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mmachs +mmachs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmachs fr7,fr8,acc0 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/frv/mmachu.cgs b/sim/testsuite/frv/mmachu.cgs new file mode 100644 index 0000000..aad07c7 --- /dev/null +++ b/sim/testsuite/frv/mmachu.cgs @@ -0,0 +1,146 @@ +# frv testcase for mmachu $GRi,$GRj,$GRk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mmachu +mmachu: + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + pass diff --git a/sim/testsuite/frv/mmrdhs.cgs b/sim/testsuite/frv/mmrdhs.cgs new file mode 100644 index 0000000..6295bc1 --- /dev/null +++ b/sim/testsuite/frv/mmrdhs.cgs @@ -0,0 +1,263 @@ +# frv testcase for mmrdhs $GRi,$GRj,$ACCk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mmrdhs +mmrdhs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed -8,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x7ffa,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xfffe,0xfffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xfffe,0xfffa,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xbfff,0xfff9,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xbfff,0xfff9,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xbfff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xbfff,0xffff,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x0001,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x0001,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x0001,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x0001,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x4003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x4003,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0xc003,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4003,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x4003,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x3ffd,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x3ffb,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed 0xc0013ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xc0013ffa,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed 0x80013ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0x80013ffa,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 0xffff,1,fr7 + set_fr_iimmed 1,0xffff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x8000,0x0000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0,1,fr7 + set_fr_iimmed 1,1,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/frv/mmrdhu.cgs b/sim/testsuite/frv/mmrdhu.cgs new file mode 100644 index 0000000..b1c0243 --- /dev/null +++ b/sim/testsuite/frv/mmrdhu.cgs @@ -0,0 +1,151 @@ +# frv testcase for mmrdhu $GRi,$GRj,$GRk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mmrdhu +mmrdhu: + set_accg_immed 0x80,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffffa,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffff8,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffff8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffff8,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffff8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0x7ffa,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xfffe,0xfffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffe,0xfffa,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xfffd,0xfffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffd,0xfffa,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xbffe,0xfff9,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xbffe,0xfff9,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0x7ffe,0xfff9,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0x7ffe,0xfff9,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7e,accg0 + test_acc_limmed 0x8000,0xfff8,acc0 + test_accg_immed 0x7e,accg1 + test_acc_limmed 0x8000,0xfff8,acc1 + + set_accg_immed 0,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0xffff,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/frv/mmulhs.cgs b/sim/testsuite/frv/mmulhs.cgs new file mode 100644 index 0000000..2104500 --- /dev/null +++ b/sim/testsuite/frv/mmulhs.cgs @@ -0,0 +1,141 @@ +# frv testcase for mmulhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mmulhs +mmulhs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -2,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffe,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffe,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + pass diff --git a/sim/testsuite/frv/mmulhu.cgs b/sim/testsuite/frv/mmulhu.cgs new file mode 100644 index 0000000..53e9b70 --- /dev/null +++ b/sim/testsuite/frv/mmulhu.cgs @@ -0,0 +1,82 @@ +# frv testcase for mmulhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mmulhu +mmulhu: + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00010000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + + pass diff --git a/sim/testsuite/frv/mmulxhs.cgs b/sim/testsuite/frv/mmulxhs.cgs new file mode 100644 index 0000000..449becf --- /dev/null +++ b/sim/testsuite/frv/mmulxhs.cgs @@ -0,0 +1,141 @@ +# frv testcase for mmulxhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mmulxhs +mmulxhs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 4,acc0 + test_accg_immed 0,accg1 + test_acc_immed 9,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x4000,2,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -2,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffe,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffe,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + pass diff --git a/sim/testsuite/frv/mmulxhu.cgs b/sim/testsuite/frv/mmulxhu.cgs new file mode 100644 index 0000000..866b64e --- /dev/null +++ b/sim/testsuite/frv/mmulxhu.cgs @@ -0,0 +1,82 @@ +# frv testcase for mmulxhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mmulxhu +mmulxhu: + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x4000,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 0x8000,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00010000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + + pass diff --git a/sim/testsuite/frv/mnop.cgs b/sim/testsuite/frv/mnop.cgs new file mode 100644 index 0000000..54dda66 --- /dev/null +++ b/sim/testsuite/frv/mnop.cgs @@ -0,0 +1,12 @@ +# frv testcase for mnop +# mach: all + + .include "testutils.inc" + + start + + .global mnop +mnop: + mnop + + pass diff --git a/sim/testsuite/frv/mnot.cgs b/sim/testsuite/frv/mnot.cgs new file mode 100644 index 0000000..3a90781 --- /dev/null +++ b/sim/testsuite/frv/mnot.cgs @@ -0,0 +1,18 @@ +# frv testcase for mnot $FRintj,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mnot +mnot: + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + mnot fr7,fr7 + test_fr_iimmed 0x55555555,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + mnot fr7,fr7 + test_fr_iimmed 0x21524110,fr7 + + pass diff --git a/sim/testsuite/frv/mor.cgs b/sim/testsuite/frv/mor.cgs new file mode 100644 index 0000000..72feaff --- /dev/null +++ b/sim/testsuite/frv/mor.cgs @@ -0,0 +1,25 @@ +# frv testcase for mor $FRinti,$FRintj,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mor +mor: + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + mor fr7,fr8,fr8 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + mor fr7,fr8,fr8 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + mor fr7,fr8,fr8 + test_fr_iimmed 0xdeadbeef,fr8 + + pass diff --git a/sim/testsuite/frv/mov.cgs b/sim/testsuite/frv/mov.cgs new file mode 100644 index 0000000..8a077eb --- /dev/null +++ b/sim/testsuite/frv/mov.cgs @@ -0,0 +1,18 @@ +# frv testcase for mov $GRi,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ori +ori: + set_gr_immed 0xdeadbeef,gr7 + set_gr_immed 0xbeefdead,gr8 + set_icc 0x08,0 + mov gr7,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0xdeadbeef,gr7 + test_gr_immed 0xdeadbeef,gr8 + + pass diff --git a/sim/testsuite/frv/movfg.cgs b/sim/testsuite/frv/movfg.cgs new file mode 100644 index 0000000..c3da00e --- /dev/null +++ b/sim/testsuite/frv/movfg.cgs @@ -0,0 +1,16 @@ +# frv testcase for movfg $FRk,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global movfg +movfg: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + movfg fr8,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/frv/movfgd.cgs b/sim/testsuite/frv/movfgd.cgs new file mode 100644 index 0000000..cc2d60d --- /dev/null +++ b/sim/testsuite/frv/movfgd.cgs @@ -0,0 +1,20 @@ +# frv testcase for movfgd $FRk,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global movfgd +movfgd: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + movfgd fr8,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + pass diff --git a/sim/testsuite/frv/movfgq.cgs b/sim/testsuite/frv/movfgq.cgs new file mode 100644 index 0000000..b3a90e8 --- /dev/null +++ b/sim/testsuite/frv/movfgq.cgs @@ -0,0 +1,29 @@ +# frv testcase for movfgq $FRk,$GRj +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global movfgq +movfgq: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + set_gr_limmed 0,0,gr10 + set_gr_limmed 0,0,gr11 + movfgq fr8,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_fr_limmed 0x1234,0x5678,fr10 + test_fr_limmed 0x9abc,0xdef0,fr11 + + pass diff --git a/sim/testsuite/frv/movgf.cgs b/sim/testsuite/frv/movgf.cgs new file mode 100644 index 0000000..40fae33 --- /dev/null +++ b/sim/testsuite/frv/movgf.cgs @@ -0,0 +1,16 @@ +# frv testcase for movgf $GRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global movgf +movgf: + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + movgf gr8,fr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/frv/movgfd.cgs b/sim/testsuite/frv/movgfd.cgs new file mode 100644 index 0000000..df844cc --- /dev/null +++ b/sim/testsuite/frv/movgfd.cgs @@ -0,0 +1,20 @@ +# frv testcase for movgfd $GRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global movgfd +movgfd: + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + movgfd gr8,fr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + pass diff --git a/sim/testsuite/frv/movgfq.cgs b/sim/testsuite/frv/movgfq.cgs new file mode 100644 index 0000000..0196133 --- /dev/null +++ b/sim/testsuite/frv/movgfq.cgs @@ -0,0 +1,29 @@ +# frv testcase for movgfq $GRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global movgfq +movgfq: + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + set_fr_iimmed 0,0,fr10 + set_fr_iimmed 0,0,fr11 + movgfq gr8,fr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_fr_limmed 0x1234,0x5678,fr10 + test_fr_limmed 0x9abc,0xdef0,fr11 + + pass diff --git a/sim/testsuite/frv/movgs.cgs b/sim/testsuite/frv/movgs.cgs new file mode 100644 index 0000000..f9d2f54 --- /dev/null +++ b/sim/testsuite/frv/movgs.cgs @@ -0,0 +1,22 @@ +# frv testcase for movgs $GRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global movgs +movgs: + set_gr_limmed 0xdead,0xbeef,gr8 + and_spr_immed 0,lcr + movgs gr8,lcr + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,lcr + + ; try alternate names for lcr + and_spr_immed 0,273 + movgs gr8,spr[273] ; lcr is spr number 273 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[273] + + pass diff --git a/sim/testsuite/frv/movsg.cgs b/sim/testsuite/frv/movsg.cgs new file mode 100644 index 0000000..b26dbc1 --- /dev/null +++ b/sim/testsuite/frv/movsg.cgs @@ -0,0 +1,16 @@ +# frv testcase for movsg $FRk,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global movsg +movsg: + set_spr_limmed 0xdead,0xbeef,lcr + set_gr_limmed 0,0,gr8 + movsg lcr,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,lcr + + pass diff --git a/sim/testsuite/frv/mpackh.cgs b/sim/testsuite/frv/mpackh.cgs new file mode 100644 index 0000000..5a87cc6 --- /dev/null +++ b/sim/testsuite/frv/mpackh.cgs @@ -0,0 +1,15 @@ +# frv testcase for mpackh $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global mpackh +mpackh: + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + mpackh fr10,fr11,fr12 + test_fr_limmed 0xbeef,0x5678,fr12 + + pass diff --git a/sim/testsuite/frv/mqcpxis.cgs b/sim/testsuite/frv/mqcpxis.cgs new file mode 100644 index 0000000..397f533 --- /dev/null +++ b/sim/testsuite/frv/mqcpxis.cgs @@ -0,0 +1,103 @@ +# frv testcase for mqcpxis $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxis +mqcpxis: + ; Positive operands + set_fr_iimmed 2,4,fr8 ; multiply small numbers + set_fr_iimmed 5,3,fr10 + set_fr_iimmed 3,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result + set_fr_iimmed 0x0001,2,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7fff,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x2000,2,fr10 + set_fr_iimmed 0x7fff,0x0000,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xc000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr10 + set_fr_iimmed 0xfffe,2,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -9,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr10 + set_fr_iimmed 0x2001,0xffff,fr9 ; 15 bit result + set_fr_iimmed 0xffff,0xfffe,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbfff,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x8001,0x0000,acc1 + + ; Negative operands + set_fr_iimmed 0x8000,0x8000,fr8 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0xfffe,0xfffc,fr9 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0x00,accg0 + test_acc_limmed 0x8000,0x0000,acc0 + test_accg_immed 0x00,accg1 + test_acc_immed 26,acc1 + + set_fr_iimmed 0xffff,0xffff,fr8 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x0000,fr9 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x0000,fr8 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x0000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + pass diff --git a/sim/testsuite/frv/mqcpxiu.cgs b/sim/testsuite/frv/mqcpxiu.cgs new file mode 100644 index 0000000..22d48f6 --- /dev/null +++ b/sim/testsuite/frv/mqcpxiu.cgs @@ -0,0 +1,60 @@ +# frv testcase for mqcpxiu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxiu +mqcpxiu: + set_fr_iimmed 4,2,fr8 ; multiply small numbers + set_fr_iimmed 3,5,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 1,3,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + test_accg_immed 0,accg1 + test_acc_immed 5,acc1 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 0,2,fr10 + set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result + set_fr_iimmed 0x0001,2,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7fff,acc1 + + set_fr_iimmed 0x4000,1,fr8 ; 16 bit result + set_fr_iimmed 0x0001,2,fr10 + set_fr_iimmed 0x4000,1,fr9 ; 17 bit result + set_fr_iimmed 0x0001,4,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x0010001,acc1 + + set_fr_iimmed 0x7fff,0x0000,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0x0000,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 1,accg1 + test_acc_immed 0xfffc0002,acc1 + + pass diff --git a/sim/testsuite/frv/mqcpxrs.cgs b/sim/testsuite/frv/mqcpxrs.cgs new file mode 100644 index 0000000..d1d1f48 --- /dev/null +++ b/sim/testsuite/frv/mqcpxrs.cgs @@ -0,0 +1,103 @@ +# frv testcase for mqcpxrs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxrs +mqcpxrs: + ; Positive operands + set_fr_iimmed 2,4,fr8 ; multiply small numbers + set_fr_iimmed 3,5,fr10 + set_fr_iimmed 3,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x0007,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ff0,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x2000,fr10 + set_fr_iimmed 0x7fff,0x0000,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr10 + set_fr_iimmed 0xfffe,2,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -3,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbff0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8006,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x8000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0x8000,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0xfffe,0xfffc,fr9 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x7fff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -14,acc1 + + set_fr_iimmed 0xffff,0xffff,fr8 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr10 + set_fr_iimmed 0x7fff,0x0000,fr9 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x0000,fr8 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x0000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + pass diff --git a/sim/testsuite/frv/mqcpxru.cgs b/sim/testsuite/frv/mqcpxru.cgs new file mode 100644 index 0000000..45e1b35 --- /dev/null +++ b/sim/testsuite/frv/mqcpxru.cgs @@ -0,0 +1,78 @@ +# frv testcase for mqcpxru $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxru +mqcpxru: + set_fr_iimmed 4,2,fr8 ; multiply small numbers + set_fr_iimmed 5,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 3,1,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + test_accg_immed 0,accg1 + test_acc_immed 1,acc1 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result + set_fr_iimmed 2,0x0001,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffd,acc1 + + set_fr_iimmed 0x4000,1,fr8 ; 16 bit result + set_fr_iimmed 4,0x0001,fr10 + set_fr_iimmed 0x8000,1,fr9 ; 17 bit result + set_fr_iimmed 4,0x0001,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x0001ffff,acc1 + + set_fr_iimmed 0x7fff,0x0000,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0x0000,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0x0001,fr9 ; saturation + set_fr_iimmed 0xffff,0x0001,fr11 + mqcpxru fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0xffff,fr8 ; saturation + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xfffe,0xffff,fr9 ; saturation + set_fr_iimmed 0xffff,0xffff,fr11 + mqcpxru fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/frv/mqlclrhs.cgs b/sim/testsuite/frv/mqlclrhs.cgs new file mode 100644 index 0000000..5e090b0 --- /dev/null +++ b/sim/testsuite/frv/mqlclrhs.cgs @@ -0,0 +1,74 @@ +# frv testcase for mqlclrhs $FRi,$FRj,$FRj +# mach: fr450 + + .include "testutils.inc" + + start + + .global mqlclrhs +mqlclrhs: + set_fr_iimmed 0x1000,0x2000,fr4 + set_fr_iimmed 0xe800,0xd800,fr5 + set_fr_iimmed 0x0800,0x0800,fr6 + set_fr_iimmed 0x0800,0x0800,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x1000,0x2000,fr8 + test_fr_limmed 0xe800,0xd800,fr9 + + set_fr_iimmed 0x1000,0x2000,fr4 + set_fr_iimmed 0xe800,0xd800,fr5 + set_fr_iimmed 0xf800,0xf800,fr6 + set_fr_iimmed 0xf800,0xf800,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0xf000,0xe000,fr8 + test_fr_limmed 0x1800,0x2800,fr9 + + set_fr_iimmed 0x1000,0x1000,fr4 + set_fr_iimmed 0x1000,0x1000,fr5 + set_fr_iimmed 0xf000,0xf800,fr6 + set_fr_iimmed 0x0800,0x1000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0xf000,fr8 + test_fr_limmed 0x1000,0x0000,fr9 + + set_fr_iimmed 0xf000,0xf000,fr4 + set_fr_iimmed 0xf000,0xf000,fr5 + set_fr_iimmed 0xf000,0xf800,fr6 + set_fr_iimmed 0x0800,0x1000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0x1000,fr8 + test_fr_limmed 0xf000,0x0000,fr9 + + set_fr_iimmed 0x8000,0x8000,fr4 + set_fr_iimmed 0x8000,0x8000,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0x8000,fr8 + test_fr_limmed 0x7fff,0x8000,fr9 + + set_fr_iimmed 0x7fff,0x7fff,fr4 + set_fr_iimmed 0x7fff,0x7fff,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_fr_limmed 0x0000,0x7fff,fr9 + + set_fr_iimmed 0x8001,0x8001,fr4 + set_fr_iimmed 0x8001,0x8001,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_fr_limmed 0x0000,0x8001,fr9 + + set_fr_iimmed 0x8000,0x8000,fr4 + set_fr_iimmed 0x0001,0xffff,fr5 + set_fr_iimmed 0x0001,0xffff,fr6 + set_fr_iimmed 0x8000,0x8000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x8000,0x7fff,fr8 + test_fr_limmed 0x0000,0x0000,fr9 + + pass diff --git a/sim/testsuite/frv/mqlmths.cgs b/sim/testsuite/frv/mqlmths.cgs new file mode 100644 index 0000000..d416d65 --- /dev/null +++ b/sim/testsuite/frv/mqlmths.cgs @@ -0,0 +1,74 @@ +# frv testcase for mqlmths $FRi,$FRj,$FRj +# mach: fr450 + + .include "testutils.inc" + + start + + .global mqlmths +mqlmths: + set_fr_iimmed 0x1000,0x2000,fr4 + set_fr_iimmed 0xe800,0xd800,fr5 + set_fr_iimmed 0x0800,0x0800,fr6 + set_fr_iimmed 0x0800,0x0800,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x0800,0x0800,fr8 + test_fr_limmed 0xf800,0xf800,fr9 + + set_fr_iimmed 0x1000,0x2000,fr4 + set_fr_iimmed 0xe800,0xd800,fr5 + set_fr_iimmed 0xf800,0xf800,fr6 + set_fr_iimmed 0xf800,0xf800,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0xf800,0xf800,fr8 + test_fr_limmed 0x0800,0x0800,fr9 + + set_fr_iimmed 0x1000,0x1000,fr4 + set_fr_iimmed 0x1000,0x1000,fr5 + set_fr_iimmed 0xe800,0xf800,fr6 + set_fr_iimmed 0x0800,0x1800,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x1000,0xf800,fr8 + test_fr_limmed 0x0800,0x1000,fr9 + + set_fr_iimmed 0xf000,0xf000,fr4 + set_fr_iimmed 0xf000,0xf000,fr5 + set_fr_iimmed 0xe800,0xf800,fr6 + set_fr_iimmed 0x0800,0x1800,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0xf000,0x0800,fr8 + test_fr_limmed 0xf800,0xf000,fr9 + + set_fr_iimmed 0x8000,0x8000,fr4 + set_fr_iimmed 0x8000,0x8000,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x7fff,0x8001,fr8 + test_fr_limmed 0x7fff,0x0000,fr9 + + set_fr_iimmed 0x7fff,0x7fff,fr4 + set_fr_iimmed 0x7fff,0x7fff,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x7fff,0x7fff,fr8 + test_fr_limmed 0x8001,0x0000,fr9 + + set_fr_iimmed 0x8001,0x8001,fr4 + set_fr_iimmed 0x8001,0x8001,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x8001,0x8001,fr8 + test_fr_limmed 0x7fff,0x0000,fr9 + + set_fr_iimmed 0x8000,0x8000,fr4 + set_fr_iimmed 0x0001,0xffff,fr5 + set_fr_iimmed 0x0001,0xffff,fr6 + set_fr_iimmed 0x8000,0x8000,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0xffff,0x0001,fr8 + test_fr_limmed 0x0001,0xffff,fr9 + + pass diff --git a/sim/testsuite/frv/mqmachs.cgs b/sim/testsuite/frv/mqmachs.cgs new file mode 100644 index 0000000..5608c64 --- /dev/null +++ b/sim/testsuite/frv/mqmachs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqmachs $GRi,$GRj,$ACCk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mqmachs +mqmachs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/frv/mqmachu.cgs b/sim/testsuite/frv/mqmachu.cgs new file mode 100644 index 0000000..e16be68 --- /dev/null +++ b/sim/testsuite/frv/mqmachu.cgs @@ -0,0 +1,144 @@ +# frv testcase for mqmachu $GRi,$GRj,$GRk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mqmachu +mqmachu: + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/frv/mqmacxhs.cgs b/sim/testsuite/frv/mqmacxhs.cgs new file mode 100644 index 0000000..0be1151 --- /dev/null +++ b/sim/testsuite/frv/mqmacxhs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqmacxhs $GRi,$GRj,$ACCk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mqmacxhs +mqmacxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 0xffff,1,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/frv/mqmulhs.cgs b/sim/testsuite/frv/mqmulhs.cgs new file mode 100644 index 0000000..0a10c29 --- /dev/null +++ b/sim/testsuite/frv/mqmulhs.cgs @@ -0,0 +1,125 @@ +# frv testcase for mqmulhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqmulhs +mqmulhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x0001,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -2,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -2,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffe,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffe,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xc000,0x8000,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xc000,0x8000,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x40000000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x40000000,acc3 + + pass diff --git a/sim/testsuite/frv/mqmulhu.cgs b/sim/testsuite/frv/mqmulhu.cgs new file mode 100644 index 0000000..e94c09ae9 --- /dev/null +++ b/sim/testsuite/frv/mqmulhu.cgs @@ -0,0 +1,80 @@ +# frv testcase for mqmulhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqmulhu +mqmulhu: + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00010000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00010000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4000,0x0000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xfffe,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xfffe,0x0001,acc3 + + pass diff --git a/sim/testsuite/frv/mqmulxhs.cgs b/sim/testsuite/frv/mqmulxhs.cgs new file mode 100644 index 0000000..7686bc1 --- /dev/null +++ b/sim/testsuite/frv/mqmulxhs.cgs @@ -0,0 +1,125 @@ +# frv testcase for mqmulxhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqmulxhs +mqmulxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 4,acc0 + test_accg_immed 0,accg1 + test_acc_immed 9,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x0001,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -2,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -2,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffe,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffe,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xc000,0x8000,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xc000,0x8000,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x40000000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x40000000,acc3 + + pass diff --git a/sim/testsuite/frv/mqmulxhu.cgs b/sim/testsuite/frv/mqmulxhu.cgs new file mode 100644 index 0000000..b60e421 --- /dev/null +++ b/sim/testsuite/frv/mqmulxhu.cgs @@ -0,0 +1,80 @@ +# frv testcase for mqmulxhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqmulxhu +mqmulxhu: + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 1,2,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 0,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 0x8000,2,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00010000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00010000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4000,0x0000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xfffe,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xfffe,0x0001,acc3 + + pass diff --git a/sim/testsuite/frv/mqsaths.cgs b/sim/testsuite/frv/mqsaths.cgs new file mode 100644 index 0000000..61ff112 --- /dev/null +++ b/sim/testsuite/frv/mqsaths.cgs @@ -0,0 +1,50 @@ +# frv testcase for mqsaths $FRi,$FRj,$FRj +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global mqsaths +mqsaths: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0001,0x7fff,fr11 + set_fr_iimmed 0x0000,0x0000,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr11 + set_fr_iimmed 0x0040,0x0040,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0xffff,0xffff,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0040,0x0040,fr12 + set_fr_iimmed 0xffff,0x8000,fr11 + set_fr_iimmed 0x0040,0x0040,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0x0001,0x0040,fr14 + test_fr_limmed 0xffff,0xffbf,fr15 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr12 + set_fr_iimmed 0x0001,0x7fff,fr11 + set_fr_iimmed 0x7fff,0x7fff,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0001,0x7fff,fr15 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr12 + set_fr_iimmed 0xffff,0x8000,fr11 + set_fr_iimmed 0x7fff,0x7fff,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0xffff,0x8000,fr14 + test_fr_limmed 0xffff,0x8000,fr15 + + pass diff --git a/sim/testsuite/frv/mqsllhi.cgs b/sim/testsuite/frv/mqsllhi.cgs new file mode 100644 index 0000000..21379f2 --- /dev/null +++ b/sim/testsuite/frv/mqsllhi.cgs @@ -0,0 +1,40 @@ +# frv testcase for mqsllhi $FRi,#u6,$FRj +# mach: fr450 + + .include "testutils.inc" + + start + + .global mqsllhi +mqsllhi: + set_fr_iimmed 0x0001,0x0002,fr4 + set_fr_iimmed 0x0003,0x0004,fr5 + mqsllhi fr4,#1,fr6 + test_fr_limmed 0x0002,0x0004,fr6 + test_fr_limmed 0x0006,0x0008,fr7 + + set_fr_iimmed 0xffff,0xfffe,fr4 + set_fr_iimmed 0xfffc,0xfff8,fr5 + mqsllhi fr4,#1,fr6 + test_fr_limmed 0xfffe,0xfffc,fr6 + test_fr_limmed 0xfff8,0xfff0,fr7 + + set_fr_iimmed 0xffff,0xfffe,fr4 + set_fr_iimmed 0xfffc,0xfff8,fr5 + mqsllhi fr4,#12,fr6 + test_fr_limmed 0xf000,0xe000,fr6 + test_fr_limmed 0xc000,0x8000,fr7 + + set_fr_iimmed 0x1234,0x5678,fr4 + set_fr_iimmed 0x9abc,0xdef0,fr5 + mqsllhi fr4,#12,fr6 + test_fr_limmed 0x4000,0x8000,fr6 + test_fr_limmed 0xc000,0x0000,fr7 + + set_fr_iimmed 0x1234,0x5678,fr4 + set_fr_iimmed 0x9abc,0xdef0,fr5 + mqsllhi fr4,#16,fr6 + test_fr_limmed 0x1234,0x5678,fr6 + test_fr_limmed 0x9abc,0xdef0,fr7 + + pass diff --git a/sim/testsuite/frv/mqsrahi.cgs b/sim/testsuite/frv/mqsrahi.cgs new file mode 100644 index 0000000..1d30179 --- /dev/null +++ b/sim/testsuite/frv/mqsrahi.cgs @@ -0,0 +1,40 @@ +# frv testcase for mqsrahi $FRi,#u6,$FRj +# mach: fr450 + + .include "testutils.inc" + + start + + .global mqsrahi +mqsrahi: + set_fr_iimmed 0x0001,0x0002,fr4 + set_fr_iimmed 0x0003,0x0004,fr5 + mqsrahi fr4,#1,fr6 + test_fr_limmed 0x0000,0x0001,fr6 + test_fr_limmed 0x0001,0x0002,fr7 + + set_fr_iimmed 0xffff,0xfffe,fr4 + set_fr_iimmed 0xfffc,0xfff8,fr5 + mqsrahi fr4,#1,fr6 + test_fr_limmed 0xffff,0xffff,fr6 + test_fr_limmed 0xfffe,0xfffc,fr7 + + set_fr_iimmed 0x8000,0xc000,fr4 + set_fr_iimmed 0xe000,0xf000,fr5 + mqsrahi fr4,#12,fr6 + test_fr_limmed 0xfff8,0xfffc,fr6 + test_fr_limmed 0xfffe,0xffff,fr7 + + set_fr_iimmed 0x1234,0x5678,fr4 + set_fr_iimmed 0x9abc,0xdef0,fr5 + mqsrahi fr4,#12,fr6 + test_fr_limmed 0x0001,0x0005,fr6 + test_fr_limmed 0xfff9,0xfffd,fr7 + + set_fr_iimmed 0x1234,0x5678,fr4 + set_fr_iimmed 0x9abc,0xdef0,fr5 + mqsrahi fr4,#16,fr6 + test_fr_limmed 0x1234,0x5678,fr6 + test_fr_limmed 0x9abc,0xdef0,fr7 + + pass diff --git a/sim/testsuite/frv/mqxmachs.cgs b/sim/testsuite/frv/mqxmachs.cgs new file mode 100644 index 0000000..6791ed3 --- /dev/null +++ b/sim/testsuite/frv/mqxmachs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqxmachs $GRi,$GRj,$ACCk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mqxmachs +mqxmachs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 6,acc2 + test_accg_immed 0,accg3 + test_acc_immed 6,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_immed 8,acc2 + test_accg_immed 0,accg3 + test_acc_immed 8,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8008,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7fff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7fff,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7ffd,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffb,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffb,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffb,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0008,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_immed 0x3fff0009,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fff0009,acc3 + test_accg_immed 0,accg0 + test_acc_immed 0x3fffbffd,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fffbffd,acc1 + + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/frv/mqxmacxhs.cgs b/sim/testsuite/frv/mqxmacxhs.cgs new file mode 100644 index 0000000..c644eed --- /dev/null +++ b/sim/testsuite/frv/mqxmacxhs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mqxmacxhs +mqxmacxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 6,acc2 + test_accg_immed 0,accg3 + test_acc_immed 6,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_immed 8,acc2 + test_accg_immed 0,accg3 + test_acc_immed 8,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8008,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7fff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7fff,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7ffd,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffb,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffb,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffb,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0008,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_immed 0x3fff0009,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fff0009,acc3 + test_accg_immed 0,accg0 + test_acc_immed 0x3fffbffd,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fffbffd,acc1 + + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 0xffff,1,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/frv/mrdacc.cgs b/sim/testsuite/frv/mrdacc.cgs new file mode 100644 index 0000000..2178036 --- /dev/null +++ b/sim/testsuite/frv/mrdacc.cgs @@ -0,0 +1,26 @@ +# frv testcase for mrdacc $ACC40i,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mrdacc +mrdacc: + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed -1,accg3 + set_acc_immed -1,acc3 + set_accg_immed 0x12,accg2 + set_acc_immed 0xdeadbeef,acc2 + + mrdacc acc0,fr10 + test_fr_iimmed 0,fr10 + + mrdacc acc3,fr10 + test_fr_iimmed 0xffffffff,fr10 + + mrdacc acc2,fr10 + test_fr_iimmed 0xdeadbeef,fr10 + + pass diff --git a/sim/testsuite/frv/mrdaccg.cgs b/sim/testsuite/frv/mrdaccg.cgs new file mode 100644 index 0000000..96e9406 --- /dev/null +++ b/sim/testsuite/frv/mrdaccg.cgs @@ -0,0 +1,26 @@ +# frv testcase for mrdaccg $ACC40i,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mrdaccg +mrdaccg: + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed -1,accg3 + set_acc_immed -1,acc3 + set_accg_immed 0x12,accg2 + set_acc_immed 0xdeadbeef,acc2 + + mrdaccg accg0,fr10 + test_fr_iimmed 0,fr10 + + mrdaccg accg3,fr10 + test_fr_iimmed 0x000000ff,fr10 + + mrdaccg accg2,fr10 + test_fr_iimmed 0x00000012,fr10 + + pass diff --git a/sim/testsuite/frv/mrotli.cgs b/sim/testsuite/frv/mrotli.cgs new file mode 100644 index 0000000..02220ee --- /dev/null +++ b/sim/testsuite/frv/mrotli.cgs @@ -0,0 +1,34 @@ +# frv testcase for mrotli $FRi,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mrotli +mrotli: + set_fr_iimmed 0,2,fr8 + mrotli fr8,0x20,fr8 ; Shift by 0 + test_fr_iimmed 2,fr8 + + set_fr_iimmed 0,2,fr8 + mrotli fr8,0,fr8 ; Shift by 0 + test_fr_iimmed 2,fr8 + + set_fr_iimmed 0,2,fr8 + mrotli fr8,1,fr8 ; Shift by 1 + test_fr_iimmed 4,fr8 + + set_fr_iimmed 0,1,fr8 + mrotli fr8,31,fr8 ; Shift by 31 + test_fr_iimmed 0x80000000,fr8 + + set_fr_iimmed 0,2,fr8 + mrotli fr8,31,fr8 ; max rotation + test_fr_iimmed 1,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + mrotli fr8,16,fr8 + test_fr_iimmed 0xbeefdead,fr8 + + pass diff --git a/sim/testsuite/frv/mrotri.cgs b/sim/testsuite/frv/mrotri.cgs new file mode 100644 index 0000000..17a5c74 --- /dev/null +++ b/sim/testsuite/frv/mrotri.cgs @@ -0,0 +1,34 @@ +# frv testcase for mrotri $FRinti,$s6,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mrotri +mrotri: + set_fr_iimmed 0x8000,0x0000,fr8 + mrotri fr8,0x20,fr8 ; Shift by 0 + test_fr_iimmed 0x80000000,fr8 + + set_fr_iimmed 0x8000,0x0000,fr8 + mrotri fr8,0,fr8 ; Shift by 0 + test_fr_iimmed 0x80000000,fr8 + + set_fr_iimmed 0x8000,0x0000,fr8 + mrotri fr8,1,fr8 ; Shift by 1 + test_fr_iimmed 0x40000000,fr8 + + set_fr_iimmed 0x8000,0x0000,fr8 + mrotri fr8,31,fr8 ; Shift by 31 + test_fr_iimmed 1,fr8 + + set_fr_iimmed 0x4000,0x0000,fr8 + mrotri fr8,31,fr8 ; max shift + test_fr_iimmed 0x80000000,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + mrotri fr8,16,fr8 ; max shift + test_fr_iimmed 0xbeefdead,fr8 + + pass diff --git a/sim/testsuite/frv/msaths.cgs b/sim/testsuite/frv/msaths.cgs new file mode 100644 index 0000000..513d5d3 --- /dev/null +++ b/sim/testsuite/frv/msaths.cgs @@ -0,0 +1,55 @@ +# frv testcase for msaths $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global msaths +msaths: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0040,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffbf,fr12 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0001,0x7fff,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0xffff,0x8000,fr12 + + pass diff --git a/sim/testsuite/frv/msathu.cgs b/sim/testsuite/frv/msathu.cgs new file mode 100644 index 0000000..4f376b2 --- /dev/null +++ b/sim/testsuite/frv/msathu.cgs @@ -0,0 +1,55 @@ +# frv testcase for msathu $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global msathu +msathu: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0040,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0040,0x0040,fr12 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0001,0x7fff,fr12 + + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x7fff,0xffff,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x7fff,0xffff,fr12 + + pass diff --git a/sim/testsuite/frv/msllhi.cgs b/sim/testsuite/frv/msllhi.cgs new file mode 100644 index 0000000..4340b9f --- /dev/null +++ b/sim/testsuite/frv/msllhi.cgs @@ -0,0 +1,30 @@ +# frv testcase for msllhi $FRi,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global msllhi +msllhi: + set_fr_iimmed 2,2,fr8 + msllhi fr8,0x20,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 2,2,fr8 + msllhi fr8,0,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 2,2,fr8 + msllhi fr8,1,fr8 ; Shift by 1 + test_fr_limmed 4,4,fr8 + + set_fr_iimmed 1,1,fr8 + msllhi fr8,31,fr8 ; Shift by 15 + test_fr_limmed 0x8000,0x8000,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + msllhi fr8,15,fr8 + test_fr_iimmed 0x80008000,fr8 + + pass diff --git a/sim/testsuite/frv/msrahi.cgs b/sim/testsuite/frv/msrahi.cgs new file mode 100644 index 0000000..182f84e --- /dev/null +++ b/sim/testsuite/frv/msrahi.cgs @@ -0,0 +1,30 @@ +# frv testcase for msrahi $FRi,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global msrahi +msrahi: + set_fr_iimmed 2,2,fr8 + msrahi fr8,0x20,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 2,2,fr8 + msrahi fr8,0,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 3,2,fr8 + msrahi fr8,1,fr8 ; Shift by 1 + test_fr_limmed 1,1,fr8 + + set_fr_iimmed 0x8000,0x7fff,fr8 + msrahi fr8,31,fr8 ; Shift by 15 + test_fr_limmed 0xffff,0x0000,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + msrahi fr8,15,fr8 + test_fr_iimmed 0xffffffff,fr8 + + pass diff --git a/sim/testsuite/frv/msrlhi.cgs b/sim/testsuite/frv/msrlhi.cgs new file mode 100644 index 0000000..c9971a9 --- /dev/null +++ b/sim/testsuite/frv/msrlhi.cgs @@ -0,0 +1,30 @@ +# frv testcase for msrlhi $FRi,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global msrlhi +msrlhi: + set_fr_iimmed 2,2,fr8 + msrlhi fr8,0x20,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 2,2,fr8 + msrlhi fr8,0,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 3,2,fr8 + msrlhi fr8,1,fr8 ; Shift by 1 + test_fr_limmed 1,1,fr8 + + set_fr_iimmed 0xffff,0x8000,fr8 + msrlhi fr8,31,fr8 ; Shift by 15 + test_fr_limmed 0x0001,0x0001,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + msrlhi fr8,15,fr8 + test_fr_iimmed 0x00010001,fr8 + + pass diff --git a/sim/testsuite/frv/msubhss.cgs b/sim/testsuite/frv/msubhss.cgs new file mode 100644 index 0000000..1ba3343 --- /dev/null +++ b/sim/testsuite/frv/msubhss.cgs @@ -0,0 +1,100 @@ +# frv testcase for msubhss $FRi,$FRj,$FRj +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global msubhss +msubhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + msubhss.p fr10,fr10,fr12 + msubhss fr11,fr10,fr13 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/msubhus.cgs b/sim/testsuite/frv/msubhus.cgs new file mode 100644 index 0000000..1a002da --- /dev/null +++ b/sim/testsuite/frv/msubhus.cgs @@ -0,0 +1,80 @@ +# frv testcase for msubhus $FRi,$FRj,$FRj +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global msubhus +msubhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + msubhus.p fr10,fr10,fr12 + msubhus fr10,fr11,fr13 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/frv/mtrap.cgs b/sim/testsuite/frv/mtrap.cgs new file mode 100644 index 0000000..65b947a --- /dev/null +++ b/sim/testsuite/frv/mtrap.cgs @@ -0,0 +1,50 @@ +# frv testcase for mp_exception +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mp_exception +mpx: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x0e0,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + set_gr_immed 0,gr5 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + mtrap ; generate interrupt + test_gr_immed 1,gr5 + + and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields + mcmpsh fr10,fr11,fcc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + mtrap ; nop + test_gr_immed 1,gr5 + + pass + +; exception handler +ok1: + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + inc_gr_immed 1,gr5 + rett 0 + fail diff --git a/sim/testsuite/frv/munpackh.cgs b/sim/testsuite/frv/munpackh.cgs new file mode 100644 index 0000000..45b2bd8 --- /dev/null +++ b/sim/testsuite/frv/munpackh.cgs @@ -0,0 +1,22 @@ +# frv testcase for munpackh $FRi,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global munpackh +munpackh: + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + munpackh fr10,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + munpackh fr10,fr12 + test_fr_limmed 0x1234,0x1234,fr12 + test_fr_limmed 0x5678,0x5678,fr13 + + pass diff --git a/sim/testsuite/frv/mwcut.cgs b/sim/testsuite/frv/mwcut.cgs new file mode 100644 index 0000000..0e31b8f --- /dev/null +++ b/sim/testsuite/frv/mwcut.cgs @@ -0,0 +1,269 @@ +# frv testcase for mwcut $FRi,FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mwcut +mwcut: + set_fr_iimmed 0x0123,0x4567,fr8 + set_fr_iimmed 0x89ab,0xcdef,fr9 + + set_fr_iimmed 0,0,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x01234567,fr11 + + set_fr_iimmed 0,1,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x02468acf,fr11 + + set_fr_iimmed 0,2,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x048d159e,fr11 + + set_fr_iimmed 0,3,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x091a2b3c,fr11 + + set_fr_iimmed 0,4,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x12345678,fr11 + + set_fr_iimmed 0,5,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x2468acf1,fr11 + + set_fr_iimmed 0,6,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x48d159e2,fr11 + + set_fr_iimmed 0,7,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x91a2b3c4,fr11 + + set_fr_iimmed 0,8,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x23456789,fr11 + + set_fr_iimmed 0,9,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x468acf13,fr11 + + set_fr_iimmed 0,10,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x8d159e26,fr11 + + set_fr_iimmed 0,11,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x1a2b3c4d,fr11 + + set_fr_iimmed 0,12,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x3456789a,fr11 + + set_fr_iimmed 0,13,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x68acf135,fr11 + + set_fr_iimmed 0,14,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xd159e26a,fr11 + + set_fr_iimmed 0,15,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xa2b3c4d5,fr11 + + set_fr_iimmed 0,16,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x456789ab,fr11 + + set_fr_iimmed 0,17,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x8acf1357,fr11 + + set_fr_iimmed 0,18,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x159e26af,fr11 + + set_fr_iimmed 0,19,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x2b3c4d5e,fr11 + + set_fr_iimmed 0,20,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x56789abc,fr11 + + set_fr_iimmed 0,21,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xacf13579,fr11 + + set_fr_iimmed 0,22,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x59e26af3,fr11 + + set_fr_iimmed 0,23,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xb3c4d5e6,fr11 + + set_fr_iimmed 0,24,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x6789abcd,fr11 + + set_fr_iimmed 0,25,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + set_fr_iimmed 0,26,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + set_fr_iimmed 0,27,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x3c4d5e6f,fr11 + + set_fr_iimmed 0,28,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x789abcde,fr11 + + set_fr_iimmed 0,29,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xf13579bd,fr11 + + set_fr_iimmed 0,30,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xe26af37b,fr11 + + set_fr_iimmed 0,31,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xc4d5e6f7,fr11 + + set_fr_iimmed 0,32,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x89abcdef,fr11 + + set_fr_iimmed 0,33,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x13579bde,fr11 + + set_fr_iimmed 0,34,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x26af37bc,fr11 + + set_fr_iimmed 0,35,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x4d5e6f78,fr11 + + set_fr_iimmed 0,36,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x9abcdef0,fr11 + + set_fr_iimmed 0,37,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x3579bde0,fr11 + + set_fr_iimmed 0,38,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x6af37bc0,fr11 + + set_fr_iimmed 0,39,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xd5e6f780,fr11 + + set_fr_iimmed 0,40,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xabcdef00,fr11 + + set_fr_iimmed 0,41,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x579bde00,fr11 + + set_fr_iimmed 0,42,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xaf37bc00,fr11 + + set_fr_iimmed 0,43,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x5e6f7800,fr11 + + set_fr_iimmed 0,44,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xbcdef000,fr11 + + set_fr_iimmed 0,45,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x79bde000,fr11 + + set_fr_iimmed 0,46,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xf37bc000,fr11 + + set_fr_iimmed 0,47,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xe6f78000,fr11 + + set_fr_iimmed 0,48,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xcdef0000,fr11 + + set_fr_iimmed 0,49,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x9bde0000,fr11 + + set_fr_iimmed 0,50,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x37bc0000,fr11 + + set_fr_iimmed 0,51,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x6f780000,fr11 + + set_fr_iimmed 0,52,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xdef00000,fr11 + + set_fr_iimmed 0,53,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xbde00000,fr11 + + set_fr_iimmed 0,54,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x7bc00000,fr11 + + set_fr_iimmed 0,55,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xf7800000,fr11 + + set_fr_iimmed 0,56,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xef000000,fr11 + + set_fr_iimmed 0,57,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xde000000,fr11 + + set_fr_iimmed 0,58,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xbc000000,fr11 + + set_fr_iimmed 0,59,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x78000000,fr11 + + set_fr_iimmed 0,60,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xf0000000,fr11 + + set_fr_iimmed 0,61,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,62,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,63,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + pass diff --git a/sim/testsuite/frv/mwcuti.cgs b/sim/testsuite/frv/mwcuti.cgs new file mode 100644 index 0000000..338eab8 --- /dev/null +++ b/sim/testsuite/frv/mwcuti.cgs @@ -0,0 +1,205 @@ +# frv testcase for mwcuti $FRi,s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mwcuti +mwcuti: + set_fr_iimmed 0x0123,0x4567,fr8 + set_fr_iimmed 0x89ab,0xcdef,fr9 + + mwcuti fr8,0,fr11 + test_fr_iimmed 0x01234567,fr11 + + mwcuti fr8,1,fr11 + test_fr_iimmed 0x02468acf,fr11 + + mwcuti fr8,2,fr11 + test_fr_iimmed 0x048d159e,fr11 + + mwcuti fr8,3,fr11 + test_fr_iimmed 0x091a2b3c,fr11 + + mwcuti fr8,4,fr11 + test_fr_iimmed 0x12345678,fr11 + + mwcuti fr8,5,fr11 + test_fr_iimmed 0x2468acf1,fr11 + + mwcuti fr8,6,fr11 + test_fr_iimmed 0x48d159e2,fr11 + + mwcuti fr8,7,fr11 + test_fr_iimmed 0x91a2b3c4,fr11 + + mwcuti fr8,8,fr11 + test_fr_iimmed 0x23456789,fr11 + + mwcuti fr8,9,fr11 + test_fr_iimmed 0x468acf13,fr11 + + mwcuti fr8,10,fr11 + test_fr_iimmed 0x8d159e26,fr11 + + mwcuti fr8,11,fr11 + test_fr_iimmed 0x1a2b3c4d,fr11 + + mwcuti fr8,12,fr11 + test_fr_iimmed 0x3456789a,fr11 + + mwcuti fr8,13,fr11 + test_fr_iimmed 0x68acf135,fr11 + + mwcuti fr8,14,fr11 + test_fr_iimmed 0xd159e26a,fr11 + + mwcuti fr8,15,fr11 + test_fr_iimmed 0xa2b3c4d5,fr11 + + mwcuti fr8,16,fr11 + test_fr_iimmed 0x456789ab,fr11 + + mwcuti fr8,17,fr11 + test_fr_iimmed 0x8acf1357,fr11 + + mwcuti fr8,18,fr11 + test_fr_iimmed 0x159e26af,fr11 + + mwcuti fr8,19,fr11 + test_fr_iimmed 0x2b3c4d5e,fr11 + + mwcuti fr8,20,fr11 + test_fr_iimmed 0x56789abc,fr11 + + mwcuti fr8,21,fr11 + test_fr_iimmed 0xacf13579,fr11 + + mwcuti fr8,22,fr11 + test_fr_iimmed 0x59e26af3,fr11 + + mwcuti fr8,23,fr11 + test_fr_iimmed 0xb3c4d5e6,fr11 + + mwcuti fr8,24,fr11 + test_fr_iimmed 0x6789abcd,fr11 + + mwcuti fr8,25,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + mwcuti fr8,26,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + mwcuti fr8,27,fr11 + test_fr_iimmed 0x3c4d5e6f,fr11 + + mwcuti fr8,28,fr11 + test_fr_iimmed 0x789abcde,fr11 + + mwcuti fr8,29,fr11 + test_fr_iimmed 0xf13579bd,fr11 + + mwcuti fr8,30,fr11 + test_fr_iimmed 0xe26af37b,fr11 + + mwcuti fr8,31,fr11 + test_fr_iimmed 0xc4d5e6f7,fr11 + + mwcuti fr8,32,fr11 + test_fr_iimmed 0x89abcdef,fr11 + + mwcuti fr8,33,fr11 + test_fr_iimmed 0x13579bde,fr11 + + mwcuti fr8,34,fr11 + test_fr_iimmed 0x26af37bc,fr11 + + mwcuti fr8,35,fr11 + test_fr_iimmed 0x4d5e6f78,fr11 + + mwcuti fr8,36,fr11 + test_fr_iimmed 0x9abcdef0,fr11 + + mwcuti fr8,37,fr11 + test_fr_iimmed 0x3579bde0,fr11 + + mwcuti fr8,38,fr11 + test_fr_iimmed 0x6af37bc0,fr11 + + mwcuti fr8,39,fr11 + test_fr_iimmed 0xd5e6f780,fr11 + + mwcuti fr8,40,fr11 + test_fr_iimmed 0xabcdef00,fr11 + + mwcuti fr8,41,fr11 + test_fr_iimmed 0x579bde00,fr11 + + mwcuti fr8,42,fr11 + test_fr_iimmed 0xaf37bc00,fr11 + + mwcuti fr8,43,fr11 + test_fr_iimmed 0x5e6f7800,fr11 + + mwcuti fr8,44,fr11 + test_fr_iimmed 0xbcdef000,fr11 + + mwcuti fr8,45,fr11 + test_fr_iimmed 0x79bde000,fr11 + + mwcuti fr8,46,fr11 + test_fr_iimmed 0xf37bc000,fr11 + + mwcuti fr8,47,fr11 + test_fr_iimmed 0xe6f78000,fr11 + + mwcuti fr8,48,fr11 + test_fr_iimmed 0xcdef0000,fr11 + + mwcuti fr8,49,fr11 + test_fr_iimmed 0x9bde0000,fr11 + + mwcuti fr8,50,fr11 + test_fr_iimmed 0x37bc0000,fr11 + + mwcuti fr8,51,fr11 + test_fr_iimmed 0x6f780000,fr11 + + mwcuti fr8,52,fr11 + test_fr_iimmed 0xdef00000,fr11 + + mwcuti fr8,53,fr11 + test_fr_iimmed 0xbde00000,fr11 + + mwcuti fr8,54,fr11 + test_fr_iimmed 0x7bc00000,fr11 + + mwcuti fr8,55,fr11 + test_fr_iimmed 0xf7800000,fr11 + + mwcuti fr8,56,fr11 + test_fr_iimmed 0xef000000,fr11 + + mwcuti fr8,57,fr11 + test_fr_iimmed 0xde000000,fr11 + + mwcuti fr8,58,fr11 + test_fr_iimmed 0xbc000000,fr11 + + mwcuti fr8,59,fr11 + test_fr_iimmed 0x78000000,fr11 + + mwcuti fr8,60,fr11 + test_fr_iimmed 0xf0000000,fr11 + + mwcuti fr8,61,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mwcuti fr8,62,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mwcuti fr8,63,fr11 + test_fr_iimmed 0x80000000,fr11 + + pass diff --git a/sim/testsuite/frv/mwtacc.cgs b/sim/testsuite/frv/mwtacc.cgs new file mode 100644 index 0000000..20b4d31 --- /dev/null +++ b/sim/testsuite/frv/mwtacc.cgs @@ -0,0 +1,23 @@ +# frv testcase for mwtacc $FRinti,$ACC40k +# mach: all + + .include "testutils.inc" + + start + + .global mwtacc +mwtacc: + test_accg_immed 0x00,accg0 + test_acc_immed 0x00000000,acc0 + + set_fr_iimmed 0xdead,0xbeef,fr10 + mwtacc fr10,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 0xdeadbeef,acc0 + + set_fr_iimmed 0x1234,0x5678,fr10 + mwtacc fr10,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 0x12345678,acc0 + + pass diff --git a/sim/testsuite/frv/mwtaccg.cgs b/sim/testsuite/frv/mwtaccg.cgs new file mode 100644 index 0000000..6e26bab --- /dev/null +++ b/sim/testsuite/frv/mwtaccg.cgs @@ -0,0 +1,23 @@ +# frv testcase for mwtaccg $FRinti,$ACC40k +# mach: all + + .include "testutils.inc" + + start + + .global mwtaccg +mwtaccg: + test_accg_immed 0x00,accg0 + test_acc_immed 0x00000000,acc0 + + set_fr_iimmed 0xdead,0xbeef,fr10 + mwtaccg fr10,accg0 + test_accg_immed 0xef,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x1234,0x5678,fr10 + mwtaccg fr10,accg0 + test_accg_immed 0x78,accg0 + test_acc_immed 0,acc0 + + pass diff --git a/sim/testsuite/frv/mxor.cgs b/sim/testsuite/frv/mxor.cgs new file mode 100644 index 0000000..6d1cce1 --- /dev/null +++ b/sim/testsuite/frv/mxor.cgs @@ -0,0 +1,30 @@ +# frv testcase for mxor $FRinti,$FRintj,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mxor +mxor: + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + mxor fr7,fr8,fr8 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + mxor fr7,fr8,fr8 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + mxor fr7,fr8,fr8 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + mxor fr7,fr8,fr8 + test_fr_iimmed 0xdeadbeef,fr8 + + pass diff --git a/sim/testsuite/frv/nandcr.cgs b/sim/testsuite/frv/nandcr.cgs new file mode 100644 index 0000000..8d3298f --- /dev/null +++ b/sim/testsuite/frv/nandcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for nandcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global nandcr +nandcr: + set_spr_immed 0x1b1b,cccr + nandcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc5,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc5,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc4,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc4,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc4,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + nandcr cc4,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/frv/nandncr.cgs b/sim/testsuite/frv/nandncr.cgs new file mode 100644 index 0000000..c761c56 --- /dev/null +++ b/sim/testsuite/frv/nandncr.cgs @@ -0,0 +1,59 @@ +# frv testcase for nandncr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global nandncr +nandncr: + set_spr_immed 0x1b1b,cccr + nandncr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc5,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + nandncr cc5,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + nandncr cc4,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc4,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc4,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc4,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/frv/nfadds.cgs b/sim/testsuite/frv/nfadds.cgs new file mode 100644 index 0000000..bdfa1dc --- /dev/null +++ b/sim/testsuite/frv/nfadds.cgs @@ -0,0 +1,179 @@ +# frv testcase for nfadds $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfadds +nfadds: + nfadds fr16,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr20,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr8,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr12,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr24,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr28,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr36,fr40,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfadds fr48,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr52,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr56,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr60,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/frv/nfdadds.cgs b/sim/testsuite/frv/nfdadds.cgs new file mode 100644 index 0000000..0be25e7 --- /dev/null +++ b/sim/testsuite/frv/nfdadds.cgs @@ -0,0 +1,225 @@ +# frv testcase for nfdadds $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdadds +nfdadds: + nfdadds fr16,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr20,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr8,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr12,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr24,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr28,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr36,fr40,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfdadds fr48,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr52,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/frv/nfdcmps.cgs b/sim/testsuite/frv/nfdcmps.cgs new file mode 100644 index 0000000..977805a --- /dev/null +++ b/sim/testsuite/frv/nfdcmps.cgs @@ -0,0 +1,1549 @@ +# frv testcase for nfdcmps $FRi,$FRj,$FCCi_2 +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdcmps +nfdcmps: + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr0,fr0,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr4,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr8,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr0,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr0,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr4,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr4,fr4,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr8,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr4,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr4,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr8,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr8,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr8,fr8,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr8,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr8,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr12,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr12,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr12,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr12,fr12,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr12,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr12,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr16,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr16,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr16,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr16,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr16,fr16,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr16,fr20,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr16,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr16,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr20,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr20,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr20,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr20,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr20,fr16,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr20,fr20,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr20,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr20,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr24,fr24,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr24,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr24,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr28,fr28,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr28,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr28,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr28,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr32,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr36,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr40,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr44,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr48,fr48,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr48,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr48,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr48,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr28,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr32,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr36,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr40,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr44,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr48,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr52,fr52,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr52,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr52,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr0,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr4,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr8,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr12,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr16,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr20,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr24,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr28,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr32,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr36,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr40,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr44,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr48,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr52,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr0,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr4,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr8,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr12,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr16,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr20,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr24,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr28,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr32,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr36,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr40,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr44,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr48,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr52,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/frv/nfddivs.cgs b/sim/testsuite/frv/nfddivs.cgs new file mode 100644 index 0000000..0b16447 --- /dev/null +++ b/sim/testsuite/frv/nfddivs.cgs @@ -0,0 +1,306 @@ +# frv testcase for nfddivs $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfddivs +nfddivs: + nfddivs fr0,fr28,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr4,fr28,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr12,fr28,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr24,fr28,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr32,fr28,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr36,fr28,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr40,fr28,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr44,fr28,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr48,fr28,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr52,fr28,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr16,fr0,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr52,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr20,fr0,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr52,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr40,fr32,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfddivs fr48,fr20,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfddivs fr52,fr16,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0x0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/frv/nfditos.cgs b/sim/testsuite/frv/nfditos.cgs new file mode 100644 index 0000000..1200944 --- /dev/null +++ b/sim/testsuite/frv/nfditos.cgs @@ -0,0 +1,31 @@ +# frv testcase for nfditos $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfditos +nfditos: + set_fr_iimmed 0,0,fr2 + set_fr_iimmed 0x0000,0x0002,fr3 + nfditos fr2,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr2 + set_fr_iimmed 0xdead,0xbeef,fr3 + nfditos fr2,fr2 + test_fr_iimmed 0xce054904,fr2 + test_fr_iimmed 0xce054904,fr3 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + + pass diff --git a/sim/testsuite/frv/nfdivs.cgs b/sim/testsuite/frv/nfdivs.cgs new file mode 100644 index 0000000..73e58b8 --- /dev/null +++ b/sim/testsuite/frv/nfdivs.cgs @@ -0,0 +1,234 @@ +# frv testcase for nfdivs $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfdivs +nfdivs: + nfdivs fr0,fr28,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr4,fr28,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr8,fr28,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr12,fr28,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr24,fr28,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr28,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr32,fr28,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr36,fr28,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr40,fr28,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr44,fr28,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr48,fr28,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr52,fr28,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr16,fr0,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr52,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr20,fr0,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr52,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr8,fr28,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr40,fr32,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfdivs fr48,fr20,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfdivs fr52,fr16,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr56,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr60,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/frv/nfdmadds.cgs b/sim/testsuite/frv/nfdmadds.cgs new file mode 100644 index 0000000..1af110c --- /dev/null +++ b/sim/testsuite/frv/nfdmadds.cgs @@ -0,0 +1,310 @@ +# frv testcase for nfdmadds $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdmadds +nfdmadds: + nfdmadds fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmadds fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr36,fr2 + set_fr_fr fr36,fr3 + nfdmadds fr28,fr8,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr8,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr36,fr2 + set_fr_fr fr36,fr3 + nfdmadds fr32,fr36,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO -- test cases to set ne flags + + pass diff --git a/sim/testsuite/frv/nfdmas.cgs b/sim/testsuite/frv/nfdmas.cgs new file mode 100644 index 0000000..07f76aa --- /dev/null +++ b/sim/testsuite/frv/nfdmas.cgs @@ -0,0 +1,349 @@ +# frv testcase for nfdmas $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + load_float_constants2 + load_float_constants3 + + .global nfdmas +nfdmas: + nfdmas fr16,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr4 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr12 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr24 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr40 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr44 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr48 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmas fr20,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr4 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr12 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr24 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr40 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr44 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr48 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmas fr28,fr0,fr60 + test_fr_fr fr60,fr0 + test_fr_fr fr62,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr4,fr60 + test_fr_fr fr60,fr4 + test_fr_fr fr62,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr12,fr60 + test_fr_fr fr60,fr12 + test_fr_fr fr62,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr24,fr60 + test_fr_fr fr60,fr24 + test_fr_fr fr62,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr28,fr60 + test_fr_fr fr60,fr28 + test_fr_fr fr62,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr32,fr60 + test_fr_fr fr60,fr32 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr32 + test_fr_fr fr63,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr36,fr60 + test_fr_fr fr60,fr36 + test_fr_fr fr62,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr40,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr44,fr60 + test_fr_fr fr60,fr44 + test_fr_fr fr62,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr48,fr60 + test_fr_fr fr60,fr48 + test_fr_fr fr62,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr52,fr60 + test_fr_fr fr60,fr52 + test_fr_fr fr62,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmas fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr8,fr28,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmas fr32,fr36,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO -- test cases to set ne flags + + pass diff --git a/sim/testsuite/frv/nfdmss.cgs b/sim/testsuite/frv/nfdmss.cgs new file mode 100644 index 0000000..3633d70 --- /dev/null +++ b/sim/testsuite/frv/nfdmss.cgs @@ -0,0 +1,319 @@ +# frv testcase for nfdmss $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + load_float_constants2 + load_float_constants3 + + .global nfdmss +nfdmss: + nfdmss fr16,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmss fr20,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmss fr28,fr0,fr60 + test_fr_fr fr60,fr0 + test_fr_fr fr62,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr4,fr60 + test_fr_fr fr60,fr4 + test_fr_fr fr62,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr12,fr60 + test_fr_fr fr60,fr12 + test_fr_fr fr62,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr24,fr60 + test_fr_fr fr60,fr24 + test_fr_fr fr62,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr28,fr60 + test_fr_fr fr60,fr28 + test_fr_fr fr61,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr62,fr28 + test_fr_fr fr63,fr20 + test_fr_fr fr63,fr16 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr32,fr60 + test_fr_fr fr60,fr32 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr32 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr36,fr60 + test_fr_fr fr60,fr36 + test_fr_fr fr62,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr40,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr44,fr60 + test_fr_fr fr60,fr44 + test_fr_fr fr62,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr48,fr60 + test_fr_fr fr60,fr48 + test_fr_fr fr62,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr52,fr60 + test_fr_fr fr60,fr52 + test_fr_fr fr62,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmss fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr8,fr28,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr62,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmss fr32,fr36,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr40 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO -- test cases to set ne flags + + pass diff --git a/sim/testsuite/frv/nfdmulcs.cgs b/sim/testsuite/frv/nfdmulcs.cgs new file mode 100644 index 0000000..227ff29 --- /dev/null +++ b/sim/testsuite/frv/nfdmulcs.cgs @@ -0,0 +1,313 @@ +# frv testcase for nfdmulcs $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdmulcs +nfdmulcs: + nfdmulcs fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfdmulcs fr48,fr32,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr52,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + ; test all regs different + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + set_fr_fr fr32,fr50 ; 2 + set_fr_fr fr28,fr51 ; 1 + set_fr_fr fr44,fr52 ; 9 + set_fr_fr fr36,fr53 ; 3 + nfdmulcs fr50,fr52,fr54 ; 2*3, 1*9 + test_fr_fr fr54,fr40 ; 6 + test_fr_fr fr55,fr44 ; 9 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/frv/nfdmuls.cgs b/sim/testsuite/frv/nfdmuls.cgs new file mode 100644 index 0000000..efe1580 --- /dev/null +++ b/sim/testsuite/frv/nfdmuls.cgs @@ -0,0 +1,300 @@ +# frv testcase for nfdmuls $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdmuls +nfdmuls: + nfdmuls fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfdmuls fr48,fr32,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr52,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/frv/nfdsads.cgs b/sim/testsuite/frv/nfdsads.cgs new file mode 100644 index 0000000..6c06f16 --- /dev/null +++ b/sim/testsuite/frv/nfdsads.cgs @@ -0,0 +1,212 @@ +# frv testcase for nfdsads $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdsads +nfdsads: + nfdsads fr16,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr32,fr2 + test_fr_fr fr2,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr36,fr2 + test_fr_fr fr2,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr40,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr44,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr20,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr32,fr2 + test_fr_fr fr2,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr36,fr2 + test_fr_fr fr2,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr40,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr44,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr8,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr12,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr24,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr28,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr36,fr40,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + set_fr_fr fr4,fr49 + nfdsads fr48,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr0,fr53 + nfdsads fr52,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/frv/nfdsqrts.cgs b/sim/testsuite/frv/nfdsqrts.cgs new file mode 100644 index 0000000..1a906bb --- /dev/null +++ b/sim/testsuite/frv/nfdsqrts.cgs @@ -0,0 +1,21 @@ +# frv testcase for nfdsqrts $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfdsqrts +nfdsqrts: + set_fr_iimmed 0x4049,0x0fdb,fr45 ; 3.141592654 + nfdsqrts fr44,fr2 ; 9.0 + test_fr_fr fr2,fr36 ; 3.0 + test_fr_iimmed 0x3fe2dfc5,fr3 ; 1.7724539 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + + pass diff --git a/sim/testsuite/frv/nfdstoi.cgs b/sim/testsuite/frv/nfdstoi.cgs new file mode 100644 index 0000000..56dc941 --- /dev/null +++ b/sim/testsuite/frv/nfdstoi.cgs @@ -0,0 +1,29 @@ +# frv testcase for nfdstoi $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfdstoi +nfdstoi: + set_fr_fr fr20,fr17 + nfdstoi fr16,fr2 + test_fr_iimmed 0,fr2 + test_fr_iimmed 0,fr3 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0xce05,0x4904,fr2 + set_fr_fr fr32,fr3 + nfdstoi fr2,fr2 + test_fr_iimmed 0xdeadbf00,fr2 + test_fr_iimmed 0x00000002,fr3 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + + pass diff --git a/sim/testsuite/frv/nfdsubs.cgs b/sim/testsuite/frv/nfdsubs.cgs new file mode 100644 index 0000000..c981aab --- /dev/null +++ b/sim/testsuite/frv/nfdsubs.cgs @@ -0,0 +1,202 @@ +# frv testcase for nfdsubs $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdsubs +nfdsubs: + nfdsubs fr0,fr16,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr4,fr16,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr8,fr16,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr12,fr16,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr24,fr16,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr28,fr16,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr32,fr16,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr36,fr16,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr40,fr16,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr44,fr16,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr48,fr16,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr52,fr16,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr0,fr20,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr4,fr20,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr8,fr20,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr12,fr20,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr24,fr20,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr28,fr20,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr32,fr20,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr36,fr20,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr40,fr20,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr44,fr20,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr48,fr20,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr52,fr20,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr32,fr36,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr44,fr40,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfdsubs fr4,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr0,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/frv/nfitos.cgs b/sim/testsuite/frv/nfitos.cgs new file mode 100644 index 0000000..539f7b2 --- /dev/null +++ b/sim/testsuite/frv/nfitos.cgs @@ -0,0 +1,44 @@ +# frv testcase for nfitos $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfitos +nfitos: + set_fr_iimmed 0,0,fr1 + nfitos fr1,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0x0000,0x0002,fr1 + nfitos fr1,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr1 + nfitos fr1,fr1 + test_fr_iimmed 0xce054904,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; These were an attempt to cause overflow + set_fr_iimmed 0x7fff,0xffff,fr1 + nfitos fr1,fr1 + test_fr_iimmed 0x4f000000,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0x8000,0x0000,fr1 + nfitos fr1,fr1 + test_fr_iimmed 0xcf000000,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/frv/nfmadds.cgs b/sim/testsuite/frv/nfmadds.cgs new file mode 100644 index 0000000..2113cd2 --- /dev/null +++ b/sim/testsuite/frv/nfmadds.cgs @@ -0,0 +1,227 @@ +# frv testcase for nfmadds $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfmadds +nfmadds: + set_fr_fr fr16,fr1 + nfmadds fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmadds fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr16,fr1 + nfmadds fr28,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr36,fr1 + nfmadds fr28,fr8,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr8,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr36,fr1 + nfmadds fr32,fr36,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + + pass diff --git a/sim/testsuite/frv/nfmas.cgs b/sim/testsuite/frv/nfmas.cgs new file mode 100644 index 0000000..b688dbd --- /dev/null +++ b/sim/testsuite/frv/nfmas.cgs @@ -0,0 +1,297 @@ +# frv testcase for nfmas $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfmas +nfmas: + nfmas fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfmas fr48,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr52,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr56,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr60,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 6,fner1 + test_spr_immed 0,fner0 + + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfmas fr48,fr32,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr52,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr56,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr60,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 6,fner1 + test_spr_immed 0,fner0 + + pass + diff --git a/sim/testsuite/frv/nfmss.cgs b/sim/testsuite/frv/nfmss.cgs new file mode 100644 index 0000000..bc7c8ef --- /dev/null +++ b/sim/testsuite/frv/nfmss.cgs @@ -0,0 +1,279 @@ +# frv testcase for nfmss $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfmss +nfmss: + nfmss fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfmss fr4,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr0,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr56,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr60,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0x6,fner1 + test_spr_immed 0,fner0 + + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfmss fr48,fr32,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr52,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr56,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr60,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0x6,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/frv/nfmsubs.cgs b/sim/testsuite/frv/nfmsubs.cgs new file mode 100644 index 0000000..1ae87e3 --- /dev/null +++ b/sim/testsuite/frv/nfmsubs.cgs @@ -0,0 +1,227 @@ +# frv testcase for nfmsubs $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfmsubs +nfmsubs: + set_fr_fr fr16,fr1 + nfmsubs fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmsubs fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr16,fr1 + nfmsubs fr28,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr32,fr1 + nfmsubs fr8,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr36,fr1 + nfmsubs fr36,fr36,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmsubs fr32,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + pass diff --git a/sim/testsuite/frv/nfmuls.cgs b/sim/testsuite/frv/nfmuls.cgs new file mode 100644 index 0000000..e4b0d2e --- /dev/null +++ b/sim/testsuite/frv/nfmuls.cgs @@ -0,0 +1,228 @@ +# frv testcase for nfmuls $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfmuls +nfmuls: + nfmuls fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr28,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr8,fr28,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr32,fr36,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfmuls fr48,fr32,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr52,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr56,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr60,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/frv/nfsqrts.cgs b/sim/testsuite/frv/nfsqrts.cgs new file mode 100644 index 0000000..8ada77a --- /dev/null +++ b/sim/testsuite/frv/nfsqrts.cgs @@ -0,0 +1,35 @@ +# frv testcase for nfsqrts $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfsqrts +nfsqrts: + nfsqrts fr44,fr1 ; 9.0 + test_fr_fr fr1,fr36 ; 3.0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + nfsqrts fr10,fr10 + test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; fp_exceptions + nfsqrts fr8,fr1 ; -1 -- invalid + test_fr_iimmed 0x7fc00000,fr1 ; nan1 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + test_spr_bits 0x80000000,31,0x0,fqst0 ; fq0.miv is clear + test_spr_bits 0x18000,15,0x0,fqst0 ; fq0.sie is clear + test_spr_bits 0x380,7,0x0,fqst0 ; fq0.ftt is clear + test_spr_bits 0x7e,1,0x0,fqst0 ; fq0.cexc is clear + test_spr_bits 0x1,0,0x0,fqst0 ; fq0.valid is clear + test_spr_immed 0,fqop0 ; fq0.opc + + pass diff --git a/sim/testsuite/frv/nfstoi.cgs b/sim/testsuite/frv/nfstoi.cgs new file mode 100644 index 0000000..2968128 --- /dev/null +++ b/sim/testsuite/frv/nfstoi.cgs @@ -0,0 +1,49 @@ +# frv testcase for nfstoi $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfstoi +nfstoi: + nfstoi fr16,fr1 + test_fr_iimmed 0,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfstoi fr20,fr1 + test_fr_iimmed 0,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfstoi fr32,fr1 + test_fr_iimmed 0x00000002,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0xce05,0x4904,fr1 + nfstoi fr1,fr1 + test_fr_iimmed 0xdeadbf00,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; These were an attempt to cause overflow and nan exceptions + nfstoi fr48,fr1 + test_fr_iimmed 0x7fffffff,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfstoi fr52,fr1 + test_fr_iimmed 0x7fffffff,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfstoi fr56,fr1 + test_fr_iimmed 0x80000000,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/frv/nfsubs.cgs b/sim/testsuite/frv/nfsubs.cgs new file mode 100644 index 0000000..3da08b9 --- /dev/null +++ b/sim/testsuite/frv/nfsubs.cgs @@ -0,0 +1,163 @@ +# frv testcase for nfsubs $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfsubs +nfsubs: + nfsubs fr0,fr16,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr4,fr16,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr8,fr16,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr12,fr16,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr24,fr16,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr28,fr16,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr32,fr16,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr36,fr16,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr40,fr16,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr44,fr16,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr48,fr16,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr52,fr16,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr0,fr20,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr4,fr20,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr8,fr20,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr12,fr20,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr24,fr20,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr28,fr20,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr32,fr20,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr36,fr20,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr40,fr20,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr44,fr20,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr48,fr20,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr52,fr20,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr32,fr36,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr44,fr40,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfsubs fr4,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr0,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr56,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr60,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/frv/nld.cgs b/sim/testsuite/frv/nld.cgs new file mode 100644 index 0000000..297468b --- /dev/null +++ b/sim/testsuite/frv/nld.cgs @@ -0,0 +1,42 @@ +# frv testcase for nld @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nld +nld: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + nld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldbf.cgs b/sim/testsuite/frv/nldbf.cgs new file mode 100644 index 0000000..1a5c25b --- /dev/null +++ b/sim/testsuite/frv/nldbf.cgs @@ -0,0 +1,42 @@ +# frv testcase for nldbf @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldbf +nldbf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + test_spr_limmed 0xc800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + nldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + test_spr_limmed 0xc800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_spr_limmed 0xc800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nldbfi.cgs b/sim/testsuite/frv/nldbfi.cgs new file mode 100644 index 0000000..aa90bc9 --- /dev/null +++ b/sim/testsuite/frv/nldbfi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldbfi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldbfi +nldbfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + nldbfi @(sp,0),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + test_spr_limmed 0xc800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 1,gr20 + nldbfi @(sp,1),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + test_spr_limmed 0xc800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + nldbfi @(sp,-1),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_spr_limmed 0xc800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nldbfu.cgs b/sim/testsuite/frv/nldbfu.cgs new file mode 100644 index 0000000..174042b --- /dev/null +++ b/sim/testsuite/frv/nldbfu.cgs @@ -0,0 +1,46 @@ +# frv testcase for nldbfu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldbfu +nldbfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + nldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + nldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nldd.cgs b/sim/testsuite/frv/nldd.cgs new file mode 100644 index 0000000..1f45761 --- /dev/null +++ b/sim/testsuite/frv/nldd.cgs @@ -0,0 +1,50 @@ +# frv testcase for nldd @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldd +nldd: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + nldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + nldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nlddf.cgs b/sim/testsuite/frv/nlddf.cgs new file mode 100644 index 0000000..d30b6dd --- /dev/null +++ b/sim/testsuite/frv/nlddf.cgs @@ -0,0 +1,50 @@ +# frv testcase for nlddf @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddf +nlddf: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nlddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + nlddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + nlddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nlddfi.cgs b/sim/testsuite/frv/nlddfi.cgs new file mode 100644 index 0000000..b58ad6f --- /dev/null +++ b/sim/testsuite/frv/nlddfi.cgs @@ -0,0 +1,47 @@ +# frv testcase for nlddfi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddfi +nlddfi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_gr sp,gr20 + nlddfi @(sp,0),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + nlddfi @(sp,8),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + nlddfi @(sp,-8),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nlddfu.cgs b/sim/testsuite/frv/nlddfu.cgs new file mode 100644 index 0000000..d45c995 --- /dev/null +++ b/sim/testsuite/frv/nlddfu.cgs @@ -0,0 +1,53 @@ +# frv testcase for nlddfu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddfu +nlddfu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + nlddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + nlddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + nlddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nlddi.cgs b/sim/testsuite/frv/nlddi.cgs new file mode 100644 index 0000000..04d2487 --- /dev/null +++ b/sim/testsuite/frv/nlddi.cgs @@ -0,0 +1,47 @@ +# frv testcase for nlddi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddi +nlddi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_gr sp,gr20 + nlddi @(sp,0),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + nlddi @(sp,8),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + nlddi @(sp,-8),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nlddu.cgs b/sim/testsuite/frv/nlddu.cgs new file mode 100644 index 0000000..44565c8 --- /dev/null +++ b/sim/testsuite/frv/nlddu.cgs @@ -0,0 +1,66 @@ +# frv testcase for nlddu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddu +nlddu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + nlddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + test_spr_limmed 0x88a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + nlddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + test_spr_limmed 0x88a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + nlddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + test_spr_limmed 0x88a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_gr_gr sp,gr8 + nlddu @(gr8,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0c01,nesr3 + test_spr_gr neear3,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldf.cgs b/sim/testsuite/frv/nldf.cgs new file mode 100644 index 0000000..6aabc67 --- /dev/null +++ b/sim/testsuite/frv/nldf.cgs @@ -0,0 +1,42 @@ +# frv testcase for nldf @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldf +nldf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + nldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nldfi.cgs b/sim/testsuite/frv/nldfi.cgs new file mode 100644 index 0000000..20f62df --- /dev/null +++ b/sim/testsuite/frv/nldfi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldfi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldfi +nldfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + nldfi @(sp,0),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + nldfi @(sp,4),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + nldfi @(sp,-4),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nldfu.cgs b/sim/testsuite/frv/nldfu.cgs new file mode 100644 index 0000000..8e95016 --- /dev/null +++ b/sim/testsuite/frv/nldfu.cgs @@ -0,0 +1,45 @@ +# frv testcase for nldfu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldfu +nldfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + nldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + nldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nldhf.cgs b/sim/testsuite/frv/nldhf.cgs new file mode 100644 index 0000000..b90d8f9 --- /dev/null +++ b/sim/testsuite/frv/nldhf.cgs @@ -0,0 +1,41 @@ +# frv testcase for nldhf @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldhf +nldhf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + test_spr_limmed 0xc840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + nldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + test_spr_limmed 0xc840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_spr_limmed 0xc840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nldhfi.cgs b/sim/testsuite/frv/nldhfi.cgs new file mode 100644 index 0000000..bcd52ed --- /dev/null +++ b/sim/testsuite/frv/nldhfi.cgs @@ -0,0 +1,38 @@ +# frv testcase for nldhfi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldhfi +nldhfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + nldhfi @(sp,0),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + test_spr_limmed 0xc840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + nldhfi @(sp,2),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + test_spr_limmed 0xc840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + nldhfi @(sp,-2),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_spr_limmed 0xc840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nldhfu.cgs b/sim/testsuite/frv/nldhfu.cgs new file mode 100644 index 0000000..97d1dd9 --- /dev/null +++ b/sim/testsuite/frv/nldhfu.cgs @@ -0,0 +1,45 @@ +# frv testcase for nldhfu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldhfu +nldhfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + nldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + nldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nldi.cgs b/sim/testsuite/frv/nldi.cgs new file mode 100644 index 0000000..c70f0cb --- /dev/null +++ b/sim/testsuite/frv/nldi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldi +nldi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nldi @(sp,0),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + nldi @(sp,4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + nldi @(sp,-4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldq.cgs b/sim/testsuite/frv/nldq.cgs new file mode 100644 index 0000000..0338e19 --- /dev/null +++ b/sim/testsuite/frv/nldq.cgs @@ -0,0 +1,67 @@ +# frv testcase for nldq @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldq +nldq: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + nldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + nldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldqf.cgs b/sim/testsuite/frv/nldqf.cgs new file mode 100644 index 0000000..8e268ac --- /dev/null +++ b/sim/testsuite/frv/nldqf.cgs @@ -0,0 +1,67 @@ +# frv testcase for nldqf @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqf +nldqf: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + nldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + nldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nldqfi.cgs b/sim/testsuite/frv/nldqfi.cgs new file mode 100644 index 0000000..ff05fae --- /dev/null +++ b/sim/testsuite/frv/nldqfi.cgs @@ -0,0 +1,64 @@ +# frv testcase for nldqfi @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqfi +nldqfi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_gr sp,gr20 + nldqfi @(sp,0),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + nldqfi @(sp,16),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 32,sp + nldqfi @(sp,-16),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nldqfu.cgs b/sim/testsuite/frv/nldqfu.cgs new file mode 100644 index 0000000..ffe2990 --- /dev/null +++ b/sim/testsuite/frv/nldqfu.cgs @@ -0,0 +1,70 @@ +# frv testcase for nldqfu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqfu +nldqfu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_immed 0,gr7 + nldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + nldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + nldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/frv/nldqu.cgs b/sim/testsuite/frv/nldqu.cgs new file mode 100644 index 0000000..a7e8b30 --- /dev/null +++ b/sim/testsuite/frv/nldqu.cgs @@ -0,0 +1,87 @@ +# frv testcase for nldqu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqu +nldqu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + nldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + test_spr_limmed 0x88c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + nldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + test_spr_limmed 0x88c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + nldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + test_spr_limmed 0x88c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + set_gr_gr sp,gr8 + nldqu @(gr8,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0c01,nesr3 + test_spr_gr neear3,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldsb.cgs b/sim/testsuite/frv/nldsb.cgs new file mode 100644 index 0000000..1db547c --- /dev/null +++ b/sim/testsuite/frv/nldsb.cgs @@ -0,0 +1,42 @@ +# frv testcase for nldsb @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldsb +nldsb: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldsb @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + test_spr_limmed 0x8820,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + nldsb @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + test_spr_limmed 0x8820,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldsb @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_spr_limmed 0x8820,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldsbi.cgs b/sim/testsuite/frv/nldsbi.cgs new file mode 100644 index 0000000..4b9dcba --- /dev/null +++ b/sim/testsuite/frv/nldsbi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldsbi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldsbi +nldsbi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nldsbi @(sp,0),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + test_spr_limmed 0x8820,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr20 + nldsbi @(sp,1),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + test_spr_limmed 0x8820,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + nldsbi @(sp,-1),gr8 + test_gr_immed 0,gr8 + test_spr_limmed 0x8820,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldsbu.cgs b/sim/testsuite/frv/nldsbu.cgs new file mode 100644 index 0000000..e60ffc0 --- /dev/null +++ b/sim/testsuite/frv/nldsbu.cgs @@ -0,0 +1,56 @@ +# frv testcase for nldsbu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldsbu +nldsbu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nldsbu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8820,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + nldsbu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8820,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldsbu @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8820,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -3,sp + set_mem_limmed 0x0000,0x00da,sp + set_gr_immed 3,gr7 + nldsbu @(sp,gr7),sp + test_gr_limmed 0xffff,0xffda,sp + test_spr_limmed 0x8120,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldsh.cgs b/sim/testsuite/frv/nldsh.cgs new file mode 100644 index 0000000..afc00c4 --- /dev/null +++ b/sim/testsuite/frv/nldsh.cgs @@ -0,0 +1,41 @@ +# frv testcase for nldsh @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldsh +nldsh: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldsh @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + test_spr_limmed 0x8860,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + nldsh @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + test_spr_limmed 0x8860,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nldsh @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_spr_limmed 0x8860,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldshi.cgs b/sim/testsuite/frv/nldshi.cgs new file mode 100644 index 0000000..60de156 --- /dev/null +++ b/sim/testsuite/frv/nldshi.cgs @@ -0,0 +1,38 @@ +# frv testcase for nldshi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldshi +nldshi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nldshi @(sp,0),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + test_spr_limmed 0x8860,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + nldshi @(sp,2),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + test_spr_limmed 0x8860,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + nldshi @(sp,-2),gr8 + test_gr_immed 0,gr8 + test_spr_limmed 0x8860,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldshu.cgs b/sim/testsuite/frv/nldshu.cgs new file mode 100644 index 0000000..775b760 --- /dev/null +++ b/sim/testsuite/frv/nldshu.cgs @@ -0,0 +1,55 @@ +# frv testcase for nldshu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldshu +nldshu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nldshu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8860,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + nldshu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8860,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nldshu @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8860,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -2,sp + set_mem_limmed 0x0000,0xdead,sp + set_gr_immed 2,gr7 + nldshu @(sp,gr7),sp + test_gr_limmed 0xffff,0xdead,sp + test_spr_limmed 0x8160,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldu.cgs b/sim/testsuite/frv/nldu.cgs new file mode 100644 index 0000000..0d1735e --- /dev/null +++ b/sim/testsuite/frv/nldu.cgs @@ -0,0 +1,55 @@ +# frv testcase for nldu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldu +nldu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8880,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8880,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + nldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8880,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nldu @(sp,gr7),sp + test_gr_limmed 0xdead,0xbeef,sp + test_spr_limmed 0x8180,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldub.cgs b/sim/testsuite/frv/nldub.cgs new file mode 100644 index 0000000..2067bcc --- /dev/null +++ b/sim/testsuite/frv/nldub.cgs @@ -0,0 +1,42 @@ +# frv testcase for nldub @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldub +nldub: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + test_spr_limmed 0x8800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + nldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + test_spr_limmed 0x8800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldubi.cgs b/sim/testsuite/frv/nldubi.cgs new file mode 100644 index 0000000..8eba516 --- /dev/null +++ b/sim/testsuite/frv/nldubi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldubi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldubi +nldubi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nldubi @(sp,0),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + test_spr_limmed 0x8800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr20 + nldubi @(sp,1),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + test_spr_limmed 0x8800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + nldubi @(sp,-1),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nldubu.cgs b/sim/testsuite/frv/nldubu.cgs new file mode 100644 index 0000000..acf9d9c --- /dev/null +++ b/sim/testsuite/frv/nldubu.cgs @@ -0,0 +1,55 @@ +# frv testcase for nldubu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldubu +nldubu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8800,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + nldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8800,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8800,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -3,sp + set_mem_limmed 0xffff,0xffda,sp + set_gr_immed 3,gr7 + nldubu @(sp,gr7),sp + test_gr_limmed 0x0000,0x00da,sp + test_spr_limmed 0x8100,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nlduh.cgs b/sim/testsuite/frv/nlduh.cgs new file mode 100644 index 0000000..1871a22 --- /dev/null +++ b/sim/testsuite/frv/nlduh.cgs @@ -0,0 +1,41 @@ +# frv testcase for nlduh @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlduh +nlduh: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nlduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + test_spr_limmed 0x8840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + nlduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + test_spr_limmed 0x8840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nlduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nlduhi.cgs b/sim/testsuite/frv/nlduhi.cgs new file mode 100644 index 0000000..ae7171e --- /dev/null +++ b/sim/testsuite/frv/nlduhi.cgs @@ -0,0 +1,38 @@ +# frv testcase for nlduhi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlduhi +nlduhi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nlduhi @(sp,0),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + test_spr_limmed 0x8840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + nlduhi @(sp,2),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + test_spr_limmed 0x8840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + nlduhi @(sp,-2),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nlduhu.cgs b/sim/testsuite/frv/nlduhu.cgs new file mode 100644 index 0000000..8142fc5 --- /dev/null +++ b/sim/testsuite/frv/nlduhu.cgs @@ -0,0 +1,55 @@ +# frv testcase for nlduhu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlduhu +nlduhu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nlduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8840,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + nlduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8840,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nlduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8840,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0xdead,sp + set_gr_immed 2,gr7 + nlduhu @(sp,gr7),sp + test_gr_limmed 0x0000,0xdead,sp + test_spr_limmed 0x8140,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/frv/nop.cgs b/sim/testsuite/frv/nop.cgs new file mode 100644 index 0000000..7180066 --- /dev/null +++ b/sim/testsuite/frv/nop.cgs @@ -0,0 +1,12 @@ +# frv testcase for nop +# mach: all + + .include "testutils.inc" + + start + + .global nop +nop: + nop + + pass diff --git a/sim/testsuite/frv/norcr.cgs b/sim/testsuite/frv/norcr.cgs new file mode 100644 index 0000000..e097a1b --- /dev/null +++ b/sim/testsuite/frv/norcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for norcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global norcr +norcr: + set_spr_immed 0x1b1b,cccr + norcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + norcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + norcr cc7,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc7,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + norcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + norcr cc6,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc6,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc5,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc5,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc5,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc5,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc4,cc7,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc4,cc6,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc4,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc4,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/frv/norncr.cgs b/sim/testsuite/frv/norncr.cgs new file mode 100644 index 0000000..a7b95da --- /dev/null +++ b/sim/testsuite/frv/norncr.cgs @@ -0,0 +1,59 @@ +# frv testcase for norncr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global norncr +norncr: + set_spr_immed 0x1b1b,cccr + norncr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + norncr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + norncr cc7,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc7,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + norncr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + norncr cc6,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc6,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc5,cc7,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc5,cc6,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc5,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc5,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc4,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc4,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc4,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc4,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/frv/not.cgs b/sim/testsuite/frv/not.cgs new file mode 100644 index 0000000..e44eabf --- /dev/null +++ b/sim/testsuite/frv/not.cgs @@ -0,0 +1,18 @@ +# frv testcase for not $GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global not +not: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + not gr7,gr7 + test_gr_limmed 0x5555,0x5555,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + not gr7,gr7 + test_gr_limmed 0x2152,0x4110,gr7 + + pass diff --git a/sim/testsuite/frv/notcr.cgs b/sim/testsuite/frv/notcr.cgs new file mode 100644 index 0000000..e6c08e0 --- /dev/null +++ b/sim/testsuite/frv/notcr.cgs @@ -0,0 +1,23 @@ +# frv testcase for notcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global notcr +notcr: + set_spr_immed 0x1b1b,cccr + notcr cc7,cc3 + test_spr_immed 0x1b5b,cccr + + notcr cc6,cc3 + test_spr_immed 0x1b1b,cccr + + notcr cc5,cc3 + test_spr_immed 0x1bdb,cccr + + notcr cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/frv/nsdiv.cgs b/sim/testsuite/frv/nsdiv.cgs new file mode 100644 index 0000000..533f2ef --- /dev/null +++ b/sim/testsuite/frv/nsdiv.cgs @@ -0,0 +1,64 @@ +# frv testcase for nsdiv $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global nsdiv +nsdiv: + set_spr_immed 0,gner0 + set_spr_immed 0,gner1 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + nsdiv gr1,gr3,gr2 + test_gr_immed 4,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + nsdiv gr1,gr3,gr2 + test_gr_immed -1,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + set_spr_immed 4,gner1 ; turn on NE bit for gr2 + nsdiv gr1,gr3,gr2 ; overflow is masked + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + nsdiv gr1,gr0,gr32 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + nsdiv gr1,gr3,gr2 + test_gr_limmed 0x8000,0x0000,gr2 + test_spr_immed 1,gner0 + test_spr_immed 4,gner1 + + nsdiv gr1,gr0,gr10 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0x00000404,gner1 + + ; simple division 12 / 3 -- should turn off ne flag + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + nsdiv gr1,gr3,gr2 + test_gr_immed 4,gr2 + test_spr_immed 1,gner0 + test_spr_immed 0x00000400,gner1 + + pass diff --git a/sim/testsuite/frv/nsdivi.cgs b/sim/testsuite/frv/nsdivi.cgs new file mode 100644 index 0000000..014fadd --- /dev/null +++ b/sim/testsuite/frv/nsdivi.cgs @@ -0,0 +1,64 @@ +# frv testcase for nsdivi $GRi,$s12,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global nsdivi +nsdivi: + set_spr_immed 0,gner0 + set_spr_immed 0,gner1 + + ; simple division 12 / 3 + set_gr_immed 12,gr1 + nsdivi gr1,3,gr2 + test_gr_immed 4,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; Random example + set_gr_limmed 0xfedc,0xba98,gr1 + nsdivi gr1,0x7ff,gr2 + test_gr_limmed 0xffff,0xdb93,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; Random negative example + set_gr_limmed 0xfedc,0xba98,gr1 + nsdivi gr1,-2048,gr2 + test_gr_immed 0x2468,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + nsdivi gr1,-1,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + nsdivi gr1,0,gr32 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + nsdivi gr1,-1,gr2 + test_gr_limmed 0x8000,0x0000,gr2 + test_spr_immed 1,gner0 + test_spr_immed 4,gner1 + + nsdivi gr1,0,gr10 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0x00000404,gner1 + + ; simple division 12 / 3 -- should turn off ne flag + set_gr_immed 12,gr1 + nsdivi gr1,3,gr2 + test_gr_immed 4,gr2 + test_spr_immed 1,gner0 + test_spr_immed 0x00000400,gner1 + + pass diff --git a/sim/testsuite/frv/nudiv.cgs b/sim/testsuite/frv/nudiv.cgs new file mode 100644 index 0000000..58bce82 --- /dev/null +++ b/sim/testsuite/frv/nudiv.cgs @@ -0,0 +1,49 @@ +# frv testcase for nudiv $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global nudiv +nudiv: + set_spr_immed 0,gner0 + set_spr_immed 0,gner1 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + nudiv gr3,gr2,gr3 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; example 1 from the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + nudiv gr3,gr2,gr3 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + or_spr_immed 0x20,isr ; turn on isr.edem + nudiv gr1,gr0,gr32 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + and_spr_immed -33,isr ; turn off isr.edem + nudiv gr1,gr0,gr10 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0x00000400,gner1 + + ; simple division 12 / 3 -- should turn off ne flag + set_gr_immed 12,gr1 + set_gr_immed 3,gr3 + nudiv gr1,gr3,gr10 + test_gr_immed 4,gr10 + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + pass diff --git a/sim/testsuite/frv/nudivi.cgs b/sim/testsuite/frv/nudivi.cgs new file mode 100644 index 0000000..2426eb3 --- /dev/null +++ b/sim/testsuite/frv/nudivi.cgs @@ -0,0 +1,51 @@ +# frv testcase for nudivi $GRi,$s12,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global nudivi +nudivi: + set_spr_immed 0,gner0 + set_spr_immed 0,gner1 + + ; simple division 12 / 3 + set_gr_immed 0x0000000c,gr3 + nudivi gr3,3,gr3 + test_gr_immed 0x00000004,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; random example + set_gr_limmed 0xfedc,0xba98,gr3 + nudivi gr3,0x7ff,gr3 + test_gr_limmed 0x001f,0xdf93,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; random example + set_gr_limmed 0xffff,0xffff,gr3 + nudivi gr3,-2048,gr3 + test_gr_immed 1,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + or_spr_immed 0x20,isr ; turn on isr.edem + nudivi gr1,0,gr32 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + and_spr_immed -33,isr ; turn off isr.edem + nudivi gr1,0,gr10 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0x00000400,gner1 + + ; simple division 12 / 3 -- should turn off ne flag + set_gr_immed 12,gr1 + nudivi gr1,3,gr10 + test_gr_immed 4,gr10 + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + pass diff --git a/sim/testsuite/frv/or.cgs b/sim/testsuite/frv/or.cgs new file mode 100644 index 0000000..b432429 --- /dev/null +++ b/sim/testsuite/frv/or.cgs @@ -0,0 +1,31 @@ +# frv testcase for or $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global or +or: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + or gr7,gr8,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + or gr7,gr8,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + or gr7,gr8,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/orcc.cgs b/sim/testsuite/frv/orcc.cgs new file mode 100644 index 0000000..a0a3e5b --- /dev/null +++ b/sim/testsuite/frv/orcc.cgs @@ -0,0 +1,31 @@ +# frv testcase for orcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global orcc +orcc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + orcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + orcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + orcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/orcr.cgs b/sim/testsuite/frv/orcr.cgs new file mode 100644 index 0000000..a5114b2 --- /dev/null +++ b/sim/testsuite/frv/orcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for orcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global orcr +orcr: + set_spr_immed 0x1b1b,cccr + orcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + orcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + orcr cc7,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc7,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + orcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + orcr cc6,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc6,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc5,cc7,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc5,cc6,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc5,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc5,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc4,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc4,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc4,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc4,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/ori.cgs b/sim/testsuite/frv/ori.cgs new file mode 100644 index 0000000..aa1d61a --- /dev/null +++ b/sim/testsuite/frv/ori.cgs @@ -0,0 +1,34 @@ +# frv testcase for ori $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ori +ori: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x07,0 ; Set mask opposite of expected + ori gr7,0x555,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xaaaa,0xafff,gr8 + + set_gr_immed 0x00000000,gr7 + set_icc 0x08,0 ; Set mask opposite of expected + ori gr7,0,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xb800,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + ori gr7,0x6ef,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xdead,0xb000,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + ori gr7,-273,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xffff,0xfeef,gr8 + + pass diff --git a/sim/testsuite/frv/oricc.cgs b/sim/testsuite/frv/oricc.cgs new file mode 100644 index 0000000..71e6d53 --- /dev/null +++ b/sim/testsuite/frv/oricc.cgs @@ -0,0 +1,34 @@ +# frv testcase for oricc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global oricc +oricc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x07,0 ; Set mask opposite of expected + oricc gr7,0x155,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xabff,gr8 + + set_gr_immed 0x00000000,gr7 + set_icc 0x08,0 ; Set mask opposite of expected + oricc gr7,0,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbe00,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + oricc gr7,0x0ef,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xdead,0xb000,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + oricc gr7,-273,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xfeef,gr8 + + pass diff --git a/sim/testsuite/frv/orncr.cgs b/sim/testsuite/frv/orncr.cgs new file mode 100644 index 0000000..b0e4e59 --- /dev/null +++ b/sim/testsuite/frv/orncr.cgs @@ -0,0 +1,59 @@ +# frv testcase for orncr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global orncr +orncr: + set_spr_immed 0x1b1b,cccr + orncr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + orncr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + orncr cc7,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc7,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + orncr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + orncr cc6,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc6,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc5,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc5,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc5,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc5,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc4,cc7,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc4,cc6,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc4,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc4,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/frv/parallel.exp b/sim/testsuite/frv/parallel.exp new file mode 100644 index 0000000..8101a67a --- /dev/null +++ b/sim/testsuite/frv/parallel.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500 fr550 fr400" + set cpu_option -mcpu + + # The .pcgs suffix is for "parallel cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.pcgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/frv/ret.cgs b/sim/testsuite/frv/ret.cgs new file mode 100644 index 0000000..1447998 --- /dev/null +++ b/sim/testsuite/frv/ret.cgs @@ -0,0 +1,91 @@ +# frv testcase for ret +# mach: all + + .include "testutils.inc" + + start + + .global ret +ret: + set_spr_addr ok1,lr + set_icc 0x0 0 + ret + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + ret + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + ret + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + ret + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + ret + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + ret + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + ret + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + ret + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + ret + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + ret + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + ret + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + ret + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + ret + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + ret + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + ret + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + ret + fail +okg: + + pass diff --git a/sim/testsuite/frv/rett.cgs b/sim/testsuite/frv/rett.cgs new file mode 100644 index 0000000..f964bae --- /dev/null +++ b/sim/testsuite/frv/rett.cgs @@ -0,0 +1,30 @@ +# frv testcase for rett $debug +# mach: all + + .include "testutils.inc" + + start + + .global rett +rett: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x0 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 +ok0: + test_gr_immed 1,gr7 + pass + fail +ok1: + inc_gr_immed 1,gr7 + rett 1 ; should be a nop + rett 0 + fail diff --git a/sim/testsuite/frv/scan.cgs b/sim/testsuite/frv/scan.cgs new file mode 100644 index 0000000..d19107d --- /dev/null +++ b/sim/testsuite/frv/scan.cgs @@ -0,0 +1,73 @@ +# frv testcase for scan $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global scan +scan: + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + scan gr7,gr8,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + scan gr7,gr8,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + scan gr7,gr8,gr9 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + scan gr7,gr8,gr9 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + scan gr7,gr8,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + scan gr7,gr8,gr9 + test_gr_immed 2,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + scan gr7,gr8,gr9 + test_gr_immed 16,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + scan gr7,gr8,gr9 + test_gr_immed 31,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + scan gr7,gr8,gr9 + test_gr_immed 7,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/frv/scani.cgs b/sim/testsuite/frv/scani.cgs new file mode 100644 index 0000000..97175dc --- /dev/null +++ b/sim/testsuite/frv/scani.cgs @@ -0,0 +1,55 @@ +# frv testcase for scani $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global scani +scani: + set_gr_limmed 0xffff,0xfeaa,gr7 + scani gr7,0x2aa,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xfeaa,gr7 + + set_gr_limmed 0xffff,0xfeaa,gr7 + scani gr7,0x2ab,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xfeaa,gr7 + + set_gr_limmed 0x0000,0x0155,gr7 + scani gr7,0x2aa,gr9 + test_gr_immed 63,gr9 + test_gr_limmed 0x0000,0x0155,gr7 + + set_gr_limmed 0x0000,0x0155,gr7 + scani gr7,0x2ab,gr9 + test_gr_immed 63,gr9 + test_gr_limmed 0x0000,0x0155,gr7 + + set_gr_limmed 0x7fff,0xffff,gr7 + scani gr7,-1,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0x7fff,0xffff,gr7 + + set_gr_limmed 0xbfff,0xffff,gr7 + scani gr7,-1,gr9 + test_gr_immed 1,gr9 + test_gr_limmed 0xbfff,0xffff,gr7 + + set_gr_limmed 0xfffe,0xffff,gr7 + scani gr7,-1,gr9 + test_gr_immed 15,gr9 + test_gr_limmed 0xfffe,0xffff,gr7 + + set_gr_limmed 0xffff,0xfffd,gr7 + scani gr7,-1,gr9 + test_gr_immed 30,gr9 + test_gr_limmed 0xffff,0xfffd,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + scani gr7,-2048,gr9 + test_gr_immed 2,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + + pass diff --git a/sim/testsuite/frv/sdiv.cgs b/sim/testsuite/frv/sdiv.cgs new file mode 100644 index 0000000..d193b23 --- /dev/null +++ b/sim/testsuite/frv/sdiv.cgs @@ -0,0 +1,75 @@ +# frv testcase for sdiv $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sdiv +sdiv: + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + sdiv gr1,gr3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + sdiv gr1,gr3,gr2 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + sdiv gr1,gr3,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e1,gr17 + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdiv gr1,gr3,gr2 ; overflow + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2; gr2 updated + + ; divide by zero + set_spr_addr ok2,lr + set_gr_addr e2,gr17 + set_gr_immed 0xdeadbeef,gr2 +e2: sdiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 2,gr15 ; handler called + test_gr_immed 0xdeadbeef,gr2 ; gr2 not updated. + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/sdivi.cgs b/sim/testsuite/frv/sdivi.cgs new file mode 100644 index 0000000..eb781e7 --- /dev/null +++ b/sim/testsuite/frv/sdivi.cgs @@ -0,0 +1,74 @@ +# frv testcase for sdivi $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sdivi +sdivi: + ; simple division 12 / 3 + set_gr_immed 12,gr1 + sdivi gr1,3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,0x7ff,gr2 + test_gr_limmed 0xffff,0xdb93,gr2 + + ; Random negative example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,-2048,gr2 + test_gr_immed 0x2468,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + sdivi gr1,-1,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e1,gr17 + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdivi gr1,-1,gr2 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; divide by zero + set_spr_addr ok2,lr + set_gr_addr e2,gr17 +e2: sdivi gr1,0,gr2 ; divide by zero + test_gr_immed 2,gr15 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/sethi.cgs b/sim/testsuite/frv/sethi.cgs new file mode 100644 index 0000000..00a3bdd --- /dev/null +++ b/sim/testsuite/frv/sethi.cgs @@ -0,0 +1,18 @@ +# frv testcase for sethi $s16,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sethi +sethi: + set_gr_immed 0,gr1 + sethi 0,gr1 + test_gr_immed 0,gr1 + sethi 1,gr1 + test_gr_immed 0x00010000,gr1 + sethi 0x7fff,gr1 + test_gr_immed 0x7fff0000,gr1 + + pass diff --git a/sim/testsuite/frv/sethilo.pcgs b/sim/testsuite/frv/sethilo.pcgs new file mode 100644 index 0000000..c8e7b60 --- /dev/null +++ b/sim/testsuite/frv/sethilo.pcgs @@ -0,0 +1,18 @@ +# frv parallel testcase for sethi $s16,$GRk and setlo $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sethilo +sethilo: + sethi.p 0xdead,gr7 + setlo 0xbeef,gr7 + test_gr_immed 0xdeadbeef,gr7 + + setlo.p 0xdead,gr7 + sethi 0xbeef,gr7 + test_gr_immed 0xbeefdead,gr7 + + pass diff --git a/sim/testsuite/frv/setlo.cgs b/sim/testsuite/frv/setlo.cgs new file mode 100644 index 0000000..6bdac2e --- /dev/null +++ b/sim/testsuite/frv/setlo.cgs @@ -0,0 +1,18 @@ +# frv testcase for setlo $s16,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_gr_immed 0,gr1 + setlo 0,gr1 + test_gr_immed 0,gr1 + setlo 1,gr1 + test_gr_immed 1,gr1 + setlo 0x7fff,gr1 + test_gr_immed 0x7fff,gr1 + + pass diff --git a/sim/testsuite/frv/setlos.cgs b/sim/testsuite/frv/setlos.cgs new file mode 100644 index 0000000..8979d13 --- /dev/null +++ b/sim/testsuite/frv/setlos.cgs @@ -0,0 +1,21 @@ +# frv testcase for setlos $s16,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global setlos +setlos: + setlos 0,gr1 + test_gr_immed 0,gr1 + setlos 1,gr1 + test_gr_immed 1,gr1 + setlos 0x7fff,gr1 + test_gr_immed 0x7fff,gr1 + setlos -1,gr1 + test_gr_immed -1,gr1 + setlos -32768,gr1 + test_gr_immed -32768,gr1 + + pass diff --git a/sim/testsuite/frv/sll.cgs b/sim/testsuite/frv/sll.cgs new file mode 100644 index 0000000..9103cf6 --- /dev/null +++ b/sim/testsuite/frv/sll.cgs @@ -0,0 +1,38 @@ +# frv testcase for sll $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sll +sll: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + sll gr8,gr7,gr8 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sll gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sll gr8,gr7,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + sll gr8,gr7,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/frv/sllcc.cgs b/sim/testsuite/frv/sllcc.cgs new file mode 100644 index 0000000..533b504 --- /dev/null +++ b/sim/testsuite/frv/sllcc.cgs @@ -0,0 +1,38 @@ +# frv testcase for sllcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global sllcc +sllcc: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sllcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sllcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sllcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + sllcc gr8,gr7,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/frv/slli.cgs b/sim/testsuite/frv/slli.cgs new file mode 100644 index 0000000..80c25c0 --- /dev/null +++ b/sim/testsuite/frv/slli.cgs @@ -0,0 +1,34 @@ +# frv testcase for slli $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global slli +slli: + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + slli gr8,0x7e0,gr8 ; Shift by 0 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + slli gr8,-31,gr8 ; Shift by 1 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + slli gr8,31,gr8 ; Shift by 31 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + slli gr8,31,gr8 ; clear register + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/frv/sllicc.cgs b/sim/testsuite/frv/sllicc.cgs new file mode 100644 index 0000000..b8e4c7d --- /dev/null +++ b/sim/testsuite/frv/sllicc.cgs @@ -0,0 +1,34 @@ +# frv testcase for sllicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global sllicc +sllicc: + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sllicc gr8,0x1e0,gr8,icc0 ; Shift by 0 + test_icc 0 0 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sllicc gr8,-31,gr8,icc0 ; Shift by 1 + test_icc 0 0 0 1 icc0 + test_gr_immed 4,gr8 + + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sllicc gr8,31,gr8,icc0 ; Shift by 31 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 2,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + sllicc gr8,31,gr8,icc0 ; clear register + test_icc 0 1 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/frv/smul.cgs b/sim/testsuite/frv/smul.cgs new file mode 100644 index 0000000..ed065a9 --- /dev/null +++ b/sim/testsuite/frv/smul.cgs @@ -0,0 +1,182 @@ +# frv testcase for smul $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global smul +smul: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + smul gr7,gr8,gr8 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + smul gr7,gr8,gr8 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + smul gr7,gr8,gr8 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + pass diff --git a/sim/testsuite/frv/smulcc.cgs b/sim/testsuite/frv/smulcc.cgs new file mode 100644 index 0000000..76a009e --- /dev/null +++ b/sim/testsuite/frv/smulcc.cgs @@ -0,0 +1,238 @@ +# frv testcase for smulcc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global smulcc +smulcc: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0xb,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x8,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0xd,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0xe,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0xf,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0xc,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x5,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x6,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x7,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x4,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0x9,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xa,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x4,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x5,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x6,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x7,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xc,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xd,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0xe,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0xc,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0xd,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xe,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xf,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + pass diff --git a/sim/testsuite/frv/smuli.cgs b/sim/testsuite/frv/smuli.cgs new file mode 100644 index 0000000..19a695c --- /dev/null +++ b/sim/testsuite/frv/smuli.cgs @@ -0,0 +1,210 @@ +# frv testcase for smuli $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global smuli +smuli: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0x0,0 + smuli gr7,2,gr8 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0x1,0 + smuli gr7,2,gr8 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_icc 0x2,0 + smuli gr7,1,gr8 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0x3,0 + smuli gr7,2,gr8 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_icc 0x4,0 + smuli gr7,0,gr8 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_icc 0x5,0 + smuli gr7,2,gr8 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x6,0 + smuli gr7,2,gr8 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_icc 0x7,0 + smuli gr7,4,gr8 + test_icc 0 1 1 1 icc0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_icc 0x8,0 + smuli gr7,0x7ff,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x3ff,gr8 + test_gr_limmed 0x7fff,0xf801,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_icc 0x9,0 + smuli gr7,2,gr8 + test_icc 1 0 0 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0xa,0 + smuli gr7,-2,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0xb,0 + smuli gr7,-2,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_icc 0xc,0 + smuli gr7,1,gr8 + test_icc 1 1 0 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0xd,0 + smuli gr7,-2,gr8 + test_icc 1 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_icc 0xe,0 + smuli gr7,0,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_icc 0xf,0 + smuli gr7,-2,gr8 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x0,0 + smuli gr7,-2,gr8 + test_icc 0 0 0 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_icc 0x1,0 + smuli gr7,-2,gr8 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_icc 0x2,0 + smuli gr7,-4,gr8 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_icc 0x3,0 + smuli gr7,-2048,gr8 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0xffff,0xfc00,gr8 + test_gr_limmed 0x0000,0x0800,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_icc 0x4,0 + smuli gr7,-2,gr8 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_icc 0x5,0 + smuli gr7,-2,gr8 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_icc 0x6,0 + smuli gr7,-1,gr8 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_icc 0x7,0 + smuli gr7,-2,gr8 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_icc 0x8,0 + smuli gr7,-2,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_icc 0x9,0 + smuli gr7,-4,gr8 + test_icc 1 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_icc 0xa,0 + smuli gr7,-2048,gr8 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x0000,0x03ff,gr8 + test_gr_limmed 0xffff,0xf800,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_icc 0xb,0 + smuli gr7,-2048,gr8 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x0000,0x0400,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + pass diff --git a/sim/testsuite/frv/smulicc.cgs b/sim/testsuite/frv/smulicc.cgs new file mode 100644 index 0000000..e9aa889 --- /dev/null +++ b/sim/testsuite/frv/smulicc.cgs @@ -0,0 +1,210 @@ +# frv testcase for smulicc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global smulicc +smulicc: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0x0,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0x1,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_icc 0x2,0 + smulicc gr7,1,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0x3,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_icc 0x4,0 + smulicc gr7,0,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_icc 0x5,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x6,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_icc 0x7,0 + smulicc gr7,4,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_icc 0x8,0 + smulicc gr7,0x1ff,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0xff,gr8 + test_gr_limmed 0x7fff,0xfe01,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_icc 0x9,0 + smulicc gr7,2,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0xa,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0xb,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_icc 0xc,0 + smulicc gr7,1,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0xd,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_icc 0xe,0 + smulicc gr7,0,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_icc 0xf,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x0,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_icc 0x1,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_icc 0x2,0 + smulicc gr7,-4,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_icc 0x3,0 + smulicc gr7,-512,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xff00,gr8 + test_gr_limmed 0x0000,0x0200,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_icc 0x4,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_icc 0x5,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_icc 0x6,0 + smulicc gr7,-1,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_icc 0x7,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_icc 0x8,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_icc 0x9,0 + smulicc gr7,-4,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_icc 0xa,0 + smulicc gr7,-512,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x0000,0x00ff,gr8 + test_gr_limmed 0xffff,0xfe00,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_icc 0xb,0 + smulicc gr7,-512,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0x0000,0x0100,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + pass diff --git a/sim/testsuite/frv/sra.cgs b/sim/testsuite/frv/sra.cgs new file mode 100644 index 0000000..0f0c864 --- /dev/null +++ b/sim/testsuite/frv/sra.cgs @@ -0,0 +1,38 @@ +# frv testcase for sra $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sra +sra: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + sra gr8,gr7,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sra gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sra gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + sra gr8,gr7,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/frv/sracc.cgs b/sim/testsuite/frv/sracc.cgs new file mode 100644 index 0000000..14f4a8b --- /dev/null +++ b/sim/testsuite/frv/sracc.cgs @@ -0,0 +1,38 @@ +# frv testcase for sracc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global sracc +sracc: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + sracc gr8,gr7,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sracc gr8,gr7,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sracc gr8,gr7,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + sracc gr8,gr7,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/frv/srai.cgs b/sim/testsuite/frv/srai.cgs new file mode 100644 index 0000000..02b9654 --- /dev/null +++ b/sim/testsuite/frv/srai.cgs @@ -0,0 +1,34 @@ +# frv testcase for srai $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global srai +srai: + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srai gr8,0x7e0,gr8 ; Shift by 0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srai gr8,-31,gr8 ; Shift by 1 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srai gr8,31,gr8 ; Shift by 31 + test_icc 1 1 1 1 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srai gr8,31,gr8 ; clear register + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/frv/sraicc.cgs b/sim/testsuite/frv/sraicc.cgs new file mode 100644 index 0000000..5dbd1e6 --- /dev/null +++ b/sim/testsuite/frv/sraicc.cgs @@ -0,0 +1,34 @@ +# frv testcase for sraicc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global sraicc +sraicc: + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + sraicc gr8,0x1e0,gr8,icc0 ; Shift by 0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sraicc gr8,-31,gr8,icc0 ; Shift by 1 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sraicc gr8,31,gr8,icc0 ; Shift by 31 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + sraicc gr8,31,gr8,icc0 ; clear register + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/frv/srl.cgs b/sim/testsuite/frv/srl.cgs new file mode 100644 index 0000000..045e75e --- /dev/null +++ b/sim/testsuite/frv/srl.cgs @@ -0,0 +1,38 @@ +# frv testcase for srl $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global srl +srl: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srl gr8,gr7,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srl gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srl gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srl gr8,gr7,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/frv/srlcc.cgs b/sim/testsuite/frv/srlcc.cgs new file mode 100644 index 0000000..1450a4b --- /dev/null +++ b/sim/testsuite/frv/srlcc.cgs @@ -0,0 +1,38 @@ +# frv testcase for srlcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global srlcc +srlcc: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srlcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srlcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srlcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srlcc gr8,gr7,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/frv/srli.cgs b/sim/testsuite/frv/srli.cgs new file mode 100644 index 0000000..72207d3 --- /dev/null +++ b/sim/testsuite/frv/srli.cgs @@ -0,0 +1,34 @@ +# frv testcase for srli $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global srli +srli: + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srli gr8,0x7e0,gr8 ; Shift by 0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srli gr8,-31,gr8 ; Shift by 1 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srli gr8,31,gr8 ; Shift by 31 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srli gr8,31,gr8 ; clear register + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/frv/srlicc.cgs b/sim/testsuite/frv/srlicc.cgs new file mode 100644 index 0000000..d232802 --- /dev/null +++ b/sim/testsuite/frv/srlicc.cgs @@ -0,0 +1,34 @@ +# frv testcase for srlicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global srlicc +srlicc: + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srlicc gr8,0x1e0,gr8,icc0 ; Shift by 0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srlicc gr8,-31,gr8,icc0 ; Shift by 1 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srlicc gr8,31,gr8,icc0 ; Shift by 31 + test_icc 0 0 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srlicc gr8,31,gr8,icc0 ; clear register + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/frv/st.cgs b/sim/testsuite/frv/st.cgs new file mode 100644 index 0000000..557713c --- /dev/null +++ b/sim/testsuite/frv/st.cgs @@ -0,0 +1,16 @@ +# frv testcase for st $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + st gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + + pass diff --git a/sim/testsuite/frv/stb.cgs b/sim/testsuite/frv/stb.cgs new file mode 100644 index 0000000..15fa1e6 --- /dev/null +++ b/sim/testsuite/frv/stb.cgs @@ -0,0 +1,16 @@ +# frv testcase for stb $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + stb gr8,@(sp,gr7) + test_mem_limmed 0xffad,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/stbf.cgs b/sim/testsuite/frv/stbf.cgs new file mode 100644 index 0000000..741327d --- /dev/null +++ b/sim/testsuite/frv/stbf.cgs @@ -0,0 +1,16 @@ +# frv testcase for stbf $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbf +stbf: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + stbf fr8,@(sp,gr7) + test_mem_limmed 0xffad,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/stbfi.cgs b/sim/testsuite/frv/stbfi.cgs new file mode 100644 index 0000000..cfea708 --- /dev/null +++ b/sim/testsuite/frv/stbfi.cgs @@ -0,0 +1,24 @@ +# frv testcase for stbfi $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbfi +stbfi: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xffff,0xffff,fr8 + stbfi fr8,@(sp,0) + test_mem_limmed 0xffad,0xbeef,sp + + inc_gr_immed 0x801,sp ; 2049 + stbfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xbeef,gr20 + + inc_gr_immed -4094,sp + stbfi fr8,@(sp,0x7ff) + test_mem_limmed 0xffff,0xffef,gr20 + + pass diff --git a/sim/testsuite/frv/stbfu.cgs b/sim/testsuite/frv/stbfu.cgs new file mode 100644 index 0000000..01bbb99 --- /dev/null +++ b/sim/testsuite/frv/stbfu.cgs @@ -0,0 +1,19 @@ +# frv testcase for stbfu $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbfu +stbfu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + stbfu fr8,@(sp,gr7) + test_mem_limmed 0xffad,0xbeef,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/frv/stbi.cgs b/sim/testsuite/frv/stbi.cgs new file mode 100644 index 0000000..f23efc9 --- /dev/null +++ b/sim/testsuite/frv/stbi.cgs @@ -0,0 +1,24 @@ +# frv testcase for stbi $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbi +stbi: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xffff,0xffff,gr8 + stbi gr8,@(sp,0) + test_mem_limmed 0xffad,0xbeef,sp + + inc_gr_immed 0x801,sp ; 2049 + stbi gr8,@(sp,-2048) + test_mem_limmed 0xffff,0xbeef,gr20 + + inc_gr_immed -4094,sp + stbi gr8,@(sp,0x7ff) + test_mem_limmed 0xffff,0xffef,gr20 + + pass diff --git a/sim/testsuite/frv/stbu.cgs b/sim/testsuite/frv/stbu.cgs new file mode 100644 index 0000000..e56ad11 --- /dev/null +++ b/sim/testsuite/frv/stbu.cgs @@ -0,0 +1,19 @@ +# frv testcase for stbu $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbu +stbu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + stbu gr8,@(sp,gr7) + test_mem_limmed 0xffad,0xbeef,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/frv/stc.cgs b/sim/testsuite/frv/stc.cgs new file mode 100644 index 0000000..581297c --- /dev/null +++ b/sim/testsuite/frv/stc.cgs @@ -0,0 +1,17 @@ +# frv testcase for stc $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stc +stc: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xffff,0xffff,cpr8 + stc cpr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + + pass diff --git a/sim/testsuite/frv/stcu.cgs b/sim/testsuite/frv/stcu.cgs new file mode 100644 index 0000000..eb9e6c5 --- /dev/null +++ b/sim/testsuite/frv/stcu.cgs @@ -0,0 +1,33 @@ +# frv testcase for stcu $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stcu +stcu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xffff,0xffff,cpr8 + stcu cpr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + test_gr_gr sp,gr20 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_cpr_limmed 0x1234,0x5678,cpr8 + stcu cpr8,@(sp,gr7) + test_mem_limmed 0x1234,0x5678,sp + test_gr_gr sp,gr20 + + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + set_cpr_limmed 0x9abc,0xdef0,cpr8 + stcu cpr8,@(sp,gr7) + test_mem_limmed 0x9abc,0xdef0,sp + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/frv/std.cgs b/sim/testsuite/frv/std.cgs new file mode 100644 index 0000000..8a2ed12 --- /dev/null +++ b/sim/testsuite/frv/std.cgs @@ -0,0 +1,32 @@ +# frv testcase for std $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + std gr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr3 ; sp is gr1 + set_gr_limmed 0xbeef,0xdead,gr0 + set_gr_limmed 0xdead,0xbeef,gr1 + std gr0,@(gr3,gr7) + test_mem_immed 0,gr3 + inc_gr_immed 4,gr3 + test_mem_immed 0,gr3 + + pass diff --git a/sim/testsuite/frv/std.pcgs b/sim/testsuite/frv/std.pcgs new file mode 100644 index 0000000..d518b8b --- /dev/null +++ b/sim/testsuite/frv/std.pcgs @@ -0,0 +1,37 @@ +# frv parallel testcase for std $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + std gr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + std.p gr8,@(sp,gr0) ; parallel + setlos 0,gr8 + ld @(sp,gr0),gr10 + ld @(sp,gr7),gr11 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + test_gr_immed 0xbeefdead,gr10 ; regs were pre-loaded + test_gr_immed 0xdeadbeef,gr11 ; not this one + + pass diff --git a/sim/testsuite/frv/stdc.cgs b/sim/testsuite/frv/stdc.cgs new file mode 100644 index 0000000..bdff0ac --- /dev/null +++ b/sim/testsuite/frv/stdc.cgs @@ -0,0 +1,21 @@ +# frv testcase for stdc $CPk,@($GRi,$GRj) +# mach: frv + + .include "testutils.inc" + + start + + .global stdc +stdc: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + stdc cpr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/stdc.pcgs b/sim/testsuite/frv/stdc.pcgs new file mode 100644 index 0000000..46c4925 --- /dev/null +++ b/sim/testsuite/frv/stdc.pcgs @@ -0,0 +1,38 @@ +# frv parallel testcase for stdc $CPk,@($GRi,$GRj) +# mach: frv + + .include "testutils.inc" + + start + + .global stdc +stdc: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + stdc cpr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 4,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + stdc.p cpr8,@(sp,gr0) ; parallel + addi sp,4,sp + subi sp,4,sp + ldc @(sp,gr0),cpr10 + ldc @(sp,gr7),cpr11 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + + pass diff --git a/sim/testsuite/frv/stdcu.cgs b/sim/testsuite/frv/stdcu.cgs new file mode 100644 index 0000000..bbae5ff --- /dev/null +++ b/sim/testsuite/frv/stdcu.cgs @@ -0,0 +1,44 @@ +# frv testcase for stdcu $CPk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stdcu +stdcu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + stdcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed -12,sp + set_gr_immed 8,gr7 + set_cpr_limmed 0x1234,0x5678,cpr8 + set_cpr_limmed 0x9abc,0xdef0,cpr9 + stdcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0x1234,0x5678,sp + inc_gr_immed 4,sp + test_mem_limmed 0x9abc,0xdef0,sp + + inc_gr_immed 4,sp + set_gr_immed -8,gr7 + set_cpr_limmed 0xfedc,0xba98,cpr8 + set_cpr_limmed 0x7654,0x3210,cpr9 + stdcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xfedc,0xba98,sp + inc_gr_immed 4,sp + test_mem_limmed 0x7654,0x3210,sp + + pass diff --git a/sim/testsuite/frv/stdf.cgs b/sim/testsuite/frv/stdf.cgs new file mode 100644 index 0000000..82c1461 --- /dev/null +++ b/sim/testsuite/frv/stdf.cgs @@ -0,0 +1,21 @@ +# frv testcase for stdf $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdf +stdf: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + stdf fr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/stdf.pcgs b/sim/testsuite/frv/stdf.pcgs new file mode 100644 index 0000000..7ef991c --- /dev/null +++ b/sim/testsuite/frv/stdf.pcgs @@ -0,0 +1,37 @@ +# frv parallel testcase for stdf $GRk,@($GRi,$GRj) +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global stdf +stdf: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + stdf fr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + stdf.p fr8,@(sp,gr0) ; parallel + fnegs fr8,fr8 + ldf @(sp,gr0),fr10 + ldf @(sp,gr7),fr11 ; memory is set + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + test_fr_iimmed 0xbeefdead,fr10 ; regs were pre-loaded + test_fr_iimmed 0xdeadbeef,fr11 ; not this one + + pass diff --git a/sim/testsuite/frv/stdfi.cgs b/sim/testsuite/frv/stdfi.cgs new file mode 100644 index 0000000..fea9b51 --- /dev/null +++ b/sim/testsuite/frv/stdfi.cgs @@ -0,0 +1,56 @@ +# frv testcase for stdfi $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdfi +stdfi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr22 + inc_gr_immed -4,sp + set_mem_limmed 0x8765,0x4321,sp + set_gr_gr sp,gr23 + inc_gr_immed -4,sp + set_mem_limmed 0xfedc,0xba98,sp + set_gr_gr sp,gr24 + inc_gr_immed -4,sp + set_mem_limmed 0x89ab,0xcdef,sp + set_gr_gr sp,gr25 + set_fr_iimmed 0xffff,0xffff,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + + stdfi fr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x8765,0x4321,gr23 + test_mem_limmed 0x1234,0x5678,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x808,sp ; 2056 + stdfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xffff,0xffff,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4080,sp + stdfi fr8,@(sp,0x7f8) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xffff,0xffff,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xffff,gr20 + + pass diff --git a/sim/testsuite/frv/stdfu.cgs b/sim/testsuite/frv/stdfu.cgs new file mode 100644 index 0000000..439cfa0 --- /dev/null +++ b/sim/testsuite/frv/stdfu.cgs @@ -0,0 +1,24 @@ +# frv testcase for stdfu $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdfu +stdfu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + stdfu fr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/stdi.cgs b/sim/testsuite/frv/stdi.cgs new file mode 100644 index 0000000..e1a783d --- /dev/null +++ b/sim/testsuite/frv/stdi.cgs @@ -0,0 +1,56 @@ +# frv testcase for stdi $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdi +stdi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr22 + inc_gr_immed -4,sp + set_mem_limmed 0x8765,0x4321,sp + set_gr_gr sp,gr23 + inc_gr_immed -4,sp + set_mem_limmed 0xfedc,0xba98,sp + set_gr_gr sp,gr24 + inc_gr_immed -4,sp + set_mem_limmed 0x89ab,0xcdef,sp + set_gr_gr sp,gr25 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + + stdi gr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x8765,0x4321,gr23 + test_mem_limmed 0x1234,0x5678,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x808,sp ; 2056 + stdi gr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xffff,0xffff,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4080,sp + stdi gr8,@(sp,0x7f8) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xffff,0xffff,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xffff,gr20 + + pass diff --git a/sim/testsuite/frv/stdu.cgs b/sim/testsuite/frv/stdu.cgs new file mode 100644 index 0000000..b5f122f --- /dev/null +++ b/sim/testsuite/frv/stdu.cgs @@ -0,0 +1,24 @@ +# frv testcase for stdu $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdu +stdu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + stdu gr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/stf.cgs b/sim/testsuite/frv/stf.cgs new file mode 100644 index 0000000..5ebc060 --- /dev/null +++ b/sim/testsuite/frv/stf.cgs @@ -0,0 +1,16 @@ +# frv testcase for stf $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stf +stf: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + stf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + + pass diff --git a/sim/testsuite/frv/stfi.cgs b/sim/testsuite/frv/stfi.cgs new file mode 100644 index 0000000..cfce1fd --- /dev/null +++ b/sim/testsuite/frv/stfi.cgs @@ -0,0 +1,37 @@ +# frv testcase for stfi $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stfi +stfi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr22 + set_fr_iimmed 0xffff,0xffff,fr8 + + stfi fr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x804,sp ; 2052 + stfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4088,sp + stfi fr8,@(sp,0x7fc) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xffff,gr20 + + pass diff --git a/sim/testsuite/frv/stfu.cgs b/sim/testsuite/frv/stfu.cgs new file mode 100644 index 0000000..e47e61d --- /dev/null +++ b/sim/testsuite/frv/stfu.cgs @@ -0,0 +1,19 @@ +# frv testcase for stfu $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stfu +stfu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + stfu fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/frv/sth.cgs b/sim/testsuite/frv/sth.cgs new file mode 100644 index 0000000..c11ae40 --- /dev/null +++ b/sim/testsuite/frv/sth.cgs @@ -0,0 +1,16 @@ +# frv testcase for sth $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + sth gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/sthf.cgs b/sim/testsuite/frv/sthf.cgs new file mode 100644 index 0000000..7310e4e --- /dev/null +++ b/sim/testsuite/frv/sthf.cgs @@ -0,0 +1,16 @@ +# frv testcase for sthf $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthf +sthf: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + sthf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/sthfi.cgs b/sim/testsuite/frv/sthfi.cgs new file mode 100644 index 0000000..ae9da97 --- /dev/null +++ b/sim/testsuite/frv/sthfi.cgs @@ -0,0 +1,31 @@ +# frv testcase for sthfi $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthfi +sthfi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + + sthfi fr8,@(sp,0) + test_mem_limmed 0xffff,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x802,sp ; 2050 + sthfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4092,sp + sthfi fr8,@(sp,0x7fe) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xbeef,gr20 + + pass diff --git a/sim/testsuite/frv/sthfu.cgs b/sim/testsuite/frv/sthfu.cgs new file mode 100644 index 0000000..df472e7 --- /dev/null +++ b/sim/testsuite/frv/sthfu.cgs @@ -0,0 +1,19 @@ +# frv testcase for sthfu $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthfu +sthfu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + sthfu fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xbeef,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/frv/sthi.cgs b/sim/testsuite/frv/sthi.cgs new file mode 100644 index 0000000..93636e9 --- /dev/null +++ b/sim/testsuite/frv/sthi.cgs @@ -0,0 +1,31 @@ +# frv testcase for sthi $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthi +sthi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + set_gr_limmed 0xffff,0xffff,gr8 + + sthi gr8,@(sp,0) + test_mem_limmed 0xffff,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x802,sp ; 2050 + sthi gr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4092,sp + sthi gr8,@(sp,0x7fe) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xbeef,gr20 + + pass diff --git a/sim/testsuite/frv/sthu.cgs b/sim/testsuite/frv/sthu.cgs new file mode 100644 index 0000000..ab35b30 --- /dev/null +++ b/sim/testsuite/frv/sthu.cgs @@ -0,0 +1,19 @@ +# frv testcase for sthu $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthu +sthu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + sthu gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xbeef,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/frv/sti.cgs b/sim/testsuite/frv/sti.cgs new file mode 100644 index 0000000..ce05003 --- /dev/null +++ b/sim/testsuite/frv/sti.cgs @@ -0,0 +1,37 @@ +# frv testcase for sti $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sti +sti: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr22 + set_gr_limmed 0xffff,0xffff,gr8 + + sti gr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x804,sp ; 2052 + sti gr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4088,sp + sti gr8,@(sp,0x7fc) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xffff,gr20 + + pass diff --git a/sim/testsuite/frv/stq.cgs b/sim/testsuite/frv/stq.cgs new file mode 100644 index 0000000..5ec8369 --- /dev/null +++ b/sim/testsuite/frv/stq.cgs @@ -0,0 +1,53 @@ +# frv testcase for stq $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stq +stq: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + stq gr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr4 ; sp is gr1 + set_gr_limmed 0xbeef,0xdead,gr0 + set_gr_limmed 0xdead,0xbeef,gr1 + set_gr_limmed 0xdead,0xdead,gr2 + set_gr_limmed 0xbeef,0xbeef,gr3 + stq gr0,@(gr4,gr7) + test_mem_immed 0,gr4 + inc_gr_immed 4,gr4 + test_mem_immed 0,gr4 + inc_gr_immed 4,gr4 + test_mem_immed 0,gr4 + inc_gr_immed 4,gr4 + test_mem_immed 0,gr4 + + pass diff --git a/sim/testsuite/frv/stq.pcgs b/sim/testsuite/frv/stq.pcgs new file mode 100644 index 0000000..268dd9e --- /dev/null +++ b/sim/testsuite/frv/stq.pcgs @@ -0,0 +1,59 @@ +# frv parallel testcase for stq $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stq +stq: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + stq gr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + stq.p gr8,@(sp,gr7) ; parallel + setlos 0,gr8 + ldq @(sp,gr7),gr12 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + test_gr_immed 0xbeefdead,gr12 + test_gr_immed 0xdeadbeef,gr13 + test_gr_immed 0xdeaddead,gr14 + test_gr_immed 0xbeefbeef,gr15 + + pass diff --git a/sim/testsuite/frv/stqc.cgs b/sim/testsuite/frv/stqc.cgs new file mode 100644 index 0000000..19fc79d --- /dev/null +++ b/sim/testsuite/frv/stqc.cgs @@ -0,0 +1,32 @@ +# frv testcase for stqc $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqc +stqc: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + set_cpr_limmed 0xdead,0xdead,cpr10 + set_cpr_limmed 0xbeef,0xbeef,cpr11 + stqc cpr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/stqc.pcgs b/sim/testsuite/frv/stqc.pcgs new file mode 100644 index 0000000..bda68ba --- /dev/null +++ b/sim/testsuite/frv/stqc.pcgs @@ -0,0 +1,60 @@ +# frv parallel testcase for stqc $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqc +stqc: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + set_cpr_limmed 0xdead,0xdead,cpr10 + set_cpr_limmed 0xbeef,0xbeef,cpr11 + stqc cpr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + set_cpr_limmed 0xdead,0xdead,cpr10 + set_cpr_limmed 0xbeef,0xbeef,cpr11 + stqc.p cpr8,@(sp,gr7) ; parallel + addi sp,4,sp + subi sp,4,sp + ldqc @(sp,gr7),cpr12 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + test_cpr_limmed 0xbeef,0xdead,cpr12 + test_cpr_limmed 0xdead,0xbeef,cpr13 + test_cpr_limmed 0xdead,0xdead,cpr14 + test_cpr_limmed 0xbeef,0xbeef,cpr15 + + pass diff --git a/sim/testsuite/frv/stqcu.cgs b/sim/testsuite/frv/stqcu.cgs new file mode 100644 index 0000000..a7746ca --- /dev/null +++ b/sim/testsuite/frv/stqcu.cgs @@ -0,0 +1,66 @@ +# frv testcase for stqcu $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqcu +stqcu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + set_cpr_limmed 0xdead,0xdead,cpr10 + set_cpr_limmed 0xbeef,0xbeef,cpr11 + stqcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + inc_gr_immed -28,sp + set_gr_immed 16,gr7 + set_cpr_limmed 0x1111,0x1111,cpr8 + set_cpr_limmed 0x2222,0x2222,cpr9 + set_cpr_limmed 0x3333,0x3333,cpr10 + set_cpr_limmed 0x4444,0x4444,cpr11 + stqcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0x1111,0x1111,sp + inc_gr_immed 4,sp + test_mem_limmed 0x2222,0x2222,sp + inc_gr_immed 4,sp + test_mem_limmed 0x3333,0x3333,sp + inc_gr_immed 4,sp + test_mem_limmed 0x4444,0x4444,sp + + inc_gr_immed 4,sp + set_gr_immed -16,gr7 + set_cpr_limmed 0x5555,0x5555,cpr8 + set_cpr_limmed 0x6666,0x6666,cpr9 + set_cpr_limmed 0x7777,0x7777,cpr10 + set_cpr_limmed 0x8888,0x8888,cpr11 + stqcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0x5555,0x5555,sp + inc_gr_immed 4,sp + test_mem_limmed 0x6666,0x6666,sp + inc_gr_immed 4,sp + test_mem_limmed 0x7777,0x7777,sp + inc_gr_immed 4,sp + test_mem_limmed 0x8888,0x8888,sp + + pass diff --git a/sim/testsuite/frv/stqf.cgs b/sim/testsuite/frv/stqf.cgs new file mode 100644 index 0000000..24dbb42 --- /dev/null +++ b/sim/testsuite/frv/stqf.cgs @@ -0,0 +1,32 @@ +# frv testcase for stqf $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqf +stqf: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + set_fr_iimmed 0xdead,0xdead,fr10 + set_fr_iimmed 0xbeef,0xbeef,fr11 + stqf fr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/stqf.pcgs b/sim/testsuite/frv/stqf.pcgs new file mode 100644 index 0000000..497f5fb --- /dev/null +++ b/sim/testsuite/frv/stqf.pcgs @@ -0,0 +1,59 @@ +# frv parallel testcase for stqf $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqf +stqf: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + set_fr_iimmed 0xdead,0xdead,fr10 + set_fr_iimmed 0xbeef,0xbeef,fr11 + stqf fr8,@(sp,gr7) ; non-parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + set_fr_iimmed 0xdead,0xdead,fr10 + set_fr_iimmed 0xbeef,0xbeef,fr11 + stqf.p fr8,@(sp,gr7) ; parallel + fnegs fr8,fr8 + ldqf @(sp,gr7),fr12 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + test_fr_iimmed 0xbeefdead,fr12 + test_fr_iimmed 0xdeadbeef,fr13 + test_fr_iimmed 0xdeaddead,fr14 + test_fr_iimmed 0xbeefbeef,fr15 + + pass diff --git a/sim/testsuite/frv/stqfi.cgs b/sim/testsuite/frv/stqfi.cgs new file mode 100644 index 0000000..6a36a90 --- /dev/null +++ b/sim/testsuite/frv/stqfi.cgs @@ -0,0 +1,95 @@ +# frv testcase for stqfi $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqfi +stqfi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr10 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr11 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr12 + inc_gr_immed -4,sp + set_mem_limmed 0x8765,0x4321,sp + set_gr_gr sp,gr13 + inc_gr_immed -4,sp + set_mem_limmed 0xfedc,0xba98,sp + set_gr_gr sp,gr14 + inc_gr_immed -4,sp + set_mem_limmed 0x89ab,0xcdef,sp + set_gr_gr sp,gr15 + inc_gr_immed -4,sp + set_mem_limmed 0x2345,0x6789,sp + set_gr_gr sp,gr16 + inc_gr_immed -4,sp + set_mem_limmed 0x9876,0x5432,sp + set_gr_gr sp,gr17 + inc_gr_immed -4,sp + set_mem_limmed 0x3456,0x789a,sp + set_gr_gr sp,gr18 + inc_gr_immed -4,sp + set_mem_limmed 0xa987,0x6543,sp + set_gr_gr sp,gr19 + inc_gr_immed -4,sp + set_mem_limmed 0x4567,0x89ab,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xba98,0x7654,sp + set_gr_gr sp,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + set_fr_iimmed 0xeeee,0xeeee,fr9 + set_fr_iimmed 0xdddd,0xdddd,fr10 + set_fr_iimmed 0xcccc,0xcccc,fr11 + + stqfi fr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0x9876,0x5432,gr17 + test_mem_limmed 0x2345,0x6789,gr16 + test_mem_limmed 0x89ab,0xcdef,gr15 + test_mem_limmed 0xfedc,0xba98,gr14 + test_mem_limmed 0x8765,0x4321,gr13 + test_mem_limmed 0x1234,0x5678,gr12 + test_mem_limmed 0xbeef,0xdead,gr11 + test_mem_limmed 0xdead,0xbeef,gr10 + + inc_gr_immed 0x810,sp ; 2064 + stqfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xffff,0xffff,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xdddd,0xdddd,gr15 + test_mem_limmed 0xcccc,0xcccc,gr14 + test_mem_limmed 0x8765,0x4321,gr13 + test_mem_limmed 0x1234,0x5678,gr12 + test_mem_limmed 0xbeef,0xdead,gr11 + test_mem_limmed 0xdead,0xbeef,gr10 + + inc_gr_immed -4064,sp + stqfi fr8,@(sp,0x7f0) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xffff,0xffff,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xdddd,0xdddd,gr15 + test_mem_limmed 0xcccc,0xcccc,gr14 + test_mem_limmed 0xffff,0xffff,gr13 + test_mem_limmed 0xeeee,0xeeee,gr12 + test_mem_limmed 0xdddd,0xdddd,gr11 + test_mem_limmed 0xcccc,0xcccc,gr10 + + pass diff --git a/sim/testsuite/frv/stqfu.cgs b/sim/testsuite/frv/stqfu.cgs new file mode 100644 index 0000000..80a1494 --- /dev/null +++ b/sim/testsuite/frv/stqfu.cgs @@ -0,0 +1,35 @@ +# frv testcase for stqfu $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqfu +stqfu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + set_fr_iimmed 0xdead,0xdead,fr10 + set_fr_iimmed 0xbeef,0xbeef,fr11 + stqfu fr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/stqi.cgs b/sim/testsuite/frv/stqi.cgs new file mode 100644 index 0000000..5a3680e --- /dev/null +++ b/sim/testsuite/frv/stqi.cgs @@ -0,0 +1,95 @@ +# frv testcase for stqi $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqi +stqi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr10 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr11 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr12 + inc_gr_immed -4,sp + set_mem_limmed 0x8765,0x4321,sp + set_gr_gr sp,gr13 + inc_gr_immed -4,sp + set_mem_limmed 0xfedc,0xba98,sp + set_gr_gr sp,gr14 + inc_gr_immed -4,sp + set_mem_limmed 0x89ab,0xcdef,sp + set_gr_gr sp,gr15 + inc_gr_immed -4,sp + set_mem_limmed 0x2345,0x6789,sp + set_gr_gr sp,gr16 + inc_gr_immed -4,sp + set_mem_limmed 0x9876,0x5432,sp + set_gr_gr sp,gr17 + inc_gr_immed -4,sp + set_mem_limmed 0x3456,0x789a,sp + set_gr_gr sp,gr18 + inc_gr_immed -4,sp + set_mem_limmed 0xa987,0x6543,sp + set_gr_gr sp,gr19 + inc_gr_immed -4,sp + set_mem_limmed 0x4567,0x89ab,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xba98,0x7654,sp + set_gr_gr sp,gr21 + set_gr_limmed 0xffff,0xffff,gr4 + set_gr_limmed 0xeeee,0xeeee,gr5 + set_gr_limmed 0xdddd,0xdddd,gr6 + set_gr_limmed 0xcccc,0xcccc,gr7 + + stqi gr4,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0x9876,0x5432,gr17 + test_mem_limmed 0x2345,0x6789,gr16 + test_mem_limmed 0x89ab,0xcdef,gr15 + test_mem_limmed 0xfedc,0xba98,gr14 + test_mem_limmed 0x8765,0x4321,gr13 + test_mem_limmed 0x1234,0x5678,gr12 + test_mem_limmed 0xbeef,0xdead,gr11 + test_mem_limmed 0xdead,0xbeef,gr10 + + inc_gr_immed 0x810,sp ; 2064 + stqi gr4,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xffff,0xffff,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xdddd,0xdddd,gr15 + test_mem_limmed 0xcccc,0xcccc,gr14 + test_mem_limmed 0x8765,0x4321,gr13 + test_mem_limmed 0x1234,0x5678,gr12 + test_mem_limmed 0xbeef,0xdead,gr11 + test_mem_limmed 0xdead,0xbeef,gr10 + + inc_gr_immed -4064,sp + stqi gr4,@(sp,0x7f0) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xffff,0xffff,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xdddd,0xdddd,gr15 + test_mem_limmed 0xcccc,0xcccc,gr14 + test_mem_limmed 0xffff,0xffff,gr13 + test_mem_limmed 0xeeee,0xeeee,gr12 + test_mem_limmed 0xdddd,0xdddd,gr11 + test_mem_limmed 0xcccc,0xcccc,gr10 + + pass diff --git a/sim/testsuite/frv/stqu.cgs b/sim/testsuite/frv/stqu.cgs new file mode 100644 index 0000000..31e8de5 --- /dev/null +++ b/sim/testsuite/frv/stqu.cgs @@ -0,0 +1,35 @@ +# frv testcase for stqu $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqu +stqu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + stqu gr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + pass diff --git a/sim/testsuite/frv/stu.cgs b/sim/testsuite/frv/stu.cgs new file mode 100644 index 0000000..cc48040 --- /dev/null +++ b/sim/testsuite/frv/stu.cgs @@ -0,0 +1,19 @@ +# frv testcase for stu $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stu +stu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + stu gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/frv/sub.cgs b/sim/testsuite/frv/sub.cgs new file mode 100644 index 0000000..5a1410c --- /dev/null +++ b/sim/testsuite/frv/sub.cgs @@ -0,0 +1,26 @@ +# frv testcase for sub $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sub +sub: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + sub gr8,gr7,gr8 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + sub gr8,gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + + sub gr8,gr8,gr8 + test_gr_immed 0,gr8 + + sub gr8,gr7,gr8 + test_gr_immed -1,gr8 + + pass diff --git a/sim/testsuite/frv/subcc.cgs b/sim/testsuite/frv/subcc.cgs new file mode 100644 index 0000000..188e0ff --- /dev/null +++ b/sim/testsuite/frv/subcc.cgs @@ -0,0 +1,34 @@ +# frv testcase for subcc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global subcc +subcc: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + subcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + subcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0b,0 ; Set mask opposite of expected + subcc gr8,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + subcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + pass diff --git a/sim/testsuite/frv/subi.cgs b/sim/testsuite/frv/subi.cgs new file mode 100644 index 0000000..c632838 --- /dev/null +++ b/sim/testsuite/frv/subi.cgs @@ -0,0 +1,56 @@ +# frv testcase for subi $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global subi +subi: + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + subi gr8,1,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + subi gr8,1,gr8 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x7ff,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + subi gr8,0x7ff,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + subi gr8,1,gr8 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + subi gr8,-1,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + subi gr8,-1,gr8 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0x8000,0x0001,gr8 + + set_gr_immed -2048,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + subi gr8,-2048,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x0e,0 ; Set mask opposite of expected + subi gr8,-1,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 1,gr8 + + pass diff --git a/sim/testsuite/frv/subicc.cgs b/sim/testsuite/frv/subicc.cgs new file mode 100644 index 0000000..b2296ee --- /dev/null +++ b/sim/testsuite/frv/subicc.cgs @@ -0,0 +1,56 @@ +# frv testcase for subicc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global subicc +subicc: + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + subicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + subicc gr8,1,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x1ff,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + subicc gr8,0x1ff,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + subicc gr8,1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + subicc gr8,-1,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + subicc gr8,-1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x8000,0x0001,gr8 + + set_gr_immed -512,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + subicc gr8,-512,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x0e,0 ; Set mask opposite of expected + subicc gr8,-1,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + + pass diff --git a/sim/testsuite/frv/subx.cgs b/sim/testsuite/frv/subx.cgs new file mode 100644 index 0000000..4559a52 --- /dev/null +++ b/sim/testsuite/frv/subx.cgs @@ -0,0 +1,60 @@ +# frv testcase for subx $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global subx +subx: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry is off + subx gr8,gr7,gr8,icc0 + test_icc 1 1 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0c,0 ; Make sure carry is off + subx gr8,gr7,gr8,icc0 + test_icc 1 1 0 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0a,0 ; Make sure carry is off + subx gr8,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Make sure carry is off + subx gr8,gr7,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 3,gr8 + set_icc 0x0f,0 ; Make sure carry is on + subx gr8,gr7,gr8,icc0 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 0,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Make sure carry is on + subx gr8,gr7,gr8,icc0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0x7fff,0xfffe,gr7 + set_icc 0x0b,0 ; Make sure carry is on + subx gr8,gr7,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 0,gr7 + set_icc 0x07,0 ; Make sure carry is on + subx gr8,gr7,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + pass diff --git a/sim/testsuite/frv/subxcc.cgs b/sim/testsuite/frv/subxcc.cgs new file mode 100644 index 0000000..713a2a7 --- /dev/null +++ b/sim/testsuite/frv/subxcc.cgs @@ -0,0 +1,60 @@ +# frv testcase for subxcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global subxcc +subxcc: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry is off + subxcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0c,0 ; Make sure carry is off + subxcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0a,0 ; Make sure carry is off + subxcc gr8,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Make sure carry is off + subxcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 3,gr8 + set_icc 0x0f,0 ; Make sure carry is on + subxcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 0,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Make sure carry is on + subxcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0x7fff,0xfffe,gr7 + set_icc 0x0b,0 ; Make sure carry is on + subxcc gr8,gr7,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 0,gr7 + set_icc 0x07,0 ; Make sure carry is on + subxcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + pass diff --git a/sim/testsuite/frv/subxi.cgs b/sim/testsuite/frv/subxi.cgs new file mode 100644 index 0000000..bbe8e4d --- /dev/null +++ b/sim/testsuite/frv/subxi.cgs @@ -0,0 +1,61 @@ +# frv testcase for subxi $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global subxi +subxi: + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry is off + subxi gr8,1,gr8,icc0 + test_icc 1 1 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0c,0 ; Make sure carry is off + subxi gr8,1,gr8,icc0 + test_icc 1 1 0 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x1ff,gr8 + set_icc 0x0a,0 ; Make sure carry is off + subxi gr8,0x1ff,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Make sure carry is off + subxi gr8,1,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 3,gr8 + set_icc 0x0f,0 ; Make sure carry is on + subxi gr8,1,gr8,icc0 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Make sure carry is on + subxi gr8,0,gr8,icc0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x200,gr8 + set_icc 0x0b,0 ; Make sure carry is on + subxi gr8,0x1ff,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x07,0 ; Make sure carry is on + subxi gr8,0,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_icc 0x07,0 ; Make sure carry is on + subxi gr8,-512,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 510,gr8 + + pass diff --git a/sim/testsuite/frv/subxicc.cgs b/sim/testsuite/frv/subxicc.cgs new file mode 100644 index 0000000..369cab9 --- /dev/null +++ b/sim/testsuite/frv/subxicc.cgs @@ -0,0 +1,61 @@ +# frv testcase for subxicc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global subxicc +subxicc: + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry is off + subxicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0c,0 ; Make sure carry is off + subxicc gr8,1,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x1ff,gr8 + set_icc 0x0a,0 ; Make sure carry is off + subxicc gr8,0x1ff,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Make sure carry is off + subxicc gr8,1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 3,gr8 + set_icc 0x0f,0 ; Make sure carry is on + subxicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Make sure carry is on + subxicc gr8,0,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x200,gr8 + set_icc 0x0b,0 ; Make sure carry is on + subxicc gr8,0x1ff,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x07,0 ; Make sure carry is on + subxicc gr8,0,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_icc 0x07,0 ; Make sure carry is on + subxicc gr8,-512,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 510,gr8 + + pass diff --git a/sim/testsuite/frv/swap.cgs b/sim/testsuite/frv/swap.cgs new file mode 100644 index 0000000..1e22903 --- /dev/null +++ b/sim/testsuite/frv/swap.cgs @@ -0,0 +1,42 @@ +# frv testcase for swap @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global swap +swap: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + swap @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 0,gr7 + swap @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + swap @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xbeef,0xdead,gr20 + + pass diff --git a/sim/testsuite/frv/swapi.cgs b/sim/testsuite/frv/swapi.cgs new file mode 100644 index 0000000..4951bfa --- /dev/null +++ b/sim/testsuite/frv/swapi.cgs @@ -0,0 +1,39 @@ +# frv testcase for swapi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global swapi +swapi: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + swapi @(sp,-4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + swapi @(sp,0),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + swapi @(sp,4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xbeef,0xdead,gr20 + + pass diff --git a/sim/testsuite/frv/tc.cgs b/sim/testsuite/frv/tc.cgs new file mode 100644 index 0000000..116190b --- /dev/null +++ b/sim/testsuite/frv/tc.cgs @@ -0,0 +1,101 @@ +# frv testcase for tc $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tc +tc: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/teq.cgs b/sim/testsuite/frv/teq.cgs new file mode 100644 index 0000000..59c6091 --- /dev/null +++ b/sim/testsuite/frv/teq.cgs @@ -0,0 +1,101 @@ +# frv testcase for teq $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global teq +teq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x2 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xa 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/testutils.inc b/sim/testsuite/frv/testutils.inc new file mode 100644 index 0000000..8261b4fa --- /dev/null +++ b/sim/testsuite/frv/testutils.inc @@ -0,0 +1,656 @@ +# gr28-gr31, fr31, icc3, fcc3 are used as tmps. +# consider them call clobbered by these macros. + + .macro start + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + .global _start +_start: + ; enable data and insn caches in copy-back mode + ; Also enable all registers + or_spr_immed 0xc80003c0,hsr0 + and_spr_immed 0xfffff3ff,hsr0 + + ; turn on psr.nem, psr.cm, psr.ef, psr.em, psr.esr, + ; disable external interrupts + or_spr_immed 0x69f8,psr + + ; If fsr exists, enable all fp_exceptions except inexact + movsg psr,gr28 + srli gr28,28,gr28 + subicc gr28,0x2,gr0,icc3 ; is fr400? + beq icc3,0,nofsr0 + or_spr_immed 0x3d000000,fsr0 +nofsr0: + + ; Set the stack pointer + sethi.p 0x7,sp + setlo 0xfffc,sp ; TODO -- what's a good value for this? + + ; Set the TBR address + sethi.p 0xf,gr28 + setlo 0xf000,gr28 + movgs gr28,tbr ; TODO -- what's a good value for this? + + ; Go to user mode -- causes too many problems + ;and_spr_immed 0xfffffffb,psr + .endm + +; Set GR with another GR + .macro set_gr_gr src targ + addi \src,0,\targ + .endm + +; Set GR with immediate value + .macro set_gr_immed val reg + .if (\val >= -32768) && (\val <= 23767) + setlos \val,\reg + .else + setlo.p %lo(\val),\reg + sethi %hi(\val),\reg + .endif + .endm + + .macro set_gr_limmed valh vall reg + sethi.p \valh,\reg + setlo \vall,\reg + .endm + +; Set GR with address value + .macro set_gr_addr addr reg + sethi.p %hi(\addr),\reg + setlo %lo(\addr),\reg + .endm + +; Set GR with SPR + .macro set_gr_spr src targ + movsg \src,\targ + .endm + +; Set GR with a value from memory + .macro set_gr_mem addr reg + set_gr_addr \addr,gr28 + ldi @(gr28,0),\reg + .endm + +; Increment GR with immediate value + .macro inc_gr_immed val reg + .if (\val >= -2048) && (\val <= 2047) + addi \reg,\val,\reg + .else + set_gr_immed \val,gr28 + add \reg,gr28,\reg + .endif + .endm + +; AND GR with immediate value + .macro and_gr_immed val reg + .if (\val >= -2048) && (\val <= 2047) + andi \reg,\val,\reg + .else + set_gr_immed \val,gr28 + and \reg,gr28,\reg + .endif + .endm + +; OR GR with immediate value + .macro or_gr_immed val reg + .if (\val >= -2048) && (\val <= 2047) + ori \reg,\val,\reg + .else + set_gr_immed \val,gr28 + or \reg,gr28,\reg + .endif + .endm + +; Set FR with another FR + .macro set_fr_fr src targ + fmovs \src,\targ + .endm + +; Set FR with integer immediate value + .macro set_fr_iimmed valh vall reg + set_gr_limmed \valh,\vall,gr28 + movgf gr28,\reg + .endm + +; Set FR with integer immediate value + .macro set_fr_immed val reg + set_gr_immed \val,gr28 + movgf gr28,\reg + .endm + +; Set FR with a value from memory + .macro set_fr_mem addr reg + set_gr_addr \addr,gr28 + ldfi @(gr28,0),\reg + .endm + +; Set double FR with another double FR + .macro set_dfr_dfr src targ + fmovd \src,\targ + .endm + +; Set double FR with a value from memory + .macro set_dfr_mem addr reg + set_gr_addr \addr,gr28 + lddfi @(gr28,0),\reg + .endm + +; Set CPR with immediate value + .macro set_cpr_immed val reg + addi sp,-4,gr28 + set_gr_immed \val,gr29 + st gr29,@(gr28,gr0) + ldc @(gr28,gr0),\reg + .endm + + .macro set_cpr_limmed valh vall reg + addi sp,-4,gr28 + set_gr_limmed \valh,\vall,gr29 + st gr29,@(gr28,gr0) + ldc @(gr28,gr0),\reg + .endm + +; Set SPR with immediate value + .macro set_spr_immed val reg + set_gr_immed \val,gr28 + movgs gr28,\reg + .endm + + .macro set_spr_limmed valh vall reg + set_gr_limmed \valh,\vall,gr28 + movgs gr28,\reg + .endm + + .macro set_spr_addr addr reg + set_gr_addr \addr,gr28 + movgs gr28,\reg + .endm + +; increment SPR with immediate value + .macro inc_spr_immed val reg + movsg \reg,gr28 + inc_gr_immed \val,gr28 + movgs gr28,\reg + .endm + +; OR spr with immediate value + .macro or_spr_immed val reg + movsg \reg,gr28 + set_gr_immed \val,gr29 + or gr28,gr29,gr28 + movgs gr28,\reg + .endm + +; AND spr with immediate value + .macro and_spr_immed val reg + movsg \reg,gr28 + set_gr_immed \val,gr29 + and gr28,gr29,gr28 + movgs gr28,\reg + .endm + +; Set accumulator with immediate value + .macro set_acc_immed val reg + set_fr_immed \val,fr31 + mwtacc fr31,\reg + .endm + +; Set accumulator guard with immediate value + .macro set_accg_immed val reg + set_fr_immed \val,fr31 + mwtaccg fr31,\reg + .endm + +; Set memory with immediate value + .macro set_mem_immed val base + set_gr_immed \val,gr28 + sti gr28,@(\base,0) + .endm + + .macro set_mem_limmed valh vall base + set_gr_limmed \valh,\vall,gr28 + sti gr28,@(\base,0) + .endm + +; Set memory with GR value + .macro set_mem_gr reg addr + set_gr_addr \addr,gr28 + sti \reg,@(gr28,0) + .endm + +; Test the value of a general register against another general register + .macro test_gr_gr reg1 reg2 + subcc \reg1,\reg2,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of an immediate against a general register + .macro test_gr_immed val reg + .if (\val >= -512) && (\val <= 511) + subicc \reg,\val,gr0,icc3 + .else + set_gr_immed \val,gr28 + subcc \reg,gr28,gr0,icc3 + .endif + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_gr_limmed valh vall reg + set_gr_limmed \valh,\vall,gr28 + subcc \reg,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of an floating register against an integer immediate + .macro test_fr_limmed valh vall reg + movfg \reg,gr29 + set_gr_limmed \valh,\vall,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_fr_iimmed val reg + movfg \reg,gr29 + set_gr_immed \val,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of a floating register against another floating point register + .macro test_fr_fr reg1 reg2 + fcmps \reg1,\reg2,fcc3 + fbeq fcc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of a double floating register against another +; double floating point register + .macro test_dfr_dfr reg1 reg2 + fcmpd \reg1,\reg2,fcc3 + fbeq fcc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of a special purpose register against an integer immediate + .macro test_spr_immed val reg + movsg \reg,gr29 + set_gr_immed \val,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_spr_limmed valh vall reg + movsg \reg,gr29 + set_gr_limmed \valh,\vall,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_spr_gr spr gr + movsg \spr,gr28 + test_gr_gr \gr,gr28 + .endm + + .macro test_spr_addr addr reg + movsg \reg,gr29 + set_gr_addr \addr,gr28 + test_gr_gr gr28,gr29 + .endm + +; Test spr bits masked and shifted against the given value + .macro test_spr_bits mask,shift,val,reg + movsg \reg,gr28 + set_gr_immed \mask,gr29 + and gr28,gr29,gr28 + srli gr28,\shift,gr29 + test_gr_immed \val,gr29 + .endm + + +; Test the value of an accumulator against an integer immediate + .macro test_acc_immed val reg + mrdacc \reg,fr31 + test_fr_iimmed \val,fr31 + .endm + +; Test the value of an accumulator against an integer immediate + .macro test_acc_limmed valh vall reg + mrdacc \reg,fr31 + test_fr_limmed \valh,\vall,fr31 + .endm + +; Test the value of an accumulator guard against an integer immediate + .macro test_accg_immed val reg + mrdaccg \reg,fr31 + test_fr_iimmed \val,fr31 + .endm + +; Test CPR agains an immediate value + .macro test_cpr_limmed valh vall reg + addi sp,-4,gr31 + stc \reg,@(gr31,gr0) + test_mem_limmed \valh,\vall,gr31 + .endm + +; Test the value of an immediate against memory + .macro test_mem_immed val base + ldi @(\base,0),gr29 + .if (\val >= -512) && (\val <= 511) + subicc gr29,\val,gr0,icc3 + .else + set_gr_immed \val,gr28 + subcc gr29,gr28,gr0,icc3 + .endif + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_mem_limmed valh vall base + ldi @(\base,0),gr29 + set_gr_limmed \valh,\vall,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Set an integer condition code + .macro set_icc mask iccno + set_gr_immed 4,gr29 + smuli gr29,\iccno,gr30 + addi gr31,16,gr31 + set_gr_immed 0xf,gr28 + sll gr28,gr31,gr28 + not gr28,gr28 + movsg ccr,gr29 + and gr28,gr29,gr29 + set_gr_immed \mask,gr28 + sll gr28,gr31,gr28 + or gr28,gr29,gr29 + movgs gr29,ccr + .endm +; started here +; Test the condition codes + .macro test_icc N Z V C iccno + .if (\N == 1) + bp \iccno,0,fail\@ + .else + bn \iccno,0,fail\@ + .endif + .if (\Z == 1) + bne \iccno,0,fail\@ + .else + beq \iccno,0,fail\@ + .endif + .if (\V == 1) + bnv \iccno,0,fail\@ + .else + bv \iccno,0,fail\@ + .endif + .if (\C == 1) + bnc \iccno,0,fail\@ + .else + bc \iccno,0,fail\@ + .endif + bra test_cc\@ +fail\@: + fail +test_cc\@: + .endm + +; Set an floating point condition code + .macro set_fcc mask fccno + set_gr_immed 4,gr29 + smuli gr29,\fccno,gr30 + set_gr_immed 0xf,gr28 + sll gr28,gr31,gr28 + not gr28,gr28 + movsg ccr,gr29 + and gr28,gr29,gr29 + set_gr_immed \mask,gr28 + sll gr28,gr31,gr28 + or gr28,gr29,gr29 + movgs gr29,ccr + .endm + +; Test the condition codes + .macro test_fcc val fccno + set_gr_immed 4,gr29 + smuli gr29,\fccno,gr30 + movsg ccr,gr29 + srl gr29,gr31,gr29 + andi gr29,0xf,gr29 + test_gr_immed \val,gr29 + .endm + +; Set PSR.ET + .macro set_psr_et val + movsg psr,gr28 + .if (\val == 1) + ori gr28,1,gr28 ; Turn on SPR.ET + .else + andi gr28,0xfffffffe,gr28 ; Turn off SPR.ET + .endif + movgs gr28,psr + .endm + +; Floating point constants + .macro float_constants +f0: .float 0.0 +f1: .float 1.0 +f2: .float 2.0 +f3: .float 3.0 +f6: .float 6.0 +f9: .float 9.0 +fn0: .float -0.0 +fn1: .float -1.0 +finf: .long 0x7f800000 +fninf: .long 0xff800000 +fmax: .long 0x7f7fffff +fmin: .long 0xff7fffff +feps: .long 0x00400000 +fneps: .long 0x80400000 +fnan1: .long 0x7fc00000 +fnan2: .long 0x7f800001 + .endm + + .macro double_constants +d0: .double 0.0 +d1: .double 1.0 +d2: .double 2.0 +d3: .double 3.0 +d6: .double 6.0 +d9: .double 9.0 +dn0: .double -0.0 +dn1: .double -1.0 +dinf: .long 0x7ff00000 + .long 0x00000000 +dninf: .long 0xfff00000 + .long 0x00000000 +dmax: .long 0x7fefffff + .long 0xffffffff +dmin: .long 0xffefffff + .long 0xffffffff +deps: .long 0x00080000 + .long 0x00000000 +dneps: .long 0x80080000 + .long 0x00000000 +dnan1: .long 0x7ff80000 + .long 0x00000000 +dnan2: .long 0x7ff00000 + .long 0x00000001 + .endm + +; Load floating point constants + .macro load_float_constants + set_fr_mem fninf,fr0 + set_fr_mem fmin,fr4 + set_fr_mem fn1,fr8 + set_fr_mem fneps,fr12 + set_fr_mem fn0,fr16 + set_fr_mem f0,fr20 + set_fr_mem feps,fr24 + set_fr_mem f1,fr28 + set_fr_mem f2,fr32 + set_fr_mem f3,fr36 + set_fr_mem f6,fr40 + set_fr_mem f9,fr44 + set_fr_mem fmax,fr48 + set_fr_mem finf,fr52 + set_fr_mem fnan1,fr56 + set_fr_mem fnan2,fr60 + .endm + + .macro load_float_constants1 + set_fr_mem fninf,fr1 + set_fr_mem fmin,fr5 + set_fr_mem fn1,fr9 + set_fr_mem fneps,fr13 + set_fr_mem fn0,fr17 + set_fr_mem f0,fr21 + set_fr_mem feps,fr25 + set_fr_mem f1,fr29 + set_fr_mem f2,fr33 + set_fr_mem f3,fr37 + set_fr_mem f6,fr41 + set_fr_mem f9,fr45 + set_fr_mem fmax,fr49 + set_fr_mem finf,fr53 + set_fr_mem fnan1,fr57 + set_fr_mem fnan2,fr61 + .endm + + .macro load_float_constants2 + set_fr_mem fninf,fr2 + set_fr_mem fmin,fr6 + set_fr_mem fn1,fr10 + set_fr_mem fneps,fr14 + set_fr_mem fn0,fr18 + set_fr_mem f0,fr22 + set_fr_mem feps,fr26 + set_fr_mem f1,fr30 + set_fr_mem f2,fr34 + set_fr_mem f3,fr38 + set_fr_mem f6,fr42 + set_fr_mem f9,fr46 + set_fr_mem fmax,fr50 + set_fr_mem finf,fr54 + set_fr_mem fnan1,fr58 + set_fr_mem fnan2,fr62 + .endm + + .macro load_float_constants3 + set_fr_mem fninf,fr3 + set_fr_mem fmin,fr7 + set_fr_mem fn1,fr11 + set_fr_mem fneps,fr15 + set_fr_mem fn0,fr19 + set_fr_mem f0,fr23 + set_fr_mem feps,fr27 + set_fr_mem f1,fr31 + set_fr_mem f2,fr35 + set_fr_mem f3,fr39 + set_fr_mem f6,fr43 + set_fr_mem f9,fr47 + set_fr_mem fmax,fr51 + set_fr_mem finf,fr55 + set_fr_mem fnan1,fr59 + set_fr_mem fnan2,fr63 + .endm + + .macro load_double_constants + set_dfr_mem dninf,fr0 + set_dfr_mem dmin,fr4 + set_dfr_mem dn1,fr8 + set_dfr_mem dneps,fr12 + set_dfr_mem dn0,fr16 + set_dfr_mem d0,fr20 + set_dfr_mem deps,fr24 + set_dfr_mem d1,fr28 + set_dfr_mem d2,fr32 + set_dfr_mem d3,fr36 + set_dfr_mem d6,fr40 + set_dfr_mem d9,fr44 + set_dfr_mem dmax,fr48 + set_dfr_mem dinf,fr52 + set_dfr_mem dnan1,fr56 + set_dfr_mem dnan2,fr60 + .endm + +; Lock the insn cache at the given address + .macro lock_insn_cache address + icpl \address,gr0,1 + .endm + +; Lock the data cache at the given address + .macro lock_data_cache address + dcpl \address,gr0,1 + .endm + +; Invalidate the data cache at the given address + .macro invalidate_data_cache address + dci @(\address,gr0) + .endm + +; Flush the data cache at the given address + .macro flush_data_cache address + dcf @(\address,gr0) + .endm + +; Write a bctrlr 0,0 insn at the address contained in the given register + .macro set_bctrlr_0_0 address + set_mem_immed 0x80382000,\address ; bctrlr 0,0 + flush_data_cache \address + .endm + +; Exit with return code + .macro exit rc + setlos #1,gr7 + set_gr_immed \rc,gr8 + tira gr0,#0 + .endm + +; Pass the test case + .macro pass +pass\@: + setlos.p #5,gr10 + setlos #1,gr8 + setlos #5,gr7 + set_gr_addr passmsg,gr9 + tira gr0,#0 + exit #0 + .endm + +; Fail the testcase + .macro fail +fail\@: + setlos.p #5,gr10 + setlos #1,gr8 + setlos #5,gr7 + set_gr_addr failmsg,gr9 + tira gr0,#0 + exit #1 + .endm diff --git a/sim/testsuite/frv/tge.cgs b/sim/testsuite/frv/tge.cgs new file mode 100644 index 0000000..3e12d92 --- /dev/null +++ b/sim/testsuite/frv/tge.cgs @@ -0,0 +1,101 @@ +# frv testcase for tge $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tge +tge: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x8 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/tgt.cgs b/sim/testsuite/frv/tgt.cgs new file mode 100644 index 0000000..7e01330 --- /dev/null +++ b/sim/testsuite/frv/tgt.cgs @@ -0,0 +1,93 @@ +# frv testcase for tgt $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tgt +tgt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x8 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/thi.cgs b/sim/testsuite/frv/thi.cgs new file mode 100644 index 0000000..36cc923 --- /dev/null +++ b/sim/testsuite/frv/thi.cgs @@ -0,0 +1,93 @@ +# frv testcase for thi $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global thi +thi: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_spr_addr bad,lr + set_icc 0x1 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x3 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x9 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_spr_addr bad,lr + set_icc 0xb 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xc 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tic.cgs b/sim/testsuite/frv/tic.cgs new file mode 100644 index 0000000..8c746f5 --- /dev/null +++ b/sim/testsuite/frv/tic.cgs @@ -0,0 +1,100 @@ +# frv testcase for tic $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tic +tic: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/tieq.cgs b/sim/testsuite/frv/tieq.cgs new file mode 100644 index 0000000..5dfc0e6 --- /dev/null +++ b/sim/testsuite/frv/tieq.cgs @@ -0,0 +1,101 @@ +# frv testcase for tieq $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tieq +tieq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x2 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr bad,lr + set_icc 0x8 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xa 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/tige.cgs b/sim/testsuite/frv/tige.cgs new file mode 100644 index 0000000..cde3ac8 --- /dev/null +++ b/sim/testsuite/frv/tige.cgs @@ -0,0 +1,101 @@ +# frv testcase for tige $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tige +tige: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr bad,lr + set_icc 0x6 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x8 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/tigt.cgs b/sim/testsuite/frv/tigt.cgs new file mode 100644 index 0000000..163d92f --- /dev/null +++ b/sim/testsuite/frv/tigt.cgs @@ -0,0 +1,92 @@ +# frv testcase for tigt $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tigt +tigt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x8 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tihi.cgs b/sim/testsuite/frv/tihi.cgs new file mode 100644 index 0000000..e564fc2 --- /dev/null +++ b/sim/testsuite/frv/tihi.cgs @@ -0,0 +1,92 @@ +# frv testcase for tihi $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tihi +tihi: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_spr_addr bad,lr + set_icc 0x1 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x3 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x9 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_spr_addr bad,lr + set_icc 0xb 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xc 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tile.cgs b/sim/testsuite/frv/tile.cgs new file mode 100644 index 0000000..7f5ef2a --- /dev/null +++ b/sim/testsuite/frv/tile.cgs @@ -0,0 +1,108 @@ +# frv testcase for tile $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tile +tile: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/tils.cgs b/sim/testsuite/frv/tils.cgs new file mode 100644 index 0000000..5713de5 --- /dev/null +++ b/sim/testsuite/frv/tils.cgs @@ -0,0 +1,108 @@ +# frv testcase for tils $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tils +tils: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/tilt.cgs b/sim/testsuite/frv/tilt.cgs new file mode 100644 index 0000000..4d596b0 --- /dev/null +++ b/sim/testsuite/frv/tilt.cgs @@ -0,0 +1,100 @@ +# frv testcase for tilt $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tilt +tilt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tin.cgs b/sim/testsuite/frv/tin.cgs new file mode 100644 index 0000000..f55c921 --- /dev/null +++ b/sim/testsuite/frv/tin.cgs @@ -0,0 +1,100 @@ +# frv testcase for tin $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tin +tin: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x2 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/tinc.cgs b/sim/testsuite/frv/tinc.cgs new file mode 100644 index 0000000..8e99e31 --- /dev/null +++ b/sim/testsuite/frv/tinc.cgs @@ -0,0 +1,100 @@ +# frv testcase for tinc $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tinc +tinc: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_spr_addr bad,lr + set_icc 0x1 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x3 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x5 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x7 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x9 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_spr_addr bad,lr + set_icc 0xb 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_spr_addr bad,lr + set_icc 0xd 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_spr_addr bad,lr + set_icc 0xf 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tine.cgs b/sim/testsuite/frv/tine.cgs new file mode 100644 index 0000000..d7e8b00 --- /dev/null +++ b/sim/testsuite/frv/tine.cgs @@ -0,0 +1,100 @@ +# frv testcase for tine $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tine +tine: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tino.cgs b/sim/testsuite/frv/tino.cgs new file mode 100644 index 0000000..65a2d6d --- /dev/null +++ b/sim/testsuite/frv/tino.cgs @@ -0,0 +1,53 @@ +# frv testcase for tino +# mach: all + + .include "testutils.inc" + + start + + .global tinev +tinev: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_gr_immed 0,gr7 + + set_icc 0x0 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x1 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x2 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x3 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x4 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x5 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x6 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x7 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x8 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x9 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xa 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xb 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xc 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xd 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xe 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xf 0 + tino ; should branch to tbr + (128 + 4)*16 + pass +bad: + fail diff --git a/sim/testsuite/frv/tinv.cgs b/sim/testsuite/frv/tinv.cgs new file mode 100644 index 0000000..7ec34a4 --- /dev/null +++ b/sim/testsuite/frv/tinv.cgs @@ -0,0 +1,100 @@ +# frv testcase for tinv $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tinv +tinv: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tip.cgs b/sim/testsuite/frv/tip.cgs new file mode 100644 index 0000000..8353422 --- /dev/null +++ b/sim/testsuite/frv/tip.cgs @@ -0,0 +1,100 @@ +# frv testcase for tip $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tip +tip: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xa 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xc 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tira.cgs b/sim/testsuite/frv/tira.cgs new file mode 100644 index 0000000..bd3139e --- /dev/null +++ b/sim/testsuite/frv/tira.cgs @@ -0,0 +1,114 @@ +# frv testcase for tira $GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tira +tira: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass diff --git a/sim/testsuite/frv/tiv.cgs b/sim/testsuite/frv/tiv.cgs new file mode 100644 index 0000000..84a2576 --- /dev/null +++ b/sim/testsuite/frv/tiv.cgs @@ -0,0 +1,100 @@ +# frv testcase for tiv $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tiv +tiv: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/tle.cgs b/sim/testsuite/frv/tle.cgs new file mode 100644 index 0000000..1322821 --- /dev/null +++ b/sim/testsuite/frv/tle.cgs @@ -0,0 +1,109 @@ +# frv testcase for tle $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tle +tle: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/tls.cgs b/sim/testsuite/frv/tls.cgs new file mode 100644 index 0000000..708e617 --- /dev/null +++ b/sim/testsuite/frv/tls.cgs @@ -0,0 +1,109 @@ +# frv testcase for tls $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tls +tls: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/tlt.cgs b/sim/testsuite/frv/tlt.cgs new file mode 100644 index 0000000..12ee05b --- /dev/null +++ b/sim/testsuite/frv/tlt.cgs @@ -0,0 +1,101 @@ +# frv testcase for tlt $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tlt +tlt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tn.cgs b/sim/testsuite/frv/tn.cgs new file mode 100644 index 0000000..05b0424 --- /dev/null +++ b/sim/testsuite/frv/tn.cgs @@ -0,0 +1,101 @@ +# frv testcase for tn $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tn +tn: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x2 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/tnc.cgs b/sim/testsuite/frv/tnc.cgs new file mode 100644 index 0000000..808db3c --- /dev/null +++ b/sim/testsuite/frv/tnc.cgs @@ -0,0 +1,101 @@ +# frv testcase for tnc $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tnc +tnc: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_spr_addr bad,lr + set_icc 0x1 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x3 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x5 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x7 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x9 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_spr_addr bad,lr + set_icc 0xb 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_spr_addr bad,lr + set_icc 0xd 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_spr_addr bad,lr + set_icc 0xf 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tne.cgs b/sim/testsuite/frv/tne.cgs new file mode 100644 index 0000000..880188d --- /dev/null +++ b/sim/testsuite/frv/tne.cgs @@ -0,0 +1,101 @@ +# frv testcase for tne $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tne +tne: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tno.cgs b/sim/testsuite/frv/tno.cgs new file mode 100644 index 0000000..df49969 --- /dev/null +++ b/sim/testsuite/frv/tno.cgs @@ -0,0 +1,54 @@ +# frv testcase for tno +# mach: all + + .include "testutils.inc" + + start + + .global tno +tno: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_icc 0x0 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x1 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x2 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x3 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x4 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x5 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x6 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x7 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x8 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x9 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xa 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xb 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xc 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xd 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xe 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xf 0 + tno ; should branch to tbr + (128 + 4)*16 + pass +bad: + fail diff --git a/sim/testsuite/frv/tnv.cgs b/sim/testsuite/frv/tnv.cgs new file mode 100644 index 0000000..d7f9241 --- /dev/null +++ b/sim/testsuite/frv/tnv.cgs @@ -0,0 +1,101 @@ +# frv testcase for tnv $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tnv +tnv: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tp.cgs b/sim/testsuite/frv/tp.cgs new file mode 100644 index 0000000..2709e31 --- /dev/null +++ b/sim/testsuite/frv/tp.cgs @@ -0,0 +1,101 @@ +# frv testcase for tp $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tp +tp: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xa 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xc 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/frv/tra.cgs b/sim/testsuite/frv/tra.cgs new file mode 100644 index 0000000..368c83a --- /dev/null +++ b/sim/testsuite/frv/tra.cgs @@ -0,0 +1,117 @@ +# frv testcase for tra $GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tra +tra: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 +bad0: + fail +ok0: + test_spr_addr bad0,pcsr + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass diff --git a/sim/testsuite/frv/tv.cgs b/sim/testsuite/frv/tv.cgs new file mode 100644 index 0000000..d173f29 --- /dev/null +++ b/sim/testsuite/frv/tv.cgs @@ -0,0 +1,101 @@ +# frv testcase for tv $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tv +tv: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/frv/udiv.cgs b/sim/testsuite/frv/udiv.cgs new file mode 100644 index 0000000..35cfa8c --- /dev/null +++ b/sim/testsuite/frv/udiv.cgs @@ -0,0 +1,48 @@ +# frv testcase for udiv $GRi,$GRj,$GRk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global udiv +udiv: + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + udiv gr3,gr2,gr3 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from udiv in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + udiv gr3,gr2,gr3 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr + set_gr_addr e1,gr17 +e1: udiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/udivi.cgs b/sim/testsuite/frv/udivi.cgs new file mode 100644 index 0000000..6a50590 --- /dev/null +++ b/sim/testsuite/frv/udivi.cgs @@ -0,0 +1,49 @@ +# frv testcase for udivi $GRi,$s12,$GRk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global udivi +udivi: + ; simple division 12 / 3 + set_gr_immed 0x0000000c,gr3 + udivi gr3,3,gr3 + test_gr_immed 0x00000004,gr3 + + ; random example + set_gr_limmed 0xfedc,0xba98,gr3 + udivi gr3,0x7ff,gr3 + test_gr_limmed 0x001f,0xdf93,gr3 + + ; random example + set_gr_limmed 0xffff,0xffff,gr3 + udivi gr3,-2048,gr3 + test_gr_immed 1,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr + set_gr_addr e1,gr17 +e1: udivi gr1,0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/frv/umul.cgs b/sim/testsuite/frv/umul.cgs new file mode 100644 index 0000000..6c61221 --- /dev/null +++ b/sim/testsuite/frv/umul.cgs @@ -0,0 +1,76 @@ +# frv testcase for umul $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global umul +umul: + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + umul gr7,gr8,gr8 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + umul gr7,gr8,gr8 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xffff,0xffff,gr7 ; max positive result + set_gr_limmed 0xffff,0xffff,gr8 + umul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xfffe,gr8 + test_gr_immed 1,gr9 + + pass diff --git a/sim/testsuite/frv/umulcc.cgs b/sim/testsuite/frv/umulcc.cgs new file mode 100644 index 0000000..c2b5cff --- /dev/null +++ b/sim/testsuite/frv/umulcc.cgs @@ -0,0 +1,98 @@ +# frv testcase for umulcc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global umulcc +umulcc: + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 1,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xffff,0xffff,gr7 ; max positive result + set_gr_limmed 0xffff,0xffff,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xfffe,gr8 + test_gr_immed 1,gr9 + + pass diff --git a/sim/testsuite/frv/umuli.cgs b/sim/testsuite/frv/umuli.cgs new file mode 100644 index 0000000..6f1b9c1 --- /dev/null +++ b/sim/testsuite/frv/umuli.cgs @@ -0,0 +1,87 @@ +# frv testcase for umuli $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global umuli +umuli: + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0x0f,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0x0e,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_icc 0x0f,0 ; Set mask opposite of expected + umuli gr7,1,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0x0b,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_icc 0x0a,0 ; Set mask opposite of expected + umuli gr7,0,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_icc 0x0f,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x0e,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result + set_icc 0x09,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_icc 0x0d,0 ; Set mask opposite of expected + umuli gr7,0x7ff,gr8 + test_icc 1 1 0 1 icc0 + test_gr_immed 0x3ff,gr8 + test_gr_limmed 0x7fff,0xf801,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_icc 0x09,0 ; Set mask opposite of expected + umuli gr7,-2048,gr8 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x7fff,0xfc00,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0xffff,0xffff,gr7 ; max positive result + set_icc 0x05,0 ; Set mask opposite of expected + umuli gr7,-1,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xffff,0xfffe,gr8 + test_gr_immed 1,gr9 + + pass diff --git a/sim/testsuite/frv/umulicc.cgs b/sim/testsuite/frv/umulicc.cgs new file mode 100644 index 0000000..0d0d0c1 --- /dev/null +++ b/sim/testsuite/frv/umulicc.cgs @@ -0,0 +1,87 @@ +# frv testcase for umulicc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global umulicc +umulicc: + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0x0f,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0x0e,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_icc 0x0f,0 ; Set mask opposite of expected + umulicc gr7,1,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0x0b,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_icc 0x0a,0 ; Set mask opposite of expected + umulicc gr7,0,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_icc 0x0f,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x0e,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result + set_icc 0x09,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_icc 0x0d,0 ; Set mask opposite of expected + umulicc gr7,0x1ff,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0xff,gr8 + test_gr_limmed 0x7fff,0xfe01,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_icc 0x09,0 ; Set mask opposite of expected + umulicc gr7,-512,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x7fff,0xff00,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0xffff,0xffff,gr7 ; max positive result + set_icc 0x05,0 ; Set mask opposite of expected + umulicc gr7,-1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xfffe,gr8 + test_gr_immed 1,gr9 + + pass diff --git a/sim/testsuite/frv/xor.cgs b/sim/testsuite/frv/xor.cgs new file mode 100644 index 0000000..97310e4 --- /dev/null +++ b/sim/testsuite/frv/xor.cgs @@ -0,0 +1,38 @@ +# frv testcase for xor $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global xor +xor: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + xor gr7,gr8,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + xor gr7,gr8,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + xor gr7,gr8,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + xor gr7,gr8,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/xorcc.cgs b/sim/testsuite/frv/xorcc.cgs new file mode 100644 index 0000000..9516b78 --- /dev/null +++ b/sim/testsuite/frv/xorcc.cgs @@ -0,0 +1,38 @@ +# frv testcase for xorcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global xorcc +xorcc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + xorcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + xorcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + xorcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + xorcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/frv/xorcr.cgs b/sim/testsuite/frv/xorcr.cgs new file mode 100644 index 0000000..bcb153b --- /dev/null +++ b/sim/testsuite/frv/xorcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for xorcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global xorcr +xorcr: + set_spr_immed 0x1b1b,cccr + xorcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc5,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + xorcr cc5,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + xorcr cc4,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + xorcr cc4,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + xorcr cc4,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + xorcr cc4,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/frv/xori.cgs b/sim/testsuite/frv/xori.cgs new file mode 100644 index 0000000..ed26660 --- /dev/null +++ b/sim/testsuite/frv/xori.cgs @@ -0,0 +1,35 @@ +# frv testcase for xori $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global xori +xori: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x07,0 ; Set mask opposite of expected + xori gr7,0x555,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xaaaa,0xafff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + xori gr7,0,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x0b,0 ; Set mask opposite of expected + xori gr7,0x2aa,gr8 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xa800,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + xori gr7,-273,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x2152,0xfeef,gr8 + + pass diff --git a/sim/testsuite/frv/xoricc.cgs b/sim/testsuite/frv/xoricc.cgs new file mode 100644 index 0000000..b473620 --- /dev/null +++ b/sim/testsuite/frv/xoricc.cgs @@ -0,0 +1,36 @@ +# frv testcase for xoricc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global xoricc +xoricc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x07,0 ; Set mask opposite of expected + xoricc gr7,0x155,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xabff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + xoricc gr7,0,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + xoricc gr7,0xaa,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xaa00,gr8 + + set_gr_limmed 0xdead,0xb000,gr7 + set_icc 0x0d,0 ; Set mask opposite of expected + xoricc gr7,-273,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x2152,0x4eef,gr8 + + pass diff --git a/sim/testsuite/ft32/ChangeLog b/sim/testsuite/ft32/ChangeLog new file mode 100644 index 0000000..cb1d2f4 --- /dev/null +++ b/sim/testsuite/ft32/ChangeLog @@ -0,0 +1,8 @@ +2015-10-12 James Bowman + + * basic.s: Add test for memory size link parameters. + Add test for program memory write port. + +2015-02-28 James Bowman + + * basic.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/ft32/allinsn.exp b/sim/testsuite/ft32/allinsn.exp new file mode 100644 index 0000000..730b422 --- /dev/null +++ b/sim/testsuite/ft32/allinsn.exp @@ -0,0 +1,15 @@ +# ft32 simulator testsuite + +if [istarget ft32-*] { + # all machines + set all_machs "ft32" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/ft32/basic.s b/sim/testsuite/ft32/basic.s new file mode 100644 index 0000000..62977c8 --- /dev/null +++ b/sim/testsuite/ft32/basic.s @@ -0,0 +1,899 @@ +# check that basic insns work. +# mach: ft32 + +.include "testutils.inc" + + start + + ldk $r0,__PMSIZE + EXPECT $r0,0x00040000 + ldk $r0,__RAMSIZE + EXPECT $r0,0x00010000 + + ldk $r4,10 + add $r4,$r4,23 + EXPECT $r4,33 + +# lda, sta + .data +tmp: .long 0 + .text + + xor.l $r0,$r0,$r0 + EXPECT $r0,0x00000000 + xor.l $r0,$r0,$r0 + add.l $r0,$r0,1 + EXPECT $r0,0x00000001 + + ldk.l $r0,0x4567 + EXPECT $r0,0x00004567 + + lpm.l $r0,k_12345678 + EXPECT $r0,0x12345678 + + sta.l tmp,$r0 + lda.l $r1,tmp + EXPECT $r1,0x12345678 + + lda.b $r1,tmp + EXPECT $r1,0x00000078 + + lda.b $r1,tmp+1 + EXPECT $r1,0x00000056 + + lda.b $r1,tmp+2 + EXPECT $r1,0x00000034 + + lda.b $r1,tmp+3 + EXPECT $r1,0x00000012 + + sta.b tmp+1,$r0 + lda.l $r1,tmp+0 + EXPECT $r1,0x12347878 + +# immediate + ldk.l $r1,12 + add.l $r1,$r1,4 + EXPECT $r1,0x00000010 + add.l $r1,$r1,0x1ff + EXPECT $r1,0x0000020f + add.l $r1,$r1,-0x200 + EXPECT $r1,0x0000000f + +# addk + xor.l $r1,$r0,$r0 + add.l $r2,$r1,127 + EXPECT $r2,0x0000007f + + add.l $r2,$r2,127 + EXPECT $r2,0x000000fe + + add.l $r2,$r2,-127 + EXPECT $r2,0x0000007f + + add.l $r2,$r2,-128 + EXPECT $r2,0xffffffff + + add.l $r2,$r2,1 + EXPECT $r2,0x00000000 + +# mul + ldk.l $r1,100 + ldk.l $r2,77 + mul.l $r3,$r1,$r2 + EXPECT $r3,0x00001e14 + + # 0x12345678 ** 2 = 0x14b66dc1df4d840L + mul.l $r3,$r0,$r0 + EXPECT $r3,0x1df4d840 + muluh.l $r3,$r0,$r0 + EXPECT $r3,0x014b66dc + +# push and pop + push.l $r0 + EXPECT $sp,0x0000fffc + ldi.l $r3,$sp,0 + EXPECT $r3,0x12345678 + + pop.l $r4 + EXPECT $sp,0x00000000 + EXPECT $r4,0x12345678 + + ldk.l $r1,0x1111 + push.l $r1 + ldk.l $r1,0x2222 + push.l $r1 + ldk.l $r1,0x3333 + push.l $r1 + ldk.l $r1,0x4444 + push.l $r1 + EXPECT $sp,0x0000fff0 + pop.l $r1 + EXPECT $r1,0x00004444 + pop.l $r1 + EXPECT $r1,0x00003333 + pop.l $r1 + EXPECT $r1,0x00002222 + pop.l $r1 + EXPECT $r1,0x00001111 + +# push and pop with $sp changes + ldk.l $r1,0xa111 + push.l $r1 + sub.l $sp,$sp,4 + ldk.l $r1,0xa222 + push.l $r1 + add.l $sp,$sp,-36 + add.l $sp,$sp,36 + pop.l $r1 + EXPECT $r1,0x0000a222 + add.l $sp,$sp,4 + pop.l $r1 + EXPECT $r1,0x0000a111 + +# sti + ldk.l $r2,80 + EXPECT $r2,0x00000050 + sti.l $r2,0,$r0 + lda.l $r1,80 + EXPECT $r1,0x12345678 + + ldk.l $r3,0xF0 + sti.b $r2,0,$r3 + lda.l $r1,80 + EXPECT $r1,0x123456f0 + + add.l $r2,$r2,1 + sti.l $r2,0,$r0 + sti.b $r2,0,$r3 + lda.l $r1,80 + EXPECT $r1,0x1234f078 + + add.l $r2,$r2,1 + sti.l $r2,0,$r0 + sti.b $r2,0,$r3 + lda.l $r1,80 + EXPECT $r1,0x12f05678 + + add.l $r2,$r2,1 + sti.l $r2,0,$r0 + sti.b $r2,0,$r3 + lda.l $r1,80 + EXPECT $r1,0xf0345678 + + ldk.l $r2,80 + sti.l $r2,0,$r0 + ldk.s $r3,0xbeef + sti.s $r2,0,$r3 + lda.l $r1,80 + EXPECT $r1,0x1234beef + add.l $r2,$r2,2 + sti.s $r2,0,$r3 + lda.l $r1,80 + EXPECT $r1,0xbeefbeef + +# lpmi + + ldk.l $r1,k_12345678 + lpmi.l $r2,$r1,0 + EXPECT $r2,0x12345678 + + lpmi.b $r2,$r1,0 + EXPECT $r2,0x00000078 + + add.l $r1,$r1,1 + lpmi.b $r2,$r1,0 + EXPECT $r2,0x00000056 + + add.l $r1,$r1,1 + lpmi.b $r2,$r1,0 + EXPECT $r2,0x00000034 + + add.l $r1,$r1,1 + lpmi.b $r2,$r1,0 + EXPECT $r2,0x00000012 + + lpmi.l $r2,$r1,4 + EXPECT $r2,0xabcdef01 + + lpmi.l $r2,$r1,-4 + EXPECT $r2,0x10111213 + + lpmi.b $r2,$r1,-4 + EXPECT $r2,0x00000010 + + ldk.l $r1,k_12345678 + lpmi.s $r2,$r1,0 + EXPECT $r2,0x00005678 + lpmi.s $r2,$r1,2 + EXPECT $r2,0x00001234 + lpmi.b $r2,$r1,6 + EXPECT $r2,0x000000cd + lpmi.b $r2,$r1,7 + EXPECT $r2,0x000000ab + lpmi.b $r2,$r1,-1 + EXPECT $r2,0x00000010 + lpmi.s $r2,$r1,-2 + EXPECT $r2,0x00001011 + + ldk.l $r1,k_12345678-127 + lpmi.b $r2,$r1,127 + EXPECT $r2,0x00000078 + + ldk.l $r1,k_12345678+128 + lpmi.b $r2,$r1,-128 + EXPECT $r2,0x00000078 + +# shifts + + lpm.l $r0,k_12345678 + ldk.l $r2,4 + ashl.l $r1,$r0,$r2 + EXPECT $r1,0x23456780 + lshr.l $r1,$r0,$r2 + EXPECT $r1,0x01234567 + ashr.l $r1,$r0,$r2 + EXPECT $r1,0x01234567 + + lpm.l $r0,k_abcdef01 + ashl.l $r1,$r0,$r2 + EXPECT $r1,0xbcdef010 + lshr.l $r1,$r0,$r2 + EXPECT $r1,0x0abcdef0 + ashr.l $r1,$r0,$r2 + EXPECT $r1,0xfabcdef0 + +# rotate right + + lpm.l $r0,k_12345678 + ror.l $r1,$r0,0 + EXPECT $r1,0x12345678 + ror.l $r1,$r0,12 + EXPECT $r1,0x67812345 + ror.l $r1,$r0,-4 + EXPECT $r1,0x23456781 + +# jmpx + ldk $r28,0xaaaaa + jmpx 0,$r28,1,failcase + jmpx 1,$r28,0,failcase + jmpx 2,$r28,1,failcase + jmpx 3,$r28,0,failcase + jmpx 4,$r28,1,failcase + jmpx 5,$r28,0,failcase + jmpx 6,$r28,1,failcase + jmpx 7,$r28,0,failcase + jmpx 8,$r28,1,failcase + jmpx 9,$r28,0,failcase + jmpx 10,$r28,1,failcase + jmpx 11,$r28,0,failcase + jmpx 12,$r28,1,failcase + jmpx 13,$r28,0,failcase + jmpx 14,$r28,1,failcase + jmpx 15,$r28,0,failcase + jmpx 16,$r28,1,failcase + jmpx 17,$r28,0,failcase + jmpx 18,$r28,1,failcase + jmpx 19,$r28,0,failcase + + move $r29,$r28 + ldk $r28,0 + jmpx 0,$r29,1,failcase + jmpx 1,$r29,0,failcase + jmpx 2,$r29,1,failcase + jmpx 3,$r29,0,failcase + jmpx 4,$r29,1,failcase + jmpx 5,$r29,0,failcase + jmpx 6,$r29,1,failcase + jmpx 7,$r29,0,failcase + jmpx 8,$r29,1,failcase + jmpx 9,$r29,0,failcase + jmpx 10,$r29,1,failcase + jmpx 11,$r29,0,failcase + jmpx 12,$r29,1,failcase + jmpx 13,$r29,0,failcase + jmpx 14,$r29,1,failcase + jmpx 15,$r29,0,failcase + jmpx 16,$r29,1,failcase + jmpx 17,$r29,0,failcase + jmpx 18,$r29,1,failcase + jmpx 19,$r29,0,failcase + + move $r30,$r29 + ldk $r29,0 + jmpx 0,$r30,1,failcase + jmpx 1,$r30,0,failcase + jmpx 2,$r30,1,failcase + jmpx 3,$r30,0,failcase + jmpx 4,$r30,1,failcase + jmpx 5,$r30,0,failcase + jmpx 6,$r30,1,failcase + jmpx 7,$r30,0,failcase + jmpx 8,$r30,1,failcase + jmpx 9,$r30,0,failcase + jmpx 10,$r30,1,failcase + jmpx 11,$r30,0,failcase + jmpx 12,$r30,1,failcase + jmpx 13,$r30,0,failcase + jmpx 14,$r30,1,failcase + jmpx 15,$r30,0,failcase + jmpx 16,$r30,1,failcase + jmpx 17,$r30,0,failcase + jmpx 18,$r30,1,failcase + jmpx 19,$r30,0,failcase + +# callx + ldk $r30,0xaaaaa + callx 0,$r30,0,skip1 + jmp failcase + callx 1,$r30,1,skip1 + jmp failcase + callx 2,$r30,0,skip1 + jmp failcase + callx 3,$r30,1,skip1 + jmp failcase + + callx 0,$r30,1,skip1 + ldk $r30,0x123 + EXPECT $r30,0x123 + +#define BIT(N,M) ((((N) & 15) << 5) | (M)) +# bextu + bextu.l $r1,$r0,(0<<5)|0 + EXPECT $r1,0x00005678 + bextu.l $r1,$r0,(4<<5)|0 + EXPECT $r1,0x00000008 + bextu.l $r1,$r0,(4<<5)|4 + EXPECT $r1,0x00000007 + bextu.l $r1,$r0,(4<<5)|28 + EXPECT $r1,0x00000001 + bextu.l $r1,$r0,(8<<5)|16 + EXPECT $r1,0x00000034 + ldk.l $r2,-1 + bextu.l $r1,$r2,(6<<5)|(3) + EXPECT $r1,0x0000003f + +# bexts + bexts.l $r1,$r0,(8<<5)|0 + EXPECT $r1,0x00000078 + bexts.l $r1,$r0,(0<<5)|16 + EXPECT $r1,0x00001234 + bexts.l $r1,$r0,(4<<5)|0 + EXPECT $r1,0xfffffff8 + # extract the '5' digit in widths 4-1 + bexts.l $r1,$r0,(4<<5)|12 + EXPECT $r1,0x00000005 + bexts.l $r1,$r0,(3<<5)|12 + EXPECT $r1,0xfffffffd + bexts.l $r1,$r0,(2<<5)|12 + EXPECT $r1,0x00000001 + bexts.l $r1,$r0,(1<<5)|12 + EXPECT $r1,0xffffffff + +# btst + # low four bits should be 0,0,0,1 + btst.l $r0,(1<<5)|0 + jmpc nz,failcase + btst.l $r0,(1<<5)|1 + jmpc nz,failcase + btst.l $r0,(1<<5)|2 + jmpc nz,failcase + btst.l $r0,(1<<5)|3 + jmpc z,failcase + + # the 6 bit field starting at position 24 is positive + btst.l $r0,(6<<5)|24 + jmpc s,failcase + # the 5 bit field starting at position 24 is negative + btst.l $r0,(5<<5)|24 + jmpc ns,failcase + + EXPECT $r0,0x12345678 + +# bins + bins.l $r1,$r0,(8 << 5) | (0) + EXPECT $r1,0x12345600 + + bins.l $r1,$r0,(0 << 5) | (8) + EXPECT $r1,0x12000078 + + ldk.l $r1,(0xff << 10) | (8 << 5) | (8) + bins.l $r1,$r0,$r1 + EXPECT $r1,0x1234ff78 + + call litr1 + .long (0x8dd1 << 10) | (0 << 5) | (0) + bins.l $r1,$r0,$r1 + EXPECT $r1,0x12348dd1 + + call litr1 + .long (0x8dd1 << 10) | (0 << 5) | (16) + bins.l $r1,$r0,$r1 + EXPECT $r1,0x8dd15678 + + ldk.l $r1,(0xde << 10) | (8 << 5) | (0) + bins.l $r1,$r0,$r1 + EXPECT $r1,0x123456de + +# ldl + ldk.l $r0,0 + ldl.l $r3,$r0,0 + EXPECT $r3,0x00000000 + ldk.l $r0,-1 + ldl.l $r3,$r0,-1 + EXPECT $r3,0xffffffff + ldk.l $r0,(0x12345678 >> 10) + ldl.l $r3,$r0,(0x12345678 & 0x3ff) + EXPECT $r3,0x12345678 + ldk.l $r0,(0xe2345678 >> 10) + ldl.l $r3,$r0,(0xe2345678 & 0x3ff) + EXPECT $r3,0xe2345678 + +# flip + ldk.l $r0,0x0000001 + flip.l $r1,$r0,0 + EXPECT $r1,0x00000001 + + lpm.l $r0,k_12345678 + flip.l $r1,$r0,0 + EXPECT $r1,0x12345678 + flip.l $r1,$r0,24 + EXPECT $r1,0x78563412 + flip.l $r1,$r0,31 + EXPECT $r1,0x1e6a2c48 + +# stack push pop + + EXPECT $sp,0x00000000 + ldk.l $r6,0x6666 + push.l $r6 + or.l $r0,$r0,$r0 # xxx + EXPECT $sp,0x0000fffc + ldi.l $r1,$sp,0 + EXPECT $r1,0x00006666 + pop.l $r1 + EXPECT $r1,0x00006666 + EXPECT $sp,0x00000000 + +# call/return + call fowia + push.l $r1 + call fowia + pop.l $r2 + sub.l $r1,$r1,$r2 + EXPECT $r1,0x00000008 + +# add,carry + + ldk.l $r0,0 + ldk.l $r1,0 + call add64 + EXPECT $r1,0x00000000 + EXPECT $r0,0x00000000 + + lpm.l $r0,k_abcdef01 + lpm.l $r1,k_abcdef01 + call add64 + EXPECT $r1,0x00000001 + EXPECT $r0,0x579bde02 + + ldk.l $r0,4 + ldk.l $r1,-5 + call add64 + EXPECT $r1,0x00000000 + EXPECT $r0,0xffffffff + + ldk.l $r0,5 + ldk.l $r1,-5 + call add64 + EXPECT $r1,0x00000001 + EXPECT $r0,0x00000000 + + lpm.l $r0,k_12345678 + ldk.l $r1,-1 + call add64 + EXPECT $r1,0x00000001 + EXPECT $r0,0x12345677 + + ldk.l $r0,-1 + ldk.l $r1,-1 + call add64 + EXPECT $r1,0x00000001 + EXPECT $r0,0xfffffffe + +# inline literal + call lit + .long 0xdecafbad + EXPECT $r0,0xdecafbad + + ldk.l $r1,0xee + call lit + ldk.l $r1,0xfe + EXPECT $r1,0x000000ee + + call lit + .long 0x01020304 + EXPECT $r0,0x01020304 + + call lit + .long lit + calli $r0 + .long 0xffaa55aa + EXPECT $r0,0xffaa55aa + +# comparisons + ldk.l $r0,-100 + ldk.l $r1,100 + cmp.l $r0,$r1 + + ldk.l $r2,0 + jmpc lt,.c1 + ldk.l $r2,1 +.c1: + EXPECT $r2,0x00000000 + + ldk.l $r2,0 + jmpc gt,.c2 + ldk.l $r2,1 +.c2: + EXPECT $r2,0x00000001 + + ldk.l $r2,0 + jmpc a,.c3 + ldk.l $r2,1 +.c3: + EXPECT $r2,0x00000000 + + ldk.l $r2,0 + jmpc b,.c4 + ldk.l $r2,1 +.c4: + EXPECT $r2,0x00000001 + + ldk.l $r2,0 + jmpc be,.c5 + ldk.l $r2,1 +.c5: + EXPECT $r2,0x00000001 + +# 8-bit comparisons + ldk.l $r0,0x8fe + ldk.l $r1,0x708 + cmp.b $r0,$r1 + + ldk.l $r2,0 + jmpc lt,.8c1 + ldk.l $r2,1 +.8c1: + EXPECT $r2,0x00000000 + + ldk.l $r2,0 + jmpc gt,.8c2 + ldk.l $r2,1 +.8c2: + EXPECT $r2,0x00000001 + + ldk.l $r2,0 + jmpc a,.8c3 + ldk.l $r2,1 +.8c3: + EXPECT $r2,0x00000000 + + ldk.l $r2,0 + jmpc b,.8c4 + ldk.l $r2,1 +.8c4: + EXPECT $r2,0x00000001 + + ldk.l $r2,0 + jmpc be,.8c5 + ldk.l $r2,1 +.8c5: + EXPECT $r2,0x00000001 + + ldk.l $r0,0x8aa + ldk.l $r1,0x7aa + cmp.b $r0,$r1 + + ldk.l $r2,0 + jmpc z,.8c6 + ldk.l $r2,1 +.8c6: + EXPECT $r2,0x00000000 + + ldk.b $r0,1 + ldk.b $r2,0xe0 + cmp.b $r2,0x1c0 + jmpc a,.8c7 + ldk.b $r0,0 +.8c7: + EXPECT $r0,0x00000001 + +# conditional call + cmp.l $r0,$r0 + callc z,lit + .long 0xccddeeff + callc nz,zr0 + EXPECT $r0,0xccddeeff + +# modify return address + ldk.l $r0,0x66 + call skip1 + ldk.l $r0,0xAA + EXPECT $r0,0x00000066 + + ldk.l $r0,0x77 + call skip2 + ldk.l $r0,0xBB + EXPECT $r0,0x00000077 + +# simple recursive function + ldk.l $r0,1 + call factorial + EXPECT $r0,0x00000001 + ldk.l $r0,2 + call factorial + EXPECT $r0,0x00000002 + ldk.l $r0,3 + call factorial + EXPECT $r0,0x00000006 + ldk.l $r0,4 + call factorial + EXPECT $r0,0x00000018 + ldk.l $r0,5 + call factorial + EXPECT $r0,0x00000078 + ldk.l $r0,6 + call factorial + EXPECT $r0,0x000002d0 + ldk.l $r0,7 + call factorial + EXPECT $r0,0x000013b0 + ldk.l $r0,12 + call factorial + EXPECT $r0,0x1c8cfc00 + +# read sp after a call + call nullfunc + EXPECT $sp,0x00000000 + +# CALLI->RETURN + ldk.l $r4,nullfunc + calli $r4 + EXPECT $sp,0x00000000 + +# Link/unlink + ldk.l $r14,0x17566 + + link $r14,48 + EXPECT $r14,0x0000fffc + sub.l $sp,$sp,200 + unlink $r14 + EXPECT $r14,0x00017566 + +# LINK->UNLINK + link $r14,48 + unlink $r14 + EXPECT $r14,0x00017566 + +# LINK->JUMPI + ldk.l $r3,.here + link $r14,48 + jmpi $r3 + jmp failcase +.here: + unlink $r14 + EXPECT $r14,0x00017566 + +# LINK->RETURN +# (This is a nonsense combination, but can still exericse it by +# using a negative parameter for the link. "link $r14,-4" leaves +# $sp exactly unchanged.) + ldk.l $r0,.returnhere + push.l $r0 + link $r14,0xfffc + return +.returnhere: + EXPECT $sp,0x00000000 + +# LPMI->CALLI + ldk.l $r0,k_abcdef01 + ldk.l $r1,increment + lpmi.l $r0,$r0,0 + calli $r1 + EXPECT $r0,0xabcdef02 + +# STRLen + lpm.l $r4,str3 + sta.l tmp,$r4 + ldk.l $r0,tmp + strlen.b $r1,$r0 + EXPECT $r1,0x00000003 + strlen.s $r1,$r0 + EXPECT $r1,0x00000003 + strlen.l $r1,$r0 + EXPECT $r1,0x00000003 + + ldk.l $r4,0 + sta.b 4,$r4 + strlen.l $r1,$r0 + EXPECT $r1,0x00000000 + + ldk.l $r4,-1 + sta.l 4,$r4 + lpm.l $r4,str3 + sta.l 8,$r4 + strlen.l $r1,$r0 + EXPECT $r1,0x00000007 + +# MEMSet + ldk.l $r0,4 + ldk.l $r1,0xaa + memset.s $r0,$r1,8 + ldk.l $r1,0x55 + memset.b $r0,$r1,5 + lda.l $r0,4 + EXPECT $r0,0x55555555 + lda.l $r0,8 + EXPECT $r0,0xaaaaaa55 + +# first cycle after mispredict + ldk.l $r0,3 + cmp.l $r0,$r0 + jmpc nz,failcase + add.l $r0,$r0,7 + EXPECT $r0,0x0000000a + jmpc nz,failcase + push.l $r0 + EXPECT $sp,0x0000fffc + pop.l $r0 + +# $sp access after stall + lpm.l $r13,0 + push.l $r0 + EXPECT $sp,0x0000fffc + pop.l $r0 + + push.l $r0 + add.l $sp,$sp,-484 + EXPECT $sp,0x0000fe18 + EXPECT $sp,0x0000fe18 + EXPECT $sp,0x0000fe18 + add.l $sp,$sp,484 + EXPECT $sp,0x0000fffc + pop.l $r0 + +# atomic exchange + lpm.l $r0,k_12345678 + lpm.l $r1,k_abcdef01 + sta.l 100,$r1 + exa.l $r0,100 + EXPECT $r0,0xabcdef01 + lda.l $r0,100 + EXPECT $r0,0x12345678 + + lpm.l $r0,k_12345678 + lpm.l $r1,k_abcdef01 + sta.l 144,$r1 + ldk.l $r7,20 + exi.l $r0,$r7,124 + EXPECT $r0,0xabcdef01 + lda.l $r0,144 + EXPECT $r0,0x12345678 + + lpm.l $r0,k_12345678 + lpm.l $r1,k_abcdef01 + push $r1 + exi.l $r0,$sp,0 + EXPECT $r0,0xabcdef01 + pop.l $r0 + EXPECT $r0,0x12345678 + +# PM write port + .equ PM_UNLOCK, 0x1fc80 + .equ PM_ADDR, 0x1fc84 + .equ PM_DATA, 0x1fc88 + + lpm.l $r0,k_12345678 + lpm.l $r1,k_abcdef01 + EXPECT $r0,0x12345678 + EXPECT $r1,0xabcdef01 + ldk.l $r3,(0x1337f7d1 >> 10) + ldl.l $r3,$r3,(0x1337f7d1 & 0x3ff) + EXPECT $r3,0x1337f7d1 + ldk $r4,k_12345678 + sta.l PM_ADDR,$r4 + + # write while locked does nothing + sta.l PM_DATA,$r1 + sta.l PM_DATA,$r0 + lpm.l $r0,k_12345678 + lpm.l $r1,k_abcdef01 + EXPECT $r0,0x12345678 + EXPECT $r1,0xabcdef01 + + # write while unlocked modifies program memory + sta.l PM_UNLOCK,$r3 + sta.l PM_DATA,$r1 + sta.l PM_DATA,$r0 + lpm.l $r0,k_12345678 + lpm.l $r1,k_abcdef01 + EXPECT $r0,0xabcdef01 + EXPECT $r1,0x12345678 + +# final stack check + EXPECT $sp,0x00000000 + + PASS + +# -------------------------------------------------- + +skip1: # skip the instruction after the call + pop.l $r1 + add.l $r1,$r1,4 + push.l $r1 + return + +skipparent: # skip the instruction after the caller's call + ldi.l $r1,$sp,4 + add.l $r1,$r1,4 + sti.l $sp,4,$r1 + return +skip2: + call skipparent + return + +add64: + addcc.l $r0,$r1 + add.l $r0,$r0,$r1 + ldk.l $r1,0 + jmpc nc,.done + ldk.l $r1,1 +.done: + return + +fowia: # find out where I'm at + ldi.l $r1,$sp,0 + return + +lit: # load literal to $r0 + pop.l $r14 + lpmi.l $r0,$r14,0 + add.l $r14,$r14,4 + jmpi $r14 +zr0: + ldk.l $r0,0 + return +litr1: + ldi.l $r1,$sp,0 + add.l $r1,$r1,4 + sti.l $sp,0,$r1 + lpmi.l $r1,$r1,-4 + return + +factorial: + ldk.l $r1,1 + cmp.l $r0,$r1 + jmpc z,.factdone + push.l $r0 + add.l $r0,$r0,-1 + call factorial + pop.l $r1 + mul.l $r0,$r0,$r1 +.factdone: + return + +nullfunc: + return + +increment: + add.l $r0,$r0,1 + return + + .long 0x10111213 +k_12345678: + .long 0x12345678 +k_abcdef01: + .long 0xabcdef01 +str3: + .string "abc" diff --git a/sim/testsuite/ft32/testutils.inc b/sim/testsuite/ft32/testutils.inc new file mode 100644 index 0000000..c07811f --- /dev/null +++ b/sim/testsuite/ft32/testutils.inc @@ -0,0 +1,65 @@ + +# Write ch to the standard output + .macro outch ch + ldk $r0,\ch + sta 0x10000,$r0 + .endm + +# End the test with return code c + .macro exit c + ldk $r0,\c + sta 0x1fffc,$r0 + .endm + +# All assembler tests should start with this macro "start" + .macro start + .text + + jmp __start + jmp __start + reti + + .data +ccsave: .long 0 + .text + +# Fiddling to load $cc from the following word in program memory +loadcc: + exi $r29,$sp,0 + lpmi $cc,$r29,0 + add $r29,$r29,4 + exi $r29,$sp,0 + return + +failcase: + outch 'f' + outch 'a' + outch 'i' + outch 'l' + outch '\n' + exit 1 + +__start: + + .endm + +# At the end of the test, the code should reach this macro PASS + .macro PASS + outch 'p' + outch 'a' + outch 's' + outch 's' + outch '\n' + exit 0 + .endm + +# Confirm that reg has value, and fail immediately if not +# Preserves all registers + .macro EXPECT reg,value + sta ccsave,$cc + call loadcc + .long \value + cmp \reg,$cc + jmpc nz,failcase + lda $cc,ccsave + .endm diff --git a/sim/testsuite/h8300/ChangeLog b/sim/testsuite/h8300/ChangeLog new file mode 100644 index 0000000..82128cc --- /dev/null +++ b/sim/testsuite/h8300/ChangeLog @@ -0,0 +1,107 @@ +2021-01-05 Mike Frysinger + + * rotl.s (mach): Set to "h8300s h8sx". + * rotr.s, rotxl.s, rotxr.s, shal.s, shar.s, shll.s, shlr.s, tas.s: + Likewise. + +2021-01-05 Mike Frysinger + + * allinsn.exp: Rewrite file to use globs. + +2004-06-28 Alexandre Oliva + + 2003-07-22 Michael Snyder + * mul.s: Don't try to use negative immediate (it's always + unsigned). + * div.s: Ditto. + +2004-06-24 Alexandre Oliva + + 2004-06-17 Alexandre Oliva + * band.s, biand.s: imm3_abs16 is not available on h8300h. + * bset.s: Likewise. Ditto for rn_abs32. + +2003-07-22 Michael Snyder + + * cmpw.s: Add test for less-than-zero immediate. + * shll.s: Test for shll reg, reg. + * shlr.s: Test for shlr reg, reg. + * mova.s: Add dozens of new mova tests. + +2003-05-30 Alexandre Oliva + + * allinsn.exp: Fix typos introduced on 2003-05-27. + +2003-05-29 Michael Snyder + + * tas.s: Use er4 for h8h and h8s, er3 for h8sx. + +2003-05-28 Michael Snyder + + * subs.s: New file. + * subx.s: New file. + * allinsn.exp: Add new subs and subx tests. + * testutils.inc: Simplify (and fix) set_carry_flag. + (clear_carry_flag, set_zero_flag, clear_zero_flag...): New macros. + * addx.s: Use simplified set_carry_flag. + +2003-05-27 Michael Snyder + + * tas.s: New file. + * band.s: New file. + * biand.s: New file. + * allinsn.exp: Add tas, band, biand tests. + * brabc.s: Add abs8 test. + * bset.s: Add bset/ne, bclr/ne tests. + +2003-05-23 Michael Snyder + + * and.b.s: Add andc exr. + * or.b.s: Add orc.exr. + * xor.b.s: Add xor exr. + + * jmp.s: Fix 8-bit indirect test. Add 7-bit vector test. + +2003-05-22 Michael Snyder + + * stack.s: Add rte/l and rts/l tests. + * allinsn.exp: Add stack tests. + +2003-05-21 Michael Snyder + + * stack.s: New file: test stack operations. + * stack.s: Add bsr, jsr tests. + * stack.s: Add trapa, rte tests. + + * div.s: Corrections for size of dividend. + +2003-05-20 Michael Snyder + + * mul.s: Corrections for unsigned multiply. + + * div.s: New file, test div instructions. + * allinsn.exp: Add div test. + +2003-05-19 Michael Snyder + + * mul.s: New file, test mul instructions. + * allinsn.exp: Add mul test. + +2003-05-14 Michael Snyder + + * addb.s, addw.s, addl.s, addw.s, addx.s, andb.s, andw.s, andl.s, + bfld.s, brabc.s, bra.s, bset.s, cmpb.s, cmpw.s, cmpl.s, daa.s, + das.s, dec.s, extw.s, extl.s, inc.s, jmp.s, ldc.s, ldm.s, mac.s, + mova.s, movb.s, movw.s, movl.s, movmd.s, movsd.s, neg.s, nop.s, + not.s, orb.s, orw.s, orl.s, rotl.s, rotr.s, rotxl.s, rotxr.s, + shal.s, shar.s, shll.s, shlr.s, stc.s, subb.s, subw.s, subl.s, + xorb.s, xorw.s, xorl.s: New files. + * allinsn.exp: New file. + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +change-log-default-name: "ChangeLog" +End: diff --git a/sim/testsuite/h8300/addb.s b/sim/testsuite/h8300/addb.s new file mode 100644 index 0000000..f1e4ebf --- /dev/null +++ b/sim/testsuite/h8300/addb.s @@ -0,0 +1,778 @@ +# Hitachi H8 testcase 'add.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # add.b #xx:8, rd ; 8 rd xxxxxxxx + # add.b #xx:8, @erd ; 7 d rd ???? 8 ???? xxxxxxxx + # add.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? 8 ???? xxxxxxxx + # add.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? 8 ???? xxxxxxxx + # add.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? 8 ???? xxxxxxxx + # add.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? 8 ???? xxxxxxxx + # add.b #xx:8, @(d:16, erd) ; 0 1 7 4 6 e b30 | rd, b31, dd:16 8 ???? xxxxxxxx + # add.b #xx:8, @(d:32, erd) ; 7 8 b30 | rd, 4 6 a 2 8 dd:32 8 ???? xxxxxxxx + # add.b #xx:8, @aa:8 ; 7 f aaaaaaaa 8 ???? xxxxxxxx + # add.b #xx:8, @aa:16 ; 6 a 1 1??? aa:16 8 ???? xxxxxxxx + # add.b #xx:8, @aa:32 ; 6 a 3 1??? aa:32 8 ???? xxxxxxxx + # add.b rs, rd ; 0 8 rs rd + # add.b reg8, @erd ; 7 d rd ???? 0 8 rs ???? + # add.b reg8, @erd+ ; 0 1 7 9 8 rd 1 rs + # add.b reg8, @erd- ; 0 1 7 9 a rd 1 rs + # add.b reg8, @+erd ; 0 1 7 9 9 rd 1 rs + # add.b reg8, @-erd ; 0 1 7 9 b rd 1 rs + # add.b reg8, @(d:16, erd) ; 0 1 7 9 c b30 | rd32, 1 rs8 imm16 + # add.b reg8, @(d:32, erd) ; 0 1 7 9 d b31 | rd32, 1 rs8 imm32 + # add.b reg8, @aa:8 ; 7 f aaaaaaaa 0 8 rs ???? + # add.b reg8, @aa:16 ; 6 a 1 1??? aa:16 0 8 rs ???? + # add.b reg8, @aa:32 ; 6 a 3 1??? aa:32 0 8 rs ???? + # + + # Coming soon: + # add.b #xx:8, @(d:2, erd) ; 0 1 7 b30 | b21 | dd:2, 8 ???? xxxxxxxx + # add.b reg8, @(d:2, erd) ; 0 1 7 9 dd:2 rd32 1 rs8 + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0 +post_byte: .byte 0 + + start + +add_b_imm8_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.b #xx:8,Rd + add.b #5:8, r0l ; Immediate 8-bit src, reg8 dst + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5aa r0 ; add result: a5 + 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +add_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@eRd + mov #byte_dest, er0 + add.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #5, r0l + beq .L1 + fail +.L1: + +add_b_imm8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@eRd+ + mov #byte_dest, er0 + add.b #5:8, @er0+ ; Immediate 8-bit src, reg post-inc dst +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #10, r0l + beq .L2 + fail +.L2: + +add_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@eRd- + mov #byte_dest, er0 + add.b #5:8, @er0- ; Immediate 8-bit src, reg post-dec dst +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #15, r0l + beq .L3 + fail +.L3: + +add_b_imm8_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@+eRd + mov #pre_byte, er0 + add.b #5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #20, r0l + beq .L4 + fail +.L4: + +add_b_imm8_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@-eRd + mov #post_byte, er0 + add.b #5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #25, r0l + beq .L5 + fail +.L5: + +add_b_imm8_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@(dd:16, eRd) + mov #post_byte, er0 + add.b #5:8, @(-1:16, er0) ; Immediate 8-bit src, 16-bit reg disp dest. +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 0xffff +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #30, r0l + beq .L6 + fail +.L6: + +add_b_imm8_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@(dd:32, eRd) + mov #pre_byte, er0 + add.b #5:8, @(1:32, er0) ; Immediate 8-bit src, 32-bit reg disp. dest. +;;; .word 0x7804 +;;; .word 0x6a28 +;;; .word 0x0000 +;;; .word 0x0001 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #35, r0l + beq .L7 + fail +.L7: + +add_b_imm8_abs8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b reg8,@aa:8 + ;; NOTE: for abs8, we will use the SBR register as a base, + ;; since otherwise we would have to make sure that the destination + ;; was in the zero page. + ;; + mov #byte_dest-100, er0 + ldc er0, sbr + add.b #5, @100:8 ; 8-bit reg src, 8-bit absolute dest +;;; .word 0x7f64 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-100, er0 ; reg 0 has base address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #40, r0l + beq .L8 + fail +.L8: + +add_b_imm8_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@aa:16 + add.b #5:8, @byte_dest:16 ; Immediate 8-bit src, 16-bit absolute dest +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #45, r0l + beq .L9 + fail +.L9: + +add_b_imm8_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@aa:32 + add.b #5:8, @byte_dest:32 ; Immediate 8-bit src, 32-bit absolute dest +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #50, r0l + beq .L10 + fail +.L10: + +.endif + +add_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.b Rs,Rd + mov.b #5, r0h + add.b r0h, r0l ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x05aa r0 ; add result: a5 + 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +add_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@eRd ; Add to register indirect + mov #byte_dest, er0 + mov #5, r1l + add.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x0890 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #55, r0l + beq .L11 + fail +.L11: + +add_b_reg8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@eRd+ ; Add to register post-increment + mov #byte_dest, er0 + mov #5, r1l + add.b r1l, @er0+ ; reg8 src, reg post-incr dest +;;; .word 0x0179 +;;; .word 0x8019 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #60, r0l + beq .L12 + fail +.L12: + +add_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@eRd- ; Add to register post-decrement + mov #byte_dest, er0 + mov #5, r1l + add.b r1l, @er0- ; reg8 src, reg post-decr dest +;;; .word 0x0179 +;;; .word 0xa019 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #65, r0l + beq .L13 + fail +.L13: + +add_b_reg8_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@+eRd ; Add to register pre-increment + mov #pre_byte, er0 + mov #5, r1l + add.b r1l, @+er0 ; reg8 src, reg pre-incr dest +;;; .word 0x0179 +;;; .word 0x9019 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #70, r0l + beq .L14 + fail +.L14: + +add_b_reg8_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@-eRd ; Add to register pre-decrement + mov #post_byte, er0 + mov #5, r1l + add.b r1l, @-er0 ; reg8 src, reg pre-decr dest +;;; .word 0x0179 +;;; .word 0xb019 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #75, r0l + beq .L15 + fail +.L15: + +add_b_reg8_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@(dd:16, eRd) ; Add to register + 16-bit displacement + mov #pre_byte, er0 + mov #5, r1l + add.b r1l, @(1:16, er0) ; reg8 src, 16-bit reg disp dest +;;; .word 0x0179 +;;; .word 0xc019 +;;; .word 0x0001 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #80, r0l + beq .L16 + fail +.L16: + +add_b_reg8_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@-eRd ; Add to register plus 32-bit displacement + mov #post_byte, er0 + mov #5, r1l + add.b r1l, @(-1:32, er0) ; reg8 src, 32-bit reg disp dest +;;; .word 0x0179 +;;; .word 0xd819 +;;; .word 0xffff +;;; .word 0xffff + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #85, r0l + beq .L17 + fail +.L17: + +add_b_reg8_abs8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b reg8,@aa:8 + ;; NOTE: for abs8, we will use the SBR register as a base, + ;; since otherwise we would have to make sure that the destination + ;; was in the zero page. + ;; + mov #byte_dest-100, er0 + ldc er0, sbr + mov #5, r1l + add.b r1l, @100:8 ; 8-bit reg src, 8-bit absolute dest +;;; .word 0x7f64 +;;; .word 0x0890 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-100, er0 ; reg 0 has base address + test_h_gr32 0xa5a5a505 er1 ; reg 1 has test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #90, r0l + beq .L18 + fail +.L18: + +add_b_reg8_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b reg8,@aa:16 + mov #5, r0l + add.b r0l, @byte_dest:16 ; 8-bit reg src, 16-bit absolute dest +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x0880 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #95, r0l + beq .L19 + fail +.L19: + +add_b_reg8_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b reg8,@aa:32 + mov #5, r0l + add.b r0l, @byte_dest:32 ; 8-bit reg src, 32-bit absolute dest +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x0880 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #100, r0l + beq .L20 + fail +.L20: + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/h8300/addl.s b/sim/testsuite/h8300/addl.s new file mode 100644 index 0000000..586fcf6 --- /dev/null +++ b/sim/testsuite/h8300/addl.s @@ -0,0 +1,1865 @@ +# Hitachi H8 testcase 'add.l' +# mach(): h8300h h8300s h8sx +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # add.l xx:3, erd + # add.l xx:16, erd + # add.l xx:32, erd + # add.l xx:16, @erd + # add.l xx:16, @erd+ + # add.l xx:16, @erd- + # add.l xx:16, @+erd + # add.l xx:16, @-erd + # add.l xx:16, @(dd:2, erd) + # add.l xx:16, @(dd:16, erd) + # add.l xx:16, @(dd:32, erd) + # add.l xx:16, @aa:16 + # add.l xx:16, @aa:32 + # add.l xx:32, @erd+ + # add.l xx:32, @erd- + # add.l xx:32, @+erd + # add.l xx:32, @-erd + # add.l xx:32, @(dd:2, erd) + # add.l xx:32, @(dd:16, erd) + # add.l xx:32, @(dd:32, erd) + # add.l xx:32, @aa:16 + # add.l xx:32, @aa:32 + # add.l ers, erd + # add.l ers, @erd + # add.l ers, @erd+ + # add.l ers, @erd- + # add.l ers, @+erd + # add.l ers, @-erd + # add.l ers, @(dd:2, erd) + # add.l ers, @(dd:16, erd) + # add.l ers, @(dd:32, erd) + # add.l ers, @aa:16 + # add.l ers, @aa:32 + # add.l ers, erd + # add.l @ers, erd + # add.l @ers+, erd + # add.l @ers-, erd + # add.l @+ers, erd + # add.l @-ers, erd + # add.l @(dd:2, ers), erd + # add.l @(dd:16, ers), erd + # add.l @(dd:32, ers), erd + # add.l @aa:16, erd + # add.l @aa:32, erd + # add.l @ers, @erd + # add.l @ers+, @erd+ + # add.l @ers-, @erd- + # add.l @+ers, +@erd + # add.l @-ers, @-erd + # add.l @(dd:2, ers), @(dd:2, erd) + # add.l @(dd:16, ers), @(dd:16, erd) + # add.l @(dd:32, ers), @(dd:32, erd) + # add.l @aa:16, @aa:16 + # add.l @aa:32, @aa:32 + + start + + .data + .align 4 +long_src: + .long 0x12345678 +long_dst: + .long 0x87654321 + + .text + + ;; + ;; Add long from immediate source + ;; + +.if (sim_cpu == h8sx) +add_l_imm3_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:3, erd + add.l #0x3:3, er0 ; Immediate 16-bit operand +;;; .word 0x0ab8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a5a8 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_imm16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, erd + add.l #0x1234, er0 ; Immediate 16-bit operand +;;; .word 0x7a18 +;;; .word 0x1234 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5b7d9 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +add_l_imm32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, erd + add.l #0x12345678, er0 ; Immediate 32-bit operand +;;; .word 0x7a10 +;;; .long 0x12345678 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +add_l_imm16_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @erd + mov.l #long_dst, er1 + add.l #0xdead:16, @er1 ; Register indirect operand +;;; .word 0x010e +;;; .word 0x0110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext11 + fail +.Lnext11: + mov.l #0x87654321, @long_dst ; Initialize it again for the next use. + +add_l_imm16_to_postinc: ; post-increment from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @erd+ + mov.l #long_dst, er1 + add.l #0xdead:16, @er1+ ; Imm16, register post-incr operands. +;;; .word 0x010e +;;; .word 0x8110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext12 + fail +.Lnext12: + mov.l #0x87654321, @long_dst ; initialize it again for the next use. + +add_l_imm16_to_postdec: ; post-decrement from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @erd- + mov.l #long_dst, er1 + add.l #0xdead:16, @er1- ; Imm16, register post-decr operands. +;;; .word 0x010e +;;; .word 0xa110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext13 + fail +.Lnext13: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @+erd + mov.l #long_dst-4, er1 + add.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands +;;; .word 0x010e +;;; .word 0x9110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext14 + fail +.Lnext14: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @-erd + mov.l #long_dst+4, er1 + add.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands +;;; .word 0x010e +;;; .word 0xb110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext15 + fail +.Lnext15: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @(dd:2, erd) + mov.l #long_dst-12, er1 + add.l #0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand +;;; .word 0x010e +;;; .word 0x3110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext16 + fail +.Lnext16: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @(dd:16, erd) + mov.l #long_dst-4, er1 + add.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x010e +;;; .word 0xc110 +;;; .word 0xdead +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext17 + fail +.Lnext17: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @(dd:32, erd) + mov.l #long_dst-8, er1 + add.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x010e +;;; .word 0xc910 +;;; .word 0xdead +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext18 + fail +.Lnext18: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @aa:16 + add.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x010e +;;; .word 0x4010 +;;; .word 0xdead +;;; .word @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext19 + fail +.Lnext19: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @aa:32 + add.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x010e +;;; .word 0x4810 +;;; .word 0xdead +;;; .long @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext20 + fail +.Lnext20: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @erd + mov.l #long_dst, er1 + add.l #0xcafedead:32, @er1 ; Register indirect operand +;;; .word 0x010e +;;; .word 0x0118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext21 + fail +.Lnext21: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_postinc: ; post-increment from imm32 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @erd+ + mov.l #long_dst, er1 + add.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands. +;;; .word 0x010e +;;; .word 0x8118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext22 + fail +.Lnext22: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_postdec: ; post-decrement from imm32 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @erd- + mov.l #long_dst, er1 + add.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands. +;;; .word 0x010e +;;; .word 0xa118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext23 + fail +.Lnext23: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @+erd + mov.l #long_dst-4, er1 + add.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands +;;; .word 0x010e +;;; .word 0x9118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext24 + fail +.Lnext24: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @-erd + mov.l #long_dst+4, er1 + add.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands +;;; .word 0x010e +;;; .word 0xb118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext25 + fail +.Lnext25: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @(dd:2, erd) + mov.l #long_dst-12, er1 + add.l #0xcafedead:32, @(12:2, er1) ; Imm32, reg plus 2-bit disp. operand +;;; .word 0x010e +;;; .word 0x3118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext26 + fail +.Lnext26: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @(dd:16, erd) + mov.l #long_dst-4, er1 + add.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x010e +;;; .word 0xc118 +;;; .long 0xcafedead +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext27 + fail +.Lnext27: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @(dd:32, erd) + mov.l #long_dst-8, er1 + add.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x010e +;;; .word 0xc918 +;;; .long 0xcafedead +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext28 + fail +.Lnext28: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @aa:16 + add.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x010e +;;; .word 0x4018 +;;; .long 0xcafedead +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext29 + fail +.Lnext29: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @aa:32 + add.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x010e +;;; .word 0x4818 +;;; .long 0xcafedead +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext30 + fail +.Lnext30: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. +.endif + + ;; + ;; Add long from register source + ;; + +add_l_reg32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, erd + mov.l #0x12345678, er1 + add.l er1, er0 ; Register 32-bit operand +;;; .word 0x0a90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 ; add result + test_h_gr32 0x12345678 er1 ; add src unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +add_l_reg32_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @erd + mov.l #long_dst, er1 + add.l er0, @er1 ; Register indirect operand +;;; .word 0x0109 +;;; .word 0x0110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext44 + fail +.Lnext44: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_postinc: ; post-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @erd+ + mov.l #long_dst, er1 + add.l er0, @er1+ ; Register post-incr operand +;;; .word 0x0109 +;;; .word 0x8110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext49 + fail +.Lnext49: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_postdec: ; post-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @erd- + mov.l #long_dst, er1 + add.l er0, @er1- ; Register post-decr operand +;;; .word 0x0109 +;;; .word 0xa110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext50 + fail +.Lnext50: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @+erd + mov.l #long_dst-4, er1 + add.l er0, @+er1 ; Register pre-incr operand +;;; .word 0x0109 +;;; .word 0x9110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext51 + fail +.Lnext51: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @-erd + mov.l #long_dst+4, er1 + add.l er0, @-er1 ; Register pre-decr operand +;;; .word 0x0109 +;;; .word 0xb110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext48 + fail +.Lnext48: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @(dd:2, erd) + mov.l #long_dst-12, er1 + add.l er0, @(12:2, er1) ; Register plus 2-bit disp. operand +;;; .word 0x0109 +;;; .word 0x3110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext52 + fail +.Lnext52: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @(dd:16, erd) + mov.l #long_dst-4, er1 + add.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x0109 +;;; .word 0xc110 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext45 + fail +.Lnext45: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @(dd:32, erd) + mov.l #long_dst-8, er1 + add.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x0109 +;;; .word 0xc910 +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext46 + fail +.Lnext46: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @aa:16 + add.l er0, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x0109 +;;; .word 0x4110 +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext41 + fail +.Lnext41: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @aa:32 + add.l er0, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x0109 +;;; .word 0x4910 +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext42 + fail +.Lnext42: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + + ;; + ;; Add long to register destination. + ;; + +add_l_indirect_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers, Rd + mov.l #long_src, er1 + add.l @er1, er0 ; Register indirect operand +;;; .word 0x010a +;;; .word 0x0110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_postinc_to_reg32: ; post-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers+, erd + mov.l #long_src, er1 + add.l @er1+, er0 ; Register post-incr operand +;;; .word 0x010a +;;; .word 0x8110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src+4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_postdec_to_reg32: ; post-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers-, erd + mov.l #long_src, er1 + add.l @er1-, er0 ; Register post-decr operand +;;; .word 0x010a +;;; .word 0xa110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src-4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_preinc_to_reg32: ; pre-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @+ers, erd + mov.l #long_src-4, er1 + add.l @+er1, er0 ; Register pre-incr operand +;;; .word 0x010a +;;; .word 0x9110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_predec_to_reg32: ; pre-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @-ers, erd + mov.l #long_src+4, er1 + add.l @-er1, er0 ; Register pre-decr operand +;;; .word 0x010a +;;; .word 0xb110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +add_l_disp2_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:2, ers), erd + mov.l #long_src-4, er1 + add.l @(4:2, er1), er0 ; Register plus 2-bit disp. operand +;;; .word 0x010a +;;; .word 0x1110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src-4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_disp16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:16, ers), erd + mov.l #long_src+0x1234, er1 + add.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand +;;; .word 0x010a +;;; .word 0xc110 +;;; .word -0x1234 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src+0x1234, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_disp32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:32, ers), erd + mov.l #long_src+65536, er1 + add.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand +;;; .word 0x010a +;;; .word 0xc910 +;;; .long -65536 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src+65536, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_abs16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @aa:16, erd + add.l @long_src:16, er0 ; 16-bit address-direct operand +;;; .word 0x010a +;;; .word 0x4010 +;;; .word @long_src + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_abs32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @aa:32, erd + add.l @long_src:32, er0 ; 32-bit address-direct operand +;;; .word 0x010a +;;; .word 0x4810 +;;; .long @long_src + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + + ;; + ;; Add long from memory to memory + ;; + +add_l_indirect_to_indirect: ; reg indirect, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers, @erd + mov.l #long_src, er1 + mov.l #long_dst, er0 + add.l @er1, @er0 +;;; .word 0x0104 +;;; .word 0x691c +;;; .word 0x0010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst ; FIXME + beq .Lnext55 + fail +.Lnext55: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext56 + fail +.Lnext56: ; OK, pass on. + +add_l_postinc_to_postinc: ; reg post-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers+, @erd+ + mov.l #long_src, er1 + mov.l #long_dst, er0 + add.l @er1+, @er0+ +;;; .word 0x0104 +;;; .word 0x6d1c +;;; .word 0x8010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst+4 er0 + test_h_gr32 long_src+4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext65 + fail +.Lnext65: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext66 + fail +.Lnext66: ; OK, pass on. + +add_l_postdec_to_postdec: ; reg post-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers-, @erd- + mov.l #long_src, er1 + mov.l #long_dst, er0 + add.l @er1-, @er0- +;;; .word 0x0106 +;;; .word 0x6d1c +;;; .word 0xa010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-4 er0 + test_h_gr32 long_src-4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext75 + fail +.Lnext75: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext76 + fail +.Lnext76: ; OK, pass on. + +add_l_preinc_to_preinc: ; reg pre-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @+ers, @+erd + mov.l #long_src-4, er1 + mov.l #long_dst-4, er0 + add.l @+er1, @+er0 +;;; .word 0x0105 +;;; .word 0x6d1c +;;; .word 0x9010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext85 + fail +.Lnext85: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext86 + fail +.Lnext86: ; OK, pass on. + +add_l_predec_to_predec: ; reg pre-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @-ers, @-erd + mov.l #long_src+4, er1 + mov.l #long_dst+4, er0 + add.l @-er1, @-er0 +;;; .word 0x0107 +;;; .word 0x6d1c +;;; .word 0xb010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext95 + fail +.Lnext95: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext96 + fail +.Lnext96: ; OK, pass on. + +add_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:2, ers), @(dd:2, erd) + mov.l #long_src-4, er1 + mov.l #long_dst-8, er0 + add.l @(4:2, er1), @(8:2, er0) +;;; .word 0x0105 +;;; .word 0x691c +;;; .word 0x2010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-8 er0 + test_h_gr32 long_src-4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext105 + fail +.Lnext105: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext106 + fail +.Lnext106: ; OK, pass on. + +add_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:16, ers), @(dd:16, erd) + mov.l #long_src-1, er1 + mov.l #long_dst-2, er0 + add.l @(1:16, er1), @(2:16, er0) +;;; .word 0x0104 +;;; .word 0x6f1c +;;; .word 0x0001 +;;; .word 0xc010 +;;; .word 0x0002 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-2 er0 + test_h_gr32 long_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext115 + fail +.Lnext115: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext116 + fail +.Lnext116: ; OK, pass on. + +add_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:32, ers), @(dd:32, erd) + mov.l #long_src-1, er1 + mov.l #long_dst-2, er0 + add.l @(1:32, er1), @(2:32, er0) +;;; .word 0x7894 +;;; .word 0x6b2c +;;; .word 0xc9c8 +;;; .long 1 +;;; .word 0xc810 +;;; .long 2 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-2 er0 + test_h_gr32 long_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext125 + fail +.Lnext125: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext126 + fail +.Lnext126: ; OK, pass on. + +add_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @aa:16, @aa:16 + add.l @long_src:16, @long_dst:16 +;;; .word 0x0104 +;;; .word 0x6b0c +;;; .word @long_src +;;; .word 0x4010 +;;; .word @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext135 + fail +.Lnext135: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext136 + fail +.Lnext136: ; OK, pass on. + +add_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @aa:32, @aa:32 + add.l @long_src:32, @long_dst:32 +;;; .word 0x0104 +;;; .word 0x6b2c +;;; .long @long_src +;;; .word 0x4810 +;;; .long @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext145 + fail +.Lnext145: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext146 + fail +.Lnext146: ; OK, pass on. + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/h8300/adds.s b/sim/testsuite/h8300/adds.s new file mode 100644 index 0000000..9789e87 --- /dev/null +++ b/sim/testsuite/h8300/adds.s @@ -0,0 +1,74 @@ +# Hitachi H8 testcase 'adds' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # adds #1, erd ; 0 b 0 xerd + # adds #2, erd ; 0 b 8 xerd + # adds #4, erd ; 0 b 9 xerd + # + + start +.if (sim_cpu) ; 32 bit only +adds_1: + set_grs_a5a5 + set_ccr_zero + + adds #1, er0 + + test_cc_clear ; adds should not affect any condition codes + test_h_gr32 0xa5a5a5a6 er0 ; result of adds #1 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +adds_2: + set_grs_a5a5 + set_ccr_zero + + adds #2, er0 + + test_cc_clear ; adds should not affect any condition codes + test_h_gr32 0xa5a5a5a7 er0 ; result of adds #2 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +adds_4: + set_grs_a5a5 + set_ccr_zero + + adds #4, er0 + + test_cc_clear ; adds should not affect any condition codes + test_h_gr32 0xa5a5a5a9 er0 ; result of adds #4 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass +.endif + exit 0 diff --git a/sim/testsuite/h8300/addw.s b/sim/testsuite/h8300/addw.s new file mode 100644 index 0000000..c38bf69 --- /dev/null +++ b/sim/testsuite/h8300/addw.s @@ -0,0 +1,87 @@ +# Hitachi H8 testcase 'add.w' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # add.w xx:3, rd ; 0 a 0xxx rd (sx only) + # add.w xx:16, rd ; 7 9 1 rd imm16 + # add.w rs, rd ; 0 9 rs rd + # + + start + +.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx +add_w_imm3: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.w #xx:3,Rd ; Immediate 3-bit operand + add.w #7, r0 ; FIXME will not assemble yet +; .word 0x0a70 ; Fake it until assembler will take it. + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5ac r0 ; add result: a5a5 + 7 + test_h_gr32 0xa5a5a5ac er0 ; add result: a5a5 + 7 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +add_w_imm16: + ;; add.w immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.w #xx:16,Rd + add.w #0x111, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111 + test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +add_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.w Rs,Rd + mov.w #0x111, r1 + add.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111 + test_h_gr16 0x0111 r1 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111 + test_h_gr32 0xa5a50111 er1 +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/addx.s b/sim/testsuite/h8300/addx.s new file mode 100644 index 0000000..ef4e9d3 --- /dev/null +++ b/sim/testsuite/h8300/addx.s @@ -0,0 +1,992 @@ +# Hitachi H8 testcase 'addx' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # addx.b #xx:8, rd8 ; 9 rd8 xxxxxxxx + # addx.b #xx:8, @erd ; 7 d erd ???? 9 ???? xxxxxxxx + # addx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? 9 ???? xxxxxxxx + # addx.b rs8, rd8 ; 0 e rs8 rd8 + # addx.b rs8, @erd ; 7 d erd ???? 0 e rs8 ???? + # addx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 0 e rs8 ???? + # addx.b @ers, rd8 ; 7 c ers ???? 0 e ???? rd8 + # addx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 0 e ???? rd8 + # addx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 1 ???? + # addx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 1 ???? + # + # word ops + # long ops + +.data +byte_src: .byte 0x5 +byte_dest: .byte 0 + + .align 2 +word_src: .word 0x505 +word_dest: .word 0 + + .align 4 +long_src: .long 0x50505 +long_dest: .long 0 + + + start + +addx_b_imm8_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b #xx:8,Rd ; Addx with carry initially zero. + addx.b #5, r0l ; Immediate 8-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa5aa r0 ; add result: a5 + 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_b_imm8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b #xx:8,Rd ; Addx with carry initially one. + set_carry_flag + addx.b #5, r0l ; Immediate 8-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa5ab r0 ; add result: a5 + 5 + 1 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5ab er0 ; add result: a5 + 5 + 1 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +addx_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b #xx:8,@eRd ; Addx to register indirect + mov #byte_dest, er0 + addx.b #5, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.b #5, @byte_dest + beq .Lb1 + fail +.Lb1: + +addx_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b #xx:8,@eRd- ; Addx to register post-decrement + mov #byte_dest, er0 + addx.b #5, @er0- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.b #10, @byte_dest + beq .Lb2 + fail +.Lb2: +.endif + +addx_b_reg8_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b Rs,Rd ; addx with carry initially zero + mov.b #5, r0h + addx.b r0h, r0l ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0x05aa r0 ; add result: a5 + 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b Rs,Rd ; addx with carry initially one + mov.b #5, r0h + set_carry_flag + addx.b r0h, r0l ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0x05ab r0 ; add result: a5 + 5 + 1 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505ab er0 ; add result: a5 + 5 + 1 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +addx_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b rs8,@eRd ; Addx to register indirect + mov #byte_dest, er0 + mov.b #5, r1l + addx.b r1l, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.b #15, @byte_dest + beq .Lb3 + fail +.Lb3: + +addx_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b rs8,@eRd- ; Addx to register post-decrement + mov #byte_dest, er0 + mov.b #5, r1l + addx.b r1l, @er0- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.b #20, @byte_dest + beq .Lb4 + fail +.Lb4: + +addx_b_rsind_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b @eRs,rd8 ; Addx from reg indirect to reg + mov #byte_src, er0 + addx.b @er0, r1l + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src er0 ; er0 still contains address + test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_b_rspostdec_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b @eRs-,rd8 ; Addx to register post-decrement + mov #byte_src, er0 + addx.b @er0-, r1l + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src-1 er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_b_rsind_rsind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b @eRs,rd8 ; Addx from reg indirect to reg + mov #byte_src, er0 + mov #byte_dest, er1 + addx.b @er0, @er1 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_src er0 ; er0 still contains src address + test_h_gr32 byte_dest er1 ; er1 still contains dst address + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the add to memory. + cmp.b #25, @byte_dest + beq .Lb5 + fail +.Lb5: + +addx_b_rspostdec_rspostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b @eRs-,rd8 ; Addx to register post-decrement + mov #byte_src, er0 + mov #byte_dest, er1 + addx.b @er0-, @er1- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_src-1 er0 ; er0 contains src address minus one + test_h_gr32 byte_dest-1 er1 ; er1 contains dst address minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the add to memory. + cmp.b #30, @byte_dest + beq .Lb6 + fail +.Lb6: + +addx_w_imm16_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w #xx:16,Rd ; Addx with carry initially zero. + addx.w #0x505, r0 ; Immediate 16-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xaaaa r0 ; add result: 0xa5a5 + 0x505 + test_h_gr32 0xa5a5aaaa er0 ; add result: 0xa5a5 + 0x505 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_w_imm16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w #xx:16,Rd ; Addx with carry initially one. + set_carry_flag + addx.w #0x505, r0 ; Immediate 16-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xaaab r0 ; add result: 0xa5a5 + 0x505 + 1 + test_h_gr32 0xa5a5aaab er0 ; add result: 0xa5a5 + 0x505 + 1 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_w_imm16_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w #xx:16,@eRd ; Addx to register indirect + mov #word_dest, er0 + addx.w #0x505, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 word_dest er0 ; er0 still contains address + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.w #0x505, @word_dest + beq .Lw1 + fail +.Lw1: + +addx_w_imm16_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w #xx:16,@eRd- ; Addx to register post-decrement + mov #word_dest, er0 + addx.w #0x505, @er0- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 ; er0 contains address minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.w #0xa0a, @word_dest + beq .Lw2 + fail +.Lw2: + +addx_w_reg16_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w Rs,Rd ; addx with carry initially zero + mov.w #0x505, e0 + addx.w e0, r0 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x0505aaaa er0 ; add result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w Rs,Rd ; addx with carry initially one + mov.w #0x505, e0 + set_carry_flag + addx.w e0, r0 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x0505aaab er0 ; add result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_w_reg16_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w rs8,@eRd ; Addx to register indirect + mov #word_dest, er0 + mov.w #0x505, r1 + addx.w r1, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 word_dest er0 ; er0 still contains address + test_h_gr32 0xa5a50505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.w #0xf0f, @word_dest + beq .Lw3 + fail +.Lw3: + +addx_w_reg16_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w rs8,@eRd- ; Addx to register post-decrement + mov #word_dest, er0 + mov.w #0x505, r1 + addx.w r1, @er0- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 ; er0 contains address minus one + test_h_gr32 0xa5a50505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.w #0x1414, @word_dest + beq .Lw4 + fail +.Lw4: + +addx_w_rsind_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w @eRs,rd8 ; Addx from reg indirect to reg + mov #word_src, er0 + addx.w @er0, r1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src er0 ; er0 still contains address + test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_w_rspostdec_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w @eRs-,rd8 ; Addx to register post-decrement + mov #word_src, er0 + addx.w @er0-, r1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src-2 er0 ; er0 contains address minus one + test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_w_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w @eRs,rd8 ; Addx from reg indirect to reg + mov #word_src, er0 + mov #word_dest, er1 + addx.w @er0, @er1 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 word_src er0 ; er0 still contains src address + test_h_gr32 word_dest er1 ; er1 still contains dst address + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the add to memory. + cmp.w #0x1919, @word_dest + beq .Lw5 + fail +.Lw5: + +addx_w_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w @eRs-,rd8 ; Addx to register post-decrement + mov #word_src, er0 + mov #word_dest, er1 + addx.w @er0-, @er1- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 word_src-2 er0 ; er0 contains src address minus one + test_h_gr32 word_dest-2 er1 ; er1 contains dst address minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the add to memory. + cmp.w #0x1e1e, @word_dest + beq .Lw6 + fail +.Lw6: + +addx_l_imm32_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l #xx:32,Rd ; Addx with carry initially zero. + addx.l #0x50505, er0 ; Immediate 32-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0xa5aaaaaa er0 ; add result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_l_imm32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l #xx:32,Rd ; Addx with carry initially one. + set_carry_flag + addx.l #0x50505, er0 ; Immediate 32-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0xa5aaaaab er0 ; add result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_l_imm32_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l #xx:32,@eRd ; Addx to register indirect + mov #long_dest, er0 + addx.l #0x50505, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 long_dest er0 ; er0 still contains address + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.l #0x50505, @long_dest + beq .Ll1 + fail +.Ll1: + +addx_l_imm32_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l #xx:32,@eRd- ; Addx to register post-decrement + mov #long_dest, er0 + addx.l #0x50505, @er0- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 ; er0 contains address minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.l #0xa0a0a, @long_dest + beq .Ll2 + fail +.Ll2: + +addx_l_reg32_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l Rs,Rd ; addx with carry initially zero + mov.l #0x50505, er0 + addx.l er0, er1 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x50505 er0 ; add load + test_h_gr32 0xa5aaaaaa er1 ; add result: + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l Rs,Rd ; addx with carry initially one + mov.l #0x50505, er0 + set_carry_flag + addx.l er0, er1 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x50505 er0 ; add result: + test_h_gr32 0xa5aaaaab er1 ; add result: + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_l_reg32_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l rs8,@eRd ; Addx to register indirect + mov #long_dest, er0 + mov.l #0x50505, er1 + addx.l er1, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 long_dest er0 ; er0 still contains address + test_h_gr32 0x50505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.l #0xf0f0f, @long_dest + beq .Ll3 + fail +.Ll3: + +addx_l_reg32_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l rs8,@eRd- ; Addx to register post-decrement + mov #long_dest, er0 + mov.l #0x50505, er1 + addx.l er1, @er0- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 ; er0 contains address minus one + test_h_gr32 0x50505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.l #0x141414, @long_dest + beq .Ll4 + fail +.Ll4: + +addx_l_rsind_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l @eRs,rd8 ; Addx from reg indirect to reg + mov #long_src, er0 + addx.l @er0, er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src er0 ; er0 still contains address + test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_l_rspostdec_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l @eRs-,rd8 ; Addx to register post-decrement + mov #long_src, er0 + addx.l @er0-, er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src-4 er0 ; er0 contains address minus one + test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_l_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l @eRs,rd8 ; Addx from reg indirect to reg + mov #long_src, er0 + mov #long_dest, er1 + addx.l @er0, @er1 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 long_src er0 ; er0 still contains src address + test_h_gr32 long_dest er1 ; er1 still contains dst address + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the add to memory. + cmp.l #0x191919, @long_dest + beq .Ll5 + fail +.Ll5: + +addx_l_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l @eRs-,rd8 ; Addx to register post-decrement + mov #long_src, er0 + mov #long_dest, er1 + addx.l @er0-, @er1- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 long_src-4 er0 ; er0 contains src address minus one + test_h_gr32 long_dest-4 er1 ; er1 contains dst address minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the add to memory. + cmp.l #0x1e1e1e, @long_dest + beq .Ll6 + fail +.Ll6: +.endif + pass + + exit 0 diff --git a/sim/testsuite/h8300/allinsn.exp b/sim/testsuite/h8300/allinsn.exp new file mode 100644 index 0000000..68468f6 --- /dev/null +++ b/sim/testsuite/h8300/allinsn.exp @@ -0,0 +1,15 @@ +# Hitachi H8/300 (h, s, sx) simulator testsuite + +if {[istarget h8300*-*-*] || [istarget h8sx*-*-*]} then { + set all_machs "h8300 h8300h h8300s h8sx" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/h8300/andb.s b/sim/testsuite/h8300/andb.s new file mode 100644 index 0000000..8f11805 --- /dev/null +++ b/sim/testsuite/h8300/andb.s @@ -0,0 +1,527 @@ +# Hitachi H8 testcase 'and.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # and.b #xx:8, rd ; e rd xxxxxxxx + # and.b #xx:8, @erd ; 7 d rd ???? e ???? xxxxxxxx + # and.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx + # and.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx + # and.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx + # and.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx + # and.b rs, rd ; 1 6 rs rd + # and.b reg8, @erd ; 7 d rd ???? 1 6 rs ???? + # and.b reg8, @erd+ ; 0 1 7 9 8 rd 6 rs + # and.b reg8, @erd- ; 0 1 7 9 a rd 6 rs + # and.b reg8, @+erd ; 0 1 7 9 9 rd 6 rs + # and.b reg8, @-erd ; 0 1 7 9 b rd 6 rs + # + # andc #xx:8, ccr ; 0 6 xxxxxxxx + # andc #xx:8, exr ; 0 1 4 1 0 6 xxxxxxxx + + # Coming soon: + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0xa5 +post_byte: .byte 0 + + start + +and_b_imm8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.b #xx:8,Rd + and.b #0xaa, r0l ; Immediate 8-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a0 r0 ; and result: a5 & aa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a0 er0 ; and result: a5 & aa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +and_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@eRd + mov #byte_dest, er0 + and.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xe0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L1 + fail +.L1: + +and_b_imm8_rdpostinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@eRd+ + mov #byte_dest, er0 + and.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xe055 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L2 + fail +.L2: + +and_b_imm8_rdpostdec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@eRd- + mov #byte_dest, er0 + and.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xe0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L3 + fail +.L3: + +and_b_imm8_rdpreinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@+eRd + mov #pre_byte, er0 + and.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xe055 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L4 + fail +.L4: + +and_b_imm8_rdpredec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@-eRd + mov #post_byte, er0 + and.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xe0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L5 + fail +.L5: + +.endif ; h8sx + +and_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.b Rs,Rd + mov.b #0xaa, r0h + and.b r0h, r0l ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xaaa0 r0 ; and result: a5 & aa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5aaa0 er0 ; and result: a5 & aa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +and_b_reg8_rdind: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@eRd ; And to register indirect + mov #byte_dest, er0 + mov #0x55, r1l + and.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1690 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L6 + fail +.L6: + +and_b_reg8_rdpostinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@eRd+ ; And to register post-incr + mov #byte_dest, er0 + mov #0xaa, r1l + and.b r1l, @er0+ ; reg8 src, reg post-incr dest +;;; .word 0x0179 +;;; .word 0x8069 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L7 + fail +.L7: + +and_b_reg8_rdpostdec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@eRd- ; And to register post-decr + mov #byte_dest, er0 + mov #0x55, r1l + and.b r1l, @er0- ; reg8 src, reg post-decr dest +;;; .word 0x0179 +;;; .word 0xa069 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L8 + fail +.L8: + +and_b_reg8_rdpreinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@+eRd ; And to register post-incr + mov #pre_byte, er0 + mov #0xaa, r1l + and.b r1l, @+er0 ; reg8 src, reg post-incr dest +;;; .word 0x0179 +;;; .word 0x9069 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L9 + fail +.L9: + +and_b_reg8_rdpredec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@-eRd ; And to register post-decr + mov #post_byte, er0 + mov #0x55, r1l + and.b r1l, @-er0 ; reg8 src, reg post-decr dest +;;; .word 0x0179 +;;; .word 0xb069 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L10 + fail +.L10: +.endif ; h8sx + +andc_imm8_ccr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; andc #xx:8,ccr + set_ccr 0xff + + test_neg_set + andc #0xf7, ccr ; Immediate 8-bit operand (neg flag) + test_neg_clear + + test_zero_set + andc #0xfb, ccr ; Immediate 8-bit operand (zero flag) + test_zero_clear + + test_ovf_set + andc #0xfd, ccr ; Immediate 8-bit operand (overflow flag) + test_ovf_clear + + test_carry_set + andc #0xfe, ccr ; Immediate 8-bit operand (carry flag) + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +andc_imm8_exr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ldc #0xff, exr + stc exr, r0l + test_h_gr8 0x87, r0l + + ;; andc #xx:8,exr + set_ccr_zero + andc #0x7f, exr + test_cc_clear + stc exr, r0l + test_h_gr8 0x7, r0l + + andc #0x3, exr + stc exr, r0l + test_h_gr8 0x3, r0l + + andc #0x1, exr + stc exr, r0l + test_h_gr8 0x1, r0l + + andc #0x0, exr + stc exr, r0l + test_h_gr8 0x0, r0l + + test_h_gr32 0xa5a5a500 er0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; not h8300 or h8300h + + pass + + exit 0 diff --git a/sim/testsuite/h8300/andl.s b/sim/testsuite/h8300/andl.s new file mode 100644 index 0000000..ac09edc --- /dev/null +++ b/sim/testsuite/h8300/andl.s @@ -0,0 +1,77 @@ +# Hitachi H8 testcase 'and.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. +and_l_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.l #xx:16,Rd + and.l #0xaaaa:16, er0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0x0000a0a0 er0 ; and result: a5a5a5a5 & aaaa + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +and_l_imm32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.l #xx:32,Rd + and.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +and_l_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.l Rs,Rd + mov.l #0xaaaaaaaa, er1 + and.l er1, er0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa + test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/andw.s b/sim/testsuite/h8300/andw.s new file mode 100644 index 0000000..4267179 --- /dev/null +++ b/sim/testsuite/h8300/andw.s @@ -0,0 +1,61 @@ +# Hitachi H8 testcase 'and.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +and_w_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.w #xx:16,Rd + and.w #0xaaaa, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +and_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.w Rs,Rd + mov.w #0xaaaa, r1 + and.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa + test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa + test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/band.s b/sim/testsuite/h8300/band.s new file mode 100644 index 0000000..3c7e5a3 --- /dev/null +++ b/sim/testsuite/h8300/band.s @@ -0,0 +1,525 @@ +# Hitachi H8 testcase 'band', 'bor', 'bxor', 'bld', 'bst', 'bstz' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_src: .byte 0xa5 +byte_dst: .byte 0 + + start + +band_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; band xx:3, reg8 + band #7, r0l ; this should NOT set the carry flag. + test_cc_clear + band #6, r0l ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, r0l ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +band_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; band xx:3, ind + band #7, @r1 ; this should NOT set the carry flag. + test_cc_clear + band #6, @r1 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @r1 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @r1 ; this should clear the carry flag + test_cc_clear +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; band xx:3, ind + band #7, @er1 ; this should NOT set the carry flag. + test_cc_clear + band #6, @er1 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @er1 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @er1 ; this should clear the carry flag + test_cc_clear + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +band_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; band xx:3, aa:8 + band #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + band #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @0x20:8 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu > h8300h) +band_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; band xx:3, aa:16 + band #7, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + band #6, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @byte_src:16 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @byte_src:16 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +band_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; band xx:3, aa:32 + band #7, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + band #6, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @byte_src:32 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @byte_src:32 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. +.endif + +bor_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bor xx:3, reg8 + bor #6, r0l ; this should NOT set the carry flag. + test_cc_clear + + bor #7, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bor #7, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + bor #6, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bor_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bor xx:3, aa:8 + bor #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bor #7, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bor #7, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + bor #6, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bxor_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bxor xx:3, reg8 + bxor #6, r0l ; this should NOT set the carry flag. + test_cc_clear + + bxor #7, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bxor #6, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + bxor #7, r0l ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +bxor_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bxor xx:3, aa:8 + bxor #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bxor #7, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bxor #6, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + bxor #7, @0x20:8 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +bld_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bld xx:3, reg8 + bld #6, r0l ; this should NOT set the carry flag. + test_cc_clear + bld #7, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bld_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; bld xx:3, ind + bld #6, @r1 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @r1 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; bld xx:3, ind + bld #6, @er1 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @er1 ; this should NOT set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bld_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bld xx:3, aa:8 + bld #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu > h8300h) +bld_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; bld xx:3, aa:16 + bld #6, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @byte_src:16 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bld_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; bld xx:3, aa:32 + bld #6, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @byte_src:32 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. +.endif + +bst_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bst xx:3, reg8 + bst #7, r0l ; this should clear bit 7 + test_cc_clear + test_h_gr16 0xa525 r0 + + set_ccr_zero + orc #1, ccr ; set the carry flag + bst #6, r0l ; this should set bit 6 + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; Rest of general regs should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bst_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bst xx:3, aa:8 + bst #7, @0x20:8 ; this should clear bit 7 + test_cc_clear + mov.b @0x20, r0l + test_h_gr16 0xa525 r0 + + set_ccr_zero + orc #1, ccr ; set the carry flag + bst #6, @0x20:8 ; this should set bit 6 + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + mov.b @0x20, r0l + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +bstz_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bstz xx:3, aa:8 + bstz #7, @0x20:8 ; this should clear bit 7 + test_cc_clear + mov.b @0x20, r0l + test_h_gr16 0xa525 r0 + + set_ccr_zero + orc #4, ccr ; set the zero flag + bstz #6, @0x20:8 ; this should set bit 6 + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + mov.b @0x20, r0l + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +btst_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; btst xx:3, reg8 + btst #7, r0l ; this should NOT set the zero flag. + test_cc_clear + btst #6, r0l ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + + test_grs_a5a5 ; general registers should not be changed. + +btst_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; btst xx:3, ind + btst #7, @r1 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @r1 ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; btst xx:3, ind + btst #7, @er1 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @er1 ; this should NOT set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +btst_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; btst xx:3, aa:8 + btst #7, @0x20:8 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @0x20:8 ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu > h8300h) +btst_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; btst xx:3, aa:16 + btst #7, @byte_src:16 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @byte_src:16 ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + + test_grs_a5a5 ; general registers should not be changed. + +btst_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; btst xx:3, aa:32 + btst #7, @byte_src:32 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @byte_src:32 ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + + test_grs_a5a5 ; general registers should not be changed. +.endif + + pass + exit 0 diff --git a/sim/testsuite/h8300/bfld.s b/sim/testsuite/h8300/bfld.s new file mode 100644 index 0000000..7c55007 --- /dev/null +++ b/sim/testsuite/h8300/bfld.s @@ -0,0 +1,286 @@ +# Hitachi H8 testcase 'bfld', 'bfst' +# mach(): h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_src: .byte 0xa5 +byte_dst: .byte 0 + + start + +.if (sim_cpu == h8sx) +bfld_imm8_ind: + set_grs_a5a5 + mov #byte_src, er2 + + ;; bfld #xx:8, @ers, rd8 + set_ccr_zero + bfld #1, @er2, r1l + test_cc_clear + test_h_gr8 1 r1l + + set_ccr_zero + bfld #2, @er2, r1l + test_cc_clear + test_h_gr8 0 r1l + + set_ccr_zero + bfld #7, @er2, r1l + test_cc_clear + test_h_gr8 5 r1l + + set_ccr_zero + bfld #0x10, @er2, r1l + test_cc_clear + test_h_gr8 0 r1l + + set_ccr_zero + bfld #0x20, @er2, r1l + test_cc_clear + test_h_gr8 1 r1l + + set_ccr_zero + bfld #0xf0, @er2, r1l + test_cc_clear + test_h_gr8 0xa r1l + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 0xa5a5a50a er1 + test_h_gr32 byte_src er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + +bfld_imm8_abs16: + set_grs_a5a5 + + ;; bfld #xx:8, @aa:16, rd8 + set_ccr_zero + bfld #0x80, @byte_src:16, r1l + test_cc_clear + test_h_gr8 1 r1l + + set_ccr_zero + bfld #0x40, @byte_src:16, r1l + test_cc_clear + test_h_gr8 0 r1l + + set_ccr_zero + bfld #0xe0, @byte_src:16, r1l + test_cc_clear + test_h_gr8 0x5 r1l + + set_ccr_zero + bfld #0x3c, @byte_src:16, r1l + test_cc_clear + test_h_gr8 9 r1l + + set_ccr_zero + bfld #0xfe, @byte_src:16, r1l + test_cc_clear + test_h_gr8 0x52 r1l + + set_ccr_zero + bfld #0, @byte_src:16, r1l + test_cc_clear + test_h_gr8 0 r1l + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 0xa5a5a500 er1 + test_h_gr32 0xa5a5a5a5 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + +bfst_imm8_ind: + set_grs_a5a5 + mov #byte_dst, er2 + + ;; bfst rd8, #xx:8, @ers + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #1, @er2 +;;; .word 0x7d20 +;;; .word 0xf901 + + test_cc_clear + cmp.b #1, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #2, @er2 +;;; .word 0x7d20 +;;; .word 0xf902 + + test_cc_clear + cmp.b #2, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #7, @er2 +;;; .word 0x7d20 +;;; .word 0xf907 + + test_cc_clear + cmp.b #5, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0x10, @er2 +;;; .word 0x7d20 +;;; .word 0xf910 + + test_cc_clear + cmp.b #0x10, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0x20, @er2 +;;; .word 0x7d20 +;;; .word 0xf920 + + test_cc_clear + cmp.b #0x20, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0xf0, @er2 +;;; .word 0x7d20 +;;; .word 0xf9f0 + + test_cc_clear + cmp.b #0x50, @byte_dst + bne fail1:16 + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 0xa5a5a5a5 er1 + test_h_gr32 byte_dst er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + +bfst_imm8_abs32: + set_grs_a5a5 + + ;; bfst #xx:8, @aa:32, rd8 + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0x80, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf980 + + test_cc_clear + cmp.b #0x80, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0x40, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf940 + + test_cc_clear + cmp.b #0x40, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0xe0, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf9e0 + + test_cc_clear + cmp.b #0xa0, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0x3c, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf93c + + test_cc_clear + cmp.b #0x14, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0xfe, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf9fe + + test_cc_clear + cmp.b #0x4a, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf900 + + test_cc_clear + cmp.b #0x0, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0x38, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf938 + + test_cc_clear + cmp.b #0x28, @byte_dst + bne fail1:16 + + ;; + ;; Now let's do one in which the bits in the destination + ;; are appropriately combined with the bits in the source. + ;; + + mov.b #0xc3, @byte_dst + set_ccr_zero + bfst r1l, #0x3c, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf93c + + test_cc_clear + cmp.b #0xd7, @byte_dst + bne fail1:16 + + test_grs_a5a5 + +.endif + pass + + exit 0 + +fail1: fail + diff --git a/sim/testsuite/h8300/biand.s b/sim/testsuite/h8300/biand.s new file mode 100644 index 0000000..c4cf285 --- /dev/null +++ b/sim/testsuite/h8300/biand.s @@ -0,0 +1,473 @@ +# Hitachi H8 testcase 'biand', 'bior', 'bixor', 'bild', 'bist', 'bistz' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_src: .byte 0xa5 +byte_dst: .byte 0 + + start + +biand_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; biand xx:3, reg8 + biand #6, r0l ; this should NOT set the carry flag. + test_cc_clear + biand #7, r0l ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, r0l ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +biand_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; biand xx:3, ind + biand #6, @r1 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @r1 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @r1 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @r1 ; this should clear the carry flag + test_cc_clear +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; biand xx:3, ind + biand #6, @er1 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @er1 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @er1 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @er1 ; this should clear the carry flag + test_cc_clear + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +biand_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; biand xx:3, aa:8 + biand #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @0x20:8 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu > h8300h) +biand_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; biand xx:3, aa:16 + biand #6, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @byte_src:16 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @byte_src:16 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +biand_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; biand xx:3, aa:32 + biand #6, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @byte_src:32 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @byte_src:32 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. +.endif + +bior_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bior xx:3, reg8 + bior #7, r0l ; this should NOT set the carry flag. + test_cc_clear + + bior #6, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bior #6, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + bior #7, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bior_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bior xx:3, aa:8 + bior #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bior #6, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bior #6, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + bior #7, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bixor_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bixor xx:3, reg8 + bixor #7, r0l ; this should NOT set the carry flag. + test_cc_clear + + bixor #6, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bixor #7, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + bixor #6, r0l ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +bixor_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bixor xx:3, aa:8 + bixor #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bixor #6, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bixor #7, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + bixor #6, @0x20:8 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +bild_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bild xx:3, reg8 + bild #7, r0l ; this should NOT set the carry flag. + test_cc_clear + bild #6, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bild_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; bild xx:3, ind + bild #7, @r1 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @r1 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; bild xx:3, ind + bild #7, @er1 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @er1 ; this should NOT set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bild_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bild xx:3, aa:8 + bild #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu > h8300h) +bild_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; bild xx:3, aa:16 + bild #7, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @byte_src:16 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bild_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; bild xx:3, aa:32 + bild #7, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @byte_src:32 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. +.endif + +bist_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bist xx:3, reg8 + bist #6, r0l ; this should set bit 6 + test_cc_clear + test_h_gr16 0xa5e5 r0 + + set_ccr_zero + orc #1, ccr ; set the carry flag + bist #7, r0l ; this should clear bit 7 + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; Rest of general regs should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bist_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bist xx:3, aa:8 + bist #6, @0x20:8 ; this should set bit 6 + test_cc_clear + mov.b @0x20, r0l + test_h_gr16 0xa5e5 r0 + + set_ccr_zero + orc #1, ccr ; set the carry flag + bist #7, @0x20:8 ; this should clear bit 7 + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + mov.b @0x20, r0l + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +bistz_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bistz xx:3, aa:8 + bistz #6, @0x20:8 ; this should set bit 6 + test_cc_clear + mov.b @0x20, r0l + test_h_gr16 0xa5e5 r0 + + set_ccr_zero + orc #4, ccr ; set the zero flag + bistz #7, @0x20:8 ; this should clear bit 7 + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + mov.b @0x20, r0l + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +bnot_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bnot xx:3, reg8 + bnot #7, r0l + test_cc_clear + test_h_gr16 0xa525 r0 + set_ccr_zero + bnot #6, r0l + test_cc_clear + test_h_gr16 0xa565 r0 + set_ccr_zero + bnot #5, r0l + test_cc_clear + test_h_gr16 0xa545 r0 + set_ccr_zero + bnot #4, r0l + test_cc_clear + test_h_gr16 0xa555 r0 + set_ccr_zero + + bnot #4, r0l + bnot #5, r0l + bnot #6, r0l + bnot #7, r0l + test_cc_clear + test_grs_a5a5 ; general registers should not be changed. + +bnot_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bnot xx:3, aa:8 + bnot #7, @0x20:8 + bnot #6, @0x20:8 + bnot #5, @0x20:8 + bnot #4, @0x20:8 + test_cc_clear + test_grs_a5a5 + mov @0x20, r0l + test_h_gr16 0xa555 r0 + + pass + exit 0 diff --git a/sim/testsuite/h8300/bra.s b/sim/testsuite/h8300/bra.s new file mode 100644 index 0000000..2ec10dc --- /dev/null +++ b/sim/testsuite/h8300/bra.s @@ -0,0 +1,165 @@ +# Hitachi H8 testcase 'bra' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start +.if (sim_cpu == h8sx) + .data + .align 4 +disp8: .long tgt_reg8 +disp16: .long tgt_reg16 +disp32: .long tgt_reg32 +dslot: .byte 0 + .text +.endif + +bra_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; bra dd:8 ; 8-bit displacement + bra tgt_8:8 +;;; .word 0x40xx ; where "xx" is tgt_8 - '.'. + fail + +tgt_8: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; not available in h8/300 mode +bra_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; bra dd:16 ; 16-bit displacement + bra tgt_24:16 ; NOTE: hard-coded to avoid relaxing. +;;; .word 0x5800 +;;; .word tgt_24 - . + fail + +tgt_24: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu == h8sx) +bra_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; bra rn.b ; 8-bit register indirect + sub.l #src8, @disp8 + mov.l @disp8, er5 + bra r5l.b +;;; .word 0x5955 +src8: fail + +tgt_reg8: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 +;;; test_h_gr32 tgt_reg8 er5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bra_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; bra rn.w ; 16-bit register indirect + sub.l #src16, @disp16 + mov.l @disp16, er5 + bra r5.w +;;; .word 0x5956 +src16: fail + +tgt_reg16: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 +;;; test_h_gr32 tgt_reg16 er5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bra_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; bra ern ; 32-bit register indirect + sub.l #src32, @disp32 + mov.l @disp32, er5 + bra er5.l +;;; .word 0x5957 +src32: fail + +tgt_reg32: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 +;;; test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bra_s: set_grs_a5a5 + set_ccr_zero + + bra/s tgt_post_delay +;;; .word 0x4017 + ;; The following instruction is in the delay slot, and should execute. + mov.b #1, @dslot + ;; After this, the next instructions should not execute. + fail + +tgt_post_delay: + test_cc_clear + cmp.b #0, @dslot ; Should be non-zero if delay slot executed. + bne dslot_ok + fail + +dslot_ok: + test_gr_a5a5 0 ; Make sure all general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + + pass + exit 0 + + \ No newline at end of file diff --git a/sim/testsuite/h8300/brabc.s b/sim/testsuite/h8300/brabc.s new file mode 100644 index 0000000..b9a08ea --- /dev/null +++ b/sim/testsuite/h8300/brabc.s @@ -0,0 +1,116 @@ +# Hitachi H8 testcase 'bra/bc' +# mach(): h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_src: .byte 0xa5 + + start + +.if (sim_cpu == h8sx) +brabc_ind_disp8: + set_grs_a5a5 + mov #byte_src, er1 + set_ccr_zero + ;; bra/bc xx:3, @erd, disp8 + bra/bc #1, @er1, .Lpass1:8 +;;; .word 0x7c10 +;;; .word 0x4110 + fail +.Lpass1: + bra/bc #2, @er1, .Lfail1:8 +;;; .word 0x7c10 +;;; .word 0x4202 + bra .Lpass2 +.Lfail1: + fail +.Lpass2: + test_cc_clear + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 byte_src er1 + test_h_gr32 0xa5a5a5a5 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + +brabc_abs8_disp16: + set_grs_a5a5 + mov.b #0xa5, @0x20:32 + set_ccr_zero + ;; bra/bc xx:3, @aa:8, disp16 + bra/bc #1, @0x20:8, .Lpass3:16 + fail +.Lpass3: + bra/bc #2, @0x20:8, Lfail:16 + + test_cc_clear + test_grs_a5a5 + +brabc_abs16_disp16: + set_grs_a5a5 + set_ccr_zero + ;; bra/bc xx:3, @aa:16, disp16 + bra/bc #1, @byte_src:16, .Lpass5:16 + fail +.Lpass5: + bra/bc #2, @byte_src:16, Lfail:16 + + test_cc_clear + test_grs_a5a5 + +brabs_ind_disp8: + set_grs_a5a5 + mov #byte_src, er1 + set_ccr_zero + ;; bra/bs xx:3, @erd, disp8 + bra/bs #2, @er1, .Lpass7:8 +;;; .word 0x7c10 +;;; .word 0x4a10 + fail +.Lpass7: + bra/bs #1, @er1, .Lfail3:8 +;;; .word 0x7c10 +;;; .word 0x4902 + bra .Lpass8 +.Lfail3: + fail +.Lpass8: + test_cc_clear + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 byte_src er1 + test_h_gr32 0xa5a5a5a5 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + +brabs_abs32_disp16: + set_grs_a5a5 + set_ccr_zero + ;; bra/bs xx:3, @aa:32, disp16 + bra/bs #2, @byte_src:32, .Lpass9:16 + fail +.Lpass9: + bra/bs #1, @byte_src:32, Lfail:16 + + test_cc_clear + test_grs_a5a5 + +.endif + + pass + + exit 0 + +Lfail: fail diff --git a/sim/testsuite/h8300/bset.s b/sim/testsuite/h8300/bset.s new file mode 100644 index 0000000..0e16fc1 --- /dev/null +++ b/sim/testsuite/h8300/bset.s @@ -0,0 +1,890 @@ +# Hitachi H8 testcase 'bset', 'bclr' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # + # bset xx:3, rd8 ; 7 0 ?xxx rd8 + # bclr xx:3, rd8 ; 7 2 ?xxx rd8 + # bset xx:3, @erd ; 7 d 0rd ???? 7 0 ?xxx ???? + # bclr xx:3, @erd ; 7 d 0rd ???? 7 2 ?xxx ???? + # bset xx:3, @abs16 ; 6 a 1 1??? aa:16 7 0 ?xxx ???? + # bclr xx:3, @abs16 ; 6 a 1 1??? aa:16 7 2 ?xxx ???? + # bset reg8, rd8 ; 6 0 rs8 rd8 + # bclr reg8, rd8 ; 6 2 rs8 rd8 + # bset reg8, @erd ; 7 d 0rd ???? 6 0 rs8 ???? + # bclr reg8, @erd ; 7 d 0rd ???? 6 2 rs8 ???? + # bset reg8, @abs32 ; 6 a 3 1??? aa:32 6 0 rs8 ???? + # bclr reg8, @abs32 ; 6 a 3 1??? aa:32 6 2 rs8 ???? + # + # bset/eq xx:3, rd8 + # bclr/eq xx:3, rd8 + # bset/ne xx:3, rd8 + # bclr/ne xx:3, rd8 + + .data +byte_dst: .byte 0 + + start + +bset_imm3_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset xx:3, rd8 + mov #0, r1l + set_ccr_zero + bset #0, r1l + test_cc_clear + test_h_gr8 1 r1l + + set_ccr_zero + bset #1, r1l + test_cc_clear + test_h_gr8 3 r1l + + set_ccr_zero + bset #2, r1l + test_cc_clear + test_h_gr8 7 r1l + + set_ccr_zero + bset #3, r1l + test_cc_clear + test_h_gr8 15 r1l + + set_ccr_zero + bset #4, r1l + test_cc_clear + test_h_gr8 31 r1l + + set_ccr_zero + bset #5, r1l + test_cc_clear + test_h_gr8 63 r1l + + set_ccr_zero + bset #6, r1l + test_cc_clear + test_h_gr8 127 r1l + + set_ccr_zero + bset #7, r1l + test_cc_clear + test_h_gr8 255 r1l + +.if (sim_cpu == h8300) + test_h_gr16 0xa5ff, r1 +.else + test_h_gr32 0xa5a5a5ff er1 +.endif + +bclr_imm3_reg8: + set_ccr_zero + bclr #7, r1l + test_cc_clear + test_h_gr8 127 r1l + + set_ccr_zero + bclr #6, r1l + test_cc_clear + test_h_gr8 63 r1l + + set_ccr_zero + bclr #5, r1l + test_cc_clear + test_h_gr8 31 r1l + + set_ccr_zero + bclr #4, r1l + test_cc_clear + test_h_gr8 15 r1l + + set_ccr_zero + bclr #3, r1l + test_cc_clear + test_h_gr8 7 r1l + + set_ccr_zero + bclr #2, r1l + test_cc_clear + test_h_gr8 3 r1l + + set_ccr_zero + bclr #1, r1l + test_cc_clear + test_h_gr8 1 r1l + + set_ccr_zero + bclr #0, r1l + test_cc_clear + test_h_gr8 0 r1l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed +.if (sim_cpu == h8300) + test_h_gr16 0xa500 r1 +.else + test_h_gr32 0xa5a5a500 er1 +.endif + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) +bset_imm3_ind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset xx:3, @erd + mov #byte_dst, er1 + set_ccr_zero + bset #0, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 1 r2l + + set_ccr_zero + bset #1, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 3 r2l + + set_ccr_zero + bset #2, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 7 r2l + + set_ccr_zero + bset #3, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 15 r2l + + set_ccr_zero + bset #4, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 31 r2l + + set_ccr_zero + bset #5, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 63 r2l + + set_ccr_zero + bset #6, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 127 r2l + + set_ccr_zero + bset #7, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 255 r2l + +.if (sim_cpu == h8300) + test_h_gr16 0xa5ff r2 +.else + test_h_gr32 0xa5a5a5ff er2 +.endif + +bclr_imm3_ind: + set_ccr_zero + bclr #7, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 127 r2l + + set_ccr_zero + bclr #6, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 63 r2l + + set_ccr_zero + bclr #5, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 31 r2l + + set_ccr_zero + bclr #4, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 15 r2l + + set_ccr_zero + bclr #3, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 7 r2l + + set_ccr_zero + bclr #2, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 3 r2l + + set_ccr_zero + bclr #1, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 1 r2l + + set_ccr_zero + bclr #0, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 0 r2l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed +.if (sim_cpu == h8300) + test_h_gr16 byte_dst r1 + test_h_gr16 0xa500 r2 +.else + test_h_gr32 byte_dst er1 + test_h_gr32 0xa5a5a500 er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu > h8300h) +bset_imm3_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset xx:3, @aa:16 + set_ccr_zero + bset #0, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 1 r2l + + set_ccr_zero + bset #1, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 3 r2l + + set_ccr_zero + bset #2, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 7 r2l + + set_ccr_zero + bset #3, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 15 r2l + + set_ccr_zero + bset #4, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 31 r2l + + set_ccr_zero + bset #5, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 63 r2l + + set_ccr_zero + bset #6, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 127 r2l + + set_ccr_zero + bset #7, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 255 r2l + +.if (sim_cpu == h8300) + test_h_gr16 0xa5ff r2 +.else + test_h_gr32 0xa5a5a5ff er2 +.endif + +bclr_imm3_abs16: + set_ccr_zero + bclr #7, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 127 r2l + + set_ccr_zero + bclr #6, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 63 r2l + + set_ccr_zero + bclr #5, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 31 r2l + + set_ccr_zero + bclr #4, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 15 r2l + + set_ccr_zero + bclr #3, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 7 r2l + + set_ccr_zero + bclr #2, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 3 r2l + + set_ccr_zero + bclr #1, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 1 r2l + + set_ccr_zero + bclr #0, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 0 r2l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 +.if (sim_cpu == h8300) + test_h_gr16 0xa500 r2 +.else + test_h_gr32 0xa5a5a500 er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif +.endif + +bset_rs8_rd8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset rs8, rd8 + mov #0, r1h + mov #0, r1l + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 1 r1l + + mov #1, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 3 r1l + + mov #2, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 7 r1l + + mov #3, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 15 r1l + + mov #4, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 31 r1l + + mov #5, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 63 r1l + + mov #6, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 127 r1l + + mov #7, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 255 r1l + +.if (sim_cpu == h8300) + test_h_gr16 0x07ff, r1 +.else + test_h_gr32 0xa5a507ff er1 +.endif + +bclr_rs8_rd8: + mov #7, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 127 r1l + + mov #6, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 63 r1l + + mov #5, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 31 r1l + + mov #4, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 15 r1l + + mov #3, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 7 r1l + + mov #2, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 3 r1l + + mov #1, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 1 r1l + + mov #0, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 0 r1l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed +.if (sim_cpu == h8300) + test_h_gr16 0x0000 r1 +.else + test_h_gr32 0xa5a50000 er1 +.endif + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) +bset_rs8_ind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset rs8, @erd + mov #byte_dst, er1 + mov #0, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 1 r2l + + mov #1, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 3 r2l + + mov #2, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 7 r2l + + mov #3, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 15 r2l + + mov #4, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 31 r2l + + mov #5, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 63 r2l + + mov #6, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 127 r2l + + mov #7, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 255 r2l + +.if (sim_cpu == h8300) + test_h_gr16 0x07ff r2 +.else + test_h_gr32 0xa5a507ff er2 +.endif + +bclr_rs8_ind: + mov #7, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 127 r2l + + mov #6, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 63 r2l + + mov #5, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 31 r2l + + mov #4, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 15 r2l + + mov #3, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 7 r2l + + mov #2, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 3 r2l + + mov #1, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 1 r2l + + mov #0, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 0 r2l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed +.if (sim_cpu == h8300) + test_h_gr16 byte_dst r1 + test_h_gr16 0x0000 r2 +.else + test_h_gr32 byte_dst er1 + test_h_gr32 0xa5a50000 er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu > h8300h) +bset_rs8_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset rs8, @aa:32 + mov #0, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 1 r2l + + mov #1, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 3 r2l + + mov #2, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 7 r2l + + mov #3, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 15 r2l + + mov #4, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 31 r2l + + mov #5, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 63 r2l + + mov #6, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 127 r2l + + mov #7, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 255 r2l + +.if (sim_cpu == h8300) + test_h_gr16 0x07ff r2 +.else + test_h_gr32 0xa5a507ff er2 +.endif + +bclr_rs8_abs32: + mov #7, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 127 r2l + + mov #6, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 63 r2l + + mov #5, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 31 r2l + + mov #4, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 15 r2l + + mov #3, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 7 r2l + + mov #2, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 3 r2l + + mov #1, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 1 r2l + + mov #0, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 0 r2l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 +.if (sim_cpu == h8300) + test_h_gr16 0x0000 r2 +.else + test_h_gr32 0xa5a50000 er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif +.endif + +.if (sim_cpu == h8sx) +bset_eq_imm3_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset/eq xx:3, rd8 + mov #0, @byte_dst + set_ccr_zero + bset/eq #0, @byte_dst:16 ; Zero is clear, should have no effect. + test_cc_clear + mov @byte_dst, r1l + test_h_gr8 0 r1l + + set_ccr_zero + orc #4, ccr ; Set zero flag + bset/eq #0, @byte_dst:16 ; Zero is set: operation should succeed. + + test_neg_clear + test_zero_set + test_ovf_clear + test_carry_clear + + mov @byte_dst, r1l + test_h_gr8 1 r1l + +bclr_eq_imm3_abs32: + mov #1, @byte_dst + set_ccr_zero + bclr/eq #0, @byte_dst:32 ; Zero is clear, should have no effect. + test_cc_clear + mov @byte_dst, r1l + test_h_gr8 1 r1l + + set_ccr_zero + orc #4, ccr ; Set zero flag + bclr/eq #0, @byte_dst:32 ; Zero is set: operation should succeed. + test_neg_clear + test_zero_set + test_ovf_clear + test_carry_clear + mov @byte_dst, r1l + test_h_gr8 0 r1l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xa5a5a500 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bset_ne_imm3_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset/ne xx:3, aa:16 + mov #0, @byte_dst + set_ccr_zero + orc #4, ccr ; Set zero flag + bset/ne #0, @byte_dst:16 ; Zero is set; should have no effect. + test_zero_set + test_neg_clear + test_ovf_clear + test_carry_clear + mov @byte_dst, r1l + test_h_gr8 0 r1l + + set_ccr_zero + bset/ne #0, @byte_dst:16 ; Zero is clear: operation should succeed. + test_cc_clear + mov @byte_dst, r1l + test_h_gr8 1 r1l + +bclr_ne_imm3_abs32: + mov #1, @byte_dst + set_ccr_zero + orc #4, ccr ; Set zero flag + ;; bclr/ne xx:3, aa:16 + bclr/ne #0, @byte_dst:32 ; Zero is set, should have no effect. + test_neg_clear + test_zero_set + test_ovf_clear + test_carry_clear + mov @byte_dst, r1l + test_h_gr8 1 r1l + + set_ccr_zero + bclr/ne #0, @byte_dst:32 ; Zero is clear: operation should succeed. + test_cc_clear + mov @byte_dst, r1l + test_h_gr8 0 r1l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xa5a5a500 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + + pass + exit 0 diff --git a/sim/testsuite/h8300/cmpb.s b/sim/testsuite/h8300/cmpb.s new file mode 100644 index 0000000..1a4f23c --- /dev/null +++ b/sim/testsuite/h8300/cmpb.s @@ -0,0 +1,1086 @@ +# Hitachi H8 testcase 'cmp.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # cmp.b #xx:8, rd ; a rd xxxxxxxx + # cmp.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx + # cmp.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx + # cmp.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx + # cmp.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx + # cmp.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx + # cmp.b rs, rd ; 1 c rs rd + # cmp.b reg8, @erd ; 7 d rd ???? 1 c rs ???? + # cmp.b reg8, @erd+ ; 0 1 7 9 8 rd 2 rs + # cmp.b reg8, @erd- ; 0 1 7 9 a rd 2 rs + # cmp.b reg8, @+erd ; 0 1 7 9 9 rd 2 rs + # cmp.b reg8, @-erd ; 0 1 7 9 b rd 2 rs + # cmp.b rsind, rdind ; 7 c 0rs 5 0 ?rd 2 ???? + # cmp.b rspostinc, rdpostinc ; 0 1 7 4 6 c 0rs c 8 ?rd 2 ???? + # cmp.b rspostdec, rdpostdec ; 0 1 7 6 6 c 0rs c a ?rd 2 ???? + # cmp.b rspreinc, rdpreinc ; 0 1 7 5 6 c 0rs c 9 ?rd 2 ???? + # cmp.b rspredec, rdpredec ; 0 1 7 7 6 c 0rs c b ?rd 2 ???? + # cmp.b disp2, disp2 ; 0 1 7 01dd:2 6 8 0rs c 00dd:2 ?rd 2 ???? + # cmp.b disp16, disp16 ; 0 1 7 4 6 e 0rs c dd:16 c 0rd 2 ???? dd:16 + # cmp.b disp32, disp32 ; 7 8 0rs 4 6 a 2 c dd:32 c 1rd 2 ???? dd:32 + # cmp.b indexb16, indexb16 ; 0 1 7 5 6 e 0rs c dd:16 d 0rd 2 ???? dd:16 + # cmp.b indexw16, indexw16 ; 0 1 7 6 6 e 0rs c dd:16 e 0rd 2 ???? dd:16 + # cmp.b indexl16, indexl16 ; 0 1 7 7 6 e 0rs c dd:16 f 0rd 2 ???? dd:16 + # cmp.b indexb32, indexb32 ; 7 8 0rs 5 6 a 2 c dd:32 d 1rd 2 ???? dd:32 + # cmp.b indexw32, indexw32 ; 7 8 0rs 6 6 a 2 c dd:32 e 1rd 2 ???? dd:32 + # cmp.b indexl32, indexl32 ; 7 8 0rs 7 6 a 2 c dd:32 f 1rd 2 ???? dd:32 + # cmp.b abs16, abs16 ; 6 a 1 5 aa:16 4 0??? 2 ???? aa:16 + # cmp.b abs32, abs32 ; 6 a 3 5 aa:32 4 1??? 2 ???? aa:32 + # + + # Coming soon: + + # ... + +.data +byte_src: .byte 0x5a +pre_byte: .byte 0 +byte_dst: .byte 0xa5 +post_byte: .byte 0 + + start + +cmp_b_imm8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.b #xx:8,Rd + cmp.b #0xa5, r0l ; Immediate 8-bit src, reg8 dest + beq .Leq1 + fail +.Leq1: cmp.b #0xa6, r0l + blt .Llt1 + fail +.Llt1: cmp.b #0xa4, r0l + bgt .Lgt1 + fail +.Lgt1: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a5 r0 ; r0 unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +cmp_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@eRd + mov #byte_dst, er0 + cmp.b #0xa5:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xa0a5 + beq .Leq2 + fail +.Leq2: set_ccr_zero + cmp.b #0xa6, @er0 +;;; .word 0x7d00 +;;; .word 0xa0a6 + blt .Llt2 + fail +.Llt2: set_ccr_zero + cmp.b #0xa4, @er0 +;;; .word 0x7d00 +;;; .word 0xa0a4 + bgt .Lgt2 + fail +.Lgt2: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L2 + fail +.L2: + +cmp_b_imm8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@eRd+ + mov #byte_dst, er0 + cmp.b #0xa5:8, @er0+ ; Immediate 8-bit src, reg postinc dst +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xa0a5 + beq .Leq3 + fail +.Leq3: test_h_gr32 post_byte er0 ; er0 contains address plus one + mov #byte_dst, er0 + set_ccr_zero + cmp.b #0xa6, @er0+ +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xa0a6 + blt .Llt3 + fail +.Llt3: test_h_gr32 post_byte er0 ; er0 contains address plus one + mov #byte_dst, er0 + set_ccr_zero + cmp.b #0xa4, @er0+ +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xa0a4 + bgt .Lgt3 + fail +.Lgt3: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L3 + fail +.L3: + +cmp_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@eRd- + mov #byte_dst, er0 + cmp.b #0xa5:8, @er0- ; Immediate 8-bit src, reg postdec dst +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xa0a5 + beq .Leq4 + fail +.Leq4: test_h_gr32 pre_byte er0 ; er0 contains address minus one + mov #byte_dst, er0 + set_ccr_zero + cmp.b #0xa6, @er0- +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xa0a6 + blt .Llt4 + fail +.Llt4: test_h_gr32 pre_byte er0 ; er0 contains address minus one + mov #byte_dst, er0 + set_ccr_zero + cmp.b #0xa4, @er0- +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xa0a4 + bgt .Lgt4 + fail +.Lgt4: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L4 + fail +.L4: + +cmp_b_imm8_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@+eRd + mov #pre_byte, er0 + cmp.b #0xa5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xa0a5 + beq .Leq5 + fail +.Leq5: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #pre_byte, er0 + set_ccr_zero + cmp.b #0xa6, @+er0 +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xa0a6 + blt .Llt5 + fail +.Llt5: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #pre_byte, er0 + set_ccr_zero + cmp.b #0xa4, @+er0 +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xa0a4 + bgt .Lgt5 + fail +.Lgt5: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L5 + fail +.L5: + +cmp_b_imm8_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@-eRd + mov #post_byte, er0 + cmp.b #0xa5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xa0a5 + beq .Leq6 + fail +.Leq6: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #post_byte, er0 + set_ccr_zero + cmp.b #0xa6, @-er0 +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xa0a6 + blt .Llt6 + fail +.Llt6: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #post_byte, er0 + set_ccr_zero + cmp.b #0xa4, @-er0 +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xa0a4 + bgt .Lgt6 + fail +.Lgt6: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L6 + fail +.L6: + + +.endif + +cmp_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.b Rs,Rd + mov.b #0xa5, r0h + cmp.b r0h, r0l ; Reg8 src, reg8 dst + beq .Leq7 + fail +.Leq7: mov.b #0xa6, r0h + cmp.b r0h, r0l + blt .Llt7 + fail +.Llt7: mov.b #0xa4, r0h + cmp.b r0h, r0l + bgt .Lgt7 + fail +.Lgt7: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa4a5 r0 ; r0l unchanged. +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a4a5 er0 ; r0l unchanged +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +cmp_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b rs8,@eRd ; cmp reg8 to register indirect + mov #byte_dst, er0 + mov #0xa5, r1l + cmp.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1c90 + beq .Leq8 + fail +.Leq8: set_ccr_zero + mov #0xa6, r1l + cmp.b r1l, @er0 +;;; .word 0x7d00 +;;; .word 0x1c90 + blt .Llt8 + fail +.Llt8: set_ccr_zero + mov #0xa4, r1l + cmp.b r1l, @er0 +;;; .word 0x7d00 +;;; .word 0x1c90 + bgt .Lgt8 + fail +.Lgt8: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 still contains address + test_h_gr32 0xa5a5a5a4 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (no change). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L8 + fail +.L8: + +cmp_b_reg8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b reg8,@eRd+ + mov #byte_dst, er0 + mov #0xa5, r1l + cmp.b r1l, @er0+ ; Immediate 8-bit src, reg post-incr dst +;;; .word 0x0179 +;;; .word 0x8029 + beq .Leq9 + fail +.Leq9: test_h_gr32 post_byte er0 ; er0 contains address plus one + mov #byte_dst er0 + mov #0xa6, r1l + set_ccr_zero + cmp.b r1l, @er0+ +;;; .word 0x0179 +;;; .word 0x8029 + blt .Llt9 + fail +.Llt9: test_h_gr32 post_byte er0 ; er0 contains address plus one + mov #byte_dst er0 + mov #0xa4, r1l + set_ccr_zero + cmp.b r1l, @er0+ +;;; .word 0x0179 +;;; .word 0x8029 + bgt .Lgt9 + fail +.Lgt9: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L9 + fail +.L9: + +cmp_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b reg8,@eRd- + mov #byte_dst, er0 + mov #0xa5, r1l + cmp.b r1l, @er0- ; Immediate 8-bit src, reg postdec dst +;;; .word 0x0179 +;;; .word 0xa029 + beq .Leq10 + fail +.Leq10: test_h_gr32 pre_byte er0 ; er0 contains address minus one + mov #byte_dst er0 + mov #0xa6, r1l + set_ccr_zero + cmp.b r1l, @er0- +;;; .word 0x0179 +;;; .word 0xa029 + blt .Llt10 + fail +.Llt10: test_h_gr32 pre_byte er0 ; er0 contains address minus one + mov #byte_dst er0 + mov #0xa4, r1l + set_ccr_zero + cmp.b r1l, @er0- +;;; .word 0x0179 +;;; .word 0xa029 + bgt .Lgt10 + fail +.Lgt10: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L10 + fail +.L10: + +cmp_b_reg8_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b reg8,@+eRd + mov #pre_byte, er0 + mov #0xa5, r1l + cmp.b r1l, @+er0 ; Immediate 8-bit src, reg post-incr dst +;;; .word 0x0179 +;;; .word 0x9029 + beq .Leq11 + fail +.Leq11: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #pre_byte er0 + mov #0xa6, r1l + set_ccr_zero + cmp.b r1l, @+er0 +;;; .word 0x0179 +;;; .word 0x9029 + blt .Llt11 + fail +.Llt11: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #pre_byte er0 + mov #0xa4, r1l + set_ccr_zero + cmp.b r1l, @+er0 +;;; .word 0x0179 +;;; .word 0x9029 + bgt .Lgt11 + fail +.Lgt11: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 contains destination address + test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L11 + fail +.L11: + +cmp_b_reg8_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b reg8,@-eRd + mov #post_byte, er0 + mov #0xa5, r1l + cmp.b r1l, @-er0 ; Immediate 8-bit src, reg postdec dst +;;; .word 0x0179 +;;; .word 0xb029 + beq .Leq12 + fail +.Leq12: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #post_byte er0 + mov #0xa6, r1l + set_ccr_zero + cmp.b r1l, @-er0 +;;; .word 0x0179 +;;; .word 0xb029 + blt .Llt12 + fail +.Llt12: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #post_byte er0 + mov #0xa4, r1l + set_ccr_zero + cmp.b r1l, @-er0 +;;; .word 0x0179 +;;; .word 0xb029 + bgt .Lgt12 + fail +.Lgt12: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 contains destination address + test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L12 + fail +.L12: + +cmp_b_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src, er1 + mov #byte_dst, er2 + set_ccr_zero + cmp.b @er1, @er2 + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src er1 + test_h_gr32 byte_dst er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.if 1 ; ambiguous +cmp_b_rspostinc_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src, er1 + mov #byte_dst, er2 + set_ccr_zero + cmp.b @er1+, @er2+ +;;; .word 0x0174 +;;; .word 0x6c1c +;;; .word 0x8220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src+1 er1 + test_h_gr32 byte_dst+1 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.endif +.if 1 ; ambiguous +cmp_b_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src, er1 + mov #byte_dst, er2 + set_ccr_zero + cmp.b @er1-, @er2- +;;; .word 0x0176 +;;; .word 0x6c1c +;;; .word 0xa220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src-1 er1 + test_h_gr32 byte_dst-1 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.endif + +cmp_b_rspreinc_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src-1, er1 + mov #byte_dst-1, er2 + set_ccr_zero + cmp.b @+er1, @+er2 +;;; .word 0x0175 +;;; .word 0x6c1c +;;; .word 0x9220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src er1 + test_h_gr32 byte_dst er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_rspredec_predec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src+1, er1 + mov #byte_dst+1, er2 + set_ccr_zero + cmp.b @-er1, @-er2 +;;; .word 0x0177 +;;; .word 0x6c1c +;;; .word 0xb220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src er1 + test_h_gr32 byte_dst er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_disp2_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src-1, er1 + mov #byte_dst-2, er2 + set_ccr_zero + cmp.b @(1:2, er1), @(2:2, er2) +;;; .word 0x0175 +;;; .word 0x681c +;;; .word 0x2220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src-1 er1 + test_h_gr32 byte_dst-2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_disp16_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src-3, er1 + mov #byte_dst-4, er2 + set_ccr_zero + cmp.b @(3:16, er1), @(4:16, er2) +;;; .word 0x0174 +;;; .word 0x6e1c +;;; .word 3 +;;; .word 0xc220 +;;; .word 4 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src-3 er1 + test_h_gr32 byte_dst-4 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_disp32_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src+5, er1 + mov #byte_dst+6, er2 + set_ccr_zero + cmp.b @(-5:32, er1), @(-6:32, er2) +;;; .word 0x7814 +;;; .word 0x6a2c +;;; .long -5 +;;; .word 0xca20 +;;; .long -6 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src+5 er1 + test_h_gr32 byte_dst+6 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_indexb16_indexb16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0xffffff01, er1 + mov #0xffffff02, er2 + set_ccr_zero + cmp.b @(byte_src-1:16, r1.b), @(byte_dst-2:16, r2.b) +;;; .word 0x0175 +;;; .word 0x6e1c +;;; .word byte_src-1 +;;; .word 0xd220 +;;; .word byte_dst-2 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0xffffff01 er1 + test_h_gr32 0xffffff02 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.if 1 ; ambiguous +cmp_b_indexw16_indexw16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0xffff0003, er1 + mov #0xffff0004, er2 + set_ccr_zero + cmp.b @(byte_src-3:16, r1.w), @(byte_dst-4:16, r2.w) +;;; .word 0x0176 +;;; .word 0x6e1c +;;; .word byte_src-3 +;;; .word 0xe220 +;;; .word byte_dst-4 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0xffff0003 er1 + test_h_gr32 0xffff0004 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.endif + +cmp_b_indexl16_indexl16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0x00000005, er1 + mov #0x00000006, er2 + set_ccr_zero + cmp.b @(byte_src-5:16, er1.l), @(byte_dst-6:16, er2.l) +;;; .word 0x0177 +;;; .word 0x6e1c +;;; .word byte_src-5 +;;; .word 0xf220 +;;; .word byte_dst-6 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0x00000005 er1 + test_h_gr32 0x00000006 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_indexb32_indexb32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0xffffff01, er1 + mov #0xffffff02, er2 + set_ccr_zero + cmp.b @(byte_src-1:32, r1.b), @(byte_dst-2:32, r2.b) +;;; .word 0x7815 +;;; .word 0x6a2c +;;; .long byte_src-1 +;;; .word 0xda20 +;;; .long byte_dst-2 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0xffffff01 er1 + test_h_gr32 0xffffff02 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +.if 1 ; ambiguous +cmp_b_indexw32_indexw32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0xffff0003, er1 + mov #0xffff0004, er2 + set_ccr_zero + cmp.b @(byte_src-3:32, r1.w), @(byte_dst-4:32, r2.w) +;;; .word 0x7816 +;;; .word 0x6a2c +;;; .long byte_src-3 +;;; .word 0xea20 +;;; .long byte_dst-4 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0xffff0003 er1 + test_h_gr32 0xffff0004 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.endif + +cmp_b_indexl32_indexl32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0x00000005, er1 + mov #0x00000006, er2 + set_ccr_zero + cmp.b @(byte_src-5:32, er1.l), @(byte_dst-6:32, er2.l) +;;; .word 0x7817 +;;; .word 0x6a2c +;;; .long byte_src-5 +;;; .word 0xfa20 +;;; .long byte_dst-6 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0x00000005 er1 + test_h_gr32 0x00000006 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_abs16_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + cmp.b @byte_src:16, @byte_dst:16 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_grs_a5a5 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_abs32_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + cmp.b @byte_src:32, @byte_dst:32 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_grs_a5a5 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +.endif + pass + + exit 0 + +fail1: fail diff --git a/sim/testsuite/h8300/cmpl.s b/sim/testsuite/h8300/cmpl.s new file mode 100644 index 0000000..55f235a --- /dev/null +++ b/sim/testsuite/h8300/cmpl.s @@ -0,0 +1,106 @@ +# Hitachi H8 testcase 'cmp.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx +cmp_l_imm3: ; + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.l #xx:3,eRd ; Immediate 3-bit operand + mov.l #5, er0 + cmp.l #5, er0 + beq eq3 + fail +eq3: + cmp.l #6, er0 + blt lt3 + fail +lt3: + cmp.l #4, er0 + bgt gt3 + fail +gt3: + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0x00000005 er0 ; er0 unchanged + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +cmp_l_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.l #xx:8,Rd + cmp.l #0xa5a5a5a5, er0 ; Immediate 16-bit operand + beq eqi + fail +eqi: cmp.l #0xa5a5a5a6, er0 + blt lti + fail +lti: cmp.l #0xa5a5a5a4, er0 + bgt gti + fail +gti: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +cmp_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.l Rs,Rd + mov.l #0xa5a5a5a5, er1 + cmp.l er1, er0 ; Register operand + beq eqr + fail +eqr: mov.l #0xa5a5a5a6, er1 + cmp.l er1, er0 + blt ltr + fail +ltr: mov.l #0xa5a5a5a4, er1 + cmp.l er1, er0 + bgt gtr + fail +gtr: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged + test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/cmpw.s b/sim/testsuite/h8300/cmpw.s new file mode 100644 index 0000000..872c56c --- /dev/null +++ b/sim/testsuite/h8300/cmpw.s @@ -0,0 +1,126 @@ +# Hitachi H8 testcase 'cmp.w' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx +cmp_w_imm3: ; + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.w #xx:3,Rd ; Immediate 3-bit operand + mov.w #5, r0 + cmp.w #5, r0 + beq eq3 + fail +eq3: + cmp.w #6, r0 + blt lt3 + fail +lt3: + cmp.w #4, r0 + bgt gt3 + fail +gt3: + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0xa5a50005 er0 ; er0 unchanged + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +cmp_w_imm16: ; cmp.w immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.w #xx:16,Rd + cmp.w #0xa5a5, r0 ; Immediate 16-bit operand + beq eqi + fail +eqi: cmp.w #0xa5a6, r0 + blt lti + fail +lti: cmp.w #0xa5a4, r0 + bgt gti + fail +gti: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a5 r0 ; r0 unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +cmp_w_imm16_less_than_zero: ; Test for less-than-zero immediate + set_grs_a5a5 + ;; cmp.w #xx:16, Rd, where #xx < 0 (ie. #xx > 0x7fff). + sub.w r0, r0 + cmp.w #0x8001, r0 + bls ltz + fail +ltz: test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +cmp_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.w Rs,Rd + mov.w #0xa5a5, r1 + cmp.w r1, r0 ; Register operand + beq eqr + fail +eqr: mov.w #0xa5a6, r1 + cmp.w r1, r0 + blt ltr + fail +ltr: mov.w #0xa5a4, r1 + cmp.w r1, r0 + bgt gtr + fail +gtr: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a5 r0 ; r0 unchanged. + test_h_gr16 0xa5a4 r1 ; r1 unchanged. +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged + test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/daa.s b/sim/testsuite/h8300/daa.s new file mode 100644 index 0000000..5f81eba --- /dev/null +++ b/sim/testsuite/h8300/daa.s @@ -0,0 +1,36 @@ +# Hitachi H8 testcase 'daa' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +daa_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; daa Rd + daa r0l ; register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr8 5 r0l + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 + diff --git a/sim/testsuite/h8300/das.s b/sim/testsuite/h8300/das.s new file mode 100644 index 0000000..9317f19 --- /dev/null +++ b/sim/testsuite/h8300/das.s @@ -0,0 +1,36 @@ +# Hitachi H8 testcase 'das' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +das_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; das Rd + das r0l ; register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 + diff --git a/sim/testsuite/h8300/dec.s b/sim/testsuite/h8300/dec.s new file mode 100644 index 0000000..122f311 --- /dev/null +++ b/sim/testsuite/h8300/dec.s @@ -0,0 +1,117 @@ +# Hitachi H8 testcase 'dec.b, dec.w, dec.l' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +dec_b: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; dec.b Rd + dec.b r0h ; Decrement 8-bit reg by one + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa4a5 r0 ; dec result: a4|a5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a4a5 er0 ; dec result: a5|a5|a4|a5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +dec_w_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; dec.w #1, Rd + dec.w #1, r0 ; Decrement 16-bit reg by one + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a4 r0 ; dec result: a5|a4 + + test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +dec_w_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; dec.w #2, Rd + dec.w #2, r0 ; Decrement 16-bit reg by two + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a3 r0 ; dec result: a5|a3 + + test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +dec_l_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; dec.l #1, eRd + dec.l #1, er0 ; Decrement 32-bit reg by one + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +dec_l_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; dec.l #2, eRd + dec.l #2, er0 ; Decrement 32-bit reg by two + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + + pass + + exit 0 diff --git a/sim/testsuite/h8300/div.s b/sim/testsuite/h8300/div.s new file mode 100644 index 0000000..fd53baf --- /dev/null +++ b/sim/testsuite/h8300/div.s @@ -0,0 +1,387 @@ +# Hitachi H8 testcase 'divs', 'divu', 'divxs', 'divxu' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) +divs_w_reg_reg: + set_grs_a5a5 + + ;; divs.w rs, rd + mov.w #32, r1 + mov.w #-2, r2 + set_ccr_zero + divs.w r2, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 0xfff0 r1 + test_h_gr32 0xa5a5fffe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divs_w_imm4_reg: + set_grs_a5a5 + + ;; divs.w xx:4, rd + mov.w #-32, r1 + set_ccr_zero + divs.w #2:4, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -16 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divs_l_reg_reg: + set_grs_a5a5 + + ;; divs.l ers, erd + mov.l #320000, er1 + mov.l #-2, er2 + set_ccr_zero + divs.l er2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -160000 er1 + test_h_gr32 -2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divs_l_imm4_reg: + set_grs_a5a5 + + ;; divs.l xx:4, rd + mov.l #-320000, er1 + set_ccr_zero + divs.l #2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -160000 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divu_w_reg_reg: + set_grs_a5a5 + + ;; divu.w rs, rd + mov.w #32, r1 + mov.w #2, r2 + set_ccr_zero + divu.w r2, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 16 r1 + test_h_gr32 0xa5a50002 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divu_w_imm4_reg: + set_grs_a5a5 + + ;; divu.w xx:4, rd + mov.w #32, r1 + set_ccr_zero + divu.w #2:4, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 16 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divu_l_reg_reg: + set_grs_a5a5 + + ;; divu.l ers, erd + mov.l #320000, er1 + mov.l #2, er2 + set_ccr_zero + divu.l er2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 160000 er1 + test_h_gr32 2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divu_l_imm4_reg: + set_grs_a5a5 + + ;; divu.l xx:4, rd + mov.l #320000, er1 + set_ccr_zero + divu.l #2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 160000 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +.if (sim_cpu) ; not equal to zero ie. not h8 +divxs_b_reg_reg: + set_grs_a5a5 + + ;; divxs.b rs, rd + mov.w #32, r1 + mov.b #-2, r2l + set_ccr_zero + divxs.b r2l, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 0x00f0 r1 + test_h_gr32 0xa5a5a5fe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +divxs_b_imm4_reg: + set_grs_a5a5 + + ;; divxs.b xx:4, rd + mov.w #-32, r1 + set_ccr_zero + divxs.b #2:4, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 0x00f0 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +divxs_w_reg_reg: + set_grs_a5a5 + + ;; divxs.w ers, erd + mov.l #0x1000, er1 + mov.w #-0x1000, r2 + set_ccr_zero + divxs.w r2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 0x0000ffff er1 + test_h_gr32 0xa5a5f000 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +divxs_w_imm4_reg: + set_grs_a5a5 + + ;; divxs.w xx:4, rd + mov.l #-4, er1 + set_ccr_zero + divxs.w #2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 0x0000fffe er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx +.endif ; not h8 + +divxu_b_reg_reg: + set_grs_a5a5 + + ;; divxu.b rs, rd + mov.w #32, r1 + mov.b #2, r2l + set_ccr_zero + divxu.b r2l, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x0010 r1 + test_h_gr16 0xa502 r2 +.if (sim_cpu) + test_h_gr32 0xa5a5a502 er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; not h8 +.if (sim_cpu == h8sx) +divxu_b_imm4_reg: + set_grs_a5a5 + + ;; divxu.b xx:4, rd + mov.w #32, r1 + set_ccr_zero + divxu.b #2:4, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x0010 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +divxu_w_reg_reg: + set_grs_a5a5 + + ;; divxu.w ers, erd + mov.l #0x1000, er1 + mov.w #0x1000, r2 + set_ccr_zero + divxu.w r2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x00000001 er1 + test_h_gr32 0xa5a51000 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +divxu_w_imm4_reg: + set_grs_a5a5 + + ;; divxu.w xx:4, rd + mov.l #0xffff, er1 + set_ccr_zero + divxu.w #2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x00017fff er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx +.endif ; not h8 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/extl.s b/sim/testsuite/h8300/extl.s new file mode 100644 index 0000000..001f6d3 --- /dev/null +++ b/sim/testsuite/h8300/extl.s @@ -0,0 +1,1146 @@ +# Hitachi H8 testcase 'exts.l, extu.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 4 +pos: .long 0xffff0001 +neg: .long 0x00008000 + +pos2: .long 0xffffff01 +neg2: .long 0x00000080 + + .text + +exts_l_reg32_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l ern32 + mov.w #1, r0 + exts.l er0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0x00000001 er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +exts_l_reg32_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l ern32 + mov.w #0xffff, r0 + exts.l er0 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffffffff er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +extu_l_reg32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l ern32 + mov.w #0xffff, r0 + extu.l er0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0x0000ffff er0 ; result of zero extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +exts_l_ind_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32 + mov.l #pos, er1 + exts.l @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslindp + fail +.Lslindp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_ind_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32 + mov.l #neg, er1 + exts.l @er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslindn + fail +.Lslindn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_ind_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @ern32 + mov.l #neg, er1 + extu.l @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulindn + fail +.Lulindn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +exts_l_postinc_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32+ + mov.l #pos, er1 + exts.l @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos+4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslpostincp + fail +.Lslpostincp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_postinc_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32+ + mov.l #neg, er1 + exts.l @er1+ + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg+4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslpostincn + fail +.Lslpostincn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_postinc_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @ern32+ + mov.l #neg, er1 + extu.l @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg+4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulpostincn + fail +.Lulpostincn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +exts_l_postdec_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32- + mov.l #pos, er1 + exts.l @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos-4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslpostdecp + fail +.Lslpostdecp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_postdec_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32- + mov.l #neg, er1 + exts.l @er1- + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg-4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslpostdecn + fail +.Lslpostdecn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_postdec_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @ern32- + mov.l #neg, er1 + extu.l @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulpostdecn + fail +.Lulpostdecn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +exts_l_preinc_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @+ern32 + mov.l #pos-4, er1 + exts.l @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslpreincp + fail +.Lslpreincp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_preinc_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @+ern32 + mov.l #neg-4, er1 + exts.l @+er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslpreincn + fail +.Lslpreincn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_preinc_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @+ern32 + mov.l #neg-4, er1 + extu.l @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulpreincn + fail +.Lulpreincn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +exts_l_predec_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @-ern32 + mov.l #pos+4, er1 + exts.l @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslpredecp + fail +.Lslpredecp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_predec_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @-ern32 + mov.l #neg+4, er1 + exts.l @-er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslpredecn + fail +.Lslpredecn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_predec_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @-ern32 + mov.l #neg+4, er1 + extu.l @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulpredecn + fail +.Lulpredecn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_disp2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @(dd:2, ern32) + mov.l #neg-8, er1 + extu.l @(8:2, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-8 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Luldisp2n + fail +.Luldisp2n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_disp16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @(dd:16, ern32) + mov.l #neg-44, er1 + extu.l @(44:16, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-44 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Luldisp16n + fail +.Luldisp16n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_disp32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @(dd:32, ern32) + mov.l #neg+444, er1 + extu.l @(-444:32, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg+444 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Luldisp32n + fail +.Luldisp32n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_abs16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @aa:16 + extu.l @neg:16 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulabs16n + fail +.Lulabs16n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_abs32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @aa:32 + extu.l @neg:32 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulabs32n + fail +.Lulabs32n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + + + + # + # exts #2, nn + # + +exts_l_reg32_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, ern32 + mov.b #1, r0l + exts.l #2, er0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0x00000001 er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +exts_l_reg32_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, ern32 + mov.b #0xff, r0l + exts.l #2, er0 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 0xffffffff er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +extu_l_reg32_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, ern32 + mov.b #0xff, r0l + extu.l #2, er0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0x000000ff er0 ; result of zero extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +exts_l_ind_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32 + mov.l #pos2, er1 + exts.l #2, @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslindp2 + fail +.Lslindp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_ind_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32 + mov.l #neg2, er1 + exts.l #2, @er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslindn2 + fail +.Lslindn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_ind_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @ern32 + mov.l #neg2, er1 + extu.l #2, @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulindn2 + fail +.Lulindn2: +;;; Note: leave the value as 0x00000080, like it started out. + +exts_l_postinc_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32+ + mov.l #pos2, er1 + exts.l #2, @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2+4 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslpostincp2 + fail +.Lslpostincp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_postinc_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32+ + mov.l #neg2, er1 + exts.l #2, @er1+ + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2+4 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslpostincn2 + fail +.Lslpostincn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_postinc_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @ern32+ + mov.l #neg2, er1 + extu.l #2, @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2+4 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulpostincn2 + fail +.Lulpostincn2: +;;; Note: leave the value as 0x00000080, like it started out. + +exts_l_postdec_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32- + mov.l #pos2, er1 + exts.l #2, @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2-4 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslpostdecp2 + fail +.Lslpostdecp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_postdec_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32- + mov.l #neg2, er1 + exts.l #2, @er1- + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2-4 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslpostdecn2 + fail +.Lslpostdecn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_postdec_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @ern32- + mov.l #neg2, er1 + extu.l #2, @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2-4 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulpostdecn2 + fail +.Lulpostdecn2: +;;; Note: leave the value as 0x00000080, like it started out. + +exts_l_preinc_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @+ern32 + mov.l #pos2-4, er1 + exts.l #2, @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslpreincp2 + fail +.Lslpreincp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_preinc_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @+ern32 + mov.l #neg2-4, er1 + exts.l #2, @+er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslpreincn2 + fail +.Lslpreincn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_preinc_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @+ern32 + mov.l #neg2-4, er1 + extu.l #2, @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulpreincn2 + fail +.Lulpreincn2: +;;; Note: leave the value as 0x00000080, like it started out. + +exts_l_predec_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @-ern32 + mov.l #pos2+4, er1 + exts.l #2, @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslpredecp2 + fail +.Lslpredecp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_predec_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @-ern32 + mov.l #neg2+4, er1 + exts.l #2, @-er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslpredecn2 + fail +.Lslpredecn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_predec_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @-ern32 + mov.l #neg2+4, er1 + extu.l #2, @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulpredecn2 + fail +.Lulpredecn2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_disp2_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @(dd:2, ern32) + mov.l #neg2-8, er1 + extu.l #2, @(8:2, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2-8 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Luldisp2n2 + fail +.Luldisp2n2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_disp16_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @(dd:16, ern32) + mov.l #neg2-44, er1 + extu.l #2, @(44:16, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2-44 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Luldisp16n2 + fail +.Luldisp16n2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_disp32_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @(dd:32, ern32) + mov.l #neg2+444, er1 + extu.l #2, @(-444:32, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2+444 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Luldisp32n2 + fail +.Luldisp32n2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_abs16_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @aa:16 + extu.l #2, @neg2:16 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulabs16n2 + fail +.Lulabs16n2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_abs32_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @aa:32 + extu.l #2, @neg2:32 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulabs32n2 + fail +.Lulabs32n2: +;;; Note: leave the value as 0x00000080, like it started out. + +.endif + + pass + + exit 0 + + + + diff --git a/sim/testsuite/h8300/extw.s b/sim/testsuite/h8300/extw.s new file mode 100644 index 0000000..b1eb491 --- /dev/null +++ b/sim/testsuite/h8300/extw.s @@ -0,0 +1,580 @@ +# Hitachi H8 testcase 'exts.w, extu.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 2 +pos: .word 0xff01 +neg: .word 0x0080 + + .text + +exts_w_reg16_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w rn16 + mov.b #1, r0l + exts.w r0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0xa5a50001 er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +exts_w_reg16_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w rn16 + mov.b #0xff, r0l + exts.w r0 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5ffff er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +extu_w_reg16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w rn16 + mov.b #0xff, r0l + extu.w r0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0xa5a500ff er0 ; result of zero extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +exts_w_ind_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern + mov.l #pos, er1 + exts.w @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswindp + fail +.Lswindp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_ind_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern + mov.l #neg, er1 + exts.w @er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswindn + fail +.Lswindn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_ind_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @ern + mov.l #neg, er1 + extu.w @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwindn + fail +.Luwindn: + ;; Note: leave the value as 0x0080, like it started out. + +exts_w_postinc_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern+ + mov.l #pos, er1 + exts.w @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos+2 er1 ; er1 still contains target address plus 2 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswpostincp + fail +.Lswpostincp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_postinc_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern+ + mov.l #neg, er1 + exts.w @er1+ + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg+2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswpostincn + fail +.Lswpostincn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_postinc_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @ern+ + mov.l #neg, er1 + extu.w @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg+2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwpostincn + fail +.Luwpostincn: + ;; Note: leave the value as 0x0080, like it started out. + +exts_w_postdec_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern- + mov.l #pos, er1 + exts.w @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos-2 er1 ; er1 still contains target address plus 2 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswpostdecp + fail +.Lswpostdecp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_postdec_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern- + mov.l #neg, er1 + exts.w @er1- + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg-2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswpostdecn + fail +.Lswpostdecn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_postdec_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @ern- + mov.l #neg, er1 + extu.w @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwpostdecn + fail +.Luwpostdecn: + ;; Note: leave the value as 0x0080, like it started out. + +exts_w_preinc_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @+ern + mov.l #pos-2, er1 + exts.w @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address plus 2 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswpreincp + fail +.Lswpreincp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_preinc_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @+ern + mov.l #neg-2, er1 + exts.w @+er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswpreincn + fail +.Lswpreincn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_preinc_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @+ern + mov.l #neg-2, er1 + extu.w @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwpreincn + fail +.Luwpreincn: + ;; Note: leave the value as 0x0080, like it started out. + +exts_w_predec_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @-ern + mov.l #pos+2, er1 + exts.w @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address plus 2 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswpredecp + fail +.Lswpredecp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_predec_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @-ern + mov.l #neg+2, er1 + exts.w @-er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswpredecn + fail +.Lswpredecn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_predec_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @-ern + mov.l #neg+2, er1 + extu.w @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwpredecn + fail +.Luwpredecn: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_disp2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @(dd:2, ern) + mov.l #neg-2, er1 + extu.w @(2:2, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwdisp2n + fail +.Luwdisp2n: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_disp16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @(dd:16, ern) + mov.l #neg-44, er1 + extu.w @(44:16, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-44 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwdisp16n + fail +.Luwdisp16n: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_disp32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @(dd:32, ern) + mov.l #neg+444, er1 + extu.w @(-444:32, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg+444 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwdisp32n + fail +.Luwdisp32n: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_abs16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @aa:16 + extu.w @neg:16 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwabs16n + fail +.Luwabs16n: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_abs32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @aa:32 + extu.w @neg:32 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwabs32n + fail +.Luwabs32n: + ;; Note: leave the value as 0x0080, like it started out. + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/h8300/inc.s b/sim/testsuite/h8300/inc.s new file mode 100644 index 0000000..69d2c3b --- /dev/null +++ b/sim/testsuite/h8300/inc.s @@ -0,0 +1,117 @@ +# Hitachi H8 testcase 'inc, inc.w, inc.l' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +inc_b: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; inc.b Rd + inc.b r0h ; Increment 8-bit reg by one + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa6a5 r0 ; inc result: a6|a5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a6a5 er0 ; inc result: a5|a5|a6|a5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +inc_w_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; inc.w #1, Rd + inc.w #1, r0 ; Increment 16-bit reg by one + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a6 r0 ; inc result: a5|a6 + + test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +inc_w_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; inc.w #2, Rd + inc.w #2, r0 ; Increment 16-bit reg by two + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a7 r0 ; inc result: a5|a7 + + test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +inc_l_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; inc.l #1, eRd + inc.l #1, er0 ; Increment 32-bit reg by one + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +inc_l_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; inc.l #2, eRd + inc.l #2, er0 ; Increment 32-bit reg by two + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + + pass + + exit 0 diff --git a/sim/testsuite/h8300/jmp.s b/sim/testsuite/h8300/jmp.s new file mode 100644 index 0000000..30a4b28 --- /dev/null +++ b/sim/testsuite/h8300/jmp.s @@ -0,0 +1,123 @@ +# Hitachi H8 testcase 'jmp' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +vector_area: + .fill 0x400, 1, 0 + + start + +.if (sim_cpu == h8sx) +jmp_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #.Ltgt_8:32, @0x20 + set_ccr_zero + ;; jmp @@aa:8 ; 8-bit displacement + jmp @@0x20 + fail + +.Ltgt_8: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +jmp_7: ; vector jump + mov.l #vector_area, er0 + ldc.l er0, vbr + set_grs_a5a5 + mov.l #.Ltgt_7:32, @vector_area+0x300 + set_ccr_zero + + jmp @@0x300 + fail +.Ltgt_7: + test_cc_clear + test_grs_a5a5 + stc.l vbr, er0 + test_h_gr32 vector_area, er0 + +.endif ; h8sx + +jmp_24: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; jmp @aa:24 ; 24-bit address + jmp @.Ltgt_24:24 + fail + +.Ltgt_24: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; Non-zero means h8300h, h8300s, or h8sx +jmp_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; jmp @ern ; register indirect + mov.l #.Ltgt_reg, er5 + jmp @er5 + fail + +.Ltgt_reg: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_h_gr32 .Ltgt_reg er5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; not h8300 + +.if (sim_cpu == h8sx) +jmp_32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; jmp @aa:32 ; 32-bit address +; jmp @.Ltgt_32:32 ; NOTE: hard-coded to avoid relaxing + .word 0x5908 + .long .Ltgt_32 + fail + +.Ltgt_32: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + + pass + exit 0 + + \ No newline at end of file diff --git a/sim/testsuite/h8300/ldc.s b/sim/testsuite/h8300/ldc.s new file mode 100644 index 0000000..3712a6c --- /dev/null +++ b/sim/testsuite/h8300/ldc.s @@ -0,0 +1,375 @@ +# Hitachi H8 testcase 'ldc' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + .data +byte_pre: + .byte 0 +byte_src: + .byte 0xff +byte_post: + .byte 0 + + start + +ldc_imm8_ccr: + set_grs_a5a5 + set_ccr_zero + + ldc #0xff, ccr ; set all ccr flags high, immediate operand + bcs .L1 ; carry flag set? + fail +.L1: bvs .L2 ; overflow flag set? + fail +.L2: beq .L3 ; zero flag set? + fail +.L3: bmi .L4 ; neg flag set? + fail +.L4: + ldc #0, ccr ; set all ccr flags low, immediate operand + bcc .L5 ; carry flag clear? + fail +.L5: bvc .L6 ; overflow flag clear? + fail +.L6: bne .L7 ; zero flag clear? + fail +.L7: bpl .L8 ; neg flag clear? + fail +.L8: + test_cc_clear + test_grs_a5a5 + +ldc_reg8_ccr: + set_grs_a5a5 + set_ccr_zero + + mov #0xff, r0h + ldc r0h, ccr ; set all ccr flags high, reg operand + bcs .L11 ; carry flag set? + fail +.L11: bvs .L12 ; overflow flag set? + fail +.L12: beq .L13 ; zero flag set? + fail +.L13: bmi .L14 ; neg flag set? + fail +.L14: + mov #0, r0h + ldc r0h, ccr ; set all ccr flags low, reg operand + bcc .L15 ; carry flag clear? + fail +.L15: bvc .L16 ; overflow flag clear? + fail +.L16: bne .L17 ; zero flag clear? + fail +.L17: bpl .L18 ; neg flag clear? + fail +.L18: + test_cc_clear + test_h_gr16 0x00a5 r0 ; Register 0 modified by test procedure. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +ldc_imm8_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + ldc #0x87, exr ; set exr to 0x87 + + stc exr, r0l ; retrieve and check exr value + cmp.b #0x87, r0l + beq .L19 + fail +.L19: + test_h_gr16 0xa587 r0 ; Register 0 modified by test procedure. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_reg8_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + mov #0x87, r0h + ldc r0h, exr ; set exr to 0x87 + + stc exr, r0l ; retrieve and check exr value + cmp.b #0x87, r0l + beq .L21 + fail +.L21: + test_h_gr16 0x8787 r0 ; Register 0 modified by test procedure. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_abs16_ccr: + set_grs_a5a5 + set_ccr_zero + + ldc @byte_src:16, ccr ; abs16 src + stc ccr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_abs16_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + ldc @byte_src:16, exr ; abs16 src + stc exr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_abs32_ccr: + set_grs_a5a5 + set_ccr_zero + + ldc @byte_src:32, ccr ; abs32 src + stc ccr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_abs32_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + ldc @byte_src:32, exr ; abs32 src + stc exr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_disp16_ccr: + set_grs_a5a5 + set_ccr_zero + + mov #byte_pre, er1 + ldc @(1:16, er1), ccr ; disp16 src + stc ccr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_h_gr32 byte_pre, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_disp16_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + mov #byte_post, er1 + ldc @(-1:16, er1), exr ; disp16 src + stc exr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_h_gr32 byte_post, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_disp32_ccr: + set_grs_a5a5 + set_ccr_zero + + mov #byte_pre, er1 + ldc @(1:32, er1), ccr ; disp32 src + stc ccr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_h_gr32 byte_pre, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_disp32_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + mov #byte_post, er1 + ldc @(-1:32, er1), exr ; disp16 src + stc exr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_h_gr32 byte_post, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_postinc_ccr: + set_grs_a5a5 + set_ccr_zero + + mov #byte_src, er1 + ldc @er1+, ccr ; postinc src + stc ccr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_h_gr32 byte_src+2, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_postinc_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + mov #byte_src, er1 + ldc @er1+, exr ; postinc src + stc exr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_h_gr32 byte_src+2, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_ind_ccr: + set_grs_a5a5 + set_ccr_zero + + mov #byte_src, er1 + ldc @er1, ccr ; postinc src + stc ccr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_h_gr32 byte_src, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_ind_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + mov #byte_src, er1 + ldc @er1, exr ; postinc src + stc exr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_h_gr32 byte_src, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx +ldc_reg_sbr: + set_grs_a5a5 + set_ccr_zero + + mov #0xaaaaaaaa, er0 + ldc er0, sbr ; set sbr to 0xaaaaaaaa + stc sbr, er1 ; retreive and check sbr value + + test_h_gr32 0xaaaaaaaa er1 + test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_reg_vbr: + set_grs_a5a5 + set_ccr_zero + + mov #0xaaaaaaaa, er0 + ldc er0, vbr ; set sbr to 0xaaaaaaaa + stc vbr, er1 ; retreive and check sbr value + + test_h_gr32 0xaaaaaaaa er1 + test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + pass + + exit 0 diff --git a/sim/testsuite/h8300/ldm.s b/sim/testsuite/h8300/ldm.s new file mode 100644 index 0000000..c816221 --- /dev/null +++ b/sim/testsuite/h8300/ldm.s @@ -0,0 +1,233 @@ +# Hitachi H8 testcase 'ldm', 'stm' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + .data + .align 4 +_stack: .long 0,1,2,3,4,5,6,7,8,9,0,0,0,0,0,0 + .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 +_stack_top: + + start + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +stm_2reg: + set_grs_a5a5 + mov #_stack_top, er7 + mov #2, er2 + mov #3, er3 + + set_ccr_zero + stm er2-er3, @-sp + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_h_gr32 2 er2 + test_h_gr32 3 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 _stack_top-8, er7 + + mov @_stack_top-4, er0 + cmp #2, er0 + bne fail1 + + mov @_stack_top-8, er0 + cmp #3, er0 + bne fail1 + + mov @_stack_top-12, er0 + cmp #0, er0 + bne fail1 + +stm_3reg: + set_grs_a5a5 + mov #_stack_top, er7 + mov #4, er4 + mov #5, er5 + mov #6, er6 + + set_ccr_zero + stm er4-er6, @-sp + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 4 er4 + test_h_gr32 5 er5 + test_h_gr32 6 er6 + test_h_gr32 _stack_top-12, er7 + + mov @_stack_top-4, er0 + cmp #4, er0 + bne fail1 + + mov @_stack_top-8, er0 + cmp #5, er0 + bne fail1 + + mov @_stack_top-12, er0 + cmp #6, er0 + bne fail1 + + mov @_stack_top-16, er0 + cmp #0, er0 + bne fail1 + +stm_4reg: + set_grs_a5a5 + mov #_stack_top, er7 + mov #1, er0 + mov #2, er1 + mov #3, er2 + mov #4, er3 + + set_ccr_zero + stm er0-er3, @-sp + test_cc_clear + + test_h_gr32 1 er0 + test_h_gr32 2 er1 + test_h_gr32 3 er2 + test_h_gr32 4 er3 + test_gr_a5a5 4 ; Make sure other general regs not disturbed + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 _stack_top-16, er7 + + mov @_stack_top-4, er0 + cmp #1, er0 + bne fail1 + + mov @_stack_top-8, er0 + cmp #2, er0 + bne fail1 + + mov @_stack_top-12, er0 + cmp #3, er0 + bne fail1 + + mov @_stack_top-16, er0 + cmp #4, er0 + bne fail1 + + mov @_stack_top-20, er0 + cmp #0, er0 + bne fail1 + +ldm_2reg: + set_grs_a5a5 + mov #_stack, er7 + + set_ccr_zero + ldm @sp+, er2-er3 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_h_gr32 1 er2 + test_h_gr32 0 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 _stack+8, er7 + +ldm_3reg: + set_grs_a5a5 + mov #_stack+4, er7 + + set_ccr_zero + ldm @sp+, er4-er6 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 3 er4 + test_h_gr32 2 er5 + test_h_gr32 1 er6 + test_h_gr32 _stack+16, er7 + +ldm_4reg: + set_grs_a5a5 + mov #_stack+4, er7 + + set_ccr_zero + ldm @sp+, er0-er3 + test_cc_clear + + test_h_gr32 4 er0 + test_h_gr32 3 er1 + test_h_gr32 2 er2 + test_h_gr32 1 er3 + test_gr_a5a5 4 ; Make sure other general regs not disturbed + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 _stack+20, er7 +.endif + +pushpop: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #_stack_top, r7 + mov #12, r1 + mov #34, r2 + mov #56, r3 + push r1 + push r2 + push r3 + pop r4 + pop r5 + pop r6 + + test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed + test_h_gr16 12 r1 + test_h_gr16 34 r2 + test_h_gr16 56 r3 + test_h_gr16 56 r4 + test_h_gr16 34 r5 + test_h_gr16 12 r6 + mov #_stack_top, r0 + cmp.w r0, r7 + bne fail1 +.else + mov #_stack_top, er7 + mov #12, er1 + mov #34, er2 + mov #56, er3 + push er1 + push er2 + push er3 + pop er4 + pop er5 + pop er6 + + test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed + test_h_gr32 12 er1 + test_h_gr32 34 er2 + test_h_gr32 56 er3 + test_h_gr32 56 er4 + test_h_gr32 34 er5 + test_h_gr32 12 er6 + test_h_gr32 _stack_top, er7 +.endif + + pass + + exit 0 + +fail1: fail diff --git a/sim/testsuite/h8300/mac.s b/sim/testsuite/h8300/mac.s new file mode 100644 index 0000000..d60fe30 --- /dev/null +++ b/sim/testsuite/h8300/mac.s @@ -0,0 +1,263 @@ +# Hitachi H8 testcase 'mac' +# mach(): h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +src1: .word 0 +src2: .word 0 + +array: .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + + start + +.if (sim_cpu) +_clrmac: + set_grs_a5a5 + set_ccr_zero + clrmac + test_cc_clear + test_grs_a5a5 + ;; Now see if the mac is actually clear... + stmac mach, er0 + test_zero_set + test_neg_clear + test_ovf_clear + test_h_gr32 0 er0 + stmac macl, er1 + test_zero_set + test_neg_clear + test_ovf_clear + test_h_gr32 0 er1 + +ld_stmac: + set_grs_a5a5 + sub.l er2, er2 + set_ccr_zero + ldmac er1, macl + stmac macl, er2 + test_ovf_clear + test_carry_clear + ;; neg and zero are undefined + test_h_gr32 0xa5a5a5a5 er2 + + sub.l er2, er2 + set_ccr_zero + ldmac er1, mach + stmac mach, er2 + test_ovf_clear + test_carry_clear + ;; neg and zero are undefined + test_h_gr32 0x0001a5 er2 + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mac_2x2: + set_grs_a5a5 + mov.w #2, r1 + mov.w r1, @src1 + mov.w #2, r2 + mov.w r2, @src2 + mov #src1, er1 + mov #src2, er2 + set_ccr_zero + clrmac + mac @er1+, @er2+ + test_cc_clear + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 src1+2 er1 + test_h_gr32 src2+2 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + + stmac macl, er0 + test_zero_clear + test_neg_clear + test_ovf_clear + test_h_gr32 4 er0 + + stmac mach, er0 + test_zero_clear + test_neg_clear + test_ovf_clear + test_h_gr32 0 er0 + +mac_same_reg_2x4: + ;; Use same reg for src and dst. Should be incremented twice, + ;; and fetch values from consecutive locations. + set_grs_a5a5 + mov.w #2, r1 + mov.w r1, @src1 + mov.w #4, r2 + mov.w r2, @src2 + mov #src1, er1 + + set_ccr_zero + clrmac + mac @er1+, @er1+ ; same register for src and dst + test_cc_clear + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 src1+4 er1 + test_h_gr32 0xa5a50004 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + + stmac macl, er0 + test_zero_clear + test_neg_clear + test_ovf_clear + test_h_gr32 8 er0 + + stmac mach, er0 + test_zero_clear + test_neg_clear + test_ovf_clear + test_h_gr32 0 er0 + +mac_0x0: + set_grs_a5a5 + mov.w #0, r1 + mov.w r1, @src1 + mov.w #0, r2 + mov.w r2, @src2 + mov #src1, er1 + mov #src2, er2 + set_ccr_zero + clrmac + mac @er1+, @er2+ + test_cc_clear + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 src1+2 er1 + test_h_gr32 src2+2 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + + stmac macl, er0 + test_zero_set ; zero flag is set + test_neg_clear + test_ovf_clear + test_h_gr32 0 er0 ; result is zero + + stmac mach, er0 + test_zero_set + test_neg_clear + test_ovf_clear + test_h_gr32 0 er0 + +mac_neg2x2: + set_grs_a5a5 + mov.w #-2, r1 + mov.w r1, @src1 + mov.w #2, r2 + mov.w r2, @src2 + mov #src1, er1 + mov #src2, er2 + set_ccr_zero + clrmac + mac @er1+, @er2+ + test_cc_clear + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 src1+2 er1 + test_h_gr32 src2+2 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + + stmac macl, er0 + test_zero_clear + test_neg_set ; neg flag is set + test_ovf_clear + test_h_gr32 -4 er0 ; result is negative + + stmac mach, er0 + test_zero_clear + test_neg_set + test_ovf_clear + test_h_gr32 -1 er0 ; negative sign extend + +mac_array: + ;; Use same reg for src and dst, pointing to an array of shorts + set_grs_a5a5 + mov #array, er1 + + set_ccr_zero + clrmac + mac @er1+, @er1+ ; same register for src and dst + mac @er1+, @er1+ ; repeat 8 times + mac @er1+, @er1+ + mac @er1+, @er1+ + mac @er1+, @er1+ + mac @er1+, @er1+ + mac @er1+, @er1+ + mac @er1+, @er1+ + test_cc_clear + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 array+32 er1 + test_h_gr32 0xa5a5a5a5 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + + stmac macl, er0 + test_zero_clear + test_neg_clear + test_ovf_clear + test_h_gr32 0xfff80008 er0 + + stmac mach, er0 + test_zero_clear + test_neg_clear + test_ovf_clear + test_h_gr32 1 er0 ; result is greater than 32 bits + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/h8300/mova.s b/sim/testsuite/h8300/mova.s new file mode 100644 index 0000000..a4bcfd6 --- /dev/null +++ b/sim/testsuite/h8300/mova.s @@ -0,0 +1,838 @@ +# Hitachi H8 testcase 'mova' +# mach(): h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +foo: .long 0x01010101 + .long 0x10101010 + .long 0x11111111 + + start + +movabl16_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/b.l @(1:16, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0xa6 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movabl16_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/b.l @(1:16, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0xa5a6 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movabl32_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/b.l @(1:32, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0xa6 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movabl32_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/b.l @(1:32, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0xa5a6 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movawl16_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/w.l @(1:16, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x14b er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movawl16_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/w.l @(1:16, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x14b4b er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movawl32_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/w.l @(1:32, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x14b er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movawl32_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/w.l @(1:32, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x14b4b er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movall16_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/l.l @(1:16, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x295 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movall16_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/l.l @(1:16, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x29695 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movall32_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/l.l @(1:32, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x295 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movall32_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/l.l @(1:32, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x29695 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +t02_mova: + set_grs_a5a5 + set_ccr_zero + + mov.l #0x01010101, er1 + mova/b.c @(0x1234:16,r1l.b),er1 ; 7A891234 + test_h_gr32 0x1235, er1 ; 1s + mov.l #0x01010101, er1 + mova/b.c @(0x1234:16,r1.w),er1 ; 7A991234 + test_h_gr32 0x1335, er1 ; 2s + mov.l #0x01010101, er1 + mova/w.c @(0x1234:16,r1l.b),er1 ; 7AA91234 + test_h_gr32 0x1236, er1 ; 3s + mov.l #0x01010101, er1 + mova/w.c @(0x1234:16,r1.w),er1 ; 7AB91234 + test_h_gr32 0x1436, er1 ; 4s + mov.l #0x01010101, er1 + mova/l.c @(0x1234:16,r1l.b),er1 ; 7AC91234 + test_h_gr32 0x1238, er1 ; 5s + mov.l #0x01010101, er1 + mova/l.c @(0x1234:16,r1.w),er1 ; 7AD91234 + test_h_gr32 0x1638, er1 ; 6s + mov.l #0x01010101, er1 + mova/b.c @(0x12345678:32,r1l.b),er1 ; 7A8112345678 + test_h_gr32 0x12345679, er1 ; 7s + mov.l #0x01010101, er1 + mova/b.c @(0x12345678:32,r1.w),er1 ; 7A9112345678 + test_h_gr32 0x12345779, er1 ; 8s + mov.l #0x01010101, er1 + mova/w.c @(0x12345678:32,r1l.b),er1 ; 7AA112345678 + test_h_gr32 0x1234567a, er1 ; 9s + mov.l #0x01010101, er1 + mova/w.c @(0x12345678:32,r1.w),er1 ; 7AB112345678 + test_h_gr32 0x1234587a, er1 ; 10s + mov.l #0x01010101, er1 + mova/l.c @(0x12345678:32,r1l.b),er1 ; 7AC112345678 + test_h_gr32 0x1234567c, er1 ; 11s + mov.l #0x01010101, er1 + mova/l.c @(0x12345678:32,r1.w),er1 ; 7AD112345678 + test_h_gr32 0x12345a7c, er1 ; 12s + +t02b: + mov.l #0x01010101, er3 + mova/b.l @(0x1234:16,r3l.b),er1 ; 78B87A891234 + test_h_gr32 0x1235, er1 ; 1 + mova/b.l @(0x1234:16,r3.w),er1 ; 78397A991234 + test_h_gr32 0x1335, er1 ; 2 + mova/w.l @(0x1234:16,r3l.b),er1 ; 78B87AA91234 + test_h_gr32 0x1236, er1 ; 3 + mova/w.l @(0x1234:16,r3.w),er1 ; 78397AB91234 + test_h_gr32 0x1436, er1 ; 4 + mova/l.l @(0x1234:16,r3l.b),er1 ; 78B87AC91234 + test_h_gr32 0x1238, er1 ; 5 + mova/l.l @(0x1234:16,r3.w),er1 ; 78397AD91234 + test_h_gr32 0x1638, er1 ; 6 + mova/b.l @(0x12345678:32,r3l.b),er1 ; 78B87A8112345678 + test_h_gr32 0x12345679, er1 ; 7 + mova/b.l @(0x12345678:32,r3.w),er1 ; 78397A9112345678 + test_h_gr32 0x12345779, er1 ; 8 + mova/w.l @(0x12345678:32,r3l.b),er1 ; 78B87AA112345678 + test_h_gr32 0x1234567a, er1 ; 9 + mova/w.l @(0x12345678:32,r3.w),er1 ; 78397AB112345678 + test_h_gr32 0x1234587a, er1 ; 10 + mova/l.l @(0x12345678:32,r3l.b),er1 ; 78B87AC112345678 + test_h_gr32 0x1234567c, er1 ; 11 + mova/l.l @(0x12345678:32,r3.w),er1 ; 78397AD112345678 + test_h_gr32 0x12345a7c, er1 ; 12 + test_h_gr32 0x01010101, er3 +t02c: + mov.l #foo, er2 + mova/b.l @(0x1234:16,@er2.b),er1 ;017F02811234 + test_h_gr32 0x1235, er1 ; 13 + test_h_gr32 foo, er2 + mova/b.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12811234 + test_h_gr32 0x1235, er1 ; 18 + test_h_gr32 foo, er2 + mova/b.l @(0x1234:16,@er2+.b),er1 ;017F82811234 + test_h_gr32 0x1235, er1 ; 14 + test_h_gr32 foo+1, er2 + mova/b.l @(0x1234:16,@-er2.b),er1 ;017FB2811234 + test_h_gr32 0x1235, er1 ; 17 + test_h_gr32 foo, er2 + mova/b.l @(0x1234:16,@+er2.b),er1 ;017F92811234 + test_h_gr32 0x1235, er1 ; 16 + test_h_gr32 foo+1, er2 + mova/b.l @(0x1234:16,@er2-.b),er1 ;017FA2811234 + test_h_gr32 0x1235, er1 ; 15 + test_h_gr32 foo, er2 +t02d: + mov.l #4, er2 + mova/b.l @(0x1234:16, @(foo:16, er2).b), er1 + test_h_gr32 0x1244, er1 ; 19 + mova/b.l @(0x1234:16, @(foo:16, r2L.b).b), er1 + test_h_gr32 0x1244, er1 ; 21 + mova/b.l @(0x1234:16, @(foo:16, r2.w).b), er1 + test_h_gr32 0x1244, er1 ; 22 + mova/b.l @(0x1234:16, @(foo:16, er2.l).b), er1 + test_h_gr32 0x1244, er1 ; 23 + + mov.l #4, er2 + mova/b.l @(0x1234:16, @(foo:32, er2).b), er1 + test_h_gr32 0x1244, er1 ; 20 + mova/b.l @(0x1234:16, @(foo:32, r2L.b).b), er1 + test_h_gr32 0x1244, er1 ; 24 + mova/b.l @(0x1234:16, @(foo:32, r2.w).b), er1 + test_h_gr32 0x1244, er1 ; 25 + mova/b.l @(0x1234:16, @(foo:32, er2.l).b), er1 + test_h_gr32 0x1244, er1 ; 26 + + mova/b.l @(0x1234:16,@foo:16.b),er1 + test_h_gr32 0x1235, er1 ; 27 + mova/b.l @(0x1234:16,@foo:32.b),er1 + test_h_gr32 0x1235, er1 ; 28 + +t02e: + mov.l #foo, er2 + mova/b.l @(0x1234:16,@er2.w),er1 ;015F02911234 + test_h_gr32 0x1335, er1 ; 29 + test_h_gr32 foo, er2 + mova/b.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12911234 + test_h_gr32 0x1335, er1 ; 34 + test_h_gr32 foo, er2 + mova/b.l @(0x1234:16,@er2+.w),er1 ;015F82911234 + test_h_gr32 0x1335, er1 ; 30 + test_h_gr32 foo+2, er2 + mova/b.l @(0x1234:16,@-er2.w),er1 ;015FB2911234 + test_h_gr32 0x1335, er1 ; 33 + test_h_gr32 foo, er2 + mova/b.l @(0x1234:16,@+er2.w),er1 ;015F92911234 + test_h_gr32 0x1335, er1 ; 32 + test_h_gr32 foo+2, er2 + mova/b.l @(0x1234:16,@er2-.w),er1 ;015FA2911234 + test_h_gr32 0x1335, er1 ; 31 + test_h_gr32 foo, er2 + + mov.l #4, er2 + mova/b.l @(0x1234:16, @(foo:16, er2).w), er1 + test_h_gr32 0x2244, er1 ; 35 + shar.l er2 + mova/b.l @(0x1234:16, @(foo:16, r2L.b).w), er1 + test_h_gr32 0x2244, er1 ; 37 + mova/b.l @(0x1234:16, @(foo:16, r2.w).w), er1 + test_h_gr32 0x2244, er1 ; 38 + mova/b.l @(0x1234:16, @(foo:16, er2.l).w), er1 + test_h_gr32 0x2244, er1 ; 39 + + mov.l #4, er2 + mova/b.l @(0x1234:16, @(foo:32, er2).w), er1 + test_h_gr32 0x2244, er1 ; 36 + shar.l er2 + mova/b.l @(0x1234:16, @(foo:32, r2L.b).w), er1 + test_h_gr32 0x2244, er1 ; 40 + mova/b.l @(0x1234:16, @(foo:32, r2.w).w), er1 + test_h_gr32 0x2244, er1 ; 41 + mova/b.l @(0x1234:16, @(foo:32, er2.l).w), er1 + test_h_gr32 0x2244, er1 ; 42 + + mova/b.l @(0x1234:16,@foo:16.w),er1 ;015F40919ABC1234 + test_h_gr32 0x1335, er1 ; 43 + mova/b.l @(0x1234:16,@foo:32.w),er1 ;015F48919ABCDEF01234 + test_h_gr32 0x1335, er1 ; 44 + +t02f: + mov.l #foo, er2 + mova/w.l @(0x1234:16,@er2.b),er1 ;017F02A11234 + test_h_gr32 0x1236, er1 ; 45 + mova/w.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12A11234 + test_h_gr32 0x1236, er1 ; 50 + mova/w.l @(0x1234:16,@er2+.b),er1 ;017F82A11234 + test_h_gr32 0x1236, er1 ; 46 + test_h_gr32 foo+1, er2 + mova/w.l @(0x1234:16,@-er2.b),er1 ;017FB2A11234 + test_h_gr32 0x1236, er1 ; 49 + test_h_gr32 foo, er2 + mova/w.l @(0x1234:16,@+er2.b),er1 ;017F92A11234 + test_h_gr32 0x1236, er1 ; 48 + test_h_gr32 foo+1, er2 + mova/w.l @(0x1234:16,@er2-.b),er1 ;017FA2A11234 + test_h_gr32 0x1236, er1 ; 47 + test_h_gr32 foo, er2 + +t02g: + mov.l #4, er2 + mova/w.l @(0x1234:16, @(foo:16, er2).b), er1 + test_h_gr32 0x1254, er1 ; 51 + mova/w.l @(0x1234:16, @(foo:16, r2L.b).b), er1 + test_h_gr32 0x1254, er1 ; 53 + mova/w.l @(0x1234:16, @(foo:16, r2.w).b), er1 + test_h_gr32 0x1254, er1 ; 54 + mova/w.l @(0x1234:16, @(foo:16, er2.l).b), er1 + test_h_gr32 0x1254, er1 ; 55 + + mov.l #4, er2 + mova/w.l @(0x1234:16, @(foo:32, er2).b), er1 + test_h_gr32 0x1254, er1 ; 52 + mova/w.l @(0x1234:16, @(foo:32, r2L.b).b), er1 + test_h_gr32 0x1254, er1 ; 56 + mova/w.l @(0x1234:16, @(foo:32, r2.w).b), er1 + test_h_gr32 0x1254, er1 ; 57 + mova/w.l @(0x1234:16, @(foo:32, er2.l).b), er1 + test_h_gr32 0x1254, er1 ; 58 + + mova/w.l @(0x1234:16,@foo:16.b),er1 ;017F40A19ABC1234 + test_h_gr32 0x1236, er1 ; 59 (can't test -- points into the woods) + mova/w.l @(0x1234:16,@foo:32.b),er1 ;017F48A19ABCDEF01234 + test_h_gr32 0x1236, er1 ; 60 (can't test -- points into the woods) + +t02h: + mov.l #foo, er2 + mova/w.l @(0x1234:16,@er2.w),er1 ;015F02B11234 + test_h_gr32 0x1436, er1 ; 61 + mova/w.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12B11234 + test_h_gr32 0x1436, er1 ; 66, 0x1234 + (@(4+foo).w << 1 + mova/w.l @(0x1234:16,@er2+.w),er1 ;015F82B11234 + test_h_gr32 0x1436, er1 ; 62 + test_h_gr32 foo+2, er2 + mova/w.l @(0x1234:16,@-er2.w),er1 ;015FB2B11234 + test_h_gr32 0x1436, er1 ; 63 + test_h_gr32 foo, er2 + mova/w.l @(0x1234:16,@+er2.w),er1 ;015F92B11234 + test_h_gr32 0x1436, er1 ; 64 + test_h_gr32 foo+2, er2 + mova/w.l @(0x1234:16,@er2-.w),er1 ;015FA2B11234 + test_h_gr32 0x1436, er1 ; 65 + test_h_gr32 foo, er2 +t02i: + mov.l #4, er2 + mova/w.l @(0x1234:16, @(foo:16, er2).w), er1 + test_h_gr32 0x3254, er1 ; 67 + shar.l er2 + mova/w.l @(0x1234:16, @(foo:16, r2L.b).w), er1 + test_h_gr32 0x3254, er1 ; 69 + mova/w.l @(0x1234:16, @(foo:16, r2.w).w), er1 + test_h_gr32 0x3254, er1 ; 70 + mova/w.l @(0x1234:16, @(foo:16, er2.l).w), er1 + test_h_gr32 0x3254, er1 ; 71 + + mov.l #4, er2 + mova/w.l @(0x1234:16, @(foo:32, er2).w), er1 + test_h_gr32 0x3254, er1 ; 68 + shar.l er2 + mova/w.l @(0x1234:16, @(foo:32, r2L.b).w), er1 + test_h_gr32 0x3254, er1 ; 72 + mova/w.l @(0x1234:16, @(foo:32, r2.w).w), er1 + test_h_gr32 0x3254, er1 ; 73 + mova/w.l @(0x1234:16, @(foo:32, er2.l).w), er1 + test_h_gr32 0x3254, er1 ; 74 + + mova/w.l @(0x1234:16,@foo:16.w),er1 ;015F40B19ABC1234 + test_h_gr32 0x1436, er1 ; 75 (can't test -- points into the woods) + mova/w.l @(0x1234:16,@foo:32.w),er1 ;015F48B19ABCDEF01234 + test_h_gr32 0x1436, er1 ; 76 (can't test -- points into the woods) + +t02j: + mov.l #foo, er2 + mova/l.l @(0x1234:16,@er2.b),er1 ;017F02C11234 + test_h_gr32 0x1238, er1 ; 77 + mova/l.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12C11234 + test_h_gr32 0x1238, er1 ; 82 + mova/l.l @(0x1234:16,@er2+.b),er1 ;017F82C11234 + test_h_gr32 0x1238, er1 ; 78 + test_h_gr32 foo+1, er2 + mova/l.l @(0x1234:16,@-er2.b),er1 ;017FB2C11234 + test_h_gr32 0x1238, er1 ; 79 + test_h_gr32 foo, er2 + mova/l.l @(0x1234:16,@+er2.b),er1 ;017F92C11234 + test_h_gr32 0x1238, er1 ; 80 + test_h_gr32 foo+1, er2 + mova/l.l @(0x1234:16,@er2-.b),er1 ;017FA2C11234 + test_h_gr32 0x1238, er1 ; 81 + test_h_gr32 foo, er2 + +t02k: + mov.l #4, er2 + mova/l.l @(0x1234:16, @(foo:16, er2).b), er1 + test_h_gr32 0x1274, er1 ; 83 + mova/l.l @(0x1234:16, @(foo:16, r2L.b).b), er1 + test_h_gr32 0x1274, er1 ; 85 + mova/l.l @(0x1234:16, @(foo:16, r2.w).b), er1 + test_h_gr32 0x1274, er1 ; 86 + mova/l.l @(0x1234:16, @(foo:16, er2.l).b), er1 + test_h_gr32 0x1274, er1 ; 87 + + mov.l #4, er2 + mova/l.l @(0x1234:16, @(foo:32, er2).b), er1 + test_h_gr32 0x1274, er1 ; 84 + mova/l.l @(0x1234:16, @(foo:32, r2L.b).b), er1 + test_h_gr32 0x1274, er1 ; 88 + mova/l.l @(0x1234:16, @(foo:32, r2.w).b), er1 + test_h_gr32 0x1274, er1 ; 89 + mova/l.l @(0x1234:16, @(foo:32, er2.l).b), er1 + test_h_gr32 0x1274, er1 ; 90 + + mova/l.l @(0x1234:16,@foo:16.b),er1 ;017F40C19ABC1234 + test_h_gr32 0x1238, er1 ; 91 (can't test -- points into the woods) + mova/l.l @(0x1234:16,@foo:32.b),er1 ;017F48C19ABCDEF01234 + test_h_gr32 0x1238, er1 ; 92 (can't test -- points into the woods) + +t02l: + mov.l #foo, er2 + mova/l.l @(0x1234:16,@er2.w),er1 ;015F02D11234 + test_h_gr32 0x1638, er1 ; 93 + mova/l.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12D11234 + test_h_gr32 0x1638, er1 ; 98 + mova/l.l @(0x1234:16,@er2+.w),er1 ;015F82D11234 + test_h_gr32 0x1638, er1 ; 94 + test_h_gr32 foo+2, er2 + mova/l.l @(0x1234:16,@-er2.w),er1 ;015FB2D11234 + test_h_gr32 0x1638, er1 ; 97 + test_h_gr32 foo, er2 + mova/l.l @(0x1234:16,@+er2.w),er1 ;015F92D11234 + test_h_gr32 0x1638, er1 ; 96 + test_h_gr32 foo+2, er2 + mova/l.l @(0x1234:16,@er2-.w),er1 ;015FA2D11234 + test_h_gr32 0x1638, er1 ; 95 + test_h_gr32 foo, er2 + +t02o: + mov.l #4, er2 + mova/l.l @(0x1234:16, @(foo:16, er2).w), er1 + test_h_gr32 0x5274, er1 ; 99 + shar.l er2 + mova/l.l @(0x1234:16, @(foo:16, r2L.b).w), er1 + test_h_gr32 0x5274, er1 ; 101 + mova/l.l @(0x1234:16, @(foo:16, r2.w).w), er1 + test_h_gr32 0x5274, er1 ; 102 + mova/l.l @(0x1234:16, @(foo:16, er2.l).w), er1 + test_h_gr32 0x5274, er1 ; 103 + + mov.l #4, er2 + mova/l.l @(0x1234:16, @(foo:32, er2).w), er1 + test_h_gr32 0x5274, er1 ; 100 + shar.l er2 + mova/l.l @(0x1234:16, @(foo:32, r2L.b).w), er1 + test_h_gr32 0x5274, er1 ; 104 + mova/l.l @(0x1234:16, @(foo:32, r2.w).w), er1 + test_h_gr32 0x5274, er1 ; 105 + mova/l.l @(0x1234:16, @(foo:32, er2.l).w), er1 + test_h_gr32 0x5274, er1 ; 106 + + mova/l.l @(0x1234:16,@foo:16.w),er1 ;015F40D19ABC1234 + test_h_gr32 0x1638, er1 ; 107 (can't test -- points into the woods) + mova/l.l @(0x1234:16,@foo:32.w),er1 ;015F48D19ABCDEF01234 + test_h_gr32 0x1638, er1 ; 108 (can't test -- points into the woods) + +t02p: + mov.l #foo, er2 + mova/b.l @(0x12345678:32,@er2.b),er1 ;017F028912345678 + test_h_gr32 0x12345679, er1 ; 109 + mova/b.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F128912345678 + test_h_gr32 0x12345679, er1 ; 114 + mova/b.l @(0x12345678:32,@er2+.b),er1 ;017F828912345678 + test_h_gr32 0x12345679, er1 ; 110 + test_h_gr32 foo+1, er2 + mova/b.l @(0x12345678:32,@-er2.b),er1 ;017FB28912345678 + test_h_gr32 0x12345679, er1 ; 113 + test_h_gr32 foo, er2 + mova/b.l @(0x12345678:32,@+er2.b),er1 ;017F928912345678 + test_h_gr32 0x12345679, er1 ; 112 + test_h_gr32 foo+1, er2 + mova/b.l @(0x12345678:32,@er2-.b),er1 ;017FA28912345678 + test_h_gr32 0x12345679, er1 ; 111 + test_h_gr32 foo, er2 + +t02q: + mov.l #4, er2 + mova/b.l @(0x12345678:32, @(foo:16, er2).b), er1 + test_h_gr32 0x12345688, er1 ; 115 + mova/b.l @(0x12345678:32, @(foo:16, r2L.b).b), er1 + test_h_gr32 0x12345688, er1 ; 117 + mova/b.l @(0x12345678:32, @(foo:16, r2.w).b), er1 + test_h_gr32 0x12345688, er1 ; 118 + mova/b.l @(0x12345678:32, @(foo:16, er2.l).b), er1 + test_h_gr32 0x12345688, er1 ; 119 + + mov.l #4, er2 + mova/b.l @(0x12345678:32, @(foo:32, er2).b), er1 + test_h_gr32 0x12345688, er1 ; 116 + mova/b.l @(0x12345678:32, @(foo:32, r2L.b).b), er1 + test_h_gr32 0x12345688, er1 ; 120 + mova/b.l @(0x12345678:32, @(foo:32, r2.w).b), er1 + test_h_gr32 0x12345688, er1 ; 121 + mova/b.l @(0x12345678:32, @(foo:32, er2.l).b), er1 + test_h_gr32 0x12345688, er1 ; 122 + + mova/b.l @(0x12345678:32,@foo:16.b),er1 + test_h_gr32 0x12345679, er1 ; 123 + mova/b.l @(0x12345678:32,@foo:32.b),er1 + test_h_gr32 0x12345679, er1 ; 124 + +t02r: + mov.l #foo, er2 + mova/b.l @(0x12345678:32,@er2.w),er1 ;015F029912345678 + test_h_gr32 0x12345779, er1 ; 125 + mova/b.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F129912345678 + test_h_gr32 0x12345779, er1 ; 130 + mova/b.l @(0x12345678:32,@er2+.w),er1 ;015F829912345678 + test_h_gr32 0x12345779, er1 ; 126 + test_h_gr32 foo+2, er2 + mova/b.l @(0x12345678:32,@-er2.w),er1 ;015FB29912345678 + test_h_gr32 0x12345779, er1 ; 129 + test_h_gr32 foo, er2 + mova/b.l @(0x12345678:32,@+er2.w),er1 ;015F929912345678 + test_h_gr32 0x12345779, er1 ; 128 + test_h_gr32 foo+2, er2 + mova/b.l @(0x12345678:32,@er2-.w),er1 ;015FA29912345678 + test_h_gr32 0x12345779, er1 ; 127 + test_h_gr32 foo, er2 + + mov.l #4, er2 + mova/b.l @(0x12345678:32, @(foo:16, er2).w), er1 + test_h_gr32 0x12346688, er1 ; 131 + shar.l er2 + mova/b.l @(0x12345678:32, @(foo:16, r2L.b).w), er1 + test_h_gr32 0x12346688, er1 ; 133 + mova/b.l @(0x12345678:32, @(foo:16, r2.w).w), er1 + test_h_gr32 0x12346688, er1 ; 134 + mova/b.l @(0x12345678:32, @(foo:16, er2.l).w), er1 + test_h_gr32 0x12346688, er1 ; 135 + + mov.l #4, er2 + mova/b.l @(0x12345678:32, @(foo:32, er2).w), er1 + test_h_gr32 0x12346688, er1 ; 132 + shar.l er2 + mova/b.l @(0x12345678:32, @(foo:32, r2L.b).w), er1 + test_h_gr32 0x12346688, er1 ; 136 + mova/b.l @(0x12345678:32, @(foo:32, r2.w).w), er1 + test_h_gr32 0x12346688, er1 ; 137 + mova/b.l @(0x12345678:32, @(foo:32, er2.l).w), er1 + test_h_gr32 0x12346688, er1 ; 138 + + mova/b.l @(0x12345678:32,@foo:16.w),er1 + test_h_gr32 0x12345779, er1 ; 139 + mova/b.l @(0x12345678:32,@foo:32.w),er1 + test_h_gr32 0x12345779, er1 ; 140 + +t02s: + mov.l #foo, er2 + mova/w.l @(0x12345678:32,@er2.b),er1 ;017F02A912345678 + test_h_gr32 0x1234567a, er1 ; 141 + mova/w.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12A912345678 + test_h_gr32 0x1234567a, er1 ; 146 + mova/w.l @(0x12345678:32,@er2+.b),er1 ;017F82A912345678 + test_h_gr32 0x1234567a, er1 ; 142 + test_h_gr32 foo+1, er2 + mova/w.l @(0x12345678:32,@-er2.b),er1 ;017FB2A912345678 + test_h_gr32 0x1234567a, er1 ; 145 + test_h_gr32 foo, er2 + mova/w.l @(0x12345678:32,@+er2.b),er1 ;017F92A912345678 + test_h_gr32 0x1234567a, er1 ; 144 + test_h_gr32 foo+1, er2 + mova/w.l @(0x12345678:32,@er2-.b),er1 ;017FA2A912345678 + test_h_gr32 0x1234567a, er1 ; 143 + test_h_gr32 foo, er2 + + mov.l #4, er2 + mova/w.l @(0x12345678:32, @(foo:16, er2).b), er1 + test_h_gr32 0x12345698, er1 ; 147 + mova/w.l @(0x12345678:32, @(foo:16, r2L.b).b), er1 + test_h_gr32 0x12345698, er1 ; 149 + mova/w.l @(0x12345678:32, @(foo:16, r2.w).b), er1 + test_h_gr32 0x12345698, er1 ; 150 + mova/w.l @(0x12345678:32, @(foo:16, er2.l).b), er1 + test_h_gr32 0x12345698, er1 ; 151 + + mov.l #4, er2 + mova/w.l @(0x12345678:32, @(foo:32, er2).b), er1 + test_h_gr32 0x12345698, er1 ; 148 + mova/w.l @(0x12345678:32, @(foo:32, r2L.b).b), er1 + test_h_gr32 0x12345698, er1 ; 152 + mova/w.l @(0x12345678:32, @(foo:32, r2.w).b), er1 + test_h_gr32 0x12345698, er1 ; 153 + mova/w.l @(0x12345678:32, @(foo:32, er2.l).b), er1 + test_h_gr32 0x12345698, er1 ; 154 + + mova/w.l @(0x12345678:32,@foo:16.b),er1 + test_h_gr32 0x1234567a, er1 ; 155 + mova/w.l @(0x12345678:32,@foo:32.b),er1 + test_h_gr32 0x1234567a, er1 ; 156 + +t02t: + mov.l #foo, er2 + mova/w.l @(0x12345678:32,@er2.w),er1 ;015F02B912345678 + test_h_gr32 0x1234587a, er1 ; 157 + mova/w.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12B912345678 + test_h_gr32 0x1234587a, er1 ; 162 + mova/w.l @(0x12345678:32,@er2+.w),er1 ;015F82B912345678 + test_h_gr32 0x1234587a, er1 ; 158 + test_h_gr32 foo+2, er2 + mova/w.l @(0x12345678:32,@-er2.w),er1 ;015FB2B912345678 + test_h_gr32 0x1234587a, er1 ; 161 + test_h_gr32 foo, er2 + mova/w.l @(0x12345678:32,@+er2.w),er1 ;015F92B912345678 + test_h_gr32 0x1234587a, er1 ; 160 + test_h_gr32 foo+2, er2 + mova/w.l @(0x12345678:32,@er2-.w),er1 ;015FA2B912345678 + test_h_gr32 0x1234587a, er1 ; 159 + test_h_gr32 foo, er2 + + mov.l #4, er2 + mova/w.l @(0x12345678:32, @(foo:16, er2).w), er1 + test_h_gr32 0x12347698, er1 ; 163 + shar.l er2 + mova/w.l @(0x12345678:32, @(foo:16, r2L.b).w), er1 + test_h_gr32 0x12347698, er1 ; 165 + mova/w.l @(0x12345678:32, @(foo:16, r2.w).w), er1 + test_h_gr32 0x12347698, er1 ; 166 + mova/w.l @(0x12345678:32, @(foo:16, er2.l).w), er1 + test_h_gr32 0x12347698, er1 ; 167 + + mov.l #4, er2 + mova/w.l @(0x12345678:32, @(foo:32, er2).w), er1 + test_h_gr32 0x12347698, er1 ; 164 + shar.l er2 + mova/w.l @(0x12345678:32, @(foo:32, r2L.b).w), er1 + test_h_gr32 0x12347698, er1 ; 168 + mova/w.l @(0x12345678:32, @(foo:32, r2.w).w), er1 + test_h_gr32 0x12347698, er1 ; 169 + mova/w.l @(0x12345678:32, @(foo:32, er2.l).w), er1 + test_h_gr32 0x12347698, er1 ; 170 + + mova/w.l @(0x12345678:32,@foo:16.w),er1 + test_h_gr32 0x1234587a, er1 ; 171 + mova/w.l @(0x12345678:32,@foo:32.w),er1 + test_h_gr32 0x1234587a, er1 ; 172 + +t02u: + mov.l #foo, er2 + mova/l.l @(0x12345678:32,@er2.b),er1 ;017F02C912345678 + test_h_gr32 0x1234567c, er1 ; 173 + mova/l.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12C912345678 + test_h_gr32 0x1234567c, er1 ; 178 + mova/l.l @(0x12345678:32,@er2+.b),er1 ;017F82C912345678 + test_h_gr32 0x1234567c, er1 ; 174 + test_h_gr32 foo+1, er2 + mova/l.l @(0x12345678:32,@-er2.b),er1 ;017FB2C912345678 + test_h_gr32 0x1234567c, er1 ; 177 + test_h_gr32 foo, er2 + mova/l.l @(0x12345678:32,@+er2.b),er1 ;017F92C912345678 + test_h_gr32 0x1234567c, er1 ; 176 + test_h_gr32 foo+1, er2 + mova/l.l @(0x12345678:32,@er2-.b),er1 ;017FA2C912345678 + test_h_gr32 0x1234567c, er1 ; 175 + test_h_gr32 foo, er2 + + mov.l #4, er2 + mova/l.l @(0x12345678:32, @(foo:16, er2).b), er1 + test_h_gr32 0x123456b8, er1 ; 179 + mova/l.l @(0x12345678:32, @(foo:16, r2L.b).b), er1 + test_h_gr32 0x123456b8, er1 ; 181 + mova/l.l @(0x12345678:32, @(foo:16, r2.w).b), er1 + test_h_gr32 0x123456b8, er1 ; 182 + mova/l.l @(0x12345678:32, @(foo:16, er2.l).b), er1 + test_h_gr32 0x123456b8, er1 ; 183 + + mov.l #4, er2 + mova/l.l @(0x12345678:32, @(foo:32, er2).b), er1 + test_h_gr32 0x123456b8, er1 ; 180 + mova/l.l @(0x12345678:32, @(foo:32, r2L.b).b), er1 + test_h_gr32 0x123456b8, er1 ; 184 + mova/l.l @(0x12345678:32, @(foo:32, r2.w).b), er1 + test_h_gr32 0x123456b8, er1 ; 185 + mova/l.l @(0x12345678:32, @(foo:32, er2.l).b), er1 + test_h_gr32 0x123456b8, er1 ; 186 + + mova/l.l @(0x12345678:32,@foo:16.b),er1 + test_h_gr32 0x1234567c, er1 ; 187 + mova/l.l @(0x12345678:32,@foo:32.b),er1 + test_h_gr32 0x1234567c, er1 ; 188 + +t02v: + mov.l #foo, er2 + mova/l.l @(0x12345678:32,@er2.w),er1 ;015F02D912345678 + test_h_gr32 0x12345a7c, er1 ; 189 + mova/l.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12D912345678 + test_h_gr32 0x12345a7c, er1 ; 194 + mova/l.l @(0x12345678:32,@er2+.w),er1 ;015F82D912345678 + test_h_gr32 0x12345a7c, er1 ; 190 + test_h_gr32 foo+2, er2 + mova/l.l @(0x12345678:32,@-er2.w),er1 ;015FB2D912345678 + test_h_gr32 0x12345a7c, er1 ; 193 + test_h_gr32 foo, er2 + mova/l.l @(0x12345678:32,@+er2.w),er1 ;015F92D912345678 + test_h_gr32 0x12345a7c, er1 ; 192 + test_h_gr32 foo+2, er2 + mova/l.l @(0x12345678:32,@er2-.w),er1 ;015FA2D912345678 + test_h_gr32 0x12345a7c, er1 ; 191 + test_h_gr32 foo, er2 + + mov.l #4, er2 + mova/l.l @(0x12345678:32, @(foo:16, er2).w), er1 + test_h_gr32 0x123496b8, er1 ; 195 + shar.l er2 + mova/l.l @(0x12345678:32, @(foo:16, r2L.b).w), er1 + test_h_gr32 0x123496b8, er1 ; 197 + mova/l.l @(0x12345678:32, @(foo:16, r2.w).w), er1 + test_h_gr32 0x123496b8, er1 ; 198 + mova/l.l @(0x12345678:32, @(foo:16, er2.l).w), er1 + test_h_gr32 0x123496b8, er1 ; 199 + + mov.l #4, er2 + mova/l.l @(0x12345678:32, @(foo:32, er2).w), er1 + test_h_gr32 0x123496b8, er1 ; 195 + shar.l er2 + mova/l.l @(0x12345678:32, @(foo:32, r2L.b).w), er1 + test_h_gr32 0x123496b8, er1 ; 197 + mova/l.l @(0x12345678:32, @(foo:32, r2.w).w), er1 + test_h_gr32 0x123496b8, er1 ; 198 + mova/l.l @(0x12345678:32, @(foo:32, er2.l).w), er1 + test_h_gr32 0x123496b8, er1 ; 199 + + mova/l.l @(0x12345678:32,@foo:16.w),er1 + test_h_gr32 0x12345a7c, er1 ; 203 + mova/l.l @(0x12345678:32,@foo:32.w),er1 + test_h_gr32 0x12345a7c, er1 ; 204 + + test_gr_a5a5 0 + test_h_gr32 2, er2 + test_h_gr32 0x01010101, er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/movb.s b/sim/testsuite/h8300/movb.s new file mode 100644 index 0000000..87dcdf3 --- /dev/null +++ b/sim/testsuite/h8300/movb.s @@ -0,0 +1,2221 @@ +# Hitachi H8 testcase 'mov.w' +# mach(): h8300h h8300s h8sx +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 4 +byte_src: + .byte 0x77 +byte_dst: + .byte 0 + + .text + + ;; + ;; Move byte from immediate source + ;; + +.if (sim_cpu == h8sx) +mov_b_imm8_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, rd + mov.b #0x77:8, r0l ; Immediate 3-bit operand +;;; .word 0xf877 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu == h8sx) +mov_b_imm4_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:4, @aa:16 + mov.b #0xf:4, @byte_dst:16 ; 16-bit address-direct operand +;;; .word 0x6adf +;;; .word @byte_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xf, @byte_dst + beq .Lnext21 + fail +.Lnext21: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm4_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:4, @aa:32 + mov.b #0xf:4, @byte_dst:32 ; 32-bit address-direct operand +;;; .word 0x6aff +;;; .long @byte_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xf, @byte_dst + beq .Lnext22 + fail +.Lnext22: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @erd + mov.l #byte_dst, er1 + mov.b #0xa5:8, @er1 ; Register indirect operand +;;; .word 0x017d +;;; .word 0x01a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext1 + fail +.Lnext1: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_postinc: ; post-increment from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @erd+ + mov.l #byte_dst, er1 + mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands. +;;; .word 0x017d +;;; .word 0x81a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst+1, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext2 + fail +.Lnext2: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_postdec: ; post-decrement from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @erd- + mov.l #byte_dst, er1 + mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands. +;;; .word 0x017d +;;; .word 0xa1a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-1, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext3 + fail +.Lnext3: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @+erd + mov.l #byte_dst-1, er1 + mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands +;;; .word 0x017d +;;; .word 0x91a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext4 + fail +.Lnext4: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @-erd + mov.l #byte_dst+1, er1 + mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands +;;; .word 0x017d +;;; .word 0xb1a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext5 + fail +.Lnext5: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @(dd:2, erd) + mov.l #byte_dst-3, er1 + mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand +;;; .word 0x017d +;;; .word 0x31a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-3, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext6 + fail +.Lnext6: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @(dd:16, erd) + mov.l #byte_dst-4, er1 + mov.b #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x017d +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext7 + fail +.Lnext7: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @(dd:32, erd) + mov.l #byte_dst-8, er1 + mov.b #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x017d +;;; .word 0xc9a5 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext8 + fail +.Lnext8: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexb16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:16, rd.b) + mov.b #0xa5:8, @(byte_dst-1:16, r1.b) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xffffff01, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexw16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0002, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:16, rd.w) + mov.b #0xa5:8, @(byte_dst-2:16, r1.w) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xffff0002, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexl16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000003, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:16, erd.l) + mov.b #0xa5:8, @(byte_dst-3:16, er1.l) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0x00000003, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexb32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff04, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:32, rd.b) + mov.b #0xa5:8, @(byte_dst-4:32, r1.b) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xffffff04 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexw32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0005, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:32, rd.w) + mov.b #0xa5:8, @(byte_dst-5:32, r1.w) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xffff0005 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexl32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000006, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:32, erd.l) + mov.b #0xa5:8, @(byte_dst-6:32, er1.l) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0x00000006 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @aa:16 + mov.b #0xa5:8, @byte_dst:16 ; 16-bit address-direct operand +;;; .word 0x017d +;;; .word 0x40a5 +;;; .word @byte_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext9 + fail +.Lnext9: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @aa:32 + mov.b #0xa5:8, @byte_dst:32 ; 32-bit address-direct operand +;;; .word 0x017d +;;; .word 0x48a5 +;;; .long @byte_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext10 + fail +.Lnext10: + mov.b #0, @byte_dst ; zero it again for the next use. + +.endif + + ;; + ;; Move byte from register source + ;; + +mov_b_reg8_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, erd + mov.b #0x12, r1l + mov.b r1l, r0l ; Register 8-bit operand +;;; .word 0x0c98 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + test_h_gr16 0xa512 r0 + test_h_gr16 0xa512 r1 ; mov src unchanged +.if (sim_cpu) + test_h_gr32 0xa5a5a512 er0 + test_h_gr32 0xa5a5a512 er1 ; mov src unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_b_reg8_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @erd + mov.l #byte_dst, er1 + mov.b r0l, @er1 ; Register indirect operand +;;; .word 0x6898 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r2l, r0l + beq .Lnext44 + fail +.Lnext44: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_b_reg8_to_postinc: ; post-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @erd+ + mov.l #byte_dst, er1 + mov.b r0l, @er1+ ; Register post-incr operand +;;; .word 0x0173 +;;; .word 0x6c98 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst+1, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b r2l, @byte_dst + beq .Lnext49 + fail +.Lnext49: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_postdec: ; post-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @erd- + mov.l #byte_dst, er1 + mov.b r0l, @er1- ; Register post-decr operand +;;; .word 0x0171 +;;; .word 0x6c98 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-1, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b r2l, @byte_dst + beq .Lnext50 + fail +.Lnext50: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @+erd + mov.l #byte_dst-1, er1 + mov.b r0l, @+er1 ; Register pre-incr operand +;;; .word 0x0172 +;;; .word 0x6c98 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b r2l, @byte_dst + beq .Lnext51 + fail +.Lnext51: + mov.b #0, @byte_dst ; zero it again for the next use. +.endif + +mov_b_reg8_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @-erd + mov.l #byte_dst+1, er1 + mov.b r0l, @-er1 ; Register pre-decr operand +;;; .word 0x6c98 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r2l, r0l + beq .Lnext48 + fail +.Lnext48: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_b_reg8_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @(dd:2, erd) + mov.l #byte_dst-3, er1 + mov.b r0l, @(3:2, er1) ; Register plus 2-bit disp. operand +;;; .word 0x0173 +;;; .word 0x6898 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-3, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b r2l, @byte_dst + beq .Lnext52 + fail +.Lnext52: + mov.b #0, @byte_dst ; zero it again for the next use. +.endif + +mov_b_reg8_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @(dd:16, erd) + mov.l #byte_dst-4, er1 + mov.b r0l, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x6e98 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 byte_dst-4, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r2l, r0l + beq .Lnext45 + fail +.Lnext45: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @(dd:32, erd) + mov.l #byte_dst-8, er1 + mov.b r0l, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7810 +;;; .word 0x6aa8 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 byte_dst-8, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r2l, r0l + beq .Lnext46 + fail +.Lnext46: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_b_reg8_to_indexb16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + set_ccr_zero + ;; mov.b ers, @(dd:16, rd.b) + mov.b r0l, @(byte_dst-1:16, r1.b) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffffff01 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexw16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0002, er1 + set_ccr_zero + ;; mov.b ers, @(dd:16, rd.w) + mov.b r0l, @(byte_dst-2:16, r1.w) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffff0002 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexl16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000003, er1 + set_ccr_zero + ;; mov.b ers, @(dd:16, erd.l) + mov.b r0l, @(byte_dst-3:16, er1.l) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x00000003 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexb32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff04 er1 + set_ccr_zero + ;; mov.b ers, @(dd:32, rd.b) + mov.b r0l, @(byte_dst-4:32, r1.b) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffffff04, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexw32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0005 er1 + set_ccr_zero + ;; mov.b ers, @(dd:32, rd.w) + mov.b r0l, @(byte_dst-5:32, r1.w) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffff0005, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexl32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000006 er1 + set_ccr_zero + ;; mov.b ers, @(dd:32, erd.l) + mov.b r0l, @(byte_dst-6:32, er1.l) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x00000006, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. +.endif + +.if (sim_cpu == h8sx) +mov_b_reg8_to_abs8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + mov.l #byte_dst-20, er0 + ldc er0, sbr + set_ccr_zero + ;; mov.b ers, @aa:8 + mov.b r1l, @20:8 ; 8-bit address-direct (sbr-relative) operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 byte_dst-20, er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r1l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. +.endif + +mov_b_reg8_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @aa:16 + mov.b r0l, @byte_dst:16 ; 16-bit address-direct operand +;;; .word 0x6a88 +;;; .word @byte_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r0l, r1l + beq .Lnext41 + fail +.Lnext41: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @aa:32 + mov.b r0l, @byte_dst:32 ; 32-bit address-direct operand +;;; .word 0x6aa8 +;;; .long @byte_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r0l, r1l + beq .Lnext42 + fail +.Lnext42: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + + ;; + ;; Move byte to register destination. + ;; + +mov_b_indirect_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers, rd + mov.l #byte_src, er1 + mov.b @er1, r0l ; Register indirect operand +;;; .word 0x6818 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_postinc_to_reg8: ; post-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers+, rd + + mov.l #byte_src, er1 + mov.b @er1+, r0l ; Register post-incr operand +;;; .word 0x6c18 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src+1, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_b_postdec_to_reg8: ; post-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers-, rd + + mov.l #byte_src, er1 + mov.b @er1-, r0l ; Register post-decr operand +;;; .word 0x0172 +;;; .word 0x6c18 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src-1, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_preinc_to_reg8: ; pre-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @+ers, rd + + mov.l #byte_src-1, er1 + mov.b @+er1, r0l ; Register pre-incr operand +;;; .word 0x0171 +;;; .word 0x6c18 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_predec_to_reg8: ; pre-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @-ers, rd + + mov.l #byte_src+1, er1 + mov.b @-er1, r0l ; Register pre-decr operand +;;; .word 0x0173 +;;; .word 0x6c18 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_b_disp2_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:2, ers), rd + mov.l #byte_src-1, er1 + mov.b @(1:2, er1), r0l ; Register plus 2-bit disp. operand +;;; .word 0x0171 +;;; .word 0x6818 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 byte_src-1, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_b_disp16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:16, ers), rd + mov.l #byte_src+0x1234, er1 + mov.b @(-0x1234:16, er1), r0l ; Register plus 16-bit disp. operand +;;; .word 0x6e18 +;;; .word -0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 byte_src+0x1234, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_disp32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:32, ers), rd + mov.l #byte_src+65536, er1 + mov.b @(-65536:32, er1), r0l ; Register plus 32-bit disp. operand +;;; .word 0x7810 +;;; .word 0x6a28 +;;; .long -65536 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 byte_src+65536, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_b_indexb16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + set_ccr_zero + ;; mov.b @(dd:16, rs.b), rd + mov.b @(byte_src-1:16, r1.b), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 + + test_h_gr32 0xffffff01, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexw16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0002, er1 + set_ccr_zero + ;; mov.b @(dd:16, rs.w), rd + mov.b @(byte_src-2:16, r1.w), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 + + test_h_gr32 0xffff0002, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexl16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000003, er1 + set_ccr_zero + ;; mov.b @(dd:16, ers.l), rd + mov.b @(byte_src-3:16, er1.l), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 + + test_h_gr32 0x00000003, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexb32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff04, er1 + set_ccr_zero + ;; mov.b @(dd:32, rs.b), rd + mov.b @(byte_src-4:32, r1.b), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 0xffffff04 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexw32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0005, er1 + set_ccr_zero + ;; mov.b @(dd:32, rs.w), rd + mov.b @(byte_src-5:32, r1.w), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 0xffff0005 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexl32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000006, er1 + set_ccr_zero + ;; mov.b @(dd:32, ers.l), rd + mov.b @(byte_src-6:32, er1.l), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 0x00000006 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +.if (sim_cpu == h8sx) +mov_b_abs8_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #byte_src-255, er1 + ldc er1, sbr + set_ccr_zero + ;; mov.b @aa:8, rd + mov.b @0xff:8, r0l ; 8-bit (sbr relative) address-direct operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src-255, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_b_abs16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @aa:16, rd + mov.b @byte_src:16, r0l ; 16-bit address-direct operand +;;; .word 0x6a08 +;;; .word @byte_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_abs32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @aa:32, rd + mov.b @byte_src:32, r0l ; 32-bit address-direct operand +;;; .word 0x6a28 +;;; .long @byte_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + + ;; + ;; Move byte from memory to memory + ;; + +mov_b_indirect_to_indirect: ; reg indirect, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers, @erd + + mov.l #byte_src, er1 + mov.l #byte_dst, er0 + mov.b @er1, @er0 +;;; .word 0x0178 +;;; .word 0x0100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst er0 + test_h_gr32 byte_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext55 + fail +.Lnext55: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext56 + fail +.Lnext56: ; OK, pass on. + +mov_b_postinc_to_postinc: ; reg post-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers+, @erd+ + + mov.l #byte_src, er1 + mov.l #byte_dst, er0 + mov.b @er1+, @er0+ +;;; .word 0x0178 +;;; .word 0x8180 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst+1 er0 + test_h_gr32 byte_src+1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext65 + fail +.Lnext65: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext66 + fail +.Lnext66: ; OK, pass on. + +mov_b_postdec_to_postdec: ; reg post-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers-, @erd- + + mov.l #byte_src, er1 + mov.l #byte_dst, er0 + mov.b @er1-, @er0- +;;; .word 0x0178 +;;; .word 0xa1a0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst-1 er0 + test_h_gr32 byte_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext75 + fail +.Lnext75: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext76 + fail +.Lnext76: ; OK, pass on. + +mov_b_preinc_to_preinc: ; reg pre-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @+ers, @+erd + + mov.l #byte_src-1, er1 + mov.l #byte_dst-1, er0 + mov.b @+er1, @+er0 +;;; .word 0x0178 +;;; .word 0x9190 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst er0 + test_h_gr32 byte_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext85 + fail +.Lnext85: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext86 + fail +.Lnext86: ; OK, pass on. + +mov_b_predec_to_predec: ; reg pre-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @-ers, @-erd + + mov.l #byte_src+1, er1 + mov.l #byte_dst+1, er0 + mov.b @-er1, @-er0 +;;; .word 0x0178 +;;; .word 0xb1b0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst er0 + test_h_gr32 byte_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext95 + fail +.Lnext95: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext96 + fail +.Lnext96: ; OK, pass on. + +mov_b_disp2_to_disp2: ; reg 2-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:2, ers), @(dd:2, erd) + + mov.l #byte_src-1, er1 + mov.l #byte_dst-2, er0 + mov.b @(1:2, er1), @(2:2, er0) +;;; .word 0x0178 +;;; .word 0x1120 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst-2 er0 + test_h_gr32 byte_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext105 + fail +.Lnext105: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext106 + fail +.Lnext106: ; OK, pass on. + +mov_b_disp16_to_disp16: ; reg 16-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:16, ers), @(dd:16, erd) + + mov.l #byte_src-1, er1 + mov.l #byte_dst-2, er0 + mov.b @(1:16, er1), @(2:16, er0) +;;; .word 0x0178 +;;; .word 0xc1c0 +;;; .word 0x0001 +;;; .word 0x0002 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst-2 er0 + test_h_gr32 byte_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext115 + fail +.Lnext115: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext116 + fail +.Lnext116: ; OK, pass on. + +mov_b_disp32_to_disp32: ; reg 32-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:32, ers), @(dd:32, erd) + + mov.l #byte_src-1, er1 + mov.l #byte_dst-2, er0 + mov.b @(1:32, er1), @(2:32, er0) +;;; .word 0x0178 +;;; .word 0xc9c8 +;;; .long 1 +;;; .long 2 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst-2 er0 + test_h_gr32 byte_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext125 + fail +.Lnext125: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext126 + fail +.Lnext126: ; OK, pass on. + +mov_b_indexb16_to_indexb16: ; reg 16-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + mov.l #0xffffff02, er0 + ;; mov.b @(dd:16, rs.b), @(dd:16, rd.b) + set_ccr_zero + mov.b @(byte_src-1:16, r1.b), @(byte_dst-2:16, r0.b) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0xffffff02 er0 + test_h_gr32 0xffffff01 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexw16_to_indewb16: ; reg 16-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0003, er1 + mov.l #0xffff0004, er0 + ;; mov.b @(dd:16, rs.w), @(dd:16, rd.w) + set_ccr_zero + mov.b @(byte_src-3:16, r1.w), @(byte_dst-4:16, r0.w) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0xffff0004 er0 + test_h_gr32 0xffff0003 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexl16_to_indexl16: ; reg 16-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000005, er1 + mov.l #0x00000006, er0 + ;; mov.b @(dd:16, ers.l), @(dd:16, erd.l) + set_ccr_zero + mov.b @(byte_src-5:16, er1.l), @(byte_dst-6:16, er0.l) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0x00000006 er0 + test_h_gr32 0x00000005 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexb32_to_indexb32: ; reg 32-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + mov.l #0xffffff02, er0 + set_ccr_zero + ;; mov.b @(dd:32, rs.b), @(dd:32, rd.b) + mov.b @(byte_src-1:32, r1.b), @(byte_dst-2:32, r0.b) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0xffffff02 er0 + test_h_gr32 0xffffff01 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexw32_to_indexw32: ; reg 32-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0003, er1 + mov.l #0xffff0004, er0 + set_ccr_zero + ;; mov.b @(dd:32, rs.w), @(dd:32, rd.w) + mov.b @(byte_src-3:32, r1.w), @(byte_dst-4:32, r0.w) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0xffff0004 er0 + test_h_gr32 0xffff0003 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexl32_to_indexl32: ; reg 32-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000005, er1 + mov.l #0x00000006, er0 + set_ccr_zero + ;; mov.b @(dd:32, rs.w), @(dd:32, rd.w) + mov.b @(byte_src-5:32, er1.l), @(byte_dst-6:32, er0.l) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0x00000006 er0 + test_h_gr32 0x00000005 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_abs16_to_abs16: ; 16-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @aa:16, @aa:16 + + mov.b @byte_src:16, @byte_dst:16 +;;; .word 0x0178 +;;; .word 0x4040 +;;; .word @byte_src +;;; .word @byte_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext135 + fail +.Lnext135: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext136 + fail +.Lnext136: ; OK, pass on. + +mov_b_abs32_to_abs32: ; 32-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @aa:32, @aa:32 + + mov.b @byte_src:32, @byte_dst:32 +;;; .word 0x0178 +;;; .word 0x4848 +;;; .long @byte_src +;;; .long @byte_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext145 + fail +.Lnext145: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext146 + fail +.Lnext146: ; OK, pass on. + + +.endif + + pass + + exit 0 + +fail1: + fail + \ No newline at end of file diff --git a/sim/testsuite/h8300/movl.s b/sim/testsuite/h8300/movl.s new file mode 100644 index 0000000..dcc3922 --- /dev/null +++ b/sim/testsuite/h8300/movl.s @@ -0,0 +1,2160 @@ +# Hitachi H8 testcase 'mov.l' +# mach(): h8300h h8300s h8sx +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 4 +long_src: + .long 0x77777777 +long_dst: + .long 0 + + .text + + ;; + ;; Move long from immediate source + ;; + +.if (sim_cpu == h8sx) +mov_l_imm3_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:3, erd + mov.l #0x3:3, er0 ; Immediate 3-bit operand +;;; .word 0x0fb8 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x3 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_imm16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, erd + mov.l #0x1234, er0 ; Immediate 16-bit operand +;;; .word 0x7a08 +;;; .word 0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x1234 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_l_imm32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, erd + mov.l #0x12345678, er0 ; Immediate 32-bit operand +;;; .word 0x7a00 +;;; .long 0x12345678 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x12345678 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_l_imm8_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @erd + mov.l #long_dst, er1 + mov.l #0xa5:8, @er1 ; Register indirect operand +;;; .word 0x010d +;;; .word 0x01a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext1 + fail +.Lnext1: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_postinc: ; post-increment from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @erd+ + mov.l #long_dst, er1 + mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands. +;;; .word 0x010d +;;; .word 0x81a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext2 + fail +.Lnext2: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_postdec: ; post-decrement from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @erd- + mov.l #long_dst, er1 + mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands. +;;; .word 0x010d +;;; .word 0xa1a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext3 + fail +.Lnext3: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @+erd + mov.l #long_dst-4, er1 + mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands +;;; .word 0x010d +;;; .word 0x91a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext4 + fail +.Lnext4: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @-erd + mov.l #long_dst+4, er1 + mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands +;;; .word 0x010d +;;; .word 0xb1a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext5 + fail +.Lnext5: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @(dd:2, erd) + mov.l #long_dst-12, er1 + mov.l #0xa5:8, @(12:2, er1) ; Imm8, reg plus 2-bit disp. operand +;;; .word 0x010d +;;; .word 0x31a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext6 + fail +.Lnext6: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @(dd:16, erd) + mov.l #long_dst-4, er1 + mov.l #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x010d +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext7 + fail +.Lnext7: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @(dd:32, erd) + mov.l #long_dst-8, er1 + mov.l #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x010d +;;; .word 0xc9a5 +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext8 + fail +.Lnext8: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @aa:16 + mov.l #0xa5:8, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x010d +;;; .word 0x40a5 +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext9 + fail +.Lnext9: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @aa:32 + mov.l #0xa5:8, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x010d +;;; .word 0x48a5 +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext10 + fail +.Lnext10: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @erd + mov.l #long_dst, er1 + mov.l #0xdead:16, @er1 ; Register indirect operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x0100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext11 + fail +.Lnext11: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_postinc: ; post-increment from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @erd+ + mov.l #long_dst, er1 + mov.l #0xdead:16, @er1+ ; Imm16, register post-incr operands. +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x8100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext12 + fail +.Lnext12: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_postdec: ; post-decrement from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @erd- + mov.l #long_dst, er1 + mov.l #0xdead:16, @er1- ; Imm16, register post-decr operands. +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0xa100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext13 + fail +.Lnext13: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @+erd + mov.l #long_dst-4, er1 + mov.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x9100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext14 + fail +.Lnext14: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @-erd + mov.l #long_dst+4, er1 + mov.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0xb100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext15 + fail +.Lnext15: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @(dd:2, erd) + mov.l #long_dst-12, er1 + mov.l #0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x3100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext16 + fail +.Lnext16: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @(dd:16, erd) + mov.l #long_dst-4, er1 + mov.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0xc100 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext17 + fail +.Lnext17: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @(dd:32, erd) + mov.l #long_dst-8, er1 + mov.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0xc900 +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext18 + fail +.Lnext18: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @aa:16 + mov.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x4000 +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext19 + fail +.Lnext19: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @aa:32 + mov.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x4800 +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext20 + fail +.Lnext20: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @erd + mov.l #long_dst, er1 + mov.l #0xcafedead:32, @er1 ; Register indirect operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x0100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext21 + fail +.Lnext21: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_postinc: ; post-increment from imm32 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @erd+ + mov.l #long_dst, er1 + mov.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands. +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x8100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext22 + fail +.Lnext22: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_postdec: ; post-decrement from imm32 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @erd- + mov.l #long_dst, er1 + mov.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands. +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0xa100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext23 + fail +.Lnext23: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @+erd + mov.l #long_dst-4, er1 + mov.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x9100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext24 + fail +.Lnext24: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @-erd + mov.l #long_dst+4, er1 + mov.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0xb100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext25 + fail +.Lnext25: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @(dd:2, erd) + mov.l #long_dst-12, er1 + mov.l #0xcafedead:32, @(12:2, er1) ; Imm32, reg plus 2-bit disp. operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x3100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext26 + fail +.Lnext26: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @(dd:16, erd) + mov.l #long_dst-4, er1 + mov.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0xc100 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext27 + fail +.Lnext27: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @(dd:32, erd) + mov.l #long_dst-8, er1 + mov.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0xc900 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext28 + fail +.Lnext28: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @aa:16 + mov.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x4000 +;;; .word @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext29 + fail +.Lnext29: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @aa:32 + mov.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x4800 +;;; .long @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext30 + fail +.Lnext30: + mov.l #0, @long_dst ; zero it again for the next use. + +.endif + + ;; + ;; Move long from register source + ;; + +mov_l_reg32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, erd + mov.l #0x12345678, er1 + mov.l er1, er0 ; Register 32-bit operand +;;; .word 0x0f90 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + test_h_gr32 0x12345678 er0 + test_h_gr32 0x12345678 er1 ; mov src unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_reg32_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @erd + mov.l #long_dst, er1 + mov.l er0, @er1 ; Register indirect operand +;;; .word 0x0100 +;;; .word 0x6990 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er2, er0 + beq .Lnext44 + fail +.Lnext44: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_l_reg32_to_postinc: ; post-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @erd+ + mov.l #long_dst, er1 + mov.l er0, @er1+ ; Register post-incr operand +;;; .word 0x0103 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l er2, @long_dst + beq .Lnext49 + fail +.Lnext49: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_postdec: ; post-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @erd- + mov.l #long_dst, er1 + mov.l er0, @er1- ; Register post-decr operand +;;; .word 0x0101 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l er2, @long_dst + beq .Lnext50 + fail +.Lnext50: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @+erd + mov.l #long_dst-4, er1 + mov.l er0, @+er1 ; Register pre-incr operand +;;; .word 0x0102 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l er2, @long_dst + beq .Lnext51 + fail +.Lnext51: + mov.l #0, @long_dst ; zero it again for the next use. +.endif ; h8sx + +mov_l_reg32_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @-erd + mov.l #long_dst+4, er1 + mov.l er0, @-er1 ; Register pre-decr operand +;;; .word 0x0100 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er2, er0 + beq .Lnext48 + fail +.Lnext48: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_l_reg32_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @(dd:2, erd) + mov.l #long_dst-12, er1 + mov.l er0, @(12:2, er1) ; Register plus 2-bit disp. operand +;;; .word 0x0103 +;;; .word 0x6990 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l er2, @long_dst + beq .Lnext52 + fail +.Lnext52: + mov.l #0, @long_dst ; zero it again for the next use. +.endif ; h8sx + +mov_l_reg32_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @(dd:16, erd) + mov.l #long_dst-4, er1 + mov.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x0100 +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er2, er0 + beq .Lnext45 + fail +.Lnext45: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @(dd:32, erd) + mov.l #long_dst-8, er1 + mov.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7890 +;;; .word 0x6ba0 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er2, er0 + beq .Lnext46 + fail +.Lnext46: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @aa:16 + mov.l er0, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x0100 +;;; .word 0x6b80 +;;; .word @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er0, er1 + beq .Lnext41 + fail +.Lnext41: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @aa:32 + mov.l er0, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x0100 +;;; .word 0x6ba0 +;;; .long @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er0, er1 + beq .Lnext42 + fail +.Lnext42: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + + ;; + ;; Move long to register destination. + ;; + +mov_l_indirect_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers, erd + mov.l #long_src, er1 + mov.l @er1, er0 ; Register indirect operand +;;; .word 0x0100 +;;; .word 0x6910 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_postinc_to_reg32: ; post-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers+, erd + + mov.l #long_src, er1 + mov.l @er1+, er0 ; Register post-incr operand +;;; .word 0x0100 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src+4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_l_postdec_to_reg32: ; post-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers-, erd + + mov.l #long_src, er1 + mov.l @er1-, er0 ; Register post-decr operand +;;; .word 0x0102 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src-4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_preinc_to_reg32: ; pre-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @+ers, erd + + mov.l #long_src-4, er1 + mov.l @+er1, er0 ; Register pre-incr operand +;;; .word 0x0101 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_predec_to_reg32: ; pre-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @-ers, erd + + mov.l #long_src+4, er1 + mov.l @-er1, er0 ; Register pre-decr operand +;;; .word 0x0103 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_l_disp2_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:2, ers), erd + mov.l #long_src-4, er1 + mov.l @(4:2, er1), er0 ; Register plus 2-bit disp. operand +;;; .word 0x0101 +;;; .word 0x6910 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src-4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +mov_l_disp16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:16, ers), erd + mov.l #long_src+0x1234, er1 + mov.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand +;;; .word 0x0100 +;;; .word 0x6f10 +;;; .word -0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src+0x1234, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_disp32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:32, ers), erd + mov.l #long_src+65536, er1 + mov.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand +;;; .word 0x7890 +;;; .word 0x6b20 +;;; .long -65536 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src+65536, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_abs16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @aa:16, erd + mov.l @long_src:16, er0 ; 16-bit address-direct operand +;;; .word 0x0100 +;;; .word 0x6b00 +;;; .word @long_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_abs32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @aa:32, erd + mov.l @long_src:32, er0 ; 32-bit address-direct operand +;;; .word 0x0100 +;;; .word 0x6b20 +;;; .long @long_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +.if (sim_cpu == h8sx) + + ;; + ;; Move long from memory to memory + ;; + +mov_l_indirect_to_indirect: ; reg indirect, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers, @erd + + mov.l #long_src, er1 + mov.l #long_dst, er0 + mov.l @er1, @er0 +;;; .word 0x0108 +;;; .word 0x0100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext55 + fail +.Lnext55: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext56 + fail +.Lnext56: ; OK, pass on. + +mov_l_postinc_to_postinc: ; reg post-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers+, @erd+ + + mov.l #long_src, er1 + mov.l #long_dst, er0 + mov.l @er1+, @er0+ +;;; .word 0x0108 +;;; .word 0x8180 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst+4 er0 + test_h_gr32 long_src+4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext65 + fail +.Lnext65: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext66 + fail +.Lnext66: ; OK, pass on. + +mov_l_postdec_to_postdec: ; reg post-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers-, @erd- + + mov.l #long_src, er1 + mov.l #long_dst, er0 + mov.l @er1-, @er0- +;;; .word 0x0108 +;;; .word 0xa1a0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-4 er0 + test_h_gr32 long_src-4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext75 + fail +.Lnext75: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext76 + fail +.Lnext76: ; OK, pass on. + +mov_l_preinc_to_preinc: ; reg pre-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @+ers, @+erd + + mov.l #long_src-4, er1 + mov.l #long_dst-4, er0 + mov.l @+er1, @+er0 +;;; .word 0x0108 +;;; .word 0x9190 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext85 + fail +.Lnext85: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext86 + fail +.Lnext86: ; OK, pass on. + +mov_l_predec_to_predec: ; reg pre-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @-ers, @-erd + + mov.l #long_src+4, er1 + mov.l #long_dst+4, er0 + mov.l @-er1, @-er0 +;;; .word 0x0108 +;;; .word 0xb1b0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext95 + fail +.Lnext95: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext96 + fail +.Lnext96: ; OK, pass on. + +mov_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:2, ers), @(dd:2, erd) + + mov.l #long_src-4, er1 + mov.l #long_dst-8, er0 + mov.l @(4:2, er1), @(8:2, er0) +;;; .word 0x0108 +;;; .word 0x1120 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-8 er0 + test_h_gr32 long_src-4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext105 + fail +.Lnext105: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext106 + fail +.Lnext106: ; OK, pass on. + +mov_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:16, ers), @(dd:16, erd) + + mov.l #long_src-1, er1 + mov.l #long_dst-2, er0 + mov.l @(1:16, er1), @(2:16, er0) +;;; .word 0x0108 +;;; .word 0xc1c0 +;;; .word 0x0001 +;;; .word 0x0002 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-2 er0 + test_h_gr32 long_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext115 + fail +.Lnext115: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext116 + fail +.Lnext116: ; OK, pass on. + +mov_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:32, ers), @(dd:32, erd) + + mov.l #long_src-1, er1 + mov.l #long_dst-2, er0 + mov.l @(1:32, er1), @(2:32, er0) +;;; .word 0x0108 +;;; .word 0xc9c8 +;;; .long 1 +;;; .long 2 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-2 er0 + test_h_gr32 long_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext125 + fail +.Lnext125: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext126 + fail +.Lnext126: ; OK, pass on. + +mov_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @aa:16, @aa:16 + + mov.l @long_src:16, @long_dst:16 +;;; .word 0x0108 +;;; .word 0x4040 +;;; .word @long_src +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext135 + fail +.Lnext135: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext136 + fail +.Lnext136: ; OK, pass on. + +mov_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @aa:32, @aa:32 + + mov.l @long_src:32, @long_dst:32 +;;; .word 0x0108 +;;; .word 0x4848 +;;; .long @long_src +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext145 + fail +.Lnext145: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext146 + fail +.Lnext146: ; OK, pass on. + + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/h8300/movmd.s b/sim/testsuite/h8300/movmd.s new file mode 100644 index 0000000..fefdc33 --- /dev/null +++ b/sim/testsuite/h8300/movmd.s @@ -0,0 +1,129 @@ +# Hitachi H8 testcase 'movmd' +# mach(): h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_src: + .byte 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 +byte_dst: + .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + + .align 2 +word_src: + .word 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 +word_dst: + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + + .align 4 +long_src: + .long 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 +long_dst: + .long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + + start +.if (sim_cpu == h8sx) +movmd_b:# + # Byte block transfer + # + set_grs_a5a5 + + mov #byte_src, er5 + mov #byte_dst, er6 + mov #10, r4 + set_ccr_zero + ;; movmd.b + movmd.b +;;; .word 0x7b94 + + test_cc_clear + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 0xa5a50000 er4 + test_h_gr32 byte_src+10 er5 + test_h_gr32 byte_dst+10 er6 + test_gr_a5a5 7 + + # + # Now make sure exactly 10 bytes were transferred. + memcmp byte_src byte_dst 10 + cmp.b #0, @byte_dst+10 + beq .L0 + fail +.L0: + +movmd_w:# + # Word block transfer + # + set_grs_a5a5 + + mov #word_src, er5 + mov #word_dst, er6 + mov #10, r4 + set_ccr_zero + ;; movmd.w + movmd.w +;;; .word 0x7ba4 + + test_cc_clear + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 0xa5a50000 er4 + test_h_gr32 word_src+20 er5 + test_h_gr32 word_dst+20 er6 + test_gr_a5a5 7 + + # + # Now make sure exactly 20 bytes were transferred. + memcmp word_src word_dst 20 + cmp.w #0, @word_dst+20 + beq .L1 + fail +.L1: + +movmd_l:# + # Long block transfer + # + set_grs_a5a5 + + mov #long_src, er5 + mov #long_dst, er6 + mov #10, r4 + set_ccr_zero + ;; movmd.b + movmd.l +;;; .word 0x7bb4 + + test_cc_clear + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 0xa5a50000 er4 + test_h_gr32 long_src+40 er5 + test_h_gr32 long_dst+40 er6 + test_gr_a5a5 7 + + # + # Now make sure exactly 40 bytes were transferred. + memcmp long_src long_dst 40 + cmp.l #0, @long_dst+40 + beq .L2 + fail +.L2: + +.endif + pass + + exit 0 diff --git a/sim/testsuite/h8300/movsd.s b/sim/testsuite/h8300/movsd.s new file mode 100644 index 0000000..2689c53 --- /dev/null +++ b/sim/testsuite/h8300/movsd.s @@ -0,0 +1,100 @@ +# Hitachi H8 testcase 'movsd' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +src: .byte 'h', 'e', 'l', 'l', 'o', 0 +dst1: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +dst2: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + + start +.if (sim_cpu == h8sx) +movsd_n:# + # In this test, the transfer will stop after n bytes. + # + set_grs_a5a5 + + mov #src, er5 + mov #dst1, er6 + mov #4, r4 + set_ccr_zero + ;; movsd.b disp:16 + movsd.b fail1:16 +;;; .word 0x7b84 +;;; .word 0x02 + + bra pass1 +fail1: fail +pass1: test_cc_clear + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 0xa5a50000 er4 + test_h_gr32 src+4 er5 + test_h_gr32 dst1+4 er6 + test_gr_a5a5 7 + + # + # Now make sure exactly 4 bytes were transferred. + cmp.b @src, @dst1 + bne fail1:16 + cmp.b @src+1, @dst1+1 + bne fail1:16 + cmp.b @src+2, @dst1+2 + bne fail1:16 + cmp.b @src+3, @dst1+3 + bne fail1:16 + cmp.b @src+4, @dst1+4 + beq fail1:16 + +movsd_s:# + # In this test, the entire null-terminated string is transferred. + # + set_grs_a5a5 + + mov #src, er5 + mov #dst2, er6 + mov #8, r4 + set_ccr_zero + ;; movsd.b disp:16 + movsd.b pass2:16 +;;; .word 0x7b84 +;;; .word 0x10 + +fail2: fail +pass2: test_cc_clear + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 0xa5a50002 er4 + test_h_gr32 src+6 er5 + test_h_gr32 dst2+6 er6 + test_gr_a5a5 7 + # + # Now make sure 5 bytes were transferred, and the 6th is zero. + cmp.b @src, @dst2 + bne fail2:16 + cmp.b @src+1, @dst2+1 + bne fail2:16 + cmp.b @src+2, @dst2+2 + bne fail2:16 + cmp.b @src+3, @dst2+3 + bne fail2:16 + cmp.b @src+4, @dst2+4 + bne fail2:16 + cmp.b #0, @dst2+5 + bne fail2:16 +.endif + pass + + exit 0 diff --git a/sim/testsuite/h8300/movw.s b/sim/testsuite/h8300/movw.s new file mode 100644 index 0000000..b8b09ea --- /dev/null +++ b/sim/testsuite/h8300/movw.s @@ -0,0 +1,1857 @@ +# Hitachi H8 testcase 'mov.w' +# mach(): h8300h h8300s h8sx +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 2 +word_src: + .word 0x7777 +word_dst: + .word 0 + + .text + + ;; + ;; Move word from immediate source + ;; + +.if (sim_cpu == h8sx) +mov_w_imm3_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:3, rd + mov.w #0x3:3, r0 ; Immediate 3-bit operand +;;; .word 0x0f30 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a50003 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_w_imm16_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, rd + mov.w #0x1234, r0 ; Immediate 16-bit operand +;;; .word 0x7900 +;;; .word 0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a51234 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_w_imm4_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:4, @aa:16 + mov.w #0xf:4, @word_dst:16 ; 4-bit imm to 16-bit address-direct +;;; .word 0x6bdf +;;; .word @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xf, @word_dst + beq .Lnext21 + fail +.Lnext21: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm4_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:4, @aa:32 + mov.w #0xf:4, @word_dst:32 ; 4-bit imm to 32-bit address-direct +;;; .word 0x6bff +;;; .long @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xf, @word_dst + beq .Lnext22 + fail +.Lnext22: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @erd + mov.l #word_dst, er1 + mov.w #0xa5:8, @er1 ; Register indirect operand +;;; .word 0x015d +;;; .word 0x01a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext1 + fail +.Lnext1: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_postinc: ; post-increment from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @erd+ + mov.l #word_dst, er1 + mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands. +;;; .word 0x015d +;;; .word 0x81a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst+2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext2 + fail +.Lnext2: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_postdec: ; post-decrement from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @erd- + mov.l #word_dst, er1 + mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands. +;;; .word 0x015d +;;; .word 0xa1a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext3 + fail +.Lnext3: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @+erd + mov.l #word_dst-2, er1 + mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands +;;; .word 0x015d +;;; .word 0x91a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext4 + fail +.Lnext4: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @-erd + mov.l #word_dst+2, er1 + mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands +;;; .word 0x015d +;;; .word 0xb1a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext5 + fail +.Lnext5: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @(dd:2, erd) + mov.l #word_dst-6, er1 + mov.w #0xa5:8, @(6:2, er1) ; Imm8, reg plus 2-bit disp. operand +;;; .word 0x015d +;;; .word 0x31a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-6, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext6 + fail +.Lnext6: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @(dd:16, erd) + mov.l #word_dst-4, er1 + mov.w #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x015d +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext7 + fail +.Lnext7: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @(dd:32, erd) + mov.l #word_dst-8, er1 + mov.w #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x015d +;;; .word 0xc9a5 +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext8 + fail +.Lnext8: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @aa:16 + mov.w #0xa5:8, @word_dst:16 ; 16-bit address-direct operand +;;; .word 0x015d +;;; .word 0x40a5 +;;; .word @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext9 + fail +.Lnext9: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @aa:32 + mov.w #0xa5:8, @word_dst:32 ; 32-bit address-direct operand +;;; .word 0x015d +;;; .word 0x48a5 +;;; .long @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext10 + fail +.Lnext10: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @erd + mov.l #word_dst, er1 + mov.w #0xdead:16, @er1 ; Register indirect operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x0100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext11 + fail +.Lnext11: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_postinc: ; post-increment from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @erd+ + mov.l #word_dst, er1 + mov.w #0xdead:16, @er1+ ; Imm16, register post-incr operands. +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x8100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst+2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext12 + fail +.Lnext12: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_postdec: ; post-decrement from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @erd- + mov.l #word_dst, er1 + mov.w #0xdead:16, @er1- ; Imm16, register post-decr operands. +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0xa100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext13 + fail +.Lnext13: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @+erd + mov.l #word_dst-2, er1 + mov.w #0xdead:16, @+er1 ; Imm16, register pre-incr operands +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x9100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext14 + fail +.Lnext14: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @-erd + mov.l #word_dst+2, er1 + mov.w #0xdead:16, @-er1 ; Imm16, register pre-decr operands +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0xb100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext15 + fail +.Lnext15: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @(dd:2, erd) + mov.l #word_dst-6, er1 + mov.w #0xdead:16, @(6:2, er1) ; Imm16, reg plus 2-bit disp. operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x3100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-6, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext16 + fail +.Lnext16: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @(dd:16, erd) + mov.l #word_dst-4, er1 + mov.w #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0xc100 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext17 + fail +.Lnext17: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @(dd:32, erd) + mov.l #word_dst-8, er1 + mov.w #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0xc900 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext18 + fail +.Lnext18: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @aa:16 + mov.w #0xdead:16, @word_dst:16 ; 16-bit address-direct operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x4000 +;;; .word @word_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext19 + fail +.Lnext19: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @aa:32 + mov.w #0xdead:16, @word_dst:32 ; 32-bit address-direct operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x4800 +;;; .long @word_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext20 + fail +.Lnext20: + mov.w #0, @word_dst ; zero it again for the next use. +.endif + + ;; + ;; Move word from register source + ;; + +mov_w_reg16_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, erd + mov.w #0x1234, r1 + mov.w r1, r0 ; Register 16-bit operand +;;; .word 0x0d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + test_h_gr16 0x1234 r0 + test_h_gr16 0x1234 r1 ; mov src unchanged +.if (sim_cpu) + test_h_gr32 0xa5a51234 er0 + test_h_gr32 0xa5a51234 er1 ; mov src unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_w_reg16_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @erd + mov.l #word_dst, er1 + mov.w r0, @er1 ; Register indirect operand +;;; .word 0x6990 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r2, r0 + beq .Lnext44 + fail +.Lnext44: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_w_reg16_to_postinc: ; post-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @erd+ + mov.l #word_dst, er1 + mov.w r0, @er1+ ; Register post-incr operand +;;; .word 0x0153 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst+2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w r2, @word_dst + beq .Lnext49 + fail +.Lnext49: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_postdec: ; post-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @erd- + mov.l #word_dst, er1 + mov.w r0, @er1- ; Register post-decr operand +;;; .word 0x0151 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w r2, @word_dst + beq .Lnext50 + fail +.Lnext50: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @+erd + mov.l #word_dst-2, er1 + mov.w r0, @+er1 ; Register pre-incr operand +;;; .word 0x0152 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w r2, @word_dst + beq .Lnext51 + fail +.Lnext51: + mov.w #0, @word_dst ; zero it again for the next use. +.endif + +mov_w_reg16_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @-erd + mov.l #word_dst+2, er1 + mov.w r0, @-er1 ; Register pre-decr operand +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r2, r0 + beq .Lnext48 + fail +.Lnext48: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_w_reg16_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @(dd:2, erd) + mov.l #word_dst-6, er1 + mov.w r0, @(6:2, er1) ; Register plus 2-bit disp. operand +;;; .word 0x0153 +;;; .word 0x6990 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-6, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w r2, @word_dst + beq .Lnext52 + fail +.Lnext52: + mov.w #0, @word_dst ; zero it again for the next use. +.endif + +mov_w_reg16_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @(dd:16, erd) + mov.l #word_dst-4, er1 + mov.w r0, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 word_dst-4, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r2, r0 + beq .Lnext45 + fail +.Lnext45: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @(dd:32, erd) + mov.l #word_dst-8, er1 + mov.w r0, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7810 +;;; .word 0x6ba0 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 word_dst-8, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r2, r0 + beq .Lnext46 + fail +.Lnext46: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @aa:16 + mov.w r0, @word_dst:16 ; 16-bit address-direct operand +;;; .word 0x6b80 +;;; .word @word_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r0, r1 + beq .Lnext41 + fail +.Lnext41: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @aa:32 + mov.w r0, @word_dst:32 ; 32-bit address-direct operand +;;; .word 0x6ba0 +;;; .long @word_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r0, r1 + beq .Lnext42 + fail +.Lnext42: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + + ;; + ;; Move word to register destination. + ;; + +mov_w_indirect_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers, rd + mov.l #word_src, er1 + mov.w @er1, r0 ; Register indirect operand +;;; .word 0x6910 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_postinc_to_reg16: ; post-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers+, rd + + mov.l #word_src, er1 + mov.w @er1+, r0 ; Register post-incr operand +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src+2, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_w_postdec_to_reg16: ; post-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers-, rd + + mov.l #word_src, er1 + mov.w @er1-, r0 ; Register post-decr operand +;;; .word 0x0152 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src-2, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_preinc_to_reg16: ; pre-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @+ers, rd + + mov.l #word_src-2, er1 + mov.w @+er1, r0 ; Register pre-incr operand +;;; .word 0x0151 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_predec_to_reg16: ; pre-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @-ers, rd + + mov.l #word_src+2, er1 + mov.w @-er1, r0 ; Register pre-decr operand +;;; .word 0x0153 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_w_disp2_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:2, ers), rd + mov.l #word_src-2, er1 + mov.w @(2:2, er1), r0 ; Register plus 2-bit disp. operand +;;; .word 0x0151 +;;; .word 0x6910 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 word_src-2, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_w_disp16_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:16, ers), rd + mov.l #word_src+0x1234, er1 + mov.w @(-0x1234:16, er1), r0 ; Register plus 16-bit disp. operand +;;; .word 0x6f10 +;;; .word -0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 word_src+0x1234, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_disp32_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:32, ers), rd + mov.l #word_src+65536, er1 + mov.w @(-65536:32, er1), r0 ; Register plus 32-bit disp. operand +;;; .word 0x7810 +;;; .word 0x6b20 +;;; .long -65536 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 word_src+65536, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_abs16_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @aa:16, rd + mov.w @word_src:16, r0 ; 16-bit address-direct operand +;;; .word 0x6b00 +;;; .word @word_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_abs32_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @aa:32, rd + mov.w @word_src:32, r0 ; 32-bit address-direct operand +;;; .word 0x6b20 +;;; .long @word_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + + ;; + ;; Move word from memory to memory + ;; + +mov_w_indirect_to_indirect: ; reg indirect, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers, @erd + + mov.l #word_src, er1 + mov.l #word_dst, er0 + mov.w @er1, @er0 +;;; .word 0x0158 +;;; .word 0x0100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst er0 + test_h_gr32 word_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext55 + fail +.Lnext55: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext56 + fail +.Lnext56: ; OK, pass on. + +mov_w_postinc_to_postinc: ; reg post-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers+, @erd+ + + mov.l #word_src, er1 + mov.l #word_dst, er0 + mov.w @er1+, @er0+ +;;; .word 0x0158 +;;; .word 0x8180 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst+2 er0 + test_h_gr32 word_src+2 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext65 + fail +.Lnext65: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext66 + fail +.Lnext66: ; OK, pass on. + +mov_w_postdec_to_postdec: ; reg post-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers-, @erd- + + mov.l #word_src, er1 + mov.l #word_dst, er0 + mov.w @er1-, @er0- +;;; .word 0x0158 +;;; .word 0xa1a0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst-2 er0 + test_h_gr32 word_src-2 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext75 + fail +.Lnext75: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext76 + fail +.Lnext76: ; OK, pass on. + +mov_w_preinc_to_preinc: ; reg pre-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @+ers, @+erd + + mov.l #word_src-2, er1 + mov.l #word_dst-2, er0 + mov.w @+er1, @+er0 +;;; .word 0x0158 +;;; .word 0x9190 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst er0 + test_h_gr32 word_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext85 + fail +.Lnext85: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext86 + fail +.Lnext86: ; OK, pass on. + +mov_w_predec_to_predec: ; reg pre-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @-ers, @-erd + + mov.l #word_src+2, er1 + mov.l #word_dst+2, er0 + mov.w @-er1, @-er0 +;;; .word 0x0158 +;;; .word 0xb1b0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst er0 + test_h_gr32 word_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext95 + fail +.Lnext95: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext96 + fail +.Lnext96: ; OK, pass on. + +mov_w_disp2_to_disp2: ; reg 2-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:2, ers), @(dd:2, erd) + + mov.l #word_src-2, er1 + mov.l #word_dst-4, er0 + mov.w @(2:2, er1), @(4:2, er0) +;;; .word 0x0158 +;;; .word 0x1120 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst-4 er0 + test_h_gr32 word_src-2 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext105 + fail +.Lnext105: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext106 + fail +.Lnext106: ; OK, pass on. + +mov_w_disp16_to_disp16: ; reg 16-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:16, ers), @(dd:16, erd) + + mov.l #word_src-1, er1 + mov.l #word_dst-2, er0 + mov.w @(1:16, er1), @(2:16, er0) +;;; .word 0x0158 +;;; .word 0xc1c0 +;;; .word 0x0001 +;;; .word 0x0002 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst-2 er0 + test_h_gr32 word_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext115 + fail +.Lnext115: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext116 + fail +.Lnext116: ; OK, pass on. + +mov_w_disp32_to_disp32: ; reg 32-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:32, ers), @(dd:32, erd) + + mov.l #word_src-1, er1 + mov.l #word_dst-2, er0 + mov.w @(1:32, er1), @(2:32, er0) +;;; .word 0x0158 +;;; .word 0xc9c8 +;;; .long 1 +;;; .long 2 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst-2 er0 + test_h_gr32 word_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext125 + fail +.Lnext125: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext126 + fail +.Lnext126: ; OK, pass on. + +mov_w_abs16_to_abs16: ; 16-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @aa:16, @aa:16 + + mov.w @word_src:16, @word_dst:16 +;;; .word 0x0158 +;;; .word 0x4040 +;;; .word @word_src +;;; .word @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext135 + fail +.Lnext135: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext136 + fail +.Lnext136: ; OK, pass on. + +mov_w_abs32_to_abs32: ; 32-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @aa:32, @aa:32 + + mov.w @word_src:32, @word_dst:32 +;;; .word 0x0158 +;;; .word 0x4848 +;;; .long @word_src +;;; .long @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext145 + fail +.Lnext145: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext146 + fail +.Lnext146: ; OK, pass on. + + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/h8300/mul.s b/sim/testsuite/h8300/mul.s new file mode 100644 index 0000000..02b9e9f --- /dev/null +++ b/sim/testsuite/h8300/mul.s @@ -0,0 +1,474 @@ +# Hitachi H8 testcase 'muls', 'muls/u', mulu', 'mulu/u', 'mulxs', 'mulxu' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) +muls_w_reg_reg: + set_grs_a5a5 + + ;; muls.w rs, rd + mov.w #32, r1 + mov.w #-2, r2 + set_ccr_zero + muls.w r2, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_h_gr32 0xa5a5fffe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_w_imm4_reg: + set_grs_a5a5 + + ;; muls.w xx:4, rd + mov.w #-32, r1 + set_ccr_zero + muls.w #2:4, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_l_reg_reg: + set_grs_a5a5 + + ;; muls.l ers, erd + mov.l #320000, er1 + mov.l #-2, er2 + set_ccr_zero + muls.l er2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -640000 er1 + test_h_gr32 -2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_l_imm4_reg: + set_grs_a5a5 + + ;; muls.l xx:4, rd + mov.l #-320000, er1 + set_ccr_zero + muls.l #2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -640000 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_u_l_reg_reg: + set_grs_a5a5 + + ;; muls/u.l ers, erd + mov.l #0x10000000, er1 + mov.l #-16, er2 + set_ccr_zero + muls/u.l er2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -1 er1 + test_h_gr32 -16 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_u_l_imm4_reg: + set_grs_a5a5 + + ;; muls/u.l xx:4, rd + mov.l #0xffffffff, er1 + set_ccr_zero + muls/u.l #2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -1 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_w_reg_reg: + set_grs_a5a5 + + ;; mulu.w rs, rd + mov.w #32, r1 + mov.w #-2, r2 + set_ccr_zero + mulu.w r2, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_h_gr32 0xa5a5fffe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_w_imm4_reg: + set_grs_a5a5 + + ;; mulu.w xx:4, rd + mov.w #32, r1 + set_ccr_zero + mulu.w #-2:4, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x1c0 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_l_reg_reg: + set_grs_a5a5 + + ;; mulu.l ers, erd + mov.l #320000, er1 + mov.l #-2, er2 + set_ccr_zero + mulu.l er2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 -640000 er1 + test_h_gr32 -2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_l_imm4_reg: + set_grs_a5a5 + + ;; mulu.l xx:4, rd + mov.l #320000, er1 + set_ccr_zero + mulu.l #-2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x445c00 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_u_l_reg_reg: + set_grs_a5a5 + + ;; mulu/u.l ers, erd + mov.l #0x10000000, er1 + mov.l #16, er2 + set_ccr_zero + mulu/u.l er2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 1 er1 + test_h_gr32 16 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_u_l_imm4_reg: + set_grs_a5a5 + + ;; mulu/u.l xx:4, rd + mov.l #0xffffffff, er1 + set_ccr_zero + mulu/u.l #2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x1 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; not equal to zero ie. not h8 +mulxs_b_reg_reg: + set_grs_a5a5 + + ;; mulxs.b rs, rd + mov.b #32, r1l + mov.b #-2, r2l + set_ccr_zero + mulxs.b r2l, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_h_gr32 0xa5a5a5fe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mulxs_b_imm4_reg: + set_grs_a5a5 + + ;; mulxs.b xx:4, rd + mov.w #-32, r1 + set_ccr_zero + mulxs.b #2:4, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +mulxs_w_reg_reg: + set_grs_a5a5 + + ;; mulxs.w ers, erd + mov.w #0x1000, r1 + mov.w #-0x1000, r2 + set_ccr_zero + mulxs.w r2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 0xff000000 er1 + test_h_gr32 0xa5a5f000 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mulxs_w_imm4_reg: + set_grs_a5a5 + + ;; mulxs.w xx:4, rd + mov.w #-1, r1 + set_ccr_zero + mulxs.w #2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -2 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx +.endif ; not h8 + +mulxu_b_reg_reg: + set_grs_a5a5 + + ;; mulxu.b rs, rd + mov.b #32, r1l + mov.b #-2, r2l + set_ccr_zero + mulxu.b r2l, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x1fc0 r1 + test_h_gr16 0xa5fe r2 +.if (sim_cpu) + test_h_gr32 0xa5a5a5fe er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; not h8 +.if (sim_cpu == h8sx) +mulxu_b_imm4_reg: + set_grs_a5a5 + + ;; mulxu.b xx:4, rd + mov.b #-32, r1l + set_ccr_zero + mulxu.b #2:4, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x1c0 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +mulxu_w_reg_reg: + set_grs_a5a5 + + ;; mulxu.w ers, erd + mov.w #0x1000, r1 + mov.w #-0x1000, r2 + set_ccr_zero + mulxu.w r2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x0f000000 er1 + test_h_gr32 0xa5a5f000 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mulxu_w_imm4_reg: + set_grs_a5a5 + + ;; mulxu.w xx:4, rd + mov.w #-1, r1 + set_ccr_zero + mulxu.w #2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x1fffe er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx +.endif ; not h8 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/neg.s b/sim/testsuite/h8300/neg.s new file mode 100644 index 0000000..de82476 --- /dev/null +++ b/sim/testsuite/h8300/neg.s @@ -0,0 +1,1022 @@ +# Hitachi H8 testcase 'neg.b, neg.w, neg.l' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # neg.b rd ; 1 7 8 rd + # neg.b @erd ; 7 d rd ???? 1 7 8 ignore + # neg.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 8 ignore + # neg.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 8 ignore + # neg.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 8 ignore + # neg.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 8 ignore + # neg.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 8 ignore + # neg.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 8 ignore + # neg.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 8 ignore + # neg.b @aa:16 ; 6 a 1 1??? aa:16 1 7 8 ignore + # neg.b @aa:32 ; 6 a 3 1??? aa:32 1 7 8 ignore + # word operations + # long operations + # + # Coming soon: + # neg.b @aa:8 ; 7 f aaaaaaaa 1 7 8 ignore + # + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + start + + # + # Note: apparently carry is set for neg of anything except zero. + # + + # + # 8-bit byte operations + # + +neg_b_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b Rd + neg r0l ; 8-bit register +;;; .word 0x1788 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5b, r0l ; result of "neg 0xa5" + beq .Lbrd + fail +.Lbrd: + test_h_gr16 0xa55b r0 ; r0 changed by 'neg' +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a55b er0 ; er0 changed by 'neg' +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +neg_b_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @eRd + mov #byte_dest, er0 + neg.b @er0 ; register indirect operand +;;; .word 0x7d00 +;;; .word 0x1780 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + cmp.b #0x5b, @er0 ; memory contents changed + beq .Lbind + fail +.Lbind: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @eRd+ + mov #byte_dest, er0 ; register post-increment operand + neg.b @er0+ +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1780 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one + cmp.b #0xa5, @-er0 + beq .Lbpostinc + fail +.Lbpostinc: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @eRd- + mov #byte_dest, er0 ; register post-decrement operand + neg.b @er0- +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1780 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one + cmp.b #0x5b, @+er0 + beq .Lbpostdec + fail +.Lbpostdec: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @+eRd + mov #byte_dest-1, er0 + neg.b @+er0 ; reg pre-increment operand +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1780 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5, @er0 + beq .Lbpreinc + fail +.Lbpreinc: + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @-eRd + mov #byte_dest+1, er0 + neg.b @-er0 ; reg pre-decr operand +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1780 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5b, @er0 + beq .Lbpredec + fail +.Lbpredec: + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_disp2dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @(dd:2, erd) + mov #byte_dest-1, er0 + neg.b @(1:2, er0) ; reg plus 2-bit displacement +;;; .word 0x0175 +;;; .word 0x6808 +;;; .word 0x1780 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5, @+er0 + beq .Lbdisp2 + fail +.Lbdisp2: + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_disp16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @(dd:16, erd) + mov #byte_dest+100, er0 + neg.b @(-100:16, er0) ; reg plus 16-bit displacement +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word -100 +;;; .word 0x1780 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5b, @byte_dest + beq .Lbdisp16 + fail +.Lbdisp16: + test_h_gr32 byte_dest+100 er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_disp32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @(dd:32, erd) + mov #byte_dest-0xfffff, er0 + neg.b @(0xfffff:32, er0) ; reg plus 32-bit displacement +;;; .word 0x7804 +;;; .word 0x6a28 +;;; .long 0xfffff +;;; .word 0x1780 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5, @byte_dest + beq .Lbdisp32 + fail +.Lbdisp32: + test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_abs16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @aa:16 + neg.b @byte_dest:16 ; 16-bit absolute address +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1780 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5b, @byte_dest + beq .Lbabs16 + fail +.Lbabs16: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_abs32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @aa:32 + neg.b @byte_dest:32 ; 32-bit absolute address +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1780 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5, @byte_dest + beq .Lbabs32 + fail +.Lbabs32: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + + # + # 16-bit word operations + # + +.if (sim_cpu) ; any except plain-vanilla h8/300 +neg_w_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w Rd + neg r1 ; 16-bit register operand +;;; .word 0x1791 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5b, r1 ; result of "neg 0xa5a5" + beq .Lwrd + fail +.Lwrd: + test_h_gr32 0xa5a55a5b er1 ; er1 changed by 'neg' + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +neg_w_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @eRd + mov #word_dest, er1 + neg.w @er1 ; register indirect operand +;;; .word 0x0154 +;;; .word 0x6d18 +;;; .word 0x1790 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5b, @word_dest ; memory contents changed + beq .Lwind + fail +.Lwind: + test_h_gr32 word_dest er1 ; er1 still contains address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @eRd+ + mov #word_dest, er1 ; register post-increment operand + neg.w @er1+ +;;; .word 0x0154 +;;; .word 0x6d18 +;;; .word 0x1790 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwpostinc + fail +.Lwpostinc: + test_h_gr32 word_dest+2 er1 ; er1 contains address plus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @eRd- + mov #word_dest, er1 + neg.w @er1- +;;; .word 0x0156 +;;; .word 0x6d18 +;;; .word 0x1790 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5b, @word_dest + beq .Lwpostdec + fail +.Lwpostdec: + test_h_gr32 word_dest-2 er1 ; er1 contains address minus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @+eRd + mov #word_dest-2, er1 + neg.w @+er1 ; reg pre-increment operand +;;; .word 0x0155 +;;; .word 0x6d18 +;;; .word 0x1790 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwpreinc + fail +.Lwpreinc: + test_h_gr32 word_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @-eRd + mov #word_dest+2, er1 + neg.w @-er1 ; reg pre-decr operand +;;; .word 0x0157 +;;; .word 0x6d18 +;;; .word 0x1790 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5b, @word_dest + beq .Lwpredec + fail +.Lwpredec: + test_h_gr32 word_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_disp2dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @(dd:2, erd) + mov #word_dest-2, er1 + neg.w @(2:2, er1) ; reg plus 2-bit displacement +;;; .word 0x0155 +;;; .word 0x6918 +;;; .word 0x1790 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwdisp2 + fail +.Lwdisp2: + test_h_gr32 word_dest-2 er1 ; er1 contains address minus one + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_disp16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @(dd:16, erd) + mov #word_dest+100, er1 + neg.w @(-100:16, er1) ; reg plus 16-bit displacement +;;; .word 0x0154 +;;; .word 0x6f18 +;;; .word -100 +;;; .word 0x1790 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5b, @word_dest + beq .Lwdisp16 + fail +.Lwdisp16: + test_h_gr32 word_dest+100 er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_disp32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @(dd:32, erd) + mov #word_dest-0xfffff, er1 + neg.w @(0xfffff:32, er1) ; reg plus 32-bit displacement +;;; .word 0x7814 +;;; .word 0x6b28 +;;; .long 0xfffff +;;; .word 0x1790 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwdisp32 + fail +.Lwdisp32: + test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_abs16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @aa:16 + neg.w @word_dest:16 ; 16-bit absolute address +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1790 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5b, @word_dest + beq .Lwabs16 + fail +.Lwabs16: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_abs32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @aa:32 + neg.w @word_dest:32 ; 32-bit absolute address +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1790 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwabs32 + fail +.Lwabs32: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif ; h8sx +.endif ; h8/300 + + # + # 32-bit word operations + # + +.if (sim_cpu) ; any except plain-vanilla h8/300 +neg_l_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l eRd + neg er1 ; 32-bit register operand +;;; .word 0x17b1 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5b, er1 ; result of "neg 0xa5a5a5a5" + beq .Llrd + fail +.Llrd: + test_h_gr32 0x5a5a5a5b er1 ; er1 changed by 'neg' + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +neg_l_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @eRd + mov #long_dest, er1 + neg.l @er1 ; register indirect operand +;;; .word 0x0104 +;;; .word 0x6d18 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5b, @long_dest ; memory contents changed + beq .Llind + fail +.Llind: + test_h_gr32 long_dest er1 ; er1 still contains address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @eRd+ + mov #long_dest, er1 ; register post-increment operand + neg.l @er1+ +;;; .word 0x0104 +;;; .word 0x6d18 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Llpostinc + fail +.Llpostinc: + test_h_gr32 long_dest+4 er1 ; er1 contains address plus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @eRd- + mov #long_dest, er1 + neg.l @er1- +;;; .word 0x0106 +;;; .word 0x6d18 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5b, @long_dest + beq .Llpostdec + fail +.Llpostdec: + test_h_gr32 long_dest-4 er1 ; er1 contains address minus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @+eRd + mov #long_dest-4, er1 + neg.l @+er1 ; reg pre-increment operand +;;; .word 0x0105 +;;; .word 0x6d18 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Llpreinc + fail +.Llpreinc: + test_h_gr32 long_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @-eRd + mov #long_dest+4, er1 + neg.l @-er1 ; reg pre-decr operand +;;; .word 0x0107 +;;; .word 0x6d18 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5b, @long_dest + beq .Llpredec + fail +.Llpredec: + test_h_gr32 long_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_disp2dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @(dd:2, erd) + mov #long_dest-4, er1 + neg.l @(4:2, er1) ; reg plus 2-bit displacement +;;; .word 0x0105 +;;; .word 0x6918 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Lldisp2 + fail +.Lldisp2: + test_h_gr32 long_dest-4 er1 ; er1 contains address minus one + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_disp16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @(dd:16, erd) + mov #long_dest+100, er1 + neg.l @(-100:16, er1) ; reg plus 16-bit displacement +;;; .word 0x0104 +;;; .word 0x6f18 +;;; .word -100 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5b, @long_dest + beq .Lldisp16 + fail +.Lldisp16: + test_h_gr32 long_dest+100 er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_disp32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @(dd:32, erd) + mov #long_dest-0xfffff, er1 + neg.l @(0xfffff:32, er1) ; reg plus 32-bit displacement +;;; .word 0x7894 +;;; .word 0x6b28 +;;; .long 0xfffff +;;; .word 0x17b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Lldisp32 + fail +.Lldisp32: + test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_abs16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @aa:16 + neg.l @long_dest:16 ; 16-bit absolute address +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x17b0 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5b, @long_dest + beq .Llabs16 + fail +.Llabs16: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_abs32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @aa:32 + neg.l @long_dest:32 ; 32-bit absolute address +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x17b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Llabs32 + fail +.Llabs32: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif ; h8sx +.endif ; h8/300 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/nop.s b/sim/testsuite/h8300/nop.s new file mode 100644 index 0000000..1d63b67 --- /dev/null +++ b/sim/testsuite/h8300/nop.s @@ -0,0 +1,26 @@ +# Hitachi H8 testcase 'nop' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +nop: set_grs_a5a5 + set_ccr_zero + + nop + + test_cc_clear + test_grs_a5a5 + + + pass + + exit 0 diff --git a/sim/testsuite/h8300/not.s b/sim/testsuite/h8300/not.s new file mode 100644 index 0000000..862c2b2 --- /dev/null +++ b/sim/testsuite/h8300/not.s @@ -0,0 +1,1009 @@ +# Hitachi H8 testcase 'not.b, not.w, not.l' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # not.b rd ; 1 7 0 rd + # not.b @erd ; 7 d rd ???? 1 7 0 ignore + # not.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 0 ignore + # not.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 0 ignore + # not.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 0 ignore + # not.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 0 ignore + # not.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 0 ignore + # not.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 0 ignore + # not.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 0 ignore + # not.b @aa:16 ; 6 a 1 1??? aa:16 1 7 0 ignore + # not.b @aa:32 ; 6 a 3 1??? aa:32 1 7 0 ignore + # word operations + # long operations + # + # Coming soon: + # not.b @aa:8 ; 7 f aaaaaaaa 1 7 0 ignore + # + +.data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + start + + # + # 8-bit byte operations + # + +not_b_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; not.b Rd + not r0l ; 8-bit register +;;; .word 0x1708 + + cmp.b #0x5a, r0l ; result of "not 0xa5" + beq .Lbrd + fail +.Lbrd: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa55a r0 ; r0 changed by 'not' +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a55a er0 ; er0 changed by 'not' +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +not_b_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @eRd + mov #byte_dest, er0 + not.b @er0 ; register indirect operand +;;; .word 0x7d00 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + cmp.b #0x5a:8, @er0 ; memory contents changed + beq .Lbind + fail +.Lbind: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @eRd+ + mov #byte_dest, er0 ; register post-increment operand + not.b @er0+ +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one + cmp.b #0xa5:8, @-er0 + beq .Lbpostinc + fail +.Lbpostinc: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @eRd- + mov #byte_dest, er0 ; register post-decrement operand + not.b @er0- +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one + cmp.b #0x5a:8, @+er0 +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xa05a + beq .Lbpostdec + fail +.Lbpostdec: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @+eRd + mov #byte_dest-1, er0 + not.b @+er0 ; reg pre-increment operand +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5:8, @er0 + beq .Lbpreinc + fail +.Lbpreinc: + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @-eRd + mov #byte_dest+1, er0 + not.b @-er0 ; reg pre-decr operand +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5a:8, @er0 + beq .Lbpredec + fail +.Lbpredec: + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_disp2dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @(dd:2, erd) + mov #byte_dest-1, er0 + not.b @(1:2, er0) ; reg plus 2-bit displacement +;;; .word 0x0175 +;;; .word 0x6808 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5:8, @+er0 + beq .Lbdisp2 + fail +.Lbdisp2: + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_disp16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @(dd:16, erd) + mov #byte_dest+100, er0 + not.b @(-100:16, er0) ; reg plus 16-bit displacement +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word -100 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5a:8, @byte_dest + beq .Lbdisp16 + fail +.Lbdisp16: + test_h_gr32 byte_dest+100 er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_disp32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @(dd:32, erd) + mov #byte_dest-0xfffff, er0 + not.b @(0xfffff:32, er0) ; reg plus 32-bit displacement +;;; .word 0x7804 +;;; .word 0x6a28 +;;; .long 0xfffff +;;; .word 0x1700 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5:8, @byte_dest + beq .Lbdisp32 + fail +.Lbdisp32: + test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_abs16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @aa:16 + not.b @byte_dest:16 ; 16-bit absolute address +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1700 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5a:8, @byte_dest + beq .Lbabs16 + fail +.Lbabs16: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_abs32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @aa:32 + not.b @byte_dest:32 ; 32-bit absolute address +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1700 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5:8, @byte_dest + beq .Lbabs32 + fail +.Lbabs32: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + + # + # 16-bit word operations + # + +.if (sim_cpu) ; any except plain-vanilla h8/300 +not_w_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; not.w Rd + not r1 ; 16-bit register operand +;;; .word 0x1711 + + cmp.w #0x5a5a, r1 ; result of "not 0xa5a5" + beq .Lwrd + fail +.Lwrd: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0xa5a55a5a er1 ; er1 changed by 'not' + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +not_w_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @eRd + mov #word_dest, er1 + not.w @er1 ; register indirect operand +;;; .word 0x0154 +;;; .word 0x6d18 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5a, @word_dest ; memory contents changed + beq .Lwind + fail +.Lwind: + test_h_gr32 word_dest er1 ; er1 still contains address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @eRd+ + mov #word_dest, er1 ; register post-increment operand + not.w @er1+ +;;; .word 0x0154 +;;; .word 0x6d18 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwpostinc + fail +.Lwpostinc: + test_h_gr32 word_dest+2 er1 ; er1 contains address plus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @eRd- + mov #word_dest, er1 + not.w @er1- +;;; .word 0x0156 +;;; .word 0x6d18 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5a, @word_dest + beq .Lwpostdec + fail +.Lwpostdec: + test_h_gr32 word_dest-2 er1 ; er1 contains address minus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @+eRd + mov #word_dest-2, er1 + not.w @+er1 ; reg pre-increment operand +;;; .word 0x0155 +;;; .word 0x6d18 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwpreinc + fail +.Lwpreinc: + test_h_gr32 word_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @-eRd + mov #word_dest+2, er1 + not.w @-er1 ; reg pre-decr operand +;;; .word 0x0157 +;;; .word 0x6d18 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5a, @word_dest + beq .Lwpredec + fail +.Lwpredec: + test_h_gr32 word_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_disp2dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @(dd:2, erd) + mov #word_dest-2, er1 + not.w @(2:2, er1) ; reg plus 2-bit displacement +;;; .word 0x0155 +;;; .word 0x6918 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwdisp2 + fail +.Lwdisp2: + test_h_gr32 word_dest-2 er1 ; er1 contains address minus one + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_disp16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @(dd:16, erd) + mov #word_dest+100, er1 + not.w @(-100:16, er1) ; reg plus 16-bit displacement +;;; .word 0x0154 +;;; .word 0x6f18 +;;; .word -100 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5a, @word_dest + beq .Lwdisp16 + fail +.Lwdisp16: + test_h_gr32 word_dest+100 er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_disp32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @(dd:32, erd) + mov #word_dest-0xfffff, er1 + not.w @(0xfffff:32, er1) ; reg plus 32-bit displacement +;;; .word 0x7814 +;;; .word 0x6b28 +;;; .long 0xfffff +;;; .word 0x1710 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwdisp32 + fail +.Lwdisp32: + test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_abs16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @aa:16 + not.w @word_dest:16 ; 16-bit absolute address +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1710 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5a, @word_dest + beq .Lwabs16 + fail +.Lwabs16: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_abs32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @aa:32 + not.w @word_dest:32 ; 32-bit absolute address +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1710 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwabs32 + fail +.Lwabs32: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif ; h8sx +.endif ; h8/300 + + # + # 32-bit word operations + # + +.if (sim_cpu) ; any except plain-vanilla h8/300 +not_l_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; not.l eRd + not er1 ; 32-bit register operand +;;; .word 0x1731 + + cmp.l #0x5a5a5a5a, er1 ; result of "not 0xa5a5a5a5" + beq .Llrd + fail +.Llrd: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0x5a5a5a5a er1 ; er1 changed by 'not' + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +not_l_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @eRd + mov #long_dest, er1 + not.l @er1 ; register indirect operand +;;; .word 0x0104 +;;; .word 0x6d18 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5a, @long_dest ; memory contents changed + beq .Llind + fail +.Llind: + test_h_gr32 long_dest er1 ; er1 still contains address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @eRd+ + mov #long_dest, er1 ; register post-increment operand + not.l @er1+ +;;; .word 0x0104 +;;; .word 0x6d18 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Llpostinc + fail +.Llpostinc: + test_h_gr32 long_dest+4 er1 ; er1 contains address plus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @eRd- + mov #long_dest, er1 + not.l @er1- +;;; .word 0x0106 +;;; .word 0x6d18 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5a, @long_dest + beq .Llpostdec + fail +.Llpostdec: + test_h_gr32 long_dest-4 er1 ; er1 contains address minus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @+eRd + mov #long_dest-4, er1 + not.l @+er1 ; reg pre-increment operand +;;; .word 0x0105 +;;; .word 0x6d18 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Llpreinc + fail +.Llpreinc: + test_h_gr32 long_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @-eRd + mov #long_dest+4, er1 + not.l @-er1 ; reg pre-decr operand +;;; .word 0x0107 +;;; .word 0x6d18 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5a, @long_dest + beq .Llpredec + fail +.Llpredec: + test_h_gr32 long_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_disp2dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @(dd:2, erd) + mov #long_dest-4, er1 + not.l @(4:2, er1) ; reg plus 2-bit displacement +;;; .word 0x0105 +;;; .word 0x6918 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Lldisp2 + fail +.Lldisp2: + test_h_gr32 long_dest-4 er1 ; er1 contains address minus one + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_disp16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @(dd:16, erd) + mov #long_dest+100, er1 + not.l @(-100:16, er1) ; reg plus 16-bit displacement +;;; .word 0x0104 +;;; .word 0x6f18 +;;; .word -100 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5a, @long_dest + beq .Lldisp16 + fail +.Lldisp16: + test_h_gr32 long_dest+100 er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_disp32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @(dd:32, erd) + mov #long_dest-0xfffff, er1 + not.l @(0xfffff:32, er1) ; reg plus 32-bit displacement +;;; .word 0x7894 +;;; .word 0x6b28 +;;; .long 0xfffff +;;; .word 0x1730 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Lldisp32 + fail +.Lldisp32: + test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_abs16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @aa:16 + not.l @long_dest:16 ; 16-bit absolute address +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1730 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5a, @long_dest + beq .Llabs16 + fail +.Llabs16: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_abs32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @aa:32 + not.l @long_dest:32 ; 32-bit absolute address +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1730 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Llabs32 + fail +.Llabs32: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif ; h8sx +.endif ; h8/300 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/orb.s b/sim/testsuite/h8300/orb.s new file mode 100644 index 0000000..72da8e6 --- /dev/null +++ b/sim/testsuite/h8300/orb.s @@ -0,0 +1,532 @@ +# Hitachi H8 testcase 'or.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # or.b #xx:8, rd ; c rd xxxxxxxx + # or.b #xx:8, @erd ; 7 d rd ???? c ???? xxxxxxxx + # or.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx + # or.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx + # or.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx + # or.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx + # or.b rs, rd ; 1 4 rs rd + # or.b reg8, @erd ; 7 d rd ???? 1 4 rs ???? + # or.b reg8, @erd+ ; 0 1 7 9 8 rd 4 rs + # or.b reg8, @erd- ; 0 1 7 9 a rd 4 rs + # or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs + # or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs + # + # orc #xx:8, ccr + # orc #xx:8, exr + + + # Coming soon: + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0xa5 +post_byte: .byte 0 + + start + +or_b_imm8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.b #xx:8,Rd + or.b #0xaa, r0l ; Immediate 8-bit src, reg8 dest + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5af r0 ; or result: a5 | aa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5af er0 ; or result: a5 | aa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +or_b_imm8_rdind: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@eRd + mov #byte_dest, er0 + or.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xc0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L1 + fail +.L1: + +or_b_imm8_rdpostinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@eRd+ + mov #byte_dest, er0 + or.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xc055 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xf5, r0l + beq .L2 + fail +.L2: + +or_b_imm8_rdpostdec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@eRd- + mov #byte_dest, er0 + or.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xc0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L3 + fail +.L3: + +or_b_imm8_rdpreinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@+eRd + mov #pre_byte, er0 + or.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xc055 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xf5, r0l + beq .L4 + fail +.L4: + +or_b_imm8_rdpredec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@-eRd + mov #post_byte, er0 + or.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xc0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L5 + fail +.L5: + + +.endif + +or_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.b Rs,Rd + mov.b #0xaa, r0h + or.b r0h, r0l ; Reg8 src, reg8 dest + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xaaaf r0 ; or result: a5 | aa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5aaaf er0 ; or result: a5 | aa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +or_b_reg8_rdind: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@eRd ; or reg8 to register indirect + mov #byte_dest, er0 + mov #0xaa, r1l + or.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1490 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L6 + fail +.L6: + +or_b_reg8_rdpostinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@eRd+ ; or reg8 to register indirect post-increment + mov #byte_dest, er0 + mov #0x55, r1l + or.b r1l, @er0+ ; reg8 src, reg post-incr dest +;;; .word 0x0179 +;;; .word 0x8049 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xf5, r0l + beq .L7 + fail +.L7: + +or_b_reg8_rdpostdec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@eRd- ; or reg8 to register indirect post-decrement + mov #byte_dest, er0 + mov #0xaa, r1l + or.b r1l, @er0- ; reg8 src, reg post-decr dest +;;; .word 0x0179 +;;; .word 0xa049 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L8 + fail +.L8: + +or_b_reg8_rdpreinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@+eRd ; or reg8 to register indirect pre-increment + mov #pre_byte, er0 + mov #0x55, r1l + or.b r1l, @+er0 ; reg8 src, reg pre-incr dest +;;; .word 0x0179 +;;; .word 0x9049 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xf5, r0l + beq .L9 + fail +.L9: + +or_b_reg8_rdpredec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@-eRd ; or reg8 to register indirect pre-decrement + mov #post_byte, er0 + mov #0xaa, r1l + or.b r1l, @-er0 ; reg8 src, reg pre-decr dest +;;; .word 0x0179 +;;; .word 0xb049 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L10 + fail +.L10: + +.endif + +orc_imm8_ccr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; orc #xx:8,ccr + + test_neg_clear + orc #0x8, ccr ; Immediate 8-bit operand (neg flag) + test_neg_set + + test_zero_clear + orc #0x4, ccr ; Immediate 8-bit operand (zero flag) + test_zero_set + + test_ovf_clear + orc #0x2, ccr ; Immediate 8-bit operand (overflow flag) + test_ovf_set + + test_carry_clear + orc #0x1, ccr ; Immediate 8-bit operand (carry flag) + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +orc_imm8_exr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ldc #0, exr + stc exr, r0l + test_h_gr8 0, r0l + + ;; orc #xx:8,exr + + orc #0x1, exr + stc exr,r0l + test_h_gr8 1, r0l + + orc #0x2, exr + stc exr,r0l + test_h_gr8 3, r0l + + orc #0x4, exr + stc exr,r0l + test_h_gr8 7, r0l + + orc #0x80, exr + stc exr,r0l + test_h_gr8 0x87, r0l + + test_h_gr32 0xa5a5a587 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; not h8300 or h8300h + + pass + + exit 0 diff --git a/sim/testsuite/h8300/orl.s b/sim/testsuite/h8300/orl.s new file mode 100644 index 0000000..03c3f22 --- /dev/null +++ b/sim/testsuite/h8300/orl.s @@ -0,0 +1,77 @@ +# Hitachi H8 testcase 'or.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. +or_l_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.l #xx:16,Rd + or.l #0xaaaa, er0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5afaf er0 ; or result: a5a5a5a5 | aaaa + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +or_l_imm32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.l #xx:32,Rd + or.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +or_l_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.l Rs,Rd + mov.l #0xaaaaaaaa, er1 + or.l er1, er0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa + test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/orw.s b/sim/testsuite/h8300/orw.s new file mode 100644 index 0000000..32eef45 --- /dev/null +++ b/sim/testsuite/h8300/orw.s @@ -0,0 +1,61 @@ +# Hitachi H8 testcase 'or.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +or_w_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.w #xx:16,Rd + or.w #0xaaaa, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +or_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.w Rs,Rd + mov.w #0xaaaa, r1 + or.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa + test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa + test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/rotl.s b/sim/testsuite/h8300/rotl.s new file mode 100644 index 0000000..1978c2d --- /dev/null +++ b/sim/testsuite/h8300/rotl.s @@ -0,0 +1,1212 @@ +# Hitachi H8 testcase 'rotl' +# mach(): h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +rotl_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotl.b r0l ; shift left arithmetic by one + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0xa54b r0 ; 1010 0101 -> 0100 1011 +.if (sim_cpu) + test_h_gr32 0xa5a5a54b er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotl_b_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotl.b @er0 ; shift right arithmetic by one, indirect + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbind1 + fail +.Lbind1: + mov.b #0xa5, @byte_dest + +rotl_b_indexb16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r0l + rotl.b @(byte_dest-5:16, r0.b) ; indexed byte/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbindexb161 + fail +.Lbindexb161: + mov.b #0xa5, @byte_dest + +rotl_b_indexw16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r0 + rotl.b @(byte_dest-256:16, r0.w) ; indexed byte/word + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a50100 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbindexw161 + fail +.Lbindexw161: + mov.b #0xa5, @byte_dest + +rotl_b_indexl16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er0 + rotl.b @(byte_dest+1:16, er0.l) ; indexed byte/long + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xffffffff er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbindexl161 + fail +.Lbindexl161: + mov.b #0xa5, @byte_dest + +rotl_b_indexb32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r1l + rotl.b @(byte_dest-5:32, r1.b) ; indexed byte/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbindexb321 + fail +.Lbindexb321: + mov.b #0xa5, @byte_dest + +rotl_b_indexw32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r1 + rotl.b @(byte_dest-256:32, r1.w) ; indexed byte/word + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a50100 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbindexw321 + fail +.Lbindexw321: + mov.b #0xa5, @byte_dest + +rotl_b_indexl32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er1 + rotl.b @(byte_dest+1:32, er1.l) ; indexed byte/long + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xffffffff er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbindexl321 + fail +.Lbindexl321: + mov.b #0xa5, @byte_dest + +.endif + +rotl_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotl.b #2, r0l ; shift left arithmetic by two + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa596 r0 ; 1010 0101 -> 1001 0110 +.if (sim_cpu) + test_h_gr32 0xa5a5a596 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotl_b_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotl.b #2, @er0 ; shift right arithmetic by one, indirect + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbind2 + fail +.Lbind2: + mov.b #0xa5, @byte_dest + +rotl_b_indexb16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r0l + rotl.b #2, @(byte_dest-5:16, r0.b) ; indexed byte/byte + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a5a505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbindexb162 + fail +.Lbindexb162: + mov.b #0xa5, @byte_dest + +rotl_b_indexw16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r0 + rotl.b #2, @(byte_dest-256:16, r0.w) ; indexed byte/word + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a50100 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbindexw162 + fail +.Lbindexw162: + mov.b #0xa5, @byte_dest + +rotl_b_indexl16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er0 + rotl.b #2, @(byte_dest+1:16, er0.l) ; indexed byte/long + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xffffffff er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbindexl162 + fail +.Lbindexl162: + mov.b #0xa5, @byte_dest + +rotl_b_indexb32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r1l + rotl.b #2, @(byte_dest-5:32, r1.b) ; indexed byte/byte + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbindexb322 + fail +.Lbindexb322: + mov.b #0xa5, @byte_dest + +rotl_b_indexw32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r1 + rotl.b #2, @(byte_dest-256:32, r1.w) ; indexed byte/word + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a50100 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbindexw322 + fail +.Lbindexw322: + mov.b #0xa5, @byte_dest + +rotl_b_indexl32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er1 + rotl.b #2, @(byte_dest+1:32, er1.l) ; indexed byte/long + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xffffffff er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbindexl322 + fail +.Lbindexl322: + mov.b #0xa5, @byte_dest + +.endif + +.if (sim_cpu) ; Not available in h8300 mode +rotl_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotl.w r0 ; shift left arithmetic by one + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0x4b4b r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + test_h_gr32 0xa5a54b4b er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotl_w_indexb16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r0l + rotl.w @(word_dest-10:16, r0.b) ; indexed word/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + cmp.w #0x4b4b, @word_dest + beq .Lwindexb161 + fail +.Lwindexb161: + mov.w #0xa5a5, @word_dest + +rotl_w_indexw16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r0 + rotl.w @(word_dest-512:16, r0.w) ; indexed word/word + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a50100 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + cmp.w #0x4b4b, @word_dest + beq .Lwindexw161 + fail +.Lwindexw161: + mov.w #0xa5a5, @word_dest + +rotl_w_indexl16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er0 + rotl.w @(word_dest+2:16, er0.l) ; indexed word/long + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xffffffff er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + cmp.w #0x4b4b, @word_dest + beq .Lwindexl161 + fail +.Lwindexl161: + mov.w #0xa5a5, @word_dest + +rotl_w_indexb32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r1l + rotl.w @(word_dest-10:32, r1.b) ; indexed word/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + cmp.w #0x4b4b, @word_dest + beq .Lwindexb321 + fail +.Lwindexb321: + mov.w #0xa5a5, @word_dest + +rotl_w_indexw32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r1 + rotl.w @(word_dest-512:32, r1.w) ; indexed word/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a50100 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + cmp.w #0x4b4b, @word_dest + beq .Lwindexw321 + fail +.Lwindexw321: + mov.w #0xa5a5, @word_dest + +rotl_w_indexl32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er1 + rotl.w @(word_dest+2:32, er1.l) ; indexed word/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xffffffff er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + cmp.w #0x4b4b, @word_dest + beq .Lwindexl321 + fail +.Lwindexl321: + mov.w #0xa5a5, @word_dest +.endif + +rotl_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotl.w #2, r0 ; shift left arithmetic by two + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0x9696 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + test_h_gr32 0xa5a59696 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotl_w_indexb16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r0l + rotl.w #2, @(word_dest-10:16, r0.b) ; indexed word/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a5a505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + cmp.w #0x9696, @word_dest + beq .Lwindexb162 + fail +.Lwindexb162: + mov.w #0xa5a5, @word_dest + +rotl_w_indexw16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r0 + rotl.w #2, @(word_dest-512:16, r0.w) ; indexed word/word + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a50100 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + cmp.w #0x9696, @word_dest + beq .Lwindexw162 + fail +.Lwindexw162: + mov.w #0xa5a5, @word_dest + +rotl_w_indexl16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er0 + rotl.w #2, @(word_dest+2:16, er0.l) ; indexed word/long + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xffffffff er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + cmp.w #0x9696, @word_dest + beq .Lwindexl162 + fail +.Lwindexl162: + mov.w #0xa5a5, @word_dest + +rotl_w_indexb32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r1l + rotl.w #2, @(word_dest-10:32, r1.b) ; indexed word/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + cmp.w #0x9696, @word_dest + beq .Lwindexb322 + fail +.Lwindexb322: + mov.w #0xa5a5, @word_dest + +rotl_w_indexw32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r1 + rotl.w #2, @(word_dest-512:32, r1.w) ; indexed word/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a50100 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + cmp.w #0x9696, @word_dest + beq .Lwindexw322 + fail +.Lwindexw322: + mov.w #0xa5a5, @word_dest + +rotl_w_indexl32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er1 + rotl.w #2, @(word_dest+2:32, er1.l) ; indexed word/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xffffffff er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + cmp.w #0x9696, @word_dest + beq .Lwindexl322 + fail +.Lwindexl322: + mov.w #0xa5a5, @word_dest +.endif + +rotl_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotl.l er0 ; shift left arithmetic by one + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + test_h_gr32 0x4b4b4b4b er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotl_l_indexb16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r0l + rotl.l @(long_dest-20:16, er0.b) ; indexed long/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + cmp.l #0x4b4b4b4b, @long_dest + beq .Llindexb161 + fail +.Llindexb161: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexw16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r0 + rotl.l @(long_dest-1024:16, er0.w) ; indexed long/word + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a50100 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + cmp.l #0x4b4b4b4b, @long_dest + beq .Llindexw161 + fail +.Llindexw161: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexl16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er0 + rotl.l @(long_dest+4:16, er0.l) ; indexed long/long + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xffffffff er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + cmp.l #0x4b4b4b4b, @long_dest + beq .Llindexl161 + fail +.Llindexl161: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexb32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r1l + rotl.l @(long_dest-20:32, er1.b) ; indexed long/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + cmp.l #0x4b4b4b4b, @long_dest + beq .Llindexb321 + fail +.Llindexb321: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexw32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r1 + rotl.l @(long_dest-1024:32, er1.w) ; indexed long/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a50100 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + cmp.l #0x4b4b4b4b, @long_dest + beq .Llindexw321 + fail +.Llindexw321: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexl32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er1 + rotl.l @(long_dest+4:32, er1.l) ; indexed long/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xffffffff er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + cmp.l #0x4b4b4b4b, @long_dest + beq .Llindexl321 + fail +.Llindexl321: + mov.l #0xa5a5a5a5, @long_dest +.endif + +rotl_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotl.l #2, er0 ; shift left arithmetic by two + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + test_h_gr32 0x96969696 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotl_l_indexb16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r0l + rotl.l #2, @(long_dest-20:16, er0.b) ; indexed long/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a5a505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + cmp.l #0x96969696, @long_dest + beq .Llindexb162 + fail +.Llindexb162: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexw16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r0 + rotl.l #2, @(long_dest-1024:16, er0.w) ; indexed long/word + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a50100 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + cmp.l #0x96969696, @long_dest + beq .Llindexw162 + fail +.Llindexw162: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexl16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er0 + rotl.l #2, @(long_dest+4:16, er0.l) ; indexed long/long + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xffffffff er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + cmp.l #0x96969696, @long_dest + beq .Llindexl162 + fail +.Llindexl162: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexb32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r1l + rotl.l #2, @(long_dest-20:32, er1.b) ; indexed long/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + cmp.l #0x96969696, @long_dest + beq .Llindexb322 + fail +.Llindexb322: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexw32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r1 + rotl.l #2, @(long_dest-1024:32, er1.w) ; indexed long/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a50100 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + cmp.l #0x96969696, @long_dest + beq .Llindexw322 + fail +.Llindexw322: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexl32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er1 + rotl.l #2, @(long_dest+4:32, er1.l) ; indexed long/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xffffffff er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + cmp.l #0x96969696, @long_dest + beq .Llindexl322 + fail +.Llindexl322: + mov.l #0xa5a5a5a5, @long_dest +.endif +.endif + + pass + + exit 0 + diff --git a/sim/testsuite/h8300/rotr.s b/sim/testsuite/h8300/rotr.s new file mode 100644 index 0000000..658ef82 --- /dev/null +++ b/sim/testsuite/h8300/rotr.s @@ -0,0 +1,1802 @@ +# Hitachi H8 testcase 'rotr' +# mach(): h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +rotr_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.b r0l ; shift right arithmetic by one + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010 +.if (sim_cpu) + test_h_gr32 0xa5a5a5d2 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotr_b_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotr.b @er0 ; shift right arithmetic by one, indirect + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbind1 + fail +.Lbind1: + mov.b #0xa5, @byte_dest + +rotr_b_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotr.b @er0+ ; shift right arithmetic by one, postinc + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpostinc1 + fail +.Lbpostinc1: + mov.b #0xa5, @byte_dest + +rotr_b_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotr.b @er0- ; shift right arithmetic by one, postdec + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpostdec1 + fail +.Lbpostdec1: + mov.b #0xa5, @byte_dest + +rotr_b_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + rotr.b @+er0 ; shift right arithmetic by one, preinc + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpreinc1 + fail +.Lbpreinc1: + mov.b #0xa5, @byte_dest + +rotr_b_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + rotr.b @-er0 ; shift right arithmetic by one, predec + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpredec1 + fail +.Lbpredec1: + mov.b #0xa5, @byte_dest + +rotr_b_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + rotr.b @(2:2, er0) ; shift right arithmetic by one, disp2 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbdisp21 + fail +.Lbdisp21: + mov.b #0xa5, @byte_dest + +rotr_b_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + rotr.b @(44:16, er0) ; shift right arithmetic by one, disp16 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbdisp161 + fail +.Lbdisp161: + mov.b #0xa5, @byte_dest + +rotr_b_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + rotr.b @(666:32, er0) ; shift right arithmetic by one, disp32 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbdisp321 + fail +.Lbdisp321: + mov.b #0xa5, @byte_dest + +rotr_b_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.b @byte_dest:16 ; shift right arithmetic by one, abs16 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbabs161 + fail +.Lbabs161: + mov.b #0xa5, @byte_dest + +rotr_b_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.b @byte_dest:32 ; shift right arithmetic by one, abs32 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbabs321 + fail +.Lbabs321: + mov.b #0xa5, @byte_dest +.endif + +rotr_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.b #2, r0l ; shift right arithmetic by two + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0xa569 r0 ; 1010 0101 -> 0110 1001 +.if (sim_cpu) + test_h_gr32 0xa5a5a569 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotr_b_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotr.b #2, @er0 ; shift right arithmetic by two, indirect + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbind2 + fail +.Lbind2: + mov.b #0xa5, @byte_dest + +rotr_b_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotr.b #2, @er0+ ; shift right arithmetic by two, postinc + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbpostinc2 + fail +.Lbpostinc2: + mov.b #0xa5, @byte_dest + +rotr_b_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotr.b #2, @er0- ; shift right arithmetic by two, postdec + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbpostdec2 + fail +.Lbpostdec2: + mov.b #0xa5, @byte_dest + +rotr_b_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + rotr.b #2, @+er0 ; shift right arithmetic by two, preinc + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbpreinc2 + fail +.Lbpreinc2: + mov.b #0xa5, @byte_dest + +rotr_b_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + rotr.b #2, @-er0 ; shift right arithmetic by two, predec + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbpredec2 + fail +.Lbpredec2: + mov.b #0xa5, @byte_dest + +rotr_b_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + rotr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbdisp22 + fail +.Lbdisp22: + mov.b #0xa5, @byte_dest + +rotr_b_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + rotr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbdisp162 + fail +.Lbdisp162: + mov.b #0xa5, @byte_dest + +rotr_b_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + rotr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbdisp322 + fail +.Lbdisp322: + mov.b #0xa5, @byte_dest + +rotr_b_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbabs162 + fail +.Lbabs162: + mov.b #0xa5, @byte_dest + +rotr_b_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbabs322 + fail +.Lbabs322: + mov.b #0xa5, @byte_dest +.endif + +.if (sim_cpu) ; Not available in h8300 mode +rotr_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.w r0 ; shift right arithmetic by one + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + test_h_gr32 0xa5a5d2d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotr_w_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotr.w @er0 ; shift right arithmetic by one, indirect + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwind1 + fail +.Lwind1: + mov.w #0xa5a5, @word_dest + +rotr_w_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotr.w @er0+ ; shift right arithmetic by one, postinc + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpostinc1 + fail +.Lwpostinc1: + mov.w #0xa5a5, @word_dest + +rotr_w_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotr.w @er0- ; shift right arithmetic by one, postdec + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpostdec1 + fail +.Lwpostdec1: + mov.w #0xa5a5, @word_dest + +rotr_w_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + rotr.w @+er0 ; shift right arithmetic by one, preinc + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpreinc1 + fail +.Lwpreinc1: + mov.w #0xa5a5, @word_dest + +rotr_w_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + rotr.w @-er0 ; shift right arithmetic by one, predec + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpredec1 + fail +.Lwpredec1: + mov.w #0xa5a5, @word_dest + +rotr_w_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + rotr.w @(4:2, er0) ; shift right arithmetic by one, disp2 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwdisp21 + fail +.Lwdisp21: + mov.w #0xa5a5, @word_dest + +rotr_w_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + rotr.w @(44:16, er0) ; shift right arithmetic by one, disp16 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwdisp161 + fail +.Lwdisp161: + mov.w #0xa5a5, @word_dest + +rotr_w_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + rotr.w @(666:32, er0) ; shift right arithmetic by one, disp32 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwdisp321 + fail +.Lwdisp321: + mov.w #0xa5a5, @word_dest + +rotr_w_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.w @word_dest:16 ; shift right arithmetic by one, abs16 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwabs161 + fail +.Lwabs161: + mov.w #0xa5a5, @word_dest + +rotr_w_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.w @word_dest:32 ; shift right arithmetic by one, abs32 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwabs321 + fail +.Lwabs321: + mov.w #0xa5a5, @word_dest +.endif + +rotr_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.w #2, r0 ; shift right arithmetic by two + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x6969 r0 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + test_h_gr32 0xa5a56969 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotr_w_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotr.w #2, @er0 ; shift right arithmetic by two, indirect + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwind2 + fail +.Lwind2: + mov.w #0xa5a5, @word_dest + +rotr_w_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotr.w #2, @er0+ ; shift right arithmetic by two, postinc + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwpostinc2 + fail +.Lwpostinc2: + mov.w #0xa5a5, @word_dest + +rotr_w_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotr.w #2, @er0- ; shift right arithmetic by two, postdec + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwpostdec2 + fail +.Lwpostdec2: + mov.w #0xa5a5, @word_dest + +rotr_w_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + rotr.w #2, @+er0 ; shift right arithmetic by two, preinc + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwpreinc2 + fail +.Lwpreinc2: + mov.w #0xa5a5, @word_dest + +rotr_w_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + rotr.w #2, @-er0 ; shift right arithmetic by two, predec + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwpredec2 + fail +.Lwpredec2: + mov.w #0xa5a5, @word_dest + +rotr_w_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + rotr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwdisp22 + fail +.Lwdisp22: + mov.w #0xa5a5, @word_dest + +rotr_w_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + rotr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwdisp162 + fail +.Lwdisp162: + mov.w #0xa5a5, @word_dest + +rotr_w_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + rotr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwdisp322 + fail +.Lwdisp322: + mov.w #0xa5a5, @word_dest + +rotr_w_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwabs162 + fail +.Lwabs162: + mov.w #0xa5a5, @word_dest + +rotr_w_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwabs322 + fail +.Lwabs322: + mov.w #0xa5a5, @word_dest +.endif + +rotr_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.l er0 ; shift right arithmetic by one, register + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1101 0010 1101 0010 1101 0010 1101 0010 + test_h_gr32 0xd2d2d2d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotr_l_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotr.l @er0 ; shift right arithmetic by one, indirect + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llind1 + fail +.Llind1: + mov #0xa5a5a5a5, @long_dest + +rotr_l_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotr.l @er0+ ; shift right arithmetic by one, postinc + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpostinc1 + fail +.Llpostinc1: + mov #0xa5a5a5a5, @long_dest + +rotr_l_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotr.l @er0- ; shift right arithmetic by one, postdec + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpostdec1 + fail +.Llpostdec1: + mov #0xa5a5a5a5, @long_dest + +rotr_l_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + rotr.l @+er0 ; shift right arithmetic by one, preinc + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpreinc1 + fail +.Llpreinc1: + mov #0xa5a5a5a5, @long_dest + +rotr_l_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + rotr.l @-er0 ; shift right arithmetic by one, predec + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpredec1 + fail +.Llpredec1: + mov #0xa5a5a5a5, @long_dest + +rotr_l_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + rotr.l @(8:2, er0) ; shift right arithmetic by one, disp2 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Lldisp21 + fail +.Lldisp21: + mov #0xa5a5a5a5, @long_dest + +rotr_l_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + rotr.l @(44:16, er0) ; shift right arithmetic by one, disp16 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Lldisp161 + fail +.Lldisp161: + mov #0xa5a5a5a5, @long_dest + +rotr_l_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + rotr.l @(666:32, er0) ; shift right arithmetic by one, disp32 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Lldisp321 + fail +.Lldisp321: + mov #0xa5a5a5a5, @long_dest + +rotr_l_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.l @long_dest:16 ; shift right arithmetic by one, abs16 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llabs161 + fail +.Llabs161: + mov #0xa5a5a5a5, @long_dest + +rotr_l_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.l @long_dest:32 ; shift right arithmetic by one, abs32 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llabs321 + fail +.Llabs321: + mov #0xa5a5a5a5, @long_dest +.endif + +rotr_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.l #2, er0 ; shift right arithmetic by two, register + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0110 1001 0110 1001 0110 1001 0110 1001 + test_h_gr32 0x69696969 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + +rotr_l_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotr.l #2, @er0 ; shift right arithmetic by two, indirect + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llind2 + fail +.Llind2: + mov #0xa5a5a5a5, @long_dest + +rotr_l_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotr.l #2, @er0+ ; shift right arithmetic by two, postinc + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llpostinc2 + fail +.Llpostinc2: + mov #0xa5a5a5a5, @long_dest + +rotr_l_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotr.l #2, @er0- ; shift right arithmetic by two, postdec + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llpostdec2 + fail +.Llpostdec2: + mov #0xa5a5a5a5, @long_dest + +rotr_l_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + rotr.l #2, @+er0 ; shift right arithmetic by two, preinc + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llpreinc2 + fail +.Llpreinc2: + mov #0xa5a5a5a5, @long_dest + +rotr_l_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + rotr.l #2, @-er0 ; shift right arithmetic by two, predec + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llpredec2 + fail +.Llpredec2: + mov #0xa5a5a5a5, @long_dest + +rotr_l_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + rotr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Lldisp22 + fail +.Lldisp22: + mov #0xa5a5a5a5, @long_dest + +rotr_l_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + rotr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Lldisp162 + fail +.Lldisp162: + mov #0xa5a5a5a5, @long_dest + +rotr_l_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + rotr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Lldisp322 + fail +.Lldisp322: + mov #0xa5a5a5a5, @long_dest + +rotr_l_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llabs162 + fail +.Llabs162: + mov #0xa5a5a5a5, @long_dest + +rotr_l_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llabs322 + fail +.Llabs322: + mov #0xa5a5a5a5, @long_dest + +.endif +.endif + pass + + exit 0 + diff --git a/sim/testsuite/h8300/rotxl.s b/sim/testsuite/h8300/rotxl.s new file mode 100644 index 0000000..d0ff4a3 --- /dev/null +++ b/sim/testsuite/h8300/rotxl.s @@ -0,0 +1,167 @@ +# Hitachi H8 testcase 'rotxl' +# mach(): h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +rotxl_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxl.b r0l ; shift left arithmetic by one +;;; .word 0x1208 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 +.if (sim_cpu) + test_h_gr32 0xa5a5a54a er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +rotxl_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxl.b #2, r0l ; shift left arithmetic by two +;;; .word 0x1248 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa595 r0 ; 1010 0101 -> 1001 0101 +.if (sim_cpu) + test_h_gr32 0xa5a5a595 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; Not available in h8300 mode +rotxl_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxl.w r0 ; shift left arithmetic by one +;;; .word 0x1210 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 + test_h_gr32 0xa5a54b4a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +rotxl_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxl.w #2, r0 ; shift left arithmetic by two +;;; .word 0x1250 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0x9695 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0101 + test_h_gr32 0xa5a59695 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +rotxl_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxl.l er0 ; shift left arithmetic by one +;;; .word 1030 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1010 + test_h_gr32 0x4b4b4b4a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +rotxl_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxl.l #2, er0 ; shift left arithmetic by two +;;; .word 0x1270 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0101 + test_h_gr32 0x96969695 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + + pass + + exit 0 + diff --git a/sim/testsuite/h8300/rotxr.s b/sim/testsuite/h8300/rotxr.s new file mode 100644 index 0000000..31a351f --- /dev/null +++ b/sim/testsuite/h8300/rotxr.s @@ -0,0 +1,2002 @@ +# Hitachi H8 testcase 'rotxr' +# mach(): h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +rotxr_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.b r0l ; shift right arithmetic by one +;;; .word 0x1308 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010 +.if (sim_cpu) + test_h_gr32 0xa5a5a552 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotxr_b_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotxr.b @er0 ; shift right arithmetic by one, indirect +;;; .word 0x7d00 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbind1 + fail +.Lbind1: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotxr.b @er0+ ; shift right arithmetic by one, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpostinc1 + fail +.Lbpostinc1: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotxr.b @er0- ; shift right arithmetic by one, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpostdec1 + fail +.Lbpostdec1: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + rotxr.b @+er0 ; shift right arithmetic by one, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpreinc1 + fail +.Lbpreinc1: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + rotxr.b @-er0 ; shift right arithmetic by one, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpredec1 + fail +.Lbpredec1: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + rotxr.b @(2:2, er0) ; shift right arithmetic by one, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbdisp21 + fail +.Lbdisp21: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + rotxr.b @(44:16, er0) ; shift right arithmetic by one, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbdisp161 + fail +.Lbdisp161: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + rotxr.b @(666:32, er0) ; shift right arithmetic by one, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbdisp321 + fail +.Lbdisp321: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.b @byte_dest:16 ; shift right arithmetic by one, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbabs161 + fail +.Lbabs161: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.b @byte_dest:32 ; shift right arithmetic by one, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbabs321 + fail +.Lbabs321: + mov #0xa5a5a5a5, @byte_dest +.endif + +rotxr_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.b #2, r0l ; shift right arithmetic by two +;;; .word 0x1348 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa5a9 r0 ; 1010 0101 -> 1010 1001 +.if (sim_cpu) + test_h_gr32 0xa5a5a5a9 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotxr_b_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotxr.b #2, @er0 ; shift right arithmetic by two, indirect +;;; .word 0x7d00 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbind2 + fail +.Lbind2: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotxr.b #2, @er0+ ; shift right arithmetic by two, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbpostinc2 + fail +.Lbpostinc2: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotxr.b #2, @er0- ; shift right arithmetic by two, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbpostdec2 + fail +.Lbpostdec2: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + rotxr.b #2, @+er0 ; shift right arithmetic by two, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbpreinc2 + fail +.Lbpreinc2: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + rotxr.b #2, @-er0 ; shift right arithmetic by two, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbpredec2 + fail +.Lbpredec2: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + rotxr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbdisp22 + fail +.Lbdisp22: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + rotxr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbdisp162 + fail +.Lbdisp162: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + rotxr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbdisp322 + fail +.Lbdisp322: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbabs162 + fail +.Lbabs162: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbabs322 + fail +.Lbabs322: + mov #0xa5a5a5a5, @byte_dest +.endif + +.if (sim_cpu) ; Not available in h8300 mode +rotxr_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.w r0 ; shift right arithmetic by one +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + test_h_gr32 0xa5a552d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotxr_w_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotxr.w @er0 ; shift right arithmetic by one, indirect +;;; .word 0x7d80 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwind1 + fail +.Lwind1: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotxr.w @er0+ ; shift right arithmetic by one, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpostinc1 + fail +.Lwpostinc1: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotxr.w @er0- ; shift right arithmetic by one, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpostdec1 + fail +.Lwpostdec1: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + rotxr.w @+er0 ; shift right arithmetic by one, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpreinc1 + fail +.Lwpreinc1: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + rotxr.w @-er0 ; shift right arithmetic by one, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpredec1 + fail +.Lwpredec1: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + rotxr.w @(4:2, er0) ; shift right arithmetic by one, disp2 +;;; .word 0x0156 +;;; .word 0xa908 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwdisp21 + fail +.Lwdisp21: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + rotxr.w @(44:16, er0) ; shift right arithmetic by one, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwdisp161 + fail +.Lwdisp161: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + rotxr.w @(666:32, er0) ; shift right arithmetic by one, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwdisp321 + fail +.Lwdisp321: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.w @word_dest:16 ; shift right arithmetic by one, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwabs161 + fail +.Lwabs161: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.w @word_dest:32 ; shift right arithmetic by one, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwabs321 + fail +.Lwabs321: + mov #0xa5a5a5a5, @word_dest +.endif + +rotxr_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.w #2, r0 ; shift right arithmetic by two +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa969 r0 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + test_h_gr32 0xa5a5a969 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotxr_w_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotxr.w #2, @er0 ; shift right arithmetic by two, indirect +;;; .word 0x7d80 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwind2 + fail +.Lwind2: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotxr.w #2, @er0+ ; shift right arithmetic by two, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwpostinc2 + fail +.Lwpostinc2: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotxr.w #2, @er0- ; shift right arithmetic by two, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwpostdec2 + fail +.Lwpostdec2: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + rotxr.w #2, @+er0 ; shift right arithmetic by two, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwpreinc2 + fail +.Lwpreinc2: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + rotxr.w #2, @-er0 ; shift right arithmetic by two, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwpredec2 + fail +.Lwpredec2: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + rotxr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 +;;; .word 0x0156 +;;; .word 0xa908 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwdisp22 + fail +.Lwdisp22: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + rotxr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwdisp162 + fail +.Lwdisp162: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + rotxr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwdisp322 + fail +.Lwdisp322: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwabs162 + fail +.Lwabs162: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwabs322 + fail +.Lwabs322: + mov #0xa5a5a5a5, @word_dest +.endif + +rotxr_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.l er0 ; shift right arithmetic by one, register +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0101 0010 1101 0010 1101 0010 1101 0010 + test_h_gr32 0x52d2d2d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotxr_l_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotxr.l @er0 ; shift right arithmetic by one, indirect +;;; .word 0x0104 +;;; .word 0xa908 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llind1 + fail +.Llind1: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotxr.l @er0+ ; shift right arithmetic by one, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpostinc1 + fail +.Llpostinc1: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotxr.l @er0- ; shift right arithmetic by one, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpostdec1 + fail +.Llpostdec1: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + rotxr.l @+er0 ; shift right arithmetic by one, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpreinc1 + fail +.Llpreinc1: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + rotxr.l @-er0 ; shift right arithmetic by one, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpredec1 + fail +.Llpredec1: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + rotxr.l @(8:2, er0) ; shift right arithmetic by one, disp2 +;;; .word 0x0106 +;;; .word 0xa908 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Lldisp21 + fail +.Lldisp21: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + rotxr.l @(44:16, er0) ; shift right arithmetic by one, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Lldisp161 + fail +.Lldisp161: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + rotxr.l @(666:32, er0) ; shift right arithmetic by one, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Lldisp321 + fail +.Lldisp321: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.l @long_dest:16 ; shift right arithmetic by one, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llabs161 + fail +.Llabs161: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.l @long_dest:32 ; shift right arithmetic by one, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llabs321 + fail +.Llabs321: + mov #0xa5a5a5a5, @long_dest +.endif + +rotxr_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.l #2, er0 ; shift right arithmetic by two, register +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1010 1001 0110 1001 0110 1001 0110 1001 + test_h_gr32 0xa9696969 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + +rotxr_l_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotxr.l #2, @er0 ; shift right arithmetic by two, indirect +;;; .word 0x0104 +;;; .word 0xa908 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llind2 + fail +.Llind2: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotxr.l #2, @er0+ ; shift right arithmetic by two, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llpostinc2 + fail +.Llpostinc2: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotxr.l #2, @er0- ; shift right arithmetic by two, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llpostdec2 + fail +.Llpostdec2: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + rotxr.l #2, @+er0 ; shift right arithmetic by two, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llpreinc2 + fail +.Llpreinc2: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + rotxr.l #2, @-er0 ; shift right arithmetic by two, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llpredec2 + fail +.Llpredec2: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + rotxr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 +;;; .word 0x0106 +;;; .word 0xa908 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Lldisp22 + fail +.Lldisp22: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + rotxr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Lldisp162 + fail +.Lldisp162: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + rotxr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Lldisp322 + fail +.Lldisp322: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llabs162 + fail +.Llabs162: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llabs322 + fail +.Llabs322: + mov #0xa5a5a5a5, @long_dest + +.endif +.endif + pass + + exit 0 + diff --git a/sim/testsuite/h8300/shal.s b/sim/testsuite/h8300/shal.s new file mode 100644 index 0000000..5d930d9 --- /dev/null +++ b/sim/testsuite/h8300/shal.s @@ -0,0 +1,167 @@ +# Hitachi H8 testcase 'shal' +# mach(): h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +shal_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shal.b r0l ; shift left arithmetic by one +;;; .word 0x1088 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear +; test_ovf_clear ; FIXME + test_neg_clear + test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 +.if (sim_cpu) + test_h_gr32 0xa5a5a54a er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shal_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shal.b #2, r0l ; shift left arithmetic by two +;;; .word 0x10c8 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear +; test_ovf_clear ; FIXME + test_neg_set + + test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100 +.if (sim_cpu) + test_h_gr32 0xa5a5a594 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; Not available in h8300 mode +shal_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shal.w r0 ; shift left arithmetic by one +;;; .word 0x1090 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear +; test_ovf_clear ; FIXME + test_neg_clear + test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 + test_h_gr32 0xa5a54b4a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shal_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shal.w #2, r0 ; shift left arithmetic by two +;;; .word 0x10d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear +; test_ovf_clear ; FIXME + test_neg_set + test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100 + test_h_gr32 0xa5a59694 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shal_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shal.l er0 ; shift left arithmetic by one +;;; .word 10b0 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear +; test_ovf_clear ; FIXME + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1010 + test_h_gr32 0x4b4b4b4a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shal_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shal.l #2, er0 ; shift left arithmetic by two +;;; .word 0x10f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear +; test_ovf_clear ; FIXME + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0100 + test_h_gr32 0x96969694 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + + pass + + exit 0 + diff --git a/sim/testsuite/h8300/shar.s b/sim/testsuite/h8300/shar.s new file mode 100644 index 0000000..6b182aa --- /dev/null +++ b/sim/testsuite/h8300/shar.s @@ -0,0 +1,2000 @@ +# Hitachi H8 testcase 'shar' +# mach(): h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +shar_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.b r0l ; shift right arithmetic by one +;;; .word 0x1188 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010 +.if (sim_cpu) + test_h_gr32 0xa5a5a5d2 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shar_b_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shar.b @er0 ; shift right arithmetic by one, indirect +;;; .word 0x7d00 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbind1 + fail +.Lbind1: + mov.b #0xa5, @byte_dest + +shar_b_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shar.b @er0+ ; shift right arithmetic by one, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpostinc1 + fail +.Lbpostinc1: + mov.b #0xa5, @byte_dest + +shar_b_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shar.b @er0- ; shift right arithmetic by one, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpostdec1 + fail +.Lbpostdec1: + mov.b #0xa5, @byte_dest + +shar_b_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + shar.b @+er0 ; shift right arithmetic by one, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpreinc1 + fail +.Lbpreinc1: + mov.b #0xa5, @byte_dest + +shar_b_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + shar.b @-er0 ; shift right arithmetic by one, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpredec1 + fail +.Lbpredec1: + mov.b #0xa5, @byte_dest + +shar_b_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + shar.b @(2:2, er0) ; shift right arithmetic by one, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbdisp21 + fail +.Lbdisp21: + mov.b #0xa5, @byte_dest + +shar_b_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + shar.b @(44:16, er0) ; shift right arithmetic by one, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbdisp161 + fail +.Lbdisp161: + mov.b #0xa5, @byte_dest + +shar_b_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + shar.b @(666:32, er0) ; shift right arithmetic by one, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbdisp321 + fail +.Lbdisp321: + mov.b #0xa5, @byte_dest + +shar_b_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.b @byte_dest:16 ; shift right arithmetic by one, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbabs161 + fail +.Lbabs161: + mov.b #0xa5, @byte_dest + +shar_b_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.b @byte_dest:32 ; shift right arithmetic by one, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbabs321 + fail +.Lbabs321: + mov.b #0xa5, @byte_dest +.endif + +shar_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.b #2, r0l ; shift right arithmetic by two +;;; .word 0x11c8 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0xa5e9 r0 ; 1010 0101 -> 1110 1001 +.if (sim_cpu) + test_h_gr32 0xa5a5a5e9 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shar_b_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shar.b #2, @er0 ; shift right arithmetic by two, indirect +;;; .word 0x7d00 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbind2 + fail +.Lbind2: + mov.b #0xa5, @byte_dest + +shar_b_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shar.b #2, @er0+ ; shift right arithmetic by two, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbpostinc2 + fail +.Lbpostinc2: + mov.b #0xa5, @byte_dest + +shar_b_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shar.b #2, @er0- ; shift right arithmetic by two, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbpostdec2 + fail +.Lbpostdec2: + mov.b #0xa5, @byte_dest + +shar_b_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + shar.b #2, @+er0 ; shift right arithmetic by two, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbpreinc2 + fail +.Lbpreinc2: + mov.b #0xa5, @byte_dest + +shar_b_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + shar.b #2, @-er0 ; shift right arithmetic by two, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbpredec2 + fail +.Lbpredec2: + mov.b #0xa5, @byte_dest + +shar_b_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + shar.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbdisp22 + fail +.Lbdisp22: + mov.b #0xa5, @byte_dest + +shar_b_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + shar.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbdisp162 + fail +.Lbdisp162: + mov.b #0xa5, @byte_dest + +shar_b_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + shar.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbdisp322 + fail +.Lbdisp322: + mov.b #0xa5, @byte_dest + +shar_b_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbabs162 + fail +.Lbabs162: + mov.b #0xa5, @byte_dest + +shar_b_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbabs322 + fail +.Lbabs322: + mov.b #0xa5, @byte_dest +.endif + +.if (sim_cpu) ; Not available in h8300 mode +shar_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.w r0 ; shift right arithmetic by one +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + test_h_gr32 0xa5a5d2d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shar_w_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shar.w @er0 ; shift right arithmetic by one, indirect +;;; .word 0x7d80 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwind1 + fail +.Lwind1: + mov.w #0xa5a5, @word_dest + +shar_w_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shar.w @er0+ ; shift right arithmetic by one, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpostinc1 + fail +.Lwpostinc1: + mov.w #0xa5a5, @word_dest + +shar_w_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shar.w @er0- ; shift right arithmetic by one, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpostdec1 + fail +.Lwpostdec1: + mov.w #0xa5a5, @word_dest + +shar_w_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + shar.w @+er0 ; shift right arithmetic by one, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpreinc1 + fail +.Lwpreinc1: + mov.w #0xa5a5, @word_dest + +shar_w_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + shar.w @-er0 ; shift right arithmetic by one, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpredec1 + fail +.Lwpredec1: + mov.w #0xa5a5, @word_dest + +shar_w_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + shar.w @(4:2, er0) ; shift right arithmetic by one, disp2 +;;; .word 0x0156 +;;; .word 0x6908 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwdisp21 + fail +.Lwdisp21: + mov.w #0xa5a5, @word_dest + +shar_w_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + shar.w @(44:16, er0) ; shift right arithmetic by one, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwdisp161 + fail +.Lwdisp161: + mov.w #0xa5a5, @word_dest + +shar_w_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + shar.w @(666:32, er0) ; shift right arithmetic by one, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwdisp321 + fail +.Lwdisp321: + mov.w #0xa5a5, @word_dest + +shar_w_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.w @word_dest:16 ; shift right arithmetic by one, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwabs161 + fail +.Lwabs161: + mov.w #0xa5a5, @word_dest + +shar_w_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.w @word_dest:32 ; shift right arithmetic by one, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwabs321 + fail +.Lwabs321: + mov.w #0xa5a5, @word_dest +.endif + +shar_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.w #2, r0 ; shift right arithmetic by two +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xe969 r0 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + test_h_gr32 0xa5a5e969 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shar_w_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shar.w #2, @er0 ; shift right arithmetic by two, indirect +;;; .word 0x7d80 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwind2 + fail +.Lwind2: + mov.w #0xa5a5, @word_dest + +shar_w_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shar.w #2, @er0+ ; shift right arithmetic by two, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwpostinc2 + fail +.Lwpostinc2: + mov.w #0xa5a5, @word_dest + +shar_w_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shar.w #2, @er0- ; shift right arithmetic by two, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwpostdec2 + fail +.Lwpostdec2: + mov.w #0xa5a5, @word_dest + +shar_w_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + shar.w #2, @+er0 ; shift right arithmetic by two, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwpreinc2 + fail +.Lwpreinc2: + mov.w #0xa5a5, @word_dest + +shar_w_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + shar.w #2, @-er0 ; shift right arithmetic by two, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwpredec2 + fail +.Lwpredec2: + mov.w #0xa5a5, @word_dest + +shar_w_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + shar.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 +;;; .word 0x0156 +;;; .word 0x6908 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwdisp22 + fail +.Lwdisp22: + mov.w #0xa5a5, @word_dest + +shar_w_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + shar.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwdisp162 + fail +.Lwdisp162: + mov.w #0xa5a5, @word_dest + +shar_w_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + shar.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwdisp322 + fail +.Lwdisp322: + mov.w #0xa5a5, @word_dest + +shar_w_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwabs162 + fail +.Lwabs162: + mov.w #0xa5a5, @word_dest + +shar_w_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwabs322 + fail +.Lwabs322: + mov.w #0xa5a5, @word_dest +.endif + +shar_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.l er0 ; shift right arithmetic by one, register +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1101 0010 1101 0010 1101 0010 1101 0010 + test_h_gr32 0xd2d2d2d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shar_l_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shar.l @er0 ; shift right arithmetic by one, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llind1 + fail +.Llind1: + mov #0xa5a5a5a5, @long_dest + +shar_l_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shar.l @er0+ ; shift right arithmetic by one, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpostinc1 + fail +.Llpostinc1: + mov #0xa5a5a5a5, @long_dest + +shar_l_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shar.l @er0- ; shift right arithmetic by one, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpostdec1 + fail +.Llpostdec1: + mov #0xa5a5a5a5, @long_dest + +shar_l_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shar.l @+er0 ; shift right arithmetic by one, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpreinc1 + fail +.Llpreinc1: + mov #0xa5a5a5a5, @long_dest + +shar_l_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shar.l @-er0 ; shift right arithmetic by one, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpredec1 + fail +.Llpredec1: + mov #0xa5a5a5a5, @long_dest + +shar_l_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shar.l @(8:2, er0) ; shift right arithmetic by one, disp2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Lldisp21 + fail +.Lldisp21: + mov #0xa5a5a5a5, @long_dest + +shar_l_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shar.l @(44:16, er0) ; shift right arithmetic by one, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Lldisp161 + fail +.Lldisp161: + mov #0xa5a5a5a5, @long_dest + +shar_l_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shar.l @(666:32, er0) ; shift right arithmetic by one, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Lldisp321 + fail +.Lldisp321: + mov #0xa5a5a5a5, @long_dest + +shar_l_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.l @long_dest:16 ; shift right arithmetic by one, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llabs161 + fail +.Llabs161: + mov #0xa5a5a5a5, @long_dest + +shar_l_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.l @long_dest:32 ; shift right arithmetic by one, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llabs321 + fail +.Llabs321: + mov #0xa5a5a5a5, @long_dest +.endif + +shar_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.l #2, er0 ; shift right arithmetic by two, register +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1110 1001 0110 1001 0110 1001 0110 1001 + test_h_gr32 0xe9696969 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + +shar_l_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shar.l #2, @er0 ; shift right arithmetic by two, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llind2 + fail +.Llind2: + mov #0xa5a5a5a5, @long_dest + +shar_l_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shar.l #2, @er0+ ; shift right arithmetic by two, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llpostinc2 + fail +.Llpostinc2: + mov #0xa5a5a5a5, @long_dest + +shar_l_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shar.l #2, @er0- ; shift right arithmetic by two, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llpostdec2 + fail +.Llpostdec2: + mov #0xa5a5a5a5, @long_dest + +shar_l_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shar.l #2, @+er0 ; shift right arithmetic by two, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llpreinc2 + fail +.Llpreinc2: + mov #0xa5a5a5a5, @long_dest + +shar_l_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shar.l #2, @-er0 ; shift right arithmetic by two, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llpredec2 + fail +.Llpredec2: + mov #0xa5a5a5a5, @long_dest + +shar_l_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shar.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Lldisp22 + fail +.Lldisp22: + mov #0xa5a5a5a5, @long_dest + +shar_l_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shar.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Lldisp162 + fail +.Lldisp162: + mov #0xa5a5a5a5, @long_dest + +shar_l_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shar.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Lldisp322 + fail +.Lldisp322: + mov #0xa5a5a5a5, @long_dest + +shar_l_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llabs162 + fail +.Llabs162: + mov #0xa5a5a5a5, @long_dest + +shar_l_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llabs322 + fail +.Llabs322: + mov #0xa5a5a5a5, @long_dest + +.endif +.endif + pass + + exit 0 + diff --git a/sim/testsuite/h8300/shll.s b/sim/testsuite/h8300/shll.s new file mode 100644 index 0000000..f21a60b --- /dev/null +++ b/sim/testsuite/h8300/shll.s @@ -0,0 +1,375 @@ +# Hitachi H8 testcase 'shll' +# mach(): h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +shll_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.b r0l ; shift left logical by one +;;; .word 0x1008 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 +.if (sim_cpu) + test_h_gr32 0xa5a5a54a er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.b #2, r0l ; shift left logical by two +;;; .word 0x1048 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100 +.if (sim_cpu) + test_h_gr32 0xa5a5a594 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shll_b_reg8_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.b #4, r0l ; shift left logical by four +;;; .word 0x10a8 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0xa550 r0 ; 1010 0101 -> 0101 0000 + test_h_gr32 0xa5a5a550 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #5, r0h + shll.b r0h, r0l ; shift left logical by register value + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0x05a0 r0 ; 1010 0101 -> 1010 0000 + test_h_gr32 0xa5a505a0 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; Not available in h8300 mode +shll_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.w r0 ; shift left logical by one +;;; .word 0x1010 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 + test_h_gr32 0xa5a54b4a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.w #2, r0 ; shift left logical by two +;;; .word 0x1050 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100 + test_h_gr32 0xa5a59694 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shll_w_reg16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.w #4, r0 ; shift left logical by four +;;; .word 0x1020 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0x5a50 r0 ; 1010 0101 1010 0101 -> 0101 1010 0101 0000 + test_h_gr32 0xa5a55a50 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_w_reg16_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.w #8, r0 ; shift left logical by eight +;;; .word 0x1060 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0xa500 r0 ; 1010 0101 1010 0101 -> 1010 0101 0000 0000 + test_h_gr32 0xa5a5a500 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_w_reg16_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #5, r0h + shll.w r0h, r0 ; shift left logical by register value + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0xb4a0 r0 ; 1010 0101 1010 0101 -> 1011 0100 1010 0000 + test_h_gr32 0xa5a5b4a0 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +shll_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.l er0 ; shift left logical by one +;;; .word 1030 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1010 + test_h_gr32 0x4b4b4b4a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.l #2, er0 ; shift left logical by two +;;; .word 0x1070 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0100 + test_h_gr32 0x96969694 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shll_l_reg32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.l #4, er0 ; shift left logical by four +;;; .word 0x1038 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0101 1010 0101 1010 0101 1010 0101 0000 + test_h_gr32 0x5a5a5a50 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_l_reg32_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.l #8, er0 ; shift left logical by eight +;;; .word 0x1078 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0xa500 r0 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1010 0101 1010 0101 1010 0101 0000 0000 + test_h_gr32 0xa5a5a500 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_l_reg32_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.l #16, er0 ; shift left logical by sixteen +;;; .word 0x10f8 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 0101 1010 0101 0000 0000 0000 0000 + test_h_gr32 0xa5a50000 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_l_reg32_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #5, r1l + shll.l r1l, er0 ; shift left logical by register value + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1011 0100 1011 0100 1011 0100 1010 0000 + test_h_gr32 0xb4b4b4a0 er0 + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif +.endif + + pass + + exit 0 + diff --git a/sim/testsuite/h8300/shlr.s b/sim/testsuite/h8300/shlr.s new file mode 100644 index 0000000..c9f6a08 --- /dev/null +++ b/sim/testsuite/h8300/shlr.s @@ -0,0 +1,4085 @@ +# Hitachi H8 testcase 'shlr' +# mach(): h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +shlr_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b r0l ; shift right logical by one +;;; .word 0x1108 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010 +.if (sim_cpu) + test_h_gr32 0xa5a5a552 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shlr_b_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b @er0 ; shift right logical by one, indirect +;;; .word 0x7d00 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbind1 + fail +.Lbind1: + mov.b #0xa5, @byte_dest + +shlr_b_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b @er0+ ; shift right logical by one, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpostinc1 + fail +.Lbpostinc1: + mov.b #0xa5, @byte_dest + +shlr_b_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b @er0- ; shift right logical by one, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpostdec1 + fail +.Lbpostdec1: + mov.b #0xa5, @byte_dest + +shlr_b_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + shlr.b @+er0 ; shift right logical by one, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpreinc1 + fail +.Lbpreinc1: + mov.b #0xa5, @byte_dest + +shlr_b_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + shlr.b @-er0 ; shift right logical by one, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpredec1 + fail +.Lbpredec1: + mov.b #0xa5, @byte_dest + +shlr_b_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + shlr.b @(2:2, er0) ; shift right logical by one, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbdisp21 + fail +.Lbdisp21: + mov.b #0xa5, @byte_dest + +shlr_b_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + shlr.b @(44:16, er0) ; shift right logical by one, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbdisp161 + fail +.Lbdisp161: + mov.b #0xa5, @byte_dest + +shlr_b_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + shlr.b @(666:32, er0) ; shift right logical by one, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbdisp321 + fail +.Lbdisp321: + mov.b #0xa5, @byte_dest + +shlr_b_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b @byte_dest:16 ; shift right logical by one, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbabs161 + fail +.Lbabs161: + mov.b #0xa5, @byte_dest + +shlr_b_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b @byte_dest:32 ; shift right logical by one, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbabs321 + fail +.Lbabs321: + mov.b #0xa5, @byte_dest +.endif + +shlr_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b #2, r0l ; shift right logical by two +;;; .word 0x1148 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0xa529 r0 ; 1010 0101 -> 0010 1001 +.if (sim_cpu) + test_h_gr32 0xa5a5a529 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shlr_b_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b #2, @er0 ; shift right logical by two, indirect +;;; .word 0x7d00 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbind2 + fail +.Lbind2: + mov.b #0xa5, @byte_dest + +shlr_b_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b #2, @er0+ ; shift right logical by two, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbpostinc2 + fail +.Lbpostinc2: + mov.b #0xa5, @byte_dest + +shlr_b_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b #2, @er0- ; shift right logical by two, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbpostdec2 + fail +.Lbpostdec2: + mov.b #0xa5, @byte_dest + +shlr_b_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + shlr.b #2, @+er0 ; shift right logical by two, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbpreinc2 + fail +.Lbpreinc2: + mov.b #0xa5, @byte_dest + +shlr_b_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + shlr.b #2, @-er0 ; shift right logical by two, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbpredec2 + fail +.Lbpredec2: + mov.b #0xa5, @byte_dest + +shlr_b_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + shlr.b #2, @(2:2, er0) ; shift right logical by two, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbdisp22 + fail +.Lbdisp22: + mov.b #0xa5, @byte_dest + +shlr_b_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + shlr.b #2, @(44:16, er0) ; shift right logical by two, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbdisp162 + fail +.Lbdisp162: + mov.b #0xa5, @byte_dest + +shlr_b_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + shlr.b #2, @(666:32, er0) ; shift right logical by two, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbdisp322 + fail +.Lbdisp322: + mov.b #0xa5, @byte_dest + +shlr_b_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b #2, @byte_dest:16 ; shift right logical by two, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbabs162 + fail +.Lbabs162: + mov.b #0xa5, @byte_dest + +shlr_b_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b #2, @byte_dest:32 ; shift right logical by two, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbabs322 + fail +.Lbabs322: + mov.b #0xa5, @byte_dest + +shlr_b_reg8_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b #4, r0l ; shift right logical by four +;;; .word 0x11a8 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0xa50a r0 ; 1010 0101 -> 0000 1010 + test_h_gr32 0xa5a5a50a er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #5, r0h + shlr.b r0h, r0l ; shift right logical by register value + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x0505 r0 ; 1010 0101 -> 0000 0101 + test_h_gr32 0xa5a50505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_b_ind_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b #4, @er0 ; shift right logical by four, indirect +;;; .word 0x7d00 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbind4 + fail +.Lbind4: + mov.b #0xa5, @byte_dest + +shlr_b_postinc_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b #4, @er0+ ; shift right logical by four, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbpostinc4 + fail +.Lbpostinc4: + mov.b #0xa5, @byte_dest + +shlr_b_postdec_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b #4, @er0- ; shift right logical by four, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbpostdec4 + fail +.Lbpostdec4: + mov.b #0xa5, @byte_dest + +shlr_b_preinc_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + shlr.b #4, @+er0 ; shift right logical by four, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbpreinc4 + fail +.Lbpreinc4: + mov.b #0xa5, @byte_dest + +shlr_b_predec_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + shlr.b #4, @-er0 ; shift right logical by four, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbpredec4 + fail +.Lbpredec4: + mov.b #0xa5, @byte_dest + +shlr_b_disp2_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + shlr.b #4, @(2:2, er0) ; shift right logical by four, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbdisp24 + fail +.Lbdisp24: + mov.b #0xa5, @byte_dest + +shlr_b_disp16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + shlr.b #4, @(44:16, er0) ; shift right logical by four, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbdisp164 + fail +.Lbdisp164: + mov.b #0xa5, @byte_dest + +shlr_b_disp32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + shlr.b #4, @(666:32, er0) ; shift right logical by four, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbdisp324 + fail +.Lbdisp324: + mov.b #0xa5, @byte_dest + +shlr_b_abs16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b #4, @byte_dest:16 ; shift right logical by four, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbabs164 + fail +.Lbabs164: + mov.b #0xa5, @byte_dest + +shlr_b_abs32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b #4, @byte_dest:32 ; shift right logical by four, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbabs324 + fail +.Lbabs324: + mov.b #0xa5, @byte_dest +.endif + +.if (sim_cpu == h8sx) +shlr_w_imm5_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #15:5, r0 ; shift right logical by 5-bit immediate +;;; .word 0x038f +;;; .word 0x1110 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + ; 1010 0101 1010 0101 -> 0000 0000 0000 0001 + test_h_gr32 0xa5a50001 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; Not available in h8300 mode +shlr_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w r0 ; shift right logical by one +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + test_h_gr32 0xa5a552d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shlr_w_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w @er0 ; shift right logical by one, indirect +;;; .word 0x7d80 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwind1 + fail +.Lwind1: + mov.w #0xa5a5, @word_dest + +shlr_w_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w @er0+ ; shift right logical by one, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpostinc1 + fail +.Lwpostinc1: + mov.w #0xa5a5, @word_dest + +shlr_w_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w @er0- ; shift right logical by one, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpostdec1 + fail +.Lwpostdec1: + mov.w #0xa5a5, @word_dest + +shlr_w_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + shlr.w @+er0 ; shift right logical by one, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpreinc1 + fail +.Lwpreinc1: + mov.w #0xa5a5, @word_dest + +shlr_w_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + shlr.w @-er0 ; shift right logical by one, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpredec1 + fail +.Lwpredec1: + mov.w #0xa5a5, @word_dest + +shlr_w_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + shlr.w @(4:2, er0) ; shift right logical by one, disp2 +;;; .word 0x0156 +;;; .word 0x6908 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwdisp21 + fail +.Lwdisp21: + mov.w #0xa5a5, @word_dest + +shlr_w_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + shlr.w @(44:16, er0) ; shift right logical by one, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwdisp161 + fail +.Lwdisp161: + mov.w #0xa5a5, @word_dest + +shlr_w_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + shlr.w @(666:32, er0) ; shift right logical by one, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwdisp321 + fail +.Lwdisp321: + mov.w #0xa5a5, @word_dest + +shlr_w_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w @word_dest:16 ; shift right logical by one, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwabs161 + fail +.Lwabs161: + mov.w #0xa5a5, @word_dest + +shlr_w_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w @word_dest:32 ; shift right logical by one, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwabs321 + fail +.Lwabs321: + mov.w #0xa5a5, @word_dest +.endif + +shlr_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #2, r0 ; shift right logical by two +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x2969 r0 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + test_h_gr32 0xa5a52969 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shlr_w_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #2, @er0 ; shift right logical by two, indirect +;;; .word 0x7d80 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwind2 + fail +.Lwind2: + mov.w #0xa5a5, @word_dest + +shlr_w_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #2, @er0+ ; shift right logical by two, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwpostinc2 + fail +.Lwpostinc2: + mov.w #0xa5a5, @word_dest + +shlr_w_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #2, @er0- ; shift right logical by two, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwpostdec2 + fail +.Lwpostdec2: + mov.w #0xa5a5, @word_dest + +shlr_w_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + shlr.w #2, @+er0 ; shift right logical by two, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwpreinc2 + fail +.Lwpreinc2: + mov.w #0xa5a5, @word_dest + +shlr_w_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + shlr.w #2, @-er0 ; shift right logical by two, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwpredec2 + fail +.Lwpredec2: + mov.w #0xa5a5, @word_dest + +shlr_w_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + shlr.w #2, @(4:2, er0) ; shift right logical by two, disp2 +;;; .word 0x0156 +;;; .word 0x6908 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwdisp22 + fail +.Lwdisp22: + mov.w #0xa5a5, @word_dest + +shlr_w_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + shlr.w #2, @(44:16, er0) ; shift right logical by two, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwdisp162 + fail +.Lwdisp162: + mov.w #0xa5a5, @word_dest + +shlr_w_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + shlr.w #2, @(666:32, er0) ; shift right logical by two, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwdisp322 + fail +.Lwdisp322: + mov.w #0xa5a5, @word_dest + +shlr_w_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #2, @word_dest:16 ; shift right logical by two, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwabs162 + fail +.Lwabs162: + mov.w #0xa5a5, @word_dest + +shlr_w_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #2, @word_dest:32 ; shift right logical by two, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwabs322 + fail +.Lwabs322: + mov.w #0xa5a5, @word_dest + +shlr_w_reg16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #4, r0 ; shift right logical by four +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x0a5a r0 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + test_h_gr32 0xa5a50a5a er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_w_reg16_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #5, r1l + shlr.w r1l, r0 ; shift right logical by register value + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x052d r0 ; 1010 0101 1010 0101 -> 0000 0101 0010 1101 + test_h_gr32 0xa5a5052d er0 + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_w_ind_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #4, @er0 ; shift right logical by four, indirect +;;; .word 0x7d80 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwind4 + fail +.Lwind4: + mov.w #0xa5a5, @word_dest + +shlr_w_postinc_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #4, @er0+ ; shift right logical by four, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwpostinc4 + fail +.Lwpostinc4: + mov.w #0xa5a5, @word_dest + +shlr_w_postdec_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #4, @er0- ; shift right logical by four, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwpostdec4 + fail +.Lwpostdec4: + mov.w #0xa5a5, @word_dest + +shlr_w_preinc_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + shlr.w #4, @+er0 ; shift right logical by four, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwpreinc4 + fail +.Lwpreinc4: + mov.w #0xa5a5, @word_dest + +shlr_w_predec_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + shlr.w #4, @-er0 ; shift right logical by four, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwpredec4 + fail +.Lwpredec4: + mov.w #0xa5a5, @word_dest + +shlr_w_disp2_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + shlr.w #4, @(4:2, er0) ; shift right logical by four, disp2 +;;; .word 0x0156 +;;; .word 0x6908 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwdisp24 + fail +.Lwdisp24: + mov.w #0xa5a5, @word_dest + +shlr_w_disp16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + shlr.w #4, @(44:16, er0) ; shift right logical by four, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwdisp164 + fail +.Lwdisp164: + mov.w #0xa5a5, @word_dest + +shlr_w_disp32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + shlr.w #4, @(666:32, er0) ; shift right logical by four, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwdisp324 + fail +.Lwdisp324: + mov.w #0xa5a5, @word_dest + +shlr_w_abs16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #4, @word_dest:16 ; shift right logical by four, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwabs164 + fail +.Lwabs164: + mov.w #0xa5a5, @word_dest + +shlr_w_abs32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #4, @word_dest:32 ; shift right logical by four, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwabs324 + fail +.Lwabs324: + mov.w #0xa5a5, @word_dest + +shlr_w_reg16_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #8, r0 ; shift right logical by eight +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x00a5 r0 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + test_h_gr32 0xa5a500a5 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_w_ind_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #8, @er0 ; shift right logical by eight, indirect +;;; .word 0x7d80 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwind8 + fail +.Lwind8: + mov.w #0xa5a5, @word_dest + +shlr_w_postinc_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #8, @er0+ ; shift right logical by eight, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwpostinc8 + fail +.Lwpostinc8: + mov.w #0xa5a5, @word_dest + +shlr_w_postdec_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #8, @er0- ; shift right logical by eight, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwpostdec8 + fail +.Lwpostdec8: + mov.w #0xa5a5, @word_dest + +shlr_w_preinc_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + shlr.w #8, @+er0 ; shift right logical by eight, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwpreinc8 + fail +.Lwpreinc8: + mov.w #0xa5a5, @word_dest + +shlr_w_predec_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + shlr.w #8, @-er0 ; shift right logical by eight, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwpredec8 + fail +.Lwpredec8: + mov.w #0xa5a5, @word_dest + +shlr_w_disp2_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + shlr.w #8, @(4:2, er0) ; shift right logical by eight, disp2 +;;; .word 0x0156 +;;; .word 0x6908 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwdisp28 + fail +.Lwdisp28: + mov.w #0xa5a5, @word_dest + +shlr_w_disp16_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + shlr.w #8, @(44:16, er0) ; shift right logical by eight, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwdisp168 + fail +.Lwdisp168: + mov.w #0xa5a5, @word_dest + +shlr_w_disp32_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + shlr.w #8, @(666:32, er0) ; shift right logical by eight, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwdisp328 + fail +.Lwdisp328: + mov.w #0xa5a5, @word_dest + +shlr_w_abs16_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #8, @word_dest:16 ; shift right logical by eight, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwabs168 + fail +.Lwabs168: + mov.w #0xa5a5, @word_dest + +shlr_w_abs32_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #8, @word_dest:32 ; shift right logical by eight, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwabs328 + fail +.Lwabs328: + mov.w #0xa5a5, @word_dest + +shlr_l_imm5_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #31:5, er0 ; shift right logical by 5-bit immediate +;;; .word 0x0399 +;;; .word 0x1130 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0000 0000 0000 0000 0000 0000 0000 0001 + test_h_gr32 0x1 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +shlr_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l er0 ; shift right logical by one, register +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0101 0010 1101 0010 1101 0010 1101 0010 + test_h_gr32 0x52d2d2d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shlr_l_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l @er0 ; shift right logical by one, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llind1 + fail +.Llind1: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l @er0+ ; shift right logical by one, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpostinc1 + fail +.Llpostinc1: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l @er0- ; shift right logical by one, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpostdec1 + fail +.Llpostdec1: + mov #0xa5a5a5a5, @long_dest + +shlr_l_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shlr.l @+er0 ; shift right logical by one, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpreinc1 + fail +.Llpreinc1: + mov #0xa5a5a5a5, @long_dest + +shlr_l_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shlr.l @-er0 ; shift right logical by one, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpredec1 + fail +.Llpredec1: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shlr.l @(8:2, er0) ; shift right logical by one, disp2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Lldisp21 + fail +.Lldisp21: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shlr.l @(44:16, er0) ; shift right logical by one, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Lldisp161 + fail +.Lldisp161: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shlr.l @(666:32, er0) ; shift right logical by one, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Lldisp321 + fail +.Lldisp321: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l @long_dest:16 ; shift right logical by one, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llabs161 + fail +.Llabs161: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l @long_dest:32 ; shift right logical by one, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llabs321 + fail +.Llabs321: + mov #0xa5a5a5a5, @long_dest +.endif + +shlr_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #2, er0 ; shift right logical by two, register +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0010 1001 0110 1001 0110 1001 0110 1001 + test_h_gr32 0x29696969 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + +shlr_l_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #2, @er0 ; shift right logical by two, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llind2 + fail +.Llind2: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #2, @er0+ ; shift right logical by two, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llpostinc2 + fail +.Llpostinc2: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #2, @er0- ; shift right logical by two, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llpostdec2 + fail +.Llpostdec2: + mov #0xa5a5a5a5, @long_dest + +shlr_l_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shlr.l #2, @+er0 ; shift right logical by two, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llpreinc2 + fail +.Llpreinc2: + mov #0xa5a5a5a5, @long_dest + +shlr_l_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shlr.l #2, @-er0 ; shift right logical by two, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llpredec2 + fail +.Llpredec2: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shlr.l #2, @(8:2, er0) ; shift right logical by two, disp2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Lldisp22 + fail +.Lldisp22: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shlr.l #2, @(44:16, er0) ; shift right logical by two, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Lldisp162 + fail +.Lldisp162: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shlr.l #2, @(666:32, er0) ; shift right logical by two, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Lldisp322 + fail +.Lldisp322: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #2, @long_dest:16 ; shift right logical by two, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llabs162 + fail +.Llabs162: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #2, @long_dest:32 ; shift right logical by two, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llabs322 + fail +.Llabs322: + mov #0xa5a5a5a5, @long_dest + +shlr_l_reg32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #4, er0 ; shift right logical by four, register +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0000 1010 0101 1010 0101 1010 0101 1010 + test_h_gr32 0x0a5a5a5a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_l_reg32_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #5, r1l + shlr.l r1l, er0 ; shift right logical by value of register + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0000 0101 0010 1101 0010 1101 0010 1101 + test_h_gr32 0x052d2d2d er0 + test_h_gr32 0xa5a5a505 er1 + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_l_ind_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #4, @er0 ; shift right logical by four, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llind4 + fail +.Llind4: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postinc_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #4, @er0+ ; shift right logical by four, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llpostinc4 + fail +.Llpostinc4: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postdec_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #4, @er0- ; shift right logical by four, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llpostdec4 + fail +.Llpostdec4: + mov #0xa5a5a5a5, @long_dest + +shlr_l_preinc_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shlr.l #4, @+er0 ; shift right logical by four, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llpreinc4 + fail +.Llpreinc4: + mov #0xa5a5a5a5, @long_dest + +shlr_l_predec_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shlr.l #4, @-er0 ; shift right logical by four, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llpredec4 + fail +.Llpredec4: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp2_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shlr.l #4, @(8:2, er0) ; shift right logical by four, disp2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Lldisp24 + fail +.Lldisp24: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shlr.l #4, @(44:16, er0) ; shift right logical by four, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Lldisp164 + fail +.Lldisp164: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shlr.l #4, @(666:32, er0) ; shift right logical by four, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Lldisp324 + fail +.Lldisp324: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #4, @long_dest:16 ; shift right logical by four, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llabs164 + fail +.Llabs164: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #4, @long_dest:32 ; shift right logical by four, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llabs324 + fail +.Llabs324: + mov #0xa5a5a5a5, @long_dest + +shlr_l_reg32_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #8, er0 ; shift right logical by eight, register +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0000 0000 1010 0101 1010 0101 1010 0101 + test_h_gr32 0x00a5a5a5 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_l_ind_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #8, @er0 ; shift right logical by eight, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llind8 + fail +.Llind8: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postinc_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #8, @er0+ ; shift right logical by eight, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llpostinc8 + fail +.Llpostinc8: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postdec_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #8, @er0- ; shift right logical by eight, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llpostdec8 + fail +.Llpostdec8: + mov #0xa5a5a5a5, @long_dest + +shlr_l_preinc_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shlr.l #8, @+er0 ; shift right logical by eight, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llpreinc8 + fail +.Llpreinc8: + mov #0xa5a5a5a5, @long_dest + +shlr_l_predec_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shlr.l #8, @-er0 ; shift right logical by eight, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llpredec8 + fail +.Llpredec8: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp2_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shlr.l #8, @(8:2, er0) ; shift right logical by eight, disp2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Lldisp28 + fail +.Lldisp28: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp16_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shlr.l #8, @(44:16, er0) ; shift right logical by eight, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Lldisp168 + fail +.Lldisp168: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp32_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shlr.l #8, @(666:32, er0) ; shift right logical by eight, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Lldisp328 + fail +.Lldisp328: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs16_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #8, @long_dest:16 ; shift right logical by eight, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llabs168 + fail +.Llabs168: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs32_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #8, @long_dest:32 ; shift right logical by eight, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llabs328 + fail +.Llabs328: + mov #0xa5a5a5a5, @long_dest + +shlr_l_reg32_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #16, er0 ; shift right logical by sixteen, register +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + test_h_gr32 0x0000a5a5 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_l_ind_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #16, @er0 ; shift right logical by sixteen, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llind16 + fail +.Llind16: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postinc_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #16, @er0+ ; shift right logical by sixteen, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llpostinc16 + fail +.Llpostinc16: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postdec_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #16, @er0- ; shift right logical by sixteen, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llpostdec16 + fail +.Llpostdec16: + mov #0xa5a5a5a5, @long_dest + +shlr_l_preinc_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shlr.l #16, @+er0 ; shift right logical by sixteen, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llpreinc16 + fail +.Llpreinc16: + mov #0xa5a5a5a5, @long_dest + +shlr_l_predec_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shlr.l #16, @-er0 ; shift right logical by sixteen, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llpredec16 + fail +.Llpredec16: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp2_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shlr.l #16, @(8:2, er0) ; shift right logical by 16, dest2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Lldisp216 + fail +.Lldisp216: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp16_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shlr.l #16, @(44:16, er0) ; shift right logical by 16, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Lldisp1616 + fail +.Lldisp1616: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp32_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shlr.l #16, @(666:32, er0) ; shift right logical by 16, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Lldisp3216 + fail +.Lldisp3216: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs16_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #16, @long_dest:16 ; shift right logical by 16, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llabs1616 + fail +.Llabs1616: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs32_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #16, @long_dest:32 ; shift right logical by 16, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llabs3216 + fail +.Llabs3216: + mov #0xa5a5a5a5, @long_dest +.endif +.endif + pass + + exit 0 + diff --git a/sim/testsuite/h8300/stack.s b/sim/testsuite/h8300/stack.s new file mode 100644 index 0000000..dd53445 --- /dev/null +++ b/sim/testsuite/h8300/stack.s @@ -0,0 +1,445 @@ +# Hitachi H8 testcase 'ldc' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.data + .align 4 +stack: +.if (sim_cpu == h8300) + .fill 128, 2, 0 +.else + .fill 128, 4, 0 +.endif +stacktop: + + .text + +push_w: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero +.if (sim_cpu == h8300) + mov.w #stacktop, r7 +.else + mov.l #stacktop, er7 +.endif + push.w r0 ; a5a5 is negative + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + push.w r1 + push.w r2 + push.w r3 + + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + + mov @stacktop-2, r0 + test_gr_a5a5 0 + mov @stacktop-4, r0 + test_gr_a5a5 0 + mov @stacktop-6, r0 + test_gr_a5a5 0 + mov @stacktop-8, r0 + test_gr_a5a5 0 + + mov.w #1, r1 + mov.w #2, r2 + mov.w #3, r3 + mov.w #4, r4 + + push.w r1 ; #1 is non-negative, non-zero + test_cc_clear + + push.w r2 + push.w r3 + push.w r4 + + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 + + mov @stacktop-10, r0 + test_h_gr16 1 r0 + mov @stacktop-12, r0 + test_h_gr16 2 r0 + mov @stacktop-14, r0 + test_h_gr16 3 r0 + mov @stacktop-16, r0 + test_h_gr16 4 r0 + +.if (sim_cpu == h8300) + test_h_gr16 4 r0 + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 +;;; test_h_gr16 stacktop-16 r7 ; FIXME +.else + test_h_gr32 0xa5a50004 er0 + test_h_gr32 0xa5a50001 er1 + test_h_gr32 0xa5a50002 er2 + test_h_gr32 0xa5a50003 er3 + test_h_gr32 0xa5a50004 er4 + test_h_gr32 stacktop-16 er7 +.endif + test_gr_a5a5 5 + test_gr_a5a5 6 + +pop_w: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero +.if (sim_cpu == h8300) + mov.w #stacktop-16, r7 +.else + mov.l #stacktop-16, er7 +.endif + pop.w r4 + pop.w r3 + pop.w r2 + pop.w r1 ; Should set all flags zero + test_cc_clear + + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 + + pop.w r4 + pop.w r3 + pop.w r2 + pop.w r1 ; a5a5 is negative + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 +.if (sim_cpu == h8300) +;;; test_h_gr16 stacktop r7 ; FIXME +.else + test_h_gr32 stacktop er7 +.endif + +.if (sim_cpu) ; non-zero means not h8300 +push_l: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + mov.l #stacktop, er7 + push.l er0 ; a5a5 is negative + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + push.l er1 + push.l er2 + push.l er3 + + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + + mov @stacktop-4, er0 + test_gr_a5a5 0 + mov @stacktop-8, er0 + test_gr_a5a5 0 + mov @stacktop-12, er0 + test_gr_a5a5 0 + mov @stacktop-16, er0 + test_gr_a5a5 0 + + mov #1, er1 + mov #2, er2 + mov #3, er3 + mov #4, er4 + + push.l er1 ; #1 is non-negative, non-zero + test_cc_clear + + push.l er2 + push.l er3 + push.l er4 + + test_h_gr32 1 er1 + test_h_gr32 2 er2 + test_h_gr32 3 er3 + test_h_gr32 4 er4 + + mov @stacktop-20, er0 + test_h_gr32 1 er0 + mov @stacktop-24, er0 + test_h_gr32 2 er0 + mov @stacktop-28, er0 + test_h_gr32 3 er0 + mov @stacktop-32, er0 + test_h_gr32 4 er0 + + test_h_gr32 4 er0 + test_h_gr32 1 er1 + test_h_gr32 2 er2 + test_h_gr32 3 er3 + test_h_gr32 4 er4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 stacktop-32 er7 + +pop_l: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + mov.l #stacktop-32, er7 + pop.l er4 + pop.l er3 + pop.l er2 + pop.l er1 ; Should set all flags zero + test_cc_clear + + test_h_gr32 1 er1 + test_h_gr32 2 er2 + test_h_gr32 3 er3 + test_h_gr32 4 er4 + + pop.l er4 + pop.l er3 + pop.l er2 + pop.l er1 ; a5a5 is negative + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 stacktop er7 +.endif + + ;; Jump over subroutine + jmp _bsr + +bsr_jsr_func: + test_ccr 0 ; call should not affect ccr + mov.w #0, r0 + mov.w #1, r1 + mov.w #2, r2 + mov.w #3, r3 + mov.w #4, r4 + mov.w #5, r5 + mov.w #6, r6 + rts + +_bsr: set_grs_a5a5 +.if (sim_cpu == h8300) + mov.w #stacktop, r7 +.else + mov.l #stacktop, er7 +.endif + set_ccr_zero + bsr bsr_jsr_func + + test_h_gr16 0 r0 + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 + test_h_gr16 5 r5 + test_h_gr16 6 r6 +.if (sim_cpu == h8300) +;;; test_h_gr16 stacktop, r7 ; FIXME +.else + test_h_gr32 stacktop, er7 +.endif + +_jsr: set_grs_a5a5 +.if (sim_cpu == h8300) + mov.w #stacktop, r7 +.else + mov.l #stacktop, er7 +.endif + set_ccr_zero + jsr bsr_jsr_func + + test_h_gr16 0 r0 + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 + test_h_gr16 5 r5 + test_h_gr16 6 r6 +.if (sim_cpu == h8300) +;;; test_h_gr16 stacktop, r7 ; FIXME +.else + test_h_gr32 stacktop, er7 +.endif + +.if (sim_cpu) ; not zero ie. not h8300 +_trapa: + set_grs_a5a5 + mov.l #trap_handler, er7 ; trap vector + mov.l er7, @0x2c + mov.l #stacktop, er7 + set_ccr_zero + trapa #3 + + test_cc_clear ; ccr should be restored by rte + test_h_gr16 0x10 r0 + test_h_gr16 0x11 r1 + test_h_gr16 0x12 r2 + test_h_gr16 0x13 r3 + test_h_gr16 0x14 r4 + test_h_gr16 0x15 r5 + test_h_gr16 0x16 r6 + test_h_gr32 stacktop er7 +.endif + +.if (sim_cpu == h8sx) +_rtsl: ; Test rts/l insn. + set_grs_a5a5 + mov #0,r0l + mov #1,r1l + mov #2,r2l + mov #3,r3l + mov #4,r4l + mov #5,r5l + mov #6,r6l + mov #stacktop, er7 + + jsr rtsl1_func + test_h_gr32 0xa5a5a500 er0 + test_h_gr32 0xa5a5a501 er1 + test_h_gr32 0xa5a5a502 er2 + test_h_gr32 0xa5a5a503 er3 + test_h_gr32 0xa5a5a504 er4 + test_h_gr32 0xa5a5a505 er5 + test_h_gr32 0xa5a5a506 er6 + test_h_gr32 stacktop er7 + + jsr rtsl2_func + test_h_gr32 0xa5a5a500 er0 + test_h_gr32 0xa5a5a501 er1 + test_h_gr32 0xa5a5a502 er2 + test_h_gr32 0xa5a5a503 er3 + test_h_gr32 0xa5a5a504 er4 + test_h_gr32 0xa5a5a505 er5 + test_h_gr32 0xa5a5a506 er6 + test_h_gr32 stacktop er7 + + jsr rtsl3_func + test_h_gr32 0xa5a5a500 er0 + test_h_gr32 0xa5a5a501 er1 + test_h_gr32 0xa5a5a502 er2 + test_h_gr32 0xa5a5a503 er3 + test_h_gr32 0xa5a5a504 er4 + test_h_gr32 0xa5a5a505 er5 + test_h_gr32 0xa5a5a506 er6 + test_h_gr32 stacktop er7 + + jsr rtsl4_func + test_h_gr32 0xa5a5a500 er0 + test_h_gr32 0xa5a5a501 er1 + test_h_gr32 0xa5a5a502 er2 + test_h_gr32 0xa5a5a503 er3 + test_h_gr32 0xa5a5a504 er4 + test_h_gr32 0xa5a5a505 er5 + test_h_gr32 0xa5a5a506 er6 + test_h_gr32 stacktop er7 +.endif ; h8sx + + pass + + exit 0 + + ;; Handler for a software exception (trap). +trap_handler: + ;; Test the 'i' interrupt mask flag. + stc ccr, r0l + test_h_gr8 0x80, r0l + ;; Change the registers (so we know we've been here) + mov.w #0x10, r0 + mov.w #0x11, r1 + mov.w #0x12, r2 + mov.w #0x13, r3 + mov.w #0x14, r4 + mov.w #0x15, r5 + mov.w #0x16, r6 + ;; Change the ccr (which will be restored by RTE) + orc #0xff, ccr + rte + +.if (sim_cpu == h8sx) + ;; Functions for testing rts/l +rtsl1_func: ; Save and restore R0 + push.l er0 + ;; Now modify it, and verify the modification. + mov #0xfeedface, er0 + test_h_gr32 0xfeedface, er0 + ;; Then use rts/l to restore them and return. + rts/l er0 + +rtsl2_func: ; Save and restore R5 and R6 + push.l er5 + push.l er6 + ;; Now modify them, and verify the modification. + mov #0xdeadbeef, er5 + mov #0xfeedface, er6 + test_h_gr32 0xdeadbeef, er5 + test_h_gr32 0xfeedface, er6 + ;; Then use rts/l to restore them and return. + rts/l (er5-er6) + +rtsl3_func: ; Save and restore R4, R5, and R6 + push.l er4 + push.l er5 + push.l er6 + ;; Now modify them, and verify the modification. + mov #0xdeafcafe, er4 + mov #0xdeadbeef, er5 + mov #0xfeedface, er6 + test_h_gr32 0xdeafcafe, er4 + test_h_gr32 0xdeadbeef, er5 + test_h_gr32 0xfeedface, er6 + ;; Then use rts/l to restore them and return. + rts/l (er4-er6) + +rtsl4_func: ; Save and restore R0 - R3 + push.l er0 + push.l er1 + push.l er2 + push.l er3 + ;; Now modify them, and verify the modification. + mov #0xdadacafe, er0 + mov #0xfeedbeef, er1 + mov #0xdeadface, er2 + mov #0xf00dd00d, er3 + test_h_gr32 0xdadacafe, er0 + test_h_gr32 0xfeedbeef, er1 + test_h_gr32 0xdeadface, er2 + test_h_gr32 0xf00dd00d, er3 + ;; Then use rts/l to restore them and return. + rts/l (er0-er3) +.endif ; h8sx diff --git a/sim/testsuite/h8300/stc.s b/sim/testsuite/h8300/stc.s new file mode 100644 index 0000000..232bd5a --- /dev/null +++ b/sim/testsuite/h8300/stc.s @@ -0,0 +1,401 @@ +# Hitachi H8 testcase 'stc' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + .data +byte_dest1: + .byte 0 + .byte 0 +byte_dest2: + .byte 0 + .byte 0 +byte_dest3: + .byte 0 + .byte 0 +byte_dest4: + .byte 0 + .byte 0 +byte_dest5: + .byte 0 + .byte 0 +byte_dest6: + .byte 0 + .byte 0 +byte_dest7: + .byte 0 + .byte 0 +byte_dest8: + .byte 0 + .byte 0 +byte_dest9: + .byte 0 + .byte 0 +byte_dest10: + .byte 0 + .byte 0 +byte_dest11: + .byte 0 + .byte 0 +byte_dest12: + .byte 0 + .byte 0 + + start + +stc_ccr_reg8: + set_grs_a5a5 + set_ccr_zero + + ldc #0xff, ccr ; test value + stc ccr, r0h ; copy test value to r0h + + test_h_gr16 0xffa5 r0 ; ff in r0h, a5 in r0l +.if (sim_cpu) ; h/s/sx + test_h_gr32 0xa5a5ffa5 er0 ; ff in r0h, a5 everywhere else +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +stc_exr_reg8: + set_grs_a5a5 + set_ccr_zero + + ldc #0x87, exr ; set exr to 0x87 + stc exr, r0l ; retrieve and check exr value + cmp.b #0x87, r0l + beq .L21 + fail +.L21: + test_h_gr32 0xa5a5a587 er0 ; Register 0 modified by test procedure. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_ccr_abs16: + set_grs_a5a5 + set_ccr_zero + + ldc #0xff, ccr + stc ccr, @byte_dest1:16 ; abs16 dest + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_exr_abs16: + set_grs_a5a5 + set_ccr_zero + + ldc #0x87, exr + stc exr, @byte_dest2:16 ; abs16 dest + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_ccr_abs32: + set_grs_a5a5 + set_ccr_zero + + ldc #0xff, ccr + stc ccr, @byte_dest3:32 ; abs32 dest + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_exr_abs32: + set_grs_a5a5 + set_ccr_zero + + ldc #0x87, exr + stc exr, @byte_dest4:32 ; abs32 dest + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_ccr_disp16: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest5-1, er1 + ldc #0xff, ccr + stc ccr, @(1:16,er1) ; disp16 dest (5) + + test_h_gr32 byte_dest5-1, er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_exr_disp16: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest6+1, er1 + ldc #0x87, exr + stc exr, @(-1:16,er1) ; disp16 dest (6) + + test_h_gr32 byte_dest6+1, er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_ccr_disp32: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest7-1, er1 + ldc #0xff, ccr + stc ccr, @(1:32,er1) ; disp32 dest (7) + + test_h_gr32 byte_dest7-1, er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_exr_disp32: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest8+1, er1 + ldc #0x87, exr + stc exr, @(-1:32,er1) ; disp16 dest (8) + + test_h_gr32 byte_dest8+1, er1 ; er1 still contains address + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_ccr_predecr: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest9+2, er1 + ldc #0xff, ccr + stc ccr, @-er1 ; predecr dest (9) + + test_h_gr32 byte_dest9 er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_exr_predecr: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest10+2, er1 + ldc #0x87, exr + stc exr, @-er1 ; predecr dest (10) + + test_h_gr32 byte_dest10, er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_ccr_ind: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest11, er1 + ldc #0xff, ccr + stc ccr, @er1 ; postinc dest (11) + + test_h_gr32 byte_dest11, er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_exr_ind: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest12, er1 + ldc #0x87, exr + stc exr, @er1, exr ; postinc dest (12) + + test_h_gr32 byte_dest12, er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx +stc_sbr_reg: + set_grs_a5a5 + set_ccr_zero + + mov #0xaaaaaaaa, er0 + ldc er0, sbr ; set sbr to 0xaaaaaaaa + stc sbr, er1 ; retreive and check sbr value + + test_h_gr32 0xaaaaaaaa er1 + test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_vbr_reg: + set_grs_a5a5 + set_ccr_zero + + mov #0xaaaaaaaa, er0 + ldc er0, vbr ; set sbr to 0xaaaaaaaa + stc vbr, er1 ; retreive and check sbr value + + test_h_gr32 0xaaaaaaaa er1 + test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +check_results: + ;; Now check results + mov @byte_dest1, r0h + cmp.b #0xff, r0h + beq .L1 + fail + +.L1: mov @byte_dest2, r0h + cmp.b #0x87, r0h + beq .L2 + fail + +.L2: mov @byte_dest3, r0h + cmp.b #0xff, r0h + beq .L3 + fail + +.L3: mov @byte_dest4, r0h + cmp.b #0x87, r0h + beq .L4 + fail + +.L4: mov @byte_dest5, r0h + cmp.b #0xff, r0h + beq .L5 + fail + +.L5: mov @byte_dest6, r0h + cmp.b #0x87, r0h + beq .L6 + fail + +.L6: mov @byte_dest7, r0h + cmp.b #0xff, r0h + beq .L7 + fail + +.L7: mov @byte_dest8, r0h + cmp.b #0x87, r0h + beq .L8 + fail + +.L8: mov @byte_dest9, r0h + cmp.b #0xff, r0h + beq .L9 + fail + +.L9: mov @byte_dest10, r0h + cmp.b #0x87, r0h + beq .L10 + fail + +.L10: mov @byte_dest11, r0h + cmp.b #0xff, r0h + beq .L11 + fail + +.L11: mov @byte_dest12, r0h + cmp.b #0x87, r0h + beq .L12 + fail + +.L12: +.endif + pass + + exit 0 diff --git a/sim/testsuite/h8300/subb.s b/sim/testsuite/h8300/subb.s new file mode 100644 index 0000000..0183294 --- /dev/null +++ b/sim/testsuite/h8300/subb.s @@ -0,0 +1,289 @@ +# Hitachi H8 testcase 'sub.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # sub.b #xx:8, rd ; + # sub.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx + # sub.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx + # sub.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx + # sub.b rs, rd ; 1 8 rs rd + # sub.b reg8, @erd ; 7 d rd ???? 1 8 rs ???? + # sub.b reg8, @erd+ ; 0 1 7 9 8 rd 3 rs + # sub.b reg8, @erd- ; 0 1 7 9 a rd 3 rs + # + + # Coming soon: + # sub.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx + # sub.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx + # sub.b reg8, @+erd ; 0 1 7 9 9 rd 3 rs + # sub.b reg8, @-erd ; 0 1 7 9 b rd 3 rs + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0xa5 +post_byte: .byte 0 + + start + +.if (0) ; Guess what? Sub.b immediate reg8 is illegal! +sub_b_imm8_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.b #xx:8,Rd + sub.b #5, r0l ; Immediate 8-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu == h8sx) +sub_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b #xx:8,@eRd + mov #byte_dest, er0 + sub.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xa105 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L1 + fail +.L1: + +sub_b_imm8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b #xx:8,@eRd+ + mov #byte_dest, er0 + sub.b #5:8, @er0+ ; Immediate 8-bit src, reg post-incr dest +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xa105 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte, er0 ; er0 still contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x9b, r0l + beq .L2 + fail +.L2: + +sub_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b #xx:8,@eRd- + mov #byte_dest, er0 + sub.b #5:8, @er0- ; Immediate 8-bit src, reg post-decr dest +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xa105 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte, er0 ; er0 still contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x96, r0l + beq .L3 + fail +.L3: + +.endif + +sub_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.b Rs,Rd + mov.b #5, r0h + sub.b r0h, r0l ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x05a0 r0 ; sub result: a5 - 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +sub_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b rs8,@eRd ; Subx to register indirect + mov #byte_dest, er0 + mov #5, r1l + sub.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1890 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x91, r0l + beq .L4 + fail +.L4: + +sub_b_reg8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b rs8,@eRd+ ; Subx to register indirect + mov #byte_dest, er0 + mov #5, r1l + sub.b r1l, @er0+ ; reg8 src, reg indirect dest +;;; .word 0x0179 +;;; .word 0x8039 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte er0 ; er0 still contains address plus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x8c, r0l + beq .L5 + fail +.L5: + +sub_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b rs8,@eRd- ; Subx to register indirect + mov #byte_dest, er0 + mov #5, r1l + sub.b r1l, @er0- ; reg8 src, reg indirect dest +;;; .word 0x0179 +;;; .word 0xa039 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte er0 ; er0 still contains address minus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x87, r0l + beq .L6 + fail +.L6: + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/h8300/subl.s b/sim/testsuite/h8300/subl.s new file mode 100644 index 0000000..7f62f11 --- /dev/null +++ b/sim/testsuite/h8300/subl.s @@ -0,0 +1,91 @@ +# Hitachi H8 testcase 'sub.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; +sub_l_imm3: ; 3-bit immediate mode only for h8sx + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.l #xx:3,eRd ; Immediate 3-bit operand + sub.l #7:3, er0 + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +sub_l_imm16: ; sub immediate 16-bit value + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.l #xx:16,eRd ; Immediate 16-bit operand + sub.l #0x1111:16, er0 + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111 + test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +sub_l_imm32: + ;; sub.l immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.l #xx:32,Rd + sub.l #0x11111111, er0 ; Immediate 32-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +sub.l.reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.l Rs,Rd + mov.l #0x11111111, er1 + sub.l er1, er0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111 + test_h_gr32 0x11111111 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/subs.s b/sim/testsuite/h8300/subs.s new file mode 100644 index 0000000..1bb5eea --- /dev/null +++ b/sim/testsuite/h8300/subs.s @@ -0,0 +1,74 @@ +# Hitachi H8 testcase 'subs' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # subs #1, erd ; 1 b 0 0erd + # subs #2, erd ; 1 b 8 0erd + # subs #4, erd ; 1 b 9 0erd + # + + start +.if (sim_cpu) ; 32 bit only +subs_1: + set_grs_a5a5 + set_ccr_zero + + subs #1, er0 + + test_cc_clear ; subs should not affect any condition codes + test_h_gr32 0xa5a5a5a4 er0 ; result of subs #1 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subs_2: + set_grs_a5a5 + set_ccr_zero + + subs #2, er0 + + test_cc_clear ; subs should not affect any condition codes + test_h_gr32 0xa5a5a5a3 er0 ; result of subs #2 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subs_4: + set_grs_a5a5 + set_ccr_zero + + subs #4, er0 + + test_cc_clear ; subs should not affect any condition codes + test_h_gr32 0xa5a5a5a1 er0 ; result of subs #4 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass +.endif + exit 0 diff --git a/sim/testsuite/h8300/subw.s b/sim/testsuite/h8300/subw.s new file mode 100644 index 0000000..2370250 --- /dev/null +++ b/sim/testsuite/h8300/subw.s @@ -0,0 +1,78 @@ +# Hitachi H8 testcase 'sub.w' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start +.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx +sub_w_imm3: ; sub.w immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.w #xx:3,Rd ; Immediate 3-bit operand + sub.w #7:3, r0 + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa59e r0 ; sub result: a5a5 - 7 + test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +sub_w_imm16: ; sub.w immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.w #xx:16,Rd + sub.w #0x111, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111 + test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +sub.w.reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.w Rs,Rd + mov.w #0x111, r1 + sub.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111 + test_h_gr16 0x0111 r1 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111 + test_h_gr32 0xa5a50111 er1 +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/subx.s b/sim/testsuite/h8300/subx.s new file mode 100644 index 0000000..78656bc --- /dev/null +++ b/sim/testsuite/h8300/subx.s @@ -0,0 +1,1010 @@ +# Hitachi H8 testcase 'subx' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # subx.b #xx:8, rd8 ; b rd8 xxxxxxxx + # subx.b #xx:8, @erd ; 7 d erd ???? b ???? xxxxxxxx + # subx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? b ???? xxxxxxxx + # subx.b rs8, rd8 ; 1 e rs8 rd8 + # subx.b rs8, @erd ; 7 d erd ???? 1 e rs8 ???? + # subx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 1 e rs8 ???? + # subx.b @ers, rd8 ; 7 c ers ???? 1 e ???? rd8 + # subx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 1 e ???? rd8 + # subx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 3 ???? + # subx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 3 ???? + # + # word ops + # long ops + +.data +byte_src: .byte 0x5 +byte_dest: .byte 0 + + .align 2 +word_src: .word 0x505 +word_dest: .word 0 + + .align 4 +long_src: .long 0x50505 +long_dest: .long 0 + + + start + +subx_b_imm8_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.b #xx:8,Rd ; Subx with carry initially zero. + subx.b #5, r0l ; Immediate 8-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_b_imm8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.b #xx:8,Rd ; Subx with carry initially one. + set_carry_flag + subx.b #4, r0l ; Immediate 8-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa5a0 r0 ; sub result: a5 - (4 + 1) +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - (4 + 1) +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +subx_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b #xx:8,@eRd ; Subx to register indirect + mov #byte_dest, er0 + mov.b #0xa5, @er0 + set_ccr_zero + subx.b #5, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains subress + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb1 + fail +.Lb1: + +subx_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b #xx:8,@eRd- ; Subx to register post-decrement + mov #byte_dest, er0 + mov.b #0xa5, @er0 + set_ccr_zero + subx.b #5, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 ; er0 contains subress minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb2 + fail +.Lb2: +.endif + +subx_b_reg8_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b Rs,Rd ; subx with carry initially zero + mov.b #5, r0h + set_ccr_zero + subx.b r0h, r0l ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0x05a0 r0 ; sub result: a5 - 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b Rs,Rd ; subx with carry initially one + mov.b #4, r0h + set_ccr_zero + set_carry_flag + subx.b r0h, r0l ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0x04a0 r0 ; sub result: a5 - (4 + 1) +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a504a0 er0 ; sub result: a5 - (4 + 1) +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +subx_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b rs8,@eRd ; Subx to register indirect + mov #byte_dest, er0 + mov.b #0xa5, @er0 + mov.b #5, r1l + set_ccr_zero + subx.b r1l, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains subress + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb3 + fail +.Lb3: + +subx_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b rs8,@eRd- ; Subx to register post-decrement + mov #byte_dest, er0 + mov.b #0xa5, @er0 + mov.b #5, r1l + set_ccr_zero + subx.b r1l, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb4 + fail +.Lb4: + +subx_b_rsind_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b @eRs,rd8 ; Subx from reg indirect to reg + mov #byte_src, er0 + set_ccr_zero + subx.b @er0, r1l + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src er0 ; er0 still contains subress + test_h_gr32 0xa5a5a5a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_b_rspostdec_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b @eRs-,rd8 ; Subx to register post-decrement + mov #byte_src, er0 + set_ccr_zero + subx.b @er0-, r1l + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src-1 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a5a5a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_b_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b @eRs,rd8 ; Subx from reg indirect to reg + mov #byte_src, er0 + mov #byte_dest, er1 + mov.b #0xa5, @er1 + set_ccr_zero + subx.b @er0, @er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src er0 ; er0 still contains src subress + test_h_gr32 byte_dest er1 ; er1 still contains dst subress + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb5 + fail +.Lb5: + +subx_b_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + mov #byte_src, er0 + mov #byte_dest, er1 + mov.b #0xa5, @er1 + set_ccr_zero + ;; subx.b @eRs-,@erd- ; Subx post-decrement to post-decrement + subx.b @er0-, @er1- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src-1 er0 ; er0 contains src subress minus one + test_h_gr32 byte_dest-1 er1 ; er1 contains dst subress minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb6 + fail +.Lb6: + +subx_w_imm16_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.w #xx:16,Rd ; Subx with carry initially zero. + subx.w #0x505, r0 ; Immediate 16-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa0a0 r0 ; sub result: 0xa5a5 + 0x505 + test_h_gr32 0xa5a5a0a0 er0 ; sub result: 0xa5a5 + 0x505 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_imm16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.w #xx:16,Rd ; Subx with carry initially one. + set_carry_flag + subx.w #0x504, r0 ; Immediate 16-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa0a0 r0 ; sub result: 0xa5a5 + 0x505 + 1 + test_h_gr32 0xa5a5a0a0 er0 ; sub result: 0xa5a5 + 0x505 + 1 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_imm16_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w #xx:16,@eRd ; Subx to register indirect + mov #word_dest, er0 + mov.w #0xa5a5, @er0 + set_ccr_zero + subx.w #0x505, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_dest er0 ; er0 still contains subress + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw1 + fail +.Lw1: + +subx_w_imm16_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w #xx:16,@eRd- ; Subx to register post-decrement + mov #word_dest, er0 + mov.w #0xa5a5, @er0 + set_ccr_zero + subx.w #0x505, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 ; er0 contains subress minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw2 + fail +.Lw2: + +subx_w_reg16_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w Rs,Rd ; subx with carry initially zero + mov.w #0x505, e0 + set_ccr_zero + subx.w e0, r0 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x0505a0a0 er0 ; sub result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w Rs,Rd ; subx with carry initially one + mov.w #0x504, e0 + set_ccr_zero + set_carry_flag + subx.w e0, r0 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x0504a0a0 er0 ; sub result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_reg16_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w rs8,@eRd ; Subx to register indirect + mov #word_dest, er0 + mov.w #0xa5a5, @er0 + mov.w #0x505, r1 + set_ccr_zero + subx.w r1, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_dest er0 ; er0 still contains subress + test_h_gr32 0xa5a50505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw3 + fail +.Lw3: + +subx_w_reg16_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w rs8,@eRd- ; Subx to register post-decrement + mov #word_dest, er0 + mov.w #0xa5a5, @er0 + mov.w #0x505, r1 + set_ccr_zero + subx.w r1, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a50505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw4 + fail +.Lw4: + +subx_w_rsind_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w @eRs,rd8 ; Subx from reg indirect to reg + mov #word_src, er0 + set_ccr_zero + subx.w @er0, r1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src er0 ; er0 still contains subress + test_h_gr32 0xa5a5a0a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_rspostdec_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w @eRs-,rd8 ; Subx to register post-decrement + mov #word_src, er0 + set_ccr_zero + subx.w @er0-, r1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src-2 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a5a0a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w @eRs,rd8 ; Subx from reg indirect to reg + mov #word_src, er0 + mov #word_dest, er1 + mov.w #0xa5a5, @er1 + set_ccr_zero + subx.w @er0, @er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src er0 ; er0 still contains src subress + test_h_gr32 word_dest er1 ; er1 still contains dst subress + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw5 + fail +.Lw5: + +subx_w_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w @eRs-,rd8 ; Subx to register post-decrement + mov #word_src, er0 + mov #word_dest, er1 + mov.w #0xa5a5, @er1 + set_ccr_zero + subx.w @er0-, @er1- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src-2 er0 ; er0 contains src subress minus one + test_h_gr32 word_dest-2 er1 ; er1 contains dst subress minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw6 + fail +.Lw6: + +subx_l_imm32_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.l #xx:32,Rd ; Subx with carry initially zero. + subx.l #0x50505, er0 ; Immediate 32-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0xa5a0a0a0 er0 ; sub result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_imm32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.l #xx:32,Rd ; Subx with carry initially one. + set_carry_flag + subx.l #0x50504, er0 ; Immediate 32-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0xa5a0a0a0 er0 ; sub result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_imm32_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l #xx:32,@eRd ; Subx to register indirect + mov #long_dest, er0 + mov.l #0xa5a5a5a5, @er0 + set_ccr_zero + subx.l #0x50505, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_dest er0 ; er0 still contains subress + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll1 + fail +.Ll1: + +subx_l_imm32_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l #xx:32,@eRd- ; Subx to register post-decrement + mov #long_dest, er0 + mov.l #0xa5a5a5a5, @er0 + set_ccr_zero + subx.l #0x50505, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 ; er0 contains subress minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll2 + fail +.Ll2: + +subx_l_reg32_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l Rs,Rd ; subx with carry initially zero + mov.l #0x50505, er0 + set_ccr_zero + subx.l er0, er1 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x50505 er0 ; sub load + test_h_gr32 0xa5a0a0a0 er1 ; sub result: + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l Rs,Rd ; subx with carry initially one + mov.l #0x50504, er0 + set_ccr_zero + set_carry_flag + subx.l er0, er1 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x50504 er0 ; sub result: + test_h_gr32 0xa5a0a0a0 er1 ; sub result: + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_reg32_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l rs8,@eRd ; Subx to register indirect + mov #long_dest, er0 + mov.l er1, @er0 + mov.l #0x50505, er1 + set_ccr_zero + subx.l er1, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_dest er0 ; er0 still contains subress + test_h_gr32 0x50505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll3 + fail +.Ll3: + +subx_l_reg32_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l rs8,@eRd- ; Subx to register post-decrement + mov #long_dest, er0 + mov.l er1, @er0 + mov.l #0x50505, er1 + set_ccr_zero + subx.l er1, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 ; er0 contains subress minus one + test_h_gr32 0x50505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll4 + fail +.Ll4: + +subx_l_rsind_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l @eRs,rd8 ; Subx from reg indirect to reg + mov #long_src, er0 + set_ccr_zero + subx.l @er0, er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src er0 ; er0 still contains subress + test_h_gr32 0xa5a0a0a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_rspostdec_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l @eRs-,rd8 ; Subx to register post-decrement + mov #long_src, er0 + set_ccr_zero + subx.l @er0-, er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src-4 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a0a0a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l @eRs,rd8 ; Subx from reg indirect to reg + mov #long_src, er0 + mov #long_dest, er1 + mov.l er2, @er1 + set_ccr_zero + subx.l @er0, @er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src er0 ; er0 still contains src subress + test_h_gr32 long_dest er1 ; er1 still contains dst subress + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll5 + fail +.Ll5: + +subx_l_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l @eRs-,rd8 ; Subx to register post-decrement + mov #long_src, er0 + mov #long_dest, er1 + mov.l er2, @er1 + set_ccr_zero + subx.l @er0-, @er1- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src-4 er0 ; er0 contains src subress minus one + test_h_gr32 long_dest-4 er1 ; er1 contains dst subress minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll6 + fail +.Ll6: +.endif + pass + + exit 0 diff --git a/sim/testsuite/h8300/tas.s b/sim/testsuite/h8300/tas.s new file mode 100644 index 0000000..60bea92 --- /dev/null +++ b/sim/testsuite/h8300/tas.s @@ -0,0 +1,80 @@ +# Hitachi H8 testcase 'tas' +# mach(): h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_dst: .byte 0 + + start + +tas_ind: ; test and set instruction + set_grs_a5a5 + mov #byte_dst, er4 + set_ccr_zero + ;; tas @erd + tas @er4 ; should set zero flag + test_carry_clear + test_neg_clear + test_ovf_clear + test_zero_set + + tas @er4 ; should clear zero, set neg + test_carry_clear + test_neg_set + test_ovf_clear + test_zero_clear + + test_gr_a5a5 0 ; general regs have not been modified + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 byte_dst, er4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + mov.b @byte_dst, r0l ; test variable has MSB set? + test_h_gr8 0x80 r0l + +.if (sim_cpu == h8sx) ; h8sx can use any register for tas +tas_h8sx: ; test and set instruction + mov.b #0, @byte_dst + set_grs_a5a5 + mov #byte_dst, er3 + set_ccr_zero + ;; tas @erd + tas @er3 ; should set zero flag + test_carry_clear + test_neg_clear + test_ovf_clear + test_zero_set + + tas @er3 ; should clear zero, set neg + test_carry_clear + test_neg_set + test_ovf_clear + test_zero_clear + + test_gr_a5a5 0 ; general regs have not been modified + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 byte_dst, er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + mov.b @byte_dst, r0l ; test variable has MSB set? + test_h_gr8 0x80 r0l +.endif ; h8sx + + pass + exit 0 diff --git a/sim/testsuite/h8300/testutils.inc b/sim/testsuite/h8300/testutils.inc new file mode 100644 index 0000000..9c2c27a --- /dev/null +++ b/sim/testsuite/h8300/testutils.inc @@ -0,0 +1,351 @@ +# Support macros for the Hitachi H8 assembly test cases. + +; Set up a minimal machine state + .macro start + .equ h8300, 0 + .equ h8300h, 1 + .equ h8300s, 2 + .equ h8sx, 3 + .if (sim_cpu == h8300s) + .h8300s + .else + .if (sim_cpu == h8300h) + .h8300h + .else + .if (sim_cpu == h8sx) + .h8300sx + .endif + .endif + .endif + + .text + .align 2 + .global _start +_start: + jmp _main + + .data + .align 2 + .global pass_str + .global fail_str + .global ok_str + .global pass_loc + .global fail_loc + .global ok_loc +pass_str: + .ascii "pass\n" +fail_str: + .ascii "fail\n" +ok_str: + .ascii "ok\n" +pass_loc16: + .word pass_str +pass_loc32: + .long pass_str +fail_loc16: + .word fail_str +fail_loc32: + .long fail_str +ok_loc16: + .word ok_str +ok_loc32: + .long ok_str + .text + + .global _write_and_exit +_write_and_exit: +;ssize_t write(int fd, const void *buf, size_t count); +;Integer arguments have to be zero extended. +.if (sim_cpu) +#if __INT_MAX__ == 32767 + extu.l er0 +#endif +.endif + jsr @@0xc7 + mov #0, r0 + jmp _exit + + .global _exit +_exit: + mov.b r0l, r0h + mov.w #0xdead, r1 + mov.w #0xbeef, r2 + sleep + + .global _main +_main: + .endm + + +; Exit with an exit code + .macro exit code + mov.w #\code, r0 + jmp _exit + .endm + +; Output "pass\n" + .macro pass + mov.w #0, r0 ; fd == stdout +.if (sim_cpu == h8300) + mov.w #pass_str, r1 ; buf == "pass\n" + mov.w #5, r2 ; len == 5 +.else + mov.l #pass_str, er1 ; buf == "pass\n" + mov.l #5, er2 ; len == 5 +.endif + jmp _write_and_exit + .endm + +; Output "fail\n" + .macro fail + mov.w #0, r0 ; fd == stdout +.if (sim_cpu == h8300) + mov.w #fail_str, r1 ; buf == "fail\n" + mov.w #5, r2 ; len == 5 +.else + mov.l #fail_str, er1 ; buf == "fail\n" + mov.l #5, er2 ; len == 5 +.endif + jmp _write_and_exit + .endm + + +; Load an 8-bit immediate value into a general register +; (reg must be r0l - r7l or r0h - r7h) + .macro mvi_h_gr8 val reg + mov.b #\val, \reg + .endm + +; Load a 16-bit immediate value into a general register +; (reg must be r0 - r7) + .macro mvi_h_gr16 val reg + mov.w #\val, \reg + .endm + +; Load a 32-bit immediate value into a general register +; (reg must be er0 - er7) + .macro mvi_h_gr32 val reg + mov.l #\val, \reg + .endm + +; Test the value of an 8-bit immediate against a general register +; (reg must be r0l - r7l or r0h - r7h) + .macro test_h_gr8 val reg + cmp.b #\val, \reg + beq .Ltest_gr8\@ + fail +.Ltest_gr8\@: + .endm + +; Test the value of a 16-bit immediate against a general register +; (reg must be r0 - r7) + .macro test_h_gr16 val reg h=h l=l + .if (sim_cpu == h8300) + test_h_gr8 (\val >> 8) \reg\h + test_h_gr8 (\val & 0xff) \reg\l + .else + cmp.w #\val, \reg + beq .Ltest_gr16\@ + fail +.Ltest_gr16\@: + .endif + .endm + +; Test the value of a 32-bit immediate against a general register +; (reg must be er0 - er7) + .macro test_h_gr32 val reg + cmp.l #\val, \reg + beq .Ltest_gr32\@ + fail +.Ltest_gr32\@: + .endm + +; Set a general register to the fixed pattern 'a5a5a5a5' + .macro set_gr_a5a5 reg + .if (sim_cpu == 0) + ; h8300 + mov.w #0xa5a5, r\reg + .else + mov.l #0xa5a5a5a5, er\reg + .endif + .endm + +; Set all general registers to the fixed pattern 'a5a5a5a5' + .macro set_grs_a5a5 + .if (sim_cpu == 0) + ; h8300 + mov.w #0xa5a5, r0 + mov.w #0xa5a5, r1 + mov.w #0xa5a5, r2 + mov.w #0xa5a5, r3 + mov.w #0xa5a5, r4 + mov.w #0xa5a5, r5 + mov.w #0xa5a5, r6 + mov.w #0xa5a5, r7 + .else + mov.l #0xa5a5a5a5, er0 + mov.l #0xa5a5a5a5, er1 + mov.l #0xa5a5a5a5, er2 + mov.l #0xa5a5a5a5, er3 + mov.l #0xa5a5a5a5, er4 + mov.l #0xa5a5a5a5, er5 + mov.l #0xa5a5a5a5, er6 + mov.l #0xa5a5a5a5, er7 + .endif + .endm + +; Test that a general register contains the fixed pattern 'a5a5a5a5' + .macro test_gr_a5a5 reg + .if (sim_cpu == 0) + ; h8300 + test_h_gr16 0xa5a5 r\reg + .else + test_h_gr32 0xa5a5a5a5 er\reg + .endif + .endm + +; Test that all general regs contain the fixed pattern 'a5a5a5a5' + .macro test_grs_a5a5 + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + .endm + +; Set condition code register to an explicit value + .macro set_ccr val + ldc #\val, ccr + .endm + +; Set all condition code flags to zero + .macro set_ccr_zero + ldc #0, ccr + .endm + +; Set carry flag true + .macro set_carry_flag + orc #1, ccr + .endm + +; Clear carry flag + .macro clear_carry_flag + andc 0xfe, ccr + .endm + +; Set zero flag true + .macro set_zero_flag + orc #4, ccr + .endm + +; Clear zero flag + .macro clear_zero_flag + andc 0xfb, ccr + .endm + +; Set neg flag true + .macro set_neg_flag + orc #8, ccr + .endm + +; Clear neg flag + .macro clear_neg_flag + andc 0xf7, ccr + .endm + +; Test that carry flag is clear + .macro test_carry_clear + bcc .Lcc\@ + fail ; carry flag not clear +.Lcc\@: + .endm + +; Test that carry flag is set + .macro test_carry_set + bcs .Lcs\@ + fail ; carry flag not clear +.Lcs\@: + .endm + +; Test that overflow flag is clear + .macro test_ovf_clear + bvc .Lvc\@ + fail ; overflow flag not clear +.Lvc\@: + .endm + +; Test that overflow flag is set + .macro test_ovf_set + bvs .Lvs\@ + fail ; overflow flag not clear +.Lvs\@: + .endm + +; Test that zero flag is clear + .macro test_zero_clear + bne .Lne\@ + fail ; zero flag not clear +.Lne\@: + .endm + +; Test that zero flag is set + .macro test_zero_set + beq .Leq\@ + fail ; zero flag not clear +.Leq\@: + .endm + +; Test that neg flag is clear + .macro test_neg_clear + bpl .Lneg\@ + fail ; negative flag not clear +.Lneg\@: + .endm + +; Test that neg flag is set + .macro test_neg_set + bmi .Lneg\@ + fail ; negative flag not clear +.Lneg\@: + .endm + +; Test ccr against an explicit value + .macro test_ccr val + .data +tccr\@: .byte 0 + .text + mov.b r0l, @tccr\@ + stc ccr, r0l + cmp.b #\val, r0l + bne .Ltcc\@ + fail +.Ltcc\@: + mov.b @tccr\@, r0l + .endm + +; Test that all (accessable) condition codes are clear + .macro test_cc_clear + test_carry_clear + test_ovf_clear + test_zero_clear + test_neg_clear + ; leaves H, I, U, and UI untested + .endm + +; Compare memory, fail if not equal (h8sx only, len > 0). + .macro memcmp src dst len + mov.l #\src, er5 + mov.l #\dst, er6 + mov.l #\len, er4 +.Lmemcmp_\@: + cmp.b @er5+, @er6+ + beq .Lmemcmp2_\@ + fail +.Lmemcmp2_\@: + dec.l #1, er4 + bne .Lmemcmp_\@ + .endm + diff --git a/sim/testsuite/h8300/xorb.s b/sim/testsuite/h8300/xorb.s new file mode 100644 index 0000000..337c396 --- /dev/null +++ b/sim/testsuite/h8300/xorb.s @@ -0,0 +1,378 @@ +# Hitachi H8 testcase 'xor.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # xor.b #xx:8, rd ; d rd xxxxxxxx + # xor.b #xx:8, @erd ; 7 d rd ???? d ???? xxxxxxxx + # xor.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx + # xor.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx + # xor.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx + # xor.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx + # xor.b rs, rd ; 1 5 rs rd + # xor.b reg8, @erd ; 7 d rd ???? 1 5 rs ???? + # xor.b reg8, @erd+ ; 0 1 7 9 8 rd 5 rs + # xor.b reg8, @erd- ; 0 1 7 9 a rd 5 rs + # xor.b reg8, @+erd ; 0 1 7 9 9 rd 5 rs + # xor.b reg8, @-erd ; 0 1 7 9 b rd 5 rs + # + # xorc #xx:8, ccr ; + # xorc #xx:8, exr ; + + # Coming soon: + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0xa5 +post_byte: .byte 0 + + start + +xor_b_imm8_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.b #xx:8,Rd + xor.b #0xff, r0l ; Immediate 8-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa55a r0 ; xor result: a5 ^ ff +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a55a er0 ; xor result: a5 ^ ff +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +xor_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b #xx:8,@eRd + mov #byte_dest, er0 + xor.b #0xff:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xd0ff + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the xor to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x5a, r0l + beq .L1 + fail +.L1: + +xor_b_imm8_postinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b #xx:8,@eRd+ + mov #byte_dest, er0 + xor.b #0xff:8, @er0+ ; Immediate 8-bit src, reg indirect dst +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xd0ff + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the xor to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa5, r0l + beq .L2 + fail +.L2: + +xor_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b #xx:8,@eRd- + mov #byte_dest, er0 + xor.b #0xff:8, @er0- ; Immediate 8-bit src, reg indirect dst +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xd0ff + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the xor to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x5a, r0l + beq .L3 + fail +.L3: + + +.endif + +xor_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.b Rs,Rd + mov.b #0xff, r0h + xor.b r0h, r0l ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xff5a r0 ; xor result: a5 ^ ff +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5ff5a er0 ; xor result: a5 ^ ff +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +xor_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b rs8,@eRd ; xor reg8 to register indirect + mov #byte_dest, er0 + mov #0xff, r1l + xor.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1590 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa5, r0l + beq .L4 + fail +.L4: + +xor_b_reg8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b rs8,@eRd+ ; xor reg8 to register post-increment + mov #byte_dest, er0 + mov #0xff, r1l + xor.b r1l, @er0+ ; reg8 src, reg post-increment dest +;;; .word 0x0179 +;;; .word 0x8059 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x5a, r0l + beq .L5 + fail +.L5: + +xor_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b rs8,@eRd- ; xor reg8 to register post-decrement + mov #byte_dest, er0 + mov #0xff, r1l + xor.b r1l, @er0- ; reg8 src, reg indirect dest +;;; .word 0x0179 +;;; .word 0xa059 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa5, r0l + beq .L6 + fail +.L6: + +.endif ; h8sx + +xorc_imm8_ccr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xorc #xx:8,ccr + + test_neg_clear + xorc #0x8, ccr ; Immediate 8-bit operand (neg flag) + test_neg_set + xorc #0x8, ccr + test_neg_clear + + test_zero_clear + xorc #0x4, ccr ; Immediate 8-bit operand (zero flag) + test_zero_set + xorc #0x4, ccr + test_zero_clear + + test_ovf_clear + xorc #0x2, ccr ; Immediate 8-bit operand (overflow flag) + test_ovf_set + xorc #0x2, ccr + test_ovf_clear + + test_carry_clear + xorc #0x1, ccr ; Immediate 8-bit operand (carry flag) + test_carry_set + xorc #0x1, ccr + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +xorc_imm8_exr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ldc #0, exr + stc exr, r0l + test_h_gr8 0, r0l + + set_ccr_zero + ;; xorc #xx:8,exr + + xorc #0x80, exr + test_cc_clear + stc exr, r0l + test_h_gr8 0x80, r0l + xorc #0x80, exr + stc exr, r0l + test_h_gr8 0, r0l + + xorc #0x4, exr + stc exr, r0l + test_h_gr8 4, r0l + xorc #0x4, exr + stc exr, r0l + test_h_gr8 0, r0l + + xorc #0x2, exr ; Immediate 8-bit operand (overflow flag) + stc exr, r0l + test_h_gr8 2, r0l + xorc #0x2, exr + stc exr, r0l + test_h_gr8 0, r0l + + xorc #0x1, exr ; Immediate 8-bit operand (carry flag) + stc exr, r0l + test_h_gr8 1, r0l + xorc #0x1, exr + stc exr, r0l + test_h_gr8 0, r0l + + test_h_gr32 0xa5a5a500 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; not h8300 or h8300h + + pass + + exit 0 diff --git a/sim/testsuite/h8300/xorl.s b/sim/testsuite/h8300/xorl.s new file mode 100644 index 0000000..67b2e49 --- /dev/null +++ b/sim/testsuite/h8300/xorl.s @@ -0,0 +1,77 @@ +# Hitachi H8 testcase 'xor.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. +xor_l_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.l #xx:16,Rd + xor.l #0xffff:16, er0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5a5a5 | ffff + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +xor_l_imm32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.l #xx:32,Rd + xor.l #0xffffffff, er0 ; Immediate 32-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +xor_l_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.l Rs,Rd + mov.l #0xffffffff, er1 + xor.l er1, er0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff + test_h_gr32 0xffffffff er1 ; Make sure er1 is unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/h8300/xorw.s b/sim/testsuite/h8300/xorw.s new file mode 100644 index 0000000..3c5e5b8 --- /dev/null +++ b/sim/testsuite/h8300/xorw.s @@ -0,0 +1,61 @@ +# Hitachi H8 testcase 'xor.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +xor_w_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.w #xx:16,Rd + xor.w #0xffff, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +xor_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.w Rs,Rd + mov.w #0xffff, r1 + xor.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff + test_h_gr16 0xffff r1 ; Make sure r1 is unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff + test_h_gr32 0xa5a5ffff er1 ; Make sure er1 is unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/iq2000/ChangeLog b/sim/testsuite/iq2000/ChangeLog new file mode 100644 index 0000000..d3f8b9d --- /dev/null +++ b/sim/testsuite/iq2000/ChangeLog @@ -0,0 +1,3 @@ +2015-04-05 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/iq2000/allinsn.exp b/sim/testsuite/iq2000/allinsn.exp new file mode 100644 index 0000000..38eee9b --- /dev/null +++ b/sim/testsuite/iq2000/allinsn.exp @@ -0,0 +1,15 @@ +# iq2000 simulator testsuite + +if [istarget iq2000-*] { + # all machines + set all_machs "iq2000" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/iq2000/pass.s b/sim/testsuite/iq2000/pass.s new file mode 100644 index 0000000..4bb07cb --- /dev/null +++ b/sim/testsuite/iq2000/pass.s @@ -0,0 +1,7 @@ +# check that the sim doesn't die immediately. +# mach: iq2000 + +.include "testutils.inc" + + start + pass diff --git a/sim/testsuite/iq2000/testutils.inc b/sim/testsuite/iq2000/testutils.inc new file mode 100644 index 0000000..0e0dabd --- /dev/null +++ b/sim/testsuite/iq2000/testutils.inc @@ -0,0 +1,53 @@ +# MACRO: exit + .macro exit nr + ori r5, r0, \nr; + # Trap function 1: exit(). + ori r4, r0, 1; + syscall; + .endm + +# MACRO: pass +# Write 'pass' to stdout and quit + .macro pass + # Trap function 5: write(). + ori r4, r0, 5; + # Use stdout. + ori r5, r0, 1; + # Point to the string. + lui r6, %hi(1f); + ori r6, r6, %lo(1f); + # Number of bytes to write. + ori r7, r0, 5; + # Trigger OS trap. + syscall; + exit 0 + .data + 1: .asciz "pass\n" + .endm + +# MACRO: fail +# Write 'fail' to stdout and quit + .macro fail + # Trap function 5: write(). + ori r4, r0, 5; + # Use stdout. + ori r5, r0, 1; + # Point to the string. + lui r6, %hi(1f); + ori r6, r6, %lo(1f); + # Number of bytes to write. + ori r7, r0, 5; + # Trigger OS trap. + syscall; + exit 0 + .data + 1: .asciz "fail\n" + .endm + +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .text +.global _start +_start: + .endm diff --git a/sim/testsuite/lm32/ChangeLog b/sim/testsuite/lm32/ChangeLog new file mode 100644 index 0000000..d3f8b9d --- /dev/null +++ b/sim/testsuite/lm32/ChangeLog @@ -0,0 +1,3 @@ +2015-04-05 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/lm32/allinsn.exp b/sim/testsuite/lm32/allinsn.exp new file mode 100644 index 0000000..6174498 --- /dev/null +++ b/sim/testsuite/lm32/allinsn.exp @@ -0,0 +1,15 @@ +# lm32 simulator testsuite + +if [istarget lm32-*] { + # all machines + set all_machs "lm32" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/lm32/pass.s b/sim/testsuite/lm32/pass.s new file mode 100644 index 0000000..3154b2b --- /dev/null +++ b/sim/testsuite/lm32/pass.s @@ -0,0 +1,7 @@ +# check that the sim doesn't die immediately. +# mach: lm32 + +.include "testutils.inc" + + start + pass diff --git a/sim/testsuite/lm32/testutils.inc b/sim/testsuite/lm32/testutils.inc new file mode 100644 index 0000000..0f62e3a --- /dev/null +++ b/sim/testsuite/lm32/testutils.inc @@ -0,0 +1,59 @@ +# MACRO: exit + .macro exit nr + mvi r1, \nr; + # Trap function 1: exit(). + mvi r8, 1; + scall; + .endm + +# MACRO: pass +# Write 'pass' to stdout and quit + .macro pass + # Trap function 5: write(). + mvi r8, 5; + # Use stdout. + mvi r1, 1; + # Point to the string. + mvhi r2, hi(1f) + ori r2, r2, lo(1f) + # Number of bytes to write. + mvi r3, 5; + # Trigger OS trap. + scall; + exit 0 + .data + 1: .asciz "pass\n" + .endm + +# MACRO: fail +# Write 'fail' to stdout and quit + .macro fail + # Trap function 5: write(). + mvi r8, 5; + # Use stdout. + mvi r1, 1; + # Point to the string. + mvhi r2, hi(1f) + ori r2, r2, lo(1f) + # Number of bytes to write. + mvi r3, 5; + # Trigger OS trap. + scall; + exit 0 + .data + 1: .asciz "fail\n" + .endm + +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .data +.global _fstack +_fstack: + .rept 0x1024 + .byte 00 + .endr + .text +.global _start +_start: + .endm diff --git a/sim/testsuite/m32c/ChangeLog b/sim/testsuite/m32c/ChangeLog new file mode 100644 index 0000000..8437919 --- /dev/null +++ b/sim/testsuite/m32c/ChangeLog @@ -0,0 +1,10 @@ +2015-11-14 Mike Frysinger + + * allinsn.exp: New file. + * fail.s, pass.s: New tests. + * testutils.inc: New test helper logic. + +2015-11-09 Mike Frysinger + + * blinky.s: Moved from ../../../m32c/. + * gloss.s, sample.ld, sample.s, sample2.c: Likewise. diff --git a/sim/testsuite/m32c/allinsn.exp b/sim/testsuite/m32c/allinsn.exp new file mode 100644 index 0000000..fb5ccca --- /dev/null +++ b/sim/testsuite/m32c/allinsn.exp @@ -0,0 +1,16 @@ +# M32C simulator testsuite. +# TODO: Add support for .c tests. + +if [istarget m32c*-*-*] { + # all machines + set all_machs "m32c" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/m32c/blinky.s b/sim/testsuite/m32c/blinky.s new file mode 100644 index 0000000..1dbad97 --- /dev/null +++ b/sim/testsuite/m32c/blinky.s @@ -0,0 +1,34 @@ +;;; blinky.s --- sample program to blink LED's on M32C simulator +;;; +;;; Copyright (C) 2005-2021 Free Software Foundation, Inc. +;;; Contributed by Red Hat, Inc. +;;; +;;; This file is part of the GNU simulators. +;;; +;;; This program is free software; you can redistribute it and/or modify +;;; it under the terms of the GNU General Public License as published by +;;; the Free Software Foundation; either version 3 of the License, or +;;; (at your option) any later version. +;;; +;;; This program is distributed in the hope that it will be useful, +;;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. +;;; +;;; You should have received a copy of the GNU General Public License +;;; along with this program. If not, see . + + .text + + .global _start +_start: + mov.w #0xe1,a0 +top: + sub.w #1,r0 + mov.b r0h,[a0] + + mov.w #1000,r1 +loop: + adjnz.w #-1,r1,loop + + jmp.w top diff --git a/sim/testsuite/m32c/fail.s b/sim/testsuite/m32c/fail.s new file mode 100644 index 0000000..5066bce --- /dev/null +++ b/sim/testsuite/m32c/fail.s @@ -0,0 +1,9 @@ +# check that the sim doesn't die immediately. +# mach: m32c +# ld: -T$srcdir/$subdir/sample.ld +# xerror: + +.include "testutils.inc" + + start + fail diff --git a/sim/testsuite/m32c/gloss.s b/sim/testsuite/m32c/gloss.s new file mode 100644 index 0000000..ce03774 --- /dev/null +++ b/sim/testsuite/m32c/gloss.s @@ -0,0 +1,32 @@ +;;; gloss.s --- system calls for sample2.x +;;; +;;; Copyright (C) 2005-2021 Free Software Foundation, Inc. +;;; Contributed by Red Hat, Inc. +;;; +;;; This file is part of the GNU simulators. +;;; +;;; This program is free software; you can redistribute it and/or modify +;;; it under the terms of the GNU General Public License as published by +;;; the Free Software Foundation; either version 3 of the License, or +;;; (at your option) any later version. +;;; +;;; This program is distributed in the hope that it will be useful, +;;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. +;;; +;;; You should have received a copy of the GNU General Public License +;;; along with this program. If not, see . + +;;; See the 'sample2.x' target in Makefile.in. + .global _exit +_exit: + mov.b #1,r0l + ste.b r0l,0xe0000 + rts + + .global _foo +_foo: + mov.b #2,r0l + ste.b r0l,0xe0000 + rts diff --git a/sim/testsuite/m32c/pass.s b/sim/testsuite/m32c/pass.s new file mode 100644 index 0000000..9f39ac0 --- /dev/null +++ b/sim/testsuite/m32c/pass.s @@ -0,0 +1,8 @@ +# check that the sim doesn't die immediately. +# mach: m32c +# ld: -T$srcdir/$subdir/sample.ld + +.include "testutils.inc" + + start + pass diff --git a/sim/testsuite/m32c/sample.ld b/sim/testsuite/m32c/sample.ld new file mode 100644 index 0000000..112012a --- /dev/null +++ b/sim/testsuite/m32c/sample.ld @@ -0,0 +1,41 @@ +/* sample2.ld --- linker script for sample2.x + +Copyright (C) 2005-2021 Free Software Foundation, Inc. +Contributed by Red Hat, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +/* See the 'sample2.x' target in Makefile.in. */ + +ENTRY(_start) + +MEMORY { + RAM1 (w) : ORIGIN = 0xc800, LENGTH = 0x0200 + RAM2 (w) : ORIGIN = 0xca56, LENGTH = 0x1000 + ROM (w) : ORIGIN = 0x30000, LENGTH = 0x1000 +} + +SECTIONS { + .data : { + *(.data*) + } > RAM1 + .text : { + *(.text*) + } > RAM2 + .fardata : { + *(.fardata*) + } > ROM +} diff --git a/sim/testsuite/m32c/sample.s b/sim/testsuite/m32c/sample.s new file mode 100644 index 0000000..14b0548 --- /dev/null +++ b/sim/testsuite/m32c/sample.s @@ -0,0 +1,27 @@ +;;; sample.s --- simple test program for M32C simulator +;;; +;;; Copyright (C) 2005-2021 Free Software Foundation, Inc. +;;; Contributed by Red Hat, Inc. +;;; +;;; This file is part of the GNU simulators. +;;; +;;; This program is free software; you can redistribute it and/or modify +;;; it under the terms of the GNU General Public License as published by +;;; the Free Software Foundation; either version 3 of the License, or +;;; (at your option) any later version. +;;; +;;; This program is distributed in the hope that it will be useful, +;;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. +;;; +;;; You should have received a copy of the GNU General Public License +;;; along with this program. If not, see . + + .text + + .global _start +_start: + mov.w #0x1234,r1 + mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3 + brk diff --git a/sim/testsuite/m32c/sample2.c b/sim/testsuite/m32c/sample2.c new file mode 100644 index 0000000..3b8f055 --- /dev/null +++ b/sim/testsuite/m32c/sample2.c @@ -0,0 +1,29 @@ +/* sample2.c --- main source for sample2.x test program for M32C simulator + +Copyright (C) 2005-2021 Free Software Foundation, Inc. +Contributed by Red Hat, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +/* See the 'sample2.x' target in Makefile.in. */ +void exit (int); + +void +start (void) +{ + foo (1, 2, 3, 4); + exit (5); +} diff --git a/sim/testsuite/m32c/testutils.inc b/sim/testsuite/m32c/testutils.inc new file mode 100644 index 0000000..fa6f5a9 --- /dev/null +++ b/sim/testsuite/m32c/testutils.inc @@ -0,0 +1,53 @@ +# MACRO: exit + .macro exit nr + mov.w \nr, r1; + # Trap function 1: exit(). + mov.b #1, r0l; + ste.b r0l, 0x400; + .endm + +# MACRO: pass +# Write 'pass' to stdout and quit + .macro pass + # Use stdout. + mov.w #1, r1; + # Point to the string. + mov.w #1f, r2; + # Number of bytes to write; push onto stack. + push.w #5; + # Adjust as the sim expects 3 byte offset. (!?) + add.w #-3, sp; + # Trap function 5: write(). + mov.b #5, r0l; + ste.b r0l, 0x400; + exit #0 + .data + 1: .asciz "pass\n" + .endm + +# MACRO: fail +# Write 'fail' to stdout and quit + .macro fail + # Use stdout. + mov.w #1, r1; + # Point to the string. + mov.w #1f, r2; + # Number of bytes to write; push onto stack. + push.w #5; + # Adjust as the sim expects 3 byte offset. (!?) + add.w #-3, sp; + # Trap function 5: write(). + mov.b #5, r0l; + ste.b r0l, 0x400; + exit #1 + .data + 1: .asciz "fail\n" + .endm + +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .text +.global _start +_start: + .endm diff --git a/sim/testsuite/m32r/ChangeLog b/sim/testsuite/m32r/ChangeLog new file mode 100644 index 0000000..3e6dbf7 --- /dev/null +++ b/sim/testsuite/m32r/ChangeLog @@ -0,0 +1,126 @@ +2021-01-15 Mike Frysinger + + * exit47.ms: New testcase from ../../m32r-elf/. + +1999-04-21 Doug Evans + + * nop.cgs: Add missing nop insn. + +1999-01-05 Doug Evans + + * allinsn.exp: Set all_machs. + * misc.exp: Likewise. + +1998-12-14 Doug Evans + + * hello.ms: Add trailing \n to expected output. + * hw-trap.ms: Ditto. + + * trap.cgs: Properly align trap2_handler. + + * uread16.ms: New testcase. + * uread32.ms: New testcase. + * uwrite16.ms: New testcase. + * uwrite32.ms: New testcase. + +Tue Sep 15 14:56:22 1998 Doug Evans + + * testutils.inc (test_h_gr): Use mvaddr_h_gr. + * rte.cgs: Test bbpc,bbpsw. + * trap.cgs: Test bbpc,bbpsw. + +Wed Jul 1 15:57:54 1998 Doug Evans + + * hw-trap.ms: New testcase. + +Wed Jun 10 10:53:20 1998 Doug Evans + + * addx.cgs: Add another test. + * jmp.cgs: Add another test. + +Mon Jun 8 16:08:27 1998 Doug Evans + + * trap.cgs: Test trap 2. + +Tue Apr 21 10:49:03 1998 Doug Evans + + * addx.cgs: Test (-1)+(-1)+1. + +Fri Apr 17 16:00:52 1998 Doug Evans + + * mv[ft]achi.cgs: Fix expected result + (sign extension of top 8 bits). + +Fri Feb 20 11:00:02 1998 Nick Clifton + + * unlock.cgs: Fixed test. + * mvfc.cgs: Fixed test. + * remu.cgs: Fixed test. + * bnc24.cgs: Test long BNC instruction. + * bnc8.cgs: Test short BNC instruction. + * ld-plus.cgs: Test LD instruction. + * macwhi.cgs: Test MACWHI instruction. + * macwlo.cgs: Test MACWLO instruction. + * mulwhi.cgs: Test MULWHI instruction. + * mulwlo.cgs: Test MULWLO instruction. + * mvfachi.cgs: Test MVFACHI instruction. + * mvfaclo.cgs: Test MVFACLO instruction. + * mvtaclo.cgs: Test MVTACLO instruction. + * addv.cgs: Test ADDV instruction. + * addv3.cgs: Test ADDV3 instruction. + * addx.cgs: Test ADDX instruction. + * lock.cgs: Test LOCK instruction. + * neg.cgs: Test NEG instruction. + * not.cgs: Test NOT instruction. + * unlock.cgs: Test UNLOCK instruction. + +Thu Feb 19 11:15:45 1998 Nick Clifton + + * testutils.inc (mvaddr_h_gr): new macro to load an + address into a general register. + + * or3.cgs: Test OR3 instruction. + * rach.cgs: Test RACH instruction. + * rem.cgs: Test REM instruction. + * sub.cgs: Test SUB instruction. + * mv.cgs: Test MV instruction. + * mul.cgs: Test MUL instruction. + * bl24.cgs: Test long BL instruction. + * bl8.cgs: Test short BL instruction. + * blez.cgs: Test BLEZ instruction. + * bltz.cgs: Test BLTZ instruction. + * bne.cgs: Test BNE instruction. + * bnez.cgs: Test BNEZ instruction. + * bra24.cgs: Test long BRA instruction. + * bra8.cgs: Test short BRA instruction. + * jl.cgs: Test JL instruction. + * or.cgs: Test OR instruction. + * jmp.cgs: Test JMP instruction. + * and.cgs: Test AND instruction. + * and3.cgs: Test AND3 instruction. + * beq.cgs: Test BEQ instruction. + * beqz.cgs: Test BEQZ instruction. + * bgez.cgs: Test BGEZ instruction. + * bgtz.cgs: Test BGTZ instruction. + * cmp.cgs: Test CMP instruction. + * cmpi.cgs: Test CMPI instruction. + * cmpu.cgs: Test CMPU instruction. + * cmpui.cgs: Test CMPUI instruction. + * div.cgs: Test DIV instruction. + * divu.cgs: Test DIVU instruction. + * cmpeq.cgs: Test CMPEQ instruction. + * sll.cgs: Test SLL instruction. + * sll3.cgs: Test SLL3 instruction. + * slli.cgs: Test SLLI instruction. + * sra.cgs: Test SRA instruction. + * sra3.cgs: Test SRA3 instruction. + * srai.cgs: Test SRAI instruction. + * srl.cgs: Test SRL instruction. + * srl3.cgs: Test SRL3 instruction. + * srli.cgs: Test SRLI instruction. + * xor3.cgs: Test XOR3 instruction. + * xor.cgs: Test XOR instruction. + +Tue Feb 17 12:46:05 1998 Doug Evans + + * *: m32r dejagnu simulator testsuite. diff --git a/sim/testsuite/m32r/add.cgs b/sim/testsuite/m32r/add.cgs new file mode 100644 index 0000000..8ed2b3a --- /dev/null +++ b/sim/testsuite/m32r/add.cgs @@ -0,0 +1,16 @@ +# m32r testcase for add $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global add +add: + + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + add r4, r5 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/m32r/add3.cgs b/sim/testsuite/m32r/add3.cgs new file mode 100644 index 0000000..d1cc848 --- /dev/null +++ b/sim/testsuite/m32r/add3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for add3 $dr,$sr,#$slo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global add3 +add3: + + mvi_h_gr r5, 1 + add3 r4, r5, 2 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/m32r/addi.cgs b/sim/testsuite/m32r/addi.cgs new file mode 100644 index 0000000..1448d0d --- /dev/null +++ b/sim/testsuite/m32r/addi.cgs @@ -0,0 +1,16 @@ +# m32r testcase for addi $dr,#$simm8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addi +addi: + + mvi_h_gr r5, 1 + addi r5, 2 + test_h_gr r5, 3 + + pass + diff --git a/sim/testsuite/m32r/addv.cgs b/sim/testsuite/m32r/addv.cgs new file mode 100644 index 0000000..704be83 --- /dev/null +++ b/sim/testsuite/m32r/addv.cgs @@ -0,0 +1,21 @@ +# m32r testcase for addv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addv +addv: + mvi_h_condbit 0 + mvi_h_gr r4, 0x80000000 + mvi_h_gr r5, 0x80000000 + + addv r4, r5 + + bnc not_ok + test_h_gr r4, 0 + + pass +not_ok: + fail diff --git a/sim/testsuite/m32r/addv3.cgs b/sim/testsuite/m32r/addv3.cgs new file mode 100644 index 0000000..a8c0a10 --- /dev/null +++ b/sim/testsuite/m32r/addv3.cgs @@ -0,0 +1,28 @@ +# m32r testcase for addv3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addv3 +addv3: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + mvi_h_gr r5, 1 + + addv3 r4, r5, #2 + + bc not_ok + + test_h_gr r4, 3 + + mvi_h_gr r5, 0x7fff8001 + + addv3 r4, r5, #0x7fff + + bnc not_ok + + pass +not_ok: + fail diff --git a/sim/testsuite/m32r/addx.cgs b/sim/testsuite/m32r/addx.cgs new file mode 100644 index 0000000..630e3db --- /dev/null +++ b/sim/testsuite/m32r/addx.cgs @@ -0,0 +1,42 @@ +# m32r testcase for addx $dr,$sr +# mach(): m32r m32rx +# timeout(): 42 + +# timeout is set to test it + + .include "testutils.inc" + + start + + .global addx +addx: + mvi_h_condbit 1 + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + addx r4, r5 + bc not_ok + test_h_gr r4, 4 + + mvi_h_gr r4, 0xfffffffe + addx r4, r5 + bnc not_ok + test_h_gr r4, 0 + + mvi_h_gr r4, -1 + mvi_h_gr r5, -1 + mvi_h_condbit 1 + addx r4,r5 + bnc not_ok + test_h_gr r4, -1 + + mvi_h_gr r4,-1 + mvi_h_gr r5,0x7fffffff + mvi_h_condbit 1 + addx r5,r4 + bnc not_ok + test_h_gr r5,0x7fffffff + + pass + +not_ok: + fail diff --git a/sim/testsuite/m32r/allinsn.exp b/sim/testsuite/m32r/allinsn.exp new file mode 100644 index 0000000..8eed80f --- /dev/null +++ b/sim/testsuite/m32r/allinsn.exp @@ -0,0 +1,21 @@ +# M32R simulator testsuite. + +if [istarget m32r*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "m32r" + + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/m32r/and.cgs b/sim/testsuite/m32r/and.cgs new file mode 100644 index 0000000..1c26885 --- /dev/null +++ b/sim/testsuite/m32r/and.cgs @@ -0,0 +1,17 @@ +# m32r testcase for and $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global and +and: + mvi_h_gr r4, 3 + mvi_h_gr r5, 6 + + and r4, r5 + + test_h_gr r4, 2 + + pass diff --git a/sim/testsuite/m32r/and3.cgs b/sim/testsuite/m32r/and3.cgs new file mode 100644 index 0000000..395de30 --- /dev/null +++ b/sim/testsuite/m32r/and3.cgs @@ -0,0 +1,17 @@ +# m32r testcase for and3 $dr,$sr,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global and3 +and3: + mvi_h_gr r4, 0 + mvi_h_gr r5, 6 + + and3 r4, r5, #3 + + test_h_gr r4, 2 + + pass diff --git a/sim/testsuite/m32r/bc24.cgs b/sim/testsuite/m32r/bc24.cgs new file mode 100644 index 0000000..6bb4333 --- /dev/null +++ b/sim/testsuite/m32r/bc24.cgs @@ -0,0 +1,24 @@ +# m32r testcase for bc $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bc24 +bc24: + + mvi_h_condbit 0 + bc.l test0fail + bra test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bc.l test1pass + fail +test1pass: + + pass + diff --git a/sim/testsuite/m32r/bc8.cgs b/sim/testsuite/m32r/bc8.cgs new file mode 100644 index 0000000..ceb622c --- /dev/null +++ b/sim/testsuite/m32r/bc8.cgs @@ -0,0 +1,23 @@ +# m32r testcase for bc $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bc8 +bc8: + + mvi_h_condbit 0 + bc.s test0fail + bra test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bc.s test1pass + fail +test1pass: + + pass diff --git a/sim/testsuite/m32r/beq.cgs b/sim/testsuite/m32r/beq.cgs new file mode 100644 index 0000000..c4d6d8b --- /dev/null +++ b/sim/testsuite/m32r/beq.cgs @@ -0,0 +1,20 @@ +# m32r testcase for beq $src1,$src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + mvi_h_gr r4, 12 + mvi_h_gr r5, 12 + beq r4, r5, ok +not_ok: + fail +ok: + mvi_h_gr r5, 11 + beq r4, r5, not_ok + + pass diff --git a/sim/testsuite/m32r/beqz.cgs b/sim/testsuite/m32r/beqz.cgs new file mode 100644 index 0000000..654737d --- /dev/null +++ b/sim/testsuite/m32r/beqz.cgs @@ -0,0 +1,18 @@ +# m32r testcase for beqz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global beqz +beqz: + mvi_h_gr r4, 0 + beqz r4, ok +not_ok: + fail +ok: + mvi_h_gr r4, 1 + beqz r4, not_ok + + pass diff --git a/sim/testsuite/m32r/bgez.cgs b/sim/testsuite/m32r/bgez.cgs new file mode 100644 index 0000000..f7031f0 --- /dev/null +++ b/sim/testsuite/m32r/bgez.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bgez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bgez +bgez: + mvi_h_gr r4, 1 + bgez r4, ok +not_ok: + fail +ok: + mvi_h_gr r4, -1 + bgez r4, not_ok + + pass diff --git a/sim/testsuite/m32r/bgtz.cgs b/sim/testsuite/m32r/bgtz.cgs new file mode 100644 index 0000000..6ab8989 --- /dev/null +++ b/sim/testsuite/m32r/bgtz.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bgtz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bgtz +bgtz: + mvi_h_gr r4, 1 + bgtz r4, ok +not_ok: + fail +ok: + mvi_h_gr r4, 0 + bgtz r4, not_ok + + pass diff --git a/sim/testsuite/m32r/bl24.cgs b/sim/testsuite/m32r/bl24.cgs new file mode 100644 index 0000000..fd6f0dd --- /dev/null +++ b/sim/testsuite/m32r/bl24.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bl $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bl24 +bl24: + bl.l test0pass +test1fail: + fail + +test0pass: + mvaddr_h_gr r4, test1fail + bne r4, r14, test1fail + + pass diff --git a/sim/testsuite/m32r/bl8.cgs b/sim/testsuite/m32r/bl8.cgs new file mode 100644 index 0000000..d263698 --- /dev/null +++ b/sim/testsuite/m32r/bl8.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bl $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bl8 +bl8: + bl.s test0pass +test1fail: + fail + +test0pass: + mvaddr_h_gr r4, test1fail + bne r4, r14, test1fail + + pass diff --git a/sim/testsuite/m32r/blez.cgs b/sim/testsuite/m32r/blez.cgs new file mode 100644 index 0000000..e3d198d --- /dev/null +++ b/sim/testsuite/m32r/blez.cgs @@ -0,0 +1,19 @@ +# m32r testcase for blez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global blez +blez: + mvi_h_gr r4, 0 + blez r4, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 1 + blez r4, test1fail + + pass diff --git a/sim/testsuite/m32r/bltz.cgs b/sim/testsuite/m32r/bltz.cgs new file mode 100644 index 0000000..c9377fc --- /dev/null +++ b/sim/testsuite/m32r/bltz.cgs @@ -0,0 +1,19 @@ +# m32r testcase for bltz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bltz +bltz: + mvi_h_gr r4, -1 + bltz r4, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 0 + bltz r4, test1fail + + pass diff --git a/sim/testsuite/m32r/bnc24.cgs b/sim/testsuite/m32r/bnc24.cgs new file mode 100644 index 0000000..692d2d5 --- /dev/null +++ b/sim/testsuite/m32r/bnc24.cgs @@ -0,0 +1,20 @@ +# m32r testcase for bnc $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnc24 +bnc24: + mvi_h_condbit 0 + bnc.l test0pass + +test1fail: + fail +test0pass: + + mvi_h_condbit 1 + bnc.l test1fail + + pass diff --git a/sim/testsuite/m32r/bnc8.cgs b/sim/testsuite/m32r/bnc8.cgs new file mode 100644 index 0000000..dae2613 --- /dev/null +++ b/sim/testsuite/m32r/bnc8.cgs @@ -0,0 +1,20 @@ +# m32r testcase for bnc $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnc8 +bnc8: + mvi_h_condbit 0 + bnc.s test0pass + +test1fail: + fail + +test0pass: + mvi_h_condbit 1 + bnc.s test1fail + + pass diff --git a/sim/testsuite/m32r/bne.cgs b/sim/testsuite/m32r/bne.cgs new file mode 100644 index 0000000..5e1d7a6 --- /dev/null +++ b/sim/testsuite/m32r/bne.cgs @@ -0,0 +1,20 @@ +# m32r testcase for bne $src1,$src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bne +bne: + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + bne r4, r5, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 2 + bne r4, r5, test1fail + + pass diff --git a/sim/testsuite/m32r/bnez.cgs b/sim/testsuite/m32r/bnez.cgs new file mode 100644 index 0000000..9f10289 --- /dev/null +++ b/sim/testsuite/m32r/bnez.cgs @@ -0,0 +1,19 @@ +# m32r testcase for bnez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnez +bnez: + mvi_h_gr r4, 1 + bnez r4, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 0 + bnez r4, test1fail + + pass diff --git a/sim/testsuite/m32r/bra24.cgs b/sim/testsuite/m32r/bra24.cgs new file mode 100644 index 0000000..d62d2bf --- /dev/null +++ b/sim/testsuite/m32r/bra24.cgs @@ -0,0 +1,15 @@ +# m32r testcase for bra $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bra24 +bra24: + bra.l ok + + fail + +ok: + pass diff --git a/sim/testsuite/m32r/bra8.cgs b/sim/testsuite/m32r/bra8.cgs new file mode 100644 index 0000000..f5f50ad --- /dev/null +++ b/sim/testsuite/m32r/bra8.cgs @@ -0,0 +1,14 @@ +# m32r testcase for bra $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bra8 +bra8: + bra.s ok + + fail +ok: + pass diff --git a/sim/testsuite/m32r/cmp.cgs b/sim/testsuite/m32r/cmp.cgs new file mode 100644 index 0000000..6ea6720 --- /dev/null +++ b/sim/testsuite/m32r/cmp.cgs @@ -0,0 +1,23 @@ +# m32r testcase for cmp $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmp +cmp: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + cmp r4, r5 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, 2 + cmp r4, r5 + bc not_ok + + pass diff --git a/sim/testsuite/m32r/cmpi.cgs b/sim/testsuite/m32r/cmpi.cgs new file mode 100644 index 0000000..af11283 --- /dev/null +++ b/sim/testsuite/m32r/cmpi.cgs @@ -0,0 +1,24 @@ +# m32r testcase for cmpi $src2,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpi +cmpi: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + + cmpi r4, #2 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, 2 + cmpi r4, #2 + bc not_ok + + + pass diff --git a/sim/testsuite/m32r/cmpu.cgs b/sim/testsuite/m32r/cmpu.cgs new file mode 100644 index 0000000..e0b4ef1 --- /dev/null +++ b/sim/testsuite/m32r/cmpu.cgs @@ -0,0 +1,23 @@ +# m32r testcase for cmpu $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpu +cmpu: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + mvi_h_gr r5, -2 + cmpu r4, r5 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, -1 + cmpu r4, r5 + bc not_ok + + pass diff --git a/sim/testsuite/m32r/cmpui.cgs b/sim/testsuite/m32r/cmpui.cgs new file mode 100644 index 0000000..aa30207 --- /dev/null +++ b/sim/testsuite/m32r/cmpui.cgs @@ -0,0 +1,22 @@ +# m32r testcase for cmpui $src2,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpui +cmpui: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + cmpui r4, #2 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, -1 + cmpui r4, #2 + bc not_ok + + pass diff --git a/sim/testsuite/m32r/div.cgs b/sim/testsuite/m32r/div.cgs new file mode 100644 index 0000000..733f362 --- /dev/null +++ b/sim/testsuite/m32r/div.cgs @@ -0,0 +1,17 @@ +# m32r testcase for div $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global div +div: + mvi_h_gr r4, 0x18000 + mvi_h_gr r5, 8 + + div r4, r5 + + test_h_gr r4, 0x3000 + + pass diff --git a/sim/testsuite/m32r/divu.cgs b/sim/testsuite/m32r/divu.cgs new file mode 100644 index 0000000..25342d5 --- /dev/null +++ b/sim/testsuite/m32r/divu.cgs @@ -0,0 +1,17 @@ +# m32r testcase for divu $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global divu +divu: + mvi_h_gr r4, 0x18000 + mvi_h_gr r5, 8 + + divu r4, r5 + + test_h_gr r4, 0x3000 + + pass diff --git a/sim/testsuite/m32r/exit47.ms b/sim/testsuite/m32r/exit47.ms new file mode 100644 index 0000000..20074f6 --- /dev/null +++ b/sim/testsuite/m32r/exit47.ms @@ -0,0 +1,11 @@ +# mach(): m32r m32rx +# status: 47 +# output: + + ;; Return with exit code 47. + + .globl _start +_start: + ldi8 r1,#47 + ldi8 r0,#1 + trap #0 diff --git a/sim/testsuite/m32r/hello.ms b/sim/testsuite/m32r/hello.ms new file mode 100644 index 0000000..7ae2277 --- /dev/null +++ b/sim/testsuite/m32r/hello.ms @@ -0,0 +1,19 @@ +# output(): Hello world!\n +# mach(): m32r m32rx + + .globl _start +_start: + +; write (hello world) + ldi8 r3,#14 + ld24 r2,#hello + ldi8 r1,#1 + ldi8 r0,#5 + trap #0 +; exit (0) + ldi8 r1,#0 + ldi8 r0,#1 + trap #0 + +length: .long 14 +hello: .ascii "Hello world!\r\n" diff --git a/sim/testsuite/m32r/hw-trap.ms b/sim/testsuite/m32r/hw-trap.ms new file mode 100644 index 0000000..2aa200b --- /dev/null +++ b/sim/testsuite/m32r/hw-trap.ms @@ -0,0 +1,31 @@ +# mach(): m32r m32rx +# output(): pass\n + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#bra_insn + ld r0,@r0 + ld24 r1,#trap2_handler + addi r1,#-0x48 ; pc relative address from trap 2 slot to handler + srai r1,#2 + or r0,r1 + ld24 r2,#0x48 ; address of trap 2 slot + st r0,@r2 + +; perform trap + ldi r4,#0 + trap #2 + test_h_gr r4,42 + + pass + +; trap 2 handler +trap2_handler: + ldi r4,#42 + rte + +bra_insn: + bra.l 0 diff --git a/sim/testsuite/m32r/jl.cgs b/sim/testsuite/m32r/jl.cgs new file mode 100644 index 0000000..a89c26a --- /dev/null +++ b/sim/testsuite/m32r/jl.cgs @@ -0,0 +1,18 @@ +# m32r testcase for jl $sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global jl +jl: + mvaddr_h_gr r4, ok + jl r4 +not_ok: + fail +ok: + mvaddr_h_gr r4, not_ok + bne r4, r14, not_ok + + pass diff --git a/sim/testsuite/m32r/jmp.cgs b/sim/testsuite/m32r/jmp.cgs new file mode 100644 index 0000000..ba0864a --- /dev/null +++ b/sim/testsuite/m32r/jmp.cgs @@ -0,0 +1,19 @@ +# m32r testcase for jmp $sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global jmp +jmp: + mvaddr_h_gr r4, ok1 + jmp r4 + fail +ok1: + mvaddr_h_gr r4, ok2 + addi r4,#1 + jmp r4 + fail +ok2: + pass diff --git a/sim/testsuite/m32r/ld-d.cgs b/sim/testsuite/m32r/ld-d.cgs new file mode 100644 index 0000000..1517436 --- /dev/null +++ b/sim/testsuite/m32r/ld-d.cgs @@ -0,0 +1,22 @@ +# m32r testcase for ld $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld_d +ld_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ld r5, @(#4, r4) + + test_h_gr r5, 0x12345678 + + pass + +data_loc: + .word 0x11223344 + .word 0x12345678 + diff --git a/sim/testsuite/m32r/ld-plus.cgs b/sim/testsuite/m32r/ld-plus.cgs new file mode 100644 index 0000000..5feaf62 --- /dev/null +++ b/sim/testsuite/m32r/ld-plus.cgs @@ -0,0 +1,28 @@ +# m32r testcase for ld $dr,@$sr+ +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld_plus +ld_plus: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ld r5, @r4+ + + test_h_gr r5, 0x12345678 + + mvaddr_h_gr r5, data_loc2 + bne r4, r5, not_ok + + pass +not_ok: + fail + +data_loc: + .word 0x12345678 +data_loc2: + .word 0x11223344 + diff --git a/sim/testsuite/m32r/ld.cgs b/sim/testsuite/m32r/ld.cgs new file mode 100644 index 0000000..ad0b86f --- /dev/null +++ b/sim/testsuite/m32r/ld.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ld $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld +ld: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ld r5, @r4 + + test_h_gr r5, 0x12345678 + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/m32r/ld24.cgs b/sim/testsuite/m32r/ld24.cgs new file mode 100644 index 0000000..74b1555 --- /dev/null +++ b/sim/testsuite/m32r/ld24.cgs @@ -0,0 +1,14 @@ +# m32r testcase for ld24 $dr,#$uimm24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld24 +ld24: + ld24 r4, #0x123456 + + test_h_gr r4, 0x123456 + + pass diff --git a/sim/testsuite/m32r/ldb-d.cgs b/sim/testsuite/m32r/ldb-d.cgs new file mode 100644 index 0000000..4a1cebb --- /dev/null +++ b/sim/testsuite/m32r/ldb-d.cgs @@ -0,0 +1,20 @@ +# m32r testcase for ldb $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldb_d +ldb_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldb r5, @(#2, r4) + + test_h_gr r5, 0x56 ; big endian processor + + pass + +data_loc: + .word 0x12345678 diff --git a/sim/testsuite/m32r/ldb.cgs b/sim/testsuite/m32r/ldb.cgs new file mode 100644 index 0000000..9b89545 --- /dev/null +++ b/sim/testsuite/m32r/ldb.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldb $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldb +ldb: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldb r5, @r4 + + test_h_gr r5, 0x12 ; big endian processor + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/m32r/ldh-d.cgs b/sim/testsuite/m32r/ldh-d.cgs new file mode 100644 index 0000000..0be0309 --- /dev/null +++ b/sim/testsuite/m32r/ldh-d.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldh $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldh_d +ldh_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldh r5, @(#2, r4) + + test_h_gr r5, 0x5678 ; big endian processor + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/m32r/ldh.cgs b/sim/testsuite/m32r/ldh.cgs new file mode 100644 index 0000000..3d8db95 --- /dev/null +++ b/sim/testsuite/m32r/ldh.cgs @@ -0,0 +1,22 @@ +# m32r testcase for ldh $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldh +ldh: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldh r5, @r4 + + test_h_gr r5, 0x1234 ; big endian processor + + pass + +data_loc: + .word 0x12345678 + + pass diff --git a/sim/testsuite/m32r/ldi16.cgs b/sim/testsuite/m32r/ldi16.cgs new file mode 100644 index 0000000..478df1c --- /dev/null +++ b/sim/testsuite/m32r/ldi16.cgs @@ -0,0 +1,14 @@ +# m32r testcase for ldi $dr,$slo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldi16 +ldi16: + ldi r4, #0x1234 + + test_h_gr r4, 0x1234 + + pass diff --git a/sim/testsuite/m32r/ldi8.cgs b/sim/testsuite/m32r/ldi8.cgs new file mode 100644 index 0000000..081e7a8 --- /dev/null +++ b/sim/testsuite/m32r/ldi8.cgs @@ -0,0 +1,14 @@ +# m32r testcase for ldi $dr,#$simm8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldi8 +ldi8: + ldi r4, #0x78 + + test_h_gr r4, 0x78 + + pass diff --git a/sim/testsuite/m32r/ldub-d.cgs b/sim/testsuite/m32r/ldub-d.cgs new file mode 100644 index 0000000..7661071 --- /dev/null +++ b/sim/testsuite/m32r/ldub-d.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldub $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldub_d +ldub_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldub r5, @(#2, r4) + + test_h_gr r5, 0xa0 ; big endian processor + + pass + +data_loc: + .word 0x8090a0b0 + diff --git a/sim/testsuite/m32r/ldub.cgs b/sim/testsuite/m32r/ldub.cgs new file mode 100644 index 0000000..27913b5 --- /dev/null +++ b/sim/testsuite/m32r/ldub.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldub $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldub +ldub: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldub r5, @r4 + + test_h_gr r5, 0x80 ; big endian processor + + pass + +data_loc: + .word 0x800000f0 + diff --git a/sim/testsuite/m32r/lduh-d.cgs b/sim/testsuite/m32r/lduh-d.cgs new file mode 100644 index 0000000..96e294f --- /dev/null +++ b/sim/testsuite/m32r/lduh-d.cgs @@ -0,0 +1,20 @@ +# m32r testcase for lduh $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lduh_d +lduh_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + lduh r5, @(#2, r4) + + test_h_gr r5, 0xf000 ; big endian processor + + pass + +data_loc: + .word 0x8000f000 diff --git a/sim/testsuite/m32r/lduh.cgs b/sim/testsuite/m32r/lduh.cgs new file mode 100644 index 0000000..a03bbee --- /dev/null +++ b/sim/testsuite/m32r/lduh.cgs @@ -0,0 +1,22 @@ +# m32r testcase for lduh $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lduh +lduh: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + lduh r5, @r4 + + test_h_gr r5, 0x8010 ; big endian processor + + pass + +data_loc: + .word 0x8010f020 + + pass diff --git a/sim/testsuite/m32r/lock.cgs b/sim/testsuite/m32r/lock.cgs new file mode 100644 index 0000000..631525e --- /dev/null +++ b/sim/testsuite/m32r/lock.cgs @@ -0,0 +1,25 @@ +# m32r testcase for lock $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lock +lock: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + lock r5, @r4 + + test_h_gr r5, 0x12345678 + + ; There is no way to test the lock bit + + unlock r5, @r4 ; Unlock the processor + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/m32r/machi.cgs b/sim/testsuite/m32r/machi.cgs new file mode 100644 index 0000000..2e2ef00 --- /dev/null +++ b/sim/testsuite/m32r/machi.cgs @@ -0,0 +1,17 @@ +# m32r testcase for machi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global machi +machi: + + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + machi r4, r5 + test_h_accum0 0, 0x20001 + + pass diff --git a/sim/testsuite/m32r/maclo.cgs b/sim/testsuite/m32r/maclo.cgs new file mode 100644 index 0000000..5d03539 --- /dev/null +++ b/sim/testsuite/m32r/maclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for maclo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global maclo +maclo: + + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x1230001 + mvi_h_gr r5, 0x4560002 + maclo r4, r5 + test_h_accum0 0, 0x20001 + + pass diff --git a/sim/testsuite/m32r/macwhi.cgs b/sim/testsuite/m32r/macwhi.cgs new file mode 100644 index 0000000..9ee7a5b --- /dev/null +++ b/sim/testsuite/m32r/macwhi.cgs @@ -0,0 +1,18 @@ +# m32r testcase for macwhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global macwhi +macwhi: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + + macwhi r4, r5 + + test_h_accum0 0, 0x20247 + + pass diff --git a/sim/testsuite/m32r/macwlo.cgs b/sim/testsuite/m32r/macwlo.cgs new file mode 100644 index 0000000..a7ce4ed --- /dev/null +++ b/sim/testsuite/m32r/macwlo.cgs @@ -0,0 +1,18 @@ +# m32r testcase for macwlo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global macwlo +macwlo: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x40002 + + macwlo r4, r5 + + test_h_accum0 0, 0x20247 + + pass diff --git a/sim/testsuite/m32r/misc.exp b/sim/testsuite/m32r/misc.exp new file mode 100644 index 0000000..6ed5638 --- /dev/null +++ b/sim/testsuite/m32r/misc.exp @@ -0,0 +1,21 @@ +# Miscellaneous M32R simulator testcases + +if [istarget m32r*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "m32r" + + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/m32r/mul.cgs b/sim/testsuite/m32r/mul.cgs new file mode 100644 index 0000000..c78f24b --- /dev/null +++ b/sim/testsuite/m32r/mul.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mul $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mul +mul: + mvi_h_gr r4, 3 + mvi_h_gr r5, 7 + + mul r5, r4 + + test_h_gr r5, 21 + + pass diff --git a/sim/testsuite/m32r/mulhi.cgs b/sim/testsuite/m32r/mulhi.cgs new file mode 100644 index 0000000..77c103d --- /dev/null +++ b/sim/testsuite/m32r/mulhi.cgs @@ -0,0 +1,16 @@ +# m32r testcase for mulhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulhi +mulhi: + + mvi_h_gr r4, 0x40000 + mvi_h_gr r5, 0x50000 + mulhi r4, r5 + test_h_accum0 0, 0x140000 + + pass diff --git a/sim/testsuite/m32r/mullo.cgs b/sim/testsuite/m32r/mullo.cgs new file mode 100644 index 0000000..11aadff --- /dev/null +++ b/sim/testsuite/m32r/mullo.cgs @@ -0,0 +1,16 @@ +# m32r testcase for mullo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mullo +mullo: + + mvi_h_gr r4, 4 + mvi_h_gr r5, 5 + mullo r4, r5 + test_h_accum0 0, 0x140000 + + pass diff --git a/sim/testsuite/m32r/mulwhi.cgs b/sim/testsuite/m32r/mulwhi.cgs new file mode 100644 index 0000000..eb18562 --- /dev/null +++ b/sim/testsuite/m32r/mulwhi.cgs @@ -0,0 +1,18 @@ +# m32r testcase for mulwhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulwhi +mulwhi: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + + mulwhi r4, r5 + + test_h_accum0 0, 0x20246 + + pass diff --git a/sim/testsuite/m32r/mulwlo.cgs b/sim/testsuite/m32r/mulwlo.cgs new file mode 100644 index 0000000..d22c268 --- /dev/null +++ b/sim/testsuite/m32r/mulwlo.cgs @@ -0,0 +1,18 @@ +# m32r testcase for mulwlo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulwlo +mulwlo: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x40002 + + mulwlo r4, r5 + + test_h_accum0 0, 0x20246 + + pass diff --git a/sim/testsuite/m32r/mv.cgs b/sim/testsuite/m32r/mv.cgs new file mode 100644 index 0000000..6945695 --- /dev/null +++ b/sim/testsuite/m32r/mv.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mv +mv: + mvi_h_gr r4, 1 + mvi_h_gr r5, 0 + + mv r5, r4 + + test_h_gr r5, 1 + + pass diff --git a/sim/testsuite/m32r/mvfachi.cgs b/sim/testsuite/m32r/mvfachi.cgs new file mode 100644 index 0000000..0222e1b --- /dev/null +++ b/sim/testsuite/m32r/mvfachi.cgs @@ -0,0 +1,22 @@ +# m32r testcase for mvfachi $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfachi +mvfachi: + mvi_h_accum0 0x11223344, 0x55667788 + mvi_h_gr r4, 0 + + mvfachi r4 + test_h_gr r4, 0x223344 + + mvi_h_accum0 0x99aabbcc, 0x55667788 + mvi_h_gr r4, 0 + + mvfachi r4 + test_h_gr r4, 0xffaabbcc + + pass diff --git a/sim/testsuite/m32r/mvfaclo.cgs b/sim/testsuite/m32r/mvfaclo.cgs new file mode 100644 index 0000000..0a88d84 --- /dev/null +++ b/sim/testsuite/m32r/mvfaclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mvfaclo $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfaclo +mvfaclo: + mvi_h_accum0 0x11223344, 0x55667788 + mvi_h_gr r4, 0 + + mvfaclo r4 + + test_h_gr r4, 0x55667788 + + pass diff --git a/sim/testsuite/m32r/mvfacmi.cgs b/sim/testsuite/m32r/mvfacmi.cgs new file mode 100644 index 0000000..580bcae --- /dev/null +++ b/sim/testsuite/m32r/mvfacmi.cgs @@ -0,0 +1,15 @@ +# m32r testcase for mvfacmi $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfacmi +mvfacmi: + + mvi_h_accum0 0x12345678, 0x87654321 + mvfacmi r4 + test_h_gr r4, 0x56788765 + + pass diff --git a/sim/testsuite/m32r/mvfc.cgs b/sim/testsuite/m32r/mvfc.cgs new file mode 100644 index 0000000..ca2470e --- /dev/null +++ b/sim/testsuite/m32r/mvfc.cgs @@ -0,0 +1,23 @@ +# m32r testcase for mvfc $dr,$scr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfc +mvfc: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + + mvfc r4, cr1 + + test_h_gr r4, 0 + + mvi_h_condbit 1 + + mvfc r4, cr1 + + test_h_gr r4, 1 + + pass diff --git a/sim/testsuite/m32r/mvtachi.cgs b/sim/testsuite/m32r/mvtachi.cgs new file mode 100644 index 0000000..6d59616 --- /dev/null +++ b/sim/testsuite/m32r/mvtachi.cgs @@ -0,0 +1,20 @@ +# m32r testcase for mvtachi $src1 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtachi +mvtachi: + mvi_h_accum0 0, 0 + + mvi_h_gr r4, 0x11223344 + mvtachi r4 + test_h_accum0 0x223344, 0x0 + + mvi_h_gr r4, 0x99aabbcc + mvtachi r4 + test_h_accum0 0xffaabbcc, 0x0 + + pass diff --git a/sim/testsuite/m32r/mvtaclo.cgs b/sim/testsuite/m32r/mvtaclo.cgs new file mode 100644 index 0000000..baafd83 --- /dev/null +++ b/sim/testsuite/m32r/mvtaclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mvtaclo $src1 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtaclo +mvtaclo: + mvi_h_accum0 0, 0 + mvi_h_gr r4, 0x11223344 + + mvtaclo r4 + + test_h_accum0 0, 0x11223344 + + pass diff --git a/sim/testsuite/m32r/mvtc.cgs b/sim/testsuite/m32r/mvtc.cgs new file mode 100644 index 0000000..94780df --- /dev/null +++ b/sim/testsuite/m32r/mvtc.cgs @@ -0,0 +1,18 @@ +# m32r testcase for mvtc $sr,$dcr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtc +mvtc: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + + mvtc r4, cr1 + bc ok + + fail +ok: + pass diff --git a/sim/testsuite/m32r/neg.cgs b/sim/testsuite/m32r/neg.cgs new file mode 100644 index 0000000..6051efa --- /dev/null +++ b/sim/testsuite/m32r/neg.cgs @@ -0,0 +1,17 @@ +# m32r testcase for neg $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global neg +neg: + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + + neg r4, r5 + + test_h_gr r4, -2 + + pass diff --git a/sim/testsuite/m32r/nop.cgs b/sim/testsuite/m32r/nop.cgs new file mode 100644 index 0000000..e06d656 --- /dev/null +++ b/sim/testsuite/m32r/nop.cgs @@ -0,0 +1,11 @@ +# m32r testcase for nop +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global nop +nop: + nop + pass diff --git a/sim/testsuite/m32r/not.cgs b/sim/testsuite/m32r/not.cgs new file mode 100644 index 0000000..e6ceb64 --- /dev/null +++ b/sim/testsuite/m32r/not.cgs @@ -0,0 +1,17 @@ +# m32r testcase for not $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global not +not: + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + + not r4, r5 + + test_h_gr r4, 0xfffffffd + + pass diff --git a/sim/testsuite/m32r/or.cgs b/sim/testsuite/m32r/or.cgs new file mode 100644 index 0000000..1b08bd0 --- /dev/null +++ b/sim/testsuite/m32r/or.cgs @@ -0,0 +1,17 @@ +# m32r testcase for or $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global or +or: + mvi_h_gr r4, 3 + mvi_h_gr r5, 6 + + or r4, r5 + + test_h_gr r4, 7 + + pass diff --git a/sim/testsuite/m32r/or3.cgs b/sim/testsuite/m32r/or3.cgs new file mode 100644 index 0000000..dc76ada --- /dev/null +++ b/sim/testsuite/m32r/or3.cgs @@ -0,0 +1,17 @@ +# m32r testcase for or3 $dr,$sr,#$ulo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global or3 +or3: + mvi_h_gr r4, 0 + mvi_h_gr r5, 6 + + or3 r4, r5, #3 + + test_h_gr r4, 7 + + pass diff --git a/sim/testsuite/m32r/rac.cgs b/sim/testsuite/m32r/rac.cgs new file mode 100644 index 0000000..35b9ae3 --- /dev/null +++ b/sim/testsuite/m32r/rac.cgs @@ -0,0 +1,23 @@ +# m32r testcase for rac +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rac +rac: + + mvi_h_accum0 1, 0x4001 + rac + test_h_accum0 2, 0x10000 + + mvi_h_accum0 0x3fff, 0xffff4000 + rac + test_h_accum0 0x7fff, 0xffff0000 + + mvi_h_accum0 0xffff8000, 0 + rac + test_h_accum0 0xffff8000, 0 + + pass diff --git a/sim/testsuite/m32r/rach.cgs b/sim/testsuite/m32r/rach.cgs new file mode 100644 index 0000000..c224698 --- /dev/null +++ b/sim/testsuite/m32r/rach.cgs @@ -0,0 +1,22 @@ +# m32r testcase for rach +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rach +rach: + mvi_h_accum0 1, 0x40004001 + rach + test_h_accum0 3, 0 + + mvi_h_accum0 0x3fff, 0xc0000000 + rach + test_h_accum0 0x7fff, 0 + + mvi_h_accum0 0xffff8000, 0 + rach + test_h_accum0 0xffff8000, 0 + + pass diff --git a/sim/testsuite/m32r/rem.cgs b/sim/testsuite/m32r/rem.cgs new file mode 100644 index 0000000..78c11cb --- /dev/null +++ b/sim/testsuite/m32r/rem.cgs @@ -0,0 +1,17 @@ +# m32r testcase for rem $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rem +rem: + mvi_h_gr r4, 12345678 + mvi_h_gr r5, 7 + + rem r4, r5 + + test_h_gr r4, 2 + + pass diff --git a/sim/testsuite/m32r/remu.cgs b/sim/testsuite/m32r/remu.cgs new file mode 100644 index 0000000..3633630 --- /dev/null +++ b/sim/testsuite/m32r/remu.cgs @@ -0,0 +1,23 @@ +# m32r testcase for remu $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global remu +remu: + mvi_h_gr r4, 17 + mvi_h_gr r5, 7 + + remu r4, r5 + + test_h_gr r4, 3 + + mvi_h_gr r4, -17 + + remu r4, r5 + + test_h_gr r4, 1 + + pass diff --git a/sim/testsuite/m32r/rte.cgs b/sim/testsuite/m32r/rte.cgs new file mode 100644 index 0000000..b389fe1 --- /dev/null +++ b/sim/testsuite/m32r/rte.cgs @@ -0,0 +1,87 @@ +# m32r testcase for rte +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rte +rte: + +; Test 1: bbpsw = 0, bpsw = 1, psw = 0 + + ; bbsm = 0, bie = 0, bbcond = 0 + mvi_h_gr r4, 0 + mvtc r4, cr8 + + ; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvi_h_gr r4, 0xc100 + mvtc r4, cr0 + + ; bbpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bbpc + + ; bpc = ret1 + mvaddr_h_gr r4, ret1 + mvtc r4, bpc + + rte + fail + +ret1: + ; test bbsm = 0, bbie = 0, bbcond = 0 + mvfc r4, cr8 + test_h_gr r4, 0 + + ; test bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvfc r4, cr0 + test_h_gr r4, 0xc1 + + ; test bbpc = 0 + mvfc r4, bbpc + test_h_gr r4, 0 + + ; test bpc = 0 + mvfc r4, bpc + test_h_gr r4, 0 + +; Test 2: bbpsw = 1, bpsw = 0, psw = 1 + + ; bbsm = 1, bie = 1, bbcond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr8 + + ; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr0 + + ; bbpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bbpc + + ; bpc = ret2 + 2 + mvaddr_h_gr r4, ret2 + 2 + mvtc r4, bpc + + rte + fail + +ret2: + ; test bbsm = 1, bbie = 1, bbcond = 1 + mvfc r4, cr8 + test_h_gr r4, 0xc1 + + ; test bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0xc100 + + ; test bbpc = 42 + mvfc r4, bbpc + test_h_gr r4, 42 + + ; test bpc = 42 + mvfc r4, bpc + test_h_gr r4, 42 + + pass diff --git a/sim/testsuite/m32r/seth.cgs b/sim/testsuite/m32r/seth.cgs new file mode 100644 index 0000000..aec3230 --- /dev/null +++ b/sim/testsuite/m32r/seth.cgs @@ -0,0 +1,20 @@ +# m32r testcase for seth $dr,#$hi16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global seth +seth: + seth r4, #0x1234 + + ; do not use test_h_gr macro since this uses seth + + srli r4, #16 + ld24 r5, #0x1234 + beq r4, r5, ok + + fail +ok: + pass diff --git a/sim/testsuite/m32r/sll.cgs b/sim/testsuite/m32r/sll.cgs new file mode 100644 index 0000000..fa3cfed --- /dev/null +++ b/sim/testsuite/m32r/sll.cgs @@ -0,0 +1,15 @@ +# m32r testcase for sll $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sll +sll: + mvi_h_gr r4, 6 + mvi_h_gr r5, 1 + sll r4, r5 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/m32r/sll3.cgs b/sim/testsuite/m32r/sll3.cgs new file mode 100644 index 0000000..ddd360c --- /dev/null +++ b/sim/testsuite/m32r/sll3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for sll3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sll3 +sll3: + mvi_h_gr r4, 1 + mvi_h_gr r5, 6 + sll3 r4, r5, #1 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/m32r/slli.cgs b/sim/testsuite/m32r/slli.cgs new file mode 100644 index 0000000..eab77da --- /dev/null +++ b/sim/testsuite/m32r/slli.cgs @@ -0,0 +1,14 @@ +# m32r testcase for slli $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global slli +slli: + mvi_h_gr r4, 6 + slli r4, #1 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/m32r/sra.cgs b/sim/testsuite/m32r/sra.cgs new file mode 100644 index 0000000..11671ed --- /dev/null +++ b/sim/testsuite/m32r/sra.cgs @@ -0,0 +1,16 @@ +# m32r testcase for sra $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sra +sra: + + mvi_h_gr r4, 0xf0f0f0ff + mvi_h_gr r5, 4 + sra r4, r5 + test_h_gr r4, 0xff0f0f0f + + pass diff --git a/sim/testsuite/m32r/sra3.cgs b/sim/testsuite/m32r/sra3.cgs new file mode 100644 index 0000000..0dd387a --- /dev/null +++ b/sim/testsuite/m32r/sra3.cgs @@ -0,0 +1,16 @@ +# m32r testcase for sra3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sra3 +sra3: + + mvi_h_gr r4, 0 + mvi_h_gr r5, 0xf0f0f0ff + sra3 r4, r5, #4 + test_h_gr r4, 0xff0f0f0f + + pass diff --git a/sim/testsuite/m32r/srai.cgs b/sim/testsuite/m32r/srai.cgs new file mode 100644 index 0000000..2a15694 --- /dev/null +++ b/sim/testsuite/m32r/srai.cgs @@ -0,0 +1,14 @@ +# m32r testcase for srai $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srai +srai: + mvi_h_gr r5, 0xf0f0f0ff + srai r5, #4 + test_h_gr r5, 0xff0f0f0f + + pass diff --git a/sim/testsuite/m32r/srl.cgs b/sim/testsuite/m32r/srl.cgs new file mode 100644 index 0000000..8838c2f --- /dev/null +++ b/sim/testsuite/m32r/srl.cgs @@ -0,0 +1,15 @@ +# m32r testcase for srl $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srl +srl: + mvi_h_gr r4, 6 + mvi_h_gr r5, 1 + srl r4, r5 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/m32r/srl3.cgs b/sim/testsuite/m32r/srl3.cgs new file mode 100644 index 0000000..a1dc484 --- /dev/null +++ b/sim/testsuite/m32r/srl3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for srl3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srl3 +srl3: + mvi_h_gr r4, 0 + mvi_h_gr r5, 6 + srl3 r4, r5, #1 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/m32r/srli.cgs b/sim/testsuite/m32r/srli.cgs new file mode 100644 index 0000000..f358a76 --- /dev/null +++ b/sim/testsuite/m32r/srli.cgs @@ -0,0 +1,15 @@ +# m32r testcase for srli $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srli +srli: + mvi_h_gr r5, 6 + srli r5, #1 + test_h_gr r5, 3 + + + pass diff --git a/sim/testsuite/m32r/st-d.cgs b/sim/testsuite/m32r/st-d.cgs new file mode 100644 index 0000000..e2668a0 --- /dev/null +++ b/sim/testsuite/m32r/st-d.cgs @@ -0,0 +1,26 @@ +# m32r testcase for st $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_d +st_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + st r5, @(#8,r4) + + mvaddr_h_gr r4, data_loc2 + ld r4, @r4 + test_h_gr r4, 1 + + pass + +data_loc: + .word 0 + .word 0 +data_loc2: + .word 0 + diff --git a/sim/testsuite/m32r/st-minus.cgs b/sim/testsuite/m32r/st-minus.cgs new file mode 100644 index 0000000..fc90351 --- /dev/null +++ b/sim/testsuite/m32r/st-minus.cgs @@ -0,0 +1,29 @@ +# m32r testcase for st $src1,@-$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_minus +st_minus: + mvaddr_h_gr r4, data_loc2 + mvi_h_gr r5, 1 + + st r5, @-r4 + + mvaddr_h_gr r5, data_loc + + bne r4, r5, not_ok + ld r4, @r4 + test_h_gr r4, 1 + + pass +not_ok: + fail + +data_loc: + .word 0 +data_loc2: + .word 0 + diff --git a/sim/testsuite/m32r/st-plus.cgs b/sim/testsuite/m32r/st-plus.cgs new file mode 100644 index 0000000..7bb4dd1 --- /dev/null +++ b/sim/testsuite/m32r/st-plus.cgs @@ -0,0 +1,28 @@ +# m32r testcase for st $src1,@+$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_plus +st_plus: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + st r5, @+r4 + + mvaddr_h_gr r5, data_loc2 + + bne r4, r5, not_ok + ld r4, @r4 + test_h_gr r4, 1 + + pass +not_ok: + fail + +data_loc: + .word 0 +data_loc2: + .word 0 diff --git a/sim/testsuite/m32r/st.cgs b/sim/testsuite/m32r/st.cgs new file mode 100644 index 0000000..9588b8c --- /dev/null +++ b/sim/testsuite/m32r/st.cgs @@ -0,0 +1,21 @@ +# m32r testcase for st $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st +st: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + st r5, @r4 + + ld r4, @r4 + test_h_gr r4, 1 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/m32r/stb-d.cgs b/sim/testsuite/m32r/stb-d.cgs new file mode 100644 index 0000000..37c2d73 --- /dev/null +++ b/sim/testsuite/m32r/stb-d.cgs @@ -0,0 +1,25 @@ +# m32r testcase for stb $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global stb_d +stb_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x1234 + + stb r5, @(#8,r4) + + mvaddr_h_gr r4, data_loc2 + ld r4, @r4 + test_h_gr r4, 0x34000000 ; big endian processor + + pass + +data_loc: + .word 0 + .word 0 +data_loc2: + .word 0 diff --git a/sim/testsuite/m32r/stb.cgs b/sim/testsuite/m32r/stb.cgs new file mode 100644 index 0000000..0128316 --- /dev/null +++ b/sim/testsuite/m32r/stb.cgs @@ -0,0 +1,21 @@ +# m32r testcase for stb $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global stb +stb: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x1234 + + stb r5, @r4 + + ld r4, @r4 + test_h_gr r4, 0x34000000 ; big endian processor + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/m32r/sth-d.cgs b/sim/testsuite/m32r/sth-d.cgs new file mode 100644 index 0000000..11aaa6d --- /dev/null +++ b/sim/testsuite/m32r/sth-d.cgs @@ -0,0 +1,25 @@ +# m32r testcase for sth $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sth_d +sth_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x123456 + + sth r5, @(#8,r4) + + mvaddr_h_gr r4, data_loc2 + ld r4, @r4 + test_h_gr r4, 0x34560000 ; big endian processor + + pass + +data_loc: + .word 0 + .word 0 +data_loc2: + .word 0 diff --git a/sim/testsuite/m32r/sth.cgs b/sim/testsuite/m32r/sth.cgs new file mode 100644 index 0000000..1a10fde --- /dev/null +++ b/sim/testsuite/m32r/sth.cgs @@ -0,0 +1,21 @@ +# m32r testcase for sth $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sth +sth: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x123456 + + sth r5, @r4 + + ld r4, @r4 + test_h_gr r4, 0x34560000 ; big endian processor + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/m32r/sub.cgs b/sim/testsuite/m32r/sub.cgs new file mode 100644 index 0000000..4d676e5 --- /dev/null +++ b/sim/testsuite/m32r/sub.cgs @@ -0,0 +1,18 @@ +# m32r testcase for sub $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sub +sub: + + mvi_h_gr r4, 7 + mvi_h_gr r5, 3 + + sub r4, r5 + + test_h_gr r4, 4 + + pass diff --git a/sim/testsuite/m32r/subv.cgs b/sim/testsuite/m32r/subv.cgs new file mode 100644 index 0000000..9474766 --- /dev/null +++ b/sim/testsuite/m32r/subv.cgs @@ -0,0 +1,20 @@ +# m32r testcase for subv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global subv +subv: + mvi_h_condbit 0 + mvi_h_gr r4, 0x80000000 + mvi_h_gr r5, 3 + + subv r4, r5 + + bc ok + + fail +ok: + pass diff --git a/sim/testsuite/m32r/subx.cgs b/sim/testsuite/m32r/subx.cgs new file mode 100644 index 0000000..e890fcf --- /dev/null +++ b/sim/testsuite/m32r/subx.cgs @@ -0,0 +1,26 @@ +# m32r testcase for subx $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global subx +subx: + mvi_h_condbit 1 + mvi_h_gr r4, 6 + mvi_h_gr r5, 4 + subx r4, r5 + bc not_ok + test_h_gr r4, 1 + + mvi_h_condbit 1 + mvi_h_gr r4, 4 + mvi_h_gr r5, 4 + subx r4, r5 + bnc not_ok + test_h_gr r4, 0xffffffff + + pass +not_ok: + fail diff --git a/sim/testsuite/m32r/testutils.inc b/sim/testsuite/m32r/testutils.inc new file mode 100644 index 0000000..1d8822a --- /dev/null +++ b/sim/testsuite/m32r/testutils.inc @@ -0,0 +1,95 @@ +# r0-r3 are used as tmps, consider them call clobbered by these macros. + + .macro start + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + .global _start +_start: + .endm + + .macro exit rc + ldi8 r1, \rc + ldi8 r0, #1 + trap #0 + .endm + + .macro pass + ldi8 r3, 5 + ld24 r2, passmsg + ldi8 r1, 1 + ldi8 r0, 5 + trap #0 + exit 0 + .endm + + .macro fail + ldi8 r3, 5 + ld24 r2, failmsg + ldi8 r1, 1 + ldi8 r0, 5 + trap #0 + exit 1 + .endm + + .macro mvi_h_gr reg, val + .if (\val >= -128) && (\val <= 127) + ldi8 \reg, \val + .else + seth \reg, high(\val) + or3 \reg, \reg, low(\val) + .endif + .endm + + .macro mvaddr_h_gr reg, addr + seth \reg, high(\addr) + or3 \reg, \reg, low(\addr) + .endm + +# Other macros know this only clobbers r0. + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + beq \reg, r0, test_gr\@ + fail +test_gr\@: + .endm + + .macro mvi_h_condbit val + ldi8 r0, 0 + ldi8 r1, 1 + .if \val + cmp r0, r1 + .else + cmp r1, r0 + .endif + .endm + + .macro test_h_condbit val + .if \val + bc test_c1\@ + fail +test_c1\@: + .else + bnc test_c0\@ + fail +test_c0\@: + .endif + .endm + + .macro mvi_h_accum0 hi, lo + mvi_h_gr r0, \hi + mvtachi r0 + mvi_h_gr r0, \lo + mvtaclo r0 + .endm + + .macro test_h_accum0 hi, lo + mvfachi r1 + test_h_gr r1, \hi + mvfaclo r1 + test_h_gr r1, \lo + .endm + diff --git a/sim/testsuite/m32r/trap.cgs b/sim/testsuite/m32r/trap.cgs new file mode 100644 index 0000000..59e136a --- /dev/null +++ b/sim/testsuite/m32r/trap.cgs @@ -0,0 +1,109 @@ +# m32r testcase for trap #$uimm4 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global trap +trap: + +; Test 1: bbpsw = 0, bpsw = 1, psw = 0 + + ; bbsm = 0, bie = 0, bbcond = 0 + mvi_h_gr r4, 0 + mvtc r4, cr8 + + ; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvi_h_gr r4, 0xc100 + mvtc r4, cr0 + + ; bbpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bbpc + + ; bpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bpc + + ; Copy trap2_handler to trap area of memory. + ld24 r0,#0x48 ; address of trap 2 handler + ld24 r1,#trap2_handler + ld r2,@r1 + st r2,@r0 + ; Set up return address. + ld24 r5,#trap2_ret1 + +trap_insn1: + trap #2 + fail + +trap2_ret1: + ; test bbsm = 1, bbie = 1, bbcond = 1 + mvfc r4, cr8 + test_h_gr r4, 0xc1 + + ; test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0 + + ; test bbpc = 42 + mvfc r4, bbpc + test_h_gr r4, 42 + + ; test bpc = proper return address + mvfc r4, bpc + test_h_gr r4, trap_insn1 + 4 + +; Test 2: bbpsw = 1, bpsw = 0, psw = 1 + + ; bbsm = 1, bie = 1, bbcond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr8 + + ; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr0 + + ; bbpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bbpc + + ; bpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bpc + + ; Set up return address. + ld24 r5,#trap2_ret2 + +trap_insn2: + trap #2 + fail + +trap2_ret2: + ; test bbsm = 0, bbie = 0, bbcond = 0 + mvfc r4, cr8 + test_h_gr r4, 0 + + ; test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0xc180 + + ; test bbpc = 0 + mvfc r4, bbpc + test_h_gr r4, 0 + + ; test bpc = proper return address + mvfc r4, bpc + test_h_gr r4, trap_insn2 + 4 + + pass + + .data + +; Don't use rte as it will undo the effects of trap we're testing. + + .p2align 2 +trap2_handler: + jmp r5 + nop diff --git a/sim/testsuite/m32r/unlock.cgs b/sim/testsuite/m32r/unlock.cgs new file mode 100644 index 0000000..1a51b7a --- /dev/null +++ b/sim/testsuite/m32r/unlock.cgs @@ -0,0 +1,30 @@ +# m32r testcase for unlock $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global unlock +unlock: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + lock r5, @r4 + + mvi_h_gr r5, 2 + unlock r5, @r4 + + ld r6, @r4 + test_h_gr r6, 2 + + mvi_h_gr r5, 0 + unlock r5, @r4 ; This should be a nop since the processor should be unlocked. + + ld r6, @r4 + test_h_gr r6, 2 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/m32r/uread16.ms b/sim/testsuite/m32r/uread16.ms new file mode 100644 index 0000000..550e99a --- /dev/null +++ b/sim/testsuite/m32r/uread16.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned read* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + ldh r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .short 42 diff --git a/sim/testsuite/m32r/uread32.ms b/sim/testsuite/m32r/uread32.ms new file mode 100644 index 0000000..935c716 --- /dev/null +++ b/sim/testsuite/m32r/uread32.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned read* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + ld r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .word 42 diff --git a/sim/testsuite/m32r/uwrite16.ms b/sim/testsuite/m32r/uwrite16.ms new file mode 100644 index 0000000..11bfd6e --- /dev/null +++ b/sim/testsuite/m32r/uwrite16.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned write* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + sth r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .short 42 diff --git a/sim/testsuite/m32r/uwrite32.ms b/sim/testsuite/m32r/uwrite32.ms new file mode 100644 index 0000000..495a123 --- /dev/null +++ b/sim/testsuite/m32r/uwrite32.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned write* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + st r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .word 42 diff --git a/sim/testsuite/m32r/xor.cgs b/sim/testsuite/m32r/xor.cgs new file mode 100644 index 0000000..254da79 --- /dev/null +++ b/sim/testsuite/m32r/xor.cgs @@ -0,0 +1,16 @@ +# m32r testcase for xor $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global xor +xor: + + mvi_h_gr r4, 3 + mvi_h_gr r5, 6 + xor r4, r5 + test_h_gr r4, 5 + + pass diff --git a/sim/testsuite/m32r/xor3.cgs b/sim/testsuite/m32r/xor3.cgs new file mode 100644 index 0000000..eee7269 --- /dev/null +++ b/sim/testsuite/m32r/xor3.cgs @@ -0,0 +1,16 @@ +# m32r testcase for xor3 $dr,$sr,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global xor3 +xor3: + + mvi_h_gr r5, 0 + mvi_h_gr r4, 3 + xor3 r5, r4, #6 + test_h_gr r5, 5 + + pass diff --git a/sim/testsuite/m68hc11/ChangeLog b/sim/testsuite/m68hc11/ChangeLog new file mode 100644 index 0000000..d3f8b9d --- /dev/null +++ b/sim/testsuite/m68hc11/ChangeLog @@ -0,0 +1,3 @@ +2015-04-05 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/m68hc11/allinsn.exp b/sim/testsuite/m68hc11/allinsn.exp new file mode 100644 index 0000000..db0cbd5 --- /dev/null +++ b/sim/testsuite/m68hc11/allinsn.exp @@ -0,0 +1,15 @@ +# m68hc11 simulator testsuite + +if [istarget m68hc11-*] { + # all machines + set all_machs "m68hc11" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/m68hc11/pass.s b/sim/testsuite/m68hc11/pass.s new file mode 100644 index 0000000..302a7fb --- /dev/null +++ b/sim/testsuite/m68hc11/pass.s @@ -0,0 +1,7 @@ +# check that the sim doesn't die immediately. +# mach: m68hc11 + +.include "testutils.inc" + + start + pass diff --git a/sim/testsuite/m68hc11/testutils.inc b/sim/testsuite/m68hc11/testutils.inc new file mode 100644 index 0000000..3d30de2 --- /dev/null +++ b/sim/testsuite/m68hc11/testutils.inc @@ -0,0 +1,53 @@ +# MACRO: exit + .macro exit nr + ldd # \nr + # The debug insn class. + .byte 0xcd + # The exit utility function. + .byte 0x03 + .endm + +# MACRO: pass +# Write 'pass' to stdout and quit + .macro pass + # Point to the string. + # NB: See comment above _pass below. + ldx #0x8000 + # Number of bytes to write. + ldd #5 + # The debug insn class. + .byte 0xcd + # The write utility function. + .byte 0x01 + exit 0 + .endm + +# MACRO: ffail +# Write 'ffail' to stdout and quit +# Normally this would be 'fail', but m68k has a pseudo "fail" op. + .macro ffail + # Point to the string. + ldx #0x8006 + # Number of bytes to write. + ldd #5 + # The debug insn class. + .byte 0xcd + # The write utility function. + .byte 0x01 + exit 0 + .endm + +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .text +# These need to be at the start of text as it's the only stable address. +# The sim will load all sections starting at the .text address and ignore +# the addresses for the other sections. +_pass: + .asciz "pass\n" +_fail: + .asciz "fail\n" +.global _start +_start: + .endm diff --git a/sim/testsuite/mcore/ChangeLog b/sim/testsuite/mcore/ChangeLog new file mode 100644 index 0000000..b0e7908 --- /dev/null +++ b/sim/testsuite/mcore/ChangeLog @@ -0,0 +1,8 @@ +2015-11-15 Mike Frysinger + + * fail.s: New test. + * testutils.inc (fail): Fix exit code. + +2015-03-29 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/mcore/allinsn.exp b/sim/testsuite/mcore/allinsn.exp new file mode 100644 index 0000000..5921cfc --- /dev/null +++ b/sim/testsuite/mcore/allinsn.exp @@ -0,0 +1,15 @@ +# mcore simulator testsuite + +if [istarget mcore-*] { + # all machines + set all_machs "mcore" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/mcore/fail.s b/sim/testsuite/mcore/fail.s new file mode 100644 index 0000000..10e3b23 --- /dev/null +++ b/sim/testsuite/mcore/fail.s @@ -0,0 +1,8 @@ +# check that the sim doesn't die immediately. +# mach: mcore +# xerror: + +.include "testutils.inc" + + start + fail diff --git a/sim/testsuite/mcore/pass.s b/sim/testsuite/mcore/pass.s new file mode 100644 index 0000000..92fada0 --- /dev/null +++ b/sim/testsuite/mcore/pass.s @@ -0,0 +1,7 @@ +# check that the sim doesn't die immediately. +# mach: mcore + +.include "testutils.inc" + + start + pass diff --git a/sim/testsuite/mcore/testutils.inc b/sim/testsuite/mcore/testutils.inc new file mode 100644 index 0000000..f5be06d --- /dev/null +++ b/sim/testsuite/mcore/testutils.inc @@ -0,0 +1,52 @@ +# MACRO: exit + .macro exit nr + movi r2, \nr + # The exit utility function. + .byte 0x00 + # The debug insn class. + .byte 0x50 + .endm + +# MACRO: pass +# Write 'pass' to stdout and quit + .macro pass + # Trap function 4: write(). + movi r1, 4; + # Use stdout. + movi r2, 1; + # Point to the string. + lrw r3, 1f; + # Number of bytes to write. + movi r4, 5; + # Trigger OS trap. + trap 1; + exit 0 + .data + 1: .asciz "pass\n" + .endm + +# MACRO: fail +# Write 'fail' to stdout and quit + .macro fail + # Trap function 4: write(). + movi r1, 4; + # Use stdout. + movi r2, 1; + # Point to the string. + lrw r3, 1f; + # Number of bytes to write. + movi r4, 5; + # Trigger OS trap. + trap 1; + exit 1 + .data + 1: .asciz "fail\n" + .endm + +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .text +.global _start +_start: + .endm diff --git a/sim/testsuite/microblaze/ChangeLog b/sim/testsuite/microblaze/ChangeLog new file mode 100644 index 0000000..2aa1f2c --- /dev/null +++ b/sim/testsuite/microblaze/ChangeLog @@ -0,0 +1,3 @@ +2015-03-29 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/microblaze/allinsn.exp b/sim/testsuite/microblaze/allinsn.exp new file mode 100644 index 0000000..f756914 --- /dev/null +++ b/sim/testsuite/microblaze/allinsn.exp @@ -0,0 +1,15 @@ +# microblaze simulator testsuite + +if [istarget microblaze-*] { + # all machines + set all_machs "microblaze" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/microblaze/pass.s b/sim/testsuite/microblaze/pass.s new file mode 100644 index 0000000..93ed924 --- /dev/null +++ b/sim/testsuite/microblaze/pass.s @@ -0,0 +1,8 @@ +# check that the sim doesn't die immediately. +# mach: microblaze +# output: + +.include "testutils.inc" + + start + pass diff --git a/sim/testsuite/microblaze/testutils.inc b/sim/testsuite/microblaze/testutils.inc new file mode 100644 index 0000000..158a3c5 --- /dev/null +++ b/sim/testsuite/microblaze/testutils.inc @@ -0,0 +1,29 @@ +# MACRO: exit + .macro exit nr + addi r3, r0, \nr; + bri 0; + .endm + +# MACRO: pass +# Write 'pass' to stdout and quit + .macro pass + exit 0 + .data + 1: .asciz "pass\n" + .endm + +# MACRO: fail +# Write 'fail' to stdout and quit + .macro fail + exit 1 + .data + 1: .asciz "fail\n" + .endm + +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .text +.global _start +_start: + .endm diff --git a/sim/testsuite/mips/ChangeLog b/sim/testsuite/mips/ChangeLog new file mode 100644 index 0000000..ea95441 --- /dev/null +++ b/sim/testsuite/mips/ChangeLog @@ -0,0 +1,118 @@ +2016-01-06 Joel Brobecker + + * hilo-hazard-4.s: Change copyright ownder to FSF. + +2015-09-25 Andrew Bennett + Ali Lown + + * basic.exp (run_micromips_test, run_sim_tests): New functions + Add support for micromips tests. + * hilo-hazard-4.s: New file. + * testutils.inc (_dowrite): Changed reserved instruction encoding. + (writemsg): Moved the la and li instructions before the data they are + assigned to, which prevents a bug where MIPS32 relocations are used + instead of micromips relocations when building for micromips. + +2015-04-13 Hans-Peter Nilsson + + * basic.exp: Don't unset target ldscript here. + +2011-01-06 Hans-Peter Nilsson + + * testutils.inc: Correct comment syntax fallout from + copyright update. + * utils-dsp.inc, utils-fpu.inc, utils-mdmx.inc: Ditto. + + * mips32-dsp.s: Update copyright year. + +2010-04-26 Mike Frysinger + + * basic.exp: Delete sim target check. + +2007-08-27 Joel Brobecker + + * testutils.inc: Change license to GPL version 3. + * utils-dsp.inc: Change license to GPL version 3. + * utils-fpu.inc: Change license to GPL version 3. + * utils-mdmx.inc: Change license to GPL version 3. + +2007-02-20 Thiemo Seufer + Chao-Ying Fu + * basic.exp: Run the dsp2 test. + * utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro. + * mips32-dsp2.s: New test. + +2007-02-17 Thiemo Seufer + + * basic.exp: Add case for mips*-sde-elf*. + (mdmxmodels): Run mdmx tests only on mdmx capable configurations. + +2007-02-13 Thiemo Seufer + + * mips32-dsp.s: Run DSP testcase only for release 2 architecture. + +2007-02-13 Thiemo Seufer + + * mdmx-ob.s: Delete extraneous include. + +2006-11-08 Thiemo Seufer + + * basic.exp: Fix spelling in comment. Use canonical form of target + patterns. Run DSP test only for DSP-capable ISAs. Check also mips32r2 + and mips64r2 if supported by the target. + +2006-08-08 Chris Dearman + + * testutils.inc (setup): __start is also a valid start symbol. + +2006-05-15 Chao-ying Fu + + * mips32-dsp.s: Add some tests for shra_r.ph, shrav_r.ph, shra_r.w, + shrav_r.w. + +2005-12-14 Chao-ying Fu + + * basic.exp: Run the dsp test. + * utils-dsp.inc: New file. + * mips32-dsp.s: New test. + +2004-04-11 Chris Demetriou + + * utils-fpu.inc (enable_fpu, ckm_fp_cc): New macros. + (clrset_fp_cc): Fix mask used for upper 7 condition codes. + * utils-mdmx.inc: Include utils-fpu.inc. + (enable_mdmx): Use enable_fpu. + +2004-04-10 Chris Demetriou + + * utils-fpu.inc: New file. + * utils-mdmx.inc: New file. + * mdmx-ob.s: New file. + * mdmx-ob-sb1.s: New file. + * basic.exp: Run new mdmx-ob and mdmx-ob-sb1 tests. + +2004-04-10 Chris Demetriou + + * fpu64-ps-sb1.s: New file. + * basic.exp: Recognize mipsisa64sb1 targets, and run fpu64-ps-sb1.s + if appropriate. + +2004-04-10 Chris Demetriou + + * fpu64-ps.s: New file. + * basic.exp: Run fpu64-ps.s. + +2004-03-29 Richard Sandiford + + * hilo-hazard-[123].s: New files. + * basic.exp (run_hilo_test): New procedure. + (models): Only list models that are included in the configuration. + (submodels): New variable, set to submodels of the above. + (mips64vr-*-elf, mips64vrel-*-elf): New configuration stanza. + Run hilo-hazard-[123].s. + +2004-01-26 Chris Demetriou + + * basic.exp: New file. + * testutils.inc: New file. + * sanity.s: New file. diff --git a/sim/testsuite/mips/basic.exp b/sim/testsuite/mips/basic.exp new file mode 100644 index 0000000..f810741 --- /dev/null +++ b/sim/testsuite/mips/basic.exp @@ -0,0 +1,106 @@ +# MIPS simulator instruction tests + +# Do "run_sim_test TESTFILE MODELS" for each combination of the +# mf{lo,hi} -> mult/div/mt{lo,hi} hazard described in mips.igen. +# Insert NOPS nops after the mflo or mfhi. +proc run_hilo_test {testfile models nops} { + foreach reg {lo hi} { + foreach insn "{mult\t\$4,\$4} {div\t\$0,\$4,\$4} {mt$reg\t\$4}" { + set contents "" + append contents "\t.macro hilo\n" + append contents "\tmf$reg\t\$4\n" + append contents "\t.rept\t$nops\n" + append contents "\tnop\n" + append contents "\t.endr\n" + append contents "\t$insn\n" + append contents "\t.endm" + + verbose -log "HILO test:\n$contents" + set file [open hilo-hazard.inc w] + puts $file $contents + close $file + + run_sim_test $testfile $models + } + } +} + +# Runs micromips tests by adding -mmicromips to as options +proc run_micromips_test { name requested_machs } { + global global_as_options; + set gas_old $global_as_options; + append global_as_options " -mmicromips " + run_sim_test $name $requested_machs + set global_as_options $gas_old +} + +# Runs all specified tests +proc run_sim_tests { name requested_machs { requested_micromips_machs "" } } { + run_sim_test $name $requested_machs + run_micromips_test $name $requested_micromips_machs +} + +# Only test mips*-*-elf (e.g., no mips*-*-linux) +if {[istarget mips*-*-elf]} { + + set dspmodels "" + set mdmxmodels "" + set micromipsmodels "" + set micromipsdspmodels "" + + if {[istarget mipsisa64sb1*-*-elf]} { + set models "sb1" + set submodels "mips1 mips2 mips3 mips4 mips32 mips64" + append mdmxmodels " mips64" + } elseif {[istarget mipsisa64*-*-elf]} { + set models "mips32 mips64 mips32r2 mips64r2" + set submodels "mips1 mips2 mips3 mips4" + append dspmodels " mips32r2 mips64r2" + append mdmxmodels " mips64 mips32r2 mips64r2" + } elseif {[istarget mips*-sde-elf*] || [istarget mips*-mti-elf*]} { + set models "mips32 mips64 mips32r2 mips64r2" + set submodels "" + append dspmodels " mips32r2 mips64r2" + append mdmxmodels " mips64 mips32r2 mips64r2" + append micromipsmodels " mips32r2" + append micromipsdspmodels " mips32r2 mips64r2" + } elseif {[istarget mipsisa32*-*-elf]} { + set models "mips32 mips32r2" + set submodels "mips1 mips2" + append dspmodels " mips32r2" + append mdmxmodels " mips32r2" + append micromipsmodels " mips32r2" + append micromipsdspmodels " mips32r2" + } elseif {[istarget mips64vr*-*-elf]} { + set models "vr4100 vr4111 vr4120 vr5000 vr5400 vr5500" + set submodels "mips1 mips2 mips3 mips4" + } elseif {[istarget mips64*-*-elf]} { + set models "mips3" + set submodels "mips1 mips2" + } else { + # fall back to just testing mips1 code. + set models "mips1" + set submodels "" + } + append submodels " " $models + set cpu_option -march + + run_sim_tests sanity.s $submodels $micromipsmodels + + foreach nops {0 1} { + run_hilo_test hilo-hazard-1.s $models $nops + run_hilo_test hilo-hazard-2.s $models $nops + } + run_hilo_test hilo-hazard-3.s $models 2 + run_hilo_test hilo-hazard-4.s $micromipsmodels 2 + + run_sim_test fpu64-ps.s $submodels + run_sim_test fpu64-ps-sb1.s $submodels + + run_sim_test mdmx-ob.s $mdmxmodels + run_sim_test mdmx-ob-sb1.s $mdmxmodels + + run_sim_tests mips32-dsp.s $dspmodels $micromipsdspmodels + run_sim_tests mips32-dsp2.s $dspmodels $micromipsdspmodels + +} diff --git a/sim/testsuite/mips/fpu64-ps-sb1.s b/sim/testsuite/mips/fpu64-ps-sb1.s new file mode 100644 index 0000000..a39d079 --- /dev/null +++ b/sim/testsuite/mips/fpu64-ps-sb1.s @@ -0,0 +1,72 @@ +# mips test sanity, expected to pass. +# mach: sb1 +# as: -mabi=eabi +# ld: -N -Ttext=0x80010000 +# output: *\\npass\\n + + .include "testutils.inc" + + .macro check_ps psval, upperval, lowerval + .set push + .set noreorder + cvt.s.pu $f0, \psval # upper + cvt.s.pl $f2, \psval # lower + li.s $f4, \upperval + li.s $f6, \lowerval + c.eq.s $fcc0, $f0, $f4 + bc1f $fcc0, _fail + c.eq.s $fcc0, $f2, $f6 + bc1f $fcc0, _fail + nop + .set pop + .endm + + setup + + .set noreorder + + .ent DIAG +DIAG: + + # make sure that Status.FR, .CU1, and .SBX are set. + mfc0 $2, $12 + or $2, $2, (1 << 26) | (1 << 29) | (1 << 16) + mtc0 $2, $12 + + + li.s $f10, 4.0 + li.s $f12, 16.0 + cvt.ps.s $f20, $f10, $f12 # $f20: u=4.0, l=16.0 + + li.s $f10, -1.0 + li.s $f12, 2.0 + cvt.ps.s $f22, $f10, $f12 # $f22: u=-1.0, l=2.0 + + + writemsg "div.ps" + + div.ps $f8, $f20, $f22 + check_ps $f8, -4.0, 8.0 + + + writemsg "recip.ps" + + recip.ps $f8, $f20 + check_ps $f8, 0.25, 0.0625 + + + writemsg "rsqrt.ps" + + rsqrt.ps $f8, $f20 + check_ps $f8, 0.5, 0.25 + + + writemsg "sqrt.ps" + + sqrt.ps $f8, $f20 + check_ps $f8, 2.0, 4.0 + + + pass + + .end DIAG diff --git a/sim/testsuite/mips/fpu64-ps.s b/sim/testsuite/mips/fpu64-ps.s new file mode 100644 index 0000000..ad493b8 --- /dev/null +++ b/sim/testsuite/mips/fpu64-ps.s @@ -0,0 +1,367 @@ +# mips test sanity, expected to pass. +# mach: mips64 sb1 +# as: -mabi=eabi +# ld: -N -Ttext=0x80010000 +# output: *\\npass\\n + + .include "testutils.inc" + + .macro check_ps psval, upperval, lowerval + .set push + .set noreorder + cvt.s.pu $f0, \psval # upper + cvt.s.pl $f2, \psval # lower + li.s $f4, \upperval + li.s $f6, \lowerval + c.eq.s $fcc0, $f0, $f4 + bc1f $fcc0, _fail + c.eq.s $fcc0, $f2, $f6 + bc1f $fcc0, _fail + nop + .set pop + .endm + + setup + + .set noreorder + + .ent DIAG +DIAG: + + # make sure that Status.FR and .CU1 are set. + mfc0 $2, $12 + or $2, $2, (1 << 26) | (1 << 29) + mtc0 $2, $12 + + + writemsg "ldc1" + + .data +1: .dword 0xc1a8000042200000 # -21.0, 40.0 + .text + la $2, 1b + ldc1 $f8, 0($2) + check_ps $f8, -21.0, 40.0 + + + writemsg "cvt.ps.s" + + li.s $f10, 1.0 + li.s $f12, 3.0 + cvt.ps.s $f8, $f10, $f12 # upper, lower + check_ps $f8, 1.0, 3.0 + + + writemsg "cvt.ps.s, sdc1, copy, ldc1" + + .data +1: .dword 0 + .dword 0 + .text + la $2, 1b + li.s $f12, -4.0 + li.s $f14, 32.0 + cvt.ps.s $f10, $f12, $f14 # upper, lower + sdc1 $f10, 8($2) + lw $3, 8($2) + lw $4, 12($2) + sw $3, 0($2) + sw $4, 4($2) + ldc1 $f8, 0($2) + check_ps $f8, -4.0, 32.0 + + + # Load some constants for later use + + li.s $f10, 4.0 + li.s $f12, 16.0 + cvt.ps.s $f20, $f10, $f12 # $f20: u=4.0, l=16.0 + + li.s $f10, -1.0 + li.s $f12, 2.0 + cvt.ps.s $f22, $f10, $f12 # $f22: u=-1.0, l=2.0 + + li.s $f10, 17.0 + li.s $f12, -8.0 + cvt.ps.s $f24, $f10, $f12 # $f24: u=17.0, l=-8.0 + + + writemsg "pll.ps" + + pll.ps $f8, $f20, $f22 + check_ps $f8, 16.0, 2.0 + + + writemsg "plu.ps" + + plu.ps $f8, $f20, $f22 + check_ps $f8, 16.0, -1.0 + + + writemsg "pul.ps" + + pul.ps $f8, $f20, $f22 + check_ps $f8, 4.0, 2.0 + + + writemsg "puu.ps" + + puu.ps $f8, $f20, $f22 + check_ps $f8, 4.0, -1.0 + + + writemsg "abs.ps" + + abs.ps $f8, $f22 + check_ps $f8, 1.0, 2.0 + + + writemsg "mov.ps" + + mov.ps $f8, $f22 + check_ps $f8, -1.0, 2.0 + + + writemsg "neg.ps" + + neg.ps $f8, $f22 + check_ps $f8, 1.0, -2.0 + + + writemsg "add.ps" + + add.ps $f8, $f20, $f22 + check_ps $f8, 3.0, 18.0 + + + writemsg "mul.ps" + + mul.ps $f8, $f20, $f22 + check_ps $f8, -4.0, 32.0 + + + writemsg "sub.ps" + + sub.ps $f8, $f20, $f22 + check_ps $f8, 5.0, 14.0 + + + writemsg "madd.ps" + + madd.ps $f8, $f24, $f20, $f22 + check_ps $f8, 13.0, 24.0 + + + writemsg "msub.ps" + + msub.ps $f8, $f24, $f20, $f22 + check_ps $f8, -21.0, 40.0 + + + writemsg "nmadd.ps" + + nmadd.ps $f8, $f24, $f20, $f22 + check_ps $f8, -13.0, -24.0 + + + writemsg "nmsub.ps" + + nmsub.ps $f8, $f24, $f20, $f22 + check_ps $f8, 21.0, -40.0 + + + writemsg "movn.ps (n)" + + li $2, 0 + mov.ps $f8, $f20 + movn.ps $f8, $f22, $2 # doesn't move + check_ps $f8, 4.0, 16.0 + + + writemsg "movn.ps (y)" + + li $2, 1 + mov.ps $f8, $f20 + movn.ps $f8, $f22, $2 # does move + check_ps $f8, -1.0, 2.0 + + + writemsg "movz.ps (y)" + + li $2, 0 + mov.ps $f8, $f20 + movz.ps $f8, $f22, $2 # does move + check_ps $f8, -1.0, 2.0 + + + writemsg "movz.ps (n)" + + li $2, 1 + mov.ps $f8, $f20 + movz.ps $f8, $f22, $2 # doesn't move + check_ps $f8, 4.0, 16.0 + + + writemsg "movf.ps (y,y)" + + cfc1 $2, $31 + or $2, $2, (1 << 23) | (1 << 25) + xor $2, $2, (1 << 23) | (1 << 25) + ctc1 $2, $31 # clear fcc0, clear fcc1 + mov.ps $f8, $f20 + movf.ps $f8, $f22, $fcc0 # moves both halves + check_ps $f8, -1.0, 2.0 + + + writemsg "movf.ps (y,n)" + + cfc1 $2, $31 + or $2, $2, (1 << 23) | (1 << 25) + xor $2, $2, (0 << 23) | (1 << 25) + ctc1 $2, $31 # set fcc0, clear fcc1 + mov.ps $f8, $f20 + movf.ps $f8, $f22, $fcc0 # moves upper half only + check_ps $f8, -1.0, 16.0 + + + writemsg "movf.ps (n,y)" + + cfc1 $2, $31 + or $2, $2, (1 << 23) | (1 << 25) + xor $2, $2, (1 << 23) | (0 << 25) + ctc1 $2, $31 # clear fcc0, set fcc1 + mov.ps $f8, $f20 + movf.ps $f8, $f22, $fcc0 # moves lower half only + check_ps $f8, 4.0, 2.0 + + + writemsg "movf.ps (n,n)" + + cfc1 $2, $31 + or $2, $2, (1 << 23) | (1 << 25) + xor $2, $2, (0 << 23) | (0 << 25) + ctc1 $2, $31 # set fcc0, set fcc1 + mov.ps $f8, $f20 + movf.ps $f8, $f22, $fcc0 # doesn't move either half + check_ps $f8, 4.0, 16.0 + + + writemsg "movt.ps (n,n)" + + cfc1 $2, $31 + or $2, $2, (1 << 23) | (1 << 25) + xor $2, $2, (1 << 23) | (1 << 25) + ctc1 $2, $31 # clear fcc0, clear fcc1 + mov.ps $f8, $f20 + movt.ps $f8, $f22, $fcc0 # doesn't move either half + check_ps $f8, 4.0, 16.0 + + + writemsg "movt.ps (n,y)" + + cfc1 $2, $31 + or $2, $2, (1 << 23) | (1 << 25) + xor $2, $2, (0 << 23) | (1 << 25) + ctc1 $2, $31 # set fcc0, clear fcc1 + mov.ps $f8, $f20 + movt.ps $f8, $f22, $fcc0 # moves lower half only + check_ps $f8, 4.0, 2.0 + + + writemsg "movt.ps (y,n)" + + cfc1 $2, $31 + or $2, $2, (1 << 23) | (1 << 25) + xor $2, $2, (1 << 23) | (0 << 25) + ctc1 $2, $31 # clear fcc0, set fcc1 + mov.ps $f8, $f20 + movt.ps $f8, $f22, $fcc0 # moves upper half only + check_ps $f8, -1.0, 16.0 + + + writemsg "movt.ps (y,y)" + + cfc1 $2, $31 + or $2, $2, (1 << 23) | (1 << 25) + xor $2, $2, (0 << 23) | (0 << 25) + ctc1 $2, $31 # set fcc0, set fcc1 + mov.ps $f8, $f20 + movt.ps $f8, $f22, $fcc0 # moves both halves + check_ps $f8, -1.0, 2.0 + + + writemsg "alnv.ps (aligned)" + + .data +1: .dword 0xc1a8000042200000 # -21.0, 40.0 + .dword 0xc228000041a00000 # -42.0, 20.0 + .text + la $2, 1b + li $3, 0 + addu $4, $3, 8 + luxc1 $f10, $3($2) + luxc1 $f12, $4($2) + alnv.ps $f8, $f10, $f12, $3 + check_ps $f8, -21.0, 40.0 + + + writemsg "alnv.ps (unaligned)" + + .data +1: .dword 0xc1a8000042200000 # -21.0, 40.0 + .dword 0xc228000041a00000 # -42.0, 20.0 + .hword 0x0001 + .text + la $2, 1b + li $3, 4 + addu $4, $3, 8 + luxc1 $f10, $3($2) + luxc1 $f12, $4($2) + alnv.ps $f8, $f10, $f12, $3 + + lb $5, 16($2) + bnez $5, 2f # little endian + nop + + # big endian + check_ps $f8, 40.0, -42.0 + b 3f + nop +2: + # little endian + check_ps $f8, 20.0, -21.0 +3: + + + # We test c.cond.ps only lightly, just to make sure it modifies + # two bits and compares the halves separately. Perhaps it should + # be tested more thoroughly. + + writemsg "c.f.ps" + + cfc1 $2, $31 + or $2, $2, (1 << 23) | (0x7f << 25) + ctc1 $2, $31 # set all fcc bits + c.f.ps $fcc0, $f8, $f8 # -> f, f + bc1t $fcc0, _fail + nop + bc1t $fcc1, _fail + nop + + + writemsg "c.olt.ps" + + cfc1 $2, $31 + or $2, $2, (1 << 23) | (0x7f << 25) + xor $2, $2, (1 << 23) | (0x7f << 25) + ctc1 $2, $31 # clear all fcc bits + c.lt.ps $fcc0, $f22, $f24 # -> f, t + bc1t $fcc0, _fail + nop + bc1f $fcc1, _fail + nop + + + pass + + .end DIAG diff --git a/sim/testsuite/mips/hilo-hazard-1.s b/sim/testsuite/mips/hilo-hazard-1.s new file mode 100644 index 0000000..f20c939 --- /dev/null +++ b/sim/testsuite/mips/hilo-hazard-1.s @@ -0,0 +1,19 @@ +# Test for architectures with mf{hi,lo} -> mult/div/mt{hi,lo} hazards. +# +# mach: mips1 mips2 mips3 mips4 vr4100 vr4111 vr4120 vr5000 vr5400 +# as: -mabi=eabi +# ld: -N -Ttext=0x80010000 +# output: HILO: * too close to MF at *\\n\\nprogram stopped*\\n +# xerror: + + .include "hilo-hazard.inc" + .include "testutils.inc" + + setup + + .set noreorder + .ent DIAG +DIAG: + hilo + pass + .end DIAG diff --git a/sim/testsuite/mips/hilo-hazard-2.s b/sim/testsuite/mips/hilo-hazard-2.s new file mode 100644 index 0000000..07b84d2 --- /dev/null +++ b/sim/testsuite/mips/hilo-hazard-2.s @@ -0,0 +1,18 @@ +# Test for architectures without mf{hi,lo} -> mult/div/mt{hi,lo} hazards. +# +# mach: vr5500 mips32 mips64 +# as: -mabi=eabi +# ld: -N -Ttext=0x80010000 +# output: pass\\n + + .include "hilo-hazard.inc" + .include "testutils.inc" + + setup + + .set noreorder + .ent DIAG +DIAG: + hilo + pass + .end DIAG diff --git a/sim/testsuite/mips/hilo-hazard-3.s b/sim/testsuite/mips/hilo-hazard-3.s new file mode 100644 index 0000000..1a0949d --- /dev/null +++ b/sim/testsuite/mips/hilo-hazard-3.s @@ -0,0 +1,18 @@ +# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween. +# +# mach: all +# as: -mabi=eabi +# ld: -N -Ttext=0x80010000 +# output: pass\\n + + .include "hilo-hazard.inc" + .include "testutils.inc" + + setup + + .set noreorder + .ent DIAG +DIAG: + hilo + pass + .end DIAG diff --git a/sim/testsuite/mips/hilo-hazard-4.s b/sim/testsuite/mips/hilo-hazard-4.s new file mode 100644 index 0000000..fc010f8 --- /dev/null +++ b/sim/testsuite/mips/hilo-hazard-4.s @@ -0,0 +1,36 @@ +# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween. +# +# mach: all +# as: -mabi=eabi -mmicromips +# ld: -N -Ttext=0x80010000 +# output: pass\\n + +# Copyright (C) 2013-2021 Free Software Foundation, Inc. +# Contributed by Andrew Bennett (andrew.bennett@imgtec.com) +# +# This file is part of the MIPS sim. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, see . + + .include "hilo-hazard.inc" + .include "testutils.inc" + + setup + + .set noreorder + .ent DIAG +DIAG: + hilo + pass + .end DIAG diff --git a/sim/testsuite/mips/mdmx-ob-sb1.s b/sim/testsuite/mips/mdmx-ob-sb1.s new file mode 100644 index 0000000..c8409fc --- /dev/null +++ b/sim/testsuite/mips/mdmx-ob-sb1.s @@ -0,0 +1,102 @@ +# MDMX .OB op tests. +# mach: sb1 +# as: -mabi=eabi +# ld: -N -Ttext=0x80010000 +# output: *\\npass\\n + + .include "testutils.inc" + .include "utils-mdmx.inc" + + setup + + .set noreorder + + .ent DIAG +DIAG: + + enable_mdmx + + # set Status.SBX to enable SB-1 extensions. + mfc0 $2, $12 + or $2, $2, (1 << 16) + mtc0 $2, $12 + + + ### + ### SB-1 Non-accumulator .ob format ops. + ### + ### Key: v = vector + ### ev = vector of single element + ### cv = vector of constant. + ### + + + writemsg "pavg.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + pavg.ob $f10, $f8, $f9 + ck_ob $f10, 0x3c4d5e6f8091a2b3 + + writemsg "pavg.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + pavg.ob $f10, $f8, $f9[6] + ck_ob $f10, 0x444d555e666f7780 + + writemsg "pavg.ob (cv)" + ld_ob $f8, 0x1122334455667788 + pavg.ob $f10, $f8, 0x10 + ck_ob $f10, 0x1119222a333b444c + + + writemsg "pabsdiff.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + pabsdiff.ob $f10, $f8, $f9 + ck_ob $f10, 0x5555555555555555 + + writemsg "pabsdiff.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + pabsdiff.ob $f10, $f8, $f9[7] + ck_ob $f10, 0x5544332211001122 + + writemsg "pabsdiff.ob (cv)" + ld_ob $f8, 0x0001020304050607 + pabsdiff.ob $f10, $f8, 0x04 + ck_ob $f10, 0x0403020100010203 + + + ### + ### SB-1 Accumulator .ob format ops + ### + ### Key: v = vector + ### ev = vector of single element + ### cv = vector of constant. + ### + + + writemsg "pabsdiffc.ob (v)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + pabsdiffc.ob $f8, $f9 + ck_acc_ob 0x0001020304050607, 0x0000000000000000, 0x5555555555555555 + + writemsg "pabsdiffc.ob (ev)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + pabsdiffc.ob $f8, $f9[7] + ck_acc_ob 0x0001020304050607, 0x0000000000000000, 0x5544332211001122 + + writemsg "pabsdiffc.ob (cv)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x0001020304050607 + pabsdiffc.ob $f8, 0x04 + ck_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0403020100010203 + + + pass + + .end DIAG diff --git a/sim/testsuite/mips/mdmx-ob.s b/sim/testsuite/mips/mdmx-ob.s new file mode 100644 index 0000000..23759ae --- /dev/null +++ b/sim/testsuite/mips/mdmx-ob.s @@ -0,0 +1,630 @@ +# MDMX .OB op tests. +# mach: mips64 sb1 +# as: -mabi=eabi +# as(mips64): -mabi=eabi -mdmx +# ld: -N -Ttext=0x80010000 +# output: *\\npass\\n + + .include "testutils.inc" + .include "utils-mdmx.inc" + + setup + + .set noreorder + + .ent DIAG +DIAG: + + enable_mdmx + + + ### + ### Non-accumulator, non-CC-using .ob format ops. + ### + ### Key: v = vector + ### ev = vector of single element + ### cv = vector of constant. + ### + + + writemsg "add.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + add.ob $f10, $f8, $f9 + ck_ob $f10, 0x7799bbddffffffff + + writemsg "add.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + add.ob $f10, $f8, $f9[6] + ck_ob $f10, 0x8899aabbccddeeff + + writemsg "add.ob (cv)" + ld_ob $f8, 0x1122334455667788 + add.ob $f10, $f8, 0x10 + ck_ob $f10, 0x2132435465768798 + + + writemsg "alni.ob" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + alni.ob $f10, $f8, $f9, 3 + ck_ob $f10, 0x4455667788667788 + + + writemsg "alnv.ob" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + li $4, 5 + alnv.ob $f10, $f8, $f9, $4 + ck_ob $f10, 0x66778866778899aa + + + writemsg "and.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + and.ob $f10, $f8, $f9 + ck_ob $f10, 0x0022000000224488 + + writemsg "and.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + and.ob $f10, $f8, $f9[4] + ck_ob $f10, 0x1100110011001188 + + writemsg "and.ob (cv)" + ld_ob $f8, 0x1122334455667788 + and.ob $f10, $f8, 0x1e + ck_ob $f10, 0x1002120414061608 + + + writemsg "max.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + max.ob $f10, $f8, $f9 + ck_ob $f10, 0x66778899aabbccdd + + writemsg "max.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + max.ob $f10, $f8, $f9[7] + ck_ob $f10, 0x6666666666667788 + + writemsg "max.ob (cv)" + ld_ob $f8, 0x1122334455667788 + max.ob $f10, $f8, 0x15 + ck_ob $f10, 0x1522334455667788 + + + writemsg "min.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + min.ob $f10, $f8, $f9 + ck_ob $f10, 0x1122334455667788 + + writemsg "min.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + min.ob $f10, $f8, $f9[7] + ck_ob $f10, 0x1122334455666666 + + writemsg "min.ob (cv)" + ld_ob $f8, 0x1122334455667788 + min.ob $f10, $f8, 0x15 + ck_ob $f10, 0x1115151515151515 + + + writemsg "mul.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x0001020304050607 + mul.ob $f10, $f8, $f9 + ck_ob $f10, 0x002266ccffffffff + + writemsg "mul.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x0001020304050607 + mul.ob $f10, $f8, $f9[4] + ck_ob $f10, 0x336699ccffffffff + + writemsg "mul.ob (cv)" + ld_ob $f8, 0x1122334455667788 + mul.ob $f10, $f8, 2 + ck_ob $f10, 0x22446688aacceeff + + + writemsg "nor.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + nor.ob $f10, $f8, $f9 + ck_ob $f10, 0x8888442200000022 + + writemsg "nor.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + nor.ob $f10, $f8, $f9[6] + ck_ob $f10, 0x8888888888888800 + + writemsg "nor.ob (cv)" + ld_ob $f8, 0x1122334455667788 + nor.ob $f10, $f8, 0x08 + ck_ob $f10, 0xe6d5c4b3a2918077 + + + writemsg "or.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + or.ob $f10, $f8, $f9 + ck_ob $f10, 0x7777bbddffffffdd + + writemsg "or.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + or.ob $f10, $f8, $f9[6] + ck_ob $f10, 0x77777777777777ff + + writemsg "or.ob (cv)" + ld_ob $f8, 0x1122334455667788 + or.ob $f10, $f8, 0x08 + ck_ob $f10, 0x192a3b4c5d6e7f88 + + + writemsg "shfl.mixh.ob" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + shfl.mixh.ob $f10, $f8, $f9 + ck_ob $f10, 0x1166227733884499 + + + writemsg "shfl.mixl.ob" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + shfl.mixl.ob $f10, $f8, $f9 + ck_ob $f10, 0x55aa66bb77cc88dd + + + writemsg "shfl.pach.ob" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + shfl.pach.ob $f10, $f8, $f9 + ck_ob $f10, 0x113355776688aacc + + + writemsg "shfl.upsl.ob" + ld_ob $f8, 0x1122334455667788 + shfl.upsl.ob $f10, $f8, $f8 + ck_ob $f10, 0x005500660077ff88 + + + writemsg "sll.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x0001020304050607 + sll.ob $f10, $f8, $f9 + ck_ob $f10, 0x1144cc2050c0c000 + + writemsg "sll.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x0001020304050607 + sll.ob $f10, $f8, $f9[3] + ck_ob $f10, 0x1020304050607080 + + writemsg "sll.ob (cv)" + ld_ob $f8, 0x1122334455667788 + sll.ob $f10, $f8, 1 + ck_ob $f10, 0x22446688aaccee10 + + + writemsg "srl.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x0001020304050607 + srl.ob $f10, $f8, $f9 + ck_ob $f10, 0x11110c0805030101 + + writemsg "srl.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x0001020304050607 + srl.ob $f10, $f8, $f9[3] + ck_ob $f10, 0x0102030405060708 + + writemsg "srl.ob (cv)" + ld_ob $f8, 0x1122334455667788 + srl.ob $f10, $f8, 1 + ck_ob $f10, 0x081119222a333b44 + + + writemsg "sub.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x0001020304050607 + sub.ob $f10, $f8, $f9 + ck_ob $f10, 0x1121314151617181 + + writemsg "sub.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + sub.ob $f10, $f8, $f9[7] + ck_ob $f10, 0x0000000000001122 + + writemsg "sub.ob (cv)" + ld_ob $f8, 0x1122334455667788 + sub.ob $f10, $f8, 0x10 + ck_ob $f10, 0x0112233445566778 + + + writemsg "xor.ob (v)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + xor.ob $f10, $f8, $f9 + ck_ob $f10, 0x7755bbddffddbb55 + + writemsg "xor.ob (ev)" + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + xor.ob $f10, $f8, $f9[6] + ck_ob $f10, 0x66554433221100ff + + writemsg "xor.ob (cv)" + ld_ob $f8, 0x1122334455667788 + xor.ob $f10, $f8, 0x08 + ck_ob $f10, 0x192a3b4c5d6e7f80 + + + ### + ### Accumulator .ob format ops (in order: rd/wr, math, scale/round) + ### + ### Key: v = vector + ### ev = vector of single element + ### cv = vector of constant. + ### + + + writemsg "wacl.ob / rac[hml].ob" + ld_ob $f8, 0x8001028304850687 + ld_ob $f9, 0x1011121314151617 + wacl.ob $f8, $f9 + ck_acc_ob 0xff0000ff00ff00ff, 0x8001028304850687, 0x1011121314151617 + + # Note: relies on data left in accumulator by previous test. + writemsg "wach.ob / rac[hml].ob" + ld_ob $f8, 0x2021222324252627 + wach.ob $f8 + ck_acc_ob 0x2021222324252627, 0x8001028304850687, 0x1011121314151617 + + + writemsg "adda.ob (v)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + adda.ob $f8, $f9 + ck_acc_ob 0x0001020304050607, 0x0000000000010101, 0x7799bbddff214365 + + writemsg "adda.ob (ev)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + adda.ob $f8, $f9[2] + ck_acc_ob 0x0001020304050607, 0x0000000001010101, 0xccddeeff10213243 + + writemsg "adda.ob (cv)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + adda.ob $f8, 0x1f + ck_acc_ob 0x0001020304050607, 0x0000000000000000, 0x30415263748596a7 + + + writemsg "addl.ob (v)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + addl.ob $f8, $f9 + ck_acc_ob 0x0000000000000000, 0x0000000000010101, 0x7799bbddff214365 + + writemsg "addl.ob (ev)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + addl.ob $f8, $f9[2] + ck_acc_ob 0x0000000000000000, 0x0000000001010101, 0xccddeeff10213243 + + writemsg "addl.ob (cv)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + addl.ob $f8, 0x1f + ck_acc_ob 0x0000000000000000, 0x0000000000000000, 0x30415263748596a7 + + + writemsg "mula.ob (v)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + mula.ob $f8, $f9 + ck_acc_ob 0x0001020304050607, 0x060f1b28384a5e75, 0xc6ce18a47282d468 + + writemsg "mula.ob (ev)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + mula.ob $f8, $f9[2] + ck_acc_ob 0x0001020304050607, 0x0c1825313e4a5663, 0x6bd641ac1782ed58 + + writemsg "mula.ob (cv)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + mula.ob $f8, 0x1f + ck_acc_ob 0x0001020304050607, 0x020406080a0c0e10, 0x0f1e2d3c4b5a6978 + + + writemsg "mull.ob (v)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + mull.ob $f8, $f9 + ck_acc_ob 0x0000000000000000, 0x060f1b28384a5e75, 0xc6ce18a47282d468 + + writemsg "mull.ob (ev)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + mull.ob $f8, $f9[2] + ck_acc_ob 0x0000000000000000, 0x0c1825313e4a5663, 0x6bd641ac1782ed58 + + writemsg "mull.ob (cv)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + mull.ob $f8, 0x1f + ck_acc_ob 0x0000000000000000, 0x020406080a0c0e10, 0x0f1e2d3c4b5a6978 + + + writemsg "muls.ob (v)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + muls.ob $f8, $f9 + ck_acc_ob 0xff00010203040506, 0xf9f0e4d7c7b5a18a, 0x3a32e85c8e7e2c98 + + writemsg "muls.ob (ev)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + muls.ob $f8, $f9[2] + ck_acc_ob 0xff00010203040506, 0xf3e7dacec1b5a99c, 0x952abf54e97e13a8 + + writemsg "muls.ob (cv)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + muls.ob $f8, 0x1f + ck_acc_ob 0xff00010203040506, 0xfdfbf9f7f5f3f1ef, 0xf1e2d3c4b5a69788 + + + writemsg "mulsl.ob (v)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + mulsl.ob $f8, $f9 + ck_acc_ob 0xffffffffffffffff, 0xf9f0e4d7c7b5a18a, 0x3a32e85c8e7e2c98 + + writemsg "mulsl.ob (ev)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + mulsl.ob $f8, $f9[2] + ck_acc_ob 0xffffffffffffffff, 0xf3e7dacec1b5a99c, 0x952abf54e97e13a8 + + writemsg "mulsl.ob (cv)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + mulsl.ob $f8, 0x1f + ck_acc_ob 0xffffffffffffffff, 0xfdfbf9f7f5f3f1ef, 0xf1e2d3c4b5a69788 + + + writemsg "suba.ob (v)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + suba.ob $f8, $f9 + ck_acc_ob 0xff00010203040506, 0xffffffffffffffff, 0xabababababababab + + writemsg "suba.ob (ev)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + suba.ob $f8, $f9[2] + ck_acc_ob 0xff00010203040506, 0xffffffffffffffff, 0x566778899aabbccd + + writemsg "suba.ob (cv)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + suba.ob $f8, 0x1f + ck_acc_ob 0xff01020304050607, 0xff00000000000000, 0xf203142536475869 + + + writemsg "subl.ob (v)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + subl.ob $f8, $f9 + ck_acc_ob 0xffffffffffffffff, 0xffffffffffffffff, 0xabababababababab + + writemsg "subl.ob (ev)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + ld_ob $f9, 0x66778899aabbccdd + subl.ob $f8, $f9[2] + ck_acc_ob 0xffffffffffffffff, 0xffffffffffffffff, 0x566778899aabbccd + + writemsg "subl.ob (cv)" + ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 + ld_ob $f8, 0x1122334455667788 + subl.ob $f8, 0x1f + ck_acc_ob 0xff00000000000000, 0xff00000000000000, 0xf203142536475869 + + + writemsg "rnau.ob (v)" + ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe + ld_ob $f8, 0x0001020304050607 + rnau.ob $f9, $f8 + ck_ob $f9, 0x4021110940201008 + + writemsg "rnau.ob (ev)" + ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe + ld_ob $f8, 0x0001020304050607 + rnau.ob $f9, $f8[4] + ck_ob $f9, 0x080809097f7f8080 + + writemsg "rnau.ob (cv)" + ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe + rnau.ob $f9, 2 + ck_ob $f9, 0x10111112feffffff + + + writemsg "rneu.ob (v)" + ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe + ld_ob $f8, 0x0001020304050607 + rneu.ob $f9, $f8 + ck_ob $f9, 0x4021110940201008 + + writemsg "rneu.ob (ev)" + ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe + ld_ob $f8, 0x0001020304050607 + rneu.ob $f9, $f8[4] + ck_ob $f9, 0x080808097f7f8080 + + writemsg "rneu.ob (cv)" + ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe + rneu.ob $f9, 2 + ck_ob $f9, 0x10101112fefeffff + + + writemsg "rzu.ob (v)" + ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe + ld_ob $f8, 0x0001020304050607 + rzu.ob $f9, $f8 + ck_ob $f9, 0x402111083f1f0f07 + + writemsg "rzu.ob (ev)" + ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe + ld_ob $f8, 0x0001020304050607 + rzu.ob $f9, $f8[4] + ck_ob $f9, 0x080808087f7f7f7f + + writemsg "rzu.ob (cv)" + ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe + rzu.ob $f9, 2 + ck_ob $f9, 0x10101111fefeffff + + + ### + ### CC-using .ob format ops. + ### + ### Key: v = vector + ### ev = vector of single element + ### cv = vector of constant. + ### + + + writemsg "c.eq.ob (v)" + ld_ob $f8, 0x0001010202030304 + ld_ob $f9, 0x0101020203030404 + clr_fp_cc 0xff + c.eq.ob $f8, $f9 + ck_fp_cc 0x55 + + writemsg "c.eq.ob (ev)" + ld_ob $f8, 0x0001010202030304 + ld_ob $f9, 0x0101020203030404 + clr_fp_cc 0xff + c.eq.ob $f8, $f9[5] + ck_fp_cc 0x18 + + writemsg "c.eq.ob (cv)" + ld_ob $f8, 0x0001010202030304 + clr_fp_cc 0xff + c.eq.ob $f8, 0x03 + ck_fp_cc 0x06 + + + writemsg "c.le.ob (v)" + ld_ob $f8, 0x0001010202030304 + ld_ob $f9, 0x0101020203030404 + clr_fp_cc 0xff + c.le.ob $f8, $f9 + ck_fp_cc 0xff + + writemsg "c.le.ob (ev)" + ld_ob $f8, 0x0001010202030304 + ld_ob $f9, 0x0101020203030404 + clr_fp_cc 0xff + c.le.ob $f8, $f9[5] + ck_fp_cc 0xf8 + + writemsg "c.le.ob (cv)" + ld_ob $f8, 0x0001010202030304 + clr_fp_cc 0xff + c.le.ob $f8, 0x03 + ck_fp_cc 0xfe + + + writemsg "c.lt.ob (v)" + ld_ob $f8, 0x0001010202030304 + ld_ob $f9, 0x0101020203030404 + clr_fp_cc 0xff + c.lt.ob $f8, $f9 + ck_fp_cc 0xaa + + writemsg "c.lt.ob (ev)" + ld_ob $f8, 0x0001010202030304 + ld_ob $f9, 0x0101020203030404 + clr_fp_cc 0xff + c.lt.ob $f8, $f9[5] + ck_fp_cc 0xe0 + + writemsg "c.lt.ob (cv)" + ld_ob $f8, 0x0001010202030304 + clr_fp_cc 0xff + c.lt.ob $f8, 0x03 + ck_fp_cc 0xf8 + + + writemsg "pickf.ob (v)" + ld_ob $f8, 0x0001020304050607 + ld_ob $f9, 0x08090a0b0c0d0e0f + clrset_fp_cc 0xff, 0xaa + pickf.ob $f10, $f8, $f9 + ck_ob $f10, 0x08010a030c050e07 + + writemsg "pickf.ob (ev)" + ld_ob $f8, 0x0001020304050607 + ld_ob $f9, 0x08090a0b0c0d0e0f + clrset_fp_cc 0xff, 0xaa + pickf.ob $f10, $f8, $f9[4] + ck_ob $f10, 0x0b010b030b050b07 + + writemsg "pickf.ob (cv)" + ld_ob $f8, 0x0001020304050607 + clrset_fp_cc 0xff, 0xaa + pickf.ob $f10, $f8, 0x10 + ck_ob $f10, 0x1001100310051007 + + + writemsg "pickt.ob (v)" + ld_ob $f8, 0x0001020304050607 + ld_ob $f9, 0x08090a0b0c0d0e0f + clrset_fp_cc 0xff, 0xaa + pickt.ob $f10, $f8, $f9 + ck_ob $f10, 0x0009020b040d060f + + writemsg "pickt.ob (ev)" + ld_ob $f8, 0x0001020304050607 + ld_ob $f9, 0x08090a0b0c0d0e0f + clrset_fp_cc 0xff, 0xaa + pickt.ob $f10, $f8, $f9[5] + ck_ob $f10, 0x000a020a040a060a + + writemsg "pickt.ob (cv)" + ld_ob $f8, 0x0001020304050607 + clrset_fp_cc 0xff, 0xaa + pickt.ob $f10, $f8, 0x10 + ck_ob $f10, 0x0010021004100610 + + + pass + + .end DIAG diff --git a/sim/testsuite/mips/mips32-dsp.s b/sim/testsuite/mips/mips32-dsp.s new file mode 100644 index 0000000..ade6bcf --- /dev/null +++ b/sim/testsuite/mips/mips32-dsp.s @@ -0,0 +1,787 @@ +# MIPS32 DSP ASE test +# mach: mips32r2 mips64r2 +#as: -mdsp +#ld: -N -Ttext=0x80010000 +#output: *\\npass\\n + +# Copyright (C) 2005-2021 Free Software Foundation, Inc. +# Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu. +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + + .include "testutils.inc" + .include "utils-dsp.inc" + + setup + + .set noreorder + + .ent DIAG +DIAG: + + writemsg "[1] Test addq.ph" + dspck_dstio addq.ph, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio addq.ph, 0x20002, 0x10001, 0x10001, 0x0, 0x0 + dspck_dstio addq.ph, 0xfffefffe, 0xffffffff, 0xffffffff, 0x0, 0x0 + dspck_dstio addq.ph, 0xffff0000, 0xffffffff, 0x1, 0x0, 0x0 + dspck_dstio addq.ph, 0x0, 0xffffffff, 0x10001, 0x0, 0x0 + + writemsg "[2] Test addq_s.ph" + dspck_dstio addq_s.ph, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio addq_s.ph, 0x20002, 0x10001, 0x10001, 0x0, 0x0 + dspck_dstio addq_s.ph, 0xfffefffe, 0xffffffff, 0xffffffff, 0x0, 0x0 + dspck_dstio addq_s.ph, 0xffff0000, 0xffffffff, 0x1, 0x0, 0x0 + dspck_dstio addq_s.ph, 0xffff0000, 0x1, 0xffffffff, 0x0, 0x0 + + writemsg "[3] Test addq_s.w" + dspck_dsti addq_s.w, 0x0, 0x0, 0x0, 0x0 + dspck_dstio addq_s.w, 0x2, 0x1, 0x1, 0x0, 0x0 + dspck_dstio addq_s.w, 0xfffffffe, 0xffffffff, 0xffffffff, 0x0, 0x0 + dspck_dstio addq_s.w, 0x0, 0xffffffff, 0x1, 0x0, 0x0 + dspck_dstio addq_s.w, 0xffff, 0xffffffff, 0x10000, 0x0, 0x0 + + writemsg "[4] Test addu.qb" + dspck_dstio addu.qb, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio addu.qb, 0x2040000, 0x102ff01, 0x10201ff, 0x0, 0x100000 + dspck_dstio addu.qb, 0xfe0001fe, 0x7f80ffff, 0x7f8002ff, 0x0, 0x100000 + dspck_dstio addu.qb, 0xffffffff, 0x10203, 0xfffefdfc, 0x0, 0x0 + dspck_dstio addu.qb, 0xffffffff, 0xfbfaf9f8, 0x4050607, 0x0, 0x0 + + writemsg "[5] Test addu_s.qb" + dspck_dstio addu_s.qb, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio addu_s.qb, 0x204ffff, 0x102ff01, 0x10201ff, 0x0, 0x100000 + dspck_dstio addu_s.qb, 0xfeffffff, 0x7f80ffff, 0x7f8002ff, 0x0, 0x100000 + dspck_dstio addu_s.qb, 0xffffffff, 0x10203, 0xfffefdfc, 0x0, 0x0 + dspck_dstio addu_s.qb, 0xffffffff, 0xfbfaf9f8, 0x4050607, 0x0, 0x0 + + writemsg "[6] Test subq.ph" + dspck_dstio subq.ph, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio subq.ph, 0x10001, 0x20002, 0x10001, 0x0, 0x0 + dspck_dstio subq.ph, 0x1ffff, 0x2fffe, 0x1ffff, 0x0, 0x0 + dspck_dstio subq.ph, 0x7fff0000, 0xfffe8000, 0x7fff8000, 0x0, 0x100000 + dspck_dstio subq.ph, 0x1ffff, 0x7fff8000, 0x7ffe8001, 0x0, 0x0 + + writemsg "[7] Test subq_s.ph" + dspck_dstio subq_s.ph, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio subq_s.ph, 0x10001, 0x20002, 0x10001, 0x0, 0x0 + dspck_dstio subq_s.ph, 0x1ffff, 0x2fffe, 0x1ffff, 0x0, 0x0 + dspck_dstio subq_s.ph, 0x0, 0x7fff8000, 0x7fff8000, 0x0, 0x0 + dspck_dstio subq_s.ph, 0x1ffff, 0x7fff8000, 0x7ffe8001, 0x0, 0x0 + + writemsg "[8] Test subq_s.w" + dspck_dsti subq_s.w, 0x0, 0x0, 0x0, 0x0 + dspck_dsti subq_s.w, 0x0, 0x7fffffff, 0x7fffffff, 0x0 + dspck_dstio subq_s.w, 0x7fffffff, 0x0, 0x80000000, 0x0, 0x100000 + dspck_dstio subq_s.w, 0x1, 0x2, 0x1, 0x0, 0x0 + dspck_dstio subq_s.w, 0xffffffff, 0xfffffffe, 0xffffffff, 0x0, 0x0 + + writemsg "[9] Test subu.qb" + dspck_dstio subu.qb, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio subu.qb, 0x4030201, 0x8060402, 0x4030201, 0x0, 0x0 + dspck_dstio subu.qb, 0xfcfdfeff, 0x4030201, 0x8060402, 0x0, 0x100000 + dspck_dstio subu.qb, 0x102ff01, 0x2040000, 0x10201ff, 0x0, 0x100000 + dspck_dstio subu.qb, 0x7f80ffff, 0xfe0001fe, 0x7f8002ff, 0x0, 0x100000 + + writemsg "[10] Test subu_s.qb" + dspck_dstio subu_s.qb, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio subu_s.qb, 0x4030201, 0x8060402, 0x4030201, 0x0, 0x0 + dspck_dstio subu_s.qb, 0x0, 0x4030201, 0x8060402, 0x0, 0x100000 + dspck_dstio subu_s.qb, 0x1020000, 0x2040000, 0x10201ff, 0x0, 0x100000 + dspck_dstio subu_s.qb, 0x7f000000, 0xfe0001fe, 0x7f8002ff, 0x0, 0x100000 + + writemsg "[11] Test addsc" + dspck_dstio addsc, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio addsc, 0x1000000, 0x84000000, 0x7d000000, 0x0, 0x2000 + dspck_dstio addsc, 0xf1000000, 0x74000000, 0x7d000000, 0x0, 0x0 + dspck_dstio addsc, 0x2, 0x1, 0x1, 0x0, 0x0 + dspck_dstio addsc, 0xffffffff, 0xfffffffe, 0x1, 0x0, 0x0 + + writemsg "[12] Test addwc" + dspck_dstio addwc, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio addwc, 0x2, 0x1, 0x1, 0x0, 0x0 + dspck_dstio addwc, 0x3, 0x1, 0x1, 0x2000, 0x2000 + dspck_dsti addwc, 0x1, 0xffffffff, 0x1, 0x2000 + dspck_dsti addwc, 0x11, 0xa, 0x6, 0x2000 + + writemsg "[13] Test modsub" + dspck_dstio modsub, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio modsub, 0x76, 0x78, 0x7802, 0x0, 0x0 + dspck_dstio modsub, 0x74, 0x76, 0x7802, 0x0, 0x0 + dspck_dstio modsub, 0x78, 0x0, 0x7802, 0x0, 0x0 + dspck_dstio modsub, 0xf9, 0xfc, 0xfe03, 0x0, 0x0 + + writemsg "[14] Test raddu.w.qb" + dspck_dsio raddu.w.qb, 0x0, 0x0, 0x0, 0x0 + dspck_dsio raddu.w.qb, 0x2, 0x1000100, 0x0, 0x0 + dspck_dsio raddu.w.qb, 0x4, 0x1010101, 0x0, 0x0 + dspck_dsio raddu.w.qb, 0x200, 0xff01ff01, 0x0, 0x0 + dspck_dsio raddu.w.qb, 0x3fc, 0xffffffff, 0x0, 0x0 + + writemsg "[15] Test absq_s.ph" + dspck_dsio absq_s.ph, 0x0, 0x0, 0x0, 0x0 + dspck_dsio absq_s.ph, 0x10001, 0xffffffff, 0x0, 0x0 + dspck_dsio absq_s.ph, 0x7fff7fff, 0x80008000, 0x0, 0x100000 + dspck_dsio absq_s.ph, 0x60000002, 0xa000fffe, 0x0, 0x0 + dspck_dsio absq_s.ph, 0x70000004, 0x9000fffc, 0x0, 0x0 + + writemsg "[16] Test absq_s.w" + dspck_dsio absq_s.w, 0x0, 0x0, 0x0, 0x0 + dspck_dsio absq_s.w, 0x1, 0xffffffff, 0x0, 0x0 + dspck_dsio absq_s.w, 0x7fffffff, 0x80000000, 0x0, 0x100000 + dspck_dsio absq_s.w, 0x40000001, 0xbfffffff, 0x0, 0x0 + dspck_dsio absq_s.w, 0x8000001, 0xf7ffffff, 0x0, 0x0 + + writemsg "[17] Test precrq.qb.ph" + dspck_dstio precrq.qb.ph, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio precrq.qb.ph, 0xff7f4020, 0xffff7fff, 0x40002000, 0x0, 0x0 + dspck_dstio precrq.qb.ph, 0xfeba7632, 0xfedcba98, 0x76543210, 0x0, 0x0 + dspck_dstio precrq.qb.ph, 0x7632feba, 0x76543210, 0xfedcba98, 0x0, 0x0 + dspck_dstio precrq.qb.ph, 0x14589cd, 0x1234567, 0x89abcdef, 0x0, 0x0 + + writemsg "[18] Test precrq.ph.w" + dspck_dstio precrq.ph.w, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio precrq.ph.w, 0xffff4000, 0xffff7fff, 0x40002000, 0x0, 0x0 + dspck_dstio precrq.ph.w, 0xfedc7654, 0xfedcba98, 0x76543210, 0x0, 0x0 + dspck_dstio precrq.ph.w, 0x7654fedc, 0x76543210, 0xfedcba98, 0x0, 0x0 + dspck_dstio precrq.ph.w, 0x12389ab, 0x1234567, 0x89abcdef, 0x0, 0x0 + + writemsg "[19] Test precrq_rs.ph.w" + dspck_dstio precrq_rs.ph.w, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio precrq_rs.ph.w, 0x7fff0000, 0x7fffffff, 0xffffffff, 0x0, 0x400000 + dspck_dstio precrq_rs.ph.w, 0x80008001, 0x80007fff, 0x8000ffff, 0x0, 0x0 + dspck_dstio precrq_rs.ph.w, 0xfedd7654, 0xfedcba98, 0x76543210, 0x0, 0x0 + dspck_dstio precrq_rs.ph.w, 0x7654fedd, 0x76543210, 0xfedcba98, 0x0, 0x0 + + writemsg "[20] Test precrqu_s.qb.ph" + dspck_dstio precrqu_s.qb.ph, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio precrqu_s.qb.ph, 0xff8040, 0xffff7fff, 0x40002000, 0x0, 0x400000 + dspck_dstio precrqu_s.qb.ph, 0xec64, 0xfedcba98, 0x76543210, 0x0, 0x400000 + dspck_dstio precrqu_s.qb.ph, 0xec640000, 0x76543210, 0xfedcba98, 0x0, 0x400000 + dspck_dstio precrqu_s.qb.ph, 0x28a0000, 0x1234567, 0x89abcdef, 0x0, 0x400000 + + writemsg "[21] Test preceq.w.phl" + dspck_dsio preceq.w.phl, 0x0, 0x0, 0x0, 0x0 + dspck_dsio preceq.w.phl, 0xffff0000, 0xffffffff, 0x0, 0x0 + dspck_dsio preceq.w.phl, 0x80000000, 0x80004000, 0x0, 0x0 + dspck_dsio preceq.w.phl, 0xc0010000, 0xc0012001, 0x0, 0x0 + dspck_dsio preceq.w.phl, 0x76540000, 0x76543210, 0x0, 0x0 + + writemsg "[22] Test preceq.w.phr" + dspck_dsio preceq.w.phr, 0x0, 0x0, 0x0, 0x0 + dspck_dsio preceq.w.phr, 0xffff0000, 0xffffffff, 0x0, 0x0 + dspck_dsio preceq.w.phr, 0x40000000, 0x80004000, 0x0, 0x0 + dspck_dsio preceq.w.phr, 0x20010000, 0xc0012001, 0x0, 0x0 + dspck_dsio preceq.w.phr, 0x32100000, 0x76543210, 0x0, 0x0 + + writemsg "[23] Test precequ.ph.qbl" + dspck_dsio precequ.ph.qbl, 0x0, 0x0, 0x0, 0x0 + dspck_dsio precequ.ph.qbl, 0x7f807f80, 0xffffffff, 0x0, 0x0 + dspck_dsio precequ.ph.qbl, 0x40000000, 0x80004000, 0x0, 0x0 + dspck_dsio precequ.ph.qbl, 0x60000080, 0xc0012001, 0x0, 0x0 + dspck_dsio precequ.ph.qbl, 0x3b002a00, 0x76543210, 0x0, 0x0 + + writemsg "[24] Test precequ.ph.qbr" + dspck_dsio precequ.ph.qbr, 0x0, 0x0, 0x0, 0x0 + dspck_dsio precequ.ph.qbr, 0x7f807f80, 0xffffffff, 0x0, 0x0 + dspck_dsio precequ.ph.qbr, 0x20000000, 0x80004000, 0x0, 0x0 + dspck_dsio precequ.ph.qbr, 0x10000080, 0xc0012001, 0x0, 0x0 + dspck_dsio precequ.ph.qbr, 0x19000800, 0x76543210, 0x0, 0x0 + + writemsg "[25] Test precequ.ph.qbla" + dspck_dsio precequ.ph.qbla, 0x0, 0x0, 0x0, 0x0 + dspck_dsio precequ.ph.qbla, 0x7f807f80, 0xffffffff, 0x0, 0x0 + dspck_dsio precequ.ph.qbla, 0x40002000, 0x80004000, 0x0, 0x0 + dspck_dsio precequ.ph.qbla, 0x60001000, 0xc0012001, 0x0, 0x0 + dspck_dsio precequ.ph.qbla, 0x3b001900, 0x76543210, 0x0, 0x0 + + writemsg "[26] Test precequ.ph.qbra" + dspck_dsio precequ.ph.qbra, 0x0, 0x0, 0x0, 0x0 + dspck_dsio precequ.ph.qbra, 0x7f807f80, 0xffffffff, 0x0, 0x0 + dspck_dsio precequ.ph.qbra, 0x0, 0x80004000, 0x0, 0x0 + dspck_dsio precequ.ph.qbra, 0x800080, 0xc0012001, 0x0, 0x0 + dspck_dsio precequ.ph.qbra, 0x2a000800, 0x76543210, 0x0, 0x0 + + writemsg "[27] Test preceu.ph.qbl" + dspck_dsio preceu.ph.qbl, 0x0, 0x0, 0x0, 0x0 + dspck_dsio preceu.ph.qbl, 0xff00ff, 0xffffffff, 0x0, 0x0 + dspck_dsio preceu.ph.qbl, 0x800000, 0x80004000, 0x0, 0x0 + dspck_dsio preceu.ph.qbl, 0xc00001, 0xc0012001, 0x0, 0x0 + dspck_dsio preceu.ph.qbl, 0x760054, 0x76543210, 0x0, 0x0 + + writemsg "[28] Test preceu.ph.qbr" + dspck_dsio preceu.ph.qbr, 0x0, 0x0, 0x0, 0x0 + dspck_dsio preceu.ph.qbr, 0xff00ff, 0xffffffff, 0x0, 0x0 + dspck_dsio preceu.ph.qbr, 0x400000, 0x80004000, 0x0, 0x0 + dspck_dsio preceu.ph.qbr, 0x200001, 0xc0012001, 0x0, 0x0 + dspck_dsio preceu.ph.qbr, 0x320010, 0x76543210, 0x0, 0x0 + + writemsg "[29] Test preceu.ph.qbla" + dspck_dsio preceu.ph.qbla, 0x0, 0x0, 0x0, 0x0 + dspck_dsio preceu.ph.qbla, 0xff00ff, 0xffffffff, 0x0, 0x0 + dspck_dsio preceu.ph.qbla, 0x800040, 0x80004000, 0x0, 0x0 + dspck_dsio preceu.ph.qbla, 0xc00020, 0xc0012001, 0x0, 0x0 + dspck_dsio preceu.ph.qbla, 0x760032, 0x76543210, 0x0, 0x0 + + writemsg "[30] Test preceu.ph.qbra" + dspck_dsio preceu.ph.qbra, 0x0, 0x0, 0x0, 0x0 + dspck_dsio preceu.ph.qbra, 0xff00ff, 0xffffffff, 0x0, 0x0 + dspck_dsio preceu.ph.qbra, 0x0, 0x80004000, 0x0, 0x0 + dspck_dsio preceu.ph.qbra, 0x10001, 0xc0012001, 0x0, 0x0 + dspck_dsio preceu.ph.qbra, 0x540010, 0x76543210, 0x0, 0x0 + + writemsg "[31] Test shll.qb" + dspck_dtsaio shll.qb, 0x0, 0x0, 0, 0x0, 0x0 + dspck_dtsai shll.qb, 0x202fefe, 0x101ffff, 1, 0x0 + dspck_dtsai shll.qb, 0xfefe0002, 0x7fff8081, 1, 0x0 + dspck_dtsai shll.qb, 0xfcfc0020, 0x7fff8008, 2, 0x0 + dspck_dtsai shll.qb, 0x68b0d868, 0x6db6db6d, 3, 0x0 + + writemsg "[32] Test shllv.qb" + dspck_dstio shllv.qb, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dsti shllv.qb, 0x202fefe, 0x101ffff, 0x1, 0x0 + dspck_dsti shllv.qb, 0xfefe0002, 0x7fff8081, 0x1, 0x0 + dspck_dsti shllv.qb, 0xfcfc0020, 0x7fff8008, 0x2, 0x0 + dspck_dsti shllv.qb, 0x68b0d868, 0x6db6db6d, 0x3, 0x0 + + writemsg "[33] Test shll.ph" + dspck_dtsaio shll.ph, 0x0, 0x0, 0, 0x0, 0x0 + dspck_dtsaio shll.ph, 0x2fffe, 0x1ffff, 1, 0x0, 0x0 + dspck_dtsaio shll.ph, 0xfffe0000, 0x7fff8000, 1, 0x0, 0x400000 + dspck_dtsaio shll.ph, 0xfffc0020, 0x7fff8008, 2, 0x0, 0x400000 + dspck_dtsaio shll.ph, 0x6db0db68, 0x6db6db6d, 3, 0x0, 0x400000 + + writemsg "[34] Test shllv.ph" + dspck_dstio shllv.ph, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio shllv.ph, 0x2fffe, 0x1ffff, 0x1, 0x0, 0x0 + dspck_dstio shllv.ph, 0xfffe0000, 0x7fff8000, 0x1, 0x0, 0x400000 + dspck_dstio shllv.ph, 0xfffc0020, 0x7fff8008, 0x2, 0x0, 0x400000 + dspck_dstio shllv.ph, 0x6db0db68, 0x6db6db6d, 0x3, 0x0, 0x400000 + + writemsg "[35] Test shll_s.ph" + dspck_dtsaio shll_s.ph, 0x0, 0x0, 0, 0x0, 0x0 + dspck_dtsaio shll_s.ph, 0x2fffe, 0x1ffff, 1, 0x0, 0x0 + dspck_dtsaio shll_s.ph, 0x7fff8000, 0x7fff8000, 1, 0x0, 0x400000 + dspck_dtsaio shll_s.ph, 0x7fff8000, 0x7fff8008, 2, 0x0, 0x400000 + dspck_dtsaio shll_s.ph, 0x7fff8000, 0x6db6db6d, 3, 0x0, 0x400000 + + writemsg "[36] Test shllv_s.ph" + dspck_dstio shllv_s.ph, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio shllv_s.ph, 0x2fffe, 0x1ffff, 0x1, 0x0, 0x0 + dspck_dstio shllv_s.ph, 0x7fff8000, 0x7fff8000, 0x1, 0x0, 0x400000 + dspck_dstio shllv_s.ph, 0x7fff8000, 0x7fff8008, 0x2, 0x0, 0x400000 + dspck_dstio shllv_s.ph, 0x7fff8000, 0x6db6db6d, 0x3, 0x0, 0x400000 + + writemsg "[37] Test shll_s.w" + dspck_dtsaio shll_s.w, 0x0, 0x0, 0, 0x0, 0x0 + dspck_dtsaio shll_s.w, 0x3fffe, 0x1ffff, 1, 0x0, 0x0 + dspck_dtsaio shll_s.w, 0x7fffffff, 0x7fff8000, 1, 0x0, 0x400000 + dspck_dtsaio shll_s.w, 0x80000000, 0x80000000, 1, 0x0, 0x400000 + dspck_dtsaio shll_s.w, 0x7fffffff, 0x7fff8008, 2, 0x0, 0x400000 + + writemsg "[38] Test shllv_s.w" + dspck_dstio shllv_s.w, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio shllv_s.w, 0x3fffe, 0x1ffff, 0x1, 0x0, 0x0 + dspck_dstio shllv_s.w, 0x7fffffff, 0x7fff8000, 0x1, 0x0, 0x400000 + dspck_dstio shllv_s.w, 0x80000000, 0x80000000, 0x1, 0x0, 0x400000 + dspck_dstio shllv_s.w, 0x7fffffff, 0x7fff8008, 0x2, 0x0, 0x400000 + + writemsg "[39] Test shrl.qb" + dspck_dtsaio shrl.qb, 0x0, 0x0, 0, 0x0, 0x0 + dspck_dtsai shrl.qb, 0x7f7f, 0x101ffff, 1, 0x0 + dspck_dtsai shrl.qb, 0x3f7f4040, 0x7fff8081, 1, 0x0 + dspck_dtsai shrl.qb, 0x1f3f2002, 0x7fff8008, 2, 0x0 + dspck_dtsai shrl.qb, 0xd161b0d, 0x6db6db6d, 3, 0x0 + + writemsg "[40] Test shrlv.qb" + dspck_dstio shrlv.qb, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dsti shrlv.qb, 0x7f7f, 0x101ffff, 0x1, 0x0 + dspck_dsti shrlv.qb, 0x3f7f4040, 0x7fff8081, 0x1, 0x0 + dspck_dsti shrlv.qb, 0x1f3f2002, 0x7fff8008, 0x2, 0x0 + dspck_dsti shrlv.qb, 0xd161b0d, 0x6db6db6d, 0x3, 0x0 + + writemsg "[41] Test shra.ph" + dspck_dtsaio shra.ph, 0x10001, 0x20002, 1, 0x0, 0x0 + dspck_dtsaio shra.ph, 0x10006, 0x10106f6f, 12, 0x0, 0x0 + dspck_dtsaio shra.ph, 0x1c000, 0x28000, 1, 0x0, 0x0 + dspck_dtsaio shra.ph, 0x2f800, 0x208000, 4, 0x0, 0x0 + dspck_dtsaio shra.ph, 0xfc01fc00, 0x80208000, 5, 0x0, 0x0 + + writemsg "[42] Test shrav.ph" + dspck_dstio shrav.ph, 0x10001, 0x20002, 0x1, 0x0, 0x0 + dspck_dstio shrav.ph, 0x10006, 0x10106f6f, 0xc, 0x0, 0x0 + dspck_dstio shrav.ph, 0x1c000, 0x28000, 0x1, 0x0, 0x0 + dspck_dstio shrav.ph, 0x2f800, 0x208000, 0x4, 0x0, 0x0 + dspck_dstio shrav.ph, 0xfc01fc00, 0x80208000, 0x5, 0x0, 0x0 + + writemsg "[43] Test shra_r.ph" + dspck_dtsaio shra_r.ph, 0x20001, 0x30002, 1, 0x0, 0x0 + dspck_dtsaio shra_r.ph, 0x10001, 0x20001, 1, 0x0, 0x0 + dspck_dtsaio shra_r.ph, 0x10001, 0x10001, 1, 0x0, 0x0 + dspck_dtsaio shra_r.ph, 0x0, 0x10001, 2, 0x0, 0x0 + dspck_dtsaio shra_r.ph, 0x7fff8000, 0x7fff8000, 0, 0x0, 0x0 + dspck_dtsaio shra_r.ph, 0x4000c000, 0x7fff8000, 1, 0x0, 0x0 + dspck_dtsaio shra_r.ph, 0x2000e000, 0x7ffe8000, 2, 0x0, 0x0 + + writemsg "[44] Test shrav_r.ph" + dspck_dstio shrav_r.ph, 0x20001, 0x30002, 0x1, 0x0, 0x0 + dspck_dstio shrav_r.ph, 0x10001, 0x20001, 0x1, 0x0, 0x0 + dspck_dstio shrav_r.ph, 0x10001, 0x10001, 0x1, 0x0, 0x0 + dspck_dstio shrav_r.ph, 0x0, 0x10001, 0x2, 0x0, 0x0 + dspck_dstio shrav_r.ph, 0x7fff8000, 0x7fff8000, 0, 0x0, 0x0 + dspck_dstio shrav_r.ph, 0x2000e000, 0x7fff8000, 2, 0x0, 0x0 + + writemsg "[45] Test shra_r.w" + dspck_dtsaio shra_r.w, 0x1, 0x2, 1, 0x0, 0x0 + dspck_dtsaio shra_r.w, 0xffff8000, 0x80000000, 16, 0x0, 0x0 + dspck_dtsaio shra_r.w, 0x8001, 0x10001, 1, 0x0, 0x0 + dspck_dtsaio shra_r.w, 0x1, 0x10001, 17, 0x0, 0x0 + dspck_dtsaio shra_r.w, 0xffffc001, 0x80010001, 17, 0x0, 0x0 + dspck_dtsaio shra_r.w, 0x7fffffff, 0x7fffffff, 0, 0x0, 0x0 + dspck_dtsaio shra_r.w, 0x40000000, 0x7fffffff, 1, 0x0, 0x0 + dspck_dtsaio shra_r.w, 0x20000000, 0x7ffffffe, 2, 0x0, 0x0 + + writemsg "[46] Test shrav_r.w" + dspck_dstio shrav_r.w, 0x1, 0x2, 0x1, 0x0, 0x0 + dspck_dstio shrav_r.w, 0xffff8000, 0x80000000, 0x10, 0x0, 0x0 + dspck_dstio shrav_r.w, 0x8001, 0x10001, 0x1, 0x0, 0x0 + dspck_dstio shrav_r.w, 0x8001, 0x10001, 0x21, 0x0, 0x0 + dspck_dstio shrav_r.w, 0x4000, 0x10001, 0x2, 0x0, 0x0 + dspck_dstio shrav_r.w, 0x7fffffff, 0x7fffffff, 0x0, 0x0, 0x0 + dspck_dstio shrav_r.w, 0x10000000, 0x7ffffffc, 0x3, 0x0, 0x0 + dspck_dstio shrav_r.w, 0x08000000, 0x7ffffff8, 0x4, 0x0, 0x0 + + writemsg "[47] Test muleu_s.ph.qbl" + dspck_dstio muleu_s.ph.qbl, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio muleu_s.ph.qbl, 0x0, 0x0, 0x40004000, 0x0, 0x0 + dspck_dstio muleu_s.ph.qbl, 0x0, 0xffffffff, 0x0, 0x0, 0x0 + dspck_dstio muleu_s.ph.qbl, 0x10001, 0x1010101, 0x10001, 0x0, 0x0 + dspck_dstio muleu_s.ph.qbl, 0x10000, 0x1000001, 0x10001, 0x0, 0x0 + + writemsg "[48] Test muleu_s.ph.qbr" + dspck_dstio muleu_s.ph.qbr, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio muleu_s.ph.qbr, 0x0, 0x0, 0x40004000, 0x0, 0x0 + dspck_dstio muleu_s.ph.qbr, 0x0, 0xffffffff, 0x0, 0x0, 0x0 + dspck_dstio muleu_s.ph.qbr, 0x10001, 0x1010101, 0x10001, 0x0, 0x0 + dspck_dstio muleu_s.ph.qbr, 0x1, 0x1000001, 0x10001, 0x0, 0x0 + + writemsg "[49] Test mulq_rs.ph" + dspck_dstio mulq_rs.ph, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio mulq_rs.ph, 0x0, 0x1, 0x1, 0x0, 0x0 + dspck_dstio mulq_rs.ph, 0x20000000, 0x40007fff, 0x40000000, 0x0, 0x0 + dspck_dstio mulq_rs.ph, 0x33330000, 0x66660000, 0x40007fff, 0x0, 0x0 + dspck_dstio mulq_rs.ph, 0xccd3332, 0x66666666, 0x10003fff, 0x0, 0x0 + + writemsg "[50] Test muleq_s.w.phl" + dspck_dstio muleq_s.w.phl, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio muleq_s.w.phl, 0x0, 0x0, 0x40004000, 0x0, 0x0 + dspck_dstio muleq_s.w.phl, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0 + dspck_dstio muleq_s.w.phl, 0x0, 0x0, 0xc000c000, 0x0, 0x0 + dspck_dstio muleq_s.w.phl, 0x0, 0x80008000, 0x0, 0x0, 0x0 + + writemsg "[51] Test muleq_s.w.phr" + dspck_dstio muleq_s.w.phr, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio muleq_s.w.phr, 0x0, 0x0, 0x40004000, 0x0, 0x0 + dspck_dstio muleq_s.w.phr, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0 + dspck_dstio muleq_s.w.phr, 0x0, 0x0, 0xc000c000, 0x0, 0x0 + dspck_dstio muleq_s.w.phr, 0x0, 0x80008000, 0x0, 0x0, 0x0 + + writemsg "[52] Test dpau.h.qbl" + dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0x1, 0x1010101, 0x1000001, 0x0, 0x0 + dspck_astio dpau.h.qbl, 0xffffffff, 0xffffffff, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0 + dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0 + dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0xff, 0xffff0001, 0x1ffff, 0x0, 0x0 + + writemsg "[53] Test dpau.h.qbr" + dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0x1, 0x1010101, 0x1000001, 0x0, 0x0 + dspck_astio dpau.h.qbr, 0xffffffff, 0xffffffff, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0 + dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0 + dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0xff, 0xffff0001, 0x1ffff, 0x0, 0x0 + + writemsg "[54] Test dpsu.h.qbl" + dspck_astio dpsu.h.qbl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio dpsu.h.qbl, 0x0, 0x1, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0 + dspck_astio dpsu.h.qbl, 0x0, 0x0, 0xffffffff, 0xffffffff, 0x1010101, 0x1000001, 0x0, 0x0 + dspck_astio dpsu.h.qbl, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0 + dspck_astio dpsu.h.qbl, 0x0, 0xff, 0x0, 0x0, 0xffff0001, 0x1ffff, 0x0, 0x0 + + writemsg "[55] Test dpsu.h.qbr" + dspck_astio dpsu.h.qbr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio dpsu.h.qbr, 0x0, 0x1, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0 + dspck_astio dpsu.h.qbr, 0x0, 0x0, 0xffffffff, 0xffffffff, 0x1010101, 0x1000001, 0x0, 0x0 + dspck_astio dpsu.h.qbr, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0 + dspck_astio dpsu.h.qbr, 0x0, 0xff, 0x0, 0x0, 0xffff0001, 0x1ffff, 0x0, 0x0 + + writemsg "[56] Test dpaq_s.w.ph" + dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0x0, 0xfffc0004, 0x7fff7fff, 0x7fff7fff, 0x0, 0x0 + dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0x0, 0xfffffffe, 0x80008000, 0x80008000, 0x0, 0xf0000 + dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0xffffffff, 0xa0000000, 0x40002000, 0x80008000, 0x0, 0x0 + dspck_astio dpaq_s.w.ph, 0xffffffff, 0xa0000000, 0xffffffff, 0x88000000, 0x10000800, 0x80008000, 0x0, 0x0 + + writemsg "[57] Test dpsq_s.w.ph" + dspck_astio dpsq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio dpsq_s.w.ph, 0x0, 0xfffc0004, 0x0, 0x0, 0x7fff7fff, 0x7fff7fff, 0x0, 0x0 + dspck_astio dpsq_s.w.ph, 0x0, 0xfffffffe, 0x0, 0x0, 0x80008000, 0x80008000, 0x0, 0xf0000 + dspck_astio dpsq_s.w.ph, 0xffffffff, 0xa0000000, 0x0, 0x0, 0x40002000, 0x80008000, 0x0, 0x0 + dspck_astio dpsq_s.w.ph, 0xffffffff, 0x88000000, 0xffffffff, 0xa0000000, 0x10000800, 0x80008000, 0x0, 0x0 + + writemsg "[58] Test mulsaq_s.w.ph" + dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x4000, 0xc0000000, 0x0, 0x0 + dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0xffffffff, 0x60010000, 0x80004000, 0x7fff4000, 0x0, 0x0 + dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0x0, 0x5fffffff, 0x80004000, 0x80004000, 0x0, 0xf0000 + dspck_astio mulsaq_s.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0xfffc0003, 0x7fff8001, 0x7fff7fff, 0x0, 0x0 + + writemsg "[59] Test dpaq_sa.l.w" + dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0x7ffffffe, 0x2, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0x7fffffff, 0xffffffff, 0x80000000, 0x80000000, 0x0, 0xf0000 + dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0xc0000000, 0x80000000, 0xc0000000, 0x7fffffff, 0x0, 0x0 + dspck_astio dpaq_sa.l.w, 0x20000000, 0x0, 0x0, 0x40000000, 0xe0000000, 0x7fffffff, 0x0, 0x0 + + writemsg "[60] Test dpsq_sa.l.w" + dspck_astio dpsq_sa.l.w, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio dpsq_sa.l.w, 0x7fffffff, 0xffffffff, 0x0, 0x0, 0x80000000, 0x80000000, 0x0, 0xf0000 + dspck_astio dpsq_sa.l.w, 0x80000000, 0x0, 0x80000000, 0x0, 0x80000000, 0x80000000, 0x0, 0xf0000 + dspck_astio dpsq_sa.l.w, 0x0, 0x0, 0x80000000, 0x1, 0x80000000, 0x80000000, 0x0, 0xf0000 + dspck_astio dpsq_sa.l.w, 0x0, 0x0, 0x3fffffff, 0x80000000, 0xc0000000, 0x7fffffff, 0x0, 0x0 + + writemsg "[61] Test maq_s.w.phl" + dspck_astio maq_s.w.phl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio maq_s.w.phl, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x0, 0x40004000, 0x0, 0x0 + dspck_astio maq_s.w.phl, 0x0, 0xffffffff, 0x0, 0xffffffff, 0x7fff7fff, 0x0, 0x0, 0x0 + dspck_astio maq_s.w.phl, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0 + dspck_astio maq_s.w.phl, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000, 0x0, 0x0 + + writemsg "[62] Test maq_s.w.phr" + dspck_astio maq_s.w.phr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio maq_s.w.phr, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x0, 0x40004000, 0x0, 0x0 + dspck_astio maq_s.w.phr, 0x0, 0xffffffff, 0x0, 0xffffffff, 0x7fff7fff, 0x0, 0x0, 0x0 + dspck_astio maq_s.w.phr, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0 + dspck_astio maq_s.w.phr, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000, 0x0, 0x0 + + writemsg "[63] Test maq_sa.w.phl" + dspck_astio maq_sa.w.phl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio maq_sa.w.phl, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0, 0x40004000, 0x0, 0x0 + dspck_astio maq_sa.w.phl, 0x0, 0x7fffffff, 0x0, 0x7fffffff, 0x7fff7fff, 0x0, 0x0, 0x0 + dspck_astio maq_sa.w.phl, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7fff7fff, 0x0, 0x0, 0x0 + dspck_astio maq_sa.w.phl, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000, 0x0, 0x0 + + writemsg "[64] Test maq_sa.w.phr" + dspck_astio maq_sa.w.phr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_astio maq_sa.w.phr, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0, 0x40004000, 0x0, 0x0 + dspck_astio maq_sa.w.phr, 0x0, 0x7fffffff, 0x0, 0x7fffffff, 0x7fff7fff, 0x0, 0x0, 0x0 + dspck_astio maq_sa.w.phr, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7fff7fff, 0x0, 0x0, 0x0 + dspck_astio maq_sa.w.phr, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000, 0x0, 0x0 + + writemsg "[65] Test bitrev" + dspck_dsio bitrev, 0x0, 0x0, 0x0, 0x0 + dspck_dsio bitrev, 0x1, 0x8000, 0x0, 0x0 + dspck_dsio bitrev, 0x8000, 0x1, 0x0, 0x0 + dspck_dsio bitrev, 0xc0c0, 0x1010303, 0x0, 0x0 + dspck_dsio bitrev, 0x1, 0xffff8000, 0x0, 0x0 + + writemsg "[66] Test insv" + dspck_tsi insv, 0xf0caf0f0, 0xf0f0f0f0, 0xa5a5a5a5, 0x311 + dspck_tsi insv, 0x7fffffe, 0x0, 0x7ffffff, 0xd01 + dspck_tsi insv, 0x3fff, 0x0, 0x3fff, 0x700 + dspck_tsi insv, 0xf0f2f0f0, 0xf0f0f0f0, 0xa5a5a5a5, 0x28f + dspck_tsi insv, 0x3fc, 0x0, 0x3ff, 0x402 + + writemsg "[67] Test repl.qb" + dspck_dIio repl.qb, 0x0, 0, 0x0, 0x0 + dspck_dIio repl.qb, 0x1010101, 1, 0x0, 0x0 + dspck_dIio repl.qb, 0xffffffff, 255, 0x0, 0x0 + dspck_dIio repl.qb, 0x7f7f7f7f, 127, 0x0, 0x0 + dspck_dIio repl.qb, 0xfefefefe, 254, 0x0, 0x0 + + writemsg "[68] Test replv.qb" + dspck_dsio replv.qb, 0x0, 0x0, 0x0, 0x0 + dspck_dsio replv.qb, 0x1010101, 0x1, 0x0, 0x0 + dspck_dsio replv.qb, 0xffffffff, 0xff, 0x0, 0x0 + dspck_dsio replv.qb, 0x7f7f7f7f, 0x37f, 0x0, 0x0 + dspck_dsio replv.qb, 0xfefefefe, 0xfffffffe, 0x0, 0x0 + + writemsg "[69] Test repl.ph" + dspck_dIio repl.ph, 0x0, 0, 0x0, 0x0 + dspck_dIio repl.ph, 0x10001, 1, 0x0, 0x0 + dspck_dIio repl.ph, 0xffffffff, -1, 0x0, 0x0 + dspck_dIio repl.ph, 0xff7fff7f, -129, 0x0, 0x0 + dspck_dIio repl.ph, 0xfffefffe, -2, 0x0, 0x0 + + writemsg "[70] Test replv.ph" + dspck_dsio replv.ph, 0x0, 0x0, 0x0, 0x0 + dspck_dsio replv.ph, 0x10001, 0x1, 0x0, 0x0 + dspck_dsio replv.ph, 0xffffffff, 0x5555ffff, 0x0, 0x0 + dspck_dsio replv.ph, 0x37f037f, 0x37f, 0x0, 0x0 + dspck_dsio replv.ph, 0xfffefffe, 0xfffffffe, 0x0, 0x0 + + writemsg "[71] Test cmpu.eq.qb" + dspck_stio cmpu.eq.qb, 0x0, 0x0, 0x0, 0xf000000 + dspck_stio cmpu.eq.qb, 0xffffffff, 0x0, 0x0, 0x0 + dspck_stio cmpu.eq.qb, 0x0, 0xffffffff, 0x0, 0x0 + dspck_stio cmpu.eq.qb, 0x10203, 0x4050607, 0x0, 0x0 + dspck_stio cmpu.eq.qb, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0 + + writemsg "[72] Test cmpu.lt.qb" + dspck_stio cmpu.lt.qb, 0x0, 0x0, 0x0, 0x0 + dspck_stio cmpu.lt.qb, 0xffffffff, 0x0, 0x0, 0x0 + dspck_stio cmpu.lt.qb, 0x0, 0xffffffff, 0x0, 0xf000000 + dspck_stio cmpu.lt.qb, 0x10203, 0x4050607, 0x0, 0xf000000 + dspck_stio cmpu.lt.qb, 0x8090a0b, 0xc0d0e0f, 0x0, 0xf000000 + + writemsg "[73] Test cmpu.le.qb" + dspck_stio cmpu.le.qb, 0x0, 0x0, 0x0, 0xf000000 + dspck_stio cmpu.le.qb, 0xffffffff, 0x0, 0x0, 0x0 + dspck_stio cmpu.le.qb, 0x0, 0xffffffff, 0x0, 0xf000000 + dspck_stio cmpu.le.qb, 0x10203, 0x4050607, 0x0, 0xf000000 + dspck_stio cmpu.le.qb, 0x8090a0b, 0xc0d0e0f, 0x0, 0xf000000 + + writemsg "[74] Test cmpgu.eq.qb" + dspck_dstio cmpgu.eq.qb, 0xf, 0x0, 0x0, 0x0, 0x0 + dspck_dstio cmpgu.eq.qb, 0x0, 0xffffffff, 0x0, 0x0, 0x0 + dspck_dstio cmpgu.eq.qb, 0x0, 0x0, 0xffffffff, 0x0, 0x0 + dspck_dstio cmpgu.eq.qb, 0x0, 0x10203, 0x4050607, 0x0, 0x0 + dspck_dstio cmpgu.eq.qb, 0x0, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0 + + writemsg "[75] Test cmpgu.lt.qb" + dspck_dstio cmpgu.lt.qb, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_dstio cmpgu.lt.qb, 0x0, 0xffffffff, 0x0, 0x0, 0x0 + dspck_dstio cmpgu.lt.qb, 0xf, 0x0, 0xffffffff, 0x0, 0x0 + dspck_dstio cmpgu.lt.qb, 0xf, 0x10203, 0x4050607, 0x0, 0x0 + dspck_dstio cmpgu.lt.qb, 0xf, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0 + + writemsg "[76] Test cmpgu.le.qb" + dspck_dstio cmpgu.le.qb, 0xf, 0x0, 0x0, 0x0, 0x0 + dspck_dstio cmpgu.le.qb, 0x0, 0xffffffff, 0x0, 0x0, 0x0 + dspck_dstio cmpgu.le.qb, 0xf, 0x0, 0xffffffff, 0x0, 0x0 + dspck_dstio cmpgu.le.qb, 0xf, 0x10203, 0x4050607, 0x0, 0x0 + dspck_dstio cmpgu.le.qb, 0xf, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0 + + writemsg "[77] Test cmp.eq.ph" + dspck_stio cmp.eq.ph, 0x0, 0x0, 0x0, 0x3000000 + dspck_stio cmp.eq.ph, 0x0, 0xffffffff, 0x0, 0x0 + dspck_stio cmp.eq.ph, 0xffffffff, 0x0, 0x0, 0x0 + dspck_stio cmp.eq.ph, 0x7fff7fff, 0xffffffff, 0x0, 0x0 + dspck_stio cmp.eq.ph, 0x11112222, 0x33334444, 0x0, 0x0 + + writemsg "[78] Test cmp.lt.ph" + dspck_stio cmp.lt.ph, 0x0, 0x0, 0x0, 0x0 + dspck_stio cmp.lt.ph, 0x0, 0xffffffff, 0x0, 0x0 + dspck_stio cmp.lt.ph, 0xffffffff, 0x0, 0x0, 0x3000000 + dspck_stio cmp.lt.ph, 0x7fff7fff, 0xffffffff, 0x0, 0x0 + dspck_stio cmp.lt.ph, 0x11112222, 0x33334444, 0x0, 0x3000000 + + writemsg "[79] Test cmp.le.ph" + dspck_stio cmp.le.ph, 0x0, 0x0, 0x0, 0x3000000 + dspck_stio cmp.le.ph, 0x0, 0xffffffff, 0x0, 0x0 + dspck_stio cmp.le.ph, 0xffffffff, 0x0, 0x0, 0x3000000 + dspck_stio cmp.le.ph, 0x7fff7fff, 0xffffffff, 0x0, 0x0 + dspck_stio cmp.le.ph, 0x11112222, 0x33334444, 0x0, 0x3000000 + + writemsg "[80] Test pick.qb" + dspck_dsti pick.qb, 0x0, 0x0, 0x0, 0x0 + dspck_dsti pick.qb, 0x0, 0xffffffff, 0x0, 0x0 + dspck_dsti pick.qb, 0xffffffff, 0xffffffff, 0x0, 0xf000000 + dspck_dsti pick.qb, 0xff, 0xffffffff, 0x0, 0x1000000 + dspck_dsti pick.qb, 0xff00, 0xffffffff, 0x0, 0x2000000 + + writemsg "[81] Test pick.ph" + dspck_dsti pick.ph, 0x0, 0x0, 0x0, 0x0 + dspck_dsti pick.ph, 0x0, 0xffffffff, 0x0, 0x0 + dspck_dsti pick.ph, 0xffffffff, 0xffffffff, 0x0, 0x3000000 + dspck_dsti pick.ph, 0xffff, 0xffffffff, 0x0, 0x1000000 + dspck_dsti pick.ph, 0xffff0000, 0xffffffff, 0x0, 0x2000000 + + writemsg "[82] Test packrl.ph" + dspck_dstio packrl.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio packrl.ph, 0x0000ffff, 0x00000000, 0xffff0000, 0x0, 0x0 + dspck_dstio packrl.ph, 0x00000000, 0x00000000, 0x0000ffff, 0x0, 0x0 + dspck_dstio packrl.ph, 0x00005555, 0x00000000, 0x5555aaaa, 0x0, 0x0 + dspck_dstio packrl.ph, 0x0000aaaa, 0x00000000, 0xaaaa5555, 0x0, 0x0 + + writemsg "[83] Test extr.w" + dspck_atsaio extr.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 + dspck_atsaio extr.w, 0x7fffffff, 0xcbcdef01 0xffffffff, 0x1f, 0x0, 0x800000 + dspck_atsaio extr.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0 + dspck_atsaio extr.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 + dspck_atsaio extr.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0 + + writemsg "[84] Test extr_r.w" + dspck_atsaio extr_r.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 + dspck_atsaio extr_r.w, 0x7fffffff, 0xcbcdef01 0x0, 0x1f, 0x0, 0x800000 + dspck_atsaio extr_r.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0 + dspck_atsaio extr_r.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 + dspck_atsaio extr_r.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0 + + writemsg "[85] Test extr_rs.w" + dspck_atsaio extr_rs.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 + dspck_atsaio extr_rs.w, 0x7fffffff, 0xcbcdef01 0x7fffffff, 0x1f, 0x0, 0x800000 + dspck_atsaio extr_rs.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0 + dspck_atsaio extr_rs.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 + dspck_atsaio extr_rs.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0 + + writemsg "[86] Test extr_s.h" + dspck_atsaio extr_s.h, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 + dspck_atsaio extr_s.h, 0x7fffffff, 0xcbcdef01 0x7fff, 0x1f, 0x0, 0x800000 + dspck_atsaio extr_s.h, 0x3fffffff, 0x2bcdef01 0x7fff, 0x1f, 0x0, 0x800000 + dspck_atsaio extr_s.h, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 + dspck_atsaio extr_s.h, 0x0, 0xfffffffe 0x7fff, 0x1, 0x0, 0x800000 + + writemsg "[87] Test extrv_s.h" + dspck_atsio extrv_s.h, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 + dspck_atsio extrv_s.h, 0x7fffffff, 0xcbcdef01 0x7fff, 0x1f, 0x0, 0x800000 + dspck_atsio extrv_s.h, 0x3fffffff, 0x2bcdef01 0x7fff, 0x1f, 0x0, 0x800000 + dspck_atsio extrv_s.h, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 + dspck_atsio extrv_s.h, 0x0, 0xfffffffe 0x7fff, 0x1, 0x0, 0x800000 + + writemsg "[88] Test extrv.w" + dspck_atsio extrv.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 + dspck_atsio extrv.w, 0x7fffffff, 0xcbcdef01 0xffffffff, 0x1f, 0x0, 0x800000 + dspck_atsio extrv.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0 + dspck_atsio extrv.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 + dspck_atsio extrv.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0 + + writemsg "[89] Test extrv_r.w" + dspck_atsio extrv_r.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 + dspck_atsio extrv_r.w, 0x7fffffff, 0xcbcdef01 0x0, 0x1f, 0x0, 0x800000 + dspck_atsio extrv_r.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0 + dspck_atsio extrv_r.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 + dspck_atsio extrv_r.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0 + + writemsg "[90] Test extrv_rs.w" + dspck_atsio extrv_rs.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 + dspck_atsio extrv_rs.w, 0x7fffffff, 0xcbcdef01 0x7fffffff, 0x1f, 0x0, 0x800000 + dspck_atsio extrv_rs.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0 + dspck_atsio extrv_rs.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 + dspck_atsio extrv_rs.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0 + + writemsg "[91] Test extp" + dspck_tasiimom extp, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x0, 0x403f + dspck_tasiimom extp, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x4000 + dspck_tasiim extp, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f + dspck_tasiim extp, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f + + writemsg "[92] Test extpv" + dspck_tasimom extpv, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x0, 0x403f + dspck_tasimom extpv, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x4000 + dspck_tasim extpv, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f + dspck_tasim extpv, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f + + writemsg "[93] Test extpdp" + dspck_tasiimom extpdp, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x3f, 0x403f + dspck_tasiimom extpdp, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x4000 + dspck_tasiim extpdp, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f + dspck_tasiim extpdp, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f + + writemsg "[94] Test extpdpv" + dspck_tasimom extpdpv, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x3f, 0x403f + dspck_tasimom extpdpv, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x4000 + dspck_tasim extpdpv, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f + dspck_tasim extpdpv, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f + + writemsg "[95] Test shilo" + dspck_asaio shilo, 0x0, 0x0, 0x0, 0x0, 0, 0x0, 0x0 + dspck_asaio shilo, 0x1, 0x80000000, 0x1, 0x80000000, 0, 0x0, 0x0 + dspck_asaio shilo, 0x1, 0x80000000, 0x3, 0x0, -1, 0x0, 0x0 + dspck_asaio shilo, 0x1, 0x80000000, 0x6, 0x0, -2, 0x0, 0x0 + dspck_asaio shilo, 0x1, 0x80000000, 0x18, 0x0, -4, 0x0, 0x0 + + writemsg "[96] Test shilov" + dspck_asio shilov, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 + dspck_asio shilov, 0x1, 0x80000000, 0x1, 0x80000000, 0x0, 0x0, 0x0 + dspck_asio shilov, 0x1, 0x80000000, 0x3, 0x0, 0xffffffff, 0x0, 0x0 + dspck_asio shilov, 0x1, 0x80000000, 0x6, 0x0, 0xfffffffe, 0x0, 0x0 + dspck_asio shilov, 0x1, 0x80000000, 0x18, 0x0, 0xfffffffc, 0x0, 0x0 + + writemsg "[97] Test mthlip" + dspck_saio mthlip, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20 + dspck_saio mthlip, 0x0, 0x1, 0x1, 0x2, 0x2, 0x8, 0x28 + dspck_saio mthlip, 0xffffffff, 0xffff1234, 0xffff1234, 0xfffffffe, 0xfffffffe, 0x10, 0x30 + dspck_saio mthlip, 0xdeadbeef, 0x1234, 0x1234, 0xbeefdead, 0xbeefdead, 0x18, 0x38 + + writemsg "[98] Test wrdsp" + dspck_wrdsp 0x0, 0x0, 0x0, 0x0 + dspck_wrdsp 0x4000, 0x20, 0x0, 0x4000 + dspck_wrdsp 0xffffffff, 0x3f, 0x0, 0x0fff7fbf + dspck_wrdsp 0x3f, 0x1, 0x0, 0x3f + dspck_wrdsp 0x1f80, 0x2, 0x0, 0x1f80 + + writemsg "[99] Test rddsp" + dspck_rddsp 0x0, 0x0, 0x0 + dspck_rddsp 0x0, 0x0, 0xffffffff + dspck_rddsp 0x3f, 0x1, 0xffffffff + dspck_rddsp 0x1f80, 0x2, 0x0fff7fbf + dspck_rddsp 0x2000, 0x4, 0x0fff7fbf + + writemsg "[100] Test lbux" + .data +mydata: + .byte 0x12 + .byte 0x34 + .byte 0x56 + .byte 0x78 + .byte 0x9a + .byte 0xbc + .byte 0xde + .byte 0xf0 + .previous + dspck_load lbux, 0x12, 0x0, mydata + dspck_load lbux, 0x34, 0x1, mydata + dspck_load lbux, 0x56, 0x2, mydata + dspck_load lbux, 0x78, 0x3, mydata + dspck_load lbux, 0x9a, 0x4, mydata + dspck_load lbux, 0xbc, 0x5, mydata + dspck_load lbux, 0xde, 0x6, mydata + dspck_load lbux, 0xf0, 0x7, mydata + + writemsg "[101] Test lhx" + .data +myhdata: + .hword 0x1234 + .hword 0x5678 + .hword 0x9abc + .hword 0xdef0 + .previous + dspck_load lhx, 0x1234, 0x0, myhdata + dspck_load lhx, 0x5678, 0x2, myhdata + dspck_load lhx, 0xffff9abc, 0x4, myhdata + dspck_load lhx, 0xffffdef0, 0x6, myhdata + + writemsg "[102] Test lwx" + .data +mywdata: + .word 0x12345678 + .word 0x9abcdef0 + .word 0x13579abc + .word 0xffff0001 + .previous + dspck_load lwx, 0x12345678, 0x0, mywdata + dspck_load lwx, 0x9abcdef0, 0x4, mywdata + dspck_load lwx, 0x13579abc, 0x8, mywdata + dspck_load lwx, 0xffff0001, 0xc, mywdata + + writemsg "[103] Test bposge32" + dspck_bposge32 0x0, 0 + dspck_bposge32 0x1f, 0 + dspck_bposge32 0x20, 1 + dspck_bposge32 0x3f, 1 + + pass + .end DIAG + diff --git a/sim/testsuite/mips/mips32-dsp2.s b/sim/testsuite/mips/mips32-dsp2.s new file mode 100644 index 0000000..8c8384e --- /dev/null +++ b/sim/testsuite/mips/mips32-dsp2.s @@ -0,0 +1,12360 @@ +# MIPS32 DSP REV 2 ASE test +# mach: mips32r2 mips64r2 +#as: -mdspr2 +#ld: -N -Ttext=0x80010000 +#output: *\\npass\\n + +# Copyright (C) 2006 MIPS Technologies, Inc. +# All rights reserved. +# Contributed by Chao-ying Fu (fu@mips.com). +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, see . + + .include "testutils.inc" + .include "utils-dsp.inc" + + setup + + .set noreorder + + .ent DIAG +DIAG: + + writemsg "[1] Test absq_s.qb" + dspck_dsio absq_s.qb, 0x40670106, 0xc099ff06, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x001c0205, 0x001c0205, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x000e0001, 0x000e00ff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01000101, 0x0100ff01, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x03000204, 0x030002fc, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x1d060400, 0xe3060400, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0019017f, 0x0019ff81, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00716e1d, 0x007192e3, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x77060003, 0x77060003, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x6100011a, 0x9f00ff1a, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x06017d00, 0x06ff8300, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x54010601, 0x54ff0601, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x10000101, 0xf000ffff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x6b7d0001, 0x6b8300ff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01550101, 0x0155ffff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x20014900, 0xe0ff4900, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00086000, 0x00f86000, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x72030102, 0x8efdff02, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00720079, 0x008e0087, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x1f496115, 0x1f499f15, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x10010000, 0x10ff0000, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x7f010700, 0x8001f900, 0x00000000, 0x00100000 + dspck_dsio absq_s.qb, 0x4141017e, 0x41bfff7e, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x6d3f0156, 0x6d3fffaa, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0103091f, 0x010309e1, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x010e400d, 0xff0e40f3, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01060101, 0xff06ff01, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x047f0240, 0xfc81fec0, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x78141d01, 0x7814e3ff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x25000000, 0xdb000000, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00040200, 0x00fc0200, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x003f0207, 0x003f0207, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x000d0140, 0x000dffc0, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x7100001e, 0x7100001e, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0101401a, 0xffffc01a, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x660e0025, 0x660e00db, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x021b0100, 0x021b0100, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00000f09, 0x00000f09, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x0100081c, 0xff00f81c, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x05000000, 0x05000000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x21661801, 0xdf661801, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x3f013c01, 0x3fff3cff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01010101, 0xffffff01, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00000103, 0x00000103, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01340004, 0xffcc0004, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01000104, 0x0100ff04, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x011f1011, 0xffe11011, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x08000001, 0x080000ff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x057f0200, 0x05810200, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0c660001, 0x0c660001, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x72011c20, 0x8eff1ce0, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x0d007803, 0x0d007803, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x4a020070, 0xb6020070, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x21083c0e, 0xdf083c0e, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x563e0105, 0xaa3eff05, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x013c000d, 0xff3c00f3, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01380104, 0xff380104, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x08006e35, 0x08009235, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x121b0100, 0x121bff00, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x79000301, 0x870003ff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x0512616b, 0x05129f6b, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x0c010700, 0x0cff0700, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x6e0e0016, 0x920e0016, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x4a011901, 0xb6ffe7ff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x02010902, 0x02fff702, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x393d0800, 0xc7c3f800, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00070000, 0x00070000, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00003400, 0x0000cc00, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x003c0000, 0x003c0000, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00000900, 0x0000f700, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01397f01, 0xffc780ff, 0x00000000, 0x00100000 + dspck_dsio absq_s.qb, 0x01000146, 0xff00ff46, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01030000, 0xff030000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x7f010119, 0x80ffffe7, 0x00000000, 0x00100000 + dspck_dsio absq_s.qb, 0x0f011c00, 0x0fff1c00, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01491f0e, 0xff491f0e, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00013e03, 0x00013e03, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x24000101, 0x2400ffff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x000e3d00, 0x000e3d00, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00003d01, 0x00003d01, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x4a031100, 0xb603ef00, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x0104026e, 0xfffc0292, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00200d01, 0x0020f3ff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01133001, 0x011330ff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x21710261, 0x218f029f, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x7b030300, 0x7b030300, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x30007801, 0x30007801, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x016e0104, 0xff92fffc, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x31014024, 0xcfff4024, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x03790457, 0x03870457, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00010200, 0x00ff0200, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00081c01, 0x00081cff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x40011d61, 0x40ffe39f, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x7f406e41, 0x80c092bf, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x003d0001, 0x00c300ff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x031c0701, 0x031c07ff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0f1e0145, 0x0f1eff45, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x3d1f1307, 0xc31f1307, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x26010003, 0x26ff0003, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x003d5501, 0x00c35501, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x02707f04, 0x02708004, 0x00000000, 0x00100000 + dspck_dsio absq_s.qb, 0x35190139, 0x35e7ffc7, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x007e0101, 0x007eff01, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x7f33013e, 0x7f33ff3e, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x40004006, 0x4000c006, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00110100, 0x0011ff00, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x11300d0d, 0xef30f30d, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x15007f66, 0x15008066, 0x00000000, 0x00100000 + dspck_dsio absq_s.qb, 0x0c01041c, 0x0cff041c, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x02071800, 0x02071800, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x010b0100, 0xff0bff00, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01010201, 0x01ff0201, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00007f1f, 0x00007f1f, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x71011c00, 0x8f011c00, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01071667, 0xff071699, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00003f00, 0x0000c100, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x18010000, 0x18ff0000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x40013701, 0xc0ff37ff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x007f3e00, 0x00813e00, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x05000000, 0x05000000, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x0100215a, 0xff00df5a, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00010101, 0x000101ff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x0100046d, 0x0100046d, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00180604, 0x00180604, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x1a01070f, 0x1aff070f, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0205011e, 0x0205ff1e, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01000255, 0xff000255, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x66030030, 0x66030030, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x3e3f2406, 0x3e3f2406, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00330000, 0x00330000, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x100f0003, 0x10f10003, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x3f010119, 0xc10101e7, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0e010000, 0x0eff0000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x1c2b0107, 0x1c2b0107, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x7201081a, 0x8eff081a, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x71000303, 0x8f000303, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x04010102, 0x04ff0102, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x030d0c7d, 0x030d0c83, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0001017c, 0x00ffff7c, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x017f5500, 0xff7f5500, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00020101, 0x0002ff01, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01010000, 0x01010000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x08011720, 0xf8ff1720, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00240120, 0x0024ffe0, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0156210b, 0xffaadf0b, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0f0e0101, 0xf10effff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00190067, 0x00e70099, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x10010107, 0xf0ff0107, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01557e03, 0x01557e03, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01017101, 0xffff7101, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01003c56, 0xff003caa, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x05007001, 0x05007001, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x02021f08, 0x02021ff8, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x0033043f, 0x0033043f, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00020101, 0x0002ff01, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x07150440, 0x071504c0, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x513f0024, 0x513f0024, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x71016101, 0x8f019fff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x031e0e01, 0x031e0e01, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x7700060d, 0x770006f3, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01033c06, 0x01033c06, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0838061e, 0x0838061e, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0300001d, 0x030000e3, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00003d1f, 0x0000c3e1, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00005649, 0x0000aa49, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x013f010a, 0xffc1ff0a, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01030101, 0xff03ffff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x30000001, 0x300000ff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x010d4a02, 0xfff3b602, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x32020000, 0x32020000, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x31000407, 0xcf000407, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x1f010c00, 0xe1ff0c00, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x71037d00, 0x71038300, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x671c0004, 0x991c0004, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00010001, 0x00ff00ff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00000f00, 0x00000f00, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x38400101, 0x384001ff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x010e7002, 0xff0e7002, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x79000000, 0x87000000, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x18016e00, 0x18ff9200, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x003c1d7f, 0x003ce380, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x0001010d, 0x0001010d, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x1b30047f, 0x1b300480, 0x00000000, 0x00100000 + dspck_dsio absq_s.qb, 0x33370001, 0x333700ff, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x71003000, 0x8f003000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x013f070e, 0xff3f070e, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x0101210d, 0xffffdff3, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01020171, 0xff02ff8f, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x7d017200, 0x83ff8e00, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x10000401, 0x1000fc01, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x000d7e02, 0x00f37e02, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00010101, 0x0001ffff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x20000161, 0x2000019f, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00030501, 0x000305ff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01010118, 0xffff0118, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x09000436, 0x09000436, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x21010100, 0xdfffff00, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x181e0100, 0x181eff00, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x09020911, 0x09fef7ef, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x05010100, 0x05ffff00, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x61137201, 0x9f138e01, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x003f2400, 0x003f2400, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x7d3d0110, 0x833d01f0, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x700e1938, 0x700ee738, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x08011d01, 0xf801e3ff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01097f03, 0x01097f03, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x05070a3f, 0x05070a3f, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01260600, 0x01260600, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x0d000200, 0xf3000200, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x02010939, 0x02ff09c7, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x070a0101, 0xf90a0101, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x2c000100, 0x2c00ff00, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00010126, 0x00ffff26, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x01010172, 0xff01ff8e, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01550f01, 0x01550fff, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0f01003e, 0x0f01003e, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x1c010140, 0x1cff0140, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00113f05, 0x00ef3f05, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x01303619, 0xff303619, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00011c60, 0x00ff1c60, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x66010100, 0x66ffff00, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x1f00404b, 0x1f00c04b, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0310016e, 0x03f00192, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x2e310125, 0x2ecf01db, 0x00000000, 0x00000000 + dspck_dsio absq_s.qb, 0x0007007f, 0x00070080, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x30790a00, 0x30870a00, 0x00100000, 0x00100000 + dspck_dsio absq_s.qb, 0x00007806, 0x00007806, 0x00100000, 0x00100000 + + writemsg "[2] Test addu.ph" + dspck_dstio addu.ph, 0x7b52f3d9, 0x800ffffa, 0xfb43f3df, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xedb67ff9, 0x80000000, 0x6db67ff9, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x8000f7fc, 0x8000fff9, 0x0000f803, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x9a51405f, 0x9999007f, 0x00b83fe0, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xc71cb3bd, 0xc71cb6db, 0x0000fce2, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x371a7fe0, 0xffe08000, 0x373affe0, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x807fc96a, 0x80002fd1, 0x007f9999, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x01bbca9a, 0xfff0c007, 0x01cb0a93, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xdd03ff12, 0x00000005, 0xdd03ff0d, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x1e35ffff, 0x1c717fff, 0x01c48000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xff350ff8, 0xff35fffa, 0x00000ffe, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x3fc0fff0, 0x3fc07ff0, 0x00008000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xfb96fc96, 0xfbc8fc6f, 0xffce0027, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7fe07fff, 0x00000000, 0x7fe07fff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x800f82c5, 0x800f02c5, 0x00008000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xc0070000, 0xc0070000, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x8000781b, 0x7ffff81b, 0x00018000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x4977ffff, 0x4924fffe, 0x00530001, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xe02afffe, 0x000b7fff, 0xe01f7fff, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x1c61e392, 0xfff0e38e, 0x1c710004, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfffb8012, 0x7fff7fff, 0x7ffc0013, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xc003c002, 0x0000c001, 0xc0030001, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x0e377f19, 0x7fff7fff, 0x8e38ff1a, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xf8020006, 0xfc018003, 0xfc018003, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x1fe3fffe, 0x1fe07ffe, 0x00038000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfb5d007e, 0xdb6d807f, 0x1ff07fff, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xfffb000a, 0xfffb000a, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfac1ff80, 0x003f7f80, 0xfa828000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x00007ffd, 0x00000000, 0x00007ffd, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7ff2400e, 0xfff33ff8, 0x7fff0016, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x009efff2, 0x801f0001, 0x807ffff1, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xff040000, 0x107e0000, 0xee860000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xf003fffe, 0x00007fff, 0xf0037fff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x80007ff9, 0x7fff7fff, 0x0001fffa, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xb8e39fdf, 0x80007fff, 0x38e31fe0, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfffffff0, 0x80000000, 0x7ffffff0, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x803f0000, 0x00000000, 0x803f0000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x6ea58000, 0x00ef0000, 0x6db68000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xfffa8004, 0xfffa7fff, 0x00000005, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x4007ffe4, 0x8000ffe4, 0xc0070000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xbfefe453, 0x3ff0e3d7, 0x7fff007c, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x07187ffd, 0xf3e07fff, 0x1338fffe, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xff36fffd, 0x00007ffd, 0xff368000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xf7fdffff, 0xf001ffff, 0x07fc0000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xffe20f1d, 0xffe2000e, 0x00000f0f, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfffcfffe, 0x00007fff, 0xfffc7fff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7ffd83a0, 0x00007fff, 0x7ffd03a1, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x7ffe8000, 0x80000000, 0xfffe8000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x00fffffe, 0x00007fff, 0x00ff7fff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xbffb7fff, 0x7fff7fff, 0x3ffc0000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfff9400a, 0x0000c003, 0xfff98007, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x800300ee, 0x8003ffeb, 0x00000103, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7fa6fffd, 0xffa60002, 0x8000fffb, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x7fff19c1, 0x7fff19c1, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfff3ffff, 0x00017fff, 0xfff28000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xc00ffffe, 0x00007fff, 0xc00f7fff, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x09050000, 0x09050000, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x003b003f, 0x002f8000, 0x000c803f, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x80008000, 0x00000000, 0x80008000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x07fdffff, 0x07fc0000, 0x0001ffff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xffc13ffe, 0x00000000, 0xffc13ffe, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x7ff7524a, 0xfff89249, 0x7fffc001, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x7ff8ffff, 0xfff97fff, 0x7fff8000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xffc0ffe8, 0x00000000, 0xffc0ffe8, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x5cfcf0ff, 0x1ff0000f, 0x3d0cf0f0, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x800c79bf, 0x7fff8000, 0x000df9bf, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xfff303fc, 0x3ff00000, 0xc00303fc, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfb2eff54, 0x1b27ffc7, 0xe007ff8d, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xbffe7fff, 0x3ffe0000, 0x80007fff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x217d601f, 0x1fe0e01f, 0x019d8000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x80007ffe, 0x7fff8000, 0x0001fffe, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xbfbd8000, 0x3fc08000, 0x7ffd0000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x80000007, 0x80000007, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xffffffff, 0x80008000, 0x7fff7fff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x33330001, 0x33330002, 0x0000ffff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x03f77fff, 0xfff90000, 0x03fe7fff, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x1fa1c71c, 0x1fa10000, 0x0000c71c, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x80007ff7, 0x00007fff, 0x8000fff8, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x5552fff0, 0x55550000, 0xfffdfff0, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xfe5b8039, 0x044b8000, 0xfa100039, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x0000dfff, 0x0000e001, 0x0000fffe, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xff781062, 0x7f800ffe, 0x7ff80064, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x04fdfffe, 0x00ff7fff, 0x03fe7fff, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x0e3e835f, 0x8e388000, 0x8006035f, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xff803ffd, 0x7f803ffe, 0x8000ffff, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xfffc7ffd, 0x0001fffd, 0xfffb8000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x7f7e7fff, 0x7ffeffff, 0xff808000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xb8e38008, 0x80007fff, 0x38e30009, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x807f0084, 0x807f007f, 0x00000005, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x000500fa, 0x0000fffb, 0x000500ff, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xfffcc00f, 0x7fffc00f, 0x7ffd0000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x5fe03fb5, 0x1ff0ffb7, 0x3ff03ffe, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xfffafff9, 0xfffb8000, 0xffff7ff9, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x9026fc12, 0x807f0000, 0x0fa7fc12, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xa0080717, 0xc0070717, 0xe0010000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x7fe0f803, 0xffe0f801, 0x80000002, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x1ffcfff8, 0x1ffc7ff9, 0x00007fff, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xfe703fff, 0xffff3ffe, 0xfe710001, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x000f001f, 0x800f0000, 0x8000001f, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x4051fac5, 0x3ff8fd71, 0x0059fd54, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x7ff6ffc0, 0x7ff9ffc0, 0xfffd0000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x474280b4, 0xfe1e8000, 0x492400b4, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x0562089a, 0x0598ff63, 0xffca0937, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xf42c7fc1, 0x00007fc0, 0xf42c0001, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x8cc70602, 0x800007fe, 0x0cc7fe04, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x7ff07ffa, 0x7ff0fffa, 0x00008000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xd59400cc, 0x803f00ca, 0x55550002, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x80008e38, 0x80008e38, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x000d8000, 0x00020000, 0x000b8000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xff0e7dc5, 0xfffffdc6, 0xff0f7fff, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x7ffaff74, 0xfffbff81, 0x7ffffff3, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x7fffffd0, 0x7fffffd0, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x0000a00d, 0x0000800f, 0x00001ffe, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x92477ff8, 0xfffe7ff8, 0x92490000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x8ff8fffc, 0x0ffe0000, 0x7ffafffc, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x001e4924, 0x002c0000, 0xfff24924, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfffe001e, 0xffff000f, 0xffff000f, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7f7e0187, 0x7f800000, 0xfffe0187, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x0002400f, 0x0000c00f, 0x00028000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x003ffff8, 0x00008000, 0x003f7ff8, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xfff8807f, 0x00000000, 0xfff8807f, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7ffffff2, 0x00000000, 0x7ffffff2, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x0002e401, 0x0000e003, 0x000203fe, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xc924009d, 0x8000009c, 0x49240001, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfb3d8129, 0xfb380129, 0x00058000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xf1301fb3, 0x00d2ffd3, 0xf05e1fe0, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7ff57fbc, 0x80007f80, 0xfff5003c, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x06a880dd, 0x06a100de, 0x00077fff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xffdf38e6, 0x7fe00003, 0x7fff38e3, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x80008003, 0x80007fff, 0x00000004, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x8003fd4e, 0x0004fce2, 0x7fff006c, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x099e0ffd, 0x07fef001, 0x01a01ffc, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xc00f7fff, 0xc00f0000, 0x00007fff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x00077ff6, 0x0000fff6, 0x00078000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x3ff01082, 0x00000084, 0x3ff00ffe, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x00eb007e, 0x00ac807f, 0x003f7fff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xc9230041, 0x7fff803f, 0x49248002, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x8006d804, 0x8000e001, 0x0006f803, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x38e3fb2c, 0x38e30004, 0x0000fb28, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x0f0fc718, 0x0f0ffffc, 0x0000c71c, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xffff7ff7, 0x8000fff8, 0x7fff7fff, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x8097c01b, 0x00880014, 0x800fc007, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x1249004a, 0x92490000, 0x8000004a, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xfff90001, 0xfff87fff, 0x00018002, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x2842bfe0, 0xe8468000, 0x3ffc3fe0, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x1591bff8, 0xffeb8000, 0x15a63ff8, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x003e08b2, 0x7fff094d, 0x803fff65, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xd01d9c49, 0xc01f7fff, 0x0ffe1c4a, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xffe72810, 0xffe9ef2d, 0xfffe38e3, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x0000b8ea, 0x000038e3, 0x00008007, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x0f1e2ea6, 0x078f1753, 0x078f1753, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x80048000, 0x00000000, 0x80048000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x803ff003, 0x003f0000, 0x8000f003, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xff00db6b, 0xff00fffe, 0x0000db6d, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x80007ffe, 0x00007fff, 0x8000ffff, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x003ffcbc, 0x8000fcbf, 0x803ffffd, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x7fffe01f, 0x7fffe01f, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x00018000, 0x00018000, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x0001469d, 0x8000069f, 0x80013ffe, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x0002d959, 0x00009999, 0x00023fc0, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfffefffa, 0x7fff7fff, 0x7fff7ffb, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7f5eff70, 0x80000070, 0xff5eff00, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7fc0fcdb, 0x8000fc9f, 0xffc0003c, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xc0128000, 0xc00f0000, 0x00038000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x00320000, 0x00320000, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xeeb5f9dc, 0xeeb5f9dc, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xffe8ff35, 0xffe90000, 0xffffff35, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xfeff7fff, 0x0e7d7fff, 0xf0820000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x192cf0f0, 0x2b380000, 0xedf4f0f0, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x100cbc25, 0x0ffc3c25, 0x00108000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x00247ff0, 0x001f0000, 0x00057ff0, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xe666c91e, 0x66664924, 0x80007ffa, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x99997ffe, 0x00008000, 0x9999fffe, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x8002ffe6, 0x00010000, 0x8001ffe6, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xff4d006c, 0x00000000, 0xff4d006c, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x7fffffff, 0x00007fff, 0x7fff8000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x70f00000, 0xf0f0fffa, 0x80000006, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xffff1c71, 0x80001c71, 0x7fff0000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x00000051, 0x80000051, 0x80000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xf7fd800e, 0xf801000f, 0xfffc7fff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xffff0003, 0x7fff0000, 0x80000003, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x7ffdffff, 0x80007fff, 0xfffd8000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x0405ccdb, 0x0007cccc, 0x03fe000f, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x07ee8000, 0x00000000, 0x07ee8000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xfe7506d9, 0x000007fe, 0xfe75fedb, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x80068000, 0x80000000, 0x00068000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x7fa0f342, 0x3fc0f1c8, 0x3fe0017a, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x4fdc6000, 0x3fe0e001, 0x0ffc7fff, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x80000002, 0x80000002, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7ffc7fd0, 0x80007fe0, 0xfffcfff0, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xe86683ca, 0xc86803cb, 0x1ffe7fff, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xffffebf1, 0x8000f0b6, 0x7ffffb3b, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xffc0b6db, 0xffc0b6db, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x80003ffe, 0x00000000, 0x80003ffe, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x803f7fa5, 0x80008000, 0x003fffa5, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x27f67fe5, 0x07fe7fff, 0x1ff8ffe6, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x87fed555, 0x80005555, 0x07fe8000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x00000ffe, 0x00000000, 0x00000ffe, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7fa5c0f9, 0x7fffc003, 0xffa600f6, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xbff32062, 0x3ff01ff0, 0x80030072, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x00000060, 0x00000000, 0x00000060, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfedc0000, 0xff6e8000, 0xff6e8000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xd9ffffff, 0x03fe0000, 0xd601ffff, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x21398005, 0x168b8007, 0x0aaefffe, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x00010004, 0x00000004, 0x00010000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xc001ffff, 0xc0017fff, 0x00008000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xffff8007, 0x7fff8000, 0x80000007, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7ff00fbe, 0x00000fb7, 0x7ff00007, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x1ffcffc0, 0x00000000, 0x1ffcffc0, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0x803f0000, 0x803f8000, 0x00008000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xb0f171b8, 0xc00171c7, 0xf0f0fff1, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x0405801e, 0x00078000, 0x03fe001e, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x7fe47fff, 0xffe4ffff, 0x80008000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x8127fffd, 0x01270001, 0x8000fffc, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xffeea4fa, 0xfffe71c7, 0xfff03333, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x60020106, 0x7ffffffd, 0xe0030109, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xfffe7ffe, 0x7ffffffe, 0x7fff8000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xff368390, 0x00000390, 0xff368000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xb6db3ffd, 0x00003ffe, 0xb6dbffff, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xc01cfffe, 0xc01ffffd, 0xfffd0001, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x0f0f8000, 0x0f0f8000, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0x70c77e01, 0x71c77fff, 0xff00fe02, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x021b8000, 0x00000000, 0x021b8000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xe01ffb12, 0xe01fffff, 0x0000fb13, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xc9260138, 0x4924ffb6, 0x80020182, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x85c47fff, 0x7ff97fff, 0x05cb0000, 0x00000000, 0x00000000 + dspck_dstio addu.ph, 0xfaba2aae, 0xfab9aaaa, 0x00018004, 0x00100000, 0x00100000 + dspck_dstio addu.ph, 0xbf32807f, 0xc001007f, 0xff318000, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x00070006, 0x80070000, 0x80000006, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x8002e38b, 0x0003e38e, 0x7ffffffd, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0xffdf7fff, 0x7fe08000, 0x7fffffff, 0x00000000, 0x00100000 + dspck_dstio addu.ph, 0x04e4b8dd, 0xffc938e3, 0x051b7ffa, 0x00000000, 0x00100000 + + writemsg "[3] Test addu_s.ph" + dspck_dstio addu_s.ph, 0x8007804c, 0x80007fff, 0x0007004d, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffff8005, 0xf2d97fff, 0xffec0006, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x0000fe78, 0x00000d88, 0x0000f0f0, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffa001, 0xfffc8003, 0x07fe1ffe, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xfffafbb5, 0x8000febc, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffffffe, 0x7fff0000, 0x8000fffe, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0x3fc08000, 0xfff8807f, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x28695555, 0x00040000, 0x28655555, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x80f1a195, 0x00f207fc, 0x7fff9999, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffe801e, 0x7fff001f, 0x7fff7fff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x00017fff, 0x00017fff, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x8000807d, 0x7fff007f, 0x00017ffe, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffff007f, 0x80000000, 0x8e38007f, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffe68ff5, 0x00000ffc, 0xffe67ff9, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x84647fff, 0x04657fff, 0x7fff0000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffb9fef, 0xfff81ff0, 0x00037fff, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0xfff87fff, 0x7ffc8006, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfff87fff, 0xfff87fff, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x81eaffff, 0x7fffcccc, 0x01eb807f, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff0005, 0x7fff0005, 0xfffd0000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xbff81029, 0x3ff80031, 0x80000ff8, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffff0008, 0x80000004, 0x80000004, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xc0e4ffff, 0xc0078000, 0x00dd8000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x85e97fcf, 0x8000000f, 0x05e97fc0, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfff3f003, 0x0003f003, 0xfff00000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffffdd1, 0xfffc0000, 0x0007fdd1, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xa491e01b, 0x24921ffc, 0x7fffc01f, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xa0770025, 0x807f0000, 0x1ff80025, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x0008ff2d, 0x0008ff2d, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xfffffffe, 0x80007fff, 0x7fff7fff, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x0006000d, 0x00060007, 0x00000006, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xdcf3ffff, 0x1ce4f801, 0xc00fffff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x8000e03d, 0x00061ffe, 0x7ffac03f, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x2017b6db, 0x1fe00000, 0x0037b6db, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff738e, 0xfff101c7, 0x7fff71c7, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xfff5ffff, 0xfff2f80a, 0x00037fff, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff0014, 0xc71c0000, 0x7fff0014, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffaffff, 0x0000ff07, 0xfffa0e69, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xff67b332, 0xff673333, 0x00007fff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xe003ebdd, 0xf0e5fc3a, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xfc017fff, 0xfffd8000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x00010000, 0x00000000, 0x00010000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0xc0077fff, 0x8000ffbb, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfff00005, 0xfff00005, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x000fffff, 0x0000ff03, 0x000fffff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x0086ffff, 0x007ffebd, 0x0007aaaa, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xbffdf92c, 0x3ffe000c, 0x7ffff920, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xfff90004, 0x00000002, 0xfff90002, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x0015bffe, 0x00033ffe, 0x00128000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xbfbf80b1, 0x3fc000b2, 0x7fff7fff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x0000000f, 0x0000000f, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xfffffffe, 0x000f0000, 0xfff9fffe, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffeffff, 0x0000f889, 0xfffefffe, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x800df007, 0x8000f007, 0x000d0000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0xf001ffff, 0x80008000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x3ffef93e, 0x3ffef93e, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xff7fffff, 0x7f807fff, 0x7fffc01f, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xf50cfc94, 0xfec87f80, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x0000ffff, 0x00008000, 0x0000aaaa, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff8004, 0x7ffc0001, 0xffff8003, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x804307c7, 0x800007c7, 0x00430000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x8012ffff, 0x00127ff8, 0x8000c001, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff07fe, 0xfe1107fe, 0xff790000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x808d0ffe, 0x008d0002, 0x80000ffc, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff8062, 0xfffe8000, 0xfff90062, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0x8000f801, 0xffe97fff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x00420689, 0x00000000, 0x00420689, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xe003fffd, 0x7ffff003, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x7fff0004, 0x00000004, 0x7fff0000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0x7fffc007, 0x80007fff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x223fff18, 0x05ce0001, 0x1c71ff17, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x27eeffff, 0x1ff07fff, 0x07fedb6d, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x8000f977, 0x80000023, 0x0000f954, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffa492, 0x80008000, 0xffe72492, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x801cffff, 0x001cffff, 0x80000000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff7fff, 0x99990000, 0x92497fff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfff81d5c, 0xfff81d5c, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0xfffe8000, 0x000ffffe, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x0002fffe, 0x00020000, 0x0000fffe, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff8000, 0x80000000, 0xfff48000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xfc01ffff, 0x0000fff1, 0xfc01cd65, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x00210000, 0x001f0000, 0x00020000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xbfc0ffff, 0x3fc07fff, 0x80008000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffe08e, 0xffcee00f, 0x1ff0007f, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfff90000, 0x7ffa0000, 0x7fff0000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffeffff, 0xfffef95b, 0x00008000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0x7fffe007, 0xfff98000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffffffe, 0x7fff0000, 0x8006fffe, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffa0000, 0x7ffd0000, 0x7ffd0000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x6db7ffff, 0x6db60675, 0x0001f98d, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff07fc, 0x7fff0000, 0x800007fc, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0xfff9ff5c, 0x807f8000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0x07fcf001, 0xfffe8000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xff82ffff, 0xff827fff, 0x00008002, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfca6ffff, 0xfc01c01f, 0x00a5cab9, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xea55ffdf, 0x0ee80000, 0xdb6dffdf, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x83fe0dbb, 0x03fe0710, 0x800006ab, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0x8002c71c, 0xfff9ffff, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffc00f, 0xfffd0000, 0x00a0c00f, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff000c, 0xfffa0004, 0xff7a0008, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff8014, 0x80000014, 0xfffa8000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffc71c, 0xffff0000, 0x8000c71c, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x3fccffff, 0x3fc0801f, 0x000c8000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffd34c, 0xffff1c71, 0xfffab6db, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xff80ffff, 0x80001ce2, 0x7f80ffff, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff107d, 0x7fff0ffe, 0xff9a007f, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff0005, 0x80000000, 0xfa280005, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x8013cccd, 0x7fffcccc, 0x00140001, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffff80, 0x80000000, 0x8001ff80, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x8ff8f49f, 0x0ff8f499, 0x80000006, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xfc38ffff, 0x00007fff, 0xfc38ffec, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffe0, 0xaaaa8000, 0x80007fe0, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffeffff, 0x7ffffff9, 0x7fff8000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xfc56ff89, 0x003f0018, 0xfc17ff71, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x81407fc0, 0x80007fc0, 0x01400000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffff07fc, 0x800f0000, 0x800007fc, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xc0038003, 0x00000000, 0xc0038003, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0xf0037fff, 0xfffdfff9, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffffff3, 0xc03f0003, 0x6666fff0, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffffffe, 0x80007fff, 0xff547fff, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x04d88000, 0x00520000, 0x04868000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x78dfaaaa, 0x38e3aaaa, 0x3ffc0000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffff2f11, 0xffc62f11, 0xc00f0000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x0071ffff, 0x006af001, 0x00071c71, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0x80008000, 0x8000ffc0, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x555f0001, 0x55550001, 0x000a0000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x405d7fff, 0x3ffc7fff, 0x00610000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x00018000, 0x00018000, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xc007c01f, 0x7fffaaaa, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff0000, 0x80000000, 0x80000000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x80000000, 0x80000000, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff0ff8, 0xfffd0ff8, 0xffce0000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x0001f003, 0x0001f003, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x000500ff, 0x000500ff, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff0009, 0xfffd0009, 0xff410000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xe001fe20, 0xe001fe20, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xfffc7fff, 0x000d8000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff0014, 0x1ff80005, 0xfff9000f, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffcfff, 0x80070ffc, 0xfe29c003, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0x7fffffd1, 0x8000fcc2, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffffff9, 0xfffc7fff, 0x3fe07ffa, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xfffdf003, 0xfffec01f, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xf3ce8050, 0xaaaa7fff, 0x49240051, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x08198000, 0x00000000, 0x08198000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x8622ffff, 0x06228002, 0x8000f803, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x8007aab9, 0x0000000f, 0x8007aaaa, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x01b9f9cd, 0x0000f9be, 0x01b9000f, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xbfe0ff8c, 0x3fe000c2, 0x8000feca, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff3ff8, 0xffff3ff8, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x00ad0002, 0x007e0001, 0x002f0001, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffcd46, 0xf262cccc, 0x8000007a, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff800c, 0xfffd000d, 0x00a97fff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0x80008000, 0xff95f003, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x87fc0003, 0x07fc0003, 0x80000000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffff0004, 0x80000002, 0x80000002, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xdb6fffff, 0xdb6dfffb, 0x00027fff, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x3ffb8000, 0x00030000, 0x3ff88000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff87fe, 0x800007fe, 0x801f8000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff9156, 0x800f1156, 0x803f8000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x08020007, 0x00060007, 0x07fc0000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xe003f410, 0xe003f409, 0x00000007, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x800e9ffc, 0x7fff8000, 0x000f1ffc, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0xb6db7fff, 0xe01f8000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffa1ff0, 0xfffa1ff0, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0xffb67fff, 0xfff68001, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffe8002, 0xfffe7fff, 0x00000003, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x0099ffff, 0x00990004, 0x0000fffe, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffd1, 0xfff9ffd1, 0xff800000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x03adffff, 0x0003fffe, 0x03aa7fff, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xfffeb8e2, 0x7fff7fff, 0x7fff38e3, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x8004fffe, 0x80047fff, 0x00007fff, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xfff98e59, 0x00008e38, 0xfff90021, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xff068000, 0xff008000, 0x00060000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0x8000ff47, 0xfff4f001, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffdb6d, 0x9999db6d, 0x80000000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x8a67ffff, 0x0a68f003, 0x7fff1ff8, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x3b4a00de, 0x00000001, 0x3b4a00dd, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff1fe0, 0x11900000, 0xf8011fe0, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x80008000, 0x80008000, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x81e61555, 0x01e70005, 0x7fff1550, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x0ffd0000, 0x00050000, 0x0ff80000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xfffc001f, 0xfff3001e, 0x00090001, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x80000801, 0x000107fe, 0x7fff0003, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x4bd80002, 0x25ec0001, 0x25ec0001, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0xc00ff754, 0xfefb7fff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x00498ff6, 0x000a0ff8, 0x003f7ffe, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x0000f003, 0x00000000, 0x0000f003, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0x8000fff9, 0xffff800f, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x0000faa5, 0x0000faa5, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xe0078000, 0xf8497fff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff100d, 0xfff90015, 0x80000ff8, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xfffd8000, 0x8000fffc, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x001280f2, 0x00008000, 0x001200f2, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff02c4, 0x80000162, 0x80000162, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x0065ffff, 0x0065fff0, 0x0000ffd4, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xffc07fff, 0xfffaffff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x07ffffff, 0x0003ff92, 0x07fcfffa, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0x7ffff801, 0x80005555, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xfcf3ffff, 0xfcb4ef00, 0x003f8000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xfb0e0016, 0xf0010016, 0x0b0d0000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x000fffcf, 0x00000000, 0x000fffcf, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff00ef, 0xfeef00e8, 0x7ff80007, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x02f97fc0, 0x02f97fc0, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffff0025, 0xfffc0006, 0x0094001f, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xfffd7fff, 0x24928000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffff53, 0xff90ff48, 0x06c1000b, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x7fffbff8, 0x7fff8000, 0x00003ff8, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0x8000e003, 0x80008000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x7fffffff, 0x00007fff, 0x7ffff3b3, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff4001, 0xfffc3ffe, 0x7fff0003, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x8019ffff, 0x8000ffef, 0x0019f2cb, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x00007fff, 0x00000000, 0x00007fff, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x00008000, 0x00000000, 0x00008000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xfffcc71c, 0x9999fffa, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff800e, 0x71c7000f, 0xfe127fff, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x000dffff, 0x000d8000, 0x00007fff, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x3ffc001b, 0x3ffc001b, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0xffff8000, 0x0f0f8000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x7ff8ffff, 0x3ffcffc0, 0x3ffcffc0, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xff36fe6c, 0x8e387fc0, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0xc00fff4c, 0x80007ff9, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffc0, 0xff000000, 0xfffeffc0, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x8000ffff, 0x8000e74a, 0x0000f007, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x07fcffff, 0x0000ffb9, 0x07fcfffe, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x8000fe8a, 0x8000fe8a, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffffff, 0x7ffcf001, 0xffff8000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x80e783fe, 0x00c88000, 0x801f03fe, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffffbde1, 0xb6db0706, 0x8000b6db, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0x7ffe9999, 0xfffffff0, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff8000, 0x7ffb0000, 0xf1a08000, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0x81e5018e, 0x7ff000be, 0x01f500d0, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x8000fffe, 0x80007fff, 0x00007fff, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xffff7fff, 0xc01f7fff, 0xffd20000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0x3ffeffff, 0x3ffeff42, 0x00005555, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffb6dd, 0x7fff0002, 0x807fb6db, 0x00100000, 0x00100000 + dspck_dstio addu_s.ph, 0xe38e0054, 0x00000000, 0xe38e0054, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0xf0f0eaa6, 0x00003ffc, 0xf0f0aaaa, 0x00000000, 0x00000000 + dspck_dstio addu_s.ph, 0x8000ffff, 0x0000ffd0, 0x8000e001, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffff5555, 0xc00f5555, 0xc03f0000, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xffffffff, 0x7ffffffc, 0xdb6d807f, 0x00000000, 0x00100000 + dspck_dstio addu_s.ph, 0xea6821cc, 0x0a651ff0, 0xe00301dc, 0x00000000, 0x00000000 + + writemsg "[4] Test adduh.qb" + dspck_dstio adduh.qb, 0x8da5b67e, 0x1c7e6f00, 0xffccfefc, 0x0, 0x0 + dspck_dstio adduh.qb, 0x001f005b, 0x01000000, 0x003e00b6, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00b2386a, 0x006600c7, 0x00ff700e, 0x0, 0x0 + dspck_dstio adduh.qb, 0x3ebe7905, 0x7c7e000b, 0x00fff300, 0x0, 0x0 + dspck_dstio adduh.qb, 0xe766078e, 0xf00006ff, 0xdfcc091e, 0x0, 0x0 + dspck_dstio adduh.qb, 0x810e0182, 0x03000005, 0xff1d03ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x070257a4, 0x0f047f92, 0x000030b6, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0086aa55, 0x00e35501, 0x0029ffaa, 0x0, 0x0 + dspck_dstio adduh.qb, 0xa800279d, 0xff003cff, 0x5200123c, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f4702ad, 0xf90000db, 0x068e057f, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0f5c6034, 0x1eaa002a, 0x010ec03e, 0x0, 0x0 + dspck_dstio adduh.qb, 0xa16f8054, 0x83db0125, 0xc003ff83, 0x0, 0x0 + dspck_dstio adduh.qb, 0x8bff3738, 0xffff6600, 0x17ff0971, 0x0, 0x0 + dspck_dstio adduh.qb, 0x3638797f, 0x6d71c000, 0x000032ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f1f9d00, 0xff3f3c00, 0x0000ff00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x8a4c3700, 0x15996400, 0xff000a00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x8100000f, 0x03000002, 0xff00001d, 0x0, 0x0 + dspck_dstio adduh.qb, 0x680d79c1, 0xcf0302b6, 0x0218f1cc, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00004300, 0x00000000, 0x00008700, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f190a09, 0x00300f13, 0xff030600, 0x0, 0x0 + dspck_dstio adduh.qb, 0x6fff0c09, 0x83ff0305, 0x5cff160e, 0x0, 0x0 + dspck_dstio adduh.qb, 0x067f1d57, 0x0600033f, 0x06ff3870, 0x0, 0x0 + dspck_dstio adduh.qb, 0x8507bfd4, 0xef0f80aa, 0x1c00fffe, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7e03027f, 0xfd0705ff, 0x00000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0xd74ee096, 0xbf0ac366, 0xef92fdc7, 0x0, 0x0 + dspck_dstio adduh.qb, 0x479c8089, 0x003a8014, 0x8eff80ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x38088540, 0x66000c81, 0x0a11ff00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00bd22e3, 0x00ff01ff, 0x007c44c7, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7e997f42, 0x00330060, 0xfcffff24, 0x0, 0x0 + dspck_dstio adduh.qb, 0xff9907be, 0xffff0eff, 0xff33007e, 0x0, 0x0 + dspck_dstio adduh.qb, 0xef004f80, 0xdf001f01, 0xff0080ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x157e0049, 0x2afd0000, 0x00000092, 0x0, 0x0 + dspck_dstio adduh.qb, 0x21033b66, 0x03004400, 0x400633cc, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0b6ac342, 0x0f54ff05, 0x0781877f, 0x0, 0x0 + dspck_dstio adduh.qb, 0x4aed7e7a, 0x8fe3f778, 0x06f8067c, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f06807f, 0x000cff00, 0xff0001ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x83bbff01, 0x08f8ff02, 0xff7eff01, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7d387fb8, 0xf37000ff, 0x0700ff71, 0x0, 0x0 + dspck_dstio adduh.qb, 0x06030066, 0x040600cc, 0x09000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0c160400, 0x00030100, 0x18290800, 0x0, 0x0 + dspck_dstio adduh.qb, 0x12000c85, 0x23000e3e, 0x02010bcc, 0x0, 0x0 + dspck_dstio adduh.qb, 0x04aa0800, 0x04aa0800, 0x04aa0800, 0x0, 0x0 + dspck_dstio adduh.qb, 0x89fb0001, 0x92ff0103, 0x81f80000, 0x0, 0x0 + dspck_dstio adduh.qb, 0xa97f2212, 0xc1ff3800, 0x92000c24, 0x0, 0x0 + dspck_dstio adduh.qb, 0x051c7e02, 0x0038f704, 0x0b000600, 0x0, 0x0 + dspck_dstio adduh.qb, 0x91f30f06, 0xffe70001, 0x24ff1f0c, 0x0, 0x0 + dspck_dstio adduh.qb, 0x02f6118d, 0x02f1051b, 0x02fc1eff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x839d4462, 0x08ff71c3, 0xff3c1801, 0x0, 0x0 + dspck_dstio adduh.qb, 0x41c28381, 0x83c3fff3, 0x00c10710, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00034c4d, 0x0007920c, 0x0000078e, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0d037f7f, 0x0006ffff, 0x1a010000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x1f037418, 0x0000e130, 0x3e060700, 0x0, 0x0 + dspck_dstio adduh.qb, 0x2a77bc80, 0x55009902, 0x00efdfff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x003f9700, 0x007e3000, 0x0100ff00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x3dff010f, 0x4aff0300, 0x31ff001f, 0x0, 0x0 + dspck_dstio adduh.qb, 0x003c9988, 0x0079ffff, 0x00003411, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f86e102, 0x00ffc305, 0xff0eff00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x183f0303, 0x12010406, 0x1e7e0201, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0d210d07, 0x0c3f0000, 0x0e031b0f, 0x0, 0x0 + dspck_dstio adduh.qb, 0x006a1e3e, 0x010e3c01, 0x00c7017c, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0239b91f, 0x0005ff30, 0x046d730f, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f003382, 0x0001000c, 0xff0066f9, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7a87c1f8, 0xe7f1ffff, 0x0e1e83f1, 0x0, 0x0 + dspck_dstio adduh.qb, 0x147c7d40, 0x00002b01, 0x28f9cf80, 0x0, 0x0 + dspck_dstio adduh.qb, 0x20050701, 0x20050701, 0x20050701, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7a7ff77f, 0x0effffff, 0xe700f000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x16007f00, 0x1e00ff00, 0x0f000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f7f6f07, 0x00007f0f, 0xffff6000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x8387817f, 0x080fffff, 0xffff0300, 0x0, 0x0 + dspck_dstio adduh.qb, 0x693c077f, 0xbf780e00, 0x130001ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0xff5b207d, 0xff3e3ebf, 0xff78033c, 0x0, 0x0 + dspck_dstio adduh.qb, 0x1fb60071, 0x006d0000, 0x3eff00e3, 0x0, 0x0 + dspck_dstio adduh.qb, 0x4a8effa8, 0x921dffc3, 0x03ffff8e, 0x0, 0x0 + dspck_dstio adduh.qb, 0xcf017814, 0xcf017814, 0xcf017814, 0x0, 0x0 + dspck_dstio adduh.qb, 0xa3077007, 0x550f0100, 0xf100e00e, 0x0, 0x0 + dspck_dstio adduh.qb, 0xbe427c80, 0x7e810201, 0xff03f7ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x86510485, 0x0d9f00ff, 0xff04090c, 0x0, 0x0 + dspck_dstio adduh.qb, 0xb51c487f, 0xfe008eff, 0x6d380200, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0e007f07, 0x0000000e, 0x1d00ff00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0940007b, 0x00000000, 0x128000f7, 0x0, 0x0 + dspck_dstio adduh.qb, 0x19432c06, 0x0087290b, 0x32003002, 0x0, 0x0 + dspck_dstio adduh.qb, 0x77f7878f, 0xeff0ffff, 0x00ff0f1f, 0x0, 0x0 + dspck_dstio adduh.qb, 0x77435378, 0xef0087f1, 0x00871f00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x81fbf8e3, 0x03f7ffc7, 0xfffff1ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f007f00, 0x0000ff00, 0xff000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x83603318, 0xffc10b30, 0x07005c00, 0x0, 0x0 + dspck_dstio adduh.qb, 0xff3301f1, 0xff3301f1, 0xff3301f1, 0x0, 0x0 + dspck_dstio adduh.qb, 0x4c361bf9, 0x000034f9, 0x996d02f9, 0x0, 0x0 + dspck_dstio adduh.qb, 0x1f00885d, 0x3e01ff87, 0x00001233, 0x0, 0x0 + dspck_dstio adduh.qb, 0x6438ff91, 0x011cff24, 0xc755ffff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x108a367f, 0x001617ff, 0x21ff5500, 0x0, 0x0 + dspck_dstio adduh.qb, 0x817f4f09, 0xff000012, 0x04ff9f00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f0c9d83, 0x00183cff, 0xfe00ff07, 0x0, 0x0 + dspck_dstio adduh.qb, 0x024080c0, 0x008001ff, 0x0500ff81, 0x0, 0x0 + dspck_dstio adduh.qb, 0x857f4d7f, 0x0b0099ff, 0xffff0100, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7ff37f3a, 0x00e7ff04, 0xffff0071, 0x0, 0x0 + dspck_dstio adduh.qb, 0xb70c580b, 0x7019aa15, 0xff000601, 0x0, 0x0 + dspck_dstio adduh.qb, 0x04b18063, 0x06e02560, 0x0283db66, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0780498a, 0x0eff9216, 0x000100ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x03872a85, 0x000f3f0c, 0x07ff16ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0c60031e, 0x13c10600, 0x0600013c, 0x0, 0x0 + dspck_dstio adduh.qb, 0x000b0003, 0x00000000, 0x00170006, 0x0, 0x0 + dspck_dstio adduh.qb, 0x3b102a4f, 0x071e0000, 0x7002559f, 0x0, 0x0 + dspck_dstio adduh.qb, 0x37227020, 0x013a0000, 0x6d0be040, 0x0, 0x0 + dspck_dstio adduh.qb, 0x737fbba4, 0xe7ff78ff, 0x0000ff49, 0x0, 0x0 + dspck_dstio adduh.qb, 0x3cd5fc36, 0x00e3f907, 0x78c7ff66, 0x0, 0x0 + dspck_dstio adduh.qb, 0x1b7f80cc, 0x180001ff, 0x1effff99, 0x0, 0x0 + dspck_dstio adduh.qb, 0x01797f60, 0x00000000, 0x03f3ffc0, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f06cc81, 0x000cffff, 0xff019904, 0x0, 0x0 + dspck_dstio adduh.qb, 0x55183c52, 0x01307866, 0xaa01003e, 0x0, 0x0 + dspck_dstio adduh.qb, 0x8d748120, 0x1c2aff1c, 0xffbf0324, 0x0, 0x0 + dspck_dstio adduh.qb, 0x31018408, 0x34020a00, 0x2e01ff11, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7a483f55, 0x04357e00, 0xf05c00aa, 0x0, 0x0 + dspck_dstio adduh.qb, 0x73800660, 0xe7010dc1, 0x00ff0000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x80557f7f, 0x010000ff, 0xffaaff00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x1f7700ff, 0x000000ff, 0x3fef00ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x55afda00, 0x0c5fff00, 0x9fffb600, 0x0, 0x0 + dspck_dstio adduh.qb, 0x387f8200, 0x00ffff00, 0x71000600, 0x0, 0x0 + dspck_dstio adduh.qb, 0x03ff6381, 0x00ff0303, 0x07ffc3ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x05012a00, 0x0b025500, 0x00000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x117f810d, 0x14ef7f17, 0x0f0f8304, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0300d043, 0x0500f708, 0x0101aa7f, 0x0, 0x0 + dspck_dstio adduh.qb, 0x01603f00, 0x00000000, 0x03c17f00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7b00c300, 0x06008700, 0xf000ff00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0013077f, 0x00000dff, 0x00270100, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00470001, 0x008e0002, 0x00000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x2a00010f, 0x5500031e, 0x00000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0f085f21, 0x1f10bf43, 0x00000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00010574, 0x00020701, 0x010004e7, 0x0, 0x0 + dspck_dstio adduh.qb, 0x1f058063, 0x3f0aff00, 0x000101c7, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f710681, 0x00750703, 0xff6d05ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x66488000, 0x6081ff00, 0x6d0f0200, 0x0, 0x0 + dspck_dstio adduh.qb, 0xa0360e00, 0x423c1800, 0xff300400, 0x0, 0x0 + dspck_dstio adduh.qb, 0x417f420d, 0x7cff8017, 0x07000404, 0x0, 0x0 + dspck_dstio adduh.qb, 0x9a879f08, 0xf90fff10, 0x3cff4000, 0x0, 0x0 + dspck_dstio adduh.qb, 0xe1006600, 0xff00cc01, 0xc3000100, 0x0, 0x0 + dspck_dstio adduh.qb, 0x08ff837f, 0x01ffccff, 0x0fff3a00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0086ff01, 0x0015ff00, 0x00f8ff03, 0x0, 0x0 + dspck_dstio adduh.qb, 0x449ebf02, 0x01ffff00, 0x873e8004, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00ff38bb, 0x00ff71ff, 0x00ff0078, 0x0, 0x0 + dspck_dstio adduh.qb, 0x4c7f0603, 0x99000d07, 0x00ff0000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x782f9c02, 0xc1403a00, 0x301eff04, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00ed1200, 0x00e71200, 0x01f31301, 0x0, 0x0 + dspck_dstio adduh.qb, 0x478381bd, 0x00ffff7c, 0x8e0703ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x09857307, 0x00ff0b00, 0x120cdb0f, 0x0, 0x0 + dspck_dstio adduh.qb, 0x85032667, 0xff070c00, 0x0c0040cf, 0x0, 0x0 + dspck_dstio adduh.qb, 0x01051e49, 0x02003792, 0x000b0600, 0x0, 0x0 + dspck_dstio adduh.qb, 0xf39f157f, 0xf7df1d00, 0xef600eff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x12150019, 0x002b0020, 0x24000112, 0x0, 0x0 + dspck_dstio adduh.qb, 0x8118710b, 0x0400e300, 0xff300017, 0x0, 0x0 + dspck_dstio adduh.qb, 0x8bae4f14, 0xff607f20, 0x18fc2008, 0x0, 0x0 + dspck_dstio adduh.qb, 0x04ff0804, 0x02ff0200, 0x07ff0f08, 0x0, 0x0 + dspck_dstio adduh.qb, 0x057f7e82, 0x03fffd05, 0x070000ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00b8df16, 0x01ffff1e, 0x0071c00e, 0x0, 0x0 + dspck_dstio adduh.qb, 0xa88f008f, 0x713e0120, 0xe0e000ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0b053b7d, 0x160570f9, 0x00050601, 0x0, 0x0 + dspck_dstio adduh.qb, 0x02959a05, 0x0481ff0b, 0x00aa3500, 0x0, 0x0 + dspck_dstio adduh.qb, 0x159e0678, 0x1c3e0c09, 0x0fff00e7, 0x0, 0x0 + dspck_dstio adduh.qb, 0x667f0300, 0xccff0700, 0x00000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0015bb00, 0x002b7800, 0x0100ff00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x40141067, 0x802820cf, 0x00000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x85031f83, 0xff013e08, 0x0c0601ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x1439488d, 0x0703011c, 0x22708fff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x000f007f, 0x00000000, 0x011f00ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f06037f, 0x00000000, 0xff0c07ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x1c630d77, 0x00000000, 0x38c71bef, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0b5ea17e, 0x166943f7, 0x0053ff06, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0f100004, 0x05200009, 0x19010100, 0x0, 0x0 + dspck_dstio adduh.qb, 0xd3368f70, 0xc7051fe1, 0xdf67ff00, 0x0, 0x0 + dspck_dstio adduh.qb, 0xc700b608, 0xc700b608, 0xc700b608, 0x0, 0x0 + dspck_dstio adduh.qb, 0x48010506, 0x0201020d, 0x8e010800, 0x0, 0x0 + dspck_dstio adduh.qb, 0x017f0300, 0x00000000, 0x03ff0600, 0x0, 0x0 + dspck_dstio adduh.qb, 0x89800100, 0xf77f0100, 0x1c810100, 0x0, 0x0 + dspck_dstio adduh.qb, 0x051fda0b, 0x0a3eff08, 0x0000b60e, 0x0, 0x0 + dspck_dstio adduh.qb, 0x85102702, 0x0c1f4f04, 0xff020000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0602f1ff, 0x0001f1ff, 0x0d03f1ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x107f44be, 0x01ff057f, 0x200083fd, 0x0, 0x0 + dspck_dstio adduh.qb, 0x780006d8, 0x000000f1, 0xf0000cc0, 0x0, 0x0 + dspck_dstio adduh.qb, 0x07124444, 0x01000105, 0x0d248783, 0x0, 0x0 + dspck_dstio adduh.qb, 0x04005f08, 0x04000000, 0x0501bf11, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00007f0b, 0x0000ff07, 0x01010010, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0bba7338, 0x00ffdf01, 0x17750770, 0x0, 0x0 + dspck_dstio adduh.qb, 0x34ff4600, 0x49ff0d01, 0x20ff7f00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x443d1440, 0x7e0d2400, 0x0a6d0581, 0x0, 0x0 + dspck_dstio adduh.qb, 0x784a485b, 0x003d55b6, 0xf0573c01, 0x0, 0x0 + dspck_dstio adduh.qb, 0x38c3407f, 0x6d8780ff, 0x04ff0000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x1f0b6045, 0x3f00bf7f, 0x0016010c, 0x0, 0x0 + dspck_dstio adduh.qb, 0xdb2200fe, 0xf00700fd, 0xc73e00ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f010f30, 0xff000b60, 0x00021300, 0x0, 0x0 + dspck_dstio adduh.qb, 0x8f037f04, 0xff060009, 0x1f00ff00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0b7f0997, 0x00000b30, 0x16ff07ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f818800, 0xff248100, 0x00df8f00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x011a047e, 0x00290100, 0x020c07fd, 0x0, 0x0 + dspck_dstio adduh.qb, 0x034e8e81, 0x040e55ff, 0x028fc704, 0x0, 0x0 + dspck_dstio adduh.qb, 0x01000b03, 0x00000000, 0x02001607, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f181404, 0x00302808, 0xff000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00000604, 0x00010c09, 0x00000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0c9e23ff, 0x09ff3fff, 0x0f3e07ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00501a0c, 0x0099340b, 0x0008000e, 0x0, 0x0 + dspck_dstio adduh.qb, 0xcc9f1802, 0xffff0101, 0x993f3004, 0x0, 0x0 + dspck_dstio adduh.qb, 0xff9f057f, 0xff400aff, 0xffff0000, 0x0, 0x0 + dspck_dstio adduh.qb, 0xe1814707, 0xffff0105, 0xc3048e0a, 0x0, 0x0 + dspck_dstio adduh.qb, 0x88136d64, 0x6627001f, 0xaa00dbaa, 0x0, 0x0 + dspck_dstio adduh.qb, 0x46201976, 0x060100e0, 0x8740330c, 0x0, 0x0 + dspck_dstio adduh.qb, 0x9b1f034c, 0xff010015, 0x373e0783, 0x0, 0x0 + dspck_dstio adduh.qb, 0x03010aaf, 0x000007ff, 0x07030d60, 0x0, 0x0 + dspck_dstio adduh.qb, 0xff00780e, 0xff00780e, 0xff00780e, 0x0, 0x0 + dspck_dstio adduh.qb, 0x3c50f37f, 0x661ee700, 0x1283ffff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x6f06075b, 0x000804b6, 0xdf050a00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x18f8df71, 0x00ffff03, 0x31f1bfdf, 0x0, 0x0 + dspck_dstio adduh.qb, 0xb2ff3260, 0xffff4900, 0x66ff1cc1, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f01af10, 0xff03ff09, 0x00006018, 0x0, 0x0 + dspck_dstio adduh.qb, 0xf6803502, 0xfeff6a01, 0xef020003, 0x0, 0x0 + dspck_dstio adduh.qb, 0x803e1f20, 0x0101003f, 0xff7c3f01, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0903b67f, 0x0001ffff, 0x13056d00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x3219a481, 0x0000ff03, 0x653349ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x2600783e, 0x4d00f17c, 0x00000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x00aa7d03, 0x00fff902, 0x00550205, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0900ff73, 0x1100ff00, 0x0100ffe7, 0x0, 0x0 + dspck_dstio adduh.qb, 0x8bd883d4, 0xffc108fe, 0x18f0ffaa, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f887f05, 0xfff9030a, 0x0018fc00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x04804970, 0x00ff0002, 0x090192df, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0a006000, 0x0000c000, 0x15010100, 0x0, 0x0 + dspck_dstio adduh.qb, 0x477f067f, 0x00000000, 0x8eff0cff, 0x0, 0x0 + dspck_dstio adduh.qb, 0xbf8f7b7c, 0xff1ff700, 0x80ff00f9, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7222978a, 0x050dff55, 0xe03830c0, 0x0, 0x0 + dspck_dstio adduh.qb, 0x5838067f, 0x06000c00, 0xaa7000ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7e007f7f, 0xfd00ffff, 0x00000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0xff046e11, 0xff05db07, 0xff04011c, 0x0, 0x0 + dspck_dstio adduh.qb, 0x21a82b1c, 0x2d583e00, 0x15f91838, 0x0, 0x0 + dspck_dstio adduh.qb, 0x2ab61f00, 0x54ff3e00, 0x006d0000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x677f0051, 0xaaff009f, 0x24000003, 0x0, 0x0 + dspck_dstio adduh.qb, 0x82d24585, 0x06c16daa, 0xffe31e60, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0008407f, 0x001180ff, 0x00000000, 0x0, 0x0 + dspck_dstio adduh.qb, 0x099ec87f, 0x12409200, 0x00fdffff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f813301, 0xfeff4700, 0x00031f03, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0000f96d, 0x0000f96d, 0x0000f96d, 0x0, 0x0 + dspck_dstio adduh.qb, 0x10aa02ff, 0x205502ff, 0x00ff02ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x6d06127f, 0x1c002400, 0xbf0d00ff, 0x0, 0x0 + dspck_dstio adduh.qb, 0x81038b7e, 0x0305180b, 0xff01fff1, 0x0, 0x0 + dspck_dstio adduh.qb, 0x0600001d, 0x00000000, 0x0d00003b, 0x0, 0x0 + dspck_dstio adduh.qb, 0x31016600, 0x61010000, 0x0101cc00, 0x0, 0x0 + dspck_dstio adduh.qb, 0x7f5c7f05, 0x00b6ff00, 0xff03000b, 0x0, 0x0 + dspck_dstio adduh.qb, 0x000461cc, 0x00065599, 0x00036dff, 0x0, 0x0 + + writemsg "[5] Test adduh_r.qb" + dspck_dstio adduh_r.qb, 0x857e6272, 0x0a00c300, 0xfffc01e3, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x07ff1fd5, 0x0eff3daa, 0x00ff00ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0f4d4d94, 0x1c99998f, 0x01000099, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x80cc5601, 0xff990201, 0x00ffaa00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x72298019, 0xdf3f0013, 0x0412ff1f, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x80800727, 0x03ff0e3e, 0xfd00000f, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x24144b19, 0x3000872b, 0x18270e06, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xd7aaa680, 0xf7e17c00, 0xb673cfff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x4810c930, 0x80189206, 0x0f07ff5a, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x7744ff75, 0xcc00ff03, 0x2187ffe7, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8005f880, 0x0002f100, 0xff08ffff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x070202ff, 0x0e0003ff, 0x000300ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xcc9f8180, 0xffffffff, 0x993e0200, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0400c03f, 0x0400ff60, 0x0300801d, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x63119474, 0x1c1c99c3, 0xaa058f25, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x451304a4, 0x0c1201db, 0x7e14076d, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x198bf898, 0x0024f1ff, 0x32f1ff30, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x3f093000, 0x01100000, 0x7c016000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x06612ba4, 0x000155e7, 0x0cc00160, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xa43b624b, 0x49210330, 0xff55c066, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x048008ff, 0x000000ff, 0x07ff0fff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x4b9a8c00, 0x60341800, 0x36ffff00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x00098102, 0x000c8104, 0x00068000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x9e628534, 0x3cbf0a01, 0xff04ff66, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x03186066, 0x062fbfcc, 0x00000000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x38602c1a, 0x0ac00f33, 0x66004900, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0482bb10, 0x0007831f, 0x07fdf301, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x7fff0500, 0x7fff0500, 0x7fff0500, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x68ff3e82, 0xcfff7c04, 0x00ff00ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xb686cc0b, 0x6d0cff13, 0xffff9902, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x1fb81570, 0x3aff10c0, 0x03711a1f, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x72618a20, 0x08c1ff40, 0xdb001400, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8330bc72, 0x075f7863, 0xff00ff80, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x87ff2f80, 0x0fff3e01, 0xffff1fff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xe3ffa6ff, 0xffff4dff, 0xc7ffffff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x00ff0002, 0x00ff0000, 0x00ff0003, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x95110cb8, 0x2b000cff, 0xfe220c71, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0a0080c3, 0x0800ff87, 0x0c0000ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0380f79f, 0x00ffeffe, 0x0500ff40, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x4976e104, 0x00e3ff03, 0x9208c305, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x7d10312f, 0x01160208, 0xf9096055, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x1e800116, 0x00000000, 0x3cff012b, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x421a3f80, 0x00337eff, 0x83010000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8243a41f, 0x047f813e, 0xff07c700, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x01803971, 0x00000000, 0x01ff71e1, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x001ec707, 0x001ec707, 0x001ec707, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x3c101ef7, 0x781f39ff, 0x000003ef, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x3c1e8a80, 0x60033000, 0x1738e3ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x87118204, 0xff020401, 0x0f1fff06, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x20002055, 0x3f0040aa, 0x00000000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x04804a00, 0x017f0c00, 0x06808700, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x613e50f0, 0x007c00e0, 0xc1009fff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0800818e, 0x000003ff, 0x0f00ff1d, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x346a037a, 0x49cf05f3, 0x1e040001, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x808221d5, 0x000504ff, 0xffff3eaa, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x19ff0200, 0x19ff0200, 0x19ff0200, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xc909988d, 0x920e301b, 0xff03ffff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x81680256, 0x02cf023e, 0xff00016d, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x06b57b82, 0x00dbefc7, 0x0b8f073c, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x011a0000, 0x01330000, 0x00000000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x7f800478, 0xfdff07ef, 0x00000000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x41826201, 0x03040200, 0x7effc102, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x80710068, 0x00000000, 0xffe100cf, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xfff9ff00, 0xfff9ff00, 0xfff9ff00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x017a060b, 0x01700015, 0x01830c00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x70419937, 0xdf7c3200, 0x0006ff6d, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x39000280, 0x3e0002ff, 0x33000201, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x1a6e4780, 0x00000000, 0x33db8eff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0005184f, 0x00081099, 0x00011f04, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xff458097, 0xff0eaa31, 0xff7c55fd, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x6e087001, 0x0000df01, 0xdb100000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x060380c3, 0x05050187, 0x0601ffff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xff68ffa4, 0xff00ff49, 0xffcfffff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x6338f018, 0xaa0fe100, 0x1b60fe30, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x19000437, 0x00000000, 0x3200086d, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x02407d82, 0x0078f8ff, 0x04070205, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x20809700, 0x33ff2e00, 0x0d00ff00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x03808080, 0x00000000, 0x06ffffff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x06020001, 0x00040000, 0x0c000001, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x66025af9, 0xc70099ff, 0x04041bf3, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x10031f0d, 0x00000000, 0x1f063e19, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x01800f20, 0x00ff1c3e, 0x01000102, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x834a26fc, 0x0f9202ff, 0xf70149f8, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x7e228301, 0xc103ff00, 0x3b400702, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x38686cf8, 0x00cf3fff, 0x700099f0, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x9f500890, 0xff240e81, 0x3f7c019f, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x77ff0005, 0x07ff0009, 0xe7ff0000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8000ff01, 0xff00ff00, 0x0000ff02, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0c2e7c42, 0x00550017, 0x1707f76d, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x09820473, 0x0f0506df, 0x03ff0107, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x011a020f, 0x0000001c, 0x01330302, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xcc977a1b, 0xffc70333, 0x9966f003, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x032b7800, 0x0555f000, 0x00000000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x7a118001, 0xf11fff00, 0x03020002, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xdb110d14, 0xff1d1626, 0xb6040401, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x7e800700, 0xfc010000, 0x00ff0e00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x47309703, 0x00002e00, 0x8e60ff05, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xb9503808, 0xff9f700f, 0x72010000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xd38c7211, 0xef30e022, 0xb6e70400, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8480e004, 0x0800df00, 0xffffe108, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xa0803e80, 0x4fff0e00, 0xf0006dff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8b808013, 0x17ffff1e, 0xff000008, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x02808289, 0x0000ff12, 0x04ff05ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x081072f7, 0x1020e3ef, 0x000000ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x10362c04, 0x10220601, 0x10495206, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x4e2bff0e, 0x4e2bff0e, 0x4e2bff0e, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xff38921f, 0xff38921f, 0xff38921f, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0b02011a, 0x04030110, 0x12000024, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x067a92e7, 0x0cef24ff, 0x0004ffcf, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x07012102, 0x0c000403, 0x01013d00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x72804880, 0x030102ff, 0xe0ff8e00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0029713c, 0x0029713c, 0x0029713c, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x01012b39, 0x02010000, 0x00005571, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0e640000, 0x01000000, 0x1bc70000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x4d030084, 0x0a0000ff, 0x8f060009, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0b191de3, 0x000101c7, 0x163039ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x92ff6a00, 0x92ff6a00, 0x92ff6a00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x9e80ffff, 0xff00fffe, 0x3dffffff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x80146725, 0x00038f00, 0xff243e49, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x08098806, 0x10111000, 0x0000ff0c, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x99046100, 0x4007c100, 0xf1000000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x800e8002, 0xff0c0100, 0x0010ff03, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x4f7d0010, 0x1ecc001d, 0x7f2e0003, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x55803302, 0x1bff3804, 0x8e002d00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0e0cda80, 0x0018c300, 0x1c00f0ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x60e64808, 0x00ff0000, 0xc0cc8f10, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x80002103, 0x00003f06, 0xff000200, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xa2010026, 0x6801000f, 0xdb00003c, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0380ed18, 0x0000db0f, 0x06ffff21, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x14a53780, 0x00ff6dff, 0x274b0000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x579c0168, 0x0ff800cf, 0x9f3f0100, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x044e002d, 0x0599005a, 0x02020000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8b3f9f4d, 0x16183e12, 0xff66ff87, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x1f6e0300, 0x02db0000, 0x3c000500, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x4a838001, 0x14ff0000, 0x7f06ff01, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x000000ff, 0x000000ff, 0x000000ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x367a0d00, 0x00001300, 0x6cf30700, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xf6034518, 0xf9057000, 0xf3001a30, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8c037705, 0xff010d01, 0x1804e108, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x3810dc04, 0x6d01bf00, 0x021ef907, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0051bc02, 0x000f8700, 0x0092f003, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xb0065e80, 0x60002cff, 0xff0b8f00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0470a501, 0x04dfcc01, 0x04007e00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x20013008, 0x40016003, 0x0000000d, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x67010004, 0xc7000007, 0x07020000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x41868080, 0x71ff00ff, 0x110cff01, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x70931e50, 0x00ff009f, 0xe0263c01, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x2380020d, 0x46000413, 0x00ff0006, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x67080000, 0x01000000, 0xcc0f0000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x95824283, 0x2aff83e3, 0xff050122, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x039b037f, 0x02ff0500, 0x033701fd, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x68440005, 0xcc690007, 0x031f0002, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x01fb2bc3, 0x02fd00ff, 0x00f95587, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x3c500180, 0x71920100, 0x070e00ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x80000600, 0x00000000, 0xff000c00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x790380a1, 0xcc00ffc3, 0x2605017e, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xe4d92110, 0xf8b60300, 0xcffc3f1f, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0e07048e, 0x0e07048e, 0x0e07048e, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x46077c13, 0x83000025, 0x080ef700, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x7378a285, 0xdff08e0a, 0x0600b6ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0260ff17, 0x01bfff28, 0x0200ff05, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x86ff0001, 0xccff0000, 0x3fff0002, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0fde807f, 0x1ec3ffe0, 0x00f8001e, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x093c0c0a, 0x0f000c0f, 0x03780b05, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x31db780c, 0x00e7ef00, 0x61cf0018, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8af1b62b, 0x33ffff00, 0xe0e36d55, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xbf015202, 0xff008704, 0x7f011d00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xf5177e70, 0xf32a00cf, 0xf703fc10, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x00003705, 0x00006d0a, 0x00000000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x80fb071e, 0xffff0d3c, 0x00f70100, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x46101b3a, 0x1c013306, 0x701f026d, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x87802080, 0xff0300e7, 0x0ffc3f18, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x1020019f, 0x1e3200ff, 0x010d013e, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x80001852, 0xff000038, 0x0000306b, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x00841b83, 0x00083607, 0x00ff00ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x6e1a863e, 0x0003fc7c, 0xdb300f00, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x740efcbc, 0xe718f8f9, 0x0104ff7e, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x6ee08783, 0x0dcf0f06, 0xcff0ffff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x88f60c74, 0xfff00000, 0x10fc18e7, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0f9bffc3, 0x09ffff87, 0x1437ffff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x01cb8080, 0x02993900, 0x00fdc7ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8000822d, 0xff00ff01, 0x00000558, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x43760a2c, 0x81df0030, 0x050d1327, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x03191013, 0x05010020, 0x00301f05, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x3e810003, 0x7bff0000, 0x00030005, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x1800000f, 0x3000001e, 0x00000000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xfe80aab3, 0xfdff7166, 0xff00e3ff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x39ff1a9f, 0x01ff15b6, 0x70fe1e87, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xf307141e, 0xe70c0c05, 0xff011b37, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x80801a37, 0xff01106d, 0x00ff2400, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x01009488, 0x0000fd8f, 0x01002b81, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x711f025c, 0x020001b6, 0xdf3e0301, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x03789804, 0x03003003, 0x03efff04, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x6e000061, 0xdb0000c1, 0x00000000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x82ffb82e, 0x04ffff0a, 0xffff7051, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x288cff3b, 0x4918ff74, 0x06ffff02, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x00f7ff18, 0x00f7ff18, 0x00f7ff18, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x12550c04, 0x00000007, 0x23aa1800, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x1e3e0350, 0x007c049f, 0x3b000100, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0b54ab1b, 0x0e0fff30, 0x07995606, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x3987c706, 0x721c8e0a, 0x00f1ff01, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x80108b17, 0xff203624, 0x0000df09, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x60038016, 0xbf050008, 0x0001ff24, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xffff8301, 0xffffff00, 0xffff0701, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x2b060d80, 0x00000000, 0x550c1aff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x84ff003a, 0x08ff006d, 0xffff0006, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x450d0026, 0x450d0026, 0x450d0026, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x19018304, 0x3001ff07, 0x01000600, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x3f640980, 0x7cc70401, 0x02010eff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x80788084, 0x000000ff, 0xfff0ff08, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x47ff3880, 0x7fff00ff, 0x0eff7001, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x403b920a, 0x0249ff00, 0x7e2d2414, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x4881823b, 0x02030504, 0x8effff71, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x44648141, 0x0000027e, 0x87c7ff03, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x08842113, 0x0ccc041e, 0x033c3e07, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xbf6bc74c, 0x7ec08e18, 0xff16ff7f, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x0180010f, 0x00000000, 0x02ff011d, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x805b3c00, 0x00000000, 0xffb67800, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8d66480e, 0xff3e8f00, 0x1b8e001b, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x00ff8513, 0x00ff0a0b, 0x00ffff1a, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8080fffe, 0x0000fffd, 0xffffffff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0xfc860f34, 0xff0c1859, 0xf9ff060e, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x00000680, 0x00000bff, 0x00000000, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x80c3dba8, 0xff87b68f, 0x00ffffc0, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x10ff37c5, 0x1fff00f0, 0x00ff6d99, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x01017f1c, 0x0201fd30, 0x00010007, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x7100170f, 0xe100261d, 0x00000801, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x84800587, 0x090008ff, 0xffff010f, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x4d41ff93, 0x997eff26, 0x0103ffff, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8c7c0878, 0x18f70000, 0xff000fef, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x8148060e, 0xff8f0500, 0x0200071c, 0x0, 0x0 + dspck_dstio adduh_r.qb, 0x9f8c8005, 0xffffff09, 0x3e180000, 0x0, 0x0 + + writemsg "[6] Test append" + dspck_tsimm append, 0x00000090, 0x00000000, 0x079f2390, 8 + dspck_tsimm append, 0x00000001, 0x00000000, 0x008a1001, 1 + dspck_tsimm append, 0x09f0acd0, 0x09f0acd0, 0xf8000003, 0 + dspck_tsimm append, 0x80000019, 0x00000019, 0x00000019, 31 + dspck_tsimm append, 0xfffffff0, 0x00000003, 0x7ffffff0, 31 + dspck_tsimm append, 0x3b92e92e, 0x0073b92e, 0x0073b92e, 12 + dspck_tsimm append, 0x4000001f, 0x80000000, 0xc000001f, 31 + dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0x7fffffff, 0 + dspck_tsimm append, 0x40000001, 0x3ffffff0, 0xc0000001, 31 + dspck_tsimm append, 0xdff59020, 0xeffac810, 0x80000000, 1 + dspck_tsimm append, 0x0dbb0000, 0x00000dbb, 0x00000000, 16 + dspck_tsimm append, 0x000f0084, 0x0000000f, 0x00000084, 16 + dspck_tsimm append, 0x00000007, 0x00000000, 0xe0000007, 5 + dspck_tsimm append, 0x00000003, 0x80000000, 0x00003423, 3 + dspck_tsimm append, 0x00165235, 0x00165235, 0x00000007, 0 + dspck_tsimm append, 0xfdd29c98, 0xfdd29c98, 0xffffbef0, 0 + dspck_tsimm append, 0xff00ff00, 0xff00ff00, 0xfffd7cd8, 0 + dspck_tsimm append, 0xf8071c71, 0xff00ff00, 0x71c71c71, 19 + dspck_tsimm append, 0xfec36c54, 0xffd86d8a, 0xcccccccc, 3 + dspck_tsimm append, 0xffffdffe, 0x07fffffe, 0x07fffffe, 13 + dspck_tsimm append, 0xffffffec, 0xfffffffe, 0x3ffffffc, 4 + dspck_tsimm append, 0x80000000, 0x80000000, 0x7ffffff9, 0 + dspck_tsimm append, 0xfffffff0, 0xfffffff0, 0x3ffffffc, 0 + dspck_tsimm append, 0xffc3d805, 0xfffff87b, 0x00000005, 11 + dspck_tsimm append, 0x00000003, 0x80000000, 0xfffffffb, 2 + dspck_tsimm append, 0xffffffff, 0x7fffffff, 0x7fffffff, 31 + dspck_tsimm append, 0x80000000, 0xff36a999, 0x80000000, 31 + dspck_tsimm append, 0x80000000, 0x80000000, 0xf8000003, 0 + dspck_tsimm append, 0xe000000e, 0xfc000001, 0xb6db6db6, 3 + dspck_tsimm append, 0xffffffff, 0x7fffffff, 0x0000ffff, 1 + dspck_tsimm append, 0x00000006, 0xc0000001, 0x00000002, 2 + dspck_tsimm append, 0x000001bd, 0x00000000, 0x000001bd, 31 + dspck_tsimm append, 0xf8000001, 0xf8000001, 0x80000000, 0 + dspck_tsimm append, 0x07e0001b, 0x0000003f, 0x0000001b, 21 + dspck_tsimm append, 0x8ffffffe, 0x7fffffff, 0x0ffffffe, 31 + dspck_tsimm append, 0x0000006f, 0x0000006f, 0xffffff80, 0 + dspck_tsimm append, 0xffca4380, 0xffff290e, 0x7fffffc0, 6 + dspck_tsimm append, 0x00000000, 0x80000000, 0x80000000, 16 + dspck_tsimm append, 0x3ffffffd, 0x1ffffffe, 0x7fffffff, 1 + dspck_tsimm append, 0x00000005, 0x00000000, 0xfffffc5d, 3 + dspck_tsimm append, 0x8000001f, 0x8000001f, 0x00000000, 0 + dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0xfffffffc, 0 + dspck_tsimm append, 0x08f97af2, 0xffe09f08, 0xfff97af2, 24 + dspck_tsimm append, 0x00000000, 0x00000000, 0x80000000, 0 + dspck_tsimm append, 0x80000002, 0x80000002, 0xffffffe3, 0 + dspck_tsimm append, 0x000011f9, 0x0ffffffe, 0x000011f9, 31 + dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0xffdf9521, 0 + dspck_tsimm append, 0x0000002d, 0x80000000, 0xfff9cbad, 7 + dspck_tsimm append, 0x24924924, 0xb6db6db6, 0x24924924, 31 + dspck_tsimm append, 0xfe000001, 0x0000007f, 0x00000001, 25 + dspck_tsimm append, 0x7ffffff9, 0x00000000, 0xfffffff9, 31 + dspck_tsimm append, 0x80000000, 0x80000000, 0x71c71c71, 0 + dspck_tsimm append, 0xb6dbffff, 0x6db6db6d, 0x7fffffff, 17 + dspck_tsimm append, 0x000000b3, 0x80000000, 0x00f042b3, 8 + dspck_tsimm append, 0xb0000000, 0x0a72ad2b, 0x00000000, 28 + dspck_tsimm append, 0x00000000, 0x00000000, 0x3ffffff8, 3 + dspck_tsimm append, 0xc71c71c7, 0xc71c71c7, 0x007ec075, 0 + dspck_tsimm append, 0xfff3ff87, 0xfffffffc, 0xffffff87, 18 + dspck_tsimm append, 0x029129e0, 0x0052253c, 0x00000000, 3 + dspck_tsimm append, 0x7fffffc4, 0x0ffffff8, 0x0003a09c, 3 + dspck_tsimm append, 0xfffffe02, 0xffffff80, 0xffe06586, 2 + dspck_tsimm append, 0x80000006, 0x7fffffff, 0x80000006, 31 + dspck_tsimm append, 0x80000000, 0x80000000, 0x0000ffff, 0 + dspck_tsimm append, 0xf9820006, 0xfffff982, 0x80000006, 16 + dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0x7ffffffc, 0 + dspck_tsimm append, 0xfffffff9, 0x7fffffff, 0xfffffff9, 7 + dspck_tsimm append, 0x8000000f, 0x8000000f, 0x00000000, 0 + dspck_tsimm append, 0x00000000, 0x00000000, 0x80000000, 31 + dspck_tsimm append, 0x00000000, 0x80000000, 0x00000000, 31 + dspck_tsimm append, 0x92492492, 0x49249249, 0x00000000, 1 + dspck_tsimm append, 0xfffffffc, 0x7fffffff, 0x00000000, 2 + dspck_tsimm append, 0x80000000, 0x00ff00ff, 0x00000000, 31 + dspck_tsimm append, 0xfffffffc, 0x7fffffff, 0x0ffffffc, 28 + dspck_tsimm append, 0x0000198c, 0x00000006, 0x0000198c, 31 + dspck_tsimm append, 0x80000000, 0x80000000, 0x80000000, 0 + dspck_tsimm append, 0xe0c44a9f, 0xfc188953, 0x80000007, 3 + dspck_tsimm append, 0xffffffe7, 0xffffffe7, 0x0000001f, 0 + dspck_tsimm append, 0xfffe0000, 0x7fffffff, 0x80000000, 17 + dspck_tsimm append, 0x7ffffffc, 0x7ffffffc, 0x000b2d36, 0 + dspck_tsimm append, 0xe0000000, 0x80000007, 0x80000000, 29 + dspck_tsimm append, 0x8000003f, 0x8000003f, 0x00000000, 0 + dspck_tsimm append, 0x00f73453, 0xfffd9cce, 0x00f73453, 31 + dspck_tsimm append, 0x00000003, 0x00000000, 0xc0000003, 2 + dspck_tsimm append, 0xf0000001, 0xf0000001, 0x80000000, 0 + dspck_tsimm append, 0x0004000f, 0xf0000001, 0x8000000f, 18 + dspck_tsimm append, 0x00003800, 0x00000007, 0x00000000, 11 + dspck_tsimm append, 0x00000000, 0x00000000, 0x80000000, 0 + dspck_tsimm append, 0xbb4000ff, 0x001745da, 0x000000ff, 21 + dspck_tsimm append, 0x00000002, 0x00000001, 0x38e38e38, 1 + dspck_tsimm append, 0x7ffff89a, 0xfffffffa, 0xfffff89a, 31 + dspck_tsimm append, 0x00000000, 0x7fffff80, 0x00000000, 31 + dspck_tsimm append, 0x80000007, 0x80000007, 0x80000007, 0 + dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0xfffff895, 0 + dspck_tsimm append, 0xfbd4ecf0, 0xfef53b3c, 0x3ffffff8, 2 + dspck_tsimm append, 0xffe00000, 0xfffffff0, 0x80000000, 17 + dspck_tsimm append, 0x0000007f, 0x80000000, 0x7fffffff, 7 + dspck_tsimm append, 0x40000007, 0x80000000, 0xc0000007, 31 + dspck_tsimm append, 0x0000007a, 0xc000000f, 0x92492492, 3 + dspck_tsimm append, 0x0000000f, 0x00000007, 0x71c71c71, 1 + dspck_tsimm append, 0xfffffec4, 0xfffffec4, 0xfffffec4, 0 + dspck_tsimm append, 0x80000000, 0x80000000, 0xff6693b4, 0 + dspck_tsimm append, 0x0ffffff8, 0x80000000, 0x0ffffff8, 31 + dspck_tsimm append, 0xfffffffe, 0x7fffffff, 0xf320ad72, 1 + dspck_tsimm append, 0x0000000a, 0x00000000, 0x0000000a, 13 + dspck_tsimm append, 0xffffffff, 0x7fffffff, 0xffffffe5, 1 + dspck_tsimm append, 0xfffffe38, 0x7fffffff, 0x38e38e38, 9 + dspck_tsimm append, 0xfffffffe, 0x7fffffff, 0xfffffffe, 10 + dspck_tsimm append, 0x0000000e, 0x00000000, 0x8e38e38e, 7 + dspck_tsimm append, 0x001b738b, 0x00000db9, 0xfff9d38b, 9 + dspck_tsimm append, 0x24924924, 0xffd5e328, 0x24924924, 31 + dspck_tsimm append, 0x00037864, 0x00037864, 0xffff0000, 0 + dspck_tsimm append, 0xfd43c708, 0xff50f1c2, 0x80000000, 2 + dspck_tsimm append, 0x80000000, 0x80000000, 0x80000000, 0 + dspck_tsimm append, 0xfffffffe, 0x7fffffff, 0x80000000, 1 + dspck_tsimm append, 0x00180007, 0x00000006, 0x00000007, 18 + dspck_tsimm append, 0xffffff0c, 0xffffff0c, 0x7fffffff, 0 + dspck_tsimm append, 0xfffec000, 0xffffffec, 0x80000000, 12 + dspck_tsimm append, 0x0000003f, 0x80000003, 0x0000000f, 4 + dspck_tsimm append, 0xe46796e9, 0xff849723, 0x000796e9, 21 + dspck_tsimm append, 0xffffffff, 0x7fffffff, 0xc71c71c7, 2 + dspck_tsimm append, 0xfffffff0, 0xfffffff0, 0x80000006, 0 + dspck_tsimm append, 0x000007f8, 0x000000ff, 0x00000000, 3 + dspck_tsimm append, 0x05900000, 0xfffa4164, 0x00000000, 18 + dspck_tsimm append, 0x000003ff, 0x0000003f, 0x7fffffff, 4 + dspck_tsimm append, 0x78000001, 0x0004372e, 0xf8000001, 31 + dspck_tsimm append, 0xfefffffb, 0xfffffffb, 0xfffffffb, 22 + dspck_tsimm append, 0x020f6aac, 0x0000107b, 0x006feaac, 13 + dspck_tsimm append, 0x0000003c, 0x0000000f, 0x3fffffe0, 2 + dspck_tsimm append, 0xf50dfa1d, 0xfea1bf43, 0xfffffffd, 3 + dspck_tsimm append, 0xb512a800, 0xfff6a255, 0x00000000, 11 + dspck_tsimm append, 0x80023a3b, 0x0ad67261, 0x00023a3b, 31 + dspck_tsimm append, 0xf9999999, 0x0000001f, 0x99999999, 29 + dspck_tsimm append, 0x00026381, 0x000004c7, 0x00000001, 7 + dspck_tsimm append, 0x80000000, 0x00000007, 0x00000000, 31 + dspck_tsimm append, 0xffff7bfc, 0xffff7bfc, 0xffffd30b, 0 + dspck_tsimm append, 0x000005f8, 0x80000002, 0x3ffffff8, 9 + dspck_tsimm append, 0x7ffffffe, 0x00000000, 0xfffffffe, 31 + dspck_tsimm append, 0x029735d1, 0x029735d1, 0xffffe9b6, 0 + dspck_tsimm append, 0x80002246, 0xffffffff, 0x00002246, 31 + dspck_tsimm append, 0xfffffe7b, 0xfffffe7b, 0x00006e8f, 0 + dspck_tsimm append, 0x000009c8, 0x00000139, 0xff00ff00, 3 + dspck_tsimm append, 0xe0000007, 0x7ffffffb, 0xe0000007, 31 + dspck_tsimm append, 0xffffffff, 0x7fffffff, 0x00000017, 3 + dspck_tsimm append, 0x0000001f, 0x0000000f, 0x7fffffff, 1 + dspck_tsimm append, 0x000076aa, 0x00000000, 0xf03a76aa, 17 + dspck_tsimm append, 0xfffffff0, 0x7fffffff, 0x80000000, 4 + dspck_tsimm append, 0x0000003e, 0x00000007, 0xfb1e10f6, 3 + dspck_tsimm append, 0x0000ffff, 0x0000ffff, 0x92492492, 0 + dspck_tsimm append, 0x0000001f, 0x80000000, 0x0000001f, 31 + dspck_tsimm append, 0xffff81dc, 0xfffff03b, 0xffffc1bc, 3 + dspck_tsimm append, 0x00001e3d, 0x00000000, 0x00001e3d, 28 + dspck_tsimm append, 0xffb26ef1, 0xfff64dde, 0x00000001, 3 + dspck_tsimm append, 0x0ffffff8, 0x00000001, 0xfffffff8, 27 + dspck_tsimm append, 0x00001c46, 0x00000e23, 0x80000000, 1 + dspck_tsimm append, 0xfffe03fe, 0xffffff01, 0xfffffffe, 9 + dspck_tsimm append, 0x8410795a, 0x7fffffff, 0x0410795a, 31 + dspck_tsimm append, 0xffffc223, 0xffffff84, 0xffff81a3, 7 + dspck_tsimm append, 0x00000000, 0x00000000, 0xfbd3119d, 0 + dspck_tsimm append, 0x00000000, 0x00000000, 0xfff4148a, 1 + dspck_tsimm append, 0xffff8a84, 0xfffff150, 0xe468dc34, 3 + dspck_tsimm append, 0x00000000, 0x00000000, 0x00000000, 0 + dspck_tsimm append, 0x00003ffe, 0x80000000, 0xfffffffe, 14 + dspck_tsimm append, 0x00000000, 0x80000000, 0xfe261ae0, 3 + dspck_tsimm append, 0x0000003e, 0x0000003e, 0x0000006d, 0 + dspck_tsimm append, 0x00000000, 0x07fffffe, 0x80000000, 31 + dspck_tsimm append, 0x00e4fe00, 0x0001c9fc, 0x80000000, 7 + dspck_tsimm append, 0x7f00ff00, 0xff804b6c, 0xff00ff00, 31 + dspck_tsimm append, 0xfffff000, 0x7ffffffc, 0x80000000, 10 + dspck_tsimm append, 0x00000002, 0x00000001, 0x1ffffffe, 1 + dspck_tsimm append, 0xf072726f, 0x7fffffff, 0x0072726f, 28 + dspck_tsimm append, 0x80000002, 0x80000002, 0x7fffffff, 0 + dspck_tsimm append, 0x00013d29, 0x000027a5, 0xff4cd0b9, 3 + dspck_tsimm append, 0x20000000, 0x2b1945c4, 0x00000000, 27 + dspck_tsimm append, 0xfffff000, 0x7fffffff, 0x00000000, 12 + dspck_tsimm append, 0xf5b64a46, 0xf5b64a46, 0x8000001f, 0 + dspck_tsimm append, 0xe0000007, 0xe0000007, 0x80000000, 0 + dspck_tsimm append, 0x00000017, 0x80000001, 0x00009bc7, 4 + dspck_tsimm append, 0x0000003f, 0xf0000003, 0x7fffffff, 4 + dspck_tsimm append, 0x80000000, 0xf8000003, 0x00000000, 31 + dspck_tsimm append, 0xfffffb48, 0x7fffffff, 0xfffffb48, 31 + dspck_tsimm append, 0x00000004, 0x00000004, 0x80000000, 0 + dspck_tsimm append, 0xa5800000, 0x00007296, 0x80000000, 22 + dspck_tsimm append, 0xc71c401f, 0x71c71c71, 0x8000001f, 14 + dspck_tsimm append, 0x8000001f, 0x8000001f, 0x000000f2, 0 + dspck_tsimm append, 0x08dacc7f, 0x00a411b5, 0xffbe4c7f, 15 + dspck_tsimm append, 0x00003fe0, 0x000000ff, 0xffffffe0, 6 + dspck_tsimm append, 0x07305dfd, 0xffdc1cc1, 0x037a5dfd, 14 + dspck_tsimm append, 0xcccccccc, 0xcccccccc, 0x00066420, 0 + dspck_tsimm append, 0xfffffff6, 0x7ffffffb, 0x00000000, 1 + dspck_tsimm append, 0x00000007, 0x80000000, 0xf0000007, 3 + dspck_tsimm append, 0xff000001, 0x7fffffff, 0xf8000001, 24 + dspck_tsimm append, 0xffffffff, 0x7fffffff, 0x7fffffff, 28 + dspck_tsimm append, 0x8c7ffff9, 0xfffffa31, 0x7ffffff9, 22 + dspck_tsimm append, 0x8000003f, 0xffffffff, 0x8000003f, 31 + dspck_tsimm append, 0x0000000f, 0x0000000f, 0xffffffc0, 0 + dspck_tsimm append, 0xf0000003, 0xf0000003, 0x80000000, 0 + dspck_tsimm append, 0x00002b44, 0x80000000, 0x00042b44, 14 + dspck_tsimm append, 0x76680c00, 0xed1d9a03, 0x80000000, 10 + dspck_tsimm append, 0x000d3ca7, 0x000d3ca7, 0x7fffffff, 0 + dspck_tsimm append, 0xffffb15c, 0x7fffffff, 0x0029b15c, 15 + dspck_tsimm append, 0xfffffffb, 0x7fffffff, 0xff80a663, 3 + dspck_tsimm append, 0x000018b3, 0x00000c59, 0x000944f9, 1 + dspck_tsimm append, 0x80000000, 0x80000000, 0x80000000, 0 + dspck_tsimm append, 0xfffffa00, 0xfffffffd, 0x00000000, 9 + dspck_tsimm append, 0x38e38e38, 0x1c71c71c, 0xf0f0f0f0, 1 + dspck_tsimm append, 0x00000b58, 0x00000b58, 0xffe0425f, 0 + dspck_tsimm append, 0x0000001c, 0x00000007, 0x80000000, 2 + dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0x0545da72, 0 + dspck_tsimm append, 0x2bffffff, 0x001bef2b, 0x7fffffff, 24 + dspck_tsimm append, 0x000000c7, 0x00000000, 0xc71c71c7, 8 + dspck_tsimm append, 0xffff5ffe, 0xffffffd7, 0xfffffffe, 10 + dspck_tsimm append, 0xffffff80, 0xffffffe0, 0x00000000, 2 + dspck_tsimm append, 0xffffffcc, 0x0ffffffc, 0xfffceb9c, 4 + dspck_tsimm append, 0x036d1448, 0x00036d14, 0xffff2348, 8 + dspck_tsimm append, 0xcb0fffff, 0xffff5961, 0x7fffffff, 19 + dspck_tsimm append, 0x00000000, 0x00000000, 0x00000000, 0 + dspck_tsimm append, 0xfffffffe, 0x7fffffff, 0x80000000, 1 + dspck_tsimm append, 0xffffffff, 0xffffffff, 0x7fffffff, 1 + dspck_tsimm append, 0xfffffffd, 0x7fffffff, 0x00000225, 3 + dspck_tsimm append, 0xe0000000, 0x00ff00ff, 0x80000000, 29 + dspck_tsimm append, 0xfffffff7, 0xfffffff7, 0x71c71c71, 0 + dspck_tsimm append, 0xffc00002, 0xfffffffe, 0x80000002, 21 + dspck_tsimm append, 0x00000003, 0x00000000, 0x00000027, 2 + dspck_tsimm append, 0xfffffff8, 0x7fffffff, 0x0ffffff8, 9 + dspck_tsimm append, 0x51a45fff, 0x00328d22, 0x7fffffff, 13 + dspck_tsimm append, 0x00003f00, 0x00000000, 0xffffff00, 14 + dspck_tsimm append, 0x00000004, 0x00000004, 0x00000000, 0 + dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0xfeec3b3a, 0 + dspck_tsimm append, 0x80000000, 0x80000000, 0xfc07f8c2, 0 + dspck_tsimm append, 0x8000006b, 0xfc000001, 0x0000006b, 31 + dspck_tsimm append, 0xffff9db6, 0x7fffffff, 0xffff9db6, 18 + dspck_tsimm append, 0x00000000, 0x00000000, 0xe38e38e3, 0 + dspck_tsimm append, 0xffffffff, 0x7fffffff, 0xffffffff, 14 + dspck_tsimm append, 0x05ec1bfc, 0x00017b06, 0x07fffffc, 10 + dspck_tsimm append, 0xff800000, 0xffffffe0, 0x80000000, 18 + dspck_tsimm append, 0xffffffff, 0x7fffffff, 0x7fffffff, 19 + dspck_tsimm append, 0x8f0f0f0f, 0x7fffffff, 0x0f0f0f0f, 31 + dspck_tsimm append, 0x38e38e39, 0x1c71c71c, 0xfffffffb, 1 + dspck_tsimm append, 0x1c71c71c, 0x1c71c71c, 0xffffc119, 0 + dspck_tsimm append, 0x00000004, 0x00000004, 0x80000000, 0 + dspck_tsimm append, 0x00000005, 0x80000000, 0x00000005, 27 + dspck_tsimm append, 0xfffffe00, 0xfffffffe, 0x00000000, 8 + + writemsg "[7] Test balign" + dspck_tsimm balign, 0x1f01fd01, 0x001f01fd, 0x015ca9c0, 1 + dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000000, 3 + dspck_tsimm balign, 0x710000f7, 0x71c71c71, 0x0000f73c, 3 + dspck_tsimm balign, 0x1b000000, 0x0000001b, 0x0000001b, 3 + dspck_tsimm balign, 0xf900248f, 0x7ffffff9, 0x00248f28, 3 + dspck_tsimm balign, 0x00003d00, 0x0000003d, 0x00000001, 1 + dspck_tsimm balign, 0xffff807f, 0x7fffff80, 0x7fffffff, 1 + dspck_tsimm balign, 0x4b000000, 0x0000004b, 0x00000000, 3 + dspck_tsimm balign, 0xffff8000, 0xffffff80, 0x002fdb08, 1 + dspck_tsimm balign, 0x0ab8dd00, 0x000ab8dd, 0x000064a2, 1 + dspck_tsimm balign, 0xffffffe2, 0x7fffffff, 0xe29d63ad, 1 + dspck_tsimm balign, 0xf803ffff, 0x3ffffff8, 0x03fffffe, 3 + dspck_tsimm balign, 0x3d800000, 0xfffe6a3d, 0x80000000, 3 + dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000000, 3 + dspck_tsimm balign, 0xffe96d00, 0xffffe96d, 0x00000000, 1 + dspck_tsimm balign, 0x000000c7, 0x80000000, 0xc71c71c7, 1 + dspck_tsimm balign, 0x3e8aac80, 0x003e8aac, 0x80000000, 1 + dspck_tsimm balign, 0x00000000, 0x80000000, 0x0000000f, 3 + dspck_tsimm balign, 0xfca3d07f, 0xfffca3d0, 0x7fffffff, 1 + dspck_tsimm balign, 0xffff8055, 0xffffff80, 0x55555555, 1 + dspck_tsimm balign, 0xffffffff, 0x7fffffff, 0xfffffff8, 1 + dspck_tsimm balign, 0x80ffffff, 0xffffff80, 0xffffff80, 3 + dspck_tsimm balign, 0x91000000, 0x0cf0c191, 0x00000000, 3 + dspck_tsimm balign, 0xffff5503, 0xffffff55, 0x0374dc74, 1 + dspck_tsimm balign, 0x000000c0, 0x80000000, 0xc0000001, 1 + dspck_tsimm balign, 0x0000087f, 0x00000008, 0x7fffffff, 1 + dspck_tsimm balign, 0xe7050500, 0xffe70505, 0x00000069, 1 + dspck_tsimm balign, 0x007fffff, 0x00000000, 0x7fffffff, 3 + dspck_tsimm balign, 0xffffe0ff, 0xffffffe0, 0xffffffe0, 1 + dspck_tsimm balign, 0xfffffe00, 0x3ffffffe, 0x00000000, 1 + dspck_tsimm balign, 0xffff80ff, 0xffffff80, 0xffe4aca7, 1 + dspck_tsimm balign, 0x01800000, 0x00000001, 0x80000005, 3 + dspck_tsimm balign, 0x0fffffff, 0x0000000f, 0xffffff39, 3 + dspck_tsimm balign, 0xd05dfc00, 0x1bd05dfc, 0x004e7d52, 1 + dspck_tsimm balign, 0xf8fffa05, 0x0ffffff8, 0xfffa0520, 3 + dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000000, 1 + dspck_tsimm balign, 0xffffeeff, 0xffffffee, 0xff7ccdf7, 1 + dspck_tsimm balign, 0x00000180, 0x80000001, 0x80000001, 1 + dspck_tsimm balign, 0xfc7fffff, 0x3ffffffc, 0x7fffffc0, 3 + dspck_tsimm balign, 0xc71c7100, 0x71c71c71, 0x00000000, 1 + dspck_tsimm balign, 0x555555ff, 0x55555555, 0xffff0000, 1 + dspck_tsimm balign, 0x33f80000, 0x02f67833, 0xf8000001, 3 + dspck_tsimm balign, 0x03029747, 0xf0000003, 0x029747e5, 3 + dspck_tsimm balign, 0x00516bff, 0x0000516b, 0xfffffd33, 1 + dspck_tsimm balign, 0xf86db6db, 0x7ffffff8, 0x6db6db6d, 3 + dspck_tsimm balign, 0xf87fffff, 0x0ffffff8, 0x7fffffff, 3 + dspck_tsimm balign, 0x107fffff, 0x00018c10, 0x7fffffff, 3 + dspck_tsimm balign, 0xf2a6e180, 0xfff2a6e1, 0x80000000, 1 + dspck_tsimm balign, 0x0000000f, 0x80000000, 0x0ffffffe, 1 + dspck_tsimm balign, 0x000000e0, 0x00000000, 0xe0000001, 1 + dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000000, 1 + dspck_tsimm balign, 0x5b00193c, 0xffff9e5b, 0x00193cb0, 3 + dspck_tsimm balign, 0x0000007f, 0x80000000, 0x7fffffff, 1 + dspck_tsimm balign, 0x0000070f, 0x80000007, 0x0ffffffc, 1 + dspck_tsimm balign, 0xff0f0f0f, 0x7fffffff, 0x0f0f0f0f, 3 + dspck_tsimm balign, 0xefc00000, 0xffffffef, 0xc0000001, 3 + dspck_tsimm balign, 0x00000c0f, 0x0000000c, 0x0ffffffc, 1 + dspck_tsimm balign, 0x05000000, 0x00000005, 0x00000001, 3 + dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000007, 1 + dspck_tsimm balign, 0x0effffff, 0xffff300e, 0xfffffffe, 3 + dspck_tsimm balign, 0x1fffeb60, 0x8000001f, 0xffeb607e, 3 + dspck_tsimm balign, 0x10bbe280, 0x0110bbe2, 0x80000004, 1 + dspck_tsimm balign, 0xffe25c1f, 0xffffe25c, 0x1ffffffc, 1 + dspck_tsimm balign, 0xffffffff, 0x00ff00ff, 0xfffffffb, 3 + dspck_tsimm balign, 0x00000000, 0x00000000, 0x00f2f43d, 1 + dspck_tsimm balign, 0xffb97400, 0xffffb974, 0x00000000, 1 + dspck_tsimm balign, 0xfffa5400, 0xfffffa54, 0x00000000, 1 + dspck_tsimm balign, 0x4d000543, 0x0005434d, 0x0005434d, 3 + dspck_tsimm balign, 0x00000080, 0x80000000, 0x80000000, 1 + dspck_tsimm balign, 0xfffe1fff, 0xfffffe1f, 0xfffffffe, 1 + dspck_tsimm balign, 0x000000aa, 0x80000000, 0xaaaaaaaa, 1 + dspck_tsimm balign, 0xfffff6c0, 0xfffffff6, 0xc000001f, 1 + dspck_tsimm balign, 0xffffff00, 0x7fffffff, 0x00000000, 1 + dspck_tsimm balign, 0xff800000, 0x7fffffff, 0x80000000, 3 + dspck_tsimm balign, 0x00800000, 0x80000000, 0x80000000, 3 + dspck_tsimm balign, 0xffffffff, 0x7fffffff, 0xffffff00, 3 + dspck_tsimm balign, 0x00000380, 0x80000003, 0x80000000, 1 + dspck_tsimm balign, 0xf08e38e3, 0x1ffffff0, 0x8e38e38e, 3 + dspck_tsimm balign, 0xfffff800, 0xfffffff8, 0x00005016, 1 + dspck_tsimm balign, 0xff000000, 0x7fffffff, 0x00000000, 3 + dspck_tsimm balign, 0x00000700, 0x00000007, 0x00002153, 1 + dspck_tsimm balign, 0xff800000, 0xffffffff, 0x80000000, 3 + dspck_tsimm balign, 0xffffff80, 0x7fffffff, 0x80000000, 1 + dspck_tsimm balign, 0xfe000000, 0x0ffffffe, 0x00000000, 3 + dspck_tsimm balign, 0xfffffde7, 0xfffffffd, 0xe75d405c, 1 + dspck_tsimm balign, 0xfd982d7f, 0xfffd982d, 0x7fffffff, 1 + dspck_tsimm balign, 0xff7fffff, 0x7fffffff, 0x7ffffffe, 3 + dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000002, 3 + dspck_tsimm balign, 0x5e7fffff, 0xff8bdc5e, 0x7fffffff, 3 + dspck_tsimm balign, 0xffffffff, 0x7fffffff, 0xffffffe6, 1 + dspck_tsimm balign, 0x00007f00, 0x8000007f, 0x00001059, 1 + dspck_tsimm balign, 0x0000007f, 0x00000000, 0x7fffffff, 1 + dspck_tsimm balign, 0x51800000, 0x32b3c151, 0x80000006, 3 + dspck_tsimm balign, 0x000000c0, 0x00000000, 0xc000001f, 1 + dspck_tsimm balign, 0x00fff286, 0x80000000, 0xfff2864d, 3 + dspck_tsimm balign, 0x00001ae4, 0x00000000, 0x001ae4b6, 3 + dspck_tsimm balign, 0x00000300, 0xf8000003, 0x00000000, 1 + dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000000, 1 + dspck_tsimm balign, 0x06f655e9, 0x80000006, 0xf655e94f, 3 + dspck_tsimm balign, 0xff000000, 0x7fffffff, 0x000000a9, 3 + dspck_tsimm balign, 0x00000780, 0xc0000007, 0x80000001, 1 + dspck_tsimm balign, 0x60ffffff, 0xffff8860, 0xffffffc8, 3 + dspck_tsimm balign, 0xfffffef8, 0xfffffffe, 0xf8000001, 1 + dspck_tsimm balign, 0x000000db, 0x00000000, 0xdb6db6db, 1 + dspck_tsimm balign, 0xfd800000, 0xfffffffd, 0x80000001, 3 + dspck_tsimm balign, 0xf1800000, 0x0002e7f1, 0x80000000, 3 + dspck_tsimm balign, 0x0d000002, 0x0000000d, 0x000002f2, 3 + dspck_tsimm balign, 0xffffffff, 0x7fffffff, 0xfffffffd, 1 + dspck_tsimm balign, 0x00000000, 0x00000000, 0x0000001c, 1 + dspck_tsimm balign, 0xfffffa00, 0xfffffffa, 0x00000000, 1 + dspck_tsimm balign, 0xffffffff, 0x7fffffff, 0xffffe59b, 1 + dspck_tsimm balign, 0x00ffffff, 0x00000000, 0xfffffff9, 3 + dspck_tsimm balign, 0xffffff7f, 0x7fffffff, 0x7fffffff, 1 + dspck_tsimm balign, 0xfffffff9, 0xffffffff, 0xfffff92d, 3 + dspck_tsimm balign, 0xaaaaaaff, 0xaaaaaaaa, 0xffffedc7, 1 + dspck_tsimm balign, 0xffffff7f, 0x7fffffff, 0x7ffffff9, 1 + dspck_tsimm balign, 0x800e0ff8, 0xffffff80, 0x0e0ff8b5, 3 + dspck_tsimm balign, 0xfff36500, 0xfffff365, 0x00000005, 1 + dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000001, 1 + + writemsg "[8] Test cmpgdu.eq.qb" + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1ef101ff, 0x07270316, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x06cc0001, 0x24000102, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1f8fc0ff, 0x28001e24, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x03ff0001, 0x37ff0405, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0083ffdf, 0xfe000007, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x001000ff, 0x3fff0a12, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0xbfff0008, 0xc7000002, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x091c038e, 0x02600600, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff0801ff, 0xff00cc08, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x06ffc700, 0x0300830d, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x021f1e01, 0x3c000100, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0cff0a3e, 0xf73ee700, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1e00ff04, 0x00ff0fdf, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x01ff0106, 0x001d49ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x7f000000, 0x088100cc, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff3e3e01, 0xff010700, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x3800e3ff, 0x00000000, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x02fffe33, 0xf00b32ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xef1ff81e, 0x000e0f8e, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x04c02400, 0xff9f1355, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000009, 0x00000000, 0x0004ff00, 0x0, 0x09000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x00000000, 0x00021a3a, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x05000001, 0x0f0002f7, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x49aa3101, 0x00008fef, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x6bc30000, 0xf0ff01ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x13c10138, 0x3a380eff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x3c1f0000, 0xe000ff16, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x05efff26, 0xff001f03, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x0000000f, 0xff495500, 0xff495500, 0x0, 0x0f000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00e7ff2b, 0x4bff1eff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x33ffff78, 0x306d0018, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x17207c00, 0x021b006c, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0xff008003, 0x0200ff0f, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffe71605, 0xf30703ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x0e031e01, 0x3801aa01, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xfff939df, 0x2f001f00, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x70240080, 0x00000066, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x720aff00, 0x0033ff3f, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x21007219, 0x19ffff00, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x7f004508, 0x0000ff49, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x0000000f, 0x510000ff, 0x510000ff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff180000, 0xc0ffdf33, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x3e013603, 0x07ff4d3c, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x00f106ff, 0x9900ffff, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xffff0754, 0xff0117ff, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x0000000f, 0x1c0c0008, 0x1c0c0008, 0x0, 0x0f000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0808ccff, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff020012, 0x00f001ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x03ff0027, 0xf1014005, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xbf3312ff, 0x18ffff06, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00073004, 0x7eb60799, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x03feff00, 0x021cfcff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0xfeff0203, 0x00ff0409, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0xfdff7638, 0x000e0138, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x031effff, 0xc131077d, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x09c3c7ff, 0xdb000700, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x120c0055, 0x1133ff06, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x20ff0336, 0x0904403f, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1a007e00, 0x8301c0ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0b00ffc3, 0x00c018e3, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0000000e, 0xff05db6d, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xc3340000, 0x83ffff01, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x01e10078, 0x090caa0e, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0xff01ef00, 0x00000000, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x3bdf081e, 0x658eff71, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x0000000f, 0x0020dfff, 0x0020dfff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00ff0cb6, 0xf801db00, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00381a66, 0x01017501, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x01006600, 0x2d0006ff, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x00000000, 0x663300ff, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x001e00e7, 0x01064905, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0b26ffc0, 0x51160001, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x252f0300, 0x26004f0e, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00000000, 0x830a4a03, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x7b2b0200, 0x07aa0600, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x070000ff, 0xfff900f9, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff706dff, 0x24ff01df, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x3c050071, 0x10003eff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x703f0018, 0xe0003500, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff0ff803, 0x0b008335, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffff08aa, 0x063003f0, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0xef008e10, 0x00000000, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x09ff0000, 0x003f11ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x00000033, 0x04020000, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x05000114, 0x55ff070c, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff3d3870, 0xff007840, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x8055ff6d, 0x0cff38f3, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x00010024, 0x007999ff, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0200ff01, 0x7d380002, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0a062702, 0x00650bff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0xf9160002, 0xff8700ff, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x00000000, 0x1f293800, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x13000700, 0x01ffaa3d, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0101ff14, 0x00497102, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff7066ff, 0xc100db24, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x6a787000, 0x00247c6f, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x210000ff, 0x01ff1e1c, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x06ff7703, 0xff00f90e, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x27fc39ff, 0x00053e00, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffff3023, 0x65009f30, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xc78e0ccf, 0x003048ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0xe7920000, 0x00007f00, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff1ae1f8, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0049ff87, 0x01ff8f00, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00ff3855, 0xc30619ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x0400ffff, 0x0000030e, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x02300100, 0xfffddb00, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x0000000f, 0xfc000eff, 0xfc000eff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x2605032f, 0xff3381ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00ff11f9, 0xaa0e01ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1fff0a01, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x2a000201, 0x49ff0600, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0007ff3c, 0xffe70107, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00000000, 0x7c0c18db, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xc71d01ff, 0x00004900, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x8700e71f, 0x2500f739, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x83060570, 0xf9ff2002, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff003c00, 0xffffff02, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x2d09ffff, 0x020006ff, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00380c1c, 0x3800f9ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x000f04e3, 0x7f11382f, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x001eff00, 0xcc01ff04, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00107f00, 0x7f01048f, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x00000000, 0x00ffdbff, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0e30c107, 0x03ff1200, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0xc157ff00, 0x1c08ff03, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x4100ff00, 0x0804c070, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x01ff03ff, 0x00f800c0, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x00000a3d, 0x0c0000cc, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x60ff3801, 0xff0099e7, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x000500fc, 0x0100133c, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00b60113, 0x1eff0400, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0xff06ffff, 0x01ffff02, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x26000500, 0xffc3ff03, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00183e01, 0xff1ef0ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff00ffff, 0xff05251a, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x300000ff, 0x00000e04, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x001ec700, 0xff0303e7, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x000a16ff, 0x01001fff, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff550703, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x55010602, 0x1a208787, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x00ff02ff, 0xff026dff, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000005, 0x3effffff, 0x0eff20ff, 0x0, 0x05000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x49fd0004, 0xcf00fe66, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00064000, 0xf920ffff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0000fff9, 0xff1f00ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x008700ff, 0x00ff4000, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00ff87e0, 0x0e00ffff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x04ff0900, 0x3192ff06, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00000b06, 0xffff0104, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00ff1800, 0x8ec3f3f8, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xc18155e7, 0x0007130c, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0f1e0f08, 0xff3e0700, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x00ff8706, 0xb6ffffff, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x00000000, 0x2401ff00, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x010a0c18, 0x1c010000, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0b00f110, 0x320304aa, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x03ff0000, 0x13ffffc1, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1203fffd, 0x002e0180, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff0130e7, 0x01c0fff1, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x60001f1d, 0xfd04ff01, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0xe7093f00, 0x00000000, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x01df0c18, 0x00f9feff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x000060df, 0x0008ff00, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x80ff0400, 0x002403c7, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xe71e1f00, 0x02ff1cff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x8f9260ff, 0x9200c302, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x0000000f, 0x55117cff, 0x55117cff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffff01ff, 0x012c0078, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffe30702, 0x0c000083, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0371c092, 0xffe08f60, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00000000, 0x38ff0301, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff017c03, 0x8edf02ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff000000, 0xffb60c92, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x8100ff38, 0xff8f4aff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x000340ff, 0x02002002, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x00000000, 0x008f1c01, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x33183b51, 0x0a0afecc, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000005, 0x00000000, 0x06003000, 0x0, 0x05000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffff6020, 0x0008570f, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x6f71ffff, 0xffcf00ff, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x40aa3000, 0xff009202, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x8e03fee7, 0x132d0001, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0c71109f, 0xc0f9ffff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x0103009f, 0x01021f00, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0e0ac7c7, 0x06fd0bfe, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x000aff66, 0x040002c0, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffff01ff, 0x1109fd00, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x013a1c0f, 0x04010003, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x0009f1ff, 0x0000783e, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xf81e01ff, 0x0001837f, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0xffff0160, 0xaafffffc, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x001eff1f, 0x9f0a0301, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0xf9ffffc7, 0x00ff0200, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff030092, 0xffff0133, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1b00001e, 0x6f07ff14, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x3c000fff, 0x00ff0201, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1ff03f60, 0x01b6fe00, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x03062003, 0x87df80ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0a240104, 0x33010242, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x3200039f, 0x00ff0003, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0xcf00ff00, 0x0006ff03, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1f044401, 0x00008f2c, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0301ff03, 0x7c0001ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x8307c100, 0x00000000, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x0300e7ff, 0x52004902, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1f0f07c7, 0xff010100, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000009, 0x00ff0000, 0x0000ff00, 0x0, 0x09000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xf806c1ff, 0xffff06df, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x66383f0a, 0xaa07ff03, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x60db1e0a, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x01000cff, 0x00000000, 0x0, 0x04000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x002b71c0, 0xcf12ff0a, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x68098102, 0xfc788e00, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x24543c00, 0x7fbfff01, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x01ff8ff7, 0x24000033, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0101b670, 0xdf02ff05, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x60050000, 0xff040001, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff1f0c00, 0xff02ff06, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xf9fff834, 0xdf06c102, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000006, 0xc1000301, 0x4200030a, 0x0, 0x06000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00ff0200, 0x601c001f, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000009, 0x003e04ff, 0x001800ff, 0x0, 0x09000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0aff1a00, 0x3ec0000d, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000009, 0x0137fc71, 0x0102ff71, 0x0, 0x09000000 + dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x0055000e, 0x00e3dbff, 0x0, 0x08000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xe7e0ff1f, 0xff050701, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x813400ff, 0x666a0d01, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x1b73ffc0, 0x002dff78, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x251f0340, 0x2300ffff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x02ff3f00, 0x0001ff1d, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0002ff80, 0xf88300ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x01092400, 0x3e07cf00, 0x0, 0x01000000 + dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x050aff00, 0xff7cffff, 0x0, 0x02000000 + dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x2b00ffff, 0x020178fc, 0x0, 0x00000000 + dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x02ff8f00, 0x00c70300, 0x0, 0x01000000 + + writemsg "[9] Test cmpgdu.lt.qb" + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff0000ff, 0x3a0cffff, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x1b0c03f8, 0x178f2d0d, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x0a02ff7f, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000e, 0x18003cff, 0xff0b7e00, 0x0, 0x0e000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x03300018, 0x0200df06, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xdfdbe7ff, 0x00ffffbf, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0xfd026046, 0xff1e1a07, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x00ffff0d, 0x1dffe300, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x00009f00, 0xff002b06, 0x0, 0x09000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x0201007f, 0x8e007f10, 0x0, 0x0a000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x3666c1aa, 0xff060000, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000d, 0x00001a02, 0xffff006d, 0x0, 0x0d000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xb6df10e3, 0xb6df10e3, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000e, 0x0e1e027c, 0xef492d00, 0x0, 0x0e000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x03ff031c, 0x00010001, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x03ffff6c, 0x1604df00, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xf8fc02fd, 0x00240030, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000007, 0x0f000300, 0x00030f18, 0x0, 0x07000000 + dspck_dstio cmpgdu.lt.qb, 0x00000001, 0xf1ffff06, 0x9200f114, 0x0, 0x01000000 + dspck_dstio cmpgdu.lt.qb, 0x00000007, 0xff310800, 0x005cff0c, 0x0, 0x07000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff0008ff, 0x0107c70b, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff71003e, 0xff71003e, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xffff0000, 0x1f00ffc3, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x0e0108ff, 0x00ff051c, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x6d01ffe1, 0x0bff017f, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x038e02ff, 0x038e02ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000e, 0x180c1dff, 0xf31ec1ff, 0x0, 0x0e000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xffff0209, 0x0000ff8f, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x01390035, 0x000eff01, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x00ff06ff, 0x30030cff, 0x0, 0x0a000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x022c496d, 0xff0bf3ff, 0x0, 0x0b000000 + dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x0d00e701, 0x061a0b2a, 0x0, 0x05000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x0000ff18, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x009f010e, 0x33070100, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000007, 0xf1ef0001, 0x03ff0105, 0x0, 0x07000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x2c0e138e, 0x00f70000, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x1e077e18, 0x0500010b, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x00ff0310, 0x3f0300ff, 0x0, 0x09000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x00ffff76, 0x001ff303, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000001, 0xff0aff0e, 0x030000ff, 0x0, 0x01000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x1e0002ff, 0x12cf3802, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x018000fd, 0x018000fd, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x0fffaa01, 0xf1383981, 0x0, 0x09000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xffef0003, 0x0700ff40, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff02c167, 0x04cfff01, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x79030300, 0x00e10106, 0x0, 0x05000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x000104ff, 0xffff0110, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000d, 0x0d0100cc, 0x0fff00df, 0x0, 0x0d000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x0004ff3d, 0x0466ff03, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x78002c07, 0x2400f9f3, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xff4000ff, 0x008100fe, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x81c1014b, 0x1038c0ff, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x020254ff, 0xffff0eff, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x0210ffcf, 0x00ff8019, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x7100ff80, 0x01db557c, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000007, 0x3b17095e, 0x00db41b6, 0x0, 0x07000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x40440500, 0x05016d00, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff0000ff, 0x010201fe, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x07000000, 0x00004000, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x00000000, 0x09f06699, 0x0, 0x0f000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x60090b04, 0xffff1011, 0x0, 0x0f000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x10cf00ff, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xf8040024, 0xf8040024, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xffc0e7e3, 0x7c000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x0721f104, 0x0501ff64, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x55100000, 0x000f1a03, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x20fff90f, 0x01aacc0a, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x2603aa00, 0x0718aa00, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xaa87f13c, 0x0003f003, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x02ff0d0e, 0x000c20c3, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xbf012492, 0xbf012492, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xffff02fe, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x030001f7, 0x00ff1d02, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xe326bfdf, 0x00f1010c, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x0300ff00, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xc3090081, 0x000392ff, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xc30200ff, 0xc30200ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x1e101603, 0x02f90103, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x16ffff8e, 0x307eff00, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x870100ff, 0x3f000e00, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x00000000, 0x001b00e3, 0x0, 0x05000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x1e01ff24, 0xc3ff0000, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000e, 0x00070040, 0x7f130227, 0x0, 0x0e000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x00004902, 0x01f90400, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x00000eff, 0x02002408, 0x0, 0x0a000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0xf0f800ff, 0x01080c70, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x01ff4700, 0x44003c00, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x06f93fff, 0xff6d00ff, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x0f030007, 0x00003449, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xf91d3c00, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x00036d02, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x03200078, 0x02780002, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x0206ff92, 0x0206ff92, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000e, 0x1f000000, 0x2ef83500, 0x0, 0x0e000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x30010b16, 0x00021800, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x66074600, 0xf06dff02, 0x0, 0x0f000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x6ef1ff60, 0x00707102, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff001b7c, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x20fe3200, 0x00497c8f, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000007, 0xff371000, 0x383cff04, 0x0, 0x07000000 + dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x8380f038, 0x00ff03ff, 0x0, 0x05000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x13000132, 0x13000132, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x0300c30f, 0x00b683fc, 0x0, 0x05000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x28007000, 0xdf8effff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000d, 0x00057e08, 0x07db011e, 0x0, 0x0d000000 + dspck_dstio cmpgdu.lt.qb, 0x00000005, 0xff030e02, 0xffc30caa, 0x0, 0x05000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x7e0000aa, 0x0000ff01, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x00ff00ff, 0xcf1b0001, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000001, 0xff8e000b, 0x060c00fc, 0x0, 0x01000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x590f00ff, 0xff0000e0, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x00004000, 0x7a003c00, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x020f01ff, 0x7c0aff01, 0x0, 0x0a000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x1d000040, 0x001fff00, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000d, 0x37000110, 0xaae1003e, 0x0, 0x0d000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000d, 0x001d00cc, 0xc7ff00ff, 0x0, 0x0d000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x0e1d12ff, 0x3c620100, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x87ff0080, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x3300df87, 0x00df8300, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x200431ff, 0xef240580, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff0002bf, 0xff027e33, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xf9db08ff, 0xcf030519, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x38001849, 0xff360000, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000007, 0xb6007300, 0x0007f709, 0x0, 0x07000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x01ff0000, 0xffaaf300, 0x0, 0x0a000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xffbfffb6, 0xffbfffb6, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x00ff01b6, 0x00ff01b6, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x0001e101, 0x01ff0000, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x013e3038, 0x02003300, 0x0, 0x0a000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x00ff01e1, 0x0100ff00, 0x0, 0x0a000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff240080, 0xff00006a, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xccffff0a, 0xccffff0a, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x3f0078ff, 0x0f171b10, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xff010740, 0xffff0004, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff7dffff, 0x00001c19, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x0307ff07, 0xff789f00, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x01e04900, 0x06023800, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xc7020066, 0x0c0034ff, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xfffc003c, 0x1f0010ff, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x80000107, 0xff240000, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x80f9343f, 0x80f9343f, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x006001fe, 0x0000027e, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x01ff0499, 0x36ff0200, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0xe1fd3070, 0x0100ff01, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x0fe3ccff, 0x1faacfaa, 0x0, 0x0a000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x6f03e31a, 0xffff0800, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x0703f9ff, 0x00e7ff30, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000001, 0x00ffff0f, 0x0000c0ff, 0x0, 0x01000000 + dspck_dstio cmpgdu.lt.qb, 0x00000001, 0x7cc7fe55, 0x070000ff, 0x0, 0x01000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0xcfff0302, 0xff013c09, 0x0, 0x0b000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x07000039, 0xff020002, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x330adbff, 0xff001501, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000e, 0x3c2800ff, 0xcc3b151e, 0x0, 0x0e000000 + dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x0380ff00, 0xbf000024, 0x0, 0x09000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x9f700001, 0xff075520, 0x0, 0x0b000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xffff78e0, 0x04000183, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x0100063f, 0xc3001e00, 0x0, 0x0a000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x00ff0502, 0xff08e1f8, 0x0, 0x0b000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x3e380300, 0x24030f03, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x7f1f0010, 0x01071800, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x00000007, 0x30000100, 0x01ffffff, 0x0, 0x07000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x00010201, 0x0d00ff83, 0x0, 0x0b000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xf901c783, 0x92030500, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xaa03f080, 0x0d000800, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0xff0037f3, 0xff00fe7f, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x00010c03, 0x01006500, 0x0, 0x0a000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xffff3800, 0xff00ff01, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x012b0460, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000007, 0x08000bf9, 0x010b16ff, 0x0, 0x07000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff0070ff, 0x00000071, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x077100ff, 0xff8100f9, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x2bff0000, 0x023f0401, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0xfffe0003, 0x15000100, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff1607ff, 0xff1607ff, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x100b0b03, 0x01ff6600, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x05007f01, 0x00ff04f0, 0x0, 0x05000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x008f0200, 0x190c3ef8, 0x0, 0x0b000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xff0060ff, 0x00ff0400, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xe008ff38, 0x00ffff00, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x0f000000, 0x03001578, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x5901f9ff, 0x00ff028e, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000d, 0x00000000, 0xffff00ff, 0x0, 0x0d000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x0001339f, 0x00f11e07, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff0038f0, 0x08000004, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x031006c0, 0xe0ff6dff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x8e00001c, 0x03010d02, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0xcfb63103, 0xf9ffff92, 0x0, 0x0f000000 + dspck_dstio cmpgdu.lt.qb, 0x00000001, 0xff99ef01, 0xc37b0713, 0x0, 0x01000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x00700e08, 0xffff3887, 0x0, 0x0f000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0xf80c0002, 0x0f009902, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff3c050e, 0x38ffff03, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000005, 0xff00b600, 0xff7c3299, 0x0, 0x05000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x0000002e, 0x080013ff, 0x0, 0x0b000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xff24dfff, 0xffff36ff, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x1b000c00, 0x1a83f900, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x02ffff1b, 0xffff010e, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x03fe0206, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x0000711d, 0x0000711d, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x01000f00, 0xffff4081, 0x0, 0x0f000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xff80fdff, 0x9fff0887, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x008efff8, 0xf981033f, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xff722fff, 0x0178008f, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x00000000, 0x07000000, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x00100626, 0x01e11830, 0x0, 0x0f000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x00e00708, 0x00007e00, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x00000000, 0x00003813, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x0333dbf9, 0x0333dbf9, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x00000000, 0x24830e06, 0x0, 0x0f000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x170106cf, 0x047fff1e, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xff0a0002, 0x3b00ff2c, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x3c83fff9, 0x02fcc1ff, 0x0, 0x05000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x71dbff30, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000001, 0xff13ff0d, 0x400400b6, 0x0, 0x01000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x01ff0200, 0xff00e72d, 0x0, 0x0b000000 + dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x01ff0155, 0x01000240, 0x0, 0x02000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x00cf0100, 0x24000408, 0x0, 0x0b000000 + dspck_dstio cmpgdu.lt.qb, 0x00000001, 0x00001800, 0x00000004, 0x0, 0x01000000 + dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x011effe3, 0x11001eff, 0x0, 0x09000000 + dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x00ff0a00, 0xff00007c, 0x0, 0x09000000 + dspck_dstio cmpgdu.lt.qb, 0x00000001, 0x338fff66, 0x0004f983, 0x0, 0x01000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff870010, 0x00f03800, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x70019200, 0x00006000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x00000001, 0xcf01ff36, 0x0001ffff, 0x0, 0x01000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x003e8700, 0x1800ffff, 0x0, 0x0b000000 + dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x220102ff, 0x012c0040, 0x0, 0x04000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x034402e7, 0x7100c303, 0x0, 0x0a000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x000f3017, 0x00015555, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x0700ff07, 0x03ffe1ff, 0x0, 0x05000000 + dspck_dstio cmpgdu.lt.qb, 0x00000009, 0xe1002678, 0xff0008ff, 0x0, 0x09000000 + dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x0106ffe3, 0x0d0007c3, 0x0, 0x08000000 + dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xffdb07aa, 0x0e03c7c0, 0x0, 0x03000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x2f01081e, 0xe0020100, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff33006d, 0x8f38ff20, 0x0, 0x06000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x00090010, 0x1a008004, 0x0, 0x0a000000 + dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x003a7f18, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x031affff, 0xffff03ff, 0x0, 0x0c000000 + dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x7805001f, 0x065600f3, 0x0, 0x05000000 + dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x0049ff99, 0xf80e00f8, 0x0, 0x09000000 + + writemsg "[10] Test cmpgdu.le.qb" + dspck_dstio cmpgdu.le.qb, 0x00000003, 0xe0870000, 0x3718fd30, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0xff001e7e, 0xef7cc338, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x000200aa, 0xc100ffff, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x0218ff01, 0xdfc13c00, 0x0, 0x0c000000 + dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0008f8ff, 0x003f00ff, 0x0, 0x0d000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x007e0828, 0x002c7f3c, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x29071000, 0x6d3c0102, 0x0, 0x0d000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0x8f1fffc0, 0x0000c301, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0xff780000, 0x00fff01e, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x0c1c00ff, 0xff339200, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x00005640, 0xff3e0d0b, 0x0, 0x0c000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00ffff02, 0x00ffff02, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0000cc38, 0xff0000ff, 0x0, 0x0d000000 + dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x7800b6ff, 0xffff9902, 0x0, 0x0c000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x200b01e0, 0xffff0700, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0x2003ff31, 0x18008f1e, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x0520c001, 0x3e01df06, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x19004600, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000004, 0xffff0cff, 0x8fff0501, 0x0, 0x04000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0xfffffd3e, 0x0023cc53, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x00000009, 0x4c7e6300, 0x601b0000, 0x0, 0x09000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0xfffe007f, 0x00000000, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0xff2017ef, 0x92000703, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0x2cc05a55, 0x17000306, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0xff011ae7, 0x0000ff01, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x00000009, 0x8302780e, 0xff010e7f, 0x0, 0x09000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0x08060007, 0x021755ff, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0x92040001, 0x00f1ff00, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0x7f800000, 0x07007ecf, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x380000ef, 0xffff10df, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x183e001f, 0x32060200, 0x0, 0x0a000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0x01cf0883, 0x0030006d, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0x3f3a1200, 0x0c000024, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x1400e000, 0xfe0c00aa, 0x0, 0x0d000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0xff0002ff, 0x00fc3ee1, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x8708c300, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0x64ff0308, 0x1eff34ff, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x00ff0002, 0xfff9df00, 0x0, 0x0a000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0x7c07300c, 0x0bffff55, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0x780e0f00, 0x0305ff00, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x0300c0ff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x100f003c, 0x100f003c, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000004, 0x3c00ff38, 0x10020806, 0x0, 0x04000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0x01ff9f1b, 0x00330401, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0x0b1c1c00, 0x030200ff, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x00000009, 0x000d0c80, 0x170102ff, 0x0, 0x09000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0xffff000e, 0x0505f86d, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x067f49aa, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x000100fc, 0x1f26024f, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x0000000d, 0xcf00ff00, 0xfffd00ff, 0x0, 0x0d000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x55033600, 0xff07f900, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0x007899ff, 0xfd003500, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x039900ff, 0x10f70400, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0x7c200007, 0x00830036, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x001eff05, 0x3affff00, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0xff3e0309, 0x0000f301, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0xf7000042, 0xdfff0692, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0x1c78ffff, 0x000029ff, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x00000005, 0x0100ffb6, 0x00000eff, 0x0, 0x05000000 + dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x000e0c83, 0x0706c004, 0x0, 0x0a000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x037e0100, 0x78f30e00, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x01007101, 0x03380715, 0x0, 0x0d000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0xc1ffff03, 0x0018008f, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0xf8ff0600, 0xffbf81ff, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0xfce0600e, 0xbf7e408e, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0xc0db5f3f, 0x0003ff3f, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0x81ffe718, 0x33c7006b, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0x35ff0006, 0x03010e10, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x1c07e0ff, 0x83ffe31f, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0x14518308, 0xff0c3f02, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0xff2e0000, 0x8e0224ff, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0xff2c00f9, 0x6aff0e7e, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0x04000370, 0x01ff800e, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0xefe10700, 0x3e024b99, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0x3c02e018, 0x0070f300, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x00000004, 0xff00c03a, 0x00050f01, 0x0, 0x04000000 + dspck_dstio cmpgdu.le.qb, 0x0000000c, 0xff00fff8, 0xff000309, 0x0, 0x0c000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0x0036ff01, 0x66055f00, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0xffff010e, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00ff0700, 0x02ffffff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xe0ff1400, 0xe0ff1400, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000005, 0x9f48870f, 0x00ff08ff, 0x0, 0x05000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x008e0137, 0x01014978, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0xff000003, 0x7f0f803f, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0xc30200ff, 0x00000000, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x03ff3001, 0xff008e9f, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0x83000d00, 0x550c2900, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x0000000a, 0xffff0473, 0xff06c324, 0x0, 0x0a000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0xb6f13eff, 0x01030805, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x380000f7, 0xe7ff0351, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0x380030b6, 0x050087ff, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0x02ccffff, 0xff130000, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0x0700023f, 0x00008762, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x00017e3f, 0x00ff0600, 0x0, 0x0c000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0xfccf01ff, 0x717187ff, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x00000009, 0x65ff0f00, 0xff080004, 0x0, 0x09000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0xf3808f17, 0x00000000, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0xb667ff07, 0x001ce7db, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x010f6dff, 0x010f6dff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xff000000, 0xff000000, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000005, 0x2302ff00, 0x011100e0, 0x0, 0x05000000 + dspck_dstio cmpgdu.le.qb, 0x00000005, 0x06000100, 0x0000008e, 0x0, 0x05000000 + dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x01ff03ff, 0x05119238, 0x0, 0x0a000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x00ff0000, 0x178700ff, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x00000009, 0x00df8110, 0x000d0078, 0x0, 0x09000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x60c3c305, 0x60c3c305, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x0022f940, 0x8703ff00, 0x0, 0x0a000000 + dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0230f324, 0x1881f17c, 0x0, 0x0d000000 + dspck_dstio cmpgdu.le.qb, 0x00000005, 0x20002c00, 0x008300ff, 0x0, 0x05000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0xcc4900ff, 0x086d1e00, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0x83ff001f, 0x3800021e, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xffff0000, 0xffff1100, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x01200216, 0x01200216, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0x1e241e92, 0x000005ff, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x0000e306, 0x3333fff3, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0xfe0307ff, 0xff000003, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x00ff04ff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x07030e00, 0xc724ff00, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0001170f, 0x7e2a0099, 0x0, 0x0d000000 + dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0000ff33, 0x023f81aa, 0x0, 0x0d000000 + dspck_dstio cmpgdu.le.qb, 0x00000005, 0x0800ff00, 0x04cc8eff, 0x0, 0x05000000 + dspck_dstio cmpgdu.le.qb, 0x00000005, 0xf1067800, 0x00f13d07, 0x0, 0x05000000 + dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0300ff00, 0xffaa6d40, 0x0, 0x0d000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0xf9000628, 0x051c0803, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x046c9f00, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x8f1c17ef, 0xb6ffff19, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0x0660df18, 0x0002ff00, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000202, 0xf0ff1602, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xff043e00, 0xff043e00, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0x04010110, 0x000000ff, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x00000009, 0x28aab600, 0xff02001b, 0x0, 0x09000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x38380501, 0xff0171ff, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0xff200ce1, 0x0010ff71, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0xff1b012d, 0x1e04ffe0, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x00000009, 0x1010240c, 0xff001f18, 0x0, 0x09000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0x4cffff15, 0x060049ff, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0xffff2639, 0x0000fef1, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x05000087, 0x0a1e00c3, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000009, 0x00f1201e, 0x08f000ff, 0x0, 0x09000000 + dspck_dstio cmpgdu.le.qb, 0x00000004, 0xe000ff0b, 0x0087db00, 0x0, 0x04000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xf9000002, 0xf9000002, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0xf8ffff00, 0x923f2df7, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x01ff1700, 0x0140ff00, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x92007edf, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0xffff0000, 0x008eef00, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x00000009, 0x012c1f00, 0x34180000, 0x0, 0x09000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0xf312ff06, 0x2300cfff, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0xff6e007f, 0x00000000, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x07000000, 0xff00021b, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x03032401, 0x03032401, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00240006, 0x30ff1cff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x7f0034ff, 0xff05ff03, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0x920d6e78, 0xfd000b60, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x009f0102, 0x3efe08ff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x0000b6ff, 0x00fc3403, 0x0, 0x0c000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x7b180000, 0x87efc303, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000004, 0xff00031c, 0x01180000, 0x0, 0x04000000 + dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x008f001c, 0x660b6c00, 0x0, 0x0a000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0x1f9900ff, 0x00010507, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x000300ff, 0x000e0300, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0x02479266, 0x18000007, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0x1537c3e1, 0x000c0100, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0x7e060200, 0x171b0b00, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0xff00026d, 0xeff935ff, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x0000013e, 0x180316ff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x0600660e, 0xff000001, 0x0, 0x0c000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x009200f3, 0x000300ff, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0xff000018, 0x2a0104c1, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x000000ef, 0xdf00001f, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x03020000, 0x4320fd00, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0x03bf3c02, 0x05aa0000, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0x03f8fff0, 0xff99c06d, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0xfcff0cff, 0x000300fc, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x00000004, 0x0d00f3ff, 0x02db1e08, 0x0, 0x04000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0x7803ffe7, 0x00000038, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x00000004, 0xff00ff0c, 0x00ff0a00, 0x0, 0x04000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0x1f710000, 0x0fff0000, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x02110049, 0x0e000083, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x0000000c, 0xfe7d0214, 0xffff0000, 0x0, 0x0c000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x01240000, 0x0fff0105, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000009, 0x080c1c03, 0xe009017e, 0x0, 0x09000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0xfcff03ff, 0x02000001, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x19ff01ff, 0xe700213c, 0x0, 0x0a000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0xe7000000, 0x00cc0c00, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x78ffefc0, 0x78ffefc0, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x043e3300, 0x1e07f97f, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00010101, 0x03ff0281, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0xf8000237, 0x003f5bff, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0x017c0100, 0x000003ff, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0xff713e00, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0x3c0006ff, 0x00007e00, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0x33000000, 0x008f02ff, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0x04e700ff, 0x02cff100, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00070000, 0x013601aa, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x00c03bff, 0x03ffff00, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x2300ff07, 0xcf780100, 0x0, 0x0c000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0xc17104ff, 0x34fde034, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x7f070000, 0x7f0f0100, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0x0e000003, 0x00ff0601, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0xffffffff, 0x710000ff, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0x00ffffff, 0x8000004f, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0xf71c9918, 0x0014aa00, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x0000007e, 0x00ff004b, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0x0a360303, 0x0000e7ff, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x00000004, 0x7effe13c, 0x03ff0700, 0x0, 0x04000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0x7efcff1c, 0x9201040d, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x00000009, 0xffff1800, 0xff0c0117, 0x0, 0x09000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x83446d02, 0x83446d02, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x137e0101, 0x99ff7e9f, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0xff000d02, 0xcf020f00, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x01600107, 0xffff4f04, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x318e00ff, 0xffffff2e, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xff000000, 0xff0666cf, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0x9f242470, 0xff00000f, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x00000c0b, 0xff0ef102, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x3f872c0d, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000007, 0x0f1913ff, 0x001e7cff, 0x0, 0x07000000 + dspck_dstio cmpgdu.le.qb, 0x00000001, 0xff8f7e66, 0x2c0626ff, 0x0, 0x01000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0x07ffaa07, 0x03040001, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0f008300, 0xdf290ef7, 0x0, 0x0d000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0x0aff1701, 0x00fffc00, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0xff007cff, 0x03ffff80, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0xf90003ff, 0xff7ffe13, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x02fd0100, 0xdb03aa01, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xff000003, 0xff7effff, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x1602001c, 0x99220302, 0x0, 0x0e000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0xf3ff0000, 0x006000ff, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0xff8f001c, 0x092f0100, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x00000008, 0x00e7077e, 0x0020002f, 0x0, 0x08000000 + dspck_dstio cmpgdu.le.qb, 0x00000002, 0xaa0100ff, 0x0800ff06, 0x0, 0x02000000 + dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xff000001, 0xff18f906, 0x0, 0x0f000000 + dspck_dstio cmpgdu.le.qb, 0x00000009, 0x00ffff05, 0x00718107, 0x0, 0x09000000 + dspck_dstio cmpgdu.le.qb, 0x00000003, 0x71193401, 0x6000ffdb, 0x0, 0x03000000 + dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x008e0111, 0x0000992b, 0x0, 0x0b000000 + dspck_dstio cmpgdu.le.qb, 0x00000000, 0x71ff5508, 0x0d060003, 0x0, 0x00000000 + dspck_dstio cmpgdu.le.qb, 0x00000005, 0x81ff3600, 0x5bff03ff, 0x0, 0x05000000 + dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x078700ff, 0xff0383cf, 0x0, 0x0a000000 + dspck_dstio cmpgdu.le.qb, 0x0000000c, 0xff00ff04, 0xffff8101, 0x0, 0x0c000000 + dspck_dstio cmpgdu.le.qb, 0x00000006, 0xff00008f, 0x19ff3a00, 0x0, 0x06000000 + dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x00c00020, 0x0fe00000, 0x0, 0x0e000000 + + writemsg "[11] Test dpa.w.ph" + dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xfea8b6db, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xf0017fff, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x0005b1d8, 0x6e41ec9a, 0x0005b1d8, 0x81590494, 0x80007ffa, 0xd5d3fc01, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x0327f3a3, 0x96512bf6, 0x0327f3a3, 0x5682ab94, 0x00628000, 0x7fff7fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xc71b8002, 0xfffe71c7, 0x7fff8000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xfffec14f, 0x38e18814, 0xfffec14f, 0x638c8814, 0x0000aaaa, 0x80058000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x3ffc0006, 0x00007ff9, 0xfff67fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0xffffffff, 0xffffffe0, 0x00000000, 0x3ffc7fe7, 0x8000fff9, 0x80007fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0e3536, 0x001f0000, 0xf8f90007, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x2aab0000, 0x0000aaaa, 0x09558000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x003b4563, 0x02d52d0c, 0x003b4563, 0x03832a54, 0x015c0000, 0x7ffe8000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xfffffffe, 0xffffffff, 0xc0037ffe, 0xffc07ff9, 0x00008000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x0000ffff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x7fffffff, 0xffffff80, 0x7fffffff, 0x8002ff7c, 0x80007fff, 0x7fff8004, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000001, 0x7fffffff, 0xf1c770f2, 0x1c710f0f, 0x8000ffff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0xc71bf1c8, 0xffff3fc0, 0x7fff0000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0xfffef965, 0x04b726aa, 0xfffef965, 0x44ae23d7, 0x800fff00, 0x80030003, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x00000000, 0x02857fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000002, 0x00000000, 0x00048ec7, 0xffb70002, 0xf003ffd0, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xc0020000, 0x7fff7ffc, 0x00008000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x0ff061e0, 0x80000002, 0xe01ff0f0, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xfff5c2de, 0xffffffff, 0xe7f502dd, 0x7ffff003, 0xc0018000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xc0597f4e, 0x7fff7fff, 0x800600ac, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff69fff2, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0xe0000000, 0x00000003, 0xdfffffff, 0xfffd0083, 0xffff8000, 0x7f800005, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xffffffff, 0x00000000, 0x01b6077b, 0xf8848000, 0xfffffc94, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xf873d01e, 0x7ffffc01, 0xf0f00110, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0xc0000000, 0x00000007, 0xc0000000, 0x00000007, 0x3ec40000, 0x00007fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x2622e9f3, 0x17799bff, 0x2622e9f2, 0xecfa45f0, 0xfe5d807f, 0xff7e5555, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x000aedee, 0x0002fc01, 0x0055fd44, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000004, 0x80000000, 0x00bef99e, 0xe007f14d, 0x0000f302, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x741b9c5f, 0x00000000, 0xb41a9c60, 0x7fff7fff, 0x7fff0000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffff8001, 0x7fff0000, 0xffff8000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0xffffffff, 0xfffeaa5a, 0xffffffff, 0xfffebef1, 0x00000003, 0x000506dd, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000035, 0xffffffff, 0xfe814613, 0x8002e00f, 0x02fefffe, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xe013ffe0, 0x7fff3ff8, 0x00208000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000007, 0xffffffff, 0xffff8009, 0x00000001, 0xc01f8002, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0xdb6db6db, 0x6db6db6d, 0xdb6db6db, 0x2db75b6d, 0x80000000, 0x7fffff80, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0xffffffff, 0xfffffff8, 0xffffffff, 0xcce10557, 0x6666f007, 0x803f0053, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x013720ed, 0x00000000, 0x413620ee, 0x00007fff, 0xe0077fff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0xffffa810, 0x9221fb51, 0xffffa810, 0x677750a7, 0x00007fff, 0x03ecaaaa, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000003, 0xffffffff, 0xfffffdbd, 0x000000c2, 0x8000fffd, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xff4cd7de, 0xffffffff, 0xff4cb0c4, 0x00000596, 0x7ffdfff9, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0x7ffffffc, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0xf8000000, 0x00000001, 0xf8000000, 0x0325b84d, 0xf9b5fffa, 0x8000f69e, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x66666666, 0x66666666, 0x66666666, 0x66666666, 0x00000000, 0x1ffe800f, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fff2401, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000002, 0x00000000, 0x00018002, 0x80000000, 0xfffdffff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x0000003f, 0x00000000, 0x0001003d, 0x00007fff, 0x19090002, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x0000003c, 0x81f26808, 0x0000003c, 0xc1e2e808, 0x00008000, 0x1c6e801f, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaa47e2, 0xf9580007, 0xfffff0f0, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xfd35146e, 0xffffffff, 0xfd35146e, 0x00008000, 0x7fff0000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0xfff110c9, 0x419edfd7, 0xfff110c9, 0x3a3bee9d, 0x00007fff, 0xfff7f13a, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x00076db4, 0xbdf3e757, 0x00076db4, 0xc151e09b, 0x7fff7fff, 0x07acff10, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x06e3f0e2, 0x3fc0e38e, 0xff20c007, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x00197fca, 0x7fff8000, 0x00350002, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x0000063c, 0xffffffff, 0xf878154c, 0xf801f0f0, 0x00007fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x1fffffff, 0xfffffffc, 0x1fffffff, 0xffff7d40, 0x0002ffeb, 0x0003063a, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfffeb9ae, 0xffa40001, 0x038cfffe, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000165, 0xffffffff, 0xdb6d74b1, 0x8000000a, 0x4924f1ee, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000004, 0x80000000, 0x00000004, 0xfffefff6, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0xf8000000, 0x00000001, 0xf8000000, 0x003cc37b, 0x0000807f, 0x8000ff86, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000004, 0x00000000, 0x03fdfa30, 0x7fff0008, 0x07fc0045, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0xaaaaf1c7, 0x80007ffc, 0x38e30000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xafcb206b, 0xc5fc7fff, 0x7fff9999, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffff4b80, 0xffed0006, 0xff66e003, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0xffffe808, 0xd9a80061, 0xffffe808, 0x99a88061, 0x7fff0000, 0x80000b22, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x07ffffff, 0xfffffffc, 0x07ffffff, 0xfffffffc, 0x00000000, 0xfffa0f9e, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x00347c63, 0xc0077fff, 0xff82002a, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x56606095, 0x00000000, 0x36812046, 0xfff07fff, 0xf001c03f, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x003cf1c6, 0x00018000, 0x71c7ff87, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x3fffffff, 0xfffffff8, 0x40000000, 0x3fb06f1b, 0xfc978000, 0x17558000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0xffffe8a9, 0x744ad39c, 0xffffe8a9, 0x74192138, 0xf0550000, 0x032ce007, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xfffeb769, 0x00000000, 0x002ab769, 0x8000ffa8, 0x00008000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0xffffffff, 0xfb19fa7e, 0x00000000, 0x3b15fa85, 0x7fff7fff, 0x7ffffffa, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0xffffffff, 0xfffffcd4, 0x00000000, 0x000f4b54, 0x8000e163, 0x0000ff80, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x02d5b67b, 0x00000000, 0x3569507f, 0x8e380132, 0x8e380132, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffff8fc5, 0x7fff07e2, 0xffff0002, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x000000fc, 0x00000000, 0x1f400ba0, 0x7ffffb32, 0x3fe02492, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000004, 0xffffffff, 0xff8ddae8, 0x0772fff9, 0xf0f04924, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000006, 0x00000000, 0x3ffa802c, 0x7fff7ffb, 0x00027ff8, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0xffff476a, 0xccd415fe, 0xffff476a, 0xb052960e, 0x8000ffd8, 0x38e36666, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x7fff0010, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x0fffffff, 0xfffffffe, 0x0fffffff, 0xffff9cbe, 0x0000ffc0, 0x5555018d, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x0000ffff, 0x0000ffff, 0x0000fffe, 0xfffd03ef, 0xc03f0000, 0x00107fff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xdb6fb668, 0x00078006, 0xfff04924, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x00000007, 0x00000000, 0x0035128a, 0x8000ed7d, 0xff96ffff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x0000e9ce, 0x507e3769, 0x0000e9ce, 0x340c704d, 0x00007fff, 0x257ac71c, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0xc71c71c7, 0xfffdffff, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x0000fff3, 0xfffe01d3, 0x80060000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000611, 0x0ecd277d, 0x00000610, 0xdd4598c5, 0x71c77fff, 0x80000eb8, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffffe978, 0x0780fffc, 0xfffd0002, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0xfffc06ca, 0x9100de16, 0xfffc06ca, 0x91009566, 0xffffb6db, 0xff8b0001, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x06729d6e, 0x2f7fe3e8, 0x06729d6e, 0x2f803306, 0x0ff8001f, 0x0005fffa, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x0000000f, 0x00000000, 0x00030003, 0x00008002, 0xcbb4fffa, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xe0057ad6, 0x7ff0fffe, 0xc003027d, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000ff8, 0x1b440000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00327ee6, 0xa703c34a, 0x00327ee6, 0xa6e88491, 0x0000c003, 0x0000006d, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x0008f375, 0x3ff0120b, 0x0000007f, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x00800000, 0x0000ff00, 0x1ffc8000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0xffffffe3, 0xe65d492d, 0xffffffe3, 0xcd70897d, 0x7ffb71c7, 0x3ff08000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0xfff08000, 0x00008000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000002, 0x80000000, 0x1248db70, 0x00002492, 0x80007fff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0xfffd6e60, 0x3316951d, 0xfffd6e5f, 0xf318951a, 0xf9d98003, 0x00007fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x7fffffff, 0xfffffffc, 0x7fffffff, 0xffe1404a, 0xffc4e003, 0x7fff0006, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000006, 0x00000000, 0x00000006, 0x800ffffa, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000007, 0x7fffffff, 0xffffee07, 0xff000001, 0x00120000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x02001147, 0xffffffff, 0xc220904e, 0x8000001f, 0x7fc00419, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0xffffffff, 0xffffffc7, 0x00000000, 0x000eb887, 0xc71c3fe0, 0xffc00002, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xfc01f95e, 0xfffe1ffc, 0x3333e00f, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x7fffffff, 0xfffffffc, 0x7fffffff, 0xe007fffc, 0x80000000, 0x3ff0ff2a, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000001, 0x1f1b24b5, 0x00000001, 0x1f1a8022, 0x0001db6d, 0x80000001, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xffffff8d, 0x00000000, 0x003fff0e, 0xffff007f, 0x80007fff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffe8002, 0xfffd8000, 0x7fff0000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0xf8000000, 0x00000001, 0xf8000000, 0x00000001, 0xf3a4ff26, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xffff8000, 0x00018000, 0x80000000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfff8000f, 0xfffe7fff, 0x0000fff0, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xffd105f4, 0x0000fb1c, 0x7fff099b, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xfffffff0, 0x80000000, 0x000042ad, 0x000000ff, 0xf8010043, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x40003f01, 0x007f8000, 0x007f8000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xfffffffb, 0x7fffffff, 0xfffffffb, 0x00000000, 0x0ffc7fff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xc00fffe1, 0x0000801f, 0xff7d7fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xffffb6da, 0xccccdb6d, 0x00000002, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x80008000, 0x80000000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xfa667d3a, 0x7ffaf655, 0xeb218000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xfffffff0, 0x00000000, 0x03c3a1d2, 0x00003ffe, 0x80000f0f, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffe8, 0x38706230, 0xffffffe8, 0x38706230, 0x00000000, 0x0000f9c2, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x000000e3, 0x9d3c57e4, 0x000000e3, 0x9dda56a8, 0x00007fff, 0x17c7013c, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x000000ff, 0xffffffff, 0xfffec914, 0x00120003, 0xf001f801, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0xf66afd8a, 0xf6925efe, 0xf66afd8a, 0xf6935f02, 0x0002ff00, 0x0002ff00, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xffffff80, 0xffffffff, 0xfff8ab72, 0x002bfffc, 0xd2e2f001, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x0000003f, 0x7fffffff, 0xffc000bf, 0x00007fff, 0x0000ff80, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xffffffff, 0x00000000, 0x402d0000, 0x7fff8000, 0x7fffffa4, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000d70, 0xffffffff, 0xfff68d70, 0x06548000, 0x00000013, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0xfffffff8, 0xc5d3660c, 0xfffffff8, 0xc5d32d23, 0x38e3fffd, 0xffff0002, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfc19edf3, 0x003c0ff8, 0x5555c03f, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xfffffff8, 0xffffffff, 0xfe9500f6, 0x80028000, 0x007f0257, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0xffff0000, 0xffff0000, 0xffff0000, 0xc000c012, 0xe0018000, 0x00127ff8, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00778b21, 0x00000000, 0x00778b21, 0x0037ffc3, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x0031c77c, 0x00000000, 0x005c477c, 0x00008000, 0x0001ffab, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xbffd8000, 0x80000006, 0x7fff8000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xffffffbe, 0xfffe0006, 0x0000fff5, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x7fffffff, 0xfffffffa, 0x7fffffff, 0xfc827fb8, 0xfc01c821, 0x00000ffe, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfd5b467a, 0x7fff2d18, 0x0005f0f0, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000e01f, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x0fffffff, 0xfffffffe, 0x10000000, 0x0ab3301e, 0x38e30f0f, 0x0e457fff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000003, 0x80000000, 0x00000003, 0x000003fe, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xffffffeb, 0xffffffff, 0xffffffeb, 0xf0078000, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x009b60e1, 0x00140c77, 0x00140c77, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0xfffffffd, 0x7aed58f9, 0xfffffffd, 0x88bfbd54, 0x1ba50000, 0x7ffffffe, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x0000000a, 0xc9d0d535, 0x0000000a, 0xd158d535, 0x00008000, 0x0000f0f0, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xe0000000, 0x00000003, 0xdfffffff, 0xfffd0003, 0xf0010006, 0x00008000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0xf0000000, 0x00000003, 0xefffffff, 0xc0075d1e, 0xff458000, 0x00df7ff0, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0xe38e38e3, 0x8e38e38e, 0xe38e38e3, 0x8e3cdf96, 0xfffafffe, 0x807f807f, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0xe0000000, 0x00000003, 0xdfffffff, 0xc0005a83, 0x8000ffc0, 0x7fff0096, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xc0007ec0, 0x8000fff8, 0x7fff0028, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0xfffffffc, 0xa1321610, 0xfffffffc, 0xa13a9487, 0x0009ff80, 0x7ffff803, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000b0c, 0xdf2900d5, 0x00000b0d, 0x1f280c3a, 0xfffa7fff, 0xfe1a7fff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf68b7b4f, 0x00001546, 0x80028e38, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x1bab38e8, 0x01897ff8, 0x800038e3, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xff916db6, 0xffffffff, 0xff9f2e07, 0xfff9001f, 0x3ff07fff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0xfffffffd, 0x1bb2d7a6, 0xfffffffc, 0xfdfa1318, 0xc71c7fff, 0x7ffffd72, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x000004d5, 0xafe0f76c, 0x000004d5, 0xafe1776b, 0x7fff0000, 0x0001ffff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0xfe090217, 0xbea0acbe, 0xfe090217, 0xbe01216e, 0x80007ff8, 0x02a9016a, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000003, 0x7fffffff, 0xfc8cdbb2, 0x803f0f0f, 0x0035c71c, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x1006a030, 0x1ff08000, 0x7ffdffe2, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x49249249, 0x24924924, 0x49249249, 0x41044924, 0x00008000, 0xff80c71c, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xc0000000, 0x00000007, 0xbfffffff, 0xff9b00d1, 0xf95005e6, 0x7fff7fff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x0002b5a3, 0xffffffff, 0xfffd35a3, 0x000bfffe, 0x80000000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0xfe5c9ac4, 0x23718f95, 0xfe5c9ac4, 0x43614fb5, 0x80007fff, 0x00003fe0, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0xb6db6db6, 0xdb6db6db, 0xb6db6db6, 0xdb6db6db, 0x07fc0006, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xffffffc0, 0xffffffff, 0xfffffddd, 0x0063000c, 0xffffffe0, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x0000a7cc, 0xffffffff, 0xe2e9bf23, 0x3a310000, 0x8007ffd2, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0xffffffff, 0xfffffff9, 0x00000000, 0x0000005e, 0xfff6ffff, 0xfff6ffff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0000800f, 0x00070000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x000000ff, 0xffffffff, 0xfff7837c, 0x0003ffec, 0x7fff7fe0, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00007fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x03fe3739, 0x00000000, 0x03fe3739, 0x00000000, 0x8000fff8, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0xfffffff8, 0xae7abf0a, 0xfffffff8, 0xaeca3e6b, 0x0000009f, 0x00007fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0xfffffcbe, 0xdc7790df, 0xfffffcbe, 0xebc796d1, 0x23bb0000, 0x6db6000b, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xdb6db6db, 0x6db6db6d, 0xdb6db6db, 0x74d2e9a5, 0xc0038e38, 0x0000f001, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x003ff001, 0xfffff801, 0xfffff801, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000001, 0x7fffffff, 0xff9a1a00, 0x66660001, 0xff007fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x00207fbe, 0x7ffffffc, 0x00410000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x00efff27, 0xf0f00002, 0xf020f094, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xfffffee6, 0x00000000, 0x3ffffee6, 0x80000000, 0x80007ffc, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000006, 0xffffffff, 0xffdf8047, 0x7fff8000, 0xffbf0000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x07ffffff, 0xfffffffc, 0x07ffffff, 0xf22c8a44, 0xff371c71, 0x80058005, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x000000a8, 0x9e0579ec, 0x000000a8, 0x94aa7e8c, 0x8000b6db, 0x007f1fe0, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x64ef51b8, 0x00000000, 0x64e751c8, 0x0000fff0, 0x7fff7fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x40006dc5, 0xfece7fff, 0xfece7fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0xf0000000, 0x00000003, 0xf0000000, 0x30059ff7, 0x7ffd7fff, 0x7fffe00f, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000001, 0x00000000, 0x040d865d, 0x800f0000, 0xf7e48000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0xc0000000, 0x00000001, 0xc0000000, 0x00000001, 0x00006db6, 0xfffe0000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xc62f7393, 0x7fff800f, 0x0c4e7ffe, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x00c48b94, 0x7666df7e, 0x00c48b94, 0x7649dfb8, 0x00007fff, 0xffc1ffc6, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0xffffffff, 0xfffbe8e0, 0x00000000, 0x18aaea4e, 0x7ff938e3, 0x03dc6666, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0xffff92e3, 0x3fa343fb, 0xffff92e3, 0x877827bc, 0xe01f8000, 0xc01f803f, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x07109f0c, 0xc00f7fff, 0x0000f003, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xe67fd9c0, 0x38e39999, 0x00003fc0, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0xffffffff, 0xffffff89, 0x00000000, 0x22a6597a, 0x7fff803f, 0x7f803a4f, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0xffffffff, 0xfffd5bb6, 0xffffffff, 0xfd56c572, 0xed937fff, 0x24d40000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x349b6162, 0x00000000, 0x349b5ed4, 0x0000006d, 0x803ffffa, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xfff1ea15, 0x85bc6da8, 0xfff1ea15, 0x85bc6daa, 0x0001c01f, 0x00020000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xfef18cd1, 0x7fff055a, 0xfde30002, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0eef430a, 0xff800bfb, 0x8000f801, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x001ef9b3, 0x000707fe, 0x003503e0, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x05da3d3b, 0x00000000, 0x09fac5da, 0x099c068f, 0x6db60059, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffc0, 0x80000000, 0x1ff681bc, 0xc00f0004, 0x8000807f, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x0000007f, 0x80000000, 0x00022188, 0xffcb000f, 0x00112492, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x00000758, 0x6666fffc, 0x0000fe2a, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f1, 0x29d3ff29, 0x7fff0000, 0x71c70000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xfffffffa, 0x00000000, 0x1b52c21f, 0x0002c03f, 0x01179249, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000f0f, 0x716bbd7a, 0x00000f0f, 0x6d6c4579, 0xc03ff801, 0x00007fff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0xfe678323, 0x8000fcd5, 0x00067fff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0xffffffff, 0xfe7b529d, 0xffffffff, 0xfe7a7ccd, 0xfff50ffc, 0x11fcffff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000004, 0x00000000, 0x00008004, 0x80001c71, 0xffff0000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xfffffefb, 0x9999fefb, 0x00000001, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xfffffffb, 0x7fffffff, 0xfe207fbc, 0x03fe7fff, 0x8000003f, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x0000400a, 0x00010006, 0x3ff80003, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x0000003f, 0xffffffff, 0xfc713b43, 0x9999f87c, 0xff807fff, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000e4c, 0xf60a9f91, 0x00000e4d, 0x6eee9f91, 0x8e388000, 0x80008000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0xc0000000, 0x00000001, 0xc0000000, 0x3fe08041, 0xfffe7fff, 0x80007fc0, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0xfefccbd4, 0x00017fff, 0xccccfff8, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffff75f, 0x0001ffe9, 0xf6bffff9, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x30c1fe84, 0x71c7fffb, 0x6db61ffe, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0xfd9e612d, 0x27f639e9, 0xfd9e612d, 0x681b685a, 0x80000619, 0x80000619, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000004, 0x80000000, 0x00000004, 0x7fe0fe15, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xffffffff, 0x00000000, 0x000017b4, 0x000f05f1, 0xffff0004, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x71c71c71, 0xc71c71c7, 0x71c71c72, 0x070cefdb, 0x0052801f, 0xfffa8000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80003333, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x0049ffd8, 0xff6cffff, 0x80000028, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x001fc0e8, 0x00000000, 0x0017e2a1, 0xe0070000, 0x003f8000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x012bfff0, 0xb6db801f, 0xff05fe37, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0xffcf2742, 0xf03b2b2a, 0xffcf2742, 0xf03b2b2a, 0x0004fffe, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffec23, 0x46cbc035, 0xffffec23, 0x46cb4035, 0x00008000, 0x80000001, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x1fffffff, 0xfffffff8, 0x1fffffff, 0xfe6afff8, 0x032a0f0f, 0x80000000, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000034, 0x00000000, 0x0001381d, 0xf8030002, 0xfff97fff, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000005, 0x7fffffff, 0xffb1efe1, 0xffec0218, 0x803fd5f3, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xff8cfada, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0xffff0000, 0xffff0000, 0xffff0001, 0x00949c5a, 0x8000ec5a, 0x000ff801, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x00d6ffff, 0x000a8000, 0x8000fe48, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00005fa3, 0xe01f7fff, 0xfffd0000, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000007, 0xc4ab6b32, 0x00000007, 0xc49beb32, 0x3fc08000, 0x0000001f, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xfffffff8, 0x00000000, 0x0001cdc2, 0x6666fff8, 0x00071fe0, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x00000002, 0xffffffff, 0xff970002, 0x00d20000, 0x8000fffe, 0x00010000, 0x00010000 + dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xff910bc3, 0x0000f90f, 0x7fff0ffc, 0x00000000, 0x00000000 + dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xf2080040, 0x1bec7ff0, 0x8000fffc, 0x00000000, 0x00000000 + + writemsg "[12] Test dps.w.ph" + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000006, 0x00000000, 0x031d1f69, 0x24920059, 0xea34fffd, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xffd46ab9, 0xffffffff, 0xe7e05a7a, 0xe00ff001, 0x8000803f, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffc605c, 0x0000054d, 0x077200af, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffeef54, 0x02500035, 0x0076ffff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000011, 0xd9821737, 0x00000011, 0xd9821ce5, 0xffff0024, 0xffeaffd7, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfff5a297, 0xfc010000, 0xfd68fffd, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xdffe8000, 0xc0018000, 0x8000fffc, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfffc8007, 0x7fff0000, 0x00070000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xf62487d3, 0x0ff8801f, 0x1ffef043, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xfefffffc, 0x0ffeff80, 0x0ffeff80, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0xffb4d691, 0x925251d6, 0xffb4d691, 0x125851bc, 0x7ffb7fff, 0x7ffb7fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0xffffffff, 0xfffa95a7, 0x00000000, 0x0007559f, 0x3ffc7fff, 0x80063fe0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x3fff8000, 0x80008000, 0x00007fff, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x0000d78e, 0xffffffff, 0xc0005796, 0x00037fff, 0x7ffd7fff, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xfeb5447c, 0xf98cfffb, 0xccccf003, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xffffff61, 0x00000000, 0x03591d89, 0xe8480000, 0x24238000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x0001ffeb, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0xffff0000, 0xffff0000, 0xffff0001, 0x020e6b68, 0xfabdf001, 0x6666ff4a, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x5874e925, 0x00000000, 0x5870e925, 0xf8038000, 0x0000fff8, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x0002dd5b, 0xffffffff, 0xfff80bd9, 0xfffefc9e, 0x08f7fcc8, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0xffffb42d, 0xf197cd6f, 0xffffb42d, 0xf1982d0f, 0x1fe0ffff, 0xfffe1fe0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xfffffffe, 0xffffffff, 0xffff800d, 0xfff07fff, 0xf001ffff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x92492492, 0x49249249, 0x92492492, 0x49249249, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x00001d14, 0x83abf203, 0x00001d14, 0x9d391ce9, 0xffe9c01f, 0x00c06666, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xc3fef807, 0x8007f809, 0x80007fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xfedc7fdb, 0xffdb8000, 0x7ffffd94, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffffffb, 0xffffffff, 0xfffffe07, 0xfff8fffd, 0xffedff8c, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x0000fae6, 0x07d70002, 0xffe0fffd, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0xc0000000, 0x0000001f, 0xbfffffff, 0xc007801f, 0x80000000, 0x800f0000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x1242ffff, 0xfff48000, 0x80002492, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0xfffff85b, 0x0e81b11b, 0xfffff85b, 0x4e7abf64, 0x7fff001d, 0x800038e3, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x800fc001, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xffffe536, 0x55eaa9bd, 0xffffe536, 0x574b935b, 0x1b478000, 0xe38efcb2, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffffec3, 0x00000000, 0x40102c07, 0x7fff3fc0, 0x8004ffb5, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x1fefffff, 0x80008000, 0x00003fe0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xff9e18fc, 0x7fc0ff2c, 0x005ac003, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xf80c0fe8, 0x7fff0ff8, 0xfff07fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x0000007f, 0x00000000, 0x004c5144, 0xff590099, 0xffd4801f, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x0fffffff, 0xfffffffc, 0x10000000, 0x01ff7bb5, 0x00187fff, 0x0003fc01, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0xe0000000, 0x00000003, 0xe0000000, 0x00000003, 0x3ff8ff84, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xfffffff9, 0x00000000, 0x0001c713, 0x00027fff, 0x1c71fffc, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x0177ccbc, 0xcbfb5c14, 0x0177ccbc, 0x8bfb5c14, 0x80000000, 0x80000000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xfdd9de19, 0x48ff2817, 0xfdd9de19, 0x48ffba61, 0xb6db0000, 0x00023fe0, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x1def42f5, 0x00000000, 0x5dc67abc, 0x02e8807f, 0xf8037fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0xffffffff, 0xffed319b, 0xffffffff, 0x7fee319a, 0x80007fff, 0x80007fff, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xffff8e7d, 0x45453af3, 0xffff8e7d, 0x354dd35b, 0xfff87fff, 0x0f0f1ff0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0003edfe, 0xdb6d8000, 0x0065ffe9, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xffff568a, 0xffffffff, 0xffff568a, 0x00000000, 0x8000ff6b, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x0002e38e, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xffdd0046, 0x00468000, 0x7fff0000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x24924924, 0x92492492, 0x24924924, 0x92491b5e, 0x09340000, 0x0001ffe4, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xffffff80, 0x00000000, 0x001f7ee1, 0x0006003f, 0xfd85803f, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x0005a068, 0x000fe007, 0x8000fff1, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xfffffff9, 0x7fffffff, 0xbf504bb8, 0x801f7f80, 0x801f019f, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xbaec1244, 0x7ffff491, 0x7fff8e38, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xfffffffd, 0x00000000, 0x0026dc42, 0x7fffdb6d, 0x00060125, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xc0000000, 0x00008000, 0x00008000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xffff6db8, 0x000236e3, 0x49240000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xe38efff7, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xee497f93, 0xffffffff, 0xefc014a3, 0xc003fb49, 0xff915555, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xfffc0000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000024, 0xffffffff, 0xf0037ff3, 0x0000c007, 0x0000c007, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00001455, 0xf149a2cb, 0x00001455, 0xb15122cb, 0x8000005b, 0x800f0000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x0011fe1d, 0x0024ffff, 0x800f003a, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfc0ee2b9, 0x0ffef803, 0x3ff801bd, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x0002e003, 0x00061ffc, 0x80000001, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffffff0, 0xffffffff, 0xfffffff0, 0x0040e774, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0xfffff967, 0x9b888bb0, 0xfffff967, 0x7d9789b0, 0x80003ff0, 0x03fe7fe0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xfe7627ab, 0xffffffff, 0xbe29a78b, 0xff467fe0, 0x80007fff, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000006, 0xffffffff, 0xbffb800f, 0x80000009, 0x80007fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x1fde46df, 0xfffd807f, 0x01a13ffc, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x3fffffff, 0xfffffff0, 0x3fffffff, 0xfffffff0, 0x00000000, 0x00003ffe, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x01e66d68, 0x80008005, 0x001503b8, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000007, 0x80000000, 0x3fff8007, 0x00007fff, 0x71c78000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000034, 0x00000000, 0x0003fffc, 0x7ff9fffe, 0xfff80000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x0000007f, 0x00000000, 0x000266a7, 0xffc0fffd, 0x0999fff8, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000009, 0xffffffff, 0xfffc7c5f, 0x003f7fff, 0x000f0007, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0xfffffe55, 0x7b4d9ef3, 0xfffffe55, 0x7b3778fe, 0x00ca0003, 0x1d05c001, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0xb348e486, 0x00000000, 0xb349a429, 0x00030000, 0xc01fe7de, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x0009f1bc, 0x4768935b, 0x0009f1bc, 0x59bbd016, 0x04117fff, 0xfd92db6d, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0xf8000000, 0x00000001, 0xf7ffffff, 0xffb2f4ce, 0x0181ffc0, 0x3333ffd2, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0xf8008007, 0x0003f001, 0xfffb8000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0xc0000000, 0x0000000f, 0xc0000000, 0x0000604d, 0xff460002, 0x007ffe04, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00030001, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x38e38e38, 0xe38e38e3, 0x38e38e38, 0xe18c3ce1, 0x7ffffffa, 0x03fe8000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xf84cad82, 0x198c7566, 0xf84cad82, 0x2569485b, 0xee79e001, 0x38e33fc0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000005, 0xffffffff, 0xc03ec8a1, 0xdb6d7fff, 0xfff47f80, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfe067001, 0xfc0df003, 0x8000ffff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x7fff0000, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x00038e1c, 0xdaf28bc2, 0x00038e1c, 0xfaf14bc4, 0x7fff7fff, 0xc003ffff, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x0000006f, 0x00000000, 0x1974006f, 0x80000000, 0x32e83fe0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000302, 0x00000000, 0x1f96026e, 0xaaaa8000, 0xff223fc0, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xe3f868fb, 0x1ff8c71c, 0xfd1c803f, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00d4e530, 0xfffd7ff0, 0x8000fe53, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0xffffff8e, 0xe33f475b, 0xffffff8e, 0xe33f475b, 0xfdb2e007, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x0000007f, 0xffffffff, 0xffd23219, 0x00a0000e, 0x492401b5, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xfff29624, 0x3f07165b, 0xfff29624, 0x3f59bda8, 0x00f5ce18, 0xc03f006f, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xe38e8000, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xe0000000, 0x00000003, 0xe0000000, 0x4034fd16, 0x8000006b, 0x7fff8007, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x0000001c, 0x61d58d9d, 0x0000001c, 0x69d48d9d, 0x8000c01f, 0x0ffe0000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xe221254c, 0x39a33aaf, 0xe221254c, 0x00c02bc7, 0xfff97fff, 0xffe771c7, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000005, 0x7fffffff, 0xfc03ff05, 0x00001ff0, 0x00001ff0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x24924924, 0x92492492, 0x24924924, 0x91b5a5e8, 0x024efffe, 0x3ffefe5d, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xfffffffd, 0x00000000, 0xff803fc0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x0398379a, 0x00000000, 0x4397b86c, 0x000f7fff, 0xfff28000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0xffff0000, 0xffff0000, 0xffff0001, 0x303158c1, 0x71c70ff8, 0x92490910, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0xffffed68, 0x8d8942da, 0xffffed68, 0x8d8aac1a, 0xffc00000, 0x05a50000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xf62cae7c, 0x00000000, 0x364aaa7f, 0x7ff07fff, 0xffc08003, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xfffffff0, 0xffffffff, 0xfd8dfff0, 0xfb158000, 0x80000007, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xfffffff5, 0x5e8df3c0, 0xfffffff5, 0x5e8df3c0, 0x7ff001e6, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x00ff00ff, 0x00ff00ff, 0x00ff00fe, 0xc10080fd, 0x00007fff, 0x7fff7ffe, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x0fffffff, 0xfffffffc, 0x0fffffff, 0xc9247fed, 0xfffb9249, 0xfffd8000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x0357b2bf, 0x0a07ffcd, 0xaaaa0007, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x3fff8000, 0x7fff0000, 0x80008007, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x0000003f, 0x00000000, 0x000d473e, 0x800038e3, 0x0003ffcb, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x03ceffff, 0x80008000, 0xfff907a5, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffff80, 0x7fffffff, 0xffffffa8, 0xfff80000, 0x0005e003, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffe9fc01, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xffffffff, 0xffffffff, 0xf9e87fff, 0xffc2f40f, 0x80008000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffdb, 0xe2a6bef0, 0xffffffdc, 0x1be2734c, 0xfa768e38, 0x0fea7fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff80005, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffff80, 0x80000000, 0x00007f7f, 0x80007fff, 0x7fff7fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xfffffda8, 0x00000000, 0x0004294a, 0x00040052, 0xfffef2fb, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xffffe010, 0xffe00001, 0x00001ff0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0x5170d173, 0xffffffff, 0x509943d5, 0x8000fe0e, 0xfe51fff9, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x0fffffff, 0xfffffff8, 0x10000000, 0x10f77036, 0xd8690007, 0x6db60004, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0xc0000000, 0x00000001, 0xc0000000, 0x00000001, 0x00000000, 0x8000003f, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xffffff80, 0x80000000, 0x00007efd, 0x807f0001, 0x00010004, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0xff12c914, 0x4706b369, 0xff12c914, 0x71b03367, 0x7ffd8000, 0xaaaaffff, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x0000ffff, 0x0000ffff, 0x0000fffe, 0xfed1ce7f, 0x00ff019a, 0x7ffc6db6, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0xfffffc15, 0x279f88fc, 0xfffffc14, 0xd7af08fc, 0x80008000, 0x8000e01f, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x0000000f, 0x6ea838f3, 0x0000000f, 0x4e0a48e4, 0x7ff907fc, 0x39477fc0, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x3ffc8000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00006950, 0x00000000, 0x00008750, 0x000f003c, 0x0000ff80, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0xffed0000, 0x0000fffd, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x3fffffff, 0xffffffe0, 0x3fffffff, 0xffffffe0, 0xfffd7fff, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xfffa17ca, 0xffffffff, 0xffbb9847, 0x00007fff, 0xb6db007d, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x0001113d, 0x8e3b5ea2, 0x0001113d, 0x73031513, 0x00003671, 0x11317fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x0363d379, 0x00000000, 0x0302d379, 0x80000000, 0xff3effff, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xffffff4c, 0xfffa7fff, 0xffe20000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xcb29ffff, 0x7fff8000, 0x7fff1652, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x0517ffff, 0x00000a30, 0x7fff8000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x0000003f, 0xffffffff, 0xffea3c92, 0xd1cbff41, 0xfffde38e, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x0022cfdc, 0xc92af564, 0x0022cfdc, 0xc93dd308, 0x0ffe0000, 0xfed28005, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffcc86a7, 0x7ff0fff9, 0x006e7ff8, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x8000e007, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00038000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00000006, 0xffffffff, 0xfff650a1, 0x0000ff65, 0xe007f001, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xeffad4a8, 0x8000039c, 0xe01f05ba, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xe0000000, 0x00000007, 0xe0000000, 0x0011ff48, 0x7fff001f, 0xffdc0005, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfff8fc05, 0xffffffff, 0xf50e7c05, 0x8000f432, 0xf5f98000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x3fff8000, 0x8000c001, 0x7fff0000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffff47f7, 0x038a1c71, 0x00340000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000004, 0xffffffff, 0xfafb0509, 0x5555b6db, 0x0f0f0000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x000000ff, 0xffffffff, 0xfce5bd96, 0xe00f7fff, 0x072907fe, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0xffffe980, 0xe7bdf8a9, 0xffffe980, 0xe7b95573, 0xfffed57b, 0x01abffe4, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00000003, 0xffffffff, 0xc048d5cb, 0xc71c8000, 0x0102801f, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xffffd806, 0x7a69a0e1, 0xffffd806, 0x93b24539, 0x8e3803fe, 0x38e30000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x1fffffff, 0xfffffff8, 0x1fffffff, 0xfff88007, 0x7fff0000, 0x000f8000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x3ff80004, 0xffff8000, 0x00057ff0, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000004, 0x00000000, 0x00270004, 0x004efffa, 0x80000000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x7fff0000, 0x7fff7fff, 0x80008000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x0000038e, 0xffffffff, 0xe4927401, 0xfffe9249, 0xe15ec001, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x000002a3, 0xfffeffd3, 0x0000000f, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x3fffffff, 0xfffffffe, 0x3fffffff, 0xff133892, 0x7fff801f, 0x0007fe2d, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffff80, 0x80000000, 0x0ffbff80, 0x80008000, 0x1ff80000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xc0802392, 0xfc7f8000, 0x24928000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1bd048c9, 0x01ad8000, 0x7fff006a, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x0005b6e2, 0x00010ea1, 0x0002ff9c, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x0000007f, 0x80000000, 0x01604a6a, 0x0f0f8006, 0xe89b0000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffdac984, 0x0000fe0f, 0x001fecd5, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0xfe8f757d, 0xbc23c059, 0xfe8f757d, 0xbc99405d, 0x00ef7fff, 0x80000004, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0xc0000000, 0x00000003, 0xc0000000, 0x00000003, 0x00000000, 0xffff803f, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0xfffff842, 0x21f53073, 0xfffff842, 0x21f53043, 0x0008ffd8, 0x00060000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xcf3d0f96, 0xffffffff, 0xcec97333, 0xe001fffd, 0xfc630000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x0000002f, 0x6519b10d, 0x0000002f, 0x617c5534, 0x073b0000, 0x7ffb08a9, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xe38e03fe, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x03ffffff, 0xfffffffe, 0x04000000, 0x0ff7810e, 0xfff97ffd, 0xe945e00f, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x0007fff0, 0x7fff0000, 0xfff00ffe, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x2492b6da, 0x7fffb6db, 0xffff7fff, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00088eaa, 0x00000000, 0x016c39e1, 0xfff10590, 0xffe9c00f, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xffc379d5, 0xffffffff, 0xfac623b0, 0x7fffffff, 0x09fb1fe0, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0xfffffb14, 0xe7dadbeb, 0xfffffb14, 0xe7d5943a, 0x00068003, 0xf6a3fff5, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x00007fff, 0xfffffff9, 0x7fff0000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x3fffffff, 0xffffffe0, 0x40000000, 0x0002ffe0, 0x8000fff2, 0x00060000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0xc0000000, 0x0000000f, 0xbfffffff, 0xc0010c0b, 0x00037fff, 0xfc017fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x000079c9, 0xa8334575, 0x000079c9, 0xa83346e9, 0x0006fffd, 0xffc20000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x000c811b, 0x0911974d, 0x000c811b, 0x0911976b, 0xffee0006, 0x0000fffb, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xfffffffc, 0x7fffffff, 0xfffffffc, 0x00038007, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xfffffff6, 0xf53bffff, 0x0000fff6, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xffffff00, 0x00000000, 0x0001bef2, 0xe0010000, 0x000e0ffe, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x3fffffff, 0xfffffff0, 0x3fffffff, 0xffffc80c, 0xeed00007, 0x000007fc, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf0041ff7, 0x7fffc001, 0x1ff80000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xfffc19dd, 0xffffffff, 0xd0f6c108, 0xfffe9249, 0xfffe9249, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x0034c062, 0x9999da9a, 0xfff8017f, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x01d0ebf0, 0x00000000, 0x01ba6ca4, 0x8000002d, 0x00007ffc, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xd639d38d, 0x138f3ffe, 0x7fff7fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0xf0000000, 0x00000003, 0xf0000000, 0x00000003, 0x7f808001, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0xb470ac84, 0x00007ffb, 0xfca72559, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffd559, 0x80001c71, 0x00010006, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0xf8000000, 0x00000003, 0xf7ffffff, 0xfffd6dbf, 0x00000009, 0x80004924, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xfe026710, 0xffffffff, 0xfe026710, 0x00000000, 0x001f07fc, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0xffffffff, 0xfffffffd, 0x00000000, 0x0006968d, 0xff220f0f, 0x0000ff90, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0xffff83a9, 0x59b3a217, 0xffff83a9, 0x59b3a217, 0x00010000, 0x00008000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0xf0000000, 0x00000007, 0xf0000000, 0x000013dd, 0x7ffff615, 0x00000002, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x00000007, 0x09568d12, 0x00000007, 0x3c8a0c93, 0x00016666, 0x807f8000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x000003d4, 0xebe18f2f, 0x000003d4, 0xebdd0fc9, 0x00000125, 0x800003ee, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x0000003f, 0x80000000, 0x31c71cb0, 0x80001c71, 0x7fff7fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0xfffa4621, 0xbeeb1105, 0xfffa4621, 0xbeeb0f90, 0x0007ffee, 0x0007ffee, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x3fffffff, 0xffffffe0, 0x3fffffff, 0xc0017edf, 0x007f7fff, 0xff007fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x002c2f59, 0x00000000, 0x002b3b45, 0xfffcffff, 0xc2fb0000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xfffffc92, 0x522e8973, 0xfffffc92, 0x521e9b71, 0x0ffeffc0, 0x00ff0000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x1b037b3e, 0x00000000, 0x1b037b3e, 0x00000000, 0x7fff7fff, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffffff0, 0xffffffff, 0xfffc10a4, 0x003f0006, 0x0ffefff7, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x000014dc, 0x582af822, 0x000014dc, 0x5815f837, 0xffe65555, 0x0000003f, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfdf2fbe5, 0xfffff9d9, 0x0000aaaa, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf8007fff, 0x0000f001, 0xc0038000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x0be5e487, 0x6003ca86, 0x0be5e487, 0x6003ca86, 0x00000000, 0xaaaafffe, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xffffc1bc, 0xfffb0000, 0xf38c8000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfebd83bf, 0x050f0000, 0x3fc0004c, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xfff101be, 0x7fffc007, 0xfffeffc0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x000006ff, 0xe1cf2bdc, 0x000006ff, 0xe1cf64c7, 0x0007e38e, 0xffff0002, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xffce0ff8, 0xfffe8000, 0x07fcff9c, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xfffd9364, 0xffffffff, 0xfffd7e9a, 0x0000f912, 0x8000fffd, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0xffffffff, 0xffdab1fd, 0xffffffff, 0xdffb11a5, 0x00047fff, 0xf8063fc0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xe0000000, 0x00000007, 0xdfffffff, 0xf3d2e6a5, 0xfff0aaaa, 0x3ff0db6d, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x000000ff, 0x00000000, 0x01bc7e46, 0x80010004, 0x0379ffd0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xf0000000, 0x00000007, 0xf0000000, 0x07fe732b, 0x0321f003, 0xffff7fff, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x8e38e38e, 0x38e38e38, 0x8e38e38e, 0x38eb0dfc, 0x80040000, 0x000fff62, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0xe0000000, 0x0000000f, 0xe0000000, 0x099b4cdb, 0x7fff8000, 0xcccce003, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0x1fffffff, 0xfffffff8, 0x1fffffff, 0xfffffff8, 0x0040ffff, 0x00000000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac0, 0xffffffff, 0xfffbba3f, 0x00000000, 0x0238a350, 0x0531c9ec, 0xffff0a98, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xe38e9999, 0xc71ccccc, 0x80000003, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x0000003f, 0xffffffff, 0xc004002c, 0xfffd7ff9, 0xfffc7fff, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffff197, 0xffffffff, 0xffd5f1eb, 0x00540000, 0x7fffe38e, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fff9999, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac1, 0xfffff32e, 0x7a61c863, 0xfffff32e, 0x7a61c863, 0x8000fff8, 0x00000000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac0, 0x55555555, 0x55555555, 0x55555555, 0x94e35557, 0x8002ff1f, 0x7fff8000, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfc003ffe, 0x0000e001, 0x0000e001, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000006, 0x80000000, 0x0603e106, 0x66660005, 0xf0f07fe0, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x000044ed, 0x000f0005, 0x001ff1da, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x800007fc, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xc000ffff, 0x7fff0000, 0x7fff8000, 0x00010000, 0x00010000 + dspckacc_astio dps.w.ph, $ac3, 0x00003469, 0x77af6dfb, 0x00003469, 0x491f8dd3, 0x80001ff8, 0xc2d77ffb, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0xffff2669, 0x49620ddd, 0xffff2669, 0x62fbdaa9, 0xc03fcccc, 0x00007fff, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x01283b98, 0x00000ff8, 0xfff3ed73, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x000de46e, 0x00000000, 0x000e5072, 0x0000001f, 0xfffcfc84, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x80000000, 0x00000005, 0x7fffffff, 0xf00b1997, 0xe007ffda, 0x80003333, 0x00000000, 0x00000000 + dspckacc_astio dps.w.ph, $ac1, 0x0fffffff, 0xfffffffe, 0x10000000, 0x004d6101, 0xf6d10000, 0x086d0014, 0x00010000, 0x00010000 + + writemsg "[13] Test madd" + dspck_astio madd, 0x000007ea, 0x1c572c4f, 0xffb0dd02, 0x1884e628, 0x0d3bfa1b, 0xfa049b1b, 0x0, 0x0 + dspck_astio madd, 0xe0000000, 0x00000001, 0xe0000000, 0x00000001, 0x00000000, 0x011bc658, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xffff323b, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x8000113a, 0xb14ea013, 0x00114bec, 0x00ff00ff, 0x0, 0x0 + dspck_astio madd, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1c71c71c, 0xffffff80, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000033, 0xff8cd5d2, 0x55c87fb6, 0xfea68177, 0x55555555, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffa807, 0x8000aff0, 0xffff500f, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x81c38c39, 0x64a2da2d, 0x33333333, 0x08d1bd1f, 0x0, 0x0 + dspck_astio madd, 0x55555555, 0x55555555, 0x5555558e, 0x65554e33, 0xfffff8de, 0xf8000001, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xffff6498, 0xffffffff, 0xffff6498, 0x00000000, 0x3ffffff0, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffe, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x6db6db6d, 0xb6db6db6, 0x6db6db6d, 0xb6db6db6, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0xffffffff, 0xfffffe1f, 0x0000000d, 0xffffffdb, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x7fffffae, 0x580ad64b, 0xfffffc9f, 0x182a9ad5, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0xfffffff5, 0x800000a8, 0x7ffffff8, 0xffffffeb, 0x0, 0x0 + dspck_astio madd, 0xe38e38e3, 0x8e38e38e, 0xe38e38e3, 0x8e38e38e, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xffdc7f4b, 0x15144627, 0xfaa30721, 0x4e8c6ff3, 0xdb6db6db, 0x24924924, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x0000003b, 0x00000000, 0x0000003b, 0x00000000, 0x1ffffffe, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xfffffffa, 0x40000000, 0x7ffffffa, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7c066337, 0x7fffffff, 0x80000000, 0x07f33991, 0x0, 0x0 + dspck_astio madd, 0x6db6db6d, 0xb6db6db6, 0x6db6db6a, 0xb6db6db6, 0x00000006, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x60000007, 0xbffffff1, 0x7fffffff, 0xc000000f, 0x0, 0x0 + dspck_astio madd, 0x1c71c71c, 0x71c71c71, 0x1c71c74a, 0x71c71c15, 0x7fffffff, 0x0000005c, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffff9, 0x00000000, 0x000675b9, 0xffffb140, 0xffffffeb, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0xc0000000, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x07ffffff, 0xfffffffe, 0x071ac183, 0x81ca7cf7, 0xfe358307, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x000017d3, 0x9e7cda6b, 0x000017d3, 0x9e760aca, 0xffffffff, 0x0006cfa1, 0x0, 0x0 + dspck_astio madd, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0x00000006, 0xfffffffe, 0x7ffffff9, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x7f1072c1, 0x1df1a7e0, 0xfe20e582, 0x7ffffff0, 0x0, 0x0 + dspck_astio madd, 0xfc000000, 0x00000001, 0xfc000000, 0x0002c99f, 0x000032f9, 0x0000000e, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffffc, 0x00000320, 0xfffff9ba, 0x00000642, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x0000007f, 0x33333333, 0x8000007f, 0x99999999, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffff80, 0x8000003f, 0xfffffc00, 0xffffff80, 0x80000007, 0x0, 0x0 + dspck_astio madd, 0x06508b03, 0xae37a5e3, 0x06508b03, 0xae37a529, 0x0000001f, 0xfffffffa, 0x0, 0x0 + dspck_astio madd, 0x00125566, 0xabd5de14, 0x00f907a0, 0x65656278, 0xfcd89036, 0xb6db6db6, 0x0, 0x0 + dspck_astio madd, 0xf8000000, 0x00000001, 0xf6000000, 0x97fffffb, 0x7ffffffa, 0xfc000001, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fa40281, 0x044fe1f3, 0x016ff5fc, 0xc0000003, 0x0, 0x0 + dspck_astio madd, 0x66666666, 0x66666666, 0x5e666667, 0x66666666, 0x80000000, 0x0ffffffe, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80000016, 0x7fffe980, 0x7fffff80, 0x0000002d, 0x0, 0x0 + dspck_astio madd, 0x38e38e38, 0xe38e38e3, 0x38e38e38, 0xe38e38e3, 0x00ff00ff, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x99999999, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xfffffb7b, 0x75082318, 0x0002e5d8, 0x74fc79a4, 0x24924924, 0x0014688b, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7ffd7ffd, 0x009b00b9, 0x8000001f, 0x00050006, 0x0, 0x0 + dspck_astio madd, 0xe072cc5d, 0xb8b90a85, 0xe072cc5d, 0xb8b9ba03, 0xffffa841, 0xfffffffe, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x000000d7, 0x3fc4c79c, 0xfffb83d7, 0xffd001c4, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x0000003a, 0xffffbc43, 0x8000003a, 0x00008779, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x92492492, 0x49249249, 0xd2492492, 0x49249249, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000007, 0x00000000, 0x00000007, 0x00000000, 0x1c71c71c, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xffffe6ab, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x0000004f, 0xaaaaaa5b, 0x000000ef, 0x55555555, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x33053ce3, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x92492492, 0x49249249, 0x92492482, 0xa36ac2e2, 0x000d1d3d, 0xfffece8d, 0x0, 0x0 + dspck_astio madd, 0xe0000000, 0x00000003, 0xdfffffff, 0xfffe0005, 0x0000ffff, 0xfffffffe, 0x0, 0x0 + dspck_astio madd, 0x1c71c71c, 0x71c71c71, 0xdc71c71f, 0x71c71c6c, 0x7fffffff, 0x80000005, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfe46c589, 0x1ffffff7, 0x3e46c5b9, 0x3ffffff0, 0x7ffffffd, 0x0, 0x0 + dspck_astio madd, 0x07ffffff, 0xfffffffe, 0x07fffb9d, 0x800008c3, 0x80000001, 0x000008c5, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x0001e522, 0xfffffec4, 0x8001e799, 0x7fffffff, 0xfffffd89, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x70000000, 0xffffffff, 0x1ffffffe, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0xcccccccc, 0xcccccccc, 0xcccd8069, 0xedb78d54, 0xff81eaa8, 0xfe934fcd, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffffc, 0xf0000000, 0xfffffffc, 0x1ffffffe, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x6d097b42, 0x684bda12, 0x55555555, 0xc71c71c7, 0x0, 0x0 + dspck_astio madd, 0x1fffffff, 0xfffffffe, 0x1fffffff, 0xfffffffe, 0x00000000, 0xfffff8a8, 0x0, 0x0 + dspck_astio madd, 0x00000003, 0xbb182077, 0x00000003, 0x9b18207b, 0xfffffffe, 0x0ffffffe, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0xf0000001, 0x00000000, 0x1ffffffe, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0xfffff0b5, 0xb030a647, 0xfffff0bd, 0x77696d78, 0x00ff00ff, 0x000007cf, 0x0, 0x0 + dspck_astio madd, 0x000b43e4, 0xbf1579a0, 0x000b43e4, 0xbf1579a0, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xf7e01642, 0xc0000007, 0xf7e01633, 0x8000000f, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000004, 0x00000000, 0x00000004, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00000377, 0xfffffe44, 0x49249249, 0x00000c24, 0x0, 0x0 + dspck_astio madd, 0x00000510, 0xd61702cf, 0x40000510, 0xd61702cf, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xff0f4741, 0xffffffff, 0xff0f4741, 0xc0000007, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x55555555, 0x55555555, 0x555555ab, 0xe2bc4ce3, 0xffff5393, 0xff7f7efa, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xc0000003, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x0000000f, 0xfffffc40, 0xc000000f, 0xffffffc0, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x55555555, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0xbfffffdf, 0x8000003f, 0x7fffffff, 0x7fffffc0, 0x0, 0x0 + dspck_astio madd, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xfffffff0, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x3ffffff8, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00d979c9, 0x0000000e, 0x80d97972, 0xffffffe3, 0x80000003, 0x0, 0x0 + dspck_astio madd, 0x66666666, 0x66666666, 0x66666666, 0x25c416af, 0xfffd7135, 0x00001945, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000de7, 0x00000000, 0x00000de7, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffe0, 0x40000000, 0x7fffffe0, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00b2f56e, 0x74d0a918, 0x0165eadd, 0x7ffffff8, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffffe, 0xff86e7b4, 0xfffffffe, 0x80000000, 0x00f23096, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffcc, 0x00000067, 0x7fffffff, 0xffffff98, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xe000000f, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xffffffc0, 0x00000000, 0x000264d6, 0xfffffff6, 0xffffc2b1, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000006, 0x80000000, 0x7fffff87, 0x8000007f, 0xffffffff, 0x0, 0x0 + dspck_astio madd, 0xe0000000, 0x00000003, 0xe0000000, 0x00000003, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfff9dd70, 0x000013e3, 0x6db097b8, 0x00002e68, 0x6db6db6d, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffc337e0, 0x0, 0x0 + dspck_astio madd, 0xffffff8a, 0xb1dbee92, 0x14e5e031, 0xcbfb4763, 0x49249249, 0x49249249, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80189cfa, 0x00000000, 0x80000000, 0xffcec60c, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x0000001f, 0xfffff1d0, 0x9001c60d, 0x0001c5ee, 0xf8000001, 0x0, 0x0 + dspck_astio madd, 0x3fffffff, 0xfffffff8, 0x31c71c72, 0x51c71c69, 0x71c71c71, 0xe0000001, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xf0000001, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x66666666, 0x66666666, 0x6665175d, 0xa7037280, 0xe000000f, 0x000a7846, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffff80, 0x40000000, 0x7fffff80, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0xffed92d5, 0x26c0d3b4, 0xffed92d7, 0x26c0d3a4, 0xfffffffc, 0x80000004, 0x0, 0x0 + dspck_astio madd, 0xb6db6db6, 0xdb6db6db, 0xb5fd1671, 0x56ce710c, 0xf8000003, 0x1bcae8bb, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7ffd67f5, 0x20914260, 0x0014c057, 0xe0000007, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xfffffff0, 0x80000000, 0x00000ef4, 0xffffffc2, 0xffffffc2, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xffffd836, 0xffffffff, 0xffffd836, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffffb, 0xffffffff, 0xfffffffb, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000b35, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x10495344, 0x00004092, 0x00004092, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x0dea8be3, 0xf64221a7, 0x485dc1f9, 0x80000003, 0x137bbcb2, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x0003b4f0, 0xfffc4b10, 0xffffffff, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xfffffffb, 0x7fffffff, 0xfffffffb, 0x7ffffff0, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7ffffff9, 0x9999999f, 0x66666666, 0xfffffff0, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffe35, 0xffffffff, 0xfffffe35, 0x0000000f, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x40000002, 0xfffffffa, 0x80000005, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x20131c81, 0xf0000007, 0xc0131c72, 0x7fffffff, 0xe000000f, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x7fffffc0, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xfffffffe, 0xb91de955, 0xfda564af, 0xd55d3109, 0x04b5369e, 0x80000006, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0000007, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x0000000f, 0x00000000, 0x0000000f, 0x80000006, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x83c3c3c3, 0x9696968f, 0xc0000007, 0xf0f0f0f0, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000002, 0x80000000, 0x00000002, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0xfffba51e, 0xa536ddaa, 0xfffba51e, 0xa536ddaa, 0x00000000, 0x0001fe81, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x7122641e, 0xe0000009, 0xf12263a6, 0x7ffffff8, 0xc000000f, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffffc0, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x0000000f, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffd2, 0x800001c6, 0xffffffa5, 0x7ffffffb, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x7fee5e4e, 0x15fdf021, 0xf85292d9, 0x024bea89, 0x0, 0x0 + dspck_astio madd, 0x000413bb, 0xafb8c6ab, 0xfc0413bd, 0x2fb8c68b, 0xf8000001, 0x7fffffe0, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xffffffe0, 0xffa48a28, 0x48038e52, 0xf0000007, 0x05b75d7e, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x03fffffe, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00082bdd, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x80000000, 0x7fffffff, 0xffffffff, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x000495dd, 0xff33514e, 0xaa48e92f, 0x01cc890f, 0x8e38e38e, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x027ea0a2, 0x40000000, 0x027ea0a2, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x80000002, 0x7ffffffa, 0x00000005, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0xbfffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x000346f7, 0xfffffffb, 0xffff5835, 0x0, 0x0 + dspck_astio madd, 0x0001d19f, 0x20a5fa03, 0x0001bb81, 0xa0a5fa03, 0x80000000, 0x00002c3b, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00075530, 0x3fffffff, 0x00075531, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0xffff1b9a, 0xdbaf3253, 0x0786a322, 0xdbaf3253, 0x80000000, 0xf0f0f0f0, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000007, 0x3fffff80, 0x00004007, 0x7fffff80, 0x7fffff80, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xff594f8c, 0xffffffff, 0xff595772, 0x00000006, 0x00000151, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7e000000, 0x83fffffe, 0x7fffffff, 0xfc000001, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000001, 0x00000000, 0x003aeaea, 0x000007ad, 0x000007ad, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffffb, 0xfd3751a3, 0x05915cb5, 0x7fffffff, 0xfa6ea346, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffede, 0xffffffda, 0x7ffffede, 0x0000004b, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0xfffffffd, 0xf69575c2, 0xfffffffe, 0x674ff42a, 0x00000007, 0x101aa458, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x0014939f, 0x00000000, 0x0014939f, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xfffffffd, 0x9e51cf8b, 0xffffffff, 0x9e51cf87, 0x00000004, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0xc0000000, 0x00000003, 0xc0000000, 0x00000003, 0x00000000, 0xffffd631, 0x0, 0x0 + dspck_astio madd, 0xf0000000, 0x00000001, 0xe8000000, 0x90000000, 0xf0000001, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000003, 0x80000000, 0x00000003, 0x00000000, 0x3fffffe0, 0x0, 0x0 + dspck_astio madd, 0x0003252e, 0xb69f700c, 0xffcf1701, 0x369f700c, 0x80000000, 0x00681c5b, 0x0, 0x0 + dspck_astio madd, 0xfc000000, 0x00000001, 0xfc000000, 0x03a4590f, 0x00001086, 0x0000386d, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfff9d117, 0xfffff3d2, 0xfff9d117, 0x80000000, 0x0000185a, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x000c90be, 0x03fffffe, 0x800c90be, 0xf8000003, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1c71c71c, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x1fffffff, 0xfffffffe, 0x2ffffff7, 0xe0000049, 0x80000005, 0xe000000f, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xffffff7a, 0x00000000, 0x0147c9ba, 0xffeb835c, 0xfffffff0, 0x0, 0x0 + dspck_astio madd, 0x07ffffff, 0xfffffffc, 0xc8000000, 0x7ffffffc, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xfffffffc, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x00000022, 0xfb3ca75c, 0x00000022, 0xfb3ca76c, 0xfffffffc, 0xfffffffc, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xfee5d86b, 0x0, 0x0 + dspck_astio madd, 0xdb6db6db, 0x6db6db6d, 0xdb6db6dd, 0x6db6db69, 0x7fffffff, 0x00000004, 0x0, 0x0 + dspck_astio madd, 0x0000d2c7, 0x86b4a129, 0x0400d2c5, 0x96b4a13e, 0xc0000003, 0xf0000007, 0x0, 0x0 + dspck_astio madd, 0x0c51f874, 0xb4db6b7a, 0x0c51f874, 0xb4db6b7a, 0x00000000, 0xffffffe7, 0x0, 0x0 + dspck_astio madd, 0xffff0000, 0xffff0000, 0xffff0000, 0xffff0000, 0x07fffffc, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x3fffffe0, 0x0, 0x0 + dspck_astio madd, 0x8e38e38e, 0x38e38e38, 0x8e38e38e, 0x38e38e38, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xffffffe0, 0xffffffff, 0xff45a550, 0x00000008, 0xffe8b4ae, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xffffffea, 0xf73d2fb4, 0xffffffea, 0xf73d1bcc, 0xffffffc8, 0x0000005b, 0x0, 0x0 + dspck_astio madd, 0xffffffeb, 0x762f3464, 0xffffffec, 0xf62f3464, 0xfffffffd, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x0000ffff, 0x0000ffff, 0xe001000f, 0x0000ffff, 0x3fffffe0, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0xff00ff00, 0xff00ff00, 0xff026364, 0xff00ff00, 0x80000000, 0xfffd3738, 0x0, 0x0 + dspck_astio madd, 0xffffffce, 0xc7ddbb22, 0xffffffce, 0xc7ddbb46, 0x00000003, 0x0000000c, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x000006ca, 0x00000000, 0x000006ca, 0xfda11f82, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x80001003, 0xffffffff, 0x80000000, 0xffffdff8, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x001379ca, 0xfffffff0, 0x001379ea, 0x7fffffff, 0xffffffe0, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000005, 0x3fffffff, 0x00000006, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0xcccccccc, 0xcccccccc, 0xcccccd3b, 0x4ccccccc, 0xffffff23, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffffb, 0x00000000, 0x17fffff5, 0x07fffffe, 0x00000003, 0x0, 0x0 + dspck_astio madd, 0x0020d5bf, 0xfe09927b, 0x001d41ff, 0xbf72ee88, 0x14f7a245, 0xffd45329, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0xffffffff, 0xfffffa4a, 0x000002db, 0xfffffffe, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffffe, 0xfff00ff0, 0x03fc03fe, 0xff00ff00, 0x0ffffffc, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x82830e7e, 0xaf9e3020, 0x7ffffff0, 0x05061cfe, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000005, 0x7fffffff, 0xfffa1e9d, 0xfffffffc, 0x0001785a, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0xfffdda1c, 0x00000000, 0x80000000, 0x00044bc8, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffea89, 0x26f1b437, 0x0005e9fc, 0xfc5edff2, 0x0, 0x0 + dspck_astio madd, 0x0072e0a3, 0x0d292f53, 0x0072e0a3, 0x0d292f53, 0x80000001, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x8e38e38e, 0x38e38e38, 0x8e386b90, 0xb8ea1e15, 0x80000007, 0x0000effb, 0x0, 0x0 + dspck_astio madd, 0x00000001, 0xc69d20d5, 0xffffffe1, 0xc69d2115, 0x7fffffff, 0xffffffc0, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00000149, 0xffffedf4, 0xfffffd6c, 0x80000007, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffd7f, 0x00000000, 0x03c47df7, 0xfffffffc, 0xff0edfe2, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x0000003f, 0x80000000, 0x0000003f, 0x00000000, 0xb6db6db6, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0xffffffff, 0x37f33ab0, 0x0e4a0e18, 0xfffffff2, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffe9300, 0xffffffff, 0xfffe9300, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x40000000, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xffff6db5, 0x2e962822, 0xffff6db4, 0xe57195d8, 0xdb6db6db, 0x00000002, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x7f5df778, 0x8a5368d4, 0xf65bcb0a, 0x10ce51e2, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffbf0, 0x0000001d, 0x1ffff84c, 0x000000e9, 0x1ffffffc, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x60000001, 0xffffffff, 0x80000000, 0x3ffffffc, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xffff4ba1, 0xffffffff, 0xffff4ba1, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x800038fa, 0xc9810771, 0x0078c699, 0x0078c699, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000003, 0x40000000, 0x80000003, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x0000003f, 0xffc00000, 0x1800003d, 0xf8000001, 0x07fffffe, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffcde4dd, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000001, 0x7fffffff, 0xfffec3a5, 0x00001a5d, 0xfffffff4, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xffe8df2a, 0xffffffff, 0xbfe8df2d, 0xc0000003, 0x00000001, 0x0, 0x0 + dspck_astio madd, 0xffffc084, 0xa9d71250, 0x3fffc083, 0xa9d71251, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x00621952, 0x74f665b4, 0xc0621952, 0xf4f665b4, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0xef52071c, 0xa6229407, 0xef52072b, 0xa6229353, 0x80000006, 0xffffffe2, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7ffca15a, 0xb6e8e84b, 0xffe8697b, 0x24924924, 0x0, 0x0 + dspck_astio madd, 0xe0000000, 0x00000007, 0xe0000000, 0x014d9d93, 0x00000016, 0x000f2a12, 0x0, 0x0 + dspck_astio madd, 0x92492492, 0x49249249, 0x925914a2, 0x3726904b, 0x0ffffffe, 0x00ff00ff, 0x0, 0x0 + dspck_astio madd, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x3ffffffe, 0x00000003, 0x7ffffffd, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x7fff1876, 0x00000000, 0x0001cf14, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x24924924, 0x92492492, 0x24924924, 0x91d7ac8b, 0x0016b19b, 0xfffffffb, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000002, 0x00000000, 0x00000002, 0xffffff80, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffe, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x1c71c71c, 0x71c71c71, 0x1c71c71c, 0x71c71c71, 0x3fffffe0, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x000099f4, 0xffffff59, 0xffffff14, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x000be722, 0xc71c71c7, 0x71d30394, 0x8e38e38e, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xff8507a5, 0x00000005, 0xffe767ee, 0x0, 0x0 + dspck_astio madd, 0x07ffffff, 0xfffffffc, 0x07fffffe, 0x38e38e34, 0x8e38e38e, 0x00000004, 0x0, 0x0 + dspck_astio madd, 0xffffffe4, 0x21d6a4a1, 0xffffffe2, 0x6453f3c1, 0xe24c9ee0, 0x0000000f, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0x8107de84, 0xfffffffe, 0x0107de84, 0x80000000, 0x00000003, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffe, 0x00000000, 0xffa16359, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x15317c20, 0x00000000, 0x15317c20, 0xffffffcc, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xfffffffb, 0xd6451027, 0xfffffffb, 0xd63833bb, 0xfffffeb1, 0x000009d4, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xf0000000, 0x00000007, 0xf3ffffff, 0x80000007, 0xf8000001, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x00000000, 0x00004990, 0xf8e38e3a, 0x871cbb60, 0xe38e38e3, 0x3ffffff0, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xf98ad94d, 0x000002be, 0xf98ad94d, 0xfffffa82, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xfffffffc, 0x80000000, 0x7fffffec, 0x7ffffff0, 0x00000001, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xfffffff8, 0x800033b9, 0xb7f26246, 0x07ec3057, 0x00068762, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0xaaaaaaaa, 0x2aaaaaaa, 0x55555555, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0xbfffffff, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio madd, 0xe38e38e3, 0x8e38e38e, 0xe38e38e3, 0x8e38e38e, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio madd, 0x00000c9f, 0x004e5a07, 0x00000c9f, 0x004e5a07, 0x0000007f, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0xffffffff, 0xffffffc0, 0xffffffff, 0xffffffc0, 0x00000018, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x7fffffff, 0xffffffff, 0x77733209, 0x7fffffff, 0x80000000, 0x11199bed, 0x0, 0x0 + dspck_astio madd, 0x0002cb5c, 0x75ecc27a, 0x0002cb5c, 0x75ecc27a, 0xffff4350, 0x00000000, 0x0, 0x0 + dspck_astio madd, 0x80000000, 0x00000004, 0x80000016, 0xbfffff4e, 0x3ffffffe, 0x0000005b, 0x0, 0x0 + + writemsg "[14] Test maddu" + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x8f0f0f0e, 0xa5a5a5a5, 0xfffffffa, 0x0f0f0f0f, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0xfffffffd, 0x00000000, 0xfffffffa, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000002, 0x00000002, 0x00000001, 0x0, 0x0 + dspck_astio maddu, 0x8e38e38e, 0x38e38e38, 0x8e38e390, 0x78e38e4d, 0xc0000007, 0x00000003, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xf485f7e8, 0x7fffffdf, 0xf485f7e8, 0x80000000, 0xffffffc0, 0x0, 0x0 + dspck_astio maddu, 0xffffc602, 0x0bedd4a3, 0x7ff8ae5c, 0x0bedd4a3, 0x80000000, 0xfff1d0b4, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xffffff80, 0x012825e2, 0xba0c5d48, 0xffff2bfb, 0x012826d8, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x0000384b, 0xffff1ed0, 0xfffffffc, 0x0000384c, 0x0, 0x0 + dspck_astio maddu, 0xfff8169f, 0xd52b1bbf, 0x7ff7c679, 0xd52bbc09, 0xffff5fb6, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x7ffffff9, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000081, 0x6217888b, 0x03903d05, 0x0000244f, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x1c71c71c, 0x00000000, 0x80000000, 0x38e38e38, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xfffffff9, 0xfffffd75, 0x00001431, 0x7ffffffc, 0xfffffaf2, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffc0, 0x7fffffff, 0xffffffc0, 0x00000000, 0x0c36d40c, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfffffff8, 0x3ffffffe, 0xfffffff9, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0xb5a134d9, 0x722c4676, 0xf22c4676, 0xc0000001, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xffc5d149, 0x000c12ec, 0xffa19882, 0xfffffffd, 0x000c12ed, 0x0, 0x0 + dspck_astio maddu, 0x00670513, 0x80ef3917, 0xf7f447fb, 0x27f9179d, 0xf85cca0f, 0xff2a171a, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xffffffff, 0x00000003, 0xfffffde3, 0xffffff79, 0x00000004, 0x0, 0x0 + dspck_astio maddu, 0x000027ee, 0x118f3a31, 0xfffc0af4, 0x119b9116, 0xfffbe309, 0xfffffffd, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0xb165aeb7, 0x0294ce7a, 0x9cb44f99, 0x02e9dd71, 0xe2ce4602, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000006, 0x4000003e, 0xffffff87, 0x8000007f, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000002, 0x80000000, 0x00000002, 0x00000000, 0x00000057, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00053916, 0xffc402d5, 0x01e5222e, 0xfffffff8, 0xffc402dd, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfffffffe, 0x0000001f, 0x24924913, 0x0000006d, 0x49249249, 0x0, 0x0 + dspck_astio maddu, 0xfffffdaf, 0xac101bf3, 0xbffffdad, 0x6c101bde, 0xfffffff9, 0xc0000003, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfffff5d7, 0x67ddd503, 0xb0444bce, 0x7fffffff, 0xcfbbaa09, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0xfe000000, 0x7fffffff, 0xfc000001, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x007cf5fa, 0x1dc4965b, 0x047cf5f9, 0x1dc4966b, 0x1ffffffc, 0x1ffffffc, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x55555555, 0x55555555, 0x55724881, 0x53f9ef45, 0x0039e658, 0x7ffffffa, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x09e7be3a, 0x37ffffe4, 0xc9e7bdda, 0xe0000003, 0x3fffffe0, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffe, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x000001fe, 0xef21c306, 0x800001f6, 0x6f21c30e, 0xffffffff, 0x7ffffff8, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000063, 0x3fffffff, 0x80000063, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x0fffffff, 0xfffffffe, 0x10000000, 0xefffff86, 0x0ffffff8, 0x0000000f, 0x0, 0x0 + dspck_astio maddu, 0x92492492, 0x49249249, 0x92492492, 0x49249249, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x1fffffff, 0xfffffff0, 0x5fffffff, 0xfffffff0, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xfffffffd, 0x00000006, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x0000001f, 0xbffffffe, 0x80000021, 0x7ffffffe, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x999989af, 0x9999a983, 0x99999999, 0xffffe57b, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xfffedf3f, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x800007ff, 0xf7fe0002, 0x0000ffff, 0x07fffffe, 0x0, 0x0 + dspck_astio maddu, 0xfc000000, 0x00000001, 0x7be65c19, 0x003347cd, 0xffccb834, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0xffffff91, 0x4b79b6c1, 0x1fffff8b, 0x2b79b705, 0xffffffef, 0x1ffffffc, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xffffffe0, 0x7ffe4028, 0x800dfe7c, 0xfffc8059, 0x7ffffffc, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x03ab636c, 0x6b5d12dc, 0xf8000003, 0x03c9b0f4, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x001558b0, 0x3fffffff, 0x001558b1, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0xffffc57f, 0x000074ff, 0x7fffffff, 0xffff8b00, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x55555555, 0x55555555, 0x55555555, 0x5555558d, 0x00000002, 0x0000001c, 0x0, 0x0 + dspck_astio maddu, 0xfffffeef, 0x6427edf8, 0xfffffeef, 0x6427edf8, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x0000001f, 0x4fe76e2a, 0x0000001f, 0x4fe76e2a, 0x00001306, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfe171397, 0xffffffff, 0xfe171397, 0xfffffffd, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xffffffe0, 0x07fffffa, 0x000000e0, 0x7fffffe0, 0x0ffffff8, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000005, 0x80000000, 0x00000005, 0x00000000, 0x00d1f23e, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000005, 0x0000007a, 0xfffffc0d, 0x8000007f, 0xfffffff8, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00000243, 0xfffffb78, 0x7fffffff, 0x00000488, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xf7536e34, 0x7fffffa9, 0x775370c8, 0xffffff5b, 0x7ffffffc, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x0019d51c, 0x0, 0x0 + dspck_astio maddu, 0x1fffffff, 0xfffffff8, 0x6000001f, 0x7ffffff8, 0x80000000, 0x8000003f, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x0000007f, 0x80000000, 0x000000d3, 0x00000015, 0x00000004, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0xedb6db6c, 0xa4924925, 0xdb6db6db, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x000000f8, 0x328b14f1, 0x2aaaaba2, 0xb28b14f1, 0x55555555, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x0fffffff, 0xfffffffc, 0x4fffffff, 0x7ffffffc, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80000015, 0x1c71c6c7, 0x38e38e38, 0x0000005f, 0x0, 0x0 + dspck_astio maddu, 0xffff0000, 0xffff0000, 0x3fff0000, 0x7fff0000, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x003eedcb, 0x8399f5aa, 0x003eedcb, 0x8399f5aa, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x0000007f, 0xf8000003, 0x8000007f, 0xf0000007, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000007, 0xff6dd515, 0x812455da, 0xfedbaa2d, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x8f0f0f0b, 0x3c3c3c40, 0x0ffffffc, 0xf0f0f0f0, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000004, 0xb6db6d5a, 0x92492504, 0xffffff80, 0xb6db6db6, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xfffffffc, 0xfffdfcd0, 0x0004065a, 0xfffbf9a2, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x38e38e38, 0xe38e38e3, 0x38e391b4, 0xe388c723, 0xfffffe70, 0x0000037c, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x78100001, 0xf8000000, 0xfc000001, 0xfc000001, 0x0, 0x0 + dspck_astio maddu, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x7ffffffe, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000024, 0xc0000019, 0xbfffff4b, 0xfffffff9, 0xc000001f, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x8000003f, 0x80000000, 0x0000007f, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x1fffffff, 0xfffffff8, 0x256ad256, 0x7ffffff8, 0x80000000, 0x0ad5a4ad, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x38e38e38, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x85a7353d, 0xd2c65610, 0xfffffff8, 0x05a7353e, 0x0, 0x0 + dspck_astio maddu, 0x92492492, 0x49249249, 0x9249249a, 0x09249059, 0x0000001f, 0x3ffffff0, 0x0, 0x0 + dspck_astio maddu, 0xffffac83, 0x13403e4f, 0xffffac83, 0x13403e4f, 0x00000000, 0xfffff96f, 0x0, 0x0 + dspck_astio maddu, 0x00000016, 0x288440c6, 0x40000016, 0x288440c6, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x0000000e, 0xd0ad2f8f, 0x0000000f, 0xfcd85881, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000007, 0x6cb5f2b1, 0x818d590f, 0x8000003f, 0xd96be4f8, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000005, 0x00000000, 0x00000005, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x80000000, 0xfffffffc, 0xfffffffe, 0x80000002, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x0000000b, 0x0007f5dc, 0x8000000b, 0x80000000, 0x000febb9, 0x0, 0x0 + dspck_astio maddu, 0xf0000000, 0x00000003, 0xf0000000, 0x00000003, 0x00000000, 0x80000001, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x8150cfff, 0x1eaa8726, 0xfffffd0d, 0x0150d003, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000299, 0x0, 0x0 + dspck_astio maddu, 0x00000014, 0x9ae8eb85, 0x24924939, 0xf656a260, 0x80000003, 0x49249249, 0x0, 0x0 + dspck_astio maddu, 0xfffe40ab, 0x2cbb3242, 0x0ffe40a3, 0x0cbb3252, 0xfffffffe, 0x0ffffff8, 0x0, 0x0 + dspck_astio maddu, 0xc0000000, 0x00000007, 0xc0000000, 0x00000007, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000001, 0x7fff447e, 0x80000001, 0x80000000, 0xfffe88fd, 0x0, 0x0 + dspck_astio maddu, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1c71c71c, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0002cd56, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80000001, 0xfffffff1, 0x00000002, 0xfffffff9, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xfffffffc, 0x871c71c3, 0x81c71c74, 0x71c71c71, 0x0ffffff8, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000007, 0x7fffffcf, 0x80000066, 0x7fffffff, 0xffffffa1, 0x0, 0x0 + dspck_astio maddu, 0xaaaaaaaa, 0xaaaaaaaa, 0xa6aaa82d, 0xcaaaa822, 0xfc000001, 0xfffffd78, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80000000, 0x13fffff5, 0x00000005, 0x03fffffe, 0x0, 0x0 + dspck_astio maddu, 0xff9edb1e, 0x08c07004, 0x009d8e06, 0xd0f88652, 0xffb19bb2, 0x00ff00ff, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x9ffffff0, 0x000001ff, 0x7fffffe0, 0x3ffffff0, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x818282c8, 0x5d9bac70, 0x03050590, 0x8000001f, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x38e38e38, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000589, 0x00000002, 0x000002c5, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xf2760d6d, 0xc71c7021, 0x643d2a1b, 0xc71c71c7, 0xfffffde2, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfffffff7, 0x3fffffff, 0xfffffff7, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0xfffff4f2, 0xbe4f2c0a, 0x38e3832b, 0x3e4f2c0a, 0x71c71c71, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xffffffff, 0x7fffec1b, 0xffff38e5, 0x80000005, 0xffffd82e, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0xf0000000, 0x00000007, 0xf0000000, 0x00000007, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00010387, 0x7ffdf8f1, 0x0002070f, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000003, 0x00000000, 0x00000003, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00004efc, 0x7ffffff9, 0x80004f07, 0x7fffffff, 0xfffffff5, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x7e000000, 0x80000000, 0xfc000001, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffe0, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00010d4d, 0x01c71c71, 0x4e39f0dd, 0x0ffffffc, 0x1c71c71c, 0x0, 0x0 + dspck_astio maddu, 0x0000064d, 0xc5646196, 0x800004fd, 0x456456f2, 0xfffffd57, 0x80000004, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfffe758e, 0xffffffff, 0xfffe758e, 0x00000000, 0xfffffffb, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x04c74fae, 0x33333331, 0x6b2db616, 0xfffffff8, 0x33333333, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0xe0000001, 0xbfffffd6, 0xfffffffa, 0xe0000007, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1ffffff8, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0xf0000000, 0x00000001, 0x6ffffb95, 0x80000001, 0x80000000, 0xfffff72b, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000002, 0x00000000, 0x00000002, 0x00000000, 0xfffffd32, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x83fffffe, 0xffffffff, 0x07fffffe, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0xf8000000, 0x00000001, 0xe8f0f0b3, 0xc3c3c401, 0xf0f0f0f0, 0xffffffc0, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000001, 0x1c71c718, 0x0000000a, 0x1c71c71c, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x0000000f, 0x80d05620, 0x762e6c85, 0x00d05632, 0xffffea73, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xf01a2f3a, 0x70000007, 0x701a2f3a, 0x80000000, 0xe000000f, 0x0, 0x0 + dspck_astio maddu, 0x0006a63e, 0xec0d609e, 0x0006a63e, 0xec0d609e, 0x00000000, 0x00000006, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x84dba689, 0xf648b2ec, 0x04dba68a, 0xfffffffe, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xffff88cd, 0x3fffffdf, 0xffff88cd, 0x7fffffc0, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x07fffffe, 0x0, 0x0 + dspck_astio maddu, 0xf0000000, 0x00000007, 0x0ffffff4, 0x00000107, 0x7ffffff0, 0x3ffffff0, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0xbfffffff, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x188fc626, 0x7ffe35df, 0x98935a65, 0xfffc6bc1, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x7f83f0b4, 0x02e85ba4, 0xfffffffa, 0xff83f0ba, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x0000000e, 0x00000000, 0x80000000, 0x0000001c, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfffb1ef8, 0xffffffff, 0xfffb2072, 0x0000003f, 0x00000006, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000003, 0xc0000000, 0x00000003, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfffffffe, 0x40000006, 0xffffffef, 0x7fffffff, 0x8000000f, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x0008246c, 0x00000000, 0x0008246c, 0x00000000, 0xfffffff8, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x007f807f, 0x7f00ff01, 0x7fffffff, 0x00ff00ff, 0x0, 0x0 + dspck_astio maddu, 0x71c71c71, 0xc71c71c7, 0xf1c39a3d, 0xc723762d, 0xfff8fb9a, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xfffffffa, 0x80000002, 0x94f8b209, 0x0000003f, 0x0a7dda31, 0x0, 0x0 + dspck_astio maddu, 0x1fffffff, 0xfffffff8, 0x2000002f, 0x400003a9, 0x0000003f, 0xc000000f, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0xff807f80, 0x00000000, 0x80000000, 0xff00ff00, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xfffffffc, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x0000007b, 0x7fffff09, 0x7fffffff, 0x000000f7, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfffc2ba3, 0xffffffff, 0xfffc99a4, 0x0000003f, 0x000001bf, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x5ffffff8, 0xffffff8f, 0xe0000007, 0xfffffff0, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x0000007f, 0x800000ea, 0x4fffc5eb, 0x07fffffe, 0x00001d4a, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000003, 0x26666653, 0x0ccccce3, 0x3fffffe0, 0x99999999, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xc71c71c7, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x0000007f, 0xffffcf89, 0x7ffd59a2, 0xffff9f05, 0x80000007, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80000000, 0x954e660f, 0x00000d84, 0x000b0c04, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00009813, 0x00000000, 0x00009813, 0x00000000, 0x8000000f, 0x0, 0x0 + dspck_astio maddu, 0x1c71c71c, 0x71c71c71, 0x1cf1479b, 0xe9cf1479, 0x7ffffff8, 0x00ff00ff, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x2f91e634, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000131, 0xef746c23, 0xfd53dbd9, 0xef747747, 0xfffff418, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x8000000b, 0x400001d1, 0x0000000f, 0xc000001f, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x013d4de2, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffe0, 0xbfffffff, 0x7fffffe0, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7ffffefc, 0x000003ff, 0xffffff00, 0xfffffffc, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00193438, 0xfd25158b, 0xffffffe3, 0x00193439, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xf8550280, 0x0ffffffb, 0xd8550090, 0x1ffffff0, 0x8000001f, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x89172bed, 0xffffffa0, 0x89172ead, 0xffffffa8, 0xfffffff8, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00ce6f01, 0x00000005, 0x00ce6ef7, 0x7fffffff, 0x0000000a, 0x0, 0x0 + dspck_astio maddu, 0xaaaaaaaa, 0xaaaaaaaa, 0x8aaaaa8f, 0xaaaaaa8a, 0xe0000001, 0xffffffe0, 0x0, 0x0 + dspck_astio maddu, 0x0fffffff, 0xfffffff8, 0x0ffffff8, 0x00000004, 0xfffffffe, 0xfffffffa, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x0000007f, 0x0, 0x0 + dspck_astio maddu, 0x09e9a721, 0x9b487a5c, 0x08eaa620, 0x9c477b5c, 0xff00ff00, 0xffffffff, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xffffff21, 0xffffffff, 0xffffff21, 0xc0000001, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x0000015c, 0xffee2d59, 0x4af0f94b, 0xffffed5b, 0xffee3ffd, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xfffffff8, 0x7fffffff, 0xfffffff8, 0x1ffffffe, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000007, 0x80000000, 0x00000007, 0x00000000, 0x38e38e38, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000005, 0xd42fd82f, 0x00000035, 0x1c278b53, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfff115b6, 0x0059de97, 0x38c7cd47, 0x00738be7, 0xc71c71c7, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x7ffffff9, 0x80000000, 0xfffffff3, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x06cfe542, 0x071c71c5, 0x3fb37382, 0x38e38e38, 0x1ffffff8, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x1b41447d, 0x01d126b3, 0x0000000f, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0xfffffc3e, 0x00000782, 0xfffff87e, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0xfffac4fc, 0x89ac2465, 0x0004c00f, 0xdb90136d, 0xffffd4e8, 0x0009fb15, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000007, 0x00000000, 0x80000000, 0x0000000e, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000007, 0x3be51184, 0x00000024, 0x33710799, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x000078f7, 0x006f346e, 0xe4e72317, 0x09923530, 0x0b9e6896, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x009b80a3, 0x0, 0x0 + dspck_astio maddu, 0x6db6db6d, 0xb6db6db6, 0x34d1da6a, 0x61864d59, 0xfffe2345, 0xc71c71c7, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x3ffffff4, 0x3fffff50, 0xc0000007, 0xffffffe7, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00001c17, 0x00051873, 0xf9619ebb, 0x0241e01a, 0x0241e01a, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x36bd3d24, 0x71c71ba6, 0x8c1293dc, 0xfffffe38, 0x71c71c71, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80000006, 0xf0981053, 0x0091369b, 0x00000c3c, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xffff0767, 0x0000016a, 0x7fff0767, 0x000002d5, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000005, 0x12492491, 0x2492492d, 0x7ffffffa, 0x24924924, 0x0, 0x0 + dspck_astio maddu, 0xffffff2f, 0xfa69e3a1, 0x3fffff2f, 0xfa69e3a1, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x028c52e8, 0x00000000, 0x028c52e8, 0x0007084a, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0xe0000000, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0x80000007, 0x0, 0x0 + dspck_astio maddu, 0x00000046, 0xee62b809, 0x70000047, 0x6e62b809, 0x80000000, 0xe0000001, 0x0, 0x0 + dspck_astio maddu, 0x8e38e38e, 0x38e38e38, 0x8e38e48d, 0x38e2d2f4, 0x000000ff, 0xffffff44, 0x0, 0x0 + dspck_astio maddu, 0x92492492, 0x49249249, 0x92492492, 0x49249249, 0xfffffc15, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x1c71c71c, 0x71c71c71, 0xd849e8ec, 0x2c3c9eda, 0xfa758269, 0xc0000001, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x0000001f, 0xffffff7e, 0x8000019f, 0xfffffffd, 0x7fffff80, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffe0, 0x7fffffff, 0xffffffe0, 0x00000000, 0x000ce333, 0x0, 0x0 + dspck_astio maddu, 0x0d8fbb41, 0x1c73dc5d, 0x8d72bf59, 0x1cadd42b, 0x7fffffff, 0xffc60832, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7ffffffb, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xffdcb2ba, 0x000000a5, 0xfb1f0932, 0xfff8b054, 0x000000a6, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0xfc000001, 0x80000000, 0x80000000, 0xf8000003, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80060038, 0x7ff3ff8e, 0x000c0071, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x3fffffe0, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x800000eb, 0x165494e0, 0x000007fb, 0x1d7533d3, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x87ffffff, 0x00000000, 0x0ffffffe, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x0000185d, 0x77927fa7, 0x0000185d, 0x77927fa7, 0x07fffffe, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000001, 0x80000000, 0x00000001, 0x0000778b, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0xbfffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffff00, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x8000562c, 0x7fffffff, 0x80000000, 0x0000ac59, 0x0, 0x0 + dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80001e96, 0xffe2f6aa, 0x00001e97, 0xffffff0d, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0xa6666666, 0xd9999999, 0xc0000003, 0x33333333, 0x0, 0x0 + dspck_astio maddu, 0x1fffffff, 0xfffffff8, 0x5fffffff, 0x7ffffff8, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xffffff00, 0x00000098, 0xfffffe67, 0x000000ff, 0x99999999, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0xef1f79f1, 0x49738e4d, 0xff10820b, 0xf0000007, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000000, 0x0001df85, 0x00000000, 0x80000000, 0x0003bf0a, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0xb8e38e38, 0x80000000, 0x80000000, 0x71c71c71, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfffffffe, 0xffe36072, 0x03217076, 0xffe3608e, 0xffffffe4, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000003, 0x80000000, 0x80000002, 0x7fffffff, 0x00000001, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfff91d9f, 0x7ffffffe, 0xfff91d9f, 0xfffffffe, 0x80000000, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x800011db, 0xfae22060, 0x000011dc, 0xffffb6a8, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0x5e860602, 0xffffffff, 0x5e8cc489, 0x000000fd, 0x000006d3, 0x0, 0x0 + dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio maddu, 0x00000000, 0x00000155, 0x3ffffffe, 0x80000155, 0x80000000, 0x7ffffffd, 0x0, 0x0 + dspck_astio maddu, 0x0000d6fa, 0x92c7d6ba, 0x002cd92c, 0x1377df80, 0x00580463, 0x80000002, 0x0, 0x0 + dspck_astio maddu, 0xffffca4e, 0xdb17acf9, 0x7fffc9f8, 0x5b17af8d, 0xffffff5b, 0x7ffffffc, 0x0, 0x0 + dspck_astio maddu, 0xffffffff, 0xfffffffd, 0xffffffff, 0xfffffffd, 0x00000000, 0x0ffffffc, 0x0, 0x0 + + writemsg "[15] Test msub" + dspck_astio msub, 0x7fffffff, 0xfffffff9, 0x40000000, 0xfffffff8, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x0fffffff, 0xfffffffc, 0x10001354, 0xffffd952, 0xffffd956, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x7fffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x1fffffff, 0xfffffffe, 0x1fffffff, 0xfffffffe, 0x00000000, 0x8000007f, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0xffffffc0, 0x400003fc, 0x3ffffffc, 0x000000ff, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfffffdc7, 0xfffffffe, 0x7ffffdc7, 0x80000000, 0xfffffffd, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7ffffffb, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0000064f, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x000100e4, 0xfffdfe36, 0xfffdfe36, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xfffffff0, 0x800022b5, 0x7fffba85, 0x7fffffff, 0xffffba95, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfffffff3, 0x0000003a, 0xfffffff3, 0x80000000, 0x00000076, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffffe89, 0x0ba42fce, 0x000007cf, 0x3004a7ff, 0x0, 0x0 + dspck_astio msub, 0xcccccccc, 0xcccccccc, 0xccc85c69, 0x4ccccccc, 0xfff71f39, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffe, 0x0000ffff, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0xffff0000, 0xffff0000, 0xffff0000, 0xffff0000, 0x00000000, 0x0ffffffe, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x0000000f, 0xffffff77, 0x24924799, 0xdb6db6db, 0xfffffc42, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x7fc9d069, 0x7b17cb50, 0x0ffffff8, 0x0362f96a, 0x0, 0x0 + dspck_astio msub, 0x6db6db6d, 0xb6db6db6, 0x6db6db6d, 0xb6db6db6, 0x00000000, 0xffffe47c, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x80000003, 0xfffffff7, 0xfffffff8, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xff78ed21, 0xffffffff, 0xff78ed21, 0x11ff3312, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x87c8a81d, 0x706eafc4, 0x7fffffff, 0xf06eafc5, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xe0000001, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffffcc6, 0x00000673, 0x7fffffff, 0x00000674, 0x0, 0x0 + dspck_astio msub, 0xf0000000, 0x00000007, 0xb000001f, 0x80000007, 0x8000003f, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfffd15b4, 0x00000004, 0xd7fd13e3, 0x0000009b, 0xf8000003, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0x0000000f, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000a66, 0x7ffeb330, 0xffffeb33, 0x7ffffff0, 0x0, 0x0 + dspck_astio msub, 0x000001bc, 0xeb36bc19, 0x000001d2, 0xeb36bab9, 0x7ffffff8, 0xffffffd4, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00003f07, 0xc0000001, 0x00003f06, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x00000024, 0x11b7df27, 0x00000087, 0x11b7df27, 0x000000c6, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffffff0, 0x0000005f, 0x80000003, 0xffffffe0, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000074, 0x000000c7, 0xfffff8a4, 0x00000190, 0x80000005, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000d09, 0x00246ddb, 0x6d253109, 0xff00ff00, 0x24924924, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0xf1c71c71, 0x80000000, 0xe38e38e3, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00000fef, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xffffc89c, 0xffffffc0, 0x3fffe87c, 0x000000ff, 0x3fffffe0, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x0000007f, 0x6db6db6e, 0xdb6db757, 0x7ffffffa, 0x24924924, 0x0, 0x0 + dspck_astio msub, 0x000006d1, 0x2c0ed11c, 0x000013ce, 0x2c0ec41f, 0xffffd909, 0x55555555, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffff80, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xfffffff8, 0x7fffffff, 0xfffffff8, 0xcccccccc, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x801af064, 0x5543e6e9, 0x06bc1917, 0xfc000001, 0x0, 0x0 + dspck_astio msub, 0xe0000000, 0x00000001, 0xe0000000, 0x00000001, 0x0030397d, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x7ffffffe, 0x80000003, 0x00000003, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffe166a, 0x800f4cab, 0x80000004, 0xfffc2cd5, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x871c71c7, 0x071c71c6, 0x3ffffffe, 0xe38e38e3, 0x0, 0x0 + dspck_astio msub, 0xb6db6db6, 0xdb6db6db, 0xd6db6daf, 0x1b6db6ea, 0xc000000f, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0xff00ff00, 0xff00ff00, 0xff011176, 0x7f00ff00, 0x80000000, 0x000024eb, 0x0, 0x0 + dspck_astio msub, 0x000a3ed2, 0xb6e3cbee, 0x000a3ed2, 0xb6e3cbee, 0xfffff9a0, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x000000ff, 0x00000008, 0x000000ef, 0x7fffffff, 0xfffffff0, 0x0, 0x0 + dspck_astio msub, 0xb6db6db6, 0xdb6db6db, 0x76db6db9, 0xdb6db6db, 0x80000000, 0x80000006, 0x0, 0x0 + dspck_astio msub, 0x0316d902, 0xa34af328, 0x0316d902, 0xa34af328, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x000011cd, 0x90eda3a7, 0x000011cd, 0x90eda3a7, 0xffffe886, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00007e56, 0x9ed89c04, 0x40007e56, 0x1ed89c04, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x1fffffff, 0xfffffffe, 0x20000000, 0x0002d92e, 0x0000b64c, 0xfffffffc, 0x0, 0x0 + dspck_astio msub, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xffffb77a, 0x00000212, 0x00000023, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0xbffffffb, 0x00000019, 0x7ffffffb, 0x80000005, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xc000001f, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x005ba7e3, 0x00000000, 0x005ba7e3, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x80000003, 0x4bfa8804, 0xfffd37f2, 0x00012f6e, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x000013fb, 0xfffff795, 0x0000467d, 0x7ffffffd, 0x000010d6, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x81ffffff, 0x7c000001, 0xfc000001, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0xc0000000, 0x0000001f, 0xc0000008, 0x0000000f, 0xfffffff0, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0xffffffff, 0xfff42292, 0x00000075, 0x000019f6, 0x0, 0x0 + dspck_astio msub, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0xfffffff8, 0xffffffe0, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xfffffffc, 0x7f650c32, 0x8135e797, 0x0135e79b, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x0000a325, 0x1b6dbc2b, 0x0000a325, 0x1b6dbc2b, 0x00000000, 0x000002fc, 0x0, 0x0 + dspck_astio msub, 0x0263b7c4, 0x3d87f376, 0x0263b7c4, 0x3d87ffc4, 0xffffffff, 0x00000c4e, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0x3afbdbbb, 0x00000001, 0xbafbdbb6, 0x7fffffff, 0xfffffffb, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000c62, 0xfffffffc, 0x80000c69, 0x7fffffff, 0x00000007, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x7fffffff, 0xfffe147a, 0xfffffffe, 0xffff0a3d, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x70000007, 0x7fffffff, 0x80000000, 0xe000000f, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0xffffffff, 0xffffff0d, 0xffffffff, 0xffffff0d, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x80079013, 0xce94fc48, 0x0079013d, 0xf0000003, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffe0, 0x40000001, 0xffffffdd, 0x7ffffffd, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x0000ffff, 0x0000ffff, 0x00014584, 0x0000ffff, 0x80000000, 0x00008b0a, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x000029cb, 0x8b721de9, 0x00708e73, 0xffa0f0cd, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00016105, 0x98d8ef9e, 0xe0016115, 0xd8d8ef7e, 0x7fffffff, 0x3fffffe0, 0x0, 0x0 + dspck_astio msub, 0x0fffffff, 0xfffffffc, 0x0fffffff, 0xfffffffc, 0xfffffff0, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x001f4978, 0xffc16d0e, 0xffc16d0e, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x005ec8cf, 0xe0000000, 0x805ec8cf, 0x80000000, 0xc0000001, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x007f807f, 0x80000000, 0x80000000, 0x00ff00ff, 0x0, 0x0 + dspck_astio msub, 0x06036d31, 0xd4e8c0c4, 0x06036d31, 0xd4732c00, 0xfffffffc, 0xffe29acf, 0x0, 0x0 + dspck_astio msub, 0x00000001, 0xacf931be, 0x00000000, 0xacf931bb, 0xfffffff9, 0xdb6db6db, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0xffffffe0, 0x8000003f, 0x0000003f, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000007, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7ffffff8, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfff83da3, 0x00000000, 0x0057f2e3, 0xffffffc0, 0x00017ed5, 0x0, 0x0 + dspck_astio msub, 0xc0000000, 0x00000001, 0xc0000000, 0x00000001, 0x00000000, 0xfffffff3, 0x0, 0x0 + dspck_astio msub, 0x00000002, 0xb02b83e8, 0x00000002, 0xb02b83e8, 0x00000000, 0x7fffffe0, 0x0, 0x0 + dspck_astio msub, 0xcccccccc, 0xcccccccc, 0xffffffff, 0xe6666665, 0x99999999, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfffff646, 0x00000000, 0xfffff646, 0x00000002, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000001, 0xfffffff2, 0x38e38e52, 0x71c71c71, 0x0000001f, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0xc71c71c7, 0x7ffffff0, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0xffffd375, 0xe706709a, 0xffffd375, 0x0b98b9c2, 0x24924924, 0x00000006, 0x0, 0x0 + dspck_astio msub, 0xffffffed, 0x0cbdc42f, 0xf6db6da4, 0xa82b7b0d, 0xb6db6db6, 0xe0000003, 0x0, 0x0 + dspck_astio msub, 0x00000033, 0x69c5c9e1, 0x00000033, 0x69c5c9e1, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x0000006e, 0x00037120, 0x5e7e8244, 0xf0000007, 0x00371206, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfffffffe, 0xffffffff, 0xff8c0c02, 0xfffffffc, 0xffe30301, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xffffff92, 0x03fffffd, 0xf7ffff96, 0x80000001, 0x07fffffc, 0x0, 0x0 + dspck_astio msub, 0x00000003, 0xc7a8bdc2, 0x40000003, 0x47a8bdc2, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00105539, 0x7fdf558d, 0xffdf558d, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xfffffffd, 0x7ffffff7, 0xfffffffd, 0xfffffff0, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x00000f18, 0x9ad32c8b, 0x00000f1a, 0x9ad32c8b, 0x00000004, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0xf0000000, 0x00000007, 0xdce455ea, 0xa6375432, 0x2637542b, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x66666666, 0x66666666, 0x62666668, 0x6e666662, 0x7fffffff, 0x07fffffc, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x0002ad3e, 0xc0000002, 0x0002ad3a, 0x7ffffffe, 0x7ffffffe, 0x0, 0x0 + dspck_astio msub, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccae6, 0x00000001, 0x000001e6, 0x0, 0x0 + dspck_astio msub, 0x00000005, 0xe272b611, 0x2492492a, 0x994e23c7, 0xb6db6db6, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0xdb6db6db, 0x6db6db6d, 0xdb6db5ef, 0xedb6db6d, 0x80000000, 0xfffffe29, 0x0, 0x0 + dspck_astio msub, 0xf242cc75, 0x02467cd4, 0xf242cc74, 0x82467cd4, 0x80000000, 0xffffffff, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xefeac421, 0x0084d062, 0x0000001f, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x7ffffffc, 0x4924923e, 0xb6db6db6, 0xfffffff3, 0x0, 0x0 + dspck_astio msub, 0xf0000000, 0x00000003, 0xeb01db92, 0x00000003, 0x80000000, 0xf603b724, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x80012949, 0xffffffff, 0x80000000, 0x00025294, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0xffffffff, 0xffffff1f, 0x0000000f, 0x0000000f, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x0000000f, 0x80043b77, 0xfff7891f, 0x7fffffff, 0xfff78910, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x3c291b99, 0x0000003d, 0x3c291b1f, 0xffffff86, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfffff6c2, 0xffffffff, 0xfffff6c2, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffb, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfee0ff36, 0x00000000, 0x6ee0ff05, 0x00000007, 0xf0000007, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0xffffffff, 0xc538de82, 0x00000007, 0x08659712, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfffe43ab, 0x00000000, 0x0ffe43a4, 0x00000001, 0xf0000007, 0x0, 0x0 + dspck_astio msub, 0xfffffd73, 0x39c3f5aa, 0xfffffd73, 0x39c3f5aa, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x0000364b, 0xffffffff, 0xff0f7a3b, 0x00000f84, 0x00000f84, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x0000001f, 0x80000000, 0x0000001f, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0xfff9873f, 0x244a0fed, 0xfff9873f, 0x24414cfd, 0x00008c2f, 0x00000010, 0x0, 0x0 + dspck_astio msub, 0x039dc6dd, 0x7a4758ed, 0x039dc6bd, 0xfa47592c, 0x7fffffff, 0x0000003f, 0x0, 0x0 + dspck_astio msub, 0xfffffff8, 0x3f5ec4f0, 0x0001cdf0, 0xbf5ec4f0, 0x00039bf1, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x00000001, 0x28e115bc, 0xfffffffe, 0x2d393a9c, 0xe822c127, 0xffffffe0, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fff9d05, 0x0062faff, 0x7fffff80, 0x0000c5f6, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x000002e3, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000004, 0xfffffffe, 0x80000010, 0x3ffffffe, 0x00000006, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x0000003f, 0xfffff39d, 0x0000003f, 0x80000000, 0xffffe73a, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0xbffffffe, 0x80000000, 0x7ffffffd, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0xfffe6dbf, 0x5b9a00bd, 0x008379c9, 0xda8fe8a8, 0x7fffffff, 0xfef5e7eb, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfff77cf1, 0x1bcfcca6, 0x4857e3a4, 0x7fffffff, 0xc86066b3, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xfffffffb, 0x7fffffff, 0xfffffffb, 0x0000b239, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00a38021, 0x4abde701, 0xf0a38021, 0xcabde701, 0x80000000, 0xe0000001, 0x0, 0x0 + dspck_astio msub, 0xc0000000, 0x0000001f, 0xc0000000, 0x0000001f, 0x00000000, 0xfffa9d9f, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0xb6db6db6, 0xdb6db6db, 0xb6db6db6, 0xdb6db6db, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000077, 0xfffffff8, 0x0000000f, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xffffffe0, 0x00000000, 0x02d0b311, 0xfff48f71, 0x0000003f, 0x0, 0x0 + dspck_astio msub, 0x33333333, 0x33333333, 0x00000000, 0x99999999, 0x66666666, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfffffffc, 0x3fffffff, 0x7ffffffc, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x8000000f, 0x80000000, 0x80000000, 0x0000001f, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0xffffffff, 0xffffffe4, 0x0000000e, 0x00000002, 0x0, 0x0 + dspck_astio msub, 0xe0000000, 0x00000007, 0xe0000000, 0x00000007, 0x0005cf66, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffffffc, 0xf0f0f0bf, 0xf0f0f0f0, 0xffffffcc, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x8007494b, 0x1fc5b5a7, 0x003a4a59, 0xe0000001, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x001039ca, 0x00000000, 0x001039ca, 0x3ffffff8, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffffbcf, 0xf0004300, 0xffffbcff, 0xf0000001, 0x0, 0x0 + dspck_astio msub, 0x0001b171, 0x4c2f383a, 0x4001b16c, 0x4c2f384a, 0x7ffffff8, 0x80000002, 0x0, 0x0 + dspck_astio msub, 0x00ff00ff, 0x00ff00ff, 0x00feecde, 0x9a984a17, 0xcccccccc, 0xffff9b5e, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x0000000e, 0x00000000, 0x80000000, 0x0000001c, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000f, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000050, 0x9a998ea7, 0x00000050, 0xda59ce67, 0x00ff00ff, 0xffffffc0, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0x1b1536d5, 0xff807f7f, 0x39f655d5, 0xff00ff00, 0x8000001f, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x7f340f68, 0x8197e12f, 0x7fffffff, 0x0197e12f, 0x0, 0x0 + dspck_astio msub, 0xf2b4a4d7, 0x7964e9af, 0xf2b4a4a9, 0xf964e9af, 0xffffffa5, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x871c71c5, 0x5555555b, 0x1c71c71c, 0xc000000f, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfffffffa, 0x00000000, 0x4ec6b0c5, 0x00821b91, 0xffffff65, 0x0, 0x0 + dspck_astio msub, 0xe38e38e3, 0x8e38e38e, 0xe38e38e3, 0x8e3bbb5d, 0xfffffff9, 0x000067f9, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000006, 0x80000000, 0x0069dcef, 0x0000f427, 0xffffff91, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffe2c94, 0x81cfc4a8, 0xfffc5929, 0x8000007f, 0x0, 0x0 + dspck_astio msub, 0xdd77f580, 0x9331e18a, 0xdd37f580, 0xb331e186, 0x07fffffe, 0x07fffffe, 0x0, 0x0 + dspck_astio msub, 0xe38e38e3, 0x8e38e38e, 0xe38e38e3, 0x8e38e38e, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x00000059, 0x2f248d6e, 0x00000059, 0x2f248d6e, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaca, 0xaaaaaa6a, 0xffffffc0, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000f98, 0xfffed780, 0x329b954b, 0xf6449993, 0xffe1889f, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0000007f, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0xe0000000, 0x00000001, 0xe9249248, 0x00000005, 0xc0000007, 0x24924924, 0x0, 0x0 + dspck_astio msub, 0xe1d4841b, 0x83a41544, 0xe1d4841b, 0x83a41544, 0x00000000, 0xfffffffa, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000007, 0x80000000, 0x000796e1, 0xfffff506, 0x000000b1, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000005, 0x3fffffff, 0x80000005, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xffc8ea08, 0xffca3761, 0x00347b46, 0x7fffffff, 0x006b913e, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x80000004, 0x6db6db7a, 0xdb6db6db, 0x0000001f, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xfffffff9, 0x87fffffb, 0xfffffff9, 0x0ffffff8, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x000002c5, 0x3ef67d53, 0xffff1305, 0xbef85cd2, 0x7fffffff, 0x0001df7f, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x01b5373c, 0xfffffffd, 0x0091bd14, 0x0, 0x0 + dspck_astio msub, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000005, 0x7ffffffd, 0x00000005, 0x80000000, 0xfffffffa, 0x0, 0x0 + dspck_astio msub, 0x3fffffff, 0xfffffff0, 0x00000001, 0x7ffffff0, 0x80000003, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0xc71c71c7, 0x1c71c71c, 0xc31c71c9, 0x2c71c714, 0x7ffffffe, 0x07fffffc, 0x0, 0x0 + dspck_astio msub, 0x00000839, 0x19ba9cf0, 0x00000854, 0x99ba9cf0, 0x00000037, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xfffffffa, 0x7ffffff0, 0x80000019, 0x0000001f, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x0000003f, 0x0003e603, 0xfff83437, 0xfff833f8, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xa8c61add, 0xffe2d17d, 0x290077e2, 0x003a5d05, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x0000003f, 0xffff1124, 0x0000003f, 0x80000000, 0xfffe2248, 0x0, 0x0 + dspck_astio msub, 0xfffff17c, 0xe6b637c5, 0x3ffff17c, 0x66b637c5, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x49249249, 0x24924924, 0x4924cd7d, 0xa491d2bb, 0xffff8997, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0xfffffff8, 0xf2102784, 0xfffffffb, 0xf210261c, 0xe000000f, 0x00000018, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x7fffffe0, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x0ffffffd, 0x4000001c, 0x3ffffffc, 0xc0000007, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0x4b830639, 0x0058a1f8, 0x4ad1c247, 0x7fffffff, 0xff4ebc0e, 0x0, 0x0 + dspck_astio msub, 0x0000484f, 0x8556c9da, 0x0000484f, 0x8556c9da, 0xfe4416d8, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfffc5b3b, 0xffffffff, 0xfffc5b3b, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x9ffffffe, 0x00000000, 0x3ffffffc, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0xc0000000, 0x00000007, 0xf333332d, 0x0000000d, 0x8000000f, 0x66666666, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00001c37, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000003, 0xffcdb199, 0x80649cd0, 0x7fffffff, 0x00649ccd, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x000c297f, 0x00000000, 0x4ef5190e, 0x000035e9, 0xfffe8949, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7f442475, 0x45dedc55, 0x3ffffffe, 0x02ef6e2b, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xfffffffa, 0x7fffffff, 0xfffffffa, 0x00000000, 0x005faa47, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0000001f, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x3fffffff, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfffa8dc5, 0x00000005, 0x7ffa8dc5, 0x0000000b, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0xe0000000, 0x00000001, 0xe0000000, 0x00000001, 0x00000000, 0x00000002, 0x0, 0x0 + dspck_astio msub, 0x0fffffff, 0xfffffffc, 0x00000000, 0x7ffffffc, 0xe0000001, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xfe82a28a, 0x000139ba, 0x7e802f15, 0x7fffffff, 0xfffd8c8b, 0x0, 0x0 + dspck_astio msub, 0xc0000000, 0x00000007, 0xe4924924, 0xb6db6dbd, 0x7fffffff, 0xb6db6db6, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x0000003f, 0xffffffff, 0xfffffc7e, 0xffffffe1, 0xffffffe1, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003817, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0x78000004, 0x0ffffff8, 0x0ffffff8, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0xf0000000, 0x00000003, 0xefffd69d, 0x00000003, 0xffffad3a, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffffce3, 0x11ce68e0, 0xc93b28a5, 0xfffff173, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0xffffff00, 0x1fffffd8, 0x80000680, 0xc000000f, 0x7fffff80, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x0000003f, 0x800003c1, 0xfffc3e3f, 0xfffff87c, 0x7fffff80, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ea2fc28, 0xce29d0a3, 0x0368899a, 0x66666666, 0x0, 0x0 + dspck_astio msub, 0x00ff00ff, 0x00ff00ff, 0x20ff00fd, 0x40ff0102, 0x7fffffff, 0xc0000003, 0x0, 0x0 + dspck_astio msub, 0xffffffff, 0x0d11f651, 0x1ffffff7, 0x0d11f651, 0x80000000, 0x3ffffff0, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0xffffffff, 0xe0000006, 0xf0000003, 0xfffffffe, 0x0, 0x0 + dspck_astio msub, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0fa3a01, 0x000000c1, 0xfffff3af, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000005, 0x7fe29a0e, 0xc3acbe2d, 0x007597c5, 0x3ffffff8, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000000, 0xbfffffff, 0x00000001, 0x7fffffff, 0x80000001, 0x0, 0x0 + dspck_astio msub, 0xf0000000, 0x00000001, 0xddb6db6d, 0x80000001, 0xdb6db6db, 0x80000000, 0x0, 0x0 + dspck_astio msub, 0xffffff0a, 0x6e28b447, 0xffffff0a, 0x6e28b447, 0x00000000, 0x3ffffffc, 0x0, 0x0 + dspck_astio msub, 0x00000000, 0x00000000, 0xfe38e38e, 0xf71c71cb, 0xf0000007, 0xe38e38e3, 0x0, 0x0 + dspck_astio msub, 0x00000005, 0xe45a1164, 0x00000005, 0xe45560c2, 0xffffffea, 0xffffc96d, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xfffffffc, 0x7ffffffd, 0x20ef7c00, 0xff3686b6, 0xfffffc5a, 0x0, 0x0 + dspck_astio msub, 0xf0000000, 0x00000001, 0xf0000000, 0x00000001, 0xff350964, 0x00000000, 0x0, 0x0 + dspck_astio msub, 0x80000000, 0x00000006, 0x7912cf83, 0x531e45e2, 0x80000006, 0xf2259f06, 0x0, 0x0 + dspck_astio msub, 0xffffffea, 0x7ebf78ed, 0x00001d61, 0x7eb81b2d, 0xffffc512, 0x7fffffe0, 0x0, 0x0 + dspck_astio msub, 0xe0000000, 0x0000000f, 0x1fffffd0, 0x800007cf, 0x8000001f, 0x7fffffc0, 0x0, 0x0 + dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffe4, 0xc71c7233, 0x000000f5, 0x1c71c71c, 0x0, 0x0 + + writemsg "[16] Test msubu" + dspck_astio msubu, 0xffffffff, 0xfffffffe, 0xfffffffe, 0x5000006a, 0x0000001b, 0x0ffffffc, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x40000000, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x61000007, 0x60000018, 0xf8000003, 0x1ffffff8, 0x0, 0x0 + dspck_astio msubu, 0x3fffffff, 0xfffffff8, 0x4033111f, 0xff66cca1, 0xfffffffd, 0xffcceee3, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffff9, 0xfffffc18, 0xfffe1447, 0x8000003f, 0x000007ce, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000006, 0xfffff8ee, 0x000d887a, 0x00000712, 0xfffffe16, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xffffffff, 0x80000004, 0x3ffffffe, 0x00000002, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x000000ff, 0xfffffa5b, 0x01943a30, 0x000005a5, 0xffffb863, 0x0, 0x0 + dspck_astio msubu, 0x0000002d, 0x47f73d6a, 0xc000002d, 0xc7f73d6a, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000003, 0x10000005, 0x9000000a, 0xf0000001, 0xfffffff9, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0024c573, 0xd82d82d8, 0x5b2a75ce, 0xc71c71c7, 0x33333333, 0x0, 0x0 + dspck_astio msubu, 0xc0000000, 0x0000000f, 0xbffffe96, 0x0000044d, 0xfffffffd, 0x0000016a, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0x999999bb, 0x99999978, 0x66666666, 0xffffffac, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffffffdc, 0xffffffff, 0xffffffdc, 0xfffffff0, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x40000000, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0xff00aefd, 0x73c61dca, 0xff00aefd, 0x73c61dca, 0x00000000, 0x71c71c71, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x1c21e374, 0x00078a61, 0x8f65ee53, 0xffffed27, 0xfff88877, 0x0, 0x0 + dspck_astio msubu, 0x1fffffff, 0xfffffffe, 0x1fffffff, 0xfffffffe, 0x7ffffff9, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xfffffffe, 0x7ffffa63, 0xfffffffe, 0x00000b38, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xc0000000, 0xffffffff, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xfffffffa, 0x00000000, 0x0000000c, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00a864d7, 0xffffffff, 0x80a864d8, 0x7fffffff, 0x00000001, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x80f13ad3, 0xb4c73b6a, 0xff0f082b, 0xffffbcc2, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffff8a, 0xbffffc56, 0xe0000007, 0x00000086, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffffff00, 0xffffffff, 0xffffff00, 0x03428034, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x801a9902, 0x752788a0, 0xffe60a0d, 0xffff5ce0, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00006cd1, 0x5ffffffb, 0xc0006cd7, 0xe0000007, 0xb6db6db6, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffff43b, 0xc0000000, 0xfffff43a, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x014f0848, 0x0, 0x0 + dspck_astio msubu, 0xe0000000, 0x0000000f, 0xe0ff0118, 0xe718e70f, 0xff00ff00, 0xffffffe7, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x01b4db37, 0x86cce935, 0x34cc1f37, 0xf2662e88, 0x7fffff80, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00000001, 0xf4f158d0, 0xffffd3eb, 0xa50763f8, 0x0ffffff8, 0x0002c165, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xf8000004, 0x0ffffff8, 0x7fffffff, 0x0ffffff8, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000004, 0x7ff53653, 0x0015935e, 0x7fffffff, 0x0015935a, 0x0, 0x0 + dspck_astio msubu, 0x1fffffff, 0xfffffff8, 0xa0000003, 0xfffffff2, 0x7fffffff, 0xfffffffa, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7cff3c20, 0x01e07a6b, 0x0360dc5c, 0xe38e38e3, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffffff80, 0xff9efe1f, 0x86ae94ae, 0xfffffbf9, 0x006101e2, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xfeee3cb2, 0xf54e5efe, 0x80000005, 0x0223869a, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000047, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0xc0000000, 0x00000003, 0xbffffab0, 0x3fff95c8, 0x00000715, 0xc000000f, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffcd8, 0xffffffff, 0xfffffcd8, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xfffd88ef, 0x7ff623be, 0x0004ee21, 0x80000002, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xffffff14, 0x00000760, 0xfffffff8, 0x000000ec, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xb6db6db7, 0x92492492, 0x92492492, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfff78198, 0xffffffff, 0xfff78198, 0x00000000, 0xffffffd9, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x40000000, 0xffffffff, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xc0000004, 0x7ffffff8, 0x7fffffff, 0x7ffffff8, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x1acdf530, 0x7fffffff, 0x80000000, 0xca64159f, 0x0, 0x0 + dspck_astio msubu, 0x92492492, 0x49249249, 0x8bb90416, 0x437b1bfc, 0xfffcdb13, 0x0690351f, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffffd, 0x7d6343ec, 0x53978299, 0xb6db6db6, 0xb6db6db6, 0x0, 0x0 + dspck_astio msubu, 0xc0000000, 0x0000001f, 0xc0000000, 0x0000001f, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0xffea00a9, 0xf7eb41a7, 0x7fea00a9, 0x77eb41ad, 0x80000002, 0xfffffffd, 0x0, 0x0 + dspck_astio msubu, 0x0b47cc33, 0x3510a0e5, 0x0b47cbb4, 0x3510b4bd, 0xffffffd8, 0x0000007f, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xfffff680, 0x00000980, 0xcccccccc, 0x00000be0, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x0b2a79ab, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xfffd7998, 0x00000000, 0x00050cd0, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0xdb6db6db, 0x6db6db6d, 0xe8954ab2, 0x2bf0f853, 0xf2d86c2e, 0xfffffffb, 0x0, 0x0 + dspck_astio msubu, 0x1fffffff, 0xfffffff0, 0x1ffffe6b, 0x0000031a, 0x0000032a, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x3fffffe0, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x0000002c, 0x8355afca, 0xecb3afa1, 0x32a2bafe, 0xfffffc14, 0x134c50d7, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000005, 0x80000000, 0x00000005, 0x00000000, 0x00000005, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffffe, 0x90000000, 0x5fffffff, 0x7fffffff, 0xe0000001, 0x0, 0x0 + dspck_astio msubu, 0x0000002e, 0x8910ff07, 0x3e88c452, 0x32ed3447, 0xf8bddf40, 0xc71c71c7, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fff8000, 0x807fff7f, 0x0000ffff, 0x7fffff80, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xe0000003, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0000000f, 0x00000000, 0x0000000f, 0x3ffffffc, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00003c56, 0x66ba1b00, 0xfffeb6c9, 0xe4bbb236, 0x03f623ee, 0x00625583, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xfffffffa, 0x05b47cf7, 0xfffffffa, 0x80000000, 0xf4970610, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x03fffffe, 0x7fffffff, 0xf8000003, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffffff9e, 0xffffffff, 0xffffff9e, 0x00000000, 0x80000001, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7d2dc9b2, 0x85a46c9a, 0x7fffffff, 0x05a46c9b, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xf9d26b9a, 0xffffffff, 0xf9d26b9a, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000021, 0x00000000, 0x00000021, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00000002, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0002eabb, 0x00000000, 0x0002eabb, 0x0000052b, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x78787878, 0x7fffffff, 0x80000000, 0x0f0f0f0f, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0000006a, 0x00000000, 0x0000006a, 0x00000000, 0x020d49cd, 0x0, 0x0 + dspck_astio msubu, 0x00000007, 0xe3d2235c, 0x80037b0a, 0x63cb2d59, 0x7fffffff, 0xfff909fd, 0x0, 0x0 + dspck_astio msubu, 0xf0000000, 0x00000007, 0x7000000d, 0xffffffed, 0x7fffffff, 0xffffffe6, 0x0, 0x0 + dspck_astio msubu, 0xf8fd8899, 0x17f7689f, 0x790b6de2, 0x17db9e0f, 0x7fffffff, 0xffe43570, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffe0, 0x7fffffef, 0x5fffff5b, 0xe0000007, 0x00000013, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0000003f, 0x00000000, 0x0000003f, 0xfffc0247, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x037abdc8, 0xffffffce, 0x037b157a, 0x00000032, 0xfffffe3f, 0x0, 0x0 + dspck_astio msubu, 0xffffffa7, 0xc03cb715, 0xffffffa7, 0xc03cb715, 0x7ffffffb, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x49249249, 0x80000000, 0x6db6db6d, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x0000dfb5, 0x3c0a7bea, 0xc000df95, 0xbc0a7bea, 0x80000000, 0x8000003f, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffffffff, 0x80008be1, 0x7ffee83e, 0xfffee83f, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x1c825747, 0x80000004, 0x1c825741, 0xfffffffe, 0x7ffffffd, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffb021, 0x8009fbcf, 0x7ffffff0, 0x00009fbd, 0x0, 0x0 + dspck_astio msubu, 0xedef3c52, 0x66e53cae, 0xedef3c52, 0x66e53cae, 0xfffffaad, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xcccccccc, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0xf1c71c73, 0xaaaaaaa9, 0xfffffffd, 0x8e38e38e, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffbad6, 0x00008a54, 0x00008a54, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x0fffffff, 0xfffffffe, 0x0fffffff, 0xfffffff5, 0x00000003, 0x00000003, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000002, 0xffffffff, 0xffffff29, 0x00000007, 0x0000001f, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffc37c, 0xfff8e8a6, 0x8000000f, 0x00007906, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000001, 0xbfffffff, 0x00000004, 0x80000003, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0xfffe15e3, 0x7cbb8090, 0xfffe15e3, 0x7cbb8090, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xffffff87, 0x25a94cb1, 0x0000007f, 0xf39be531, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xffff540a, 0x1f38cb1c, 0x00759396, 0x01766916, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xfffffffe, 0x7fffffff, 0xfffffffe, 0x8000001f, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfa217d54, 0xc0000000, 0xfa217d53, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xf419bc42, 0xffffffff, 0xf419bc42, 0x00000000, 0x000002df, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000007, 0x7ffffff2, 0x00000025, 0x8000000f, 0xfffffffe, 0x0, 0x0 + dspck_astio msubu, 0xfbb0eec1, 0x328b488a, 0xfbb0ee7d, 0xb28b488a, 0x00000087, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0x800001c8, 0x80000000, 0xfffffc6f, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x1fffffff, 0xfffffff8, 0x1fffffff, 0xfffffff8, 0xf0f0f0f0, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00008301, 0xc0000011, 0x80008285, 0x3ffffffe, 0xffffffc2, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0000003f, 0x00000000, 0x0000003f, 0xfffffa2e, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffc0, 0x38e38e38, 0xffffffc0, 0x80000000, 0x8e38e38e, 0x0, 0x0 + dspck_astio msubu, 0x0000ffff, 0x0000ffff, 0xfc010000, 0x0800fffd, 0x07fffffe, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffffb, 0xffffffff, 0xfffffffb, 0x00000000, 0x00000291, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00001e54, 0xffffef77, 0x1b663fd4, 0x0072a780, 0x0024eb33, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xffe661c3, 0x00ccf1e8, 0x00199e3d, 0xfffffff8, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x7ffffffa, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xf684bda1, 0x5ed097b4, 0x1c71c71c, 0x55555555, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0xfffffffc, 0x00000018, 0x80000006, 0xfffffffc, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0000000f, 0xfffa81d7, 0x800afc60, 0x7fffffff, 0x000afc51, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0x9ffffff0, 0x80000000, 0xc000001f, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffffff, 0x0000516f, 0x00000001, 0xffffae91, 0x0, 0x0 + dspck_astio msubu, 0x000000f8, 0x56399121, 0xfe526437, 0x2d07f221, 0x3fffffe0, 0x06b67308, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00163269, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffff815, 0x0000002d, 0x0000002d, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x40000000, 0x7fffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0000000b, 0xe6666665, 0x199999a6, 0x80000007, 0x33333333, 0x0, 0x0 + dspck_astio msubu, 0xf0000000, 0x00000001, 0xf0000000, 0x00000001, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0eb04dcd, 0x80000003, 0x0eb04dcd, 0xfffffffa, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0x9ebb1b6a, 0x800007f5, 0x1ebb0b81, 0x7fffffff, 0xfffff017, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000007, 0xfc4309df, 0x9439d5d5, 0xfca63823, 0x03c9a726, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffffffc5, 0xc0000000, 0x7fffffc5, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0xfffffffe, 0x61915789, 0xfffffffd, 0x94c48abd, 0xcccccccc, 0x00000001, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0000007f, 0xc0000001, 0x0000007e, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0x80000004, 0x00000000, 0xfffffff8, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xf8000001, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x03ffffff, 0xfffffffe, 0x03fffee9, 0x00000115, 0x00000117, 0xffffffff, 0x0, 0x0 + dspck_astio msubu, 0xf8000000, 0x00000001, 0x7800052a, 0x00000001, 0x80000000, 0xfffff5ac, 0x0, 0x0 + dspck_astio msubu, 0x3fffffff, 0xfffffffc, 0x3fffffff, 0xfffffffc, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0000007f, 0xffafa9bf, 0x4dec9e1f, 0xff982958, 0x005076e4, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000003, 0xff08f708, 0xf700ff04, 0x00ff00ff, 0xf8000001, 0x0, 0x0 + dspck_astio msubu, 0x71c71c71, 0xc71c71c7, 0xf9c71c54, 0x371c71a8, 0xf0000001, 0x8000001f, 0x0, 0x0 + dspck_astio msubu, 0xfffff80f, 0x720bafb1, 0xbffff7ff, 0xf20bafb1, 0x80000000, 0x8000001f, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffffe, 0xffffffea, 0x80000029, 0x7fffffff, 0x0000002b, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x5b6db6db, 0xc9249249, 0x7fffffff, 0x49249249, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00004c2b, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffff0, 0xbfffffff, 0xfffffff0, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffe88, 0xff807f80, 0x80feff87, 0x00ff00ff, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x69fd40e5, 0x02bf3100, 0x2c057e62, 0x7fffff80, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x40000000, 0xfffffffe, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x3fffffff, 0xffffffff, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x40000000, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0xffff7e92, 0xa1fd60f7, 0xffff7e92, 0xa1fd60f7, 0xfffffd0e, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x0fffffff, 0xfffffff8, 0x901ded6e, 0xfffffff8, 0xffc42522, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xf0000008, 0x1ffffff0, 0x7fffffff, 0x1ffffff0, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000007, 0x80000000, 0x00000007, 0x00000000, 0xc0000007, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000005, 0x00000000, 0x00000005, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffffff00, 0x82d2f0f4, 0xfa5a1d18, 0x7fffffff, 0xfa5a1e18, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffffffe0, 0xffffffff, 0xffffffe0, 0x00000000, 0xc0000003, 0x0, 0x0 + dspck_astio msubu, 0x0000ffff, 0x0000ffff, 0x3c00fff9, 0xc000fff6, 0xe0000003, 0xe0000003, 0x0, 0x0 + dspck_astio msubu, 0x1fffffff, 0xfffffff8, 0x1e000001, 0x03fffff6, 0x7fffffff, 0x03fffffe, 0x0, 0x0 + dspck_astio msubu, 0x07ffffff, 0xfffffffc, 0x0d10b78f, 0x84179a4c, 0xfaef7446, 0xffffd348, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x7ffda82e, 0xaf39f01f, 0x00026b1b, 0xf80644b3, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x1c26803b, 0xfffffff5, 0xe342f214, 0x00000017, 0x71c71c71, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffd1d, 0x00087aa1, 0x52b385fb, 0xffff4463, 0xfff840f6, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00062960, 0x142d3efc, 0x00062783, 0x5f5768c0, 0x0e0fa864, 0x000021e7, 0x0, 0x0 + dspck_astio msubu, 0x2dc9effb, 0x5078e410, 0xedc9effb, 0xd078e410, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x24924924, 0x92492492, 0xa49670c7, 0x12492492, 0x80000000, 0xfff7b0bb, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffffff00, 0xffffb5d7, 0xffffff00, 0x00009450, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x40000000, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x01de74e5, 0xffffff3d, 0x01de75a8, 0xffffffff, 0x000000c3, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffff9, 0xc0000034, 0xbffffe63, 0xffffff35, 0x3ffffffe, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000006, 0x80000000, 0x00000006, 0x00000000, 0x0040f4c3, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffa1f46, 0x00982f95, 0xa16156d4, 0xffffcb29, 0xff680522, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x00000001, 0x7fffffff, 0x7fffffff, 0xffffffff, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffc8ba9c, 0xffffffff, 0xffc8ba9c, 0xffffff80, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0xf8000000, 0x00000003, 0xf7ff872e, 0x48123473, 0x00afde54, 0x00afde54, 0x0, 0x0 + dspck_astio msubu, 0x1fffffff, 0xfffffff8, 0xdffffffe, 0xfffffffb, 0x80000003, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000001, 0x7fffe3d7, 0x00070a41, 0xffffffc0, 0x00001c29, 0x0, 0x0 + dspck_astio msubu, 0xfffe2dd6, 0xf11a0080, 0xffc086f1, 0xf11a0080, 0x007b4dca, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffffff27, 0xffffffff, 0xffffff27, 0x00000000, 0xffffff80, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffcee797, 0x01022826, 0xd8f29997, 0xfffcd5b2, 0xff00ff00, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x60000009, 0x3fffffaf, 0x3ffffff0, 0x7ffffffb, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000001, 0xc0000001, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x7ffffffb, 0x00000140, 0x00000005, 0xffffffc0, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xfffffff8, 0x7fffffe0, 0x80000037, 0x7fffffff, 0x0000003f, 0x0, 0x0 + dspck_astio msubu, 0x00001fa6, 0x773631a4, 0xe0001fb7, 0x77363124, 0xfffffff8, 0x1ffffff0, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x8012ee16, 0x11d80000, 0xffee11d8, 0xffff0000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xc0000002, 0x80000000, 0x80000000, 0x7ffffffb, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffffff, 0xfcb57eb7, 0x00000003, 0x0118d5c3, 0x0, 0x0 + dspck_astio msubu, 0x00000003, 0x351ff10a, 0x00000003, 0x351ff10a, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00001365, 0xffffffba, 0x66667a11, 0x66666666, 0x000000ae, 0x0, 0x0 + dspck_astio msubu, 0x000004b1, 0x69983cd9, 0xe00004b5, 0x69983cd9, 0x3ffffff8, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0000036e, 0x8005a241, 0xffbc689e, 0xfff4bb88, 0x7ffffffa, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xfffffffe, 0x00000000, 0x00000004, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x7ffffff1, 0x00000780, 0x00000078, 0x1ffffff0, 0x0, 0x0 + dspck_astio msubu, 0xc0000000, 0x00000001, 0xbff9dd5f, 0x57ed0020, 0x0006554b, 0xf8000003, 0x0, 0x0 + dspck_astio msubu, 0xfc000000, 0x00000001, 0xfc000000, 0x00000001, 0x00000000, 0x1c71c71c, 0x0, 0x0 + dspck_astio msubu, 0x3fffffff, 0xfffffff8, 0x801f172c, 0x407c5cb5, 0xc0000003, 0xffd68bc1, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffffff, 0xfffd8b22, 0x00000766, 0x00000055, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffffff, 0xff67190d, 0x0000001f, 0x0004eead, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffda51, 0x1ffd7a01, 0x00002b11, 0xe000000f, 0x0, 0x0 + dspck_astio msubu, 0xfd5d4c43, 0xa13b6134, 0xfd5d4c37, 0xa13b60d4, 0x80000004, 0x00000018, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xffffffff, 0xffff1d1f, 0x000000f1, 0x000000f1, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000001, 0xfffb94e3, 0x80000001, 0x80000000, 0x0008d639, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffff0, 0xffffffe2, 0x0000002c, 0x7fffffff, 0x0000003c, 0x0, 0x0 + dspck_astio msubu, 0x00070e03, 0x97f7a85b, 0x00070e03, 0x97f7a85b, 0x00000000, 0xfffffff2, 0x0, 0x0 + dspck_astio msubu, 0xf8000000, 0x00000001, 0xf7ffff44, 0x80000178, 0x00000177, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x0fffffff, 0xfffffff8, 0x0fffffff, 0xfffffff8, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x011306b6, 0xfffffff9, 0x011307dc, 0xffffffd6, 0x00000007, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffb, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0xf8000000, 0x00000003, 0xb8000010, 0x7fffffe3, 0x7fffffff, 0x7fffffe0, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffffff, 0x7fffff81, 0x8000007f, 0x00000001, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x8d897496, 0xbffffffe, 0x0d89749c, 0x7fffffff, 0x80000006, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffffffe4, 0xff4bf0eb, 0xdf3237cd, 0x00cdc817, 0xe0000001, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0x0000e84e, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xffffffec, 0xc0000000, 0x7fffffec, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0xe0000000, 0x0000000f, 0xa0000000, 0x0000000f, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0xfc000000, 0x00000001, 0xfb3ab669, 0xa8bb517e, 0xffff27bf, 0x00c54a3d, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfc2218ff, 0xffffd159, 0x7c22764c, 0x00005d4d, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xfffffff0, 0x00000000, 0x000004f5, 0x0, 0x0 + dspck_astio msubu, 0xffefbf40, 0x178f5a0d, 0xffefbf40, 0x178f5a0d, 0x00000000, 0x0007af70, 0x0, 0x0 + dspck_astio msubu, 0xffffff8e, 0x6d14471f, 0x0000b5d1, 0x6d027d05, 0xffffffe7, 0xffff49d6, 0x0, 0x0 + dspck_astio msubu, 0x0fffffff, 0xfffffffc, 0x0fffffff, 0xfffffffc, 0x00000000, 0x7ffffffa, 0x0, 0x0 + dspck_astio msubu, 0x55555555, 0x55555555, 0xd55eecdd, 0xd089b115, 0x7fffffc0, 0xffecd16f, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000001, 0x0de281a2, 0x80000001, 0xe43afcbb, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0xf0000000, 0x00000003, 0xf0000000, 0x00000003, 0x00000000, 0xffff0000, 0x0, 0x0 + dspck_astio msubu, 0xdb6db6db, 0x6db6db6d, 0xdb6db6db, 0x6db6db6d, 0x00000000, 0xfffc600b, 0x0, 0x0 + dspck_astio msubu, 0x71c71c71, 0xc71c71c7, 0x71c715e5, 0x578ae7e5, 0x068c761e, 0x0000ffff, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0xfffff29a, 0x9fff9bfa, 0xf0000007, 0x00000e4a, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0x029e7524, 0x48ac0b06, 0xfd618b21, 0xffffffba, 0x0, 0x0 + dspck_astio msubu, 0xc0000000, 0x0000000f, 0xc0000000, 0x0000000f, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x00000003, 0xfffffff9, 0xfffffffa, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffee3b, 0x00004713, 0xfffffffc, 0x000011c5, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x40000000, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x0000045a, 0xedef9a30, 0xc0000457, 0xedef9a30, 0x80000006, 0x80000000, 0x0, 0x0 + dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7d39892c, 0x058ceda7, 0x7fffffff, 0x058ceda8, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xff9aa03c, 0xc0000000, 0x7f9aa03c, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0xc71c71c7, 0x1c71c71c, 0xae413bc4, 0x32fef829, 0x18db3689, 0xfffffa9b, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000009, 0x00000000, 0x00000009, 0x000000c1, 0x00000000, 0x0, 0x0 + dspck_astio msubu, 0xffffffff, 0xfffffff0, 0xc0000000, 0x7ffffff0, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x0000003f, 0xc0000000, 0x8000003f, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio msubu, 0x80000000, 0x00000000, 0x00000832, 0x800062a6, 0xffffef8f, 0x80000006, 0x0, 0x0 + dspck_astio msubu, 0x00000000, 0x00000000, 0x000008d4, 0xfff85422, 0xffffff06, 0xfffff825, 0x0, 0x0 + dspck_astio msubu, 0x00447ca7, 0xb87a4605, 0xc0447ca8, 0x387a4605, 0x80000000, 0x7fffffff, 0x0, 0x0 + + writemsg "[17] Test mul.ph" + dspck_dstio mul.ph, 0x00007f5b, 0x000000a5, 0x00007fff, 0x0, 0x00200000 + dspck_dstio mul.ph, 0x00008001, 0x0000ffff, 0x0f0f7fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x3ff90000, 0xffff7fff, 0xc0070000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00007fff, 0x00040001, 0x00007fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00008000, 0x80008000, 0x800000f5, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x7fc1fb98, 0xffff7fff, 0x803f0468, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0xffe00000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000ff60, 0x80000014, 0x0000fff8, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xa9400000, 0xff5b0000, 0x7fc00000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x001028e0, 0x7fff00b9, 0xfff03fe0, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x149c0000, 0xfe340000, 0x00837fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x9ff10000, 0x7fff3fc0, 0xe00f8000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfe80ffc0, 0x7fc0ffc0, 0x80060001, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00108001, 0x7fffffff, 0xfff07fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x7fff000e, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x00000003, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x8000a010, 0x800003fe, 0x083d1ff8, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x8b100001, 0xc71c7fff, 0xc71c7fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x000b0fae, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000016e, 0x8000ffc3, 0x000efffa, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xdda40000, 0x1ffc7fff, 0x00970000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x1e6e0000, 0xfffbf5ae, 0xf9ea8000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000df90, 0x00000ed4, 0x00000ed4, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00040000, 0x80000007, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x7ffecccc, 0x80008000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x7fff0000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xa00c7fe7, 0xfffafffb, 0x0ffe8005, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfffe0000, 0x00010000, 0xfffe0000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x7ffffffe, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00199a8d, 0x0005ffd3, 0x0005e01f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00007ffd, 0xf0f07fff, 0x00000003, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00007fe1, 0x80007fff, 0x0000001f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000ffa0, 0xfc12fffc, 0x00000018, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x5cc0c390, 0x3fc007fc, 0x038dc71c, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00008000, 0x00008000, 0x00003333, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x1d560000, 0xffff8000, 0xe2aafffe, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfd917fdb, 0xffa70025, 0x00077fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x018c7808, 0xff9d00ff, 0xfffc7ff8, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000fe56, 0x000001aa, 0xf2ec7fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x63348000, 0x33338000, 0x0ffc7fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x000e0000, 0x80070efd, 0x00020000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0xc003001f, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0c780000, 0xf3880000, 0x7fff0a2d, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xffe06db4, 0x7ff00005, 0x80024924, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00020000, 0x7fff8000, 0xfffe0000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00006d1c, 0x0000010f, 0x7fff4924, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x8003f002, 0xfffd0ffe, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0xffd61dc4, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x08ae0000, 0xf752b6db, 0x7fff0000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00008000, 0x00000069, 0x09bc8000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80008000, 0x800029b1, 0x33338000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x01007004, 0x7fc007fe, 0x03fc3ffe, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80000000, 0xf3290000, 0x8000ff07, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x3ff64008, 0x00051ffe, 0x3ffe1ffc, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x7fffe200, 0x7ffffe20, 0x00010010, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x6feb8000, 0xfff9ffff, 0xf0038000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xff8007e7, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xd1be042a, 0xfe82ffff, 0x001ffbd6, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x7ff70000, 0xfffd0000, 0x8003c007, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00057fff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00007ff2, 0x00008002, 0x7ffafff9, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00400000, 0x7fff0000, 0xffc01967, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80020000, 0x7ffa0003, 0x55550000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xfba27ffc, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x8000fc00, 0x0003ff00, 0x80000004, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xc9ae0e0e, 0xed290002, 0x03fe0707, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x80000000, 0x00008000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80006170, 0x7ffff75d, 0x80000030, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x33340000, 0x7ffe8000, 0x66660024, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x001affff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80008007, 0xf001fff9, 0x80007fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x6790e21f, 0x1ffc00ff, 0x061cfee1, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00008000, 0x7fff8000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x60ae0000, 0xf0030000, 0x003a8000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00009248, 0x80004924, 0x80008002, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xaa568000, 0x807ffff3, 0xaaaa8000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x55c00001, 0xffa9ffff, 0x3fc0ffff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfe900000, 0x01707ffe, 0x7fff8000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfe707fc1, 0xfe707fff, 0xe001003f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x609f0000, 0x00fffffc, 0x00610000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfe800000, 0x80060000, 0x7fc0ff00, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80001ff9, 0x8000ffff, 0x7fffe007, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000005, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xedc08000, 0x00498000, 0xffc0005d, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x3627b261, 0xf627c001, 0xc001f261, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00007f8d, 0xfda17fff, 0x00000073, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80000000, 0xffff0000, 0x80008000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80007efd, 0x80008007, 0xffc9ffdb, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x80007fe0, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x804b0000, 0x7fff8000, 0xffb50000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x86880000, 0x8e38c001, 0xe8a70000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x000083ff, 0xfffafc01, 0x00007fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x2146fede, 0x7fff0091, 0xdebafffe, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000002, 0x00007fff, 0x0000fffe, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00004009, 0x0000e003, 0x0000e003, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xff100000, 0xfff0eebe, 0x800f0000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x8000fb52, 0x8000ffff, 0x02b104ae, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0xfffb000e, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80068000, 0x80020189, 0x00038000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x8000edb8, 0x7fff7ff8, 0x80009249, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x74272ae8, 0x7fff2aa3, 0x0bd97ff8, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x05ee0000, 0x00010000, 0x05eeffe7, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xffc1b080, 0x803f009f, 0x7fffff80, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x8000e4a0, 0x7ffbb6db, 0x80003fe0, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x81c0fc28, 0xfff97fff, 0x7fc003d8, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80008005, 0x80007fff, 0x8003fffb, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00008000, 0xffff0003, 0x00008000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xe8188000, 0xffe871c7, 0x00ff8000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x5520000a, 0x0357fffe, 0x3fe0fffb, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfcb0fff4, 0x7fff0003, 0x0350fffc, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000ffc7, 0x00020039, 0x0000ffff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00003ffd, 0x0000c003, 0xfff2ffff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x1c720048, 0x7fff0018, 0xe38ec003, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000abc5, 0x8000fe95, 0xfff01c71, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00314000, 0x7ff97f80, 0x7ff97f80, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x2d9a0000, 0x0ffe8006, 0x01338000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x08000000, 0xff000329, 0xfff80000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x7fa0ffa4, 0x8003002e, 0x7fe0fffe, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x11aefed6, 0x001f7fff, 0x0092012a, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xebf37e20, 0xfffde00f, 0x06af7fe0, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x7fdfc01c, 0x0021f007, 0x7fff0004, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xffa050a0, 0x00061fe0, 0xfff0007b, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00008000, 0x7fff8000, 0x0000f803, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xb6d50000, 0x000f000b, 0xb6db0000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xffe07fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xbff10070, 0xc00f03f9, 0x7fff3ff0, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xff6e0000, 0x7ffffcb1, 0x00920000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00008031, 0x8000c007, 0x8000c007, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xdc718000, 0x1c717fff, 0xc0018000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x06e88000, 0x0000fb00, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x7ffd0040, 0x0003ffe0, 0x7fff07fe, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x8000e9e1, 0x00091c71, 0x80001c71, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xf4570000, 0xfdab0000, 0x0005fff9, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80039ffa, 0xfffdf003, 0x7fff7ffe, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xffae7a4f, 0x00521abd, 0xfffffffb, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x40e0b95d, 0xfff9ff95, 0x3fe000a9, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000004, 0x00000004, 0xf0f00001, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000096, 0x0000ffe2, 0xff80fffb, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000f61, 0x7fff807f, 0x0000801f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x0000fff0, 0xfda48000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfe440004, 0xfffeffff, 0x00defffc, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0006139d, 0xffff04c3, 0xfffa801f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x3ff00000, 0x00000f3d, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00008000, 0xdf11fc0f, 0x00008000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00070000, 0x7ff98000, 0x7fff0002, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x7ff70000, 0x7ffd8000, 0x00030000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x38038000, 0xf8037fff, 0xc0018000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x0000f007, 0x00010000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x7fcf7ecf, 0x7ff97fff, 0x00070131, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x006c0000, 0xfffd8000, 0xffdc036c, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xd3540002, 0xe01f0002, 0xf22c0001, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x1f001485, 0xff08eed7, 0x3fe0f803, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x0ffefff8, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x43dc7fdd, 0x1f74fffb, 0x38e38007, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000c84, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x463c0000, 0x02440000, 0x801f0000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00009ff1, 0xffeb7fff, 0x0000e00f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x7ffbc004, 0x7fff0ffe, 0x00050ffe, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00007fe1, 0x00ffffff, 0x0000801f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x9ffdffb2, 0x7fff001a, 0xe003fffd, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00030052, 0xfff9ffae, 0xb6db7fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x5980de10, 0x7fc01ff0, 0x0e9ac01f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xffb20000, 0x004e007f, 0xffff0000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00004030, 0x00003ff0, 0x1af5fffd, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x800052d0, 0x8000f803, 0x7ffff0f0, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x8002800f, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80000000, 0xfffd0000, 0x80000004, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xea9e0000, 0x002e8000, 0xff890000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x7f806666, 0x1fe06666, 0x00040001, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000666c, 0x0000cccc, 0x8000fff9, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x55550000, 0x0000007f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x8004aaaa, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x8000804d, 0x80007fff, 0x7ff9ffb3, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x8000fffe, 0x8000fffe, 0xe0070001, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80800000, 0x3fc00000, 0x07fe0012, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0080d486, 0x3fe0f9ca, 0xfffc8007, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x3f460000, 0xe01fb6db, 0x7ffa0000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x7abf21bc, 0x05411ffc, 0x7fffff91, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x80008000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xf0070000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00060000, 0xfffa0000, 0x7fff06fb, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000802a, 0xfffcfff9, 0x80007ffa, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x45538000, 0x1c718000, 0xf003e007, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x80000000, 0x00f0e003, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00020309, 0xfffeffdb, 0x7fffffeb, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000ffff, 0xffc6ffff, 0x80000001, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x7fff7fff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0014fe04, 0xffecfffc, 0xffff807f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x7fff8000, 0x0000fe48, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x84448000, 0x80040001, 0x01118000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80000000, 0x8000ff24, 0xe0070000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfa6b2578, 0xffff0008, 0x059504af, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xd2b48294, 0x0a2e3ffe, 0x6db6feb6, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x63348000, 0x0ffc7fff, 0x33338000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00002110, 0x0000ffa4, 0x0000ffa4, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0xb6dbc1cc, 0x00008000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xee990000, 0xfe6b1ff8, 0x000b8000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xff802c9e, 0x0002f9b1, 0xffc01ffe, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xbf047f97, 0xf0820015, 0x2f027ffb, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000f388, 0x80000008, 0x8002fe71, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000edd7, 0x8000f007, 0x0000ffb1, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x000031c0, 0x00000039, 0x3ff03fc0, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfffaa718, 0xfffefe74, 0x0003fcfe, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00005ee1, 0x800000ff, 0x011ac01f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x80000000, 0x06805555, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xe41e0000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x0000ffdf, 0x00230000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x00000001, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x8001c925, 0x7fff7fff, 0xffffb6db, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0010cd3e, 0xfff0e00f, 0xffff00e2, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfffc0000, 0xfffc10ab, 0x00010000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x83270000, 0x010d8000, 0x80037fe0, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x1fe47ffb, 0x00720005, 0x0b827fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80030000, 0x7ffffff0, 0xfffd0000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xbebe13c1, 0xe00705dd, 0xffd20135, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x01000199, 0x7f80f803, 0xfffe3333, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x6a5071b8, 0xf0f00011, 0xff0b8e38, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0000fe30, 0x0000fff8, 0x13d2003a, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0xffc77fff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0980c036, 0x0980f33e, 0xfc010005, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80007ffb, 0x7fff8005, 0x8000ffff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00008001, 0x0000ffff, 0x7fff7fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xf003007f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfffe0099, 0x0002ffcd, 0x7ffffffd, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfffa8000, 0x7ffd8000, 0x00021e89, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0001e2c0, 0x7fffefb2, 0x7fff0060, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00108000, 0x3ffe8000, 0x7ff8ff3f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xd4fd0fff, 0xd4fdf001, 0x0001ffff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xfffbffa0, 0x80050008, 0x7ffffff4, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0xc001f83c, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x80007fff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x38e3ffa2, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x80000000, 0x80000000, 0x7fff807f, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0xe0108000, 0xfffe8000, 0x0ff87fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x8b103290, 0xc71cf934, 0xc71cf934, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x7ffff900, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x0a900001, 0x00347fff, 0x00347fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x8000fffc, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0xfc017fff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xfc110002, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00000000, 0x00008000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00008000, 0xfd7f8000, 0x00007fff, 0x00200000, 0x00200000 + dspck_dstio mul.ph, 0x00bfa4e5, 0x00bffd6f, 0x000100eb, 0x00200000, 0x00200000 + + writemsg "[18] Test mul_s.ph" + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x012a0007, 0x0, 0x00000000 + dspck_dstio mul_s.ph, 0x80000000, 0x7fff0000, 0x80068000, 0x00000000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x00000f0f, 0x00000f0f, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fffff93, 0xf989006d, 0xdb6dffff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0xc00ffd8a, 0x00061ffe, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0x0297fce4, 0xf8037fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008000, 0xf0037fff, 0x0000fffd, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xe0208000, 0xffff7fff, 0x1fe0e001, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x0000f003, 0x0000f003, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x7fc00000, 0xf0160000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x0ffcf400, 0xffc0fa7d, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x7ffff294, 0x38e30000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x8000fff8, 0x0c320001, 0x8000fff8, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0xe01f2492, 0x000b8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008000, 0x00006666, 0xffeb8006, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x00009249, 0x8e38fff7, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008000, 0xfffffedd, 0x000007fc, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x1ff86666, 0x2492f96f, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x8000fb3e, 0x8000ffd6, 0x0ffc001d, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x3fc00000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0xfff7ee64, 0xf00102aa, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x7fff7fff, 0xfffe7fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x7fc05555, 0x7ffffe96, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x0ff97fff, 0xffffffe9, 0xf007e38e, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x00e1ff80, 0xe38e0000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000440, 0x0006ffbc, 0x9999fff0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0xfffd8000, 0x80007fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff153c, 0xfc67f562, 0xff5bfffe, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x1ffec001, 0x001e1ffc, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x00007fff, 0x92497fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x00013ff0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0xffcd807f, 0xfb80129a, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x7ffd05cc, 0xfea90000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00e17fff, 0x000f7fff, 0x000f7fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff807f, 0x7fff807f, 0x3fe00001, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0xfffe7fff, 0x80047fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xf8c78000, 0xf8c7801f, 0x00010ffe, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x7fff0000, 0x8000000e, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0xfffd0000, 0x7fffc03f, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80017fff, 0xfffff232, 0x7fff8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x7ffe7fff, 0xff800010, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008000, 0x7fff0003, 0x00008000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xe91a0000, 0xfc2f0000, 0x0006800f, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x00630000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x1ff8001f, 0x7fff7ff0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x7fff8000, 0x7fff8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x80000000, 0xf9400000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008001, 0x088bffff, 0xfb127fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff2888, 0x00be0004, 0x7fff0a22, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x00000004, 0x800738e3, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x800f0000, 0x0ffc029d, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0x7ff0aaaa, 0xf0010002, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000004, 0x00ca0004, 0xf0030001, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x8000f123, 0xf0017fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0xfffb8000, 0x7fff7fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0xe4ee7fff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0004, 0xff41fffe, 0xff41fffe, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x7fff8000, 0x00008000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x7ffac00f, 0x80078000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x1ff0e11b, 0x80058000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x8000b6db, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x1ff8fffc, 0x71c77f80, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0xff8f0000, 0x800f0000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0x80007fff, 0x3ff0fc01, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x1fe0000f, 0x803f7fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x013dffe0, 0x7ffafa98, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xf8227fff, 0x00138000, 0xff968000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7ffffaa0, 0x8000fffc, 0xffc60158, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008000, 0x80077fe0, 0x0000ff53, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008000, 0x00000004, 0x00798000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x80007fff, 0x7ffb3fc0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x800400ff, 0x7ffe7f80, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0x03ce0180, 0xcccc8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0x800f02e4, 0x7fff8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xff607ffb, 0x000a8005, 0xfff0ffff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x7fff0000, 0x71c77ffe, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x7fff0000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x02258000, 0x00018000, 0x02250001, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0xe007024a, 0xe38e0ce0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0xf803007f, 0xf0f03ff0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x00008000, 0xfd898007, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x00007ffd, 0x00007ff8, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x6666009f, 0x800004de, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0xf7d4febe, 0xfe107fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fffe2cc, 0x7ffffef5, 0x7fff001c, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xfe500000, 0x00010000, 0xfe507fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x80070000, 0xfb560000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x80006db6, 0x00046666, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x80000000, 0x80007fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0xffeb0000, 0x92497fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0xff003333, 0x7fff7fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x7fff0000, 0x80000002, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x7fff0000, 0xfff37fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0xffeccccc, 0x8000b6db, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0xc00f7fff, 0xffe18000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x8000fa18, 0x7fff00bd, 0x8000fff8, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x7fff06eb, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x99990000, 0x0005db6d, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x7ff98000, 0xfffd8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0xf9a37ffb, 0x00000004, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x00220000, 0xdb6d7ffe, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00107fff, 0x0004f803, 0x0004f803, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x00050ff8, 0x1c710ff8, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x8000f75a, 0x9249ffff, 0x1c7108a6, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x7fff00c2, 0x7fff3ff0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xfe300000, 0xfffc8000, 0x00740000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0xfffb0000, 0x7fff7fc0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008000, 0xfffb8000, 0x00007fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x80006db6, 0x00001ff0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008004, 0x00000001, 0x80008004, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x00d10004, 0x02e17fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xccfccccc, 0xfffccccc, 0x0cc10001, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xfe300000, 0x003a0000, 0xfff8ff00, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0xffab0000, 0x924900ff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0x80008000, 0x7fff7fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0xe00f0000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xf0040000, 0x0ffc0006, 0xffff0000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x00007fff, 0x49241ff8, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x007f001f, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x0000fd45, 0x0000fddc, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0xfffafffd, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x800005f4, 0x7fff007f, 0xfe6d000c, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xfa210000, 0x01f58000, 0xfffd0000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x1ff87fff, 0x00d08000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x0000ffee, 0x0000fffd, 0xf0170006, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00058000, 0xffff3ffe, 0xfffb8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fffffd0, 0x803f000c, 0xffb2fffc, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x7fffffe0, 0x7ffc8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0xfff100ff, 0x0fc88000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x7fff0057, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008000, 0x3ff87fff, 0x0000ffc0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x8000fff8, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0xe38e00b0, 0x8007f0f0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x8000f44f, 0x7fff0000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xff608000, 0xffe08000, 0x00057fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x3a708000, 0x00028000, 0x1d380ffe, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x800f8000, 0x001ff001, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x8000016b, 0x014c0003, 0x80030079, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x8000f0f0, 0x24928007, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0xf00305e9, 0xc00ff003, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0xff007fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xaaaa0031, 0x00010007, 0xaaaa0007, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x8000fff8, 0xffff8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x1ffe001c, 0x7fffc00f, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x1b0f0000, 0x7fff8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000100, 0x0000fff0, 0x0000fff0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00097fff, 0x00032492, 0x00032492, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0x7fffb6db, 0xfff07fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x8000fe1c, 0xe00f0016, 0x6666ffea, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fffffe7, 0x80050005, 0xfdbefffb, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x02a47fff, 0x001a8000, 0x001a8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x80028000, 0x801f0000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x80000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0x7fffc01f, 0xfbc57fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x0000026f, 0x7fff7fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x0000d300, 0x7fffffe0, 0x00000168, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x99997fff, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0xfcf67fe0, 0xfeb27fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x80007fff, 0xfffcfff8, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0xfc0afffc, 0xe01f0000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008000, 0xfc9adb6d, 0x00007fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x7fff0000, 0xffe08000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0xfffd0000, 0x00003fe0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x7fff0000, 0x0000c01f, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0xffe07fff, 0x30a7fffe, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7ffff89d, 0x8000ffc3, 0xe3ef001f, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x80047fff, 0xff260000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x7fff0000, 0x0ffe00cb, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008000, 0x0000003f, 0x0df48000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x032a0000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x0c448000, 0x002ff0f0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0xff8c0018, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xa05d7fff, 0x0003800f, 0xe01fece2, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fffc040, 0x1fe0ffff, 0x7ffc3fc0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0xf8108000, 0xf003c007, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x7ffffffd, 0x001c2c39, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x7fff7fff, 0x0048803f, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x7fff0000, 0xfffa8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xfff87fff, 0xfffcc01f, 0x0002801f, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0xffd8263d, 0xf0013ffc, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0xaaaa003f, 0x3fc00000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0xfff6c01f, 0xc01f0000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x0043fbb6, 0x03cc7fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0xf0f0000c, 0x7fff7fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x1e960000, 0xf5ce0000, 0xfffd8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x002a8000, 0x7ffffcf6, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x7fffc00f, 0x8000fffd, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0x800000b1, 0x0ffe8003, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x8000007f, 0x1ff30000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff807f, 0x7ff0807f, 0x00170001, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0xfff10000, 0xf0017fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x00000ff8, 0xfffe7fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0xc0f27fff, 0xffd7803f, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x7fff3333, 0x7fff3333, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x7fff0087, 0x00cc3fc0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x7fffe003, 0x7fff0075, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0x03fe8e38, 0x80007fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x00001ff0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xfea07fff, 0xfffc9999, 0x0058807f, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00009249, 0xffc00000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00008000, 0x00040000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x80008000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008000, 0x02efdb6d, 0x00007fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x80008000, 0xfc95c75c, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x80000000, 0x00008000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00008000, 0x7fff9249, 0x000000ff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xf99a7fff, 0xffd90004, 0x002a7fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00e17fff, 0x000f3333, 0x000f3333, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0x0000fc32, 0x8007f801, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x6db60000, 0x00020000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7ffffed9, 0xff76ffff, 0x80000127, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x0c8a7fff, 0x00037fff, 0x042e0447, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x8005f803, 0xffe28000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x0303800f, 0x7fff7fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x1e2001b0, 0xfffeff94, 0xf0f0fffc, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x000f5555, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x0000ffc3, 0x01c70000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0x003f8000, 0xe38e0006, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00007fff, 0xdb6d7fff, 0x00007fff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x2492e003, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x8000f001, 0x7fff9249, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0xf0038000, 0xe01f7ffc, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00457fff, 0xfffd8000, 0xffe9ffff, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x8000fb8e, 0x7fff8000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x7fffffda, 0x1ffce38e, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00070000, 0xffff0006, 0xfff90000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x8000f002, 0x8000ffff, 0x00150ffe, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x00000006, 0x00000001, 0xf0010006, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0xf0db7fff, 0x7ffffff0, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x7fff8004, 0xfffb0000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0000, 0x3fc0ffd5, 0x7fff0000, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80007fff, 0x807f7fff, 0x00090005, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80008000, 0x00b66666, 0xf003fffa, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x8000d654, 0x8000007f, 0x7fffffac, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0xffcf7fff, 0xec7d8003, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x80001df2, 0xc71cff53, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0xff788000, 0xfffc007f, 0x0022f7fb, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x80000000, 0x3fe00000, 0x80000029, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff8000, 0x7fff000a, 0x003db6db, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff0024, 0x8000fffa, 0x8000fffa, 0x00200000, 0x00200000 + dspck_dstio mul_s.ph, 0x7fff7fff, 0x80007fff, 0xff9f0001, 0x00200000, 0x00200000 + + writemsg "[19] Test mulq_rs.w" + dspck_dstio mulq_rs.w, 0x00000151, 0xfffffeaf, 0x80000000, 0x0, 0x00000000 + dspck_dstio mulq_rs.w, 0x0017fc8f, 0xe0000007, 0xffa00dc2, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0xfe9ce071, 0xc0000001, 0x02c63f1f, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000000, 0xffffffc0, 0x0003065a, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x000a50e9, 0x8000001f, 0xfff5af17, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000006, 0x7fffffff, 0x00000006, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0xff0bda44, 0xff0bda44, 0x7fffffc0, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000001, 0x0000003a, 0x026b670d, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000001, 0xfffffcec, 0xffe29d3a, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0xffffffde, 0x10d559b5, 0xffffff00, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000046, 0x00000046, 0x7fffffff, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x0000ffff, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000080, 0xffffff80, 0x80000006, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000040, 0x7fffffff, 0x00000040, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000000, 0x80000005, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x7ffffff9, 0x7ffffffa, 0x7fffffff, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x7ffffffd, 0x7fffffff, 0x7ffffffe, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000056, 0x7fffff80, 0x00000056, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000234, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x006bfe19, 0x24924924, 0x0179f958, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x12492491, 0x3ffffffe, 0x24924924, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000096, 0xffa6fc9a, 0xffff2867, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x00000006, 0x0f0f0f0f, 0x00000035, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0xffffffe1, 0x7fffffff, 0xffffffe1, 0x00000000, 0x00000000 + dspck_dstio mulq_rs.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00000000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xfffff429, 0xfffff429, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x01000000, 0x0ffffffc, 0x07fffffe, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000001, 0xffffffff, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x66666665, 0x66666666, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x0000001b, 0x80000007, 0xffffffe5, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x80000005, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x3fffffe0, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffffad0b, 0x80000007, 0x000052f5, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xffff0000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000027, 0x80000006, 0xffffffd9, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x07fffffc, 0x7fffffff, 0x07fffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00078e5a, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00a1c74b, 0xffffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x7ffffff4, 0x7ffffffb, 0x7ffffff9, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffffadf4, 0xff3e7557, 0x00364356, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x000000df, 0xe000000f, 0xfffffc82, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000001, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000128, 0x7fffffff, 0x00000128, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x01abeed0, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffff0001, 0x80000000, 0x0000ffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xff58cf32, 0xfffffff8, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000001, 0xff00ff00, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x000b829a, 0x7fffffff, 0x000b829a, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x1ffffff0, 0x7fffffff, 0x1ffffff0, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x80000015, 0x7ffffff0, 0x80000005, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xfffffff8, 0xfffffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x80000002, 0x80000001, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffe1aa82, 0x7fffffff, 0xffe1aa82, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xff9b6f67, 0xfffffffa, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000004, 0x80000000, 0xfffffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000006, 0x7fffffff, 0x00000006, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000007, 0x7ffffffb, 0x00000007, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfff013c6, 0x24924924, 0xffc84534, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffa8d35, 0x002b965b, 0xf0000007, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffe43f8, 0xff411954, 0x0129b9d1, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x8000007f, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xffffcca4, 0xfffffc33, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x7ffffffb, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x7ffffff8, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00001dad, 0xffffe01a, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffffffd, 0x00000007, 0xc0000007, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x01ffffff, 0xf0000003, 0xf0000003, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffffeff, 0x000005c4, 0xe9bfc5a9, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00001742, 0xffffe8be, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x7ffffffb, 0x80000000, 0x80000005, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x1ffffffe, 0x1ffffffe, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xfffffffc, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0xffffff97, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffff6e13, 0x000091ed, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000005, 0xb6db6db6, 0xfffffff8, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000038, 0x7fffffff, 0x00000038, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xf0000003, 0x7fffffff, 0xf0000003, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xf0f0f0f0, 0xf0f0f0f0, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000aee, 0xfffff512, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xf0000002, 0x0ffffffe, 0x80000001, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x000000ff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x0000001c, 0xffffffc0, 0xc71a53fe, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x38e38e1c, 0x71c71c71, 0x3fffffe0, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x80000005, 0x7fffffff, 0x80000004, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x8e38e38f, 0x71c71c71, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0xffff3933, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffff5da6, 0x0000a25a, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000fd3, 0x7fffffff, 0x00000fd3, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffffb9c, 0xffffdcdf, 0x0ffffff8, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x015c1cc7, 0xfea3e339, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0xaaaaaaaa, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x054b7975, 0x00000001, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000003, 0x7fffffff, 0x00000003, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x011434d5, 0x49249249, 0x01e35c75, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00000007, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x7fffffc0, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x353dcce8, 0x7fffffff, 0x353dcce8, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x80000005, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xe683a401, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffffffc, 0xffffffe0, 0x0ed9ff25, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xfffffff9, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x8e38e38e, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xf8000002, 0x07fffffe, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffffffd8, 0xf0000007, 0x00000140, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x0000000f, 0xff67e80c, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x80000001, 0x80000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffde962, 0x0ffffffe, 0xffef4b11, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xffffffff, 0xffffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x80000001, 0x80000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00574a38, 0x7fffffff, 0x00574a38, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffffff1d, 0x000000ff, 0x8e38e38e, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xffed1970, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xf0000009, 0xe0000003, 0x3fffffe0, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xff807f81, 0x00ff00ff, 0xc0000003, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0xf8000001, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffff2ec, 0xffffcbb0, 0x1ffffff8, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000003, 0x00000007, 0x38e38e38, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffffffcb, 0x80000000, 0x00000035, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x7ffffffa, 0x7ffffffd, 0x7ffffffd, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000001, 0xb6db6db6, 0xfffffffe, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x12f684bd, 0x55555555, 0x1c71c71c, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x1249248d, 0x3ffffff0, 0x24924924, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xffffffff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xff81f884, 0x013b12b5, 0xcccccccc, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x0000006f, 0x00000d3b, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x023b15c9, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xfffffffa, 0x0014e498, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000001, 0xf0000007, 0xfffffffa, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x7ffffffd, 0x80000000, 0x80000003, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xfffffc38, 0xfffffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffffff36, 0x7fffff80, 0xffffff36, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00ead470, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000006, 0x80000000, 0xfffffffa, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000066, 0x80000000, 0xffffff9a, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000001, 0x0ffffff8, 0x00000006, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffffffc, 0x1ffffff0, 0xfffffff0, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xfffffbe1, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00034357, 0xfffcbca9, 0x8000000f, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x5e0a72ef, 0x6db6db6d, 0x6db6db6d, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x80000001, 0x80000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xffffffc0, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffffff71, 0xfffff709, 0x07fffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x80000004, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00001e53, 0xffffe1ad, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xffffffff, 0x00000004, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000005, 0x003d27bc, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffffffe3, 0x0000001d, 0x80000005, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xfffffffe, 0xe0000003, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00000003, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffffec3, 0xfffffd86, 0x3ffffff0, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xf8000007, 0x3fffffe0, 0xf0000007, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfff2d687, 0x66666666, 0xffef8c29, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000002, 0x80000000, 0xfffffffe, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x7ffffff8, 0x7ffffff9, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x146725b0, 0xeb98da50, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xfff7f8d8, 0xfffffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x0000049a, 0x00001251, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffff007, 0xc000001f, 0x00001ff2, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00024b75, 0x7fffffff, 0x00024b75, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x000002ad, 0x00128096, 0x00128096, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xf1c71c72, 0x38e38e38, 0xe0000001, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x0006c160, 0x7fffffff, 0x0006c160, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xfffffff8, 0xfffffff0, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xc0000007, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x80000002, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x0ffffffe, 0x0ffffffe, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfc000002, 0x80000000, 0x03fffffe, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0xffffffe3, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x38e38e39, 0x80000000, 0xc71c71c7, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000028, 0xffffffd8, 0x80000005, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x80000001, 0x80000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x0ffffffe, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x0000000f, 0x80000001, 0xfffffff1, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffface56, 0x0005d7df, 0x8e38e38e, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x0000000a, 0x0000000f, 0x55555555, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000002, 0xfffffffe, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x80000004, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x80000004, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffffffe, 0x00000002, 0x8e38e38e, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x3fffffe1, 0xc000001f, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xfffffffa, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000007, 0x00000007, 0x7fffffe0, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00001bc5, 0x00001bc5, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x06e5c118, 0x1db69774, 0x1db69774, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00b25008, 0x80000001, 0xff4daff8, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xf8000003, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x7fffff81, 0x80000000, 0x8000007f, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000001, 0x7fffffff, 0x00000001, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffe01fe0, 0xff00ff00, 0x0ffffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000003, 0x00020e6a, 0x00009c63, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffffff0, 0x7fffffff, 0xfffffff0, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000006, 0xfffffffa, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xc0000001, 0xc0000001, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00001866, 0x00030ccb, 0x03fffffe, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x07fffffe, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffffffff, 0xffffffff, 0x66666666, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffffffff, 0x71c71c71, 0xffffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffff312, 0xffff3f7b, 0x0898d847, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xffffffa7, 0x00573bd0, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffffffe1, 0x80000000, 0x0000001f, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xffffff00, 0xffffff00, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0xfffffff9, 0xfffffff9, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000002, 0x001f3444, 0x00000683, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000001, 0xfffffffd, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffffff7, 0x7fffffff, 0xfffffff7, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0xffffe06d, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffffffe, 0x7ffffff9, 0xfffffffe, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000104, 0x00000289, 0x33333333, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000002, 0xffffff00, 0xff00ff00, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x000003d1, 0x80000000, 0xfffffc2f, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x007dd65e, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000000, 0x0003aa03, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x00000001, 0xff00ff00, 0xffffff99, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0x1c71c71d, 0x80000000, 0xe38e38e3, 0x00200000, 0x00200000 + dspck_dstio mulq_rs.w, 0xfffd5905, 0x03fffffe, 0xffab20ab, 0x00200000, 0x00200000 + + writemsg "[20] Test mulq_s.ph" + dspck_dstio mulq_s.ph, 0x99990000, 0x7ffffffa, 0x9999fb8b, 0x0, 0x00000000 + dspck_dstio mulq_s.ph, 0x00040090, 0xfda10091, 0xff0d7fff, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0xf0040000, 0x80000000, 0x0ffc0000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0xfff70000, 0x800ffffe, 0x0009ffff, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000023, 0x00000023, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0xffff0000, 0xffff0000, 0x7fff1ffc, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00007ff1, 0xfffe8000, 0xff5f800f, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x04540000, 0x7fff0000, 0x04551ff8, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x0001ffff, 0x00a1fdb7, 0x00cd0003, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0xfffa0000, 0x05800000, 0xff8b0000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0xfff80005, 0xffe00006, 0x1fe07fff, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00008003, 0x00008003, 0x7fff7fff, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00000000, 0x7fff0000, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x1fdee004, 0x1fe01ffc, 0x7ffa8000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0xfde20000, 0x043b0000, 0xc003c71c, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00001948, 0xfff338e3, 0xfff338e3, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x0000ff19, 0xfec6ff19, 0x00007fff, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x005b0000, 0x7fff0000, 0x005c0002, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0xffffc71d, 0x00048e38, 0xfb413ffe, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x55558000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x00088000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x8001fffd, 0x80000003, 0x7fff8000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00001fff, 0xfa028000, 0x0000e001, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00000000, 0x1ff838e3, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000002, 0xf0070000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00008000, 0x072f0000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0xffda0000, 0x3ffe0000, 0xffb5ff07, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0xffffff00, 0xfd6e7fff, 0x001fff00, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00551ff7, 0xaaaa1ff8, 0xff807fff, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0xf0d1096f, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x8001c02f, 0x8000801f, 0x7fff3fe0, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x8001fffd, 0x7fffffd4, 0x800007ac, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x0000ffff, 0x7fff0007, 0x0000fddb, 0x00000000, 0x00000000 + dspck_dstio mulq_s.ph, 0x7fff7ffe, 0x80007fff, 0x80007fff, 0x00000000, 0x00200000 + dspck_dstio mulq_s.ph, 0x003be001, 0x7fffe001, 0x003c7fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00008001, 0x00008000, 0x00067fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x665f7fff, 0x66668000, 0x7ff88000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x7ffe8001, 0x7fff8000, 0x7fff7fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffc0ffd, 0xffe00ffe, 0x0fed7fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffd7ff28, 0xf0f0ff28, 0x015b7f80, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x01d80012, 0x01d9002f, 0x7fff3333, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfee37ffe, 0x011d7fff, 0x80007fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000e003, 0x00003ffc, 0x0000c003, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000fff8, 0x0006fff8, 0x0ffe7fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0xff510053, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000fdfc, 0x00000204, 0x006a803f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffe0000, 0x7fff8000, 0xfffe0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff0000, 0x0025e001, 0xff140000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffffffff, 0xfffdffff, 0x00d70016, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x02a30000, 0x02a47fff, 0x7ff90000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffffffe, 0x00107fff, 0xfff9fffe, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x0000003f, 0x000f0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0004ffee, 0xfeb73fe0, 0xfe1bffdd, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000ff80, 0xffd87fff, 0xff1fff80, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x1ffd01ff, 0xc0030ffe, 0xc0030ffe, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000db6f, 0x09c18006, 0x00002492, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x001d1ff8, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x999a0000, 0x66660015, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff0004, 0xff468000, 0x0003fffc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00abffff, 0x7ff90001, 0x00ace007, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00001101, 0x00152ea8, 0x00152ea8, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00016524, 0x00ff8e38, 0x00ff8e38, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x0000c71c, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xf802ffff, 0x80000006, 0x07fef003, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffd0003, 0x7ff00004, 0xfffd7fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffffffa3, 0xfffbcccc, 0x001f00e8, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x8000801f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x8001013d, 0x7ffffec3, 0x80018000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00220175, 0x80008002, 0xffdefe8a, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000ff00, 0x55557fff, 0x0000ff00, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xeb848001, 0x147c8000, 0x80007fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x7ffe0000, 0x7fffe003, 0x7fff0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x7ff9004d, 0x7fff004e, 0x7ffa7fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000e202, 0x7fff807f, 0x00001e1b, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xdb6d0093, 0x7fff0094, 0xdb6d7fc0, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff0000, 0x00010000, 0x8000e007, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x020a0000, 0xefd7ffd9, 0xefd7ffd9, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000fffd, 0x49246666, 0x0000fffd, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfff12493, 0x000fdb6d, 0x80008000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x801f0000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x0068fe27, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xe03f0000, 0x3fc0fff1, 0xc03f0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000001, 0xea200cf7, 0x0000000c, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffc9ffff, 0xffc9fffc, 0x7ffe000e, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xe38f000b, 0xe38e000c, 0x7ffb7fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x55560072, 0xaaaa0073, 0x80007fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00060000, 0x09000001, 0x005a0fb2, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x3ffb3332, 0x80048003, 0xc003cccc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffc10000, 0x80007ff0, 0x003f0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00007ffe, 0x000b7fff, 0x000b7fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff0000, 0xffff0007, 0x7fff0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffe5feb9, 0xffe52e09, 0x7ffafc75, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000fffe, 0xfffb8000, 0xfffd0002, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000ff3f, 0xfffe0302, 0xe38ee003, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x01d00003, 0x7fff0b0a, 0x01d1002e, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff0000, 0x012e7fff, 0xfff70000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000e5e0, 0x00004924, 0x0000d248, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000ffff, 0x3ffc001f, 0x0002ffee, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x03088002, 0x03098000, 0x7fff7ffe, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x0000ff1c, 0x801ffffd, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00001caa, 0x00007fff, 0x7fff1cab, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff7fff, 0x00288000, 0xfefd8000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0e370000, 0x1ffe0000, 0x38e3ffd2, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x017e0000, 0xfe420f0f, 0x92490000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xff1af384, 0x80006666, 0x00e6f066, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xc040f003, 0x8000800f, 0x3fc00ffe, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x7ffe0000, 0x7fff002a, 0x7fff0005, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x3f1e0000, 0x0000c001, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xe008ffff, 0x1ff8fff9, 0x80000004, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffcffff, 0xffe5003f, 0x11cdfffd, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x0194000f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfff20000, 0x7ffffffc, 0xfff20000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0xfe1e3ffe, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xc0070006, 0xc0078000, 0x7ffffffa, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000100, 0x0000ff00, 0x1c718000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xf00a0000, 0x7fc0ffc9, 0xf0030000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffb0000, 0x80030000, 0x0005d28f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfc4d8001, 0xfc4d7fff, 0x7fff8000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00b16666, 0x00000001, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000001, 0x00007fff, 0x7ff80002, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x002c7ff4, 0xfb448006, 0xfb448006, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x001d0001, 0x001e0006, 0x7fff1793, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00ff0000, 0xf803fff8, 0xf0010000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x7fff0000, 0x80000000, 0x8000803f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x49230005, 0x7fff0006, 0x49247fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00017ffe, 0x00027fff, 0x7ffe7fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000fffe, 0x00000002, 0x3fe08000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff0032, 0xffff7fff, 0x1ff80033, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000024, 0xc001007f, 0xffff2492, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x8002fff1, 0x8002000f, 0x7fff8000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00060000, 0xfffa0029, 0x80000002, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xff8bfff5, 0x8000fff5, 0x00757ffa, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x00040014, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000e00b, 0x00011ff8, 0x71c7800f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00050009, 0x000600ff, 0x7fff04f2, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x8003fffd, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x8001fff0, 0x8000fff0, 0x7fff7ffc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000ffff, 0x1fe0f003, 0x00000002, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xf87cfb15, 0x0f0f7f80, 0xc01ffb11, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffaffde, 0x00ff0022, 0xfd0f8000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000006, 0x00008000, 0xfffdfffa, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000ff80, 0xffc07fff, 0xffffff80, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00400000, 0x05b3002e, 0x05b3002e, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff0002, 0x0067fffe, 0xfff68000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00e00000, 0x80007ff8, 0xff200000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffe00000, 0xffe00000, 0x7fff00ba, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffc00000, 0x007fc5c4, 0xc03f0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000033, 0x0000019b, 0xf0030ff8, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xf9e7ff08, 0x71c70648, 0xf924ec4b, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000fffe, 0x0000001f, 0x8000f83e, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xe74dfff9, 0x80008007, 0x18b30007, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00eeffc8, 0xff12ff90, 0x80003ff8, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000001, 0xe7817fff, 0x00000002, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x8040003e, 0x7fc07fff, 0x8000003f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0ff80000, 0xe00f0000, 0xc0017ffc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xff80ffff, 0x7fffffea, 0xff80001f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0xc03fffc0, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00008000, 0x07fc0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xe38f0000, 0xc71c8000, 0x3ffc0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00007fff, 0xe38e0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00008008, 0x00007ff8, 0xffff8000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000f878, 0x00000f0f, 0x0000c003, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x7ff80000, 0x7ffe0000, 0x7ffafff0, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x000d0000, 0xdb6d0000, 0xffd00000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x07a20000, 0x8000fff0, 0xf85efe19, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffd0000, 0x80003ffe, 0x00030000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffdc0000, 0x80000034, 0x00240000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x7ffff007, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x1fed6db7, 0x800f9249, 0xe00f8000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0xfbbb7fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xf8f60004, 0x8006fffb, 0x070a8007, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfff0fae2, 0x00fd148a, 0xf868e01f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff8001, 0x1ffc7fff, 0xfffc8000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0007c002, 0x00083ffe, 0x7ffb8000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000fe38, 0x7fff01c8, 0x00008000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffe0000, 0xfff8ff00, 0x1ff80000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00008005, 0xfff60000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffffffb, 0x0001fffb, 0x80007fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xf15effff, 0x2492ff00, 0xcccc0002, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00010000, 0xfffd0000, 0xc00f0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffffc020, 0x3ffe3fe0, 0xfffe8000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000fffa, 0x00008000, 0x3ff00006, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000ffea, 0x0000ffe0, 0xfffd5555, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x1fe0003e, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00160000, 0x07fc0000, 0x01708000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfbe6ffff, 0xfbe6fff0, 0x7fff0268, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0048b6db, 0x007f7fff, 0x4924b6db, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000feb7, 0x00077fff, 0x0003feb7, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00018003, 0x00047ffd, 0x3ffc8000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffffd78, 0xff7f7fc0, 0x003ffd77, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x1fff0000, 0x8000ffdc, 0xe001fffd, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xc0100000, 0x80000000, 0x3ff01ffc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0xffe00042, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfff4ffc0, 0x156f0040, 0xffb98000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000014, 0x07fc0015, 0x00007ff9, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x80073332, 0x80003333, 0x7ff97ffe, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x803f0000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0xc0010000, 0x00007ff8, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00007fff, 0x14190000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffa90000, 0x801f000f, 0x00570000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x3ffb0000, 0x3ffcc03f, 0x7fff0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00010008, 0xe001fff8, 0xfff88000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfff50000, 0x000b0003, 0x80070028, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x7fff7fff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x8000e00f, 0x0000ffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000ed2a, 0xfc0112d6, 0x00008005, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0a8e001e, 0xe364003d, 0xd0c63ffe, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfff900c9, 0x7fff8000, 0xfff9ff37, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000ffff, 0x80000001, 0x0000f0f0, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x1fed1ff9, 0xc007e007, 0xc01f8000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff0000, 0x00020003, 0xffff0b25, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000ff01, 0x00028000, 0x249200ff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff0000, 0x0ffc0000, 0xfffff007, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfcb60193, 0x8002f9b2, 0x034ae001, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00008e38, 0xe0017fff, 0x00008e38, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00007ffe, 0xffe07fff, 0xffe07fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffdfff7, 0xffe85555, 0x0fd5fff3, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000fffe, 0xe0407fff, 0xfffcfffe, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff0000, 0xfc91ff94, 0x0007ffde, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x1fff7ffe, 0xc0017fff, 0xc0017fff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xff81e676, 0x007f7fff, 0x8000e676, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x49250000, 0xb6dbfffd, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfff40000, 0xf9170000, 0x00d7370e, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xffff0001, 0xffff8000, 0x066effff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000f008, 0xfe980ff8, 0x00008000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x0000002e, 0x00400000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000288, 0xfffef6ce, 0x0000dcb7, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00070000, 0x0005fff3, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffd2493, 0xe00f8000, 0x0009db6d, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xf0180002, 0xe02e014c, 0x3ff800e3, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0xfffcfdb5, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xf98f0000, 0xf31f1ffc, 0x3ffc0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000ffff, 0x00001ff0, 0x0000fffc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0xfffd0000, 0xfffd0000, 0x7fff0000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x0000ffff, 0x0001003d, 0x0ff8ffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.ph, 0x00008003, 0x00007fff, 0xfffd8003, 0x00200000, 0x00200000 + + writemsg "[21] Test mulq_s.w" + dspck_dstio mulq_s.w, 0xff0c108a, 0x7fffffff, 0xff0c108a, 0x0, 0x00000000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x00000003, 0xe0000003, 0xfffffff0, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x183db574, 0x80000000, 0xe7c24a8c, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x80000001, 0x80000000, 0x7fffffff, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0xffffffff, 0x0000001f, 0xffff35c4, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000001, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x00000014, 0x0002b663, 0x0003c2c1, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x80000040, 0x80000000, 0x7fffffc0, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0xfffffffb, 0x00000009, 0xc0000001, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x00000016, 0x00001668, 0x008359a8, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0xfffffff3, 0x0000000d, 0x80000000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x0db6db67, 0x92492492, 0xf0000007, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0xfffffe9a, 0x7fffffff, 0xfffffe9a, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x00000005, 0x00000016, 0x1ffffff8, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0xc0000002, 0xc0000001, 0x7ffffffd, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0xf8000005, 0x07fffffc, 0x8000001f, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x3fffffe1, 0xc000001f, 0x80000000, 0x00000000, 0x00000000 + dspck_dstio mulq_s.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00000000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000950, 0xf0000001, 0xffffb57e, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfff00096, 0x000fff6a, 0x80000005, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xfffffff9, 0xfffffff9, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffed029, 0x80000004, 0x00012fd7, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x0000010c, 0xfffffef4, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0x00005914, 0xfffffffa, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x0ffffffb, 0x0ffffffc, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000007, 0xfffe016e, 0xfffe016e, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000040, 0xffffffc0, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0xffffffff, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xffffffe7, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffc5c9, 0xffffc5c9, 0x7ffffffd, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000048, 0x0000005b, 0x66666666, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x0001c5fe, 0x1ffffff0, 0x000717fa, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffffffd, 0x00000004, 0xb6db6db6, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000035, 0x07313e72, 0x000003b8, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x07878783, 0x0f0f0f0f, 0x3fffffe0, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffffffc, 0x80000000, 0x00000004, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x92492492, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000004, 0x00000004, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000003, 0x24924924, 0x0000000b, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0xfc000001, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x49249249, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xe0000001, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x000042ba, 0xdb6db6db, 0xffff1672, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffff0001, 0x80000000, 0x0000ffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0x80000000, 0x00000001, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffe0, 0x7fffffff, 0xffffffe0, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffe0898, 0x6db6db6d, 0xfffdb4b2, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0xf8000001, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000004, 0x80000000, 0xfffffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x000018c6, 0x7fffffff, 0x000018c7, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0xfffffe56, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0xffff2078, 0x000020b2, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000547, 0xffe601dc, 0xffe601dc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffd5, 0x0000002b, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xffffffff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xb6db6db7, 0x49249249, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0xf0f8a664, 0x00000001, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x3a4591a6, 0x3a4591a7, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffffffe, 0x0013515a, 0xfffff583, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0xffffffff, 0x0004bf5d, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xffffff00, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00070ab3, 0xf0000003, 0xffc7aa60, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x01eb9ec6, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00001d42, 0xffffe2be, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000d04, 0x000026e8, 0x2ad42035, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000444, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0xfffea52d, 0x0000016c, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0x00076c0f, 0xfffffe7a, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000005, 0x80000003, 0xfffffffa, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xe0000007, 0xe0000007, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x28a9770b, 0xd75688f5, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x007bc9dd, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x0002b243, 0xffea6de7, 0xf0000003, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xaaaaaaaa, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x8000000f, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffef, 0xffffffeb, 0x66666666, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x71c71c72, 0x8e38e38e, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffb2beb4, 0xffb2beb4, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0xfffffffe, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x1ffffff0, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x0000003f, 0x0000007f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x0000007f, 0xffffff80, 0x8000007f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffff873, 0x38e38e38, 0xffffef03, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xff11e299, 0xffffff93, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffe2c0, 0x7fffffff, 0xffffe2c0, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x92492492, 0x7fffffff, 0x92492492, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xb6db6dbf, 0xb6db6db6, 0x7ffffff0, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0x00000007, 0xf0f0f0f0, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffff45ae, 0x03fffffe, 0xffe8b5c2, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffe9, 0xd216970c, 0x0000003f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x000085ee, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xfffffff8, 0xfbf0cdae, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffd5, 0x7fffffff, 0xffffffd5, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x0000000e, 0x000000de, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000007, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x71c71c72, 0x80000000, 0x8e38e38e, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xfffffe9a, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xf6ee22d3, 0xf6ee22d3, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x0ffffff8, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x06e0d113, 0x1ffffffe, 0x1b834451, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffffff9, 0x00000007, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x000fedbb, 0xfff01244, 0x8000003f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0xffffffec, 0x000d133d, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x0000770c, 0xeeae9cd4, 0xfffc901a, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffff80, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000016, 0x7fffffff, 0x00000017, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xffb013f5, 0xfffffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7ffffff7, 0x7fffffff, 0x7ffffff8, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffffffc, 0x0000000f, 0xe38e38e3, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xc0000005, 0x80000003, 0x3ffffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfd7927a7, 0x80000000, 0x0286d859, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xfffefd47, 0xfffffffd, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000005, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0xf8000001, 0x00000001, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xff19d329, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x0000001a, 0xffffffe2, 0x8e38e38e, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00008b8d, 0x80000000, 0xffff7473, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x000000ae, 0x00000001, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xfffffff9, 0xffde2edd, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000007, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x0000002c, 0xfffff0a0, 0xfe8d6d48, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7ffffffa, 0x80000006, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffffffa, 0xfffffffa, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x3e66848c, 0x3e66848d, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xff00ff01, 0x80000006, 0x00ff00ff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x1c71c71b, 0x1c71c71c, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xffffff8a, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0xc000000f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x0ffffffb, 0x7fffffff, 0x0ffffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x0000001b, 0x00001eb2, 0x00741f18, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000006, 0x80000000, 0xfffffffa, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfec0fe9f, 0x7fffffff, 0xfec0fe9f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xfffffffb, 0xfffffffa, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x3f336130, 0xc0cc9ece, 0x80000003, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x80000020, 0x7fffffe0, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0x01671684, 0xffffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x1ffffffb, 0x1ffffffc, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xfffffff8, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffe9c39, 0xfffe9c39, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfff26d00, 0x80000000, 0x000d9300, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x0000003f, 0x00462bc5, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffe5, 0xffd4233e, 0x00004d60, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x55555555, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x000000ff, 0x80000007, 0xffffff00, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x80000082, 0x7ffffffc, 0x8000007f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000001, 0x80000000, 0xffffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffa5, 0x03fffffe, 0xfffff4a1, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xf8000001, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x0b1b48af, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfee7cc77, 0xfee7cc77, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffed035, 0x7fffffff, 0xfffed035, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x0ffffffb, 0x7fffffff, 0x0ffffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x7fffffe0, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x24924924, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000665, 0x001c9d40, 0x001c9d40, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfeec5637, 0x80000000, 0x0113a9c9, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x80000001, 0x7fffffff, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x000020f9, 0x00041f3a, 0x03fffffe, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xc0000020, 0x3fffffe0, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffeb505, 0xffd6a0ba, 0x03fffffe, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0xfffffffa, 0x0038e08e, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x000000aa, 0xaaaaaaaa, 0xffffff00, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00009fb6, 0x80000006, 0xffff6049, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffffe0, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0x1ffffff8, 0xfffffffe, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xffff5c9e, 0xffff5c9e, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffec, 0x00000027, 0xc0000007, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x000001a7, 0x0000069e, 0x1ffffff8, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000a7d, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x000e65db, 0x80000000, 0xfff19a25, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xffffd56d, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x08d62e22, 0x08d62e23, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x01de3389, 0xfe21cc77, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7fffff7b, 0x7fffff80, 0x7ffffffb, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xf0000002, 0x0ffffffe, 0x80000005, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x7fffffc0, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x06ea08ba, 0x06ea08bb, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x000023a2, 0xf0000001, 0xfffee2e8, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x1fffffef, 0xc0000003, 0xc000001f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x000741c7, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x99999999, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffff, 0x00000001, 0xffff192b, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffffab1, 0x80000000, 0x0000054f, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffe7, 0xffffe80b, 0x0083b5b6, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x000123c5, 0x7fffffff, 0x000123c6, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00745b2f, 0xc0000001, 0xff1749a1, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x2082081f, 0x49249249, 0x38e38e38, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x99999999, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x03160aab, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xe000000f, 0xfffffffd, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x80000001, 0x80000000, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xfffffffa, 0x80000001, 0x00000006, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0xfffffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffffca, 0x3ffffff8, 0xffffff95, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x039ef36c, 0xe308649b, 0xf0000001, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000295, 0x80000000, 0xfffffd6b, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xfe0d4e6c, 0xfffffffc, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xffffff82, 0xffffff82, 0x7fffffff, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0xffffff5c, 0xffffe198, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7ffffff8, 0x00200000, 0x00200000 + dspck_dstio mulq_s.w, 0xff92e452, 0xfe4b9148, 0x1ffffff0, 0x00200000, 0x00200000 + + writemsg "[22] Test mulsa.w.ph" + + writemsg "[23] Test mult" + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffff80, 0x80001ee1, 0x8000001f, 0x000000ff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xfffffc4c, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffff9, 0x24924910, 0x00000030, 0xdb6db6db, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xf999999a, 0x39999999, 0x33333333, 0xe0000003, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xc0000000, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffed55c4, 0x0012aa3c, 0xffc8014c, 0x55555555, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000139c, 0xbffddadb, 0xffffb18d, 0xc0000007, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000600e, 0xdb6c36a0, 0x24924924, 0x0002a068, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffff8ff, 0xd404cc78, 0x00060edd, 0xfed82ad8, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffc0, 0x00000080, 0x7fffffff, 0xffffff80, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xc71c71e3, 0x71c71c80, 0x7fffffc0, 0x8e38e38e, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xf0f0f0f0, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x3fffffbf, 0x80000080, 0x7fffff80, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x002da41f, 0x23dbb8a8, 0x24924924, 0x013f7cda, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffff8bd, 0x80000000, 0x80000000, 0x00000e85, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x02ce79a3, 0xffc8bb91, 0xfffffff3, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x000003aa, 0x00000000, 0xfffff8ac, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x000c9f35, 0xa62ea81a, 0xec8d57a7, 0xff59da56, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000007, 0x00000001, 0x00000007, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfe3b2ec0, 0x0389a280, 0x7fffffff, 0xfc765d80, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000044, 0x7ffffeee, 0x7ffffffe, 0x00000089, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x000000d0, 0xfffffe5e, 0x7fffffff, 0x000001a2, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x07fffffe, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffc0, 0x00000200, 0x7ffffffc, 0xffffff80, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffd3, 0x0000005a, 0x7fffffff, 0xffffffa6, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000003, 0x5b09cf80, 0xf949ec61, 0xffffff80, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0001c000, 0x80000000, 0xfffc7fff, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x33333333, 0x80000000, 0x80000000, 0x99999999, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xffffff00, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000291, 0x00000000, 0xfffffade, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x0ffffff8, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x000001a8, 0x35cbde00, 0xfffe5622, 0xff00ff00, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffff6, 0x8000010a, 0x00000026, 0xc0000007, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xff99c744, 0xfffffffe, 0x00331c5e, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x007f807f, 0x7f00ff01, 0x7fffffff, 0x00ff00ff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x0000001f, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xa000002a, 0xf0000007, 0x00000006, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x7ffffffd, 0xffffffff, 0x80000003, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffeef, 0x66666224, 0xcccccccc, 0x00000553, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffc0, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000001d, 0x29f3de4e, 0x0000007f, 0x3ac97ab2, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x1ffffffd, 0x80000008, 0x7ffffffe, 0x3ffffffc, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xc0000002, 0x00000000, 0x7ffffffc, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x33333333, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffffe, 0x24613100, 0xfe04abf0, 0x000000f0, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x000432ad, 0xfff79aa4, 0x0008655c, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0x88022908, 0xfffffd51, 0x002cb688, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000277b, 0xffffb108, 0x7fffffff, 0x00004ef8, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0x80000040, 0xffffffff, 0x7fffffc0, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x8000007f, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffe0, 0x00000040, 0xffffffc0, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xffef3bc0, 0xffffffc0, 0x00004311, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00021873, 0x80000000, 0x80000000, 0xfffbcf19, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x000001fd, 0xe18d1db0, 0xfe0afcaa, 0xfffefb78, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0ffffff7, 0xe0000010, 0x7fffffff, 0x1ffffff0, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000001b, 0xffffffcf, 0x0000003f, 0x71c71c71, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000007e, 0xd06923d4, 0x00c47864, 0x0000a53d, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffaf6, 0x00002850, 0x80000004, 0x00000a14, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000006, 0x00000000, 0x80000000, 0xfffffff4, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xe0000003, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000003f, 0x7ffffd06, 0x7ffffffa, 0x0000007f, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffe98e, 0x9248e13e, 0x00004e8d, 0xb6db6db6, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x3fffffbf, 0x80000080, 0x7fffffff, 0x7fffff80, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x000fa5ff, 0x80000000, 0x80000000, 0xffe0b401, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfe000001, 0x00000000, 0x03fffffe, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffff25, 0x00000000, 0x80000000, 0x000001b6, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xfffffff9, 0x00000007, 0xffffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000009, 0x80000000, 0x80000000, 0xffffffed, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000a809, 0x5ffabfb5, 0xe0000001, 0xfffabfb5, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfe666667, 0x30ccccce, 0x99999999, 0x03fffffe, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x000051b2, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000006, 0xfffffff2, 0x7fffffff, 0x0000000e, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x007155c7, 0x1caa7200, 0x8e38e38e, 0xff00ff00, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffff80, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000002, 0x7ffffec5, 0x8000003f, 0xfffffffb, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x0ffffff8, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xc0000003, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x07fffffb, 0xf0000008, 0x0ffffff8, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xe0000001, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffffd, 0x6db6db72, 0xfffffffa, 0x6db6db6d, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0ffffffc, 0x20000015, 0x80000003, 0xe0000007, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffe0e21, 0x8003e3bd, 0xfffc1c43, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffff8, 0x00000010, 0xfffffff0, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0x80000001, 0xffffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xc0000001, 0xfffffffd, 0x7fffffff, 0x80000003, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000000f, 0x7fffffe1, 0x0000001f, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffaaffaa, 0xff55ff56, 0xaaaaaaaa, 0x00ff00ff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xc0000003, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x80000000, 0x80000000, 0xffffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xd5555555, 0x80000000, 0x55555555, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xe26e778a, 0x00000000, 0x3b2310ec, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00159f32, 0x00001982, 0x000000d9, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000029, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7ffffff8, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x1ffffffc, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffffd, 0x8000001e, 0x00000005, 0x80000006, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffed, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x1ffffffe, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000111d, 0x4bab939c, 0xfef9f346, 0xffef47da, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xffff9d82, 0xfffffff2, 0x00000709, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xfffb09c5, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xff2d02c3, 0xa97e9e60, 0xf968161a, 0x1ffffff0, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffa5, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x000159d9, 0x00000000, 0x80000000, 0xfffd4c4e, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x3ffffffe, 0x00000003, 0x7fffffff, 0x7ffffffd, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000010, 0xfffffffe, 0xfffffff8, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffa1, 0x999999f8, 0x66666666, 0xffffff14, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x001eebe2, 0x9721b440, 0xfa7075b8, 0xfa7075b8, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffffe, 0x00000004, 0x7fffffff, 0xfffffffc, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x03ffffff, 0x80000004, 0x1ffffffe, 0x1ffffffe, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x80000000, 0xffffffff, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xfffffff4, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffff1, 0xa4223c13, 0x001dbb2f, 0xffff845d, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x28f5c28f, 0x0a3d70a4, 0x66666666, 0x66666666, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffdd95, 0x000044d6, 0xffffbb2a, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xf8e38e3c, 0x4e38e3a0, 0x3fffffe0, 0xe38e38e3, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffd32, 0xf43ba168, 0xfffeef0c, 0x02a0829e, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xff5c6f4b, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xe000000f, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x12492491, 0xdb6db6dc, 0x7fffffff, 0x24924924, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x002ed3b6, 0xfdce136c, 0xff44b124, 0xc0000003, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x02eb78cd, 0xfa290e64, 0x05d6f19c, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0x80000001, 0xffffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffffe, 0x80000030, 0xfffffffa, 0x3ffffff8, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000002, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfff48c2c, 0x916e7a6e, 0xff48c2c9, 0x0ffffffe, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x99999999, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x0187ef00, 0xfffe7811, 0xffffff00, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xc0000000, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfe000000, 0xbffffff0, 0x3ffffff0, 0xf8000001, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0x8000001e, 0x00000002, 0xc000000f, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000007, 0x7ffffff1, 0x0000000f, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xfff81c0c, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xf0000001, 0x3ffffffa, 0x3ffffffe, 0xc0000003, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xc0000000, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffe1, 0x400001ec, 0x1ffffffe, 0xffffff0a, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x38e38e3a, 0xe38e38e3, 0xfffffffe, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000039c, 0x4ffe31d8, 0x0ffffff8, 0x000039c5, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xc71c71c7, 0x80000000, 0x71c71c71, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x35250910, 0x000074a4, 0x000074a4, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x0001cc6c, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00006834, 0xfffffffa, 0xffffeea2, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffff21fd, 0x9a3e884e, 0xff209972, 0x00fe67df, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xff56b900, 0xfff78940, 0x00000014, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xf8000002, 0xffffffff, 0x07fffffe, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xfb83a9f5, 0x0000142f, 0xffffc71b, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000003d, 0x7fffff85, 0x0000007b, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xc0000000, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xc0000000, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xffe0894c, 0x0007ddad, 0xfffffffc, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xf9d62cdf, 0x80000000, 0x80000000, 0x0c53a641, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x1fffffef, 0xc0000020, 0x3fffffe0, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xf5ae1969, 0x94a3cd2d, 0x7fffffff, 0xeb5c32d3, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x7ffffffa, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xffffff46, 0x0000001f, 0xfffffffa, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xf8000002, 0xdfffffc8, 0x1ffffff8, 0xc0000007, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000001, 0x7ffffffd, 0x7fffffff, 0x00000003, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xfffa8ef6, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00ff00ff, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xfffeffce, 0x00005566, 0xfffffffd, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000002, 0x80000000, 0xfffffffb, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x04924924, 0x36db6db8, 0x24924924, 0x1ffffffe, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffe8787e, 0x00eb4b14, 0xffd0f0fc, 0x7ffffffb, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffffe, 0x00000040, 0xfffffffc, 0x7ffffff0, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffffd, 0x00000060, 0x7ffffff0, 0xfffffffa, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000007, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffd0, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x23925630, 0x00000006, 0x05edb908, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xc0000001, 0x7ffffffe, 0x7fffffff, 0x80000002, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffd5ed, 0x8003f1bc, 0xe0000003, 0x00015094, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffc59623, 0x00000000, 0x80000000, 0x0074d3ba, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0x00000000, 0x80000000, 0x00000002, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00090b11, 0x5f6f4eea, 0xff6f4eea, 0xf0000001, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x01fffffe, 0xfc000002, 0x7fffffff, 0x03fffffe, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00001756, 0x7fff73f9, 0x80000003, 0xffffd153, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffd0a, 0x705814cc, 0x000184ba, 0xfe0d199e, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xf0000003, 0x9ffffff9, 0xe0000007, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00016eb5, 0x1cf71a04, 0x00448344, 0x055a36b1, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000072c, 0x80000000, 0xfffff1a7, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xfbc0adf4, 0xfffffffc, 0x010fd483, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x24924924, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffe6, 0x80000000, 0x00000033, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xf9fa3ca4, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x07fffffc, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0028575c, 0x7faf5147, 0x7fffffff, 0x0050aeb9, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000001, 0x80000000, 0xfffffffd, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0020c263, 0x493a6936, 0xffb38fc3, 0x92492492, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x92492492, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7ffffffe, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0000003b, 0x924923a4, 0x24924924, 0x000001a1, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x1ffffff0, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xffffff97, 0xfffffff9, 0x0000000f, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x6614e9cb, 0x00000003, 0x2206f899, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xd5555555, 0x80000000, 0x55555555, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000010, 0xfffff780, 0x3fffffe0, 0x00000044, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffffe, 0x38e38e3c, 0xfffffffc, 0x71c71c71, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000ada, 0xfffd74ac, 0xffffd494, 0xc000000f, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xfffffffe, 0x80000000, 0x00000003, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x000e7bb8, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x06666665, 0x19999994, 0xe0000007, 0xcccccccc, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x40000000, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xfffffe1e, 0xfffffffe, 0x000000f1, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x0ffffff8, 0x80000000, 0x80000000, 0xe000000f, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x3fffffbf, 0x80000080, 0x7fffffff, 0x7fffff80, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000007, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x06666664, 0xc6666668, 0x66666666, 0x0ffffffc, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xfffffe04, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x0005f1dd, 0x00000000, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x3fffffe1, 0x000003c1, 0x8000001f, 0x8000001f, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xfffff12d, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xfe8fe1ac, 0xfffffffe, 0x00b80f2a, 0x0, 0x0 + dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xc000000f, 0x00000000, 0x0, 0x0 + + writemsg "[24] Test multu" + dspck_astio multu, 0x0, 0x0, 0xfe76f09e, 0xc2ab91bb, 0xfe770721, 0xffffe95b, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x000074a2, 0xf426fd5d, 0xffffe5ff, 0x000074a3, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x8e38936d, 0xc71c91d4, 0x8e38e38e, 0xffff6fc6, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7f8a380f, 0x80eb8fdf, 0x7fffffff, 0xff147021, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xcccccccc, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x33333333, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x03fffffe, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x40000006, 0x7fffffe2, 0x7ffffffe, 0x8000000f, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000007, 0x7ffffff1, 0x7fffffff, 0x0000000f, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x02e86b10, 0x80000000, 0x80000000, 0x05d0d621, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x0000019a, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x000006f6, 0x3fff909c, 0x1ffffffe, 0x000037b2, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000008, 0x7fffff89, 0x7ffffff9, 0x00000011, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x92492492, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00018e61, 0xfff9c678, 0xfffffffc, 0x00018e62, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ffffffc, 0x00000006, 0x7fffffff, 0xfffffffa, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0000052b, 0xfffff5a8, 0x7fffffff, 0x00000a58, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7f473cc5, 0x80000000, 0xfe8e798b, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xf0000003, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x07fffffe, 0xf0000002, 0x0ffffffe, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0xdb6cdb6d, 0x49250000, 0xdb6db6db, 0xffff0000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x0000000f, 0x00000003, 0x00000005, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x9225e90d, 0x6dc87930, 0x92492492, 0xffc257d8, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x000a182c, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0630fe6a, 0x00000000, 0x80000000, 0x0c61fcd4, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7ffffff9, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00ff00f6, 0xdd22dd2b, 0xfffff7d5, 0x00ff00ff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xfff85e98, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ffe475d, 0x0006e284, 0xfffc8ebe, 0x7ffffffe, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffff06, 0x00000000, 0x80000000, 0xfffffe0c, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffffff, 0x00000000, 0xfffffffe, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0xe1000005, 0xa0000009, 0xf0000003, 0xf0000003, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ff24291, 0x001b7adc, 0x7fffffff, 0xffe48524, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x80000000, 0x00000001, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fc59261, 0x0074db3c, 0xff8b24c4, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x03fffffe, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x020fc465, 0xfbe07734, 0x7fffffff, 0x041f88cc, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x37fffff2, 0x3ffffff0, 0x3ffffff0, 0xe0000001, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xfffffff9, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x018a5afd, 0x16485b28, 0x38e38e38, 0x06ee9973, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x14b59aac, 0x001069e4, 0x00000143, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffffff, 0x00000000, 0xfffffffe, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xffff0000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000015, 0xfffff584, 0x00000016, 0xffffff86, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x50c299ad, 0x01482b13, 0x0000003f, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x032edfac, 0x4d120538, 0x3ffffffc, 0x0cbb7eb2, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000063, 0x80000000, 0x000000c7, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xe000000f, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x05e1578d, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3fffffdf, 0x80000040, 0x7fffffff, 0x7fffffc0, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x70000001, 0x60000001, 0xe0000001, 0x80000001, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x051c66dc, 0xf5c73246, 0x051c66dd, 0xfffffffe, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ffffff0, 0x80000000, 0xffffffe1, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0ffffffd, 0xa000000c, 0x1ffffffc, 0x7ffffffd, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xfffe8fd3, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3ffffffc, 0x80000000, 0x80000000, 0x7ffffff9, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ffffffe, 0x00000000, 0xfffffffc, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xe38e38e3, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ffffffc, 0x80000005, 0xfffffffb, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x03fffffe, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000112, 0xfffdf3c8, 0xfffffe18, 0x00000113, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x038e38e3, 0x0e38e390, 0x1ffffffc, 0x1c71c71c, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xf0f0f0f0, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x4000001f, 0x80000000, 0x8000003f, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00b125e3, 0x1c9a1dfc, 0x00ec3284, 0xc000001f, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xcccccccc, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ff6577f, 0xffecaefe, 0x80000001, 0xffecaefe, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xdb6db6db, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x0000002a, 0x0000000e, 0x00000003, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000e71, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0xff872168, 0x00f1bd2c, 0xff87216a, 0xfffffffe, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0ffffffc, 0x00000000, 0x1ffffff8, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7e68000b, 0x00000000, 0x80000000, 0xfcd00016, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xffff0000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000003, 0x677d987f, 0x0000ffff, 0x00036781, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffffff, 0x80000000, 0x80000000, 0xffffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x000003c0, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ff831e4, 0x80000000, 0x80000000, 0xfff063c9, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x009abdbd, 0xff654242, 0x00e81c9d, 0xaaaaaaaa, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000942, 0x38e36930, 0x00005354, 0x1c71c71c, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0xfffdaeea, 0x52fcab79, 0xffffd9b5, 0xfffdd535, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x5397829c, 0x687d6344, 0x92492492, 0x92492492, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xc71c71c7, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x6db6ae6e, 0xb6dbb8b4, 0xffff9704, 0x6db6db6d, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x000079c8, 0x00000000, 0x0000f390, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffff89, 0x80000000, 0x80000000, 0xffffff13, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000002, 0x00000000, 0x00000004, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3ffffffc, 0x00000007, 0x7fffffff, 0x7ffffff9, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00085b36, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000015, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x329161f8, 0xfcd6e9e1, 0x71c71c71, 0x71c71c71, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000fff, 0xeffe0002, 0x0000ffff, 0x0ffffffe, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x0000005c, 0x0000002e, 0x00000002, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0xffffb839, 0x0002cd62, 0xffffb843, 0xfffffff6, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffceec, 0x00000000, 0x80000000, 0xffff9dd8, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0xffffcf4a, 0x004def30, 0xfffffe58, 0xffffd0f2, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3ffffffb, 0x80000008, 0x7ffffff8, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffff24, 0x80000000, 0x80000000, 0xfffffe49, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000001, 0xfffffffc, 0x7fffffff, 0x00000004, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x000009ee, 0x5af151c4, 0x001e4dca, 0x0053e53a, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x06f539d5, 0x92a45fc4, 0x08b2884b, 0xcccccccc, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fc9ef10, 0xfd773484, 0xff93de16, 0x80000006, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffffc6, 0x80000000, 0xffffff8d, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ffffffb, 0x00000008, 0x7fffffff, 0xfffffff8, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000003, 0xfc03fc00, 0x00000004, 0xff00ff00, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffff15, 0x00000000, 0x80000000, 0xfffffe2a, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x8000001f, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000074, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x000001a4, 0x00000000, 0x00000348, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0574b162, 0xcaca899b, 0x0574cbe1, 0xfffb24fb, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x40000000, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0efffffe, 0x4ffffffa, 0xf0000003, 0x0ffffffe, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x000000d1, 0x7ffff2e8, 0x00000346, 0x3ffffffc, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x30000000, 0x69999999, 0x33333333, 0xf0000003, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0xffffffff, 0x80000001, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x093a7f8a, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00007735, 0xffff88ca, 0x00007736, 0xffffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x009488a6, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7f057c01, 0x944d7360, 0x8e38e38e, 0xe4a378d0, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0064c309, 0xfcd9e7b0, 0x00c98614, 0x7ffffffc, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0000000f, 0x80000000, 0x80000000, 0x0000001f, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ffffffe, 0x80000000, 0xfffffffd, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000003, 0xdfffffc2, 0x0000001f, 0x1ffffffe, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x0ffffff8, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0dfb8d31, 0x6408e59d, 0x1bf71a63, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffa0, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xc0000003, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x40000003, 0x80000000, 0x80000007, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0xf8000001, 0x0ffffffa, 0xf8000003, 0xfffffffe, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0003f590, 0xfe053780, 0x7fffffc0, 0x0007eb22, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000003, 0xfff80180, 0xfffe0060, 0x00000004, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0000001f, 0x80000000, 0x0000003f, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00041824, 0x00000206, 0x00000206, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x749e996a, 0x96c2cd29, 0xe93d32d7, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0000010f, 0x8fffbc1c, 0x000021f2, 0x07fffffe, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00878b27, 0x000066f7, 0x00000151, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000003, 0x00000000, 0x00000006, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xc000000f, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xfff168d9, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00ff00fe, 0x47b847b9, 0x00ff00ff, 0xffffff47, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7c000007, 0x50000012, 0x80000006, 0xf8000003, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00c11193, 0x0003c921, 0x00000033, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffffeb, 0x00000028, 0x7fffffff, 0xffffffd8, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00003a82, 0x7ffe2bec, 0x00007505, 0x7ffffffc, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xfffffffa, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x01145411, 0xf534b74c, 0x0228a824, 0x7ffffffb, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xffffffdb, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x000001c0, 0x7ffffc7f, 0x00000381, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xf8000001, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x33333333, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000004, 0xfffffff6, 0x0000000a, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x66666666, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x1b27e4eb, 0xa9477b41, 0xdb6db6db, 0x1fae8b13, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x0000be96, 0x0000261e, 0x00000005, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x55555551, 0xaaaaaaae, 0xfffffff6, 0x55555555, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xe000000f, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0003995e, 0xfff8cd42, 0xfffffffe, 0x0003995f, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3ffffffc, 0x80000006, 0x7ffffffa, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000018, 0xdb6db6b2, 0x0000003a, 0x6db6db6d, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ffff9a6, 0x80000000, 0x80000000, 0xfffff34d, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ffffffe, 0x80000001, 0x7fffffff, 0xffffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x0000ffff, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x0000000f, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x5555555e, 0xfffffff6, 0xaaaaaaaa, 0x8000000f, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0000045c, 0x7ffff747, 0x000008b9, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x40000000, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0ffffffd, 0xe0000004, 0x1ffffffc, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x0f47fd80, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x61861860, 0xf3cf3cf4, 0x92492492, 0xaaaaaaaa, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x000b3ecb, 0xbc200518, 0x000b3ede, 0xfffe6034, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x6fffffff, 0x9fffffff, 0xe0000001, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x965ed6bb, 0x9649f1c4, 0xc43375ce, 0xc43375ce, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x01a780d2, 0xfcb0fe5a, 0x034f01a6, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x000147f5, 0xfffeb80a, 0x000147f6, 0xffffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0000001d, 0x1000001f, 0x0000001f, 0xf0000001, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xff2e87d4, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000001, 0x493e3209, 0x0000001f, 0x0a9ee8d7, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x07cebd1b, 0x00000001, 0x07cebd1b, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0000000c, 0x8787877b, 0x000000d5, 0x0f0f0f0f, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x05d59a7e, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffc139, 0x00007d8c, 0x7fffffff, 0xffff8274, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0xffaa6169, 0xffaa6169, 0x00000001, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000026, 0x00000000, 0x0000004c, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x000021e6, 0xc9462000, 0x0000b200, 0x30c1d990, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x4000000d, 0x7fffff84, 0x8000001f, 0x7ffffffc, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x1999999a, 0x4ccccccc, 0x33333333, 0x80000004, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffffc2, 0xfffffe80, 0xffffff80, 0x80000003, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x1c71c71b, 0xc71c71c8, 0x1c71c71c, 0xfffffffe, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0xeffffffb, 0x7fffffe8, 0xfffffff8, 0xf0000003, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0000001a, 0x00000000, 0x00000034, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x004dffc5, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xb6db6db6, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x80000002, 0x7ffffffd, 0xffffffff, 0x80000003, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xfffffb6c, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3ffffff0, 0x00000000, 0x7fffffe0, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x1fffffff, 0xa4924924, 0xe0000001, 0x24924924, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000007, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x78afbbdb, 0x1d41108c, 0x7ffffffe, 0xf15f77ba, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7f807f80, 0x00000000, 0x80000000, 0xff00ff00, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x01865853, 0x80000000, 0x80000000, 0x030cb0a7, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x276b6547, 0x0d23cc6d, 0x00000003, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7ffffffe, 0x80000001, 0xffffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fff8000, 0x00000000, 0x80000000, 0xffff0000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x7fffffff, 0x00000000, 0xfffffffe, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x000001e3, 0x00004dfc, 0xc000001f, 0x00000284, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xf9e53251, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x4000003d, 0xfffffe83, 0x8000007f, 0x7ffffffd, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x40000001, 0x00000000, 0x80000002, 0x80000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x0000795a, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x003dbb65, 0x00000000, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x000024fc, 0x0000062a, 0x00000006, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0xb216ed65, 0x736f7568, 0xf9534c5c, 0xb6db6db6, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x0fcf55dc, 0xc0c2a88c, 0x0fcf55dd, 0xfffffffc, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x6db6c500, 0xb6db9316, 0x6db6db6d, 0xffffcbae, 0x0, 0x0 + dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00ff00ff, 0x0, 0x0 + + writemsg "[25] Test precr.qb.ph" + dspck_dstio precr.qb.ph, 0x997ce000, 0xfa99ff7c, 0x1fe08000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0008ff00, 0x80000008, 0x7fff8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xbd1e1b49, 0xe1bd001e, 0x001b9249, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf848d166, 0x0ff80448, 0xfdd10a66, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0600feab, 0x00068000, 0xfffe1cab, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xffff023e, 0x7fffffff, 0x0002003e, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfe3300e6, 0xfffe3333, 0x8000fbe6, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xdbffffe9, 0xb6db7fff, 0xffffd3e9, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00000092, 0x00000000, 0x0000f892, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0080ff53, 0x80007f80, 0x7fff0753, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x006e0306, 0x8000ff6e, 0xe0030006, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x88dbf0f7, 0x0088b6db, 0x7ff000f7, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xaae5aac3, 0xaaaaffe5, 0xfcaa07c3, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfdfe5549, 0xfffd3ffe, 0x55559249, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x05e1acff, 0x8005ffe1, 0x09ac7fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x000007fe, 0x00000000, 0xc0071ffe, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xe7fbdfde, 0xfee77ffb, 0xebdf02de, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfe0133ff, 0x1ffe0001, 0xfd337fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfa793f02, 0x7ffa0c79, 0x803f0002, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf9ff0000, 0xfff97fff, 0x00008000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x8eff0122, 0xe38e7fff, 0xf0010022, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00e80000, 0x0000ffe8, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xffffe300, 0x7fff7fff, 0xffe30000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00ff000a, 0x00007fff, 0x0000000a, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x3fff1f00, 0xc03f7fff, 0x801f8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x1300fff8, 0x00130000, 0x7fff3ff8, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0000c366, 0x00000000, 0x00c36666, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfffd0094, 0x7ffffffd, 0x80000094, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0000e3ff, 0x00000000, 0x38e3ffff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfdc3f600, 0xfffdffc3, 0x02f60000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x03f800ff, 0x00031ff8, 0x00007fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xeb00e04a, 0xffeb8000, 0xffe0024a, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfefffd8e, 0x0ffe7fff, 0xfffdf78e, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfff8b901, 0x00fffff8, 0xf3b9c001, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x3a330000, 0x003a3333, 0x00008000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff023ffe, 0x7fff8002, 0xc03f07fe, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xaae0ff02, 0xaaaaffe0, 0x7fff0002, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xffc0ff49, 0x7fff3fc0, 0x7fff3949, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff00af00, 0x7fff8000, 0x0faf0000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff000005, 0x7fff0000, 0x80008005, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x03000000, 0x00030000, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf038fa00, 0x7ff08e38, 0xfffa8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0060036d, 0x00000060, 0x0003ff6d, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00000f5c, 0x00000000, 0xf90fdd5c, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xffff3392, 0x7fffffff, 0x33332492, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x07800001, 0xf007ff80, 0xff008001, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00fcf803, 0x80000ffc, 0x3ff8f003, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x07fffff0, 0xc0077fff, 0x7ffff0f0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0f354101, 0xc00fff35, 0x0441f801, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff02fc03, 0x7fff0002, 0x3ffcf803, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xb1ffb1ff, 0x00b17fff, 0x00b17fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x33f005ff, 0x3333fff0, 0x80057fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x3fffff00, 0xc03f7fff, 0x7fff0000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfc000000, 0x3ffc8000, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x09003855, 0x00098000, 0x8e385555, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xe0fff8fc, 0xffe07fff, 0xfff8fffc, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0000240f, 0x00000000, 0x4924000f, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x07c003f0, 0xf0077fc0, 0xe003f0f0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff000000, 0x7fff0000, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00dd0000, 0x80000cdd, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xe80000f8, 0xffe80000, 0x8000fff8, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x38490c04, 0x8e38f549, 0x000c8004, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf1fef9f9, 0xfff1fffe, 0xfff97ff9, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xffa13f00, 0x7fffffa1, 0xc03f8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00ff00ff, 0x80007fff, 0x80007fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfc000105, 0x7ffc0000, 0xf8010005, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff000000, 0x7fff8000, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0002ff49, 0x80008002, 0xffff9249, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0100fdc8, 0x80018000, 0xfffd02c8, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf001ff00, 0x7ff00001, 0x7fff0000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0005f800, 0x00000005, 0x7ff88000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00fe00fe, 0x8000fffe, 0x8000fffe, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x3fc0ff00, 0xc03f3fc0, 0x7fff0000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf80001fd, 0x3ff88000, 0x00017ffd, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0001ff87, 0x00000001, 0x7ffffe87, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf96600ff, 0xfff9f566, 0x8000ffff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x6d7efef2, 0xdb6d007e, 0x07fefff2, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfffc0000, 0x7fff1ffc, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00e2c7ff, 0x0000ffe2, 0x71c77fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0001fff8, 0x8000fc01, 0x7fff1ff8, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xdb03dfc0, 0xffdb0003, 0xe6dfffc0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf8009200, 0x1ff88000, 0x24920000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00801c00, 0x00007f80, 0xc71c8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00cc0ee4, 0x8000cccc, 0x000effe4, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x15180000, 0xfe150318, 0x80000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf8000000, 0x0ff88000, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xe1001cff, 0xfde10000, 0xc71c7fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00f800f3, 0x80003ff8, 0x000035f3, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfffe0103, 0x7fff7ffe, 0x80010003, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfcf9fcf9, 0xfffc7ff9, 0xfffc7ff9, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0000e300, 0x80008000, 0x38e30000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00fffd08, 0xff007fff, 0xfffd1008, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x015cfc00, 0xfc01fb5c, 0xfffc0000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfe130000, 0x0ffe0113, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x7805f001, 0x00780005, 0xf0f0c001, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x06ffff2f, 0xf0067fff, 0x7fff002f, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x000017e0, 0x80000000, 0x0a173fe0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf7c0061c, 0xfff73fc0, 0x8006fa1c, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfcc400eb, 0x07fce9c4, 0xff00f3eb, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x03808fff, 0xe003ff80, 0x1c8fffff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x3cf0fcf0, 0x003cf0f0, 0xfffcfff0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x01f50800, 0xf001fff5, 0x00088000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfc070f01, 0xfffcc007, 0x800fc001, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x3ff30366, 0x803ffff3, 0x00036666, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x7f5700ff, 0x2b7f0257, 0xec007fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xffd1c07f, 0x7fff26d1, 0x3fc0007f, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0801c747, 0x0008f001, 0x71c7fc47, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xe0994f00, 0x7fe09999, 0x094f8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x3c238e01, 0xff3cef23, 0xe38ec001, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x02fc0462, 0x0002fffc, 0x00040f62, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf8018bf9, 0xfff8e001, 0x018bfff9, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xb6fff001, 0x6db6ffff, 0xfff0e001, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xed000000, 0x02ed8000, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff03ff00, 0xfffff803, 0x7fff8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf805f805, 0xfff88005, 0xfff88005, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xe7ee3f33, 0xe2e731ee, 0x803f3333, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00fe0000, 0x00001ffe, 0x80000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00f91f00, 0x8000fff9, 0xe01f0000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x89fc0000, 0xff890ffc, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfb07e767, 0xfffbc007, 0xffe70167, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x3360fab6, 0x0033fe60, 0xfffa6db6, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfb00fe00, 0x7ffb0000, 0xfffe8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00011c1b, 0x8000c001, 0xc71c001b, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfff8fff8, 0x7fff1ff8, 0x7fff1ff8, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff8f71fe, 0xfffff88f, 0x1c717ffe, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0306fce0, 0x00038006, 0xfffc7fe0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x000000ff, 0x00008000, 0x0000ffff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x4a00ffcb, 0xff4a8000, 0x7ffff8cb, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00ff3300, 0x00007fff, 0x33330000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00e00000, 0x00003fe0, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x9202f8ff, 0x24920002, 0x1ff800ff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00fa1c00, 0x0000fffa, 0xc71c8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x1f3fc03f, 0xc01fc03f, 0xffc0003f, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00f00000, 0x80003ff0, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x24ff1e00, 0x49247fff, 0x0e1e0000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x5dff5dff, 0xfe5dffff, 0xfe5dffff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00c0ffea, 0x00007fc0, 0x7fff00ea, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00000000, 0x00008000, 0x00008000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfffff713, 0x7fff7fff, 0x01f70013, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x01c9b6de, 0x8001ffc9, 0xe4b6fcde, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00000007, 0x00000000, 0x80008007, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xc800d151, 0x00c88000, 0xffd10351, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xeaf80000, 0xffea3ff8, 0x80000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x92fcfc2b, 0x24923ffc, 0xfffcf72b, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfe10a803, 0x03fe0310, 0xffa8c003, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x003f51f2, 0x8000803f, 0xfe51d6f2, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0fbcfcff, 0x800fffbc, 0xfffc7fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x71000ef0, 0x1c718000, 0x0e0ef0f0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00ff0001, 0x80007fff, 0x00000001, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x22f0e005, 0x00221ff0, 0x11e00005, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xffa506ff, 0x7ffff8a5, 0x00067fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00b9faa3, 0x8000ffb9, 0xfffaffa3, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00f0c7fb, 0x00003ff0, 0xf3c77ffb, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfe6dd500, 0xfffedb6d, 0xfed58000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00ff8bf2, 0x00007fff, 0xff8bfff2, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00ff8cf0, 0x00007fff, 0x018cf0f0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x01003f86, 0xf8018000, 0xc03f0086, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff008c07, 0x7fffff00, 0xf18cf007, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfb3f3600, 0xfffb003f, 0xff360000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x000c1f00, 0x0000fc0c, 0x801f0000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x000008b1, 0x00000000, 0x0008fab1, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xaaffaaff, 0xaaaaffff, 0xaaaaffff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00fcfee3, 0x8000fffc, 0x07feffe3, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0000feff, 0x80000000, 0x0ffe7fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00330033, 0x80001e33, 0x80001e33, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfc00fecc, 0x07fc8000, 0xfffecccc, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf904ff02, 0xfff90004, 0x7fff0002, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00fd002b, 0x0000fffd, 0x8000ff2b, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x1c6dfc00, 0xc71cdb6d, 0x1ffc8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf8fe49fc, 0xfff83ffe, 0x92491ffc, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfb3f0480, 0xfffbc03f, 0x0004ff80, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xda1500f0, 0x27da0015, 0x80003ff0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x3f00009a, 0x803f8000, 0x0000fe9a, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xaafff001, 0xaaaa7fff, 0x3ff0fc01, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0004ff71, 0x00000004, 0x7ffff271, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00f80000, 0x80003ff8, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x006a0000, 0x8000016a, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x01a04801, 0xf001f5a0, 0x1f480001, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x05ffffb1, 0x80057fff, 0x00ff00b1, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0000ffff, 0x00000000, 0x7fff7fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x40ff40ff, 0x00407fff, 0x00407fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x07fff538, 0xf007ffff, 0xfff58e38, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0000002e, 0x80008000, 0x8000df2e, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x4800b200, 0xff480000, 0xfcb28000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xc0ff0000, 0x7fc07fff, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x000007fc, 0x00000000, 0x00070ffc, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff3ffffe, 0x7ffffc3f, 0x7ffffffe, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x005f00ff, 0x8000005f, 0x00007fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfeff80aa, 0x07fe7fff, 0x7f80aaaa, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0000250e, 0x00000000, 0xff25000e, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf30100c0, 0xfff30001, 0x8000fbc0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfc00ffc2, 0xfffc8000, 0x7fff00c2, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xf6ff6a05, 0x00f67fff, 0xff6a0005, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x38004100, 0x8e380000, 0x01418000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00000f00, 0x80008000, 0xe00f8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x491cf0ff, 0x0049001c, 0xf0f07fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x051f16f8, 0x0005801f, 0x01161ff8, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xefb6c9f0, 0xffef6db6, 0xdac97ff0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff6fff6f, 0x7fffea6f, 0x7fffea6f, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x019d0000, 0x0001ff9d, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00003b8b, 0x00008000, 0x003b028b, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x1a29ff06, 0x001a0029, 0x7fff8006, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xd3d2fffc, 0x1ad3f3d2, 0x7fff7ffc, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff000000, 0x7fff8000, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x12f07a00, 0x00127ff0, 0xfe7a8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfffffa00, 0x7fff7fff, 0xfffa0000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x007a0000, 0x0000007a, 0x00000000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfffdfffd, 0x7fff7ffd, 0x7fff7ffd, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x000003ff, 0x00000000, 0xe0037fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0f010f01, 0x800ffc01, 0x800ffc01, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0001f1fe, 0x80000001, 0xfff1fffe, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00000003, 0x00008000, 0x00000003, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00fb0f09, 0x80007ffb, 0xc00f0009, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x7f5501ff, 0x807f5555, 0x00017fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfcff00ff, 0x0ffc7fff, 0x80007fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfef8ef00, 0xfffefff8, 0xfeef0000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x03f60083, 0x0003fff6, 0x80000a83, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x1ffe0725, 0x801f1ffe, 0x00070b25, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfffff700, 0x7fff7fff, 0xfff70000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x005c0100, 0x8000025c, 0x00010000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0146ff00, 0x00010046, 0x7fff8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfff9fffe, 0x7ffffff9, 0x7ffffffe, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x1f0266e0, 0x001f0002, 0x66661fe0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfe00031f, 0xfffe0000, 0xc003801f, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0000ff35, 0x00000000, 0x7fff0035, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff00001f, 0x7fff0000, 0x8000011f, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x9c1c010a, 0xd39cc71c, 0x0001000a, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xff070077, 0x7fffc007, 0x0000ff77, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x1efe008f, 0x051efffe, 0x8000ff8f, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xbb03fec0, 0xffbbf803, 0xfffe3fc0, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0002fe00, 0x80000002, 0x3ffe8000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xddffddff, 0xffdd7fff, 0xffdd7fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x00001fff, 0x00008000, 0x801f7fff, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xb6c7fe00, 0x6db6ffc7, 0x3ffe0000, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x0ff800f1, 0x000ffff8, 0x0000fff1, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x1a2c008d, 0x011aff2c, 0x0000ff8d, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x03d00209, 0x0303ffd0, 0x8002d309, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x028bfffd, 0x0002ff8b, 0xffff7ffd, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0x000000fe, 0x00000000, 0x0000fffe, 0x0, 0x0 + dspck_dstio precr.qb.ph, 0xfff90000, 0x7ffffff9, 0x00000000, 0x0, 0x0 + + writemsg "[26] Test precr_sra.ph.w" + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 13 + dspck_tsimm precr_sra.ph.w, 0x00000028, 0x0000ffff, 0x00283a6e, 16 + dspck_tsimm precr_sra.ph.w, 0xffffffc0, 0x7fffffff, 0xffffffc0, 0 + dspck_tsimm precr_sra.ph.w, 0xf0f00000, 0xf0f0f0f0, 0x00000000, 0 + dspck_tsimm precr_sra.ph.w, 0x71c7fffe, 0x38e38e38, 0xfffffff0, 3 + dspck_tsimm precr_sra.ph.w, 0x000fffff, 0x7fffffff, 0xf8000003, 27 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00004aa2, 0x00000010, 31 + dspck_tsimm precr_sra.ph.w, 0x0000fffc, 0x00000004, 0x80000000, 29 + dspck_tsimm precr_sra.ph.w, 0x55558e38, 0x55555555, 0x38e38e38, 0 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffffeb, 0x000019ad, 31 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0xf0000001, 0x00000000, 2 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x0ffffff8, 0x7fffffff, 31 + dspck_tsimm precr_sra.ph.w, 0x1fff1fff, 0x7fffffff, 0x7fffffff, 18 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x7fffffff, 0x00000000, 3 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0xfffffff9, 31 + dspck_tsimm precr_sra.ph.w, 0xdb6d0734, 0xb6db6db6, 0x00073400, 8 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0xfffee2a8, 29 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xfff8c7ef, 0x00000000, 30 + dspck_tsimm precr_sra.ph.w, 0xaa370000, 0xff0daa37, 0x00000000, 0 + dspck_tsimm precr_sra.ph.w, 0x55550000, 0x55555555, 0x80000000, 12 + dspck_tsimm precr_sra.ph.w, 0x92490000, 0x92492492, 0x00000000, 1 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x7fffffff, 0x00000000, 3 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000007, 0x00000000, 30 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x7fffffff, 0x00000000, 31 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0x7fffffff, 0xfffffffd, 6 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xff00ff00, 0x7ffffffb, 31 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffffff, 0x0000245d, 31 + dspck_tsimm precr_sra.ph.w, 0xfffb007f, 0x7ffffffb, 0x8000007f, 0 + dspck_tsimm precr_sra.ph.w, 0xffe5ffff, 0xffffffe5, 0x7fffffff, 0 + dspck_tsimm precr_sra.ph.w, 0x0007ffff, 0x7fffffff, 0xfe942219, 28 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0x7fffffff, 0 + dspck_tsimm precr_sra.ph.w, 0x00ff00ff, 0x000000ff, 0x000000ff, 0 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffff2f, 0x00000000, 31 + dspck_tsimm precr_sra.ph.w, 0x001f0000, 0x8000001f, 0x80000000, 0 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x3ffffffc, 0x7fffffff, 31 + dspck_tsimm precr_sra.ph.w, 0x00002492, 0x80000000, 0x92492492, 0 + dspck_tsimm precr_sra.ph.w, 0xc000f800, 0x80000000, 0xf0000001, 17 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xc71c71c7, 0x07fffffe, 31 + dspck_tsimm precr_sra.ph.w, 0x0000ffa3, 0x80000000, 0xfffffd1d, 3 + dspck_tsimm precr_sra.ph.w, 0xffff0230, 0x7fffffff, 0x00000230, 0 + dspck_tsimm precr_sra.ph.w, 0x0000fffc, 0x00000000, 0x80000000, 29 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000006, 0x7fffffff, 9 + dspck_tsimm precr_sra.ph.w, 0x0002ffff, 0x00000005, 0x7fffffff, 1 + dspck_tsimm precr_sra.ph.w, 0xfffffef5, 0x7fffffff, 0xfffffef5, 0 + dspck_tsimm precr_sra.ph.w, 0x912b5555, 0x0832912b, 0x55555555, 0 + dspck_tsimm precr_sra.ph.w, 0xb4c30002, 0xfd05b4c3, 0x00000002, 0 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x0000000f, 0x7ffffff9, 4 + dspck_tsimm precr_sra.ph.w, 0xff80fff1, 0xffffff80, 0xfffffff1, 0 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x80000000, 0x0000705a, 31 + dspck_tsimm precr_sra.ph.w, 0x0000ff00, 0x00000000, 0xffffff00, 0 + dspck_tsimm precr_sra.ph.w, 0x3af90000, 0xffba75f2, 0x80000000, 1 + dspck_tsimm precr_sra.ph.w, 0x07ffffff, 0x1ffffff0, 0xfffffeae, 18 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xfffffff9, 0x80000000, 10 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000049, 10 + dspck_tsimm precr_sra.ph.w, 0x0000ab83, 0x80000000, 0x000b5706, 1 + dspck_tsimm precr_sra.ph.w, 0xffc0ffc0, 0x80000000, 0x8000007f, 25 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000002, 27 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffffb1, 0x00000015, 31 + dspck_tsimm precr_sra.ph.w, 0xf83d0000, 0x00ddf07a, 0x00000000, 1 + dspck_tsimm precr_sra.ph.w, 0x0000fff8, 0x80000000, 0x3ffffff8, 0 + dspck_tsimm precr_sra.ph.w, 0x0000fffc, 0x00000000, 0x0ffffffc, 0 + dspck_tsimm precr_sra.ph.w, 0x0003ffff, 0xc0000003, 0x7fffffff, 0 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xc0000001, 0x00000000, 31 + dspck_tsimm precr_sra.ph.w, 0xfffc0000, 0xfffffffc, 0x00000000, 0 + dspck_tsimm precr_sra.ph.w, 0xfff9ffff, 0xfffffff9, 0x7fffffff, 0 + dspck_tsimm precr_sra.ph.w, 0xffea3aef, 0xffffffea, 0xffff3aef, 0 + dspck_tsimm precr_sra.ph.w, 0xffff0003, 0xffff4871, 0x19692a52, 27 + dspck_tsimm precr_sra.ph.w, 0xfffe0000, 0xfcb6a83c, 0x00000000, 25 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x3fffffe0, 0x7ffffffc, 31 + dspck_tsimm precr_sra.ph.w, 0xc71caaaa, 0x38e38e38, 0x55555555, 1 + dspck_tsimm precr_sra.ph.w, 0x5e5cfffe, 0x00017971, 0x7ffffffa, 2 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000004, 0x80000000, 6 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x0001114c, 0x000000dd, 27 + dspck_tsimm precr_sra.ph.w, 0x00000001, 0x80000000, 0xf8000003, 1 + dspck_tsimm precr_sra.ph.w, 0xfc6770e9, 0xfffff8cf, 0x3142e1d3, 1 + dspck_tsimm precr_sra.ph.w, 0x9eb0f0f0, 0x00029eb0, 0xf0f0f0f0, 0 + dspck_tsimm precr_sra.ph.w, 0x000bfffe, 0x00000017, 0x7ffffffc, 1 + dspck_tsimm precr_sra.ph.w, 0x78720003, 0xeb027872, 0xf8000003, 0 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffbc1b, 0x33333333, 31 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x0001bfb2, 0x7ffffffa, 31 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x7fffffff, 0x80000000, 2 + dspck_tsimm precr_sra.ph.w, 0xfffffff1, 0x7fffffff, 0xfe67ff8f, 3 + dspck_tsimm precr_sra.ph.w, 0x6666fd7d, 0x66666666, 0xfffffd7d, 0 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000001, 0x0000003f, 6 + dspck_tsimm precr_sra.ph.w, 0xffffb6db, 0x7fffffff, 0xdb6db6db, 0 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x014f24fb, 31 + dspck_tsimm precr_sra.ph.w, 0x6db60000, 0x6db6db6d, 0x80000000, 10 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x0f0f0f0f, 31 + dspck_tsimm precr_sra.ph.w, 0xffc0bb38, 0x7fffffc0, 0x0d50bb38, 0 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xfffffff9, 0x000001ca, 13 + dspck_tsimm precr_sra.ph.w, 0xb152ffff, 0xffff62a4, 0x7fffffff, 1 + dspck_tsimm precr_sra.ph.w, 0x0fffffff, 0x07fffffe, 0x7fffffff, 15 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0x3ffffffe, 0x7ffffffe, 1 + dspck_tsimm precr_sra.ph.w, 0xff920000, 0xffe489b1, 0x0000000b, 14 + dspck_tsimm precr_sra.ph.w, 0x34df7f80, 0x1e9469bf, 0xff00ff00, 1 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x02728de8, 0xffff5c80, 30 + dspck_tsimm precr_sra.ph.w, 0xffff5f0d, 0x7fffffff, 0x00045f0d, 0 + dspck_tsimm precr_sra.ph.w, 0xfffefea8, 0xfffffffe, 0xfffffea8, 0 + dspck_tsimm precr_sra.ph.w, 0x0000fc00, 0x00000000, 0xf0000001, 18 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xff8942a6, 0x7fffffc0, 31 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 31 + dspck_tsimm precr_sra.ph.w, 0x7c470000, 0x0f88e8b9, 0x80000000, 13 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x1ffffffc, 0x00000000, 8 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x7fffffff, 0x7fffffff, 31 + dspck_tsimm precr_sra.ph.w, 0x1249fe20, 0x00001249, 0xfffffe20, 0 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xfffe8e4d, 0x00000007, 29 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xfff8431e, 0xf0000001, 31 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00011d30, 0x000003ea, 30 + dspck_tsimm precr_sra.ph.w, 0xfffefffe, 0x7ffffffa, 0x7ffffff8, 2 + dspck_tsimm precr_sra.ph.w, 0x00003fc0, 0x80000000, 0xff00ff00, 2 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x80000000, 0x7fffffff, 0 + dspck_tsimm precr_sra.ph.w, 0x0028ffe1, 0x0000028e, 0xfffffe18, 4 + dspck_tsimm precr_sra.ph.w, 0x00006b69, 0x80000000, 0x004c6b69, 0 + dspck_tsimm precr_sra.ph.w, 0x00010072, 0xf8000001, 0x00000072, 0 + dspck_tsimm precr_sra.ph.w, 0x5154ffff, 0xfda8aa16, 0xffffff80, 7 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 31 + dspck_tsimm precr_sra.ph.w, 0x003f0001, 0x7fffffff, 0x038f9b87, 25 + dspck_tsimm precr_sra.ph.w, 0x0fff0000, 0x3fffffe0, 0x00000000, 18 + dspck_tsimm precr_sra.ph.w, 0xfffc0000, 0xc000001f, 0x00000000, 28 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xff00ff00, 0x00000006, 31 + dspck_tsimm precr_sra.ph.w, 0xfe40fead, 0xfffffe40, 0xfffffead, 0 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 2 + dspck_tsimm precr_sra.ph.w, 0xfcbc001a, 0xfffff978, 0x00000034, 1 + dspck_tsimm precr_sra.ph.w, 0x2492fffc, 0x24924924, 0x0ffffff8, 1 + dspck_tsimm precr_sra.ph.w, 0x65590000, 0x09f19567, 0xf8000001, 2 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x0004db12, 0x00000000, 31 + dspck_tsimm precr_sra.ph.w, 0x00070007, 0xc0000007, 0xc0000007, 0 + dspck_tsimm precr_sra.ph.w, 0x0000f807, 0x80000000, 0x00ff00ff, 5 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0x7fffffff, 6 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000004, 0x00000004, 3 + dspck_tsimm precr_sra.ph.w, 0x7fff0000, 0x7fffffff, 0x00000003, 16 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xe000000f, 0xe000000f, 31 + dspck_tsimm precr_sra.ph.w, 0xfff0fff0, 0x3ffffff0, 0x3ffffff0, 0 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xffff0000, 0xc0000001, 31 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x0ffffffc, 0x80000000, 31 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x80000000, 0x80000000, 15 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x3ffffffe, 0x00003717, 31 + dspck_tsimm precr_sra.ph.w, 0x00070a24, 0xc0000007, 0x00000a24, 0 + dspck_tsimm precr_sra.ph.w, 0xfffe8529, 0x3ffffffe, 0x019f8529, 0 + dspck_tsimm precr_sra.ph.w, 0xfffbff80, 0xfffffffb, 0x7fffff80, 0 + dspck_tsimm precr_sra.ph.w, 0x38e30000, 0x38e38e38, 0xfc000001, 10 + dspck_tsimm precr_sra.ph.w, 0xfffd3127, 0xfffffffa, 0xd986624f, 1 + dspck_tsimm precr_sra.ph.w, 0xfff3ffff, 0xffffff33, 0x1ffffffe, 4 + dspck_tsimm precr_sra.ph.w, 0xbbf30003, 0x0003bbf3, 0xf8000003, 0 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffffe3, 0x00000000, 12 + dspck_tsimm precr_sra.ph.w, 0x9249ffff, 0x92492492, 0xfffffffd, 7 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0x80000000, 0xfffffffd, 31 + dspck_tsimm precr_sra.ph.w, 0x0000fff9, 0x001540d2, 0x99999999, 28 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0x80000000, 0x8000000f, 31 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xfc889cce, 0x80000000, 31 + dspck_tsimm precr_sra.ph.w, 0xffea0000, 0xffffff52, 0x80000000, 3 + dspck_tsimm precr_sra.ph.w, 0x0f0f0000, 0x0f0f0f0f, 0x80000000, 0 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x7fffffff, 0x00000000, 15 + dspck_tsimm precr_sra.ph.w, 0x38060000, 0xff13806f, 0x80000000, 4 + dspck_tsimm precr_sra.ph.w, 0xffff8d70, 0x0000ffff, 0x00008d70, 0 + dspck_tsimm precr_sra.ph.w, 0x0000fffc, 0x000000c9, 0xe000000f, 27 + dspck_tsimm precr_sra.ph.w, 0x0000f000, 0x00000002, 0x8000001f, 19 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x7fffffff, 31 + dspck_tsimm precr_sra.ph.w, 0x8e38003f, 0x38e38e38, 0x0000003f, 0 + dspck_tsimm precr_sra.ph.w, 0x00b80000, 0x000000b8, 0x00000000, 0 + dspck_tsimm precr_sra.ph.w, 0xffc00000, 0x80000004, 0x00000002, 25 + dspck_tsimm precr_sra.ph.w, 0xfffffd55, 0xfffd47dc, 0xaaaaaaaa, 21 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 4 + dspck_tsimm precr_sra.ph.w, 0x837d0000, 0xfffd06fb, 0x00000000, 1 + dspck_tsimm precr_sra.ph.w, 0x00002d30, 0x00000000, 0x00016985, 3 + dspck_tsimm precr_sra.ph.w, 0x000f0007, 0x0000000f, 0x00000007, 0 + dspck_tsimm precr_sra.ph.w, 0x00010000, 0x00000001, 0x00000000, 0 + dspck_tsimm precr_sra.ph.w, 0xff800000, 0x80000000, 0x0000007f, 24 + dspck_tsimm precr_sra.ph.w, 0x0f0f0000, 0xf0f0f0f0, 0x80000000, 4 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x0000ffff, 0xffe2a7e0, 31 + dspck_tsimm precr_sra.ph.w, 0x00003333, 0x00000000, 0x66666666, 17 + dspck_tsimm precr_sra.ph.w, 0xfbe9fbe9, 0xfffffbe9, 0xfffffbe9, 0 + dspck_tsimm precr_sra.ph.w, 0xffccffde, 0xffffffcc, 0xffffffde, 0 + dspck_tsimm precr_sra.ph.w, 0x0000001f, 0x00000000, 0x8000001f, 0 + dspck_tsimm precr_sra.ph.w, 0x000046ab, 0x80000001, 0x00023559, 3 + dspck_tsimm precr_sra.ph.w, 0xffff0007, 0x7fffffff, 0xe000000f, 1 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x7fffffff, 0xffffffc3, 31 + dspck_tsimm precr_sra.ph.w, 0xffff00ef, 0x7fffffff, 0x000003be, 2 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0x7ffffffe, 0x7fffffff, 1 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000007, 0x00000000, 13 + dspck_tsimm precr_sra.ph.w, 0x0001ffff, 0xf0000001, 0x7fffffff, 0 + dspck_tsimm precr_sra.ph.w, 0x00460046, 0x00000235, 0x00000235, 3 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffffe1, 0x80000003, 9 + dspck_tsimm precr_sra.ph.w, 0xfffffff0, 0xfffffffe, 0xffffffe0, 1 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x7ffffff8, 0x49249249, 31 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x7fffffff, 31 + dspck_tsimm precr_sra.ph.w, 0xfffffff0, 0xffffffe0, 0x80000000, 27 + dspck_tsimm precr_sra.ph.w, 0xff80fff2, 0x7fffff80, 0xfffffff2, 0 + dspck_tsimm precr_sra.ph.w, 0x001fff16, 0x0000001f, 0xffffff16, 0 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0xffffffe0, 17 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0x7fffffff, 3 + dspck_tsimm precr_sra.ph.w, 0xfff8ffff, 0x0ffffff8, 0x7fffffff, 0 + dspck_tsimm precr_sra.ph.w, 0x0000de5a, 0x00000000, 0xff79698f, 10 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xffffffd1, 0xfffffff0, 8 + dspck_tsimm precr_sra.ph.w, 0x00013908, 0x00000001, 0xfee43908, 0 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xfffffff8, 0xfded729c, 31 + dspck_tsimm precr_sra.ph.w, 0x0000fe72, 0x00000000, 0xce5a1cb7, 21 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 0 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffff00, 0x7fffffff, 31 + dspck_tsimm precr_sra.ph.w, 0x72defff8, 0x003a72de, 0x3ffffff8, 0 + dspck_tsimm precr_sra.ph.w, 0x0000dccd, 0x00000000, 0x1bdccd6d, 8 + dspck_tsimm precr_sra.ph.w, 0x98880000, 0x01e13110, 0x80000000, 1 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x7fffffff, 0x80000000, 0 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000007, 0x80000000, 31 + dspck_tsimm precr_sra.ph.w, 0xfffaffff, 0x7ffffffa, 0x7fffffff, 0 + dspck_tsimm precr_sra.ph.w, 0xffff0001, 0xffffffff, 0x00000006, 2 + dspck_tsimm precr_sra.ph.w, 0x0000099e, 0x00000005, 0xeeb099ef, 4 + dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffffff, 0x80000000, 0 + dspck_tsimm precr_sra.ph.w, 0xfffee60a, 0xfffffc46, 0xffcc1534, 9 + dspck_tsimm precr_sra.ph.w, 0xfffeffff, 0x80000000, 0xc000000f, 30 + dspck_tsimm precr_sra.ph.w, 0xff000000, 0xffffff00, 0x00000000, 0 + dspck_tsimm precr_sra.ph.w, 0x00070000, 0x00000007, 0x80000000, 0 + dspck_tsimm precr_sra.ph.w, 0xffef0000, 0xfffffefa, 0x80000000, 4 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x0000081f, 0x00000007, 31 + dspck_tsimm precr_sra.ph.w, 0x486effff, 0x000d21b8, 0x7fffffff, 2 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x7fffffff, 0x99999999, 31 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0x7fffffff, 7 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x80000000, 14 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 0 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x0ffffffe, 0x00000000, 31 + dspck_tsimm precr_sra.ph.w, 0x000000ff, 0x80000000, 0x000000ff, 0 + dspck_tsimm precr_sra.ph.w, 0xff800039, 0x80000000, 0x3939e9c0, 24 + dspck_tsimm precr_sra.ph.w, 0x00000001, 0x1ffffffe, 0x7fffffff, 30 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xffffffff, 0xfffffd61, 31 + dspck_tsimm precr_sra.ph.w, 0x00010001, 0x00000688, 0x00000688, 10 + dspck_tsimm precr_sra.ph.w, 0xb6db1c71, 0xdb6db6db, 0x8e38e38e, 3 + dspck_tsimm precr_sra.ph.w, 0x00679999, 0x000000cf, 0x33333333, 1 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 2 + dspck_tsimm precr_sra.ph.w, 0x0034ffff, 0x000068d6, 0xffffff5d, 9 + dspck_tsimm precr_sra.ph.w, 0x0000fc00, 0x00000000, 0x80000000, 21 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x80000000, 0x00000000, 8 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x7fffffff, 0x7fffffff, 31 + dspck_tsimm precr_sra.ph.w, 0x000001a6, 0x80000000, 0x0034dff6, 13 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xffff389e, 0xffffffff, 31 + dspck_tsimm precr_sra.ph.w, 0x00007b11, 0x00000000, 0xe734f622, 1 + dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x007c388e, 0xffff2106, 25 + dspck_tsimm precr_sra.ph.w, 0x00000000, 0x80000000, 0x00000000, 0 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0x7fffffff, 0x7fffffc0, 12 + dspck_tsimm precr_sra.ph.w, 0xffff0057, 0x7fffffff, 0x00000057, 0 + dspck_tsimm precr_sra.ph.w, 0x09240000, 0x24924924, 0x00000000, 18 + dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xfffffffe, 0x3ffffff8, 6 + + writemsg "[27] Test precr_sra_r.ph.w" + dspck_tsimm precr_sra_r.ph.w, 0xffe0ffe0, 0x3fffffe0, 0x3fffffe0, 0 + dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0xc0000007, 0x80000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0xfff80001, 0x7fffffc0, 0x00000004, 3 + dspck_tsimm precr_sra_r.ph.w, 0x71c70000, 0xc71c71c7, 0x00000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000001, 0x000000ff, 0x7ffffffe, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00008e89, 0x00000002, 0x0118e88a, 4 + dspck_tsimm precr_sra_r.ph.w, 0xffffffff, 0x80000007, 0x80000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0x0000aaab, 0xfffffffb, 0x55555555, 13 + dspck_tsimm precr_sra_r.ph.w, 0x00020000, 0x0000007f, 0xffffffec, 6 + dspck_tsimm precr_sra_r.ph.w, 0x0000fffe, 0x00000000, 0x7ffffffc, 1 + dspck_tsimm precr_sra_r.ph.w, 0x0000fb86, 0x00000000, 0xfffffb86, 0 + dspck_tsimm precr_sra_r.ph.w, 0x7a02ff61, 0xfffe7a02, 0xffffff61, 0 + dspck_tsimm precr_sra_r.ph.w, 0xff48ff48, 0xffffff48, 0xffffff48, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffcea3, 0x00000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0x9cc70000, 0xffa731b1, 0x1ffffffc, 6 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0xc0000007, 7 + dspck_tsimm precr_sra_r.ph.w, 0xf0000000, 0x80000000, 0x000000ff, 19 + dspck_tsimm precr_sra_r.ph.w, 0xfff00010, 0x80000000, 0x7fffffc0, 27 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0x00000007, 31 + dspck_tsimm precr_sra_r.ph.w, 0x8e390000, 0x38e38e38, 0x7fffffff, 6 + dspck_tsimm precr_sra_r.ph.w, 0xfffffff9, 0x7fffffff, 0xfffffff9, 0 + dspck_tsimm precr_sra_r.ph.w, 0xfffe0000, 0x80000000, 0x0000007f, 30 + dspck_tsimm precr_sra_r.ph.w, 0x714dbe05, 0xffbee29a, 0x067b7c09, 1 + dspck_tsimm precr_sra_r.ph.w, 0xffffffff, 0x7fffffff, 0x7fffffff, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00109996, 0x0000001f, 0xfff1332b, 1 + dspck_tsimm precr_sra_r.ph.w, 0xcccc11ce, 0xcccccccc, 0x000011ce, 0 + dspck_tsimm precr_sra_r.ph.w, 0x645343ef, 0x0000c8a6, 0x27ca87de, 1 + dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0x7fffffff, 0xffffffe5, 5 + dspck_tsimm precr_sra_r.ph.w, 0xe02b0000, 0x00270156, 0x80000000, 3 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7ffffffc, 0x00000000, 8 + dspck_tsimm precr_sra_r.ph.w, 0x80008000, 0x3ffffffc, 0x3ffffff8, 15 + dspck_tsimm precr_sra_r.ph.w, 0xfffe7d97, 0x07fffffe, 0x0fa27d97, 0 + dspck_tsimm precr_sra_r.ph.w, 0xfff00002, 0x7fffffe0, 0xc0000003, 1 + dspck_tsimm precr_sra_r.ph.w, 0x00000001, 0x00000004, 0x71c71c71, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x7ffffff9, 0x00000288, 31 + dspck_tsimm precr_sra_r.ph.w, 0x87881ce0, 0x0f0f0f0f, 0x024839bf, 1 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x80000000, 6 + dspck_tsimm precr_sra_r.ph.w, 0xfffe0001, 0x3ffffffe, 0x80000001, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0xff8e97bb, 31 + dspck_tsimm precr_sra_r.ph.w, 0xffff0001, 0x80000000, 0x7fffffff, 31 + dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000000, 0xfffffeae, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x7fffff80, 13 + dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000000, 0xc720a895, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xfffffffa, 0x7fffffff, 7 + dspck_tsimm precr_sra_r.ph.w, 0x03dcf706, 0x0000f6f9, 0xfffdc18d, 6 + dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x7fffffff, 0x80000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xfffe262b, 0xfffffa76, 24 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x80000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0xffc10000, 0xffffc0e6, 0x0ffffffc, 8 + dspck_tsimm precr_sra_r.ph.w, 0x00040004, 0x00000004, 0x00000004, 0 + dspck_tsimm precr_sra_r.ph.w, 0xfff20000, 0x92492492, 0x000000c9, 27 + dspck_tsimm precr_sra_r.ph.w, 0x0000999a, 0xffffffb7, 0x99999999, 12 + dspck_tsimm precr_sra_r.ph.w, 0x00010002, 0xf0000007, 0xe000000f, 3 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x000016ca, 0x00000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0x096f0000, 0x00004b75, 0x00000001, 3 + dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x7fffffff, 0xc71c71c7, 31 + dspck_tsimm precr_sra_r.ph.w, 0xa80cfe4e, 0xffd4a80c, 0xfffffe4e, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffffff, 0x7fffffff, 8 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000b61, 0xe38e38e3, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x00000003, 3 + dspck_tsimm precr_sra_r.ph.w, 0x00060000, 0x00000059, 0xf8000003, 4 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x8000001f, 0x07fffffc, 10 + dspck_tsimm precr_sra_r.ph.w, 0xb4ef0000, 0x03769de4, 0x00000000, 5 + dspck_tsimm precr_sra_r.ph.w, 0x000001a1, 0x80000000, 0x000001a1, 0 + dspck_tsimm precr_sra_r.ph.w, 0x0000fffd, 0x00000001, 0xffffffe5, 3 + dspck_tsimm precr_sra_r.ph.w, 0xfc000000, 0x80000000, 0x00000000, 21 + dspck_tsimm precr_sra_r.ph.w, 0x00000008, 0x7fffffff, 0x0000001f, 2 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7ffffffa, 0x7ffffffc, 6 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x0f0f0f0f, 0x00000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x00000001, 0x00000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x7fffffff, 0xfffeb397, 31 + dspck_tsimm precr_sra_r.ph.w, 0x66660000, 0x66666666, 0x00000000, 16 + dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x92492492, 0x00000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0xe0000000, 0xffff0000, 0x07fffffe, 3 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xc000000f, 0xdb6db6db, 31 + dspck_tsimm precr_sra_r.ph.w, 0xffe00000, 0xffffffe0, 0x00000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0xfff89999, 0x0ffffff8, 0x99999999, 0 + dspck_tsimm precr_sra_r.ph.w, 0x0000fffd, 0x00000002, 0xffffa3b3, 13 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x3fffffe0, 0x3fffffe0, 31 + dspck_tsimm precr_sra_r.ph.w, 0xf5ec0003, 0xfffff5ec, 0xf0000003, 0 + dspck_tsimm precr_sra_r.ph.w, 0x676d0000, 0x0002676d, 0x00000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00010001, 0x7fffffff, 0x7fffffff, 31 + dspck_tsimm precr_sra_r.ph.w, 0x0000fffb, 0x7fffffff, 0xffffffec, 2 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xf8649518, 0x00000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000004, 0x00000000, 8 + dspck_tsimm precr_sra_r.ph.w, 0xe1e2db6e, 0xf0f0f0f0, 0xdb6db6db, 7 + dspck_tsimm precr_sra_r.ph.w, 0x0003fff8, 0x00000003, 0xfffffff8, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000003, 0x80000000, 0x80000006, 1 + dspck_tsimm precr_sra_r.ph.w, 0x0001fffe, 0x80000002, 0xfffffffb, 1 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x1ffffff8, 0xe000000f, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0xffffffff, 1 + dspck_tsimm precr_sra_r.ph.w, 0xfff80000, 0x3ffffff0, 0x7fffffff, 1 + dspck_tsimm precr_sra_r.ph.w, 0x000038e4, 0x00000000, 0xc71c71c7, 1 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x00000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00002492, 0x00000000, 0x49249249, 5 + dspck_tsimm precr_sra_r.ph.w, 0x002d0000, 0x00005ae8, 0xfffffff0, 9 + dspck_tsimm precr_sra_r.ph.w, 0xffae0000, 0xfffffd6e, 0x00000000, 3 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x7fffffff, 5 + dspck_tsimm precr_sra_r.ph.w, 0x80000000, 0xf0000001, 0x00000273, 13 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0x00000000, 1 + dspck_tsimm precr_sra_r.ph.w, 0x55550a42, 0x55555555, 0x07c29079, 6 + dspck_tsimm precr_sra_r.ph.w, 0xfb93fffc, 0xfffffb93, 0xfffffffc, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xff00ff00, 0xe76358a9, 30 + dspck_tsimm precr_sra_r.ph.w, 0xfffeffff, 0x80000000, 0xc000000f, 30 + dspck_tsimm precr_sra_r.ph.w, 0x00000002, 0xffffffff, 0x8000000f, 3 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7ffffff9, 0x7ffffffa, 8 + dspck_tsimm precr_sra_r.ph.w, 0xe3d1fff8, 0xffdfe3d1, 0x7ffffff8, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffe407, 0xfffffffe, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000320, 0xfffffff8, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000d37, 0xfffffff9, 0x0034dcb6, 10 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x00000000, 8 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000035, 0x00000000, 8 + dspck_tsimm precr_sra_r.ph.w, 0x0000fff8, 0x00000000, 0x3ffffff0, 1 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x3ffffffc, 0x00000000, 10 + dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0xffffebc6, 0x80000000, 12 + dspck_tsimm precr_sra_r.ph.w, 0x000038e3, 0x00000000, 0xe38e38e3, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00010001, 0x7ffffff0, 0x7fffffff, 31 + dspck_tsimm precr_sra_r.ph.w, 0xeb0f8e39, 0x00075875, 0xc71c71c7, 3 + dspck_tsimm precr_sra_r.ph.w, 0x00005ae3, 0x00000000, 0x00005ae3, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x0000774b, 0x0000774b, 19 + dspck_tsimm precr_sra_r.ph.w, 0x0223fffc, 0x00000446, 0x1ffffff8, 1 + dspck_tsimm precr_sra_r.ph.w, 0x00030000, 0x80000003, 0x00000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0x00000000, 6 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffc3b4, 0x00000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xff00ff00, 0x00018f10, 27 + dspck_tsimm precr_sra_r.ph.w, 0x150b1f10, 0x0010a85b, 0x0000f87d, 3 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x0000006d, 0x00033da5, 31 + dspck_tsimm precr_sra_r.ph.w, 0x002cfe00, 0x0ae3bff1, 0x80000000, 22 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffffff, 0x00000000, 24 + dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0xe0000001, 0x00000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0x80000007, 0xffffe93d, 13 + dspck_tsimm precr_sra_r.ph.w, 0x0000fffe, 0xffffffff, 0xffffffe0, 4 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x7fffffff, 2 + dspck_tsimm precr_sra_r.ph.w, 0xf7ebf7eb, 0x0003f7eb, 0x0003f7eb, 0 + dspck_tsimm precr_sra_r.ph.w, 0xe45c003f, 0xffcce45c, 0x0000003f, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000001, 0xfd467217, 0x7fffffff, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00074f22, 0xf0000007, 0xed2e4f22, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x0000005c, 0x7fffffff, 6 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0xf3f39787, 31 + dspck_tsimm precr_sra_r.ph.w, 0xffffffff, 0xfffffffa, 0xfffffffa, 3 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffffc0, 0x80000000, 9 + dspck_tsimm precr_sra_r.ph.w, 0x8a5d0000, 0x007c8a5d, 0x00000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000003, 0xfffea149, 31 + dspck_tsimm precr_sra_r.ph.w, 0xfffffff0, 0x7fffffff, 0xfffffff0, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x00000000, 3 + dspck_tsimm precr_sra_r.ph.w, 0xffffffff, 0x80000000, 0x80000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0xffeb0fdb, 0xffffffeb, 0x01d00fdb, 0 + dspck_tsimm precr_sra_r.ph.w, 0x0000fe1d, 0x00000000, 0xfffff874, 2 + dspck_tsimm precr_sra_r.ph.w, 0xfffed715, 0x1ffffffc, 0xe4c3ae2a, 1 + dspck_tsimm precr_sra_r.ph.w, 0xcc260000, 0x03e61329, 0xc000001f, 7 + dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000000, 0x0001cdbc, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00030000, 0xe0000003, 0x00000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0x0005b8cd, 0x80000005, 0x0014b8cd, 0 + dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0x00000000, 0xf8000003, 27 + dspck_tsimm precr_sra_r.ph.w, 0xfff003d2, 0xfffffff0, 0x000003d2, 0 + dspck_tsimm precr_sra_r.ph.w, 0xffe00000, 0x7fffffc0, 0x00000000, 1 + dspck_tsimm precr_sra_r.ph.w, 0xfffcfffc, 0x7ffffff0, 0x1ffffff0, 2 + dspck_tsimm precr_sra_r.ph.w, 0x00000040, 0xffffffa3, 0x7fffffff, 25 + dspck_tsimm precr_sra_r.ph.w, 0xfab9005a, 0xfffffab9, 0x0000005a, 0 + dspck_tsimm precr_sra_r.ph.w, 0xe0000000, 0x80000001, 0x00000000, 18 + dspck_tsimm precr_sra_r.ph.w, 0x978676f6, 0xffa65e16, 0x0001dbd7, 2 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x02c51b17, 0x02c51b17, 31 + dspck_tsimm precr_sra_r.ph.w, 0x948e0000, 0xff14a470, 0x80000000, 3 + dspck_tsimm precr_sra_r.ph.w, 0xc0000000, 0xe0000007, 0x8000003f, 15 + dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000000, 0x00000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000004, 0x80000000, 0x80000004, 0 + dspck_tsimm precr_sra_r.ph.w, 0x0000fffc, 0x00000000, 0x7ffffffc, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7ffffffb, 0x8000003f, 12 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x0002cce6, 0x07fffffc, 31 + dspck_tsimm precr_sra_r.ph.w, 0xf299aa30, 0xfffff299, 0xfffeaa30, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000002, 0xe0000007, 0x00000060, 6 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x00000000, 3 + dspck_tsimm precr_sra_r.ph.w, 0xfe000000, 0x80000000, 0x0002471b, 22 + dspck_tsimm precr_sra_r.ph.w, 0x24920000, 0x92492492, 0xffffffff, 3 + dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000000, 0x00000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0x2ba5fffc, 0xfff82ba5, 0x07fffffc, 0 + dspck_tsimm precr_sra_r.ph.w, 0xff00356e, 0xffffff00, 0x0121356e, 0 + dspck_tsimm precr_sra_r.ph.w, 0x66663c60, 0x66666666, 0xd0c23c60, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00002492, 0x00000001, 0x92492492, 15 + dspck_tsimm precr_sra_r.ph.w, 0xffbfffff, 0xffffffbf, 0x7fffffff, 0 + dspck_tsimm precr_sra_r.ph.w, 0xc7450008, 0xffde3a28, 0x8000003f, 3 + dspck_tsimm precr_sra_r.ph.w, 0x0000b6db, 0x7fffffff, 0xdb6db6db, 3 + dspck_tsimm precr_sra_r.ph.w, 0xc0000000, 0x80000000, 0x00000000, 17 + dspck_tsimm precr_sra_r.ph.w, 0x00ad0000, 0x000acd12, 0x00000005, 12 + dspck_tsimm precr_sra_r.ph.w, 0xbdee0000, 0xff9d7bdc, 0x00000000, 1 + dspck_tsimm precr_sra_r.ph.w, 0x001b3333, 0x0000006b, 0xcccccccc, 2 + dspck_tsimm precr_sra_r.ph.w, 0x81480000, 0x0140a402, 0xe000000f, 7 + dspck_tsimm precr_sra_r.ph.w, 0x0503ffe0, 0x00a05c2c, 0xfffc0bb1, 13 + dspck_tsimm precr_sra_r.ph.w, 0x830c0001, 0x007c185d, 0xe0000007, 3 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0xfbae5c82, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x7fffffff, 2 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00003423, 0x00007446, 30 + dspck_tsimm precr_sra_r.ph.w, 0x0000001f, 0x00000000, 0x8000001f, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000002, 0x00000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0xffb7664a, 0x0928ffb7, 0xff89664a, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x0ffffffe, 8 + dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x7fffffff, 0x1ffffffc, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00040000, 0x7fffffff, 0xffffffe0, 29 + dspck_tsimm precr_sra_r.ph.w, 0x0000fff7, 0x00000815, 0xf7723f4f, 24 + dspck_tsimm precr_sra_r.ph.w, 0x00fffffe, 0x00ff00ff, 0x7ffffffe, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x80000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000001, 0x00000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x1ffffffe, 6 + dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0xff2e1e63, 0x80000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0x0000fffd, 0x7fffffff, 0xfffffffa, 1 + dspck_tsimm precr_sra_r.ph.w, 0x6db70000, 0xdb6db6db, 0x80000000, 11 + dspck_tsimm precr_sra_r.ph.w, 0x141f0001, 0xff00507d, 0x00000002, 2 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x00000000, 1 + dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0x80000000, 0x7fffffff, 0 + dspck_tsimm precr_sra_r.ph.w, 0x2e9d0000, 0xfff2e9cd, 0x00000000, 4 + dspck_tsimm precr_sra_r.ph.w, 0xffd8fc00, 0xfb087aa5, 0x80000000, 21 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x33333333, 0xffffe715, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x7fffffff, 3 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0xe000000f, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00033c3c, 0x0000000d, 0xf0f0f0f0, 2 + dspck_tsimm precr_sra_r.ph.w, 0xfff8ffff, 0x3ffffff8, 0x7fffffff, 0 + dspck_tsimm precr_sra_r.ph.w, 0xff800000, 0x8000001f, 0xffffff00, 24 + dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0x00000000, 0x80000000, 31 + dspck_tsimm precr_sra_r.ph.w, 0x0000ffb7, 0x00000000, 0xffdbb2cf, 15 + dspck_tsimm precr_sra_r.ph.w, 0x2c03d9c7, 0x0002c033, 0xf39d9c77, 4 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffffff, 0xffffff2b, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffffff, 0x07fffffe, 11 + dspck_tsimm precr_sra_r.ph.w, 0x40000000, 0x7fffffe0, 0xffff0000, 17 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x00000003, 13 + dspck_tsimm precr_sra_r.ph.w, 0x00010001, 0x7fffffff, 0x7fffffff, 31 + dspck_tsimm precr_sra_r.ph.w, 0x0000b9b9, 0x00000002, 0xff1dcdc4, 3 + dspck_tsimm precr_sra_r.ph.w, 0x000f0000, 0x0000000f, 0x00000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x0000003f, 0x00000000, 6 + dspck_tsimm precr_sra_r.ph.w, 0xfff801e6, 0x7ffffff8, 0x000001e6, 0 + dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000000, 0xffffffe4, 31 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x00000000, 1 + dspck_tsimm precr_sra_r.ph.w, 0x00000013, 0x3ffffff0, 0x000004cf, 6 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffffea, 0xc0000003, 7 + dspck_tsimm precr_sra_r.ph.w, 0x000034c6, 0x80000000, 0xffff34c6, 0 + dspck_tsimm precr_sra_r.ph.w, 0xfffefe02, 0xfffffec1, 0x00ff00ff, 7 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0x80000000, 0 + dspck_tsimm precr_sra_r.ph.w, 0xe000e000, 0x80000000, 0x80000000, 18 + dspck_tsimm precr_sra_r.ph.w, 0x9b7fffff, 0x005c9b7f, 0x7fffffff, 0 + dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x8000003f, 0x80000003, 14 + dspck_tsimm precr_sra_r.ph.w, 0x0000bd45, 0x80000000, 0x1c7b7a8a, 1 + dspck_tsimm precr_sra_r.ph.w, 0xffd70000, 0xffffffad, 0x00000000, 1 + + writemsg "[28] Test prepend" + dspck_tsimm prepend, 0x5ffff0df, 0xffff86fc, 0xfffffe02, 3 + dspck_tsimm prepend, 0x00000000, 0x00000000, 0xfffffe06, 0 + dspck_tsimm prepend, 0x0fffffff, 0x7fffffff, 0x80000000, 3 + dspck_tsimm prepend, 0x80000000, 0x80000000, 0x00000000, 0 + dspck_tsimm prepend, 0x00000000, 0x00000000, 0xffffff23, 0 + dspck_tsimm prepend, 0x01feed28, 0xff76947a, 0x00000000, 7 + dspck_tsimm prepend, 0x00000035, 0x00000035, 0xffffffc0, 0 + dspck_tsimm prepend, 0x80000000, 0x80000000, 0x01130b02, 0 + dspck_tsimm prepend, 0x7ffffffe, 0x7ffffffe, 0xc0000001, 0 + dspck_tsimm prepend, 0x7fffffff, 0x7fffffff, 0x7fffffff, 0 + dspck_tsimm prepend, 0x1a75980e, 0x1a75980e, 0x1b4c3c1e, 0 + dspck_tsimm prepend, 0x7fffffff, 0xffffffff, 0x7ffffffc, 1 + dspck_tsimm prepend, 0x00060000, 0xc0000003, 0x00000000, 13 + dspck_tsimm prepend, 0x7fffffff, 0xfffffffe, 0x00000000, 1 + dspck_tsimm prepend, 0xfffffffe, 0x1ffffffe, 0x7fffffff, 31 + dspck_tsimm prepend, 0x00000000, 0x00000000, 0x00000000, 0 + dspck_tsimm prepend, 0xfffffb50, 0x7fffffff, 0xfffffda8, 31 + dspck_tsimm prepend, 0x6b2c0000, 0xc0000007, 0xfffff6b2, 12 + dspck_tsimm prepend, 0x0015491f, 0x002a923e, 0x1ffffff8, 1 + dspck_tsimm prepend, 0x00000021, 0xfffffee4, 0x00000010, 31 + dspck_tsimm prepend, 0xf6ecdac9, 0xf8034c6b, 0xfb766d64, 31 + dspck_tsimm prepend, 0xb7ffffff, 0x7ffffffb, 0x0000002b, 4 + dspck_tsimm prepend, 0xfffffffa, 0xfffffffa, 0x7fffffff, 0 + dspck_tsimm prepend, 0xffaaaaaa, 0x55555555, 0x7fffffff, 9 + dspck_tsimm prepend, 0x00016000, 0x80000000, 0x80000005, 18 + dspck_tsimm prepend, 0x7fffffff, 0x7fffffff, 0x000004fc, 0 + dspck_tsimm prepend, 0x00000000, 0x0035d189, 0x80000000, 31 + dspck_tsimm prepend, 0x8000007f, 0x8000007f, 0xff00ff00, 0 + dspck_tsimm prepend, 0xaf600000, 0x00000000, 0x03557af6, 12 + dspck_tsimm prepend, 0x000000e3, 0x000000e3, 0x0008f4ab, 0 + dspck_tsimm prepend, 0x00000000, 0x00000000, 0x00000000, 2 + dspck_tsimm prepend, 0x61e1e1e1, 0x0f0f0f0f, 0x00000003, 3 + dspck_tsimm prepend, 0x002559bf, 0x002559bf, 0xdb6db6db, 0 + dspck_tsimm prepend, 0x19999999, 0x66666666, 0x7fffff80, 2 + dspck_tsimm prepend, 0xe85fb7d6, 0x80000000, 0xfa17edf5, 30 + dspck_tsimm prepend, 0x6b800000, 0xc0000001, 0x00003cb5, 7 + dspck_tsimm prepend, 0xc71c71c7, 0xc71c71c7, 0x00000335, 0 + dspck_tsimm prepend, 0x8000001f, 0x8000001f, 0xfffffef3, 0 + dspck_tsimm prepend, 0x00200000, 0x00000006, 0x80000002, 12 + dspck_tsimm prepend, 0x50c7ffff, 0xffffffd5, 0xf8c02863, 15 + dspck_tsimm prepend, 0x0008fd99, 0x33299df8, 0x000011fb, 25 + dspck_tsimm prepend, 0x00f00000, 0x00000000, 0xc000000f, 12 + dspck_tsimm prepend, 0x00000000, 0x00000001, 0x00000000, 31 + dspck_tsimm prepend, 0xebffffff, 0x7ffffffb, 0x7ffffffd, 5 + dspck_tsimm prepend, 0xffffffc0, 0x80000000, 0x7fffffff, 25 + dspck_tsimm prepend, 0xc0ffffff, 0x0ffffffc, 0x0ffffffc, 4 + dspck_tsimm prepend, 0x8000003f, 0xfffffe6a, 0xc000001f, 31 + dspck_tsimm prepend, 0x7face03a, 0xfeb380e9, 0x7ffffffd, 2 + dspck_tsimm prepend, 0x3ffffffd, 0x7ffffffa, 0x00000000, 1 + dspck_tsimm prepend, 0xe0000003, 0x8000000f, 0xdb6db6db, 2 + dspck_tsimm prepend, 0x001548ff, 0xfffd232e, 0x00001548, 24 + dspck_tsimm prepend, 0x6000000f, 0xc000001f, 0x00000000, 1 + dspck_tsimm prepend, 0x000000cc, 0x33333333, 0x00000000, 22 + dspck_tsimm prepend, 0x00000004, 0x0000db1b, 0xc0000001, 30 + dspck_tsimm prepend, 0x01ffffff, 0xffffffff, 0xe0000007, 10 + dspck_tsimm prepend, 0x80000000, 0x00000000, 0xffffff5f, 1 + dspck_tsimm prepend, 0x0000007e, 0x0d2efcd1, 0x8000003f, 31 + dspck_tsimm prepend, 0xda000000, 0x00000000, 0xffffff6d, 7 + dspck_tsimm prepend, 0x00040d38, 0x00081a70, 0xe4606c5a, 1 + dspck_tsimm prepend, 0xc0000007, 0x80000000, 0xe0000003, 31 + dspck_tsimm prepend, 0x00000000, 0x00000000, 0xfff9ab12, 0 + dspck_tsimm prepend, 0xffffffff, 0x80000000, 0x7fffffff, 31 + dspck_tsimm prepend, 0x00007fff, 0xffffd894, 0x00000000, 17 + dspck_tsimm prepend, 0xffed5610, 0x0ffffffe, 0xfff6ab08, 31 + dspck_tsimm prepend, 0x00000002, 0x80000000, 0x00000000, 30 + dspck_tsimm prepend, 0x0019ffff, 0x7fffffff, 0x00000006, 14 + dspck_tsimm prepend, 0xe0000000, 0x80000000, 0x7fffffff, 2 + dspck_tsimm prepend, 0x003ffffc, 0xfffff23b, 0x00000000, 10 + dspck_tsimm prepend, 0x00000001, 0x80000000, 0x80000000, 31 + dspck_tsimm prepend, 0x00000011, 0x00000011, 0x7fffffff, 0 + dspck_tsimm prepend, 0x7ffffffd, 0xfffffffa, 0x1c71c71c, 1 + dspck_tsimm prepend, 0xe6666666, 0xcccccccc, 0xf8000001, 1 + dspck_tsimm prepend, 0x00000001, 0x80000000, 0x80000000, 31 + dspck_tsimm prepend, 0xfdb739b8, 0xfdb739b8, 0x000000e1, 0 + dspck_tsimm prepend, 0x00000fff, 0x7fffffff, 0x80000000, 19 + dspck_tsimm prepend, 0x7ffff90b, 0xfffff216, 0x80000000, 1 + dspck_tsimm prepend, 0x00000000, 0x3ffffff8, 0x00000000, 31 + dspck_tsimm prepend, 0xfea7a4f9, 0xfea7a4f9, 0xfffffffe, 0 + dspck_tsimm prepend, 0xfffffffe, 0x7fffffff, 0x7fffffff, 31 + dspck_tsimm prepend, 0x0000033f, 0x7fffffff, 0x00000006, 25 + dspck_tsimm prepend, 0x8e7fffff, 0x7fffffff, 0x8e38e38e, 8 + dspck_tsimm prepend, 0xfffffffc, 0x00000000, 0xfffffffe, 31 + dspck_tsimm prepend, 0x7fffffff, 0x7fffffff, 0x00000000, 0 + dspck_tsimm prepend, 0xffffff4e, 0x80000000, 0xffffffd3, 30 + dspck_tsimm prepend, 0xf0000001, 0xf0000001, 0x00000006, 0 + dspck_tsimm prepend, 0x000017ff, 0xfffffff8, 0x00000002, 21 + dspck_tsimm prepend, 0x49666666, 0x66666666, 0x49249249, 8 + dspck_tsimm prepend, 0x000001fe, 0x7fffffff, 0x000000ff, 31 + dspck_tsimm prepend, 0x1ffffff8, 0x1ffffff8, 0x80000001, 0 + dspck_tsimm prepend, 0xffffff97, 0xe0000003, 0xffffffcb, 31 + dspck_tsimm prepend, 0xfffec8d0, 0xfffb2342, 0x0000001f, 2 + dspck_tsimm prepend, 0x40000000, 0x80000000, 0xfffffffe, 1 + dspck_tsimm prepend, 0x03fffffe, 0x03fffffe, 0x00000c17, 0 + dspck_tsimm prepend, 0x80000000, 0x00000000, 0xc0000003, 1 + dspck_tsimm prepend, 0xcea81fff, 0x03fffffe, 0xfffd39d5, 13 + dspck_tsimm prepend, 0xc0000c64, 0x0003192a, 0x0000d270, 6 + dspck_tsimm prepend, 0x000001ff, 0x3ffffffe, 0x00000000, 21 + dspck_tsimm prepend, 0x20000000, 0x80000000, 0x80000000, 2 + dspck_tsimm prepend, 0xfec42a9c, 0x1ffffff0, 0xff62154e, 31 + dspck_tsimm prepend, 0xf973ffff, 0x7fffffff, 0xffffff2e, 13 + dspck_tsimm prepend, 0x7c000000, 0xf8000001, 0x80000000, 1 + dspck_tsimm prepend, 0x0000006f, 0x7fffffff, 0xe0000003, 27 + dspck_tsimm prepend, 0x6d17c000, 0xe000000f, 0x0000368b, 15 + dspck_tsimm prepend, 0x0000003f, 0x7fffffff, 0x80000000, 25 + dspck_tsimm prepend, 0x18000000, 0x0000029c, 0x00001460, 10 + dspck_tsimm prepend, 0x59a85fba, 0xfdd559c5, 0x000acd42, 19 + dspck_tsimm prepend, 0xe7ffffff, 0x3ffffff8, 0x0081575f, 3 + dspck_tsimm prepend, 0xffffed07, 0xffffed07, 0x00000000, 0 + dspck_tsimm prepend, 0x4fffffff, 0x7fffffff, 0x00000002, 3 + dspck_tsimm prepend, 0xf8ffffff, 0x3fffffe0, 0x07fffffe, 6 + dspck_tsimm prepend, 0x000a559a, 0x000a559a, 0x7fffffff, 0 + dspck_tsimm prepend, 0x0f261bcd, 0x1e4c379a, 0x00000ae6, 1 + dspck_tsimm prepend, 0x00000000, 0x00000001, 0xfffffff0, 1 + dspck_tsimm prepend, 0xe0000bcb, 0x0000bcb1, 0xfffffffe, 4 + dspck_tsimm prepend, 0x8010c97e, 0x002192fc, 0x7fffffff, 1 + dspck_tsimm prepend, 0x00000000, 0x00000000, 0xfffff7e4, 1 + dspck_tsimm prepend, 0x7ffffff0, 0x7ffffff0, 0x00000000, 0 + dspck_tsimm prepend, 0xdffffffe, 0x7ffffff8, 0x80000007, 2 + dspck_tsimm prepend, 0xfffffff5, 0xfffffffa, 0xfffffffa, 31 + dspck_tsimm prepend, 0x7ffffffa, 0x7ffffffa, 0x7fffffff, 0 + dspck_tsimm prepend, 0x00000000, 0x00000000, 0x7ffffff0, 0 + dspck_tsimm prepend, 0x000001ff, 0x8000001f, 0x000000ff, 31 + dspck_tsimm prepend, 0x00000000, 0x00000000, 0x00000000, 27 + dspck_tsimm prepend, 0x00083a04, 0x00107408, 0x07fffffc, 1 + dspck_tsimm prepend, 0xfffffffe, 0x7fffffff, 0x7fffffff, 31 + dspck_tsimm prepend, 0xffffc25d, 0xaaaaaaaa, 0xffffe12e, 31 + dspck_tsimm prepend, 0x0003e000, 0xf8000001, 0x00000000, 14 + dspck_tsimm prepend, 0x29fc2bb3, 0x29fc2bb3, 0x80000000, 0 + dspck_tsimm prepend, 0xffffa900, 0x000036c7, 0xfffffd48, 27 + dspck_tsimm prepend, 0xffffffba, 0xffffffba, 0x0f0f0f0f, 0 + dspck_tsimm prepend, 0x00000017, 0xffffc303, 0x80000005, 30 + dspck_tsimm prepend, 0x07fffe00, 0xffff0000, 0x00000003, 7 + dspck_tsimm prepend, 0xfffffff7, 0xf0000003, 0xfffffffe, 29 + dspck_tsimm prepend, 0xffe97f08, 0x00000005, 0xfff4bf84, 31 + dspck_tsimm prepend, 0xfffcc6a5, 0xfffcc6a5, 0x7fffffff, 0 + dspck_tsimm prepend, 0xe0000003, 0xe0000003, 0x66666666, 0 + dspck_tsimm prepend, 0xe0000000, 0x00000000, 0x00000827, 3 + dspck_tsimm prepend, 0xf8000000, 0x80000000, 0x7fffffff, 4 + dspck_tsimm prepend, 0xe0000003, 0xe0000003, 0x80000000, 0 + dspck_tsimm prepend, 0x24924940, 0x80000000, 0x92492492, 25 + dspck_tsimm prepend, 0x000001f9, 0x000001f9, 0x1ce10bb3, 0 + dspck_tsimm prepend, 0xfffe0000, 0x00000000, 0x3ffffffc, 17 + dspck_tsimm prepend, 0x0000728f, 0xfffffffe, 0x00001ca3, 30 + dspck_tsimm prepend, 0xfe1db4e0, 0x00000de7, 0xfff0eda7, 27 + dspck_tsimm prepend, 0x07fffffe, 0x0ffffffc, 0x00000000, 1 + dspck_tsimm prepend, 0x80f31ed7, 0x01e63dae, 0x8000007f, 1 + dspck_tsimm prepend, 0xf0000000, 0x80000000, 0x000072d7, 3 + dspck_tsimm prepend, 0xfffffff4, 0x000d0717, 0xfffffffa, 31 + dspck_tsimm prepend, 0x007fffff, 0xfffffff8, 0x80000000, 9 + dspck_tsimm prepend, 0x00000000, 0x00000000, 0x00000000, 0 + dspck_tsimm prepend, 0xe0000006, 0x00006000, 0xf0000003, 31 + dspck_tsimm prepend, 0xf8ffffff, 0x7fffffff, 0x07fffffc, 7 + dspck_tsimm prepend, 0x001fffff, 0x7fffffff, 0x00000000, 10 + dspck_tsimm prepend, 0xffffffec, 0xffffffd8, 0x00000003, 1 + dspck_tsimm prepend, 0xffdfffff, 0x7fffffff, 0x7fffffff, 10 + dspck_tsimm prepend, 0x0000003f, 0x0000003f, 0x0000003f, 0 + dspck_tsimm prepend, 0x00fe67cb, 0xfe67cb2a, 0x00000000, 8 + dspck_tsimm prepend, 0xffe00014, 0x0000a3af, 0x7fffffff, 11 + dspck_tsimm prepend, 0x80000000, 0x80000000, 0xe0000003, 0 + dspck_tsimm prepend, 0x03999999, 0x33333333, 0x00000007, 9 + dspck_tsimm prepend, 0xffffc400, 0x00000022, 0xfffffff1, 22 + dspck_tsimm prepend, 0xaffffe94, 0xffffe940, 0x00a6984a, 4 + dspck_tsimm prepend, 0x02000000, 0x80000000, 0x00000000, 6 + dspck_tsimm prepend, 0xffffe59b, 0xffffe59b, 0x80000000, 0 + dspck_tsimm prepend, 0x04000000, 0x80000000, 0x80000000, 5 + dspck_tsimm prepend, 0xffff0000, 0x00000000, 0x7fffffc0, 22 + dspck_tsimm prepend, 0x01fc0000, 0x00000334, 0x8000007f, 14 + dspck_tsimm prepend, 0x7ffffff0, 0x7ffffff0, 0xfffffffe, 0 + dspck_tsimm prepend, 0x0ff00ff0, 0xff00ff00, 0x00000000, 4 + dspck_tsimm prepend, 0x00001fff, 0x3ffffffe, 0x80000000, 17 + dspck_tsimm prepend, 0x00000001, 0x80000000, 0x80000000, 31 + dspck_tsimm prepend, 0x012b9440, 0x2b9440fc, 0x00000001, 8 + dspck_tsimm prepend, 0x72000000, 0x00000002, 0xffffd5c8, 10 + dspck_tsimm prepend, 0xfff138af, 0xfff138af, 0x80000000, 0 + dspck_tsimm prepend, 0x00000000, 0x00000000, 0x00000000, 16 + dspck_tsimm prepend, 0xe3000000, 0x00000002, 0xe38e38e3, 8 + dspck_tsimm prepend, 0xf4911d04, 0xf4911d04, 0x8000007f, 0 + dspck_tsimm prepend, 0x7ffffff0, 0x7ffffff0, 0x00000000, 0 + dspck_tsimm prepend, 0x09ffe215, 0xffe21573, 0xffffe109, 8 + dspck_tsimm prepend, 0x7fffffff, 0x7fffffff, 0xc890ef17, 0 + dspck_tsimm prepend, 0x52000000, 0x80000001, 0xfffdb214, 6 + dspck_tsimm prepend, 0x0000000f, 0xfee9b599, 0x00000000, 28 + dspck_tsimm prepend, 0x7ffff4ab, 0xffffe956, 0x0000016c, 1 + dspck_tsimm prepend, 0x007ff716, 0xffee2d5e, 0x00000000, 9 + dspck_tsimm prepend, 0xfffffffe, 0xfffffffe, 0x00000000, 0 + dspck_tsimm prepend, 0xd9ffffec, 0xfffff66c, 0xfffff66c, 7 + dspck_tsimm prepend, 0x00000000, 0x00000fb4, 0x80000000, 15 + dspck_tsimm prepend, 0xe0000000, 0x00000000, 0x7fffffff, 3 + dspck_tsimm prepend, 0x00000735, 0x00000735, 0xffffffff, 0 + dspck_tsimm prepend, 0x90000000, 0x80000000, 0x1ffffffc, 3 + dspck_tsimm prepend, 0x000000ff, 0xffffb926, 0x00000000, 24 + dspck_tsimm prepend, 0x00002b8d, 0x00002b8d, 0x8000007f, 0 + dspck_tsimm prepend, 0xc0000000, 0x00000000, 0x00000017, 2 + dspck_tsimm prepend, 0x80000000, 0x80000000, 0xff9a0952, 0 + dspck_tsimm prepend, 0x0f76e7cf, 0x0f76e7cf, 0x0f76e7cf, 0 + dspck_tsimm prepend, 0x38e38e38, 0x7fffffff, 0x1c71c71c, 31 + dspck_tsimm prepend, 0xea000000, 0x80000001, 0xfffffffa, 6 + dspck_tsimm prepend, 0x03fffffd, 0xfffff747, 0x0000000f, 10 + dspck_tsimm prepend, 0x01f80000, 0xe0000007, 0xe0000007, 10 + dspck_tsimm prepend, 0xfffffdbf, 0xffff6c3a, 0xffffffed, 27 + dspck_tsimm prepend, 0x000464c3, 0x7fffffff, 0x00008c98, 29 + dspck_tsimm prepend, 0x80000004, 0x80000004, 0x00000000, 0 + dspck_tsimm prepend, 0x00000128, 0x00000128, 0x0000003c, 0 + dspck_tsimm prepend, 0x2002c2ed, 0x00161769, 0x00de5fe1, 3 + dspck_tsimm prepend, 0x00001fff, 0xffffff80, 0xf0000007, 22 + dspck_tsimm prepend, 0xfffe0000, 0x00000e92, 0x7fffffff, 15 + dspck_tsimm prepend, 0x0001fffe, 0x00000000, 0x0000ffff, 31 + dspck_tsimm prepend, 0xffffffff, 0xe0000001, 0x7fffffff, 31 + dspck_tsimm prepend, 0x01ffffff, 0x7fffffff, 0x00000000, 6 + dspck_tsimm prepend, 0xfffffc19, 0xfffffe0c, 0xfffffe0c, 31 + dspck_tsimm prepend, 0x40000000, 0x80000000, 0x00084488, 1 + dspck_tsimm prepend, 0xe0000000, 0x80000000, 0x7fffffff, 2 + dspck_tsimm prepend, 0x00000001, 0x80000000, 0x80000000, 31 + dspck_tsimm prepend, 0xfff80000, 0x00000000, 0xfffffffe, 14 + dspck_tsimm prepend, 0x00000001, 0xc71c71c7, 0x00000000, 31 + dspck_tsimm prepend, 0x00010000, 0x80000000, 0x00000000, 15 + dspck_tsimm prepend, 0x83fffffe, 0x07fffffc, 0x0001594b, 1 + dspck_tsimm prepend, 0x00800000, 0x80000000, 0x80000000, 8 + dspck_tsimm prepend, 0x1ffffff0, 0x1ffffff0, 0x8000007f, 0 + dspck_tsimm prepend, 0x3ff28345, 0xffca0d15, 0x7ffffff8, 2 + dspck_tsimm prepend, 0x00000001, 0xfffffffc, 0x00000000, 31 + dspck_tsimm prepend, 0x00000000, 0x00000002, 0x80000000, 4 + dspck_tsimm prepend, 0xa4f1ca00, 0x80000000, 0x00293c72, 22 + dspck_tsimm prepend, 0xe03fffff, 0xffffff58, 0xffffff80, 10 + dspck_tsimm prepend, 0x001fe01f, 0x00ff00ff, 0x80000000, 3 + dspck_tsimm prepend, 0xe1e1e1e1, 0xffffff80, 0xf0f0f0f0, 31 + dspck_tsimm prepend, 0x56c7a000, 0x000037a4, 0x0012b63d, 19 + dspck_tsimm prepend, 0xf07fffff, 0x3ffffff8, 0xfffffff8, 7 + dspck_tsimm prepend, 0xfffa4948, 0x00000000, 0xffff4929, 29 + dspck_tsimm prepend, 0xfffffff8, 0xfffffff0, 0xf8000003, 1 + dspck_tsimm prepend, 0xffffff00, 0x00000000, 0x7fffffff, 24 + dspck_tsimm prepend, 0x00120000, 0x00000007, 0x00000009, 15 + dspck_tsimm prepend, 0xffc1ffff, 0xffffff9d, 0xffffffe0, 15 + dspck_tsimm prepend, 0x0000007f, 0xfffe3d99, 0x80000000, 25 + dspck_tsimm prepend, 0x00000000, 0x00000000, 0x00000000, 7 + dspck_tsimm prepend, 0xfde6992d, 0x80000005, 0xfef34c96, 31 + dspck_tsimm prepend, 0xffffffff, 0xffffffe8, 0x7fffffff, 29 + dspck_tsimm prepend, 0x1ffffff0, 0x00000000, 0x0ffffff8, 31 + dspck_tsimm prepend, 0x7ffffffe, 0x7ffffffe, 0xff0fceda, 0 + dspck_tsimm prepend, 0x00000000, 0x00000000, 0x0002e398, 0 + + writemsg "[29] Test shra.qb" + dspck_dtsaio shra.qb, 0x00ff0000, 0x00ff3f01, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x003fe138, 0x007fc371, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000701, 0x01001d04, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0300fffc, 0x6d18fd87, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0dffc3ff, 0x0dffc3ff, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ff05ff, 0x00ff14ff, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000003ff, 0x000e35f9, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x01ff0000, 0x06ff0000, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xf9f800f5, 0xcfc705aa, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ff0000, 0x02bf0900, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000214, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ffffff, 0x00ffffff, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x87080001, 0x87080001, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xf1000300, 0xe3000701, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x030300ff, 0x7f7000ff, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0000ff, 0xff0100ff, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff05ff07, 0xff59ff78, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ff0000, 0x00ff001c, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff00ff02, 0xff01ff04, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0cfe01, 0xff0cfe01, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0000ff00, 0x0000ff00, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0f0e00, 0xff1e1c00, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff000000, 0x8f070d04, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000003, 0x06000039, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000f00f0, 0x000f00f0, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000100, 0x01010f00, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000004, 0x00000008, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x0d070300, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfafc00ff, 0xaac700ff, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xffff00ff, 0xffff00ff, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0cffff00, 0x66ffff03, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x06e700e6, 0x1b9f0199, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfb040000, 0xdb240000, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0efe0304, 0x38f90f12, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00e00300, 0x00810f00, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xe61f0803, 0x997c200f, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ffff00, 0x72e3ff00, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xf00f0809, 0x807e404d, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0ef3ffed, 0x1ce7ffdb, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00fffff1, 0x04ffff8e, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ff0100, 0x00f91101, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x007f2001, 0x007f2001, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfb0f09ff, 0xef3f27ff, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00023f00, 0x00047e00, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ff0000, 0x1fff0006, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000000ff, 0x020700ff, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff003e03, 0xff007c06, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xf800feff, 0x8100e7ff, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x541ecfbf, 0x541ecfbf, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x1500f701, 0x2a00ef03, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0000ff00, 0x3000f100, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfd0300fe, 0xaa7e00c7, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ff0009, 0x02ff0048, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000000ff, 0x010000ff, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff00fe00, 0xff00aa19, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff000000, 0x9208001c, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000000ff, 0x130003e7, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfffff000, 0xffffc102, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x07000319, 0x0e000733, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff000000, 0xff00011e, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff00f000, 0xff01e000, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0100ffff, 0x7a04ffff, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff000200, 0xff000b01, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xefff0100, 0xbfff0600, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x03ffff00, 0x70f1ff00, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x03f80301, 0x3f8e3019, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00027c03, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xf9003c01, 0xf9003c01, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0000fe, 0xf8112e99, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0006f5, 0xff0030aa, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x0c050204, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ffff00, 0x01ffff00, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xf3000100, 0xcc000400, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x0220077f, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x01000010, 0x03010020, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x01ff0009, 0x07ff0124, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfffc0000, 0xffe10301, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfe0400f8, 0xf02000c1, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff000012, 0xff010024, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x001b0603, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0000ff00, 0x3e1bff02, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfd3301ff, 0xfd3301ff, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfc070000, 0xe33d0000, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0000ff02, 0x0000ff02, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x023706e0, 0x046e0cc0, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xc3ff0700, 0xc3ff0700, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0000f806, 0x00008166, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x60ff0105, 0x60ff0105, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xf3ff0100, 0x99ff0800, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000004, 0x03010046, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000001, 0x0c00102b, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0001ff00, 0x0660f93c, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff000df3, 0xff0036cc, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0000ff03, 0x0102ff3b, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0003ff, 0xff000fff, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00038103, 0x00038103, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x03ff00f6, 0x1cff00b6, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xf600030a, 0xdb010e2b, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x02ff0300, 0x24ff3a00, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000000ff, 0x3f1000ff, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00e00f00, 0x01c11e01, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff00f900, 0xff009900, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfe000000, 0xc31b0400, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x38ff00c3, 0x70ff0087, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0000ff, 0x8e0009f9, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00010001, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0901d500, 0x1303aa00, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0000ff, 0xff0007ff, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x06fff803, 0x6aff8138, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00f30300, 0x019f1c03, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0002ffff, 0x0027fff0, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00fe0000, 0x00f80000, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x021f0049, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000301, 0x061b6f24, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0700016c, 0x0700016c, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfc03ff00, 0x817fff00, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff00ff00, 0x8e00cf00, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfd000000, 0xaa1a0e1f, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ffff01, 0x00ffff01, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x01ffff01, 0x18f0ff1a, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0000ff, 0xff003fcf, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xf00001f9, 0x81000ccf, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff00ff00, 0xff00ff02, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0000ff00, 0x0000ff24, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x129f0908, 0x129f0908, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x1b0000ff, 0x6d0001ff, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0f0007ff, 0x3d001fff, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ffff00, 0x1ee7c700, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff030000, 0xff1d0000, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff000000, 0xf90e0159, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff030200, 0xff332b00, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ffff00, 0x00c7e700, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x1c08ffff, 0x7120ffff, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xffffff00, 0xff99c300, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000000ff, 0x030800aa, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfe000001, 0xdf171c20, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff000000, 0xff08331c, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x02001c00, 0x05003800, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0102ffff, 0x1820f8ff, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000002, 0x0001024d, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ffff01, 0x00ffc160, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000100, 0x06054800, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00010003, 0x0e1a0638, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0000ffff, 0x0000ffff, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x01030700, 0x040e1f01, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfd0000f8, 0xdb00068e, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x05000001, 0x2f000008, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff09ffff, 0xff48ffff, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0002e101, 0x000a8706, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ff0000, 0x0dff001f, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00fe00ff, 0x03cc00ff, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0f0614ff, 0x1f0c29ff, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0000ff, 0xc30f05ff, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x001f1509, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff00ffff, 0xe00affff, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xeaf00006, 0xaac00018, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0000fc02, 0x00009f47, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0006ffff, 0x0118ffff, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xcc090000, 0xcc090000, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000000fc, 0x000700e0, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xe300f13e, 0xc701e37c, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0000ff38, 0x0000ff70, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0600f0, 0xff0600f0, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x60c30dff, 0x60c30dff, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfffc0000, 0xfde70001, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x06c00700, 0x06c00700, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ffff00, 0x00f1ff0c, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xffb61fff, 0xffb61fff, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00010000, 0x01330700, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00fe00ff, 0x018f02ff, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0465cc0e, 0x0465cc0e, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0000ff, 0xff0700ff, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfff600ff, 0xffb600ff, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ff01ff, 0x00ff38e0, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000000ff, 0x000f1eff, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xe3021701, 0xe3021701, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ff0a00, 0x00ff5403, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfc000000, 0x80000100, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0000ff, 0xff000fff, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0f000300, 0x1f000700, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0fff0007, 0x7fff003f, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000100, 0x32287e00, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00020004, 0x00160320, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfefeff00, 0x819ffe10, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ff0300, 0x03ff7f00, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x01ffff00, 0x24ffff00, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000000ff, 0x000000ff, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x06ff6000, 0x06ff6000, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xffffff03, 0xffffff03, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000c0700, 0x00331c00, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xffc79f04, 0xffc79f04, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xe3ffffff, 0xc7ffffff, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ff041c, 0x00ff1371, 2, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000001fe, 0x000038df, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x03000c01, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfff9f101, 0xfccf8e0f, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfffe0000, 0xffe10100, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff0106f6, 0xf90d36b6, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xc75500ff, 0xc75500ff, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x1ee30001, 0x3dc70103, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0000000a, 0x00010755, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x0201003f, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x1f7e0e00, 0x1f7e0e00, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x02003f01, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff000000, 0xc1660d07, 7, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xfffeff00, 0xffc7ff00, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xf206ff00, 0x9231ff01, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000300ff, 0x007f0efc, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0000fc00, 0x0c00c00f, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00ff0100, 0x08ff3c01, 5, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x096071ff, 0x096071ff, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x3f0300ff, 0x7e0600ff, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0630ff30, 0x0c60ff60, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xe3133849, 0xe3133849, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff01ff02, 0xff1efe20, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x05000002, 0x5504002d, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x02000e00, 0x15007102, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x018e030c, 0x018e030c, 0, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000003, 0x0101033e, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000113, 0x00010227, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0001fcf8, 0x070ee1c0, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x000000ff, 0x020000ff, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0cff0fff, 0x60ff78ff, 3, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0001ff00, 0x0103ff01, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0xff010000, 0xff170600, 4, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x010000ff, 0x783a04db, 6, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x0c0e3200, 0x181d6500, 1, 0x0, 0x0 + dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 5, 0x0, 0x0 + + writemsg "[30] Test shra_r.qb" + dspck_dtsaio shra_r.qb, 0x01060078, 0x01060078, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0001fe00, 0x001acc00, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00003100, 0x00003100, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0111e7ff, 0x0111e7ff, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00020400, 0xff080e00, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x0bff0002, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xe0051f1e, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000008, 0x0000001e, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000100, 0x15047cff, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xf9100005, 0xc77e0129, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x10020000, 0x200400ff, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x706d0d09, 0x706d0d09, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0000ff00, 0x0101bf01, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x10100000, 0x1f1fffff, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x3e000000, 0x7cffffff, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x0607ff11, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xff00030f, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xe0f907ff, 0xe0f907ff, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x100fffff, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000200, 0x080b781e, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x20c71c30, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000004, 0x0000ff07, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x009905ff, 0x009905ff, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000001, 0x24010049, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0a000000, 0x26ff0100, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00f01e00, 0x00bf7800, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xdbffe019, 0xdbffe019, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00001007, 0x00ff200e, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x01000000, 0x54c7001e, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0007f500, 0x0038aafd, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000002fd, 0x06033b92, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00040001, 0xff470016, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000e070f, 0x001b0d1e, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00f208e0, 0xffc72080, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00ff0000, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x99180083, 0x99180083, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xdb010300, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0100050f, 0x09012478, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000300, 0xff006d0d, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0c000800, 0x60ff3c01, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x02020000, 0x1b21ff00, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xf2000005, 0xc701ff12, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xff00000b, 0xff00000b, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00f90003, 0xff8fff30, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x04ffe7ff, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0c0005cc, 0x0c0005cc, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00ff0700, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x02000003, 0x0700000c, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00ff0200, 0x00fd03ff, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00010000, 0x00550eff, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x0400ff00, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xff000000, 0xe0ffff01, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x11010c00, 0x220218ff, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x000a00ff, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00060500, 0xff0b0aff, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0000f701, 0x0100db04, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x01010000, 0x3e260101, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000001ff, 0x000001ff, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0001ff00, 0x0838cf00, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000010f0, 0xff0040bf, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0000ff00, 0x0300990f, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x1000f41f, 0x3e00cf7c, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x20793338, 0x20793338, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000000ff, 0x0f00ff87, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x001c011c, 0x00370238, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x03000003, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00070000, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xef00ff03, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x1e13000d, 0x1e13000d, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x080c00ff, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00f90000, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000d0300, 0x001a0600, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x18f7ff01, 0x18f7ff01, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0000fa05, 0x00ffe715, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x04000b00, 0x230055ff, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000108, 0x01ff0420, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000000ff, 0x00f901aa, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000300, 0x07006602, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000100, 0x02ff08fd, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x4002e800, 0x7f03cfff, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000300fe, 0x000bfff7, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000100, 0x02001300, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00c8000c, 0x008fff17, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0a9f000e, 0x0a9f000e, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0000003e, 0x00ff007c, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x020002fe, 0x1dff18e0, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000002fd, 0x00000fe7, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000100fe, 0x032c00c1, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xff080001, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000200fe, 0xff4df9c0, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x06001f00, 0x18ff7c00, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xb601ffff, 0xb601ffff, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x30f40933, 0x60e71166, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xf20003f0, 0x92031b81, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00350037, 0x0069006e, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xfe020000, 0x817303ff, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00020100, 0xff3f19ff, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x25ee3c08, 0x49db780f, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xffff0003, 0xffff0003, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000000fa, 0xffffff9f, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x07ff0000, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00010001, 0x007f0052, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0000fe10, 0x0000ef7e, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xaa0000ff, 0xaa0000ff, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x12070b02, 0x240e1503, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xf0080000, 0xc01e0001, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0000000f, 0x02010075, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xee000c01, 0xb6003003, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xff000905, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xe1000103, 0x8300020c, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xff000000, 0xe3000000, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x10070800, 0x7e383cff, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000008, 0x0000003c, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xff00f700, 0xf900b603, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00ff0100, 0xffcc35ff, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0000fa01, 0x0101e703, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xfa010002, 0xcf0b010e, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x05fa1004, 0x26cc7e21, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x02010303, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xffff00ff, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xff101ce0, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00010001, 0xff2dff18, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x03000002, 0x6000ff35, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000001, 0xe3ff1020, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0eeb0100, 0x36aa0300, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00030000, 0x01300000, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00fd0100, 0xfff30501, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0000fc06, 0x00fff70c, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0001fe01, 0xff409f40, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0408fd08, 0x0e20f31e, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x24ff609f, 0x24ff609f, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x01000000, 0x66ffff2a, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x09fd0e00, 0x12f91c00, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xfff30192, 0xfff30192, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00080000, 0x013f0000, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0c00011f, 0x0c00011f, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00ff0101, 0xfff70709, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x01000101, 0x06fe0408, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00080000, 0x067eff00, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000100, 0x00ff7802, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00020010, 0x0003ff1f, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00010000, 0xff550002, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x2500f001, 0x2500f001, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000110, 0xff00011f, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000000ff, 0x30000083, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000100, 0x15ff7806, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x100b0500, 0x100b0500, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00e40000, 0xff8fffff, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000500f9, 0xfd4eff8f, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000002, 0x00000c30, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00070000, 0xff390000, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x02030003, 0x080cff0c, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00f80005, 0xff83014d, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00010100, 0x007e41f1, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x011b0304, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x02fe0000, 0x30bf0300, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x0100f00c, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xfdfd0000, 0xf3f30101, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x01040000, 0x1f7ffe04, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x1e04010f, 0x3b08021e, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0100fe00, 0x2b00c700, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xffff0000, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0002ffe0, 0xff04fdc0, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00ff0802, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x008e0600, 0x008e0600, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xffccfc3e, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x04010010, 0x04010010, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00030000, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00010000, 0xff7e000f, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0c0000e2, 0x170000c3, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x02ff0400, 0x3fe07f03, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x0112000c, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x7f0000e1, 0x7f0000e1, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000001, 0x0100055d, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x04000100, 0x46000f01, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xe79f0106, 0xe79f0106, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x24618f00, 0x24618f00, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00e74900, 0x00e74900, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000200fe, 0x0c7f0a99, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x090efd07, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000000ff, 0x000001db, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00e00403, 0xff810e0d, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xf3090300, 0x994918ff, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x09000000, 0x49000000, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x79ff3018, 0x79ff3018, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000000ff, 0xff0100f9, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00e1ff03, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x04fe0002, 0x71c1f13a, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x01010001, 0x2416f117, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xff000000, 0xef0c0200, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xc800001c, 0x8fff0038, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x07f200fc, 0x389201e3, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00010000, 0x3f4000ff, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00100100, 0x003f02ff, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00380000, 0x00380000, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x020a0013, 0x0927ff4d, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x18c0e004, 0x18c0e004, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000000ff, 0x3f03ef87, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x001f7cff, 0x001f7cff, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000006ff, 0xff0066f0, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00ff06fc, 0x02f733e0, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00010002, 0x0005010e, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x1c00f700, 0x1c00f700, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x0800fc00, 0x7fffc3f9, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x1fc30fc3, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00f20000, 0xff8e0000, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x0aff0000, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000100, 0x010a551c, 6, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000100, 0x00ff1804, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00010000, 0x001affff, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00020000, 0x0007ff00, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xff0fffff, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00020002, 0x01070006, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x07010003, 0x7213ff2a, 4, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x03000000, 0x0aff0100, 2, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x000000ff, 0xf80003e1, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xc33c3302, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x68ff00ff, 0x68ff00ff, 0, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x040000ff, 0x71fff0df, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0xffff0100, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 3, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x003c1fe1, 7, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0xc2d5e600, 0x83aaccff, 1, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x01000000, 0x1400ff00, 5, 0x0, 0x0 + dspck_dtsaio shra_r.qb, 0x00000000, 0x02011cff, 6, 0x0, 0x0 + + writemsg "[31] Test shrav.qb" + dspck_dstio shrav.qb, 0x00000000, 0x02020003, 0xafd3a2af, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x04000101, 0x3fa6c62b, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000ff0e, 0x0100ff1c, 0xc0a75279, 0x0, 0x0 + dspck_dstio shrav.qb, 0xfcfcfc03, 0x9f8f8061, 0x2dd91095, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ff6007, 0x00ff6007, 0x00000000, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x39010030, 0xb35f4bd6, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0100ff00, 0x0c00ff00, 0xb39018b3, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xdd9d8345, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x0009010d, 0x117dc387, 0x0, 0x0 + dspck_dstio shrav.qb, 0x165b1edf, 0x165b1edf, 0x8bdd73b0, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff00ffff, 0xff00ffff, 0xa882ebfc, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x01000b00, 0xa1f78da5, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff0000f8, 0xff0000c1, 0xc240332b, 0x0, 0x0 + dspck_dstio shrav.qb, 0x1f002b00, 0x3f005600, 0x9d77deb9, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff00ff00, 0x87188134, 0x98ddb447, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff00ffff, 0x8204819f, 0x8204819f, 0x0, 0x0 + dspck_dstio shrav.qb, 0xfcfff00e, 0xe1ff8071, 0xe85e9f4b, 0x0, 0x0 + dspck_dstio shrav.qb, 0x01ff0000, 0x36ff0000, 0x63dc6b55, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000100, 0x070e6610, 0x96ce4886, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00021e08, 0x00053c10, 0x061c5191, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0001040f, 0x0306103f, 0x49591efa, 0x0, 0x0 + dspck_dstio shrav.qb, 0xffff019f, 0xffff019f, 0x2e3876b8, 0x0, 0x0 + dspck_dstio shrav.qb, 0x47394dc0, 0x47394dc0, 0x47394dc0, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xf5574786, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00bf8700, 0x00bf8700, 0x42635220, 0x0, 0x0 + dspck_dstio shrav.qb, 0xfe0000ff, 0xb60000ff, 0x15d4257e, 0x0, 0x0 + dspck_dstio shrav.qb, 0x1f00d512, 0x3f00aa24, 0xdf5baef1, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00f90000, 0x06cc0500, 0x06ec25e3, 0x0, 0x0 + dspck_dstio shrav.qb, 0xfeff0000, 0x99e70302, 0xe9b3a706, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00f37c00, 0x00f37c00, 0x0dbd3a00, 0x0, 0x0 + dspck_dstio shrav.qb, 0x01051207, 0x0517491c, 0x0f07fe0a, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0106001f, 0x0106001f, 0x8f132c78, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ffff00, 0x00ffff03, 0x2945c7ed, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0001fd00, 0x062cb11d, 0x062cb11d, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff0000ff, 0xe00c08ff, 0xac63fe5d, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff010000, 0xff3f0203, 0xbe03f215, 0x0, 0x0 + dspck_dstio shrav.qb, 0x02ff0dff, 0x08ff37ff, 0x0b8206a2, 0x0, 0x0 + dspck_dstio shrav.qb, 0x05000000, 0x5b030d01, 0xefe6d0f4, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0x417f4151, 0x0, 0x0 + dspck_dstio shrav.qb, 0x380022ff, 0x380022ff, 0x21b5f3f0, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0d0a1402, 0x352a530a, 0x352a530a, 0x0, 0x0 + dspck_dstio shrav.qb, 0x03ff0000, 0x33ff070c, 0x49b3c244, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff0100ff, 0xff0c00ff, 0xf802e8c3, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000ffff, 0x0006ffff, 0x0e271af5, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0b700000, 0x0b700000, 0x00000000, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000300f8, 0x000600f1, 0xd4bc0121, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000100fe, 0x042001cf, 0x87f2742d, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000ff00, 0x0500ff03, 0x36e58b23, 0x0, 0x0 + dspck_dstio shrav.qb, 0x01000000, 0x06000202, 0x3f6da0fa, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00fb0101, 0x00db0b0a, 0xa68689f3, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000001, 0x00051a27, 0x06d1563d, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000000ff, 0x000300ff, 0x93639cc4, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0f010000, 0x7e080000, 0x859a2a53, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0100ff03, 0x0800ff1f, 0x66c89803, 0x0, 0x0 + dspck_dstio shrav.qb, 0xffff0407, 0xffff111c, 0x173c43e2, 0x0, 0x0 + dspck_dstio shrav.qb, 0x1bff00fb, 0x37ff01f7, 0x60ab3591, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000f0fb, 0x0000c0ef, 0xe332bb62, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x3f060f1f, 0x3695b34f, 0x0, 0x0 + dspck_dstio shrav.qb, 0xfe000700, 0xef037100, 0xa8a15ae4, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0003ff00, 0x1e6dff00, 0xcd7da8bd, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000f707, 0x0000f707, 0x00000000, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000107, 0x00001e71, 0xc58eccb4, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff0000ff, 0xff020bff, 0x86423814, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00f00003, 0x00e10107, 0x4d551709, 0x0, 0x0 + dspck_dstio shrav.qb, 0x05ffff00, 0x29ffff00, 0x32044deb, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff000000, 0xff010202, 0x9c48e7a5, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000000ff, 0x000018c3, 0x315e3446, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ff0000, 0x00ff0004, 0xc41aca7e, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000101ff, 0x050f0eff, 0x94849dbb, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000001fe, 0x001d36c3, 0xc39610f5, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff0001ff, 0xff0309ff, 0x4ed1528b, 0x0, 0x0 + dspck_dstio shrav.qb, 0xe0fd04ff, 0x83f710ff, 0xac920fca, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000f000, 0x0100c103, 0x06a82daa, 0x0, 0x0 + dspck_dstio shrav.qb, 0x02ffff00, 0x24fdff01, 0xf20a70a4, 0x0, 0x0 + dspck_dstio shrav.qb, 0x7840fff7, 0x7840fff7, 0x1924ffd8, 0x0, 0x0 + dspck_dstio shrav.qb, 0x03ff24ff, 0x03ff24ff, 0x0619b520, 0x0, 0x0 + dspck_dstio shrav.qb, 0x04ff098e, 0x04ff098e, 0xe6650048, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0eff0001, 0x1cff0003, 0xea144cb1, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff0100ff, 0xdb7e06ff, 0xdfa828de, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff000100, 0xfc0c3c00, 0x5911f40d, 0x0, 0x0 + dspck_dstio shrav.qb, 0x01e40000, 0x05920300, 0x19d88f1a, 0x0, 0x0 + dspck_dstio shrav.qb, 0xffffffe0, 0xffffffc0, 0x651ab179, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00330016, 0x00330016, 0x86d483b8, 0x0, 0x0 + dspck_dstio shrav.qb, 0x01000008, 0x0f000040, 0xff5594a3, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff010300, 0xff030600, 0x4b9c7bd9, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000000e, 0x0000001c, 0xd4498c01, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000000ff, 0x007102ff, 0xb63d928f, 0x0, 0x0 + dspck_dstio shrav.qb, 0xf0001938, 0xe1013370, 0x501b0be9, 0x0, 0x0 + dspck_dstio shrav.qb, 0xe008ff00, 0xc111ff00, 0x0f48f791, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00010400, 0x01030901, 0x03bec071, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff3e3002, 0xff7c6004, 0x1408a259, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xab16062d, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000000ff, 0x30003efc, 0xd50a4476, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x02010006, 0x19f2191b, 0x0, 0x0 + dspck_dstio shrav.qb, 0x03ff03fd, 0x66f371bd, 0x66f371bd, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0b0bff06, 0x0b0bff06, 0x537ca288, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0ef900ff, 0x3be703ff, 0x0314e022, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000000fe, 0x000803aa, 0x78d420d6, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000600c1, 0x000c0083, 0x2ecd3cc9, 0x0, 0x0 + dspck_dstio shrav.qb, 0xffffffff, 0xffffbf8e, 0x96dd54e7, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00f11f00, 0x00c77c01, 0xd2c78f22, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000006ff, 0x000a60f7, 0x6deed8ac, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00090000, 0x8c623acd, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0001f803, 0x04118133, 0xdfc175a4, 0x0, 0x0 + dspck_dstio shrav.qb, 0x07f3f300, 0x1fcccc00, 0x874135ba, 0x0, 0x0 + dspck_dstio shrav.qb, 0xf9ff10c0, 0xf9ff10c0, 0x00000000, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000000ff, 0x17070c8e, 0x24d2eb27, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ff00ff, 0x00aa00aa, 0xe98fb6c7, 0x0, 0x0 + dspck_dstio shrav.qb, 0x010cff33, 0x010cff33, 0xb92126d0, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0007ffff, 0x003cffff, 0x85da748b, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0100fc00, 0x33008702, 0xa5e7f1e5, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000ff00, 0x0001f100, 0x39b74ddd, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000000f1, 0x000000f1, 0x00000000, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000000c7, 0x0000008f, 0xa5d38501, 0x0, 0x0 + dspck_dstio shrav.qb, 0xd33be338, 0xa676c771, 0xa676c771, 0x0, 0x0 + dspck_dstio shrav.qb, 0xfe000001, 0xe100001f, 0xd257bb44, 0x0, 0x0 + dspck_dstio shrav.qb, 0xfffffc00, 0xffffe000, 0x80856f23, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000033, 0xfca7c1af, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0b000005, 0x1600000a, 0xfcf17749, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0300c300, 0x07008700, 0xf7d6c109, 0x0, 0x0 + dspck_dstio shrav.qb, 0x01fc0000, 0x10cf0001, 0xbdf51434, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000fd00, 0x0300db00, 0xd5835b3c, 0x0, 0x0 + dspck_dstio shrav.qb, 0x2a300707, 0x55610e0f, 0x4a0f2999, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ff0000, 0x00ff0031, 0x542810b7, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00fcff00, 0x07cfff01, 0xd483ba64, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000ff00, 0x0007ff00, 0x939cb144, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0100ff00, 0x6018ff0c, 0xda2ae0a6, 0x0, 0x0 + dspck_dstio shrav.qb, 0x1d000574, 0x1d000574, 0x81c54170, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xd90eac9c, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x02000100, 0x45fa4234, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000000fc, 0x05021692, 0xd2a97325, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ff0000, 0x15c00000, 0x26163786, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000208ff, 0x010510ff, 0x5642cae9, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ffff00, 0x07ffff01, 0x06c6977d, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xcf158188, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0x89751668, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000ffe1, 0x0000ffc3, 0x051fe121, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0f1400f6, 0x3f5200da, 0x3f5200da, 0x0, 0x0 + dspck_dstio shrav.qb, 0x180d0100, 0x311a0200, 0x1fc3d561, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0c00ff01, 0x1900ff02, 0x85158e01, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff0001f8, 0xff0008c0, 0x42ddc17b, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000001ff, 0x00001cff, 0xd8c9f45c, 0x0, 0x0 + dspck_dstio shrav.qb, 0x010000ff, 0x040001ff, 0x3655c3c2, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xea33d1d2, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00070001, 0x58f8fe47, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff041800, 0xff041800, 0xe459f6d8, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ff0000, 0x04e32426, 0x42839a26, 0x0, 0x0 + dspck_dstio shrav.qb, 0x02030000, 0x0b0e0200, 0x3c75a952, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00f8f0ff, 0x00c181ff, 0xafd45b2b, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00301e00, 0xa85dfb5f, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff000000, 0xff006601, 0x7d9c855f, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff06001b, 0xff18006d, 0x1dcd6cf2, 0x0, 0x0 + dspck_dstio shrav.qb, 0x01000003, 0x0b000018, 0x3f66acf3, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff000000, 0xff000204, 0xc90e2906, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00fe00f8, 0x04e00383, 0xeeb69444, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000c00ff, 0x006000ff, 0xe8ac4013, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff02fe01, 0xe155c625, 0xe155c625, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff010000, 0xff180300, 0x00f72d24, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff00ffff, 0x8e48fff1, 0x7b3afccf, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00060416, 0x00060416, 0xde10aa60, 0x0, 0x0 + dspck_dstio shrav.qb, 0x001c1205, 0x00714914, 0xd51c7482, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff020002, 0xff4e005f, 0xe30ca9f5, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff0000ff, 0xfd0100bf, 0x46699ddf, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000ff00, 0x0101ff04, 0x25bb8687, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0x96640109, 0x0, 0x0 + dspck_dstio shrav.qb, 0x36000b00, 0x6d001600, 0xc4451731, 0x0, 0x0 + dspck_dstio shrav.qb, 0xe300ff30, 0xc700ff60, 0x52d5c559, 0x0, 0x0 + dspck_dstio shrav.qb, 0x380f17ff, 0x701e2eff, 0xf200a999, 0x0, 0x0 + dspck_dstio shrav.qb, 0x2e000700, 0x5c000e00, 0xf33d2349, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff000701, 0xff007119, 0xda59fd44, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff01ff00, 0xf710ff01, 0x2ef51474, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ff0107, 0x00ff1d70, 0x4923c7e4, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000100, 0x113a4923, 0x742077fe, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff381800, 0xff703100, 0x3b772a49, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0103ff00, 0x0103ff00, 0x42bfc240, 0x0, 0x0 + dspck_dstio shrav.qb, 0x1a01effd, 0x1a01effd, 0x71d8f2c8, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00010001, 0x00680147, 0x5b418ea6, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff010006, 0xff16076d, 0xf6845a7c, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000302fc, 0x12704b8f, 0x897b354d, 0x0, 0x0 + dspck_dstio shrav.qb, 0xffff0a01, 0xffff2906, 0x91185112, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0x2afc9373, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff030000, 0xff1e0000, 0xc08259b3, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00030f0e, 0x9ed5dad4, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff0000fe, 0xc01c0081, 0xa8c7260e, 0x0, 0x0 + dspck_dstio shrav.qb, 0x020000ea, 0x090001aa, 0x82443f9a, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff000000, 0xff000000, 0xd8801cd3, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x37000001, 0x24480ffe, 0x0, 0x0 + dspck_dstio shrav.qb, 0x03ff3800, 0x06ff7100, 0x5fcde621, 0x0, 0x0 + dspck_dstio shrav.qb, 0xe3cc0fff, 0xe3cc0fff, 0x80546498, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000000ff, 0x060000ff, 0xa63e71eb, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xef98b601, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0007f800, 0x077e8301, 0x8fd74ca4, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0001f340, 0x0001f340, 0xf9525288, 0x0, 0x0 + dspck_dstio shrav.qb, 0x07000000, 0x7e040000, 0x2b9b0454, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff031d01, 0xff031d01, 0x3723b810, 0x0, 0x0 + dspck_dstio shrav.qb, 0x080c001e, 0x080c001e, 0x27388b78, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00fc0000, 0x00e70002, 0xfd5731ab, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff010001, 0xf37c3066, 0xadf6eeee, 0x0, 0x0 + dspck_dstio shrav.qb, 0x03010000, 0x7c380000, 0x6273b78d, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00030000, 0x16730000, 0x2ff34b55, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ff0303, 0x00ff0606, 0x9e9bf481, 0x0, 0x0 + dspck_dstio shrav.qb, 0x81000003, 0x81000003, 0x877e1140, 0x0, 0x0 + dspck_dstio shrav.qb, 0x03000003, 0x32000c30, 0xcac0f81c, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ff00ff, 0x00ff00ff, 0xf0769d3e, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff0003fb, 0xfe021edb, 0x3fde5653, 0x0, 0x0 + dspck_dstio shrav.qb, 0xfeff00fd, 0xccff00b6, 0xa1455fad, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff0600f8, 0xff3103c7, 0xce48298b, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0x8e94e6c8, 0x0, 0x0 + dspck_dstio shrav.qb, 0xffff02ff, 0xffff17ff, 0xc64cbde3, 0x0, 0x0 + dspck_dstio shrav.qb, 0xf801df00, 0xf103bf00, 0xb7c8b3c1, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff00ff00, 0xff02ff1e, 0xeaff692d, 0x0, 0x0 + dspck_dstio shrav.qb, 0xf9000000, 0x92000108, 0xcd1eda74, 0x0, 0x0 + dspck_dstio shrav.qb, 0x09066699, 0x09066699, 0xba540f48, 0x0, 0x0 + dspck_dstio shrav.qb, 0x3c0000ff, 0x780000ff, 0xbd382b61, 0x0, 0x0 + dspck_dstio shrav.qb, 0xf10700f3, 0xf10700f3, 0x96530318, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00fffe00, 0x1fff9203, 0xf6b888b6, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00010003, 0x0012053f, 0xd4bedd14, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ff0000, 0x03ff0302, 0xe69bf4bc, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0006fcf1, 0x0035e38e, 0xce0b293b, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00fffe00, 0x01e3bf10, 0xb6ff1c56, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000000f1, 0x000103c7, 0xeb1baaa2, 0x0, 0x0 + dspck_dstio shrav.qb, 0x1df00007, 0x3be0000e, 0x13eefe49, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000600ff, 0x0c6000ff, 0x6d6530cc, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ff010d, 0x00ff010d, 0x76c2f0d8, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x0001786d, 0x933f62cf, 0x0, 0x0 + dspck_dstio shrav.qb, 0xff0000fe, 0xff0500f0, 0x0700174b, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00f3f000, 0x009f8301, 0x07c93ba3, 0x0, 0x0 + dspck_dstio shrav.qb, 0xfcff0000, 0x87ff0000, 0xd7adcf45, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0003fb04, 0x0118db22, 0x9edbd473, 0x0, 0x0 + dspck_dstio shrav.qb, 0x000000ff, 0x000e00ff, 0x30b7e6ff, 0x0, 0x0 + dspck_dstio shrav.qb, 0xcc000701, 0xcc000701, 0x00000000, 0x0, 0x0 + dspck_dstio shrav.qb, 0x121aff04, 0x2535ff08, 0x09d93101, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00fff9ff, 0x03ffccff, 0x8388608b, 0x0, 0x0 + dspck_dstio shrav.qb, 0xf804ea1f, 0xe010aa7c, 0xee906422, 0x0, 0x0 + dspck_dstio shrav.qb, 0xf800ff00, 0xf101ff00, 0xbcbb8611, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00ff0400, 0x00f04000, 0xd26579c4, 0x0, 0x0 + dspck_dstio shrav.qb, 0x00000000, 0x60007800, 0xe87d4f0f, 0x0, 0x0 + dspck_dstio shrav.qb, 0x0000ff00, 0x0000b604, 0x08b5b807, 0x0, 0x0 + dspck_dstio shrav.qb, 0x020f031f, 0x041f063e, 0xc1b93021, 0x0, 0x0 + + writemsg "[32] Test shrav_r.qb" + dspck_dstio shrav_r.qb, 0x01000000, 0x3301040f, 0x242d09be, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x08ef04ff, 0x08ef04ff, 0x00000000, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xff000000, 0xefff0300, 0x60471685, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02f81700, 0x09e15c00, 0xb8f4bda2, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x550000f1, 0x550000f1, 0x93bd72c0, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x023a2500, 0x047349ff, 0x1512c6c1, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00f10006, 0xff870031, 0x5a89d3fb, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x0023f800, 0xb60ef5cf, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xff110949, 0xff110949, 0xd2e09ff0, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0000ff00, 0x00009f0f, 0xfe907307, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xf00b0102, 0x81550611, 0xd5b7e94b, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x39e80e01, 0x71cf1c01, 0x28f5f269, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00ef0003, 0x2687028f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000004, 0x0001003e, 0xe45d186c, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x010f01e4, 0x011e01c7, 0xcee65491, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x000001ff, 0x07007e83, 0x17124257, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xffff00fd, 0xd0e0fca5, 0xd0e0fca5, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x000904fe, 0xff4922f3, 0xaa1589b3, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x111fe219, 0x457a8762, 0x457a8762, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000001, 0x18000078, 0xfe0946a7, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01000000, 0x71000fc3, 0xe027864f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x920f055c, 0x920f055c, 0x00000000, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00010002, 0x00050013, 0x46bb17bb, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02000004, 0x3507f878, 0xc84e5045, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00fe1c00, 0xfff77100, 0x96f1736a, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xff000a04, 0xff000a04, 0x00000000, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00ff0000, 0x1081ffff, 0xbbd479f7, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x70562009, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xdb000000, 0xb6ffffff, 0xceeb3209, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xbf5be101, 0xbf5be101, 0x638a5990, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00060000, 0xff300000, 0xc6c80193, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xf8f80600, 0x83876000, 0x16aff16c, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xff0500ff, 0xff0500ff, 0xa37e4968, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000300, 0x00003603, 0x451d55fc, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xf700000a, 0xb6ff0052, 0xc97e86ab, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0d000200, 0x33ff0600, 0x9894bee2, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00ff0000, 0x008e18ff, 0x364d3e67, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x1fffff00, 0xc9033376, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00ff0000, 0x0536ff89, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000001, 0x0fff0579, 0xf61738e7, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x032c0000, 0x2a826707, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x06030115, 0x170b0455, 0xc1ae0e2a, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00ff0000, 0x00aaffff, 0xcbacb87e, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xff02ff01, 0xd46bb34e, 0xd46bb34e, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xe7fe2bff, 0xe7fe2bff, 0x00000000, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x06030300, 0x0008459e, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00001000, 0xff0040ff, 0xb93b915a, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02020100, 0x677f4a06, 0x9f141b8e, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000100, 0xff005500, 0xe4397cfe, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02000000, 0x49000300, 0x17825ba5, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01f100ff, 0x01e100fe, 0x03fc3491, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x0012000f, 0xc931e687, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xfc09000e, 0xdf440171, 0xdfaac933, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x0000ff07, 0x1986bee4, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000001, 0xfff00054, 0xc8d79356, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x09ff0000, 0xbbc8f8f6, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0000ff00, 0x06ffc707, 0xe90b9db6, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x301a0027, 0x6033004e, 0x07dcb981, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x73bef463, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01180002, 0x045e0008, 0x98da93ea, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xfafc0000, 0xe7f00000, 0x54b35ef2, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x1a3efcff, 0x337cf8fd, 0xa36a5c11, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xfe000000, 0x87e00013, 0x4d8800ae, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x06000000, 0x3000fd00, 0xe412b51b, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x4901ff49, 0x4901ff49, 0x00000000, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x010100fe, 0x38200083, 0xf5b9c7e6, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00050000, 0x0049fe00, 0x463b491c, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00ffffff, 0xe53983a5, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00fe0000, 0x1487ff01, 0x682f399e, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00ff01ff, 0x395b152d, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000103, 0x0d001b66, 0x9b1936a5, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0xff00feff, 0x7c8e6786, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x1e000100, 0xc771647f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000200, 0x00ff0400, 0x36e1a469, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xffff1cfc, 0xffff1cfc, 0x877b2530, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0xff260205, 0x9900067f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x2371af46, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xffc75500, 0xffc75500, 0xfb9fb348, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000b00, 0x00005500, 0x38ed940b, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xe8f8f205, 0x9fdfc713, 0xc2cd014a, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01000b01, 0x01001601, 0xa5f80111, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x020c0000, 0x0730ff00, 0x528e8c4a, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000001, 0x0000ff24, 0xd47c0d7e, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01df0000, 0x01df0000, 0x00000000, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x06fe03ff, 0x58df31f4, 0x58df31f4, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xfd000000, 0xe700ff00, 0xc410611b, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x000000ff, 0x00030fdf, 0xd2494f75, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x000000fc, 0x00f9ffc1, 0xd9d062f4, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xffdb3ed0, 0xfeb67c9f, 0x304ab6a9, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01000002, 0x04010007, 0x37ea5b1a, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x49ff6681, 0x49ff6681, 0x0b6ea420, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x010d1504, 0x010d1504, 0x83e09d28, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x020000fe, 0x61ff009f, 0x2f50a106, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00ff03ef, 0x00ff03ef, 0x54d09060, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0d8c5298, 0x0d8c5298, 0x0d8c5298, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000300, 0x000362f3, 0xa5e9ccb5, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x040a201b, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xfc1a0000, 0xf06600ff, 0x6a9c5e7a, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00010000, 0xff08ff00, 0x074eb1a3, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00290000, 0x00290000, 0x93762660, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02000000, 0x3800ff00, 0x48a9cdc5, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0701cd02, 0x0e019904, 0xe4498451, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0a0ef900, 0x0a0ef900, 0x00000000, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00e40208, 0xff8e061e, 0xeeab1a0a, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0xff003e00, 0xa79b2f47, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00020200, 0xff434001, 0xe7617b0d, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000100, 0xff207e00, 0x5af39467, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00010001, 0xc443e76f, 0xc443e76f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01000100, 0x3f00490b, 0xafee0fd6, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00010701, 0x00010e02, 0x7410a9a9, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000002, 0x00000008, 0x30f14b02, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0a008100, 0x0a008100, 0x0dd94070, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xff000200, 0xec0327fc, 0xec0327fc, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00080001, 0x037c0011, 0xadeff08c, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000400, 0x00007eff, 0x5e569c2d, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0008303e, 0x000f607c, 0x9cd3b211, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x010000ff, 0x43ff06cc, 0x78a57306, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00020000, 0x007c05ff, 0xea658946, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0xc03dde95, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01000000, 0x0c0104ff, 0xf68aca14, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x051b0305, 0x051b0305, 0xf1384590, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x81190e00, 0x81190e00, 0xbfd1e558, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00ff0000, 0x206b0a24, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00ff00ff, 0x11990e8f, 0x11990e8f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00020000, 0x00040000, 0x4f7dd351, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0a02f000, 0x2908bf00, 0x0fa650ca, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01010101, 0x13162424, 0xd31bd115, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00030000, 0x00600008, 0x0e771295, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02000000, 0x4d0200f1, 0x8d564cd5, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xff00876d, 0xff00876d, 0xb4f870e0, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x010100fe, 0x403a029f, 0x5ca38336, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02000000, 0x4900ffff, 0x6c565805, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x000000ff, 0xcf020083, 0x407e9f27, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x070600ff, 0x070600ff, 0x0c048ac0, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x05020000, 0x4d1e0000, 0x74d658c4, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x808f85aa, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0014e002, 0x004e8007, 0x4f7e36c2, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00ff00fe, 0x18c30383, 0x6f593c76, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000005, 0xff00000a, 0xd31ffe59, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xdb7e0500, 0xdb7e0500, 0x5a21c1c0, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00f8fd00, 0x0087cf01, 0xab4fe12c, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x920a0325, 0x920a0325, 0xf2b828f0, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xfe000001, 0xe7020712, 0x42284324, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000200, 0x00017109, 0x42efba8e, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02020600, 0x0d0c3303, 0x20ee61db, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0000fe00, 0x0500cf07, 0xd61058bd, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0xf803fff8, 0x22ff6da4, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000004, 0xffff0038, 0xee761a1c, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xf7081eff, 0xf7081eff, 0xeb44b7f8, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0138db00, 0x0138db00, 0x00000000, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00050000, 0x0155ffff, 0x3d63281c, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x04000000, 0x10010000, 0x1385a6e2, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x09000000, 0x490301ff, 0x76f7c833, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0100f300, 0x07019900, 0x308ece2b, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0xf700ff07, 0x3ff4817e, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0xa5fb9a3f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000008, 0x00ff0278, 0xf0f3a2ec, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02000002, 0x3301013e, 0xf7f185cd, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01010000, 0x625e083c, 0xed380d7f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02010002, 0x361b0839, 0xf6d339b5, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x20010502, 0x7f021206, 0x662ff09a, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x003801ff, 0x003801ff, 0x0dff0f30, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00100401, 0x00400e02, 0x1f4f656a, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00040200, 0x000e0700, 0xf27342ba, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xffe3208e, 0xffe3208e, 0x17ba7058, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xeb00e415, 0xaa008f53, 0xfc013b02, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00ff0000, 0x0edb0101, 0x10b7c7d6, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x0003ff01, 0xb799731e, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x07160000, 0x0e2b00ff, 0xc919bf81, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0210006e, 0x0210006e, 0x00000000, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x1f1cf245, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xff150cff, 0xff150cff, 0xf379eda8, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000100, 0xfffd2410, 0x0be3f526, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000002, 0x0408ff6d, 0x0daf8956, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0000fc00, 0xfcff8000, 0xbeed5325, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x07fe01c0, 0xcfed84ff, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x09ffc303, 0x06c567c7, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02020000, 0x493e01ff, 0xcd1f25fd, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00ff0203, 0x03e33955, 0xa367eb2d, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0xc96c5e96, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x78009900, 0x78009900, 0xb3665bb0, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0000c100, 0xff008100, 0x23b16a21, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00400020, 0x007fff3f, 0x4bc39d21, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x71e7df02, 0x71e7df02, 0x00000000, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0xfff00600, 0x9ec54cc6, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00010001, 0x0632ff3f, 0x98ad56be, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01010202, 0x01020403, 0x371bb129, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00ff0000, 0xffaa0000, 0x33c4022f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x000104ff, 0xda281adc, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0401f9e6, 0x0f02e399, 0x4b81eec2, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x000000ff, 0xffff04cf, 0x41c8f006, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000100, 0x000578ff, 0xa7934b3f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xe4000102, 0xc7000104, 0x0f3d95a9, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x06c93e00, 0x0c927c00, 0x00785d99, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00007e00, 0x00007e00, 0x1b2347d0, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02000101, 0x06ff0402, 0xda698eaa, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xf700001f, 0xdbff007c, 0x75cf352a, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0xf700000a, 0xb955a7e6, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0xb46ce47c, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x04000202, 0x1e000f10, 0xed948deb, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x0000ff00, 0x09ef9ffe, 0x5b4e52ef, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00040000, 0xff73ff04, 0xe7a5fc7d, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000100, 0x030049ff, 0xdc2991be, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x0c8e982b, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x07090d00, 0x4ff82c0f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0xfffd0004, 0x12ad99bc, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x04000002, 0x3effff1f, 0x4e8a4e8c, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xff000000, 0xc0021e07, 0x049f2bae, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0xe0e70c02, 0xc38d562f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xff0000ff, 0x8f1c0080, 0xa425a9cf, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0xe81d3790, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00ff0000, 0x00cc0001, 0x9f2d62a6, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x04000003, 0x7101ff67, 0xe22220b5, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x32ab766e, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xf20500f7, 0x922500b6, 0xe9644183, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x1e0035ff, 0x502a8edf, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000004, 0x00ffff0e, 0xc76337ba, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00c1ff07, 0x00c1ff07, 0x6b3899d8, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x66854f6b, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01fd0001, 0x1899ff13, 0xa977a60d, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00fe0000, 0x04b60302, 0xd7d19e45, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01d01c00, 0x029f3700, 0x51bd5929, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x043801db, 0x043801db, 0x1c65f388, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x0000000e, 0x67925dfe, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02000000, 0x30ff00ff, 0x79699c05, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x55ff0104, 0x55ff0104, 0x4a05a198, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0xff000000, 0xf8ff0000, 0x7debe48b, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x1400000f, 0x00be0856, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x010c1892, 0x010c1892, 0x5fb16428, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x01010000, 0x7c781304, 0xdadc334f, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000200, 0xff00600a, 0xb96f1cfe, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0x00ff00ff, 0x8c1d6ddc, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x00000000, 0xf11c0703, 0x3bd612be, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x2d030000, 0x59050000, 0x7b8773e9, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02fcf500, 0x10e1aaff, 0x14b53d2b, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x04040810, 0x1c1c3e7e, 0x7edfdbbb, 0x0, 0x0 + dspck_dstio shrav_r.qb, 0x02fcf800, 0x18c18300, 0xaa7d35d4, 0x0, 0x0 + + writemsg "[33] Test shrl.ph" + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0fff0fc5, 0xfff7fc52, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00010000, 0xfb362492, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00001fff, 0x0000fffb, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x000f000c, 0xfffbc71c, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x7fff7fff, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00200000, 0x807f0000, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00010001, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x07fe07f8, 0xffceff10, 5, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x001c0001, 0x1c7101a9, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00010000, 0x1c7103fe, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00c70000, 0xc71c0006, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x09241ffd, 0x4924ffe8, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00380038, 0xe38ee00f, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x000e0000, 0xe003001f, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x3fc03fe2, 0xff00ff8b, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x03ff0000, 0x7fff0000, 5, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 9, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00010001, 0xfc01b6db, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x007c0040, 0xf9938000, 9, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x000003ff, 0x00007fff, 5, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0007007f, 0x07fc7fff, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x001e0100, 0x0f0f8000, 7, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x01ff0000, 0xffaf001f, 7, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00030000, 0xfffe0000, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00010001, 0xfe3f8000, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00010000, 0x7fff1dbb, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00010001, 0x0b5f0ffc, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00ff007f, 0xfff67fff, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x020001ff, 0x80007fff, 6, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00c000ff, 0xc001fffc, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x07ff3ffd, 0x1ffefff6, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0003001f, 0x007f03fe, 5, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x000001a9, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00070000, 0x7fc004b9, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x1ffe2000, 0x7ff88000, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x1fff1fff, 0x7fff7fff, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x000003c0, 0x0006f001, 6, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0030003f, 0xc003fff4, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x60077fff, 0xc00ffffe, 1, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x001c001f, 0xe001ffef, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x07ff0000, 0x7fff0000, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000004, 0x00018002, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x007f7fff, 0x007f7fff, 0, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00040000, 0x80000000, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x40003fff, 0x80007fff, 1, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x003f0020, 0xffeb8000, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00031ffc, 0x000d7ff0, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x16de0003, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x1c710391, 0x38e30722, 1, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00030000, 0xe38e0000, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x007f0040, 0xffc08000, 9, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x801fcd54, 0x801fcd54, 0, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x7fe07f8b, 0xffc0ff17, 1, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x7ff00000, 0xffe00000, 1, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00070003, 0x39dc1fe0, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x80000002, 0x80000002, 0, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x008000e1, 0x8000e14a, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00060000, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000018, 0x04ccc001, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x1fff0fff, 0xfffd7fff, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000040, 0x000a8000, 9, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x7fff7fff, 0x7fff7fff, 0, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x3ffb3fff, 0xffefffff, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0fff0000, 0x7fff0000, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0080007f, 0x80007ff9, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x000003ff, 0x00011ff8, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000007, 0x0356fe0f, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00080007, 0x80007ffc, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00137fc0, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x007f0100, 0x3fe08000, 7, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 0, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00030000, 0xf00301dc, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x02000000, 0x80030000, 6, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x001f6666, 0x003fcccc, 1, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00030003, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x03fa031b, 0xfe8fc6df, 6, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x001b1000, 0x00dc8000, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000006, 7, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x001f0019, 0x7fff6666, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x007f0000, 0xffe4017a, 9, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000fff, 0x00007fff, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0010001f, 0x8000fff5, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x35f20001, 0xd7ca0005, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x000f0080, 0x0ffc8003, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x08000000, 0x80040000, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x3fff7d81, 0x7ffffb02, 1, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x03ff07c0, 0x7ffff803, 5, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00070000, 0xfc880075, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x1fff3fff, 0x7ffdfffe, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00070006, 0xffffdb6d, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000001, 0x7fff9249, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00020000, 0x80000001, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00002000, 0x00008000, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00e30012, 0xe38e127f, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x3ff00000, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0000007f, 0x00007ffd, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x000301ff, 0x00fb7fff, 6, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x003f001f, 0xfffa7fff, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x03c30ffe, 0x0f0f3ff8, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000003, 7, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00010001, 0xf12e801f, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0000076d, 0x0000edba, 5, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x03ff03fd, 0xffffff5b, 6, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x02490fe9, 0x2492fe9d, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0000003f, 0x00001ffe, 7, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00040000, 0x80000000, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x01ff0043, 0x1ffe0433, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0000000f, 0x0000f003, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00020001, 0x92497fc0, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x01ff03ff, 0x7ffffffe, 6, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x03ff0ffe, 0x3ff8ffec, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00010001, 0xfffd8000, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x1fff01ff, 0xfffd0ff8, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00010000, 0x7ffb0000, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x001f0030, 0x7fffc00f, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00030003, 0x7fff7fff, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00010001, 0x800f803f, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x001f0000, 0x7fff0000, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x7fff07fc, 0x7fff07fc, 0, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x07800666, 0xf001cccc, 5, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x007f0000, 0x7ffa0000, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000125, 0x000024ba, 5, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x040003ff, 0x80007ffc, 5, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0002007f, 0x00b41ffc, 6, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0fff0000, 0x7ffa0000, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00030001, 0xf0037fff, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x000000e0, 0x0000e01f, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x07ff0000, 0xfffc0000, 5, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0001001f, 0x0d0fffa0, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00ff0000, 0xffff0033, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00020000, 0x80001c71, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x100001e1, 0x80000f0f, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00310000, 0xc71c0000, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x040003ff, 0x80007fff, 5, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000002, 0x00008000, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000040, 0x00808005, 9, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000010, 0x00048000, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x04fd07ff, 0x27ec3ffc, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0001000f, 0x0fa67f80, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000002, 0x003f8007, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00070007, 0x7fff7fff, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x01ff01ff, 0xfffdfffe, 7, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x007f0000, 0xffd80000, 9, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0000007f, 0x00007fff, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00ff007f, 0x7fff3fc0, 7, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000003, 0x00d3f801, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x1fff0000, 0x7fff0000, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000007, 0x0143f5ce, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00010001, 0xcbe08003, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x1fff0002, 0xfffb0011, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x03ff0000, 0xffcc0000, 6, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000200, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00100003, 0x80001ff0, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x000000ff, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x007f003f, 0xfe867fff, 9, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000ffc, 0x00000ffc, 0, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x03e00049, 0xf8011252, 6, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00070000, 0xfffd0003, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x07ff0e00, 0x7fffe007, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000007, 0x001b7fff, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x20003ffa, 0x8000ffea, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x8000cd47, 0x8000cd47, 0, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x001b0001, 5, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00030000, 0x0f0f0000, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00030000, 0x7f801ffe, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00070007, 0x1ff01daa, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00100007, 0x80003fc0, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x000d0000, 0x00d00000, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00020003, 0x8000ffff, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0fff0000, 0x7fff0000, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00040006, 0x8000c007, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0c030fff, 0xc03ffffc, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000003, 0x0000ff1b, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x003f0031, 0xfffec71c, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00070004, 0xffd98002, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00fe00ff, 0xfe6eff94, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x020000ff, 0x80043fe0, 6, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 6, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x3fff3fff, 0x7fff7fff, 1, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00003fff, 0x0000ffff, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x38e35b6d, 0x71c7b6db, 1, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x009d0000, 0x09d70004, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0aaa0803, 0xaaaa803f, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00080008, 0x803f8007, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x78137fff, 0xf027fffe, 1, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x40024000, 0x80058000, 1, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00030000, 0x3ffc0000, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x01ff0049, 0xff802492, 7, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x1ff9000b, 0xffc9005b, 3, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00030000, 0xcccc0041, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0000001f, 0x0000fe0a, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00010000, 0x80000000, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0010001f, 0x807ff801, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00008000, 0x00008000, 0, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0008000f, 0x8000fb96, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0000000f, 0x0000fef9, 12, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x007f0040, 0xfef68000, 9, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0fff0001, 0xfffc0013, 4, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00070007, 0xffd9e003, 13, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0000007f, 0x00067fc0, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00010000, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x1fff3fff, 0x7ffffffc, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x002a003f, 0x55557ffc, 9, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x001f0001, 0xff220ffe, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00480000, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x7fffe003, 0x7fffe003, 0, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00030002, 0xfea18e38, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x008000db, 0x8000db6d, 8, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x01ff01ff, 0xfffefffc, 7, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000002, 0x01538002, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x000f0000, 0x3fc00000, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000001, 0x00000005, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 7, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x000001c7, 0x0000e38e, 7, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00030000, 0xc71c0000, 14, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x007f0007, 0xffd80e1d, 9, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x0000002d, 0x03feb6db, 10, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x40000000, 0x80000000, 1, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x001c0010, 0xe38e8000, 11, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x00000000, 0x00007fff, 15, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x20003ffd, 0x8002fff4, 2, 0x0, 0x0 + dspck_dtsaio shrl.ph, 0x07ff0003, 0x7fff0033, 4, 0x0, 0x0 + + writemsg "[34] Test shrlv.ph" + dspck_dstio shrlv.ph, 0x80001ffe, 0x80001ffe, 0x00000000, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00070001, 0xfff53333, 0x3815c9ad, 0x0, 0x0 + dspck_dstio shrlv.ph, 0xfffdff23, 0xfffdff23, 0x4e836a20, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x001b001f, 0xdb6dffff, 0x66d24b3b, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000005, 0x2059cb19, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x001f001f, 0xfffcfff9, 0x1138d8db, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00040000, 0x80001ffe, 0x0c5ccedd, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0feb0000, 0xfeb80000, 0xdcdf6034, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000010, 0x00048000, 0x59fd687b, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00030012, 0x06b22492, 0x448c9f49, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x01e00000, 0xf00e0000, 0x31bba6f7, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000007ff, 0x0000fff4, 0x025a9815, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00001ffc, 0x0002ffe5, 0x4ac0b643, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x7e003ff0, 0xfc017fe0, 0x086f9ee1, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x01720150, 0x5ca35416, 0x5ca35416, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x03f303f0, 0xfceefc01, 0xd5e8b646, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0000007f, 0x00187fff, 0x18318df8, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000001, 0x3ffc7fff, 0xaece87fe, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x07f807fe, 0xff0effdd, 0x38b51875, 0x0, 0x0 + dspck_dstio shrlv.ph, 0xfd7f3333, 0xfd7f3333, 0x89feb4d0, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00ff07ff, 0x0ffe7fff, 0x8003d454, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000f0007, 0xfffd7ffa, 0x5b427c2c, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xab0ee5b0, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0008000f, 0x8005ffff, 0x13be73ac, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000001, 0x1ffc7fff, 0xb05e134e, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000020, 0x00008000, 0x51ecdcaa, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00ff0000, 0x7fff0000, 0x58d7fab7, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000f000f, 0xfff6ffff, 0xc4d9c01c, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x0b813c8a, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000078, 0x000bf007, 0x401a8529, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0008000c, 0x8000c853, 0x389594dc, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x07ff0800, 0x7fff8000, 0x13e88bf4, 0x0, 0x0 + dspck_dstio shrlv.ph, 0xfff51fe0, 0xfff51fe0, 0x00000000, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00e00000, 0xe0010000, 0xe9cc1168, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x01000000, 0x80000000, 0x380e6e67, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000f0010, 0x7fff8000, 0x0315280b, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x020003ff, 0x8000fffd, 0x0c532bb6, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x15290b12, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x003300da, 0x066e1b59, 0xb482d2d5, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x003f001f, 0xff897fff, 0x62064a7a, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x03fe0006, 0xfcfd57fe, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000004, 0xd3fe9f73, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x309a1fc6, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0003007d, 0x07fcfb58, 0xcbab8f29, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x001d0011, 0x0758046f, 0xe1bf1846, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000003, 0x3fc0e00f, 0x395a470e, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x03fef007, 0x03fef007, 0x00000000, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xbf14b400, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x11260024, 0x11260024, 0x00000000, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000001, 0x5136fa9f, 0x5136fa9f, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x003f0040, 0x7fff8000, 0xe0e04679, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000100, 0x00018000, 0x6b0ee687, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x007f0000, 0xff8c0004, 0x20a06ac9, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00040000, 0x80000000, 0x90f923bd, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x07ed0000, 0xfdbf0002, 0xf4a97d05, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0ffc3e00, 0x3ff0f801, 0x4844d9e2, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x003f0000, 0x7ffd0000, 0x04ddd8c9, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000001ff, 0x0000ffff, 0xf1dd3c57, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000010, 0x035b801f, 0xa52c2fbb, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xd0be099e, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x07fc0400, 0xff808000, 0x0ddbf085, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000000fc, 0x0000fc36, 0xae6c51c8, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x07ff03ff, 0xfffd7fff, 0x43189025, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x7fff0000, 0xa679b7ff, 0x0, 0x0 + dspck_dstio shrlv.ph, 0xfffcfc09, 0xfffcfc09, 0x00000000, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00010000, 0x3ff01ffc, 0xe10483ad, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0000078e, 0x0002f1de, 0x83c9bed5, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x1fff2000, 0x7fff8000, 0x17e071b2, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000057, 0x0000015d, 0x5b2d1752, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0000e007, 0x0000e007, 0x00000000, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x001f00cc, 0x1fe0cccc, 0x04795338, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00010002, 0x553ab1ae, 0x553ab1ae, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x64484000, 0xc8918000, 0x62fa20e1, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00ff007f, 0xfff07ff9, 0xfc5faa38, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0fff0000, 0xfff10000, 0x1b365e04, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x1fff0fff, 0xfffa7fff, 0xac8b8483, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xb47e2a1a, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00001ff0, 0xd64022ae, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x02000000, 0x80040000, 0x5f307386, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00010000, 0x01880000, 0x4475b3b8, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x001f0000, 0xfffe007f, 0xfc18fe2b, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x07ff0fff, 0x7ffffffc, 0x5944b7c4, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x40003ffd, 0x80007ffb, 0x669ee441, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x3fe91fff, 0xffa47fff, 0x94583a12, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x003f019b, 0x422f026c, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x40007fee, 0x8000ffdc, 0xf91dab61, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000003ff, 0x0001ffe9, 0x554897a6, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x37b91bab, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x012403ff, 0x24927fff, 0xb726d8f5, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00020000, 0x10350763, 0x83b1f64b, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x9487082f, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x01c70003, 0x38e3007f, 0x71bba4b5, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x3fe40090, 0xff910243, 0xbe658982, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0000dde1, 0x0000dde1, 0x00000000, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x7fff0000, 0x55f4898f, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x80000994, 0x80000994, 0x7901da20, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x020001ff, 0x80007fff, 0xc4c25336, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000003ff, 0x0020fffd, 0xa7d861f6, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x4c29ed09, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000004, 0x01e18000, 0x2ce1bb0d, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x4f17250a, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000001fe, 0x0006ff3d, 0x3948b837, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000010, 0x00008003, 0x152f5f7b, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x07ff1fff, 0x1ffe7fff, 0x5fa8e602, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000103ff, 0x00277ff9, 0x4c2af275, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x003f0015, 0xffff5555, 0x3460057a, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000001, 0x00007fff, 0x0e7615de, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x007f0000, 0x7ff80000, 0x2c0f8e08, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000020, 0x00008000, 0x97f23f7a, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00010003, 0x3ffc7fff, 0xedb171cd, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x467096da, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00141f67, 0x00a1fb3a, 0xa78af053, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0e7b0c00, 0xe7b9c003, 0xd30ef944, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00003c01, 0x0000f007, 0x8302e082, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00e00006, 0xe00f06b2, 0xee95bd18, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00ff0000, 0x1ffe0002, 0x13514835, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x1fff0fff, 0xfffd7fff, 0xd54e95d3, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x003f003f, 0xfffefff2, 0xcc87c3fa, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00040295, 0x2c42599b, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00c41fff, 0x03137fff, 0x6104a862, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x6db60000, 0x6db60000, 0x709b11e0, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x003f003f, 0xfff8fff9, 0x545450da, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x007f0002, 0x7fcd7e6d, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00030000, 0x7fff0017, 0x0e08407d, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00030000, 0x33330000, 0xc182ac2c, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00230020, 0x8e388000, 0x30dda44a, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000001, 0x7fffb6db, 0x1b9a83af, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0000000d, 0x0000d967, 0x6d9aaa6c, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x199901e1, 0xcccc0f0f, 0x3a5318a3, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0fe200b6, 0xfe2b0b62, 0xa216cf74, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x001c007f, 0x38e3ff81, 0x4858edf9, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x07fe01cb, 0xc81e90cc, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00010000, 0xfc01014a, 0x30b7f88f, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0003001f, 0x0c887ff8, 0x1f97133a, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x80007fff, 0x80007fff, 0xc9295bb0, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x008000e0, 0x8000e01f, 0xbbbe9e68, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0060007f, 0xc01ffff8, 0xc7cdbda9, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x07fd03ff, 0xffa97fff, 0x3cdb6085, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x007f0000, 0xffc00000, 0xf33401a9, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000001, 0x0000ffef, 0x91a9c83f, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00200000, 0x80000000, 0xcbad4e0a, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x1fff000d, 0x7fff0036, 0x111e2072, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x1c713fee, 0x71c7ffb9, 0x4b998f22, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x020003e0, 0x8000f803, 0xf24f4c36, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000000ff, 0x001fff6b, 0xdaa71b18, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0000003f, 0x0238ffe0, 0x3c15b6fa, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00010001, 0x80008000, 0x7838256f, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000800, 0x00008000, 0xf4ab3504, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x0000004f, 0x6dfdcfbd, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x1ff81ff8, 0x1ff81ff8, 0x74dced40, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00710180, 0x38e3c01f, 0x09804e37, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x05768000, 0x05768000, 0x26707240, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x49a3e60a, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0000018c, 0x00000632, 0x2fb9cec2, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x2000000d, 0x80030035, 0xabe958c2, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0001001c, 0x0ffee38e, 0xeb2b266b, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000200, 0x00008000, 0xc22b8f96, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00070000, 0xfffc0005, 0x1ae8fc8d, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xf0e98239, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0975000a, 0x0975000a, 0x00000000, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000007, 0x348f0396, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00010003, 0x7fffff7d, 0x198aecce, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0fff0fff, 0x7fff7fff, 0x598e8ed3, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xfdda32a8, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x03f90000, 0xfe6c0002, 0xc8ba2496, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000c07fe, 0x0189ffd2, 0xb6ef89c5, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x1fff2000, 0x7fff8000, 0x52fbcdd2, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x000000f1, 0x77db9978, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x3ff82000, 0xffe08000, 0x142abe02, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x010001ff, 0x8003fffd, 0x8d576df7, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0100001f, 0x80000ffe, 0x5c205077, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x40004000, 0x80008000, 0x6cd7dad1, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00070000, 0xfff8000a, 0x5a20231d, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000007ff, 0x0000fffe, 0x97dc1bc5, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000007ff, 0x0004ffff, 0x5882b3f5, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00ff0000, 0xff80003f, 0x7706d078, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000020, 0x00008000, 0x3db5290a, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000db6, 0x0000db6d, 0xb989b284, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0000001f, 0x0000fff8, 0xa2f67c7b, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x03ff03ff, 0xfffeffff, 0x80fafaf6, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x080007ff, 0x80007fff, 0xeddc0bc4, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0c000f0f, 0xc001f0f0, 0x26fda924, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000001, 0x00008000, 0xfdb7deef, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x040007af, 0x8000f5fd, 0x0c5110f5, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x03e00000, 0xf8010007, 0xdb1bbfa6, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00010002, 0x7fff8000, 0x89b8da4e, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x007f0000, 0xfffe0006, 0xb248ae79, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00030000, 0x7ff800f9, 0xccad0f4d, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00080000, 0x80000000, 0x08bc2f7c, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x001f0010, 0xff008000, 0x0d060f8b, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x008000ff, 0x8000fffd, 0x1101b038, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000001ff, 0x0000ff80, 0x2b8d6dc7, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x007b3ff0, 0x007b3ff0, 0x00000000, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x17f3125e, 0xbf9d92f3, 0xbf9d92f3, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00010001, 0xf803fff4, 0x9347887f, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x07ff0fc2, 0x7ffffc2b, 0x7fd4b604, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x3fff7f9b, 0x7fffff37, 0xd1837a51, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x008c00ce, 0x8c30ce18, 0x8c30ce18, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00010001, 0xffdafdc0, 0x19e15c9f, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x049600fe, 0x92c21fc5, 0x92c21fc5, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000004, 0x00008003, 0x01b37bbd, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000c71, 0x0000c71c, 0x3ab39334, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000f0007, 0xfaff7fff, 0xedf43a8c, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000707ff, 0x00717ffc, 0x1460b684, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00020003, 0x9999c003, 0x2c980d8e, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00001ff4, 0x0000ffa6, 0x7267cb13, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000f0008, 0xf8018005, 0x9ff74a2c, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00010000, 0xf0f07f80, 0x2242505f, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x3fff0003, 0xffff000f, 0xda1c89a2, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000001e0, 0x0008f007, 0x00ae2c77, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x007f01ff, 0x3ffcfff7, 0x8ee68f87, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x08000016, 0x80000166, 0x07499164, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xfc0ee4ec, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0000001f, 0x0000fff0, 0x04b633fb, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000008, 0x00008000, 0x15c0274c, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x7ffd7ffd, 0xfffafffa, 0x7337d061, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00200015, 0x807f5555, 0xdfbea0da, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x400377d2, 0x8006efa4, 0x31220071, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0c710000, 0xc71c000e, 0x9c1ec864, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x001f001f, 0xfca5ffb4, 0x9373ddcb, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x03ff003c, 0xfffe0f36, 0x78d15b96, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00030003, 0xe01ffffe, 0xa4e9f9de, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000000, 0x00007fff, 0xe040783f, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000003, 0x00003ffe, 0xf76b2d5c, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x003f0000, 0xfffe000d, 0x319bb95a, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x000f0008, 0xffff8000, 0xafd2ac4c, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0000007f, 0x00fffffd, 0x9f497189, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00010000, 0x80000000, 0x61e03e6f, 0x0, 0x0 + dspck_dstio shrlv.ph, 0xb6db0000, 0xb6db0000, 0x00000000, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00800000, 0x807f0000, 0x48557c78, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x3fff0000, 0x7fff0000, 0x0e4da731, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00800000, 0x80060001, 0x85f65858, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000f80, 0x0009f801, 0xc3fcd024, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x00000003, 0x0000fffb, 0x5830059e, 0x0, 0x0 + dspck_dstio shrlv.ph, 0x0000000a, 0x00000154, 0xc719a275, 0x0, 0x0 + + writemsg "[35] Test subu.ph" + dspck_dstio subu.ph, 0x0f47f8f0, 0x003700ec, 0xf0f007fc, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x8043fffb, 0x7ffffffb, 0xffbc0000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xff847100, 0xff8b8004, 0x00070f04, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x7f818152, 0x80008000, 0x007ffeae, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x02774000, 0x02753ffe, 0xfffefffe, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x00b6e004, 0x00b50000, 0xffff1ffc, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xffa7f8ee, 0xffe3f8ec, 0x003cfffe, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xffce0ff7, 0xffce0ff8, 0x00000001, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x0003ffc6, 0x0000ffca, 0xfffd0004, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x3fe03ffe, 0x3fe03ffe, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x0076034c, 0x0076034c, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x0001f7c2, 0x8000f801, 0x7fff003f, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x7fff0165, 0x7fff0164, 0x0000ffff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x815d8004, 0x7fff8000, 0xfea2fffc, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xfffc4036, 0x7ff97fc0, 0x7ffd3f8a, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x14dc0001, 0xfffb8000, 0xeb1f7fff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xc0204ccd, 0xc0018000, 0xffe13333, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x3990ce2b, 0x3a89cccc, 0x00f9fea1, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x800301b5, 0x000201b5, 0x7fff0000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x000dfffa, 0xfffefffa, 0xfff10000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x7ff92b49, 0x80000f0f, 0x0007e3c6, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x092b4ccd, 0xcf638000, 0xc6383333, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x8e2f55d5, 0xfff6007f, 0x71c7aaaa, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xffe3ef13, 0xffe3e003, 0x0000f0f0, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x80058000, 0x00000000, 0x7ffb8000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x00000002, 0x00000002, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x08818fff, 0x00010ffe, 0xf7807fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xb33303ae, 0x3333033f, 0x8000ff91, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x00000000, 0x0015c003, 0x0015c003, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x0f7fff00, 0x0ffeff00, 0x007f0000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x87fd0000, 0x07fc0000, 0x7fff0000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x7ff8e869, 0x7ffff003, 0x0007079a, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x0008471d, 0x80078000, 0x7fff38e3, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x800c0003, 0x7ffffffb, 0xfff3fff8, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x8012878e, 0x000c8004, 0x7ffaf876, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x1ffe8000, 0x1ffe8000, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xe38bf6bf, 0xe38efe19, 0x0003075a, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x80017fff, 0x00007fff, 0x7fff0000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xffb1666a, 0xffe70003, 0x00369999, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x0000800f, 0x8000000f, 0x80008000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x106c7fd7, 0x02c97fff, 0xf25d0028, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x7003c004, 0xf0030000, 0x80003ffc, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xfff98000, 0x7ff87fff, 0x7fffffff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x07fe72ff, 0x07fcf33e, 0xfffe803f, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x80018001, 0x00000000, 0x7fff7fff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x0000ff88, 0x7fffff85, 0x7ffffffd, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xc7198021, 0xc71c0020, 0x00037fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xfa9a1c72, 0xfa9ae38e, 0x0000c71c, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00eaffef, 0x0000ffee, 0xff16ffff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x70eb0004, 0x7ffa8004, 0x0f0f8000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0xfff9ff39, 0xfffaff39, 0x00010000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x00000001, 0x00000000, 0x0000ffff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x3ffeffcb, 0x3ffeffcb, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00008001, 0x7fff0000, 0x7fff7fff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x80003f79, 0x7fff3ff8, 0xffff007f, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x3b9dfc01, 0x1bbcfc01, 0xe01f0000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x8038fff5, 0x0037fff1, 0x7ffffffc, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x0046fff3, 0x0000fff6, 0xffba0003, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x7ffffe83, 0xfffffe83, 0x80000000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x7f687ff9, 0xff687fff, 0x80000006, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x10cfafe8, 0x00002fef, 0xef318007, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x8001e38d, 0x0000e38e, 0x7fff0001, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x8075f5ca, 0x00790000, 0x80040a36, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xff55d546, 0xff525555, 0xfffd800f, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x80030fff, 0x7fff0006, 0xfffcf007, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x5b757ffc, 0x80070000, 0x24928004, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xd5508002, 0x55550001, 0x80057fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xfffbfffd, 0x00000000, 0x00050003, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xffff0001, 0xffff8000, 0x00007fff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xc002f839, 0x0000f841, 0x3ffe0008, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xfffc0045, 0x0000003f, 0x0004fffa, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00710001, 0xfffe8000, 0xff8d7fff, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x80088d72, 0x00008e38, 0x7ff800c6, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xfffd0001, 0xfffd8000, 0x00007fff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x0ffb849c, 0x0ffc051b, 0x0001807f, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x80070004, 0x80007fff, 0xfff97ffb, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xfe1e0808, 0xfe1b00c7, 0xfffdf8bf, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xed7cfa6d, 0xedbbfa33, 0x003fffc6, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x00808001, 0x00000000, 0xff807fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xfffd0959, 0x7ffd03fe, 0x8000faa5, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xe0017269, 0xffff9249, 0x1ffe1fe0, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0xb42bffaf, 0xf41bffbd, 0x3ff0000e, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x3fe187af, 0x00007ff0, 0xc01ff841, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x0000ffd8, 0x0000ffd6, 0x0000fffe, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xe0027ff0, 0x0000ffef, 0x1ffe7fff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xf0090000, 0x00050000, 0x0ffc0000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x000d1289, 0x00020359, 0xfff5f0d0, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x80060005, 0x80078004, 0x00017fff, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x00000000, 0x275d7fff, 0x275d7fff, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x7ff5ffc0, 0x80007fff, 0x000b803f, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x7a0b5556, 0xfa0b0000, 0x8000aaaa, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00008002, 0x80008000, 0x8000fffe, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x00000000, 0xc00ffff1, 0xc00ffff1, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x800136db, 0x0000b6db, 0x7fff8000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xfffa0000, 0x1ff88000, 0x1ffe8000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x80010003, 0x00000000, 0x7ffffffd, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x7ffa8002, 0xfff90001, 0x7fff7fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x00000000, 0xffcf0007, 0xffcf0007, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0xffd43fc1, 0x00020000, 0x002ec03f, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x45598000, 0xf0030000, 0xaaaa8000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x8004ff4c, 0x00040000, 0x800000b4, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x36dc8ffc, 0xb6db0ffc, 0x7fff8000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x0000b1a8, 0x00003fe0, 0x00008e38, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xbfc176eb, 0x3fc0b6db, 0x7fff3ff0, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x7ff58e40, 0x80000007, 0x000b71c7, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x00000000, 0x7fff0007, 0x7fff0007, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x8a5d55d5, 0x0a5d007f, 0x8000aaaa, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x80027ff9, 0x00010000, 0x7fff8007, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x7faefffc, 0x80007fff, 0x00528003, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xe0127fff, 0x00028000, 0x1ff00001, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x7ffefef2, 0x7ffe0000, 0x0000010e, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xfc00e980, 0xfc01ffff, 0x0001167f, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00637804, 0x0063f803, 0x00007fff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x554fffe1, 0xfff90000, 0xaaaa001f, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00788008, 0x00000000, 0xff887ff8, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00000000, 0x7fff0000, 0x7fff0000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00087ffb, 0x8000fffa, 0x7ff87fff, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0xfcbe8040, 0x00000045, 0x03428005, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x0006f0f0, 0x0005f0f0, 0xffff0000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x0080e007, 0x0000e007, 0xff800000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x7ffb0406, 0xfffa0007, 0x7ffffc01, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xa4b2ffff, 0x2492ffff, 0x7fe00000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xb8e36010, 0x7fff8000, 0xc71c1ff0, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x005c7fff, 0x03767fff, 0x031a0000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0xfffb2492, 0x00002492, 0x00050000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00000000, 0x71c77fff, 0x71c77fff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x60038000, 0x7fff0000, 0x1ffc8000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x4ac4fe24, 0x0ae3fe25, 0xc01f0001, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x00007ffc, 0x7ffffffc, 0x7fff8000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x80000005, 0x00000007, 0x80000002, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x7ff507fe, 0x7fff0001, 0x000af803, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x7ff9dc91, 0xfff9c01f, 0x8000e38e, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xf73f0082, 0xfa37007d, 0x02f8fffb, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00008381, 0x80008000, 0x8000fc7f, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x03fffff0, 0x0000ffff, 0xfc01000f, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x12518000, 0x92490000, 0x7ff88000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x1fe0ffc9, 0x1fe0ffcc, 0x00000003, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xe0091ffc, 0x00011ffc, 0x1ff80000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x0ff98000, 0xfffc0000, 0xf0038000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x801f4040, 0x800f8000, 0xfff03fc0, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x3fe37fc5, 0x3ff07fff, 0x000d003a, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x7ffb0002, 0xfffb0002, 0x80000000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0xf8fefffa, 0xf8fe7fff, 0x00008005, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x333453d4, 0x0000d3db, 0xcccc8007, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x6658fffe, 0xfff1fffe, 0x99990000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x7ffc8042, 0xfffc0041, 0x80007fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x1f9c81c4, 0xffbb01c3, 0xe01f7fff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x7fa07ff9, 0x7fff8003, 0x005f000a, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x7ffa70f0, 0xfff97fff, 0x7fff0f0f, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x7f4bff03, 0xffcafffa, 0x807f00f7, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00007ffa, 0x00008000, 0x00000006, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x7ffcf884, 0xfffcf884, 0x80000000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x8002fffd, 0x7fff7ffc, 0xfffd7fff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x707203ff, 0xf0720000, 0x8000fc01, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x8000000d, 0x00000000, 0x8000fff3, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x4010f1c5, 0x80007ffd, 0x3ff08e38, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x7ffac003, 0x7ffaffff, 0x00003ffc, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00e0d392, 0x00fff003, 0x001f1c71, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x00008001, 0x80008000, 0x8000ffff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xb6dc8003, 0x00008000, 0x4924fffd, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x800ffff9, 0x000afff9, 0x7ffb0000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xb8e3ffb7, 0x7ffffff6, 0xc71c003f, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x800704de, 0x800704de, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xfff87bd3, 0xfff57fe0, 0xfffd040d, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00018020, 0x8000001f, 0x7fff7fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x7ff9fff8, 0x7ff8fffe, 0xffff0006, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x7fa273cb, 0x7fc0f3cb, 0x001e8000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00000000, 0x15632492, 0x15632492, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x1ff25fc1, 0x1ff83fe0, 0x0006e01f, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x0f13bcf1, 0x00001246, 0xf0ed5555, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x5556fe11, 0x0000fa71, 0xaaaafc60, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xc0070a19, 0xc007006d, 0x0000f654, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x80023fe4, 0x80003fe0, 0xfffefffc, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x7ffd7fae, 0xffffffad, 0x80027fff, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0xfffa7c02, 0xfffa8000, 0x000003fe, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x4dbaffff, 0xe003ffff, 0x92490000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x062effff, 0x00037fff, 0xf9d58000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xa0017c21, 0x1ffcfc01, 0x7ffb7fe0, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x8024ffff, 0x00237fff, 0x7fff8000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x2000f985, 0x3ff0fc01, 0x1ff0027c, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x7d7683ff, 0xfd6f03fe, 0x7ff97fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xd556e351, 0x5555e38e, 0x7fff003d, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x8163cccc, 0x0163cccc, 0x80000000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xff99ffde, 0xff8afffb, 0xfff1001d, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xfdd93ff5, 0x00001ffc, 0x0227e007, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x0000dffa, 0x00001ff8, 0x00003ffe, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x07fba413, 0xfffc7f80, 0xf801db6d, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x8ffcb9ba, 0x8003aaaa, 0xf007f0f0, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x7ff39ffc, 0xfff27fff, 0x7fffe003, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xfffa0f0f, 0xfffa0f0f, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00e6fffe, 0x00000000, 0xff1a0002, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x07ff01c1, 0x07feffe0, 0xfffffe1f, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xf0038006, 0xf0037fff, 0x0000fff9, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xfffce020, 0x00000000, 0x00041fe0, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x00058001, 0x7fff0000, 0x7ffa7fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x3ff1ff83, 0x0000ff82, 0xc00fffff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xff748001, 0xfff30000, 0x007f7fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x0248fffe, 0x0248fffe, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x0f0fdb31, 0xffffdb6d, 0xf0f0003c, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0xc00f8003, 0xc00f8003, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0xe2afc022, 0xfffbc01f, 0x1d4cfffd, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00000000, 0x7ffb8000, 0x7ffb8000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x3ff88005, 0x3ff80000, 0x00007ffb, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x49480ffc, 0x49240ffc, 0xffdc0000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xff817fd2, 0x8000ffd1, 0x807f7fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x796c8086, 0xf96b807f, 0x7ffffff9, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0xf8018001, 0xf8010000, 0x00007fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xdff6fc38, 0xe00f0000, 0x001903c8, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x8020065a, 0x8000ff39, 0xffe0f8df, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x803f0f78, 0x003f07fc, 0x8000f884, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0xdb6e0003, 0x00000000, 0x2492fffd, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x0ff00029, 0x0ff00029, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0xfa747fb8, 0x001cffb7, 0x05a87fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x9ff67ff4, 0x7ff9fff4, 0xe0038000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x7ff30000, 0x7fff7fff, 0x000c7fff, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x1fbd8000, 0xffc08000, 0xe0030000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x00000e12, 0x00000e12, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x7f8a8001, 0x80000000, 0x00767fff, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x80231ffc, 0x00231ffc, 0x80000000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x81bffd18, 0x01bf003f, 0x80000327, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x8f0f333d, 0x7fff0009, 0xf0f0cccc, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x0070802a, 0x00728003, 0x0002ffd9, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x40020001, 0x3ffe8000, 0xfffc7fff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x0000f803, 0x0000f803, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0xffee0001, 0xfffe8000, 0x00107fff, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x9249801b, 0x92490017, 0x00007ffc, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x7ffb0e0f, 0x7fff0000, 0x0004f1f1, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x81210f0f, 0x01210f0f, 0x80000000, 0x00000000, 0x00100000 + dspck_dstio subu.ph, 0x8001f989, 0x8000f989, 0xffff0000, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x87ff7fb3, 0x07fefff2, 0x7fff803f, 0x00100000, 0x00100000 + dspck_dstio subu.ph, 0x60078005, 0xe007fffd, 0x80007ff8, 0x00000000, 0x00000000 + dspck_dstio subu.ph, 0x87fea534, 0x7fff2534, 0xf8018000, 0x00100000, 0x00100000 + + writemsg "[36] Test subu_s.ph" + dspck_dstio subu_s.ph, 0x4008019c, 0x8000019c, 0x3ff80000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00007f50, 0x00008000, 0x000100b0, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x7fedaaaa, 0xffe6ffff, 0x7ff95555, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000981, 0x0019fffa, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x60010000, 0xe003f3f1, 0x8002ffff, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x71330023, 0x7f800023, 0x0e4d0000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x7ffe8000, 0x80008000, 0x00020000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7fabf071, 0x7fffff80, 0x00540f0f, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000010f, 0x0001010f, 0xffe30000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7fff8003, 0x7ffffffd, 0x00007ffa, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x0000403f, 0x7fc0c03f, 0xfffc8000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x1cdf1ff8, 0x7fff7fff, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x471d01fd, 0x8000fffe, 0x38e3fe01, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x3ff00ff8, 0xe0017fc0, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00030031, 0x00050037, 0x00020006, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x0ff90000, 0xfffa0000, 0xf0017ff8, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x807f000f, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000fff7, 0x03fafff9, 0x80030002, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0xda050000, 0xdb6d0000, 0x01680000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x3fff0000, 0x7ffb0103, 0x3ffc9999, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x7c740001, 0x7fff8000, 0x038b7fff, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x1ffe7ffa, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00007fbf, 0x7fc07ffe, 0xf0f0003f, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00007ff9, 0x7ff9fff9, 0x80078000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x7ffd0000, 0x80003ffc, 0x0003fbaa, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xffc70001, 0xffc78000, 0x00007fff, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0xa0030ff8, 0xe0010ff8, 0x3ffe0000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00008b6e, 0x0000fd35, 0x000071c7, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000cde, 0x80018000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000019, 0xff678000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00003ffe, 0x00053ffe, 0xff000000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x3ff90001, 0xfffa8000, 0xc0017fff, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0xdffdd110, 0xfff9e01f, 0x1ffc0f0f, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7ffc0000, 0xfffc0245, 0x8000ffc5, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000008, 0x0000ffe8, 0x3ffeffe0, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000e38e, 0x7ffcffff, 0x807f1c71, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x0000fbdf, 0x8000fffc, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x0006fbc8, 0x8005fffc, 0x7fff0434, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000f801, 0x0000f801, 0x80000000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x06fd18e5, 0x070338e3, 0x00061ffe, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x800001ce, 0x80008000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x000721a9, 0xfed1b6db, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7fff0000, 0x7fff0000, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x49238000, 0x4924ffff, 0x00017fff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00007ffb, 0x66668000, 0xe0070005, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0xffbaf752, 0xfffffffb, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x000000ff, 0xffc08000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x07fc0000, 0x07fc07fc, 0x0000fffe, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00006b3a, 0xf7817fff, 0xfd7a14c5, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00003ff0, 0x07feffff, 0x7fffc00f, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000ffdb, 0x7fffffdb, 0x803f0000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00007fff, 0x0028fe2a, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x2fe40000, 0xf0030005, 0xc01f007f, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xdfa30128, 0xff9b0128, 0x1ff80000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x7ffa0000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x638fc003, 0x8000c003, 0x1c710000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00007fff, 0x00007fff, 0xffc50000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x36dc0000, 0xb6db7fff, 0x7fff7fff, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x00018000, 0x8000fffc, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000ff6b, 0x0000ff6b, 0x80050000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xeeeb0000, 0xeeeb38e3, 0x0000ffdb, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000001, 0x007e8000, 0x1ff87fff, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x0003638e, 0x7fff7fff, 0x7ffc1c71, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x3fe80000, 0xc0070000, 0x801f7fff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x14340000, 0xffff0000, 0xebcbfffe, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xff290000, 0xff2d0000, 0x0004e01f, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x80000005, 0xffff7fff, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x036103fe, 0x03fe03fe, 0x009d0000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x6666f007, 0xfffffffc, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000807f, 0x0000807f, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x00007fff, 0x00008000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x09880000, 0x09888000, 0x00008000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fff0000, 0x80001e0a, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x00050ff8, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00040000, 0x00090000, 0x00058000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x001f0000, 0x801f3ff8, 0x80008000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00001fe0, 0x0ffc8000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xfffc6db6, 0xfffc6db6, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x0001dfe7, 0x8000dfe7, 0x7fff0000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x0e561ffc, 0x0ff8ffff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7fda0000, 0x80000000, 0x002600ad, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00007f00, 0x0000ff00, 0x00008000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00008000, 0x00018000, 0xaaaa0000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x8000c03f, 0x8000f332, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7f840006, 0x80008000, 0x007c7ffa, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xc01f0000, 0xc03f8000, 0x0020f0de, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0xff7a0000, 0xfff8fa66, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xc003002d, 0xc003002d, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x0000ffe8, 0xfffffffe, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x00000ffe, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x6b3d0000, 0x7fff0000, 0x14c20002, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0xffe7003f, 0xffe7003f, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fffe00f, 0xc3dbffff, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x012b0000, 0x012b7fff, 0x0000fff0, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000c76f, 0x8000d504, 0x80000d95, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x744d03b1, 0x7fff03b8, 0x0bb20007, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x7f57e00f, 0x8000e00f, 0x00a90000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x0002002f, 0x001dfffa, 0x001bffcb, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x8e380000, 0x8e388000, 0x0000ffa0, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fff0003, 0x7fff0003, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000001, 0x00000001, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x3dde0000, 0xffff8000, 0xc2218000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00007ff9, 0x007b7fff, 0xdb6d0006, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00008006, 0xffc78006, 0xffff0000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000e7f5, 0x0003e7f6, 0xffd90001, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x19996007, 0x9999e007, 0x80008000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x7ffc8000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x000016c2, 0x0000e38e, 0x7ffbcccc, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7fff0000, 0x7fff0000, 0x00008000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00061a54, 0x00061a54, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000fb7b, 0x07fcfb96, 0x7fff001b, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x03ac003c, 0x1fe00063, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x000036cc, 0x7fc07ff0, 0xfffd4924, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0xff673ffe, 0xffffffff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00007ffd, 0x1e797fff, 0x80000002, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x3f330000, 0xff340004, 0xc001ff80, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x15950000, 0x5555003f, 0x3fc0fc01, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x79dd0000, 0x7ffa03a5, 0x061d2492, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00550000, 0x0e140000, 0x0dbf0000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x00360000, 0x007cfe89, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000000f, 0x0006000f, 0xffc00000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x3ffc0000, 0xff89f003, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0xc0030000, 0xf0077fff, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x7fda7fe4, 0x80007fff, 0x0026001b, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7ffd0000, 0xfffc0000, 0x7fff0000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x000f7ffa, 0x1c71f2c4, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x7fff7fff, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x0ead0000, 0xe38e7fff, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x0000e003, 0x803fffc3, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fff8000, 0xf470ff39, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00017f40, 0x0001ff3f, 0x00007fff, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fff0000, 0xfffef001, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00001fd0, 0x00003fc0, 0x80001ff0, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x03cd0000, 0x03cf003d, 0x0002f001, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7ffd00ff, 0x800000ff, 0x00030000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00024001, 0x8001c001, 0x7fff8000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000006, 0x00008006, 0xffd58000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0xdfe40000, 0xe0030001, 0x001f0380, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fff803f, 0x7fffff76, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00377fff, 0xff007fff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000002, 0x80048002, 0xf0038000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xc001f003, 0xc001f003, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00001963, 0x00003953, 0x80051ff0, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fc027d2, 0x80008005, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fff7fff, 0xff417fff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0xfff8000d, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fe07fff, 0x7ffff803, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0xfcb08004, 0xfcb08004, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x0004fff9, 0xfffefff9, 0xfffa0000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7f1b0000, 0xff1b0007, 0x80008000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x007ffffe, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0xfef8f46d, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00008005, 0x0000fffe, 0xffe07ff9, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x80007ffe, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00001171, 0x0012f172, 0xe003e001, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00006719, 0x00dd7fff, 0x800018e6, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x70018002, 0xf0018002, 0x80000000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xff6a0000, 0xfffb7fff, 0x00918e38, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0xfff9100e, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x08aa0000, 0xe8ad0003, 0xe003ff53, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x7fc00000, 0xffc07fff, 0x80008003, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000789b, 0x00017fff, 0xf49e0764, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x0000fff8, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xfeeb0000, 0xffea8000, 0x00ffe38e, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x80000000, 0x80007fff, 0x00007fff, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0xfffb0000, 0xfffb0ffc, 0x00007fff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xf001efa8, 0xf001efb1, 0x00000009, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x0000003f, 0x00007fff, 0x004f7fc0, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7ffe197a, 0x7ffe7fe0, 0x00006666, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00001ff9, 0x7ffffffc, 0xfffee003, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x000048d1, 0x80004924, 0x80000053, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00090000, 0x8002e01f, 0x7ff9ff80, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xffb9000e, 0xffb9000f, 0x00000001, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x6004df6f, 0xe001e003, 0x7ffd0094, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x70f00000, 0x7fff800f, 0x0f0fffff, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000009, 0x7fff8001, 0xf0037ff8, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7ffd0000, 0x80007ffb, 0x0003803f, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x009403fe, 0x7fff8000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x19000001, 0x19000001, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00006004, 0x00068000, 0x7fc01ffc, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0xfffd8001, 0xfffd8001, 0x00000000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x7ffe7fff, 0x80007fff, 0x00020000, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x3ff60001, 0x3ffc8000, 0x00067fff, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x00030003, 0xfa0d1ff0, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0xc0038000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xfffd0012, 0xfffdfff2, 0x0000ffe0, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xb7240000, 0xf007000d, 0x38e3ffdd, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x124d0000, 0x1ffe8000, 0x0db1aaaa, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x22220000, 0xcccc0000, 0xaaaa0000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fff8000, 0xf30effff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x00548003, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x8000c003, 0x8000c003, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x02a20000, 0xffff8003, 0xfd5dfde3, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x3df40000, 0x3fc0000f, 0x01ccfd82, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x40080000, 0xc0071fe0, 0x7fff8000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00007ff3, 0x2634fff6, 0xffe28003, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00007fff, 0x7ffffff0, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0xfee47f81, 0xff008000, 0x001c007f, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x1ffc0000, 0xf803fff8, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000601f, 0x0ffe7fff, 0xc0071fe0, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x1ffc0002, 0x7ff08000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x80000000, 0x80000000, 0x0000fffe, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x7fff0000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00008000, 0x7fe0ffff, 0xf8037fff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fff38e3, 0x7fff8000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x248c0000, 0xfff98000, 0xdb6d8007, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0xfffe00c2, 0xfffe00c2, 0x00000000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xb6db0000, 0xb6dbe713, 0x0000fffe, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00006008, 0x0000e007, 0x80007fff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x8000c00f, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x8000c007, 0xfffffe44, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x00001ff0, 0x00003ff8, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x1ff082a2, 0x1ff08e38, 0x00000b96, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000eb0f, 0x1ffceb10, 0x1ffc0001, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x0000ffff, 0x0000ffff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00009238, 0x00009249, 0xfe070011, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00007f01, 0x0000ff00, 0x00057fff, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000060, 0x000f007f, 0x8000001f, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x92490000, 0xcafefffc, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x40090003, 0xc0018003, 0x7ff88000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x3ffc7fff, 0xfffbfee3, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fff8000, 0xffeffff1, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x0000f0f0, 0x0000f0f0, 0x00630000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0xc0010004, 0xfe7b8000, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0xdfe2ffcb, 0xe001fff0, 0x001f0025, 0x00000000, 0x00000000 + dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x00037ffb, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x7ffa7fff, 0x7ffa7fff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00340000, 0xffeef3a0, 0xffbaffe0, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xfffc7e0f, 0xfffcfd8f, 0x00007f80, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x7fff0000, 0x7fff040e, 0x0000fc42, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x7fff1ff0, 0x7fffdb6d, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0x800fcccc, 0xffd1e007, 0x00000000, 0x00100000 + dspck_dstio subu_s.ph, 0xfde40000, 0xfe1b002d, 0x003707c1, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0xfe100010, 0xffff0010, 0x01ef0000, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00007f18, 0x8000ff17, 0xc00f7fff, 0x00100000, 0x00100000 + dspck_dstio subu_s.ph, 0x00000000, 0xe0018000, 0xffa7fff0, 0x00100000, 0x00100000 + + writemsg "[37] Test subuh.qb" + dspck_dstio subuh.qb, 0x00f97100, 0x012fe3ff, 0x003c00ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x610100a6, 0xc303000c, 0x000000c0, 0x0, 0x0 + dspck_dstio subuh.qb, 0x638b7f01, 0xff15ff03, 0x38ff0000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0081087f, 0x050011ff, 0x05fd0001, 0x0, 0x0 + dspck_dstio subuh.qb, 0x1f7f767f, 0x3effffff, 0x00001200, 0x0, 0x0 + dspck_dstio subuh.qb, 0x810019d5, 0x020237aa, 0xff0205ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0580e57f, 0x0c0002ff, 0x02ff3800, 0x0, 0x0 + dspck_dstio subuh.qb, 0xd9800e03, 0x92001e07, 0xdfff0100, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7f417ffd, 0xfffffff8, 0x007c00fd, 0x0, 0x0 + dspck_dstio subuh.qb, 0x000847fe, 0x00118f14, 0x00010017, 0x0, 0x0 + dspck_dstio subuh.qb, 0xc6f07f1b, 0x0e59ff3c, 0x81790005, 0x0, 0x0 + dspck_dstio subuh.qb, 0x3800c597, 0xefff7e0e, 0x7efff3df, 0x0, 0x0 + dspck_dstio subuh.qb, 0x3ce67f29, 0x7839ff6b, 0x006c0119, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0180f4fe, 0x0200e000, 0x00fff803, 0x0, 0x0 + dspck_dstio subuh.qb, 0x03096182, 0xff20ff04, 0xf80d3cff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7f0dec00, 0xff1a0e00, 0x00003500, 0x0, 0x0 + dspck_dstio subuh.qb, 0x2f2ac993, 0x7e550426, 0x1f0071ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x077f0603, 0x0fff0c06, 0x00000000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x43ff7f00, 0xff00ff00, 0x78010000, 0x0, 0x0 + dspck_dstio subuh.qb, 0xe1ff008e, 0x8f00001b, 0xcc0100fe, 0x0, 0x0 + dspck_dstio subuh.qb, 0x04116af8, 0x0922fff0, 0x00002aff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xe6fc0080, 0x00000000, 0x330700ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x5adf06fe, 0xc71f0c00, 0x13600003, 0x0, 0x0 + dspck_dstio subuh.qb, 0x8310fd11, 0x02ff003d, 0xfcdf051b, 0x0, 0x0 + dspck_dstio subuh.qb, 0xd6fe7500, 0x0500f301, 0x58030901, 0x0, 0x0 + dspck_dstio subuh.qb, 0x054f47c2, 0x0a9fff3b, 0x000170b6, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00185cb9, 0x01ffc300, 0x00cf0b8e, 0x0, 0x0 + dspck_dstio subuh.qb, 0xc1e7dd87, 0x81012b00, 0xff3270f1, 0x0, 0x0 + dspck_dstio subuh.qb, 0x22007fea, 0x5803ff08, 0x13030033, 0x0, 0x0 + dspck_dstio subuh.qb, 0xf4783f8c, 0x01f17f07, 0x180000ef, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7402003f, 0xff050081, 0x17000003, 0x0, 0x0 + dspck_dstio subuh.qb, 0x07fc0400, 0x83011000, 0x75080700, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0080007e, 0xff00fffd, 0xffffff00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7f4f8836, 0xffff0f70, 0x0060ff04, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7fa00019, 0xff3f0033, 0x00ff0000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x78e56400, 0xf003e0ff, 0x003818ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xfe7b6a8e, 0x00fff300, 0x04081fe3, 0x0, 0x0 + dspck_dstio subuh.qb, 0x02fd00ba, 0x7a000074, 0x760600ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x82020b07, 0x0304190e, 0xff000200, 0x0, 0x0 + dspck_dstio subuh.qb, 0x007d5f00, 0x01ffbf01, 0x00040000, 0x0, 0x0 + dspck_dstio subuh.qb, 0xff000011, 0x00000040, 0x0200001d, 0x0, 0x0 + dspck_dstio subuh.qb, 0x37807a82, 0x7300ff03, 0x04ff0aff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x4c06d5fe, 0xf80caa00, 0x5f00ff04, 0x0, 0x0 + dspck_dstio subuh.qb, 0xd13c4181, 0x1e79f301, 0x7c0070ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xd78acdf5, 0x040c0866, 0x55f86d7c, 0x0, 0x0 + dspck_dstio subuh.qb, 0x2c817f82, 0x6601ff03, 0x0eff00fe, 0x0, 0x0 + dspck_dstio subuh.qb, 0x01c70802, 0x03751505, 0x00e70500, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00000000, 0x9fff0000, 0x9fff0000, 0x0, 0x0 + dspck_dstio subuh.qb, 0xc4ff00ff, 0x0f000000, 0x87020002, 0x0, 0x0 + dspck_dstio subuh.qb, 0xe6e307f7, 0x00010e0e, 0x333a001f, 0x0, 0x0 + dspck_dstio subuh.qb, 0x200e90c0, 0x401d0001, 0x0000e080, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7c76071c, 0xf9ff103f, 0x00130106, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00000000, 0x0e0200f1, 0x0e0200f1, 0x0, 0x0 + dspck_dstio subuh.qb, 0xc97db37f, 0x00ff33ff, 0x6d05cc00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x721c7710, 0xff39ff4a, 0x1a01102a, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00000000, 0x080805ff, 0x080805ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x37fc2508, 0x7e00c31f, 0x1007780f, 0x0, 0x0 + dspck_dstio subuh.qb, 0x11803e7d, 0x24007cff, 0x01ff0005, 0x0, 0x0 + dspck_dstio subuh.qb, 0x79f428fc, 0xffcf8103, 0x0ce7300b, 0x0, 0x0 + dspck_dstio subuh.qb, 0xc060c5f7, 0x00c04001, 0x7f00b613, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0002ba00, 0x00050300, 0x00018f00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x3fedca80, 0xff190400, 0x803f70ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x41c1fef9, 0xff0200f1, 0x7c8003ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x9cc4ff80, 0x00000000, 0xc77801ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7f5b607f, 0xffb6c1ff, 0x00000000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x78080002, 0xf1100004, 0x00000000, 0x0, 0x0 + dspck_dstio subuh.qb, 0xc080fe80, 0x00000000, 0x80ff03ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7ef1ebff, 0xfc0b4700, 0x00297002, 0x0, 0x0 + dspck_dstio subuh.qb, 0x9080efab, 0x0000c055, 0xe0ffe1ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0363e603, 0x07c7001c, 0x00003316, 0x0, 0x0 + dspck_dstio subuh.qb, 0x818f0086, 0x01000003, 0xffe100f7, 0x0, 0x0 + dspck_dstio subuh.qb, 0xe64761cc, 0x00ffff01, 0x33713c68, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7ffd4618, 0xff328f30, 0x01370200, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0040efc8, 0xffff148f, 0xff7e35ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xe8607f87, 0xcfc0ff0e, 0xff0000ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xf883e53f, 0x08052a7e, 0x18ff6000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x07bfb583, 0x0e183905, 0x0099cfff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00611f1f, 0x01ff40ff, 0x003c02c1, 0x0, 0x0 + dspck_dstio subuh.qb, 0xa52c00dd, 0x00660007, 0xb60e004d, 0x0, 0x0 + dspck_dstio subuh.qb, 0x3738f5ff, 0x6e7104f0, 0x000019f1, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00f800e6, 0x01000000, 0x000f0033, 0x0, 0x0 + dspck_dstio subuh.qb, 0x9e194f17, 0x2cffff3c, 0xefcc600e, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x86fc8000, 0x00000000, 0xf307ff00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x2da0f1f1, 0x5b1f0000, 0x00df1e1e, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00f07f8d, 0x00e0ff09, 0x00ff01ef, 0x0, 0x0 + dspck_dstio subuh.qb, 0x3ef4ff82, 0x7edffe04, 0x02f7ffff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x96eaf047, 0x2c4d58ff, 0xff787871, 0x0, 0x0 + dspck_dstio subuh.qb, 0xfbfe8182, 0x00010103, 0x0904ffff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0518fee8, 0x0a380f00, 0x00071330, 0x0, 0x0 + dspck_dstio subuh.qb, 0xfb07ffac, 0x00f10018, 0x0ae302bf, 0x0, 0x0 + dspck_dstio subuh.qb, 0x9880c46f, 0x300000e0, 0xffff7801, 0x0, 0x0 + dspck_dstio subuh.qb, 0x5e7f7184, 0xc3fff300, 0x060010f8, 0x0, 0x0 + dspck_dstio subuh.qb, 0xf3803cd5, 0x04007800, 0x1eff0055, 0x0, 0x0 + dspck_dstio subuh.qb, 0x22777921, 0xc1fffd49, 0x7c100a06, 0x0, 0x0 + dspck_dstio subuh.qb, 0x5a01f703, 0xcc033d07, 0x18004f01, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0866f7ff, 0x10ff6d00, 0x00337f02, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00000000, 0xf9030cff, 0xf9030cff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xf0fafa4e, 0xdf0b07fd, 0xff161260, 0x0, 0x0 + dspck_dstio subuh.qb, 0xe5faf003, 0x05f3000e, 0x3aff1f07, 0x0, 0x0 + dspck_dstio subuh.qb, 0xe20080f0, 0x15ff0000, 0x51ffff20, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7f35003e, 0xff710081, 0x00060004, 0x0, 0x0 + dspck_dstio subuh.qb, 0x19901c08, 0x4d003840, 0x1ae0002f, 0x0, 0x0 + dspck_dstio subuh.qb, 0x805b707b, 0x00b6fffc, 0xff001e06, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0c787989, 0x1ef1f302, 0x050000f0, 0x0, 0x0 + dspck_dstio subuh.qb, 0x007f0606, 0x00ff0c0c, 0x00000000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7ff859f7, 0xff00b6cf, 0x000f03e0, 0x0, 0x0 + dspck_dstio subuh.qb, 0x07fd002f, 0x11001f5e, 0x02061f00, 0x0, 0x0 + dspck_dstio subuh.qb, 0xfd8880d0, 0x000f0000, 0x06ffff60, 0x0, 0x0 + dspck_dstio subuh.qb, 0x660100ff, 0xff03ff00, 0x3200ff02, 0x0, 0x0 + dspck_dstio subuh.qb, 0x84cdea80, 0x010b5400, 0xf8717fff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7dbaff81, 0xff35fe02, 0x05c1ffff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00d08f00, 0x00991cff, 0x00f9fdff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xfffb7fff, 0x0005ff00, 0x010e0001, 0x0, 0x0 + dspck_dstio subuh.qb, 0xfc7f3dcc, 0x00fff927, 0x07007f8f, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7ff91d08, 0xff00fd3f, 0x000dc32e, 0x0, 0x0 + dspck_dstio subuh.qb, 0x81af0f8c, 0x01411f18, 0xffe301ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xf2ad0f18, 0xe321554b, 0xffc7371a, 0x0, 0x0 + dspck_dstio subuh.qb, 0xd718fcff, 0x0355f800, 0x5524ff01, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0cdd0341, 0x18040783, 0x00490001, 0x0, 0x0 + dspck_dstio subuh.qb, 0x12004ee1, 0x3c00c001, 0x1800243f, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7e00a633, 0xff0402ff, 0x0203b699, 0x0, 0x0 + dspck_dstio subuh.qb, 0x2c0ff073, 0x991fdfff, 0x4001ff19, 0x0, 0x0 + dspck_dstio subuh.qb, 0x77840073, 0xff00ffe7, 0x10f7ff00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x008000be, 0x00000000, 0x00ff0083, 0x0, 0x0 + dspck_dstio subuh.qb, 0xd5f1f002, 0x00000005, 0x551e2000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x72057b00, 0xfdccf900, 0x18c10300, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7977ff82, 0xf3ff1c03, 0x00101dff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xff7fc8f1, 0x00ff0838, 0x01007855, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0f5f8503, 0x1fc10907, 0x0002ff00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x3c9a00fc, 0x781400f8, 0x00df00ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7c7cfb00, 0xffffc300, 0x0707cc00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7f90c20e, 0xff1f001c, 0x01ff7c00, 0x0, 0x0 + dspck_dstio subuh.qb, 0xd32c00f4, 0x5d780130, 0xb6200047, 0x0, 0x0 + dspck_dstio subuh.qb, 0xe109f05f, 0xc11f60bf, 0xff0c7f00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x38abfe88, 0x71170010, 0x00c103ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7fc635fe, 0xff70bf02, 0x00e35506, 0x0, 0x0 + dspck_dstio subuh.qb, 0xc7ff0ef1, 0x8e02e002, 0xff03c31f, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7847b8fc, 0xf8990038, 0x070b8f3f, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7f004428, 0xffffc055, 0x00ff3805, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0e05e3fe, 0x30110200, 0x13063c03, 0x0, 0x0 + dspck_dstio subuh.qb, 0x1d00f102, 0x78010005, 0x3e001e00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x01ffd780, 0x02020000, 0x000352ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xfe05197d, 0x030a3cff, 0x06000905, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7cc47476, 0xff0cfffc, 0x0783170f, 0x0, 0x0 + dspck_dstio subuh.qb, 0x9f01abdb, 0x01035500, 0xc301ff49, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7a3c4c5f, 0xfff199df, 0x0b790020, 0x0, 0x0 + dspck_dstio subuh.qb, 0x607bf08e, 0xfff90700, 0x3f0226e3, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7c010082, 0xff020003, 0x060000ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x99817f00, 0x0102ff00, 0xcfff0100, 0x0, 0x0 + dspck_dstio subuh.qb, 0x03e8c992, 0xf7cf0224, 0xf0ff70ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xe9798103, 0x02f3013c, 0x3000ff35, 0x0, 0x0 + dspck_dstio subuh.qb, 0xc49aab9e, 0x00000000, 0x78ccaac3, 0x0, 0x0 + dspck_dstio subuh.qb, 0xb2a4804c, 0x584700aa, 0xf3ffff11, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7f803c06, 0xff007c10, 0x00ff0304, 0x0, 0x0 + dspck_dstio subuh.qb, 0x01642d87, 0x03cc5b0e, 0x000401ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x2f7f024c, 0x5fff0699, 0x00010100, 0x0, 0x0 + dspck_dstio subuh.qb, 0x77e200ff, 0xef000101, 0x003c0002, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00000b00, 0x01011700, 0x00000000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7f7ee8c2, 0xffffcf7c, 0x0003fff7, 0x0, 0x0 + dspck_dstio subuh.qb, 0x095f7101, 0x18c0ff03, 0x06011c00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7cf833f4, 0xff0066c7, 0x061000df, 0x0, 0x0 + dspck_dstio subuh.qb, 0xff0f09e2, 0x7f331200, 0x8114003c, 0x0, 0x0 + dspck_dstio subuh.qb, 0x920e77c0, 0x24fff30e, 0xffe3058e, 0x0, 0x0 + dspck_dstio subuh.qb, 0x6f5bfefd, 0xdfb60001, 0x01000406, 0x0, 0x0 + dspck_dstio subuh.qb, 0x8023032c, 0x00b6077e, 0xff700026, 0x0, 0x0 + dspck_dstio subuh.qb, 0x9698009e, 0x2b00ff3c, 0xffcfffff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00e40078, 0x0801fff1, 0x0738ff00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x6dfe0219, 0xfd000432, 0x23030000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x02000678, 0x04ff0cff, 0x00ff000e, 0x0, 0x0 + dspck_dstio subuh.qb, 0x8ff4a2ff, 0x00df0409, 0xe1f7c00b, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00ec00ae, 0x00180040, 0x003f00e3, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0063b8f9, 0x01ff0206, 0x00389213, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00fc809b, 0x00010035, 0x0009ffff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xe6fec900, 0xcc009202, 0xff03ff01, 0x0, 0x0 + dspck_dstio subuh.qb, 0x837f9d78, 0x06ff01ff, 0xff01c70f, 0x0, 0x0 + dspck_dstio subuh.qb, 0xecab0400, 0x15550800, 0x3cff0000, 0x0, 0x0 + dspck_dstio subuh.qb, 0xea810212, 0x10000624, 0x3cfe0100, 0x0, 0x0 + dspck_dstio subuh.qb, 0x1f430769, 0xff878fff, 0xc101812d, 0x0, 0x0 + dspck_dstio subuh.qb, 0x828d7f74, 0x0318ffff, 0xfffe0117, 0x0, 0x0 + dspck_dstio subuh.qb, 0x007bf8ff, 0x01fff003, 0x0109ff04, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00a6fb03, 0x01190608, 0x01cc0f01, 0x0, 0x0 + dspck_dstio subuh.qb, 0x8f8208f3, 0x1e011402, 0xfffc031c, 0x0, 0x0 + dspck_dstio subuh.qb, 0x3efa807f, 0x7e0100ff, 0x010cff01, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00f503f1, 0x000e0fdf, 0x002409fd, 0x0, 0x0 + dspck_dstio subuh.qb, 0x8aed2066, 0x053e41ff, 0xf0630033, 0x0, 0x0 + dspck_dstio subuh.qb, 0x80018100, 0x00030101, 0xff00ff00, 0x0, 0x0 + dspck_dstio subuh.qb, 0xd0490087, 0x1f92000e, 0x7f0000ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x6f7f7f00, 0xdfffff00, 0x01000000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x960000e8, 0x1dff0001, 0xf1ff0030, 0x0, 0x0 + dspck_dstio subuh.qb, 0xffede781, 0x00194c01, 0x023e7eff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00000000, 0x1c0101ff, 0x1c0101ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x61012b49, 0xc30256ff, 0x0000006c, 0x0, 0x0 + dspck_dstio subuh.qb, 0x40247fee, 0x81ffff00, 0x00b60024, 0x0, 0x0 + dspck_dstio subuh.qb, 0xc018a743, 0x07f015ff, 0x87c0c778, 0x0, 0x0 + dspck_dstio subuh.qb, 0x6d08700a, 0xdb10e115, 0x00000000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x54e094fc, 0xfd811c00, 0x55c1f308, 0x0, 0x0 + dspck_dstio subuh.qb, 0xf2ff80fc, 0x00000006, 0x1c01ff0d, 0x0, 0x0 + dspck_dstio subuh.qb, 0x37810001, 0x70010005, 0x01ff0002, 0x0, 0x0 + dspck_dstio subuh.qb, 0x40703cfe, 0x81ff7800, 0x001f0004, 0x0, 0x0 + dspck_dstio subuh.qb, 0x3300ff11, 0xc7ff0060, 0x60ff013e, 0x0, 0x0 + dspck_dstio subuh.qb, 0xa97f0800, 0x51ff1400, 0xff010300, 0x0, 0x0 + dspck_dstio subuh.qb, 0x06908110, 0x0e2002ff, 0x02ffffdf, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0ed5fe81, 0x1c000001, 0x005503ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7d414300, 0xff8effff, 0x050c78ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x079f3337, 0x0e3dff7f, 0x00ff9910, 0x0, 0x0 + dspck_dstio subuh.qb, 0x4701005f, 0x8f0301bf, 0x00000000, 0x0, 0x0 + dspck_dstio subuh.qb, 0xfe4f301f, 0x009f9fff, 0x03003ec1, 0x0, 0x0 + dspck_dstio subuh.qb, 0x369fd185, 0x70022408, 0x03c381fe, 0x0, 0x0 + dspck_dstio subuh.qb, 0x07ff80ff, 0xff070000, 0xf009ff01, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x87f6001e, 0x0e00ffff, 0xff14ffc3, 0x0, 0x0 + dspck_dstio subuh.qb, 0xee8078e4, 0x0c00ff07, 0x2fff0f3f, 0x0, 0x0 + dspck_dstio subuh.qb, 0xb0039a00, 0x002601ff, 0x9f1fccff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x1e7b3682, 0x3df9ff03, 0x010392ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0003c70c, 0x00ff8e18, 0x00f9ff00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0eb3ad1c, 0x1d663cfc, 0x00ffe1c3, 0x0, 0x0 + dspck_dstio subuh.qb, 0xa4818f1e, 0x45011e3c, 0xfcffff00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00001917, 0x00003332, 0x00000004, 0x0, 0x0 + dspck_dstio subuh.qb, 0x161f2c35, 0xf9bfb66b, 0xcc805d00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0cff87ff, 0x99000000, 0x8002f101, 0x0, 0x0 + dspck_dstio subuh.qb, 0x8c60b80b, 0x00c0001c, 0xe7008f06, 0x0, 0x0 + dspck_dstio subuh.qb, 0xf4f1497f, 0x3c7192ff, 0x538f0000, 0x0, 0x0 + dspck_dstio subuh.qb, 0xce1b002e, 0x0c3c006a, 0x7006000e, 0x0, 0x0 + dspck_dstio subuh.qb, 0x81ca0088, 0x01020f04, 0xff6d0ef3, 0x0, 0x0 + dspck_dstio subuh.qb, 0x6e8aac81, 0xff132801, 0x23ffcfff, 0x0, 0x0 + dspck_dstio subuh.qb, 0xf2f0f8e4, 0x00000000, 0x1c200f38, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0700007f, 0x0f0000ff, 0x00000000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00ff8207, 0xff00030f, 0xff01ff00, 0x0, 0x0 + dspck_dstio subuh.qb, 0xfea2825b, 0x010403db, 0x05bfff24, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0a473f87, 0x158e7f0e, 0x000000ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x4370419d, 0x87e0ff02, 0x00007cc7, 0x0, 0x0 + dspck_dstio subuh.qb, 0x7f71e7b0, 0xfffd0460, 0x001a36ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00000000, 0x00ff0099, 0x00ff0099, 0x0, 0x0 + dspck_dstio subuh.qb, 0xac7e1f2c, 0x19fc3f58, 0xc1000000, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00e80fef, 0x00cf2b33, 0x00fe0c55, 0x0, 0x0 + dspck_dstio subuh.qb, 0x00000000, 0x0e3fff00, 0x0e3fff00, 0x0, 0x0 + dspck_dstio subuh.qb, 0x817280fe, 0x01ff0000, 0xff1bff03, 0x0, 0x0 + dspck_dstio subuh.qb, 0xd8638166, 0x8fcc01ff, 0xdf05ff33, 0x0, 0x0 + dspck_dstio subuh.qb, 0xf89acb83, 0x08001d06, 0x18cc87ff, 0x0, 0x0 + dspck_dstio subuh.qb, 0x43c99b83, 0x87921103, 0x00ffdbfc, 0x0, 0x0 + dspck_dstio subuh.qb, 0xfe4b0273, 0x02ff3dff, 0x06683818, 0x0, 0x0 + dspck_dstio subuh.qb, 0x0064814b, 0x71cc0199, 0x7103ff03, 0x0, 0x0 + + writemsg "[38] Test subuh_r.qb" + dspck_dstio subuh_r.qb, 0xffea298d, 0x0004b601, 0x023165e7, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0f007e44, 0x40ffff87, 0x22ff0400, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x3a80387f, 0x7fff70ff, 0x0b000001, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0cb90b0f, 0x1c00251d, 0x058f1000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x4a2557c8, 0xc355bf00, 0x300c1270, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x7eff6a83, 0xff00e305, 0x04030fff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00790004, 0x07ff00ff, 0x080e00f8, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x7f807ff9, 0xffffff00, 0x0100010e, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x32250178, 0x7f4a0ef0, 0x1c010c00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x2e7c5a82, 0x64ffff00, 0x08074bfc, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x003e48fd, 0x007eff05, 0x0003700c, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xe1e719f9, 0x00003100, 0x3e33000f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x1e81fc81, 0x3f00f700, 0x04ffffff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x000c0000, 0xffff00ff, 0xffe701ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0be7157f, 0x16003ffe, 0x01321600, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf1a4002e, 0x000a015b, 0x1fc30100, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xff40920d, 0x018e0419, 0x030ee100, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf9621989, 0x00e03f10, 0x0e1c0eff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00020900, 0x00031200, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xc1952699, 0x70086030, 0xefdf14ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x8133891f, 0x00ff013e, 0xff99ef01, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xd082f89a, 0x8f000003, 0xeffd10cf, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xe2e73fcb, 0x0100ff23, 0x3d33818e, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00fd00b9, 0x00000000, 0x0007008e, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xb90066e0, 0x0000ff09, 0x8f013349, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x780d0003, 0xf0190006, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x66e8cec2, 0xffcf0000, 0x33ff657c, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x397deec3, 0xf0ff1b00, 0x7f06407b, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf0a110d6, 0x00012000, 0x20c00055, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x94050432, 0x270e0767, 0xff040003, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf400cd7c, 0x040099f7, 0x1c00ff00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x81b48102, 0x00670003, 0xffffff00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x806ec2b9, 0xffe10100, 0x00067e8f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x70121801, 0xe7239201, 0x07006200, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x15057cf4, 0x2b1fff00, 0x01160819, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x38f164ff, 0x8f00c700, 0x201e0002, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x7c028500, 0xffff0200, 0x07fcf900, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x016e3e07, 0x01db7fff, 0x000003f1, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xfe027d7f, 0x0705ffff, 0x0c020601, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x10f26433, 0x1f01c77c, 0x001d0017, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x7f8278fc, 0xff02fc02, 0x02ff0c0a, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x60910180, 0xc00001ff, 0x00df0000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x73041c01, 0xffff3b04, 0x19f70303, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x02baf30e, 0x0302e3ff, 0x008efde3, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xb17bfe81, 0x41ff0001, 0xe00904ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf4fe87fc, 0xaa190cc3, 0xc31dffcc, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x02001081, 0x0401ff00, 0x0001dfff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xc0f02539, 0x7e048771, 0xff243d00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x930081b9, 0x00000000, 0xdb00ff8f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0978fc92, 0xf8ff001c, 0xe71009f8, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf881cfef, 0x0e000d01, 0x1fff7024, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xff6d0802, 0x00e0102b, 0x02070027, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00f7cb01, 0x00003f03, 0x0113aa01, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x098100f9, 0x2000ff01, 0x0effff10, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x9d800055, 0x38ffffaa, 0xff00ff00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x847fb068, 0x00ff5dfd, 0xf802fe2d, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x280248ac, 0x710d8f16, 0x220900bf, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0111097e, 0x01257cff, 0x00046b04, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xfff7803c, 0x0000ffff, 0x03130087, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x847c302b, 0x00ff6056, 0xf8080000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xd0148000, 0x1028ffff, 0x710000ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x84cb6e00, 0x070ddb00, 0xff780000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x02003840, 0x04006f80, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x338b81ec, 0x66150000, 0x00ffff28, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xd60480fa, 0x01fffff3, 0x55f800ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xc1f83403, 0x0055e310, 0x7f667c0a, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x4300e380, 0x990000ff, 0x14003b00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf6e479bf, 0x00c7fe04, 0x14ff0c87, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00da0007, 0xff7fff0e, 0xffccff00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0400ff0c, 0x07000078, 0x00010360, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x2e7f9b00, 0xe3ff34ff, 0x8702ffff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x02636efc, 0x03c7e305, 0x0001070d, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x3cfd707a, 0x7d00e0ff, 0x0606000c, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00c702ff, 0xff7e031e, 0xfff10021, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x03401a7f, 0x058033ff, 0x00000002, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf11424b7, 0xe18e556d, 0xff660eff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0500a1fd, 0x100000f7, 0x0700bffd, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x800501fa, 0xff0a0300, 0x0000010c, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00000000, 0x0002782a, 0x0002782a, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0100fe33, 0x01000080, 0x0000051a, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x37ca01e9, 0x7c000204, 0x0e6c0032, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x06fd3a3c, 0x6c007583, 0x6107010c, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x01708a73, 0x01df03f8, 0x0000f013, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x52b8f9d2, 0xbf010002, 0x1c920f5f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xe298f7b1, 0xc30ae060, 0xffdbf3ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x88e58211, 0x002f0083, 0xf066fc62, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x85843fe4, 0x0206f9c7, 0xf8ff7cff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xc1b5ce7d, 0x800300ff, 0xff996405, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00000000, 0x00ff2007, 0x00ff2007, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xd17fa0c8, 0x28ff3e1e, 0x8701ff8f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00000000, 0x0f030100, 0x0f030100, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x81810002, 0x0000fff3, 0xffffffef, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x72de6801, 0xe300ff02, 0x00453000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x9ce82ad0, 0x3730559f, 0xff6001ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x04b91888, 0xff038000, 0xf89250f0, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0400001c, 0x07000037, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x81002d16, 0x00ff923e, 0xffff3812, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x797543c5, 0xf1ffc308, 0x00163e7f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x81710188, 0x00e1010e, 0xff0000ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x81000082, 0x01000000, 0xff0000fd, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00000000, 0x13180833, 0x13180833, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x374100c6, 0xfff7ff0a, 0x9275ff7e, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x1f2790b1, 0x7dcf0000, 0x4081e19f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x04fe1900, 0x07f836ff, 0x00fc04ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xc4fffaac, 0x04000138, 0x7c020de0, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x80000106, 0xff00010b, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0080e889, 0x00ff0f10, 0x000040ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xe0b7c107, 0x3f060028, 0x7f997f1b, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x398d41c1, 0x71188102, 0x00ff0081, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x37018480, 0x6d0206ff, 0x0000ff00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x8f0ae8cc, 0x003a0278, 0xe32733e1, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xc250f1f5, 0x83dfe008, 0xff40ff1f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x84847b10, 0x0707ff33, 0xffff0a14, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x017c80ff, 0x1ff7ff00, 0x1e000002, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x052bec05, 0x0bff000a, 0x01aa2900, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x08648000, 0x10c7ff00, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x91298042, 0x2054ff83, 0xff020000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x42308003, 0x8360ff12, 0x0001000d, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x801f0000, 0xff3d0000, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x01045212, 0x0c08bf23, 0x0b011c00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x03ffc106, 0x0500100e, 0x00038f02, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xecf00005, 0x58df000d, 0x80ff0003, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xfe036af0, 0x1be1ffdf, 0x1fdb2bff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0034fc48, 0xff73008f, 0xff0b0800, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0201a268, 0x0d0124df, 0x0a00e110, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x3e390581, 0x7c780900, 0x000600ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x826c8000, 0x02ffff00, 0xfe270000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x5bd6d380, 0xb60125ff, 0x01558000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x1f02390f, 0xfe03802b, 0xc1000e0e, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x690000e4, 0xffffffc7, 0x2effffff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x78816287, 0xff00ff0c, 0x10ff3cff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x6f3fc111, 0xff7e003f, 0x22017f1e, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x610b0407, 0xc116070e, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x80b2d8ff, 0xff638e00, 0x00ffdf03, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xfe7e88f6, 0x02ff0f0a, 0x0703ff1f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x05e8021f, 0x0a18043d, 0x00480000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x9e7a8100, 0x1fff0101, 0xe30bff01, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xfda0ca88, 0x00000000, 0x06c16df1, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xdc7a8080, 0x00ffffff, 0x490c0000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x7cfb79e8, 0xff00f1c7, 0x080b00f7, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x300f0b5e, 0xe73e16ff, 0x87200044, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x07820c7f, 0x0d02ffff, 0x00ffe701, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x375b8511, 0xffb60322, 0x9200f900, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x11ff3702, 0x2502ff03, 0x03049200, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00000000, 0xff0b011c, 0xff0b011c, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x4281d679, 0xff0178fc, 0x7cffcc0b, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x78800702, 0xf0ff0e03, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x02012180, 0x040141ff, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0001018d, 0x0002ff18, 0x0000feff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x7ac004e7, 0xf301080c, 0x0081013f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xa0009f02, 0x3eff0105, 0xffffc301, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xc47eb97a, 0x87ff00f3, 0xff038f00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x4200fe00, 0xff000e00, 0x7c001300, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00ebff81, 0x00550000, 0x008002ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xa102d362, 0x400499e1, 0xff00f31e, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x1c500304, 0x389f0507, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xff998181, 0x00000000, 0x03cfffff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xa26f8031, 0x04dffff3, 0xc1010092, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xe1fc2b80, 0x000755ff, 0x3e100000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf5777e90, 0x19fffd00, 0x2f1101e0, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x83807c87, 0x04ffff0d, 0xff0007ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x010f0ae7, 0x191e1800, 0x18000433, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x030000e2, 0x0e000003, 0x0900003f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xfb0300ed, 0x0a06ff01, 0x1500ff27, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x05007fe5, 0x0a03ff01, 0x00030238, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xb479ff84, 0x66ff0006, 0xff0e03ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x81f4f9ee, 0x0106022e, 0xff1e1152, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x01ffc300, 0x01010000, 0x00037b00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xff00fdfb, 0x00000000, 0x0300070a, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xeef481f8, 0x00000007, 0x2418ff18, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xfdfc807e, 0x7106ffff, 0x780e0003, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x253a7e62, 0xb673ffc3, 0x6d000400, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x76ff78e5, 0xef06ff03, 0x03090f39, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xff1a0300, 0x013306ff, 0x030000ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x897f8158, 0x0aff00b6, 0xf802ff07, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x7cf68131, 0xf7000076, 0x0015ff14, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xfa06e931, 0x132a0af0, 0x201e398e, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x393cc1b0, 0x717c005e, 0x00047eff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0a07401e, 0x140e7f3c, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x78020100, 0xff060100, 0x0f020000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x819d8000, 0x0039ffff, 0xffff00ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf1fce91e, 0x0107013c, 0x20103000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xa02dfdf1, 0x076092e0, 0xc70799ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00000000, 0xefff7107, 0xefff7107, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x3931ec80, 0x717f01ff, 0x001e2a00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x807fb237, 0xffff3f7e, 0x0001db10, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xc2009078, 0x83001ef7, 0xff01ff07, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x70ebe74c, 0xff4600cf, 0x1f713337, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x5f38fb08, 0xc07104ff, 0x03020ef0, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x5f6f0081, 0xbfe10700, 0x010308ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x807ffb88, 0xffff000e, 0x00010aff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0ccf0191, 0x497e0220, 0x32e100ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf93a07c8, 0x00920e0f, 0x0f1f007f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x6020ef82, 0xc03f1b03, 0x00003eff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00e20f81, 0x01006600, 0x013d49ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0e66ff15, 0xfce1002a, 0xe1150300, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xd7d4307f, 0x1f2460ff, 0x717c0002, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x209a6e81, 0x9f33ff00, 0x60ff24ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x805a807d, 0xffc0ffff, 0x000c0006, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0e7e2d10, 0x1efff32e, 0x0303990e, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x39022a89, 0x80035410, 0x0e0000ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x5c460bc1, 0xbf8f1701, 0x0703017f, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0a183f00, 0x16ff7f00, 0x02cf0200, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x92200efa, 0x223f1c00, 0xff00000c, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xfc01b9c0, 0x00010000, 0x08008f80, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x3933d6ac, 0x7166aa57, 0x0000ffff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0f880540, 0x1e0e0b80, 0x00ff0200, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xe93f08fe, 0x00ff2800, 0x2e811805, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x7318380e, 0xe730701c, 0x01000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x6100007f, 0xc10000fe, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x66088071, 0xcc10ffe1, 0x00000000, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xfdd3ad80, 0xf8240fff, 0xff7fb600, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf8008480, 0x0f0000ff, 0x1f00f900, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0ea87906, 0x1c10ff0f, 0x01c10e03, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00558100, 0x00ff00ff, 0x0055ffff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x400f80e8, 0x80ffffcf, 0x00e100ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x009a20fe, 0xff333f05, 0xffff000a, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x967b483f, 0x0fffff99, 0xe30a701c, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x3ea1424e, 0xff00879f, 0x83bf0403, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00000000, 0xff0106aa, 0xff0106aa, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x190100aa, 0x3301ff14, 0x0200ffc0, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x7fc18d28, 0xff811855, 0x02ffff05, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xc0000100, 0x000002ff, 0x810000ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x7c00d49a, 0xf8001833, 0x000070ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x00000000, 0x00b620ff, 0x00b620ff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x815b3ff1, 0x00ffff00, 0xfe49811e, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xdc504993, 0xb69f9200, 0xff0000db, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x046e3b8b, 0x07e07c05, 0x000507ef, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x24351981, 0xc3fc6000, 0x7c922eff, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0070830f, 0x00df041e, 0x0000ff00, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x0f1e3e98, 0x1e3eff2c, 0x010383fc, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x690000f8, 0xe10002e7, 0x0f0103f8, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x5e70128e, 0xc0e02702, 0x050004e7, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xe6bd7bc3, 0x0a78ff7c, 0x3fff09f7, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf2638104, 0xe0ff000b, 0xfc3aff03, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0xf5001802, 0x01003024, 0x18010020, 0x0, 0x0 + dspck_dstio subuh_r.qb, 0x013300f7, 0x01ffff01, 0x0099ff13, 0x0, 0x0 + + writemsg "[39] Test addqh.ph" + dspck_dstio addqh.ph, 0x24914000, 0x49247ffe, 0xffff0003, 0x0, 0x0 + dspck_dstio addqh.ph, 0x499dfffc, 0x7fff7ff9, 0x133b8000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x21effc3c, 0x03fe315c, 0x3fe0c71c, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3fffbf8f, 0x7fff8000, 0x0000ff1f, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc0420001, 0x00050002, 0x807f0000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x07fd0006, 0x0003000d, 0x0ff80000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x00022db6, 0x0004db6d, 0x00007fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffff00f9, 0x8000fff4, 0x7fff01ff, 0x0, 0x0 + dspck_dstio addqh.ph, 0x0000c001, 0x00000000, 0x00008002, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc0030443, 0x8000088a, 0x0007fffc, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf78015e5, 0xf0010bdb, 0xff001ff0, 0x0, 0x0 + dspck_dstio addqh.ph, 0x00031fea, 0x000dffd8, 0xfffa3ffc, 0x0, 0x0 + dspck_dstio addqh.ph, 0x09190ea3, 0xfffafd4a, 0x12381ffc, 0x0, 0x0 + dspck_dstio addqh.ph, 0xefcf3ff3, 0xe01fffe7, 0xff807fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc32d7fff, 0x065a7fff, 0x80007fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0x30033ffd, 0xe007fffc, 0x7fff7fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc7185c71, 0x8e3838e3, 0xfff87fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc6718000, 0x807f8000, 0x0c648000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfc46fffb, 0xf88d0000, 0x0000fff6, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffffdf7d, 0x7fffdb6d, 0x8000e38e, 0x0, 0x0 + dspck_dstio addqh.ph, 0x1fe0fe02, 0x3fc00003, 0x0000fc01, 0x0, 0x0 + dspck_dstio addqh.ph, 0xce38c000, 0x1c710000, 0x80008000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3fffd555, 0x7fffaaaa, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf0033ffc, 0xe0077ff9, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x7ffebcf7, 0x7fff803f, 0x7ffef9af, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf3c0c3fe, 0xe78007fc, 0x00008000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x0000fffb, 0x0000fff6, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x103dffff, 0x007f8000, 0x1ffc7fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0x401cc006, 0x7ffffffd, 0x003a800f, 0x0, 0x0 + dspck_dstio addqh.ph, 0x021e7fff, 0x021e7fff, 0x021e7fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xa2f0d8e7, 0xc5e0b6db, 0x8000faf4, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfff8ce38, 0x001f8000, 0xffd21c71, 0x0, 0x0 + dspck_dstio addqh.ph, 0x03fedb6d, 0x03fedb6d, 0x03fedb6d, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3ffffff8, 0x7ffffff0, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x17f3c71c, 0x3fe00000, 0xf0078e38, 0x0, 0x0 + dspck_dstio addqh.ph, 0xe00200af, 0xfffefffe, 0xc0070161, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf004401d, 0x00027fff, 0xe007003c, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3f960000, 0x7fff0000, 0xff2e0000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x05cff005, 0x0000e001, 0x0b9e0009, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfdd23ffe, 0xffa07fff, 0xfc04fffe, 0x0, 0x0 + dspck_dstio addqh.ph, 0xcd550000, 0xcd550000, 0xcd550000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x0c21f382, 0x0002ff91, 0x1841e774, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfc010dfe, 0xf8031ffc, 0x0000fc01, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3bf02450, 0xf8017fff, 0x7fe0c8a1, 0x0, 0x0 + dspck_dstio addqh.ph, 0x185affd2, 0xf0bc0181, 0x3ff8fe23, 0x0, 0x0 + dspck_dstio addqh.ph, 0x0785bfff, 0x0f0fffff, 0xfffc8000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xec20be41, 0xe00f8000, 0xf832fc82, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc0025fef, 0x00043fe0, 0x80007fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfff73fff, 0xffe07fff, 0x000e0000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc000c007, 0x00008000, 0x8000000f, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc2020e0a, 0x04041c14, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3fff036b, 0x7fff06d7, 0xffff0000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x4e3800a6, 0x1c7102f9, 0x7ffffe53, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfffdf205, 0x000003fc, 0xfffae00f, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf5c8003c, 0xea5d0005, 0x01330074, 0x0, 0x0 + dspck_dstio addqh.ph, 0xb803c002, 0xf0018006, 0x8005ffff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc003c010, 0x00018000, 0x80050020, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3c561c71, 0x38b538e3, 0x3ff80000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x40950e34, 0x7ffffff7, 0x012c1c71, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc0003fff, 0x80000000, 0x00007fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfc2fd75d, 0x001f1c71, 0xf83f9249, 0x0, 0x0 + dspck_dstio addqh.ph, 0x5999022f, 0x7fff0458, 0x33330007, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf3260006, 0xe0010000, 0x064b000c, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffebb878, 0xffd88000, 0xfffef0f0, 0x0, 0x0 + dspck_dstio addqh.ph, 0x8000cccc, 0x80009999, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3ffff031, 0x0000e003, 0x7fff005f, 0x0, 0x0 + dspck_dstio addqh.ph, 0x47470670, 0x7f800000, 0x0f0f0ce0, 0x0, 0x0 + dspck_dstio addqh.ph, 0x0ffeec4a, 0x1ffed8ab, 0xfffeffe9, 0x0, 0x0 + dspck_dstio addqh.ph, 0x03f9ffec, 0x07fcffd9, 0xfff70000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x38e3c924, 0x00000000, 0x71c79249, 0x0, 0x0 + dspck_dstio addqh.ph, 0xeaed0015, 0xaaaa002b, 0x2b300000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf35a407f, 0xe6b47fff, 0x000100ff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf8763511, 0xf0f0fc6c, 0xfffc6db6, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfe2603ff, 0x00000000, 0xfc4c07fe, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc00013b2, 0x00002747, 0x8000001d, 0x0, 0x0 + dspck_dstio addqh.ph, 0x40013ffe, 0x0003fffd, 0x7fff7fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xa38e0921, 0x80009249, 0xc71c7ff9, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfff8bc03, 0x80008003, 0x7ff0f803, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf8463fff, 0xf08d7fff, 0x0000ffff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffe3d907, 0xffc08000, 0x0007320e, 0x0, 0x0 + dspck_dstio addqh.ph, 0x1b6dffff, 0x7fff8000, 0xb6db7fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0x001f3fff, 0x803f7fff, 0x7fff0000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x01003fff, 0xfe020000, 0x03fe7fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf94ee071, 0x0000fffb, 0xf29cc0e7, 0x0, 0x0 + dspck_dstio addqh.ph, 0xff9ec00a, 0xff3c0005, 0x0000800f, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3003fb87, 0xe007f6c8, 0x7fff0046, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffcffe4c, 0xff9efc99, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x4096199c, 0x01343333, 0x7ff80006, 0x0, 0x0 + dspck_dstio addqh.ph, 0xbfff001b, 0xffff0001, 0x80000035, 0x0, 0x0 + dspck_dstio addqh.ph, 0xbffdff0f, 0xfffbfe1f, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfff83fff, 0x7ff00000, 0x80017fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xca63e002, 0x14c7c001, 0x80000004, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffffc020, 0x00000001, 0xfffe803f, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfffc0000, 0xfff80001, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffff0032, 0x7fff0064, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3ffb0000, 0x7ffa0000, 0xfffd0000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xbeb3af32, 0xfd638000, 0x8003de64, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc039fed1, 0x8000fda2, 0x00730000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfe540000, 0x00000000, 0xfca80000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3ffe78e3, 0xfffd71c7, 0x7fff7fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0x7fff07fc, 0x7fff07fc, 0x7fff07fc, 0x0, 0x0 + dspck_dstio addqh.ph, 0x7ff7c016, 0x7fffffed, 0x7ff0803f, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf0b70ff0, 0x00000000, 0xe16f1fe0, 0x0, 0x0 + dspck_dstio addqh.ph, 0x47fe4001, 0x7fff0003, 0x0ffe7fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0x0f85bff1, 0x1f028000, 0x0009ffe3, 0x0, 0x0 + dspck_dstio addqh.ph, 0xdb6dbf80, 0xb6dbff00, 0x00008000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x003f0006, 0x007f000c, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfffd8000, 0x7ffb8000, 0x80008000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xbfdc3fff, 0xffb87fff, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x00020000, 0x00040000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x2636ffa7, 0x7fff000f, 0xcc6eff40, 0x0, 0x0 + dspck_dstio addqh.ph, 0x7fffe003, 0x7fffe003, 0x7fffe003, 0x0, 0x0 + dspck_dstio addqh.ph, 0x402eeccb, 0x005d3ffe, 0x7fff9999, 0x0, 0x0 + dspck_dstio addqh.ph, 0x4033ccce, 0x7ff80003, 0x006f9999, 0x0, 0x0 + dspck_dstio addqh.ph, 0x201f8000, 0xc03f8000, 0x7fff8000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf800fde6, 0x00000000, 0xf001fbcd, 0x0, 0x0 + dspck_dstio addqh.ph, 0x000f26d6, 0x00700db4, 0xffaf3ff8, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf007ee48, 0xe00fe003, 0xfffffc8e, 0x0, 0x0 + dspck_dstio addqh.ph, 0x33f1fff7, 0x71c70003, 0xf61cffeb, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffff02f6, 0xffff02f6, 0xffff02f6, 0x0, 0x0 + dspck_dstio addqh.ph, 0x80000003, 0x80000007, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x7fffdfe0, 0x7fff8000, 0x7fff3fc0, 0x0, 0x0 + dspck_dstio addqh.ph, 0x4001bffe, 0x00038000, 0x7ffffffc, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfffe7ffc, 0xfffe7ffc, 0xfffe7ffc, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffff3ffc, 0xffff7fff, 0xfffffffa, 0x0, 0x0 + dspck_dstio addqh.ph, 0x404144a2, 0x1a1c0946, 0x66667fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffff1be1, 0x7fff3fc0, 0x8000f803, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc003ffff, 0x00068000, 0x80007fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfff2fffc, 0xffe4fff8, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x05f09b6d, 0xfffd8000, 0x0be4b6db, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3ffd2aaa, 0x7fff5555, 0xfffc0000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x022ec3bb, 0x045d0776, 0x00008000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xcb888e38, 0xcb888e38, 0xcb888e38, 0x0, 0x0 + dspck_dstio addqh.ph, 0xe01bc001, 0xc03f8000, 0xfff70002, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3cff1e30, 0x7fff1ff0, 0xfa001c71, 0x0, 0x0 + dspck_dstio addqh.ph, 0x8000c016, 0x8000002c, 0x80008000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf801ffff, 0xfffcffff, 0xf0070000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x47b88000, 0x0ff08000, 0x7f808000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x0000ffff, 0x00000000, 0x0000ffff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xbfff4001, 0xffff0003, 0x80007fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0x1ff7fff9, 0x3fe00001, 0x000ffff2, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf7d207f9, 0xffa2f003, 0xf0031ff0, 0x0, 0x0 + dspck_dstio addqh.ph, 0x018902df, 0x000705b8, 0x030c0006, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf8033d7a, 0xf0077fff, 0x0000faf6, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffbd3ff5, 0xfffcfff2, 0xff7e7ff9, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc000ecbb, 0x8000f5e9, 0x0000e38e, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfff309d7, 0xffe713b0, 0x0000ffff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfd35e2e9, 0xfaa50000, 0xffc5c5d3, 0x0, 0x0 + dspck_dstio addqh.ph, 0xbe00dff8, 0x80003ff0, 0xfc018000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfd45db6d, 0xfa86b6db, 0x00040000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x8002c001, 0x80008000, 0x80050003, 0x0, 0x0 + dspck_dstio addqh.ph, 0xff42d555, 0x00010000, 0xfe84aaaa, 0x0, 0x0 + dspck_dstio addqh.ph, 0x2b463801, 0x7ffff003, 0xd68e7fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0x01243fff, 0x02467fff, 0x00020000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc007e001, 0x800fc003, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfffc0fc8, 0x80001ff8, 0x7ff9ff99, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc0000ff8, 0x00010000, 0x80001ff0, 0x0, 0x0 + dspck_dstio addqh.ph, 0x000a3fff, 0x00000000, 0x00147fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc3ab8003, 0x07578000, 0x80008006, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffdee007, 0xffc0c00f, 0xfffc0000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x2003fffe, 0x7ffffffd, 0xc0070000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x00297fff, 0x01017fff, 0xff517fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0x80000e3d, 0x80001c71, 0x80000009, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3ff25ffe, 0x7fff3ffe, 0xffe57fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf678dff0, 0xf0f0ffe0, 0xfc01c001, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfffffffd, 0xfffffffd, 0xfffffffd, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf801f1c7, 0xf0030000, 0x0000e38e, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc000fff0, 0x00000000, 0x8000ffe0, 0x0, 0x0 + dspck_dstio addqh.ph, 0x80007fff, 0x80007fff, 0x80007fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfff6200f, 0xffec7fff, 0x0000c01f, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf1c7ffff, 0x00000000, 0xe38efffe, 0x0, 0x0 + dspck_dstio addqh.ph, 0x0517ffaa, 0x0000ff16, 0x0a2e003f, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf00f41bd, 0xe01f037c, 0x00007fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3ffe0000, 0x7ffd0001, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x0225f80e, 0x0002f007, 0x04480016, 0x0, 0x0 + dspck_dstio addqh.ph, 0xcc510003, 0xff090006, 0x99990000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x1c934005, 0x4924000b, 0xf0037fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xbf98c9da, 0xff3113b4, 0x80008000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xa56bc004, 0xcad48000, 0x80020008, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc00236de, 0x80050006, 0x00006db6, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3ffd004c, 0x7ffffffe, 0xfffb009b, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3e8058e2, 0x7ff071c7, 0xfd103ffe, 0x0, 0x0 + dspck_dstio addqh.ph, 0x0eedc110, 0xfddd01a1, 0x1ffe807f, 0x0, 0x0 + dspck_dstio addqh.ph, 0xefd70110, 0xffa80220, 0xe0070000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfc15fffe, 0xf840fffc, 0xffeb0000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf879c47b, 0x0003803f, 0xf0f008b7, 0x0, 0x0 + dspck_dstio addqh.ph, 0x08b0ffe0, 0x0db28000, 0x03ae7fc0, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfae70000, 0xf5ce0000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x2aaaff67, 0x0000fcb3, 0x5555021c, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc71effe8, 0x0005fff9, 0x8e38ffd8, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc3fe8000, 0x07fc8000, 0x80008000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x0001ff7f, 0x0002ff00, 0x0000ffff, 0x0, 0x0 + dspck_dstio addqh.ph, 0x1338ffff, 0x3ffcffff, 0xe674ffff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc001fffc, 0x80000000, 0x0002fff8, 0x0, 0x0 + dspck_dstio addqh.ph, 0x00003ff8, 0x0000fff2, 0x00007fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc0150000, 0x002a3ffe, 0x8000c003, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc71c0000, 0xc71c0000, 0xc71c0000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc89d0800, 0x92490004, 0xfef20ffc, 0x0, 0x0 + dspck_dstio addqh.ph, 0xd657c000, 0x02050000, 0xaaaa8000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xe007a00f, 0x0000c01f, 0xc00f8000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x8000fffc, 0x80000000, 0x8000fff8, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc07fc000, 0x80000000, 0x00ff8000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x014dc002, 0x029c8000, 0xfffe0004, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3ff80111, 0x7ff00222, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfff6005e, 0xfff0ffea, 0xfffc00d2, 0x0, 0x0 + dspck_dstio addqh.ph, 0x8000ce13, 0x8000ce13, 0x8000ce13, 0x0, 0x0 + dspck_dstio addqh.ph, 0xb009fffc, 0xe00f7ff8, 0x80048000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x00019555, 0x00008000, 0x0003aaaa, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfbc0bfff, 0xe003fffd, 0x177d8002, 0x0, 0x0 + dspck_dstio addqh.ph, 0xe00f007e, 0xc01f00fc, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf2f18002, 0x05e18004, 0xe0018000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffff0048, 0x7ffffd97, 0x800002f9, 0x0, 0x0 + dspck_dstio addqh.ph, 0xf0102b8c, 0xe0034924, 0x001d0df4, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfff50036, 0x000a0098, 0xffe0ffd5, 0x0, 0x0 + dspck_dstio addqh.ph, 0xff52c001, 0xfeac8000, 0xfff90003, 0x0, 0x0 + dspck_dstio addqh.ph, 0x05fa26e6, 0xe01f3309, 0x2bd61ac4, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc0003fff, 0x80007fff, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x00003fff, 0x00000000, 0x00007fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffdcfc01, 0xffaa0000, 0x000ff803, 0x0, 0x0 + dspck_dstio addqh.ph, 0xfff919d3, 0x00000000, 0xfff233a6, 0x0, 0x0 + dspck_dstio addqh.ph, 0x000101bf, 0x000203fe, 0x0000ff81, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3f933c28, 0xff2e3852, 0x7ff93ffe, 0x0, 0x0 + dspck_dstio addqh.ph, 0x00004786, 0x00000f0f, 0x00007ffd, 0x0, 0x0 + dspck_dstio addqh.ph, 0x80000ffa, 0x8000fffd, 0x80001ff8, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffff3fff, 0x80000000, 0x7fff7fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc0bb200f, 0x0157c01f, 0x801f7fff, 0x0, 0x0 + dspck_dstio addqh.ph, 0xe79e3fff, 0x24927fff, 0xaaaa0000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x5feff006, 0x3fe0e00f, 0x7ffffffe, 0x0, 0x0 + dspck_dstio addqh.ph, 0xbfff02fd, 0xffffff80, 0x8000067b, 0x0, 0x0 + dspck_dstio addqh.ph, 0x4002fffe, 0x0005fffc, 0x7fff0000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3fa4e081, 0xff49c003, 0x7fff00ff, 0x0, 0x0 + dspck_dstio addqh.ph, 0x3fff0000, 0x7fff0000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc0000002, 0x80000005, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xffeeb88b, 0xffe5e2df, 0xfff88e38, 0x0, 0x0 + dspck_dstio addqh.ph, 0x1f21fffc, 0xfffbfff8, 0x3e480000, 0x0, 0x0 + dspck_dstio addqh.ph, 0xd3d78000, 0x80008000, 0x27af8000, 0x0, 0x0 + dspck_dstio addqh.ph, 0x012cc011, 0x02558000, 0x00030022, 0x0, 0x0 + dspck_dstio addqh.ph, 0x0070c00d, 0x0000fffb, 0x00e0801f, 0x0, 0x0 + dspck_dstio addqh.ph, 0xc0031ffb, 0x00071ffe, 0x80001ff8, 0x0, 0x0 + dspck_dstio addqh.ph, 0x4a96fffe, 0x152d0000, 0x7ffffffc, 0x0, 0x0 + + writemsg "[40] Test addqh_r.ph" + dspck_dstio addqh_r.ph, 0x5feebfff, 0x7ffbfffe, 0x3fe08000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0001060c, 0x00020c18, 0x0000ffff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xf4f5fff9, 0xfffcfff2, 0xe9edffff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xe000391e, 0x80037fc0, 0x3ffcf27b, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3ffcf588, 0x7fffeb10, 0xfff90000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4000f06f, 0x7fff00be, 0x0000e01f, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x40030000, 0x00068000, 0x7fff7fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00a40007, 0x00ff000e, 0x00490000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x135dc000, 0x06c18007, 0x1ff8fff8, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfffd054b, 0xfff90aea, 0x0000ffac, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0004c001, 0x00078002, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xe0020000, 0xc0030000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0005bffa, 0x000f8000, 0xfffbfff4, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3c0040fc, 0xf8017fff, 0x7fff01f9, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x38ed8003, 0x00128000, 0x71c78005, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xffff3fd0, 0xfffd7fc0, 0x0000ffe0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0fedffff, 0xfffe7ffd, 0x1fdc8000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xcb2047fb, 0xc9747ffd, 0xcccc0ff8, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xb0082ffe, 0x8000e001, 0xe00f7ffa, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x088cc526, 0x1117f803, 0x00009249, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc00d4953, 0x80007fff, 0x001a12a6, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x76db3fc0, 0x6db60000, 0x7fff7f80, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xffdfbff3, 0xfffdffe6, 0xffc08000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4ffc000e, 0x7fff001c, 0x1ff80000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xbfe3f7f1, 0xffc6f001, 0x8000ffe0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xffbf1620, 0xfffffdb2, 0xff7e2e8e, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4000bfff, 0x7ffffffe, 0x00008000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3ffefffa, 0xfffde003, 0x7fff1ff0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc0161ff8, 0x80050000, 0x00263ff0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xb333fff4, 0xccccffe9, 0x9999fffe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00002fff, 0xffffe003, 0x00007ffa, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0750400f, 0x0ea37fff, 0xfffc001f, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xffff0000, 0xffff0000, 0xffff0000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x30010c2d, 0xe0031866, 0x7ffffff3, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc000ff4a, 0x8000fe93, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x1f08ffbb, 0x3e140000, 0xfffbff76, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3ffff6d2, 0xffff0000, 0x7fffeda3, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0000eedf, 0x00000000, 0x0000ddbe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x7ff85ffe, 0x7ff07fff, 0x7fff3ffc, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0001000f, 0x0002801f, 0x00007fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc0033d92, 0x8000fb24, 0x00067fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x1ff22ab4, 0x7fe00013, 0xc0035555, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xffff0000, 0xffff0000, 0xffff0000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x078823df, 0x000007fe, 0x0f0f3fc0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x7fff07ff, 0x7fff0ffe, 0x7fff0000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x2691ffff, 0x49248000, 0x03fe7ffd, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x40000007, 0x00000000, 0x7fff000d, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0000c401, 0xffff07fe, 0x00008004, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfcd9ffff, 0xfd46ffff, 0xfc6bffff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xffffff34, 0x3ffcfe69, 0xc001ffff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x7fc00ffe, 0x7fc00ffe, 0x7fc00ffe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x44f338da, 0x7fff6db6, 0x09e603fe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xffafff3a, 0xff5dfe70, 0x00000003, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x1c280ff8, 0xfffd0000, 0x38531ff0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0000c05a, 0x7fff00b3, 0x80008000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0000dff9, 0x7ffffff1, 0x8000c001, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x11c707fe, 0x238d0004, 0x00010ff8, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x2a6b8000, 0xff808000, 0x55558000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xf8e4bfe3, 0x71c7ffc5, 0x80018000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3f4807fb, 0xfe910ff8, 0x7ffffffe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xe279c000, 0xc4f28000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0ffe1fe4, 0x1ffcffd8, 0x00003ff0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0000fffe, 0x80008000, 0x7fff7ffc, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x47ff3ff4, 0x7fff3ff0, 0x0ffe3ff8, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xff310000, 0xff610000, 0xff00ffff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfd700003, 0x00000000, 0xfae00005, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0000fff7, 0x0000ffef, 0x0000ffff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc0010ccc, 0x80009999, 0x00017fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4b5bc08d, 0x16b6803f, 0x7fff00da, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x03a4fff0, 0x03a4fff0, 0x03a4fff0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x1ffc2000, 0x3ff80003, 0x00003ffc, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00203ff0, 0x00000000, 0x003f7fe0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xe00103eb, 0xfffeffff, 0xc00307d6, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x7fff000a, 0x7fff0013, 0x7fff0000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00070032, 0x000a0066, 0x0004fffe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xe008c0be, 0xc00f8000, 0x0000017c, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xffed0a23, 0xffda093f, 0x00000b07, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xffebc000, 0x00000000, 0xffd68000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x400047ee, 0x7fff7fe0, 0x00000ffc, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3fe08000, 0x3fe08000, 0x3fe08000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4000e666, 0x00000000, 0x7fffcccc, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x1d6ffff1, 0xffffffe0, 0x3ade0001, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x1fe0f8e4, 0x3fc08000, 0xffff71c7, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x400cbfd9, 0x7ff9ffaf, 0x001f8003, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x03fde672, 0x07fc0018, 0xfffecccc, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00015ff0, 0x00003fe0, 0x00027fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x000f0001, 0x00060001, 0x00170000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xf1c7407e, 0xe38e7fc0, 0xffff013c, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xf801ffdb, 0x00000000, 0xf001ffb5, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00021ffe, 0x00000000, 0x00033ffc, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0924ffe3, 0x7fffffc0, 0x92490005, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc1bf0000, 0x80007fff, 0x037e8000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x401ac000, 0x7fff8000, 0x00350000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xf800c000, 0xf0010000, 0xfffe8000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x36db3fde, 0x00007fff, 0x6db6ffbd, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xe37dff9c, 0xc00f0000, 0x06ebff38, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x400b0013, 0x00170016, 0x7fff000f, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3ec44ffe, 0xfd8c1ffc, 0x7ffc7fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x07fc0000, 0x0ff80000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xbff80028, 0xffef001c, 0x80000033, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfe5a033c, 0xfcad06b1, 0x0006ffc6, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xffff0003, 0xfffd0000, 0x00000005, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfffe0000, 0xfffc0000, 0x0000ffff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x1fe4c007, 0xffcc8000, 0x3ffc000e, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfffd1d44, 0xffff3fc0, 0xfffafac7, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x7fe0087e, 0x7fc010fc, 0x7fff0000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x02ebffd0, 0x01d8ff9f, 0x03fe0000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00018000, 0x00018000, 0x00008000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x803f004e, 0x803f004e, 0x803f004e, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3ff0bff2, 0x7fe08003, 0x0000ffe1, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x007ffc77, 0x00fff0f0, 0xffff07fe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3ffd4000, 0xfffb0000, 0x7fff7fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x000000fe, 0x000000fe, 0x000000fe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xbfffffd1, 0x8000fff9, 0xfffeffa8, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x40004000, 0x00007fff, 0x7fff0000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc000083f, 0x0000007f, 0x80000ffe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x401f7fff, 0x7fff7fff, 0x003f7fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc0000005, 0x0000ffeb, 0x8000001f, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x001ebf26, 0xfffcfe4c, 0x003f8000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xbfab7fff, 0xff557fff, 0x80007fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3c20c008, 0x7ffa000f, 0xf8458000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x01564ff8, 0x02ad1ff0, 0xffff7fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3ffebfd9, 0xfffd801f, 0x7fffff92, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x47fffffd, 0x0ffefffa, 0x7fff0000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0076bffe, 0x0000fffc, 0x00ec8000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfe8b0000, 0x00000000, 0xfd160000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xffe1c000, 0x00018000, 0xffc0ffff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00003fe0, 0x0000ffc0, 0x00007fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4000ff3a, 0x7fffff73, 0x0000ff00, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3334fff4, 0x0001ffeb, 0x6666fffc, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00914000, 0x031d0000, 0xfe057fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x800001ce, 0x80000000, 0x8000039c, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3ffa4000, 0x7ffc7fff, 0xfff80000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfc01400a, 0xf0030014, 0x07fe7fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4232fce5, 0x7ffff9c9, 0x04650000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0000bffd, 0x8000fffa, 0x7fff8000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xeae70000, 0xd5a90000, 0x00250000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x27df4003, 0x0ffe0006, 0x3fc07fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfffcffae, 0x0000ffff, 0xfff8ff5c, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00031fe0, 0x00050000, 0x00003fc0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfed84000, 0xfdb47fff, 0xfffb0000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x03df0011, 0x07fe0006, 0xffc0001b, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x119afffe, 0x119afffe, 0x119afffe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00002e23, 0x80003333, 0x7fff2913, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xdfe0ffff, 0x3fc0fffe, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xd555c93a, 0x0000002b, 0xaaaa9249, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x73330000, 0x7fff8000, 0x66667fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00002492, 0x00000000, 0x00004924, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3ffd0017, 0x7fff0061, 0xfffaffcd, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfe280000, 0xfc4f8000, 0x00007fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc00c7fff, 0x80027fff, 0x00167fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00008000, 0xffff8000, 0x00018000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x2aa60788, 0x55550000, 0xfff60f0f, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc3fe023c, 0x80000479, 0x07fcffff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4000078b, 0x00000006, 0x7fff0f0f, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xb801402c, 0xf0017fff, 0x80000059, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfffeff7f, 0xfffcfffe, 0x0000ff00, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfe264000, 0x00000000, 0xfc4b7fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0fffbff3, 0x1ffeffe6, 0x00008000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xdfeef01c, 0xff9c0018, 0xc03fe01f, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc000c000, 0x00008000, 0x8000ffff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x7fdc4032, 0x7fc00065, 0x7ff87fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00107fff, 0x00007fff, 0x001f7fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00000004, 0x00050001, 0xfffb0006, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xff7d0032, 0xfeff0006, 0xfffb005d, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x40d1c001, 0x7ff88000, 0x01aa0001, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc000fdf9, 0x0000fc01, 0x8000fff0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x1b9e7fee, 0x375c7fe0, 0xffdf7ffb, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3ff94009, 0x7fff0012, 0xfff27fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x95570814, 0x8004002c, 0xaaaa0ffc, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xbfffee11, 0x8000e001, 0xfffefc21, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xbf0ec1ff, 0xfe1c8000, 0x800003fe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc3923fbb, 0xc0077fff, 0xc71cff77, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x803f7ffa, 0x803f7ffa, 0x803f7ffa, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc0001237, 0x80001c71, 0x000007fc, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xe00441ff, 0x000003fe, 0xc0077fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00003ffc, 0x80007ff8, 0x7fff0000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3fff1fe0, 0xffff0000, 0x7fff3fc0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0000f043, 0x0000007f, 0x0000e007, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00003fc0, 0x00007f80, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x2aa98000, 0xfffd8000, 0x55558000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3ffff860, 0x7fff0000, 0xfffef0bf, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4000c000, 0x7fff8000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xffff0001, 0xfff80001, 0x00060001, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfff91b6b, 0xfff27ffa, 0x0000b6db, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc0000002, 0x00000000, 0x80000004, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xf47af551, 0xf8033ff8, 0xf0f0aaaa, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc925c000, 0x00008000, 0x92490000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xf7f2e561, 0xf00303a6, 0xffe0c71c, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x5c71c000, 0x7fff8000, 0x38e30000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x1fe01265, 0x00000ad3, 0x3fc019f7, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xe7e9c019, 0xc007002b, 0x0fca8006, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4187bea9, 0x7ffffd51, 0x030f8000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x5fe85fff, 0x3fe03ffe, 0x7ff07fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x2491c3fe, 0x492407fc, 0xfffd8000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xf879fff2, 0xf0f00000, 0x0002ffe3, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x40412003, 0x7fffc007, 0x00837fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4003e58a, 0x0006fffe, 0x7fffcb15, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0003fffe, 0x0006fffb, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4fffc36c, 0x7fff803f, 0x1ffe0699, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xcccd0003, 0x99990006, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0002ffff, 0x00000000, 0x0004fffd, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xcccf1d19, 0x00053a31, 0x99990000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xf7ff4007, 0xf0017fff, 0xfffc000f, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xcccd38e4, 0x999971c7, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xb96cefc8, 0xf2d8fc01, 0x8000e38e, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x7fbee008, 0x7ffb0001, 0x7f80c00f, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc0043f90, 0x00087fff, 0x8000ff20, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfb09bfff, 0xf6168002, 0xfffbfffc, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x4003bffd, 0x00078000, 0x7ffffffa, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x43ff0000, 0x07fe7fff, 0x7fff8000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x5ff0fffb, 0x7ffffff9, 0x3fe0fffd, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc002eff9, 0x8000ffeb, 0x0004e007, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc24b8000, 0x80018000, 0x04948000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x76db41ff, 0x6db67fff, 0x7fff03fe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xa0213000, 0x8002e001, 0xc03f7fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x53c05ff8, 0x27817fff, 0x7fff3ff0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xf8041000, 0xf0070001, 0x00001ffe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x020232f3, 0x03feff80, 0x00066666, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xff0efffe, 0xff0efffe, 0xff0efffe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x003efe5f, 0x007f0000, 0xfffcfcbd, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xbff03000, 0xffe07fff, 0x8000e001, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x119d4000, 0x33330000, 0xf0077fff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc0003ff8, 0x80007ff0, 0x0000ffff, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x023102dc, 0x00000000, 0x046205b8, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xfd870924, 0xfff57fff, 0xfb189249, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x07fa000f, 0xfffc001f, 0x0ff8fffe, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xb0ff0000, 0xe1fd0000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x3fff3be1, 0x7ffff801, 0xffff7fc0, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xc007ffe4, 0xc007ffe4, 0xc007ffe4, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xede476db, 0xfbc67fff, 0xe0016db6, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0xbffefe68, 0x8000fffb, 0xfffcfcd5, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0001bffc, 0x00018000, 0x0001fff8, 0x0, 0x0 + dspck_dstio addqh_r.ph, 0x0000ffda, 0xffffffd4, 0x0000ffe0, 0x0, 0x0 + + writemsg "[41] Test subqh.ph" + dspck_dstio subqh.ph, 0xffb9d590, 0xff620075, 0xfff05555, 0x0, 0x0 + dspck_dstio subqh.ph, 0xdb6ec05f, 0xb6db807f, 0xffffffc0, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000000, 0x7fff0000, 0x7fff0000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfc01ffff, 0xf803fffe, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x410507b2, 0x021aff6b, 0x800ff007, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbff9006b, 0x800000d4, 0x000dfffd, 0x0, 0x0 + dspck_dstio subqh.ph, 0xf8040000, 0x00007fff, 0x0ff87fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x1c2cfff8, 0x2db40000, 0xf55b000f, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3ff8a054, 0x7fffc0a8, 0x000f7fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc0003fff, 0x00007fff, 0x7fff0000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfff5eff7, 0xfff1ffec, 0x00061ffe, 0x0, 0x0 + dspck_dstio subqh.ph, 0xff80bff6, 0x0000ffec, 0x00ff7fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfff10000, 0xffe18000, 0xfffe8000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x1000fcb7, 0x3ffeff00, 0x1ffe0591, 0x0, 0x0 + dspck_dstio subqh.ph, 0x002038e4, 0x00000000, 0xffc08e38, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbffd4004, 0xfffa0009, 0x7fff8000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0002ffef, 0x0000ffe0, 0xfffb0001, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0000079a, 0x00000f7d, 0x00000049, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0000c56c, 0x80000ad7, 0x80007fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x07ff3f83, 0x0ffe7fff, 0x000000f9, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbf5f0000, 0x801f0000, 0x01610000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3fb9bbcd, 0xff738000, 0x80000865, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0001f248, 0x0003e487, 0x0000fff7, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc3fffe89, 0x80000000, 0xf80102ed, 0x0, 0x0 + dspck_dstio subqh.ph, 0x7fff31c7, 0x7fffe38e, 0x80008000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x038a01cc, 0x0315ff9a, 0xfc01fc01, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc04643ff, 0x008b07fe, 0x7fff8000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00005ffe, 0x00007fff, 0xffffc003, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3fffc000, 0x7fff8000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x56d70ffe, 0x3ff81ffc, 0x92490000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xffff0001, 0x00000000, 0x0001fffe, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000000, 0xf81f7fff, 0xf81f7fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x35e20000, 0xfe0e0000, 0x92490000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000000, 0x0000fff9, 0x0000fff9, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc000bff9, 0x0000fff1, 0x7fff7fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc001fffa, 0x8002fff4, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x4603fffc, 0x7fff0000, 0xf3f80007, 0x0, 0x0 + dspck_dstio subqh.ph, 0xffff41f5, 0xffff03eb, 0x00008000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x000050ae, 0x80007fff, 0x8000dea2, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfffeff46, 0xfffcfe8d, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x266601ff, 0x7fff0000, 0x3333fc01, 0x0, 0x0 + dspck_dstio subqh.ph, 0xf081c04c, 0x00fa0098, 0x1ff87fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3fe00c4a, 0x7ffffff5, 0x003fe760, 0x0, 0x0 + dspck_dstio subqh.ph, 0x7fffe022, 0x7fffc03f, 0x8000fffa, 0x0, 0x0 + dspck_dstio subqh.ph, 0x47ff3ff8, 0x7fff0000, 0xf001800f, 0x0, 0x0 + dspck_dstio subqh.ph, 0x40d2f007, 0x01a5e00f, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00407fff, 0x00017fff, 0xff808000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x4003ff3a, 0x7fffff1a, 0xfff800a5, 0x0, 0x0 + dspck_dstio subqh.ph, 0xffff0e6f, 0xfffe1cd7, 0x0000fff8, 0x0, 0x0 + dspck_dstio subqh.ph, 0x8002c035, 0x8003006a, 0x7fff7fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x8000bff8, 0x80008000, 0x7fff000f, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbfed0000, 0xffda0000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc0004ffc, 0x80001ff8, 0x00008000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x40030062, 0x7fff00c3, 0xfff9ffff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000010, 0x00000000, 0x0000ffe0, 0x0, 0x0 + dspck_dstio subqh.ph, 0x03fec010, 0x00000000, 0xf8037fe0, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfa8303ff, 0xf5040000, 0xfffef801, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfffdff7c, 0x80000000, 0x80060107, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbf96dc72, 0xff2b8000, 0x7fffc71c, 0x0, 0x0 + dspck_dstio subqh.ph, 0x30070002, 0xe00f0004, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc000e003, 0x8000c007, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0000c925, 0x00000000, 0x00006db6, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000000, 0xfff90000, 0xfff90000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xff15c713, 0xfe378e38, 0x000d0011, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc01fffe0, 0x803f7fc0, 0x00007fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfffefffd, 0xfffd0000, 0x00000006, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3ffbffff, 0xfff7fffe, 0x8000ffff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0ffe00bd, 0x1ffc017a, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0000e669, 0x8000cccc, 0x8000fffa, 0x0, 0x0 + dspck_dstio subqh.ph, 0xffff3fff, 0xfffffffe, 0x00008000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x7ffc39b4, 0x7ff8f369, 0x80008000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xf805c000, 0x00038000, 0x0ff80000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbfff00aa, 0x8000016a, 0x00020015, 0x0, 0x0 + dspck_dstio subqh.ph, 0xebfe0001, 0xdb6d0000, 0x0370fffe, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00002000, 0x00007ff8, 0x00003ff8, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3f7e0040, 0xfefc007f, 0x8000fffe, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3fbf08e1, 0x7f8011c1, 0x0001fffe, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc004dffe, 0x80078000, 0xfffec003, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfe10f010, 0xfc270000, 0x00061fe0, 0x0, 0x0 + dspck_dstio subqh.ph, 0x1ffdfffb, 0xfffe0006, 0xc003000f, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000000, 0xfff60000, 0xfff60000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x40073fff, 0x7fff7fff, 0xfff00000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x07ffc96a, 0x0ffe8001, 0x0000ed2d, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc000f47d, 0x00000000, 0x7fff1706, 0x0, 0x0 + dspck_dstio subqh.ph, 0x005d4000, 0x003b0001, 0xff808000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00cefbfd, 0x005ff803, 0xfec30008, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfffe3fff, 0xfffc7fff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x80000400, 0x800007fe, 0x7ffffffe, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3fffc003, 0x7fff0001, 0x00007ffa, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc0001ff9, 0x00000002, 0x7fffc00f, 0x0, 0x0 + dspck_dstio subqh.ph, 0x407fc002, 0x7fff8000, 0xff00fffc, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000000, 0x001e007f, 0x001e007f, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0e8cc02a, 0x1d1d0045, 0x00057ff0, 0x0, 0x0 + dspck_dstio subqh.ph, 0xffe11213, 0x00042492, 0x0042006b, 0x0, 0x0 + dspck_dstio subqh.ph, 0x8040f02f, 0x807fe01f, 0x7fffffc0, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfef21ff2, 0xffc60024, 0x01e1c03f, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc0033fbf, 0x8000fffe, 0xfffa807f, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0000c000, 0x7fff8000, 0x7fff0000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0801cffe, 0x000a8000, 0xf007e003, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfffcdfd0, 0x3ff0ff80, 0x3ff83fe0, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfff0233b, 0x7fe0e00f, 0x7fff9999, 0x0, 0x0 + dspck_dstio subqh.ph, 0x7fff00b2, 0x7fff016c, 0x80000007, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbfb21ac0, 0x8000f582, 0x009cc001, 0x0, 0x0 + dspck_dstio subqh.ph, 0xddb81066, 0xe0031ffe, 0x2492ff31, 0x0, 0x0 + dspck_dstio subqh.ph, 0x400e2492, 0x7fff4924, 0xffe30000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x8001583e, 0x80017ff8, 0x7fffcf7b, 0x0, 0x0 + dspck_dstio subqh.ph, 0xffee4005, 0x001f000a, 0x00428000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x1ff4c34c, 0x7fe08000, 0x3ff8f967, 0x0, 0x0 + dspck_dstio subqh.ph, 0x1555ffe8, 0x7fffffff, 0x5555002f, 0x0, 0x0 + dspck_dstio subqh.ph, 0x1fdd1ff0, 0x3fc00000, 0x0006c01f, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfbfe8040, 0xfff8807f, 0x07fc7fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc02d7fdf, 0x80007fc0, 0xffa68001, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0139216e, 0x02723fc0, 0x0000fce3, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbfc03eec, 0x80007fff, 0x007f0227, 0x0, 0x0 + dspck_dstio subqh.ph, 0x7fffd556, 0x7fff0002, 0x80005555, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0fa88000, 0x1c718000, 0xfd207fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0xe492c924, 0x8000db6d, 0xb6db4924, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc000c71c, 0x80018e38, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0003300f, 0x00077fff, 0x00001fe0, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3fc0400f, 0xff807fff, 0x8000ffe0, 0x0, 0x0 + dspck_dstio subqh.ph, 0xb005c040, 0xe0030000, 0x7ff87f80, 0x0, 0x0 + dspck_dstio subqh.ph, 0xf165ffdc, 0x000000b6, 0x1d3500fe, 0x0, 0x0 + dspck_dstio subqh.ph, 0xffffd369, 0x00000d39, 0x00016666, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc000401f, 0x0000003f, 0x7fff8000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x38032ff7, 0xf0071ffe, 0x8000c00f, 0x0, 0x0 + dspck_dstio subqh.ph, 0xf1b00074, 0x035e00e8, 0x1ffe0000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xe02004ba, 0x0000097e, 0x3fc00009, 0x0, 0x0 + dspck_dstio subqh.ph, 0x7fffdb6d, 0x7fffb6db, 0x80000001, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfa49ff47, 0x048efe8e, 0x0ffc0000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00038000, 0x7fff8000, 0x7ff87fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0xb1c7e8f3, 0xe38ed1f6, 0x7fff000f, 0x0, 0x0 + dspck_dstio subqh.ph, 0x07883fff, 0x0000fffe, 0xf0f08000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000000, 0xc03f6666, 0xc03f6666, 0x0, 0x0 + dspck_dstio subqh.ph, 0x1d7b0fe7, 0xfffcffd0, 0xc505e001, 0x0, 0x0 + dspck_dstio subqh.ph, 0x39c53ff9, 0x7fff7fff, 0x0c74000d, 0x0, 0x0 + dspck_dstio subqh.ph, 0x36dbff90, 0x6db6ff3f, 0xffff001f, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc71c4000, 0x00000000, 0x71c78000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc000fff0, 0x00008000, 0x7fff801f, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3fc3c7ff, 0x00050ffe, 0x807f7fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0xb002f2d7, 0xe0030001, 0x7fff1a53, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00001800, 0x7fff3ffc, 0x7fff0ffc, 0x0, 0x0 + dspck_dstio subqh.ph, 0x4ff837ae, 0x7fffef5c, 0xe00f8000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xffb2f001, 0xff67fffb, 0x00031ff8, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000001, 0x00000000, 0x0000fffe, 0x0, 0x0 + dspck_dstio subqh.ph, 0x40070000, 0x7ffffffe, 0xfff0fffe, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfffd1fff, 0x00000000, 0x0006c001, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000000, 0x3e278000, 0x3e278000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x401cc001, 0x7ffc0000, 0xffc47ffd, 0x0, 0x0 + dspck_dstio subqh.ph, 0xdd03009b, 0xe01f0143, 0x2619000c, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc0293b91, 0x807ff723, 0x002d8000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x7fffe34e, 0x7fffc71c, 0x8000007f, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc0403fff, 0x80000000, 0xff808001, 0x0, 0x0 + dspck_dstio subqh.ph, 0xf5640921, 0xeac89249, 0x00008006, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3ffe6492, 0xfffd4924, 0x80008000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xdffc0000, 0x3ff80000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3ff7ce39, 0x7fff8000, 0x0011e38e, 0x0, 0x0 + dspck_dstio subqh.ph, 0x4ff0e003, 0x7fffc007, 0xe01f0000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xff1a300d, 0xffff7ffa, 0x01ca1fe0, 0x0, 0x0 + dspck_dstio subqh.ph, 0x8000fc02, 0x80000000, 0x7fff07fc, 0x0, 0x0 + dspck_dstio subqh.ph, 0x004e5fff, 0x009c3ffe, 0x00008000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3ffdbfe2, 0x7ffa8000, 0x0000003b, 0x0, 0x0 + dspck_dstio subqh.ph, 0x4039401c, 0x00727fff, 0x8000ffc7, 0x0, 0x0 + dspck_dstio subqh.ph, 0x5ff80003, 0x7fff0004, 0xc00ffffd, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3fff1ff0, 0xffff3fe0, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00003f61, 0x7ffffec3, 0x7fff8000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0000ffe7, 0x00000000, 0x00000031, 0x0, 0x0 + dspck_dstio subqh.ph, 0xff9b1b6b, 0xff36b6db, 0xffff8004, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfffe4000, 0x00000000, 0x00048000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xffc0fff8, 0x00000000, 0x007f000f, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc001bffb, 0x0001fff5, 0x7fff7fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x004009a1, 0x0001e00f, 0xff80cccc, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbffccffc, 0xfff88000, 0x7fffe007, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0044ff08, 0x0246fe10, 0x01bdffff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x4913f1b5, 0x7ff80000, 0xedd11c95, 0x0, 0x0 + dspck_dstio subqh.ph, 0x07847fff, 0xfff87fff, 0xf0f08000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xf8274000, 0xf0940000, 0x00458000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfe61ddba, 0xfcc0e007, 0xfffe2492, 0x0, 0x0 + dspck_dstio subqh.ph, 0xe6661f87, 0xccccff10, 0xffffc001, 0x0, 0x0 + dspck_dstio subqh.ph, 0x32480394, 0x24920728, 0xc0010000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x04007fff, 0x00017fff, 0xf8018000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfbb8ffff, 0xf5e9fffd, 0xfe79fffe, 0x0, 0x0 + dspck_dstio subqh.ph, 0x1ffec05e, 0x3ffc00bc, 0x00007fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3ffffff3, 0x7fff8006, 0x0000801f, 0x0, 0x0 + dspck_dstio subqh.ph, 0x20070000, 0xc00f0000, 0x8000ffff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x000010fa, 0x000021f5, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000000, 0x8000fe19, 0x8000fe19, 0x0, 0x0 + dspck_dstio subqh.ph, 0x7fff3fff, 0x7fffffff, 0x80008000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x1fab0145, 0x3f57028a, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x20004001, 0x7fff0002, 0x3ffe8000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xff59c000, 0xfeb38001, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbbd31c71, 0x800038e3, 0x085a0000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00013ffd, 0x00000000, 0xfffe8006, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbffa067f, 0xfff4007f, 0x7ffff380, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc0043ffe, 0x0007fffc, 0x7fff8000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfcd9f054, 0xf9badb6d, 0x0008fac4, 0x0, 0x0 + dspck_dstio subqh.ph, 0x4000b008, 0x00008000, 0x80001ff0, 0x0, 0x0 + dspck_dstio subqh.ph, 0xffd40000, 0x00048000, 0x005b8000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x1ff6003d, 0xfff00079, 0xc003fffe, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3fff0000, 0x7fff0000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc00344c6, 0x8000098d, 0xfff98000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xe661c004, 0xcccc0000, 0x000a7ff8, 0x0, 0x0 + dspck_dstio subqh.ph, 0xa02ff4ed, 0xc03fe9db, 0x7fe00000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xf0010000, 0xe0030000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc020b6db, 0x8000db6d, 0xffc06db6, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3feaedb6, 0x7ffadb6d, 0x00260000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00750004, 0x007f0000, 0xff94fff8, 0x0, 0x0 + dspck_dstio subqh.ph, 0x4ffcefbf, 0x7ffffc01, 0xe0071c82, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00003fff, 0x7fff7fff, 0x7fff0000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00000000, 0x01457fff, 0x01457fff, 0x0, 0x0 + dspck_dstio subqh.ph, 0x36b70001, 0xed6f001f, 0x8000001d, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0403c239, 0x07fc8000, 0xfff6fb8d, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfdf9a001, 0xfff08000, 0x03fe3ffe, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbe32d555, 0x8000aaaa, 0x039c0000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3f864008, 0xff0d0010, 0x80008000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00003ffd, 0x00000000, 0x00008006, 0x0, 0x0 + dspck_dstio subqh.ph, 0xe003c000, 0xc0078000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00007fff, 0x7fff7fff, 0x7fff8000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x4fd0f820, 0x7fc0003d, 0xe01f0ffc, 0x0, 0x0 + dspck_dstio subqh.ph, 0x7333fffc, 0x66660000, 0x80000008, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfff7048b, 0xfff50000, 0x0006f6e9, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbf4a4000, 0x80060000, 0x01718000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xbc0301b9, 0x80050006, 0x07fefc93, 0x0, 0x0 + dspck_dstio subqh.ph, 0xff98ffff, 0x00048000, 0x00d38002, 0x0, 0x0 + dspck_dstio subqh.ph, 0x24707fff, 0x0ffc7fff, 0xc71c8001, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc801c001, 0x8004ffff, 0xf0017ffc, 0x0, 0x0 + dspck_dstio subqh.ph, 0xffc4ffbf, 0x0000fffe, 0x0077007f, 0x0, 0x0 + dspck_dstio subqh.ph, 0xc0477fff, 0x007f7fff, 0x7ff08000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x001fb971, 0x803f8000, 0x80000d1d, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0083c011, 0x00098000, 0xff03ffdd, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3ffdf001, 0x7fffe003, 0x00040000, 0x0, 0x0 + dspck_dstio subqh.ph, 0x3ffe1fe0, 0xfffd3fc0, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.ph, 0xfff2d000, 0x00011ffe, 0x001d7ffd, 0x0, 0x0 + dspck_dstio subqh.ph, 0x0e5836e6, 0x003f7fff, 0xe38e1232, 0x0, 0x0 + dspck_dstio subqh.ph, 0x00803330, 0x00ff6666, 0xffff0006, 0x0, 0x0 + + writemsg "[42] Test subqh_r.ph" + dspck_dstio subqh_r.ph, 0xbfe10af9, 0x8000cccc, 0x003fb6db, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc01cffe0, 0x0036ffc0, 0x7fff0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xe01d3010, 0xc03f7fff, 0x00051fe0, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x40002002, 0x0000c003, 0x80008000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xeee1fffe, 0xfdba8000, 0x1ff88005, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x4002c000, 0x00038000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x40004000, 0x7fff7fff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc9250003, 0x0000fff8, 0x6db6fff3, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x43ff1b6e, 0x7fffb6db, 0xf8018000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00010bbb, 0x0000ff00, 0xffffe78a, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00000000, 0xf0030000, 0xf0030000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x4001c004, 0x00028000, 0x8000fff9, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc041feea, 0x807ffdd4, 0xfffd0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf87cfffc, 0x0007fff8, 0x0f0f0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc001003b, 0x80000000, 0xffffff8a, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x4000ffff, 0x7ffffffe, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc0010000, 0x00018000, 0x7fff8000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3ffdc000, 0x00008000, 0x80060001, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfff32b09, 0xffe5d611, 0x00008000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00133fff, 0xfff5fffe, 0xffcf8000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0000ffe1, 0x00008000, 0x0000803f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xd99a3c01, 0x3333f801, 0x7fff8000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0002dfb4, 0x0003c01f, 0x000000b7, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0855c001, 0x07560000, 0xf6ad7fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x4001bff1, 0x7fff8000, 0xfffe001f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0259ffff, 0x2492fffe, 0x1fe00000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x4fffc008, 0x1ffe000e, 0x80007fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc0404080, 0x80007fff, 0xff80ff00, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc008fe03, 0x800ffc01, 0x0000fffb, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x19ae1ff1, 0x33333fe0, 0xffd7fffe, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0001f802, 0x0000fffc, 0xfffe0ff8, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x163ecf4f, 0xfffe8004, 0xd382e167, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x1ff80041, 0x3ff00001, 0x0000ff80, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x11aff017, 0x036ce01f, 0xe00ffff1, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf4fafc17, 0xe9f3fc01, 0x000003d4, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x4000db6d, 0x0000b6db, 0x80000002, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0fac3801, 0x1f557fff, 0xfffe0ffe, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xffff0000, 0xfffc0000, 0xfffe0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x2038bf0f, 0x3ffcfe1c, 0xff8d7fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00012010, 0x0002c01f, 0x00008000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xffc10000, 0xff808000, 0xffff8001, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xbe03fff0, 0xfc01fffb, 0x7ffb001c, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0003011d, 0x0002fc82, 0xfffdfa48, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfb364ffc, 0xf8011ff8, 0x01968000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xbaf74003, 0xf5e57fff, 0x7ff8fffa, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x40001ff1, 0x00000000, 0x8000c01f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0000ebf5, 0x0000fffd, 0x00002813, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xe003f1c7, 0xc007fffe, 0x00021c71, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfc01ffff, 0x0000fffd, 0x07fe0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc2000062, 0x03fefffd, 0x7fffff3a, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xbffd4035, 0xfff8006a, 0x7fff8000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x031f0020, 0x0636ffff, 0xfff9ffc0, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc045bf41, 0x807f8001, 0xfff60180, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0000045a, 0x7fff01f5, 0x7ffff941, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfccef02c, 0x00030050, 0x06671ff8, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x36dccff1, 0x00011fe0, 0x92497fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf009c020, 0x00018000, 0x1ff0ffc0, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xd55900ae, 0x00060004, 0x5555fea8, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xe00a18f7, 0x00043333, 0x3ff00145, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x4040c00f, 0x007f801f, 0x80000002, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x5ffcc018, 0x7fff001f, 0xc0077ff0, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3ffcf018, 0x7fffe01f, 0x0007fff0, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0000f30d, 0x7fffe61a, 0x7fff0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfff90000, 0xfff10000, 0x00000001, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00000000, 0x7fffff71, 0x7fffff71, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x38023fe1, 0x7fff7fc0, 0x0ffcfffe, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xa004f816, 0x80000029, 0x3ff80ffe, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x80010006, 0x8000ffcc, 0x7fffffc0, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xbf4b000b, 0xfe85fffd, 0x7ff0ffe7, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x80010000, 0x80007fff, 0x7fff7fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x7fe00ffd, 0x7fc00ffc, 0x8001f003, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00000000, 0x71c77fff, 0x71c77fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfe33c023, 0xfc6b8000, 0x0005ffbb, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xd812124a, 0xf0030000, 0x3fe0db6d, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfe88b804, 0x00018000, 0x02f10ff8, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc00ec788, 0x80000f0f, 0xffe47fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xcffdbfff, 0x80008001, 0xe0070004, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x31c7407f, 0x7fff7fff, 0x1c71ff02, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfffef1c8, 0xfffb0000, 0xffff1c71, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x08341001, 0x00691ffe, 0xf001fffc, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x436f4000, 0x06de7fff, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x4000fd9b, 0x7fff0000, 0xffff04cb, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00150000, 0x001f7fff, 0xfff57fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x010fc090, 0x02210119, 0x00037ff9, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3fe2f969, 0x7ffff243, 0x003cff71, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xff8dd001, 0x00058003, 0x00ece001, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0071ffc1, 0x00e50001, 0x0004007f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf0100002, 0xe01f0003, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3bfdd03f, 0xf8011ffe, 0x80077f80, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc78b0000, 0x0f0f7ffe, 0x7ff97fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0110c001, 0x00000000, 0xfde17fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xff5f05ff, 0xfbf30ffc, 0xfd3503fe, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x400ff802, 0x0021ffff, 0x80040ffc, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x8003014b, 0x80020064, 0x7ffcfdcf, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3334ffef, 0x0001fffa, 0x9999001d, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0ccda760, 0x9999800f, 0x8000314f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x80000060, 0x7fff003f, 0x8000ff80, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00134000, 0x00057fff, 0xffe00000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x4000c001, 0x00000000, 0x80007fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00000000, 0xfc260a01, 0xfc260a01, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x1ff8a00a, 0xffff800f, 0xc00f3ffc, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x1fe81ff2, 0xffef3fe0, 0xc01ffffc, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x199ad555, 0x0000aaaa, 0xcccc0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf9d878e4, 0x03ac71c7, 0x0ffc8000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc46a0002, 0x08cd8004, 0x7ff98000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xbffe3ffe, 0x80000000, 0x00058005, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc0313ff9, 0x80007fff, 0xff9e000d, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xffefeaab, 0xffdd5555, 0xffff7fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0ec2bfff, 0xfd92fffd, 0xe00f7fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0002fff1, 0xffffffff, 0xfffc001e, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc0038000, 0x80057fff, 0x00008000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc0013ffc, 0x0000fff8, 0x7fff8000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc0234010, 0x0025001f, 0x7fe08000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xbf40bfff, 0x80008000, 0x01800002, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3f800001, 0x7fff0000, 0x00ffffff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0000c001, 0xffff8000, 0x0000ffff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfffcc000, 0x0007ffff, 0x000f7fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfea80000, 0xfd500000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xff802010, 0xff007fff, 0x00003fe0, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xeff5eb71, 0xffe6d6ce, 0x1ffcffec, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x40f2fff9, 0x02230000, 0x803f000f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc0dcf2b3, 0x01b70001, 0x7fff1a9b, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00070000, 0x10090000, 0x0ffc0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf2df8003, 0xe0038000, 0xfa467ffa, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0000f010, 0x7fffe01f, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf8983eb9, 0xf130fd72, 0x00008000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x02b0dffa, 0x0520c003, 0xffc10010, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xdb6e0000, 0x00000000, 0x49240000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3ffc1ef1, 0x7ff03fe0, 0xfff801ff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xff9cc000, 0x00028000, 0x00ca0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc002eda9, 0x8000db6d, 0xfffc001b, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x4788bffd, 0x7fff8000, 0xf0f00007, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf1fbffe1, 0x00660000, 0x1c71003f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3bffdcec, 0x7ffcf2bb, 0x07fe38e3, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x003dfbfd, 0x0003fae4, 0xff8902ea, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x03ff871d, 0x07fe8e38, 0x00007fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x1b6ad805, 0x7ff8c001, 0x49240ff8, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00dd4004, 0x00000007, 0xfe468000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0c5c0200, 0x18b70000, 0x0000fc01, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00004748, 0xffff0f0f, 0x0000807f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0c850000, 0xfc970000, 0xe38e0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0001fff9, 0x00007ff0, 0xfffe7fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0006f001, 0x000ae003, 0xfffe0002, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xe010fe01, 0x00000000, 0x3fe003fe, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x80043fe1, 0x80070000, 0x7fff803f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x1e6ef01d, 0x38e30038, 0xfc081ffe, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xbf81c000, 0xff008000, 0x7fff0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf9013fff, 0xf2017fff, 0x00000002, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00040000, 0x00020000, 0xfffb0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf739c001, 0xfe4a8000, 0x0fd8fffe, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc000ffeb, 0x8000ffd6, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x016fe38f, 0x00000000, 0xfd2338e3, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf5623fed, 0xf36dffe0, 0x08a98007, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0000e390, 0x0000c71c, 0x0000fffc, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0002c000, 0x7fff8000, 0x7ffc0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xb87a1ffb, 0x80033ffe, 0x0f0f0009, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x5ffcff86, 0x3ff80001, 0x800000f6, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfffe47fc, 0x80007fff, 0x8005f007, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00030008, 0x0006000f, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x7ffef7c5, 0x7ffbff80, 0x80000ff7, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf7bc0006, 0x00000000, 0x1089fff5, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x8000ffea, 0x7fffffea, 0x80000016, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xebebc0db, 0xfff901b5, 0x28247fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0000c005, 0x7fff0003, 0x7fff7ff9, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x5fe04000, 0x3fc00000, 0x80008000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf009c002, 0x00010000, 0x1ff07ffc, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0000b39e, 0xffffe73b, 0x00007fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x40004000, 0x7fff7fff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00000000, 0xe01f807f, 0xe01f807f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xbf5c03ff, 0x800007fe, 0x01480000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x871ded35, 0x8e38e01f, 0x7fff05b6, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x01a70033, 0x00d70000, 0xfd89ff9b, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0003c000, 0x0000fffe, 0xfffa7fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xffce3334, 0x00010000, 0x00669999, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfff10020, 0x00007fff, 0x001f7fc0, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x36dfc010, 0x00060000, 0x92497fe0, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00122020, 0x0024c03f, 0x00008000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xff664001, 0xfdcc0001, 0xff008000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0ccdb503, 0x9999ea04, 0x80007fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3ffec012, 0xfffc8007, 0x8000ffe3, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc001bf75, 0x0000807f, 0x7fff0195, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3ffd404d, 0x7ffa0099, 0x00008000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00001009, 0xffff1ff8, 0x0000ffe6, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xbffc3002, 0xfff77fff, 0x7fff1ffc, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xbfc5f003, 0xff88e007, 0x7fff0002, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xb8010000, 0xf001fff8, 0x7ffffff9, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfc0a07bd, 0x0012ff80, 0x07fef007, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xe0001231, 0xc00f0465, 0x000fe003, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xffe3c003, 0xffc48000, 0xfffefffa, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3d660197, 0x7fff0087, 0x0534fd5a, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xbff40820, 0x80000ff8, 0x0019ffb9, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf2b25ffd, 0xe64a7ffd, 0x00e7c003, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x406af00c, 0x00d40008, 0x80001ff0, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00000000, 0x7fff0002, 0x7fff0002, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3f0affec, 0x7fff0001, 0x01ec0029, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x5ffcfffd, 0x3ff80000, 0x80000006, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc0434000, 0x80000000, 0xff7a8000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00003ffe, 0x8000fffb, 0x80008000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0ffbe38e, 0xfff9c71c, 0xe0030000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc1740000, 0x80060000, 0xfd1e0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x46cc1ff7, 0x1fe0fffd, 0x9249c00f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xffe4f164, 0x0000e622, 0x0038035b, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xc00001ff, 0x800003fe, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xdffeff34, 0xc001fff6, 0x0006018e, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x1c72ffb9, 0x0000fff0, 0xc71c007f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x40690fee, 0x7fffffea, 0xff2ee00f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xbfece010, 0xffd7c01f, 0x7fff0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3c021b6e, 0xf803b6db, 0x80008000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00001e31, 0x7ffe1c71, 0x7fffe00f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x40000001, 0x00000000, 0x8000ffff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x01230000, 0x00000000, 0xfdba0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x40004001, 0x7fff0002, 0x00008000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3fe8c402, 0x7fff8004, 0x002ff801, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x80102004, 0x801f7fff, 0x7fff3ff8, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfc27fffe, 0xf853fffc, 0x00060000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x5ffc3ffd, 0x7ffa7fff, 0xc0030006, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf666f327, 0x1ffee64d, 0x33330000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0fc800df, 0xff9701bd, 0xe0070000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00000000, 0x0000ffff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x09234000, 0x92497fff, 0x8003ffff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x40623d6b, 0x7ffffb54, 0xff3c807f, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x0010fbe9, 0x001ff803, 0xffff0032, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x9b6e4000, 0x80000000, 0x49248000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3ffc0000, 0x7ff80000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00770000, 0xfff57fff, 0xff077fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x8002c046, 0x8002000c, 0x7fff7f80, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf61d3f3b, 0x00047fff, 0x13cb018a, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x4fff4017, 0x7fff7fff, 0xe001ffd1, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xffee0000, 0xffd60000, 0xfffa0000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x6a9b0725, 0x7fe00e4c, 0xaaaa0002, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3ffd11ed, 0x7fffff47, 0x0006db6d, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xfffddfff, 0xffffc001, 0x00060004, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xdb6bbfdd, 0xfffa803f, 0x49240086, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf6f3bf06, 0xede6fe0b, 0x00007fff, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x00002d33, 0x00001a66, 0x0000c001, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x2f30c0b2, 0xde608000, 0x8000fe9c, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x1c1f0022, 0x383e0044, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0xf004dc22, 0xe007f83b, 0x00003ff8, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x000000c8, 0x0000007f, 0x0000feef, 0x0, 0x0 + dspck_dstio subqh_r.ph, 0x3940ff95, 0x71c7fffd, 0xff4800d3, 0x0, 0x0 + + writemsg "[43] Test addqh.w" + dspck_dstio addqh.w, 0xff6f3d59, 0x00000000, 0xfede7ab3, 0x0, 0x0 + dspck_dstio addqh.w, 0x0203217d, 0x000642fd, 0x03fffffe, 0x0, 0x0 + dspck_dstio addqh.w, 0x40000001, 0x7fffffff, 0x00000003, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffff48f, 0xffffe920, 0xffffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffffff, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xfff71220, 0xffee1fbf, 0x00000481, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffffffa, 0xfffffffa, 0xfffffffb, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffffffe, 0x00000000, 0xfffffffc, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffffc9d, 0x00000000, 0xfffff93b, 0x0, 0x0 + dspck_dstio addqh.w, 0xbfffffae, 0x80000000, 0xffffff5c, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xbffffdc5, 0x80000000, 0xfffffb8a, 0x0, 0x0 + dspck_dstio addqh.w, 0xfe2cab6a, 0xfc600dbd, 0xfff94917, 0x0, 0x0 + dspck_dstio addqh.w, 0x1ffffff5, 0x3fffffe0, 0x0000000a, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000045, 0x00000082, 0x00000008, 0x0, 0x0 + dspck_dstio addqh.w, 0xf8000001, 0x00000000, 0xf0000003, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x1fffffc7, 0x7fffff80, 0xc000000f, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffffb40, 0x00000000, 0xfffff681, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffffbf, 0x7fffff80, 0xfffffffe, 0x0, 0x0 + dspck_dstio addqh.w, 0xc7ffffff, 0x80000000, 0x0ffffffe, 0x0, 0x0 + dspck_dstio addqh.w, 0x00008065, 0x0000000d, 0x000100be, 0x0, 0x0 + dspck_dstio addqh.w, 0x80000002, 0x80000000, 0x80000004, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000001, 0x0, 0x0 + dspck_dstio addqh.w, 0xf6db6df6, 0x6db6db6d, 0x8000007f, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x0000024e, 0x00000000, 0x0000049d, 0x0, 0x0 + dspck_dstio addqh.w, 0x3ffff2a5, 0x7fffffff, 0xffffe54c, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffffff8, 0x80000000, 0x7ffffff0, 0x0, 0x0 + dspck_dstio addqh.w, 0xc8000002, 0x80000007, 0x0ffffffe, 0x0, 0x0 + dspck_dstio addqh.w, 0x2aaaaaaa, 0x00000000, 0x55555555, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000000, 0x00000001, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xfef8701b, 0x00000000, 0xfdf0e037, 0x0, 0x0 + dspck_dstio addqh.w, 0xbfffde84, 0x8000007f, 0xffffbc89, 0x0, 0x0 + dspck_dstio addqh.w, 0x000001d6, 0x0000068d, 0xfffffd1f, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000003, 0x00000000, 0x00000007, 0x0, 0x0 + dspck_dstio addqh.w, 0x32cb2cb2, 0x1c71c71c, 0x49249249, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000003, 0x00000000, 0x00000007, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffffe0, 0xffffffe0, 0x7fffffe0, 0x0, 0x0 + dspck_dstio addqh.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x3ffffffd, 0xfffffffc, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000002, 0x00000000, 0x00000004, 0x0, 0x0 + dspck_dstio addqh.w, 0x078787a7, 0x0f0f0f0f, 0x0000003f, 0x0, 0x0 + dspck_dstio addqh.w, 0x0009a9ea, 0xffffffff, 0x001353d5, 0x0, 0x0 + dspck_dstio addqh.w, 0x3ffffffc, 0x7fffffff, 0xfffffffa, 0x0, 0x0 + dspck_dstio addqh.w, 0x40000000, 0x7ffffffc, 0x00000004, 0x0, 0x0 + dspck_dstio addqh.w, 0x0a1439fc, 0x009de2c8, 0x138a9131, 0x0, 0x0 + dspck_dstio addqh.w, 0x40000001, 0x00000003, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000004, 0x00000004, 0x00000004, 0x0, 0x0 + dspck_dstio addqh.w, 0x3ffffffc, 0x7ffffffe, 0xfffffffb, 0x0, 0x0 + dspck_dstio addqh.w, 0xedb6db6d, 0xdb6db6db, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xdaee365b, 0xff00ff00, 0xb6db6db6, 0x0, 0x0 + dspck_dstio addqh.w, 0xc00ab1c0, 0x80000007, 0x00156379, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffffff, 0x00000000, 0xffffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xf7fffffe, 0xf0000001, 0xfffffffb, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffffe63, 0x00000000, 0xfffffcc7, 0x0, 0x0 + dspck_dstio addqh.w, 0xf7fffca4, 0xf0000007, 0xfffff942, 0x0, 0x0 + dspck_dstio addqh.w, 0x38e38e38, 0x38e38e38, 0x38e38e38, 0x0, 0x0 + dspck_dstio addqh.w, 0xffeddc38, 0xffdbb57e, 0x000002f2, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffc6eb, 0xffff8dd8, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0x40000003, 0x7fffffff, 0x00000007, 0x0, 0x0 + dspck_dstio addqh.w, 0xdfffffe3, 0xffffffa7, 0xc000001f, 0x0, 0x0 + dspck_dstio addqh.w, 0xbff6e6d6, 0xffedcdac, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x2aaad101, 0x00004cae, 0x55555555, 0x0, 0x0 + dspck_dstio addqh.w, 0xff807fbf, 0xff00ff00, 0x0000007f, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffffe2, 0x80000004, 0x7fffffc0, 0x0, 0x0 + dspck_dstio addqh.w, 0x3ffffffe, 0x7fffffff, 0xfffffffe, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffffff, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xfe000000, 0xfc000001, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x43fffffd, 0x07fffffc, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0x002b158f, 0x00562b46, 0xffffffd8, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000002, 0x00000003, 0x80000001, 0x0, 0x0 + dspck_dstio addqh.w, 0x09fffffd, 0x0ffffffc, 0x03fffffe, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000005, 0x00000005, 0x00000006, 0x0, 0x0 + dspck_dstio addqh.w, 0x087f807e, 0x00ff00ff, 0x0ffffffe, 0x0, 0x0 + dspck_dstio addqh.w, 0x3e8d552c, 0x7fffffff, 0xfd1aaa59, 0x0, 0x0 + dspck_dstio addqh.w, 0x0000006e, 0x0000003f, 0x0000009e, 0x0, 0x0 + dspck_dstio addqh.w, 0x400097ab, 0x00012f58, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffffffe, 0x7ffffffc, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xff774142, 0xfeee8285, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x1000c7c8, 0x00018f95, 0x1ffffffc, 0x0, 0x0 + dspck_dstio addqh.w, 0x40000002, 0x00000005, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0x03ef6066, 0xffdec0cf, 0x07fffffe, 0x0, 0x0 + dspck_dstio addqh.w, 0xffb63183, 0xff6c6306, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xff807f83, 0xff00ff00, 0x00000007, 0x0, 0x0 + dspck_dstio addqh.w, 0x5ffffffd, 0x7fffffff, 0x3ffffffc, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffff00, 0xffffff00, 0xffffff00, 0x0, 0x0 + dspck_dstio addqh.w, 0x000144dc, 0x000289b9, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xbf8d4ed6, 0x80000003, 0xff1a9daa, 0x0, 0x0 + dspck_dstio addqh.w, 0xfe7f4090, 0xfcfe8121, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x03c898ae, 0x0791315c, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xc56173b3, 0x0ac2e760, 0x80000007, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffffff, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffffffb, 0xfffffffe, 0xfffffff8, 0x0, 0x0 + dspck_dstio addqh.w, 0xf800aeb7, 0x00015d68, 0xf0000007, 0x0, 0x0 + dspck_dstio addqh.w, 0x2aaaaaaa, 0x55555555, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x0000f569, 0x0001eb4f, 0xffffff83, 0x0, 0x0 + dspck_dstio addqh.w, 0x0800001d, 0x0ffffffc, 0x0000003f, 0x0, 0x0 + dspck_dstio addqh.w, 0x0005ce3e, 0xffffffdd, 0x000b9ca0, 0x0, 0x0 + dspck_dstio addqh.w, 0xdc71c71c, 0x80000000, 0x38e38e38, 0x0, 0x0 + dspck_dstio addqh.w, 0x1ffffffc, 0x00000018, 0x3fffffe0, 0x0, 0x0 + dspck_dstio addqh.w, 0x43efada4, 0x7fffffff, 0x07df5b49, 0x0, 0x0 + dspck_dstio addqh.w, 0x01b25e99, 0xfffffffd, 0x0364bd35, 0x0, 0x0 + dspck_dstio addqh.w, 0x0000c659, 0x00018cb3, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x38e38e4e, 0x71c71c71, 0x0000002c, 0x0, 0x0 + dspck_dstio addqh.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x000000ff, 0x000000ff, 0x000000ff, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xbffff5bb, 0xffffeb77, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xbfff800f, 0xffff0000, 0x8000001f, 0x0, 0x0 + dspck_dstio addqh.w, 0xd5555555, 0xaaaaaaaa, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xd5555555, 0x00000000, 0xaaaaaaaa, 0x0, 0x0 + dspck_dstio addqh.w, 0xdbb34f6b, 0x008b3121, 0xb6db6db6, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000c75, 0x00000000, 0x000018eb, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffffe0, 0xffffffc0, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0x9555555c, 0xaaaaaaaa, 0x8000000f, 0x0, 0x0 + dspck_dstio addqh.w, 0x4076b0e8, 0x7ffffffc, 0x00ed61d4, 0x0, 0x0 + dspck_dstio addqh.w, 0x2aaaaaaa, 0x55555555, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xfff3652d, 0xffe6c981, 0x000000da, 0x0, 0x0 + dspck_dstio addqh.w, 0x44b02eb9, 0x7ffffff8, 0x09605d7a, 0x0, 0x0 + dspck_dstio addqh.w, 0x0013efed, 0x00209236, 0x00074da5, 0x0, 0x0 + dspck_dstio addqh.w, 0xbffffffd, 0x80000000, 0xfffffffb, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000338, 0x00000671, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x3f6a238c, 0x7ffffff8, 0xfed44720, 0x0, 0x0 + dspck_dstio addqh.w, 0x64924924, 0x7fffffff, 0x49249249, 0x0, 0x0 + dspck_dstio addqh.w, 0x38000000, 0x7fffffff, 0xf0000001, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffffff, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000000, 0x00000000, 0x80000001, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffffffd, 0x00000000, 0xfffffffb, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xe19050bf, 0x00000001, 0xc320a17e, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000006, 0x0000000c, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000002, 0x00000004, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x001ed11f, 0x00000000, 0x003da23f, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xbfffffff, 0x80000000, 0xffffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0x3ffeb2f4, 0xfffd65f8, 0x7ffffff0, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffffff, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xcccc7814, 0x99999999, 0xffff5690, 0x0, 0x0 + dspck_dstio addqh.w, 0xc000000b, 0xc0000007, 0xc000000f, 0x0, 0x0 + dspck_dstio addqh.w, 0xf8000002, 0xf0000007, 0xfffffffe, 0x0, 0x0 + dspck_dstio addqh.w, 0xffff2888, 0xffff2888, 0xffff2888, 0x0, 0x0 + dspck_dstio addqh.w, 0xbfffff80, 0xffffff00, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xdb6db675, 0xffffff35, 0xb6db6db6, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000003, 0x80000000, 0x00000007, 0x0, 0x0 + dspck_dstio addqh.w, 0x3ffffffe, 0xfffffffe, 0x7ffffffe, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffff7f, 0x7fffffff, 0xffffff00, 0x0, 0x0 + dspck_dstio addqh.w, 0x59999989, 0x33333333, 0x7fffffe0, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xf0000007, 0xf0000007, 0xf0000007, 0x0, 0x0 + dspck_dstio addqh.w, 0xc00000d4, 0x80000002, 0x000001a7, 0x0, 0x0 + dspck_dstio addqh.w, 0xdffffffe, 0x80000000, 0x3ffffffc, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0x1ff102a8, 0x3ffffff0, 0xffe20561, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xbff42c92, 0xffe85925, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xf1c71c71, 0xaaaaaaaa, 0x38e38e38, 0x0, 0x0 + dspck_dstio addqh.w, 0x00023367, 0xfffffffc, 0x000466d2, 0x0, 0x0 + dspck_dstio addqh.w, 0xf8000003, 0xf0000007, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xff807f80, 0x00000000, 0xff00ff00, 0x0, 0x0 + dspck_dstio addqh.w, 0x40027c25, 0x7fffffff, 0x0004f84b, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x3f9fcf15, 0xff3f9e2c, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xfff9c870, 0x00000005, 0xfff390dc, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fc25387, 0xff84a710, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xbffffd58, 0xfffffab0, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xb904c03b, 0x80000000, 0xf2098076, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffffff2, 0xffffffe4, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x3f00ae1d, 0xfe015c3c, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xbffffff9, 0xfffffff2, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xbfffff4a, 0x80000000, 0xfffffe94, 0x0, 0x0 + dspck_dstio addqh.w, 0xbfe01fc0, 0xffc03f80, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0008001, 0x80000003, 0x0000ffff, 0x0, 0x0 + dspck_dstio addqh.w, 0x3ffff7d1, 0xffffefa4, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0x40002914, 0x00005249, 0x7fffffe0, 0x0, 0x0 + dspck_dstio addqh.w, 0x221d4ee8, 0x043a9df1, 0x3fffffe0, 0x0, 0x0 + dspck_dstio addqh.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xff020def, 0xfe041bde, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffffffd, 0x7ffffffb, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000000, 0xfffffffb, 0x00000006, 0x0, 0x0 + dspck_dstio addqh.w, 0xc00000cb, 0x80000000, 0x00000196, 0x0, 0x0 + dspck_dstio addqh.w, 0x0cd25a83, 0x0b4505df, 0x0e5faf28, 0x0, 0x0 + dspck_dstio addqh.w, 0x0ffffff6, 0x1ffffff0, 0xfffffffd, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffd176, 0xffffffff, 0xffffa2ed, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000000, 0x00000001, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x4ffffffa, 0x1ffffff8, 0x7ffffffd, 0x0, 0x0 + dspck_dstio addqh.w, 0xd491985f, 0xaaaaaaaa, 0xfe788615, 0x0, 0x0 + dspck_dstio addqh.w, 0x40000036, 0x7ffffffe, 0x0000006f, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffff80, 0xffffff00, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000016, 0x00000023, 0x00000009, 0x0, 0x0 + dspck_dstio addqh.w, 0x3e000000, 0x7fffffff, 0xfc000001, 0x0, 0x0 + dspck_dstio addqh.w, 0x1ffffff8, 0x3ffffff0, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xbfff66e1, 0xfffecdc2, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xf0000000, 0x00000000, 0xe0000001, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0xfc000005, 0x00000007, 0xf8000003, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffffda, 0xffffffda, 0xffffffda, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xb0000003, 0x80000000, 0xe0000007, 0x0, 0x0 + dspck_dstio addqh.w, 0xc0000018, 0xfffffff1, 0x8000003f, 0x0, 0x0 + dspck_dstio addqh.w, 0xe000001b, 0x3ffffff8, 0x8000003f, 0x0, 0x0 + dspck_dstio addqh.w, 0x1d986f80, 0x3b6f4028, 0xffc19ed9, 0x0, 0x0 + dspck_dstio addqh.w, 0x0aaaaaae, 0xc0000007, 0x55555555, 0x0, 0x0 + dspck_dstio addqh.w, 0x1248fe2b, 0x24924924, 0xffffb333, 0x0, 0x0 + dspck_dstio addqh.w, 0x0001ca6e, 0x000394cd, 0x0000000f, 0x0, 0x0 + dspck_dstio addqh.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xf7e0ad68, 0xffc15ad0, 0xf0000001, 0x0, 0x0 + dspck_dstio addqh.w, 0x80000002, 0x80000004, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000003, 0x00000000, 0x00000006, 0x0, 0x0 + dspck_dstio addqh.w, 0xfffffff1, 0x00000000, 0xffffffe3, 0x0, 0x0 + dspck_dstio addqh.w, 0x0e38e38e, 0x1c71c71c, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000004, 0x00000008, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0xffffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x52492491, 0x7fffffff, 0x24924924, 0x0, 0x0 + dspck_dstio addqh.w, 0x3e8c09b9, 0x7fffffff, 0xfd181374, 0x0, 0x0 + dspck_dstio addqh.w, 0xbfffffff, 0x8000003f, 0xffffffc0, 0x0, 0x0 + dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x000000eb, 0x000001d7, 0x00000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x3fffed54, 0x7fffffe0, 0xffffdac9, 0x0, 0x0 + dspck_dstio addqh.w, 0xfc000000, 0x00000000, 0xf8000001, 0x0, 0x0 + dspck_dstio addqh.w, 0xbf0e62c0, 0x80000000, 0xfe1cc581, 0x0, 0x0 + dspck_dstio addqh.w, 0x3249248a, 0x3ffffff0, 0x24924924, 0x0, 0x0 + dspck_dstio addqh.w, 0xf0000004, 0x00000001, 0xe0000007, 0x0, 0x0 + dspck_dstio addqh.w, 0x7ffffffa, 0x7ffffffa, 0x7ffffffa, 0x0, 0x0 + dspck_dstio addqh.w, 0xe0014d4c, 0x00029a79, 0xc000001f, 0x0, 0x0 + dspck_dstio addqh.w, 0x07878797, 0x0f0f0f0f, 0x0000001f, 0x0, 0x0 + dspck_dstio addqh.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh.w, 0x3ffffffd, 0xfffffffc, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh.w, 0x003d608a, 0x0002bc6f, 0x007804a6, 0x0, 0x0 + + writemsg "[44] Test addqh_r.w" + dspck_dstio addqh_r.w, 0x001c2e53, 0xffffffed, 0x00385cb8, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xd55557da, 0x0000050a, 0xaaaaaaaa, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x07ffffff, 0x00000000, 0x0ffffffe, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc07f8083, 0x00ff00ff, 0x80000007, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3fffff92, 0xffffffa4, 0x7fffff80, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000a36, 0x0000146b, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000003, 0x00000000, 0x80000006, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffce4ead, 0x000021b8, 0xff9c7ba2, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfbff2863, 0xfffe50c3, 0xf8000003, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x006b3544, 0x00d66a89, 0xfffffffe, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfb87c222, 0xc3dc5111, 0x33333333, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000001, 0x00000001, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0737f9f, 0x80000000, 0x00e6ff3d, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0000021b, 0x00000435, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0e4639b4, 0x001aac4b, 0x1c71c71c, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xe0000017, 0xc000000f, 0x0000001f, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xe0000004, 0xe0000001, 0xe0000007, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbfffffff, 0x80000000, 0xfffffffd, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000004, 0x00000007, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x02022147, 0x03fffffe, 0x0004428f, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbfffcea2, 0x80000004, 0xffff9d40, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0000023f, 0x000004a2, 0xffffffdb, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xff4bf5da, 0xfe97eba2, 0x00000012, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfffffff7, 0x00000000, 0xffffffed, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfffffff6, 0xffffffec, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xd8000002, 0xf0000003, 0xc0000001, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfe2b8f23, 0xfe2b8f23, 0xfe2b8f23, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x7ffffff0, 0x7fffffe0, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc2f27694, 0x80000000, 0x05e4ed28, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000001, 0x00000001, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfffff9a5, 0x00000000, 0xfffff349, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x33333333, 0x66666666, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x20000000, 0xc0000001, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfe000001, 0xfc000001, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x36db68c5, 0x6db6db6d, 0xfffff61d, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x000000ee, 0x00000003, 0x000001d9, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc71c71c7, 0x00000000, 0x8e38e38e, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x4000007f, 0x000000ff, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3fffd85e, 0xffffb0bc, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfffffe9b, 0xfffffd36, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbffff359, 0x80000000, 0xffffe6b2, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00079fed, 0x000f3fda, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf8000001, 0x00000000, 0xf0000001, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000002, 0x80000004, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x07bc1ffd, 0xfff8f339, 0x0f7f4cc0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x20000001, 0x7fffffff, 0xc0000003, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfc57b223, 0xffffffc0, 0xf8af6486, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x24924925, 0x49249249, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x47fffffe, 0x7fffffff, 0x0ffffffc, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffffd536, 0xffffaa6c, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000011, 0x0000001f, 0x00000003, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x03979f3a, 0x00000000, 0x072f3e73, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3ff806f1, 0xfff00de3, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x7ffffff0, 0x7fffffe0, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x007e6f6e, 0x00ff00ff, 0xfffddddc, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffcd1c51, 0x0000003f, 0xff9a3862, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbb6a9bf9, 0xf6d537f2, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00008c1a, 0x00011833, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xcccccccd, 0x00000000, 0x99999999, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x78e38e38, 0x71c71c71, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3ffffffe, 0xfffffffd, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x1ffffffe, 0x00000000, 0x3ffffffc, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfffffdfe, 0xfffffdfe, 0xfffffdfe, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffebcf00, 0xffd79eff, 0xffffff00, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x4ffffff7, 0x7ffffffe, 0x1ffffff0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf878787b, 0xf0f0f0f0, 0x00000006, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x2ffffffd, 0x1ffffffc, 0x3ffffffe, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xec9a775a, 0xffff4359, 0xd935ab5b, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xe0000002, 0x00000000, 0xc0000003, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000008, 0x8000000f, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffffffbf, 0xffffff80, 0xfffffffd, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0000000f, 0x00000000, 0x0000001d, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000000, 0xffffffff, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00002f90, 0xfffffffb, 0x00005f25, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xdb6ee8cf, 0xb6db6db6, 0x000263e8, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000003, 0x7fffffff, 0x00000006, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbf030c41, 0x80000000, 0xfe061881, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbf8dec7a, 0x80000001, 0xff1bd8f3, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffcac1e3, 0xfffffff8, 0xff9583ce, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xd5555555, 0xaaaaaaaa, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfffffff8, 0x00000000, 0xfffffff0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0003b152, 0x000af736, 0xfffc6b6e, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xd5555556, 0xaaaaaaaa, 0x00000002, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x1c71c720, 0x38e38e38, 0x00000007, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf9906a36, 0xf378b685, 0xffa81de6, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf8015b6a, 0x0002b6d2, 0xf0000001, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x01d83e62, 0x00000000, 0x03b07cc3, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0005d570, 0x000baadf, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x00000003, 0xfffffffd, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x08000006, 0x0ffffffe, 0x0000000e, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3ffbc0cd, 0x7fffffff, 0xfff7819a, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x07fffffb, 0x0ffffff8, 0xfffffffe, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0000033f, 0x00000681, 0xfffffffc, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00008000, 0x0000ffff, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3ffffff0, 0x00000000, 0x7fffffe0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf7ffffd7, 0xffffffac, 0xf0000001, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xe38e38e6, 0xc71c71c7, 0x00000005, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffd22f1c, 0xfffffff0, 0xffa45e47, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3fffffc0, 0x00000000, 0x7fffff80, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x78e38e19, 0x71c71c71, 0x7fffffc0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x20000000, 0xc0000001, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf1c71c62, 0xe38e38e3, 0xffffffe0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfde8abd7, 0xfbd157ad, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfffffd4e, 0xfffffa9b, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00089cd9, 0xfffffffe, 0x001139b4, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3fffffff, 0xffffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000000, 0x7ffffffb, 0x00000004, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffffffff, 0x00000000, 0xfffffffd, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xd5555558, 0xaaaaaaaa, 0x00000006, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xedb6db6e, 0x00000000, 0xdb6db6db, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf1b6db6d, 0xdb6db6db, 0x07fffffe, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x332937e8, 0x66666666, 0xffec096a, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xe0000004, 0x00000000, 0xc0000007, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000f2d, 0x80000000, 0x00001e59, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfb4d222c, 0xfb4d222c, 0xfb4d222c, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000007, 0x7fffffff, 0x0000000f, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfff2720c, 0xffe4e418, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000001, 0x80000000, 0x00000002, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x02000001, 0x03fffffe, 0x00000004, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000160, 0x000002c0, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x404316be, 0x00862d7d, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x000000d2, 0x00000000, 0x000001a4, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000002, 0x00000005, 0xffffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc00000b7, 0x80000000, 0x0000016d, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3fff1ad6, 0xfffe35cb, 0x7fffffe0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfeca0cca, 0xfd94533c, 0xffffc658, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfd7c9654, 0xfa792698, 0x00800610, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0ffffffc, 0x00000000, 0x1ffffff8, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfffed677, 0x0000029d, 0xfffdaa51, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc00019b9, 0x80000000, 0x00003371, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xeffffff9, 0xe0000001, 0xfffffff0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfc000000, 0xf8000003, 0xfffffffc, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x8ccccccd, 0x99999999, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0fffb73b, 0xffff6e78, 0x1ffffffe, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfff4e911, 0xfffa944b, 0xffef3dd6, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x000734ec, 0x000e69d6, 0x00000002, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffffff72, 0x00000000, 0xfffffee3, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbfcd0886, 0x80000000, 0xff9a110b, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0793bc28, 0x0793bc28, 0x0793bc28, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffffffd6, 0x00000000, 0xffffffab, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x4c294f11, 0x7fffffff, 0x18529e22, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000054, 0x00000000, 0x000000a7, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3fffffc0, 0x7fffffff, 0xffffff80, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf3333333, 0x80000000, 0x66666666, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfffffffe, 0x7ffffffb, 0x80000001, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00002e1a, 0x000070b7, 0xffffeb7c, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffd905d7, 0xffb4030a, 0xfffe08a3, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xedededee, 0x0f0f0f0f, 0xcccccccc, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x5ffffff0, 0x7fffffff, 0x3fffffe0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3b33332f, 0x66666666, 0x0ffffff8, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfffff2ad, 0x00000000, 0xffffe559, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000005, 0x00000009, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000001, 0x00000001, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x36db6db9, 0x6db6db6d, 0x00000005, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000002, 0x7fffffff, 0x80000005, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000001, 0x00000002, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000058, 0x80000000, 0x000000af, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbcccccce, 0xe0000003, 0x99999999, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf7ff8002, 0xffff0000, 0xf0000003, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x1ffffff9, 0x00000002, 0x3ffffff0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000005, 0x80000000, 0x00000009, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000005, 0x00000009, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xe38e38e2, 0xc71c71c7, 0xfffffffd, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00387f01, 0x00711173, 0xffffec8f, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000008, 0x8000000f, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffffffe0, 0x00000000, 0xffffffc0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbffffffd, 0x80000000, 0xfffffff9, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000002, 0x00000004, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbfffc643, 0xffff8c86, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0000001f, 0xfffffffe, 0x0000003f, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbfff8000, 0x80000000, 0xffff0000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf0000080, 0x000000ff, 0xe0000001, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000017, 0x0000002f, 0xfffffffe, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3ffffff0, 0x7fffffe0, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xe0000004, 0xc0000007, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf8787878, 0x00000000, 0xf0f0f0f0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfffa8163, 0xfffffff8, 0xfff502cd, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x24924925, 0x49249249, 0x00000001, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbfff77a4, 0xfffeef40, 0x80000007, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xbff2bb9c, 0x80000001, 0xffe57736, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc15f7fad, 0x80000000, 0x02beff5a, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfdc65340, 0xfb8ca680, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000690, 0x80000001, 0x00000d1e, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xb290f262, 0xe521e4c3, 0x80000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00003e81, 0x00007cff, 0x00000003, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xb1c71c74, 0xe38e38e3, 0x80000005, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x00000003, 0x00000000, 0x00000006, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x1f807f7c, 0x3ffffff8, 0xff00ff00, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfff7827d, 0xfff7827d, 0xfff7827d, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40088cfb, 0x001119f8, 0x7ffffffe, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xe38e3cb7, 0xc71c71c7, 0x000007a7, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3fffffe3, 0xffffffc9, 0x7ffffffc, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf5c71c70, 0xe38e38e3, 0x07fffffc, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3ffff9e6, 0x7ffffffb, 0xfffff3d0, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x003ed38d, 0x007da71b, 0xfffffffe, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3fffffff, 0x7ffffffa, 0x00000003, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000006, 0x0000000c, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x3fffffff, 0xfffffffe, 0x7fffffff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0003a055, 0x00000000, 0x000740a9, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xc0000003, 0xffffffff, 0x80000007, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x009322ba, 0x00000000, 0x01264574, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0012afc2, 0x00000668, 0x0025591c, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf8000083, 0xf0000007, 0x000000ff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xf1c71c72, 0xe38e38e3, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x400000ce, 0x7fffffff, 0x0000019c, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x0000006b, 0x00000000, 0x000000d5, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xfed45432, 0xfda8a765, 0x000000ff, 0x0, 0x0 + dspck_dstio addqh_r.w, 0xffffffe0, 0xffffffc0, 0x00000000, 0x0, 0x0 + dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + + writemsg "[45] Test subqh.w" + dspck_dstio subqh.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000002, 0xfffffffc, 0xfffffff8, 0x0, 0x0 + dspck_dstio subqh.w, 0x000001cf, 0xfffffff9, 0xfffffc5b, 0x0, 0x0 + dspck_dstio subqh.w, 0xffffffff, 0xffffffff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x0ffffffd, 0xfffffffe, 0xe0000003, 0x0, 0x0 + dspck_dstio subqh.w, 0xf1c71c73, 0xe38e38e3, 0xfffffffc, 0x0, 0x0 + dspck_dstio subqh.w, 0x40072e8c, 0x7ffffff8, 0xfff1a2df, 0x0, 0x0 + dspck_dstio subqh.w, 0xffff94d2, 0xffff29a5, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0xef8d03bd, 0xdf1a077b, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xefffffff, 0xfffffffc, 0x1ffffffe, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000010, 0x00000018, 0x7ffffff8, 0x0, 0x0 + dspck_dstio subqh.w, 0x43fffffa, 0x07fffffc, 0x80000007, 0x0, 0x0 + dspck_dstio subqh.w, 0xbfffffcf, 0x80000007, 0x00000069, 0x0, 0x0 + dspck_dstio subqh.w, 0xbf2a3e1a, 0xfe547c33, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000023, 0x80000006, 0xffffffc0, 0x0, 0x0 + dspck_dstio subqh.w, 0x07fffffc, 0x0ffffff8, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x78e38e38, 0x7fffffff, 0x8e38e38e, 0x0, 0x0 + dspck_dstio subqh.w, 0x38e380c1, 0xffffe510, 0x8e38e38e, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0008000, 0x80000000, 0xffff0000, 0x0, 0x0 + dspck_dstio subqh.w, 0x03935765, 0x00000000, 0xf8d95135, 0x0, 0x0 + dspck_dstio subqh.w, 0xffffffff, 0xffffffff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000007, 0x0000000e, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0xffedf426, 0xffdbe85d, 0x00000010, 0x0, 0x0 + dspck_dstio subqh.w, 0x0000011a, 0x0000023a, 0x00000005, 0x0, 0x0 + dspck_dstio subqh.w, 0x41ac198f, 0x7ffffff8, 0xfca7ccd9, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000003, 0x7fffffff, 0x7ffffff9, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000020, 0x00000021, 0x7fffffe0, 0x0, 0x0 + dspck_dstio subqh.w, 0xbffffffd, 0xfffffffa, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0xff1f0938, 0x00000000, 0x01c1ed8f, 0x0, 0x0 + dspck_dstio subqh.w, 0x01f31c43, 0xffe63888, 0xfc000001, 0x0, 0x0 + dspck_dstio subqh.w, 0x7ffffffd, 0x7fffffff, 0x80000005, 0x0, 0x0 + dspck_dstio subqh.w, 0x0ccccccc, 0x7fffffff, 0x66666666, 0x0, 0x0 + dspck_dstio subqh.w, 0x3ffffffc, 0xffffffff, 0x80000007, 0x0, 0x0 + dspck_dstio subqh.w, 0xadb6db6e, 0xdb6db6db, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x1c398ddd, 0x00000000, 0xc78ce445, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xffe4e571, 0xffc9c9e2, 0xffffff00, 0x0, 0x0 + dspck_dstio subqh.w, 0xfffee4e2, 0xfffe5537, 0x00008b73, 0x0, 0x0 + dspck_dstio subqh.w, 0xfffd2c0b, 0xffff0000, 0x0004a7ea, 0x0, 0x0 + dspck_dstio subqh.w, 0x3fd334e4, 0x7ffffffd, 0x00599635, 0x0, 0x0 + dspck_dstio subqh.w, 0x0e38e90e, 0x1c71c71c, 0xfffff500, 0x0, 0x0 + dspck_dstio subqh.w, 0xcffffff8, 0x80000000, 0xe000000f, 0x0, 0x0 + dspck_dstio subqh.w, 0xfffffffe, 0x00000000, 0x00000004, 0x0, 0x0 + dspck_dstio subqh.w, 0x4000000c, 0x00000018, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x00000000, 0xffffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0xffa1a497, 0xffffff80, 0x00bcb652, 0x0, 0x0 + dspck_dstio subqh.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x4000003f, 0x7fffffff, 0xffffff80, 0x0, 0x0 + dspck_dstio subqh.w, 0xbf807f80, 0x80000000, 0x00ff00ff, 0x0, 0x0 + dspck_dstio subqh.w, 0x07576dca, 0x0eaedb95, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xd4cccccc, 0x0ffffffe, 0x66666666, 0x0, 0x0 + dspck_dstio subqh.w, 0x3fffff6d, 0xfffffedb, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000002, 0x00000000, 0xfffffffc, 0x0, 0x0 + dspck_dstio subqh.w, 0x40000002, 0x7fffffff, 0xfffffffa, 0x0, 0x0 + dspck_dstio subqh.w, 0xffffff80, 0xffffff00, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xc9249247, 0xfffffffc, 0x6db6db6d, 0x0, 0x0 + dspck_dstio subqh.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x05e03a4e, 0xfff7f3dd, 0xf4377f41, 0x0, 0x0 + dspck_dstio subqh.w, 0x80000001, 0x80000000, 0x7ffffffd, 0x0, 0x0 + dspck_dstio subqh.w, 0xe66664e6, 0xfffffd00, 0x33333333, 0x0, 0x0 + dspck_dstio subqh.w, 0x0000b407, 0x00016802, 0xfffffff3, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000189, 0x000002f2, 0xffffffe0, 0x0, 0x0 + dspck_dstio subqh.w, 0x3ffc3657, 0xfff86caf, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xdff8bda6, 0xfff17b4a, 0x3ffffffe, 0x0, 0x0 + dspck_dstio subqh.w, 0xc1835749, 0x0306ae91, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x07fffede, 0x0ffffff8, 0x0000023b, 0x0, 0x0 + dspck_dstio subqh.w, 0x3ffffff0, 0x00000000, 0x8000001f, 0x0, 0x0 + dspck_dstio subqh.w, 0xe0000004, 0xc000000f, 0x00000007, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x3ff77753, 0xffeeeea7, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0xcffffffe, 0x80000000, 0xe0000003, 0x0, 0x0 + dspck_dstio subqh.w, 0x0e36c890, 0xfffbca03, 0xe38e38e3, 0x0, 0x0 + dspck_dstio subqh.w, 0xfffffffd, 0xfffffffb, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x3ffffe2c, 0x7fffffff, 0x000003a6, 0x0, 0x0 + dspck_dstio subqh.w, 0xbfff4575, 0x80000000, 0x00017515, 0x0, 0x0 + dspck_dstio subqh.w, 0xc00004b7, 0x80000003, 0xfffff694, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xbffffff8, 0xffffffeb, 0x7ffffffb, 0x0, 0x0 + dspck_dstio subqh.w, 0x3fffffbd, 0x7fffffe0, 0x00000066, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x105324c2, 0x00a6498c, 0xe0000007, 0x0, 0x0 + dspck_dstio subqh.w, 0x2000000f, 0xc000001f, 0x80000001, 0x0, 0x0 + dspck_dstio subqh.w, 0xc000000f, 0x8000001f, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x0001894e, 0x00031261, 0xffffffc5, 0x0, 0x0 + dspck_dstio subqh.w, 0x3ffffffe, 0x7fffffff, 0x00000003, 0x0, 0x0 + dspck_dstio subqh.w, 0xf80b23d0, 0xf0f0f0f0, 0x00daa950, 0x0, 0x0 + dspck_dstio subqh.w, 0x07c00d4c, 0x0ffffffc, 0x007fe564, 0x0, 0x0 + dspck_dstio subqh.w, 0x3fffffbb, 0xfffffff6, 0x8000007f, 0x0, 0x0 + dspck_dstio subqh.w, 0x400075bb, 0x7fffffff, 0xffff1489, 0x0, 0x0 + dspck_dstio subqh.w, 0xbf6334b0, 0x80000000, 0x013996a0, 0x0, 0x0 + dspck_dstio subqh.w, 0xc3fffffe, 0x80000000, 0xf8000003, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x0000021e, 0x0000021e, 0x0, 0x0 + dspck_dstio subqh.w, 0x36db6db7, 0x00000001, 0x92492492, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0434639, 0x8000001f, 0xff7973ad, 0x0, 0x0 + dspck_dstio subqh.w, 0xffffd64d, 0x00000000, 0x00005365, 0x0, 0x0 + dspck_dstio subqh.w, 0xeb20f296, 0xc000000f, 0xe9be1ae2, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000001, 0x80000002, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xbfffffc0, 0xffffff80, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0xeaaaaaab, 0x80000000, 0xaaaaaaaa, 0x0, 0x0 + dspck_dstio subqh.w, 0x18000003, 0xf0000007, 0xc0000001, 0x0, 0x0 + dspck_dstio subqh.w, 0xbea0ad0c, 0x80000005, 0x02bea5ec, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000009, 0x00000012, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x000d812e, 0x001b025c, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xf8787875, 0xfffffff9, 0x0f0f0f0f, 0x0, 0x0 + dspck_dstio subqh.w, 0xf6ce4183, 0xfffde50e, 0x12616208, 0x0, 0x0 + dspck_dstio subqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x36db6db5, 0xfffffffc, 0x92492492, 0x0, 0x0 + dspck_dstio subqh.w, 0xbc000002, 0xf8000003, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xfffffffc, 0x00000000, 0x00000007, 0x0, 0x0 + dspck_dstio subqh.w, 0xdffffffc, 0x3ffffff8, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x00206760, 0x00029488, 0xffc1c5c8, 0x0, 0x0 + dspck_dstio subqh.w, 0xc000000a, 0x80000000, 0xffffffeb, 0x0, 0x0 + dspck_dstio subqh.w, 0x7fffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x76db6db6, 0x6db6db6d, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x10000008, 0x1ffffffe, 0xffffffee, 0x0, 0x0 + dspck_dstio subqh.w, 0x000009b0, 0x00001360, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xbf94ea3f, 0xf0f0f0f0, 0x71c71c71, 0x0, 0x0 + dspck_dstio subqh.w, 0x40000000, 0x7fffffff, 0xffffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x02242312, 0x0448a055, 0x00005a30, 0x0, 0x0 + dspck_dstio subqh.w, 0x3ffff1b4, 0xffffe368, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x7fffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000002, 0x00000004, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x3ffffff8, 0xfffffff0, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x0fffffff, 0x1ffffffc, 0xfffffffe, 0x0, 0x0 + dspck_dstio subqh.w, 0xc71c06f7, 0x8e38e38e, 0x0000d59f, 0x0, 0x0 + dspck_dstio subqh.w, 0xffffcc01, 0xffff9802, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x40000071, 0x7fffffff, 0xffffff1d, 0x0, 0x0 + dspck_dstio subqh.w, 0xbffffd5c, 0x80000000, 0x00000547, 0x0, 0x0 + dspck_dstio subqh.w, 0x400006c3, 0x7fffffff, 0xfffff279, 0x0, 0x0 + dspck_dstio subqh.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x8000000f, 0x8000000f, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000007, 0x0000000f, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xb6e5ed26, 0x80000000, 0x123425b3, 0x0, 0x0 + dspck_dstio subqh.w, 0xbfffff8b, 0xffffff15, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x4000007f, 0x7fffffff, 0xffffff00, 0x0, 0x0 + dspck_dstio subqh.w, 0x0000007f, 0x000000ff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x8ccccccd, 0x80000000, 0x66666666, 0x0, 0x0 + dspck_dstio subqh.w, 0x3fffff9b, 0x7fffffff, 0x000000c8, 0x0, 0x0 + dspck_dstio subqh.w, 0xc9249249, 0x00000000, 0x6db6db6d, 0x0, 0x0 + dspck_dstio subqh.w, 0xfffffd6d, 0xfffffad2, 0xfffffff8, 0x0, 0x0 + dspck_dstio subqh.w, 0xc05a2b05, 0x00b455eb, 0x7fffffe0, 0x0, 0x0 + dspck_dstio subqh.w, 0xf8000002, 0x00000000, 0x0ffffffc, 0x0, 0x0 + dspck_dstio subqh.w, 0xce38e38e, 0x80000000, 0xe38e38e3, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000010, 0x00000000, 0xffffffe0, 0x0, 0x0 + dspck_dstio subqh.w, 0x4000000f, 0x0000001f, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x76db6db6, 0x6db6db6d, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x245f6257, 0x49249249, 0x0065cd9b, 0x0, 0x0 + dspck_dstio subqh.w, 0xfff90c88, 0x00000000, 0x000de6ef, 0x0, 0x0 + dspck_dstio subqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xb0000008, 0x80000000, 0x1ffffff0, 0x0, 0x0 + dspck_dstio subqh.w, 0x3f69acda, 0x7fffffff, 0x012ca64a, 0x0, 0x0 + dspck_dstio subqh.w, 0x0000001c, 0x00000002, 0xffffffca, 0x0, 0x0 + dspck_dstio subqh.w, 0x47ffffff, 0x7fffffff, 0xf0000001, 0x0, 0x0 + dspck_dstio subqh.w, 0x7fffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xbed9f06a, 0x8000000f, 0x024c1f3b, 0x0, 0x0 + dspck_dstio subqh.w, 0xbfffff81, 0xffffff02, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x00007ffc, 0xfffffff8, 0xffff0000, 0x0, 0x0 + dspck_dstio subqh.w, 0xe30e12e7, 0xe28decea, 0x1c71c71c, 0x0, 0x0 + dspck_dstio subqh.w, 0xf1c71c52, 0xffffffc1, 0x1c71c71c, 0x0, 0x0 + dspck_dstio subqh.w, 0x0000d973, 0x0001739e, 0xffffc0b7, 0x0, 0x0 + dspck_dstio subqh.w, 0xe1bd3033, 0x037a605e, 0x3ffffff8, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000003, 0x80000006, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x4000001f, 0x0000003f, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xdb6db6de, 0x00000005, 0x49249249, 0x0, 0x0 + dspck_dstio subqh.w, 0x7fffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0003cd9, 0x8000007f, 0xffff86cc, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000053, 0xfffffff9, 0xffffff53, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000001, 0x00000003, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x0000001e, 0xfffffe63, 0xfffffe27, 0x0, 0x0 + dspck_dstio subqh.w, 0xffffffff, 0x00000000, 0x00000001, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000001, 0x0000000a, 0x00000008, 0x0, 0x0 + dspck_dstio subqh.w, 0xdfffffff, 0x80000000, 0xc0000001, 0x0, 0x0 + dspck_dstio subqh.w, 0xf34e99c0, 0xe784bb19, 0x00e78799, 0x0, 0x0 + dspck_dstio subqh.w, 0x3ffffffc, 0x7ffffff8, 0xffffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x0000007f, 0xfffffffe, 0xffffff00, 0x0, 0x0 + dspck_dstio subqh.w, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0xbffc0915, 0xfff81228, 0x7ffffffe, 0x0, 0x0 + dspck_dstio subqh.w, 0x0000049b, 0x000000ff, 0xfffff7c8, 0x0, 0x0 + dspck_dstio subqh.w, 0x000056e0, 0x00015b1a, 0x0000ad5a, 0x0, 0x0 + dspck_dstio subqh.w, 0x4e38e38e, 0x7fffffff, 0xe38e38e3, 0x0, 0x0 + dspck_dstio subqh.w, 0x00029102, 0x000521e5, 0xffffffe0, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x00000010, 0x00000010, 0x0, 0x0 + dspck_dstio subqh.w, 0x52492492, 0x24924924, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xfbffffff, 0xfffffffc, 0x07fffffe, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000002, 0x00000001, 0xfffffffc, 0x0, 0x0 + dspck_dstio subqh.w, 0xbffefb51, 0x80000001, 0x0002095e, 0x0, 0x0 + dspck_dstio subqh.w, 0x12343403, 0xffd61ee2, 0xdb6db6db, 0x0, 0x0 + dspck_dstio subqh.w, 0xc9249251, 0x92492492, 0xfffffff0, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000001, 0x00000002, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x3ffead8b, 0xfffd5b16, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x111a2950, 0x023452a1, 0xe0000001, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xe0001c7d, 0xc0000003, 0xffffc708, 0x0, 0x0 + dspck_dstio subqh.w, 0xfffffff8, 0x00000000, 0x0000000f, 0x0, 0x0 + dspck_dstio subqh.w, 0x12492482, 0x24924924, 0x0000001f, 0x0, 0x0 + dspck_dstio subqh.w, 0x3ffffcaf, 0x7fffffc0, 0x00000662, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xeaaaaaab, 0x55555555, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x80000001, 0x80000000, 0x7ffffffd, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x1db10c4b, 0x1db10c4b, 0x0, 0x0 + dspck_dstio subqh.w, 0xfffffffd, 0x00000000, 0x00000005, 0x0, 0x0 + dspck_dstio subqh.w, 0x3fffffe0, 0x7fffffff, 0x0000003f, 0x0, 0x0 + dspck_dstio subqh.w, 0x3ffffffa, 0xfffffffa, 0x80000005, 0x0, 0x0 + dspck_dstio subqh.w, 0xd8787888, 0xc000001f, 0x0f0f0f0f, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000002, 0x00000000, 0x7ffffffb, 0x0, 0x0 + dspck_dstio subqh.w, 0xffffb823, 0xffff704b, 0x00000005, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0xe0000002, 0xc000000f, 0x0000000b, 0x0, 0x0 + dspck_dstio subqh.w, 0x7fffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_dstio subqh.w, 0x3fc87d59, 0xff90fb32, 0x8000007f, 0x0, 0x0 + dspck_dstio subqh.w, 0xbfffffda, 0x80000006, 0x00000051, 0x0, 0x0 + dspck_dstio subqh.w, 0x0dd0d75a, 0xfc000001, 0xe05e514d, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x403ce94e, 0x7fffffff, 0xff862d63, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0xffffffff, 0xffffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0xc0000000, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x0260df06, 0x03fffffe, 0xff3e41f2, 0x0, 0x0 + dspck_dstio subqh.w, 0xfffffffb, 0x00000000, 0x0000000a, 0x0, 0x0 + dspck_dstio subqh.w, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh.w, 0x045c6e60, 0x00368e02, 0xf77db141, 0x0, 0x0 + dspck_dstio subqh.w, 0xc1a2e7f1, 0x0345cfdd, 0x7ffffffb, 0x0, 0x0 + dspck_dstio subqh.w, 0xffffffc0, 0x00000000, 0x0000007f, 0x0, 0x0 + dspck_dstio subqh.w, 0xf0000008, 0x0000000f, 0x1ffffffe, 0x0, 0x0 + dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh.w, 0xbfffffff, 0x80000000, 0x00000001, 0x0, 0x0 + dspck_dstio subqh.w, 0x4ffffffc, 0x1ffffff8, 0x80000000, 0x0, 0x0 + + writemsg "[46] Test subqh_r.w" + dspck_dstio subqh_r.w, 0xffffffff, 0x7ffffffc, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3ffffff3, 0x00000004, 0x8000001f, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3b0ded23, 0x7fffffff, 0x09e425ba, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffff6353, 0x00000000, 0x0001395a, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x00488e7e, 0x00488e7e, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xce38e38f, 0x80000000, 0xe38e38e3, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x31c71c70, 0xe38e38e3, 0x80000003, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00872e0d, 0x010e5c19, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffdde0b5, 0xffbbc97c, 0x00000812, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3fc71e03, 0x7fffffff, 0x0071c3fa, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xff89baf8, 0x0000001d, 0x00ec8a2e, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000002, 0x80000000, 0xfffffffc, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffff93b, 0xfffff276, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000010, 0x00000000, 0x7fffffe0, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffff1fb, 0xffffe3f3, 0xfffffffd, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffff9171, 0x000022e1, 0x0000ffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000002, 0x00000004, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000001, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc00002c5, 0x00000583, 0x7ffffff9, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xde000005, 0xfc000001, 0x3ffffff8, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffffffff, 0x00000000, 0x00000002, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xedb6db6b, 0xdb6db6db, 0x00000005, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3fffff9a, 0x7ffffffa, 0x000000c7, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x000003fe, 0x00000800, 0x00000005, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xa6666667, 0xcccccccc, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3fffb09e, 0xffff613c, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x12492492, 0x24924924, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x1ffffffe, 0x3ffffffe, 0x00000003, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x0000001c, 0x7ffffff8, 0x7fffffc0, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffe2283, 0xfffffed4, 0x0003b9ce, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xf1c64eb3, 0xfffe6481, 0x1c71c71c, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000011, 0x00000020, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000040, 0x00000000, 0x7fffff80, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000003, 0x7fffffff, 0xfffffffa, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xa0000002, 0x80000001, 0x3ffffffe, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x17fffffd, 0x0ffffffc, 0xe0000003, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000019, 0x0000003f, 0x0000000e, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x4000004e, 0x7fffffff, 0xffffff63, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffa5206, 0xfff4bb71, 0x00001766, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000001, 0x00000001, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xd0000000, 0x80000000, 0xe0000001, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000008, 0x0000000f, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffffb5d, 0x00000000, 0x00000947, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x95555556, 0xaaaaaaaa, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xedb6e224, 0x00000d6c, 0x24924924, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000004, 0xffffffff, 0xfffffff8, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x01304bc6, 0x0000000b, 0xfd9f687f, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3c000002, 0x7fffffff, 0x07fffffc, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3ffffff0, 0x7fffffff, 0x0000001f, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3ffffffe, 0x00000000, 0x80000004, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000001, 0x7fffffff, 0x7ffffffe, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffffffe, 0x00000000, 0x00000004, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xbfffffa2, 0x80000004, 0x000000c1, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000010, 0x00000020, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffb06b9, 0xfff60d71, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000005, 0x00000008, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x000001c7, 0xfffffff8, 0xfffffc6b, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc4000000, 0x07fffffe, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x4fffffff, 0x7fffffff, 0xe0000001, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffffe055, 0xfffffffd, 0x00003f53, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x09624045, 0xfffffc0a, 0xed3b7b80, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x36db6db7, 0x00000000, 0x92492492, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000080, 0x000000ff, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x1dee5b50, 0x3be82111, 0x000b6a71, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xa0000001, 0xc0000001, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x36db6df7, 0x0000007f, 0x92492492, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffff24e1, 0xfffe3d5c, 0xfffff39a, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000004, 0x00000000, 0xfffffff9, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc924924a, 0x00000000, 0x6db6db6d, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3f3b9830, 0x7fffffff, 0x0188cf9f, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000eb2, 0x00001d64, 0x80000001, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xf8000001, 0x00000000, 0x0ffffffe, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffff693, 0xfffffff9, 0x000012d4, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xe0000002, 0x3ffffffc, 0x7ffffff8, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffffffd, 0xfffffffa, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x4000791b, 0x0000f236, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffffffe5, 0x00000009, 0x0000003f, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffffffe1, 0x00000000, 0x0000003f, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffffffe, 0x7ffffffb, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000020, 0x0000003f, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x400016d4, 0x00002da7, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xefffa3ce, 0xe000000f, 0x0000b874, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x0000000f, 0x0000001d, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000002, 0x80000000, 0xfffffffd, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xd8000003, 0xf0000001, 0x3ffffffc, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x0000000e, 0xffffff9b, 0xffffff80, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3ff8eab8, 0xfff1d573, 0x80000003, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x4055317a, 0x00aa62f3, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xff688053, 0x0000001f, 0x012eff79, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc000041e, 0x00000838, 0x7ffffffd, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc001e15d, 0x0003c2b8, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3ffffffd, 0x7fffffff, 0x00000006, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc71c718c, 0xffffff89, 0x71c71c71, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x20000000, 0x00000000, 0xc0000001, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x1000017d, 0x1ffffff8, 0xfffffcfe, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfb5dbcbf, 0x00000000, 0x09448683, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffffff1, 0x7fffffe0, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xbffffcaf, 0xfffff95c, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x0000037c, 0x000006f8, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc08c8a8b, 0x01191514, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xff63dc33, 0x00000000, 0x0138479b, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xff523fac, 0x00000000, 0x015b80a8, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000002, 0x7fffffff, 0xfffffffb, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xd5555555, 0xaaaaaaaa, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3e000001, 0xfc000001, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfdfffff3, 0xffffffe4, 0x03fffffe, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000008, 0x8000000f, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000001, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x0200001f, 0x0000003f, 0xfc000001, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x01f2725a, 0x03fffffe, 0x001b1b4a, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xbfea0af9, 0xffd415f1, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffac2a9, 0xfff58552, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000430, 0x00000846, 0xffffffe6, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x4000012a, 0x00000254, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xccccccca, 0x99999999, 0x00000005, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc000386c, 0x00007057, 0x7fffff80, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xf1c71cf2, 0x000000ff, 0x1c71c71c, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffffffc, 0x1ffffff0, 0x1ffffff8, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x95555556, 0x80000000, 0x55555555, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xf1c71c71, 0xfffffffe, 0x1c71c71c, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x4002c377, 0x7fffff80, 0xfffa7893, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfff485a0, 0xffe90b40, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xbfffffb7, 0xffffff6d, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000165, 0xfffffffc, 0xfffffd33, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffffff80, 0xffffff00, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xe4924926, 0x49249249, 0x7ffffffe, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffffe93, 0xfffffd26, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x03878789, 0x0f0f0f0f, 0x07fffffe, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000004, 0x00000000, 0xfffffff8, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xe6666667, 0x00000000, 0x33333333, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0004bdf, 0x80000000, 0xffff6842, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xcd96d052, 0x1b2da0a2, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x07ffffff, 0x0ffffffe, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x80000001, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000001, 0x00000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xf7ffff48, 0xf0000007, 0x00000177, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfbfffc7c, 0xf8000001, 0x00000709, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc000005d, 0x000000b9, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000008, 0x00000000, 0xfffffff0, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffa3bd56, 0xffc442a7, 0x007cc7fc, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00011efa, 0x00000000, 0xfffdc20d, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x402580d4, 0x7fffff80, 0xffb4fdd9, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x0000000f, 0x0000001b, 0xfffffffe, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xe0000001, 0x00000000, 0x3ffffffe, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000ec0, 0x00001d7e, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffff7a5b, 0xfffef4b5, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x80000001, 0x80000000, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x16db6dbb, 0x6db6db6d, 0x3ffffff8, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000052, 0x00000000, 0xffffff5d, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xe0000001, 0xc0000001, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xb1c71c72, 0xe38e38e3, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x051c79f3, 0x0a38f3e5, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0xfffffffe, 0xffffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffffffff, 0x7ffffffd, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xbffffffe, 0x80000000, 0x00000004, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xe9c71c74, 0xe38e38e3, 0x0ffffffc, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffff1e1, 0x0000001f, 0x00001c5d, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3ffffffd, 0xfffffffa, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3f304cb7, 0xfe60996d, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x1ffffffe, 0x1ffffffe, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfddf601d, 0xfffb717e, 0x043cb145, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffffe59, 0xffffffa2, 0x000002f1, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x41ffffff, 0x03fffffe, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffee8aec, 0xffdd15f6, 0x0000001f, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3ffffff9, 0x00000000, 0x8000000f, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfff9b067, 0x000192c2, 0x000e31f5, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x0138583e, 0x0270b07b, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x52492492, 0x24924924, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x0005ef18, 0x000bdd2f, 0xffffff00, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xbffffffe, 0xfffffffa, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000001, 0x7fffffff, 0xfffffffe, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xd5555556, 0x00000000, 0x55555555, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000008, 0x0000000f, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc8000003, 0x0ffffffe, 0x7ffffff9, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xe6666667, 0x33333333, 0x66666666, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xd555553a, 0xaaaaaaaa, 0x00000037, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x43ffffff, 0x7fffffff, 0xf8000001, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xa0000004, 0x80000000, 0x3ffffff8, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x76db6db7, 0x7fffffff, 0x92492492, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3fffffa4, 0xffffff47, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000256, 0x7ffffff0, 0xfffffb44, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x03fccfc0, 0xfff99f81, 0xf8000001, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000169, 0x0000003f, 0xfffffd6d, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x000036cc, 0x00006d99, 0x00000001, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000001, 0x00000000, 0x7ffffffe, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x07fffffe, 0x0ffffffc, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x01ffffff, 0x03fffffe, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3f769ced, 0xfeed39d9, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc928f7da, 0x92492492, 0xfff734de, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000001, 0x00000001, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc00089a4, 0x80000000, 0xfffeecb9, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x0001e8c1, 0xffffffff, 0xfffc2e7e, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x040001c0, 0x00000383, 0xf8000003, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffe677c, 0x00000005, 0x0003310d, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x007f8080, 0x00000000, 0xff00ff00, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xc0000002, 0x00000003, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xa38e38e4, 0xc71c71c7, 0x7fffffff, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000003, 0x00000006, 0x00000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x3fffebd9, 0xffffd7b2, 0x80000000, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x384f2cdc, 0x7ffffffb, 0x0f61a643, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffdc404b, 0xffffff16, 0x00477e80, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x06196184, 0x0c313aef, 0xfffe77e8, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xbfffe9cf, 0x80000003, 0x00002c65, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xff61cc0c, 0xfec39819, 0x00000001, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffffffff, 0xffffffff, 0x00000002, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xffb8e420, 0xfe72c740, 0xff00ff00, 0x0, 0x0 + dspck_dstio subqh_r.w, 0xfffffff9, 0x00000000, 0x0000000f, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000000, 0xffbf1455, 0xffbf1455, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000399, 0x00000000, 0xfffff8cf, 0x0, 0x0 + dspck_dstio subqh_r.w, 0x00000020, 0x7fffffff, 0x7fffffc0, 0x0, 0x0 + + writemsg "[47] Test dpax.w.ph" + dspck_astio dpax.w.ph, 0xffcc0271, 0xca18bc2e, 0xffcc0271, 0xca57d72e, 0xfb808000, 0x0000f1fa, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xfffffffe, 0x23cfbe27, 0xfffffffe, 0x1d2fbe27, 0x0ff80d40, 0x80000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffcca479, 0xd7f08525, 0xffcca479, 0xd7f40525, 0x80000000, 0x7ffffff9, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xfffffffa, 0x80000000, 0x00750010, 0xff00ffea, 0x7fff8000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xe0000000, 0x00000001, 0xdfffffff, 0xffff8003, 0x00008002, 0x00018000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xfff6fe31, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffe83c, 0x7ee98f5a, 0xffffe83c, 0x7ee99763, 0x00010000, 0xfb9a0809, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x0077b797, 0x00000000, 0x0077b797, 0x01aa7ff8, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x0c988000, 0xe6f08000, 0xffdf8000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xff389ae7, 0xffffffff, 0xff389ae7, 0x00000000, 0x00030006, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffff55, 0x4ce6cffe, 0xffffff55, 0x4d31e1e9, 0xfb4ffe59, 0xfffcf001, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xff764a9a, 0xffffffff, 0xbf764aba, 0x7fff3ff0, 0xfffe8000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffed545b, 0xba8b4081, 0xffed545b, 0xba8b4081, 0x00000000, 0x7fff0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x02de41b6, 0x7fff05f4, 0x7fe0ffca, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x8e38e38e, 0x38e38e38, 0x8e38e38e, 0x38f888f8, 0x00007fe0, 0x002a7ffa, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x003959f5, 0xc83b70dd, 0x003959f5, 0xc85db054, 0x0e5ec001, 0xff770000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x0000000c, 0x4b8b9d19, 0x0000000c, 0x4b92db66, 0xc00f8000, 0x0000ffe3, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00006e32, 0x00000000, 0x0001ade7, 0x0000fffb, 0xc00f7fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffffffe1, 0x001f0a00, 0x0000ffff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f3dc7f, 0x000efc7d, 0xff2bfff8, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000005, 0x00000000, 0x3f8d80e9, 0x00e37fff, 0x7fff8001, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x1fffffff, 0xfffffff0, 0x20000000, 0x007f5245, 0x0ee400ff, 0x7ffffffd, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0x80010000, 0x80008000, 0x7fff7fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x0004056c, 0xff00e1aa, 0xffde0002, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x400fffdf, 0x7fff7fff, 0x00227fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x2aaa71cb, 0xaaaa1c71, 0xfffb8000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfff15a90, 0x800000b8, 0x007e001e, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x3fffffff, 0xfffffff8, 0x40000000, 0x010d6008, 0x0ff88000, 0xffe40ffe, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xe0203fbf, 0x00003fc0, 0x80010000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfd466820, 0x00ff3333, 0xf260ffff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x0fffffff, 0xfffffffc, 0x10000000, 0x002dcbf4, 0x0ffcee0b, 0xfd740001, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x24924924, 0x92492492, 0x24924924, 0x524aa490, 0x7fff7fff, 0x80000002, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xe66b6847, 0xffffffff, 0xe658686d, 0xffed7fff, 0xffed7fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfffe148d, 0x07cd0000, 0xfc76ffc1, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x0000007f, 0x00000000, 0x0000007f, 0x0f0f0388, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x000006af, 0xabcceced, 0x000006af, 0x72e894b5, 0xff807fff, 0x8e380194, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfe629883, 0x067c0000, 0x7ff0c03f, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xc0000000, 0x00000003, 0xbfffffff, 0xfff8f032, 0x2585801f, 0xfffeffc9, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x10b8748a, 0x743c61f0, 0x10b8748a, 0x6cb896c3, 0xffde0f0f, 0x803fffff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x008405b0, 0x557c83bc, 0x008405b0, 0x5709a350, 0x00243ff0, 0x06065555, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xffe5a17f, 0x00000000, 0x3fe5a17f, 0x8000ffac, 0x00008000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0ffef098, 0x7fff0587, 0x00031ffc, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000012, 0x00000000, 0x00400012, 0x0000ff80, 0x80000f0f, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00001250, 0x00000000, 0x0003df0a, 0x001effc8, 0x33337fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x66666666, 0x66666666, 0x66666666, 0x76628666, 0x1ff80002, 0x1ffc7fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000004, 0x00000000, 0x3fdfffc5, 0x003f807f, 0x80007fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x170b47a0, 0xe8f48004, 0xe8f48004, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffff3380, 0x001f0199, 0xff800000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xffffffff, 0x00000000, 0x00000095, 0x80000032, 0x00030000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfd8893bc, 0x13bcfffd, 0x0000e001, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x0b4f9e09, 0x00000000, 0x0b211fda, 0x80050000, 0x0ffc005d, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00030100, 0xff808000, 0xfffafffe, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000001, 0x80000000, 0x3fd80011, 0x80007ff0, 0x7fff003f, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xff013549, 0x681031d4, 0xff013549, 0x68130382, 0xf001ffed, 0xffe7ffd3, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xc0000000, 0x00000007, 0xbfffffff, 0xff809ee8, 0x0000801f, 0x00ff0a86, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xbfbf01c0, 0x8000fef9, 0x3fc07fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfffb000a, 0x7ffffffb, 0x7ffffffb, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfb6ff842, 0x0ff8ffff, 0x00e6b6db, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x0000088e, 0xffffffff, 0xffb9b579, 0x1c717ffc, 0xff58007b, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x0000000e, 0x00000000, 0x03fdf812, 0x7fff7fff, 0x07fefffe, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x66666666, 0x66666666, 0x66666666, 0xe6666666, 0x80008000, 0x80008000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xecf94b29, 0x00000000, 0x25df4b25, 0x00048e38, 0x80007fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x04020001, 0x8000fffe, 0x7ffff7fa, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xc0028000, 0x7ffb0000, 0xfffd8000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xf255837f, 0x47886f17, 0xf255837f, 0x0788f7b3, 0x8000ffe3, 0xffb47fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00027ffb, 0x00058000, 0x00007fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x03e1cdf8, 0xa96c16d6, 0x03e1cdf8, 0xe97096d6, 0xfff08000, 0x80078000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xd9e94f4d, 0x9d784e3b, 0xd9e94f4d, 0x3d7a8e38, 0x7fff7fff, 0xc0038000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x3fffffff, 0xfffffff8, 0x40000000, 0x0003fff0, 0x7fff7fff, 0x00080000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x1006fc7a, 0x1fc800ca, 0x2d997ff8, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x154a9560, 0x00003fe0, 0x55558000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffd8, 0x79c870b1, 0xffffffd8, 0x8c1ef049, 0x7ffc8000, 0xdb6d001a, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xffff36bb, 0xe003fffc, 0x2a520001, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x0000f2f5, 0x7c6b1ec2, 0x0000f2f5, 0x3c689ec8, 0x7fff8000, 0x7ffffffa, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xf0037fff, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xffffd533, 0xffffffff, 0xe001152f, 0x3ffc8000, 0x00028001, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xffffffc0, 0xffffffff, 0xfffe904a, 0xf8030017, 0xf8030017, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xfffce093, 0x7f16d58e, 0xfffce093, 0xc3a910fb, 0xdb6d8000, 0x8000e001, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xe0000000, 0x00000007, 0xe0000000, 0x00097ff4, 0x3a807fff, 0x00130000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffe5807f, 0xffff8000, 0x0035ff80, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x01e1c1e2, 0x1ffe0000, 0x03540f0f, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xffffff00, 0x00000000, 0x00150ee6, 0x8000fcd2, 0xfffbffd6, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xf4d6bbe0, 0xd4af2714, 0xf4d6bbe0, 0xd4af0be0, 0xfffe000a, 0xfd2aff6c, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xfffe180f, 0xffffffff, 0xfffe180f, 0x0ff87fff, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000006, 0x00000000, 0x012afdb0, 0xc0037fff, 0x02560000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00064bde, 0x6def2da8, 0x00064bde, 0x6def2da8, 0x00008001, 0x000038e3, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x001f0000, 0xf5fa0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xfffabeee, 0xffffffff, 0xc002beee, 0x80000000, 0x66667ff0, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x000a4200, 0x00000328, 0x03400000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x04877fff, 0x80008000, 0x0000f6f1, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x1fffffff, 0xfffffff8, 0x1fffffff, 0xfe048377, 0x0040fc01, 0x7fff0ffe, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x38e38e38, 0xe38e38e3, 0x38e38e38, 0xe38f38e1, 0x00027fff, 0x00020000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xfdb52b6d, 0xffffffff, 0xddb62b6d, 0xfffc3ffe, 0x80000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xffffff86, 0xffffffff, 0xff5b89a5, 0x052400ff, 0x0005e001, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x3ffe405a, 0x8000e00f, 0x00068002, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffe07fff, 0x00008000, 0x003f001d, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00002dcb, 0xf9bc70cf, 0x00002dcb, 0xe2d9b0df, 0x2dc53ff0, 0xffff8000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x3fffffff, 0xfffffffc, 0x40000000, 0x0001000c, 0xe0018000, 0xfffa0010, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xff4e7ffd, 0x00028000, 0x01657fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x3fffffff, 0xfffffffe, 0x40000000, 0x1c733e1f, 0x38e307fc, 0x003f7fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x00000000, 0xe30bfff4, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x38e38e38, 0xe38e38e3, 0x38e38e38, 0xe38e38e3, 0x00000000, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xf0000000, 0x00000007, 0xefffffff, 0xff92052f, 0x80047ffa, 0xff240000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xf576e81f, 0xffffffff, 0xf576e81f, 0x00000000, 0x01dbff60, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xfc000000, 0x00000001, 0xfc000000, 0x000a8001, 0x00008000, 0xffeb7fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x0011e31c, 0x00000000, 0x000d822a, 0xff00c00f, 0x0012ffe2, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x000068c0, 0x00000000, 0x000ee8a3, 0x7fff0000, 0xfff5001d, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfaa7727f, 0x051b8000, 0x0fc77f80, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xffff8018, 0x80007ff8, 0xfffdfffe, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00157fc0, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x0144fd76, 0x0ff87fff, 0x028a0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xf8000000, 0x00000003, 0xf7ffffff, 0xbfd81c3f, 0x07fc7fff, 0x8000faf1, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xfffffffe, 0x00000000, 0x009a9c28, 0x0da2ff80, 0xe2c90a45, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000004, 0x00000000, 0x000015e8, 0x00000579, 0x00048000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x000db8ca, 0xe62a7100, 0x000db8ca, 0xe62be7f4, 0x0007007f, 0x02f10033, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xff6a2e0d, 0x0000e003, 0x04afe001, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00066c49, 0x00000000, 0x377af3dc, 0x7fffc01f, 0xfd976db6, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x0152375f, 0xfffc3cdd, 0x05977fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000002, 0x80000000, 0x071bb8e4, 0xc0070000, 0x8000e38e, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xfffffffb, 0x9491ad9b, 0xfffffffb, 0x9491ad9b, 0xe0010000, 0xe0010000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xfffffe04, 0x00000000, 0x078a7e04, 0xf0ac003f, 0x80008000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffd7c53c, 0x5cd959a6, 0xffd7c53c, 0x5a0cf1f3, 0xfff97fff, 0xfa66eb0b, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf00398e9, 0xe00700e2, 0xfff87fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfffffc02, 0x03fe0000, 0x0000ffff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0x9428d7af, 0x7fff9999, 0x7fff007f, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x66666666, 0x66666666, 0x66666666, 0x60058ba6, 0x0004e66b, 0x3fc08000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x000a003a, 0x00000000, 0x3fe8c312, 0xffa87fc0, 0x7fff0227, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xffff84fb, 0xffffffff, 0xfffc48e3, 0x80060f0f, 0xfffc0006, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x079a525f, 0xf0caffff, 0x7fff8003, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00007ffc, 0x7ffc3fe0, 0x00000001, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x0003000e, 0x5fa455fd, 0x0003000e, 0x200724bd, 0x03148000, 0x7fff1ff0, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x002a020e, 0x00000000, 0x1272dd7c, 0x80007fff, 0x24920000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x1fffffff, 0xfffffffc, 0x20000000, 0x00000ff8, 0xfffc0000, 0xccccfc01, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfffc43b1, 0x0000c03f, 0x000f1c71, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfb0e8930, 0xf62c008e, 0xf2567ffd, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00001534, 0xe6fbfbaf, 0x00001534, 0xe8421aad, 0xe38efffe, 0x0000f489, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x10d7ffff, 0x80008000, 0x0000de50, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffffeec6, 0x000a0000, 0x0000fe47, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xfa24204c, 0x272c952e, 0xfa24204c, 0x2824f0a3, 0x8000ffef, 0xb6dbfe19, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x202eb020, 0x807f7fff, 0x7fff3fe0, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000fffc, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x000d0000, 0x000d0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xfffffffc, 0xe50728f9, 0xfffffffd, 0x49912909, 0x7ff0b6db, 0x80007fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfff95548, 0x7ff0000f, 0x8e380000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0xff00c7f5, 0xfc017fff, 0x00013ffe, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xe0100000, 0x7fff8000, 0x3fe00000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x0000000a, 0xd15c588b, 0x0000000a, 0xd15c588b, 0x0000ff00, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffc813c6, 0xc149c5e6, 0xffc813c7, 0x0149c5e6, 0x80000000, 0xe0078000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x05084908, 0x00017ff8, 0x0a129999, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xf0000000, 0x00000007, 0xf0000000, 0x00000007, 0xffe50000, 0xff270000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xf0000000, 0x00000001, 0xf0000000, 0x08848001, 0x8000edc8, 0x8000012f, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000074, 0x1b0038de, 0x00000074, 0x1b36b871, 0x7fffff94, 0x0000006d, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xf0000000, 0x00000001, 0xefffffff, 0xffff2c61, 0xfff00000, 0x7fff0d3a, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfff91c64, 0xf803003e, 0xe38e0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xfe125772, 0x6b08c6aa, 0xfe125772, 0x6b095ed4, 0x00020006, 0xeeb27fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x1ff88000, 0x00008000, 0xc00ffffd, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffff0000, 0xffff0000, 0xffff0000, 0xf5667ffa, 0x7fff8000, 0x15370006, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf0009fff, 0x00007fff, 0xe0018003, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x0001ffbf, 0x00027ff0, 0x00027ff0, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000229, 0xfffdfff8, 0x0113fc6a, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x0016ab99, 0x4543824b, 0x0016ab99, 0x254b823b, 0x00018000, 0x3ff0fff0, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xe0000000, 0x00000007, 0xdfffffff, 0xfb81bbc9, 0xe01f8000, 0x07fe03fe, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0ffc0000, 0x0ffc0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000006, 0x00000000, 0x00000004, 0xffff0001, 0xffff0001, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xe0000000, 0x0000000f, 0xe0000000, 0x0000000f, 0x00000000, 0x8000803f, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x1fffffff, 0xfffffff8, 0x20000000, 0x00017ff5, 0x7fff0000, 0x00000003, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x1ff67e85, 0x807f3ff0, 0x7ff0fffb, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00007fff, 0x00007fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xfc000000, 0x00000001, 0xfc000000, 0x00000001, 0x000c0000, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xfffffffe, 0x7fffffff, 0xfffa5b77, 0x24927fff, 0xfffbffea, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xffd3e3a7, 0xffffffff, 0xffe36388, 0x001f0000, 0xf0037fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfd0a0000, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xfe687fe0, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xbfc7d4e3, 0x7fffc71c, 0x00ff8000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xfffffff9, 0x7fffffff, 0x8002fff5, 0x80048000, 0x7fff7fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x30039ff8, 0x8000e007, 0x7fff8000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x00077ff0, 0x7fff000f, 0x7fff0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x0148886e, 0xffc07fff, 0x0291ffd4, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x0007ffe0, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xc0000000, 0x00000003, 0xbfffffff, 0xffc82eab, 0xf801000c, 0xeb5106dc, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffffffc8, 0xffc80000, 0x00000001, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x0000003f, 0x00000000, 0x0000003f, 0xfdfffffe, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xf0000000, 0x00000003, 0xefffffff, 0xff43804b, 0x0179ffee, 0xfffc8000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xfe8ad804, 0xffffffff, 0xfe8adde2, 0x02ef0000, 0x7fff0002, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00febe, 0xfffdfff7, 0x00050007, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffc0, 0x7fffffff, 0xc04d7f26, 0x7fff8000, 0x7fff009a, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x92492492, 0x49249249, 0x92492492, 0x49249249, 0xe7848006, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xb6db6db6, 0xdb6db6db, 0xb6db6db6, 0xdb41b6db, 0x80000059, 0x8000ffff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xfffffff8, 0x43399daf, 0xfffffff8, 0x42529daf, 0x00008000, 0x01ce0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xfc4d31dc, 0xffffffff, 0xfc4d31dc, 0x7fff07fc, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x000a806d, 0x80038007, 0x002bffc0, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf8782d2f, 0x0000f0f0, 0x7ffd0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfff40000, 0x00008000, 0x0018ffff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x1fffffff, 0xfffffff8, 0x20000000, 0x004b843b, 0x00970002, 0x026d7fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000004, 0x68c0a988, 0x00000004, 0xb8b82989, 0x80007fff, 0x7fffe00f, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffeb, 0x78c2edb5, 0xffffffeb, 0x78b6b66e, 0x0000057f, 0xfdc77fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xfff0eef5, 0x51889b89, 0xfff0eef5, 0x51889b89, 0x9249c03f, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xf84ab6fc, 0xc09e0f91, 0xc09e0f91, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000004, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x0000006e, 0xffffffff, 0xbfd880be, 0xffb07fff, 0x80007fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x40000000, 0x80000000, 0x00c28000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000187, 0x00000000, 0x00000187, 0x6db63fe0, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x3425d915, 0x16035ef6, 0x3425d915, 0x15836ef6, 0xff807ff0, 0xff807ff0, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000007, 0x00000000, 0x00000007, 0x155a0000, 0x7fff0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x09d149d4, 0x7ffa3fe0, 0x000313a2, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00001b20, 0x00207fff, 0x000000d9, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00008000, 0x00007ff0, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x33333333, 0x33333333, 0x33333333, 0x33333397, 0xffcc0005, 0x00140000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x0fffffff, 0xfffffff8, 0x0fffffff, 0xffec09f8, 0x7fc00003, 0x0000ffd8, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x000106ed, 0x03147fff, 0xffff007f, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x000f7e5b, 0xffffffff, 0xbf12f5dc, 0xe01f8003, 0x7fff07fc, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffffe7dc, 0x0024fff0, 0xfff4ff4f, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x0000007f, 0x00000000, 0x003d3375, 0x00000099, 0x66660000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x000085a0, 0x00000000, 0x000085a0, 0x0000ff91, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000004, 0x00000000, 0x0475c622, 0x800001de, 0xffe1f714, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xfffffe4d, 0xae92c158, 0xfffffe4d, 0xcaf3c158, 0x7ff08000, 0xc73e0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xc0000000, 0x0000000f, 0xbfffffff, 0xfffe7ff3, 0x0007fffc, 0x80078000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffbb1d, 0x43b25b1f, 0xffffbb1d, 0x43b25b1f, 0x00000000, 0xcccce01f, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xe023feff, 0x80008004, 0xffc03ff8, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x1c71c71c, 0x71c71c71, 0x1c71c71c, 0x71c71c71, 0xffe50087, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xe0000000, 0x0000000f, 0xdfffffff, 0xfffff3c7, 0x020cfffd, 0x020cfffd, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xfffffffc, 0x7fffffff, 0xfffffffc, 0x00000000, 0xfb1ef803, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00001313, 0xa71010dc, 0x00001313, 0xa6e69284, 0x7ffffeab, 0x8000fe58, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00020017, 0xfff8ffff, 0xffd1c003, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xffffffc0, 0xffffffff, 0xffffffd0, 0xfffe8006, 0x0000fff8, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x005ac344, 0x00000000, 0x005ac6bf, 0xfed7fff8, 0x0000fffd, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x18931984, 0x9e5fb4f4, 0x18931984, 0x9e5fb4f4, 0x000008e3, 0x000008e3, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x0006aab7, 0xc71c0000, 0x01beffe2, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xf8e2fc4a, 0xccbc94c7, 0xf8e2fc4a, 0xcbfa964b, 0xfe7cff9a, 0x00007fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000ea5, 0xffffffff, 0xfe7150b5, 0x7ff87fc0, 0xfcfbffe6, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x0006b784, 0xffffffff, 0xffa3b698, 0x7fff01b2, 0x800000ec, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xfffffffd, 0xffffffff, 0xe02fba8b, 0x807f000f, 0x00b23fe0, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xfffffffc, 0x00000000, 0x0007c39a, 0xffa50007, 0x7ffff401, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xfffffffd, 0x80000000, 0x00187f9b, 0x7fff8002, 0xffcf0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xffffffff, 0xfffffffa, 0xffffffff, 0xffff01c4, 0xfffe0002, 0x00e47fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffd5af3, 0x7fffdb6d, 0x007f001f, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffff, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0xfffffff8, 0x00017fff, 0x00000000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfd8ea1cf, 0x00ff0801, 0xc0078e38, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x04078000, 0x80008000, 0xf7f10000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000007, 0x7fffffff, 0xfffb0011, 0xfffb7fff, 0xfffb7fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1c61c73c, 0x7fffffe0, 0x7fff0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x8e38e38e, 0x38e38e38, 0x8e38e38d, 0xf903a2d8, 0x7fc00a50, 0x00028000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x1fffffff, 0xfffffff8, 0x1fffffff, 0xdb6f36d6, 0x042db6db, 0x7ffa0000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xe6663334, 0xccccf371, 0x00007fff, 0x0, 0x0 + dspck_astio dpax.w.ph, 0xfffffffb, 0x69d2cb92, 0xfffffffb, 0x6e6ed51c, 0xffffefde, 0xb6dbfd60, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x80000000, 0x0000000f, 0x80000000, 0x3ff6000f, 0x80008000, 0x00148000, 0x0, 0x0 + dspck_astio dpax.w.ph, 0x0fffffff, 0xfffffffe, 0x10000000, 0x4000002e, 0x8000fffa, 0xfff88000, 0x0, 0x0 + + writemsg "[48] Test dpsx.w.ph" + dspck_astio dpsx.w.ph, 0x00000000, 0x00002f6a, 0x00000000, 0x03c83547, 0x92491ff8, 0x000108d3, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xffd31d0f, 0x3fe0ffc7, 0x168700c8, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xc0000000, 0x00000001, 0xbfffffff, 0xc0010000, 0x7fff7fff, 0x00007fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x0000036b, 0x077a03a6, 0x0000036a, 0xc77a03a6, 0x00008000, 0x80007fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00952fec, 0xffffffff, 0xf8b934e7, 0x01c91f5a, 0x38e37fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf1776268, 0xe38ef009, 0xfafe8003, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffff3, 0xffffffff, 0xc0ddf436, 0x7fff01ab, 0x80077ff0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x000b4598, 0x7860d4a7, 0x000b4598, 0x786454a7, 0xffe40007, 0x80000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x0000920f, 0xffffffff, 0xffcf059c, 0x7fff00d1, 0x0ffc0049, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffa4b7b3, 0xffb7f803, 0xf0017fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfc010015, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000002, 0x00000000, 0x00000002, 0x00000000, 0x8000ffd2, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffff873, 0x03c6ffff, 0x00000002, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xe9e8a7d3, 0xffffffff, 0xe9d3297b, 0x7fff3fc0, 0x00060028, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffffb, 0xffffffff, 0xffec0023, 0x7fff0000, 0x00000028, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x002e0000, 0x0000005c, 0x8000e003, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00003d56, 0xd2c15fd1, 0x00003d56, 0xd2c15fd1, 0xfff88000, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xfc000000, 0x00000001, 0xfc000000, 0x00000001, 0x00000000, 0x7fff7fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffff0000, 0xffff0000, 0xffff0000, 0xfffe012a, 0xfed80002, 0x7fff0001, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x3fff8000, 0x002d7fff, 0x80000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xe0000000, 0x00000007, 0xe0000000, 0x3ffe883d, 0x7fff020d, 0xfffc8002, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffff803f, 0x00007fc0, 0x0001fff3, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00037fe4, 0x00007ffc, 0xfff90000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffef0fe, 0x8000fc7b, 0xffb30000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x1fffffff, 0xfffffffe, 0x1fffffff, 0xfffffffe, 0x7fff8000, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xfb365ad0, 0x1ed0b6db, 0x0000aaaa, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffff70ee, 0x0f042e88, 0xffff70ee, 0x0f092e7e, 0x7ffffffb, 0x7ffffffb, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffc0, 0x7fffffff, 0xe666b29f, 0x00077fff, 0x3333000c, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000001, 0x00000000, 0x0003fc01, 0x0000fff8, 0x7f808003, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000fff8, 0x00002492, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x04fd00ff, 0x800003fe, 0x800003fe, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0018b892, 0xff95053b, 0xfb770000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x033172c2, 0x00000000, 0x03358aa2, 0x05fa8001, 0x0008fffc, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x0fffffff, 0xfffffff8, 0x10000000, 0x0000624a, 0x01b3f9ac, 0x000ffffe, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf0038000, 0x7fffe007, 0x80000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x0000007f, 0x80000000, 0x00817f7f, 0xff008000, 0x00037fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x0029da05, 0x03feffec, 0x7f80f803, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000076, 0x22a330e7, 0x00000076, 0x22a03147, 0x0006c001, 0x00007ff0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x08223fc0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x33333333, 0x33333333, 0x33333333, 0x498db953, 0x0c3138e3, 0x80007fe0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffff7, 0xffffffff, 0xfffffff7, 0x00000000, 0xf8010ffc, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000fd1, 0x941a16c2, 0x00000fd1, 0x941a16c2, 0x80000000, 0xfffc0000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x0000003f, 0xffffffff, 0xbf7b003f, 0x80008000, 0xfef68000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000006, 0x00000000, 0x00000006, 0x0001fa45, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xf9f06eaf, 0xffffffff, 0xf9e80851, 0x7ffe6666, 0x00150000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000736, 0x00000000, 0x012c9e61, 0x0259fffe, 0x0f1b8003, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00000000, 0x7ffffe10, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf2bfe482, 0xd6c300fe, 0x8000aaaa, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xdb6db6db, 0x6db6db6d, 0xdb6db6db, 0x6db7db6b, 0xc00ffffe, 0x7fff0000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x0000000a, 0xffffffff, 0xfffa0016, 0x8000000c, 0x7fff0000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffce0064, 0x00000064, 0x7fffc00f, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xff043c0e, 0xffffffff, 0xff5c6eec, 0x0006fe56, 0x33338000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xfffffff0, 0x00000000, 0x0001fffe, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xffff80d4, 0xffffffff, 0xffff80d4, 0x00000000, 0xfffa8000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x18c86851, 0x7ffff30f, 0x0002ce6f, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000024, 0x8f22c155, 0x00000024, 0x8f21c155, 0x80000001, 0x8000fffd, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xfff4005d, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffcd479d, 0x00f47fff, 0xfff938e3, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x0281bf68, 0x0000ebed, 0x1ff8fff9, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000001, 0x7fffffff, 0xffff3333, 0x9999f0f0, 0x0000fffe, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xff6b010f, 0xd0cd0002, 0x02fcfcd8, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x0000001f, 0x80000000, 0x007ff8ef, 0x078dff00, 0x7f80fff0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xe0000000, 0x00000003, 0xdfffffff, 0xfffffffc, 0x00010000, 0x3ffc0007, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfe0103fe, 0x7fff0000, 0x7fff03fe, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffff9, 0xffffffff, 0xfce5253d, 0x00000636, 0x7ffa5555, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000128, 0xffffffff, 0xcccfcdf2, 0x00007ff9, 0x6666ffc0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00e5fe34, 0xff1a7fff, 0xff1a7fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x07ffffff, 0xfffffffe, 0x08000000, 0x0000112c, 0x05ba0000, 0x7ffffffd, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffff2a0f, 0x00d40001, 0x02c500ff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfd1d0b8c, 0xf4740000, 0xe694c001, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x0a6f6607, 0x1efa9e25, 0x0a6f6607, 0x1efb7418, 0x2a01fffe, 0x7ffa0001, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffff7fff, 0xffff0000, 0xffff8000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffffd, 0xffffffff, 0xbffff7bd, 0xfd408000, 0x8000fffd, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x38e3dff4, 0x8000fffd, 0x1ffc71c7, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffff7043, 0xbf88adca, 0xffff7043, 0xbf88adca, 0x8000012f, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000003, 0x00000000, 0x00276083, 0xfa20ffff, 0xff0006b4, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x1812b202, 0x0c346666, 0xc0011ffe, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x800f0004, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x07e413dd, 0x00000000, 0x07e313df, 0x00007fff, 0x00028000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xe0000000, 0x0000000f, 0xdfffffff, 0xf007000f, 0x8000ffef, 0x8000e01f, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xff350b1a, 0xff358007, 0xff358007, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xf0000000, 0x00000001, 0xf0000000, 0x00000001, 0xfe2e0000, 0xfffe0000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffffe, 0x00000000, 0x07363aba, 0xe00f8005, 0x0f0ffd77, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1ff8e007, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xe0037fff, 0x800007fe, 0x0000c007, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00014485, 0xffffffff, 0xfd6f4a89, 0xfff97fff, 0x05240020, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00003ffc, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000014, 0x00000000, 0x001a7294, 0xff288000, 0xffff1ff0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x000005d6, 0xf4ab40d9, 0x000005d6, 0xf4cea0d2, 0xff007fff, 0xfff91fe0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf004fff9, 0x7fff8000, 0xe003fff9, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffaa, 0x29390e59, 0xffffffaa, 0x28b847a8, 0x000fff00, 0x80000d3f, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xf7c80000, 0x80000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x0003b7d7, 0x00000000, 0x10009807, 0x801ffff9, 0x3ffe1ffe, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07fe8006, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000004, 0xffffffff, 0xfa9ca1f8, 0xf8161954, 0x0e778000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfff96dca, 0xffffffff, 0xf801cda9, 0xc001c001, 0xe01f0002, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xfffffffc, 0x80000000, 0x07fea008, 0x1ffc0000, 0x0047c003, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xe38e47f4, 0x80010001, 0xf0f0c71c, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x0dcc0000, 0x00090000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000001, 0xffffffff, 0xe008373f, 0x00073ff0, 0x7fff013e, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xf0000000, 0x00000001, 0xf0000000, 0x00000001, 0x71c7fff4, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x00003ffd, 0xe001fffd, 0x00000002, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xf11dfd4f, 0xffffffff, 0xf0128589, 0x2492ffe0, 0x5555079b, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xd5d529aa, 0xff005555, 0x80007fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xfffe5659, 0xa74f6473, 0xfffe5659, 0xa94d6cef, 0x800507fc, 0xc01f0000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000007, 0x51b5bd6c, 0x00000007, 0x55b03d6c, 0x80000000, 0x000107f5, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x0000001f, 0x80000000, 0x0fee820f, 0x7fffe01f, 0x7ff00000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00007ffa, 0x0000fe64, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x07ffffff, 0xfffffffc, 0x07ffffff, 0xe666e662, 0x7ffe1ffe, 0x00003333, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xffffef5a, 0xffffffff, 0xbffdc558, 0xff127fff, 0x7ff8f8d5, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x132bd9a8, 0x80010000, 0x7fff2658, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x0000ec51, 0xffffffff, 0xe1e2f3d1, 0xc001f0f0, 0x1ff88000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x0fffffff, 0xfffffff8, 0x0fffffff, 0xfffce318, 0xfffd1fe0, 0x00190000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000003, 0x7fffffff, 0xfffe107f, 0x00000ffc, 0x001ffc4b, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x02a294cc, 0x3ffcffe8, 0xfff5f575, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0xbf02ff03, 0x80007fff, 0x00038007, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xe0000000, 0x00000007, 0xdfffffff, 0xfffb802a, 0xfff98000, 0xfff70005, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x0000007f, 0x80000000, 0x26ac5078, 0x8000f007, 0xc0015555, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffe6b82d, 0xec14ffff, 0x6666feb6, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x3fffffff, 0xfffffff0, 0x40000000, 0x000005f0, 0xfffa0006, 0xff000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffff8, 0x00000000, 0x02017f2c, 0x03d03ffe, 0xff9a8000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffec00c8, 0x00008005, 0xffd800ff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffffcf6, 0xfff93581, 0x0000ff91, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xffffffe8, 0xffffffff, 0xbb9f0449, 0x55557fff, 0x7fff0d26, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00bb4976, 0xfe9efeb6, 0x07fc7fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xff0037fd, 0x0000f801, 0xe003ff00, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000003, 0x7fffffff, 0xc0030004, 0x00078000, 0x80009249, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfffa8000, 0x00008000, 0xfff50000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xffbf07f5, 0xffffffff, 0xffbc07db, 0x7fffffe0, 0x8000ffe6, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xff92db59, 0xe0f2153f, 0xff92db59, 0xa0f1fe47, 0x8000008c, 0x002a8000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x0000003f, 0x7fffffff, 0xccd2af81, 0x00ee8000, 0x9999f959, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x07ff0000, 0x00000ffe, 0x80008005, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x0037dc2c, 0x00000000, 0x4ff6dcab, 0x7fff8000, 0x1ffe807f, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x3fe0003e, 0x7fff4924, 0x0000803f, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xb6db0000, 0xe0070000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffd8, 0xa5e1ab49, 0xffffffd8, 0xe5e12b49, 0xc0018000, 0x7fff0000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffb58e5d, 0x7ffa01d0, 0x80000265, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x07ffffff, 0xfffffffe, 0x07ffffff, 0xc001fffb, 0x7ffd7fff, 0x00007fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x00008bfe, 0xfffc0039, 0xffc91ff0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x000000c5, 0xffdfff60, 0x00000006, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffc0, 0x7fffffff, 0xffffffc0, 0xff6be01f, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x018d0143, 0xb9740aeb, 0x018d0143, 0xb92e55b3, 0x1f1800ee, 0x3fe00055, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffc0, 0x7fffffff, 0xf43f91ad, 0x7ffffffa, 0xff121781, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000048, 0x00000f0f, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x0001397d, 0x8018a206, 0x0001397d, 0x7200903b, 0x7ffb3fc0, 0xff801c71, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfff48000, 0x0f088000, 0xffe90000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x0000008d, 0xffc0ffff, 0x01cdfffb, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfffb85ad, 0x0003b6db, 0xfff0f801, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xfffff0e5, 0xdeafdd22, 0xfffff0e5, 0xdebb4c1d, 0x00ff00b7, 0xf007fffc, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffcd5, 0xffffffff, 0xfff8fce3, 0x0000000e, 0x7ffffe35, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000344, 0xc75e94f9, 0x00000344, 0xcf5a6511, 0x00000ff8, 0x8003ff08, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffecccd, 0xedc66666, 0x00030000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x01f1d0d3, 0x00000000, 0x01f1d0d3, 0x000c7fff, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xb6db6db6, 0xdb6db6db, 0xb6db6db6, 0xdb662863, 0xe38efff4, 0xfffcffbc, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x24924924, 0x92492492, 0x24924924, 0x924c2290, 0x80000006, 0xd5ab0004, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xf1ca0491, 0x71c7ffed, 0xf7131ff8, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x0000003e, 0x57f1e1af, 0x0000003e, 0x3d3ff722, 0x7fff7ffe, 0xe00f5555, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x07ffffff, 0xfffffffe, 0x08000000, 0x00037fe9, 0x00000007, 0x80037ffc, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x0000003f, 0x80000000, 0x1000c040, 0xe003c001, 0x7fff8000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xffffa0a8, 0x00000000, 0x00058408, 0x000cf1b0, 0xfffe8000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x55558000, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x8e38e38e, 0x38e38e38, 0x8e38e38e, 0x78a38e38, 0x7f800000, 0x1ffe8000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x0bd37f9c, 0x1743ff9c, 0x7fff8000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xf0000000, 0x00000007, 0xf0000000, 0x002dffab, 0x2492fffa, 0x0000febe, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x0000000f, 0x7fffffff, 0xe0008011, 0xc0030002, 0x7fff8000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xffa00000, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x1fffffff, 0xfffffffe, 0x1fffffff, 0xfffffffe, 0x00000000, 0x00010025, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xdb6db6db, 0x6db6db6d, 0xdb6db6db, 0x6e0f8563, 0x1c717fff, 0xff50fffa, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000e6c, 0x2cf185fa, 0x00000e6b, 0xf9be193c, 0x00059999, 0x8000fc26, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000001, 0x00000000, 0x00000e15, 0x0385e003, 0x0000fffc, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x0000008d, 0x00050001, 0x0004ffe3, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x2007d466, 0xffa3c007, 0x7fff1fe0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfc04feee, 0x00113fc0, 0x0ffc0001, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x3a19a389, 0x00000000, 0x3a21f266, 0x1ffcf007, 0x0005ffc0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffff7f, 0xb24c0ece, 0xffffff7f, 0xb24c0ece, 0x3ff0ffff, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xffe96e44, 0xffffffff, 0xfbe92ea4, 0x1ff08000, 0xf8010006, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffe87, 0xffffffff, 0xd00b7e87, 0x80001ff8, 0x8000801f, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x0fffffff, 0xfffffff8, 0x10000000, 0x1c71c714, 0x003dc71c, 0x7fff0000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x0069a7ce, 0x1c71fff0, 0x8004fc01, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00338000, 0x0067ffff, 0x00008000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffffc, 0x00000000, 0x006901e6, 0xfffefcba, 0x1fe05555, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xfffffffd, 0x00000000, 0x006adb6d, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000102, 0xffffffff, 0xf8dfbebb, 0x7fff07fe, 0xf3570f0b, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf000ffff, 0x0001e001, 0x80008000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffff7fd, 0xffffffff, 0xfffff7fd, 0x00000000, 0x00000623, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x03726678, 0x379f21d3, 0x03726678, 0x379f21d3, 0x00008000, 0x00007fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffff0000, 0xffff0000, 0xffff0000, 0xfffe8000, 0x00008000, 0xfffffff0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xeffd0000, 0x8000fff9, 0x8000e001, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x03329667, 0x00003333, 0xf0038002, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x000f1a6a, 0xc2980006, 0x005d003f, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x8e38e38e, 0x38e38e38, 0x8e38e38e, 0x38e2e692, 0x0000c81e, 0xfffde57d, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x0f0ffffc, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xc000f729, 0x800202f2, 0x00038000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffff0, 0xffffffff, 0xff577ea0, 0xfffffe08, 0xaaaa8000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x99999999, 0x99999999, 0x99999999, 0x99999999, 0x49240000, 0xe1d50000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffff12, 0x1b257b7a, 0xffffff12, 0x1b35fb5a, 0xffe08000, 0x00017fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xfffff8d0, 0x68ef9c7c, 0xfffff8d0, 0x68ef9c7c, 0x80000000, 0x80000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xfffffffb, 0x469d3791, 0xfffffffb, 0x4356b7e2, 0x3fe00e07, 0x3bb90003, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000252, 0x0000fffa, 0x0063ff80, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x33333333, 0x33333333, 0x33333333, 0x4cd2b327, 0x80007fff, 0xfff43333, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x99999999, 0x99999999, 0x99999999, 0xd97f9819, 0x3ff07fc0, 0x8000ffe8, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xd2e75f8b, 0xffffffff, 0xefb033d6, 0x39cb0000, 0x0079807f, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xff1f0000, 0x00038000, 0xfe3e0000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000002, 0x00000000, 0x0056f258, 0x00020185, 0xc71cc00f, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffc92498, 0xfff8ff80, 0x92490003, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffffb, 0xffffffff, 0xf80478ac, 0xff95f007, 0x80000253, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000007, 0xffffffff, 0xf0150007, 0x00008000, 0xe02a0194, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x0000006d, 0x3fa9cd30, 0x0000006d, 0x3fadf504, 0xfff10048, 0xfe8e3ffc, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000001, 0x7fffffff, 0xfffe0001, 0x8000fffe, 0x8000fffe, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x0ac9c25a, 0x00000000, 0x0acdfa0d, 0xfb490000, 0x001b00e5, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffff65, 0xd48b4c13, 0xffffff65, 0xd0d74c04, 0xf8897fff, 0xfff18000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x7ffffffd, 0x7fff0003, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xffffffe0, 0xffffffff, 0xfd7e67fc, 0x0000f001, 0xd7e4fffa, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x0000000a, 0xffffffff, 0xffccc1b4, 0xfff83ffe, 0x00cd0002, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf51683fe, 0xaaaa3ffc, 0x00ffe003, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x07fdffff, 0x0ffc0000, 0xfffd8000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf8055f45, 0xc01ff003, 0xc01ff003, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffe9c56, 0xffffffff, 0xfffe9c56, 0x80000000, 0xf8010000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xff1a3358, 0x0f56f008, 0x00000efc, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x92492492, 0x49249249, 0x92492492, 0x334074ed, 0xdca67fff, 0x3ffc4924, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x0000007f, 0x7fffffff, 0xfff1c0f8, 0xe0010007, 0xc001ff80, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xfffe945c, 0xb2ef1065, 0xfffe945c, 0xb2ef13e5, 0xfc01ff80, 0x00070000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x33333333, 0x33333333, 0x33333333, 0x33346b4b, 0xfffbfff8, 0xff2b3fc0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xfff85a2d, 0x00e23275, 0xfff85a2d, 0x00e23275, 0xe001002e, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xc0004017, 0x3ff87fff, 0x7fff0003, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xfffffffe, 0xb0add741, 0xfffffffe, 0xa54325fb, 0x0eda07fc, 0x7ff87fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffdb, 0xfcbd2611, 0xffffffdb, 0xc98a7e58, 0x7ffffffb, 0xfd2d6666, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00007e92, 0xfff50001, 0x8003ffdf, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000006, 0xffffffff, 0xff800506, 0xf8038005, 0xff000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fff3fe0, 0x00000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xc000fffe, 0x7fff0000, 0x00057fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x01df0e8b, 0xff807fff, 0xfc8b4924, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xfff8aae2, 0x83eb47c3, 0xfff8aae2, 0x806ea5f2, 0xf903e01f, 0x000f8000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x0011373f, 0xffbc3fc0, 0xffff3fe0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffffd, 0xffffffff, 0xffff7e6e, 0xffff0051, 0x00058006, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf8eea9b8, 0xf0013352, 0x00077ffa, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffff, 0xffffffff, 0xffffffff, 0xf99c800b, 0xcccc0000, 0xc01fe00f, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x000000ff, 0x00000000, 0x7fc000ff, 0x80007fc0, 0x80007fc0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffff39ba, 0xe003001b, 0x03cafffd, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00fe65fc, 0x4cf3252d, 0x00fe65fc, 0x6cd36576, 0xc03f000a, 0xffff7fff, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xc0000000, 0x80008000, 0x80000000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffff9dad, 0x9b20bcbf, 0xffff9dad, 0xb4b21653, 0x3ff00004, 0x7fff9999, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x000844f6, 0xffc07fff, 0xfff60d14, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffcd70, 0x878ab614, 0xffffcd70, 0xc78cb614, 0x00057fff, 0x80008000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xfffff607, 0x4e30d872, 0xfffff607, 0x4e301834, 0x00ff7fff, 0x0002ffc0, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xffffffbd, 0xc6f0c624, 0xffffffbd, 0xc6ef49a4, 0x00070004, 0x80007f80, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x12380004, 0x1c713ffc, 0xf0018000, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0xfe986b7c, 0xe5856df2, 0xfe986b7c, 0xe18775ee, 0x000007fc, 0x7fff0001, 0x0, 0x0 + dspck_astio dpsx.w.ph, 0x00000000, 0x00000001, 0x00000000, 0x3ffffffd, 0x7ffffffe, 0x3ffe8000, 0x0, 0x0 + + writemsg "[49] Test dpaqx_s.w.ph" + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x05946d31, 0xdb6d8000, 0xfa51005d, 0x00000000, 0x00000000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0xffff2cd6, 0xf91307af, 0xffff2cd6, 0xf8d4c631, 0x8000007f, 0xc03fffff, 0x00000000, 0x00000000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x6db6db6d, 0xb6db6db6, 0x6db6db6d, 0x5f1df8de, 0xdb6d7fff, 0xcccc7fe0, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x7fbc03bf, 0x7ff8ffc5, 0x7ff87fff, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xffffffe8, 0xfffcff1f, 0x00000003, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xffef9dc8, 0xf995fd15, 0x010300d1, 0x00000000, 0x00000000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x24924924, 0x92492492, 0x24924924, 0x92502496, 0x7ffefff8, 0x8000ffff, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xe0000000, 0x00000001, 0xe0000000, 0x000059b9, 0xfff4e00f, 0x0000fc43, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff30fea0, 0x00300000, 0x7fff7fff, 0x00000000, 0x00000000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00994ab2, 0xfe260517, 0x0f0f0000, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x07ffffff, 0xfffffffc, 0x07ffffff, 0xffb4fffc, 0x0007004b, 0x80000000, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf2db9dbb, 0x00007ffa, 0xf2dbfffd, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x6db6db6d, 0xb6db6db6, 0x6db6db6d, 0xb6db6db6, 0x00000000, 0x000f8001, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x7ffe0011, 0x7ffffffe, 0xfffc7fff, 0x00000000, 0x00000000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xfff60014, 0x00007fff, 0xfff60004, 0x00000000, 0x00000000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x8064ff35, 0x00658000, 0x80007fff, 0x00000000, 0x00020000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0xfe5f10c3, 0xe760a390, 0xfe5f10c3, 0xeb23d032, 0xde5f7fff, 0x03bffff0, 0x00020000, 0x00020000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xfffffffe, 0x00000000, 0x6465fffe, 0x80008000, 0xaaaaf0f0, 0x00020000, 0x00020000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x0b951e8a, 0x00db3fe0, 0x157f7fff, 0x00030000, 0x00030000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x36db9249, 0x80007fff, 0xb6db8000, 0x00020000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xff147f80, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4924c71c, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x04684d7d, 0x07fe7fff, 0x0377ff25, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xffd90040, 0x7fff8000, 0x0007ffe0, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x000000cf, 0x9a5c8bed, 0x000000cf, 0x7f3b824f, 0x1ff0003f, 0x7fff9249, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0fffffff, 0xfffffffe, 0x10000000, 0x0001ffbe, 0x00100000, 0xfff80ffe, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x552bffe7, 0xfffdaaaa, 0x803ffff6, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffa300b9, 0x7fff8001, 0x0000ffa3, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xfffa000c, 0x00006db6, 0xfff90000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000004, 0x00000000, 0x003f4342, 0xffffff04, 0xe003db6d, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x0fffffff, 0xfffffff8, 0x10000000, 0x7ffee4c6, 0x80010001, 0xf2678000, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x6304bc88, 0x00000000, 0x62f35b60, 0x8000f007, 0x0234ffcb, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xffffffe8, 0xffffffff, 0xdb75dd20, 0x7fe00006, 0xfa0adb6d, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x000f1c9c, 0xffe0ffda, 0x38e38000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000003, 0xffffffff, 0xa5fadb71, 0x80009249, 0x7fffec4f, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x0000000f, 0xffffffff, 0xfffff905, 0x00000035, 0xffef7fff, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x3fffffff, 0xffffffe0, 0x3fffffff, 0xfffdffe0, 0x01ac0002, 0x80000000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xedb82494, 0x80006db6, 0x7fff7ffd, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xffffffff, 0xfffffffb, 0x00000000, 0x0007fffb, 0x0000fff8, 0x80007fff, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0xfffffff8, 0x7fff8000, 0x00000000, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xfc000000, 0x00000001, 0xfc000000, 0x3ff10001, 0x00008000, 0xc00f0005, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xff2a4acf, 0xde8c3ffc, 0x24924924, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x0001ffec, 0x0002fffc, 0x00007ffb, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x000002aa, 0x00000000, 0x000401aa, 0xfffffc01, 0xff800000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x80000000, 0x00000002, 0x80000000, 0x000205b4, 0x0000cc3b, 0xfffb0000, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000047, 0x1ff00024, 0x00010000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x0012900a, 0x0e63ded6, 0x0012900a, 0x0e61ded6, 0x00000002, 0x8000001c, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xfff9b250, 0xff80fe1b, 0xfff8066c, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x33333333, 0x33333333, 0x33333332, 0xb3353237, 0x7fffc03f, 0xfffe8000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x0000000f, 0x00007fff, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xf8000000, 0x00000001, 0xf7ffffff, 0x00210001, 0x7fe07fff, 0x80008000, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x38e30006, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000788, 0x9cf9f5fb, 0x00000788, 0x9cf9f5c3, 0x0000fffe, 0x000e8001, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0xf8000000, 0x00000001, 0xf8000000, 0x0046fd3f, 0x00300047, 0x7ff90003, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000e003, 0x00000000, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x801fffc1, 0x7fff0000, 0xcccc801f, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xfffffffe, 0x7fffffff, 0xf883ce44, 0x0ff8ff21, 0xb6dbc003, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xff3dec21, 0x0611807f, 0x0000f001, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xfffffff8, 0x7fffffff, 0xf7d91fde, 0x9249f803, 0x7ffe0031, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xffffff00, 0x00000000, 0x3ff0ff00, 0x00008000, 0xc00fc003, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xffe241e9, 0xffffffff, 0xffe56f15, 0x80000f0f, 0x000afffe, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xffffff88, 0x0000fffc, 0x000f0065, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000004, 0xffffffff, 0x7805bf8c, 0x7fffe00f, 0x1ffc8000, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xc0000000, 0x00000007, 0xbfffffff, 0x70cef337, 0x80007ff8, 0xf0cd7fff, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00000f80, 0xff08fffc, 0x0000fff8, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xffffffff, 0xfffffff7, 0xffffffff, 0xe78c30e3, 0xe78afffe, 0x80007fff, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x24924924, 0x92492492, 0x24924924, 0x1249e496, 0x8000ffff, 0x1ffe7fff, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0x80010000, 0xe0018000, 0x7fff0000, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x7f7e89b7, 0x7ffffea5, 0x002c7f80, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xe0011c71, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xfffffffa, 0x3271a679, 0xfffffff9, 0xb2aea679, 0x80008000, 0x00037fc0, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00084bde, 0xf8019999, 0xffffff88, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xffffff8e, 0xffffffff, 0xf0071f80, 0x056b7fff, 0xf0070000, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x7e333a5f, 0x0ffe7ffa, 0x8000f168, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000001, 0xffffffff, 0xfc41ff01, 0xff808000, 0x03fec001, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000018, 0xffffffff, 0xf6a49bf0, 0x8000fe99, 0xcccc09eb, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0xe0000000, 0x00000007, 0xe0000000, 0x000183b7, 0x00037fff, 0x000115f3, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0fffffff, 0xfffffffc, 0x0fffffff, 0xfffffffc, 0x0000fffd, 0x00000000, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x0000002f, 0xfffc8000, 0x0000fffa, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xffffff32, 0x00000000, 0x00016ed6, 0x00170000, 0xf8e007fe, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0x1585a691, 0xfffffffe, 0x95a72df3, 0x7ffff0f0, 0xfff3801f, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x1fffffff, 0xfffffffc, 0x20000000, 0x000000ac, 0x3ff00058, 0x00010000, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0xdcbc91a8, 0x8b369f8f, 0xdcbc91a8, 0x8b3edd7f, 0xfc010000, 0x2d2cfef8, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xfffa0000, 0x80007fff, 0x00000006, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00003f5b, 0x0f60cd1e, 0x00003f5b, 0x0f60cd1e, 0x00008000, 0x00008000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x000000ba, 0xfffeffe1, 0xfffd0000, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xffffffe0, 0xffffffff, 0xf007ffe0, 0x0ff80006, 0x00008000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000005, 0x00000000, 0x44840005, 0x8000e00f, 0x8000db6d, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000001, 0xd93ec0f4, 0x00000001, 0xd91fc0f4, 0x7ffe8000, 0x001f0000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xc0257fb6, 0x7fff7fff, 0x001ec007, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffb, 0x00000000, 0x0000fff7, 0x8002ff4e, 0x0000ffff, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x0fffffff, 0xfffffffe, 0x10000000, 0x7f69b805, 0x49248000, 0x8000fef9, 0x000a0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xffffffff, 0x4ecd37bf, 0xfffffffe, 0xdd5e386f, 0xff7c8000, 0x71c7aaaa, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x00b1bb1d, 0x07407fff, 0x00b1000d, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xeb1ac922, 0xb6db0005, 0x0fef2492, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xa75e1a0c, 0xfca5ff86, 0xf0f07ffd, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xc0000000, 0x0000000f, 0xc0000000, 0x2493020f, 0x8000fff8, 0xffe0db6d, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000007, 0xffffffff, 0xffe5ff3d, 0xffe57f80, 0x00017fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x1ffbc008, 0x00007fff, 0x1ffcffff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x09f1ffe0, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x0000007f, 0x00000000, 0x000333bf, 0xfff8e001, 0x0000cccc, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x3fffffff, 0xfffffffc, 0x3fffffff, 0xff6b3298, 0xfffffb59, 0x0ffe0000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x0000001f, 0x80000000, 0x3ffb8027, 0x00007fff, 0x3ffc0000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0x83558304, 0xffff6db6, 0x801f0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffbf0e92, 0xd352c2a3, 0xffbf0e92, 0xd34bc2b1, 0x7fff0000, 0x0000fff9, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0xd2690abc, 0x00000000, 0x526a2aba, 0x8000ffff, 0xf0017fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xff71ddae, 0x00000000, 0x32a47700, 0x8006ffff, 0x801fcccc, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x2c2db31a, 0x00000000, 0x1e8f2012, 0x8000e001, 0x367c0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xfffffff8, 0x167a2b30, 0xfffffff8, 0x167b47a4, 0xfffbf001, 0x0000e38e, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaa2, 0x00b60004, 0xffff0000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xfffffffb, 0xffffffff, 0x800ec6f5, 0x001f8000, 0x7fff38e3, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xfffbf808, 0xfffc0004, 0xff007fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffeca179, 0x9c0defe7, 0xffeca179, 0xa328844f, 0xfffd38e3, 0x0ffc00c0, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xfffffffa, 0x7fffffff, 0xfc00dfee, 0x0000e003, 0x0ffe0006, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0xfffffe6e, 0x201ba127, 0xfffffe6d, 0xa014a127, 0x7fff0008, 0x80008000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xfe4f6b2e, 0xb6db0000, 0x999902f5, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x0000007f, 0x00000000, 0x0ffee081, 0x7fff0ffe, 0x7fff0001, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffe, 0xffffffff, 0x8004fff6, 0xc0078004, 0x7fff0000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x0fffffff, 0xfffffff8, 0x10000000, 0x4924fff8, 0x7fc08000, 0xb6db0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x1863fffe, 0x92498003, 0x55558000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x000026ac, 0x00000006, 0x03398000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x1fffffff, 0xfffffffe, 0x20000000, 0x7ffe0120, 0x7ffffffc, 0xffdc7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0xffc07f80, 0x00008000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xf0000000, 0x00000001, 0xefffffff, 0xfff80011, 0x0000fff8, 0x7fff8000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x3fffffff, 0xfffffffc, 0x3fffffff, 0xfffffffc, 0x00000000, 0xfffeffe0, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000007, 0xffffffff, 0xffffffe7, 0x0000fff8, 0x000207a4, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xff7c0000, 0x00840000, 0x00698000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x0000007f, 0x80000000, 0x00000043, 0x031cfffa, 0x00050000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xf8704678, 0xffffffff, 0xf8704678, 0xf058800f, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x80000000, 0x0000007f, 0x7fffffff, 0xfff324df, 0xfffe0026, 0xdb6d7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x58313cef, 0x49241ffc, 0xfffb7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xfffffffc, 0x9321c3c0, 0xfffffffc, 0x92cbc46c, 0x0000ffaa, 0x7ffffffb, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000003, 0x00000000, 0x00015555, 0x000038e3, 0x00037f80, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xfff40401, 0x00000000, 0x0dc7e859, 0xf5177fff, 0x02eb8001, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xffe67a34, 0x001a06ca, 0x00098000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0xe0000000, 0x00000001, 0xe0000000, 0x80000000, 0x80000000, 0x80048000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x0000003f, 0x7fffffff, 0x8009002f, 0x7fff7fff, 0x00088000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x1fff0000, 0x8000fffa, 0x8000e007, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1ce2c63c, 0xffff7fff, 0x00708000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xff2b63f0, 0xff8271c7, 0xff10ff44, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf266fffb, 0x8000fffe, 0x00010d99, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x07c5007f, 0xf7fbffc0, 0x7fff8000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x7ffe0002, 0x00007fff, 0x7fff7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xfffffff2, 0xffffffff, 0xffffff2a, 0x0001fffc, 0x00190000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x33333333, 0x33333333, 0x33333333, 0xb3190b24, 0x8000029b, 0xfafb8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x3fffffff, 0xfffffff0, 0x3fffffff, 0xfffe0004, 0x7fffffff, 0xfff8fffe, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x3fffffff, 0xfffffff0, 0x40000000, 0x0251fb50, 0x80007fff, 0x0250fffe, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00cf4fc0, 0x55a72693, 0x00cf4fc0, 0x55b72613, 0x00100000, 0x00007ffc, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xc71c0000, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x3fa20000, 0xc01f8000, 0x003f8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0fffffff, 0xfffffff8, 0x10000000, 0x001087b0, 0x02123fc0, 0x000003fe, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xffffffff, 0xfff466a6, 0x00000000, 0x198d19da, 0x00013ffe, 0x33330000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x0000000f, 0xffffffff, 0xffff000f, 0x80007fff, 0x00000001, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0xffffe351, 0x19cff3df, 0xffffe351, 0x1a35d2c3, 0xffe15555, 0x0093f003, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00034480, 0x0000e5dc, 0xfff07fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xfffffc7c, 0x3136be68, 0xfffffc7c, 0x4f2db500, 0xc00f8000, 0x0008c3f4, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x0001e5cd, 0x994d42cb, 0x0001e5cd, 0x994d42cb, 0x80000000, 0x80000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x03ffffff, 0xfffffffe, 0x03ffffff, 0xf7ff0ff8, 0x7fff0004, 0x8000f803, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0xffffffff, 0xfff8ebaa, 0xffffffff, 0x8012dda0, 0x801ff9e6, 0x007f7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x1175dd14, 0x7fff71c7, 0x00001176, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000017, 0xc417ec8c, 0x00000017, 0xc43cec90, 0xfffeffd9, 0x80007fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00014957, 0xb94c731c, 0x00014957, 0xb9501dca, 0x0001e38e, 0xfff47fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x1fffffff, 0xfffffff0, 0x20000000, 0x006122d0, 0xff8f097a, 0x0563059e, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00229851, 0x00000000, 0x00229851, 0x00000e45, 0x00000015, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x6db6db6d, 0xb6db6db6, 0x6db6db6d, 0xb6db6db6, 0x003f000e, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffc0, 0x7fffffff, 0xfff9bfc6, 0xffff9249, 0x00071ffc, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x00077fdf, 0xe0018002, 0x1ff88000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x2aaad1ad, 0x00000000, 0x2983380d, 0x66668000, 0x012e0008, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0070000, 0xe0070000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xfed3701a, 0x7fffdb6d, 0xfffbfed2, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0xffffffff, 0xfffff372, 0xffffffff, 0xbdbd59da, 0x7fff0f0f, 0x8000cccc, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffc, 0xffffffff, 0xe7e90c14, 0xe3e50002, 0x001f6db6, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffff9, 0x7fffffff, 0xf84bacab, 0x71c7ff97, 0x8000f6df, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x000106ee, 0xa5857119, 0x000106ee, 0x8589b0fb, 0xe003fff8, 0x00007ffb, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x3ff70020, 0x80007fff, 0x7ff03ff8, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x03ffffff, 0xfffffffe, 0x03ffffff, 0xfffa282a, 0x001800a9, 0x001ee003, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000013, 0xffffffff, 0xc2f00013, 0x8000fd50, 0x80003fc0, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xc00bfff0, 0x80008001, 0xfff83ffc, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xfffffffd, 0x80007fff, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xe03a3522, 0xe00f002b, 0x7fe07fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x8000003f, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffffe44, 0x00000000, 0x81c1fabe, 0x0ffc7fff, 0x71c77fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x801ffff8, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfff607c0, 0xffe0fff0, 0x000027e1, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xcbec8822, 0x7ffff003, 0xffffcbec, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfffc0000, 0x0004fffe, 0x00008000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000005, 0x00000000, 0x00000005, 0x7fff0000, 0x7fff0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xfffffcec, 0xffffffff, 0xd821fcec, 0x80008000, 0x1fe007fe, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xfc0b2f8e, 0x51a4180a, 0xfc0b2f8e, 0x51a4055a, 0x005cfff3, 0x005cfff3, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffe, 0x01058e38, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x11440c4e, 0x00037ff9, 0x1145ffae, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x1fffffff, 0xfffffff8, 0x20000000, 0x000198d8, 0xfff08000, 0xfffe0339, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xfffff13e, 0x47048cc4, 0xfffff13e, 0x06a28da8, 0x80007fff, 0xff8e3ff0, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffa017, 0xfc010006, 0xfc010006, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x80000000, 0x00000004, 0x7fffffff, 0xfffd000a, 0x7fff0000, 0x8004fffd, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0x80010000, 0x800f8000, 0x7fff0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffff8, 0x80000000, 0x00f8fe06, 0x7fff0000, 0x7fff00f9, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x0006ffe4, 0xfff900ff, 0x00008002, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x666d38ef, 0x8e389999, 0x8000fff9, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xfffffffc, 0x80000000, 0x01cbb22e, 0x03e9807f, 0x00273fc0, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x0031b553, 0xffffffff, 0x8033b551, 0x00008001, 0x7fff0003, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x0000a24f, 0x8215c333, 0x0000a24f, 0xb8654371, 0x80008001, 0xc01f0991, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00d7d86e, 0xc845e3f6, 0x00d7d86e, 0xc845500e, 0xfff6ffff, 0x3ffe00ff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xf0000000, 0x00000007, 0xefffffff, 0xffe40727, 0xff8e8000, 0x001cfff8, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xfffa49e9, 0x7af19a01, 0xfffa49e9, 0x7ae0ff5d, 0xfe867fff, 0xfffe04f2, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x000003fe, 0x00000000, 0x000003fe, 0x00000000, 0xffdf0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x0006ac2f, 0xffffffff, 0xe015aa6f, 0x7fe0ff17, 0x0000e007, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x3fffffff, 0xfffffffc, 0x40000000, 0x7ff9588a, 0x026d8002, 0x80060047, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x80030000, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xffffffe4, 0x00000002, 0xfff97ffb, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x10657ba7, 0xf003068b, 0x07fc8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0xd66fd94c, 0x00000000, 0xd65eec6c, 0xffbcffef, 0x7f80fffc, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0xf0000000, 0x00000007, 0xf0000000, 0x00000007, 0x00007fe0, 0x00007fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0xc73871c7, 0x8000ffe5, 0x8000ffff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xef13ffff, 0x80008000, 0xf0f01ffc, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xfffd8000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0fffffff, 0xfffffffc, 0x0fffffff, 0xfffffffc, 0x80017fff, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x0004fa09, 0x00000000, 0x00d472c5, 0xe00fff40, 0x8000ffc2, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x000019d6, 0x25d2e61a, 0x000019d6, 0x25d2e61a, 0x00000000, 0x007f0001, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffb, 0xffffffff, 0xfffffffb, 0x00000000, 0x00008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xfc004d44, 0xfffde00f, 0x0ffc6db6, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xce3fffff, 0x8000fe8d, 0x80003333, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000002, 0x77029de6, 0x00000002, 0x77029de6, 0x0000ffb5, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xfffff9e6, 0xd57b1bc1, 0xfffff9e6, 0xc633f18f, 0x1ff0fd49, 0xe01fc00f, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000007, 0x00000000, 0x00000007, 0x00000000, 0xfd7ef003, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00001c0d, 0xdcaa4259, 0x00001c0d, 0xdcbc4235, 0x7fff0009, 0x7fff0009, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xffffff80, 0x7fffffff, 0x8000ff80, 0x80000000, 0x7fff7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x80000000, 0x00000002, 0x7fffffff, 0xfa180002, 0x800001d1, 0x000005e8, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffe0, 0x80000000, 0x04def622, 0x7fe07fff, 0x04df0000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffbee6c, 0x00000000, 0x3ff8ee6c, 0x80000000, 0xf001c003, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0x8002b414, 0xffc17fff, 0x8000fc8a, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xff546bd0, 0xffffffff, 0xff586bd0, 0xf003fffc, 0x80000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x24924924, 0x92492492, 0x24924924, 0x92492492, 0xf5e80000, 0x80000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffffb, 0x7fffffff, 0xf5a7ffff, 0x7fff0a56, 0x8000fffe, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000528, 0xffffffff, 0xff72e8f2, 0xf82ff932, 0x7fff9999, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00dae090, 0xf0f0ffff, 0xfff8f8bc, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x0000ffff, 0x0000ffff, 0x0000fffe, 0xffb107ff, 0xffd03ffc, 0xff008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0fffffff, 0xfffffffe, 0x0fffffff, 0x8004fffe, 0x8000fffc, 0x80007fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffd, 0xffffffff, 0xaaaaaaa9, 0x7fff8000, 0x0000aaaa, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0fffffff, 0xfffffff8, 0x10000000, 0x000dffea, 0x00000015, 0x55553c28, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x24f94f56, 0x8000fd5b, 0xfff1db07, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac3, 0x80000000, 0x0000003f, 0x7fffffff, 0xf9082a17, 0x00027ffd, 0xf9067fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x0a7f4d02, 0xdb6dc03f, 0xffe8db6d, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac0, 0x80000000, 0x0000003f, 0x7fffffff, 0xffc23e3f, 0x000f7f80, 0xffc20000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xf0000000, 0x00000003, 0xefffffff, 0xfff471cd, 0xfff3e186, 0x000071c7, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffc03fe, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffff8, 0x80000000, 0x7f7efdf8, 0x7f80ff80, 0x00037fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0xffffffff, 0xfffe99c9, 0xffffffff, 0xfffe99c9, 0x00000000, 0x0000f801, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x1872bff8, 0xe38e3ffc, 0xf8018000, 0x000f0000, 0x000f0000 + + writemsg "[50] Test dpaqx_sa.w.ph" + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xe0000003, 0xffffffff, 0xa57e0003, 0x80008000, 0xcccc6db6, 0x00000000, 0x00000000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xf88d618b, 0xffffffff, 0xf887a56b, 0xfffcfe2e, 0x007a7fff, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x800f1c6e, 0x000071c7, 0x00118002, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0xbfef8020, 0x00007fff, 0x3ff0ffff, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x000140d3, 0xffffffff, 0xfffe40d9, 0x7fff6666, 0x0000fffd, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xe5e57930, 0xffffffff, 0xe5de793e, 0x00007fff, 0xfff90000, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x07361af3, 0x00000000, 0x07501abf, 0x7fff0018, 0x7fff0002, 0x00010000, 0x00010000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x09fa7ff0, 0x80008006, 0x00010000, 0x00030000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00008010, 0xfff87ff8, 0x000107fe, 0x00030000, 0x00030000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x324df2ec, 0x00000000, 0x3257f2d8, 0x00007fff, 0x000a3ffc, 0x00030000, 0x00030000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffffe, 0x00000000, 0x0001ffe2, 0x0000fffe, 0x80070000, 0x00020000, 0x00020000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x3330666a, 0x7fff3ffe, 0x6666ffff, 0x00020000, 0x00020000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xffffffff, 0xffffffff, 0xc04ef87f, 0xc00ffff1, 0xffc07f80, 0x00020000, 0x00020000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000032, 0x0000fffb, 0xfffb07e8, 0x00020000, 0x00020000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xecf8827c, 0xffffffff, 0xecf87bdc, 0xffc0ffe8, 0xfffe000e, 0x00020000, 0x00020000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x01ccab39, 0x00000000, 0x01cca86d, 0xe38efffe, 0x00b30000, 0x00020000, 0x00020000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80030000, 0x7f800000, 0x00030000, 0x00030000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x38e38e38, 0x00000000, 0x4a5d7e40, 0xf6827fff, 0x07fc8000, 0x00030000, 0x00030000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xffef0770, 0xf0078000, 0x00000088, 0x00030000, 0x00030000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7ffffffa, 0x00000000, 0x7fffffff, 0x33330008, 0x7f80fff9, 0x00030000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xe38ec00f, 0x3ff80007, 0x000a0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x38e38e38, 0x00000000, 0x393a8e38, 0x80008000, 0xffa90000, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffb, 0xffffffff, 0xfffffffb, 0x00390001, 0x00000000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x003fffff, 0x00008000, 0x7fc07fff, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0xc103fd0c, 0xc01f3ff8, 0x7ffbfde2, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0x0000f0f0, 0x00008004, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x0003f46b, 0xffffffff, 0xf0f4e62b, 0xfff47ff8, 0xf0f0fff8, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x02aa0000, 0x0000fd56, 0x80007ffa, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000003, 0xffffffff, 0x80000000, 0x0000003f, 0xfff3e003, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7ffffffb, 0x00000000, 0x7ffd4c1b, 0x0f0f0171, 0xff100000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffff7, 0x00000000, 0x7ffe391f, 0xffc97fff, 0x7fffff7b, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xfffffffe, 0x00000000, 0x69512d5b, 0x8000e951, 0x7fff8000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffc0, 0x00000000, 0x7fffffc0, 0x00000000, 0x000e0007, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffe, 0x00000000, 0x80028004, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000009, 0x00000000, 0x00000009, 0x8000c00f, 0x00000000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000004, 0xffffffff, 0x80000000, 0x8000fff8, 0x000f3ffe, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffff1, 0x00000000, 0x2492fff1, 0x8000c007, 0x0000db6d, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffb, 0x00000000, 0x0005c713, 0x8e380004, 0x7ffffffe, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xc14f86eb, 0xffffffff, 0xc46a80b5, 0x8000031b, 0x7fff0000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x80000005, 0xffffffff, 0x8021db55, 0x7fffb6db, 0xffed0017, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xff6e72de, 0xffffffff, 0xff74f100, 0x7fff000f, 0x3ff0ffff, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7fe0fff2, 0x00000000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xffaff986, 0xffffffff, 0xffb6f978, 0x00000007, 0x7fff0699, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x4001a6a9, 0xfffbc001, 0x7ffffc22, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffff0000, 0x80008000, 0x00010000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000003, 0xffffffff, 0xb3340003, 0x8000fafe, 0x0000cccc, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffff7, 0xffffffff, 0xfc9d31a7, 0xf274fff0, 0x00241ffe, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0882eefa, 0x7fff0087, 0x7fff07fc, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00003cf0, 0x00000000, 0x00003cf0, 0x00000000, 0xfffce007, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x7fa9c8d7, 0xfc7e8000, 0x80000c4a, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffff0, 0x00000000, 0x4920184c, 0x7fffe38e, 0x000f4924, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00004275, 0x00000000, 0x1fde1a81, 0x00051fe0, 0x7fffcf2e, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x935162de, 0xffd81351, 0x7ffffe48, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffffc, 0x00000000, 0x001c9f44, 0x1c71800f, 0xff8afe6e, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xdb6db6db, 0xffffffff, 0xdb7cb6bd, 0xffcf000f, 0x7fff0000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xc00f0005, 0x7fff3fe0, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x003b4548, 0x800001c6, 0x0406ffd3, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xc01f7fba, 0x00047fff, 0xc01fffff, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x3fc00111, 0x80007fff, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffd52, 0x00000000, 0x03fbfe52, 0x00007fc0, 0x03fe1169, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x006f440d, 0xffffffff, 0xf075647f, 0x7ffffffe, 0x3fe0f007, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7ffffffb, 0x00000000, 0x60102a55, 0xff758000, 0x1ff0ffd9, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x80008000, 0xfffbff3f, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x0f0f0f0f, 0x00000000, 0x0f0f0f0f, 0x00000000, 0x1f378000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffe62, 0xffffffff, 0xfffffe62, 0x00000000, 0xff327ff0, 0x000a0000, 0x000a0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x0000014c, 0x00000000, 0x7ffff125, 0x8000000d, 0xff618000, 0x000b0000, 0x000b0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x99999999, 0xffffffff, 0x80000000, 0xfb9f8000, 0x49240020, 0x000b0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xf0017fff, 0x7fffff80, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0021d94c, 0x2d3e005f, 0x07fc004f, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0076af00, 0x00000000, 0x0076af00, 0xfff90000, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7fffffff, 0x7ff98000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0x809bfe92, 0xffe4807f, 0x7fff8002, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xc0000003, 0xffffffff, 0xbfc02003, 0xffe07fc0, 0xffe07fc0, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00000000, 0xff70f25f, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000102, 0x00000000, 0x00d30cde, 0x80000045, 0x0016ff2d, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0xffffffff, 0x80000000, 0x0f0f8000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x80008000, 0x1fe00000, 0x000e0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xfffe0000, 0x005d7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fb6a85b, 0xfefffaa0, 0xfffe2492, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x000676a7, 0x00000000, 0x000676a7, 0xffff0000, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x8000e2a7, 0x80008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00001d74, 0x00000000, 0x00001e28, 0x00020000, 0x1ffc002d, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x8000007f, 0xffffffff, 0x8000007f, 0xfffc5555, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x1ffffff0, 0xffffffff, 0xb999fff0, 0x00ff6666, 0x80000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7ff5806b, 0x1fe0000f, 0xaaaafffe, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x55555555, 0x00000000, 0x7fffffff, 0x2fa80000, 0x80067fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x8000003f, 0x00000000, 0x0000003e, 0x80001ff0, 0x00008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xfbeefffd, 0x03fe8000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00725318, 0xff8cfa0b, 0x00248000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xe99839be, 0x7fffe997, 0x7ff90000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x0000ffe4, 0xffda8004, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x3ffffff8, 0x00000000, 0x3ffffff8, 0xf7a80000, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xfe9512f0, 0x00000000, 0x7f281558, 0x7ffffe84, 0xcccc7ffc, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xf0000003, 0xffffffff, 0xf002fffd, 0x7ffff0f0, 0x00000003, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xff5a604a, 0x00000000, 0x075abf9a, 0xf80316b8, 0x00138000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x0feb0400, 0x00057fc0, 0x0ff88000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00000000, 0x80006666, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0000264c, 0x8000fccf, 0xfffa0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xf9130dda, 0xf9130064, 0x00007fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xffe76797, 0xffffffff, 0xf7d68095, 0x3fe07fff, 0xf801ffdc, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000003, 0x00000000, 0x00125559, 0x3ffcfff9, 0xf9d30024, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xfffc3a24, 0x00000000, 0x0722b9a6, 0xc007f8de, 0x8000fff7, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x49249249, 0x00000000, 0x7fffffff, 0xc0070000, 0x80078000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x333d62fd, 0x00000000, 0x333d62fd, 0x00590000, 0x00590000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x55555555, 0xffffffff, 0xd5555557, 0x8000ffff, 0x7fff7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xe6458001, 0x00008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffe, 0x00000000, 0x073f8006, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0004819e, 0x00000000, 0x0004ba20, 0x1fe00009, 0xff990001, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xf8000003, 0xffffffff, 0xf7ff0007, 0xffffffff, 0x7fffffff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x000179e7, 0xffffffff, 0xf00979e7, 0x00008000, 0x0ff87fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0cbac798, 0x00000000, 0x0ca9c7ba, 0xfcc0ffef, 0x7fff0000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xe00ffff0, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x000053c0, 0x00000000, 0x000053c0, 0x00000000, 0x7ff9e007, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x0013ffd8, 0x7fff000a, 0x7fff000a, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000001, 0x00000000, 0x01320605, 0xffeafece, 0x8000ffdd, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0ffca012, 0xf0038000, 0x00008003, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0xffffffff, 0xffe38475, 0x8005f5f8, 0x01b87fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x03771ff0, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xff719f94, 0xffffffff, 0xffb09dc6, 0x003ffff8, 0x00157fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0000003f, 0x00000000, 0x0000003f, 0x00008000, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000fea, 0xffffffff, 0x80000000, 0x800003fa, 0xdb6d7f80, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x000001ae, 0xffffffff, 0xfffffbd2, 0x000f0000, 0xfff7ffce, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7fff0000, 0x7fff7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00001bec, 0x00000000, 0x003509d2, 0xc2e9fd33, 0xfc01ffc0, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffb6123, 0xffffffff, 0xa4936123, 0x2db48000, 0x2db48000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x80000000, 0x3ff8fc5f, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xffffc18d, 0xffffffff, 0xffffc18d, 0x00000000, 0x00007fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x80008000, 0xfc548000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffc5700, 0x00000000, 0x7fffffff, 0x7ffffa96, 0x80007ff8, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xf7c140e2, 0x00000000, 0x37bdc0ec, 0xc0010000, 0x001c8005, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xdb6db6db, 0xffffffff, 0xd53050eb, 0x0000c618, 0x0dcb7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x8005fff4, 0x7fff0003, 0x7fff0003, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x000001f0, 0xffffffff, 0xffffd108, 0x0c3a0000, 0xd148fffe, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000003, 0x00000000, 0x00000003, 0x00038001, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x6db6db6d, 0x00000000, 0x6db0d0dd, 0x000000ca, 0xfc2c1fe0, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x71132c51, 0xf803c00f, 0x1fe0f003, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff800fb, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xe49376e4, 0x71c77fff, 0x00ffe007, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x00008000, 0x0000f803, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00062f91, 0x00000000, 0x2003ef95, 0x7fff0000, 0x7fff1ffe, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffff0, 0x00000000, 0x01c5ca98, 0xc71cc71c, 0xfc010002, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xfedc1764, 0x00018000, 0x01240bb2, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xffffffff, 0x00000000, 0x0001d303, 0xfffa5555, 0x0000d915, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x0000ffff, 0x00000000, 0x71c61c73, 0x7fff38e3, 0x7fff38e3, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x81e9fc2c, 0x034f7fff, 0xff146db6, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00099362, 0xf626f007, 0xffc7ffe0, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0063eed7, 0x00000000, 0x0063eed7, 0x00000000, 0x7f800016, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xfe9b0f10, 0xffffffff, 0xfe9b7c54, 0x05680006, 0xc01f0051, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x8003ffe0, 0x0000fff0, 0xe0010000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffffc, 0xffffffff, 0xffb82e5c, 0x0000f8d0, 0x04ff0061, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffff883, 0x00000000, 0x7f8bf96a, 0x80007fff, 0xff8c8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000001, 0x00000000, 0x00009bed, 0xfcaa8000, 0xffff000f, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x1f505597, 0xffffffff, 0xbf4215b5, 0x1ff07fff, 0x80017fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0668bf07, 0xffffffff, 0xe670bef3, 0x00028000, 0x1ff8fffb, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xc0000003, 0xffffffff, 0xdff8ffc7, 0x8000fffe, 0x000fe007, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x0000003f, 0xffffffff, 0xfffb003f, 0x00000005, 0x8000fffb, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x046ccb93, 0x00000000, 0x04d4879b, 0xfffb03fe, 0x0cfe0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00ff00ff, 0x00000000, 0x00ff00ff, 0x00000000, 0x7f808003, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xf9bdee71, 0xffffffff, 0xf9bbee75, 0x00007fff, 0xfffecaf1, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00075732, 0x00000000, 0x00075732, 0x2d250000, 0x2d250000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000004, 0x00000000, 0x7fffffff, 0x80008000, 0x80008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0000599b, 0x00000000, 0x0000599b, 0xfffc0000, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x740f882b, 0xf6468000, 0x02377ff9, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0x80000000, 0x00d37fff, 0x80008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffe0, 0x00000000, 0x7fffffe0, 0x80000000, 0x49240000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xffffffcc, 0xffffffff, 0xfff800cc, 0x8000fff8, 0x1ff00006, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xca06af80, 0x92497f80, 0x00ac3fc0, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xe0000001, 0xffffffff, 0xe0080001, 0xfffbfffd, 0x80008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffc66, 0xffffffff, 0xfffffc64, 0xc71cffff, 0x00010000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x49249249, 0xffffffff, 0xc92a923f, 0x80050000, 0xfffe7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x81fee00a, 0x0ffbfe01, 0x8000ffff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xffffff2c, 0xffffffff, 0xff319e1c, 0x00ce001f, 0xfe4e8005, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xc0000003, 0xffffffff, 0xdacb90c3, 0x80001b7a, 0x7ff000ab, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fff000b, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xedeb1ff0, 0x00007fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xfff49a0a, 0x00000000, 0x0620a728, 0x0cbb7fff, 0x062c0001, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00140000, 0x000a8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x76b9124f, 0x001f7fff, 0xf69a7ffe, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0ffe8000, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xffece62f, 0xffffffff, 0xffe80297, 0x0011000b, 0xc71c0000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x8007ec08, 0x8000007f, 0x07fc0000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xffc80370, 0xfff8ffc8, 0x7ff80001, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x8001bf44, 0xfffd7fff, 0x0001e01f, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7ffffe5b, 0x0004000f, 0xfff20000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x002a6d51, 0xffffffff, 0xfdf90e8b, 0x078e3363, 0xfa81003b, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x78e463e9, 0xc71c0003, 0x000f0ffe, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x00000000, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x8000001f, 0xffffffff, 0x8000001f, 0x0005db6d, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xffffff7e, 0xffffffff, 0xff56e35a, 0xc0036db6, 0x000f016c, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x6db6db6d, 0x00000000, 0x6fb5b2dd, 0x6db6012a, 0x6db6012a, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7ffffffe, 0x00000000, 0x7fffffff, 0x8000ff59, 0x06d38000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x1ffffff0, 0x00000000, 0x2c92b712, 0xe6d5f575, 0xfffec00f, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xfc01b6e0, 0x03fcfffc, 0x49248000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x24924924, 0x00000000, 0x24924924, 0x00000000, 0x000e7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7ffd07fc, 0x55551fe0, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00000000, 0x7ffff74a, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xffffcbb8, 0xffffffff, 0xc0eb49e2, 0x7fff0000, 0x006ac0eb, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x037df97e, 0xffffffff, 0x839df940, 0x801f7fff, 0x00007fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000047, 0x00000000, 0x000e002b, 0xfff98001, 0xfff98001, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xc0000003, 0xffffffff, 0xc0000003, 0x6666ffff, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00004b97, 0x00000000, 0x00004b97, 0x00000000, 0x00030111, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x92492492, 0xffffffff, 0x9249648a, 0x00000001, 0x1ffc0004, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xff00ff00, 0xffffffff, 0xff013ec2, 0x3ffcffff, 0xe01f0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xcfdad684, 0xffffffff, 0xcfdad6c0, 0x0000fffa, 0xfffbe493, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xffffe46d, 0xffffffff, 0xffffe44d, 0x00000002, 0xfff80004, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xffffcaaa, 0xffffffff, 0xfff9cbf2, 0xfff5ffc8, 0xff564924, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x0000000f, 0x00000000, 0x00000123, 0x00060000, 0xfe200017, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80010000, 0x80001ff0, 0x0000ffff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00003ff8, 0x0000807f, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xf0635618, 0x0ffeaaaa, 0xff6e8000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x0001d4b0, 0x00000000, 0x7fffffff, 0x7fff8005, 0xffeb7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x1c71c147, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7ffffffb, 0x00000000, 0x7ffffffb, 0x00000000, 0x0000fffd, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xffffff80, 0x00000000, 0x0014ff56, 0x7fff0015, 0x7fff0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xf8000001, 0xffffffff, 0xc0fd0001, 0x00248000, 0x37030000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xd097284c, 0xffffffff, 0xd099284c, 0x80000000, 0x0000fffe, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7ffffffc, 0x00000000, 0x7fffffff, 0xfffcfff5, 0x0000fff6, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00ff00ff, 0x00000000, 0x00ff00ff, 0xfc450000, 0xfff00000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x3148d154, 0x7fc07fff, 0x05162c49, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xdb6db6db, 0xffffffff, 0xc9a05e1f, 0x7fffc001, 0x03a9f007, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xc001c01f, 0x00003ffe, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffff251, 0xffffffff, 0xfffdf255, 0xfffe0000, 0xff9e7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0002c020, 0xfffdffff, 0x1ff08000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x0000000c, 0x00000000, 0x7ffeff96, 0x7ffffffc, 0xe00f7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xc000000f, 0xffffffff, 0xbf01000f, 0x00008000, 0x00ffaaaa, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00000509, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xdb6db6db, 0xffffffff, 0xdb611a63, 0x19bcfff4, 0x3fc0ffdf, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7fff8000, 0x00000002, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x6db6db6d, 0x00000000, 0x0002b6fb, 0x9249ffef, 0xf0f07fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffffd, 0xffffffff, 0xff00b9c5, 0x7ffb0003, 0x1d4cff00, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xffffc14b, 0x00000000, 0x38afe0d9, 0x38b4068f, 0x00c97fe0, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fa86da9, 0x004f000f, 0xb6db8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x1ffffff8, 0x00000000, 0x6924fdf8, 0x80000004, 0xffc0b6db, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xc000001f, 0xffffffff, 0xbffe6d3f, 0x1ff80007, 0xfea0fffa, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x1ff8e001, 0x492400ff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0012ffda, 0x7fe07fff, 0x00130000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xffffffff, 0x00000000, 0x01cfffff, 0xff2e8000, 0xff028000, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x000007b4, 0x00000000, 0x30b05b14, 0x7ff93fc0, 0x7ffff0f0, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffe764c8, 0x0064e38e, 0x0000e081, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xc0000003, 0xffffffff, 0xbf913411, 0xff929999, 0x00017fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xf8000001, 0xffffffff, 0xf8000001, 0x00000000, 0x8005c71c, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xfffffe9f, 0xffb43fe0, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7fff7fff, 0x00000558, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xf82c0000, 0x1fe00000, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffc, 0x00000000, 0x00026ccc, 0x00560000, 0xfff7039c, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffc, 0xffffffff, 0xfe00efe0, 0x07fefe7b, 0x0000e007, 0x000f0000, 0x000f0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xf1ad5eb4, 0xffffffff, 0xf1ad5eb4, 0x00000000, 0x00057fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffff0, 0xffffffff, 0xfffffff8, 0xffff0000, 0x0000fffc, 0x000e0000, 0x000e0000 + dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80eb0000, 0xff157fff, 0x00008000, 0x000e0000, 0x000e0000 + + writemsg "[51] Test dpsqx_s.w.ph" + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x2492b6da, 0xdb6d8000, 0x00007fff, 0x00000000, 0x00000000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xffffffc4, 0x00000000, 0x00feff84, 0xffe08000, 0x00ffffff, 0x00010000, 0x00010000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000001, 0x00000000, 0x7fff0001, 0x000b8000, 0x7fff0000, 0x00000000, 0x00000000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000001, 0x00000000, 0x4d748fad, 0x55557fff, 0xdd21c01f, 0x00000000, 0x00000000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00005244, 0x00000db6, 0xfffd0000, 0x00010000, 0x00010000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xffc054e0, 0xfff0c003, 0xff80028f, 0x00000000, 0x00000000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xfffffff8, 0x7fffffff, 0xfffffff8, 0x92490000, 0x80070000, 0x00010000, 0x00010000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00003f63, 0xe876f2fc, 0x00003f63, 0xe876f2fc, 0x00000000, 0x001f3fe0, 0x00000000, 0x00000000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xfffffffc, 0x80000000, 0x0055ffa6, 0xff297fff, 0x00003333, 0x00000000, 0x00000000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000013, 0xffffffff, 0xffc98e23, 0x0006feaf, 0xe95e9249, 0x00000000, 0x00000000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x0208d1d3, 0xddcccf9f, 0x0208d1d3, 0xddcce11b, 0x000201f8, 0xfffcff91, 0x00000000, 0x00000000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xfffdf0f0, 0x00010000, 0x00010000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xc0000000, 0x00000001, 0xbfffffff, 0xed386571, 0x02d07ffd, 0x0ff87fff, 0x00000000, 0x00000000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xf0000000, 0x00000003, 0xefffffff, 0xfc01fff5, 0xfffffc01, 0x80007ff9, 0x00000000, 0x00000000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xfff660c2, 0xffffffff, 0xfffc06c0, 0xfffb0003, 0xe4547fff, 0x00010000, 0x00010000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x0000001f, 0xffffffff, 0x80000020, 0x80000000, 0xf8038000, 0x00000000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xf8000000, 0x00000003, 0xf7ffffff, 0xcccd6669, 0x7fff01bb, 0x00003333, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xf0000000, 0x00000007, 0xf0000000, 0x0000a105, 0x04c0ffff, 0x7fff000a, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xffd3a2c6, 0xfe9d0000, 0x0000f001, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xfffffffe, 0x6b07649d, 0xfffffffe, 0x6b17647d, 0xfff00000, 0x7fff7fff, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00001915, 0x9091c8b8, 0x00001915, 0x8ff6fb5a, 0xffc6ff87, 0x99998000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x55555555, 0x55555555, 0x55555555, 0xd5545555, 0x8000001b, 0x00007fff, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xfffff945, 0xffffffff, 0xfffcf96f, 0xffe9fffd, 0x80070000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x3fffffff, 0xfffffffc, 0x40000000, 0x8662c002, 0x80007fff, 0xe0036666, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x55555555, 0x55555555, 0x55555555, 0x554e15cd, 0x1ffc000e, 0x3ffc0001, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x0000000f, 0xffffffff, 0xf9f02f83, 0x05b5b6db, 0xff617fff, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x01cd0b40, 0xfc01040a, 0x001039c0, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x01e46e08, 0x00000000, 0x81c46e46, 0x80067fff, 0x801f0000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xfffbff4d, 0x000a549d, 0xfffbff4c, 0xe13f9233, 0x025a7fff, 0x1c717fff, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xb6db6db6, 0xdb6db6db, 0xb6db6db6, 0xdb6db6db, 0x00000000, 0x80000000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x0129823f, 0xffcee007, 0xffe27fff, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffff03, 0x35e13d56, 0xffffff03, 0x35e220e6, 0xc71c3fe0, 0x00000002, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00030006, 0x00017fff, 0xfffdfffa, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffcf7f3, 0xfffdff32, 0xfffb8000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x0000006b, 0xb4ed34b8, 0x0000006b, 0xb25330b8, 0xff808000, 0xfd66fffc, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xe6377963, 0xffffffff, 0xe6377963, 0x00000000, 0xfffd7fff, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffbc, 0x1d56b826, 0xffffffbc, 0x1d59b826, 0x80008007, 0x80007ffc, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xfffffff0, 0xfffdc8dd, 0x00000000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xfffff704, 0x127e1c68, 0xfffff704, 0x127e1c5c, 0x00060000, 0x00690001, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00001e7a, 0xffffffff, 0xff55727a, 0xff000000, 0x014aaaaa, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x0000018b, 0x00420000, 0xfe66fffd, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xff95fff0, 0xff96f46c, 0x00008000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000004, 0x00000000, 0x0045ff78, 0x00007fff, 0xffbaffe9, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000005, 0x7fffffff, 0xfc040801, 0x7fff8000, 0x000203fe, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xe38e38e3, 0x8e38e38e, 0xe38e38e3, 0x8e38e38e, 0xf0f00000, 0x00000000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x48d1a39a, 0x00000000, 0x48f2a3a0, 0x8000ffff, 0x00030021, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x0000000c, 0x0c497530, 0x0000000c, 0x0c4b7512, 0xfffd8000, 0x0002fffb, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000006, 0xffffffff, 0xc0027d28, 0x3ffe016d, 0x00017fff, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000001, 0x0f639f38, 0x00000000, 0x8f6c9f28, 0x00007fff, 0x7ff88000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x55166513, 0x7fff003f, 0x7fe0aaaa, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x000001b4, 0x00000000, 0x000400ec, 0x0000ff11, 0x02248000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffffff, 0xfffffffd, 0xffffffff, 0xf017387b, 0xfffce00f, 0xc03ffffc, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x0ffe0000, 0x0ffe0000, 0x80008000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xc0000000, 0x00000003, 0xc0000000, 0x2489db43, 0xdb6d803f, 0x00007fe0, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x0004fb27, 0x00140000, 0x0018e01f, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffffff, 0xfff86f81, 0xffffffff, 0xfff86f7d, 0x00000001, 0x00027f80, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x3fffffff, 0xffffffe0, 0x3fffffff, 0xffffffe0, 0x07fe0000, 0x03fe0000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xfffffef0, 0xc81352f5, 0xfffffef0, 0xc7ef93c3, 0x011771c7, 0x00010ffe, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x0061adb8, 0x892ce692, 0x0061adb8, 0x8951e648, 0x7fff0000, 0x0000ffdb, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xc0082497, 0xc0070004, 0xdb6d8000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xfc000000, 0x00000001, 0xfbffffff, 0xf0041ff9, 0x00000ffc, 0x7fff0000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x0033ff98, 0xf003ffcc, 0x7fff0000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x0000495f, 0xaca5aaeb, 0x0000495f, 0xad3e97cb, 0xfecef001, 0x00003ff8, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x0000006b, 0x00000000, 0x0001a08d, 0x014f0000, 0x8000ff61, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x01ebf1a4, 0xfb3cb2c6, 0x01ebf1a4, 0xa5e8b2b2, 0x7ffbaaaa, 0x8000fffe, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x000002dc, 0x9e9a53c7, 0x000002dc, 0x1e9c53c5, 0x02eb7fff, 0x7fff0000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000005, 0x80000000, 0x00000005, 0x00017fff, 0x00000000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x063a150b, 0x5ca2e025, 0x063a150b, 0x5c9ce025, 0x80000000, 0x036cfffa, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0xc0018000, 0x7fff8000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xffffff06, 0x00000000, 0x000eff06, 0x0000000f, 0x80000000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfba50006, 0x00000000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000001, 0xbfa5a453, 0x00000001, 0xbf8cd953, 0xfffa7fff, 0x0016c467, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x2a110863, 0x00000000, 0x2614e781, 0x00070ffc, 0x1ff0f007, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xf0000000, 0x00000003, 0xf0000000, 0x00010c43, 0x01880001, 0x8000fffc, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xfc000000, 0x00000001, 0xfc000000, 0x68e309a7, 0x6db67fff, 0x04d38000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xff626849, 0xa8847aae, 0xff626849, 0xa83c5af4, 0x012fffff, 0x7fff1ee4, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xf0021ffc, 0x7fff0005, 0x00000ffe, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000394, 0xffffffff, 0x924b0394, 0x80008000, 0x92490002, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffff5f, 0xfff00000, 0xc007fffb, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x76c21a35, 0x00000000, 0x86c01a35, 0x800f8000, 0x0ffe0000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffe162, 0xc09e823b, 0xffffe162, 0xc09e823b, 0x0000e38e, 0x00000000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000007, 0x7fffffff, 0xfeae07f3, 0xf8037ffd, 0x01520000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffdd, 0xd34a8b05, 0xffffffdd, 0x534c8b03, 0x00007fff, 0x7fffe50d, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffc42c, 0x8501eb4b, 0xffffc42c, 0x850122f5, 0xfffa800f, 0xffff04a1, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000005, 0x00000000, 0x00021e89, 0x07a10002, 0x8000fffe, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffffff, 0xfffffbda, 0x00000000, 0x0000ca8e, 0x00010cec, 0xfff80006, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xfffffb03, 0xffffffff, 0x80017ab0, 0xe0078000, 0x80000006, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000eef, 0xa2626579, 0x00000eef, 0x2266db99, 0x8004ff70, 0x00698000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x1fffffff, 0xfffffff8, 0x20000000, 0xfff6fff8, 0x80007ff8, 0x80007fff, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000003, 0x00000000, 0x00257095, 0xc03fffea, 0x7fff001f, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffb, 0x00000000, 0x8000ffef, 0x7fff7ffb, 0x8000fffa, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffff852f, 0x4788b9a2, 0xffff852f, 0x317c3942, 0x3ff08000, 0xe9f2fffd, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xffffff80, 0xffffffff, 0xffffff80, 0xdb6d7fff, 0x00000000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000078, 0x00000000, 0x00002146, 0xffef3ffe, 0x000000f7, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x3ffc0000, 0x3ffc0000, 0x3ffe8000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xfffff783, 0xffffffff, 0x2491f783, 0x80009249, 0x80009249, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x001448fb, 0x7fff6db6, 0xfffbfff0, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xcccc0000, 0xcccc0000, 0x00058000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xffffff00, 0xffffffff, 0xffffff00, 0x00000000, 0xfff03ff0, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x00080def, 0x0007fff8, 0x7fffff00, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x0006ffff, 0x80000000, 0x00000007, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xffffff00, 0x00000000, 0x0347fbb8, 0x55550000, 0x7ffffb14, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00670000, 0x80001437, 0x00000067, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf6e0123f, 0x0ff87fff, 0x00004924, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x03fb807f, 0x1c71f801, 0x3fc00000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xfffffed5, 0x6eb30c90, 0xfffffed5, 0x8e8c1450, 0x7fe00000, 0xffffe01f, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x03892485, 0xe4c0f937, 0x03892485, 0xe4d7f889, 0x7ffffffc, 0xfff0ffe9, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x03570000, 0x80008000, 0x03550002, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xfffe01fc, 0x07fefffe, 0x807f0000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x07ffffff, 0xfffffffc, 0x08000000, 0x000026ca, 0xffff8000, 0x00001367, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffff9, 0x80000000, 0x1b6ca48d, 0xe0010000, 0x1e426db6, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x3fffffff, 0xfffffffc, 0x40000000, 0x7fed0d10, 0x00ff7fff, 0x800f017b, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x02834930, 0x00000000, 0x02834930, 0xf5f87fff, 0x00000000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xc0000000, 0x00000003, 0xbfffffff, 0xfffe38e3, 0xc71c007f, 0x0000fffc, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xe3da01b6, 0x0986801f, 0xe003cccc, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0001000e, 0x00000000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xfffef704, 0x00000000, 0x03fbf784, 0x7fc0fbc2, 0x0000fc01, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000265, 0x00000000, 0x7fff0265, 0x80000000, 0x000f7fff, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00019da7, 0xd2dfd8fe, 0x00019da7, 0xd333b9ae, 0x80008e38, 0xee630ffc, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x219e0000, 0x80003ffe, 0x8000e1a0, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00051a30, 0x93e3d658, 0x00051a31, 0x93e1d658, 0x80008000, 0x7fff7fff, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffe52dd0, 0xb6a53cf9, 0xffe52dd0, 0xb6a50d05, 0xcccc07fe, 0x00030000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x002f9747, 0x00000000, 0x002fe233, 0x80002576, 0xffff0000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f819c0f, 0x0000ff1a, 0x3fc0cccc, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xc003f77c, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0x4a719a07, 0xffffffff, 0x7c329a07, 0x31c4fffd, 0x80008000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000005, 0xffffffff, 0xf461af61, 0x7ffff99d, 0xf0f00ade, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x3fffffff, 0xfffffffe, 0x3fffffff, 0xfffffffe, 0x80008000, 0x00000000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x000011ed, 0x00000000, 0x000011ed, 0x3ff80000, 0xffc00000, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000015, 0xffffffff, 0xc2c20015, 0x800002b3, 0x8000c00f, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x0000fffe, 0x7fff7fff, 0x0000ffff, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000003, 0x00000000, 0x0015e35d, 0x800038e3, 0xffd10001, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xffffc2d4, 0x0000020a, 0x000f1ffc, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0x80058000, 0x00000000, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffff0, 0x7fffffff, 0x7ffffff1, 0x80000000, 0x00008000, 0x00020000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00079c4b, 0x00000000, 0x00084f97, 0xffa60143, 0x000000ff, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xf0000000, 0x00000003, 0xf0000000, 0x7ff9ff03, 0x8000ff80, 0xffff7ffa, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x06120000, 0x06228000, 0xfff08000, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x0fffffff, 0xfffffffc, 0x10000000, 0x0060d9b8, 0x1ffc0f0f, 0xfff2fe83, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xfffb17f0, 0xe3740000, 0x0000ffea, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffff0, 0x7fffffff, 0xff73fff0, 0xff640010, 0x80008000, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xe03e6b1c, 0xffffffff, 0xe03e6a9c, 0xffff0000, 0xf0f0ffc0, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000104, 0xeff86417, 0x00000104, 0xf7f6041d, 0xfffd8000, 0x07fef001, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x80007fff, 0x00000000, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xc0000000, 0x00000003, 0xbfffffff, 0x8004fff7, 0x7fff8002, 0x80030000, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x0000007f, 0x80000000, 0x0000007f, 0x00000000, 0x807f0135, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000005, 0xffffffff, 0xffffff15, 0xc01fffe2, 0xfffc0000, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xfea6d946, 0x00000000, 0x53fbd9a0, 0x55550003, 0xfff18000, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xfffffff0, 0x7fffffff, 0xfffffff0, 0x00000000, 0x00000000, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xffef3e2c, 0xffffffff, 0xffef3e2c, 0x00000000, 0x8000ffde, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfffffffe, 0xffffffff, 0x7fff8000, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x0005fff4, 0x7ffffffd, 0x7ffffffd, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xffea7dbf, 0x00000000, 0x1c5b7cc1, 0x1c71007f, 0x00018000, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffff9c, 0xa2f00fdf, 0xffffff9c, 0xa318a265, 0x00473ff0, 0x0000b6db, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x000018c7, 0x003d021a, 0x0000ffcc, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xfffffffc, 0x7fffffff, 0xfffffffc, 0x00001ffc, 0x00003fe0, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffd0ffff, 0x00008000, 0xffd1028d, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0001ff9e, 0x00000000, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xfff31e51, 0xffffffff, 0xfff32a07, 0xfa257fc0, 0x00000001, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xfffffff8, 0x7fffffff, 0xfffffff8, 0x00000fc1, 0x00000000, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0x8000fff8, 0x00000000, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x0fffffff, 0xfffffffc, 0x0fffffff, 0xf005ff7c, 0xfffc3ff0, 0x1ffc0000, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xf0070000, 0xf0077fff, 0x00008000, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x0057f0ac, 0x00000000, 0x8037f0ac, 0x00008000, 0x7fe07ffa, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x5f724e7f, 0x8000209d, 0x7fc07fff, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00007c33, 0xffffffff, 0xfffc7c3b, 0x00000004, 0x7fff9249, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x003b0adf, 0x88661e68, 0x003b0adf, 0x884ad91c, 0x1ff009ce, 0xfec500ce, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x7ffd0006, 0x00038000, 0x80007fff, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffff2817, 0x84076dc7, 0xffff2817, 0x84326d71, 0xffd50000, 0xfff87fff, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00015b6b, 0xe56bd5cd, 0x00015b6b, 0xe56ad5dd, 0x1ffee007, 0x00000004, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xb6db6db6, 0xdb6db6db, 0xb6db6db6, 0x7168a629, 0x1fe08001, 0x99990e8a, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x0000000a, 0xa1b1b7c6, 0x0000000a, 0xa29ffc86, 0x4924febc, 0x8000fc28, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x000ac690, 0x00000000, 0x0006c9d2, 0x0004fff9, 0x003b7fff, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xfffffffc, 0x00000000, 0x7ff8fffc, 0x80008000, 0x00007ff9, 0x00060000, 0x00060000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000edc, 0xffffffff, 0x40208e9d, 0x80003fe0, 0x7fff8000, 0x00060000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffe8a740, 0x6aed4a59, 0xffe8a740, 0x6aed4a59, 0x00067fff, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00078846, 0x1555102f, 0x00078846, 0x1654783b, 0x0000e003, 0x03feffff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0x80dbfe86, 0x801fff43, 0x7fff8000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xfffffffb, 0x80000000, 0x00000037, 0x0000000f, 0xfffef007, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffb, 0x00000000, 0x0006cfe5, 0x000d38e3, 0xfff8dfef, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xfffdfff6, 0xdb6d0000, 0x7ffffff9, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x8e38e38e, 0x38e38e38, 0x8e38e38e, 0x3a768b12, 0xff227fff, 0xfe6d0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xfffe3805, 0xffffffff, 0xfffd5875, 0x00250ff8, 0x00070000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x0062b411, 0x30dbf45f, 0x0062b410, 0xbf15d78d, 0xfffc7fff, 0x71c7fff4, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00f3f0be, 0x2efcd0a6, 0x00f3f0be, 0x2f02ce6a, 0x005b7fff, 0xfffbfe9b, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x000000e8, 0x5d89b153, 0x000000e8, 0x47616e13, 0x800015e6, 0x7ff0ffbb, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x03e95ee3, 0xfc01e12a, 0x0f0f0918, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000001, 0x6ea2d64b, 0x00000001, 0x6ef6d64b, 0x0054aaaa, 0x00008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x8f0e0000, 0x7fff8000, 0x0f0f8000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00f8010d, 0x00000007, 0x7fff7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xffff8780, 0xf0f08006, 0x0000fffc, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xfffe2a94, 0xffffffff, 0xfffe4a8c, 0x0ffc0001, 0x0000ffff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x7f702cae, 0xfb627ff9, 0x803ff801, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000122, 0x832b01c4, 0x00000122, 0x8316a6d0, 0xb6db004d, 0x1ff0fffe, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x0000b153, 0xa32a28ae, 0x0000b154, 0x230428a4, 0x801ffffa, 0xffdb7ff9, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffffa, 0x80000000, 0x671300fc, 0x00d87fff, 0x99999999, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xf804104c, 0x07fcfff9, 0x00067fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xf8019000, 0x07fee001, 0xfffe7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xf8020fc4, 0xfff907fe, 0x7ffffffc, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000007, 0x7fffffff, 0xeb9cda0d, 0xf46b801f, 0xe0037fe0, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffc0, 0x80000000, 0x0040fcd0, 0x3ffc0012, 0x8000ffa2, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x24706728, 0x0ffc8006, 0x0001c003, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x1fffffff, 0xfffffffc, 0x20000000, 0x0005fffc, 0x80000000, 0x80010006, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x7ffa7fff, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x010cfde6, 0x7ffffff3, 0x7fffff00, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x000001b7, 0x00048000, 0x0000ffc9, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffffff, 0xe8486105, 0xffffffff, 0xce18cfb3, 0x0000e5cf, 0x80070006, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x7ff0001e, 0x00007fff, 0x800f02a6, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xfffffef0, 0xffffffff, 0xfc0606e4, 0x7fff03f5, 0x7fff0005, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000064, 0xffffffff, 0xcccd66ca, 0x00003333, 0x7fff8000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffe0740e, 0x3287e00f, 0xff80ffff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x0fffffff, 0xfffffffe, 0x10000000, 0x2aad8000, 0x80005555, 0xc0030005, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x0eeee002, 0xfef0f001, 0x7fff8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xfe876f58, 0xffffffff, 0xfe391ab2, 0xaaaa0053, 0x7fff0007, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x0000043c, 0x010d0001, 0xfffcfffe, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xfffffff9, 0x00000000, 0x71737f85, 0x8e380ffe, 0x028f7ffd, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xfffe33c5, 0xffffffff, 0xffd533d1, 0x80008006, 0xffffffd8, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00005270, 0x0fa26952, 0x00005270, 0x0f719bc2, 0xfc01cccc, 0xff860000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xfffc0000, 0x80000000, 0x8000fffc, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xfffffe27, 0xffffffff, 0x8800ee2d, 0xf8038000, 0x80047fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xc0000000, 0x00000001, 0xbfffffff, 0xffffff8d, 0x0000ffe3, 0xfffefafe, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xffbe11b2, 0x80000003, 0xfd0dffbe, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffffff, 0xfffffffe, 0xffffffff, 0xc0027ffa, 0x00003ffe, 0x7fffff2f, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffa9c9, 0x4e755172, 0xffffa9c9, 0x52c649cc, 0x0451ffee, 0x00078001, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffdd803f, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfffe3c20, 0xfff1ff5a, 0x0000f0f0, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffe0, 0x7fffffff, 0xfe2a2708, 0x1ffc807f, 0xfe5c00ce, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xe007d9a7, 0x01141ffe, 0x7fe000ff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xfffffffa, 0x80000000, 0x2a95d530, 0xffffc01f, 0x5555ffe6, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x0000003f, 0x00000000, 0x0f0f003f, 0x0f0f0000, 0x7ffc8000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000001, 0x7fffffff, 0xc03f0001, 0x9999c03f, 0x80000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffe87fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffffe, 0x7fffffff, 0xfffffffe, 0x80009249, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x0002feb5, 0x0003ffff, 0xff5b8000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0xf311d96e, 0x00000000, 0xf213db4c, 0x7fff0ffe, 0xfff800ff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x000003e9, 0x00000000, 0x000003e9, 0x00008000, 0x0000e0d1, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x0000000f, 0x7fffffff, 0xffe80023, 0x0019800f, 0x00017fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000641, 0xb58ec28c, 0x00000641, 0x9ae4e7e2, 0x12ab8000, 0xf8017fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x7ffbffff, 0x80003ffe, 0x80003ffe, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1c71c71c, 0x00000000, 0x00009999, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x7ffc0000, 0xfffc8000, 0x80008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffff80, 0xacac92de, 0xffffff80, 0x2ca992e6, 0x7fff0005, 0x7fff7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfdcbffff, 0xfdcc0000, 0x80008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffffff, 0xfffffffb, 0xffffffff, 0x7fad01ee, 0xffad8000, 0x80008003, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xfffff4ce, 0x7fffffff, 0xfa670000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xfff083e0, 0x1fe0001f, 0x3ff00000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x000008ee, 0x00000000, 0x00006a26, 0x00cc0001, 0x0000ffc3, 0x000e0000, 0x000e0000 + + writemsg "[52] Test dpsqx_sa.w.ph" + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffffe7, 0x00000000, 0x0050ffe7, 0x8000ffe0, 0x00000051, 0x00000000, 0x00000000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xfffffff8, 0xfe1afff8, 0x00000000, 0x00020000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000001, 0x00000000, 0x0144cbeb, 0x0a07fffc, 0x7ffff001, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x005e8cd9, 0xffffffff, 0x80608cd7, 0x7fff0000, 0xf0017fff, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x99999999, 0xffffffff, 0x99999999, 0x00000006, 0x00000006, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x007cd308, 0x00000000, 0x007b365c, 0x00070ebd, 0x00070ebd, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffffffd4, 0x00000000, 0x7fff00d4, 0x00017fff, 0x8000ff80, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffb, 0x00000000, 0x03c80efb, 0x80001ff8, 0xf0f00005, 0x00020000, 0x00020000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x800b3278, 0x0006fff0, 0x7ffa6666, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xfc000001, 0xffffffff, 0xfbe80031, 0x7ffffffa, 0x7fff001e, 0x00030000, 0x00030000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7ffffffd, 0x00000000, 0x7fffffff, 0x29ac1fe0, 0xffda000b, 0x00030000, 0x00070000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x2472b6da, 0x8000db6d, 0x7fffffe0, 0x00070000, 0x00070000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7ffffffd, 0x00000000, 0x7fffffff, 0xdb6d8000, 0x7ffffffa, 0x00070000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xffffffe2, 0xffffffff, 0x8001def3, 0xfff18000, 0x80000ff8, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0000835a, 0x03eefffd, 0x1c710005, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7ffffff8, 0x00000000, 0x165faaa2, 0xebb47fff, 0x55558000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x000002e1, 0x00000000, 0x00004af7, 0xfffc0269, 0xfff1fff9, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x8c0c9084, 0x0062f0f0, 0x6666003f, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x92492492, 0xffffffff, 0x924224a0, 0x7fff7fff, 0x00070000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffca267, 0xffffffff, 0xfffd05af, 0x08460000, 0x8006fffa, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x7fff0015, 0x80008000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xaaaaaaaa, 0xffffffff, 0xaaaaaaaa, 0x7ffff0f0, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000b8e, 0xffffffff, 0xe90a7b6e, 0x00027ff8, 0x16f63fe0, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffffff80, 0xffffffff, 0x80000000, 0x80008000, 0x8000aaaa, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x7ffef004, 0xfc018000, 0x7ffffffe, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x0000c90c, 0x7fffdcec, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x0000005a, 0x00000000, 0x0000005a, 0x0ff80006, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffde, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xffffffff, 0x00000000, 0x10e6de3b, 0x00017fff, 0xef187ffa, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x0520cc81, 0x00000000, 0x0520cc81, 0xfffe8000, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00ff00ff, 0x00000000, 0x7fffffff, 0x00057fff, 0x80007fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x80070004, 0xff887ffd, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0xbff019e0, 0x3ff000cf, 0xfff08000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x1ffffffe, 0x00000000, 0x20000fde, 0x0000007f, 0xfff07fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000002, 0xffffffff, 0x80000002, 0x7fffffc0, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x0000003a, 0x00000000, 0x0000003a, 0x001f8000, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x00577fff, 0x80000001, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffff00, 0xffffffff, 0x8020fef0, 0xfff87fe0, 0x7fff0003, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000013, 0x00000000, 0x7c01080f, 0x800003fe, 0x7fff7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffffff, 0x00000000, 0x7fef5577, 0x7fff1c71, 0x0003800f, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00003a28, 0x00000000, 0x7f843c56, 0x00077f80, 0x8003800f, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x1fe3fff9, 0x7ffd1fe0, 0x80007fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffffce35, 0xffffffff, 0x9248ee2d, 0x8000fc01, 0x00049249, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0x8002d5be, 0x7fff0260, 0xffd37fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xffff0002, 0x00007fff, 0x00010c61, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffff8d, 0xffffffff, 0xf0069bc5, 0x8004ffff, 0x8e38f007, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000007, 0xffffffff, 0x80000000, 0xff70ff54, 0xff70ff54, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7fff7fff, 0x7fff7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xff3744f1, 0xffffffff, 0xff28425b, 0x80000329, 0x03530006, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffff7ffd, 0xffffffff, 0x80011223, 0xfe847fff, 0x7fffffdb, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000437, 0xffffffff, 0xf47cd219, 0x7fff136e, 0x49240069, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xf4b2f5c7, 0xffffffff, 0xb551a685, 0xe01fe070, 0x8000803f, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffff0001, 0x80008000, 0x7fff8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000072, 0x00000000, 0x3fa11ff2, 0x7fc00000, 0xc8f8c03f, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7ffffff9, 0x00000000, 0x4047f7f9, 0x00007f80, 0x3ff8fee5, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x80001ba0, 0xfff0fc9f, 0x000000dd, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x000149e8, 0xffffffff, 0xf89b5920, 0xffff0766, 0x7fff0036, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x60209fb9, 0xf0017fff, 0x1fe00003, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x400877cf, 0x3ff8fff8, 0xff7e7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0000f801, 0xc0012492, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0xc376fd80, 0x8000f8fb, 0x3fc03ff8, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffffc00a, 0xffffffff, 0xdf510168, 0x7fff7fff, 0x00b31ffc, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x0000ffff, 0xffffffff, 0xf8145a0f, 0xfe338005, 0xf8130003, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffd65ca2, 0xffffffff, 0xffd65ca2, 0x00010000, 0x00010000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00017b63, 0xffffffff, 0xc0187b43, 0xc007fff0, 0x7fff8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xfb740918, 0x00007fff, 0x048c7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x0024c304, 0x00000000, 0x0024d04e, 0xff430000, 0x80000009, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x000001bc, 0x0000ff91, 0x0002000f, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffffff, 0xffffffff, 0x8001e809, 0x7fff0003, 0x03fe7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x004281fc, 0x00000000, 0x004281fc, 0x00000000, 0x00001efe, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x03860040, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x60037fe7, 0x7ffa0000, 0x00001ffe, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000006, 0xffffffff, 0x80000000, 0x800500b2, 0x33330000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffbf8006, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7ffffffe, 0x00000000, 0x7fffffff, 0x00003fe0, 0xfffc9249, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xe0000003, 0xffffffff, 0xffe0c041, 0x00047fff, 0xe01f0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xc03f0000, 0x3ffc8001, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7ffeffff, 0x80000000, 0x7fffffff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x1c71c71c, 0x00000000, 0x1c55e79e, 0xc003ffdf, 0x807f000a, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x007c8000, 0xfffae001, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xf8000003, 0xffffffff, 0x80000000, 0x00008000, 0x8000fffe, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x7ffffffb, 0x00000000, 0x7ffffffb, 0x8000f007, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x1ffffff8, 0x00000000, 0x23fdfff8, 0x8000fc2f, 0x000003fe, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x1ffffff8, 0x00000000, 0x2123fb68, 0x00008002, 0x01243ff8, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffff8, 0xffffffff, 0xfffffff8, 0xf7b90000, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffff80, 0x00000000, 0x7ffaaa20, 0xfffcaaaa, 0xfffcaaaa, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x000001ad, 0xffffffff, 0xfc994b21, 0xf0f0fffd, 0x3ffee30c, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0xfff8000e, 0x00078000, 0x7fff7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x02e6cef6, 0x00000000, 0x02e8244e, 0x00000003, 0xc71cfff3, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xffacf75a, 0xffffffff, 0xffacf264, 0x007f0000, 0xc0010005, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000195, 0xffffffff, 0x8400f995, 0x7fff7fff, 0x7ffffc01, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xc000001f, 0x00000000, 0x3f6ee63d, 0xf8037fff, 0x8000f6fb, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffc0, 0x00000000, 0x7fffffff, 0xfffa7fff, 0xc01fdb6d, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x003fff80, 0x7fff0038, 0x0000ffc0, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x01563ffc, 0x80008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000c4a, 0x00000000, 0x00000c4a, 0x00000000, 0xfff6004f, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xffefffca, 0x8000ffff, 0xffe5fff0, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xee8c0000, 0x0000ee8c, 0x80008000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7f7ff9f3, 0xfff5ff80, 0x8001ffae, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00780017, 0x00003ffe, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xb6db8000, 0xf77cfdec, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x80000001, 0xffffffff, 0x80000000, 0x80000000, 0x8003800f, 0x000e0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7fff0000, 0x8000aaaa, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffff68f, 0x00000000, 0x0040f487, 0x00410000, 0x00318004, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xffffff00, 0xffffffff, 0xfff8ff0e, 0x7fffc00f, 0x00000007, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x07fffffc, 0x00000000, 0x07fffffc, 0xffc0fec4, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x0f0f0f0f, 0x00000000, 0x0ef00f4d, 0x7ffffffa, 0x0000001f, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffffb, 0xffffffff, 0x8e75fd13, 0x80068e38, 0x8000003e, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xfffffe6f, 0x00000000, 0x0003e1df, 0x1c717ffc, 0xfffdfffc, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xc000000f, 0xffffffff, 0xc13a92c1, 0x92490000, 0x8000016f, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffa79b42, 0xffffffff, 0xffa79b42, 0xf0d9027c, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffc0, 0x00000000, 0x7fffac6e, 0xffd30000, 0x7fffff13, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x00c6f801, 0x7fff8000, 0x000e0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000006, 0xffffffff, 0x8001fffe, 0x00020000, 0x000d8002, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xff1a274e, 0x0004fffa, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x35e594be, 0x00000000, 0x35e44320, 0xfff9e38e, 0xfffef003, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, 0x03fe0000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0xf1c71c70, 0x8e388000, 0x00007fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x000058b2, 0x00000000, 0x000058b2, 0x00000000, 0x7ffffffc, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xfffffffc, 0x00000000, 0x00012494, 0x00000004, 0xdb6d3ff8, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff33ff8, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xff7b8000, 0x7fffc007, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x99999999, 0xffffffff, 0x98c19e85, 0x8000005a, 0x7ff9ff82, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffffff, 0x00000000, 0x07e3ffff, 0x8000ffe8, 0x800007fc, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xcccccccc, 0xffffffff, 0xc93f8e2c, 0x0ffcfffc, 0xffbb1c71, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x002feb2d, 0x00000000, 0x002feb2d, 0x00000000, 0x0002e003, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xff8d2fc9, 0x00000000, 0x3f91e89f, 0x38e37fff, 0xc001fff2, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7fffffc0, 0xf18c7fc0, 0x000e0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xffa6892b, 0xffffffff, 0x8025892b, 0x807f0000, 0x8e388000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x07fef002, 0xfffa7fff, 0xf8010000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x0046fd8a, 0x8005800f, 0xfffc004b, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000007, 0xffffffff, 0xbffe0007, 0xfff58000, 0x3ffe0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00ff00ff, 0xffffffff, 0xebe2169b, 0xfe877fff, 0x151dfff9, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xf8000003, 0x00000000, 0x3da574b7, 0x7fff7fff, 0x3a5a8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x8000003f, 0xffffffff, 0x80000000, 0x00008000, 0xfe2f1ed8, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xfecda9e4, 0xfd99e01f, 0xfd99e01f, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x001fa337, 0xffffffff, 0x99c43cc5, 0x99993333, 0xffe38000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00002718, 0xfffdf0f0, 0x00000684, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfeaf28c5, 0xffffffff, 0xfeaf29b9, 0x0000003d, 0xfffec040, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x1a6b4c3a, 0x00000000, 0x7fffffff, 0x1ffc7ffc, 0x80008000, 0x000e0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x0000007f, 0xffffffff, 0xff02027b, 0x7fff007f, 0x7fff007f, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7fffffed, 0xfffec00f, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7ffffffc, 0x00000000, 0x40087fec, 0x10207fff, 0x3ff80000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x800f7fff, 0x7fff0002, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7ffffffb, 0x00017f80, 0x00000002, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000001, 0x00000000, 0x7ffc7c8d, 0x8006fff9, 0x3fc07fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000001, 0x00000000, 0x1ffd8009, 0xc0018000, 0x00003ffc, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x0001bfcf, 0xffffffff, 0xffe25ecd, 0x08f58000, 0x000201dd, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x80000006, 0x00000000, 0x00257906, 0xff3b8005, 0x7fff1c3f, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x000004d5, 0x00000000, 0x0000052d, 0xfffc0000, 0x8000000b, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000005, 0xffffffff, 0x81873507, 0x99998007, 0x000801df, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfff441cd, 0x00000000, 0x7ff2c24b, 0xffff7fff, 0x8000c03f, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x07fffffc, 0x00000000, 0x07ffe1de, 0x00000f0f, 0x00010000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00bfba7e, 0xffffffff, 0xc0d3399e, 0x00007ff9, 0x3ff08000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xe0000001, 0xffffffff, 0xc0115f81, 0x8001ff9f, 0x12a3e003, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x24924924, 0x00000000, 0x23e14906, 0xff4fffff, 0xfff18000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fb91de1, 0xfff000ff, 0x1c718e38, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffd, 0xffffffff, 0xf80001fd, 0x8000ff00, 0xfc01f808, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffff0, 0xffffffff, 0x807efff0, 0x8001807f, 0x80000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xfffffffa, 0xf7f30001, 0x00030000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x1ffffffe, 0x00000000, 0x3fee352e, 0x7fff1889, 0x0037e007, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffffc, 0xffffffff, 0xfff700fc, 0x7fe0fffb, 0x80000004, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0000fffc, 0xfffc7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000005, 0x00000000, 0x00021f17, 0xfff3f007, 0x00110000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xe885e01f, 0xff007fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffff0, 0xffffffff, 0xf0081fe0, 0xaaaa0ff8, 0x7fff0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x07fffffe, 0x00000000, 0x07fffffe, 0x00000f0f, 0x000000ff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x0000001f, 0xffffffff, 0x8000c865, 0x03b67fff, 0x7fff002a, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffe6838, 0xffffffff, 0xffff6738, 0xffff3fc0, 0xffff3fc0, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000006, 0xffffffff, 0x801a2210, 0xffcf8000, 0x800f1d15, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffe0, 0x00000000, 0x6ffb6e10, 0xedfb00f4, 0x00008e38, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00050765, 0x00000000, 0x0004e76b, 0xffff0000, 0xfd81f003, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x92492492, 0xffffffff, 0x9249248e, 0xfffefe80, 0x0000ffff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x0001554b, 0x00000000, 0x0001554b, 0x00000000, 0x801f8004, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffff80, 0x00000000, 0x7fffffff, 0xfffe7fff, 0x80018000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7ff801a4, 0x0ffe7fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x0000619e, 0xffffffff, 0x80000000, 0x7fff6666, 0x7fff6666, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x0014c26f, 0x00000000, 0x3fd4c26f, 0x00008000, 0x3fc08000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7ffffffd, 0x00000000, 0x7fffffff, 0x8000039d, 0x0ba63ffc, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80027fe2, 0x00050000, 0x0000c003, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffeccf6f, 0x00000000, 0x0384c83f, 0x8000fc68, 0x7fff0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xf0000007, 0xffffffff, 0xf78d038d, 0xef13f803, 0x7ffcfcb3, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00000006, 0x00000000, 0x007ef232, 0xfffa8000, 0x007ffed9, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffc64a, 0x00000000, 0x0b605896, 0xffc6e38e, 0x3333ff98, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x7ffd0000, 0x7fff8000, 0xfffe8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffffd, 0x00000000, 0x7ff8000b, 0x8e387fff, 0x80070000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xfffdaaaa, 0x7fff7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000003, 0x00000000, 0x10113daf, 0x7ffa7ff0, 0xffedf001, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffff0, 0xffffffff, 0xff990658, 0xfffcfcc8, 0xf001ffff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000156, 0x00000000, 0x0002ac06, 0x8e380000, 0x7fff0003, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00338e2c, 0x38e371c7, 0xffc60000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xc71c71c7, 0xffffffff, 0xc7e771c7, 0xf00700cb, 0x80000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x000000e2, 0xffffffff, 0xc6b372a8, 0x7fffff96, 0x800038e3, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xffffff9a, 0x00000000, 0x0ffbff9a, 0x00040ffc, 0x80000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffff3bd, 0x00000000, 0x7fe08db3, 0x00037fe0, 0x8000e657, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xffffff28, 0xffffffff, 0xffffff28, 0xffd2ffd9, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x1ee224ec, 0x00000000, 0x1ee224ec, 0x00008000, 0x00007fff, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000005, 0xffffffff, 0x80000000, 0x00000091, 0x018c0000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffffe, 0xffffffff, 0xf99cead0, 0x66660005, 0xfda307fc, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffc072f, 0xffffffff, 0xfffc072f, 0x00000000, 0x3ff8cccc, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xef2025f7, 0x00000000, 0x08bd266b, 0x001d8000, 0x199dfffe, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01267ffe, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x000007fc, 0x000007fc, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xd46c2ef6, 0x00697fff, 0x2b940031, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xf0d9ff06, 0x801f8000, 0xf0d60004, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xc0000007, 0xffffffff, 0x8cceccdf, 0x00038007, 0xcccc0000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7ffce5c9, 0xffff1ff0, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x0007fff1, 0x7ff90000, 0x7ff87fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0xbfe1d34c, 0x021e3fc0, 0x8000f803, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x029b31c9, 0x00000000, 0x069d31c9, 0x03ea0018, 0x80008000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xff680130, 0x0001ff68, 0x80010000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffb77, 0xffffffff, 0xfffffb77, 0xf0030000, 0xff280000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x0018cfeb, 0x00000000, 0x0015d00f, 0x801ffffa, 0xc0030000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000192, 0x00000000, 0x000b00f8, 0x71c7fff5, 0x7ff90000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x009d026e, 0x00000000, 0x009304c6, 0x0000c00f, 0xffec8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00029e0d, 0x00000000, 0x018d9e0d, 0x80008000, 0x018b0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xfffffe7c, 0xffffffff, 0xe394a934, 0x0000c00f, 0xc71c0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffffe, 0x00000000, 0x0e27f90a, 0x7fff38e3, 0xe01f0003, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x6db6db6d, 0x00000000, 0x6db6db6d, 0x8000edab, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x8007c010, 0x0001fff8, 0x7ffd1fe0, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000003, 0x00000000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x0000124e, 0xffffffff, 0xf8042246, 0x07fc6db6, 0x00007fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x1ffec002, 0x7fff0000, 0x7f80e001, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x0080d77c, 0xffffffff, 0x8080d7b9, 0x000f8000, 0x8000fffe, 0x000e0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80370000, 0x00000037, 0x80004924, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7c2d07a5, 0x800103d3, 0x7fff0000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x00000000, 0x7ffff001, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0x80000000, 0x80030ff8, 0x7fff801f, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7ffffffb, 0x00000000, 0x7e640669, 0x0001c001, 0xfcca7fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x07fffffc, 0xffffffff, 0x8801a0b5, 0x8000fff4, 0x115d8000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xe8653084, 0xffffffff, 0xc3d379a8, 0x24920000, 0x04367fff, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x0006062c, 0x00000000, 0x0006062c, 0x803f0030, 0x00000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffa83, 0xffffffff, 0x8006fa77, 0x03fe7fff, 0x7ffa0000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0000fff8, 0xfffdff35, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x0000000a, 0xffffffff, 0xfffe000a, 0x0018fffe, 0x80000000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffffffe9, 0xffffffff, 0xf2fbffe9, 0xf2fcffe2, 0x00008000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffff0, 0x00000000, 0x08536eec, 0x3ff07fff, 0xf7aefffd, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffffd, 0xffffffff, 0x8e39e38b, 0x7fff0000, 0xcebf71c7, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x001435cb, 0x00000000, 0x001535eb, 0xffff0006, 0xffe87f80, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffff76c, 0x00000000, 0x0c1681b0, 0x8000db6d, 0x2d96ff10, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xfffe0000, 0x7fff7ffd, 0x000e0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7ffc0007, 0x7fffe2b6, 0x00000004, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x03fffffe, 0x00000000, 0x03f6bb8e, 0x05b4fff7, 0x80000006, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00070000, 0x00070000, 0x000f0000, 0x000f0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xfb8108fe, 0x7fff0000, 0xfffd047f, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffffb, 0x00000000, 0x7ffe4007, 0x7ffff001, 0xfffa8000, 0x000e0000, 0x000e0000 + dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x000002f4, 0xffffffff, 0x8676a8d4, 0x80007ff9, 0xf9908007, 0x000f0000, 0x000f0000 + + pass + .end DIAG diff --git a/sim/testsuite/mips/sanity.s b/sim/testsuite/mips/sanity.s new file mode 100644 index 0000000..74551ed --- /dev/null +++ b/sim/testsuite/mips/sanity.s @@ -0,0 +1,20 @@ +# mips test sanity, expected to pass. +# mach: all +# as: -mabi=eabi +# ld: -N -Ttext=0x80010000 +# output: *\\npass\\n + + .include "testutils.inc" + + setup + + .set noreorder + + .ent DIAG +DIAG: + + writemsg "Sanity is good!" + + pass + + .end DIAG diff --git a/sim/testsuite/mips/testutils.inc b/sim/testsuite/mips/testutils.inc new file mode 100644 index 0000000..a0fcd0a --- /dev/null +++ b/sim/testsuite/mips/testutils.inc @@ -0,0 +1,150 @@ +# MIPS simulator testsuite utility functions. +# Copyright (C) 2004-2021 Free Software Foundation, Inc. +# Contributed by Chris Demetriou of Broadcom Corporation. +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . */ + + +# $1, $4, $5, %6, are used as temps by the macros defined here. + + .macro writemsg msg + la $5, 901f + li $6, 902f - 901f + .data +901: .ascii "\msg\n" +902: + .previous + .set push + .set noreorder + jal _dowrite + li $4, 0 + .set pop + .endm + + + # The MIPS simulator uses "break 0x3ff" as the code to exit, + # with the return value in $4 (a0). + .macro exit rc + li $4, \rc + break 0x3ff + .endm + + + .macro setup + + .global _start + .global __start + .ent _start +_start: +__start: + .set push + .set noreorder + j DIAG + nop + .set pop + .end _start + + .global _fail + .ent _fail +_fail: + writemsg "fail" + exit 1 + .end _fail + + .global _pass + .ent _pass +_pass: + writemsg "pass" + exit 0 + .end _pass + + # The MIPS simulator can use multiple different monitor types, + # so we hard-code the simulator "write" reserved instruction opcode, + # rather than jumping to a vector that invokes it. The operation + # expects RA to point to the location at which to continue + # after writing. + .global _dowrite + .ent _dowrite +_dowrite: + # Write opcode (reserved instruction). See sim_monitor and its + # callers in sim/mips/interp.c. + .word 0x00000039 | ((8 << 1) << 6) + .end _dowrite + + .endm # setup + + + .macro pass + .set push + .set noreorder + j _pass + nop + .set pop + .endm + + + .macro fail + .set push + .set noreorder + j _fail + nop + .set pop + .endm + + + .macro load32 reg, val + li \reg, \val + .endm + + + .macro load64 reg, val + dli \reg, \val + .endm + + + .macro loadaddr reg, addr + la \reg, \addr + .endm + + + .macro checkreg reg, expreg + .set push + .set noat + .set noreorder + beq \expreg, \reg, 901f + nop + fail +901: + .set pop + .endm + + + .macro check32 reg, val + .set push + .set noat + load32 $1, \val + checkreg \reg, $1 + .set pop + .endm + + + .macro check64 reg, val + .set push + .set noat + load64 $1, \val + checkreg \reg, $1 + .set pop + .endm diff --git a/sim/testsuite/mips/utils-dsp.inc b/sim/testsuite/mips/utils-dsp.inc new file mode 100644 index 0000000..936f691 --- /dev/null +++ b/sim/testsuite/mips/utils-dsp.inc @@ -0,0 +1,443 @@ +# MIPS DSP ASE simulator testsuite utility functions. +# Copyright (C) 2005-2021 Free Software Foundation, Inc. +# Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu. +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . */ + +# $4, $5, $6, $7, $ac0, $ac1, $ac2, $ac3 are used as temps by the macros +# defined here. + + # If a != b, jump to _fail. + # Otherwise, fall through. + .macro dsp_assert a, b + beq \a, \b, 1f + nop + j _fail + nop +1: + .endm + + # Set dsp control register <= crin + # Check if d == (inst ?, s, t) + # Check if crout == dsp control register + .macro dspck_dstio inst, d, s, t, crin, crout + li $4, \crin + wrdsp $4 + li $4, \s + li $5, \t + \inst $6, $4, $5 + li $7, \d + dsp_assert $6, $7 + li $4, \crout + rddsp $5 + dsp_assert $4, $5 + .endm + + # Set dsp control register <= crin + # (inst s, t) + # Check if crout == dsp control register + .macro dspck_stio inst, s, t, crin, crout + li $4, \crin + wrdsp $4 + li $4, \s + li $5, \t + \inst $4, $5 + li $4, \crout + rddsp $5 + dsp_assert $4, $5 + .endm + + # Set dsp control register <= crin + # Check if d == (inst ?, s, t) + .macro dspck_dsti inst, d, s, t, crin + li $4, \crin + wrdsp $4 + li $4, \s + li $5, \t + \inst $6, $4, $5 + li $7, \d + dsp_assert $6, $7 + .endm + + # Set dsp control register <= crin + # Check if tou == (inst tin, s) + .macro dspck_tsi inst, tou, tin, s, crin + li $4, \crin + wrdsp $4 + li $4, \s + li $5, \tin + \inst $5, $4 + li $6, \tou + dsp_assert $5, $6 + .endm + + # Set dsp control register <= crin + # Check if d == (inst ?, imm) + # Check if crout == dsp control register + .macro dspck_dIio inst, d, imm, crin, crout + li $4, \crin + wrdsp $4 + \inst $5, \imm + li $6, \d + dsp_assert $5, $6 + li $4, \crout + rddsp $5 + dsp_assert $4, $5 + .endm + + # Set dsp control register <= crin + # Check if d == (inst ?, s) + # Check if crout == dsp control register + .macro dspck_dsio inst, d, s, crin, crout + li $4, \crin + wrdsp $4 + li $4, \s + \inst $6, $4 + li $7, \d + dsp_assert $6, $7 + li $4, \crout + rddsp $5 + dsp_assert $4, $5 + .endm + + # Set dsp control register <= crin + # Check if d == (inst ?, t, sa) + # Check if crout == dsp control register + .macro dspck_dtsaio inst, d, t, sa, crin, crout + li $4, \crin + wrdsp $4 + li $4, \t + \inst $6, $4, \sa + li $7, \d + dsp_assert $6, $7 + li $4, \crout + rddsp $5 + dsp_assert $4, $5 + .endm + + # Set dsp control register <= crin + # Check if d == (inst ?, t, sa) + .macro dspck_dtsai inst, d, t, sa, crin + li $4, \crin + wrdsp $4 + li $4, \t + \inst $6, $4, \sa + li $7, \d + dsp_assert $6, $7 + .endm + + # Set dsp control register <= crin + # Set $ac3 <= {hiin, loin} + # (inst $ac3, s, t) + # Check if {hiou, loou} == $ac3 + # Check if (crout & 0x80000) == (dsp control register & 0x80000) + .macro dspck_astio inst, hiin, loin, hiou, loou, s, t, crin, crout + li $4, \crin + wrdsp $4 + li $4, \hiin + mthi $4, $ac3 + li $4, \loin + mtlo $4, $ac3 + li $4, \s + li $5, \t + \inst $ac3, $4, $5 + li $4, \hiou + mfhi $5, $ac3 + dsp_assert $4, $5 + li $4, \loou + mflo $5, $ac3 + dsp_assert $4, $5 + li $4, \crout + and $4, $4, 0x80000 + rddsp $5 + and $5, $5, 0x80000 + dsp_assert $4, $5 + .endm + + # Set dsp control register <= crin + # Set $ac1 <= {hi, lo} + # Check if t == (inst ? $ac1, sa) + # Check if crout == dsp control register + .macro dspck_atsaio inst, hi, lo, t, sa, crin, crout + li $4, \crin + wrdsp $4 + li $4, \hi + mthi $4, $ac1 + li $4, \lo + mtlo $4, $ac1 + \inst $5, $ac1, \sa + li $6, \t + dsp_assert $5, $6 + li $4, \crout + rddsp $5 + dsp_assert $4, $5 + .endm + + # Set dsp control register <= crin + # Set acc <= {hiin, loin} + # (inst acc, s, t) + # Check if {hiou, loou} == acc + # Check if (crout & 0x80000) == (dsp control register & 0x80000) + .macro dspckacc_astio inst, acc, hiin, loin, hiou, loou, s, t, crin, crout + li $4, \crin + wrdsp $4 + li $4, \hiin + mthi $4, \acc + li $4, \loin + mtlo $4, \acc + li $4, \s + li $5, \t + \inst \acc, $4, $5 + li $4, \hiou + mfhi $5, \acc + dsp_assert $4, $5 + li $4, \loou + mflo $5, \acc + dsp_assert $4, $5 + li $4, \crout + and $4, $4, 0x80000 + rddsp $5 + and $5, $5, 0x80000 + dsp_assert $4, $5 + .endm + + # Set dsp control register <= crin + # Set $ac1 <= {hi, lo} + # Check if t == (inst ? $ac1, s) + # Check if crout == dsp control register + .macro dspck_atsio inst, hi, lo, t, s, crin, crout + li $4, \crin + wrdsp $4 + li $4, \hi + mthi $4, $ac1 + li $4, \lo + mtlo $4, $ac1 + li $4, \s + \inst $5, $ac1, $4 + li $6, \t + dsp_assert $5, $6 + li $4, \crout + rddsp $5 + dsp_assert $4, $5 + .endm + + # Set dsp control register <= (crin & crinmask) + # Set $ac2 <= {hi, lo} + # Check if t == (inst ? $ac2, size) + # Check if (crout & croutmask) == (dsp control register & croutmask) + .macro dspck_tasiimom inst, hi, lo, t, size, crin, crinmask, crout, croutmask + li $4, \crin + and $4, \crinmask + wrdsp $4 + li $4, \hi + mthi $4, $ac2 + li $4, \lo + mtlo $4, $ac2 + \inst $5, $ac2, \size + li $6, \t + dsp_assert $5, $6 + li $4, \crout + and $4, \croutmask + rddsp $5 + and $5, \croutmask + dsp_assert $4, $5 + .endm + + # Set dsp control register <= (crin & crinmask) + # Set $ac2 <= {hi, lo} + # Check if t == (inst ? $ac2, size) + .macro dspck_tasiim inst, hi, lo, t, size, crin, crinmask + li $4, \crin + and $4, \crinmask + wrdsp $4 + li $4, \hi + mthi $4, $ac2 + li $4, \lo + mtlo $4, $ac2 + \inst $5, $ac2, \size + li $6, \t + dsp_assert $5, $6 + .endm + + # Set dsp control register <= (crin & crinmask) + # Set $ac2 <= {hi, lo} + # Check if t == (inst ? $ac2, s) + # Check if (crout & croutmask) == (dsp control register & croutmask) + .macro dspck_tasimom inst, hi, lo, t, s, crin, crinmask, crout, croutmask + li $4, \crin + and $4, \crinmask + wrdsp $4 + li $4, \hi + mthi $4, $ac2 + li $4, \lo + mtlo $4, $ac2 + li $4, \s + \inst $5, $ac2, $4 + li $6, \t + dsp_assert $5, $6 + li $4, \crout + and $4, \croutmask + rddsp $5 + and $5, \croutmask + dsp_assert $4, $5 + .endm + + # Set dsp control register <= (crin & crinmask) + # Set $ac2 <= {hi, lo} + # Check if t == (inst ? $ac2, s) + .macro dspck_tasim inst, hi, lo, t, s, crin, crinmask + li $4, \crin + and $4, \crinmask + wrdsp $4 + li $4, \hi + mthi $4, $ac2 + li $4, \lo + mtlo $4, $ac2 + li $4, \s + \inst $5, $ac2, $4 + li $6, \t + dsp_assert $5, $6 + .endm + + # Set dsp control register <= crin + # Set $ac0 <= {hi, lo} + # (inst $ac0, shift) + # Check if $ac0 == {hio, loo} + # Check if crout == dsp control register + .macro dspck_asaio inst, hi, lo, hio, loo, shift, crin, crout + li $4, \crin + wrdsp $4 + li $4, \hi + mthi $4, $ac0 + li $4, \lo + mtlo $4, $ac0 + \inst $ac0, \shift + mfhi $5, $ac0 + li $6, \hio + dsp_assert $5, $6 + mflo $5, $ac0 + li $6, \loo + dsp_assert $5, $6 + li $4, \crout + rddsp $5 + dsp_assert $4, $5 + .endm + + # Set dsp control register <= crin + # Set $ac0 <= {hi, lo} + # (inst $ac0, s) + # Check if $ac0 == {hio, loo} + # Check if crout == dsp control register + .macro dspck_asio inst, hi, lo, hio, loo, s, crin, crout + li $4, \crin + wrdsp $4 + li $4, \hi + mthi $4, $ac0 + li $4, \lo + mtlo $4, $ac0 + li $4, \s + \inst $ac0, $4 + mfhi $5, $ac0 + li $6, \hio + dsp_assert $5, $6 + mflo $5, $ac0 + li $6, \loo + dsp_assert $5, $6 + li $4, \crout + rddsp $5 + dsp_assert $4, $5 + .endm + + # Set dsp control register <= crin + # Set $ac3 <= {hi, lo} + # Check if s == (inst ? $ac3) + # Check if $ac3 == {hio, loo} + # Check if crout == dsp control register + .macro dspck_saio inst, hi, lo, hio, loo, s, crin, crout + li $4, \crin + wrdsp $4 + li $4, \hi + mthi $4, $ac3 + li $4, \lo + mtlo $4, $ac3 + li $5, \s + \inst $5, $ac3 + mfhi $5, $ac3 + li $6, \hio + dsp_assert $5, $6 + mflo $5, $ac3 + li $6, \loo + dsp_assert $5, $6 + li $4, \crout + rddsp $5 + dsp_assert $4, $5 + .endm + + # Set dsp control register <= crin + # (wrdsp s, m) + # Check if crout == dsp control register + .macro dspck_wrdsp s, m, crin, crout + li $4, \crin + wrdsp $4 + li $5, \s + wrdsp $5, \m + li $6, \crout + rddsp $7 + dsp_assert $6, $7 + .endm + + # Set dsp control register <= crin + # Check if d == (rddsp ?, m) + .macro dspck_rddsp d, m, crin + li $4, \crin + wrdsp $4 + rddsp $5, \m + li $6, \d + dsp_assert $5, $6 + .endm + + # Check if d == (inst i(b)) + .macro dspck_load inst, d, i, b + li $4, \i + la $5, \b + \inst $6, $4($5) + li $7, \d + dsp_assert $6, $7 + .endm + + # Set dsp control register <= crin + # Check if bposge32 is taken or not as expected in r + # (1 => taken, 0 => not taken) + .macro dspck_bposge32 crin, r + li $4, \crin + wrdsp $4 + li $5, 1 + bposge32 1f + nop + li $5, 0 +1: + li $6, \r + dsp_assert $5, $6 + .endm + + # Check if tou == (inst tin, s) + .macro dspck_tsimm inst, tou, tin, s, sa + li $4, \s + li $5, \tin + \inst $5, $4, \sa + li $6, \tou + dsp_assert $5, $6 + .endm diff --git a/sim/testsuite/mips/utils-fpu.inc b/sim/testsuite/mips/utils-fpu.inc new file mode 100644 index 0000000..1cba87a --- /dev/null +++ b/sim/testsuite/mips/utils-fpu.inc @@ -0,0 +1,104 @@ +# MIPS simulator testsuite FPU utility functions. +# Copyright (C) 2004-2021 Free Software Foundation, Inc. +# Contributed by Chris Demetriou of Broadcom Corporation. +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . */ + + .macro enable_fpu fr + mfc0 $20, $12 + or $20, $20, (1 << 29) | (\fr << 26) + mtc0 $20, $20 + .endm + + ### + ### Data movement macros + ### + + .macro ld_fp_df r, v + .data +1: .double \v + .previous + ldc1 \r, 1b + .endm + + .macro ld_fp_di r, v + .data +1: .dword \v + .previous + ldc1 \r, 1b + .endm + + .macro ld_fp_sf r, v + .data +1: .float \v + .previous + lwc1 \r, 1b + .endm + + .macro ld_fp_si r, v + .data +1: .word \v + .previous + lwc1 \r, 1b + .endm + + + ### + ### FP condition code manipulation macros + ### + + .macro clrset_fp_cc clr, set + cfc1 $20, $31 + or $20, $20, (((\clr & 0xfe) << 24) | ((\clr & 0x01) << 23)) + xor $20, $20, (((\clr & 0xfe) << 24) | ((\clr & 0x01) << 23)) + or $20, $20, (((\set & 0xfe) << 24) | ((\set & 0x01) << 23)) + ctc1 $20, $31 + .endm + + .macro clr_fp_cc clr + clrset_fp_cc \clr, 0 + .endm + + .macro set_fp_cc set + clrset_fp_cc 0, \set + .endm + + .macro get_fp_cc r + .set push + .set noat + cfc1 $1, $31 + srl $1, $1, 23 + andi \r, $1, 0x1fc + andi $1, $1, 0x1 + srl \r, \r, 1 + or \r, \r, $1 + .set pop + .endm + + .macro ck_fp_cc v + get_fp_cc $20 + xori $20, $20, \v + bnez $20, _fail + nop + .endm + + .macro ckm_fp_cc v, mask + get_fp_cc $20 + xori $20, $20, \v + andi $20, $20, \mask + bnez $20, _fail + nop + .endm diff --git a/sim/testsuite/mips/utils-mdmx.inc b/sim/testsuite/mips/utils-mdmx.inc new file mode 100644 index 0000000..62634ef --- /dev/null +++ b/sim/testsuite/mips/utils-mdmx.inc @@ -0,0 +1,71 @@ +# MIPS simulator testsuite MDMX utility functions. +# Copyright (C) 2004-2021 Free Software Foundation, Inc. +# Contributed by Chris Demetriou of Broadcom Corporation. +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . */ + + .include "utils-fpu.inc" + + ### + ### Shared macros + ### + + # Enable MDMX: enable the FPU w/ FR=1, then set Status.MX + .macro enable_mdmx + enable_fpu 1 + mfc0 $20, $12 + or $20, $20, (1 << 24) + mtc0 $20, $12 + .endm + + + ### + ### .OB-format macros + ### + + .macro ld_ob r, v + .data +1: .dword \v + .previous + ldc1 \r, 1b + .endm + + .macro ck_ob r, v + .data +1: .dword \v + .previous + dmfc1 $20, \r + ld $21, 1b + bne $20, $21, _fail + nop + .endm + + .macro ld_acc_ob h, m, l + ld_ob $f20, \m + ld_ob $f21, \l + wacl.ob $f20, $f21 + ld_ob $f20, \h + wach.ob $f20 + .endm + + .macro ck_acc_ob h, m, l + rach.ob $f20 + ck_ob $f20, \h + racm.ob $f20 + ck_ob $f20, \m + racl.ob $f20 + ck_ob $f20, \l + .endm diff --git a/sim/testsuite/mn10300/ChangeLog b/sim/testsuite/mn10300/ChangeLog new file mode 100644 index 0000000..d3f8b9d --- /dev/null +++ b/sim/testsuite/mn10300/ChangeLog @@ -0,0 +1,3 @@ +2015-04-05 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/mn10300/allinsn.exp b/sim/testsuite/mn10300/allinsn.exp new file mode 100644 index 0000000..f8431e7 --- /dev/null +++ b/sim/testsuite/mn10300/allinsn.exp @@ -0,0 +1,15 @@ +# mn10300 simulator testsuite + +if [istarget mn10300-*] { + # all machines + set all_machs "mn10300" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/mn10300/pass.s b/sim/testsuite/mn10300/pass.s new file mode 100644 index 0000000..b48fa4c --- /dev/null +++ b/sim/testsuite/mn10300/pass.s @@ -0,0 +1,7 @@ +# check that the sim doesn't die immediately. +# mach: mn10300 + +.include "testutils.inc" + + start + pass diff --git a/sim/testsuite/mn10300/testutils.inc b/sim/testsuite/mn10300/testutils.inc new file mode 100644 index 0000000..6418817 --- /dev/null +++ b/sim/testsuite/mn10300/testutils.inc @@ -0,0 +1,63 @@ +# MACRO: exit + .macro exit nr + mov \nr, d1; + # Trap function 1: exit(). + mov 1, d0; + syscall; + .endm + +# MACRO: pass +# Write 'pass' to stdout and quit + .macro pass + # Trap function 5: write(). + mov 5, d0; + # Use stdout. + mov 1, d1; + # Point to the string. + mov 1f, a0; + mov a0, (12, sp); + # Number of bytes to write. + mov 5, d3; + mov d3, (16, sp); + # Trigger OS trap. + syscall; + exit 0 + .data + 1: .asciz "pass\n" + .endm + +# MACRO: fail +# Write 'fail' to stdout and quit + .macro fail + # Trap function 5: write(). + mov 5, d0; + # Use stdout. + mov 1, d1; + # Point to the string. + mov 1f, a0; + mov a0, (12, sp); + # Number of bytes to write. + mov 5, d3; + mov d3, (16, sp); + # Trigger OS trap. + syscall; + exit 0 + .data + 1: .asciz "fail\n" + .endm + +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .data +.global _stack +_stack: + .rept 8 + .long 0 + .endr + .text +.global _start +_start: + mov _stack, a0; + mov a0, sp; + .endm diff --git a/sim/testsuite/moxie/ChangeLog b/sim/testsuite/moxie/ChangeLog new file mode 100644 index 0000000..d3f8b9d --- /dev/null +++ b/sim/testsuite/moxie/ChangeLog @@ -0,0 +1,3 @@ +2015-04-05 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/moxie/allinsn.exp b/sim/testsuite/moxie/allinsn.exp new file mode 100644 index 0000000..1a6af8b --- /dev/null +++ b/sim/testsuite/moxie/allinsn.exp @@ -0,0 +1,15 @@ +# moxie simulator testsuite + +if [istarget moxie-*] { + # all machines + set all_machs "moxie" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/moxie/pass.s b/sim/testsuite/moxie/pass.s new file mode 100644 index 0000000..4d8e385 --- /dev/null +++ b/sim/testsuite/moxie/pass.s @@ -0,0 +1,7 @@ +# check that the sim doesn't die immediately. +# mach: moxie + +.include "testutils.inc" + + start + pass diff --git a/sim/testsuite/moxie/testutils.inc b/sim/testsuite/moxie/testutils.inc new file mode 100644 index 0000000..dbdcf7c --- /dev/null +++ b/sim/testsuite/moxie/testutils.inc @@ -0,0 +1,46 @@ +# MACRO: exit + .macro exit nr + ldi.l $r0, \nr; + # Trap function 1: exit(). + swi 1; + .endm + +# MACRO: pass +# Write 'pass' to stdout and quit + .macro pass + # Use stdout. + ldi.b $r0, 1; + # Point to the string. + ldi.l $r1, 1f; + # Number of bytes to write. + ldi.s $r2, 5; + # Trap function 5: write(). + swi 5; + exit 0 + .data + 1: .asciz "pass\n" + .endm + +# MACRO: fail +# Write 'fail' to stdout and quit + .macro fail + # Use stdout. + ldi.b $r0, 1; + # Point to the string. + ldi.l $r1, 1f; + # Number of bytes to write. + ldi.s $r2, 5; + # Trap function 5: write(). + swi 5; + exit 0 + .data + 1: .asciz "fail\n" + .endm + +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .text +.global _start +_start: + .endm diff --git a/sim/testsuite/msp430/ChangeLog b/sim/testsuite/msp430/ChangeLog new file mode 100644 index 0000000..cd6b195 --- /dev/null +++ b/sim/testsuite/msp430/ChangeLog @@ -0,0 +1,17 @@ +2020-08-05 Jozef Lawrynowicz + + * mpyull_hwmult.s: New test. + +2020-01-22 Jozef Lawrynowicz + + * rrux.s: New test. + +2016-01-05 Nick Clifton + + * testutils.inc (__pass): Use the LMA addresses of the _passmsg + symbol. + (__fail): Likewise. + +2014-03-10 Mike Frysinger + + * add.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/msp430/add.s b/sim/testsuite/msp430/add.s new file mode 100644 index 0000000..76247ed --- /dev/null +++ b/sim/testsuite/msp430/add.s @@ -0,0 +1,20 @@ +# check that basic add insn works. +# mach: msp430 + +.include "testutils.inc" + + start + + mov #10, r4 + add #23, r4 + cmp #33, r4 + jne 1f + + cmp #32, r4 + jlo 1f + + cmp #34, r4 + jhs 1f + + pass +1: fail diff --git a/sim/testsuite/msp430/allinsn.exp b/sim/testsuite/msp430/allinsn.exp new file mode 100644 index 0000000..affa8ae --- /dev/null +++ b/sim/testsuite/msp430/allinsn.exp @@ -0,0 +1,15 @@ +# msp430 simulator testsuite + +if [istarget msp430-*] { + # all machines + set all_machs "msp430" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/msp430/mpyull_hwmult.s b/sim/testsuite/msp430/mpyull_hwmult.s new file mode 100644 index 0000000..911fa11 --- /dev/null +++ b/sim/testsuite/msp430/mpyull_hwmult.s @@ -0,0 +1,55 @@ +# Test that unsigned widening multiplication of 32-bit operands to produce a +# 64-bit result is simulated correctly, when using 32-bit or F5series hardware +# multiply functionality. +# 0xffff fffc * 0x2 = 0x1 ffff fff8 +# mach: msp430 + +# 32-bit hwmult register addresses +.set MPY32L, 0x0140 +.set MPY32H, 0x0142 +.set OP2L, 0x0150 +.set OP2H, 0x0152 +.set RES0, 0x0154 +.set RES1, 0x0156 +.set RES2, 0x0158 +.set RES3, 0x015A + +# F5series hwmult register addresses +.set MPY32L_F5, 0x04D0 +.set MPY32H_F5, 0x04D2 +.set OP2L_F5, 0x04E0 +.set OP2H_F5, 0x04E2 +.set RES0_F5, 0x04E4 +.set RES1_F5, 0x04E6 +.set RES2_F5, 0x04E8 +.set RES3_F5, 0x04EA + +.include "testutils.inc" + + start + + ; Test 32bit hwmult + MOV.W #2, &MPY32L ; Load operand 1 Low into multiplier + MOV.W #0, &MPY32H ; Load operand 1 High into multiplier + MOV.W #-4, &OP2L ; Load operand 2 Low into multiplier + MOV.W #-1, &OP2H ; Load operand 2 High, trigger MPY + + CMP.W #-8, &RES0 { JNE .L5 + CMP.W #-1, &RES1 { JNE .L5 + CMP.W #1, &RES2 { JNE .L5 + CMP.W #0, &RES3 { JNE .L5 + + ; Test f5series hwmult + MOV.W #2, &MPY32L_F5 + MOV.W #0, &MPY32H_F5 + MOV.W #-4, &OP2L_F5 + MOV.W #-1, &OP2H_F5 + + CMP.W #-8, &RES0_F5 { JNE .L5 + CMP.W #-1, &RES1_F5 { JNE .L5 + CMP.W #1, &RES2_F5 { JNE .L5 + CMP.W #0, &RES3_F5 { JEQ .L6 +.L5: + fail +.L6: + pass diff --git a/sim/testsuite/msp430/rrux.s b/sim/testsuite/msp430/rrux.s new file mode 100644 index 0000000..07fc8d5 --- /dev/null +++ b/sim/testsuite/msp430/rrux.s @@ -0,0 +1,14 @@ +# check that rrux (synthesized as rrc with ZC bit set) works. +# mach: msp430 + +.include "testutils.inc" + + start + + setc ; set the carry bit to ensure ZC bit is obeyed + mov.w #16, r10 + rrux.w r10 + cmp.w #8, r10 + jeq 1f + fail + 1: pass diff --git a/sim/testsuite/msp430/testutils.inc b/sim/testsuite/msp430/testutils.inc new file mode 100644 index 0000000..1ddef23 --- /dev/null +++ b/sim/testsuite/msp430/testutils.inc @@ -0,0 +1,100 @@ +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .text + + # Skip over these inlined funcs. + jmp __start; + + .global __pass + .type __pass, function +__pass: + # Note - we cannot just invoke: + # + # write 1, _passmsg, 5 + # + # here because _passmsg contains the run-time (VMA) address of + # the pass string (probably 0x500) not the load-time (LMA) + # address (probably 0x804c). Normally using the VMA address + # would be the correct thing to do - *if* there was some start + # up code which copied data from LMA to VMA. But we have no + # start up code, so the data still resides at the LMA + # address. Hence we use __romdatastart instead. + # + # Note - we are cheating because the address that we pass to + # "write" should actually be: + # + # __romdatastart + (_passmsg - __datastart) + # + # but the assembler cannot cope with this expression. So we + # cheat and use the fact that we know that _passmsg is the + # first string in the .data section and so (_passmsg - + # __datastart) evaluates to zero. + + write 1, __romdatastart, 5 + exit 0 + + .global __fail + .type __fail, function +__fail: + # Note - see above. + # + # write 1, _failmsg, 5 + # + # This time we use the fact that _passmsg is aligned to a + # 16 byte boundary to work out that (_failmsg - __datastart) + # evaluates to 0x10. + + write 1, __romdatastart + 0x10, 5 + exit 1 + + .data +_passmsg: + .ascii "pass\n" + .align 4 + +_failmsg: + .ascii "fail\n" + .align 4 + + .text + .global __start + .type __start, function +__start: + .endm + +# MACRO: system_call +# Make a libgloss/Linux system call + .macro system_call nr:req + call #(0x180|\nr); + .endm + +# MACRO: exit +# Quit the current test + .macro exit rc:req + mov #\rc, r12 + system_call 1 + .endm + +# MACRO: pass +# Write 'pass' to stdout via syscalls and quit; +# meant for non-OS operating environments + .macro pass + jmp __pass; + .endm + +# MACRO: fail +# Write 'fail' to stdout via syscalls and quit; +# meant for non-OS operating environments + .macro fail + jmp __fail; + .endm + +# MACRO: write +# Just like the write() C function; uses system calls + .macro write fd:req, buf:req, count:req + mov #\fd, r12; + mov #\buf, r13; + mov #\count, r14; + system_call 5 + .endm diff --git a/sim/testsuite/or1k/ChangeLog b/sim/testsuite/or1k/ChangeLog new file mode 100644 index 0000000..f562380 --- /dev/null +++ b/sim/testsuite/or1k/ChangeLog @@ -0,0 +1,46 @@ +2019-06-13 Stafford Horne + + * fpu-unordered.S: New file. + * fpu64a32-unordered.S: New file. + +2019-06-13 Stafford Horne + + * adrp.S: New file. + +2019-06-13 Stafford Horne + + * fpu64a32.S: New file. + +2018-10-05 Stafford Horne + + * div.S: Fix tests to match correct overflow/carry semantics. + * mul.S: Likewise. + +2017-12-12 Peter Gavin + Stafford Horne + + * add.S: New file. + * alltests.exp: New file. + * and.S: New file. + * basic.S: New file. + * div.S: New file. + * ext.S: New file. + * find.S: New file. + * flag.S: New file. + * fpu.S: New file. + * jump.S: New file. + * load.S: New file. + * mac.S: New file. + * mfspr.S: New file. + * mul.S: New file. + * or.S: New file. + * or1k-asm-test-env.h: New file. + * or1k-asm-test-helpers.h: New file. + * or1k-asm-test.h: New file. + * or1k-asm.h: New file. + * or1k-test.ld: New file. + * ror.S: New file. + * shift.S: New file. + * spr-defs.h: New file. + * sub.S: New file. + * xor.S: New file. diff --git a/sim/testsuite/or1k/add.S b/sim/testsuite/or1k/add.S new file mode 100644 index 0000000..2cff73d --- /dev/null +++ b/sim/testsuite/or1k/add.S @@ -0,0 +1,639 @@ +/* Tests instructions l.add, l.addc, l.addi and l.addic. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x00000001);\n +# output: report(0x00000002);\n +# output: report(0x00000003);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000001);\n +# output: report(0x00000002);\n +# output: report(0x00000003);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0xfffffffe);\n +# output: report(0xfffffffd);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x40000000);\n +# output: report(0x3fffffff);\n +# output: report(0x7fffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x40000000);\n +# output: report(0x40000000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xc0000000);\n +# output: report(0xc0000000);\n +# output: report(0x80000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xbfffffff);\n +# output: report(0xbfffffff);\n +# output: report(0x7ffffffe);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x40000000);\n +# output: report(0x40000000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0xfffffffe);\n +# output: report(0xfffffffd);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xbfffffff);\n +# output: report(0xbfffffff);\n +# output: report(0x7ffffffe);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x00000001);\n +# output: report(0x00000002);\n +# output: report(0x00000003);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0xfffffffe);\n +# output: report(0xfffffffd);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x40000000);\n +# output: report(0x3fffffff);\n +# output: report(0x7fffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x40000000);\n +# output: report(0x3fffffff);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x40000000);\n +# output: report(0x40000000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xc0000000);\n +# output: report(0xc0000000);\n +# output: report(0x80000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xc0000000);\n +# output: report(0xbfffffff);\n +# output: report(0x80000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xbfffffff);\n +# output: report(0xbfffffff);\n +# output: report(0x7ffffffe);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x40000000);\n +# output: report(0x40000000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x40000000);\n +# output: report(0x3fffffff);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0xfffffffe);\n +# output: report(0xfffffffd);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xbfffffff);\n +# output: report(0xbfffffff);\n +# output: report(0x7ffffffe);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x00000001);\n +# output: report(0x00000002);\n +# output: report(0x00000003);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000001);\n +# output: report(0x00000002);\n +# output: report(0x00000003);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0x0000fffe);\n +# output: report(0xfffffffd);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x7fff8000);\n +# output: report(0x00007fff);\n +# output: report(0x7fffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x7fffc000);\n +# output: report(0x00004000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x80008000);\n +# output: report(0x00008000);\n +# output: report(0x80000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x80007fff);\n +# output: report(0x00008000);\n +# output: report(0x7fffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x7fffc000);\n +# output: report(0x00004000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0x0000fffe);\n +# output: report(0xfffffffd);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x80007fff);\n +# output: report(0x00008000);\n +# output: report(0x7fffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x00000001);\n +# output: report(0x00000002);\n +# output: report(0x00000003);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0x0000fffe);\n +# output: report(0xfffffffd);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x7fff8000);\n +# output: report(0x00007fff);\n +# output: report(0x7fffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x7fff8000);\n +# output: report(0x00007fff);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x7fffc000);\n +# output: report(0x00004000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000000);\n +# output: report(0x0000ffff);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x80008000);\n +# output: report(0x00008000);\n +# output: report(0x80000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x80007fff);\n +# output: report(0x00008000);\n +# output: report(0x80000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x80007fff);\n +# output: report(0x00008000);\n +# output: report(0x7fffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x7fffc000);\n +# output: report(0x00004000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x7fffc000);\n +# output: report(0x00003fff);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0x0000fffe);\n +# output: report(0xfffffffd);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000000);\n +# output: report(0x0000ffff);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x80007fff);\n +# output: report(0x00008000);\n +# output: report(0x7fffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + STANDARD_TEST_ENVIRONMENT + + .section .exception_vectors + + /* Range exception. */ + .org 0xb00 + + /* The handling is a bit dubious at present. We just patch the + instruction with l.nop and restart. This will go wrong in branch + delay slots. But we don't have those in this test. */ + l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE + PUSH r2 + PUSH r3 + /* Save the address of the instruction that caused the problem. */ + MOVE_FROM_SPR r2, SPR_EPCR_BASE + LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */ + l.sw 0(r2), r3 + POP r3 + POP r2 + l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE + l.rfe + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test l.add */ + + /* Add two small positive numbers */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 1, 2 + + /* The carry flag should be ignored. */ + TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.add, 1, 2 + + /* Add two small negative numbers, which should set the carry flag + but not the overflow flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, -1, -2 + + /* Add two quite large positive numbers. Should set neither the + overflow nor the carry flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, \ + 0x3fffffff + + /* Add two large positive numbers. Should set the overflow, but + not the carry flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, \ + 0x40000000 + + /* Add two quite large negative numbers. Should set the carry, but + not the overflow flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, -1073741824, \ + -1073741824 /* -1073741824 = 0xC0000000 */ + + /* Add two large negative numbers. Should set both the overflow + and carry flags. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xbfffffff, \ + 0xbfffffff + + /* Check that range exceptions are triggered. */ + + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Check that an overflow alone causes a RANGE Exception. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, \ + 0x40000000 + + /* Check that a carry alone does not cause a RANGE Exception. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xffffffff, \ + 0xfffffffe + + /* Check that carry and overflow together cause an exception. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xbfffffff, \ + 0xbfffffff + + CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Test l.addc */ + + /* Add two small positive numbers */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 1, 2 + + /* Add two small negative numbers. Sets the carry flag but not the + overflow flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1, -2 + + /* Add two quite large positive numbers. Should set neither the + overflow nor the carry flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, \ + 0x3fffffff + + /* Add two quite large positive numbers with a carry in. Should + set the overflow but not the carry flag. */ + TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x40000000, \ + 0x3fffffff + + /* Add two large positive numbers. Should set the overflow, but + not the carry flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, \ + 0x40000000 + + /* Add the largest unsigned value to zero with a carry. This + potentially can break a simplistic test for carry that does not + consider the carry flag properly. Do it both ways around. */ + TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, -1, 0 + TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0, -1 + + /* Add two quite large negative numbers. Should set the carry, but + not the overflow flag. Here -1073741824 is 0xC0000000. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1073741824, \ + -1073741824 + + /* Add two quite large negative numbers that would overflow, with a + carry that just avoids the overflow. Should set the carry, but + not the overflow flag. Here -1073741824 is 0xC0000000 and + -1073741825 is 0xBFFFFFFF. */ + TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, -1073741824, \ + -1073741825 + + /* Add two large negative numbers. Should set both the overflow + and carry flags. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1073741825, \ + -1073741825 + + /* Check that range exceptions are triggered. */ + + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Check that an overflow alone causes a RANGE Exception, even when + it is the carry that causes the overflow. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, \ + 0x40000000 + TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x40000000, \ + 0x3fffffff + + /* Check that a carry alone does not cause a RANGE Exception, even + when it is the carry that causes the overflow. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0xffffffff, \ + 0xfffffffe + TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x00000000, \ + 0xffffffff + + /* Check that carry and overflow together cause an exception. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0xbfffffff, \ + 0xbfffffff + + CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Test l.addi */ + + /* Add two small positive numbers */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 1, 2 + + /* Check carry in is ignored. */ + TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addi, 1, 2 + + /* Add two small negative numbers. Sets the carry flag but not the + overflow flag. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0xffffffff, \ + 0xfffe + + /* Add two quite large positive numbers. Should set neither the + overflow nor the carry flag. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fff8000, \ + 0x7fff + + /* Add two large positive numbers. Should set the overflow, but + not the carry flag. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fffc000, \ + 0x4000 + + /* Add two quite large negative numbers. Should set the carry, but + not the overflow flag. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80008000, \ + 0x8000 + + /* Add two large negative numbers. Should set both the overflow + and carry flags. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80007fff, \ + 0x8000 + + /* Check that range exceptions are triggered. */ + + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Check that an overflow alone causes a RANGE Exception. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fffc000, \ + 0x4000 + + /* Check that a carry alone does not cause a RANGE Exception. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0xffffffff, \ + 0xfffe + + /* Check that carry and overflow together cause an exception. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80007fff, \ + 0x8000 + + CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Test l.addi */ + + /* Add two small positive numbers */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 1, 2 + + /* Add two small negative numbers. Sets the carry flag but not the + overflow flag. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0xffffffff, \ + 0xfffe + + /* Add two quite large positive numbers. Should set neither the + overflow nor the carry flag. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fff8000, \ + 0x7fff + + /* Add two quite large positive numbers with a carry in. Should + set the overflow but not the carry flag. */ + TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x7fff8000, 0x7fff + + /* Add two large positive numbers. Should set the overflow, but + not the carry flag. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fffc000, \ + 0x4000 + + /* Add the largest unsigned value to zero with a carry. This + potentially can break a simplistic test for carry that does not + consider the carry flag properly. Do it both ways around. */ + TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0xffffffff, 0x0000 + TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x00000000, 0xffff + + /* Add two quite large negative numbers. Should set the carry, but + not the overflow flag. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80008000, \ + 0x8000 + + /* Add two quite large negative numbers that would overflow, with a + carry that just avoids the overflow. This should set the carry, + but not the overflow flag. */ + TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x80007fff, 0x8000 + + /* Add two large negative numbers. Should set both the overflow + and carry flags. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80007fff, \ + 0x8000 + + /* Check that range exceptions are triggered. */ + + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Check that an overflow alone causes a RANGE Exception, even when + it is the carry that causes the overflow. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fffc000, \ + 0x4000 + TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x7fffc000, 0x3fff + + /* Check that a carry alone does not cause a RANGE Exception, even + when it is the carry that causes the overflow. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0xffffffff, \ + 0xfffe + TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x00000000, 0xffff + + /* Check that carry and overflow together cause an exception. */ + TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80007fff, \ + 0x8000 + + CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/adrp.S b/sim/testsuite/or1k/adrp.S new file mode 100644 index 0000000..c0883b6 --- /dev/null +++ b/sim/testsuite/or1k/adrp.S @@ -0,0 +1,73 @@ +/* Tests the load page address instruction. + + Copyright (C) 2019-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x00002064);\n +# output: report(0x00012138);\n +# output: report(0x00002000);\n +# output: report(0x00012000);\n +# output: report(0x00002000);\n +# output: report(0x00014000);\n +# output: report(0x00000000);\n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + STANDARD_TEST_ENVIRONMENT + + .section .data + .org 0x10000 + .align 4 + .type pi, @object + .size pi, 4 +pi: + .float 3.14159 + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Print out the PC. To compare with that loaded by l.adrp. */ + l.jal capture_pc + l.nop +capture_pc: + REPORT_REG_TO_CONSOLE r9 + + /* Print out our data address to compared with l.adrp offset. */ + l.movhi r11, ha(pi) + l.addi r11, r11, lo(pi) + REPORT_REG_TO_CONSOLE r11 + + /* Test l.adrp with symbols, loads page of symbol to register. */ + l.adrp r4, start_tests + REPORT_REG_TO_CONSOLE r4 + + l.adrp r4, pi + REPORT_REG_TO_CONSOLE r4 + + /* Test l.adrp with immediate, immediate is the page offset. */ + l.adrp r4, 0x0 + REPORT_REG_TO_CONSOLE r4 + + l.adrp r4, 0x12000 + REPORT_REG_TO_CONSOLE r4 + + l.adrp r4, -0x2000 + REPORT_REG_TO_CONSOLE r4 + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/alltests.exp b/sim/testsuite/or1k/alltests.exp new file mode 100644 index 0000000..dd08fbc --- /dev/null +++ b/sim/testsuite/or1k/alltests.exp @@ -0,0 +1,34 @@ +# OR1K simulator testsuite. +# +# Copyright 2017-2021 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +if [istarget or1k*-*-*] { + + set all_machs "or1k" + + global global_ld_options + set global_ld_options "-T $srcdir/$subdir/or1k-test.ld" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.S]] { + + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } + +} diff --git a/sim/testsuite/or1k/and.S b/sim/testsuite/or1k/and.S new file mode 100644 index 0000000..8003d38 --- /dev/null +++ b/sim/testsuite/or1k/and.S @@ -0,0 +1,198 @@ +/* Tests instructions l.and, l.andi. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0xffffffff);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0xaaaaaaaa);\n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x55555555);\n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0xb38f0f83);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0xc4c70f07);\n +# output: report(0x44400004);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x38f0f83b);\n +# output: report(0x30800803);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0x0000ffff);\n +# output: report(0x0000ffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x0000aaaa);\n +# output: report(0x0000aaaa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x00005555);\n +# output: report(0x00005555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x00005555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000f83);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000f07);\n +# output: report(0x00000004);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000f83b);\n +# output: report(0x00000803);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + STANDARD_TEST_ENVIRONMENT + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Always set OVE. We should never trigger an exception, even if + this bit is set. */ + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Test the l.and instruction with a range of operands. */ + TEST_INST_I32_I32 l.and, 0x00000000, 0x00000000 + TEST_INST_I32_I32 l.and, 0xffffffff, 0xffffffff + TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0x00000000 + TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0xaaaaaaaa + TEST_INST_I32_I32 l.and, 0x55555555, 0x00000000 + TEST_INST_I32_I32 l.and, 0x55555555, 0x55555555 + TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0x55555555 + TEST_INST_I32_I32 l.and, 0x4c70f07c, 0xb38f0f83 + TEST_INST_I32_I32 l.and, 0x4c70f07c, 0xc4c70f07 + TEST_INST_I32_I32 l.and, 0xb38f0f83, 0x38f0f83b + + /* Test the l.andi instruction with a range of operands. */ + TEST_INST_I32_I16 l.andi, 0x00000000, 0x0000 + TEST_INST_I32_I16 l.andi, 0xffffffff, 0xffff + TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0x0000 + TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0xaaaa + TEST_INST_I32_I16 l.andi, 0x55555555, 0x0000 + TEST_INST_I32_I16 l.andi, 0x55555555, 0x5555 + TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0x5555 + TEST_INST_I32_I16 l.andi, 0x4c70f07c, 0x0f83 + TEST_INST_I32_I16 l.andi, 0x4c70f07c, 0x0f07 + TEST_INST_I32_I16 l.andi, 0xb38f0f83, 0xf83b + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/basic.S b/sim/testsuite/or1k/basic.S new file mode 100644 index 0000000..02faebb --- /dev/null +++ b/sim/testsuite/or1k/basic.S @@ -0,0 +1,522 @@ +/* Tests some basic CPU instructions. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0xffff0012);\n +# output: report(0x12352af7);\n +# output: report(0x7ffffffe);\n +# output: report(0xffffa5a7);\n +# output: report(0x000fffff);\n +# output: report(0x00002800);\n +# output: report(0x00000009);\n +# output: report(0xdeaddead);\n +# output: report(0xffff0000);\n +# output: report(0x12345678);\n +# output: report(0xabcdf0bd);\n +# output: exit(0)\n + +#include "or1k-asm-test-env.h" + +#define FIRST_RAM_ADDR 0x00000000 + + STANDARD_TEST_HEADER + + /* Early test begin. */ + + /* Do this test upfront, as it modifies STACK_POINTER_R1. */ + + l.addi r1 , r0 , 0x1 + l.addi r2 , r1 , 0x2 + l.addi r3 , r2 , 0x4 + l.addi r4 , r3 , 0x8 + l.addi r5 , r4 , 0x10 + l.addi r6 , r5 , 0x20 + l.addi r7 , r6 , 0x40 + l.addi r8 , r7 , 0x80 + l.addi r9 , r8 , 0x100 + l.addi r10, r9 , 0x200 + l.addi r11, r10, 0x400 + l.addi r12, r11, 0x800 + l.addi r13, r12, 0x1000 + l.addi r14, r13, 0x2000 + l.addi r15, r14, 0x4000 + l.addi r16, r15, 0x8000 + + l.sub r31, r0 , r1 + l.sub r30, r31, r2 + l.sub r29, r30, r3 + l.sub r28, r29, r4 + l.sub r27, r28, r5 + l.sub r26, r27, r6 + l.sub r25, r26, r7 + l.sub r24, r25, r8 + l.sub r23, r24, r9 + l.sub r22, r23, r10 + l.sub r21, r22, r11 + l.sub r20, r21, r12 + l.sub r19, r20, r13 + l.sub r18, r19, r14 + l.sub r17, r18, r15 + l.sub r16, r17, r16 + + /* We cannot use REPORT_REG_TO_CONSOLE here, as the stack is not + set up yet. */ + MOVE_REG NOP_REPORT_R3, r16 + REPORT_TO_CONSOLE /* Should be 0xffff0012 */ + + /* Early test end. */ + + STANDARD_TEST_BODY + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Read and write from RAM. */ + + LOAD_IMMEDIATE r31, FIRST_RAM_ADDR + l.sw 0(r31), r16 + + l.movhi r3,0x1234 + l.ori r3,r3,0x5678 + + l.sw 4(r31),r3 + + l.lbz r4,4(r31) + l.add r8,r8,r4 + l.sb 11(r31),r4 + l.lbz r4,5(r31) + l.add r8,r8,r4 + l.sb 10(r31),r4 + l.lbz r4,6(r31) + l.add r8,r8,r4 + l.sb 9(r31),r4 + l.lbz r4,7(r31) + l.add r8,r8,r4 + l.sb 8(r31),r4 + + l.lbs r4,8(r31) + l.add r8,r8,r4 + l.sb 7(r31),r4 + l.lbs r4,9(r31) + l.add r8,r8,r4 + l.sb 6(r31),r4 + l.lbs r4,10(r31) + l.add r8,r8,r4 + l.sb 5(r31),r4 + l.lbs r4,11(r31) + l.add r8,r8,r4 + l.sb 4(r31),r4 + + l.lhz r4,4(r31) + l.add r8,r8,r4 + l.sh 10(r31),r4 + l.lhz r4,6(r31) + l.add r8,r8,r4 + l.sh 8(r31),r4 + + l.lhs r4,8(r31) + l.add r8,r8,r4 + l.sh 6(r31),r4 + l.lhs r4,10(r31) + l.add r8,r8,r4 + l.sh 4(r31),r4 + + l.lwz r4,4(r31) + l.add r8,r8,r4 + + REPORT_REG_TO_CONSOLE r8 /* Should be 0x12352af7 */ + + l.lwz r9,0(r31) + l.add r8,r9,r8 + l.sw 0(r31),r8 + + /* Test arithmetic operations. */ + + l.addi r3,r0,1 + l.addi r4,r0,2 + l.addi r5,r0,-1 + l.addi r6,r0,-1 + l.addi r8,r0,0 + + l.sub r7,r5,r3 + l.sub r8,r3,r5 + l.add r8,r8,r7 + + l.div r7,r7,r4 + l.add r9,r3,r4 + l.mul r7,r9,r7 + l.divu r7,r7,r4 + l.add r8,r8,r7 + + REPORT_REG_TO_CONSOLE r8 /* Should be 0x7ffffffe */ + + l.lwz r9,0(r31) + l.add r8,r9,r8 + l.sw 0(r31),r8 + + /* Test logical operations. */ + + l.addi r3,r0,1 + l.addi r4,r0,2 + l.addi r5,r0,-1 + l.addi r6,r0,-1 + l.addi r8,r0,0 + + l.andi r8,r8,1 + l.and r8,r8,r3 + + l.xori r8,r5,0xa5a5 + l.xor r8,r8,r5 + + l.ori r8,r8,2 + l.or r8,r8,r4 + + REPORT_REG_TO_CONSOLE r8 /* Should be 0xffffa5a7 */ + + l.lwz r9,0(r31) + l.add r8,r9,r8 + l.sw 0(r31),r8 + + /* Test shifting operations. */ + + l.addi r3,r0,1 + l.addi r4,r0,2 + l.addi r5,r0,-1 + l.addi r6,r0,-1 + l.addi r8,r0,0 + + l.slli r8,r5,6 + l.sll r8,r8,r4 + + l.srli r8,r8,6 + l.srl r8,r8,r4 + + l.srai r8,r8,2 + l.sra r8,r8,r4 + + REPORT_REG_TO_CONSOLE r8 /* Should be 0x000fffff */ + + l.lwz r9,0(r31) + l.add r8,r9,r8 + l.sw 0(r31),r8 + + /* Test the CPU flag. */ + + l.addi r3,r0,1 + l.addi r4,r0,-2 + l.addi r8,r0,0 + + l.sfeq r3,r3 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfeq r3,r4 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfeqi r3,1 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfeqi r3,-2 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfne r3,r3 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfne r3,r4 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfnei r3,1 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfnei r3,-2 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgtu r3,r3 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgtu r3,r4 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgtui r3,1 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgtui r3,-2 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgeu r3,r3 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgeu r3,r4 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgeui r3,1 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgeui r3,-2 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfltu r3,r3 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfltu r3,r4 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfltui r3,1 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfltui r3,-2 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfleu r3,r3 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfleu r3,r4 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfleui r3,1 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfleui r3,-2 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgts r3,r3 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgts r3,r4 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgtsi r3,1 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgtsi r3,-2 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfges r3,r3 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfges r3,r4 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgesi r3,1 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfgesi r3,-2 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sflts r3,r3 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sflts r3,r4 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfltsi r3,1 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfltsi r3,-2 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfles r3,r3 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sfles r3,r4 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sflesi r3,1 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + l.sflesi r3,-2 + l.mfspr r5,r0,17 + l.andi r4,r5,0x200 + l.add r8,r8,r4 + + REPORT_REG_TO_CONSOLE r8 /* Should be 0x00002800 */ + + l.lwz r9,0(r31) + l.add r8,r9,r8 + l.sw 0(r31),r8 + + /* Test the jump instructions. */ + + l.addi r8,r0,0 + + OR1K_DELAYED ( + OR1K_INST (l.addi r8,r8,1), + OR1K_INST (l.j _T1) + ) + +_T2: OR1K_DELAYED ( + OR1K_INST (l.addi r8,r8,1), + OR1K_INST (l.jr r9) + ) + +_T1: OR1K_DELAYED ( + OR1K_INST (l.addi r8,r8,1), + OR1K_INST (l.jal _T2) + ) + + l.sfeqi r0,0 + OR1K_DELAYED ( + OR1K_INST (l.addi r8,r8,1), + OR1K_INST (l.bf _T3) + ) + +_T3: l.sfeqi r0,1 + OR1K_DELAYED ( + OR1K_INST (l.addi r8,r8,1), + OR1K_INST (l.bf _T4) + ) + + l.addi r8,r8,1 + +_T4: l.sfeqi r0,0 + OR1K_DELAYED ( + OR1K_INST (l.addi r8,r8,1), + OR1K_INST (l.bnf _T5) + ) + + l.addi r8,r8,1 + +_T5: l.sfeqi r0,1 + OR1K_DELAYED ( + OR1K_INST (l.addi r8,r8,1), + OR1K_INST (l.bnf _T6) + ) + + l.addi r8,r8,1 + +_T6: l.movhi r3,hi (_T7) + l.ori r3,r3,lo (_T7) + l.mtspr r0,r3,32 + l.mfspr r5,r0,17 + l.mtspr r0,r5,64 + l.rfe + l.addi r8,r8,1 /* l.rfe should not have a delay slot */ + + l.addi r8,r8,1 + +_T7: REPORT_REG_TO_CONSOLE r8 /* Should be 0x000000009 */ + + l.lwz r9,0(r31) + l.add r8,r9,r8 + l.sw 0(r31),r8 + + l.lwz r9,0(r31) + l.movhi r3,0x4c69 + l.ori r3,r3,0xe5f7 + l.add r8,r8,r3 + + REPORT_REG_TO_CONSOLE r8 /* Should be 0xdeaddead */ + + /* Test l.movhi, on 32-bit implementations it should not + sign-extend anything. */ + + l.movhi r3, -1 + REPORT_REG_TO_CONSOLE r3 + + /* Test l.cmov */ + + LOAD_IMMEDIATE r14, 0x12345678 + LOAD_IMMEDIATE r15, 0xABCDF0BD + + SET_SPR_SR_FLAGS SPR_SR_F, r6, r7 + l.cmov r10, r14, r15 + CLEAR_SPR_SR_FLAGS SPR_SR_F, r6, r7 + l.cmov r11, r14, r15 + + REPORT_REG_TO_CONSOLE r10 + REPORT_REG_TO_CONSOLE r11 + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/div.S b/sim/testsuite/or1k/div.S new file mode 100644 index 0000000..dc73d73 --- /dev/null +++ b/sim/testsuite/or1k/div.S @@ -0,0 +1,291 @@ +/* Tests the divide instructions. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x0000000c);\n +# output: report(0x00000003);\n +# output: report(0x00000004);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x0000000b);\n +# output: report(0x00000003);\n +# output: report(0x00000003);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffff4);\n +# output: report(0xfffffffd);\n +# output: report(0x00000004);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffff5);\n +# output: report(0xfffffffd);\n +# output: report(0x00000003);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffff4);\n +# output: report(0x00000003);\n +# output: report(0xfffffffc);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffff5);\n +# output: report(0x00000003);\n +# output: report(0xfffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x0000000c);\n +# output: report(0xfffffffd);\n +# output: report(0xfffffffc);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x0000000b);\n +# output: report(0xfffffffd);\n +# output: report(0xfffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x0000000c);\n +# output: report(0x00000000);\n +# output: report(0xfffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffff4);\n +# output: report(0x00000000);\n +# output: report(0xfffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x0000000c);\n +# output: report(0x00000000);\n +# output: report(0xfffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0xfffffff4);\n +# output: report(0x00000000);\n +# output: report(0xfffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x0000000c);\n +# output: report(0x00000003);\n +# output: report(0x00000004);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x0000000b);\n +# output: report(0x00000003);\n +# output: report(0x00000003);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffff4);\n +# output: report(0xfffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffff5);\n +# output: report(0xfffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffff4);\n +# output: report(0x00000003);\n +# output: report(0x55555551);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffff5);\n +# output: report(0x00000003);\n +# output: report(0x55555551);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x0000000c);\n +# output: report(0xfffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x0000000b);\n +# output: report(0xfffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x0000000c);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffff4);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x0000000c);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0xfffffff4);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + STANDARD_TEST_ENVIRONMENT + + .section .exception_vectors + + /* Range exception. */ + .org 0xb00 + + l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE + PUSH r2 + PUSH r3 + /* Save the address of the instruction that caused the problem. */ + MOVE_FROM_SPR r2, SPR_EPCR_BASE + LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */ + l.sw 0(r2), r3 + POP r3 + POP r2 + l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE + l.rfe + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test l.div */ + + /* Divide two positive numbers and check rounding. Should set no + flags. */ + TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000003 /* 12 / 3 = 4 */ + TEST_INST_I32_I32 l.div, 0x0000000b, 0x00000003 /* 11 / 3 = 3 */ + + /* Divide two negative numbers and check rounding. Should set no + flags. */ + TEST_INST_I32_I32 l.div, 0xfffffff4, 0xfffffffd + TEST_INST_I32_I32 l.div, 0xfffffff5, 0xfffffffd + + /* Divide a negative number by a positive number and check + rounding. Should set no flags. */ + TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000003 + TEST_INST_I32_I32 l.div, 0xfffffff5, 0x00000003 + + /* Divide a positive number by a negative number and check + rounding. Should set no flags. */ + TEST_INST_I32_I32 l.div, 0x0000000c, 0xfffffffd + TEST_INST_I32_I32 l.div, 0x0000000b, 0xfffffffd + + /* Divide by zero. This will set the overflow flag. */ + TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000000 + TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000000 + + /* Check that range exceptions are triggered. */ + + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Divide by zero. This will set the overflow flag and trigger an + exception. */ + TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000000 + TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000000 + + CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Test l.divu */ + + /* Divide two positive numbers and check rounding. Should set no + flags. */ + TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000003 + TEST_INST_I32_I32 l.divu, 0x0000000b, 0x00000003 + + /* Divide two numbers that would be negative under 2's complement + and check rounding. Should set no flags. */ + TEST_INST_I32_I32 l.divu, 0xfffffff4, 0xfffffffd + TEST_INST_I32_I32 l.divu, 0xfffffff5, 0xfffffffd + + /* Divide a number that would be negative under 2's complement by a + number that would be positive under 2's complement and check + rounding. This should set no flags. */ + TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000003 + TEST_INST_I32_I32 l.divu, 0xfffffff5, 0x00000003 + + /* Divide a number that would be positive under 2's complement by a + number that would be negative under 2's complement and check + rounding. This should set no flags. */ + TEST_INST_I32_I32 l.divu, 0x0000000c, 0xfffffffd + TEST_INST_I32_I32 l.divu, 0x0000000b, 0xfffffffd + + /* Divide by zero. This will set the carry flag. */ + TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000000 + TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000000 + + /* Check that range exceptions are triggered. */ + + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Divide by zero. This will set the carry flag and trigger an + exception. */ + TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000000 + TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000000 + + CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/ext.S b/sim/testsuite/or1k/ext.S new file mode 100644 index 0000000..e7e68f0 --- /dev/null +++ b/sim/testsuite/or1k/ext.S @@ -0,0 +1,236 @@ +/* Tests the l.ext{b,h}{s,z} instructions. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x0000007f);\n +# output: report(0x0000007f);\n +# output: report(0x00000053);\n +# output: report(0x00000053);\n +# output: report(0x0000ff53);\n +# output: report(0x00000053);\n +# output: report(0x00001234);\n +# output: report(0x00000034);\n +# output: report(0x000000ff);\n +# output: report(0xffffffff);\n +# output: report(0x00000080);\n +# output: report(0xffffff80);\n +# output: report(0x0000ff80);\n +# output: report(0xffffff80);\n +# output: report(0x00007f80);\n +# output: report(0xffffff80);\n +# output: report(0x00007fff);\n +# output: report(0xffffffff);\n +# output: report(0x0000007f);\n +# output: report(0x0000007f);\n +# output: report(0x00000053);\n +# output: report(0x00000053);\n +# output: report(0x0000ff53);\n +# output: report(0x00000053);\n +# output: report(0x00001234);\n +# output: report(0x00000034);\n +# output: report(0x000000ff);\n +# output: report(0x000000ff);\n +# output: report(0x00000080);\n +# output: report(0x00000080);\n +# output: report(0x0000ff80);\n +# output: report(0x00000080);\n +# output: report(0x00007f80);\n +# output: report(0x00000080);\n +# output: report(0x00007fff);\n +# output: report(0x000000ff);\n +# output: report(0x00007fff);\n +# output: report(0x00007fff);\n +# output: report(0x00005233);\n +# output: report(0x00005233);\n +# output: report(0xffff2f53);\n +# output: report(0x00002f53);\n +# output: report(0x12345678);\n +# output: report(0x00005678);\n +# output: report(0x0000ffff);\n +# output: report(0xffffffff);\n +# output: report(0x00008000);\n +# output: report(0xffff8000);\n +# output: report(0x0000ff80);\n +# output: report(0xffffff80);\n +# output: report(0x80008000);\n +# output: report(0xffff8000);\n +# output: report(0x7fffffff);\n +# output: report(0xffffffff);\n +# output: report(0x00007fff);\n +# output: report(0x00007fff);\n +# output: report(0x00005233);\n +# output: report(0x00005233);\n +# output: report(0xffff2f53);\n +# output: report(0x00002f53);\n +# output: report(0x12345678);\n +# output: report(0x00005678);\n +# output: report(0x0000ffff);\n +# output: report(0x0000ffff);\n +# output: report(0x00008000);\n +# output: report(0x00008000);\n +# output: report(0x0000ff80);\n +# output: report(0x0000ff80);\n +# output: report(0x80008000);\n +# output: report(0x00008000);\n +# output: report(0x7fffffff);\n +# output: report(0x0000ffff);\n +# output: report(0xffffffff);\n +# output: report(0xffffffff);\n +# output: report(0x7fffffff);\n +# output: report(0x7fffffff);\n +# output: report(0x7fff7fff);\n +# output: report(0x7fff7fff);\n +# output: report(0xffff7f7f);\n +# output: report(0xffff7f7f);\n +# output: report(0xffffff7f);\n +# output: report(0xffffff7f);\n +# output: report(0xffff7fff);\n +# output: report(0xffff7fff);\n +# output: report(0x7fff7f7f);\n +# output: report(0x7fff7f7f);\n +# output: report(0x12345678);\n +# output: report(0x12345678);\n +# output: report(0xffffffff);\n +# output: report(0xffffffff);\n +# output: report(0x7fffffff);\n +# output: report(0x7fffffff);\n +# output: report(0x7fff7fff);\n +# output: report(0x7fff7fff);\n +# output: report(0xffff7f7f);\n +# output: report(0xffff7f7f);\n +# output: report(0xffffff7f);\n +# output: report(0xffffff7f);\n +# output: report(0xffff7fff);\n +# output: report(0xffff7fff);\n +# output: report(0x7fff7f7f);\n +# output: report(0x7fff7f7f);\n +# output: report(0x12345678);\n +# output: report(0x12345678);\n +# output: exit(0)\n + +#include "or1k-asm-test-env.h" + + .macro CHECK_EXT insn, val, mask, high_mask + LOAD_IMMEDIATE r4, \val + REPORT_REG_TO_CONSOLE r4 + \insn r5, r4 + REPORT_REG_TO_CONSOLE r5 + LOAD_IMMEDIATE r6, \mask + l.xori r7, r6, -1 + l.and r8, r4, r6 + l.and r9, r5, r6 + l.sfne r8, r9 + OR1K_DELAYED_NOP (l.bf ext_fail) + l.and r8, r5, r7 + LOAD_IMMEDIATE r7, \high_mask + l.sfne r8, r7 + OR1K_DELAYED_NOP (l.bf ext_fail) + .endm + +#define CHECK_HIGH3_CLEAR(insn, val) CHECK_EXT insn, val, 0x000000ff, 0 +#define CHECK_HIGH3_SET(val) CHECK_EXT l.extbs, val, 0x000000ff, 0xffffff00 +#define CHECK_HIGH2_CLEAR(insn, val) CHECK_EXT insn, val, 0x0000ffff, 0 +#define CHECK_HIGH2_SET(val) CHECK_EXT l.exths, val, 0x0000ffff, 0xffff0000 + + .macro CHECK_MOVE insn, val + LOAD_IMMEDIATE r4, \val + REPORT_REG_TO_CONSOLE r4 + \insn r5, r4 + REPORT_REG_TO_CONSOLE r5 + l.sfne r5, r4 + OR1K_DELAYED_NOP (l.bf ext_fail) + .endm + + STANDARD_TEST_ENVIRONMENT + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test l.extbs */ + CHECK_HIGH3_CLEAR ( l.extbs, 0x7f ) + CHECK_HIGH3_CLEAR ( l.extbs, 0x53 ) + CHECK_HIGH3_CLEAR ( l.extbs, 0xff53 ) + CHECK_HIGH3_CLEAR ( l.extbs, 0x1234 ) + + CHECK_HIGH3_SET (0xff) + CHECK_HIGH3_SET (0x80) + CHECK_HIGH3_SET (0xff80) + CHECK_HIGH3_SET (0x7f80) + CHECK_HIGH3_SET (0x7fff) + + /* Test l.extbz */ + CHECK_HIGH3_CLEAR (l.extbz, 0x7f) + CHECK_HIGH3_CLEAR (l.extbz, 0x53) + CHECK_HIGH3_CLEAR (l.extbz, 0xff53) + CHECK_HIGH3_CLEAR (l.extbz, 0x1234) + + CHECK_HIGH3_CLEAR (l.extbz, 0xff) + CHECK_HIGH3_CLEAR (l.extbz, 0x80) + CHECK_HIGH3_CLEAR (l.extbz, 0xff80) + CHECK_HIGH3_CLEAR (l.extbz, 0x7f80) + CHECK_HIGH3_CLEAR (l.extbz, 0x7fff) + + /* Test l.exths */ + CHECK_HIGH2_CLEAR (l.exths, 0x7fff) + CHECK_HIGH2_CLEAR (l.exths, 0x5233) + CHECK_HIGH2_CLEAR (l.exths, 0xffff2f53) + CHECK_HIGH2_CLEAR (l.exths, 0x12345678) + + CHECK_HIGH2_SET (0xffff) + CHECK_HIGH2_SET (0x8000) + CHECK_HIGH2_SET (0xff80) + CHECK_HIGH2_SET (0x80008000) + CHECK_HIGH2_SET (0x7fffffff) + + /* Test l.exthz */ + CHECK_HIGH2_CLEAR (l.exthz, 0x7fff) + CHECK_HIGH2_CLEAR (l.exthz, 0x5233) + CHECK_HIGH2_CLEAR (l.exthz, 0xffff2f53) + CHECK_HIGH2_CLEAR (l.exthz, 0x12345678) + + CHECK_HIGH2_CLEAR (l.exthz, 0xffff) + CHECK_HIGH2_CLEAR (l.exthz, 0x8000) + CHECK_HIGH2_CLEAR (l.exthz, 0xff80) + CHECK_HIGH2_CLEAR (l.exthz, 0x80008000) + CHECK_HIGH2_CLEAR (l.exthz, 0x7fffffff) + + /* Test l.extws */ + CHECK_MOVE l.extws, 0xffffffff + CHECK_MOVE l.extws, 0x7fffffff + CHECK_MOVE l.extws, 0x7fff7fff + CHECK_MOVE l.extws, 0xffff7f7f + CHECK_MOVE l.extws, 0xffffff7f + CHECK_MOVE l.extws, 0xffff7fff + CHECK_MOVE l.extws, 0x7fff7f7f + CHECK_MOVE l.extws, 0x12345678 + + /* Test l.extwz */ + CHECK_MOVE l.extwz, 0xffffffff + CHECK_MOVE l.extwz, 0x7fffffff + CHECK_MOVE l.extwz, 0x7fff7fff + CHECK_MOVE l.extwz, 0xffff7f7f + CHECK_MOVE l.extwz, 0xffffff7f + CHECK_MOVE l.extwz, 0xffff7fff + CHECK_MOVE l.extwz, 0x7fff7f7f + CHECK_MOVE l.extwz, 0x12345678 + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 + +ext_fail: + EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR diff --git a/sim/testsuite/or1k/find.S b/sim/testsuite/or1k/find.S new file mode 100644 index 0000000..7713c17 --- /dev/null +++ b/sim/testsuite/or1k/find.S @@ -0,0 +1,100 @@ +/* Tests the find instructions. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x80000000);\n +# output: report(0x00000020);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000002);\n +# output: \n +# output: report(0x00018000);\n +# output: report(0x00000010);\n +# output: \n +# output: report(0xc0000000);\n +# output: report(0x0000001f);\n +# output: \n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x80000000);\n +# output: report(0x00000020);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x0000001f);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000020);\n +# output: \n +# output: report(0x00018000);\n +# output: report(0x00000011);\n +# output: \n +# output: report(0xc0000000);\n +# output: report(0x00000020);\n +# output: \n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + .macro TEST_FIND opcode, operand + LOAD_IMMEDIATE r5, \operand + REPORT_REG_TO_CONSOLE r5 + \opcode r4, r5 + REPORT_REG_TO_CONSOLE r4 + PRINT_NEWLINE_TO_CONSOLE + .endm + + STANDARD_TEST_ENVIRONMENT + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test l.ff1 */ + + TEST_FIND l.ff1, 0x00000001 + TEST_FIND l.ff1, 0x80000000 + TEST_FIND l.ff1, 0x55555555 + TEST_FIND l.ff1, 0xaaaaaaaa + TEST_FIND l.ff1, 0x00018000 + TEST_FIND l.ff1, 0xc0000000 + TEST_FIND l.ff1, 0x00000000 + + /* Test l.fl1 */ + + TEST_FIND l.fl1, 0x00000001 + TEST_FIND l.fl1, 0x80000000 + TEST_FIND l.fl1, 0x55555555 + TEST_FIND l.fl1, 0xaaaaaaaa + TEST_FIND l.fl1, 0x00018000 + TEST_FIND l.fl1, 0xc0000000 + TEST_FIND l.fl1, 0x00000000 + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/flag.S b/sim/testsuite/or1k/flag.S new file mode 100644 index 0000000..b614c1a --- /dev/null +++ b/sim/testsuite/or1k/flag.S @@ -0,0 +1,386 @@ +/* Tests the set flag (l.sf*) instructions. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + +#define INT_MAX 2147483647 /* 0x7fffffff */ +#define INT_MAX_MIN1 2147483646 /* 0x7ffffffe */ +#define NEG_INT_MAX -2147483648 /* 0x80000000 */ +#define NEG_INT_MAX_PL1 -2147483647 /* 0x80000001 */ +#define MIN1 -1 /* 0xffffffff */ + +#define SHRT_MIN (-32768) +#define SHRT_MAX 32767 + +#define UINT_MAX 4294967295 /* 0xffffffff */ +#define UINT_MAX_MIN1 4294967294 /* 0xfffffffe */ + +#define USHRT_MAX 65535 + + .macro MOVE_TO_R4_R5_AND_REPORT a, b + LOAD_IMMEDIATE r4, \a + LOAD_IMMEDIATE r5, \b + + /* During development, add REPORT_xxx statements here to see the + operands. */ + .endm + + .macro MOVE_TO_R4_AND_REPORT_I a, b + LOAD_IMMEDIATE r4, \a + + /* During development, add REPORT_xxx statements here to see the + operands. */ + .endm + + .macro SHOULD_BE_SET + OR1K_DELAYED_NOP (l.bnf failed) + .endm + + .macro SHOULDNT_BE_SET + OR1K_DELAYED_NOP (l.bf failed) + .endm + + .macro SHOULD_BE_LESS_THAN_SIGNED a, b + MOVE_TO_R4_R5_AND_REPORT \a , \b + + l.sfeq r4, r5 + SHOULDNT_BE_SET + l.sfne r4, r5 + SHOULD_BE_SET + l.sfgts r4, r5 + SHOULDNT_BE_SET + l.sfges r4, r5 + SHOULDNT_BE_SET + l.sfles r4, r5 + SHOULD_BE_SET + l.sflts r4, r5 + SHOULD_BE_SET + .endm + + .macro SHOULD_BE_GREATER_THAN_SIGNED a, b + MOVE_TO_R4_R5_AND_REPORT \a , \b + + l.sfeq r4, r5 + SHOULDNT_BE_SET + l.sfne r4, r5 + SHOULD_BE_SET + l.sfgts r4, r5 + SHOULD_BE_SET + l.sfges r4, r5 + SHOULD_BE_SET + l.sfles r4, r5 + SHOULDNT_BE_SET + l.sflts r4, r5 + SHOULDNT_BE_SET + .endm + + .macro SHOULD_BE_LESS_THAN_UNSIGNED a, b + MOVE_TO_R4_R5_AND_REPORT \a , \b + + l.sfeq r4, r5 + SHOULDNT_BE_SET + l.sfne r4, r5 + SHOULD_BE_SET + l.sfgtu r4, r5 + SHOULDNT_BE_SET + l.sfgeu r4, r5 + SHOULDNT_BE_SET + l.sfleu r4, r5 + SHOULD_BE_SET + l.sfltu r4, r5 + SHOULD_BE_SET + .endm + + .macro SHOULD_BE_GREATER_THAN_UNSIGNED a, b + MOVE_TO_R4_R5_AND_REPORT \a , \b + + l.sfeq r4, r5 + SHOULDNT_BE_SET + l.sfne r4, r5 + SHOULD_BE_SET + l.sfgtu r4, r5 + SHOULD_BE_SET + l.sfgeu r4, r5 + SHOULD_BE_SET + l.sfleu r4, r5 + SHOULDNT_BE_SET + l.sfltu r4, r5 + SHOULDNT_BE_SET + .endm + + .macro SHOULD_BE_EQUAL a, b + MOVE_TO_R4_R5_AND_REPORT \a , \b + + l.sfeq r4, r5 + SHOULD_BE_SET + l.sfne r4, r5 + SHOULDNT_BE_SET + + /* Signed tests. */ + l.sfgts r4, r5 + SHOULDNT_BE_SET + l.sfges r4, r5 + SHOULD_BE_SET + l.sfles r4, r5 + SHOULD_BE_SET + l.sflts r4, r5 + SHOULDNT_BE_SET + + /* Unsigned tests. */ + l.sfgtu r4, r5 + SHOULDNT_BE_SET + l.sfgeu r4, r5 + SHOULD_BE_SET + l.sfleu r4, r5 + SHOULD_BE_SET + l.sfltu r4, r5 + SHOULDNT_BE_SET + .endm + + .macro SHOULDNT_BE_EQUAL a, b + MOVE_TO_R4_R5_AND_REPORT \a , \b + + l.sfeq r4, r5 + SHOULDNT_BE_SET + l.sfne r4, r5 + SHOULD_BE_SET + .endm + + .macro SHOULD_BE_EQUAL_I a, b + MOVE_TO_R4_AND_REPORT_I \a, \b + + l.sfeqi r4, \b + SHOULD_BE_SET + l.sfnei r4, \b + SHOULDNT_BE_SET + + /* Signed tests. */ + l.sfgtsi r4, \b + SHOULDNT_BE_SET + l.sfgesi r4, \b + SHOULD_BE_SET + l.sflesi r4, \b + SHOULD_BE_SET + l.sfltsi r4, \b + SHOULDNT_BE_SET + + /* Unsigned tests. */ + l.sfgtui r4, \b + SHOULDNT_BE_SET + l.sfgeui r4, \b + SHOULD_BE_SET + l.sfleui r4, \b + SHOULD_BE_SET + l.sfltui r4, \b + SHOULDNT_BE_SET + .endm + + .macro SHOULDNT_BE_EQUAL_I a, b + MOVE_TO_R4_AND_REPORT_I \a, \b + + l.sfeqi r4, \b + SHOULDNT_BE_SET + l.sfnei r4, \b + SHOULD_BE_SET + .endm + + .macro SHOULD_BE_LESS_THAN_SIGNED_I a, b + MOVE_TO_R4_AND_REPORT_I \a, \b + + l.sfeqi r4, \b + SHOULDNT_BE_SET + l.sfnei r4, \b + SHOULD_BE_SET + l.sfgtsi r4, \b + SHOULDNT_BE_SET + l.sfgesi r4, \b + SHOULDNT_BE_SET + l.sflesi r4, \b + SHOULD_BE_SET + l.sfltsi r4, \b + SHOULD_BE_SET + .endm + + .macro SHOULD_BE_GREATER_THAN_SIGNED_I a, b + MOVE_TO_R4_AND_REPORT_I \a, \b + + l.sfeqi r4, \b + SHOULDNT_BE_SET + l.sfnei r4, \b + SHOULD_BE_SET + l.sfgtsi r4, \b + SHOULD_BE_SET + l.sfgesi r4, \b + SHOULD_BE_SET + l.sflesi r4, \b + SHOULDNT_BE_SET + l.sfltsi r4, \b + SHOULDNT_BE_SET + .endm + + .macro SHOULD_BE_LESS_THAN_UNSIGNED_I a, b + MOVE_TO_R4_AND_REPORT_I \a, \b + + l.sfeqi r4, \b + SHOULDNT_BE_SET + l.sfnei r4, \b + SHOULD_BE_SET + l.sfgtui r4, \b + SHOULDNT_BE_SET + l.sfgeui r4, \b + SHOULDNT_BE_SET + l.sfleui r4, \b + SHOULD_BE_SET + l.sfltui r4, \b + SHOULD_BE_SET + .endm + + .macro SHOULD_BE_GREATER_THAN_UNSIGNED_I a, b + MOVE_TO_R4_AND_REPORT_I \a, \b + + l.sfeqi r4, \b + SHOULDNT_BE_SET + l.sfnei r4, \b + SHOULD_BE_SET + l.sfgtui r4, \b + SHOULD_BE_SET + l.sfgeui r4, \b + SHOULD_BE_SET + l.sfleui r4, \b + SHOULDNT_BE_SET + l.sfltui r4, \b + SHOULDNT_BE_SET + .endm + + STANDARD_TEST_ENVIRONMENT + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Signed tests */ + + SHOULD_BE_LESS_THAN_SIGNED 0, 1 + SHOULD_BE_LESS_THAN_SIGNED MIN1, 0 + SHOULD_BE_LESS_THAN_SIGNED INT_MAX_MIN1, INT_MAX + SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, INT_MAX + SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, INT_MAX_MIN1 + SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX_PL1, INT_MAX + SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX_PL1, INT_MAX_MIN1 + SHOULD_BE_LESS_THAN_SIGNED -7, -6 + SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, NEG_INT_MAX_PL1 + SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, MIN1 + SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, 0 + + SHOULD_BE_GREATER_THAN_SIGNED 1, 0 + SHOULD_BE_GREATER_THAN_SIGNED 0, MIN1 + SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, INT_MAX_MIN1 + SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, NEG_INT_MAX + SHOULD_BE_GREATER_THAN_SIGNED INT_MAX_MIN1, NEG_INT_MAX + SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, NEG_INT_MAX_PL1 + SHOULD_BE_GREATER_THAN_SIGNED INT_MAX_MIN1, NEG_INT_MAX_PL1 + SHOULD_BE_GREATER_THAN_SIGNED -6, -7 + SHOULD_BE_GREATER_THAN_SIGNED NEG_INT_MAX_PL1, NEG_INT_MAX + SHOULD_BE_GREATER_THAN_SIGNED MIN1, NEG_INT_MAX + SHOULD_BE_GREATER_THAN_SIGNED 0, NEG_INT_MAX + + /* See the immediate tests below. */ + SHOULD_BE_LESS_THAN_SIGNED 0xFFFF7FFF, 0xFFFF8000 + /* See the immediate tests below. */ + SHOULD_BE_GREATER_THAN_SIGNED 0xFFFF8001, 0xFFFF8000 + + /* Signed tests, immediate */ + + SHOULD_BE_LESS_THAN_SIGNED_I 0, 1 + SHOULD_BE_LESS_THAN_SIGNED_I -1, 0 + SHOULD_BE_LESS_THAN_SIGNED_I -7, -6 + + SHOULD_BE_GREATER_THAN_SIGNED_I 0x00008000, 0x7FFF + SHOULD_BE_LESS_THAN_SIGNED_I 0xFFFFFFFF, 0x7FFF + /* 0x8000 gets sign-extended to 0xFFFF8000. */ + SHOULD_BE_LESS_THAN_SIGNED_I 0xFFFF7FFF, 0x8000 + /* 0x8000 gets sign-extended to 0xFFFF8000. */ + SHOULD_BE_GREATER_THAN_SIGNED_I 0xFFFF8001, 0x8000 + /* 0x8000 gets sign-extended to 0xFFFF8000. */ + SHOULD_BE_GREATER_THAN_SIGNED_I 0x00008000, 0x8000 + + /* Unsigned tests */ + + SHOULD_BE_LESS_THAN_UNSIGNED 0, 1 + SHOULD_BE_LESS_THAN_UNSIGNED UINT_MAX_MIN1, UINT_MAX + SHOULD_BE_GREATER_THAN_UNSIGNED 1, 0 + SHOULD_BE_GREATER_THAN_UNSIGNED UINT_MAX, UINT_MAX_MIN1 + SHOULD_BE_GREATER_THAN_UNSIGNED UINT_MAX, 0 + SHOULD_BE_GREATER_THAN_UNSIGNED 0x80000001, 0x80000000 + SHOULD_BE_LESS_THAN_UNSIGNED 0x80000000, 0x80000001 + SHOULD_BE_GREATER_THAN_UNSIGNED 0x80000000, 0x7fffffff + SHOULD_BE_LESS_THAN_UNSIGNED 0x7fffffff, 0x80000000 + SHOULD_BE_GREATER_THAN_UNSIGNED 0x7fffffff, 0x7ffffffe + SHOULD_BE_LESS_THAN_UNSIGNED 0x7ffffffe, 0x7fffffff + SHOULD_BE_LESS_THAN_UNSIGNED 0x2024fae0, 0xfef03220 + + /* Unsigned tests, immediate */ + + SHOULD_BE_LESS_THAN_UNSIGNED_I 0, 1 + SHOULD_BE_GREATER_THAN_UNSIGNED_I 1, 0 + SHOULD_BE_LESS_THAN_UNSIGNED_I SHRT_MAX - 1, SHRT_MAX + SHOULD_BE_GREATER_THAN_UNSIGNED_I SHRT_MAX , SHRT_MAX - 1 + + /* The sign extension produces unexpected results here. */ + + /* 0xFFFF gets sign-extended to 0xFFFFFFFF. */ + SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFFFFFF - 1, 0xFFFF + /* 0x8000 gets sign-extended to 0xFFFF8000. */ + SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFF7FFF, 0x8000 + + /* Equal tests. */ + + SHOULD_BE_EQUAL 0, 0 + SHOULD_BE_EQUAL UINT_MAX, UINT_MAX + SHOULD_BE_EQUAL MIN1, UINT_MAX + SHOULD_BE_EQUAL INT_MAX, INT_MAX + SHOULD_BE_EQUAL NEG_INT_MAX, NEG_INT_MAX + + /* Equal tests, immediate. Test the 16-to-32-bit sign extension. */ + + SHOULD_BE_EQUAL_I 0, 0 + SHOULD_BE_EQUAL_I 0x00007FFF, 0x7FFF + SHOULD_BE_EQUAL_I 0xFFFF8000, 0x8000 + SHOULD_BE_EQUAL_I 0xFFFFFFFF, 0xFFFF + + /* Non-equal tests. */ + + SHOULDNT_BE_EQUAL 0, 1 + SHOULDNT_BE_EQUAL UINT_MAX, INT_MAX + SHOULDNT_BE_EQUAL UINT_MAX, NEG_INT_MAX + SHOULDNT_BE_EQUAL MIN1, NEG_INT_MAX_PL1 + SHOULDNT_BE_EQUAL INT_MAX, NEG_INT_MAX + SHOULDNT_BE_EQUAL NEG_INT_MAX_PL1, UINT_MAX_MIN1 + + /* Non-equal tests, immediate. Test the 16-to-32-bit sign + extension. */ + + SHOULDNT_BE_EQUAL_I 0x00008000, 0x8000 + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 + +failed: + EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR diff --git a/sim/testsuite/or1k/fpu-unordered.S b/sim/testsuite/or1k/fpu-unordered.S new file mode 100644 index 0000000..a4e6556 --- /dev/null +++ b/sim/testsuite/or1k/fpu-unordered.S @@ -0,0 +1,97 @@ +/* Tests some basic unordered fpu compare instructions. + + Copyright (C) 2019-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x40490fd0);\n +# output: report(0x402df84d);\n +# output: report(0x7fc00000);\n +# output: \n +# output: report(0x00000001);\n +# output: \n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000001);\n +# output: \n +# output: report(0x00000001);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + STANDARD_TEST_ENVIRONMENT + + .section .data + .align 4 + .type pi, @object + .size pi, 4 +anchor: +pi: + .float 3.14159 + + .type e, @object + .size e, 4 +e: + .float 2.71828 + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test unordered float comparisons. Setting up: + * r11 pointer to data + * r12 pi as float + * r13 e as float + * r16 nan as float + */ + l.ori r11, r0, ha(anchor) + l.addi r11, r11, lo(anchor) + l.lwz r12, 0(r11) + + l.lwz r13, 4(r11) + + /* Make a NaN. */ + lf.sub.s r16, r13, r13 + lf.div.s r16, r16, r16 + + /* Output to ensure we loaded it correctly. */ + REPORT_REG_TO_CONSOLE r12 + REPORT_REG_TO_CONSOLE r13 + REPORT_REG_TO_CONSOLE r16 + PRINT_NEWLINE_TO_CONSOLE + + lf.sfuge.s r12, r13 + MOVE_FROM_SPR r2, SPR_SR + REPORT_BIT_TO_CONSOLE r2, SPR_SR_F + PRINT_NEWLINE_TO_CONSOLE + + lf.sfun.s r12, r13 + MOVE_FROM_SPR r2, SPR_SR + REPORT_BIT_TO_CONSOLE r2, SPR_SR_F + PRINT_NEWLINE_TO_CONSOLE + + lf.sfun.s r12, r16 + MOVE_FROM_SPR r2, SPR_SR + REPORT_BIT_TO_CONSOLE r2, SPR_SR_F + PRINT_NEWLINE_TO_CONSOLE + + lf.sfueq.s r12, r12 + MOVE_FROM_SPR r2, SPR_SR + REPORT_BIT_TO_CONSOLE r2, SPR_SR_F + PRINT_NEWLINE_TO_CONSOLE + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/fpu.S b/sim/testsuite/or1k/fpu.S new file mode 100644 index 0000000..9a164b1 --- /dev/null +++ b/sim/testsuite/or1k/fpu.S @@ -0,0 +1,129 @@ +/* Tests some basic fpu instructions. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x00007ab7);\n +# output: report(0xffffd8f0);\n +# output: report(0x46f56e00);\n +# output: report(0xc61c4000);\n +# output: report(0x00007ab7);\n +# output: report(0xffffd8f0);\n +# output: \n +# output: report(0xc0490e56);\n +# output: report(0xfffffffd);\n +# output: \n +# output: report(0x4e6b4bbb);\n +# output: \n +# output: report(0xbdc0be40);\n +# output: \n +# output: report(0x00000001);\n +# output: \n +# output: WARNING: ignoring fpu error caught in fast mode.\n +# output: report(0x00000000);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + STANDARD_TEST_ENVIRONMENT + + .section .exception_vectors + + /* Floating point exception. */ + .org 0xd00 + + /* The handling is a bit dubious at present. We just patch the + instruction with l.nop and restart. This will go wrong in branch + delay slots. But we don't have those in this test. */ + l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE + PUSH r2 + PUSH r3 + /* Save the address of the instruction that caused the problem. */ + MOVE_FROM_SPR r2, SPR_EPCR_BASE + LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */ + l.sw -4(r2), r3 + POP r3 + POP r2 + l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE + l.rfe + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test lf.itof.s int to float conversion. Setting up: + * r10 31415.0f + * r12 -10000.0f + */ + l.ori r11, r0, 31415 + l.ori r13, r0, -10000 + l.movhi r15, 0xffff + l.or r13, r13, r15 + + REPORT_REG_TO_CONSOLE r11 + REPORT_REG_TO_CONSOLE r13 + lf.itof.s r10, r11 + lf.itof.s r12, r13 + REPORT_REG_TO_CONSOLE r10 + REPORT_REG_TO_CONSOLE r12 + + /* Test lf.ftoi.s float to int conversion. */ + lf.ftoi.s r11, r10 + lf.ftoi.s r13, r12 + REPORT_REG_TO_CONSOLE r11 + REPORT_REG_TO_CONSOLE r13 + PRINT_NEWLINE_TO_CONSOLE + + /* Test lf.div.s divide 31415 by -1000 to get -pi. Setting up: + * r8 -3.1415f + */ + lf.div.s r8, r10, r12 + REPORT_REG_TO_CONSOLE r8 + + lf.ftoi.s r11, r8 + REPORT_REG_TO_CONSOLE r11 + PRINT_NEWLINE_TO_CONSOLE + + /* Test lf.mul.s multiply -pi x -10000 x 31415. Setting up: + * r6 986902225 + */ + lf.mul.s r6, r8, r12 + lf.mul.s r6, r6, r10 + REPORT_REG_TO_CONSOLE r6 + PRINT_NEWLINE_TO_CONSOLE + + /* Test lf.rem.s remainder of 986902225 / -pi. */ + lf.rem.s r2, r6, r8 + REPORT_REG_TO_CONSOLE r2 + PRINT_NEWLINE_TO_CONSOLE + + /* Test lf.sfge.s set flag if r6 >= r10. */ + lf.sfge.s r6, r10 + MOVE_FROM_SPR r2, SPR_SR + REPORT_BIT_TO_CONSOLE r2, SPR_SR_F + PRINT_NEWLINE_TO_CONSOLE + + /* Test raising an exception by dividing by 0. */ + MOVE_FROM_SPR r2, SPR_FPCSR + l.ori r2, r2, 0x1 + MOVE_TO_SPR SPR_FPCSR, r2 +div0: lf.div.s r2, r8, r0 + REPORT_EXCEPTION div0 + PRINT_NEWLINE_TO_CONSOLE + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/fpu64a32-unordered.S b/sim/testsuite/or1k/fpu64a32-unordered.S new file mode 100644 index 0000000..1966916 --- /dev/null +++ b/sim/testsuite/or1k/fpu64a32-unordered.S @@ -0,0 +1,100 @@ +/* Tests some basic unordered fpu compare instructions. + + Copyright (C) 2019-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x400921f9);\n +# output: report(0xf01b866e);\n +# output: report(0x4005bf09);\n +# output: report(0x95aaf790);\n +# output: report(0x7ff80000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000001);\n +# output: \n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000001);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + STANDARD_TEST_ENVIRONMENT + + .section .data + .align 4 + .type pi, @object + .size pi, 8 +anchor: +pi: + .double 3.14159 + + .type e, @object + .size e, 8 +e: + .double 2.71828 + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test unordered double comparisons. Setting up: + * r11 pointer to data + * r12,r13 pi as double + * r14,r15 e as double + * r16,r17 nan as double + */ + l.ori r11, r0, ha(anchor) + l.addi r11, r11, lo(anchor) + l.lwz r12, 0(r11) + l.lwz r13, 4(r11) + + l.lwz r14, 8(r11) + l.lwz r15, 12(r11) + + /* Make a NaN. */ + lf.sub.d r16,r18, r12,r13, r12,r13 + lf.div.d r16,r18, r16,r18, r16,r18 + + /* Output to ensure we loaded it correctly. */ + REPORT_REG_TO_CONSOLE r12 + REPORT_REG_TO_CONSOLE r13 + + REPORT_REG_TO_CONSOLE r14 + REPORT_REG_TO_CONSOLE r15 + + REPORT_REG_TO_CONSOLE r16 + REPORT_REG_TO_CONSOLE r18 + PRINT_NEWLINE_TO_CONSOLE + + lf.sfuge.d r12,r13, r14,r15 + MOVE_FROM_SPR r2, SPR_SR + REPORT_BIT_TO_CONSOLE r2, SPR_SR_F + PRINT_NEWLINE_TO_CONSOLE + + lf.sfun.d r12,r13, r14,r15 + MOVE_FROM_SPR r2, SPR_SR + REPORT_BIT_TO_CONSOLE r2, SPR_SR_F + PRINT_NEWLINE_TO_CONSOLE + + lf.sfun.d r12,r13, r16,r18 + MOVE_FROM_SPR r2, SPR_SR + REPORT_BIT_TO_CONSOLE r2, SPR_SR_F + PRINT_NEWLINE_TO_CONSOLE + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/fpu64a32.S b/sim/testsuite/or1k/fpu64a32.S new file mode 100644 index 0000000..319af48 --- /dev/null +++ b/sim/testsuite/or1k/fpu64a32.S @@ -0,0 +1,172 @@ +/* Tests some basic fpu instructions. + + Copyright (C) 2019-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x400921f9);\n +# output: report(0xf01b866e);\n +# output: report(0x4005bf09);\n +# output: report(0x95aaf790);\n +# output: report(0x00000000);\n +# output: report(0x00001234);\n +# output: \n +# output: report(0x40b23400);\n +# output: report(0x00000000);\n +# output: report(0x40b23400);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x40177081);\n +# output: report(0xc2e33eff);\n +# output: report(0x400921f9);\n +# output: report(0xf01b866e);\n +# output: \n +# output: report(0x40211456);\n +# output: report(0x587dfabf);\n +# output: report(0x400921f9);\n +# output: report(0xf01b866d);\n +# output: \n +# output: report(0x00000001);\n +# output: \n +# output: WARNING: ignoring fpu error caught in fast mode.\n +# output: report(0x00000000);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + STANDARD_TEST_ENVIRONMENT + + .section .exception_vectors + + /* Floating point exception. */ + .org 0xd00 + + /* The handling is a bit dubious at present. We just patch the + instruction with l.nop and restart. This will go wrong in branch + delay slots. But we don't have those in this test. */ + l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE + PUSH r2 + PUSH r3 + /* Save the address of the instruction that caused the problem. */ + MOVE_FROM_SPR r2, SPR_EPCR_BASE + LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */ + l.sw -4(r2), r3 + POP r3 + POP r2 + l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE + l.rfe + + .section .data + .align 4 + .type pi, @object + .size pi, 8 +anchor: +pi: + .double 3.14159 + + .type e, @object + .size e, 8 +e: + .double 2.71828 + + .type large, @object + .size large, 8 +large: + .long 0 + .long 0x1234 + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test lf.itof.d int to double conversion. Setting up: + * r11 pointer to data + * r12,r13 pi as double + * r14,r15 e as double + * r16,r17 a long long + */ + l.ori r11, r0, ha(anchor) + l.addi r11, r11, lo(anchor) + l.lwz r12, 0(r11) + l.lwz r13, 4(r11) + + l.lwz r14, 8(r11) + l.lwz r15, 12(r11) + + l.lwz r16, 16(r11) + l.lwz r18, 20(r11) + + /* Output to ensure we loaded it correctly. */ + REPORT_REG_TO_CONSOLE r12 + REPORT_REG_TO_CONSOLE r13 + + REPORT_REG_TO_CONSOLE r14 + REPORT_REG_TO_CONSOLE r15 + + REPORT_REG_TO_CONSOLE r16 + REPORT_REG_TO_CONSOLE r18 + PRINT_NEWLINE_TO_CONSOLE + + /* Convert the big long to a double. */ + lf.itof.d r16,r18, r16,r18 + REPORT_REG_TO_CONSOLE r16 + REPORT_REG_TO_CONSOLE r18 + + /* Convert the double back to a long, it should match before. */ + lf.ftoi.d r16,r18, r16,r18 + lf.itof.d r16,r18, r16,r18 + + REPORT_REG_TO_CONSOLE r16 + REPORT_REG_TO_CONSOLE r18 + + PRINT_NEWLINE_TO_CONSOLE + + /* Add and subtract some double values. */ + lf.add.d r12,r13, r12,r13, r14,r15 + REPORT_REG_TO_CONSOLE r12 + REPORT_REG_TO_CONSOLE r13 + + lf.sub.d r12,r13, r12,r13, r14,r15 + REPORT_REG_TO_CONSOLE r12 + REPORT_REG_TO_CONSOLE r13 + PRINT_NEWLINE_TO_CONSOLE + + /* Multiply and divide double values. */ + lf.mul.d r12,r13, r12,r13, r14,r15 + REPORT_REG_TO_CONSOLE r12 + REPORT_REG_TO_CONSOLE r13 + + lf.div.d r12,r13, r12,r13, r14,r15 + REPORT_REG_TO_CONSOLE r12 + REPORT_REG_TO_CONSOLE r13 + PRINT_NEWLINE_TO_CONSOLE + + /* Test lf.sfge.s set flag if r6 >= r10. */ + lf.sfge.d r12,r13, r14,r15 + MOVE_FROM_SPR r2, SPR_SR + REPORT_BIT_TO_CONSOLE r2, SPR_SR_F + PRINT_NEWLINE_TO_CONSOLE + + /* Test raising an exception by dividing by 0. */ + MOVE_FROM_SPR r2, SPR_FPCSR + l.ori r2, r2, 0x1 + MOVE_TO_SPR SPR_FPCSR, r2 +div0: lf.div.d r2,r3, r12,r13, r0,r1 + REPORT_EXCEPTION div0 + PRINT_NEWLINE_TO_CONSOLE + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/jump.S b/sim/testsuite/or1k/jump.S new file mode 100644 index 0000000..8181886 --- /dev/null +++ b/sim/testsuite/or1k/jump.S @@ -0,0 +1,105 @@ +/* Tests the jump instructions. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x48000000);\n +# output: report(0x00000005);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x48000000);\n +# output: report(0x00000009);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x44000000);\n +# output: report(0x00000005);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x44000000);\n +# output: report(0x00000009);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + +/* Tests a jump instruction using a register destination. + Checks whether the jump succeeds, or whether an exception is triggered + (but not if the right exception was triggered yet). + + We manually construct the opcode, to allow us to force R9 into the + destination field, to test exception handling. Usually the assembler + would prevent this. + + Do not specify R31 as the register to use for the jump, as it's used + internally. */ + + .macro TEST_JUMP opcode_value dest_register_number alignment_offset + REPORT_IMMEDIATE_TO_CONSOLE \opcode_value + REPORT_IMMEDIATE_TO_CONSOLE \dest_register_number + REPORT_IMMEDIATE_TO_CONSOLE \alignment_offset + LOAD_IMMEDIATE r\dest_register_number, 51f + \alignment_offset + /* Generate the jump opcode. */ +\@1$: OR1K_DELAYED_NOP \ + (.word ( \opcode_value | (\dest_register_number << 11) )) + /* If the jump failed, we land here. */ + REPORT_IMMEDIATE_TO_CONSOLE 1 + OR1K_DELAYED_NOP (l.j 52f) + /* If the jump succeeds, we land here. */ +51: REPORT_IMMEDIATE_TO_CONSOLE 0 +52: REPORT_EXCEPTION \@1$ + PRINT_NEWLINE_TO_CONSOLE + .endm + + STANDARD_TEST_ENVIRONMENT + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test l.jalr (jump and link register) */ + TEST_JUMP 0x48000000, 5, 0 + /* TODO: The sim does not support unaligned memory access yet. + TEST_JUMP 0x48000000, 5, 1 + TEST_JUMP 0x48000000, 5, 2 + TEST_JUMP 0x48000000, 5, 3 + */ + + /* Test with link register as the destination. This is not + allowed. */ + TEST_JUMP 0x48000000, 9, 0 + + /* Test l.jr (jump register) */ + TEST_JUMP 0x44000000, 5, 0 + /* TODO: The sim does not support unaligned memory access yet. + TEST_JUMP 0x44000000, 5, 1 + TEST_JUMP 0x44000000, 5, 2 + TEST_JUMP 0x44000000, 5, 3 + */ + + /* Test with link register as the destination. */ + TEST_JUMP 0x44000000, 9, 0 + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/load.S b/sim/testsuite/or1k/load.S new file mode 100644 index 0000000..3644a87 --- /dev/null +++ b/sim/testsuite/or1k/load.S @@ -0,0 +1,358 @@ +/* Tests the load and store instructions. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0xdeadbeef);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0x80000000);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0x80000000);\n +# output: report(0xffffffff);\n +# output: report(0xdeadbeef);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0x80000000);\n +# output: report(0xdeadbeef);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0x80000000);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0x80000000);\n +# output: report(0xffffffff);\n +# output: report(0xdeadbeef);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0x80000000);\n +# output: report(0x000000de);\n +# output: report(0x000000ad);\n +# output: report(0x000000be);\n +# output: report(0x000000ef);\n +# output: report(0x000000ef);\n +# output: report(0x000000be);\n +# output: report(0x000000ad);\n +# output: report(0x000000de);\n +# output: report(0xffffffde);\n +# output: report(0xffffffad);\n +# output: report(0xffffffbe);\n +# output: report(0xffffffef);\n +# output: report(0xffffffef);\n +# output: report(0xffffffbe);\n +# output: report(0xffffffad);\n +# output: report(0xffffffde);\n +# output: report(0x0000dead);\n +# output: report(0x0000beef);\n +# output: report(0x0000beef);\n +# output: report(0x0000dead);\n +# output: report(0xffffdead);\n +# output: report(0xffffbeef);\n +# output: report(0xffffbeef);\n +# output: report(0xffffdead);\n +# output: report(0xa1a2a3a4);\n +# output: report(0xb4b3b2b1);\n +# output: report(0x81828384);\n +# output: report(0x53545152);\n +# output: report(0xa0b0c0d0);\n +# output: report(0xa1b1c1d1);\n +# output: report(0xa3b3c3d3);\n +# output: report(0xa2b2c2d2);\n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + .macro TEST_LW opcode, label, offset + LOAD_IMMEDIATE r5, \label + \opcode r4, \offset(r5) + REPORT_REG_TO_CONSOLE r4 + .endm + + STANDARD_TEST_ENVIRONMENT + + .section .rodata + .balign 4 + +50: .word 0xdeadbeef +51: .word 0x00000000 +52: .word 0x7fffffff +53: .word 0x80000000 +54: .word 0xffffffff + + .section .data + .balign 4 + +buffer1: .word 0x00000000 +buffer2: .word 0x00000000 +buffer3: .word 0x00000000 +buffer4: .word 0x00000000 +buffer5: + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test instruction l.lws */ + + /* Load with zero offset. */ + TEST_LW l.lws 50b, 0 + TEST_LW l.lws 51b, 0 + TEST_LW l.lws 52b, 0 + TEST_LW l.lws 53b, 0 + TEST_LW l.lws 54b, 0 + + /* Load with positive offset. */ + TEST_LW l.lws 50b, 4 + TEST_LW l.lws 50b, 8 + TEST_LW l.lws 50b, 12 + TEST_LW l.lws 50b, 16 + + /* Load with negative offset. */ + TEST_LW l.lws 54b, -16 + TEST_LW l.lws 54b, -12 + TEST_LW l.lws 54b, -8 + TEST_LW l.lws 54b, -4 + + /* TODO: add here test cases to cover unaligned memory accesses + with l.lws. */ + + /* Test instruction l.lwz */ + + /* Load with zero offset. */ + TEST_LW l.lwz 50b, 0 + TEST_LW l.lwz 51b, 0 + TEST_LW l.lwz 52b, 0 + TEST_LW l.lwz 53b, 0 + TEST_LW l.lwz 54b, 0 + + /* Load with positive offset. */ + TEST_LW l.lwz 50b, 4 + TEST_LW l.lwz 50b, 8 + TEST_LW l.lwz 50b, 12 + TEST_LW l.lwz 50b, 16 + + /* Load with negative offset. */ + TEST_LW l.lwz 54b, -16 + TEST_LW l.lwz 54b, -12 + TEST_LW l.lwz 54b, -8 + TEST_LW l.lwz 54b, -4 + + /* TODO: add here test cases to cover unaligned memory accesses + with l.lwz. */ + + /* Test instruction l.lbz */ + + /* Read data at label 50, forwards, byte by byte. */ + LOAD_IMMEDIATE r5, 50b + + l.lbz r4, 0(r5) + REPORT_REG_TO_CONSOLE r4 + + l.lbz r4, 1(r5) + REPORT_REG_TO_CONSOLE r4 + + l.lbz r4, 2(r5) + REPORT_REG_TO_CONSOLE r4 + + l.lbz r4, 3(r5) + REPORT_REG_TO_CONSOLE r4 + + /* Read data at label 50, backwards, byte by byte. */ + LOAD_IMMEDIATE r31, 51b + + l.lbz r3, -1(r31) + REPORT_REG_TO_CONSOLE r3 + + l.lbz r3, -2(r31) + REPORT_REG_TO_CONSOLE r3 + + l.lbz r3, -3(r31) + REPORT_REG_TO_CONSOLE r3 + + l.lbz r3, -4(r31) + REPORT_REG_TO_CONSOLE r3 + + /* Test instruction l.lbs */ + + /* Read data at label 50, forwards, byte by byte. */ + LOAD_IMMEDIATE r5, 50b + + l.lbs r4, 0(r5) + REPORT_REG_TO_CONSOLE r4 + + l.lbs r4, 1(r5) + REPORT_REG_TO_CONSOLE r4 + + l.lbs r4, 2(r5) + REPORT_REG_TO_CONSOLE r4 + + l.lbs r4, 3(r5) + REPORT_REG_TO_CONSOLE r4 + + /* Read data at label 50, backwards, byte by byte. */ + LOAD_IMMEDIATE r31, 51b + + l.lbs r3, -1(r31) + REPORT_REG_TO_CONSOLE r3 + + l.lbs r3, -2(r31) + REPORT_REG_TO_CONSOLE r3 + + l.lbs r3, -3(r31) + REPORT_REG_TO_CONSOLE r3 + + l.lbs r3, -4(r31) + REPORT_REG_TO_CONSOLE r3 + + /* Test instruction l.lhz */ + + /* Read data at label 50, forwards, half-word by half-word. */ + LOAD_IMMEDIATE r5, 50b + + l.lhz r4, 0(r5) + REPORT_REG_TO_CONSOLE r4 + + l.lhz r4, 2(r5) + REPORT_REG_TO_CONSOLE r4 + + /* Read data at label 50, backwards, half-word by half-word. */ + LOAD_IMMEDIATE r31, 51b + + l.lhz r3, -2(r31) + REPORT_REG_TO_CONSOLE r3 + + l.lhz r3, -4(r31) + REPORT_REG_TO_CONSOLE r3 + + /* TODO: add here test cases to cover unaligned memory accesses + with l.lhz. */ + + /* Test instruction l.lhs */ + + /* Read data at label 50, forwards, half-word by half-word. */ + LOAD_IMMEDIATE r5, 50b + + l.lhs r4, 0(r5) + REPORT_REG_TO_CONSOLE r4 + + l.lhs r4, 2(r5) + REPORT_REG_TO_CONSOLE r4 + + /* Read data at label 50, backwards, half-word by half-word. */ + LOAD_IMMEDIATE r31, 51b + + l.lhs r3, -2(r31) + REPORT_REG_TO_CONSOLE r3 + + l.lhs r3, -4(r31) + REPORT_REG_TO_CONSOLE r3 + + /* TODO: add here test cases to cover unaligned memory accesses + with l.lhs. */ + + /* Test instruction l.sb */ + + /* Write 32-bits forwards, byte-to-byte. */ + LOAD_IMMEDIATE r5, buffer1 + + LOAD_IMMEDIATE r10, 0xA1 + LOAD_IMMEDIATE r11, 0xA2 + LOAD_IMMEDIATE r12, 0xA3 + LOAD_IMMEDIATE r13, 0xA4 + + l.sb 0(r5), r10 + l.sb 1(r5), r11 + l.sb 2(r5), r12 + l.sb 3(r5), r13 + + l.lwz r3, 0(r5) + REPORT_REG_TO_CONSOLE r3 + + /* Write 32-bits backwards, byte-to-byte. */ + LOAD_IMMEDIATE r6, buffer2 + + LOAD_IMMEDIATE r10, 0xB1 + LOAD_IMMEDIATE r11, 0xB2 + LOAD_IMMEDIATE r12, 0xB3 + LOAD_IMMEDIATE r13, 0xB4 + + l.sb -1(r6), r10 + l.sb -2(r6), r11 + l.sb -3(r6), r12 + l.sb -4(r6), r13 + + l.lwz r3, 0(r5) + REPORT_REG_TO_CONSOLE r3 + + /* TODO: add here test cases to cover unaligned memory accesses + with l.sb. */ + + /* Test instruction l.sh */ + + /* Write 32-bits forwards, one half-word at a time. */ + LOAD_IMMEDIATE r5, buffer1 + + LOAD_IMMEDIATE r10, 0x8182 + LOAD_IMMEDIATE r11, 0x8384 + + l.sh 0(r5), r10 + l.sh 2(r5), r11 + + l.lwz r3, 0(r5) + REPORT_REG_TO_CONSOLE r3 + + /* Write 32-bits backwards, one half-word at a time. */ + LOAD_IMMEDIATE r6, buffer2 + + LOAD_IMMEDIATE r10, 0x5152 + LOAD_IMMEDIATE r11, 0x5354 + + l.sh -2(r6), r10 + l.sh -4(r6), r11 + + l.lwz r3, 0(r5) + REPORT_REG_TO_CONSOLE r3 + + /* TODO: add here test cases to cover unaligned memory accesses + with l.sh. */ + + /* Test instruction l.sw */ + LOAD_IMMEDIATE r5, buffer1 + LOAD_IMMEDIATE r6, buffer5 + + LOAD_IMMEDIATE r10, 0xA0B0C0D0 + LOAD_IMMEDIATE r11, 0xA1B1C1D1 + LOAD_IMMEDIATE r12, 0xA2B2C2D2 + LOAD_IMMEDIATE r13, 0xA3B3C3D3 + + l.sw 0(r5), r10 + l.sw 4(r5), r11 + l.sw -4(r6), r12 + l.sw -8(r6), r13 + + TEST_LW l.lwz buffer1, 0 + TEST_LW l.lwz buffer2, 0 + TEST_LW l.lwz buffer3, 0 + TEST_LW l.lwz buffer4, 0 + + /* TODO: add here test cases to cover unaligned memory accesses + with l.sw. */ + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/mac.S b/sim/testsuite/or1k/mac.S new file mode 100644 index 0000000..c57a78f --- /dev/null +++ b/sim/testsuite/or1k/mac.S @@ -0,0 +1,778 @@ +/* Tests the MAC instructions. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x00000000);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x0000000c);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x40000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0x00000006);\n +# output: report(0x80000000);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x7ffffffe);\n +# output: report(0x00000000);\n +# output: report(0x80000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x7ffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x0000000c);\n +# output: report(0x00000000);\n +# output: report(0x00000005);\n +# output: report(0xffffffff);\n +# output: report(0xfffffffa);\n +# output: report(0x00000000);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0x7fffffff);\n +# output: report(0xfffffff9);\n +# output: report(0xffffffff);\n +# output: report(0xfffffff9);\n +# output: report(0xfffffffe);\n +# output: report(0xffffffff);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0x80000000);\n +# output: report(0xffffffff);\n +# output: report(0x80000006);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0x7fffffff);\n +# output: report(0xffffffff);\n +# output: report(0x7fffffff);\n +# output: report(0xfffffffe);\n +# output: report(0xffffffff);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x0000000c);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x40000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0x00000006);\n +# output: report(0x80000000);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x7ffffffe);\n +# output: report(0x00000000);\n +# output: report(0x80000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x7ffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x0000000c);\n +# output: report(0x00000000);\n +# output: report(0x00000005);\n +# output: report(0xffffffff);\n +# output: report(0xfffffffa);\n +# output: report(0x00000000);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0x7fffffff);\n +# output: report(0xfffffff9);\n +# output: report(0xffffffff);\n +# output: report(0xfffffff9);\n +# output: report(0xfffffffe);\n +# output: report(0xffffffff);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0x80000000);\n +# output: report(0xffffffff);\n +# output: report(0x80000006);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0x7fffffff);\n +# output: report(0xffffffff);\n +# output: report(0x7fffffff);\n +# output: report(0xfffffffe);\n +# output: report(0xffffffff);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000006);\n +# output: report(0x0000000c);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000006);\n +# output: report(0x00000006);\n +# output: report(0x7ffffffe);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0x7ffffffd);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000006);\n +# output: report(0x0000000c);\n +# output: report(0x00000005);\n +# output: report(0xfffffffa);\n +# output: report(0x00000006);\n +# output: report(0xffffffff);\n +# output: report(0xfffffff9);\n +# output: report(0xfffffff9);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x80000000);\n +# output: report(0x80000006);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0x7fffffff);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0xfffffffa);\n +# output: report(0x00000000);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0xfffffffa);\n +# output: report(0x3fffffff);\n +# output: report(0xfffffffa);\n +# output: report(0xffffffff);\n +# output: report(0xfffffff4);\n +# output: report(0xfffffffe);\n +# output: report(0xffffffff);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0xffffffff);\n +# output: report(0x80000002);\n +# output: report(0xffffffff);\n +# output: report(0x80000004);\n +# output: report(0x00000000);\n +# output: report(0x00000004);\n +# output: report(0x7ffffffe);\n +# output: report(0xffffffff);\n +# output: report(0xffffffff);\n +# output: report(0x80000001);\n +# output: report(0xffffffff);\n +# output: report(0x00000004);\n +# output: report(0xfffffffe);\n +# output: report(0x00000004);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000006);\n +# output: report(0xffffffff);\n +# output: report(0xfffffff9);\n +# output: report(0x00000000);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x0000000c);\n +# output: report(0x00000001);\n +# output: report(0x00000005);\n +# output: report(0x7fffffff);\n +# output: report(0xffffffff);\n +# output: report(0xffffffff);\n +# output: report(0xffffffff);\n +# output: report(0xffffffff);\n +# output: report(0x00000005);\n +# output: report(0x80000000);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x80000006);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x7fffffff);\n +# output: report(0xffffffff);\n +# output: report(0x7fffffff);\n +# output: report(0x80000000);\n +# output: report(0x80000000);\n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + .macro TEST_MACRC mac_hi, mac_lo, op1, op2 + LOAD_IMMEDIATE r2, \mac_hi + MOVE_TO_SPR SPR_MACHI, r2 + LOAD_IMMEDIATE r2, \mac_lo + MOVE_TO_SPR SPR_MACLO, r2 + LOAD_IMMEDIATE r5, \op1 + LOAD_IMMEDIATE r6, \op2 + l.mac r5, r6 + l.macrc r3 + REPORT_REG_TO_CONSOLE r3 + .endm + + .macro TEST_MAC mac_hi, mac_lo, op1, op2 + LOAD_IMMEDIATE r2, \mac_hi + MOVE_TO_SPR SPR_MACHI, r2 + LOAD_IMMEDIATE r2, \mac_lo + MOVE_TO_SPR SPR_MACLO, r2 + LOAD_IMMEDIATE r5, \op1 + LOAD_IMMEDIATE r6, \op2 + l.mac r5, r6 + MOVE_FROM_SPR r3, SPR_MACHI + REPORT_REG_TO_CONSOLE r3 + MOVE_FROM_SPR r3, SPR_MACLO + REPORT_REG_TO_CONSOLE r3 + .endm + + .macro TEST_MACI mac_hi, mac_lo, op1, op2_immediate + LOAD_IMMEDIATE r2, \mac_hi + MOVE_TO_SPR SPR_MACHI, r2 + LOAD_IMMEDIATE r2, \mac_lo + MOVE_TO_SPR SPR_MACLO, r2 + LOAD_IMMEDIATE r5, \op1 + l.maci r5, \op2_immediate + MOVE_FROM_SPR r3, SPR_MACHI + REPORT_REG_TO_CONSOLE r3 + MOVE_FROM_SPR r3, SPR_MACLO + REPORT_REG_TO_CONSOLE r3 + .endm + + .macro TEST_MSB mac_hi, mac_lo, op1, op2 + LOAD_IMMEDIATE r2, \mac_hi + MOVE_TO_SPR SPR_MACHI, r2 + LOAD_IMMEDIATE r2, \mac_lo + MOVE_TO_SPR SPR_MACLO, r2 + LOAD_IMMEDIATE r5, \op1 + LOAD_IMMEDIATE r6, \op2 + l.msb r5, r6 + MOVE_FROM_SPR r3, SPR_MACHI + REPORT_REG_TO_CONSOLE r3 + MOVE_FROM_SPR r3, SPR_MACLO + REPORT_REG_TO_CONSOLE r3 + .endm + + STANDARD_TEST_ENVIRONMENT + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test the l.mac instruction. */ + + /* two small positive numbers */ + + /* MAC two small positive numbers on a zero total */ + TEST_MAC 0x00000000, 0x00000000, 0x00000002, 0x00000003 + + /* MAC two small positive numbers on a small positive total */ + TEST_MAC 0x00000000, 0x00000006, 0x00000002, 0x00000003, + + /* MAC two small positive numbers on a moderate positive total */ + TEST_MAC 0x00000000, 0xfffffffa, 0x00000002, 0x00000003 + + /* MAC two small positive numbers on a large positive total */ + TEST_MAC 0x3fffffff, 0xfffffffa, 0x00000002, 0x00000003 + + /* MAC two small positive numbers on a small negative total */ + TEST_MAC 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003 + + /* MAC two small positive numbers on a moderate negative total */ + TEST_MAC 0xffffffff, 0x00000000, 0x00000002, 0x00000003 + + /* MAC two small positive numbers on a large negative total */ + TEST_MAC 0x80000000, 0x00000000, 0x00000002, 0x00000003 + + /* two moderate positive numbers */ + + /* MAC two moderate positive numbers on a zero total */ + TEST_MAC 0x00000000, 0x00000000, 0x00008001, 0x0000fffe + + /* MAC two moderate positive numbers on a small positive total */ + TEST_MAC 0x00000000, 0x00000002, 0x00008001, 0x0000fffe + + /* MAC two moderate positive numbers on a moderate positive total */ + TEST_MAC 0x00000000, 0x80000002, 0x00008001, 0x0000fffe + + /* MAC two moderate positive numbers on a large positive total */ + TEST_MAC 0x7fffffff, 0x80000001, 0x00008001, 0x0000fffe + + /* MAC two moderate positive numbers on a small negative total */ + TEST_MAC 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe + + /* MAC two moderate positive numbers on a moderate negative total */ + TEST_MAC 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe + + /* MAC two moderate positive numbers on a large negative total */ + TEST_MAC 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe + + /* two small negative numbers */ + + /* MAC two small negative numbers on a zero total */ + TEST_MAC 0x00000000, 0x00000000, 0xfffffffe, 0xfffffffd + + /* MAC two small negative numbers on a small positive total */ + TEST_MAC 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd + + /* MAC two small negative numbers on a small negative total */ + TEST_MAC 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd + + /* one small positive and one small negative */ + + /* MAC one small positive and one small negative number on a zero + total */ + TEST_MAC 0x00000000, 0x00000000, 0x00000002, 0xfffffffd + + /* MAC one small positive and one small negative number on a small + positive total */ + TEST_MAC 0x00000000, 0x0000000c, 0x00000002, 0xfffffffd + + /* MAC one small positive and one small negative number on a + moderate positive total */ + TEST_MAC 0x00000001, 0x00000005, 0x00000002, 0xfffffffd + + /* MAC one small positive and one small negative number on a large + positive total */ + TEST_MAC 0x7fffffff, 0xffffffff, 0x00000002, 0xfffffffd + + /* MAC one small positive and one small negative number on a small + negative total */ + TEST_MAC 0xffffffff, 0xffffffff, 0x00000002, 0xfffffffd + + /* MAC one small positive and one small negative number on a + moderate negative total */ + TEST_MAC 0xffffffff, 0x00000005, 0x00000002, 0xfffffffd + + /* MAC one small positive and one small negative number on a large + negative total */ + TEST_MAC 0x80000000, 0x00000006, 0x00000002, 0xfffffffd + + /* one moderate positive and one moderate negative number */ + + /* MAC one moderate positive and one moderate negative number on a + zero total */ + TEST_MAC 0x00000000, 0x00000000, 0x00008000, 0xffff0000 + + /* MAC one moderate positive and one moderate negative number on a + small positive total */ + TEST_MAC 0x00000000, 0x00000006, 0x00008000, 0xffff0000 + + /* MAC one moderate positive and one moderate negative number on a + moderate positive total */ + TEST_MAC 0x00000000, 0x80000000, 0x00008000, 0xffff0000 + + /* MAC one moderate positive and one moderate negative number on a + large positive total */ + TEST_MAC 0x7fffffff, 0xffffffff, 0x00008000, 0xffff0000 + + /* MAC one moderate positive and one moderate negative number on a + small negative total */ + TEST_MAC 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000 + + /* MAC one moderate positive and one moderate negative number on a + moderate negative total */ + TEST_MAC 0xffffffff, 0x7fffffff, 0x00008000, 0xffff0000 + + /* MAC one moderate positive and one moderate negative number on a + large negative total */ + TEST_MAC 0x80000000, 0x80000000, 0x00008000, 0xffff0000 + + /* Test the l.maci instruction. */ + + /* two small positive numbers */ + + /* MAC two small positive numbers on a zero total */ + TEST_MACI 0x00000000, 0x00000000, 0x00000002, 0x0003 + + /* MAC two small positive numbers on a small positive total */ + TEST_MACI 0x00000000, 0x00000006, 0x00000002, 0x0003 + + /* MAC two small positive numbers on a moderate positive total */ + TEST_MACI 0x00000000, 0xfffffffa, 0x00000002, 0x0003 + + /* MAC two small positive numbers on a large positive total */ + TEST_MACI 0x3fffffff, 0xfffffffa, 0x00000002, 0x0003 + + /* MAC two small positive numbers on a small negative total */ + TEST_MACI 0xffffffff, 0xfffffffa, 0x00000002, 0x0003 + + /* MAC two small positive numbers on a moderate negative total */ + TEST_MACI 0xffffffff, 0x00000000, 0x00000002, 0x0003 + + /* MAC two small positive numbers on a large negative total */ + TEST_MACI 0x80000000, 0x00000000, 0x00000002, 0x0003 + + /* two moderate positive numbers */ + + /* MAC two moderate positive numbers on a zero total */ + TEST_MACI 0x00000000, 0x00000000, 0x00010002, 0x7fff + + /* MAC two moderate positive numbers on a small positive total */ + TEST_MACI 0x00000000, 0x00000002, 0x00010002, 0x7fff + + /* MAC two moderate positive numbers on a moderate positive total */ + TEST_MACI 0x00000000, 0x80000002, 0x00010002, 0x7fff + + /* MAC two moderate positive numbers on a large positive total */ + TEST_MACI 0x7fffffff, 0x80000001, 0x00010002, 0x7fff + + /* MAC two moderate positive numbers on a small negative total */ + TEST_MACI 0xffffffff, 0xffffffff, 0x00010002, 0x7fff + + /* MAC two moderate positive numbers on a moderate negative total */ + TEST_MACI 0xffffffff, 0x80000002, 0x00010002, 0x7fff + + /* MAC two moderate positive numbers on a large negative total */ + TEST_MACI 0xfffffffe, 0x80000002, 0x00010002, 0x7fff + + /* two small negative numbers */ + + /* MAC two small negative numbers on a zero total */ + TEST_MACI 0x00000000, 0x00000000, 0xfffffffe, 0xfffd + + /* MAC two small negative numbers on a small positive total */ + TEST_MACI 0x00000000, 0x00000006, 0xfffffffe, 0xfffd + + /* MAC two small negative numbers on a small negative total */ + TEST_MACI 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffd + + /* one small positive and one small negative */ + + /* MAC one small positive and one small negative number on a zero + total */ + TEST_MACI 0x00000000, 0x00000000, 0x00000002, 0xfffd + + /* MAC one small positive and one small negative number on a small + positive total */ + TEST_MACI 0x00000000, 0x0000000c, 0x00000002, 0xfffd + + /* MAC one small positive and one small negative number on a + moderate positive total */ + TEST_MACI 0x00000001, 0x00000005, 0x00000002, 0xfffd + + /* MAC one small positive and one small negative number on a large + positive total */ + TEST_MACI 0x7fffffff, 0xffffffff, 0x00000002, 0xfffd + + /* MAC one small positive and one small negative number on a small + negative total */ + TEST_MACI 0xffffffff, 0xffffffff, 0x00000002, 0xfffd + + /* MAC one small positive and one small negative number on a + moderate negative total */ + TEST_MACI 0xffffffff, 0x00000005, 0x00000002, 0xfffd + + /* MAC one small positive and one small negative number on a large + negative total */ + TEST_MACI 0x80000000, 0x00000006, 0x00000002, 0xfffd + + /* one moderate positive and one moderate negative */ + + /* MAC one moderate positive and one moderate negative number on a + zero total */ + TEST_MACI 0x00000000, 0x00000000, 0x00010000, 0x8000 + + /* MAC one moderate positive and one moderate negative number on a + small positive total */ + TEST_MACI 0x00000000, 0x00000006, 0x00010000, 0x8000 + + /* MAC one moderate positive and one moderate negative number on a + moderate positive total */ + TEST_MACI 0x00000000, 0x80000000, 0x00010000, 0x8000 + + /* MAC one moderate positive and one moderate negative number on a + large positive total */ + TEST_MACI 0x7fffffff, 0xffffffff, 0x00010000, 0x8000 + + /* MAC one moderate positive and one moderate negative number on a + small negative total */ + TEST_MACI 0xffffffff, 0xffffffff, 0x00010000, 0x8000 + + /* MAC one moderate positive and one moderate negative number on a + moderate negative total */ + TEST_MACI 0xffffffff, 0x7fffffff, 0x00010000, 0x8000 + + /* MAC one moderate positive and one moderate negative number on a + large negative total */ + TEST_MACI 0x80000000, 0x80000000, 0x00010000, 0x8000 + + /* Test the l.macrc instruction. + + Note that these tests use the same input data as the ones for + l.mac above. The results are the same, but only the low 32-bits + are compared. */ + + /* two small positive numbers */ + + /* MAC two small positive numbers on a zero total */ + TEST_MACRC 0x00000000, 0x00000000, 0x00000002, 0x00000003 + + /* MAC two small positive numbers on a small positive total */ + TEST_MACRC 0x00000000, 0x00000006, 0x00000002, 0x00000003 + + /* MAC two small positive numbers on a moderate positive total */ + TEST_MACRC 0x00000000, 0xfffffffa, 0x00000002, 0x00000003 + + /* MAC two small positive numbers on a large positive total */ + TEST_MACRC 0x3fffffff, 0xfffffffa, 0x00000002, 0x00000003 + + /* MAC two small positive numbers on a small negative total */ + TEST_MACRC 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003 + + /* MAC two small positive numbers on a moderate negative total */ + TEST_MACRC 0xffffffff, 0x00000000, 0x00000002, 0x00000003 + + /* MAC two small positive numbers on a large negative total */ + TEST_MACRC 0x80000000, 0x00000000, 0x00000002, 0x00000003 + + /* two moderate positive numbers */ + + /* MAC two moderate positive numbers on a zero total */ + TEST_MACRC 0x00000000, 0x00000000, 0x00008001, 0x0000fffe + + /* MAC two moderate positive numbers on a small positive total */ + TEST_MACRC 0x00000000, 0x00000002, 0x00008001, 0x0000fffe + + /* MAC two moderate positive numbers on a moderate positive total */ + TEST_MACRC 0x00000000, 0x80000002, 0x00008001, 0x0000fffe + + /* MAC two moderate positive numbers on a large positive total */ + TEST_MACRC 0x7fffffff, 0x80000001, 0x00008001, 0x0000fffe + + /* MAC two moderate positive numbers on a small negative total */ + TEST_MACRC 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe + + /* MAC two moderate positive numbers on a moderate negative total */ + TEST_MACRC 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe + + /* MAC two moderate positive numbers on a large negative total */ + TEST_MACRC 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe + + /* two small negative numbers */ + + /* MAC two small negative numbers on a zero total */ + TEST_MACRC 0x00000000, 0x00000000, 0xfffffffe, 0xfffffffd + + /* MAC two small negative numbers on a small positive total */ + TEST_MACRC 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd + + /* MAC two small negative numbers on a small negative total */ + TEST_MACRC 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd + + /* one small positive and one small negative number */ + + /* MAC one small positive and one small negative number on a zero + total */ + TEST_MACRC 0x00000000, 0x00000000, 0x00000002, 0xfffffffd + + /* MAC one small positive and one small negative number on a small + positive total */ + TEST_MACRC 0x00000000, 0x0000000c, 0x00000002, 0xfffffffd + + /* MAC one small positive and one small negative number on a + moderate positive total */ + TEST_MACRC 0x00000001, 0x00000005, 0x00000002, 0xfffffffd + + /* MAC one small positive and one small negative number on a large + positive total */ + TEST_MACRC 0x7fffffff, 0xffffffff, 0x00000002, 0xfffffffd + + /* MAC one small positive and one small negative number on a small + negative total */ + TEST_MACRC 0xffffffff, 0xffffffff, 0x00000002, 0xfffffffd + + /* MAC one small positive and one small negative number on a + moderate negative total */ + TEST_MACRC 0xffffffff, 0x00000005, 0x00000002, 0xfffffffd + + /* MAC one small positive and one small negative number on a large + negative total */ + TEST_MACRC 0x80000000, 0x00000006, 0x00000002, 0xfffffffd + + /* one moderate positive and one moderate negative */ + + /* MAC one moderate positive and one moderate negative number on a + zero total */ + TEST_MACRC 0x00000000, 0x00000000, 0x00008000, 0xffff0000 + + /* MAC one moderate positive and one moderate negative number on a + small positive total */ + TEST_MACRC 0x00000000, 0x00000006, 0x00008000, 0xffff0000 + + /* MAC one moderate positive and one moderate negative number on a + moderate positive total */ + TEST_MACRC 0x00000000, 0x80000000, 0x00008000, 0xffff0000 + + /* MAC one moderate positive and one moderate negative number on a + large positive total */ + TEST_MACRC 0x7fffffff, 0xffffffff, 0x00008000, 0xffff0000 + + /* MAC one moderate positive and one moderate negative number on a + small negative total */ + TEST_MACRC 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000 + + /* MAC one moderate positive and one moderate negative number on a + moderate negative total */ + TEST_MACRC 0xffffffff, 0x7fffffff, 0x00008000, 0xffff0000 + + /* MAC one moderate positive and one moderate negative number on a + large negative total */ + TEST_MACRC 0x80000000, 0x80000000, 0x00008000, 0xffff0000 + + /* Test the l.msb instruction. */ + + /* MSB two small positive numbers on a zero total */ + TEST_MSB 0x00000000, 0x00000000, 0x00000002, 0x00000003 + + /* MSB two small positive numbers on a small positive total */ + TEST_MSB 0x00000000, 0x0000000c, 0x00000002, 0x00000003 + + /* MSB two small positive numbers on a moderate positive total */ + TEST_MSB 0x00000001, 0x00000000, 0x00000002, 0x00000003 + + /* MSB two small positive numbers on a large positive total */ + TEST_MSB 0x40000000, 0x00000000, 0x00000002, 0x00000003 + + /* MSB two small positive numbers on a small negative total */ + TEST_MSB 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003 + + /* MSB two small positive numbers on a moderate negative total */ + TEST_MSB 0xffffffff, 0x00000005, 0x00000002, 0x00000003 + + /* MSB two small positive numbers on a large negative total */ + TEST_MSB 0x80000000, 0x00000006, 0x00000002, 0x00000003 + + /* two moderate positive numbers */ + + /* MSB two moderate positive numbers on a zero total */ + TEST_MSB 0x00000000, 0x00000000, 0x00008001, 0x0000fffe + + /* MSB two moderate positive numbers on a small positive total */ + TEST_MSB 0x00000000, 0x00000002, 0x00008001, 0x0000fffe + + /* MSB two moderate positive numbers on a moderate positive total */ + TEST_MSB 0x00000000, 0x80000002, 0x00008001, 0x0000fffe + + /* MSB two moderate positive numbers on a large positive total */ + TEST_MSB 0x7fffffff, 0x7ffffffd, 0x00008001, 0x0000fffe + + /* MSB two moderate positive numbers on a small negative total */ + TEST_MSB 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe + + /* MSB two moderate positive numbers on a moderate negative total */ + TEST_MSB 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe + + /* MSB two moderate positive numbers on a large negative total */ + TEST_MSB 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe + + /* two small negative numbers */ + + /* MSB two small negative numbers on a zero total */ + TEST_MSB 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd + + /* MSB two small negative numbers on a small positive total */ + TEST_MSB 0x00000000, 0x0000000c, 0xfffffffe, 0xfffffffd + + /* MSB two small negative numbers on a small negative total */ + TEST_MSB 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd + + /* one small positive and one small negative number */ + + /* MSB one small positive and one small negative number on a zero + total */ + TEST_MSB 0x00000000, 0x00000000, 0x00000002, 0xfffffffd + + /* MSB one small positive and one small negative number on a small + positive total */ + TEST_MSB 0x00000000, 0x00000006, 0x00000002, 0xfffffffd + + /* MSB one small positive and one small negative number on a + moderate positive total */ + TEST_MSB 0x00000000, 0xffffffff, 0x00000002, 0xfffffffd + + /* MSB one small positive and one small negative number on a large + positive total */ + TEST_MSB 0x7fffffff, 0xfffffff9, 0x00000002, 0xfffffffd + + /* MSB one small positive and one small negative number on a small + negative total */ + TEST_MSB 0xffffffff, 0xfffffff9, 0x00000002, 0xfffffffd + + /* MSB one small positive and one small negative number on a + moderate negative total */ + TEST_MSB 0xfffffffe, 0xffffffff, 0x00000002, 0xfffffffd + + /* MSB one small positive and one small negative number on a large + negative total */ + TEST_MSB 0x80000000, 0x00000000, 0x00000002, 0xfffffffd + + /* one moderate positive and one moderate negative number */ + + /* MSB one moderate positive and one moderate negative number on a + zero total */ + TEST_MSB 0x00000000, 0x00000000, 0x00008000, 0xffff0000 + + /* MSB one moderate positive and one moderate negative number on a + small positive total */ + TEST_MSB 0x00000000, 0x00000006, 0x00008000, 0xffff0000 + + /* MSB one moderate positive and one moderate negative number on a + moderate positive total */ + TEST_MSB 0x00000000, 0x80000000, 0x00008000, 0xffff0000 + + /* MSB one moderate positive and one moderate negative number on a + large positive total */ + TEST_MSB 0x7fffffff, 0x7fffffff, 0x00008000, 0xffff0000 + + /* MSB one moderate positive and one moderate negative number on a + small negative total */ + TEST_MSB 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000 + + /* MSB one moderate positive and one moderate negative number on a + moderate negative total */ + TEST_MSB 0xfffffffe, 0xffffffff, 0x00008000, 0xffff0000 + + /* MSB one moderate positive and one moderate negative number on a + large negative total */ + TEST_MSB 0x80000000, 0x00000000, 0x00008000, 0xffff0000 + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/mfspr.S b/sim/testsuite/or1k/mfspr.S new file mode 100644 index 0000000..1aa74e1 --- /dev/null +++ b/sim/testsuite/or1k/mfspr.S @@ -0,0 +1,171 @@ +/* Tests instructions l.mfspr and l.mtspr. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x00000000);\n +# output: report(0x00002801);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00002801);\n +# output: report(0x00000000);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00002801);\n +# output: report(0x00002801);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00000801);\n +# output: report(0x00002000);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00002000);\n +# output: report(0x00000801);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00002801);\n +# output: report(0x00000001);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00000800);\n +# output: report(0x00002801);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00000000);\n +# output: report(0x00002801);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00002801);\n +# output: report(0x00000000);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00002801);\n +# output: report(0x00002801);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00000801);\n +# output: report(0x00002000);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00002000);\n +# output: report(0x00000801);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00002801);\n +# output: report(0x00000001);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: report(0x00000800);\n +# output: report(0x00002801);\n +# output: report(0xdeadbeef);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-env.h" + +#define MACLO_VAL 0xdeadbeef + + /* A macro to carry out a test of l.mfspr. + + MACLO (0x2801) is used as the SPR, since it can be read and + cleared using l.macrc and can be set using l.maci. spr_number + and immediate_val_to_or should be chosen to address this + register. + + The value placed in the register is entirely arbitrary - we use + 0xdeadbeef. */ + + .macro TEST_MFSPR spr_number, immediate_val_to_or + REPORT_IMMEDIATE_TO_CONSOLE \spr_number + REPORT_IMMEDIATE_TO_CONSOLE \immediate_val_to_or + /* Write MACLO_VAL to MACLO. */ + l.macrc r2 + LOAD_IMMEDIATE r2, MACLO_VAL + l.maci r2, 1 + LOAD_IMMEDIATE r5, \spr_number + l.mfspr r4, r5, \immediate_val_to_or + REPORT_REG_TO_CONSOLE r4 + PRINT_NEWLINE_TO_CONSOLE + .endm + + /* A macro to carry out a test of l.mtspr + + MACLO (0x2801) is used as the SPR, since it can be read and + cleared using l.macrc and can be set using l.maci. The + arguments spr_number and immediate_val_to_or should be chosen + to address this register. + + The value placed in the register is entirely arbitrary - we use + 0xdeadbeef. */ + + .macro TEST_MTSPR spr_number, immediate_val_to_or + REPORT_IMMEDIATE_TO_CONSOLE \spr_number + REPORT_IMMEDIATE_TO_CONSOLE \immediate_val_to_or + /* Clear MACLO */ + l.macrc r2 + LOAD_IMMEDIATE r4, MACLO_VAL + LOAD_IMMEDIATE r5, \spr_number + l.mtspr r5, r4, \immediate_val_to_or + /* Retrieve MACLO. */ + l.macrc r4 + REPORT_REG_TO_CONSOLE r4 + PRINT_NEWLINE_TO_CONSOLE + .endm + + STANDARD_TEST_ENVIRONMENT + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test the l.mfspr instruction with a range of operands. */ + + /* Move a test value using zero in the register. */ + TEST_MFSPR SPR_VR, SPR_MACLO /* 0x0000, 0x2801 */ + + /* Move a test value using zero as the constant. */ + TEST_MFSPR SPR_MACLO, SPR_VR /* 0x2801, 0x0000 */ + + /* Move a test value using non-zero in both register and constant. */ + + /* Some of these values will not give the correct result if OR + rather than ADD is used to determine the SPR address. */ + TEST_MFSPR SPR_MACLO, SPR_MACLO /* 0x2801, 0x2801 */ + TEST_MFSPR SPR_DMMUPR, SPR_ICCR /* 0x0801, 0x2000 */ + TEST_MFSPR SPR_ICCR, SPR_DMMUPR /* 0x2000, 0x0801 */ + TEST_MFSPR SPR_MACLO, SPR_UPR /* 0x2801, 0x0001 */ + TEST_MFSPR SPR_DMMUCR, SPR_MACLO /* 0x0800, 0x2801 */ + + /* Test the l.mtspr instruction with a range of operands. */ + + /* Move a test value using zero in the register. */ + TEST_MTSPR SPR_VR, SPR_MACLO /* 0x0000, 0x2801 */ + + /* Move a test value using zero as the constant. */ + TEST_MTSPR SPR_MACLO, SPR_VR /* 0x2801, 0x0000 */ + + /* Move a test value using non-zero in both register and constant. */ + + /* Some of these values will not give the correct result if or + rather than add is used to determine the SPR address. */ + TEST_MTSPR SPR_MACLO, SPR_MACLO /* 0x2801, 0x2801 */ + TEST_MTSPR SPR_DMMUPR, SPR_ICCR /* 0x0801, 0x2000 */ + TEST_MTSPR SPR_ICCR, SPR_DMMUPR /* 0x2000, 0x0801 */ + TEST_MTSPR SPR_MACLO, SPR_UPR /* 0x2801, 0x0001 */ + TEST_MTSPR SPR_DMMUCR, SPR_MACLO /* 0x0800, 0x2801 */ + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/mul.S b/sim/testsuite/or1k/mul.S new file mode 100644 index 0000000..e126be8 --- /dev/null +++ b/sim/testsuite/or1k/mul.S @@ -0,0 +1,565 @@ +/* Tests the multiply instructions. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x00000002);\n +# output: report(0x00000003);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00008001);\n +# output: report(0x0000fffe);\n +# output: report(0x7ffffffe);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00008000);\n +# output: report(0x00010000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00010000);\n +# output: report(0x00010000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffffe);\n +# output: report(0xfffffffd);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffff7fff);\n +# output: report(0xffff0002);\n +# output: report(0x7ffffffe);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffff7fff);\n +# output: report(0xffff0000);\n +# output: report(0x80010000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffff0000);\n +# output: report(0xfffeffff);\n +# output: report(0x00010000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000002);\n +# output: report(0xfffffffd);\n +# output: report(0xfffffffa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffff8000);\n +# output: report(0x00010000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffff7fff);\n +# output: report(0x00010000);\n +# output: report(0x7fff0000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x80000000);\n +# output: report(0x00000001);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00008000);\n +# output: report(0x00010000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x00000002);\n +# output: report(0xfffffffd);\n +# output: report(0xfffffffa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffff7fff);\n +# output: report(0xffff0000);\n +# output: report(0x80010000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x00000002);\n +# output: report(0x00000003);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00010002);\n +# output: report(0x00007fff);\n +# output: report(0x7ffffffe);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00020000);\n +# output: report(0x00004000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00040000);\n +# output: report(0x00004000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffffe);\n +# output: report(0x0000fffd);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffefffe);\n +# output: report(0x00008001);\n +# output: report(0x7ffffffe);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffe0000);\n +# output: report(0x0000bfff);\n +# output: report(0x80020000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffdfffe);\n +# output: report(0x00008000);\n +# output: report(0x00010000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000002);\n +# output: report(0x0000fffd);\n +# output: report(0xfffffffa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00010000);\n +# output: report(0x00008000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffdfffc);\n +# output: report(0x00004000);\n +# output: report(0x7fff0000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x80000000);\n +# output: report(0x00000001);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00020000);\n +# output: report(0x00004000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0xfffffffe);\n +# output: report(0x0000fffd);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffdfffe);\n +# output: report(0x00008000);\n +# output: report(0x00010000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x00000002);\n +# output: report(0x00000003);\n +# output: report(0x00000006);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00008001);\n +# output: report(0x0000fffe);\n +# output: report(0x7ffffffe);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00008000);\n +# output: report(0x00010000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00010000);\n +# output: report(0x00010000);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffffe);\n +# output: report(0xfffffffd);\n +# output: report(0x00000006);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffff7fff);\n +# output: report(0xffff0002);\n +# output: report(0x7ffffffe);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffff7fff);\n +# output: report(0xffff0000);\n +# output: report(0x80010000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffff0000);\n +# output: report(0xfffeffff);\n +# output: report(0x00010000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000002);\n +# output: report(0xfffffffd);\n +# output: report(0xfffffffa);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffff8000);\n +# output: report(0x00010000);\n +# output: report(0x80000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffff7fff);\n +# output: report(0x00010000);\n +# output: report(0x7fff0000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x80000000);\n +# output: report(0x00000001);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00008000);\n +# output: report(0x00010000);\n +# output: report(0x80000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000002);\n +# output: report(0xfffffffd);\n +# output: report(0xfffffffa);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0xffff7fff);\n +# output: report(0xffff0000);\n +# output: report(0x80010000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + STANDARD_TEST_ENVIRONMENT + + .section .exception_vectors + + /* Range exception. */ + .org 0xb00 + + /* The handling is a bit dubious at present. We just patch the + instruction with l.nop and restart. This will go wrong in branch + delay slots, but we are not testing that here. */ + l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE + PUSH r2 + PUSH r3 + /* Save the address of the instruction that caused the problem. */ + MOVE_FROM_SPR r2, SPR_EPCR_BASE + LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */ + l.sw 0(r2), r3 + POP r3 + POP r2 + l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE + l.rfe + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test l.mul */ + + /* Multiply two small positive numbers. This should set no flags. + */ + TEST_INST_I32_I32 l.mul, 0x00000002, 0x00000003 + + /* Multiply two quite large positive numbers. This should set no + flags */ + TEST_INST_I32_I32 l.mul, 0x00008001, 0x0000fffe + + /* Multiply two slightly too large positive numbers. This should + set the overflow, but not the carry flag . */ + TEST_INST_I32_I32 l.mul, 0x00008000, 0x00010000 + + /* Multiply two large positive numbers. This should set the + overflow flags (even though the result is not a negative + number. */ + TEST_INST_I32_I32 l.mul, 0x00010000, 0x00010000 + + /* Multiply two small negative numbers. This will set no flags. */ + TEST_INST_I32_I32 l.mul, 0xfffffffe, 0xfffffffd + + /* Multiply two quite large negative numbers. This will no flags. */ + TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0002 + + /* Multiply two slightly too large negative numbers. This should + set the overflow flag. */ + TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0000 + + /* Multiply two large negative numbers. This should set the + both the carry and overflow flags (even though the result is a + positive number. */ + TEST_INST_I32_I32 l.mul, 0xffff0000, 0xfffeffff + + /* Multiply one small negative number and one small positive + number. This will set the no flags. */ + TEST_INST_I32_I32 l.mul, 0x00000002, 0xfffffffd + + /* Multiply one quite large negative number and one quite large + positive number. This will set no flags. */ + TEST_INST_I32_I32 l.mul, 0xffff8000, 0x00010000 + + /* Multiply one slightly too large negative number and one slightly + too large positive number. This should set the overflow flag. */ + TEST_INST_I32_I32 l.mul, 0xffff7fff, 0x00010000 + + /* Multiply the largest negative number by positive unity. This + should set neither carry, nor overflow flag. */ + TEST_INST_I32_I32 l.mul, 0x80000000, 0x00000001 + + /* Check that range exceptions are triggered. */ + + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Check that an overflow alone causes a RANGE Exception. */ + TEST_INST_I32_I32 l.mul, 0x00008000, 0x00010000 + + /* Check multiply of a negative and positive does not cause a RANGE + Exception. */ + TEST_INST_I32_I32 l.mul, 0x00000002, 0xfffffffd + + /* Check that negative overflow causes a RANGE exception. */ + TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0000 + + CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + + /* Test l.muli */ + + /* Multiply two small positive numbers. This should set no flags. */ + TEST_INST_I32_I16 l.muli, 0x00000002, 0x0003 + + /* Multiply two quite large positive numbers. This should set no + flags */ + TEST_INST_I32_I16 l.muli, 0x00010002, 0x7fff + + /* Multiply two slightly too large positive numbers. This should + set the overflow, but not the carry flag. */ + TEST_INST_I32_I16 l.muli, 0x00020000, 0x4000 + + /* Multiply two large positive numbers. This should set the + overflow flag, even though the result is not a negative number. */ + TEST_INST_I32_I16 l.muli, 0x00040000, 0x4000 + + /* Multiply two small negative numbers. This should set no flags. */ + TEST_INST_I32_I16 l.muli, 0xfffffffe, 0xfffd + + /* Multiply two quite large negative numbers. This will set no + flags. */ + TEST_INST_I32_I16 l.muli, 0xfffefffe, 0x8001 + + /* Multiply two slightly too large negative numbers. This should + set the overflow flag. */ + TEST_INST_I32_I16 l.muli, 0xfffe0000, 0xbfff + + /* Multiply two large negative numbers. This should set the + overflow flag, even though the result is a positive number. */ + TEST_INST_I32_I16 l.muli, 0xfffdfffe, 0x8000 + + /* Multiply one small negative number and one small positive + number. This will set no flags. */ + TEST_INST_I32_I16 l.muli, 0x00000002, 0xfffd + + /* Multiply one quite large negative number and one quite large + positive number. This will set no flags. */ + TEST_INST_I32_I16 l.muli, 0x00010000, 0x8000 + + /* Multiply one slightly too large negative number and one slightly + too large positive number. This will set the overflow flag. */ + TEST_INST_I32_I16 l.muli, 0xfffdfffc, 0x4000 + + /* Multiply the largest negative number by positive unity. Should + set neither carry, nor overflow flag. */ + TEST_INST_I32_I16 l.muli, 0x80000000, 0x0001 + + /* Check that range exceptions are triggered. */ + + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Check that an overflow alone causes a RANGE Exception. */ + TEST_INST_I32_I16 l.muli, 0x00020000, 0x4000 + + /* Check that two negatives will not cause a RANGE Exception. */ + TEST_INST_I32_I16 l.muli, 0xfffffffe, 0xfffd + + /* Check that multiply of larget negative and positive numbers causes + a RANGE exception and overflow. */ + TEST_INST_I32_I16 l.muli, 0xfffdfffe, 0x8000 + + CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Test l.mulu */ + + /* Multiply two small positive numbers. This should set no flags. */ + TEST_INST_I32_I32 l.mulu, 0x00000002, 0x00000003 + + /* Multiply two quite large positive numbers. This should set no + flags. */ + TEST_INST_I32_I32 l.mulu, 0x00008001, 0x0000fffe + + /* Multiply two slightly too large positive numbers. This will set + no flags. */ + TEST_INST_I32_I32 l.mulu, 0x00008000, 0x00010000 + + /* Multiply two large positive numbers. This will set the overflow + flag. */ + TEST_INST_I32_I32 l.mulu, 0x00010000, 0x00010000 + + /* Multiply two small negative numbers. This will set the + carry flag, but not the overflow flag. */ + TEST_INST_I32_I32 l.mulu, 0xfffffffe, 0xfffffffd + + /* Multiply two quite large negative numbers. This will set the + carry flag, but not the overflow flag. */ + TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0002 + + /* Multiply two slightly too large negative numbers. This will set + the carry flag, and not the overflow flag */ + TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0000 + + /* Multiply two large negative numbers. This will set the both the + carry flag (even though the result is a positive number.) */ + TEST_INST_I32_I32 l.mulu, 0xffff0000, 0xfffeffff + + /* Multiply one small negative number and one small positive + number. This will set the carry flag, but not the overflow + flag. */ + TEST_INST_I32_I32 l.mulu, 0x00000002, 0xfffffffd + + /* Multiply one quite large negative number and one quite large + positive number. This will set the carry flag, but not the + overflow flag. */ + TEST_INST_I32_I32 l.mulu, 0xffff8000, 0x00010000 + + /* Multiply one slightly too large negative number and one slightly + too large positive number. This will set the carry flag, but + not the overflow flag. */ + TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0x00010000 + + /* Multiply the largest negative number by positive unity. Should + set neither carry, nor overflow flag. */ + TEST_INST_I32_I32 l.mulu, 0x80000000, 0x00000001 + + /* Check that range exceptions are never triggered. */ + + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Check that what would cause an overflow alone in 2's complement + does not cause a RANGE Exception. */ + TEST_INST_I32_I32 l.mulu, 0x00008000, 0x00010000 + + /* Check that a carry causes a RANGE Exception. */ + TEST_INST_I32_I32 l.mulu, 0x00000002, 0xfffffffd + + /* Check that what would cause an overflow and carry in 2's + complement causes a RANGE Exception. */ + TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0000 + + CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/or.S b/sim/testsuite/or1k/or.S new file mode 100644 index 0000000..b20bec8 --- /dev/null +++ b/sim/testsuite/or1k/or.S @@ -0,0 +1,199 @@ +/* Tests instructions l.or, l.ori. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0xffffffff);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0xaaaaaaaa);\n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x55555555);\n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x55555555);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0xb38f0f83);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0xc4c70f07);\n +# output: report(0xccf7ff7f);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x38f0f83b);\n +# output: report(0xbbffffbb);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0x0000ffff);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x0000aaaa);\n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x00005555);\n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x00005555);\n +# output: report(0xaaaaffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000f83);\n +# output: report(0x4c70ffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000f07);\n +# output: report(0x4c70ff7f);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000f83b);\n +# output: report(0xb38fffbb);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + STANDARD_TEST_ENVIRONMENT + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Always set OVE. We should never trigger an exception, even if + this bit is set. */ + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Test the l.or instruction with a range of operands. */ + + TEST_INST_I32_I32 l.or, 0x00000000, 0x00000000 + TEST_INST_I32_I32 l.or, 0xffffffff, 0xffffffff + TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0x00000000 + TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0xaaaaaaaa + TEST_INST_I32_I32 l.or, 0x55555555, 0x00000000 + TEST_INST_I32_I32 l.or, 0x55555555, 0x55555555 + TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0x55555555 + TEST_INST_I32_I32 l.or, 0x4c70f07c, 0xb38f0f83 + TEST_INST_I32_I32 l.or, 0x4c70f07c, 0xc4c70f07 + TEST_INST_I32_I32 l.or, 0xb38f0f83, 0x38f0f83b + + /* Test the l.ori instruction with a range of operands. */ + TEST_INST_I32_I16 l.ori, 0x00000000, 0x0000 + TEST_INST_I32_I16 l.ori, 0xffffffff, 0xffff + TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0x0000 + TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0xaaaa + TEST_INST_I32_I16 l.ori, 0x55555555, 0x0000 + TEST_INST_I32_I16 l.ori, 0x55555555, 0x5555 + TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0x5555 + TEST_INST_I32_I16 l.ori, 0x4c70f07c, 0x0f83 + TEST_INST_I32_I16 l.ori, 0x4c70f07c, 0x0f07 + TEST_INST_I32_I16 l.ori, 0xb38f0f83, 0xf83b + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/or1k-asm-test-env.h b/sim/testsuite/or1k/or1k-asm-test-env.h new file mode 100644 index 0000000..bbaeeeb --- /dev/null +++ b/sim/testsuite/or1k/or1k-asm-test-env.h @@ -0,0 +1,59 @@ +/* Testsuite macros for OpenRISC. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef OR1K_ASM_TEST_ENV_H +#define OR1K_ASM_TEST_ENV_H + +#include "or1k-asm.h" +#include "or1k-asm-test.h" + + .macro STANDARD_TEST_HEADER + /* Without the "a" (allocatable) flag, this section gets some + default flags and is discarded by objcopy when flattening to + the binary file. */ + .section .exception_vectors, "ax" + .org 0x100 + .global _start +_start: + /* Clear R0 on start-up. There is no guarantee that R0 is hardwired + to zero and indeed it is not when simulating. */ + CLEAR_REG r0 + OR1K_DELAYED_NOP(l.j test_startup) + .section .text +test_startup: + .endm + + .macro STANDARD_TEST_BODY + LOAD_IMMEDIATE STACK_POINTER_R1, stack_begin + CLEAR_BSS r3, r4 + CALL r3, start_tests + EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_SUCCESS + .section .stack + .space 4096 /* We need more than EXCEPTION_STACK_SKIP_SIZE bytes. */ +stack_begin: + .endm + + .macro STANDARD_TEST_ENVIRONMENT + /* One of the test cases needs to do some tests before setting up + the stack and so on. That's the reason this macro is split into + 2 parts allowing the caller to inject code between the 2 + initialisation phases. */ + STANDARD_TEST_HEADER + STANDARD_TEST_BODY + .endm + +#endif /* OR1K_ASM_TEST_ENV_H */ diff --git a/sim/testsuite/or1k/or1k-asm-test-helpers.h b/sim/testsuite/or1k/or1k-asm-test-helpers.h new file mode 100644 index 0000000..699479c --- /dev/null +++ b/sim/testsuite/or1k/or1k-asm-test-helpers.h @@ -0,0 +1,121 @@ +/* Testsuite helpers for OpenRISC. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef OR1K_ASM_TEST_HELPERS_H +#define OR1K_ASM_TEST_HELPERS_H + +#include "spr-defs.h" +#include "or1k-asm-test-env.h" + + /* During exception handling the instruction under test is + overwritten with a nop. Here we check if that is the case and + report. */ + + .macro REPORT_EXCEPTION instruction_addr + PUSH r2 + PUSH r3 + LOAD_IMMEDIATE r3, \instruction_addr + l.lws r2, 0(r3) + LOAD_IMMEDIATE r3, 0x15000000 /* l.nop */ + l.sfeq r2, r3 + OR1K_DELAYED_NOP (l.bnf 1f) + REPORT_IMMEDIATE_TO_CONSOLE 0x00000001 + OR1K_DELAYED_NOP (l.j 2f) +1: + REPORT_IMMEDIATE_TO_CONSOLE 0x00000000 +2: + POP r3 + POP r2 + .endm + + /* Test that will set and clear sr flags, run instruction report + the result and whether or not there was an exception. + + Arguments: + flags_to_set - sr flags to set + flags_to_clear - sr flags to clear + opcode - the instruction to execute + op1 - first argument to the instruction + op2 - second argument to the function + + Reports: + report(0x00000001);\n op1 + report(0x00000002);\n op1 + report(0x00000003);\n result + report(0x00000000);\n 1 if carry + report(0x00000000);\n 1 if overflow + report(0x00000000);\n 1 if exception + \n */ + + .macro TEST_INST_FF_I32_I32 flags_to_set, flags_to_clear, opcode, op1, op2 + LOAD_IMMEDIATE r5, \op1 + LOAD_IMMEDIATE r6, \op2 + REPORT_REG_TO_CONSOLE r5 + REPORT_REG_TO_CONSOLE r6 + /* Clear the last exception address. */ + MOVE_TO_SPR SPR_EPCR_BASE, ZERO_R0 + SET_SPR_SR_FLAGS \flags_to_set , r2, r3 + CLEAR_SPR_SR_FLAGS \flags_to_clear, r2, r3 +\@1$: \opcode r4, r5, r6 + MOVE_FROM_SPR r2, SPR_SR /* Save the flags. */ + REPORT_REG_TO_CONSOLE r4 + + REPORT_BIT_TO_CONSOLE r2, SPR_SR_CY + REPORT_BIT_TO_CONSOLE r2, SPR_SR_OV + REPORT_EXCEPTION \@1$ + PRINT_NEWLINE_TO_CONSOLE + .endm + + .macro TEST_INST_FF_I32_I16 flags_to_set, flags_to_clear, opcode, op1, op2 + LOAD_IMMEDIATE r5, \op1 + REPORT_REG_TO_CONSOLE r5 + REPORT_IMMEDIATE_TO_CONSOLE \op2 + SET_SPR_SR_FLAGS \flags_to_set , r2, r3 + CLEAR_SPR_SR_FLAGS \flags_to_clear, r2, r3 + /* Clear the last exception address. */ + MOVE_TO_SPR SPR_EPCR_BASE, ZERO_R0 +\@1$: \opcode r4, r5, \op2 + MOVE_FROM_SPR r2, SPR_SR /* Save the flags. */ + REPORT_REG_TO_CONSOLE r4 + REPORT_BIT_TO_CONSOLE r2, SPR_SR_CY + REPORT_BIT_TO_CONSOLE r2, SPR_SR_OV + REPORT_EXCEPTION \@1$ + PRINT_NEWLINE_TO_CONSOLE + .endm + + .macro TEST_INST_I32_I32 opcode, op1, op2 + TEST_INST_FF_I32_I32 0, 0, \opcode, \op1, \op2 + .endm + + .macro TEST_INST_I32_I16 opcode, op1, op2 + TEST_INST_FF_I32_I16 0, 0, \opcode, \op1, \op2 + .endm + + .macro CHECK_CARRY_AND_OVERFLOW_NOT_SET overwritten_reg1, overwritten_reg2 + MOVE_FROM_SPR \overwritten_reg1, SPR_SR + + LOAD_IMMEDIATE \overwritten_reg2, SPR_SR_CY + SPR_SR_OV + l.and \overwritten_reg1, \overwritten_reg1, \overwritten_reg2 + l.sfne \overwritten_reg1, ZERO_R0 + + OR1K_DELAYED_NOP (l.bnf \@2$) + + EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR +\@2$: + .endm + +#endif /* OR1K_ASM_TEST_HELPERS_H */ diff --git a/sim/testsuite/or1k/or1k-asm-test.h b/sim/testsuite/or1k/or1k-asm-test.h new file mode 100644 index 0000000..3525673 --- /dev/null +++ b/sim/testsuite/or1k/or1k-asm-test.h @@ -0,0 +1,226 @@ +/* Testsuite architecture macros for OpenRISC. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef OR1K_ASM_TEST_H +#define OR1K_ASM_TEST_H + +#include "spr-defs.h" + +/* Register definitions */ + +/* The "jump and link" instructions store the return address in R9. */ +#define LINK_REGISTER_R9 r9 + +/* These register definitions match the ABI. */ +#define ZERO_R0 r0 +#define STACK_POINTER_R1 r1 +#define FRAME_POINTER_R2 r2 +#define RETURN_VALUE_R11 r11 + + /* Load/move/clear helpers */ + + .macro LOAD_IMMEDIATE reg, val + l.movhi \reg, hi ( \val ) + l.ori \reg, \reg, lo ( \val ) + .endm + + .macro MOVE_REG dest_reg, src_reg + .ifnes "\dest_reg","\src_reg" + l.ori \dest_reg, \src_reg, 0 + .endif + .endm + + .macro CLEAR_REG reg + l.movhi \reg, 0 + .endm + + .macro MOVE_FROM_SPR reg, spr_reg + l.mfspr \reg, ZERO_R0, \spr_reg + .endm + + .macro MOVE_TO_SPR spr_reg, reg + l.mtspr ZERO_R0, \reg, \spr_reg + .endm + + .macro SET_SPR_SR_FLAGS flag_mask, scratch_reg_1, scratch_reg_2 + /* We cannot use PUSH and POP here because some flags like Carry + would get overwritten. */ + + /* We could optimise this routine, as instruction l.mtspr already + does a logical OR. */ + MOVE_FROM_SPR \scratch_reg_2, SPR_SR + LOAD_IMMEDIATE \scratch_reg_1, \flag_mask + l.or \scratch_reg_2, \scratch_reg_2, \scratch_reg_1 + MOVE_TO_SPR SPR_SR, \scratch_reg_2 + .endm + + .macro CLEAR_SPR_SR_FLAGS flag_mask, scratch_reg_1, scratch_reg_2 + /* We cannot use PUSH and POP here because some flags like Carry + would get overwritten. */ + + MOVE_FROM_SPR \scratch_reg_2, SPR_SR + LOAD_IMMEDIATE \scratch_reg_1, ~\flag_mask + l.and \scratch_reg_2, \scratch_reg_2, \scratch_reg_1 + MOVE_TO_SPR SPR_SR, \scratch_reg_2 + + .endm + + /* Stack helpers */ + +/* This value is defined in the OpenRISC 1000 specification. */ +#define EXCEPTION_STACK_SKIP_SIZE 128 + + /* WARNING: Functions without prolog cannot use these PUSH or POP + macros. + + PERFORMANCE WARNING: These PUSH/POP macros are convenient, but + can lead to slow code. If you need to PUSH or POP several + registers, it's faster to use non-zero offsets when + loading/storing and then increment/decrement the stack pointer + just once. */ + + .macro PUSH reg + l.addi STACK_POINTER_R1, STACK_POINTER_R1, -4 + l.sw 0(STACK_POINTER_R1), \reg + .endm + + /* WARNING: see the warnings for PUSH. */ + .macro POP reg + l.lwz \reg, 0(STACK_POINTER_R1) + l.addi STACK_POINTER_R1, STACK_POINTER_R1, 4 + .endm + +/* l.nop definitions for simulation control and console output. */ + +/* Register definitions for the simulation l.nop codes. */ +#define NOP_REPORT_R3 r3 +#define NOP_EXIT_R3 r3 + +/* SEC = Simulation Exit Code */ +#define SEC_SUCCESS 0 +#define SEC_RETURNED_FROM_MAIN 1 +#define SEC_GENERIC_ERROR 2 + + /* When running under the simulator, this l.nop code terminates the + simulation. */ + .macro EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE immediate_value + LOAD_IMMEDIATE NOP_EXIT_R3, \immediate_value + l.nop 1 + .endm + + .macro EXIT_SIMULATION_WITH_REG_EXIT_CODE reg + MOVE_REG NOP_EXIT_R3, \reg + l.nop 1 + .endm + + /* When running under the simulator, this l.nop code prints the + value of R3 to the console. */ + .macro REPORT_TO_CONSOLE + l.nop 2 + .endm + + /* NOTE: The stack must be set up, as this macro uses PUSH and POP. */ + .macro REPORT_REG_TO_CONSOLE reg + .ifeqs "\reg","r3" + /* Nothing more to do here, R3 is the register that gets printed. */ + REPORT_TO_CONSOLE + .else + PUSH NOP_REPORT_R3 + MOVE_REG NOP_REPORT_R3, \reg + REPORT_TO_CONSOLE + POP NOP_REPORT_R3 + .endif + .endm + + /* NOTE: The stack must be set up, as this macro uses PUSH and POP. */ + .macro REPORT_IMMEDIATE_TO_CONSOLE val + PUSH NOP_REPORT_R3 + LOAD_IMMEDIATE NOP_REPORT_R3, \val + REPORT_TO_CONSOLE + POP NOP_REPORT_R3 + .endm + + .macro PRINT_NEWLINE_TO_CONSOLE + PUSH r3 + LOAD_IMMEDIATE r3, 0x0A + l.nop 4 + POP r3 + .endm + + /* If SR[F] is set, writes 0x00000001 to the console, otherwise it + writes 0x00000000. */ + .macro REPORT_SRF_TO_CONSOLE + OR1K_DELAYED_NOP (l.bnf \@1$) + REPORT_IMMEDIATE_TO_CONSOLE 0x00000001 + OR1K_DELAYED_NOP (l.j \@2$) +\@1$: + REPORT_IMMEDIATE_TO_CONSOLE 0x00000000 +\@2$: + .endm + + /* If the given register is 0, writes 0x00000000 to the console, + otherwise it writes 0x00000001. */ + .macro REPORT_BOOL_TO_CONSOLE reg + l.sfne \reg, ZERO_R0 + REPORT_SRF_TO_CONSOLE + .endm + + /* Writes to the console the value of the given register bit. */ + .macro REPORT_BIT_TO_CONSOLE reg, single_bit_mask + PUSH r2 + PUSH r3 + PUSH r4 + MOVE_REG r2, \reg + LOAD_IMMEDIATE r4, \single_bit_mask + l.and r3, r2, r4 + REPORT_BOOL_TO_CONSOLE r3 + POP r4 + POP r3 + POP r2 + .endm + + /* Jump helpers */ + + .macro CALL overwritten_reg, subroutine_name + LOAD_IMMEDIATE \overwritten_reg, \subroutine_name + OR1K_DELAYED_NOP (l.jalr \overwritten_reg) + .endm + + .macro RETURN_TO_LINK_REGISTER_R9 + OR1K_DELAYED_NOP (l.jr LINK_REGISTER_R9) + .endm + + /* Clear the BSS section on start-up */ + + .macro CLEAR_BSS overwritten_reg1, overwritten_reg2 + LOAD_IMMEDIATE \overwritten_reg1, _bss_begin + LOAD_IMMEDIATE \overwritten_reg2, _bss_end + l.sfgeu \overwritten_reg1, \overwritten_reg2 + OR1K_DELAYED_NOP (l.bf bss_is_empty) +bss_clear_loop: + /* Possible optimisation to investigate: + move "l.sw 0(\overwritten_reg1), r0" to the jump delay slot as + "l.sw -4(\overwritten_reg1), r0" or similar. But keep in mind that + there are plans to remove the jump delay slot. */ + l.sw 0(\overwritten_reg1), r0 + l.addi \overwritten_reg1, \overwritten_reg1, 4 + l.sfgtu \overwritten_reg2, \overwritten_reg1 + OR1K_DELAYED_NOP (l.bf bss_clear_loop) +bss_is_empty: + .endm + +#endif /* OR1K_ASM_TEST_H */ diff --git a/sim/testsuite/or1k/or1k-asm.h b/sim/testsuite/or1k/or1k-asm.h new file mode 100644 index 0000000..37f4461 --- /dev/null +++ b/sim/testsuite/or1k/or1k-asm.h @@ -0,0 +1,37 @@ +/* Testsuite assembly helpers for OpenRISC. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef OR1K_ASM_H +#define OR1K_ASM_H + +#define OR1K_INST(...) __VA_ARGS__ + +#if defined(__OR1K_NODELAY__) +#define OR1K_DELAYED(a, b) a; b +#define OR1K_DELAYED_NOP(a) a +.nodelay +#elif defined(__OR1K_DELAY__) +#define OR1K_DELAYED(a, b) b; a +#define OR1K_DELAYED_NOP(a) a; l.nop +#elif defined(__OR1K_DELAY_COMPAT__) +#define OR1K_DELAYED(a, b) a; b; l.nop +#define OR1K_DELAYED_NOP(a) a; l.nop +#else +#error One of __OR1K_NODELAY__, __OR1K_DELAY__, or __OR1K_DELAY_COMPAT__ must be defined +#endif + +#endif /* OR1K_ASM_H */ diff --git a/sim/testsuite/or1k/or1k-test.ld b/sim/testsuite/or1k/or1k-test.ld new file mode 100644 index 0000000..fe6fd73 --- /dev/null +++ b/sim/testsuite/or1k/or1k-test.ld @@ -0,0 +1,75 @@ +/* Test linker script for OpenRISC. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +MEMORY +{ + /* The exception vectors actually start at 0x100, but if you specify + that address here, the "--output-target binary" step will start from + address 0 with the contents meant for address 0x100. */ + exception_vectors : ORIGIN = 0 , LENGTH = 8K + ram : ORIGIN = 8K, LENGTH = 2M - 8K +} + +SECTIONS +{ + .exception_vectors : + { + KEEP(*(.exception_vectors)) + } > exception_vectors + + .text : + { + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + } > ram + + .data : + { + *(.data) + *(.data.*) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + + /* WARNING about section size alignment: + The start-up assembly code can only clear BSS section sizes + which are aligned to 4 bytes. However, the size of the BSS + section may not be aligned, therefore up to 3 bytes more could + be zeroed on start-up. This is normally not an issue, as the + start of the next section is usually aligned too, so those extra + bytes should be just padding. I did try the following trick to + align the BSS section size, to no avail: + + . = ALIGN(., 4); + */ + } > ram + + _bss_begin = ADDR(.bss); + _bss_end = _bss_begin + SIZEOF(.bss); + + .stack ALIGN(16) (NOLOAD): + { + *(.stack) + } > ram +} + +ENTRY(_start) /* Otherwise, --gc-sections would throw everything away. */ diff --git a/sim/testsuite/or1k/ror.S b/sim/testsuite/or1k/ror.S new file mode 100644 index 0000000..ce47c12 --- /dev/null +++ b/sim/testsuite/or1k/ror.S @@ -0,0 +1,159 @@ +/* Tests instructions l.ror and l.rori. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0xb38f0f83);\n +# output: report(0x00000000);\n +# output: report(0xb38f0f83);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000001);\n +# output: report(0xd9c787c1);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000004);\n +# output: report(0x3b38f0f8);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000010);\n +# output: report(0x0f83b38f);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000001f);\n +# output: report(0x671e1f07);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000021);\n +# output: report(0xd9c787c1);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00002224);\n +# output: report(0x3b38f0f8);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00f789f0);\n +# output: report(0x0f83b38f);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0xffffffff);\n +# output: report(0x671e1f07);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000000);\n +# output: report(0xb38f0f83);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000001);\n +# output: report(0xd9c787c1);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000004);\n +# output: report(0x3b38f0f8);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000010);\n +# output: report(0x0f83b38f);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000001f);\n +# output: report(0x671e1f07);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000021);\n +# output: report(0xd9c787c1);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000024);\n +# output: report(0x3b38f0f8);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000030);\n +# output: report(0x0f83b38f);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000003f);\n +# output: report(0x671e1f07);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-env.h" + + .macro TEST_ROR op1, op2, res + /* Note that 'res' is not used here. We could stop using the + .TestResults file and use 'res' here instead. */ + LOAD_IMMEDIATE r5, \op1 + LOAD_IMMEDIATE r6, \op2 + REPORT_REG_TO_CONSOLE r5 + REPORT_REG_TO_CONSOLE r6 + l.ror r4, r5, r6 + REPORT_REG_TO_CONSOLE r4 + PRINT_NEWLINE_TO_CONSOLE + .endm + + .macro TEST_RORI op1, op2, res + /* Note that 'res' is not used here. We could stop using the + .TestResults file and use 'res' here instead. */ + LOAD_IMMEDIATE r5, \op1 + REPORT_REG_TO_CONSOLE r5 + REPORT_IMMEDIATE_TO_CONSOLE \op2 + l.rori r4, r5, \op2 + REPORT_REG_TO_CONSOLE r4 + PRINT_NEWLINE_TO_CONSOLE + .endm + + STANDARD_TEST_ENVIRONMENT + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test the l.ror instruction. */ + + /* Rotate by zero */ + TEST_ROR 0xb38f0f83, 0x00000000, 0xb38f0f83 + + /* Rotate by amounts in the 1 - 31 range. */ + TEST_ROR 0xb38f0f83, 0x00000001, 0xd9c787c1 + TEST_ROR 0xb38f0f83, 0x00000004, 0x3b38f0f8 + TEST_ROR 0xb38f0f83, 0x00000010, 0x0f83b38f + TEST_ROR 0xb38f0f83, 0x0000001f, 0x671e1f07 + + /* Rotate by larger amounts - should be masked. */ + TEST_ROR 0xb38f0f83, 0x00000021, 0xd9c787c1 + TEST_ROR 0xb38f0f83, 0x00002224, 0x3b38f0f8 + TEST_ROR 0xb38f0f83, 0x00f789f0, 0x0f83b38f + TEST_ROR 0xb38f0f83, 0xffffffff, 0x671e1f07 + + /* Test the l.rori instruction. */ + + /* Rotate by zero */ + TEST_RORI 0xb38f0f83, 0x00000000, 0xb38f0f83 + + /* Rotate by amounts in the 1 - 31 range. */ + TEST_RORI 0xb38f0f83, 0x01, 0xd9c787c1 + TEST_RORI 0xb38f0f83, 0x04, 0x3b38f0f8 + TEST_RORI 0xb38f0f83, 0x10, 0x0f83b38f + TEST_RORI 0xb38f0f83, 0x1f, 0x671e1f07 + + /* Rotate by larger amounts (32 - 63) - should be masked. */ + TEST_RORI 0xb38f0f83, 0x21, 0xd9c787c1 + TEST_RORI 0xb38f0f83, 0x24, 0x3b38f0f8 + TEST_RORI 0xb38f0f83, 0x30, 0x0f83b38f + TEST_RORI 0xb38f0f83, 0x3f, 0x671e1f07 + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/shift.S b/sim/testsuite/or1k/shift.S new file mode 100644 index 0000000..a98da29 --- /dev/null +++ b/sim/testsuite/or1k/shift.S @@ -0,0 +1,541 @@ +/* Tests the shift instructions. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0xb38f0f83);\n +# output: report(0x00000000);\n +# output: report(0xb38f0f83);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000001);\n +# output: report(0x671e1f06);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000004);\n +# output: report(0x38f0f830);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000010);\n +# output: report(0x0f830000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000001f);\n +# output: report(0x80000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000021);\n +# output: report(0x671e1f06);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00002224);\n +# output: report(0x38f0f830);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00f789f0);\n +# output: report(0x0f830000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0xffffffff);\n +# output: report(0x80000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000000);\n +# output: report(0xb38f0f83);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000001);\n +# output: report(0x671e1f06);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000004);\n +# output: report(0x38f0f830);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000010);\n +# output: report(0x0f830000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000001f);\n +# output: report(0x80000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000021);\n +# output: report(0x671e1f06);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000024);\n +# output: report(0x38f0f830);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000030);\n +# output: report(0x0f830000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000003f);\n +# output: report(0x80000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000000);\n +# output: report(0xb38f0f83);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000001);\n +# output: report(0xd9c787c1);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000004);\n +# output: report(0xfb38f0f8);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000010);\n +# output: report(0xffffb38f);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000001f);\n +# output: report(0xffffffff);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000001);\n +# output: report(0x2638783e);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000004);\n +# output: report(0x04c70f07);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000010);\n +# output: report(0x00004c70);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x0000001f);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000021);\n +# output: report(0xd9c787c1);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00002224);\n +# output: report(0xfb38f0f8);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00f789f0);\n +# output: report(0xffffb38f);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0xffffffff);\n +# output: report(0xffffffff);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000021);\n +# output: report(0x2638783e);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00002224);\n +# output: report(0x04c70f07);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00f789f0);\n +# output: report(0x00004c70);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000000);\n +# output: report(0xb38f0f83);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000001);\n +# output: report(0xd9c787c1);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000004);\n +# output: report(0xfb38f0f8);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000010);\n +# output: report(0xffffb38f);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000001f);\n +# output: report(0xffffffff);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000001);\n +# output: report(0x2638783e);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000004);\n +# output: report(0x04c70f07);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000010);\n +# output: report(0x00004c70);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x0000001f);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000021);\n +# output: report(0xd9c787c1);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000024);\n +# output: report(0xfb38f0f8);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000030);\n +# output: report(0xffffb38f);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000003f);\n +# output: report(0xffffffff);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000021);\n +# output: report(0x2638783e);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000024);\n +# output: report(0x04c70f07);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000030);\n +# output: report(0x00004c70);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x0000003f);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000000);\n +# output: report(0xb38f0f83);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000001);\n +# output: report(0x59c787c1);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000004);\n +# output: report(0x0b38f0f8);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000010);\n +# output: report(0x0000b38f);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000001f);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000001);\n +# output: report(0x2638783e);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000004);\n +# output: report(0x04c70f07);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000010);\n +# output: report(0x00004c70);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x0000001f);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000021);\n +# output: report(0x59c787c1);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00002224);\n +# output: report(0x0b38f0f8);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00f789f0);\n +# output: report(0x0000b38f);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0xffffffff);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000021);\n +# output: report(0x2638783e);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00002224);\n +# output: report(0x04c70f07);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00f789f0);\n +# output: report(0x00004c70);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000000);\n +# output: report(0xb38f0f83);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000001);\n +# output: report(0x59c787c1);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000004);\n +# output: report(0x0b38f0f8);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000010);\n +# output: report(0x0000b38f);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000001f);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000001);\n +# output: report(0x2638783e);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000004);\n +# output: report(0x04c70f07);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000010);\n +# output: report(0x00004c70);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x0000001f);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000021);\n +# output: report(0x59c787c1);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000024);\n +# output: report(0x0b38f0f8);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x00000030);\n +# output: report(0x0000b38f);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000003f);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000021);\n +# output: report(0x2638783e);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000024);\n +# output: report(0x04c70f07);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000030);\n +# output: report(0x00004c70);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x0000003f);\n +# output: report(0x00000000);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + .macro TEST_SHIFT opcode, op1, op2 + LOAD_IMMEDIATE r5, \op1 + LOAD_IMMEDIATE r6, \op2 + REPORT_REG_TO_CONSOLE r5 + REPORT_REG_TO_CONSOLE r6 + \opcode r4, r5, r6 + CHECK_CARRY_AND_OVERFLOW_NOT_SET r2, r3 + REPORT_REG_TO_CONSOLE r4 + PRINT_NEWLINE_TO_CONSOLE + .endm + + .macro TEST_SHIFT_I opcode, op1, op2 + LOAD_IMMEDIATE r5, \op1 + REPORT_REG_TO_CONSOLE r5 + REPORT_IMMEDIATE_TO_CONSOLE \op2 + \opcode r4, r5, \op2 + CHECK_CARRY_AND_OVERFLOW_NOT_SET r2, r3 + REPORT_REG_TO_CONSOLE r4 + PRINT_NEWLINE_TO_CONSOLE + .endm + + STANDARD_TEST_ENVIRONMENT + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Always set OVE. We should never trigger an exception, even if + this bit is set. */ + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Test l.sll */ + + /* Shift left by zero. */ + TEST_SHIFT l.sll, 0xb38f0f83, 0x00000000 + + /* Shift left by amounts in the 1-31 range. */ + TEST_SHIFT l.sll, 0xb38f0f83, 0x00000001 + TEST_SHIFT l.sll, 0xb38f0f83, 0x00000004 + TEST_SHIFT l.sll, 0xb38f0f83, 0x00000010 + TEST_SHIFT l.sll, 0xb38f0f83, 0x0000001f + + /* Shift left by larger amounts - should be masked. */ + TEST_SHIFT l.sll, 0xb38f0f83, 0x00000021 + TEST_SHIFT l.sll, 0xb38f0f83, 0x00002224 + TEST_SHIFT l.sll, 0xb38f0f83, 0x00f789f0 + TEST_SHIFT l.sll, 0xb38f0f83, 0xffffffff + + /* Test l.slli */ + + /* Shift left by zero. */ + TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0000 + + /* Shift left by amounts in the 1-31 range. */ + TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0001 + TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0004 + TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0010 + TEST_SHIFT_I l.slli, 0xb38f0f83, 0x001f + + /* Shift left by larger amounts - should be masked. */ + TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0021 + TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0024 + TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0030 + TEST_SHIFT_I l.slli, 0xb38f0f83, 0x003f + + /* Test l.sra */ + + /* Shift right by zero. */ + TEST_SHIFT l.sra, 0xb38f0f83, 0x00000000 + + /* Shift right by amounts in the 1-31 range. */ + TEST_SHIFT l.sra, 0xb38f0f83, 0x00000001 + TEST_SHIFT l.sra, 0xb38f0f83, 0x00000004 + TEST_SHIFT l.sra, 0xb38f0f83, 0x00000010 + TEST_SHIFT l.sra, 0xb38f0f83, 0x0000001f + + TEST_SHIFT l.sra, 0x4c70f07c, 0x00000001 + TEST_SHIFT l.sra, 0x4c70f07c, 0x00000004 + TEST_SHIFT l.sra, 0x4c70f07c, 0x00000010 + TEST_SHIFT l.sra, 0x4c70f07c, 0x0000001f + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFT l.sra, 0xb38f0f83, 0x00000021 + TEST_SHIFT l.sra, 0xb38f0f83, 0x00002224 + TEST_SHIFT l.sra, 0xb38f0f83, 0x00f789f0 + TEST_SHIFT l.sra, 0xb38f0f83, 0xffffffff + + TEST_SHIFT l.sra, 0x4c70f07c, 0x00000021 + TEST_SHIFT l.sra, 0x4c70f07c, 0x00002224 + TEST_SHIFT l.sra, 0x4c70f07c, 0x00f789f0 + TEST_SHIFT l.sra, 0x4c70f07c, 0xffffffff + + /* Test l.srai */ + + /* Shift right by zero. */ + TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0000 + + /* Shift right by amounts in the 1-31 range. */ + TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0001 + TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0004 + TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0010 + TEST_SHIFT_I l.srai, 0xb38f0f83, 0x001f + + TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0001 + TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0004 + TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0010 + TEST_SHIFT_I l.srai, 0x4c70f07c, 0x001f + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0021 + TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0024 + TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0030 + TEST_SHIFT_I l.srai, 0xb38f0f83, 0x003f + + TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0021 + TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0024 + TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0030 + TEST_SHIFT_I l.srai, 0x4c70f07c, 0x003f + + /* Test l.srl */ + + /* Shift right by zero. */ + TEST_SHIFT l.srl, 0xb38f0f83, 0x00000000 + + /* Shift right by amounts in the 1-31 range. */ + TEST_SHIFT l.srl, 0xb38f0f83, 0x00000001 + TEST_SHIFT l.srl, 0xb38f0f83, 0x00000004 + TEST_SHIFT l.srl, 0xb38f0f83, 0x00000010 + TEST_SHIFT l.srl, 0xb38f0f83, 0x0000001f + + TEST_SHIFT l.srl, 0x4c70f07c, 0x00000001 + TEST_SHIFT l.srl, 0x4c70f07c, 0x00000004 + TEST_SHIFT l.srl, 0x4c70f07c, 0x00000010 + TEST_SHIFT l.srl, 0x4c70f07c, 0x0000001f + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFT l.srl, 0xb38f0f83, 0x00000021 + TEST_SHIFT l.srl, 0xb38f0f83, 0x00002224 + TEST_SHIFT l.srl, 0xb38f0f83, 0x00f789f0 + TEST_SHIFT l.srl, 0xb38f0f83, 0xffffffff + + TEST_SHIFT l.srl, 0x4c70f07c, 0x00000021 + TEST_SHIFT l.srl, 0x4c70f07c, 0x00002224 + TEST_SHIFT l.srl, 0x4c70f07c, 0x00f789f0 + TEST_SHIFT l.srl, 0x4c70f07c, 0xffffffff + + /* Test l.srli */ + + /* Shift right by zero. */ + TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0000 + + /* Shift right by amounts in the 1-31 range. */ + TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0001 + TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0004 + TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0010 + TEST_SHIFT_I l.srli, 0xb38f0f83, 0x001f + + TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0001 + TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0004 + TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0010 + TEST_SHIFT_I l.srli, 0x4c70f07c, 0x001f + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0021 + TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0024 + TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0030 + TEST_SHIFT_I l.srli, 0xb38f0f83, 0x003f + + TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0021 + TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0024 + TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0030 + TEST_SHIFT_I l.srli, 0x4c70f07c, 0x003f + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/spr-defs.h b/sim/testsuite/or1k/spr-defs.h new file mode 100644 index 0000000..f0ec5e7 --- /dev/null +++ b/sim/testsuite/or1k/spr-defs.h @@ -0,0 +1,120 @@ +/* Special Purpose Registers definitions + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef SPR_DEFS_H +#define SPR_DEFS_H + +#define MAX_GRPS 32 +#define MAX_SPRS_PER_GRP_BITS 11 + +/* Base addresses for the groups */ +#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_FP (11<< MAX_SPRS_PER_GRP_BITS) + +/* System control and status group */ +#define SPR_VR (SPRGROUP_SYS + 0) +#define SPR_UPR (SPRGROUP_SYS + 1) +#define SPR_CPUCFGR (SPRGROUP_SYS + 2) +#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) +#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) +#define SPR_DCCFGR (SPRGROUP_SYS + 5) +#define SPR_ICCFGR (SPRGROUP_SYS + 6) +#define SPR_DCFGR (SPRGROUP_SYS + 7) +#define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_NPC (SPRGROUP_SYS + 16) +#define SPR_SR (SPRGROUP_SYS + 17) +#define SPR_PPC (SPRGROUP_SYS + 18) +#define SPR_FPCSR (SPRGROUP_SYS + 20) +#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) +#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) +#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) +#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) +#define SPR_ESR_BASE (SPRGROUP_SYS + 64) +#define SPR_ESR_LAST (SPRGROUP_SYS + 79) +#define SPR_GPR_BASE (SPRGROUP_SYS + 1024) + +/* Data MMU group */ +#define SPR_DMMUCR (SPRGROUP_DMMU + 0) +#define SPR_DMMUPR (SPRGROUP_DMMU + 1) +#define SPR_DTLBEIR (SPRGROUP_DMMU + 2) +#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) +#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) +#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) +#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) + +/* Instruction MMU group */ +#define SPR_IMMUCR (SPRGROUP_IMMU + 0) +#define SPR_ITLBEIR (SPRGROUP_IMMU + 2) +#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) +#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) +#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) +#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) + +/* Data cache group */ +#define SPR_DCCR (SPRGROUP_DC + 0) +#define SPR_DCBPR (SPRGROUP_DC + 1) +#define SPR_DCBFR (SPRGROUP_DC + 2) +#define SPR_DCBIR (SPRGROUP_DC + 3) +#define SPR_DCBWR (SPRGROUP_DC + 4) +#define SPR_DCBLR (SPRGROUP_DC + 5) +#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) +#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) + +/* Instruction cache group */ +#define SPR_ICCR (SPRGROUP_IC + 0) +#define SPR_ICBPR (SPRGROUP_IC + 1) +#define SPR_ICBIR (SPRGROUP_IC + 2) +#define SPR_ICBLR (SPRGROUP_IC + 3) +#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) +#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) + +/* MAC group */ +#define SPR_MACLO (SPRGROUP_MAC + 1) +#define SPR_MACHI (SPRGROUP_MAC + 2) + +/* Bit definitions for the Supervision Register. */ +#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ +#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ +#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ +#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ +#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ +#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ +#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ +#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ +#define SPR_SR_CE 0x00000100 /* CID Enable */ +#define SPR_SR_F 0x00000200 /* Condition Flag */ +#define SPR_SR_CY 0x00000400 /* Carry flag */ +#define SPR_SR_OV 0x00000800 /* Overflow flag */ +#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ +#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ +#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */ +#define SPR_SR_FO 0x00008000 /* Fixed one */ +#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */ +#define SPR_SR_RES 0x0ffe0000 /* Reserved */ +#define SPR_SR_CID 0xf0000000 /* Context ID */ + +#endif /* SPR_DEFS_H */ diff --git a/sim/testsuite/or1k/sub.S b/sim/testsuite/or1k/sub.S new file mode 100644 index 0000000..3886145 --- /dev/null +++ b/sim/testsuite/or1k/sub.S @@ -0,0 +1,215 @@ +/* Tests instruction l.sub. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x00000003);\n +# output: report(0x00000002);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000001);\n +# output: report(0x00000002);\n +# output: report(0xffffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000003);\n +# output: report(0x00000002);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xfffffffd);\n +# output: report(0xfffffffe);\n +# output: report(0xffffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0xfffffffe);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x7fffffff);\n +# output: report(0x3fffffff);\n +# output: report(0x40000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x40000000);\n +# output: report(0x40000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x3fffffff);\n +# output: report(0x40000000);\n +# output: report(0xffffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x40000000);\n +# output: report(0x3fffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x80000000);\n +# output: report(0x7fffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x7fffffff);\n +# output: report(0x80000000);\n +# output: report(0xffffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x80000000);\n +# output: report(0x7fffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: report(0x3fffffff);\n +# output: report(0x40000000);\n +# output: report(0xffffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x7fffffff);\n +# output: report(0x80000000);\n +# output: report(0xffffffff);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: report(0x00000001);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + STANDARD_TEST_ENVIRONMENT + + .section .exception_vectors + + /* Range exception. */ + .org 0xb00 + + /* The handling is a bit dubious at present. We just patch the + instruction with l.nop and restart. This will go wrong in branch + delay slots. But we don't have those in this test. */ + l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE + PUSH r2 + PUSH r3 + /* Save the address of the instruction that caused the problem. */ + MOVE_FROM_SPR r2, SPR_EPCR_BASE + LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */ + l.sw 0(r2), r3 + POP r3 + POP r2 + l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE + l.rfe + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Test l.sub */ + + /* Subtract two small positive numbers. Sets the carry, but never + the overflow if the result is negative. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x00000003, \ + 0x00000002 + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x00000001, \ + 0x00000002 + + /* Check carry in is ignored. */ + TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.sub, 0x00000003, 0x00000002 + + /* Subtract two small negative numbers. Sets the carry flag if + the result is negative, but never the overflow flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0xfffffffd, \ + 0xfffffffe + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0xffffffff, \ + 0xfffffffe + + /* Subtract two quite large positive numbers. Should set neither + the overflow nor the carry flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, \ + 0x3fffffff + + /* Subtract two quite large negative numbers. Should set neither + the overflow nor the carry flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x40000000, \ + 0x40000000 + + /* Subtract two large positive numbers with a negative result. + Should set the carry, but not the overflow flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x3fffffff, \ + 0x40000000 + + /* Subtract two large negative numbers with a positive result. + Should set neither the carry nor the overflow flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x40000000, \ + 0x3fffffff + + /* Subtract a large positive from a large negative number. Should + set overflow but not the carry flag. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x80000000, \ + 0x7fffffff + + /* Subtract a large negative from a large positive number. Should + set both the overflow and carry flags. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, \ + 0x80000000 + + /* Check that range exceptions are triggered. */ + + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Check that an overflow alone causes a RANGE Exception. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x80000000, \ + 0x7fffffff + + /* Check that a carry alone does not cause a RANGE Exception. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x3fffffff, \ + 0x40000000 + + /* Check that carry and overflow together cause an exception. */ + TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, \ + 0x80000000 + + CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/or1k/xor.S b/sim/testsuite/or1k/xor.S new file mode 100644 index 0000000..2dc0ad8 --- /dev/null +++ b/sim/testsuite/or1k/xor.S @@ -0,0 +1,200 @@ +/* Tests instructions l.xor, l.xori. + + Copyright (C) 2017-2021 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +# mach: or1k +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x55555555);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0xb38f0f83);\n +# output: report(0xffffffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0xc4c70f07);\n +# output: report(0x88b7ff7b);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x38f0f83b);\n +# output: report(0x8b7ff7b8);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xffffffff);\n +# output: report(0x0000ffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0xaaaaaaaa);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x0000aaaa);\n +# output: report(0x55550000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x55555555);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x55555555);\n +# output: report(0x00005555);\n +# output: report(0x55550000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xaaaaaaaa);\n +# output: report(0x00005555);\n +# output: report(0xaaaaffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000f83);\n +# output: report(0x4c70ffff);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0x4c70f07c);\n +# output: report(0x00000f07);\n +# output: report(0x4c70ff7b);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: report(0xb38f0f83);\n +# output: report(0x0000f83b);\n +# output: report(0x4c70f7b8);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: report(0x00000000);\n +# output: \n +# output: exit(0)\n + +#include "or1k-asm-test-helpers.h" + + STANDARD_TEST_ENVIRONMENT + + .section .text +start_tests: + PUSH LINK_REGISTER_R9 + + /* Always set OVE. We should never trigger an exception, even if + this bit is set. */ + SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 + + /* Test the l.xor instruction with a range of operands. */ + + TEST_INST_I32_I32 l.xor, 0x00000000, 0x00000000 + TEST_INST_I32_I32 l.xor, 0xffffffff, 0xffffffff + TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0x00000000 + TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0xaaaaaaaa + TEST_INST_I32_I32 l.xor, 0x55555555, 0x00000000 + TEST_INST_I32_I32 l.xor, 0x55555555, 0x55555555 + TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0x55555555 + TEST_INST_I32_I32 l.xor, 0x4c70f07c, 0xb38f0f83 + TEST_INST_I32_I32 l.xor, 0x4c70f07c, 0xc4c70f07 + TEST_INST_I32_I32 l.xor, 0xb38f0f83, 0x38f0f83b + + /* Test the l.xori instruction with a range of operands. */ + + TEST_INST_I32_I16 l.xori, 0x00000000, 0x0000 + TEST_INST_I32_I16 l.xori, 0xffffffff, 0xffff + TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0x0000 + TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0xaaaa + TEST_INST_I32_I16 l.xori, 0x55555555, 0x0000 + TEST_INST_I32_I16 l.xori, 0x55555555, 0x5555 + TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0x5555 + TEST_INST_I32_I16 l.xori, 0x4c70f07c, 0x0f83 + TEST_INST_I32_I16 l.xori, 0x4c70f07c, 0x0f07 + TEST_INST_I32_I16 l.xori, 0xb38f0f83, 0xf83b + + POP LINK_REGISTER_R9 + RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/pru/ChangeLog b/sim/testsuite/pru/ChangeLog new file mode 100644 index 0000000..3d862d1 --- /dev/null +++ b/sim/testsuite/pru/ChangeLog @@ -0,0 +1,17 @@ +2020-11-12 Dimitar Dimitrov + + * lmbd.s: New test. + +2019-09-23 Dimitar Dimitrov + + * add.s: New test. + * allinsn.exp: New file. + * dmem-zero-pass.s: New test. + * dmem-zero-trap.s: New test. + * dram.s: New test. + * jmp.s: New test. + * loop-imm.s: New test. + * loop-reg.s: New test. + * mul.s: New test. + * subreg.s: New test. + * testutils.inc: New file. diff --git a/sim/testsuite/pru/add.s b/sim/testsuite/pru/add.s new file mode 100644 index 0000000..89e6f13 --- /dev/null +++ b/sim/testsuite/pru/add.s @@ -0,0 +1,40 @@ +# Check that basic add insn works. +# mach: pru + +# Copyright (C) 2016-2021 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +.include "testutils.inc" + + start + + ldi r4, 10 + add r4, r4, 23 + qbne 2f, r4, 33 + + qblt 2f, r4, 33 + + qbgt 2f, r4, 33 + + jmp 1f + + fail + +1: + pass +2: fail diff --git a/sim/testsuite/pru/allinsn.exp b/sim/testsuite/pru/allinsn.exp new file mode 100644 index 0000000..d147f73 --- /dev/null +++ b/sim/testsuite/pru/allinsn.exp @@ -0,0 +1,33 @@ +# PRU simulator testsuite. + +# Copyright (C) 2016-2021 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +if [istarget pru-*] { + # all machines + set all_machs "pru" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/pru/dmem-zero-pass.s b/sim/testsuite/pru/dmem-zero-pass.s new file mode 100644 index 0000000..7206d2f --- /dev/null +++ b/sim/testsuite/pru/dmem-zero-pass.s @@ -0,0 +1,29 @@ +# Check that DMEM zero address access works by default. +# mach: pru + +# Copyright (C) 2016-2021 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +.include "testutils.inc" + + start + + ldi r1, 0 + lbbo &r2, r1, 0, 4 + + pass diff --git a/sim/testsuite/pru/dmem-zero-trap.s b/sim/testsuite/pru/dmem-zero-trap.s new file mode 100644 index 0000000..58febb7 --- /dev/null +++ b/sim/testsuite/pru/dmem-zero-trap.s @@ -0,0 +1,32 @@ +# Check that DMEM zero address access can be trapped. +# mach: pru +# sim: --error-null-deref +# xerror: +# output: core: 4 byte read to unmapped address 0x0 at *\n + +# Copyright (C) 2016-2021 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +.include "testutils.inc" + + start + + ldi r1, 0 + lbbo &r2, r1, 0, 4 + + pass diff --git a/sim/testsuite/pru/dram.s b/sim/testsuite/pru/dram.s new file mode 100644 index 0000000..5f35633 --- /dev/null +++ b/sim/testsuite/pru/dram.s @@ -0,0 +1,72 @@ +# Check that DRAM memory access works. +# mach: pru + +# Copyright (C) 2016-2021 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +.include "testutils.inc" + + start + + fill r20, 16 + ldi r10, 0 + not r10, r10 + qbne F, r20, r10 + qbne F, r21, r10 + qbne F, r22, r10 + qbne F, r23, r10 + + zero r20, 16 + qbne F, r20, 0 + qbne F, r21, 0 + qbne F, r22, 0 + qbne F, r23, 0 + + ldi r0, testarray + lbbo &r20, r0, 0, 7 + qbne F, r20.b0, 0x01 + qbne F, r20.b1, 0x23 + qbne F, r20.b2, 0x45 + qbne F, r20.b3, 0x67 + qbne F, r21.b0, 0x89 + qbne F, r21.b1, 0xab + qbne F, r21.b2, 0xcd + qbne F, r21.b3, 0x00 ; Should not have been loaded! + qbne F, r22, 0 + qbne F, r23, 0 + + ldi r1, 0x11 + sbbo &r1, r0, 9, 1 + ldi r1, 0x11 + sbbo &r1, r0, 12, 4 + + lbbo &r20, r0, 0, 16 + qbne F, r21.b3, 0xef + qbne F, r22.b0, 0xff + qbne F, r22.b1, 0x11 + qbne F, r22.b2, 0xff + qbne F, r22.b3, 0xff + qbne F, r23, 0x11 + + pass +F: fail + + .data +testarray: + .byte 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff diff --git a/sim/testsuite/pru/jmp.s b/sim/testsuite/pru/jmp.s new file mode 100644 index 0000000..9b2ec10 --- /dev/null +++ b/sim/testsuite/pru/jmp.s @@ -0,0 +1,40 @@ +# Check that jump and branch insns work. +# mach: pru + +# Copyright (C) 2016-2021 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +.include "testutils.inc" + + start + + ldi r10, 10 + call func1 + qbne F, r10, 11 + + ldi r0, %pmem(1f) + jmp r0 + fail +1: + pass +F: fail + + +func1: + add r10, r10, 1 + ret diff --git a/sim/testsuite/pru/lmbd.s b/sim/testsuite/pru/lmbd.s new file mode 100644 index 0000000..36e3086 --- /dev/null +++ b/sim/testsuite/pru/lmbd.s @@ -0,0 +1,61 @@ +# Check that lmbd insn works. +# mach: pru + +# Copyright (C) 2020-2021 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +.include "testutils.inc" + + start + + ldi32 r14, 0xffffffff + ldi32 r15, 0x0 + ldi32 r16, 0x40000000 + ldi32 r17, 8 + + lmbd r0, r14, 0 + qbne 2f, r0, 32 + + lmbd r0, r14, 1 + qbne 2f, r0, 31 + + lmbd r0, r15, 1 + qbne 2f, r0, 32 + + lmbd r0, r15, 0 + qbne 2f, r0, 31 + + lmbd r0, r16, r15 + qbne 2f, r0, 31 + + lmbd r0, r16, 1 + qbne 2f, r0, 30 + + lmbd r0, r14.w1, 1 + qbne 2f, r0, 15 + + lmbd r0, r17.b0, 1 + qbne 2f, r0, 3 + + lmbd r0, r17.b0, r15 + qbne 2f, r0, 7 + + +1: + pass +2: fail diff --git a/sim/testsuite/pru/loop-imm.s b/sim/testsuite/pru/loop-imm.s new file mode 100644 index 0000000..4de04fa --- /dev/null +++ b/sim/testsuite/pru/loop-imm.s @@ -0,0 +1,43 @@ +# Check that loop insn works. +# mach: pru + +# Copyright (C) 2016-2021 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +.include "testutils.inc" + + start + + ldi r25, 0 + ldi r26, 0 + ldi r27, 0 + + add r27, r27, 1 + loop 1f, 10 + add r25, r25, 1 + add r26, r26, 2 +1: + add r27, r27, 1 + + qbne F, r25, 10 + qbne F, r26, 20 + qbne F, r27, 2 + + pass + +F: fail diff --git a/sim/testsuite/pru/loop-reg.s b/sim/testsuite/pru/loop-reg.s new file mode 100644 index 0000000..3fe6654 --- /dev/null +++ b/sim/testsuite/pru/loop-reg.s @@ -0,0 +1,44 @@ +# Check that loop insn works. +# mach: pru + +# Copyright (C) 2016-2021 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +.include "testutils.inc" + + start + + ldi r25, 0 + ldi r26, 0 + ldi r27, 0 + ldi r28, 10 + + add r27, r27, 1 + loop 1f, r28 + add r25, r25, 1 + add r26, r26, 2 +1: + add r27, r27, 1 + + qbne F, r25, 10 + qbne F, r26, 20 + qbne F, r27, 2 + + pass + +F: fail diff --git a/sim/testsuite/pru/mul.s b/sim/testsuite/pru/mul.s new file mode 100644 index 0000000..7aacc41 --- /dev/null +++ b/sim/testsuite/pru/mul.s @@ -0,0 +1,89 @@ +# Check that multiplication works. +# mach: pru + +# Copyright (C) 2016-2021 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +.include "testutils.inc" + + start + + # MUL: Test regular case + ldi r28, 1001 + ldi r29, 4567 + nop + xin 0, r26, 4 + qbne32 2f, r26, 1001 * 4567 + + # MUL: Test the pipeline emulation + ldi r28, 1002 + ldi r29, 1003 + ldi r29, 4004 + xin 0, r26, 4 + qbne32 2f, r26, 1002 * 1003 + xin 0, r26, 4 + qbne32 2f, r26, 1002 * 4004 + + # MUL: Test 64-bit result + ldi32 r28, 0x12345678 + ldi32 r29, 0xaabbccdd + nop + xin 0, r26, 8 + qbne32 2f, r26, 0x45BE4598 + qbne32 2f, r27, 0xC241C38 + + # MAC: Test regular case + ldi r25, 1 + xout 0, r25, 1 + ldi r25, 3 + xout 0, r25, 1 + + ldi r25, 1 + ldi r28, 1001 + ldi r29, 2002 + xout 0, r25, 1 + ldi r28, 3003 + ldi r29, 4004 + xout 0, r25, 1 + + xin 0, r26, 4 + qbne32 2f, r26, (1001 * 2002) + (3003 * 4004) + + # MAC: Test 64-bit result + ldi r25, 3 + xout 0, r25, 1 + + ldi r25, 1 + ldi32 r28, 0x10203040 + ldi32 r29, 0x50607080 + xout 0, r25, 1 + ldi32 r28, 0xa0b0c0d0 + ldi32 r29, 0x11223344 + xout 0, r25, 1 + + xin 0, r26, 8 + qbne32 2f, r26, 0x8E30C740 + qbne32 2f, r27, 0xFD156B1 + + jmp 1f + + fail + +1: + pass +2: fail diff --git a/sim/testsuite/pru/subreg.s b/sim/testsuite/pru/subreg.s new file mode 100644 index 0000000..372f700 --- /dev/null +++ b/sim/testsuite/pru/subreg.s @@ -0,0 +1,40 @@ +# Check that subregister addressing works. +# mach: pru + +# Copyright (C) 2016-2021 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +.include "testutils.inc" + + start + + ldi r0, 0x01ff + add r0, r0.b0, r0.b1 + qbne F, r0.b0, 0x00 + qbne F, r0.b1, 0x01 + qbne F, r0.w2, 0x00 + + ldi r0, 0x01ff + add r0.b0, r0.b0, r0.b1 + adc r0, r0.b1, r0.b3 + qbne F, r0.b0, 0x02 + qbne F, r0.b1, 0x00 + qbne F, r0.w2, 0x00 + + pass +F: fail diff --git a/sim/testsuite/pru/testutils.inc b/sim/testsuite/pru/testutils.inc new file mode 100644 index 0000000..dfe63f3 --- /dev/null +++ b/sim/testsuite/pru/testutils.inc @@ -0,0 +1,100 @@ +# Copyright (C) 2016-2021 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# MACRO: start +# All assembler tests should start with a call to "main_test" + .macro start + .text + + .global _start +_start: + + # Skip over these inlined funcs. + jmp __main_test; + + .global __pass + .type __pass, function +__pass: + # Note - DRAM LMA and VMA are equal for PRU, so + # we can afford to pass DRAM pointer directly. + write 1, _passmsg, 5 + exit 0 + + .global __fail + .type __fail, function +__fail: + write 1, _failmsg, 5 + exit 1 + + .data +_passmsg: + .ascii "pass\n" + +_failmsg: + .ascii "fail\n" + + .text + .global __main_test + .type __main_test, function +__main_test: + .endm + +# MACRO: system_call +# Make a libgloss system call + .macro system_call nr:req, arg1=0, arg2=0, arg3=0 + ldi r1, \nr + ldi r14, \arg1 + ldi r15, \arg2 + ldi r16, \arg3 + halt + .endm + +# MACRO: exit +# Quit the current test + .macro exit rc:req + system_call 1, \rc + .endm + +# MACRO: pass +# Write 'pass' to stdout via syscalls and quit; +# meant for non-OS operating environments + .macro pass + jmp __pass; + .endm + +# MACRO: fail +# Write 'fail' to stdout via syscalls and quit; +# meant for non-OS operating environments + .macro fail + jmp __fail; + .endm + +# MACRO: write +# Just like the write() C function; uses system calls + .macro write fd:req, str:req, len:req + system_call 5, \fd, \str, \len + .endm + +# MACRO: qbne32 +# Like qbne instruction, but check a 32-bit constant value. + .macro qbne32 label:req, op0:req, C0:req + qbne \label, \op0\().b0, ((\C0) >> 0) & 0xff + qbne \label, \op0\().b1, ((\C0) >> 8) & 0xff + qbne \label, \op0\().b2, ((\C0) >> 16) & 0xff + qbne \label, \op0\().b3, ((\C0) >> 24) & 0xff + .endm diff --git a/sim/testsuite/sh/ChangeLog b/sim/testsuite/sh/ChangeLog new file mode 100644 index 0000000..e3852f9 --- /dev/null +++ b/sim/testsuite/sh/ChangeLog @@ -0,0 +1,77 @@ +2004-09-13 DJ Delorie + + * sim/sh/allinsn.exp: Set global_as_options and + global_ld_options appropriately for little endian builds. + * sim/sh/movua.s: Support little endian. + +2004-09-08 Michael Snyder + + Commited by Corinna Vinschen + * allinsn.exp: Add new tests. + * bandor.s: New file. + * bandornot.s: New file. + * bclr.s: New file. + * bld.s: New file. + * bldnot.s: New file. + * bset.s: New file. + * bst.s: New file. + * bxor.s: New file. + * clip.s: New file. + * div.s: New file. + * fail.s: New file, make sure fail works. + * fsca.s: New file. + * fsrra.s: New file. + * mov.s: New file. + * mulr.s: New file. + * pass.s: New file, make sure pass works. + * pushpop.s: New file. + * resbank.s: New file. + * testutils.inc (bf8k, bt8k, assertmem): New macros. + +2004-02-12 Michael Snyder + + * and.s, movi.s, sett.s: New files. + * allinsn.exp: Add new tests. + * testutils.inc (set_sr_bit): Fix macro labels. + +2004-01-07 Michael Snyder + + * dmxy.s, fipr.s, fpchg.s, ldrc.s, loop.s, movli.s, movua.s, + movxy.s, pabs.s, pclr.s, prnd.s, psub.s, pswap.s: New files. + * allinsn.exp: Add new tests. + * testutils.inc (set_sr_bit): Add argument. + (set_greg): Add .align directives. + +2003-08-11 Michael Snyder + + * macl.s: New file. + * macw.s: New file. + * allinsn.exp: Add new tests for mac.w and mac.l. + +2003-07-25 Michael Snyder + + * pshai.s, pshar.s, pshli.s, pshlr.s: New files. + * allinsn.exp: Add psha, pshl tests. + * pdec.s, pinc.s, padd.s, paddc.s: New files. + * allinsn.exp: Add pdec, pinc, padd, paddc tests. + * pand.s, pdmsb.s: New files. + * allinsn.exp: Add pand, pdmsb tests. + +2003-07-23 Michael Snyder + + * pmuls.s: New file. + +2003-07-08 Michael Snyder + + * allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s, + fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s, + float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s, + fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s, + shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files. + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/sim/testsuite/sh/add.s b/sim/testsuite/sh/add.s new file mode 100644 index 0000000..9519251 --- /dev/null +++ b/sim/testsuite/sh/add.s @@ -0,0 +1,86 @@ +# sh testcase for add +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 1 +_y: .long 1 + + start + +add_reg_reg_direct: + set_grs_a5a5 + mov.l i, r1 + mov.l j, r2 + add r1, r2 + test_gr0_a5a5 + assertreg 2 r1 + assertreg 4 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +add_reg_reg_indirect: + set_grs_a5a5 + mov.l x, r1 + mov.l y, r2 + mov.l @r1, r1 + mov.l @r2, r2 + add r1, r2 + test_gr0_a5a5 + assertreg 1 r1 + assertreg 2 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +add_imm_reg: + set_grs_a5a5 + add #0x16, r1 + test_gr0_a5a5 + assertreg 0xa5a5a5bb r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y +i: .long 2 +j: .long 2 + diff --git a/sim/testsuite/sh/allinsn.exp b/sim/testsuite/sh/allinsn.exp new file mode 100644 index 0000000..40d1392 --- /dev/null +++ b/sim/testsuite/sh/allinsn.exp @@ -0,0 +1,89 @@ +# sh tests + +set all "sh shdsp" + +set global_as_options "" +set global_ld_options "" + +foreach opt $board_variant_list { + switch "x$opt" { + x-ml { set global_as_options "-little --defsym LITTLE=1" + set global_ld_options "-EL" } + } +} + +if [istarget sh-*elf] { + run_sim_test add.s $all + run_sim_test and.s $all + run_sim_test bandor.s sh + run_sim_test bandornot.s sh + run_sim_test bclr.s sh + run_sim_test bld.s sh + run_sim_test bldnot.s sh + run_sim_test bset.s sh + run_sim_test bst.s sh + run_sim_test bxor.s sh + run_sim_test clip.s sh + run_sim_test div.s sh + run_sim_test dmxy.s shdsp + run_sim_test fabs.s sh + run_sim_test fadd.s sh + run_sim_test fcmpeq.s sh + run_sim_test fcmpgt.s sh + run_sim_test fcnvds.s sh + run_sim_test fcnvsd.s sh + run_sim_test fdiv.s sh + run_sim_test fipr.s sh + run_sim_test fldi0.s sh + run_sim_test fldi1.s sh + run_sim_test flds.s sh + run_sim_test float.s sh + run_sim_test fmac.s sh + run_sim_test fmov.s sh + run_sim_test fmul.s sh + run_sim_test fneg.s sh + run_sim_test fpchg.s sh + run_sim_test frchg.s sh + run_sim_test fschg.s sh + run_sim_test fsqrt.s sh + run_sim_test fsub.s sh + run_sim_test ftrc.s sh + run_sim_test ldrc.s shdsp + run_sim_test loop.s shdsp + run_sim_test macl.s sh + run_sim_test macw.s sh + run_sim_test mov.s $all + run_sim_test movi.s $all + run_sim_test movli.s $all + run_sim_test movua.s $all + run_sim_test movxy.s shdsp + run_sim_test mulr.s sh + run_sim_test pabs.s shdsp + run_sim_test paddc.s shdsp + run_sim_test padd.s shdsp + run_sim_test pand.s shdsp + run_sim_test pclr.s shdsp + run_sim_test pdec.s shdsp + run_sim_test pdmsb.s shdsp + run_sim_test pinc.s shdsp + run_sim_test pmuls.s shdsp + run_sim_test prnd.s shdsp + run_sim_test pshai.s shdsp + run_sim_test pshar.s shdsp + run_sim_test pshli.s shdsp + run_sim_test pshlr.s shdsp + run_sim_test psub.s shdsp + run_sim_test pswap.s shdsp + run_sim_test pushpop.s sh + run_sim_test resbank.s sh + run_sim_test sett.s sh + run_sim_test shll.s $all + run_sim_test shll2.s $all + run_sim_test shll8.s $all + run_sim_test shll16.s $all + run_sim_test shlr.s $all + run_sim_test shlr2.s $all + run_sim_test shlr8.s $all + run_sim_test shlr16.s $all + run_sim_test swap.s $all +} diff --git a/sim/testsuite/sh/and.s b/sim/testsuite/sh/and.s new file mode 100644 index 0000000..0093447 --- /dev/null +++ b/sim/testsuite/sh/and.s @@ -0,0 +1,89 @@ +# sh testcase for and +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 +_y: .long 0x55555555 + + start + +and_reg_reg_direct: + set_grs_a5a5 + mov.l i, r1 + mov.l j, r2 + and r1, r2 + test_gr0_a5a5 + assertreg 0xa5a5a5a5 r1 + assertreg 0xa0a0a0a0 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + bra and_imm_reg + nop + + .align 2 +i: .long 0xa5a5a5a5 +j: .long 0xaaaaaaaa + +and_imm_reg: + set_grs_a5a5 + and #0xff, r0 + assertreg 0xa5, r0 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +and_b_imm_ind: + set_grs_a5a5 + mov.l x, r0 + and.b #0x55, @(r0, GBR) + mov.l @r0, r0 + + assertreg 0xa5a5a505, r0 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y + diff --git a/sim/testsuite/sh/bandor.s b/sim/testsuite/sh/bandor.s new file mode 100644 index 0000000..9ada485 --- /dev/null +++ b/sim/testsuite/sh/bandor.s @@ -0,0 +1,120 @@ +# sh testcase for band, bor +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 + + start + +bandor_b_imm_disp12_reg: + set_grs_a5a5 + # Make sure T is true to start. + sett + + mov.l x, r1 + + band.b #0, @(3, r1) + bf8k mfail + bor.b #1, @(3, r1) + bf8k mfail + band.b #2, @(3, r1) + bf8k mfail + bor.b #3, @(3, r1) + bf8k mfail + + bor.b #4, @(3, r1) + bf8k mfail + band.b #5, @(3, r1) + bf8k mfail + bor.b #6, @(3, r1) + bf8k mfail + band.b #7, @(3, r1) + bf8k mfail + + band.b #0, @(2, r1) + bf8k mfail + bor.b #1, @(2, r1) + bf8k mfail + band.b #2, @(2, r1) + bf8k mfail + bor.b #3, @(2, r1) + bf8k mfail + + bra .L2 + nop + + .align 2 +x: .long _x + +.L2: + bor.b #4, @(2, r1) + bf8k mfail + band.b #5, @(2, r1) + bf8k mfail + bor.b #6, @(2, r1) + bf8k mfail + band.b #7, @(2, r1) + bf8k mfail + + band.b #0, @(1, r1) + bf8k mfail + bor.b #1, @(1, r1) + bf8k mfail + band.b #2, @(1, r1) + bf8k mfail + bor.b #3, @(1, r1) + bf8k mfail + + bor.b #4, @(1, r1) + bf8k mfail + band.b #5, @(1, r1) + bf8k mfail + bor.b #6, @(1, r1) + bf8k mfail + band.b #7, @(1, r1) + bf8k mfail + + band.b #0, @(0, r1) + bf8k mfail + bor.b #1, @(0, r1) + bf8k mfail + band.b #2, @(0, r1) + bf8k mfail + bor.b #3, @(0, r1) + bf8k mfail + + bor.b #4, @(0, r1) + bf8k mfail + band.b #5, @(0, r1) + bf8k mfail + bor.b #6, @(0, r1) + bf8k mfail + band.b #7, @(0, r1) + bf8k mfail + + assertreg _x, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/bandornot.s b/sim/testsuite/sh/bandornot.s new file mode 100644 index 0000000..1787d0d --- /dev/null +++ b/sim/testsuite/sh/bandornot.s @@ -0,0 +1,120 @@ +# sh testcase for bandnot, bornot +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 + + start + +bandor_b_imm_disp12_reg: + set_grs_a5a5 + # Make sure T is true to start. + sett + + mov.l x, r1 + + bandnot.b #0, @(3, r1) + bt8k mfail + bornot.b #1, @(3, r1) + bf8k mfail + bandnot.b #2, @(3, r1) + bt8k mfail + bornot.b #3, @(3, r1) + bf8k mfail + + bornot.b #4, @(3, r1) + bf8k mfail + bandnot.b #5, @(3, r1) + bt8k mfail + bornot.b #6, @(3, r1) + bf8k mfail + bandnot.b #7, @(3, r1) + bt8k mfail + + bandnot.b #0, @(2, r1) + bt8k mfail + bornot.b #1, @(2, r1) + bf8k mfail + bandnot.b #2, @(2, r1) + bt8k mfail + bornot.b #3, @(2, r1) + bf8k mfail + + bra .L2 + nop + + .align 2 +x: .long _x + +.L2: + bornot.b #4, @(2, r1) + bf8k mfail + bandnot.b #5, @(2, r1) + bt8k mfail + bornot.b #6, @(2, r1) + bf8k mfail + bandnot.b #7, @(2, r1) + bt8k mfail + + bandnot.b #0, @(1, r1) + bt8k mfail + bornot.b #1, @(1, r1) + bf8k mfail + bandnot.b #2, @(1, r1) + bt8k mfail + bornot.b #3, @(1, r1) + bf8k mfail + + bornot.b #4, @(1, r1) + bf8k mfail + bandnot.b #5, @(1, r1) + bt8k mfail + bornot.b #6, @(1, r1) + bf8k mfail + bandnot.b #7, @(1, r1) + bt8k mfail + + bandnot.b #0, @(0, r1) + bt8k mfail + bornot.b #1, @(0, r1) + bf8k mfail + bandnot.b #2, @(0, r1) + bt8k mfail + bornot.b #3, @(0, r1) + bf8k mfail + + bornot.b #4, @(0, r1) + bf8k mfail + bandnot.b #5, @(0, r1) + bt8k mfail + bornot.b #6, @(0, r1) + bf8k mfail + bandnot.b #7, @(0, r1) + bt8k mfail + + assertreg _x, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/bclr.s b/sim/testsuite/sh/bclr.s new file mode 100644 index 0000000..cbe1c7e --- /dev/null +++ b/sim/testsuite/sh/bclr.s @@ -0,0 +1,139 @@ +# sh testcase for bclr +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xffffffff +_y: .long 0x55555555 + + start + +bclr_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bclr.b #0, @(3, r1) + assertmem _x, 0xfffffffe + bclr.b #1, @(3, r1) + assertmem _x, 0xfffffffc + bclr.b #2, @(3, r1) + assertmem _x, 0xfffffff8 + bclr.b #3, @(3, r1) + assertmem _x, 0xfffffff0 + + bclr.b #4, @(3, r1) + assertmem _x, 0xffffffe0 + bclr.b #5, @(3, r1) + assertmem _x, 0xffffffc0 + bclr.b #6, @(3, r1) + assertmem _x, 0xffffff80 + bclr.b #7, @(3, r1) + assertmem _x, 0xffffff00 + + bclr.b #0, @(2, r1) + assertmem _x, 0xfffffe00 + bclr.b #1, @(2, r1) + assertmem _x, 0xfffffc00 + bclr.b #2, @(2, r1) + assertmem _x, 0xfffff800 + bclr.b #3, @(2, r1) + assertmem _x, 0xfffff000 + + bra .L2 + nop + + .align 2 +x: .long _x +y: .long _y + +.L2: + bclr.b #4, @(2, r1) + assertmem _x, 0xffffe000 + bclr.b #5, @(2, r1) + assertmem _x, 0xffffc000 + bclr.b #6, @(2, r1) + assertmem _x, 0xffff8000 + bclr.b #7, @(2, r1) + assertmem _x, 0xffff0000 + + bclr.b #0, @(1, r1) + assertmem _x, 0xfffe0000 + bclr.b #1, @(1, r1) + assertmem _x, 0xfffc0000 + bclr.b #2, @(1, r1) + assertmem _x, 0xfff80000 + bclr.b #3, @(1, r1) + assertmem _x, 0xfff00000 + + bclr.b #4, @(1, r1) + assertmem _x, 0xffe00000 + bclr.b #5, @(1, r1) + assertmem _x, 0xffc00000 + bclr.b #6, @(1, r1) + assertmem _x, 0xff800000 + bclr.b #7, @(1, r1) + assertmem _x, 0xff000000 + + bclr.b #0, @(0, r1) + assertmem _x, 0xfe000000 + bclr.b #1, @(0, r1) + assertmem _x, 0xfc000000 + bclr.b #2, @(0, r1) + assertmem _x, 0xf8000000 + bclr.b #3, @(0, r1) + assertmem _x, 0xf0000000 + + bclr.b #4, @(0, r1) + assertmem _x, 0xe0000000 + bclr.b #5, @(0, r1) + assertmem _x, 0xc0000000 + bclr.b #6, @(0, r1) + assertmem _x, 0x80000000 + bclr.b #7, @(0, r1) + assertmem _x, 0x00000000 + + assertreg _x, r1 + +bclr_imm_reg: + set_greg 0xff, r1 + bclr #0, r1 + assertreg 0xfe, r1 + bclr #1, r1 + assertreg 0xfc, r1 + bclr #2, r1 + assertreg 0xf8, r1 + bclr #3, r1 + assertreg 0xf0, r1 + + bclr #4, r1 + assertreg 0xe0, r1 + bclr #5, r1 + assertreg 0xc0, r1 + bclr #6, r1 + assertreg 0x80, r1 + bclr #7, r1 + assertreg 0x00, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/bld.s b/sim/testsuite/sh/bld.s new file mode 100644 index 0000000..172718d --- /dev/null +++ b/sim/testsuite/sh/bld.s @@ -0,0 +1,121 @@ +# sh testcase for bld +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 +_y: .long 0x55555555 + + start + +bld_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bld.b #0, @(0, r1) + bf8k mfail + bld.b #1, @(0, r1) + bt8k mfail + bld.b #2, @(0, r1) + bf8k mfail + bld.b #3, @(0, r1) + bt8k mfail + + bld.b #4, @(0, r1) + bt8k mfail + bld.b #5, @(0, r1) + bf8k mfail + bld.b #6, @(0, r1) + bt8k mfail + bld.b #7, @(0, r1) + bf8k mfail + + bld.b #0, @(1, r1) + bf8k mfail + bld.b #1, @(1, r1) + bt8k mfail + bld.b #2, @(1, r1) + bf8k mfail + bld.b #3, @(1, r1) + bt8k mfail + + bld.b #4, @(1, r1) + bt8k mfail + bld.b #5, @(1, r1) + bf8k mfail + bld.b #6, @(1, r1) + bt8k mfail + bld.b #7, @(1, r1) + bf8k mfail + + bld.b #0, @(2, r1) + bf8k mfail + bld.b #1, @(2, r1) + bt8k mfail + bld.b #2, @(2, r1) + bf8k mfail + bld.b #3, @(2, r1) + bt8k mfail + + bld.b #4, @(2, r1) + bt8k mfail + bld.b #5, @(2, r1) + bf8k mfail + bld.b #6, @(2, r1) + bt8k mfail + bld.b #7, @(2, r1) + bf8k mfail + + bld.b #0, @(3, r1) + bf8k mfail + bld.b #1, @(3, r1) + bt8k mfail + bld.b #2, @(3, r1) + bf8k mfail + bld.b #3, @(3, r1) + bt8k mfail + + bld.b #4, @(3, r1) + bt8k mfail + bld.b #5, @(3, r1) + bf8k mfail + bld.b #6, @(3, r1) + bt8k mfail + bld.b #7, @(3, r1) + bf8k mfail + + assertreg _x, r1 + +bld_imm_reg: + set_greg 0xa5a5a5a5, r1 + bld #0, r1 + bf8k mfail + bld #1, r1 + bt8k mfail + bld #2, r1 + bf8k mfail + bld #3, r1 + bt8k mfail + + bld #4, r1 + bt8k mfail + bld #5, r1 + bf8k mfail + bld #6, r1 + bt8k mfail + bld #7, r1 + bf8k mfail + + test_grs_a5a5 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y + diff --git a/sim/testsuite/sh/bldnot.s b/sim/testsuite/sh/bldnot.s new file mode 100644 index 0000000..eda87de --- /dev/null +++ b/sim/testsuite/sh/bldnot.s @@ -0,0 +1,102 @@ +# sh testcase for bldnot +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 +_y: .long 0x55555555 + + start + +bldnot_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bldnot.b #0, @(0, r1) + bt8k mfail + bldnot.b #1, @(0, r1) + bf8k mfail + bldnot.b #2, @(0, r1) + bt8k mfail + bldnot.b #3, @(0, r1) + bf8k mfail + + bldnot.b #4, @(0, r1) + bf8k mfail + bldnot.b #5, @(0, r1) + bt8k mfail + bldnot.b #6, @(0, r1) + bf8k mfail + bldnot.b #7, @(0, r1) + bt8k mfail + + bldnot.b #0, @(1, r1) + bt8k mfail + bldnot.b #1, @(1, r1) + bf8k mfail + bldnot.b #2, @(1, r1) + bt8k mfail + bldnot.b #3, @(1, r1) + bf8k mfail + + bldnot.b #4, @(1, r1) + bf8k mfail + bldnot.b #5, @(1, r1) + bt8k mfail + bldnot.b #6, @(1, r1) + bf8k mfail + bldnot.b #7, @(1, r1) + bt8k mfail + + bldnot.b #0, @(2, r1) + bt8k mfail + bldnot.b #1, @(2, r1) + bf8k mfail + bldnot.b #2, @(2, r1) + bt8k mfail + bldnot.b #3, @(2, r1) + bf8k mfail + + bldnot.b #4, @(2, r1) + bf8k mfail + bldnot.b #5, @(2, r1) + bt8k mfail + bldnot.b #6, @(2, r1) + bf8k mfail + bldnot.b #7, @(2, r1) + bt8k mfail + + bldnot.b #0, @(3, r1) + bt8k mfail + bldnot.b #1, @(3, r1) + bf8k mfail + bldnot.b #2, @(3, r1) + bt8k mfail + bldnot.b #3, @(3, r1) + bf8k mfail + + bldnot.b #4, @(3, r1) + bf8k mfail + bldnot.b #5, @(3, r1) + bt8k mfail + bldnot.b #6, @(3, r1) + bf8k mfail + bldnot.b #7, @(3, r1) + bt8k mfail + + assertreg _x, r1 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y + diff --git a/sim/testsuite/sh/bset.s b/sim/testsuite/sh/bset.s new file mode 100644 index 0000000..13ae246 --- /dev/null +++ b/sim/testsuite/sh/bset.s @@ -0,0 +1,139 @@ +# sh testcase for bset +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0 +_y: .long 0x55555555 + + start + +bset_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bset.b #0, @(3, r1) + assertmem _x, 0x1 + bset.b #1, @(3, r1) + assertmem _x, 0x3 + bset.b #2, @(3, r1) + assertmem _x, 0x7 + bset.b #3, @(3, r1) + assertmem _x, 0xf + + bset.b #4, @(3, r1) + assertmem _x, 0x1f + bset.b #5, @(3, r1) + assertmem _x, 0x3f + bset.b #6, @(3, r1) + assertmem _x, 0x7f + bset.b #7, @(3, r1) + assertmem _x, 0xff + + bset.b #0, @(2, r1) + assertmem _x, 0x1ff + bset.b #1, @(2, r1) + assertmem _x, 0x3ff + bset.b #2, @(2, r1) + assertmem _x, 0x7ff + bset.b #3, @(2, r1) + assertmem _x, 0xfff + + bra .L2 + nop + + .align 2 +x: .long _x +y: .long _y + +.L2: + bset.b #4, @(2, r1) + assertmem _x, 0x1fff + bset.b #5, @(2, r1) + assertmem _x, 0x3fff + bset.b #6, @(2, r1) + assertmem _x, 0x7fff + bset.b #7, @(2, r1) + assertmem _x, 0xffff + + bset.b #0, @(1, r1) + assertmem _x, 0x1ffff + bset.b #1, @(1, r1) + assertmem _x, 0x3ffff + bset.b #2, @(1, r1) + assertmem _x, 0x7ffff + bset.b #3, @(1, r1) + assertmem _x, 0xfffff + + bset.b #4, @(1, r1) + assertmem _x, 0x1fffff + bset.b #5, @(1, r1) + assertmem _x, 0x3fffff + bset.b #6, @(1, r1) + assertmem _x, 0x7fffff + bset.b #7, @(1, r1) + assertmem _x, 0xffffff + + bset.b #0, @(0, r1) + assertmem _x, 0x1ffffff + bset.b #1, @(0, r1) + assertmem _x, 0x3ffffff + bset.b #2, @(0, r1) + assertmem _x, 0x7ffffff + bset.b #3, @(0, r1) + assertmem _x, 0xfffffff + + bset.b #4, @(0, r1) + assertmem _x, 0x1fffffff + bset.b #5, @(0, r1) + assertmem _x, 0x3fffffff + bset.b #6, @(0, r1) + assertmem _x, 0x7fffffff + bset.b #7, @(0, r1) + assertmem _x, 0xffffffff + + assertreg _x, r1 + +bset_imm_reg: + set_greg 0, r1 + bset #0, r1 + assertreg 0x1, r1 + bset #1, r1 + assertreg 0x3, r1 + bset #2, r1 + assertreg 0x7, r1 + bset #3, r1 + assertreg 0xf, r1 + + bset #4, r1 + assertreg 0x1f, r1 + bset #5, r1 + assertreg 0x3f, r1 + bset #6, r1 + assertreg 0x7f, r1 + bset #7, r1 + assertreg 0xff, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/bst.s b/sim/testsuite/sh/bst.s new file mode 100644 index 0000000..e8b6d65 --- /dev/null +++ b/sim/testsuite/sh/bst.s @@ -0,0 +1,142 @@ +# sh testcase for bst +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0 +_y: .long 0x55555555 + + start + +bst_b_imm_disp12_reg: + set_grs_a5a5 + # Make sure T is true to start. + sett + + mov.l x, r1 + + bst.b #0, @(3, r1) + assertmem _x, 0x1 + bst.b #1, @(3, r1) + assertmem _x, 0x3 + bst.b #2, @(3, r1) + assertmem _x, 0x7 + bst.b #3, @(3, r1) + assertmem _x, 0xf + + bst.b #4, @(3, r1) + assertmem _x, 0x1f + bst.b #5, @(3, r1) + assertmem _x, 0x3f + bst.b #6, @(3, r1) + assertmem _x, 0x7f + bst.b #7, @(3, r1) + assertmem _x, 0xff + + bst.b #0, @(2, r1) + assertmem _x, 0x1ff + bst.b #1, @(2, r1) + assertmem _x, 0x3ff + bst.b #2, @(2, r1) + assertmem _x, 0x7ff + bst.b #3, @(2, r1) + assertmem _x, 0xfff + + bra .L2 + nop + + .align 2 +x: .long _x +y: .long _y + +.L2: + bst.b #4, @(2, r1) + assertmem _x, 0x1fff + bst.b #5, @(2, r1) + assertmem _x, 0x3fff + bst.b #6, @(2, r1) + assertmem _x, 0x7fff + bst.b #7, @(2, r1) + assertmem _x, 0xffff + + bst.b #0, @(1, r1) + assertmem _x, 0x1ffff + bst.b #1, @(1, r1) + assertmem _x, 0x3ffff + bst.b #2, @(1, r1) + assertmem _x, 0x7ffff + bst.b #3, @(1, r1) + assertmem _x, 0xfffff + + bst.b #4, @(1, r1) + assertmem _x, 0x1fffff + bst.b #5, @(1, r1) + assertmem _x, 0x3fffff + bst.b #6, @(1, r1) + assertmem _x, 0x7fffff + bst.b #7, @(1, r1) + assertmem _x, 0xffffff + + bst.b #0, @(0, r1) + assertmem _x, 0x1ffffff + bst.b #1, @(0, r1) + assertmem _x, 0x3ffffff + bst.b #2, @(0, r1) + assertmem _x, 0x7ffffff + bst.b #3, @(0, r1) + assertmem _x, 0xfffffff + + bst.b #4, @(0, r1) + assertmem _x, 0x1fffffff + bst.b #5, @(0, r1) + assertmem _x, 0x3fffffff + bst.b #6, @(0, r1) + assertmem _x, 0x7fffffff + bst.b #7, @(0, r1) + assertmem _x, 0xffffffff + + assertreg _x, r1 + +bst_imm_reg: + set_greg 0, r1 + bst #0, r1 + assertreg 0x1, r1 + bst #1, r1 + assertreg 0x3, r1 + bst #2, r1 + assertreg 0x7, r1 + bst #3, r1 + assertreg 0xf, r1 + + bst #4, r1 + assertreg 0x1f, r1 + bst #5, r1 + assertreg 0x3f, r1 + bst #6, r1 + assertreg 0x7f, r1 + bst #7, r1 + assertreg 0xff, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/bxor.s b/sim/testsuite/sh/bxor.s new file mode 100644 index 0000000..abedd38 --- /dev/null +++ b/sim/testsuite/sh/bxor.s @@ -0,0 +1,120 @@ +# sh testcase for bxor +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 + + start + +bxor_b_imm_disp12_reg: + set_grs_a5a5 + # Make sure T is true to start. + sett + + mov.l x, r1 + + bxor.b #0, @(3, r1) + bt8k mfail + bxor.b #1, @(3, r1) + bt8k mfail + bxor.b #2, @(3, r1) + bf8k mfail + bxor.b #3, @(3, r1) + bf8k mfail + + bxor.b #4, @(3, r1) + bf8k mfail + bxor.b #5, @(3, r1) + bt8k mfail + bxor.b #6, @(3, r1) + bt8k mfail + bxor.b #7, @(3, r1) + bf8k mfail + + bxor.b #0, @(2, r1) + bt8k mfail + bxor.b #1, @(2, r1) + bt8k mfail + bxor.b #2, @(2, r1) + bf8k mfail + bxor.b #3, @(2, r1) + bf8k mfail + + bra .L2 + nop + + .align 2 +x: .long _x + +.L2: + bxor.b #4, @(2, r1) + bf8k mfail + bxor.b #5, @(2, r1) + bt8k mfail + bxor.b #6, @(2, r1) + bt8k mfail + bxor.b #7, @(2, r1) + bf8k mfail + + bxor.b #0, @(1, r1) + bt8k mfail + bxor.b #1, @(1, r1) + bt8k mfail + bxor.b #2, @(1, r1) + bf8k mfail + bxor.b #3, @(1, r1) + bf8k mfail + + bxor.b #4, @(1, r1) + bf8k mfail + bxor.b #5, @(1, r1) + bt8k mfail + bxor.b #6, @(1, r1) + bt8k mfail + bxor.b #7, @(1, r1) + bf8k mfail + + bxor.b #0, @(0, r1) + bt8k mfail + bxor.b #1, @(0, r1) + bt8k mfail + bxor.b #2, @(0, r1) + bf8k mfail + bxor.b #3, @(0, r1) + bf8k mfail + + bxor.b #4, @(0, r1) + bf8k mfail + bxor.b #5, @(0, r1) + bt8k mfail + bxor.b #6, @(0, r1) + bt8k mfail + bxor.b #7, @(0, r1) + bf8k mfail + + assertreg _x, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/clip.s b/sim/testsuite/sh/clip.s new file mode 100644 index 0000000..12770c381 --- /dev/null +++ b/sim/testsuite/sh/clip.s @@ -0,0 +1,89 @@ +# sh testcase for clips, clipu +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +clips_b: + set_grs_a5a5 + clips.b r1 + test_gr0_a5a5 + assertreg 0xffffff80 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +clipu_b: + set_grs_a5a5 + clipu.b r1 + test_gr0_a5a5 + assertreg 0xff r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +clips_w: + set_grs_a5a5 + clips.w r1 + test_gr0_a5a5 + assertreg 0xffff8000 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +clipu_w: + set_grs_a5a5 + clipu.w r1 + test_gr0_a5a5 + assertreg 0xffff r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + diff --git a/sim/testsuite/sh/div.s b/sim/testsuite/sh/div.s new file mode 100644 index 0000000..8293c21 --- /dev/null +++ b/sim/testsuite/sh/div.s @@ -0,0 +1,199 @@ +# sh testcase for divs and divu +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +divs_1: ! divide by one + set_grs_a5a5 + mov #1, r0 + divs r0, r1 + assertreg0 1 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divs_2: ! divide by two + set_grs_a5a5 + mov #2, r0 + divs r0, r1 + assertreg0 2 + assertreg 0xd2d2d2d3, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divs_3: ! divide by three + set_grs_a5a5 + mov #3, r0 + divs r0, r1 + assertreg0 3 + assertreg 0xe1e1e1e2, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divs_0: ! divide by zero + set_grs_a5a5 + mov #0, r0 + divs r0, r1 + assertreg0 0 + assertreg 0x7fffffff, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divs_o: ! divide signed overflow + set_grs_a5a5 + mov #16, r0 + movi20 #0x8000, r1 + shad r0, r1 ! r1 == 0x80000000 + mov #-1, r0 + divs r0, r1 + assertreg0 -1 + assertreg 0x7fffffff, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + +divu_1: ! divide by one, unsigned + set_grs_a5a5 + mov #1, r0 + divu r0, r1 + assertreg0 1 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divu_2: ! divide by two, unsigned + set_grs_a5a5 + mov #2, r0 + divu r0, r1 + assertreg0 2 + assertreg 0x52d2d2d2, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divu_3: ! divide by three, unsigned + set_grs_a5a5 + mov #3, r0 + divu r0, r1 + assertreg0 3 + assertreg 0x37373737, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divu_0: ! divide by zero, unsigned + set_grs_a5a5 + mov #0, r0 + divu r0, r1 + assertreg0 0 + assertreg 0xffffffff, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + + pass + + exit 0 + + \ No newline at end of file diff --git a/sim/testsuite/sh/dmxy.s b/sim/testsuite/sh/dmxy.s new file mode 100644 index 0000000..0e96963 --- /dev/null +++ b/sim/testsuite/sh/dmxy.s @@ -0,0 +1,21 @@ +# sh testcase for setdmx, setdmy, clrdmxy +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + setdmx + test_sr_bit_set 0x400 + test_sr_bit_clear 0x800 + setdmy + test_sr_bit_clear 0x400 + test_sr_bit_set 0x800 + clrdmxy + test_sr_bit_clear 0x400 + test_sr_bit_clear 0x800 + + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/fabs.s b/sim/testsuite/sh/fabs.s new file mode 100644 index 0000000..1fb354e --- /dev/null +++ b/sim/testsuite/sh/fabs.s @@ -0,0 +1,115 @@ +# sh testcase for fabs +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fabs_freg_b0: + single_prec + bank0 + set_grs_a5a5 + set_fprs_a5a5 + # fabs(0.0) = 0.0. + fldi0 fr0 + fabs fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bt .L1 + fail +.L1: + # fabs(1.0) = 1.0. + fldi1 fr0 + fabs fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt .L2 + fail +.L2: + # fabs(-1.0) = 1.0. + fldi1 fr0 + fneg fr0 + fabs fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt .L3 + fail +.L3: + test_grs_a5a5 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fabs_dreg_b0: + # double precision tests. + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # fabs(0.0) = 0.0. + fldi0 fr0 + flds fr0, fpul + fcnvsd fpul, dr0 + fabs dr0 + assert_dpreg_i 0 dr0 + + # fabs(1.0) = 1.0. + fldi1 fr0 + flds fr0, fpul + fcnvsd fpul, dr0 + fabs dr0 + assert_dpreg_i 1 dr0 + + # check. + fldi1 fr2 + flds fr2, fpul + fcnvsd fpul, dr2 + fcmp/eq dr0, dr2 + bt .L4 + fail + +.L4: + # fabs(-1.0) = 1.0. + fldi1 fr0 + fneg fr0 + flds fr0, fpul + fcnvsd fpul, dr0 + fabs dr0 + assert_dpreg_i 1 dr0 + + # check. + fldi1 fr2 + flds fr2, fpul + fcnvsd fpul, dr2 + fcmp/eq dr0, dr2 + bt .L5 + fail +.L5: + test_grs_a5a5 + assert_dpreg_i 1 dr0 + assert_dpreg_i 1 dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fadd.s b/sim/testsuite/sh/fadd.s new file mode 100644 index 0000000..72431f0 --- /dev/null +++ b/sim/testsuite/sh/fadd.s @@ -0,0 +1,75 @@ +# sh testcase for fadd +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fadd_freg_freg_b0: + set_grs_a5a5 + set_fprs_a5a5 + bank0 + + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + assert_fpreg_i 2 fr1 + + fldi0 fr0 + fldi1 fr1 + fadd fr0, fr1 + assert_fpreg_i 1 fr1 + + fldi1 fr0 + fldi0 fr1 + fadd fr0, fr1 + assert_fpreg_i 1 fr1 + test_grs_a5a5 + assert_fpreg_i 1 fr0 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fadd_dreg_dreg_b0: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + fldi1 fr0 + fldi1 fr2 + flds fr0, fpul + fcnvsd fpul, dr0 + flds fr2, fpul + fcnvsd fpul, dr2 + fadd dr0, dr2 + fcnvds dr2, fpul + fsts fpul, fr0 + + test_grs_a5a5 + assert_fpreg_i 2, fr0 + assert_dpreg_i 2, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fail.s b/sim/testsuite/sh/fail.s new file mode 100644 index 0000000..0ffb0b2 --- /dev/null +++ b/sim/testsuite/sh/fail.s @@ -0,0 +1,13 @@ +# sh testcase, fail +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + + fail + + exit 0 + diff --git a/sim/testsuite/sh/fcmpeq.s b/sim/testsuite/sh/fcmpeq.s new file mode 100644 index 0000000..9c0ef57 --- /dev/null +++ b/sim/testsuite/sh/fcmpeq.s @@ -0,0 +1,119 @@ +# sh testcase for fcmpeq +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fcmpeq_single: + set_grs_a5a5 + set_fprs_a5a5 + # 1.0 == 1.0. + fldi1 fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + # 0.0 != 1.0. + fldi0 fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf .L1 + fail +.L1: + # 1.0 != 0.0. + fldi1 fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bf .L2 + fail +.L2: + # 2.0 != 1.0 + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf .L3 + fail +.L3: + test_grs_a5a5 + assert_fpreg_i 2, fr0 + assert_fpreg_i 1, fr1 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fcmpeq_double: + # 1.0 == 1.0 + set_grs_a5a5 + set_fprs_a5a5 + double_prec + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L10 + fail +.L10: + # 0.0 != 1.0 + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bf .L11 + fail +.L11: + # 1.0 != 0.0 + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bf .L12 + fail +.L12: + # 2.0 != 1.0 + fldi1 fr0 + single_prec + fadd fr0, fr0 + double_prec + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bf .L13 + fail +.L13: + test_grs_a5a5 + assert_dpreg_i 2, dr0 + assert_dpreg_i 1, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 + diff --git a/sim/testsuite/sh/fcmpgt.s b/sim/testsuite/sh/fcmpgt.s new file mode 100644 index 0000000..c6945ba --- /dev/null +++ b/sim/testsuite/sh/fcmpgt.s @@ -0,0 +1,119 @@ +# sh testcase for fcmpgt +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fcmpgt_single: + set_grs_a5a5 + set_fprs_a5a5 + # 1.0 !> 1.0. + fldi1 fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bf .L0 + fail +.L0: + # 0.0 !> 1.0. + fldi0 fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bt .L1 + fail +.L1: + # 1.0 > 0.0. + fldi1 fr0 + fldi0 fr1 + fcmp/gt fr0, fr1 + bf .L2 + fail +.L2: + # 2.0 > 1.0 + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bf .L3 + fail +.L3: + test_grs_a5a5 + assert_fpreg_i 2, fr0 + assert_fpreg_i 1, fr1 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fcmpgt_double: + # double precision tests. + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # 1.0 !> 1.0. + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/gt dr0, dr2 + bf .L10 + fail +.L10: + # 0.0 !> 1.0. + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/gt dr0, dr2 + bt .L11 + fail +.L11: + # 1.0 > 0.0. + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/gt dr0, dr2 + bf .L12 + fail +.L12: + # 2.0 > 1.0. + fldi1 fr0 + single_prec + fadd fr0, fr0 + double_prec + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/gt dr0, dr2 + bf .L13 + fail +.L13: + test_grs_a5a5 + assert_dpreg_i 2, dr0 + assert_dpreg_i 1, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fcnvds.s b/sim/testsuite/sh/fcnvds.s new file mode 100644 index 0000000..cffcb49 --- /dev/null +++ b/sim/testsuite/sh/fcnvds.s @@ -0,0 +1,56 @@ +# sh testcase for fcnvds +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + double_prec + sz_64 + set_grs_a5a5 + set_fprs_a5a5 + mov.l ax, r0 + fmov @r0, dr0 + fcnvds dr0, fpul + fsts fpul, fr2 + + assert_dpreg_i 5, dr0 + single_prec + assert_fpreg_i 5, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + assertreg0 x + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + exit 0 + + .align 2 +x: .double 5.0 +ax: .long x + diff --git a/sim/testsuite/sh/fcnvsd.s b/sim/testsuite/sh/fcnvsd.s new file mode 100644 index 0000000..6592540 --- /dev/null +++ b/sim/testsuite/sh/fcnvsd.s @@ -0,0 +1,40 @@ +# sh testcase for fcnvsd +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + set_grs_a5a5 + set_fprs_a5a5 + double_prec + fldi1 fr0 + flds fr0, fpul + fcnvsd fpul, dr2 + assert_dpreg_i 1, dr2 + + # Convert back. + fcnvds dr2, fpul + fsts fpul, fr1 + single_prec + assert_fpreg_i 1, fr1 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + test_grs_a5a5 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 + diff --git a/sim/testsuite/sh/fdiv.s b/sim/testsuite/sh/fdiv.s new file mode 100644 index 0000000..629e774 --- /dev/null +++ b/sim/testsuite/sh/fdiv.s @@ -0,0 +1,91 @@ +# sh testcase for fdiv +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fdiv_single: + # Single test + set_grs_a5a5 + set_fprs_a5a5 + single_prec + # 1.0 / 0.0 should be INF + # (and not crash the sim). + fldi0 fr0 + fldi1 fr1 + fdiv fr0, fr1 + assert_fpreg_x 0x7f800000, fr1 + + # 0.0 / 1.0 == 0.0. + fldi0 fr0 + fldi1 fr1 + fdiv fr1, fr0 + assert_fpreg_x 0, fr0 + + # 2.0 / 1.0 == 2.0. + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + fdiv fr1, fr2 + assert_fpreg_i 2, fr2 + + # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + fdiv fr2, fr1 + # fr1 should contain 0.5. + fadd fr1, fr1 + assert_fpreg_i 1, fr1 + test_grs_a5a5 + assert_fpreg_i 2, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fdiv_double: + # Double test + set_grs_a5a5 + set_fprs_a5a5 + # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. + fldi1 fr1 + fldi1 fr2 + # This add must be in single precision. The rest must be in double. + fadd fr2, fr2 + double_prec + _s2d fr1, dr0 + _s2d fr2, dr2 + fdiv dr2, dr0 + # dr0 should contain 0.5. + # double it, expect 1.0. + fadd dr0, dr0 + assert_dpreg_i 1, dr0 + assert_dpreg_i 2, dr2 + test_grs_a5a5 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 + diff --git a/sim/testsuite/sh/fipr.s b/sim/testsuite/sh/fipr.s new file mode 100644 index 0000000..6a949aa --- /dev/null +++ b/sim/testsuite/sh/fipr.s @@ -0,0 +1,137 @@ +# sh testcase for fipr $fvm, $fvn +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +initv0: + set_grs_a5a5 + set_fprs_a5a5 + # Load 1 into fr0. + fldi1 fr0 + # Load 2 into fr1. + fldi1 fr1 + fadd fr1, fr1 + # Load 4 into fr2. + fldi1 fr2 + fadd fr2, fr2 + fadd fr2, fr2 + # Load 8 into fr3. + fmov fr2, fr3 + fadd fr2, fr3 + +initv8: + fldi1 fr8 + fldi0 fr9 + fldi1 fr10 + fldi0 fr11 + + fipr fv0, fv8 +test1: + # Result will be in fr11. + assert_fpreg_i 1, fr0 + assert_fpreg_i 2, fr1 + assert_fpreg_i 4, fr2 + assert_fpreg_i 8, fr3 + assert_fpreg_x 0xa5a5a5a5, fr4 + assert_fpreg_x 0xa5a5a5a5, fr5 + assert_fpreg_x 0xa5a5a5a5, fr6 + assert_fpreg_x 0xa5a5a5a5, fr7 + assert_fpreg_i 1, fr8 + assert_fpreg_i 0, fr9 + assert_fpreg_i 1, fr10 + assert_fpreg_i 5, fr11 + assert_fpreg_x 0xa5a5a5a5, fr12 + assert_fpreg_x 0xa5a5a5a5, fr13 + assert_fpreg_x 0xa5a5a5a5, fr14 + assert_fpreg_x 0xa5a5a5a5, fr15 + + test_grs_a5a5 +test_infp: + # Test positive infinity + fldi0 fr11 + mov.l infp, r0 + lds r0, fpul + fsts fpul, fr0 + fipr fv0, fv8 + # fr11 should be plus infinity + assert_fpreg_x 0x7f800000, fr11 +test_infm: + # Test negitive infinity + fldi0 fr11 + mov.l infm, r0 + lds r0, fpul + fsts fpul, fr0 + fipr fv0, fv8 + # fr11 should be plus infinity + assert_fpreg_x 0xff800000, fr11 +test_qnanp: + # Test positive qnan + fldi0 fr11 + mov.l qnanp, r0 + lds r0, fpul + fsts fpul, fr0 + fipr fv0, fv8 + # fr11 should be plus qnan (or greater) + flds fr11, fpul + sts fpul, r1 + cmp/ge r0, r1 + bt .L0 + fail +.L0: +test_snanp: + # Test positive snan + fldi0 fr11 + mov.l snanp, r0 + lds r0, fpul + fsts fpul, fr0 + fipr fv0, fv8 + # fr11 should be plus snan (or greater) + flds fr11, fpul + sts fpul, r1 + cmp/ge r0, r1 + bt .L1 + fail +.L1: +.if 0 + # Handling of nan and inf not implemented yet. +test_qnanm: + # Test negantive qnan + fldi0 fr11 + mov.l qnanm, r0 + lds r0, fpul + fsts fpul, fr0 + fipr fv0, fv8 + # fr11 should be minus qnan (or less) + flds fr11, fpul + sts fpul, r1 + cmp/ge r1, r0 + bt .L2 + fail +.L2: +test_snanm: + # Test negative snan + fldi0 fr11 + mov.l snanm, r0 + lds r0, fpul + fsts fpul, fr0 + fipr fv0, fv8 + # fr11 should be minus snan (or less) + flds fr11, fpul + sts fpul, r1 + cmp/ge r1, r0 + bt .L3 + fail +.L3: +.endif + pass + exit 0 + + .align 2 +qnanp: .long 0x7f800001 +qnanm: .long 0xff800001 +snanp: .long 0x7fc00000 +snanm: .long 0xffc00000 +infp: .long 0x7f800000 +infm: .long 0xff800000 diff --git a/sim/testsuite/sh/fldi0.s b/sim/testsuite/sh/fldi0.s new file mode 100644 index 0000000..1e20058 --- /dev/null +++ b/sim/testsuite/sh/fldi0.s @@ -0,0 +1,37 @@ +# sh testcase for fldi0 $frn +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fldi0_single: + set_grs_a5a5 + set_fprs_a5a5 + fldi0 fr0 + fldi0 fr2 + fldi0 fr4 + fldi0 fr6 + fldi0 fr8 + fldi0 fr10 + fldi0 fr12 + fldi0 fr14 + test_grs_a5a5 + assert_fpreg_i 0 fr0 + assert_fpreg_i 0 fr2 + assert_fpreg_i 0 fr4 + assert_fpreg_i 0 fr6 + assert_fpreg_i 0 fr8 + assert_fpreg_i 0 fr10 + assert_fpreg_i 0 fr12 + assert_fpreg_i 0 fr14 + assert_fpreg_x 0xa5a5a5a5 fr1 + assert_fpreg_x 0xa5a5a5a5 fr3 + assert_fpreg_x 0xa5a5a5a5 fr5 + assert_fpreg_x 0xa5a5a5a5 fr7 + assert_fpreg_x 0xa5a5a5a5 fr9 + assert_fpreg_x 0xa5a5a5a5 fr11 + assert_fpreg_x 0xa5a5a5a5 fr13 + assert_fpreg_x 0xa5a5a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sh/fldi1.s b/sim/testsuite/sh/fldi1.s new file mode 100644 index 0000000..1b7c170 --- /dev/null +++ b/sim/testsuite/sh/fldi1.s @@ -0,0 +1,38 @@ +# sh testcase for fldi1 $frn +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fldi1_single: + set_grs_a5a5 + set_fprs_a5a5 + fldi1 fr1 + fldi1 fr3 + fldi1 fr5 + fldi1 fr7 + fldi1 fr9 + fldi1 fr11 + fldi1 fr13 + fldi1 fr15 + test_grs_a5a5 + assert_fpreg_x 0xa5a5a5a5 fr0 + assert_fpreg_x 0xa5a5a5a5 fr2 + assert_fpreg_x 0xa5a5a5a5 fr4 + assert_fpreg_x 0xa5a5a5a5 fr6 + assert_fpreg_x 0xa5a5a5a5 fr8 + assert_fpreg_x 0xa5a5a5a5 fr10 + assert_fpreg_x 0xa5a5a5a5 fr12 + assert_fpreg_x 0xa5a5a5a5 fr14 + assert_fpreg_i 1 fr1 + assert_fpreg_i 1 fr3 + assert_fpreg_i 1 fr5 + assert_fpreg_i 1 fr7 + assert_fpreg_i 1 fr9 + assert_fpreg_i 1 fr11 + assert_fpreg_i 1 fr13 + assert_fpreg_i 1 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/flds.s b/sim/testsuite/sh/flds.s new file mode 100644 index 0000000..086b4ed --- /dev/null +++ b/sim/testsuite/sh/flds.s @@ -0,0 +1,43 @@ +# sh testcase for flds +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +flds_zero: + set_grs_a5a5 + set_fprs_a5a5 + fldi0 fr0 + flds fr0, fpul + fsts fpul, fr1 + fcmp/eq fr0, fr1 + bt flds_one + fail +flds_one: + fldi1 fr0 + flds fr0, fpul + fsts fpul, fr1 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + test_grs_a5a5 + assert_fpreg_i 1, fr0 + assert_fpreg_i 1, fr1 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sh/float.s b/sim/testsuite/sh/float.s new file mode 100644 index 0000000..e5a3bc6 --- /dev/null +++ b/sim/testsuite/sh/float.s @@ -0,0 +1,149 @@ +# sh testcase for float +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + +float_pos: + set_grs_a5a5 + set_fprs_a5a5 + single_prec + mov #3, r0 + lds r0, fpul + float fpul, fr2 + + # Check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + fcmp/eq fr1, fr2 + bt float_neg + fail + +float_neg: + mov #3, r0 + neg r0, r0 + lds r0, fpul + float fpul, fr2 + + # Check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + fneg fr1 + fcmp/eq fr1, fr2 + bt .L0 + fail +.L0: + assertreg0 -3 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + assert_fpreg_i 1, fr0 + assert_fpreg_i -3, fr1 + assert_fpreg_i -3, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +double_pos: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + mov #3, r0 + lds r0, fpul + float fpul, dr4 + + # check the result. + fldi1 fr0 + fldi1 fr1 + single_prec + fadd fr0, fr1 + fadd fr0, fr1 + double_prec + _s2d fr1, dr2 + fcmp/eq dr2, dr4 + bt double_neg + fail + +double_neg: + double_prec + mov #3, r0 + neg r0, r0 + lds r0, fpul + float fpul, dr4 + + # check the result. + fldi1 fr0 + fldi1 fr1 + single_prec + fadd fr0, fr1 + fadd fr0, fr1 + fneg fr1 + double_prec + _s2d fr1, dr2 + fcmp/eq dr2, dr4 + bt .L2 + fail +.L2: + assertreg0 -3 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + single_prec + assert_fpreg_i 1, fr0 + assert_fpreg_i -3, fr1 + double_prec + assert_dpreg_i -3, dr2 + assert_dpreg_i -3, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fmac.s b/sim/testsuite/sh/fmac.s new file mode 100644 index 0000000..eba1da5 --- /dev/null +++ b/sim/testsuite/sh/fmac.s @@ -0,0 +1,98 @@ +# sh testcase for fmac +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fmac_: + set_grs_a5a5 + set_fprs_a5a5 + # 0.0 * x + y = y. + + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + fcmp/eq fr0, fr2 + bt .L0 + fail +.L0: + # x * y + 0.0 = x * y. + + fldi1 fr0 + fldi1 fr1 + fldi0 fr2 + # double it. + fadd fr1, fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + fadd fr0, fr0 + fcmp/eq fr0, fr2 + bt .L1 + fail +.L1: + # x * 0.0 + y = y. + + fldi1 fr0 + fldi0 fr1 + fldi1 fr2 + fadd fr2, fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + # double fr0. + fadd fr0, fr0 + fcmp/eq fr0, fr2 + bt .L2 + fail +.L2: + # x * 0.0 + 0.0 = 0.0 + + fldi1 fr0 + fadd fr0, fr0 + fldi0 fr1 + fldi0 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi0 fr0 + fcmp/eq fr0, fr2 + bt .L3 + fail +.L3: + # 0.0 * x + 0.0 = 0.0. + + fldi0 fr0 + fldi1 fr1 + # double it. + fadd fr1, fr1 + fldi0 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi0 fr0 + fcmp/eq fr0, fr2 + bt .L4 + fail +.L4: + test_grs_a5a5 + assert_fpreg_i 0, fr0 + assert_fpreg_i 2, fr1 + assert_fpreg_i 0, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sh/fmov.s b/sim/testsuite/sh/fmov.s new file mode 100644 index 0000000..29c51b5 --- /dev/null +++ b/sim/testsuite/sh/fmov.s @@ -0,0 +1,322 @@ +# sh testcase for all fmov instructions +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + .macro init + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fldi1 fr3 + .endm + + start + +fmov1: # Test fr -> fr. + set_grs_a5a5 + set_fprs_a5a5 + init + single_prec + sz_32 + fmov fr0, fr1 + # Ensure fr0 and fr1 are now equal. + fcmp/eq fr0, fr1 + bt fmov2 + fail + +fmov2: # Test dr -> dr. + init + double_prec + sz_64 + fmov dr0, dr2 + # Ensure dr0 and dr2 are now equal. + fcmp/eq dr0, dr2 + bt fmov3 + fail + +fmov3: # Test dr -> xd and xd -> dr. + init + sz_64 + fmov dr0, xd0 + # Ensure dr0 and xd0 are now equal. + fmov xd0, dr2 + fcmp/eq dr0, dr2 + bt fmov4 + fail + +fmov4: # Test xd -> xd. + init + sz_64 + double_prec + fmov dr0, xd0 + fmov xd0, xd2 + fmov xd2, dr2 + # Ensure dr0 and dr2 are now equal. + fcmp/eq dr0, dr2 + bt .L0 + fail + + # FIXME: test fmov.s fr -> @gr, fmov dr -> @gr + # FIXME: test fmov.s @gr -> fr, fmov @gr -> dr + # FIXME: test fmov.s @gr+ -> fr, fmov @gr+ -> dr + # FIXME: test fmov.s fr -> @-gr, fmov dr -> @-gr + # FIXME: test fmov.s @(r0,gr) -> fr, fmov @(r0,gr) -> dr + # FIXME: test fmov.s fr -> @(r0,gr), fmov dr -> @(r0,gr) + +.L0: + test_grs_a5a5 + sz_32 + single_prec + assert_fpreg_i 0, fr0 + assert_fpreg_i 1, fr1 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fmov5: # Test fr -> @rn and @rn -> fr. + init + sz_32 + single_prec + # FIXME! Use a reserved memory location! + mov #40, r0 + shll8 r0 + fmov fr0, @r0 + fmov @r0, fr1 + fcmp/eq fr0, fr1 + bt fmov6 + fail + +fmov6: # Test dr -> @rn and @rn -> dr. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + fmov dr0, @r0 + fmov @r0, dr2 + fcmp/eq dr0, dr2 + bt fmov7 + fail + +fmov7: # Test xd -> @rn and @rn -> xd. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + fmov dr0, xd0 + fmov xd0, @r0 + fmov @r0, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt fmov8 + fail + +fmov8: # Test fr -> @-rn. + init + sz_32 + single_prec + mov #40, r0 + shll8 r0 + # Preserve. + mov r0, r1 + fmov fr0, @-r0 + fmov @r0, fr2 + fcmp/eq fr0, fr2 + bt f8b + fail +f8b: # check pre-dec. + add #4, r0 + cmp/eq r0, r1 + bt fmov9 + fail + +fmov9: # Test dr -> @-rn. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, @-r0 + fmov @r0, dr2 + fcmp/eq dr0, dr2 + bt f9b + fail +f9b: # check pre-dec. + add #8, r0 + cmp/eq r0, r1 + bt fmov10 + fail + +fmov10: # Test xd -> @-rn. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, xd0 + fmov xd0, @-r0 + fmov @r0, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt f10b + fail +f10b: # check pre-dec. + add #8, r0 + cmp/eq r0, r1 + bt fmov11 + fail + +fmov11: # Test @rn+ -> fr. + init + sz_32 + single_prec + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov fr0, @r0 + fmov @r0+, fr2 + fcmp/eq fr0, fr2 + bt f11b + fail +f11b: # check post-inc. + add #4, r1 + cmp/eq r0, r1 + bt fmov12 + fail + +fmov12: # Test @rn+ -> dr. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + # preserve r0. + mov r0, r1 + fmov dr0, @r0 + fmov @r0+, dr2 + fcmp/eq dr0, dr2 + bt f12b + fail +f12b: # check post-inc. + add #8, r1 + cmp/eq r0, r1 + bt fmov13 + fail + +fmov13: # Test @rn -> xd. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, xd0 + fmov xd0, @r0 + fmov @r0+, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt f13b + fail +f13b: + add #8, r1 + cmp/eq r0, r1 + bt fmov14 + fail + +fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr. + init + sz_32 + single_prec + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov fr0, @(r0, r1) + fmov @(r0, r1), fr1 + fcmp/eq fr0, fr1 + bt fmov15 + fail + +fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov dr0, @(r0, r1) + fmov @(r0, r1), dr2 + fcmp/eq dr0, dr2 + bt fmov16 + fail + +fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov dr0, xd0 + fmov xd0, @(r0, r1) + fmov @(r0, r1), xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt .L1 + fail +.L1: + assertreg0 0x2800 + assertreg 0, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + sz_32 + single_prec + assert_fpreg_i 0, fr0 + assert_fpreg_i 1, fr1 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fmul.s b/sim/testsuite/sh/fmul.s new file mode 100644 index 0000000..81a2545 --- /dev/null +++ b/sim/testsuite/sh/fmul.s @@ -0,0 +1,116 @@ +# sh testcase for fmul +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + .macro init + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + .endm + + start +fmul_single: + set_grs_a5a5 + set_fprs_a5a5 + # 0.0 * 0.0 = 0.0. + init + fmul fr0, fr0 + assert_fpreg_i 0, fr0 + + # 0.0 * 1.0 = 0.0. + init + fmul fr1, fr0 + assert_fpreg_i 0, fr0 + + # 1.0 * 0.0 = 0.0. + init + fmul fr0, fr1 + assert_fpreg_i 0, fr1 + + # 1.0 * 1.0 = 1.0. + init + fmul fr1, fr1 + assert_fpreg_i 1, fr1 + + # 2.0 * 1.0 = 2.0. + init + fmul fr2, fr1 + assert_fpreg_i 2, fr1 + + test_grs_a5a5 + assert_fpreg_i 0, fr0 + assert_fpreg_i 2, fr1 + assert_fpreg_i 2, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + .macro dinit + fldi0 fr0 + fldi1 fr2 + fldi1 fr4 + single_prec + fadd fr4, fr4 + double_prec + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + .endm + +fmul_double: + double_prec + # 0.0 * 0.0 = 0.0. + dinit + fmul dr0, dr0 + assert_dpreg_i 0, dr0 + + # 0.0 * 1.0 = 0.0. + dinit + fmul dr2, dr0 + assert_dpreg_i 0, dr0 + + # 1.0 * 0.0 = 0.0. + dinit + fmul dr0, dr2 + assert_dpreg_i 0, dr2 + + # 1.0 * 1.0 = 1.0. + dinit + fmul dr2, dr2 + assert_dpreg_i 1, dr2 + + # 2.0 * 1.0 = 2.0. + dinit + fmul dr4, dr2 + assert_dpreg_i 2, dr2 + + test_grs_a5a5 + assert_dpreg_i 0, dr0 + assert_dpreg_i 2, dr2 + assert_dpreg_i 2, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fneg.s b/sim/testsuite/sh/fneg.s new file mode 100644 index 0000000..dd5fe5d --- /dev/null +++ b/sim/testsuite/sh/fneg.s @@ -0,0 +1,112 @@ +# sh testcase for fneg +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fneg_single: + set_grs_a5a5 + set_fprs_a5a5 + # neg(0.0) = 0.0. + fldi0 fr0 + fldi0 fr1 + fneg fr0 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + # neg(1.0) = fsub(0,1) + fldi1 fr0 + fneg fr0 + fldi0 fr1 + fldi1 fr2 + fsub fr2, fr1 + fcmp/eq fr0, fr1 + bt .L1 + fail +.L1: + # neg(neg(1.0)) = 1.0. + fldi1 fr0 + fldi1 fr1 + fneg fr0 + fneg fr0 + fcmp/eq fr0, fr1 + bt .L2 + fail +.L2: + test_grs_a5a5 + assert_fpreg_i 1, fr0 + assert_fpreg_i 1, fr1 + assert_fpreg_i 1, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fneg_double: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # neg(0.0) = 0.0. + fldi0 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fneg dr0 + fcmp/eq dr0, dr2 + bt .L10 + fail +.L10: + # neg(1.0) = fsub(0,1) + fldi1 fr0 + _s2d fr0, dr0 + fneg dr0 + fldi0 fr2 + fldi1 fr3 + single_prec + fsub fr3, fr2 + double_prec + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L11 + fail +.L11: + # neg(neg(1.0)) = 1.0. + fldi1 fr0 + _s2d fr0, dr0 + fldi1 fr2 + _s2d fr2, dr2 + fneg dr2 + fneg dr2 + fcmp/eq dr0, dr2 + bt .L12 + fail +.L12: + test_grs_a5a5 + assert_dpreg_i 1, dr0 + assert_dpreg_i 1, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fpchg.s b/sim/testsuite/sh/fpchg.s new file mode 100644 index 0000000..47ba03b --- /dev/null +++ b/sim/testsuite/sh/fpchg.s @@ -0,0 +1,30 @@ +# sh testcase for fpchg +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + set_grs_a5a5 + set_fprs_a5a5 + sts fpscr, r0 + assertreg0 0 + fpchg + sts fpscr, r0 + assertreg0 0x80000 + fpchg + sts fpscr, r0 + assertreg0 0 + fpchg + sts fpscr, r0 + assertreg0 0x80000 + fpchg + sts fpscr, r0 + assertreg0 0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + test_fprs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sh/frchg.s b/sim/testsuite/sh/frchg.s new file mode 100644 index 0000000..c5dc099 --- /dev/null +++ b/sim/testsuite/sh/frchg.s @@ -0,0 +1,30 @@ +# sh testcase for frchg +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + set_grs_a5a5 + set_fprs_a5a5 + sts fpscr, r0 + assertreg0 0 + frchg + sts fpscr, r0 + assertreg0 0x200000 + frchg + sts fpscr, r0 + assertreg0 0 + frchg + sts fpscr, r0 + assertreg0 0x200000 + frchg + sts fpscr, r0 + assertreg0 0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + test_fprs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sh/fsca.s b/sim/testsuite/sh/fsca.s new file mode 100644 index 0000000..90df6c9 --- /dev/null +++ b/sim/testsuite/sh/fsca.s @@ -0,0 +1,97 @@ +# sh testcase for fsca +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsca: + set_grs_a5a5 + set_fprs_a5a5 + # Start with angle zero + mov.l zero, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + + mov.l plus_90, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 1, fr2 + assert_fpreg_i 0, fr3 + + mov.l plus_180, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i -1, fr3 + + mov.l plus_270, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i -1, fr2 + assert_fpreg_i 0, fr3 + + mov.l plus_360, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + + mov.l minus_90, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i -1, fr2 + assert_fpreg_i 0, fr3 + + mov.l minus_180, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i -1, fr3 + + mov.l minus_270, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 1, fr2 + assert_fpreg_i 0, fr3 + + mov.l minus_360, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + + assertreg0 0xffff0000 + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + test_fpr_a5a5 fr0 + test_fpr_a5a5 fr1 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 + + .align 2 +zero: .long 0 +one_bitty: .long 1 +plus_90: .long 0x04000 +plus_180: .long 0x08000 +plus_270: .long 0x0c000 +plus_360: .long 0x10000 +minus_90: .long 0xffffc000 +minus_180: .long 0xffff8000 +minus_270: .long 0xffff4000 +minus_360: .long 0xffff0000 +minus_1_bitty: .long 0xffffffff diff --git a/sim/testsuite/sh/fschg.s b/sim/testsuite/sh/fschg.s new file mode 100644 index 0000000..7454787 --- /dev/null +++ b/sim/testsuite/sh/fschg.s @@ -0,0 +1,29 @@ +# sh testcase for fschg +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + set_grs_a5a5 + set_fprs_a5a5 + sts fpscr, r0 + assertreg0 0 + fschg + sts fpscr, r0 + assertreg0 0x100000 + fschg + sts fpscr, r0 + assertreg0 0 + fschg + sts fpscr, r0 + assertreg0 0x100000 + fschg + sts fpscr, r0 + assertreg0 0 + + set_greg 0xa5a5a5a5 r0 + test_grs_a5a5 + test_fprs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/fsqrt.s b/sim/testsuite/sh/fsqrt.s new file mode 100644 index 0000000..cb61bcf --- /dev/null +++ b/sim/testsuite/sh/fsqrt.s @@ -0,0 +1,120 @@ +# sh testcase for fsqrt +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsqrt_single: + set_grs_a5a5 + set_fprs_a5a5 + # sqrt(0.0) = 0.0. + fldi0 fr0 + fsqrt fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + # sqrt(1.0) = 1.0. + fldi1 fr0 + fsqrt fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt .L1 + fail +.L1: + # sqrt(4.0) = 2.0 + fldi1 fr0 + # Double it. + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + fsqrt fr0 + fldi1 fr1 + # Double it. + fadd fr1, fr1 + fcmp/eq fr0, fr1 + bt .L2 + fail +.L2: + test_grs_a5a5 + assert_fpreg_i 2, fr0 + assert_fpreg_i 2, fr1 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fsqrt_double: + double_prec + set_grs_a5a5 + set_fprs_a5a5 + # sqrt(0.0) = 0.0. + fldi0 fr0 + _s2d fr0, dr0 + fsqrt dr0 + fldi0 fr2 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L10 + fail +.L10: + # sqrt(1.0) = 1.0. + fldi1 fr0 + _s2d fr0, dr0 + fsqrt dr0 + fldi1 fr2 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L11 + fail +.L11: + # sqrt(4.0) = 2.0. + fldi1 fr0 + # Double it. + single_prec + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + double_prec + _s2d fr0, dr0 + fsqrt dr0 + fldi1 fr2 + # Double it. + single_prec + fadd fr2, fr2 + double_prec + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L12 + fail +.L12: + test_grs_a5a5 + assert_dpreg_i 2, dr0 + assert_dpreg_i 2, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fsrra.s b/sim/testsuite/sh/fsrra.s new file mode 100644 index 0000000..fdd2235 --- /dev/null +++ b/sim/testsuite/sh/fsrra.s @@ -0,0 +1,62 @@ +# sh testcase for fsrra +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsrra_single: + set_grs_a5a5 + set_fprs_a5a5 + # 1/sqrt(0.0) = +infinity. + fldi0 fr0 + fsrra fr0 + assert_fpreg_x 0x7f800000, fr0 + + # 1/sqrt(1.0) = 1.0. + fldi1 fr0 + fsrra fr0 + assert_fpreg_i 1, fr0 + + # 1/sqrt(4.0) = 1/2.0 + fldi1 fr0 + # Double it. + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + fsrra fr0 + fldi1 fr2 + # Double it. + fadd fr2, fr2 + fldi1 fr1 + # Divide + fdiv fr2, fr1 + fcmp/eq fr0, fr1 + bt .L2 + fail +.L2: + # Double-check (pun intended) + fadd fr0, fr0 + assert_fpreg_i 1, fr0 + fadd fr1, fr1 + assert_fpreg_i 1, fr1 + + # And make sure the rest of the regs are un-affected. + assert_fpreg_i 2, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + test_grs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sh/fsub.s b/sim/testsuite/sh/fsub.s new file mode 100644 index 0000000..dfe9172 --- /dev/null +++ b/sim/testsuite/sh/fsub.s @@ -0,0 +1,136 @@ +# sh testcase for fsub +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsub_single: + set_grs_a5a5 + set_fprs_a5a5 + # 0.0 - 0.0 = 0.0. + fldi0 fr0 + fldi0 fr1 + fsub fr0, fr1 + fldi0 fr2 + fcmp/eq fr1, fr2 + bt .L0 + fail +.L0: + # 1.0 - 0.0 = 1.0. + fldi0 fr0 + fldi1 fr1 + fsub fr0, fr1 + fldi1 fr2 + fcmp/eq fr1, fr2 + bt .L1 + fail +.L1: + # 1.0 - 1.0 = 0.0. + fldi1 fr0 + fldi1 fr1 + fsub fr0, fr1 + fldi0 fr2 + fcmp/eq fr1, fr2 + bt .L2 + fail +.L2: + # 0.0 - 1.0 = -1.0. + fldi1 fr0 + fldi0 fr1 + fsub fr0, fr1 + fldi1 fr2 + fneg fr2 + fcmp/eq fr1, fr2 + bt .L3 + fail +.L3: + test_grs_a5a5 + assert_fpreg_i 1, fr0 + assert_fpreg_i -1, fr1 + assert_fpreg_i -1, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fsub_double: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # 0.0 - 0.0 = 0.0. + fldi0 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi0 fr4 + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L10 + fail +.L10: + # 1.0 - 0.0 = 1.0. + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi1 fr4 + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L11 + fail +.L11: + # 1.0 - 1.0 = 0.0. + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi0 fr4 + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L12 + fail +.L12: + # 0.0 - 1.0 = -1.0. + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi1 fr4 + single_prec + fneg fr4 + double_prec + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L13 + fail +.L13: + test_grs_a5a5 + assert_dpreg_i 1, dr0 + assert_dpreg_i -1, dr2 + assert_dpreg_i -1, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sh/ftrc.s b/sim/testsuite/sh/ftrc.s new file mode 100644 index 0000000..25e33be --- /dev/null +++ b/sim/testsuite/sh/ftrc.s @@ -0,0 +1,156 @@ +# sh testcase for ftrc +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +ftrc_single: + set_grs_a5a5 + set_fprs_a5a5 + # ftrc(0.0) = 0. + fldi0 fr0 + ftrc fr0, fpul + # check results. + mov #0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L0 + fail +.L0: + # ftrc(1.5) = 1. + fldi1 fr0 + fldi1 fr1 + fldi1 fr2 + # double it. + fadd fr2, fr2 + # form the fraction. + fdiv fr2, fr1 + fadd fr1, fr0 + # now we've got 1.5 in fr0. + ftrc fr0, fpul + # check results. + mov #1, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L1 + fail +.L1: + # ftrc(-1.5) = -1. + fldi1 fr0 + fneg fr0 + fldi1 fr1 + fldi1 fr2 + # double it. + fadd fr2, fr2 + # form the fraction. + fdiv fr2, fr1 + fneg fr1 + # -1 + -0.5 = -1.5. + fadd fr1, fr0 + # now we've got 1.5 in fr0. + ftrc fr0, fpul + # check results. + mov #1, r0 + neg r0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt ftrc_double + fail + +ftrc_double: + double_prec + # ftrc(0.0) = 0. + fldi0 fr0 + _s2d fr0, dr0 + ftrc dr0, fpul + # check results. + mov #0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L10 + fail +.L10: + # ftrc(1.5) = 1. + fldi1 fr0 + fldi1 fr2 + fldi1 fr4 + # double it. + single_prec + fadd fr4, fr4 + # form 0.5. + fdiv fr4, fr2 + fadd fr2, fr0 + double_prec + # now we've got 1.5 in fr0, so do some single->double + # conversions and perform the ftrc. + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + ftrc dr0, fpul + + # check results. + mov #1, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L11 + fail +.L11: + # ftrc(-1.5) = -1. + fldi1 fr0 + fneg fr0 + fldi1 fr2 + fldi1 fr4 + single_prec + # double it. + fadd fr4, fr4 + # form the fraction. + fdiv fr4, fr2 + fneg fr2 + # -1 + -0.5 = -1.5. + fadd fr2, fr0 + double_prec + # now we've got 1.5 in fr0, so do some single->double + # conversions and perform the ftrc. + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + ftrc dr0, fpul + + # check results. + mov #1, r0 + neg r0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L12 + fail +.L12: + assertreg0 -1 + assertreg -1, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + assert_dpreg_i 2, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sh/ldrc.s b/sim/testsuite/sh/ldrc.s new file mode 100644 index 0000000..4441313 --- /dev/null +++ b/sim/testsuite/sh/ldrc.s @@ -0,0 +1,118 @@ +# sh testcase for ldrc, strc +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +setrc_imm: + set_grs_a5a5 + # Test setrc + # + ldrs lstart + ldre lend + setrc #0xff + get_sr r1 + shlr16 r1 + set_greg 0xfff, r0 + and r0, r1 + assertreg 0xff, r1 + + stc rs, r0 ! rs unchanged + assertreg0 lstart + stc re, r0 ! re unchanged + assertreg0 lend + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + +setrc_reg: + set_grs_a5a5 + # Test setrc + # + ldrs lstart + ldre lend + set_greg 0xfff, r0 + setrc r0 + get_sr r1 + shlr16 r1 + set_greg 0xfff, r0 + and r0, r1 + assertreg 0xfff, r1 + + stc rs, r0 ! rs unchanged + assertreg0 lstart + stc re, r0 ! re unchanged + assertreg0 lend + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + + bra ldrc_imm + + .global lstart + .align 2 +lstart: nop + nop + nop + nop + .global lend + .align 2 +lend: nop + nop + nop + nop + +ldrc_imm: + set_grs_a5a5 + # Test ldrc + setrc #0x0 ! zero rc + ldrc #0xa5 + get_sr r1 + shlr16 r1 + set_greg 0xfff, r0 + and r0, r1 + assertreg 0xa5, r1 + stc rs, r0 ! rs unchanged + assertreg0 lstart + stc re, r0 + assertreg0 lend+1 ! bit 0 set in re + + # fix up re for next test + dt r0 ! Ugh! No DEC insn! + ldc r0, re + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + +ldrc_reg: + set_grs_a5a5 + # Test ldrc + setrc #0x0 ! zero rc + set_greg 0xa5a, r0 + ldrc r0 + get_sr r1 + shlr16 r1 + set_greg 0xfff, r0 + and r0, r1 + assertreg 0xa5a, r1 + stc rs, r0 ! rs unchanged + assertreg0 lstart + stc re, r0 + assertreg0 lend+1 ! bit 0 set in re + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + + pass + exit 0 + diff --git a/sim/testsuite/sh/loop.s b/sim/testsuite/sh/loop.s new file mode 100644 index 0000000..6040519 --- /dev/null +++ b/sim/testsuite/sh/loop.s @@ -0,0 +1,311 @@ +# sh testcase for loop control +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start +loop1: + set_grs_a5a5 + + ldrs Loop1_start0+8 + ldre Loop1_start0+4 + setrc #5 +Loop1_start0: + add #1, r1 ! Before loop + # Loop should execute one instruction five times. +Loop1_begin: + add #1, r1 ! Within loop +Loop1_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before) + assertreg 0xa5a5a5a5+8, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop2: + set_grs_a5a5 + + ldrs Loop2_start0+6 + ldre Loop2_start0+4 + setrc #5 +Loop2_start0: + add #1, r1 ! Before loop + # Loop should execute two instructions five times. +Loop2_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loop2_end: + add #3, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 14 (ten in loop, three after, one before) + assertreg 0xa5a5a5a5+14, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop3: + set_grs_a5a5 + + ldrs Loop3_start0+4 + ldre Loop3_start0+4 + setrc #5 +Loop3_start0: + add #1, r1 ! Before loop + # Loop should execute three instructions five times. +Loop3_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loop3_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before) + assertreg 0xa5a5a5a5+18, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop4: + set_grs_a5a5 + + ldrs Loop4_begin + ldre Loop4_last3+4 + setrc #5 + add #1, r1 ! Before loop + # Loop should execute four instructions five times. +Loop4_begin: +Loop4_last3: + add #1, r1 ! Within loop +Loop4_last2: + add #1, r1 ! Within loop +Loop4_last1: + add #1, r1 ! Within loop +Loop4_last: + add #1, r1 ! Within loop +Loop4_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 23 (20 in loop, two after, one before) + assertreg 0xa5a5a5a5+23, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop5: + set_grs_a5a5 + + ldrs Loop5_begin + ldre Loop5_last3+4 + setrc #5 + add #1, r1 ! Before loop + # Loop should execute five instructions five times. +Loop5_begin: + add #1, r1 ! Within loop +Loop5_last3: + add #1, r1 ! Within loop +Loop5_last2: + add #1, r1 ! Within loop +Loop5_last1: + add #1, r1 ! Within loop +Loop5_last: + add #1, r1 ! Within loop +Loop5_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 28 (25 in loop, two after, one before) + assertreg 0xa5a5a5a5+28, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loopn: + set_grs_a5a5 + + ldrs Loopn_begin + ldre Loopn_last3+4 + setrc #5 + add #1, r1 ! Before loop + # Loop should execute n instructions five times. +Loopn_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loopn_last3: + add #1, r1 ! Within loop +Loopn_last2: + add #1, r1 ! Within loop +Loopn_last1: + add #1, r1 ! Within loop +Loopn_last: + add #1, r1 ! Within loop +Loopn_end: + add #3, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 64 (60 in loop, three after, one before) + assertreg 0xa5a5a5a5+64, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop1e: + set_grs_a5a5 + + ldrs Loop1e_begin + ldre Loop1e_last + ldrc #5 + add #1, r1 ! Before loop + # Loop should execute one instruction five times. +Loop1e_begin: +Loop1e_last: + add #1, r1 ! Within loop +Loop1e_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before) + assertreg 0xa5a5a5a5+8, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop2e: + set_grs_a5a5 + + ldrs Loop2e_begin + ldre Loop2e_last + ldrc #5 + add #1, r1 ! Before loop + # Loop should execute two instructions five times. +Loop2e_begin: + add #1, r1 ! Within loop +Loop2e_last: + add #1, r1 ! Within loop +Loop2e_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 13 (ten in loop, two after, one before) + assertreg 0xa5a5a5a5+13, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop3e: + set_grs_a5a5 + + ldrs Loop3e_begin + ldre Loop3e_last + ldrc #5 + add #1, r1 ! Before loop + # Loop should execute three instructions five times. +Loop3e_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loop3e_last: + add #1, r1 ! Within loop +Loop3e_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before) + assertreg 0xa5a5a5a5+18, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop4e: + set_grs_a5a5 + + ldrs Loop4e_begin + ldre Loop4e_last + ldrc #5 + add #1, r1 ! Before loop + # Loop should execute four instructions five times. +Loop4e_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loop4e_last: + add #1, r1 ! Within loop +Loop4e_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 23 (twenty in loop, two after, one before) + assertreg 0xa5a5a5a5+23, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop5e: + set_grs_a5a5 + + ldrs Loop5e_begin + ldre Loop5e_last + ldrc #5 + add #1, r1 ! Before loop + # Loop should execute five instructions five times. +Loop5e_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loop5e_last: + add #1, r1 ! Within loop +Loop5e_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 28 (twenty five in loop, two after, one before) + assertreg 0xa5a5a5a5+28, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop_n_e: + set_grs_a5a5 + + ldrs Loop_n_e_begin + ldre Loop_n_e_last + ldrc #5 + add #1, r1 ! Before loop + # Loop should execute n instructions five times. +Loop_n_e_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loop_n_e_last: + add #1, r1 ! Within loop +Loop_n_e_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 48 (forty five in loop, two after, one before) + assertreg 0xa5a5a5a5+48, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + + pass + + exit 0 + diff --git a/sim/testsuite/sh/macl.s b/sim/testsuite/sh/macl.s new file mode 100644 index 0000000..39b3b7d --- /dev/null +++ b/sim/testsuite/sh/macl.s @@ -0,0 +1,54 @@ +# sh testcase for mac.l +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + # force S-bit clear + clrs + +init: + # Prime {MACL, MACH} to #1. + mov #1, r0 + dmulu.l r0, r0 + + # Set up addresses. + mov.l pfour00, r0 ! 85 + mov.l pfour12, r1 ! 17 + +test: + mac.l @r0+, @r1+ + +check: + # Check result. + assert_sreg 0, mach + assert_sreg 85*17+1, macl + + # Ensure post-increment occurred. + assertreg0 four00+4 + assertreg four12+4, r1 + +doubleinc: + mov.l pfour00, r0 + mac.l @r0+, @r0+ + assertreg0 four00+8 + + + pass + exit 0 + + .align 1 +four00: + .long 85 + .long 2 +four12: + .long 17 + .long 3 + + .align 2 +pfour00: + .long four00 +pfour12: + .long four12 diff --git a/sim/testsuite/sh/macw.s b/sim/testsuite/sh/macw.s new file mode 100644 index 0000000..7e3ebc0 --- /dev/null +++ b/sim/testsuite/sh/macw.s @@ -0,0 +1,56 @@ +# sh testcase for mac.w +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + + # Prime {MACL, MACH} to #1. + mov #1, r0 + dmulu.l r0, r0 + + # Set up addresses. + mov.l pfour00, r0 ! 85 + mov.l pfour12, r1 ! 17 + +test: + mac.w @r0+, @r1+ ! MAC = 85 * 17 + 1 + +check: + # Check result. + assert_sreg 0, mach + assert_sreg 85*17+1, macl + + # Ensure post-increment occurred. + assertreg0 four00+2 + assertreg four12+2, r1 + +doubleinc: + mov.l pfour00, r0 + mac.w @r0+, @r0+ + assertreg0 four00+4 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + + pass + exit 0 + + .align 2 +four00: + .word 85 + .word 2 +four12: + .word 17 + .word 3 + + +pfour00: + .long four00 +pfour12: + .long four12 diff --git a/sim/testsuite/sh/mov.s b/sim/testsuite/sh/mov.s new file mode 100644 index 0000000..37fef51 --- /dev/null +++ b/sim/testsuite/sh/mov.s @@ -0,0 +1,118 @@ +# sh testcase for all mov.[bwl] instructions +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + .align 2 +_lsrc: .long 0x55555555 +_wsrc: .long 0x55550000 +_bsrc: .long 0x55000000 + + .align 2 +_ldst: .long 0 +_wdst: .long 0 +_bdst: .long 0 + + + start + +movb_disp12_reg: # Test 8-bit @(disp12,gr) -> gr + set_grs_a5a5 + mov.l bsrc, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.b @(444,r1), r2 + + assertreg _bsrc-444, r1 + assertreg 0x55, r2 + +movb_reg_disp12: # Test 8-bit gr -> @(disp12,gr) + set_grs_a5a5 + mov.l bdst, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.b r2, @(444,r1) + + assertreg _bdst-444, r1 + assertmem _bdst, 0xa5000000 + +movw_disp12_reg: # Test 16-bit @(disp12,gr) -> gr + set_grs_a5a5 + mov.l wsrc, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.w @(444,r1), r2 + + assertreg _wsrc-444, r1 + assertreg 0x5555, r2 + +movw_reg_disp12: # Test 16-bit gr -> @(disp12,gr) + set_grs_a5a5 + mov.l wdst, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.w r2, @(444,r1) + + assertreg _wdst-444, r1 + assertmem _wdst, 0xa5a50000 + +movl_disp12_reg: # Test 32-bit @(disp12,gr) -> gr + set_grs_a5a5 + mov.l lsrc, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.l @(444,r1), r2 + + assertreg _lsrc-444, r1 + assertreg 0x55555555, r2 + +movl_reg_disp12: # Test 32-bit gr -> @(disp12,gr) + set_grs_a5a5 + mov.l ldst, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.l r2, @(444,r1) + + assertreg _ldst-444, r1 + assertmem _ldst, 0xa5a5a5a5 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + +lsrc: .long _lsrc +wsrc: .long _wsrc +bsrc: .long _bsrc + +ldst: .long _ldst +wdst: .long _wdst +bdst: .long _bdst + diff --git a/sim/testsuite/sh/movi.s b/sim/testsuite/sh/movi.s new file mode 100644 index 0000000..e54f4f6 --- /dev/null +++ b/sim/testsuite/sh/movi.s @@ -0,0 +1,76 @@ +# sh testcase for all mov <#imm> instructions +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + +mov_i_reg: # Test + set_grs_a5a5 + mov #-0x55, r1 + + assertreg 0xffffffab, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +movi20_reg: # Test + set_grs_a5a5 + movi20 #-0x55555,r1 + + assertreg 0xfffaaaab, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +movi20s_reg: # Test << 8 + set_grs_a5a5 + movi20s #-0x5555500,r1 + + assertreg 0xfaaaab00, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/movli.s b/sim/testsuite/sh/movli.s new file mode 100644 index 0000000..eacd103 --- /dev/null +++ b/sim/testsuite/sh/movli.s @@ -0,0 +1,55 @@ +# sh testcase for movli +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +x: .long 1 +y: .long 2 +z: .long 3 + + start + set_grs_a5a5 + mov.l xptr, r1 + mov.l yptr, r2 + # Move linked/conditional, x to y + movli.l @r1, r0 + movco.l r0, @r2 + + # Check result. + assertreg0 1 + mov.l yptr, r1 + mov.l @r1, r2 + assertreg 1, r2 + + # Now attempt an unlinked move of r0 to z + mov.l zptr, r1 + movco.l r0, @r1 + + # Check that z is unchanged. + mov.l zptr, r1 + mov.l @r1, r2 + assertreg 3, r2 + + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + exit 0 + + .align 2 +xptr: .long x +yptr: .long y +zptr: .long z diff --git a/sim/testsuite/sh/movua.s b/sim/testsuite/sh/movua.s new file mode 100644 index 0000000..fa12fe5 --- /dev/null +++ b/sim/testsuite/sh/movua.s @@ -0,0 +1,197 @@ +# sh testcase for movua +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start +movua_1: + set_grs_a5a5 + mov.l srcp, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x03020100 +.else + assertreg0 0x00010203 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x04030201 +.else + assertreg0 0x01020304 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x05040302 +.else + assertreg0 0x02030405 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x06050403 +.else + assertreg0 0x03040506 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x07060504 +.else + assertreg0 0x04050607 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x08070605 +.else + assertreg0 0x05060708 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x09080706 +.else + assertreg0 0x06070809 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0a090807 +.else + assertreg0 0x0708090a +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0b0a0908 +.else + assertreg0 0x08090a0b +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0c0b0a09 +.else + assertreg0 0x090a0b0c +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0d0c0b0a +.else + assertreg0 0x0a0b0c0d +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0e0d0c0b +.else + assertreg0 0x0b0c0d0e +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0f0e0d0c +.else + assertreg0 0x0c0d0e0f +.endif + + assertreg src+12, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + bra movua_4: + nop + + .align 0 +src: .byte 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 + .align 2 +srcp: .long src + +movua_4: + set_grs_a5a5 + mov.l srcp2, r1 + movua.l @r1+, r0 +.ifdef LITTLE + assertreg0 0x03020100 +.else + assertreg0 0x00010203 +.endif + assertreg src+4, r1 + + mov.l srcp2, r1 + add #1, r1 + movua.l @r1+, r0 +.ifdef LITTLE + assertreg0 0x04030201 +.else + assertreg0 0x01020304 +.endif + assertreg src+5, r1 + + mov.l srcp2, r1 + add #2, r1 + movua.l @r1+, r0 +.ifdef LITTLE + assertreg0 0x05040302 +.else + assertreg0 0x02030405 +.endif + assertreg src+6, r1 + + mov.l srcp2, r1 + add #3, r1 + movua.l @r1+, r0 +.ifdef LITTLE + assertreg0 0x06050403 +.else + assertreg0 0x03040506 +.endif + assertreg src+7, r1 + + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + exit 0 + +srcp2: .long src + diff --git a/sim/testsuite/sh/movxy.s b/sim/testsuite/sh/movxy.s new file mode 100644 index 0000000..7768ef9 --- /dev/null +++ b/sim/testsuite/sh/movxy.s @@ -0,0 +1,1186 @@ +# sh testcase for movxy +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +src1: .word 1 +src2: .word 2 +src3: .word 3 +src4: .word 4 +src5: .word 5 +src6: .word 6 +src7: .word 7 +src8: .word 8 +src9: .word 9 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + +dst1: .word 0 +dst2: .word 0 +dst3: .word 0 +dst4: .word 0 +dst5: .word 0 +dst6: .word 0 +dst7: .word 0 +dst8: .word 0 +dst9: .word 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + + start +movxw_nopy: + set_grs_a5a5 + # load up pointers + mov.l srcp1, r4 + mov.l dstp1, r5 + + # perform moves + movx.w @r4, x0 + pcopy x0, a0 + movx.w a0, @r5 + + # verify pointers unchanged + mov.l srcp1, r0 + cmp/eq r0, r4 + bt .L0 + fail +.L0: + mov.l dstp1, r1 + cmp/eq r1, r5 + bt .L1 + fail +.L1: + # verify copied values + mov.w @r0, r0 + mov.w @r1, r1 + cmp/eq r0, r1 + bt .L2 + fail +.L2: + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +movyw_nopx: + set_grs_a5a5 + # load up pointers + mov.l srcp2, r6 + mov.l dstp2, r7 + + # perform moves + movy.w @r6, y0 + pcopy y0, a0 + movy.w a0, @r7 + + # verify pointers unchanged + mov.l srcp2, r2 + cmp/eq r2, r6 + bt .L3 + fail +.L3: + mov.l dstp2, r3 + cmp/eq r3, r7 + bt .L4 + fail +.L4: + # verify copied values + mov.w @r2, r2 + mov.w @r3, r3 + cmp/eq r2, r3 + bt .L5 + fail +.L5: + test_gr_a5a5 r0 + test_gr_a5a5 r1 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +movxw_movyw: + set_grs_a5a5 + # load up pointers + mov.l srcp3, r4 + mov.l dstp3, r5 + mov.l srcp4, r6 + mov.l dstp4, r7 + + # perform moves + movx.w @r4, x1 movy.w @r6, y1 + pcopy x1, a0 + pcopy y1, a1 + movx.w a0, @r5 movy.w a1, @r7 + + # verify pointers unchanged + mov.l srcp3, r0 + cmp/eq r0, r4 + bt .L6 + fail +.L6: + mov.l dstp3, r1 + cmp/eq r1, r5 + bt .L7 + fail +.L7: + mov.l srcp4, r2 + cmp/eq r2, r6 + bt .L8 + fail +.L8: + mov.l dstp4, r3 + cmp/eq r3, r7 + bt .L9 + fail +.L9: + # verify copied values + mov.w @r0, r0 + mov.w @r1, r1 + cmp/eq r0, r1 + bt .L10 + fail +.L10: + mov.w @r2, r2 + mov.w @r3, r3 + cmp/eq r2, r3 + bt .L11 + fail +.L11: + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + bra movxw_movyw_new + nop + + .align 2 +srcp1: .long src1 +srcp2: .long src2 +srcp3: .long src3 +srcp4: .long src4 +srcp5: .long src5 +srcp6: .long src6 +srcp7: .long src7 +srcp8: .long src8 +srcp9: .long src9 + +dstp1: .long dst1 +dstp2: .long dst2 +dstp3: .long dst3 +dstp4: .long dst4 +dstp5: .long dst5 +dstp6: .long dst6 +dstp7: .long dst7 +dstp8: .long dst8 +dstp9: .long dst9 + +movxw_movyw_new: + set_grs_a5a5 + # load up pointers + mov.l srcp5b, r0 + mov.l dstp5b, r1 + mov.l srcp6b, r2 + mov.l dstp6b, r3 + + # perform moves + movx.w @r0, x1 + movy.w @r2, y1 + movx.w x1, @r1 + movy.w y1, @r3 + + # verify pointers unchanged + mov.l srcp5b, r4 + cmp/eq r0, r4 + bt .L12 + fail + +.L12: + mov.l dstp5b, r5 + cmp/eq r1, r5 + bt .L13 + fail +.L13: + mov.l srcp6b, r6 + cmp/eq r2, r6 + bt .L14 + fail +.L14: + mov.l dstp6b, r7 + cmp/eq r3, r7 + bt .L15 + fail +.L15: + # verify copied values + mov.w @r0, r0 + mov.w @r1, r1 + cmp/eq r0, r1 + bt .L16 + fail +.L16: + mov.w @r2, r2 + mov.w @r3, r3 + cmp/eq r2, r3 + bt .L17 + fail +.L17: + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + mov.l srcp1b, r0 + mov.l dstp1b, r1 + mov.l srcp2b, r2 + mov.l dstp2b, r3 + mov.l srcp1b, r4 + mov.l dstp1b, r5 + mov.l srcp2b, r6 + mov.l dstp2b, r7 + mov #4, r8 + mov #4, r9 + bra .L18 + nop + + .align 2 +srcp1b: .long src1 +srcp2b: .long src2 +srcp3b: .long src3 +srcp4b: .long src4 +srcp5b: .long src5 +srcp6b: .long src6 +srcp7b: .long src7 +srcp8b: .long src8 +srcp9b: .long src9 + +dstp1b: .long dst1 +dstp2b: .long dst2 +dstp3b: .long dst3 +dstp4b: .long dst4 +dstp5b: .long dst5 +dstp6b: .long dst6 +dstp7b: .long dst7 +dstp8b: .long dst8 +dstp9b: .long dst9 + +.L18: + + # movx.w @Ax{}, Dx | nopy +movxwaxdx_nopy: + movx.w @r4,x0 ! .word 0xf004 + movx.w @r4,x1 ! .word 0xf084 + movx.w @r5,x0 ! .word 0xf204 + movx.w @r5,x1 ! .word 0xf284 + movx.w @r4+,x0 ! .word 0xf008 + movx.w @r4+,x1 ! .word 0xf088 + movx.w @r5+,x0 ! .word 0xf208 + movx.w @r5+,x1 ! .word 0xf288 + movx.w @r4+r8,x0 ! .word 0xf00c + movx.w @r4+r8,x1 ! .word 0xf08c + movx.w @r5+r8,x0 ! .word 0xf20c + movx.w @r5+r8,x1 ! .word 0xf28c + # movx.w Da, @Ax{} | nopy +movxwdaax_nopy: + movx.w a0,@r4 ! .word 0xf024 + movx.w a1,@r4 ! .word 0xf0a4 + movx.w a0,@r5 ! .word 0xf224 + movx.w a1,@r5 ! .word 0xf2a4 + movx.w a0,@r4+ ! .word 0xf028 + movx.w a1,@r4+ ! .word 0xf0a8 + movx.w a0,@r5+ ! .word 0xf228 + movx.w a1,@r5+ ! .word 0xf2a8 + movx.w a0,@r4+r8 ! .word 0xf02c + movx.w a1,@r4+r8 ! .word 0xf0ac + movx.w a0,@r5+r8 ! .word 0xf22c + movx.w a1,@r5+r8 ! .word 0xf2ac + # movy.w @Ay{}, Dy | nopx +movywaydy_nopx: + movy.w @r6,y0 ! .word 0xf001 + movy.w @r6,y1 ! .word 0xf041 + movy.w @r7,y0 ! .word 0xf101 + movy.w @r7,y1 ! .word 0xf141 + movy.w @r6+,y0 ! .word 0xf002 + movy.w @r6+,y1 ! .word 0xf042 + movy.w @r7+,y0 ! .word 0xf102 + movy.w @r7+,y1 ! .word 0xf142 + movy.w @r6+r9,y0 ! .word 0xf003 + movy.w @r6+r9,y1 ! .word 0xf043 + movy.w @r7+r9,y0 ! .word 0xf103 + movy.w @r7+r9,y1 ! .word 0xf143 + # movy.w Da, @Ay{} | nopx +movywdaay_nopx: + movy.w a0,@r6 ! .word 0xf011 + movy.w a1,@r6 ! .word 0xf051 + movy.w a0,@r7 ! .word 0xf111 + movy.w a1,@r7 ! .word 0xf151 + movy.w a0,@r6+ ! .word 0xf012 + movy.w a1,@r6+ ! .word 0xf052 + movy.w a0,@r7+ ! .word 0xf112 + movy.w a1,@r7+ ! .word 0xf152 + movy.w a0,@r6+r9 ! .word 0xf013 + movy.w a1,@r6+r9 ! .word 0xf053 + movy.w a0,@r7+r9 ! .word 0xf113 + movy.w a1,@r7+r9 ! .word 0xf153 + # movx {} || movy {} +movx_movy: + movx.w @r4,x0 movy.w @r6,y0 ! .word 0xf005 + movx.w @r4,x0 movy.w @r6,y1 ! .word 0xf045 + movx.w @r4,x1 movy.w @r6,y0 ! .word 0xf085 + movx.w @r4,x1 movy.w @r6,y1 ! .word 0xf0c5 + movx.w @r4,x0 movy.w @r7,y0 ! .word 0xf105 + movx.w @r4,x0 movy.w @r7,y1 ! .word 0xf145 + movx.w @r4,x1 movy.w @r7,y0 ! .word 0xf185 + movx.w @r4,x1 movy.w @r7,y1 ! .word 0xf1c5 + movx.w @r5,x0 movy.w @r6,y0 ! .word 0xf205 + movx.w @r5,x0 movy.w @r6,y1 ! .word 0xf245 + movx.w @r5,x1 movy.w @r6,y0 ! .word 0xf285 + movx.w @r5,x1 movy.w @r6,y1 ! .word 0xf2c5 + movx.w @r5,x0 movy.w @r7,y0 ! .word 0xf305 + movx.w @r5,x0 movy.w @r7,y1 ! .word 0xf345 + movx.w @r5,x1 movy.w @r7,y0 ! .word 0xf385 + movx.w @r5,x1 movy.w @r7,y1 ! .word 0xf3c5 + movx.w @r4,x0 movy.w @r6+,y0 ! .word 0xf006 + movx.w @r4,x0 movy.w @r6+,y1 ! .word 0xf046 + movx.w @r4,x1 movy.w @r6+,y0 ! .word 0xf086 + movx.w @r4,x1 movy.w @r6+,y1 ! .word 0xf0c6 + movx.w @r4,x0 movy.w @r7+,y0 ! .word 0xf106 + movx.w @r4,x0 movy.w @r7+,y1 ! .word 0xf146 + movx.w @r4,x1 movy.w @r7+,y0 ! .word 0xf186 + movx.w @r4,x1 movy.w @r7+,y1 ! .word 0xf1c6 + movx.w @r5,x0 movy.w @r6+,y0 ! .word 0xf206 + movx.w @r5,x0 movy.w @r6+,y1 ! .word 0xf246 + movx.w @r5,x1 movy.w @r6+,y0 ! .word 0xf286 + movx.w @r5,x1 movy.w @r6+,y1 ! .word 0xf2c6 + movx.w @r5,x0 movy.w @r7+,y0 ! .word 0xf306 + movx.w @r5,x0 movy.w @r7+,y1 ! .word 0xf346 + movx.w @r5,x1 movy.w @r7+,y0 ! .word 0xf386 + movx.w @r5,x1 movy.w @r7+,y1 ! .word 0xf3c6 + movx.w @r4,x0 movy.w @r6+r9,y0 ! .word 0xf007 + movx.w @r4,x0 movy.w @r6+r9,y1 ! .word 0xf047 + movx.w @r4,x1 movy.w @r6+r9,y0 ! .word 0xf087 + movx.w @r4,x1 movy.w @r6+r9,y1 ! .word 0xf0c7 + movx.w @r4,x0 movy.w @r7+r9,y0 ! .word 0xf107 + movx.w @r4,x0 movy.w @r7+r9,y1 ! .word 0xf147 + movx.w @r4,x1 movy.w @r7+r9,y0 ! .word 0xf187 + movx.w @r4,x1 movy.w @r7+r9,y1 ! .word 0xf1c7 + movx.w @r5,x0 movy.w @r6+r9,y0 ! .word 0xf207 + movx.w @r5,x0 movy.w @r6+r9,y1 ! .word 0xf247 + movx.w @r5,x1 movy.w @r6+r9,y0 ! .word 0xf287 + movx.w @r5,x1 movy.w @r6+r9,y1 ! .word 0xf2c7 + movx.w @r5,x0 movy.w @r7+r9,y0 ! .word 0xf307 + movx.w @r5,x0 movy.w @r7+r9,y1 ! .word 0xf347 + movx.w @r5,x1 movy.w @r7+r9,y0 ! .word 0xf387 + movx.w @r5,x1 movy.w @r7+r9,y1 ! .word 0xf3c7 + movx.w @r4+,x0 movy.w @r6,y0 ! .word 0xf009 + movx.w @r4+,x0 movy.w @r6,y1 ! .word 0xf049 + movx.w @r4+,x1 movy.w @r6,y0 ! .word 0xf089 + movx.w @r4+,x1 movy.w @r6,y1 ! .word 0xf0c9 + movx.w @r4+,x0 movy.w @r7,y0 ! .word 0xf109 + movx.w @r4+,x0 movy.w @r7,y1 ! .word 0xf149 + movx.w @r4+,x1 movy.w @r7,y0 ! .word 0xf189 + movx.w @r4+,x1 movy.w @r7,y1 ! .word 0xf1c9 + movx.w @r5+,x0 movy.w @r6,y0 ! .word 0xf209 + movx.w @r5+,x0 movy.w @r6,y1 ! .word 0xf249 + movx.w @r5+,x1 movy.w @r6,y0 ! .word 0xf289 + movx.w @r5+,x1 movy.w @r6,y1 ! .word 0xf2c9 + movx.w @r5+,x0 movy.w @r7,y0 ! .word 0xf309 + movx.w @r5+,x0 movy.w @r7,y1 ! .word 0xf349 + movx.w @r5+,x1 movy.w @r7,y0 ! .word 0xf389 + movx.w @r5+,x1 movy.w @r7,y1 ! .word 0xf3c9 + movx.w @r4+,x0 movy.w @r6+,y0 ! .word 0xf00a + movx.w @r4+,x0 movy.w @r6+,y1 ! .word 0xf04a + movx.w @r4+,x1 movy.w @r6+,y0 ! .word 0xf08a + movx.w @r4+,x1 movy.w @r6+,y1 ! .word 0xf0ca + movx.w @r4+,x0 movy.w @r7+,y0 ! .word 0xf10a + movx.w @r4+,x0 movy.w @r7+,y1 ! .word 0xf14a + movx.w @r4+,x1 movy.w @r7+,y0 ! .word 0xf18a + movx.w @r4+,x1 movy.w @r7+,y1 ! .word 0xf1ca + movx.w @r5+,x0 movy.w @r6+,y0 ! .word 0xf20a + movx.w @r5+,x0 movy.w @r6+,y1 ! .word 0xf24a + movx.w @r5+,x1 movy.w @r6+,y0 ! .word 0xf28a + movx.w @r5+,x1 movy.w @r6+,y1 ! .word 0xf2ca + movx.w @r5+,x0 movy.w @r7+,y0 ! .word 0xf30a + movx.w @r5+,x0 movy.w @r7+,y1 ! .word 0xf34a + movx.w @r5+,x1 movy.w @r7+,y0 ! .word 0xf38a + movx.w @r5+,x1 movy.w @r7+,y1 ! .word 0xf3ca + movx.w @r4+,x0 movy.w @r6+r9,y0 ! .word 0xf00b + movx.w @r4+,x0 movy.w @r6+r9,y1 ! .word 0xf04b + movx.w @r4+,x1 movy.w @r6+r9,y0 ! .word 0xf08b + movx.w @r4+,x1 movy.w @r6+r9,y1 ! .word 0xf0cb + movx.w @r4+,x0 movy.w @r7+r9,y0 ! .word 0xf10b + movx.w @r4+,x0 movy.w @r7+r9,y1 ! .word 0xf14b + movx.w @r4+,x1 movy.w @r7+r9,y0 ! .word 0xf18b + movx.w @r4+,x1 movy.w @r7+r9,y1 ! .word 0xf1cb + movx.w @r5+,x0 movy.w @r6+r9,y0 ! .word 0xf20b + movx.w @r5+,x0 movy.w @r6+r9,y1 ! .word 0xf24b + movx.w @r5+,x1 movy.w @r6+r9,y0 ! .word 0xf28b + movx.w @r5+,x1 movy.w @r6+r9,y1 ! .word 0xf2cb + movx.w @r5+,x0 movy.w @r7+r9,y0 ! .word 0xf30b + movx.w @r5+,x0 movy.w @r7+r9,y1 ! .word 0xf34b + movx.w @r5+,x1 movy.w @r7+r9,y0 ! .word 0xf38b + movx.w @r5+,x1 movy.w @r7+r9,y1 ! .word 0xf3cb + movx.w @r4+r8,x0 movy.w @r6,y0 ! .word 0xf00d + movx.w @r4+r8,x0 movy.w @r6,y1 ! .word 0xf04d + movx.w @r4+r8,x1 movy.w @r6,y0 ! .word 0xf08d + movx.w @r4+r8,x1 movy.w @r6,y1 ! .word 0xf0cd + movx.w @r4+r8,x0 movy.w @r7,y0 ! .word 0xf10d + movx.w @r4+r8,x0 movy.w @r7,y1 ! .word 0xf14d + movx.w @r4+r8,x1 movy.w @r7,y0 ! .word 0xf18d + movx.w @r4+r8,x1 movy.w @r7,y1 ! .word 0xf1cd + movx.w @r5+r8,x0 movy.w @r6,y0 ! .word 0xf20d + movx.w @r5+r8,x0 movy.w @r6,y1 ! .word 0xf24d + movx.w @r5+r8,x1 movy.w @r6,y0 ! .word 0xf28d + movx.w @r5+r8,x1 movy.w @r6,y1 ! .word 0xf2cd + movx.w @r5+r8,x0 movy.w @r7,y0 ! .word 0xf30d + movx.w @r5+r8,x0 movy.w @r7,y1 ! .word 0xf34d + movx.w @r5+r8,x1 movy.w @r7,y0 ! .word 0xf38d + movx.w @r5+r8,x1 movy.w @r7,y1 ! .word 0xf3cd + movx.w @r4+r8,x0 movy.w @r6+,y0 ! .word 0xf00e + movx.w @r4+r8,x0 movy.w @r6+,y1 ! .word 0xf04e + movx.w @r4+r8,x1 movy.w @r6+,y0 ! .word 0xf08e + movx.w @r4+r8,x1 movy.w @r6+,y1 ! .word 0xf0ce + movx.w @r4+r8,x0 movy.w @r7+,y0 ! .word 0xf10e + movx.w @r4+r8,x0 movy.w @r7+,y1 ! .word 0xf14e + movx.w @r4+r8,x1 movy.w @r7+,y0 ! .word 0xf18e + movx.w @r4+r8,x1 movy.w @r7+,y1 ! .word 0xf1ce + movx.w @r5+r8,x0 movy.w @r6+,y0 ! .word 0xf20e + movx.w @r5+r8,x0 movy.w @r6+,y1 ! .word 0xf24e + movx.w @r5+r8,x1 movy.w @r6+,y0 ! .word 0xf28e + movx.w @r5+r8,x1 movy.w @r6+,y1 ! .word 0xf2ce + movx.w @r5+r8,x0 movy.w @r7+,y0 ! .word 0xf30e + movx.w @r5+r8,x0 movy.w @r7+,y1 ! .word 0xf34e + movx.w @r5+r8,x1 movy.w @r7+,y0 ! .word 0xf38e + movx.w @r5+r8,x1 movy.w @r7+,y1 ! .word 0xf3ce + movx.w @r4+r8,x0 movy.w @r6+r9,y0 ! .word 0xf00f + movx.w @r4+r8,x0 movy.w @r6+r9,y1 ! .word 0xf04f + movx.w @r4+r8,x1 movy.w @r6+r9,y0 ! .word 0xf08f + movx.w @r4+r8,x1 movy.w @r6+r9,y1 ! .word 0xf0cf + movx.w @r4+r8,x0 movy.w @r7+r9,y0 ! .word 0xf10f + movx.w @r4+r8,x0 movy.w @r7+r9,y1 ! .word 0xf14f + movx.w @r4+r8,x1 movy.w @r7+r9,y0 ! .word 0xf18f + movx.w @r4+r8,x1 movy.w @r7+r9,y1 ! .word 0xf1cf + movx.w @r5+r8,x0 movy.w @r6+r9,y0 ! .word 0xf20f + movx.w @r5+r8,x0 movy.w @r6+r9,y1 ! .word 0xf24f + movx.w @r5+r8,x1 movy.w @r6+r9,y0 ! .word 0xf28f + movx.w @r5+r8,x1 movy.w @r6+r9,y1 ! .word 0xf2cf + movx.w @r5+r8,x0 movy.w @r7+r9,y0 ! .word 0xf30f + movx.w @r5+r8,x0 movy.w @r7+r9,y1 ! .word 0xf34f + movx.w @r5+r8,x1 movy.w @r7+r9,y0 ! .word 0xf38f + movx.w @r5+r8,x1 movy.w @r7+r9,y1 ! .word 0xf3cf + movx.w @r4,x0 movy.w a0,@r6 ! .word 0xf015 + movx.w @r4,x0 movy.w a1,@r6 ! .word 0xf055 + movx.w @r4,x1 movy.w a0,@r6 ! .word 0xf095 + movx.w @r4,x1 movy.w a1,@r6 ! .word 0xf0d5 + movx.w @r4,x0 movy.w a0,@r7 ! .word 0xf115 + movx.w @r4,x0 movy.w a1,@r7 ! .word 0xf155 + movx.w @r4,x1 movy.w a0,@r7 ! .word 0xf195 + movx.w @r4,x1 movy.w a1,@r7 ! .word 0xf1d5 + movx.w @r5,x0 movy.w a0,@r6 ! .word 0xf215 + movx.w @r5,x0 movy.w a1,@r6 ! .word 0xf255 + movx.w @r5,x1 movy.w a0,@r6 ! .word 0xf295 + movx.w @r5,x1 movy.w a1,@r6 ! .word 0xf2d5 + movx.w @r5,x0 movy.w a0,@r7 ! .word 0xf315 + movx.w @r5,x0 movy.w a1,@r7 ! .word 0xf355 + movx.w @r5,x1 movy.w a0,@r7 ! .word 0xf395 + movx.w @r5,x1 movy.w a1,@r7 ! .word 0xf3d5 + movx.w @r4,x0 movy.w a0,@r6+ ! .word 0xf016 + movx.w @r4,x0 movy.w a1,@r6+ ! .word 0xf056 + movx.w @r4,x1 movy.w a0,@r6+ ! .word 0xf096 + movx.w @r4,x1 movy.w a1,@r6+ ! .word 0xf0d6 + movx.w @r4,x0 movy.w a0,@r7+ ! .word 0xf116 + movx.w @r4,x0 movy.w a1,@r7+ ! .word 0xf156 + movx.w @r4,x1 movy.w a0,@r7+ ! .word 0xf196 + movx.w @r4,x1 movy.w a1,@r7+ ! .word 0xf1d6 + movx.w @r5,x0 movy.w a0,@r6+ ! .word 0xf216 + movx.w @r5,x0 movy.w a1,@r6+ ! .word 0xf256 + movx.w @r5,x1 movy.w a0,@r6+ ! .word 0xf296 + movx.w @r5,x1 movy.w a1,@r6+ ! .word 0xf2d6 + movx.w @r5,x0 movy.w a0,@r7+ ! .word 0xf316 + movx.w @r5,x0 movy.w a1,@r7+ ! .word 0xf356 + movx.w @r5,x1 movy.w a0,@r7+ ! .word 0xf396 + movx.w @r5,x1 movy.w a1,@r7+ ! .word 0xf3d6 + movx.w @r4,x0 movy.w a0,@r6+r9 ! .word 0xf017 + movx.w @r4,x0 movy.w a1,@r6+r9 ! .word 0xf057 + movx.w @r4,x1 movy.w a0,@r6+r9 ! .word 0xf097 + movx.w @r4,x1 movy.w a1,@r6+r9 ! .word 0xf0d7 + movx.w @r4,x0 movy.w a0,@r7+r9 ! .word 0xf117 + movx.w @r4,x0 movy.w a1,@r7+r9 ! .word 0xf157 + movx.w @r4,x1 movy.w a0,@r7+r9 ! .word 0xf197 + movx.w @r4,x1 movy.w a1,@r7+r9 ! .word 0xf1d7 + movx.w @r5,x0 movy.w a0,@r6+r9 ! .word 0xf217 + movx.w @r5,x0 movy.w a1,@r6+r9 ! .word 0xf257 + movx.w @r5,x1 movy.w a0,@r6+r9 ! .word 0xf297 + movx.w @r5,x1 movy.w a1,@r6+r9 ! .word 0xf2d7 + movx.w @r5,x0 movy.w a0,@r7+r9 ! .word 0xf317 + movx.w @r5,x0 movy.w a1,@r7+r9 ! .word 0xf357 + movx.w @r5,x1 movy.w a0,@r7+r9 ! .word 0xf397 + movx.w @r5,x1 movy.w a1,@r7+r9 ! .word 0xf3d7 + movx.w @r4+,x0 movy.w a0,@r6 ! .word 0xf019 + movx.w @r4+,x0 movy.w a1,@r6 ! .word 0xf059 + movx.w @r4+,x1 movy.w a0,@r6 ! .word 0xf099 + movx.w @r4+,x1 movy.w a1,@r6 ! .word 0xf0d9 + movx.w @r4+,x0 movy.w a0,@r7 ! .word 0xf119 + movx.w @r4+,x0 movy.w a1,@r7 ! .word 0xf159 + movx.w @r4+,x1 movy.w a0,@r7 ! .word 0xf199 + movx.w @r4+,x1 movy.w a1,@r7 ! .word 0xf1d9 + movx.w @r5+,x0 movy.w a0,@r6 ! .word 0xf219 + movx.w @r5+,x0 movy.w a1,@r6 ! .word 0xf259 + movx.w @r5+,x1 movy.w a0,@r6 ! .word 0xf299 + movx.w @r5+,x1 movy.w a1,@r6 ! .word 0xf2d9 + movx.w @r5+,x0 movy.w a0,@r7 ! .word 0xf319 + movx.w @r5+,x0 movy.w a1,@r7 ! .word 0xf359 + movx.w @r5+,x1 movy.w a0,@r7 ! .word 0xf399 + movx.w @r5+,x1 movy.w a1,@r7 ! .word 0xf3d9 + movx.w @r4+,x0 movy.w a0,@r6+ ! .word 0xf01a + movx.w @r4+,x0 movy.w a1,@r6+ ! .word 0xf05a + movx.w @r4+,x1 movy.w a0,@r6+ ! .word 0xf09a + movx.w @r4+,x1 movy.w a1,@r6+ ! .word 0xf0da + movx.w @r4+,x0 movy.w a0,@r7+ ! .word 0xf11a + movx.w @r4+,x0 movy.w a1,@r7+ ! .word 0xf15a + movx.w @r4+,x1 movy.w a0,@r7+ ! .word 0xf19a + movx.w @r4+,x1 movy.w a1,@r7+ ! .word 0xf1da + movx.w @r5+,x0 movy.w a0,@r6+ ! .word 0xf21a + movx.w @r5+,x0 movy.w a1,@r6+ ! .word 0xf25a + movx.w @r5+,x1 movy.w a0,@r6+ ! .word 0xf29a + movx.w @r5+,x1 movy.w a1,@r6+ ! .word 0xf2da + movx.w @r5+,x0 movy.w a0,@r7+ ! .word 0xf31a + movx.w @r5+,x0 movy.w a1,@r7+ ! .word 0xf35a + movx.w @r5+,x1 movy.w a0,@r7+ ! .word 0xf39a + movx.w @r5+,x1 movy.w a1,@r7+ ! .word 0xf3da + movx.w @r4+,x0 movy.w a0,@r6+r9 ! .word 0xf01b + movx.w @r4+,x0 movy.w a1,@r6+r9 ! .word 0xf05b + movx.w @r4+,x1 movy.w a0,@r6+r9 ! .word 0xf09b + movx.w @r4+,x1 movy.w a1,@r6+r9 ! .word 0xf0db + movx.w @r4+,x0 movy.w a0,@r7+r9 ! .word 0xf11b + movx.w @r4+,x0 movy.w a1,@r7+r9 ! .word 0xf15b + movx.w @r4+,x1 movy.w a0,@r7+r9 ! .word 0xf19b + movx.w @r4+,x1 movy.w a1,@r7+r9 ! .word 0xf1db + movx.w @r5+,x0 movy.w a0,@r6+r9 ! .word 0xf21b + movx.w @r5+,x0 movy.w a1,@r6+r9 ! .word 0xf25b + movx.w @r5+,x1 movy.w a0,@r6+r9 ! .word 0xf29b + movx.w @r5+,x1 movy.w a1,@r6+r9 ! .word 0xf2db + movx.w @r5+,x0 movy.w a0,@r7+r9 ! .word 0xf31b + movx.w @r5+,x0 movy.w a1,@r7+r9 ! .word 0xf35b + movx.w @r5+,x1 movy.w a0,@r7+r9 ! .word 0xf39b + movx.w @r5+,x1 movy.w a1,@r7+r9 ! .word 0xf3db + movx.w @r4+r8,x0 movy.w a0,@r6 ! .word 0xf01d + movx.w @r4+r8,x0 movy.w a1,@r6 ! .word 0xf05d + movx.w @r4+r8,x1 movy.w a0,@r6 ! .word 0xf09d + movx.w @r4+r8,x1 movy.w a1,@r6 ! .word 0xf0dd + movx.w @r4+r8,x0 movy.w a0,@r7 ! .word 0xf11d + movx.w @r4+r8,x0 movy.w a1,@r7 ! .word 0xf15d + movx.w @r4+r8,x1 movy.w a0,@r7 ! .word 0xf19d + movx.w @r4+r8,x1 movy.w a1,@r7 ! .word 0xf1dd + movx.w @r5+r8,x0 movy.w a0,@r6 ! .word 0xf21d + movx.w @r5+r8,x0 movy.w a1,@r6 ! .word 0xf25d + movx.w @r5+r8,x1 movy.w a0,@r6 ! .word 0xf29d + movx.w @r5+r8,x1 movy.w a1,@r6 ! .word 0xf2dd + movx.w @r5+r8,x0 movy.w a0,@r7 ! .word 0xf31d + movx.w @r5+r8,x0 movy.w a1,@r7 ! .word 0xf35d + movx.w @r5+r8,x1 movy.w a0,@r7 ! .word 0xf39d + movx.w @r5+r8,x1 movy.w a1,@r7 ! .word 0xf3dd + movx.w @r4+r8,x0 movy.w a0,@r6+ ! .word 0xf01e + movx.w @r4+r8,x0 movy.w a1,@r6+ ! .word 0xf05e + movx.w @r4+r8,x1 movy.w a0,@r6+ ! .word 0xf09e + movx.w @r4+r8,x1 movy.w a1,@r6+ ! .word 0xf0de + movx.w @r4+r8,x0 movy.w a0,@r7+ ! .word 0xf11e + movx.w @r4+r8,x0 movy.w a1,@r7+ ! .word 0xf15e + movx.w @r4+r8,x1 movy.w a0,@r7+ ! .word 0xf19e + movx.w @r4+r8,x1 movy.w a1,@r7+ ! .word 0xf1de + movx.w @r5+r8,x0 movy.w a0,@r6+ ! .word 0xf21e + movx.w @r5+r8,x0 movy.w a1,@r6+ ! .word 0xf25e + movx.w @r5+r8,x1 movy.w a0,@r6+ ! .word 0xf29e + movx.w @r5+r8,x1 movy.w a1,@r6+ ! .word 0xf2de + movx.w @r5+r8,x0 movy.w a0,@r7+ ! .word 0xf31e + movx.w @r5+r8,x0 movy.w a1,@r7+ ! .word 0xf35e + movx.w @r5+r8,x1 movy.w a0,@r7+ ! .word 0xf39e + movx.w @r5+r8,x1 movy.w a1,@r7+ ! .word 0xf3de + movx.w @r4+r8,x0 movy.w a0,@r6+r9 ! .word 0xf01f + movx.w @r4+r8,x0 movy.w a1,@r6+r9 ! .word 0xf05f + movx.w @r4+r8,x1 movy.w a0,@r6+r9 ! .word 0xf09f + movx.w @r4+r8,x1 movy.w a1,@r6+r9 ! .word 0xf0df + movx.w @r4+r8,x0 movy.w a0,@r7+r9 ! .word 0xf11f + movx.w @r4+r8,x0 movy.w a1,@r7+r9 ! .word 0xf15f + movx.w @r4+r8,x1 movy.w a0,@r7+r9 ! .word 0xf19f + movx.w @r4+r8,x1 movy.w a1,@r7+r9 ! .word 0xf1df + movx.w @r5+r8,x0 movy.w a0,@r6+r9 ! .word 0xf21f + movx.w @r5+r8,x0 movy.w a1,@r6+r9 ! .word 0xf25f + movx.w @r5+r8,x1 movy.w a0,@r6+r9 ! .word 0xf29f + movx.w @r5+r8,x1 movy.w a1,@r6+r9 ! .word 0xf2df + movx.w @r5+r8,x0 movy.w a0,@r7+r9 ! .word 0xf31f + movx.w @r5+r8,x0 movy.w a1,@r7+r9 ! .word 0xf35f + movx.w @r5+r8,x1 movy.w a0,@r7+r9 ! .word 0xf39f + movx.w @r5+r8,x1 movy.w a1,@r7+r9 ! .word 0xf3df + movx.w a0,@r4 movy.w @r6,y0 ! .word 0xf025 + movx.w a0,@r4 movy.w @r6,y1 ! .word 0xf065 + movx.w a1,@r4 movy.w @r6,y0 ! .word 0xf0a5 + movx.w a1,@r4 movy.w @r6,y1 ! .word 0xf0e5 + movx.w a0,@r4 movy.w @r7,y0 ! .word 0xf125 + movx.w a0,@r4 movy.w @r7,y1 ! .word 0xf165 + movx.w a1,@r4 movy.w @r7,y0 ! .word 0xf1a5 + movx.w a1,@r4 movy.w @r7,y1 ! .word 0xf1e5 + movx.w a0,@r5 movy.w @r6,y0 ! .word 0xf225 + movx.w a0,@r5 movy.w @r6,y1 ! .word 0xf265 + movx.w a1,@r5 movy.w @r6,y0 ! .word 0xf2a5 + movx.w a1,@r5 movy.w @r6,y1 ! .word 0xf2e5 + movx.w a0,@r5 movy.w @r7,y0 ! .word 0xf325 + movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf365 + movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf3a5 + movx.w a1,@r5 movy.w @r7,y1 ! .word 0xf3e5 + movx.w a0,@r4 movy.w @r6+,y0 ! .word 0xf026 + movx.w a0,@r4 movy.w @r6+,y1 ! .word 0xf066 + movx.w a1,@r4 movy.w @r6+,y0 ! .word 0xf0a6 + movx.w a1,@r4 movy.w @r6+,y1 ! .word 0xf0e6 + movx.w a0,@r4 movy.w @r7+,y0 ! .word 0xf126 + movx.w a0,@r4 movy.w @r7+,y1 ! .word 0xf166 + movx.w a1,@r4 movy.w @r7+,y0 ! .word 0xf1a6 + movx.w a1,@r4 movy.w @r7+,y1 ! .word 0xf1e6 + movx.w a0,@r5 movy.w @r6+,y0 ! .word 0xf226 + movx.w a0,@r5 movy.w @r6+,y1 ! .word 0xf266 + movx.w a1,@r5 movy.w @r6+,y0 ! .word 0xf2a6 + movx.w a1,@r5 movy.w @r6+,y1 ! .word 0xf2e6 + movx.w a0,@r5 movy.w @r7+,y0 ! .word 0xf326 + movx.w a0,@r5 movy.w @r7+,y1 ! .word 0xf366 + movx.w a1,@r5 movy.w @r7+,y0 ! .word 0xf3a6 + movx.w a1,@r5 movy.w @r7+,y1 ! .word 0xf3e6 + movx.w a0,@r4 movy.w @r6+r9,y0 ! .word 0xf027 + movx.w a0,@r4 movy.w @r6+r9,y1 ! .word 0xf067 + movx.w a1,@r4 movy.w @r6+r9,y0 ! .word 0xf0a7 + movx.w a1,@r4 movy.w @r6+r9,y1 ! .word 0xf0e7 + movx.w a0,@r4 movy.w @r7+r9,y0 ! .word 0xf127 + movx.w a0,@r4 movy.w @r7+r9,y1 ! .word 0xf167 + movx.w a1,@r4 movy.w @r7+r9,y0 ! .word 0xf1a7 + movx.w a1,@r4 movy.w @r7+r9,y1 ! .word 0xf1e7 + movx.w a0,@r5 movy.w @r6+r9,y0 ! .word 0xf227 + movx.w a0,@r5 movy.w @r6+r9,y1 ! .word 0xf267 + movx.w a1,@r5 movy.w @r6+r9,y0 ! .word 0xf2a7 + movx.w a1,@r5 movy.w @r6+r9,y1 ! .word 0xf2e7 + movx.w a0,@r5 movy.w @r7+r9,y0 ! .word 0xf327 + movx.w a0,@r5 movy.w @r7+r9,y1 ! .word 0xf367 + movx.w a1,@r5 movy.w @r7+r9,y0 ! .word 0xf3a7 + movx.w a1,@r5 movy.w @r7+r9,y1 ! .word 0xf3e7 + movx.w a0,@r4+ movy.w @r6,y0 ! .word 0xf029 + movx.w a0,@r4+ movy.w @r6,y1 ! .word 0xf069 + movx.w a1,@r4+ movy.w @r6,y0 ! .word 0xf0a9 + movx.w a1,@r4+ movy.w @r6,y1 ! .word 0xf0e9 + movx.w a0,@r4+ movy.w @r7,y0 ! .word 0xf129 + movx.w a0,@r4+ movy.w @r7,y1 ! .word 0xf169 + movx.w a1,@r4+ movy.w @r7,y0 ! .word 0xf1a9 + movx.w a1,@r4+ movy.w @r7,y1 ! .word 0xf1e9 + movx.w a0,@r5+ movy.w @r6,y0 ! .word 0xf229 + movx.w a0,@r5+ movy.w @r6,y1 ! .word 0xf269 + movx.w a1,@r5+ movy.w @r6,y0 ! .word 0xf2a9 + movx.w a1,@r5+ movy.w @r6,y1 ! .word 0xf2e9 + movx.w a0,@r5+ movy.w @r7,y0 ! .word 0xf329 + movx.w a0,@r5+ movy.w @r7,y1 ! .word 0xf369 + movx.w a1,@r5+ movy.w @r7,y0 ! .word 0xf3a9 + movx.w a1,@r5+ movy.w @r7,y1 ! .word 0xf3e9 + movx.w a0,@r4+ movy.w @r6+,y0 ! .word 0xf02a + movx.w a0,@r4+ movy.w @r6+,y1 ! .word 0xf06a + movx.w a1,@r4+ movy.w @r6+,y0 ! .word 0xf0aa + movx.w a1,@r4+ movy.w @r6+,y1 ! .word 0xf0ea + movx.w a0,@r4+ movy.w @r7+,y0 ! .word 0xf12a + movx.w a0,@r4+ movy.w @r7+,y1 ! .word 0xf16a + movx.w a1,@r4+ movy.w @r7+,y0 ! .word 0xf1aa + movx.w a1,@r4+ movy.w @r7+,y1 ! .word 0xf1ea + movx.w a0,@r5+ movy.w @r6+,y0 ! .word 0xf22a + movx.w a0,@r5+ movy.w @r6+,y1 ! .word 0xf26a + movx.w a1,@r5+ movy.w @r6+,y0 ! .word 0xf2aa + movx.w a1,@r5+ movy.w @r6+,y1 ! .word 0xf2ea + movx.w a0,@r5+ movy.w @r7+,y0 ! .word 0xf32a + movx.w a0,@r5+ movy.w @r7+,y1 ! .word 0xf36a + movx.w a1,@r5+ movy.w @r7+,y0 ! .word 0xf3aa + movx.w a1,@r5+ movy.w @r7+,y1 ! .word 0xf3ea + movx.w a0,@r4+ movy.w @r6+r9,y0 ! .word 0xf02b + movx.w a0,@r4+ movy.w @r6+r9,y1 ! .word 0xf06b + movx.w a1,@r4+ movy.w @r6+r9,y0 ! .word 0xf0ab + movx.w a1,@r4+ movy.w @r6+r9,y1 ! .word 0xf0eb + movx.w a0,@r4+ movy.w @r7+r9,y0 ! .word 0xf12b + movx.w a0,@r4+ movy.w @r7+r9,y1 ! .word 0xf16b + movx.w a1,@r4+ movy.w @r7+r9,y0 ! .word 0xf1ab + movx.w a1,@r4+ movy.w @r7+r9,y1 ! .word 0xf1eb + movx.w a0,@r5+ movy.w @r6+r9,y0 ! .word 0xf22b + movx.w a0,@r5+ movy.w @r6+r9,y1 ! .word 0xf26b + movx.w a1,@r5+ movy.w @r6+r9,y0 ! .word 0xf2ab + movx.w a1,@r5+ movy.w @r6+r9,y1 ! .word 0xf2eb + movx.w a0,@r5+ movy.w @r7+r9,y0 ! .word 0xf32b + movx.w a0,@r5+ movy.w @r7+r9,y1 ! .word 0xf36b + movx.w a1,@r5+ movy.w @r7+r9,y0 ! .word 0xf3ab + movx.w a1,@r5+ movy.w @r7+r9,y1 ! .word 0xf3eb + movx.w a0,@r4+r8 movy.w @r6,y0 ! .word 0xf02d + movx.w a0,@r4+r8 movy.w @r6,y1 ! .word 0xf06d + movx.w a1,@r4+r8 movy.w @r6,y0 ! .word 0xf0ad + movx.w a1,@r4+r8 movy.w @r6,y1 ! .word 0xf0ed + movx.w a0,@r4+r8 movy.w @r7,y0 ! .word 0xf12d + movx.w a0,@r4+r8 movy.w @r7,y1 ! .word 0xf16d + movx.w a1,@r4+r8 movy.w @r7,y0 ! .word 0xf1ad + movx.w a1,@r4+r8 movy.w @r7,y1 ! .word 0xf1ed + movx.w a0,@r5+r8 movy.w @r6,y0 ! .word 0xf22d + movx.w a0,@r5+r8 movy.w @r6,y1 ! .word 0xf26d + movx.w a1,@r5+r8 movy.w @r6,y0 ! .word 0xf2ad + movx.w a1,@r5+r8 movy.w @r6,y1 ! .word 0xf2ed + movx.w a0,@r5+r8 movy.w @r7,y0 ! .word 0xf32d + movx.w a0,@r5+r8 movy.w @r7,y1 ! .word 0xf36d + movx.w a1,@r5+r8 movy.w @r7,y0 ! .word 0xf3ad + movx.w a1,@r5+r8 movy.w @r7,y1 ! .word 0xf3ed + movx.w a0,@r4+r8 movy.w @r6+,y0 ! .word 0xf02e + movx.w a0,@r4+r8 movy.w @r6+,y1 ! .word 0xf06e + movx.w a1,@r4+r8 movy.w @r6+,y0 ! .word 0xf0ae + movx.w a1,@r4+r8 movy.w @r6+,y1 ! .word 0xf0ee + movx.w a0,@r4+r8 movy.w @r7+,y0 ! .word 0xf12e + movx.w a0,@r4+r8 movy.w @r7+,y1 ! .word 0xf16e + movx.w a1,@r4+r8 movy.w @r7+,y0 ! .word 0xf1ae + movx.w a1,@r4+r8 movy.w @r7+,y1 ! .word 0xf1ee + movx.w a0,@r5+r8 movy.w @r6+,y0 ! .word 0xf22e + movx.w a0,@r5+r8 movy.w @r6+,y1 ! .word 0xf26e + movx.w a1,@r5+r8 movy.w @r6+,y0 ! .word 0xf2ae + movx.w a1,@r5+r8 movy.w @r6+,y1 ! .word 0xf2ee + movx.w a0,@r5+r8 movy.w @r7+,y0 ! .word 0xf32e + movx.w a0,@r5+r8 movy.w @r7+,y1 ! .word 0xf36e + movx.w a1,@r5+r8 movy.w @r7+,y0 ! .word 0xf3ae + movx.w a1,@r5+r8 movy.w @r7+,y1 ! .word 0xf3ee + movx.w a0,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf02f + movx.w a0,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf06f + movx.w a1,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf0af + movx.w a1,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf0ef + movx.w a0,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf12f + movx.w a0,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf16f + movx.w a1,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf1af + movx.w a1,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf1ef + movx.w a0,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf22f + movx.w a0,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf26f + movx.w a1,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf2af + movx.w a1,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf2ef + movx.w a0,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf32f + movx.w a0,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf36f + movx.w a1,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf3af + movx.w a1,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf3ef + +movxwaxydxy: + movx.w @r4,x0 ! + movx.w @r4,y0 ! + movx.w @r4,x1 ! + movx.w @r4,y1 ! + movx.w @r0,x0 ! + movx.w @r0,y0 ! + movx.w @r0,x1 ! + movx.w @r0,y1 ! + movx.w @r5,x0 ! + movx.w @r5,y0 ! + movx.w @r5,x1 ! + movx.w @r5,y1 ! + movx.w @r1,x0 ! + movx.w @r1,y0 ! + movx.w @r1,x1 ! + movx.w @r1,y1 ! + movx.w @r4+,x0 ! + movx.w @r4+,y0 ! + movx.w @r4+,x1 ! + movx.w @r4+,y1 ! + movx.w @r0+,x0 ! + movx.w @r0+,y0 ! + movx.w @r0+,x1 ! + movx.w @r0+,y1 ! + movx.w @r5+,x0 ! + movx.w @r5+,y0 ! + movx.w @r5+,x1 ! + movx.w @r5+,y1 ! + movx.w @r1+,x0 ! + movx.w @r1+,y0 ! + movx.w @r1+,x1 ! + movx.w @r1+,y1 ! + movx.w @r4+r8,x0 ! + movx.w @r4+r8,y0 ! + movx.w @r4+r8,x1 ! + movx.w @r4+r8,y1 ! + movx.w @r0+r8,x0 ! + movx.w @r0+r8,y0 ! + movx.w @r0+r8,x1 ! + movx.w @r0+r8,y1 ! + movx.w @r5+r8,x0 ! + movx.w @r5+r8,y0 ! + movx.w @r5+r8,x1 ! + movx.w @r5+r8,y1 ! + movx.w @r1+r8,x0 ! + movx.w @r1+r8,y0 ! + movx.w @r1+r8,x1 ! + movx.w @r1+r8,y1 ! + +movxwdaxaxy: ! + movx.w a0,@r4 ! + movx.w x0,@r4 ! + movx.w a1,@r4 ! + movx.w x1,@r4 ! + movx.w a0,@r0 ! + movx.w x0,@r0 ! + movx.w a1,@r0 ! + movx.w x1,@r0 ! + movx.w a0,@r5 ! + movx.w x0,@r5 ! + movx.w a1,@r5 ! + movx.w x1,@r5 ! + movx.w a0,@r1 ! + movx.w x0,@r1 ! + movx.w a1,@r1 ! + movx.w x1,@r1 ! + movx.w a0,@r4+ ! + movx.w x0,@r4+ ! + movx.w a1,@r4+ ! + movx.w x1,@r4+ ! + movx.w a0,@r0+ ! + movx.w x0,@r0+ ! + movx.w a1,@r0+ ! + movx.w x1,@r0+ ! + movx.w a0,@r5+ ! + movx.w x0,@r5+ ! + movx.w a1,@r5+ ! + movx.w x1,@r5+ ! + movx.w a0,@r1+ ! + movx.w x0,@r1+ ! + movx.w a1,@r1+ ! + movx.w x1,@r1+ ! + movx.w a0,@r4+r8 ! + movx.w x0,@r4+r8 ! + movx.w a1,@r4+r8 ! + movx.w x1,@r4+r8 ! + movx.w a0,@r0+r8 ! + movx.w x0,@r0+r8 ! + movx.w a1,@r0+r8 ! + movx.w x1,@r0+r8 ! + movx.w a0,@r5+r8 ! + movx.w x0,@r5+r8 ! + movx.w a1,@r5+r8 ! + movx.w x1,@r5+r8 ! + movx.w a0,@r1+r8 ! + movx.w x0,@r1+r8 ! + movx.w a1,@r1+r8 ! + movx.w x1,@r1+r8 ! + +movywayxdyx: ! + movy.w @r6,y0 ! + movy.w @r6,y1 ! + movy.w @r6,x0 ! + movy.w @r6,x1 ! + movy.w @r7,y0 ! + movy.w @r7,y1 ! + movy.w @r7,x0 ! + movy.w @r7,x1 ! + movy.w @r2,y0 ! + movy.w @r2,y1 ! + movy.w @r2,x0 ! + movy.w @r2,x1 ! + movy.w @r3,y0 ! + movy.w @r3,y1 ! + movy.w @r3,x0 ! + movy.w @r3,x1 ! + movy.w @r6+,y0 ! + movy.w @r6+,y1 ! + movy.w @r6+,x0 ! + movy.w @r6+,x1 ! + movy.w @r7+,y0 ! + movy.w @r7+,y1 ! + movy.w @r7+,x0 ! + movy.w @r7+,x1 ! + movy.w @r2+,y0 ! + movy.w @r2+,y1 ! + movy.w @r2+,x0 ! + movy.w @r2+,x1 ! + movy.w @r3+,y0 ! + movy.w @r3+,y1 ! + movy.w @r3+,x0 ! + movy.w @r3+,x1 ! + movy.w @r6+r9,y0 ! + movy.w @r6+r9,y1 ! + movy.w @r6+r9,x0 ! + movy.w @r6+r9,x1 ! + movy.w @r7+r9,y0 ! + movy.w @r7+r9,y1 ! + movy.w @r7+r9,x0 ! + movy.w @r7+r9,x1 ! + movy.w @r2+r9,y0 ! + movy.w @r2+r9,y1 ! + movy.w @r2+r9,x0 ! + movy.w @r2+r9,x1 ! + movy.w @r3+r9,y0 ! + movy.w @r3+r9,y1 ! + movy.w @r3+r9,x0 ! + movy.w @r3+r9,x1 ! + +movywdayayx: + movy.w a0,@r6 + movy.w a1,@r6 + movy.w y0,@r6 + movy.w y1,@r6 + movy.w a0,@r7 + movy.w a1,@r7 + movy.w y0,@r7 + movy.w y1,@r7 + movy.w a0,@r2 + movy.w a1,@r2 + movy.w y0,@r2 + movy.w y1,@r2 + movy.w a0,@r3 + movy.w a1,@r3 + movy.w y0,@r3 + movy.w y1,@r3 + movy.w a0,@r6+ + movy.w a1,@r6+ + movy.w y0,@r6+ + movy.w y1,@r6+ + movy.w a0,@r7+ + movy.w a1,@r7+ + movy.w y0,@r7+ + movy.w y1,@r7+ + movy.w a0,@r2+ + movy.w a1,@r2+ + movy.w y0,@r2+ + movy.w y1,@r2+ + movy.w a0,@r3+ + movy.w a1,@r3+ + movy.w y0,@r3+ + movy.w y1,@r3+ + movy.w a0,@r6+r9 + movy.w a1,@r6+r9 + movy.w y0,@r6+r9 + movy.w y1,@r6+r9 + movy.w a0,@r7+r9 + movy.w a1,@r7+r9 + movy.w y0,@r7+r9 + movy.w y1,@r7+r9 + movy.w a0,@r2+r9 + movy.w a1,@r2+r9 + movy.w y0,@r2+r9 + movy.w y1,@r2+r9 + movy.w a0,@r3+r9 + movy.w a1,@r3+r9 + movy.w y0,@r3+r9 + movy.w y1,@r3+r9 + + mov r4, r0 + mov r4, r1 + mov r4, r2 + mov r4, r3 + mov r4, r5 + mov r4, r6 + mov r5, r7 + +movxlaxydxy: + movx.l @r4,x0 + movx.l @r4,y0 + movx.l @r4,x1 + movx.l @r4,y1 + movx.l @r0,x0 + movx.l @r0,y0 + movx.l @r0,x1 + movx.l @r0,y1 + movx.l @r5,x0 + movx.l @r5,y0 + movx.l @r5,x1 + movx.l @r5,y1 + movx.l @r1,x0 + movx.l @r1,y0 + movx.l @r1,x1 + movx.l @r1,y1 + movx.l @r4+,x0 + movx.l @r4+,y0 + movx.l @r4+,x1 + movx.l @r4+,y1 + movx.l @r0+,x0 + movx.l @r0+,y0 + movx.l @r0+,x1 + movx.l @r0+,y1 + movx.l @r5+,x0 + movx.l @r5+,y0 + movx.l @r5+,x1 + movx.l @r5+,y1 + movx.l @r1+,x0 + movx.l @r1+,y0 + movx.l @r1+,x1 + movx.l @r1+,y1 + movx.l @r4+r8,x0 + movx.l @r4+r8,y0 + movx.l @r4+r8,x1 + movx.l @r4+r8,y1 + movx.l @r0+r8,x0 + movx.l @r0+r8,y0 + movx.l @r0+r8,x1 + movx.l @r0+r8,y1 + movx.l @r5+r8,x0 + movx.l @r5+r8,y0 + movx.l @r5+r8,x1 + movx.l @r5+r8,y1 + movx.l @r1+r8,x0 + movx.l @r1+r8,y0 + movx.l @r1+r8,x1 + movx.l @r1+r8,y1 + +movxldaxaxy: + movx.l a0,@r4 + movx.l x0,@r4 + movx.l a1,@r4 + movx.l x1,@r4 + movx.l a0,@r0 + movx.l x0,@r0 + movx.l a1,@r0 + movx.l x1,@r0 + movx.l a0,@r5 + movx.l x0,@r5 + movx.l a1,@r5 + movx.l x1,@r5 + movx.l a0,@r1 + movx.l x0,@r1 + movx.l a1,@r1 + movx.l x1,@r1 + movx.l a0,@r4+ + movx.l x0,@r4+ + movx.l a1,@r4+ + movx.l x1,@r4+ + movx.l a0,@r0+ + movx.l x0,@r0+ + movx.l a1,@r0+ + movx.l x1,@r0+ + movx.l a0,@r5+ + movx.l x0,@r5+ + movx.l a1,@r5+ + movx.l x1,@r5+ + movx.l a0,@r1+ + movx.l x0,@r1+ + movx.l a1,@r1+ + movx.l x1,@r1+ + movx.l a0,@r4+r8 + movx.l x0,@r4+r8 + movx.l a1,@r4+r8 + movx.l x1,@r4+r8 + movx.l a0,@r0+r8 + movx.l x0,@r0+r8 + movx.l a1,@r0+r8 + movx.l x1,@r0+r8 + movx.l a0,@r5+r8 + movx.l x0,@r5+r8 + movx.l a1,@r5+r8 + movx.l x1,@r5+r8 + movx.l a0,@r1+r8 + movx.l x0,@r1+r8 + movx.l a1,@r1+r8 + movx.l x1,@r1+r8 + +movylayxdyx: + movy.l @r6,y0 + movy.l @r6,y1 + movy.l @r6,x0 + movy.l @r6,x1 + movy.l @r7,y0 + movy.l @r7,y1 + movy.l @r7,x0 + movy.l @r7,x1 + movy.l @r2,y0 + movy.l @r2,y1 + movy.l @r2,x0 + movy.l @r2,x1 + movy.l @r3,y0 + movy.l @r3,y1 + movy.l @r3,x0 + movy.l @r3,x1 + movy.l @r6+,y0 + movy.l @r6+,y1 + movy.l @r6+,x0 + movy.l @r6+,x1 + movy.l @r7+,y0 + movy.l @r7+,y1 + movy.l @r7+,x0 + movy.l @r7+,x1 + movy.l @r2+,y0 + movy.l @r2+,y1 + movy.l @r2+,x0 + movy.l @r2+,x1 + movy.l @r3+,y0 + movy.l @r3+,y1 + movy.l @r3+,x0 + movy.l @r3+,x1 + movy.l @r6+r9,y0 + movy.l @r6+r9,y1 + movy.l @r6+r9,x0 + movy.l @r6+r9,x1 + movy.l @r7+r9,y0 + movy.l @r7+r9,y1 + movy.l @r7+r9,x0 + movy.l @r7+r9,x1 + movy.l @r2+r9,y0 + movy.l @r2+r9,y1 + movy.l @r2+r9,x0 + movy.l @r2+r9,x1 + movy.l @r3+r9,y0 + movy.l @r3+r9,y1 + movy.l @r3+r9,x0 + movy.l @r3+r9,x1 + +movyldayayx: + movy.l a0,@r6 + movy.l a1,@r6 + movy.l y0,@r6 + movy.l y1,@r6 + movy.l a0,@r7 + movy.l a1,@r7 + movy.l y0,@r7 + movy.l y1,@r7 + movy.l a0,@r2 + movy.l a1,@r2 + movy.l y0,@r2 + movy.l y1,@r2 + movy.l a0,@r3 + movy.l a1,@r3 + movy.l y0,@r3 + movy.l y1,@r3 + movy.l a0,@r6+ + movy.l a1,@r6+ + movy.l y0,@r6+ + movy.l y1,@r6+ + movy.l a0,@r7+ + movy.l a1,@r7+ + movy.l y0,@r7+ + movy.l y1,@r7+ + movy.l a0,@r2+ + movy.l a1,@r2+ + movy.l y0,@r2+ + movy.l y1,@r2+ + movy.l a0,@r3+ + movy.l a1,@r3+ + movy.l y0,@r3+ + movy.l y1,@r3+ + movy.l a0,@r6+r9 + movy.l a1,@r6+r9 + movy.l y0,@r6+r9 + movy.l y1,@r6+r9 + movy.l a0,@r7+r9 + movy.l a1,@r7+r9 + movy.l y0,@r7+r9 + movy.l y1,@r7+r9 + movy.l a0,@r2+r9 + movy.l a1,@r2+r9 + movy.l y0,@r2+r9 + movy.l y1,@r2+r9 + movy.l a0,@r3+r9 + movy.l a1,@r3+r9 + movy.l y0,@r3+r9 + movy.l y1,@r3+r9 + + pass + exit 0 diff --git a/sim/testsuite/sh/mulr.s b/sim/testsuite/sh/mulr.s new file mode 100644 index 0000000..1e755ab --- /dev/null +++ b/sim/testsuite/sh/mulr.s @@ -0,0 +1,162 @@ +# sh testcase for mulr +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +mulr_1: ! multiply by one + set_grs_a5a5 + mov #1, r0 + mulr r0, r1 + assertreg0 1 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_2: ! multiply by two + set_grs_a5a5 + mov #2, r0 + mov #12, r1 + mulr r0, r1 + assertreg0 2 + assertreg 24, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_3: ! multiply five by five + set_grs_a5a5 + mov #5, r0 + mov #5, r1 + mulr r0, r1 + assertreg0 5 + assertreg 25, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + +mulr_4: ! multiply 127 by 127 + set_grs_a5a5 + mov #127, r0 + mov #127, r1 + mulr r0, r1 + assertreg0 127 + assertreg 0x3f01, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_5: ! multiply -1 by -1 + set_grs_a5a5 + mov #-1, r0 + mov #-1, r1 + mulr r0, r1 + assertreg0 -1 + assertreg 1, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_6: ! multiply 46340 by 46340 + set_grs_a5a5 + movi20 #46340, r0 + movi20 #46340, r1 + mulr r0, r1 + assertreg0 46340 + assertreg 0x7ffea810, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_7: ! multiply 7ffff by 7ffff (overflow) + set_grs_a5a5 + movi20 #0x7ffff, r0 + movi20 #0x7ffff, r1 + mulr r0, r1 + assertreg0 0x7ffff + assertreg 0xfff00001, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + + pass + + exit 0 + + \ No newline at end of file diff --git a/sim/testsuite/sh/pabs.s b/sim/testsuite/sh/pabs.s new file mode 100644 index 0000000..6a9e4f2 --- /dev/null +++ b/sim/testsuite/sh/pabs.s @@ -0,0 +1,54 @@ +# sh testcase for pabs +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + # FIXME: opcode table ambiguity in ignored bits 4-7. + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pabs x0, x1 + pabs y0, y1 + assert_sreg 0x5a5a5a5b, x1 + assert_sreg 0x5a5a5a5b, y1 + pabs x1, x0 + pabs y1, y0 + assert_sreg 0x5a5a5a5b, x0 + assert_sreg 0x5a5a5a5b, y0 + + set_dcfalse + dct pabs a0, a0 + dct pabs m0, m0 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, m0 + set_dctrue + dct pabs a0, a0 + dct pabs m0, m0 + assert_sreg 0x5a5a5a5b, a0 + assert_sreg2 0x5a5a5a5b, m0 + + set_dctrue + dcf pabs a1, a1 + dcf pabs m1, m1 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf pabs a1, a1 + dcf pabs m1, m1 + assert_sreg2 0x5a5a5a5b, a1 + assert_sreg2 0x5a5a5a5b, m1 + + test_grs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sh/padd.s b/sim/testsuite/sh/padd.s new file mode 100644 index 0000000..072935d --- /dev/null +++ b/sim/testsuite/sh/padd.s @@ -0,0 +1,54 @@ +# sh testcase for padd +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + padd x0, y0, a0 + assert_sreg 0x4b4b4b4a, a0 + + # 2 + 2 = 4 + mov #2, r0 + lds r0, x0 + lds r0, y0 + padd x0, y0, a0 + assert_sreg 4, a0 + + set_dcfalse + dct padd x0, y0, a1 + assert_sreg2 0xa5a5a5a5, a1 + set_dctrue + dct padd x0, y0, a1 + assert_sreg2 4, a1 + + set_dctrue + dcf padd x0, y0, m1 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf padd x0, y0, m1 + assert_sreg2 4, m1 + + # padd / pmuls + + padd x0, y0, y0 pmuls x1, y1, m1 + assert_sreg 4, y0 + assert_sreg2 0x3fc838b2, m1 ! (int) 0xa5a5 x (int) 0xa5a5 x 2 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + + pass + exit 0 diff --git a/sim/testsuite/sh/paddc.s b/sim/testsuite/sh/paddc.s new file mode 100644 index 0000000..0dd3b67 --- /dev/null +++ b/sim/testsuite/sh/paddc.s @@ -0,0 +1,39 @@ +# sh testcase for paddc +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + # 2 + 2 = 4 + set_dcfalse + mov #2, r0 + lds r0, x0 + lds r0, y0 + paddc x0, y0, a0 + assert_sreg 4, a0 + + # 2 + 2 + carry = 5 + set_dctrue + paddc x0, y0, a1 + assert_sreg2 5, a1 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sh/pand.s b/sim/testsuite/sh/pand.s new file mode 100644 index 0000000..cddf058 --- /dev/null +++ b/sim/testsuite/sh/pand.s @@ -0,0 +1,48 @@ +# sh testcase for pand +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pand x0, y0, a0 + assert_sreg 0xa5a50000, a0 + + # 0xa5a5a5a5 & 0x5a5a5a5a == 0 + set_greg 0x5a5a5a5a r0 + lds r0, x0 + pand x0, y0, a0 + assert_sreg 0, a0 + + set_dcfalse + dct pand x0, y0, m0 + assert_sreg2 0xa5a5a5a5, m0 + set_dctrue + dct pand x0, y0, m0 + assert_sreg2 0, m0 + + set_dctrue + dcf pand x0, y0, m1 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf pand x0, y0, m1 + assert_sreg2 0, m1 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, a1 + + pass + exit 0 diff --git a/sim/testsuite/sh/pass.s b/sim/testsuite/sh/pass.s new file mode 100644 index 0000000..cc3bbcc --- /dev/null +++ b/sim/testsuite/sh/pass.s @@ -0,0 +1,14 @@ +# sh testcase, pass +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + test_grs_a5a5 + pass + + exit 0 + diff --git a/sim/testsuite/sh/pclr.s b/sim/testsuite/sh/pclr.s new file mode 100644 index 0000000..c396f83 --- /dev/null +++ b/sim/testsuite/sh/pclr.s @@ -0,0 +1,65 @@ +# sh testcase for pclr +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + # FIXME: opcode table ambiguity in ignored bits 4-7. + + .include "testutils.inc" + + start +pclr_cc: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + assert_sreg 0xa5a5a5a5, x0 + pclr x0 + assert_sreg 0, x0 + + set_dcfalse + dct pclr x1 + assert_sreg 0xa5a5a5a5, x1 + set_dctrue + dct pclr x1 + assert_sreg 0, x1 + + set_dctrue + dcf pclr y0 + assert_sreg 0xa5a5a5a5, y0 + set_dcfalse + dcf pclr y0 + assert_sreg 0, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pclr_pmuls: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pclr x0 pmuls y0, y1, a0 + + assert_sreg 0, x0 + assert_sreg 0x3fc838b2, a0 ! 0xa5a5 x 0xa5a5 + + test_grs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sh/pdec.s b/sim/testsuite/sh/pdec.s new file mode 100644 index 0000000..fa4b6a5 --- /dev/null +++ b/sim/testsuite/sh/pdec.s @@ -0,0 +1,110 @@ +# sh testcase for pdec +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pdecx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pdec x0, y0 + assert_sreg 0xa5a40000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pdecy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pdec y0, x0 + assert_sreg 0xa5a40000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dct_pdecx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dcfalse + dct pdec x0, y0 + assert_sreg 0xa5a5a5a5, y0 + set_dctrue + dct pdec x0, y0 + assert_sreg 0xa5a40000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dcf_pdecy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dctrue + dcf pdec y0, x0 + assert_sreg 0xa5a5a5a5, x0 + set_dcfalse + dcf pdec y0, x0 + assert_sreg 0xa5a40000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sh/pdmsb.s b/sim/testsuite/sh/pdmsb.s new file mode 100644 index 0000000..0cb7829 --- /dev/null +++ b/sim/testsuite/sh/pdmsb.s @@ -0,0 +1,230 @@ +# sh testcase for pdmsb +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x0, x0 +L0: pdmsb x0, x1 +# assert_sreg 31<<16, x1 + set_sreg 0x1, x0 +L1: pdmsb x0, x1 + assert_sreg 30<<16, x1 + set_sreg 0x3, x0 +L2: pdmsb x0, x1 + assert_sreg 29<<16, x1 + set_sreg 0x7, x0 +L3: pdmsb x0, x1 + assert_sreg 28<<16, x1 + set_sreg 0xf, x0 +L4: pdmsb x0, x1 + assert_sreg 27<<16, x1 + set_sreg 0x1f, x0 +L5: pdmsb x0, x1 + assert_sreg 26<<16, x1 + set_sreg 0x3f, x0 +L6: pdmsb x0, x1 + assert_sreg 25<<16, x1 + set_sreg 0x7f, x0 +L7: pdmsb x0, x1 + assert_sreg 24<<16, x1 + set_sreg 0xff, x0 +L8: pdmsb x0, x1 + assert_sreg 23<<16, x1 + + set_sreg 0x1ff, x0 +L9: pdmsb x0, x1 + assert_sreg 22<<16, x1 + set_sreg 0x3ff, x0 +L10: pdmsb x0, x1 + assert_sreg 21<<16, x1 + set_sreg 0x7ff, x0 +L11: pdmsb x0, x1 + assert_sreg 20<<16, x1 + set_sreg 0xfff, x0 +L12: pdmsb x0, x1 + assert_sreg 19<<16, x1 + set_sreg 0x1fff, x0 +L13: pdmsb x0, x1 + assert_sreg 18<<16, x1 + set_sreg 0x3fff, x0 +L14: pdmsb x0, x1 + assert_sreg 17<<16, x1 + set_sreg 0x7fff, x0 +L15: pdmsb x0, x1 + assert_sreg 16<<16, x1 + set_sreg 0xffff, x0 +L16: pdmsb x0, x1 + assert_sreg 15<<16, x1 + + set_sreg 0x1ffff, x0 +L17: pdmsb x0, x1 + assert_sreg 14<<16, x1 + set_sreg 0x3ffff, x0 +L18: pdmsb x0, x1 + assert_sreg 13<<16, x1 + set_sreg 0x7ffff, x0 +L19: pdmsb x0, x1 + assert_sreg 12<<16, x1 + set_sreg 0xfffff, x0 +L20: pdmsb x0, x1 + assert_sreg 11<<16, x1 + set_sreg 0x1fffff, x0 +L21: pdmsb x0, x1 + assert_sreg 10<<16, x1 + set_sreg 0x3fffff, x0 +L22: pdmsb x0, x1 + assert_sreg 9<<16, x1 + set_sreg 0x7fffff, x0 +L23: pdmsb x0, x1 + assert_sreg 8<<16, x1 + set_sreg 0xffffff, x0 +L24: pdmsb x0, x1 + assert_sreg 7<<16, x1 + + set_sreg 0x1ffffff, x0 +L25: pdmsb x0, x1 + assert_sreg 6<<16, x1 + set_sreg 0x3ffffff, x0 +L26: pdmsb x0, x1 + assert_sreg 5<<16, x1 + set_sreg 0x7ffffff, x0 +L27: pdmsb x0, x1 + assert_sreg 4<<16, x1 + set_sreg 0xfffffff, x0 +L28: pdmsb x0, x1 + assert_sreg 3<<16, x1 + set_sreg 0x1fffffff, x0 +L29: pdmsb x0, x1 + assert_sreg 2<<16, x1 + set_sreg 0x3fffffff, x0 +L30: pdmsb x0, x1 + assert_sreg 1<<16, x1 + set_sreg 0x7fffffff, x0 +L31: pdmsb x0, x1 + assert_sreg 0<<16, x1 + set_sreg 0xffffffff, x0 +L32: pdmsb x0, x1 +# assert_sreg 31<<16, x1 + + set_sreg 0xfffffffe, x0 +L33: pdmsb x0, x1 + assert_sreg 30<<16, x1 + set_sreg 0xfffffffc, x0 +L34: pdmsb x0, x1 + assert_sreg 29<<16, x1 + set_sreg 0xfffffff8, x0 +L35: pdmsb x0, x1 + assert_sreg 28<<16, x1 + set_sreg 0xfffffff0, x0 +L36: pdmsb x0, x1 + assert_sreg 27<<16, x1 + set_sreg 0xffffffe0, x0 +L37: pdmsb x0, x1 + assert_sreg 26<<16, x1 + set_sreg 0xffffffc0, x0 +L38: pdmsb x0, x1 + assert_sreg 25<<16, x1 + set_sreg 0xffffff80, x0 +L39: pdmsb x0, x1 + assert_sreg 24<<16, x1 + set_sreg 0xffffff00, x0 +L40: pdmsb x0, x1 + assert_sreg 23<<16, x1 + + set_sreg 0xfffffe00, x0 +L41: pdmsb x0, x1 + assert_sreg 22<<16, x1 + set_sreg 0xfffffc00, x0 +L42: pdmsb x0, x1 + assert_sreg 21<<16, x1 + set_sreg 0xfffff800, x0 +L43: pdmsb x0, x1 + assert_sreg 20<<16, x1 + set_sreg 0xfffff000, x0 +L44: pdmsb x0, x1 + assert_sreg 19<<16, x1 + set_sreg 0xffffe000, x0 +L45: pdmsb x0, x1 + assert_sreg 18<<16, x1 + set_sreg 0xffffc000, x0 +L46: pdmsb x0, x1 + assert_sreg 17<<16, x1 + set_sreg 0xffff8000, x0 +L47: pdmsb x0, x1 + assert_sreg 16<<16, x1 + set_sreg 0xffff0000, x0 +L48: pdmsb x0, x1 + assert_sreg 15<<16, x1 + + set_sreg 0xfffe0000, x0 +L49: pdmsb x0, x1 + assert_sreg 14<<16, x1 + set_sreg 0xfffc0000, x0 +L50: pdmsb x0, x1 + assert_sreg 13<<16, x1 + set_sreg 0xfff80000, x0 +L51: pdmsb x0, x1 + assert_sreg 12<<16, x1 + set_sreg 0xfff00000, x0 +L52: pdmsb x0, x1 + assert_sreg 11<<16, x1 + set_sreg 0xffe00000, x0 +L53: pdmsb x0, x1 + assert_sreg 10<<16, x1 + set_sreg 0xffc00000, x0 +L54: pdmsb x0, x1 + assert_sreg 9<<16, x1 + set_sreg 0xff800000, x0 +L55: pdmsb x0, x1 + assert_sreg 8<<16, x1 + set_sreg 0xff000000, x0 +L56: pdmsb x0, x1 + assert_sreg 7<<16, x1 + + set_sreg 0xfe000000, x0 +L57: pdmsb x0, x1 + assert_sreg 6<<16, x1 + set_sreg 0xfc000000, x0 +L58: pdmsb x0, x1 + assert_sreg 5<<16, x1 + set_sreg 0xf8000000, x0 +L59: pdmsb x0, x1 + assert_sreg 4<<16, x1 + set_sreg 0xf0000000, x0 +L60: pdmsb x0, x1 + assert_sreg 3<<16, x1 + set_sreg 0xe0000000, x0 +L61: pdmsb x0, x1 + assert_sreg 2<<16, x1 + set_sreg 0xc0000000, x0 +L62: pdmsb x0, x1 + assert_sreg 1<<16, x1 + set_sreg 0x80000000, x0 +L63: pdmsb x0, x1 + assert_sreg 0<<16, x1 + set_sreg 0x00000000, x0 +L64: pdmsb x0, x1 +# assert_sreg 31<<16, x1 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sh/pinc.s b/sim/testsuite/sh/pinc.s new file mode 100644 index 0000000..0067bc0 --- /dev/null +++ b/sim/testsuite/sh/pinc.s @@ -0,0 +1,110 @@ +# sh testcase for pinc +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pincx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pinc x0, y0 + assert_sreg 0xa5a60000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pincy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pinc y0, x0 + assert_sreg 0xa5a60000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dct_pincx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dcfalse + dct pinc x0, y0 + assert_sreg 0xa5a5a5a5, y0 + set_dctrue + dct pinc x0, y0 + assert_sreg 0xa5a60000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dcf_pincy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dctrue + dcf pinc y0, x0 + assert_sreg 0xa5a5a5a5, x0 + set_dcfalse + dcf pinc y0, x0 + assert_sreg 0xa5a60000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sh/pmuls.s b/sim/testsuite/sh/pmuls.s new file mode 100644 index 0000000..4cff878 --- /dev/null +++ b/sim/testsuite/sh/pmuls.s @@ -0,0 +1,33 @@ +# sh testcase for pmuls +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + # 2 x 2 = 8 (?) + # (I don't understand why the result is x2, + # but that's what it says in the manual...) + mov #2, r0 + shll16 r0 + lds r0, y0 + lds r0, y1 + pmuls y0, y1, a0 + + assert_sreg 8, a0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + pass + exit 0 + diff --git a/sim/testsuite/sh/prnd.s b/sim/testsuite/sh/prnd.s new file mode 100644 index 0000000..897d5b9 --- /dev/null +++ b/sim/testsuite/sh/prnd.s @@ -0,0 +1,90 @@ +# sh testcase for prnd +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + # FIXME: opcode table ambiguity in ignored bits 4-7. + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + # prnd(0xa5a5a5a5) = 0xa5a60000 + prnd x0, x0 + prnd y0, y0 + assert_sreg 0xa5a60000, x0 + assert_sreg 0xa5a60000, y0 + + # prnd(1) = 1 + mov #1, r0 + shll16 r0 + lds r0, x0 + pcopy x0, y0 + prnd x0, x0 + prnd y0, y0 + assert_sreg 0x10000, x0 + assert_sreg 0x10000, y0 + + # prnd(1.4999999) = 1 + mov #1, r0 + shll8 r0 + or #0x7f, r0 + shll8 r0 + or #0xff, r0 + lds r0, x0 + pcopy x0, y0 + prnd x0, x0 + prnd y0, y0 + assert_sreg 0x10000, x0 + assert_sreg 0x10000, y0 + + # prnd(1.5) = 2 + mov #1, r0 + shll8 r0 + or #0x80, r0 + shll8 r0 + lds r0, x0 + pcopy x0, y0 + prnd x0, x0 + prnd y0, y0 + assert_sreg 0x20000, x0 + assert_sreg 0x20000, y0 + + # dct prnd + set_dcfalse + dct prnd x0, x1 + dct prnd y0, y1 + assert_sreg2 0xa5a5a5a5, x1 + assert_sreg2 0xa5a5a5a5, y1 + set_dctrue + dct prnd x0, x1 + dct prnd y0, y1 + assert_sreg2 0x20000, x1 + assert_sreg2 0x20000, y1 + + # dcf prnd + set_dctrue + dcf prnd x0, m0 + dcf prnd y0, m1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf prnd x0, m0 + dcf prnd y0, m1 + assert_sreg2 0x20000, m0 + assert_sreg2 0x20000, m1 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + pass + exit 0 diff --git a/sim/testsuite/sh/pshai.s b/sim/testsuite/sh/pshai.s new file mode 100644 index 0000000..b2cdbbc --- /dev/null +++ b/sim/testsuite/sh/pshai.s @@ -0,0 +1,200 @@ +# sh testcase for psha +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +psha_imm: ! shift arithmetic, immediate operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x1, a0 + psha #0, a0 + assert_sreg 0x1, a0 + psha #-0, a0 + assert_sreg 0x1, a0 + + psha #1, a0 + assert_sreg 0x2, a0 + psha #-1, a0 + assert_sreg 0x1, a0 + + psha #2, a0 + assert_sreg 0x4, a0 + psha #-2, a0 + assert_sreg 0x1, a0 + + psha #3, a0 + assert_sreg 0x8, a0 + psha #-3, a0 + assert_sreg 0x1, a0 + + psha #4, a0 + assert_sreg 0x10, a0 + psha #-4, a0 + assert_sreg 0x1, a0 + + psha #5, a0 + assert_sreg 0x20, a0 + psha #-5, a0 + assert_sreg 0x1, a0 + + psha #6, a0 + assert_sreg 0x40, a0 + psha #-6, a0 + assert_sreg 0x1, a0 + + psha #7, a0 + assert_sreg 0x80, a0 + psha #-7, a0 + assert_sreg 0x1, a0 + + psha #8, a0 + assert_sreg 0x100, a0 + psha #-8, a0 + assert_sreg 0x1, a0 + + psha #9, a0 + assert_sreg 0x200, a0 + psha #-9, a0 + assert_sreg 0x1, a0 + + psha #10, a0 + assert_sreg 0x400, a0 + psha #-10, a0 + assert_sreg 0x1, a0 + + psha #11, a0 + assert_sreg 0x800, a0 + psha #-11, a0 + assert_sreg 0x1, a0 + + psha #12, a0 + assert_sreg 0x1000, a0 + psha #-12, a0 + assert_sreg 0x1, a0 + + psha #13, a0 + assert_sreg 0x2000, a0 + psha #-13, a0 + assert_sreg 0x1, a0 + + psha #14, a0 + assert_sreg 0x4000, a0 + psha #-14, a0 + assert_sreg 0x1, a0 + + psha #15, a0 + assert_sreg 0x8000, a0 + psha #-15, a0 + assert_sreg 0x1, a0 + + psha #16, a0 + assert_sreg 0x10000, a0 + psha #-16, a0 + assert_sreg 0x1, a0 + + psha #17, a0 + assert_sreg 0x20000, a0 + psha #-17, a0 + assert_sreg 0x1, a0 + + psha #18, a0 + assert_sreg 0x40000, a0 + psha #-18, a0 + assert_sreg 0x1, a0 + + psha #19, a0 + assert_sreg 0x80000, a0 + psha #-19, a0 + assert_sreg 0x1, a0 + + psha #20, a0 + assert_sreg 0x100000, a0 + psha #-20, a0 + assert_sreg 0x1, a0 + + psha #21, a0 + assert_sreg 0x200000, a0 + psha #-21, a0 + assert_sreg 0x1, a0 + + psha #22, a0 + assert_sreg 0x400000, a0 + psha #-22, a0 + assert_sreg 0x1, a0 + + psha #23, a0 + assert_sreg 0x800000, a0 + psha #-23, a0 + assert_sreg 0x1, a0 + + psha #24, a0 + assert_sreg 0x1000000, a0 + psha #-24, a0 + assert_sreg 0x1, a0 + + psha #25, a0 + assert_sreg 0x2000000, a0 + psha #-25, a0 + assert_sreg 0x1, a0 + + psha #26, a0 + assert_sreg 0x4000000, a0 + psha #-26, a0 + assert_sreg 0x1, a0 + + psha #27, a0 + assert_sreg 0x8000000, a0 + psha #-27, a0 + assert_sreg 0x1, a0 + + psha #28, a0 + assert_sreg 0x10000000, a0 + psha #-28, a0 + assert_sreg 0x1, a0 + + psha #29, a0 + assert_sreg 0x20000000, a0 + psha #-29, a0 + assert_sreg 0x1, a0 + + psha #30, a0 + assert_sreg 0x40000000, a0 + psha #-30, a0 + assert_sreg 0x1, a0 + + psha #31, a0 + assert_sreg 0x80000000, a0 + psha #-31, a0 + assert_sreg 0xffffffff, a0 + + psha #32, a0 + assert_sreg 0x00000000, a0 +# I don't grok what should happen here... +# psha #-32, a0 +# assert_sreg 0x0, a0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sh/pshar.s b/sim/testsuite/sh/pshar.s new file mode 100644 index 0000000..01c4b5f --- /dev/null +++ b/sim/testsuite/sh/pshar.s @@ -0,0 +1,265 @@ +# sh testcase for psha +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +psha_reg: ! shift arithmetic, register operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x1, x0 + set_sreg 0x0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x10000, y0 + psha x0, y0, x0 + assert_sreg 0x2, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x20000, y0 + psha x0, y0, x0 + assert_sreg 0x4, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x30000, y0 + psha x0, y0, x0 + assert_sreg 0x8, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x40000, y0 + psha x0, y0, x0 + assert_sreg 0x10, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x50000, y0 + psha x0, y0, x0 + assert_sreg 0x20, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x60000, y0 + psha x0, y0, x0 + assert_sreg 0x40, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x70000, y0 + psha x0, y0, x0 + assert_sreg 0x80, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x80000, y0 + psha x0, y0, x0 + assert_sreg 0x100, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x90000, y0 + psha x0, y0, x0 + assert_sreg 0x200, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xa0000, y0 + psha x0, y0, x0 + assert_sreg 0x400, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xb0000, y0 + psha x0, y0, x0 + assert_sreg 0x800, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xc0000, y0 + psha x0, y0, x0 + assert_sreg 0x1000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xd0000, y0 + psha x0, y0, x0 + assert_sreg 0x2000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xe0000, y0 + psha x0, y0, x0 + assert_sreg 0x4000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xf0000, y0 + psha x0, y0, x0 + assert_sreg 0x8000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x100000, y0 + psha x0, y0, x0 + assert_sreg 0x10000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x110000, y0 + psha x0, y0, x0 + assert_sreg 0x20000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x120000, y0 + psha x0, y0, x0 + assert_sreg 0x40000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x130000, y0 + psha x0, y0, x0 + assert_sreg 0x80000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x140000, y0 + psha x0, y0, x0 + assert_sreg 0x100000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x150000, y0 + psha x0, y0, x0 + assert_sreg 0x200000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x160000, y0 + psha x0, y0, x0 + assert_sreg 0x400000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x170000, y0 + psha x0, y0, x0 + assert_sreg 0x800000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x180000, y0 + psha x0, y0, x0 + assert_sreg 0x1000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x190000, y0 + psha x0, y0, x0 + assert_sreg 0x2000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1a0000, y0 + psha x0, y0, x0 + assert_sreg 0x4000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1b0000, y0 + psha x0, y0, x0 + assert_sreg 0x8000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1c0000, y0 + psha x0, y0, x0 + assert_sreg 0x10000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1d0000, y0 + psha x0, y0, x0 + assert_sreg 0x20000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1e0000, y0 + psha x0, y0, x0 + assert_sreg 0x40000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1f0000, y0 + psha x0, y0, x0 + assert_sreg 0x80000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0xffffffff, x0 + + set_sreg 0x200000, y0 + psha x0, y0, x0 + assert_sreg 0x00000000, x0 +# I don't grok what should happen here... +# pneg y0, y0 +# psha x0, y0, x0 +# assert_sreg 0x0, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sh/pshli.s b/sim/testsuite/sh/pshli.s new file mode 100644 index 0000000..a6616e8 --- /dev/null +++ b/sim/testsuite/sh/pshli.s @@ -0,0 +1,119 @@ +# sh testcase for pshl +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pshl_imm: ! shift logical, immediate operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x10000, a0 + pshl #0, a0 + assert_sreg 0x10000, a0 + pshl #-0, a0 + assert_sreg 0x10000, a0 + + pshl #1, a0 + assert_sreg 0x20000, a0 + pshl #-1, a0 + assert_sreg 0x10000, a0 + + pshl #2, a0 + assert_sreg 0x40000, a0 + pshl #-2, a0 + assert_sreg 0x10000, a0 + + pshl #3, a0 + assert_sreg 0x80000, a0 + pshl #-3, a0 + assert_sreg 0x10000, a0 + + pshl #4, a0 + assert_sreg 0x100000, a0 + pshl #-4, a0 + assert_sreg 0x10000, a0 + + pshl #5, a0 + assert_sreg 0x200000, a0 + pshl #-5, a0 + assert_sreg 0x10000, a0 + + pshl #6, a0 + assert_sreg 0x400000, a0 + pshl #-6, a0 + assert_sreg 0x10000, a0 + + pshl #7, a0 + assert_sreg 0x800000, a0 + pshl #-7, a0 + assert_sreg 0x10000, a0 + + pshl #8, a0 + assert_sreg 0x1000000, a0 + pshl #-8, a0 + assert_sreg 0x10000, a0 + + pshl #9, a0 + assert_sreg 0x2000000, a0 + pshl #-9, a0 + assert_sreg 0x10000, a0 + + pshl #10, a0 + assert_sreg 0x4000000, a0 + pshl #-10, a0 + assert_sreg 0x10000, a0 + + pshl #11, a0 + assert_sreg 0x8000000, a0 + pshl #-11, a0 + assert_sreg 0x10000, a0 + + pshl #12, a0 + assert_sreg 0x10000000, a0 + pshl #-12, a0 + assert_sreg 0x10000, a0 + + pshl #13, a0 + assert_sreg 0x20000000, a0 + pshl #-13, a0 + assert_sreg 0x10000, a0 + + pshl #14, a0 + assert_sreg 0x40000000, a0 + pshl #-14, a0 + assert_sreg 0x10000, a0 + + pshl #15, a0 + assert_sreg 0x80000000, a0 + pshl #-15, a0 + assert_sreg 0x10000, a0 + + pshl #16, a0 + assert_sreg 0x00000000, a0 + pshl #-16, a0 + assert_sreg 0x0, a0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sh/pshlr.s b/sim/testsuite/sh/pshlr.s new file mode 100644 index 0000000..36cb47f --- /dev/null +++ b/sim/testsuite/sh/pshlr.s @@ -0,0 +1,152 @@ +# sh testcase for pshl +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pshl_reg: ! shift arithmetic, register operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x10000, x0 + set_sreg 0x0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x10000, y0 + pshl x0, y0, x0 + assert_sreg 0x20000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x20000, y0 + pshl x0, y0, x0 + assert_sreg 0x40000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x30000, y0 + pshl x0, y0, x0 + assert_sreg 0x80000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x40000, y0 + pshl x0, y0, x0 + assert_sreg 0x100000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x50000, y0 + pshl x0, y0, x0 + assert_sreg 0x200000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x60000, y0 + pshl x0, y0, x0 + assert_sreg 0x400000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x70000, y0 + pshl x0, y0, x0 + assert_sreg 0x800000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x80000, y0 + pshl x0, y0, x0 + assert_sreg 0x1000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x90000, y0 + pshl x0, y0, x0 + assert_sreg 0x2000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xa0000, y0 + pshl x0, y0, x0 + assert_sreg 0x4000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xb0000, y0 + pshl x0, y0, x0 + assert_sreg 0x8000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xc0000, y0 + pshl x0, y0, x0 + assert_sreg 0x10000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xd0000, y0 + pshl x0, y0, x0 + assert_sreg 0x20000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xe0000, y0 + pshl x0, y0, x0 + assert_sreg 0x40000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xf0000, y0 + pshl x0, y0, x0 + assert_sreg 0x80000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x100000, y0 + pshl x0, y0, x0 + assert_sreg 0x00000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x0, x0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sh/psub.s b/sim/testsuite/sh/psub.s new file mode 100644 index 0000000..bcfd26e --- /dev/null +++ b/sim/testsuite/sh/psub.s @@ -0,0 +1,64 @@ +# sh testcase for psub +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + +psub_sx_sy: + # 0xa5a5a5a5 minus 0xa5a5a5a5 equals zero + psub x0, y0, a0 + assert_sreg 0, a0 + +psub_sy_sx: + # 100 - 25 = 75 + mov #100, r0 + mov #25, r1 + lds r0, y1 + lds r1, x1 + psub y1, x1, a0 + assert_sreg 75, a0 + +dct_psub: + # 100 - 25 = 75 + set_dcfalse + dct psub y1, x1, a1 + assert_sreg2 0xa5a5a5a5, a1 + set_dctrue + dct psub y1, x1, a1 + assert_sreg2 75, a1 + +dcf_psub: + # 25 - 100 = -75 + set_dctrue + dcf psub x1, y1, m1 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf psub x1, y1, m1 + assert_sreg2 -75, m1 + +psub_pmuls: + # 25 - 100 = -75, and 2 x 2 = 8 (yes, eight, not four) + mov #2, r0 + shll16 r0 + lds r0, x0 + lds r0, y0 + psub x1, y1, a1 pmuls x0, y0, a0 + assert_sreg 8, a0 + assert_sreg2 -75, a1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/pswap.s b/sim/testsuite/sh/pswap.s new file mode 100644 index 0000000..5bd6a59 --- /dev/null +++ b/sim/testsuite/sh/pswap.s @@ -0,0 +1,177 @@ +# sh testcase for pswap +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pswapx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_greg 0xa5a57777, r0 + lds r0, x0 + pswap x0, y0 + assert_sreg 0x7777a5a5, y0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a57777, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pswapy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_greg 0xa5a57777, r0 + lds r0, y0 + pswap y0, x0 + assert_sreg 0x7777a5a5, x0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a57777, y0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pswapa: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_greg 0xa5a57777, r0 + lds r0, a0 + pcopy a0, a1 + pswap a1, y0 + assert_sreg 0x7777a5a5, y0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a57777, a0 + assert_sreg2 0xa5a57777, a1 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pswapm: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_greg 0xa5a57777, r0 + lds r0, a0 + pcopy a0, m1 + pswap m1, y0 + assert_sreg 0x7777a5a5, y0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a57777, a0 + assert_sreg2 0xa5a57777, m1 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + + +dct_pswapx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_greg 0xa5a57777, r0 + lds r0, x0 + set_dcfalse + dct pswap x0, y0 + assert_sreg 0xa5a5a5a5, y0 + set_dctrue + dct pswap x0, y0 + assert_sreg 0x7777a5a5, y0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a57777, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dcf_pswapy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_greg 0xa5a57777, r0 + lds r0, x0 + set_dctrue + dcf pswap x0, y0 + assert_sreg 0xa5a5a5a5, y0 + set_dcfalse + dcf pswap x0, y0 + assert_sreg 0x7777a5a5, y0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a57777, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sh/pushpop.s b/sim/testsuite/sh/pushpop.s new file mode 100644 index 0000000..9ee5bfd --- /dev/null +++ b/sim/testsuite/sh/pushpop.s @@ -0,0 +1,146 @@ +# sh testcase for push/pop (mov,movml,movmu...) insns. +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start +movml_1: + set_greg 0, r0 + set_greg 1, r1 + set_greg 2, r2 + set_greg 3, r3 + set_greg 4, r4 + set_greg 5, r5 + set_greg 6, r6 + set_greg 7, r7 + set_greg 8, r8 + set_greg 9, r9 + set_greg 10, r10 + set_greg 11, r11 + set_greg 12, r12 + set_greg 13, r13 + set_greg 14, r14 + set_sreg 15, pr + + movml.l r15,@-r15 + + assertmem stackt-4, 15 + assertmem stackt-8, 14 + assertmem stackt-12, 13 + assertmem stackt-16, 12 + assertmem stackt-20, 11 + assertmem stackt-24, 10 + assertmem stackt-28, 9 + assertmem stackt-32, 8 + assertmem stackt-36, 7 + assertmem stackt-40, 6 + assertmem stackt-44, 5 + assertmem stackt-48, 4 + assertmem stackt-52, 3 + assertmem stackt-56, 2 + assertmem stackt-60, 1 + assertmem stackt-64, 0 + + assertreg0 0 + assertreg 1, r1 + assertreg 2, r2 + assertreg 3, r3 + assertreg 4, r4 + assertreg 5, r5 + assertreg 6, r6 + assertreg 7, r7 + assertreg 8, r8 + assertreg 9, r9 + assertreg 10, r10 + assertreg 11, r11 + assertreg 12, r12 + assertreg 13, r13 + assertreg 14, r14 + mov r15, r0 + assertreg0 stackt-64 + +movml_2: + set_grs_a5a5 + movml.l @r15+, r15 + assert_sreg 15, pr + assertreg0 0 + assertreg 1, r1 + assertreg 2, r2 + assertreg 3, r3 + assertreg 4, r4 + assertreg 5, r5 + assertreg 6, r6 + assertreg 7, r7 + assertreg 8, r8 + assertreg 9, r9 + assertreg 10, r10 + assertreg 11, r11 + assertreg 12, r12 + assertreg 13, r13 + assertreg 14, r14 + mov r15, r0 + assertreg0 stackt + +movmu_1: + set_grs_a5a5 + add #1,r14 + add #2,r13 + add #3,r12 + set_sreg 0xa5a5,pr + + movmu.l r12,@-r15 + + assert_sreg 0xa5a5,pr + assertreg 0xa5a5a5a6, r14 + assertreg 0xa5a5a5a7, r13 + assertreg 0xa5a5a5a8, r12 + test_gr_a5a5 r11 + test_gr_a5a5 r10 + test_gr_a5a5 r9 + test_gr_a5a5 r8 + test_gr_a5a5 r7 + test_gr_a5a5 r6 + test_gr_a5a5 r5 + test_gr_a5a5 r4 + test_gr_a5a5 r3 + test_gr_a5a5 r2 + test_gr_a5a5 r1 + test_gr_a5a5 r0 + mov r15, r0 + assertreg stackt-16, r0 + + assertmem stackt-4, 0xa5a5 + assertmem stackt-8, 0xa5a5a5a6 + assertmem stackt-12, 0xa5a5a5a7 + assertmem stackt-16, 0xa5a5a5a8 + +movmu_2: + set_grs_a5a5 + movmu.l @r15+,r12 + + assert_sreg 0xa5a5, pr + assertreg 0xa5a5a5a6, r14 + assertreg 0xa5a5a5a7, r13 + assertreg 0xa5a5a5a8, r12 + test_gr_a5a5 r11 + test_gr_a5a5 r10 + test_gr_a5a5 r9 + test_gr_a5a5 r8 + test_gr_a5a5 r7 + test_gr_a5a5 r6 + test_gr_a5a5 r5 + test_gr_a5a5 r4 + test_gr_a5a5 r3 + test_gr_a5a5 r2 + test_gr_a5a5 r1 + test_gr_a5a5 r0 + mov r15, r0 + assertreg stackt, r0 + + pass + + exit 0 + + \ No newline at end of file diff --git a/sim/testsuite/sh/resbank.s b/sim/testsuite/sh/resbank.s new file mode 100644 index 0000000..33801b8 --- /dev/null +++ b/sim/testsuite/sh/resbank.s @@ -0,0 +1,268 @@ +# sh testcase for ldbank stbank resbank +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .macro SEND reg bankno regno + set_greg ((\bankno << 7) + (\regno << 2)), \reg + .endm + + start + +stbank_1: + set_grs_a5a5 + mov #0, r0 + SEND r1, 0, 0 + stbank r0, @r1 + mov #1, r0 + SEND r1, 0, 1 + stbank r0, @r1 + mov #2, r0 + SEND r1, 0, 2 + stbank r0, @r1 + mov #3, r0 + SEND r1, 0, 3 + stbank r0, @r1 + mov #4, r0 + SEND r1, 0, 4 + stbank r0, @r1 + mov #5, r0 + SEND r1, 0, 5 + stbank r0, @r1 + mov #6, r0 + SEND r1, 0, 6 + stbank r0, @r1 + mov #7, r0 + SEND r1, 0, 7 + stbank r0, @r1 + mov #8, r0 + SEND r1, 0, 8 + stbank r0, @r1 + mov #9, r0 + SEND r1, 0, 9 + stbank r0, @r1 + mov #10, r0 + SEND r1, 0, 10 + stbank r0, @r1 + mov #11, r0 + SEND r1, 0, 11 + stbank r0, @r1 + mov #12, r0 + SEND r1, 0, 12 + stbank r0, @r1 + mov #13, r0 + SEND r1, 0, 13 + stbank r0, @r1 + mov #14, r0 + SEND r1, 0, 14 + stbank r0, @r1 + mov #15, r0 + SEND r1, 0, 15 + stbank r0, @r1 + mov #16, r0 + SEND r1, 0, 16 + stbank r0, @r1 + mov #17, r0 + SEND r1, 0, 17 + stbank r0, @r1 + mov #18, r0 + SEND r1, 0, 18 + stbank r0, @r1 + mov #19, r0 + SEND r1, 0, 19 + stbank r0, @r1 + + assertreg0 19 + assertreg 19 << 2, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +ldbank_1: + set_grs_a5a5 + SEND r1, 0, 0 + ldbank @r1, r0 + assertreg0 0 + SEND r1, 0, 1 + ldbank @r1, r0 + assertreg0 1 + SEND r1, 0, 2 + ldbank @r1, r0 + assertreg0 2 + SEND r1, 0, 3 + ldbank @r1, r0 + assertreg0 3 + SEND r1, 0, 4 + ldbank @r1, r0 + assertreg0 4 + SEND r1, 0, 5 + ldbank @r1, r0 + assertreg0 5 + SEND r1, 0, 6 + ldbank @r1, r0 + assertreg0 6 + SEND r1, 0, 7 + ldbank @r1, r0 + assertreg0 7 + SEND r1, 0, 8 + ldbank @r1, r0 + assertreg0 8 + SEND r1, 0, 9 + ldbank @r1, r0 + assertreg0 9 + SEND r1, 0, 10 + ldbank @r1, r0 + assertreg0 10 + SEND r1, 0, 11 + ldbank @r1, r0 + assertreg0 11 + SEND r1, 0, 12 + ldbank @r1, r0 + assertreg0 12 + SEND r1, 0, 13 + ldbank @r1, r0 + assertreg0 13 + SEND r1, 0, 14 + ldbank @r1, r0 + assertreg0 14 + SEND r1, 0, 15 + ldbank @r1, r0 + assertreg0 15 + SEND r1, 0, 16 + ldbank @r1, r0 + assertreg0 16 + SEND r1, 0, 17 + ldbank @r1, r0 + assertreg0 17 + SEND r1, 0, 18 + ldbank @r1, r0 + assertreg0 18 + SEND r1, 0, 19 + ldbank @r1, r0 + assertreg0 19 + + assertreg (19 << 2), r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +resbank_1: + set_grs_a5a5 + mov #1, r0 + trapa #13 ! magic trap, sets ibnr + + resbank + + assertreg0 0 + assertreg 1, r1 + assertreg 2, r2 + assertreg 3, r3 + assertreg 4, r4 + assertreg 5, r5 + assertreg 6, r6 + assertreg 7, r7 + assertreg 8, r8 + assertreg 9, r9 + assertreg 10, r10 + assertreg 11, r11 + assertreg 12, r12 + assertreg 13, r13 + assertreg 14, r14 + assert_sreg 15, mach + assert_sreg 17, pr + assert_creg 18, gbr + assert_sreg 19, macl + +resbank_2: + set_grs_a5a5 + movi20 #555, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + + set_sr_bit (1 << 14) ! set BO + + resbank + + assert_sreg 555, macl + assert_sreg 554, mach + assert_creg 553, gbr + assert_sreg 552, pr + assertreg 551, r14 + assertreg 550, r13 + assertreg 549, r12 + assertreg 548, r11 + assertreg 547, r10 + assertreg 546, r9 + assertreg 545, r8 + assertreg 544, r7 + assertreg 543, r6 + assertreg 542, r5 + assertreg 541, r4 + assertreg 540, r3 + assertreg 539, r2 + assertreg 538, r1 + assertreg0 537 + + mov r15, r0 + assertreg0 stackt + + pass + + exit 0 diff --git a/sim/testsuite/sh/sett.s b/sim/testsuite/sh/sett.s new file mode 100644 index 0000000..fff2d2d --- /dev/null +++ b/sim/testsuite/sh/sett.s @@ -0,0 +1,65 @@ +# sh testcase for sett, clrt, movt +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start +sett_1: set_grs_a5a5 + sett + bt .Lsett + nop + fail +.Lsett: + test_grs_a5a5 + +clrt_1: set_grs_a5a5 + clrt + bf .Lclrt + nop + fail +.Lclrt: + test_grs_a5a5 + +movt_1: set_grs_a5a5 + sett + movt r1 + test_gr_a5a5 r0 + assertreg 1, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +movt_2: set_grs_a5a5 + clrt + movt r1 + test_gr_a5a5 r0 + assertreg 0, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 diff --git a/sim/testsuite/sh/shll.s b/sim/testsuite/sh/shll.s new file mode 100644 index 0000000..ec2ea12 --- /dev/null +++ b/sim/testsuite/sh/shll.s @@ -0,0 +1,91 @@ +# sh testcase for shll +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shll: + set_grs_a5a5 + mov #1, r1 + shll r1 + assertreg 2, r1 + shll r1 + assertreg 4, r1 + shll r1 + assertreg 8, r1 + shll r1 + assertreg 16, r1 + shll r1 + assertreg 32, r1 + shll r1 + assertreg 64, r1 + shll r1 + assertreg 0x80, r1 + shll r1 + assertreg 0x100, r1 + shll r1 + assertreg 0x200, r1 + shll r1 + assertreg 0x400, r1 + shll r1 + assertreg 0x800, r1 + shll r1 + assertreg 0x1000, r1 + shll r1 + assertreg 0x2000, r1 + shll r1 + assertreg 0x4000, r1 + shll r1 + assertreg 0x8000, r1 + shll r1 + assertreg 0x10000, r1 + shll r1 + assertreg 0x20000, r1 + shll r1 + assertreg 0x40000, r1 + shll r1 + assertreg 0x80000, r1 + shll r1 + assertreg 0x100000, r1 + shll r1 + assertreg 0x200000, r1 + shll r1 + assertreg 0x400000, r1 + shll r1 + assertreg 0x800000, r1 + shll r1 + assertreg 0x1000000, r1 + shll r1 + assertreg 0x2000000, r1 + shll r1 + assertreg 0x4000000, r1 + shll r1 + assertreg 0x8000000, r1 + shll r1 + assertreg 0x10000000, r1 + shll r1 + assertreg 0x20000000, r1 + shll r1 + assertreg 0x40000000, r1 + shll r1 + assertreg 0x80000000, r1 + shll r1 + assertreg 0, r1 + shll r1 + assertreg 0, r1 + + # another: + mov #1, r1 + shll r1 + shll r1 + shll r1 + assertreg 8, r1 + + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sh/shll16.s b/sim/testsuite/sh/shll16.s new file mode 100644 index 0000000..4574835 --- /dev/null +++ b/sim/testsuite/sh/shll16.s @@ -0,0 +1,46 @@ +# sh testcase for shll16 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shll16: + set_grs_a5a5 + mov #0x18, r1 + shll16 r1 + assertreg 0x180000, r1 + shll16 r1 + assertreg 0, r1 + + # another: + mov #1, r1 + shll16 r1 + mov #1, r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + cmp/eq r1, r7 + bt okay + fail +okay: + set_greg 0xa5a5a5a5, r1 + set_greg 0xa5a5a5a5, r7 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/shll2.s b/sim/testsuite/sh/shll2.s new file mode 100644 index 0000000..01a784c --- /dev/null +++ b/sim/testsuite/sh/shll2.s @@ -0,0 +1,51 @@ +# sh testcase for shll2 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shll2: + set_grs_a5a5 + mov #1, r1 + shll2 r1 + assertreg 4, r1 + shll2 r1 + assertreg 16, r1 + shll2 r1 + assertreg 64, r1 + shll2 r1 + assertreg 0x100, r1 + shll2 r1 + assertreg 0x400, r1 + shll2 r1 + assertreg 0x1000, r1 + shll2 r1 + assertreg 0x4000, r1 + shll2 r1 + assertreg 0x10000, r1 + shll2 r1 + assertreg 0x40000, r1 + shll2 r1 + assertreg 0x100000, r1 + shll2 r1 + assertreg 0x400000, r1 + shll2 r1 + assertreg 0x1000000, r1 + shll2 r1 + assertreg 0x4000000, r1 + shll2 r1 + assertreg 0x10000000, r1 + shll2 r1 + assertreg 0x40000000, r1 + shll2 r1 + assertreg 0, r1 + + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + + pass + exit 0 + diff --git a/sim/testsuite/sh/shll8.s b/sim/testsuite/sh/shll8.s new file mode 100644 index 0000000..71e241d --- /dev/null +++ b/sim/testsuite/sh/shll8.s @@ -0,0 +1,42 @@ +# sh testcase for shll8 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shll8: + set_grs_a5a5 + mov #1, r1 + shll8 r1 + assertreg 0x100, r1 + shll8 r1 + assertreg 0x10000, r1 + shll8 r1 + assertreg 0x1000000, r1 + shll8 r1 + assertreg 0, r1 + + # another: + mov #1, r1 + shll8 r1 + mov #1, r2 + shll r2 + shll r2 + shll r2 + shll r2 + shll r2 + shll r2 + shll r2 + shll r2 + cmp/eq r1, r2 + bt okay + fail +okay: + set_greg 0xa5a5a5a5, r1 + set_greg 0xa5a5a5a5, r2 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/shlr.s b/sim/testsuite/sh/shlr.s new file mode 100644 index 0000000..8755afb --- /dev/null +++ b/sim/testsuite/sh/shlr.s @@ -0,0 +1,42 @@ +# sh testcase for shlr +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shlr: + set_grs_a5a5 + mov #0, r0 + or #192, r0 + shlr r0 + assertreg0 96 + shlr r0 + assertreg0 48 + shlr r0 + assertreg0 24 + shlr r0 + assertreg0 12 + shlr r0 + assertreg0 6 + shlr r0 + assertreg0 3 + + # Make sure a bit is shifted into T. + shlr r0 + bf wrong + assertreg0 1 + # Ditto. + shlr r0 + bf wrong + assertreg0 0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + pass + exit 0 + +wrong: + fail diff --git a/sim/testsuite/sh/shlr16.s b/sim/testsuite/sh/shlr16.s new file mode 100644 index 0000000..1161c66 --- /dev/null +++ b/sim/testsuite/sh/shlr16.s @@ -0,0 +1,20 @@ +# sh testcase for shlr16 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shrl16: + set_grs_a5a5 + shlr16 r0 + assertreg0 0xa5a5 + shlr16 r0 + assertreg0 0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/shlr2.s b/sim/testsuite/sh/shlr2.s new file mode 100644 index 0000000..ce554dd --- /dev/null +++ b/sim/testsuite/sh/shlr2.s @@ -0,0 +1,48 @@ +# sh testcase for shlr2 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shrl2: + set_grs_a5a5 + shlr2 r0 + assertreg0 0x29696969 + shlr2 r0 + assertreg0 0x0a5a5a5a + shlr2 r0 + assertreg0 0x02969696 + shlr2 r0 + assertreg0 0x00a5a5a5 + shlr2 r0 + assertreg0 0x00296969 + shlr2 r0 + assertreg0 0x000a5a5a + shlr2 r0 + assertreg0 0x00029696 + shlr2 r0 + assertreg0 0x0000a5a5 + shlr2 r0 + assertreg0 0x00002969 + shlr2 r0 + assertreg0 0x00000a5a + shlr2 r0 + assertreg0 0x00000296 + shlr2 r0 + assertreg0 0x000000a5 + shlr2 r0 + assertreg0 0x00000029 + shlr2 r0 + assertreg0 0x0000000a + shlr2 r0 + assertreg0 0x00000002 + shlr2 r0 + assertreg0 0 + + set_greg 0xa5a5a5a5 r0 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/shlr8.s b/sim/testsuite/sh/shlr8.s new file mode 100644 index 0000000..d609af1 --- /dev/null +++ b/sim/testsuite/sh/shlr8.s @@ -0,0 +1,24 @@ +# sh testcase for shlr8 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shrl8: + set_grs_a5a5 + shlr8 r0 + assertreg0 0xa5a5a5 + shlr8 r0 + assertreg0 0xa5a5 + shlr8 r0 + assertreg0 0xa5 + shlr8 r0 + assertreg0 0x0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/swap.s b/sim/testsuite/sh/swap.s new file mode 100644 index 0000000..4dd6572 --- /dev/null +++ b/sim/testsuite/sh/swap.s @@ -0,0 +1,59 @@ +# sh testcase for swap +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +swapb: + set_grs_a5a5 + mov #0x5a, r0 + shll8 r0 + or #0xa5, r0 + assertreg0 0x5aa5 + + swap.b r0, r1 + assertreg 0xa55a, r1 + + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +swapw: + set_grs_a5a5 + mov #0x5a, r0 + shll16 r0 + or #0xa5, r0 + assertreg0 0x5a00a5 + + swap.w r0, r1 + assertreg 0xa5005a, r1 + + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + exit 0 diff --git a/sim/testsuite/sh/testutils.inc b/sim/testsuite/sh/testutils.inc new file mode 100644 index 0000000..c9644b4 --- /dev/null +++ b/sim/testsuite/sh/testutils.inc @@ -0,0 +1,617 @@ +# Support macros for the sh assembly test cases. + + .equ no_dsp, 0 + .equ yes_dsp, 1 + + .section .rodata + .align 2 +_pass: .string "pass\n" +_fail: .string "fail\n" +_stack: .fill 128, 4, 0 +stackt: + + .macro push reg + mov.l \reg, @-r15 + .endm + + .macro pop reg + mov.l @r15+, \reg + .endm + + .macro start + .text + .align 1 + .global start +start: mov.l stackp, r15 + bra main + nop + .align 2 +stackp: .long stackt +mpass: + mov #4, r4 + mov #1, r5 + mov.l ppass, r6 + mov #5, r7 + trapa #34 + rts + nop +mfail: + mov #4, r4 + mov #1, r5 + mov.l pfail, r6 + mov #5, r7 + trapa #34 + mov #1, r5 +mexit: + mov #1, r4 + mov #0, r6 + mov #0, r7 + trapa #34 + .align 2 +ppass: .long _pass +pfail: .long _fail + +mtesta5: + push r0 + mov.l a5a5, r0 + cmp/eq r1, r0 + bf mfail + cmp/eq r2, r0 + bf mfail + cmp/eq r3, r0 + bf mfail + cmp/eq r4, r0 + bf mfail + cmp/eq r5, r0 + bf mfail + cmp/eq r6, r0 + bf mfail + cmp/eq r7, r0 + bf mfail + cmp/eq r8, r0 + bf mfail + cmp/eq r9, r0 + bf mfail + cmp/eq r10, r0 + bf mfail + cmp/eq r11, r0 + bf mfail + cmp/eq r12, r0 + bf mfail + cmp/eq r13, r0 + bf mfail + cmp/eq r14, r0 + bf mfail + # restore and check r0 + pop r0 + cmp/eq r0, r1 + bf mfail + # pass + rts + nop +.if (sim_cpu == no_dsp) +mtesta5_fp: + push r0 + flds fr0, fpul + sts fpul, r0 + push r0 + mov.l a5a5, r0 + lds r0, fpul + fsts fpul, fr0 + fcmp/eq fr1, fr0 + bf mfail + fcmp/eq fr2, fr0 + bf mfail + fcmp/eq fr3, fr0 + bf mfail + fcmp/eq fr4, fr0 + bf mfail + fcmp/eq fr5, fr0 + bf mfail + fcmp/eq fr6, fr0 + bf mfail + fcmp/eq fr7, fr0 + bf mfail + fcmp/eq fr8, fr0 + bf mfail + fcmp/eq fr9, fr0 + bf mfail + fcmp/eq fr10, fr0 + bf mfail + fcmp/eq fr11, fr0 + bf mfail + fcmp/eq fr12, fr0 + bf mfail + fcmp/eq fr13, fr0 + bf mfail + fcmp/eq fr14, fr0 + bf mfail + fcmp/eq fr15, fr0 + bf mfail + # restore and check fr0 + pop r0 + lds r0, fpul + fsts fpul, fr0 + fcmp/eq fr0, fr1 + bf mfail + # restore r0 and pass + pop r0 + rts + nop +.endif + +mseta5: + mov.l a5a5, r0 + mov.l a5a5, r1 + mov.l a5a5, r2 + mov.l a5a5, r3 + mov.l a5a5, r4 + mov.l a5a5, r5 + mov.l a5a5, r6 + mov.l a5a5, r7 + mov.l a5a5, r8 + mov.l a5a5, r9 + mov.l a5a5, r10 + mov.l a5a5, r11 + mov.l a5a5, r12 + mov.l a5a5, r13 + mov.l a5a5, r14 + rts + nop + +.if (sim_cpu == no_dsp) +mseta5_fp: + push r0 + mov.l a5a5, r0 + lds r0, fpul + fsts fpul, fr0 + fsts fpul, fr1 + fsts fpul, fr2 + fsts fpul, fr3 + fsts fpul, fr4 + fsts fpul, fr5 + fsts fpul, fr6 + fsts fpul, fr7 + fsts fpul, fr8 + fsts fpul, fr9 + fsts fpul, fr10 + fsts fpul, fr11 + fsts fpul, fr12 + fsts fpul, fr13 + fsts fpul, fr14 + fsts fpul, fr15 + pop r0 + rts + nop +.endif + + .align 2 +a5a5: .long 0xa5a5a5a5 +main: + .endm + + .macro exit val + mov #\val, r5 + bra mexit + nop + .endm + + .macro pass + bsr mpass + nop + .endm + + .macro fail + bra mfail + nop + .endm + # Branch if false -- 8k range + .macro bf8k label + bt .Lbf8k\@ + bra \label +.Lbf8k\@: + .endm + + # Branch if true -- 8k range + .macro bt8k label + bf .Lbt8k\@ + bra \label +.Lbt8k\@: + .endm + + # Assert value of register (any general register but r0) + # Preserves r0 on stack, restores it on success. + .macro assertreg val reg + push r0 + mov.l .Larval\@, r0 + cmp/eq r0, \reg + bt .Lar\@ + fail + .align 2 +.Larval\@: + .long \val +.Lar\@: pop r0 + .endm + + # Assert value of register zero + # Preserves r1 on stack, restores it on success. + .macro assertreg0 val + push r1 + mov.l .Lazval\@, r1 + cmp/eq r1, r0 + bt .Laz\@ + fail + .align 2 +.Lazval\@: + .long \val +.Laz\@: pop r1 + .endm + + # Assert value of system register + # [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...] + .macro assert_sreg val reg + push r0 + sts \reg, r0 + assertreg0 \val + pop r0 + .endm + + # Assert value of system register that isn't directly stc-able + # [a1, m0, m1, ...] + .macro assert_sreg2 val reg + push r0 + sts a0, r0 + push r0 + pcopy \reg, a0 + sts a0, r0 + assertreg0 \val + pop r0 + lds r0, a0 + pop r0 + .endm + + # Assert value of control register + # [gbr, vbr, ssr, spc, sgr, dbr, r[0-7]_bank, sr, mod, re, rs, ...] + .macro assert_creg val reg + push r0 + stc \reg, r0 + assertreg0 \val + pop r0 + .endm + + # Assert integer value of fp register + # Preserves r0 on stack, restores it on success + # Assumes single-precision fp mode + .macro assert_fpreg_i val freg + push r0 + ftrc \freg, fpul + sts fpul, r0 + assertreg0 \val + pop r0 + .endm + + # Assert integer value of dp register + # Preserves r0 on stack, restores it on success + # Assumes double-precision fp mode + .macro assert_dpreg_i val dreg + push r0 + ftrc \dreg, fpul + sts fpul, r0 + assertreg0 \val + pop r0 + .endm + + # Assert hex value of fp register + # Preserves r0 on stack, restores it on success + # Assumes single-precision fp mode + .macro assert_fpreg_x val freg + push r0 + flds \freg, fpul + sts fpul, r0 + assertreg0 \val + pop r0 + .endm + + # Set FP bank 0 + # Saves and restores r0 and r1 + .macro bank0 + push r0 + push r1 + mov #32, r1 + shll16 r1 + not r1, r1 + sts fpscr, r0 + and r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP bank 1 + .macro bank1 + push r0 + push r1 + mov #32, r1 + shll16 r1 + sts fpscr, r0 + or r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP 32-bit xfer + .macro sz_32 + push r0 + push r1 + mov #16, r1 + shll16 r1 + not r1, r1 + sts fpscr, r0 + and r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP 64-bit xfer + .macro sz_64 + push r0 + push r1 + mov #16, r1 + shll16 r1 + sts fpscr, r0 + or r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP single precision + .macro single_prec + push r0 + push r1 + mov #8, r1 + shll16 r1 + not r1, r1 + sts fpscr, r0 + and r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP double precision + .macro double_prec + push r0 + push r1 + mov #8, r1 + shll16 r1 + sts fpscr, r0 + or r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + .macro set_carry + sett + .endm + + .macro set_ovf + sett + .endm + + .macro clear_carry + clrt + .endm + + .macro clear_ovf + clrt + .endm + + # sets, clrs + + + .macro set_grs_a5a5 + bsr mseta5 + nop + .endm + + .macro set_greg val greg + mov.l gregval\@, \greg + bra set_greg\@ + nop + .align 2 +gregval\@: .long \val +set_greg\@: + .endm + + .macro set_fprs_a5a5 + bsr mseta5_fp + nop + .endm + + .macro test_grs_a5a5 + bsr mtesta5 + nop + .endm + + .macro test_fprs_a5a5 + bsr mtesta5_fp + nop + .endm + + .macro test_gr_a5a5 reg + assertreg 0xa5a5a5a5 \reg + .endm + + .macro test_fpr_a5a5 reg + assert_fpreg_x 0xa5a5a5a5 \reg + .endm + + .macro test_gr0_a5a5 + assertreg0 0xa5a5a5a5 + .endm + + # Perform a single to double precision floating point conversion. + # Assumes correct settings of fpscr. + .macro _s2d fpr dpr + flds \fpr, fpul + fcnvsd fpul, \dpr + .endm + + # Manipulate the status register + .macro set_sr val + push r0 + mov.l .Lsrval\@, r0 + ldc r0, sr + pop r0 + bra .Lsetsr\@ + nop + .align 2 +.Lsrval\@: + .long \val +.Lsetsr\@: + .endm + + .macro get_sr reg + stc sr, \reg + .endm + + .macro test_sr val + push r0 + get_sr r0 + assertreg0 \val + pop r0 + .endm + + .macro set_sr_bit val + push r0 + push r1 + get_sr r0 + mov.l .Lsrbitval\@, r1 + or r1, r0 + ldc r0, sr + pop r1 + pop r0 + bra .Lsrbit\@ + nop + .align 2 +.Lsrbitval\@: + .long \val +.Lsrbit\@: + .endm + + .macro test_sr_bit_set val + push r0 + push r1 + get_sr r0 + mov.l .Ltsbsval\@, r1 + tst r1, r0 + bf .Ltsbs\@ + fail + .align 2 +.Ltsbsval\@: + .long \val +.Ltsbs\@: + pop r1 + pop r0 + .endm + + .macro test_sr_bit_clear val + push r0 + push r1 + get_sr r0 + mov.l .Ltsbcval\@, r1 + not r0, r0 + tst r1, r0 + bf .Ltsbc\@ + fail + .align 2 +.Ltsbcval\@: + .long \val +.Ltsbc\@: + pop r1 + pop r0 + .endm + + # Set system registers + .macro set_sreg val reg + # [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...] + push r0 + mov.l .Lssrval\@, r0 + lds r0, \reg + pop r0 + bra .Lssr\@ + nop + .align 2 +.Lssrval\@: + .long \val +.Lssr\@: + .endm + + .macro set_sreg2 val reg + # [a1, m0, m1, ...] + push r0 + sts a0, r0 + push r0 + mov.l .Lssr2val\@, r0 + lds r0, a0 + pcopy a0, \reg + pop r0 + lds r0, a0 + pop r0 + bra .Lssr2_\@ + nop + .align 2 +.Lssr2val\@: + .long \val +.Lssr2_\@: + .endm + + + .macro set_creg val reg + # [gbr, vbr, ssr, spc, sgr, dbr... ] + push r0 + mov.l .Lscrval\@, r0 + ldc r0, \reg + pop r0 + bra .Lscr\@ + nop + .align 2 +.Lscrval\@: + .long \val +.Lscr\@: + .endm + + .macro set_dctrue + push r0 + sts dsr, r0 + or #1, r0 + lds r0, dsr + pop r0 + .endm + + .macro set_dcfalse + push r0 + sts dsr, r0 + not r0, r0 + or #1, r0 + not r0, r0 + lds r0, dsr + pop r0 + .endm + + .macro assertmem addr val + push r0 + mov.l .Laddr\@, r0 + mov.l @r0, r0 + assertreg0 \val + bra .Lam\@ + nop + .align 2 +.Laddr\@: + .long \addr +.Lam\@: pop r0 + .endm diff --git a/sim/testsuite/sim/aarch64/ChangeLog b/sim/testsuite/sim/aarch64/ChangeLog deleted file mode 100644 index f4671da..0000000 --- a/sim/testsuite/sim/aarch64/ChangeLog +++ /dev/null @@ -1,83 +0,0 @@ -2017-04-22 Jim Wilson - - * fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align - data. - * sumulh.s: Delete unnecessary data alignment. - * stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp - arguments to match change. - * ldn_multiple.s, stn_multiple.s: New. - -2017-04-08 Jim Wilson - - * fcvtl.s: New. - - * fcmXX.s: New. - -2017-03-25 Jim Wilson - - * adds.s: Add checks for values -2 and 1, where C is not set. - -2017-03-03 Jim Wilson - - * sumov.s: Correct compare test values. - * sumulh.s: New. - -2017-02-25 Jim Wilson - - * sumov.s: New. - - * cnt.s: New. - -2017-02-19 Jim Wilson - - * bit.s: Change cmp immediates to account for addv bug fix. - * cmtst.s, ldn_single.s, stn_single.s: Likewise. - * xtl.s: New. - -2017-02-14 Jim Wilson - - * mla.s: New. - - * bit.s: New. - - * ldn_single.s: New. - * ldnr.s: New. - * stn_single.s: New. - -2017-01-23 Jim Wilson - - * cmtst.s: New. - -2017-01-17 Jim Wilson - - * addv.s: New. - * xtn.s: New. - -2017-01-09 Jim Wilson - - * uzp.s: New. - -2017-01-04 Jim Wilson - - * fcsel.s: New. - * fcvtz.s: New. - * fminnm.s: New. - * mls.s: New. - * mul.s: New. - -2016-12-21 Jim Wilson - - * fcmp.s: New. - -2016-12-13 Jim Wilson - - * testutils.inc (pass): Move .Lpass to start. - (fail): Move .Lfail to start. Return 1 instead of 0. - (start): Moved .Lpass and .Lfail to here. - * adds.s: New. - * fstur.s: New. - * tbnz.s: New. - -2015-11-24 Nick Clifton - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/sim/aarch64/adds.s b/sim/testsuite/sim/aarch64/adds.s deleted file mode 100644 index fdea5a7..0000000 --- a/sim/testsuite/sim/aarch64/adds.s +++ /dev/null @@ -1,98 +0,0 @@ -# mach: aarch64 - -# Check the basic integer compare instructions: adds, adds64, subs, subs64. -# For add, check value pairs 1 and -1 (Z), -1 and -1 (N), 2 and -1 (C), -# and MIN_INT and -1 (V), -# Also check -2 and 1 (not C). -# For sub, negate the second value. - -.include "testutils.inc" - - start - mov w0, #1 - mov w1, #-1 - adds w2, w0, w1 - bne .Lfailure - mov w0, #-1 - mov w1, #-1 - adds w2, w0, w1 - bpl .Lfailure - mov w0, #2 - mov w1, #-1 - adds w2, w0, w1 - bcc .Lfailure - mov w0, #0x80000000 - mov w1, #-1 - adds w2, w0, w1 - bvc .Lfailure - mov w0, #-2 - mov w1, #1 - adds w2, w0, w1 - bcs .Lfailure - - mov x0, #1 - mov x1, #-1 - adds x2, x0, x1 - bne .Lfailure - mov x0, #-1 - mov x1, #-1 - adds x2, x0, x1 - bpl .Lfailure - mov x0, #2 - mov x1, #-1 - adds x2, x0, x1 - bcc .Lfailure - mov x0, #0x8000000000000000 - mov x1, #-1 - adds x2, x0, x1 - bvc .Lfailure - mov x0, #-2 - mov x1, #1 - adds x2, x0, x1 - bcs .Lfailure - - mov w0, #1 - mov w1, #1 - subs w2, w0, w1 - bne .Lfailure - mov w0, #-1 - mov w1, #1 - subs w2, w0, w1 - bpl .Lfailure - mov w0, #2 - mov w1, #1 - subs w2, w0, w1 - bcc .Lfailure - mov w0, #0x80000000 - mov w1, #1 - subs w2, w0, w1 - bvc .Lfailure - mov w0, #-2 - mov w1, #-1 - subs w2, w0, w1 - bcs .Lfailure - - mov x0, #1 - mov x1, #1 - subs x2, x0, x1 - bne .Lfailure - mov x0, #-1 - mov x1, #1 - subs x2, x0, x1 - bpl .Lfailure - mov x0, #2 - mov x1, #1 - subs x2, x0, x1 - bcc .Lfailure - mov x0, #0x8000000000000000 - mov x1, #1 - subs x2, x0, x1 - bvc .Lfailure - mov x0, #-2 - mov x1, #-1 - subs x2, x0, x1 - bcs .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/addv.s b/sim/testsuite/sim/aarch64/addv.s deleted file mode 100644 index 4da8935..0000000 --- a/sim/testsuite/sim/aarch64/addv.s +++ /dev/null @@ -1,50 +0,0 @@ -# mach: aarch64 - -# Check the add across vector instruction: addv. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d - - start - adrp x0, input - ldr q0, [x0, #:lo12:input] - - addv b1, v0.8b - mov x1, v1.d[0] - cmp x1, #36 - bne .Lfailure - - addv b1, v0.16b - mov x1, v1.d[0] - cmp x1, #136 - bne .Lfailure - - addv h1, v0.4h - mov x1, v1.d[0] - mov x2, #5136 - cmp x1, x2 - bne .Lfailure - - addv h1, v0.8h - mov x1, v1.d[0] - mov x2, #18496 - cmp x1, x2 - bne .Lfailure - - addv s1, v0.4s - mov x1, v1.d[0] - mov x2, 8220 - movk x2, 0x2824, lsl 16 - cmp x1, x2 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/allinsn.exp b/sim/testsuite/sim/aarch64/allinsn.exp deleted file mode 100644 index 54d6478..0000000 --- a/sim/testsuite/sim/aarch64/allinsn.exp +++ /dev/null @@ -1,15 +0,0 @@ -# AArch64 simulator testsuite - -if [istarget aarch64*-*] { - # all machines - set all_machs "aarch64" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/aarch64/bit.s b/sim/testsuite/sim/aarch64/bit.s deleted file mode 100644 index 01a1d4e..0000000 --- a/sim/testsuite/sim/aarch64/bit.s +++ /dev/null @@ -1,91 +0,0 @@ -# mach: aarch64 - -# Check the bitwise vector instructions: bif, bit, bsl, eor. - -.include "testutils.inc" - - .data - .align 4 -inputa: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d -inputb: - .word 0x40302010 - .word 0x80706050 - .word 0xc0b0a090 - .word 0x01f0e0d0 -mask: - .word 0xFF00FF00 - .word 0x00FF00FF - .word 0xF0F0F0F0 - .word 0x0F0F0F0F - - start - adrp x0, inputa - ldr q0, [x0, #:lo12:inputa] - adrp x0, inputb - ldr q1, [x0, #:lo12:inputb] - adrp x0, mask - ldr q2, [x0, #:lo12:mask] - - mov v3.8b, v0.8b - bif v3.8b, v1.8b, v2.8b - addv b4, v3.8b - mov x1, v4.d[0] - cmp x1, #50 - bne .Lfailure - - mov v3.16b, v0.16b - bif v3.16b, v1.16b, v2.16b - addv b4, v3.16b - mov x1, v4.d[0] - cmp x1, #252 - bne .Lfailure - - mov v3.8b, v0.8b - bit v3.8b, v1.8b, v2.8b - addv b4, v3.8b - mov x1, v4.d[0] - cmp x1, #50 - bne .Lfailure - - mov v3.16b, v0.16b - bit v3.16b, v1.16b, v2.16b - addv b4, v3.16b - mov x1, v4.d[0] - cmp x1, #13 - bne .Lfailure - - mov v3.8b, v2.8b - bsl v3.8b, v0.8b, v1.8b - addv b4, v3.8b - mov x1, v4.d[0] - cmp x1, #50 - bne .Lfailure - - mov v3.16b, v2.16b - bsl v3.16b, v0.16b, v1.16b - addv b4, v3.16b - mov x1, v4.d[0] - cmp x1, #252 - bne .Lfailure - - mov v3.8b, v0.8b - eor v3.8b, v1.8b, v2.8b - addv b4, v3.8b - mov x1, v4.d[0] - cmp x1, #252 - bne .Lfailure - - mov v3.16b, v0.16b - eor v3.16b, v1.16b, v2.16b - addv b4, v3.16b - mov x1, v4.d[0] - cmp x1, #247 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/cmtst.s b/sim/testsuite/sim/aarch64/cmtst.s deleted file mode 100644 index 7e6a4c3..0000000 --- a/sim/testsuite/sim/aarch64/cmtst.s +++ /dev/null @@ -1,104 +0,0 @@ -# mach: aarch64 - -# Check the vector compare bitwise test instruction: cmtst. - -.include "testutils.inc" - - .data - .align 4 -inputb: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d -inputh: - .word 0x00020001 - .word 0x00040003 - .word 0x00060005 - .word 0x00800007 -inputs: - .word 0x00000001 - .word 0x00000002 - .word 0x00000003 - .word 0x00000004 -inputd: - .word 0x00000001 - .word 0x00000000 - .word 0x00000002 - .word 0x00000000 -inputd2: - .word 0x00000003 - .word 0x00000000 - .word 0x00000004 - .word 0x00000000 - - start - adrp x0, inputb - ldr q0, [x0, #:lo12:inputb] - rev64 v1.16b, v0.16b - - cmtst v2.8b, v0.8b, v1.8b - addv b3, v2.8b - mov x1, v3.d[0] - cmp x1, #0xfa - bne .Lfailure - - cmtst v2.16b, v0.16b, v1.16b - addv b3, v2.16b - mov x1, v3.d[0] - cmp x1, #0xf4 - bne .Lfailure - - adrp x0, inputh - ldr q0, [x0, #:lo12:inputh] - rev64 v1.8h, v0.8h - - cmtst v2.4h, v0.4h, v1.4h - addv h3, v2.4h - mov x1, v3.d[0] - mov x2, #0xfffe - cmp x1, x2 - bne .Lfailure - - cmtst v2.8h, v0.8h, v1.8h - addv h3, v2.8h - mov x1, v3.d[0] - mov x2, #0xfffc - cmp x1, x2 - bne .Lfailure - - adrp x0, inputs - ldr q0, [x0, #:lo12:inputs] - mov v1.d[0], v0.d[1] - mov v1.d[1], v0.d[0] - rev64 v1.4s, v1.4s - - cmtst v2.2s, v0.2s, v1.2s - mov x1, v2.d[0] - mov x2, #0xffffffff00000000 - cmp x1, x2 - bne .Lfailure - - cmtst v2.4s, v0.4s, v1.4s - addv s3, v2.4s - mov x1, v3.d[0] - mov x2, #0xfffffffe - cmp x1, x2 - bne .Lfailure - - adrp x0, inputd - ldr q0, [x0, #:lo12:inputd] - adrp x0, inputd2 - ldr q1, [x0, #:lo12:inputd2] - - cmtst v2.2d, v0.2d, v1.2d - mov x1, v2.d[0] - cmp x1, #-1 - bne .Lfailure - mov x2, v2.d[1] - cmp x2, #0 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/cnt.s b/sim/testsuite/sim/aarch64/cnt.s deleted file mode 100644 index b4be2e3..0000000 --- a/sim/testsuite/sim/aarch64/cnt.s +++ /dev/null @@ -1,33 +0,0 @@ -# mach: aarch64 - -# Check the popcount instruction: cnt. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x0f070605 - .word 0x44332211 - .word 0xff776655 - - start - adrp x0, input - ldr q0, [x0, #:lo12:input] - - cnt v1.8b, v0.8b - addv b2, v1.8b - mov x1, v2.d[0] - cmp x1, #16 - bne .Lfailure - - cnt v1.16b, v0.16b - addv b2, v1.16b - mov x1, v2.d[0] - cmp x1, #48 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/fcmXX.s b/sim/testsuite/sim/aarch64/fcmXX.s deleted file mode 100644 index cc1a2a9..0000000 --- a/sim/testsuite/sim/aarch64/fcmXX.s +++ /dev/null @@ -1,77 +0,0 @@ -# mach: aarch64 - -# Check the FP scalar compare zero instructions: fcmeq, fcmle, fcmlt, fcmge, -# fcmgt. -# Check values -1, 0, and 1. - -.include "testutils.inc" - - start - fmov s0, wzr - fcmeq s1, s0, #0.0 - mov w0, v1.s[0] - cmp w0, #-1 - bne .Lfailure - fmov s0, #-1.0 - fcmeq s1, s0, #0.0 - mov w0, v1.s[0] - cmp w0, #0 - bne .Lfailure - fmov d0, xzr - fcmeq d1, d0, #0.0 - mov x0, v1.d[0] - cmp x0, #-1 - bne .Lfailure - fmov d0, #1.0 - fcmeq d1, d0, #0.0 - mov x0, v1.d[0] - cmp x0, #0 - bne .Lfailure - - fmov s0, #-1.0 - fcmle s1, s0, #0.0 - mov w0, v1.s[0] - cmp w0, #-1 - bne .Lfailure - fmov d0, #-1.0 - fcmle d1, d0, #0.0 - mov x0, v1.d[0] - cmp x0, #-1 - bne .Lfailure - - fmov s0, #-1.0 - fcmlt s1, s0, #0.0 - mov w0, v1.s[0] - cmp w0, #-1 - bne .Lfailure - fmov d0, #-1.0 - fcmlt d1, d0, #0.0 - mov x0, v1.d[0] - cmp x0, #-1 - bne .Lfailure - - fmov s0, #1.0 - fcmge s1, s0, #0.0 - mov w0, v1.s[0] - cmp w0, #-1 - bne .Lfailure - fmov d0, #1.0 - fcmge d1, d0, #0.0 - mov x0, v1.d[0] - cmp x0, #-1 - bne .Lfailure - - fmov s0, #1.0 - fcmgt s1, s0, #0.0 - mov w0, v1.s[0] - cmp w0, #-1 - bne .Lfailure - fmov d0, #1.0 - fcmgt d1, d0, #0.0 - mov x0, v1.d[0] - cmp x0, #-1 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/fcmp.s b/sim/testsuite/sim/aarch64/fcmp.s deleted file mode 100644 index fd826c4..0000000 --- a/sim/testsuite/sim/aarch64/fcmp.s +++ /dev/null @@ -1,146 +0,0 @@ -# mach: aarch64 - -# Check the FP compare instructions: fcmps, fcmpzs, fcmpes, fcmpzes, fcmpd, -# fcmpzd, fcmped, fcmpzed. -# For 1 operand compares, check 0, 1, -1, +Inf, -Inf. -# For 2 operand compares, check 1/1, 1/-2, -1/2, +Inf/+Inf, +Inf/-Inf. -# FIXME: Check for qNaN and sNaN when exception raising support added. - -.include "testutils.inc" - - start - fmov s0, wzr - fcmp s0, #0.0 - bne .Lfailure - fcmpe s0, #0.0 - bne .Lfailure - fmov d0, xzr - fcmp d0, #0.0 - bne .Lfailure - fcmpe d0, #0.0 - bne .Lfailure - - fmov s0, #1.0 - fcmp s0, #0.0 - blo .Lfailure - fcmpe s0, #0.0 - blo .Lfailure - fmov d0, #1.0 - fcmp d0, #0.0 - blo .Lfailure - fcmpe d0, #0.0 - blo .Lfailure - - fmov s0, #-1.0 - fcmp s0, #0.0 - bpl .Lfailure - fcmpe s0, #0.0 - bpl .Lfailure - fmov d0, #-1.0 - fcmp d0, #0.0 - bpl .Lfailure - fcmpe d0, #0.0 - bpl .Lfailure - - fmov s0, #1.0 - fmov s1, wzr - fdiv s0, s0, s1 - fcmp s0, #0.0 - blo .Lfailure - fcmpe s0, #0.0 - blo .Lfailure - fmov d0, #1.0 - fmov d1, xzr - fdiv d0, d0, d1 - fcmp d0, #0.0 - blo .Lfailure - fcmpe d0, #0.0 - blo .Lfailure - - fmov s0, #-1.0 - fmov s1, wzr - fdiv s0, s0, s1 - fcmp s0, #0.0 - bpl .Lfailure - fcmpe s0, #0.0 - bpl .Lfailure - fmov d0, #-1.0 - fmov d1, xzr - fdiv d0, d0, d1 - fcmp d0, #0.0 - bpl .Lfailure - fcmpe d0, #0.0 - bpl .Lfailure - - fmov s0, #1.0 - fmov s1, #1.0 - fcmp s0, s1 - bne .Lfailure - fcmpe s0, s1 - bne .Lfailure - fmov d0, #1.0 - fmov d1, #1.0 - fcmp d0, d1 - bne .Lfailure - fcmpe d0, d1 - bne .Lfailure - - fmov s0, #1.0 - fmov s1, #-2.0 - fcmp s0, s1 - blo .Lfailure - fcmpe s0, s1 - blo .Lfailure - fmov d0, #1.0 - fmov d1, #-2.0 - fcmp d0, d1 - blo .Lfailure - fcmpe d0, d1 - blo .Lfailure - - fmov s0, #-1.0 - fmov s1, #2.0 - fcmp s0, s1 - bpl .Lfailure - fcmpe s0, s1 - bpl .Lfailure - fmov d0, #-1.0 - fmov d1, #2.0 - fcmp d0, d1 - bpl .Lfailure - fcmpe d0, d1 - bpl .Lfailure - - fmov s0, #1.0 - fmov s1, wzr - fdiv s0, s0, s1 - fcmp s0, s0 - bne .Lfailure - fcmpe s0, s0 - bne .Lfailure - fmov s1, #-1.0 - fmov s2, wzr - fdiv s1, s1, s2 - fcmp s0, s1 - blo .Lfailure - fcmpe s0, s1 - blo .Lfailure - - fmov d0, #1.0 - fmov d1, xzr - fdiv d0, d0, d1 - fcmp d0, d0 - bne .Lfailure - fcmpe d0, d0 - bne .Lfailure - fmov d1, #-1.0 - fmov d2, xzr - fdiv d1, d1, d2 - fcmp d0, d1 - blo .Lfailure - fcmpe d0, d1 - blo .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/fcsel.s b/sim/testsuite/sim/aarch64/fcsel.s deleted file mode 100644 index 5b8443c..0000000 --- a/sim/testsuite/sim/aarch64/fcsel.s +++ /dev/null @@ -1,53 +0,0 @@ -# mach: aarch64 - -# Check the FP Conditional Select instruction: fcsel. -# Check 1/1 eq/neg, and 1/2 lt/gt. - -.include "testutils.inc" - - start - fmov s0, #1.0 - fmov s1, #1.0 - fmov s2, #-1.0 - fcmp s0, s1 - fcsel s3, s0, s2, eq - fcmp s3, s0 - bne .Lfailure - fcsel s3, s0, s2, ne - fcmp s3, s2 - bne .Lfailure - - fmov s0, #1.0 - fmov s1, #2.0 - fcmp s0, s1 - fcsel s3, s0, s2, lt - fcmp s3, s0 - bne .Lfailure - fcsel s3, s0, s2, gt - fcmp s3, s2 - bne .Lfailure - - fmov d0, #1.0 - fmov d1, #1.0 - fmov d2, #-1.0 - fcmp d0, d1 - fcsel d3, d0, d2, eq - fcmp d3, d0 - bne .Lfailure - fcsel d3, d0, d2, ne - fcmp d3, d2 - bne .Lfailure - - fmov d0, #1.0 - fmov d1, #2.0 - fcmp d0, d1 - fcsel d3, d0, d2, lt - fcmp d3, d0 - bne .Lfailure - fcsel d3, d0, d2, gt - fcmp d3, d2 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/fcvtl.s b/sim/testsuite/sim/aarch64/fcvtl.s deleted file mode 100644 index 8febc08..0000000 --- a/sim/testsuite/sim/aarch64/fcvtl.s +++ /dev/null @@ -1,59 +0,0 @@ -# mach: aarch64 - -# Check the FP convert to longer precision: fcvtl, fcvtl2. -# Test values 1.5, -1.5, INTMAX, and INT_MIN. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 1069547520 - .word 3217031168 - .word 1325400064 - .word 3472883712 -d1p5: - .word 0 - .word 1073217536 -dm1p5: - .word 0 - .word -1074266112 -dimax: - .word 0 - .word 1105199104 -dimin: - .word 0 - .word -1042284544 - - start - adrp x0, input - add x0, x0, #:lo12:input - ld1 {v0.4s}, [x0] - - fcvtl v1.2d, v0.2s - mov x1, v1.d[0] - adrp x2, d1p5 - ldr x3, [x2, #:lo12:d1p5] - cmp x1, x3 - bne .Lfailure - mov x1, v1.d[1] - adrp x2, dm1p5 - ldr x3, [x2, #:lo12:dm1p5] - cmp x1, x3 - bne .Lfailure - - fcvtl2 v2.2d, v0.4s - mov x1, v2.d[0] - adrp x2, dimax - ldr x3, [x2, #:lo12:dimax] - cmp x1, x3 - bne .Lfailure - mov x1, v2.d[1] - adrp x2, dimin - ldr x3, [x2, #:lo12:dimin] - cmp x1, x3 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/fcvtz.s b/sim/testsuite/sim/aarch64/fcvtz.s deleted file mode 100644 index 311fc2e..0000000 --- a/sim/testsuite/sim/aarch64/fcvtz.s +++ /dev/null @@ -1,203 +0,0 @@ -# mach: aarch64 - -# Check the FP convert to int round toward zero instructions: fcvtszs32, -# fcvtszs, fcvtszd32, fcvtszd, fcvtzu. -# For 32-bit signed convert, test values -1.5, INT_MAX, and INT_MIN. -# For 64-bit signed convert, test values -1.5, LONG_MAX, and LONG_MIN. -# For 32-bit unsigned convert, test values 1.5, INT_MAX, and UINT_MAX. -# For 64-bit unsigned convert, test values 1.5, LONG_MAX, and ULONG_MAX. - - .data - .align 4 -fm1p5: - .word 3217031168 -fimax: - .word 1325400064 -fimin: - .word 3472883712 -flmax: - .word 1593835520 -flmin: - .word 3741319168 -f1p5: - .word 1069547520 -fuimax: - .word 1333788672 -fulmax: - .word 1602224128 - -dm1p5: - .word 0 - .word -1074266112 -dimax: - .word 4290772992 - .word 1105199103 -dimin: - .word 0 - .word -1042284544 -dlmax: - .word 0 - .word 1138753536 -dlmin: - .word 0 - .word -1008730112 -d1p5: - .word 0 - .word 1073217536 -duimax: - .word 4292870144 - .word 1106247679 -dulmax: - .word 0 - .word 1139802112 - -.include "testutils.inc" - - start - adrp x0, fm1p5 - ldr s0, [x0, #:lo12:fm1p5] - fcvtzs w1, s0 - cmp w1, #-1 - bne .Lfailure - adrp x0, fimax - ldr s0, [x0, #:lo12:fimax] - fcvtzs w1, s0 - mov w2, #0x7fffffff - cmp w1, w2 - bne .Lfailure - adrp x0, fimin - ldr s0, [x0, #:lo12:fimin] - fcvtzs w1, s0 - mov w2, #0x80000000 - cmp w1, w2 - bne .Lfailure - - adrp x0, fm1p5 - ldr s0, [x0, #:lo12:fm1p5] - fcvtzs x1, s0 - cmp x1, #-1 - bne .Lfailure - adrp x0, flmax - ldr s0, [x0, #:lo12:flmax] - fcvtzs x1, s0 - mov x2, #0x7fffffffffffffff - cmp x1, x2 - bne .Lfailure - adrp x0, flmin - ldr s0, [x0, #:lo12:flmin] - fcvtzs x1, s0 - mov x2, #0x8000000000000000 - cmp x1, x2 - bne .Lfailure - - adrp x0, dm1p5 - ldr d0, [x0, #:lo12:dm1p5] - fcvtzs w1, d0 - cmp w1, #-1 - bne .Lfailure - adrp x0, dimax - ldr d0, [x0, #:lo12:dimax] - fcvtzs w1, d0 - mov w2, #0x7fffffff - cmp w1, w2 - bne .Lfailure - adrp x0, dimin - ldr d0, [x0, #:lo12:dimin] - fcvtzs w1, d0 - mov w2, #0x80000000 - cmp w1, w2 - bne .Lfailure - - adrp x0, dm1p5 - ldr d0, [x0, #:lo12:dm1p5] - fcvtzs x1, d0 - cmp x1, #-1 - bne .Lfailure - adrp x0, dlmax - ldr d0, [x0, #:lo12:dlmax] - fcvtzs x1, d0 - mov x2, #0x7fffffffffffffff - cmp x1, x2 - bne .Lfailure - adrp x0, dlmin - ldr d0, [x0, #:lo12:dlmin] - fcvtzs x1, d0 - mov x2, #0x8000000000000000 - cmp x1, x2 - bne .Lfailure - - adrp x0, f1p5 - ldr s0, [x0, #:lo12:f1p5] - fcvtzu w1, s0 - cmp w1, #1 - bne .Lfailure - adrp x0, fimax - ldr s0, [x0, #:lo12:fimax] - fcvtzu w1, s0 - mov w2, #0x80000000 - cmp w1, w2 - bne .Lfailure - adrp x0, fuimax - ldr s0, [x0, #:lo12:fuimax] - fcvtzu w1, s0 - mov w2, #0xffffffff - cmp w1, w2 - bne .Lfailure - - adrp x0, f1p5 - ldr s0, [x0, #:lo12:f1p5] - fcvtzu x1, s0 - cmp x1, #1 - bne .Lfailure - adrp x0, flmax - ldr s0, [x0, #:lo12:flmax] - fcvtzu x1, s0 - mov x2, #0x8000000000000000 - cmp x1, x2 - bne .Lfailure - adrp x0, fulmax - ldr s0, [x0, #:lo12:fulmax] - fcvtzu x1, s0 - mov x2, #0xffffffffffffffff - cmp x1, x2 - bne .Lfailure - - adrp x0, d1p5 - ldr d0, [x0, #:lo12:d1p5] - fcvtzu w1, d0 - cmp w1, #1 - bne .Lfailure - adrp x0, dimax - ldr d0, [x0, #:lo12:dimax] - fcvtzu w1, d0 - mov w2, #0x7fffffff - cmp w1, w2 - bne .Lfailure - adrp x0, duimax - ldr d0, [x0, #:lo12:duimax] - fcvtzu w1, d0 - mov w2, #0xffffffff - cmp w1, w2 - bne .Lfailure - - adrp x0, d1p5 - ldr d0, [x0, #:lo12:d1p5] - fcvtzu x1, d0 - cmp x1, #1 - bne .Lfailure - adrp x0, dlmax - ldr d0, [x0, #:lo12:dlmax] - fcvtzu x1, d0 - mov x2, #0x8000000000000000 - cmp x1, x2 - bne .Lfailure - adrp x0, dulmax - ldr d0, [x0, #:lo12:dulmax] - fcvtzu x1, d0 - mov x2, #0xffffffffffffffff - cmp x1, x2 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/fminnm.s b/sim/testsuite/sim/aarch64/fminnm.s deleted file mode 100644 index 43ccd7c..0000000 --- a/sim/testsuite/sim/aarch64/fminnm.s +++ /dev/null @@ -1,82 +0,0 @@ -# mach: aarch64 - -# Check the FP min/max number instructions: fminnm, fmaxnm, dminnm, dmaxnm. -# For min, check 2/1, 1/0, -1/-Inf. -# For max, check 1/2, -1/0, 1/+inf. - -.include "testutils.inc" - - start - fmov s0, #2.0 - fmov s1, #1.0 - fminnm s2, s0, s1 - fcmp s2, s1 - bne .Lfailure - fmov d0, #2.0 - fmov d1, #1.0 - fminnm d2, d0, d1 - fcmp d2, d1 - bne .Lfailure - - fmov s0, #1.0 - fmov s1, wzr - fminnm s2, s0, s1 - fcmp s2, s1 - bne .Lfailure - fmov d0, #1.0 - fmov d1, xzr - fminnm d2, d0, d1 - fcmp d2, d1 - bne .Lfailure - - fmov s0, #-1.0 - fmov s1, wzr - fdiv s1, s0, s1 - fminnm s2, s0, s1 - fcmp s2, s1 - bne .Lfailure - fmov d0, #-1.0 - fmov d1, xzr - fdiv d1, d0, d1 - fminnm d1, d0, d1 - fcmp d0, d0 - bne .Lfailure - - fmov s0, #1.0 - fmov s1, #2.0 - fmaxnm s2, s0, s1 - fcmp s2, s1 - bne .Lfailure - fmov d0, #1.0 - fmov d1, #2.0 - fmaxnm d2, d0, d1 - fcmp d2, d1 - bne .Lfailure - - fmov s0, #-1.0 - fmov s1, wzr - fmaxnm s2, s0, s1 - fcmp s2, s1 - bne .Lfailure - fmov d0, #-1.0 - fmov d1, xzr - fmaxnm d2, d0, d1 - fcmp d2, d1 - bne .Lfailure - - fmov s0, #1.0 - fmov s1, wzr - fdiv s1, s0, s1 - fmaxnm s2, s0, s1 - fcmp s2, s1 - bne .Lfailure - fmov d0, #1.0 - fmov d1, xzr - fdiv d1, d0, d1 - fmaxnm d1, d0, d1 - fcmp d0, d0 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/fstur.s b/sim/testsuite/sim/aarch64/fstur.s deleted file mode 100644 index 80e5c67..0000000 --- a/sim/testsuite/sim/aarch64/fstur.s +++ /dev/null @@ -1,137 +0,0 @@ -# mach: aarch64 - -# Check the FP store unscaled offset instructions: fsturs, fsturd, fsturq. -# Check the values -1, and XXX_MAX, which tests all bits. -# Check with offsets -256 and 255, which tests all bits. -# Also tests the FP load unscaled offset instructions: fldurs, fldurd, fldurq. - -.include "testutils.inc" - - .data - .align 4 -fm1: - .word 3212836864 -fmax: - .word 2139095039 -ftmp: - .word 0 - -dm1: - .word 0 - .word -1074790400 -dmax: - .word 4294967295 - .word 2146435071 -dtmp: - .word 0 - .word 0 - -ldm1: - .word 0 - .word 0 - .word 0 - .word -1073807360 -ldmax: - .word 4294967295 - .word 4294967295 - .word 4294967295 - .word 2147418111 -ldtmp: - .word 0 - .word 0 - .word 0 - .word 0 - - start - adrp x1, ftmp - add x1, x1, :lo12:ftmp - - adrp x0, fm1 - add x0, x0, :lo12:fm1 - sub x5, x0, #255 - sub x6, x1, #255 - movi d2, #0 - ldur s2, [x5, #255] - stur s2, [x6, #255] - ldr w3, [x0] - ldr w4, [x1] - cmp w3, w4 - bne .Lfailure - - adrp x0, fmax - add x0, x0, :lo12:fmax - add x5, x0, #256 - add x6, x1, #256 - movi d2, #0 - ldur s2, [x5, #-256] - stur s2, [x6, #-256] - ldr w3, [x0] - ldr w4, [x1] - cmp w3, w4 - bne .Lfailure - - adrp x1, dtmp - add x1, x1, :lo12:dtmp - - adrp x0, dm1 - add x0, x0, :lo12:dm1 - sub x5, x0, #255 - sub x6, x1, #255 - movi d2, #0 - ldur d2, [x5, #255] - stur d2, [x6, #255] - ldr x3, [x0] - ldr x4, [x1] - cmp x3, x4 - bne .Lfailure - - adrp x0, dmax - add x0, x0, :lo12:dmax - add x5, x0, #256 - add x6, x1, #256 - movi d2, #0 - ldur d2, [x5, #-256] - stur d2, [x6, #-256] - ldr x3, [x0] - ldr x4, [x1] - cmp x3, x4 - bne .Lfailure - - adrp x1, ldtmp - add x1, x1, :lo12:ldtmp - - adrp x0, ldm1 - add x0, x0, :lo12:ldm1 - sub x5, x0, #255 - sub x6, x1, #255 - movi v2.2d, #0 - ldur q2, [x5, #255] - stur q2, [x6, #255] - ldr x3, [x0] - ldr x4, [x1] - cmp x3, x4 - bne .Lfailure - ldr x3, [x0, 8] - ldr x4, [x1, 8] - cmp x3, x4 - bne .Lfailure - - adrp x0, ldmax - add x0, x0, :lo12:ldmax - add x5, x0, #256 - add x6, x1, #256 - movi v2.2d, #0 - ldur q2, [x5, #-256] - stur q2, [x6, #-256] - ldr x3, [x0] - ldr x4, [x1] - cmp x3, x4 - bne .Lfailure - ldr x3, [x0, 8] - ldr x4, [x1, 8] - cmp x3, x4 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/ldn_multiple.s b/sim/testsuite/sim/aarch64/ldn_multiple.s deleted file mode 100644 index 285ef7e..0000000 --- a/sim/testsuite/sim/aarch64/ldn_multiple.s +++ /dev/null @@ -1,136 +0,0 @@ -# mach: aarch64 - -# Check the load multiple structure instructions: ld1, ld2, ld3, ld4. -# Check the addressing modes: no offset, post-index immediate offset, -# post-index register offset. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d - .word 0xfcfdfeff - .word 0xf8f9fafb - .word 0xf4f5f6f7 - .word 0xf0f1f2f3 - - start - adrp x0, input - add x0, x0, :lo12:input - - mov x2, x0 - mov x3, #16 - ld1 {v0.16b}, [x2], 16 - ld1 {v1.8h}, [x2], x3 - addv b4, v0.16b - addv b5, v1.16b - mov x4, v4.d[0] - cmp x4, #136 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #120 - bne .Lfailure - - mov x2, x0 - mov x3, #16 - ld2 {v0.8b, v1.8b}, [x2], x3 - ld2 {v2.4h, v3.4h}, [x2], 16 - addv b4, v0.8b - addv b5, v1.8b - addv b6, v2.8b - addv b7, v3.8b - mov x4, v4.d[0] - cmp x4, #64 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #72 - bne .Lfailure - mov x6, v6.d[0] - cmp x6, #196 - bne .Lfailure - mov x7, v7.d[0] - cmp x7, #180 - bne .Lfailure - - mov x2, x0 - ld3 {v0.2s, v1.2s, v2.2s}, [x2] - addv b4, v0.8b - addv b5, v1.8b - addv b6, v2.8b - mov x4, v4.d[0] - cmp x4, #68 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #16 - bne .Lfailure - mov x6, v6.d[0] - cmp x6, #16 - bne .Lfailure - - mov x2, x0 - ld4 {v0.4h, v1.4h, v2.4h, v3.4h}, [x2] - addv b4, v0.8b - addv b5, v1.8b - addv b6, v2.8b - addv b7, v3.8b - mov x4, v4.d[0] - cmp x4, #0 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #0 - bne .Lfailure - mov x6, v6.d[0] - cmp x6, #0 - bne .Lfailure - mov x7, v7.d[0] - cmp x7, #0 - bne .Lfailure - - mov x2, x0 - ld1 {v0.4s, v1.4s}, [x2] - addv b4, v0.16b - addv b5, v1.16b - mov x4, v4.d[0] - cmp x4, #136 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #120 - bne .Lfailure - - mov x2, x0 - ld1 {v0.1d, v1.1d, v2.1d}, [x2] - addv b4, v0.8b - addv b5, v1.8b - addv b6, v2.8b - mov x4, v4.d[0] - cmp x4, #36 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #100 - bne .Lfailure - mov x6, v6.d[0] - cmp x6, #220 - bne .Lfailure - - mov x2, x0 - ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x2] - addv b4, v0.8b - addv b5, v1.8b - addv b6, v2.8b - mov x4, v4.d[0] - cmp x4, #36 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #100 - bne .Lfailure - mov x6, v6.d[0] - cmp x6, #220 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/ldn_single.s b/sim/testsuite/sim/aarch64/ldn_single.s deleted file mode 100644 index 9681520..0000000 --- a/sim/testsuite/sim/aarch64/ldn_single.s +++ /dev/null @@ -1,102 +0,0 @@ -# mach: aarch64 - -# Check the load single 1-element structure to one lane instructions: -# ld1, ld2, ld3, ld4. -# Check the addressing modes: no offset, post-index immediate offset, -# post-index register offset. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d - .word 0x14131211 - .word 0x18171615 - .word 0x1c1b1a19 - .word 0x201f1e1d - - start - adrp x0, input - add x0, x0, :lo12:input - - mov x2, x0 - mov x3, #1 - mov x4, #4 - ld1 {v0.b}[0], [x2], 1 - ld1 {v0.b}[1], [x2], x3 - ld1 {v0.h}[1], [x2], 2 - ld1 {v0.s}[1], [x2], x4 - ld1 {v0.d}[1], [x2] - addv b1, v0.16b - mov x5, v1.d[0] - cmp x5, #136 - bne .Lfailure - - mov x2, x0 - mov x3, #16 - mov x4, #4 - ld2 {v0.d, v1.d}[0], [x2], x3 - ld2 {v0.s, v1.s}[2], [x2], 8 - ld2 {v0.h, v1.h}[6], [x2], x4 - ld2 {v0.b, v1.b}[14], [x2], 2 - ld2 {v0.b, v1.b}[15], [x2] - addv b2, v0.16b - addv b3, v1.16b - mov x5, v2.d[0] - mov x6, v3.d[0] - cmp x5, #221 - bne .Lfailure - cmp x6, #51 - bne .Lfailure - - mov x2, x0 - ld3 {v0.s, v1.s, v2.s}[0], [x2], 12 - ld3 {v0.s, v1.s, v2.s}[1], [x2] - mov x2, x0 - mov x3, #12 - ld3 {v0.s, v1.s, v2.s}[2], [x2], x3 - ld3 {v0.s, v1.s, v2.s}[3], [x2] - addv b3, v0.16b - addv b4, v1.16b - addv b5, v2.16b - mov x4, v3.d[0] - mov x5, v4.d[0] - mov x6, v5.d[0] - cmp x4, #136 - bne .Lfailure - cmp x5, #200 - bne .Lfailure - cmp x6, #8 - bne .Lfailure - - mov x2, x0 - ld4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16 - ld4 {v0.s, v1.s, v2.s, v3.s}[1], [x2] - mov x2, x0 - mov x3, #16 - ld4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], x3 - ld4 {v0.s, v1.s, v2.s, v3.s}[3], [x2] - addv b4, v0.16b - addv b5, v1.16b - addv b6, v2.16b - addv b7, v3.16b - mov x4, v4.d[0] - mov x5, v5.d[0] - mov x6, v6.d[0] - mov x7, v7.d[0] - cmp x4, #168 - bne .Lfailure - cmp x5, #232 - bne .Lfailure - cmp x6, #40 - bne .Lfailure - cmp x7, #104 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/ldnr.s b/sim/testsuite/sim/aarch64/ldnr.s deleted file mode 100644 index 7126c46..0000000 --- a/sim/testsuite/sim/aarch64/ldnr.s +++ /dev/null @@ -1,178 +0,0 @@ -# mach: aarch64 - -# Check the load single 1-element structure and replicate to all lanes insns: -# ld1r, ld2r, ld3r, ld4r. -# Check the addressing modes: no offset, post-index immediate offset, -# post-index register offset. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d -input2: - .word 0x00000001 - .word 0x00000002 - .word 0x00000003 - .word 0x00000004 - .word 0x00000005 - .word 0x00000006 - .word 0x00000007 - .word 0x00000008 - .word 0x00000009 - .word 0x0000000a - .word 0x0000000b - .word 0x0000000c - - start - adrp x0, input - add x0, x0, :lo12:input - adrp x1, input2 - add x1, x1, :lo12:input2 - - mov x2, x0 - mov x3, #1 - ld1r {v0.8b}, [x2], 1 - ld1r {v1.16b}, [x2], x3 - ld1r {v2.4h}, [x2], 2 - ld1r {v3.8h}, [x2] - addv b0, v0.8b - addv b1, v1.16b - addv b2, v2.8b - addv b3, v3.16b - mov x2, v0.d[0] - mov x3, v1.d[0] - mov x4, v2.d[0] - mov x5, v3.d[0] - cmp x2, #8 - bne .Lfailure - cmp x3, #32 - bne .Lfailure - cmp x4, #28 - bne .Lfailure - cmp x5, #88 - bne .Lfailure - - mov x2, x1 - mov x3, #8 - ld2r {v0.2s, v1.2s}, [x2], 8 - ld2r {v2.4s, v3.4s}, [x2], x3 - ld2r {v4.1d, v5.1d}, [x2], 16 - ld2r {v6.2d, v7.2d}, [x2] - addp v0.2s, v0.2s, v1.2s - addv s2, v2.4s - addv s3, v3.4s - addp v4.2s, v4.2s, v5.2s - addv s6, v6.4s - addv s7, v7.4s - mov w2, v0.s[0] - mov w3, v0.s[1] - mov x4, v2.d[0] - mov x5, v3.d[0] - mov w6, v4.s[0] - mov w7, v4.s[1] - mov x8, v6.d[0] - mov x9, v7.d[0] - cmp w2, #2 - bne .Lfailure - cmp w3, #4 - bne .Lfailure - cmp x4, #12 - bne .Lfailure - cmp x5, #16 - bne .Lfailure - cmp w6, #11 - bne .Lfailure - cmp w7, #15 - bne .Lfailure - cmp x8, #38 - bne .Lfailure - cmp x9, #46 - bne .Lfailure - - mov x2, x0 - mov x3, #3 - ld3r {v0.8b, v1.8b, v2.8b}, [x2], 3 - ld3r {v3.8b, v4.8b, v5.8b}, [x2], x3 - ld3r {v6.8b, v7.8b, v8.8b}, [x2] - addv b0, v0.8b - addv b1, v1.8b - addv b2, v2.8b - addv b3, v3.8b - addv b4, v4.8b - addv b5, v5.8b - addv b6, v6.8b - addv b7, v7.8b - addv b8, v8.8b - addv b9, v9.8b - mov x2, v0.d[0] - mov x3, v1.d[0] - mov x4, v2.d[0] - mov x5, v3.d[0] - mov x6, v4.d[0] - mov x7, v5.d[0] - mov x8, v6.d[0] - mov x9, v7.d[0] - mov x10, v8.d[0] - cmp x2, #8 - bne .Lfailure - cmp x3, #16 - bne .Lfailure - cmp x4, #24 - bne .Lfailure - cmp x5, #32 - bne .Lfailure - cmp x6, #40 - bne .Lfailure - cmp x7, #48 - bne .Lfailure - cmp x8, #56 - bne .Lfailure - cmp x9, #64 - bne .Lfailure - cmp x10, #72 - bne .Lfailure - - mov x2, x1 - ld4r {v0.4s, v1.4s, v2.4s, v3.4s}, [x2], 16 - ld4r {v4.4s, v5.4s, v6.4s, v7.4s}, [x2] - addv s0, v0.4s - addv s1, v1.4s - addv s2, v2.4s - addv s3, v3.4s - addv s4, v4.4s - addv s5, v5.4s - addv s6, v6.4s - addv s7, v7.4s - mov x2, v0.d[0] - mov x3, v1.d[0] - mov x4, v2.d[0] - mov x5, v3.d[0] - mov x6, v4.d[0] - mov x7, v5.d[0] - mov x8, v6.d[0] - mov x9, v7.d[0] - cmp x2, #4 - bne .Lfailure - cmp x3, #8 - bne .Lfailure - cmp x4, #12 - bne .Lfailure - cmp x5, #16 - bne .Lfailure - cmp x6, #20 - bne .Lfailure - cmp x7, #24 - bne .Lfailure - cmp x8, #28 - bne .Lfailure - cmp x9, #32 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/mla.s b/sim/testsuite/sim/aarch64/mla.s deleted file mode 100644 index e3ea836..0000000 --- a/sim/testsuite/sim/aarch64/mla.s +++ /dev/null @@ -1,105 +0,0 @@ -# mach: aarch64 - -# Check the vector multiply add instruction: mla. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d -m8b: - .word 0x110a0502 - .word 0x4132251a -m16b: - .word 0x110a0502 - .word 0x4132251a - .word 0x917a6552 - .word 0x01e2c5aa -m4h: - .word 0x180a0402 - .word 0x70323c1a -m8h: - .word 0x180a0402 - .word 0x70323c1a - .word 0x087ab452 - .word 0xe0e26caa -m2s: - .word 0x140a0402 - .word 0xa46a3c1a -m4s: - .word 0x140a0402 - .word 0xa46a3c1a - .word 0xb52ab452 - .word 0x464b6caa - - start - adrp x0, input - ldr q0, [x0, #:lo12:input] - - movi v1.8b, #1 - mla v1.8b, v0.8b, v0.8b - mov x1, v1.d[0] - adrp x3, m8b - ldr x4, [x3, #:lo12:m8b] - cmp x1, x4 - bne .Lfailure - - movi v1.16b, #1 - mla v1.16b, v0.16b, v0.16b - mov x1, v1.d[0] - mov x2, v1.d[1] - adrp x3, m16b - ldr x4, [x3, #:lo12:m16b] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:m16b+8] - cmp x2, x5 - bne .Lfailure - - movi v1.4h, #1 - mla v1.4h, v0.4h, v0.4h - mov x1, v1.d[0] - adrp x3, m4h - ldr x4, [x3, #:lo12:m4h] - cmp x1, x4 - bne .Lfailure - - movi v1.8h, #1 - mla v1.8h, v0.8h, v0.8h - mov x1, v1.d[0] - mov x2, v1.d[1] - adrp x3, m8h - ldr x4, [x3, #:lo12:m8h] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:m8h+8] - cmp x2, x5 - bne .Lfailure - - movi v1.2s, #1 - mla v1.2s, v0.2s, v0.2s - mov x1, v1.d[0] - adrp x3, m2s - ldr x4, [x3, #:lo12:m2s] - cmp x1, x4 - bne .Lfailure - - movi v1.4s, #1 - mla v1.4s, v0.4s, v0.4s - mov x1, v1.d[0] - mov x2, v1.d[1] - adrp x3, m4s - ldr x4, [x3, #:lo12:m4s] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:m4s+8] - cmp x2, x5 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/mls.s b/sim/testsuite/sim/aarch64/mls.s deleted file mode 100644 index 5c9e225..0000000 --- a/sim/testsuite/sim/aarch64/mls.s +++ /dev/null @@ -1,105 +0,0 @@ -# mach: aarch64 - -# Check the vector multiply subtract instruction: mls. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d -m8b: - .word 0xf1f8fd00 - .word 0xc1d0dde8 -m16b: - .word 0xf1f8fd00 - .word 0xc1d0dde8 - .word 0x71889db0 - .word 0x01203d58 -m4h: - .word 0xe7f8fc00 - .word 0x8fd0c3e8 -m8h: - .word 0xe7f8fc00 - .word 0x8fd0c3e8 - .word 0xf7884bb0 - .word 0x1f209358 -m2s: - .word 0xebf5fc00 - .word 0x5b95c3e8 -m4s: - .word 0xebf5fc00 - .word 0x5b95c3e8 - .word 0x4ad54bb0 - .word 0xb9b49358 - - start - adrp x0, input - ldr q0, [x0, #:lo12:input] - - movi v1.8b, #1 - mls v1.8b, v0.8b, v0.8b - mov x1, v1.d[0] - adrp x3, m8b - ldr x4, [x3, #:lo12:m8b] - cmp x1, x4 - bne .Lfailure - - movi v1.16b, #1 - mls v1.16b, v0.16b, v0.16b - mov x1, v1.d[0] - mov x2, v1.d[1] - adrp x3, m16b - ldr x4, [x3, #:lo12:m16b] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:m16b+8] - cmp x2, x5 - bne .Lfailure - - movi v1.4h, #1 - mls v1.4h, v0.4h, v0.4h - mov x1, v1.d[0] - adrp x3, m4h - ldr x4, [x3, #:lo12:m4h] - cmp x1, x4 - bne .Lfailure - - movi v1.8h, #1 - mls v1.8h, v0.8h, v0.8h - mov x1, v1.d[0] - mov x2, v1.d[1] - adrp x3, m8h - ldr x4, [x3, #:lo12:m8h] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:m8h+8] - cmp x2, x5 - bne .Lfailure - - movi v1.2s, #1 - mls v1.2s, v0.2s, v0.2s - mov x1, v1.d[0] - adrp x3, m2s - ldr x4, [x3, #:lo12:m2s] - cmp x1, x4 - bne .Lfailure - - movi v1.4s, #1 - mls v1.4s, v0.4s, v0.4s - mov x1, v1.d[0] - mov x2, v1.d[1] - adrp x3, m4s - ldr x4, [x3, #:lo12:m4s] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:m4s+8] - cmp x2, x5 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/mul.s b/sim/testsuite/sim/aarch64/mul.s deleted file mode 100644 index 783dba7..0000000 --- a/sim/testsuite/sim/aarch64/mul.s +++ /dev/null @@ -1,99 +0,0 @@ -# mach: aarch64 - -# Check the non-widening multiply vector instruction: mul. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d -m8b: - .word 0x10090401 - .word 0x40312419 -m16b: - .word 0x10090401 - .word 0x40312419 - .word 0x90796451 - .word 0x00e1c4a9 -m4h: - .word 0x18090401 - .word 0x70313c19 -m8h: - .word 0x18090401 - .word 0x70313c19 - .word 0x0879b451 - .word 0xe0e16ca9 -m2s: - .word 0x140a0401 - .word 0xa46a3c19 -m4s: - .word 0x140a0401 - .word 0xa46a3c19 - .word 0xb52ab451 - .word 0x464b6ca9 - - start - adrp x0, input - ldr q0, [x0, #:lo12:input] - - mul v1.8b, v0.8b, v0.8b - mov x1, v1.d[0] - adrp x3, m8b - ldr x4, [x0, #:lo12:m8b] - cmp x1, x4 - bne .Lfailure - - mul v1.16b, v0.16b, v0.16b - mov x1, v1.d[0] - mov x2, v1.d[1] - adrp x3, m16b - ldr x4, [x0, #:lo12:m16b] - cmp x1, x4 - bne .Lfailure - ldr x5, [x0, #:lo12:m16b+8] - cmp x2, x5 - bne .Lfailure - - mul v1.4h, v0.4h, v0.4h - mov x1, v1.d[0] - adrp x3, m4h - ldr x4, [x0, #:lo12:m4h] - cmp x1, x4 - bne .Lfailure - - mul v1.8h, v0.8h, v0.8h - mov x1, v1.d[0] - mov x2, v1.d[1] - adrp x3, m8h - ldr x4, [x0, #:lo12:m8h] - cmp x1, x4 - bne .Lfailure - ldr x5, [x0, #:lo12:m8h+8] - cmp x2, x5 - bne .Lfailure - - mul v1.2s, v0.2s, v0.2s - mov x1, v1.d[0] - adrp x3, m2s - ldr x4, [x0, #:lo12:m2s] - cmp x1, x4 - bne .Lfailure - - mul v1.4s, v0.4s, v0.4s - mov x1, v1.d[0] - mov x2, v1.d[1] - adrp x3, m4s - ldr x4, [x0, #:lo12:m4s] - cmp x1, x4 - bne .Lfailure - ldr x5, [x0, #:lo12:m4s+8] - cmp x2, x5 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/pass.s b/sim/testsuite/sim/aarch64/pass.s deleted file mode 100644 index 7ce7de5..0000000 --- a/sim/testsuite/sim/aarch64/pass.s +++ /dev/null @@ -1,7 +0,0 @@ -# check that the sim doesn't die immediately. -# mach: aarch64 - -.include "testutils.inc" - - start - pass diff --git a/sim/testsuite/sim/aarch64/stn_multiple.s b/sim/testsuite/sim/aarch64/stn_multiple.s deleted file mode 100644 index 1a3f24d..0000000 --- a/sim/testsuite/sim/aarch64/stn_multiple.s +++ /dev/null @@ -1,171 +0,0 @@ -# mach: aarch64 - -# Check the store multiple structure instructions: st1, st2, st3, st4. -# Check the addressing modes: no offset, post-index immediate offset, -# post-index register offset. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d - .word 0xfcfdfeff - .word 0xf8f9fafb - .word 0xf4f5f6f7 - .word 0xf0f1f2f3 -output: - .zero 64 - - start - adrp x0, input - add x0, x0, :lo12:input - adrp x1, output - add x1, x1, :lo12:output - - mov x2, x0 - ldr q0, [x2], 16 - ldr q1, [x2] - mov x2, x0 - ldr q2, [x2], 16 - ldr q3, [x2] - - mov x2, x1 - mov x3, #16 - st1 {v0.16b}, [x2], 16 - st1 {v1.8h}, [x2], x3 - mov x2, x1 - ldr q4, [x2], 16 - ldr q5, [x2] - addv b4, v4.16b - addv b5, v5.16b - mov x4, v4.d[0] - cmp x4, #136 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #120 - bne .Lfailure - - mov x2, x1 - mov x3, #16 - st2 {v0.8b, v1.8b}, [x2], 16 - st2 {v2.4h, v3.4h}, [x2], x3 - mov x2, x1 - ldr q4, [x2], 16 - ldr q5, [x2] - addv b4, v4.16b - addv b5, v5.16b - mov x4, v4.d[0] - cmp x4, #0 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #0 - bne .Lfailure - - mov x2, x1 - st3 {v0.4s, v1.4s, v2.4s}, [x2] - ldr q4, [x2], 16 - ldr q5, [x2], 16 - ldr q6, [x2] - addv b4, v4.16b - addv b5, v5.16b - addv b6, v6.16b - mov x4, v4.d[0] - cmp x4, #36 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #0 - bne .Lfailure - mov x6, v6.d[0] - cmp x6, #100 - bne .Lfailure - - mov x2, x1 - st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x2] - ldr q4, [x2], 16 - ldr q5, [x2], 16 - ldr q6, [x2], 16 - ldr q7, [x2] - addv b4, v4.16b - addv b5, v5.16b - addv b6, v6.16b - addv b7, v7.16b - mov x4, v4.d[0] - cmp x4, #0 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #0 - bne .Lfailure - mov x6, v6.d[0] - cmp x6, #0 - bne .Lfailure - mov x7, v7.d[0] - cmp x7, #0 - bne .Lfailure - - pass - - mov x2, x1 - st1 {v0.2s, v1.2s}, [x2], 16 - st1 {v2.1d, v3.1d}, [x2] - mov x2, x1 - ldr q4, [x2], 16 - ldr q5, [x2] - addv b4, v4.16b - addv b5, v5.16b - mov x4, v4.d[0] - cmp x4, #0 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #0 - bne .Lfailure - - mov x2, x1 - st1 {v0.2d, v1.2d, v2.2d}, [x2] - mov x2, x1 - ldr q4, [x2], 16 - ldr q5, [x2], 16 - ldr q6, [x2] - addv b4, v4.16b - addv b5, v5.16b - addv b6, v6.16b - mov x4, v4.d[0] - cmp x4, #136 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #120 - bne .Lfailure - mov x6, v6.d[0] - cmp x6, #136 - bne .Lfailure - - mov x2, x1 - st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x2] - mov x2, x1 - ldr q4, [x2], 16 - ldr q5, [x2], 16 - ldr q6, [x2], 16 - ldr q7, [x2] - addv b4, v4.16b - addv b5, v5.16b - addv b6, v6.16b - addv b7, v7.16b - mov x4, v4.d[0] - cmp x4, #136 - bne .Lfailure - mov x5, v5.d[0] - cmp x5, #120 - bne .Lfailure - mov x6, v6.d[0] - cmp x6, #136 - bne .Lfailure - mov x7, v7.d[0] - cmp x7, #120 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/stn_single.s b/sim/testsuite/sim/aarch64/stn_single.s deleted file mode 100644 index a24b084..0000000 --- a/sim/testsuite/sim/aarch64/stn_single.s +++ /dev/null @@ -1,124 +0,0 @@ -# mach: aarch64 - -# Check the store single 1-element structure to one lane instructions: -# st1, st2, st3, st4. -# Check the addressing modes: no offset, post-index immediate offset, -# post-index register offset. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d - .word 0x14131211 - .word 0x18171615 - .word 0x1c1b1a19 - .word 0x201f1e1d -output: - .zero 64 - - start - adrp x0, input - add x0, x0, :lo12:input - adrp x1, output - add x1, x1, :lo12:output - - mov x2, x0 - ldr q0, [x2], 16 - ldr q1, [x2] - mov x2, x0 - ldr q2, [x2], 16 - ldr q3, [x2] - - mov x2, x1 - mov x3, #1 - mov x4, #4 - st1 {v0.b}[0], [x2], 1 - st1 {v0.b}[1], [x2], x3 - st1 {v0.h}[1], [x2], 2 - st1 {v0.s}[1], [x2], x4 - st1 {v0.d}[1], [x2] - ldr q4, [x1] - addv b4, v4.16b - mov x5, v4.d[0] - cmp x5, #136 - bne .Lfailure - - mov x2, x1 - mov x3, #16 - mov x4, #4 - st2 {v0.d, v1.d}[0], [x2], x3 - st2 {v0.s, v1.s}[2], [x2], 8 - st2 {v0.h, v1.h}[6], [x2], x4 - st2 {v0.b, v1.b}[14], [x2], 2 - st2 {v0.b, v1.b}[15], [x2] - mov x2, x1 - ldr q4, [x2], 16 - ldr q5, [x2] - addv b4, v4.16b - addv b5, v5.16b - mov x5, v4.d[0] - mov x6, v5.d[0] - cmp x5, #200 - bne .Lfailure - cmp x6, #72 - bne .Lfailure - - mov x2, x1 - mov x3, #12 - st3 {v0.s, v1.s, v2.s}[0], [x2], 12 - st3 {v0.s, v1.s, v2.s}[1], [x2], x3 - st3 {v0.s, v1.s, v2.s}[2], [x2], 12 - st3 {v0.s, v1.s, v2.s}[3], [x2] - mov x2, x1 - ldr q4, [x2], 16 - ldr q5, [x2], 16 - ldr q6, [x2] - addv b4, v4.16b - addv b5, v5.16b - addv b6, v6.16b - mov x4, v4.d[0] - mov x5, v5.d[0] - mov x6, v6.d[0] - cmp x4, #120 - bne .Lfailure - cmp x5, #8 - bne .Lfailure - cmp x6, #24 - bne .Lfailure - - mov x2, x1 - mov x3, #16 - st4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16 - st4 {v0.s, v1.s, v2.s, v3.s}[1], [x2], x3 - st4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], 16 - st4 {v0.s, v1.s, v2.s, v3.s}[3], [x2] - mov x2, x1 - ldr q4, [x2], 16 - ldr q5, [x2], 16 - ldr q6, [x2], 16 - ldr q7, [x2] - addv b4, v4.16b - addv b5, v5.16b - addv b6, v6.16b - addv b7, v7.16b - mov x4, v4.d[0] - mov x5, v5.d[0] - mov x6, v6.d[0] - mov x7, v7.d[0] - cmp x4, #168 - bne .Lfailure - cmp x5, #232 - bne .Lfailure - cmp x6, #40 - bne .Lfailure - cmp x7, #104 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/sumov.s b/sim/testsuite/sim/aarch64/sumov.s deleted file mode 100644 index 7180c6a..0000000 --- a/sim/testsuite/sim/aarch64/sumov.s +++ /dev/null @@ -1,93 +0,0 @@ -# mach: aarch64 - -# Check the mov from asimd to general reg instructions: smov, umov. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x08070605 - .word 0xf4f3f2f1 - .word 0xf8f7f6f5 - - start - adrp x0, input - ldr q0, [x0, #:lo12:input] - - smov w0, v0.b[0] - smov w3, v0.b[12] - cmp w0, #1 - bne .Lfailure - cmp w3, #-11 - bne .Lfailure - - smov x0, v0.b[1] - smov x3, v0.b[13] - cmp x0, #2 - bne .Lfailure - cmp x3, #-10 - bne .Lfailure - - smov w0, v0.h[0] - smov w1, v0.h[4] - cmp w0, #0x0201 - bne .Lfailure - cmp w1, #-3343 - bne .Lfailure - - smov x0, v0.h[1] - smov x1, v0.h[5] - cmp x0, #0x0403 - bne .Lfailure - cmp x1, #-2829 - bne .Lfailure - - smov x0, v0.s[1] - smov x1, v0.s[3] - mov x2, #0x0605 - movk x2, #0x0807, lsl #16 - cmp x0, x2 - bne .Lfailure - mov w3, #0xf6f5 - movk w3, #0xf8f7, lsl #16 - sxtw x3, w3 - cmp x1, x3 - bne .Lfailure - - umov w0, v0.b[0] - umov w3, v0.b[12] - cmp w0, #1 - bne .Lfailure - cmp w3, #0xf5 - bne .Lfailure - - umov w0, v0.h[0] - umov w1, v0.h[4] - cmp w0, #0x0201 - bne .Lfailure - mov w2, #0xf2f1 - cmp w1, w2 - bne .Lfailure - - umov w0, v0.s[0] - umov w1, v0.s[2] - mov w2, #0x0201 - movk w2, #0x0403, lsl #16 - cmp w0, w2 - bne .Lfailure - mov w3, #0xf2f1 - movk w3, #0xf4f3, lsl #16 - cmp w1, w3 - bne .Lfailure - - umov x0, v0.d[0] - adrp x1, input - ldr x2, [x1, #:lo12:input] - cmp x0, x2 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/sumulh.s b/sim/testsuite/sim/aarch64/sumulh.s deleted file mode 100644 index d75e0c6..0000000 --- a/sim/testsuite/sim/aarch64/sumulh.s +++ /dev/null @@ -1,53 +0,0 @@ -# mach: aarch64 - -# Check the multiply highpart instructions: smulh, umulh. - -# Test -2*2, -1<<32*-1<<32, -2*-2, and 2*2. - -.include "testutils.inc" - - start - - mov x0, #-2 - mov x1, #2 - smulh x2, x0, x1 - cmp x2, #-1 - bne .Lfailure - umulh x3, x0, x1 - cmp x3, #1 - bne .Lfailure - - mov w0, #-1 - lsl x0, x0, #32 // 0xffffffff00000000 - mov x1, x0 - smulh x2, x0, x1 - cmp x2, #1 - bne .Lfailure - umulh x3, x0, x1 - mov w4, #-2 - lsl x4, x4, #32 - add x4, x4, #1 // 0xfffffffe00000001 - cmp x3, x4 - bne .Lfailure - - mov x0, #-2 - mov x1, #-2 - smulh x2, x0, x1 - cmp x2, #0 - bne .Lfailure - umulh x3, x0, x1 - cmp x3, #-4 - bne .Lfailure - - mov x0, #2 - mov x1, #2 - smulh x2, x0, x1 - cmp x2, #0 - bne .Lfailure - umulh x3, x0, x1 - cmp x3, #0 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/tbnz.s b/sim/testsuite/sim/aarch64/tbnz.s deleted file mode 100644 index 2416101..0000000 --- a/sim/testsuite/sim/aarch64/tbnz.s +++ /dev/null @@ -1,55 +0,0 @@ -# mach: aarch64 - -# Check the test-bit-and-branch instructions: tbnz, and tbz. -# We check the edge condition bit positions: 0, 1<<31, 1<<32, 1<<63. - -.include "testutils.inc" - - start - mov x0, #1 - tbnz x0, #0, .L1 - fail -.L1: - tbz x0, #0, .Lfailure - mov x0, #0xFFFFFFFFFFFFFFFE - tbnz x0, #0, .Lfailure - tbz x0, #0, .L2 - fail -.L2: - - mov x0, #0x80000000 - tbnz x0, #31, .L3 - fail -.L3: - tbz x0, #31, .Lfailure - mov x0, #0xFFFFFFFF7FFFFFFF - tbnz x0, #31, .Lfailure - tbz x0, #31, .L4 - fail -.L4: - - mov x0, #0x100000000 - tbnz x0, #32, .L5 - fail -.L5: - tbz x0, #32, .Lfailure - mov x0, #0xFFFFFFFEFFFFFFFF - tbnz x0, #32, .Lfailure - tbz x0, #32, .L6 - fail -.L6: - - mov x0, #0x8000000000000000 - tbnz x0, #63, .L7 - fail -.L7: - tbz x0, #63, .Lfailure - mov x0, #0x7FFFFFFFFFFFFFFF - tbnz x0, #63, .Lfailure - tbz x0, #63, .L8 - fail -.L8: - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/testutils.inc b/sim/testsuite/sim/aarch64/testutils.inc deleted file mode 100644 index 1fc9bc8..0000000 --- a/sim/testsuite/sim/aarch64/testutils.inc +++ /dev/null @@ -1,70 +0,0 @@ -# MACRO: exit -# Terminates execution. - .macro exit nr - - stp x29, x30, [sp,#-32]! - mov x4, #0x26 - mov x7, #\nr - mov x29, sp - movk x4, #0x2, lsl #16 - add x1, x29, #0x10 - str x4, [x29,#16] - str x7, [x29,#24] - mov w0, #0x18 - hlt #0xf000 - - .endm - -# MACRO: swiwrite -# Writes the string in X1 to stdout - .macro swiwrite len - - stp x29, x30, [sp,#-48]! - mov x0, #1 - mov x2, #\len - mov x29, sp - str x0, [x29,#24] - str x1, [x29,#32] - str x2, [x29,#40] - mov w0, #0x5 - add x1, x29, #0x18 - hlt #0xf000 - ldp x29, x30, [sp],#48 - ret - - .endm - -# MACRO: pass -# Write 'pass' to stdout and quit - .macro pass - - adrp x1, .Lpass - add x1, x1, :lo12:.Lpass - - swiwrite 5 - exit 0 - .endm - -# MACRO: fail -# Write 'fail' to stdout and quit - .macro fail - - adrp x1, .Lfail - add x1, x1, :lo12:.Lfail - swiwrite 5 - exit 1 - .endm - -# MACRO: start -# All assembler tests should start with a call to "start" - .macro start - .data -.Lpass: - .asciz "pass\n" -.Lfail: - .asciz "fail\n" - - .text -.global _start -_start: - .endm diff --git a/sim/testsuite/sim/aarch64/uzp.s b/sim/testsuite/sim/aarch64/uzp.s deleted file mode 100644 index 851005e..0000000 --- a/sim/testsuite/sim/aarch64/uzp.s +++ /dev/null @@ -1,216 +0,0 @@ -# mach: aarch64 - -# Check the unzip instructions: uzp1, uzp2. - -.include "testutils.inc" - - .data - .align 4 -input1: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d -input2: - .word 0x14131211 - .word 0x18171615 - .word 0x1c1b1a19 - .word 0x201f1e1d -zl8b: - .word 0x07050301 - .word 0x17151311 -zu8b: - .word 0x08060402 - .word 0x18161412 -zl16b: - .word 0x07050301 - .word 0x0f0d0b09 - .word 0x17151311 - .word 0x1f1d1b19 -zu16b: - .word 0x08060402 - .word 0x100e0c0a - .word 0x18161412 - .word 0x201e1c1a -zl4h: - .word 0x06050201 - .word 0x16151211 -zu4h: - .word 0x08070403 - .word 0x18171413 -zl8h: - .word 0x06050201 - .word 0x0e0d0a09 - .word 0x16151211 - .word 0x1e1d1a19 -zu8h: - .word 0x08070403 - .word 0x100f0c0b - .word 0x18171413 - .word 0x201f1c1b -zl2s: - .word 0x04030201 - .word 0x14131211 -zu2s: - .word 0x08070605 - .word 0x18171615 -zl4s: - .word 0x04030201 - .word 0x0c0b0a09 - .word 0x14131211 - .word 0x1c1b1a19 -zu4s: - .word 0x08070605 - .word 0x100f0e0d - .word 0x18171615 - .word 0x201f1e1d -zl2d: - .word 0x04030201 - .word 0x08070605 - .word 0x14131211 - .word 0x18171615 -zu2d: - .word 0x0c0b0a09 - .word 0x100f0e0d - .word 0x1c1b1a19 - .word 0x201f1e1d - - start - adrp x0, input1 - ldr q0, [x0, #:lo12:input1] - adrp x0, input2 - ldr q1, [x0, #:lo12:input2] - - uzp1 v2.8b, v0.8b, v1.8b - mov x1, v2.d[0] - adrp x3, zl8b - ldr x4, [x3, #:lo12:zl8b] - cmp x1, x4 - bne .Lfailure - - uzp2 v2.8b, v0.8b, v1.8b - mov x1, v2.d[0] - adrp x3, zu8b - ldr x4, [x3, #:lo12:zu8b] - cmp x1, x4 - bne .Lfailure - - uzp1 v2.16b, v0.16b, v1.16b - mov x1, v2.d[0] - mov x2, v2.d[1] - adrp x3, zl16b - ldr x4, [x3, #:lo12:zl16b] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:zl16b+8] - cmp x2, x5 - bne .Lfailure - - uzp2 v2.16b, v0.16b, v1.16b - mov x1, v2.d[0] - mov x2, v2.d[1] - adrp x3, zu16b - ldr x4, [x3, #:lo12:zu16b] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:zu16b+8] - cmp x2, x5 - bne .Lfailure - - uzp1 v2.4h, v0.4h, v1.4h - mov x1, v2.d[0] - adrp x3, zl4h - ldr x4, [x3, #:lo12:zl4h] - cmp x1, x4 - bne .Lfailure - - uzp2 v2.4h, v0.4h, v1.4h - mov x1, v2.d[0] - adrp x3, zu4h - ldr x4, [x3, #:lo12:zu4h] - cmp x1, x4 - bne .Lfailure - - uzp1 v2.8h, v0.8h, v1.8h - mov x1, v2.d[0] - mov x2, v2.d[1] - adrp x3, zl8h - ldr x4, [x3, #:lo12:zl8h] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:zl8h+8] - cmp x2, x5 - bne .Lfailure - - uzp2 v2.8h, v0.8h, v1.8h - mov x1, v2.d[0] - mov x2, v2.d[1] - adrp x3, zu8h - ldr x4, [x3, #:lo12:zu8h] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:zu8h+8] - cmp x2, x5 - bne .Lfailure - - uzp1 v2.2s, v0.2s, v1.2s - mov x1, v2.d[0] - adrp x3, zl2s - ldr x4, [x3, #:lo12:zl2s] - cmp x1, x4 - bne .Lfailure - - uzp2 v2.2s, v0.2s, v1.2s - mov x1, v2.d[0] - adrp x3, zu2s - ldr x4, [x3, #:lo12:zu2s] - cmp x1, x4 - bne .Lfailure - - uzp1 v2.4s, v0.4s, v1.4s - mov x1, v2.d[0] - mov x2, v2.d[1] - adrp x3, zl4s - ldr x4, [x3, #:lo12:zl4s] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:zl4s+8] - cmp x2, x5 - bne .Lfailure - - uzp2 v2.4s, v0.4s, v1.4s - mov x1, v2.d[0] - mov x2, v2.d[1] - adrp x3, zu4s - ldr x4, [x3, #:lo12:zu4s] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:zu4s+8] - cmp x2, x5 - bne .Lfailure - - uzp1 v2.2d, v0.2d, v1.2d - mov x1, v2.d[0] - mov x2, v2.d[1] - adrp x3, zl2d - ldr x4, [x3, #:lo12:zl2d] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:zl2d+8] - cmp x2, x5 - bne .Lfailure - - uzp2 v2.2d, v0.2d, v1.2d - mov x1, v2.d[0] - mov x2, v2.d[1] - adrp x3, zu2d - ldr x4, [x3, #:lo12:zu2d] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:zu2d+8] - cmp x2, x5 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/xtl.s b/sim/testsuite/sim/aarch64/xtl.s deleted file mode 100644 index 16ef892..0000000 --- a/sim/testsuite/sim/aarch64/xtl.s +++ /dev/null @@ -1,101 +0,0 @@ -#mach: aarch64 - -# Check the extend long instructions: sxtl, sxtl2, uxtl, uxtl2. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x08070605 - .word 0xfcfdfeff - .word 0xf8f9fafb - - start - adrp x0, input - ldr q0, [x0, #:lo12:input] - - uxtl v1.8h, v0.8b - uxtl2 v2.8h, v0.16b - addv h3, v1.8h - addv h4, v2.8h - mov x1, v3.d[0] - mov x2, v4.d[0] - cmp x1, #36 - bne .Lfailure - cmp x2, #2012 - bne .Lfailure - - uxtl v1.4s, v0.4h - uxtl2 v2.4s, v0.8h - addv s3, v1.4s - addv s4, v2.4s - mov x1, v3.d[0] - mov x2, v4.d[0] - mov x3, #5136 - cmp x1, x3 - bne .Lfailure - mov x4, #0xeff0 - movk x4, 0x3, lsl #16 - cmp x2, x4 - bne .Lfailure - - uxtl v1.2d, v0.2s - uxtl2 v2.2d, v0.4s - addv s3, v1.4s - addv s4, v2.4s - mov x1, v3.d[0] - mov x2, v4.d[0] - mov x3, #0x0806 - movk x3, #0x0c0a, lsl #16 - cmp x1, x3 - bne .Lfailure - mov x4, #0xf9fa - movk x4, #0xf5f7, lsl #16 - cmp x2, x4 - bne .Lfailure - - sxtl v1.8h, v0.8b - sxtl2 v2.8h, v0.16b - addv h3, v1.8h - addv h4, v2.8h - mov x1, v3.d[0] - mov x2, v4.d[0] - cmp x1, #36 - bne .Lfailure - mov x3, #0xffdc - cmp x2, x3 - bne .Lfailure - - sxtl v1.4s, v0.4h - sxtl2 v2.4s, v0.8h - addv s3, v1.4s - addv s4, v2.4s - mov x1, v3.d[0] - mov x2, v4.d[0] - mov x3, #5136 - cmp x1, x3 - bne .Lfailure - mov x4, #0xeff0 - movk x4, 0xffff, lsl #16 - bne .Lfailure - - sxtl v1.2d, v0.2s - sxtl2 v2.2d, v0.4s - addv s3, v1.4s - addv s4, v2.4s - mov x1, v3.d[0] - mov x2, v4.d[0] - mov x3, #0x0806 - movk x3, #0x0c0a, lsl #16 - cmp x1, x3 - bne .Lfailure - mov x4, #0xf9f8 - movk x4, #0xf5f7, lsl #16 - cmp x2, x4 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/aarch64/xtn.s b/sim/testsuite/sim/aarch64/xtn.s deleted file mode 100644 index de369f7..0000000 --- a/sim/testsuite/sim/aarch64/xtn.s +++ /dev/null @@ -1,79 +0,0 @@ -# mach: aarch64 - -# Check the extract narrow instructions: xtn, xtn2. - -.include "testutils.inc" - - .data - .align 4 -input: - .word 0x04030201 - .word 0x08070605 - .word 0x0c0b0a09 - .word 0x100f0e0d -input2: - .word 0x14131211 - .word 0x18171615 - .word 0x1c1b1a19 - .word 0x201f1e1d -x16b: - .word 0x07050301 - .word 0x0f0d0b09 - .word 0x17151311 - .word 0x1f1d1b19 -x8h: - .word 0x06050201 - .word 0x0e0d0a09 - .word 0x16151211 - .word 0x1e1d1a19 -x4s: - .word 0x04030201 - .word 0x0c0b0a09 - .word 0x14131211 - .word 0x1c1b1a19 - - start - adrp x0, input - ldr q0, [x0, #:lo12:input] - adrp x0, input2 - ldr q1, [x0, #:lo12:input2] - - xtn v2.8b, v0.8h - xtn2 v2.16b, v1.8h - mov x1, v2.d[0] - mov x2, v2.d[1] - adrp x3, x16b - ldr x4, [x3, #:lo12:x16b] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:x16b+8] - cmp x2, x5 - bne .Lfailure - - xtn v2.4h, v0.4s - xtn2 v2.8h, v1.4s - mov x1, v2.d[0] - mov x2, v2.d[1] - adrp x3, x8h - ldr x4, [x3, #:lo12:x8h] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:x8h+8] - cmp x2, x5 - bne .Lfailure - - xtn v2.2s, v0.2d - xtn2 v2.4s, v1.2d - mov x1, v2.d[0] - mov x2, v2.d[1] - adrp x3, x4s - ldr x4, [x3, #:lo12:x4s] - cmp x1, x4 - bne .Lfailure - ldr x5, [x3, #:lo12:x4s+8] - cmp x2, x5 - bne .Lfailure - - pass -.Lfailure: - fail diff --git a/sim/testsuite/sim/arm/ChangeLog b/sim/testsuite/sim/arm/ChangeLog deleted file mode 100644 index 1237d81..0000000 --- a/sim/testsuite/sim/arm/ChangeLog +++ /dev/null @@ -1,122 +0,0 @@ -2013-05-07 Jayant Sonar - Kaushik Phatak - - * movw-movt.ms: New file: Test movw & movt instructions. - -2011-07-01 Nick Clifton - - PR sim/12737 - * iwmmxt/wcmpgt.cgs: Remove expectation of failure. - * iwmmxt/wmac.cgs: Remove expectation of failure. - * iwmmxt/wsra.cgs: Remove expectation of failure. - * xscale/blx.cgs: Remove expectation of failure. - -2011-05-11 Joseph Myers - Hans-Peter Nilsson - - PR sim/12737 - * iwmmxt/wcmpgt.cgs, iwmmxt/wmac.cgs, - iwmmxt/wsra.cgs, xscale/blx.cgs: Kfail. - -2011-05-04 Joseph Myers - - * allinsn.exp (xscale*-*-*): Don't handle target. - * misc.exp (thumb*-*-*, xscale*-*-*): Don't handle - targets. - * iwmmxt/iwmmxt.exp: Test for arm*-*-* instead of - xscale*-*-*. - * thumb/allthumb.exp (thumb*-*-*): Don't handle target. - * xscale/xscale.exp: Test for arm*-*-* instead of - xscale*-*-*. - -2003-04-01 Nick Clifton - - * .: New directory: Tests for ARM simulator. - * allinsn.exp: New file: Test script. - * testutils.inc: New file: Test macros. - * adc.cgs, add.cgs, and.cgs, - b.cgs, bic.cgs, bl.cgs, bx.cgs, - cmn.cgs, cmp.cgs, eor.cgs, - hello.ms, ldm.cgs, ldr.cgs, - ldrb.cgs, ldrh.cgs, ldrsb.cgs, - ldrsh.cgs, misaligned1.ms, misaligned2.ms, - misaligned3.ms, misc.exp, mla.cgs, - mov.cgs, mrs.cgs, msr.cgs, - mul.cgs, mvn.cgs, orr.cgs, - rsb.cgs, rsc.cgs, sbc.cgs, - smlal.cgs, smull.cgs, stm.cgs, - str.cgs, strb.cgs, strh.cgs, - sub.cgs, swi.cgs, swp.cgs, - swpb.cgs, teq.cgs, tst.cgs, - umlal.cgs, umull.cgs: New files: ARM tests. - * iwmmxt: New Directory: Tests for iWMMXt. - * iwmmxt/iwmmxt.exp: New file: Test script. - * iwmmxt/testutils.inc: New file: Test macros. - * iwmmxt/tbcst.cgs, iwmmxt/textrm.cgs, - iwmmxt/tinsr.cgs, iwmmxt/tmia.cgs, - iwmmxt/tmiaph.cgs, iwmmxt/tmiaxy.cgs, - iwmmxt/tmovmsk.cgss, iwmmxt/wacc.cgs, - iwmmxt/wadd.cgs, iwmmxt/waligni.cgs, - iwmmxt/walignr.cgs, iwmmxt/wand.cgs, - iwmmxt/wandn.cgs, iwmmxt/wavg2.cgs, - iwmmxt/wcmpeq.cgs, iwmmxt/wcmpgt.cgs, - iwmmxt/wmac.cgs, iwmmxt/wmadd.cgs, - iwmmxt/wmax.cgs, iwmmxt/wmin.cgs, - iwmmxt/wmov.cgs, iwmmxt/wmul.cgs, - iwmmxt/wor.cgs, iwmmxt/wpack.cgs, - iwmmxt/wror.cgs, iwmmxt/wsad.cgs, - iwmmxt/wshufh.cgs, iwmmxt/wsll.cgs, - iwmmxt/wsra.cgs, iwmmxt/wsrl.cgs, - iwmmxt/wsub.cgs, iwmmxt/wunpckeh.cgs, - iwmmxt/wunpckel.cgs, iwmmxt/wunpckih.cgs, - iwmmxt/wunpckil.cgs, iwmmxt/wxor.cgs, - iwmmxt/wzero.cgs: New files: iWMMXt tests. - * thumb: New Directory: Thumb tests. - * thumb/allthumb.exp: New file: Test script. - * thumb/testutils.inc: New file: Test macros. - * thumb/adc.cgs, thumb/add-hd-hs.cgs, - thumb/add-hd-rs.cgs, thumb/add-rd-hs.cgs, - thumb/add-sp.cgs, thumb/add.cgs, - thumb/addi.cgs, thumb/addi8.cgs, - thumb/and.cgs, thumb/asr.cgs, thumb/b.cgs, - thumb/bcc.cgs, thumb/bcs.cgs, - thumb/beq.cgs, thumb/bge.cgs, - thumb/bgt.cgs, thumb/bhi.cgs, - thumb/bic.cgs, thumb/bl-hi.cgs, - thumb/bl-lo.cgs, thumb/ble.cgs, - thumb/bls.cgs, thumb/blt.cgs, - thumb/bmi.cgs, thumb/bne.cgs, - thumb/bpl.cgs, thumb/bvc.cgs, - thumb/bvs.cgs, thumb/bx-hs.cgs, - thumb/bx-rs.cgs, thumb/cmn.cgs, - thumb/cmp-hd-hs.cgs, thumb/cmp-hd-rs.cgs, - thumb/cmp-rd-hs.cgs, thumb/cmp.cgs, - thumb/eor.cgs, thumb/lda-pc.cgs, - thumb/lda-sp.cgs, thumb/ldmia.cgs, - thumb/ldr-imm.cgs, thumb/ldr-pc.cgs, - thumb/ldr-sprel.cgs, thumb/ldr.cgs, - thumb/ldrb-imm.cgs, thumb/ldrb.cgs, - thumb/ldrh-imm.cgs, thumb/ldrh.cgs, - thumb/ldsb.cgs, thumb/ldsh.cgs, - thumb/lsl.cgs, thumb/lsr.cgs, - thumb/mov-hd-hs.cgs, thumb/mov-hd-rs.cgs, - thumb/mov-rd-hs.cgs, thumb/mov.cgs, - thumb/mul.cgs, thumb/mvn.cgs, - thumb/neg.cgs, thumb/orr.cgs, - thumb/pop-pc.cgs, thumb/pop.cgs, - thumb/push-lr.cgs, thumb/push.cgs, - thumb/ror.cgs, thumb/sbc.cgs, - thumb/stmia.cgs, thumb/str-imm.cgs, - thumb/str-sprel.cgs, thumb/str.cgs, - thumb/strb-imm.cgs, thumb/strb.cgs, - thumb/strh-imm.cgs, thumb/strh.cgs, - thumb/sub-sp.cgs, thumb/sub.cgs, - thumb/subi.cgs, thumb/subi8.cgs, - thumb/swi.cgs, thumb/tst.cgs: New files: Thumb - tests. - * xscale: New directory. - * xscale/xscale.exp: New file: Test script. - * xscale/testutils.inc: New file: Test macros. - * xscale/blx.cgs, xscale/mia.cgs, - xscale/miaph.cgs, xscale/miaxy.cgs, - xscale/mra.cgs: New files: XScale tests. diff --git a/sim/testsuite/sim/arm/adc.cgs b/sim/testsuite/sim/arm/adc.cgs deleted file mode 100644 index b6659a1..0000000 --- a/sim/testsuite/sim/arm/adc.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# arm testcase for adc -# mach: all - -# ??? Unfinished, more tests needed. - - .include "testutils.inc" - - start - -# adc$cond${set-cc?} $rd,$rn,$imm12 - - .global adc_imm -adc_imm: - mvi_h_gr r4,1 - mvi_h_cnvz 0,0,0,0 - adc r5,r4,#1 - test_h_cnvz 0,0,0,0 - test_h_gr r5,2 - -# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} - - .global adc_reg_imm_shift -adc_reg_imm_shift: - mvi_h_gr r4,1 - mvi_h_gr r5,1 - mvi_h_cnvz 0,0,0,0 - adc r6,r4,r5,lsl #2 - test_h_cnvz 0,0,0,0 - test_h_gr r6,5 - -# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} - - .global adc_reg_reg_shift -adc_reg_reg_shift: - mvi_h_gr r4,1 - mvi_h_gr r5,1 - mvi_h_gr r6,2 - mvi_h_cnvz 0,0,0,0 - adc r7,r4,r5,lsl r6 - test_h_cnvz 0,0,0,0 - test_h_gr r7,5 - - pass diff --git a/sim/testsuite/sim/arm/add.cgs b/sim/testsuite/sim/arm/add.cgs deleted file mode 100644 index eba32e0..0000000 --- a/sim/testsuite/sim/arm/add.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# arm testcase for add -# mach: all - -# ??? Unfinished, more tests needed. - - .include "testutils.inc" - - start - -# add$cond${set-cc?} $rd,$rn,$imm12 - - .global add_imm -add_imm: - mvi_h_gr r4,1 - mvi_h_cnvz 0,0,0,0 - add r5,r4,#1 - test_h_cnvz 0,0,0,0 - test_h_gr r5,2 - -# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} - - .global add_reg_imm_shift -add_reg_imm_shift: - mvi_h_gr r4,1 - mvi_h_gr r5,1 - mvi_h_cnvz 0,0,0,0 - add r6,r4,r5,lsl #2 - test_h_cnvz 0,0,0,0 - test_h_gr r6,5 - -# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} - - .global add_reg_reg_shift -add_reg_reg_shift: - mvi_h_gr r4,1 - mvi_h_gr r5,1 - mvi_h_gr r6,2 - mvi_h_cnvz 0,0,0,0 - add r7,r4,r5,lsl r6 - test_h_cnvz 0,0,0,0 - test_h_gr r7,5 - - pass diff --git a/sim/testsuite/sim/arm/allinsn.exp b/sim/testsuite/sim/arm/allinsn.exp deleted file mode 100644 index 9752da6..0000000 --- a/sim/testsuite/sim/arm/allinsn.exp +++ /dev/null @@ -1,28 +0,0 @@ -# ARM simulator testsuite. - -if { [istarget arm*-*-*] } { - # load support procs (none yet) - # load_lib cgen.exp - - # all machines - set all_machs "xscale" - - if [is_remote host] { - remote_download host $srcdir/$subdir/testutils.inc - } - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } - - if [is_remote host] { - remote_file host delete testutils.inc - } -} diff --git a/sim/testsuite/sim/arm/and.cgs b/sim/testsuite/sim/arm/and.cgs deleted file mode 100644 index cd8f003..0000000 --- a/sim/testsuite/sim/arm/and.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# arm testcase for and -# mach: all - -# ??? Unfinished, more tests needed. - - .include "testutils.inc" - - start - -# and$cond${set-cc?} $rd,$rn,$imm12 - - .global and_imm -and_imm: - mvi_h_gr r4,1 - mvi_h_cnvz 0,0,0,0 - and r5,r4,#1 - test_h_cnvz 0,0,0,0 - test_h_gr r5,1 - -# and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} - - .global and_reg_imm_shift -and_reg_imm_shift: - mvi_h_gr r4,1 - mvi_h_gr r5,1 - mvi_h_cnvz 0,0,0,0 - and r6,r4,r5,lsl #1 - test_h_cnvz 0,0,0,0 - test_h_gr r6,0 - -# and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} - - .global and_reg_reg_shift -and_reg_reg_shift: - mvi_h_gr r4,1 - mvi_h_gr r5,1 - mvi_h_gr r6,1 - mvi_h_cnvz 0,0,0,0 - and r7,r4,r5,lsl r6 - test_h_cnvz 0,0,0,0 - test_h_gr r7,0 - - pass diff --git a/sim/testsuite/sim/arm/b.cgs b/sim/testsuite/sim/arm/b.cgs deleted file mode 100644 index 414b963..0000000 --- a/sim/testsuite/sim/arm/b.cgs +++ /dev/null @@ -1,261 +0,0 @@ -# arm testcase for b$cond $offset24 -# mach: all - -# ??? Still need to test edge cases. - - .include "testutils.inc" - - start - - .global b -b: - -# b foo - - b balways1 - fail -balways1: - -# beq foo - - mvi_h_gr r4,4 - mvi_h_gr r5,4 - cmp r4,r5 - beq beq1 - fail -beq1: - mvi_h_gr r5,5 - cmp r4,r5 - beq beq2 - b beq3 -beq2: - fail -beq3: - -# bne foo - - mvi_h_gr r4,4 - mvi_h_gr r5,5 - cmp r4,r5 - bne bne1 - fail -bne1: - mvi_h_gr r5,4 - cmp r4,r5 - bne bne2 - b bne3 -bne2: - fail -bne3: - -# bcs foo - - mvi_h_cnvz 1,0,0,0 - bcs bcs1 - fail -bcs1: - mvi_h_cnvz 0,0,0,0 - bcs bcs2 - b bcs3 -bcs2: - fail -bcs3: - -# bcc foo - - mvi_h_cnvz 0,0,0,0 - bcc bcc1 - fail -bcc1: - mvi_h_cnvz 1,0,0,0 - bcc bcc2 - b bcc3 -bcc2: - fail -bcc3: - -# bmi foo - - mvi_h_cnvz 0,1,0,0 - bmi bmi1 - fail -bmi1: - mvi_h_cnvz 0,0,0,0 - bmi bmi2 - b bmi3 -bmi2: - fail -bmi3: - -# bpl foo - - mvi_h_cnvz 0,0,0,0 - bpl bpl1 - fail -bpl1: - mvi_h_cnvz 0,1,0,0 - bpl bpl2 - b bpl3 -bpl2: - fail -bpl3: - -# bvs foo - - mvi_h_cnvz 0,0,1,0 - bvs bvs1 - fail -bvs1: - mvi_h_cnvz 0,0,0,0 - bvs bvs2 - b bvs3 -bvs2: - fail -bvs3: - -# bvc foo - - mvi_h_cnvz 0,0,0,0 - bvc bvc1 - fail -bvc1: - mvi_h_cnvz 0,0,1,0 - bvc bvc2 - b bvc3 -bvc2: - fail -bvc3: - -# bhi foo - - mvi_h_gr r4,5 - mvi_h_gr r5,4 - cmp r4,r5 - bhi bhi1 - fail -bhi1: - mvi_h_gr r5,5 - cmp r4,r5 - bhi bhi2 - b bhi3 -bhi2: - fail -bhi3: - mvi_h_gr r5,6 - cmp r4,r5 - bhi bhi4 - b bhi5 -bhi4: - fail -bhi5: - -# bls foo - - mvi_h_gr r4,4 - mvi_h_gr r5,5 - cmp r4,r5 - bls bls1 - fail -bls1: - mvi_h_gr r5,4 - cmp r4,r5 - bls bls2 - fail -bls2: - mvi_h_gr r5,3 - cmp r4,r5 - bls bls3 - b bls4 -bls3: - fail -bls4: - -# bge foo - - mvi_h_gr r4,4 - mvi_h_gr r5,4 - cmp r4,r5 - bge bge1 - fail -bge1: - mvi_h_gr r5,3 - cmp r4,r5 - bge bge2 - fail -bge2: - mvi_h_gr r5,5 - cmp r4,r5 - bge bge3 - b bge4 -bge3: - fail -bge4: - -# blt foo - - mvi_h_gr r4,4 - mvi_h_gr r5,5 - cmp r4,r5 - blt blt1 - fail -blt1: - mvi_h_gr r5,4 - cmp r4,r5 - blt blt2 - b blt3 -blt2: - fail -blt3: - mvi_h_gr r5,3 - cmp r4,r5 - blt blt4 - b blt5 -blt4: - fail -blt5: - -# bgt foo - - mvi_h_gr r4,4 - mvi_h_gr r5,3 - cmp r4,r5 - bgt bgt1 - fail -bgt1: - mvi_h_gr r5,4 - cmp r4,r5 - bgt bgt2 - b bgt3 -bgt2: - fail -bgt3: - mvi_h_gr r5,5 - cmp r4,r5 - bgt bgt4 - b bgt5 -bgt4: - fail -bgt5: - -# ble foo - - mvi_h_gr r4,4 - mvi_h_gr r5,4 - cmp r4,r5 - ble ble1 - fail -ble1: - mvi_h_gr r5,5 - cmp r4,r5 - ble ble2 - fail -ble2: - mvi_h_gr r5,3 - cmp r4,r5 - ble ble3 - b ble4 -ble3: - fail -ble4: - - pass diff --git a/sim/testsuite/sim/arm/bic.cgs b/sim/testsuite/sim/arm/bic.cgs deleted file mode 100644 index 37a9b6c..0000000 --- a/sim/testsuite/sim/arm/bic.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# arm testcase for bic -# mach: all - -# ??? Unfinished, more tests needed. - - .include "testutils.inc" - - start - -# bic$cond${set-cc?} $rd,$rn,$imm12 - - .global bic_imm -bic_imm: - mvi_h_gr r4,1 - mvi_h_cnvz 0,0,0,0 - bic r5,r4,#0 - test_h_cnvz 0,0,0,0 - test_h_gr r5,1 - -# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftimm} - - .global bic_reg_imm_shift -bic_reg_imm_shift: - mvi_h_gr r4,7 - mvi_h_gr r5,1 - mvi_h_cnvz 0,0,0,0 - bic r6,r4,r5,lsl #1 - test_h_cnvz 0,0,0,0 - test_h_gr r6,5 - -# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftreg} - - .global bic_reg_reg_shift -bic_reg_reg_shift: - mvi_h_gr r4,7 - mvi_h_gr r5,1 - mvi_h_gr r6,1 - mvi_h_cnvz 0,0,0,0 - bic r7,r4,r5,lsl r6 - test_h_cnvz 0,0,0,0 - test_h_gr r7,5 - - pass diff --git a/sim/testsuite/sim/arm/bl.cgs b/sim/testsuite/sim/arm/bl.cgs deleted file mode 100644 index fbc7ef5..0000000 --- a/sim/testsuite/sim/arm/bl.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# arm testcase for bl$cond $offset24 -# mach: all - - .include "testutils.inc" - - start - - .global bl -bl: - mvi_h_gr r14,0 - bl bl2 -bl1: - fail -bl2: - mvaddr_h_gr r4,bl1 - cmp r14,r4 - beq bl3 - fail -bl3: - - pass diff --git a/sim/testsuite/sim/arm/bx.cgs b/sim/testsuite/sim/arm/bx.cgs deleted file mode 100644 index 4c18af4..0000000 --- a/sim/testsuite/sim/arm/bx.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bx$cond $rn -# mach: unfinished - - .include "testutils.inc" - - start - - .global bx -bx: - bx0 pc - - pass diff --git a/sim/testsuite/sim/arm/cmn.cgs b/sim/testsuite/sim/arm/cmn.cgs deleted file mode 100644 index 1829fc7..0000000 --- a/sim/testsuite/sim/arm/cmn.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for cmn${cond}${set-cc?} $rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmn_imm -cmn_imm: - cmn00 pc,0 - - pass -# arm testcase for cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmn_reg_imm_shift -cmn_reg_imm_shift: - cmn00 pc,pc,pc,lsl 0 - - pass -# arm testcase for cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmn_reg_reg_shift -cmn_reg_reg_shift: - cmn00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/cmp.cgs b/sim/testsuite/sim/arm/cmp.cgs deleted file mode 100644 index ab9dd59..0000000 --- a/sim/testsuite/sim/arm/cmp.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for cmp${cond}${set-cc?} $rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp_imm -cmp_imm: - cmp00 pc,0 - - pass -# arm testcase for cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp_reg_imm_shift -cmp_reg_imm_shift: - cmp00 pc,pc,pc,lsl 0 - - pass -# arm testcase for cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp_reg_reg_shift -cmp_reg_reg_shift: - cmp00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/eor.cgs b/sim/testsuite/sim/arm/eor.cgs deleted file mode 100644 index 5bbb1c6..0000000 --- a/sim/testsuite/sim/arm/eor.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for eor$cond${set-cc?} $rd,$rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global eor_imm -eor_imm: - eor00 pc,pc,0 - - pass -# arm testcase for eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global eor_reg_imm_shift -eor_reg_imm_shift: - eor00 pc,pc,pc,lsl 0 - - pass -# arm testcase for eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global eor_reg_reg_shift -eor_reg_reg_shift: - eor00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/hello.ms b/sim/testsuite/sim/arm/hello.ms deleted file mode 100644 index b063c29..0000000 --- a/sim/testsuite/sim/arm/hello.ms +++ /dev/null @@ -1,91 +0,0 @@ -# output(): Hello, world.\n -# mach(): all - -# Emit hello world while switching back and forth between arm/thumb. -# ??? Unfinished - - .macro invalid -# This is "undefined" but it's not properly decoded yet. - .word 0x07ffffff -# This is stc which isn't recognized yet. - stc 0,cr0,[r0] - .endm - - .global _start -_start: -# Run some simple insns to confirm the engine is at least working. - nop - -# Skip over output text. - - bl skip_output - -hello_text: - .asciz "Hello, world.\n" - - .p2align 2 -skip_output: - -# Prime loop. - - mov r4, r14 - -output_next: - -# Switch arm->thumb to output next chacter. -# At this point r4 must point to the next character to output. - - adr r0, into_thumb + 1 - bx r0 - -into_thumb: - .thumb - -# Output a character. - - mov r0,#3 @ writec angel call - mov r1,r4 - swi 0xab @ ??? Confirm number. - -# Switch thumb->arm. - - adr r5, back_to_arm - bx r5 - - .p2align 2 -back_to_arm: - .arm - -# Load next character, see if done. - - add r4,r4,#1 - sub r3,r3,r3 - ldrb r5,[r4,r3] - teq r5,#0 - beq done - -# Output a character (in arm mode). - - mov r0,#3 - mov r1,r4 - swi #0x123456 - -# Load next character, see if done. - - add r4,r4,#1 - sub r3,r3,r3 - ldrb r5,[r4,r3] - teq r5,#0 - bne output_next - -done: - mov r0,#0x18 - ldr r1,exit_code - swi #0x123456 - -# If that fails, try to die with an invalid insn. - - invalid - -exit_code: - .word 0x20026 diff --git a/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp b/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp deleted file mode 100644 index 4def690..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp +++ /dev/null @@ -1,28 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology simulator testsuite. - -if { [istarget arm*-*-*] } { - # load support procs (none yet) - # load_lib cgen.exp - - # all machines - set all_machs "xscale" - - if [is_remote host] { - remote_download host $srcdir/$subdir/testutils.inc - } - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } - - if [is_remote host] { - remote_file host delete testutils.inc - } -} diff --git a/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs b/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs deleted file mode 100644 index b7138df..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TBCST -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global tbcst -tbcst: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte Wide Broadcast - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - tbcstb wr0, r2 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0xffffffff - test_h_gr r1, 0xffffffff - test_h_gr r2, 0x111111ff - - # Test Half Word Wide Broadcast - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - tbcsth wr0, r2 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x11ff11ff - test_h_gr r1, 0x11ff11ff - test_h_gr r2, 0x111111ff - - # Test Word Wide Broadcast - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - tbcstw wr0, r2 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x111111ff - test_h_gr r1, 0x111111ff - test_h_gr r2, 0x111111ff - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/testutils.inc b/sim/testsuite/sim/arm/iwmmxt/testutils.inc deleted file mode 100644 index ae49db8..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/testutils.inc +++ /dev/null @@ -1,118 +0,0 @@ -# r0-r3 are used as tmps, consider them call clobbered by these macros. -# This uses the angel rom monitor calls. -# ??? How do we use the \@ facility of .macros ??? -# @ is the comment char! - - .macro mvi_h_gr reg, val - ldr \reg,[pc] - b . + 8 - .word \val - .endm - - .macro mvaddr_h_gr reg, addr - ldr \reg,[pc] - b . + 8 - .word \addr - .endm - - .macro start - .data -failmsg: - .asciz "fail\n" -passmsg: - .asciz "pass\n" - .text - -do_pass: - ldr r1, passmsg_addr - mov r0, #4 - swi #0x123456 - exit 0 -passmsg_addr: - .word passmsg - -do_fail: - ldr r1, failmsg_addr - mov r0, #4 - swi #0x123456 - exit 1 -failmsg_addr: - .word failmsg - - .global _start -_start: - .endm - -# *** Other macros know pass/fail are 4 bytes in size! Yuck. - - .macro pass - b do_pass - .endm - - .macro fail - b do_fail - .endm - - .macro exit rc - # ??? This works with the ARMulator but maybe not others. - #mov r0, #\rc - #swi #1 - # This seems to be portable (though it ignores rc). - mov r0,#0x18 - mvi_h_gr r1, 0x20026 - swi #0x123456 - # If that returns, punt with a sigill. - stc 0,cr0,[r0] - .endm - -# Other macros know this only clobbers r0. -# WARNING: It also clobbers the condition codes (FIXME). - .macro test_h_gr reg, val - mvaddr_h_gr r0, \val - cmp \reg, r0 - beq . + 8 - fail - .endm - - .macro mvi_h_cnvz c, n, v, z - mov r0, #0 - .if \c - orr r0, r0, #0x20000000 - .endif - .if \n - orr r0, r0, #0x80000000 - .endif - .if \v - orr r0, r0, #0x10000000 - .endif - .if \z - orr r0, r0, #0x40000000 - .endif - mrs r1, cpsr - bic r1, r1, #0xf0000000 - orr r1, r1, r0 - msr cpsr, r1 - # ??? nops needed - .endm - -# ??? Preserve condition codes? - .macro test_h_cnvz c, n, v, z - mov r0, #0 - .if \c - orr r0, r0, #0x20000000 - .endif - .if \n - orr r0, r0, #0x80000000 - .endif - .if \v - orr r0, r0, #0x10000000 - .endif - .if \z - orr r0, r0, #0x40000000 - .endif - mrs r1, cpsr - and r1, r1, #0xf0000000 - cmp r0, r1 - beq . + 8 - fail - .endm diff --git a/sim/testsuite/sim/arm/iwmmxt/textrm.cgs b/sim/testsuite/sim/arm/iwmmxt/textrm.cgs deleted file mode 100644 index fb3dc94..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/textrm.cgs +++ /dev/null @@ -1,113 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TEXTRM -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global textrm -textrm: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Wide Extraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - textrmub r2, wr0, #3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00000012 - - # Test Signed Byte Wide Extraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - textrmsb r2, wr0, #4 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0xfffffff0 - - # Test Unsigned Half Word Wide Extraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - textrmuh r2, wr0, #3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00009abc - - # Test Signed Half Word Wide Extraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - textrmsh r2, wr0, #1 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00001234 - - # Test Unsigned Word Wide Extraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - textrmuw r2, wr0, #0 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x12345678 - - # Test Signed Word Wide Extraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - textrmsw r2, wr0, #1 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs b/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs deleted file mode 100644 index f457b19..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TINSR -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global tinsr -tinsr: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte Wide Insertion - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - tinsrb wr0, r2, #3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0xff345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x111111ff - - # Test Half Word Wide Insertion - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - tinsrh wr0, r2, #2 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abc11ff - test_h_gr r2, 0x111111ff - - # Test Word Wide Insertion - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x111111ff - - tmcrr wr0, r0, r1 - - tinsrw wr0, r2, #1 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x111111ff - test_h_gr r2, 0x111111ff - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tmia.cgs b/sim/testsuite/sim/arm/iwmmxt/tmia.cgs deleted file mode 100644 index 0b0da66..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/tmia.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TMIA -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global tmia -tmia: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - tmia wr0, r2, r3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x354f53c4 - test_h_gr r1, 0x4e330b5e - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs b/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs deleted file mode 100644 index 3778b0a..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TMIAPH -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global tmiaph -tmiaph: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - tmiaph wr0, r2, r3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0xfec3f9f4 - test_h_gr r1, 0x55667787 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs b/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs deleted file mode 100644 index e7a7b73..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs +++ /dev/null @@ -1,89 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TMIAxy -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global tmiaXY -tmiaXY: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Bottom Bottom Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - tmiaBB wr0, r2, r3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x05f753c4 - test_h_gr r1, 0x55667788 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - # Test Bottom Top Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - tmiaBT wr0, r2, r3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0xeeede364 - test_h_gr r1, 0x55667787 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - # Test Top Bottom Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - tmiaTB wr0, r2, r3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x0ec85c04 - test_h_gr r1, 0x55667788 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - # Test Top Top Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - tmiaTT wr0, r2, r3 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x09eed974 - test_h_gr r1, 0x55667788 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs b/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs deleted file mode 100644 index cfea5b7..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for TMOVMSK -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global tmovmsk -tmovmsk: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte Wide Mask Transfer - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - - tmcrr wr0, r0, r1 - - tmovmskb r2, wr0 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x000000f0 - - # Test Half Word Wide Mask Transfer - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - - tmcrr wr0, r0, r1 - - tmovmskh r2, wr0 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x0000000c - - # Test Word Wide Mask Transfer - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - - tmcrr wr0, r0, r1 - - tmovmskw r2, wr0 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00000002 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wacc.cgs b/sim/testsuite/sim/arm/iwmmxt/wacc.cgs deleted file mode 100644 index b3ffea1..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wacc.cgs +++ /dev/null @@ -1,77 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WACC -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wacc -wacc: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Wide Accumulation - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - waccb wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00000438 - test_h_gr r3, 0x00000000 - - # Test Unsigned Half Word Wide Accumulation - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wacch wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x0001e258 - test_h_gr r3, 0x00000000 - - # Test Unsigned Word Wide Accumulation - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - waccw wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0xacf13568 - test_h_gr r3, 0x00000000 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wadd.cgs b/sim/testsuite/sim/arm/iwmmxt/wadd.cgs deleted file mode 100644 index bb4d0ab..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wadd.cgs +++ /dev/null @@ -1,251 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WADD -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wadd -wadd: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test UnSaturated Byte Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test Unsigned Saturated Byte Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddbus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test Signed Saturated Byte Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddbss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x2345677f - test_h_gr r5, 0xabcdef11 - - # Test UnSaturated Halfword Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test Unsigned Saturated Halfword Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddhus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test Signed Saturated Halfword Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddhss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test UnSaturated Word Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test Unsigned Saturated Word Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddwus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - # Test Signed Saturated Word Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waddwss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456789 - test_h_gr r5, 0xabcdef11 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/waligni.cgs b/sim/testsuite/sim/arm/iwmmxt/waligni.cgs deleted file mode 100644 index dc99dae..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/waligni.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WALIGNI -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global waligni -waligni: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test 2 byte align - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - waligni wr2, wr0, wr1, #2 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0xdef01234 - test_h_gr r5, 0x11119abc - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/walignr.cgs b/sim/testsuite/sim/arm/iwmmxt/walignr.cgs deleted file mode 100644 index 85df51e..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/walignr.cgs +++ /dev/null @@ -1,137 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WALIGNR -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global walignr -walignr: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test 0 byte align - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - mvi_h_gr r6, 3 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - tmcr wcgr0, r6 - - walignr0 wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - tmrc r6, wcgr0 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0xbcdef012 - test_h_gr r5, 0x1111119a - test_h_gr r6, 3 - - # Test 1 byte align - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - mvi_h_gr r6, 4 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - tmcr wcgr1, r6 - - walignr1 wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - tmrc r6, wcgr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x9abcdef0 - test_h_gr r5, 0x11111111 - test_h_gr r6, 4 - - # Test 2 byte align - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - mvi_h_gr r6, 2 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - tmcr wcgr2, r6 - - walignr2 wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - tmrc r6, wcgr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0xdef01234 - test_h_gr r5, 0x11119abc - test_h_gr r6, 2 - - # Test 3 byte align - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - mvi_h_gr r6, 5 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - tmcr wcgr3, r6 - - walignr3 wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - tmrc r6, wcgr3 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x119abcde - test_h_gr r5, 0x00111111 - test_h_gr r6, 5 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wand.cgs b/sim/testsuite/sim/arm/iwmmxt/wand.cgs deleted file mode 100644 index 018383f..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wand.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WAND -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wand -wand: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wand wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x10101010 - test_h_gr r5, 0x00000000 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wandn.cgs b/sim/testsuite/sim/arm/iwmmxt/wandn.cgs deleted file mode 100644 index f2c2305..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wandn.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WANDN -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wandn -wandn: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wandn wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x02244668 - test_h_gr r5, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs b/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs deleted file mode 100644 index cac2c1a..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs +++ /dev/null @@ -1,121 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WAVG2 -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wavg2 -wavg2: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte Wide Averaging - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wavg2b wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x11223344 - test_h_gr r5, 0x5e6f8089 - - # Test Byte Wide Averaging with Rounding - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wavg2br wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x12233445 - test_h_gr r5, 0x5e6f8089 - - # Test Half Word Wide Averaging - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wavg2h wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x11a233c4 - test_h_gr r5, 0x5e6f8089 - - # Test Half Word Wide Averaging with Rounding - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wavg2hr wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x11a333c5 - test_h_gr r5, 0x5e6f8089 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs b/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs deleted file mode 100644 index 13ef3dc..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs +++ /dev/null @@ -1,95 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WCMPEQ -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wcmpeq -wcmpeq: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte Wide Compare Equal To - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x9abcde00 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpeqb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x9abcde00 - test_h_gr r4, 0x00000000 - test_h_gr r5, 0xffffffff - - # Test Half Word Wide Compare Equal To - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x9abcde00 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpeqh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x9abcde00 - test_h_gr r4, 0x00000000 - test_h_gr r5, 0xffffffff - - # Test Word Wide Compare Equal To - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x9abcde00 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpeqw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x9abcde00 - test_h_gr r4, 0x00000000 - test_h_gr r5, 0xffffffff - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs b/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs deleted file mode 100644 index 33086c9..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs +++ /dev/null @@ -1,173 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WCMPGT -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wcmpgt -wcmpgt: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Wide Compare Greater Than - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpgtub wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xffffffff - test_h_gr r5, 0xffffff00 - - # Test Signed Byte Wide Compare Greater Than - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpgtsb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xffffffff - test_h_gr r5, 0x00000000 - - # Test Unsigned Half Word Wide Compare Greater Than - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpgtuh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xffffffff - test_h_gr r5, 0xffffffff - - # Test Signed Half Word Wide Compare Greater Than - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpgtsh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xffffffff - test_h_gr r5, 0x00000000 - - # Test Unsigned Word Wide Compare Greater Than - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpgtuw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xffffffff - test_h_gr r5, 0xffffffff - - # Test Signed Word Wide Compare Greater Than - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wcmpgtsw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xffffffff - test_h_gr r5, 0x00000000 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmac.cgs b/sim/testsuite/sim/arm/iwmmxt/wmac.cgs deleted file mode 100644 index 0857ef9..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wmac.cgs +++ /dev/null @@ -1,121 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WMAC -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wmac -wmac: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned, Multiply Accumulate, Non-zeroing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x33333333 - mvi_h_gr r5, 0x44444444 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmacu wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x6c889377 - test_h_gr r5, 0x44444444 - - # Test Unsigned, Multiply Accumulate, Zeroing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x33333333 - mvi_h_gr r5, 0x44444444 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmacuz wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x39556044 - test_h_gr r5, 0x00000000 - - # Test Signed, Multiply Accumulate, Non-zeroing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x33333333 - mvi_h_gr r5, 0x44444444 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmacs wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x28449377 - test_h_gr r5, 0x44444444 - - # Test Signed, Multiply Accumulate, Zeroing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x33333333 - mvi_h_gr r5, 0x44444444 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmacsz wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xf5116044 - test_h_gr r5, 0xffffffff - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs b/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs deleted file mode 100644 index 564b3be..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WMADD -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wmadd -wmadd: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned, Multiply Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaddu wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x06fa5f6c - test_h_gr r5, 0x325b00d8 - - # Test Signed, Multiply Addition - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmadds wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x06fa5f6c - test_h_gr r5, 0xee1700d8 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmax.cgs b/sim/testsuite/sim/arm/iwmmxt/wmax.cgs deleted file mode 100644 index 3a684ce..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wmax.cgs +++ /dev/null @@ -1,173 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WMAX -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wmax -wmax: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Maximum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaxub wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x9abcde11 - - # Test Signed Byte Maximum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaxsb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x11111111 - - # Test Unsigned Halfword Maximum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaxuh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x9abcde00 - - # Test Signed Halfword Maximum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaxsh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x11111111 - - # Test Unsigned Word Maximum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaxuw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x9abcde00 - - # Test Signed Word Maximum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmaxsw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x11111111 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmin.cgs b/sim/testsuite/sim/arm/iwmmxt/wmin.cgs deleted file mode 100644 index 3bc1c08..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wmin.cgs +++ /dev/null @@ -1,173 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WMIN -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wmin -wmin: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Minimum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wminub wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x11111111 - test_h_gr r5, 0x11111100 - - # Test Signed Byte Minimum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wminsb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x11111111 - test_h_gr r5, 0x9abcde00 - - # Test Unsigned Halfword Minimum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wminuh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x11111111 - test_h_gr r5, 0x11111111 - - # Test Signed Halfword Minimum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wminsh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x11111111 - test_h_gr r5, 0x9abcde00 - - # Test Unsigned Word Minimum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wminuw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x11111111 - test_h_gr r5, 0x11111111 - - # Test Signed Word Minimum - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wminsw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x11111111 - test_h_gr r5, 0x9abcde00 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmov.cgs b/sim/testsuite/sim/arm/iwmmxt/wmov.cgs deleted file mode 100644 index e86fed6..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wmov.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WMOV -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wmov -wmov: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wmov wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmul.cgs b/sim/testsuite/sim/arm/iwmmxt/wmul.cgs deleted file mode 100644 index 0978b63..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wmul.cgs +++ /dev/null @@ -1,121 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WMUL -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wmul -wmul: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned, Most Significant Multiply - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmulum wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x013605c3 - test_h_gr r5, 0x14a11db9 - - # Test Unsigned, Least Significant Multiply - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmulul wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xa974b5f8 - test_h_gr r5, 0x84f87be0 - - # Test Signed, Most Significant Multiply - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmulsm wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x013605c3 - test_h_gr r5, 0xf27ffb97 - - # Test Signed, Least Significant Multiply - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wmulsl wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0xa974b5f8 - test_h_gr r5, 0x84f87be0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wor.cgs b/sim/testsuite/sim/arm/iwmmxt/wor.cgs deleted file mode 100644 index 48d5f53..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wor.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WOR -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wor -wor: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wor wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x13355779 - test_h_gr r5, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wpack.cgs b/sim/testsuite/sim/arm/iwmmxt/wpack.cgs deleted file mode 100644 index 0546bd4..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wpack.cgs +++ /dev/null @@ -1,173 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WPACK -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wpack -wpack: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Halfword, Unsigned Saturation, Packing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wpackhus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x0000ffff - test_h_gr r5, 0x0000ffff - - # Test Halfword, Signed Saturation, Packing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wpackhss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x80807f7f - test_h_gr r5, 0x00007f7f - - # Test Word, Unsigned Saturation, Packing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wpackwus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x0000ffff - test_h_gr r5, 0x0000ffff - - # Test Word, Signed Saturation, Packing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wpackwss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x80007fff - test_h_gr r5, 0x00007fff - - # Test Double Word, Unsigned Saturation, Packing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wpackdus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x00000000 - test_h_gr r5, 0x11111111 - - # Test Double Word, Signed Saturation, Packing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wpackdss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x80000000 - test_h_gr r5, 0x11111111 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wror.cgs b/sim/testsuite/sim/arm/iwmmxt/wror.cgs deleted file mode 100644 index e329916..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wror.cgs +++ /dev/null @@ -1,167 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WROR -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wror -wror: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Halfword wide rotate right by register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wrorh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x091a2b3c - test_h_gr r5, 0x4d5e6f78 - - # Test Halfword wide rotate right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr0, r2 - tmcrr wr1, r2, r3 - - wrorhg wr1, wr0, wcgr0 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr0 - tmrrc r3, r4, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x091a2b3c - test_h_gr r4, 0x4d5e6f78 - - # Test Word wide rotate right by register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wrorw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x2b3c091a - test_h_gr r5, 0x6f784d5e - - # Test Word wide rotate right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr0, r2 - tmcrr wr1, r2, r3 - - wrorwg wr1, wr0, wcgr0 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr0 - tmrrc r3, r4, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x2b3c091a - test_h_gr r4, 0x6f784d5e - - # Test Double Word wide rotate right by register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wrord wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x6f78091a - test_h_gr r5, 0x2b3c4d5e - - # Test Double Word wide rotate right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr0, r2 - tmcrr wr1, r2, r3 - - wrordg wr1, wr0, wcgr0 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr0 - tmrrc r3, r4, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x6f78091a - test_h_gr r4, 0x2b3c4d5e - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsad.cgs b/sim/testsuite/sim/arm/iwmmxt/wsad.cgs deleted file mode 100644 index 34a20cc..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wsad.cgs +++ /dev/null @@ -1,121 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WSAD -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wsad -wsad: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte wide absolute accumulation - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x22222222 - mvi_h_gr r5, 0x22222222 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsadb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x2222258e - test_h_gr r5, 0x00000000 - - # Test Byte wide absolute accumulation with zeroing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x22222222 - mvi_h_gr r5, 0x22222222 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsadbz wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x0000036c - test_h_gr r5, 0x00000000 - - # Test Halfword wide absolute accumulation - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x22222222 - mvi_h_gr r5, 0x22222222 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsadh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x22239e14 - test_h_gr r5, 0x00000000 - - # Test Halfword wide absolute accumulation with zeroing - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x22222222 - mvi_h_gr r4, 0x22222222 - mvi_h_gr r5, 0x22222222 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsadhz wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x22222222 - test_h_gr r4, 0x00017bf2 - test_h_gr r5, 0x00000000 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs b/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs deleted file mode 100644 index d5cff1e..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WSHUFH -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wshufh -wshufh: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wshufh wr1, wr0, #0x1b - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0xdef09abc - test_h_gr r3, 0x56781234 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsll.cgs b/sim/testsuite/sim/arm/iwmmxt/wsll.cgs deleted file mode 100644 index 17d7893..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wsll.cgs +++ /dev/null @@ -1,167 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WSLL -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wsll -wsll: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Halfword Logical Shift Left - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsllh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23406780 - test_h_gr r5, 0xabc0ef00 - - # Test Halfword Aritc Shift Left by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr1, r2 - tmcrr wr1, r3, r4 - - wsllhg wr1, wr0, wcgr1 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr1 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x23406780 - test_h_gr r4, 0xabc0ef00 - - # Test Word Logical Shift Left - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsllw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456780 - test_h_gr r5, 0xabcdef00 - - # Test Word Logical Shift Left by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr2, r2 - tmcrr wr1, r3, r4 - - wsllwg wr1, wr0, wcgr2 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr2 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x23456780 - test_h_gr r4, 0xabcdef00 - - # Test Double Word Logical Shift Left - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdefc - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wslld wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdefc - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x23456780 - test_h_gr r5, 0xabcdefc1 - - # Test Double Word Logical Shift Left by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdefc - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr3, r2 - tmcrr wr1, r3, r4 - - wslldg wr1, wr0, wcgr3 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr3 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdefc - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x23456780 - test_h_gr r4, 0xabcdefc1 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsra.cgs b/sim/testsuite/sim/arm/iwmmxt/wsra.cgs deleted file mode 100644 index db998bb..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wsra.cgs +++ /dev/null @@ -1,167 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WSRA -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wsra -wsra: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Halfword Arithmetic Shift Right - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsrah wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01230567 - test_h_gr r5, 0xf9abfdef - - # Test Halfword Arithmetic Shift Right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr1, r2 - tmcrr wr1, r3, r4 - - wsrahg wr1, wr0, wcgr1 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr1 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x01230567 - test_h_gr r4, 0xf9abfdef - - # Test Word Arithmetic Shift Right - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsraw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0xf9abcdef - - # Test Word Arithmetic Shift Right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr2, r2 - tmcrr wr1, r3, r4 - - wsrawg wr1, wr0, wcgr2 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr2 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x01234567 - test_h_gr r4, 0xf9abcdef - - # Test Double Word Arithmetic Shift Right - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdefc - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsrad wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdefc - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0xc1234567 - test_h_gr r5, 0xf9abcdef - - # Test Double Word Arithmetic Shift Right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdefc - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr3, r2 - tmcrr wr1, r3, r4 - - wsradg wr1, wr0, wcgr3 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr3 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdefc - test_h_gr r2, 0x11111104 - test_h_gr r3, 0xc1234567 - test_h_gr r4, 0xf9abcdef - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs b/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs deleted file mode 100644 index 416a464..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs +++ /dev/null @@ -1,167 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WSRL -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wsrl -wsrl: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Halfword Logical Shift Right - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsrlh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01230567 - test_h_gr r5, 0x09ab0def - - # Test Halfword Logical Shift Right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr1, r2 - tmcrr wr1, r3, r4 - - wsrlhg wr1, wr0, wcgr1 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr1 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x01230567 - test_h_gr r4, 0x09ab0def - - # Test Word Logical Shift Right - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsrlw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x09abcdef - - # Test Word Logical Shift Right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr2, r2 - tmcrr wr1, r3, r4 - - wsrlwg wr1, wr0, wcgr2 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr2 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x01234567 - test_h_gr r4, 0x09abcdef - - # Test Double Word Logical Shift Right - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdefc - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsrld wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdefc - test_h_gr r2, 0x11111104 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0xc1234567 - test_h_gr r5, 0x09abcdef - - # Test Double Word Logical Shift Right by CG register - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdefc - mvi_h_gr r2, 0x11111104 - mvi_h_gr r3, 0 - mvi_h_gr r4, 0 - - tmcrr wr0, r0, r1 - tmcr wcgr3, r2 - tmcrr wr1, r3, r4 - - wsrldg wr1, wr0, wcgr3 - - tmrrc r0, r1, wr0 - tmrc r2, wcgr3 - tmrrc r3, r4, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdefc - test_h_gr r2, 0x11111104 - test_h_gr r3, 0xc1234567 - test_h_gr r4, 0x09abcdef - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsub.cgs b/sim/testsuite/sim/arm/iwmmxt/wsub.cgs deleted file mode 100644 index b0e77be..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wsub.cgs +++ /dev/null @@ -1,251 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WSUB -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wsub -wsub: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsaturated Byte subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abcdef - - # Test Unsigned saturated Byte subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubbus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abcd00 - - # Test Signed saturated Byte subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubbss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abcdef - - # Test Unsaturated Halfword subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abccef - - # Test Unsigned saturated Halfword subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubhus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abccef - - # Test Signed saturated Halfword subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubhss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abccef - - # Test Unsaturated Word subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abccef - - # Test Unsigned saturated Word subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubwus wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abccef - - # Test Signed saturated Word subtraction - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcde00 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x11111111 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wsubwss wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcde00 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x11111111 - test_h_gr r4, 0x01234567 - test_h_gr r5, 0x89abccef - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs deleted file mode 100644 index 32a70f4..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs +++ /dev/null @@ -1,137 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEH -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wunpckeh -wunpckeh: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Unpacking - - mvi_h_gr r0, 0x12345687 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckehub wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345687 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00de00f0 - test_h_gr r3, 0x009a00bc - - # Test Signed Byte Unpacking - - mvi_h_gr r0, 0x12345687 - mvi_h_gr r1, 0x7abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckehsb wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345687 - test_h_gr r1, 0x7abcdef0 - test_h_gr r2, 0xffdefff0 - test_h_gr r3, 0x007affbc - - # Test Unsigned Halfword Unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckehuh wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x0000def0 - test_h_gr r3, 0x00009abc - - # Test Signed Halfword Unpacking - - mvi_h_gr r0, 0x12348678 - mvi_h_gr r1, 0x7abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckehsh wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12348678 - test_h_gr r1, 0x7abcdef0 - test_h_gr r2, 0xffffdef0 - test_h_gr r3, 0x00007abc - - # Test Unsigned Word Unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckehuw wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x9abcdef0 - test_h_gr r3, 0x00000000 - - # Test Signed Word Unpacking - - mvi_h_gr r0, 0x82345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckehsw wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x82345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x9abcdef0 - test_h_gr r3, 0xffffffff - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs deleted file mode 100644 index a6ffb4f..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs +++ /dev/null @@ -1,137 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEL -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wunpckel -wunpckel: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Unsigned Byte Unpacking - - mvi_h_gr r0, 0x12345687 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckelub wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345687 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00560087 - test_h_gr r3, 0x00120034 - - # Test Signed Byte Unpacking - - mvi_h_gr r0, 0x12345687 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckelsb wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345687 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x0056ff87 - test_h_gr r3, 0x00120034 - - # Test Unsigned Halfword Unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckeluh wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x00005678 - test_h_gr r3, 0x00001234 - - # Test Signed Halfword Unpacking - - mvi_h_gr r0, 0x12348678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckelsh wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12348678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0xffff8678 - test_h_gr r3, 0x00001234 - - # Test Unsigned Word Unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckeluw wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x00000000 - - # Test Signed Word Unpacking - - mvi_h_gr r0, 0x82345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0 - mvi_h_gr r3, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - - wunpckelsw wr1, wr0 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - - test_h_gr r0, 0x82345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x82345678 - test_h_gr r3, 0xffffffff - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs deleted file mode 100644 index 41fed0e..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs +++ /dev/null @@ -1,95 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIH -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wunpckih -wunpckih: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wunpckihb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x00de00f0 - test_h_gr r5, 0x009a00bc - - # Test Halfword unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wunpckihh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x0000def0 - test_h_gr r5, 0x00009abc - - # Test Word unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wunpckihw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x9abcdef0 - test_h_gr r5, 0x00000000 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs deleted file mode 100644 index 7bd7300..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs +++ /dev/null @@ -1,95 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIL -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wunpckil -wunpckil: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Byte unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wunpckilb wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x11561178 - test_h_gr r5, 0x11121134 - - # Test Halfword unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wunpckilh wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x11115678 - test_h_gr r5, 0x11111234 - - # Test Word unpacking - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wunpckilw wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x12345678 - test_h_gr r5, 0x11111111 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wxor.cgs b/sim/testsuite/sim/arm/iwmmxt/wxor.cgs deleted file mode 100644 index 95e1fc8..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wxor.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WXOR -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wxor -wxor: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - mvi_h_gr r2, 0x11111111 - mvi_h_gr r3, 0x00000000 - mvi_h_gr r4, 0 - mvi_h_gr r5, 0 - - tmcrr wr0, r0, r1 - tmcrr wr1, r2, r3 - tmcrr wr2, r4, r5 - - wxor wr2, wr0, wr1 - - tmrrc r0, r1, wr0 - tmrrc r2, r3, wr1 - tmrrc r4, r5, wr2 - - test_h_gr r0, 0x12345678 - test_h_gr r1, 0x9abcdef0 - test_h_gr r2, 0x11111111 - test_h_gr r3, 0x00000000 - test_h_gr r4, 0x03254769 - test_h_gr r5, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wzero.cgs b/sim/testsuite/sim/arm/iwmmxt/wzero.cgs deleted file mode 100644 index 78fa7c5..0000000 --- a/sim/testsuite/sim/arm/iwmmxt/wzero.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# Intel(r) Wireless MMX(tm) technology testcase for WZERO -# mach: xscale -# as: -mcpu=xscale+iwmmxt - - .include "testutils.inc" - - start - - .global wzero -wzero: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mvi_h_gr r0, 0x12345678 - mvi_h_gr r1, 0x9abcdef0 - - tmcrr wr0, r0, r1 - - wzero wr0 - - tmrrc r0, r1, wr0 - - test_h_gr r0, 0x00000000 - test_h_gr r1, 0x00000000 - - pass diff --git a/sim/testsuite/sim/arm/ldm.cgs b/sim/testsuite/sim/arm/ldm.cgs deleted file mode 100644 index 6831a83..0000000 --- a/sim/testsuite/sim/arm/ldm.cgs +++ /dev/null @@ -1,89 +0,0 @@ -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmda_wb -ldmda_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmda -ldmda: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmdb_wb -ldmdb_wb: - - pass -# arm testcase for ldm$cond .. -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmdb -ldmdb: - ldm0 .. - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmia_wb -ldmia_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmia -ldmia: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmib_wb -ldmib_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmib -ldmib: - - pass diff --git a/sim/testsuite/sim/arm/ldr.cgs b/sim/testsuite/sim/arm/ldr.cgs deleted file mode 100644 index 437b68c..0000000 --- a/sim/testsuite/sim/arm/ldr.cgs +++ /dev/null @@ -1,192 +0,0 @@ -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_dec_imm_offset -ldr_post_dec_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_dec_nonpriv_imm_offset -ldr_post_dec_nonpriv_imm_offset: - ldr0t pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_dec_nonpriv_reg_offset -ldr_post_dec_nonpriv_reg_offset: - ldr0t pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_dec_reg_offset -ldr_post_dec_reg_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_inc_imm_offset -ldr_post_inc_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_inc_nonpriv_imm_offset -ldr_post_inc_nonpriv_imm_offset: - ldr0t pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_inc_nonpriv_reg_offset -ldr_post_inc_nonpriv_reg_offset: - ldr0t pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_post_inc_reg_offset -ldr_post_inc_reg_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_dec_imm_offset -ldr_pre_dec_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_dec_reg_offset -ldr_pre_dec_reg_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_dec_wb_imm_offset -ldr_pre_dec_wb_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_dec_wb_reg_offset -ldr_pre_dec_wb_reg_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_inc_imm_offset -ldr_pre_inc_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_inc_reg_offset -ldr_pre_inc_reg_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_inc_wb_imm_offset -ldr_pre_inc_wb_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pre_inc_wb_reg_offset -ldr_pre_inc_wb_reg_offset: - ldr0 pc,??? - - pass diff --git a/sim/testsuite/sim/arm/ldrb.cgs b/sim/testsuite/sim/arm/ldrb.cgs deleted file mode 100644 index b09880c..0000000 --- a/sim/testsuite/sim/arm/ldrb.cgs +++ /dev/null @@ -1,192 +0,0 @@ -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_dec_imm_offset -ldrb_post_dec_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}bt $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_dec_nonpriv_imm_offset -ldrb_post_dec_nonpriv_imm_offset: - ldr0bt pc,??? - - pass -# arm testcase for ldr${cond}bt $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_dec_nonpriv_reg_offset -ldrb_post_dec_nonpriv_reg_offset: - ldr0bt pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_dec_reg_offset -ldrb_post_dec_reg_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_inc_imm_offset -ldrb_post_inc_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}bt $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_inc_nonpriv_imm_offset -ldrb_post_inc_nonpriv_imm_offset: - ldr0bt pc,??? - - pass -# arm testcase for ldr${cond}bt $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_inc_nonpriv_reg_offset -ldrb_post_inc_nonpriv_reg_offset: - ldr0bt pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_post_inc_reg_offset -ldrb_post_inc_reg_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_dec_imm_offset -ldrb_pre_dec_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_dec_reg_offset -ldrb_pre_dec_reg_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_dec_wb_imm_offset -ldrb_pre_dec_wb_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_dec_wb_reg_offset -ldrb_pre_dec_wb_reg_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_inc_imm_offset -ldrb_pre_inc_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_inc_reg_offset -ldrb_pre_inc_reg_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_inc_wb_imm_offset -ldrb_pre_inc_wb_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_pre_inc_wb_reg_offset -ldrb_pre_inc_wb_reg_offset: - ldr0b pc,??? - - pass diff --git a/sim/testsuite/sim/arm/ldrh.cgs b/sim/testsuite/sim/arm/ldrh.cgs deleted file mode 100644 index 16a4323..0000000 --- a/sim/testsuite/sim/arm/ldrh.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_post_dec_imm_offset -ldrh_post_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_post_dec_reg_offset -ldrh_post_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_post_inc_imm_offset -ldrh_post_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_post_inc_reg_offset -ldrh_post_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_dec_imm_offset -ldrh_pre_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_dec_reg_offset -ldrh_pre_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_dec_wb_imm_offset -ldrh_pre_dec_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_dec_wb_reg_offset -ldrh_pre_dec_wb_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_inc_imm_offset -ldrh_pre_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_inc_reg_offset -ldrh_pre_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_inc_wb_imm_offset -ldrh_pre_inc_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_pre_inc_wb_reg_offset -ldrh_pre_inc_wb_reg_offset: - - pass diff --git a/sim/testsuite/sim/arm/ldrsb.cgs b/sim/testsuite/sim/arm/ldrsb.cgs deleted file mode 100644 index 4d08f4c..0000000 --- a/sim/testsuite/sim/arm/ldrsb.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_post_dec_imm_offset -ldrsb_post_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_post_dec_reg_offset -ldrsb_post_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_post_inc_imm_offset -ldrsb_post_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_post_inc_reg_offset -ldrsb_post_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_dec_imm_offset -ldrsb_pre_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_dec_reg_offset -ldrsb_pre_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_dec_wb_imm_offset -ldrsb_pre_dec_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_dec_wb_reg_offset -ldrsb_pre_dec_wb_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_inc_imm_offset -ldrsb_pre_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_inc_reg_offset -ldrsb_pre_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_inc_wb_imm_offset -ldrsb_pre_inc_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsb_pre_inc_wb_reg_offset -ldrsb_pre_inc_wb_reg_offset: - - pass diff --git a/sim/testsuite/sim/arm/ldrsh.cgs b/sim/testsuite/sim/arm/ldrsh.cgs deleted file mode 100644 index 5a6e7c7..0000000 --- a/sim/testsuite/sim/arm/ldrsh.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_post_dec_imm_offset -ldrsh_post_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_post_dec_reg_offset -ldrsh_post_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_post_inc_imm_offset -ldrsh_post_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_post_inc_reg_offset -ldrsh_post_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_dec_imm_offset -ldrsh_pre_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_dec_reg_offset -ldrsh_pre_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_dec_wb_imm_offset -ldrsh_pre_dec_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_dec_wb_reg_offset -ldrsh_pre_dec_wb_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_inc_imm_offset -ldrsh_pre_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_inc_reg_offset -ldrsh_pre_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_inc_wb_imm_offset -ldrsh_pre_inc_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrsh_pre_inc_wb_reg_offset -ldrsh_pre_inc_wb_reg_offset: - - pass diff --git a/sim/testsuite/sim/arm/misaligned1.ms b/sim/testsuite/sim/arm/misaligned1.ms deleted file mode 100644 index 69fda47..0000000 --- a/sim/testsuite/sim/arm/misaligned1.ms +++ /dev/null @@ -1,61 +0,0 @@ -# Test LDR instructions with offsets misaligned by 1 byte. -# mach(): all - - .macro invalid -# This is "undefined" but it's not properly decoded yet. - .word 0x07ffffff -# This is stc which isn't recognized yet. - stc 0,cr0,[r0] - .endm - - .global _start -_start: -# Run some simple insns to confirm the engine is at least working. - nop - -# Skip over output text. - bl do_test - -pass: - .asciz "pass\n" - .p2align 2 - -do_test: - mov r4, r14 - bl continue -word1: - .word 0x5555 -continue: - ldr r6, [r14, #1] - ldr r7, word2 - cmp r6, r7 - # Failed. - bne done - -output_next: -# Output a character (in arm mode). - mov r0,#3 - mov r1,r4 - swi #0x123456 - -# Load next character, see if done. - add r4,r4,#1 - sub r3,r3,r3 - ldrb r5,[r4,r3] - teq r5,#0 - bne output_next - -done: - mov r0,#0x18 - ldr r1,exit_code - swi #0x123456 - -# If that fails, try to die with an invalid insn. - invalid - -exit_code: - .word 0x20026 - .word 0xFFFFFFFF -word2: - .word 0x55000055 - .word 0xFFFFFFFF diff --git a/sim/testsuite/sim/arm/misaligned2.ms b/sim/testsuite/sim/arm/misaligned2.ms deleted file mode 100644 index 3a03326..0000000 --- a/sim/testsuite/sim/arm/misaligned2.ms +++ /dev/null @@ -1,60 +0,0 @@ -# Test LDR instructions with offsets misaligned by 2 bytes. -# mach(): all - - .macro invalid -# This is "undefined" but it's not properly decoded yet. - .word 0x07ffffff -# This is stc which isn't recognized yet. - stc 0,cr0,[r0] - .endm - - .global _start -_start: -# Run some simple insns to confirm the engine is at least working. - nop - -# Skip over output text. - bl do_test - -pass: - .asciz "pass\n" - .p2align 2 - -do_test: - mov r4, r14 - bl continue -word1: - .word 0x5555 -continue: - ldr r6, [r14, #2] - ldr r7, word2 - cmp r6, r7 - # Failed. - bne done - -output_next: -# Output a character (in arm mode). - mov r0,#3 - mov r1,r4 - swi #0x123456 - -# Load next character, see if done. - add r4,r4,#1 - sub r3,r3,r3 - ldrb r5,[r4,r3] - teq r5,#0 - bne output_next - -done: - mov r0,#0x18 - ldr r1,exit_code - swi #0x123456 - -# If that fails, try to die with an invalid insn. - invalid - -exit_code: - .word 0x20026 - -word2: - .word 0x55550000 diff --git a/sim/testsuite/sim/arm/misaligned3.ms b/sim/testsuite/sim/arm/misaligned3.ms deleted file mode 100644 index bf2d9f1..0000000 --- a/sim/testsuite/sim/arm/misaligned3.ms +++ /dev/null @@ -1,62 +0,0 @@ -# Test LDR instructions with offsets misaligned by 3 bytes. -# mach(): all - - .macro invalid -# This is "undefined" but it's not properly decoded yet. - .word 0x07ffffff -# This is stc which isn't recognized yet. - stc 0,cr0,[r0] - .endm - - .global _start -_start: -# Run some simple insns to confirm the engine is at least working. - nop - -# Skip over output text. - bl do_test - -pass: - .asciz "pass\n" - .p2align 2 - -do_test: - mov r4, r14 - bl continue -word1: - .word 0x5555 -continue: - ldr r6, [r14, #3] - ldr r7, word2 - cmp r6, r7 - # Failed. - bne done - -output_next: -# Output a character (in arm mode). - mov r0,#3 - mov r1,r4 - swi #0x123456 - -# Load next character, see if done. - add r4,r4,#1 - sub r3,r3,r3 - ldrb r5,[r4,r3] - teq r5,#0 - bne output_next - -done: - mov r0,#0x18 - ldr r1,exit_code - swi #0x123456 - -# If that fails, try to die with an invalid insn. - invalid - -exit_code: - .word 0x20026 - - .word 0xFFFFFFFF -word2: - .word 0x555500 - .word 0xFFFFFFFF diff --git a/sim/testsuite/sim/arm/misc.exp b/sim/testsuite/sim/arm/misc.exp deleted file mode 100644 index bc36ca8..0000000 --- a/sim/testsuite/sim/arm/misc.exp +++ /dev/null @@ -1,20 +0,0 @@ -# Miscellaneous ARM simulator testcases - -if { [istarget arm*-*-*] } { - # load support procs - # load_lib cgen.exp - - # all machines - set all_machs "arm7tdmi" - - # The .ms suffix is for "miscellaneous .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/arm/mla.cgs b/sim/testsuite/sim/arm/mla.cgs deleted file mode 100644 index c82dd0c..0000000 --- a/sim/testsuite/sim/arm/mla.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mla$cond${set-cc?} ${mul-rd},$rm,$rs,${mul-rn} -# mach: unfinished - - .include "testutils.inc" - - start - - .global mla -mla: - mla00 pc,pc,pc,pc - - pass diff --git a/sim/testsuite/sim/arm/mov.cgs b/sim/testsuite/sim/arm/mov.cgs deleted file mode 100644 index d2a83d3..0000000 --- a/sim/testsuite/sim/arm/mov.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for mov$cond${set-cc?} $rd,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov_imm -mov_imm: - mov00 pc,0 - - pass -# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov_reg_imm_shift -mov_reg_imm_shift: - mov00 pc,pc,pc,lsl 0 - - pass -# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov_reg_reg_shift -mov_reg_reg_shift: - mov00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/movw-movt.ms b/sim/testsuite/sim/arm/movw-movt.ms deleted file mode 100644 index 1be815d..0000000 --- a/sim/testsuite/sim/arm/movw-movt.ms +++ /dev/null @@ -1,53 +0,0 @@ -# output(): Hello, world.\n -# mach(): all - -# This is a test for movw & movt instructions. -# It emits hello world if movw & movt works appropriately. - - .macro invalid -# This is "undefined" but it's not properly decoded yet. - .word 0x07ffffff -# This is stc which isn't recognized yet. - stc 0,cr0,[r0] - .endm - - .global _start -_start: -# Run some simple insns to confirm the engine is at least working. - nop - -# Skip over output text. - - bl skip_output - -hello_text: - .asciz "Hello, world.\n" - - .p2align 2 -skip_output: - movw r4, #:lower16:hello_text - movt r4, #:upper16:hello_text - -output_next: -# Output a character - mov r0,#3 - mov r1,r4 - swi #0x123456 - -# Load next character, see if done. - add r4,r4,#1 - sub r3,r3,r3 - ldrb r5,[r4,r3] - teq r5,#0 - bne output_next - -done: - mov r0,#0x18 - ldr r1,exit_code - swi #0x123456 - -# If that fails, try to die with an invalid insn. - invalid - -exit_code: - .word 0x20026 diff --git a/sim/testsuite/sim/arm/mrs.cgs b/sim/testsuite/sim/arm/mrs.cgs deleted file mode 100644 index 22c5e95..0000000 --- a/sim/testsuite/sim/arm/mrs.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# arm testcase for mrs$cond $rd,cpsr -# mach: unfinished - - .include "testutils.inc" - - start - - .global mrs_c -mrs_c: - mrs0 pc,cpsr - - pass -# arm testcase for mrs$cond $rd,spsr -# mach: unfinished - - .include "testutils.inc" - - start - - .global mrs_s -mrs_s: - mrs0 pc,spsr - - pass diff --git a/sim/testsuite/sim/arm/msr.cgs b/sim/testsuite/sim/arm/msr.cgs deleted file mode 100644 index c79f0bd..0000000 --- a/sim/testsuite/sim/arm/msr.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# arm testcase for msr$cond cpsr,$rm -# mach: unfinished - - .include "testutils.inc" - - start - - .global msr_c -msr_c: - msr0 cpsr,pc - - pass -# arm testcase for msr$cond spsr,$rm -# mach: unfinished - - .include "testutils.inc" - - start - - .global msr_s -msr_s: - msr0 spsr,pc - - pass diff --git a/sim/testsuite/sim/arm/mul.cgs b/sim/testsuite/sim/arm/mul.cgs deleted file mode 100644 index 4f0a926..0000000 --- a/sim/testsuite/sim/arm/mul.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mul$cond${set-cc?} ${mul-rd},$rm,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global mul -mul: - mul00 pc,pc,pc - - pass diff --git a/sim/testsuite/sim/arm/mvn.cgs b/sim/testsuite/sim/arm/mvn.cgs deleted file mode 100644 index 92fd3a4..0000000 --- a/sim/testsuite/sim/arm/mvn.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for mvn$cond${set-cc?} $rd,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global mvn_imm -mvn_imm: - mvn00 pc,0 - - pass -# arm testcase for mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global mvn_reg_imm_shift -mvn_reg_imm_shift: - mvn00 pc,pc,pc,lsl 0 - - pass -# arm testcase for mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global mvn_reg_reg_shift -mvn_reg_reg_shift: - mvn00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/orr.cgs b/sim/testsuite/sim/arm/orr.cgs deleted file mode 100644 index 3fc67ad..0000000 --- a/sim/testsuite/sim/arm/orr.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for orr$cond${set-cc?} $rd,$rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global orr_imm -orr_imm: - orr00 pc,pc,0 - - pass -# arm testcase for orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global orr_reg_imm_shift -orr_reg_imm_shift: - orr00 pc,pc,pc,lsl 0 - - pass -# arm testcase for orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global orr_reg_reg_shift -orr_reg_reg_shift: - orr00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/rsb.cgs b/sim/testsuite/sim/arm/rsb.cgs deleted file mode 100644 index 14edc35..0000000 --- a/sim/testsuite/sim/arm/rsb.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for rsb$cond${set-cc?} $rd,$rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global rsb_imm -rsb_imm: - rsb00 pc,pc,0 - - pass -# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global rsb_reg_imm_shift -rsb_reg_imm_shift: - rsb00 pc,pc,pc,lsl 0 - - pass -# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global rsb_reg_reg_shift -rsb_reg_reg_shift: - rsb00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/rsc.cgs b/sim/testsuite/sim/arm/rsc.cgs deleted file mode 100644 index 078fbcc..0000000 --- a/sim/testsuite/sim/arm/rsc.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for rsc$cond${set-cc?} $rd,$rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global rsc_imm -rsc_imm: - rsc00 pc,pc,0 - - pass -# arm testcase for rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global rsc_reg_imm_shift -rsc_reg_imm_shift: - rsc00 pc,pc,pc,lsl 0 - - pass -# arm testcase for rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global rsc_reg_reg_shift -rsc_reg_reg_shift: - rsc00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/sbc.cgs b/sim/testsuite/sim/arm/sbc.cgs deleted file mode 100644 index 9462702..0000000 --- a/sim/testsuite/sim/arm/sbc.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for sbc$cond${set-cc?} $rd,$rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global sbc_imm -sbc_imm: - sbc00 pc,pc,0 - - pass -# arm testcase for sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global sbc_reg_imm_shift -sbc_reg_imm_shift: - sbc00 pc,pc,pc,lsl 0 - - pass -# arm testcase for sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global sbc_reg_reg_shift -sbc_reg_reg_shift: - sbc00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/smlal.cgs b/sim/testsuite/sim/arm/smlal.cgs deleted file mode 100644 index 4ad1373..0000000 --- a/sim/testsuite/sim/arm/smlal.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for smlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global smlal -smlal: - smlal00 pc,pc,pc,pc - - pass diff --git a/sim/testsuite/sim/arm/smull.cgs b/sim/testsuite/sim/arm/smull.cgs deleted file mode 100644 index 22e3960..0000000 --- a/sim/testsuite/sim/arm/smull.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for smull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global smull -smull: - smull00 pc,pc,pc,pc - - pass diff --git a/sim/testsuite/sim/arm/stm.cgs b/sim/testsuite/sim/arm/stm.cgs deleted file mode 100644 index c381216..0000000 --- a/sim/testsuite/sim/arm/stm.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmda_wb -stmda_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmda -stmda: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmdb_wb -stmdb_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmdb -stmdb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmia_wb -stmia_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmia -stmia: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmib_wb -stmib_wb: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmib -stmib: - - pass diff --git a/sim/testsuite/sim/arm/str.cgs b/sim/testsuite/sim/arm/str.cgs deleted file mode 100644 index 82c683b..0000000 --- a/sim/testsuite/sim/arm/str.cgs +++ /dev/null @@ -1,192 +0,0 @@ -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_dec_imm_offset -str_post_dec_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_dec_nonpriv_imm_offset -str_post_dec_nonpriv_imm_offset: - ldr0t pc,??? - - pass -# arm testcase for str${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_dec_nonpriv_reg_offset -str_post_dec_nonpriv_reg_offset: - str0t pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_dec_reg_offset -str_post_dec_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_inc_imm_offset -str_post_inc_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_inc_nonpriv_imm_offset -str_post_inc_nonpriv_imm_offset: - ldr0t pc,??? - - pass -# arm testcase for str${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_inc_nonpriv_reg_offset -str_post_inc_nonpriv_reg_offset: - str0t pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_post_inc_reg_offset -str_post_inc_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_dec_imm_offset -str_pre_dec_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_dec_reg_offset -str_pre_dec_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_dec_wb_imm_offset -str_pre_dec_wb_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_dec_wb_reg_offset -str_pre_dec_wb_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_inc_imm_offset -str_pre_inc_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_inc_reg_offset -str_pre_inc_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_inc_wb_imm_offset -str_pre_inc_wb_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_pre_inc_wb_reg_offset -str_pre_inc_wb_reg_offset: - str0 pc,??? - - pass diff --git a/sim/testsuite/sim/arm/strb.cgs b/sim/testsuite/sim/arm/strb.cgs deleted file mode 100644 index 875a649..0000000 --- a/sim/testsuite/sim/arm/strb.cgs +++ /dev/null @@ -1,192 +0,0 @@ -# arm testcase for ldr${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_dec_imm_offset -strb_post_dec_imm_offset: - ldr0b pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_dec_nonpriv_imm_offset -strb_post_dec_nonpriv_imm_offset: - ldr0t pc,??? - - pass -# arm testcase for str${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_dec_nonpriv_reg_offset -strb_post_dec_nonpriv_reg_offset: - str0t pc,??? - - pass -# arm testcase for str${cond}b $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_dec_reg_offset -strb_post_dec_reg_offset: - str0b pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_inc_imm_offset -strb_post_inc_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for ldr${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_inc_nonpriv_imm_offset -strb_post_inc_nonpriv_imm_offset: - ldr0t pc,??? - - pass -# arm testcase for str${cond}t $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_inc_nonpriv_reg_offset -strb_post_inc_nonpriv_reg_offset: - str0t pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_post_inc_reg_offset -strb_post_inc_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_dec_imm_offset -strb_pre_dec_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_dec_reg_offset -strb_pre_dec_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_dec_wb_imm_offset -strb_pre_dec_wb_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_dec_wb_reg_offset -strb_pre_dec_wb_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_inc_imm_offset -strb_pre_inc_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_inc_reg_offset -strb_pre_inc_reg_offset: - str0 pc,??? - - pass -# arm testcase for ldr${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_inc_wb_imm_offset -strb_pre_inc_wb_imm_offset: - ldr0 pc,??? - - pass -# arm testcase for str${cond} $rd,??? -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_pre_inc_wb_reg_offset -strb_pre_inc_wb_reg_offset: - str0 pc,??? - - pass diff --git a/sim/testsuite/sim/arm/strh.cgs b/sim/testsuite/sim/arm/strh.cgs deleted file mode 100644 index e111d48..0000000 --- a/sim/testsuite/sim/arm/strh.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_post_dec_imm_offset -strh_post_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_post_dec_reg_offset -strh_post_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_post_inc_imm_offset -strh_post_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_post_inc_reg_offset -strh_post_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_dec_imm_offset -strh_pre_dec_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_dec_reg_offset -strh_pre_dec_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_dec_wb_imm_offset -strh_pre_dec_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_dec_wb_reg_offset -strh_pre_dec_wb_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_inc_imm_offset -strh_pre_inc_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_inc_reg_offset -strh_pre_inc_reg_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_inc_wb_imm_offset -strh_pre_inc_wb_imm_offset: - - pass -# arm testcase for FIXME -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_pre_inc_wb_reg_offset -strh_pre_inc_wb_reg_offset: - - pass diff --git a/sim/testsuite/sim/arm/sub.cgs b/sim/testsuite/sim/arm/sub.cgs deleted file mode 100644 index 50f222c..0000000 --- a/sim/testsuite/sim/arm/sub.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for sub$cond${set-cc?} $rd,$rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global sub_imm -sub_imm: - sub00 pc,pc,0 - - pass -# arm testcase for sub$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global sub_reg_imm_shift -sub_reg_imm_shift: - sub00 pc,pc,pc,lsl 0 - - pass -# arm testcase for sub$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global sub_reg_reg_shift -sub_reg_reg_shift: - sub00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/swi.cgs b/sim/testsuite/sim/arm/swi.cgs deleted file mode 100644 index 0c23d43..0000000 --- a/sim/testsuite/sim/arm/swi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for swi$cond ${swi-comment} -# mach: unfinished - - .include "testutils.inc" - - start - - .global swi -swi: - swi0 0 - - pass diff --git a/sim/testsuite/sim/arm/swp.cgs b/sim/testsuite/sim/arm/swp.cgs deleted file mode 100644 index f965ef2..0000000 --- a/sim/testsuite/sim/arm/swp.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for swp$cond $rd,$rm,[$rn] -# mach: unfinished - - .include "testutils.inc" - - start - - .global swp -swp: - swp0 pc,pc,[pc] - - pass diff --git a/sim/testsuite/sim/arm/swpb.cgs b/sim/testsuite/sim/arm/swpb.cgs deleted file mode 100644 index 6f8a076..0000000 --- a/sim/testsuite/sim/arm/swpb.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for swpb${cond}b $rd,$rm,[$rn] -# mach: unfinished - - .include "testutils.inc" - - start - - .global swpb -swpb: - swpb0b pc,pc,[pc] - - pass diff --git a/sim/testsuite/sim/arm/teq.cgs b/sim/testsuite/sim/arm/teq.cgs deleted file mode 100644 index 6c69347..0000000 --- a/sim/testsuite/sim/arm/teq.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for teq${cond}${set-cc?} $rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global teq_imm -teq_imm: - teq00 pc,0 - - pass -# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global teq_reg_imm_shift -teq_reg_imm_shift: - teq00 pc,pc,pc,lsl 0 - - pass -# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global teq_reg_reg_shift -teq_reg_reg_shift: - teq00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/testutils.inc b/sim/testsuite/sim/arm/testutils.inc deleted file mode 100644 index ae49db8..0000000 --- a/sim/testsuite/sim/arm/testutils.inc +++ /dev/null @@ -1,118 +0,0 @@ -# r0-r3 are used as tmps, consider them call clobbered by these macros. -# This uses the angel rom monitor calls. -# ??? How do we use the \@ facility of .macros ??? -# @ is the comment char! - - .macro mvi_h_gr reg, val - ldr \reg,[pc] - b . + 8 - .word \val - .endm - - .macro mvaddr_h_gr reg, addr - ldr \reg,[pc] - b . + 8 - .word \addr - .endm - - .macro start - .data -failmsg: - .asciz "fail\n" -passmsg: - .asciz "pass\n" - .text - -do_pass: - ldr r1, passmsg_addr - mov r0, #4 - swi #0x123456 - exit 0 -passmsg_addr: - .word passmsg - -do_fail: - ldr r1, failmsg_addr - mov r0, #4 - swi #0x123456 - exit 1 -failmsg_addr: - .word failmsg - - .global _start -_start: - .endm - -# *** Other macros know pass/fail are 4 bytes in size! Yuck. - - .macro pass - b do_pass - .endm - - .macro fail - b do_fail - .endm - - .macro exit rc - # ??? This works with the ARMulator but maybe not others. - #mov r0, #\rc - #swi #1 - # This seems to be portable (though it ignores rc). - mov r0,#0x18 - mvi_h_gr r1, 0x20026 - swi #0x123456 - # If that returns, punt with a sigill. - stc 0,cr0,[r0] - .endm - -# Other macros know this only clobbers r0. -# WARNING: It also clobbers the condition codes (FIXME). - .macro test_h_gr reg, val - mvaddr_h_gr r0, \val - cmp \reg, r0 - beq . + 8 - fail - .endm - - .macro mvi_h_cnvz c, n, v, z - mov r0, #0 - .if \c - orr r0, r0, #0x20000000 - .endif - .if \n - orr r0, r0, #0x80000000 - .endif - .if \v - orr r0, r0, #0x10000000 - .endif - .if \z - orr r0, r0, #0x40000000 - .endif - mrs r1, cpsr - bic r1, r1, #0xf0000000 - orr r1, r1, r0 - msr cpsr, r1 - # ??? nops needed - .endm - -# ??? Preserve condition codes? - .macro test_h_cnvz c, n, v, z - mov r0, #0 - .if \c - orr r0, r0, #0x20000000 - .endif - .if \n - orr r0, r0, #0x80000000 - .endif - .if \v - orr r0, r0, #0x10000000 - .endif - .if \z - orr r0, r0, #0x40000000 - .endif - mrs r1, cpsr - and r1, r1, #0xf0000000 - cmp r0, r1 - beq . + 8 - fail - .endm diff --git a/sim/testsuite/sim/arm/thumb/adc.cgs b/sim/testsuite/sim/arm/thumb/adc.cgs deleted file mode 100644 index 58d74c1..0000000 --- a/sim/testsuite/sim/arm/thumb/adc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for adc $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_adc -alu_adc: - adc r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs deleted file mode 100644 index 0307acc..0000000 --- a/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add $hd,$hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global add_hd_hs -add_hd_hs: - add r8,r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs deleted file mode 100644 index ca080f7..0000000 --- a/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add $hd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global add_hd_rs -add_hd_rs: - add r8,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs deleted file mode 100644 index 46373a0..0000000 --- a/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add $rd,$hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global add_rd_hs -add_rd_hs: - add r0,r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/add-sp.cgs b/sim/testsuite/sim/arm/thumb/add-sp.cgs deleted file mode 100644 index 54efa2a..0000000 --- a/sim/testsuite/sim/arm/thumb/add-sp.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add sp,#$sword7 -# mach: unfinished - - .include "testutils.inc" - - start - - .global add_sp -add_sp: - add sp,#0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/add.cgs b/sim/testsuite/sim/arm/thumb/add.cgs deleted file mode 100644 index 63cc20c..0000000 --- a/sim/testsuite/sim/arm/thumb/add.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add $rd,$rs,$rn -# mach: unfinished - - .include "testutils.inc" - - start - - .global add -add: - add r0,r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/addi.cgs b/sim/testsuite/sim/arm/thumb/addi.cgs deleted file mode 100644 index 00ec76d..0000000 --- a/sim/testsuite/sim/arm/thumb/addi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add $rd,$rs,#$offset3 -# mach: unfinished - - .include "testutils.inc" - - start - - .global addi -addi: - add r0,r0,#0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/addi8.cgs b/sim/testsuite/sim/arm/thumb/addi8.cgs deleted file mode 100644 index d8e9f81..0000000 --- a/sim/testsuite/sim/arm/thumb/addi8.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add ${bit10-rd},#$offset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global addi8 -addi8: - add r0,#0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/allthumb.exp b/sim/testsuite/sim/arm/thumb/allthumb.exp deleted file mode 100644 index 4298663..0000000 --- a/sim/testsuite/sim/arm/thumb/allthumb.exp +++ /dev/null @@ -1,20 +0,0 @@ -# ARM simulator testsuite. - -if { [istarget arm*-*-*] } { - # load support procs (none yet) - # load_lib cgen.exp - - # all machines - set all_machs "arm7tdmi" - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/arm/thumb/and.cgs b/sim/testsuite/sim/arm/thumb/and.cgs deleted file mode 100644 index d67adf4..0000000 --- a/sim/testsuite/sim/arm/thumb/and.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for and $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_and -alu_and: - and r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/asr.cgs b/sim/testsuite/sim/arm/thumb/asr.cgs deleted file mode 100644 index 4d21dae..0000000 --- a/sim/testsuite/sim/arm/thumb/asr.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# arm testcase for asr $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_asr -alu_asr: - asr r0,r0 - -# FIXME: Also asr $rd,$rs,#$offset5 - - pass diff --git a/sim/testsuite/sim/arm/thumb/b.cgs b/sim/testsuite/sim/arm/thumb/b.cgs deleted file mode 100644 index ecae537..0000000 --- a/sim/testsuite/sim/arm/thumb/b.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for b $offset11 -# mach: unfinished - - .include "testutils.inc" - - start - - .global b -b: - b footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bcc.cgs b/sim/testsuite/sim/arm/thumb/bcc.cgs deleted file mode 100644 index 6c84458..0000000 --- a/sim/testsuite/sim/arm/thumb/bcc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bcc $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bcc -bcc: - bcc footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bcs.cgs b/sim/testsuite/sim/arm/thumb/bcs.cgs deleted file mode 100644 index a29a8fb..0000000 --- a/sim/testsuite/sim/arm/thumb/bcs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bcs $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bcs -bcs: - bcs footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/beq.cgs b/sim/testsuite/sim/arm/thumb/beq.cgs deleted file mode 100644 index 33f3748..0000000 --- a/sim/testsuite/sim/arm/thumb/beq.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for beq $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global beq -beq: - beq footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bge.cgs b/sim/testsuite/sim/arm/thumb/bge.cgs deleted file mode 100644 index 4eb543d..0000000 --- a/sim/testsuite/sim/arm/thumb/bge.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bge $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bge -bge: - bge footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bgt.cgs b/sim/testsuite/sim/arm/thumb/bgt.cgs deleted file mode 100644 index 1ffe092..0000000 --- a/sim/testsuite/sim/arm/thumb/bgt.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bgt $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bgt -bgt: - bgt footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bhi.cgs b/sim/testsuite/sim/arm/thumb/bhi.cgs deleted file mode 100644 index c9811c6..0000000 --- a/sim/testsuite/sim/arm/thumb/bhi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bhi $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bhi -bhi: - bhi footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bic.cgs b/sim/testsuite/sim/arm/thumb/bic.cgs deleted file mode 100644 index 6dca1ef..0000000 --- a/sim/testsuite/sim/arm/thumb/bic.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bic $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_bic -alu_bic: - bic r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/bl-hi.cgs b/sim/testsuite/sim/arm/thumb/bl-hi.cgs deleted file mode 100644 index c7400c7..0000000 --- a/sim/testsuite/sim/arm/thumb/bl-hi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bl-hi ${lbwl-hi} -# mach: unfinished - - .include "testutils.inc" - - start - - .global bl_hi -bl_hi: - bl-hi 0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/bl-lo.cgs b/sim/testsuite/sim/arm/thumb/bl-lo.cgs deleted file mode 100644 index ed76613..0000000 --- a/sim/testsuite/sim/arm/thumb/bl-lo.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bl-lo ${lbwl-lo} -# mach: unfinished - - .include "testutils.inc" - - start - - .global bl_lo -bl_lo: - bl-lo 0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/ble.cgs b/sim/testsuite/sim/arm/thumb/ble.cgs deleted file mode 100644 index e9c5a8f..0000000 --- a/sim/testsuite/sim/arm/thumb/ble.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ble $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global ble -ble: - ble footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bls.cgs b/sim/testsuite/sim/arm/thumb/bls.cgs deleted file mode 100644 index 483412b..0000000 --- a/sim/testsuite/sim/arm/thumb/bls.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bls $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bls -bls: - bls footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/blt.cgs b/sim/testsuite/sim/arm/thumb/blt.cgs deleted file mode 100644 index 0fbcbe8..0000000 --- a/sim/testsuite/sim/arm/thumb/blt.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for blt $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global blt -blt: - blt footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bmi.cgs b/sim/testsuite/sim/arm/thumb/bmi.cgs deleted file mode 100644 index 8f7558a..0000000 --- a/sim/testsuite/sim/arm/thumb/bmi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bmi $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bmi -bmi: - bmi footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bne.cgs b/sim/testsuite/sim/arm/thumb/bne.cgs deleted file mode 100644 index a5ac348..0000000 --- a/sim/testsuite/sim/arm/thumb/bne.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bne $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bne -bne: - bne footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bpl.cgs b/sim/testsuite/sim/arm/thumb/bpl.cgs deleted file mode 100644 index 8f64259..0000000 --- a/sim/testsuite/sim/arm/thumb/bpl.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bpl $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bpl -bpl: - bpl footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bvc.cgs b/sim/testsuite/sim/arm/thumb/bvc.cgs deleted file mode 100644 index bbd3af5..0000000 --- a/sim/testsuite/sim/arm/thumb/bvc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bvc $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bvc -bvc: - bvc footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bvs.cgs b/sim/testsuite/sim/arm/thumb/bvs.cgs deleted file mode 100644 index 8c9a551..0000000 --- a/sim/testsuite/sim/arm/thumb/bvs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bvs $soffset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global bvs -bvs: - bvs footext - - pass diff --git a/sim/testsuite/sim/arm/thumb/bx-hs.cgs b/sim/testsuite/sim/arm/thumb/bx-hs.cgs deleted file mode 100644 index d963387..0000000 --- a/sim/testsuite/sim/arm/thumb/bx-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bx $hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global bx_hs -bx_hs: - bx r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/bx-rs.cgs b/sim/testsuite/sim/arm/thumb/bx-rs.cgs deleted file mode 100644 index f6db8c8..0000000 --- a/sim/testsuite/sim/arm/thumb/bx-rs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for bx $rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global bx_rs -bx_rs: - bx r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/cmn.cgs b/sim/testsuite/sim/arm/thumb/cmn.cgs deleted file mode 100644 index 96d53a1..0000000 --- a/sim/testsuite/sim/arm/thumb/cmn.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for cmn $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_cmn -alu_cmn: - cmn r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs deleted file mode 100644 index 96a91a2..0000000 --- a/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for cmp $hd,$hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp_hd_hs -cmp_hd_hs: - cmp r8,r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs deleted file mode 100644 index 9fc4875..0000000 --- a/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for cmp $hd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp_hd_rs -cmp_hd_rs: - cmp r8,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs deleted file mode 100644 index e3f7a4a..0000000 --- a/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for cmp $rd,$hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp_rd_hs -cmp_rd_hs: - cmp r0,r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/cmp.cgs b/sim/testsuite/sim/arm/thumb/cmp.cgs deleted file mode 100644 index 7564099..0000000 --- a/sim/testsuite/sim/arm/thumb/cmp.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# arm testcase for cmp ${bit10-rd},#$offset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global cmp -cmp: - cmp r0,#0 - -# FIXME: Also: cmp $rd,$rs - - pass diff --git a/sim/testsuite/sim/arm/thumb/eor.cgs b/sim/testsuite/sim/arm/thumb/eor.cgs deleted file mode 100644 index cc6021c..0000000 --- a/sim/testsuite/sim/arm/thumb/eor.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for eor $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_eor -alu_eor: - eor r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/lda-pc.cgs b/sim/testsuite/sim/arm/thumb/lda-pc.cgs deleted file mode 100644 index 74407e2..0000000 --- a/sim/testsuite/sim/arm/thumb/lda-pc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add ${bit10-rd},pc,$word8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global lda_pc -lda_pc: - add r0,pc,0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/lda-sp.cgs b/sim/testsuite/sim/arm/thumb/lda-sp.cgs deleted file mode 100644 index ce2b62e..0000000 --- a/sim/testsuite/sim/arm/thumb/lda-sp.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add ${bit10-rd},sp,$word8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global lda_sp -lda_sp: - add r0,sp,0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldmia.cgs b/sim/testsuite/sim/arm/thumb/ldmia.cgs deleted file mode 100644 index 550031e..0000000 --- a/sim/testsuite/sim/arm/thumb/ldmia.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldmia $rb!,{$rlist} -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldmia -ldmia: - ldmia r0!,{0} - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldr-imm.cgs b/sim/testsuite/sim/arm/thumb/ldr-imm.cgs deleted file mode 100644 index a757f33..0000000 --- a/sim/testsuite/sim/arm/thumb/ldr-imm.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldr $rd,[$rb,#${offset5-7}] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_imm -ldr_imm: - ldr r0,[r0,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldr-pc.cgs b/sim/testsuite/sim/arm/thumb/ldr-pc.cgs deleted file mode 100644 index 8227562..0000000 --- a/sim/testsuite/sim/arm/thumb/ldr-pc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldr ${bit10-rd},[pc,#$word8] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_pc -ldr_pc: - ldr r0,[pc,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs b/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs deleted file mode 100644 index 11eee26..0000000 --- a/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldr ${bit10-rd},[sp,#$word8] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr_sprel -ldr_sprel: - ldr r0,[sp,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldr.cgs b/sim/testsuite/sim/arm/thumb/ldr.cgs deleted file mode 100644 index 03af925..0000000 --- a/sim/testsuite/sim/arm/thumb/ldr.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldr $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldr -ldr: - ldr r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs b/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs deleted file mode 100644 index c1eeafe..0000000 --- a/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldrb $rd,[$rb,#$offset5] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb_imm -ldrb_imm: - ldrb r0,[r0,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldrb.cgs b/sim/testsuite/sim/arm/thumb/ldrb.cgs deleted file mode 100644 index 316a10f..0000000 --- a/sim/testsuite/sim/arm/thumb/ldrb.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldrb $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrb -ldrb: - ldrb r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs b/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs deleted file mode 100644 index 81ea1e0..0000000 --- a/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldrh $rd,[$rb,#${offset5-6}] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh_imm -ldrh_imm: - ldrh r0,[r0,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldrh.cgs b/sim/testsuite/sim/arm/thumb/ldrh.cgs deleted file mode 100644 index 3ff8f4e..0000000 --- a/sim/testsuite/sim/arm/thumb/ldrh.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldrh $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldrh -ldrh: - ldrh r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldsb.cgs b/sim/testsuite/sim/arm/thumb/ldsb.cgs deleted file mode 100644 index e1612c9..0000000 --- a/sim/testsuite/sim/arm/thumb/ldsb.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldsb $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldsb -ldsb: - ldsb r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/ldsh.cgs b/sim/testsuite/sim/arm/thumb/ldsh.cgs deleted file mode 100644 index 46d49ac..0000000 --- a/sim/testsuite/sim/arm/thumb/ldsh.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ldsh $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global ldsh -ldsh: - ldsh r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/lsl.cgs b/sim/testsuite/sim/arm/thumb/lsl.cgs deleted file mode 100644 index 05222e7..0000000 --- a/sim/testsuite/sim/arm/thumb/lsl.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# arm testcase for lsl $rd,$rs,#$offset5 -# mach: unfinished - - .include "testutils.inc" - - start - - .global lsl -lsl: - lsl r0,r0,#0 - -# FIXME: Also lsl $rd,$rs - - pass diff --git a/sim/testsuite/sim/arm/thumb/lsr.cgs b/sim/testsuite/sim/arm/thumb/lsr.cgs deleted file mode 100644 index fe38fe0..0000000 --- a/sim/testsuite/sim/arm/thumb/lsr.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# arm testcase for lsr $rd,$rs,#$offset5 -# mach: unfinished - - .include "testutils.inc" - - start - - .global lsr -lsr: - lsr r0,r0,#0 - -# FIXME: Also lsr $rd,$rs - - pass diff --git a/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs deleted file mode 100644 index 2050908..0000000 --- a/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mov $hd,$hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov_hd_hs -mov_hd_hs: - mov r8,r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs deleted file mode 100644 index 3d229c3..0000000 --- a/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mov $hd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov_hd_rs -mov_hd_rs: - mov r8,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs deleted file mode 100644 index 0661dfa..0000000 --- a/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mov $rd,$hs -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov_rd_hs -mov_rd_hs: - mov r0,r8 - - pass diff --git a/sim/testsuite/sim/arm/thumb/mov.cgs b/sim/testsuite/sim/arm/thumb/mov.cgs deleted file mode 100644 index b497b0f..0000000 --- a/sim/testsuite/sim/arm/thumb/mov.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mov ${bit10-rd},#$offset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global mov -mov: - mov r0,#0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/mul.cgs b/sim/testsuite/sim/arm/thumb/mul.cgs deleted file mode 100644 index d160c56..0000000 --- a/sim/testsuite/sim/arm/thumb/mul.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mul $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_mul -alu_mul: - mul r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/mvn.cgs b/sim/testsuite/sim/arm/thumb/mvn.cgs deleted file mode 100644 index 606ce85..0000000 --- a/sim/testsuite/sim/arm/thumb/mvn.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for mvn $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_mvn -alu_mvn: - mvn r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/neg.cgs b/sim/testsuite/sim/arm/thumb/neg.cgs deleted file mode 100644 index 09f0c81..0000000 --- a/sim/testsuite/sim/arm/thumb/neg.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for neg $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_neg -alu_neg: - neg r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/orr.cgs b/sim/testsuite/sim/arm/thumb/orr.cgs deleted file mode 100644 index de6f688..0000000 --- a/sim/testsuite/sim/arm/thumb/orr.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for orr $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_orr -alu_orr: - orr r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/pop-pc.cgs b/sim/testsuite/sim/arm/thumb/pop-pc.cgs deleted file mode 100644 index 4579cad..0000000 --- a/sim/testsuite/sim/arm/thumb/pop-pc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for pop {${rlist-pc}} -# mach: unfinished - - .include "testutils.inc" - - start - - .global pop_pc -pop_pc: - pop {0} - - pass diff --git a/sim/testsuite/sim/arm/thumb/pop.cgs b/sim/testsuite/sim/arm/thumb/pop.cgs deleted file mode 100644 index b156e1d..0000000 --- a/sim/testsuite/sim/arm/thumb/pop.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for pop {$rlist} -# mach: unfinished - - .include "testutils.inc" - - start - - .global pop -pop: - pop {0} - - pass diff --git a/sim/testsuite/sim/arm/thumb/push-lr.cgs b/sim/testsuite/sim/arm/thumb/push-lr.cgs deleted file mode 100644 index ee700a4..0000000 --- a/sim/testsuite/sim/arm/thumb/push-lr.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for push {${rlist-lr}} -# mach: unfinished - - .include "testutils.inc" - - start - - .global push_lr -push_lr: - push {0} - - pass diff --git a/sim/testsuite/sim/arm/thumb/push.cgs b/sim/testsuite/sim/arm/thumb/push.cgs deleted file mode 100644 index ff94ca5..0000000 --- a/sim/testsuite/sim/arm/thumb/push.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for push {$rlist} -# mach: unfinished - - .include "testutils.inc" - - start - - .global push -push: - push {0} - - pass diff --git a/sim/testsuite/sim/arm/thumb/ror.cgs b/sim/testsuite/sim/arm/thumb/ror.cgs deleted file mode 100644 index 991fa66..0000000 --- a/sim/testsuite/sim/arm/thumb/ror.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for ror $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_ror -alu_ror: - ror r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/sbc.cgs b/sim/testsuite/sim/arm/thumb/sbc.cgs deleted file mode 100644 index 078b061..0000000 --- a/sim/testsuite/sim/arm/thumb/sbc.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for sbc $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_sbc -alu_sbc: - sbc r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/stmia.cgs b/sim/testsuite/sim/arm/thumb/stmia.cgs deleted file mode 100644 index 0e1c30c..0000000 --- a/sim/testsuite/sim/arm/thumb/stmia.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for stmia $rb!,{$rlist} -# mach: unfinished - - .include "testutils.inc" - - start - - .global stmia -stmia: - stmia r0!,{0} - - pass diff --git a/sim/testsuite/sim/arm/thumb/str-imm.cgs b/sim/testsuite/sim/arm/thumb/str-imm.cgs deleted file mode 100644 index ce75941..0000000 --- a/sim/testsuite/sim/arm/thumb/str-imm.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for str $rd,[$rb,#${offset5-7}] -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_imm -str_imm: - str r0,[r0,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/str-sprel.cgs b/sim/testsuite/sim/arm/thumb/str-sprel.cgs deleted file mode 100644 index 132edfb..0000000 --- a/sim/testsuite/sim/arm/thumb/str-sprel.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for str ${bit10-rd},[sp,#$word8] -# mach: unfinished - - .include "testutils.inc" - - start - - .global str_sprel -str_sprel: - str r0,[sp,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/str.cgs b/sim/testsuite/sim/arm/thumb/str.cgs deleted file mode 100644 index 073e20b..0000000 --- a/sim/testsuite/sim/arm/thumb/str.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for str $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global str -str: - str r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/strb-imm.cgs b/sim/testsuite/sim/arm/thumb/strb-imm.cgs deleted file mode 100644 index 2b5bcf7..0000000 --- a/sim/testsuite/sim/arm/thumb/strb-imm.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for strb $rd,[$rb,#$offset5] -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb_imm -strb_imm: - strb r0,[r0,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/strb.cgs b/sim/testsuite/sim/arm/thumb/strb.cgs deleted file mode 100644 index b7cb763..0000000 --- a/sim/testsuite/sim/arm/thumb/strb.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for strb $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global strb -strb: - strb r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/strh-imm.cgs b/sim/testsuite/sim/arm/thumb/strh-imm.cgs deleted file mode 100644 index 9500288..0000000 --- a/sim/testsuite/sim/arm/thumb/strh-imm.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for strh $rd,[$rb,#${offset5-6}] -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh_imm -strh_imm: - strh r0,[r0,#0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/strh.cgs b/sim/testsuite/sim/arm/thumb/strh.cgs deleted file mode 100644 index 13f3a0d..0000000 --- a/sim/testsuite/sim/arm/thumb/strh.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for strh $rd,[$rb,$ro] -# mach: unfinished - - .include "testutils.inc" - - start - - .global strh -strh: - strh r0,[r0,r0] - - pass diff --git a/sim/testsuite/sim/arm/thumb/sub-sp.cgs b/sim/testsuite/sim/arm/thumb/sub-sp.cgs deleted file mode 100644 index e676f58..0000000 --- a/sim/testsuite/sim/arm/thumb/sub-sp.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for add sp,#-$sword7 -# mach: unfinished - - .include "testutils.inc" - - start - - .global sub_sp -sub_sp: - add sp,#-0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/sub.cgs b/sim/testsuite/sim/arm/thumb/sub.cgs deleted file mode 100644 index 91cd7ab..0000000 --- a/sim/testsuite/sim/arm/thumb/sub.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for sub $rd,$rs,$rn -# mach: unfinished - - .include "testutils.inc" - - start - - .global sub -sub: - sub r0,r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/subi.cgs b/sim/testsuite/sim/arm/thumb/subi.cgs deleted file mode 100644 index 044efd0..0000000 --- a/sim/testsuite/sim/arm/thumb/subi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for sub $rd,$rs,#$offset3 -# mach: unfinished - - .include "testutils.inc" - - start - - .global subi -subi: - sub r0,r0,#0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/subi8.cgs b/sim/testsuite/sim/arm/thumb/subi8.cgs deleted file mode 100644 index 0c4d717..0000000 --- a/sim/testsuite/sim/arm/thumb/subi8.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for sub ${bit10-rd},#$offset8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global subi8 -subi8: - sub r0,#0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/swi.cgs b/sim/testsuite/sim/arm/thumb/swi.cgs deleted file mode 100644 index 1724c14..0000000 --- a/sim/testsuite/sim/arm/thumb/swi.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for swi $value8 -# mach: unfinished - - .include "testutils.inc" - - start - - .global swi -swi: - swi 0 - - pass diff --git a/sim/testsuite/sim/arm/thumb/testutils.inc b/sim/testsuite/sim/arm/thumb/testutils.inc deleted file mode 100644 index bdae29b..0000000 --- a/sim/testsuite/sim/arm/thumb/testutils.inc +++ /dev/null @@ -1,91 +0,0 @@ -# FIXME: wip, copied from ../testutils.inc -# r0-r3 are used as tmps, consider them call clobbered by these macros. -# This uses the angel rom monitor calls. -# ??? How do we use the \@ facility of .macros ??? -# @ is the comment char! - - .macro a_mvi_h_gr reg, val - ldr \reg,[pc] - b . + 8 - .word \val - .endm - - .macro mvaddr_h_gr reg, addr - ldr \reg,[pc] - b . + 8 - .word \val - .endm - - .macro start - .data -failmsg: - .asciz "fail\n" -passmsg: - .asciz "pass\n" - .text - -do_pass: - ldr r1, passmsg_addr - mov r0, #4 - swi #0x123456 - exit 0 -passmsg_addr: - .word passmsg - -do_fail: - ldr r1, failmsg_addr - mov r0, #4 - swi #0x123456 - exit 1 -failmsg_addr: - .word failmsg - - .global _start -_start: - .endm - -# *** Other macros know pass/fail are 4 bytes in size! Yuck. - - .macro pass - b do_pass - .endm - - .macro fail - b do_fail - .endm - - .macro exit rc - mov r1, #\rc - mov r0, #0x2a @ decimal 42 - swi #1 - # If that returns, punt with a sigill. - stc 0,cr0,[r0] - .endm - -# Other macros know this only clobbers r0. - .macro test_h_gr reg, val - mvaddr_h_gr r0, \val - cmp \reg, r0 - beq . + 8 - fail - .endm - - .macro mvi_h_cc c, n, v, z - ldi8 r0, 0 - ldi8 r1, 1 - .if xxx - cmp r0, r1 - .else - cmp r1, r0 - .endif - .endm - - .macro test_h_cc c, n, v, z - .if xxx - bc . + 8 - fail - .else - bnc . + 8 - fail - .endif - .endm diff --git a/sim/testsuite/sim/arm/thumb/tst.cgs b/sim/testsuite/sim/arm/thumb/tst.cgs deleted file mode 100644 index 068fccc..0000000 --- a/sim/testsuite/sim/arm/thumb/tst.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for tst $rd,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global alu_tst -alu_tst: - tst r0,r0 - - pass diff --git a/sim/testsuite/sim/arm/tst.cgs b/sim/testsuite/sim/arm/tst.cgs deleted file mode 100644 index f071707..0000000 --- a/sim/testsuite/sim/arm/tst.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# arm testcase for tst${cond}${set-cc?} $rn,$imm12 -# mach: unfinished - - .include "testutils.inc" - - start - - .global tst_imm -tst_imm: - tst00 pc,0 - - pass -# arm testcase for tst$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} -# mach: unfinished - - .include "testutils.inc" - - start - - .global tst_reg_imm_shift -tst_reg_imm_shift: - tst00 pc,pc,pc,lsl 0 - - pass -# arm testcase for tst$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} -# mach: unfinished - - .include "testutils.inc" - - start - - .global tst_reg_reg_shift -tst_reg_reg_shift: - tst00 pc,pc,pc,lsl pc - - pass diff --git a/sim/testsuite/sim/arm/umlal.cgs b/sim/testsuite/sim/arm/umlal.cgs deleted file mode 100644 index 1c17fb6..0000000 --- a/sim/testsuite/sim/arm/umlal.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for umlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global umlal -umlal: - umlal00 pc,pc,pc,pc - - pass diff --git a/sim/testsuite/sim/arm/umull.cgs b/sim/testsuite/sim/arm/umull.cgs deleted file mode 100644 index a58541c..0000000 --- a/sim/testsuite/sim/arm/umull.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# arm testcase for umull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs -# mach: unfinished - - .include "testutils.inc" - - start - - .global umull -umull: - umull00 pc,pc,pc,pc - - pass diff --git a/sim/testsuite/sim/arm/xscale/blx.cgs b/sim/testsuite/sim/arm/xscale/blx.cgs deleted file mode 100644 index 854647b..0000000 --- a/sim/testsuite/sim/arm/xscale/blx.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# arm testcase for bl$cond $offset24 -# mach: all - - .include "testutils.inc" - - start - - .arm - blx thumb - - .thumb - .thumb_func -thumb: - nop - blx next - blx PASS - nop - nop - - .section text1, "ax" - .arm -next: - add r0, r1, r0 - bx lr - -FAIL: - fail -PASS: - pass - - diff --git a/sim/testsuite/sim/arm/xscale/mia.cgs b/sim/testsuite/sim/arm/xscale/mia.cgs deleted file mode 100644 index a3f729e..0000000 --- a/sim/testsuite/sim/arm/xscale/mia.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# XSCALE testcase for MIA -# mach: xscale -# as: -mcpu=xscale - - .include "testutils.inc" - - start - - .global mia -mia: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - mia acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0x354f53c4 - test_h_gr r1, 0x4e330b5e - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/xscale/miaph.cgs b/sim/testsuite/sim/arm/xscale/miaph.cgs deleted file mode 100644 index 53fb201..0000000 --- a/sim/testsuite/sim/arm/xscale/miaph.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# XSCALE testcase for MIAPH -# mach: xscale -# as: -mcpu=xscale - - .include "testutils.inc" - - start - - .global miaph -miaph: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - miaph acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0xfec3f9f4 - test_h_gr r1, 0x55667787 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/xscale/miaxy.cgs b/sim/testsuite/sim/arm/xscale/miaxy.cgs deleted file mode 100644 index 624564e..0000000 --- a/sim/testsuite/sim/arm/xscale/miaxy.cgs +++ /dev/null @@ -1,89 +0,0 @@ -# XSCALE testcase for MIAxy -# mach: xscale -# as: -mcpu=xscale - - .include "testutils.inc" - - start - - .global miaXY -miaXY: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Bottom Bottom Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - miaBB acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0x05f753c4 - test_h_gr r1, 0x55667788 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - # Test Bottom Top Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - miaBT acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0xeeede364 - test_h_gr r1, 0x55667787 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - # Test Top Bottom Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - miaTB acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0x0ec85c04 - test_h_gr r1, 0x55667788 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - # Test Top Top Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - miaTT acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0x09eed974 - test_h_gr r1, 0x55667788 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass diff --git a/sim/testsuite/sim/arm/xscale/mra.cgs b/sim/testsuite/sim/arm/xscale/mra.cgs deleted file mode 100644 index be4d9df..0000000 --- a/sim/testsuite/sim/arm/xscale/mra.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# XScale testcase for MAR and MRA -# mach: xscale -# as: -mcpu=xscale - - .include "testutils.inc" - - start - - .global mar_mra -mar_mra: - mvi_h_gr r2,0 - mvi_h_gr r3,0 - mvi_h_gr r4,0x0000EFA0 - mvi_h_gr r5,0xA0A0A0A0 - - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - mar acc0, r5, r4 - mra r2, r3, acc0 - - test_h_gr r2,0xA0A0A0A0 - test_h_gr r3,0x0000EFA0 - test_h_gr r4,0x0000EFA0 - test_h_gr r5,0xA0A0A0A0 - - pass diff --git a/sim/testsuite/sim/arm/xscale/testutils.inc b/sim/testsuite/sim/arm/xscale/testutils.inc deleted file mode 100644 index ae49db8..0000000 --- a/sim/testsuite/sim/arm/xscale/testutils.inc +++ /dev/null @@ -1,118 +0,0 @@ -# r0-r3 are used as tmps, consider them call clobbered by these macros. -# This uses the angel rom monitor calls. -# ??? How do we use the \@ facility of .macros ??? -# @ is the comment char! - - .macro mvi_h_gr reg, val - ldr \reg,[pc] - b . + 8 - .word \val - .endm - - .macro mvaddr_h_gr reg, addr - ldr \reg,[pc] - b . + 8 - .word \addr - .endm - - .macro start - .data -failmsg: - .asciz "fail\n" -passmsg: - .asciz "pass\n" - .text - -do_pass: - ldr r1, passmsg_addr - mov r0, #4 - swi #0x123456 - exit 0 -passmsg_addr: - .word passmsg - -do_fail: - ldr r1, failmsg_addr - mov r0, #4 - swi #0x123456 - exit 1 -failmsg_addr: - .word failmsg - - .global _start -_start: - .endm - -# *** Other macros know pass/fail are 4 bytes in size! Yuck. - - .macro pass - b do_pass - .endm - - .macro fail - b do_fail - .endm - - .macro exit rc - # ??? This works with the ARMulator but maybe not others. - #mov r0, #\rc - #swi #1 - # This seems to be portable (though it ignores rc). - mov r0,#0x18 - mvi_h_gr r1, 0x20026 - swi #0x123456 - # If that returns, punt with a sigill. - stc 0,cr0,[r0] - .endm - -# Other macros know this only clobbers r0. -# WARNING: It also clobbers the condition codes (FIXME). - .macro test_h_gr reg, val - mvaddr_h_gr r0, \val - cmp \reg, r0 - beq . + 8 - fail - .endm - - .macro mvi_h_cnvz c, n, v, z - mov r0, #0 - .if \c - orr r0, r0, #0x20000000 - .endif - .if \n - orr r0, r0, #0x80000000 - .endif - .if \v - orr r0, r0, #0x10000000 - .endif - .if \z - orr r0, r0, #0x40000000 - .endif - mrs r1, cpsr - bic r1, r1, #0xf0000000 - orr r1, r1, r0 - msr cpsr, r1 - # ??? nops needed - .endm - -# ??? Preserve condition codes? - .macro test_h_cnvz c, n, v, z - mov r0, #0 - .if \c - orr r0, r0, #0x20000000 - .endif - .if \n - orr r0, r0, #0x80000000 - .endif - .if \v - orr r0, r0, #0x10000000 - .endif - .if \z - orr r0, r0, #0x40000000 - .endif - mrs r1, cpsr - and r1, r1, #0xf0000000 - cmp r0, r1 - beq . + 8 - fail - .endm diff --git a/sim/testsuite/sim/arm/xscale/xscale.exp b/sim/testsuite/sim/arm/xscale/xscale.exp deleted file mode 100644 index 7c08f11..0000000 --- a/sim/testsuite/sim/arm/xscale/xscale.exp +++ /dev/null @@ -1,28 +0,0 @@ -# XSCALE simulator testsuite. - -if { [istarget arm*-*-*] } { - # load support procs (none yet) - # load_lib cgen.exp - - # all machines - set all_machs "xscale" - - if [is_remote host] { - remote_download host $srcdir/$subdir/testutils.inc - } - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } - - if [is_remote host] { - remote_file host delete testutils.inc - } -} diff --git a/sim/testsuite/sim/avr/ChangeLog b/sim/testsuite/sim/avr/ChangeLog deleted file mode 100644 index 8c1bde2..0000000 --- a/sim/testsuite/sim/avr/ChangeLog +++ /dev/null @@ -1,7 +0,0 @@ -2015-03-29 Mike Frysinger - - * testutils.inc (start): Change to _start and add global markings. - -2015-03-28 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/sim/avr/allinsn.exp b/sim/testsuite/sim/avr/allinsn.exp deleted file mode 100644 index 584a93d..0000000 --- a/sim/testsuite/sim/avr/allinsn.exp +++ /dev/null @@ -1,15 +0,0 @@ -# avr simulator testsuite - -if [istarget avr-*] { - # all machines - set all_machs "avr" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/avr/pass.s b/sim/testsuite/sim/avr/pass.s deleted file mode 100644 index fbcc485..0000000 --- a/sim/testsuite/sim/avr/pass.s +++ /dev/null @@ -1,7 +0,0 @@ -# check that the sim doesn't die immediately. -# mach: avr - -.include "testutils.inc" - - start - pass diff --git a/sim/testsuite/sim/avr/testutils.inc b/sim/testsuite/sim/avr/testutils.inc deleted file mode 100644 index baad45d..0000000 --- a/sim/testsuite/sim/avr/testutils.inc +++ /dev/null @@ -1,42 +0,0 @@ -# MACRO: outc -# Write byte to stdout - .macro outc ch - ldi r16, \ch - out 0x32, r16 - .endm - -# MACRO: exit - .macro exit nr - ldi r16, \nr - out 0x2f, r16 - .endm - -# MACRO: pass -# Write 'pass' to stdout and quit - .macro pass - outc 'p' - outc 'a' - outc 's' - outc 's' - outc '\n' - exit 0 - .endm - -# MACRO: fail -# Write 'fail' to stdout and quit - .macro fail - outc 'f' - outc 'a' - outc 'i' - outc 'l' - outc '\n' - exit 1 - .endm - -# MACRO: start -# All assembler tests should start with a call to "start" - .macro start - .text -.global _start -_start: - .endm diff --git a/sim/testsuite/sim/bfin/.gitignore b/sim/testsuite/sim/bfin/.gitignore deleted file mode 100644 index 5164f03..0000000 --- a/sim/testsuite/sim/bfin/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.[jxX] diff --git a/sim/testsuite/sim/bfin/10272_small.s b/sim/testsuite/sim/bfin/10272_small.s deleted file mode 100644 index b260f9c..0000000 --- a/sim/testsuite/sim/bfin/10272_small.s +++ /dev/null @@ -1,51 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - loadsym P5, tmp0; - - r6=0xFF (Z); - W[p5+0x6] = r6; - - r0.l=0x0808; - r0.h=0xffff; - - R1 = W[P5 + 0x6 ] (X); - R0 = DEPOSIT(R1, R0); - W[P5+0x6] = R0; - - R5=W[P5+0x6] (X); - DBGA(r5.l,0xffff); - - /* This instruction order fails to successfully write R0 back */ - r0.l=0x0808; - r0.h=0xffff; - - loadsym P5, tmp0; - - r6=0xFF (Z); - W[p5+0x6] = r6; - R1 = W[P5 + 0x6 ] (X); - R0 = DEPOSIT(R1, R0); - W[P5+0x6] = R0; - - R5=W[P5+0x6] (X); - DBGA(r5.l,0xffff); - - r4=1; - loadsym P5, tmp0; - r6=0xFF (Z); - W[p5+0x6] = r6; - R1 = W[P5 + 0x6 ] (X); - R0 = R1+R4; - W[P5+0x6] = R0; - - R5=W[P5+0x6] (X); - DBGA(r5.l,0x100); - - pass; - - .data -tmp0: - .space (0x10); diff --git a/sim/testsuite/sim/bfin/10436.s b/sim/testsuite/sim/bfin/10436.s deleted file mode 100644 index 9975436..0000000 --- a/sim/testsuite/sim/bfin/10436.s +++ /dev/null @@ -1,39 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - loadsym i0, tmp0; - - r1 = i0; - b0=i0; - r3=4; - l0=0; - m0=0; - - r5.l=0xdead; - r5.h=0xbeef; - - l0=r3; - [i0++] = r5; - l0 = 0; - r0 = i0; - - CC = R0 == R1; - if !CC JUMP _fail; - - l0=r3; - r3=[i0--]; - r0=i0; - - CC = R0 == R1; - if !CC JUMP _fail; - - pass - -_fail: - fail - - .data -tmp0: - .space (0x100); diff --git a/sim/testsuite/sim/bfin/10622.s b/sim/testsuite/sim/bfin/10622.s deleted file mode 100644 index 67076af..0000000 --- a/sim/testsuite/sim/bfin/10622.s +++ /dev/null @@ -1,21 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - r2.l = 0x1234; - r2.h = 0xff90; - - r4=8; - i2=r2; - m2 = 4; - a0 = 0; - r1.l = (a0 += r4.l *r4.l) (IS) || I2 += m2 || nop; - - r0 = i2; - - dbga(r0.l, 0x1238); - dbga(r0.h, 0xff90); - -_halt0: - pass; diff --git a/sim/testsuite/sim/bfin/10742.s b/sim/testsuite/sim/bfin/10742.s deleted file mode 100644 index 67cb6c9..0000000 --- a/sim/testsuite/sim/bfin/10742.s +++ /dev/null @@ -1,17 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - r5.h=0x1234; - r5.l=0x5678; - - p5 = r5; - p5.l = 0x1000; - - r0 = p5; - dbga(r0.h, 0x1234); - dbga(r0.l, 0x1000); - - pass diff --git a/sim/testsuite/sim/bfin/10799.s b/sim/testsuite/sim/bfin/10799.s deleted file mode 100644 index 76e1eb3..0000000 --- a/sim/testsuite/sim/bfin/10799.s +++ /dev/null @@ -1,55 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - fp = sp; - - [--SP]=RETS; - - loadsym R1, _b; - loadsym R2, _a; - R0 = R2; - - SP += -12; - R2 = 4; - - CALL _dot; - R1 = R0; - - R0 = 30; - dbga( r1.l, 0x1e); - - - pass - -_dot: - P0 = R1; - CC = R2 <= 0; - R3 = R0; - R0 = 0; - IF CC JUMP ._P1L1 (bp); - R0 = 1; - I0 = R3; - R0 = MAX (R0,R2) || R2 = [P0++] || NOP; - P1 = R0; - R0 = 0; - R1 = [I0++]; - LSETUP (._P1L4 , ._P1L5) LC0=P1; - -._P1L4: - R1 *= R2; -._P1L5: - R0= R0 + R1 (NS) || R2 = [P0++] || R1 = [I0++]; - -._P1L1: - RTS; - -.data; -_a: - .db 0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00; - .db 0x04,0x00,0x00,0x00; - -_b: - .db 0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00; - .db 0x04,0x00,0x00,0x00; diff --git a/sim/testsuite/sim/bfin/11080.s b/sim/testsuite/sim/bfin/11080.s deleted file mode 100644 index c5652cc..0000000 --- a/sim/testsuite/sim/bfin/11080.s +++ /dev/null @@ -1,40 +0,0 @@ -# Blackfin testcase for DISALGNEXCPT -# mach: bfin - -.include "testutils.inc" - start - - loadsym R0, foo; - R0 += 1; - I1 = R0; - - M0 = 4 (z); - - //dag0misalgn, dag1misalgn EXCAUSE value - R7 = 0x24 (z); - - // Get just the EXCAUSE field before - R5=SEQSTAT; - R5 = R5 << 26; - R5 = R5 >> 26; - - DISALGNEXCPT || R2 = [I1++M0]; // i1 = 0xff9004aa (misaligned) - - // Get just the EXCAUSE field after - R6=SEQSTAT; - R6 = R6 << 26; - R6 = R6 >> 26; - - // EXCAUSE of 0x24 == misaligned data memory access - CC = R6 == R7; - if CC jump _fail; - -_pass: - pass; - -_fail: - fail; - - .data -foo: - .space 0x10 diff --git a/sim/testsuite/sim/bfin/7641.s b/sim/testsuite/sim/bfin/7641.s deleted file mode 100644 index 864480c..0000000 --- a/sim/testsuite/sim/bfin/7641.s +++ /dev/null @@ -1,38 +0,0 @@ -# Blackfin testcase for playing with TESTSET -# mach: bfin - - .include "testutils.inc" - - start - - loadsym P0, element1 - - loadsym P1, element2 - - R0 = B [P0]; // R0 should get 00 - R1 = B [P1]; // R1 should get 02 - - TESTSET(P0); // should set CC and MSB of memory byte - R0 = CC; - TESTSET(P1); // should clear CC and not change MSB of memory - R1 = CC; - - R2 = B [P0]; // R2 should get 80 - R3 = B [P1]; // R3 should get 02 - - dbga(R0.l,0x0001); - dbga(R0.h,0x0000); - dbga(R1.l,0x0000); - dbga(R1.h,0x0000); - dbga(R2.l,0x0080); - dbga(R2.h,0x0000); - dbga(R3.l,0x0082); - dbga(R3.h,0x0000); - - pass - -.data -.align 4; -element1: .long 0x0 -element2: .long 0x2 -element3: .long 0x4 diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog deleted file mode 100644 index b8fdc04..0000000 --- a/sim/testsuite/sim/bfin/ChangeLog +++ /dev/null @@ -1,370 +0,0 @@ -2021-01-04 Mike Frysinger - - * mdma-skel.h: Include stdlib.h. - -2015-10-11 Mike Frysinger - - PR sim/18407 - * ashift_left.s: New test. - -2013-12-07 Mike Frysinger - - * run-tests.sh: Add +x file mode. - -2013-06-23 Mike Frysinger - - * run-tests.sh (usage): Fix typo in exit. - -2013-06-23 Mike Frysinger - - * se_all32bitopcodes.S (se_all_next_insn): Skip debug insn opcodes. - -2013-06-23 Mike Frysinger - - * se_allopcodes.h (_match): Simplify register test to one less insn. - Omit the SSYNC insn when compiling for the sim. - -2013-06-23 Mike Frysinger - - * testutils.inc: Trim trailing whitespace. - -2013-06-17 Mike Frysinger - - * run-tests.sh: Add support for running in parallel. - -2013-06-17 Mike Frysinger - - * se_allopcodes.h: Add debugging related comments. - -2013-06-17 Mike Frysinger - - * se_allopcodes.h: Do not clear RETN/RETE/RETI. - -2012-04-09 Robin Getz - - * random_0017.S, random_0018.S, random_0025.S: New ASTAT shift tests. - -2012-04-09 Robin Getz - - * random_0036.S, random_0037.S: New astat tests. - -2012-04-09 Mike Frysinger - - * se_all64bitg1opcodes.S: Delete xfail line. - * se_all64bitg2opcodes.S: Likewise. - -2012-04-08 Mike Frysinger - - * se_all16bitopcodes.S (SE_ALL_BITS): Define to 16. - (SE_ALL_NEW_INSN_STUB): Define. - (se_all_load_table): Delete. - (se_all_new_insn_log): Likewise. - * se_all32bitopcodes.S: Add more details on slowness. - (SE_ALL_BITS): Define to 13. - (se_all_load_table): Delete. - (se_all_new_insn_stub, se_all_new_insn_log): Likewise. - * se_all64bitg0opcodes.S: Add more details on slowness. - (se_all_new_insn_stub): Delete. - * se_all64bitg1opcodes.S: See mach to bfin. - (se_all_new_insn_stub): Delete. - * se_all64bitg2opcodes.S: See mach to bfin. - (se_all_new_insn_stub): Delete. - * se_allopcodes.h (LOAD_PFX): Define based on SE_ALL_BITS. - (se_all_new_16bit_insn_log, se_all_new_32bit_insn_log): Unify - into new se_all_new_insn_log helper. - (se_all_load_table): New helper. - (se_all_new_insn_stub): Likewise. - -2012-03-25 Mike Frysinger - - * c_dsp32mac_dr_a1a0.s: Change 0x12efbc5569 to 0xefbc5569. - * c_dsp32mac_dr_a1a0_iutsh.s: Change 0x12efbc556 to 0x2efbc556. - * c_dsp32mac_dr_a1a0_m.s: Change 0x12efbc5569 to 0xefbc5569. - * c_dsp32shift_vmaxvmax.s: Change 0xa11002001 to 0x11002001. - * c_dsp32shiftim_af_s.s: Change 0x3a1230001 to 0xa1230001. - - * fact.s: Comment out test with too large a number (6227020800). - - * allinsn.exp: If preprocessing usp.S fails, set has_cpp to 0, - else set it to 1. If compiling argc.c fails, set has_cc to 0, - else set it to 1. When processing each src file, if has_ccp is - 0 and the file ends in .S, skip it; if it has_cc is 0 and the - file ends in .c, skip it. - -2012-03-19 Mike Frysinger - - * se_all64bitg0opcodes.S, se_all64bitg1opcodes.S, - se_all64bitg2opcodes.S: New exhaustive parallel insn tests. - -2012-03-19 Mike Frysinger - - * se_allopcodes.h: New framework for testing opcode regions. - * se_all16bitopcodes.S: Convert over to se_allopcodes.h. - * se_all32bitopcodes.S: Likewise. - -2012-03-19 Stuart Henderson - - * c_dsp32shiftim_amix.s: Check edge cases in shift behavior. - -2012-03-19 Robin Getz - - * random_0014.S, random_0015.S, random_0016.S: New tests for shifts. - -2012-03-18 Mike Frysinger - - * se_all16bitopcodes.S: Merge code from se_all32bitopcodes.S. - -2011-09-28 Mike Frysinger - - * vit_max2.s: New tests for parallel VIT_MAX insns. - -2011-06-18 Robin Getz - - * random_0019.S, random_0020.S, random_0021.S, random_0022.S, - random_0023.S, random_0024.S, random_0026.S, random_0027.S, - random_0028.S, random_0029.S, random_0030.S, random_0032.S, - random_0035.S: New tests for dsp insns. - -2011-06-04 Mike Frysinger - - * .gitignore, 10272_small.s, 10436.s, 10622.s, 10742.s, 10799.s, - 11080.s, 7641.s, a0.s, a0shift.S, a10.s, a11.S, a12.s, a1.s, a20.S, - a21.s, a22.s, a23.s, a24.s, a25.s, a26.s, a2.s, a30.s, a3.s, a4.s, - a5.s, a6.s, a7.s, a8.s, a9.s, abs-2.S, abs-3.S, abs-4.S, abs_acc.s, - abs.S, acc-rot.s, acp5_19.s, acp5_4.s, add_imm7.s, add_shift.S, - add_sub_acc.s, addsub_flags.S, algnbug1.s, algnbug2.s, allinsn.exp, - argc.c, ashift_flags.s, ashift.s, b0.S, b1.s, b2.S, brcc.s, brevadd.s, - byteop16m.s, byteop16p.s, byteop1p.s, byteop2p.s, byteop3p.s, - byteunpack.s, c_alu2op_arith_r_sft.s, c_alu2op_conv_b.s, - c_alu2op_conv_h.s, c_alu2op_conv_mix.s, c_alu2op_conv_neg.s, - c_alu2op_conv_toggle.s, c_alu2op_conv_xb.s, c_alu2op_conv_xh.s, - c_alu2op_divq.s, c_alu2op_divs.s, c_alu2op_log_l_sft.s, - c_alu2op_log_r_sft.s, c_alu2op_shadd_1.s, c_alu2op_shadd_2.s, - c_brcc_bp1.s, c_brcc_bp2.s, c_brcc_bp3.s, c_brcc_bp4.s, - c_brcc_brf_bp.s, c_brcc_brf_brt_bp.s, c_brcc_brf_brt_nbp.s, - c_brcc_brf_fbkwd.s, c_brcc_brf_nbp.s, c_brcc_brt_bp.s, - c_brcc_brt_nbp.s, c_brcc_kills_dhits.s, c_brcc_kills_dmiss.s, - c_br_preg_killed_ac.s, c_br_preg_killed_ex1.s, c_br_preg_stall_ac.s, - c_br_preg_stall_ex1.s, cc0.s, cc1.s, cc5.S, c_cactrl_iflush_pr_pp.s, - c_cactrl_iflush_pr.s, c_calla_ljump.s, c_calla_subr.s, cc-alu.S, - cc-astat-bits.s, c_cc2dreg.s, c_cc2stat_cc_ac.S, c_cc2stat_cc_an.s, - c_cc2stat_cc_aq.s, c_cc2stat_cc_av0.S, c_cc2stat_cc_av1.S, - c_cc2stat_cc_az.s, c_ccflag_a0a1.S, c_cc_flag_ccmv_depend.S, - c_ccflag_dr_dr.s, c_ccflag_dr_dr_uu.s, c_cc_flagdreg_mvbrsft.s, - c_cc_flagdreg_mvbrsft_s1.s, c_cc_flagdreg_mvbrsft_sn.s, - c_ccflag_dr_imm3.s, c_ccflag_dr_imm3_uu.s, c_ccflag_pr_imm3.s, - c_ccflag_pr_imm3_uu.s, c_ccflag_pr_pr.s, c_ccflag_pr_pr_uu.s, - c_ccmv_cc_dr_dr.s, c_ccmv_cc_dr_pr.s, c_ccmv_cc_pr_pr.s, - c_ccmv_ncc_dr_dr.s, c_ccmv_ncc_dr_pr.s, c_ccmv_ncc_pr_pr.s, - c_cc_regmvlogi_mvbrsft.s, c_cc_regmvlogi_mvbrsft_s1.s, - c_cc_regmvlogi_mvbrsft_sn.S, c_comp3op_dr_and_dr.s, - c_comp3op_dr_minus_dr.s, c_comp3op_dr_mix.s, c_comp3op_dr_or_dr.s, - c_comp3op_dr_plus_dr.s, c_comp3op_dr_xor_dr.s, - c_comp3op_pr_plus_pr_sh1.s, c_comp3op_pr_plus_pr_sh2.s, - c_compi2opd_dr_add_i7_n.s, c_compi2opd_dr_add_i7_p.s, - c_compi2opd_dr_eq_i7_n.s, c_compi2opd_dr_eq_i7_p.s, - c_compi2opd_flags_2.S, c_compi2opd_flags.S, c_compi2opp_pr_add_i7_n.s, - c_compi2opp_pr_add_i7_p.s, c_compi2opp_pr_eq_i7_n.s, - c_compi2opp_pr_eq_i7_p.s, c_dagmodik_lnz_imgebl.s, - c_dagmodik_lnz_imltbl.s, c_dagmodik_lz_inc_dec.s, - c_dagmodim_lnz_imgebl.s, c_dagmodim_lnz_imltbl.s, - c_dagmodim_lz_inc_dec.s, c_dsp32alu_a0a1s.s, c_dsp32alu_a0_pm_a1.s, - c_dsp32alu_aa_absabs.s, c_dsp32alu_a_abs_a.s, c_dsp32alu_aa_negneg.s, - c_dsp32alu_absabs.s, c_dsp32alu_abs.s, c_dsp32alu_alhwx.s, - c_dsp32alu_a_neg_a.s, c_dsp32alu_awx.s, c_dsp32alu_byteop1ew.s, - c_dsp32alu_byteop2.s, c_dsp32alu_byteop3.s, c_dsp32alu_bytepack.s, - c_dsp32alu_byteunpack.s, c_dsp32alu_disalnexcpt.s, c_dsp32alu_maxmax.s, - c_dsp32alu_max.s, c_dsp32alu_minmin.s, c_dsp32alu_min.s, - c_dsp32alu_mix.s, c_dsp32alu_rh_m.s, c_dsp32alu_rh_p.s, - c_dsp32alu_rh_rnd12_m.s, c_dsp32alu_rh_rnd12_p.s, - c_dsp32alu_rh_rnd20_m.s, c_dsp32alu_rh_rnd20_p.s, - c_dsp32alu_r_lh_a0pa1.s, c_dsp32alu_rlh_rnd.s, c_dsp32alu_rl_m.s, - c_dsp32alu_rl_p.s, c_dsp32alu_rl_rnd12_m.s, c_dsp32alu_rl_rnd12_p.s, - c_dsp32alu_rl_rnd20_m.s, c_dsp32alu_rl_rnd20_p.s, c_dsp32alu_rmm.s, - c_dsp32alu_rmp.s, c_dsp32alu_rm.s, c_dsp32alu_r_negneg.s, - c_dsp32alu_rpm.s, c_dsp32alu_rpp.s, c_dsp32alu_rp.s, - c_dsp32alu_rr_lph_a1a0.s, c_dsp32alu_rrpm_aa.s, c_dsp32alu_rrpmmp.s, - c_dsp32alu_rrpmmp_sft.s, c_dsp32alu_rrpmmp_sft_x.s, c_dsp32alu_rrpm.s, - c_dsp32alu_rrppmm.s, c_dsp32alu_rrppmm_sft.s, - c_dsp32alu_rrppmm_sft_x.s, c_dsp32alu_saa.s, c_dsp32alu_sat_aa.S, - c_dsp32alu_search.s, c_dsp32alu_sgn.s, c_dsp32mac_a1a0_iuw32.s, - c_dsp32mac_a1a0_m.s, c_dsp32mac_a1a0.s, c_dsp32mac_dr_a0_ih.s, - c_dsp32mac_dr_a0_i.s, c_dsp32mac_dr_a0_is.s, c_dsp32mac_dr_a0_iu.s, - c_dsp32mac_dr_a0_m.s, c_dsp32mac_dr_a0.s, c_dsp32mac_dr_a0_s.s, - c_dsp32mac_dr_a0_t.s, c_dsp32mac_dr_a0_tu.s, c_dsp32mac_dr_a0_u.s, - c_dsp32mac_dr_a1a0_iutsh.s, c_dsp32mac_dr_a1a0_m.s, - c_dsp32mac_dr_a1a0.s, c_dsp32mac_dr_a1_ih.s, c_dsp32mac_dr_a1_i.s, - c_dsp32mac_dr_a1_is.s, c_dsp32mac_dr_a1_iu.s, c_dsp32mac_dr_a1_m.s, - c_dsp32mac_dr_a1.s, c_dsp32mac_dr_a1_s.s, c_dsp32mac_dr_a1_t.s, - c_dsp32mac_dr_a1_tu.s, c_dsp32mac_dr_a1_u.s, c_dsp32mac_mix.s, - c_dsp32mac_pair_a0_i.s, c_dsp32mac_pair_a0_is.s, - c_dsp32mac_pair_a0_m.s, c_dsp32mac_pair_a0.s, c_dsp32mac_pair_a0_s.s, - c_dsp32mac_pair_a0_u.s, c_dsp32mac_pair_a1a0_i.s, - c_dsp32mac_pair_a1a0_is.s, c_dsp32mac_pair_a1a0_m.s, - c_dsp32mac_pair_a1a0.s, c_dsp32mac_pair_a1a0_s.s, - c_dsp32mac_pair_a1a0_u.s, c_dsp32mac_pair_a1_i.s, - c_dsp32mac_pair_a1_is.s, c_dsp32mac_pair_a1_m.s, c_dsp32mac_pair_a1.s, - c_dsp32mac_pair_a1_s.s, c_dsp32mac_pair_a1_u.s, c_dsp32mac_pair_mix.s, - c_dsp32mult_dr_ih.s, c_dsp32mult_dr_i.s, c_dsp32mult_dr_is.s, - c_dsp32mult_dr_iu.s, c_dsp32mult_dr_m_i.s, c_dsp32mult_dr_m_iutsh.s, - c_dsp32mult_dr_mix.s, c_dsp32mult_dr_m.s, c_dsp32mult_dr_m_s.s, - c_dsp32mult_dr_m_t.s, c_dsp32mult_dr_m_u.s, c_dsp32mult_dr.s, - c_dsp32mult_dr_s.s, c_dsp32mult_dr_t.s, c_dsp32mult_dr_tu.s, - c_dsp32mult_dr_u.s, c_dsp32mult_pair_i.s, c_dsp32mult_pair_is.s, - c_dsp32mult_pair_m_i.s, c_dsp32mult_pair_m_is.s, c_dsp32mult_pair_m.s, - c_dsp32mult_pair_m_s.s, c_dsp32mult_pair_m_u.s, c_dsp32mult_pair.s, - c_dsp32mult_pair_s.s, c_dsp32mult_pair_u.s, c_dsp32shift_a0alr.s, - c_dsp32shift_af.s, c_dsp32shift_af_s.s, c_dsp32shift_ahalf_ln.s, - c_dsp32shift_ahalf_ln_s.s, c_dsp32shift_ahalf_lp.s, - c_dsp32shift_ahalf_lp_s.s, c_dsp32shift_ahalf_rn.s, - c_dsp32shift_ahalf_rn_s.s, c_dsp32shift_ahalf_rp.s, - c_dsp32shift_ahalf_rp_s.s, c_dsp32shift_ahh.s, c_dsp32shift_ahh_s.s, - c_dsp32shift_align16.s, c_dsp32shift_align24.s, c_dsp32shift_align8.s, - c_dsp32shift_amix.s, c_dsp32shift_bitmux.s, c_dsp32shift_bxor.s, - c_dsp32shift_expadj_h.s, c_dsp32shift_expadj_l.s, - c_dsp32shift_expadj_r.s, c_dsp32shift_expexp_r.s, c_dsp32shift_fdepx.s, - c_dsp32shift_fextx.s, c_dsp32shiftim_a0alr.s, c_dsp32shiftim_af.s, - c_dsp32shiftim_af_s.s, c_dsp32shiftim_ahalf_ln.s, - c_dsp32shiftim_ahalf_ln_s.s, c_dsp32shiftim_ahalf_lp.s, - c_dsp32shiftim_ahalf_lp_s.s, c_dsp32shiftim_ahalf_rn.s, - c_dsp32shiftim_ahalf_rn_s.s, c_dsp32shiftim_ahalf_rp.s, - c_dsp32shiftim_ahalf_rp_s.s, c_dsp32shiftim_ahh.s, - c_dsp32shiftim_ahh_s.s, c_dsp32shiftim_amix.s, c_dsp32shiftim_lf.s, - c_dsp32shiftim_lhalf_ln.s, c_dsp32shiftim_lhalf_lp.s, - c_dsp32shiftim_lhalf_rn.s, c_dsp32shiftim_lhalf_rp.s, - c_dsp32shiftim_lhh.s, c_dsp32shiftim_lmix.s, c_dsp32shiftim_rot.s, - c_dsp32shift_lf.s, c_dsp32shift_lhalf_ln.s, c_dsp32shift_lhalf_lp.s, - c_dsp32shift_lhalf_rn.s, c_dsp32shift_lhalf_rp.s, c_dsp32shift_lhh.s, - c_dsp32shift_lmix.s, c_dsp32shift_ones.s, c_dsp32shift_pack.s, - c_dsp32shift_rot_mix.s, c_dsp32shift_rot.s, c_dsp32shift_signbits_rh.s, - c_dsp32shift_signbits_rl.s, c_dsp32shift_signbits_r.s, - c_dsp32shift_vmax.s, c_dsp32shift_vmaxvmax.s, c_dspldst_ld_drhi_ipp.s, - c_dspldst_ld_drhi_i.s, c_dspldst_ld_dr_ippm.s, c_dspldst_ld_dr_ipp.s, - c_dspldst_ld_dr_i.s, c_dspldst_ld_drlo_ipp.s, c_dspldst_ld_drlo_i.s, - c_dspldst_st_drhi_ipp.s, c_dspldst_st_drhi_i.s, c_dspldst_st_dr_ippm.s, - c_dspldst_st_dr_ipp.s, c_dspldst_st_dr_i.s, c_dspldst_st_drlo_ipp.s, - c_dspldst_st_drlo_i.s, cec-exact-exception.S, cec-ifetch.S, - cec-multi-pending.S, cec-non-operating-env.s, cec-no-snen-reti.S, - cec-raise-reti.S, cec-snen-reti.S, cec-syscfg-ssstep.S, - cec-system-call.S, c_except_illopcode.S, c_except_sys_sstep.S, - c_except_user_mode.S, c_interr_disable_enable.S, c_interr_disable.S, - c_interr_excpt.S, c_interr_loopsetup_stld.S, c_interr_nested.S, - c_interr_nmi.S, c_interr_pending_2.S, c_interr_pending.S, - c_interr_timer_reload.S, c_interr_timer.S, c_interr_timer_tcount.S, - c_interr_timer_tscale.S, cir1.s, cir.s, c_ldimmhalf_dreg.s, - c_ldimmhalf_drhi.s, c_ldimmhalf_drlo.s, c_ldimmhalf_h_dr.s, - c_ldimmhalf_h_ibml.s, c_ldimmhalf_h_pr.s, c_ldimmhalf_l_dr.s, - c_ldimmhalf_l_ibml.s, c_ldimmhalf_l_pr.s, c_ldimmhalf_lz_dr.s, - c_ldimmhalf_lzhi_dr.s, c_ldimmhalf_lzhi_ibml.s, c_ldimmhalf_lzhi_pr.s, - c_ldimmhalf_lz_ibml.s, c_ldimmhalf_lz_pr.s, c_ldimmhalf_pibml.s, - c_ldstidxl_ld_dr_b.s, c_ldstidxl_ld_dreg.s, c_ldstidxl_ld_dr_h.s, - c_ldstidxl_ld_dr_xb.s, c_ldstidxl_ld_dr_xh.s, c_ldstidxl_ld_preg.s, - c_ldstidxl_st_dr_b.s, c_ldstidxl_st_dreg.s, c_ldstidxl_st_dr_h.s, - c_ldstidxl_st_preg.s, c_ldstiifp_ld_dreg.s, c_ldstiifp_ld_preg.s, - c_ldstiifp_st_dreg.s, c_ldstiifp_st_preg.s, c_ldstii_ld_dreg.s, - c_ldstii_ld_dr_h.s, c_ldstii_ld_dr_xh.s, c_ldstii_ld_preg.s, - c_ldstii_st_dreg.s, c_ldstii_st_dr_h.s, c_ldstii_st_preg.s, - c_ldst_ld_d_p_b.s, c_ldst_ld_d_p_h.s, c_ldst_ld_d_p_mm_b.s, - c_ldst_ld_d_p_mm_h.s, c_ldst_ld_d_p_mm.s, c_ldst_ld_d_p_mm_xb.s, - c_ldst_ld_d_p_mm_xh.s, c_ldst_ld_d_p_pp_b.s, c_ldst_ld_d_p_pp_h.s, - c_ldst_ld_d_p_ppmm_hbx.s, c_ldst_ld_d_p_pp.s, c_ldst_ld_d_p_pp_xb.s, - c_ldst_ld_d_p_pp_xh.s, c_ldst_ld_d_p.s, c_ldst_ld_d_p_xb.s, - c_ldst_ld_d_p_xh.s, c_ldst_ld_p_p_mm.s, c_ldst_ld_p_p_pp.s, - c_ldst_ld_p_p.s, c_ldstpmod_ld_dreg.s, c_ldstpmod_ld_dr_hi.s, - c_ldstpmod_ld_dr_lo.s, c_ldstpmod_ld_h_xh.s, c_ldstpmod_ld_lohi.s, - c_ldstpmod_st_dreg.s, c_ldstpmod_st_dr_hi.s, c_ldstpmod_st_dr_lo.s, - c_ldstpmod_st_lohi.s, c_ldst_st_p_d_b.s, c_ldst_st_p_d_h.s, - c_ldst_st_p_d_mm_b.s, c_ldst_st_p_d_mm_h.s, c_ldst_st_p_d_mm.s, - c_ldst_st_p_d_pp_b.s, c_ldst_st_p_d_pp_h.s, c_ldst_st_p_d_pp.s, - c_ldst_st_p_d.s, c_ldst_st_p_p_mm.s, c_ldst_st_p_p_pp.s, - c_ldst_st_p_p.s, c_linkage.s, cli-sti.s, c_logi2op_alshft_mix.s, - c_logi2op_arith_shft.s, c_logi2op_bitclr.s, c_logi2op_bitset.s, - c_logi2op_bittgl.s, c_logi2op_bittst.s, c_logi2op_log_l_shft_astat.S, - c_logi2op_log_l_shft.s, c_logi2op_log_r_shft_astat.S, - c_logi2op_log_r_shft.s, c_logi2op_nbittst.s, c_loopsetup_nested_bot.s, - c_loopsetup_nested_prelc.s, c_loopsetup_nested.s, - c_loopsetup_nested_top.s, c_loopsetup_overlap.s, - c_loopsetup_preg_div2_lc0.s, c_loopsetup_preg_div2_lc1.s, - c_loopsetup_preg_lc0.s, c_loopsetup_preg_lc1.s, - c_loopsetup_preg_stld.s, c_loopsetup_prelc.s, c_loopsetup_topbotcntr.s, - c_mmr_interr_ctl.s, c_mmr_loop.S, c_mmr_loop_user_except.S, - c_mmr_ppop_illegal_adr.S, c_mmr_ppopm_illegal_adr.S, c_mmr_timer.S, - c_mode_supervisor.S, c_mode_user.S, c_mode_user_superivsor.S, cmpacc.s, - cmpdreg.S, c_multi_issue_dsp_ld_ld.s, c_multi_issue_dsp_ldst_1.s, - c_multi_issue_dsp_ldst_2.s, compare.s, conv_enc_gen.s, - c_progctrl_call_pcpr.s, c_progctrl_call_pr.s, - c_progctrl_clisti_interr.S, c_progctrl_csync_mmr.S, - c_progctrl_except_rtx.S, c_progctrl_excpt.S, c_progctrl_jump_pcpr.s, - c_progctrl_jump_pr.s, c_progctrl_nop.s, c_progctrl_raise_rt_i_n.S, - c_progctrl_rts.s, c_ptr2op_pr_neg_pr.s, c_ptr2op_pr_sft_2_1.s, - c_ptr2op_pr_shadd_1_2.s, c_pushpopmultiple_dp_pair.s, - c_pushpopmultiple_dp.s, c_pushpopmultiple_dreg.s, - c_pushpopmultiple_preg.s, c_regmv_acc_acc.s, c_regmv_dag_lz_dep.s, - c_regmv_dr_acc_acc.s, c_regmv_dr_dep_nostall.s, c_regmv_dr_dr.s, - c_regmv_dr_imlb.s, c_regmv_dr_pr.s, c_regmv_imlb_dep_nostall.s, - c_regmv_imlb_dep_stall.s, c_regmv_imlb_dr.s, c_regmv_imlb_imlb.s, - c_regmv_imlb_pr.s, c_regmv_pr_dep_nostall.s, c_regmv_pr_dep_stall.s, - c_regmv_pr_dr.s, c_regmv_pr_imlb.s, c_regmv_pr_pr.s, - c_seq_ac_raise_mv_ppop.S, c_seq_ac_raise_mv.S, - c_seq_ac_regmv_pushpop.S, c_seq_dec_raise_pushpop.S, - c_seq_ex1_brcc_mv_pop.S, c_seq_ex1_call_mv_pop.S, c_seq_ex1_j_mv_pop.S, - c_seq_ex1_raise_brcc_mv_pop.S, c_seq_ex1_raise_call_mv_pop.S, - c_seq_ex1_raise_j_mv_pop.S, c_seq_ex2_brcc_mp_mv_pop.S, - c_seq_ex2_mmrj_mvpop.S, c_seq_ex2_mmr_mvpop.S, - c_seq_ex2_raise_mmrj_mvpop.S, c_seq_ex2_raise_mmr_mvpop.S, - c_seq_ex3_ls_brcc_mvp.S, c_seq_ex3_ls_mmrj_mvp.S, - c_seq_ex3_ls_mmr_mvp.S, c_seq_ex3_raise_ls_mmrj_mvp.S, - c_seq_wb_cs_lsmmrj_mvp.S, c_seq_wb_raisecs_lsmmrj_mvp.S, - c_seq_wb_rti_lsmmrj_mvp.S, c_seq_wb_rtn_lsmmrj_mvp.S, - c_seq_wb_rtx_lsmmrj_mvp.S, c_ujump.s, cycles.s, d0.s, d1.s, d2.s, - dbg_brprd_ntkn_src_kill.S, dbg_brtkn_nprd_src_kill.S, - dbg_jmp_src_kill.S, dbg_tr_basic.S, dbg_tr_simplejp.S, dbg_tr_tbuf0.S, - dbg_tr_umode.S, disalnexcpt_implicit.S, div0.s, divq.s, dotproduct2.s, - dotproduct.s, double_prec_mult.s, dsp_a4.s, dsp_a7.s, dsp_a8.s, - dsp_d0.s, dsp_d1.s, dsp_neg.S, dsp_s1.s, e0.s, edn_snafu.s, - eu_dsp32mac_s.s, events.s, f221.s, fact.s, fir.s, fsm.s, greg2.s, - hwloop-bits.S, hwloop-branch-in.s, hwloop-branch-out.s, - hwloop-lt-bits.s, hwloop-nested.s, i0.s, iir.s, issue103.s, issue109.s, - issue112.s, issue113.s, issue117.s, issue118.s, issue119.s, issue121.s, - issue123.s, issue124.s, issue125.s, issue126.s, issue127.s, issue129.s, - issue139.S, issue140.S, issue142.s, issue144.s, issue146.S, issue175.s, - issue205.s, issue257.s, issue272.S, issue83.s, issue89.s, l0.s, - l0shift.s, l2_loop.s, link-2.s, link.s, lmu_cplb_multiple0.S, - lmu_cplb_multiple1.S, lmu_excpt_align.S, lmu_excpt_default.S, - lmu_excpt_illaddr.S, lmu_excpt_prot0.S, lmu_excpt_prot1.S, load.s, - logic.s, loop_snafu.s, loop_strncpy.s, lp0.s, lp1.s, lsetup.s, - m0boundary.s, m10.s, m11.s, m12.s, m13.s, m14.s, m15.s, m16.s, m17.s, - m1.S, m2.s, m3.s, m4.s, m5.s, m6.s, m7.s, m8.s, m9.s, mac2halfreg.S, - Makefile, math.s, max_min_flags.s, mc_s2.s, mdma-32bit-1d.c, - mdma-32bit-1d-neg-count.c, mdma-8bit-1d.c, mdma-8bit-1d-neg-count.c, - mdma-skel.h, mem3.s, mmr-exception.s, move.s, msa_acp_5_10.s, - msa_acp_5.10.S, msa_acp_5.12_1.S, msa_acp_5.12_2.S, mult.s, neg-2.S, - neg-3.S, neg.S, nshift.s, PN_generator.s, pr.s, push-pop-multiple.s, - pushpopreg_1.s, push-pop.s, quadaddsub.s, random_0001.s, random_0002.S, - random_0003.S, random_0004.S, random_0005.S, random_0006.S, - random_0007.S, random_0008.S, random_0009.S, random_0010.S, - random_0011.S, random_0012.S, random_0013.S, random_0031.S, - random_0033.S, random_0034.S, run-tests.sh, s0.s, s10.s, s11.s, s12.s, - s13.s, s14.s, s15.s, s16.s, s17.s, s18.s, s19.s, s1.s, s20.s, s21.s, - s2.s, s30.s, s3.s, s4.s, s5.s, s6.s, s7.s, s8.s, s9.s, saatest.s, - se_all16bitopcodes.S, se_all32bitopcodes.lds, se_all32bitopcodes.S, - se_brtarget_stall.S, se_bug_ui2.S, se_bug_ui3.S, se_bug_ui.S, - se_cc2stat_haz.S, se_cc_kill.S, se_cof.S, se_event_quad.S, - se_excpt_dagprotviol.S, se_excpt_ifprotviol.S, se_excpt_ssstep.S, - se_illegalcombination.S, se_kills2.S, se_kill_wbbr.S, - se_loop_disable.S, se_loop_kill_01.S, se_loop_kill_dcr_01.S, - se_loop_kill_dcr.S, se_loop_kill.S, se_loop_lr.S, - se_loop_mv2lb_stall.S, se_loop_mv2lc.S, se_loop_mv2lc_stall.S, - se_loop_mv2lt_stall.S, se_loop_nest_ppm_1.S, se_loop_nest_ppm_2.S, - se_loop_nest_ppm.S, se_loop_ppm_1.S, se_loop_ppm_int.S, se_loop_ppm.S, - se_lsetup_kill.S, se_misaligned_fetch.S, se_more_ret_haz.S, se_mv2lp.S, - se_oneins_zoff.S, se_popkill.S, seqstat.s, se_regmv_usp_sysreg.S, - se_rets_hazard.s, se_rts_rti.S, se_ssstep_dagprotviol.S, se_ssync.S, - se_stall_if2.S, se_undefinedinstruction1.S, se_undefinedinstruction2.S, - se_undefinedinstruction3.S, se_undefinedinstruction4.S, - se_usermode_protviol.S, sign.s, simple0.s, sri.s, stk2.s, stk3.s, - stk4.s, stk5.s, stk6.s, stk.s, syscfg.s, tar10622.s, test-dma.h, - test.h, testset2.s, testset.s, testutils.inc, unlink.S, up0.s, usp.S, - vec-abs-2.S, vec-abs-3.S, vec-abs.S, vecadd.s, vec-neg-2.S, - vec-neg-3.S, vec-neg.S, viterbi2.s, vit_max.s, wtf.s, x1.s, zcall.s, - zeroflagrnd.s: New files. diff --git a/sim/testsuite/sim/bfin/PN_generator.s b/sim/testsuite/sim/bfin/PN_generator.s deleted file mode 100644 index 7d92b85..0000000 --- a/sim/testsuite/sim/bfin/PN_generator.s +++ /dev/null @@ -1,78 +0,0 @@ -# mach: bfin - -// GENERIC PN SEQUENCE GENERATOR -// Linear Feedback Shift Register -// ------------------------------- -// This solution implements an LFSR by applying an XOR reduction -// function to the 40 bit accumulator, XORing the contents of the -// CC bit, shifting by one the accumulator, and inserting the -// resulting bit on the open bit slot. -// CC --> ----- XOR-------------------------- -// | | | | | | -// | | | | | | -// +------------------------------+ v -// | b0 b1 b2 b3 b38 b39 | in <-- by one -// +------------------------------+ -// after: -// +------------------------------+ -// | b1 b2 b3 b38 b39 in | -// +------------------------------+ -// The program shown here is a PN sequence generator, and hence -// does not take any input other than the initial state. However, -// in order to accept an input, one simply needs to rotate the -// input sequence via CC prior to applying the XOR reduction. - -.include "testutils.inc" - start - - loadsym P1, output; - init_r_regs 0; - ASTAT = R0; - -// load Polynomial into A1 - A1 = A0 = 0; - R0.L = 0x1cd4; - R0.H = 0xab18; - A1.w = R0; - R0.L = 0x008d; - A1.x = R0.L; - -// load InitState into A0 - R0.L = 0x0001; - R0.H = 0x0000; - A0.w = R0; - R0.L = 0x0000; - A0.x = R0.L; - - P4 = 4; - LSETUP ( l$0 , l$0end ) LC0 = P4; - l$0: // **** START l-LOOP ***** - - P4 = 32; - LSETUP ( m$1 , m$1 ) LC1 = P4; // **** START m-LOOP ***** - m$1: - A0 = BXORSHIFT( A0 , A1, CC ); - -// store 16 bits of outdata RL1 - R1 = A0.w; - l$0end: - [ P1 ++ ] = R1; - -// Check results - loadsym I2, output; - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5adf ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x2fc9 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0xbd91 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5520 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x80d5 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x7fef ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x34d1 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x915c ); - pass - - .data; -output: - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/a0.s b/sim/testsuite/sim/bfin/a0.s deleted file mode 100644 index 3bc78d6..0000000 --- a/sim/testsuite/sim/bfin/a0.s +++ /dev/null @@ -1,17 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - R0 = 1; - R0 <<= 1; - DBGA ( R0.L , 2 ); - R0 <<= 1; - DBGA ( R0.L , 4 ); - R0 <<= 3; - DBGA ( R0.L , 32 ); - R0 += 5; - DBGA ( R0.L , 37 ); - R0 += -7; - DBGA ( R0.L , 30 ); - pass diff --git a/sim/testsuite/sim/bfin/a0shift.S b/sim/testsuite/sim/bfin/a0shift.S deleted file mode 100644 index 18bfcbd..0000000 --- a/sim/testsuite/sim/bfin/a0shift.S +++ /dev/null @@ -1,169 +0,0 @@ -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - -// 0xfffffe371c - r0 = 0; - r1 = 0; - r2 = 0; - r3 = 0; - r4 = 0; - r5 = 0; - r6 = 0; - r7 = 0; - a1 = a0 =0; - astat = R0; - - R6.L = 0x8000; - R5.H = 0x8000; - -// load acc with values; - R0.L = 0xc062; - R0.H = 0xffee; - A0.w = R0; - R0.L = 0xc52c; - A0.x = R0; - R0.L = 0x8d10; - R0.H = 0x34c; - A1.w = R0; - R0.L = 0xe10c; - A1.x = R0; -// load regs with values; - R0.L = 0xe844; - R0.H = 0x4aba; - R1.L = 0xa294; - R1.H = 0x52ea; - R2.L = 0xafda; - R2.H = 0x5c32; -// end load regs and acc; - R0.H = (A1 = R5.L * R6.H), R0.L = (A0 += R5.L * R6.H) (FU); -P0 = ASTAT; -CHECKREG P0, (_VS|_V|_V_COPY); - - CHECKREG R0, 0xffff; -R0 = A1.w -CHECKREG R0, 0; -R0 = A1.x -CHECKREG R0, 0; -R0 = A0.w -CHECKREG R0, 0xffeec062; -R0 = A0.x -CHECKREG R0, 0x2c; - P0 = ASTAT; - CHECKREG P0, (_VS|_V|_V_COPY); - R4 = R6 +|- R5 , R3 = R6 -|+ R5; - CHECKREG R3, 0x80008000; - CHECKREG R4, 0x80008000; - P0 = ASTAT; - CHECKREG P0, (_VS|_V|_V_COPY|_AN); - A1 = R7.L * R2.L (M), A0 -= R7.L * R2.H (IS); - P0 = ASTAT; - CHECKREG P0, (_VS|_V|_V_COPY|_AN); - R7.H = R1.H * R3.L (TFU); - CHECKREG R7, 0x29750000; - P0 = ASTAT; - CHECKREG P0, (_VS|_AN); - R7.H = ( A1 -= R2.L * R5.H ), A0 = R2.L * R5.H; - CHECKREG R7, 0xafda0000; -R0 = A1.w -CHECKREG R0, 0xafda0000; -R0 = A1.x -CHECKREG R0, 0xffffffff; -R0 = A0.w -CHECKREG R0, 0x50260000; -R0 = A0.x -CHECKREG R0, 0x0; - P0 = ASTAT; - CHECKREG P0, (_VS|_AN); - R3 = R7.L * R6.H, R2 = R7.L * R6.H (IS); - CHECKREG R3, 0; - CHECKREG R2, 0; - P0 = ASTAT; - CHECKREG P0, (_VS|_AN); - R1.H = (A1 += R7.L * R4.H) (M), R1.L = (A0 = R7.H * R4.H) (FU); - CHECKREG R1, 0xafda57ed; - P0 = ASTAT; -R0 = A1.w -CHECKREG R0, 0xafda0000; -R0 = A1.x -CHECKREG R0, 0xffffffff; -R0 = A0.w -CHECKREG R0, 0x57ed0000; -R0 = A0.x -CHECKREG R0, 0x0; - CHECKREG P0, (_VS|_AN); - R3 = R6.H * R5.L (FU); - CHECKREG R3, 0; - P0 = ASTAT; - CHECKREG P0, (_VS|_AN); - R5.H = ( A1 += R3.L * R1.L ) (M), A0 -= R3.H * R1.H (ISS2); - CHECKREG R5, 0x80000000; -R0 = A1.w -CHECKREG R0, 0xafda0000; -R0 = A1.x -CHECKREG R0, 0xffffffff; -R0 = A0.w -CHECKREG R0, 0x57ed0000; -R0 = A0.x -CHECKREG R0, 0x0; - P0 = ASTAT; - CHECKREG P0, (_VS|_V|_V_COPY|_AN); - R3 = R3 +|- R5 , R6 = R3 -|+ R5 (CO); - CHECKREG R3, 0x80000000; - CHECKREG R6, 0x00008000; - P0 = ASTAT; - CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); - R7 = ( A1 += R4.L * R1.L ) (M), R6 = ( A0 += R4.L * R1.H ); -R0 = A1.w -CHECKREG R0, 0x83e38000; -R0 = A1.x -CHECKREG R0, 0xffffffff; -R0 = A0.w -CHECKREG R0, 0xa8130000; -R0 = A0.x -CHECKREG R0, 0x0; - CHECKREG R6, 0x7fffffff - CHECKREG R7, 0x83e38000 - P0 = ASTAT; - CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); - IF CC P2 = R1; - R2.H = (A1 = R7.L * R5.H) (M), R2.L = (A0 = R7.L * R5.H) (ISS2); - CHECKREG R2, 0x80007fff - P0 = ASTAT; - CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); - R3.H = R4.H * R2.H, R3.L = R4.L * R2.L (T); - CHECKREG R3, 0x7fff8001 - P0 = ASTAT; - CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); - R7 = ( A1 = R7.H * R1.H ) (M), A0 -= R7.H * R1.H (FU); - CHECKREG R7, 0xaabe7c4e - P0 = ASTAT; - CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ); - R0.H = R7.L * R4.H (M), R0.L = R7.L * R4.H (TFU); - CHECKREG R0, 0x3e273e27 - P0 = ASTAT; - CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ); - R5 = ( A1 = R7.L * R7.L ), R4 = ( A0 -= R7.H * R7.H ) (ISS2); - CHECKREG R5, 0x78b74f88 - CHECKREG R4, 0xc73635f8 -R0 = A1.w -CHECKREG R0, 0x3c5ba7c4; -R0 = A1.x -CHECKREG R0, 0x0; -R0 = A0.w -CHECKREG R0, 0xe39b1afc; -R0 = A0.x -CHECKREG R0, 0xffffffff; - R0 = ASTAT; - CHECKREG r0, (_VS|_AV0S|_AZ|_AN); - A0 = A0 >> 2; - R0 = ASTAT; - checkreg r0, (_VS|_AV0S); - R0 = A0.x; - DBGA (R0.L, 0x3f); - R0 = A0.w; - checkreg r0, 0xF8E6C6BF; - - pass diff --git a/sim/testsuite/sim/bfin/a1.s b/sim/testsuite/sim/bfin/a1.s deleted file mode 100644 index 40f9d40..0000000 --- a/sim/testsuite/sim/bfin/a1.s +++ /dev/null @@ -1,29 +0,0 @@ -// check the imm7 bit constants bounds -# mach: bfin - -.include "testutils.inc" - start - - R0 = 63; - DBGA ( R0.L , 63 ); - R0 = -64; - DBGA ( R0.L , 0xffc0 ); - P0 = 63; - R0 = P0; DBGA ( R0.L , 63 ); - P0 = -64; - R0 = P0; DBGA ( R0.L , 0xffc0 ); - -// check loading imm16 into h/l halves - R0.L = 0x1111; - DBGA ( R0.L , 0x1111 ); - - R0.H = 0x1111; - DBGA ( R0.H , 0x1111 ); - - P0.L = 0x2222; - R0 = P0; DBGA ( R0.L , 0x2222 ); - - P0.H = 0x2222; - R0 = P0; DBGA ( R0.H , 0x2222 ); - - pass diff --git a/sim/testsuite/sim/bfin/a10.s b/sim/testsuite/sim/bfin/a10.s deleted file mode 100644 index 4117e60..0000000 --- a/sim/testsuite/sim/bfin/a10.s +++ /dev/null @@ -1,176 +0,0 @@ -// ALU test program. -// Test dual 16 bit MAX, MIN, ABS instructions -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; -// MAX -// first operand is larger, so AN=0 - R0.L = 0x0001; - R0.H = 0x0002; - R1.L = 0x0000; - R1.H = 0x0000; - R7 = MAX ( R0 , R1 ) (V); - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0002 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// second operand is larger - R0.L = 0x0000; - R0.H = 0x0000; - R1.L = 0x0001; - R1.H = 0x0022; - R7 = MAX ( R0 , R1 ) (V); - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0022 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// one operand larger, one smaller. - R0.L = 0x000a; - R0.H = 0x0000; - R1.L = 0x0001; - R1.H = 0x0022; - R7 = MAX ( R0 , R1 ) (V); - DBGA ( R7.L , 0x000a ); - DBGA ( R7.H , 0x0022 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0x8001; - R0.H = 0xffff; - R1.L = 0x8000; - R1.H = 0x0022; - R7 = MAX ( R0 , R1 ) (V); - DBGA ( R7.L , 0x8001 ); - DBGA ( R7.H , 0x0022 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0x8000; - R0.H = 0xffff; - R1.L = 0x8000; - R1.H = 0x0022; - R7 = MAX ( R0 , R1 ) (V); - DBGA ( R7.L , 0x8000 ); - DBGA ( R7.H , 0x0022 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// MIN -// second operand is smaller - R0.L = 0x0001; - R0.H = 0x0004; - R1.L = 0x0000; - R1.H = 0x0000; - R7 = MIN ( R0 , R1 ) (V); - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// first operand is smaller - R0.L = 0xffff; - R0.H = 0x8001; - R1.L = 0x0000; - R1.H = 0x0000; - R7 = MIN ( R0 , R1 ) (V); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x8001 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// one of each - R0.L = 0xffff; - R0.H = 0x0034; - R1.L = 0x0999; - R1.H = 0x0010; - R7 = MIN ( R0 , R1 ) (V); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x0010 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0xffff; - R0.H = 0x0010; - R1.L = 0x0999; - R1.H = 0x0010; - R7 = MIN ( R0 , R1 ) (V); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x0010 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// ABS - R0.L = 0x0001; - R0.H = 0x8001; - R7 = ABS R0 (V); - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x7fff ); - _DBG ASTAT; - R6 = ASTAT; - _DBG R6; - - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = VS; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0x0001; - R0.H = 0x8000; - R7 = ABS R0 (V); - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0x0000; - R0.H = 0xffff; - R7 = ABS R0 (V); - _DBG R7; - _DBG ASTAT; - R6 = ASTAT; - _DBG R6; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0001 ); - CC = VS; R6 = CC; DBGA ( R6.L, 0x1 ); - CC = AZ; R6 = CC; DBGA ( R6.L, 0x1 ); - - pass diff --git a/sim/testsuite/sim/bfin/a11.S b/sim/testsuite/sim/bfin/a11.S deleted file mode 100644 index bf3723a..0000000 --- a/sim/testsuite/sim/bfin/a11.S +++ /dev/null @@ -1,386 +0,0 @@ -// Test ALU RND RND12 RND20 -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - - R7 = 0; - ASTAT = R7; - -// 7ffffff0 -// + 00008000 -// -> 7fff0000 - R0 = 0xfff0 (Z); - R0.H = 0x7fff; - R7.L = R0 (RND); - R0 = ASTAT; - CHECKREG R7, 0x7fff; - CHECKREG R0, (_VS|_V|_V_COPY); - -// 7ffffff0 -// + 00008000 -// -> 7fff0000 - R0.L = 0xfff0; - R0.H = 0x7fff; - R7.H = R0 (RND); - R0 = ASTAT; - CHECKREG R7, 0x7fff7fff; - CHECKREG R0, (_VS|_V|_V_COPY); - -// 7ff0fff0 -// + 00008000 -// -> 7ff10000 - R0.L = 0xfff0; - R0.H = 0x7ff0; - R7.L = R0 (RND); - R0 = ASTAT; - CHECKREG R7, 0x7fff7ff1 - CHECKREG R0, (_VS); - -// 7ff0fff0 -// + 00008000 -// -> 7ff10000 -// 7ff0fff0 -// + 8000 -// -> 7ff1 - R0.L = 0xfff0; - R0.H = 0x7ff0; - R7.H = R0 (RND); - R0 = ASTAT; - CHECKREG R7, 0x7ff17ff1 - CHECKREG R0, (_VS); - -// fffffff0 -// + 00008000 -// -> 00000000 - R0.L = 0xfff0; - R0.H = 0xffff; - R7.L = R0 (RND); - R0 = ASTAT; - CHECKREG R7, 0x7ff10000; - CHECKREG R0, (_VS|_AZ); - -// fffffff0 -// + 00008000 -// -> 00000000 - R0.L = 0xfff0; - R0.H = 0xffff; - R7.H = R0 (RND); - R0 = ASTAT; - DBGA ( R7.H , 0 ); - CHECKREG R0, (_VS|_AZ); - -// 00fffff0 -// + 00008000 -// -> 0100 - R0.L = 0xfff0; - R0.H = 0x00ff; - R7.L = R0 (RND); - R0 = ASTAT; - DBGA ( R7.L , 0x0100 ); - CHECKREG R0, (_VS); - -// RND12 - -// 07ffe000 -// + 00000000 -// = 07ffe000 -// + 00000800 -// -> 7ffe - R0.L = 0xe000; - R0.H = 0x07ff; - R1 = 0x0000 (Z); - R1.H = 0x0000; - R7.L = R0 + R1 (RND12); - R0 = ASTAT; - DBGA ( R7.L , 0x7ffe ); - CHECKREG R0, (_VS); - -// 07ffff00 -// + 00000000 -// = 07ffff00 -// + 00000800 -// -> 7fff - R0.L = 0xff00; - R0.H = 0x07ff; - R1.L = 0x0000; - R1.H = 0x0000; - R7.L = R0 + R1 (RND12); - R0 = ASTAT; - DBGA ( R7.L , 0x7fff ); - CHECKREG R0, (_VS|_V|_V_COPY); - -// 07fffc00 -// + 00000f00 -// = 08000b00 -// + 00000800 -// -> 7fff - R0.L = 0xfc00; - R0.H = 0x07ff; - R1.L = 0x0f00; - R1.H = 0x0000; - R7.L = R0 + R1 (RND12); - R0 = ASTAT; - DBGA ( R7.L , 0x7fff ); - CHECKREG R0, (_VS|_V|_V_COPY); - -// 07ff c000 -// + 0000 1000 -// = 07ff d000 -// + 0000 0800 -// -> 7ff d - R0.L = 0xc000; - R0.H = 0x07ff; - R1.L = 0x1000; - R1.H = 0x0000; - _DBG ASTAT; - R7.L = R0 + R1 (RND12); - _DBG ASTAT; - R0 = ASTAT; - _DBG R0; - DBGA ( R7.L , 0x7ffd ); - CHECKREG R0, (_VS); - -// ffff ffea -// + 07ff fe00 -// = 107ff fdea -// + 0000 0800 -// -> 7ff f - R0.L = 0xffea; - R0.H = 0xffff; - R1.L = 0xfe00; - R1.H = 0x07ff; - _DBG ASTAT; - R7.L = R0 + R1 (RND12); - _DBG ASTAT; - R0 = ASTAT; - _DBG R0; - DBGA ( R7.L , 0x7fff ); - CHECKREG R0, (_VS|_V|_V_COPY); - -// Small negative plus small negative should give zero -// ffff ffff -// + ffff ffff -// + 0000 0800 -// -> 000 0 - R0.L = 0xffff; - R0.H = 0xffff; - R1.L = 0xffff; - R1.H = 0xffff; - _DBG ASTAT; - R7.L = R0 + R1 (RND12); - R0 = ASTAT; - _DBG R0; - DBGA ( R7.L , 0x0000 ); - CHECKREG R0, (_VS|_AZ); - -// Small negative minus small positive should give zero -// ffff ffff -// + 0000 0001 -// - 0000 0800 -// -> 000 0 - R0.L = 0xffff; - R0.H = 0xffff; - R1.L = 0x0001; - R1.H = 0x0000; - R7.L = R0 - R1 (RND12); - R0 = ASTAT; - DBGA ( R7.L , 0x0000 ); - CHECKREG R0, (_VS|_AZ); - -// Large positive plus large positive should give maxpos -// 07ff ffff -// + 07ff ffff -// + 0000 0800 -// -> 7ff f - R0.L = 0xffff; - R0.H = 0x07ff; - R1.L = 0xffff; - R1.H = 0x07ff; - R7.L = R0 + R1 (RND12); - R0 = ASTAT; - DBGA ( R7.L , 0x7fff ); - CHECKREG R0, (_VS|_V|_V_COPY); - -// Large negative plus large negative should give maxneg -// 0800 0000 -// + 0800 0000 -// + 0000 0800 -// -> 800 0 - R0.L = 0x0000; - R0.H = 0x0800; - R1.L = 0x0000; - R1.H = 0x0800; - R7.L = R0 + R1 (RND12); - R0 = ASTAT; - DBGA ( R7.L , 0x7fff ); - CHECKREG R0, (_VS|_V|_V_COPY); - -// Large positive minus large negative should give maxpos -// 07ff ffff -// - 0800 0000 -// + 0000 0800 -// -> 800 0 - R0.L = 0xffff; - R0.H = 0x07ff; - R1.L = 0x0000; - R1.H = 0x0800; - R7.L = R0 - R1 (RND12); - R0 = ASTAT; - _DBG ASTAT; - DBGA ( R7.L , 0x0 ); - CHECKREG R0, (_VS|_AZ); - -// Large negative minus large positive should give maxneg -// 0800 0000 -// - 07ff ffff -// + 0000 0800 -// -> 800 0 - R0.L = 0x0000; - R0.H = 0x0800; - R1.L = 0xffff; - R1.H = 0x07ff; - R7.L = R0 - R1 (RND12); - R0 = ASTAT; - _DBG ASTAT; - DBGA ( R7.L , 0x0000 ); - CHECKREG R0, (_VS|_AZ); - -// cef4 3ed6 -// - 56f4 417a -// + 0000 0800 -// -> 800 0 - R0.L = 0x3ed6; - R0.H = 0xcef4; - R1.L = 0x417a; - R1.H = 0x56f4; - R7.L = R0 - R1 (RND12); - R0 = ASTAT; - DBGA ( R7.L , 0x8000 ); - CHECKREG R0, (_VS|_V|_V_COPY|_AN); - -// RND20 - -// 00ff 0000 -// + 0000 0000 -// + 0008 0000 -// ->0010 - R0.L = 0x0000; - R0.H = 0x00ff; - R1.L = 0x0000; - R1.H = 0x0000; - R7.L = R0 + R1 (RND20); - R0 = ASTAT; - DBGA ( R7.L , 0x0010 ); - CHECKREG R0, (_VS); - -// 00f0 0000 -// + 000f 0000 -// + 0008 0000 -// ->0010 - R0.L = 0x0000; - R0.H = 0x00f0; - R1.L = 0x0000; - R1.H = 0x000f; - R7.L = R0 + R1 (RND20); - R0 = ASTAT; - DBGA ( R7.L , 0x0010 ); - CHECKREG R0, (_VS); - -// 7ff0 0000 -// + 0000 0000 -// + 0008 0000 -// ->07ff - R0.L = 0x0000; - R0.H = 0x7ff0; - R1.L = 0x0000; - R1.H = 0x0000; - R7.L = R0 + R1 (RND20); - R0 = ASTAT; - DBGA ( R7.L , 0x07ff ); - CHECKREG R0, (_VS); - -// 7fff 0000 -// + 0000 0000 -// + 0008 0000 -// ->0800 - R0.L = 0x0000; - R0.H = 0x7fff; - R1.L = 0x0000; - R1.H = 0x0000; - R7.L = R0 + R1 (RND20); - R0 = ASTAT; - DBGA ( R7.L , 0x0800 ); - CHECKREG R0, (_VS); - -// ffff 0000 -// + 0000 0000 -// + 0008 0000 -// ->0000 - R0.L = 0x0000; - R0.H = 0xffff; - R1.L = 0x0000; - R1.H = 0x0000; - R7.L = R0 + R1 (RND20); - R0 = ASTAT; - DBGA ( R7.L , 0x0000 ); - DBGA ( R0.H , 0x0200 ); - DBGA ( R0.L , 0x0001 ); - -// ff00 0000 -// + 0010 0000 -// + 0008 0000 -// ->fff1 - R0.L = 0x0000; - R0.H = 0xff00; - R1.L = 0x0000; - R1.H = 0x0010; - R7.L = R0 + R1 (RND20); - R0 = ASTAT; - DBGA ( R7.L , 0xfff1 ); - CHECKREG R0, (_VS|_AN); - -// ff00 0000 -// + 0018 0000 -// + 0008 0000 -// ->fff2 - R0.L = 0x0000; - R0.H = 0xff00; - R1.L = 0x0000; - R1.H = 0x0018; - R7.L = R0 + R1 (RND20); - R0 = ASTAT; - DBGA ( R7.L , 0xfff2 ); - CHECKREG R0, (_VS|_AN); - -// Small negative plus small negative should give zero -// ffff ffff -// + ffff ffff -// + 0008 0000 -// ->0000 - R0.L = 0xffff; - R0.H = 0xffff; - R1.L = 0xffff; - R1.H = 0xffff; - R7.L = R0 + R1 (RND20); - R0 = ASTAT; - DBGA ( R7.L , 0x0000 ); - CHECKREG R0, (_VS|_AZ); - -// Small negative minus small positive should give zero -// ffff ffff -// + 0000 0010 -// + 0008 0000 -// ->0000 - R0.L = 0xffff; - R0.H = 0xffff; - R1.L = 0x0010; - R1.H = 0x0000; - R7.L = R0 - R1 (RND20); - R0 = ASTAT; - DBGA ( R7.L , 0x0000 ); - CHECKREG R0, (_VS|_AZ); - - pass diff --git a/sim/testsuite/sim/bfin/a12.s b/sim/testsuite/sim/bfin/a12.s deleted file mode 100644 index ddc436e..0000000 --- a/sim/testsuite/sim/bfin/a12.s +++ /dev/null @@ -1,40 +0,0 @@ -// Test SAA -# mach: bfin - -.include "testutils.inc" - start - - I0 = 0; - I1 = 0; - - imm32 R0, 0x04030201; - imm32 R2, 0x04030201; - A1 = A0 = 0; - saa(r1:0,r3:2); - R0 = A0.w; - R1 = A1.w; - CHECKREG R0, 0; - CHECKREG R1, 0; - - imm32 R0, 0x00000201; - imm32 R2, 0x00020102; - A1 = A0 = 0; - saa(r1:0,r3:2); - saa(r1:0,r3:2); - saa(r1:0,r3:2); - R0 = A0.w; - R1 = A1.w; - CHECKREG R0, 0x00030003; - CHECKREG R1, 0x00000006; - - imm32 R0, 0x000300ff; - imm32 R2, 0x0001ff00; - A1 = A0 = 0; - saa(r1:0,r3:2); - saa(r1:0,r3:2); - R0 = A0.w; - R1 = A1.w; - CHECKREG R0, 0x1fe01fe; - CHECKREG R1, 0x0000004; - - pass diff --git a/sim/testsuite/sim/bfin/a2.s b/sim/testsuite/sim/bfin/a2.s deleted file mode 100644 index eb668dd..0000000 --- a/sim/testsuite/sim/bfin/a2.s +++ /dev/null @@ -1,179 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - loadsym P0, middle; - - R0 = [ P0 + 0 ]; DBGA ( R0.L , 50 ); - R0 = [ P0 + 4 ]; DBGA ( R0.L , 51 ); - R0 = [ P0 + 8 ]; DBGA ( R0.L , 52 ); - R0 = [ P0 + 12 ]; DBGA ( R0.L , 53 ); - R0 = [ P0 + 16 ]; DBGA ( R0.L , 54 ); - R0 = [ P0 + 20 ]; DBGA ( R0.L , 55 ); - R0 = [ P0 + 24 ]; DBGA ( R0.L , 56 ); - R0 = [ P0 + 28 ]; DBGA ( R0.L , 57 ); - - R0 = [ P0 + -4 ]; DBGA ( R0.L , 49 ); - R0 = [ P0 + -8 ]; DBGA ( R0.L , 48 ); - R0 = [ P0 + -12 ]; DBGA ( R0.L , 47 ); - R0 = [ P0 + -16 ]; DBGA ( R0.L , 46 ); - R0 = [ P0 + -20 ]; DBGA ( R0.L , 45 ); - R0 = [ P0 + -24 ]; DBGA ( R0.L , 44 ); - R0 = [ P0 + -28 ]; DBGA ( R0.L , 43 ); - R0 = [ P0 + -32 ]; DBGA ( R0.L , 42 ); - - FP = P0; - - R0 = [ FP + 0 ]; DBGA ( R0.L , 50 ); - R0 = [ FP + 4 ]; DBGA ( R0.L , 51 ); - R0 = [ FP + 8 ]; DBGA ( R0.L , 52 ); - R0 = [ FP + 12 ]; DBGA ( R0.L , 53 ); - R0 = [ FP + 16 ]; DBGA ( R0.L , 54 ); - R0 = [ FP + 20 ]; DBGA ( R0.L , 55 ); - R0 = [ FP + 24 ]; DBGA ( R0.L , 56 ); - R0 = [ FP + 28 ]; DBGA ( R0.L , 57 ); - R0 = [ FP + 32 ]; DBGA ( R0.L , 58 ); - R0 = [ FP + 36 ]; DBGA ( R0.L , 59 ); - R0 = [ FP + 40 ]; DBGA ( R0.L , 60 ); - R0 = [ FP + 44 ]; DBGA ( R0.L , 61 ); - R0 = [ FP + 48 ]; DBGA ( R0.L , 62 ); - R0 = [ FP + 52 ]; DBGA ( R0.L , 63 ); - R0 = [ FP + 56 ]; DBGA ( R0.L , 64 ); - R0 = [ FP + 60 ]; DBGA ( R0.L , 65 ); - - R0 = [ FP + -4 ]; DBGA ( R0.L , 49 ); - R0 = [ FP + -8 ]; DBGA ( R0.L , 48 ); - R0 = [ FP + -12 ]; DBGA ( R0.L , 47 ); - R0 = [ FP + -16 ]; DBGA ( R0.L , 46 ); - R0 = [ FP + -20 ]; DBGA ( R0.L , 45 ); - R0 = [ FP + -24 ]; DBGA ( R0.L , 44 ); - R0 = [ FP + -28 ]; DBGA ( R0.L , 43 ); - R0 = [ FP + -32 ]; DBGA ( R0.L , 42 ); - R0 = [ FP + -36 ]; DBGA ( R0.L , 41 ); - R0 = [ FP + -40 ]; DBGA ( R0.L , 40 ); - R0 = [ FP + -44 ]; DBGA ( R0.L , 39 ); - R0 = [ FP + -48 ]; DBGA ( R0.L , 38 ); - R0 = [ FP + -52 ]; DBGA ( R0.L , 37 ); - R0 = [ FP + -56 ]; DBGA ( R0.L , 36 ); - R0 = [ FP + -60 ]; DBGA ( R0.L , 35 ); - R0 = [ FP + -64 ]; DBGA ( R0.L , 34 ); - R0 = [ FP + -68 ]; DBGA ( R0.L , 33 ); - R0 = [ FP + -72 ]; DBGA ( R0.L , 32 ); - R0 = [ FP + -76 ]; DBGA ( R0.L , 31 ); - R0 = [ FP + -80 ]; DBGA ( R0.L , 30 ); - R0 = [ FP + -84 ]; DBGA ( R0.L , 29 ); - R0 = [ FP + -88 ]; DBGA ( R0.L , 28 ); - R0 = [ FP + -92 ]; DBGA ( R0.L , 27 ); - R0 = [ FP + -96 ]; DBGA ( R0.L , 26 ); - R0 = [ FP + -100 ]; DBGA ( R0.L , 25 ); - R0 = [ FP + -104 ]; DBGA ( R0.L , 24 ); - R0 = [ FP + -108 ]; DBGA ( R0.L , 23 ); - R0 = [ FP + -112 ]; DBGA ( R0.L , 22 ); - R0 = [ FP + -116 ]; DBGA ( R0.L , 21 ); - - pass - - .data -base: - .dd 0 - .dd 1 - .dd 2 - .dd 3 - .dd 4 - .dd 5 - .dd 6 - .dd 7 - .dd 8 - .dd 9 - .dd 10 - .dd 11 - .dd 12 - .dd 13 - .dd 14 - .dd 15 - .dd 16 - .dd 17 - .dd 18 - .dd 19 - .dd 20 - .dd 21 - .dd 22 - .dd 23 - .dd 24 - .dd 25 - .dd 26 - .dd 27 - .dd 28 - .dd 29 - .dd 30 - .dd 31 - .dd 32 - .dd 33 - .dd 34 - .dd 35 - .dd 36 - .dd 37 - .dd 38 - .dd 39 - .dd 40 - .dd 41 - .dd 42 - .dd 43 - .dd 44 - .dd 45 - .dd 46 - .dd 47 - .dd 48 - .dd 49 -middle: - .dd 50 - .dd 51 - .dd 52 - .dd 53 - .dd 54 - .dd 55 - .dd 56 - .dd 57 - .dd 58 - .dd 59 - .dd 60 - .dd 61 - .dd 62 - .dd 63 - .dd 64 - .dd 65 - .dd 66 - .dd 67 - .dd 68 - .dd 69 - .dd 70 - .dd 71 - .dd 72 - .dd 73 - .dd 74 - .dd 75 - .dd 76 - .dd 77 - .dd 78 - .dd 79 - .dd 80 - .dd 81 - .dd 82 - .dd 83 - .dd 84 - .dd 85 - .dd 86 - .dd 87 - .dd 88 - .dd 89 - .dd 90 - .dd 91 - .dd 92 - .dd 93 - .dd 94 - .dd 95 - .dd 96 - .dd 97 - .dd 98 - .dd 99 diff --git a/sim/testsuite/sim/bfin/a20.S b/sim/testsuite/sim/bfin/a20.S deleted file mode 100644 index 6245994..0000000 --- a/sim/testsuite/sim/bfin/a20.S +++ /dev/null @@ -1,68 +0,0 @@ -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - R1 = 0; - ASTAT = R1; - - R1.H = -32768; - R2 = 0; - R2.H = -32768; - R3 = R1 +|+ R2; - _DBG ASTAT; - R7 = ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY|_AC1|_AZ); - - R0.L = 32767; - R0.H = 32767; - R0 = R0 +|- R0; - _DBG ASTAT; - R7 = ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN|_AZ) - - R0 = 0; - ASTAT = R0; - _DBG ASTAT; - R7 = ASTAT; - CHECKREG R7, (_UNSET) - - R1.L = -1; - R1.H = 0x7fff; - R0 = ABS R1; - _DBG R0; - _DBG ASTAT; - R7 = ASTAT; - CHECKREG R7, (_UNSET) - - R1=0; - R1.H = 0x8000; - _DBG R1; - R0 = ABS R1; - _DBG R0; - _DBG ASTAT; - R7 = ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY) - - R0 = 0; - ASTAT = R0; - - R1.L = 32767; - R1.H = 32767; - R0 = R1 +|+ R1 (CO); - _DBG R0; - _DBG ASTAT; - R7 = ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY|_AN) - - R0.L = -1; - R0.H = 32766; - R1.L = -1; - R1.H = -32768; - R0 = PACK( R0.H , R1.L ); - _DBG R0; - R7 = ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY|_AN) - - pass diff --git a/sim/testsuite/sim/bfin/a21.s b/sim/testsuite/sim/bfin/a21.s deleted file mode 100644 index c621921..0000000 --- a/sim/testsuite/sim/bfin/a21.s +++ /dev/null @@ -1,83 +0,0 @@ -// Test ALU RND RND12 RND20 -# mach: bfin - -.include "testutils.inc" - start - - -// positive saturation - R0 = 0xffffffff; - A0.w = R0; - A1.w = R0; - R0 = 0x7f (X); - A0.x = R0; - A1.x = R0; - R3 = A1 + A0, R4 = A1 - A0 (S); - DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff ); - DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 ); - -// neg saturation - R0 = 0; - A0.w = R0; - A1.w = R0; - R0 = 0x80 (X); - A0.x = R0; - A1.x = R0; - R3 = A1 + A0, R4 = A1 - A0 (S); - DBGA ( R3.H , 0x8000 ); DBGA ( R3.L , 0x0000 ); - DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 ); - -// positive saturation - R0 = 0xfffffff0; - A0.w = R0; - A1.w = R0; - R0 = 0x01; - A0.x = R0; - A1.x = R0; - R3 = A1 + A0, R4 = A1 - A0 (S); - DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff ); - DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 ); - -// no sat - R0 = 0xfffffff0; - A0.w = R0; - A1.w = R0; - R0 = 0x01; - A0.x = R0; - A1.x = R0; - R3 = A1 + A0, R4 = A1 - A0 (NS); - DBGA ( R3.H , 0xffff ); DBGA ( R3.L , 0xffe0 ); - DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 ); - -// add and sub +1 -1 - R0 = 0x00000001; - A0.w = R0; - R0 = 0xffffffff; - A1.w = R0; - R0 = 0; - A0.x = R0; - R0 = 0xff (X); - A1.x = R0; - R3 = A1 + A0, R4 = A1 - A0 (NS); - DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); // 0 - DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); // -2 - -// should get the same with saturation - R3 = A1 + A0, R4 = A1 - A0 (S); - DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); // 0 - DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); // -2 - -// add and sub -1 +1 but with reverse order of A0 A1 - R0 = 0x00000001; - A0.w = R0; - R0 = 0xffffffff; - A1.w = R0; - R0 = 0; - A0.x = R0; - R0 = 0xff (X); - A1.x = R0; - R3 = A0 + A1, R4 = A0 - A1 (NS); - DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); - DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0002 ); - - pass diff --git a/sim/testsuite/sim/bfin/a22.s b/sim/testsuite/sim/bfin/a22.s deleted file mode 100644 index 1df76df..0000000 --- a/sim/testsuite/sim/bfin/a22.s +++ /dev/null @@ -1,83 +0,0 @@ -// Test ALU NEG accumulators -# mach: bfin - -.include "testutils.inc" - start - - - R0 = 0xffffffff; - A0.w = R0; - R0 = 0x7f (X); - A0.x = R0; - A0 = - A0; - _DBG A0; - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 ); - DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff80 ); - - R0 = 0x1; - A0.w = R0; - R0 = 0x0; - A0.x = R0; - A0 = - A0; - R4 = A0.w; - R5 = A0.x; - _DBG A0; - DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); - DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); - - R0 = 0xffffffff; - A0.w = R0; - R0 = 0xff (X); - A0.x = R0; - A0 = - A0; - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); - - R0 = 0x00000000; - A0.w = R0; - R0 = 0x80 (X); - A0.x = R0; - A0 = - A0; - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); - -// NEG NEG - R0 = 0x00000000; - A0.w = R0; - R0 = 0x80 (X); - A0.x = R0; - - R0 = 0xffffffff; - A1.w = R0; - R0 = 0x7f (X); - A1.x = R0; - - A1 = - A1, A0 = - A0; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); - - R4 = A1.w; - R5 = A1.x; - _DBG A1; - DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 ); - DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff80 ); - -// NEG NEG register - R0.L = 0x0001; - R0.H = 0x8000; - - R3 = - R0 (V); - DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff ); - - _DBG ASTAT; - - pass diff --git a/sim/testsuite/sim/bfin/a23.s b/sim/testsuite/sim/bfin/a23.s deleted file mode 100644 index d63fa0c..0000000 --- a/sim/testsuite/sim/bfin/a23.s +++ /dev/null @@ -1,84 +0,0 @@ -// Test ALU ABS accumulators -# mach: bfin - -.include "testutils.inc" - start - - - R0 = 0x00000000; - A0.w = R0; - R0 = 0x80 (X); - A0.x = R0; - - A0 = ABS A0; - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); - - R0 = 0x00000001; - A0.w = R0; - R0 = 0x80 (X); - A0.x = R0; - - A0 = ABS A0; - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); - - R0 = 0xffffffff; - A0.w = R0; - R0 = 0xff (X); - A0.x = R0; - - A0 = ABS A0; - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); - - R0 = 0xfffffff0; - A0.w = R0; - R0 = 0x7f (X); - A0.x = R0; - - A0 = ABS A0; - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfff0 ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); - - R0 = 0x00000000; - A0.w = R0; - R0 = 0x80 (X); - A0.x = R0; - - A1 = ABS A0; - R4 = A1.w; - R5 = A1.x; - DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); - - R0 = 0x00000000; - A0.w = R0; - R0 = 0x80 (X); - A0.x = R0; - - R0 = 0x00000002; - A1.w = R0; - R0 = 0x80 (X); - A1.x = R0; - - A1 = ABS A1, A0 = ABS A0; - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); - - R4 = A1.w; - R5 = A1.x; - DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); - - pass diff --git a/sim/testsuite/sim/bfin/a24.s b/sim/testsuite/sim/bfin/a24.s deleted file mode 100644 index 507350f..0000000 --- a/sim/testsuite/sim/bfin/a24.s +++ /dev/null @@ -1,12 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0x1111 (X); - R0.H = 0x1111; - A0.x = R0; - R1 = A0.x; - DBGA ( R1.L , 0x11 ); - DBGA ( R1.H , 0x0 ); - pass diff --git a/sim/testsuite/sim/bfin/a25.s b/sim/testsuite/sim/bfin/a25.s deleted file mode 100644 index b5d5d7b..0000000 --- a/sim/testsuite/sim/bfin/a25.s +++ /dev/null @@ -1,28 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - A1 = A0 = 0; - R0.L = 0x01; - A0.x = R0; -//A0 = 0x0100000000 -//A1 = 0x0000000000 - - R4.L = 0x2d1a; - R4.H = 0x32e0; - - A1.x = R4; -//A1 = 0x1a00000000 - - A0.w = A1.x; - - _DBG A0; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x001a ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0001 ); - - pass diff --git a/sim/testsuite/sim/bfin/a26.s b/sim/testsuite/sim/bfin/a26.s deleted file mode 100644 index 2e9a0b5..0000000 --- a/sim/testsuite/sim/bfin/a26.s +++ /dev/null @@ -1,72 +0,0 @@ -// Test ALU SEARCH instruction -# mach: bfin - -.include "testutils.inc" - start - - - init_r_regs 0; - ASTAT = R0; - - R0 = 4; - R1 = 5; - A1 = A0 = 0; - - R2.L = 0x0001; - R2.H = 0xffff; - - loadsym P0, foo; - - ( R1 , R0 ) = SEARCH R2 (GT); - - // R0 should be the pointer - R7 = P0; - CC = R0 == R7; - if !CC JUMP _fail; - - _DBG R1; // does not change - DBGA ( R1.H , 0 ); DBGA ( R1.L , 0x5 ); - - _DBG A0; // changes - R0 = A0.w; - DBGA ( R0.H , 0 ); DBGA ( R0.L , 0x1 ); - - _DBG A1; // does not change - R0 = A1.w; - DBGA ( R0.H , 0 ); DBGA ( R0.L , 0 ); - - R0 = 4; - R1 = 5; - A1 = A0 = 0; - - R2.L = 0x0000; - R2.H = 0xffff; - - loadsym p0, foo; - - ( R1 , R0 ) = SEARCH R2 (LT); - - _DBG R0; // no change - DBGA ( R0.H , 0 ); DBGA ( R0.L , 4 ); - - _DBG R1; // change - R7 = P0; - CC = R1 == R7; - if !CC JUMP _fail; - - _DBG A0; - R0 = A0.w; - DBGA ( R0.H , 0 ); DBGA ( R0.L , 0 ); - - _DBG A1; - R0 = A1.w; - DBGA ( R0.H , 0xffff ); DBGA ( R0.L , 0xffff ); - - pass - -_fail: - fail; - - .data -foo: - .space (0x100) diff --git a/sim/testsuite/sim/bfin/a3.s b/sim/testsuite/sim/bfin/a3.s deleted file mode 100644 index c53300b..0000000 --- a/sim/testsuite/sim/bfin/a3.s +++ /dev/null @@ -1,313 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - loadsym P1, middle; - - R0 = W [ P1 + -2 ] (Z); DBGA ( R0.L , 49 ); - R0 = W [ P1 + -4 ] (Z); DBGA ( R0.L , 48 ); - R0 = W [ P1 + -6 ] (Z); DBGA ( R0.L , 47 ); - R0 = W [ P1 + -8 ] (Z); DBGA ( R0.L , 46 ); - R0 = W [ P1 + -10 ] (Z); DBGA ( R0.L , 45 ); - R0 = W [ P1 + -12 ] (Z); DBGA ( R0.L , 44 ); - R0 = W [ P1 + -14 ] (Z); DBGA ( R0.L , 43 ); - R0 = W [ P1 + -16 ] (Z); DBGA ( R0.L , 42 ); - R0 = W [ P1 + -18 ] (Z); DBGA ( R0.L , 41 ); - R0 = W [ P1 + -20 ] (Z); DBGA ( R0.L , 40 ); - R0 = W [ P1 + -22 ] (Z); DBGA ( R0.L , 39 ); - R0 = W [ P1 + -24 ] (Z); DBGA ( R0.L , 38 ); - R0 = W [ P1 + -26 ] (Z); DBGA ( R0.L , 37 ); - R0 = W [ P1 + -28 ] (Z); DBGA ( R0.L , 36 ); - R0 = W [ P1 + -30 ] (Z); DBGA ( R0.L , 35 ); - R0 = W [ P1 + -32 ] (Z); DBGA ( R0.L , 34 ); - R0 = W [ P1 + -34 ] (Z); DBGA ( R0.L , 33 ); - R0 = W [ P1 + -36 ] (Z); DBGA ( R0.L , 32 ); - R0 = W [ P1 + -38 ] (Z); DBGA ( R0.L , 31 ); - R0 = W [ P1 + -40 ] (Z); DBGA ( R0.L , 30 ); - R0 = W [ P1 + -42 ] (Z); DBGA ( R0.L , 29 ); - R0 = W [ P1 + -44 ] (Z); DBGA ( R0.L , 28 ); - R0 = W [ P1 + -46 ] (Z); DBGA ( R0.L , 27 ); - R0 = W [ P1 + -48 ] (Z); DBGA ( R0.L , 26 ); - R0 = W [ P1 + -50 ] (Z); DBGA ( R0.L , 25 ); - R0 = W [ P1 + -52 ] (Z); DBGA ( R0.L , 24 ); - R0 = W [ P1 + -54 ] (Z); DBGA ( R0.L , 23 ); - R0 = W [ P1 + -56 ] (Z); DBGA ( R0.L , 22 ); - R0 = W [ P1 + -58 ] (Z); DBGA ( R0.L , 21 ); - R0 = W [ P1 + -60 ] (Z); DBGA ( R0.L , 20 ); - R0 = W [ P1 + -62 ] (Z); DBGA ( R0.L , 19 ); - R0 = W [ P1 + -64 ] (Z); DBGA ( R0.L , 18 ); - R0 = W [ P1 + -66 ] (Z); DBGA ( R0.L , 17 ); - R0 = W [ P1 + -68 ] (Z); DBGA ( R0.L , 16 ); - R0 = W [ P1 + -70 ] (Z); DBGA ( R0.L , 15 ); - R0 = W [ P1 + -72 ] (Z); DBGA ( R0.L , 14 ); - R0 = W [ P1 + -74 ] (Z); DBGA ( R0.L , 13 ); - R0 = W [ P1 + -76 ] (Z); DBGA ( R0.L , 12 ); - R0 = W [ P1 + -78 ] (Z); DBGA ( R0.L , 11 ); - R0 = W [ P1 + -80 ] (Z); DBGA ( R0.L , 10 ); - R0 = W [ P1 + -82 ] (Z); DBGA ( R0.L , 9 ); - R0 = W [ P1 + -84 ] (Z); DBGA ( R0.L , 8 ); - R0 = W [ P1 + -86 ] (Z); DBGA ( R0.L , 7 ); - R0 = W [ P1 + -88 ] (Z); DBGA ( R0.L , 6 ); - R0 = W [ P1 + -90 ] (Z); DBGA ( R0.L , 5 ); - R0 = W [ P1 + -92 ] (Z); DBGA ( R0.L , 4 ); - R0 = W [ P1 + -94 ] (Z); DBGA ( R0.L , 3 ); - R0 = W [ P1 + -96 ] (Z); DBGA ( R0.L , 2 ); - R0 = W [ P1 + -98 ] (Z); DBGA ( R0.L , 1 ); - R0 = W [ P1 + 0 ] (Z); DBGA ( R0.L , 50 ); - R0 = W [ P1 + 2 ] (Z); DBGA ( R0.L , 51 ); - R0 = W [ P1 + 4 ] (Z); DBGA ( R0.L , 52 ); - R0 = W [ P1 + 6 ] (Z); DBGA ( R0.L , 53 ); - R0 = W [ P1 + 8 ] (Z); DBGA ( R0.L , 54 ); - R0 = W [ P1 + 10 ] (Z); DBGA ( R0.L , 55 ); - R0 = W [ P1 + 12 ] (Z); DBGA ( R0.L , 56 ); - R0 = W [ P1 + 14 ] (Z); DBGA ( R0.L , 57 ); - R0 = W [ P1 + 16 ] (Z); DBGA ( R0.L , 58 ); - R0 = W [ P1 + 18 ] (Z); DBGA ( R0.L , 59 ); - R0 = W [ P1 + 20 ] (Z); DBGA ( R0.L , 60 ); - R0 = W [ P1 + 22 ] (Z); DBGA ( R0.L , 61 ); - R0 = W [ P1 + 24 ] (Z); DBGA ( R0.L , 62 ); - R0 = W [ P1 + 26 ] (Z); DBGA ( R0.L , 63 ); - R0 = W [ P1 + 28 ] (Z); DBGA ( R0.L , 64 ); - R0 = W [ P1 + 30 ] (Z); DBGA ( R0.L , 65 ); - R0 = W [ P1 + 32 ] (Z); DBGA ( R0.L , 66 ); - R0 = W [ P1 + 34 ] (Z); DBGA ( R0.L , 67 ); - R0 = W [ P1 + 36 ] (Z); DBGA ( R0.L , 68 ); - R0 = W [ P1 + 38 ] (Z); DBGA ( R0.L , 69 ); - R0 = W [ P1 + 40 ] (Z); DBGA ( R0.L , 70 ); - R0 = W [ P1 + 42 ] (Z); DBGA ( R0.L , 71 ); - R0 = W [ P1 + 44 ] (Z); DBGA ( R0.L , 72 ); - R0 = W [ P1 + 46 ] (Z); DBGA ( R0.L , 73 ); - R0 = W [ P1 + 48 ] (Z); DBGA ( R0.L , 74 ); - R0 = W [ P1 + 50 ] (Z); DBGA ( R0.L , 75 ); - R0 = W [ P1 + 52 ] (Z); DBGA ( R0.L , 76 ); - R0 = W [ P1 + 54 ] (Z); DBGA ( R0.L , 77 ); - R0 = W [ P1 + 56 ] (Z); DBGA ( R0.L , 78 ); - R0 = W [ P1 + 58 ] (Z); DBGA ( R0.L , 79 ); - R0 = W [ P1 + 60 ] (Z); DBGA ( R0.L , 80 ); - R0 = W [ P1 + 62 ] (Z); DBGA ( R0.L , 81 ); - R0 = W [ P1 + 64 ] (Z); DBGA ( R0.L , 82 ); - R0 = W [ P1 + 66 ] (Z); DBGA ( R0.L , 83 ); - R0 = W [ P1 + 68 ] (Z); DBGA ( R0.L , 84 ); - R0 = W [ P1 + 70 ] (Z); DBGA ( R0.L , 85 ); - R0 = W [ P1 + 72 ] (Z); DBGA ( R0.L , 86 ); - R0 = W [ P1 + 74 ] (Z); DBGA ( R0.L , 87 ); - R0 = W [ P1 + 76 ] (Z); DBGA ( R0.L , 88 ); - R0 = W [ P1 + 78 ] (Z); DBGA ( R0.L , 89 ); - R0 = W [ P1 + 80 ] (Z); DBGA ( R0.L , 90 ); - R0 = W [ P1 + 82 ] (Z); DBGA ( R0.L , 91 ); - R0 = W [ P1 + 84 ] (Z); DBGA ( R0.L , 92 ); - R0 = W [ P1 + 86 ] (Z); DBGA ( R0.L , 93 ); - R0 = W [ P1 + 88 ] (Z); DBGA ( R0.L , 94 ); - R0 = W [ P1 + 90 ] (Z); DBGA ( R0.L , 95 ); - R0 = W [ P1 + 92 ] (Z); DBGA ( R0.L , 96 ); - R0 = W [ P1 + 94 ] (Z); DBGA ( R0.L , 97 ); - R0 = W [ P1 + 96 ] (Z); DBGA ( R0.L , 98 ); - R0 = W [ P1 + 98 ] (Z); DBGA ( R0.L , 99 ); - - FP = P1; - - R0 = W [ FP + -2 ] (Z); DBGA ( R0.L , 49 ); - R0 = W [ FP + -4 ] (Z); DBGA ( R0.L , 48 ); - R0 = W [ FP + -6 ] (Z); DBGA ( R0.L , 47 ); - R0 = W [ FP + -8 ] (Z); DBGA ( R0.L , 46 ); - R0 = W [ FP + -10 ] (Z); DBGA ( R0.L , 45 ); - R0 = W [ FP + -12 ] (Z); DBGA ( R0.L , 44 ); - R0 = W [ FP + -14 ] (Z); DBGA ( R0.L , 43 ); - R0 = W [ FP + -16 ] (Z); DBGA ( R0.L , 42 ); - R0 = W [ FP + -18 ] (Z); DBGA ( R0.L , 41 ); - R0 = W [ FP + -20 ] (Z); DBGA ( R0.L , 40 ); - R0 = W [ FP + -22 ] (Z); DBGA ( R0.L , 39 ); - R0 = W [ FP + -24 ] (Z); DBGA ( R0.L , 38 ); - R0 = W [ FP + -26 ] (Z); DBGA ( R0.L , 37 ); - R0 = W [ FP + -28 ] (Z); DBGA ( R0.L , 36 ); - R0 = W [ FP + -30 ] (Z); DBGA ( R0.L , 35 ); - R0 = W [ FP + -32 ] (Z); DBGA ( R0.L , 34 ); - R0 = W [ FP + -34 ] (Z); DBGA ( R0.L , 33 ); - R0 = W [ FP + -36 ] (Z); DBGA ( R0.L , 32 ); - R0 = W [ FP + -38 ] (Z); DBGA ( R0.L , 31 ); - R0 = W [ FP + -40 ] (Z); DBGA ( R0.L , 30 ); - R0 = W [ FP + -42 ] (Z); DBGA ( R0.L , 29 ); - R0 = W [ FP + -44 ] (Z); DBGA ( R0.L , 28 ); - R0 = W [ FP + -46 ] (Z); DBGA ( R0.L , 27 ); - R0 = W [ FP + -48 ] (Z); DBGA ( R0.L , 26 ); - R0 = W [ FP + -50 ] (Z); DBGA ( R0.L , 25 ); - R0 = W [ FP + -52 ] (Z); DBGA ( R0.L , 24 ); - R0 = W [ FP + -54 ] (Z); DBGA ( R0.L , 23 ); - R0 = W [ FP + -56 ] (Z); DBGA ( R0.L , 22 ); - R0 = W [ FP + -58 ] (Z); DBGA ( R0.L , 21 ); - R0 = W [ FP + -60 ] (Z); DBGA ( R0.L , 20 ); - R0 = W [ FP + -62 ] (Z); DBGA ( R0.L , 19 ); - R0 = W [ FP + -64 ] (Z); DBGA ( R0.L , 18 ); - R0 = W [ FP + -66 ] (Z); DBGA ( R0.L , 17 ); - R0 = W [ FP + -68 ] (Z); DBGA ( R0.L , 16 ); - R0 = W [ FP + -70 ] (Z); DBGA ( R0.L , 15 ); - R0 = W [ FP + -72 ] (Z); DBGA ( R0.L , 14 ); - R0 = W [ FP + -74 ] (Z); DBGA ( R0.L , 13 ); - R0 = W [ FP + -76 ] (Z); DBGA ( R0.L , 12 ); - R0 = W [ FP + -78 ] (Z); DBGA ( R0.L , 11 ); - R0 = W [ FP + -80 ] (Z); DBGA ( R0.L , 10 ); - R0 = W [ FP + -82 ] (Z); DBGA ( R0.L , 9 ); - R0 = W [ FP + -84 ] (Z); DBGA ( R0.L , 8 ); - R0 = W [ FP + -86 ] (Z); DBGA ( R0.L , 7 ); - R0 = W [ FP + -88 ] (Z); DBGA ( R0.L , 6 ); - R0 = W [ FP + -90 ] (Z); DBGA ( R0.L , 5 ); - R0 = W [ FP + -92 ] (Z); DBGA ( R0.L , 4 ); - R0 = W [ FP + -94 ] (Z); DBGA ( R0.L , 3 ); - R0 = W [ FP + -96 ] (Z); DBGA ( R0.L , 2 ); - R0 = W [ FP + -98 ] (Z); DBGA ( R0.L , 1 ); - R0 = W [ FP + 0 ] (Z); DBGA ( R0.L , 50 ); - R0 = W [ FP + 2 ] (Z); DBGA ( R0.L , 51 ); - R0 = W [ FP + 4 ] (Z); DBGA ( R0.L , 52 ); - R0 = W [ FP + 6 ] (Z); DBGA ( R0.L , 53 ); - R0 = W [ FP + 8 ] (Z); DBGA ( R0.L , 54 ); - R0 = W [ FP + 10 ] (Z); DBGA ( R0.L , 55 ); - R0 = W [ FP + 12 ] (Z); DBGA ( R0.L , 56 ); - R0 = W [ FP + 14 ] (Z); DBGA ( R0.L , 57 ); - R0 = W [ FP + 16 ] (Z); DBGA ( R0.L , 58 ); - R0 = W [ FP + 18 ] (Z); DBGA ( R0.L , 59 ); - R0 = W [ FP + 20 ] (Z); DBGA ( R0.L , 60 ); - R0 = W [ FP + 22 ] (Z); DBGA ( R0.L , 61 ); - R0 = W [ FP + 24 ] (Z); DBGA ( R0.L , 62 ); - R0 = W [ FP + 26 ] (Z); DBGA ( R0.L , 63 ); - R0 = W [ FP + 28 ] (Z); DBGA ( R0.L , 64 ); - R0 = W [ FP + 30 ] (Z); DBGA ( R0.L , 65 ); - R0 = W [ FP + 32 ] (Z); DBGA ( R0.L , 66 ); - R0 = W [ FP + 34 ] (Z); DBGA ( R0.L , 67 ); - R0 = W [ FP + 36 ] (Z); DBGA ( R0.L , 68 ); - R0 = W [ FP + 38 ] (Z); DBGA ( R0.L , 69 ); - R0 = W [ FP + 40 ] (Z); DBGA ( R0.L , 70 ); - R0 = W [ FP + 42 ] (Z); DBGA ( R0.L , 71 ); - R0 = W [ FP + 44 ] (Z); DBGA ( R0.L , 72 ); - R0 = W [ FP + 46 ] (Z); DBGA ( R0.L , 73 ); - R0 = W [ FP + 48 ] (Z); DBGA ( R0.L , 74 ); - R0 = W [ FP + 50 ] (Z); DBGA ( R0.L , 75 ); - R0 = W [ FP + 52 ] (Z); DBGA ( R0.L , 76 ); - R0 = W [ FP + 54 ] (Z); DBGA ( R0.L , 77 ); - R0 = W [ FP + 56 ] (Z); DBGA ( R0.L , 78 ); - R0 = W [ FP + 58 ] (Z); DBGA ( R0.L , 79 ); - R0 = W [ FP + 60 ] (Z); DBGA ( R0.L , 80 ); - R0 = W [ FP + 62 ] (Z); DBGA ( R0.L , 81 ); - R0 = W [ FP + 64 ] (Z); DBGA ( R0.L , 82 ); - R0 = W [ FP + 66 ] (Z); DBGA ( R0.L , 83 ); - R0 = W [ FP + 68 ] (Z); DBGA ( R0.L , 84 ); - R0 = W [ FP + 70 ] (Z); DBGA ( R0.L , 85 ); - R0 = W [ FP + 72 ] (Z); DBGA ( R0.L , 86 ); - R0 = W [ FP + 74 ] (Z); DBGA ( R0.L , 87 ); - R0 = W [ FP + 76 ] (Z); DBGA ( R0.L , 88 ); - R0 = W [ FP + 78 ] (Z); DBGA ( R0.L , 89 ); - R0 = W [ FP + 80 ] (Z); DBGA ( R0.L , 90 ); - R0 = W [ FP + 82 ] (Z); DBGA ( R0.L , 91 ); - R0 = W [ FP + 84 ] (Z); DBGA ( R0.L , 92 ); - R0 = W [ FP + 86 ] (Z); DBGA ( R0.L , 93 ); - R0 = W [ FP + 88 ] (Z); DBGA ( R0.L , 94 ); - R0 = W [ FP + 90 ] (Z); DBGA ( R0.L , 95 ); - R0 = W [ FP + 92 ] (Z); DBGA ( R0.L , 96 ); - R0 = W [ FP + 94 ] (Z); DBGA ( R0.L , 97 ); - R0 = W [ FP + 96 ] (Z); DBGA ( R0.L , 98 ); - R0 = W [ FP + 98 ] (Z); DBGA ( R0.L , 99 ); - pass - - .data - - .dw 0 - .dw 1 - .dw 2 - .dw 3 - .dw 4 - .dw 5 - .dw 6 - .dw 7 - .dw 8 - .dw 9 - .dw 10 - .dw 11 - .dw 12 - .dw 13 - .dw 14 - .dw 15 - .dw 16 - .dw 17 - .dw 18 - .dw 19 - .dw 20 - .dw 21 - .dw 22 - .dw 23 - .dw 24 - .dw 25 - .dw 26 - .dw 27 - .dw 28 - .dw 29 - .dw 30 - .dw 31 - .dw 32 - .dw 33 - .dw 34 - .dw 35 - .dw 36 - .dw 37 - .dw 38 - .dw 39 - .dw 40 - .dw 41 - .dw 42 - .dw 43 - .dw 44 - .dw 45 - .dw 46 - .dw 47 - .dw 48 - .dw 49 -middle: - .dw 50 - .dw 51 - .dw 52 - .dw 53 - .dw 54 - .dw 55 - .dw 56 - .dw 57 - .dw 58 - .dw 59 - .dw 60 - .dw 61 - .dw 62 - .dw 63 - .dw 64 - .dw 65 - .dw 66 - .dw 67 - .dw 68 - .dw 69 - .dw 70 - .dw 71 - .dw 72 - .dw 73 - .dw 74 - .dw 75 - .dw 76 - .dw 77 - .dw 78 - .dw 79 - .dw 80 - .dw 81 - .dw 82 - .dw 83 - .dw 84 - .dw 85 - .dw 86 - .dw 87 - .dw 88 - .dw 89 - .dw 90 - .dw 91 - .dw 92 - .dw 93 - .dw 94 - .dw 95 - .dw 96 - .dw 97 - .dw 98 - .dw 99 diff --git a/sim/testsuite/sim/bfin/a30.s b/sim/testsuite/sim/bfin/a30.s deleted file mode 100644 index 38dd401..0000000 --- a/sim/testsuite/sim/bfin/a30.s +++ /dev/null @@ -1,55 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - R0.L = 0.5; - R0.H = 0.5; - R1.L = 0.5; - R1.H = 0.5; - - R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); - _DBGCMPLX R2; - _DBGCMPLX R3; - - DBGA ( R2.L , 0.5 ); - DBGA ( R2.H , 0.5 ); - DBGA ( R3.L , 0 ); - DBGA ( R3.H , 0 ); - - R1.L = 0.125; - R1.H = 0.125; - - R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); - _DBGCMPLX R2; - _DBGCMPLX R3; - DBGA ( R2.L , 0.3125 ); - DBGA ( R2.H , 0.3125 ); - DBGA ( R3.L , 0.1875 ); - DBGA ( R3.H , 0.1875 ); - - R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR); - _DBGCMPLX R0; - _DBGCMPLX R1; - DBGA ( R0.L , 0.25 ); - DBGA ( R0.H , 0.25 ); - DBGA ( R1.L , 0.0625 ); - DBGA ( R1.H , 0.0625 ); - - R0 = 1; - R0 <<= 15; - R1 = R0 << 16; - r0=r0 | r1; - R1 = R0; - - R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); - - _DBGCMPLX R2; - _DBGCMPLX R3; - DBGA ( R0.L , 0x8000 ); - DBGA ( R0.H , 0x8000 ); - DBGA ( R1.L , 0x8000 ); - DBGA ( R1.H , 0x8000 ); - - pass diff --git a/sim/testsuite/sim/bfin/a4.s b/sim/testsuite/sim/bfin/a4.s deleted file mode 100644 index d0f5ef5..0000000 --- a/sim/testsuite/sim/bfin/a4.s +++ /dev/null @@ -1,36 +0,0 @@ -# Blackfin testcase for signbits -# mach: bfin - - .include "testutils.inc" - - start - -xx: - R0 = 1; - CALL red; - JUMP.L aa; - - .align 16 -aa: - R0 = 2; - CALL red; - JUMP.S bb; - - .align 16 -bb: - R0 = 3; - CALL red; - JUMP.S ccd; - - .align 16 -red: - RTS; - - .align 16 -ccd: - R1 = 3 (Z); - CC = R0 == R1 - if CC jump 1f; - fail -1: - pass diff --git a/sim/testsuite/sim/bfin/a5.s b/sim/testsuite/sim/bfin/a5.s deleted file mode 100644 index d0c0143..0000000 --- a/sim/testsuite/sim/bfin/a5.s +++ /dev/null @@ -1,140 +0,0 @@ -// ALU test program. -// Test instructions -// rL4= L+L (r2,r3); -// rH4= L+H (r2,r3) S; -// rL4= L-L (r2,r3); -// rH4= L-H (r2,r3) S; -# mach: bfin - -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - -// overflow positive - R0.L = 0x0000; - R0.H = 0x7fff; - R1.L = 0x7fff; - R1.H = 0x0000; - R7 = 0; - ASTAT = R7; - R3.L = R0.H + R1.L (NS); - DBGA ( R3.L , 0xfffe ); - DBGA ( R3.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - -// overflow negative - R0.L = 0xffff; - R0.H = 0x0000; - R1.L = 0x0000; - R1.H = 0x8000; - R3 = 0; - R7 = 0; - ASTAT = R7; - R3.H = R0.L + R1.H (NS); - DBGA ( R3.L , 0x0000 ); - DBGA ( R3.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// saturate positive - R0.L = 0x0000; - R0.H = 0x7fff; - R1.L = 0x7fff; - R1.H = 0x0000; - R3 = 0; - R7 = 0; - ASTAT = R7; - R3.L = R0.H + R1.L (S); - DBGA ( R3.L , 0x7fff ); - DBGA ( R3.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - -// saturate negative - R0.L = 0xffff; - R0.H = 0x0000; - R1.L = 0x0000; - R1.H = 0x8000; - R3 = 0; - R7 = 0; - ASTAT = R7; - R3.L = R0.L + R1.H (S); - DBGA ( R3.L , 0x8000 ); - DBGA ( R3.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// overflow positive with subtraction - R0.L = 0x0000; - R0.H = 0x7fff; - R1.L = 0xffff; - R1.H = 0x0000; - R7 = 0; - ASTAT = R7; - R3.L = R0.H - R1.L (NS); - DBGA ( R3.L , 0x8000 ); - DBGA ( R3.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - -// overflow negative with subtraction - R0.L = 0x8000; - R0.H = 0x0000; - R1.L = 0x0000; - R1.H = 0x0001; - R3 = 0; - R7 = 0; - ASTAT = R7; - R3.H = R0.L - R1.H (NS); - DBGA ( R3.L , 0x0000 ); - DBGA ( R3.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// saturate positive with subtraction - R0.L = 0x0000; - R0.H = 0x7fff; - R1.L = 0xffff; - R1.H = 0x0000; - R7 = 0; - ASTAT = R7; - R3.H = R0.H - R1.L (S); - DBGA ( R3.L , 0x0000 ); - DBGA ( R3.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - -// saturate negative with subtraction - R0.L = 0x8000; - R0.H = 0x0000; - R1.L = 0x0000; - R1.H = 0x0001; - R3 = 0; - R7 = 0; - ASTAT = R7; - R3.H = R0.L - R1.H (S); - DBGA ( R3.L , 0x0000 ); - DBGA ( R3.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - - pass diff --git a/sim/testsuite/sim/bfin/a6.s b/sim/testsuite/sim/bfin/a6.s deleted file mode 100644 index 27de5d2..0000000 --- a/sim/testsuite/sim/bfin/a6.s +++ /dev/null @@ -1,132 +0,0 @@ -// ALU test program. -// Test instructions -// r7 = +/+ (r0,r1); -// r7 = +/+ (r0,r1) s; -// r7 = +/+ (r0,r1) sx; -# mach: bfin - -.include "testutils.inc" - start - - -// one result overflows positive - R0.L = 0x0001; - R0.H = 0x0010; - R1.L = 0x7fff; - R1.H = 0x0010; - R7 = 0; - ASTAT = R7; - R7 = R0 +|+ R1; - DBGA ( R7.L , 0x8000 ); - DBGA ( R7.H , 0x0020 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - -// one result overflows negative - R0.L = 0xffff; - R0.H = 0x0010; - R1.L = 0x8000; - R1.H = 0x0010; - R7 = 0; - ASTAT = R7; - R7 = R0 +|+ R1; - DBGA ( R7.L , 0x7fff ); - DBGA ( R7.H , 0x0020 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// one result zero - R0.L = 0x0001; - R0.H = 0xffff; - R1.L = 0x0001; - R1.H = 0x0001; - R7 = 0; - ASTAT = R7; - R7 = R0 +|+ R1; - DBGA ( R7.L , 0x0002 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R5 = CC; DBGA ( R5.L , 0x1 ); - CC = AN; R5 = CC; DBGA ( R5.L , 0x0 ); - CC = V; R5 = CC; DBGA ( R5.L , 0x0 ); - CC = AC0; R5 = CC; DBGA ( R5.L , 0x0 ); - -// one result saturates positive - R0.L = 0x0001; - R0.H = 0x0010; - R1.L = 0x7fff; - R1.H = 0x0010; - R7 = 0; - ASTAT = R7; - R7 = R0 +|+ R1 (S); - DBGA ( R7.L , 0x7fff ); - DBGA ( R7.H , 0x0020 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - -// one result saturates negative - R0.L = 0xffff; - R0.H = 0x0010; - R1.L = 0x8000; - R1.H = 0x0010; - R7 = 0; - ASTAT = R7; - R7 = R0 +|+ R1 (S); - DBGA ( R7.L , 0x8000 ); - DBGA ( R7.H , 0x0020 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// two results saturates negative - R0.L = 0xffff; - R0.H = 0xfff0; - R1.L = 0x8000; - R1.H = 0x8000; - R7 = 0; - ASTAT = R7; - R7 = R0 +|+ R1 (S); - DBGA ( R7.L , 0x8000 ); - DBGA ( R7.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// one result overflows positive and cross - R0.L = 0x0001; - R0.H = 0x0010; - R1.L = 0x7fff; - R1.H = 0x0010; - R7 = 0; - ASTAT = R7; - R7 = R0 +|+ R1 (CO); - DBGA ( R7.L , 0x0020 ); - DBGA ( R7.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - -// one result saturates negative and cross - R0.L = 0xffff; - R0.H = 0x0010; - R1.L = 0x8000; - R1.H = 0x0010; - R7 = 0; - ASTAT = R7; - R7 = R0 +|+ R1 (SCO); - DBGA ( R7.L , 0x0020 ); - DBGA ( R7.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - - pass diff --git a/sim/testsuite/sim/bfin/a7.s b/sim/testsuite/sim/bfin/a7.s deleted file mode 100644 index 4fbc5f6..0000000 --- a/sim/testsuite/sim/bfin/a7.s +++ /dev/null @@ -1,179 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - R1 = 0; - R0 = 0; - R0 = R1 ^ R0; - -//_DBG ASTAT; -//R7 = ASTAT; -//DBGA ( R7.L , 1 ); - cc = az; - r7 = cc; - dbga( r7.l, 1); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - - R0 = R1 | R0; -//_DBG ASTAT; -//R7 = ASTAT; -//DBGA ( R7.L , 1 ); - cc = az; - r7 = cc; - dbga( r7.l, 1); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - - R0 = 0; - R1 = 1; - CC = R0 == R1; - -//_DBG ASTAT; -//R7 = ASTAT; -//DBGA ( R7.L , 2 ); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 1); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - - CC = BITTST ( R1 , 1 ); - -//_DBG ASTAT; -//R7 = ASTAT; -//DBGA ( R7.L , 2 ); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 1); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - - CC = ! BITTST( R1 , 1 ); -//_DBG ASTAT; -//R7 = ASTAT; -//DBGA ( R7.L , 0x22 ); - r7 = cc; - dbga( r7.l, 1); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 1); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - - R0.L = 0; - R0.H = 0x8000; - R0 >>>= 1; - _DBG ASTAT; -//R7 = ASTAT; -//DBGA ( R7.L , 0x22 ); - cc = az; - r6 = cc; - dbga( r6.l, 0); - cc = an; - r6 = cc; - dbga( r6.l, 1); - cc = av0; - r6 = cc; - dbga( r6.l, 0); - cc = av0s; - r6 = cc; - dbga( r6.l, 0); - cc = av1; - r6 = cc; - dbga( r6.l, 0); - cc = av1s; - r6 = cc; - dbga( r6.l, 0); - - R0.L = 17767; R0.H = 291; - R1.L = 52719; R1.H = -30293; - R2.L = 39612; R2.H = 22136; - R3.L = 4660; R3.H = -8464; - R4.L = 26777; R4.H = 9029; - R5.L = 9029; R5.H = 30865; - R6.L = 21554; R6.H = -26506; - R7.L = 22136; R7.H = 4660; - R0 = R0 + R0; - R1 = R0 - R1; - R2 = R0 & R2; - R3 = R0 | R3; - R4 = R0 & R4; - R5 = R0 & R5; - R6 = R0 | R6; - R7 = R0 & R7; - DBGA ( R0.l , 35534 ); DBGA( R0.h , 582 ); - DBGA( R1.l , 48351 ); DBGA ( R1.h , 30874 ); - DBGA ( R2.l , 35468 ); DBGA ( R2.h , 576 ); - DBGA ( R3.l , 39678 ); DBGA ( R3.h , 0xdef6); - DBGA ( R4.l , 2184 ); DBGA ( R4.h , 580 ); - DBGA ( R5.l , 580 ); DBGA( R5.h , 0 ); - DBGA ( R6.l, 57086 ); DBGA ( R6.h , 0x9a76 ); - DBGA ( R7.l , 584 ); DBGA ( R7.h , 516 ); - pass diff --git a/sim/testsuite/sim/bfin/a8.s b/sim/testsuite/sim/bfin/a8.s deleted file mode 100644 index 23f3464..0000000 --- a/sim/testsuite/sim/bfin/a8.s +++ /dev/null @@ -1,41 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - -// xh, h, xb, b - R0.L = 32898; R0.H = 1; - R1.L = 49346; R1.H = 3; - R2.L = 6; R2.H = -1; - R3.L = 129; R3.H = 7; - R4.L = 4; R4.H = 0; - R5.L = 5; R5.H = 0; - R6.L = 6; R6.H = 0; - R7.L = 7; R7.H = 0; - R4 = R0.L (X); - -// _DBG ASTAT; R7 = ASTAT;DBGA ( R7.L , 2 ); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 1); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - - R5 = R0.L; - R6 = R1.B (X); - R7 = R1.B; - DBGA ( R4.l , 32898 ); DBGA ( R4.h , 0xffff); - pass diff --git a/sim/testsuite/sim/bfin/a9.s b/sim/testsuite/sim/bfin/a9.s deleted file mode 100644 index 525b17f..0000000 --- a/sim/testsuite/sim/bfin/a9.s +++ /dev/null @@ -1,219 +0,0 @@ -// ALU test program. -// Test 32 bit MAX, MIN, ABS instructions -# mach: bfin - -.include "testutils.inc" - start - - -// MAX -// first operand is larger, so AN=0 - R0.L = 0x0001; - R0.H = 0x0000; - R1.L = 0x0000; - R1.H = 0x0000; - R7 = MAX ( R0 , R1 ); - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// second operand is larger, so AN=1 - R0.L = 0x0000; - R0.H = 0x0000; - R1.L = 0x0001; - R1.H = 0x0000; - R7 = MAX ( R0 , R1 ); - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// first operand is larger, check correct output with overflow - R0.L = 0xffff; - R0.H = 0x7fff; - R1.L = 0xffff; - R1.H = 0xffff; - R7 = MAX ( R0 , R1 ); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// second operand is larger, no overflow here - R0.L = 0xffff; - R0.H = 0xffff; - R1.L = 0xffff; - R1.H = 0x7fff; - R7 = MAX ( R0 , R1 ); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// second operand is larger, overflow - R0.L = 0xffff; - R0.H = 0x800f; - R1.L = 0xffff; - R1.H = 0x7fff; - R7 = MAX ( R0 , R1 ); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0S; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1S; R7 = CC; DBGA ( R7.L , 0x0 ); - -// both operands equal - R0.L = 0x0080; - R0.H = 0x8000; - R1.L = 0x0080; - R1.H = 0x8000; - R7 = MAX ( R0 , R1 ); - DBGA ( R7.L , 0x0080 ); - DBGA ( R7.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// MIN -// second operand is smaller - R0.L = 0x0001; - R0.H = 0x0000; - R1.L = 0x0000; - R1.H = 0x0000; - R7 = MIN ( R0 , R1 ); - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// first operand is smaller - R0.L = 0x0001; - R0.H = 0x8000; - R1.L = 0x0000; - R1.H = 0x0000; - R7 = MIN ( R0 , R1 ); - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// first operand is smaller, overflow - R0.L = 0x0001; - R0.H = 0x8000; - R1.L = 0x0000; - R1.H = 0x0ff0; - R7 = MIN ( R0 , R1 ); - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// equal operands - R0.L = 0x0001; - R0.H = 0x8000; - R1.L = 0x0001; - R1.H = 0x8000; - R7 = MIN ( R0 , R1 ); - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// ABS - R0.L = 0x0001; - R0.H = 0x8000; - R7 = ABS R0; - _DBG R7; - _DBG ASTAT; - R6 = ASTAT; - - _DBG R6; - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x7fff ); -//CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); -//CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); -//CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); -//CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); -//CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); -//CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0x0001; - R0.H = 0x0000; - R7 = ABS R0; - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0x0000; - R0.H = 0x8000; - R7 = ABS R0; - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0xffff; - R0.H = 0xffff; - R7 = ABS R0; - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0x0000; - R0.H = 0x0000; - R7 = ABS R0; - _DBG R7; - _DBG ASTAT; - R6 = ASTAT; - _DBG R6; - - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - CC = VS; R6 = CC; DBGA (R6.L, 0x1); - CC = AZ; R6 = CC; DBGA (R6.L, 0x1); - - pass diff --git a/sim/testsuite/sim/bfin/abs-2.S b/sim/testsuite/sim/bfin/abs-2.S deleted file mode 100644 index 1e768b0..0000000 --- a/sim/testsuite/sim/bfin/abs-2.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for ABS instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x8765; - R0.L = 0x4321; - R1 = ABS R0; - R7 = ASTAT; - R2.H = 0x789a; - R2.L = 0xbcdf; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AZ AN V V_COPY */ - R3.H = HI(_AZ|_AN|_V|_V_COPY); - R3.L = LO(_AZ|_AN|_V|_V_COPY); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: */ - R3.H = HI(0); - R3.L = LO(0); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/abs-3.S b/sim/testsuite/sim/bfin/abs-3.S deleted file mode 100644 index 44ba765..0000000 --- a/sim/testsuite/sim/bfin/abs-3.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for ABS instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x0; - R0.L = 0x0; - R1 = ABS R0; - R7 = ASTAT; - R2.H = 0x0; - R2.L = 0x0; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AN V V_COPY */ - R3.H = HI(_AN|_V|_V_COPY); - R3.L = LO(_AN|_V|_V_COPY); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: AZ */ - R3.H = HI(_AZ); - R3.L = LO(_AZ); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/abs-4.S b/sim/testsuite/sim/bfin/abs-4.S deleted file mode 100644 index 0e691e0..0000000 --- a/sim/testsuite/sim/bfin/abs-4.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for ABS instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x8000; - R0.L = 0x0; - R1 = ABS R0; - R7 = ASTAT; - R2.H = 0x7fff; - R2.L = 0xffff; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AZ AN V V_COPY */ - R3.H = HI(_AZ|_AN); - R3.L = LO(_AZ|_AN); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: V V_COPY VS */ - R3.H = HI(_V|_V_COPY|_VS); - R3.L = LO(_V|_V_COPY|_VS); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC0 AC0_COPY AC1 */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/abs.S b/sim/testsuite/sim/bfin/abs.S deleted file mode 100644 index 1425d42..0000000 --- a/sim/testsuite/sim/bfin/abs.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for ABS instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x1234; - R0.L = 0x5678; - R1 = ABS R0; - R7 = ASTAT; - R2.H = 0x1234; - R2.L = 0x5678; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AZ AN V V_COPY */ - R3.H = HI(_AZ|_AN|_V|_V_COPY); - R3.L = LO(_AZ|_AN|_V|_V_COPY); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: */ - R3.H = HI(0); - R3.L = LO(0); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/abs_acc.s b/sim/testsuite/sim/bfin/abs_acc.s deleted file mode 100644 index 99ed052..0000000 --- a/sim/testsuite/sim/bfin/abs_acc.s +++ /dev/null @@ -1,224 +0,0 @@ -// ACP 5.7 ABS(A1) sets AV0 -# mach: bfin - -.include "testutils.inc" - start - - r1=0x80 (z); - A0=0; - A0.x=r1; - A0=abs A0; - _DBG astat; -//r7=astat; -//dbga (r7.h, 0x3); -//dbga (r7.l, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 1); - cc = av0s; - r7 = cc; - dbga( r7.l, 1); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - - r6=A0.x; - dbga (r6.l, 0x7f); - - r1=0x80 (z); - A1=0; - A1.x=r1; - A1=abs A1; - _DBG astat; -//r7=astat; -//dbga (r7.h, 0xf); -//dbga (r7.l, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 1); - cc = av0s; - r7 = cc; - dbga( r7.l, 1); - cc = av1; - r7 = cc; - dbga( r7.l, 1); - cc = av1s; - r7 = cc; - dbga( r7.l, 1); - - r6=A1.x; - dbga (r6.l, 0x7f); - - r7=0; - astat=r7; - r1=0x80 (z); - A1=0; - A1.x=r1; - A0 = abs A1; - _DBG astat; -//r7=astat; -//dbga (r7.h, 0x3); -//dbga (r7.l, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 1); - cc = av0s; - r7 = cc; - dbga( r7.l, 1); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - - r6=A0.x; - dbga (r6.l, 0x7f); - - r7=0; - astat=r7; - r1=0x80 (z); - A0=0; - A0.x=r1; - A1 = abs A0; - _DBG astat; -//r7=astat; -//dbga (r7.h, 0xc); -//dbga (r7.l, 0x0); - cc = az; - r3 = cc; - dbga( r3.l, 0); - cc = an; - r3 = cc; - dbga( r3.l, 0); - cc = av0; - r3 = cc; - dbga( r3.l, 0); - cc = av0s; - r3 = cc; - dbga( r3.l, 0); - cc = av1; - r3 = cc; - dbga( r3.l, 1); - cc = av1s; - r3 = cc; - dbga( r3.l, 1); - - r6=A1.x; - dbga (r6.l, 0x7f); - - r7=0; - astat=r7; - r1=0x80 (z); - A1=0; - A1.x=r1; - A0.x=r6; - _DBG A1; - _DBG A0; - A1=abs A1, A0=abs A0; - _DBG ASTAT; -//r7=astat; -//dbga (r7.h, 0xc); -//dbga (r7.l, 0x0); - cc = az; - r4 = cc; - dbga( r4.l, 0); - cc = an; - r4 = cc; - dbga( r4.l, 0); - cc = av0; - r4 = cc; - dbga( r4.l, 0); - cc = av0s; - r4 = cc; - dbga( r4.l, 0); - cc = av1; - r4 = cc; - dbga( r4.l, 1); - cc = av1s; - r4 = cc; - dbga( r4.l, 1); - - r7=0; - astat=r7; - r1=0x80 (z); - A1=0; - A1.x=r1; - A0 = A1; - A1=abs A1, A0=abs A0; - _DBG ASTAT; -//r7=astat; -//dbga (r7.h, 0xf); -//dbga (r7.l, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 1); - cc = av0s; - r7 = cc; - dbga( r7.l, 1); - cc = av1; - r7 = cc; - dbga( r7.l, 1); - cc = av1s; - r7 = cc; - dbga( r7.l, 1); - -// ACP 5.8 ABS sometimes sets AN - - r7=0; - astat=r7; - r0=1; - r1=abs r0; - _DBG r0; - _DBG r1; - _DBG astat; -//r7=astat; -//dbga (r7.h, 0x0); -//dbga (r7.l, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - - pass; diff --git a/sim/testsuite/sim/bfin/acc-rot.s b/sim/testsuite/sim/bfin/acc-rot.s deleted file mode 100644 index ccf307c..0000000 --- a/sim/testsuite/sim/bfin/acc-rot.s +++ /dev/null @@ -1,129 +0,0 @@ -# Blackfin testcase for Accumulator Rotates (ROT) -# mach: bfin - - .include "testutils.inc" - - .macro atest_setup acc:req, val_x:req, val_w:req, cc:req, shift:req - imm32 R0, \val_w - imm32 R1, \val_x - R2 = \cc; - R3 = \shift - \acc\().W = R0; - \acc\().X = R1; - CC = R2; - .endm - - .macro atest_check acc:req, exp_x:req, exp_w:req, expcc:req - R7 = CC; - CHECKREG R7, \expcc; - - R2 = \acc\().W; - CHECKREG R2, \exp_w; - - R6 = \acc\().X; - R6 = R6.B (z); - CHECKREG R6, \exp_x; - .endm - - .macro _atest acc:req, val_x:req, val_w:req, cc:req, shift:req, exp_x:req, exp_w:req, expcc:req - atest_setup \acc, \val_x, \val_w, \cc, \shift - _DBG \acc; - \acc = ROT \acc BY \shift; - atest_check \acc, \exp_x, \exp_w, \expcc - - atest_setup \acc, \val_x, \val_w, \cc, \shift - \acc = ROT \acc BY R3.L; - atest_check \acc, \exp_x, \exp_w, \expcc - .endm - - .macro atest val_x:req, val_w:req, cc:req, shift:req, exp_x:req, exp_w:req, expcc:req - _atest A0, \val_x, \val_w, \cc, \shift, \exp_x, \exp_w, \expcc - _atest A1, \val_x, \val_w, \cc, \shift, \exp_x, \exp_w, \expcc - .endm - - start - - atest 0x00, 0x00000000, 0, 0, 0x00, 0x00000000, 0 - atest 0xa5, 0xa5a5a5a5, 0, 0, 0xa5, 0xa5a5a5a5, 0 - atest 0x00, 0x00000000, 1, 0, 0x00, 0x00000000, 1 - atest 0xa5, 0xa5a5a5a5, 1, 0, 0xa5, 0xa5a5a5a5, 1 - atest 0x00, 0x00000000, 0, 10, 0x00, 0x00000000, 0 - - atest 0x00, 0x0000000f, 0, 4, 0x00, 0x000000f0, 0 - atest 0x00, 0x0000000f, 1, 4, 0x00, 0x000000f8, 0 - atest 0x00, 0x0000000f, 0, 20, 0x00, 0x00f00000, 0 - atest 0x00, 0x0000000f, 1, 20, 0x00, 0x00f80000, 0 - atest 0x00, 0x0000000f, 0, -5, 0xf0, 0x00000000, 0 - atest 0x00, 0x0000000f, 1, -5, 0xf8, 0x00000000, 0 - atest 0x00, 0x0000000f, 0, -1, 0x00, 0x00000007, 1 - atest 0x00, 0x0000000f, 1, -1, 0x80, 0x00000007, 1 - - atest 0xff, 0xffffffff, 1, 10, 0xff, 0xffffffff, 1 - atest 0x11, 0x11111110, 0, -5, 0x00, 0x88888888, 1 - - atest 0x1f, 0x2e3d4c5b, 1, 0, 0x1f, 0x2e3d4c5b, 1 - atest 0x1f, 0x2e3d4c5b, 1, 1, 0x3e, 0x5c7a98b7, 0 - atest 0x1f, 0x2e3d4c5b, 1, 2, 0x7c, 0xb8f5316e, 0 - atest 0x1f, 0x2e3d4c5b, 1, 3, 0xf9, 0x71ea62dc, 0 - atest 0x1f, 0x2e3d4c5b, 1, 4, 0xf2, 0xe3d4c5b8, 1 - atest 0x1f, 0x2e3d4c5b, 1, 5, 0xe5, 0xc7a98b71, 1 - atest 0x1f, 0x2e3d4c5b, 1, 6, 0xcb, 0x8f5316e3, 1 - atest 0x1f, 0x2e3d4c5b, 1, 7, 0x97, 0x1ea62dc7, 1 - atest 0x1f, 0x2e3d4c5b, 1, 8, 0x2e, 0x3d4c5b8f, 1 - atest 0x1f, 0x2e3d4c5b, 1, 9, 0x5c, 0x7a98b71f, 0 - atest 0x1f, 0x2e3d4c5b, 1, 10, 0xb8, 0xf5316e3e, 0 - atest 0x1f, 0x2e3d4c5b, 1, 11, 0x71, 0xea62dc7c, 1 - atest 0x1f, 0x2e3d4c5b, 1, 12, 0xe3, 0xd4c5b8f9, 0 - atest 0x1f, 0x2e3d4c5b, 1, 13, 0xc7, 0xa98b71f2, 1 - atest 0x1f, 0x2e3d4c5b, 1, 14, 0x8f, 0x5316e3e5, 1 - atest 0x1f, 0x2e3d4c5b, 1, 15, 0x1e, 0xa62dc7cb, 1 - atest 0x1f, 0x2e3d4c5b, 1, 16, 0x3d, 0x4c5b8f97, 0 - atest 0x1f, 0x2e3d4c5b, 1, 17, 0x7a, 0x98b71f2e, 0 - atest 0x1f, 0x2e3d4c5b, 1, 18, 0xf5, 0x316e3e5c, 0 - atest 0x1f, 0x2e3d4c5b, 1, 19, 0xea, 0x62dc7cb8, 1 - atest 0x1f, 0x2e3d4c5b, 1, 20, 0xd4, 0xc5b8f971, 1 - atest 0x1f, 0x2e3d4c5b, 1, 21, 0xa9, 0x8b71f2e3, 1 - atest 0x1f, 0x2e3d4c5b, 1, 22, 0x53, 0x16e3e5c7, 1 - atest 0x1f, 0x2e3d4c5b, 1, 23, 0xa6, 0x2dc7cb8f, 0 - atest 0x1f, 0x2e3d4c5b, 1, 24, 0x4c, 0x5b8f971e, 1 - atest 0x1f, 0x2e3d4c5b, 1, 25, 0x98, 0xb71f2e3d, 0 - atest 0x1f, 0x2e3d4c5b, 1, 26, 0x31, 0x6e3e5c7a, 1 - atest 0x1f, 0x2e3d4c5b, 1, 27, 0x62, 0xdc7cb8f5, 0 - atest 0x1f, 0x2e3d4c5b, 1, 28, 0xc5, 0xb8f971ea, 0 - atest 0x1f, 0x2e3d4c5b, 1, 29, 0x8b, 0x71f2e3d4, 1 - atest 0x1f, 0x2e3d4c5b, 1, 30, 0x16, 0xe3e5c7a9, 1 - atest 0x1f, 0x2e3d4c5b, 1, 31, 0x2d, 0xc7cb8f53, 0 - atest 0x1f, 0x2e3d4c5b, 1, -1, 0x8f, 0x971ea62d, 1 - atest 0x1f, 0x2e3d4c5b, 1, -2, 0xc7, 0xcb8f5316, 1 - atest 0x1f, 0x2e3d4c5b, 1, -3, 0xe3, 0xe5c7a98b, 0 - atest 0x1f, 0x2e3d4c5b, 1, -4, 0x71, 0xf2e3d4c5, 1 - atest 0x1f, 0x2e3d4c5b, 1, -5, 0xb8, 0xf971ea62, 1 - atest 0x1f, 0x2e3d4c5b, 1, -6, 0xdc, 0x7cb8f531, 0 - atest 0x1f, 0x2e3d4c5b, 1, -7, 0x6e, 0x3e5c7a98, 1 - atest 0x1f, 0x2e3d4c5b, 1, -8, 0xb7, 0x1f2e3d4c, 0 - atest 0x1f, 0x2e3d4c5b, 1, -9, 0x5b, 0x8f971ea6, 0 - atest 0x1f, 0x2e3d4c5b, 1, -10, 0x2d, 0xc7cb8f53, 0 - atest 0x1f, 0x2e3d4c5b, 1, -11, 0x16, 0xe3e5c7a9, 1 - atest 0x1f, 0x2e3d4c5b, 1, -12, 0x8b, 0x71f2e3d4, 1 - atest 0x1f, 0x2e3d4c5b, 1, -13, 0xc5, 0xb8f971ea, 0 - atest 0x1f, 0x2e3d4c5b, 1, -14, 0x62, 0xdc7cb8f5, 0 - atest 0x1f, 0x2e3d4c5b, 1, -15, 0x31, 0x6e3e5c7a, 1 - atest 0x1f, 0x2e3d4c5b, 1, -16, 0x98, 0xb71f2e3d, 0 - atest 0x1f, 0x2e3d4c5b, 1, -17, 0x4c, 0x5b8f971e, 1 - atest 0x1f, 0x2e3d4c5b, 1, -18, 0xa6, 0x2dc7cb8f, 0 - atest 0x1f, 0x2e3d4c5b, 1, -19, 0x53, 0x16e3e5c7, 1 - atest 0x1f, 0x2e3d4c5b, 1, -20, 0xa9, 0x8b71f2e3, 1 - atest 0x1f, 0x2e3d4c5b, 1, -21, 0xd4, 0xc5b8f971, 1 - atest 0x1f, 0x2e3d4c5b, 1, -22, 0xea, 0x62dc7cb8, 1 - atest 0x1f, 0x2e3d4c5b, 1, -23, 0xf5, 0x316e3e5c, 0 - atest 0x1f, 0x2e3d4c5b, 1, -24, 0x7a, 0x98b71f2e, 0 - atest 0x1f, 0x2e3d4c5b, 1, -25, 0x3d, 0x4c5b8f97, 0 - atest 0x1f, 0x2e3d4c5b, 1, -26, 0x1e, 0xa62dc7cb, 1 - atest 0x1f, 0x2e3d4c5b, 1, -27, 0x8f, 0x5316e3e5, 1 - atest 0x1f, 0x2e3d4c5b, 1, -28, 0xc7, 0xa98b71f2, 1 - atest 0x1f, 0x2e3d4c5b, 1, -29, 0xe3, 0xd4c5b8f9, 0 - atest 0x1f, 0x2e3d4c5b, 1, -30, 0x71, 0xea62dc7c, 1 - atest 0x1f, 0x2e3d4c5b, 1, -31, 0xb8, 0xf5316e3e, 0 - atest 0x1f, 0x2e3d4c5b, 1, -32, 0x5c, 0x7a98b71f, 0 - - pass diff --git a/sim/testsuite/sim/bfin/acp5_19.s b/sim/testsuite/sim/bfin/acp5_19.s deleted file mode 100644 index 74e7552..0000000 --- a/sim/testsuite/sim/bfin/acp5_19.s +++ /dev/null @@ -1,12 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - r0.h=0xa5a5; - r0.l=0xffff; - a0 = 0; - r0=a0.x; - dbga(r0.h, 0x0000); - dbga(r0.l, 0x0000); - pass; diff --git a/sim/testsuite/sim/bfin/acp5_4.s b/sim/testsuite/sim/bfin/acp5_4.s deleted file mode 100644 index 993f7ba..0000000 --- a/sim/testsuite/sim/bfin/acp5_4.s +++ /dev/null @@ -1,39 +0,0 @@ -// test RND setting AZ -# mach: bfin - -.include "testutils.inc" - start - - -// result is zero with overflow ==> AZ, therefore, is not set - R0.L = 0x8000; - R0 = R0.L (X); - R1.L = R0 (RND); - CC = AZ; R7 = CC; - DBGA(R1.L, 0); - DBGA ( R7.L , 0x1 ); - -// No Overflow, result is zero, AZ is set - R0 = 1 (X); - R1.L = r0 (RND); - CC = AZ; R7 = CC; - DBGA(R1.L, 0); - DBGA ( R7.L , 0x1 ); - -// result should be 1 - R0.L = 0x8000; - R0.H = 0; - R1.L = R0 (RND); - CC = AZ; R7 = CC; - DBGA(R1.L, 1); - DBGA ( R7.L , 0x0 ); - -// Result should be non-zero - R0.H = 0x7ff0; - R0.L = 0x8000; - R1.L = R0 (RND); - CC = AZ; R7 = CC; - DBGA(R1.L, 0x7ff1); - DBGA ( R7.L , 0x0 ); - - pass diff --git a/sim/testsuite/sim/bfin/add_imm7.s b/sim/testsuite/sim/bfin/add_imm7.s deleted file mode 100644 index 31f1538..0000000 --- a/sim/testsuite/sim/bfin/add_imm7.s +++ /dev/null @@ -1,38 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - r0 = 0 - ASTAT = r0; - - r2=-7; - r2+=-63; - _dbg r2; - _dbg astat; - r7=astat; - dbga ( r7.h, 0x0); - dbga ( r7.l, 0x1006); - - r7=0; - astat=r7; - r2=64; - r2+=-64; - _dbg r2; - _dbg astat; - r7=astat; - dbga ( r7.h, 0x0); - dbga ( r7.l, 0x1005); - - r7=0; - astat=r7; - r2=0; - r2.h=0x8000; - r2+=-63; - _dbg astat; - _dbg r2; - r7=astat; - dbga ( r7.h, 0x0300); - dbga ( r7.l, 0x100c); - - pass diff --git a/sim/testsuite/sim/bfin/add_shift.S b/sim/testsuite/sim/bfin/add_shift.S deleted file mode 100644 index 8a8bf63..0000000 --- a/sim/testsuite/sim/bfin/add_shift.S +++ /dev/null @@ -1,53 +0,0 @@ -// ACP 5.6 Flags for dreg=(dreg+dreg)<<1,2 -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - - r1=0; - ASTAT = R1; - r2=0; - r2.h=0x4000; - r2=(r2+r1)<<2; - dbga (r2.l,0x0); - dbga (r2.h,0x0); - _dbg ASTAT; - r7=ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY|_AZ) - - r2=0; - r2.h=0x4000; - r2=(r2+r1)<<1; - dbga (r2.l,0x0); - dbga (r2.h,0x8000); - _dbg ASTAT; - r7=ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY|_AN) - - r1=0; - r1.h=0xd300; - r2=0; - r2.h=0xb700; - r2=(r2+r1)<<1; - dbga (r2.l,0x0); - dbga (r2.h,0x1400); - _dbg ASTAT; - r7=ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY) - - r0 = 1; - r0 <<= 31; // r0 should be 0x80000000 - r7 = 0; - ASTAT = r7; - _dbg r0; - r1 = r0; - _dbg r1; - r1 = (r1 + r0) << 1; // add overflows to zero, no shift overflow - _dbg r1; - _dbg ASTAT; - r7 = ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY|_AZ); - - pass diff --git a/sim/testsuite/sim/bfin/add_sub_acc.s b/sim/testsuite/sim/bfin/add_sub_acc.s deleted file mode 100644 index 84416d0..0000000 --- a/sim/testsuite/sim/bfin/add_sub_acc.s +++ /dev/null @@ -1,123 +0,0 @@ -// ACP 5.9 A0 -= A1 doesn't set flags -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - R0 = 0x0; - astat=r0; - A0.w = R0; - R0.L = 0x0080; - A0.x = R0; - R1 = 1; - - _DBG A0; - _DBG A1; - - A0 -= A1; - _dbg A0; - _dbg ASTAT; - r7=astat; - dbga (r7.h, 0x0); - dbga (r7.l, 0x1006); - - A1 = A0 = 0; - R0 = 0x1 (z); - astat=r0; - A0.w = R0; - R0.L = 0x0080; - A0.x = R0; - R1 = 1; - - _DBG A0; - _DBG A1; - - A0 -= A1; - _dbg A0; - _dbg ASTAT; - r7=astat; - dbga (r7.h, 0x0); - dbga (r7.l, 0x1006); - - A1 = A0 = 0; - R0 = 0x0; - astat=r0; - A0.w = R0; - R0.L = 0x0080; - A0.x = R0; - R1 = 1; - A1 = R1; - - _DBG A0; - _DBG A1; - - A0 -= A1; - _dbg A0; - _dbg ASTAT; - r7=astat; - dbga (r7.h, 0x3); - dbga (r7.l, 0x1006); - - A1 = A0 = 0; - R0 = 0x1 (z); - astat=r0; - A0.w = R0; - R0.L = 0x0080; - A0.x = R0; - R1 = 2 (z); - A1 = R1; - - _DBG A0; - _DBG A1; - - A0 -= A1; - _dbg A0; - _dbg ASTAT; - r7=astat; - dbga (r7.h, 0x3); - dbga (r7.l, 0x1006); - - # - - A1 = A0 = 0; - R0 = 0x0; - astat=r0; - R0.L=0xffff; - R0.H=0xffff; - A0.w = R0; - R1=0x7f; - A0.x = R1; - A1.x = R1; - A1.w = R0; - - _DBG A0; - _DBG A1; - - A0 += A1; - _dbg A0; - _dbg ASTAT; - r7=astat; - dbga (r7.h, 0x3); - dbga (r7.l, 0x0); - - A1 = A0 = 0; - R0 = 0x0; - astat=r0; - A0.w = R0; - R1=0x80; - A0.x = R1; - A1.x = R1; - A1.w = R0; - - _DBG A0; - _DBG A1; - - A0 += A1; - _dbg A0; - _dbg ASTAT; - r7=astat; - dbga (r7.h, 0x3); - dbga (r7.l, 0x1006); - - pass; diff --git a/sim/testsuite/sim/bfin/addsub_flags.S b/sim/testsuite/sim/bfin/addsub_flags.S deleted file mode 100644 index 78319c5..0000000 --- a/sim/testsuite/sim/bfin/addsub_flags.S +++ /dev/null @@ -1,107 +0,0 @@ -// ACP 5.17 Dual ALU ops -// AZ, AN, AC0, AC1, V and VS are affected -// AV0, AV0S, AV1, AV1S are unaffected -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - A0 = A1 = 0; - - r0=0; - r0.h=0x7fff; - r2=0; - r2.h=0x7000; - r1=r0+r2,r3=r0-r2; - r7=astat; - _dbg r1; - _dbg r3; - _dbg astat; - CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); - - a1=r2; - a0=r0; - r1=a0+a1, r3=a0-a1; - r7=astat; - _dbg a0; - _dbg a1; - _dbg r1; - _dbg r3; - _dbg astat; - CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); - - a0=r2; - a1=r0; - r1=a1+a0, r3=a1-a0; - r7=astat; - _dbg a0; - _dbg a1; - _dbg r1; - _dbg r3; - _dbg astat; - CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); - - r0.h=0xafff; - r2.h=0xa000; - a1=r2; - a0=r0; - r1=a0+a1, r3=a0-a1; - r7=astat; - _dbg a0; - _dbg a1; - _dbg r1; - _dbg r3; - _dbg astat; - CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); - - r1=a0+a1, r3=a0-a1 (s); - r7=astat; - _dbg a0; - _dbg a1; - _dbg r1; - _dbg r3; - _dbg astat; - CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1|_AN); - - r0.h=0xafff; - r2.h=0xa000; - a0=r2; - a1=r0; - r1=a1+a0, r3=a1-a0; - r7=astat; - _dbg a0; - _dbg a1; - _dbg r1; - _dbg r3; - _dbg astat; - CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); - - r1=a1+a0, r3=a1-a0 (s); - r7=astat; - _dbg a0; - _dbg a1; - _dbg r1; - _dbg r3; - _dbg astat; - CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1|_AN); - - r2.h=0x8001; - r1=r0+r2,r3=r0-r2; - _dbg r1; - _dbg r3; - _dbg astat; - r7=astat; - CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); - - r2.h=0x8000; - r1=r0+r2,r3=r0-r2; - r7=astat; - _dbg r1; - _dbg r3; - _dbg astat; - CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); - - pass; diff --git a/sim/testsuite/sim/bfin/algnbug1.s b/sim/testsuite/sim/bfin/algnbug1.s deleted file mode 100644 index be0363b..0000000 --- a/sim/testsuite/sim/bfin/algnbug1.s +++ /dev/null @@ -1,38 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - loadsym P0, blocka; - I0 = P0; - - DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; - DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; - - DBGA ( R0.L , 0xfeff ); - DBGA ( R0.H , 0xfcfd ); - DBGA ( R1.L , 0xfafb ); - DBGA ( R1.H , 0xf8f9 ); - - I0 = P0; - M0 = 1 (X); - I0 += M0; - - DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; - DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; - - DBGA ( R0.L , 0xfeff ); - DBGA ( R0.H , 0xfcfd ); - DBGA ( R1.L , 0xfafb ); - DBGA ( R1.H , 0xf8f9 ); - - pass - - .data - .align 8 -blocka: - .dw 0xfeff - .dw 0xfcfd - .dw 0xfafb - .dw 0xf8f9 diff --git a/sim/testsuite/sim/bfin/algnbug2.s b/sim/testsuite/sim/bfin/algnbug2.s deleted file mode 100644 index b06d5ad..0000000 --- a/sim/testsuite/sim/bfin/algnbug2.s +++ /dev/null @@ -1,69 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - M0 = 1 (X); - loadsym I0, blocka; - - DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; - DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; - - DBGA ( R0.L , 0xfeff ); - DBGA ( R0.H , 0xfcfd ); - DBGA ( R1.L , 0xfafb ); - DBGA ( R1.H , 0xf8f9 ); - - loadsym I0, blocka; - I0 += M0; - - DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; - DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; - - DBGA ( R0.L , 0xfeff ); - DBGA ( R0.H , 0xfcfd ); - DBGA ( R1.L , 0xfafb ); - DBGA ( R1.H , 0xf8f9 ); - - loadsym I0, blocka; - I0 += M0; - - DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; - DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; - - DBGA ( R0.L , 0xfeff ); - DBGA ( R0.H , 0xfcfd ); - DBGA ( R1.L , 0xfafb ); - DBGA ( R1.H , 0xf8f9 ); - - loadsym I0, blocka; - I0 += M0; - - DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; - DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; - - DBGA ( R0.L , 0xfeff ); - DBGA ( R0.H , 0xfcfd ); - DBGA ( R1.L , 0xfafb ); - DBGA ( R1.H , 0xf8f9 ); - - loadsym I0, blocka; - I0 += M0; - - DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; - DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; - - DBGA ( R0.H , 0xfcfd ); - DBGA ( R1.L , 0xfafb ); - DBGA ( R1.H , 0xf8f9 ); - - pass - - .data; - .align 8 -blocka: - .dw 0xfeff - .dw 0xfcfd - .dw 0xfafb - .dw 0xf8f9 diff --git a/sim/testsuite/sim/bfin/allinsn.exp b/sim/testsuite/sim/bfin/allinsn.exp deleted file mode 100644 index aa304ea..0000000 --- a/sim/testsuite/sim/bfin/allinsn.exp +++ /dev/null @@ -1,43 +0,0 @@ -# Analog Devices Blackfin simulator testsuite - -if [istarget bfin-*-elf] { - # all machines - set all_machs "bfin" - - # See if we have a preprocessor available. - if { [target_compile $srcdir/$subdir/usp.S compilercheck.x "preprocess" \ - [list "incdir=$srcdir/$subdir"]] == "" } { - set has_cpp 1 - } { - verbose -log "Can't execute preprocessor" - set has_cpp 0 - } - - # See if we have a compiler available. - if { [target_compile $srcdir/$subdir/argc.c compilercheck.x "executable" \ - [list "incdir=$srcdir/$subdir" "additional_flags=-msim"]] == "" } { - set has_cc 1 - } { - verbose -log "Can't execute C compiler" - set has_cc 0 - } - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.\[csS\]]] { - # If we don't have a compiler available, skip tests :(. - if { $has_cpp == 0 && [string match "*.S" $src] } { - untested $src - continue - } - if { $has_cc == 0 && [string match "*.c" $src] } { - untested $src - continue - } - - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/bfin/argc.c b/sim/testsuite/sim/bfin/argc.c deleted file mode 100644 index 21f1fef..0000000 --- a/sim/testsuite/sim/bfin/argc.c +++ /dev/null @@ -1,31 +0,0 @@ -/* Basic argc/argv tests. -# mach: bfin -# cc: -msim -# progopts: a bb ccc dddd -*/ - -int streq(const char *s1, const char *s2) -{ - int i = 0; - - while (s1[i] && s2[i] && s1[i] == s2[i]) - ++i; - - return s1[i] == '\0' && s2[i] == '\0'; -} - -int main(int argc, char *argv[]) -{ - if (argc != 5) - return 1; - if (!streq(argv[1], "a")) - return 2; - if (!streq(argv[2], "bb")) - return 2; - if (!streq(argv[3], "ccc")) - return 2; - if (!streq(argv[4], "dddd")) - return 2; - puts("pass"); - return 0; -} diff --git a/sim/testsuite/sim/bfin/ashift.s b/sim/testsuite/sim/bfin/ashift.s deleted file mode 100644 index de0b36e..0000000 --- a/sim/testsuite/sim/bfin/ashift.s +++ /dev/null @@ -1,323 +0,0 @@ -# Blackfin testcase for ashift -# mach: bfin - - .include "testutils.inc" - - .macro ashift_test in:req, shift:req, out:req, opt - r0 = \in (Z); - r2.L = \shift; - r2.h = ASHIFT R0.L BY R2.L \opt; - DBGA (r2.h, \out); - .endm - - start - - /* - * 16-bit ashift and lshift uses a 6-bit signed magnitude, which - * gives a range from -32 to 31. In the case where the magnitude - * is -32, make sure the answer is correct. - */ - -ashift_test 0x8001, 33, 0xffff; -ashift_test 0x8001, 32, 0xffff; -ashift_test 0x8001, 31, 0x0000; -ashift_test 0x8001, 30, 0x0000; -ashift_test 0x8001, 29, 0x0000; -ashift_test 0x8001, 28, 0x0000; -ashift_test 0x8001, 27, 0x0000; -ashift_test 0x8001, 26, 0x0000; -ashift_test 0x8001, 25, 0x0000; -ashift_test 0x8001, 24, 0x0000; -ashift_test 0x8001, 23, 0x0000; -ashift_test 0x8001, 22, 0x0000; -ashift_test 0x8001, 21, 0x0000; -ashift_test 0x8001, 20, 0x0000; -ashift_test 0x8001, 19, 0x0000; -ashift_test 0x8001, 18, 0x0000; -ashift_test 0x8001, 17, 0x0000; -ashift_test 0x8001, 16, 0x0000; -ashift_test 0x8001, 15, 0x8000; -ashift_test 0x8001, 14, 0x4000; -ashift_test 0x8001, 13, 0x2000; -ashift_test 0x8001, 12, 0x1000; -ashift_test 0x8001, 11, 0x0800; -ashift_test 0x8001, 10, 0x0400; -ashift_test 0x8001, 9, 0x0200; -ashift_test 0x8001, 8, 0x0100; -ashift_test 0x8001, 7, 0x0080; -ashift_test 0x8001, 6, 0x0040; -ashift_test 0x8001, 5, 0x0020; -ashift_test 0x8001, 4, 0x0010; -ashift_test 0x8001, 3, 0x0008; -ashift_test 0x8001, 2, 0x0004; -ashift_test 0x8001, 1, 0x0002; -ashift_test 0x8001, 0, 0x8001; -ashift_test 0x8001, -1, 0xc000; -ashift_test 0x8001, -2, 0xe000; -ashift_test 0x8001, -3, 0xf000; -ashift_test 0x8001, -4, 0xf800; -ashift_test 0x8001, -5, 0xfc00; -ashift_test 0x8001, -6, 0xfe00; -ashift_test 0x8001, -7, 0xff00; -ashift_test 0x8001, -8, 0xff80; -ashift_test 0x8001, -9, 0xffc0; -ashift_test 0x8001, -10, 0xffe0; -ashift_test 0x8001, -11, 0xfff0; -ashift_test 0x8001, -12, 0xfff8; -ashift_test 0x8001, -13, 0xfffc; -ashift_test 0x8001, -14, 0xfffe; -ashift_test 0x8001, -15, 0xffff; -ashift_test 0x8001, -16, 0xffff; -ashift_test 0x8001, -17, 0xffff; -ashift_test 0x8001, -18, 0xffff; -ashift_test 0x8001, -19, 0xffff; -ashift_test 0x8001, -20, 0xffff; -ashift_test 0x8001, -21, 0xffff; -ashift_test 0x8001, -22, 0xffff; -ashift_test 0x8001, -23, 0xffff; -ashift_test 0x8001, -24, 0xffff; -ashift_test 0x8001, -25, 0xffff; -ashift_test 0x8001, -26, 0xffff; -ashift_test 0x8001, -27, 0xffff; -ashift_test 0x8001, -28, 0xffff; -ashift_test 0x8001, -29, 0xffff; -ashift_test 0x8001, -30, 0xffff; -ashift_test 0x8001, -31, 0xffff; -ashift_test 0x8001, -32, 0xffff; -ashift_test 0x8001, -33, 0x0; -ashift_test 0x8001, -34, 0x0; - -ashift_test 0x8001, 33, 0xffff, (S); -ashift_test 0x8001, 32, 0xffff, (S); -ashift_test 0x8001, 31, 0x8000, (S); -ashift_test 0x8001, 30, 0x8000, (S); -ashift_test 0x8001, 29, 0x8000, (S); -ashift_test 0x8001, 28, 0x8000, (S); -ashift_test 0x8001, 27, 0x8000, (S); -ashift_test 0x8001, 26, 0x8000, (S); -ashift_test 0x8001, 25, 0x8000, (S); -ashift_test 0x8001, 24, 0x8000, (S); -ashift_test 0x8001, 23, 0x8000, (S); -ashift_test 0x8001, 22, 0x8000, (S); -ashift_test 0x8001, 21, 0x8000, (S); -ashift_test 0x8001, 20, 0x8000, (S); -ashift_test 0x8001, 19, 0x8000, (S); -ashift_test 0x8001, 18, 0x8000, (S); -ashift_test 0x8001, 17, 0x8000, (S); -ashift_test 0x8001, 16, 0x8000, (S); -ashift_test 0x8001, 15, 0x8000, (S); -ashift_test 0x8001, 14, 0x8000, (S); -ashift_test 0x8001, 13, 0x8000, (S); -ashift_test 0x8001, 12, 0x8000, (S); -ashift_test 0x8001, 11, 0x8000, (S); -ashift_test 0x8001, 10, 0x8000, (S); -ashift_test 0x8001, 9, 0x8000, (S); -ashift_test 0x8001, 8, 0x8000, (S); -ashift_test 0x8001, 7, 0x8000, (S); -ashift_test 0x8001, 6, 0x8000, (S); -ashift_test 0x8001, 5, 0x8000, (S); -ashift_test 0x8001, 4, 0x8000, (S); -ashift_test 0x8001, 3, 0x8000, (S); -ashift_test 0x8001, 2, 0x8000, (S); -ashift_test 0x8001, 1, 0x8000, (S); -ashift_test 0x8001, 0, 0x8001, (S); -ashift_test 0x8001, -1, 0xc000, (S); -ashift_test 0x8001, -2, 0xe000, (S); -ashift_test 0x8001, -3, 0xf000, (S); -ashift_test 0x8001, -4, 0xf800, (S); -ashift_test 0x8001, -5, 0xfc00, (S); -ashift_test 0x8001, -6, 0xfe00, (S); -ashift_test 0x8001, -7, 0xff00, (S); -ashift_test 0x8001, -8, 0xff80, (S); -ashift_test 0x8001, -9, 0xffc0, (S); -ashift_test 0x8001, -10, 0xffe0, (S); -ashift_test 0x8001, -11, 0xfff0, (S); -ashift_test 0x8001, -12, 0xfff8, (S); -ashift_test 0x8001, -13, 0xfffc, (S); -ashift_test 0x8001, -14, 0xfffe, (S); -ashift_test 0x8001, -15, 0xffff, (S); -ashift_test 0x8001, -16, 0xffff, (S); -ashift_test 0x8001, -17, 0xffff, (S); -ashift_test 0x8001, -18, 0xffff, (S); -ashift_test 0x8001, -19, 0xffff, (S); -ashift_test 0x8001, -20, 0xffff, (S); -ashift_test 0x8001, -21, 0xffff, (S); -ashift_test 0x8001, -22, 0xffff, (S); -ashift_test 0x8001, -23, 0xffff, (S); -ashift_test 0x8001, -24, 0xffff, (S); -ashift_test 0x8001, -25, 0xffff, (S); -ashift_test 0x8001, -26, 0xffff, (S); -ashift_test 0x8001, -27, 0xffff, (S); -ashift_test 0x8001, -28, 0xffff, (S); -ashift_test 0x8001, -29, 0xffff, (S); -ashift_test 0x8001, -30, 0xffff, (S); -ashift_test 0x8001, -31, 0xffff, (S); -ashift_test 0x8001, -32, 0xffff, (S); -ashift_test 0x8001, -33, 0x8000, (S); -ashift_test 0x8001, -34, 0x8000, (S); - - -ashift_test 0x4002, 33, 0x0; -ashift_test 0x4002, 32, 0x0; -ashift_test 0x4002, 31, 0x0; -ashift_test 0x4002, 30, 0x0; -ashift_test 0x4002, 20, 0x0; -ashift_test 0x4002, 19, 0x0; -ashift_test 0x4002, 18, 0x0; -ashift_test 0x4002, 17, 0x0; -ashift_test 0x4002, 16, 0x0; -ashift_test 0x4002, 15, 0x0; -ashift_test 0x4002, 14, 0x8000; -ashift_test 0x4002, 13, 0x4000; -ashift_test 0x4002, 12, 0x2000; -ashift_test 0x4002, 11, 0x1000; -ashift_test 0x4002, 10, 0x0800; -ashift_test 0x4002, 9, 0x0400; -ashift_test 0x4002, 8, 0x0200; -ashift_test 0x4002, 7, 0x0100; -ashift_test 0x4002, 6, 0x0080; -ashift_test 0x4002, 5, 0x0040; -ashift_test 0x4002, 4, 0x0020; -ashift_test 0x4002, 3, 0x0010; -ashift_test 0x4002, 2, 0x0008; -ashift_test 0x4002, 1, 0x8004; -ashift_test 0x4002, 0, 0x4002; -ashift_test 0x4002, -1, 0x2001; -ashift_test 0x4002, -2, 0x1000; -ashift_test 0x4002, -3, 0x0800; -ashift_test 0x4002, -4, 0x0400; -ashift_test 0x4002, -5, 0x0200; -ashift_test 0x4002, -6, 0x0100; -ashift_test 0x4002, -7, 0x0080; -ashift_test 0x4002, -8, 0x0040; -ashift_test 0x4002, -9, 0x0020; -ashift_test 0x4002, -10, 0x0010; -ashift_test 0x4002, -11, 0x0008; -ashift_test 0x4002, -12, 0x0004; -ashift_test 0x4002, -13, 0x0002; -ashift_test 0x4002, -14, 0x0001; -ashift_test 0x4002, -15, 0x0; -ashift_test 0x4002, -16, 0x0; -ashift_test 0x4002, -17, 0x0; -ashift_test 0x4002, -31, 0x0; -ashift_test 0x4002, -32, 0x0; -ashift_test 0x4002, -33, 0x0; -ashift_test 0x4002, -34, 0x0; - -ashift_test 0x4002, 33, 0x0, (S); -ashift_test 0x4002, 32, 0x0, (S); -ashift_test 0x4002, 31, 0x7fff, (S); -ashift_test 0x4002, 30, 0x7fff, (S); -ashift_test 0x4002, 20, 0x7fff, (S); -ashift_test 0x4002, 19, 0x7fff, (S); -ashift_test 0x4002, 18, 0x7fff, (S); -ashift_test 0x4002, 17, 0x7fff, (S); -ashift_test 0x4002, 16, 0x7fff, (S); -ashift_test 0x4002, 15, 0x7fff, (S); -ashift_test 0x4002, 14, 0x7fff, (S); -ashift_test 0x4002, 13, 0x7fff, (S); -ashift_test 0x4002, 12, 0x7fff, (S); -ashift_test 0x4002, 11, 0x7fff, (S); -ashift_test 0x4002, 10, 0x7fff, (S); -ashift_test 0x4002, 9, 0x7fff, (S); -ashift_test 0x4002, 8, 0x7fff, (S); -ashift_test 0x4002, 7, 0x7fff, (S); -ashift_test 0x4002, 6, 0x7fff, (S); -ashift_test 0x4002, 5, 0x7fff, (S); -ashift_test 0x4002, 4, 0x7fff, (S); -ashift_test 0x4002, 3, 0x7fff, (S); -ashift_test 0x4002, 2, 0x7fff, (S); -ashift_test 0x4002, 1, 0x7fff, (S); -ashift_test 0x4002, 0, 0x4002, (S); -ashift_test 0x4002, -1, 0x2001, (S); -ashift_test 0x4002, -2, 0x1000, (S); -ashift_test 0x4002, -3, 0x0800, (S); -ashift_test 0x4002, -4, 0x0400, (S); -ashift_test 0x4002, -5, 0x0200, (S); -ashift_test 0x4002, -6, 0x0100, (S); -ashift_test 0x4002, -7, 0x0080, (S); -ashift_test 0x4002, -8, 0x0040, (S); -ashift_test 0x4002, -9, 0x0020, (S); -ashift_test 0x4002, -10, 0x0010, (S); -ashift_test 0x4002, -11, 0x0008, (S); -ashift_test 0x4002, -12, 0x0004, (S); -ashift_test 0x4002, -13, 0x0002, (S); -ashift_test 0x4002, -14, 0x0001, (S); -ashift_test 0x4002, -15, 0x0000, (S); -ashift_test 0x4002, -16, 0x0000, (S); -ashift_test 0x4002, -17, 0x0000, (S); -ashift_test 0x4002, -31, 0x0000, (S); -ashift_test 0x4002, -32, 0x0000, (S); -ashift_test 0x4002, -33, 0x7fff, (S); -ashift_test 0x4002, -34, 0x7fff, (S); - -ashift_test 0x0001, 33, 0x0000, (S); -ashift_test 0x0001, 32, 0x0000, (S); -ashift_test 0x0001, 31, 0x7fff, (S); -ashift_test 0x0001, 30, 0x7fff, (S); -ashift_test 0x0001, 29, 0x7fff, (S); -ashift_test 0x0001, 28, 0x7fff, (S); -ashift_test 0x0001, 27, 0x7fff, (S); -ashift_test 0x0001, 26, 0x7fff, (S); -ashift_test 0x0001, 25, 0x7fff, (S); -ashift_test 0x0001, 24, 0x7fff, (S); -ashift_test 0x0001, 23, 0x7fff, (S); -ashift_test 0x0001, 22, 0x7fff, (S); -ashift_test 0x0001, 21, 0x7fff, (S); -ashift_test 0x0001, 20, 0x7fff, (S); -ashift_test 0x0001, 19, 0x7fff, (S); -ashift_test 0x0001, 18, 0x7fff, (S); -ashift_test 0x0001, 17, 0x7fff, (S); -ashift_test 0x0001, 16, 0x7fff, (S); -ashift_test 0x0001, 15, 0x7fff, (S); -ashift_test 0x0001, 14, 0x4000, (S); -ashift_test 0x0001, 13, 0x2000, (S); -ashift_test 0x0001, 12, 0x1000, (S); -ashift_test 0x0001, 11, 0x0800, (S); -ashift_test 0x0001, 10, 0x0400, (S); -ashift_test 0x0001, 9, 0x0200, (S); -ashift_test 0x0001, 8, 0x0100, (S); -ashift_test 0x0001, 7, 0x0080, (S); -ashift_test 0x0001, 6, 0x0040, (S); -ashift_test 0x0001, 5, 0x0020, (S); -ashift_test 0x0001, 4, 0x0010, (S); -ashift_test 0x0001, 3, 0x0008, (S); -ashift_test 0x0001, 2, 0x0004, (S); -ashift_test 0x0001, 1, 0x0002, (S); -ashift_test 0x0001, 0, 0x0001, (S); -ashift_test 0x0001, -1, 0x0000, (S); -ashift_test 0x0001, -2, 0x0000, (S); -ashift_test 0x0001, -3, 0x0000, (S); -ashift_test 0x0001, -4, 0x0000, (S); -ashift_test 0x0001, -5, 0x0000, (S); -ashift_test 0x0001, -6, 0x0000, (S); -ashift_test 0x0001, -7, 0x0000, (S); -ashift_test 0x0001, -8, 0x0000, (S); -ashift_test 0x0001, -9, 0x0000, (S); -ashift_test 0x0001, -10, 0x0000, (S); -ashift_test 0x0001, -11, 0x0000, (S); -ashift_test 0x0001, -12, 0x0000, (S); -ashift_test 0x0001, -13, 0x0000, (S); -ashift_test 0x0001, -14, 0x0, (S); -ashift_test 0x0001, -15, 0x0, (S); -ashift_test 0x0001, -16, 0x0, (S); -ashift_test 0x0001, -17, 0x0, (S); -ashift_test 0x0001, -18, 0x0, (S); -ashift_test 0x0001, -19, 0x0, (S); -ashift_test 0x0001, -20, 0x0, (S); -ashift_test 0x0001, -21, 0x0, (S); -ashift_test 0x0001, -22, 0x0, (S); -ashift_test 0x0001, -23, 0x0, (S); -ashift_test 0x0001, -24, 0x0, (S); -ashift_test 0x0001, -25, 0x0, (S); -ashift_test 0x0001, -26, 0x0, (S); -ashift_test 0x0001, -27, 0x0, (S); -ashift_test 0x0001, -28, 0x0, (S); -ashift_test 0x0001, -29, 0x0, (S); -ashift_test 0x0001, -30, 0x0, (S); -ashift_test 0x0001, -31, 0x0, (S); -ashift_test 0x0001, -32, 0x0, (S); -ashift_test 0x0001, -33, 0x7fff, (S); -ashift_test 0x0001, -34, 0x7fff, (S); - - pass diff --git a/sim/testsuite/sim/bfin/ashift_flags.s b/sim/testsuite/sim/bfin/ashift_flags.s deleted file mode 100644 index 87f00be..0000000 --- a/sim/testsuite/sim/bfin/ashift_flags.s +++ /dev/null @@ -1,84 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - -// load r1=0x7fffffff -// load r2=0x80000000 -// load r3=0x000000ff -// load r4=0x00000000 - loadsym p0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - - _dbg r0; - _dbg r1; - _dbg r2; - _dbg r3; - _dbg r4; - - R7 = 0; - ASTAT = R7; - r5 = r1 << 0x4 (s); - _DBG ASTAT; - r7=astat; - dbga (r5.h, 0x7fff); - dbga (r5.l, 0xffff); - dbga (r7.h, 0x0300); // V=1, VS=1 - dbga (r7.l, 0x8); - - R7 = 0; - ASTAT = R7; - r5.h = r1.h << 0x4 (s); - _DBG ASTAT; - r7=astat; - dbga (r5.h, 0x7fff); - dbga (r7.h, 0x0300); // V=1, VS=1 - dbga (r7.l, 0x8); - - A0 = 0; - A0.w = r1; - A0.x = r0.l; - r6 = 0x3; - _dbg r6; - _dbg A0; - R7 = 0; - ASTAT = R7; - A0 = ASHIFT A0 BY R6.L; - _DBG ASTAT; - _DBG A0; - r7 = astat; - dbga (r7.h, 0x0); // AV0=0, AV0S=0 - dbga (r7.l, 0x2); // AN = 1 - - A1 = 0; - A1 = r1; - A1.x = r0.l; - r6 = 0x3; - _dbg A1; - R7 = 0; - ASTAT = R7; - A1 = ASHIFT A1 BY R6.L; - _DBG ASTAT; - _DBG A1; - r7 = astat; - dbga (r7.h, 0x0); // AV1=0, AV1S=0 - dbga (r7.l, 0x2); // AN = 1 - - pass - - .data 0x1000; -data0: - .dw 0x1111 - .dw 0x1111 - .dw 0xffff - .dw 0x7fff - .dw 0x0000 - .dw 0x8000 - .dw 0x00ff - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/ashift_left.s b/sim/testsuite/sim/bfin/ashift_left.s deleted file mode 100644 index 04cfa40..0000000 --- a/sim/testsuite/sim/bfin/ashift_left.s +++ /dev/null @@ -1,17 +0,0 @@ -# Blackfin testcase for left ashift -# Dreg = Dreg << imm (S); -# mach: bfin - - .include "testutils.inc" - - .macro test in:req, shift:req, out:req, opt - imm32 r0, \in; - r1 = r0 >>> \shift \opt; - CHECKREG r1, \out; - .endm - - start - -test 2, 1, 1, (S); - - pass diff --git a/sim/testsuite/sim/bfin/b0.S b/sim/testsuite/sim/bfin/b0.S deleted file mode 100644 index 5a02092..0000000 --- a/sim/testsuite/sim/bfin/b0.S +++ /dev/null @@ -1,51 +0,0 @@ -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - CC = R0 == R0; - - AZ = CC; - _DBG ASTAT; - R0 = ASTAT; CHECKREG R0, (_AC0|_AC0_COPY|_CC|_AZ); - R0 = R0 + R0; - R0 = ASTAT; CHECKREG R0, (_CC); - - AN = CC; - R0 = ASTAT; CHECKREG R0, (_CC|_AN); - R0 = - R0; - R0 = ASTAT; CHECKREG R0, (_CC|_AN); - - AC0 = CC; - _DBG ASTAT; - R0 = ASTAT; CHECKREG R0, (_AC0|_CC|_AN); - - AV0 = CC; - _DBG ASTAT; - R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_CC|_AN); - - AV1 = CC; - _DBG ASTAT; - R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_CC|_AN); - - AQ = CC; - _DBG ASTAT; - R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AQ|_CC|_AN); - - CC = R0 < R0; - _DBG ASTAT; - -// When AV0 is set, AV1 is unchanged - AQ = CC; - _DBG ASTAT; - R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AC0_COPY|_AZ); - - AV1 = CC; - _DBG ASTAT; - R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_AC0_COPY|_AZ); - - pass diff --git a/sim/testsuite/sim/bfin/b1.s b/sim/testsuite/sim/bfin/b1.s deleted file mode 100644 index c9eaeca..0000000 --- a/sim/testsuite/sim/bfin/b1.s +++ /dev/null @@ -1,12 +0,0 @@ -# mach: bfin -.include "testutils.inc" - start - - R0 = 0; - CC = R0 == R0; - - IF CC JUMP 4; - JUMP.S LL1; - pass -LL1: - fail diff --git a/sim/testsuite/sim/bfin/b2.S b/sim/testsuite/sim/bfin/b2.S deleted file mode 100644 index 731f874..0000000 --- a/sim/testsuite/sim/bfin/b2.S +++ /dev/null @@ -1,26 +0,0 @@ -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - CC = BITTST ( R0 , 0x0 ); - BITSET( R0 , 0x0 ); - CC = BITTST ( R0 , 0x0 ); - CC = ! BITTST( R0 , 0x0 ); - R1.L = 1; - R1.H = 0; - CC = R0 == R1; - CC = BITTST ( R0 , 0x1 ); - R5 = ASTAT; - CHECKREG R5, (_AC0|_AC0_COPY|_AZ) - - BITSET( R0 , 0x1 ); - R5 = ASTAT; - CHECKREG R5, 0 - CC = BITTST ( R0 , 0x1 ); - CC = ! BITTST( R0 , 0x1 ); - pass diff --git a/sim/testsuite/sim/bfin/brcc.s b/sim/testsuite/sim/bfin/brcc.s deleted file mode 100644 index 479bf50..0000000 --- a/sim/testsuite/sim/bfin/brcc.s +++ /dev/null @@ -1,164 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - /* Stall tests */ - - r0 = 0; - r1 = 1; - loadsym p0, foo; - p1 = p0; - -pass_1: - cc = r0; - nop; - nop; - - if cc jump _fail_1; - [p0++] = p0; - [p0++] = p0; - r7 = p0; - r5 = CC; - P1 += 8; - r6 = p1; - CC = R6 == R7; - if !CC jump _failure; - - cc = R5; - if !cc jump over; - -_fail_1: - [p0++] = p0; - [p0++] = p0; - -back: - if !cc jump skip(bp); - -_fail_2: - [p0++] = p0; - [p0++] = p0; - -over: - if cc jump _fail_3(bp); - [p0++] = p0; - [p0++] = p0; - r7=p0; - R5=cc; - P1 += 8; - R6 = P1; - CC = R6 == R7; - if !CC jump _failure; - - CC = R5; - if !cc jump back(bp); - -_fail_3: - [p0++] = p0; - [p0++] = p0; - -skip: - [p0++] = p0; - [p0++] = p0; - [p0++] = p0; - r7=p0; - - P1 += 0xc; - R6 = P1; - CC = R6 == R7; - if !CC jump _failure; - -next: - [p0++] = p0; - r7=p0; - P1 += 4; - R6 = P1; - CC = R6 == R7; - if !CC jump _failure; - -pass_2: - cc = r1; - nop; - nop; - - if !cc jump _fail_4; - [p0++] = p0; - [p0++] = p0; - r7=p0; - R5 = cc; - P1 += 8; - R6 = P1; - CC = R6 == R7; - if !CC jump _failure; - - cc = R5; - if cc jump over_2; - -_fail_4: - [p0++] = p0; - [p0++] = p0; - P1 += 8; - -back_2: - if cc jump skip_2 (bp); - -_fail_5: - [p0++] = p0; - [p0++] = p0; - P1 += 8; - -over_2: - if !cc jump _fail_6 (bp); - [p0++] = p0; - [p0++] = p0; - r7=p0; - R5 = cc; - P1 += 8; - R6 = P1; - CC = R6 == R7; - if !CC jump _failure; - cc = R5; - - if cc jump back_2 (bp); - -_fail_6: - [p0++] = p0; - [p0++] = p0; - -skip_2: - [p0++] = p0; - [p0++] = p0; - [p0++] = p0; - r7=p0; - R5 = cc; - P1 += 0xc; - R6 = P1; - CC = R6 == R7; - if !CC jump _failure; - cc = r5; - - if cc jump next_2 (bp); - -next_2: - [p0++] = p0; - [p0++] = p0; - P1 += 8; - r7=p0; - r6 = P1; - CC = R6 == R7; - if !CC jump _failure; - - cc = r0; -_halt: - pass; - -_fail_7: - [p0++] = p0; - -_failure: - fail; - - .data -foo: - .space (0x100) diff --git a/sim/testsuite/sim/bfin/brevadd.s b/sim/testsuite/sim/bfin/brevadd.s deleted file mode 100644 index 56e1122..0000000 --- a/sim/testsuite/sim/bfin/brevadd.s +++ /dev/null @@ -1,20 +0,0 @@ -# Blackfin testcase for signbits -# mach: bfin - - .include "testutils.inc" - - start - - L2 = 0; - M2 = -4 (X); - I2.H = 0x9000; - I2.L = 0; - I2 += M2 (BREV); - R2 = I2; - imm32 r0, 0x10000002 - CC = R2 == R0 - if CC jump 1f; - - fail -1: - pass diff --git a/sim/testsuite/sim/bfin/byteop16m.s b/sim/testsuite/sim/bfin/byteop16m.s deleted file mode 100644 index bd7478f..0000000 --- a/sim/testsuite/sim/bfin/byteop16m.s +++ /dev/null @@ -1,76 +0,0 @@ -# Blackfin testcase for BYTEOP16M -# mach: bfin - - .include "testutils.inc" - - start - - .macro check_it resL:req, resH:req - imm32 R6, \resL - CC = R4 == R6; - IF !CC JUMP 1f; -#DBG R4 - imm32 R7, \resH - CC = R5 == R7; - IF !CC JUMP 1f; -#DBG R5 - .endm - .macro test_byteop16m i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req - dmm32 I0, \i0 - dmm32 I1, \i1 - - (R4, R5) = BYTEOP16M (R1:0, R3:2); - check_it \resL, \resH - (R4, R5) = BYTEOP16M (R1:0, R3:2) (R); - check_it \resLR, \resHR - - jump 2f; -1: fail -2: - .endm - - imm32 R0, 0x01020304 - imm32 R1, 0x10203040 - imm32 R2, 0x0a0b0c0d - imm32 R3, 0xa0b0c0d0 - - test_byteop16m 0, 0, 0xfff7fff7, 0xfff7fff7, 0xff70ff70, 0xff70ff70 - test_byteop16m 0, 1, 0xff31fff8, 0xfff8fff8, 0x0003ff80, 0xff80ff80 - test_byteop16m 0, 2, 0xff41ff32, 0xfff9fff9, 0x00040013, 0xff90ff90 - test_byteop16m 0, 3, 0xff51ff42, 0xff33fffa, 0x00050014, 0x0023ffa0 - test_byteop16m 1, 0, 0x0036fff6, 0xfff6fff6, 0xff64ff60, 0xff60ff60 - test_byteop16m 1, 1, 0xff70fff7, 0xfff7fff7, 0xfff7ff70, 0xff70ff70 - test_byteop16m 1, 2, 0xff80ff31, 0xfff8fff8, 0xfff80003, 0xff80ff80 - test_byteop16m 1, 3, 0xff90ff41, 0xff32fff9, 0xfff90004, 0x0013ff90 - test_byteop16m 2, 0, 0x00260035, 0xfff5fff5, 0xff63ff54, 0xff50ff50 - test_byteop16m 2, 1, 0xff600036, 0xfff6fff6, 0xfff6ff64, 0xff60ff60 - test_byteop16m 2, 2, 0xff70ff70, 0xfff7fff7, 0xfff7fff7, 0xff70ff70 - test_byteop16m 2, 3, 0xff80ff80, 0xff31fff8, 0xfff8fff8, 0x0003ff80 - test_byteop16m 3, 0, 0x00160025, 0x0034fff4, 0xff62ff53, 0xff44ff40 - test_byteop16m 3, 1, 0xff500026, 0x0035fff5, 0xfff5ff63, 0xff54ff50 - test_byteop16m 3, 2, 0xff60ff60, 0x0036fff6, 0xfff6fff6, 0xff64ff60 - test_byteop16m 3, 3, 0xff70ff70, 0xff70fff7, 0xfff7fff7, 0xfff7ff70 - - imm32 R0, ~0x01020304 - imm32 R1, ~0x10203040 - imm32 R2, ~0x0a0b0c0d - imm32 R3, ~0xa0b0c0d0 - - test_byteop16m 0, 0, 0x00090009, 0x00090009, 0x00900090, 0x00900090 - test_byteop16m 0, 1, 0x00cf0008, 0x00080008, 0xfffd0080, 0x00800080 - test_byteop16m 0, 2, 0x00bf00ce, 0x00070007, 0xfffcffed, 0x00700070 - test_byteop16m 0, 3, 0x00af00be, 0x00cd0006, 0xfffbffec, 0xffdd0060 - test_byteop16m 1, 0, 0xffca000a, 0x000a000a, 0x009c00a0, 0x00a000a0 - test_byteop16m 1, 1, 0x00900009, 0x00090009, 0x00090090, 0x00900090 - test_byteop16m 1, 2, 0x008000cf, 0x00080008, 0x0008fffd, 0x00800080 - test_byteop16m 1, 3, 0x007000bf, 0x00ce0007, 0x0007fffc, 0xffed0070 - test_byteop16m 2, 0, 0xffdaffcb, 0x000b000b, 0x009d00ac, 0x00b000b0 - test_byteop16m 2, 1, 0x00a0ffca, 0x000a000a, 0x000a009c, 0x00a000a0 - test_byteop16m 2, 2, 0x00900090, 0x00090009, 0x00090009, 0x00900090 - test_byteop16m 2, 3, 0x00800080, 0x00cf0008, 0x00080008, 0xfffd0080 - test_byteop16m 3, 0, 0xffeaffdb, 0xffcc000c, 0x009e00ad, 0x00bc00c0 - test_byteop16m 3, 1, 0x00b0ffda, 0xffcb000b, 0x000b009d, 0x00ac00b0 - test_byteop16m 3, 2, 0x00a000a0, 0xffca000a, 0x000a000a, 0x009c00a0 - test_byteop16m 3, 3, 0x00900090, 0x00900009, 0x00090009, 0x00090090 - - pass diff --git a/sim/testsuite/sim/bfin/byteop16p.s b/sim/testsuite/sim/bfin/byteop16p.s deleted file mode 100644 index fdc5d66..0000000 --- a/sim/testsuite/sim/bfin/byteop16p.s +++ /dev/null @@ -1,74 +0,0 @@ -# Blackfin testcase for BYTEOP16P -# mach: bfin - - .include "testutils.inc" - - start - - .macro check_it resL:req, resH:req - imm32 R6, \resL - CC = R4 == R6; - IF !CC JUMP 1f; - imm32 R7, \resH - CC = R5 == R7; - IF !CC JUMP 1f; - .endm - .macro test_byteop16p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req - dmm32 I0, \i0 - dmm32 I1, \i1 - - (R4, R5) = BYTEOP16P (R1:0, R3:2); - check_it \resL, \resH - (R4, R5) = BYTEOP16P (R1:0, R3:2) (R); - check_it \resLR, \resHR - - jump 2f; -1: fail -2: - .endm - - imm32 R0, 0x01020304 - imm32 R1, 0x10203040 - imm32 R2, 0x0a0b0c0d - imm32 R3, 0xa0b0c0d0 - - test_byteop16p 0, 0, 0x000b000d, 0x000f0011, 0x00b000d0, 0x00f00110 - test_byteop16p 0, 1, 0x00d1000c, 0x000e0010, 0x001d00c0, 0x00e00100 - test_byteop16p 0, 2, 0x00c100d2, 0x000d000f, 0x001c002d, 0x00d000f0 - test_byteop16p 0, 3, 0x00b100c2, 0x00d3000e, 0x001b002c, 0x003d00e0 - test_byteop16p 1, 0, 0x004a000c, 0x000e0010, 0x00a400c0, 0x00e00100 - test_byteop16p 1, 1, 0x0110000b, 0x000d000f, 0x001100b0, 0x00d000f0 - test_byteop16p 1, 2, 0x010000d1, 0x000c000e, 0x0010001d, 0x00c000e0 - test_byteop16p 1, 3, 0x00f000c1, 0x00d2000d, 0x000f001c, 0x002d00d0 - test_byteop16p 2, 0, 0x003a004b, 0x000d000f, 0x00a300b4, 0x00d000f0 - test_byteop16p 2, 1, 0x0100004a, 0x000c000e, 0x001000a4, 0x00c000e0 - test_byteop16p 2, 2, 0x00f00110, 0x000b000d, 0x000f0011, 0x00b000d0 - test_byteop16p 2, 3, 0x00e00100, 0x00d1000c, 0x000e0010, 0x001d00c0 - test_byteop16p 3, 0, 0x002a003b, 0x004c000e, 0x00a200b3, 0x00c400e0 - test_byteop16p 3, 1, 0x00f0003a, 0x004b000d, 0x000f00a3, 0x00b400d0 - test_byteop16p 3, 2, 0x00e00100, 0x004a000c, 0x000e0010, 0x00a400c0 - test_byteop16p 3, 3, 0x00d000f0, 0x0110000b, 0x000d000f, 0x001100b0 - - imm32 R0, ~0x01020304 - imm32 R1, ~0x10203040 - imm32 R2, ~0x0a0b0c0d - imm32 R3, ~0xa0b0c0d0 - - test_byteop16p 0, 0, 0x01f301f1, 0x01ef01ed, 0x014e012e, 0x010e00ee - test_byteop16p 0, 1, 0x012d01f2, 0x01f001ee, 0x01e1013e, 0x011e00fe - test_byteop16p 0, 2, 0x013d012c, 0x01f101ef, 0x01e201d1, 0x012e010e - test_byteop16p 0, 3, 0x014d013c, 0x012b01f0, 0x01e301d2, 0x01c1011e - test_byteop16p 1, 0, 0x01b401f2, 0x01f001ee, 0x015a013e, 0x011e00fe - test_byteop16p 1, 1, 0x00ee01f3, 0x01f101ef, 0x01ed014e, 0x012e010e - test_byteop16p 1, 2, 0x00fe012d, 0x01f201f0, 0x01ee01e1, 0x013e011e - test_byteop16p 1, 3, 0x010e013d, 0x012c01f1, 0x01ef01e2, 0x01d1012e - test_byteop16p 2, 0, 0x01c401b3, 0x01f101ef, 0x015b014a, 0x012e010e - test_byteop16p 2, 1, 0x00fe01b4, 0x01f201f0, 0x01ee015a, 0x013e011e - test_byteop16p 2, 2, 0x010e00ee, 0x01f301f1, 0x01ef01ed, 0x014e012e - test_byteop16p 2, 3, 0x011e00fe, 0x012d01f2, 0x01f001ee, 0x01e1013e - test_byteop16p 3, 0, 0x01d401c3, 0x01b201f0, 0x015c014b, 0x013a011e - test_byteop16p 3, 1, 0x010e01c4, 0x01b301f1, 0x01ef015b, 0x014a012e - test_byteop16p 3, 2, 0x011e00fe, 0x01b401f2, 0x01f001ee, 0x015a013e - test_byteop16p 3, 3, 0x012e010e, 0x00ee01f3, 0x01f101ef, 0x01ed014e - - pass diff --git a/sim/testsuite/sim/bfin/byteop1p.s b/sim/testsuite/sim/bfin/byteop1p.s deleted file mode 100644 index e90d790..0000000 --- a/sim/testsuite/sim/bfin/byteop1p.s +++ /dev/null @@ -1,75 +0,0 @@ -# Blackfin testcase for BYTEOP1P -# mach: bfin - - .include "testutils.inc" - - start - - .macro check_it res:req - imm32 R7, \res - CC = R6 == R7; - IF !CC JUMP 1f; - .endm - .macro test_byteop1p i0:req, i1:req, res:req, resT:req, resR:req, resTR:req - dmm32 I0, \i0 - dmm32 I1, \i1 - - R6 = BYTEOP1P (R1:0, R3:2); - check_it \res - R6 = BYTEOP1P (R1:0, R3:2) (T); - check_it \resT - R6 = BYTEOP1P (R1:0, R3:2) (R); - check_it \resR - R6 = BYTEOP1P (R1:0, R3:2) (T, R); - check_it \resTR - - jump 2f; -1: fail -2: - .endm - - imm32 R0, 0x01020304 - imm32 R1, 0x10203040 - imm32 R2, 0x0a0b0c0d - imm32 R3, 0xa0b0c0d0 - - test_byteop1p 0, 0, 0x06070809, 0x05060708, 0x58687888, 0x58687888 - test_byteop1p 0, 1, 0x69060708, 0x68060708, 0x0f607080, 0x0e607080 - test_byteop1p 0, 2, 0x61690708, 0x60690607, 0x0e176878, 0x0e166878 - test_byteop1p 0, 3, 0x59616a07, 0x58616907, 0x0e161f70, 0x0d161e70 - test_byteop1p 1, 0, 0x25060708, 0x25060708, 0x52607080, 0x52607080 - test_byteop1p 1, 1, 0x88060708, 0x88050607, 0x09586878, 0x08586878 - test_byteop1p 1, 2, 0x80690607, 0x80680607, 0x080f6070, 0x080e6070 - test_byteop1p 1, 3, 0x78616907, 0x78606906, 0x080e1768, 0x070e1668 - test_byteop1p 2, 0, 0x1d260708, 0x1d250607, 0x525a6878, 0x515a6878 - test_byteop1p 2, 1, 0x80250607, 0x80250607, 0x08526070, 0x08526070 - test_byteop1p 2, 2, 0x78880607, 0x78880506, 0x08095868, 0x07085868 - test_byteop1p 2, 3, 0x70806906, 0x70806806, 0x07080f60, 0x07080e60 - test_byteop1p 3, 0, 0x151e2607, 0x151d2607, 0x515a6270, 0x51596270 - test_byteop1p 3, 1, 0x781d2607, 0x781d2506, 0x08525a68, 0x07515a68 - test_byteop1p 3, 2, 0x70802506, 0x70802506, 0x07085260, 0x07085260 - test_byteop1p 3, 3, 0x68788806, 0x68788805, 0x07080958, 0x06070858 - - imm32 R0, ~0x01020304 - imm32 R1, ~0x10203040 - imm32 R2, ~0x0a0b0c0d - imm32 R3, ~0xa0b0c0d0 - - test_byteop1p 0, 0, 0xfaf9f8f7, 0xf9f8f7f6, 0xa7978777, 0xa7978777 - test_byteop1p 0, 1, 0x97f9f8f7, 0x96f9f8f7, 0xf19f8f7f, 0xf09f8f7f - test_byteop1p 0, 2, 0x9f96f9f8, 0x9e96f8f7, 0xf1e99787, 0xf1e89787 - test_byteop1p 0, 3, 0xa79e96f8, 0xa69e95f8, 0xf2e9e18f, 0xf1e9e08f - test_byteop1p 1, 0, 0xdaf9f8f7, 0xdaf9f8f7, 0xad9f8f7f, 0xad9f8f7f - test_byteop1p 1, 1, 0x77faf9f8, 0x77f9f8f7, 0xf7a79787, 0xf6a79787 - test_byteop1p 1, 2, 0x7f97f9f8, 0x7f96f9f8, 0xf7f19f8f, 0xf7f09f8f - test_byteop1p 1, 3, 0x879f96f9, 0x879e96f8, 0xf8f1e997, 0xf7f1e897 - test_byteop1p 2, 0, 0xe2daf9f8, 0xe2d9f8f7, 0xaea59787, 0xada59787 - test_byteop1p 2, 1, 0x7fdaf9f8, 0x7fdaf9f8, 0xf7ad9f8f, 0xf7ad9f8f - test_byteop1p 2, 2, 0x8777faf9, 0x8777f9f8, 0xf8f7a797, 0xf7f6a797 - test_byteop1p 2, 3, 0x8f7f97f9, 0x8f7f96f9, 0xf8f7f19f, 0xf8f7f09f - test_byteop1p 3, 0, 0xeae2d9f8, 0xeae1d9f8, 0xaea69d8f, 0xaea59d8f - test_byteop1p 3, 1, 0x87e2daf9, 0x87e2d9f8, 0xf8aea597, 0xf7ada597 - test_byteop1p 3, 2, 0x8f7fdaf9, 0x8f7fdaf9, 0xf8f7ad9f, 0xf8f7ad9f - test_byteop1p 3, 3, 0x978777fa, 0x978777f9, 0xf9f8f7a7, 0xf8f7f6a7 - - pass diff --git a/sim/testsuite/sim/bfin/byteop2p.s b/sim/testsuite/sim/bfin/byteop2p.s deleted file mode 100644 index e11109a..0000000 --- a/sim/testsuite/sim/bfin/byteop2p.s +++ /dev/null @@ -1,58 +0,0 @@ -# Blackfin testcase for BYTEOP2P -# mach: bfin - - .include "testutils.inc" - - start - - .macro check_it res:req - imm32 R7, \res - CC = R6 == R7; - IF !CC JUMP 1f; - .endm - .macro test_byteop2p i0:req, resRL:req, resRH:req, resTL:req, resTH:req, resRLr:req, resRHr:req, resTLr:req, resTHr:req - dmm32 I0, \i0 - - R6 = BYTEOP2P (R1:0, R3:2) (rndl); - check_it \resRL - R6 = BYTEOP2P (R1:0, R3:2) (rndh); - check_it \resRH - R6 = BYTEOP2P (R1:0, R3:2) (tl); - check_it \resTL - R6 = BYTEOP2P (R1:0, R3:2) (th); - check_it \resTH - R6 = BYTEOP2P (R1:0, R3:2) (rndl, r); - check_it \resRLr - R6 = BYTEOP2P (R1:0, R3:2) (rndh, r); - check_it \resRHr - R6 = BYTEOP2P (R1:0, R3:2) (tl, r); - check_it \resTLr - R6 = BYTEOP2P (R1:0, R3:2) (th, r); - check_it \resTHr - - jump 2f; -1: fail -2: - .endm - - imm32 R0, 0x01020304 - imm32 R1, 0x10203040 - imm32 R2, 0x0a0b0c0d - imm32 R3, 0xa0b0c0d0 - - test_byteop2p 0, 0x00060008, 0x06000800, 0x00060008, 0x06000800, 0x00600080, 0x60008000, 0x00600080, 0x60008000 - test_byteop2p 1, 0x00470007, 0x47000700, 0x00460007, 0x46000700, 0x00300070, 0x30007000, 0x00300070, 0x30007000 - test_byteop2p 2, 0x00800006, 0x80000600, 0x00800006, 0x80000600, 0x00080060, 0x08006000, 0x00080060, 0x08006000 - test_byteop2p 3, 0x00700047, 0x70004700, 0x00700046, 0x70004600, 0x00070030, 0x07003000, 0x00070030, 0x07003000 - - imm32 R0, ~0x01020304 - imm32 R1, ~0x10203040 - imm32 R2, ~0x0a0b0c0d - imm32 R3, ~0xa0b0c0d0 - - test_byteop2p 0, 0x00f900f7, 0xf900f700, 0x00f900f7, 0xf900f700, 0x009f007f, 0x9f007f00, 0x009f007f, 0x9f007f00 - test_byteop2p 1, 0x00b800f8, 0xb800f800, 0x00b800f8, 0xb800f800, 0x00cf008f, 0xcf008f00, 0x00ce008f, 0xce008f00 - test_byteop2p 2, 0x007f00f9, 0x7f00f900, 0x007f00f9, 0x7f00f900, 0x00f7009f, 0xf7009f00, 0x00f7009f, 0xf7009f00 - test_byteop2p 3, 0x008f00b8, 0x8f00b800, 0x008f00b8, 0x8f00b800, 0x00f800cf, 0xf800cf00, 0x00f800ce, 0xf800ce00 - - pass diff --git a/sim/testsuite/sim/bfin/byteop3p.s b/sim/testsuite/sim/bfin/byteop3p.s deleted file mode 100644 index a5390f8..0000000 --- a/sim/testsuite/sim/bfin/byteop3p.s +++ /dev/null @@ -1,119 +0,0 @@ -# Blackfin testcase for BYTEOP3P -# mach: bfin - - .include "testutils.inc" - - start - - .macro check_it res:req - imm32 R7, \res - CC = R6 == R7; - IF !CC JUMP 1f; - .endm - .macro test_byteop3p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req - dmm32 I0, \i0 - dmm32 I1, \i1 - - R6 = BYTEOP3P (R1:0, R3:2) (LO); - check_it \resL - R6 = BYTEOP3P (R1:0, R3:2) (HI); - check_it \resH - R6 = BYTEOP3P (R1:0, R3:2) (LO, R); - check_it \resLR - R6 = BYTEOP3P (R1:0, R3:2) (HI, R); - check_it \resHR - - jump 2f; -1: fail -2: - .endm - - imm32 R0, 0x01020304 - imm32 R1, 0x10203040 - imm32 R2, 0x0a0b0c0d - imm32 R3, 0xa0b0c0d0 - - test_byteop3p 0, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 0, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 0, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 0, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 2, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 2, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 2, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 2, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 3, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 3, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 3, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 3, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - - imm32 R0, ~0x01020304 - imm32 R1, ~0x10203040 - imm32 R2, ~0x0a0b0c0d - imm32 R3, ~0xa0b0c0d0 - - test_byteop3p 0, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 0, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 0, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 0, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 1, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 1, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 1, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 1, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 2, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 2, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 2, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 2, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 3, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 3, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 3, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - test_byteop3p 3, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - - imm32 R0, 0x00010002 - imm32 R1, 0x00030004 - imm32 R2, 0x10203040 - imm32 R3, 0x50607080 - - test_byteop3p 0, 0, 0x00110032, 0x21004200, 0x00530074, 0x63008400 - test_byteop3p 0, 1, 0x00810022, 0x11003200, 0x00430064, 0x53007400 - test_byteop3p 0, 2, 0x00710012, 0x81002200, 0x00330054, 0x43006400 - test_byteop3p 0, 3, 0x00610082, 0x71001200, 0x00230044, 0x33005400 - test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 2, 0, 0x00140031, 0x24004100, 0x00520073, 0x62008300 - test_byteop3p 2, 1, 0x00840021, 0x14003100, 0x00420063, 0x52007300 - test_byteop3p 2, 2, 0x00740011, 0x84002100, 0x00320053, 0x42006300 - test_byteop3p 2, 3, 0x00640081, 0x74001100, 0x00220043, 0x32005300 - test_byteop3p 3, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 3, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 3, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 3, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 - - imm32 R0, 0x00100200 - imm32 R1, 0x30000040 - imm32 R2, 0x1a2b3c4d - imm32 R3, 0x5e6f7a8b - - test_byteop3p 0, 0, 0x002a00ff, 0x3b00ff00, 0x00ff00ba, 0xff00cb00 - test_byteop3p 0, 1, 0x009b00ff, 0x2a00ff00, 0x00ff00af, 0xff00ba00 - test_byteop3p 0, 2, 0x008a00ff, 0x9b00ff00, 0x00ff009e, 0xff00af00 - test_byteop3p 0, 3, 0x007f00ff, 0x8a00ff00, 0x00ff008d, 0xff009e00 - test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x008e007a, 0x9f008b00 - test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x007d006f, 0x8e007a00 - test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x006c005e, 0x7d006f00 - test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x005b004d, 0x6c005e00 - test_byteop3p 2, 0, 0x005a004c, 0x6b005d00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 2, 1, 0x00cb003b, 0x5a004c00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 2, 2, 0x00ba002a, 0xcb003b00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 2, 3, 0x00af009b, 0xba002a00, 0x00ff00ff, 0xff00ff00 - test_byteop3p 3, 0, 0x001a00ff, 0x2b00ff00, 0x00ff00aa, 0xff00bb00 - test_byteop3p 3, 1, 0x008b00ff, 0x1a00ff00, 0x00ff009f, 0xff00aa00 - test_byteop3p 3, 2, 0x007a00ff, 0x8b00ff00, 0x00ff008e, 0xff009f00 - test_byteop3p 3, 3, 0x006f00ff, 0x7a00ff00, 0x00ff007d, 0xff008e00 - - pass diff --git a/sim/testsuite/sim/bfin/byteunpack.s b/sim/testsuite/sim/bfin/byteunpack.s deleted file mode 100644 index 883c071..0000000 --- a/sim/testsuite/sim/bfin/byteunpack.s +++ /dev/null @@ -1,45 +0,0 @@ -# Blackfin testcase for playing with BYTEUNPACK -# mach: bfin - - .include "testutils.inc" - - start - - .macro _bu_pre_test i0:req, src0:req, src1:req - dmm32 I0, \i0 - imm32 R0, \src0 - imm32 R1, \src1 - .endm - .macro _bu_chk_test dst0:req, dst1:req - imm32 R2, \dst0 - imm32 R3, \dst1 - CC = R5 == R2; - IF !CC jump 1f; - CC = R6 == R3; - IF !CC jump 1f; - .endm - .macro bu_test i0:req, dst0:req, dst1:req, src0:req, src1:req - _bu_pre_test \i0, \src0, \src1 - (R6, R5) = BYTEUNPACK R1:0; - _bu_chk_test \dst0, \dst1 - .endm - .macro bu_r_test i0:req, dst0:req, dst1:req, src0:req, src1:req - _bu_pre_test \i0, \src0, \src1 - (R6, R5) = BYTEUNPACK R1:0 (R); - _bu_chk_test \dst0, \dst1 - .endm - - # Taken from PRM - bu_test 0, 0x00BA00DD, 0x00BE00EF, 0xBEEFBADD, 0xFEEDFACE - bu_test 1, 0x00EF00BA, 0x00CE00BE, 0xBEEFBADD, 0xFEEDFACE - bu_test 2, 0x00BE00EF, 0x00FA00CE, 0xBEEFBADD, 0xFEEDFACE - bu_test 3, 0x00CE00BE, 0x00ED00FA, 0xBEEFBADD, 0xFEEDFACE - - # Taken from PRM - bu_r_test 0, 0x00FA00CE, 0x00FE00ED, 0xBEEFBADD, 0xFEEDFACE - bu_r_test 1, 0x00ED00FA, 0x00DD00FE, 0xBEEFBADD, 0xFEEDFACE - bu_r_test 2, 0x00FE00ED, 0x00BA00DD, 0xBEEFBADD, 0xFEEDFACE - bu_r_test 3, 0x00DD00FE, 0x00EF00BA, 0xBEEFBADD, 0xFEEDFACE - - pass -1: fail diff --git a/sim/testsuite/sim/bfin/c_alu2op_arith_r_sft.s b/sim/testsuite/sim/bfin/c_alu2op_arith_r_sft.s deleted file mode 100644 index 7ce9d4e..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_arith_r_sft.s +++ /dev/null @@ -1,226 +0,0 @@ -//Original:/testcases/core/c_alu2op_arith_r_sft/c_alu2op_arith_r_sft.dsp -// Spec Reference: alu2op arith right -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x856789ab; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R1.L = 1; -R1 >>>= R0; -R2 >>>= R0; -R3 >>>= R0; -R4 >>>= R0; -R5 >>>= R0; -R6 >>>= R0; -R7 >>>= R0; -R4 >>>= R0; -R0 >>>= R0; -CHECKREG r1, 0x12340001; -CHECKREG r2, 0x23456789; -CHECKREG r3, 0x3456789A; -CHECKREG r4, 0x856789AB; -CHECKREG r5, 0x96789ABC; -CHECKREG r6, 0xA789ABCD; -CHECKREG r7, 0xB89ABCDE; -CHECKREG r0, 0x00000000; - -imm32 r0, 0x01230002; -imm32 r1, 0x00000000; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R1.L = -1; -R0 >>>= R1; -R2 >>>= R1; -R3 >>>= R1; -R4 >>>= R1; -R5 >>>= R1; -R6 >>>= R1; -R7 >>>= R1; -R1 >>>= R1; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0xFFFFFFFF; -CHECKREG r3, 0xFFFFFFFF; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0xFFFFFFFF; -CHECKREG r7, 0xFFFFFFFF; - -imm32 r0, 0x51230002; -imm32 r1, 0x12345678; -imm32 r2, 0x00000000; -imm32 r3, 0x3456789a; -imm32 r4, 0x956789ab; -imm32 r5, 0x86789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R2.L = 31; -R0 >>>= R2; -R1 >>>= R2; -R3 >>>= R2; -R4 >>>= R2; -R5 >>>= R2; -R6 >>>= R2; -R7 >>>= R2; -R2 >>>= R2; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x01230002; -imm32 r1, 0x82345678; -imm32 r2, 0x93456789; -imm32 r3, 0x00000000; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R3.L = -31; -R0 >>>= R3; -R1 >>>= R3; -R2 >>>= R3; -R4 >>>= R3; -R5 >>>= R3; -R6 >>>= R3; -R7 >>>= R3; -R3 >>>= R3; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0xFFFFFFFF; -CHECKREG r2, 0xFFFFFFFF; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0xFFFFFFFF; -CHECKREG r7, 0xFFFFFFFF; - -imm32 r0, 0x00000001; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x00000000; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R4.L = 15; -R1 >>>= R4; -R2 >>>= R4; -R3 >>>= R4; -R0 >>>= R4; -R5 >>>= R4; -R6 >>>= R4; -R7 >>>= R4; -R4 >>>= R4; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00002468; -CHECKREG r2, 0x0000468A; -CHECKREG r3, 0x000068AC; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0xFFFF2CF1; -CHECKREG r6, 0xFFFF4F13; -CHECKREG r7, 0xFFFF7135; - -imm32 r0, 0x01230002; -imm32 r1, 0x00000000; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0x00000000; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R5.L = -15; -R0 >>>= R5; -R1 >>>= R5; -R2 >>>= R5; -R3 >>>= R5; -R4 >>>= R5; -R6 >>>= R5; -R7 >>>= R5; -R5 >>>= R5; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0xFFFFFFFF; -CHECKREG r3, 0xFFFFFFFF; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0xFFFFFFFF; -CHECKREG r7, 0xFFFFFFFF; - -imm32 r0, 0x51230002; -imm32 r1, 0x12345678; -imm32 r2, 0xb1256790; -imm32 r3, 0x3456789a; -imm32 r4, 0x956789ab; -imm32 r5, 0x86789abc; -imm32 r6, 0x00000000; -imm32 r7, 0x789abcde; -R6.L = 24; -R0 >>>= R6; -R1 >>>= R6; -R2 >>>= R6; -R3 >>>= R6; -R4 >>>= R6; -R5 >>>= R6; -R7 >>>= R6; -R6 >>>= R6; -CHECKREG r0, 0x00000051; -CHECKREG r1, 0x00000012; -CHECKREG r2, 0xFFFFFFB1; -CHECKREG r3, 0x00000034; -CHECKREG r4, 0xFFFFFF95; -CHECKREG r5, 0xFFFFFF86; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000078; - -imm32 r0, 0x01230002; -imm32 r1, 0x82345678; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0x00000000; -R7.L = -24; -R0 >>>= R7; -R1 >>>= R7; -R2 >>>= R7; -R3 >>>= R7; -R4 >>>= R7; -R5 >>>= R7; -R6 >>>= R7; -R7 >>>= R7; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0xFFFFFFFF; -CHECKREG r2, 0xFFFFFFFF; -CHECKREG r3, 0xFFFFFFFF; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0xFFFFFFFF; -CHECKREG r7, 0x00000000; - -// special case -R2.L = -1; -R2.H = 32767; -R0 = 0; -R2 >>>= R0; -CHECKREG r2, 0x7FFFFFFF; - -pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_b.s b/sim/testsuite/sim/bfin/c_alu2op_conv_b.s deleted file mode 100644 index 0de3b52..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_conv_b.s +++ /dev/null @@ -1,211 +0,0 @@ -//Original:/testcases/core/c_alu2op_conv_b/c_alu2op_conv_b.dsp -// Spec Reference: alu2op convert b -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00789abc; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x856789ab; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R0 = R0.B (Z); -R1 = R0.B (Z); -R2 = R0.B (Z); -R3 = R0.B (Z); -R4 = R0.B (Z); -R5 = R0.B (Z); -R6 = R0.B (Z); -R7 = R0.B (Z); -CHECKREG r0, 0x000000BC; -CHECKREG r1, 0x000000BC; -CHECKREG r2, 0x000000BC; -CHECKREG r3, 0x000000BC; -CHECKREG r4, 0x000000BC; -CHECKREG r5, 0x000000BC; -CHECKREG r6, 0x000000BC; -CHECKREG r7, 0x000000BC; - -imm32 r0, 0x01230002; -imm32 r1, 0x00374659; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R0 = R1.B (Z); -R2 = R1.B (Z); -R3 = R1.B (Z); -R4 = R1.B (Z); -R5 = R1.B (Z); -R6 = R1.B (Z); -R7 = R1.B (Z); -R1 = R1.B (Z); -CHECKREG r0, 0x00000059; -CHECKREG r1, 0x00000059; -CHECKREG r2, 0x00000059; -CHECKREG r3, 0x00000059; -CHECKREG r4, 0x00000059; -CHECKREG r5, 0x00000059; -CHECKREG r6, 0x00000059; -CHECKREG r7, 0x00000059; - -imm32 r0, 0x10789abc; -imm32 r1, 0x11345678; -imm32 r2, 0x93156789; -imm32 r3, 0xd451789a; -imm32 r4, 0x856719ab; -imm32 r5, 0x267891bc; -imm32 r6, 0xa789ab1d; -imm32 r7, 0x989ab1de; -R0 = R2.B (Z); -R1 = R2.B (Z); -R3 = R2.B (Z); -R4 = R2.B (Z); -R5 = R2.B (Z); -R6 = R2.B (Z); -R7 = R2.B (Z); -R2 = R2.B (Z); -CHECKREG r0, 0x00000089; -CHECKREG r1, 0x00000089; -CHECKREG r2, 0x00000089; -CHECKREG r3, 0x00000089; -CHECKREG r4, 0x00000089; -CHECKREG r5, 0x00000089; -CHECKREG r6, 0x00000089; -CHECKREG r7, 0x00000089; - -imm32 r0, 0x21230002; -imm32 r1, 0x02374659; -imm32 r2, 0x93256789; -imm32 r3, 0xa952789a; -imm32 r4, 0xb59729ab; -imm32 r5, 0xc67992bc; -imm32 r6, 0xd7899b2d; -imm32 r7, 0xe89ab9d2; -R0 = R3.B (Z); -R1 = R3.B (Z); -R2 = R3.B (Z); -R4 = R3.B (Z); -R5 = R3.B (Z); -R6 = R3.B (Z); -R7 = R3.B (Z); -R3 = R3.B (Z); -CHECKREG r0, 0x0000009A; -CHECKREG r1, 0x0000009A; -CHECKREG r2, 0x0000009A; -CHECKREG r3, 0x0000009A; -CHECKREG r4, 0x0000009A; -CHECKREG r5, 0x0000009A; -CHECKREG r6, 0x0000009A; -CHECKREG r7, 0x0000009A; - -imm32 r0, 0xa0789abc; -imm32 r1, 0x1a345678; -imm32 r2, 0x23a56789; -imm32 r3, 0x645a789a; -imm32 r4, 0x8667a9ab; -imm32 r5, 0x96689abc; -imm32 r6, 0xa787abad; -imm32 r7, 0xb89a7cda; -R0 = R4.B (Z); -R1 = R4.B (Z); -R2 = R4.B (Z); -R3 = R4.B (Z); -R4 = R4.B (Z); -R5 = R4.B (Z); -R6 = R4.B (Z); -R7 = R4.B (Z); -CHECKREG r0, 0x000000AB; -CHECKREG r1, 0x000000AB; -CHECKREG r2, 0x000000AB; -CHECKREG r3, 0x000000AB; -CHECKREG r4, 0x000000AB; -CHECKREG r5, 0x000000AB; -CHECKREG r6, 0x000000AB; -CHECKREG r7, 0x000000AB; - -imm32 r0, 0xf1230002; -imm32 r1, 0x0f374659; -imm32 r2, 0x93f56789; -imm32 r3, 0xa45f789a; -imm32 r4, 0xb567f9ab; -imm32 r5, 0xc6789fbc; -imm32 r6, 0xd789abfd; -imm32 r7, 0xe89abcdf; -R0 = R5.B (Z); -R1 = R5.B (Z); -R2 = R5.B (Z); -R3 = R5.B (Z); -R4 = R5.B (Z); -R6 = R5.B (Z); -R7 = R5.B (Z); -R5 = R5.B (Z); -CHECKREG r0, 0x000000BC; -CHECKREG r1, 0x000000BC; -CHECKREG r2, 0x000000BC; -CHECKREG r3, 0x000000BC; -CHECKREG r4, 0x000000BC; -CHECKREG r5, 0x000000BC; -CHECKREG r6, 0x000000BC; -CHECKREG r7, 0x000000BC; - -imm32 r0, 0xe0789abc; -imm32 r1, 0xe2345678; -imm32 r2, 0x2e456789; -imm32 r3, 0x34e6789a; -imm32 r4, 0x856e89ab; -imm32 r5, 0x9678eabc; -imm32 r6, 0xa789aecd; -imm32 r7, 0xb89abcee; -R0 = R6.B (Z); -R1 = R6.B (Z); -R2 = R6.B (Z); -R3 = R6.B (Z); -R4 = R6.B (Z); -R5 = R6.B (Z); -R7 = R6.B (Z); -R6 = R6.B (Z); -CHECKREG r0, 0x000000CD; -CHECKREG r1, 0x000000CD; -CHECKREG r2, 0x000000CD; -CHECKREG r3, 0x000000CD; -CHECKREG r4, 0x000000CD; -CHECKREG r5, 0x000000CD; -CHECKREG r6, 0x000000CD; -CHECKREG r7, 0x000000CD; - -imm32 r0, 0x012300f5; -imm32 r1, 0x80374659; -imm32 r2, 0x98456589; -imm32 r3, 0xa486589a; -imm32 r4, 0xb56589ab; -imm32 r5, 0xc6588abc; -imm32 r6, 0xd589a8cd; -imm32 r7, 0x589abc88; -R0 = R7.B (Z); -R1 = R7.B (Z); -R2 = R7.B (Z); -R3 = R7.B (Z); -R4 = R7.B (Z); -R5 = R7.B (Z); -R6 = R7.B (Z); -R7 = R7.B (Z); -CHECKREG r0, 0x00000088; -CHECKREG r1, 0x00000088; -CHECKREG r2, 0x00000088; -CHECKREG r3, 0x00000088; -CHECKREG r4, 0x00000088; -CHECKREG r5, 0x00000088; -CHECKREG r6, 0x00000088; -CHECKREG r7, 0x00000088; - - -pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_h.s b/sim/testsuite/sim/bfin/c_alu2op_conv_h.s deleted file mode 100644 index 70468a6..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_conv_h.s +++ /dev/null @@ -1,211 +0,0 @@ -//Original:/testcases/core/c_alu2op_conv_h/c_alu2op_conv_h.dsp -// Spec Reference: alu2op convert h -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00789abc; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x856789ab; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R0 = R0.L (Z); -R1 = R0.L (Z); -R2 = R0.L (Z); -R3 = R0.L (Z); -R4 = R0.L (Z); -R5 = R0.L (Z); -R6 = R0.L (Z); -R7 = R0.L (Z); -CHECKREG r0, 0x00009ABC; -CHECKREG r1, 0x00009ABC; -CHECKREG r2, 0x00009ABC; -CHECKREG r3, 0x00009ABC; -CHECKREG r4, 0x00009ABC; -CHECKREG r5, 0x00009ABC; -CHECKREG r6, 0x00009ABC; -CHECKREG r7, 0x00009ABC; - -imm32 r0, 0x01230002; -imm32 r1, 0x00374659; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R0 = R1.L (Z); -R2 = R1.L (Z); -R3 = R1.L (Z); -R4 = R1.L (Z); -R5 = R1.L (Z); -R6 = R1.L (Z); -R7 = R1.L (Z); -R1 = R1.L (Z); -CHECKREG r0, 0x00004659; -CHECKREG r1, 0x00004659; -CHECKREG r2, 0x00004659; -CHECKREG r3, 0x00004659; -CHECKREG r4, 0x00004659; -CHECKREG r5, 0x00004659; -CHECKREG r6, 0x00004659; -CHECKREG r7, 0x00004659; - -imm32 r0, 0x10789abc; -imm32 r1, 0x11345678; -imm32 r2, 0x93156789; -imm32 r3, 0xd451789a; -imm32 r4, 0x856719ab; -imm32 r5, 0x267891bc; -imm32 r6, 0xa789ab1d; -imm32 r7, 0x989ab1de; -R0 = R2.L (Z); -R1 = R2.L (Z); -R3 = R2.L (Z); -R4 = R2.L (Z); -R5 = R2.L (Z); -R6 = R2.L (Z); -R7 = R2.L (Z); -R2 = R2.L (Z); -CHECKREG r0, 0x00006789; -CHECKREG r1, 0x00006789; -CHECKREG r2, 0x00006789; -CHECKREG r3, 0x00006789; -CHECKREG r4, 0x00006789; -CHECKREG r5, 0x00006789; -CHECKREG r6, 0x00006789; -CHECKREG r7, 0x00006789; - -imm32 r0, 0x21230002; -imm32 r1, 0x02374659; -imm32 r2, 0x93256789; -imm32 r3, 0xa952789a; -imm32 r4, 0xb59729ab; -imm32 r5, 0xc67992bc; -imm32 r6, 0xd7899b2d; -imm32 r7, 0xe89ab9d2; -R0 = R3.L (Z); -R1 = R3.L (Z); -R2 = R3.L (Z); -R4 = R3.L (Z); -R5 = R3.L (Z); -R6 = R3.L (Z); -R7 = R3.L (Z); -R3 = R3.L (Z); -CHECKREG r0, 0x0000789A; -CHECKREG r1, 0x0000789A; -CHECKREG r2, 0x0000789A; -CHECKREG r3, 0x0000789A; -CHECKREG r4, 0x0000789A; -CHECKREG r5, 0x0000789A; -CHECKREG r6, 0x0000789A; -CHECKREG r7, 0x0000789A; - -imm32 r0, 0xa0789abc; -imm32 r1, 0x1a345678; -imm32 r2, 0x23a56789; -imm32 r3, 0x645a789a; -imm32 r4, 0x8667a9ab; -imm32 r5, 0x96689abc; -imm32 r6, 0xa787abad; -imm32 r7, 0xb89a7cda; -R0 = R4.L (Z); -R1 = R4.L (Z); -R2 = R4.L (Z); -R3 = R4.L (Z); -R4 = R4.L (Z); -R5 = R4.L (Z); -R6 = R4.L (Z); -R7 = R4.L (Z); -CHECKREG r0, 0x0000A9AB; -CHECKREG r1, 0x0000A9AB; -CHECKREG r2, 0x0000A9AB; -CHECKREG r3, 0x0000A9AB; -CHECKREG r4, 0x0000A9AB; -CHECKREG r5, 0x0000A9AB; -CHECKREG r6, 0x0000A9AB; -CHECKREG r7, 0x0000A9AB; - -imm32 r0, 0xf1230002; -imm32 r1, 0x0f374659; -imm32 r2, 0x93f56789; -imm32 r3, 0xa45f789a; -imm32 r4, 0xb567f9ab; -imm32 r5, 0xc6789fbc; -imm32 r6, 0xd789abfd; -imm32 r7, 0xe89abcdf; -R0 = R5.L (Z); -R1 = R5.L (Z); -R2 = R5.L (Z); -R3 = R5.L (Z); -R4 = R5.L (Z); -R6 = R5.L (Z); -R7 = R5.L (Z); -R5 = R5.L (Z); -CHECKREG r0, 0x00009FBC; -CHECKREG r1, 0x00009FBC; -CHECKREG r2, 0x00009FBC; -CHECKREG r3, 0x00009FBC; -CHECKREG r4, 0x00009FBC; -CHECKREG r5, 0x00009FBC; -CHECKREG r6, 0x00009FBC; -CHECKREG r7, 0x00009FBC; - -imm32 r0, 0xe0789abc; -imm32 r1, 0xe2345678; -imm32 r2, 0x2e456789; -imm32 r3, 0x34e6789a; -imm32 r4, 0x856e89ab; -imm32 r5, 0x9678eabc; -imm32 r6, 0xa789aecd; -imm32 r7, 0xb89abcee; -R0 = R6.L (Z); -R1 = R6.L (Z); -R2 = R6.L (Z); -R3 = R6.L (Z); -R4 = R6.L (Z); -R5 = R6.L (Z); -R7 = R6.L (Z); -R6 = R6.L (Z); -CHECKREG r0, 0x0000AECD; -CHECKREG r1, 0x0000AECD; -CHECKREG r2, 0x0000AECD; -CHECKREG r3, 0x0000AECD; -CHECKREG r4, 0x0000AECD; -CHECKREG r5, 0x0000AECD; -CHECKREG r6, 0x0000AECD; -CHECKREG r7, 0x0000AECD; - -imm32 r0, 0x012300f5; -imm32 r1, 0x80374659; -imm32 r2, 0x98456589; -imm32 r3, 0xa486589a; -imm32 r4, 0xb56589ab; -imm32 r5, 0xc6588abc; -imm32 r6, 0xd589a8cd; -imm32 r7, 0x589abc88; -R0 = R7.L (Z); -R1 = R7.L (Z); -R2 = R7.L (Z); -R3 = R7.L (Z); -R4 = R7.L (Z); -R5 = R7.L (Z); -R6 = R7.L (Z); -R7 = R7.L (Z); -CHECKREG r0, 0x0000BC88; -CHECKREG r1, 0x0000BC88; -CHECKREG r2, 0x0000BC88; -CHECKREG r3, 0x0000BC88; -CHECKREG r4, 0x0000BC88; -CHECKREG r5, 0x0000BC88; -CHECKREG r6, 0x0000BC88; -CHECKREG r7, 0x0000BC88; - - -pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_mix.s b/sim/testsuite/sim/bfin/c_alu2op_conv_mix.s deleted file mode 100644 index 7c33c13..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_conv_mix.s +++ /dev/null @@ -1,186 +0,0 @@ -//Original:/testcases/core/c_alu2op_conv_mix/c_alu2op_conv_mix.dsp -// Spec Reference: alu2op convert mix -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00789abc; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x856789ab; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R0 = R0.B (X); -R1 = R1.L (X); -R2 = R2.L (Z); -R3 = R3.B (X); -R4 = R4.B (Z); -R5 = - R5; -R6 = ~ R6; -R7 = R7.L (X); -CHECKREG r0, 0xFFFFFFBC; -CHECKREG r1, 0x00005678; -CHECKREG r2, 0x00006789; -CHECKREG r3, 0xFFFFFF9A; -CHECKREG r4, 0x000000AB; -CHECKREG r5, 0x69876544; -CHECKREG r6, 0x58765432; -CHECKREG r7, 0xFFFFBCDE; - -imm32 r0, 0x01230002; -imm32 r1, 0x00374659; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R6 = R0.B (X); -R7 = R1.L (X); -R0 = R2.L (Z); -R1 = R3.B (X); -R2 = R4.B (Z); -R3 = - R5; -R4 = ~ R6; -R5 = R7.L (X); -CHECKREG r0, 0x00006789; -CHECKREG r1, 0xFFFFFF9A; -CHECKREG r2, 0x000000AB; -CHECKREG r3, 0x39876544; -CHECKREG r4, 0xFFFFFFFD; -CHECKREG r5, 0x00004659; -CHECKREG r6, 0x00000002; -CHECKREG r7, 0x00004659; - -imm32 r0, 0x51230002; -imm32 r1, 0x12345678; -imm32 r2, 0x91203450; -imm32 r3, 0x3456789a; -imm32 r4, 0x956789ab; -imm32 r5, 0x86789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0x789abcde; -R5 = R0.B (X); -R6 = R1.L (X); -R7 = R2.L (Z); -R0 = R3.B (X); -R1 = R4.B (Z); -R2 = - R5; -R3 = ~ R6; -R4 = R7.L (X); -CHECKREG r0, 0xFFFFFF9A; -CHECKREG r1, 0x000000AB; -CHECKREG r2, 0xFFFFFFFE; -CHECKREG r3, 0xFFFFA987; -CHECKREG r4, 0x00003450; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00005678; -CHECKREG r7, 0x00003450; - -imm32 r0, 0x01230002; -imm32 r1, 0x82345678; -imm32 r2, 0x93456789; -imm32 r3, 0x00000000; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R4 = R0.B (X); -R5 = R1.L (X); -R6 = R2.L (Z); -R7 = R3.B (X); -R0 = R4.B (Z); -R1 = - R5; -R2 = ~ R6; -R3 = R7.L (X); -CHECKREG r0, 0x00000002; -CHECKREG r1, 0xFFFFA988; -CHECKREG r2, 0xFFFF9876; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000002; -CHECKREG r5, 0x00005678; -CHECKREG r6, 0x00006789; -CHECKREG r7, 0x00000000; - -imm32 r0, 0xadf00001; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x00000000; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R3 = R0.B (X); -R4 = R1.L (X); -R5 = R2.L (Z); -R6 = R3.B (X); -R7 = R4.B (Z); -R0 = - R5; -R1 = ~ R6; -R2 = R7.L (X); -CHECKREG r0, 0xFFFF9877; -CHECKREG r1, 0xFFFFFFFE; -CHECKREG r2, 0x00000078; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00005678; -CHECKREG r5, 0x00006789; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000078; - -imm32 r0, 0x01230002; -imm32 r1, 0x00000000; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0x54238900; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R2 = R0.B (X); -R3 = R1.L (X); -R4 = R2.L (Z); -R5 = R3.B (X); -R6 = R4.B (Z); -R7 = - R5; -R0 = ~ R6; -R1 = R7.L (X); -CHECKREG r0, 0xFFFFFFFD; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000002; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000002; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x51230002; -imm32 r1, 0x12345678; -imm32 r2, 0x00000000; -imm32 r3, 0x3456789a; -imm32 r4, 0x956789ab; -imm32 r5, 0x86789abc; -imm32 r6, 0x00000000; -imm32 r7, 0x789abcde; -R1 = R0.B (X); -R2 = R1.L (X); -R3 = R2.L (Z); -R4 = R3.B (X); -R5 = R4.B (Z); -R6 = - R5; -R0 = ~ R6; -R7 = R7.L (X); -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000002; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00000002; -CHECKREG r4, 0x00000002; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0xFFFFFFFE; -CHECKREG r7, 0xFFFFBCDE; - - -pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_neg.s b/sim/testsuite/sim/bfin/c_alu2op_conv_neg.s deleted file mode 100644 index 85314a8..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_conv_neg.s +++ /dev/null @@ -1,211 +0,0 @@ -//Original:/testcases/core/c_alu2op_conv_neg/c_alu2op_conv_neg.dsp -// Spec Reference: alu2op (-) negative -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00789abc; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x856789ab; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R0 = - R0; -R1 = - R0; -R2 = - R0; -R3 = - R0; -R4 = - R0; -R5 = - R0; -R6 = - R0; -R7 = - R0; -CHECKREG r0, 0xFF876544; -CHECKREG r1, 0x00789ABC; -CHECKREG r2, 0x00789ABC; -CHECKREG r3, 0x00789ABC; -CHECKREG r4, 0x00789ABC; -CHECKREG r5, 0x00789ABC; -CHECKREG r6, 0x00789ABC; -CHECKREG r7, 0x00789ABC; - -imm32 r0, 0x01230002; -imm32 r1, 0x00374659; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R0 = - R1; -R1 = - R1; -R2 = - R1; -R3 = - R1; -R4 = - R1; -R5 = - R1; -R6 = - R1; -R7 = - R1; -CHECKREG r0, 0xFFC8B9A7; -CHECKREG r1, 0xFFC8B9A7; -CHECKREG r2, 0x00374659; -CHECKREG r3, 0x00374659; -CHECKREG r4, 0x00374659; -CHECKREG r5, 0x00374659; -CHECKREG r6, 0x00374659; -CHECKREG r7, 0x00374659; - -imm32 r0, 0x10789abc; -imm32 r1, 0x11345678; -imm32 r2, 0x93156789; -imm32 r3, 0xd451789a; -imm32 r4, 0x856719ab; -imm32 r5, 0x267891bc; -imm32 r6, 0xa789ab1d; -imm32 r7, 0x989ab1de; -R0 = - R2; -R1 = - R2; -R2 = - R2; -R3 = - R2; -R4 = - R2; -R5 = - R2; -R6 = - R2; -R7 = - R2; -CHECKREG r0, 0x6CEA9877; -CHECKREG r1, 0x6CEA9877; -CHECKREG r2, 0x6CEA9877; -CHECKREG r3, 0x93156789; -CHECKREG r4, 0x93156789; -CHECKREG r5, 0x93156789; -CHECKREG r6, 0x93156789; -CHECKREG r7, 0x93156789; - -imm32 r0, 0x21230002; -imm32 r1, 0x02374659; -imm32 r2, 0x93256789; -imm32 r3, 0xa952789a; -imm32 r4, 0xb59729ab; -imm32 r5, 0xc67992bc; -imm32 r6, 0xd7899b2d; -imm32 r7, 0xe89ab9d2; -R0 = - R3; -R1 = - R3; -R2 = - R3; -R3 = - R3; -R4 = - R3; -R5 = - R3; -R6 = - R3; -R7 = - R3; -CHECKREG r0, 0x56AD8766; -CHECKREG r1, 0x56AD8766; -CHECKREG r2, 0x56AD8766; -CHECKREG r3, 0x56AD8766; -CHECKREG r4, 0xA952789A; -CHECKREG r5, 0xA952789A; -CHECKREG r6, 0xA952789A; -CHECKREG r7, 0xA952789A; - -imm32 r0, 0xa0789abc; -imm32 r1, 0x1a345678; -imm32 r2, 0x23a56789; -imm32 r3, 0x645a789a; -imm32 r4, 0x8667a9ab; -imm32 r5, 0x96689abc; -imm32 r6, 0xa787abad; -imm32 r7, 0xb89a7cda; -R0 = - R4; -R1 = - R4; -R2 = - R4; -R3 = - R4; -R4 = - R4; -R5 = - R4; -R6 = - R4; -R7 = - R4; -CHECKREG r0, 0x79985655; -CHECKREG r1, 0x79985655; -CHECKREG r2, 0x79985655; -CHECKREG r3, 0x79985655; -CHECKREG r4, 0x79985655; -CHECKREG r5, 0x8667A9AB; -CHECKREG r6, 0x8667A9AB; -CHECKREG r7, 0x8667A9AB; - -imm32 r0, 0xf1230002; -imm32 r1, 0x0f374659; -imm32 r2, 0x93f56789; -imm32 r3, 0xa45f789a; -imm32 r4, 0xb567f9ab; -imm32 r5, 0xc6789fbc; -imm32 r6, 0xd789abfd; -imm32 r7, 0xe89abcdf; -R0 = - R5; -R1 = - R5; -R2 = - R5; -R3 = - R5; -R4 = - R5; -R5 = - R5; -R6 = - R5; -R7 = - R5; -CHECKREG r0, 0x39876044; -CHECKREG r1, 0x39876044; -CHECKREG r2, 0x39876044; -CHECKREG r3, 0x39876044; -CHECKREG r4, 0x39876044; -CHECKREG r5, 0x39876044; -CHECKREG r6, 0xC6789FBC; -CHECKREG r7, 0xC6789FBC; - -imm32 r0, 0xe0789abc; -imm32 r1, 0xe2345678; -imm32 r2, 0x2e456789; -imm32 r3, 0x34e6789a; -imm32 r4, 0x856e89ab; -imm32 r5, 0x9678eabc; -imm32 r6, 0xa789aecd; -imm32 r7, 0xb89abcee; -R0 = - R6; -R1 = - R6; -R2 = - R6; -R3 = - R6; -R4 = - R6; -R5 = - R6; -R6 = - R6; -R7 = - R6; -CHECKREG r0, 0x58765133; -CHECKREG r1, 0x58765133; -CHECKREG r2, 0x58765133; -CHECKREG r3, 0x58765133; -CHECKREG r4, 0x58765133; -CHECKREG r5, 0x58765133; -CHECKREG r6, 0x58765133; -CHECKREG r7, 0xA789AECD; - -imm32 r0, 0x012300f5; -imm32 r1, 0x80374659; -imm32 r2, 0x98456589; -imm32 r3, 0xa486589a; -imm32 r4, 0xb56589ab; -imm32 r5, 0xc6588abc; -imm32 r6, 0xd589a8cd; -imm32 r7, 0x589abc88; -R0 = - R7; -R1 = - R7; -R2 = - R7; -R3 = - R7; -R4 = - R7; -R5 = - R7; -R7 = - R7; -R6 = - R7; -CHECKREG r0, 0xA7654378; -CHECKREG r1, 0xA7654378; -CHECKREG r2, 0xA7654378; -CHECKREG r3, 0xA7654378; -CHECKREG r4, 0xA7654378; -CHECKREG r5, 0xA7654378; -CHECKREG r6, 0x589ABC88; -CHECKREG r7, 0xA7654378; - - -pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_toggle.s b/sim/testsuite/sim/bfin/c_alu2op_conv_toggle.s deleted file mode 100644 index 791d7a9..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_conv_toggle.s +++ /dev/null @@ -1,211 +0,0 @@ -//Original:/testcases/core/c_alu2op_conv_toggle/c_alu2op_conv_toggle.dsp -// Spec Reference: alu2op (~) toggle -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00789abc; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x856789ab; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R0 = ~ R0; -R1 = ~ R0; -R2 = ~ R0; -R3 = ~ R0; -R4 = ~ R0; -R5 = ~ R0; -R6 = ~ R0; -R7 = ~ R0; -CHECKREG r0, 0xFF876543; -CHECKREG r1, 0x00789ABC; -CHECKREG r2, 0x00789ABC; -CHECKREG r3, 0x00789ABC; -CHECKREG r4, 0x00789ABC; -CHECKREG r5, 0x00789ABC; -CHECKREG r6, 0x00789ABC; -CHECKREG r7, 0x00789ABC; - -imm32 r0, 0x01230002; -imm32 r1, 0x00374659; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R0 = ~ R1; -R1 = ~ R1; -R2 = ~ R1; -R3 = ~ R1; -R4 = ~ R1; -R5 = ~ R1; -R6 = ~ R1; -R7 = ~ R1; -CHECKREG r0, 0xFFC8B9A6; -CHECKREG r1, 0xFFC8B9A6; -CHECKREG r2, 0x00374659; -CHECKREG r3, 0x00374659; -CHECKREG r4, 0x00374659; -CHECKREG r5, 0x00374659; -CHECKREG r6, 0x00374659; -CHECKREG r7, 0x00374659; - -imm32 r0, 0x10789abc; -imm32 r1, 0x11345678; -imm32 r2, 0x93156789; -imm32 r3, 0xd451789a; -imm32 r4, 0x856719ab; -imm32 r5, 0x267891bc; -imm32 r6, 0xa789ab1d; -imm32 r7, 0x989ab1de; -R0 = ~ R2; -R1 = ~ R2; -R2 = ~ R2; -R3 = ~ R2; -R4 = ~ R2; -R5 = ~ R2; -R6 = ~ R2; -R7 = ~ R2; -CHECKREG r0, 0x6CEA9876; -CHECKREG r1, 0x6CEA9876; -CHECKREG r2, 0x6CEA9876; -CHECKREG r3, 0x93156789; -CHECKREG r4, 0x93156789; -CHECKREG r5, 0x93156789; -CHECKREG r6, 0x93156789; -CHECKREG r7, 0x93156789; - -imm32 r0, 0x21230002; -imm32 r1, 0x02374659; -imm32 r2, 0x93256789; -imm32 r3, 0xa952789a; -imm32 r4, 0xb59729ab; -imm32 r5, 0xc67992bc; -imm32 r6, 0xd7899b2d; -imm32 r7, 0xe89ab9d2; -R0 = ~ R3; -R1 = ~ R3; -R2 = ~ R3; -R3 = ~ R3; -R4 = ~ R3; -R5 = ~ R3; -R6 = ~ R3; -R7 = ~ R3; -CHECKREG r0, 0x56AD8765; -CHECKREG r1, 0x56AD8765; -CHECKREG r2, 0x56AD8765; -CHECKREG r3, 0x56AD8765; -CHECKREG r4, 0xA952789A; -CHECKREG r5, 0xA952789A; -CHECKREG r6, 0xA952789A; -CHECKREG r7, 0xA952789A; - -imm32 r0, 0xa0789abc; -imm32 r1, 0x1a345678; -imm32 r2, 0x23a56789; -imm32 r3, 0x645a789a; -imm32 r4, 0x8667a9ab; -imm32 r5, 0x96689abc; -imm32 r6, 0xa787abad; -imm32 r7, 0xb89a7cda; -R0 = ~ R4; -R1 = ~ R4; -R2 = ~ R4; -R3 = ~ R4; -R4 = ~ R4; -R5 = ~ R4; -R6 = ~ R4; -R7 = ~ R4; -CHECKREG r0, 0x79985654; -CHECKREG r1, 0x79985654; -CHECKREG r2, 0x79985654; -CHECKREG r3, 0x79985654; -CHECKREG r4, 0x79985654; -CHECKREG r5, 0x8667A9AB; -CHECKREG r6, 0x8667A9AB; -CHECKREG r7, 0x8667A9AB; - -imm32 r0, 0xf1230002; -imm32 r1, 0x0f374659; -imm32 r2, 0x93f56789; -imm32 r3, 0xa45f789a; -imm32 r4, 0xb567f9ab; -imm32 r5, 0xc6789fbc; -imm32 r6, 0xd789abfd; -imm32 r7, 0xe89abcdf; -R0 = ~ R5; -R1 = ~ R5; -R2 = ~ R5; -R3 = ~ R5; -R4 = ~ R5; -R5 = ~ R5; -R6 = ~ R5; -R7 = ~ R5; -CHECKREG r0, 0x39876043; -CHECKREG r1, 0x39876043; -CHECKREG r2, 0x39876043; -CHECKREG r3, 0x39876043; -CHECKREG r4, 0x39876043; -CHECKREG r5, 0x39876043; -CHECKREG r6, 0xC6789FBC; -CHECKREG r7, 0xC6789FBC; - -imm32 r0, 0xe0789abc; -imm32 r1, 0xe2345678; -imm32 r2, 0x2e456789; -imm32 r3, 0x34e6789a; -imm32 r4, 0x856e89ab; -imm32 r5, 0x9678eabc; -imm32 r6, 0xa789aecd; -imm32 r7, 0xb89abcee; -R0 = ~ R6; -R1 = ~ R6; -R2 = ~ R6; -R3 = ~ R6; -R4 = ~ R6; -R5 = ~ R6; -R6 = ~ R6; -R7 = ~ R6; -CHECKREG r0, 0x58765132; -CHECKREG r1, 0x58765132; -CHECKREG r2, 0x58765132; -CHECKREG r3, 0x58765132; -CHECKREG r4, 0x58765132; -CHECKREG r5, 0x58765132; -CHECKREG r6, 0x58765132; -CHECKREG r7, 0xA789AECD; - -imm32 r0, 0x012300f5; -imm32 r1, 0x80374659; -imm32 r2, 0x98456589; -imm32 r3, 0xa486589a; -imm32 r4, 0xb56589ab; -imm32 r5, 0xc6588abc; -imm32 r6, 0xd589a8cd; -imm32 r7, 0x589abc88; -R0 = ~ R7; -R1 = ~ R7; -R2 = ~ R7; -R3 = ~ R7; -R4 = ~ R7; -R5 = ~ R7; -R7 = ~ R7; -R6 = ~ R7; -CHECKREG r0, 0xA7654377; -CHECKREG r1, 0xA7654377; -CHECKREG r2, 0xA7654377; -CHECKREG r3, 0xA7654377; -CHECKREG r4, 0xA7654377; -CHECKREG r5, 0xA7654377; -CHECKREG r6, 0x589ABC88; -CHECKREG r7, 0xA7654377; - - -pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_xb.s b/sim/testsuite/sim/bfin/c_alu2op_conv_xb.s deleted file mode 100644 index 779a790..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_conv_xb.s +++ /dev/null @@ -1,211 +0,0 @@ -//Original:/testcases/core/c_alu2op_conv_xb/c_alu2op_conv_xb.dsp -// Spec Reference: alu2op convert xb -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00789abc; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x856789ab; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R0 = R0.B (X); -R1 = R0.B (X); -R2 = R0.B (X); -R3 = R0.B (X); -R4 = R0.B (X); -R5 = R0.B (X); -R6 = R0.B (X); -R7 = R0.B (X); -CHECKREG r0, 0xFFFFFFBC; -CHECKREG r1, 0xFFFFFFBC; -CHECKREG r2, 0xFFFFFFBC; -CHECKREG r3, 0xFFFFFFBC; -CHECKREG r4, 0xFFFFFFBC; -CHECKREG r5, 0xFFFFFFBC; -CHECKREG r6, 0xFFFFFFBC; -CHECKREG r7, 0xFFFFFFBC; - -imm32 r0, 0x01230002; -imm32 r1, 0x00374659; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R0 = R1.B (X); -R2 = R1.B (X); -R3 = R1.B (X); -R4 = R1.B (X); -R5 = R1.B (X); -R6 = R1.B (X); -R7 = R1.B (X); -R1 = R1.B (X); -CHECKREG r0, 0x00000059; -CHECKREG r1, 0x00000059; -CHECKREG r2, 0x00000059; -CHECKREG r3, 0x00000059; -CHECKREG r4, 0x00000059; -CHECKREG r5, 0x00000059; -CHECKREG r6, 0x00000059; -CHECKREG r7, 0x00000059; - -imm32 r0, 0x10789abc; -imm32 r1, 0x11345678; -imm32 r2, 0x93156789; -imm32 r3, 0xd451789a; -imm32 r4, 0x856719ab; -imm32 r5, 0x267891bc; -imm32 r6, 0xa789ab1d; -imm32 r7, 0x989ab1de; -R0 = R2.B (X); -R1 = R2.B (X); -R3 = R2.B (X); -R4 = R2.B (X); -R5 = R2.B (X); -R6 = R2.B (X); -R7 = R2.B (X); -R2 = R2.B (X); -CHECKREG r0, 0xFFFFFF89; -CHECKREG r1, 0xFFFFFF89; -CHECKREG r2, 0xFFFFFF89; -CHECKREG r3, 0xFFFFFF89; -CHECKREG r4, 0xFFFFFF89; -CHECKREG r5, 0xFFFFFF89; -CHECKREG r6, 0xFFFFFF89; -CHECKREG r7, 0xFFFFFF89; - -imm32 r0, 0x21230002; -imm32 r1, 0x02374659; -imm32 r2, 0x93256789; -imm32 r3, 0xa952789a; -imm32 r4, 0xb59729ab; -imm32 r5, 0xc67992bc; -imm32 r6, 0xd7899b2d; -imm32 r7, 0xe89ab9d2; -R0 = R3.B (X); -R1 = R3.B (X); -R2 = R3.B (X); -R4 = R3.B (X); -R5 = R3.B (X); -R6 = R3.B (X); -R7 = R3.B (X); -R3 = R3.B (X); -CHECKREG r0, 0xFFFFFF9A; -CHECKREG r1, 0xFFFFFF9A; -CHECKREG r2, 0xFFFFFF9A; -CHECKREG r3, 0xFFFFFF9A; -CHECKREG r4, 0xFFFFFF9A; -CHECKREG r5, 0xFFFFFF9A; -CHECKREG r6, 0xFFFFFF9A; -CHECKREG r7, 0xFFFFFF9A; - -imm32 r0, 0xa0789abc; -imm32 r1, 0x1a345678; -imm32 r2, 0x23a56789; -imm32 r3, 0x645a789a; -imm32 r4, 0x8667a9ab; -imm32 r5, 0x96689abc; -imm32 r6, 0xa787abad; -imm32 r7, 0xb89a7cda; -R0 = R4.B (X); -R1 = R4.B (X); -R2 = R4.B (X); -R3 = R4.B (X); -R4 = R4.B (X); -R5 = R4.B (X); -R6 = R4.B (X); -R7 = R4.B (X); -CHECKREG r0, 0xFFFFFFAB; -CHECKREG r1, 0xFFFFFFAB; -CHECKREG r2, 0xFFFFFFAB; -CHECKREG r3, 0xFFFFFFAB; -CHECKREG r4, 0xFFFFFFAB; -CHECKREG r5, 0xFFFFFFAB; -CHECKREG r6, 0xFFFFFFAB; -CHECKREG r7, 0xFFFFFFAB; - -imm32 r0, 0xf1230002; -imm32 r1, 0x0f374659; -imm32 r2, 0x93f56789; -imm32 r3, 0xa45f789a; -imm32 r4, 0xb567f9ab; -imm32 r5, 0xc6789fbc; -imm32 r6, 0xd789abfd; -imm32 r7, 0xe89abcdf; -R0 = R5.B (X); -R1 = R5.B (X); -R2 = R5.B (X); -R3 = R5.B (X); -R4 = R5.B (X); -R6 = R5.B (X); -R7 = R5.B (X); -R5 = R5.B (X); -CHECKREG r0, 0xFFFFFFBC; -CHECKREG r1, 0xFFFFFFBC; -CHECKREG r2, 0xFFFFFFBC; -CHECKREG r3, 0xFFFFFFBC; -CHECKREG r4, 0xFFFFFFBC; -CHECKREG r5, 0xFFFFFFBC; -CHECKREG r6, 0xFFFFFFBC; -CHECKREG r7, 0xFFFFFFBC; - -imm32 r0, 0xe0789abc; -imm32 r1, 0xe2345678; -imm32 r2, 0x2e456789; -imm32 r3, 0x34e6789a; -imm32 r4, 0x856e89ab; -imm32 r5, 0x9678eabc; -imm32 r6, 0xa789aecd; -imm32 r7, 0xb89abcee; -R0 = R6.B (X); -R1 = R6.B (X); -R2 = R6.B (X); -R3 = R6.B (X); -R4 = R6.B (X); -R5 = R6.B (X); -R7 = R6.B (X); -R6 = R6.B (X); -CHECKREG r0, 0xFFFFFFCD; -CHECKREG r1, 0xFFFFFFCD; -CHECKREG r2, 0xFFFFFFCD; -CHECKREG r3, 0xFFFFFFCD; -CHECKREG r4, 0xFFFFFFCD; -CHECKREG r5, 0xFFFFFFCD; -CHECKREG r6, 0xFFFFFFCD; -CHECKREG r7, 0xFFFFFFCD; - -imm32 r0, 0x012300f5; -imm32 r1, 0x80374659; -imm32 r2, 0x98456589; -imm32 r3, 0xa486589a; -imm32 r4, 0xb56589ab; -imm32 r5, 0xc6588abc; -imm32 r6, 0xd589a8cd; -imm32 r7, 0x589abc88; -R0 = R7.B (X); -R1 = R7.B (X); -R2 = R7.B (X); -R3 = R7.B (X); -R4 = R7.B (X); -R5 = R7.B (X); -R6 = R7.B (X); -R7 = R7.B (X); -CHECKREG r0, 0xFFFFFF88; -CHECKREG r1, 0xFFFFFF88; -CHECKREG r2, 0xFFFFFF88; -CHECKREG r3, 0xFFFFFF88; -CHECKREG r4, 0xFFFFFF88; -CHECKREG r5, 0xFFFFFF88; -CHECKREG r6, 0xFFFFFF88; -CHECKREG r7, 0xFFFFFF88; - - -pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_xh.s b/sim/testsuite/sim/bfin/c_alu2op_conv_xh.s deleted file mode 100644 index 75b06c0..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_conv_xh.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_alu2op_conv_xh/c_alu2op_conv_xh.dsp -// Spec Reference: alu2op convert xh -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x00789abc; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x856789ab; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R0 = R0.L (X); -R1 = R0.L (X); -R2 = R0.L (X); -R3 = R0.L (X); -R4 = R0.L (X); -R5 = R0.L (X); -R6 = R0.L (X); -R7 = R0.L (X); -CHECKREG r0, 0xFFFF9ABC; -CHECKREG r1, 0xFFFF9ABC; -CHECKREG r2, 0xFFFF9ABC; -CHECKREG r3, 0xFFFF9ABC; -CHECKREG r4, 0xFFFF9ABC; -CHECKREG r5, 0xFFFF9ABC; -CHECKREG r6, 0xFFFF9ABC; -CHECKREG r7, 0xFFFF9ABC; - -imm32 r0, 0x01230002; -imm32 r1, 0x00374659; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R0 = R1.L (X); -R2 = R1.L (X); -R3 = R1.L (X); -R4 = R1.L (X); -R5 = R1.L (X); -R6 = R1.L (X); -R7 = R1.L (X); -R1 = R1.L (X); -CHECKREG r0, 0x00004659; -CHECKREG r1, 0x00004659; -CHECKREG r2, 0x00004659; -CHECKREG r3, 0x00004659; -CHECKREG r4, 0x00004659; -CHECKREG r5, 0x00004659; -CHECKREG r6, 0x00004659; -CHECKREG r7, 0x00004659; - -imm32 r0, 0x10789abc; -imm32 r1, 0x11345678; -imm32 r2, 0x93156789; -imm32 r3, 0xd451789a; -imm32 r4, 0x856719ab; -imm32 r5, 0x267891bc; -imm32 r6, 0xa789ab1d; -imm32 r7, 0x989ab1de; -R0 = R2.L (X); -R1 = R2.L (X); -R3 = R2.L (X); -R4 = R2.L (X); -R5 = R2.L (X); -R6 = R2.L (X); -R7 = R2.L (X); -R2 = R2.L (X); -CHECKREG r0, 0x00006789; -CHECKREG r1, 0x00006789; -CHECKREG r2, 0x00006789; -CHECKREG r3, 0x00006789; -CHECKREG r4, 0x00006789; -CHECKREG r5, 0x00006789; -CHECKREG r6, 0x00006789; -CHECKREG r7, 0x00006789; - -imm32 r0, 0x21230002; -imm32 r1, 0x02374659; -imm32 r2, 0x93256789; -imm32 r3, 0xa952789a; -imm32 r4, 0xb59729ab; -imm32 r5, 0xc67992bc; -imm32 r6, 0xd7899b2d; -imm32 r7, 0xe89ab9d2; -R0 = R3.L (X); -R1 = R3.L (X); -R2 = R3.L (X); -R4 = R3.L (X); -R5 = R3.L (X); -R6 = R3.L (X); -R7 = R3.L (X); -R3 = R3.L (X); -CHECKREG r0, 0x0000789A; -CHECKREG r1, 0x0000789A; -CHECKREG r2, 0x0000789A; -CHECKREG r3, 0x0000789A; -CHECKREG r4, 0x0000789A; -CHECKREG r5, 0x0000789A; -CHECKREG r6, 0x0000789A; -CHECKREG r7, 0x0000789A; - -imm32 r0, 0xa0789abc; -imm32 r1, 0x1a345678; -imm32 r2, 0x23a56789; -imm32 r3, 0x645a789a; -imm32 r4, 0x8667a9ab; -imm32 r5, 0x96689abc; -imm32 r6, 0xa787abad; -imm32 r7, 0xb89a7cda; -R0 = R4.L (X); -R1 = R4.L (X); -R2 = R4.L (X); -R3 = R4.L (X); -R4 = R4.L (X); -R5 = R4.L (X); -R6 = R4.L (X); -R7 = R4.L (X); -CHECKREG r0, 0xFFFFA9AB; -CHECKREG r1, 0xFFFFA9AB; -CHECKREG r2, 0xFFFFA9AB; -CHECKREG r3, 0xFFFFA9AB; -CHECKREG r4, 0xFFFFA9AB; -CHECKREG r5, 0xFFFFA9AB; -CHECKREG r6, 0xFFFFA9AB; -CHECKREG r7, 0xFFFFA9AB; - -imm32 r0, 0xf1230002; -imm32 r1, 0x0f374659; -imm32 r2, 0x93f56789; -imm32 r3, 0xa45f789a; -imm32 r4, 0xb567f9ab; -imm32 r5, 0xc6789fbc; -imm32 r6, 0xd789abfd; -imm32 r7, 0xe89abcdf; -R0 = R5.L (X); -R1 = R5.L (X); -R2 = R5.L (X); -R3 = R5.L (X); -R4 = R5.L (X); -R6 = R5.L (X); -R7 = R5.L (X); -R5 = R5.L (X); -CHECKREG r0, 0xFFFF9FBC; -CHECKREG r1, 0xFFFF9FBC; -CHECKREG r2, 0xFFFF9FBC; -CHECKREG r3, 0xFFFF9FBC; -CHECKREG r4, 0xFFFF9FBC; -CHECKREG r5, 0xFFFF9FBC; -CHECKREG r6, 0xFFFF9FBC; -CHECKREG r7, 0xFFFF9FBC; - -imm32 r0, 0xe0789abc; -imm32 r1, 0xe2345678; -imm32 r2, 0x2e456789; -imm32 r3, 0x34e6789a; -imm32 r4, 0x856e89ab; -imm32 r5, 0x9678eabc; -imm32 r6, 0xa789aecd; -imm32 r7, 0xb89abcee; -R0 = R6.L (X); -R1 = R6.L (X); -R2 = R6.L (X); -R3 = R6.L (X); -R4 = R6.L (X); -R5 = R6.L (X); -R7 = R6.L (X); -R6 = R6.L (X); -CHECKREG r0, 0xFFFFAECD; -CHECKREG r1, 0xFFFFAECD; -CHECKREG r2, 0xFFFFAECD; -CHECKREG r3, 0xFFFFAECD; -CHECKREG r4, 0xFFFFAECD; -CHECKREG r5, 0xFFFFAECD; -CHECKREG r6, 0xFFFFAECD; -CHECKREG r7, 0xFFFFAECD; - -imm32 r0, 0x012300f5; -imm32 r1, 0x80374659; -imm32 r2, 0x98456589; -imm32 r3, 0xa486589a; -imm32 r4, 0xb56589ab; -imm32 r5, 0xc6588abc; -imm32 r6, 0xd589a8cd; -imm32 r7, 0x589abc88; -R0 = R7.L (X); -R1 = R7.L (X); -R2 = R7.L (X); -R3 = R7.L (X); -R4 = R7.L (X); -R5 = R7.L (X); -R6 = R7.L (X); -R7 = R7.L (X); -CHECKREG r0, 0xFFFFBC88; -CHECKREG r1, 0xFFFFBC88; -CHECKREG r2, 0xFFFFBC88; -CHECKREG r3, 0xFFFFBC88; -CHECKREG r4, 0xFFFFBC88; -CHECKREG r5, 0xFFFFBC88; -CHECKREG r6, 0xFFFFBC88; -CHECKREG r7, 0xFFFFBC88; - - -pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_divq.s b/sim/testsuite/sim/bfin/c_alu2op_divq.s deleted file mode 100644 index 2a03227..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_divq.s +++ /dev/null @@ -1,220 +0,0 @@ -//Original:/testcases/core/c_alu2op_divq/c_alu2op_divq.dsp -// Spec Reference: alu2op divide q -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x856789ab; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R0.L = 1; -DIVQ ( R1 , R0 ); -DIVQ ( R2 , R0 ); -DIVQ ( R3 , R0 ); -DIVQ ( R4 , R0 ); -DIVQ ( R5 , R0 ); -DIVQ ( R6 , R0 ); -DIVQ ( R7 , R0 ); -DIVQ ( R4 , R0 ); -DIVQ ( R0 , R0 ); -CHECKREG r1, 0x2466ACF1; -CHECKREG r2, 0x4688CF13; -CHECKREG r3, 0x68AAF135; -CHECKREG r4, 0x159C26AD; -CHECKREG r5, 0x2CF33578; -CHECKREG r6, 0x4F15579A; -CHECKREG r7, 0x713779BC; -CHECKREG r0, 0xFFFE0002; - -imm32 r0, 0x01230002; -imm32 r1, 0x00000000; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R1.L = -1; -DIVQ ( R0 , R1 ); -DIVQ ( R2 , R1 ); -DIVQ ( R3 , R1 ); -DIVQ ( R4 , R1 ); -DIVQ ( R5 , R1 ); -DIVQ ( R6 , R1 ); -DIVQ ( R7 , R1 ); -DIVQ ( R1 , R1 ); -CHECKREG r0, 0x02440004; -CHECKREG r1, 0x0003FFFE; -CHECKREG r2, 0x2688CF13; -CHECKREG r3, 0x48AEF135; -CHECKREG r4, 0x6AD11357; -CHECKREG r5, 0x8CF33579; -CHECKREG r6, 0xAF15579B; -CHECKREG r7, 0xD13779BD; - -imm32 r0, 0x51230002; -imm32 r1, 0x12345678; -imm32 r2, 0x00000000; -imm32 r3, 0x3456789a; -imm32 r4, 0x956789ab; -imm32 r5, 0x86789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R2.L = 31; -DIVQ ( R0 , R2 ); -DIVQ ( R1 , R2 ); -DIVQ ( R3 , R2 ); -DIVQ ( R4 , R2 ); -DIVQ ( R5 , R2 ); -DIVQ ( R6 , R2 ); -DIVQ ( R7 , R2 ); -DIVQ ( R2 , R2 ); -CHECKREG r0, 0xA2840005; -CHECKREG r1, 0x242AACF1; -CHECKREG r2, 0xFFC2003E; -CHECKREG r3, 0x686EF135; -CHECKREG r4, 0x2A911356; -CHECKREG r5, 0x0D2F3578; -CHECKREG r6, 0xCF51579B; -CHECKREG r7, 0xF0F779BD; - -imm32 r0, 0x01230002; -imm32 r1, 0x82345678; -imm32 r2, 0x93456789; -imm32 r3, 0x00000000; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R3.L = -31; -DIVQ ( R0 , R3 ); -DIVQ ( R1 , R3 ); -DIVQ ( R2 , R3 ); -DIVQ ( R4 , R3 ); -DIVQ ( R5 , R3 ); -DIVQ ( R6 , R3 ); -DIVQ ( R7 , R3 ); -DIVQ ( R3 , R3 ); -CHECKREG r0, 0x02080004; -CHECKREG r1, 0x042AACF1; -CHECKREG r2, 0x26C8CF13; -CHECKREG r3, 0x003FFFC2; -CHECKREG r4, 0x6B0D1357; -CHECKREG r5, 0x8D2F3579; -CHECKREG r6, 0xAF51579B; -CHECKREG r7, 0xD17379BD; - -imm32 r0, 0x00000001; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x00000000; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R4.L = 15; -DIVQ ( R1 , R4 ); -DIVQ ( R2 , R4 ); -DIVQ ( R3 , R4 ); -DIVQ ( R0 , R4 ); -DIVQ ( R5 , R4 ); -DIVQ ( R6 , R4 ); -DIVQ ( R7 , R4 ); -DIVQ ( R4 , R4 ); -CHECKREG r0, 0xFFE20002; -CHECKREG r1, 0x2486ACF1; -CHECKREG r2, 0x466CCF13; -CHECKREG r3, 0x688EF135; -CHECKREG r4, 0x001E001F; -CHECKREG r5, 0x2D0F3578; -CHECKREG r6, 0x4F31579A; -CHECKREG r7, 0x715379BC; - -imm32 r0, 0x01230002; -imm32 r1, 0x00000000; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0x00000000; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R5.L = -15; -DIVQ ( R0 , R5 ); -DIVQ ( R1 , R5 ); -DIVQ ( R2 , R5 ); -DIVQ ( R3 , R5 ); -DIVQ ( R4 , R5 ); -DIVQ ( R6 , R5 ); -DIVQ ( R7 , R5 ); -DIVQ ( R5 , R5 ); -CHECKREG r0, 0x02640004; -CHECKREG r1, 0xFFE20001; -CHECKREG r2, 0x26A8CF13; -CHECKREG r3, 0x48CAF135; -CHECKREG r4, 0x6AED1357; -CHECKREG r5, 0x001FFFE2; -CHECKREG r6, 0xAF31579B; -CHECKREG r7, 0xD15379BD; - -imm32 r0, 0x51230002; -imm32 r1, 0x12345678; -imm32 r2, 0xb1256790; -imm32 r3, 0x3456789a; -imm32 r4, 0x956789ab; -imm32 r5, 0x86789abc; -imm32 r6, 0x00000000; -imm32 r7, 0x789abcde; -R6.L = 24; -DIVQ ( R0 , R6 ); -DIVQ ( R1 , R6 ); -DIVQ ( R2 , R6 ); -DIVQ ( R3 , R6 ); -DIVQ ( R4 , R6 ); -DIVQ ( R5 , R6 ); -DIVQ ( R7 , R6 ); -DIVQ ( R6 , R6 ); -CHECKREG r0, 0xA2760005; -CHECKREG r1, 0x2438ACF1; -CHECKREG r2, 0x621ACF20; -CHECKREG r3, 0x68DCF135; -CHECKREG r4, 0x2A9F1356; -CHECKREG r5, 0x0D213578; -CHECKREG r6, 0xFFD00030; -CHECKREG r7, 0xF16579BD; - -imm32 r0, 0x01230002; -imm32 r1, 0x82345678; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0x00000000; -R7.L = -24; -DIVQ ( R0 , R7 ); -DIVQ ( R1 , R7 ); -DIVQ ( R2 , R7 ); -DIVQ ( R3 , R7 ); -DIVQ ( R4 , R7 ); -DIVQ ( R5 , R7 ); -DIVQ ( R6 , R7 ); -DIVQ ( R7 , R7 ); -CHECKREG r0, 0x02160004; -CHECKREG r1, 0x0438ACF1; -CHECKREG r2, 0x26BACF13; -CHECKREG r3, 0x48DCF135; -CHECKREG r4, 0x6AFF1357; -CHECKREG r5, 0x8D213579; -CHECKREG r6, 0xAF43579B; -CHECKREG r7, 0x0031FFD0; - - -pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_divs.s b/sim/testsuite/sim/bfin/c_alu2op_divs.s deleted file mode 100644 index f0fc091..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_divs.s +++ /dev/null @@ -1,220 +0,0 @@ -//Original:/testcases/core/c_alu2op_divs/c_alu2op_divs.dsp -// Spec Reference: alu2op divide s -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x856789ab; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R0.L = 1; -DIVS ( R1 , R0 ); -DIVS ( R2 , R0 ); -DIVS ( R3 , R0 ); -DIVS ( R4 , R0 ); -DIVS ( R5 , R0 ); -DIVS ( R6 , R0 ); -DIVS ( R7 , R0 ); -DIVS ( R4 , R0 ); -DIVS ( R0 , R0 ); -CHECKREG r1, 0x2468ACF0; -CHECKREG r2, 0x468ACF12; -CHECKREG r3, 0x68ACF134; -CHECKREG r4, 0x159E26AE; -CHECKREG r5, 0x2CF13579; -CHECKREG r6, 0x4F13579B; -CHECKREG r7, 0x713579BD; -CHECKREG r0, 0x00000002; - -imm32 r0, 0x01230002; -imm32 r1, 0x00000000; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R1.L = -1; -DIVS ( R0 , R1 ); -DIVS ( R2 , R1 ); -DIVS ( R3 , R1 ); -DIVS ( R4 , R1 ); -DIVS ( R5 , R1 ); -DIVS ( R6 , R1 ); -DIVS ( R7 , R1 ); -DIVS ( R1 , R1 ); -CHECKREG r0, 0x02460005; -CHECKREG r1, 0x0001FFFF; -CHECKREG r2, 0x268ACF12; -CHECKREG r3, 0x48ACF134; -CHECKREG r4, 0x6ACF1356; -CHECKREG r5, 0x8CF13578; -CHECKREG r6, 0xAF13579A; -CHECKREG r7, 0xD13579BC; - -imm32 r0, 0x51230002; -imm32 r1, 0x12345678; -imm32 r2, 0x00000000; -imm32 r3, 0x3456789a; -imm32 r4, 0x956789ab; -imm32 r5, 0x86789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R2.L = 31; -DIVS ( R0 , R2 ); -DIVS ( R1 , R2 ); -DIVS ( R3 , R2 ); -DIVS ( R4 , R2 ); -DIVS ( R5 , R2 ); -DIVS ( R6 , R2 ); -DIVS ( R7 , R2 ); -DIVS ( R2 , R2 ); -CHECKREG r0, 0xA2460004; -CHECKREG r1, 0x2468ACF0; -CHECKREG r2, 0x0000003E; -CHECKREG r3, 0x68ACF134; -CHECKREG r4, 0x2ACF1357; -CHECKREG r5, 0x0CF13579; -CHECKREG r6, 0xCF13579A; -CHECKREG r7, 0xF13579BC; - -imm32 r0, 0x01230002; -imm32 r1, 0x82345678; -imm32 r2, 0x93456789; -imm32 r3, 0x00000000; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R3.L = -31; -DIVS ( R0 , R3 ); -DIVS ( R1 , R3 ); -DIVS ( R2 , R3 ); -DIVS ( R4 , R3 ); -DIVS ( R5 , R3 ); -DIVS ( R6 , R3 ); -DIVS ( R7 , R3 ); -DIVS ( R3 , R3 ); -CHECKREG r0, 0x02460005; -CHECKREG r1, 0x0468ACF0; -CHECKREG r2, 0x268ACF12; -CHECKREG r3, 0x0001FFC3; -CHECKREG r4, 0x6ACF1356; -CHECKREG r5, 0x8CF13578; -CHECKREG r6, 0xAF13579A; -CHECKREG r7, 0xD13579BC; - -imm32 r0, 0x00000001; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x00000000; -imm32 r5, 0x96789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb89abcde; -R4.L = 15; -DIVS ( R1 , R4 ); -DIVS ( R2 , R4 ); -DIVS ( R3 , R4 ); -DIVS ( R0 , R4 ); -DIVS ( R5 , R4 ); -DIVS ( R6 , R4 ); -DIVS ( R7 , R4 ); -DIVS ( R4 , R4 ); -CHECKREG r0, 0x00000002; -CHECKREG r1, 0x2468ACF0; -CHECKREG r2, 0x468ACF12; -CHECKREG r3, 0x68ACF134; -CHECKREG r4, 0x0000001E; -CHECKREG r5, 0x2CF13579; -CHECKREG r6, 0x4F13579B; -CHECKREG r7, 0x713579BD; - -imm32 r0, 0x01230002; -imm32 r1, 0x00000000; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0x00000000; -imm32 r6, 0xd789abcd; -imm32 r7, 0xe89abcde; -R5.L = -15; -DIVS ( R0 , R5 ); -DIVS ( R1 , R5 ); -DIVS ( R2 , R5 ); -DIVS ( R3 , R5 ); -DIVS ( R4 , R5 ); -DIVS ( R6 , R5 ); -DIVS ( R7 , R5 ); -DIVS ( R5 , R5 ); -CHECKREG r0, 0x02460005; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x268ACF12; -CHECKREG r3, 0x48ACF134; -CHECKREG r4, 0x6ACF1356; -CHECKREG r5, 0x0001FFE3; -CHECKREG r6, 0xAF13579A; -CHECKREG r7, 0xD13579BC; - -imm32 r0, 0x51230002; -imm32 r1, 0x12345678; -imm32 r2, 0xb1256790; -imm32 r3, 0x3456789a; -imm32 r4, 0x956789ab; -imm32 r5, 0x86789abc; -imm32 r6, 0x00000000; -imm32 r7, 0x789abcde; -R6.L = 24; -DIVS ( R0 , R6 ); -DIVS ( R1 , R6 ); -DIVS ( R2 , R6 ); -DIVS ( R3 , R6 ); -DIVS ( R4 , R6 ); -DIVS ( R5 , R6 ); -DIVS ( R7 , R6 ); -DIVS ( R6 , R6 ); -CHECKREG r0, 0xA2460004; -CHECKREG r1, 0x2468ACF0; -CHECKREG r2, 0x624ACF21; -CHECKREG r3, 0x68ACF134; -CHECKREG r4, 0x2ACF1357; -CHECKREG r5, 0x0CF13579; -CHECKREG r6, 0x00000030; -CHECKREG r7, 0xF13579BC; - -imm32 r0, 0x01230002; -imm32 r1, 0x82345678; -imm32 r2, 0x93456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0x00000000; -R7.L = -24; -DIVS ( R0 , R7 ); -DIVS ( R1 , R7 ); -DIVS ( R2 , R7 ); -DIVS ( R3 , R7 ); -DIVS ( R4 , R7 ); -DIVS ( R5 , R7 ); -DIVS ( R6 , R7 ); -DIVS ( R7 , R7 ); -CHECKREG r0, 0x02460005; -CHECKREG r1, 0x0468ACF0; -CHECKREG r2, 0x268ACF12; -CHECKREG r3, 0x48ACF134; -CHECKREG r4, 0x6ACF1356; -CHECKREG r5, 0x8CF13578; -CHECKREG r6, 0xAF13579A; -CHECKREG r7, 0x0001FFD1; - - -pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_log_l_sft.s b/sim/testsuite/sim/bfin/c_alu2op_log_l_sft.s deleted file mode 100644 index 06489ef..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_log_l_sft.s +++ /dev/null @@ -1,220 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_alu2op_log_l_sft/c_alu2op_log_l_sft.dsp -// Spec Reference: alu2op logical left -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - imm32 r0, 0x00000000; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x856789ab; - imm32 r5, 0x96789abc; - imm32 r6, 0xa789abcd; - imm32 r7, 0xb89abcde; - R0.L = 1; - R1 <<= R0; - R2 <<= R0; - R3 <<= R0; - R4 <<= R0; - R5 <<= R0; - R6 <<= R0; - R7 <<= R0; - R4 <<= R0; - R0 <<= R0; - CHECKREG r1, 0x2468ACF0; - CHECKREG r2, 0x468ACF12; - CHECKREG r3, 0x68ACF134; - CHECKREG r4, 0x159E26AC; - CHECKREG r5, 0x2CF13578; - CHECKREG r6, 0x4F13579A; - CHECKREG r7, 0x713579BC; - CHECKREG r0, 0x00000002; - - imm32 r0, 0x01230002; - imm32 r1, 0x00000000; - imm32 r2, 0x93456789; - imm32 r3, 0xa456789a; - imm32 r4, 0xb56789ab; - imm32 r5, 0xc6789abc; - imm32 r6, 0xd789abcd; - imm32 r7, 0xe89abcde; - R1.L = -1; - R0 <<= R1; - R2 <<= R1; - R3 <<= R1; - R4 <<= R1; - R5 <<= R1; - R6 <<= R1; - R7 <<= R1; - R1 <<= R1; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000000; - - imm32 r0, 0x51230002; - imm32 r1, 0x12345678; - imm32 r2, 0x00000000; - imm32 r3, 0x3456789a; - imm32 r4, 0x956789ab; - imm32 r5, 0x86789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R2.L = 31; - R0 <<= R2; - R1 <<= R2; - R3 <<= R2; - R4 <<= R2; - R5 <<= R2; - R6 <<= R2; - R7 <<= R2; - R2 <<= R2; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x80000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x80000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x80000000; - CHECKREG r7, 0x00000000; - - imm32 r0, 0x01230002; - imm32 r1, 0x82345678; - imm32 r2, 0x93456789; - imm32 r3, 0x00000000; - imm32 r4, 0xb56789ab; - imm32 r5, 0xc6789abc; - imm32 r6, 0xd789abcd; - imm32 r7, 0xe89abcde; - R3.L = -31; - R0 <<= R3; - R1 <<= R3; - R2 <<= R3; - R4 <<= R3; - R5 <<= R3; - R6 <<= R3; - R7 <<= R3; - R3 <<= R3; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000000; - - imm32 r0, 0x00000001; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x00000000; - imm32 r5, 0x96789abc; - imm32 r6, 0xa789abcd; - imm32 r7, 0xb89abcde; - R4.L = 15; - R1 <<= R4; - R2 <<= R4; - R3 <<= R4; - R0 <<= R4; - R5 <<= R4; - R6 <<= R4; - R7 <<= R4; - R4 <<= R4; - CHECKREG r0, 0x00008000; - CHECKREG r1, 0x2B3C0000; - CHECKREG r2, 0xB3C48000; - CHECKREG r3, 0x3C4D0000; - CHECKREG r4, 0x00078000; - CHECKREG r5, 0x4D5E0000; - CHECKREG r6, 0xD5E68000; - CHECKREG r7, 0x5E6F0000; - - imm32 r0, 0x01230002; - imm32 r1, 0x00000000; - imm32 r2, 0x93456789; - imm32 r3, 0xa456789a; - imm32 r4, 0xb56789ab; - imm32 r5, 0x00000000; - imm32 r6, 0xd789abcd; - imm32 r7, 0xe89abcde; - R5.L = -15; - R0 <<= R5; - R1 <<= R5; - R2 <<= R5; - R3 <<= R5; - R4 <<= R5; - R6 <<= R5; - R7 <<= R5; - R5 <<= R5; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000000; - - imm32 r0, 0x51230002; - imm32 r1, 0x12345678; - imm32 r2, 0xb1256790; - imm32 r3, 0x3456789a; - imm32 r4, 0x956789ab; - imm32 r5, 0x86789abc; - imm32 r6, 0x00000000; - imm32 r7, 0x789abcde; - R6.L = 24; - R0 <<= R6; - R1 <<= R6; - R2 <<= R6; - R3 <<= R6; - R4 <<= R6; - R5 <<= R6; - R7 <<= R6; - R6 <<= R6; - CHECKREG r0, 0x02000000; - CHECKREG r1, 0x78000000; - CHECKREG r2, 0x90000000; - CHECKREG r3, 0x9A000000; - CHECKREG r4, 0xAB000000; - CHECKREG r5, 0xBC000000; - CHECKREG r6, 0x18000000; - CHECKREG r7, 0xDE000000; - - imm32 r0, 0x01230002; - imm32 r1, 0x82345678; - imm32 r2, 0x93456789; - imm32 r3, 0xa456789a; - imm32 r4, 0xb56789ab; - imm32 r5, 0xc6789abc; - imm32 r6, 0xd789abcd; - imm32 r7, 0x00000000; - R7.L = -24; - R0 <<= R7; - R1 <<= R7; - R2 <<= R7; - R3 <<= R7; - R4 <<= R7; - R5 <<= R7; - R6 <<= R7; - R7 <<= R7; - CHECKREG r0, 0x00; - CHECKREG r1, 0x00; - CHECKREG r2, 0x00; - CHECKREG r3, 0x00; - CHECKREG r4, 0x00; - CHECKREG r5, 0x00; - CHECKREG r6, 0x00; - CHECKREG r7, 0x00; - - pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_log_r_sft.s b/sim/testsuite/sim/bfin/c_alu2op_log_r_sft.s deleted file mode 100644 index fdb14fc..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_log_r_sft.s +++ /dev/null @@ -1,217 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_alu2op_log_r_sft/c_alu2op_log_r_sft.dsp -// Spec Reference: alu2op logical right -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x00000000; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x856789ab; - imm32 r5, 0x96789abc; - imm32 r6, 0xa789abcd; - imm32 r7, 0xb89abcde; - R0.L = 1; - R1 >>= R0; - R2 >>= R0; - R3 >>= R0; - R4 >>= R0; - R5 >>= R0; - R6 >>= R0; - R7 >>= R0; - R4 >>= R0; - R0 >>= R0; - CHECKREG r1, 0x091A2B3C; - CHECKREG r2, 0x11A2B3C4; - CHECKREG r3, 0x1A2B3C4D; - CHECKREG r4, 0x2159E26A; - CHECKREG r5, 0x4B3C4D5E; - CHECKREG r6, 0x53C4D5E6; - CHECKREG r7, 0x5C4D5E6F; - CHECKREG r0, 0x00000000; - - imm32 r0, 0x01230002; - imm32 r1, 0x00000000; - imm32 r2, 0x93456789; - imm32 r3, 0xa456789a; - imm32 r4, 0xb56789ab; - imm32 r5, 0xc6789abc; - imm32 r6, 0xd789abcd; - imm32 r7, 0xe89abcde; - R1.L = -1; - R0 >>= R1; - R2 >>= R1; - R3 >>= R1; - R4 >>= R1; - R5 >>= R1; - R6 >>= R1; - R7 >>= R1; - R1 >>= R1; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000000; - - imm32 r0, 0x51230002; - imm32 r1, 0x12345678; - imm32 r2, 0x00000000; - imm32 r3, 0x3456789a; - imm32 r4, 0x956789ab; - imm32 r5, 0x86789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R2.L = 31; - R0 >>= R2; - R1 >>= R2; - R3 >>= R2; - R4 >>= R2; - R5 >>= R2; - R6 >>= R2; - R7 >>= R2; - R2 >>= R2; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000001; - CHECKREG r5, 0x00000001; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000000; - - imm32 r0, 0x01230002; - imm32 r1, 0x82345678; - imm32 r2, 0x93456789; - imm32 r3, 0x00000000; - imm32 r4, 0xb56789ab; - imm32 r5, 0xc6789abc; - imm32 r6, 0xd789abcd; - imm32 r7, 0xe89abcde; - R3.L = -31; - R0 >>= R3; - R1 >>= R3; - R2 >>= R3; - R4 >>= R3; - R5 >>= R3; - R6 >>= R3; - R7 >>= R3; - R3 >>= R3; - CHECKREG r0, 0x00; - CHECKREG r1, 0x0; - CHECKREG r2, 0x0; - CHECKREG r3, 0x0; - CHECKREG r4, 0x0; - CHECKREG r5, 0x0; - CHECKREG r6, 0x0; - CHECKREG r7, 0x0; - - imm32 r0, 0x00000001; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x00000000; - imm32 r5, 0x96789abc; - imm32 r6, 0xa789abcd; - imm32 r7, 0xb89abcde; - R4.L = 15; - R1 >>= R4; - R2 >>= R4; - R3 >>= R4; - R0 >>= R4; - R5 >>= R4; - R6 >>= R4; - R7 >>= R4; - R4 >>= R4; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00002468; - CHECKREG r2, 0x0000468A; - CHECKREG r3, 0x000068AC; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00012CF1; - CHECKREG r6, 0x00014F13; - CHECKREG r7, 0x00017135; - - imm32 r0, 0x01230002; - imm32 r1, 0x00000000; - imm32 r2, 0x93456789; - imm32 r3, 0xa456789a; - imm32 r4, 0xb56789ab; - imm32 r5, 0x00000000; - imm32 r6, 0xd789abcd; - imm32 r7, 0xe89abcde; - R5.L = -15; - R0 >>= R5; - R1 >>= R5; - R2 >>= R5; - R3 >>= R5; - R4 >>= R5; - R6 >>= R5; - R7 >>= R5; - R5 >>= R5; - CHECKREG r0, 0x000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x0000; - CHECKREG r3, 0x0000; - CHECKREG r4, 0x0000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x0000; - CHECKREG r7, 0x0000; - - imm32 r0, 0x51230002; - imm32 r1, 0x12345678; - imm32 r2, 0xb1256790; - imm32 r3, 0x3456789a; - imm32 r4, 0x956789ab; - imm32 r5, 0x86789abc; - imm32 r6, 0x00000000; - imm32 r7, 0x789abcde; - R6.L = 24; - R0 >>= R6; - R1 >>= R6; - R2 >>= R6; - R3 >>= R6; - R4 >>= R6; - R5 >>= R6; - R7 >>= R6; - R6 >>= R6; - CHECKREG r0, 0x00000051; - CHECKREG r1, 0x00000012; - CHECKREG r2, 0x000000B1; - CHECKREG r3, 0x00000034; - CHECKREG r4, 0x00000095; - CHECKREG r5, 0x00000086; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000078; - - imm32 r0, 0x01230002; - imm32 r1, 0x82345678; - imm32 r2, 0x93456789; - imm32 r3, 0xa456789a; - imm32 r4, 0xb56789ab; - imm32 r5, 0xc6789abc; - imm32 r6, 0xd789abcd; - imm32 r7, 0x00000000; - R7.L = -24; - R0 >>= R7; - R1 >>= R7; - R2 >>= R7; - R3 >>= R7; - R4 >>= R7; - R5 >>= R7; - R6 >>= R7; - R7 >>= R7; - CHECKREG r0, 0x00; - CHECKREG r1, 0x00; - CHECKREG r2, 0x00; - CHECKREG r3, 0x00; - CHECKREG r4, 0x00; - CHECKREG r5, 0x00; - CHECKREG r6, 0x00; - CHECKREG r7, 0x00; - - pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_shadd_1.s b/sim/testsuite/sim/bfin/c_alu2op_shadd_1.s deleted file mode 100644 index 73e39ec..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_shadd_1.s +++ /dev/null @@ -1,209 +0,0 @@ -//Original:/testcases/core/c_alu2op_shadd_1/c_alu2op_shadd_1.dsp -// Spec Reference: alu2op shadd 1 -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x03417990; -imm32 r1, 0x12315678; -imm32 r2, 0x23416789; -imm32 r3, 0x3451789a; -imm32 r4, 0x856189ab; -imm32 r5, 0x96719abc; -imm32 r6, 0xa781abcd; -imm32 r7, 0xb891bcde; -R1 = ( R1 + R0 ) << 1; -R2 = ( R2 + R0 ) << 1; -R3 = ( R3 + R0 ) << 1; -R4 = ( R4 + R0 ) << 1; -R5 = ( R5 + R0 ) << 1; -R6 = ( R6 + R0 ) << 1; -R7 = ( R7 + R0 ) << 1; -R0 = ( R0 + R0 ) << 1; -CHECKREG r0, 0x0D05E640; -CHECKREG r1, 0x2AE5A010; -CHECKREG r2, 0x4D05C232; -CHECKREG r3, 0x6F25E454; -CHECKREG r4, 0x11460676; -CHECKREG r5, 0x33662898; -CHECKREG r6, 0x55864ABA; -CHECKREG r7, 0x77A66CDC; - -imm32 r0, 0x03457290; -imm32 r1, 0x12345278; -imm32 r2, 0x23456289; -imm32 r3, 0x3456729a; -imm32 r4, 0x856782ab; -imm32 r5, 0x967892bc; -imm32 r6, 0xa789a2cd; -imm32 r7, 0xb89ab2de; -R0 = ( R0 + R1 ) << 1; -R2 = ( R2 + R1 ) << 1; -R3 = ( R3 + R1 ) << 1; -R4 = ( R4 + R1 ) << 1; -R5 = ( R5 + R1 ) << 1; -R6 = ( R6 + R1 ) << 1; -R7 = ( R7 + R1 ) << 1; -R1 = ( R1 + R1 ) << 1; -CHECKREG r0, 0x2AF38A10; -CHECKREG r1, 0x48D149E0; -CHECKREG r2, 0x6AF36A02; -CHECKREG r3, 0x8D158A24; -CHECKREG r4, 0x2F37AA46; -CHECKREG r5, 0x5159CA68; -CHECKREG r6, 0x737BEA8A; -CHECKREG r7, 0x959E0AAC; - -imm32 r0, 0x03457930; -imm32 r1, 0x12345638; -imm32 r2, 0x23456739; -imm32 r3, 0x3456783a; -imm32 r4, 0x8567893b; -imm32 r5, 0x96789a3c; -imm32 r6, 0xa789ab3d; -imm32 r7, 0xb89abc3e; -R0 = ( R0 + R2 ) << 1; -R1 = ( R1 + R2 ) << 1; -R3 = ( R3 + R2 ) << 1; -R4 = ( R4 + R2 ) << 1; -R5 = ( R5 + R2 ) << 1; -R6 = ( R6 + R2 ) << 1; -R7 = ( R7 + R2 ) << 1; -R2 = ( R2 + R2 ) << 1; -CHECKREG r0, 0x4D15C0D2; -CHECKREG r1, 0x6AF37AE2; -CHECKREG r2, 0x8D159CE4; -CHECKREG r3, 0xAF37BEE6; -CHECKREG r4, 0x5159E0E8; -CHECKREG r5, 0x737C02EA; -CHECKREG r6, 0x959E24EC; -CHECKREG r7, 0xB7C046EE; - -imm32 r0, 0x04457990; -imm32 r1, 0x14345678; -imm32 r2, 0x24456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x846789ab; -imm32 r5, 0x94789abc; -imm32 r6, 0xa489abcd; -imm32 r7, 0xb49abcde; -R0 = ( R0 + R3 ) << 1; -R1 = ( R1 + R3 ) << 1; -R2 = ( R2 + R3 ) << 1; -R4 = ( R4 + R3 ) << 1; -R5 = ( R5 + R3 ) << 1; -R6 = ( R6 + R3 ) << 1; -R7 = ( R7 + R3 ) << 1; -R3 = ( R3 + R3 ) << 1; -CHECKREG r0, 0x7137E454; -CHECKREG r1, 0x91159E24; -CHECKREG r2, 0xB137C046; -CHECKREG r3, 0xD159E268; -CHECKREG r4, 0x717C048A; -CHECKREG r5, 0x919E26AC; -CHECKREG r6, 0xB1C048CE; -CHECKREG r7, 0xD1E26AF0; - -imm32 r0, 0x03417990; -imm32 r1, 0x12315678; -imm32 r2, 0x23416789; -imm32 r3, 0x3451789a; -imm32 r4, 0x856189ab; -imm32 r5, 0x96719abc; -imm32 r6, 0xa781abcd; -imm32 r7, 0xb891bcde; -R0 = ( R0 + R4 ) << 1; -R1 = ( R1 + R4 ) << 1; -R2 = ( R2 + R4 ) << 1; -R3 = ( R3 + R4 ) << 1; -R5 = ( R5 + R4 ) << 1; -R6 = ( R6 + R4 ) << 1; -R7 = ( R7 + R4 ) << 1; -R4 = ( R4 + R4 ) << 1; -CHECKREG r0, 0x11460676; -CHECKREG r1, 0x2F25C046; -CHECKREG r2, 0x5145E268; -CHECKREG r3, 0x7366048A; -CHECKREG r4, 0x158626AC; -CHECKREG r5, 0x37A648CE; -CHECKREG r6, 0x59C66AF0; -CHECKREG r7, 0x7BE68D12; - -imm32 r0, 0x03457290; -imm32 r1, 0x12345278; -imm32 r2, 0x23456289; -imm32 r3, 0x3456729a; -imm32 r4, 0x856782ab; -imm32 r5, 0x967892bc; -imm32 r6, 0xa789a2cd; -imm32 r7, 0xb89ab2de; -R0 = ( R0 + R5 ) << 1; -R1 = ( R1 + R5 ) << 1; -R2 = ( R2 + R5 ) << 1; -R3 = ( R3 + R5 ) << 1; -R4 = ( R4 + R5 ) << 1; -R6 = ( R6 + R5 ) << 1; -R7 = ( R7 + R5 ) << 1; -R5 = ( R5 + R5 ) << 1; -CHECKREG r0, 0x337C0A98; -CHECKREG r1, 0x5159CA68; -CHECKREG r2, 0x737BEA8A; -CHECKREG r3, 0x959E0AAC; -CHECKREG r4, 0x37C02ACE; -CHECKREG r5, 0x59E24AF0; -CHECKREG r6, 0x7C046B12; -CHECKREG r7, 0x9E268B34; - -imm32 r0, 0x03457930; -imm32 r1, 0x12345638; -imm32 r2, 0x23456739; -imm32 r3, 0x3456783a; -imm32 r4, 0x8567893b; -imm32 r5, 0x96789a3c; -imm32 r6, 0xa789ab3d; -imm32 r7, 0xb89abc3e; -R0 = ( R0 + R6 ) << 1; -R1 = ( R1 + R6 ) << 1; -R2 = ( R2 + R6 ) << 1; -R3 = ( R3 + R6 ) << 1; -R4 = ( R4 + R6 ) << 1; -R5 = ( R5 + R6 ) << 1; -R7 = ( R7 + R6 ) << 1; -R6 = ( R6 + R6 ) << 1; -CHECKREG r0, 0x559E48DA; -CHECKREG r1, 0x737C02EA; -CHECKREG r2, 0x959E24EC; -CHECKREG r3, 0xB7C046EE; -CHECKREG r4, 0x59E268F0; -CHECKREG r5, 0x7C048AF2; -CHECKREG r6, 0x9E26ACF4; -CHECKREG r7, 0xC048CEF6; - -imm32 r0, 0x04457990; -imm32 r1, 0x14345678; -imm32 r2, 0x24456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x846789ab; -imm32 r5, 0x94789abc; -imm32 r6, 0xa489abcd; -imm32 r7, 0xb49abcde; -R0 = ( R0 + R7 ) << 1; -R1 = ( R1 + R7 ) << 1; -R2 = ( R2 + R7 ) << 1; -R3 = ( R3 + R7 ) << 1; -R4 = ( R4 + R7 ) << 1; -R5 = ( R5 + R7 ) << 1; -R6 = ( R6 + R7 ) << 1; -R7 = ( R7 + R7 ) << 1; -CHECKREG r0, 0x71C06CDC; -CHECKREG r1, 0x919E26AC; -CHECKREG r2, 0xB1C048CE; -CHECKREG r3, 0xD1E26AF0; -CHECKREG r4, 0x72048D12; -CHECKREG r5, 0x9226AF34; -CHECKREG r6, 0xB248D156; -CHECKREG r7, 0xD26AF378; -pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_shadd_2.s b/sim/testsuite/sim/bfin/c_alu2op_shadd_2.s deleted file mode 100644 index b9812f4..0000000 --- a/sim/testsuite/sim/bfin/c_alu2op_shadd_2.s +++ /dev/null @@ -1,209 +0,0 @@ -//Original:/testcases/core/c_alu2op_shadd_2/c_alu2op_shadd_2.dsp -// Spec Reference: alu2op shadd 2 -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x03417990; -imm32 r1, 0x12315678; -imm32 r2, 0x23416789; -imm32 r3, 0x3451789a; -imm32 r4, 0x856189ab; -imm32 r5, 0x96719abc; -imm32 r6, 0xa781abcd; -imm32 r7, 0xb891bcde; -R1 = ( R1 + R0 ) << 2; -R2 = ( R2 + R0 ) << 2; -R3 = ( R3 + R0 ) << 2; -R4 = ( R4 + R0 ) << 2; -R5 = ( R5 + R0 ) << 2; -R6 = ( R6 + R0 ) << 2; -R7 = ( R7 + R0 ) << 2; -R0 = ( R0 + R0 ) << 2; -CHECKREG r0, 0x1A0BCC80; -CHECKREG r1, 0x55CB4020; -CHECKREG r2, 0x9A0B8464; -CHECKREG r3, 0xDE4BC8A8; -CHECKREG r4, 0x228C0CEC; -CHECKREG r5, 0x66CC5130; -CHECKREG r6, 0xAB0C9574; -CHECKREG r7, 0xEF4CD9B8; - -imm32 r0, 0x03457290; -imm32 r1, 0x12345278; -imm32 r2, 0x23456289; -imm32 r3, 0x3456729a; -imm32 r4, 0x856782ab; -imm32 r5, 0x967892bc; -imm32 r6, 0xa789a2cd; -imm32 r7, 0xb89ab2de; -R0 = ( R0 + R1 ) << 2; -R2 = ( R2 + R1 ) << 2; -R3 = ( R3 + R1 ) << 2; -R4 = ( R4 + R1 ) << 2; -R5 = ( R5 + R1 ) << 2; -R6 = ( R6 + R1 ) << 2; -R7 = ( R7 + R1 ) << 2; -R1 = ( R1 + R1 ) << 2; -CHECKREG r0, 0x55E71420; -CHECKREG r1, 0x91A293C0; -CHECKREG r2, 0xD5E6D404; -CHECKREG r3, 0x1A2B1448; -CHECKREG r4, 0x5E6F548C; -CHECKREG r5, 0xA2B394D0; -CHECKREG r6, 0xE6F7D514; -CHECKREG r7, 0x2B3C1558; - -imm32 r0, 0x03457930; -imm32 r1, 0x12345638; -imm32 r2, 0x23456739; -imm32 r3, 0x3456783a; -imm32 r4, 0x8567893b; -imm32 r5, 0x96789a3c; -imm32 r6, 0xa789ab3d; -imm32 r7, 0xb89abc3e; -R0 = ( R0 + R2 ) << 2; -R1 = ( R1 + R2 ) << 2; -R3 = ( R3 + R2 ) << 2; -R4 = ( R4 + R2 ) << 2; -R5 = ( R5 + R2 ) << 2; -R6 = ( R6 + R2 ) << 2; -R7 = ( R7 + R2 ) << 2; -R2 = ( R2 + R2 ) << 2; -CHECKREG r0, 0x9A2B81A4; -CHECKREG r1, 0xD5E6F5C4; -CHECKREG r2, 0x1A2B39C8; -CHECKREG r3, 0x5E6F7DCC; -CHECKREG r4, 0xA2B3C1D0; -CHECKREG r5, 0xE6F805D4; -CHECKREG r6, 0x2B3C49D8; -CHECKREG r7, 0x6F808DDC; - -imm32 r0, 0x04457990; -imm32 r1, 0x14345678; -imm32 r2, 0x24456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x846789ab; -imm32 r5, 0x94789abc; -imm32 r6, 0xa489abcd; -imm32 r7, 0xb49abcde; -R0 = ( R0 + R3 ) << 2; -R1 = ( R1 + R3 ) << 2; -R2 = ( R2 + R3 ) << 2; -R4 = ( R4 + R3 ) << 2; -R5 = ( R5 + R3 ) << 2; -R6 = ( R6 + R3 ) << 2; -R7 = ( R7 + R3 ) << 2; -R3 = ( R3 + R3 ) << 2; -CHECKREG r0, 0xE26FC8A8; -CHECKREG r1, 0x222B3C48; -CHECKREG r2, 0x626F808C; -CHECKREG r3, 0xA2B3C4D0; -CHECKREG r4, 0xE2F80914; -CHECKREG r5, 0x233C4D58; -CHECKREG r6, 0x6380919C; -CHECKREG r7, 0xA3C4D5E0; - -imm32 r0, 0x03417990; -imm32 r1, 0x12315678; -imm32 r2, 0x23416789; -imm32 r3, 0x3451789a; -imm32 r4, 0x856189ab; -imm32 r5, 0x96719abc; -imm32 r6, 0xa781abcd; -imm32 r7, 0xb891bcde; -R0 = ( R0 + R4 ) << 2; -R1 = ( R1 + R4 ) << 2; -R2 = ( R2 + R4 ) << 2; -R3 = ( R3 + R4 ) << 2; -R5 = ( R5 + R4 ) << 2; -R6 = ( R6 + R4 ) << 2; -R7 = ( R7 + R4 ) << 2; -R4 = ( R4 + R4 ) << 2; -CHECKREG r0, 0x228C0CEC; -CHECKREG r1, 0x5E4B808C; -CHECKREG r2, 0xA28BC4D0; -CHECKREG r3, 0xE6CC0914; -CHECKREG r4, 0x2B0C4D58; -CHECKREG r5, 0x6F4C919C; -CHECKREG r6, 0xB38CD5E0; -CHECKREG r7, 0xF7CD1A24; - -imm32 r0, 0x03457290; -imm32 r1, 0x12345278; -imm32 r2, 0x23456289; -imm32 r3, 0x3456729a; -imm32 r4, 0x856782ab; -imm32 r5, 0x967892bc; -imm32 r6, 0xa789a2cd; -imm32 r7, 0xb89ab2de; -R0 = ( R0 + R5 ) << 2; -R1 = ( R1 + R5 ) << 2; -R2 = ( R2 + R5 ) << 2; -R3 = ( R3 + R5 ) << 2; -R4 = ( R4 + R5 ) << 2; -R6 = ( R6 + R5 ) << 2; -R7 = ( R7 + R5 ) << 2; -R5 = ( R5 + R5 ) << 2; -CHECKREG r0, 0x66F81530; -CHECKREG r1, 0xA2B394D0; -CHECKREG r2, 0xE6F7D514; -CHECKREG r3, 0x2B3C1558; -CHECKREG r4, 0x6F80559C; -CHECKREG r5, 0xB3C495E0; -CHECKREG r6, 0xF808D624; -CHECKREG r7, 0x3C4D1668; - -imm32 r0, 0x03457930; -imm32 r1, 0x12345638; -imm32 r2, 0x23456739; -imm32 r3, 0x3456783a; -imm32 r4, 0x8567893b; -imm32 r5, 0x96789a3c; -imm32 r6, 0xa789ab3d; -imm32 r7, 0xb89abc3e; -R0 = ( R0 + R6 ) << 2; -R1 = ( R1 + R6 ) << 2; -R2 = ( R2 + R6 ) << 2; -R3 = ( R3 + R6 ) << 2; -R4 = ( R4 + R6 ) << 2; -R5 = ( R5 + R6 ) << 2; -R7 = ( R7 + R6 ) << 2; -R6 = ( R6 + R6 ) << 2; -CHECKREG r0, 0xAB3C91B4; -CHECKREG r1, 0xE6F805D4; -CHECKREG r2, 0x2B3C49D8; -CHECKREG r3, 0x6F808DDC; -CHECKREG r4, 0xB3C4D1E0; -CHECKREG r5, 0xF80915E4; -CHECKREG r6, 0x3C4D59E8; -CHECKREG r7, 0x80919DEC; - -imm32 r0, 0x04457990; -imm32 r1, 0x14345678; -imm32 r2, 0x24456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x846789ab; -imm32 r5, 0x94789abc; -imm32 r6, 0xa489abcd; -imm32 r7, 0xb49abcde; -R0 = ( R0 + R7 ) << 2; -R1 = ( R1 + R7 ) << 2; -R2 = ( R2 + R7 ) << 2; -R3 = ( R3 + R7 ) << 2; -R4 = ( R4 + R7 ) << 2; -R5 = ( R5 + R7 ) << 2; -R6 = ( R6 + R7 ) << 2; -R7 = ( R7 + R7 ) << 2; -CHECKREG r0, 0xE380D9B8; -CHECKREG r1, 0x233C4D58; -CHECKREG r2, 0x6380919C; -CHECKREG r3, 0xA3C4D5E0; -CHECKREG r4, 0xE4091A24; -CHECKREG r5, 0x244D5E68; -CHECKREG r6, 0x6491A2AC; -CHECKREG r7, 0xA4D5E6F0; -pass diff --git a/sim/testsuite/sim/bfin/c_br_preg_killed_ac.s b/sim/testsuite/sim/bfin/c_br_preg_killed_ac.s deleted file mode 100644 index 67a5bdc..0000000 --- a/sim/testsuite/sim/bfin/c_br_preg_killed_ac.s +++ /dev/null @@ -1,82 +0,0 @@ -//Original:/testcases/seq/c_br_preg_killed_ac/c_br_preg_killed_ac.dsp -// Spec Reference: brcc kills data cache hits -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x00000000; - imm32 r1, 0x00000001; - imm32 r2, 0x00000002; - imm32 r3, 0x00000003; - imm32 r4, 0x00000004; - imm32 r5, 0x00000005; - imm32 r6, 0x00000006; - imm32 r7, 0x00000007; - imm32 p1, 0x00000011; - imm32 p2, 0x00000012; - - P4 = 4; - P2 = 2; - loadsym P5, DATA0; - loadsym I0, DATA1; - -begin: - ASTAT = R0; // clear CC - IF !CC JUMP LABEL1; // (bp); - CC = R4 < R5; // CC FLAG killed - R1 = 21; -LABEL1: - JUMP ( PC + P4 ); //brf LABEL2; // (bp); - CC = ! CC; -LABEL2: - JUMP ( PC + P4 ); //brf LABEL3; // (bp); - R2 = - R2; // ALU2op killed -LABEL3: - JUMP ( PC + P4 ); //brf LABEL4; - R3 <<= 2; // LOGI2op killed -LABEL4: - JUMP ( PC + P4 ); //brf LABEL5; - R0 = R1 + R2; // COMP3op killed -LABEL5: - JUMP ( PC + P4 ); //brf LABEL6; - R4 += 3; // COMPI2opD killed -LABEL6: - JUMP ( PC + P4 ); //brf LABEL7; // (bp); - R5 = 25; // LDIMMHALF killed -LABEL7: - JUMP ( PC + P4 ); //brf LABEL8; - R6 = CC; // CC2REG killed -LABEL8: - JUMP ( PC + P4 ); //brf LABEL9; - JUMP ( PC + P2 ); //BAD1; // UJUMP killed -LABEL9: - JUMP ( PC + P4 ); //brf LABELCHK1; -BAD1: - R7 = [ P5 ]; // LDST killed - -LABELCHK1: - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00000002; - CHECKREG r3, 0x00000003; - CHECKREG r4, 0x00000004; - CHECKREG r5, 0x00000005; - CHECKREG r6, 0x00000006; - CHECKREG r7, 0x00000007; - - pass - - .data -DATA0: - .dd 0x000a0000 - .dd 0x000b0001 - .dd 0x000c0002 - .dd 0x000d0003 - .dd 0x000e0004 - -DATA1: - .dd 0x00f00100 - .dd 0x00e00101 - .dd 0x00d00102 - .dd 0x00c00103 diff --git a/sim/testsuite/sim/bfin/c_br_preg_killed_ex1.s b/sim/testsuite/sim/bfin/c_br_preg_killed_ex1.s deleted file mode 100644 index 7a18f53..0000000 --- a/sim/testsuite/sim/bfin/c_br_preg_killed_ex1.s +++ /dev/null @@ -1,85 +0,0 @@ -//Original:/testcases/seq/c_br_preg_killed_ex1/c_br_preg_killed_ex1.dsp -// Spec Reference: brcc kills data cache hits -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x00000000; - imm32 r1, 0x00000001; - imm32 r2, 0x00000002; - imm32 r3, 0x00000003; - imm32 r4, 0x00000004; - imm32 r5, 0x00000005; - imm32 r6, 0x00000006; - imm32 r7, 0x00000007; - imm32 p1, 0x00000011; - imm32 p2, 0x00000012; -.ifndef BFIN_HOST - imm32 p3, 0x00000013; -.endif - imm32 p4, 0x00000014; - - P2 = 4; - loadsym p5, DATA0; - loadsym I0, DATA1; - -begin: - ASTAT = R0; // clear CC - IF !CC JUMP LABEL1; // (bp); - CC = R4 < R5; // CC FLAG killed - R1 = 21; -LABEL1: - JUMP ( PC + P2 ); //brf LABEL2; // (bp); - CC = ! CC; -LABEL2: - IF !CC JUMP LABEL3; // (bp); - R2 = - R2; // ALU2op killed -LABEL3: - IF !CC JUMP LABEL4; - R3 <<= 2; // LOGI2op killed -LABEL4: - IF !CC JUMP LABEL5; - R0 = R1 + R2; // COMP3op killed -LABEL5: - IF !CC JUMP LABEL6; - R4 += 3; // COMPI2opD killed -LABEL6: - IF !CC JUMP LABEL7; // (bp); - R5 = 25; // LDIMMHALF killed -LABEL7: - IF !CC JUMP LABEL8; - R6 = CC; // CC2REG killed -LABEL8: - IF !CC JUMP LABEL9; - JUMP.S BAD1; // UJUMP killed -LABEL9: - IF !CC JUMP LABELCHK1; -BAD1: - R7 = [ P5 ]; // LDST killed - -LABELCHK1: - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00000002; - CHECKREG r3, 0x00000003; - CHECKREG r4, 0x00000004; - CHECKREG r5, 0x00000005; - CHECKREG r6, 0x00000006; - CHECKREG r7, 0x00000007; - - pass - - .data -DATA0: - .dd 0x000a0000 - .dd 0x000b0001 - .dd 0x000c0002 - .dd 0x000d0003 - .dd 0x000e0004 - -DATA1: - .dd 0x00f00100 - .dd 0x00e00101 - .dd 0x00d00102 - .dd 0x00c00103 diff --git a/sim/testsuite/sim/bfin/c_br_preg_stall_ac.s b/sim/testsuite/sim/bfin/c_br_preg_stall_ac.s deleted file mode 100644 index 7ac29e6..0000000 --- a/sim/testsuite/sim/bfin/c_br_preg_stall_ac.s +++ /dev/null @@ -1,75 +0,0 @@ -//Original:/testcases/seq/c_br_preg_stall_ac/c_br_preg_stall_ac.dsp -// Spec Reference: brcc kills data cache hits -# mach: bfin - -.include "testutils.inc" - start - - /* This test likes to assume the current [SP] is valid */ - SP += -12; - - imm32 r0, 0x00000000; - imm32 r1, 0x00000001; - imm32 r2, 0x00000002; - imm32 r3, 0x00000003; - imm32 r4, 0x00000004; - imm32 r5, 0x00000005; - imm32 r6, 0x00000006; - imm32 r7, 0x00000007; - imm32 p1, 0x00000011; - imm32 p2, 0x00000012; -.ifndef BFIN_HOST; - imm32 p3, 0x00000013; -.endif - imm32 p4, 0x00000014; - - P1 = 4; - P2 = 6; - loadsym P5, DATA0; - loadsym I0, DATA1; - -begin: - ASTAT = R0; // clear CC - R0 = CC; - IF CC R1 = R0; - [ SP ] = P2; - P2 = [ SP ]; - JUMP ( PC + P2 ); //brf LABEL1; // (bp); - CC = R4 < R5; // CC FLAG killed - R1 = 21; -LABEL1: - JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1' - CC = ! CC; -LABEL2: - JUMP ( PC + P1 ); //brf LABEL3; - JUMP ( PC + P2 ); //BAD1; // UJUMP killed -LABEL3: - JUMP ( PC + P1 ); //brf LABELCHK1; -BAD1: - R7 = [ P5 ]; // LDST killed - -LABELCHK1: - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00000002; - CHECKREG r3, 0x00000003; - CHECKREG r4, 0x00000004; - CHECKREG r5, 0x00000005; - CHECKREG r6, 0x00000006; - CHECKREG r7, 0x00000007; - - pass - - .data -DATA0: - .dd 0x000a0000 - .dd 0x000b0001 - .dd 0x000c0002 - .dd 0x000d0003 - .dd 0x000e0004 - -DATA1: - .dd 0x00f00100 - .dd 0x00e00101 - .dd 0x00d00102 - .dd 0x00c00103 diff --git a/sim/testsuite/sim/bfin/c_br_preg_stall_ex1.s b/sim/testsuite/sim/bfin/c_br_preg_stall_ex1.s deleted file mode 100644 index 5310edf..0000000 --- a/sim/testsuite/sim/bfin/c_br_preg_stall_ex1.s +++ /dev/null @@ -1,70 +0,0 @@ -//Original:/testcases/seq/c_br_preg_stall_ex1/c_br_preg_stall_ex1.dsp -// Spec Reference: brcc kills data cache hits -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x00000000; - imm32 r1, 0x00000001; - imm32 r2, 0x00000002; - imm32 r3, 0x00000003; - imm32 r4, 0x00000004; - imm32 r5, 0x00000005; - imm32 r6, 0x00000006; - imm32 r7, 0x00000007; - imm32 p1, 0x00000011; - imm32 p2, 0x00000012; -.ifndef BFIN_HOST - imm32 p3, 0x00000013; -.endif - imm32 p4, 0x00000014; - - P1 = 4; - P2 = 6; - loadsym p5, DATA0; - loadsym I0, DATA1; - -begin: - ASTAT = R0; // clear CC - R0 = CC; - IF CC R1 = R0; - IF !CC JUMP LABEL1; - R0 = LC0; - R2 = R1 + R0; -LABEL1: - JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1' - CC = ! CC; -LABEL2: - JUMP ( PC + P1 ); //brf LABEL3; - JUMP ( PC + P2 ); //BAD1; // UJUMP killed -LABEL3: - JUMP ( PC + P1 ); //brf LABELCHK1; -BAD1: - R7 = [ P5 ]; // LDST killed - -LABELCHK1: - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00000002; - CHECKREG r3, 0x00000003; - CHECKREG r4, 0x00000004; - CHECKREG r5, 0x00000005; - CHECKREG r6, 0x00000006; - CHECKREG r7, 0x00000007; - - pass - - .data -DATA0: - .dd 0x000a0000 - .dd 0x000b0001 - .dd 0x000c0002 - .dd 0x000d0003 - .dd 0x000e0004 - -DATA1: - .dd 0x00f00100 - .dd 0x00e00101 - .dd 0x00d00102 - .dd 0x00c00103 diff --git a/sim/testsuite/sim/bfin/c_brcc_bp1.s b/sim/testsuite/sim/bfin/c_brcc_bp1.s deleted file mode 100644 index 012d1a5..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_bp1.s +++ /dev/null @@ -1,45 +0,0 @@ -//Original:/testcases/core/c_brcc_bp1/c_brcc_bp1.dsp -// Spec Reference: brcc bp -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -begin: -ASTAT = R0; // clear cc - CC = ! CC; // set cc=1 - IF CC JUMP good1 (BP); // branch on true (should branch) - R1 = 1; // if go here, error -good1: IF !CC JUMP bad1; // branch on false (should not branch) - JUMP.S good2; // should branch here -bad1: R2 = 2; // if go here, error -good2: CC = ! CC; // clear cc=0 - IF !CC JUMP good3; // branch on false (should branch) - R3 = 3; // if go here, error -good3: IF CC JUMP bad2; // branch on true (should not branch) - JUMP.S end; // we're done -bad2: R4 = 4; // if go here error - -end: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_brcc_bp2.s b/sim/testsuite/sim/bfin/c_brcc_bp2.s deleted file mode 100644 index 1fc7278..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_bp2.s +++ /dev/null @@ -1,45 +0,0 @@ -//Original:/testcases/core/c_brcc_bp2/c_brcc_bp2.dsp -// Spec Reference: brcc bp -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -begin: -ASTAT = R0; // clear cc - CC = ! CC; // set cc=1 - IF CC JUMP good1 (BP); // branch on true (should branch) - R1 = 1; // if go here, error -good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) - JUMP.S good2; // should branch here -bad1: R2 = 2; // if go here, error -good2: CC = ! CC; // clear cc=0 - IF !CC JUMP good3; // branch on false (should branch) - R3 = 3; // if go here, error -good3: IF CC JUMP bad2; // branch on true (should not branch) - JUMP.S end; // we're done -bad2: R4 = 4; // if go here error - -end: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_brcc_bp3.s b/sim/testsuite/sim/bfin/c_brcc_bp3.s deleted file mode 100644 index 0a21994..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_bp3.s +++ /dev/null @@ -1,47 +0,0 @@ -//Original:/testcases/core/c_brcc_bp3/c_brcc_bp3.dsp -// Spec Reference: brcc bp -# mach: bfin - -.include "testutils.inc" - start - - - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -begin: -ASTAT = R0; // clear cc - CC = ! CC; // set cc=1 - IF CC JUMP good1 (BP); // branch on true (should branch) - R1 = 1; // if go here, error -good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) - JUMP.S good2; // should branch here -bad1: R2 = 2; // if go here, error -good2: CC = ! CC; // clear cc=0 - IF !CC JUMP good3 (BP); // branch on false (should branch) - R3 = 3; // if go here, error -good3: IF CC JUMP bad2; // branch on true (should not branch) - JUMP.S end; // we're done -bad2: R4 = 4; // if go here error - -end: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_brcc_bp4.s b/sim/testsuite/sim/bfin/c_brcc_bp4.s deleted file mode 100644 index 39f64b1..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_bp4.s +++ /dev/null @@ -1,46 +0,0 @@ -//Original:/testcases/core/c_brcc_bp4/c_brcc_bp4.dsp -// Spec Reference: brcc bp -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -begin: -ASTAT = R0; // clear cc - CC = ! CC; // set cc=1 - IF CC JUMP good1 (BP); // branch on true (should branch) - R1 = 1; // if go here, error -good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) - JUMP.S good2; // should branch here -bad1: R2 = 2; // if go here, error -good2: CC = ! CC; // clear cc=0 - IF !CC JUMP good3 (BP); // branch on false (should branch) - R3 = 3; // if go here, error -good3: IF CC JUMP bad2 (BP); // branch on true (should not branch) - JUMP.S end; // we're done -bad2: R4 = 4; // if go here error - -end: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_brcc_brf_bp.s b/sim/testsuite/sim/bfin/c_brcc_brf_bp.s deleted file mode 100644 index 7ca29c5..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_brf_bp.s +++ /dev/null @@ -1,46 +0,0 @@ -//Original:/testcases/core/c_brcc_brf_bp/c_brcc_brf_bp.dsp -// Spec Reference: brcc brf bp -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -begin: -ASTAT = R0; // clear cc - IF !CC JUMP good1 (BP); // branch on false (should branch) - CC = ! CC; // set cc=1 - R1 = 1; // if go here, error -good1: IF !CC JUMP good2 (BP); // branch on false (should branch) -bad1: R2 = 2; // if go here, error -good2: CC = ! CC; // - IF !CC JUMP bad2 (BP); // branch on false (should not branch) - CC = ! CC; - IF !CC JUMP good3 (BP); // branch on false (should branch) - R3 = 3; // if go here, error -good3: IF !CC JUMP end; // branch on true (should branch) -bad2: R4 = 4; // if go here error - -end: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_brcc_brf_brt_bp.s b/sim/testsuite/sim/bfin/c_brcc_brf_brt_bp.s deleted file mode 100644 index c9f2945..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_brf_brt_bp.s +++ /dev/null @@ -1,47 +0,0 @@ -//Original:/testcases/core/c_brcc_brf_brt_bp/c_brcc_brf_brt_bp.dsp -// Spec Reference: brcc brfbrt -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000444; -imm32 r5, 0x00000555; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -begin: - ASTAT = R0; // clear cc - CC = R4 < R5; - IF CC JUMP good1 (BP); // branch on true (should branch) - R1 = 1; // if go here, error -good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) - CC = ! CC; - IF !CC JUMP good2; // should branch here -bad1: R2 = 2; // if go here, error -good2: CC = ! CC; // clear cc=0 - IF CC JUMP good3 (BP); // branch on false (should branch) - R3 = 3; // if go here, error -good3: IF !CC JUMP bad2 (BP); // branch on true (should not branch) - IF CC JUMP end; // we're done -bad2: R0 = 8; // if go here error - -end: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000444; -CHECKREG r5, 0x00000555; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_brcc_brf_brt_nbp.s b/sim/testsuite/sim/bfin/c_brcc_brf_brt_nbp.s deleted file mode 100644 index 32b3bd0..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_brf_brt_nbp.s +++ /dev/null @@ -1,46 +0,0 @@ -//Original:/testcases/core/c_brcc_brf_brt_nbp/c_brcc_brf_brt_nbp.dsp -// Spec Reference: brcc brf brt no bp -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -begin: - ASTAT = R0; // clear cc - CC = ! CC; // set cc=1 - IF CC JUMP good1; // branch on true (should branch) - R1 = 1; // if go here, error -good1: IF !CC JUMP bad1; // branch on false (should not branch) - JUMP.S good2; // should branch here -bad1: R2 = 2; // if go here, error -good2: CC = ! CC; // clear cc=0 - IF !CC JUMP good3; // branch on false (should branch) - R3 = 3; // if go here, error -good3: IF CC JUMP bad2; // branch on true (should not branch) - JUMP.S end; // we're done -bad2: R4 = 4; // if go here error - -end: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_brcc_brf_fbkwd.s b/sim/testsuite/sim/bfin/c_brcc_brf_fbkwd.s deleted file mode 100644 index 371238c..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_brf_fbkwd.s +++ /dev/null @@ -1,46 +0,0 @@ -//Original:/testcases/core/c_brcc_brf_fbkwd/c_brcc_brf_fbkwd.dsp -// Spec Reference: brcc brf forward/backward -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -ASTAT = R0; - -IF !CC JUMP SUBR; - R1.L = 0xeeee; - R2.L = 0x2222; - R3.L = 0x3333; -JBACK: - R4.L = 0x4444; - - - - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00001111; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00004444; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass - -//.code 0x448 -SUBR: - R1.L = 0x1111; -IF !CC JUMP JBACK; diff --git a/sim/testsuite/sim/bfin/c_brcc_brf_nbp.s b/sim/testsuite/sim/bfin/c_brcc_brf_nbp.s deleted file mode 100644 index 52eb0f3..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_brf_nbp.s +++ /dev/null @@ -1,45 +0,0 @@ -//Original:/testcases/core/c_brcc_brf_nbp/c_brcc_brf_nbp.dsp -// Spec Reference: brcc brf no bp -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -begin: - ASTAT = R0; // clear cc - IF !CC JUMP good1; // branch on false (should branch) - CC = ! CC; // set cc=1 - R1 = 1; // if go here, error -good1: IF !CC JUMP good2; // branch on false (should branch) -bad1: R2 = 2; // if go here, error -good2: CC = ! CC; // - IF !CC JUMP bad2; // branch on false (should not branch) - CC = ! CC; - IF !CC JUMP good3; // branch on false (should branch) - R3 = 3; // if go here, error -good3: IF !CC JUMP end; // branch on true (should branch) -bad2: R4 = 4; // if go here error - -end: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_brcc_brt_bp.s b/sim/testsuite/sim/bfin/c_brcc_brt_bp.s deleted file mode 100644 index d3ad0fc..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_brt_bp.s +++ /dev/null @@ -1,46 +0,0 @@ -//Original:/testcases/core/c_brcc_brt_bp/c_brcc_brt_bp.dsp -// Spec Reference: brcc brt bp -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -begin: - ASTAT = R0; // clear cc - CC = ! CC; // set cc=1 - IF CC JUMP good1 (BP); // (should branch) - R1 = 1; // if go here, error -good1: IF CC JUMP good2 (BP); // (should branch) -bad1: R2 = 2; // if go here, error -good2: CC = ! CC; // - IF CC JUMP bad2 (BP); // (should not branch) - CC = ! CC; - IF CC JUMP good3 (BP); // (should branch) - R3 = 3; // if go here, error -good3: IF CC JUMP end (BP); // (should branch) -bad2: R4 = 4; // if go here error - -end: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_brcc_brt_nbp.s b/sim/testsuite/sim/bfin/c_brcc_brt_nbp.s deleted file mode 100644 index a1c5e6b..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_brt_nbp.s +++ /dev/null @@ -1,45 +0,0 @@ -//Original:/testcases/core/c_brcc_brt_nbp/c_brcc_brt_nbp.dsp -// Spec Reference: brcc brt no bp -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -begin: - ASTAT = R0; // clear cc - CC = ! CC; // set cc=1 - IF CC JUMP good1; // (should branch) - R1 = 1; // if go here, error -good1: IF CC JUMP good2; // (should branch) -bad1: R2 = 2; // if go here, error -good2: CC = ! CC; // - IF CC JUMP bad2; // (should not branch) - CC = ! CC; - IF CC JUMP good3; // (should branch) - R3 = 3; // if go here, error -good3: IF CC JUMP end; // (should branch) -bad2: R4 = 4; // if go here error - -end: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_brcc_kills_dhits.s b/sim/testsuite/sim/bfin/c_brcc_kills_dhits.s deleted file mode 100644 index 5224554..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_kills_dhits.s +++ /dev/null @@ -1,136 +0,0 @@ -//Original:/testcases/core/c_brcc_kills_dhits/c_brcc_kills_dhits.dsp -// Spec Reference: brcc kills data cache hits -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x00000000; - imm32 r1, 0x00000001; - imm32 r2, 0x00000002; - imm32 r3, 0x00000003; - imm32 r4, 0x00000004; - imm32 r5, 0x00000005; - imm32 r6, 0x00000006; - imm32 r7, 0x00000007; - imm32 p1, 0x00000011; - imm32 p2, 0x00000012; -.ifndef BFIN_HOST - imm32 p3, 0x00000013; -.endif - imm32 p4, 0x00000014; - - loadsym P5, DATA0; - loadsym I0, DATA1; - -begin: - ASTAT = R0; // clear CC - IF !CC JUMP LABEL1; // (bp); - CC = R4 < R5; // CC FLAG killed - R1 = 21; -LABEL1: - IF !CC JUMP LABEL2; // (bp); - CC = ! CC; -LABEL2: - IF !CC JUMP LABEL3; // (bp); - R2 = - R2; // ALU2op killed -LABEL3: - IF !CC JUMP LABEL4; - R3 <<= 2; // LOGI2op killed -LABEL4: - IF !CC JUMP LABEL5; - R0 = R1 + R2; // COMP3op killed -LABEL5: - IF !CC JUMP LABEL6; - R4 += 3; // COMPI2opD killed -LABEL6: - IF !CC JUMP LABEL7; // (bp); - R5 = 25; // LDIMMHALF killed -LABEL7: - IF !CC JUMP LABEL8; - R6 = CC; // CC2REG killed -LABEL8: - IF !CC JUMP LABEL9; - JUMP.S BAD1; // UJUMP killed -LABEL9: - IF !CC JUMP LABELCHK1; -BAD1: - R7 = [ P5 ]; // LDST killed - -LABELCHK1: - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00000002; - CHECKREG r3, 0x00000003; - CHECKREG r4, 0x00000004; - CHECKREG r5, 0x00000005; - CHECKREG r6, 0x00000006; - CHECKREG r7, 0x00000007; - -LABEL10: - IF !CC JUMP LABEL11; - R1 = ( A1 += R4.L * R5.H ), A0 += R4.H * R5.L; -// DSP32MAC killed - -LABEL11: - IF !CC JUMP LABEL12; - R2 = R2 +|+ R3; // DSP32ALU killed - -LABEL12: - IF !CC JUMP LABEL13; - R3 = LSHIFT R2 BY R3.L (V); // dsp32shift killed - -LABEL13: - IF !CC JUMP LABEL14; - R4.H = R1.L << 6; // DSP32SHIFTIMM killed - -LABEL14: - IF !CC JUMP LABEL15; - P2 = P1; // REGMV PREG-PREG killed - -LABEL15: - IF !CC JUMP LABEL16; - R5 = P1; // REGMV Pr-to-Dr killed - -LABEL16: - IF !CC JUMP LABEL17; - ASTAT = R2; // REGMV Dr-to-sys killed - -LABEL17: - IF !CC JUMP LABEL18; - R6 = ASTAT; // REGMV sys-to-Dr killed - -LABEL18: - IF !CC JUMP LABEL19; - [ I0 ] = R2; // DSPLDST store killed - -LABEL19: - IF !CC JUMP end; - R7 = [ I0 ]; // DSPLDST load killed - -end: - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00000002; - CHECKREG r3, 0x00000003; - CHECKREG r4, 0x00000004; - CHECKREG r5, 0x00000005; - CHECKREG r6, 0x00000006; - CHECKREG r7, 0x00000007; - - pass - - .data -DATA0: - .dd 0x000a0000 - .dd 0x000b0001 - .dd 0x000c0002 - .dd 0x000d0003 - .dd 0x000e0004 - -DATA1: - .dd 0x00f00100 - .dd 0x00e00101 - .dd 0x00d00102 - .dd 0x00c00103 diff --git a/sim/testsuite/sim/bfin/c_brcc_kills_dmiss.s b/sim/testsuite/sim/bfin/c_brcc_kills_dmiss.s deleted file mode 100644 index 62bd7e1..0000000 --- a/sim/testsuite/sim/bfin/c_brcc_kills_dmiss.s +++ /dev/null @@ -1,137 +0,0 @@ -//Original:/testcases/core/c_brcc_kills_dmiss/c_brcc_kills_dmiss.dsp -// Spec Reference: brcc kills data cache miss -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x00000000; - imm32 r1, 0x00000001; - imm32 r2, 0x00000002; - imm32 r3, 0x00000003; - imm32 r4, 0x00000004; - imm32 r5, 0x00000005; - imm32 r6, 0x00000006; - imm32 r7, 0x00000007; - imm32 p1, 0x00000011; - imm32 p2, 0x00000012; -.ifndef BFIN_HOST - imm32 p3, 0x00000013; -.endif - imm32 p4, 0x00000014; - - loadsym P5, DATA0; - loadsym I0, DATA1; - -begin: - ASTAT = R0; // clear CC - IF !CC JUMP LABEL1; // (bp); - CC = R4 < R5; // CC FLAG killed - R1 = 21; -LABEL1: - IF !CC JUMP LABEL2; // (bp); - CC = ! CC; -LABEL2: - IF !CC JUMP LABEL3; // (bp); - R2 = - R2; // ALU2op killed -LABEL3: - IF !CC JUMP LABEL4; - R3 <<= 2; // LOGI2op killed -LABEL4: - IF !CC JUMP LABEL5; - R0 = R1 + R2; // COMP3op killed -LABEL5: - IF !CC JUMP LABEL6; - R4 += 3; // COMPI2opD killed -LABEL6: - IF !CC JUMP LABEL7; // (bp); - R5 = 25; // LDIMMHALF killed -LABEL7: - IF !CC JUMP LABEL8; - R6 = CC; // CC2REG killed -LABEL8: - IF !CC JUMP LABEL9; - JUMP.S BAD1; // UJUMP killed -LABEL9: - IF !CC JUMP LABELCHK1; -BAD1: - R7 = [ P5 ]; // LDST killed - -LABELCHK1: - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00000002; - CHECKREG r3, 0x00000003; - CHECKREG r4, 0x00000004; - CHECKREG r5, 0x00000005; - CHECKREG r6, 0x00000006; - CHECKREG r7, 0x00000007; - -LABEL10: - IF !CC JUMP LABEL11; - R1 = ( A1 += R4.L * R5.H ), A0 += R4.H * R5.L; -// DSP32MAC killed - -LABEL11: - IF !CC JUMP LABEL12; - R2 = R2 +|+ R3; // DSP32ALU killed - -LABEL12: - IF !CC JUMP LABEL13; - R3 = LSHIFT R2 BY R3.L (V); // dsp32shift killed - -LABEL13: - IF !CC JUMP LABEL14; - R4.H = R1.L << 6; // DSP32SHIFTIMM killed - -LABEL14: - IF !CC JUMP LABEL15; - P2 = P1; // REGMV PREG-PREG killed - -LABEL15: - IF !CC JUMP LABEL16; - R5 = P1; // REGMV Pr-to-Dr killed - -LABEL16: - IF !CC JUMP LABEL17; - ASTAT = R2; // REGMV Dr-to-sys killed - -LABEL17: - IF !CC JUMP LABEL18; - R6 = ASTAT; // REGMV sys-to-Dr killed - -LABEL18: - IF !CC JUMP LABEL19; - [ I0 ] = R2; // DSPLDST store killed - -LABEL19: - IF !CC JUMP end; - R7 = [ I0 ]; // DSPLDST load killed - -end: - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00000002; - CHECKREG r3, 0x00000003; - CHECKREG r4, 0x00000004; - CHECKREG r5, 0x00000005; - CHECKREG r6, 0x00000006; - CHECKREG r7, 0x00000007; - - pass - - .data -DATA0: - .dd 0x000a0000 - .dd 0x000b0001 - .dd 0x000c0002 - .dd 0x000d0003 - .dd 0x000e0004 - - .data -DATA1: - .dd 0x00f00100 - .dd 0x00e00101 - .dd 0x00d00102 - .dd 0x00c00103 diff --git a/sim/testsuite/sim/bfin/c_cactrl_iflush_pr.s b/sim/testsuite/sim/bfin/c_cactrl_iflush_pr.s deleted file mode 100644 index 5d85792..0000000 --- a/sim/testsuite/sim/bfin/c_cactrl_iflush_pr.s +++ /dev/null @@ -1,102 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr/c_cactrl_iflush_pr.dsp -// Spec Reference: c_cactrl iflush_pr -# mach: bfin - -.include "testutils.inc" - start - -// initial values -//p1=0x448; -//imm32 p1, CODE_ADDR_1; - loadsym p1, SUBR1; -// set all regs - - imm32 r0, 0x13545abd; - imm32 r1, 0xadbcfec7; - imm32 r2, 0xa1245679; - imm32 r3, 0x00060007; - imm32 r4, 0xefbc4569; - imm32 r5, 0x1235000b; - imm32 r6, 0x000c000d; - imm32 r7, 0x678e000f; -// The result accumulated in A0 and A1, and stored to a reg half - R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; - R3.H = A1 , A0 = R7.H * R6.L (T); -// begin of iflush - IFLUSH [ P1 ]; // p1 = 0xf00 - R7 = 0; - ASTAT = R7; - IF !CC JUMP SUBR1; -JBACK: - R6 = 0; - -//r4 = (a1 = l*h) M, a0 = h*l (r3,r2); -//r5 a1 = l*h, = (a0 = h*l) (r1,r0) IS; - CHECKREG r2, 0xFFD15679; - CHECKREG r3, 0xFFD00007; - CHECKREG r4, 0x00074569; - CHECKREG r5, 0x12358000; - - pass - -//.code 0x448 -//.code CODE_ADDR_1 -SUBR1: - R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L; - A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2); - IF !CC JUMP JBACK; - NOP; NOP; NOP; NOP; NOP; - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F diff --git a/sim/testsuite/sim/bfin/c_cactrl_iflush_pr_pp.s b/sim/testsuite/sim/bfin/c_cactrl_iflush_pr_pp.s deleted file mode 100644 index 96fbdc9..0000000 --- a/sim/testsuite/sim/bfin/c_cactrl_iflush_pr_pp.s +++ /dev/null @@ -1,100 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr_pp/c_cactrl_iflush_pr_pp.dsp -// Spec Reference: c_cactrl iflush_pr [p++] -# mach: bfin - -.include "testutils.inc" - start - - loadsym p2, SUBR1; -// set all regs - - imm32 r0, 0x13545abd; - imm32 r1, 0xadbcfec7; - imm32 r2, 0xa1245679; - imm32 r3, 0x00060007; - imm32 r4, 0xefbc4569; - imm32 r5, 0x1235000b; - imm32 r6, 0x000c000d; - imm32 r7, 0x678e000f; -// The result accumulated in A0 and A1, and stored to a reg half - R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; - R3.H = A1 , A0 = R7.H * R6.L (T); -// begin of iflush - IFLUSH [ P2 ++ ]; // p2 = 0x448 - R7 = 0; - ASTAT = R7; - IF !CC JUMP SUBR1; -JBACK: - R6 = 0; - -//r4 = (a1 = l*h) M, a0 = h*l (r3,r2); -//r5 a1 = l*h, = (a0 = h*l) (r1,r0) IS; - CHECKREG r2, 0xFFD15679; - CHECKREG r3, 0xFFD00007; - CHECKREG r4, 0x00074569; - CHECKREG r5, 0x12358000; -//CHECKREG p2, 0x00000468; - - pass - -//.code 0x448 -//.code CODE_ADDR_1 -SUBR1: - R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L; - A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2); - IF !CC JUMP JBACK; - NOP; NOP; NOP; NOP; NOP; - -// Pre-load memory witb known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F diff --git a/sim/testsuite/sim/bfin/c_calla_ljump.s b/sim/testsuite/sim/bfin/c_calla_ljump.s deleted file mode 100644 index be1e94f..0000000 --- a/sim/testsuite/sim/bfin/c_calla_ljump.s +++ /dev/null @@ -1,31 +0,0 @@ -//Original:/testcases/core/c_calla_ljump/c_calla_ljump.dsp -// Spec Reference: progctrl calla ljump -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -JUMP.L SUBR; - -JBACK: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00001111; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass - -SUBR: // should jump here - R1.L = 0x1111; - JUMP.L JBACK; - R2.L = 0x2222; // should not go here - JUMP.L JBACK; -RTS; diff --git a/sim/testsuite/sim/bfin/c_calla_subr.s b/sim/testsuite/sim/bfin/c_calla_subr.s deleted file mode 100644 index 8c651da..0000000 --- a/sim/testsuite/sim/bfin/c_calla_subr.s +++ /dev/null @@ -1,28 +0,0 @@ -//Original:/testcases/core/c_calla_subr/c_calla_subr.dsp -// Spec Reference: progctrl calla subr -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -CALL SUBR; - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00001111; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass - -SUBR: // should jump here - R1.L = 0x1111; - RTS; - R2.L = 0x2222; // should not go here - RTS; diff --git a/sim/testsuite/sim/bfin/c_cc2dreg.s b/sim/testsuite/sim/bfin/c_cc2dreg.s deleted file mode 100644 index 38aab85..0000000 --- a/sim/testsuite/sim/bfin/c_cc2dreg.s +++ /dev/null @@ -1,56 +0,0 @@ -//Original:/testcases/core/c_cc2dreg/c_cc2dreg.dsp -// Spec Reference: cc2dreg -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00120000; -imm32 r2, 0x00000003; -imm32 r3, 0x00000004; - -imm32 r4, 0x00770088; -imm32 r5, 0x009900aa; -imm32 r6, 0x00bb00cc; -imm32 r7, 0x00000000; - -ASTAT = R0; - -CC = R1; -R1 = CC; -CC = R1; -CC = ! CC; -R2 = CC; -CC = R2; -CC = ! CC; -R3 = CC; -CC = R3; -CC = ! CC; -R4 = CC; -CC = R5; -R5 = CC; -CC = R6; -R6 = CC; -CC = ! CC; -R7 = CC; -R0 = CC; - - - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; - - - - -pass diff --git a/sim/testsuite/sim/bfin/c_cc2stat_cc_ac.S b/sim/testsuite/sim/bfin/c_cc2stat_cc_ac.S deleted file mode 100644 index 964f82a..0000000 --- a/sim/testsuite/sim/bfin/c_cc2stat_cc_ac.S +++ /dev/null @@ -1,240 +0,0 @@ -//Original:/testcases/core/c_cc2stat_cc_ac/c_cc2stat_cc_ac.dsp -// Spec Reference: cc2stat cc ac -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - imm32 r0, _UNSET; - imm32 r1, _UNSET; - imm32 r2, _UNSET; - imm32 r3, _UNSET; - imm32 r4, _UNSET; - imm32 r5, _UNSET; - imm32 r6, _UNSET; - imm32 r7, _UNSET; - -// test CC = AC 0-0, 0-1, 1-0, 1-1 - imm32 R7, 0x00; - ASTAT = R7; // cc = 0, AC0 = 0 - CC = AC0; // - R0 = CC; // - - imm32 R7, _AC0; - ASTAT = R7; // cc = 0, AC0 = 1 - CC = AC0; // - R1 = CC; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AC0 = 0 - CC = AC0; // - R2 = CC; // - - imm32 R7, (_CC|_AC0); - ASTAT = R7; // cc = 1, AC0 = 1 - CC = AC0; // - R3 = CC; // - -// test cc |= AC (0-0, 0-1, 1-0, 1-1) - imm32 R7, 0x00; - ASTAT = R7; // cc = 0, AC0 = 0 - CC |= AC0; // - R4 = CC; // - - imm32 R7, _AC0; - ASTAT = R7; // cc = 0, AC0 = 1 - CC |= AC0; // - R5 = CC; // - - imm32 R7, (_CC|_AC0); - ASTAT = R7; // cc = 1, AC0 = 0 - CC |= AC0; // - R6 = CC; // - - imm32 R7, (_CC|_AC0); - ASTAT = R7; // cc = 1, AC0 = 1 - CC |= AC0; // - R7 = CC; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _SET; - CHECKREG r2, _UNSET; - CHECKREG r3, _SET; - CHECKREG r4, _UNSET; - CHECKREG r5, _SET; - CHECKREG r6, _SET; - CHECKREG r7, _SET; - -// test CC &= AC (0-0, 0-1, 1-0, 1-1) - imm32 R7, 0x00; - ASTAT = R7; // cc = 0, AC0 = 0 - CC &= AC0; // - R4 = CC; // - - imm32 R7, _AC0; - ASTAT = R7; // cc = 0, AC0 = 1 - CC &= AC0; // - R5 = CC; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AC0 = 0 - CC &= AC0; // - R6 = CC; // - - imm32 R7, (_CC|_AC0); - ASTAT = R7; // cc = 1, AC0 = 1 - CC &= AC0; // - R7 = CC; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _SET; - CHECKREG r2, _UNSET; - CHECKREG r3, _SET; - CHECKREG r4, _UNSET; - CHECKREG r5, _UNSET; - CHECKREG r6, _UNSET; - CHECKREG r7, _SET; - -// test CC ^= AC (0-0, 0-1, 1-0, 1-1) - imm32 R7, 0x00; - ASTAT = R7; // cc = 0, AC0 = 0 - CC ^= AC0; // - R4 = CC; // - - imm32 R7, _AC0; - ASTAT = R7; // cc = 0, AC0 = 1 - CC ^= AC0; // - R5 = CC; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AC0 = 0 - CC ^= AC0; // - R6 = CC; // - - imm32 R7, (_CC|_AC0); - ASTAT = R7; // cc = 1, AC0 = 1 - CC ^= AC0; // - R7 = CC; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _SET; - CHECKREG r2, _UNSET; - CHECKREG r3, _SET; - CHECKREG r4, _UNSET; - CHECKREG r5, _SET; - CHECKREG r6, _SET; - CHECKREG r7, _UNSET; - -// test AC0 = CC 0-0, 0-1, 1-0, 1-1 - imm32 R7, 0x00; - ASTAT = R7; // cc = 0, AC0 = 0 - AC0 = CC; // - R0 = ASTAT; // - - imm32 R7, _AC0; - ASTAT = R7; // cc = 0, AC0 = 1 - AC0 = CC; // - R1 = ASTAT; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AC0 = 0 - AC0 = CC; // - R2 = ASTAT; // - - imm32 R7, (_CC|_AC0); - ASTAT = R7; // cc = 1, AC0 = 1 - AC0 = CC; // - R3 = ASTAT; // - -// test AC0 |= CC (0-0, 0-1, 1-0, 1-1) - imm32 R7, 0x00; - ASTAT = R7; // cc = 0, AC0 = 0 - AC0 |= CC; // - R4 = ASTAT; // - - imm32 R7, _AC0; - ASTAT = R7; // cc = 0, AC0 = 1 - AC0 |= CC; // - R5 = ASTAT; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AC0 = 0 - AC0 |= CC; // - R6 = ASTAT; // - - imm32 R7, (_CC|_AC0); - ASTAT = R7; // cc = 1, AC0 = 1 - AC0 |= CC; // - R7 = ASTAT; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _UNSET; - CHECKREG r2, (_AC0|_CC); - CHECKREG r3, (_CC|_AC0); - CHECKREG r4, _UNSET; - CHECKREG r5, (_AC0); - CHECKREG r6, (_AC0|_CC); - CHECKREG r7, (_CC|_AC0); - -// test AC0 &= CC (0-0, 0-1, 1-0, 1-1) - imm32 R7, 0x00; - ASTAT = R7; // cc = 0, AC0 = 0 - AC0 &= CC; // - R4 = ASTAT; // - - imm32 R7, _AC0; - ASTAT = R7; // cc = 0, AC0 = 1 - AC0 &= CC; // - R5 = ASTAT; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AC0 = 0 - AC0 &= CC; // - R6 = ASTAT; // - - imm32 R7, (_CC|_AC0); - ASTAT = R7; // cc = 1, AC0 = 1 - AC0 &= CC; // - R7 = ASTAT; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _UNSET; - CHECKREG r2, (_CC|_AC0); - CHECKREG r3, (_CC|_AC0); - CHECKREG r4, _UNSET; - CHECKREG r5, _UNSET; - CHECKREG r6, _CC; - CHECKREG r7, (_CC|_AC0); - -// test AC0 ^= CC (0-0, 0-1, 1-0, 1-1) - imm32 R7, 0x00; - ASTAT = R7; // cc = 0, AC0 = 0 - AC0 ^= CC; // - R4 = ASTAT; // - - imm32 R7, _AC0; - ASTAT = R7; // cc = 0, AC0 = 1 - AC0 ^= CC; // - R5 = ASTAT; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AC0 = 0 - AC0 ^= CC; // - R6 = ASTAT; // - - imm32 R7, (_CC|_AC0); - ASTAT = R7; // cc = 1, AC0 = 1 - AC0 ^= CC; // - R7 = ASTAT; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _UNSET; - CHECKREG r2, (_CC|_AC0); - CHECKREG r3, (_CC|_AC0); - CHECKREG r4, _UNSET; - CHECKREG r5, (_AC0); - CHECKREG r6, (_CC|_AC0); - CHECKREG r7, _CC; - - pass diff --git a/sim/testsuite/sim/bfin/c_cc2stat_cc_an.s b/sim/testsuite/sim/bfin/c_cc2stat_cc_an.s deleted file mode 100644 index d93024f..0000000 --- a/sim/testsuite/sim/bfin/c_cc2stat_cc_an.s +++ /dev/null @@ -1,243 +0,0 @@ -//Original:/testcases/core/c_cc2stat_cc_an/c_cc2stat_cc_an.dsp -// Spec Reference: cc2stat cc an -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -// test CC = AN 0-0, 0-1, 1-0, 1-1 -R7 = 0x00; -ASTAT = R7; // cc = 0, AN = 0 -CC = AN; // -R0 = CC; // - -R7 = 0x02; -ASTAT = R7; // cc = 0, AN = 1 -CC = AN; // -R1 = CC; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AN = 0 -CC = AN; // -R2 = CC; // - -R7 = 0x22; -ASTAT = R7; // cc = 1, AN = 1 -CC = AN; // -R3 = CC; // - -// test cc |= AN (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AN = 0 -CC |= AN; // -R4 = CC; // - -R7 = 0x02; -ASTAT = R7; // cc = 0, AN = 1 -CC |= AN; // -R5 = CC; // - -R7 = 0x22; -ASTAT = R7; // cc = 1, AN = 0 -CC |= AN; // -R6 = CC; // - -R7 = 0x22; -ASTAT = R7; // cc = 1, AN = 1 -CC |= AN; // -R7 = CC; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000001; - -// test CC &= AN (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AN = 0 -CC &= AN; // -R4 = CC; // - -R7 = 0x02; -ASTAT = R7; // cc = 0, AN = 1 -CC &= AN; // -R5 = CC; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AN = 0 -CC &= AN; // -R6 = CC; // - -R7 = 0x22; -ASTAT = R7; // cc = 1, AN = 1 -CC &= AN; // -R7 = CC; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; - -// test CC ^= AN (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AN = 0 -CC ^= AN; // -R4 = CC; // - -R7 = 0x02; -ASTAT = R7; // cc = 0, AN = 1 -CC ^= AN; // -R5 = CC; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AN = 0 -CC ^= AN; // -R6 = CC; // - -R7 = 0x22; -ASTAT = R7; // cc = 1, AN = 1 -CC ^= AN; // -R7 = CC; // - - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; - -// test AN = CC 0-0, 0-1, 1-0, 1-1 -R7 = 0x00; -ASTAT = R7; // cc = 0, AN = 0 -AN = CC; // -R0 = ASTAT; // - -R7 = 0x02; -ASTAT = R7; // cc = 0, AN = 1 -AN = CC; // -R1 = ASTAT; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AN = 0 -AN = CC; // -R2 = ASTAT; // - -R7 = 0x22; -ASTAT = R7; // cc = 1, AN = 1 -AN = CC; // -R3 = ASTAT; // - -// test AN |= CC (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AN = 0 -AN |= CC; // -R4 = ASTAT; // - -R7 = 0x02; -ASTAT = R7; // cc = 0, AN = 1 -AN |= CC; // -R5 = ASTAT; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AN = 0 -AN |= CC; // -R6 = ASTAT; // - -R7 = 0x22; -ASTAT = R7; // cc = 1, AN = 1 -AN |= CC; // -R7 = ASTAT; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000022; -CHECKREG r3, 0x00000022; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000022; -CHECKREG r7, 0x00000022; - -// test AN &= CC (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AN = 0 -AN &= CC; // -R4 = ASTAT; // - -R7 = 0x02; -ASTAT = R7; // cc = 0, AN = 1 -AN &= CC; // -R5 = ASTAT; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AN = 0 -AN &= CC; // -R6 = ASTAT; // - -R7 = 0x22; -ASTAT = R7; // cc = 1, AN = 1 -AN &= CC; // -R7 = ASTAT; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000022; -CHECKREG r3, 0x00000022; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000020; -CHECKREG r7, 0x00000022; - -// test AN ^= CC (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AN = 0 -AN ^= CC; // -R4 = ASTAT; // - -R7 = 0x02; -ASTAT = R7; // cc = 0, AN = 1 -AN ^= CC; // -R5 = ASTAT; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AN = 0 -AN ^= CC; // -R6 = ASTAT; // - -R7 = 0x22; -ASTAT = R7; // cc = 1, AN = 1 -AN ^= CC; // -R7 = ASTAT; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000022; -CHECKREG r3, 0x00000022; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000022; -CHECKREG r7, 0x00000020; - - -pass diff --git a/sim/testsuite/sim/bfin/c_cc2stat_cc_aq.s b/sim/testsuite/sim/bfin/c_cc2stat_cc_aq.s deleted file mode 100644 index e8b877e..0000000 --- a/sim/testsuite/sim/bfin/c_cc2stat_cc_aq.s +++ /dev/null @@ -1,243 +0,0 @@ -//Original:/testcases/core/c_cc2stat_cc_aq/c_cc2stat_cc_aq.dsp -// Spec Reference: cc2stat cc aq -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -// test CC = AQ 0-0, 0-1, 1-0, 1-1 -R7 = 0x00; -ASTAT = R7; // cc = 0, AQ = 0 -CC = AQ; // -R0 = CC; // - -R7 = 0x40 (X); -ASTAT = R7; // cc = 0, AQ = 1 -CC = AQ; // -R1 = CC; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AQ = 0 -CC = AQ; // -R2 = CC; // - -R7 = 0x60 (X); -ASTAT = R7; // cc = 1, AQ = 1 -CC = AQ; // -R3 = CC; // - -// test cc |= AQ (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AQ = 0 -CC |= AQ; // -R4 = CC; // - -R7 = 0x40 (X); -ASTAT = R7; // cc = 0, AQ = 1 -CC |= AQ; // -R5 = CC; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AQ = 0 -CC |= AQ; // -R6 = CC; // - -R7 = 0x60 (X); -ASTAT = R7; // cc = 1, AQ = 1 -CC |= AQ; // -R7 = CC; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000001; - -// test CC &= AQ (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AQ = 0 -CC &= AQ; // -R4 = CC; // - -R7 = 0x40 (X); -ASTAT = R7; // cc = 0, AQ = 1 -CC &= AQ; // -R5 = CC; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AQ = 0 -CC &= AQ; // -R6 = CC; // - -R7 = 0x60 (X); -ASTAT = R7; // cc = 1, AQ = 1 -CC &= AQ; // -R7 = CC; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; - -// test CC ^= AQ (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AQ = 0 -CC ^= AQ; // -R4 = CC; // - -R7 = 0x40 (X); -ASTAT = R7; // cc = 0, AQ = 1 -CC ^= AQ; // -R5 = CC; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AQ = 0 -CC ^= AQ; // -R6 = CC; // - -R7 = 0x60 (X); -ASTAT = R7; // cc = 1, AQ = 1 -CC ^= AQ; // -R7 = CC; // - - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; - -// test AQ = CC 0-0, 0-1, 1-0, 1-1 -R7 = 0x00; -ASTAT = R7; // cc = 0, AQ = 0 -AQ = CC; // -R0 = ASTAT; // - -R7 = 0x40 (X); -ASTAT = R7; // cc = 0, AQ = 1 -AQ = CC; // -R1 = ASTAT; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AQ = 0 -AQ = CC; // -R2 = ASTAT; // - -R7 = 0x60 (X); -ASTAT = R7; // cc = 1, AQ = 1 -AQ = CC; // -R3 = ASTAT; // - -// test AQ |= CC (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AQ = 0 -AQ |= CC; // -R4 = ASTAT; // - -R7 = 0x40 (X); -ASTAT = R7; // cc = 0, AQ = 1 -AQ |= CC; // -R5 = ASTAT; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AQ = 0 -AQ |= CC; // -R6 = ASTAT; // - -R7 = 0x60 (X); -ASTAT = R7; // cc = 1, AQ = 1 -AQ |= CC; // -R7 = ASTAT; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000060; -CHECKREG r3, 0x00000060; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000040; -CHECKREG r6, 0x00000060; -CHECKREG r7, 0x00000060; - -// test AQ &= CC (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AQ = 0 -AQ &= CC; // -R4 = ASTAT; // - -R7 = 0x40 (X); -ASTAT = R7; // cc = 0, AQ = 1 -AQ &= CC; // -R5 = ASTAT; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AQ = 0 -AQ &= CC; // -R6 = ASTAT; // - -R7 = 0x60 (X); -ASTAT = R7; // cc = 1, AQ = 1 -AQ &= CC; // -R7 = ASTAT; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000060; -CHECKREG r3, 0x00000060; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000020; -CHECKREG r7, 0x00000060; - -// test AQ ^= CC (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AQ = 0 -AQ ^= CC; // -R4 = ASTAT; // - -R7 = 0x40 (X); -ASTAT = R7; // cc = 0, AQ = 1 -AQ ^= CC; // -R5 = ASTAT; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AQ = 0 -AQ ^= CC; // -R6 = ASTAT; // - -R7 = 0x60 (X); -ASTAT = R7; // cc = 1, AQ = 1 -AQ ^= CC; // -R7 = ASTAT; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000060; -CHECKREG r3, 0x00000060; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000040; -CHECKREG r6, 0x00000060; -CHECKREG r7, 0x00000020; - - -pass diff --git a/sim/testsuite/sim/bfin/c_cc2stat_cc_av0.S b/sim/testsuite/sim/bfin/c_cc2stat_cc_av0.S deleted file mode 100644 index c600902..0000000 --- a/sim/testsuite/sim/bfin/c_cc2stat_cc_av0.S +++ /dev/null @@ -1,241 +0,0 @@ -//Original:/testcases/core/c_cc2stat_cc_av0/c_cc2stat_cc_av0.dsp -// Spec Reference: cc2stat cc av0 -# mach: bfin - -#include "test.h" - .include "testutils.inc" - - start - - imm32 r0, 0x00000000; - imm32 r1, 0x00000000; - imm32 r2, 0x00000000; - imm32 r3, 0x00000000; - imm32 r4, 0x00000000; - imm32 r5, 0x00000000; - imm32 r6, 0x00000000; - imm32 r7, 0x00000000; - -// test CC = AV0 0-0, 0-1, 1-0, 1-1 - R7 = 0x00; - ASTAT = R7; // cc = 0, AV0 = 0 - CC = AV0; // - R0 = CC; // - - imm32 R7, _AV0; - ASTAT = R7; // cc = 0, AV0 = 1 - CC = AV0; // - R1 = CC; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV0 = 0 - CC = AV0; // - R2 = CC; // - - imm32 R7, (_CC|_AV0); - ASTAT = R7; // cc = 1, AV0 = 1 - CC = AV0; // - R3 = CC; // - -// test cc |= AV0 (0-0, 0-1, 1-0, 1-1) - R7 = 0x00; - ASTAT = R7; // cc = 0, AV0 = 0 - CC |= AV0; // - R4 = CC; // - - imm32 R7, _AV0; - ASTAT = R7; // cc = 0, AV0 = 1 - CC |= AV0; // - R5 = CC; // - - imm32 R7, (_CC|_AV0); - ASTAT = R7; // cc = 1, AV0 = 0 - CC |= AV0; // - R6 = CC; // - - imm32 R7, (_CC|_AV0); - ASTAT = R7; // cc = 1, AV0 = 1 - CC |= AV0; // - R7 = CC; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _SET; - CHECKREG r2, _UNSET; - CHECKREG r3, _SET; - CHECKREG r4, _UNSET; - CHECKREG r5, _SET; - CHECKREG r6, _SET; - CHECKREG r7, _SET; - -// test CC &= AV0 (0-0, 0-1, 1-0, 1-1) - R7 = 0x00; - ASTAT = R7; // cc = 0, AV0 = 0 - CC &= AV0; // - R4 = CC; // - - imm32 R7, _AV0; - ASTAT = R7; // cc = 0, AV0 = 1 - CC &= AV0; // - R5 = CC; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV0 = 0 - CC &= AV0; // - R6 = CC; // - - imm32 R7, (_CC|_AV0); - ASTAT = R7; // cc = 1, AV0 = 1 - CC &= AV0; // - R7 = CC; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _SET; - CHECKREG r2, _UNSET; - CHECKREG r3, _SET; - CHECKREG r4, _UNSET; - CHECKREG r5, _UNSET; - CHECKREG r6, _UNSET; - CHECKREG r7, _SET; - -// test CC ^= AV0 (0-0, 0-1, 1-0, 1-1) - R7 = 0x00; - ASTAT = R7; // cc = 0, AV0 = 0 - CC ^= AV0; // - R4 = CC; // - - imm32 R7, _AV0; - ASTAT = R7; // cc = 0, AV0 = 1 - CC ^= AV0; // - R5 = CC; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV0 = 0 - CC ^= AV0; // - R6 = CC; // - - imm32 R7, (_CC|_AV0); - ASTAT = R7; // cc = 1, AV0 = 1 - CC ^= AV0; // - R7 = CC; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _SET; - CHECKREG r2, _UNSET; - CHECKREG r3, _SET; - CHECKREG r4, _UNSET; - CHECKREG r5, _SET; - CHECKREG r6, _SET; - CHECKREG r7, _UNSET; - -// test AV0 = CC 0-0, 0-1, 1-0, 1-1 - R7 = 0x00; - ASTAT = R7; // cc = 0, AV0 = 0 - AV0 = CC; // - R0 = ASTAT; // - - imm32 R7, _AV0; - ASTAT = R7; // cc = 0, AV0 = 1 - AV0 = CC; // - R1 = ASTAT; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV0 = 0 - AV0 = CC; // - R2 = ASTAT; // - - imm32 R7, (_CC|_AV0); - ASTAT = R7; // cc = 1, AV0 = 1 - AV0 = CC; // - R3 = ASTAT; // - -// test AV0 |= CC (0-0, 0-1, 1-0, 1-1) - R7 = 0x00; - ASTAT = R7; // cc = 0, AV0 = 0 - AV0 |= CC; // - R4 = ASTAT; // - - imm32 R7, _AV0; - ASTAT = R7; // cc = 0, AV0 = 1 - AV0 |= CC; // - R5 = ASTAT; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV0 = 0 - AV0 |= CC; // - R6 = ASTAT; // - - imm32 R7, (_CC|_AV0); - ASTAT = R7; // cc = 1, AV0 = 1 - AV0 |= CC; // - R7 = ASTAT; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _UNSET; - CHECKREG r2, (_CC|_AV0); - CHECKREG r3, (_CC|_AV0); - CHECKREG r4, _UNSET; - CHECKREG r5, _AV0; - CHECKREG r6, (_CC|_AV0); - CHECKREG r7, (_CC|_AV0); - -// test AV0 &= CC (0-0, 0-1, 1-0, 1-1) - R7 = 0x00; - ASTAT = R7; // cc = 0, AV0 = 0 - AV0 &= CC; // - R4 = ASTAT; // - - imm32 R7, _AV0; - ASTAT = R7; // cc = 0, AV0 = 1 - AV0 &= CC; // - R5 = ASTAT; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV0 = 0 - AV0 &= CC; // - R6 = ASTAT; // - - imm32 R7, (_CC|_AV0); - ASTAT = R7; // cc = 1, AV0 = 1 - AV0 &= CC; // - R7 = ASTAT; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _UNSET; - CHECKREG r2, (_CC|_AV0); - CHECKREG r3, (_CC|_AV0); - CHECKREG r4, _UNSET; - CHECKREG r5, _UNSET; - CHECKREG r6, (_CC); - CHECKREG r7, (_CC|_AV0); - -// test AV0 ^= CC (0-0, 0-1, 1-0, 1-1) - R7 = 0x00; - ASTAT = R7; // cc = 0, AV0 = 0 - AV0 ^= CC; // - R4 = ASTAT; // - - imm32 R7, _AV0; - ASTAT = R7; // cc = 0, AV0 = 1 - AV0 ^= CC; // - R5 = ASTAT; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV0 = 0 - AV0 ^= CC; // - R6 = ASTAT; // - - imm32 R7, (_CC|_AV0); - ASTAT = R7; // cc = 1, AV0 = 1 - AV0 ^= CC; // - R7 = ASTAT; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _UNSET; - CHECKREG r2, (_CC|_AV0); - CHECKREG r3, (_CC|_AV0); - CHECKREG r4, _UNSET; - CHECKREG r5, _AV0; - CHECKREG r6, (_CC|_AV0); - CHECKREG r7, _CC; - - pass diff --git a/sim/testsuite/sim/bfin/c_cc2stat_cc_av1.S b/sim/testsuite/sim/bfin/c_cc2stat_cc_av1.S deleted file mode 100644 index 2855085..0000000 --- a/sim/testsuite/sim/bfin/c_cc2stat_cc_av1.S +++ /dev/null @@ -1,240 +0,0 @@ -//Original:/testcases/core/c_cc2stat_cc_av1/c_cc2stat_cc_av1.dsp -// Spec Reference: cc2stat cc av1 -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - imm32 r0, 0x00000000; - imm32 r1, 0x00000000; - imm32 r2, 0x00000000; - imm32 r3, 0x00000000; - imm32 r4, 0x00000000; - imm32 r5, 0x00000000; - imm32 r6, 0x00000000; - imm32 r7, 0x00000000; - -// test CC = AV1 0-0, 0-1, 1-0, 1-1 - R7 = 0x00; - ASTAT = R7; // cc = 0, AV1 = 0 - CC = AV1; // - R0 = CC; // - - imm32 R7, _AV1; - ASTAT = R7; // cc = 0, AV1 = 1 - CC = AV1; // - R1 = CC; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV1 = 0 - CC = AV1; // - R2 = CC; // - - imm32 R7, (_CC|_AV1); - ASTAT = R7; // cc = 1, AV1 = 1 - CC = AV1; // - R3 = CC; // - -// test cc |= AV1 (0-0, 0-1, 1-0, 1-1) - R7 = 0x00; - ASTAT = R7; // cc = 0, AV1 = 0 - CC |= AV1; // - R4 = CC; // - - imm32 R7, _AV1; - ASTAT = R7; // cc = 0, AV1 = 1 - CC |= AV1; // - R5 = CC; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV1 = 0 - CC |= AV1; // - R6 = CC; // - - imm32 R7, (_CC|_AV1); - ASTAT = R7; // cc = 1, AV1 = 1 - CC |= AV1; // - R7 = CC; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _SET; - CHECKREG r2, _UNSET; - CHECKREG r3, _SET; - CHECKREG r4, _UNSET; - CHECKREG r5, _SET; - CHECKREG r6, _SET; - CHECKREG r7, _SET; - -// test CC &= AV1 (0-0, 0-1, 1-0, 1-1) - R7 = 0x00; - ASTAT = R7; // cc = 0, AV1 = 0 - CC &= AV1; // - R4 = CC; // - - imm32 R7, _AV1; - ASTAT = R7; // cc = 0, AV1 = 1 - CC &= AV1; // - R5 = CC; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV1 = 0 - CC &= AV1; // - R6 = CC; // - - imm32 R7, (_CC|_AV1); - ASTAT = R7; // cc = 1, AV1 = 1 - CC &= AV1; // - R7 = CC; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _SET; - CHECKREG r2, _UNSET; - CHECKREG r3, _SET; - CHECKREG r4, _UNSET; - CHECKREG r5, _UNSET; - CHECKREG r6, _UNSET; - CHECKREG r7, _SET; - -// test CC ^= AV1 (0-0, 0-1, 1-0, 1-1) - R7 = 0x00; - ASTAT = R7; // cc = 0, AV1 = 0 - CC ^= AV1; // - R4 = CC; // - - imm32 R7, _AV1; - ASTAT = R7; // cc = 0, AV1 = 1 - CC ^= AV1; // - R5 = CC; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV1 = 0 - CC ^= AV1; // - R6 = CC; // - - imm32 R7, (_CC|_AV1); - ASTAT = R7; // cc = 1, AV1 = 1 - CC ^= AV1; // - R7 = CC; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _SET; - CHECKREG r2, _UNSET; - CHECKREG r3, _SET; - CHECKREG r4, _UNSET; - CHECKREG r5, _SET; - CHECKREG r6, _SET; - CHECKREG r7, _UNSET; - -// test AV1 = CC 0-0, 0-1, 1-0, 1-1 - R7 = 0x00; - ASTAT = R7; // cc = 0, AV1 = 0 - AV1 = CC; // - R0 = ASTAT; // - - imm32 R7, _AV1; - ASTAT = R7; // cc = 0, AV1 = 1 - AV1 = CC; // - R1 = ASTAT; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV1 = 0 - AV1 = CC; // - R2 = ASTAT; // - - imm32 R7, (_CC|_AV1); - ASTAT = R7; // cc = 1, AV1 = 1 - AV1 = CC; // - R3 = ASTAT; // - -// test AV1 |= CC (0-0, 0-1, 1-0, 1-1) - R7 = 0x00; - ASTAT = R7; // cc = 0, AV1 = 0 - AV1 |= CC; // - R4 = ASTAT; // - - imm32 R7, _AV1; - ASTAT = R7; // cc = 0, AV1 = 1 - AV1 |= CC; // - R5 = ASTAT; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV1 = 0 - AV1 |= CC; // - R6 = ASTAT; // - - imm32 R7, (_CC|_AV1); - ASTAT = R7; // cc = 1, AV1 = 1 - AV1 |= CC; // - R7 = ASTAT; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _UNSET; - CHECKREG r2, (_CC|_AV1); - CHECKREG r3, (_CC|_AV1); - CHECKREG r4, _UNSET; - CHECKREG r5, _AV1; - CHECKREG r6, (_CC|_AV1); - CHECKREG r7, (_CC|_AV1); - -// test AV1 &= CC (0-0, 0-1, 1-0, 1-1) - R7 = 0x00; - ASTAT = R7; // cc = 0, AV1 = 0 - AV1 &= CC; // - R4 = ASTAT; // - - imm32 R7, _AV1; - ASTAT = R7; // cc = 0, AV1 = 1 - AV1 &= CC; // - R5 = ASTAT; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV1 = 0 - AV1 &= CC; // - R6 = ASTAT; // - - imm32 R7, (_CC|_AV1); - ASTAT = R7; // cc = 1, AV1 = 1 - AV1 &= CC; // - R7 = ASTAT; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _UNSET; - CHECKREG r2, (_CC|_AV1); - CHECKREG r3, (_CC|_AV1); - CHECKREG r4, _UNSET; - CHECKREG r5, _UNSET; - CHECKREG r6, _CC; - CHECKREG r7, (_CC|_AV1); - -// test AV1 ^= CC (0-0, 0-1, 1-0, 1-1) - R7 = 0x00; - ASTAT = R7; // cc = 0, AV1 = 0 - AV1 ^= CC; // - R4 = ASTAT; // - - imm32 R7, _AV1; - ASTAT = R7; // cc = 0, AV1 = 1 - AV1 ^= CC; // - R5 = ASTAT; // - - imm32 R7, _CC; - ASTAT = R7; // cc = 1, AV1 = 0 - AV1 ^= CC; // - R6 = ASTAT; // - - imm32 R7, (_CC|_AV1); - ASTAT = R7; // cc = 1, AV1 = 1 - AV1 ^= CC; // - R7 = ASTAT; // - - CHECKREG r0, _UNSET; - CHECKREG r1, _UNSET; - CHECKREG r2, (_CC|_AV1); - CHECKREG r3, (_CC|_AV1); - CHECKREG r4, _UNSET; - CHECKREG r5, _AV1; - CHECKREG r6, (_CC|_AV1); - CHECKREG r7, _CC; - - pass diff --git a/sim/testsuite/sim/bfin/c_cc2stat_cc_az.s b/sim/testsuite/sim/bfin/c_cc2stat_cc_az.s deleted file mode 100644 index 0d8b05b..0000000 --- a/sim/testsuite/sim/bfin/c_cc2stat_cc_az.s +++ /dev/null @@ -1,243 +0,0 @@ -//Original:/testcases/core/c_cc2stat_cc_az/c_cc2stat_cc_az.dsp -// Spec Reference: cc2stat cc az -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -// test CC = AZ 0-0, 0-1, 1-0, 1-1 -R7 = 0x00; -ASTAT = R7; // cc = 0, AZ = 0 -CC = AZ; // -R0 = CC; // - -R7 = 0x01; -ASTAT = R7; // cc = 0, AZ = 1 -CC = AZ; // -R1 = CC; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AZ = 0 -CC = AZ; // -R2 = CC; // - -R7 = 0x21; -ASTAT = R7; // cc = 1, AZ = 1 -CC = AZ; // -R3 = CC; // - -// test cc |= AZ (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AZ = 0 -CC |= AZ; // -R4 = CC; // - -R7 = 0x01; -ASTAT = R7; // cc = 0, AZ = 1 -CC |= AZ; // -R5 = CC; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AZ = 0 -CC |= AZ; // -R6 = CC; // - -R7 = 0x21; -ASTAT = R7; // cc = 1, AZ = 1 -CC |= AZ; // -R7 = CC; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000001; - -// test CC &= AZ (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AZ = 0 -CC &= AZ; // -R4 = CC; // - -R7 = 0x01; -ASTAT = R7; // cc = 0, AZ = 1 -CC &= AZ; // -R5 = CC; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AZ = 0 -CC &= AZ; // -R6 = CC; // - -R7 = 0x21; -ASTAT = R7; // cc = 1, AZ = 1 -CC &= AZ; // -R7 = CC; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; - -// test CC ^= AZ (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AZ = 0 -CC ^= AZ; // -R4 = CC; // - -R7 = 0x01; -ASTAT = R7; // cc = 0, AZ = 1 -CC ^= AZ; // -R5 = CC; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AZ = 0 -CC ^= AZ; // -R6 = CC; // - -R7 = 0x21; -ASTAT = R7; // cc = 1, AZ = 1 -CC ^= AZ; // -R7 = CC; // - - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; - -// test AZ = CC 0-0, 0-1, 1-0, 1-1 -R7 = 0x00; -ASTAT = R7; // cc = 0, AZ = 0 -AZ = CC; // -R0 = ASTAT; // - -R7 = 0x01; -ASTAT = R7; // cc = 0, AZ = 1 -AZ = CC; // -R1 = ASTAT; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AZ = 0 -AZ = CC; // -R2 = ASTAT; // - -R7 = 0x21; -ASTAT = R7; // cc = 1, AZ = 1 -AZ = CC; // -R3 = ASTAT; // - -// test AZ |= CC (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AZ = 0 -AZ |= CC; // -R4 = ASTAT; // - -R7 = 0x01; -ASTAT = R7; // cc = 0, AZ = 1 -AZ |= CC; // -R5 = ASTAT; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AZ = 0 -AZ |= CC; // -R6 = ASTAT; // - -R7 = 0x21; -ASTAT = R7; // cc = 1, AZ = 1 -AZ |= CC; // -R7 = ASTAT; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000021; -CHECKREG r3, 0x00000021; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000021; -CHECKREG r7, 0x00000021; - -// test AZ &= CC (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AZ = 0 -AZ &= CC; // -R4 = ASTAT; // - -R7 = 0x01; -ASTAT = R7; // cc = 0, AZ = 1 -AZ &= CC; // -R5 = ASTAT; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AZ = 0 -AZ &= CC; // -R6 = ASTAT; // - -R7 = 0x21; -ASTAT = R7; // cc = 1, AZ = 1 -AZ &= CC; // -R7 = ASTAT; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000021; -CHECKREG r3, 0x00000021; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000020; -CHECKREG r7, 0x00000021; - -// test AZ ^= CC (0-0, 0-1, 1-0, 1-1) -R7 = 0x00; -ASTAT = R7; // cc = 0, AZ = 0 -AZ ^= CC; // -R4 = ASTAT; // - -R7 = 0x01; -ASTAT = R7; // cc = 0, AZ = 1 -AZ ^= CC; // -R5 = ASTAT; // - -R7 = 0x20; -ASTAT = R7; // cc = 1, AZ = 0 -AZ ^= CC; // -R6 = ASTAT; // - -R7 = 0x21; -ASTAT = R7; // cc = 1, AZ = 1 -AZ ^= CC; // -R7 = ASTAT; // - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000021; -CHECKREG r3, 0x00000021; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000021; -CHECKREG r7, 0x00000020; - - -pass diff --git a/sim/testsuite/sim/bfin/c_cc_flag_ccmv_depend.S b/sim/testsuite/sim/bfin/c_cc_flag_ccmv_depend.S deleted file mode 100644 index 807a753..0000000 --- a/sim/testsuite/sim/bfin/c_cc_flag_ccmv_depend.S +++ /dev/null @@ -1,80 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_cc_flag_ccmv_depend/c_cc_flag_ccmv_depend.dsp -// Spec Reference: ccflag followed by ccmv (# stalls) -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - imm32 r0, 0xa08d2311; - imm32 r1, 0x10120040; - imm32 r2, 0x62b61557; - imm32 r3, 0x07300007; - imm32 r4, 0x00740088; - imm32 r5, 0x609950aa; - imm32 r6, 0x20bb06cc; - imm32 r7, 0xd90e108f; - - imm32 p1, 0x1401101f; - imm32 p2, 0x3204108e; - imm32 fp, 0xd93f1084; - imm32 p4, 0xeb04106f; - imm32 p5, 0xa90e5089; - - CC = R7; // cc2dreg - IF CC R0 = R3; // ccmov - R6 = R0 + R4; - - CC = ! CC; // cc2dreg - IF CC R1 = P1; // ccmov - - CC = R5 < R1; // ccflag - R1 = ASTAT; - IF !CC R2 = R5; // ccmov - - CC = R2 == R3; // ccflag - IF CC P1 = R4; // ccmov - - CC = ! CC; - CC = R7 < R5; - IF CC P2 = P5; // ccmov - - CC = P5 == 3; - IF CC FP = R2; // ccmov - - R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair - - CC = A0 == A1; - IF !CC R3 = R6; // ccmov - R7 = R3 + R2; - - A0 += A1 (W32); // dsp32alu a0 + a1 - CC = A0 < A1; - IF CC R4 = P4; // ccmov - R6 = R4; - - R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac - CC = A0 <= A1; - IF CC R5 = P5; // ccmov - - A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac - CC = A0 <= A1; - IF CC P5 = R6; // ccmov - - CHECKREG r0, 0x07300007; - CHECKREG r1, (_AC0|_AC0_COPY); - CHECKREG r2, 0x00766960; - CHECKREG r3, 0x07A4008F; - CHECKREG r4, 0xEB04106F; - CHECKREG r5, 0xA90E5089; - CHECKREG r6, 0xEB04106F; - CHECKREG r7, 0x075D69EF; - CHECKREG p1, 0x1401101F; - CHECKREG p2, 0xA90E5089; - CHECKREG fp, 0xD93F1084; - CHECKREG p4, 0xEB04106F; - CHECKREG p5, 0xA90E5089; - - pass diff --git a/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft.s b/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft.s deleted file mode 100644 index a36f31a..0000000 --- a/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft.s +++ /dev/null @@ -1,87 +0,0 @@ -//Original:/testcases/core/c_cc_flagdreg_mvbrsft/c_cc_flagdreg_mvbrsft.dsp -// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0xa08d2311; -imm32 r1, 0x10120040; -imm32 r2, 0x62b61557; -imm32 r3, 0x07300007; -imm32 r4, 0x00740088; -imm32 r5, 0x609950aa; -imm32 r6, 0x20bb06cc; -imm32 r7, 0xd90e108f; - - ASTAT = R0; - - CC = R1; // cc2dreg - IF CC R1 = R3; // ccmov - CC = ! CC; // cc2dreg - IF CC R3 = R2; // ccmov - CC = R0 < R1; // ccflag - IF CC R4 = R5; // ccmov - CC = R2 == R3; - IF CC R4 = R5; // ccmov - CC = R0; // cc2dreg - IF !CC JUMP LABEL1; // branch on - CC = ! CC; - IF !CC JUMP LABEL2 (BP); // branch on -LABEL1: - R6 = R0 + R2; - JUMP.S END; -LABEL2: - R7 = R5 - R3; - CC = R0 < R1; // ccflag - IF CC JUMP END (BP); // branch on - R4 = R5 + R7; - -END: - -CHECKREG r0, 0xA08D2311; -CHECKREG r1, 0x07300007; -CHECKREG r2, 0x62B61557; -CHECKREG r3, 0x07300007; -CHECKREG r4, 0x609950AA; -CHECKREG r5, 0x609950AA; -CHECKREG r6, 0x20BB06CC; -CHECKREG r7, 0x596950A3; - -imm32 r0, 0x408d2711; -imm32 r1, 0x15124040; -imm32 r2, 0x62661557; -imm32 r3, 0x073b0007; -imm32 r4, 0x01f49088; -imm32 r5, 0x6e2959aa; -imm32 r6, 0xa0b506cc; -imm32 r7, 0x00000002; - - - CC = R1; // cc2dreg - R2 = ROT R2 BY 1; // dsp32shiftim_rot - CC = ! CC; // cc2dreg - R3 = ROT R0 BY -3; // dsp32shiftim_rot - CC = R0 < R1; // ccflag - R6 = ROT R4 BY 5; // dsp32shiftim_rot - CC = R2 == R3; - IF CC R4 = R5; // ccmov - CC = R0; // cc2dreg - R7 = ROT R6 BY R7.L; - -CHECKREG r0, 0x408D2711; -CHECKREG r1, 0x15124040; -CHECKREG r2, 0xC4CC2AAF; -CHECKREG r3, 0x6811A4E2; -CHECKREG r4, 0x01F49088; -CHECKREG r5, 0x6E2959AA; -CHECKREG r6, 0x3E921100; -CHECKREG r7, 0xFA484402; - - - - -pass diff --git a/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_s1.s b/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_s1.s deleted file mode 100644 index 24505c2..0000000 --- a/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_s1.s +++ /dev/null @@ -1,99 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_s1/c_cc_flagdreg_mvbrsft_s1.dsp -// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft) -# mach: bfin - -.include "testutils.inc" - start - - INIT_P_REGS 0; - - imm32 r0, 0xa08d2311; - imm32 r1, 0x10120040; - imm32 r2, 0x62b61557; - imm32 r3, 0x07300007; - imm32 r4, 0x00740088; - imm32 r5, 0x609950aa; - imm32 r6, 0x20bb06cc; - imm32 r7, 0xd90e108f; - - ASTAT = R0; - - CC = R1; // cc2dreg - R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac - IF CC R1 = R3; // ccmov - CC = ! CC; // cc2dreg - R4.H = R1.L + R0.L (S); // dsp32alu - IF CC R3 = R2; // ccmov - CC = R0 < R1; // ccflag - R4.L = R5.L << 1; // dsp32shiftimm - IF CC R4 = R5; // ccmov - CC = R2 == R3; // ccflag - R7 = R1.L * R4.L, R6 = R1.H * R4.H; // dsp32mult - IF CC R4 = R5; // ccmov - CC = R0; // cc2dreg - A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac - IF !CC JUMP LABEL1; // branch on - CC = ! CC; // cc2dreg - P1.L = 0x3000; // ldimmhalf - IF !CC JUMP LABEL2 (BP); // branch -LABEL1: - R6 = R6 + R2; - JUMP.S END; -LABEL2: - R7 = R5 - R7; - CC = R0 < R1; // ccflag - P2 = A0.w; - IF CC JUMP END (BP); // branch - P3 = A1.w; - R5 = R5 + R7; - -END: - - CHECKREG r0, 0xA08D2311; - CHECKREG r1, 0x07300007; - CHECKREG r2, 0x00011557; - CHECKREG r3, 0x07300007; - CHECKREG r4, 0x609950AA; - CHECKREG r5, 0x609950AA; - CHECKREG r6, 0x056C9760; - CHECKREG r7, 0x6094E75E; - CHECKREG p1, 0x00003000; - CHECKREG p2, 0x01382894; - CHECKREG p3, 0x00000000; - - imm32 r0, 0x408d2711; - imm32 r1, 0x15124040; - imm32 r2, 0x62661557; - imm32 r3, 0x073b0007; - imm32 r4, 0x01f49088; - imm32 r5, 0x6e2959aa; - imm32 r6, 0xa0b506cc; - imm32 r7, 0x00000002; - - CC = R1; // cc2dreg - - R2 = ROT R2 BY 1; // dsp32shiftim_rot - CC = ! CC; // cc2dreg - R3 >>= R7; // alu2op sft - R3 = ROT R0 BY -3; // dsp32shiftim_rot - CC = R0 < R1; // ccflag - R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair - R6 = ROT R4 BY 5; // dsp32shiftim_rot - CC = R2 == R3; // ccflag - P1 = R1; // regmv - IF CC R4 = R5; // ccmov - CC = R0; // cc2dreg - R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft - R7 = ROT R6 BY R7.L; // dsp32shiftim_rot - - CHECKREG r0, 0x408D2711; - CHECKREG r1, 0x2ACFF368; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0xFFFC8440; - CHECKREG r4, 0x01F49088; - CHECKREG r5, 0x6E2959AA; - CHECKREG r6, 0x15BD33A8; - CHECKREG r7, 0x56F4CEA2; - CHECKREG p1, 0x15124040; - - pass diff --git a/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_sn.s b/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_sn.s deleted file mode 100644 index 8002cbd..0000000 --- a/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_sn.s +++ /dev/null @@ -1,118 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_sn/c_cc_flagdreg_mvbrsft_sn.dsp -// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft) -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0xa08d2311; - imm32 r1, 0x10120040; - imm32 r2, 0x62b61557; - imm32 r3, 0x07300007; - imm32 r4, 0x00740088; - imm32 r5, 0x609950aa; - imm32 r6, 0x20bb06cc; - imm32 r7, 0xd90e108f; - - imm32 p1, 0x1401101f; - imm32 p2, 0x3204108e; - imm32 p3, 0xd93f1084; - imm32 p4, 0xeb04106f; - imm32 p5, 0xa90e5089; - - ASTAT = R0; - - CC = R1; // cc2dreg - R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac - I0 = P1; // regmv - IF CC R1 = R3; // ccmov - CC = ! CC; // cc2dreg - R4.H = R1.L + R0.L (S); // dsp32alu - M0 = P2; // regmv - IF CC R3 = R2; // ccmov - CC = R0 < R1; // ccflag - R4.L = R5.L << 1; // dsp32shiftimm - I0 += M0; // dagmodim - R2 = R0 + R2; // comp3op dr plus dr - IF CC R4 = R5; // ccmov - CC = R2 == R3; // ccflag - R7 = R1.L * R4.L, R6 = R1.H * R4.H; // dsp32mult - R5 = R0 + R2; // comp3op dr plus dr - BITCLR( R6 , 1 ); - IF CC R4 = R5; // ccmov - CC = R0; // cc2dreg - A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac - IF !CC JUMP LABEL1; // branch on - CC = ! CC; // cc2dreg - P1.L = 0x3000; // ldimmhalf - A0 += A1 (W32); // dsp32alu a0 + a1 - IF !CC JUMP LABEL2 (BP); // branch -LABEL1: - R6 = R6 + R2; - JUMP.S END; -LABEL2: - R7 = R5 - R7; - CC = R0 < R1; // ccflag - P2 = A0.w; - IF CC JUMP END (BP); // branch - P3 = A1.w; - R5 = R5 + R7; - -END: - - CHECKREG r0, 0xA08D2311; - CHECKREG r1, 0x07300007; - CHECKREG r2, 0xA08E3868; - CHECKREG r3, 0x07300007; - CHECKREG r4, 0x609950AA; - CHECKREG r5, 0x411B5B79; - CHECKREG r6, 0x056C9760; - CHECKREG r7, 0x4116F22D; - CHECKREG p1, 0x14013000; - CHECKREG p2, 0x033352A4; - CHECKREG p3, 0xD93F1084; - - imm32 r0, 0x408d2711; - imm32 r1, 0x15124040; - imm32 r2, 0x62661557; - imm32 r3, 0x073b0007; - imm32 r4, 0x01f49088; - imm32 r5, 0x6e2959aa; - imm32 r6, 0xa0b506cc; - imm32 r7, 0x00000002; - - CC = R1; // cc2dreg - P1 = -15; // compi2opp_pr_eq_i7 - R2 = ROT R2 BY 1; // dsp32shiftim_rot - CC = ! CC; // cc2dreg - R3 >>= R7; // alu2op sft - R4 = ROT R0 BY -3; // dsp32shiftim_rot - CC = R0 < R1; // ccflag - R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair - R5 = R0 + R2; // comp3op dr plus dr - R6 = ROT R4 BY 5; // dsp32shiftim_rot - CC = R2 == R3; // ccflag - P2 = R1; // regmv - R4.H = R1.L + R3.H (S); // dsp32alu - I0 = P1; // regmv - IF CC R4 = R5; // ccmov - CC = R0; // cc2dreg - R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft - I0 += 2; - P3 = I0; - R3.L = R5.L << 1; // dsp32shiftimm - R7 = ROT R6 BY R7.L; // dsp32shiftim_rot - - CHECKREG r0, 0x408D2711; - CHECKREG r1, 0x2ACFF368; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0xFFFD4E22; - CHECKREG r4, 0x403DA4E2; - CHECKREG r5, 0x408D2711; - CHECKREG r6, 0x15BD33A8; - CHECKREG r7, 0x56F4CEA2; - CHECKREG p1, 0xFFFFFFF1; - CHECKREG p2, 0x15124040; - CHECKREG p3, 0xFFFFFFF3; - - pass diff --git a/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft.s b/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft.s deleted file mode 100644 index 7ad1823..0000000 --- a/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft.s +++ /dev/null @@ -1,83 +0,0 @@ -//Original:/testcases/core/c_cc_regmvlogi_mvbrsft/c_cc_regmvlogi_mvbrsft.dsp -// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x00000020; // cc=1 -imm32 r1, 0x00000000; // cc=0 -imm32 r2, 0x62b61557; -imm32 r3, 0x07300007; -imm32 r4, 0x00740088; -imm32 r5, 0x609950aa; -imm32 r6, 0x20bb06cc; -imm32 r7, 0xd90e108f; - - - ASTAT = R0; // cc=1 REGMV - IF CC R1 = R3; // ccmov - ASTAT = R1; // cc=0 REGMV - IF CC R3 = R2; // ccmv - CC = R0 < R1; // ccflag - IF CC R4 = R5; // ccmv - CC = ! BITTST( R0 , 4 ); // cc = 0 - IF CC R4 = R5; // ccmv - CC = BITTST ( R1 , 4 ); // cc = 0 - IF !CC JUMP LABEL1; // branch - CC = ! CC; - IF !CC JUMP LABEL2 (BP); // branch -LABEL1: - R6 = R0 + R2; - JUMP.S END; -LABEL2: - R7 = R5 - R3; - CC = R0 < R1; // ccflag - IF CC JUMP END (BP); // branch on - R4 = R5 + R7; - -END: - -CHECKREG r0, 0x00000020; -CHECKREG r1, 0x07300007; -CHECKREG r2, 0x62B61557; -CHECKREG r3, 0x07300007; -CHECKREG r4, 0x609950AA; -CHECKREG r5, 0x609950AA; -CHECKREG r6, 0x62B61577; -CHECKREG r7, 0xD90E108F; - -imm32 r0, 0x00000020; -imm32 r1, 0x00000000; -imm32 r2, 0x62661557; -imm32 r3, 0x073b0007; -imm32 r4, 0x01f49088; -imm32 r5, 0x6e2959aa; -imm32 r6, 0xa0b506cc; -imm32 r7, 0x00000002; - - - ASTAT = R0; // cc=1 REGMV - R2 = ROT R2 BY 1; // dsp32shiftim_rot - ASTAT = R1; // cc=0 REGMV - R3 = ROT R3 BY 1; // dsp32shiftim_rot - CC = ! BITTST( R0 , 4 ); // cc = 0 - R6 = ROT R4 BY 5; // dsp32shiftim_rot - CC = BITTST ( R1 , 4 ); // cc = 0 - IF CC R4 = R5; // ccmov - CC = BITTST ( R0 , 4 ); // cc = 1 - R7 = ROT R6 BY R7.L; - -CHECKREG r0, 0x00000020; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0xC4CC2AAF; -CHECKREG r3, 0x0E76000E; -CHECKREG r4, 0x01F49088; -CHECKREG r5, 0x6E2959AA; -CHECKREG r6, 0x3E921110; -CHECKREG r7, 0xFA484440; - -pass diff --git a/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_s1.s b/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_s1.s deleted file mode 100644 index f0306c9..0000000 --- a/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_s1.s +++ /dev/null @@ -1,98 +0,0 @@ -//Original:/testcases/core/c_cc_regmvlogi_mvbrsft_s1/c_cc_regmvlogi_mvbrsft_s1.dsp -// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft) -# mach: bfin - -.include "testutils.inc" - start - - -A0 = 0; -A1 = 0; - -imm32 r0, 0x00000020; // cc=1 -imm32 r1, 0x00000000; // cc=0 -imm32 r2, 0x62b61557; -imm32 r3, 0x07300007; -imm32 r4, 0x00740088; -imm32 r5, 0x609950aa; -imm32 r6, 0x20bb06cc; -imm32 r7, 0x00000002; - - -ASTAT = R0; // cc=1 REGMV -R5 = R0 + R2; // comp3op dr plus dr -IF CC R1 = R3; // ccmov -ASTAT = R1; // cc=0 REGMV -R4 >>= R7; // alu2op sft -IF CC R3 = R2; // ccmv -CC = R0 < R1; // ccflag -R3.H = R1.L + R3.H (S); // dsp32alu -IF CC R4 = R5; // ccmv -CC = ! BITTST( R0 , 4 ); // cc = 0 -R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft -IF CC R4 = R5; // ccmv -CC = BITTST ( R1 , 4 ); // cc = 0 -R3.L = R5.L << 1; // dsp32shiftim -IF !CC JUMP LABEL1; // branch -CC = ! CC; -R1 = ( A1 = R7.L * R4.L ), R0 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair -IF !CC JUMP LABEL2 (BP); // branch -LABEL1: - R2 = R0 + R2; -JUMP.S END; -LABEL2: - R7 = R5 - R3; -CC = R0 < R1; // ccflag -R5 = R0 + R2; // comp3op dr plus dr -IF CC JUMP END (BP); // branch on -R4 = R5 + R7; - -END: - -CHECKREG r0, 0x00000020; -CHECKREG r1, 0x0398000C; -CHECKREG r2, 0x62B61577; -CHECKREG r3, 0x07372AEE; -CHECKREG r4, 0x62B61577; -CHECKREG r5, 0x62B61577; -CHECKREG r6, 0xFC680013; -CHECKREG r7, 0x00000002; - -imm32 r0, 0x00000020; -imm32 r1, 0x00000000; -imm32 r2, 0x62661557; -imm32 r3, 0x073b0007; -imm32 r4, 0x01f49088; -imm32 r5, 0x6e2959aa; -imm32 r6, 0xa0b506cc; -imm32 r7, 0x00000002; - - - ASTAT = R0; // cc=1 REGMV - R4.H = R1.L + R0.L (S); // dsp32alu - R2 = ROT R2 BY 1; // dsp32shiftim_rot - ASTAT = R1; // cc=0 REGMV - A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac - R3 = ROT R3 BY 1; // dsp32shiftim_rot - CC = ! BITTST( R0 , 4 ); // cc = 0 - R4.L = R5.L << 1; // dsp32shiftimm - R6 = ROT R4 BY 5; // dsp32shiftim_rot - CC = BITTST ( R1 , 4 ); // cc = 0 - R7 = R0 + R2; // comp3op dr plus dr - IF CC R4 = R5; // ccmov - A0 += A1 (W32); // dsp32alu a0 + a1 - CC = BITTST ( R0 , 4 ); // cc = 1 - R5 = ROT R6 BY R7.L; - R0 = A0.w; - R1 = A1.w; - -CHECKREG r0, 0x026B943C; -CHECKREG r1, 0x00025592; -CHECKREG r2, 0xC4CC2AAF; -CHECKREG r3, 0x0E76000E; -CHECKREG r4, 0x0020B354; -CHECKREG r5, 0x35480105; -CHECKREG r6, 0x04166A90; -CHECKREG r7, 0xC4CC2ACF; - -pass diff --git a/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_sn.S b/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_sn.S deleted file mode 100644 index 8b04188..0000000 --- a/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_sn.S +++ /dev/null @@ -1,127 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_cc_regmvlogi_mvbrsft_sn/c_cc_regmvlogi_mvbrsft_sn.dsp -// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft) -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - INIT_I_REGS 0; - INIT_M_REGS 0; - INIT_L_REGS 0; - INIT_B_REGS 0; - INIT_R_REGS 0; - INIT_P_REGS 0; - ASTAT = R0; - A0 = A1 = 0; - - imm32 r0, (_CC); // cc=1 - imm32 r1, 0x00000000; // cc=0 - imm32 r2, 0x62b61557; - imm32 r3, 0x07300007; - imm32 r4, 0x00740088; - imm32 r5, 0x609950aa; - imm32 r6, 0x20bb06cc; - imm32 r7, 0x00000002; - - A0 = R4; - A1 = R6; - - ASTAT = R0; // cc=1 REGMV - P2 = R2; - R2 = R0 + R2; // comp3op dr plus dr - M0 = P2; // regmv - IF CC R1 = R3; // ccmov - ASTAT = R1; // cc=0 REGMV - R3 >>= R7; // alu2op sft - R3 = R0 + R2; // comp3op dr plus dr - I0 = R5; - IF CC R3 = R2; // ccmv - CC = R0 < R1; // ccflag - R3.H = R1.L + R3.H (S); // dsp32alu - R5 = ( A1 = R7.L * R4.H ), R4 = ( A0 = R7.H * R4.L ); // dsp32mac pair - IF CC R4 = R5; // ccmv - CC = ! BITTST( R0 , 4 ); // cc = 0 - R0 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft - I0 += 2; // dagmodim - IF CC R4 = R5; // ccmv - CC = BITTST ( R1 , 4 ); // cc = 0 - R7.L = R5.L << 1; // dsp32shiftim - R1 = R0 +|- R1 , R5 = R0 -|+ R1 (ASR); // dsp32alu sft - P1 = A0.w; - IF !CC JUMP LABEL1; // branch - CC = ! CC; - R1 = ( A1 = R7.L * R4.L ), R0 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair - I0 += M0; // dagmodim - P2 = A1.w; - IF !CC JUMP LABEL2 (BP); // branch -LABEL1: - R2 = R0 + R2; - JUMP.S END; -LABEL2: - R7 = R5 - R3; - CC = R0 < R1; // ccflag - R6 = R0 + R2; // comp3op dr plus dr - P4 = I0; - IF CC JUMP END (BP); // branch on - R7 = R5 + R7; - -END: - - CHECKREG r0, 0x0398000C; - CHECKREG r1, 0x05640002; - CHECKREG r2, 0x664E1583; - CHECKREG r3, 0x62BD1597; - CHECKREG r4, 0x000001D0; - CHECKREG r5, 0xFE340009; - CHECKREG r6, 0xFC680013; - CHECKREG r7, 0x000003A0; - CHECKREG p1, 0x00000000; - CHECKREG p2, 0x62B61557; - CHECKREG p4, 0x00000000; - - imm32 r0, (_CC); - imm32 r1, 0x00000000; - imm32 r2, 0x62661557; - imm32 r3, 0x073b0007; - imm32 r4, 0x01f49088; - imm32 r5, 0x6e2959aa; - imm32 r6, 0xa0b506cc; - imm32 r7, 0xabd30002; - - A1 = A0 = 0; - ASTAT = R0; // cc=1 REGMV - R2.H = R3.L + R4.L (NS); // dsp32alu - R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac - R3 = ROT R2 BY 1; // dsp32shiftim_rot - ASTAT = R1; // cc=0 REGMV - A1 += R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac - R2.L = R5.L << 1; // dsp32shiftimm - R5 = ROT R3 BY 1; // dsp32shiftim_rot - CC = ! BITTST( R0 , 4 ); // cc = 0 - R4.L = R5.L << 1; // dsp32shiftimm - R0 >>= R7; // alu2op sft - A0 += A1; // dsp32alu a0 + a1 - R6 = ROT R4 BY 5; // dsp32shiftim_rot - CC = BITTST ( R1 , 4 ); // cc = 0 - R0 = R0 + R2; // comp3op dr plus dr - R5 = R3.L * R4.H, R4 = R3.H * R4.L; // dsp32mult - P1 = A0.w; - IF CC R4 = R5; // ccmov - P1.L = 0x3000; // ldimmhalf - P2 = A1.w; // regmv - CC = BITTST ( R0 , 4 ); // cc = 1 - R7 = ROT R6 BY R7.L; - - CHECKREG r0, 0x0001B354; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x0001B354; - CHECKREG r3, 0x00022AAF; - CHECKREG r4, 0xFFFEAAF0; - CHECKREG r5, 0x00A6BB98; - CHECKREG r6, 0x3E955790; - CHECKREG r7, 0xFA555E42; - CHECKREG p1, 0x07193000; - CHECKREG p2, 0x071EE3B4; - - pass diff --git a/sim/testsuite/sim/bfin/c_ccflag_a0a1.S b/sim/testsuite/sim/bfin/c_ccflag_a0a1.S deleted file mode 100644 index 8163417..0000000 --- a/sim/testsuite/sim/bfin/c_ccflag_a0a1.S +++ /dev/null @@ -1,143 +0,0 @@ -//Original:/testcases/core/c_ccflag_a0a1/c_ccflag_a0a1.dsp -// Spec Reference: ccflag a0-a1 (==, <, <=) -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - imm32 r0, 0x12345778; - imm32 r1, 0x12345678; - imm32 r2, 0x056789ab; - imm32 r3, 0x80231345; - - imm32 r4, 0x00770088; - imm32 r5, 0x009900aa; - imm32 r6, 0x00bb00cc; - imm32 r7, _UNSET; - - ASTAT = R7; - R4 = ASTAT; - A0 = R0; - A1 = R0; - -// positive a0 EQUAL to a1 - CC = A0 == A1; - R5 = ASTAT; - CC = A0 < A1; - R6 = ASTAT; - CHECKREG r4, _UNSET; - CHECKREG r5, (_AC0|_CC|_AC0_COPY|_AZ); - CHECKREG r6, (_AC0|_AC0_COPY|_AZ); - CC = A0 <= A1; - R5 = ASTAT; - CC = A0 < A1; - R6 = ASTAT; - CC = A0 <= A1; - R7 = ASTAT; - CHECKREG r5, (_AC0|_CC|_AC0_COPY|_AZ); - CHECKREG r6, (_AC0|_AC0_COPY|_AZ); - CHECKREG r7, (_AC0|_CC|_AC0_COPY|_AZ); - -// positive a0 GREATER than to positive a1 - A1 = R1; - CC = A0 == A1; - R5 = ASTAT; - CC = A0 < A1; - R6 = ASTAT; - CC = A0 <= A1; - R7 = ASTAT; - CHECKREG r5, (_AC0|_AC0_COPY); // carry - CHECKREG r6, (_AC0|_AC0_COPY); - CHECKREG r7, (_AC0|_AC0_COPY); - -// positive a0 LESS than to positive a1 - A1 = R2; - CC = A0 == A1; - R5 = ASTAT; - CC = A0 < A1; - R6 = ASTAT; - CC = A0 <= A1; - R7 = ASTAT; - CHECKREG r5, (_AC0|_AC0_COPY); - CHECKREG r6, (_AC0|_AC0_COPY); - CHECKREG r7, (_AC0|_AC0_COPY); - -// positive a0 GREATER than to neg a1 - A1 = R3; - CC = A0 == A1; - R5 = ASTAT; - CC = A0 < A1; - R6 = ASTAT; - CC = A0 <= A1; - R7 = ASTAT; - CHECKREG r5, _UNSET; - CHECKREG r6, _UNSET; - CHECKREG r7, _UNSET; - -// negative a0 and positive a1 - imm32 r0, -1; - imm32 r1, 2; - imm32 r2, -3; - imm32 r3, -4; - A0 = R0; - A1 = R1; - - R7 = 0; - ASTAT = R7; - R4 = ASTAT; - - CC = A0 == A1; - R5 = ASTAT; - CC = A0 < A1; - R6 = ASTAT; - CC = A0 <= A1; - R7 = ASTAT; - CHECKREG r4, _UNSET; - CHECKREG r5, (_AC0|_AC0_COPY|_AN); - CHECKREG r6, (_AC0|_AC0_COPY|_CC|_AN); - CHECKREG r7, (_AC0|_AC0_COPY|_CC|_AN); - -// negative a0 LESS than neg a1 - A0 = R3; - A1 = R4; - CC = A0 == A1; - R5 = ASTAT; - CC = A0 < A1; - R6 = ASTAT; - CC = A0 <= A1; - R7 = ASTAT; - CHECKREG r4, _UNSET; - CHECKREG r5, (_AC0|_AC0_COPY|_AN); - CHECKREG r6, (_AC0|_AC0_COPY|_CC|_AN); - CHECKREG r7, (_AC0|_AC0_COPY|_CC|_AN); - -// negative a0 GREATER neg a1 - A0 = R0; - A1 = R3; - CC = A0 == A1; - R5 = ASTAT; - CC = A0 < A1; - R6 = ASTAT; - CC = A0 <= A1; - R7 = ASTAT; - CHECKREG r4, _UNSET; - CHECKREG r5, (_AC0|_AC0_COPY); - CHECKREG r6, (_AC0|_AC0_COPY); - CHECKREG r7, (_AC0|_AC0_COPY); - -// negative a0 EQUAL neg imm3 - A0 = R3; - A1 = R3; - CC = A0 == A1; - R5 = ASTAT; - CC = A0 < A1; - R6 = ASTAT; - CC = A0 <= A1; - R7 = ASTAT; - CHECKREG r4, _UNSET; - CHECKREG r5, (_AC0|_CC|_AC0_COPY|_AZ); - CHECKREG r6, (_AC0|_AC0_COPY|_AZ); - CHECKREG r7, (_AC0|_CC|_AC0_COPY|_AZ); - - pass diff --git a/sim/testsuite/sim/bfin/c_ccflag_dr_dr.s b/sim/testsuite/sim/bfin/c_ccflag_dr_dr.s deleted file mode 100644 index a72cb0c..0000000 --- a/sim/testsuite/sim/bfin/c_ccflag_dr_dr.s +++ /dev/null @@ -1,299 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr/c_ccflag_dr_dr.dsp -// Spec Reference: ccflags dr-dr -# mach: bfin - -.include "testutils.inc" - start - - -imm32 r0, 0x00110022; -imm32 r1, 0x00110022; -imm32 r2, 0x00330044; -imm32 r3, 0x00550066; - -imm32 r4, 0x00770088; -imm32 r5, 0x009900aa; -imm32 r6, 0x00bb00cc; -imm32 r7, 0x00000000; - -ASTAT = R7; -R4 = ASTAT; - -// positive dreg-1 EQUAL to positive dreg-2 -CC = R0 == R1; -R5 = ASTAT; -CC = R0 < R1; -R6 = ASTAT; -CC = R0 <= R1; -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00001025; -CHECKREG r6, 0x00001005; -CHECKREG r7, 0x00001025; -CC = R0 < R1; -R4 = ASTAT; -CC = R0 <= R1 (IU); -R5 = ASTAT; -CHECKREG r4, 0x00001005; -CHECKREG r5, 0x00001025; - -// positive dreg-1 GREATER than positive dreg-2 -CC = R3 == R2; -R5 = ASTAT; -CC = R3 < R2; -R6 = ASTAT; -CC = R3 <= R2; -R7 = ASTAT; -CHECKREG r5, 0x00001004; -CHECKREG r6, 0x00001004; -CHECKREG r7, 0x00001004; -CC = R3 < R2 (IU); -R4 = ASTAT; -CC = R3 <= R2 (IU); -R5 = ASTAT; -CHECKREG r4, 0x00001004; -CHECKREG r5, 0x00001004; - - -// positive dreg-1 LESS than positive dreg-2 -CC = R2 == R3; -R5 = ASTAT; -CC = R2 < R3; -R6 = ASTAT; -CC = R2 <= R3; -R7 = ASTAT; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000022; -CHECKREG r7, 0x00000022; -CC = R2 < R3; -R4 = ASTAT; -CC = R2 <= R3; -R5 = ASTAT; -CHECKREG r4, 0x00000022; -CHECKREG r5, 0x00000022; - -imm32 r0, 0x01230123; -imm32 r1, 0x81230123; -imm32 r2, 0x04560456; -imm32 r3, 0x87890789; -// operate on negative number -R7 = 0; -ASTAT = R7; -R4 = ASTAT; - -// positive dreg-1 GREATER than negative dreg-2 -CC = R0 == R1; -R5 = ASTAT; -CC = R0 < R1; -R6 = ASTAT; -CC = R0 <= R1; -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// negative dreg-1 LESS than POSITIVE dreg-2 small -CC = R3 == R2; -R5 = ASTAT; -CC = R3 < R2; -R6 = ASTAT; -CC = R3 <= R2; -R7 = ASTAT; -CHECKREG r5, 0x00001006; -CHECKREG r6, 0x00001026; -CHECKREG r7, 0x00001026; - -// negative dreg-1 GREATER than negative dreg-2 -CC = R1 == R3; -R5 = ASTAT; -CC = R1 < R3; -R6 = ASTAT; -CC = R1 <= R3; -R7 = ASTAT; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000022; -CHECKREG r7, 0x00000022; - -// negative dreg-1 LESS than negative dreg-2 -CC = R3 == R1; -R5 = ASTAT; -CC = R3 < R1; -R6 = ASTAT; -CC = R3 <= R1; -R7 = ASTAT; -CHECKREG r5, 0x00001004; -CHECKREG r6, 0x00001004; -CHECKREG r7, 0x00001004; - - -imm32 r0, 0x80230123; -imm32 r1, 0x00230123; -imm32 r2, 0x80560056; -imm32 r3, 0x00890089; -// operate on negative number -R7 = 0; -ASTAT = R7; -R4 = ASTAT; - -// negative dreg-1 LESS than POSITIVE dreg-2 -CC = R2 == R3; -R5 = ASTAT; -CC = R2 < R3; -R6 = ASTAT; -CC = R2 <= R3; -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00001006; // overflow and carry but not negative -CHECKREG r6, 0x00001026; // cc overflow, carry and negative -CHECKREG r7, 0x00001026; - - -imm32 r4, 0x44444444; -imm32 r5, 0x55555555; -imm32 r6, 0x66666666; -imm32 r7, 0x77777777; - -imm32 r0, 0x00000000; -imm32 r1, 0x11111111; -imm32 r2, 0x22222222; -imm32 r3, 0x33333333; - -ASTAT = R0; -R3 = ASTAT; -NOP; -CHECKREG r3, 0x00000000; - -// positive dreg-1 EQUAL to positive dreg-2 -CC = R4 == R5; -R0 = ASTAT; -CC = R4 < R5; -R1 = ASTAT; -CC = R4 <= R5; -R2 = ASTAT; -CC = R4 < R5; -R3 = ASTAT; -CHECKREG r0, 0x00000002; -CHECKREG r1, 0x00000022; -CHECKREG r2, 0x00000022; -CHECKREG r3, 0x00000022; -CC = R4 <= R5; -R0 = ASTAT; -NOP; -CHECKREG r0, 0x00000022; - -// positive dreg-1 GREATER than positive dreg-2 -CC = R7 == R6; -R0 = ASTAT; -CC = R7 < R6; -R1 = ASTAT; -CC = R7 <= R6; -R2 = ASTAT; -CC = R7 < R6; -R3 = ASTAT; -CHECKREG r0, 0x00001004; -CHECKREG r1, 0x00001004; -CHECKREG r2, 0x00001004; -CHECKREG r3, 0x00001004; -CC = R7 <= R6 (IU); -R0 = ASTAT; -NOP; -CHECKREG r0, 0x00001004; - - -// positive dreg-1 LESS than positive dreg-2 -CC = R6 == R7; -R0 = ASTAT; -CC = R6 < R7; -R1 = ASTAT; -CC = R6 <= R7; -R2 = ASTAT; -CC = R6 < R7; -R3 = ASTAT; -CHECKREG r0, 0x00000002; -CHECKREG r1, 0x00000022; -CHECKREG r2, 0x00000022; -CHECKREG r3, 0x00000022; -CC = R6 <= R7; -R0 = ASTAT; -NOP; -CHECKREG r0, 0x00000022; - -imm32 r4, 0x01230123; -imm32 r5, 0x81230123; -imm32 r6, 0x04560456; -imm32 r7, 0x87890789; -// operate on negative number -R0 = 0; -ASTAT = R0; -R3 = ASTAT; -CHECKREG r3, 0x00000000; - -// positive dreg-1 GREATER than negative dreg-2 -CC = R4 == R5; -R1 = ASTAT; -CC = R4 < R5; -R2 = ASTAT; -CC = R4 <= R5; -R3 = ASTAT; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; - -// negative dreg-1 LESS than POSITIVE dreg-2 small -CC = R7 == R6; -R0 = ASTAT; -CC = R7 < R6; -R1 = ASTAT; -CC = R7 <= R6; -R2 = ASTAT; -CHECKREG r0, 0x00001006; -CHECKREG r1, 0x00001026; -CHECKREG r2, 0x00001026; - -// negative dreg-1 GREATER than negative dreg-2 -CC = R5 == R7; -R0 = ASTAT; -CC = R5 < R7; -R1 = ASTAT; -CC = R5 <= R7; -R2 = ASTAT; -CHECKREG r0, 0x00000002; -CHECKREG r1, 0x00000022; -CHECKREG r2, 0x00000022; - -// negative dreg-1 LESS than negative dreg-2 -CC = R7 == R5; -R1 = ASTAT; -CC = R7 < R5; -R2 = ASTAT; -CC = R7 <= R5; -R3 = ASTAT; -CHECKREG r1, 0x00001004; -CHECKREG r2, 0x00001004; -CHECKREG r3, 0x00001004; - - -imm32 r4, 0x80230123; -imm32 r5, 0x00230123; -imm32 r6, 0x80560056; -imm32 r7, 0x00890089; -// operate on negative number -R3 = 0; -ASTAT = R3; -R0 = ASTAT; - -// negative dreg-1 LESS than POSITIVE dreg-2 -CC = R6 == R7; -R1 = ASTAT; -CC = R6 < R7; -R2 = ASTAT; -CC = R6 <= R7; -R3 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00001006; // overflow and carry but not negative -CHECKREG r2, 0x00001026; // cc overflow, carry and negative -CHECKREG r3, 0x00001026; - - -pass; diff --git a/sim/testsuite/sim/bfin/c_ccflag_dr_dr_uu.s b/sim/testsuite/sim/bfin/c_ccflag_dr_dr_uu.s deleted file mode 100644 index 2709c89..0000000 --- a/sim/testsuite/sim/bfin/c_ccflag_dr_dr_uu.s +++ /dev/null @@ -1,299 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr_uu/c_ccflag_dr_dr_uu.dsp -// Spec Reference: ccflags dr-dr_uu -# mach: bfin - -.include "testutils.inc" - start - - -imm32 r0, 0x00110022; -imm32 r1, 0x00110022; -imm32 r2, 0x00330044; -imm32 r3, 0x00550066; - -imm32 r4, 0x00770088; -imm32 r5, 0x009900aa; -imm32 r6, 0x00bb00cc; -imm32 r7, 0x00000000; - -ASTAT = R7; -R4 = ASTAT; - -// positive dreg-1 EQUAL to positive dreg-2 -CC = R0 == R1; -R5 = ASTAT; -CC = R0 < R1 (IU); -R6 = ASTAT; -CC = R0 <= R1 (IU); -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00001025; -CHECKREG r6, 0x00001005; -CHECKREG r7, 0x00001025; -CC = R0 < R1 (IU); -R4 = ASTAT; -CC = R0 <= R1 (IU); -R5 = ASTAT; -CHECKREG r4, 0x00001005; -CHECKREG r5, 0x00001025; - -// positive dreg-1 GREATER than positive dreg-2 -CC = R3 == R2; -R5 = ASTAT; -CC = R3 < R2 (IU); -R6 = ASTAT; -CC = R3 <= R2 (IU); -R7 = ASTAT; -CHECKREG r5, 0x00001004; -CHECKREG r6, 0x00001004; -CHECKREG r7, 0x00001004; -CC = R3 < R2 (IU); -R4 = ASTAT; -CC = R3 <= R2 (IU); -R5 = ASTAT; -CHECKREG r4, 0x00001004; -CHECKREG r5, 0x00001004; - - -// positive dreg-1 LESS than positive dreg-2 -CC = R2 == R3; -R5 = ASTAT; -CC = R2 < R3 (IU); -R6 = ASTAT; -CC = R2 <= R3 (IU); -R7 = ASTAT; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000022; -CHECKREG r7, 0x00000022; -CC = R2 < R3 (IU); -R4 = ASTAT; -CC = R2 <= R3 (IU); -R5 = ASTAT; -CHECKREG r4, 0x00000022; -CHECKREG r5, 0x00000022; - -imm32 r0, 0x01230123; -imm32 r1, 0x81230123; -imm32 r2, 0x04560456; -imm32 r3, 0x87890789; -// operate on negative number -R7 = 0; -ASTAT = R7; -R4 = ASTAT; - -// positive dreg-1 GREATER than negative dreg-2 -CC = R0 == R1; -R5 = ASTAT; -CC = R0 < R1 (IU); -R6 = ASTAT; -CC = R0 <= R1 (IU); -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000022; -CHECKREG r7, 0x00000022; - -// negative dreg-1 LESS than POSITIVE dreg-2 small -CC = R3 == R2; -R5 = ASTAT; -CC = R3 < R2 (IU); -R6 = ASTAT; -CC = R3 <= R2 (IU); -R7 = ASTAT; -CHECKREG r5, 0x00001006; -CHECKREG r6, 0x00001004; -CHECKREG r7, 0x00001004; - -// negative dreg-1 GREATER than negative dreg-2 -CC = R1 == R3; -R5 = ASTAT; -CC = R1 < R3 (IU); -R6 = ASTAT; -CC = R1 <= R3 (IU); -R7 = ASTAT; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000022; -CHECKREG r7, 0x00000022; - -// negative dreg-1 LESS than negative dreg-2 -CC = R3 == R1; -R5 = ASTAT; -CC = R3 < R1 (IU); -R6 = ASTAT; -CC = R3 <= R1 (IU); -R7 = ASTAT; -CHECKREG r5, 0x00001004; -CHECKREG r6, 0x00001004; -CHECKREG r7, 0x00001004; - - -imm32 r0, 0x80230123; -imm32 r1, 0x00230123; -imm32 r2, 0x80560056; -imm32 r3, 0x00890089; -// operate on negative number -R7 = 0; -ASTAT = R7; -R4 = ASTAT; - -// negative dreg-1 LESS than POSITIVE dreg-2 -CC = R2 == R3; -R5 = ASTAT; -CC = R2 < R3 (IU); -R6 = ASTAT; -CC = R2 <= R3 (IU); -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00001006; // overflow and carry but not negative -CHECKREG r6, 0x00001004; // cc overflow, carry and negative -CHECKREG r7, 0x00001004; - - -imm32 r4, 0x44444444; -imm32 r5, 0x55555555; -imm32 r6, 0x66666666; -imm32 r7, 0x77777777; - -imm32 r0, 0x00000000; -imm32 r1, 0x11111111; -imm32 r2, 0x22222222; -imm32 r3, 0x33333333; - -ASTAT = R0; -R3 = ASTAT; -NOP; -CHECKREG r3, 0x00000000; - -// positive dreg-1 EQUAL to positive dreg-2 -CC = R4 == R5; -R0 = ASTAT; -CC = R4 < R5 (IU); -R1 = ASTAT; -CC = R4 <= R5 (IU); -R2 = ASTAT; -CC = R4 < R5 (IU); -R3 = ASTAT; -CHECKREG r0, 0x00000002; -CHECKREG r1, 0x00000022; -CHECKREG r2, 0x00000022; -CHECKREG r3, 0x00000022; -CC = R4 <= R5 (IU); -R0 = ASTAT; -NOP; -CHECKREG r0, 0x00000022; - -// positive dreg-1 GREATER than positive dreg-2 -CC = R7 == R6; -R0 = ASTAT; -CC = R7 < R6 (IU); -R1 = ASTAT; -CC = R7 <= R6 (IU); -R2 = ASTAT; -CC = R7 < R6 (IU); -R3 = ASTAT; -CHECKREG r0, 0x00001004; -CHECKREG r1, 0x00001004; -CHECKREG r2, 0x00001004; -CHECKREG r3, 0x00001004; -CC = R7 <= R6 (IU); -R0 = ASTAT; -NOP; -CHECKREG r0, 0x00001004; - - -// positive dreg-1 LESS than positive dreg-2 -CC = R6 == R7; -R0 = ASTAT; -CC = R6 < R7 (IU); -R1 = ASTAT; -CC = R6 <= R7 (IU); -R2 = ASTAT; -CC = R6 < R7 (IU); -R3 = ASTAT; -CHECKREG r0, 0x00000002; -CHECKREG r1, 0x00000022; -CHECKREG r2, 0x00000022; -CHECKREG r3, 0x00000022; -CC = R6 <= R7 (IU); -R0 = ASTAT; -NOP; -CHECKREG r0, 0x00000022; - -imm32 r4, 0x01230123; -imm32 r5, 0x81230123; -imm32 r6, 0x04560456; -imm32 r7, 0x87890789; -// operate on negative number -R0 = 0; -ASTAT = R0; -R3 = ASTAT; -CHECKREG r3, 0x00000000; - -// positive dreg-1 GREATER than negative dreg-2 -CC = R4 == R5; -R1 = ASTAT; -CC = R4 < R5 (IU); -R2 = ASTAT; -CC = R4 <= R5 (IU); -R3 = ASTAT; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000022; -CHECKREG r3, 0x00000022; - -// negative dreg-1 LESS than POSITIVE dreg-2 small -CC = R7 == R6; -R0 = ASTAT; -CC = R7 < R6 (IU); -R1 = ASTAT; -CC = R7 <= R6 (IU); -R2 = ASTAT; -CHECKREG r0, 0x00001006; -CHECKREG r1, 0x00001004; -CHECKREG r2, 0x00001004; - -// negative dreg-1 GREATER than negative dreg-2 -CC = R5 == R7; -R0 = ASTAT; -CC = R5 < R7 (IU); -R1 = ASTAT; -CC = R5 <= R7 (IU); -R2 = ASTAT; -CHECKREG r0, 0x00000002; -CHECKREG r1, 0x00000022; -CHECKREG r2, 0x00000022; - -// negative dreg-1 LESS than negative dreg-2 -CC = R7 == R5; -R1 = ASTAT; -CC = R7 < R5 (IU); -R2 = ASTAT; -CC = R7 <= R5 (IU); -R3 = ASTAT; -CHECKREG r1, 0x00001004; -CHECKREG r2, 0x00001004; -CHECKREG r3, 0x00001004; - - -imm32 r4, 0x80230123; -imm32 r5, 0x00230123; -imm32 r6, 0x80560056; -imm32 r7, 0x00890089; -// operate on negative number -R3 = 0; -ASTAT = R3; -R0 = ASTAT; - -// negative dreg-1 LESS than POSITIVE dreg-2 -CC = R6 == R7; -R1 = ASTAT; -CC = R6 < R7 (IU); -R2 = ASTAT; -CC = R6 <= R7 (IU); -R3 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00001006; // overflow and carry but not negative -CHECKREG r2, 0x00001004; // cc overflow, carry and negative -CHECKREG r3, 0x00001004; - - -pass; diff --git a/sim/testsuite/sim/bfin/c_ccflag_dr_imm3.s b/sim/testsuite/sim/bfin/c_ccflag_dr_imm3.s deleted file mode 100644 index e584b80..0000000 --- a/sim/testsuite/sim/bfin/c_ccflag_dr_imm3.s +++ /dev/null @@ -1,224 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3/c_ccflag_dr_imm3.dsp -// Spec Reference: ccflag dr-imm3 -# mach: bfin - -.include "testutils.inc" - start - - -imm32 r0, 0x00000001; -imm32 r1, 0x00000002; -imm32 r2, 0x00000003; -imm32 r3, 0x00000004; - -imm32 r4, 0x00770088; -imm32 r5, 0x009900aa; -imm32 r6, 0x00bb00cc; -imm32 r7, 0x00000000; - -ASTAT = R7; -R4 = ASTAT; - -// positive dreg EQUAL to positive imm3 -CC = R0 == 1; -R5 = ASTAT; -CC = R0 < 1; -R6 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00001025; -CHECKREG r6, 0x00001005; -CC = R0 <= 1; -R5 = ASTAT; -CC = R0 < 1; -R6 = ASTAT; -CC = R0 <= 1; -R7 = ASTAT; -CHECKREG r5, 0x00001025; -CHECKREG r6, 0x00001005; -CHECKREG r7, 0x00001025; - -// positive dreg GREATER than to positive imm3 -CC = R1 == 1; -R5 = ASTAT; -CC = R1 < 1; -R6 = ASTAT; -CC = R1 <= 1; -R7 = ASTAT; -CHECKREG r5, 0x00001004; // carry -CHECKREG r6, 0x00001004; -CHECKREG r7, 0x00001004; - -// positive dreg LESS than to positive imm3 -CC = R0 == 2; -R5 = ASTAT; -CC = R0 < 2; -R6 = ASTAT; -CC = R0 <= 2; -R7 = ASTAT; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000022; -CHECKREG r7, 0x00000022; - -// positive dreg GREATER than to neg imm3 -CC = R2 == -4; -R5 = ASTAT; -CC = R2 < -4; -R6 = ASTAT; -CC = R2 <= -4; -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, -1; -imm32 r1, -2; -imm32 r2, -3; -imm32 r3, -4; -// negative dreg and positive imm3 -R7 = 0; -ASTAT = R7; -R4 = ASTAT; - -CC = R3 == 1; -R5 = ASTAT; -CC = R3 < 1; -R6 = ASTAT; -CC = R3 <= 1; -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00001006; -CHECKREG r6, 0x00001026; -CHECKREG r7, 0x00001026; - -// negative dreg LESS than neg imm3 -CC = R2 == -1; -R4 = ASTAT; -CC = R2 < -1; -R5 = ASTAT; -CC = R2 <= -1; -R6 = ASTAT; -CHECKREG r4, 0x00000002; -CHECKREG r5, 0x00000022; -CHECKREG r6, 0x00000022; - -// negative dreg GREATER neg imm3 -CC = R0 == -4; -R4 = ASTAT; -CC = R0 < -4; -R5 = ASTAT; -CC = R0 <= -4; -R6 = ASTAT; -CHECKREG r4, 0x00001004; -CHECKREG r5, 0x00001004; -CHECKREG r6, 0x00001004; - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; - -imm32 r4, 0x00000001; -imm32 r5, 0x00000002; -imm32 r6, 0x00000003; -imm32 r7, 0x00000004; - -ASTAT = R0; -R3 = ASTAT; - -// positive dreg EQUAL to positive imm3 -CC = R4 == 1; -R1 = ASTAT; -CC = R4 < 1; -R2 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00001025; -CHECKREG r2, 0x00001005; -CC = R4 <= 1; -R1 = ASTAT; -CC = R4 < 1; -R2 = ASTAT; -CC = R4 <= 1; -R3 = ASTAT; -CHECKREG r1, 0x00001025; -CHECKREG r2, 0x00001005; -CHECKREG r3, 0x00001025; - -// positive dreg GREATER than to positive imm3 -CC = R5 == 1; -R1 = ASTAT; -CC = R5 < 1; -R2 = ASTAT; -CC = R5 <= 1; -R3 = ASTAT; -CHECKREG r1, 0x00001004; // carry -CHECKREG r2, 0x00001004; -CHECKREG r3, 0x00001004; - -// positive dreg LESS than to positive imm3 -CC = R6 == 2; -R1 = ASTAT; -CC = R6 < 2; -R2 = ASTAT; -CC = R6 <= 2; -R3 = ASTAT; -CHECKREG r1, 0x00001004; -CHECKREG r2, 0x00001004; -CHECKREG r3, 0x00001004; - -// positive dreg GREATER than to neg imm3 -CC = R6 == -4; -R1 = ASTAT; -CC = R6 < -4; -R2 = ASTAT; -CC = R6 <= -4; -R3 = ASTAT; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; - -imm32 r4, -1; -imm32 r5, -2; -imm32 r6, -3; -imm32 r7, -4; -// negative dreg and positive imm3 -R3 = 0; -ASTAT = R3; -R0 = ASTAT; - -CC = R7 == 1; -R1 = ASTAT; -CC = R7 < 1; -R2 = ASTAT; -CC = R7 <= 1; -R3 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00001006; -CHECKREG r2, 0x00001026; -CHECKREG r3, 0x00001026; - -// negative dreg LESS than neg imm3 -CC = R6 == -1; -R0 = ASTAT; -CC = R6 < -1; -R1 = ASTAT; -CC = R6 <= -1; -R2 = ASTAT; -CHECKREG r0, 0x00000002; -CHECKREG r1, 0x00000022; -CHECKREG r2, 0x00000022; - -// negative dreg GREATER neg imm3 -CC = R4 == -4; -R0 = ASTAT; -CC = R4 < -4; -R1 = ASTAT; -CC = R4 <= -4; -R2 = ASTAT; -CHECKREG r0, 0x00001004; -CHECKREG r1, 0x00001004; -CHECKREG r2, 0x00001004; - - - -pass; diff --git a/sim/testsuite/sim/bfin/c_ccflag_dr_imm3_uu.s b/sim/testsuite/sim/bfin/c_ccflag_dr_imm3_uu.s deleted file mode 100644 index d4a6a48..0000000 --- a/sim/testsuite/sim/bfin/c_ccflag_dr_imm3_uu.s +++ /dev/null @@ -1,221 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3_uu/c_ccflag_dr_imm3_uu.dsp -// Spec Reference: ccflag dr-imm3 (uu) -# mach: bfin - -.include "testutils.inc" - start - - -imm32 r0, 0x00000001; -imm32 r1, 0x00000002; -imm32 r2, 0x00000003; -imm32 r3, 0x00000004; - -imm32 r4, 0x00770088; -imm32 r5, 0x009900aa; -imm32 r6, 0x00bb00cc; -imm32 r7, 0x00000000; - -ASTAT = R7; -R4 = ASTAT; - -// positive dreg EQUAL to positive imm3 -CC = R0 == 1; -R5 = ASTAT; -CC = R0 < 1; -R6 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00001025; -CHECKREG r6, 0x00001005; -CC = R0 <= 1; -R5 = ASTAT; -CC = R0 < 1 (IU); -R6 = ASTAT; -CC = R0 <= 1 (IU); -R7 = ASTAT; -CHECKREG r5, 0x00001025; -CHECKREG r6, 0x00001005; -CHECKREG r7, 0x00001025; - -// positive dreg GREATER than to positive imm3 -CC = R1 == 1; -R5 = ASTAT; -CC = R1 < 1 (IU); -R6 = ASTAT; -CC = R1 <= 1 (IU); -R7 = ASTAT; -CHECKREG r5, 0x00001004; // carry -CHECKREG r6, 0x00001004; -CHECKREG r7, 0x00001004; - -// positive dreg LESS than to positive imm3 -CC = R0 == 2; -R5 = ASTAT; -CC = R0 < 2 (IU); -R6 = ASTAT; -CC = R0 <= 2 (IU); -R7 = ASTAT; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000022; -CHECKREG r7, 0x00000022; - -// positive dreg GREATER than to neg imm3 -CC = R2 == -4; -R5 = ASTAT; -CC = R2 < 4 (IU); -R6 = ASTAT; -CC = R2 <= 4 (IU); -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000022; -CHECKREG r7, 0x00000022; - -imm32 r0, -1; -imm32 r1, -2; -imm32 r2, -3; -imm32 r3, -4; -// negative dreg and positive imm3 -R7 = 0; -ASTAT = R7; -R4 = ASTAT; - -CC = R3 == 1; -R5 = ASTAT; -CC = R3 < 1 (IU); -R6 = ASTAT; -CC = R3 <= 1 (IU); -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00001006; -CHECKREG r6, 0x00001004; -CHECKREG r7, 0x00001004; - -// negative dreg LESS than neg imm3 -CC = R2 == -1; -R4 = ASTAT; -CC = R2 < 1 (IU); -R5 = ASTAT; -CC = R2 <= 1 (IU); -R6 = ASTAT; -CHECKREG r4, 0x00000002; -CHECKREG r5, 0x00001004; -CHECKREG r6, 0x00001004; - -// negative dreg GREATER neg imm3 -CC = R0 == -2; -R4 = ASTAT; -CC = R0 < 4 (IU); -R5 = ASTAT; -CC = R0 <= 4 (IU); -R6 = ASTAT; -CHECKREG r4, 0x00001004; -CHECKREG r5, 0x00001004; -CHECKREG r6, 0x00001004; - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; - -imm32 r4, 0x00000001; -imm32 r5, 0x00000002; -imm32 r6, 0x00000003; -imm32 r7, 0x00000004; - -ASTAT = R0; -R3 = ASTAT; - -// positive dreg EQUAL to positive imm3 -CC = R4 == 1; -R1 = ASTAT; -CC = R4 < 1 (IU); -R2 = ASTAT; -CC = R4 <= 1 (IU); -R3 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00001025; -CHECKREG r2, 0x00001005; -CHECKREG r3, 0x00001025; - -// positive dreg GREATER than to positive imm3 -CC = R5 == 1; -R1 = ASTAT; -CC = R5 < 1 (IU); -R2 = ASTAT; -CC = R5 <= 1 (IU); -R3 = ASTAT; -CHECKREG r1, 0x00001004; // carry -CHECKREG r2, 0x00001004; -CHECKREG r3, 0x00001004; - -// positive dreg LESS than to positive imm3 -CC = R6 == 2; -R1 = ASTAT; -CC = R6 < 2 (IU); -R2 = ASTAT; -CC = R6 <= 2 (IU); -R3 = ASTAT; -CHECKREG r1, 0x00001004; -CHECKREG r2, 0x00001004; -CHECKREG r3, 0x00001004; - -// positive dreg GREATER than to neg imm3 -CC = R6 == -4; -R1 = ASTAT; -CC = R6 < 4 (IU); -R2 = ASTAT; -CC = R6 <= 4 (IU); -R3 = ASTAT; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000022; -CHECKREG r3, 0x00000022; - -imm32 r4, -1; -imm32 r5, -2; -imm32 r6, -3; -imm32 r7, -4; -// negative dreg and positive imm3 -R3 = 0; -ASTAT = R3; -R0 = ASTAT; - -CC = R7 == 1; -R1 = ASTAT; -CC = R7 < 1 (IU); -R2 = ASTAT; -CC = R7 <= 1 (IU); -R3 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00001006; -CHECKREG r2, 0x00001004; -CHECKREG r3, 0x00001004; - -// negative dreg LESS than neg imm3 -CC = R6 == -1; -R0 = ASTAT; -CC = R6 < 1 (IU); -R1 = ASTAT; -CC = R6 <= 1 (IU); -R2 = ASTAT; -CHECKREG r0, 0x00000002; -CHECKREG r1, 0x00001004; -CHECKREG r2, 0x00001004; - -// negative dreg GREATER neg imm3 -CC = R4 == -4; -R0 = ASTAT; -CC = R4 < 4 (IU); -R1 = ASTAT; -CC = R4 <= 4 (IU); -R2 = ASTAT; -CHECKREG r0, 0x00001004; -CHECKREG r1, 0x00001004; -CHECKREG r2, 0x00001004; - - - - - - -pass; diff --git a/sim/testsuite/sim/bfin/c_ccflag_pr_imm3.s b/sim/testsuite/sim/bfin/c_ccflag_pr_imm3.s deleted file mode 100644 index aa6a0eb..0000000 --- a/sim/testsuite/sim/bfin/c_ccflag_pr_imm3.s +++ /dev/null @@ -1,539 +0,0 @@ -//Original:/testcases/core/c_ccflag_pr_imm3/c_ccflag_pr_imm3.dsp -// Spec Reference: ccflag pr-imm3 -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -//imm32 p0, 0x00000001; -imm32 p1, 0x00000001; -imm32 p2, 0x00000002; -imm32 p3, 0x00000003; -imm32 p4, 0x00000001; -imm32 p5, 0x00000002; -imm32 sp, 0x00000003; -imm32 fp, 0x00000003; - -R0 = 0; -ASTAT = R0; -// positive dreg EQUAL to positive imm3 -CC = P1 == 1; -R0 = ASTAT; -CC = P1 < 1; -R1 = ASTAT; -CC = P1 <= 1; -R2 = ASTAT; -CC = P2 == 2; -R3 = ASTAT; -CC = P2 < 2; -R4 = ASTAT; -CC = P2 <= 2; -R5 = ASTAT; -CHECKREG r0, 0x00000020; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000020; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000020; - -CC = P3 == 3; -R0 = ASTAT; -CC = P3 < 3; -R1 = ASTAT; -CC = P3 <= 3; -R2 = ASTAT; -CC = P4 == 1; -R3 = ASTAT; -CC = P4 < 1; -R4 = ASTAT; -CC = P4 <= 1; -R5 = ASTAT; -CHECKREG r0, 0x00000020; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000020; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000020; - -CC = P5 == 2; -R0 = ASTAT; -CC = P5 < 2; -R1 = ASTAT; -CC = P5 <= 2; -R2 = ASTAT; -CC = SP == 3; -R3 = ASTAT; -CC = SP < 3; -R4 = ASTAT; -CC = SP <= 3; -R5 = ASTAT; -CHECKREG r0, 0x00000020; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000020; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000020; - -CC = FP == 3; -R5 = ASTAT; -CC = FP < 3; -R6 = ASTAT; -CC = FP <= 3; -R7 = ASTAT; -CHECKREG r5, 0x00000020; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000020; - -// positive dreg GREATER than positive imm3 -imm32 p1, 0x00000002; -imm32 p2, 0x00000002; -imm32 p3, 0x00000003; -imm32 p4, 0x00000002; -imm32 p5, 0x00000002; -imm32 sp, 0x00000003; -imm32 fp, 0x00000003; -CC = P1 == 0; -R0 = ASTAT; -CC = P1 < 0; -R1 = ASTAT; -CC = P1 <= 0; -R2 = ASTAT; -CC = P2 == 1; -R3 = ASTAT; -CC = P2 < 1; -R4 = ASTAT; -CC = P2 <= 1; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - -CC = P3 == 2; -R0 = ASTAT; -CC = P3 < 2; -R1 = ASTAT; -CC = P3 <= 2; -R2 = ASTAT; -CC = P4 == 0; -R3 = ASTAT; -CC = P4 < 0; -R4 = ASTAT; -CC = P4 <= 0; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - -CC = P5 == 1; -R0 = ASTAT; -CC = P5 < 1; -R1 = ASTAT; -CC = P5 <= 1; -R2 = ASTAT; -CC = SP == 2; -R3 = ASTAT; -CC = SP < 2; -R4 = ASTAT; -CC = SP <= 2; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - -CC = FP == 2; -R5 = ASTAT; -CC = FP < 2; -R6 = ASTAT; -CC = FP <= 2; -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// positive dreg LESS than positive imm3 -imm32 p1, 0x00000001; -imm32 p2, 0x00000002; -imm32 p3, 0x00000002; -imm32 p4, 0x00000001; -imm32 p5, 0x00000001; -imm32 sp, 0x00000002; -imm32 fp, 0x00000002; -CC = P1 == 2; -R0 = ASTAT; -CC = P1 < 2; -R1 = ASTAT; -CC = P1 <= 2; -R2 = ASTAT; -CC = P2 == 3; -R3 = ASTAT; -CC = P2 < 3; -R4 = ASTAT; -CC = P2 <= 3; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000020; -CHECKREG r5, 0x00000020; - -CC = P3 == 3; -R0 = ASTAT; -CC = P3 < 3; -R1 = ASTAT; -CC = P3 <= 3; -R2 = ASTAT; -CC = P4 == 3; -R3 = ASTAT; -CC = P4 < 3; -R4 = ASTAT; -CC = P4 <= 3; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000020; -CHECKREG r5, 0x00000020; - -CC = P5 == 3; -R0 = ASTAT; -CC = P5 < 3; -R1 = ASTAT; -CC = P5 <= 3; -R2 = ASTAT; -CC = SP == 3; -R3 = ASTAT; -CC = SP < 3; -R4 = ASTAT; -CC = SP <= 3; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000020; -CHECKREG r5, 0x00000020; - -CC = FP == 3; -R5 = ASTAT; -CC = FP < 3; -R6 = ASTAT; -CC = FP <= 3; -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000020; -CHECKREG r7, 0x00000020; - - -// positive dreg GREATER than neg imm3 -CC = P1 == -1; -R0 = ASTAT; -CC = P1 < -1; -R1 = ASTAT; -CC = P1 <= -1; -R2 = ASTAT; -CC = P2 == -2; -R3 = ASTAT; -CC = P2 < -2; -R4 = ASTAT; -CC = P2 <= -2; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - -CC = P3 == -3; -R0 = ASTAT; -CC = P3 < -3; -R1 = ASTAT; -CC = P3 <= -3; -R2 = ASTAT; -CC = P4 == -4; -R3 = ASTAT; -CC = P4 < -4; -R4 = ASTAT; -CC = P4 <= -4; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - -CC = P5 == -1; -R0 = ASTAT; -CC = P5 < -1; -R1 = ASTAT; -CC = P5 <= -1; -R2 = ASTAT; -CC = SP == -2; -R3 = ASTAT; -CC = SP < -2; -R4 = ASTAT; -CC = SP <= -2; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - -CC = FP == -4; -R5 = ASTAT; -CC = FP < -4; -R6 = ASTAT; -CC = FP <= -4; -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - - - -imm32 p1, -1; -imm32 p2, -2; -imm32 p3, -3; -imm32 p4, -4; -imm32 p5, -1; -imm32 sp, -2; -imm32 fp, -3; -// negative dreg equal negative imm3 -CC = P1 == -1; -R0 = ASTAT; -CC = P1 < -1; -R1 = ASTAT; -CC = P1 <= -1; -R2 = ASTAT; -CC = P2 == -2; -R3 = ASTAT; -CC = P2 < -2; -R4 = ASTAT; -CC = P2 <= -2; -R5 = ASTAT; -CHECKREG r0, 0x00000020; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000020; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000020; - -CC = P3 == -3; -R0 = ASTAT; -CC = P3 < -3; -R1 = ASTAT; -CC = P3 <= -3; -R2 = ASTAT; -CC = P4 == -4; -R3 = ASTAT; -CC = P4 < -4; -R4 = ASTAT; -CC = P4 <= -4; -R5 = ASTAT; -CHECKREG r0, 0x00000020; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000020; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000020; - -CC = P5 == -1; -R0 = ASTAT; -CC = P5 < -1; -R1 = ASTAT; -CC = P5 <= -1; -R2 = ASTAT; -CC = SP == -2; -R3 = ASTAT; -CC = SP < -2; -R4 = ASTAT; -CC = SP <= -2; -R5 = ASTAT; -CHECKREG r0, 0x00000020; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000020; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000020; - -CC = FP == -3; -R5 = ASTAT; -CC = FP < -3; -R6 = ASTAT; -CC = FP <= -3; -R7 = ASTAT; -CHECKREG r5, 0x00000020; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000020; - - -// negative dreg GREATER neg imm3 -imm32 p1, -1; -imm32 p2, -1; -imm32 p3, -2; -imm32 p4, -3; -imm32 p5, -1; -imm32 sp, -2; -imm32 fp, -3; -CC = P1 == -2; -R0 = ASTAT; -CC = P1 < -2; -R1 = ASTAT; -CC = P1 <= -2; -R2 = ASTAT; -CC = P2 == -3; -R3 = ASTAT; -CC = P2 < -3; -R4 = ASTAT; -CC = P2 <= -3; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - -CC = P3 == -4; -R0 = ASTAT; -CC = P3 < -4; -R1 = ASTAT; -CC = P3 <= -4; -R2 = ASTAT; -CC = P4 == -4; -R3 = ASTAT; -CC = P4 < -4; -R4 = ASTAT; -CC = P4 <= -4; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - -CC = P5 == -2; -R0 = ASTAT; -CC = P5 < -2; -R1 = ASTAT; -CC = P5 <= -2; -R2 = ASTAT; -CC = SP == -3; -R3 = ASTAT; -CC = SP < -3; -R4 = ASTAT; -CC = SP <= -3; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - -CC = FP == -4; -R5 = ASTAT; -CC = FP < -4; -R6 = ASTAT; -CC = FP <= -4; -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// negative dreg LESS than neg imm3 -imm32 p1, -2; -imm32 p2, -2; -imm32 p3, -3; -imm32 p4, -3; -imm32 p5, -4; -imm32 sp, -4; -imm32 fp, -4; -imm32 p4, -4; -CC = P1 == -1; -R0 = ASTAT; -CC = P1 < -1; -R1 = ASTAT; -CC = P1 <= -1; -R2 = ASTAT; -CC = P2 == -1; -R3 = ASTAT; -CC = P2 < -1; -R4 = ASTAT; -CC = P2 <= -1; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000020; -CHECKREG r5, 0x00000020; - -CC = P3 == -2; -R0 = ASTAT; -CC = P3 < -2; -R1 = ASTAT; -CC = P3 <= -2; -R2 = ASTAT; -CC = P4 == -2; -R3 = ASTAT; -CC = P4 < -2; -R4 = ASTAT; -CC = P4 <= -2; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000020; -CHECKREG r5, 0x00000020; - -CC = P5 == -3; -R0 = ASTAT; -CC = P5 < -3; -R1 = ASTAT; -CC = P5 <= -3; -R2 = ASTAT; -CC = SP == -3; -R3 = ASTAT; -CC = SP < -3; -R4 = ASTAT; -CC = SP <= -3; -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000020; -CHECKREG r5, 0x00000020; - -CC = FP == -3; -R5 = ASTAT; -CC = FP < -3; -R6 = ASTAT; -CC = FP <= -3; -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000020; -CHECKREG r7, 0x00000020; - - -pass diff --git a/sim/testsuite/sim/bfin/c_ccflag_pr_imm3_uu.s b/sim/testsuite/sim/bfin/c_ccflag_pr_imm3_uu.s deleted file mode 100644 index 6b18702..0000000 --- a/sim/testsuite/sim/bfin/c_ccflag_pr_imm3_uu.s +++ /dev/null @@ -1,238 +0,0 @@ -//Original:/testcases/core/c_ccflag_pr_imm3_uu/c_ccflag_pr_imm3_uu.dsp -// Spec Reference: ccflag pr-imm3 (uu) -# mach: bfin - -.include "testutils.inc" - start - - - -INIT_R_REGS 0; - - -//imm32 p0, 0x00000001; -imm32 p1, 0x00000001; -imm32 p2, 0x00000002; -imm32 p3, 0x00000003; -imm32 p4, 0x00000004; -imm32 p5, 0x00000005; -imm32 sp, 0x00000006; -imm32 fp, 0x00000007; - -R0 = 0; -ASTAT = R0; -// positive preg EQUAL to positive imm3 -CC = P1 == 1; -R0 = ASTAT; -CC = P1 < 1 (IU); -R1 = ASTAT; -CC = P1 <= 1 (IU); -R2 = ASTAT; -CC = P2 == 2; -R3 = ASTAT; -CC = P2 < 2 (IU); -R4 = ASTAT; -CC = P2 <= 2 (IU); -R5 = ASTAT; -CHECKREG r0, 0x00000020; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000020; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000020; - -CC = P3 == 3; -R0 = ASTAT; -CC = P3 < 3 (IU); -R1 = ASTAT; -CC = P3 <= 3 (IU); -R2 = ASTAT; -CC = P4 == 3; -R3 = ASTAT; -CC = P4 < 4 (IU); -R4 = ASTAT; -CC = P4 <= 4 (IU); -R5 = ASTAT; -CHECKREG r0, 0x00000020; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000020; - -CC = P5 == 3; -R0 = ASTAT; -CC = P5 < 5 (IU); -R1 = ASTAT; -CC = P5 <= 5 (IU); -R2 = ASTAT; -CC = SP == 3; -R3 = ASTAT; -CC = SP < 6 (IU); -R4 = ASTAT; -CC = SP <= 6 (IU); -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000020; - -CC = FP == 3; -R5 = ASTAT; -CC = FP < 7 (IU); -R6 = ASTAT; -CC = FP <= 7 (IU); -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000020; - -// positive preg GREATER than positive imm3 -CC = P1 == 0; -R0 = ASTAT; -CC = P1 < 0 (IU); -R1 = ASTAT; -CC = P1 <= 0 (IU); -R2 = ASTAT; -CC = P2 == 1; -R3 = ASTAT; -CC = P2 < 1 (IU); -R4 = ASTAT; -CC = P2 <= 1 (IU); -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - -CC = P3 == 2; -R0 = ASTAT; -CC = P3 < 2 (IU); -R1 = ASTAT; -CC = P3 <= 2 (IU); -R2 = ASTAT; -CC = P4 == 3; -R3 = ASTAT; -CC = P4 < 3 (IU); -R4 = ASTAT; -CC = P4 <= 3 (IU); -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - -CC = P5 == 3; -R0 = ASTAT; -CC = P5 < 4 (IU); -R1 = ASTAT; -CC = P5 <= 4 (IU); -R2 = ASTAT; -CC = SP == 3; -R3 = ASTAT; -CC = SP < 5 (IU); -R4 = ASTAT; -CC = SP <= 5 (IU); -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - -CC = FP == 3; -R5 = ASTAT; -CC = FP < 6 (IU); -R6 = ASTAT; -CC = FP <= 6 (IU); -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// positive preg LESS than positive imm3 -imm32 p1, 0x00000000; -imm32 p2, 0x00000001; -imm32 p3, 0x00000002; -imm32 p4, 0x00000003; -imm32 p5, 0x00000004; -imm32 sp, 0x00000005; -imm32 fp, 0x00000006; -CC = P1 == 2; -R0 = ASTAT; -CC = P1 < 2 (IU); -R1 = ASTAT; -CC = P1 <= 2 (IU); -R2 = ASTAT; -CC = P2 == 3; -R3 = ASTAT; -CC = P2 < 3 (IU); -R4 = ASTAT; -CC = P2 <= 3 (IU); -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000020; -CHECKREG r5, 0x00000020; - -CC = P3 == 3; -R0 = ASTAT; -CC = P3 < 4 (IU); -R1 = ASTAT; -CC = P3 <= 4 (IU); -R2 = ASTAT; -CC = P4 == 3; -R3 = ASTAT; -CC = P4 < 5 (IU); -R4 = ASTAT; -CC = P4 <= 5 (IU); -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000020; -CHECKREG r4, 0x00000020; -CHECKREG r5, 0x00000020; - -CC = P5 == 3; -R0 = ASTAT; -CC = P5 < 6 (IU); -R1 = ASTAT; -CC = P5 <= 6 (IU); -R2 = ASTAT; -CC = SP == 3; -R3 = ASTAT; -CC = SP < 7 (IU); -R4 = ASTAT; -CC = SP <= 7 (IU); -R5 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000020; -CHECKREG r5, 0x00000020; - -CC = FP == 3; -R5 = ASTAT; -CC = FP < 7 (IU); -R6 = ASTAT; -CC = FP <= 7 (IU); -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000020; -CHECKREG r7, 0x00000020; - - - - -pass diff --git a/sim/testsuite/sim/bfin/c_ccflag_pr_pr.s b/sim/testsuite/sim/bfin/c_ccflag_pr_pr.s deleted file mode 100644 index ef9db52..0000000 --- a/sim/testsuite/sim/bfin/c_ccflag_pr_pr.s +++ /dev/null @@ -1,262 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr/c_ccflag_pr_pr.dsp -// Spec Reference: ccflag pr-pr -# mach: bfin - -.include "testutils.inc" - start - -INIT_P_REGS 0; -INIT_R_REGS 0; - - -//imm32 p0, 0x00110022; -imm32 p1, 0x00110022; -imm32 p2, 0x00330044; -imm32 p3, 0x00550066; - -imm32 p4, 0x00770088; -imm32 p5, 0x009900aa; -imm32 fp, 0x00bb00cc; -imm32 sp, 0x00000000; - -R0 = 0; -ASTAT = R0; -R4 = ASTAT; - -// positive preg-1 EQUAL to positive preg-2 -CC = P2 == P1; -R5 = ASTAT; -P5 = R5; -CC = P2 < P1; -R6 = ASTAT; -CC = P2 <= P1; -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// positive preg-1 GREATER than positive preg-2 -CC = P3 == P2; -R5 = ASTAT; -CC = P3 < P2; -R6 = ASTAT; -CC = P3 <= P2; -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; -// positive preg-1 LESS than positive preg-2 -CC = P2 == P3; -R5 = ASTAT; -CC = P2 < P3; -R6 = ASTAT; -CC = P2 <= P3; -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000020; -CHECKREG r7, 0x00000020; - -//imm32 p0, 0x01230123; -imm32 p1, 0x81230123; -imm32 p2, 0x04560456; -imm32 p3, 0x87890789; -// operate on negative number -R0 = 0; -ASTAT = R0; -R4 = ASTAT; - -// positive preg-1 GREATER than negative preg-2 -CC = P2 == P1; -R5 = ASTAT; -CC = P2 < P1; -R6 = ASTAT; -CC = P2 <= P1; -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// negative preg-1 LESS than POSITIVE preg-2 small -CC = P3 == P2; -R5 = ASTAT; -CC = P3 < P2; -R6 = ASTAT; -CC = P3 <= P2; -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000020; -CHECKREG r7, 0x00000020; - -// negative preg-1 GREATER than negative preg-2 -CC = P1 == P3; -R5 = ASTAT; -CC = P1 < P3; -R6 = ASTAT; -CC = P1 <= P3; -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000020; -CHECKREG r7, 0x00000020; - -// negative preg-1 LESS than negative preg-2 -CC = P3 == P1; -R5 = ASTAT; -CC = P3 < P1; -R6 = ASTAT; -CC = P3 <= P1; -R7 = ASTAT; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - - -//imm32 p0, 0x80230123; -imm32 p1, 0x00230123; -imm32 p2, 0x80560056; -imm32 p3, 0x00890089; -// operate on negative number -R0 = 0; -ASTAT = R0; -R4 = ASTAT; - -// negative preg-1 LESS than POSITIVE preg-2 -CC = P2 == P3; -R5 = ASTAT; -CC = P2 < P3; -R6 = ASTAT; -CC = P2 <= P3; -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; // overflow and carry but not negative -CHECKREG r6, 0x00000020; // cc overflow, carry and negative -CHECKREG r7, 0x00000020; - - -imm32 p4, 0x44444444; -imm32 p5, 0x55555555; -imm32 fp, 0x66666666; -imm32 sp, 0x77777777; - -//imm32 p0, 0x00000000; -imm32 p1, 0x11111111; -imm32 p2, 0x00000000; -imm32 p3, 0x33333333; - -ASTAT = R0; -R3 = ASTAT; -CHECKREG r3, 0x00000000; - -// positive preg-1 EQUAL to positive preg-2 -CC = P4 == P5; -R0 = ASTAT; -CC = P4 < P5; -R1 = ASTAT; -CC = P4 <= P5; -R2 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; - -// positive preg-1 GREATER than positive preg-2 -CC = SP == FP; -R0 = ASTAT; -CC = SP < FP; -R1 = ASTAT; -CC = SP <= FP; -R2 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; - - -// positive preg-1 LESS than positive preg-2 -CC = FP == SP; -R0 = ASTAT; -CC = FP < SP; -R1 = ASTAT; -CC = FP <= SP; -R2 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; - -imm32 p4, 0x01230123; -imm32 p5, 0x81230123; -imm32 fp, 0x04560456; -imm32 sp, 0x87890789; -// operate on negative number -R0 = 0; -ASTAT = R0; -R3 = ASTAT; // nop; -CHECKREG r3, 0x00000000; - -// positive preg-1 GREATER than negative preg-2 -CC = P4 == P5; -R1 = ASTAT; -CC = P4 < P5; -R2 = ASTAT; -CC = P4 <= P5; -R3 = ASTAT; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; - -// negative preg-1 LESS than POSITIVE preg-2 small -CC = SP == FP; -R0 = ASTAT; -CC = SP < FP; -R1 = ASTAT; -CC = SP <= FP; -R2 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; - -// negative preg-1 GREATER than negative preg-2 -CC = P5 == SP; -R0 = ASTAT; -CC = P5 < SP; -R1 = ASTAT; -CC = P5 <= SP; -R2 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; - -// negative preg-1 LESS than negative preg-2 -CC = SP == P5; -R1 = ASTAT; -CC = SP < P5; -R2 = ASTAT; -CC = SP <= P5; -R3 = ASTAT; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; - - -imm32 p4, 0x80230123; -imm32 p5, 0x00230123; -imm32 fp, 0x80560056; -imm32 sp, 0x00890089; -// operate on negative number -P3 = 0; -ASTAT = P3; -R0 = ASTAT; - -// negative preg-1 LESS than POSITIVE preg-2 -CC = R6 == R7; -R1 = ASTAT; -CC = R6 < R7; -R2 = ASTAT; -CC = R6 <= R7; -R3 = ASTAT; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00001025; // overflow and carry but not negative -CHECKREG r2, 0x00001005; // cc overflow, carry and negative -CHECKREG r3, 0x00001025; - - -pass; diff --git a/sim/testsuite/sim/bfin/c_ccflag_pr_pr_uu.s b/sim/testsuite/sim/bfin/c_ccflag_pr_pr_uu.s deleted file mode 100644 index 0cde8c2..0000000 --- a/sim/testsuite/sim/bfin/c_ccflag_pr_pr_uu.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr_uu/c_ccflag_pr_pr_uu.dsp -// Spec Reference: ccflag pr-pr (uu) -# mach: bfin - -.include "testutils.inc" - start - -INIT_R_REGS 0; - -//imm32 p0, 0x00110022; -imm32 p1, 0x00110022; -imm32 p2, 0x00330044; -imm32 p3, 0x00550066; - -imm32 p4, 0x00770088; -imm32 p5, 0x009900aa; -imm32 fp, 0x00bb00cc; -imm32 sp, 0x00000000; - -ASTAT = R0; -R4 = ASTAT; - -// positive preg-1 EQUAL to positive preg-2 -CC = P2 < P1 (IU); -R6 = ASTAT; -CC = P2 <= P1 (IU); -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// positive preg-1 GREATER than positive preg-2 -CC = P3 < P2 (IU); -R6 = ASTAT; -CC = P3 <= P2 (IU); -R7 = ASTAT; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; -// positive preg-1 LESS than positive preg-2 -CC = P2 < P3 (IU); -R6 = ASTAT; -CC = P2 <= P3 (IU); -R7 = ASTAT; -CHECKREG r6, 0x00000020; -CHECKREG r7, 0x00000020; - -//imm32 p0, 0x01230123; -imm32 p1, 0x81230123; -imm32 p2, 0x04560456; -imm32 p3, 0x87890789; -// operate on negative number -R0 = 0; -ASTAT = R0; -R4 = ASTAT; - -// positive preg-1 GREATER than negative preg-2 -CC = P2 < P1 (IU); -R6 = ASTAT; -CC = P2 <= P1 (IU); -R7 = ASTAT; -CHECKREG r4, 0x00000000; -CHECKREG r6, 0x00000020; -CHECKREG r7, 0x00000020; - -// negative preg-1 LESS than POSITIVE preg-2 small -CC = P3 < P2 (IU); -R6 = ASTAT; -CC = P3 <= P2 (IU); -R7 = ASTAT; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// negative preg-1 GREATER than negative preg-2 -CC = P1 < P3 (IU); -R6 = ASTAT; -CC = P1 <= P3 (IU); -R7 = ASTAT; -CHECKREG r6, 0x00000020; -CHECKREG r7, 0x00000020; - -// negative preg-1 LESS than negative preg-2 -CC = P3 < P1 (IU); -R6 = ASTAT; -CC = P3 <= P1 (IU); -R7 = ASTAT; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - - -//imm32 p0, 0x80230123; -imm32 p1, 0x00230123; -imm32 p2, 0x80560056; -imm32 p3, 0x00890089; -// operate on negative number -R0 = 0; -ASTAT = R0; -R4 = ASTAT; - -// negative preg-1 LESS than POSITIVE preg-2 -CC = P2 < P3 (IU); -R6 = ASTAT; -CC = P2 <= P3 (IU); -R7 = ASTAT; -CHECKREG r4, 0x00000000; // overflow and carry but not negative -CHECKREG r6, 0x00000000; // cc overflow, carry and negative -CHECKREG r7, 0x00000000; - - -imm32 p4, 0x44444444; -imm32 p5, 0x55555555; -imm32 fp, 0x66666666; -imm32 sp, 0x77777777; - -//imm32 p0, 0x00000000; -imm32 p1, 0x11111111; -imm32 p2, 0x00000000; -imm32 p3, 0x33333333; - -ASTAT = R0; -R3 = ASTAT; -CHECKREG r3, 0x00000000; - -// positive preg-1 EQUAL to positive preg-2 -CC = P4 < P5; -R1 = ASTAT; -CC = P4 <= P5; -R2 = ASTAT; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; - -// positive preg-1 GREATER than positive preg-2 -CC = SP < FP (IU); -R1 = ASTAT; -CC = SP <= FP (IU); -R2 = ASTAT; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; - - -// positive preg-1 LESS than positive preg-2 -CC = FP < SP (IU); -R1 = ASTAT; -CC = FP <= SP (IU); -R2 = ASTAT; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; - -imm32 p4, 0x01230123; -imm32 p5, 0x81230123; -imm32 fp, 0x04560456; -imm32 sp, 0x87890789; -// operate on negative number -R0 = 0; -ASTAT = R0; -R3 = ASTAT; // nop; -CHECKREG r3, 0x00000000; - -// positive preg-1 GREATER than negative preg-2 -CC = P4 < P5 (IU); -R2 = ASTAT; -CC = P4 <= P5 (IU); -R3 = ASTAT; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000020; - -// negative preg-1 LESS than POSITIVE preg-2 small -CC = SP < FP (IU); -R1 = ASTAT; -CC = SP <= FP (IU); -R2 = ASTAT; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; - -// negative preg-1 GREATER than negative preg-2 -CC = P5 < SP (IU); -R1 = ASTAT; -CC = P5 <= SP (IU); -R2 = ASTAT; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000020; - -// negative preg-1 LESS than negative preg-2 -CC = SP < P5 (IU); -R2 = ASTAT; -CC = SP <= P5 (IU); -R3 = ASTAT; -CHECKREG r1, 0x00000020; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; - - -imm32 p4, 0x80230123; -imm32 p5, 0x00230123; -imm32 fp, 0x80560056; -imm32 sp, 0x00890089; -// operate on negative number -R0 = 0; -ASTAT = R0; -R0 = ASTAT; - -// negative preg-1 LESS than POSITIVE preg-2 -CC = R6 < R7 (IU); -R2 = ASTAT; -CC = R6 <= R7 (IU); -R3 = ASTAT; -CHECKREG r0, 0x00000000; // overflow and carry but not negative -CHECKREG r2, 0x00001005; // cc overflow, carry and negative -CHECKREG r3, 0x00001025; - - -pass; diff --git a/sim/testsuite/sim/bfin/c_ccmv_cc_dr_dr.s b/sim/testsuite/sim/bfin/c_ccmv_cc_dr_dr.s deleted file mode 100644 index b9e4fa6..0000000 --- a/sim/testsuite/sim/bfin/c_ccmv_cc_dr_dr.s +++ /dev/null @@ -1,124 +0,0 @@ -//Original:/testcases/core/c_ccmv_cc_dr_dr/c_ccmv_cc_dr_dr.dsp -// Spec Reference: ccmv cc dreg = dreg -# mach: bfin - -.include "testutils.inc" - start - -R0 = 0; -ASTAT = R0; - - -imm32 r0, 0xa08d2301; -imm32 r1, 0xd0021053; -imm32 r2, 0x2f041405; -imm32 r3, 0x60b61507; -imm32 r4, 0x50487609; -imm32 r5, 0x3005900b; -imm32 r6, 0x2a0c660d; -imm32 r7, 0xd90e108f; -IF CC R0 = R0; -IF CC R1 = R3; -IF CC R2 = R5; -IF CC R3 = R2; -CC = ! CC; -IF CC R4 = R6; -IF CC R5 = R1; -IF CC R6 = R7; -CC = ! CC; -IF CC R7 = R4; -CHECKREG r0, 0xA08D2301; -CHECKREG r1, 0xD0021053; -CHECKREG r2, 0x2F041405; -CHECKREG r3, 0x60B61507; -CHECKREG r4, 0x2A0C660D; -CHECKREG r5, 0xD0021053; -CHECKREG r6, 0xD90E108F; -CHECKREG r7, 0xD90E108F; - - -imm32 r0, 0x308d2301; -imm32 r1, 0xd4023053; -imm32 r2, 0x2f041405; -imm32 r3, 0x60f61507; -imm32 r4, 0xd0487f09; -imm32 r5, 0x300b900b; -imm32 r6, 0x2a0cd60d; -imm32 r7, 0xd90e189f; -IF CC R4 = R3; -IF CC R5 = R7; -IF CC R6 = R1; -IF CC R7 = R2; -CC = ! CC; -IF CC R0 = R6; -IF CC R1 = R5; -IF CC R2 = R4; -CC = ! CC; -IF CC R3 = R0; -CHECKREG r0, 0x2A0CD60D; -CHECKREG r1, 0x300B900B; -CHECKREG r2, 0xD0487F09; -CHECKREG r3, 0x60F61507; -CHECKREG r4, 0xD0487F09; -CHECKREG r5, 0x300B900B; -CHECKREG r6, 0x2A0CD60D; -CHECKREG r7, 0xD90E189F; - - -imm32 r0, 0x708d2301; -imm32 r1, 0xd8021053; -imm32 r2, 0x2f041405; -imm32 r3, 0x65b61507; -imm32 r4, 0x59487609; -imm32 r5, 0x3005900b; -imm32 r6, 0x2abc660d; -imm32 r7, 0xd90e108f; -IF CC R0 = R2; -IF CC R1 = R3; -CC = ! CC; -IF CC R2 = R5; -IF CC R3 = R7; -CC = ! CC; -IF CC R4 = R1; -IF CC R5 = R4; -IF CC R6 = R7; -IF CC R7 = R6; -CHECKREG r0, 0x708D2301; -CHECKREG r1, 0xD8021053; -CHECKREG r2, 0x3005900B; -CHECKREG r3, 0xD90E108F; -CHECKREG r4, 0x59487609; -CHECKREG r5, 0x3005900B; -CHECKREG r6, 0x2ABC660D; -CHECKREG r7, 0xD90E108F; - - -imm32 r0, 0xc08d2301; -imm32 r1, 0xdb021053; -imm32 r2, 0x2f041405; -imm32 r3, 0x64b61507; -imm32 r4, 0x50487609; -imm32 r5, 0x30f5900b; -imm32 r6, 0x2a4c660d; -imm32 r7, 0x895e108f; -IF CC R4 = R3; -IF CC R5 = R7; -CC = ! CC; -IF CC R6 = R2; -IF CC R7 = R6; -CC = ! CC; -IF CC R0 = R1; -IF CC R1 = R2; -IF CC R2 = R0; -IF CC R3 = R4; -CHECKREG r0, 0xC08D2301; -CHECKREG r1, 0xDB021053; -CHECKREG r2, 0x2F041405; -CHECKREG r3, 0x64B61507; -CHECKREG r4, 0x50487609; -CHECKREG r5, 0x30F5900B; -CHECKREG r6, 0x2F041405; -CHECKREG r7, 0x2F041405; - - -pass diff --git a/sim/testsuite/sim/bfin/c_ccmv_cc_dr_pr.s b/sim/testsuite/sim/bfin/c_ccmv_cc_dr_pr.s deleted file mode 100644 index 186a199..0000000 --- a/sim/testsuite/sim/bfin/c_ccmv_cc_dr_pr.s +++ /dev/null @@ -1,61 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ccmv_cc_dr_pr/c_ccmv_cc_dr_pr.dsp -// Spec Reference: ccmv cc dpreg = dpreg -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - imm32 r0, 0x138d2301; - imm32 r1, 0x20421053; - imm32 r2, 0x3f051405; - imm32 r3, 0x40b66507; - imm32 r4, 0x50487709; - imm32 r5, 0x6005908b; - imm32 r6, 0x7a0c6609; - imm32 r7, 0x890e108f; - imm32 p1, 0x9d021053; - imm32 p2, 0xafb41405; - imm32 p3, 0xb0bf1507; - imm32 p4, 0xd0483609; - imm32 p5, 0xe005d00b; - imm32 sp, 0xfa0c667d; - imm32 fp, 0xc90e108f; - IF CC R0 = P0; - IF CC P1 = R3; - IF CC R2 = P5; - IF CC P2 = R2; - CC = ! CC; - IF CC P3 = R6; - IF CC R5 = P1; - IF CC P4 = R7; - CC = ! CC; - IF CC R7 = P4; - IF CC P5 = R3; - IF CC R6 = SP; - IF CC R3 = P2; - CC = ! CC; - IF CC SP = R6; - IF CC R1 = P5; - IF CC FP = R4; - CC = ! CC; - IF CC R3 = P3; - CHECKREG r0, 0x138D2301; - CHECKREG r1, 0xE005D00B; - CHECKREG r2, 0x3F051405; - CHECKREG r3, 0x40B66507; - CHECKREG r4, 0x50487709; - CHECKREG r5, 0x9D021053; - CHECKREG r6, 0x7A0C6609; - CHECKREG r7, 0x890E108F; - CHECKREG p1, 0x9D021053; - CHECKREG p2, 0xAFB41405; - CHECKREG p3, 0x7A0C6609; - CHECKREG p4, 0x890E108F; - CHECKREG p5, 0xE005D00B; - CHECKREG sp, 0x7A0C6609; - CHECKREG fp, 0x50487709; - - pass diff --git a/sim/testsuite/sim/bfin/c_ccmv_cc_pr_pr.s b/sim/testsuite/sim/bfin/c_ccmv_cc_pr_pr.s deleted file mode 100644 index df93ccb..0000000 --- a/sim/testsuite/sim/bfin/c_ccmv_cc_pr_pr.s +++ /dev/null @@ -1,111 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ccmv_cc_pr_pr/c_ccmv_cc_pr_pr.dsp -// Spec Reference: ccmv cc preg = preg -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - imm32 p1, 0xd0021053; - imm32 p2, 0x2f041405; - imm32 p3, 0x60b61507; - imm32 p4, 0x50487609; - imm32 p5, 0x3005900b; - imm32 sp, 0x2a0c660d; - imm32 fp, 0xd90e108f; - IF CC P3 = P3; - IF CC P1 = P3; - IF CC P2 = P5; - IF CC P3 = P2; - CC = ! CC; - IF CC P4 = SP; - IF CC P5 = P1; - IF CC SP = FP; - CC = ! CC; - IF CC FP = P4; - CHECKREG p1, 0xD0021053; - CHECKREG p2, 0x2F041405; - CHECKREG p3, 0x60B61507; - CHECKREG p4, 0x2A0C660D; - CHECKREG p5, 0xD0021053; - CHECKREG sp, 0xD90E108F; - CHECKREG fp, 0xD90E108F; - - imm32 p1, 0xd4023053; - imm32 p2, 0x2f041405; - imm32 p3, 0x60f61507; - imm32 p4, 0xd0487f09; - imm32 p5, 0x300b900b; - imm32 sp, 0x2a0cd60d; - imm32 fp, 0xd90e189f; - IF CC P4 = P3; - IF CC P5 = FP; - IF CC SP = P1; - IF CC FP = P2; - CC = ! CC; - IF CC P3 = SP; - IF CC P1 = P5; - IF CC P2 = P4; - CC = ! CC; - IF CC P3 = P2; - CHECKREG p1, 0x300B900B; - CHECKREG p2, 0xD0487F09; - CHECKREG p3, 0x2A0CD60D; - CHECKREG p4, 0xD0487F09; - CHECKREG p5, 0x300B900B; - CHECKREG sp, 0x2A0CD60D; - CHECKREG fp, 0xD90E189F; - - imm32 p1, 0xd8021053; - imm32 p2, 0x2f041405; - imm32 p3, 0x65b61507; - imm32 p4, 0x59487609; - imm32 p5, 0x3005900b; - imm32 sp, 0x2abc660d; - imm32 fp, 0xd90e108f; - IF CC P3 = P2; - IF CC P1 = P3; - CC = ! CC; - IF CC P2 = P5; - IF CC P3 = FP; - CC = ! CC; - IF CC P4 = P1; - IF CC P5 = P4; - IF CC SP = FP; - IF CC FP = SP; - CHECKREG p1, 0xD8021053; - CHECKREG p2, 0x3005900B; - CHECKREG p3, 0xD90E108F; - CHECKREG p4, 0x59487609; - CHECKREG p5, 0x3005900B; - CHECKREG sp, 0x2ABC660D; - CHECKREG fp, 0xD90E108F; - - imm32 p1, 0xdb021053; - imm32 p2, 0x2f041405; - imm32 p3, 0x64b61507; - imm32 p4, 0x50487609; - imm32 p5, 0x30f5900b; - imm32 sp, 0x2a4c660d; - imm32 fp, 0x895e108f; - IF CC P4 = P3; - IF CC P5 = FP; - CC = ! CC; - IF CC SP = P2; - IF CC FP = SP; - CC = ! CC; - IF CC P3 = P1; - IF CC P1 = P2; - IF CC P2 = P3; - IF CC P3 = P4; - CHECKREG p1, 0xDB021053; - CHECKREG p2, 0x2F041405; - CHECKREG p3, 0x64B61507; - CHECKREG p4, 0x50487609; - CHECKREG p5, 0x30F5900B; - CHECKREG sp, 0x2F041405; - CHECKREG fp, 0x2F041405; - - pass diff --git a/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_dr.s b/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_dr.s deleted file mode 100644 index 94a6e32..0000000 --- a/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_dr.s +++ /dev/null @@ -1,123 +0,0 @@ -//Original:/testcases/core/c_ccmv_ncc_dr_dr/c_ccmv_ncc_dr_dr.dsp -// Spec Reference: ccmv !cc dreg = dreg -# mach: bfin - -.include "testutils.inc" - start -R0 = 0; -ASTAT = R0; - - -imm32 r0, 0x808d2301; -imm32 r1, 0x90021053; -imm32 r2, 0x21041405; -imm32 r3, 0x60261507; -imm32 r4, 0x50447609; -imm32 r5, 0xdfe5500b; -imm32 r6, 0x2a0c660d; -imm32 r7, 0xd90e1b8f; -IF !CC R0 = R0; -IF !CC R1 = R3; -IF !CC R2 = R5; -IF !CC R3 = R2; -CC = ! CC; -IF !CC R4 = R6; -IF !CC R5 = R1; -IF !CC R6 = R7; -CC = ! CC; -IF !CC R7 = R4; -CHECKREG r0, 0x808D2301; -CHECKREG r1, 0x60261507; -CHECKREG r2, 0xDFE5500B; -CHECKREG r3, 0xDFE5500B; -CHECKREG r4, 0x50447609; -CHECKREG r5, 0xDFE5500B; -CHECKREG r6, 0x2A0C660D; -CHECKREG r7, 0x50447609; - - -imm32 r0, 0x308d2301; -imm32 r1, 0xd4023053; -imm32 r2, 0x2f041405; -imm32 r3, 0x60f61507; -imm32 r4, 0xd0487f09; -imm32 r5, 0x300b900b; -imm32 r6, 0x2a0cd60d; -imm32 r7, 0xd90e189f; -IF !CC R4 = R3; -IF !CC R5 = R7; -IF !CC R6 = R1; -IF !CC R7 = R2; -CC = ! CC; -IF !CC R0 = R6; -IF !CC R1 = R5; -IF !CC R2 = R4; -CC = ! CC; -IF !CC R3 = R0; -CHECKREG r0, 0x308D2301; -CHECKREG r1, 0xD4023053; -CHECKREG r2, 0x2F041405; -CHECKREG r3, 0x308D2301; -CHECKREG r4, 0x60F61507; -CHECKREG r5, 0xD90E189F; -CHECKREG r6, 0xD4023053; -CHECKREG r7, 0x2F041405; - - -imm32 r0, 0x708d2301; -imm32 r1, 0xd8021053; -imm32 r2, 0x2f041405; -imm32 r3, 0x65b61507; -imm32 r4, 0x59487609; -imm32 r5, 0x3005900b; -imm32 r6, 0x2abc660d; -imm32 r7, 0xd90e108f; -IF !CC R0 = R2; -IF !CC R1 = R3; -CC = ! CC; -IF !CC R2 = R5; -IF !CC R3 = R7; -CC = ! CC; -IF !CC R4 = R1; -IF !CC R5 = R4; -IF !CC R6 = R7; -IF !CC R7 = R6; -CHECKREG r0, 0x2F041405; -CHECKREG r1, 0x65B61507; -CHECKREG r2, 0x2F041405; -CHECKREG r3, 0x65B61507; -CHECKREG r4, 0x65B61507; -CHECKREG r5, 0x65B61507; -CHECKREG r6, 0xD90E108F; -CHECKREG r7, 0xD90E108F; - - -imm32 r0, 0xc08d2301; -imm32 r1, 0xdb021053; -imm32 r2, 0x2f041405; -imm32 r3, 0x64b61507; -imm32 r4, 0x50487609; -imm32 r5, 0x30f5900b; -imm32 r6, 0x2a4c660d; -imm32 r7, 0x895e108f; -IF !CC R4 = R3; -IF !CC R5 = R7; -CC = ! CC; -IF !CC R6 = R2; -IF !CC R7 = R6; -CC = ! CC; -IF !CC R0 = R1; -IF !CC R1 = R2; -IF !CC R2 = R0; -IF !CC R3 = R4; -CHECKREG r0, 0xDB021053; -CHECKREG r1, 0x2F041405; -CHECKREG r2, 0xDB021053; -CHECKREG r3, 0x64B61507; -CHECKREG r4, 0x64B61507; -CHECKREG r5, 0x895E108F; -CHECKREG r6, 0x2A4C660D; -CHECKREG r7, 0x895E108F; - - -pass diff --git a/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_pr.s b/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_pr.s deleted file mode 100644 index 1b981ac..0000000 --- a/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_pr.s +++ /dev/null @@ -1,60 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_dr_pr/c_ccmv_ncc_dr_pr.dsp -// Spec Reference: ccmv !cc dpreg = dpreg -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - imm32 r0, 0x138d2301; - imm32 r1, 0x20421053; - imm32 r2, 0x3f051405; - imm32 r3, 0x40b66507; - imm32 r4, 0x50487709; - imm32 r5, 0x6005908b; - imm32 r6, 0x7a0c6609; - imm32 r7, 0x890e108f; - imm32 p1, 0x9d021053; - imm32 p2, 0xafb41405; - imm32 p3, 0xb0bf1507; - imm32 p4, 0xd0483609; - imm32 p5, 0xe005d00b; - imm32 sp, 0xfa0c667d; - imm32 fp, 0xc90e108f; - IF !CC R0 = P0; - CC = ! CC; - IF !CC P1 = R3; - IF !CC R2 = P5; - IF !CC P2 = R2; - IF !CC P3 = R6; - IF !CC R5 = P1; - CC = ! CC; - IF !CC P4 = R7; - IF !CC R7 = P4; - IF !CC P5 = R3; - IF !CC R6 = SP; - CC = ! CC; - IF !CC R3 = P2; - IF !CC SP = R6; - IF !CC R1 = P5; - CC = ! CC; - IF !CC FP = R4; - IF !CC R3 = P3; - CHECKREG r1, 0x20421053; - CHECKREG r2, 0x3F051405; - CHECKREG r3, 0xB0BF1507; - CHECKREG r4, 0x50487709; - CHECKREG r5, 0x6005908B; - CHECKREG r6, 0xFA0C667D; - CHECKREG r7, 0x890E108F; - CHECKREG p1, 0x9D021053; - CHECKREG p2, 0xAFB41405; - CHECKREG p3, 0xB0BF1507; - CHECKREG p4, 0x890E108F; - CHECKREG p5, 0x40B66507; - CHECKREG sp, 0xFA0C667D; - CHECKREG fp, 0x50487709; - - pass diff --git a/sim/testsuite/sim/bfin/c_ccmv_ncc_pr_pr.s b/sim/testsuite/sim/bfin/c_ccmv_ncc_pr_pr.s deleted file mode 100644 index 58c38ed..0000000 --- a/sim/testsuite/sim/bfin/c_ccmv_ncc_pr_pr.s +++ /dev/null @@ -1,111 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_pr_pr/c_ccmv_ncc_pr_pr.dsp -// Spec Reference: ccmv !cc preg = preg -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - imm32 p1, 0xd0021053; - imm32 p2, 0x2f041405; - imm32 p3, 0x60b61507; - imm32 p4, 0x50487609; - imm32 p5, 0x3005900b; - imm32 sp, 0x2a0c660d; - imm32 fp, 0xd90e108f; - IF !CC P3 = P3; - IF !CC P1 = P3; - CC = ! CC; - IF !CC P2 = P5; - IF !CC P3 = P2; - IF !CC P4 = SP; - IF !CC P5 = P1; - IF !CC SP = FP; - CC = ! CC; - IF !CC FP = P4; - CHECKREG p1, 0x60B61507; - CHECKREG p2, 0x2F041405; - CHECKREG p3, 0x60B61507; - CHECKREG p4, 0x50487609; - CHECKREG p5, 0x3005900B; - CHECKREG sp, 0x2A0C660D; - CHECKREG fp, 0x50487609; - - imm32 p1, 0xd4023053; - imm32 p2, 0x2f041405; - imm32 p3, 0x60f61507; - imm32 p4, 0xd0487f09; - imm32 p5, 0x300b900b; - imm32 sp, 0x2a0cd60d; - imm32 fp, 0xd90e189f; - IF !CC P4 = P3; - IF !CC P5 = FP; - CC = ! CC; - IF !CC SP = P1; - IF !CC FP = P2; - IF !CC P3 = SP; - IF !CC P1 = P5; - IF !CC P2 = P4; - CC = ! CC; - IF !CC P3 = P2; - CHECKREG p1, 0xD4023053; - CHECKREG p2, 0x2F041405; - CHECKREG p3, 0x2F041405; - CHECKREG p4, 0x60F61507; - CHECKREG p5, 0xD90E189F; - CHECKREG sp, 0x2A0CD60D; - CHECKREG fp, 0xD90E189F; - - imm32 p1, 0xd8021053; - imm32 p2, 0x2f041405; - imm32 p3, 0x65b61507; - imm32 p4, 0x59487609; - imm32 p5, 0x3005900b; - imm32 sp, 0x2abc660d; - imm32 fp, 0xd90e108f; - IF !CC P3 = P2; - IF !CC P1 = P3; - CC = ! CC; - IF !CC P2 = P5; - IF !CC P3 = FP; - IF !CC P4 = P1; - IF !CC P5 = P4; - IF !CC SP = FP; - CC = ! CC; - IF !CC FP = SP; - CHECKREG p1, 0x2F041405; - CHECKREG p2, 0x2F041405; - CHECKREG p3, 0x2F041405; - CHECKREG p4, 0x59487609; - CHECKREG p5, 0x3005900B; - CHECKREG sp, 0x2ABC660D; - CHECKREG fp, 0x2ABC660D; - - imm32 p1, 0xdb021053; - imm32 p2, 0x2f041405; - imm32 p3, 0x64b61507; - imm32 p4, 0x50487609; - imm32 p5, 0x30f5900b; - imm32 sp, 0x2a4c660d; - imm32 fp, 0x895e108f; - IF !CC P4 = P3; - IF !CC P5 = FP; - IF !CC SP = P2; - IF !CC FP = SP; - CC = ! CC; - IF !CC P3 = P1; - IF !CC P1 = P2; - CC = ! CC; - IF !CC P2 = P3; - IF !CC P3 = P4; - CHECKREG p1, 0xDB021053; - CHECKREG p2, 0x64B61507; - CHECKREG p3, 0x64B61507; - CHECKREG p4, 0x64B61507; - CHECKREG p5, 0x895E108F; - CHECKREG sp, 0x2F041405; - CHECKREG fp, 0x2F041405; - - pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_dr_and_dr.s b/sim/testsuite/sim/bfin/c_comp3op_dr_and_dr.s deleted file mode 100644 index 567187b..0000000 --- a/sim/testsuite/sim/bfin/c_comp3op_dr_and_dr.s +++ /dev/null @@ -1,412 +0,0 @@ -//Original:/testcases/core/c_comp3op_dr_and_dr/c_comp3op_dr_and_dr.dsp -// Spec Reference: comp3op dregs & dregs -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x01234567; -imm32 r1, 0x89abcdef; -imm32 r2, 0x56789abc; -imm32 r3, 0xdef01234; -imm32 r4, 0x23456899; -imm32 r5, 0x78912345; -imm32 r6, 0x98765432; -imm32 r7, 0x12345678; -R0 = R0 & R0; -R1 = R0 & R1; -R2 = R0 & R2; -R3 = R0 & R3; -R4 = R0 & R4; -R5 = R0 & R5; -R6 = R0 & R6; -R7 = R0 & R7; -CHECKREG r0, 0x01234567; -CHECKREG r1, 0x01234567; -CHECKREG r2, 0x00200024; -CHECKREG r3, 0x00200024; -CHECKREG r4, 0x01014001; -CHECKREG r5, 0x00010145; -CHECKREG r6, 0x00224422; -CHECKREG r7, 0x00204460; - -imm32 r0, 0x01231567; -imm32 r1, 0x89ab1def; -imm32 r2, 0x56781abc; -imm32 r3, 0xdef01234; -imm32 r4, 0x23451899; -imm32 r5, 0x78911345; -imm32 r6, 0x98761432; -imm32 r7, 0x12341678; -R0 = R1 & R0; -R1 = R1 & R1; -R2 = R1 & R2; -R3 = R1 & R3; -R4 = R1 & R4; -R5 = R1 & R5; -R6 = R1 & R6; -R7 = R1 & R7; -CHECKREG r0, 0x01231567; -CHECKREG r1, 0x89AB1DEF; -CHECKREG r2, 0x002818AC; -CHECKREG r3, 0x88A01024; -CHECKREG r4, 0x01011889; -CHECKREG r5, 0x08811145; -CHECKREG r6, 0x88221422; -CHECKREG r7, 0x00201468; - -imm32 r0, 0x01234527; -imm32 r1, 0x89abcd2f; -imm32 r2, 0x56789a2c; -imm32 r3, 0xdef01224; -imm32 r4, 0x23456829; -imm32 r5, 0x78912325; -imm32 r6, 0x98765422; -imm32 r7, 0x12345628; -R0 = R2 & R0; -R1 = R2 & R1; -R2 = R2 & R2; -R3 = R2 & R3; -R4 = R2 & R4; -R5 = R2 & R5; -R6 = R2 & R6; -R7 = R2 & R7; -CHECKREG r0, 0x00200024; -CHECKREG r1, 0x0028882C; -CHECKREG r2, 0x56789A2C; -CHECKREG r3, 0x56701224; -CHECKREG r4, 0x02400828; -CHECKREG r5, 0x50100224; -CHECKREG r6, 0x10701020; -CHECKREG r7, 0x12301228; - -imm32 r0, 0x01234563; -imm32 r1, 0x89abcde3; -imm32 r2, 0x56789ab3; -imm32 r3, 0xdef01233; -imm32 r4, 0x23456893; -imm32 r5, 0x78912343; -imm32 r6, 0x98765433; -imm32 r7, 0x12345673; -R0 = R3 & R0; -R1 = R3 & R1; -R2 = R3 & R2; -R3 = R3 & R3; -R4 = R3 & R4; -R5 = R3 & R5; -R6 = R3 & R6; -R7 = R3 & R7; -CHECKREG r0, 0x00200023; -CHECKREG r1, 0x88A00023; -CHECKREG r2, 0x56701233; -CHECKREG r3, 0xDEF01233; -CHECKREG r4, 0x02400013; -CHECKREG r5, 0x58900203; -CHECKREG r6, 0x98701033; -CHECKREG r7, 0x12301233; - -imm32 r0, 0x41234567; -imm32 r1, 0x49abcdef; -imm32 r2, 0x46789abc; -imm32 r3, 0x4ef01234; -imm32 r4, 0x43456899; -imm32 r5, 0x48912345; -imm32 r6, 0x48765432; -imm32 r7, 0x42345678; -R0 = R4 & R0; -R1 = R4 & R1; -R2 = R4 & R2; -R3 = R4 & R3; -R4 = R4 & R4; -R5 = R4 & R5; -R6 = R4 & R6; -R7 = R4 & R7; -CHECKREG r0, 0x41014001; -CHECKREG r1, 0x41014889; -CHECKREG r2, 0x42400898; -CHECKREG r3, 0x42400010; -CHECKREG r4, 0x43456899; -CHECKREG r5, 0x40012001; -CHECKREG r6, 0x40444010; -CHECKREG r7, 0x42044018; - -imm32 r0, 0x05234567; -imm32 r1, 0x85abcdef; -imm32 r2, 0x55789abc; -imm32 r3, 0xd5f01234; -imm32 r4, 0x25456899; -imm32 r5, 0x75912345; -imm32 r6, 0x95765432; -imm32 r7, 0x15345678; -R0 = R5 & R0; -R1 = R5 & R1; -R2 = R5 & R2; -R3 = R5 & R3; -R4 = R5 & R4; -R5 = R5 & R5; -R6 = R5 & R6; -R7 = R5 & R7; -CHECKREG r0, 0x05010145; -CHECKREG r1, 0x05810145; -CHECKREG r2, 0x55100204; -CHECKREG r3, 0x55900204; -CHECKREG r4, 0x25012001; -CHECKREG r5, 0x75912345; -CHECKREG r6, 0x15100000; -CHECKREG r7, 0x15100240; - -imm32 r0, 0x01264567; -imm32 r1, 0x89a6cdef; -imm32 r2, 0x56769abc; -imm32 r3, 0xdef61234; -imm32 r4, 0x23466899; -imm32 r5, 0x78962345; -imm32 r6, 0x98765432; -imm32 r7, 0x12365678; -R0 = R6 & R0; -R1 = R6 & R1; -R2 = R6 & R2; -R3 = R6 & R3; -R4 = R6 & R4; -R5 = R6 & R5; -R6 = R6 & R6; -R7 = R6 & R7; -CHECKREG r0, 0x00264422; -CHECKREG r1, 0x88264422; -CHECKREG r2, 0x10761030; -CHECKREG r3, 0x98761030; -CHECKREG r4, 0x00464010; -CHECKREG r5, 0x18160000; -CHECKREG r6, 0x98765432; -CHECKREG r7, 0x10365430; - -imm32 r0, 0x01237567; -imm32 r1, 0x89ab7def; -imm32 r2, 0x56787abc; -imm32 r3, 0xdef07234; -imm32 r4, 0x23457899; -imm32 r5, 0x78917345; -imm32 r6, 0x98767432; -imm32 r7, 0x12345678; -R0 = R7 & R0; -R1 = R7 & R1; -R2 = R7 & R2; -R3 = R7 & R3; -R4 = R7 & R4; -R5 = R7 & R5; -R6 = R7 & R6; -R7 = R7 & R7; -CHECKREG r0, 0x00205460; -CHECKREG r1, 0x00205468; -CHECKREG r2, 0x12305238; -CHECKREG r3, 0x12305230; -CHECKREG r4, 0x02045018; -CHECKREG r5, 0x10105240; -CHECKREG r6, 0x10345430; -CHECKREG r7, 0x12345678; - -imm32 r0, 0x11234567; -imm32 r1, 0x81abcdef; -imm32 r2, 0x56189abc; -imm32 r3, 0xdef11234; -imm32 r4, 0x23451899; -imm32 r5, 0x78912145; -imm32 r6, 0x98765412; -imm32 r7, 0x12345671; -R0 = R1 & R0; -R1 = R2 & R0; -R2 = R3 & R0; -R3 = R4 & R0; -R4 = R5 & R0; -R5 = R6 & R0; -R6 = R7 & R0; -R7 = R0 & R0; -CHECKREG r0, 0x01234567; -CHECKREG r1, 0x00000024; -CHECKREG r2, 0x00210024; -CHECKREG r3, 0x01010001; -CHECKREG r4, 0x00010145; -CHECKREG r5, 0x00224402; -CHECKREG r6, 0x00204461; -CHECKREG r7, 0x01234567; - -imm32 r0, 0x01231567; -imm32 r1, 0x29ab1def; -imm32 r2, 0x52781abc; -imm32 r3, 0xde201234; -imm32 r4, 0x23421899; -imm32 r5, 0x78912345; -imm32 r6, 0x98761232; -imm32 r7, 0x12341628; -R0 = R2 & R1; -R1 = R3 & R1; -R2 = R4 & R1; -R3 = R5 & R1; -R4 = R6 & R1; -R5 = R7 & R1; -R6 = R0 & R1; -R7 = R1 & R1; -CHECKREG r0, 0x002818AC; -CHECKREG r1, 0x08201024; -CHECKREG r2, 0x00001000; -CHECKREG r3, 0x08000004; -CHECKREG r4, 0x08201020; -CHECKREG r5, 0x00201020; -CHECKREG r6, 0x00201024; -CHECKREG r7, 0x08201024; - -imm32 r0, 0x03234527; -imm32 r1, 0x893bcd2f; -imm32 r2, 0x56739a2c; -imm32 r3, 0x3ef03224; -imm32 r4, 0x23456329; -imm32 r5, 0x78312335; -imm32 r6, 0x98735423; -imm32 r7, 0x12343628; -R0 = R4 & R2; -R1 = R5 & R2; -R2 = R6 & R2; -R3 = R7 & R2; -R4 = R0 & R2; -R5 = R1 & R2; -R6 = R2 & R2; -R7 = R3 & R2; -CHECKREG r0, 0x02410228; -CHECKREG r1, 0x50310224; -CHECKREG r2, 0x10731020; -CHECKREG r3, 0x10301020; -CHECKREG r4, 0x00410020; -CHECKREG r5, 0x10310020; -CHECKREG r6, 0x10731020; -CHECKREG r7, 0x10301020; - -imm32 r0, 0x04234563; -imm32 r1, 0x894bcde3; -imm32 r2, 0x56749ab3; -imm32 r3, 0x4ef04233; -imm32 r4, 0x24456493; -imm32 r5, 0x78412344; -imm32 r6, 0x98745434; -imm32 r7, 0x12344673; -R0 = R5 & R3; -R1 = R6 & R3; -R2 = R7 & R3; -R3 = R0 & R3; -R4 = R1 & R3; -R5 = R2 & R3; -R6 = R3 & R3; -R7 = R4 & R3; -CHECKREG r0, 0x48400200; -CHECKREG r1, 0x08704030; -CHECKREG r2, 0x02304233; -CHECKREG r3, 0x48400200; -CHECKREG r4, 0x08400000; -CHECKREG r5, 0x00000200; -CHECKREG r6, 0x48400200; -CHECKREG r7, 0x08400000; - -imm32 r0, 0x41235567; -imm32 r1, 0x49abc5ef; -imm32 r2, 0x46789a5c; -imm32 r3, 0x4ef01235; -imm32 r4, 0x53456899; -imm32 r5, 0x45912345; -imm32 r6, 0x48565432; -imm32 r7, 0x42355678; -R0 = R6 & R4; -R1 = R7 & R4; -R2 = R0 & R4; -R3 = R1 & R4; -R4 = R2 & R4; -R5 = R3 & R4; -R6 = R4 & R4; -R7 = R5 & R4; -CHECKREG r0, 0x40444010; -CHECKREG r1, 0x42054018; -CHECKREG r2, 0x40444010; -CHECKREG r3, 0x42054018; -CHECKREG r4, 0x40444010; -CHECKREG r5, 0x40044010; -CHECKREG r6, 0x40444010; -CHECKREG r7, 0x40044010; - -imm32 r0, 0x05264567; -imm32 r1, 0x85ab6def; -imm32 r2, 0x657896bc; -imm32 r3, 0xd6f01264; -imm32 r4, 0x25656896; -imm32 r5, 0x75962345; -imm32 r6, 0x95766432; -imm32 r7, 0x15345678; -R0 = R7 & R5; -R1 = R0 & R5; -R2 = R1 & R5; -R3 = R2 & R5; -R4 = R3 & R5; -R5 = R4 & R5; -R6 = R5 & R5; -R7 = R6 & R5; -CHECKREG r0, 0x15140240; -CHECKREG r1, 0x15140240; -CHECKREG r2, 0x15140240; -CHECKREG r3, 0x15140240; -CHECKREG r4, 0x15140240; -CHECKREG r5, 0x15140240; -CHECKREG r6, 0x15140240; -CHECKREG r7, 0x15140240; - -imm32 r0, 0x01764567; -imm32 r1, 0x89a7cdef; -imm32 r2, 0x56767abc; -imm32 r3, 0xdef61734; -imm32 r4, 0x73466879; -imm32 r5, 0x77962347; -imm32 r6, 0x98765432; -imm32 r7, 0x12375678; -R0 = R7 & R6; -R1 = R0 & R6; -R2 = R1 & R6; -R3 = R2 & R6; -R4 = R3 & R6; -R5 = R4 & R6; -R6 = R5 & R6; -R7 = R6 & R6; -CHECKREG r0, 0x10365430; -CHECKREG r1, 0x10365430; -CHECKREG r2, 0x10365430; -CHECKREG r3, 0x10365430; -CHECKREG r4, 0x10365430; -CHECKREG r5, 0x10365430; -CHECKREG r6, 0x10365430; -CHECKREG r7, 0x10365430; - -imm32 r0, 0x81238567; -imm32 r1, 0x88ab78ef; -imm32 r2, 0x56887a8c; -imm32 r3, 0x8ef87238; -imm32 r4, 0x28458899; -imm32 r5, 0x78817845; -imm32 r6, 0x98787482; -imm32 r7, 0x12348678; -R0 = R1 & R7; -R1 = R2 & R7; -R2 = R3 & R7; -R3 = R4 & R7; -R4 = R5 & R7; -R5 = R6 & R7; -R6 = R7 & R7; -R7 = R0 & R7; -CHECKREG r0, 0x00200068; -CHECKREG r1, 0x12000208; -CHECKREG r2, 0x02300238; -CHECKREG r3, 0x00048018; -CHECKREG r4, 0x10000040; -CHECKREG r5, 0x10300400; -CHECKREG r6, 0x12348678; -CHECKREG r7, 0x00200068; - - -pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_dr_minus_dr.s b/sim/testsuite/sim/bfin/c_comp3op_dr_minus_dr.s deleted file mode 100644 index ebf2b0b..0000000 --- a/sim/testsuite/sim/bfin/c_comp3op_dr_minus_dr.s +++ /dev/null @@ -1,412 +0,0 @@ -//Original:/testcases/core/c_comp3op_dr_minus_dr/c_comp3op_dr_minus_dr.dsp -// Spec Reference: comp3op dregs - dregs -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x01234567; -imm32 r1, 0x89abcdef; -imm32 r2, 0x56789abc; -imm32 r3, 0xdef01234; -imm32 r4, 0x23456899; -imm32 r5, 0x78912345; -imm32 r6, 0x98765432; -imm32 r7, 0x12345678; -R0 = R0 - R0; -R1 = R0 - R1; -R2 = R0 - R2; -R3 = R0 - R3; -R4 = R0 - R4; -R5 = R0 - R5; -R6 = R0 - R6; -R7 = R0 - R7; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x76543211; -CHECKREG r2, 0xA9876544; -CHECKREG r3, 0x210FEDCC; -CHECKREG r4, 0xDCBA9767; -CHECKREG r5, 0x876EDCBB; -CHECKREG r6, 0x6789ABCE; -CHECKREG r7, 0xEDCBA988; - -imm32 r0, 0x01231567; -imm32 r1, 0x89ab1def; -imm32 r2, 0x56781abc; -imm32 r3, 0xdef01234; -imm32 r4, 0x23451899; -imm32 r5, 0x78911345; -imm32 r6, 0x98761432; -imm32 r7, 0x12341678; -R0 = R1 - R0; -R1 = R1 - R1; -R2 = R1 - R2; -R3 = R1 - R3; -R4 = R1 - R4; -R5 = R1 - R5; -R6 = R1 - R6; -R7 = R1 - R7; -CHECKREG r0, 0x88880888; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0xA987E544; -CHECKREG r3, 0x210FEDCC; -CHECKREG r4, 0xDCBAE767; -CHECKREG r5, 0x876EECBB; -CHECKREG r6, 0x6789EBCE; -CHECKREG r7, 0xEDCBE988; - -imm32 r0, 0x01234527; -imm32 r1, 0x89abcd2f; -imm32 r2, 0x56789a2c; -imm32 r3, 0xdef01224; -imm32 r4, 0x23456829; -imm32 r5, 0x78912325; -imm32 r6, 0x98765422; -imm32 r7, 0x12345628; -R0 = R2 - R0; -R1 = R2 - R1; -R2 = R2 - R2; -R3 = R2 - R3; -R4 = R2 - R4; -R5 = R2 - R5; -R6 = R2 - R6; -R7 = R2 - R7; -CHECKREG r0, 0x55555505; -CHECKREG r1, 0xCCCCCCFD; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x210FEDDC; -CHECKREG r4, 0xDCBA97D7; -CHECKREG r5, 0x876EDCDB; -CHECKREG r6, 0x6789ABDE; -CHECKREG r7, 0xEDCBA9D8; - -imm32 r0, 0x01234563; -imm32 r1, 0x89abcde3; -imm32 r2, 0x56789ab3; -imm32 r3, 0xdef01233; -imm32 r4, 0x23456893; -imm32 r5, 0x78912343; -imm32 r6, 0x98765433; -imm32 r7, 0x12345673; -R0 = R3 - R0; -R1 = R3 - R1; -R2 = R3 - R2; -R3 = R3 - R3; -R4 = R3 - R4; -R5 = R3 - R5; -R6 = R3 - R6; -R7 = R3 - R7; -CHECKREG r0, 0xDDCCCCD0; -CHECKREG r1, 0x55444450; -CHECKREG r2, 0x88777780; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0xDCBA976D; -CHECKREG r5, 0x876EDCBD; -CHECKREG r6, 0x6789ABCD; -CHECKREG r7, 0xEDCBA98D; - -imm32 r0, 0x41234567; -imm32 r1, 0x49abcdef; -imm32 r2, 0x46789abc; -imm32 r3, 0x4ef01234; -imm32 r4, 0x43456899; -imm32 r5, 0x48912345; -imm32 r6, 0x48765432; -imm32 r7, 0x42345678; -R0 = R4 - R0; -R1 = R4 - R1; -R2 = R4 - R2; -R3 = R4 - R3; -R4 = R4 - R4; -R5 = R4 - R5; -R6 = R4 - R6; -R7 = R4 - R7; -CHECKREG r0, 0x02222332; -CHECKREG r1, 0xF9999AAA; -CHECKREG r2, 0xFCCCCDDD; -CHECKREG r3, 0xF4555665; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0xB76EDCBB; -CHECKREG r6, 0xB789ABCE; -CHECKREG r7, 0xBDCBA988; - -imm32 r0, 0x05234567; -imm32 r1, 0x85abcdef; -imm32 r2, 0x55789abc; -imm32 r3, 0xd5f01234; -imm32 r4, 0x25456899; -imm32 r5, 0x75912345; -imm32 r6, 0x95765432; -imm32 r7, 0x15345678; -R0 = R5 - R0; -R1 = R5 - R1; -R2 = R5 - R2; -R3 = R5 - R3; -R4 = R5 - R4; -R5 = R5 - R5; -R6 = R5 - R6; -R7 = R5 - R7; -CHECKREG r0, 0x706DDDDE; -CHECKREG r1, 0xEFE55556; -CHECKREG r2, 0x20188889; -CHECKREG r3, 0x9FA11111; -CHECKREG r4, 0x504BBAAC; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x6A89ABCE; -CHECKREG r7, 0xEACBA988; - -imm32 r0, 0x01264567; -imm32 r1, 0x89a6cdef; -imm32 r2, 0x56769abc; -imm32 r3, 0xdef61234; -imm32 r4, 0x23466899; -imm32 r5, 0x78962345; -imm32 r6, 0x98765432; -imm32 r7, 0x12365678; -R0 = R6 - R0; -R1 = R6 - R1; -R2 = R6 - R2; -R3 = R6 - R3; -R4 = R6 - R4; -R5 = R6 - R5; -R6 = R6 - R6; -R7 = R6 - R7; -CHECKREG r0, 0x97500ECB; -CHECKREG r1, 0x0ECF8643; -CHECKREG r2, 0x41FFB976; -CHECKREG r3, 0xB98041FE; -CHECKREG r4, 0x752FEB99; -CHECKREG r5, 0x1FE030ED; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0xEDC9A988; - -imm32 r0, 0x01237567; -imm32 r1, 0x89ab7def; -imm32 r2, 0x56787abc; -imm32 r3, 0xdef07234; -imm32 r4, 0x23457899; -imm32 r5, 0x78917345; -imm32 r6, 0x98767432; -imm32 r7, 0x12345678; -R0 = R7 - R0; -R1 = R7 - R1; -R2 = R7 - R2; -R3 = R7 - R3; -R4 = R7 - R4; -R5 = R7 - R5; -R6 = R7 - R6; -R7 = R7 - R7; -CHECKREG r0, 0x1110E111; -CHECKREG r1, 0x8888D889; -CHECKREG r2, 0xBBBBDBBC; -CHECKREG r3, 0x3343E444; -CHECKREG r4, 0xEEEEDDDF; -CHECKREG r5, 0x99A2E333; -CHECKREG r6, 0x79BDE246; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x11234567; -imm32 r1, 0x81abcdef; -imm32 r2, 0x56189abc; -imm32 r3, 0xdef11234; -imm32 r4, 0x23451899; -imm32 r5, 0x78912145; -imm32 r6, 0x98765412; -imm32 r7, 0x12345671; -R0 = R1 - R0; -R1 = R2 - R0; -R2 = R3 - R0; -R3 = R4 - R0; -R4 = R5 - R0; -R5 = R6 - R0; -R6 = R7 - R0; -R7 = R0 - R0; -CHECKREG r0, 0x70888888; -CHECKREG r1, 0xE5901234; -CHECKREG r2, 0x6E6889AC; -CHECKREG r3, 0xB2BC9011; -CHECKREG r4, 0x080898BD; -CHECKREG r5, 0x27EDCB8A; -CHECKREG r6, 0xA1ABCDE9; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x01231567; -imm32 r1, 0x29ab1def; -imm32 r2, 0x52781abc; -imm32 r3, 0xde201234; -imm32 r4, 0x23421899; -imm32 r5, 0x78912345; -imm32 r6, 0x98761232; -imm32 r7, 0x12341628; -R0 = R2 - R1; -R1 = R3 - R1; -R2 = R4 - R1; -R3 = R5 - R1; -R4 = R6 - R1; -R5 = R7 - R1; -R6 = R0 - R1; -R7 = R1 - R1; -CHECKREG r0, 0x28CCFCCD; -CHECKREG r1, 0xB474F445; -CHECKREG r2, 0x6ECD2454; -CHECKREG r3, 0xC41C2F00; -CHECKREG r4, 0xE4011DED; -CHECKREG r5, 0x5DBF21E3; -CHECKREG r6, 0x74580888; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x03234527; -imm32 r1, 0x893bcd2f; -imm32 r2, 0x56739a2c; -imm32 r3, 0x3ef03224; -imm32 r4, 0x23456329; -imm32 r5, 0x78312335; -imm32 r6, 0x98735423; -imm32 r7, 0x12343628; -R0 = R4 - R2; -R1 = R5 - R2; -R2 = R6 - R2; -R3 = R7 - R2; -R4 = R0 - R2; -R5 = R1 - R2; -R6 = R2 - R2; -R7 = R3 - R2; -CHECKREG r0, 0xCCD1C8FD; -CHECKREG r1, 0x21BD8909; -CHECKREG r2, 0x41FFB9F7; -CHECKREG r3, 0xD0347C31; -CHECKREG r4, 0x8AD20F06; -CHECKREG r5, 0xDFBDCF12; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x8E34C23A; - -imm32 r0, 0x04234563; -imm32 r1, 0x894bcde3; -imm32 r2, 0x56749ab3; -imm32 r3, 0x4ef04233; -imm32 r4, 0x24456493; -imm32 r5, 0x78412344; -imm32 r6, 0x98745434; -imm32 r7, 0x12344673; -R0 = R5 - R3; -R1 = R6 - R3; -R2 = R7 - R3; -R3 = R0 - R3; -R4 = R1 - R3; -R5 = R2 - R3; -R6 = R3 - R3; -R7 = R4 - R3; -CHECKREG r0, 0x2950E111; -CHECKREG r1, 0x49841201; -CHECKREG r2, 0xC3440440; -CHECKREG r3, 0xDA609EDE; -CHECKREG r4, 0x6F237323; -CHECKREG r5, 0xE8E36562; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x94C2D445; - -imm32 r0, 0x41235567; -imm32 r1, 0x49abc5ef; -imm32 r2, 0x46789a5c; -imm32 r3, 0x4ef01235; -imm32 r4, 0x53456899; -imm32 r5, 0x45912345; -imm32 r6, 0x48565432; -imm32 r7, 0x42355678; -R0 = R6 - R4; -R1 = R7 - R4; -R2 = R0 - R4; -R3 = R1 - R4; -R4 = R2 - R4; -R5 = R3 - R4; -R6 = R4 - R4; -R7 = R5 - R4; -CHECKREG r0, 0xF510EB99; -CHECKREG r1, 0xEEEFEDDF; -CHECKREG r2, 0xA1CB8300; -CHECKREG r3, 0x9BAA8546; -CHECKREG r4, 0x4E861A67; -CHECKREG r5, 0x4D246ADF; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0xFE9E5078; - -imm32 r0, 0x05264567; -imm32 r1, 0x85ab6def; -imm32 r2, 0x657896bc; -imm32 r3, 0xd6f01264; -imm32 r4, 0x25656896; -imm32 r5, 0x75962345; -imm32 r6, 0x95766432; -imm32 r7, 0x15345678; -R0 = R7 - R5; -R1 = R0 - R5; -R2 = R1 - R5; -R3 = R2 - R5; -R4 = R3 - R5; -R5 = R4 - R5; -R6 = R5 - R5; -R7 = R6 - R5; -CHECKREG r0, 0x9F9E3333; -CHECKREG r1, 0x2A080FEE; -CHECKREG r2, 0xB471ECA9; -CHECKREG r3, 0x3EDBC964; -CHECKREG r4, 0xC945A61F; -CHECKREG r5, 0x53AF82DA; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0xAC507D26; - -imm32 r0, 0x01764567; -imm32 r1, 0x89a7cdef; -imm32 r2, 0x56767abc; -imm32 r3, 0xdef61734; -imm32 r4, 0x73466879; -imm32 r5, 0x77962347; -imm32 r6, 0x98765432; -imm32 r7, 0x12375678; -R0 = R7 - R6; -R1 = R0 - R6; -R2 = R1 - R6; -R3 = R2 - R6; -R4 = R3 - R6; -R5 = R4 - R6; -R6 = R5 - R6; -R7 = R6 - R6; -CHECKREG r0, 0x79C10246; -CHECKREG r1, 0xE14AAE14; -CHECKREG r2, 0x48D459E2; -CHECKREG r3, 0xB05E05B0; -CHECKREG r4, 0x17E7B17E; -CHECKREG r5, 0x7F715D4C; -CHECKREG r6, 0xE6FB091A; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x81238567; -imm32 r1, 0x88ab78ef; -imm32 r2, 0x56887a8c; -imm32 r3, 0x8ef87238; -imm32 r4, 0x28458899; -imm32 r5, 0x78817845; -imm32 r6, 0x98787482; -imm32 r7, 0x12348678; -R0 = R1 - R7; -R1 = R2 - R7; -R2 = R3 - R7; -R3 = R4 - R7; -R4 = R5 - R7; -R5 = R6 - R7; -R6 = R7 - R7; -R7 = R0 - R7; -CHECKREG r0, 0x7676F277; -CHECKREG r1, 0x4453F414; -CHECKREG r2, 0x7CC3EBC0; -CHECKREG r3, 0x16110221; -CHECKREG r4, 0x664CF1CD; -CHECKREG r5, 0x8643EE0A; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x64426BFF; - - -pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_dr_mix.s b/sim/testsuite/sim/bfin/c_comp3op_dr_mix.s deleted file mode 100644 index 4920918..0000000 --- a/sim/testsuite/sim/bfin/c_comp3op_dr_mix.s +++ /dev/null @@ -1,237 +0,0 @@ -//Original:/testcases/core/c_comp3op_dr_mix/c_comp3op_dr_mix.dsp -// Spec Reference: comp3op dregs mix -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x01234567; -imm32 r1, 0x89abcdef; -imm32 r2, 0x56789abc; -imm32 r3, 0xdef01234; -imm32 r4, 0x23456899; -imm32 r5, 0x78912345; -imm32 r6, 0x98765432; -imm32 r7, 0x12345678; -R0 = R0 + R0; -R1 = R0 - R1; -R2 = R0 & R2; -R3 = R0 | R3; -R4 = R0 & R4; -R5 = R0 & R5; -R6 = R0 | R6; -R7 = R0 & R7; -CHECKREG r0, 0x02468ACE; -CHECKREG r1, 0x789ABCDF; -CHECKREG r2, 0x02408A8C; -CHECKREG r3, 0xDEF69AFE; -CHECKREG r4, 0x02440888; -CHECKREG r5, 0x00000244; -CHECKREG r6, 0x9A76DEFE; -CHECKREG r7, 0x02040248; - -imm32 r0, 0x01231567; -imm32 r1, 0x89ab1def; -imm32 r2, 0x56781abc; -imm32 r3, 0xdef01234; -imm32 r4, 0x23451899; -imm32 r5, 0x78911345; -imm32 r6, 0x98761432; -imm32 r7, 0x12341678; -R0 = R1 + R0; -R1 = R1 - R1; -R2 = R1 & R2; -R3 = R1 | R3; -R4 = R1 & R4; -R5 = R1 & R5; -R6 = R1 | R6; -R7 = R1 & R7; -CHECKREG r0, 0x8ACE3356; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0xDEF01234; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x98761432; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x01234527; -imm32 r1, 0x89abcd2f; -imm32 r2, 0x56789a2c; -imm32 r3, 0xdef01224; -imm32 r4, 0x23456829; -imm32 r5, 0x78912325; -imm32 r6, 0x98765422; -imm32 r7, 0x12345628; -R0 = R2 + R0; -R1 = R2 - R1; -R2 = R2 & R2; -R3 = R2 | R3; -R4 = R2 & R4; -R5 = R2 & R5; -R6 = R2 | R6; -R7 = R2 & R7; -CHECKREG r0, 0x579BDF53; -CHECKREG r1, 0xCCCCCCFD; -CHECKREG r2, 0x56789A2C; -CHECKREG r3, 0xDEF89A2C; -CHECKREG r4, 0x02400828; -CHECKREG r5, 0x50100224; -CHECKREG r6, 0xDE7EDE2E; -CHECKREG r7, 0x12301228; - -imm32 r0, 0x01234563; -imm32 r1, 0x89abcde3; -imm32 r2, 0x56789ab3; -imm32 r3, 0xdef01233; -imm32 r4, 0x23456893; -imm32 r5, 0x78912343; -imm32 r6, 0x98765433; -imm32 r7, 0x12345673; -R0 = R3 + R0; -R1 = R3 - R1; -R2 = R3 & R2; -R3 = R3 | R3; -R4 = R3 & R4; -R5 = R3 - R5; -R6 = R3 | R6; -R7 = R3 & R7; -CHECKREG r0, 0xE0135796; -CHECKREG r1, 0x55444450; -CHECKREG r2, 0x56701233; -CHECKREG r3, 0xDEF01233; -CHECKREG r4, 0x02400013; -CHECKREG r5, 0x665EEEF0; -CHECKREG r6, 0xDEF65633; -CHECKREG r7, 0x12301233; - -imm32 r0, 0x41234567; -imm32 r1, 0x49abcdef; -imm32 r2, 0x46789abc; -imm32 r3, 0x4ef01234; -imm32 r4, 0x43456899; -imm32 r5, 0x48912345; -imm32 r6, 0x48765432; -imm32 r7, 0x42345678; -R0 = R4 + R0; -R1 = R4 - R1; -R2 = R4 & R2; -R3 = R4 | R3; -R4 = R4 & R4; -R5 = R4 & R5; -R6 = R4 | R6; -R7 = R4 & R7; -CHECKREG r0, 0x8468AE00; -CHECKREG r1, 0xF9999AAA; -CHECKREG r2, 0x42400898; -CHECKREG r3, 0x4FF57ABD; -CHECKREG r4, 0x43456899; -CHECKREG r5, 0x40012001; -CHECKREG r6, 0x4B777CBB; -CHECKREG r7, 0x42044018; - -imm32 r0, 0x05234567; -imm32 r1, 0x85abcdef; -imm32 r2, 0x55789abc; -imm32 r3, 0xd5f01234; -imm32 r4, 0x25456899; -imm32 r5, 0x75912345; -imm32 r6, 0x95765432; -imm32 r7, 0x15345678; -R0 = R5 + R0; -R1 = R5 - R1; -R2 = R5 & R2; -R3 = R5 | R3; -R4 = R5 & R4; -R5 = R5 & R5; -R6 = R5 | R6; -R7 = R5 & R7; -CHECKREG r0, 0x7AB468AC; -CHECKREG r1, 0xEFE55556; -CHECKREG r2, 0x55100204; -CHECKREG r3, 0xF5F13375; -CHECKREG r4, 0x25012001; -CHECKREG r5, 0x75912345; -CHECKREG r6, 0xF5F77777; -CHECKREG r7, 0x15100240; - -imm32 r0, 0x01264567; -imm32 r1, 0x89a6cdef; -imm32 r2, 0x56769abc; -imm32 r3, 0xdef61234; -imm32 r4, 0x23466899; -imm32 r5, 0x78962345; -imm32 r6, 0x98765432; -imm32 r7, 0x12365678; -R0 = R6 + R0; -R1 = R6 - R1; -R2 = R6 & R2; -R3 = R6 | R3; -R4 = R6 & R4; -R5 = R6 & R5; -R6 = R6 | R6; -R7 = R6 & R7; -CHECKREG r0, 0x999C9999; -CHECKREG r1, 0x0ECF8643; -CHECKREG r2, 0x10761030; -CHECKREG r3, 0xDEF65636; -CHECKREG r4, 0x00464010; -CHECKREG r5, 0x18160000; -CHECKREG r6, 0x98765432; -CHECKREG r7, 0x10365430; - -imm32 r0, 0x01237567; -imm32 r1, 0x89ab7def; -imm32 r2, 0x56787abc; -imm32 r3, 0xdef07234; -imm32 r4, 0x23457899; -imm32 r5, 0x78917345; -imm32 r6, 0x98767432; -imm32 r7, 0x12345678; -R0 = R7 + R0; -R1 = R7 - R1; -R2 = R7 & R2; -R3 = R7 | R3; -R4 = R7 & R4; -R5 = R7 - R5; -R6 = R7 | R6; -R7 = R7 & R7; -CHECKREG r0, 0x1357CBDF; -CHECKREG r1, 0x8888D889; -CHECKREG r2, 0x12305238; -CHECKREG r3, 0xDEF4767C; -CHECKREG r4, 0x02045018; -CHECKREG r5, 0x99A2E333; -CHECKREG r6, 0x9A76767A; -CHECKREG r7, 0x12345678; - - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; - - -R0 = R1 + R2; -R1 = R3 - R2; -R2 = R4 & R3; -R3 = R5 | R4; -R4 = R6 & R7; -CHECKREG r0, 0x00060008; -CHECKREG r1, 0x00020002; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x000A000B; -CHECKREG r4, 0x000C000D; -CHECKREG r5, 0x000a000b; -CHECKREG r6, 0x000c000d; -CHECKREG r7, 0x000e000f; - - -pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_dr_or_dr.s b/sim/testsuite/sim/bfin/c_comp3op_dr_or_dr.s deleted file mode 100644 index 36e6401..0000000 --- a/sim/testsuite/sim/bfin/c_comp3op_dr_or_dr.s +++ /dev/null @@ -1,412 +0,0 @@ -//Original:/testcases/core/c_comp3op_dr_or_dr/c_comp3op_dr_or_dr.dsp -// Spec Reference: comp3op dregs | dregs -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x01234567; -imm32 r1, 0x89abcdef; -imm32 r2, 0x56789abc; -imm32 r3, 0xdef01234; -imm32 r4, 0x23456899; -imm32 r5, 0x78912345; -imm32 r6, 0x98765432; -imm32 r7, 0x12345678; -R0 = R0 | R0; -R1 = R0 | R1; -R2 = R0 | R2; -R3 = R0 | R3; -R4 = R0 | R4; -R5 = R0 | R5; -R6 = R0 | R6; -R7 = R0 | R7; -CHECKREG r0, 0x01234567; -CHECKREG r1, 0x89ABCDEF; -CHECKREG r2, 0x577BDFFF; -CHECKREG r3, 0xDFF35777; -CHECKREG r4, 0x23676DFF; -CHECKREG r5, 0x79B36767; -CHECKREG r6, 0x99775577; -CHECKREG r7, 0x1337577F; - -imm32 r0, 0x01231567; -imm32 r1, 0x89ab1def; -imm32 r2, 0x56781abc; -imm32 r3, 0xdef01234; -imm32 r4, 0x23451899; -imm32 r5, 0x78911345; -imm32 r6, 0x98761432; -imm32 r7, 0x12341678; -R0 = R1 | R0; -R1 = R1 | R1; -R2 = R1 | R2; -R3 = R1 | R3; -R4 = R1 | R4; -R5 = R1 | R5; -R6 = R1 | R6; -R7 = R1 | R7; -CHECKREG r0, 0x89AB1DEF; -CHECKREG r1, 0x89AB1DEF; -CHECKREG r2, 0xDFFB1FFF; -CHECKREG r3, 0xDFFB1FFF; -CHECKREG r4, 0xABEF1DFF; -CHECKREG r5, 0xF9BB1FEF; -CHECKREG r6, 0x99FF1DFF; -CHECKREG r7, 0x9BBF1FFF; - -imm32 r0, 0x01234527; -imm32 r1, 0x89abcd2f; -imm32 r2, 0x56789a2c; -imm32 r3, 0xdef01224; -imm32 r4, 0x23456829; -imm32 r5, 0x78912325; -imm32 r6, 0x98765422; -imm32 r7, 0x12345628; -R0 = R2 | R0; -R1 = R2 | R1; -R2 = R2 | R2; -R3 = R2 | R3; -R4 = R2 | R4; -R5 = R2 | R5; -R6 = R2 | R6; -R7 = R2 | R7; -CHECKREG r0, 0x577BDF2F; -CHECKREG r1, 0xDFFBDF2F; -CHECKREG r2, 0x56789A2C; -CHECKREG r3, 0xDEF89A2C; -CHECKREG r4, 0x777DFA2D; -CHECKREG r5, 0x7EF9BB2D; -CHECKREG r6, 0xDE7EDE2E; -CHECKREG r7, 0x567CDE2C; - -imm32 r0, 0x01234563; -imm32 r1, 0x89abcde3; -imm32 r2, 0x56789ab3; -imm32 r3, 0xdef01233; -imm32 r4, 0x23456893; -imm32 r5, 0x78912343; -imm32 r6, 0x98765433; -imm32 r7, 0x12345673; -R0 = R3 | R0; -R1 = R3 | R1; -R2 = R3 | R2; -R3 = R3 | R3; -R4 = R3 | R4; -R5 = R3 | R5; -R6 = R3 | R6; -R7 = R3 | R7; -CHECKREG r0, 0xDFF35773; -CHECKREG r1, 0xDFFBDFF3; -CHECKREG r2, 0xDEF89AB3; -CHECKREG r3, 0xDEF01233; -CHECKREG r4, 0xFFF57AB3; -CHECKREG r5, 0xFEF13373; -CHECKREG r6, 0xDEF65633; -CHECKREG r7, 0xDEF45673; - -imm32 r0, 0x41234567; -imm32 r1, 0x49abcdef; -imm32 r2, 0x46789abc; -imm32 r3, 0x4ef01234; -imm32 r4, 0x43456899; -imm32 r5, 0x48912345; -imm32 r6, 0x48765432; -imm32 r7, 0x42345678; -R0 = R4 | R0; -R1 = R4 | R1; -R2 = R4 | R2; -R3 = R4 | R3; -R4 = R4 | R4; -R5 = R4 | R5; -R6 = R4 | R6; -R7 = R4 | R7; -CHECKREG r0, 0x43676DFF; -CHECKREG r1, 0x4BEFEDFF; -CHECKREG r2, 0x477DFABD; -CHECKREG r3, 0x4FF57ABD; -CHECKREG r4, 0x43456899; -CHECKREG r5, 0x4BD56BDD; -CHECKREG r6, 0x4B777CBB; -CHECKREG r7, 0x43757EF9; - -imm32 r0, 0x05234567; -imm32 r1, 0x85abcdef; -imm32 r2, 0x55789abc; -imm32 r3, 0xd5f01234; -imm32 r4, 0x25456899; -imm32 r5, 0x75912345; -imm32 r6, 0x95765432; -imm32 r7, 0x15345678; -R0 = R5 | R0; -R1 = R5 | R1; -R2 = R5 | R2; -R3 = R5 | R3; -R4 = R5 | R4; -R5 = R5 | R5; -R6 = R5 | R6; -R7 = R5 | R7; -CHECKREG r0, 0x75B36767; -CHECKREG r1, 0xF5BBEFEF; -CHECKREG r2, 0x75F9BBFD; -CHECKREG r3, 0xF5F13375; -CHECKREG r4, 0x75D56BDD; -CHECKREG r5, 0x75912345; -CHECKREG r6, 0xF5F77777; -CHECKREG r7, 0x75B5777D; - -imm32 r0, 0x01264567; -imm32 r1, 0x89a6cdef; -imm32 r2, 0x56769abc; -imm32 r3, 0xdef61234; -imm32 r4, 0x23466899; -imm32 r5, 0x78962345; -imm32 r6, 0x98765432; -imm32 r7, 0x12365678; -R0 = R6 | R0; -R1 = R6 | R1; -R2 = R6 | R2; -R3 = R6 | R3; -R4 = R6 | R4; -R5 = R6 | R5; -R6 = R6 | R6; -R7 = R6 | R7; -CHECKREG r0, 0x99765577; -CHECKREG r1, 0x99F6DDFF; -CHECKREG r2, 0xDE76DEBE; -CHECKREG r3, 0xDEF65636; -CHECKREG r4, 0xBB767CBB; -CHECKREG r5, 0xF8F67777; -CHECKREG r6, 0x98765432; -CHECKREG r7, 0x9A76567A; - -imm32 r0, 0x01237567; -imm32 r1, 0x89ab7def; -imm32 r2, 0x56787abc; -imm32 r3, 0xdef07234; -imm32 r4, 0x23457899; -imm32 r5, 0x78917345; -imm32 r6, 0x98767432; -imm32 r7, 0x12345678; -R0 = R7 | R0; -R1 = R7 | R1; -R2 = R7 | R2; -R3 = R7 | R3; -R4 = R7 | R4; -R5 = R7 | R5; -R6 = R7 | R6; -R7 = R7 | R7; -CHECKREG r0, 0x1337777F; -CHECKREG r1, 0x9BBF7FFF; -CHECKREG r2, 0x567C7EFC; -CHECKREG r3, 0xDEF4767C; -CHECKREG r4, 0x33757EF9; -CHECKREG r5, 0x7AB5777D; -CHECKREG r6, 0x9A76767A; -CHECKREG r7, 0x12345678; - -imm32 r0, 0x11234567; -imm32 r1, 0x81abcdef; -imm32 r2, 0x56189abc; -imm32 r3, 0xdef11234; -imm32 r4, 0x23451899; -imm32 r5, 0x78912145; -imm32 r6, 0x98765412; -imm32 r7, 0x12345671; -R0 = R1 | R0; -R1 = R2 | R0; -R2 = R3 | R0; -R3 = R4 | R0; -R4 = R5 | R0; -R5 = R6 | R0; -R6 = R7 | R0; -R7 = R0 | R0; -CHECKREG r0, 0x91ABCDEF; -CHECKREG r1, 0xD7BBDFFF; -CHECKREG r2, 0xDFFBDFFF; -CHECKREG r3, 0xB3EFDDFF; -CHECKREG r4, 0xF9BBEDEF; -CHECKREG r5, 0x99FFDDFF; -CHECKREG r6, 0x93BFDFFF; -CHECKREG r7, 0x91ABCDEF; - -imm32 r0, 0x01231567; -imm32 r1, 0x29ab1def; -imm32 r2, 0x52781abc; -imm32 r3, 0xde201234; -imm32 r4, 0x23421899; -imm32 r5, 0x78912345; -imm32 r6, 0x98761232; -imm32 r7, 0x12341628; -R0 = R2 | R1; -R1 = R3 | R1; -R2 = R4 | R1; -R3 = R5 | R1; -R4 = R6 | R1; -R5 = R7 | R1; -R6 = R0 | R1; -R7 = R1 | R1; -CHECKREG r0, 0x7BFB1FFF; -CHECKREG r1, 0xFFAB1FFF; -CHECKREG r2, 0xFFEB1FFF; -CHECKREG r3, 0xFFBB3FFF; -CHECKREG r4, 0xFFFF1FFF; -CHECKREG r5, 0xFFBF1FFF; -CHECKREG r6, 0xFFFB1FFF; -CHECKREG r7, 0xFFAB1FFF; - -imm32 r0, 0x03234527; -imm32 r1, 0x893bcd2f; -imm32 r2, 0x56739a2c; -imm32 r3, 0x3ef03224; -imm32 r4, 0x23456329; -imm32 r5, 0x78312335; -imm32 r6, 0x98735423; -imm32 r7, 0x12343628; -R0 = R4 | R2; -R1 = R5 | R2; -R2 = R6 | R2; -R3 = R7 | R2; -R4 = R0 | R2; -R5 = R1 | R2; -R6 = R2 | R2; -R7 = R3 | R2; -CHECKREG r0, 0x7777FB2D; -CHECKREG r1, 0x7E73BB3D; -CHECKREG r2, 0xDE73DE2F; -CHECKREG r3, 0xDE77FE2F; -CHECKREG r4, 0xFF77FF2F; -CHECKREG r5, 0xFE73FF3F; -CHECKREG r6, 0xDE73DE2F; -CHECKREG r7, 0xDE77FE2F; - -imm32 r0, 0x04234563; -imm32 r1, 0x894bcde3; -imm32 r2, 0x56749ab3; -imm32 r3, 0x4ef04233; -imm32 r4, 0x24456493; -imm32 r5, 0x78412344; -imm32 r6, 0x98745434; -imm32 r7, 0x12344673; -R0 = R5 | R3; -R1 = R6 | R3; -R2 = R7 | R3; -R3 = R0 | R3; -R4 = R1 | R3; -R5 = R2 | R3; -R6 = R3 | R3; -R7 = R4 | R3; -CHECKREG r0, 0x7EF16377; -CHECKREG r1, 0xDEF45637; -CHECKREG r2, 0x5EF44673; -CHECKREG r3, 0x7EF16377; -CHECKREG r4, 0xFEF57777; -CHECKREG r5, 0x7EF56777; -CHECKREG r6, 0x7EF16377; -CHECKREG r7, 0xFEF57777; - -imm32 r0, 0x41235567; -imm32 r1, 0x49abc5ef; -imm32 r2, 0x46789a5c; -imm32 r3, 0x4ef01235; -imm32 r4, 0x53456899; -imm32 r5, 0x45912345; -imm32 r6, 0x48565432; -imm32 r7, 0x42355678; -R0 = R6 | R4; -R1 = R7 | R4; -R2 = R0 | R4; -R3 = R1 | R4; -R4 = R2 | R4; -R5 = R3 | R4; -R6 = R4 | R4; -R7 = R5 | R4; -CHECKREG r0, 0x5B577CBB; -CHECKREG r1, 0x53757EF9; -CHECKREG r2, 0x5B577CBB; -CHECKREG r3, 0x53757EF9; -CHECKREG r4, 0x5B577CBB; -CHECKREG r5, 0x5B777EFB; -CHECKREG r6, 0x5B577CBB; -CHECKREG r7, 0x5B777EFB; - -imm32 r0, 0x05264567; -imm32 r1, 0x85ab6def; -imm32 r2, 0x657896bc; -imm32 r3, 0xd6f01264; -imm32 r4, 0x25656896; -imm32 r5, 0x75962345; -imm32 r6, 0x95766432; -imm32 r7, 0x15345678; -R0 = R7 | R5; -R1 = R0 | R5; -R2 = R1 | R5; -R3 = R2 | R5; -R4 = R3 | R5; -R5 = R4 | R5; -R6 = R5 | R5; -R7 = R6 | R5; -CHECKREG r0, 0x75B6777D; -CHECKREG r1, 0x75B6777D; -CHECKREG r2, 0x75B6777D; -CHECKREG r3, 0x75B6777D; -CHECKREG r4, 0x75B6777D; -CHECKREG r5, 0x75B6777D; -CHECKREG r6, 0x75B6777D; -CHECKREG r7, 0x75B6777D; - -imm32 r0, 0x01764567; -imm32 r1, 0x89a7cdef; -imm32 r2, 0x56767abc; -imm32 r3, 0xdef61734; -imm32 r4, 0x73466879; -imm32 r5, 0x77962347; -imm32 r6, 0x98765432; -imm32 r7, 0x12375678; -R0 = R7 | R6; -R1 = R0 | R6; -R2 = R1 | R6; -R3 = R2 | R6; -R4 = R3 | R6; -R5 = R4 | R6; -R6 = R5 | R6; -R7 = R6 | R6; -CHECKREG r0, 0x9A77567A; -CHECKREG r1, 0x9A77567A; -CHECKREG r2, 0x9A77567A; -CHECKREG r3, 0x9A77567A; -CHECKREG r4, 0x9A77567A; -CHECKREG r5, 0x9A77567A; -CHECKREG r6, 0x9A77567A; -CHECKREG r7, 0x9A77567A; - -imm32 r0, 0x81238567; -imm32 r1, 0x88ab78ef; -imm32 r2, 0x56887a8c; -imm32 r3, 0x8ef87238; -imm32 r4, 0x28458899; -imm32 r5, 0x78817845; -imm32 r6, 0x98787482; -imm32 r7, 0x12348678; -R0 = R1 | R7; -R1 = R2 | R7; -R2 = R3 | R7; -R3 = R4 | R7; -R4 = R5 | R7; -R5 = R6 | R7; -R6 = R7 | R7; -R7 = R0 | R7; -CHECKREG r0, 0x9ABFFEFF; -CHECKREG r1, 0x56BCFEFC; -CHECKREG r2, 0x9EFCF678; -CHECKREG r3, 0x3A758EF9; -CHECKREG r4, 0x7AB5FE7D; -CHECKREG r5, 0x9A7CF6FA; -CHECKREG r6, 0x12348678; -CHECKREG r7, 0x9ABFFEFF; - - -pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_dr_plus_dr.s b/sim/testsuite/sim/bfin/c_comp3op_dr_plus_dr.s deleted file mode 100644 index fff4cb7..0000000 --- a/sim/testsuite/sim/bfin/c_comp3op_dr_plus_dr.s +++ /dev/null @@ -1,412 +0,0 @@ -//Original:/testcases/core/c_comp3op_dr_plus_dr/c_comp3op_dr_plus_dr.dsp -// Spec Reference: comp3op dregs + dregs -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x01234567; -imm32 r1, 0x89abcdef; -imm32 r2, 0x56789abc; -imm32 r3, 0xdef01234; -imm32 r4, 0x23456899; -imm32 r5, 0x78912345; -imm32 r6, 0x98765432; -imm32 r7, 0x12345678; -R0 = R0 + R0; -R1 = R0 + R1; -R2 = R0 + R2; -R3 = R0 + R3; -R4 = R0 + R4; -R5 = R0 + R5; -R6 = R0 + R6; -R7 = R0 + R7; -CHECKREG r0, 0x02468ACE; -CHECKREG r1, 0x8BF258BD; -CHECKREG r2, 0x58BF258A; -CHECKREG r3, 0xE1369D02; -CHECKREG r4, 0x258BF367; -CHECKREG r5, 0x7AD7AE13; -CHECKREG r6, 0x9ABCDF00; -CHECKREG r7, 0x147AE146; - -imm32 r0, 0x01231567; -imm32 r1, 0x89ab1def; -imm32 r2, 0x56781abc; -imm32 r3, 0xdef01234; -imm32 r4, 0x23451899; -imm32 r5, 0x78911345; -imm32 r6, 0x98761432; -imm32 r7, 0x12341678; -R0 = R1 + R0; -R1 = R1 + R1; -R2 = R1 + R2; -R3 = R1 + R3; -R4 = R1 + R4; -R5 = R1 + R5; -R6 = R1 + R6; -R7 = R1 + R7; -CHECKREG r0, 0x8ACE3356; -CHECKREG r1, 0x13563BDE; -CHECKREG r2, 0x69CE569A; -CHECKREG r3, 0xF2464E12; -CHECKREG r4, 0x369B5477; -CHECKREG r5, 0x8BE74F23; -CHECKREG r6, 0xABCC5010; -CHECKREG r7, 0x258A5256; - -imm32 r0, 0x01234527; -imm32 r1, 0x89abcd2f; -imm32 r2, 0x56789a2c; -imm32 r3, 0xdef01224; -imm32 r4, 0x23456829; -imm32 r5, 0x78912325; -imm32 r6, 0x98765422; -imm32 r7, 0x12345628; -R0 = R2 + R0; -R1 = R2 + R1; -R2 = R2 + R2; -R3 = R2 + R3; -R4 = R2 + R4; -R5 = R2 + R5; -R6 = R2 + R6; -R7 = R2 + R7; -CHECKREG r0, 0x579BDF53; -CHECKREG r1, 0xE024675B; -CHECKREG r2, 0xACF13458; -CHECKREG r3, 0x8BE1467C; -CHECKREG r4, 0xD0369C81; -CHECKREG r5, 0x2582577D; -CHECKREG r6, 0x4567887A; -CHECKREG r7, 0xBF258A80; - -imm32 r0, 0x01234563; -imm32 r1, 0x89abcde3; -imm32 r2, 0x56789ab3; -imm32 r3, 0xdef01233; -imm32 r4, 0x23456893; -imm32 r5, 0x78912343; -imm32 r6, 0x98765433; -imm32 r7, 0x12345673; -R0 = R3 + R0; -R1 = R3 + R1; -R2 = R3 + R2; -R3 = R3 + R3; -R4 = R3 + R4; -R5 = R3 + R5; -R6 = R3 + R6; -R7 = R3 + R7; -CHECKREG r0, 0xE0135796; -CHECKREG r1, 0x689BE016; -CHECKREG r2, 0x3568ACE6; -CHECKREG r3, 0xBDE02466; -CHECKREG r4, 0xE1258CF9; -CHECKREG r5, 0x367147A9; -CHECKREG r6, 0x56567899; -CHECKREG r7, 0xD0147AD9; - -imm32 r0, 0x41234567; -imm32 r1, 0x49abcdef; -imm32 r2, 0x46789abc; -imm32 r3, 0x4ef01234; -imm32 r4, 0x43456899; -imm32 r5, 0x48912345; -imm32 r6, 0x48765432; -imm32 r7, 0x42345678; -R0 = R4 + R0; -R1 = R4 + R1; -R2 = R4 + R2; -R3 = R4 + R3; -R4 = R4 + R4; -R5 = R4 + R5; -R6 = R4 + R6; -R7 = R4 + R7; -CHECKREG r0, 0x8468AE00; -CHECKREG r1, 0x8CF13688; -CHECKREG r2, 0x89BE0355; -CHECKREG r3, 0x92357ACD; -CHECKREG r4, 0x868AD132; -CHECKREG r5, 0xCF1BF477; -CHECKREG r6, 0xCF012564; -CHECKREG r7, 0xC8BF27AA; - -imm32 r0, 0x05234567; -imm32 r1, 0x85abcdef; -imm32 r2, 0x55789abc; -imm32 r3, 0xd5f01234; -imm32 r4, 0x25456899; -imm32 r5, 0x75912345; -imm32 r6, 0x95765432; -imm32 r7, 0x15345678; -R0 = R5 + R0; -R1 = R5 + R1; -R2 = R5 + R2; -R3 = R5 + R3; -R4 = R5 + R4; -R5 = R5 + R5; -R6 = R5 + R6; -R7 = R5 + R7; -CHECKREG r0, 0x7AB468AC; -CHECKREG r1, 0xFB3CF134; -CHECKREG r2, 0xCB09BE01; -CHECKREG r3, 0x4B813579; -CHECKREG r4, 0x9AD68BDE; -CHECKREG r5, 0xEB22468A; -CHECKREG r6, 0x80989ABC; -CHECKREG r7, 0x00569D02; - -imm32 r0, 0x01264567; -imm32 r1, 0x89a6cdef; -imm32 r2, 0x56769abc; -imm32 r3, 0xdef61234; -imm32 r4, 0x23466899; -imm32 r5, 0x78962345; -imm32 r6, 0x98765432; -imm32 r7, 0x12365678; -R0 = R6 + R0; -R1 = R6 + R1; -R2 = R6 + R2; -R3 = R6 + R3; -R4 = R6 + R4; -R5 = R6 + R5; -R6 = R6 + R6; -R7 = R6 + R7; -CHECKREG r0, 0x999C9999; -CHECKREG r1, 0x221D2221; -CHECKREG r2, 0xEEECEEEE; -CHECKREG r3, 0x776C6666; -CHECKREG r4, 0xBBBCBCCB; -CHECKREG r5, 0x110C7777; -CHECKREG r6, 0x30ECA864; -CHECKREG r7, 0x4322FEDC; - -imm32 r0, 0x01237567; -imm32 r1, 0x89ab7def; -imm32 r2, 0x56787abc; -imm32 r3, 0xdef07234; -imm32 r4, 0x23457899; -imm32 r5, 0x78917345; -imm32 r6, 0x98767432; -imm32 r7, 0x12345678; -R0 = R7 + R0; -R1 = R7 + R1; -R2 = R7 + R2; -R3 = R7 + R3; -R4 = R7 + R4; -R5 = R7 + R5; -R6 = R7 + R6; -R7 = R7 + R7; -CHECKREG r0, 0x1357CBDF; -CHECKREG r1, 0x9BDFD467; -CHECKREG r2, 0x68ACD134; -CHECKREG r3, 0xF124C8AC; -CHECKREG r4, 0x3579CF11; -CHECKREG r5, 0x8AC5C9BD; -CHECKREG r6, 0xAAAACAAA; -CHECKREG r7, 0x2468ACF0; - -imm32 r0, 0x11234567; -imm32 r1, 0x81abcdef; -imm32 r2, 0x56189abc; -imm32 r3, 0xdef11234; -imm32 r4, 0x23451899; -imm32 r5, 0x78912145; -imm32 r6, 0x98765412; -imm32 r7, 0x12345671; -R0 = R1 + R0; -R1 = R2 + R0; -R2 = R3 + R0; -R3 = R4 + R0; -R4 = R5 + R0; -R5 = R6 + R0; -R6 = R7 + R0; -R7 = R0 + R0; -CHECKREG r0, 0x92CF1356; -CHECKREG r1, 0xE8E7AE12; -CHECKREG r2, 0x71C0258A; -CHECKREG r3, 0xB6142BEF; -CHECKREG r4, 0x0B60349B; -CHECKREG r5, 0x2B456768; -CHECKREG r6, 0xA50369C7; -CHECKREG r7, 0x259E26AC; - -imm32 r0, 0x01231567; -imm32 r1, 0x29ab1def; -imm32 r2, 0x52781abc; -imm32 r3, 0xde201234; -imm32 r4, 0x23421899; -imm32 r5, 0x78912345; -imm32 r6, 0x98761232; -imm32 r7, 0x12341628; -R0 = R2 + R1; -R1 = R3 + R1; -R2 = R4 + R1; -R3 = R5 + R1; -R4 = R6 + R1; -R5 = R7 + R1; -R6 = R0 + R1; -R7 = R1 + R1; -CHECKREG r0, 0x7C2338AB; -CHECKREG r1, 0x07CB3023; -CHECKREG r2, 0x2B0D48BC; -CHECKREG r3, 0x805C5368; -CHECKREG r4, 0xA0414255; -CHECKREG r5, 0x19FF464B; -CHECKREG r6, 0x83EE68CE; -CHECKREG r7, 0x0F966046; - -imm32 r0, 0x03234527; -imm32 r1, 0x893bcd2f; -imm32 r2, 0x56739a2c; -imm32 r3, 0x3ef03224; -imm32 r4, 0x23456329; -imm32 r5, 0x78312335; -imm32 r6, 0x98735423; -imm32 r7, 0x12343628; -R0 = R3 + R2; -R1 = R4 + R2; -R2 = R5 + R2; -R3 = R6 + R2; -R4 = R7 + R2; -R5 = R0 + R2; -R6 = R1 + R2; -R7 = R2 + R2; -CHECKREG r0, 0x9563CC50; -CHECKREG r1, 0x79B8FD55; -CHECKREG r2, 0xCEA4BD61; -CHECKREG r3, 0x67181184; -CHECKREG r4, 0xE0D8F389; -CHECKREG r5, 0x640889B1; -CHECKREG r6, 0x485DBAB6; -CHECKREG r7, 0x9D497AC2; - -imm32 r0, 0x04234563; -imm32 r1, 0x894bcde3; -imm32 r2, 0x56749ab3; -imm32 r3, 0x4ef04233; -imm32 r4, 0x24456493; -imm32 r5, 0x78412344; -imm32 r6, 0x98745434; -imm32 r7, 0x12344673; -R0 = R4 + R3; -R1 = R5 + R3; -R2 = R6 + R3; -R3 = R7 + R3; -R4 = R0 + R3; -R5 = R1 + R3; -R6 = R2 + R3; -R7 = R3 + R3; -CHECKREG r0, 0x7335A6C6; -CHECKREG r1, 0xC7316577; -CHECKREG r2, 0xE7649667; -CHECKREG r3, 0x612488A6; -CHECKREG r4, 0xD45A2F6C; -CHECKREG r5, 0x2855EE1D; -CHECKREG r6, 0x48891F0D; -CHECKREG r7, 0xC249114C; - -imm32 r0, 0x41235567; -imm32 r1, 0x49abc5ef; -imm32 r2, 0x46789a5c; -imm32 r3, 0x4ef01235; -imm32 r4, 0x53456899; -imm32 r5, 0x45912345; -imm32 r6, 0x48565432; -imm32 r7, 0x42355678; -R0 = R5 + R4; -R1 = R6 + R4; -R2 = R7 + R4; -R3 = R0 + R4; -R4 = R1 + R4; -R5 = R2 + R4; -R6 = R3 + R4; -R7 = R4 + R4; -CHECKREG r0, 0x98D68BDE; -CHECKREG r1, 0x9B9BBCCB; -CHECKREG r2, 0x957ABF11; -CHECKREG r3, 0xEC1BF477; -CHECKREG r4, 0xEEE12564; -CHECKREG r5, 0x845BE475; -CHECKREG r6, 0xDAFD19DB; -CHECKREG r7, 0xDDC24AC8; - -imm32 r0, 0x05264567; -imm32 r1, 0x85ab6def; -imm32 r2, 0x657896bc; -imm32 r3, 0xd6f01264; -imm32 r4, 0x25656896; -imm32 r5, 0x75962345; -imm32 r6, 0x95766432; -imm32 r7, 0x15345678; -R0 = R6 + R5; -R1 = R7 + R5; -R2 = R0 + R5; -R3 = R1 + R5; -R4 = R2 + R5; -R5 = R3 + R5; -R6 = R4 + R5; -R7 = R5 + R5; -CHECKREG r0, 0x0B0C8777; -CHECKREG r1, 0x8ACA79BD; -CHECKREG r2, 0x80A2AABC; -CHECKREG r3, 0x00609D02; -CHECKREG r4, 0xF638CE01; -CHECKREG r5, 0x75F6C047; -CHECKREG r6, 0x6C2F8E48; -CHECKREG r7, 0xEBED808E; - -imm32 r0, 0x01764567; -imm32 r1, 0x89a7cdef; -imm32 r2, 0x56767abc; -imm32 r3, 0xdef61734; -imm32 r4, 0x73466879; -imm32 r5, 0x77962347; -imm32 r6, 0x98765432; -imm32 r7, 0x12375678; -R0 = R7 + R6; -R1 = R0 + R6; -R2 = R1 + R6; -R3 = R2 + R6; -R4 = R3 + R6; -R5 = R4 + R6; -R6 = R5 + R6; -R7 = R6 + R6; -CHECKREG r0, 0xAAADAAAA; -CHECKREG r1, 0x4323FEDC; -CHECKREG r2, 0xDB9A530E; -CHECKREG r3, 0x7410A740; -CHECKREG r4, 0x0C86FB72; -CHECKREG r5, 0xA4FD4FA4; -CHECKREG r6, 0x3D73A3D6; -CHECKREG r7, 0x7AE747AC; - -imm32 r0, 0x81238567; -imm32 r1, 0x88ab78ef; -imm32 r2, 0x56887a8c; -imm32 r3, 0x8ef87238; -imm32 r4, 0x28458899; -imm32 r5, 0x78817845; -imm32 r6, 0x98787482; -imm32 r7, 0x12348678; -R0 = R1 + R7; -R1 = R2 + R7; -R2 = R3 + R7; -R3 = R4 + R7; -R4 = R5 + R7; -R5 = R6 + R7; -R6 = R7 + R7; -R7 = R0 + R7; -CHECKREG r0, 0x9ADFFF67; -CHECKREG r1, 0x68BD0104; -CHECKREG r2, 0xA12CF8B0; -CHECKREG r3, 0x3A7A0F11; -CHECKREG r4, 0x8AB5FEBD; -CHECKREG r5, 0xAAACFAFA; -CHECKREG r6, 0x24690CF0; -CHECKREG r7, 0xAD1485DF; - - -pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_dr_xor_dr.s b/sim/testsuite/sim/bfin/c_comp3op_dr_xor_dr.s deleted file mode 100644 index fa0db63..0000000 --- a/sim/testsuite/sim/bfin/c_comp3op_dr_xor_dr.s +++ /dev/null @@ -1,412 +0,0 @@ -//Original:/testcases/core/c_comp3op_dr_xor_dr/c_comp3op_dr_xor_dr.dsp -// Spec Reference: comp3op dregs xor dregs -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x01234567; -imm32 r1, 0x89abcdef; -imm32 r2, 0x56789abc; -imm32 r3, 0xdef01234; -imm32 r4, 0x23456899; -imm32 r5, 0x78912345; -imm32 r6, 0x98765432; -imm32 r7, 0x12345678; -R0 = R0 ^ R0; -R1 = R0 ^ R1; -R2 = R0 ^ R2; -R3 = R0 ^ R3; -R4 = R0 ^ R4; -R5 = R0 ^ R5; -R6 = R0 ^ R6; -R7 = R0 ^ R7; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x89ABCDEF; -CHECKREG r2, 0x56789ABC; -CHECKREG r3, 0xDEF01234; -CHECKREG r4, 0x23456899; -CHECKREG r5, 0x78912345; -CHECKREG r6, 0x98765432; -CHECKREG r7, 0x12345678; - -imm32 r0, 0x01231567; -imm32 r1, 0x89ab1def; -imm32 r2, 0x56781abc; -imm32 r3, 0xdef01234; -imm32 r4, 0x23451899; -imm32 r5, 0x78911345; -imm32 r6, 0x98761432; -imm32 r7, 0x12341678; -R0 = R1 ^ R0; -R1 = R1 ^ R1; -R2 = R1 ^ R2; -R3 = R1 ^ R3; -R4 = R1 ^ R4; -R5 = R1 ^ R5; -R6 = R1 ^ R6; -R7 = R1 ^ R7; -CHECKREG r0, 0x88880888; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x56781ABC; -CHECKREG r3, 0xDEF01234; -CHECKREG r4, 0x23451899; -CHECKREG r5, 0x78911345; -CHECKREG r6, 0x98761432; -CHECKREG r7, 0x12341678; - -imm32 r0, 0x01234527; -imm32 r1, 0x89abcd2f; -imm32 r2, 0x56789a2c; -imm32 r3, 0xdef01224; -imm32 r4, 0x23456829; -imm32 r5, 0x78912325; -imm32 r6, 0x98765422; -imm32 r7, 0x12345628; -R0 = R2 ^ R0; -R1 = R2 ^ R1; -R2 = R2 ^ R2; -R3 = R2 ^ R3; -R4 = R2 ^ R4; -R5 = R2 ^ R5; -R6 = R2 ^ R6; -R7 = R2 ^ R7; -CHECKREG r0, 0x575BDF0B; -CHECKREG r1, 0xDFD35703; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0xDEF01224; -CHECKREG r4, 0x23456829; -CHECKREG r5, 0x78912325; -CHECKREG r6, 0x98765422; -CHECKREG r7, 0x12345628; - -imm32 r0, 0x01234563; -imm32 r1, 0x89abcde3; -imm32 r2, 0x56789ab3; -imm32 r3, 0xdef01233; -imm32 r4, 0x23456893; -imm32 r5, 0x78912343; -imm32 r6, 0x98765433; -imm32 r7, 0x12345673; -R0 = R3 ^ R0; -R1 = R3 ^ R1; -R2 = R3 ^ R2; -R3 = R3 ^ R3; -R4 = R3 ^ R4; -R5 = R3 ^ R5; -R6 = R3 ^ R6; -R7 = R3 ^ R7; -CHECKREG r0, 0xDFD35750; -CHECKREG r1, 0x575BDFD0; -CHECKREG r2, 0x88888880; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x23456893; -CHECKREG r5, 0x78912343; -CHECKREG r6, 0x98765433; -CHECKREG r7, 0x12345673; - -imm32 r0, 0x41234567; -imm32 r1, 0x49abcdef; -imm32 r2, 0x46789abc; -imm32 r3, 0x4ef01234; -imm32 r4, 0x43456899; -imm32 r5, 0x48912345; -imm32 r6, 0x48765432; -imm32 r7, 0x42345678; -R0 = R4 ^ R0; -R1 = R4 ^ R1; -R2 = R4 ^ R2; -R3 = R4 ^ R3; -R4 = R4 ^ R4; -R5 = R4 ^ R5; -R6 = R4 ^ R6; -R7 = R4 ^ R7; -CHECKREG r0, 0x02662DFE; -CHECKREG r1, 0x0AEEA576; -CHECKREG r2, 0x053DF225; -CHECKREG r3, 0x0DB57AAD; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x48912345; -CHECKREG r6, 0x48765432; -CHECKREG r7, 0x42345678; - -imm32 r0, 0x05234567; -imm32 r1, 0x85abcdef; -imm32 r2, 0x55789abc; -imm32 r3, 0xd5f01234; -imm32 r4, 0x25456899; -imm32 r5, 0x75912345; -imm32 r6, 0x95765432; -imm32 r7, 0x15345678; -R0 = R5 ^ R0; -R1 = R5 ^ R1; -R2 = R5 ^ R2; -R3 = R5 ^ R3; -R4 = R5 ^ R4; -R5 = R5 ^ R5; -R6 = R5 ^ R6; -R7 = R5 ^ R7; -CHECKREG r0, 0x70B26622; -CHECKREG r1, 0xF03AEEAA; -CHECKREG r2, 0x20E9B9F9; -CHECKREG r3, 0xA0613171; -CHECKREG r4, 0x50D44BDC; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x95765432; -CHECKREG r7, 0x15345678; - -imm32 r0, 0x01264567; -imm32 r1, 0x89a6cdef; -imm32 r2, 0x56769abc; -imm32 r3, 0xdef61234; -imm32 r4, 0x23466899; -imm32 r5, 0x78962345; -imm32 r6, 0x98765432; -imm32 r7, 0x12365678; -R0 = R6 ^ R0; -R1 = R6 ^ R1; -R2 = R6 ^ R2; -R3 = R6 ^ R3; -R4 = R6 ^ R4; -R5 = R6 ^ R5; -R6 = R6 ^ R6; -R7 = R6 ^ R7; -CHECKREG r0, 0x99501155; -CHECKREG r1, 0x11D099DD; -CHECKREG r2, 0xCE00CE8E; -CHECKREG r3, 0x46804606; -CHECKREG r4, 0xBB303CAB; -CHECKREG r5, 0xE0E07777; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x12365678; - -imm32 r0, 0x01237567; -imm32 r1, 0x89ab7def; -imm32 r2, 0x56787abc; -imm32 r3, 0xdef07234; -imm32 r4, 0x23457899; -imm32 r5, 0x78917345; -imm32 r6, 0x98767432; -imm32 r7, 0x12345678; -R0 = R7 ^ R0; -R1 = R7 ^ R1; -R2 = R7 ^ R2; -R3 = R7 ^ R3; -R4 = R7 ^ R4; -R5 = R7 ^ R5; -R6 = R7 ^ R6; -R7 = R7 ^ R7; -CHECKREG r0, 0x1317231F; -CHECKREG r1, 0x9B9F2B97; -CHECKREG r2, 0x444C2CC4; -CHECKREG r3, 0xCCC4244C; -CHECKREG r4, 0x31712EE1; -CHECKREG r5, 0x6AA5253D; -CHECKREG r6, 0x8A42224A; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x11234567; -imm32 r1, 0x81abcdef; -imm32 r2, 0x56189abc; -imm32 r3, 0xdef11234; -imm32 r4, 0x23451899; -imm32 r5, 0x78912145; -imm32 r6, 0x98765412; -imm32 r7, 0x12345671; -R0 = R1 ^ R0; -R1 = R2 ^ R0; -R2 = R3 ^ R0; -R3 = R4 ^ R0; -R4 = R5 ^ R0; -R5 = R6 ^ R0; -R6 = R7 ^ R0; -R7 = R0 ^ R0; -CHECKREG r0, 0x90888888; -CHECKREG r1, 0xC6901234; -CHECKREG r2, 0x4E799ABC; -CHECKREG r3, 0xB3CD9011; -CHECKREG r4, 0xE819A9CD; -CHECKREG r5, 0x08FEDC9A; -CHECKREG r6, 0x82BCDEF9; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x01231567; -imm32 r1, 0x29ab1def; -imm32 r2, 0x52781abc; -imm32 r3, 0xde201234; -imm32 r4, 0x23421899; -imm32 r5, 0x78912345; -imm32 r6, 0x98761232; -imm32 r7, 0x12341628; -R0 = R2 ^ R1; -R1 = R3 ^ R1; -R2 = R4 ^ R1; -R3 = R5 ^ R1; -R4 = R6 ^ R1; -R5 = R7 ^ R1; -R6 = R0 ^ R1; -R7 = R1 ^ R1; -CHECKREG r0, 0x7BD30753; -CHECKREG r1, 0xF78B0FDB; -CHECKREG r2, 0xD4C91742; -CHECKREG r3, 0x8F1A2C9E; -CHECKREG r4, 0x6FFD1DE9; -CHECKREG r5, 0xE5BF19F3; -CHECKREG r6, 0x8C580888; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x03234527; -imm32 r1, 0x893bcd2f; -imm32 r2, 0x56739a2c; -imm32 r3, 0x3ef03224; -imm32 r4, 0x23456329; -imm32 r5, 0x78312335; -imm32 r6, 0x98735423; -imm32 r7, 0x12343628; -R0 = R4 ^ R2; -R1 = R5 ^ R2; -R2 = R6 ^ R2; -R3 = R7 ^ R2; -R4 = R0 ^ R2; -R5 = R1 ^ R2; -R6 = R2 ^ R2; -R7 = R3 ^ R2; -CHECKREG r0, 0x7536F905; -CHECKREG r1, 0x2E42B919; -CHECKREG r2, 0xCE00CE0F; -CHECKREG r3, 0xDC34F827; -CHECKREG r4, 0xBB36370A; -CHECKREG r5, 0xE0427716; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x12343628; - -imm32 r0, 0x04234563; -imm32 r1, 0x894bcde3; -imm32 r2, 0x56749ab3; -imm32 r3, 0x4ef04233; -imm32 r4, 0x24456493; -imm32 r5, 0x78412344; -imm32 r6, 0x98745434; -imm32 r7, 0x12344673; -R0 = R5 ^ R3; -R1 = R6 ^ R3; -R2 = R7 ^ R3; -R3 = R0 ^ R3; -R4 = R1 ^ R3; -R5 = R2 ^ R3; -R6 = R3 ^ R3; -R7 = R4 ^ R3; -CHECKREG r0, 0x36B16177; -CHECKREG r1, 0xD6841607; -CHECKREG r2, 0x5CC40440; -CHECKREG r3, 0x78412344; -CHECKREG r4, 0xAEC53543; -CHECKREG r5, 0x24852704; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0xD6841607; - -imm32 r0, 0x41235567; -imm32 r1, 0x49abc5ef; -imm32 r2, 0x46789a5c; -imm32 r3, 0x4ef01235; -imm32 r4, 0x53456899; -imm32 r5, 0x45912345; -imm32 r6, 0x48565432; -imm32 r7, 0x42355678; -R0 = R6 ^ R4; -R1 = R7 ^ R4; -R2 = R0 ^ R4; -R3 = R1 ^ R4; -R4 = R2 ^ R4; -R5 = R3 ^ R4; -R6 = R4 ^ R4; -R7 = R5 ^ R4; -CHECKREG r0, 0x1B133CAB; -CHECKREG r1, 0x11703EE1; -CHECKREG r2, 0x48565432; -CHECKREG r3, 0x42355678; -CHECKREG r4, 0x1B133CAB; -CHECKREG r5, 0x59266AD3; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x42355678; - -imm32 r0, 0x05264567; -imm32 r1, 0x85ab6def; -imm32 r2, 0x657896bc; -imm32 r3, 0xd6f01264; -imm32 r4, 0x25656896; -imm32 r5, 0x75962345; -imm32 r6, 0x95766432; -imm32 r7, 0x15345678; -R0 = R7 ^ R5; -R1 = R0 ^ R5; -R2 = R1 ^ R5; -R3 = R2 ^ R5; -R4 = R3 ^ R5; -R5 = R4 ^ R5; -R6 = R5 ^ R5; -R7 = R6 ^ R5; -CHECKREG r0, 0x60A2753D; -CHECKREG r1, 0x15345678; -CHECKREG r2, 0x60A2753D; -CHECKREG r3, 0x15345678; -CHECKREG r4, 0x60A2753D; -CHECKREG r5, 0x15345678; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x15345678; - -imm32 r0, 0x01764567; -imm32 r1, 0x89a7cdef; -imm32 r2, 0x56767abc; -imm32 r3, 0xdef61734; -imm32 r4, 0x73466879; -imm32 r5, 0x77962347; -imm32 r6, 0x98765432; -imm32 r7, 0x12375678; -R0 = R7 ^ R6; -R1 = R0 ^ R6; -R2 = R1 ^ R6; -R3 = R2 ^ R6; -R4 = R3 ^ R6; -R5 = R4 ^ R6; -R6 = R5 ^ R6; -R7 = R6 ^ R6; -CHECKREG r0, 0x8A41024A; -CHECKREG r1, 0x12375678; -CHECKREG r2, 0x8A41024A; -CHECKREG r3, 0x12375678; -CHECKREG r4, 0x8A41024A; -CHECKREG r5, 0x12375678; -CHECKREG r6, 0x8A41024A; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x81238567; -imm32 r1, 0x88ab78ef; -imm32 r2, 0x56887a8c; -imm32 r3, 0x8ef87238; -imm32 r4, 0x28458899; -imm32 r5, 0x78817845; -imm32 r6, 0x98787482; -imm32 r7, 0x12348678; -R0 = R1 ^ R7; -R1 = R2 ^ R7; -R2 = R3 ^ R7; -R3 = R4 ^ R7; -R4 = R5 ^ R7; -R5 = R6 ^ R7; -R6 = R7 ^ R7; -R7 = R0 ^ R7; -CHECKREG r0, 0x9A9FFE97; -CHECKREG r1, 0x44BCFCF4; -CHECKREG r2, 0x9CCCF440; -CHECKREG r3, 0x3A710EE1; -CHECKREG r4, 0x6AB5FE3D; -CHECKREG r5, 0x8A4CF2FA; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x88AB78EF; - - -pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh1.s b/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh1.s deleted file mode 100644 index f570a5f..0000000 --- a/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh1.s +++ /dev/null @@ -1,302 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh1/c_comp3op_pr_plus_pr_sh1.dsp -// Spec Reference: comp3op pregs + pregs << 1 -# mach: bfin - -.include "testutils.inc" - start - - imm32 p1, 0x89ab1def; - imm32 p2, 0x56781abc; - imm32 p3, 0xdef01234; - imm32 p4, 0x23451899; - imm32 p5, 0x78911345; - imm32 sp, 0x98761432; - imm32 fp, 0x12341678; - P1 = P1 + ( P1 << 1 ); - P2 = P1 + ( P2 << 1 ); - P3 = P1 + ( P3 << 1 ); - P4 = P1 + ( P4 << 1 ); - P5 = P1 + ( P5 << 1 ); - SP = P1 + ( SP << 1 ); - FP = P1 + FP; - CHECKREG p1, 0x9D0159CD; - CHECKREG p2, 0x49F18F45; - CHECKREG p3, 0x5AE17E35; - CHECKREG p4, 0xE38B8AFF; - CHECKREG p5, 0x8E238057; - CHECKREG sp, 0xCDED8231; - CHECKREG fp, 0xAF357045; - - imm32 p1, 0x89abcd2f; - imm32 p2, 0x56789a2c; - imm32 p3, 0xdef01224; - imm32 p4, 0x23456829; - imm32 p5, 0x78912325; - imm32 sp, 0x98765422; - imm32 fp, 0x12345628; - P1 = P2 + ( P1 << 1 ); - P2 = P2 + ( P2 << 1 ); - P3 = P2 + ( P3 << 1 ); - P4 = P2 + ( P4 << 1 ); - P5 = P2 + ( P5 << 1 ); - SP = P2 + ( SP << 1 ); - FP = P2 + ( FP << 1 ); - CHECKREG p1, 0x69D0348A; - CHECKREG p2, 0x0369CE84; - CHECKREG p3, 0xC149F2CC; - CHECKREG p4, 0x49F49ED6; - CHECKREG p5, 0xF48C14CE; - CHECKREG sp, 0x345676C8; - CHECKREG fp, 0x27D27AD4; - - imm32 p1, 0x89abcde3; - imm32 p2, 0x56789ab3; - imm32 p3, 0xdef01233; - imm32 p4, 0x23456893; - imm32 p5, 0x78912343; - imm32 sp, 0x98765433; - imm32 fp, 0x12345673; - P1 = P3 + ( P1 << 1 ); - P2 = P3 + ( P2 << 1 ); - P3 = P3 + ( P3 << 1 ); - P4 = P3 + ( P4 << 1 ); - P5 = P3 + ( P5 << 1 ); - SP = P3 + ( SP << 1 ); - FP = P3 + ( FP << 1 ); - CHECKREG p1, 0xF247ADF9; - CHECKREG p2, 0x8BE14799; - CHECKREG p3, 0x9CD03699; - CHECKREG p4, 0xE35B07BF; - CHECKREG p5, 0x8DF27D1F; - CHECKREG sp, 0xCDBCDEFF; - CHECKREG fp, 0xC138E37F; - - imm32 p1, 0x49abcdef; - imm32 p2, 0x46789abc; - imm32 p3, 0x4ef01234; - imm32 p4, 0x43456899; - imm32 p5, 0x48912345; - imm32 sp, 0x48765432; - imm32 fp, 0x42345678; - P1 = P4 + ( P1 << 1 ); - P2 = P4 + ( P2 << 1 ); - P3 = P4 + ( P3 << 1 ); - P4 = P4 + ( P4 << 1 ); - P5 = P4 + ( P5 << 1 ); - SP = P4 + ( SP << 1 ); - FP = P4 + ( FP << 1 ); - CHECKREG p1, 0xD69D0477; - CHECKREG p2, 0xD0369E11; - CHECKREG p3, 0xE1258D01; - CHECKREG p4, 0xC9D039CB; - CHECKREG p5, 0x5AF28055; - CHECKREG sp, 0x5ABCE22F; - CHECKREG fp, 0x4E38E6BB; - - imm32 p1, 0x85abcdef; - imm32 p2, 0x55789abc; - imm32 p3, 0xd5f01234; - imm32 p4, 0x25456899; - imm32 p5, 0x75912345; - imm32 sp, 0x95765432; - imm32 fp, 0x15345678; - P1 = P5 + ( P1 << 1 ); - P2 = P5 + ( P2 << 1 ); - P3 = P5 + ( P3 << 1 ); - P4 = P5 + ( P4 << 1 ); - P5 = P5 + ( P5 << 1 ); - SP = P5 + ( SP << 1 ); - FP = P5 + ( FP << 1 ); - CHECKREG p1, 0x80E8BF23; - CHECKREG p2, 0x208258BD; - CHECKREG p3, 0x217147AD; - CHECKREG p4, 0xC01BF477; - CHECKREG p5, 0x60B369CF; - CHECKREG sp, 0x8BA01233; - CHECKREG fp, 0x8B1C16BF; - - imm32 p1, 0x89a6cdef; - imm32 p2, 0x56769abc; - imm32 p3, 0xdef61234; - imm32 p4, 0x23466899; - imm32 p5, 0x78962345; - imm32 sp, 0x98765432; - imm32 fp, 0x12365678; - P1 = SP + ( P1 << 1 ); - P2 = SP + ( P2 << 1 ); - P3 = SP + ( P3 << 1 ); - P4 = SP + ( P4 << 1 ); - P5 = SP + ( P5 << 1 ); - SP = SP + ( SP << 1 ); - FP = SP + ( FP << 1 ); - CHECKREG p1, 0xABC3F010; - CHECKREG p2, 0x456389AA; - CHECKREG p3, 0x5662789A; - CHECKREG p4, 0xDF032564; - CHECKREG p5, 0x89A29ABC; - CHECKREG sp, 0xC962FC96; - CHECKREG fp, 0xEDCFA986; - - imm32 p1, 0x89ab7def; - imm32 p2, 0x56787abc; - imm32 p3, 0xdef07234; - imm32 p4, 0x23457899; - imm32 p5, 0x78917345; - imm32 sp, 0x98767432; - imm32 fp, 0x12345678; - P1 = FP + ( P1 << 1 ); - P2 = FP + ( P2 << 1 ); - P3 = FP + ( P3 << 1 ); - P4 = FP + ( P4 << 1 ); - P5 = FP + ( P5 << 1 ); - SP = FP + ( SP << 1 ); - FP = FP + ( FP << 1 ); - CHECKREG p1, 0x258B5256; - CHECKREG p2, 0xBF254BF0; - CHECKREG p3, 0xD0153AE0; - CHECKREG p4, 0x58BF47AA; - CHECKREG p5, 0x03573D02; - CHECKREG sp, 0x43213EDC; - CHECKREG fp, 0x369D0368; - - imm32 p1, 0x29ab1def; - imm32 p2, 0x52781abc; - imm32 p3, 0xde201234; - imm32 p4, 0x23421899; - imm32 p5, 0x78912345; - imm32 sp, 0x98761232; - imm32 fp, 0x12341628; - P1 = P3 + ( P1 << 1 ); - P2 = P4 + ( P1 << 1 ); - P3 = P5 + ( P1 << 1 ); - P4 = SP + ( P1 << 1 ); - P5 = FP + ( P1 << 1 ); - FP = P1 + ( P1 << 1 ); - CHECKREG p1, 0x31764E12; - CHECKREG p2, 0x862EB4BD; - CHECKREG p3, 0xDB7DBF69; - CHECKREG p4, 0xFB62AE56; - CHECKREG p5, 0x7520B24C; - CHECKREG fp, 0x9462EA36; - - imm32 p1, 0x893bcd2f; - imm32 p2, 0x56739a2c; - imm32 p3, 0x3ef03224; - imm32 p4, 0x23456329; - imm32 p5, 0x78312335; - imm32 sp, 0x98735423; - imm32 fp, 0x12343628; - P1 = P4 + ( P2 << 1 ); - P2 = P5 + ( P2 << 1 ); - P3 = SP + ( P2 << 1 ); - P4 = FP + ( P2 << 1 ); - SP = P1 + ( P2 << 1 ); - FP = P2 + ( P2 << 1 ); - CHECKREG p1, 0xD02C9781; - CHECKREG p2, 0x2518578D; - CHECKREG p3, 0xE2A4033D; - CHECKREG p4, 0x5C64E542; - CHECKREG sp, 0x1A5D469B; - CHECKREG fp, 0x6F4906A7; - - imm32 p1, 0x894bcde3; - imm32 p2, 0x56749ab3; - imm32 p3, 0x4ef04233; - imm32 p4, 0x24456493; - imm32 p5, 0x78412344; - imm32 sp, 0x98745434; - imm32 fp, 0x12344673; - P1 = P5 + ( P3 << 1 ); - P2 = SP + ( P3 << 1 ); - P3 = FP + ( P3 << 1 ); - P5 = P1 + ( P3 << 1 ); - SP = P2 + ( P3 << 1 ); - FP = P3 + ( P3 << 1 ); - CHECKREG p1, 0x1621A7AA; - CHECKREG p2, 0x3654D89A; - CHECKREG p3, 0xB014CAD9; - CHECKREG p5, 0x764B3D5C; - CHECKREG sp, 0x967E6E4C; - CHECKREG fp, 0x103E608B; - - imm32 p1, 0x49abc5ef; - imm32 p2, 0x46789a5c; - imm32 p3, 0x4ef01235; - imm32 p4, 0x53456899; - imm32 p5, 0x45912345; - imm32 sp, 0x48565432; - imm32 fp, 0x42355678; - P1 = SP + ( P4 << 1 ); - P2 = FP + ( P4 << 1 ); - P4 = P1 + ( P4 << 1 ); - P5 = P2 + ( P4 << 1 ); - SP = P3 + ( P4 << 1 ); - FP = P4 + ( P4 << 1 ); - CHECKREG p1, 0xEEE12564; - CHECKREG p2, 0xE8C027AA; - CHECKREG p4, 0x956BF696; - CHECKREG p5, 0x139814D6; - CHECKREG sp, 0x79C7FF61; - CHECKREG fp, 0xC043E3C2; - - imm32 p1, 0x85ab6def; - imm32 p2, 0x657896bc; - imm32 p3, 0xd6f01264; - imm32 p4, 0x25656896; - imm32 p5, 0x75962345; - imm32 sp, 0x95766432; - imm32 fp, 0x15345678; - P1 = FP + ( P5 << 1 ); - P3 = P1 + ( P5 << 1 ); - P4 = P2 + ( P5 << 1 ); - P5 = P3 + ( P5 << 1 ); - SP = P4 + ( P5 << 1 ); - FP = P5 + ( P5 << 1 ); - CHECKREG p1, 0x00609D02; - CHECKREG p3, 0xEB8CE38C; - CHECKREG p4, 0x50A4DD46; - CHECKREG p5, 0xD6B92A16; - CHECKREG sp, 0xFE173172; - CHECKREG fp, 0x842B7E42; - - imm32 p1, 0x89a7cdef; - imm32 p2, 0x56767abc; - imm32 p3, 0xdef61734; - imm32 p4, 0x73466879; - imm32 p5, 0x77962347; - imm32 sp, 0x98765432; - imm32 fp, 0x12375678; - P2 = P1 + ( SP << 1 ); - P3 = P2 + ( SP << 1 ); - P4 = P3 + ( SP << 1 ); - P5 = P4 + ( SP << 1 ); - SP = P5 + ( SP << 1 ); - FP = SP + ( SP << 1 ); - CHECKREG p2, 0xBA947653; - CHECKREG p3, 0xEB811EB7; - CHECKREG p4, 0x1C6DC71B; - CHECKREG p5, 0x4D5A6F7F; - CHECKREG sp, 0x7E4717E3; - CHECKREG fp, 0x7AD547A9; - - imm32 p1, 0x88ab78ef; - imm32 p2, 0x56887a8c; - imm32 p3, 0x8ef87238; - imm32 p4, 0x28458899; - imm32 p5, 0x78817845; - imm32 sp, 0x98787482; - imm32 fp, 0x12348678; - P1 = P2 + ( FP << 1 ); - P2 = P3 + ( FP << 1 ); - P3 = P4 + ( FP << 1 ); - P4 = P5 + ( FP << 1 ); - P5 = SP + ( FP << 1 ); - SP = FP + ( FP << 1 ); - CHECKREG p1, 0x7AF1877C; - CHECKREG p2, 0xB3617F28; - CHECKREG p3, 0x4CAE9589; - CHECKREG p4, 0x9CEA8535; - CHECKREG p5, 0xBCE18172; - CHECKREG sp, 0x369D9368; - - pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh2.s b/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh2.s deleted file mode 100644 index dd86726..0000000 --- a/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh2.s +++ /dev/null @@ -1,302 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh2/c_comp3op_pr_plus_pr_sh2.dsp -// Spec Reference: comp3op pregs + pregs << 2 -# mach: bfin - -.include "testutils.inc" - start - - imm32 p1, 0x89ab1def; - imm32 p2, 0x56781abc; - imm32 p3, 0xdef01234; - imm32 p4, 0x23451899; - imm32 p5, 0x78911345; - imm32 sp, 0x98761432; - imm32 fp, 0x12341678; - P1 = P1 + ( P1 << 2 ); - P2 = P1 + ( P2 << 2 ); - P3 = P1 + ( P3 << 2 ); - P4 = P1 + ( P4 << 2 ); - P5 = P1 + ( P5 << 2 ); - SP = P1 + ( SP << 2 ); - FP = P1 + FP; - CHECKREG p1, 0xB05795AB; - CHECKREG p2, 0x0A38009B; - CHECKREG p3, 0x2C17DE7B; - CHECKREG p4, 0x3D6BF80F; - CHECKREG p5, 0x929BE2BF; - CHECKREG sp, 0x122FE673; - CHECKREG fp, 0xC28BAC23; - - imm32 p1, 0x89abcd2f; - imm32 p2, 0x56789a2c; - imm32 p3, 0xdef01224; - imm32 p4, 0x23456829; - imm32 p5, 0x78912325; - imm32 sp, 0x98765422; - imm32 fp, 0x12345628; - P1 = P2 + ( P1 << 2 ); - P2 = P2 + ( P2 << 2 ); - P3 = P2 + ( P3 << 2 ); - P4 = P2 + ( P4 << 2 ); - P5 = P2 + ( P5 << 2 ); - SP = P2 + ( SP << 2 ); - FP = P2 + ( FP << 2 ); - CHECKREG p1, 0x7D27CEE8; - CHECKREG p2, 0xB05B02DC; - CHECKREG p3, 0x2C1B4B6C; - CHECKREG p4, 0x3D70A380; - CHECKREG p5, 0x929F8F70; - CHECKREG sp, 0x12345364; - CHECKREG fp, 0xF92C5B7C; - - imm32 p1, 0x89abcde3; - imm32 p2, 0x56789ab3; - imm32 p3, 0xdef01233; - imm32 p4, 0x23456893; - imm32 p5, 0x78912343; - imm32 sp, 0x98765433; - imm32 fp, 0x12345673; - P1 = P3 + ( P1 << 2 ); - P2 = P3 + ( P2 << 2 ); - P3 = P3 + ( P3 << 2 ); - P4 = P3 + ( P4 << 2 ); - P5 = P3 + ( P5 << 2 ); - SP = P3 + ( SP << 2 ); - FP = P3 + ( FP << 2 ); - CHECKREG p1, 0x059F49BF; - CHECKREG p2, 0x38D27CFF; - CHECKREG p3, 0x5AB05AFF; - CHECKREG p4, 0xE7C5FD4B; - CHECKREG p5, 0x3CF4E80B; - CHECKREG sp, 0xBC89ABCB; - CHECKREG fp, 0xA381B4CB; - - imm32 p1, 0x49abcdef; - imm32 p2, 0x46789abc; - imm32 p3, 0x4ef01234; - imm32 p4, 0x43456899; - imm32 p5, 0x48912345; - imm32 sp, 0x48765432; - imm32 fp, 0x42345678; - P1 = P4 + ( P1 << 2 ); - P2 = P4 + ( P2 << 2 ); - P3 = P4 + ( P3 << 2 ); - P4 = P4 + ( P4 << 2 ); - P5 = P4 + ( P5 << 2 ); - SP = P4 + ( SP << 2 ); - FP = P4 + ( FP << 2 ); - CHECKREG p1, 0x69F4A055; - CHECKREG p2, 0x5D27D389; - CHECKREG p3, 0x7F05B169; - CHECKREG p4, 0x505B0AFD; - CHECKREG p5, 0x729F9811; - CHECKREG sp, 0x72345BC5; - CHECKREG fp, 0x592C64DD; - - imm32 p1, 0x85abcdef; - imm32 p2, 0x55789abc; - imm32 p3, 0xd5f01234; - imm32 p4, 0x25456899; - imm32 p5, 0x75912345; - imm32 sp, 0x95765432; - imm32 fp, 0x15345678; - P1 = P5 + ( P1 << 2 ); - P2 = P5 + ( P2 << 2 ); - P3 = P5 + ( P3 << 2 ); - P4 = P5 + ( P4 << 2 ); - P5 = P5 + ( P5 << 2 ); - SP = P5 + ( SP << 2 ); - FP = P5 + ( FP << 2 ); - CHECKREG p1, 0x8C405B01; - CHECKREG p2, 0xCB738E35; - CHECKREG p3, 0xCD516C15; - CHECKREG p4, 0x0AA6C5A9; - CHECKREG p5, 0x4BD5B059; - CHECKREG sp, 0xA1AF0121; - CHECKREG fp, 0xA0A70A39; - - imm32 p1, 0x89a6cdef; - imm32 p2, 0x56769abc; - imm32 p3, 0xdef61234; - imm32 p4, 0x23466899; - imm32 p5, 0x78962345; - imm32 sp, 0x98765432; - imm32 fp, 0x12365678; - P1 = SP + ( P1 << 2 ); - P2 = SP + ( P2 << 2 ); - P3 = SP + ( P3 << 2 ); - P4 = SP + ( P4 << 2 ); - P5 = SP + ( P5 << 2 ); - SP = SP + ( SP << 2 ); - FP = SP + ( FP << 2 ); - CHECKREG p1, 0xBF118BEE; - CHECKREG p2, 0xF250BF22; - CHECKREG p3, 0x144E9D02; - CHECKREG p4, 0x258FF696; - CHECKREG p5, 0x7ACEE146; - CHECKREG sp, 0xFA4FA4FA; - CHECKREG fp, 0x4328FEDA; - - imm32 p1, 0x89ab7def; - imm32 p2, 0x56787abc; - imm32 p3, 0xdef07234; - imm32 p4, 0x23457899; - imm32 p5, 0x78917345; - imm32 sp, 0x98767432; - imm32 fp, 0x12345678; - P1 = FP + ( P1 << 2 ); - P2 = FP + ( P2 << 2 ); - P3 = FP + ( P3 << 2 ); - P4 = FP + ( P4 << 2 ); - P5 = FP + ( P5 << 2 ); - SP = FP + ( SP << 2 ); - FP = FP + ( FP << 2 ); - CHECKREG p1, 0x38E24E34; - CHECKREG p2, 0x6C164168; - CHECKREG p3, 0x8DF61F48; - CHECKREG p4, 0x9F4A38DC; - CHECKREG p5, 0xF47A238C; - CHECKREG sp, 0x740E2740; - CHECKREG fp, 0x5B05B058; - - imm32 p1, 0x29ab1def; - imm32 p2, 0x52781abc; - imm32 p3, 0xde201234; - imm32 p4, 0x23421899; - imm32 p5, 0x78912345; - imm32 sp, 0x98761232; - imm32 fp, 0x12341628; - P1 = P3 + ( P1 << 2 ); - P2 = P4 + ( P1 << 2 ); - P3 = P5 + ( P1 << 2 ); - P4 = SP + ( P1 << 2 ); - P5 = FP + ( P1 << 2 ); - FP = P1 + ( P1 << 2 ); - CHECKREG p1, 0x84CC89F0; - CHECKREG p2, 0x36744059; - CHECKREG p3, 0x8BC34B05; - CHECKREG p4, 0xABA839F2; - CHECKREG p5, 0x25663DE8; - CHECKREG fp, 0x97FEB1B0; - - imm32 p1, 0x893bcd2f; - imm32 p2, 0x56739a2c; - imm32 p3, 0x3ef03224; - imm32 p4, 0x23456329; - imm32 p5, 0x78312335; - imm32 sp, 0x98735423; - imm32 fp, 0x12343628; - P1 = P4 + ( P2 << 2 ); - P2 = P5 + ( P2 << 2 ); - P3 = SP + ( P2 << 2 ); - P4 = FP + ( P2 << 2 ); - SP = P1 + ( P2 << 2 ); - FP = P2 + ( P2 << 2 ); - CHECKREG p1, 0x7D13CBD9; - CHECKREG p2, 0xD1FF8BE5; - CHECKREG p3, 0xE07183B7; - CHECKREG p4, 0x5A3265BC; - CHECKREG sp, 0xC511FB6D; - CHECKREG fp, 0x19FDBB79; - - imm32 p1, 0x894bcde3; - imm32 p2, 0x56749ab3; - imm32 p3, 0x4ef04233; - imm32 p4, 0x24456493; - imm32 p5, 0x78412344; - imm32 sp, 0x98745434; - imm32 fp, 0x12344673; - P1 = P5 + ( P3 << 2 ); - P2 = SP + ( P3 << 2 ); - P3 = FP + ( P3 << 2 ); - P5 = P1 + ( P3 << 2 ); - SP = P2 + ( P3 << 2 ); - FP = P3 + ( P3 << 2 ); - CHECKREG p1, 0xB4022C10; - CHECKREG p2, 0xD4355D00; - CHECKREG p3, 0x4DF54F3F; - CHECKREG p5, 0xEBD7690C; - CHECKREG sp, 0x0C0A99FC; - CHECKREG fp, 0x85CA8C3B; - - imm32 p1, 0x49abc5ef; - imm32 p2, 0x46789a5c; - imm32 p3, 0x4ef01235; - imm32 p4, 0x53456899; - imm32 p5, 0x45912345; - imm32 sp, 0x48565432; - imm32 fp, 0x42355678; - P1 = SP + ( P4 << 2 ); - P2 = FP + ( P4 << 2 ); - P4 = P1 + ( P4 << 2 ); - P5 = P2 + ( P4 << 2 ); - SP = P3 + ( P4 << 2 ); - FP = P4 + ( P4 << 2 ); - CHECKREG p1, 0x956BF696; - CHECKREG p2, 0x8F4AF8DC; - CHECKREG p4, 0xE28198FA; - CHECKREG p5, 0x19515CC4; - CHECKREG sp, 0xD8F6761D; - CHECKREG fp, 0x6C87FCE2; - - imm32 p1, 0x85ab6def; - imm32 p2, 0x657896bc; - imm32 p3, 0xd6f01264; - imm32 p4, 0x25656896; - imm32 p5, 0x75962345; - imm32 sp, 0x95766432; - imm32 fp, 0x15345678; - P1 = FP + ( P5 << 2 ); - P3 = P1 + ( P5 << 2 ); - P4 = P2 + ( P5 << 2 ); - P5 = P3 + ( P5 << 2 ); - SP = P4 + ( P5 << 2 ); - FP = P5 + ( P5 << 2 ); - CHECKREG p1, 0xEB8CE38C; - CHECKREG p3, 0xC1E570A0; - CHECKREG p4, 0x3BD123D0; - CHECKREG p5, 0x983DFDB4; - CHECKREG sp, 0x9CC91AA0; - CHECKREG fp, 0xF935F484; - - imm32 p1, 0x89a7cdef; - imm32 p2, 0x56767abc; - imm32 p3, 0xdef61734; - imm32 p4, 0x73466879; - imm32 p5, 0x77962347; - imm32 sp, 0x98765432; - imm32 fp, 0x12375678; - P2 = P1 + ( SP << 2 ); - P3 = P2 + ( SP << 2 ); - P4 = P3 + ( SP << 2 ); - P5 = P4 + ( SP << 2 ); - SP = P5 + ( SP << 2 ); - FP = SP + ( SP << 2 ); - CHECKREG p2, 0xEB811EB7; - CHECKREG p3, 0x4D5A6F7F; - CHECKREG p4, 0xAF33C047; - CHECKREG p5, 0x110D110F; - CHECKREG sp, 0x72E661D7; - CHECKREG fp, 0x3E7FE933; - - imm32 p1, 0x88ab78ef; - imm32 p2, 0x56887a8c; - imm32 p3, 0x8ef87238; - imm32 p4, 0x28458899; - imm32 p5, 0x78817845; - imm32 sp, 0x98787482; - imm32 fp, 0x12348678; - P1 = P2 + ( FP << 2 ); - P2 = P3 + ( FP << 2 ); - P3 = P4 + ( FP << 2 ); - P4 = P5 + ( FP << 2 ); - P5 = SP + ( FP << 2 ); - SP = FP + ( FP << 2 ); - CHECKREG p1, 0x9F5A946C; - CHECKREG p2, 0xD7CA8C18; - CHECKREG p3, 0x7117A279; - CHECKREG p4, 0xC1539225; - CHECKREG p5, 0xE14A8E62; - CHECKREG sp, 0x5B06A058; - - pass diff --git a/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_n.s b/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_n.s deleted file mode 100644 index af3406b..0000000 --- a/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_n.s +++ /dev/null @@ -1,164 +0,0 @@ -//Original:/testcases/core/c_compi2opd_dr_add_i7_n/c_compi2opd_dr_add_i7_n.dsp -// Spec Reference: compi2opd dregs += imm7 negative -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -R0 += 0; -R1 += -1; -R2 += -2; -R3 += -3; -R4 += -4; -R5 += -5; -R6 += -6; -R7 += -7; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0xFFFFFFFF; -CHECKREG r2, 0xFFFFFFFE; -CHECKREG r3, 0xFFFFFFFD; -CHECKREG r4, 0xFFFFFFFC; -CHECKREG r5, 0xFFFFFFFB; -CHECKREG r6, 0xFFFFFFFA; -CHECKREG r7, 0xFFFFFFF9; - -R0 += -8; -R1 += -9; -R2 += -10; -R3 += -11; -R4 += -12; -R5 += -13; -R6 += -14; -R7 += -15; -CHECKREG r0, 0xFFFFFFF8; -CHECKREG r1, 0xFFFFFFF6; -CHECKREG r2, 0xFFFFFFF4; -CHECKREG r3, 0xFFFFFFF2; -CHECKREG r4, 0xFFFFFFF0; -CHECKREG r5, 0xFFFFFFEE; -CHECKREG r6, 0xFFFFFFEC; -CHECKREG r7, 0xFFFFFFEA; - -R0 += -16; -R1 += -17; -R2 += -18; -R3 += -19; -R4 += -20; -R5 += -21; -R6 += -22; -R7 += -23; -CHECKREG r0, 0xFFFFFFE8; -CHECKREG r1, 0xFFFFFFE5; -CHECKREG r2, 0xFFFFFFE2; -CHECKREG r3, 0xFFFFFFDF; -CHECKREG r4, 0xFFFFFFDC; -CHECKREG r5, 0xFFFFFFD9; -CHECKREG r6, 0xFFFFFFD6; -CHECKREG r7, 0xFFFFFFD3; - -R0 += -24; -R1 += -25; -R2 += -26; -R3 += -27; -R4 += -28; -R5 += -29; -R6 += -30; -R7 += -31; -CHECKREG r0, 0xFFFFFFD0; -CHECKREG r1, 0xFFFFFFCC; -CHECKREG r2, 0xFFFFFFC8; -CHECKREG r3, 0xFFFFFFC4; -CHECKREG r4, 0xFFFFFFC0; -CHECKREG r5, 0xFFFFFFBC; -CHECKREG r6, 0xFFFFFFB8; -CHECKREG r7, 0xFFFFFFB4; - -R0 += -32; -R1 += -33; -R2 += -34; -R3 += -35; -R4 += -36; -R5 += -37; -R6 += -38; -R7 += -39; -CHECKREG r0, 0xFFFFFFB0; -CHECKREG r1, 0xFFFFFFAB; -CHECKREG r2, 0xFFFFFFA6; -CHECKREG r3, 0xFFFFFFA1; -CHECKREG r4, 0xFFFFFF9C; -CHECKREG r5, 0xFFFFFF97; -CHECKREG r6, 0xFFFFFF92; -CHECKREG r7, 0xFFFFFF8D; - -R0 += -40; -R1 += -41; -R2 += -42; -R3 += -43; -R4 += -44; -R5 += -45; -R6 += -46; -R7 += -47; -CHECKREG r0, 0xFFFFFF88; -CHECKREG r1, 0xFFFFFF82; -CHECKREG r2, 0xFFFFFF7C; -CHECKREG r3, 0xFFFFFF76; -CHECKREG r4, 0xFFFFFF70; -CHECKREG r5, 0xFFFFFF6A; -CHECKREG r6, 0xFFFFFF64; -CHECKREG r7, 0xFFFFFF5E; - -R0 += -48; -R1 += -49; -R2 += -50; -R3 += -51; -R4 += -52; -R5 += -53; -R6 += -54; -R7 += -55; -CHECKREG r0, 0xFFFFFF58; -CHECKREG r1, 0xFFFFFF51; -CHECKREG r2, 0xFFFFFF4A; -CHECKREG r3, 0xFFFFFF43; -CHECKREG r4, 0xFFFFFF3C; -CHECKREG r5, 0xFFFFFF35; -CHECKREG r6, 0xFFFFFF2E; -CHECKREG r7, 0xFFFFFF27; - -R0 += -56; -R1 += -57; -R2 += -58; -R3 += -59; -R4 += -60; -R5 += -61; -R6 += -62; -R7 += -63; -CHECKREG r0, 0xFFFFFF20; -CHECKREG r1, 0xFFFFFF18; -CHECKREG r2, 0xFFFFFF10; -CHECKREG r3, 0xFFFFFF08; -CHECKREG r4, 0xFFFFFF00; -CHECKREG r5, 0xFFFFFEF8; -CHECKREG r6, 0xFFFFFEF0; -CHECKREG r7, 0xFFFFFEE8; - -R0 += -64; -R1 += -64; -R2 += -64; -R3 += -64; -R4 += -64; -R5 += -64; -R6 += -64; -R7 += -64; -CHECKREG r0, 0xFFFFFEE0; -CHECKREG r1, 0xFFFFFED8; -CHECKREG r2, 0xFFFFFED0; -CHECKREG r3, 0xFFFFFEC8; -CHECKREG r4, 0xFFFFFEC0; -CHECKREG r5, 0xFFFFFEB8; -CHECKREG r6, 0xFFFFFEB0; -CHECKREG r7, 0xFFFFFEA8; - -pass diff --git a/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_p.s b/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_p.s deleted file mode 100644 index 66b4537..0000000 --- a/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_p.s +++ /dev/null @@ -1,147 +0,0 @@ -//Original:/testcases/core/c_compi2opd_dr_add_i7_p/c_compi2opd_dr_add_i7_p.dsp -// Spec Reference: compi2opd dregs += imm7 positive -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -R0 += 0; -R1 += 1; -R2 += 2; -R3 += 3; -R4 += 4; -R5 += 5; -R6 += 6; -R7 += 7; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00000003; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x00000005; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x00000007; - -R0 += 8; -R1 += 9; -R2 += 10; -R3 += 11; -R4 += 12; -R5 += 13; -R6 += 14; -R7 += 15; -CHECKREG r0, 0x00000008; -CHECKREG r1, 0x0000000A; -CHECKREG r2, 0x0000000C; -CHECKREG r3, 0x0000000E; -CHECKREG r4, 0x00000010; -CHECKREG r5, 0x00000012; -CHECKREG r6, 0x00000014; -CHECKREG r7, 0x00000016; - -R0 += 16; -R1 += 17; -R2 += 18; -R3 += 19; -R4 += 20; -R5 += 21; -R6 += 22; -R7 += 23; -CHECKREG r0, 0x00000018; -CHECKREG r1, 0x0000001B; -CHECKREG r2, 0x0000001E; -CHECKREG r3, 0x00000021; -CHECKREG r4, 0x00000024; -CHECKREG r5, 0x00000027; -CHECKREG r6, 0x0000002A; -CHECKREG r7, 0x0000002D; - -R0 += 24; -R1 += 25; -R2 += 26; -R3 += 27; -R4 += 28; -R5 += 29; -R6 += 30; -R7 += 31; -CHECKREG r0, 0x00000030; -CHECKREG r1, 0x00000034; -CHECKREG r2, 0x00000038; -CHECKREG r3, 0x0000003C; -CHECKREG r4, 0x00000040; -CHECKREG r5, 0x00000044; -CHECKREG r6, 0x00000048; -CHECKREG r7, 0x0000004C; - -R0 += 32; -R1 += 33; -R2 += 34; -R3 += 35; -R4 += 36; -R5 += 37; -R6 += 38; -R7 += 39; -CHECKREG r0, 0x00000050; -CHECKREG r1, 0x00000055; -CHECKREG r2, 0x0000005A; -CHECKREG r3, 0x0000005F; -CHECKREG r4, 0x00000064; -CHECKREG r5, 0x00000069; -CHECKREG r6, 0x0000006E; -CHECKREG r7, 0x00000073; - -R0 += 40; -R1 += 41; -R2 += 42; -R3 += 43; -R4 += 44; -R5 += 45; -R6 += 46; -R7 += 47; -CHECKREG r0, 0x00000078; -CHECKREG r1, 0x0000007E; -CHECKREG r2, 0x00000084; -CHECKREG r3, 0x0000008A; -CHECKREG r4, 0x00000090; -CHECKREG r5, 0x00000096; -CHECKREG r6, 0x0000009C; -CHECKREG r7, 0x000000A2; - -R0 += 48; -R1 += 49; -R2 += 50; -R3 += 51; -R4 += 52; -R5 += 53; -R6 += 54; -R7 += 55; -CHECKREG r0, 0x000000A8; -CHECKREG r1, 0x000000AF; -CHECKREG r2, 0x000000B6; -CHECKREG r3, 0x000000BD; -CHECKREG r4, 0x000000C4; -CHECKREG r5, 0x000000CB; -CHECKREG r6, 0x000000D2; -CHECKREG r7, 0x000000D9; - -R0 += 56; -R1 += 57; -R2 += 58; -R3 += 59; -R4 += 60; -R5 += 61; -R6 += 62; -R7 += 63; -CHECKREG r0, 0x000000E0; -CHECKREG r1, 0x000000E8; -CHECKREG r2, 0x000000F0; -CHECKREG r3, 0x000000F8; -CHECKREG r4, 0x00000100; -CHECKREG r5, 0x00000108; -CHECKREG r6, 0x00000110; -CHECKREG r7, 0x00000118; - -pass diff --git a/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_n.s b/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_n.s deleted file mode 100644 index 509929d..0000000 --- a/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_n.s +++ /dev/null @@ -1,166 +0,0 @@ -//Original:/testcases/core/c_compi2opd_dr_eq_i7_n/c_compi2opd_dr_eq_i7_n.dsp -// Spec Reference: compi2opd dregs = imm7 negative -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - - -R0 = -0; -R1 = -1; -R2 = -2; -R3 = -3; -R4 = -4; -R5 = -5; -R6 = -6; -R7 = -7; -CHECKREG r0, -0; -CHECKREG r1, -1; -CHECKREG r2, -2; -CHECKREG r3, -3; -CHECKREG r4, -4; -CHECKREG r5, -5; -CHECKREG r6, -6; -CHECKREG r7, -7; - -R0 = -8; -R1 = -9; -R2 = -10; -R3 = -11; -R4 = -12; -R5 = -13; -R6 = -14; -R7 = -15; -CHECKREG r0, -8; -CHECKREG r1, -9; -CHECKREG r2, -10; -CHECKREG r3, -11; -CHECKREG r4, -12; -CHECKREG r5, -13; -CHECKREG r6, -14; -CHECKREG r7, -15; - -R0 = -16; -R1 = -17; -R2 = -18; -R3 = -19; -R4 = -20; -R5 = -21; -R6 = -22; -R7 = -23; -CHECKREG r0, -16; -CHECKREG r1, -17; -CHECKREG r2, -18; -CHECKREG r3, -19; -CHECKREG r4, -20; -CHECKREG r5, -21; -CHECKREG r6, -22; -CHECKREG r7, -23; - -R0 = -24; -R1 = -25; -R2 = -26; -R3 = -27; -R4 = -28; -R5 = -29; -R6 = -30; -R7 = -31; -CHECKREG r0, -24; -CHECKREG r1, -25; -CHECKREG r2, -26; -CHECKREG r3, -27; -CHECKREG r4, -28; -CHECKREG r5, -29; -CHECKREG r6, -30; -CHECKREG r7, -31; - -R0 = -32; -R1 = -33; -R2 = -34; -R3 = -35; -R4 = -36; -R5 = -37; -R6 = -38; -R7 = -39; -CHECKREG r0, -32; -CHECKREG r1, -33; -CHECKREG r2, -34; -CHECKREG r3, -35; -CHECKREG r4, -36; -CHECKREG r5, -37; -CHECKREG r6, -38; -CHECKREG r7, -39; - -R0 = -40; -R1 = -41; -R2 = -42; -R3 = -43; -R4 = -44; -R5 = -45; -R6 = -46; -R7 = -47; -CHECKREG r0, -40; -CHECKREG r1, -41; -CHECKREG r2, -42; -CHECKREG r3, -43; -CHECKREG r4, -44; -CHECKREG r5, -45; -CHECKREG r6, -46; -CHECKREG r7, -47; - -R0 = -48; -R1 = -49; -R2 = -50; -R3 = -51; -R4 = -52; -R5 = -53; -R6 = -54; -R7 = -55; -CHECKREG r0, -48; -CHECKREG r1, -49; -CHECKREG r2, -50; -CHECKREG r3, -51; -CHECKREG r4, -52; -CHECKREG r5, -53; -CHECKREG r6, -54; -CHECKREG r7, -55; - -R0 = -56; -R1 = -57; -R2 = -58; -R3 = -59; -R4 = -60; -R5 = -61; -R6 = -62; -R7 = -63; -CHECKREG r0, -56; -CHECKREG r1, -57; -CHECKREG r2, -58; -CHECKREG r3, -59; -CHECKREG r4, -60; -CHECKREG r5, -61; -CHECKREG r6, -62; -CHECKREG r7, -63; - -R0 = -64; -R1 = -64; -R2 = -64; -R3 = -64; -R4 = -64; -R5 = -64; -R6 = -64; -R7 = -64; -CHECKREG r0, -64; -CHECKREG r1, -64; -CHECKREG r2, -64; -CHECKREG r3, -64; -CHECKREG r4, -64; -CHECKREG r5, -64; -CHECKREG r6, -64; -CHECKREG r7, -64; - - -pass diff --git a/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_p.s b/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_p.s deleted file mode 100644 index 5e792cc..0000000 --- a/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_p.s +++ /dev/null @@ -1,147 +0,0 @@ -//Original:/testcases/core/c_compi2opd_dr_eq_i7_p/c_compi2opd_dr_eq_i7_p.dsp -// Spec Reference: compi2opd dregs = imm7 positive -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -R0 = 0; -R1 = 1; -R2 = 2; -R3 = 3; -R4 = 4; -R5 = 5; -R6 = 6; -R7 = 7; -CHECKREG r0, 0; -CHECKREG r1, 1; -CHECKREG r2, 2; -CHECKREG r3, 3; -CHECKREG r4, 4; -CHECKREG r5, 5; -CHECKREG r6, 6; -CHECKREG r7, 7; - -R0 = 8; -R1 = 9; -R2 = 10; -R3 = 11; -R4 = 12; -R5 = 13; -R6 = 14; -R7 = 15; -CHECKREG r0, 8; -CHECKREG r1, 9; -CHECKREG r2, 10; -CHECKREG r3, 11; -CHECKREG r4, 12; -CHECKREG r5, 13; -CHECKREG r6, 14; -CHECKREG r7, 15; - -R0 = 16; -R1 = 17; -R2 = 18; -R3 = 19; -R4 = 20; -R5 = 21; -R6 = 22; -R7 = 23; -CHECKREG r0, 16; -CHECKREG r1, 17; -CHECKREG r2, 18; -CHECKREG r3, 19; -CHECKREG r4, 20; -CHECKREG r5, 21; -CHECKREG r6, 22; -CHECKREG r7, 23; - -R0 = 24; -R1 = 25; -R2 = 26; -R3 = 27; -R4 = 28; -R5 = 29; -R6 = 30; -R7 = 31; -CHECKREG r0, 24; -CHECKREG r1, 25; -CHECKREG r2, 26; -CHECKREG r3, 27; -CHECKREG r4, 28; -CHECKREG r5, 29; -CHECKREG r6, 30; -CHECKREG r7, 31; - -R0 = 32; -R1 = 33; -R2 = 34; -R3 = 35; -R4 = 36; -R5 = 37; -R6 = 38; -R7 = 39; -CHECKREG r0, 32; -CHECKREG r1, 33; -CHECKREG r2, 34; -CHECKREG r3, 35; -CHECKREG r4, 36; -CHECKREG r5, 37; -CHECKREG r6, 38; -CHECKREG r7, 39; - -R0 = 40; -R1 = 41; -R2 = 42; -R3 = 43; -R4 = 44; -R5 = 45; -R6 = 46; -R7 = 47; -CHECKREG r0, 40; -CHECKREG r1, 41; -CHECKREG r2, 42; -CHECKREG r3, 43; -CHECKREG r4, 44; -CHECKREG r5, 45; -CHECKREG r6, 46; -CHECKREG r7, 47; - -R0 = 48; -R1 = 49; -R2 = 50; -R3 = 51; -R4 = 52; -R5 = 53; -R6 = 54; -R7 = 55; -CHECKREG r0, 48; -CHECKREG r1, 49; -CHECKREG r2, 50; -CHECKREG r3, 51; -CHECKREG r4, 52; -CHECKREG r5, 53; -CHECKREG r6, 54; -CHECKREG r7, 55; - -R0 = 56; -R1 = 57; -R2 = 58; -R3 = 59; -R4 = 60; -R5 = 61; -R6 = 62; -R7 = 63; -CHECKREG r0, 56; -CHECKREG r1, 57; -CHECKREG r2, 58; -CHECKREG r3, 59; -CHECKREG r4, 60; -CHECKREG r5, 61; -CHECKREG r6, 62; -CHECKREG r7, 63; - -pass diff --git a/sim/testsuite/sim/bfin/c_compi2opd_flags.S b/sim/testsuite/sim/bfin/c_compi2opd_flags.S deleted file mode 100644 index 5438e91..0000000 --- a/sim/testsuite/sim/bfin/c_compi2opd_flags.S +++ /dev/null @@ -1,600 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_compi2opd_flags/c_compi2opd_flags.dsp -// Spec Reference: compi2opd dregs += imm7 flags (az, an, ac, av0) -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - INIT_R_REGS 0; - ASTAT = R0; // initialize astat - -// AZ for R0 - imm32 r0, 0x00000000; - R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R0 += 1; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R0 += -1; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R1 = R0; - R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R3 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r3, (_AC0|_AC0_COPY|_AZ); - CHECKREG r4, (_AN); - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R0 - imm32 r0, 0xffffffff; - R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R1 = R0; - R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0xFFFFFFFF; - CHECKREG r1, 0x00000000; - CHECKREG r5, (_AN); - CHECKREG r6, (_AZ); - CHECKREG r7, (_AC0|_AC0_COPY|_AZ); - -// AC, AV0 for R0 - imm32 r0, 0x7fffffff; - R0 += 1; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R1 = R0; - R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R2 = R0; - R0 += -1; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x7FFFFFFE; - CHECKREG r1, 0x80000000; - CHECKREG r2, 0x7FFFFFFF; - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); //C - CHECKREG r7, (_VS|_V|_V_COPY|_AN); // A - -// AZ, AN, AC, AV0 for R0 - R0 = 0; - ASTAT = R0; - imm32 r0, 0x80000000; - R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R1 = R0; - R0 += 1; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R2 = R0; - R0 += 1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x80000001; - CHECKREG r1, 0x7FFFFFFF; - CHECKREG r2, 0x80000000; - CHECKREG r5, (_VS|_AN); - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - -// AZ for R0 - R1 = 0; - ASTAT = R1; - imm32 r1, 0x00000000; - R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R1 += 1; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R1 += -1; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R0 = R1; - R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R3 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r3, (_AC0|_AC0_COPY|_AZ); - CHECKREG r4, (_AN); - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R1 - imm32 r1, 0xffffffff; - R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R0 = R1; - R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0xFFFFFFFF; - CHECKREG r5, (_AN); - CHECKREG r6, (_AZ); - CHECKREG r7, (_AC0|_AC0_COPY|_AZ); - -// AC, AV0 for R1 - imm32 r1, 0x7fffffff; - R1 += 1; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R0 = R1; - R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R2 = R1; - R1 += -1; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x80000000; - CHECKREG r1, 0x7FFFFFFE; - CHECKREG r2, 0x7FFFFFFF; - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R1 - R1 = 0; - ASTAT = R1; - imm32 r1, 0x80000000; - R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R0 = R1; - R1 += 1; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R2 = R1; - R1 += 1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x7FFFFFFF; - CHECKREG r1, 0x80000001; - CHECKREG r2, 0x80000000; - CHECKREG r5, (_VS|_AN); - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - -// AZ for R2 - imm32 r2, 0x00000000; - ASTAT = R2; - R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R2 += 1; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R2 += -1; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R1 = R2; - R2 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R2 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R3 = ASTAT; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, (_AC0|_AC0_COPY|_AZ); - CHECKREG r4, (_AN); - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R2 - imm32 r2, 0xffffffff; - R2 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R1 = R2; - R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R2 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r2, 0xFFFFFFFF; - CHECKREG r1, 0x00000000; - CHECKREG r5, (_AN); - CHECKREG r6, (_AZ); - CHECKREG r7, (_AC0|_AC0_COPY|_AZ); - -// AC, AV0 for R2 - imm32 r2, 0x7fffffff; - R2 += 1; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R0 = R2; - R2 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R1 = R2; - R2 += -1; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x80000000; - CHECKREG r1, 0x7FFFFFFF; - CHECKREG r2, 0x7FFFFFFE; - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R2 - R2 = 0; - ASTAT = R2; - imm32 r2, 0x80000000; - R2 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R0 = R2; - R2 += 1; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R1 = R2; - R2 += 1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x7FFFFFFF; - CHECKREG r1, 0x80000000; - CHECKREG r2, 0x80000001; - CHECKREG r5, (_VS|_AN); - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - -// AZ for R3 - imm32 r3, 0x00000000; - ASTAT = R3; - R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R3 += 1; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R3 += -1; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R0 = R3; - R3 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R3 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R2 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r2, (_AC0|_AC0_COPY|_AZ); - CHECKREG r3, 0x00000000; - CHECKREG r4, (_AN); - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R3 - imm32 r3, 0xffffffff; - R3 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R0 = R3; - R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R3 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r3, 0xFFFFFFFF; - CHECKREG r5, (_AN); - CHECKREG r6, (_AZ); - CHECKREG r7, (_AC0|_AC0_COPY|_AZ); - -// AC, AV0 for R3 - imm32 r3, 0x7fffffff; - R3 += 1; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R0 = R3; - R3 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R1 = R3; - R3 += -1; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x80000000; - CHECKREG r1, 0x7FFFFFFF; - CHECKREG r3, 0x7FFFFFFE; - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R3 - R3 = 0; - ASTAT = R3; - imm32 r3, 0x80000000; - R3 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R0 = R3; - R3 += 1; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R1 = R3; - R3 += 1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x7FFFFFFF; - CHECKREG r1, 0x80000000; - CHECKREG r3, 0x80000001; - CHECKREG r5, (_VS|_AN); - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - -// AZ for R4 - imm32 r4, 0x00000000; - ASTAT = R4; - R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R4 += 1; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R4 += -1; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R1 = R4; - R4 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R3 = ASTAT; - R4 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R2 = ASTAT; - CHECKREG r1, 0x00000000; - CHECKREG r2, (_AC0|_AC0_COPY|_AZ); - CHECKREG r3, (_AN); - CHECKREG r4, 0x00000000; - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R4 - imm32 r4, 0xffffffff; - R4 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R1 = R4; - R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R4 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r1, 0x00000000; - CHECKREG r4, 0xFFFFFFFF; - CHECKREG r5, (_AN); - CHECKREG r6, (_AZ); - CHECKREG r7, (_AC0|_AC0_COPY|_AZ); - -// AC, AV0 for R4 - imm32 r4, 0x7fffffff; - R4 += 1; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R1 = R4; - R4 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R2 = R4; - R4 += -1; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r1, 0x80000000; - CHECKREG r2, 0x7FFFFFFF; - CHECKREG r4, 0x7FFFFFFE; - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R4 - R4 = 0; - ASTAT = R4; - imm32 r4, 0x80000000; - R4 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R1 = R4; - R4 += 1; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R2 = R4; - R4 += 1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r1, 0x7FFFFFFF; - CHECKREG r2, 0x80000000; - CHECKREG r4, 0x80000001; - CHECKREG r5, (_VS|_AN); - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - -// AZ for R5 - imm32 r5, 0x00000000; - ASTAT = R5; - R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R5 += 1; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R5 += -1; // az = 1 an = 0 ac = 1 av0 = 0 - R2 = ASTAT; - R0 = R5; - R5 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R5 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R3 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r2, (_AC0|_AC0_COPY|_AZ); - CHECKREG r3, (_AC0|_AC0_COPY|_AZ); - CHECKREG r4, (_AN); - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R5 - imm32 r5, 0xffffffff; - R5 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R0 = R5; - R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R5 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r4, (_AN); - CHECKREG r5, 0xFFFFFFFF; - CHECKREG r6, (_AZ); - CHECKREG r7, (_AC0|_AC0_COPY|_AZ); - -// AC, AV0 for R5 - imm32 r5, 0x7fffffff; - R5 += 1; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R0 = R5; - R5 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R2 = R5; - R5 += -1; // az = 0 an = 0 ac = 1 av0 = 0 - R4 = ASTAT; - CHECKREG r0, 0x80000000; - CHECKREG r2, 0x7FFFFFFF; - CHECKREG r4, (_VS|_AC0|_AC0_COPY); - CHECKREG r5, 0x7FFFFFFE; - CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R5 - R5 = 0; - ASTAT = R5; - imm32 r5, 0x80000000; - R5 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R0 = R5; - R5 += 1; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R2 = R5; - R5 += 1; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - CHECKREG r0, 0x7FFFFFFF; - CHECKREG r2, 0x80000000; - CHECKREG r4, (_VS|_AN); - CHECKREG r5, 0x80000001; - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - -// AZ for R6 - imm32 r6, 0x00000000; - ASTAT = R6; - R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R6 += 1; // az = 0 an = 0 ac = 0 av0 = 0 - R0 = ASTAT; - R6 += -1; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R1 = R6; - R6 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R6 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R3 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r3, (_AC0|_AC0_COPY|_AZ); - CHECKREG r4, (_AN); - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R6 - imm32 r6, 0xffffffff; - R6 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R1 = R6; - R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R4 = ASTAT; - R6 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r1, 0x00000000; - CHECKREG r4, (_AZ); - CHECKREG r5, (_AN); - CHECKREG r6, 0xFFFFFFFF; - CHECKREG r7, (_AC0|_AC0_COPY|_AZ); - -// AC, AV0 for R6 - R6 = 0; - ASTAT = R6; - imm32 r6, 0x7fffffff; - R6 += 1; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R0 = R6; - R6 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R4 = ASTAT; - R1 = R6; - R6 += -1; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x80000000; - CHECKREG r1, 0x7FFFFFFF; - CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, 0x7FFFFFFE; - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R6 - R6 = 0; - ASTAT = R6; - imm32 r6, 0x80000000; - R6 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R0 = R6; - R6 += 1; // az = 1 an = 1 ac = 0 av0 = 1 - R4 = ASTAT; - R1 = R6; - R6 += 1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x7FFFFFFF; - CHECKREG r1, 0x80000000; - CHECKREG r4, (_VS|_V|_V_COPY|_AN); - CHECKREG r5, (_VS|_AN); - CHECKREG r6, 0x80000001; - CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - -// AZ for R7 - imm32 r7, 0x00000000; - ASTAT = R7; - R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R1 = ASTAT; - R7 += 1; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R7 += -1; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R0 = R7; - R7 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R7 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R2 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r1, (_AZ); - CHECKREG r2, (_AC0|_AC0_COPY|_AZ); - CHECKREG r4, (_AN); - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000000; - -// AN, AC for R7 - imm32 r7, 0xffffffff; - R7 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R4 = ASTAT; - R0 = R7; - R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R7 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r4, (_AC0|_AC0_COPY|_AZ); - CHECKREG r5, (_AN); - CHECKREG r6, (_AZ); - CHECKREG r7, 0xFFFFFFFF; - -// AC, AV0 for R7 - R7 = 0; - ASTAT = R7; - imm32 r7, 0x7fffffff; - R7 += 1; // az = 0 an = 1 ac = 0 av0 = 1 - R4 = ASTAT; - R0 = R7; - R7 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R1 = R7; - R7 += -1; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x80000000; - CHECKREG r1, 0x7FFFFFFF; - CHECKREG r4, (_VS|_V|_V_COPY|_AN); - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r7, 0x7FFFFFFE; - -// AZ, AN, AC, AV0 for R7 - R7 = 0; - ASTAT = R7; - imm32 r7, 0x80000000; - R7 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R4 = ASTAT; - R0 = R7; - R7 += 1; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R1 = R7; - R7 += 1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x7FFFFFFF; - CHECKREG r1, 0x80000000; - CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r5, (_VS|_AN); - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, 0x80000001; - - pass diff --git a/sim/testsuite/sim/bfin/c_compi2opd_flags_2.S b/sim/testsuite/sim/bfin/c_compi2opd_flags_2.S deleted file mode 100644 index 83bf1b0..0000000 --- a/sim/testsuite/sim/bfin/c_compi2opd_flags_2.S +++ /dev/null @@ -1,600 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_compi2opd_flags_2/c_compi2opd_flags_2.dsp -// Spec Reference: compi2opd dregs += imm7 flags_2 (az, an, ac, av0) -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - INIT_R_REGS 0; - - ASTAT = R0; // initialize astat - -// AZ for R0 - imm32 r0, 0x00000000; - R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R0 += 1; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R0 += -1; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R1 = R0; - R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R3 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r3, (_AC0|_AC0_COPY|_AZ); - CHECKREG r4, (_AN); - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R0 - imm32 r0, 0xffffffff; - R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R1 = R0; - R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0xFFFFFFFF; - CHECKREG r1, 0x00000000; - CHECKREG r5, (_AN); - CHECKREG r6, (_AZ); - CHECKREG r7, (_AC0|_AC0_COPY|_AZ); - -// AC, AV0 for R0 - imm32 r0, 0x7fffffff; - R0 += 1; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R1 = R0; - R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R2 = R0; - R0 += -1; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x7FFFFFFE; - CHECKREG r1, 0x80000000; - CHECKREG r2, 0x7FFFFFFF; - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, (_AC0|_AC0_COPY|_V|_V_COPY|_VS); - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R0 - R0 = 0; - ASTAT = R0; - imm32 r0, 0x80000000; - R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R1 = R0; - R0 += 1; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R2 = R0; - R0 += 1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x80000001; - CHECKREG r1, 0x7FFFFFFF; - CHECKREG r2, 0x80000000; - CHECKREG r5, (_VS|_AN); - CHECKREG r6, (_VS|_V_COPY|_V|_AN); - CHECKREG r7, (_VS|_V_COPY|_V|_AC0|_AC0_COPY); - -// AZ for R0 - imm32 r1, 0x00000000; - ASTAT = R1; - R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R1 += 1; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R1 += -1; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R0 = R1; - R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R3 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r3, (_AC0|_AC0_COPY|_AZ); - CHECKREG r4, (_AN); - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R1 - r1 = 0; - ASTAT = r1; - imm32 r1, 0xffffffff; - R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R0 = R1; - R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0xFFFFFFFF; - CHECKREG r5, (_AN); - CHECKREG r6, (_AZ); - CHECKREG r7, (_AC0|_AC0_COPY|_AZ); - -// AC, AV0 for R1 - imm32 r1, 0x7fffffff; - R1 += 1; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R0 = R1; - R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R2 = R1; - R1 += -1; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x80000000; - CHECKREG r1, 0x7FFFFFFE; - CHECKREG r2, 0x7FFFFFFF; - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R1 - R1 = 0; - ASTAT = R1; - imm32 r1, 0x80000000; - R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R0 = R1; - R1 += 1; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R2 = R1; - R1 += 1; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x7FFFFFFF; - CHECKREG r1, 0x80000001; - CHECKREG r2, 0x80000000; - CHECKREG r5, (_VS|_AN); - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - -// AZ for R2 - imm32 r2, 0x00000000; - ASTAT = R2; - R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R2 += 2; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R2 += -2; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R1 = R2; - R2 += -2; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R2 += 2; // az = 1 an = 0 ac = 1 av0 = 0 - R3 = ASTAT; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, (_AC0|_AC0_COPY|_AZ); - CHECKREG r4, (_AN); - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R2 - R2 = 0; - ASTAT = R2; - imm32 r2, 0xffffffff; - R2 += 2; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R1 = R2; - R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R2 += -2; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r2, 0xFFFFFFFF; - CHECKREG r1, (_AZ); - CHECKREG r5, (_AN); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AC0|_AC0_COPY); - -// AC, AV0 for R2 - imm32 r2, 0x7fffffff; - R2 += 2; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R0 = R2; - R2 += -2; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R1 = R2; - R2 += -2; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x80000001; - CHECKREG r1, 0x7FFFFFFF; - CHECKREG r2, 0x7FFFFFFD; - CHECKREG r5, (_AC0|_AC0_COPY|_VS); - CHECKREG r6, (_AC0|_AC0_COPY|_VS|_V|_V_COPY); - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R2 - R2 = 0; - ASTAT = R2; - imm32 r2, 0x80000000; - R2 += -2; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R0 = R2; - R2 += 2; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R1 = R2; - R2 += 2; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x7FFFFFFE; - CHECKREG r1, 0x80000000; - CHECKREG r2, 0x80000002; - CHECKREG r5, (_VS|_AN); - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, (_AC0|_AC0_COPY|_VS|_V|_V_COPY); - -// AZ for R3 - imm32 r3, 0x00000000; - ASTAT = R3; - R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R3 += 3; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R3 += -3; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R0 = R3; - R3 += -3; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R3 += 3; // az = 1 an = 0 ac = 1 av0 = 0 - R2 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r2, (_AC0|_AC0_COPY|_AZ); - CHECKREG r3, 0x00000000; - CHECKREG r4, (_AN); - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R3 - imm32 r3, 0xffffffff; - R3 += 3; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R0 = R3; - R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R3 += -3; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x00000002; - CHECKREG r3, 0xFFFFFFFF; - CHECKREG r5, (_AN); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AC0|_AC0_COPY); - -// AC, AV0 for R3 - imm32 r3, 0x7fffffff; - R3 += 3; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R0 = R3; - R3 += -3; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R1 = R3; - R3 += -3; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x80000002; - CHECKREG r1, 0x7FFFFFFF; - CHECKREG r3, 0x7FFFFFFC; - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, (_AC0|_AC0_COPY|_VS|_V|_V_COPY); - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R3 - R3 = 0; - ASTAT = R3; - imm32 r3, 0x80000000; - R3 += -3; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R0 = R3; - R3 += 3; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R1 = R3; - R3 += 3; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x7FFFFFFD; - CHECKREG r1, 0x80000000; - CHECKREG r3, 0x80000003; - CHECKREG r5, (_VS|_AN); - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - -// AZ for R4 - imm32 r4, 0x00000000; - ASTAT = R4; - R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R4 += 4; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R4 += -4; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R1 = R4; - R4 += -4; // az = 0 an = 1 ac = 0 av0 = 0 - R3 = ASTAT; - R4 += 4; // az = 1 an = 0 ac = 1 av0 = 0 - R2 = ASTAT; - CHECKREG r1, 0x00000000; - CHECKREG r2, (_AC0|_AC0_COPY|_AZ); - CHECKREG r3, (_AN); - CHECKREG r4, 0x00000000; - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R4 - imm32 r4, 0xffffffff; - R4 += 4; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R1 = R4; - R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R4 += -4; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r1, 0x00000003; - CHECKREG r4, 0xFFFFFFFF; - CHECKREG r5, (_AN); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AC0|_AC0_COPY); - -// AC, AV0 for R4 - imm32 r4, 0x7fffffff; - R4 += 4; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R1 = R4; - R4 += -4; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R2 = R4; - R4 += -4; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r1, 0x80000003; - CHECKREG r2, 0x7FFFFFFF; - CHECKREG r4, 0x7FFFFFFB; - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R4 - R4 = 0; - ASTAT = R4; - imm32 r4, 0x80000000; - R4 += -4; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R1 = R4; - R4 += 4; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R2 = R4; - R4 += 4; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r1, 0x7FFFFFFC; - CHECKREG r2, 0x80000000; - CHECKREG r4, 0x80000004; - CHECKREG r5, (_VS|_AN); - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - -// AZ for R5 - imm32 r5, 0x00000000; - ASTAT = R5; - R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R5 += 5; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R5 += -5; // az = 1 an = 0 ac = 1 av0 = 0 - R2 = ASTAT; - R0 = R5; - R5 += -5; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R5 += 5; // az = 1 an = 0 ac = 1 av0 = 0 - R3 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r2, (_AC0|_AC0_COPY|_AZ); - CHECKREG r3, (_AC0|_AC0_COPY|_AZ); - CHECKREG r4, (_AN); - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R5 - imm32 r5, 0xffffffff; - R5 += 5; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R0 = R5; - R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R5 += -5; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - CHECKREG r0, 0x00000004; - CHECKREG r4, (_AN); - CHECKREG r5, 0xFFFFFFFF; - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AC0|_AC0_COPY); - -// AC, AV0 for R5 - imm32 r5, 0x7fffffff; - R5 += 5; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R0 = R5; - R5 += -5; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R2 = R5; - R5 += -5; // az = 0 an = 0 ac = 1 av0 = 0 - R4 = ASTAT; - CHECKREG r0, 0x80000004; - CHECKREG r2, 0x7FFFFFFF; - CHECKREG r4, (_VS|_AC0|_AC0_COPY); - CHECKREG r5, 0x7FFFFFFA; - CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R5 - R5 = 0; - ASTAT = R5; - imm32 r5, 0x80000000; - R5 += -5; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R0 = R5; - R5 += 5; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R2 = R5; - R5 += 5; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - CHECKREG r0, 0x7FFFFFFB; - CHECKREG r2, 0x80000000; - CHECKREG r4, (_VS|_AN); - CHECKREG r5, 0x80000005; - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - -// AZ for R6 - imm32 r6, 0x00000000; - ASTAT = R6; - R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R7 = ASTAT; - R6 += 6; // az = 0 an = 0 ac = 0 av0 = 0 - R0 = ASTAT; - R6 += -6; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R1 = R6; - R6 += -6; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R6 += 6; // az = 1 an = 0 ac = 1 av0 = 0 - R3 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r3, (_AC0|_AC0_COPY|_AZ); - CHECKREG r4, (_AN); - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, (_AZ); - -// AN, AC for R6 - imm32 r6, 0xffffffff; - R6 += 6; // az = 1 an = 0 ac = 1 av0 = 0 - R7 = ASTAT; - R1 = R6; - R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R4 = ASTAT; - R6 += -6; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r1, 0x00000005; - CHECKREG r4, 0x00000000; - CHECKREG r5, (_AN); - CHECKREG r6, 0xFFFFFFFF; - CHECKREG r7, (_AC0|_AC0_COPY); - -// AC, AV0 for R6 - imm32 r6, 0x7fffffff; - R6 += 6; // az = 0 an = 1 ac = 0 av0 = 1 - R7 = ASTAT; - R0 = R6; - R6 += -6; // az = 0 an = 0 ac = 1 av0 = 1 - R4 = ASTAT; - R1 = R6; - R6 += -6; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x80000005; - CHECKREG r1, 0x7FFFFFFF; - CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, 0x7FFFFFF9; - CHECKREG r7, (_VS|_V|_V_COPY|_AN); - -// AZ, AN, AC, AV0 for R6 - R6 = 0; - ASTAT = R6; - imm32 r6, 0x80000000; - R6 += -6; // az = 0 an = 0 ac = 1 av0 = 1 - R7 = ASTAT; - R0 = R6; - R6 += 6; // az = 1 an = 1 ac = 0 av0 = 1 - R4 = ASTAT; - R1 = R6; - R6 += 6; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x7FFFFFFA; - CHECKREG r1, 0x80000000; - CHECKREG r4, (_VS|_V|_V_COPY|_AN); - CHECKREG r5, (_VS|_AN); - CHECKREG r6, 0x80000006; - CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - -// AZ for R7 - imm32 r7, 0x00000000; - ASTAT = R7; - R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R1 = ASTAT; - R7 += 7; // az = 0 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R7 += -7; // az = 1 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - R0 = R7; - R7 += -7; // az = 0 an = 1 ac = 0 av0 = 0 - R4 = ASTAT; - R7 += 7; // az = 1 an = 0 ac = 1 av0 = 0 - R2 = ASTAT; - CHECKREG r0, 0x00000000; - CHECKREG r1, (_AZ); - CHECKREG r2, (_AC0|_AC0_COPY|_AZ); - CHECKREG r4, (_AN); - CHECKREG r5, (_AC0|_AC0_COPY|_AZ); - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000000; - -// AN, AC for R7 - imm32 r7, 0xffffffff; - R7 += 7; // az = 1 an = 0 ac = 1 av0 = 0 - R4 = ASTAT; - R0 = R7; - R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 - R6 = ASTAT; - R7 += -7; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x00000006; - CHECKREG r4, (_AC0|_AC0_COPY); - CHECKREG r5, (_AN); - CHECKREG r6, 0x00000000; - CHECKREG r7, 0xFFFFFFFF; - -// AC, AV0 for R7 - imm32 r7, 0x7fffffff; - R7 += 7; // az = 0 an = 1 ac = 0 av0 = 1 - R4 = ASTAT; - R0 = R7; - R7 += -7; // az = 0 an = 0 ac = 1 av0 = 1 - R6 = ASTAT; - R1 = R7; - R7 += -7; // az = 0 an = 0 ac = 1 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x80000006; - CHECKREG r1, 0x7FFFFFFF; - CHECKREG r4, (_VS|_V|_V_COPY|_AN); - CHECKREG r5, (_VS|_AC0|_AC0_COPY); - CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r7, 0x7FFFFFF8; - -// AZ, AN, AC, AV0 for R7 - R7 = 0; - ASTAT = R7; - imm32 r7, 0x80000000; - R7 += -7; // az = 0 an = 0 ac = 1 av0 = 1 - R4 = ASTAT; - R0 = R7; - R7 += 7; // az = 1 an = 1 ac = 0 av0 = 1 - R6 = ASTAT; - R1 = R7; - R7 += 7; // az = 0 an = 1 ac = 0 av0 = 0 - R5 = ASTAT; - CHECKREG r0, 0x7FFFFFF9; - CHECKREG r1, 0x80000000; - CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); - CHECKREG r5, (_VS|_AN); - CHECKREG r6, (_VS|_V|_V_COPY|_AN); - CHECKREG r7, 0x80000007; - - pass diff --git a/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_n.s b/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_n.s deleted file mode 100644 index b63cb86..0000000 --- a/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_n.s +++ /dev/null @@ -1,149 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_n/c_compi2opp_pr_add_i7_n.dsp -// Spec Reference: compi2opp pregs += imm7 negative -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - INIT_P_REGS 0; - - imm32 sp, 0x00000000; - imm32 fp, 0x00000000; - - P1 += -1; - P2 += -2; - P3 += -3; - P4 += -4; - P5 += -5; - SP += -6; - FP += -7; - CHECKREG p1, 0xFFFFFFFF; - CHECKREG p2, 0xFFFFFFFE; - CHECKREG p3, 0xFFFFFFFD; - CHECKREG p4, 0xFFFFFFFC; - CHECKREG p5, 0xFFFFFFFB; - CHECKREG sp, 0xFFFFFFFA; - CHECKREG fp, 0xFFFFFFF9; - - P1 += -9; - P2 += -10; - P3 += -11; - P4 += -12; - P5 += -13; - SP += -14; - FP += -15; - CHECKREG p1, 0xFFFFFFF6; - CHECKREG p2, 0xFFFFFFF4; - CHECKREG p3, 0xFFFFFFF2; - CHECKREG p4, 0xFFFFFFF0; - CHECKREG p5, 0xFFFFFFEE; - CHECKREG sp, 0xFFFFFFEC; - CHECKREG fp, 0xFFFFFFEA; - - P1 += -17; - P2 += -18; - P3 += -19; - P4 += -20; - P5 += -21; - SP += -22; - FP += -23; - CHECKREG p1, 0xFFFFFFE5; - CHECKREG p2, 0xFFFFFFE2; - CHECKREG p3, 0xFFFFFFDF; - CHECKREG p4, 0xFFFFFFDC; - CHECKREG p5, 0xFFFFFFD9; - CHECKREG sp, 0xFFFFFFD6; - CHECKREG fp, 0xFFFFFFD3; - - P1 += -25; - P2 += -26; - P3 += -27; - P4 += -28; - P5 += -29; - SP += -30; - FP += -31; - CHECKREG p1, 0xFFFFFFCC; - CHECKREG p2, 0xFFFFFFC8; - CHECKREG p3, 0xFFFFFFC4; - CHECKREG p4, 0xFFFFFFC0; - CHECKREG p5, 0xFFFFFFBC; - CHECKREG sp, 0xFFFFFFB8; - CHECKREG fp, 0xFFFFFFB4; - - P1 += -33; - P2 += -34; - P3 += -35; - P4 += -36; - P5 += -37; - SP += -38; - FP += -39; - CHECKREG p1, 0xFFFFFFAB; - CHECKREG p2, 0xFFFFFFA6; - CHECKREG p3, 0xFFFFFFA1; - CHECKREG p4, 0xFFFFFF9C; - CHECKREG p5, 0xFFFFFF97; - CHECKREG sp, 0xFFFFFF92; - CHECKREG fp, 0xFFFFFF8D; - - P1 += -41; - P2 += -42; - P3 += -43; - P4 += -44; - P5 += -45; - SP += -46; - FP += -47; - CHECKREG p1, 0xFFFFFF82; - CHECKREG p2, 0xFFFFFF7C; - CHECKREG p3, 0xFFFFFF76; - CHECKREG p4, 0xFFFFFF70; - CHECKREG p5, 0xFFFFFF6A; - CHECKREG sp, 0xFFFFFF64; - CHECKREG fp, 0xFFFFFF5E; - - P1 += -49; - P2 += -50; - P3 += -51; - P4 += -52; - P5 += -53; - SP += -54; - FP += -55; - CHECKREG p1, 0xFFFFFF51; - CHECKREG p2, 0xFFFFFF4A; - CHECKREG p3, 0xFFFFFF43; - CHECKREG p4, 0xFFFFFF3C; - CHECKREG p5, 0xFFFFFF35; - CHECKREG sp, 0xFFFFFF2E; - CHECKREG fp, 0xFFFFFF27; - - P1 += -57; - P2 += -58; - P3 += -59; - P4 += -60; - P5 += -61; - SP += -62; - FP += -63; - CHECKREG p1, 0xFFFFFF18; - CHECKREG p2, 0xFFFFFF10; - CHECKREG p3, 0xFFFFFF08; - CHECKREG p4, 0xFFFFFF00; - CHECKREG p5, 0xFFFFFEF8; - CHECKREG sp, 0xFFFFFEF0; - CHECKREG fp, 0xFFFFFEE8; - - P1 += -64; - P2 += -64; - P3 += -64; - P4 += -64; - P5 += -64; - SP += -64; - FP += -64; - CHECKREG p1, 0xFFFFFED8; - CHECKREG p2, 0xFFFFFED0; - CHECKREG p3, 0xFFFFFEC8; - CHECKREG p4, 0xFFFFFEC0; - CHECKREG p5, 0xFFFFFEB8; - CHECKREG sp, 0xFFFFFEB0; - CHECKREG fp, 0xFFFFFEA8; - - pass diff --git a/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_p.s b/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_p.s deleted file mode 100644 index 75336a8..0000000 --- a/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_p.s +++ /dev/null @@ -1,116 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_p/c_compi2opp_pr_add_i7_p.dsp -// Spec Reference: compi2opp pregs += imm7 positive -# mach: bfin - -.include "testutils.inc" - start - - INIT_P_REGS 0; - - imm32 fp, 0x00000000; - - P1 += 1; - P2 += 2; - P3 += 3; - P4 += 4; - P5 += 5; - FP += 7; - CHECKREG p1, 0x00000001; - CHECKREG p2, 0x00000002; - CHECKREG p3, 0x00000003; - CHECKREG p4, 0x00000004; - CHECKREG p5, 0x00000005; - CHECKREG fp, 0x00000007; - - P1 += 9; - P2 += 10; - P3 += 11; - P4 += 12; - P5 += 13; - FP += 15; - CHECKREG p1, 0x0000000A; - CHECKREG p2, 0x0000000C; - CHECKREG p3, 0x0000000E; - CHECKREG p4, 0x00000010; - CHECKREG p5, 0x00000012; - CHECKREG fp, 0x00000016; - - P1 += 17; - P2 += 18; - P3 += 19; - P4 += 20; - P5 += 21; - FP += 23; - CHECKREG p1, 0x0000001B; - CHECKREG p2, 0x0000001E; - CHECKREG p3, 0x00000021; - CHECKREG p4, 0x00000024; - CHECKREG p5, 0x00000027; - CHECKREG fp, 0x0000002D; - - P1 += 25; - P2 += 26; - P3 += 27; - P4 += 28; - P5 += 29; - FP += 31; - CHECKREG p1, 0x00000034; - CHECKREG p2, 0x00000038; - CHECKREG p3, 0x0000003C; - CHECKREG p4, 0x00000040; - CHECKREG p5, 0x00000044; - CHECKREG fp, 0x0000004C; - - P1 += 33; - P2 += 34; - P3 += 35; - P4 += 36; - P5 += 37; - FP += 39; - CHECKREG p1, 0x00000055; - CHECKREG p2, 0x0000005A; - CHECKREG p3, 0x0000005F; - CHECKREG p4, 0x00000064; - CHECKREG p5, 0x00000069; - CHECKREG fp, 0x00000073; - - P1 += 41; - P2 += 42; - P3 += 43; - P4 += 44; - P5 += 45; - FP += 47; - CHECKREG p1, 0x0000007E; - CHECKREG p2, 0x00000084; - CHECKREG p3, 0x0000008A; - CHECKREG p4, 0x00000090; - CHECKREG p5, 0x00000096; - CHECKREG fp, 0x000000A2; - - P1 += 49; - P2 += 50; - P3 += 51; - P4 += 52; - P5 += 53; - FP += 55; - CHECKREG p1, 0x000000AF; - CHECKREG p2, 0x000000B6; - CHECKREG p3, 0x000000BD; - CHECKREG p4, 0x000000C4; - CHECKREG p5, 0x000000CB; - CHECKREG fp, 0x000000D9; - - P1 += 57; - P2 += 58; - P3 += 59; - P4 += 60; - P5 += 61; - FP += 63; - CHECKREG p1, 0x000000E8; - CHECKREG p2, 0x000000F0; - CHECKREG p3, 0x000000F8; - CHECKREG p4, 0x00000100; - CHECKREG p5, 0x00000108; - CHECKREG fp, 0x00000118; - - pass diff --git a/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_n.s b/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_n.s deleted file mode 100644 index efeeb69..0000000 --- a/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_n.s +++ /dev/null @@ -1,161 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_n/c_compi2opp_pr_eq_i7_n.dsp -// Spec Reference: compi2opp pregs = imm7 negative -# mach: bfin - -.include "testutils.inc" - start - - R0 = -0; - P1 = -1; - P2 = -2; - P3 = -3; - P4 = -4; - P5 = -5; - SP = -6; - FP = -7; - CHECKREG r0, -0; - CHECKREG p1, -1; - CHECKREG p2, -2; - CHECKREG p3, -3; - CHECKREG p4, -4; - CHECKREG p5, -5; - CHECKREG sp, -6; - CHECKREG fp, -7; - - R0 = -8; - P1 = -9; - P2 = -10; - P3 = -11; - P4 = -12; - P5 = -13; - SP = -14; - FP = -15; - CHECKREG r0, -8; - CHECKREG p1, -9; - CHECKREG p2, -10; - CHECKREG p3, -11; - CHECKREG p4, -12; - CHECKREG p5, -13; - CHECKREG sp, -14; - CHECKREG fp, -15; - - R0 = -16; - P1 = -17; - P2 = -18; - P3 = -19; - P4 = -20; - P5 = -21; - SP = -22; - FP = -23; - CHECKREG r0, -16; - CHECKREG p1, -17; - CHECKREG p2, -18; - CHECKREG p3, -19; - CHECKREG p4, -20; - CHECKREG p5, -21; - CHECKREG sp, -22; - CHECKREG fp, -23; - - R0 = -24; - P1 = -25; - P2 = -26; - P3 = -27; - P4 = -28; - P5 = -29; - SP = -30; - FP = -31; - CHECKREG r0, -24; - CHECKREG p1, -25; - CHECKREG p2, -26; - CHECKREG p3, -27; - CHECKREG p4, -28; - CHECKREG p5, -29; - CHECKREG sp, -30; - CHECKREG fp, -31; - - R0 = -32; - P1 = -33; - P2 = -34; - P3 = -35; - P4 = -36; - P5 = -37; - SP = -38; - FP = -39; - CHECKREG r0, -32; - CHECKREG p1, -33; - CHECKREG p2, -34; - CHECKREG p3, -35; - CHECKREG p4, -36; - CHECKREG p5, -37; - CHECKREG sp, -38; - CHECKREG fp, -39; - - R0 = -40; - P1 = -41; - P2 = -42; - P3 = -43; - P4 = -44; - P5 = -45; - SP = -46; - FP = -47; - CHECKREG r0, -40; - CHECKREG p1, -41; - CHECKREG p2, -42; - CHECKREG p3, -43; - CHECKREG p4, -44; - CHECKREG p5, -45; - CHECKREG sp, -46; - CHECKREG fp, -47; - - R0 = -48; - P1 = -49; - P2 = -50; - P3 = -51; - P4 = -52; - P5 = -53; - SP = -54; - FP = -55; - CHECKREG r0, -48; - CHECKREG p1, -49; - CHECKREG p2, -50; - CHECKREG p3, -51; - CHECKREG p4, -52; - CHECKREG p5, -53; - CHECKREG sp, -54; - CHECKREG fp, -55; - - R0 = -56; - P1 = -57; - P2 = -58; - P3 = -59; - P4 = -60; - P5 = -61; - SP = -62; - FP = -63; - CHECKREG r0, -56; - CHECKREG p1, -57; - CHECKREG p2, -58; - CHECKREG p3, -59; - CHECKREG p4, -60; - CHECKREG p5, -61; - CHECKREG sp, -62; - CHECKREG fp, -63; - - R0 = -64; - P1 = -64; - P2 = -64; - P3 = -64; - P4 = -64; - P5 = -64; - SP = -64; - FP = -64; - CHECKREG r0, -64; - CHECKREG p1, -64; - CHECKREG p2, -64; - CHECKREG p3, -64; - CHECKREG p4, -64; - CHECKREG p5, -64; - CHECKREG sp, -64; - CHECKREG fp, -64; - - pass diff --git a/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_p.s b/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_p.s deleted file mode 100644 index 75433bc..0000000 --- a/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_p.s +++ /dev/null @@ -1,131 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_p/c_compi2opp_pr_eq_i7_p.dsp -// Spec Reference: compi2opd pregs = imm7 positive -# mach: bfin - -.include "testutils.inc" - start - -//R0 = 0; - P1 = 1; - P2 = 2; - P3 = 3; - P4 = 4; - P5 = 5; - SP = 6; - FP = 7; - CHECKREG p1, 1; - CHECKREG p2, 2; - CHECKREG p3, 3; - CHECKREG p4, 4; - CHECKREG p5, 5; - CHECKREG sp, 6; - CHECKREG fp, 7; - - P1 = 9; - P2 = 10; - P3 = 11; - P4 = 12; - P5 = 13; - SP = 14; - FP = 15; - CHECKREG p1, 9; - CHECKREG p2, 10; - CHECKREG p3, 11; - CHECKREG p4, 12; - CHECKREG p5, 13; - CHECKREG sp, 14; - CHECKREG fp, 15; - - P1 = 17; - P2 = 18; - P3 = 19; - P4 = 20; - P5 = 21; - SP = 22; - FP = 23; - CHECKREG p1, 17; - CHECKREG p2, 18; - CHECKREG p3, 19; - CHECKREG p4, 20; - CHECKREG p5, 21; - CHECKREG sp, 22; - CHECKREG fp, 23; - - P1 = 25; - P2 = 26; - P3 = 27; - P4 = 28; - P5 = 29; - SP = 30; - FP = 31; - CHECKREG p1, 25; - CHECKREG p2, 26; - CHECKREG p3, 27; - CHECKREG p4, 28; - CHECKREG p5, 29; - CHECKREG sp, 30; - CHECKREG fp, 31; - - R0 = 32; - P1 = 33; - P2 = 34; - P3 = 35; - P4 = 36; - P5 = 37; - SP = 38; - FP = 39; - CHECKREG r0, 32; - CHECKREG p1, 33; - CHECKREG p2, 34; - CHECKREG p3, 35; - CHECKREG p4, 36; - CHECKREG p5, 37; - CHECKREG sp, 38; - CHECKREG fp, 39; - - P1 = 41; - P2 = 42; - P3 = 43; - P4 = 44; - P5 = 45; - SP = 46; - FP = 47; - CHECKREG p1, 41; - CHECKREG p2, 42; - CHECKREG p3, 43; - CHECKREG p4, 44; - CHECKREG p5, 45; - CHECKREG sp, 46; - CHECKREG fp, 47; - - P1 = 49; - P2 = 50; - P3 = 51; - P4 = 52; - P5 = 53; - SP = 54; - FP = 55; - CHECKREG p1, 49; - CHECKREG p2, 50; - CHECKREG p3, 51; - CHECKREG p4, 52; - CHECKREG p5, 53; - CHECKREG sp, 54; - CHECKREG fp, 55; - - P1 = 57; - P2 = 58; - P3 = 59; - P4 = 60; - P5 = 61; - SP = 62; - FP = 63; - CHECKREG p1, 57; - CHECKREG p2, 58; - CHECKREG p3, 59; - CHECKREG p4, 60; - CHECKREG p5, 61; - CHECKREG sp, 62; - CHECKREG fp, 63; - - pass diff --git a/sim/testsuite/sim/bfin/c_dagmodik_lnz_imgebl.s b/sim/testsuite/sim/bfin/c_dagmodik_lnz_imgebl.s deleted file mode 100644 index cea97ad..0000000 --- a/sim/testsuite/sim/bfin/c_dagmodik_lnz_imgebl.s +++ /dev/null @@ -1,290 +0,0 @@ -//Original:/testcases/core/c_dagmodik_lnz_imgebl/c_dagmodik_lnz_imgebl.dsp -// Spec Reference: dagmodik l not zero & i+m >= b+l -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -imm32 i0, 0x00001000; -imm32 i1, 0x00001100; -imm32 i2, 0x00001010; -imm32 i3, 0x00001001; - -imm32 b0, 0x00001000; -imm32 b1, 0x00001000; -imm32 b2, 0x00001000; -imm32 b3, 0x00001000; - -imm32 l0, 0x00000001; -imm32 l1, 0x00000002; -imm32 l2, 0x00000003; -imm32 l3, 0x00000004; - -imm32 m0, 0x00000015; -imm32 m1, 0x00000016; -imm32 m2, 0x00000017; -imm32 m3, 0x00000018; - - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001001; -CHECKREG r1, 0x00001100; -CHECKREG r2, 0x0000100F; -CHECKREG r3, 0x00001003; -CHECKREG r4, 0x00001002; -CHECKREG r5, 0x00001100; -CHECKREG r6, 0x0000100E; -CHECKREG r7, 0x00001001; - - - I0 -= 2; - I1 -= 2; - I2 -= 2; - I3 -= 2; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 -= 2; - I1 -= 2; - I2 -= 2; - I3 -= 2; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001000; -CHECKREG r1, 0x000010FE; -CHECKREG r2, 0x0000100C; -CHECKREG r3, 0x00001003; -CHECKREG r4, 0x00000FFF; -CHECKREG r5, 0x000010FC; -CHECKREG r6, 0x0000100A; -CHECKREG r7, 0x00001001; - - I0 += 4; - I1 += 4; - I2 += 4; - I3 += 4; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += 4; - I1 += 4; - I2 += 4; - I3 += 4; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001002; -CHECKREG r1, 0x000010FE; -CHECKREG r2, 0x0000100B; -CHECKREG r3, 0x00001001; -CHECKREG r4, 0x00001005; -CHECKREG r5, 0x00001100; -CHECKREG r6, 0x0000100C; -CHECKREG r7, 0x00001001; - - I0 -= 4; - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG r0, 0x00000FFE; -CHECKREG r1, 0x000010F8; -CHECKREG r2, 0x00001004; -CHECKREG r3, 0x00001001; -CHECKREG r4, 0x00001005; -CHECKREG r5, 0x00001100; -CHECKREG r6, 0x0000100C; -CHECKREG r7, 0x00001001; - - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00000FFE; -CHECKREG r1, 0x000010F8; -CHECKREG r2, 0x00001004; -CHECKREG r3, 0x00001001; -CHECKREG r4, 0x00000FF8; -CHECKREG r5, 0x000010F0; -CHECKREG r6, 0x00000FFF; -CHECKREG r7, 0x00001001; - -// i+m = b+l -imm32 i0, 0x00001000; -imm32 i1, 0x00001100; -imm32 i2, 0x00001010; -imm32 i3, 0x00001001; - -imm32 b0, 0x00001000; -imm32 b1, 0x00001100; -imm32 b2, 0x00001010; -imm32 b3, 0x00001001; - -imm32 l0, 0x00000015; -imm32 l1, 0x00000016; -imm32 l2, 0x00000017; -imm32 l3, 0x00000018; - -imm32 m0, 0x00000015; -imm32 m1, 0x00000016; -imm32 m2, 0x00000017; -imm32 m3, 0x00000018; - - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001002; -CHECKREG r1, 0x00001102; -CHECKREG r2, 0x00001012; -CHECKREG r3, 0x00001003; -CHECKREG r4, 0x00001004; -CHECKREG r5, 0x00001104; -CHECKREG r6, 0x00001014; -CHECKREG r7, 0x00001005; - - - I0 -= 2; - I1 -= 2; - I2 -= 2; - I3 -= 2; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 -= 2; - I1 -= 2; - I2 -= 2; - I3 -= 2; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001002; -CHECKREG r1, 0x00001102; -CHECKREG r2, 0x00001012; -CHECKREG r3, 0x00001003; -CHECKREG r4, 0x00001000; -CHECKREG r5, 0x00001100; -CHECKREG r6, 0x00001010; -CHECKREG r7, 0x00001001; - - I0 += 4; - I1 += 4; - I2 += 4; - I3 += 4; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += 4; - I1 += 4; - I2 += 4; - I3 += 4; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001004; -CHECKREG r1, 0x00001104; -CHECKREG r2, 0x00001014; -CHECKREG r3, 0x00001005; -CHECKREG r4, 0x00001008; -CHECKREG r5, 0x00001108; -CHECKREG r6, 0x00001018; -CHECKREG r7, 0x00001009; - - I0 -= 4; - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG r0, 0x00001000; -CHECKREG r1, 0x00001100; -CHECKREG r2, 0x00001010; -CHECKREG r3, 0x00001001; -CHECKREG r4, 0x00001008; -CHECKREG r5, 0x00001108; -CHECKREG r6, 0x00001018; -CHECKREG r7, 0x00001009; - - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001000; -CHECKREG r1, 0x00001100; -CHECKREG r2, 0x00001010; -CHECKREG r3, 0x00001001; -CHECKREG r4, 0x0000100D; -CHECKREG r5, 0x0000110E; -CHECKREG r6, 0x0000101F; -CHECKREG r7, 0x00001011; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dagmodik_lnz_imltbl.s b/sim/testsuite/sim/bfin/c_dagmodik_lnz_imltbl.s deleted file mode 100644 index 7142682..0000000 --- a/sim/testsuite/sim/bfin/c_dagmodik_lnz_imltbl.s +++ /dev/null @@ -1,289 +0,0 @@ -//Original:/testcases/core/c_dagmodik_lnz_imltbl/c_dagmodik_lnz_imltbl.dsp -// Spec Reference: dagmodik l not zero & i+m < b -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -imm32 i0, 0x00001000; -imm32 i1, 0x00001100; -imm32 i2, 0x00001010; -imm32 i3, 0x00001001; - -imm32 b0, 0x0000100e; -imm32 b1, 0x0000110c; -imm32 b2, 0x0000101a; -imm32 b3, 0x00001008; - -imm32 l0, 0x000000a1; -imm32 l1, 0x000000b2; -imm32 l2, 0x000000c3; -imm32 l3, 0x000000d4; - -imm32 m0, 0x00000005; -imm32 m1, 0x00000004; -imm32 m2, 0x00000003; -imm32 m3, 0x00000002; - - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001002; -CHECKREG r1, 0x00001102; -CHECKREG r2, 0x00001012; -CHECKREG r3, 0x00001003; -CHECKREG r4, 0x00001004; -CHECKREG r5, 0x00001104; -CHECKREG r6, 0x00001014; -CHECKREG r7, 0x00001005; - - - I0 -= 2; - I1 -= 2; - I2 -= 2; - I3 -= 2; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 -= 2; - I1 -= 2; - I2 -= 2; - I3 -= 2; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x000010A3; -CHECKREG r1, 0x000011B4; -CHECKREG r2, 0x000010D5; -CHECKREG r3, 0x000010D7; -CHECKREG r4, 0x000010A1; -CHECKREG r5, 0x000011B2; -CHECKREG r6, 0x000010D3; -CHECKREG r7, 0x000010D5; - - I0 += 4; - I1 += 4; - I2 += 4; - I3 += 4; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += 4; - I1 += 4; - I2 += 4; - I3 += 4; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x000010A5; -CHECKREG r1, 0x000011B6; -CHECKREG r2, 0x000010D7; -CHECKREG r3, 0x000010D9; -CHECKREG r4, 0x000010A9; -CHECKREG r5, 0x000011BA; -CHECKREG r6, 0x000010DB; -CHECKREG r7, 0x00001009; - - I0 -= 4; - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG r0, 0x000010A1; -CHECKREG r1, 0x000011B2; -CHECKREG r2, 0x000010D3; -CHECKREG r3, 0x000010D5; -CHECKREG r4, 0x000010A9; -CHECKREG r5, 0x000011BA; -CHECKREG r6, 0x000010DB; -CHECKREG r7, 0x00001009; - - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x000010A1; -CHECKREG r1, 0x000011B2; -CHECKREG r2, 0x000010D3; -CHECKREG r3, 0x000010D5; -CHECKREG r4, 0x00001099; -CHECKREG r5, 0x000011AA; -CHECKREG r6, 0x000010CB; -CHECKREG r7, 0x000010CD; - -// i+m = b+l -imm32 i0, 0x00001000; -imm32 i1, 0x00001100; -imm32 i2, 0x00001010; -imm32 i3, 0x00001001; - -imm32 b0, 0x0000100e; -imm32 b1, 0x0000110c; -imm32 b2, 0x0000101a; -imm32 b3, 0x00001008; - -imm32 l0, 0x00000011; -imm32 l1, 0x00000012; -imm32 l2, 0x00000013; -imm32 l3, 0x00000014; - -imm32 m0, 0x00000002; -imm32 m1, 0x00000003; -imm32 m2, 0x00000004; -imm32 m3, 0x00000005; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001002; -CHECKREG r1, 0x00001102; -CHECKREG r2, 0x00001012; -CHECKREG r3, 0x00001003; -CHECKREG r4, 0x00001004; -CHECKREG r5, 0x00001104; -CHECKREG r6, 0x00001014; -CHECKREG r7, 0x00001005; - - - I0 -= 2; - I1 -= 2; - I2 -= 2; - I3 -= 2; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 -= 2; - I1 -= 2; - I2 -= 2; - I3 -= 2; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001013; -CHECKREG r1, 0x00001114; -CHECKREG r2, 0x00001025; -CHECKREG r3, 0x00001017; -CHECKREG r4, 0x00001011; -CHECKREG r5, 0x00001112; -CHECKREG r6, 0x00001023; -CHECKREG r7, 0x00001015; - - I0 += 4; - I1 += 4; - I2 += 4; - I3 += 4; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += 4; - I1 += 4; - I2 += 4; - I3 += 4; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001015; -CHECKREG r1, 0x00001116; -CHECKREG r2, 0x00001027; -CHECKREG r3, 0x00001019; -CHECKREG r4, 0x00001019; -CHECKREG r5, 0x0000111A; -CHECKREG r6, 0x0000102B; -CHECKREG r7, 0x00001009; - - I0 -= 4; - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG r0, 0x00001011; -CHECKREG r1, 0x00001112; -CHECKREG r2, 0x00001023; -CHECKREG r3, 0x00001015; -CHECKREG r4, 0x00001019; -CHECKREG r5, 0x0000111A; -CHECKREG r6, 0x0000102B; -CHECKREG r7, 0x00001009; - - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001011; -CHECKREG r1, 0x00001112; -CHECKREG r2, 0x00001023; -CHECKREG r3, 0x00001015; -CHECKREG r4, 0x0000101A; -CHECKREG r5, 0x0000111C; -CHECKREG r6, 0x0000101B; -CHECKREG r7, 0x0000100D; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dagmodik_lz_inc_dec.s b/sim/testsuite/sim/bfin/c_dagmodik_lz_inc_dec.s deleted file mode 100644 index 64ac946..0000000 --- a/sim/testsuite/sim/bfin/c_dagmodik_lz_inc_dec.s +++ /dev/null @@ -1,140 +0,0 @@ -//Original:/testcases/core/c_dagmodik_lz_inc_dec/c_dagmodik_lz_inc_dec.dsp -// Spec Reference: dagmodik L=0, I incremented & decremented -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -imm32 i0, 0x00001000; -imm32 i1, 0x00001100; -imm32 i2, 0x00001200; -imm32 i3, 0x00001300; -imm32 m0, 0x00000000; -imm32 m1, 0x00000110; -imm32 m2, 0x00000210; -imm32 m3, 0x00000310; - - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001002; -CHECKREG r1, 0x00001102; -CHECKREG r2, 0x00001202; -CHECKREG r3, 0x00001302; -CHECKREG r4, 0x00001004; -CHECKREG r5, 0x00001104; -CHECKREG r6, 0x00001204; -CHECKREG r7, 0x00001304; - - - I0 -= 2; - I1 -= 2; - I2 -= 2; - I3 -= 2; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 -= 2; - I1 -= 2; - I2 -= 2; - I3 -= 2; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001002; -CHECKREG r1, 0x00001102; -CHECKREG r2, 0x00001202; -CHECKREG r3, 0x00001302; -CHECKREG r4, 0x00001000; -CHECKREG r5, 0x00001100; -CHECKREG r6, 0x00001200; -CHECKREG r7, 0x00001300; - - I0 += 4; - I1 += 4; - I2 += 4; - I3 += 4; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += 4; - I1 += 4; - I2 += 4; - I3 += 4; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001004; -CHECKREG r1, 0x00001104; -CHECKREG r2, 0x00001204; -CHECKREG r3, 0x00001304; -CHECKREG r4, 0x00001008; -CHECKREG r5, 0x00001108; -CHECKREG r6, 0x00001208; -CHECKREG r7, 0x00001308; - - I0 -= 4; - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG r0, 0x00001000; -CHECKREG r1, 0x00001100; -CHECKREG r2, 0x00001200; -CHECKREG r3, 0x00001300; -CHECKREG r4, 0x00001008; -CHECKREG r5, 0x00001108; -CHECKREG r6, 0x00001208; -CHECKREG r7, 0x00001308; - - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; - I0 -= 4; - I1 -= 4; - I2 -= 4; - I3 -= 4; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001000; -CHECKREG r1, 0x00001100; -CHECKREG r2, 0x00001200; -CHECKREG r3, 0x00001300; -CHECKREG r4, 0x00000FF8; -CHECKREG r5, 0x000010F8; -CHECKREG r6, 0x000011F8; -CHECKREG r7, 0x000012F8; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dagmodim_lnz_imgebl.s b/sim/testsuite/sim/bfin/c_dagmodim_lnz_imgebl.s deleted file mode 100644 index 4189c05..0000000 --- a/sim/testsuite/sim/bfin/c_dagmodim_lnz_imgebl.s +++ /dev/null @@ -1,108 +0,0 @@ -//Original:/testcases/core/c_dagmodim_lnz_imgebl/c_dagmodim_lnz_imgebl.dsp -// Spec Reference: dagmodim l not zero & i+m >= b+l -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -imm32 i0, 0x00001000; -imm32 i1, 0x00001100; -imm32 i2, 0x00001010; -imm32 i3, 0x00001001; - -imm32 b0, 0x00001000; -imm32 b1, 0x00001000; -imm32 b2, 0x00001000; -imm32 b3, 0x00001000; - -imm32 l0, 0x00000001; -imm32 l1, 0x00000002; -imm32 l2, 0x00000003; -imm32 l3, 0x00000004; - -imm32 m0, 0x00000015; -imm32 m1, 0x00000016; -imm32 m2, 0x00000017; -imm32 m3, 0x00000018; - - I0 += M0; - I1 += M1; - I2 += M2; - I3 += M3; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += M1; - I1 += M2; - I2 += M3; - I3 += M0; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; - -CHECKREG r0, 0x00001014; -CHECKREG r1, 0x00001114; -CHECKREG r2, 0x00001024; -CHECKREG r3, 0x00001015; -CHECKREG r4, 0x00001029; -CHECKREG r5, 0x00001129; -CHECKREG r6, 0x00001039; -CHECKREG r7, 0x00001026; - - I0 -= M2; - I1 -= M3; - I2 -= M0; - I3 -= M1; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 -= M3; - I1 -= M2; - I2 -= M1; - I3 -= M0; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001012; -CHECKREG r1, 0x00001111; -CHECKREG r2, 0x00001024; -CHECKREG r3, 0x00001010; -CHECKREG r4, 0x00000FFB; -CHECKREG r5, 0x000010FA; -CHECKREG r6, 0x0000100E; -CHECKREG r7, 0x00000FFF; - - I0 += M3 (BREV); - I1 += M0 (BREV); - I2 += M1 (BREV); - I3 += M2 (BREV); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += M2 (BREV); - I1 += M3 (BREV); - I2 += M0 (BREV); - I3 += M1 (BREV); -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00000FEF; -CHECKREG r1, 0x000010E0; -CHECKREG r2, 0x0000101B; -CHECKREG r3, 0x00000FE7; -CHECKREG r4, 0x00000FFB; -CHECKREG r5, 0x000010F8; -CHECKREG r6, 0x00001001; -CHECKREG r7, 0x00000FF2; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dagmodim_lnz_imltbl.s b/sim/testsuite/sim/bfin/c_dagmodim_lnz_imltbl.s deleted file mode 100644 index 152c94b..0000000 --- a/sim/testsuite/sim/bfin/c_dagmodim_lnz_imltbl.s +++ /dev/null @@ -1,109 +0,0 @@ -//Original:/testcases/core/c_dagmodim_lnz_imltbl/c_dagmodim_lnz_imltbl.dsp -// Spec Reference: dagmodim l not zero & i+m < b -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -imm32 i0, 0x00001000; -imm32 i1, 0x00001100; -imm32 i2, 0x00001010; -imm32 i3, 0x00001001; - -imm32 b0, 0x0000110e; -imm32 b1, 0x0000110c; -imm32 b2, 0x0000110a; -imm32 b3, 0x00001108; - -imm32 l0, 0x000000a1; -imm32 l1, 0x000000b2; -imm32 l2, 0x000000c3; -imm32 l3, 0x000000d4; - -imm32 m0, 0x00000005; -imm32 m1, 0x00000004; -imm32 m2, 0x00000003; -imm32 m3, 0x00000002; - - I0 += M0; - I1 += M1; - I2 += M2; - I3 += M3; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += M1; - I1 += M2; - I2 += M3; - I3 += M0; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001005; -CHECKREG r1, 0x00001104; -CHECKREG r2, 0x00001013; -CHECKREG r3, 0x00001003; -CHECKREG r4, 0x00001009; -CHECKREG r5, 0x00001107; -CHECKREG r6, 0x00001015; -CHECKREG r7, 0x00001008; - - - I0 -= M2; - I1 -= M3; - I2 -= M0; - I3 -= M1; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 -= M3; - I1 -= M2; - I2 -= M1; - I3 -= M0; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x000010A7; -CHECKREG r1, 0x000011B7; -CHECKREG r2, 0x000010D3; -CHECKREG r3, 0x000010D8; -CHECKREG r4, 0x00001146; -CHECKREG r5, 0x000011B4; -CHECKREG r6, 0x00001192; -CHECKREG r7, 0x000011A7; - - I0 += M3 (BREV); - I1 += M0 (BREV); - I2 += M1 (BREV); - I3 += M2 (BREV); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += M2 (BREV); - I1 += M3 (BREV); - I2 += M0 (BREV); - I3 += M1 (BREV); -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x00001145; -CHECKREG r1, 0x000011B3; -CHECKREG r2, 0x00001196; -CHECKREG r3, 0x000011A5; -CHECKREG r4, 0x00001146; -CHECKREG r5, 0x000011B0; -CHECKREG r6, 0x00001190; -CHECKREG r7, 0x000011A3; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dagmodim_lz_inc_dec.s b/sim/testsuite/sim/bfin/c_dagmodim_lz_inc_dec.s deleted file mode 100644 index 094a7d8..0000000 --- a/sim/testsuite/sim/bfin/c_dagmodim_lz_inc_dec.s +++ /dev/null @@ -1,98 +0,0 @@ -//Original:/testcases/core/c_dagmodim_lz_inc_dec/c_dagmodim_lz_inc_dec.dsp -// Spec Reference: dagmodim L=0, I incremented & decremented (by M) -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -imm32 i0, 0x10001000; -imm32 i1, 0x02001100; -imm32 i2, 0x00301010; -imm32 i3, 0x00041001; - -imm32 m0, 0x00000005; -imm32 m1, 0x00000006; -imm32 m2, 0x00000007; -imm32 m3, 0x00000008; - - I0 += M0; - I1 += M1; - I2 += M2; - I3 += M3; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += M1; - I1 += M2; - I2 += M3; - I3 += M0; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; - -CHECKREG r0, 0x10001005; -CHECKREG r1, 0x02001106; -CHECKREG r2, 0x00301017; -CHECKREG r3, 0x00041009; -CHECKREG r4, 0x1000100B; -CHECKREG r5, 0x0200110D; -CHECKREG r6, 0x0030101F; -CHECKREG r7, 0x0004100E; - - I0 -= M2; - I1 -= M3; - I2 -= M0; - I3 -= M1; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 -= M3; - I1 -= M2; - I2 -= M1; - I3 -= M0; -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x10001004; -CHECKREG r1, 0x02001105; -CHECKREG r2, 0x0030101A; -CHECKREG r3, 0x00041008; -CHECKREG r4, 0x10000FFC; -CHECKREG r5, 0x020010FE; -CHECKREG r6, 0x00301014; -CHECKREG r7, 0x00041003; - - I0 += M3 (BREV); - I1 += M0 (BREV); - I2 += M1 (BREV); - I3 += M2 (BREV); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; - I0 += M2 (BREV); - I1 += M3 (BREV); - I2 += M0 (BREV); - I3 += M1 (BREV); -R4 = I0; -R5 = I1; -R6 = I2; -R7 = I3; -CHECKREG r0, 0x10000FF2; -CHECKREG r1, 0x020010F8; -CHECKREG r2, 0x00301011; -CHECKREG r3, 0x00041005; -CHECKREG r4, 0x10000FF4; -CHECKREG r5, 0x020010F4; -CHECKREG r6, 0x00301014; -CHECKREG r7, 0x00041000; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_a0_pm_a1.s b/sim/testsuite/sim/bfin/c_dsp32alu_a0_pm_a1.s deleted file mode 100644 index dda7ddd..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_a0_pm_a1.s +++ /dev/null @@ -1,39 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_a0_pm_a1/c_dsp32alu_a0_pm_a1.dsp -// Spec Reference: dsp32alu a0 += a1 -# mach: bfin - -.include "testutils.inc" - start - - - -A1 = A0 = 0; - -imm32 r0, 0x25678911; -imm32 r1, 0x0029ab2d; -imm32 r2, 0x00145535; -imm32 r3, 0xf6567747; -imm32 r4, 0xe566895b; -imm32 r5, 0x67897b6d; -imm32 r6, 0xb4445875; -imm32 r7, 0x86667797; -A0 = R0; -A1 = R1; - -A0 += A1; -A0 += A1 (W32); -A0 += A1; -A0 += A1 (W32); -R5 = A0.w; - -A1 = R2; -A0 -= A1; -A0 -= A1 (W32); -A0 -= A1; -A0 -= A1 (W32); -R6 = A0.w; -CHECKREG r5, 0x260E35C5; -CHECKREG r6, 0x25BCE0F1; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_a0a1s.s b/sim/testsuite/sim/bfin/c_dsp32alu_a0a1s.s deleted file mode 100644 index ee20bb7..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_a0a1s.s +++ /dev/null @@ -1,82 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_a0a1s/c_dsp32alu_a0a1s.dsp -// Spec Reference: dsp32alu a0a1s -# mach: bfin - -.include "testutils.inc" - start - - - -A1 = A0 = 0; - -imm32 r0, 0x15678911; -imm32 r1, 0xa789ab1d; -imm32 r2, 0xd4445515; -imm32 r3, 0xf6667717; -imm32 r4, 0xe567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0xb4445515; -imm32 r7, 0x86667777; -// A0 & A1 types -A0 = R0; -A1 = R1; - R6 = A0.w; - R7 = A1.w; -A0 = 0; -A1 = 0; - R0 = A0.w; - R1 = A1.w; -A0 = R2; -A1 = R3; -A0 = A0 (S); -A1 = A1 (S); - R4 = A0.w; - R5 = A1.w; -A0 = A1; - R2 = A0.w; -A0 = R3; -A1 = A0; - R3 = A1.w; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0xF6667717; -CHECKREG r3, 0xF6667717; -CHECKREG r4, 0xD4445515; -CHECKREG r5, 0xF6667717; -CHECKREG r6, 0x15678911; -CHECKREG r7, 0xA789AB1D; - -A1 = A0 = 0; - R0 = A0.w; - R1 = A1.w; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; - -imm32 r0, 0xa1567891; -imm32 r1, 0xba789abd; -imm32 r2, 0xcd412355; -imm32 r3, 0xdf646777; -imm32 r4, 0xe567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0xb4445515; -imm32 r7, 0xf666aeb7; - -A0 = R4; -A1 = R5; - R0 = A0.w; - R1 = A1.w; -A0 = R6; -A1 = R7; - R2 = A0.w; - R3 = A1.w; -CHECKREG r0, 0xE567891B; -CHECKREG r1, 0x6789AB1D; -CHECKREG r2, 0xB4445515; -CHECKREG r3, 0xF666AEB7; -CHECKREG r4, 0xE567891B; -CHECKREG r5, 0x6789AB1D; -CHECKREG r6, 0xB4445515; -CHECKREG r7, 0xF666AEB7; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_a_abs_a.s b/sim/testsuite/sim/bfin/c_dsp32alu_a_abs_a.s deleted file mode 100644 index 3a83972..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_a_abs_a.s +++ /dev/null @@ -1,34 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_a_abs_a/c_dsp32alu_a_abs_a.dsp -// Spec Reference: dsp32alu a = abs a -# mach: bfin - -.include "testutils.inc" - start - - - - - -imm32 r0, 0xa5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3b44b515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -A1 = A0 = 0; -A0 = R0; - -A0 = ABS A0; -A1 = ABS A0; -A1 = ABS A1; -A0 = ABS A1; -R1 = A0.w; -R2 = A1.w; -CHECKREG r0, 0xA5678911; -CHECKREG r1, 0x5A9876EF; -CHECKREG r2, 0x5A9876EF; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_a_neg_a.s b/sim/testsuite/sim/bfin/c_dsp32alu_a_neg_a.s deleted file mode 100644 index 263e900..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_a_neg_a.s +++ /dev/null @@ -1,34 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_a_neg_a/c_dsp32alu_a_neg_a.dsp -// Spec Reference: dsp32alu a = neg a -# mach: bfin - -.include "testutils.inc" - start - - - - - -imm32 r0, 0xa5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3b44b515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -A1 = A0 = 0; -A0 = R0; - -A0 = - A0; -A1 = - A0; -A1 = - A1; -A0 = - A1; -R1 = A0.w; -R2 = A1.w; -CHECKREG r0, 0xA5678911; -CHECKREG r1, 0xA5678911; -CHECKREG r2, 0x5A9876EF; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_aa_absabs.s b/sim/testsuite/sim/bfin/c_dsp32alu_aa_absabs.s deleted file mode 100644 index fd505f0..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_aa_absabs.s +++ /dev/null @@ -1,35 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_aa_absabs/c_dsp32alu_aa_absabs.dsp -// Spec Reference: dsp32alu a1, a0 = abs / abs a1, a0 -# mach: bfin - -.include "testutils.inc" - start - - - - - -imm32 r0, 0xa5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3b44b515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -A0 = R0; -A1 = R1; - -A1 = ABS A1, A0 = ABS A0; -R2 = A0.w; -R3 = A1.w; -A1 = ABS A1, A0 = ABS A0; -R4 = A0.w; -R5 = A1.w; -CHECKREG r2, 0x5A9876EF; -CHECKREG r3, 0x2789AB1D; -CHECKREG r4, 0x5A9876EF; -CHECKREG r5, 0x2789AB1D; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_aa_negneg.s b/sim/testsuite/sim/bfin/c_dsp32alu_aa_negneg.s deleted file mode 100644 index 4d6f4bf..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_aa_negneg.s +++ /dev/null @@ -1,35 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_aa_negneg/c_dsp32alu_aa_negneg.dsp -// Spec Reference: dsp32alu a1, a0 = neg / neg a1, a0 -# mach: bfin - -.include "testutils.inc" - start - - - - - -imm32 r0, 0xa5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3b44b515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -A0 = R0; -A1 = R1; - -A1 = - A1, A0 = - A0; -R2 = A0.w; -R3 = A1.w; -A1 = - A1, A0 = - A0; -R4 = A0.w; -R5 = A1.w; -CHECKREG r2, 0x5A9876EF; -CHECKREG r3, 0xD87654E3; -CHECKREG r4, 0xA5678911; -CHECKREG r5, 0x2789AB1D; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_abs.s b/sim/testsuite/sim/bfin/c_dsp32alu_abs.s deleted file mode 100644 index 0504a7b..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_abs.s +++ /dev/null @@ -1,62 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_abs/c_dsp32alu_abs.dsp -// Spec Reference: dsp32alu dregs = abs ( dregs, dregs) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0 = ABS R0; -R1 = ABS R1; -R2 = ABS R2; -R3 = ABS R3; -R4 = ABS R4; -R5 = ABS R5; -R6 = ABS R6; -R7 = ABS R7; -CHECKREG r0, 0x15678911; -CHECKREG r1, 0x2789AB1D; -CHECKREG r2, 0x34445515; -CHECKREG r3, 0x46667717; -CHECKREG r4, 0x5567891B; -CHECKREG r5, 0x6789AB1D; -CHECKREG r6, 0x74445515; -CHECKREG r7, 0x79998889; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r4, 0xd8889929; -imm32 r5, 0xeaaabb2b; -imm32 r6, 0xfcccdd2d; -imm32 r7, 0x0eeeffff; -R0 = ABS R7; -R1 = ABS R6; -R2 = ABS R5; -R3 = ABS R4; -R4 = ABS R3; -R5 = ABS R2; -R6 = ABS R1; -R7 = ABS R0; -CHECKREG r0, 0x0EEEFFFF; -CHECKREG r1, 0x033322D3; -CHECKREG r2, 0x155544D5; -CHECKREG r3, 0x277766D7; -CHECKREG r4, 0x277766D7; -CHECKREG r5, 0x155544D5; -CHECKREG r6, 0x033322D3; -CHECKREG r7, 0x0EEEFFFF; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_absabs.s b/sim/testsuite/sim/bfin/c_dsp32alu_absabs.s deleted file mode 100644 index bb1cafc..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_absabs.s +++ /dev/null @@ -1,62 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_absabs/c_dsp32alu_absabs.dsp -// Spec Reference: dsp32alu dregs = abs / abs ( dregs, dregs) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0 = ABS R0 (V); -R1 = ABS R1 (V); -R2 = ABS R2 (V); -R3 = ABS R3 (V); -R4 = ABS R4 (V); -R5 = ABS R5 (V); -R6 = ABS R6 (V); -R7 = ABS R7 (V); -CHECKREG r0, 0x156776EF; -CHECKREG r1, 0x278954E3; -CHECKREG r2, 0x34445515; -CHECKREG r3, 0x46667717; -CHECKREG r4, 0x556776E5; -CHECKREG r5, 0x678954E3; -CHECKREG r6, 0x74445515; -CHECKREG r7, 0x799A7777; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r4, 0xd8889929; -imm32 r5, 0xeaaabb2b; -imm32 r6, 0xfcccdd2d; -imm32 r7, 0x0eeeffff; -R0 = ABS R7 (V); -R1 = ABS R6 (V); -R2 = ABS R5 (V); -R3 = ABS R4 (V); -R4 = ABS R3 (V); -R5 = ABS R2 (V); -R6 = ABS R1 (V); -R7 = ABS R0 (V); -CHECKREG r0, 0x0EEE0001; -CHECKREG r1, 0x033422D3; -CHECKREG r2, 0x155644D5; -CHECKREG r3, 0x277866D7; -CHECKREG r4, 0x277866D7; -CHECKREG r5, 0x155644D5; -CHECKREG r6, 0x033422D3; -CHECKREG r7, 0x0EEE0001; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_alhwx.s b/sim/testsuite/sim/bfin/c_dsp32alu_alhwx.s deleted file mode 100644 index 3ca87a7..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_alhwx.s +++ /dev/null @@ -1,128 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_alhwx/c_dsp32alu_alhwx.dsp -// Spec Reference: dsp32alu alhwx -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - A1 = A0 = 0; - - imm32 r0, 0xa5678911; - imm32 r1, 0xaa89ab1d; - imm32 r2, 0xd4b45515; - imm32 r3, 0xf66e7717; - imm32 r4, 0xe567f91b; - imm32 r5, 0x6789ae1d; - imm32 r6, 0xb4445515; - imm32 r7, 0x8666a7d7; - A0.L = R0.L; - A0.H = R0.H; - A0.x = R1.L; - R7 = A0.w; - R6 = A0.x; - R5.L = A0.x; - A1.L = R4.L; - A1.H = R4.H; - A1.x = R3.L; - R0 = A1.w; - R1 = A1.x; - R2.L = A1.x; - CHECKREG r0, 0xE567F91B; - CHECKREG r1, 0x00000017; - CHECKREG r2, 0xD4B40017; - CHECKREG r3, 0xF66E7717; - CHECKREG r4, 0xE567F91B; - CHECKREG r5, 0x6789001D; - CHECKREG r6, 0x0000001D; - CHECKREG r7, 0xA5678911; - - imm32 r0, 0xe5678911; - imm32 r1, 0xaa89ab1d; - imm32 r2, 0xdfb45515; - imm32 r3, 0xf66e7717; - imm32 r4, 0xe5d7f91b; - imm32 r5, 0x67e9ae1d; - imm32 r6, 0xb4445515; - imm32 r7, 0x866aa7b7; - A0.L = R1.L; - A0.H = R1.H; - A0.x = R2.L; - R5 = A0.w; - R7 = A0.x; - R6.L = A0.x; - A1.L = R3.L; - A1.H = R3.H; - A1.x = R4.L; - R1 = A1.w; - R2 = A1.x; - R0.L = A1.x; - CHECKREG r0, 0xE567001B; - CHECKREG r1, 0xF66E7717; - CHECKREG r2, 0x0000001B; - CHECKREG r3, 0xF66E7717; - CHECKREG r4, 0xE5D7F91B; - CHECKREG r5, 0xAA89AB1D; - CHECKREG r6, 0xB4440015; - CHECKREG r7, 0x00000015; - - imm32 r0, 0x35678911; - imm32 r1, 0xa489ab1d; - imm32 r2, 0xd4545515; - imm32 r3, 0xf6667717; - imm32 r4, 0x9567f91b; - imm32 r5, 0x6a89ae1d; - imm32 r6, 0xb4445515; - imm32 r7, 0x8666a7d7; - A0.L = R3.L; - A0.H = R3.H; - A0.x = R4.L; - R0 = A0.w; - R1 = A0.x; - R2.L = A0.x; - A1.L = R5.L; - A1.H = R6.H; - A1.x = R7.L; - R7 = A1.w; - R5 = A1.x; - R5.L = A1.x; - CHECKREG r0, 0xF6667717; - CHECKREG r1, 0x0000001B; - CHECKREG r2, 0xD454001B; - CHECKREG r3, 0xF6667717; - CHECKREG r4, 0x9567F91B; - CHECKREG r5, 0xffffffD7; - CHECKREG r6, 0xB4445515; - CHECKREG r7, 0xB444AE1D; - - imm32 r0, 0xd5678911; - imm32 r1, 0x2a89ab1d; - imm32 r2, 0xd3b45515; - imm32 r3, 0xf66e7717; - imm32 r4, 0xe5d7f91b; - imm32 r5, 0x67e9ae1d; - imm32 r6, 0xb4445515; - imm32 r7, 0x889aa7b7; - A0.L = R4.L; - A0.H = R5.H; - A0.x = R6.L; - R1 = A0.w; - R2 = A0.x; - R3.L = A0.x; - A1.L = R0.L; - A1.H = R0.H; - A1.x = R7.L; - R4 = A1.w; - R5 = A1.x; - R6.L = A1.x; - CHECKREG r0, 0xD5678911; - CHECKREG r1, 0x67E9F91B; - CHECKREG r2, 0x00000015; - CHECKREG r3, 0xF66E0015; - CHECKREG r4, 0xD5678911; - CHECKREG r5, 0xffffffB7; - CHECKREG r6, 0xB444ffB7; - CHECKREG r7, 0x889AA7B7; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_awx.s b/sim/testsuite/sim/bfin/c_dsp32alu_awx.s deleted file mode 100644 index 652264c..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_awx.s +++ /dev/null @@ -1,61 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_awx/c_dsp32alu_awx.dsp -// Spec Reference: dsp32alu awx -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -// A0 & A1 types -A0 = 0; -A1 = 0; - -A0.L = R0.L; -A0.H = R0.H; -A0.x = R2.L; -R3 = A0.w; -R4 = A1.w; -R5.L = A0.x; -//rl6 = a1x; -CHECKREG r3, 0x15678911; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x67890015; -//CHECKREG r6, 0x74440000; - -R5 = ( A0 += A1 ); -R6.L = ( A0 += A1 ); -R7.H = ( A0 += A1 ); -CHECKREG r5, 0x7FFFFFFF; -CHECKREG r6, 0x74447FFF; -CHECKREG r7, 0x7FFF7777; - -A0 += A1; -R0 = A0.w; -CHECKREG r0, 0x15678911; - -A0 -= A1; -R1 = A0.w; -CHECKREG r1, 0x15678911; - -R2 = A1.L + A1.H, R3 = A0.L + A0.H; /* 0x */ -CHECKREG r2, 0x00000000; -CHECKREG r3, 0xFFFF9E78; - -A0 = A1; -R4 = A0.w; -R5 = A1.w; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_byteop1ew.s b/sim/testsuite/sim/bfin/c_dsp32alu_byteop1ew.s deleted file mode 100644 index ff20a19..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_byteop1ew.s +++ /dev/null @@ -1,136 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop1ew/c_dsp32alu_byteop1ew.dsp -// Spec Reference: dsp32alu byteop1ew -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r4, 0x5567891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x74445515; - imm32 r7, 0x86667777; - R4 = BYTEOP1P ( R1:0 , R3:2 ); - R5 = BYTEOP1P ( R1:0 , R3:2 ) (R); - R6 = BYTEOP1P ( R1:0 , R3:2 ) (T); - R7 = BYTEOP1P ( R1:0 , R3:2 ) (T , R); - R0 = BYTEOP1P ( R1:0 , R3:2 ) (T , R); - CHECKREG r4, 0x25566F13; - CHECKREG r5, 0x3778911A; - CHECKREG r6, 0x24556F13; - CHECKREG r7, 0x3677911A; - CHECKREG r0, 0x3677911A; - - imm32 r0, 0x1567892b; - imm32 r1, 0x2789ab2d; - imm32 r2, 0x34445525; - imm32 r3, 0x46667727; - imm32 r4, 0x58889929; - imm32 r5, 0x6aaabb2b; - imm32 r6, 0x7cccdd2d; - imm32 r7, 0x8eeeffff; - R0 = BYTEOP1P ( R3:2 , R1:0 ); - R1 = BYTEOP1P ( R3:2 , R1:0 ) (R); - R2 = BYTEOP1P ( R3:2 , R1:0 ) (T); - R3 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); - R4 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); - R5 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); - R6 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); - R7 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); - CHECKREG r0, 0x25566F28; - CHECKREG r1, 0x3778912A; - CHECKREG r2, 0x2C4D6226; - CHECKREG r3, 0x3E6F8428; - CHECKREG r4, 0x3A738A29; - CHECKREG r5, 0x3A738A29; - CHECKREG r6, 0x3A738A29; - CHECKREG r7, 0x3A738A29; - - imm32 r0, 0x416789ab; - imm32 r1, 0x6289abcd; - imm32 r2, 0x43445555; - imm32 r3, 0x64667777; - imm32 r0, 0x456789ab; - imm32 r1, 0x6689abcd; - imm32 r2, 0x47445555; - imm32 r3, 0x68667777; - ( R1 , R2 ) = BYTEOP16P ( R1:0 , R3:2 ); - ( R0 , R3 ) = BYTEOP16P ( R1:0 , R3:2 ) (R); - ( R4 , R5 ) = BYTEOP16P ( R3:2 , R1:0 ); - ( R6 , R7 ) = BYTEOP16P ( R3:2 , R1:0 ); - CHECKREG r0, 0x006800F2; - CHECKREG r1, 0x008C00AB; - CHECKREG r2, 0x00DE0100; - CHECKREG r3, 0x00770122; - CHECKREG r4, 0x00000146; - CHECKREG r5, 0x000100F2; - CHECKREG r6, 0x00000146; - CHECKREG r7, 0x000100F2; - - imm32 r0, 0x416789ab; - imm32 r1, 0x6289abcd; - imm32 r2, 0x43445555; - imm32 r3, 0x64667777; - imm32 r0, 0x456789ab; - imm32 r1, 0x6689abcd; - imm32 r2, 0x47445555; - imm32 r3, 0x68667777; - ( R7 , R6 ) = BYTEOP16P ( R3:2 , R1:0 ); - ( R5 , R4 ) = BYTEOP16P ( R3:2 , R1:0 ) (R); - ( R2 , R3 ) = BYTEOP16P ( R3:2 , R1:0 ); - ( R1 , R0 ) = BYTEOP16P ( R3:2 , R1:0 ); - CHECKREG r0, 0x00890156; - CHECKREG r1, 0x004500F3; - CHECKREG r2, 0x008C00AB; - CHECKREG r3, 0x00DE0100; - CHECKREG r4, 0x01220144; - CHECKREG r5, 0x00CE00EF; - CHECKREG r6, 0x00DE0100; - CHECKREG r7, 0x008C00AB; - - imm32 r0, 0x416789ab; - imm32 r1, 0x6289abcd; - imm32 r2, 0x43445555; - imm32 r3, 0x64667777; - imm32 r0, 0x456789ab; - imm32 r1, 0x6689abcd; - imm32 r2, 0x47445555; - imm32 r3, 0x68667777; - ( R1 , R2 ) = BYTEOP16M ( R1:0 , R3:2 ); - ( R0 , R3 ) = BYTEOP16M ( R1:0 , R3:2 ) (R); - ( R4 , R5 ) = BYTEOP16M ( R3:2 , R1:0 ); - ( R6 , R7 ) = BYTEOP16M ( R3:2 , R1:0 ); - CHECKREG r0, 0x00970098; - CHECKREG r1, 0xFFFE0023; - CHECKREG r2, 0x00340056; - CHECKREG r3, 0xFF89FFAC; - CHECKREG r4, 0x0000FF9D; - CHECKREG r5, 0x0000FFBE; - CHECKREG r6, 0x0000FF9D; - CHECKREG r7, 0x0000FFBE; - - imm32 r0, 0x516789ab; - imm32 r1, 0x6289abcd; - imm32 r2, 0x73445555; - imm32 r3, 0x84667777; - imm32 r0, 0x956789ab; - imm32 r1, 0xa689abcd; - imm32 r2, 0xb7445555; - imm32 r3, 0xc86def77; - ( R7 , R6 ) = BYTEOP16M ( R3:2 , R1:0 ); - ( R5 , R4 ) = BYTEOP16M ( R3:2 , R1:0 ) (R); - ( R2 , R3 ) = BYTEOP16M ( R3:2 , R1:0 ); - ( R1 , R0 ) = BYTEOP16M ( R3:2 , R1:0 ); - CHECKREG r0, 0x00760032; - CHECKREG r1, 0xFF6BFFBB; - CHECKREG r2, 0x0022FFDD; - CHECKREG r3, 0xFFCCFFAA; - CHECKREG r4, 0x0044FFAA; - CHECKREG r5, 0x0022FFE4; - CHECKREG r6, 0xFFCCFFAA; - CHECKREG r7, 0x0022FFDD; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_byteop2.s b/sim/testsuite/sim/bfin/c_dsp32alu_byteop2.s deleted file mode 100644 index 544a5bd..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_byteop2.s +++ /dev/null @@ -1,76 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop2/c_dsp32alu_byteop2.dsp -// Spec Reference: dsp32alu byteop2 -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r4, 0x5567891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x74445515; - imm32 r7, 0x86667777; - R4 = BYTEOP2P ( R1:0 , R3:2 ) (RNDL); - R5 = BYTEOP2P ( R1:0 , R3:2 ) (RNDL , R); - R6 = BYTEOP2P ( R1:0 , R3:2 ) (RNDH); - R7 = BYTEOP2P ( R1:0 , R3:2 ) (RNDH , R); - CHECKREG r4, 0x003D0041; - CHECKREG r5, 0x00570056; - CHECKREG r6, 0x3D004100; - CHECKREG r7, 0x57005600; - - imm32 r0, 0x1567892b; - imm32 r1, 0x2789ab2d; - imm32 r2, 0x34445525; - imm32 r3, 0x46667727; - imm32 r4, 0x58889929; - imm32 r5, 0x6aaabb2b; - imm32 r6, 0x7cccdd2d; - imm32 r7, 0x8eeeffff; - R0 = BYTEOP2P ( R3:2 , R1:0 ) (RNDL); - R1 = BYTEOP2P ( R3:2 , R1:0 ) (RNDL , R); - R2 = BYTEOP2P ( R3:2 , R1:0 ) (RNDH); - R3 = BYTEOP2P ( R3:2 , R1:0 ) (RNDH , R); - CHECKREG r0, 0x003D004C; - CHECKREG r1, 0x0057005E; - CHECKREG r2, 0x2D003200; - CHECKREG r3, 0x41003F00; - - imm32 r0, 0x716789ab; - imm32 r1, 0x8289abcd; - imm32 r2, 0x93445555; - imm32 r3, 0xa4667777; - imm32 r4, 0xb56789ab; - imm32 r5, 0xd689abcd; - imm32 r6, 0xe7445555; - imm32 r7, 0x6f661235; - R4 = BYTEOP2P ( R1:0 , R3:2 ) (TL); - R5 = BYTEOP2P ( R1:0 , R3:2 ) (TL , R); - R6 = BYTEOP2P ( R1:0 , R3:2 ) (TH); - R7 = BYTEOP2P ( R1:0 , R3:2 ) (TH , R); - CHECKREG r4, 0x006B0077; - CHECKREG r5, 0x00850099; - CHECKREG r6, 0x6B007700; - CHECKREG r7, 0x85009900; - - imm32 r0, 0x416789ab; - imm32 r1, 0x6289abcd; - imm32 r2, 0x43445555; - imm32 r3, 0x64667777; - imm32 r4, 0x456789ab; - imm32 r5, 0x6689abcd; - imm32 r6, 0x47445555; - imm32 r7, 0x68667777; - R0 = BYTEOP2P ( R3:2 , R1:0 ) (TL); - R1 = BYTEOP2P ( R3:2 , R1:0 ) (TL , R); - R2 = BYTEOP2P ( R3:2 , R1:0 ) (TH); - R3 = BYTEOP2P ( R3:2 , R1:0 ) (TH , R); - CHECKREG r0, 0x004B0077; - CHECKREG r1, 0x006D0099; - CHECKREG r2, 0x34004800; - CHECKREG r3, 0x4D006100; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_byteop3.s b/sim/testsuite/sim/bfin/c_dsp32alu_byteop3.s deleted file mode 100644 index af32c06..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_byteop3.s +++ /dev/null @@ -1,76 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop3/c_dsp32alu_byteop3.dsp -// Spec Reference: dsp32alu byteop3 -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r4, 0x5567891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x74445515; - imm32 r7, 0x86667777; - R4 = BYTEOP3P ( R1:0 , R3:2 ) (LO); - R5 = BYTEOP3P ( R1:0 , R3:2 ) (HI); - R6 = BYTEOP3P ( R1:0 , R3:2 ) (LO); - R7 = BYTEOP3P ( R1:0 , R3:2 ) (HI); - CHECKREG r4, 0x00FF0000; - CHECKREG r5, 0xFF000000; - CHECKREG r6, 0x00FF0000; - CHECKREG r7, 0xFF000000; - - imm32 r0, 0x1567892b; - imm32 r1, 0x2789ab2d; - imm32 r2, 0x34445525; - imm32 r3, 0x46667727; - imm32 r4, 0x58889929; - imm32 r5, 0x6aaabb2b; - imm32 r6, 0x7cccdd2d; - imm32 r7, 0x8eeeffff; - R0 = BYTEOP3P ( R3:2 , R1:0 ) (LO); - R1 = BYTEOP3P ( R3:2 , R1:0 ) (LO); - R2 = BYTEOP3P ( R3:2 , R1:0 ) (HI); - R3 = BYTEOP3P ( R3:2 , R1:0 ) (HI); - CHECKREG r0, 0x00FF00FF; - CHECKREG r1, 0x00FF00FF; - CHECKREG r2, 0xFF00FF00; - CHECKREG r3, 0x00000000; - - imm32 r0, 0x716789ab; - imm32 r1, 0x8289abcd; - imm32 r2, 0x93445555; - imm32 r3, 0xa4667777; - imm32 r4, 0xb56789ab; - imm32 r5, 0xd689abcd; - imm32 r6, 0xe7445555; - imm32 r7, 0x6f661235; - R4 = BYTEOP3P ( R1:0 , R3:2 ) (LO); - R5 = BYTEOP3P ( R1:0 , R3:2 ) (LO); - R6 = BYTEOP3P ( R1:0 , R3:2 ) (HI); - R7 = BYTEOP3P ( R1:0 , R3:2 ) (HI); - CHECKREG r4, 0x00FF0000; - CHECKREG r5, 0x00FF0000; - CHECKREG r6, 0xFF000000; - CHECKREG r7, 0xFF000000; - - imm32 r0, 0x416789ab; - imm32 r1, 0x6289abcd; - imm32 r2, 0x43445555; - imm32 r3, 0x64667777; - imm32 r4, 0x456789ab; - imm32 r5, 0x6689abcd; - imm32 r6, 0x47445555; - imm32 r7, 0x68667777; - R0 = BYTEOP3P ( R3:2 , R1:0 ) (LO); - R1 = BYTEOP3P ( R3:2 , R1:0 ) (LO); - R2 = BYTEOP3P ( R3:2 , R1:0 ) (HI); - R3 = BYTEOP3P ( R3:2 , R1:0 ) (HI); - CHECKREG r0, 0x00FF00FF; - CHECKREG r1, 0x00FF00FF; - CHECKREG r2, 0xFF00FF00; - CHECKREG r3, 0x00000000; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_bytepack.s b/sim/testsuite/sim/bfin/c_dsp32alu_bytepack.s deleted file mode 100644 index 731a692..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_bytepack.s +++ /dev/null @@ -1,77 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_bytepack/c_dsp32alu_bytepack.dsp -// Spec Reference: dsp32alu bytepack -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R4 = BYTEPACK ( R0 , R0 ); -R5 = BYTEPACK ( R0 , R1 ); -R6 = BYTEPACK ( R0 , R2 ); -R7 = BYTEPACK ( R0 , R3 ); -CHECKREG r4, 0x67116711; -CHECKREG r5, 0x891D6711; -CHECKREG r6, 0x44156711; -CHECKREG r7, 0x66176711; - -imm32 r0, 0x1567892b; -imm32 r1, 0x2789ab2d; -imm32 r2, 0x34445525; -imm32 r3, 0x46667727; -imm32 r4, 0x58889929; -imm32 r5, 0x6aaabb2b; -imm32 r6, 0x7cccdd2d; -imm32 r7, 0x8eeeffff; -R4 = BYTEPACK ( R1 , R4 ); -R5 = BYTEPACK ( R1 , R5 ); -R6 = BYTEPACK ( R1 , R6 ); -R7 = BYTEPACK ( R1 , R7 ); -CHECKREG r4, 0x8829892D; -CHECKREG r5, 0xAA2B892D; -CHECKREG r6, 0xCC2D892D; -CHECKREG r7, 0xEEFF892D; - -imm32 r0, 0x416789ab; -imm32 r1, 0x6289abcd; -imm32 r2, 0x43445555; -imm32 r3, 0x64667777; -imm32 r0, 0x456789ab; -imm32 r1, 0x6689abcd; -imm32 r2, 0x47445555; -imm32 r3, 0x68667777; -R4 = BYTEPACK ( R2 , R0 ); -R5 = BYTEPACK ( R2 , R1 ); -R6 = BYTEPACK ( R2 , R2 ); -R7 = BYTEPACK ( R2 , R3 ); -CHECKREG r4, 0x67AB4455; -CHECKREG r5, 0x89CD4455; -CHECKREG r6, 0x44554455; -CHECKREG r7, 0x66774455; - -imm32 r0, 0x496789ab; -imm32 r1, 0x6489abcd; -imm32 r2, 0x4b445555; -imm32 r3, 0x6c647777; -imm32 r4, 0x8d889999; -imm32 r5, 0xaeaa4bbb; -imm32 r6, 0xcfccd44d; -imm32 r7, 0xe1eefff4; -R4 = BYTEPACK ( R3 , R4 ); -R5 = BYTEPACK ( R3 , R5 ); -R6 = BYTEPACK ( R3 , R6 ); -R7 = BYTEPACK ( R3 , R7 ); -CHECKREG r4, 0x88996477; -CHECKREG r5, 0xAABB6477; -CHECKREG r6, 0xCC4D6477; -CHECKREG r7, 0xEEF46477; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_byteunpack.s b/sim/testsuite/sim/bfin/c_dsp32alu_byteunpack.s deleted file mode 100644 index 95fa30a..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_byteunpack.s +++ /dev/null @@ -1,113 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteunpack/c_dsp32alu_byteunpack.dsp -// Spec Reference: dsp32alu byteunpack -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r4, 0x5567891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x74445515; - imm32 r7, 0x86667777; - ( R4 , R5 ) = BYTEUNPACK R1:0; - ( R1 , R3 ) = BYTEUNPACK R1:0; - ( R0 , R7 ) = BYTEUNPACK R1:0; - ( R6 , R2 ) = BYTEUNPACK R1:0; - CHECKREG r0, 0x00150067; - CHECKREG r1, 0x00150067; - CHECKREG r2, 0x00000067; - CHECKREG r3, 0x00890011; - CHECKREG r4, 0x00150067; - CHECKREG r5, 0x00890011; - CHECKREG r6, 0x00000015; - CHECKREG r7, 0x00890011; - - imm32 r0, 0x1567892b; - imm32 r1, 0x2789ab2d; - imm32 r2, 0x34445525; - imm32 r3, 0x46667727; - imm32 r4, 0x58889929; - imm32 r5, 0x6aaabb2b; - imm32 r6, 0x7cccdd2d; - imm32 r7, 0x8eeeffff; - ( R1 , R0 ) = BYTEUNPACK R3:2; - ( R3 , R4 ) = BYTEUNPACK R3:2; - ( R5 , R2 ) = BYTEUNPACK R3:2; - ( R7 , R6 ) = BYTEUNPACK R3:2; - CHECKREG r0, 0x00550025; - CHECKREG r1, 0x00340044; - CHECKREG r2, 0x00550025; - CHECKREG r3, 0x00340044; - CHECKREG r4, 0x00550025; - CHECKREG r5, 0x00340044; - CHECKREG r6, 0x00000025; - CHECKREG r7, 0x00000055; - - imm32 r0, 0x416789ab; - imm32 r1, 0x6289abcd; - imm32 r2, 0x43445555; - imm32 r3, 0x64667777; - imm32 r0, 0x456789ab; - imm32 r1, 0x6689abcd; - imm32 r2, 0x47445555; - imm32 r3, 0x68667777; - ( R1 , R2 ) = BYTEUNPACK R1:0 (R); - ( R3 , R6 ) = BYTEUNPACK R1:0 (R); - ( R4 , R0 ) = BYTEUNPACK R1:0 (R); - ( R5 , R7 ) = BYTEUNPACK R1:0 (R); - CHECKREG r0, 0x00000089; - CHECKREG r1, 0x00660089; - CHECKREG r2, 0x00AB00CD; - CHECKREG r3, 0x00000066; - CHECKREG r4, 0x00000066; - CHECKREG r5, 0x00000066; - CHECKREG r6, 0x00000089; - CHECKREG r7, 0x00000089; - - imm32 r0, 0x496789ab; - imm32 r1, 0x6489abcd; - imm32 r2, 0x4b445555; - imm32 r3, 0x6c647777; - imm32 r4, 0x8d889999; - imm32 r5, 0xaeaa4bbb; - imm32 r6, 0xcfccd44d; - imm32 r7, 0xe1eefff4; - ( R0 , R1 ) = BYTEUNPACK R3:2 (R); - ( R2 , R3 ) = BYTEUNPACK R3:2 (R); - ( R4 , R5 ) = BYTEUNPACK R3:2 (R); - ( R6 , R7 ) = BYTEUNPACK R3:2 (R); - CHECKREG r0, 0x006C0064; - CHECKREG r1, 0x00770077; - CHECKREG r2, 0x006C0064; - CHECKREG r3, 0x00770077; - CHECKREG r4, 0x00000077; - CHECKREG r5, 0x00000077; - CHECKREG r6, 0x00000077; - CHECKREG r7, 0x00000077; - - imm32 r0, 0x4537891b; - imm32 r1, 0x6759ab2d; - imm32 r2, 0x44555535; - imm32 r3, 0x66665747; - imm32 r4, 0x88789565; - imm32 r5, 0xaa8abb5b; - imm32 r6, 0xcc9cdd85; - imm32 r7, 0xeeaeff9f; - ( R0 , R1 ) = BYTEUNPACK R1:0; - ( R2 , R3 ) = BYTEUNPACK R3:2 (R); - ( R4 , R5 ) = BYTEUNPACK R1:0 (R); - ( R6 , R7 ) = BYTEUNPACK R3:2; - CHECKREG r0, 0x00450037; - CHECKREG r1, 0x0089001B; - CHECKREG r2, 0x00660066; - CHECKREG r3, 0x00570047; - CHECKREG r4, 0x00000089; - CHECKREG r5, 0x0000001B; - CHECKREG r6, 0x00000066; - CHECKREG r7, 0x00000066; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_disalnexcpt.s b/sim/testsuite/sim/bfin/c_dsp32alu_disalnexcpt.s deleted file mode 100644 index ef5d916..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_disalnexcpt.s +++ /dev/null @@ -1,255 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_disalnexcpt/c_dsp32alu_disalnexcpt.dsp -// Spec Reference: c_dsp32alu_disalgnexcpt -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym P0, DATA1; - P0 += 1; I0 = P0; - loadsym P0, DATA2; - P0 += 1; I1 = P0; - loadsym P0, DATA3; - P0 += 1; I2 = P0; - loadsym P0, DATA4; - P0 += 1; I3 = P0; - - DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; - DISALGNEXCPT || NOP || R1 = [ I1 ++ ]; - DISALGNEXCPT || NOP || R2 = [ I2 ++ ]; - DISALGNEXCPT || NOP || R3 = [ I3 ++ ]; - DISALGNEXCPT || NOP || R4 = [ I0 ++ ]; - DISALGNEXCPT || NOP || R5 = [ I1 ++ ]; - DISALGNEXCPT || NOP || R6 = [ I2 ++ ]; - DISALGNEXCPT || NOP || R7 = [ I3 ++ ]; - CHECKREG r0, 0x00010203; - CHECKREG r1, 0x20212223; - CHECKREG r2, 0x40414243; - CHECKREG r3, 0x60616263; - CHECKREG r4, 0x04050607; - CHECKREG r5, 0x24252627; - CHECKREG r6, 0x44454647; - CHECKREG r7, 0x64656667; - -// reverse to minus mninus i-- - DISALGNEXCPT || NOP || R0 = [ I0 -- ]; - DISALGNEXCPT || NOP || R1 = [ I1 -- ]; - DISALGNEXCPT || NOP || R2 = [ I2 -- ]; - DISALGNEXCPT || NOP || R3 = [ I3 -- ]; - DISALGNEXCPT || NOP || R4 = [ I0 -- ]; - DISALGNEXCPT || NOP || R5 = [ I1 -- ]; - DISALGNEXCPT || NOP || R6 = [ I2 -- ]; - DISALGNEXCPT || NOP || R7 = [ I3 -- ]; - CHECKREG r0, 0x08090A0B; - CHECKREG r1, 0x28292A2B; - CHECKREG r2, 0x48494A4B; - CHECKREG r3, 0x68696A6B; - CHECKREG r4, 0x04050607; - CHECKREG r5, 0x24252627; - CHECKREG r6, 0x44454647; - CHECKREG r7, 0x64656667; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - -DATA2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - -DATA3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - -DATA4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - -DATA5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xBC0DBE26 - -DATA6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_max.s b/sim/testsuite/sim/bfin/c_dsp32alu_max.s deleted file mode 100644 index 74d36f9..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_max.s +++ /dev/null @@ -1,261 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_max/c_dsp32alu_max.dsp -// Spec Reference: dsp32alu dregs = max ( dregs, dregs) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x85678911; -imm32 r1, 0x9789ab1d; -imm32 r2, 0xa4445b15; -imm32 r3, 0x46667717; -imm32 r4, 0xd567f91b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0 = MAX ( R0 , R0 ); -R1 = MAX ( R0 , R1 ); -R2 = MAX ( R0 , R2 ); -R3 = MAX ( R0 , R3 ); -R4 = MAX ( R0 , R4 ); -R5 = MAX ( R0 , R5 ); -R6 = MAX ( R0 , R6 ); -R7 = MAX ( R0 , R7 ); -CHECKREG r0, 0x85678911; -CHECKREG r1, 0x9789AB1D; -CHECKREG r2, 0xA4445B15; -CHECKREG r3, 0x46667717; -CHECKREG r4, 0xD567F91B; -CHECKREG r5, 0x6789AB1D; -CHECKREG r6, 0x74445515; -CHECKREG r7, 0x86667777; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r4, 0xd8889929; -imm32 r5, 0xeaaabb2b; -imm32 r6, 0xfcccdd2d; -imm32 r7, 0x0eeeffff; -R0 = MAX ( R1 , R0 ); -R1 = MAX ( R1 , R1 ); -R2 = MAX ( R1 , R2 ); -R3 = MAX ( R1 , R3 ); -R4 = MAX ( R1 , R4 ); -R5 = MAX ( R1 , R5 ); -R6 = MAX ( R1 , R6 ); -R7 = MAX ( R1 , R7 ); -CHECKREG r0, 0xA789AB2D; -CHECKREG r1, 0xA789AB2D; -CHECKREG r2, 0xB4445525; -CHECKREG r3, 0xC6667727; -CHECKREG r4, 0xD8889929; -CHECKREG r5, 0xEAAABB2B; -CHECKREG r6, 0xFCCCDD2D; -CHECKREG r7, 0x0EEEFFFF; - -imm32 r0, 0x416789ab; -imm32 r1, 0x6289abcd; -imm32 r2, 0x43445555; -imm32 r3, 0x64667777; -imm32 r4, 0x456789ab; -imm32 r5, 0x6689abcd; -imm32 r6, 0x47445555; -imm32 r7, 0x68667777; -R0 = MAX ( R2 , R0 ); -R1 = MAX ( R2 , R1 ); -R2 = MAX ( R2 , R2 ); -R3 = MAX ( R2 , R3 ); -R4 = MAX ( R2 , R4 ); -R5 = MAX ( R2 , R5 ); -R6 = MAX ( R2 , R6 ); -R7 = MAX ( R2 , R7 ); -CHECKREG r0, 0x43445555; -CHECKREG r1, 0x6289ABCD; -CHECKREG r2, 0x43445555; -CHECKREG r3, 0x64667777; -CHECKREG r4, 0x456789AB; -CHECKREG r5, 0x6689ABCD; -CHECKREG r6, 0x47445555; -CHECKREG r7, 0x68667777; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -R0 = MAX ( R3 , R0 ); -R1 = MAX ( R3 , R1 ); -R2 = MAX ( R3 , R2 ); -R3 = MAX ( R3 , R3 ); -R4 = MAX ( R3 , R4 ); -R5 = MAX ( R3 , R5 ); -R6 = MAX ( R3 , R6 ); -R7 = MAX ( R3 , R7 ); -CHECKREG r0, 0xC6667727; -CHECKREG r1, 0xC6667727; -CHECKREG r2, 0xC6667727; -CHECKREG r3, 0xC6667727; -CHECKREG r4, 0x456789AB; -CHECKREG r5, 0x6689ABCD; -CHECKREG r6, 0x47445555; -CHECKREG r7, 0x68667777; - -imm32 r0, 0x5537891b; -imm32 r1, 0x6759ab2d; -imm32 r2, 0x74555535; -imm32 r3, 0x86665747; -imm32 r4, 0x88789565; -imm32 r5, 0xaa8abb5b; -imm32 r6, 0xcc9cdd85; -imm32 r7, 0xeeaeff9f; -R0 = MAX ( R4 , R0 ); -R1 = MAX ( R4 , R1 ); -R2 = MAX ( R4 , R2 ); -R3 = MAX ( R4 , R3 ); -R4 = MAX ( R4 , R4 ); -R5 = MAX ( R4 , R5 ); -R6 = MAX ( R4 , R6 ); -R7 = MAX ( R4 , R7 ); -CHECKREG r0, 0x5537891B; -CHECKREG r1, 0x6759AB2D; -CHECKREG r2, 0x74555535; -CHECKREG r3, 0x88789565; -CHECKREG r4, 0x88789565; -CHECKREG r5, 0xAA8ABB5B; -CHECKREG r6, 0xCC9CDD85; -CHECKREG r7, 0xEEAEFF9F; - -imm32 r0, 0x556b89ab; -imm32 r1, 0x69764bcd; -imm32 r2, 0x79736564; -imm32 r3, 0x81278394; -imm32 r4, 0x98876439; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0xcccc1ddd; -imm32 r7, 0x12346fff; -R0 = MAX ( R5 , R0 ); -R1 = MAX ( R5 , R1 ); -R2 = MAX ( R5 , R2 ); -R3 = MAX ( R5 , R3 ); -R4 = MAX ( R5 , R4 ); -R5 = MAX ( R5 , R5 ); -R6 = MAX ( R5 , R6 ); -R7 = MAX ( R5 , R7 ); -CHECKREG r0, 0x556B89AB; -CHECKREG r1, 0x69764BCD; -CHECKREG r2, 0x79736564; -CHECKREG r3, 0xAAAA0BBB; -CHECKREG r4, 0xAAAA0BBB; -CHECKREG r5, 0xAAAA0BBB; -CHECKREG r6, 0xCCCC1DDD; -CHECKREG r7, 0x12346FFF; - -imm32 r0, 0xe56739ab; -imm32 r1, 0xf7694bcd; -imm32 r2, 0xa3456755; -imm32 r3, 0x66666777; -imm32 r4, 0x42345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R0 = MAX ( R6 , R0 ); -R1 = MAX ( R6 , R1 ); -R2 = MAX ( R6 , R2 ); -R3 = MAX ( R6 , R3 ); -R4 = MAX ( R6 , R4 ); -R5 = MAX ( R6 , R5 ); -R6 = MAX ( R6 , R6 ); -R7 = MAX ( R6 , R7 ); -CHECKREG r0, 0x043290D6; -CHECKREG r1, 0x043290D6; -CHECKREG r2, 0x043290D6; -CHECKREG r3, 0x66666777; -CHECKREG r4, 0x42345699; -CHECKREG r5, 0x45678B6B; -CHECKREG r6, 0x043290D6; -CHECKREG r7, 0x1234567F; - -imm32 r0, 0x576789ab; -imm32 r1, 0xd779abcd; -imm32 r2, 0x23456755; -imm32 r3, 0x56789007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0xf9ab1d7d; -imm32 r7, 0xabcd2ff7; -R0 = MAX ( R7 , R0 ); -R1 = MAX ( R7 , R1 ); -R2 = MAX ( R7 , R2 ); -R3 = MAX ( R7 , R3 ); -R4 = MAX ( R7 , R4 ); -R5 = MAX ( R7 , R5 ); -R6 = MAX ( R7 , R6 ); -R7 = MAX ( R7 , R7 ); -CHECKREG r0, 0x576789AB; -CHECKREG r1, 0xD779ABCD; -CHECKREG r2, 0x23456755; -CHECKREG r3, 0x56789007; -CHECKREG r4, 0x789AB799; -CHECKREG r5, 0xABCD2FF7; -CHECKREG r6, 0xF9AB1D7D; -CHECKREG r7, 0xABCD2FF7; -imm32 r0, 0xe56739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0xd3456755; -imm32 r3, 0x66666777; -imm32 r4, 0x12345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R4 = MAX ( R4 , R7 ); -R5 = MAX ( R5 , R5 ); -R2 = MAX ( R6 , R3 ); -R6 = MAX ( R0 , R4 ); -R0 = MAX ( R1 , R6 ); -R2 = MAX ( R2 , R1 ); -R1 = MAX ( R3 , R0 ); -R7 = MAX ( R7 , R4 ); -CHECKREG r0, 0x67694BCD; -CHECKREG r1, 0x67694BCD; -CHECKREG r2, 0x67694BCD; -CHECKREG r3, 0x66666777; -CHECKREG r4, 0x12345699; -CHECKREG r5, 0x45678B6B; -CHECKREG r6, 0x12345699; -CHECKREG r7, 0x12345699; - -imm32 r0, 0xd76789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0xe3456755; -imm32 r3, 0x56789007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcd2ff7; -R3 = MAX ( R4 , R0 ); -R5 = MAX ( R5 , R1 ); -R2 = MAX ( R2 , R2 ); -R7 = MAX ( R7 , R3 ); -R4 = MAX ( R3 , R4 ); -R0 = MAX ( R1 , R5 ); -R1 = MAX ( R0 , R6 ); -R6 = MAX ( R6 , R7 ); -CHECKREG r0, 0x6779ABCD; -CHECKREG r1, 0x6779ABCD; -CHECKREG r2, 0xE3456755; -CHECKREG r3, 0x789AB799; -CHECKREG r4, 0x789AB799; -CHECKREG r5, 0x6779ABCD; -CHECKREG r6, 0x789AB799; -CHECKREG r7, 0x789AB799; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_maxmax.s b/sim/testsuite/sim/bfin/c_dsp32alu_maxmax.s deleted file mode 100644 index 8e39d22..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_maxmax.s +++ /dev/null @@ -1,261 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_maxmax/c_dsp32alu_maxmax.dsp -// Spec Reference: dsp32alu dregs = max / max ( dregs, dregs) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x25678911; -imm32 r1, 0x2389ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0xe6657717; -imm32 r4, 0x5a67891b; -imm32 r5, 0x67b9ab1d; -imm32 r6, 0x744d5515; -imm32 r7, 0x8666c777; -R0 = MAX ( R0 , R0 ) (V); -R1 = MAX ( R0 , R1 ) (V); -R2 = MAX ( R0 , R2 ) (V); -R3 = MAX ( R0 , R3 ) (V); -R4 = MAX ( R0 , R4 ) (V); -R5 = MAX ( R0 , R5 ) (V); -R6 = MAX ( R0 , R6 ) (V); -R7 = MAX ( R0 , R7 ) (V); -CHECKREG r0, 0x25678911; -CHECKREG r1, 0x2567AB1D; -CHECKREG r2, 0x34445515; -CHECKREG r3, 0x25677717; -CHECKREG r4, 0x5A67891B; -CHECKREG r5, 0x67B9AB1D; -CHECKREG r6, 0x744D5515; -CHECKREG r7, 0x2567C777; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r4, 0xd8889929; -imm32 r5, 0xeaaabb2b; -imm32 r6, 0xfcccdd2d; -imm32 r7, 0x0eeeffff; -R0 = MAX ( R1 , R0 ) (V); -R1 = MAX ( R1 , R1 ) (V); -R2 = MAX ( R1 , R2 ) (V); -R3 = MAX ( R1 , R3 ) (V); -R4 = MAX ( R1 , R4 ) (V); -R5 = MAX ( R1 , R5 ) (V); -R6 = MAX ( R1 , R6 ) (V); -R7 = MAX ( R1 , R7 ) (V); -CHECKREG r0, 0xA789AB2D; -CHECKREG r1, 0xA789AB2D; -CHECKREG r2, 0xB4445525; -CHECKREG r3, 0xC6667727; -CHECKREG r4, 0xD888AB2D; -CHECKREG r5, 0xEAAABB2B; -CHECKREG r6, 0xFCCCDD2D; -CHECKREG r7, 0x0EEEFFFF; - -imm32 r0, 0x416789ab; -imm32 r1, 0x5289abcd; -imm32 r2, 0x63445555; -imm32 r3, 0xa7669777; -imm32 r4, 0x456789ab; -imm32 r5, 0xb689abcd; -imm32 r6, 0xd7445555; -imm32 r7, 0x68667777; -R0 = MAX ( R2 , R0 ) (V); -R1 = MAX ( R2 , R1 ) (V); -R2 = MAX ( R2 , R2 ) (V); -R3 = MAX ( R2 , R3 ) (V); -R4 = MAX ( R2 , R4 ) (V); -R5 = MAX ( R2 , R5 ) (V); -R6 = MAX ( R2 , R6 ) (V); -R7 = MAX ( R2 , R7 ) (V); -CHECKREG r0, 0x63445555; -CHECKREG r1, 0x63445555; -CHECKREG r2, 0x63445555; -CHECKREG r3, 0x63445555; -CHECKREG r4, 0x63445555; -CHECKREG r5, 0x63445555; -CHECKREG r6, 0x63445555; -CHECKREG r7, 0x68667777; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -R0 = MAX ( R3 , R0 ) (V); -R1 = MAX ( R3 , R1 ) (V); -R2 = MAX ( R3 , R2 ) (V); -R3 = MAX ( R3 , R3 ) (V); -R4 = MAX ( R3 , R4 ) (V); -R5 = MAX ( R3 , R5 ) (V); -R6 = MAX ( R3 , R6 ) (V); -R7 = MAX ( R3 , R7 ) (V); -CHECKREG r0, 0xC6667727; -CHECKREG r1, 0xC6667727; -CHECKREG r2, 0xC6667727; -CHECKREG r3, 0xC6667727; -CHECKREG r4, 0x63447727; -CHECKREG r5, 0x63447727; -CHECKREG r6, 0x63447727; -CHECKREG r7, 0x68667777; - -imm32 r0, 0x4537891b; -imm32 r1, 0x6759ab2d; -imm32 r2, 0x44555535; -imm32 r3, 0x66665747; -imm32 r4, 0x88789565; -imm32 r5, 0xaa8abb5b; -imm32 r6, 0xcc9cdd85; -imm32 r7, 0xeeaeff9f; -R0 = MAX ( R4 , R0 ) (V); -R1 = MAX ( R4 , R1 ) (V); -R2 = MAX ( R4 , R2 ) (V); -R3 = MAX ( R4 , R3 ) (V); -R4 = MAX ( R4 , R4 ) (V); -R5 = MAX ( R4 , R5 ) (V); -R6 = MAX ( R4 , R6 ) (V); -R7 = MAX ( R4 , R7 ) (V); -CHECKREG r0, 0x45379565; -CHECKREG r1, 0x6759AB2D; -CHECKREG r2, 0x44555535; -CHECKREG r3, 0x66665747; -CHECKREG r4, 0x88789565; -CHECKREG r5, 0xAA8ABB5B; -CHECKREG r6, 0xCC9CDD85; -CHECKREG r7, 0xEEAEFF9F; - -imm32 r0, 0xa56b89ab; -imm32 r1, 0x659b4bcd; -imm32 r2, 0xd9736564; -imm32 r3, 0x61278394; -imm32 r4, 0xb8876439; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0xcccc1ddd; -imm32 r7, 0x12346fff; -R0 = MAX ( R5 , R0 ) (V); -R1 = MAX ( R5 , R1 ) (V); -R2 = MAX ( R5 , R2 ) (V); -R3 = MAX ( R5 , R3 ) (V); -R4 = MAX ( R5 , R4 ) (V); -R5 = MAX ( R5 , R5 ) (V); -R6 = MAX ( R5 , R6 ) (V); -R7 = MAX ( R5 , R7 ) (V); -CHECKREG r0, 0xAAAA0BBB; -CHECKREG r1, 0x659B4BCD; -CHECKREG r2, 0xD9736564; -CHECKREG r3, 0x61270BBB; -CHECKREG r4, 0xB8876439; -CHECKREG r5, 0xAAAA0BBB; -CHECKREG r6, 0xCCCC1DDD; -CHECKREG r7, 0x12346FFF; - -imm32 r0, 0x956739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0xd3456755; -imm32 r3, 0x66666777; -imm32 r4, 0x12345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R0 = MAX ( R6 , R0 ) (V); -R1 = MAX ( R6 , R1 ) (V); -R2 = MAX ( R6 , R2 ) (V); -R3 = MAX ( R6 , R3 ) (V); -R4 = MAX ( R6 , R4 ) (V); -R5 = MAX ( R6 , R5 ) (V); -R6 = MAX ( R6 , R6 ) (V); -R7 = MAX ( R6 , R7 ) (V); -CHECKREG r0, 0x043239AB; -CHECKREG r1, 0x67694BCD; -CHECKREG r2, 0x04326755; -CHECKREG r3, 0x66666777; -CHECKREG r4, 0x12345699; -CHECKREG r5, 0x456790D6; -CHECKREG r6, 0x043290D6; -CHECKREG r7, 0x1234567F; - -imm32 r0, 0x876789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0xd3456755; -imm32 r3, 0x56789007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcd2ff7; -R0 = MAX ( R7 , R0 ) (V); -R1 = MAX ( R7 , R1 ) (V); -R2 = MAX ( R7 , R2 ) (V); -R3 = MAX ( R7 , R3 ) (V); -R4 = MAX ( R7 , R4 ) (V); -R5 = MAX ( R7 , R5 ) (V); -R6 = MAX ( R7 , R6 ) (V); -R7 = MAX ( R7 , R7 ) (V); -CHECKREG r0, 0xABCD2FF7; -CHECKREG r1, 0x67792FF7; -CHECKREG r2, 0xD3456755; -CHECKREG r3, 0x56782FF7; -CHECKREG r4, 0x789A2FF7; -CHECKREG r5, 0xABCD2FF7; -CHECKREG r6, 0xABCD2FF7; -CHECKREG r7, 0xABCD2FF7; -imm32 r0, 0x456739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0x03456755; -imm32 r3, 0x66666777; -imm32 r4, 0x12345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R4 = MAX ( R4 , R7 ) (V); -R5 = MAX ( R5 , R5 ) (V); -R2 = MAX ( R6 , R3 ) (V); -R6 = MAX ( R0 , R4 ) (V); -R0 = MAX ( R1 , R6 ) (V); -R2 = MAX ( R2 , R1 ) (V); -R1 = MAX ( R3 , R0 ) (V); -R7 = MAX ( R7 , R4 ) (V); -CHECKREG r0, 0x67695699; -CHECKREG r1, 0x67696777; -CHECKREG r2, 0x67696777; -CHECKREG r3, 0x66666777; -CHECKREG r4, 0x12345699; -CHECKREG r5, 0x45678B6B; -CHECKREG r6, 0x45675699; -CHECKREG r7, 0x12345699; - -imm32 r0, 0x876789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0x2345d755; -imm32 r3, 0x5678b007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcd2ff7; -R3 = MAX ( R4 , R0 ) (V); -R5 = MAX ( R5 , R1 ) (V); -R2 = MAX ( R2 , R2 ) (V); -R7 = MAX ( R7 , R3 ) (V); -R4 = MAX ( R3 , R4 ) (V); -R0 = MAX ( R1 , R5 ) (V); -R1 = MAX ( R0 , R6 ) (V); -R6 = MAX ( R6 , R7 ) (V); -CHECKREG r0, 0x67790BBB; -CHECKREG r1, 0x67791D7D; -CHECKREG r2, 0x2345D755; -CHECKREG r3, 0x789AB799; -CHECKREG r4, 0x789AB799; -CHECKREG r5, 0x67790BBB; -CHECKREG r6, 0x789A2FF7; -CHECKREG r7, 0x789A2FF7; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_min.s b/sim/testsuite/sim/bfin/c_dsp32alu_min.s deleted file mode 100644 index b36eaac..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_min.s +++ /dev/null @@ -1,261 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_min/c_dsp32alu_min.dsp -// Spec Reference: dsp32alu dregs = min ( dregs, dregs) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x35678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x74445515; -imm32 r3, 0xf6667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0 = MIN ( R0 , R0 ); -R1 = MIN ( R0 , R1 ); -R2 = MIN ( R0 , R2 ); -R3 = MIN ( R0 , R3 ); -R4 = MIN ( R0 , R4 ); -R5 = MIN ( R0 , R5 ); -R6 = MIN ( R0 , R6 ); -R7 = MIN ( R0 , R7 ); -CHECKREG r0, 0x35678911; -CHECKREG r1, 0x2789AB1D; -CHECKREG r2, 0x35678911; -CHECKREG r3, 0xF6667717; -CHECKREG r4, 0x35678911; -CHECKREG r5, 0x35678911; -CHECKREG r6, 0x35678911; -CHECKREG r7, 0x86667777; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r4, 0xd8889929; -imm32 r5, 0xeaaabb2b; -imm32 r6, 0xfcccdd2d; -imm32 r7, 0x0eeeffff; -R0 = MIN ( R1 , R0 ); -R1 = MIN ( R1 , R1 ); -R2 = MIN ( R1 , R2 ); -R3 = MIN ( R1 , R3 ); -R4 = MIN ( R1 , R4 ); -R5 = MIN ( R1 , R5 ); -R6 = MIN ( R1 , R6 ); -R7 = MIN ( R1 , R7 ); -CHECKREG r0, 0x9567892B; -CHECKREG r1, 0xA789AB2D; -CHECKREG r2, 0xA789AB2D; -CHECKREG r3, 0xA789AB2D; -CHECKREG r4, 0xA789AB2D; -CHECKREG r5, 0xA789AB2D; -CHECKREG r6, 0xA789AB2D; -CHECKREG r7, 0xA789AB2D; - -imm32 r0, 0x716789ab; -imm32 r1, 0x8289abcd; -imm32 r2, 0x93445555; -imm32 r3, 0xa4667777; -imm32 r4, 0x456789ab; -imm32 r5, 0xb689abcd; -imm32 r6, 0x47445555; -imm32 r7, 0x68667777; -R0 = MIN ( R2 , R0 ); -R1 = MIN ( R2 , R1 ); -R2 = MIN ( R2 , R2 ); -R3 = MIN ( R2 , R3 ); -R4 = MIN ( R2 , R4 ); -R5 = MIN ( R2 , R5 ); -R6 = MIN ( R2 , R6 ); -R7 = MIN ( R2 , R7 ); -CHECKREG r0, 0x93445555; -CHECKREG r1, 0x8289ABCD; -CHECKREG r2, 0x93445555; -CHECKREG r3, 0x93445555; -CHECKREG r4, 0x93445555; -CHECKREG r5, 0x93445555; -CHECKREG r6, 0x93445555; -CHECKREG r7, 0x93445555; - -imm32 r0, 0x2567892b; -imm32 r1, 0x5789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -R0 = MIN ( R3 , R0 ); -R1 = MIN ( R3 , R1 ); -R2 = MIN ( R3 , R2 ); -R3 = MIN ( R3 , R3 ); -R4 = MIN ( R3 , R4 ); -R5 = MIN ( R3 , R5 ); -R6 = MIN ( R3 , R6 ); -R7 = MIN ( R3 , R7 ); -CHECKREG r0, 0x9567892B; -CHECKREG r1, 0xA789AB2D; -CHECKREG r2, 0xB4445525; -CHECKREG r3, 0xC6667727; -CHECKREG r4, 0x93445555; -CHECKREG r5, 0x93445555; -CHECKREG r6, 0x93445555; -CHECKREG r7, 0x93445555; - -imm32 r0, 0xd537891b; -imm32 r1, 0x6759ab2d; -imm32 r2, 0xf455b535; -imm32 r3, 0x66665747; -imm32 r4, 0x88789565; -imm32 r5, 0xaa8abb5b; -imm32 r6, 0xcc9cdd85; -imm32 r7, 0xeeaeff9f; -R0 = MIN ( R4 , R0 ); -R1 = MIN ( R4 , R1 ); -R2 = MIN ( R4 , R2 ); -R3 = MIN ( R4 , R3 ); -R4 = MIN ( R4 , R4 ); -R5 = MIN ( R4 , R5 ); -R6 = MIN ( R4 , R6 ); -R7 = MIN ( R4 , R7 ); -CHECKREG r0, 0x88789565; -CHECKREG r1, 0x88789565; -CHECKREG r2, 0x88789565; -CHECKREG r3, 0x88789565; -CHECKREG r4, 0x88789565; -CHECKREG r5, 0x88789565; -CHECKREG r6, 0x88789565; -CHECKREG r7, 0x88789565; - -imm32 r0, 0xa56b89ab; -imm32 r1, 0x69764bcd; -imm32 r2, 0x49736564; -imm32 r3, 0x61278394; -imm32 r4, 0x98876439; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0xcccc1ddd; -imm32 r7, 0x12346fff; -R0 = MIN ( R5 , R0 ); -R1 = MIN ( R5 , R1 ); -R2 = MIN ( R5 , R2 ); -R3 = MIN ( R5 , R3 ); -R4 = MIN ( R5 , R4 ); -R5 = MIN ( R5 , R5 ); -R6 = MIN ( R5 , R6 ); -R7 = MIN ( R5 , R7 ); -CHECKREG r0, 0xA56B89AB; -CHECKREG r1, 0xAAAA0BBB; -CHECKREG r2, 0xAAAA0BBB; -CHECKREG r3, 0xAAAA0BBB; -CHECKREG r4, 0x98876439; -CHECKREG r5, 0xAAAA0BBB; -CHECKREG r6, 0xAAAA0BBB; -CHECKREG r7, 0xAAAA0BBB; - -imm32 r0, 0xe56739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0x03456755; -imm32 r3, 0x66666777; -imm32 r4, 0xd2345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R0 = MIN ( R6 , R0 ); -R1 = MIN ( R6 , R1 ); -R2 = MIN ( R6 , R2 ); -R3 = MIN ( R6 , R3 ); -R4 = MIN ( R6 , R4 ); -R5 = MIN ( R6 , R5 ); -R6 = MIN ( R6 , R6 ); -R7 = MIN ( R6 , R7 ); -CHECKREG r0, 0xE56739AB; -CHECKREG r1, 0x043290D6; -CHECKREG r2, 0x03456755; -CHECKREG r3, 0x043290D6; -CHECKREG r4, 0xD2345699; -CHECKREG r5, 0x043290D6; -CHECKREG r6, 0x043290D6; -CHECKREG r7, 0x043290D6; - -imm32 r0, 0x476789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0x23456755; -imm32 r3, 0x56789007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcd2ff7; -R0 = MIN ( R7 , R0 ); -R1 = MIN ( R7 , R1 ); -R2 = MIN ( R7 , R2 ); -R3 = MIN ( R7 , R3 ); -R4 = MIN ( R7 , R4 ); -R5 = MIN ( R7 , R5 ); -R6 = MIN ( R7 , R6 ); -R7 = MIN ( R7 , R7 ); -CHECKREG r0, 0xABCD2FF7; -CHECKREG r1, 0xABCD2FF7; -CHECKREG r2, 0xABCD2FF7; -CHECKREG r3, 0xABCD2FF7; -CHECKREG r4, 0xABCD2FF7; -CHECKREG r5, 0xAAAA0BBB; -CHECKREG r6, 0x89AB1D7D; -CHECKREG r7, 0xABCD2FF7; -imm32 r0, 0x456739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0xd3456755; -imm32 r3, 0x66666777; -imm32 r4, 0x12345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0xb43290d6; -imm32 r7, 0x1234567f; -R4 = MIN ( R4 , R7 ); -R5 = MIN ( R5 , R5 ); -R2 = MIN ( R6 , R3 ); -R6 = MIN ( R0 , R4 ); -R0 = MIN ( R1 , R6 ); -R2 = MIN ( R2 , R1 ); -R1 = MIN ( R3 , R0 ); -R7 = MIN ( R7 , R4 ); -CHECKREG r0, 0x1234567F; -CHECKREG r1, 0x1234567F; -CHECKREG r2, 0xB43290D6; -CHECKREG r3, 0x66666777; -CHECKREG r4, 0x1234567F; -CHECKREG r5, 0x45678B6B; -CHECKREG r6, 0x1234567F; -CHECKREG r7, 0x1234567F; - -imm32 r0, 0xa76789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0xf3456755; -imm32 r3, 0x56789007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcd2ff7; -R3 = MIN ( R4 , R0 ); -R5 = MIN ( R5 , R1 ); -R2 = MIN ( R2 , R2 ); -R7 = MIN ( R7 , R3 ); -R4 = MIN ( R3 , R4 ); -R0 = MIN ( R1 , R5 ); -R1 = MIN ( R0 , R6 ); -R6 = MIN ( R6 , R7 ); -CHECKREG r0, 0xAAAA0BBB; -CHECKREG r1, 0x89AB1D7D; -CHECKREG r2, 0xF3456755; -CHECKREG r3, 0xA76789AB; -CHECKREG r4, 0xA76789AB; -CHECKREG r5, 0xAAAA0BBB; -CHECKREG r6, 0x89AB1D7D; -CHECKREG r7, 0xA76789AB; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_minmin.s b/sim/testsuite/sim/bfin/c_dsp32alu_minmin.s deleted file mode 100644 index 4106245..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_minmin.s +++ /dev/null @@ -1,261 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_minmin/c_dsp32alu_minmin.dsp -// Spec Reference: dsp32alu dregs = min / min ( dregs, dregs) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x25678911; -imm32 r1, 0x2389ab1d; -imm32 r2, 0x2a445345; -imm32 r3, 0x46657717; -imm32 r4, 0xd567e91b; -imm32 r5, 0x6789af1d; -imm32 r6, 0x74445d85; -imm32 r7, 0x8666a779; -R0 = MIN ( R0 , R0 ) (V); -R1 = MIN ( R0 , R1 ) (V); -R2 = MIN ( R0 , R2 ) (V); -R3 = MIN ( R0 , R3 ) (V); -R4 = MIN ( R0 , R4 ) (V); -R5 = MIN ( R0 , R5 ) (V); -R6 = MIN ( R0 , R6 ) (V); -R7 = MIN ( R0 , R7 ) (V); -CHECKREG r0, 0x25678911; -CHECKREG r1, 0x23898911; -CHECKREG r2, 0x25678911; -CHECKREG r3, 0x25678911; -CHECKREG r4, 0xD5678911; -CHECKREG r5, 0x25678911; -CHECKREG r6, 0x25678911; -CHECKREG r7, 0x86668911; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r4, 0xd8889929; -imm32 r5, 0xeaaabb2b; -imm32 r6, 0xfcccdd2d; -imm32 r7, 0x0eeeffff; -R0 = MIN ( R1 , R0 ) (V); -R1 = MIN ( R1 , R1 ) (V); -R2 = MIN ( R1 , R2 ) (V); -R3 = MIN ( R1 , R3 ) (V); -R4 = MIN ( R1 , R4 ) (V); -R5 = MIN ( R1 , R5 ) (V); -R6 = MIN ( R1 , R6 ) (V); -R7 = MIN ( R1 , R7 ) (V); -CHECKREG r0, 0x9567892B; -CHECKREG r1, 0xA789AB2D; -CHECKREG r2, 0xA789AB2D; -CHECKREG r3, 0xA789AB2D; -CHECKREG r4, 0xA7899929; -CHECKREG r5, 0xA789AB2D; -CHECKREG r6, 0xA789AB2D; -CHECKREG r7, 0xA789AB2D; - -imm32 r0, 0x416789ab; -imm32 r1, 0x5289abcd; -imm32 r2, 0x43445555; -imm32 r3, 0xa466a777; -imm32 r4, 0x45678dab; -imm32 r5, 0xf689abcd; -imm32 r6, 0x47445555; -imm32 r7, 0x68667777; -R0 = MIN ( R2 , R0 ) (V); -R1 = MIN ( R2 , R1 ) (V); -R2 = MIN ( R2 , R2 ) (V); -R3 = MIN ( R2 , R3 ) (V); -R4 = MIN ( R2 , R4 ) (V); -R5 = MIN ( R2 , R5 ) (V); -R6 = MIN ( R2 , R6 ) (V); -R7 = MIN ( R2 , R7 ) (V); -CHECKREG r0, 0x416789AB; -CHECKREG r1, 0x4344ABCD; -CHECKREG r2, 0x43445555; -CHECKREG r3, 0xA466A777; -CHECKREG r4, 0x43448DAB; -CHECKREG r5, 0xF689ABCD; -CHECKREG r6, 0x43445555; -CHECKREG r7, 0x43445555; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -R0 = MIN ( R3 , R0 ) (V); -R1 = MIN ( R3 , R1 ) (V); -R2 = MIN ( R3 , R2 ) (V); -R3 = MIN ( R3 , R3 ) (V); -R4 = MIN ( R3 , R4 ) (V); -R5 = MIN ( R3 , R5 ) (V); -R6 = MIN ( R3 , R6 ) (V); -R7 = MIN ( R3 , R7 ) (V); -CHECKREG r0, 0x9567892B; -CHECKREG r1, 0xA789AB2D; -CHECKREG r2, 0xB4445525; -CHECKREG r3, 0xC6667727; -CHECKREG r4, 0xC6668DAB; -CHECKREG r5, 0xC666ABCD; -CHECKREG r6, 0xC6665555; -CHECKREG r7, 0xC6665555; - -imm32 r0, 0x5537891b; -imm32 r1, 0x6759ab2d; -imm32 r2, 0x74555535; -imm32 r3, 0x86665747; -imm32 r4, 0x98789565; -imm32 r5, 0xaa8abb5b; -imm32 r6, 0xcc9cdd85; -imm32 r7, 0xeeaeff9f; -R0 = MIN ( R4 , R0 ) (V); -R1 = MIN ( R4 , R1 ) (V); -R2 = MIN ( R4 , R2 ) (V); -R3 = MIN ( R4 , R3 ) (V); -R4 = MIN ( R4 , R4 ) (V); -R5 = MIN ( R4 , R5 ) (V); -R6 = MIN ( R4 , R6 ) (V); -R7 = MIN ( R4 , R7 ) (V); -CHECKREG r0, 0x9878891B; -CHECKREG r1, 0x98789565; -CHECKREG r2, 0x98789565; -CHECKREG r3, 0x86669565; -CHECKREG r4, 0x98789565; -CHECKREG r5, 0x98789565; -CHECKREG r6, 0x98789565; -CHECKREG r7, 0x98789565; - -imm32 r0, 0x256b89ab; -imm32 r1, 0x64764bcd; -imm32 r2, 0x49736564; -imm32 r3, 0x61278394; -imm32 r4, 0x98876439; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0xcccc1ddd; -imm32 r7, 0x43346fff; -R0 = MIN ( R5 , R0 ) (V); -R1 = MIN ( R5 , R1 ) (V); -R2 = MIN ( R5 , R2 ) (V); -R3 = MIN ( R5 , R3 ) (V); -R4 = MIN ( R5 , R4 ) (V); -R5 = MIN ( R5 , R5 ) (V); -R6 = MIN ( R5 , R6 ) (V); -R7 = MIN ( R5 , R7 ) (V); -CHECKREG r0, 0xAAAA89AB; -CHECKREG r1, 0xAAAA0BBB; -CHECKREG r2, 0xAAAA0BBB; -CHECKREG r3, 0xAAAA8394; -CHECKREG r4, 0x98870BBB; -CHECKREG r5, 0xAAAA0BBB; -CHECKREG r6, 0xAAAA0BBB; -CHECKREG r7, 0xAAAA0BBB; - -imm32 r0, 0x456739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0x03456755; -imm32 r3, 0x66666777; -imm32 r4, 0x12345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R0 = MIN ( R6 , R0 ) (V); -R1 = MIN ( R6 , R1 ) (V); -R2 = MIN ( R6 , R2 ) (V); -R3 = MIN ( R6 , R3 ) (V); -R4 = MIN ( R6 , R4 ) (V); -R5 = MIN ( R6 , R5 ) (V); -R6 = MIN ( R6 , R6 ) (V); -R7 = MIN ( R6 , R7 ) (V); -CHECKREG r0, 0x043290D6; -CHECKREG r1, 0x043290D6; -CHECKREG r2, 0x034590D6; -CHECKREG r3, 0x043290D6; -CHECKREG r4, 0x043290D6; -CHECKREG r5, 0x04328B6B; -CHECKREG r6, 0x043290D6; -CHECKREG r7, 0x043290D6; - -imm32 r0, 0x976789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0x8345a755; -imm32 r3, 0x5678b007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcd2ff7; -R0 = MIN ( R7 , R0 ) (V); -R1 = MIN ( R7 , R1 ) (V); -R2 = MIN ( R7 , R2 ) (V); -R3 = MIN ( R7 , R3 ) (V); -R4 = MIN ( R7 , R4 ) (V); -R5 = MIN ( R7 , R5 ) (V); -R6 = MIN ( R7 , R6 ) (V); -R7 = MIN ( R7 , R7 ) (V); -CHECKREG r0, 0x976789AB; -CHECKREG r1, 0xABCDABCD; -CHECKREG r2, 0x8345A755; -CHECKREG r3, 0xABCDB007; -CHECKREG r4, 0xABCDB799; -CHECKREG r5, 0xAAAA0BBB; -CHECKREG r6, 0x89AB1D7D; -CHECKREG r7, 0xABCD2FF7; -imm32 r0, 0x456739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0x03456755; -imm32 r3, 0x66666777; -imm32 r4, 0x12345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R4 = MIN ( R4 , R7 ) (V); -R5 = MIN ( R5 , R5 ) (V); -R2 = MIN ( R6 , R3 ) (V); -R6 = MIN ( R0 , R4 ) (V); -R0 = MIN ( R1 , R6 ) (V); -R2 = MIN ( R2 , R1 ) (V); -R1 = MIN ( R3 , R0 ) (V); -R7 = MIN ( R7 , R4 ) (V); -CHECKREG r0, 0x123439AB; -CHECKREG r1, 0x123439AB; -CHECKREG r2, 0x043290D6; -CHECKREG r3, 0x66666777; -CHECKREG r4, 0x1234567F; -CHECKREG r5, 0x45678B6B; -CHECKREG r6, 0x123439AB; -CHECKREG r7, 0x1234567F; - -imm32 r0, 0xa76789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0xb3456755; -imm32 r3, 0x5678d007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcd2ff7; -R3 = MIN ( R4 , R0 ) (V); -R5 = MIN ( R5 , R1 ) (V); -R2 = MIN ( R2 , R2 ) (V); -R7 = MIN ( R7 , R3 ) (V); -R4 = MIN ( R3 , R4 ) (V); -R0 = MIN ( R1 , R5 ) (V); -R1 = MIN ( R0 , R6 ) (V); -R6 = MIN ( R6 , R7 ) (V); -CHECKREG r0, 0xAAAAABCD; -CHECKREG r1, 0x89ABABCD; -CHECKREG r2, 0xB3456755; -CHECKREG r3, 0xA76789AB; -CHECKREG r4, 0xA76789AB; -CHECKREG r5, 0xAAAAABCD; -CHECKREG r6, 0x89AB89AB; -CHECKREG r7, 0xA76789AB; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_mix.s b/sim/testsuite/sim/bfin/c_dsp32alu_mix.s deleted file mode 100644 index e54523c..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_mix.s +++ /dev/null @@ -1,137 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_mix/c_dsp32alu_mix.dsp -// Spec Reference: dsp32alu mix -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - -// ALU operations include parallel addition, subtraction, MAX, MIN, ABS on 16-bit -// and 32-bit data. If an operation use a single ALU only, it uses ALU0. - - imm32 r2, 0x44445555; - imm32 r3, 0x66667777; - imm32 r4, 0x88889999; - imm32 r5, 0xaaaabbbb; - imm32 r6, 0xccccdddd; - imm32 r7, 0xeeeeffff; - - imm32 r0, 0x456789ab; - imm32 r1, 0x6789abcd; -// Use only single ALU (ALU0 only), with saturation (S) - R2 = R1 + R0 (NS); /* 0xACF13578 */ - R3 = R2 + R0 (NS); /* 0xACF13578 */ - CHECKREG r2, 0xACF13578; - CHECKREG r3, 0xF258BF23; - R2 = R1 + R0 (S); /* 0x7FFFFFFF */ - R3 = R1 - R0 (NS); /* 0x22222222 */ - R4.L = R1.L + R0.L (NS); /* 0x88883578 */ - R5.L = R1.L + R0.H (NS); /* 0xAAAAF134 */ - R6.L = R1.H + R0.L (NS); /* 0xCCCCF134 */ - R7.L = R1.H + R0.H (NS); /* 0xEEEEACF0 */ - CHECKREG r2, 0x7FFFFFFF; - CHECKREG r3, 0x22222222; - CHECKREG r4, 0x88883578; - CHECKREG r5, 0xAAAAF134; - CHECKREG r6, 0xCCCCF134; - CHECKREG r7, 0xEEEEACF0; - - R4.H = R1.L + R0.L (S); /* 0x80003578 */ - R5.H = R1.L + R0.H (S); /* 0xF134F134 */ - R6.H = R1.H + R0.L (S); /* 0xF134F134 */ - CHECKREG r4, 0x80003578; - CHECKREG r5, 0xF134F134; - CHECKREG r6, 0xF134F134; - - R4.H = R1.L + R0.L (S); /* 0x80003578 */ - R5.H = R1.L + R0.H (S); /* 0xF134F134 */ - R6.H = R1.H + R0.L (S); /* 0xF134F134 */ - CHECKREG r4, 0x80003578; /* 0x */ - CHECKREG r5, 0xF134F134; /* 0x */ - CHECKREG r6, 0xF134F134; /* 0x */ - - R4.H = R1.L + R0.L (S); /* 0x80003578 */ - R5.H = R1.L + R0.H (S); /* 0xF134F134 */ - R6.H = R1.H + R0.L (S); /* 0xF134F134 */ - R7.H = R1.H + R0.H (S); /* 0x7FFFACF0 */ - CHECKREG r4, 0x80003578; /* 0x */ - CHECKREG r5, 0xF134F134; /* 0x */ - CHECKREG r6, 0xF134F134; /* 0x */ - CHECKREG r7, 0x7FFFACF0; /* 0x */ - -// Dual - R2 = R0 +|+ R1 (SCO); /* 0x80007FFF */ - R3 = R0 +|- R1 (S); /* 0x7FFFDDDE */ - R4 = R0 -|+ R1 (SCO); /* 0x8000DDDE)*/ - R5 = R0 -|- R1 (SCO); /* 0xDDDEDDDE */ - CHECKREG r2, 0x80007FFF; - CHECKREG r3, 0x7FFFDDDE; - CHECKREG r4, 0x8000DDDE; - CHECKREG r5, 0xDDDEDDDE; - R2 = R0 +|+ R1, R3 = R0 -|- R1 (SCO); /* 0x */ -CHECKREG r2, 0x7FFF8000; - R4 = R0 +|- R1 , R5 = R0 -|+ R1 (CO); /* 0x */ - R6 = R0 + R1, R7 = R0 - R1 (S); /* 0x */ - CHECKREG r2, 0x7FFF8000; - CHECKREG r3, 0xDDDEDDDE; - CHECKREG r4, 0xACF0DDDE; - CHECKREG r5, 0x3578DDDE; - CHECKREG r6, 0x7FFFFFFF; - CHECKREG r7, 0xDDDDDDDE; - -// Max min abs types - R3 = MAX ( R0 , R1 ); /* 0x6789ABCD */ - R4 = MIN ( R0 , R1 ); /* 0x456789AB */ - R5 = ABS R0; /* 0x456789AB */ - CHECKREG r3, 0x6789ABCD; - CHECKREG r4, 0x456789AB; - CHECKREG r5, 0x456789AB; - R3 = MAX ( R0 , R1 ) (V); /* 0x6789ABCD */ - R4 = MIN ( R0 , R1 ) (V); /* 0x456789AB */ - R5 = ABS R0 (V); /* 0x45677655 */ - CHECKREG r3, 0x6789ABCD; - CHECKREG r4, 0x456789AB; - CHECKREG r5, 0x45677655; - -// RND types - R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L; - R3.L = R0 + R1 (RND12); /* 0x */ - R4.H = R0 - R1 (RND12); /* 0x */ - R5.L = R0 + R1 (RND20); /* 0x */ - R6.H = R0 - R1 (RND20); /* 0x */ - R7.H = R1 (RND); /* 0x */ - CHECKREG r2, 0xBBBCBBBC; - CHECKREG r3, 0x67897FFF; - CHECKREG r4, 0x800089AB; - CHECKREG r5, 0x45670ACF; - CHECKREG r6, 0xFDDEFFFF; - CHECKREG r7, 0x678ADDDE; - - R7 = - R0 (V); /* 0x */ - CHECKREG r7, 0xBA997655; -// A0 & A1 types - A0 = 0; - A1 = 0; - A0.L = R0.L; - A0.H = R0.H; - A0 = A1; - A0.x = R0.L; - A1.x = R0.L; - R2.L = A0.x; /* 0x */ - R3.L = A1.x; /* 0x */ - R4 = ( A0 += A1 ); /* 0x */ - R5.L = ( A0 += A1 ); /* 0x */ - R5.H = ( A0 += A1 ); /* 0x */ - CHECKREG r2, 0xBBBCffAB; /* 0x */ - CHECKREG r3, 0x6789ffAB; /* 0x */ - CHECKREG r4, 0x80000000; /* 0x */ - CHECKREG r5, 0x80008000; /* 0x */ - A0 += A1; - A0 -= A1; - R6 = A1.L + A1.H, R7 = A0.L + A0.H; /* 0x */ - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000000; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_r_lh_a0pa1.s b/sim/testsuite/sim/bfin/c_dsp32alu_r_lh_a0pa1.s deleted file mode 100644 index 931662b..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_r_lh_a0pa1.s +++ /dev/null @@ -1,75 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_r_lh_a0pa1/c_dsp32alu_r_lh_a0pa1.dsp -// Spec Reference: dsp32alu r(lh) = ( a0 += a1) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x15678911; -imm32 r1, 0x0125ab2d; -imm32 r2, 0x04445535; -imm32 r3, 0x00567747; -imm32 r4, 0x0566895b; -imm32 r5, 0x07897b6d; -imm32 r6, 0x04445875; -imm32 r7, 0x06667797; -A0 = R0; -A1 = R1; -R0 = ( A0 += A1 ); -R1 = ( A0 += A1 ); -R2 = ( A0 += A1 ); -R3 = ( A0 += A1 ); -R4 = ( A0 += A1 ); -R5 = ( A0 += A1 ); -R6 = ( A0 += A1 ); -R7 = ( A0 += A1 ); -CHECKREG r0, 0x168D343E; -CHECKREG r1, 0x17B2DF6B; -CHECKREG r2, 0x18D88A98; -CHECKREG r3, 0x19FE35C5; -CHECKREG r4, 0x1B23E0F2; -CHECKREG r5, 0x1C498C1F; -CHECKREG r6, 0x1D6F374C; -CHECKREG r7, 0x1E94E279; - -imm32 r0, 0x068D343E; -imm32 r1, 0x02B2DF6B; -imm32 r2, 0x48388A98; -imm32 r3, 0x59F435C5; -imm32 r4, 0x6B25E0F2; -imm32 r5, 0x7C496C1F; -imm32 r6, 0x886F374C; -imm32 r7, 0x9E94E279; -A0 = R0; -A1 = R1; -R0.L = ( A0 += A1 ); -R0.H = ( A0 += A1 ); -R1.L = ( A0 += A1 ); -R1.H = ( A0 += A1 ); -R2.L = ( A0 += A1 ); -R2.H = ( A0 += A1 ); -R3.L = ( A0 += A1 ); -R3.H = ( A0 += A1 ); -R4.L = ( A0 += A1 ); -R4.H = ( A0 += A1 ); -R5.L = ( A0 += A1 ); -R5.H = ( A0 += A1 ); -R6.L = ( A0 += A1 ); -R6.H = ( A0 += A1 ); -R7.L = ( A0 += A1 ); -R7.H = ( A0 += A1 ); -CHECKREG r0, 0x0BF30940; -CHECKREG r1, 0x11590EA6; -CHECKREG r2, 0x16BE140C; -CHECKREG r3, 0x1C241971; -CHECKREG r4, 0x218A1ED7; -CHECKREG r5, 0x26F0243D; -CHECKREG r6, 0x2C5529A3; -CHECKREG r7, 0x31BB2F08; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_r_negneg.s b/sim/testsuite/sim/bfin/c_dsp32alu_r_negneg.s deleted file mode 100644 index 9c9d60c..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_r_negneg.s +++ /dev/null @@ -1,88 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_r_negneg/c_dsp32alu_r_negneg.dsp -// Spec Reference: dsp32alu dregs = neg / neg dregs -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0xa5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3b44b515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0 = - R0 (V); -R1 = - R1 (V); -R2 = - R2 (V); -R3 = - R3 (V); -R4 = - R4 (V); -R5 = - R5 (V); -R6 = - R6 (V); -R7 = - R7 (V); -CHECKREG r0, 0x5A9976EF; -CHECKREG r1, 0xD87754E3; -CHECKREG r2, 0xC4BC4AEB; -CHECKREG r3, 0xB99A88E9; -CHECKREG r4, 0xAA9976E5; -CHECKREG r5, 0x987754E3; -CHECKREG r6, 0x8BBCAAEB; -CHECKREG r7, 0x799A8889; - -imm32 r0, 0xa567892b; -imm32 r1, 0x2789ab2d; -imm32 r2, 0x344d5525; -imm32 r3, 0xd6667727; -imm32 r4, 0x58889929; -imm32 r5, 0x6aaabb2b; -imm32 r6, 0x7ccfdd2d; -imm32 r7, 0x8eeeffff; -R1 = - R0 (V); -R2 = - R1 (V); -R3 = - R2 (V); -R4 = - R3 (V); -R5 = - R4 (V); -R6 = - R5 (V); -R7 = - R6 (V); -R0 = - R7 (V); -CHECKREG r0, 0xA567892B; -CHECKREG r1, 0x5A9976D5; -CHECKREG r2, 0xA567892B; -CHECKREG r3, 0x5A9976D5; -CHECKREG r4, 0xA567892B; -CHECKREG r5, 0x5A9976D5; -CHECKREG r6, 0xA567892B; -CHECKREG r7, 0x5A9976D5; - -imm32 r0, 0xb5678941; -imm32 r1, 0x2789ab5d; -imm32 r2, 0x34445565; -imm32 r3, 0xe6667777; -imm32 r4, 0x5567898b; -imm32 r5, 0x6789ab9d; -imm32 r6, 0xc4445505; -imm32 r7, 0x8666b777; -R2 = - R0 (V); -R3 = - R1 (V); -R4 = - R2 (V); -R5 = - R3 (V); -R6 = - R4 (V); -R7 = - R5 (V); -R0 = - R6 (V); -R1 = - R7 (V); -CHECKREG r0, 0xB5678941; -CHECKREG r1, 0x2789AB5D; -CHECKREG r2, 0x4A9976BF; -CHECKREG r3, 0xD87754A3; -CHECKREG r4, 0xB5678941; -CHECKREG r5, 0x2789AB5D; -CHECKREG r6, 0x4A9976BF; -CHECKREG r7, 0xD87754A3; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rh_m.s b/sim/testsuite/sim/bfin/c_dsp32alu_rh_m.s deleted file mode 100644 index ba4dfa3..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rh_m.s +++ /dev/null @@ -1,263 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rh_m/c_dsp32alu_rh_m.dsp -// Spec Reference: dsp32alu dreg (half) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x89678911; -imm32 r1, 0x2189ab1d; -imm32 r2, 0x34145515; -imm32 r3, 0x46617717; -imm32 r4, 0x5678191b; -imm32 r5, 0x6789a11d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667771; -R0.H = R0.L - R0.L (NS); -R1.H = R0.L - R1.H (NS); -R2.H = R0.H - R2.L (NS); -R3.H = R0.H - R3.H (NS); -R4.H = R0.L - R4.L (NS); -R5.H = R0.L - R5.H (NS); -R6.H = R0.H - R6.L (NS); -R7.H = R0.H - R7.H (NS); -CHECKREG r4, 0x6FF6191B; -CHECKREG r5, 0x2188A11D; -CHECKREG r6, 0xAAEB5515; -CHECKREG r7, 0x799A7771; -CHECKREG r4, 0x6FF6191B; -CHECKREG r5, 0x2188A11D; -CHECKREG r6, 0xAAEB5515; -CHECKREG r7, 0x799A7771; - -imm32 r0, 0x25678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x38445515; -imm32 r3, 0x468a7717; -imm32 r4, 0x5678e91b; -imm32 r5, 0x6789af1d; -imm32 r6, 0x744455f5; -imm32 r7, 0x8666777f; -R0.H = R1.L - R0.L (NS); -R1.H = R1.L - R1.H (NS); -R2.H = R1.H - R2.L (NS); -R3.H = R1.H - R3.H (NS); -R4.H = R1.L - R4.L (NS); -R5.H = R1.L - R5.H (NS); -R6.H = R1.H - R6.L (NS); -R7.H = R1.H - R7.H (NS); -CHECKREG r4, 0xC202E91B; -CHECKREG r5, 0x4394AF1D; -CHECKREG r6, 0x2D9F55F5; -CHECKREG r7, 0xFD2E777F; -CHECKREG r4, 0xC202E91B; -CHECKREG r5, 0x4394AF1D; -CHECKREG r6, 0x2D9F55F5; -CHECKREG r7, 0xFD2E777F; - -imm32 r0, 0x78678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34885515; -imm32 r3, 0x466aa717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789aa1d; -imm32 r6, 0x74445aa5; -imm32 r7, 0x866677a7; -R0.H = R2.L - R0.L (NS); -R1.H = R2.L - R1.H (NS); -R2.H = R2.H - R2.L (NS); -R3.H = R2.H - R3.H (NS); -R4.H = R2.L - R4.L (NS); -R5.H = R2.L - R5.H (NS); -R6.H = R2.H - R6.L (NS); -R7.H = R2.H - R7.H (NS); -CHECKREG r4, 0xCBFA891B; -CHECKREG r5, 0xED8CAA1D; -CHECKREG r6, 0x84CE5AA5; -CHECKREG r7, 0x590D77A7; -CHECKREG r4, 0xCBFA891B; -CHECKREG r5, 0xED8CAA1D; -CHECKREG r6, 0x84CE5AA5; -CHECKREG r7, 0x590D77A7; - -imm32 r0, 0xb5678911; -imm32 r1, 0xb789ab1d; -imm32 r2, 0x3b445515; -imm32 r3, 0x46b67717; -imm32 r4, 0x567b891b; -imm32 r5, 0x6789bb1d; -imm32 r6, 0x74445b15; -imm32 r7, 0x866677b7; -R0.H = R3.L - R0.L (NS); -R1.H = R3.L - R1.H (NS); -R2.H = R3.H - R2.L (NS); -R3.H = R3.H - R3.H (NS); -R4.H = R3.L - R4.L (NS); -R5.H = R3.L - R5.H (NS); -R6.H = R3.H - R6.L (NS); -R7.H = R3.H - R7.H (NS); -CHECKREG r4, 0xEDFC891B; -CHECKREG r5, 0x0F8EBB1D; -CHECKREG r6, 0xA4EB5B15; -CHECKREG r7, 0x799A77B7; -CHECKREG r4, 0xEDFC891B; -CHECKREG r5, 0x0F8EBB1D; -CHECKREG r6, 0xA4EB5B15; -CHECKREG r7, 0x799A77B7; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.H = R4.L - R0.L (NS); -R1.H = R4.L - R1.H (NS); -R2.H = R4.H - R2.L (NS); -R3.H = R4.H - R3.H (NS); -R4.H = R4.L - R4.L (NS); -R5.H = R4.L - R5.H (NS); -R6.H = R4.H - R6.L (NS); -R7.H = R4.H - R7.H (NS); -CHECKREG r4, 0x0000891B; -CHECKREG r5, 0x2192AB1D; -CHECKREG r6, 0xAAEB5515; -CHECKREG r7, 0x799A7777; -CHECKREG r4, 0x0000891B; -CHECKREG r5, 0x2192AB1D; -CHECKREG r6, 0xAAEB5515; -CHECKREG r7, 0x799A7777; - -imm32 r0, 0xcc678911; -imm32 r1, 0xc789ab1d; -imm32 r2, 0x3c445515; -imm32 r3, 0x46c67717; -imm32 r4, 0x567c891b; -imm32 r5, 0x6789cb1d; -imm32 r6, 0x74445c15; -imm32 r7, 0x866677c7; -R0.H = R5.L - R0.L (NS); -R1.H = R5.L - R1.H (NS); -R2.H = R5.H - R2.L (NS); -R3.H = R5.H - R3.H (NS); -R4.H = R5.L - R4.L (NS); -R5.H = R5.L - R5.H (NS); -R6.H = R5.H - R6.L (NS); -R7.H = R5.H - R7.H (NS); -CHECKREG r4, 0x4202891B; -CHECKREG r5, 0x6394CB1D; -CHECKREG r6, 0x077F5C15; -CHECKREG r7, 0xDD2E77C7; -CHECKREG r4, 0x4202891B; -CHECKREG r5, 0x6394CB1D; -CHECKREG r6, 0x077F5C15; -CHECKREG r7, 0xDD2E77C7; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.H = R6.L - R0.L (NS); -R1.H = R6.L - R1.H (NS); -R2.H = R6.H - R2.L (NS); -R3.H = R6.H - R3.H (NS); -R4.H = R6.L - R4.L (NS); -R5.H = R6.L - R5.H (NS); -R6.H = R6.H - R6.L (NS); -R7.H = R6.H - R7.H (NS); -CHECKREG r4, 0xCBFA891B; -CHECKREG r5, 0xED8CAB1D; -CHECKREG r6, 0x1F2F5515; -CHECKREG r7, 0x98C97777; -CHECKREG r4, 0xCBFA891B; -CHECKREG r5, 0xED8CAB1D; -CHECKREG r6, 0x1F2F5515; -CHECKREG r7, 0x98C97777; - -imm32 r0, 0xd5678911; -imm32 r1, 0x2e89ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667e17; -imm32 r4, 0x56e8891b; -imm32 r5, 0x678eab1d; -imm32 r6, 0x7444e515; -imm32 r7, 0x86667e77; -R0.H = R7.L - R0.L (NS); -R1.H = R7.L - R1.H (NS); -R2.H = R7.H - R2.L (NS); -R3.H = R7.H - R3.H (NS); -R4.H = R7.L - R4.L (NS); -R5.H = R7.L - R5.H (NS); -R6.H = R7.H - R6.L (NS); -R7.H = R7.H - R7.H (NS); -CHECKREG r4, 0xF55C891B; -CHECKREG r5, 0x16E9AB1D; -CHECKREG r6, 0xA151E515; -CHECKREG r7, 0x00007E77; -CHECKREG r4, 0xF55C891B; -CHECKREG r5, 0x16E9AB1D; -CHECKREG r6, 0xA151E515; -CHECKREG r7, 0x00007E77; - -imm32 r0, 0xff678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34ff5515; -imm32 r3, 0x4666f717; -imm32 r4, 0x567f891b; -imm32 r5, 0x6789fb1d; -imm32 r6, 0x74445f15; -imm32 r7, 0x866677f7; -R6.H = R2.L - R3.L (S); -R1.H = R4.L - R5.H (S); -R5.H = R7.H - R2.L (S); -R3.H = R0.H - R0.H (S); -R0.H = R3.L - R4.L (S); -R2.H = R5.L - R7.H (S); -R7.H = R6.H - R7.L (S); -R4.H = R1.H - R6.H (S); -CHECKREG r4, 0x8000891B; -CHECKREG r5, 0x8000FB1D; -CHECKREG r6, 0x5DFE5F15; -CHECKREG r7, 0xE60777F7; -CHECKREG r4, 0x8000891B; -CHECKREG r5, 0x8000FB1D; -CHECKREG r6, 0x5DFE5F15; -CHECKREG r7, 0xE60777F7; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R3.H = R4.L - R0.L (S); -R1.H = R6.L - R3.H (S); -R4.H = R3.H - R2.L (S); -R6.H = R7.H - R1.H (S); -R2.H = R5.L - R4.L (S); -R7.H = R2.L - R7.H (S); -R0.H = R1.H - R6.L (S); -R5.H = R0.H - R5.H (S); -CHECKREG r4, 0xAAF5891B; -CHECKREG r5, 0x986DAB1D; -CHECKREG r6, 0x80005515; -CHECKREG r7, 0x7FFF7777; -CHECKREG r4, 0xAAF5891B; -CHECKREG r5, 0x986DAB1D; -CHECKREG r6, 0x80005515; -CHECKREG r7, 0x7FFF7777; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rh_p.s b/sim/testsuite/sim/bfin/c_dsp32alu_rh_p.s deleted file mode 100644 index fb7d3fa..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rh_p.s +++ /dev/null @@ -1,263 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rh_p/c_dsp32alu_rh_p.dsp -// Spec Reference: dsp32alu dreg (half) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x34678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34645515; -imm32 r3, 0x46667717; -imm32 r4, 0xd678891b; -imm32 r5, 0x6e89ab1d; -imm32 r6, 0x74b45515; -imm32 r7, 0x866cc777; -R0.H = R0.L + R0.L (NS); -R1.H = R0.L + R1.H (NS); -R2.H = R0.H + R2.L (NS); -R3.H = R0.H + R3.H (NS); -R4.H = R0.L + R4.L (NS); -R5.H = R0.L + R5.H (NS); -R6.H = R0.H + R6.L (NS); -R7.H = R0.H + R7.H (NS); -CHECKREG r4, 0x122C891B; -CHECKREG r5, 0xF79AAB1D; -CHECKREG r6, 0x67375515; -CHECKREG r7, 0x988EC777; -CHECKREG r4, 0x122C891B; -CHECKREG r5, 0xF79AAB1D; -CHECKREG r6, 0x67375515; -CHECKREG r7, 0x988EC777; - -imm32 r0, 0x12348911; -imm32 r1, 0x2e89ab1d; -imm32 r2, 0x34f45515; -imm32 r3, 0x46d67717; -imm32 r4, 0x567b891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x7444b515; -imm32 r7, 0x86667a77; -R0.H = R1.L + R0.L (NS); -R1.H = R1.L + R1.H (NS); -R2.H = R1.H + R2.L (NS); -R3.H = R1.H + R3.H (NS); -R4.H = R1.L + R4.L (NS); -R5.H = R1.L + R5.H (NS); -R6.H = R1.H + R6.L (NS); -R7.H = R1.H + R7.H (NS); -CHECKREG r4, 0x3438891B; -CHECKREG r5, 0x12A6AB1D; -CHECKREG r6, 0x8EBBB515; -CHECKREG r7, 0x600C7A77; -CHECKREG r4, 0x3438891B; -CHECKREG r5, 0x12A6AB1D; -CHECKREG r6, 0x8EBBB515; -CHECKREG r7, 0x600C7A77; - -imm32 r0, 0x85678911; -imm32 r1, 0x3989ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46a67717; -imm32 r4, 0x5e78891b; -imm32 r5, 0x67d9ab1d; -imm32 r6, 0x744b5515; -imm32 r7, 0x86668777; -R0.H = R2.L + R0.L (NS); -R1.H = R2.L + R1.H (NS); -R2.H = R2.H + R2.L (NS); -R3.H = R2.H + R3.H (NS); -R4.H = R2.L + R4.L (NS); -R5.H = R2.L + R5.H (NS); -R6.H = R2.H + R6.L (NS); -R7.L = R2.H + R7.H (NS); -CHECKREG r4, 0xDE30891B; -CHECKREG r5, 0xBCEEAB1D; -CHECKREG r6, 0xDE6E5515; -CHECKREG r7, 0x86660FBF; -CHECKREG r4, 0xDE30891B; -CHECKREG r5, 0xBCEEAB1D; -CHECKREG r6, 0xDE6E5515; -CHECKREG r7, 0x86660FBF; - -imm32 r0, 0x25678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3e445515; -imm32 r3, 0x46d67717; -imm32 r4, 0x567f891b; -imm32 r5, 0x6789bb1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667b77; -R0.H = R3.L + R0.L (NS); -R1.H = R3.L + R1.H (NS); -R2.H = R3.H + R2.L (NS); -R3.H = R3.H + R3.H (NS); -R4.H = R3.L + R4.L (NS); -R5.H = R3.L + R5.H (NS); -R6.H = R3.H + R6.L (NS); -R7.H = R3.H + R7.H (NS); -CHECKREG r4, 0x0032891B; -CHECKREG r5, 0xDEA0BB1D; -CHECKREG r6, 0xE2C15515; -CHECKREG r7, 0x14127B77; -CHECKREG r4, 0x0032891B; -CHECKREG r5, 0xDEA0BB1D; -CHECKREG r6, 0xE2C15515; -CHECKREG r7, 0x14127B77; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.H = R4.L + R0.L (NS); -R1.H = R4.L + R1.H (NS); -R2.H = R4.H + R2.L (NS); -R3.H = R4.H + R3.H (NS); -R4.H = R4.L + R4.L (NS); -R5.H = R4.L + R5.H (NS); -R6.H = R4.H + R6.L (NS); -R7.H = R4.H + R7.H (NS); -CHECKREG r4, 0x1236891B; -CHECKREG r5, 0xF0A4AB1D; -CHECKREG r6, 0x674B5515; -CHECKREG r7, 0x989C7777; -CHECKREG r4, 0x1236891B; -CHECKREG r5, 0xF0A4AB1D; -CHECKREG r6, 0x674B5515; -CHECKREG r7, 0x989C7777; - -imm32 r0, 0xa5678911; -imm32 r1, 0x2a89ab1d; -imm32 r2, 0x34d45515; -imm32 r3, 0x466b7717; -imm32 r4, 0x5678f91b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x7444a515; -imm32 r7, 0x86667b77; -R0.H = R5.L + R0.L (NS); -R1.H = R5.L + R1.H (NS); -R2.H = R5.H + R2.L (NS); -R3.H = R5.H + R3.H (NS); -R4.H = R5.L + R4.L (NS); -R5.H = R5.L + R5.H (NS); -R6.H = R5.H + R6.L (NS); -R7.H = R5.H + R7.H (NS); -CHECKREG r4, 0xA438F91B; -CHECKREG r5, 0x12A6AB1D; -CHECKREG r6, 0xB7BBA515; -CHECKREG r7, 0x990C7B77; -CHECKREG r4, 0xA438F91B; -CHECKREG r5, 0x12A6AB1D; -CHECKREG r6, 0xB7BBA515; -CHECKREG r7, 0x990C7B77; - -imm32 r0, 0xf5678911; -imm32 r1, 0x2f89ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46f67717; -imm32 r4, 0x5678891b; -imm32 r5, 0x678fab1d; -imm32 r6, 0x7444f515; -imm32 r7, 0x86667f77; -R0.L = R6.L + R0.L (NS); -R1.H = R6.L + R1.H (NS); -R2.H = R6.H + R2.L (NS); -R3.H = R6.H + R3.H (NS); -R4.H = R6.L + R4.L (NS); -R5.H = R6.L + R5.H (NS); -R6.H = R6.H + R6.L (NS); -R7.H = R6.H + R7.H (NS); -CHECKREG r4, 0x7E30891B; -CHECKREG r5, 0x5CA4AB1D; -CHECKREG r6, 0x6959F515; -CHECKREG r7, 0xEFBF7F77; -CHECKREG r4, 0x7E30891B; -CHECKREG r5, 0x5CA4AB1D; -CHECKREG r6, 0x6959F515; -CHECKREG r7, 0xEFBF7F77; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.H = R7.L + R0.L (NS); -R1.H = R7.L + R1.H (NS); -R2.H = R7.H + R2.L (NS); -R3.H = R7.H + R3.H (NS); -R4.H = R7.L + R4.L (NS); -R5.H = R7.L + R5.H (NS); -R6.H = R7.H + R6.L (NS); -R7.H = R7.H + R7.H (NS); -CHECKREG r4, 0x0092891B; -CHECKREG r5, 0xDF00AB1D; -CHECKREG r6, 0xDB7B5515; -CHECKREG r7, 0x0CCC7777; -CHECKREG r4, 0x0092891B; -CHECKREG r5, 0xDF00AB1D; -CHECKREG r6, 0xDB7B5515; -CHECKREG r7, 0x0CCC7777; - -imm32 r0, 0x56678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34645515; -imm32 r3, 0x466a7717; -imm32 r4, 0x5678e91b; -imm32 r5, 0x6789af1d; -imm32 r6, 0x744455f5; -imm32 r7, 0x866677b7; -R6.H = R2.L + R3.L (S); -R1.H = R4.L + R5.H (S); -R5.H = R7.H + R2.L (S); -R3.H = R0.H + R0.H (S); -R0.H = R3.L + R4.L (S); -R2.H = R5.L + R7.H (S); -R7.H = R6.H + R7.L (S); -R4.H = R1.H + R6.H (S); -CHECKREG r4, 0x7FFFE91B; -CHECKREG r5, 0xDB7BAF1D; -CHECKREG r6, 0x7FFF55F5; -CHECKREG r7, 0x7FFF77B7; -CHECKREG r4, 0x7FFFE91B; -CHECKREG r5, 0xDB7BAF1D; -CHECKREG r6, 0x7FFF55F5; -CHECKREG r7, 0x7FFF77B7; - -imm32 r0, 0x95678911; -imm32 r1, 0x2989ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46967717; -imm32 r4, 0x5679891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74449515; -imm32 r7, 0x86667977; -R3.H = R4.L + R0.L (S); -R1.H = R6.L + R3.H (S); -R4.H = R3.H + R2.L (S); -R6.H = R7.H + R1.H (S); -R2.H = R5.L + R4.L (S); -R7.H = R2.L + R7.H (S); -R0.H = R1.H + R6.L (S); -R5.H = R0.H + R5.H (S); -CHECKREG r4, 0xD515891B; -CHECKREG r5, 0xE789AB1D; -CHECKREG r6, 0x80009515; -CHECKREG r7, 0xDB7B7977; -CHECKREG r4, 0xD515891B; -CHECKREG r5, 0xE789AB1D; -CHECKREG r6, 0x80009515; -CHECKREG r7, 0xDB7B7977; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_m.s b/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_m.s deleted file mode 100644 index daf114a..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_m.s +++ /dev/null @@ -1,258 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_m/c_dsp32alu_rh_rnd12_m.dsp -// Spec Reference: dsp32alu dreg (half) -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x45678ad1; - imm32 r1, 0x2789ab1d; - imm32 r2, 0xf4445545; - imm32 r3, 0x46667767; - imm32 r4, 0xe678891b; - imm32 r5, 0x6f89ab1d; - imm32 r6, 0x7444d565; - imm32 r7, 0x8666b797; - R0.H = R0 - R0 (RND12); - R1.H = R0 - R1 (RND12); - R2.H = R0 - R2 (RND12); - R3.H = R0 - R3 (RND12); - R4.H = R0 - R4 (RND12); - R5.H = R0 - R5 (RND12); - R6.H = R0 - R6 (RND12); - R7.H = R0 - R7 (RND12); - CHECKREG r0, 0x00008AD1; - CHECKREG r1, 0x8000AB1D; - CHECKREG r2, 0x7fff5545; - CHECKREG r3, 0x80007767; - CHECKREG r4, 0x7fff891B; - CHECKREG r5, 0x8000AB1D; - CHECKREG r6, 0x8000D565; - CHECKREG r7, 0x7fffB797; - - imm32 r0, 0xd5678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0xa4445515; - imm32 r3, 0x46667717; - imm32 r4, 0x5b78891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x74e45515; - imm32 r7, 0x86a6b777; - R0.H = R1 - R0 (RND12); - R1.H = R1 - R1 (RND12); - R2.H = R1 - R2 (RND12); - R3.H = R1 - R3 (RND12); - R4.H = R1 - R4 (RND12); - R5.H = R1 - R5 (RND12); - R6.H = R1 - R6 (RND12); - R7.H = R1 - R7 (RND12); - CHECKREG r0, 0x7fff8911; - CHECKREG r1, 0x0000AB1D; - CHECKREG r2, 0x7fff5515; - CHECKREG r3, 0x80007717; - CHECKREG r4, 0x8000891B; - CHECKREG r5, 0x8000AB1D; - CHECKREG r6, 0x80005515; - CHECKREG r7, 0x7fffB777; - - imm32 r0, 0xa5678091; - imm32 r1, 0x2789ab1d; - imm32 r2, 0xb4445515; - imm32 r3, 0x46667717; - imm32 r4, 0xd678891b; - imm32 r5, 0x6e89ab4d; - imm32 r6, 0x74445567; - imm32 r7, 0x86967757; - R0.H = R2 - R0 (RND12); - R1.H = R2 - R1 (RND12); - R2.H = R2 - R2 (RND12); - R3.H = R2 - R3 (RND12); - R4.H = R2 - R4 (RND12); - R5.H = R2 - R5 (RND12); - R6.H = R2 - R6 (RND12); - R7.H = R2 - R7 (RND12); - CHECKREG r0, 0x7fff8091; - CHECKREG r1, 0x8000AB1D; - CHECKREG r2, 0x00005515; - CHECKREG r3, 0x80007717; - CHECKREG r4, 0x7fff891B; - CHECKREG r5, 0x8000AB4D; - CHECKREG r6, 0x80005567; - CHECKREG r7, 0x7fff7757; - - imm32 r0, 0x35678991; - imm32 r1, 0x2789ab8d; - imm32 r2, 0xd4445515; - imm32 r3, 0x46667737; - imm32 r4, 0x5678891b; - imm32 r5, 0xeab9ab4d; - imm32 r6, 0x744e5515; - imm32 r7, 0x866e747f; - R0.H = R3 - R0 (RND12); - R1.H = R3 - R1 (RND12); - R2.H = R3 - R2 (RND12); - R3.H = R3 - R3 (RND12); - R4.H = R3 - R4 (RND12); - R5.H = R3 - R5 (RND12); - R6.H = R3 - R6 (RND12); - R7.H = R3 - R7 (RND12); - CHECKREG r0, 0x7fff8991; - CHECKREG r1, 0x7fffAB8D; - CHECKREG r2, 0x7fff5515; - CHECKREG r3, 0x00007737; - CHECKREG r4, 0x8000891B; - CHECKREG r5, 0x7fffAB4D; - CHECKREG r6, 0x80005515; - CHECKREG r7, 0x7fff747F; - - imm32 r0, 0xe5678931; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34e45555; - imm32 r3, 0xd6667767; - imm32 r4, 0x5675891b; - imm32 r5, 0x6789abfd; - imm32 r6, 0xa4465515; - imm32 r7, 0x8b66e7b7; - R0.H = R4 - R0 (RND12); - R1.H = R4 - R1 (RND12); - R2.H = R4 - R2 (RND12); - R3.H = R4 - R3 (RND12); - R4.H = R4 - R4 (RND12); - R5.H = R4 - R5 (RND12); - R6.H = R4 - R6 (RND12); - R7.H = R4 - R7 (RND12); - CHECKREG r0, 0x7fff8931; - CHECKREG r1, 0x7fffAB1D; - CHECKREG r2, 0x7fff5555; - CHECKREG r3, 0x7fff7767; - CHECKREG r4, 0x0000891B; - CHECKREG r5, 0x8000ABFD; - CHECKREG r6, 0x7fff5515; - CHECKREG r7, 0x7fffE7B7; - - imm32 r0, 0x35678931; - imm32 r1, 0x2789ab4d; - imm32 r2, 0x3e445585; - imm32 r3, 0x46667717; - imm32 r4, 0xe6f8899b; - imm32 r5, 0x6789db1d; - imm32 r6, 0xf44a5515; - imm32 r7, 0x866b77b7; - R0.H = R5 - R0 (RND12); - R1.H = R5 - R1 (RND12); - R2.H = R5 - R2 (RND12); - R3.H = R5 - R3 (RND12); - R4.H = R5 - R4 (RND12); - R5.H = R5 - R5 (RND12); - R6.H = R5 - R6 (RND12); - R7.H = R5 - R7 (RND12); - CHECKREG r0, 0x7fff8931; - CHECKREG r1, 0x7fffAB4D; - CHECKREG r2, 0x7fff5585; - CHECKREG r3, 0x7fff7717; - CHECKREG r4, 0x7fff899B; - CHECKREG r5, 0x0000DB1D; - CHECKREG r6, 0x7fff5515; - CHECKREG r7, 0x7fff77B7; - - imm32 r0, 0xb5678911; - imm32 r1, 0xc789ab1d; - imm32 r2, 0x3ab45515; - imm32 r3, 0x466b7717; - imm32 r4, 0x4678e91b; - imm32 r5, 0x6789af1d; - imm32 r6, 0xf4445515; - imm32 r7, 0x86e6f777; - R0.H = R6 - R0 (RND12); - R1.H = R6 - R1 (RND12); - R2.H = R6 - R2 (RND12); - R3.H = R6 - R3 (RND12); - R4.H = R6 - R4 (RND12); - R5.H = R6 - R5 (RND12); - R6.H = R6 - R6 (RND12); - R7.H = R6 - R7 (RND12); - CHECKREG r0, 0x7fff8911; - CHECKREG r1, 0x7fffAB1D; - CHECKREG r2, 0x80005515; - CHECKREG r3, 0x80007717; - CHECKREG r4, 0x8000E91B; - CHECKREG r5, 0x8000AF1D; - CHECKREG r6, 0x00005515; - CHECKREG r7, 0x7fffF777; - - imm32 r0, 0xab678051; - imm32 r1, 0x2c89a26d; - imm32 r2, 0x34d455f5; - imm32 r3, 0x466e7717; - imm32 r4, 0x567f89bb; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x744e55a5; - imm32 r7, 0x8666ab77; - R0.H = R7 - R0 (RND12); - R1.H = R7 - R1 (RND12); - R2.H = R7 - R2 (RND12); - R3.H = R7 - R3 (RND12); - R4.H = R7 - R4 (RND12); - R5.H = R7 - R5 (RND12); - R6.H = R7 - R6 (RND12); - R7.H = R7 - R7 (RND12); - CHECKREG r0, 0x80008051; - CHECKREG r1, 0x8000A26D; - CHECKREG r2, 0x800055F5; - CHECKREG r3, 0x80007717; - CHECKREG r4, 0x800089BB; - CHECKREG r5, 0x8000AB1D; - CHECKREG r6, 0x800055A5; - CHECKREG r7, 0x0000AB77; - - imm32 r0, 0x15678901; - imm32 r1, 0x2789abad; - imm32 r2, 0x34445515; - imm32 r3, 0x466677d7; - imm32 r4, 0x5678891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x74445535; - imm32 r7, 0x86667747; - R6.H = R2 - R3 (RND12); - R1.H = R4 - R5 (RND12); - R5.H = R7 - R2 (RND12); - R3.H = R0 - R0 (RND12); - R0.H = R3 - R4 (RND12); - R2.H = R5 - R7 (RND12); - R7.H = R6 - R7 (RND12); - R4.H = R1 - R6 (RND12); - CHECKREG r0, 0x80008901; - CHECKREG r1, 0x8000ABAD; - CHECKREG r2, 0x99a35515; - CHECKREG r3, 0x000077D7; - CHECKREG r4, 0x0005891B; - CHECKREG r5, 0x8000AB1D; - CHECKREG r6, 0x80005535; - CHECKREG r7, 0x999e7747; - - imm32 r0, 0x15678121; - imm32 r1, 0x2789ab3d; - imm32 r2, 0x34445565; - imm32 r3, 0x4d667797; - imm32 r4, 0x567889ab; - imm32 r5, 0x67beabbd; - imm32 r6, 0x7b445515; - imm32 r7, 0x86d6e777; - R3.H = R4 - R0 (RND12); - R1.H = R6 - R3 (RND12); - R4.H = R3 - R2 (RND12); - R6.H = R7 - R1 (RND12); - R2.H = R5 - R4 (RND12); - R7.H = R2 - R7 (RND12); - R0.H = R1 - R6 (RND12); - R5.H = R0 - R5 (RND12); - CHECKREG r0, 0x7fff8121; - CHECKREG r1, 0xb44eAB3D; - CHECKREG r2, 0x80005565; - CHECKREG r3, 0x7fff7797; - CHECKREG r4, 0x7fff89AB; - CHECKREG r5, 0x7fffABBD; - CHECKREG r6, 0x80005515; - CHECKREG r7, 0x9297E777; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_p.s b/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_p.s deleted file mode 100644 index fe54a86..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_p.s +++ /dev/null @@ -1,262 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_p/c_dsp32alu_rh_rnd12_p.dsp -// Spec Reference: dsp32alu dreg (half) -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - - imm32 r0, 0x45678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0xf4445515; - imm32 r3, 0x46667717; - imm32 r4, 0xe678891b; - imm32 r5, 0x6f89ab1d; - imm32 r6, 0x7444d515; - imm32 r7, 0x8666b777; - R0.H = R0 + R0 (RND12); - R1.H = R0 + R1 (RND12); - R2.H = R0 + R2 (RND12); - R3.H = R0 + R3 (RND12); - R4.H = R0 + R4 (RND12); - R5.H = R0 + R5 (RND12); - R6.H = R0 + R6 (RND12); - R7.H = R0 + R7 (RND12); - CHECKREG r0, 0x7FFF8911; - CHECKREG r1, 0x7fffAB1D; - CHECKREG r2, 0x7fff5515; - CHECKREG r3, 0x7fff7717; - CHECKREG r4, 0x7fff891B; - CHECKREG r5, 0x7fffAB1D; - CHECKREG r6, 0x7fffD515; - CHECKREG r7, 0x6664B777; - - imm32 r0, 0xd5678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0xa4445515; - imm32 r3, 0x46667717; - imm32 r4, 0x5b78891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x74e45515; - imm32 r7, 0x86a6b777; - R0.H = R1 + R0 (RND12); - R1.H = R1 + R1 (RND12); - R2.H = R1 + R2 (RND12); - R3.H = R1 + R3 (RND12); - R4.H = R1 + R4 (RND12); - R5.H = R1 + R5 (RND12); - R6.H = R1 + R6 (RND12); - R7.H = R1 + R7 (RND12); - CHECKREG r0, 0xcf138911; - CHECKREG r1, 0x7FFFAB1D; - CHECKREG r2, 0x7fff5515; - CHECKREG r3, 0x7fff7717; - CHECKREG r4, 0x7fff891B; - CHECKREG r5, 0x7fffAB1D; - CHECKREG r6, 0x7fff5515; - CHECKREG r7, 0x6A66B777; - - imm32 r0, 0xa5678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0xb4445515; - imm32 r3, 0x46667717; - imm32 r4, 0xd678891b; - imm32 r5, 0x6e89ab1d; - imm32 r6, 0x74445515; - imm32 r7, 0x86967777; - R0.H = R2 + R0 (RND12); - R1.H = R2 + R1 (RND12); - R2.H = R2 + R2 (RND12); - R3.H = R2 + R3 (RND12); - R4.H = R2 + R4 (RND12); - R5.H = R2 + R5 (RND12); - R6.H = R2 + R6 (RND12); - R7.H = R2 + R7 (RND12); - CHECKREG r4, 0x8000891B; - CHECKREG r5, 0x8000AB1D; - CHECKREG r6, 0x80005515; - CHECKREG r7, 0x80007777; - CHECKREG r4, 0x8000891B; - CHECKREG r5, 0x8000AB1D; - CHECKREG r6, 0x80005515; - CHECKREG r7, 0x80007777; - - imm32 r0, 0x35678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0xd4445515; - imm32 r3, 0x46667717; - imm32 r4, 0x5678891b; - imm32 r5, 0xeab9ab1d; - imm32 r6, 0x744e5515; - imm32 r7, 0x866e777f; - R0.H = R3 + R0 (RND12); - R1.H = R3 + R1 (RND12); - R2.H = R3 + R2 (RND12); - R3.H = R3 + R3 (RND12); - R4.H = R3 + R4 (RND12); - R5.H = R3 + R5 (RND12); - R6.H = R3 + R6 (RND12); - R7.H = R3 + R7 (RND12); - CHECKREG r0, 0x7FFF8911; - CHECKREG r1, 0x7FFFAB1D; - CHECKREG r2, 0x7FFF5515; - CHECKREG r3, 0x7FFF7717; - CHECKREG r4, 0x7fff891B; - CHECKREG r5, 0x7fffAB1D; - CHECKREG r6, 0x7fff5515; - CHECKREG r7, 0x66df777F; - - imm32 r0, 0xe5678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34e45515; - imm32 r3, 0xd6667717; - imm32 r4, 0x5675891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0xa4465515; - imm32 r7, 0x8b66e777; - R0.H = R4 + R0 (RND12); - R1.H = R4 + R1 (RND12); - R2.H = R4 + R2 (RND12); - R3.H = R4 + R3 (RND12); - R4.H = R4 + R4 (RND12); - R5.H = R4 + R5 (RND12); - R6.H = R4 + R6 (RND12); - R7.H = R4 + R7 (RND12); - CHECKREG r0, 0x7FFF8911; - CHECKREG r1, 0x7FFFAB1D; - CHECKREG r2, 0x7FFF5515; - CHECKREG r3, 0x7FFF7717; - CHECKREG r4, 0x7FFF891B; - CHECKREG r5, 0x7fffAB1D; - CHECKREG r6, 0x7fff5515; - CHECKREG r7, 0x7fffE777; - - imm32 r0, 0x35678111; - imm32 r1, 0x2789a21d; - imm32 r2, 0x3e445535; - imm32 r3, 0x46667757; - imm32 r4, 0xe6f8891b; - imm32 r5, 0x6789db7d; - imm32 r6, 0xf44a5595; - imm32 r7, 0x866b7770; - R0.H = R5 + R0 (RND12); - R1.H = R5 + R1 (RND12); - R2.H = R5 + R2 (RND12); - R3.H = R5 + R3 (RND12); - R4.H = R5 + R4 (RND12); - R5.H = R5 + R5 (RND12); - R6.H = R5 + R6 (RND12); - R7.H = R5 + R7 (RND12); - CHECKREG r0, 0x7FFF8111; - CHECKREG r1, 0x7FFFA21D; - CHECKREG r2, 0x7fff5535; - CHECKREG r3, 0x7FFF7757; - CHECKREG r4, 0x7FFF891B; - CHECKREG r5, 0x7FFFDB7D; - CHECKREG r6, 0x7fff5595; - CHECKREG r7, 0x66b57770; - - imm32 r0, 0xb5678911; - imm32 r1, 0xc789ab1d; - imm32 r2, 0x3ab45515; - imm32 r3, 0x466b7717; - imm32 r4, 0x4678e91b; - imm32 r5, 0x6789af1d; - imm32 r6, 0xf4445515; - imm32 r7, 0x86e6f777; - R0.H = R6 + R0 (RND12); - R1.H = R6 + R1 (RND12); - R2.H = R6 + R2 (RND12); - R3.H = R6 + R3 (RND12); - R4.H = R6 + R4 (RND12); - R5.H = R6 + R5 (RND12); - R6.H = R6 + R6 (RND12); - R7.H = R6 + R7 (RND12); - CHECKREG r0, 0x80008911; - CHECKREG r1, 0x8000AB1D; - CHECKREG r2, 0x7fff5515; - CHECKREG r3, 0x7FFF7717; - CHECKREG r4, 0x7FFFE91B; - CHECKREG r5, 0x7FFFAF1D; - CHECKREG r6, 0x80005515; - CHECKREG r7, 0x8000F777; - - imm32 r0, 0xab678021; - imm32 r1, 0x2c89a33d; - imm32 r2, 0x34d45575; - imm32 r3, 0x466e7797; - imm32 r4, 0x567f89fb; - imm32 r5, 0x6789abdd; - imm32 r6, 0x744e5515; - imm32 r7, 0x8666ab87; - R0.H = R7 + R0 (RND12); - R1.H = R7 + R1 (RND12); - R2.H = R7 + R2 (RND12); - R3.H = R7 + R3 (RND12); - R4.H = R7 + R4 (RND12); - R5.H = R7 + R5 (RND12); - R6.H = R7 + R6 (RND12); - R7.H = R7 + R7 (RND12); - CHECKREG r0, 0x80008021; - CHECKREG r1, 0x8000A33D; - CHECKREG r2, 0x80005575; - CHECKREG r3, 0x80007797; - CHECKREG r4, 0x800089FB; - CHECKREG r5, 0x8000ABDD; - CHECKREG r6, 0xab505515; - CHECKREG r7, 0x8000AB87; - - imm32 r0, 0x15678901; - imm32 r1, 0x2789ab2d; - imm32 r2, 0x34445535; - imm32 r3, 0x46667747; - imm32 r4, 0x56788915; - imm32 r5, 0x6789ab6d; - imm32 r6, 0x74445518; - imm32 r7, 0x86667797; - R6.H = R2 + R3 (RND12); - R1.H = R4 + R5 (RND12); - R5.H = R7 + R2 (RND12); - R3.H = R0 + R0 (RND12); - R0.H = R3 + R4 (RND12); - R2.H = R5 + R7 (RND12); - R7.H = R6 + R7 (RND12); - R4.H = R1 + R6 (RND12); - CHECKREG r0, 0x7fff8901; - CHECKREG r1, 0x7FFFAB2D; - CHECKREG r2, 0x80005535; - CHECKREG r3, 0x7FFF7747; - CHECKREG r4, 0x7fff8915; - CHECKREG r5, 0x8000AB6D; - CHECKREG r6, 0x7FFF5518; - CHECKREG r7, 0x665D7797; - - imm32 r0, 0x35678911; - imm32 r1, 0x2489ab1d; - imm32 r2, 0x34545565; - imm32 r3, 0x4d6677b7; - imm32 r4, 0x567889db; - imm32 r5, 0x67beab1d; - imm32 r6, 0x7b445595; - imm32 r7, 0x86d6e707; - R3.H = R4 + R0 (RND12); - R1.H = R6 + R3 (RND12); - R4.H = R3 + R2 (RND12); - R6.H = R7 + R1 (RND12); - R2.H = R5 + R4 (RND12); - R7.H = R2 + R7 (RND12); - R0.H = R1 + R6 (RND12); - R5.H = R0 + R5 (RND12); - CHECKREG r0, 0x7fff8911; - CHECKREG r1, 0x7fffAB1D; - CHECKREG r2, 0x7FFF5565; - CHECKREG r3, 0x7FFF77B7; - CHECKREG r4, 0x7fff89DB; - CHECKREG r5, 0x7FFFAB1D; - CHECKREG r6, 0x6d695595; - CHECKREG r7, 0x6D64E707; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_m.s b/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_m.s deleted file mode 100644 index 8283394..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_m.s +++ /dev/null @@ -1,258 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rh_rnd20_m/c_dsp32alu_rh_rnd20_m.dsp -// Spec Reference: dsp32alu dreg (half) -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0xa5678911; -imm32 r1, 0x2a89ab1d; -imm32 r2, 0x34a45515; -imm32 r3, 0x46a67717; -imm32 r4, 0x5678891b; -imm32 r5, 0x678aab1d; -imm32 r6, 0x7444a515; -imm32 r7, 0x86667a77; -R0.H = R0 - R0 (RND20); -R1.H = R0 - R1 (RND20); -R2.H = R0 - R2 (RND20); -R3.H = R0 - R3 (RND20); -R4.H = R0 - R4 (RND20); -R5.H = R0 - R5 (RND20); -R6.H = R0 - R6 (RND20); -R7.H = R0 - R7 (RND20); -CHECKREG r0, 0x00008911; -CHECKREG r1, 0xFD57AB1D; -CHECKREG r2, 0xFCB65515; -CHECKREG r3, 0xFB967717; -CHECKREG r4, 0xFA98891B; -CHECKREG r5, 0xF987AB1D; -CHECKREG r6, 0xF8BCA515; -CHECKREG r7, 0x079A7A77; - -imm32 r0, 0xa5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0xb4445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5b78891b; -imm32 r5, 0x67bbab1d; -imm32 r6, 0x7444b515; -imm32 r7, 0x86667b77; -R0.H = R1 - R0 (RND20); -R1.H = R1 - R1 (RND20); -R2.H = R1 - R2 (RND20); -R3.H = R1 - R3 (RND20); -R4.H = R1 - R4 (RND20); -R5.H = R1 - R5 (RND20); -R6.H = R1 - R6 (RND20); -R7.H = R1 - R7 (RND20); -CHECKREG r0, 0x08228911; -CHECKREG r1, 0x0000AB1D; -CHECKREG r2, 0x04BC5515; -CHECKREG r3, 0xFB9A7717; -CHECKREG r4, 0xFA49891B; -CHECKREG r5, 0xF984AB1D; -CHECKREG r6, 0xF8BCB515; -CHECKREG r7, 0x079A7B77; - -imm32 r0, 0xa5678911; -imm32 r1, 0x2a89ab1d; -imm32 r2, 0x3a445515; -imm32 r3, 0x46a67717; -imm32 r4, 0x567a891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445a15; -imm32 r7, 0x866677a7; -R0.H = R2 - R0 (RND20); -R1.H = R2 - R1 (RND20); -R2.H = R2 - R2 (RND20); -R3.H = R2 - R3 (RND20); -R4.H = R2 - R4 (RND20); -R5.H = R2 - R5 (RND20); -R6.H = R2 - R6 (RND20); -R7.H = R2 - R7 (RND20); -CHECKREG r0, 0x094E8911; -CHECKREG r1, 0x00FCAB1D; -CHECKREG r2, 0x00005515; -CHECKREG r3, 0xFB967717; -CHECKREG r4, 0xFA98891B; -CHECKREG r5, 0xF987AB1D; -CHECKREG r6, 0xF8BC5A15; -CHECKREG r7, 0x079A77A7; - -imm32 r0, 0xb5678911; -imm32 r1, 0xb789ab1d; -imm32 r2, 0x3d445515; -imm32 r3, 0x46d67717; -imm32 r4, 0x5678891b; -imm32 r5, 0x678ddb1d; -imm32 r6, 0x74445d15; -imm32 r7, 0x866677d7; -R0.H = R3 - R0 (RND20); -R1.H = R3 - R1 (RND20); -R2.H = R3 - R2 (RND20); -R3.H = R3 - R3 (RND20); -R4.H = R3 - R4 (RND20); -R5.H = R3 - R5 (RND20); -R6.H = R3 - R6 (RND20); -R7.H = R3 - R7 (RND20); -CHECKREG r0, 0x09178911; -CHECKREG r1, 0x08F5AB1D; -CHECKREG r2, 0x00995515; -CHECKREG r3, 0x00007717; -CHECKREG r4, 0xFA98891B; -CHECKREG r5, 0xF987DB1D; -CHECKREG r6, 0xF8BC5D15; -CHECKREG r7, 0x079A77D7; - -imm32 r0, 0xd5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0xd4445515; -imm32 r3, 0xd6667717; -imm32 r4, 0x5d78891b; -imm32 r5, 0x67d9ab1d; -imm32 r6, 0x744d5515; -imm32 r7, 0x8666dd77; -R0.H = R4 - R0 (RND20); -R1.H = R4 - R1 (RND20); -R2.H = R4 - R2 (RND20); -R3.H = R4 - R3 (RND20); -R4.H = R4 - R4 (RND20); -R5.H = R4 - R5 (RND20); -R6.H = R4 - R6 (RND20); -R7.H = R4 - R7 (RND20); -CHECKREG r0, 0x08818911; -CHECKREG r1, 0x035FAB1D; -CHECKREG r2, 0x08935515; -CHECKREG r3, 0x08717717; -CHECKREG r4, 0x0000891B; -CHECKREG r5, 0xF982AB1D; -CHECKREG r6, 0xF8BB5515; -CHECKREG r7, 0x079ADD77; - -imm32 r0, 0xe5678911; -imm32 r1, 0x2e89ab1d; -imm32 r2, 0x34d45515; -imm32 r3, 0x46667717; -imm32 r4, 0x567d891b; -imm32 r5, 0x6789db1d; -imm32 r6, 0x74445d15; -imm32 r7, 0x866677d7; -R0.H = R5 - R0 (RND20); -R1.H = R5 - R1 (RND20); -R2.H = R5 - R2 (RND20); -R3.H = R5 - R3 (RND20); -R4.H = R5 - R4 (RND20); -R5.H = R5 - R5 (RND20); -R6.H = R5 - R6 (RND20); -R7.H = R5 - R7 (RND20); -CHECKREG r0, 0x08228911; -CHECKREG r1, 0x0390AB1D; -CHECKREG r2, 0x032B5515; -CHECKREG r3, 0x02127717; -CHECKREG r4, 0x0111891B; -CHECKREG r5, 0x0000DB1D; -CHECKREG r6, 0xF8BC5D15; -CHECKREG r7, 0x079A77D7; - -imm32 r0, 0xa5678911; -imm32 r1, 0x2a89ab1d; -imm32 r2, 0x34a45515; -imm32 r3, 0x46a67717; -imm32 r4, 0x56a8891b; -imm32 r5, 0x678aab1d; -imm32 r6, 0x7444a515; -imm32 r7, 0x86667a77; -R0.H = R6 - R0 (RND20); -R1.H = R6 - R1 (RND20); -R2.H = R6 - R2 (RND20); -R3.H = R6 - R3 (RND20); -R4.H = R6 - R4 (RND20); -R5.H = R6 - R5 (RND20); -R6.H = R6 - R6 (RND20); -R7.H = R6 - R7 (RND20); -CHECKREG r0, 0x0CEE8911; -CHECKREG r1, 0x049CAB1D; -CHECKREG r2, 0x03FA5515; -CHECKREG r3, 0x02DA7717; -CHECKREG r4, 0x01DA891B; -CHECKREG r5, 0x00CCAB1D; -CHECKREG r6, 0x0000A515; -CHECKREG r7, 0x079A7A77; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.H = R7 - R0 (RND20); -R1.H = R7 - R1 (RND20); -R2.H = R7 - R2 (RND20); -R3.H = R7 - R3 (RND20); -R4.H = R7 - R4 (RND20); -R5.H = R7 - R5 (RND20); -R6.H = R7 - R6 (RND20); -R7.H = R7 - R7 (RND20); -CHECKREG r0, 0xF7108911; -CHECKREG r1, 0xF5EEAB1D; -CHECKREG r2, 0xF5225515; -CHECKREG r3, 0xF4007717; -CHECKREG r4, 0xF2FF891B; -CHECKREG r5, 0xF1EEAB1D; -CHECKREG r6, 0xF1225515; -CHECKREG r7, 0x00007777; - -imm32 r0, 0xe5678911; -imm32 r1, 0xe789ab1d; -imm32 r2, 0xe4445515; -imm32 r3, 0x4ee67717; -imm32 r4, 0x567e891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x7444e515; -imm32 r7, 0x86667e77; -R6.H = R2 - R3 (RND20); -R1.H = R4 - R5 (RND20); -R5.H = R7 - R2 (RND20); -R3.H = R0 - R0 (RND20); -R0.H = R3 - R4 (RND20); -R2.H = R5 - R7 (RND20); -R7.H = R6 - R7 (RND20); -R4.H = R1 - R6 (RND20); -CHECKREG r0, 0xFA988911; -CHECKREG r1, 0xFEEFAB1D; -CHECKREG r2, 0x073C5515; -CHECKREG r3, 0x00007717; -CHECKREG r4, 0x005A891B; -CHECKREG r5, 0xFA22AB1D; -CHECKREG r6, 0xF956E515; -CHECKREG r7, 0x072F7E77; - -imm32 r0, 0xe5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3d445515; -imm32 r3, 0x46d67717; -imm32 r4, 0x567d891b; -imm32 r5, 0x6789db1d; -imm32 r6, 0x7444d515; -imm32 r7, 0x86667d77; -R3.H = R4 - R0 (RND20); -R1.H = R6 - R3 (RND20); -R4.H = R3 - R2 (RND20); -R6.H = R7 - R1 (RND20); -R2.H = R5 - R4 (RND20); -R7.H = R2 - R7 (RND20); -R0.H = R1 - R6 (RND20); -R5.H = R0 - R5 (RND20); -CHECKREG r0, 0x00EE8911; -CHECKREG r1, 0x06D3AB1D; -CHECKREG r2, 0x06AF5515; -CHECKREG r3, 0x07117717; -CHECKREG r4, 0xFC9D891B; -CHECKREG r5, 0xF996DB1D; -CHECKREG r6, 0xF7F9D515; -CHECKREG r7, 0x08057D77; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_p.s b/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_p.s deleted file mode 100644 index 231db02..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_p.s +++ /dev/null @@ -1,258 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rh_rnd20_p/c_dsp32alu_rh_rnd20_p.dsp -// Spec Reference: dsp32alu dreg (half) -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0xa5678911; -imm32 r1, 0x2a89ab1d; -imm32 r2, 0x34a45515; -imm32 r3, 0x46a67717; -imm32 r4, 0x5678891b; -imm32 r5, 0x678aab1d; -imm32 r6, 0x7444a515; -imm32 r7, 0x86667a77; -R0.H = R0 + R0 (RND20); -R1.H = R0 + R1 (RND20); -R2.H = R0 + R2 (RND20); -R3.H = R0 + R3 (RND20); -R4.H = R0 + R4 (RND20); -R5.H = R0 + R5 (RND20); -R6.H = R0 + R6 (RND20); -R7.H = R0 + R7 (RND20); -CHECKREG r0, 0xF4AD8911; -CHECKREG r1, 0x01F3AB1D; -CHECKREG r2, 0x02955515; -CHECKREG r3, 0x03B57717; -CHECKREG r4, 0x04B2891B; -CHECKREG r5, 0x05C4AB1D; -CHECKREG r6, 0x068FA515; -CHECKREG r7, 0xF7B17A77; - -imm32 r0, 0xa5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0xb4445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5b78891b; -imm32 r5, 0x67bbab1d; -imm32 r6, 0x7444b515; -imm32 r7, 0x86667b77; -R0.H = R1 + R0 (RND20); -R1.H = R1 + R1 (RND20); -R2.H = R1 + R2 (RND20); -R3.H = R1 + R3 (RND20); -R4.H = R1 + R4 (RND20); -R5.H = R1 + R5 (RND20); -R6.H = R1 + R6 (RND20); -R7.H = R1 + R7 (RND20); -CHECKREG r0, 0xFCCF8911; -CHECKREG r1, 0x04F1AB1D; -CHECKREG r2, 0xFB935515; -CHECKREG r3, 0x04B67717; -CHECKREG r4, 0x0607891B; -CHECKREG r5, 0x06CBAB1D; -CHECKREG r6, 0x0793B515; -CHECKREG r7, 0xF8B67B77; - -imm32 r0, 0xa5678911; -imm32 r1, 0x2a89ab1d; -imm32 r2, 0x3a445515; -imm32 r3, 0x46a67717; -imm32 r4, 0x567a891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445a15; -imm32 r7, 0x866677a7; -R0.H = R2 + R0 (RND20); -R1.H = R2 + R1 (RND20); -R2.H = R2 + R2 (RND20); -R3.H = R2 + R3 (RND20); -R4.H = R2 + R4 (RND20); -R5.H = R2 + R5 (RND20); -R6.H = R2 + R6 (RND20); -R7.H = R2 + R7 (RND20); -CHECKREG r0, 0xFDFB8911; -CHECKREG r1, 0x064DAB1D; -CHECKREG r2, 0x07495515; -CHECKREG r3, 0x04DF7717; -CHECKREG r4, 0x05DC891B; -CHECKREG r5, 0x06EDAB1D; -CHECKREG r6, 0x07B95A15; -CHECKREG r7, 0xF8DB77A7; - -imm32 r0, 0xb5678911; -imm32 r1, 0xb789ab1d; -imm32 r2, 0x3d445515; -imm32 r3, 0x46d67717; -imm32 r4, 0x5678891b; -imm32 r5, 0x678ddb1d; -imm32 r6, 0x74445d15; -imm32 r7, 0x866677d7; -R0.H = R3 + R0 (RND20); -R1.H = R3 + R1 (RND20); -R2.H = R3 + R2 (RND20); -R3.H = R3 + R3 (RND20); -R4.H = R3 + R4 (RND20); -R5.H = R3 + R5 (RND20); -R6.H = R3 + R6 (RND20); -R7.H = R3 + R7 (RND20); -CHECKREG r0, 0xFFC48911; -CHECKREG r1, 0xFFE6AB1D; -CHECKREG r2, 0x08425515; -CHECKREG r3, 0x08DB7717; -CHECKREG r4, 0x05F5891B; -CHECKREG r5, 0x0707DB1D; -CHECKREG r6, 0x07D25D15; -CHECKREG r7, 0xF8F477D7; - -imm32 r0, 0xd5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0xd4445515; -imm32 r3, 0xd6667717; -imm32 r4, 0x5d78891b; -imm32 r5, 0x67d9ab1d; -imm32 r6, 0x744d5515; -imm32 r7, 0x8666dd77; -R0.H = R4 + R0 (RND20); -R1.H = R4 + R1 (RND20); -R2.H = R4 + R2 (RND20); -R3.H = R4 + R3 (RND20); -R4.H = R4 + R4 (RND20); -R5.H = R4 + R5 (RND20); -R6.H = R4 + R6 (RND20); -R7.H = R4 + R7 (RND20); -CHECKREG r0, 0x032E8911; -CHECKREG r1, 0x0850AB1D; -CHECKREG r2, 0x031C5515; -CHECKREG r3, 0x033E7717; -CHECKREG r4, 0x0BAF891B; -CHECKREG r5, 0x0739AB1D; -CHECKREG r6, 0x08005515; -CHECKREG r7, 0xF921DD77; - -imm32 r0, 0xe5678911; -imm32 r1, 0x2e89ab1d; -imm32 r2, 0x34d45515; -imm32 r3, 0x46667717; -imm32 r4, 0x567d891b; -imm32 r5, 0x6789db1d; -imm32 r6, 0x74445d15; -imm32 r7, 0x866677d7; -R0.H = R5 + R0 (RND20); -R1.H = R5 + R1 (RND20); -R2.H = R5 + R2 (RND20); -R3.H = R5 + R3 (RND20); -R4.H = R5 + R4 (RND20); -R5.H = R5 + R5 (RND20); -R6.H = R5 + R6 (RND20); -R7.H = R5 + R7 (RND20); -CHECKREG r0, 0x04CF8911; -CHECKREG r1, 0x0961AB1D; -CHECKREG r2, 0x09C65515; -CHECKREG r3, 0x0ADF7717; -CHECKREG r4, 0x0BE0891B; -CHECKREG r5, 0x0CF1DB1D; -CHECKREG r6, 0x08135D15; -CHECKREG r7, 0xF93677D7; - -imm32 r0, 0xa5678911; -imm32 r1, 0x2a89ab1d; -imm32 r2, 0x34a45515; -imm32 r3, 0x46a67717; -imm32 r4, 0x56a8891b; -imm32 r5, 0x678aab1d; -imm32 r6, 0x7444a515; -imm32 r7, 0x86667a77; -R0.H = R6 + R0 (RND20); -R1.H = R6 + R1 (RND20); -R2.H = R6 + R2 (RND20); -R3.H = R6 + R3 (RND20); -R4.H = R6 + R4 (RND20); -R5.H = R6 + R5 (RND20); -R6.H = R6 + R6 (RND20); -R7.H = R6 + R7 (RND20); -CHECKREG r0, 0x019B8911; -CHECKREG r1, 0x09EDAB1D; -CHECKREG r2, 0x0A8F5515; -CHECKREG r3, 0x0BAF7717; -CHECKREG r4, 0x0CAF891B; -CHECKREG r5, 0x0DBDAB1D; -CHECKREG r6, 0x0E89A515; -CHECKREG r7, 0xF94F7A77; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.H = R7 + R0 (RND20); -R1.H = R7 + R1 (RND20); -R2.H = R7 + R2 (RND20); -R3.H = R7 + R3 (RND20); -R4.H = R7 + R4 (RND20); -R5.H = R7 + R5 (RND20); -R6.H = R7 + R6 (RND20); -R7.H = R7 + R7 (RND20); -CHECKREG r0, 0xF9BD8911; -CHECKREG r1, 0xFADFAB1D; -CHECKREG r2, 0xFBAB5515; -CHECKREG r3, 0xFCCD7717; -CHECKREG r4, 0xFDCE891B; -CHECKREG r5, 0xFEDFAB1D; -CHECKREG r6, 0xFFAB5515; -CHECKREG r7, 0xF0CD7777; - -imm32 r0, 0xe5678911; -imm32 r1, 0xe789ab1d; -imm32 r2, 0xe4445515; -imm32 r3, 0x4ee67717; -imm32 r4, 0x567e891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x7444e515; -imm32 r7, 0x86667e77; -R6.H = R2 + R3 (RND20); -R1.H = R4 + R5 (RND20); -R5.H = R7 + R2 (RND20); -R3.H = R0 + R0 (RND20); -R0.H = R3 + R4 (RND20); -R2.H = R5 + R7 (RND20); -R7.H = R6 + R7 (RND20); -R4.H = R1 + R6 (RND20); -CHECKREG r0, 0x05338911; -CHECKREG r1, 0x0BE1AB1D; -CHECKREG r2, 0xF7D15515; -CHECKREG r3, 0xFCAD7717; -CHECKREG r4, 0x00F1891B; -CHECKREG r5, 0xF6ABAB1D; -CHECKREG r6, 0x0333E515; -CHECKREG r7, 0xF89A7E77; - -imm32 r0, 0xe5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3d445515; -imm32 r3, 0x46d67717; -imm32 r4, 0x567d891b; -imm32 r5, 0x6789db1d; -imm32 r6, 0x7444d515; -imm32 r7, 0x86667d77; -R3.H = R4 + R0 (RND20); -R1.H = R6 + R3 (RND20); -R4.H = R3 + R2 (RND20); -R6.H = R7 + R1 (RND20); -R2.H = R5 + R4 (RND20); -R7.H = R2 + R7 (RND20); -R0.H = R1 + R6 (RND20); -R5.H = R0 + R5 (RND20); -CHECKREG r0, 0x00068911; -CHECKREG r1, 0x0780AB1D; -CHECKREG r2, 0x06BA5515; -CHECKREG r3, 0x03BE7717; -CHECKREG r4, 0x0410891B; -CHECKREG r5, 0x0679DB1D; -CHECKREG r6, 0xF8DED515; -CHECKREG r7, 0xF8D27D77; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rl_m.s b/sim/testsuite/sim/bfin/c_dsp32alu_rl_m.s deleted file mode 100644 index d942d91..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rl_m.s +++ /dev/null @@ -1,263 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rl_m/c_dsp32alu_rl_m.dsp -// Spec Reference: dsp32alu dreg (half) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x55678911; -imm32 r1, 0x2759ab1d; -imm32 r2, 0x34455515; -imm32 r3, 0x46665717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789a51d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.L = R0.L - R0.L (NS); -R1.L = R0.L - R1.H (NS); -R2.L = R0.H - R2.L (NS); -R3.L = R0.H - R3.H (NS); -R4.L = R0.L - R4.L (NS); -R5.L = R0.L - R5.H (NS); -R6.L = R0.H - R6.L (NS); -R7.L = R0.H - R7.H (NS); -CHECKREG r4, 0x567876E5; -CHECKREG r5, 0x67899877; -CHECKREG r6, 0x74440052; -CHECKREG r7, 0x8666CF01; -CHECKREG r4, 0x567876E5; -CHECKREG r5, 0x67899877; -CHECKREG r6, 0x74440052; -CHECKREG r7, 0x8666CF01; - -imm32 r0, 0x44678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x344d5515; -imm32 r3, 0x4666d717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789cc1d; -imm32 r6, 0x74445c15; -imm32 r7, 0x86667c77; -R0.L = R1.L - R0.L (NS); -R1.L = R1.L - R1.H (NS); -R2.L = R1.H - R2.L (NS); -R3.L = R1.H - R3.H (NS); -R4.L = R1.L - R4.L (NS); -R5.L = R1.L - R5.H (NS); -R6.L = R1.H - R6.L (NS); -R7.L = R1.H - R7.H (NS); -CHECKREG r4, 0x5678FA79; -CHECKREG r5, 0x67891C0B; -CHECKREG r6, 0x7444CB74; -CHECKREG r7, 0x8666A123; -CHECKREG r4, 0x5678FA79; -CHECKREG r5, 0x67891C0B; -CHECKREG r6, 0x7444CB74; -CHECKREG r7, 0x8666A123; - -imm32 r0, 0xcc678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34c45515; -imm32 r3, 0x466c7717; -imm32 r4, 0x5678c91b; -imm32 r5, 0x6789ac1d; -imm32 r6, 0x74445515; -imm32 r7, 0x866677c7; -R0.L = R2.L - R0.L (NS); -R1.L = R2.L - R1.H (NS); -R2.L = R2.H - R2.L (NS); -R3.L = R2.H - R3.H (NS); -R4.L = R2.L - R4.L (NS); -R5.L = R2.L - R5.H (NS); -R6.L = R2.H - R6.L (NS); -R7.L = R2.H - R7.H (NS); -CHECKREG r4, 0x56781694; -CHECKREG r5, 0x67897826; -CHECKREG r6, 0x7444DFAF; -CHECKREG r7, 0x8666AE5E; -CHECKREG r4, 0x56781694; -CHECKREG r5, 0x67897826; -CHECKREG r6, 0x7444DFAF; -CHECKREG r7, 0x8666AE5E; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.L = R3.L - R0.L (NS); -R1.L = R3.L - R1.H (NS); -R2.L = R3.H - R2.L (NS); -R3.L = R3.H - R3.H (NS); -R4.L = R3.L - R4.L (NS); -R5.L = R3.L - R5.H (NS); -R6.L = R3.H - R6.L (NS); -R7.L = R3.H - R7.H (NS); -CHECKREG r4, 0x567876E5; -CHECKREG r5, 0x67899877; -CHECKREG r6, 0x7444F151; -CHECKREG r7, 0x8666C000; -CHECKREG r4, 0x567876E5; -CHECKREG r5, 0x67899877; -CHECKREG r6, 0x7444F151; -CHECKREG r7, 0x8666C000; - -imm32 r0, 0xe5678911; -imm32 r1, 0x2e89ab1d; -imm32 r2, 0x34e45515; -imm32 r3, 0x466e7717; -imm32 r4, 0x5678e91b; -imm32 r5, 0x6789ae1d; -imm32 r6, 0x744455e5; -imm32 r7, 0x8666777e; -R0.L = R4.L - R0.L (NS); -R1.L = R4.L - R1.H (NS); -R2.L = R4.H - R2.L (NS); -R3.L = R4.H - R3.H (NS); -R4.L = R4.L - R4.L (NS); -R5.L = R4.L - R5.H (NS); -R6.L = R4.H - R6.L (NS); -R7.L = R4.H - R7.H (NS); -CHECKREG r4, 0x56780000; -CHECKREG r5, 0x67899877; -CHECKREG r6, 0x74440093; -CHECKREG r7, 0x8666D012; -CHECKREG r4, 0x56780000; -CHECKREG r5, 0x67899877; -CHECKREG r6, 0x74440093; -CHECKREG r7, 0x8666D012; - -imm32 r0, 0xdd678911; -imm32 r1, 0xd789ab1d; -imm32 r2, 0x3d445515; -imm32 r3, 0x46d67717; -imm32 r4, 0x567d891b; -imm32 r5, 0x6789db1d; -imm32 r6, 0x74445d15; -imm32 r7, 0x866677d7; -R0.L = R5.L - R0.L (NS); -R1.L = R5.L - R1.H (NS); -R2.L = R5.H - R2.L (NS); -R3.L = R5.H - R3.H (NS); -R4.L = R5.L - R4.L (NS); -R5.L = R5.L - R5.H (NS); -R6.L = R5.H - R6.L (NS); -R7.L = R5.H - R7.H (NS); -CHECKREG r4, 0x567D5202; -CHECKREG r5, 0x67897394; -CHECKREG r6, 0x74440A74; -CHECKREG r7, 0x8666E123; -CHECKREG r4, 0x567D5202; -CHECKREG r5, 0x67897394; -CHECKREG r6, 0x74440A74; -CHECKREG r7, 0x8666E123; - -imm32 r0, 0x85678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x38445515; -imm32 r3, 0x46667717; -imm32 r4, 0x568a891b; -imm32 r5, 0x67a9ab1d; -imm32 r6, 0x744a5515; -imm32 r7, 0x8666aa77; -R0.L = R6.L - R0.L (NS); -R1.L = R6.L - R1.H (NS); -R2.L = R6.H - R2.L (NS); -R3.L = R6.H - R3.H (NS); -R4.L = R6.L - R4.L (NS); -R5.L = R6.L - R5.H (NS); -R6.L = R6.H - R6.L (NS); -R7.L = R6.H - R7.H (NS); -CHECKREG r4, 0x568ACBFA; -CHECKREG r5, 0x67A9ED6C; -CHECKREG r6, 0x744A1F35; -CHECKREG r7, 0x8666EDE4; -CHECKREG r4, 0x568ACBFA; -CHECKREG r5, 0x67A9ED6C; -CHECKREG r6, 0x744A1F35; -CHECKREG r7, 0x8666EDE4; - -imm32 r0, 0x35678911; -imm32 r1, 0x2389ab1d; -imm32 r2, 0x34845515; -imm32 r3, 0x466a7717; -imm32 r4, 0x5678a91b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445b15; -imm32 r7, 0x866677b7; -R0.L = R7.L - R0.L (NS); -R1.L = R7.L - R1.H (NS); -R2.L = R7.H - R2.L (NS); -R3.L = R7.H - R3.H (NS); -R4.L = R7.L - R4.L (NS); -R5.L = R7.L - R5.H (NS); -R6.L = R7.H - R6.L (NS); -R7.L = R7.H - R7.H (NS); -CHECKREG r4, 0x5678CE9C; -CHECKREG r5, 0x6789102E; -CHECKREG r6, 0x74442B51; -CHECKREG r7, 0x86660000; -CHECKREG r4, 0x5678CE9C; -CHECKREG r5, 0x6789102E; -CHECKREG r6, 0x74442B51; -CHECKREG r7, 0x86660000; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R6.L = R2.L - R3.L (S); -R1.L = R4.L - R5.H (S); -R5.L = R7.H - R2.L (S); -R3.L = R0.H - R0.H (S); -R0.L = R3.L - R4.L (S); -R2.L = R5.L - R7.H (S); -R7.L = R6.H - R7.L (S); -R4.L = R1.H - R6.H (S); -CHECKREG r4, 0x5678B345; -CHECKREG r5, 0x67898000; -CHECKREG r6, 0x7444DDFE; -CHECKREG r7, 0x8666FCCD; -CHECKREG r4, 0x5678B345; -CHECKREG r5, 0x67898000; -CHECKREG r6, 0x7444DDFE; -CHECKREG r7, 0x8666FCCD; - -imm32 r0, 0x1d678911; -imm32 r1, 0x27d9ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x466d7717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789dd1d; -imm32 r6, 0x74445515; -imm32 r7, 0x866677d7; -R3.L = R4.L - R0.L (S); -R1.L = R6.L - R3.H (S); -R4.L = R3.H - R2.L (S); -R6.L = R7.H - R1.H (S); -R2.L = R5.L - R4.L (S); -R7.L = R2.L - R7.H (S); -R0.L = R1.H - R6.L (S); -R5.L = R0.H - R5.H (S); -CHECKREG r4, 0x5678F158; -CHECKREG r5, 0x6789B5DE; -CHECKREG r6, 0x74448000; -CHECKREG r7, 0x8666655F; -CHECKREG r4, 0x5678F158; -CHECKREG r5, 0x6789B5DE; -CHECKREG r6, 0x74448000; -CHECKREG r7, 0x8666655F; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rl_p.s b/sim/testsuite/sim/bfin/c_dsp32alu_rl_p.s deleted file mode 100644 index 3c037bd..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rl_p.s +++ /dev/null @@ -1,263 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rl_p/c_dsp32alu_rl_p.dsp -// Spec Reference: dsp32alu dreg (half) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x19678911; -imm32 r1, 0x2799ab1d; -imm32 r2, 0x34945515; -imm32 r3, 0x46967717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86669977; -R0.L = R0.L + R0.L (NS); -R1.L = R0.L + R1.H (NS); -R2.L = R0.H + R2.L (NS); -R3.L = R0.H + R3.H (NS); -R4.L = R0.L + R4.L (NS); -R5.L = R0.L + R5.H (NS); -R6.L = R0.H + R6.L (NS); -R7.L = R0.H + R7.H (NS); -CHECKREG r4, 0x56789B3D; -CHECKREG r5, 0x678979AB; -CHECKREG r6, 0x74446E7C; -CHECKREG r7, 0x86669FCD; -CHECKREG r4, 0x56789B3D; -CHECKREG r5, 0x678979AB; -CHECKREG r6, 0x74446E7C; -CHECKREG r7, 0x86669FCD; - -imm32 r0, 0x15678911; -imm32 r1, 0xaa89ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46a67717; -imm32 r4, 0x567a891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445a15; -imm32 r7, 0x866677a7; -R0.L = R1.L + R0.L (NS); -R1.L = R1.L + R1.H (NS); -R2.L = R1.H + R2.L (NS); -R3.L = R1.H + R3.H (NS); -R4.L = R1.L + R4.L (NS); -R5.L = R1.L + R5.H (NS); -R6.L = R1.H + R6.L (NS); -R7.L = R1.H + R7.H (NS); -CHECKREG r4, 0x567ADEC1; -CHECKREG r5, 0x6789BD2F; -CHECKREG r6, 0x7444049E; -CHECKREG r7, 0x866630EF; -CHECKREG r4, 0x567ADEC1; -CHECKREG r5, 0x6789BD2F; -CHECKREG r6, 0x7444049E; -CHECKREG r7, 0x866630EF; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.L = R2.L + R0.L (NS); -R1.L = R2.L + R1.H (NS); -R2.L = R2.H + R2.L (NS); -R3.L = R2.H + R3.H (NS); -R4.L = R2.L + R4.L (NS); -R5.L = R2.L + R5.H (NS); -R6.L = R2.H + R6.L (NS); -R7.L = R2.H + R7.H (NS); -CHECKREG r4, 0x56781274; -CHECKREG r5, 0x6789F0E2; -CHECKREG r6, 0x74448959; -CHECKREG r7, 0x8666BAAA; -CHECKREG r4, 0x56781274; -CHECKREG r5, 0x6789F0E2; -CHECKREG r6, 0x74448959; -CHECKREG r7, 0x8666BAAA; - -imm32 r0, 0xb5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3bb45515; -imm32 r3, 0x46667717; -imm32 r4, 0x567b891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x7444b515; -imm32 r7, 0x86667b77; -R0.L = R3.L + R0.L (NS); -R1.L = R3.L + R1.H (NS); -R2.L = R3.H + R2.L (NS); -R3.L = R3.H + R3.H (NS); -R4.L = R3.L + R4.L (NS); -R5.L = R3.L + R5.H (NS); -R6.L = R3.H + R6.L (NS); -R7.L = R3.H + R7.H (NS); -CHECKREG r4, 0x567B15E7; -CHECKREG r5, 0x6789F455; -CHECKREG r6, 0x7444FB7B; -CHECKREG r7, 0x8666CCCC; -CHECKREG r4, 0x567B15E7; -CHECKREG r5, 0x6789F455; -CHECKREG r6, 0x7444FB7B; -CHECKREG r7, 0x8666CCCC; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.L = R4.L + R0.L (NS); -R1.L = R4.L + R1.H (NS); -R2.L = R4.H + R2.L (NS); -R3.L = R4.H + R3.H (NS); -R4.L = R4.L + R4.L (NS); -R5.L = R4.L + R5.H (NS); -R6.L = R4.H + R6.L (NS); -R7.L = R4.H + R7.H (NS); -CHECKREG r4, 0x56781236; -CHECKREG r5, 0x678979BF; -CHECKREG r6, 0x7444AB8D; -CHECKREG r7, 0x8666DCDE; -CHECKREG r4, 0x56781236; -CHECKREG r5, 0x678979BF; -CHECKREG r6, 0x7444AB8D; -CHECKREG r7, 0x8666DCDE; - -imm32 r0, 0xcc678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3c445515; -imm32 r3, 0x46c67717; -imm32 r4, 0x567c891b; -imm32 r5, 0x6789cb1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667c77; -R0.L = R5.L + R0.L (NS); -R1.L = R5.L + R1.H (NS); -R2.L = R5.H + R2.L (NS); -R3.L = R5.H + R3.H (NS); -R4.L = R5.L + R4.L (NS); -R5.L = R5.L + R5.H (NS); -R6.L = R5.H + R6.L (NS); -R7.L = R5.H + R7.H (NS); -CHECKREG r4, 0x567C5438; -CHECKREG r5, 0x678932A6; -CHECKREG r6, 0x7444BC9E; -CHECKREG r7, 0x8666EDEF; -CHECKREG r4, 0x567C5438; -CHECKREG r5, 0x678932A6; -CHECKREG r6, 0x7444BC9E; -CHECKREG r7, 0x8666EDEF; - -imm32 r0, 0xd5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3d445515; -imm32 r3, 0x46d67717; -imm32 r4, 0x5678891b; -imm32 r5, 0x678dab1d; -imm32 r6, 0x7444d515; -imm32 r7, 0x86667d77; -R0.L = R6.L + R0.L (NS); -R1.L = R6.L + R1.H (NS); -R2.L = R6.H + R2.L (NS); -R3.L = R6.H + R3.H (NS); -R4.L = R6.L + R4.L (NS); -R5.L = R6.L + R5.H (NS); -R6.L = R6.H + R6.L (NS); -R7.L = R6.H + R7.H (NS); -CHECKREG r4, 0x56785E30; -CHECKREG r5, 0x678D3CA2; -CHECKREG r6, 0x74444959; -CHECKREG r7, 0x8666FAAA; -CHECKREG r4, 0x56785E30; -CHECKREG r5, 0x678D3CA2; -CHECKREG r6, 0x74444959; -CHECKREG r7, 0x8666FAAA; - -imm32 r0, 0xf5678911; -imm32 r1, 0x2f89ab1d; -imm32 r2, 0x34f45515; -imm32 r3, 0x466f7717; -imm32 r4, 0x5678f91b; -imm32 r5, 0x6789af1d; -imm32 r6, 0x744455f5; -imm32 r7, 0x8666777f; -R0.L = R7.L + R0.L (NS); -R1.L = R7.L + R1.H (NS); -R2.L = R7.H + R2.L (NS); -R3.L = R7.H + R3.H (NS); -R4.L = R7.L + R4.L (NS); -R5.L = R7.L + R5.H (NS); -R6.L = R7.H + R6.L (NS); -R7.L = R7.H + R7.H (NS); -CHECKREG r4, 0x5678709A; -CHECKREG r5, 0x6789DF08; -CHECKREG r6, 0x7444DC5B; -CHECKREG r7, 0x86660CCC; -CHECKREG r4, 0x5678709A; -CHECKREG r5, 0x6789DF08; -CHECKREG r6, 0x7444DC5B; -CHECKREG r7, 0x86660CCC; - -imm32 r0, 0x55678911; -imm32 r1, 0x2589ab1d; -imm32 r2, 0x35545515; -imm32 r3, 0x46d67717; -imm32 r4, 0x5678891b; -imm32 r5, 0x678dab1d; -imm32 r6, 0x7444d515; -imm32 r7, 0x86667d77; -R6.L = R2.L + R3.L (S); -R1.L = R4.L + R5.H (S); -R5.L = R7.H + R2.L (S); -R3.L = R0.H + R0.H (S); -R0.L = R3.L + R4.L (S); -R2.L = R5.L + R7.H (S); -R7.L = R6.H + R7.L (S); -R4.L = R1.H + R6.H (S); -CHECKREG r4, 0x56787FFF; -CHECKREG r5, 0x678DDB7B; -CHECKREG r6, 0x74447FFF; -CHECKREG r7, 0x86667FFF; -CHECKREG r4, 0x56787FFF; -CHECKREG r5, 0x678DDB7B; -CHECKREG r6, 0x74447FFF; -CHECKREG r7, 0x86667FFF; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R3.L = R4.L + R0.L (S); -R1.L = R6.L + R3.H (S); -R4.L = R3.H + R2.L (S); -R6.L = R7.H + R1.H (S); -R2.L = R5.L + R4.L (S); -R7.L = R2.L + R7.H (S); -R0.L = R1.H + R6.L (S); -R5.L = R0.H + R5.H (S); -CHECKREG r4, 0x56787FFF; -CHECKREG r5, 0x67897CF0; -CHECKREG r6, 0x7444ADEF; -CHECKREG r7, 0x8666B182; -CHECKREG r4, 0x56787FFF; -CHECKREG r5, 0x67897CF0; -CHECKREG r6, 0x7444ADEF; -CHECKREG r7, 0x8666B182; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_m.s b/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_m.s deleted file mode 100644 index 3beee88..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_m.s +++ /dev/null @@ -1,261 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_m/c_dsp32alu_rl_rnd12_m.dsp -// Spec Reference: dsp32alu dreg (half) -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - imm32 r0, 0x85678911; - imm32 r1, 0x9189ab1d; - imm32 r2, 0xa4245515; - imm32 r3, 0xb6637717; - imm32 r4, 0xc678491b; - imm32 r5, 0x6789a51d; - imm32 r6, 0xe4445565; - imm32 r7, 0x86667777; - R0.L = R0 - R0 (RND12); - R1.L = R0 - R1 (RND12); - R2.L = R0 - R2 (RND12); - R3.L = R0 - R3 (RND12); - R4.L = R0 - R4 (RND12); - R5.L = R0 - R5 (RND12); - R6.L = R0 - R6 (RND12); - R7.L = R0 - R7 (RND12); - CHECKREG r0, 0x85670000; - CHECKREG r1, 0x91898000; - CHECKREG r2, 0xA4248000; - CHECKREG r3, 0xB6638000; - CHECKREG r4, 0xC6788000; - CHECKREG r5, 0x67898000; - CHECKREG r6, 0xE4448000; - CHECKREG r7, 0x8666F009; - - imm32 r0, 0x75678921; - imm32 r1, 0x2789ab14; - imm32 r2, 0xd4745515; - imm32 r3, 0x4d677767; - imm32 r4, 0x56d8791b; - imm32 r5, 0x678dab1d; - imm32 r6, 0x74445515; - imm32 r7, 0x86a6d777; - R0.L = R1 - R0 (RND12); - R1.L = R1 - R1 (RND12); - R2.L = R1 - R2 (RND12); - R3.L = R1 - R3 (RND12); - R4.L = R1 - R4 (RND12); - R5.L = R1 - R5 (RND12); - R6.L = R1 - R6 (RND12); - R7.L = R1 - R7 (RND12); - CHECKREG r0, 0x75678000; - CHECKREG r1, 0x27890000; - CHECKREG r2, 0xD4747FFF; - CHECKREG r3, 0x4D678000; - CHECKREG r4, 0x56D88000; - CHECKREG r5, 0x678D8000; - CHECKREG r6, 0x74448000; - CHECKREG r7, 0x86A67fff; - - imm32 r0, 0x55678911; - imm32 r1, 0x2689ab1d; - imm32 r2, 0x3d445515; - imm32 r3, 0x46967717; - imm32 r4, 0xa67a891b; - imm32 r5, 0x6789bb1d; - imm32 r6, 0x7444d515; - imm32 r7, 0x8666c777; - R0.L = R2 - R0 (RND12); - R1.L = R2 - R1 (RND12); - R2.L = R2 - R2 (RND12); - R3.L = R2 - R3 (RND12); - R4.L = R2 - R4 (RND12); - R5.L = R2 - R5 (RND12); - R6.L = R2 - R6 (RND12); - R7.L = R2 - R7 (RND12); - CHECKREG r0, 0x55678000; - CHECKREG r1, 0x26897fff; - CHECKREG r2, 0x3D440000; - CHECKREG r3, 0x46968000; - CHECKREG r4, 0xA67A7fff; - CHECKREG r5, 0x67898000; - CHECKREG r6, 0x74448000; - CHECKREG r7, 0x86667fff; - - imm32 r0, 0xf5678911; - imm32 r1, 0xd789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0xe6667717; - imm32 r4, 0x5678891b; - imm32 r5, 0x6d89ab1d; - imm32 r6, 0x7444d515; - imm32 r7, 0xe6667b77; - R0.L = R3 - R0 (RND12); - R1.L = R3 - R1 (RND12); - R2.L = R3 - R2 (RND12); - R3.L = R3 - R3 (RND12); - R4.L = R3 - R4 (RND12); - R5.L = R3 - R5 (RND12); - R6.L = R3 - R6 (RND12); - R7.L = R3 - R7 (RND12); - CHECKREG r0, 0xF5678000; - CHECKREG r1, 0xD7897fff; - CHECKREG r2, 0x34448000; - CHECKREG r3, 0xE6660000; - CHECKREG r4, 0x56788000; - CHECKREG r5, 0x6D898000; - CHECKREG r6, 0x74448000; - CHECKREG r7, 0xE666FFF8; - - imm32 r0, 0xa5678911; - imm32 r1, 0x2b89ab1d; - imm32 r2, 0x34c45515; - imm32 r3, 0x46d67717; - imm32 r4, 0x56e8891b; - imm32 r5, 0x67f9ab1d; - imm32 r6, 0x74445515; - imm32 r7, 0x86687777; - R0.L = R4 - R0 (RND12); - R1.L = R4 - R1 (RND12); - R2.L = R4 - R2 (RND12); - R3.L = R4 - R3 (RND12); - R4.L = R4 - R4 (RND12); - R5.L = R4 - R5 (RND12); - R6.L = R4 - R6 (RND12); - R7.L = R4 - R7 (RND12); - CHECKREG r0, 0xa5677fff; - CHECKREG r1, 0x2b897fff; - CHECKREG r2, 0x34c47fff; - CHECKREG r3, 0x46d67fff; - CHECKREG r4, 0x56E80000; - CHECKREG r5, 0x67F98000; - CHECKREG r6, 0x74448000; - CHECKREG r7, 0x86687fff; - - imm32 r0, 0xe5678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0xd6667717; - imm32 r4, 0x5ff8891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x744e5515; - imm32 r7, 0x8666a7b7; - R0.L = R5 - R0 (RND12); - R1.L = R5 - R1 (RND12); - R2.L = R5 - R2 (RND12); - R3.L = R5 - R3 (RND12); - R4.L = R5 - R4 (RND12); - R5.L = R5 - R5 (RND12); - R6.L = R5 - R6 (RND12); - R7.L = R5 - R7 (RND12); - CHECKREG r0, 0xE5677fff; - CHECKREG r1, 0x27897fff; - CHECKREG r2, 0x34447fff; - CHECKREG r3, 0xD6667fff; - CHECKREG r4, 0x5FF87912; - CHECKREG r5, 0x67890000; - CHECKREG r6, 0x744E8000; - CHECKREG r7, 0x86667fff; - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ae1d; - imm32 r2, 0x344455e5; - imm32 r3, 0x4666771d; - imm32 r4, 0x5678891b; - imm32 r5, 0x6789abdd; - imm32 r6, 0x74a45515; - imm32 r7, 0x866c77b7; - R0.L = R6 - R0 (RND12); - R1.L = R6 - R1 (RND12); - R2.L = R6 - R2 (RND12); - R3.L = R6 - R3 (RND12); - R4.L = R6 - R4 (RND12); - R5.L = R6 - R5 (RND12); - R6.L = R6 - R6 (RND12); - R7.L = R6 - R7 (RND12); - CHECKREG r0, 0x15677fff; - CHECKREG r1, 0x27897fff; - CHECKREG r2, 0x34447fff; - CHECKREG r3, 0x46667fff; - CHECKREG r4, 0x56787fff; - CHECKREG r5, 0x67897fff; - CHECKREG r6, 0x74A40000; - CHECKREG r7, 0x866C7fff; - - imm32 r0, 0x25678911; - imm32 r1, 0x2389ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46567717; - imm32 r4, 0x5678891b; - imm32 r5, 0x678dab1d; - imm32 r6, 0x7444b515; - imm32 r7, 0xb666a777; - R0.L = R7 - R0 (RND12); - R1.L = R7 - R1 (RND12); - R2.L = R7 - R2 (RND12); - R3.L = R7 - R3 (RND12); - R4.L = R7 - R4 (RND12); - R5.L = R7 - R5 (RND12); - R6.L = R7 - R6 (RND12); - R7.L = R7 - R7 (RND12); - CHECKREG r0, 0x25678000; - CHECKREG r1, 0x23898000; - CHECKREG r2, 0x34448000; - CHECKREG r3, 0x46568000; - CHECKREG r4, 0x56788000; - CHECKREG r5, 0x678D8000; - CHECKREG r6, 0x74448000; - CHECKREG r7, 0xB6660000; - - imm32 r0, 0xaa678911; - imm32 r1, 0x27ddab1d; - imm32 r2, 0x344bb515; - imm32 r3, 0x46667717; - imm32 r4, 0x56dd891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x7444bb15; - imm32 r7, 0x86ff7777; - R6.L = R2 - R3 (RND12); - R1.L = R4 - R5 (RND12); - R5.L = R7 - R2 (RND12); - R3.L = R0 - R0 (RND12); - R0.L = R3 - R4 (RND12); - R2.L = R5 - R7 (RND12); - R7.L = R6 - R7 (RND12); - R4.L = R1 - R6 (RND12); - CHECKREG r0, 0xAA678000; - CHECKREG r1, 0x27DD8000; - CHECKREG r2, 0x344B7fff; - CHECKREG r3, 0x46660000; - CHECKREG r4, 0x56DD8000; - CHECKREG r5, 0x67898000; - CHECKREG r6, 0x74448000; - CHECKREG r7, 0x86FF7fff; - - imm32 r0, 0x95678911; - imm32 r1, 0x2d89ab1d; - imm32 r2, 0x34b45515; - imm32 r3, 0x46c67717; - imm32 r4, 0x567e891b; - imm32 r5, 0x678fab1d; - imm32 r6, 0x744e5515; - imm32 r7, 0x8b66a777; - R3.L = R4 - R0 (RND12); - R1.L = R6 - R3 (RND12); - R4.L = R3 - R2 (RND12); - R6.L = R7 - R1 (RND12); - R2.L = R5 - R4 (RND12); - R7.L = R2 - R7 (RND12); - R0.L = R1 - R6 (RND12); - R5.L = R0 - R5 (RND12); - CHECKREG r0, 0x95678000; - CHECKREG r1, 0x2D897fff; - CHECKREG r2, 0x34B47fff; - CHECKREG r3, 0x46C67fff; - CHECKREG r4, 0x567E7fff; - CHECKREG r5, 0x678F8000; - CHECKREG r6, 0x744E8000; - CHECKREG r7, 0x8B667FFF; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_p.s b/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_p.s deleted file mode 100644 index bc159a2..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_p.s +++ /dev/null @@ -1,262 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_p/c_dsp32alu_rl_rnd12_p.dsp -// Spec Reference: dsp32alu dreg (half) -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - - imm32 r0, 0x85678011; - imm32 r1, 0x9189a11d; - imm32 r2, 0xa4245235; - imm32 r3, 0xb6637747; - imm32 r4, 0xc67849db; - imm32 r5, 0x6789a5fd; - imm32 r6, 0xe4445565; - imm32 r7, 0x86667707; - R0.L = R0 + R0 (RND12); - R1.L = R0 + R1 (RND12); - R2.L = R0 + R2 (RND12); - R3.L = R0 + R3 (RND12); - R4.L = R0 + R4 (RND12); - R5.L = R0 + R5 (RND12); - R6.L = R0 + R6 (RND12); - R7.L = R0 + R7 (RND12); - CHECKREG r0, 0x85678000; - CHECKREG r1, 0x91898000; - CHECKREG r2, 0xA4248000; - CHECKREG r3, 0xB6638000; - CHECKREG r4, 0xC6788000; - CHECKREG r5, 0x67898000; - CHECKREG r6, 0xE4448000; - CHECKREG r7, 0x86668000; - - imm32 r0, 0x75678921; - imm32 r1, 0x2789ab14; - imm32 r2, 0xd4745515; - imm32 r3, 0x4d677767; - imm32 r4, 0x56d8791b; - imm32 r5, 0x678dab1d; - imm32 r6, 0x74445515; - imm32 r7, 0x86a6d777; - R0.L = R1 + R0 (RND12); - R1.L = R1 + R1 (RND12); - R2.L = R1 + R2 (RND12); - R3.L = R1 + R3 (RND12); - R4.L = R1 + R4 (RND12); - R5.L = R1 + R5 (RND12); - R6.L = R1 + R6 (RND12); - R7.L = R1 + R7 (RND12); - CHECKREG r0, 0x75677FFF; - CHECKREG r1, 0x27897FFF; - CHECKREG r2, 0xD474bfdd; - CHECKREG r3, 0x4D677fff; - CHECKREG r4, 0x56D87FFF; - CHECKREG r5, 0x678D7FFF; - CHECKREG r6, 0x74447FFF; - CHECKREG r7, 0x86A68000; - - imm32 r0, 0x55678911; - imm32 r1, 0x2689ab2d; - imm32 r2, 0x3d44551a; - imm32 r3, 0x469677cd; - imm32 r4, 0xa67a89bb; - imm32 r5, 0x6789bb1d; - imm32 r6, 0x7444d525; - imm32 r7, 0x8666c747; - R0.L = R2 + R0 (RND12); - R1.L = R2 + R1 (RND12); - R2.L = R2 + R2 (RND12); - R3.L = R2 + R3 (RND12); - R4.L = R2 + R4 (RND12); - R5.L = R2 + R5 (RND12); - R6.L = R2 + R6 (RND12); - R7.L = R2 + R7 (RND12); - CHECKREG r0, 0x55677fff; - CHECKREG r1, 0x26897fff; - CHECKREG r2, 0x3D447fff; - CHECKREG r3, 0x46967fff; - CHECKREG r4, 0xA67A8000; - CHECKREG r5, 0x67897fff; - CHECKREG r6, 0x74447fff; - CHECKREG r7, 0x86668000; - - imm32 r0, 0xf5678901; - imm32 r1, 0xd789ab7d; - imm32 r2, 0x34445565; - imm32 r3, 0xe6667757; - imm32 r4, 0x5678894b; - imm32 r5, 0x6d89ab3d; - imm32 r6, 0x7444d525; - imm32 r7, 0xe6667b77; - R0.L = R3 + R0 (RND12); - R1.L = R3 + R1 (RND12); - R2.L = R3 + R2 (RND12); - R3.L = R3 + R3 (RND12); - R4.L = R3 + R4 (RND12); - R5.L = R3 + R5 (RND12); - R6.L = R3 + R6 (RND12); - R7.L = R3 + R7 (RND12); - CHECKREG r0, 0xF5678000; - CHECKREG r1, 0xD7898000; - CHECKREG r2, 0x34447FFF; - CHECKREG r3, 0xE6668000; - CHECKREG r4, 0x56787FFF; - CHECKREG r5, 0x6D897FFF; - CHECKREG r6, 0x74447FFF; - CHECKREG r7, 0xE6668000; - - imm32 r0, 0xa5678911; - imm32 r1, 0x2b89ab1d; - imm32 r2, 0x34c45515; - imm32 r3, 0x46d67717; - imm32 r4, 0x56e8891b; - imm32 r5, 0x67f9ab1d; - imm32 r6, 0x74445515; - imm32 r7, 0x86687777; - R0.L = R4 + R0 (RND12); - R1.L = R4 + R1 (RND12); - R2.L = R4 + R2 (RND12); - R3.L = R4 + R3 (RND12); - R4.L = R4 + R4 (RND12); - R5.L = R4 + R5 (RND12); - R6.L = R4 + R6 (RND12); - R7.L = R4 + R7 (RND12); - CHECKREG r0, 0xA567c501; - CHECKREG r1, 0x2B897fff; - CHECKREG r2, 0x34C47FFF; - CHECKREG r3, 0x46D67FFF; - CHECKREG r4, 0x56E87FFF; - CHECKREG r5, 0x67F97FFF; - CHECKREG r6, 0x74447FFF; - CHECKREG r7, 0x86688000; - - imm32 r0, 0xe5678911; - imm32 r1, 0x2789ab2d; - imm32 r2, 0x34445535; - imm32 r3, 0xd6667747; - imm32 r4, 0x5ff8895b; - imm32 r5, 0x6789ab8d; - imm32 r6, 0x744e5515; - imm32 r7, 0x8666a7b7; - R0.L = R5 + R0 (RND12); - R1.L = R5 + R1 (RND12); - R2.L = R5 + R2 (RND12); - R3.L = R5 + R3 (RND12); - R4.L = R5 + R4 (RND12); - R5.L = R5 + R5 (RND12); - R6.L = R5 + R6 (RND12); - R7.L = R5 + R7 (RND12); - CHECKREG r0, 0xE5677FFF; - CHECKREG r1, 0x27897FFF; - CHECKREG r2, 0x34447FFF; - CHECKREG r3, 0xD6667FFF; - CHECKREG r4, 0x5FF87fff; - CHECKREG r5, 0x67897FFF; - CHECKREG r6, 0x744E7FFF; - CHECKREG r7, 0x86668000; - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ae1d; - imm32 r2, 0x344455e5; - imm32 r3, 0x4666771d; - imm32 r4, 0x5678891b; - imm32 r5, 0x6789abdd; - imm32 r6, 0x74a45515; - imm32 r7, 0x866c77b7; - R0.L = R6 + R0 (RND12); - R1.L = R6 + R1 (RND12); - R2.L = R6 + R2 (RND12); - R3.L = R6 + R3 (RND12); - R4.L = R6 + R4 (RND12); - R5.L = R6 + R5 (RND12); - R6.L = R6 + R6 (RND12); - R7.L = R6 + R7 (RND12); - CHECKREG r0, 0x15677FFF; - CHECKREG r1, 0x27897FFF; - CHECKREG r2, 0x34447FFF; - CHECKREG r3, 0x46667FFF; - CHECKREG r4, 0x56787FFF; - CHECKREG r5, 0x67897FFF; - CHECKREG r6, 0x74A47FFF; - CHECKREG r7, 0x866Cb10f; - - imm32 r0, 0x25678931; - imm32 r1, 0x2389ab14; - imm32 r2, 0x34445576; - imm32 r3, 0x46567787; - imm32 r4, 0x5678899b; - imm32 r5, 0x678dab1d; - imm32 r6, 0x7444b515; - imm32 r7, 0xb666a777; - R0.L = R7 + R0 (RND12); - R1.L = R7 + R1 (RND12); - R2.L = R7 + R2 (RND12); - R3.L = R7 + R3 (RND12); - R4.L = R7 + R4 (RND12); - R5.L = R7 + R5 (RND12); - R6.L = R7 + R6 (RND12); - R7.L = R7 + R7 (RND12); - CHECKREG r0, 0x25678000; - CHECKREG r1, 0x23898000; - CHECKREG r2, 0x34448000; - CHECKREG r3, 0x4656cbd2; - CHECKREG r4, 0x56787FFF; - CHECKREG r5, 0x678D7FFF; - CHECKREG r6, 0x74447FFF; - CHECKREG r7, 0xB6668000; - - imm32 r0, 0xaa678911; - imm32 r1, 0x27ddab1d; - imm32 r2, 0x344bb515; - imm32 r3, 0x46667717; - imm32 r4, 0x56dd891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x7444bb15; - imm32 r7, 0x86ff7777; - R6.L = R2 + R3 (RND12); - R1.L = R4 + R5 (RND12); - R5.L = R7 + R2 (RND12); - R3.L = R0 + R0 (RND12); - R0.L = R3 + R4 (RND12); - R2.L = R5 + R7 (RND12); - R7.L = R6 + R7 (RND12); - R4.L = R1 + R6 (RND12); - CHECKREG r0, 0xAA677FFF; - CHECKREG r1, 0x27DD7FFF; - CHECKREG r2, 0x344B8000; - CHECKREG r3, 0x46668000; - CHECKREG r4, 0x56DD7FFF; - CHECKREG r5, 0x67898000; - CHECKREG r6, 0x74447FFF; - CHECKREG r7, 0x86FFb43f; - - imm32 r0, 0x95678911; - imm32 r1, 0x2d89ab1d; - imm32 r2, 0x34b45515; - imm32 r3, 0x46c67717; - imm32 r4, 0x567e891b; - imm32 r5, 0x678fab1d; - imm32 r6, 0x744e5515; - imm32 r7, 0x8b66a777; - R3.L = R4 + R0 (RND12); - R1.L = R6 + R3 (RND12); - R4.L = R3 + R2 (RND12); - R6.L = R7 + R1 (RND12); - R2.L = R5 + R4 (RND12); - R7.L = R2 + R7 (RND12); - R0.L = R1 + R6 (RND12); - R5.L = R0 + R5 (RND12); - CHECKREG r0, 0x95677fff; - CHECKREG r1, 0x2D897FFF; - CHECKREG r2, 0x34B47FFF; - CHECKREG r3, 0x46C68000; - CHECKREG r4, 0x567E7FFF; - CHECKREG r5, 0x678Fcf73; - CHECKREG r6, 0x744E8000; - CHECKREG r7, 0x8B668000; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_m.s b/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_m.s deleted file mode 100644 index 4916fd0..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_m.s +++ /dev/null @@ -1,262 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rl_rnd20_m/c_dsp32alu_rl_rnd20_m.dsp -// Spec Reference: dsp32alu dreg (half) -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x75678911; -imm32 r1, 0xa789ab1d; -imm32 r2, 0x34745515; -imm32 r3, 0x4b677717; -imm32 r4, 0x5678791b; -imm32 r5, 0xc789a71d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.L = R0 - R0 (RND20); -R1.L = R0 - R1 (RND20); -R2.L = R0 - R2 (RND20); -R3.L = R0 - R3 (RND20); -R4.L = R0 - R4 (RND20); -R5.L = R0 - R5 (RND20); -R6.L = R0 - R6 (RND20); -R7.L = R0 - R7 (RND20); -CHECKREG r0, 0x75670000; -CHECKREG r1, 0xA7890CDE; -CHECKREG r2, 0x3474040F; -CHECKREG r3, 0x4B6702A0; -CHECKREG r4, 0x567801EF; -CHECKREG r5, 0xC7890ADE; -CHECKREG r6, 0x74440012; -CHECKREG r7, 0x86660EF0; - -imm32 r0, 0xe5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3e445515; -imm32 r3, 0x46667717; -imm32 r4, 0x56e8891b; -imm32 r5, 0x678eab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86e67e77; -R0.L = R1 - R0 (RND20); -CHECKREG r0, 0xE5670422; -R1.L = R1 - R1 (RND20); -CHECKREG r1, 0x27890000; -R2.L = R1 - R2 (RND20); -CHECKREG r2, 0x3E44FE94; -R3.L = R1 - R3 (RND20); -CHECKREG r3, 0x4666FE12; -R4.L = R1 - R4 (RND20); -R5.L = R1 - R5 (RND20); -R6.L = R1 - R6 (RND20); -R7.L = R1 - R7 (RND20); -CHECKREG r0, 0xE5670422; -CHECKREG r1, 0x27890000; -CHECKREG r2, 0x3E44FE94; -CHECKREG r3, 0x4666FE12; -CHECKREG r4, 0x56E8FD0A; -CHECKREG r5, 0x678EFC00; -CHECKREG r6, 0x7444FB34; -CHECKREG r7, 0x86E60A0A; - -imm32 r0, 0xdd678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3d445515; -imm32 r3, 0x46667717; -imm32 r4, 0x56d8891b; -imm32 r5, 0x678dab1d; -imm32 r6, 0x7444d515; -imm32 r7, 0x86667d77; -R0.L = R2 - R0 (RND20); -R1.L = R2 - R1 (RND20); -R2.L = R2 - R2 (RND20); -R3.L = R2 - R3 (RND20); -R4.L = R2 - R4 (RND20); -R5.L = R2 - R5 (RND20); -R6.L = R2 - R6 (RND20); -R7.L = R2 - R7 (RND20); -CHECKREG r0, 0xDD6705FE; -CHECKREG r1, 0x2789015C; -CHECKREG r2, 0x3D440000; -CHECKREG r3, 0x4666FF6E; -CHECKREG r4, 0x56D8FE67; -CHECKREG r5, 0x678DFD5B; -CHECKREG r6, 0x7444FC90; -CHECKREG r7, 0x86660B6E; - -imm32 r0, 0xa5678911; -imm32 r1, 0x2a89ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46a67717; -imm32 r4, 0x567a891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x7444c515; -imm32 r7, 0x86667c77; -R0.L = R3 - R0 (RND20); -R1.L = R3 - R1 (RND20); -R2.L = R3 - R2 (RND20); -R3.L = R3 - R3 (RND20); -R4.L = R3 - R4 (RND20); -R5.L = R3 - R5 (RND20); -R6.L = R3 - R6 (RND20); -R7.L = R3 - R7 (RND20); -CHECKREG r0, 0xA5670A14; -CHECKREG r1, 0x2A8901C2; -CHECKREG r2, 0x34440126; -CHECKREG r3, 0x46A60000; -CHECKREG r4, 0x567AFF03; -CHECKREG r5, 0x6789FDF2; -CHECKREG r6, 0x7444FD26; -CHECKREG r7, 0x86660C04; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.L = R4 - R0 (RND20); -R1.L = R4 - R1 (RND20); -R2.L = R4 - R2 (RND20); -R3.L = R4 - R3 (RND20); -R4.L = R4 - R4 (RND20); -R5.L = R4 - R5 (RND20); -R6.L = R4 - R6 (RND20); -R7.L = R4 - R7 (RND20); -CHECKREG r0, 0x15670411; -CHECKREG r1, 0x278902EF; -CHECKREG r2, 0x34440223; -CHECKREG r3, 0x46660101; -CHECKREG r4, 0x56780000; -CHECKREG r5, 0x6789FEEF; -CHECKREG r6, 0x7444FE23; -CHECKREG r7, 0x86660D01; - -imm32 r0, 0x95678911; -imm32 r1, 0x8789ab1d; -imm32 r2, 0x74445515; -imm32 r3, 0x4a667717; -imm32 r4, 0x56b8891b; -imm32 r5, 0x678dab1d; -imm32 r6, 0x7444e515; -imm32 r7, 0x86667d77; -R0.L = R5 - R0 (RND20); -R1.L = R5 - R1 (RND20); -R2.L = R5 - R2 (RND20); -R3.L = R5 - R3 (RND20); -R4.L = R5 - R4 (RND20); -R5.L = R5 - R5 (RND20); -R6.L = R5 - R6 (RND20); -R7.L = R5 - R7 (RND20); -CHECKREG r0, 0x95670D22; -CHECKREG r1, 0x87890E00; -CHECKREG r2, 0x7444FF35; -CHECKREG r3, 0x4A6601D2; -CHECKREG r4, 0x56B8010D; -CHECKREG r5, 0x678D0000; -CHECKREG r6, 0x7444FF35; -CHECKREG r7, 0x86660E12; - -imm32 r0, 0x35678911; -imm32 r1, 0x2459ab1d; -imm32 r2, 0x34465515; -imm32 r3, 0xe6667717; -imm32 r4, 0x5d78891b; -imm32 r5, 0x67b9ab1d; -imm32 r6, 0x744a5515; -imm32 r7, 0x8666c777; -R0.L = R6 - R0 (RND20); -R1.L = R6 - R1 (RND20); -R2.L = R6 - R2 (RND20); -R3.L = R6 - R3 (RND20); -R4.L = R6 - R4 (RND20); -R5.L = R6 - R5 (RND20); -R6.L = R6 - R6 (RND20); -R7.L = R6 - R7 (RND20); -CHECKREG r0, 0x356703EE; -CHECKREG r1, 0x245904FF; -CHECKREG r2, 0x34460400; -CHECKREG r3, 0xE66608DE; -CHECKREG r4, 0x5D78016D; -CHECKREG r5, 0x67B900C9; -CHECKREG r6, 0x744A0000; -CHECKREG r7, 0x86660EDE; - -imm32 r0, 0xa5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3a445515; -imm32 r3, 0x4c667717; -imm32 r4, 0x56b8891b; -imm32 r5, 0x678dab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x8666d777; -R0.L = R7 - R0 (RND20); -R1.L = R7 - R1 (RND20); -R2.L = R7 - R2 (RND20); -R3.L = R7 - R3 (RND20); -R4.L = R7 - R4 (RND20); -R5.L = R7 - R5 (RND20); -R6.L = R7 - R6 (RND20); -R7.L = R7 - R7 (RND20); -CHECKREG r0, 0xA567FE10; -CHECKREG r1, 0x2789F5EE; -CHECKREG r2, 0x3A44F4C2; -CHECKREG r3, 0x4C66F3A0; -CHECKREG r4, 0x56B8F2FB; -CHECKREG r5, 0x678DF1EE; -CHECKREG r6, 0x7444F122; -CHECKREG r7, 0x86660000; - -imm32 r0, 0xabd78911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0xd4445515; -imm32 r3, 0x4e667717; -imm32 r4, 0x56f8891b; -imm32 r5, 0x678aab1d; -imm32 r6, 0x7444b515; -imm32 r7, 0x86667d77; -R6.L = R2 - R3 (RND20); -R1.L = R4 - R5 (RND20); -R5.L = R7 - R2 (RND20); -R3.L = R0 - R0 (RND20); -R0.L = R3 - R4 (RND20); -R2.L = R5 - R7 (RND20); -R7.L = R6 - R7 (RND20); -R4.L = R1 - R6 (RND20); -CHECKREG r0, 0xABD7FF77; -CHECKREG r1, 0x2789FEF7; -CHECKREG r2, 0xD4440E12; -CHECKREG r3, 0x4E660000; -CHECKREG r4, 0x56F8FB34; -CHECKREG r5, 0x678AFB22; -CHECKREG r6, 0x7444F85E; -CHECKREG r7, 0x86660EDE; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R3.L = R4 - R0 (RND20); -R1.L = R6 - R3 (RND20); -R4.L = R3 - R2 (RND20); -R6.L = R7 - R1 (RND20); -R2.L = R5 - R4 (RND20); -R7.L = R2 - R7 (RND20); -R0.L = R1 - R6 (RND20); -R5.L = R0 - R5 (RND20); -CHECKREG r0, 0x1567FB34; -CHECKREG r1, 0x278902DE; -CHECKREG r2, 0x34440111; -CHECKREG r3, 0x46660411; -CHECKREG r4, 0x56780122; -CHECKREG r5, 0x6789FADE; -CHECKREG r6, 0x7444F5EE; -CHECKREG r7, 0x86660ADE; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_p.s b/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_p.s deleted file mode 100644 index ced4fcc..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_p.s +++ /dev/null @@ -1,258 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rl_rnd20_p/c_dsp32alu_rl_rnd20_p.dsp -// Spec Reference: dsp32alu dreg (half) -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x75678911; -imm32 r1, 0xa789ab1d; -imm32 r2, 0x34745515; -imm32 r3, 0x4b677717; -imm32 r4, 0x5678791b; -imm32 r5, 0xc789a71d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.L = R0 + R0 (RND20); -R1.L = R0 + R1 (RND20); -R2.L = R0 + R2 (RND20); -R3.L = R0 + R3 (RND20); -R4.L = R0 + R4 (RND20); -R5.L = R0 + R5 (RND20); -R6.L = R0 + R6 (RND20); -R7.L = R0 + R7 (RND20); -CHECKREG r0, 0x75670EAD; -CHECKREG r1, 0xA78901CF; -CHECKREG r2, 0x34740A9E; -CHECKREG r3, 0x4B670C0D; -CHECKREG r4, 0x56780CBE; -CHECKREG r5, 0xC78903CF; -CHECKREG r6, 0x74440E9B; -CHECKREG r7, 0x8666FFBD; - -imm32 r0, 0xe5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3e445515; -imm32 r3, 0x46667717; -imm32 r4, 0x56e8891b; -imm32 r5, 0x678eab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86e67e77; -R0.L = R1 + R0 (RND20); -R1.L = R1 + R1 (RND20); -R2.L = R1 + R2 (RND20); -R3.L = R1 + R3 (RND20); -R4.L = R1 + R4 (RND20); -R5.L = R1 + R5 (RND20); -R6.L = R1 + R6 (RND20); -R7.L = R1 + R7 (RND20); -CHECKREG r0, 0xE56700CF; -CHECKREG r1, 0x278904F1; -CHECKREG r2, 0x3E44065D; -CHECKREG r3, 0x466606DF; -CHECKREG r4, 0x56E807E7; -CHECKREG r5, 0x678E08F1; -CHECKREG r6, 0x744409BD; -CHECKREG r7, 0x86E6FAE7; - -imm32 r0, 0xdd678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3d445515; -imm32 r3, 0x46667717; -imm32 r4, 0x56d8891b; -imm32 r5, 0x678dab1d; -imm32 r6, 0x7444d515; -imm32 r7, 0x86667d77; -R0.L = R2 + R0 (RND20); -R1.L = R2 + R1 (RND20); -R2.L = R2 + R2 (RND20); -R3.L = R2 + R3 (RND20); -R4.L = R2 + R4 (RND20); -R5.L = R2 + R5 (RND20); -R6.L = R2 + R6 (RND20); -R7.L = R2 + R7 (RND20); -CHECKREG r0, 0xDD6701AB; -CHECKREG r1, 0x2789064D; -CHECKREG r2, 0x3D4407A9; -CHECKREG r3, 0x4666083B; -CHECKREG r4, 0x56D80942; -CHECKREG r5, 0x678D0A4D; -CHECKREG r6, 0x74440B19; -CHECKREG r7, 0x8666FC3B; - -imm32 r0, 0xa5678911; -imm32 r1, 0x2a89ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46a67717; -imm32 r4, 0x567a891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x7444c515; -imm32 r7, 0x86667c77; -R0.L = R3 + R0 (RND20); -R1.L = R3 + R1 (RND20); -R2.L = R3 + R2 (RND20); -R3.L = R3 + R3 (RND20); -R4.L = R3 + R4 (RND20); -R5.L = R3 + R5 (RND20); -R6.L = R3 + R6 (RND20); -R7.L = R3 + R7 (RND20); -CHECKREG r0, 0xA567FEC1; -CHECKREG r1, 0x2A890713; -CHECKREG r2, 0x344407AF; -CHECKREG r3, 0x46A608D5; -CHECKREG r4, 0x567A09D2; -CHECKREG r5, 0x67890AE3; -CHECKREG r6, 0x74440BAF; -CHECKREG r7, 0x8666FCD1; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0.L = R4 + R0 (RND20); -R1.L = R4 + R1 (RND20); -R2.L = R4 + R2 (RND20); -R3.L = R4 + R3 (RND20); -R4.L = R4 + R4 (RND20); -R5.L = R4 + R5 (RND20); -R6.L = R4 + R6 (RND20); -R7.L = R4 + R7 (RND20); -CHECKREG r0, 0x156706BE; -CHECKREG r1, 0x278907E0; -CHECKREG r2, 0x344408AC; -CHECKREG r3, 0x466609CE; -CHECKREG r4, 0x56780ACF; -CHECKREG r5, 0x67890BE0; -CHECKREG r6, 0x74440CAC; -CHECKREG r7, 0x8666FDCE; - -imm32 r0, 0x95678911; -imm32 r1, 0x8789ab1d; -imm32 r2, 0x74445515; -imm32 r3, 0x4a667717; -imm32 r4, 0x56b8891b; -imm32 r5, 0x678dab1d; -imm32 r6, 0x7444e515; -imm32 r7, 0x86667d77; -R0.L = R5 + R0 (RND20); -R1.L = R5 + R1 (RND20); -R2.L = R5 + R2 (RND20); -R3.L = R5 + R3 (RND20); -R4.L = R5 + R4 (RND20); -R5.L = R5 + R5 (RND20); -R6.L = R5 + R6 (RND20); -R7.L = R5 + R7 (RND20); -CHECKREG r0, 0x9567FFCF; -CHECKREG r1, 0x8789FEF1; -CHECKREG r2, 0x74440DBD; -CHECKREG r3, 0x4A660B1F; -CHECKREG r4, 0x56B80BE4; -CHECKREG r5, 0x678D0CF2; -CHECKREG r6, 0x74440DBD; -CHECKREG r7, 0x8666FEDF; - -imm32 r0, 0x35678911; -imm32 r1, 0x2459ab1d; -imm32 r2, 0x34465515; -imm32 r3, 0xe6667717; -imm32 r4, 0x5d78891b; -imm32 r5, 0x67b9ab1d; -imm32 r6, 0x744a5515; -imm32 r7, 0x8666c777; -R0.L = R6 + R0 (RND20); -R1.L = R6 + R1 (RND20); -R2.L = R6 + R2 (RND20); -R3.L = R6 + R3 (RND20); -R4.L = R6 + R4 (RND20); -R5.L = R6 + R5 (RND20); -R6.L = R6 + R6 (RND20); -R7.L = R6 + R7 (RND20); -CHECKREG r0, 0x35670A9B; -CHECKREG r1, 0x2459098A; -CHECKREG r2, 0x34460A89; -CHECKREG r3, 0xE66605AB; -CHECKREG r4, 0x5D780D1C; -CHECKREG r5, 0x67B90DC0; -CHECKREG r6, 0x744A0E89; -CHECKREG r7, 0x8666FFAB; - -imm32 r0, 0xa5678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3a445515; -imm32 r3, 0x4c667717; -imm32 r4, 0x56b8891b; -imm32 r5, 0x678dab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x8666d777; -R0.L = R7 + R0 (RND20); -R1.L = R7 + R1 (RND20); -R2.L = R7 + R2 (RND20); -R3.L = R7 + R3 (RND20); -R4.L = R7 + R4 (RND20); -R5.L = R7 + R5 (RND20); -R6.L = R7 + R6 (RND20); -R7.L = R7 + R7 (RND20); -CHECKREG r0, 0xA567F2BD; -CHECKREG r1, 0x2789FADF; -CHECKREG r2, 0x3A44FC0B; -CHECKREG r3, 0x4C66FD2D; -CHECKREG r4, 0x56B8FDD2; -CHECKREG r5, 0x678DFEDF; -CHECKREG r6, 0x7444FFAB; -CHECKREG r7, 0x8666F0CD; - -imm32 r0, 0xabd78911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0xd4445515; -imm32 r3, 0x4e667717; -imm32 r4, 0x56f8891b; -imm32 r5, 0x678aab1d; -imm32 r6, 0x7444b515; -imm32 r7, 0x86667d77; -R6.L = R2 + R3 (RND20); -R1.L = R4 + R5 (RND20); -R5.L = R7 + R2 (RND20); -R3.L = R0 + R0 (RND20); -R0.L = R3 + R4 (RND20); -R2.L = R5 + R7 (RND20); -R7.L = R6 + R7 (RND20); -R4.L = R1 + R6 (RND20); -CHECKREG r0, 0xABD70A56; -CHECKREG r1, 0x27890BE8; -CHECKREG r2, 0xD444FEDF; -CHECKREG r3, 0x4E66F57B; -CHECKREG r4, 0x56F809BD; -CHECKREG r5, 0x678AF5AB; -CHECKREG r6, 0x7444022B; -CHECKREG r7, 0x8666FFAB; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5678891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R3.L = R4 + R0 (RND20); -R1.L = R6 + R3 (RND20); -R4.L = R3 + R2 (RND20); -R6.L = R7 + R1 (RND20); -R2.L = R5 + R4 (RND20); -R7.L = R2 + R7 (RND20); -R0.L = R1 + R6 (RND20); -R5.L = R0 + R5 (RND20); -CHECKREG r0, 0x156709BD; -CHECKREG r1, 0x27890BAB; -CHECKREG r2, 0x34440BE0; -CHECKREG r3, 0x466606BE; -CHECKREG r4, 0x567807AB; -CHECKREG r5, 0x678907CF; -CHECKREG r6, 0x7444FADF; -CHECKREG r7, 0x8666FBAB; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rlh_rnd.s b/sim/testsuite/sim/bfin/c_dsp32alu_rlh_rnd.s deleted file mode 100644 index b7f0c2a..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rlh_rnd.s +++ /dev/null @@ -1,66 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rlh_rnd/c_dsp32alu_rlh_rnd.dsp -// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x4537891b; -imm32 r1, 0x6759ab2d; -imm32 r2, 0x44555535; -imm32 r3, 0x66665747; -imm32 r4, 0x88789565; -imm32 r5, 0xaa8abb5b; -imm32 r6, 0xcc9cdd85; -imm32 r7, 0xeeaeff9f; -R0.L = R1 (RND); -R0.H = R2 (RND); -R1.L = R3 (RND); -R1.H = R4 (RND); -R2.L = R5 (RND); -R2.H = R6 (RND); -CHECKREG r0, 0x4455675A; -CHECKREG r1, 0x88796666; -CHECKREG r2, 0xCC9DAA8B; - - -imm32 r0, 0xe537891b; -imm32 r1, 0xf759ab2d; -imm32 r2, 0x4ef55535; -imm32 r3, 0x666b5747; -imm32 r4, 0xc8789565; -imm32 r5, 0xaa8abb5b; -imm32 r6, 0x8c9cdd85; -imm32 r7, 0x9eaeff9f; -R3.L = R0 (RND); -R3.H = R1 (RND); -R4.L = R2 (RND); -R4.H = R5 (RND); -R5.L = R6 (RND); -R5.H = R7 (RND); -CHECKREG r3, 0xF75AE538; -CHECKREG r4, 0xAA8B4EF5; -CHECKREG r5, 0x9EAF8C9D; - -imm32 r0, 0x5537891b; -imm32 r1, 0x6759ab2d; -imm32 r2, 0x8ef55535; -imm32 r3, 0x666b5747; -imm32 r4, 0xc8789565; -imm32 r5, 0xea8abb5b; -imm32 r6, 0xfc9cdd85; -imm32 r7, 0x9eaeff9f; -R6.L = R0 (RND); -R6.H = R1 (RND); -R7.L = R2 (RND); -R7.H = R3 (RND); -R5.L = R4 (RND); -R5.H = R5 (RND); -CHECKREG r5, 0xEA8BC879; -CHECKREG r6, 0x675A5538; -CHECKREG r7, 0x666B8EF5; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rm.s b/sim/testsuite/sim/bfin/c_dsp32alu_rm.s deleted file mode 100644 index f8c1407..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rm.s +++ /dev/null @@ -1,262 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rm/c_dsp32alu_rm.dsp -// Spec Reference: dsp32alu -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x35678911; -imm32 r1, 0x2389ab1d; -imm32 r2, 0x34345515; -imm32 r3, 0x46637717; -imm32 r4, 0x5567391b; -imm32 r5, 0x6789a31d; -imm32 r6, 0x744455a5; -imm32 r7, 0x866677a7; -R0 = R0 - R0 (NS); -R1 = R0 - R1 (NS); -R2 = R0 - R2 (NS); -R3 = R0 - R3 (NS); -R4 = R0 - R4 (NS); -R5 = R0 - R5 (NS); -R6 = R0 - R6 (NS); -R7 = R0 - R7 (NS); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0xDC7654E3; -CHECKREG r2, 0xCBCBAAEB; -CHECKREG r3, 0xB99C88E9; -CHECKREG r4, 0xAA98C6E5; -CHECKREG r5, 0x98765CE3; -CHECKREG r6, 0x8BBBAA5B; -CHECKREG r7, 0x79998859; - -imm32 r0, 0xa5678911; -imm32 r1, 0x4a89ab1d; -imm32 r2, 0x54a45515; -imm32 r3, 0x466a7717; -imm32 r4, 0x5567a91b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445a15; -imm32 r7, 0x866677a7; -R0 = R1 - R0 (NS); -R1 = R1 - R1 (NS); -R2 = R1 - R2 (NS); -R3 = R1 - R3 (NS); -R4 = R1 - R4 (NS); -R5 = R1 - R5 (NS); -R6 = R1 - R6 (NS); -R7 = R1 - R7 (NS); -CHECKREG r0, 0xA522220C; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0xAB5BAAEB; -CHECKREG r3, 0xB99588E9; -CHECKREG r4, 0xAA9856E5; -CHECKREG r5, 0x987654E3; -CHECKREG r6, 0x8BBBA5EB; -CHECKREG r7, 0x79998859; - -imm32 r0, 0xda678911; -imm32 r1, 0x27c9ab1d; -imm32 r2, 0x344c5515; -imm32 r3, 0x4666c717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x744455b5; -imm32 r7, 0x8666777b; -R0 = R2 - R0 (NS); -R1 = R2 - R1 (NS); -R2 = R2 - R2 (NS); -R3 = R2 - R3 (NS); -R4 = R2 - R4 (NS); -R5 = R2 - R5 (NS); -R6 = R2 - R6 (NS); -R7 = R2 - R7 (NS); -CHECKREG r0, 0x59E4CC04; -CHECKREG r1, 0x0C82A9F8; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0xB99938E9; -CHECKREG r4, 0xAA9876E5; -CHECKREG r5, 0x987654E3; -CHECKREG r6, 0x8BBBAA4B; -CHECKREG r7, 0x79998885; - -imm32 r0, 0x65678911; -imm32 r1, 0x7289ab1d; -imm32 r2, 0x84345515; -imm32 r3, 0x96647717; -imm32 r4, 0x5567591b; -imm32 r5, 0x6789a61d; -imm32 r6, 0x744d5515; -imm32 r7, 0x8666b777; -R0 = R3 - R0 (NS); -R1 = R3 - R1 (NS); -R2 = R3 - R2 (NS); -R3 = R3 - R3 (NS); -R4 = R3 - R4 (NS); -R5 = R3 - R5 (NS); -R6 = R3 - R6 (NS); -R7 = R3 - R7 (NS); -CHECKREG r0, 0x30FCEE06; -CHECKREG r1, 0x23DACBFA; -CHECKREG r2, 0x12302202; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0xAA98A6E5; -CHECKREG r5, 0x987659E3; -CHECKREG r6, 0x8BB2AAEB; -CHECKREG r7, 0x79994889; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0 = R4 - R0 (NS); -R1 = R4 - R1 (NS); -R2 = R4 - R2 (NS); -R3 = R4 - R3 (NS); -R4 = R4 - R4 (NS); -R5 = R4 - R5 (NS); -R6 = R4 - R6 (NS); -R7 = R4 - R7 (NS); -CHECKREG r0, 0x4000000A; -CHECKREG r1, 0x2DDDDDFE; -CHECKREG r2, 0x21233406; -CHECKREG r3, 0x0F011204; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x987654E3; -CHECKREG r6, 0x8BBBAAEB; -CHECKREG r7, 0x79998889; - -imm32 r0, 0x95678911; -imm32 r1, 0x8789ab1d; -imm32 r2, 0x74445515; -imm32 r3, 0x36667717; -imm32 r4, 0x3567891b; -imm32 r5, 0x6e89ab1d; -imm32 r6, 0x74e45515; -imm32 r7, 0x866e7777; -R0 = R5 - R0 (NS); -R1 = R5 - R1 (NS); -R2 = R5 - R2 (NS); -R3 = R5 - R3 (NS); -R4 = R5 - R4 (NS); -R5 = R5 - R5 (NS); -R6 = R5 - R6 (NS); -R7 = R5 - R7 (NS); -CHECKREG r0, 0xD922220C; -CHECKREG r1, 0xE7000000; -CHECKREG r2, 0xFA455608; -CHECKREG r3, 0x38233406; -CHECKREG r4, 0x39222202; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x8B1BAAEB; -CHECKREG r7, 0x79918889; - -imm32 r0, 0x5a678911; -imm32 r1, 0x67c9ab1d; -imm32 r2, 0x744d5515; -imm32 r3, 0x8666b717; -imm32 r4, 0x9567891b; -imm32 r5, 0x6789db1d; -imm32 r6, 0x74445f15; -imm32 r7, 0x866677f7; -R0 = R6 - R0 (NS); -R1 = R6 - R1 (NS); -R2 = R6 - R2 (NS); -R3 = R6 - R3 (NS); -R4 = R6 - R4 (NS); -R5 = R6 - R5 (NS); -R6 = R6 - R6 (NS); -R7 = R6 - R7 (NS); -CHECKREG r0, 0x19DCD604; -CHECKREG r1, 0x0C7AB3F8; -CHECKREG r2, 0xFFF70A00; -CHECKREG r3, 0xEDDDA7FE; -CHECKREG r4, 0xDEDCD5FA; -CHECKREG r5, 0x0CBA83F8; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x79998809; - -imm32 r0, 0x25678911; -imm32 r1, 0x2389ab1d; -imm32 r2, 0x3a455515; -imm32 r3, 0x46d66717; -imm32 r4, 0x556b891b; -imm32 r5, 0x6789cb1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0 = R7 - R0 (NS); -R1 = R7 - R1 (NS); -R2 = R7 - R2 (NS); -R3 = R7 - R3 (NS); -R4 = R7 - R4 (NS); -R5 = R7 - R5 (NS); -R6 = R7 - R6 (NS); -R7 = R7 - R7 (NS); -CHECKREG r0, 0x60FEEE66; -CHECKREG r1, 0x62DCCC5A; -CHECKREG r2, 0x4C212262; -CHECKREG r3, 0x3F901060; -CHECKREG r4, 0x30FAEE5C; -CHECKREG r5, 0x1EDCAC5A; -CHECKREG r6, 0x12222262; -CHECKREG r7, 0x00000000; - -imm32 r0, 0xd5678911; -imm32 r1, 0x2e89ab1d; -imm32 r2, 0x34f45515; -imm32 r3, 0x466b7717; -imm32 r4, 0x5567c91b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445115; -imm32 r7, 0x866a7d77; -R3 = R1 - R4 (S); -R7 = R4 - R6 (S); -R2 = R7 - R7 (S); -R4 = R5 - R0 (S); -R5 = R3 - R1 (S); -R6 = R2 - R3 (S); -R0 = R0 - R2 (S); -R1 = R6 - R5 (S); -CHECKREG r0, 0xD5678911; -CHECKREG r1, 0x7C45E719; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0xD921E202; -CHECKREG r4, 0x7FFFFFFF; -CHECKREG r5, 0xAA9836E5; -CHECKREG r6, 0x26DE1DFE; -CHECKREG r7, 0xE1237806; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R3 = R3 - R3 (S); -R1 = R7 - R6 (S); -R4 = R1 - R2 (S); -R7 = R4 - R0 (S); -R5 = R6 - R4 (S); -R2 = R5 - R5 (S); -R6 = R2 - R1 (S); -R0 = R0 - R7 (S); -CHECKREG r0, 0x7FFFFFFF; -CHECKREG r1, 0x80000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x80000000; -CHECKREG r5, 0x7FFFFFFF; -CHECKREG r6, 0x7FFFFFFF; -CHECKREG r7, 0x80000000; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rmm.s b/sim/testsuite/sim/bfin/c_dsp32alu_rmm.s deleted file mode 100644 index 85170a8..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rmm.s +++ /dev/null @@ -1,264 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rmm/c_dsp32alu_rmm.dsp -// Spec Reference: dsp32alu dreg = -/- ( dreg, dreg) -# mach: bfin - -.include "testutils.inc" - start - - - - -// ALU operations include parallel addition, subtraction -// and 32-bit data. If an operation use a single ALU only, it uses ALU0. - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0 = R0 -|- R0; -R1 = R0 -|- R1; -R2 = R0 -|- R2; -R3 = R0 -|- R3; -R4 = R0 -|- R4; -R5 = R0 -|- R5; -R6 = R0 -|- R6; -R7 = R0 -|- R7; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0xD87754E3; -CHECKREG r2, 0xCBBCAAEB; -CHECKREG r3, 0xB99A88E9; -CHECKREG r4, 0xAA9976E5; -CHECKREG r5, 0x987754E3; -CHECKREG r6, 0x8BBCAAEB; -CHECKREG r7, 0x799A8889; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r4, 0xd8889929; -imm32 r5, 0xeaaabb2b; -imm32 r6, 0xfcccdd2d; -imm32 r7, 0x0eeeffff; -R0 = R1 -|- R0; -R1 = R1 -|- R1; -R2 = R1 -|- R2; -R3 = R1 -|- R3; -R4 = R1 -|- R4; -R5 = R1 -|- R5; -R6 = R1 -|- R6; -R7 = R1 -|- R7; -CHECKREG r0, 0x12222202; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x4BBCAADB; -CHECKREG r3, 0x399A88D9; -CHECKREG r4, 0x277866D7; -CHECKREG r5, 0x155644D5; -CHECKREG r6, 0x033422D3; -CHECKREG r7, 0xF1120001; - -imm32 r0, 0x416789ab; -imm32 r1, 0x6289abcd; -imm32 r2, 0x43445555; -imm32 r3, 0x64667777; -imm32 r4, 0x456789ab; -imm32 r5, 0x6689abcd; -imm32 r6, 0x47445555; -imm32 r7, 0x68667777; -R0 = R2 -|- R0; -R1 = R2 -|- R1; -R2 = R2 -|- R2; -R3 = R2 -|- R3; -R4 = R2 -|- R4; -R5 = R2 -|- R5; -R6 = R2 -|- R6; -R7 = R2 -|- R7; -CHECKREG r0, 0x01DDCBAA; -CHECKREG r1, 0xE0BBA988; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x9B9A8889; -CHECKREG r4, 0xBA997655; -CHECKREG r5, 0x99775433; -CHECKREG r6, 0xB8BCAAAB; -CHECKREG r7, 0x979A8889; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -R0 = R3 -|- R0; -R1 = R3 -|- R1; -R2 = R3 -|- R2; -R3 = R3 -|- R3; -R4 = R3 -|- R4; -R5 = R3 -|- R5; -R6 = R3 -|- R6; -R7 = R3 -|- R7; -CHECKREG r0, 0x30FFEDFC; -CHECKREG r1, 0x1EDDCBFA; -CHECKREG r2, 0x12222202; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x456789AB; -CHECKREG r5, 0x6689ABCD; -CHECKREG r6, 0x47445555; -CHECKREG r7, 0x68667777; - -imm32 r0, 0x4537891b; -imm32 r1, 0x6759ab2d; -imm32 r2, 0x44555535; -imm32 r3, 0x66665747; -imm32 r4, 0x88789565; -imm32 r5, 0xaa8abb5b; -imm32 r6, 0xcc9cdd85; -imm32 r7, 0xeeaeff9f; -R0 = R4 -|- R0; -R1 = R4 -|- R1; -R2 = R4 -|- R2; -R3 = R4 -|- R3; -R4 = R4 -|- R4; -R5 = R4 -|- R5; -R6 = R4 -|- R6; -R7 = R4 -|- R7; -CHECKREG r0, 0x43410C4A; -CHECKREG r1, 0x211FEA38; -CHECKREG r2, 0x44234030; -CHECKREG r3, 0x22123E1E; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x557644A5; -CHECKREG r6, 0x3364227B; -CHECKREG r7, 0x11520061; - -imm32 r0, 0x456b89ab; -imm32 r1, 0x69764bcd; -imm32 r2, 0x49736564; -imm32 r3, 0x61278394; -imm32 r4, 0x98876439; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0xcccc1ddd; -imm32 r7, 0x12346fff; -R0 = R5 -|- R0; -R1 = R5 -|- R1; -R2 = R5 -|- R2; -R3 = R5 -|- R3; -R4 = R5 -|- R4; -R5 = R5 -|- R5; -R6 = R5 -|- R6; -R7 = R5 -|- R7; -CHECKREG r0, 0x653F8210; -CHECKREG r1, 0x4134BFEE; -CHECKREG r2, 0x6137A657; -CHECKREG r3, 0x49838827; -CHECKREG r4, 0x1223A782; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x3334E223; -CHECKREG r7, 0xEDCC9001; - -imm32 r0, 0x456739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0x03456755; -imm32 r3, 0x66666777; -imm32 r4, 0x12345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R0 = R6 -|- R0; -R1 = R6 -|- R1; -R2 = R6 -|- R2; -R3 = R6 -|- R3; -R4 = R6 -|- R4; -R5 = R6 -|- R5; -R6 = R6 -|- R6; -R7 = R6 -|- R7; -CHECKREG r0, 0xBECB572B; -CHECKREG r1, 0x9CC94509; -CHECKREG r2, 0x00ED2981; -CHECKREG r3, 0x9DCC295F; -CHECKREG r4, 0xF1FE3A3D; -CHECKREG r5, 0xBECB056B; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0xEDCCA981; - -imm32 r0, 0x476789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0x23456755; -imm32 r3, 0x56789007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcd2ff7; -R0 = R7 -|- R0; -R1 = R7 -|- R1; -R2 = R7 -|- R2; -R3 = R7 -|- R3; -R4 = R7 -|- R4; -R5 = R7 -|- R5; -R6 = R7 -|- R6; -R7 = R7 -|- R7; -CHECKREG r0, 0x6466A64C; -CHECKREG r1, 0x4454842A; -CHECKREG r2, 0x8888C8A2; -CHECKREG r3, 0x55559FF0; -CHECKREG r4, 0x3333785E; -CHECKREG r5, 0x0123243C; -CHECKREG r6, 0x2222127A; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x456739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0x03456755; -imm32 r3, 0x66666777; -imm32 r4, 0x12345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R4 = R4 -|- R7 (S); -R5 = R5 -|- R5 (CO); -R2 = R6 -|- R3 (SCO); -R6 = R0 -|- R4 (S); -R0 = R1 -|- R6 (S); -R2 = R2 -|- R1 (CO); -R1 = R3 -|- R0 (CO); -R7 = R7 -|- R4 (SCO); -CHECKREG r0, 0x2202123C; -CHECKREG r1, 0x553B4464; -CHECKREG r2, 0x51FF1897; -CHECKREG r3, 0x66666777; -CHECKREG r4, 0x0000001A; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x45673991; -CHECKREG r7, 0x56651234; - -imm32 r0, 0x476789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0x23456755; -imm32 r3, 0x56789007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcd2ff7; -R3 = R4 -|- R0 (S); -R5 = R5 -|- R1 (SCO); -R2 = R2 -|- R2 (S); -R7 = R7 -|- R3 (CO); -R4 = R3 -|- R4 (CO); -R0 = R1 -|- R5 (S); -R1 = R0 -|- R6 (SCO); -R6 = R6 -|- R7 (SCO); -CHECKREG r0, 0x078B2BCD; -CHECKREG r1, 0x0E507DE0; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x31332DEE; -CHECKREG r4, 0x7655B899; -CHECKREG r5, 0x5FEE8000; -CHECKREG r6, 0xA2E387A2; -CHECKREG r7, 0x02097A9A; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rmp.s b/sim/testsuite/sim/bfin/c_dsp32alu_rmp.s deleted file mode 100644 index b15397d..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rmp.s +++ /dev/null @@ -1,264 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rmp/c_dsp32alu_rmp.dsp -// Spec Reference: dsp32alu dreg = -/+ ( dreg, dreg) -# mach: bfin - -.include "testutils.inc" - start - - - - -// ALU operations include parallel addition, subtraction -// and 32-bit data. If an operation use a single ALU only, it uses ALU0. - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0 = R0 -|+ R0; -R1 = R0 -|+ R1; -R2 = R0 -|+ R2; -R3 = R0 -|+ R3; -R4 = R0 -|+ R4; -R5 = R0 -|+ R5; -R6 = R0 -|+ R6; -R7 = R0 -|+ R7; -CHECKREG r0, 0x00001222; -CHECKREG r1, 0xD877BD3F; -CHECKREG r2, 0xCBBC6737; -CHECKREG r3, 0xB99A8939; -CHECKREG r4, 0xAA999B3D; -CHECKREG r5, 0x9877BD3F; -CHECKREG r6, 0x8BBC6737; -CHECKREG r7, 0x799A8999; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r4, 0xd8889929; -imm32 r5, 0xeaaabb2b; -imm32 r6, 0xfcccdd2d; -imm32 r7, 0x0eeeffff; -R0 = R1 -|+ R0; -R1 = R1 -|+ R1; -R2 = R1 -|+ R2; -R3 = R1 -|+ R3; -R4 = R1 -|+ R4; -R5 = R1 -|+ R5; -R6 = R1 -|+ R6; -R7 = R1 -|+ R7; -CHECKREG r0, 0x12223458; -CHECKREG r1, 0x0000565A; -CHECKREG r2, 0x4BBCAB7F; -CHECKREG r3, 0x399ACD81; -CHECKREG r4, 0x2778EF83; -CHECKREG r5, 0x15561185; -CHECKREG r6, 0x03343387; -CHECKREG r7, 0xF1125659; - -imm32 r0, 0x416789ab; -imm32 r1, 0x6289abcd; -imm32 r2, 0x43445555; -imm32 r3, 0x64667777; -imm32 r4, 0x456789ab; -imm32 r5, 0x6689abcd; -imm32 r6, 0x47445555; -imm32 r7, 0x68667777; -R0 = R2 -|+ R0; -R1 = R2 -|+ R1; -R2 = R2 -|+ R2; -R3 = R2 -|+ R3; -R4 = R2 -|+ R4; -R5 = R2 -|+ R5; -R6 = R2 -|+ R6; -R7 = R2 -|+ R7; -CHECKREG r0, 0x01DDDF00; -CHECKREG r1, 0xE0BB0122; -CHECKREG r2, 0x0000AAAA; -CHECKREG r3, 0x9B9A2221; -CHECKREG r4, 0xBA993455; -CHECKREG r5, 0x99775677; -CHECKREG r6, 0xB8BCFFFF; -CHECKREG r7, 0x979A2221; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -R0 = R3 -|+ R0; -R1 = R3 -|+ R1; -R2 = R3 -|+ R2; -R3 = R3 -|+ R3; -R4 = R3 -|+ R4; -R5 = R3 -|+ R5; -R6 = R3 -|+ R6; -R7 = R3 -|+ R7; -CHECKREG r4, 0x456722A3; -CHECKREG r5, 0x668944C5; -CHECKREG r6, 0x4744EE4D; -CHECKREG r7, 0x6866106F; -CHECKREG r4, 0x456722A3; -CHECKREG r5, 0x668944C5; -CHECKREG r6, 0x4744EE4D; -CHECKREG r7, 0x6866106F; - -imm32 r0, 0x4537891b; -imm32 r1, 0x6759ab2d; -imm32 r2, 0x44555535; -imm32 r3, 0x66665747; -imm32 r4, 0x88789565; -imm32 r5, 0xaa8abb5b; -imm32 r6, 0xcc9cdd85; -imm32 r7, 0xeeaeff9f; -R0 = R4 -|+ R0; -R1 = R4 -|+ R1; -R2 = R4 -|+ R2; -R3 = R4 -|+ R3; -R4 = R4 -|+ R4; -R5 = R4 -|+ R5; -R6 = R4 -|+ R6; -R7 = R4 -|+ R7; -CHECKREG r0, 0x43411E80; -CHECKREG r1, 0x211F4092; -CHECKREG r2, 0x4423EA9A; -CHECKREG r3, 0x2212ECAC; -CHECKREG r4, 0x00002ACA; -CHECKREG r5, 0x5576E625; -CHECKREG r6, 0x3364084F; -CHECKREG r7, 0x11522A69; - -imm32 r0, 0x456b89ab; -imm32 r1, 0x69764bcd; -imm32 r2, 0x49736564; -imm32 r3, 0x61278394; -imm32 r4, 0x98876439; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0xcccc1ddd; -imm32 r7, 0x12346fff; -R0 = R5 -|+ R0; -R1 = R5 -|+ R1; -R2 = R5 -|+ R2; -R3 = R5 -|+ R3; -R4 = R5 -|+ R4; -R5 = R5 -|+ R5; -R6 = R5 -|+ R6; -R7 = R5 -|+ R7; -CHECKREG r0, 0x653F9566; -CHECKREG r1, 0x41345788; -CHECKREG r2, 0x6137711F; -CHECKREG r3, 0x49838F4F; -CHECKREG r4, 0x12236FF4; -CHECKREG r5, 0x00001776; -CHECKREG r6, 0x33343553; -CHECKREG r7, 0xEDCC8775; - -imm32 r0, 0x456739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0x03456755; -imm32 r3, 0x66666777; -imm32 r4, 0x12345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R0 = R6 -|+ R0; -R1 = R6 -|+ R1; -R2 = R6 -|+ R2; -R3 = R6 -|+ R3; -R4 = R6 -|+ R4; -R5 = R6 -|+ R5; -R6 = R6 -|+ R6; -R7 = R6 -|+ R7; -CHECKREG r0, 0xBECBCA81; -CHECKREG r1, 0x9CC9DCA3; -CHECKREG r2, 0x00EDF82B; -CHECKREG r3, 0x9DCCF84D; -CHECKREG r4, 0xF1FEE76F; -CHECKREG r5, 0xBECB1C41; -CHECKREG r6, 0x000021AC; -CHECKREG r7, 0xEDCC782B; - -imm32 r0, 0x476789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0x23456755; -imm32 r3, 0x56789007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcd2ff7; -R0 = R7 -|+ R0; -R1 = R7 -|+ R1; -R2 = R7 -|+ R2; -R3 = R7 -|+ R3; -R4 = R7 -|+ R4; -R5 = R7 -|+ R5; -R6 = R7 -|+ R6; -R7 = R7 -|+ R7; -CHECKREG r0, 0x6466B9A2; -CHECKREG r1, 0x4454DBC4; -CHECKREG r2, 0x8888974C; -CHECKREG r3, 0x5555BFFE; -CHECKREG r4, 0x3333E790; -CHECKREG r5, 0x01233BB2; -CHECKREG r6, 0x22224D74; -CHECKREG r7, 0x00005FEE; - -imm32 r0, 0x456739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0x03456755; -imm32 r3, 0x66666777; -imm32 r4, 0x12345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R4 = R4 -|+ R7 (S); -R5 = R5 -|+ R5 (CO); -R2 = R6 -|+ R3 (SCO); -R6 = R0 -|+ R4 (S); -R0 = R1 -|+ R6 (S); -R2 = R2 -|+ R1 (CO); -R1 = R3 -|+ R0 (CO); -R7 = R7 -|+ R4 (SCO); -CHECKREG r0, 0x22027FFF; -CHECKREG r1, 0xE7764464; -CHECKREG r2, 0xE99990E4; -CHECKREG r3, 0x66666777; -CHECKREG r4, 0x00007FFF; -CHECKREG r5, 0x16D60000; -CHECKREG r6, 0x45677FFF; -CHECKREG r7, 0x7FFF1234; - -imm32 r0, 0x476789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0x23456755; -imm32 r3, 0x56789007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcd2ff7; -R3 = R4 -|+ R0 (S); -R5 = R5 -|+ R1 (SCO); -R2 = R2 -|+ R2 (S); -R7 = R7 -|+ R3 (CO); -R4 = R3 -|+ R4 (CO); -R0 = R1 -|+ R5 (S); -R1 = R0 -|+ R6 (SCO); -R6 = R6 -|+ R7 (SCO); -CHECKREG r0, 0x7FFF8000; -CHECKREG r1, 0x9D7D7FFF; -CHECKREG r2, 0x00007FFF; -CHECKREG r3, 0x31338000; -CHECKREG r4, 0x3799B899; -CHECKREG r5, 0xB7888000; -CHECKREG r6, 0x7FFFD9B4; -CHECKREG r7, 0xAFF77A9A; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rp.s b/sim/testsuite/sim/bfin/c_dsp32alu_rp.s deleted file mode 100644 index 6984bc4..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rp.s +++ /dev/null @@ -1,262 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rp/c_dsp32alu_rp.dsp -// Spec Reference: dsp32alu -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0xa5678911; -imm32 r1, 0x2a89ab1d; -imm32 r2, 0x34a45515; -imm32 r3, 0x466a7717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445a15; -imm32 r7, 0x866677a7; -R0 = R0 + R0 (NS); -R1 = R0 + R1 (NS); -R2 = R0 + R2 (NS); -R3 = R0 + R3 (NS); -R4 = R0 + R4 (NS); -R5 = R0 + R5 (NS); -R6 = R0 + R6 (NS); -R7 = R0 + R7 (NS); -CHECKREG r0, 0x4ACF1222; -CHECKREG r1, 0x7558BD3F; -CHECKREG r2, 0x7F736737; -CHECKREG r3, 0x91398939; -CHECKREG r4, 0xA0369B3D; -CHECKREG r5, 0xB258BD3F; -CHECKREG r6, 0xBF136C37; -CHECKREG r7, 0xD13589C9; - -imm32 r0, 0xabc78911; -imm32 r1, 0x27c9ab1d; -imm32 r2, 0x344c5515; -imm32 r3, 0x4666c717; -imm32 r4, 0x5567c91b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445c15; -imm32 r7, 0x866677c7; -R0 = R1 + R0 (NS); -R1 = R1 + R1 (NS); -R2 = R1 + R2 (NS); -R3 = R1 + R3 (NS); -R4 = R1 + R4 (NS); -R5 = R1 + R5 (NS); -R6 = R1 + R6 (NS); -R7 = R1 + R7 (NS); -CHECKREG r0, 0xD391342E; -CHECKREG r1, 0x4F93563A; -CHECKREG r2, 0x83DFAB4F; -CHECKREG r3, 0x95FA1D51; -CHECKREG r4, 0xA4FB1F55; -CHECKREG r5, 0xB71D0157; -CHECKREG r6, 0xC3D7B24F; -CHECKREG r7, 0xD5F9CE01; - -imm32 r0, 0xdd678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46d67717; -imm32 r4, 0x5567891b; -imm32 r5, 0x678dab1d; -imm32 r6, 0x7444d515; -imm32 r7, 0x86667d77; -R0 = R2 + R0 (NS); -R1 = R2 + R1 (NS); -R2 = R2 + R2 (NS); -R3 = R2 + R3 (NS); -R4 = R2 + R4 (NS); -R5 = R2 + R5 (NS); -R6 = R2 + R6 (NS); -R7 = R2 + R7 (NS); -CHECKREG r0, 0x11ABDE26; -CHECKREG r1, 0x5BCE0032; -CHECKREG r2, 0x6888AA2A; -CHECKREG r3, 0xAF5F2141; -CHECKREG r4, 0xBDF03345; -CHECKREG r5, 0xD0165547; -CHECKREG r6, 0xDCCD7F3F; -CHECKREG r7, 0xEEEF27A1; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0 = R3 + R0 (NS); -R1 = R3 + R1 (NS); -R2 = R3 + R2 (NS); -R3 = R3 + R3 (NS); -R4 = R3 + R4 (NS); -R5 = R3 + R5 (NS); -R6 = R3 + R6 (NS); -R7 = R3 + R7 (NS); -CHECKREG r0, 0x5BCE0028; -CHECKREG r1, 0x6DF02234; -CHECKREG r2, 0x7AAACC2C; -CHECKREG r3, 0x8CCCEE2E; -CHECKREG r4, 0xE2347749; -CHECKREG r5, 0xF456994B; -CHECKREG r6, 0x01114343; -CHECKREG r7, 0x133365A5; - -imm32 r0, 0xee678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34e45515; -imm32 r3, 0x46667717; -imm32 r4, 0x556e891b; -imm32 r5, 0x6789eb1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667e77; -R0 = R4 + R0 (NS); -R1 = R4 + R1 (NS); -R2 = R4 + R2 (NS); -R3 = R4 + R3 (NS); -R4 = R4 + R4 (NS); -R5 = R4 + R5 (NS); -R6 = R4 + R6 (NS); -R7 = R4 + R7 (NS); -CHECKREG r0, 0x43D6122C; -CHECKREG r1, 0x7CF83438; -CHECKREG r2, 0x8A52DE30; -CHECKREG r3, 0x9BD50032; -CHECKREG r4, 0xAADD1236; -CHECKREG r5, 0x1266FD53; -CHECKREG r6, 0x1F21674B; -CHECKREG r7, 0x314390AD; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0 = R5 + R0 (NS); -R1 = R5 + R1 (NS); -R2 = R5 + R2 (NS); -R3 = R5 + R3 (NS); -R4 = R5 + R4 (NS); -R5 = R5 + R5 (NS); -R6 = R5 + R6 (NS); -R7 = R5 + R7 (NS); -CHECKREG r0, 0x7CF1342E; -CHECKREG r1, 0x8F13563A; -CHECKREG r2, 0x9BCE0032; -CHECKREG r3, 0xADF02234; -CHECKREG r4, 0xBCF13438; -CHECKREG r5, 0xCF13563A; -CHECKREG r6, 0x4357AB4F; -CHECKREG r7, 0x5579CDB1; - -imm32 r0, 0xff678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34f45515; -imm32 r3, 0x46667717; -imm32 r4, 0x556f891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x7444f515; -imm32 r7, 0x86667f77; -R0 = R6 + R0 (NS); -R1 = R6 + R1 (NS); -R2 = R6 + R2 (NS); -R3 = R6 + R3 (NS); -R4 = R6 + R4 (NS); -R5 = R6 + R5 (NS); -R6 = R6 + R6 (NS); -R7 = R6 + R7 (NS); -CHECKREG r0, 0x73AC7E26; -CHECKREG r1, 0x9BCEA032; -CHECKREG r2, 0xA9394A2A; -CHECKREG r3, 0xBAAB6C2C; -CHECKREG r4, 0xC9B47E30; -CHECKREG r5, 0xDBCEA032; -CHECKREG r6, 0xE889EA2A; -CHECKREG r7, 0x6EF069A1; - -imm32 r0, 0xed678911; -imm32 r1, 0x27d9ab1d; -imm32 r2, 0x344d5515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567c91b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445c15; -imm32 r7, 0x866677c7; -R0 = R7 + R0 (NS); -R1 = R7 + R1 (NS); -R2 = R7 + R2 (NS); -R3 = R7 + R3 (NS); -R4 = R7 + R4 (NS); -R5 = R7 + R5 (NS); -R6 = R7 + R6 (NS); -R7 = R7 + R7 (NS); -CHECKREG r0, 0x73CE00D8; -CHECKREG r1, 0xAE4022E4; -CHECKREG r2, 0xBAB3CCDC; -CHECKREG r3, 0xCCCCEEDE; -CHECKREG r4, 0xDBCE40E2; -CHECKREG r5, 0xEDF022E4; -CHECKREG r6, 0xFAAAD3DC; -CHECKREG r7, 0x0CCCEF8E; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R3 = R1 + R4 (S); -R7 = R4 + R6 (S); -R2 = R7 + R7 (S); -R4 = R5 + R0 (S); -R5 = R3 + R1 (S); -R6 = R2 + R3 (S); -R0 = R0 + R2 (S); -R1 = R6 + R5 (S); -CHECKREG r0, 0x7FFFFFFF; -CHECKREG r1, 0x7FFFFFFF; -CHECKREG r2, 0x7FFFFFFF; -CHECKREG r3, 0x7CF13438; -CHECKREG r4, 0x7CF1342E; -CHECKREG r5, 0x7FFFFFFF; -CHECKREG r6, 0x7FFFFFFF; -CHECKREG r7, 0x7FFFFFFF; - -imm32 r0, 0x55678911; -imm32 r1, 0x6a89ab1d; -imm32 r2, 0x74d45515; -imm32 r3, 0x866f7717; -imm32 r4, 0x5567c91b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R3 = R3 + R3 (S); -R1 = R7 + R6 (S); -R4 = R1 + R2 (S); -R7 = R4 + R0 (S); -R5 = R6 + R4 (S); -R2 = R5 + R5 (S); -R6 = R2 + R1 (S); -R0 = R0 + R7 (S); -CHECKREG r0, 0x7FFFFFFF; -CHECKREG r1, 0xFAAACC8C; -CHECKREG r2, 0x7FFFFFFF; -CHECKREG r3, 0x80000000; -CHECKREG r4, 0x6F7F21A1; -CHECKREG r5, 0x7FFFFFFF; -CHECKREG r6, 0x7AAACC8B; -CHECKREG r7, 0x7FFFFFFF; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rpm.s b/sim/testsuite/sim/bfin/c_dsp32alu_rpm.s deleted file mode 100644 index ebdec07..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rpm.s +++ /dev/null @@ -1,264 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rpm/c_dsp32alu_rpm.dsp -// Spec Reference: dsp32alu dreg = +/- ( dreg, dreg) -# mach: bfin - -.include "testutils.inc" - start - - - - -// ALU operations include parallel addition, subtraction -// and 32-bit data. If an operation use a single ALU only, it uses ALU0. - -imm32 r0, 0x65678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34845515; -imm32 r3, 0x46697717; -imm32 r4, 0x5567191b; -imm32 r5, 0x6789a31d; -imm32 r6, 0x74445545; -imm32 r7, 0x86667779; -R0 = R0 +|- R0; -R1 = R0 +|- R1; -R2 = R0 +|- R2; -R3 = R0 +|- R3; -R4 = R0 +|- R4; -R5 = R0 +|- R5; -R6 = R0 +|- R6; -R7 = R0 +|- R7; -CHECKREG r0, 0xCACE0000; -CHECKREG r1, 0xF25754E3; -CHECKREG r2, 0xFF52AAEB; -CHECKREG r3, 0x113788E9; -CHECKREG r4, 0x2035E6E5; -CHECKREG r5, 0x32575CE3; -CHECKREG r6, 0x3F12AABB; -CHECKREG r7, 0x51348887; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r4, 0xd8889929; -imm32 r5, 0xeaaabb2b; -imm32 r6, 0xfcccdd2d; -imm32 r7, 0x0eeeffff; -R0 = R1 +|- R0; -R1 = R1 +|- R1; -R2 = R1 +|- R2; -R3 = R1 +|- R3; -R4 = R1 +|- R4; -R5 = R1 +|- R5; -R6 = R1 +|- R6; -R7 = R1 +|- R7; -CHECKREG r0, 0x3CF02202; -CHECKREG r1, 0x4F120000; -CHECKREG r2, 0x0356AADB; -CHECKREG r3, 0x157888D9; -CHECKREG r4, 0x279A66D7; -CHECKREG r5, 0x39BC44D5; -CHECKREG r6, 0x4BDE22D3; -CHECKREG r7, 0x5E000001; - -imm32 r0, 0x416789ab; -imm32 r1, 0x6289abcd; -imm32 r2, 0x43445555; -imm32 r3, 0x64667777; -imm32 r4, 0x456789ab; -imm32 r5, 0x6689abcd; -imm32 r6, 0x47445555; -imm32 r7, 0x68667777; -R0 = R2 +|- R0; -R1 = R2 +|- R1; -R2 = R2 +|- R2; -R3 = R2 +|- R3; -R4 = R2 +|- R4; -R5 = R2 +|- R5; -R6 = R2 +|- R6; -R7 = R2 +|- R7; -CHECKREG r0, 0x84ABCBAA; -CHECKREG r1, 0xA5CDA988; -CHECKREG r2, 0x86880000; -CHECKREG r3, 0xEAEE8889; -CHECKREG r4, 0xCBEF7655; -CHECKREG r5, 0xED115433; -CHECKREG r6, 0xCDCCAAAB; -CHECKREG r7, 0xEEEE8889; - -imm32 r0, 0xa567892b; -imm32 r1, 0xaa89ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6a67727; -imm32 r0, 0x9a67892b; -imm32 r1, 0xa7a9ab2d; -imm32 r2, 0xb44a5525; -imm32 r3, 0xc666a727; -R0 = R3 +|- R0; -R1 = R3 +|- R1; -R2 = R3 +|- R2; -R3 = R3 +|- R3; -R4 = R3 +|- R4; -R5 = R3 +|- R5; -R6 = R3 +|- R6; -R7 = R3 +|- R7; -CHECKREG r0, 0x60CD1DFC; -CHECKREG r1, 0x6E0FFBFA; -CHECKREG r2, 0x7AB05202; -CHECKREG r3, 0x8CCC0000; -CHECKREG r4, 0x58BB89AB; -CHECKREG r5, 0x79DDABCD; -CHECKREG r6, 0x5A985555; -CHECKREG r7, 0x7BBA7777; - -imm32 r0, 0x4537891b; -imm32 r1, 0x6759ab2d; -imm32 r2, 0x44555535; -imm32 r3, 0x66665747; -imm32 r4, 0x88789565; -imm32 r5, 0xaa8abb5b; -imm32 r6, 0xcc9cdd85; -imm32 r7, 0xeeaeff9f; -R0 = R4 +|- R0; -R1 = R4 +|- R1; -R2 = R4 +|- R2; -R3 = R4 +|- R3; -R4 = R4 +|- R4; -R5 = R4 +|- R5; -R6 = R4 +|- R6; -R7 = R4 +|- R7; -CHECKREG r0, 0xCDAF0C4A; -CHECKREG r1, 0xEFD1EA38; -CHECKREG r2, 0xCCCD4030; -CHECKREG r3, 0xEEDE3E1E; -CHECKREG r4, 0x10F00000; -CHECKREG r5, 0xBB7A44A5; -CHECKREG r6, 0xDD8C227B; -CHECKREG r7, 0xFF9E0061; - -imm32 r0, 0x456b89ab; -imm32 r1, 0x69764bcd; -imm32 r2, 0x49736564; -imm32 r3, 0x61278394; -imm32 r4, 0x98876439; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0xcccc1ddd; -imm32 r7, 0x12346fff; -R0 = R5 +|- R0; -R1 = R5 +|- R1; -R2 = R5 +|- R2; -R3 = R5 +|- R3; -R4 = R5 +|- R4; -R5 = R5 +|- R5; -R6 = R5 +|- R6; -R7 = R5 +|- R7; -CHECKREG r0, 0xF0158210; -CHECKREG r1, 0x1420BFEE; -CHECKREG r2, 0xF41DA657; -CHECKREG r3, 0x0BD18827; -CHECKREG r4, 0x4331A782; -CHECKREG r5, 0x55540000; -CHECKREG r6, 0x2220E223; -CHECKREG r7, 0x67889001; - -imm32 r0, 0x456739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0x03456755; -imm32 r3, 0x66666777; -imm32 r4, 0x12345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R0 = R6 +|- R0; -R1 = R6 +|- R1; -R2 = R6 +|- R2; -R3 = R6 +|- R3; -R4 = R6 +|- R4; -R5 = R6 +|- R5; -R6 = R6 +|- R6; -R7 = R6 +|- R7; -CHECKREG r0, 0x4999572B; -CHECKREG r1, 0x6B9B4509; -CHECKREG r2, 0x07772981; -CHECKREG r3, 0x6A98295F; -CHECKREG r4, 0x16663A3D; -CHECKREG r5, 0x4999056B; -CHECKREG r6, 0x08640000; -CHECKREG r7, 0x1A98A981; - -imm32 r0, 0xb76789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0x2b456755; -imm32 r3, 0x56789007; -imm32 r4, 0x78bab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcdbff7; -R0 = R7 +|- R0; -R1 = R7 +|- R1; -R2 = R7 +|- R2; -R3 = R7 +|- R3; -R4 = R7 +|- R4; -R5 = R7 +|- R5; -R6 = R7 +|- R6; -R7 = R7 +|- R7; -CHECKREG r0, 0x6334364C; -CHECKREG r1, 0x1346142A; -CHECKREG r2, 0xD71258A2; -CHECKREG r3, 0x02452FF0; -CHECKREG r4, 0x2487085E; -CHECKREG r5, 0x5677B43C; -CHECKREG r6, 0x3578A27A; -CHECKREG r7, 0x579A0000; -imm32 r0, 0x456739ab; -imm32 r1, 0x67694bcd; -imm32 r2, 0x03456755; -imm32 r3, 0x66666777; -imm32 r4, 0x12345699; -imm32 r5, 0x45678b6b; -imm32 r6, 0x043290d6; -imm32 r7, 0x1234567f; -R4 = R4 +|- R7 (S); -R5 = R5 +|- R5 (CO); -R2 = R6 +|- R3 (SCO); -R6 = R0 +|- R4 (S); -R0 = R1 +|- R6 (S); -R2 = R2 +|- R1 (CO); -R1 = R3 +|- R0 (CO); -R7 = R7 +|- R4 (SCO); -CHECKREG r0, 0x7FFF123C; -CHECKREG r1, 0x553BE665; -CHECKREG r2, 0x1ECBE769; -CHECKREG r3, 0x66666777; -CHECKREG r4, 0x2468001A; -CHECKREG r5, 0x00008ACE; -CHECKREG r6, 0x69CF3991; -CHECKREG r7, 0x5665369C; - -imm32 r0, 0xb76789ab; -imm32 r1, 0x6b79abcd; -imm32 r2, 0x2b456755; -imm32 r3, 0x56b89007; -imm32 r4, 0x78bab799; -imm32 r5, 0xaaab0bbb; -imm32 r6, 0x89abbd7d; -imm32 r7, 0xabcd2bf7; -R3 = R4 +|- R0 (S); -R5 = R5 +|- R1 (SCO); -R2 = R2 +|- R2 (S); -R7 = R7 +|- R3 (CO); -R4 = R3 +|- R4 (CO); -R0 = R1 +|- R5 (S); -R1 = R0 +|- R6 (SCO); -R6 = R6 +|- R7 (SCO); -CHECKREG r0, 0x7FFF95A9; -CHECKREG r1, 0xD82C09AA; -CHECKREG r2, 0x568A0000; -CHECKREG r3, 0x30212DEE; -CHECKREG r4, 0x7655A8DB; -CHECKREG r5, 0x5FEE1624; -CHECKREG r6, 0xE18F87B4; -CHECKREG r7, 0xFE09DBEE; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rpp.s b/sim/testsuite/sim/bfin/c_dsp32alu_rpp.s deleted file mode 100644 index 5a69267..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rpp.s +++ /dev/null @@ -1,266 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rpp/c_dsp32alu_rpp.dsp -// Spec Reference: dsp32alu dreg = +/+ ( dreg, dreg) -# mach: bfin - -.include "testutils.inc" - start - - - - -// ALU operations include parallel addition, subtraction -// and 32-bit data. If an operation use a single ALU only, it uses ALU0. - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -R0 = R0 +|+ R0; -R1 = R0 +|+ R1; -R2 = R0 +|+ R2; -R3 = R0 +|+ R3; -R4 = R0 +|+ R4; -R5 = R0 +|+ R5; -R6 = R0 +|+ R6; -R7 = R0 +|+ R7; -CHECKREG r0, 0x2ACE1222; -CHECKREG r1, 0x5257BD3F; -CHECKREG r2, 0x5F126737; -CHECKREG r3, 0x71348939; -CHECKREG r4, 0x80359B3D; -CHECKREG r5, 0x9257BD3F; -CHECKREG r6, 0x9F126737; -CHECKREG r7, 0xB1348999; - -imm32 r0, 0x9567892b; -imm32 r1, 0xa789ab2d; -imm32 r2, 0xb4445525; -imm32 r3, 0xc6667727; -imm32 r4, 0xd8889929; -imm32 r5, 0xeaaabb2b; -imm32 r6, 0xfcccdd2d; -imm32 r7, 0x0eeeffff; -R0 = R1 +|+ R0; -R1 = R1 +|+ R1; -R2 = R1 +|+ R2; -R3 = R1 +|+ R3; -R4 = R1 +|+ R4; -R5 = R1 +|+ R5; -R6 = R1 +|+ R6; -R7 = R1 +|+ R7; -CHECKREG r0, 0x3CF03458; -CHECKREG r1, 0x4F12565A; -CHECKREG r2, 0x0356AB7F; -CHECKREG r3, 0x1578CD81; -CHECKREG r4, 0x279AEF83; -CHECKREG r5, 0x39BC1185; -CHECKREG r6, 0x4BDE3387; -CHECKREG r7, 0x5E005659; - -imm32 r0, 0x416789ab; -imm32 r1, 0x6289abcd; -imm32 r2, 0x43445555; -imm32 r3, 0x64667777; -imm32 r4, 0x456789ab; -imm32 r5, 0x6689abcd; -imm32 r6, 0x47445555; -imm32 r7, 0x68667777; -R0 = R2 +|+ R0; -R1 = R2 +|+ R1; -R2 = R2 +|+ R2; -R3 = R2 +|+ R3; -R4 = R2 +|+ R4; -R5 = R2 +|+ R5; -R6 = R2 +|+ R6; -R7 = R2 +|+ R7; -CHECKREG r0, 0x84ABDF00; -CHECKREG r1, 0xA5CD0122; -CHECKREG r2, 0x8688AAAA; -CHECKREG r3, 0xEAEE2221; -CHECKREG r4, 0xCBEF3455; -CHECKREG r5, 0xED115677; -CHECKREG r6, 0xCDCCFFFF; -CHECKREG r7, 0xEEEE2221; - -imm32 r0, 0xd567892b; -imm32 r1, 0xad89ab2d; -imm32 r2, 0xb4d45525; -imm32 r3, 0xc66d7727; -imm32 r0, 0x9567d92b; -imm32 r1, 0xa789ad2d; -imm32 r2, 0xb44455d5; -imm32 r3, 0xc666772d; -R0 = R3 +|+ R0; -R1 = R3 +|+ R1; -R2 = R3 +|+ R2; -R3 = R3 +|+ R3; -R4 = R3 +|+ R4; -R5 = R3 +|+ R5; -R6 = R3 +|+ R6; -R7 = R3 +|+ R7; -CHECKREG r0, 0x5BCD5058; -CHECKREG r1, 0x6DEF245A; -CHECKREG r2, 0x7AAACD02; -CHECKREG r3, 0x8CCCEE5A; -CHECKREG r4, 0x58BB22AF; -CHECKREG r5, 0x79DD44D1; -CHECKREG r6, 0x5A98EE59; -CHECKREG r7, 0x7BBA107B; - -imm32 r0, 0x4577891b; -imm32 r1, 0x6779ab2d; -imm32 r2, 0x44755535; -imm32 r3, 0x66765747; -imm32 r4, 0x88779565; -imm32 r5, 0xaa7abb5b; -imm32 r6, 0xcc97dd85; -imm32 r7, 0xeeae7f9f; -R0 = R4 +|+ R0; -R1 = R4 +|+ R1; -R2 = R4 +|+ R2; -R3 = R4 +|+ R3; -R4 = R4 +|+ R4; -R5 = R4 +|+ R5; -R6 = R4 +|+ R6; -R7 = R4 +|+ R7; -CHECKREG r0, 0xCDEE1E80; -CHECKREG r1, 0xEFF04092; -CHECKREG r2, 0xCCECEA9A; -CHECKREG r3, 0xEEEDECAC; -CHECKREG r4, 0x10EE2ACA; -CHECKREG r5, 0xBB68E625; -CHECKREG r6, 0xDD85084F; -CHECKREG r7, 0xFF9CAA69; - -imm32 r0, 0x456b89ab; -imm32 r1, 0x69764bcd; -imm32 r2, 0x49736564; -imm32 r3, 0x61278394; -imm32 r4, 0x98876439; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0xcccc1ddd; -imm32 r7, 0x12346fff; -R0 = R5 +|+ R0; -R1 = R5 +|+ R1; -R2 = R5 +|+ R2; -R3 = R5 +|+ R3; -R4 = R5 +|+ R4; -R5 = R5 +|+ R5; -R6 = R5 +|+ R6; -R7 = R5 +|+ R7; -CHECKREG r0, 0xF0159566; -CHECKREG r1, 0x14205788; -CHECKREG r2, 0xF41D711F; -CHECKREG r3, 0x0BD18F4F; -CHECKREG r4, 0x43316FF4; -CHECKREG r5, 0x55541776; -CHECKREG r6, 0x22203553; -CHECKREG r7, 0x67888775; - -imm32 r0, 0xaa6739ab; -imm32 r1, 0x67dd4bcd; -imm32 r2, 0x03456755; -imm32 r3, 0x6b66bb77; -imm32 r4, 0x12345699; -imm32 r5, 0x45b78b6b; -imm32 r6, 0x043b90d6; -imm32 r7, 0x12b4bb7f; -R0 = R6 +|+ R0; -R1 = R6 +|+ R1; -R2 = R6 +|+ R2; -R3 = R6 +|+ R3; -R4 = R6 +|+ R4; -R5 = R6 +|+ R5; -R6 = R6 +|+ R6; -R7 = R6 +|+ R7; -CHECKREG r0, 0xAEA2CA81; -CHECKREG r1, 0x6C18DCA3; -CHECKREG r2, 0x0780F82B; -CHECKREG r3, 0x6FA14C4D; -CHECKREG r4, 0x166FE76F; -CHECKREG r5, 0x49F21C41; -CHECKREG r6, 0x087621AC; -CHECKREG r7, 0x1B2ADD2B; - -imm32 r0, 0x976789ab; -imm32 r1, 0x6979abcd; -imm32 r2, 0x23956755; -imm32 r3, 0x56799007; -imm32 r4, 0x789a9799; -imm32 r5, 0xaaaa09bb; -imm32 r6, 0x89ab1d9d; -imm32 r7, 0xabcd2ff9; -R0 = R7 +|+ R0; -R1 = R7 +|+ R1; -R2 = R7 +|+ R2; -R3 = R7 +|+ R3; -R4 = R7 +|+ R4; -R5 = R7 +|+ R5; -R6 = R7 +|+ R6; -R7 = R7 +|+ R7; -CHECKREG r0, 0x4334B9A4; -CHECKREG r1, 0x1546DBC6; -CHECKREG r2, 0xCF62974E; -CHECKREG r3, 0x0246C000; -CHECKREG r4, 0x2467C792; -CHECKREG r5, 0x567739B4; -CHECKREG r6, 0x35784D96; -CHECKREG r7, 0x579A5FF2; - -imm32 r0, 0x856739ab; -imm32 r1, 0x87694bcd; -imm32 r2, 0x08856755; -imm32 r3, 0x66686777; -imm32 r4, 0x12385699; -imm32 r5, 0x4567886b; -imm32 r6, 0x04329086; -imm32 r7, 0x12345678; -R4 = R4 +|+ R7 (S); -R5 = R5 +|+ R5 (CO); -R2 = R6 +|+ R3 (SCO); -R6 = R0 +|+ R4 (S); -R0 = R1 +|+ R6 (S); -R2 = R2 +|+ R1 (CO); -R1 = R3 +|+ R0 (CO); -R7 = R7 +|+ R4 (SCO); -CHECKREG r0, 0x80007FFF; -CHECKREG r1, 0xE776E668; -CHECKREG r2, 0xB6677F66; -CHECKREG r3, 0x66686777; -CHECKREG r4, 0x246C7FFF; -CHECKREG r5, 0x10D68ACE; -CHECKREG r6, 0xA9D37FFF; -CHECKREG r7, 0x7FFF36A0; - -imm32 r0, 0x476789ab; -imm32 r1, 0x6779abcd; -imm32 r2, 0x23456755; -imm32 r3, 0x56789007; -imm32 r4, 0x789ab799; -imm32 r5, 0xaaaa0bbb; -imm32 r6, 0x89ab1d7d; -imm32 r7, 0xabcd2ff7; -R3 = R4 +|+ R0 (S); -R5 = R5 +|+ R1 (SCO); -R2 = R2 +|+ R2 (S); -R7 = R7 +|+ R3 (CO); -R4 = R3 +|+ R4 (CO); -R0 = R1 +|+ R5 (S); -R1 = R0 +|+ R6 (SCO); -R6 = R6 +|+ R7 (SCO); -CHECKREG r0, 0x1F01BDF0; -CHECKREG r1, 0xDB6DA8AC; -CHECKREG r2, 0x468A7FFF; -CHECKREG r3, 0x7FFF8000; -CHECKREG r4, 0x3799F899; -CHECKREG r5, 0xB7881223; -CHECKREG r6, 0x49498000; -CHECKREG r7, 0xAFF72BCC; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rr_lph_a1a0.s b/sim/testsuite/sim/bfin/c_dsp32alu_rr_lph_a1a0.s deleted file mode 100644 index 5ce3598..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rr_lph_a1a0.s +++ /dev/null @@ -1,33 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rr_lph_a1a0/c_dsp32alu_rr_lph_a1a0.dsp -// Spec Reference: dsp32alu (dregs, dregs) = L + H, L + H (a1, a0) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x25678911; -imm32 r1, 0x0029ab2d; -imm32 r2, 0x00145535; -imm32 r3, 0xf6567747; -imm32 r4, 0xe566895b; -imm32 r5, 0x67897b6d; -imm32 r6, 0xb4445875; -imm32 r7, 0x86667797; -A1 = R1; -A0 = R0; - -R2 = A1.L + A1.H, R3 = A0.L + A0.H; -R4 = A1.L + A1.H, R5 = A0.L + A0.H; -R6 = A1.L + A1.H, R7 = A0.L + A0.H; -CHECKREG r2, 0xFFFFAB56; -CHECKREG r3, 0xFFFFAE78; -CHECKREG r4, 0xFFFFAB56; -CHECKREG r5, 0xFFFFAE78; -CHECKREG r6, 0xFFFFAB56; -CHECKREG r7, 0xFFFFAE78; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrpm.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrpm.s deleted file mode 100644 index 2ced758..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rrpm.s +++ /dev/null @@ -1,265 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rrpm/c_dsp32alu_rrpm.dsp -// Spec Reference: dsp32alu (dreg, dreg) -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x75678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34745515; -imm32 r3, 0x46677717; -imm32 r0, 0x5567a91b; -imm32 r1, 0x6789aa1d; -imm32 r2, 0x744455a5; -imm32 r3, 0x8666777a; -R0 = R0 + R0, R7 = R0 - R0 (NS); -R1 = R0 + R1, R6 = R0 - R1 (NS); -R2 = R0 + R2, R5 = R0 - R2 (NS); -R3 = R0 + R3, R4 = R0 - R3 (NS); -R4 = R0 + R4, R3 = R0 - R4 (NS); -R5 = R0 + R5, R2 = R0 - R5 (NS); -R6 = R0 + R6, R1 = R0 - R6 (NS); -R7 = R0 + R7, R0 = R0 - R7 (NS); -CHECKREG r0, 0xAACF5236; -CHECKREG r1, 0x6789AA1D; -CHECKREG r2, 0x744455A5; -CHECKREG r3, 0x8666777A; -CHECKREG r4, 0xCF382CF2; -CHECKREG r5, 0xE15A4EC7; -CHECKREG r6, 0xEE14FA4F; -CHECKREG r7, 0xAACF5236; - -imm32 r0, 0x4567892b; -imm32 r1, 0x4489ab2d; -imm32 r2, 0x54445525; -imm32 r3, 0x66645727; -imm32 r4, 0x78889629; -imm32 r5, 0x8aaabb6b; -imm32 r6, 0x9cccdd2d; -imm32 r7, 0x0eee3fff; -R0 = R1 + R0, R7 = R1 - R0 (NS); -R1 = R1 + R1, R6 = R1 - R1 (NS); -R2 = R1 + R2, R5 = R1 - R2 (NS); -R3 = R1 + R3, R4 = R1 - R3 (NS); -R4 = R1 + R4, R3 = R1 - R4 (NS); -R5 = R1 + R5, R2 = R1 - R5 (NS); -R6 = R1 + R6, R1 = R1 - R6 (NS); -R7 = R1 + R7, R0 = R1 - R7 (NS); -CHECKREG r0, 0x89F13458; -CHECKREG r1, 0x8913565A; -CHECKREG r2, 0x54445525; -CHECKREG r3, 0x66645727; -CHECKREG r4, 0xABC2558D; -CHECKREG r5, 0xBDE2578F; -CHECKREG r6, 0x8913565A; -CHECKREG r7, 0x8835785C; - - -imm32 r0, 0x496789ab; -imm32 r1, 0x6489abcd; -imm32 r2, 0x4b445555; -imm32 r3, 0x6c647777; -imm32 r4, 0x8d889999; -imm32 r5, 0x1eaa4bbb; -imm32 r6, 0x2fccd44d; -imm32 r7, 0x31eefff4; -R0 = R2 + R0, R7 = R2 - R0 (NS); -R1 = R2 + R1, R6 = R2 - R1 (NS); -R2 = R2 + R2, R5 = R2 - R2 (NS); -R3 = R2 + R3, R4 = R2 - R3 (NS); -R4 = R2 + R4, R3 = R2 - R4 (NS); -R5 = R2 + R5, R2 = R2 - R5 (NS); -R6 = R2 + R6, R1 = R2 - R6 (NS); -R7 = R2 + R7, R0 = R2 - R7 (NS); -CHECKREG r0, 0x94ABDF00; -CHECKREG r1, 0xAFCE0122; -CHECKREG r2, 0x9688AAAA; -CHECKREG r3, 0x6C647777; -CHECKREG r4, 0xC0ACDDDD; -CHECKREG r5, 0x9688AAAA; -CHECKREG r6, 0x7D435432; -CHECKREG r7, 0x98657654; - -imm32 r0, 0xa537891b; -imm32 r1, 0x6a59ab2d; -imm32 r2, 0x44a55535; -imm32 r3, 0x166a5747; -imm32 r4, 0x6878a565; -imm32 r5, 0x7a8aba5b; -imm32 r6, 0x8c9cdd85; -imm32 r7, 0x9eaeffaf; -R0 = R3 + R0, R7 = R3 - R0 (NS); -R1 = R3 + R1, R6 = R3 - R1 (NS); -R2 = R3 + R2, R5 = R3 - R2 (NS); -R3 = R3 + R3, R4 = R3 - R3 (NS); -R4 = R3 + R4, R3 = R3 - R4 (NS); -R5 = R3 + R5, R2 = R3 - R5 (NS); -R6 = R3 + R6, R1 = R3 - R6 (NS); -R7 = R3 + R7, R0 = R3 - R7 (NS); -CHECKREG r0, 0xBBA1E062; -CHECKREG r1, 0x80C40274; -CHECKREG r2, 0x5B0FAC7C; -CHECKREG r3, 0x2CD4AE8E; -CHECKREG r4, 0x2CD4AE8E; -CHECKREG r5, 0xFE99B0A0; -CHECKREG r6, 0xD8E55AA8; -CHECKREG r7, 0x9E077CBA; - -imm32 r0, 0x15678911; -imm32 r1, 0x9789ab1d; -imm32 r2, 0x94445515; -imm32 r3, 0x96667717; -imm32 r0, 0x5267891b; -imm32 r1, 0x67a9ab1d; -imm32 r2, 0x744c5515; -imm32 r3, 0x8666d777; -R0 = R4 + R0, R7 = R4 - R0 (NS); -R1 = R4 + R1, R6 = R4 - R1 (NS); -R2 = R4 + R2, R5 = R4 - R2 (NS); -R3 = R4 + R3, R4 = R4 - R3 (NS); -R4 = R4 + R4, R3 = R4 - R4 (NS); -R5 = R4 + R5, R2 = R4 - R5 (NS); -R6 = R4 + R6, R1 = R4 - R6 (NS); -R7 = R4 + R7, R0 = R4 - R7 (NS); -CHECKREG r0, 0x726E88BB; -CHECKREG r1, 0x87B0AABD; -CHECKREG r2, 0x945354B5; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x4CDBAE2E; -CHECKREG r5, 0x056407A7; -CHECKREG r6, 0x1206B19F; -CHECKREG r7, 0x2748D3A1; - -imm32 r0, 0xa567892b; -imm32 r1, 0x4a89ab2d; -imm32 r2, 0x54a45525; -imm32 r3, 0x666d7727; -imm32 r4, 0x7888d929; -imm32 r5, 0x8aaabe2b; -imm32 r6, 0x9cccdd2d; -imm32 r7, 0x0eeeffef; -R0 = R5 + R0, R7 = R5 - R0 (NS); -R1 = R5 + R1, R6 = R5 - R1 (NS); -R2 = R5 + R2, R5 = R5 - R2 (NS); -R3 = R5 + R3, R4 = R5 - R3 (NS); -R4 = R5 + R4, R3 = R5 - R4 (NS); -R5 = R5 + R5, R2 = R5 - R5 (NS); -R6 = R5 + R6, R1 = R5 - R6 (NS); -R7 = R5 + R7, R0 = R5 - R7 (NS); -CHECKREG r0, 0x86C99D0C; -CHECKREG r1, 0x2BEBBF0E; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x666D7727; -CHECKREG r4, 0x059F5AE5; -CHECKREG r5, 0x6C0CD20C; -CHECKREG r6, 0xAC2DE50A; -CHECKREG r7, 0x5150070C; - - -imm32 r0, 0x496789ab; -imm32 r1, 0x6489abcd; -imm32 r2, 0x4b445555; -imm32 r3, 0x6c647777; -imm32 r4, 0x8d889999; -imm32 r5, 0x1eaa4bbb; -imm32 r6, 0x2fccd44d; -imm32 r7, 0x31eefff4; -R0 = R6 + R0, R7 = R6 - R0 (NS); -R1 = R6 + R1, R6 = R6 - R1 (NS); -R2 = R6 + R2, R5 = R6 - R2 (NS); -R3 = R6 + R3, R4 = R6 - R3 (NS); -R4 = R6 + R4, R3 = R6 - R4 (NS); -R5 = R6 + R5, R2 = R6 - R5 (NS); -R6 = R6 + R6, R1 = R6 - R6 (NS); -R7 = R6 + R7, R0 = R6 - R7 (NS); -CHECKREG r0, 0xB021065E; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x4B445555; -CHECKREG r3, 0x6C647777; -CHECKREG r4, 0x2A21D989; -CHECKREG r5, 0x4B41FBAB; -CHECKREG r6, 0x96865100; -CHECKREG r7, 0x7CEB9BA2; - -imm32 r0, 0xe537891b; -imm32 r1, 0xe759ab2d; -imm32 r2, 0x4e555535; -imm32 r3, 0x16e65747; -imm32 r4, 0x687e9565; -imm32 r5, 0x7a8aeb5b; -imm32 r6, 0x8c9cdd85; -imm32 r7, 0x9eaefe9f; -R0 = R7 + R0, R7 = R7 - R0 (NS); -R1 = R7 + R1, R6 = R7 - R1 (NS); -R2 = R7 + R2, R5 = R7 - R2 (NS); -R3 = R7 + R3, R4 = R7 - R3 (NS); -R4 = R7 + R4, R3 = R7 - R4 (NS); -R5 = R7 + R5, R2 = R7 - R5 (NS); -R6 = R7 + R6, R1 = R7 - R6 (NS); -R7 = R7 + R7, R0 = R7 - R7 (NS); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0xE759AB2D; -CHECKREG r2, 0x4E555535; -CHECKREG r3, 0x16E65747; -CHECKREG r4, 0x5C0893C1; -CHECKREG r5, 0x249995D3; -CHECKREG r6, 0x8B953FDB; -CHECKREG r7, 0x72EEEB08; - -imm32 r0, 0x496789ab; -imm32 r1, 0x6489abcd; -imm32 r2, 0x4b445555; -imm32 r3, 0x6c647777; -imm32 r4, 0x8d889999; -imm32 r5, 0x1eaa4bbb; -imm32 r6, 0x2fccd44d; -imm32 r7, 0x31eefff4; -R2 = R4 + R0, R7 = R4 - R0 (S); -R3 = R7 + R1, R6 = R7 - R1 (NS); -R4 = R0 + R2, R5 = R0 - R2 (S); -R5 = R4 + R3, R4 = R4 - R3 (NS); -R6 = R2 + R4, R3 = R2 - R4 (S); -R7 = R3 + R5, R2 = R3 - R5 (NS); -R0 = R1 + R6, R1 = R1 - R6 (S); -R1 = R5 + R7, R0 = R5 - R7 (S); -CHECKREG r0, 0x64DDDDDE; -CHECKREG r1, 0xA4E4D39A; -CHECKREG r2, 0x9640C966; -CHECKREG r3, 0x9B222222; -CHECKREG r4, 0x3BCE0122; -CHECKREG r5, 0x04E158BC; -CHECKREG r6, 0x12BE2466; -CHECKREG r7, 0xA0037ADE; - -imm32 r0, 0xa537891b; -imm32 r1, 0x6d59ab2d; -imm32 r2, 0x4f555535; -imm32 r3, 0x16c65747; -imm32 r4, 0x687c9565; -imm32 r5, 0x7a8acb5b; -imm32 r6, 0x8c9cdc85; -imm32 r7, 0x9eaefb9f; -R4 = R3 + R0, R1 = R3 - R0 (S); -R5 = R6 + R1, R2 = R6 - R1 (S); -R6 = R7 + R2, R3 = R7 - R2 (S); -R7 = R0 + R3, R4 = R0 - R3 (NS); -R0 = R2 + R4, R5 = R2 - R4 (S); -R1 = R1 + R5, R6 = R1 - R5 (S); -R2 = R5 + R6, R7 = R5 - R6 (NS); -R3 = R4 + R7, R0 = R4 - R7 (S); -CHECKREG r0, 0x052876A0; -CHECKREG r1, 0x6B0640B0; -CHECKREG r2, 0x718ECE2C; -CHECKREG r3, 0x80000000; -CHECKREG r4, 0x86888D7C; -CHECKREG r5, 0xF9777284; -CHECKREG r6, 0x78175BA8; -CHECKREG r7, 0x816016DC; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrpm_aa.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrpm_aa.s deleted file mode 100644 index 7c1e3a3..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rrpm_aa.s +++ /dev/null @@ -1,70 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rrpm_aa/c_dsp32alu_rrpm_aa.dsp -// Spec Reference: dsp32alu (dregs, dregs) = +/- (a, a) amod1 -# mach: bfin - -.include "testutils.inc" - start - - - -A1 = A0 = 0; - -imm32 r0, 0x75678911; -imm32 r1, 0xa789ab2d; -imm32 r2, 0x34745515; -imm32 r3, 0x46677757; -imm32 r4, 0xb567a96b; -imm32 r5, 0x6789aa1d; -imm32 r6, 0x744455a5; -imm32 r7, 0x8666777a; -A0 = R0; -A1 = R1; - -R0 = A1 + A0, R7 = A1 - A0 (NS); -R1 = A0 + A1, R6 = A0 - A1 (NS); -R2 = A1 + A0, R5 = A1 - A0 (NS); -R3 = A0 + A1, R4 = A0 - A1 (NS); -R4 = A1 + A0, R0 = A1 - A0 (NS); -R5 = A0 + A1, R1 = A0 - A1 (NS); -R6 = A0 + A1, R2 = A0 - A1 (NS); -R7 = A1 + A0, R3 = A1 - A0 (NS); -CHECKREG r0, 0x3222221C; -CHECKREG r1, 0xCDDDDDE4; -CHECKREG r2, 0xCDDDDDE4; -CHECKREG r3, 0x3222221C; -CHECKREG r4, 0x1CF1343E; -CHECKREG r5, 0x1CF1343E; -CHECKREG r6, 0x1CF1343E; -CHECKREG r7, 0x1CF1343E; - -imm32 r0, 0x8537891b; -imm32 r1, 0x3759ab2d; -imm32 r2, 0x4e555535; -imm32 r3, 0x16e65747; -imm32 r4, 0x687e9565; -imm32 r5, 0x7a8aeb5b; -imm32 r6, 0x8c9cdd85; -imm32 r7, 0x9eaefe9f; -A0 = R0; -A1 = R1; -R3 = A1 + A0, R7 = A1 - A0 (S); -R4 = A0 + A1, R6 = A0 - A1 (S); -R5 = A1 + A0, R4 = A1 - A0 (S); -R6 = A0 + A1, R5 = A0 - A1 (S); -R7 = A1 + A0, R3 = A1 - A0 (S); -R0 = A0 + A1, R2 = A0 - A1 (S); -R1 = A0 + A1, R0 = A0 - A1 (S); -R2 = A1 + A0, R1 = A1 - A0 (S); -CHECKREG r0, 0x80000000; -CHECKREG r1, 0x7FFFFFFF; -CHECKREG r2, 0xBC913448; -CHECKREG r3, 0x7FFFFFFF; -CHECKREG r4, 0x7FFFFFFF; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0xBC913448; -CHECKREG r7, 0xBC913448; - - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp.s deleted file mode 100644 index 6951a9f..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp.s +++ /dev/null @@ -1,263 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rrpmmp/c_dsp32alu_rrpmmp.dsp -// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) amod0 -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x35678911; -imm32 r1, 0x2489ab1d; -imm32 r2, 0x34545515; -imm32 r3, 0x46667717; -imm32 r0, 0x5567891b; -imm32 r1, 0x67889b1d; -imm32 r2, 0x74445915; -imm32 r3, 0x86667797; -R0 = R0 +|- R0 , R7 = R0 -|+ R0; -R1 = R0 +|- R1 , R6 = R0 -|+ R1; -R2 = R0 +|- R2 , R5 = R0 -|+ R2; -R3 = R0 +|- R3 , R4 = R0 -|+ R3; -R4 = R0 +|- R4 , R3 = R0 -|+ R4; -R5 = R0 +|- R5 , R2 = R0 -|+ R5; -R6 = R0 +|- R6 , R1 = R0 -|+ R6; -R7 = R0 +|- R7 , R0 = R0 -|+ R7; -CHECKREG r0, 0xAACE1236; -CHECKREG r1, 0x67889B1D; -CHECKREG r2, 0x74445915; -CHECKREG r3, 0x86667797; -CHECKREG r4, 0xCF368869; -CHECKREG r5, 0xE158A6EB; -CHECKREG r6, 0xEE1464E3; -CHECKREG r7, 0xAACEEDCA; - -imm32 r0, 0xe5678911; -imm32 r1, 0x2e89ab1d; -imm32 r2, 0x34e45515; -imm32 r3, 0x466e7717; -imm32 r0, 0x5567ee1b; -imm32 r1, 0x6789abed; -imm32 r2, 0x7444551e; -imm32 r3, 0x86e67777; -R0 = R1 +|- R0 , R7 = R1 -|+ R0; -R1 = R1 +|- R1 , R6 = R1 -|+ R1; -R2 = R1 +|- R2 , R5 = R1 -|+ R2; -R3 = R1 +|- R3 , R4 = R1 -|+ R3; -R4 = R1 +|- R4 , R3 = R1 -|+ R4; -R5 = R1 +|- R5 , R2 = R1 -|+ R5; -R6 = R1 +|- R6 , R1 = R1 -|+ R6; -R7 = R1 +|- R7 , R0 = R1 -|+ R7; -CHECKREG r0, 0xBCF0F1E2; -CHECKREG r1, 0xCF1257DA; -CHECKREG r2, 0x7444551E; -CHECKREG r3, 0x86E67777; -CHECKREG r4, 0x173E8889; -CHECKREG r5, 0x29E0AAE2; -CHECKREG r6, 0xCF12A826; -CHECKREG r7, 0xE134BDD2; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r0, 0x5567891b; -imm32 r1, 0x6789ab1d; -imm32 r2, 0x74445515; -imm32 r3, 0x86667777; -R0 = R2 +|- R0 , R7 = R2 -|+ R0; -R1 = R2 +|- R1 , R6 = R2 -|+ R1; -R2 = R2 +|- R2 , R5 = R2 -|+ R2; -R3 = R2 +|- R3 , R4 = R2 -|+ R3; -R4 = R2 +|- R4 , R3 = R2 -|+ R4; -R5 = R2 +|- R5 , R2 = R2 -|+ R5; -R6 = R2 +|- R6 , R1 = R2 -|+ R6; -R7 = R2 +|- R7 , R0 = R2 -|+ R7; -CHECKREG r0, 0xC9AB885A; -CHECKREG r1, 0xDBCDAA5C; -CHECKREG r2, 0xE888AA2A; -CHECKREG r3, 0x86667777; -CHECKREG r4, 0x4AAA8889; -CHECKREG r5, 0xE88855D6; -CHECKREG r6, 0xF543A9F8; -CHECKREG r7, 0x0765CBFA; - -imm32 r0, 0x85678911; -imm32 r1, 0x2889ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r0, 0x5587891b; -imm32 r1, 0x6788ab1d; -imm32 r2, 0x74448515; -imm32 r3, 0x86667877; -R0 = R3 +|- R0 , R7 = R3 -|+ R0; -R1 = R3 +|- R1 , R6 = R3 -|+ R1; -R2 = R3 +|- R2 , R5 = R3 -|+ R2; -R3 = R3 +|- R3 , R4 = R3 -|+ R3; -R4 = R3 +|- R4 , R3 = R3 -|+ R4; -R5 = R3 +|- R5 , R2 = R3 -|+ R5; -R6 = R3 +|- R6 , R1 = R3 -|+ R6; -R7 = R3 +|- R7 , R0 = R3 -|+ R7; -CHECKREG r0, 0xDBEDF280; -CHECKREG r1, 0xEDEE1482; -CHECKREG r2, 0xFAAAEE7A; -CHECKREG r3, 0x0CCCF0EE; -CHECKREG r4, 0x0CCC0F12; -CHECKREG r5, 0x1EEEF362; -CHECKREG r6, 0x2BAACD5A; -CHECKREG r7, 0x3DABEF5C; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r0, 0x5567891b; -imm32 r1, 0x6789ab1d; -imm32 r2, 0x74445515; -imm32 r3, 0x86667777; -R0 = R4 +|- R0 , R7 = R4 -|+ R0; -R1 = R4 +|- R1 , R6 = R4 -|+ R1; -R2 = R4 +|- R2 , R5 = R4 -|+ R2; -R3 = R4 +|- R3 , R4 = R4 -|+ R3; -R4 = R4 +|- R4 , R3 = R4 -|+ R4; -R5 = R4 +|- R5 , R2 = R4 -|+ R5; -R6 = R4 +|- R6 , R1 = R4 -|+ R6; -R7 = R4 +|- R7 , R0 = R4 -|+ R7; -CHECKREG r0, 0x5567982D; -CHECKREG r1, 0x6789BA2F; -CHECKREG r2, 0x74446427; -CHECKREG r3, 0x00000D12; -CHECKREG r4, 0x0CCC0000; -CHECKREG r5, 0xA5549BD9; -CHECKREG r6, 0xB20F45D1; -CHECKREG r7, 0xC43167D3; - -imm32 r0, 0x95678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x39445515; -imm32 r3, 0x46967717; -imm32 r0, 0x5567891b; -imm32 r1, 0x6789ab1d; -imm32 r2, 0x74495515; -imm32 r3, 0x86669777; -R0 = R5 +|- R0 , R7 = R5 -|+ R0; -R1 = R5 +|- R1 , R6 = R5 -|+ R1; -R2 = R5 +|- R2 , R5 = R5 -|+ R2; -R3 = R5 +|- R3 , R4 = R5 -|+ R3; -R4 = R5 +|- R4 , R3 = R5 -|+ R4; -R5 = R5 +|- R5 , R2 = R5 -|+ R5; -R6 = R5 +|- R6 , R1 = R5 -|+ R6; -R7 = R5 +|- R7 , R0 = R5 -|+ R7; -CHECKREG r0, 0x122924F4; -CHECKREG r1, 0x244B46F6; -CHECKREG r2, 0x0000E1DC; -CHECKREG r3, 0x86667953; -CHECKREG r4, 0xDBB06889; -CHECKREG r5, 0x62160000; -CHECKREG r6, 0x9FE1B90A; -CHECKREG r7, 0xB203DB0C; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r0, 0x5567891b; -imm32 r1, 0x6789ab1d; -imm32 r2, 0x74445515; -imm32 r3, 0x86667777; -R0 = R6 +|- R0 , R7 = R6 -|+ R0; -R1 = R6 +|- R1 , R6 = R6 -|+ R1; -R2 = R6 +|- R2 , R5 = R6 -|+ R2; -R3 = R6 +|- R3 , R4 = R6 -|+ R3; -R4 = R6 +|- R4 , R3 = R6 -|+ R4; -R5 = R6 +|- R5 , R2 = R6 -|+ R5; -R6 = R6 +|- R6 , R1 = R6 -|+ R6; -R7 = R6 +|- R7 , R0 = R6 -|+ R7; -CHECKREG r0, 0x26364225; -CHECKREG r1, 0x0000C84E; -CHECKREG r2, 0x74441D63; -CHECKREG r3, 0x86663FC5; -CHECKREG r4, 0xEA4A8889; -CHECKREG r5, 0xFC6CAAEB; -CHECKREG r6, 0x70B00000; -CHECKREG r7, 0xBB2ABDDB; - -imm32 r0, 0x67898911; -imm32 r1, 0xb789ab1d; -imm32 r2, 0x3b445515; -imm32 r3, 0x46b67717; -imm32 r0, 0x5567891b; -imm32 r1, 0x678bab1d; -imm32 r2, 0x7444b515; -imm32 r3, 0x86667b77; -R0 = R7 +|- R0 , R7 = R7 -|+ R0; -R1 = R7 +|- R1 , R6 = R7 -|+ R1; -R2 = R7 +|- R2 , R5 = R7 -|+ R2; -R3 = R7 +|- R3 , R4 = R7 -|+ R3; -R4 = R7 +|- R4 , R3 = R7 -|+ R4; -R5 = R7 +|- R5 , R2 = R7 -|+ R5; -R6 = R7 +|- R6 , R1 = R7 -|+ R6; -R7 = R7 +|- R7 , R0 = R7 -|+ R7; -CHECKREG r0, 0x00008DEC; -CHECKREG r1, 0x678B3909; -CHECKREG r2, 0x74444301; -CHECKREG r3, 0x86660963; -CHECKREG r4, 0x45208489; -CHECKREG r5, 0x57424AEB; -CHECKREG r6, 0x63FB54E3; -CHECKREG r7, 0xCB860000; - -imm32 r0, 0xe5678911; -imm32 r1, 0x2e89ab1d; -imm32 r2, 0x34ee5515; -imm32 r3, 0x4666e717; -imm32 r0, 0x5567891b; -imm32 r1, 0x6789ae1d; -imm32 r2, 0x744455e5; -imm32 r3, 0x8666777e; -R4 = R2 +|- R5 , R3 = R2 -|+ R5 (S); -R0 = R5 +|- R3 , R5 = R5 -|+ R3 (CO); -R2 = R6 +|- R2 , R0 = R6 -|+ R2 (SCO); -R3 = R4 +|- R0 , R2 = R4 -|+ R0 (S); -R7 = R7 +|- R6 , R6 = R7 -|+ R6 (CO); -R6 = R1 +|- R7 , R1 = R1 -|+ R7 (SCO); -R5 = R0 +|- R4 , R7 = R0 -|+ R4 (S); -R1 = R3 +|- R1 , R4 = R3 -|+ R1 (CO); -CHECKREG r0, 0x7FFFEFB7; -CHECKREG r1, 0xFFFFE33B; -CHECKREG r2, 0x0000FAB1; -CHECKREG r3, 0x7FFF1B43; -CHECKREG r4, 0x534BFFFF; -CHECKREG r5, 0x7FFFE4BD; -CHECKREG r6, 0x7FFF0300; -CHECKREG r7, 0x0000FAB1; - -imm32 r0, 0xff678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x3f445515; -imm32 r3, 0x46f67717; -imm32 r0, 0x556f891b; -imm32 r1, 0x6789fb1d; -imm32 r2, 0x74445f15; -imm32 r3, 0x866677f7; -R4 = R3 +|- R3 , R5 = R3 -|+ R3 (SCO); -R1 = R6 +|- R1 , R6 = R6 -|+ R1 (SCO); -R6 = R1 +|- R4 , R4 = R1 -|+ R4 (S); -R7 = R4 +|- R2 , R0 = R4 -|+ R2 (S); -R2 = R2 +|- R6 , R1 = R2 -|+ R6 (CO); -R3 = R5 +|- R5 , R7 = R5 -|+ R5 (CO); -R5 = R7 +|- R7 , R3 = R7 -|+ R7 (SCO); -R0 = R0 +|- R0 , R2 = R0 -|+ R0 (SCO); -CHECKREG r0, 0x17760000; -CHECKREG r1, 0x66F87445; -CHECKREG r2, 0x7FFF0000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x7FFF07E3; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0xFFFF07E3; -CHECKREG r7, 0x00000000; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft.s deleted file mode 100644 index bd48482..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft.s +++ /dev/null @@ -1,262 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft/c_dsp32alu_rrpmmp_sft.dsp -// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, << -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - - imm32 r0, 0x35678911; - imm32 r1, 0x2489ab1d; - imm32 r2, 0x34545515; - imm32 r3, 0x46667717; - imm32 r0, 0x5567891b; - imm32 r1, 0x67889b1d; - imm32 r2, 0x74445915; - imm32 r3, 0x86667797; - R0 = R0 +|- R0 , R7 = R0 -|+ R0 (ASR); - R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); - R2 = R0 +|- R2 , R5 = R0 -|+ R2 (ASR); - R3 = R0 +|- R3 , R4 = R0 -|+ R3 (ASR); - R4 = R0 +|- R4 , R3 = R0 -|+ R4 (ASR); - R5 = R0 +|- R5 , R2 = R0 -|+ R5 (ASR); - R6 = R0 +|- R6 , R1 = R0 -|+ R6 (ASR); - R7 = R0 +|- R7 , R0 = R0 -|+ R7 (ASR); - CHECKREG r0, 0x2AB3c48D; - CHECKREG r1, 0x2F3CE6C7; - CHECKREG r2, 0x326B1645; - CHECKREG r3, 0xf6F31DE5; - CHECKREG r4, 0x5E73E21A; - CHECKREG r5, 0x22FCE9BB; - CHECKREG r6, 0x262B1939; - CHECKREG r7, 0x2AB33B72; - - imm32 r0, 0xe5678911; - imm32 r1, 0x2e89ab1d; - imm32 r2, 0x34e45515; - imm32 r3, 0x466e7717; - imm32 r0, 0x5567ee1b; - imm32 r1, 0x6789abed; - imm32 r2, 0x7444551e; - imm32 r3, 0x86e67777; - R0 = R1 +|- R0 , R7 = R1 -|+ R0 (ASR); - R1 = R1 +|- R1 , R6 = R1 -|+ R1 (ASR); - R2 = R1 +|- R2 , R5 = R1 -|+ R2 (ASR); - R3 = R1 +|- R3 , R4 = R1 -|+ R3 (ASR); - R4 = R1 +|- R4 , R3 = R1 -|+ R4 (ASR); - R5 = R1 +|- R5 , R2 = R1 -|+ R5 (ASR); - R6 = R1 +|- R6 , R1 = R1 -|+ R6 (ASR); - R7 = R1 +|- R7 , R0 = R1 -|+ R7 (ASR); - CHECKREG r0, 0x1559d17D; - CHECKREG r1, 0x33C4d5F6; - CHECKREG r2, 0x36F31547; - CHECKREG r3, 0xfB9C1DDD; - CHECKREG r4, 0x6BEDE222; - CHECKREG r5, 0x3095eAB8; - CHECKREG r6, 0x33C42A09; - CHECKREG r7, 0x1E6A0479; - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r0, 0x5567891b; - imm32 r1, 0x6789ab1d; - imm32 r2, 0x74445515; - imm32 r3, 0x86667777; - R0 = R2 +|- R0 , R7 = R2 -|+ R0 (ASR); - R1 = R2 +|- R1 , R6 = R2 -|+ R1 (ASR); - R2 = R2 +|- R2 , R5 = R2 -|+ R2 (ASR); - R3 = R2 +|- R3 , R4 = R2 -|+ R3 (ASR); - R4 = R2 +|- R4 , R3 = R2 -|+ R4 (ASR); - R5 = R2 +|- R5 , R2 = R2 -|+ R5 (ASR); - R6 = R2 +|- R6 , R1 = R2 -|+ R6 (ASR); - R7 = R2 +|- R7 , R0 = R2 -|+ R7 (ASR); - CHECKREG r0, 0x155A0CD1; - CHECKREG r1, 0x19E21551; - CHECKREG r2, 0x3A222A8A; - CHECKREG r3, 0xfEAA1DDD; - CHECKREG r4, 0x7599e222; - CHECKREG r5, 0x3A22d575; - CHECKREG r6, 0x203F1538; - CHECKREG r7, 0x24C81DB9; - - imm32 r0, 0x85678911; - imm32 r1, 0x2889ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r0, 0x5587891b; - imm32 r1, 0x6788ab1d; - imm32 r2, 0x74448515; - imm32 r3, 0x86667877; - R0 = R3 +|- R0 , R7 = R3 -|+ R0 (ASR); - R1 = R3 +|- R1 , R6 = R3 -|+ R1 (ASR); - R2 = R3 +|- R2 , R5 = R3 -|+ R2 (ASR); - R3 = R3 +|- R3 , R4 = R3 -|+ R3 (ASR); - R4 = R3 +|- R4 , R3 = R3 -|+ R4 (ASR); - R5 = R3 +|- R5 , R2 = R3 -|+ R5 (ASR); - R6 = R3 +|- R6 , R1 = R3 -|+ R6 (ASR); - R7 = R3 +|- R7 , R0 = R3 -|+ R7 (ASR); - CHECKREG r0, 0x15621E82; - CHECKREG r1, 0x19E22702; - CHECKREG r2, 0x1D111D80; - CHECKREG r3, 0xc3333C3B; - CHECKREG r4, 0xc333c3C4; - CHECKREG r5, 0xa6221EBA; - CHECKREG r6, 0xa9511538; - CHECKREG r7, 0xaDD11DB9; - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r0, 0x5567891b; - imm32 r1, 0x6789ab1d; - imm32 r2, 0x74445515; - imm32 r3, 0x86667777; - R0 = R4 +|- R0 , R7 = R4 -|+ R0 (ASR); - R1 = R4 +|- R1 , R6 = R4 -|+ R1 (ASR); - R2 = R4 +|- R2 , R5 = R4 -|+ R2 (ASR); - R3 = R4 +|- R3 , R4 = R4 -|+ R3 (ASR); - R4 = R4 +|- R4 , R3 = R4 -|+ R4 (ASR); - R5 = R4 +|- R5 , R2 = R4 -|+ R5 (ASR); - R6 = R4 +|- R6 , R1 = R4 -|+ R6 (ASR); - R7 = R4 +|- R7 , R0 = R4 -|+ R7 (ASR); - CHECKREG r0, 0x33C0d337; - CHECKREG r1, 0x3848dBB8; - CHECKREG r2, 0x3B770636; - CHECKREG r3, 0x00001D9D; - CHECKREG r4, 0x1E660000; - CHECKREG r5, 0xe2EEf9CA; - CHECKREG r6, 0xe61D2448; - CHECKREG r7, 0xeAA62CC8; - - imm32 r0, 0x95678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x39445515; - imm32 r3, 0x46967717; - imm32 r0, 0x5567891b; - imm32 r1, 0x6789ab1d; - imm32 r2, 0x74495515; - imm32 r3, 0x86669777; - R0 = R5 +|- R0 , R7 = R5 -|+ R0 (ASR); - R1 = R5 +|- R1 , R6 = R5 -|+ R1 (ASL); - R2 = R5 +|- R2 , R5 = R5 -|+ R2 (ASR); - R3 = R5 +|- R3 , R4 = R5 -|+ R3 (ASL); - R4 = R5 +|- R4 , R3 = R5 -|+ R4 (ASR); - R5 = R5 +|- R5 , R2 = R5 -|+ R5 (ASR); - R6 = R5 +|- R6 , R1 = R5 -|+ R6 (ASR); - R7 = R5 +|- R7 , R0 = R5 -|+ R7 (ASL); - CHECKREG r0, 0xE11E82E4; - CHECKREG r1, 0xe04424E7; - CHECKREG r2, 0x0000276F; - CHECKREG r3, 0xaaBD529D; - CHECKREG r4, 0x0c95D4D1; - CHECKREG r5, 0xb7520000; - CHECKREG r6, 0xd70EdB19; - CHECKREG r7, 0xfC2A7D1C; - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r0, 0x5567891b; - imm32 r1, 0x6789ab1d; - imm32 r2, 0x74445515; - imm32 r3, 0x86667777; - R0 = R6 +|- R0 , R7 = R6 -|+ R0 (ASR); - R1 = R6 +|- R1 , R6 = R6 -|+ R1 (ASL); - R2 = R6 +|- R2 , R5 = R6 -|+ R2 (ASL); - R3 = R6 +|- R3 , R4 = R6 -|+ R3 (ASR); - R4 = R6 +|- R4 , R3 = R6 -|+ R4 (ASR); - R5 = R6 +|- R5 , R2 = R6 -|+ R5 (ASR); - R6 = R6 +|- R6 , R1 = R6 -|+ R6 (ASL); - R7 = R6 +|- R7 , R0 = R6 -|+ R7 (ASR); - CHECKREG r0, 0x5dAAd90D; - CHECKREG r1, 0x000031B0; - CHECKREG r2, 0x04BFe7B7; - CHECKREG r3, 0xd95C272E; - CHECKREG r4, 0x05AEe53D; - CHECKREG r5, 0xDa4B24B5; - CHECKREG r6, 0x7C280000; - CHECKREG r7, 0x1e7D26F3; - - imm32 r0, 0x67898911; - imm32 r1, 0xb789ab1d; - imm32 r2, 0x3b445515; - imm32 r3, 0x46b67717; - imm32 r0, 0x5567891b; - imm32 r1, 0x678bab1d; - imm32 r2, 0x7444b515; - imm32 r3, 0x86667b77; - R0 = R7 +|- R0 , R7 = R7 -|+ R0 (ASR); - R1 = R7 +|- R1 , R6 = R7 -|+ R1 (ASR); - R2 = R7 +|- R2 , R5 = R7 -|+ R2 (ASL); - R3 = R7 +|- R3 , R4 = R7 -|+ R3 (ASR); - R4 = R7 +|- R4 , R3 = R7 -|+ R4 (ASL); - R5 = R7 +|- R5 , R2 = R7 -|+ R5 (ASL); - R6 = R7 +|- R6 , R1 = R7 -|+ R6 (ASL); - R7 = R7 +|- R7 , R0 = R7 -|+ R7 (ASR); - CHECKREG r0, 0x0000d807; - CHECKREG r1, 0x4c163332; - CHECKREG r2, 0x07FAe47E; - CHECKREG r3, 0x6aF2038C; - CHECKREG r4, 0x273A5c90; - CHECKREG r5, 0x8a327b9E; - CHECKREG r6, 0x46162cEA; - CHECKREG r7, 0xe48B0000; - - imm32 r0, 0xe5678911; - imm32 r1, 0x2e89ab1d; - imm32 r2, 0x34ee5515; - imm32 r3, 0x4666e717; - imm32 r0, 0x5567891b; - imm32 r1, 0x6789ae1d; - imm32 r2, 0x744455e5; - imm32 r3, 0x8666777e; - R4 = R2 +|- R5 , R3 = R2 -|+ R5 (ASR); - R0 = R5 +|- R3 , R5 = R5 -|+ R3 (ASL); - R2 = R6 +|- R2 , R0 = R6 -|+ R2 (ASR); - R3 = R4 +|- R0 , R2 = R4 -|+ R0 (ASR); - R7 = R7 +|- R6 , R6 = R7 -|+ R6 (ASR); - R6 = R1 +|- R7 , R1 = R1 -|+ R7 (ASL); - R5 = R0 +|- R4 , R7 = R0 -|+ R4 (ASR); - R1 = R3 +|- R1 , R4 = R3 -|+ R1 (ASL); - CHECKREG r0, 0xE8e94167; - CHECKREG r1, 0x31084d1C; - CHECKREG r2, 0x0b291745; - CHECKREG r3, 0xF412d5de; - CHECKREG r4, 0x9f400a5C; - CHECKREG r5, 0xF4122a22; - CHECKREG r6, 0xf9B28924; - CHECKREG r7, 0xF4D71745; - - imm32 r0, 0xff678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x3f445515; - imm32 r3, 0x46f67717; - imm32 r0, 0x556f891b; - imm32 r1, 0x6789fb1d; - imm32 r2, 0x74445f15; - imm32 r3, 0x866677f7; - R4 = R3 +|- R3 , R5 = R3 -|+ R3 (ASR); - R1 = R6 +|- R1 , R6 = R6 -|+ R1 (ASL); - R6 = R1 +|- R4 , R4 = R1 -|+ R4 (ASR); - R7 = R4 +|- R2 , R0 = R4 -|+ R2 (ASL); - R2 = R2 +|- R6 , R1 = R2 -|+ R6 (ASR); - R3 = R5 +|- R5 , R7 = R5 -|+ R5 (ASL); - R5 = R7 +|- R7 , R3 = R7 -|+ R7 (ASR); - R0 = R0 +|- R0 , R2 = R0 -|+ R0 (ASR); - CHECKREG r0, 0x53880000; - CHECKREG r1, 0x67eb368e; - CHECKREG r2, 0x0000da38; - CHECKREG r3, 0x0000dfdc; - CHECKREG r4, 0x1e080e07; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0xa46e0e07; - CHECKREG r7, 0x0000dfdc; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft_x.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft_x.s deleted file mode 100644 index f8711a5..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft_x.s +++ /dev/null @@ -1,261 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft_x/c_dsp32alu_rrpmmp_sft_x.dsp -// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, << -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - imm32 r0, 0x35678911; - imm32 r1, 0x2489ab1d; - imm32 r2, 0x34545515; - imm32 r3, 0x46667717; - imm32 r0, 0x5567891b; - imm32 r1, 0x67889b1d; - imm32 r2, 0x74445915; - imm32 r3, 0x86667797; - R0 = R0 +|- R0 , R7 = R0 -|+ R0 (CO , ASR); - R1 = R0 +|- R1 , R6 = R0 -|+ R1 (CO , ASR); - R2 = R0 +|- R2 , R5 = R0 -|+ R2 (CO , ASR); - R3 = R0 +|- R3 , R4 = R0 -|+ R3 (CO , ASR); - R4 = R0 +|- R4 , R3 = R0 -|+ R4 (CO , ASR); - R5 = R0 +|- R5 , R2 = R0 -|+ R5 (CO , ASR); - R6 = R0 +|- R6 , R1 = R0 -|+ R6 (CO , ASR); - R7 = R0 +|- R7 , R0 = R0 -|+ R7 (CO , ASR); - CHECKREG r0, 0x00006626; - CHECKREG r1, 0xfb7743ec; - CHECKREG r2, 0xf848146e; - CHECKREG r3, 0x33c00cce; - CHECKREG r4, 0x4899cc40; - CHECKREG r5, 0x40f807b7; - CHECKREG r6, 0x117a0488; - CHECKREG r7, 0xef410000; - - imm32 r0, 0xe5678911; - imm32 r1, 0x2e89ab1d; - imm32 r2, 0x34e45515; - imm32 r3, 0x466e7717; - imm32 r0, 0x5567ee1b; - imm32 r1, 0x6789abed; - imm32 r2, 0x7444551e; - imm32 r3, 0x86e67777; - R0 = R1 +|- R0 , R7 = R1 -|+ R0 (CO , ASR); - R1 = R1 +|- R1 , R6 = R1 -|+ R1 (CO , ASR); - R2 = R1 +|- R2 , R5 = R1 -|+ R2 (CO , ASR); - R3 = R1 +|- R3 , R4 = R1 -|+ R3 (CO , ASR); - R4 = R1 +|- R4 , R3 = R1 -|+ R4 (CO , ASR); - R5 = R1 +|- R5 , R2 = R1 -|+ R5 (CO , ASR); - R6 = R1 +|- R6 , R1 = R1 -|+ R6 (CO , ASR); - R7 = R1 +|- R7 , R0 = R1 -|+ R7 (CO , ASR); - CHECKREG r0, 0x336f197e; - CHECKREG r1, 0x00005dce; - CHECKREG r2, 0xfcd11e7d; - CHECKREG r3, 0x382815e7; - CHECKREG r4, 0x51a2c7d7; - CHECKREG r5, 0x490c032f; - CHECKREG r6, 0x09bb0000; - CHECKREG r7, 0xe6822a5e; - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r0, 0x5567891b; - imm32 r1, 0x6789ab1d; - imm32 r2, 0x74445515; - imm32 r3, 0x86667777; - R0 = R2 +|- R0 , R7 = R2 -|+ R0 (CO , ASR); - R1 = R2 +|- R1 , R6 = R2 -|+ R1 (CO , ASR); - R2 = R2 +|- R2 , R5 = R2 -|+ R2 (CO , ASR); - R3 = R2 +|- R3 , R4 = R2 -|+ R3 (CO , ASR); - R4 = R2 +|- R4 , R3 = R2 -|+ R4 (CO , ASR); - R5 = R2 +|- R5 , R2 = R2 -|+ R5 (CO , ASR); - R6 = R2 +|- R6 , R1 = R2 -|+ R6 (CO , ASR); - R7 = R2 +|- R7 , R0 = R2 -|+ R7 (CO , ASR); - CHECKREG r0, 0x0f820874; - CHECKREG r1, 0x0afafff3; - CHECKREG r2, 0x00000f97; - CHECKREG r3, 0x3b771c44; - CHECKREG r4, 0x57ffc488; - CHECKREG r5, 0x64ac0000; - CHECKREG r6, 0x000c049d; - CHECKREG r7, 0xf78c0014; - - imm32 r0, 0x85678911; - imm32 r1, 0x2889ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r0, 0x5587891b; - imm32 r1, 0x6788ab1d; - imm32 r2, 0x74448515; - imm32 r3, 0x86667877; - R0 = R3 +|- R0 , R7 = R3 -|+ R0 (CO , ASR); - R1 = R3 +|- R1 , R6 = R3 -|+ R1 (CO , ASR); - R2 = R3 +|- R2 , R5 = R3 -|+ R2 (CO , ASR); - R3 = R3 +|- R3 , R4 = R3 -|+ R3 (CO , ASR); - R4 = R3 +|- R4 , R3 = R3 -|+ R4 (CO , ASR); - R5 = R3 +|- R5 , R2 = R3 -|+ R5 (CO , ASR); - R6 = R3 +|- R6 , R1 = R3 -|+ R6 (CO , ASR); - R7 = R3 +|- R7 , R0 = R3 -|+ R7 (CO , ASR); - CHECKREG r0, 0x8fb3ff9b; - CHECKREG r1, 0x8b33f71b; - CHECKREG r2, 0x8804009d; - CHECKREG r3, 0x000086f7; - CHECKREG r4, 0xff6e0000; - CHECKREG r5, 0xff63fef3; - CHECKREG r6, 0x08e5fbc4; - CHECKREG r7, 0x0064f744; - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r0, 0x5567891b; - imm32 r1, 0x6789ab1d; - imm32 r2, 0x74445515; - imm32 r3, 0x86667777; - R0 = R4 +|- R0 , R7 = R4 -|+ R0 (CO , ASR); - R1 = R4 +|- R1 , R6 = R4 -|+ R1 (CO , ASR); - R2 = R4 +|- R2 , R5 = R4 -|+ R2 (CO , ASR); - R3 = R4 +|- R3 , R4 = R4 -|+ R3 (CO , ASR); - R4 = R4 +|- R4 , R3 = R4 -|+ R4 (CO , ASR); - R5 = R4 +|- R5 , R2 = R4 -|+ R5 (CO , ASR); - R6 = R4 +|- R6 , R1 = R4 -|+ R6 (CO , ASR); - R7 = R4 +|- R7 , R0 = R4 -|+ R7 (CO , ASR); - CHECKREG r0, 0xEA813B97; - CHECKREG r1, 0xE5F93316; - CHECKREG r2, 0xe2ca0898; - CHECKREG r3, 0x3C840000; - CHECKREG r4, 0x3BBB0000; - CHECKREG r5, 0x33221D35; - CHECKREG r6, 0x08A41A07; - CHECKREG r7, 0x0024157E; - - imm32 r0, 0x95678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x39445515; - imm32 r3, 0x46967717; - imm32 r0, 0x5567891b; - imm32 r1, 0x6789ab1d; - imm32 r2, 0x74495515; - imm32 r3, 0x86669777; - R0 = R5 +|- R0 , R7 = R5 -|+ R0 (CO , ASR); - R1 = R5 +|- R1 , R6 = R5 -|+ R1 (CO , ASL); - R2 = R5 +|- R2 , R5 = R5 -|+ R2 (CO , ASR); - R3 = R5 +|- R3 , R4 = R5 -|+ R3 (CO , ASL); - R4 = R5 +|- R4 , R3 = R5 -|+ R4 (CO , ASR); - R5 = R5 +|- R5 , R2 = R5 -|+ R5 (CO , ASR); - R6 = R5 +|- R6 , R1 = R5 -|+ R6 (CO , ASR); - R7 = R5 +|- R7 , R0 = R5 -|+ R7 (CO , ASL); - CHECKREG r0, 0xDDBACBFA; - CHECKREG r1, 0xCB995440; - CHECKREG r2, 0xDF6C0000; - CHECKREG r3, 0x227525AF; - CHECKREG r4, 0x1375bCF7; - CHECKREG r5, 0x39250000; - CHECKREG r6, 0xE4E43467; - CHECKREG r7, 0x189A2246; - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r0, 0x5567891b; - imm32 r1, 0x6789ab1d; - imm32 r2, 0x74445515; - imm32 r3, 0x86667777; - R0 = R6 +|- R0 , R7 = R6 -|+ R0 (CO , ASR); - R1 = R6 +|- R1 , R6 = R6 -|+ R1 (CO , ASL); - R2 = R6 +|- R2 , R5 = R6 -|+ R2 (CO , ASL); - R3 = R6 +|- R3 , R4 = R6 -|+ R3 (CO , ASR); - R4 = R6 +|- R4 , R3 = R6 -|+ R4 (CO , ASR); - R5 = R6 +|- R5 , R2 = R6 -|+ R5 (CO , ASR); - R6 = R6 +|- R6 , R1 = R6 -|+ R6 (CO , ASL); - R7 = R6 +|- R7 , R0 = R6 -|+ R7 (CO , ASR); - CHECKREG r0, 0xE3DF0EAF; - CHECKREG r1, 0xEAD80000; - CHECKREG r2, 0xC81F0FB9; - CHECKREG r3, 0x0B83C2F9; - CHECKREG r4, 0xFC0FEF32; - CHECKREG r5, 0xaF4F3297; - CHECKREG r6, 0xFC200000; - CHECKREG r7, 0xED701C21; - - imm32 r0, 0x67898911; - imm32 r1, 0xb789ab1d; - imm32 r2, 0x3b445515; - imm32 r3, 0x46b67717; - imm32 r0, 0x5567891b; - imm32 r1, 0x678bab1d; - imm32 r2, 0x7444b515; - imm32 r3, 0x86667b77; - R0 = R7 +|- R0 , R7 = R7 -|+ R0 (CO , ASR); - R1 = R7 +|- R1 , R6 = R7 -|+ R1 (CO , ASR); - R2 = R7 +|- R2 , R5 = R7 -|+ R2 (CO , ASL); - R3 = R7 +|- R3 , R4 = R7 -|+ R3 (CO , ASR); - R4 = R7 +|- R4 , R3 = R7 -|+ R4 (CO , ASL); - R5 = R7 +|- R5 , R2 = R7 -|+ R5 (CO , ASL); - R6 = R7 +|- R6 , R1 = R7 -|+ R6 (CO , ASL); - R7 = R7 +|- R7 , R0 = R7 -|+ R7 (CO , ASR); - CHECKREG r0, 0xCC040000; - CHECKREG r1, 0x031A2E1C; - CHECKREG r2, 0x1170A0D8; - CHECKREG r3, 0xE4405DC2; - CHECKREG r4, 0xECB64BD0; - CHECKREG r5, 0xA9A01EA0; - CHECKREG r6, 0x1C5C2CF6; - CHECKREG r7, 0xD29E0000; - - imm32 r0, 0xe5678911; - imm32 r1, 0x2e89ab1d; - imm32 r2, 0x34ee5515; - imm32 r3, 0x4666e717; - imm32 r0, 0x5567891b; - imm32 r1, 0x6789ae1d; - imm32 r2, 0x744455e5; - imm32 r3, 0x8666777e; - R4 = R2 +|- R5 , R3 = R2 -|+ R5 (CO , ASR); - R0 = R5 +|- R3 , R5 = R5 -|+ R3 (CO , ASL); - R2 = R6 +|- R2 , R0 = R6 -|+ R2 (CO , ASR); - R3 = R4 +|- R0 , R2 = R4 -|+ R0 (CO , ASR); - R7 = R7 +|- R6 , R6 = R7 -|+ R6 (CO , ASR); - R6 = R1 +|- R7 , R1 = R1 -|+ R7 (CO , ASL); - R5 = R0 +|- R4 , R7 = R0 -|+ R4 (CO , ASR); - R1 = R3 +|- R1 , R4 = R3 -|+ R1 (CO , ASL); - CHECKREG r0, 0x416dd40c; - CHECKREG r1, 0xaEE68766; - CHECKREG r2, 0xF7D7e6C2; - CHECKREG r3, 0x282F23CB; - CHECKREG r4, 0x07C6f1D6; - CHECKREG r5, 0x282FDC35; - CHECKREG r6, 0xBE0C8930; - CHECKREG r7, 0xF7D7193D; - - imm32 r0, 0xff678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x3f445515; - imm32 r3, 0x46f67717; - imm32 r0, 0x556f891b; - imm32 r1, 0x6789fb1d; - imm32 r2, 0x74445f15; - imm32 r3, 0x866677f7; - R4 = R3 +|- R3 , R5 = R3 -|+ R3 (CO , ASR); - R1 = R6 +|- R1 , R6 = R6 -|+ R1 (CO , ASL); - R6 = R1 +|- R4 , R4 = R1 -|+ R4 (CO , ASR); - R7 = R4 +|- R2 , R0 = R4 -|+ R2 (CO , ASL); - R2 = R2 +|- R6 , R1 = R2 -|+ R6 (CO , ASR); - R3 = R5 +|- R5 , R7 = R5 -|+ R5 (CO , ASL); - R5 = R7 +|- R7 , R3 = R7 -|+ R7 (CO , ASR); - R0 = R0 +|- R0 , R2 = R0 -|+ R0 (CO , ASR); - CHECKREG r0, 0x82EE0000; - CHECKREG r1, 0x369445BE; - CHECKREG r2, 0x339E0000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x0E136262; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0xe8C80E13; - CHECKREG r7, 0x00000000; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm.s deleted file mode 100644 index 3d62e56..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm.s +++ /dev/null @@ -1,263 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_rrppmm/c_dsp32alu_rrppmm.dsp -// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) amod0 -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x95679911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34945515; -imm32 r3, 0x46967717; -imm32 r4, 0x5597891b; -imm32 r5, 0x6989ab1d; -imm32 r6, 0x94445515; -imm32 r7, 0x96667777; -R0 = R0 +|+ R0, R7 = R0 -|- R0; -R1 = R0 +|+ R1, R6 = R0 -|- R1; -R2 = R0 +|+ R2, R5 = R0 -|- R2; -R3 = R0 +|+ R3, R4 = R0 -|- R3; -R4 = R0 +|+ R4, R3 = R0 -|- R4; -R5 = R0 +|+ R5, R2 = R0 -|- R5; -R6 = R0 +|+ R6, R1 = R0 -|- R6; -R7 = R0 +|+ R7, R0 = R0 -|- R7; -CHECKREG r0, 0x2ACE3222; -CHECKREG r1, 0x2789AB1D; -CHECKREG r2, 0x34945515; -CHECKREG r3, 0x46967717; -CHECKREG r4, 0x0F06ED2D; -CHECKREG r5, 0x21080F2F; -CHECKREG r6, 0x2E13B927; -CHECKREG r7, 0x2ACE3222; - -imm32 r0, 0x11678911; -imm32 r1, 0xa719ab1d; -imm32 r2, 0x3a415515; -imm32 r3, 0x46a67717; -imm32 r4, 0x556a891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445a15; -imm32 r7, 0x866677a7; -R0 = R1 +|+ R0, R7 = R1 -|- R0; -R1 = R1 +|+ R1, R6 = R1 -|- R1; -R2 = R1 +|+ R2, R5 = R1 -|- R2; -R3 = R1 +|+ R3, R4 = R1 -|- R3; -R4 = R1 +|+ R4, R3 = R1 -|- R4; -R5 = R1 +|+ R5, R2 = R1 -|- R5; -R6 = R1 +|+ R6, R1 = R1 -|- R6; -R7 = R1 +|+ R7, R0 = R1 -|- R7; -CHECKREG r0, 0xB880342E; -CHECKREG r1, 0x4E32563A; -CHECKREG r2, 0x3A415515; -CHECKREG r3, 0x46A67717; -CHECKREG r4, 0x55BE355D; -CHECKREG r5, 0x6223575F; -CHECKREG r6, 0x4E32563A; -CHECKREG r7, 0xE3E47846; - -imm32 r0, 0xb567891b; -imm32 r1, 0x2b89abbd; -imm32 r2, 0x34b45b15; -imm32 r3, 0x466bb717; -imm32 r4, 0x556bb91b; -imm32 r5, 0x67b9ab1d; -imm32 r6, 0x7b4455b5; -imm32 r7, 0xb666777b; -R0 = R2 +|+ R0, R7 = R2 -|- R0; -R1 = R2 +|+ R1, R6 = R2 -|- R1; -R2 = R2 +|+ R2, R5 = R2 -|- R2; -R3 = R2 +|+ R3, R4 = R2 -|- R3; -R4 = R2 +|+ R4, R3 = R2 -|- R4; -R5 = R2 +|+ R5, R2 = R2 -|- R5; -R6 = R2 +|+ R6, R1 = R2 -|- R6; -R7 = R2 +|+ R7, R0 = R2 -|- R7; -CHECKREG r0, 0xEA1BE430; -CHECKREG r1, 0x603D06D2; -CHECKREG r2, 0x6968B62A; -CHECKREG r3, 0x466BB717; -CHECKREG r4, 0x8C65B53D; -CHECKREG r5, 0x6968B62A; -CHECKREG r6, 0x72936582; -CHECKREG r7, 0xE8B58824; - -imm32 r0, 0xbc678c11; -imm32 r1, 0x27c9cb1d; -imm32 r2, 0x344c5515; -imm32 r3, 0x46c6c717; -imm32 r4, 0x55678c1b; -imm32 r5, 0x6c89abcd; -imm32 r6, 0x7444551c; -imm32 r7, 0x8c667777; -R0 = R3 +|+ R0, R7 = R3 -|- R0; -R1 = R3 +|+ R1, R6 = R3 -|- R1; -R2 = R3 +|+ R2, R5 = R3 -|- R2; -R3 = R3 +|+ R3, R4 = R3 -|- R3; -R4 = R3 +|+ R4, R3 = R3 -|- R4; -R5 = R3 +|+ R5, R2 = R3 -|- R5; -R6 = R3 +|+ R6, R1 = R3 -|- R6; -R7 = R3 +|+ R7, R0 = R3 -|- R7; -CHECKREG r0, 0x032D5328; -CHECKREG r1, 0x6E8F9234; -CHECKREG r2, 0x7B121C2C; -CHECKREG r3, 0x8D8C8E2E; -CHECKREG r4, 0x8D8C8E2E; -CHECKREG r5, 0xA0060030; -CHECKREG r6, 0xAC898A28; -CHECKREG r7, 0x17EBC934; - -imm32 r0, 0xd56789d1; -imm32 r1, 0x2d89abdd; -imm32 r2, 0x34d455d5; -imm32 r3, 0x4d667717; -imm32 r4, 0x5dd7891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0xd44d5515; -imm32 r7, 0xd666d777; -R0 = R4 +|+ R0, R7 = R4 -|- R0; -R1 = R4 +|+ R1, R6 = R4 -|- R1; -R2 = R4 +|+ R2, R5 = R4 -|- R2; -R3 = R4 +|+ R3, R4 = R4 -|- R3; -R4 = R4 +|+ R4, R3 = R4 -|- R4; -R5 = R4 +|+ R5, R2 = R4 -|- R5; -R6 = R4 +|+ R6, R1 = R4 -|- R6; -R7 = R4 +|+ R7, R0 = R4 -|- R7; -CHECKREG r0, 0x987224BE; -CHECKREG r1, 0xF09446CA; -CHECKREG r2, 0xF7DFF0C2; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x20E22408; -CHECKREG r5, 0x49E5574E; -CHECKREG r6, 0x51300146; -CHECKREG r7, 0xA9522352; - -imm32 r0, 0xc567a911; -imm32 r1, 0x278aab1d; -imm32 r2, 0x3c445515; -imm32 r3, 0x46a67717; -imm32 r4, 0x55c7891b; -imm32 r5, 0x6a8cab1d; -imm32 r6, 0x7444c515; -imm32 r7, 0xa6667c77; -R0 = R5 +|+ R0, R7 = R5 -|- R0; -R1 = R5 +|+ R1, R6 = R5 -|- R1; -R2 = R5 +|+ R2, R5 = R5 -|- R2; -R3 = R5 +|+ R3, R4 = R5 -|- R3; -R4 = R5 +|+ R4, R3 = R5 -|- R4; -R5 = R5 +|+ R5, R2 = R5 -|- R5; -R6 = R5 +|+ R6, R1 = R5 -|- R6; -R7 = R5 +|+ R7, R0 = R5 -|- R7; -CHECKREG r0, 0xB76BAA04; -CHECKREG r1, 0x198EAC10; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x46A67717; -CHECKREG r4, 0x15EA34F9; -CHECKREG r5, 0x5C90AC10; -CHECKREG r6, 0x9F92AC10; -CHECKREG r7, 0x01B5AE1C; - -imm32 r0, 0xd5678911; -imm32 r1, 0x2ddddd1d; -imm32 r2, 0x34ddd515; -imm32 r3, 0x46d67717; -imm32 r4, 0x5d6d891b; -imm32 r5, 0x6789db1d; -imm32 r6, 0x74445d15; -imm32 r7, 0xd66677d7; -R0 = R6 +|+ R0, R7 = R6 -|- R0; -R1 = R6 +|+ R1, R6 = R6 -|- R1; -R2 = R6 +|+ R2, R5 = R6 -|- R2; -R3 = R6 +|+ R3, R4 = R6 -|- R3; -R4 = R6 +|+ R4, R3 = R6 -|- R4; -R5 = R6 +|+ R5, R2 = R6 -|- R5; -R6 = R6 +|+ R6, R1 = R6 -|- R6; -R7 = R6 +|+ R7, R0 = R6 -|- R7; -CHECKREG r0, 0xEDF12BEC; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x34DDD515; -CHECKREG r3, 0x46D67717; -CHECKREG r4, 0x45F888D9; -CHECKREG r5, 0x57F12ADB; -CHECKREG r6, 0x8CCEFFF0; -CHECKREG r7, 0x2BABD3F4; - -imm32 r0, 0xf567a911; -imm32 r1, 0x2f8aab1d; -imm32 r2, 0x34a45515; -imm32 r3, 0x4a6f7717; -imm32 r4, 0x5567f91b; -imm32 r5, 0xa789af1d; -imm32 r6, 0x74445515; -imm32 r7, 0x866677f7; -R0 = R7 +|+ R0, R7 = R7 -|- R0; -R1 = R7 +|+ R1, R6 = R7 -|- R1; -R2 = R7 +|+ R2, R5 = R7 -|- R2; -R3 = R7 +|+ R3, R4 = R7 -|- R3; -R4 = R7 +|+ R4, R3 = R7 -|- R4; -R5 = R7 +|+ R5, R2 = R7 -|- R5; -R6 = R7 +|+ R6, R1 = R7 -|- R6; -R7 = R7 +|+ R7, R0 = R7 -|- R7; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x2F8AAB1D; -CHECKREG r2, 0x34A45515; -CHECKREG r3, 0x4A6F7717; -CHECKREG r4, 0xD78F26B5; -CHECKREG r5, 0xED5A48B7; -CHECKREG r6, 0xF274F2AF; -CHECKREG r7, 0x21FE9DCC; - -imm32 r0, 0xe5678911; -imm32 r1, 0x2e89ab1d; -imm32 r2, 0x34e45515; -imm32 r3, 0x46667717; -imm32 r4, 0x556e891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x7444e515; -imm32 r7, 0x86667e77; -R4 = R2 +|+ R5, R3 = R2 -|- R5 (S); -R0 = R5 +|+ R3, R5 = R5 -|- R3 (CO); -R2 = R6 +|+ R2, R0 = R6 -|- R2 (SCO); -R3 = R4 +|+ R0, R2 = R4 -|- R0 (S); -R7 = R7 +|+ R6, R6 = R7 -|- R6 (CO); -R6 = R1 +|+ R7, R1 = R1 -|- R7 (SCO); -R5 = R0 +|+ R4, R7 = R0 -|- R4 (S); -R1 = R3 +|+ R1, R4 = R3 -|- R1 (CO); -CHECKREG r0, 0x90003F60; -CHECKREG r1, 0x8FFF7371; -CHECKREG r2, 0x7FFFC0D2; -CHECKREG r3, 0x0FFF3F92; -CHECKREG r4, 0x0BB38FFF; -CHECKREG r5, 0x0FFF3F92; -CHECKREG r6, 0x29330EA9; -CHECKREG r7, 0x80003F2E; - -imm32 r0, 0xd5678911; -imm32 r1, 0xff89ab1d; -imm32 r2, 0x34f45515; -imm32 r3, 0x46667717; -imm32 r4, 0x556f891b; -imm32 r5, 0x6789fb1d; -imm32 r6, 0x74445f15; -imm32 r7, 0x866677f7; -R4 = R3 +|+ R3, R5 = R3 -|- R3 (SCO); -R1 = R6 +|+ R1, R6 = R6 -|- R1 (SCO); -R6 = R1 +|+ R4, R4 = R1 -|- R4 (S); -R7 = R4 +|+ R2, R0 = R4 -|- R2 (S); -R2 = R2 +|+ R6, R1 = R2 -|- R6 (CO); -R3 = R5 +|+ R5, R7 = R5 -|- R5 (CO); -R5 = R7 +|+ R7, R3 = R7 -|- R7 (SCO); -R0 = R0 +|+ R0, R2 = R0 -|- R0 (SCO); -CHECKREG r0, 0x80008000; -CHECKREG r1, 0xD516B4F5; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0xF3CE8A33; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x7FFF7FFF; -CHECKREG r7, 0x00000000; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft.s deleted file mode 100644 index 027f516..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft.s +++ /dev/null @@ -1,261 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft/c_dsp32alu_rrppmm_sft.dsp -// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, << -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - imm32 r0, 0x95679911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34945515; - imm32 r3, 0x46967717; - imm32 r4, 0x5597891b; - imm32 r5, 0x6989ab1d; - imm32 r6, 0x94445515; - imm32 r7, 0x96667777; - R0 = R0 +|+ R0, R7 = R0 -|- R0 (ASR); - R1 = R0 +|+ R1, R6 = R0 -|- R1 (ASL); - R2 = R0 +|+ R2, R5 = R0 -|- R2 (ASR); - R3 = R0 +|+ R3, R4 = R0 -|- R3 (ASR); - R4 = R0 +|+ R4, R3 = R0 -|- R4 (ASL); - R5 = R0 +|+ R5, R2 = R0 -|- R5 (ASR); - R6 = R0 +|+ R6, R1 = R0 -|- R6 (ASL); - R7 = R0 +|+ R7, R0 = R0 -|- R7 (ASR); - CHECKREG r0, 0xcAB3cC88; - CHECKREG r1, 0x73567A52; - CHECKREG r2, 0xf27FfB89; - CHECKREG r3, 0xdBFE1028; - CHECKREG r4, 0x799E541C; - CHECKREG r5, 0xa2E89D87; - CHECKREG r6, 0xE246e9F2; - CHECKREG r7, 0xcAB3cC88; - - imm32 r0, 0x11678911; - imm32 r1, 0xa719ab1d; - imm32 r2, 0x3a415515; - imm32 r3, 0x46a67717; - imm32 r4, 0x556a891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x74445a15; - imm32 r7, 0x866677a7; - R0 = R1 +|+ R0, R7 = R1 -|- R0 (ASR); - R1 = R1 +|+ R1, R6 = R1 -|- R1 (ASR); - R2 = R1 +|+ R2, R5 = R1 -|- R2 (ASL); - R3 = R1 +|+ R3, R4 = R1 -|- R3 (ASR); - R4 = R1 +|+ R4, R3 = R1 -|- R4 (ASR); - R5 = R1 +|+ R5, R2 = R1 -|- R5 (ASR); - R6 = R1 +|+ R6, R1 = R1 -|- R6 (ASL); - R7 = R1 +|+ R7, R0 = R1 -|- R7 (ASR); - CHECKREG r0, 0x41AC229A; - CHECKREG r1, 0x4E32563A; - CHECKREG r2, 0xe6B4fF86; - CHECKREG r3, 0xfB70088D; - CHECKREG r4, 0xaBA9a290; - CHECKREG r5, 0xc064aB96; - CHECKREG r6, 0x4E32563A; - CHECKREG r7, 0x0C8533A0; - - imm32 r0, 0xb567891b; - imm32 r1, 0x2b89abbd; - imm32 r2, 0x34b45b15; - imm32 r3, 0x466bb717; - imm32 r4, 0x556bb91b; - imm32 r5, 0x67b9ab1d; - imm32 r6, 0x7b4455b5; - imm32 r7, 0xb666777b; - R0 = R2 +|+ R0, R7 = R2 -|- R0 (ASR); - R1 = R2 +|+ R1, R6 = R2 -|- R1 (ASR); - R2 = R2 +|+ R2, R5 = R2 -|- R2 (ASR); - R3 = R2 +|+ R3, R4 = R2 -|- R3 (ASL); - R4 = R2 +|+ R4, R3 = R2 -|- R4 (ASR); - R5 = R2 +|+ R5, R2 = R2 -|- R5 (ASR); - R6 = R2 +|+ R6, R1 = R2 -|- R6 (ASL); - R7 = R2 +|+ R7, R0 = R2 -|- R7 (ASR); - CHECKREG r0, 0xED5Ae246; - CHECKREG r1, 0x2B8AaBBC; - CHECKREG r2, 0x1A5A2D8A; - CHECKREG r3, 0x2C11098C; - CHECKREG r4, 0x08A35188; - CHECKREG r5, 0x1A5A2D8A; - CHECKREG r6, 0x3DDE0A6C; - CHECKREG r7, 0x2D004B43; - - imm32 r0, 0xbc678c11; - imm32 r1, 0x27c9cb1d; - imm32 r2, 0x344c5515; - imm32 r3, 0x46c6c717; - imm32 r4, 0x55678c1b; - imm32 r5, 0x6c89abcd; - imm32 r6, 0x7444551c; - imm32 r7, 0x8c667777; - R0 = R3 +|+ R0, R7 = R3 -|- R0 (ASL); - R1 = R3 +|+ R1, R6 = R3 -|- R1 (ASR); - R2 = R3 +|+ R2, R5 = R3 -|- R2 (ASR); - R3 = R3 +|+ R3, R4 = R3 -|- R3 (ASR); - R4 = R3 +|+ R4, R3 = R3 -|- R4 (ASL); - R5 = R3 +|+ R5, R2 = R3 -|- R5 (ASR); - R6 = R3 +|+ R6, R1 = R3 -|- R6 (ASR); - R7 = R3 +|+ R7, R0 = R3 -|- R7 (ASL); - CHECKREG r0, 0xF19C3044; - CHECKREG r1, 0xbF07C818; - CHECKREG r2, 0xC227eA96; - CHECKREG r3, 0x8D8C8E2E; - CHECKREG r4, 0x8D8C8E2E; - CHECKREG r5, 0xCB64a397; - CHECKREG r6, 0xCE85C615; - CHECKREG r7, 0x44940874; - - imm32 r0, 0xd56789d1; - imm32 r1, 0x2d89abdd; - imm32 r2, 0x34d455d5; - imm32 r3, 0x4d667717; - imm32 r4, 0x5dd7891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0xd44d5515; - imm32 r7, 0xd666d777; - R0 = R4 +|+ R0, R7 = R4 -|- R0 (ASR); - R1 = R4 +|+ R1, R6 = R4 -|- R1 (ASR); - R2 = R4 +|+ R2, R5 = R4 -|- R2 (ASR); - R3 = R4 +|+ R3, R4 = R4 -|- R3 (ASL); - R4 = R4 +|+ R4, R3 = R4 -|- R4 (ASR); - R5 = R4 +|+ R5, R2 = R4 -|- R5 (ASL); - R6 = R4 +|+ R6, R1 = R4 -|- R6 (ASR); - R7 = R4 +|+ R7, R0 = R4 -|- R7 (ASR); - CHECKREG r0, 0xeE551231; - CHECKREG r1, 0x045D1AB4; - CHECKREG r2, 0x18C214CA; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x20E22408; - CHECKREG r5, 0x6AC67B56; - CHECKREG r6, 0x1C840953; - CHECKREG r7, 0x328D11D6; - - imm32 r0, 0xc567a911; - imm32 r1, 0x278aab1d; - imm32 r2, 0x3c445515; - imm32 r3, 0x46a67717; - imm32 r4, 0x55c7891b; - imm32 r5, 0x6a8cab1d; - imm32 r6, 0x7444c515; - imm32 r7, 0xa6667c77; - R0 = R5 +|+ R0, R7 = R5 -|- R0 (ASR); - R1 = R5 +|+ R1, R6 = R5 -|- R1 (ASL); - R2 = R5 +|+ R2, R5 = R5 -|- R2 (ASR); - R3 = R5 +|+ R3, R4 = R5 -|- R3 (ASR); - R4 = R5 +|+ R4, R3 = R5 -|- R4 (ASR); - R5 = R5 +|+ R5, R2 = R5 -|- R5 (ASL); - R6 = R5 +|+ R6, R1 = R5 -|- R6 (ASR); - R7 = R5 +|+ R7, R0 = R5 -|- R7 (ASR); - CHECKREG r0, 0x04FFD585; - CHECKREG r1, 0x6B46D608; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x17720887; - CHECKREG r4, 0xFFB1a27D; - CHECKREG r5, 0x5C90AC10; - CHECKREG r6, 0xF14AD608; - CHECKREG r7, 0x5791D68B; - - imm32 r0, 0xd5678911; - imm32 r1, 0x2ddddd1d; - imm32 r2, 0x34ddd515; - imm32 r3, 0x46d67717; - imm32 r4, 0x5d6d891b; - imm32 r5, 0x6789db1d; - imm32 r6, 0x74445d15; - imm32 r7, 0xd66677d7; - R0 = R6 +|+ R0, R7 = R6 -|- R0 (ASR); - R1 = R6 +|+ R1, R6 = R6 -|- R1 (ASR); - R2 = R6 +|+ R2, R5 = R6 -|- R2 (ASR); - R3 = R6 +|+ R3, R4 = R6 -|- R3 (ASL); - R4 = R6 +|+ R4, R3 = R6 -|- R4 (ASR); - R5 = R6 +|+ R5, R2 = R6 -|- R5 (ASR); - R6 = R6 +|+ R6, R1 = R6 -|- R6 (ASL); - R7 = R6 +|+ R7, R0 = R6 -|- R7 (ASR); - CHECKREG r0, 0x9EAFcAF7; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x16040544; - CHECKREG r3, 0x353C5719; - CHECKREG r4, 0xEDF6E8E3; - CHECKREG r5, 0x0D2F3AB7; - CHECKREG r6, 0x8CCCFFF0; - CHECKREG r7, 0xeE1D34F9; - - imm32 r0, 0xf567a911; - imm32 r1, 0x2f8aab1d; - imm32 r2, 0x34a45515; - imm32 r3, 0x4a6f7717; - imm32 r4, 0x5567f91b; - imm32 r5, 0xa789af1d; - imm32 r6, 0x74445515; - imm32 r7, 0x866677f7; - R0 = R7 +|+ R0, R7 = R7 -|- R0 (ASR); - R1 = R7 +|+ R1, R6 = R7 -|- R1 (ASL); - R2 = R7 +|+ R2, R5 = R7 -|- R2 (ASR); - R3 = R7 +|+ R3, R4 = R7 -|- R3 (ASR); - R4 = R7 +|+ R4, R3 = R7 -|- R4 (ASL); - R5 = R7 +|+ R5, R2 = R7 -|- R5 (ASL); - R6 = R7 +|+ R6, R1 = R7 -|- R6 (ASR); - R7 = R7 +|+ R7, R0 = R7 -|- R7 (ASL); - CHECKREG r0, 0x00000000; - CHECKREG r1, 0xCB4Af763; - CHECKREG r2, 0xFD24bC88; - CHECKREG r3, 0x12EEdE8A; - CHECKREG r4, 0x0F0EbF42; - CHECKREG r5, 0x24D8e144; - CHECKREG r6, 0xFD34700F; - CHECKREG r7, 0x21FC9DCC; - - imm32 r0, 0xe5678911; - imm32 r1, 0x2e89ab1d; - imm32 r2, 0x34e45515; - imm32 r3, 0x46667717; - imm32 r4, 0x556e891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x7444e515; - imm32 r7, 0x86667e77; - R4 = R2 +|+ R5, R3 = R2 -|- R5 (ASR); - R0 = R5 +|+ R3, R5 = R5 -|- R3 (ASL); - R2 = R6 +|+ R2, R0 = R6 -|- R2 (ASL); - R3 = R4 +|+ R0, R2 = R4 -|- R0 (ASR); - R7 = R7 +|+ R6, R6 = R7 -|- R6 (ASL); - R6 = R1 +|+ R7, R1 = R1 -|- R7 (ASL); - R5 = R0 +|+ R4, R7 = R0 -|- R4 (ASR); - R1 = R3 +|+ R1, R4 = R3 -|- R1 (ASR); - CHECKREG r0, 0x7EC02000; - CHECKREG r1, 0x6C72EC0B; - CHECKREG r2, 0xe7BBF00C; - CHECKREG r3, 0x667B100C; - CHECKREG r4, 0xfA082401; - CHECKREG r5, 0x667B100C; - CHECKREG r6, 0x47BAE46A; - CHECKREG r7, 0x18450FF3; - - imm32 r0, 0xd5678911; - imm32 r1, 0xff89ab1d; - imm32 r2, 0x34f45515; - imm32 r3, 0x46667717; - imm32 r4, 0x556f891b; - imm32 r5, 0x6789fb1d; - imm32 r6, 0x74445f15; - imm32 r7, 0x866677f7; - R4 = R3 +|+ R3, R5 = R3 -|- R3 (ASR); - R1 = R6 +|+ R1, R6 = R6 -|- R1 (ASL); - R6 = R1 +|+ R4, R4 = R1 -|- R4 (ASL); - R7 = R4 +|+ R2, R0 = R4 -|- R2 (ASR); - R2 = R2 +|+ R6, R1 = R2 -|- R6 (ASR); - R3 = R5 +|+ R5, R7 = R5 -|- R5 (ASL); - R5 = R7 +|+ R7, R3 = R7 -|- R7 (ASL); - R0 = R0 +|+ R0, R2 = R0 -|- R0 (ASR); - CHECKREG r0, 0x06BAF2C2; - CHECKREG r1, 0xEC7A1F0F; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x42683A9A; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x5C0016F6; - CHECKREG r7, 0x00000000; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft_x.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft_x.s deleted file mode 100644 index 32913f6..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft_x.s +++ /dev/null @@ -1,261 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft_x/c_dsp32alu_rrppmm_sft_x.dsp -// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, << X -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - imm32 r0, 0x95679911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34945515; - imm32 r3, 0x46967717; - imm32 r4, 0x5597891b; - imm32 r5, 0x6989ab1d; - imm32 r6, 0x94445515; - imm32 r7, 0x96667777; - R0 = R0 +|+ R0, R7 = R0 -|- R0 (CO , ASR); - R1 = R0 +|+ R1, R6 = R0 -|- R1 (CO , ASL); - R2 = R0 +|+ R2, R5 = R0 -|- R2 (CO , ASR); - R3 = R0 +|+ R3, R4 = R0 -|- R3 (CO , ASR); - R4 = R0 +|+ R4, R3 = R0 -|- R4 (CO , ASL); - R5 = R0 +|+ R5, R2 = R0 -|- R5 (CO , ASR); - R6 = R0 +|+ R6, R1 = R0 -|- R6 (CO , ASL); - R7 = R0 +|+ R7, R0 = R0 -|- R7 (CO , ASR); - CHECKREG r0, 0xcC88cAB3; - CHECKREG r1, 0x7AAA72FE; - CHECKREG r2, 0xf454f9B4; - CHECKREG r3, 0xe35208D4; - CHECKREG r4, 0x4CC880F2; - CHECKREG r5, 0x9BB2a4BD; - CHECKREG r6, 0xE29EE99A; - CHECKREG r7, 0xcAB3cC88; - - imm32 r0, 0x11678911; - imm32 r1, 0xa719ab1d; - imm32 r2, 0x3a415515; - imm32 r3, 0x46a67717; - imm32 r4, 0x556a891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x74445a15; - imm32 r7, 0x866677a7; - R0 = R1 +|+ R0, R7 = R1 -|- R0 (CO , ASR); - R1 = R1 +|+ R1, R6 = R1 -|- R1 (CO , ASR); - R2 = R1 +|+ R2, R5 = R1 -|- R2 (CO , ASL); - R3 = R1 +|+ R3, R4 = R1 -|- R3 (CO , ASR); - R4 = R1 +|+ R4, R3 = R1 -|- R4 (CO , ASR); - R5 = R1 +|+ R5, R2 = R1 -|- R5 (CO , ASR); - R6 = R1 +|+ R6, R1 = R1 -|- R6 (CO , ASL); - R7 = R1 +|+ R7, R0 = R1 -|- R7 (CO , ASR); - CHECKREG r0, 0x41AC229A; - CHECKREG r1, 0x563A4E32; - CHECKREG r2, 0xe8B6fD84; - CHECKREG r3, 0xfD72068B; - CHECKREG r4, 0xa08EaDAB; - CHECKREG r5, 0xa994c266; - CHECKREG r6, 0x4E32563A; - CHECKREG r7, 0x33A00C85; - - imm32 r0, 0xb567891b; - imm32 r1, 0x2b89abbd; - imm32 r2, 0x34b45b15; - imm32 r3, 0x466bb717; - imm32 r4, 0x556bb91b; - imm32 r5, 0x67b9ab1d; - imm32 r6, 0x7b4455b5; - imm32 r7, 0xb666777b; - R0 = R2 +|+ R0, R7 = R2 -|- R0 (CO , ASR); - R1 = R2 +|+ R1, R6 = R2 -|- R1 (CO , ASR); - R2 = R2 +|+ R2, R5 = R2 -|- R2 (CO , ASR); - R3 = R2 +|+ R3, R4 = R2 -|- R3 (CO , ASL); - R4 = R2 +|+ R4, R3 = R2 -|- R4 (CO , ASR); - R5 = R2 +|+ R5, R2 = R2 -|- R5 (CO , ASR); - R6 = R2 +|+ R6, R1 = R2 -|- R6 (CO , ASL); - R7 = R2 +|+ R7, R0 = R2 -|- R7 (CO , ASR); - CHECKREG r0, 0xED5Ae246; - CHECKREG r1, 0x2B8AaBBC; - CHECKREG r2, 0x2D8A1A5A; - CHECKREG r3, 0x3F41F65C; - CHECKREG r4, 0x3E581BD3; - CHECKREG r5, 0x1A5A2D8A; - CHECKREG r6, 0x0A6C3DDE; - CHECKREG r7, 0x4B432D00; - - imm32 r0, 0xbc678c11; - imm32 r1, 0x27c9cb1d; - imm32 r2, 0x344c5515; - imm32 r3, 0x46c6c717; - imm32 r4, 0x55678c1b; - imm32 r5, 0x6c89abcd; - imm32 r6, 0x7444551c; - imm32 r7, 0x8c667777; - R0 = R3 +|+ R0, R7 = R3 -|- R0 (CO , ASL); - R1 = R3 +|+ R1, R6 = R3 -|- R1 (CO , ASR); - R2 = R3 +|+ R2, R5 = R3 -|- R2 (CO , ASR); - R3 = R3 +|+ R3, R4 = R3 -|- R3 (CO , ASR); - R4 = R3 +|+ R4, R3 = R3 -|- R4 (CO , ASL); - R5 = R3 +|+ R5, R2 = R3 -|- R5 (CO , ASR); - R6 = R3 +|+ R6, R1 = R3 -|- R6 (CO , ASR); - R7 = R3 +|+ R7, R0 = R3 -|- R7 (CO , ASL); - CHECKREG r0, 0xF19C3044; - CHECKREG r1, 0xbF07C818; - CHECKREG r2, 0xC227eA96; - CHECKREG r3, 0x8E2E8D8C; - CHECKREG r4, 0x8D8C8E2E; - CHECKREG r5, 0xa397CB64; - CHECKREG r6, 0xC615CE85; - CHECKREG r7, 0x08744494; - - imm32 r0, 0xd56789d1; - imm32 r1, 0x2d89abdd; - imm32 r2, 0x34d455d5; - imm32 r3, 0x4d667717; - imm32 r4, 0x5dd7891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0xd44d5515; - imm32 r7, 0xd666d777; - R0 = R4 +|+ R0, R7 = R4 -|- R0 (CO , ASR); - R1 = R4 +|+ R1, R6 = R4 -|- R1 (CO , ASR); - R2 = R4 +|+ R2, R5 = R4 -|- R2 (CO , ASR); - R3 = R4 +|+ R3, R4 = R4 -|- R3 (CO , ASL); - R4 = R4 +|+ R4, R3 = R4 -|- R4 (CO , ASR); - R5 = R4 +|+ R5, R2 = R4 -|- R5 (CO , ASL); - R6 = R4 +|+ R6, R1 = R4 -|- R6 (CO , ASR); - R7 = R4 +|+ R7, R0 = R4 -|- R7 (CO , ASR); - CHECKREG r0, 0xeE551231; - CHECKREG r1, 0x045D1AB4; - CHECKREG r2, 0x18C214CA; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x240820E2; - CHECKREG r5, 0x7B566AC6; - CHECKREG r6, 0x09531C84; - CHECKREG r7, 0x11D6328D; - - imm32 r0, 0xc567a911; - imm32 r1, 0x278aab1d; - imm32 r2, 0x3c445515; - imm32 r3, 0x46a67717; - imm32 r4, 0x55c7891b; - imm32 r5, 0x6a8cab1d; - imm32 r6, 0x7444c515; - imm32 r7, 0xa6667c77; - R0 = R5 +|+ R0, R7 = R5 -|- R0 (CO , ASR); - R1 = R5 +|+ R1, R6 = R5 -|- R1 (CO , ASL); - R2 = R5 +|+ R2, R5 = R5 -|- R2 (CO , ASR); - R3 = R5 +|+ R3, R4 = R5 -|- R3 (CO , ASR); - R4 = R5 +|+ R4, R3 = R5 -|- R4 (CO , ASR); - R5 = R5 +|+ R5, R2 = R5 -|- R5 (CO , ASL); - R6 = R5 +|+ R6, R1 = R5 -|- R6 (CO , ASR); - R7 = R5 +|+ R7, R0 = R5 -|- R7 (CO , ASR); - CHECKREG r0, 0x04FFD585; - CHECKREG r1, 0x6B46D608; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x327AeD7F; - CHECKREG r4, 0xbD85e4A9; - CHECKREG r5, 0xAC105C90; - CHECKREG r6, 0xD608F14A; - CHECKREG r7, 0xD68B5791; - - imm32 r0, 0xd5678911; - imm32 r1, 0x2ddddd1d; - imm32 r2, 0x34ddd515; - imm32 r3, 0x46d67717; - imm32 r4, 0x5d6d891b; - imm32 r5, 0x6789db1d; - imm32 r6, 0x74445d15; - imm32 r7, 0xd66677d7; - R0 = R6 +|+ R0, R7 = R6 -|- R0 (CO , ASR); - R1 = R6 +|+ R1, R6 = R6 -|- R1 (CO , ASR); - R2 = R6 +|+ R2, R5 = R6 -|- R2 (CO , ASR); - R3 = R6 +|+ R3, R4 = R6 -|- R3 (CO , ASL); - R4 = R6 +|+ R4, R3 = R6 -|- R4 (CO , ASR); - R5 = R6 +|+ R5, R2 = R6 -|- R5 (CO , ASR); - R6 = R6 +|+ R6, R1 = R6 -|- R6 (CO , ASL); - R7 = R6 +|+ R7, R0 = R6 -|- R7 (CO , ASR); - CHECKREG r0, 0x9EAFcAF7; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x0ED20C76; - CHECKREG r3, 0x1873F3E2; - CHECKREG r4, 0x4C1A0ABF; - CHECKREG r5, 0x33851461; - CHECKREG r6, 0xFFF08CCC; - CHECKREG r7, 0x34F9eE1D; - - imm32 r0, 0xf567a911; - imm32 r1, 0x2f8aab1d; - imm32 r2, 0x34a45515; - imm32 r3, 0x4a6f7717; - imm32 r4, 0x5567f91b; - imm32 r5, 0xa789af1d; - imm32 r6, 0x74445515; - imm32 r7, 0x866677f7; - R0 = R7 +|+ R0, R7 = R7 -|- R0 (CO , ASR); - R1 = R7 +|+ R1, R6 = R7 -|- R1 (CO , ASL); - R2 = R7 +|+ R2, R5 = R7 -|- R2 (CO , ASR); - R3 = R7 +|+ R3, R4 = R7 -|- R3 (CO , ASR); - R4 = R7 +|+ R4, R3 = R7 -|- R4 (CO , ASL); - R5 = R7 +|+ R5, R2 = R7 -|- R5 (CO , ASL); - R6 = R7 +|+ R6, R1 = R7 -|- R6 (CO , ASR); - R7 = R7 +|+ R7, R0 = R7 -|- R7 (CO , ASL); - CHECKREG r0, 0x00000000; - CHECKREG r1, 0xaC561657; - CHECKREG r2, 0x5E305B7C; - CHECKREG r3, 0x73FA7D7E; - CHECKREG r4, 0x204EaE02; - CHECKREG r5, 0x4250c3CC; - CHECKREG r6, 0x511B1C28; - CHECKREG r7, 0x9DCC21FC; - - imm32 r0, 0xe5678911; - imm32 r1, 0x2e89ab1d; - imm32 r2, 0x34e45515; - imm32 r3, 0x46667717; - imm32 r4, 0x556e891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x7444e515; - imm32 r7, 0x86667e77; - R4 = R2 +|+ R5, R3 = R2 -|- R5 (CO , ASR); - R0 = R5 +|+ R3, R5 = R5 -|- R3 (CO , ASL); - R2 = R6 +|+ R2, R0 = R6 -|- R2 (CO , ASL); - R3 = R4 +|+ R0, R2 = R4 -|- R0 (CO , ASR); - R7 = R7 +|+ R6, R6 = R7 -|- R6 (CO , ASL); - R6 = R1 +|+ R7, R1 = R1 -|- R7 (CO , ASL); - R5 = R0 +|+ R4, R7 = R0 -|- R4 (CO , ASR); - R1 = R3 +|+ R1, R4 = R3 -|- R1 (CO , ASR); - CHECKREG r0, 0x20007EC0; - CHECKREG r1, 0xfF9258EB; - CHECKREG r2, 0xC0AC171B; - CHECKREG r3, 0x371B3F6C; - CHECKREG r4, 0xE6813788; - CHECKREG r5, 0x371B3F6C; - CHECKREG r6, 0x47BAE46A; - CHECKREG r7, 0x3F53e8E5; - - imm32 r0, 0xd5678911; - imm32 r1, 0xff89ab1d; - imm32 r2, 0x34f45515; - imm32 r3, 0x46667717; - imm32 r4, 0x556f891b; - imm32 r5, 0x6789fb1d; - imm32 r6, 0x74445f15; - imm32 r7, 0x866677f7; - R4 = R3 +|+ R3, R5 = R3 -|- R3 (CO , ASR); - R1 = R6 +|+ R1, R6 = R6 -|- R1 (CO , ASL); - R6 = R1 +|+ R4, R4 = R1 -|- R4 (CO , ASL); - R7 = R4 +|+ R2, R0 = R4 -|- R2 (CO , ASR); - R2 = R2 +|+ R6, R1 = R2 -|- R6 (CO , ASR); - R3 = R5 +|+ R5, R7 = R5 -|- R5 (CO , ASL); - R5 = R7 +|+ R7, R3 = R7 -|- R7 (CO , ASL); - R0 = R0 +|+ R0, R2 = R0 -|- R0 (CO , ASR); - CHECKREG r0, 0xF6A902D3; - CHECKREG r1, 0x1F0FEC7A; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x3A9A4268; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x5C0016F6; - CHECKREG r7, 0x00000000; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_saa.s b/sim/testsuite/sim/bfin/c_dsp32alu_saa.s deleted file mode 100644 index 6cb577e..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_saa.s +++ /dev/null @@ -1,70 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_saa/c_dsp32alu_saa.dsp -// Spec Reference: dsp32alu saa -# mach: bfin - -.include "testutils.inc" - start - - A1 = 0; - A0 = 0; - - imm32 r0, 0x15678911; - imm32 r1, 0x2789ab1d; - imm32 r2, 0x34445515; - imm32 r3, 0x46667717; - imm32 r4, 0x5567891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0x74445515; - imm32 r7, 0x86667777; - A0 = 0; - A1 = 0; - SAA ( R1:0 , R3:2 ); - R4 = A0.w; - R5 = A1.w; - CHECKREG r4, 0x00340004; - CHECKREG r5, 0x001F0023; - SAA ( R3:2 , R1:0 ); - R6 = A0.w; - R7 = A1.w; - CHECKREG r6, 0x00680008; - CHECKREG r7, 0x003E0046; - - imm32 r0, 0x1567892b; - imm32 r1, 0x2789ab2d; - imm32 r2, 0x34445525; - imm32 r3, 0x46667727; - imm32 r4, 0x00340004; - imm32 r5, 0x001F0023; - imm32 r6, 0x00680008; - imm32 r7, 0x003E0046; - SAA ( R1:0 , R3:2 ); - R0 = A0.w; - R1 = A1.w; - CHECKREG r0, 0x009C000E; - CHECKREG r1, 0x005D0069; - SAA ( R3:2 , R1:0 ); - R2 = A0.w; - R3 = A1.w; - CHECKREG r2, 0x00F10025; - CHECKREG r3, 0x009100C1; - - imm32 r0, 0x496789ab; - imm32 r1, 0x6489abcd; - imm32 r2, 0x4b445555; - imm32 r3, 0x6c647777; - imm32 r4, 0x8d889999; - imm32 r5, 0xaeaa4bbb; - imm32 r6, 0xcfccd44d; - imm32 r7, 0xe1eefff4; - SAA ( R3:2 , R1:0 ) (R); - R0 = A0.w; - R1 = A1.w; - CHECKREG r0, 0x0125007B; - CHECKREG r1, 0x009900E6; - SAA ( R1:0 , R3:2 ) (R); - R6 = A0.w; - R7 = A1.w; - CHECKREG r6, 0x019C00EA; - CHECKREG r7, 0x0105011B; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_sat_aa.S b/sim/testsuite/sim/bfin/c_dsp32alu_sat_aa.S deleted file mode 100644 index 981de01..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_sat_aa.S +++ /dev/null @@ -1,41 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32alu_sat_aa/c_dsp32alu_sat_aa.dsp -// Spec Reference: dsp32alu sat ( a1, a0) -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - A0 = A1 = 0; - - imm32 r0, 0xabefda8f; - imm32 r1, 0x789abced; - imm32 r2, 0x3b44b515; - imm32 r3, 0x96667717; - imm32 r4, 0x5567891b; - imm32 r5, 0x6789ab1d; - imm32 r6, 0xabcdef89; - imm32 r7, 0xefadbc8a; - A0 = R0; - A1 = R1; - A1 = A1 (S), A0 = A0 (S); - R0 = ASTAT; - R2 = A0.w; - R3 = A1.w; - - A0 = R6; - A1 = R7; - A1 = A1 (S), A0 = A0 (S); - R1 = ASTAT; - R4 = A0.w; - R5 = A1.w; - CHECKREG r0, _AN; - CHECKREG r1, _AN; - CHECKREG r2, 0xABEFDA8F; - CHECKREG r3, 0x789ABCED; - CHECKREG r4, 0xABCDEF89; - CHECKREG r5, 0xEFADBC8A; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_search.s b/sim/testsuite/sim/bfin/c_dsp32alu_search.s deleted file mode 100644 index 68b3d32..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_search.s +++ /dev/null @@ -1,74 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_search/c_dsp32alu_search.dsp -// Spec Reference: dsp32alu search -# mach: bfin - -.include "testutils.inc" - start - -imm32 p0, 0x11234556; - -imm32 r0, 0x15678911; -imm32 r1, 0x2789ab1d; -imm32 r2, 0x34445515; -imm32 r3, 0x46667717; -imm32 r4, 0x5567891b; -imm32 r5, 0x6789ab1d; -imm32 r6, 0x74445515; -imm32 r7, 0x86667777; -( R0 , R1 ) = SEARCH R2 (GE); -( R2 , R3 ) = SEARCH R4 (GT); -( R4 , R5 ) = SEARCH R0 (LE); -( R7 , R6 ) = SEARCH R1 (LT); -CHECKREG r0, 0x11234556; -CHECKREG r1, 0x11234556; -CHECKREG r2, 0x11234556; -CHECKREG r3, 0x46667717; -CHECKREG r4, 0x11234556; -CHECKREG r5, 0x11234556; -CHECKREG r6, 0x74445515; -CHECKREG r7, 0x86667777; - -imm32 r0, 0x416789ab; -imm32 r1, 0x6289abcd; -imm32 r2, 0x43445555; -imm32 r3, 0x64667777; -imm32 r0, 0x456789ab; -imm32 r1, 0x6689abcd; -imm32 r2, 0x47445555; -imm32 r3, 0x68667777; -( R2 , R1 ) = SEARCH R3 (LE); -( R6 , R3 ) = SEARCH R5 (GT); -( R4 , R7 ) = SEARCH R2 (GE); -( R0 , R5 ) = SEARCH R4 (LT); -CHECKREG r0, 0x11234556; -CHECKREG r1, 0x6689ABCD; -CHECKREG r2, 0x47445555; -CHECKREG r3, 0x68667777; -CHECKREG r4, 0x11234556; -CHECKREG r5, 0x11234556; -CHECKREG r6, 0x74445515; -CHECKREG r7, 0x11234556; - -imm32 r0, 0x516789ab; -imm32 r1, 0x6289abcd; -imm32 r2, 0x73445555; -imm32 r3, 0x84667777; -imm32 r0, 0x956789ab; -imm32 r1, 0xa689abcd; -imm32 r2, 0xb7445555; -imm32 r3, 0xc86def77; -( R3 , R4 ) = SEARCH R5 (GT); -( R0 , R7 ) = SEARCH R6 (GE); -( R6 , R1 ) = SEARCH R2 (LT); -( R2 , R5 ) = SEARCH R4 (LE); -CHECKREG r0, 0x11234556; -CHECKREG r1, 0xA689ABCD; -CHECKREG r2, 0xB7445555; -CHECKREG r3, 0xC86DEF77; -CHECKREG r4, 0x11234556; -CHECKREG r5, 0x11234556; -CHECKREG r6, 0x11234556; -CHECKREG r7, 0x11234556; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_sgn.s b/sim/testsuite/sim/bfin/c_dsp32alu_sgn.s deleted file mode 100644 index de36c20..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32alu_sgn.s +++ /dev/null @@ -1,39 +0,0 @@ -//Original:/testcases/core/c_dsp32alu_sgn/c_dsp32alu_sgn.dsp -// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x456789ab; -imm32 r1, 0x6689abcd; -imm32 r2, 0x47445555; -imm32 r3, 0x68667777; -R4.H = R4.L = SIGN(R2.H) * R0.H + SIGN(R2.L) * R0.L; -R5.H = R5.L = SIGN(R2.H) * R1.H + SIGN(R2.L) * R1.L; -R6.H = R6.L = SIGN(R2.H) * R2.H + SIGN(R2.L) * R2.L; -R7.H = R7.L = SIGN(R2.H) * R3.H + SIGN(R2.L) * R3.L; -CHECKREG r4, 0xCF12CF12; -CHECKREG r5, 0x12561256; -CHECKREG r6, 0x9C999C99; -CHECKREG r7, 0xDFDDDFDD; - -imm32 r0, 0x496789ab; -imm32 r1, 0x6489abcd; -imm32 r2, 0x4b445555; -imm32 r3, 0x6c647777; -imm32 r4, 0x8d889999; -imm32 r5, 0xaeaa4bbb; -imm32 r6, 0xcfccd44d; -imm32 r7, 0xe1eefff4; -R0.H = R0.L = SIGN(R3.H) * R4.H + SIGN(R3.L) * R4.L; -R1.H = R1.L = SIGN(R3.H) * R5.H + SIGN(R3.L) * R5.L; -R2.H = R2.L = SIGN(R3.H) * R6.H + SIGN(R3.L) * R6.L; -R3.H = R3.L = SIGN(R3.H) * R7.H + SIGN(R3.L) * R7.L; -CHECKREG r0, 0x27212721; -CHECKREG r1, 0xFA65FA65; -CHECKREG r2, 0xA419A419; -CHECKREG r3, 0xE1E2E1E2; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_a1a0.s b/sim/testsuite/sim/bfin/c_dsp32mac_a1a0.s deleted file mode 100644 index 25c2a2d..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_a1a0.s +++ /dev/null @@ -1,255 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_a1a0/c_dsp32mac_a1a0.dsp -// Spec Reference: dsp32mac a1 a0 -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -imm32 r0, 0x00000000; -A0 = 0; -A1 = 0; -ASTAT = r0; - - -// test the default (signed fraction : left ) -imm32 r0, 0x12345678; -imm32 r1, 0x33456789; -imm32 r2, 0x5556789a; -imm32 r3, 0x75678912; -imm32 r4, 0x86789123; -imm32 r5, 0xa7891234; -imm32 r6, 0xc1234567; -imm32 r7, 0xf1234567; -A1 = R0.L * R1.L, A0 = R0.L * R1.L; -R0 = A0.w; -R1 = A1.w; -A1 = R2.L * R3.L, A0 += R2.L * R3.H; -R2 = A0.w; -R3 = A1.w; -A1 += R4.L * R5.L, A0 = R4.H * R5.L; -R4 = A0.w; -R5 = A1.w; -A1 += R6.L * R7.L, A0 += R6.H * R7.H; -R6 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x45F11C70; -CHECKREG r1, 0x45F11C70; -CHECKREG r2, 0xB48EEC5C; -CHECKREG r3, 0x8FF1C9A8; -CHECKREG r4, 0xEEB780C0; -CHECKREG r5, 0x802DABE0; -CHECKREG r6, 0xF6043652; -CHECKREG r7, 0xA5CF0AC2; - -imm32 r0, 0x12245618; -imm32 r1, 0x23256719; -imm32 r2, 0x3426781a; -imm32 r3, 0x45278912; -imm32 r4, 0x56289113; -imm32 r5, 0x67291214; -imm32 r6, 0xa1234517; -imm32 r7, 0xc1234517; -A1 = R0.L * R1.H, A0 += R0.L * R1.L; -R0 = A0.w; -R1 = A1.w; -A1 = R2.L * R3.H, A0 += R2.L * R3.H; -R2 = A0.w; -R3 = A1.w; -A1 = R4.L * R5.H, A0 += R4.H * R5.L; -R4 = A0.w; -R5 = A1.w; -A1 = R6.L * R7.H, A0 += R6.H * R7.H; -R6 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x3B5C5702; -CHECKREG r1, 0x17A372F0; -CHECKREG r2, 0x7C3EF2EE; -CHECKREG r3, 0x40E29BEC; -CHECKREG r4, 0x886A092E; -CHECKREG r5, 0xA699C216; -CHECKREG r6, 0xB700DEC0; -CHECKREG r7, 0xDE11924A; - -imm32 r0, 0x15245648; -imm32 r1, 0x25256749; -imm32 r2, 0x3526784a; -imm32 r3, 0x45278942; -imm32 r4, 0x55389143; -imm32 r5, 0x65391244; -imm32 r6, 0xa5334547; -imm32 r7, 0xc5334547; -A1 += R0.H * R1.H, A0 = R0.L * R1.L; -R0 = A0.w; -R1 = A1.w; -A1 += R2.H * R3.H, A0 = R2.L * R3.H; -R2 = A0.w; -R3 = A1.w; -A1 += R4.H * R5.H, A0 = R4.H * R5.L; -R4 = A0.w; -R5 = A1.w; -A1 += R6.H * R7.H, A0 = R6.H * R7.H; -R6 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x459F2510; -CHECKREG r1, 0xE43416B2; -CHECKREG r2, 0x40FC8A8C; -CHECKREG r3, 0x00EAC446; -CHECKREG r4, 0x0C2925C0; -CHECKREG r5, 0x444EE736; -CHECKREG r6, 0x29B65052; -CHECKREG r7, 0x6E053788; - - -imm32 r0, 0x13245628; -imm32 r1, 0x23256729; -imm32 r2, 0x3326782a; -imm32 r3, 0x43278922; -imm32 r4, 0x56389123; -imm32 r5, 0x67391224; -imm32 r6, 0xa1334527; -imm32 r7, 0xc1334527; -A1 += R0.H * R1.L, A0 += R0.L * R1.L; -R0 = A0.w; -R1 = A1.w; -A1 = R2.H * R3.L, A0 += R2.L * R3.H; -R2 = A0.w; -R3 = A1.w; -A1 = R4.H * R5.L, A0 += R4.H * R5.L; -R4 = A0.w; -R5 = A1.w; -A1 = R6.H * R7.L, A0 += R6.H * R7.H; -R6 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x6F261922; -CHECKREG r1, 0x7D725110; -CHECKREG r2, 0xAE30B1EE; -CHECKREG r3, 0xD0804218; -CHECKREG r4, 0xBA68D1AE; -CHECKREG r5, 0x0C381FC0; -CHECKREG r6, 0xE8EBF200; -CHECKREG r7, 0xCCC89B8A; - - -imm32 r0, 0x01340678; -imm32 r1, 0x02450789; -imm32 r2, 0x0356089a; -imm32 r3, 0x04670912; -imm32 r4, 0x05780123; -imm32 r5, 0x06890234; -imm32 r6, 0x07230567; -imm32 r7, 0x00230567; -A1 -= R0.L * R1.L, A0 = R0.L * R1.L; -R0 = A0.w; -R1 = A1.w; -A1 = R2.L * R3.L, A0 -= R2.L * R3.H; -R2 = A0.w; -R3 = A1.w; -A1 -= R4.L * R5.L, A0 -= R4.H * R5.L; -R4 = A0.w; -R5 = A1.w; -A1 -= R6.L * R7.L, A0 += R6.H * R7.H; -R6 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x00617C70; -CHECKREG r1, 0xCC671F1A; -CHECKREG r2, 0x0015C084; -CHECKREG r3, 0x009C09A8; -CHECKREG r4, 0xFFFDA7C4; -CHECKREG r5, 0x00970770; -CHECKREG r6, 0xFFFF9B56; -CHECKREG r7, 0x005CA88E; - -imm32 r0, 0x00245618; -imm32 r1, 0x01256719; -imm32 r2, 0x0226781a; -imm32 r3, 0x03278912; -imm32 r4, 0x06489113; -imm32 r5, 0x05291214; -imm32 r6, 0x01634517; -imm32 r7, 0x02234517; -A1 += R0.L * R1.H, A0 -= R0.L * R1.L; -R0 = A0.w; -R1 = A1.w; -A1 -= R2.L * R3.H, A0 += R2.L * R3.H; -R2 = A0.w; -R3 = A1.w; -A1 -= R4.L * R5.H, A0 -= R4.H * R5.L; -R4 = A0.w; -R5 = A1.w; -A1 += R6.L * R7.H, A0 -= R6.H * R7.H; -R6 = A0.w; -R7 = A1.w; -CHECKREG r0, 0xBAA77AA6; -CHECKREG r1, 0x0121BB7E; -CHECKREG r2, 0xBD9CAE92; -CHECKREG r3, 0xFE2C8792; -CHECKREG r4, 0xBCB99352; -CHECKREG r5, 0x02A5517C; -CHECKREG r6, 0xBCB3A640; -CHECKREG r7, 0x03CC91C6; - -imm32 r0, 0x10240648; -imm32 r1, 0x25156749; -imm32 r2, 0x3526084a; -imm32 r3, 0x45238942; -imm32 r4, 0x51381143; -imm32 r5, 0x62392244; -imm32 r6, 0xa3333547; -imm32 r7, 0xc4334547; -A1 += R0.H * R1.H, A0 -= R0.L * R1.L; -R0 = A0.w; -R1 = A1.w; -A1 -= R2.H * R3.H, A0 -= R2.L * R3.H; -R2 = A0.w; -R3 = A1.w; -A1 -= R4.H * R5.H, A0 += R4.H * R5.L; -R4 = A0.w; -R5 = A1.w; -A1 += R6.H * R7.H, A0 -= R6.H * R7.H; -R6 = A0.w; -R7 = A1.w; -CHECKREG r0, 0xB7A22130; -CHECKREG r1, 0x08799FAE; -CHECKREG r2, 0xB327F8F4; -CHECKREG r3, 0xEBC49B4A; -CHECKREG r4, 0xC8E5FEB4; -CHECKREG r5, 0xAD71905A; -CHECKREG r6, 0x9D8AE062; -CHECKREG r7, 0xD8CCAEAC; - - -imm32 r0, 0x10245628; -imm32 r1, 0x23056729; -imm32 r2, 0x3320782a; -imm32 r3, 0x43270922; -imm32 r4, 0x56389023; -imm32 r5, 0x67391024; -imm32 r6, 0x21334507; -imm32 r7, 0x11334520; -A1 += R0.H * R1.L, A0 -= R0.L * R1.L; -R0 = A0.w; -R1 = A1.w; -A1 -= R2.H * R3.L, A0 += R2.L * R3.H; -R2 = A0.w; -R3 = A1.w; -A1 -= R4.H * R5.L, A0 -= R4.H * R5.L; -R4 = A0.w; -R5 = A1.w; -A1 += R6.H * R7.L, A0 -= R6.H * R7.H; -R6 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x581B1792; -CHECKREG r1, 0xE5CED234; -CHECKREG r2, 0x9725B05E; -CHECKREG r3, 0xE228FDB4; -CHECKREG r4, 0x8C46709E; -CHECKREG r5, 0xD749BDF4; -CHECKREG r6, 0x87D0704C; -CHECKREG r7, 0xE93788B4; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_iuw32.s b/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_iuw32.s deleted file mode 100644 index 16910ff..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_iuw32.s +++ /dev/null @@ -1,1014 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_a1a0_iuw32/c_dsp32mac_a1a0_iuw32.dsp -// Spec Reference: dsp32mac a1 a0 iuw32 MNOP -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -imm32 r0, 0x00000000; -A0 = 0; -A1 = 0; -ASTAT = r0; - - -// test the (signed integer: no ) I=1 -imm32 r0, 0x22345628; -imm32 r1, 0x23456729; -imm32 r2, 0x3456782a; -imm32 r3, 0x45678922; -imm32 r4, 0x56789123; -imm32 r5, 0x67891224; -imm32 r6, 0xa1234527; -imm32 r7, 0xc1234567; -A1 = R0.L * R7.L, A0 = R0.L * R7.L (IS); -R0 = A0.w; -R7 = A1.w; -A1 = R6.L * R1.L, A0 += R6.L * R1.H (IS); -R6 = A0.w; -R1 = A1.w; -A1 += R2.L * R3.L, A0 = R2.H * R3.L (IS); -R2 = A0.w; -R3 = A1.w; -A1 += R5.L * R4.L, A0 += R5.H * R4.H (IS); -R5 = A0.w; -R4 = A1.w; -CHECKREG r0, 0x175B7218; -CHECKREG r1, 0x1BDDC43F; -CHECKREG r2, 0xE7B2F96C; -CHECKREG r3, 0xE41233D3; -CHECKREG r4, 0xDC3712BF; -CHECKREG r5, 0x0AAB87A4; -CHECKREG r6, 0x20E26A9B; -CHECKREG r7, 0x175B7218; - -imm32 r0, 0x13335678; -imm32 r1, 0x23436789; -imm32 r2, 0x3353789a; -imm32 r3, 0xa3638912; -imm32 r4, 0x53739123; -imm32 r5, 0x63831234; -imm32 r6, 0xa1234567; -imm32 r7, 0xc1234567; -A1 = R2.L * R7.H, A0 += R2.L * R7.L (IS); -R2 = A0.w; -R7 = A1.w; -A1 = R6.L * R1.H, A0 += R6.L * R1.H (IS); -R6 = A0.w; -R1 = A1.w; -A1 += R0.L * R5.H, A0 = R0.H * R5.L (IS); -R0 = A0.w; -R5 = A1.w; -A1 += R4.L * R3.H, A0 = R4.H * R3.H (IS); -R4 = A0.w; -R3 = A1.w; -CHECKREG r0, 0x015D7C5C; -CHECKREG r1, 0x098F3EF5; -CHECKREG r2, 0x2B5D8F9A; -CHECKREG r3, 0x53474FE6; -CHECKREG r4, 0xE1CF7E79; -CHECKREG r5, 0x2B2BE65D; -CHECKREG r6, 0x34ECCE8F; -CHECKREG r7, 0xE262970E; - -imm32 r0, 0x14345678; -imm32 r1, 0x24456789; -imm32 r2, 0x3456789a; -imm32 r3, 0x44678912; -imm32 r4, 0x54789123; -imm32 r5, 0x67891244; -imm32 r6, 0xa1234547; -imm32 r7, 0xc1234547; -A1 += R4.H * R0.L, A0 = R4.L * R0.L (IS); -R4 = A0.w; -R0 = A1.w; -A1 = R3.H * R1.L, A0 += R3.L * R1.H (IS); -R3 = A0.w; -R1 = A1.w; -A1 = R2.H * R6.L, A0 = R2.H * R6.L (IS); -R2 = A0.w; -R6 = A1.w; -A1 += R7.H * R5.L, A0 += R7.H * R5.H (IS); -R7 = A0.w; -R5 = A1.w; -CHECKREG r0, 0x6FCF3826; -CHECKREG r1, 0x1BAA0C1F; -CHECKREG r2, 0x0E29B1DA; -CHECKREG r3, 0xC9B44442; -CHECKREG r4, 0xDA8DCA68; -CHECKREG r5, 0x09AD7526; -CHECKREG r6, 0x0E29B1DA; -CHECKREG r7, 0xF4BD2295; - -imm32 r0, 0x15345678; -imm32 r1, 0x23556789; -imm32 r2, 0x3455789a; -imm32 r3, 0x45675912; -imm32 r4, 0x56789523; -imm32 r5, 0x67891234; -imm32 r6, 0xa1234557; -imm32 r7, 0xc1234565; -A1 += R0.H * R1.H, A0 = R0.L * R1.L (IS); -R0 = A0.w; -R1 = A1.w; -A1 = R5.H * R6.H, A0 = R5.L * R6.H (IS); -R5 = A0.w; -R6 = A1.w; -A1 = R4.H * R3.H, A0 += R4.H * R3.L (IS); -R4 = A0.w; -R3 = A1.w; -A1 = R2.H * R7.H, A0 = R2.H * R7.H (IS); -R2 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x22F88E38; -CHECKREG r1, 0x0C9A9B6A; -CHECKREG r2, 0xF3263C9F; -CHECKREG r3, 0x17712248; -CHECKREG r4, 0x1756FD8C; -CHECKREG r5, 0xF941311C; -CHECKREG r6, 0xD9A250BB; -CHECKREG r7, 0xF3263C9F; - -// test the (unsigned or integer :no ) U=1 -imm32 r0, 0x62345678; -imm32 r1, 0x26456789; -imm32 r2, 0x3466789a; -imm32 r3, 0x45668912; -imm32 r4, 0x56786123; -imm32 r5, 0x67891634; -imm32 r6, 0xa1234567; -imm32 r7, 0xc1234566; -A1 = R0.L * R2.L, A0 = R0.L * R2.L (FU); -R0 = A0.w; -R2 = A1.w; -A1 = R1.L * R3.L, A0 += R1.L * R3.H (FU); -R1 = A0.w; -R3 = A1.w; -A1 += R4.L * R6.L, A0 = R4.H * R6.L (FU); -R4 = A0.w; -R6 = A1.w; -A1 += R5.L * R7.L, A0 += R5.H * R7.H (FU); -R5 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x28BC4430; -CHECKREG r1, 0x44CD71C6; -CHECKREG r2, 0x28BC4430; -CHECKREG r3, 0x376F98A2; -CHECKREG r4, 0x17712248; -CHECKREG r5, 0x658D9303; -CHECKREG r6, 0x51C51CB7; -CHECKREG r7, 0x57C9F96F; - -imm32 r0, 0x12345678; -imm32 r1, 0x73456789; -imm32 r2, 0x8456789a; -imm32 r3, 0x49998912; -imm32 r4, 0x56782123; -imm32 r5, 0x67891234; -imm32 r6, 0xa1234577; -imm32 r7, 0xc1234567; -A1 = R2.L * R3.H, A0 = R2.L * R3.L (FU); -R2 = A0.w; -R3 = A1.w; -A1 = R0.L * R1.H, A0 = R0.L * R1.H (FU); -R0 = A0.w; -R1 = A1.w; -A1 += R4.L * R5.H, A0 = R4.H * R5.L (FU); -R4 = A0.w; -R5 = A1.w; -A1 = R7.L * R6.H, A0 += R7.H * R6.H (FU); -R6 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x26EF3658; -CHECKREG r1, 0x26EF3658; -CHECKREG r2, 0x4092E4D4; -CHECKREG r3, 0x22ABFE0A; -CHECKREG r4, 0x06260060; -CHECKREG r5, 0x34560713; -CHECKREG r6, 0x7FB76B29; -CHECKREG r7, 0x2BAF4415; - -imm32 r0, 0x1234567a; -imm32 r1, 0x2345678a; -imm32 r2, 0x3456a89a; -imm32 r3, 0x4a678912; -imm32 r4, 0xa6789123; -imm32 r5, 0xc7891234; -imm32 r6, 0xa1234567; -imm32 r7, 0xc1234567; -A1 = R5.H * R4.L, A0 = R5.L * R4.L (FU); -R4 = A0.w; -R5 = A1.w; -A1 = R3.H * R2.L, A0 = R3.L * R2.H (FU); -R2 = A0.w; -R3 = A1.w; -A1 = R1.H * R0.L, A0 = R1.H * R0.L (FU); -R0 = A0.w; -R1 = A1.w; -A1 = R7.H * R6.L, A0 = R7.H * R6.H (FU); -R6 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x0BE9FCE2; -CHECKREG r1, 0x0BE9FCE2; -CHECKREG r2, 0x1C05B40C; -CHECKREG r3, 0x310059F6; -CHECKREG r4, 0x0A51F11C; -CHECKREG r5, 0x711FE0BB; -CHECKREG r6, 0x79916AC9; -CHECKREG r7, 0x345C2415; - -imm32 r0, 0xb2345678; -imm32 r1, 0x2b456789; -imm32 r2, 0x34b6789a; -imm32 r3, 0xc56b8912; -imm32 r4, 0x5c78b123; -imm32 r5, 0x67c91b34; -imm32 r6, 0xa12345b7; -imm32 r7, 0xc123456b; -A1 = R6.H * R7.H, A0 = R6.L * R7.L (FU); -R6 = A0.w; -R7 = A1.w; -A1 = R5.H * R4.H, A0 = R5.L * R4.H (FU); -R4 = A0.w; -R5 = A1.w; -A1 = R2.H * R3.H, A0 = R2.H * R3.L (FU); -R2 = A0.w; -R3 = A1.w; -A1 = R0.H * R1.H, A0 = R0.H * R1.H (FU); -R0 = A0.w; -R1 = A1.w; -CHECKREG r0, 0x1E1EC404; -CHECKREG r1, 0x1E1EC404; -CHECKREG r2, 0x1C391ACC; -CHECKREG r3, 0x28A61612; -CHECKREG r4, 0x09D37060; -CHECKREG r5, 0x257CE238; -CHECKREG r6, 0x12E7767D; -CHECKREG r7, 0x79916AC9; - -// Test w32 -imm32 r0, 0x123df178; -imm32 r1, 0x2245e189; -imm32 r2, 0x3256719a; -imm32 r3, 0x42678112; -imm32 r4, 0xa2789123; -imm32 r5, 0x62891134; -imm32 r6, 0xa2b34167; -imm32 r7, 0xc22d4167; -A1 = R0.L * R4.L, A0 += R0.L * R4.L (W32); -R0 = A0.w; -R4 = A1.w; -A1 = R1.L * R5.L, A0 += R1.L * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A1 = R2.L * R6.L, A0 += R2.H * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 = R3.L * R4.L, A0 += R3.H * R4.H (W32); -R3 = A0.w; -R4 = A1.w; -CHECKREG r0, 0x2AB4BAD4; -CHECKREG r1, 0x13410376; -CHECKREG r2, 0x2CF930AA; -CHECKREG r3, 0x33802490; -CHECKREG r4, 0x091C5540; -CHECKREG r5, 0xFBE7D1A8; -CHECKREG r6, 0x3A0B9DEC; -CHECKREG r7, 0xC22D4167; - -imm32 r0, 0x553df344; -imm32 r1, 0x2525e349; -imm32 r2, 0x3252734a; -imm32 r3, 0x42658342; -imm32 r4, 0xa5789343; -imm32 r5, 0x63591344; -imm32 r6, 0xa3b54347; -imm32 r7, 0xc32d4347; -A1 += R0.L * R4.H, A0 = R0.L * R4.L (W32); -R0 = A0.w; -R4 = A1.w; -A1 += R1.L * R5.H, A0 = R1.L * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A1 += R2.L * R6.H, A0 = R2.H * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 += R3.L * R4.H, A0 = R3.H * R4.H (W32); -R3 = A0.w; -R4 = A1.w; -CHECKREG r0, 0x0AD16D98; -CHECKREG r1, 0xE9B67EC2; -CHECKREG r2, 0x1A72D57C; -CHECKREG r3, 0x0965C3AC; -CHECKREG r4, 0x970BD9DE; -CHECKREG r5, 0xFBD48BC2; -CHECKREG r6, 0xA8B3CE66; -CHECKREG r7, 0xC32D4347; - -imm32 r0, 0x163df678; -imm32 r1, 0x2625e689; -imm32 r2, 0x3652769a; -imm32 r3, 0x46628612; -imm32 r4, 0xa6789623; -imm32 r5, 0x63691634; -imm32 r6, 0xa3634367; -imm32 r7, 0xc3264667; -A1 += R0.H * R4.L, A0 = R0.L * R4.L (W32); -R0 = A0.w; -R4 = A1.w; -A1 = R1.H * R5.L, A0 += R1.L * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A1 += R2.H * R6.L, A0 = R2.H * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 += R3.H * R4.L, A0 += R3.H * R4.H (W32); -R3 = A0.w; -R4 = A1.w; -CHECKREG r0, 0x07E204D0; -CHECKREG r1, 0xF41B1732; -CHECKREG r2, 0x1C9AA1FC; -CHECKREG r3, 0xD8C785D8; -CHECKREG r4, 0x5DCEA034; -CHECKREG r5, 0x069DDB08; -CHECKREG r6, 0x23387D04; -CHECKREG r7, 0xC3264667; - -imm32 r0, 0x123df378; -imm32 r1, 0x2225e389; -imm32 r2, 0x3252739a; -imm32 r3, 0x42628312; -imm32 r4, 0xa3789323; -imm32 r5, 0x63891334; -imm32 r6, 0xa3b34367; -imm32 r7, 0xc32d4367; -A1 += R0.H * R4.H, A0 = R0.L * R4.L (W32); -R0 = A0.w; -R4 = A1.w; -A1 = R1.H * R5.H, A0 = R1.L * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A1 += R2.H * R6.H, A0 = R2.H * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 = R3.H * R4.H, A0 = R3.H * R4.H (W32); -R3 = A0.w; -R4 = A1.w; -CHECKREG r0, 0x0AA862D0; -CHECKREG r1, 0xE9DD7EA2; -CHECKREG r2, 0x1A7F69FC; -CHECKREG r3, 0x29CFB5BC; -CHECKREG r4, 0x29CFB5BC; -CHECKREG r5, 0x1A8D299A; -CHECKREG r6, 0xF643F446; -CHECKREG r7, 0xC32D4367; - -imm32 r0, 0x123df678; -imm32 r1, 0x2345e789; -imm32 r2, 0x34567b9a; -imm32 r3, 0x45678c12; -imm32 r4, 0xa6789123; -imm32 r5, 0x6c891234; -imm32 r6, 0xa1b34567; -imm32 r7, 0xc12d4567; -A1 = R0.H * R4.L, A0 = R0.H * R4.L (W32); -R0 = A0.w; -R4 = A1.w; -A1 = R1.H * R5.L, A0 = R1.H * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A1 = R2.H * R6.H, A0 = R2.L * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 = R3.H * R4.H, A0 = R3.L * R4.H (W32); -R3 = A0.w; -R4 = A1.w; -CHECKREG r0, 0xF03416AE; -CHECKREG r1, 0x1DE7F7DA; -CHECKREG r2, 0x430479EC; -CHECKREG r3, 0x0E4EA750; -CHECKREG r4, 0xF76F51D8; -CHECKREG r5, 0x05040808; -CHECKREG r6, 0xD9715C44; -CHECKREG r7, 0xC12D4567; - -// MNOP & w32 -imm32 r0, 0x623df17a; -imm32 r1, 0x7245e18b; -imm32 r2, 0x8256719a; -imm32 r3, 0x92678112; -imm32 r4, 0xa2789123; -imm32 r5, 0xb2891134; -imm32 r6, 0xc2b34167; -imm32 r7, 0xd22d4167; -A0 += R0.L * R4.L (W32); -R0 = A0.w; -R4 = A1.w; -A0 = R1.L * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A0 += R2.H * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A0 = R3.H * R7.H (W32); -R3 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x1AE2E2AC; -CHECKREG r1, 0x126EB2C6; -CHECKREG r2, 0xD2393FFA; -CHECKREG r3, 0x273C7436; -CHECKREG r4, 0xF76F51D8; -CHECKREG r5, 0xF76F51D8; -CHECKREG r6, 0xF76F51D8; -CHECKREG r7, 0xF76F51D8; - -imm32 r0, 0xa23df17a; -imm32 r1, 0x7b45e18b; -imm32 r2, 0x82c6719a; -imm32 r3, 0x126d8112; -imm32 r4, 0xc278e123; -imm32 r5, 0xb2491f34; -imm32 r6, 0x89b54167; -imm32 r7, 0xd25d6767; -A1 += R0.L * R4.L (W32); -R0 = A0.w; -R4 = A1.w; -A1 = R1.L * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A1 += R2.H * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 = R3.H * R7.H (W32); -R3 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x273C7436; -CHECKREG r1, 0x273C7436; -CHECKREG r2, 0x273C7436; -CHECKREG r3, 0x273C7436; -CHECKREG r4, 0xFAEFCD34; -CHECKREG r5, 0x127DED46; -CHECKREG r6, 0xD281B49A; -CHECKREG r7, 0xF96E3732; - -// test MM=1(Mix mode), MAC1 executes a mixed mode multiplication: (one input is -// signed, the other input is unsigned -imm32 r0, 0x22345628; -imm32 r1, 0x23456729; -imm32 r2, 0x3456782a; -imm32 r3, 0x45678922; -imm32 r4, 0x56789123; -imm32 r5, 0x67891224; -imm32 r6, 0xa1234527; -imm32 r7, 0xc1234567; -A1 += R0.L * R7.L (M), A0 = R0.L * R7.L (IS); -R0 = A0.w; -R7 = A1.w; -A1 = R6.L * R1.L (M), A0 += R6.L * R1.H (IS); -R6 = A0.w; -R1 = A1.w; -A1 = R2.L * R3.L (M), A0 = R2.H * R3.L (IS); -R2 = A0.w; -R3 = A1.w; -A1 += R5.L * R4.L (M), A0 += R5.H * R4.H (IS); -R5 = A0.w; -R4 = A1.w; -CHECKREG r0, 0x175B7218; -CHECKREG r1, 0x1BDDC43F; -CHECKREG r2, 0xE7B2F96C; -CHECKREG r3, 0x405E6F94; -CHECKREG r4, 0x4AA74E80; -CHECKREG r5, 0x0AAB87A4; -CHECKREG r6, 0x20E26A9B; -CHECKREG r7, 0x10C9A94A; - -imm32 r0, 0x13335678; -imm32 r1, 0x23436789; -imm32 r2, 0x3353789a; -imm32 r3, 0xa3638912; -imm32 r4, 0x53739123; -imm32 r5, 0x63831234; -imm32 r6, 0xa1234567; -imm32 r7, 0xc1234567; -A1 += R2.L * R7.H (M), A0 = R2.L * R7.L (IS); -R2 = A0.w; -R7 = A1.w; -A1 = R6.L * R1.H (M), A0 = R6.L * R1.H (IS); -R6 = A0.w; -R1 = A1.w; -A1 += R0.L * R5.H (M), A0 = R0.H * R5.L (IS); -R0 = A0.w; -R5 = A1.w; -A1 = R4.L * R3.H (M), A0 += R4.H * R3.H (IS); -R4 = A0.w; -R3 = A1.w; -CHECKREG r0, 0x015D7C5C; -CHECKREG r1, 0x098F3EF5; -CHECKREG r2, 0x20B207F6; -CHECKREG r3, 0xB93E6989; -CHECKREG r4, 0xE32CFAD5; -CHECKREG r5, 0x2B2BE65D; -CHECKREG r6, 0x098F3EF5; -CHECKREG r7, 0xA5A3E58E; - -imm32 r0, 0x14345678; -imm32 r1, 0x24456789; -imm32 r2, 0x3456789a; -imm32 r3, 0x44678912; -imm32 r4, 0x54789123; -imm32 r5, 0x67891244; -imm32 r6, 0xa1234547; -imm32 r7, 0xc1234547; -A1 = R4.H * R0.L (M), A0 = R4.L * R0.L (IS); -R4 = A0.w; -R0 = A1.w; -A1 = R3.H * R1.L (M), A0 = R3.L * R1.H (IS); -R3 = A0.w; -R1 = A1.w; -A1 = R2.H * R6.L (M), A0 = R2.H * R6.L (IS); -R2 = A0.w; -R6 = A1.w; -A1 = R7.H * R5.L (M), A0 = R7.H * R5.H (IS); -R7 = A0.w; -R5 = A1.w; -CHECKREG r0, 0x1C87E840; -CHECKREG r1, 0x1BAA0C1F; -CHECKREG r2, 0x0E29B1DA; -CHECKREG r3, 0xEF2679DA; -CHECKREG r4, 0xDA8DCA68; -CHECKREG r5, 0xFB83C34C; -CHECKREG r6, 0x0E29B1DA; -CHECKREG r7, 0xE69370BB; - -imm32 r0, 0x15345678; -imm32 r1, 0x23556789; -imm32 r2, 0x3455789a; -imm32 r3, 0x45675912; -imm32 r4, 0x56789523; -imm32 r5, 0x67891234; -imm32 r6, 0xa1234557; -imm32 r7, 0xc1234565; -A1 = R0.H * R1.H (M), A0 = R0.L * R1.L (IS); -R0 = A0.w; -R1 = A1.w; -A1 = R5.H * R6.H (M), A0 = R5.L * R6.H (IS); -R5 = A0.w; -R6 = A1.w; -A1 += R4.H * R3.H (M), A0 = R4.H * R3.L (IS); -R4 = A0.w; -R3 = A1.w; -A1 += R2.H * R7.H (M), A0 = R2.H * R7.H (IS); -R2 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x22F88E38; -CHECKREG r1, 0x02ED2644; -CHECKREG r2, 0xF3263C9F; -CHECKREG r3, 0x589C7303; -CHECKREG r4, 0x1E15CC70; -CHECKREG r5, 0xF941311C; -CHECKREG r6, 0x412B50BB; -CHECKREG r7, 0x8017AFA2; - -// test the (unsigned or integer :no ) U=1 -imm32 r0, 0x62345678; -imm32 r1, 0x26456789; -imm32 r2, 0x3466789a; -imm32 r3, 0x45668912; -imm32 r4, 0x56786123; -imm32 r5, 0x67891634; -imm32 r6, 0xa1234567; -imm32 r7, 0xc1234566; -A1 = R0.L * R2.L (M), A0 = R0.L * R2.L (FU); -R0 = A0.w; -R2 = A1.w; -A1 += R1.L * R3.L (M), A0 = R1.L * R3.H (FU); -R1 = A0.w; -R3 = A1.w; -A1 = R4.L * R6.L (M), A0 = R4.H * R6.L (FU); -R4 = A0.w; -R6 = A1.w; -A1 += R5.L * R7.L (M), A0 = R5.H * R7.H (FU); -R5 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x28BC4430; -CHECKREG r1, 0x1C112D96; -CHECKREG r2, 0x28BC4430; -CHECKREG r3, 0x602BDCD2; -CHECKREG r4, 0x17712248; -CHECKREG r5, 0x4E1C70BB; -CHECKREG r6, 0x1A558415; -CHECKREG r7, 0x205A60CD; - -imm32 r0, 0x12345678; -imm32 r1, 0x73456789; -imm32 r2, 0x8456789a; -imm32 r3, 0x49998912; -imm32 r4, 0x56782123; -imm32 r5, 0x67891234; -imm32 r6, 0xa1234577; -imm32 r7, 0xc1234567; -A1 = R2.L * R3.H (M), A0 = R2.L * R3.L (FU); -R2 = A0.w; -R3 = A1.w; -A1 = R0.L * R1.H (M), A0 = R0.L * R1.H (FU); -R0 = A0.w; -R1 = A1.w; -A1 = R4.L * R5.H (M), A0 = R4.H * R5.L (FU); -R4 = A0.w; -R5 = A1.w; -A1 = R7.L * R6.H (M), A0 = R7.H * R6.H (FU); -R6 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x26EF3658; -CHECKREG r1, 0x26EF3658; -CHECKREG r2, 0x4092E4D4; -CHECKREG r3, 0x22ABFE0A; -CHECKREG r4, 0x06260060; -CHECKREG r5, 0x0D66D0BB; -CHECKREG r6, 0x79916AC9; -CHECKREG r7, 0x2BAF4415; - -imm32 r0, 0x1234567a; -imm32 r1, 0x2345678a; -imm32 r2, 0x3456a89a; -imm32 r3, 0x4a678912; -imm32 r4, 0xa6789123; -imm32 r5, 0xc7891234; -imm32 r6, 0xa1234567; -imm32 r7, 0xc1234567; -A1 = R5.H * R4.L (M), A0 += R5.L * R4.L (FU); -R4 = A0.w; -R5 = A1.w; -A1 = R3.H * R2.L (M), A0 = R3.L * R2.H (FU); -R2 = A0.w; -R3 = A1.w; -A1 = R1.H * R0.L (M), A0 += R1.H * R0.L (FU); -R0 = A0.w; -R1 = A1.w; -A1 = R7.H * R6.L (M), A0 = R7.H * R6.H (FU); -R6 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x27EFB0EE; -CHECKREG r1, 0x0BE9FCE2; -CHECKREG r2, 0x1C05B40C; -CHECKREG r3, 0x310059F6; -CHECKREG r4, 0x83E35BE5; -CHECKREG r5, 0xDFFCE0BB; -CHECKREG r6, 0x79916AC9; -CHECKREG r7, 0xEEF52415; - -imm32 r0, 0xb2345678; -imm32 r1, 0x2b456789; -imm32 r2, 0x34b6789a; -imm32 r3, 0xc56b8912; -imm32 r4, 0x5c78b123; -imm32 r5, 0x67c91b34; -imm32 r6, 0xa12345b7; -imm32 r7, 0xc123456b; -A1 += R6.H * R7.H (M), A0 = R6.L * R7.L (FU); -R6 = A0.w; -R7 = A1.w; -A1 += R5.H * R4.H (M), A0 = R5.L * R4.H (FU); -R4 = A0.w; -R5 = A1.w; -A1 = R2.H * R3.H (M), A0 += R2.H * R3.L (FU); -R2 = A0.w; -R3 = A1.w; -A1 = R0.H * R1.H (M), A0 += R0.H * R1.H (FU); -R0 = A0.w; -R1 = A1.w; -CHECKREG r0, 0x442B4F30; -CHECKREG r1, 0xF2D9C404; -CHECKREG r2, 0x260C8B2C; -CHECKREG r3, 0x28A61612; -CHECKREG r4, 0x09D37060; -CHECKREG r5, 0xCCE07116; -CHECKREG r6, 0x12E7767D; -CHECKREG r7, 0xA7638EDE; - -// Test w32 -imm32 r0, 0x123df178; -imm32 r1, 0x2245e189; -imm32 r2, 0x3256719a; -imm32 r3, 0x42678112; -imm32 r4, 0xa2789123; -imm32 r5, 0x62891134; -imm32 r6, 0xa2b34167; -imm32 r7, 0xc22d4167; -A1 = R0.L * R7.L (M), A0 = R0.L * R7.L (W32); -R0 = A0.w; -R7 = A1.w; -A1 += R1.L * R5.L (M), A0 = R1.L * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A1 = R2.L * R6.L (M), A0 = R2.H * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 += R3.L * R4.L (M), A0 = R3.H * R4.H (W32); -R3 = A0.w; -R4 = A1.w; -CHECKREG r0, 0xF8933E90; -CHECKREG r1, 0xE88C48A2; -CHECKREG r2, 0x19B82D34; -CHECKREG r3, 0xCF7A9C90; -CHECKREG r4, 0xD50FA66C; -CHECKREG r5, 0xFA3D881C; -CHECKREG r6, 0x1D05CEF6; -CHECKREG r7, 0xFC499F48; - -imm32 r0, 0x553df344; -imm32 r1, 0x2525e349; -imm32 r2, 0x3252734a; -imm32 r3, 0x42658342; -imm32 r4, 0xa5789343; -imm32 r5, 0x63591344; -imm32 r6, 0xa3b54347; -imm32 r7, 0xc32d4347; -A1 = R0.L * R7.H (M), A0 = R0.L * R7.L (W32); -R0 = A0.w; -R7 = A1.w; -A1 = R1.L * R5.H (M), A0 += R1.L * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A1 = R2.L * R6.H (M), A0 = R2.H * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 = R3.L * R4.H (M), A0 += R3.H * R4.H (W32); -R3 = A0.w; -R4 = A1.w; -CHECKREG r0, 0xF94E87B8; -CHECKREG r1, 0xE305067A; -CHECKREG r2, 0x1A72D57C; -CHECKREG r3, 0xEB7D462C; -CHECKREG r4, 0xAF5F10F0; -CHECKREG r5, 0xF4DB3F61; -CHECKREG r6, 0x49B9A152; -CHECKREG r7, 0xF64A8EF4; - -imm32 r0, 0x163df678; -imm32 r1, 0x2625e689; -imm32 r2, 0x3652769a; -imm32 r3, 0x46628612; -imm32 r4, 0xa6789623; -imm32 r5, 0x63691634; -imm32 r6, 0xa3634367; -imm32 r7, 0xc3264667; -A1 = R0.H * R7.L (M), A0 = R0.L * R7.L (W32); -R0 = A0.w; -R7 = A1.w; -A1 = R1.H * R5.L (M), A0 = R1.L * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A1 += R2.H * R6.L (M), A0 = R2.H * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 = R3.H * R4.L (M), A0 = R3.H * R4.H (W32); -R3 = A0.w; -R4 = A1.w; -CHECKREG r0, 0xFAC1F490; -CHECKREG r1, 0xEC391262; -CHECKREG r2, 0x1C9AA1FC; -CHECKREG r3, 0xCEC513E0; -CHECKREG r4, 0x29470B66; -CHECKREG r5, 0x034EED84; -CHECKREG r6, 0x119C3E82; -CHECKREG r7, 0x061DA08B; - -imm32 r0, 0x123df378; -imm32 r1, 0x2225e389; -imm32 r2, 0x3252739a; -imm32 r3, 0x42628312; -imm32 r4, 0xa3789323; -imm32 r5, 0x63891334; -imm32 r6, 0xa3b34367; -imm32 r7, 0xc32d4367; -A1 = R0.H * R7.H (M), A0 = R0.L * R7.L (W32); -R0 = A0.w; -R7 = A1.w; -A1 = R1.H * R5.H (M), A0 = R1.L * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A1 += R2.H * R6.H (M), A0 += R2.H * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 += R3.H * R4.H (M), A0 += R3.H * R4.H (W32); -R3 = A0.w; -R4 = A1.w; -CHECKREG r0, 0xF966BA90; -CHECKREG r1, 0xE9DD7EA2; -CHECKREG r2, 0x045CE89E; -CHECKREG r3, 0xD45FF07E; -CHECKREG r4, 0x57D77E13; -CHECKREG r5, 0x0D4694CD; -CHECKREG r6, 0x2D73FA23; -CHECKREG r7, 0x0DE7ABB9; - -imm32 r0, 0x123df678; -imm32 r1, 0x2345e789; -imm32 r2, 0x34567b9a; -imm32 r3, 0x45678c12; -imm32 r4, 0xa6789123; -imm32 r5, 0x6c891234; -imm32 r6, 0xa1b34567; -imm32 r7, 0xc12d4567; -A1 = R0.H * R4.L (M), A0 = R0.H * R4.L (W32); -R0 = A0.w; -R4 = A1.w; -A1 = R1.H * R5.L (M), A0 = R1.H * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A1 = R2.H * R6.H (M), A0 = R2.L * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 = R3.H * R4.H (M), A0 = R3.L * R4.H (W32); -R3 = A0.w; -R4 = A1.w; -CHECKREG r0, 0xF03416AE; -CHECKREG r1, 0x1DE7F7DA; -CHECKREG r2, 0x430479EC; -CHECKREG r3, 0xF6A29C3C; -CHECKREG r4, 0x02CD9C01; -CHECKREG r5, 0x02820404; -CHECKREG r6, 0x210EAE22; -CHECKREG r7, 0xC12D4567; - -// MNOP & w32 -imm32 r0, 0x623df17a; -imm32 r1, 0x7245e18b; -imm32 r2, 0x8256719a; -imm32 r3, 0x92678112; -imm32 r4, 0xa2789123; -imm32 r5, 0xb2891134; -imm32 r6, 0xc2b34167; -imm32 r7, 0xd22d4167; -A0 = R0.L * R4.L (W32); -R0 = A0.w; -R4 = A1.w; -A0 += R1.L * R5.H (W32); -R1 = A0.w; -R5 = A1.w; -A0 = R2.H * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A0 += R3.H * R7.H (W32); -R3 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x0C943B5C; -CHECKREG r1, 0x1F02EE22; -CHECKREG r2, 0xBFCA8D34; -CHECKREG r3, 0xE707016A; -CHECKREG r4, 0x02CD9C01; -CHECKREG r5, 0x02CD9C01; -CHECKREG r6, 0x02CD9C01; -CHECKREG r7, 0x02CD9C01; - -imm32 r0, 0xa23df17a; -imm32 r1, 0x7b45e18b; -imm32 r2, 0x82c6719a; -imm32 r3, 0x126d8112; -imm32 r4, 0xc278e123; -imm32 r5, 0xb2491f34; -imm32 r6, 0x89b54167; -imm32 r7, 0xd25d6767; -A1 += R0.L * R4.L (M,W32); -R0 = A0.w; -R4 = A1.w; -A1 = R1.L * R5.H (M,W32); -R1 = A0.w; -R5 = A1.w; -A1 += R2.H * R6.L (M,W32); -R2 = A0.w; -R6 = A1.w; -A1 = R3.H * R7.H (M,W32); -R3 = A0.w; -R7 = A1.w; -CHECKREG r0, 0xE707016A; -CHECKREG r1, 0xE707016A; -CHECKREG r2, 0xE707016A; -CHECKREG r3, 0xE707016A; -CHECKREG r4, 0xF607D9AF; -CHECKREG r5, 0xEAC9F6A3; -CHECKREG r6, 0xCACBDA4D; -CHECKREG r7, 0x0F241B99; - -imm32 r0, 0x123df678; -imm32 r1, 0x2345e789; -imm32 r2, 0x34567b9a; -imm32 r3, 0x45678c12; -imm32 r4, 0xa6789123; -imm32 r5, 0x6c891234; -imm32 r6, 0xa1b34567; -imm32 r7, 0xc12d4567; -A1 -= R0.H * R4.L (M), A0 += R0.H * R4.L (IS); -R0 = A0.w; -R4 = A1.w; -A1 -= R1.H * R5.L (M), A0 -= R1.H * R5.H (FU); -R1 = A0.w; -R5 = A1.w; -A1 += R2.H * R6.H (M), A0 -= R2.L * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 -= R3.H * R4.H (M), A0 -= R3.L * R4.H (W32); -R3 = A0.w; -R4 = A1.w; -CHECKREG r0, 0xDF210CC1; -CHECKREG r1, 0xD02D10D4; -CHECKREG r2, 0x8D2896E8; -CHECKREG r3, 0x9181B214; -CHECKREG r4, 0x220C8AE5; -CHECKREG r5, 0x024B0C3E; -CHECKREG r6, 0x2359BA60; -CHECKREG r7, 0xC12D4567; - -imm32 r0, 0x123df678; -imm32 r1, 0x2345e789; -imm32 r2, 0x34567b9a; -imm32 r3, 0x45678c12; -imm32 r4, 0xa6789123; -imm32 r5, 0x6c891234; -imm32 r6, 0xa1b34567; -imm32 r7, 0xc12d4567; -A1 -= R0.H * R4.L (M), A0 = R0.H * R4.L (IS); -R0 = A0.w; -R4 = A1.w; -A1 -= R1.H * R5.L (M), A0 = R1.H * R5.H (FU); -R1 = A0.w; -R5 = A1.w; -A1 -= R2.H * R6.H (M), A0 = R2.L * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A1 -= R3.H * R4.H (M), A0 = R3.L * R4.H (W32); -R3 = A0.w; -R4 = A1.w; -CHECKREG r0, 0xF81A0B57; -CHECKREG r1, 0x0EF3FBED; -CHECKREG r2, 0x430479EC; -CHECKREG r3, 0xEA874D74; -CHECKREG r4, 0xEDB77A95; -CHECKREG r5, 0x15337B8A; -CHECKREG r6, 0xF424CD68; -CHECKREG r7, 0xC12D4567; - -// MNOP & w32 -imm32 r0, 0x623df17a; -imm32 r1, 0x7245e18b; -imm32 r2, 0x8256719a; -imm32 r3, 0x92678112; -imm32 r4, 0xa2789123; -imm32 r5, 0xb2891134; -imm32 r6, 0xc2b34167; -imm32 r7, 0xd22d4167; -A0 -= R0.L * R4.L (IS); -R0 = A0.w; -R4 = A1.w; -A0 -= R1.L * R5.H (FU); -R1 = A0.w; -R5 = A1.w; -A0 -= R2.H * R6.L (W32); -R2 = A0.w; -R6 = A1.w; -A0 -= R3.H * R7.H (W32); -R3 = A0.w; -R7 = A1.w; -CHECKREG r0, 0xE43D2FC6; -CHECKREG r1, 0x46F1D663; -CHECKREG r2, 0x8727492F; -CHECKREG r3, 0x80000000; -CHECKREG r4, 0xEDB77A95; -CHECKREG r5, 0xEDB77A95; -CHECKREG r6, 0xEDB77A95; -CHECKREG r7, 0xEDB77A95; - -imm32 r0, 0xa23df17a; -imm32 r1, 0x7b45e18b; -imm32 r2, 0x82c6719a; -imm32 r3, 0x126d8112; -imm32 r4, 0xc278e123; -imm32 r5, 0xb2491f34; -imm32 r6, 0x89b54167; -imm32 r7, 0xd25d6767; -A1 -= R0.L * R4.L (M,IS); -R0 = A0.w; -R4 = A1.w; -A1 -= R1.L * R5.H (M,FU); -R1 = A0.w; -R5 = A1.w; -A1 -= R2.H * R6.L (M,W32); -R2 = A0.w; -R6 = A1.w; -A1 -= R3.H * R7.H (M,FU); -R3 = A0.w; -R7 = A1.w; -CHECKREG r0, 0x80000000; -CHECKREG r1, 0x80000000; -CHECKREG r2, 0x80000000; -CHECKREG r3, 0x80000000; -CHECKREG r4, 0xFA7D3CE7; -CHECKREG r5, 0x0FB34644; -CHECKREG r6, 0x2FB1629A; -CHECKREG r7, 0x208D4701; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_m.s deleted file mode 100644 index 69d54d3..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_m.s +++ /dev/null @@ -1,340 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_a1a0_m/c_dsp32mac_a1a0_m.dsp -// Spec Reference: dsp32mac a1 a0 m MNOP -# mach: bfin - -.include "testutils.inc" - start - - - INIT_R_REGS 0; - - - imm32 r0, 0x00000000; - A0 = 0; - A1 = 0; - ASTAT = r0; - -// test the MNOP default (signed fraction : left ) rounding U=0 I=0 T=0 w32=1 - imm32 r0, 0x123c5678; - imm32 r1, 0x2345c789; - imm32 r2, 0x34567c9a; - imm32 r3, 0x456789c2; - imm32 r4, 0xc678912c; - imm32 r5, 0x6c891234; - imm32 r6, 0xa1c34567; - imm32 r7, 0xc12c4567; - - A0 = 0; - A1 = 0; - - A1 = R0.L * R1.L (M); - R0 = A0.w; - R1 = A1.w; - A0 += R2.H * R3.H; - R2 = A0.w; - R3 = A1.w; - A1 += R4.L * R5.H; - R4 = A0.w; - R5 = A1.w; - A0 += R6.L * R7.H; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x43658E38; - CHECKREG r2, 0x1C607934; - CHECKREG r3, 0x43658E38; - CHECKREG r4, 0x1C607934; - CHECKREG r5, 0xE56C0F50; - CHECKREG r6, 0xFA4FA29C; - CHECKREG r7, 0xE56C0F50; - - imm32 r0, 0xd2345678; - imm32 r1, 0x2d456789; - imm32 r2, 0x34d6789a; - imm32 r3, 0x456d8912; - imm32 r4, 0x5678d123; - imm32 r5, 0x67891d34; - imm32 r6, 0xa12345d7; - imm32 r7, 0xc123456d; - A0 += R6.H * R7.L; - R6 = A0.w; - R7 = A1.w; - A1 += R4.L * R5.H; - R4 = A0.w; - R5 = A1.w; - A0 += R2.L * R3.L; - R2 = A0.w; - R3 = A1.w; - A1 += R0.H * R1.L; - R0 = A0.w; - R1 = A1.w; - CHECKREG r0, 0x56CD8212; - CHECKREG r1, 0x9A78E46E; - CHECKREG r2, 0x56CD8212; - CHECKREG r3, 0xBF8410C6; - CHECKREG r4, 0xC6DBB86A; - CHECKREG r5, 0xBF8410C6; - CHECKREG r6, 0xC6DBB86A; - CHECKREG r7, 0xE56C0F50; - -// test MM=1(Mix mode), MAC1 executes a mixed mode multiplication: (one input is -// signed, the other input is unsigned - imm32 r0, 0x12345678; - imm32 r1, 0x33456789; - imm32 r2, 0x5556789a; - imm32 r3, 0x75678912; - imm32 r4, 0x86789123; - imm32 r5, 0xa7891234; - imm32 r6, 0xc1234567; - imm32 r7, 0xf1234567; - A1 += R0.L * R1.L (M), A0 = R0.L * R1.L; - R0 = A0.w; - R1 = A1.w; - A1 = R2.L * R3.L (M), A0 += R2.L * R3.H; - R2 = A0.w; - R3 = A1.w; - A1 += R4.L * R5.L (M), A0 = R4.H * R5.L; - R4 = A0.w; - R5 = A1.w; - A1 = R6.L * R7.L (M), A0 = R6.H * R7.H; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x45F11C70; - CHECKREG r1, 0xBD7172A6; - CHECKREG r2, 0xB48EEC5C; - CHECKREG r3, 0x4092E4D4; - CHECKREG r4, 0xEEB780C0; - CHECKREG r5, 0x38B0D5F0; - CHECKREG r6, 0x074CB592; - CHECKREG r7, 0x12D0AF71; - - imm32 r0, 0x12245618; - imm32 r1, 0x23256719; - imm32 r2, 0x3426781a; - imm32 r3, 0x45278912; - imm32 r4, 0x56289113; - imm32 r5, 0x67291214; - imm32 r6, 0xa1234517; - imm32 r7, 0xc1234517; - A1 += R0.L * R1.H (M), A0 = R0.L * R1.L; - R0 = A0.w; - R1 = A1.w; - A1 += R2.L * R3.H (M), A0 = R2.L * R3.H; - R2 = A0.w; - R3 = A1.w; - A1 += R4.L * R5.H (M), A0 = R4.H * R5.L; - R4 = A0.w; - R5 = A1.w; - A1 += R6.L * R7.H (M), A0 += R6.H * R7.H; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x455820B0; - CHECKREG r1, 0x1EA268E9; - CHECKREG r2, 0x40E29BEC; - CHECKREG r3, 0x3F13B6DF; - CHECKREG r4, 0x0C2B1640; - CHECKREG r5, 0x126097EA; - CHECKREG r6, 0x3AC1EBD2; - CHECKREG r7, 0x4680610F; - - imm32 r0, 0x15245648; - imm32 r1, 0x25256749; - imm32 r2, 0x3526784a; - imm32 r3, 0x45278942; - imm32 r4, 0x55389143; - imm32 r5, 0x65391244; - imm32 r6, 0xa5334547; - imm32 r7, 0xc5334547; - A1 = R0.H * R1.H (M), A0 = R0.L * R1.L; - R0 = A0.w; - R1 = A1.w; - A1 += R2.H * R3.H (M), A0 += R2.L * R3.H; - R2 = A0.w; - R3 = A1.w; - A1 = R4.H * R5.H (M), A0 = R4.H * R5.L; - R4 = A0.w; - R5 = A1.w; - A1 = R6.H * R7.H (M), A0 = R6.H * R7.H; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x459F2510; - CHECKREG r1, 0x03114234; - CHECKREG r2, 0x869BAF9C; - CHECKREG r3, 0x116C98FE; - CHECKREG r4, 0x0C2925C0; - CHECKREG r5, 0x21B21178; - CHECKREG r6, 0x29B65052; - CHECKREG r7, 0xBA0E2829; - - imm32 r0, 0x13245628; - imm32 r1, 0x23256729; - imm32 r2, 0x3326782a; - imm32 r3, 0x43278922; - imm32 r4, 0x56389123; - imm32 r5, 0x67391224; - imm32 r6, 0xa1334527; - imm32 r7, 0xc1334527; - A1 = R0.H * R1.L (M), A0 = R0.L * R1.L; - R0 = A0.w; - R1 = A1.w; - A1 += R2.H * R3.L (M), A0 = R2.L * R3.H; - R2 = A0.w; - R3 = A1.w; - A1 = R4.H * R5.L (M), A0 = R4.H * R5.L; - R4 = A0.w; - R5 = A1.w; - A1 += R6.H * R7.L (M), A0 = R6.H * R7.H; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x456FC8D0; - CHECKREG r1, 0x07B68CC4; - CHECKREG r2, 0x3F0A98CC; - CHECKREG r3, 0x231CADD0; - CHECKREG r4, 0x0C381FC0; - CHECKREG r5, 0x061C0FE0; - CHECKREG r6, 0x2E832052; - CHECKREG r7, 0xEC805DA5; - -// test the MNOP default (signed fraction : left ) rounding U=0 I=0 T=0 w32=1 - imm32 r0, 0x123c5678; - imm32 r1, 0x2345c789; - imm32 r2, 0x34567c9a; - imm32 r3, 0x456789c2; - imm32 r4, 0xc678912c; - imm32 r5, 0x6c891234; - imm32 r6, 0xa1c34567; - imm32 r7, 0xc12c4567; - - A0 = 0; - A1 = 0; - - A1 += R0.L * R1.L (M); - R0 = A0.w; - R1 = A1.w; - A0 += R2.H * R3.H; - R2 = A0.w; - R3 = A1.w; - A1 = R4.L * R5.H (M); - R4 = A0.w; - R5 = A1.w; - A0 += R6.L * R7.H; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x43658E38; - CHECKREG r2, 0x1C607934; - CHECKREG r3, 0x43658E38; - CHECKREG r4, 0x1C607934; - CHECKREG r5, 0xD103408C; - CHECKREG r6, 0xFA4FA29C; - CHECKREG r7, 0xD103408C; - - imm32 r0, 0xd2345678; - imm32 r1, 0x2d456789; - imm32 r2, 0x34d6789a; - imm32 r3, 0x456d8912; - imm32 r4, 0x5678d123; - imm32 r5, 0x67891d34; - imm32 r6, 0xa12345d7; - imm32 r7, 0xc123456d; - A0 = R6.H * R7.L; - R6 = A0.w; - R7 = A1.w; - A1 = R4.L * R5.H (M); - R4 = A0.w; - R5 = A1.w; - A0 = R2.L * R3.L; - R2 = A0.w; - R3 = A1.w; - A1 += R0.H * R1.L (M); - R0 = A0.w; - R1 = A1.w; - CHECKREG r0, 0x8FF1C9A8; - CHECKREG r1, 0xDA866A8F; - CHECKREG r2, 0x8FF1C9A8; - CHECKREG r3, 0xED0C00BB; - CHECKREG r4, 0xCC8C15CE; - CHECKREG r5, 0xED0C00BB; - CHECKREG r6, 0xCC8C15CE; - CHECKREG r7, 0xD103408C; - - imm32 r0, 0x123c5678; - imm32 r1, 0x2345c789; - imm32 r2, 0x34567c9a; - imm32 r3, 0x456789c2; - imm32 r4, 0xc678912c; - imm32 r5, 0x6c891234; - imm32 r6, 0xa1c34567; - imm32 r7, 0xc12c4567; - - A0 = 0; - A1 = 0; - - A1 -= R0.L * R1.L (M); - R0 = A0.w; - R1 = A1.w; - A0 -= R2.H * R3.H; - R2 = A0.w; - R3 = A1.w; - A1 -= R4.L * R5.H (M); - R4 = A0.w; - R5 = A1.w; - A0 -= R6.L * R7.H; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0xBC9A71C8; - CHECKREG r2, 0xE39F86CC; - CHECKREG r3, 0xBC9A71C8; - CHECKREG r4, 0xE39F86CC; - CHECKREG r5, 0xEB97313C; - CHECKREG r6, 0x05B05D64; - CHECKREG r7, 0xEB97313C; - - imm32 r0, 0xd2345678; - imm32 r1, 0x2d456789; - imm32 r2, 0x34d6789a; - imm32 r3, 0x456d8912; - imm32 r4, 0x5678d123; - imm32 r5, 0x67891d34; - imm32 r6, 0xa12345d7; - imm32 r7, 0xc123456d; - A0 -= R6.H * R7.L; - R6 = A0.w; - R7 = A1.w; - A1 -= R4.L * R5.H (M); - R4 = A0.w; - R5 = A1.w; - A0 -= R2.L * R3.L; - R2 = A0.w; - R3 = A1.w; - A1 -= R0.H * R1.L (M); - R0 = A0.w; - R1 = A1.w; - CHECKREG r0, 0xA9327DEE; - CHECKREG r1, 0x1110C6AD; - CHECKREG r2, 0xA9327DEE; - CHECKREG r3, 0xFE8B3081; - CHECKREG r4, 0x39244796; - CHECKREG r5, 0xFE8B3081; - CHECKREG r6, 0x39244796; - CHECKREG r7, 0xEB97313C; - - pass - - .data -DATA0: - .dd 0x000a0000 - .dd 0x000b0001 - .dd 0x000c0002 - .dd 0x000d0003 - .dd 0x000e0004 - .dd 0x000f0005 - -DATA1: - .dd 0x00f00100 - .dd 0x00e00101 - .dd 0x00d00102 - .dd 0x00c00103 - .dd 0x00b00104 - .dd 0x00a00105 diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0.s deleted file mode 100644 index 71bd916..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0.s +++ /dev/null @@ -1,124 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a0/c_dsp32mac_dr_a0.dsp -// Spec Reference: dsp32mac dr_a0 -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0xab235675; -imm32 r1, 0xcaba5127; -imm32 r2, 0x13a46705; -imm32 r3, 0x000a0007; -imm32 r4, 0x90abad09; -imm32 r5, 0x10aceadb; -imm32 r6, 0x000c00ad; -imm32 r7, 0x1246700a; - -A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0xb3545abd; -imm32 r1, 0xabbcfec7; -imm32 r2, 0xa1b45679; -imm32 r3, 0x000b0007; -imm32 r4, 0xefbcb569; -imm32 r5, 0x12350b0b; -imm32 r6, 0x000c00bd; -imm32 r7, 0x678e000b; -A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ); -R1 = A0.w; -A1 -= R2.L * R3.L, R2.L = ( A0 = R2.H * R3.L ); -R3 = A0.w; -A1 = R4.L * R5.L, R4.L = ( A0 += R4.H * R5.H ); -R5 = A0.w; -A1 = R6.L * R7.L, R6.L = ( A0 = R6.L * R7.H ); -R7 = A0.w; -CHECKREG r0, 0xB354FF22; -CHECKREG r1, 0xFF221DD6; -CHECKREG r2, 0xA1B4FFFB; -CHECKREG r3, 0xFFFAD7D8; -CHECKREG r4, 0xEFBCFDAB; -CHECKREG r5, 0xFDAA8BB0; -CHECKREG r6, 0x000C0099; -CHECKREG r7, 0x0098E7AC; - -imm32 r0, 0xc3545abd; -imm32 r1, 0xacbcfec7; -imm32 r2, 0xa1c45679; -imm32 r3, 0x000c0007; -imm32 r4, 0xefbcc569; -imm32 r5, 0x12350c0b; -imm32 r6, 0x000c00cd; -imm32 r7, 0x678e000c; -A1 = R1.L * R0.H, R0.L = ( A0 = R1.L * R0.L ); -R1 = A0.w; -A1 -= R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ); -R3 = A0.w; -A1 = R4.H * R5.H, R4.L = ( A0 += R4.H * R5.H ); -R5 = A0.w; -A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ); -R7 = A0.w; -CHECKREG r0, 0xC354FF22; -CHECKREG r1, 0xFF221DD6; -CHECKREG r2, 0xA1C4FF27; -CHECKREG r3, 0xFF27451E; -CHECKREG r4, 0xEFBCFCD7; -CHECKREG r5, 0xFCD6F8F6; -CHECKREG r6, 0x000CFD7D; -CHECKREG r7, 0xFD7CD262; - -imm32 r0, 0xd3545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1d45679; -imm32 r3, 0x000d0007; -imm32 r4, 0xefbcd569; -imm32 r5, 0x12350d0b; -imm32 r6, 0x000c00dd; -imm32 r7, 0x678e000d; -A1 += R1.H * R0.L, R0.L = ( A0 -= R1.L * R0.L ); -R1 = A0.w; -A1 = R2.H * R3.H, R2.L = ( A0 -= R2.H * R3.L ); -R3 = A0.w; -A1 -= R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ); -R5 = A0.w; -A1 += R6.H * R7.L, R6.L = ( A0 = R6.L * R7.H ); -R7 = A0.w; -CHECKREG r0, 0xD354FE5B; -CHECKREG r1, 0xFE5AB48C; -CHECKREG r2, 0xA1D4FE60; -CHECKREG r3, 0xFE5FDAF4; -CHECKREG r4, 0xEFBC00B0; -CHECKREG r5, 0x00B0271C; -CHECKREG r6, 0x000C00B3; -CHECKREG r7, 0x00B2CB2C; - -imm32 r0, 0xe3545abd; -imm32 r1, 0xaebcfec7; -imm32 r2, 0xa1e45679; -imm32 r3, 0x000e0007; -imm32 r4, 0xefbce569; -imm32 r5, 0x12350e0b; -imm32 r6, 0x000c00ed; -imm32 r7, 0x678e000e; -A1 = R1.H * R0.H, R0.L = ( A0 = R1.L * R0.L ); -R1 = A0.w; -A1 += R2.H * R3.H, R2.L = ( A0 += R2.H * R3.L ); -R3 = A0.w; -A1 = R4.H * R5.H, R4.L = ( A0 = R4.H * R5.H ); -R5 = A0.w; -A1 = R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H ); -R7 = A0.w; -CHECKREG r0, 0xE354FF22; -CHECKREG r1, 0xFF221DD6; -CHECKREG r2, 0xA1E4FF1D; -CHECKREG r3, 0xFF1CF84E; -CHECKREG r4, 0xEFBCFDB0; -CHECKREG r5, 0xFDAFB3D8; -CHECKREG r6, 0x000CFCF0; -CHECKREG r7, 0xFCEFF6EC; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_i.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_i.s deleted file mode 100644 index 4696075..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_i.s +++ /dev/null @@ -1,119 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a0_i/c_dsp32mac_dr_a0_i.dsp -// Spec Reference: dsp32mac dr a0 i (signed int) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0xa3545abd; -imm32 r1, 0x9dbcfec7; -imm32 r2, 0xc9248679; -imm32 r3, 0xd0969007; -imm32 r4, 0xefb94569; -imm32 r5, 0xcd35900b; -imm32 r6, 0xe00c890d; -imm32 r7, 0xf78e909f; -A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (IS); -R1 = A0.w; -A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IS); -R3 = A0.w; -A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IS); -R5 = A0.w; -A1 += R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H ) (IS); -R7 = A0.w; -CHECKREG r0, 0xA3548000; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0xC9247FFF; -CHECKREG r3, 0x17FEBFFC; -CHECKREG r4, 0xEFB97FFF; -CHECKREG r5, 0x1B398649; -CHECKREG r6, 0xE00C7FFF; -CHECKREG r7, 0x174CF613; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x68548abd; -imm32 r1, 0x7d8cfec7; -imm32 r2, 0xa1285679; -imm32 r3, 0xb0068007; -imm32 r4, 0xcfbc4869; -imm32 r5, 0xd235c08b; -imm32 r6, 0xe00ca008; -imm32 r7, 0x678e700f; -R0.L = ( A0 -= R1.L * R0.L ) (IS); -R1 = A0.w; -R2.L = ( A0 += R2.L * R3.H ) (IS); -R3 = A0.w; -R4.L = ( A0 = R4.H * R5.L ) (IS); -R5 = A0.w; -R6.L = ( A0 -= R6.H * R7.H ) (IS); -R7 = A0.w; -CHECKREG r0, 0x68547FFF; -CHECKREG r1, 0x16BD9728; -CHECKREG r2, 0xA1288000; -CHECKREG r3, 0xFBB9CDFE; -CHECKREG r4, 0xCFBC7FFF; -CHECKREG r5, 0x0BF6CB14; -CHECKREG r6, 0xE00C7FFF; -CHECKREG r7, 0x18E3B06C; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x7b54babd; -imm32 r1, 0xb7bcdec7; -imm32 r2, 0x7b7be679; -imm32 r3, 0x80b77007; -imm32 r4, 0x9fbb7569; -imm32 r5, 0xa235b70b; -imm32 r6, 0xb00c3b7d; -imm32 r7, 0xc78ea0b7; -R0.L = ( A0 = R1.L * R0.L ) (IS); -R1 = A0.w; -R2.L = ( A0 -= R2.H * R3.L ) (IS); -R3 = A0.w; -R4.L = ( A0 = R4.H * R5.H ) (IS); -R5 = A0.w; -R6.L = ( A0 += R6.L * R7.H ) (IS); -R7 = A0.w; -CHECKREG r0, 0x7B547FFF; -CHECKREG r1, 0x08FD0EEB; -CHECKREG r2, 0x7B7B8000; -CHECKREG r3, 0xD2F3DE8E; -CHECKREG r4, 0x9FBB7FFF; -CHECKREG r5, 0x234567B7; -CHECKREG r6, 0xB00C7FFF; -CHECKREG r7, 0x1627920D; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0xe3545abd; -imm32 r1, 0x5ebcfec7; -imm32 r2, 0x71e45679; -imm32 r3, 0x900e0007; -imm32 r4, 0xafbce569; -imm32 r5, 0xd2359e0b; -imm32 r6, 0xc00ca0ed; -imm32 r7, 0x678ed00e; -A1 -= R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (IS); -R3 = A0.w; -A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ) (IS); -R7 = A0.w; -A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (IS); -R5 = A0.w; -A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (IS); -R1 = A0.w; -CHECKREG r0, 0xE3547FFF; -CHECKREG r1, 0x2E5AD9ED; -CHECKREG r2, 0x71E47FFF; -CHECKREG r3, 0x15B8A0F8; -CHECKREG r4, 0xAFBC7FFF; -CHECKREG r5, 0x0E5B99EC; -CHECKREG r6, 0xC00C7FFF; -CHECKREG r7, 0x3FFFCC18; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_ih.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_ih.s deleted file mode 100644 index 3735995..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_ih.s +++ /dev/null @@ -1,119 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a0_ih/c_dsp32mac_dr_a0_ih.dsp -// Spec Reference: dsp32mac dr a0 ih (integer mutiplication with high word extraction) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0xf3545abd; -imm32 r1, 0x7fbcfec7; -imm32 r2, 0xc7fff679; -imm32 r3, 0xd0799007; -imm32 r4, 0xefb79f69; -imm32 r5, 0xcd35700b; -imm32 r6, 0xe00c87fd; -imm32 r7, 0xf78e909f; -A1 = R1.L * R0.L, R0.L = ( A0 -= R1.L * R0.L ) (IH); -R1 = A0.w; -A1 = R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IH); -R3 = A0.w; -A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IH); -R5 = A0.w; -A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (IH); -R7 = A0.w; -CHECKREG r0, 0xF354006F; -CHECKREG r1, 0x006EF115; -CHECKREG r2, 0xC7FF187F; -CHECKREG r3, 0x187EE7F9; -CHECKREG r4, 0xEFB71BBA; -CHECKREG r5, 0x1BBA13DC; -CHECKREG r6, 0xE00C1FB0; -CHECKREG r7, 0x1FAF9D32; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0xc5548abd; -imm32 r1, 0x9b5cfec7; -imm32 r2, 0xa9b55679; -imm32 r3, 0xb09b5007; -imm32 r4, 0xcfb9b5c9; -imm32 r5, 0x52359b5c; -imm32 r6, 0xe50c5098; -imm32 r7, 0x675e7509; -R0.L = ( A0 = R1.L * R0.L ) (IH); -R1 = A0.w; -R2.L = ( A0 += R2.L * R3.H ) (IH); -R3 = A0.w; -R4.L = ( A0 = R4.H * R5.L ) (IH); -R5 = A0.w; -R6.L = ( A0 -= R6.H * R7.H ) (IH); -R7 = A0.w; -CHECKREG r0, 0xC554008F; -CHECKREG r1, 0x008F5EEB; -CHECKREG r2, 0xA9B5E5BE; -CHECKREG r3, 0xE5BDEA2E; -CHECKREG r4, 0xCFB912FB; -CHECKREG r5, 0x12FAA97C; -CHECKREG r6, 0xE50C1DDD; -CHECKREG r7, 0x1DDCBB14; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x4b54babd; -imm32 r1, 0x12346ec7; -imm32 r2, 0xa4bbe679; -imm32 r3, 0x8abdb707; -imm32 r4, 0x9f4b7b69; -imm32 r5, 0xa234877b; -imm32 r6, 0xb00c4887; -imm32 r7, 0xc78ea4b8; -R0.L = ( A0 = R1.L * R0.L ) (IH); -R1 = A0.w; -R2.L = ( A0 -= R2.H * R3.L ) (IH); -R3 = A0.w; -R4.L = ( A0 = R4.H * R5.H ) (IH); -R5 = A0.w; -R6.L = ( A0 += R6.L * R7.H ) (IH); -R7 = A0.w; -CHECKREG r0, 0x4B54E207; -CHECKREG r1, 0xE2075EEB; -CHECKREG r2, 0xA4BBC803; -CHECKREG r3, 0xC80330CE; -CHECKREG r4, 0x9F4B236F; -CHECKREG r5, 0x236ED13C; -CHECKREG r6, 0xB00C1371; -CHECKREG r7, 0x1370FD1E; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0x1a545abd; -imm32 r1, 0x42fcfec7; -imm32 r2, 0xc53f5679; -imm32 r3, 0x9c64f007; -imm32 r4, 0xafc7ec69; -imm32 r5, 0xd23c891b; -imm32 r6, 0xc00cc602; -imm32 r7, 0x678edc7e; -A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (IH); -R3 = A0.w; -A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (IH); -R7 = A0.w; -A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (IH); -R5 = A0.w; -A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (IH); -R1 = A0.w; -CHECKREG r0, 0x1A54EEED; -CHECKREG r1, 0xEEED15DF; -CHECKREG r2, 0xC53F1302; -CHECKREG r3, 0x13020C09; -CHECKREG r4, 0xAFC7EEE5; -CHECKREG r5, 0xEEE57293; -CHECKREG r6, 0xC00CFD3D; -CHECKREG r7, 0xFD3CE337; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_is.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_is.s deleted file mode 100644 index 9c10949..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_is.s +++ /dev/null @@ -1,119 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a0_is/c_dsp32mac_dr_a0_is.dsp -// Spec Reference: dsp32mac dr a0 is (scale by 2.0 signed fraction with round) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0xf3545abd; -imm32 r1, 0x7fbcfec7; -imm32 r2, 0xc7fff679; -imm32 r3, 0xd0799007; -imm32 r4, 0xefb79f69; -imm32 r5, 0xcd35700b; -imm32 r6, 0xe00c87fd; -imm32 r7, 0xf78e909f; -A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (ISS2); -R1 = A0.w; -A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (ISS2); -R3 = A0.w; -A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (ISS2); -R5 = A0.w; -A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (ISS2); -R7 = A0.w; -CHECKREG r0, 0xF3548000; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0xC7FF8000; -CHECKREG r3, 0xE71226F2; -CHECKREG r4, 0xEFB78000; -CHECKREG r5, 0xEA4D52D5; -CHECKREG r6, 0xE00C8000; -CHECKREG r7, 0xEE42DC2B; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0xc5548abd; -imm32 r1, 0x9b5cfec7; -imm32 r2, 0xa9b55679; -imm32 r3, 0xb09b5007; -imm32 r4, 0xcfb9b5c9; -imm32 r5, 0x52359b5c; -imm32 r6, 0xe50c5098; -imm32 r7, 0x675e7509; -R0.L = ( A0 -= R1.L * R0.L ) (ISS2); -R1 = A0.w; -R2.L = ( A0 += R2.L * R3.H ) (ISS2); -R3 = A0.w; -R4.L = ( A0 = R4.H * R5.L ) (ISS2); -R5 = A0.w; -R6.L = ( A0 -= R6.H * R7.H ) (ISS2); -R7 = A0.w; -CHECKREG r0, 0xC5548000; -CHECKREG r1, 0xEDB37D40; -CHECKREG r2, 0xA9B58000; -CHECKREG r3, 0xD2E20883; -CHECKREG r4, 0xCFB97FFF; -CHECKREG r5, 0x12FAA97C; -CHECKREG r6, 0xE50C7FFF; -CHECKREG r7, 0x1DDCBB14; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x4b54babd; -imm32 r1, 0x12346ec7; -imm32 r2, 0xa4bbe679; -imm32 r3, 0x8abdb707; -imm32 r4, 0x9f4b7b69; -imm32 r5, 0xa234877b; -imm32 r6, 0xb00c4887; -imm32 r7, 0xc78ea4b8; -R0.L = ( A0 = R1.L * R0.L ) (ISS2); -R1 = A0.w; -R2.L = ( A0 -= R2.H * R3.L ) (ISS2); -R3 = A0.w; -R4.L = ( A0 = R4.H * R5.H ) (ISS2); -R5 = A0.w; -R6.L = ( A0 += R6.L * R7.H ) (ISS2); -R7 = A0.w; -CHECKREG r0, 0x4B548000; -CHECKREG r1, 0xE2075EEB; -CHECKREG r2, 0xA4BB8000; -CHECKREG r3, 0xC80330CE; -CHECKREG r4, 0x9F4B7FFF; -CHECKREG r5, 0x236ED13C; -CHECKREG r6, 0xB00C7FFF; -CHECKREG r7, 0x1370FD1E; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0x1a545abd; -imm32 r1, 0x42fcfec7; -imm32 r2, 0xc53f5679; -imm32 r3, 0x9c64f007; -imm32 r4, 0xafc7ec69; -imm32 r5, 0xd23c891b; -imm32 r6, 0xc00cc602; -imm32 r7, 0x678edc7e; -A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (ISS2); -R3 = A0.w; -A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (ISS2); -R7 = A0.w; -A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (ISS2); -R5 = A0.w; -A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (ISS2); -R1 = A0.w; -CHECKREG r0, 0x1A548000; -CHECKREG r1, 0xF0477293; -CHECKREG r2, 0xC53F7FFF; -CHECKREG r3, 0x13020C09; -CHECKREG r4, 0xAFC78000; -CHECKREG r5, 0xEEE57293; -CHECKREG r6, 0xC00C8000; -CHECKREG r7, 0xFD3CE337; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_iu.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_iu.s deleted file mode 100644 index 2017459..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_iu.s +++ /dev/null @@ -1,119 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a0_iu/c_dsp32mac_dr_a0_iu.dsp -// Spec Reference: dsp32mac dr a0 iu (unsigned int) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0x83545abd; -imm32 r1, 0x78bcfec7; -imm32 r2, 0xc7948679; -imm32 r3, 0xd0799007; -imm32 r4, 0xefb79569; -imm32 r5, 0xcd35700b; -imm32 r6, 0xe00c877d; -imm32 r7, 0xf78e9097; -A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ); -R1 = A0.w; -A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ); -R3 = A0.w; -A1 = R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ); -R5 = A0.w; -A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ); -R7 = A0.w; -CHECKREG r0, 0x8354FF22; -CHECKREG r1, 0xFF221DD6; -CHECKREG r2, 0xC794315B; -CHECKREG r3, 0x315B6A18; -CHECKREG r4, 0xEFB72AE5; -CHECKREG r5, 0x2AE51252; -CHECKREG r6, 0xE00C32D9; -CHECKREG r7, 0x32D896FE; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0xc5548abd; -imm32 r1, 0x7b5cfec7; -imm32 r2, 0xa1b55679; -imm32 r3, 0xb00b5007; -imm32 r4, 0xcfbcb5c9; -imm32 r5, 0x5235cb5c; -imm32 r6, 0xe50c50b8; -imm32 r7, 0x675e750b; -R0.L = ( A0 = R1.L * R0.L ); -R1 = A0.w; -R2.L = ( A0 += R2.L * R3.H ); -R3 = A0.w; -R4.L = ( A0 -= R4.H * R5.L ); -R5 = A0.w; -R6.L = ( A0 = R6.H * R7.H ); -R7 = A0.w; -CHECKREG r0, 0xC554011F; -CHECKREG r1, 0x011EBDD6; -CHECKREG r2, 0xA1B5CB1B; -CHECKREG r3, 0xCB1A8C3C; -CHECKREG r4, 0xCFBCB741; -CHECKREG r5, 0xB741151C; -CHECKREG r6, 0xE50CEA3C; -CHECKREG r7, 0xEA3BDCD0; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x4b54babd; -imm32 r1, 0xbabcdec7; -imm32 r2, 0xa4bbe679; -imm32 r3, 0x8abdb007; -imm32 r4, 0x9f4b7b69; -imm32 r5, 0xa23487bb; -imm32 r6, 0xb00c488b; -imm32 r7, 0xc78ea4b8; -R0.L = ( A0 -= R1.L * R0.L ); -R1 = A0.w; -R2.L = ( A0 = R2.H * R3.L ); -R3 = A0.w; -R4.L = ( A0 = R4.H * R5.H ); -R5 = A0.w; -R6.L = ( A0 += R6.L * R7.H ); -R7 = A0.w; -CHECKREG r0, 0x4B54D842; -CHECKREG r1, 0xD841BEFA; -CHECKREG r2, 0xA4BB3906; -CHECKREG r3, 0x3906223A; -CHECKREG r4, 0x9F4B46DE; -CHECKREG r5, 0x46DDA278; -CHECKREG r6, 0xB00C26E0; -CHECKREG r7, 0x26E036AC; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0x1a545abd; -imm32 r1, 0x52fcfec7; -imm32 r2, 0xc13f5679; -imm32 r3, 0x9c04f007; -imm32 r4, 0xafccec69; -imm32 r5, 0xd23c5e1b; -imm32 r6, 0xc00cc6e2; -imm32 r7, 0x678edc7e; -A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ); -R3 = A0.w; -A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ); -R7 = A0.w; -A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ); -R5 = A0.w; -A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ); -R1 = A0.w; -CHECKREG r0, 0x1A544DFA; -CHECKREG r1, 0x4DFA5880; -CHECKREG r2, 0xC13F2602; -CHECKREG r3, 0x26025482; -CHECKREG r4, 0xAFCC1CAD; -CHECKREG r5, 0x1CAD17A0; -CHECKREG r6, 0xC00C4F71; -CHECKREG r7, 0x4F70B886; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_m.s deleted file mode 100644 index dcdbae0..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_m.s +++ /dev/null @@ -1,127 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a0_m/c_dsp32mac_dr_a0_m.dsp -// Spec Reference: dsp32mac dr_a0 m -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0xab235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acefdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246700f; - -A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; -A1 -= R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ); -R1 = A0.w; -A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ); -R3 = A0.w; -A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ); -R5 = A0.w; -A1 = R6.H * R7.H, R6.L = ( A0 = R6.L * R7.H ); -R7 = A0.w; -CHECKREG r0, 0x1354FF22; -CHECKREG r1, 0xFF221DD6; -CHECKREG r2, 0xA124FF27; -CHECKREG r3, 0xFF274DDE; -CHECKREG r4, 0xEFBCFCD7; -CHECKREG r5, 0xFCD701B6; -CHECKREG r6, 0x000C000B; -CHECKREG r7, 0x000A846C; - -// The result accumulated in A1, and stored to a reg half (MNOP) -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; -R0.L = ( A0 += R6.L * R7.L ); -R1 = A0.w; -R2.L = ( A0 -= R2.L * R3.H ); -R3 = A0.w; -R4.L = ( A0 += R4.H * R5.L ); -R5 = A0.w; -R6.L = ( A0 = R0.H * R1.H ); -R7 = A0.w; -CHECKREG r0, 0x1354000B; -CHECKREG r1, 0x000A85F2; -CHECKREG r2, 0xA1240006; -CHECKREG r3, 0x00067846; -CHECKREG r4, 0xEFBC0005; -CHECKREG r5, 0x0005126E; -CHECKREG r6, 0x000C0002; -CHECKREG r7, 0x00018290; - -// The result accumulated in A1 , and stored to a reg half (MNOP) -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; -R0.L = ( A0 = R1.L * R0.L ); -R1 = A0.w; -R2.L = ( A0 += R2.H * R3.L ); -R3 = A0.w; -R4.L = ( A0 += R4.H * R5.H ); -R5 = A0.w; -R6.L = ( A0 += R6.L * R7.H ); -R7 = A0.w; -CHECKREG r0, 0x1354FF22; -CHECKREG r1, 0xFF221DD6; -CHECKREG r2, 0xA124FF1D; -CHECKREG r3, 0xFF1CEDCE; -CHECKREG r4, 0xEFBCFCCD; -CHECKREG r5, 0xFCCCA1A6; -CHECKREG r6, 0x000CFCD7; -CHECKREG r7, 0xFCD72612; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; -A1 = R1.L * R0.L (M), R6.L = ( A0 -= R1.L * R0.L ); -R7 = A0.w; -A1 -= R2.L * R3.H (M), R2.L = ( A0 += R2.H * R3.L ); -R3 = A0.w; -A1 = R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ); -R5 = A0.w; -A1 -= R6.H * R7.H (M), R0.L = ( A0 = R6.L * R7.H ); -R1 = A0.w; -CHECKREG r0, 0x1354000B; -CHECKREG r1, 0x000A83F2; -CHECKREG r2, 0xA124FDB0; -CHECKREG r3, 0xFDAFD834; -CHECKREG r4, 0xEFBCFDB0; -CHECKREG r5, 0xFDAFB3D8; -CHECKREG r6, 0x000CFDB5; -CHECKREG r7, 0xFDB5083C; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_s.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_s.s deleted file mode 100644 index 2288130..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_s.s +++ /dev/null @@ -1,119 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a0_s/c_dsp32mac_dr_a0_s.dsp -// Spec Reference: dsp32mac dr a0 s (scale by 2.0 signed fraction with round) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0x83545abd; -imm32 r1, 0x98bcfec7; -imm32 r2, 0xc9948679; -imm32 r3, 0xd0999007; -imm32 r4, 0xefb99569; -imm32 r5, 0xcd35900b; -imm32 r6, 0xe00c89ad; -imm32 r7, 0xf78e909a; -A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (S2RND); -R1 = A0.w; -A1 = R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (S2RND); -R3 = A0.w; -A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (S2RND); -R5 = A0.w; -A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (S2RND); -R7 = A0.w; -CHECKREG r0, 0x8354FE44; -CHECKREG r1, 0xFF221DD6; -CHECKREG r2, 0xC9945F37; -CHECKREG r3, 0x2F9B8618; -CHECKREG r4, 0xEFB96C22; -CHECKREG r5, 0x361112B2; -CHECKREG r6, 0xE00C7BBF; -CHECKREG r7, 0x3DDFA49E; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0xc8548abd; -imm32 r1, 0x7bccfec7; -imm32 r2, 0xa1bc5679; -imm32 r3, 0xb00bc007; -imm32 r4, 0xcfbcb8c9; -imm32 r5, 0x5235cb8c; -imm32 r6, 0xe50ca0b8; -imm32 r7, 0x675e700b; -R0.L = ( A0 = R1.L * R0.L ) (S2RND); -R1 = A0.w; -R2.L = ( A0 += R2.L * R3.H ) (S2RND); -R3 = A0.w; -R4.L = ( A0 -= R4.H * R5.L ) (S2RND); -R5 = A0.w; -R6.L = ( A0 = R6.H * R7.H ) (S2RND); -R7 = A0.w; -CHECKREG r0, 0xC854023D; -CHECKREG r1, 0x011EBDD6; -CHECKREG r2, 0xA1BC9635; -CHECKREG r3, 0xCB1A8C3C; -CHECKREG r4, 0xCFBC8000; -CHECKREG r5, 0xB7532E9C; -CHECKREG r6, 0xE50CD478; -CHECKREG r7, 0xEA3BDCD0; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x7b54babd; -imm32 r1, 0xbabcdec7; -imm32 r2, 0xabbbe679; -imm32 r3, 0x8abdb007; -imm32 r4, 0x9fab7b69; -imm32 r5, 0xa23a87bb; -imm32 r6, 0xb00ca88b; -imm32 r7, 0xc78eaab8; -R0.L = ( A0 = R1.L * R0.L ) (S2RND); -R1 = A0.w; -R2.L = ( A0 -= R2.H * R3.L ) (S2RND); -R3 = A0.w; -R4.L = ( A0 = R4.H * R5.H ) (S2RND); -R5 = A0.w; -R6.L = ( A0 += R6.L * R7.H ) (S2RND); -R7 = A0.w; -CHECKREG r0, 0x7B5423F4; -CHECKREG r1, 0x11FA1DD6; -CHECKREG r2, 0xABBBBAA7; -CHECKREG r3, 0xDD53999C; -CHECKREG r4, 0x9FAB7FFF; -CHECKREG r5, 0x4692C57C; -CHECKREG r6, 0xB00C7FFF; -CHECKREG r7, 0x6D23D9B0; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0xfa545abd; -imm32 r1, 0x5ffcfec7; -imm32 r2, 0xc1ef5679; -imm32 r3, 0x9c0ef007; -imm32 r4, 0xafccec69; -imm32 r5, 0xd23c9e1b; -imm32 r6, 0xc00cc0e2; -imm32 r7, 0x678edc0e; -A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (S2RND); -R3 = A0.w; -A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (S2RND); -R7 = A0.w; -A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (S2RND); -R5 = A0.w; -A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (S2RND); -R1 = A0.w; -CHECKREG r0, 0xFA54CF65; -CHECKREG r1, 0xE7B2ACD4; -CHECKREG r2, 0xC1EF7FFF; -CHECKREG r3, 0x6C45F786; -CHECKREG r4, 0xAFCCCEDE; -CHECKREG r5, 0xE76F2094; -CHECKREG r6, 0xC00C0838; -CHECKREG r7, 0x041C3834; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_t.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_t.s deleted file mode 100644 index f72f8cc..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_t.s +++ /dev/null @@ -1,119 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a0_t/c_dsp32mac_dr_a0_t.dsp -// Spec Reference: dsp32mac dr a0 t (truncation) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0xa3545abd; -imm32 r1, 0xbdbcfec7; -imm32 r2, 0xc1248679; -imm32 r3, 0xd0069007; -imm32 r4, 0xefbc4569; -imm32 r5, 0xcd35500b; -imm32 r6, 0xe00c800d; -imm32 r7, 0xf78e900f; -A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (T); -R1 = A0.w; -A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (T); -R3 = A0.w; -A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (T); -R5 = A0.w; -A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (T); -R7 = A0.w; -CHECKREG r0, 0xA354FF22; -CHECKREG r1, 0xFF221DD6; -CHECKREG r2, 0xC12436FD; -CHECKREG r3, 0x36FD0FF8; -CHECKREG r4, 0xEFBC3D71; -CHECKREG r5, 0x3D716BD0; -CHECKREG r6, 0xE00C45E2; -CHECKREG r7, 0x45E2903C; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x63548abd; -imm32 r1, 0x7dbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0xb0069007; -imm32 r4, 0xcfbc4569; -imm32 r5, 0xd235c00b; -imm32 r6, 0xe00ca00d; -imm32 r7, 0x678e700f; -R0.L = ( A0 = R1.L * R0.L ) (T); -R1 = A0.w; -R2.L = ( A0 += R2.L * R3.H ) (T); -R3 = A0.w; -R4.L = ( A0 -= R4.H * R5.L ) (T); -R5 = A0.w; -R6.L = ( A0 = R6.H * R7.H ) (T); -R7 = A0.w; -CHECKREG r0, 0x6354011E; -CHECKREG r1, 0x011EBDD6; -CHECKREG r2, 0xA124CB17; -CHECKREG r3, 0xCB172B82; -CHECKREG r4, 0xCFBCB2F9; -CHECKREG r5, 0xB2F9515A; -CHECKREG r6, 0xE00CE626; -CHECKREG r7, 0xE6263550; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x5354babd; -imm32 r1, 0x6dbcdec7; -imm32 r2, 0x7124e679; -imm32 r3, 0x80067007; -imm32 r4, 0x9fbc4569; -imm32 r5, 0xa235900b; -imm32 r6, 0xb00c300d; -imm32 r7, 0xc78ea00f; -R0.L = ( A0 -= R1.L * R0.L ) (T); -R1 = A0.w; -R2.L = ( A0 = R2.H * R3.L ) (T); -R3 = A0.w; -R4.L = ( A0 -= R4.H * R5.H ) (T); -R5 = A0.w; -R6.L = ( A0 += R6.L * R7.H ) (T); -R7 = A0.w; -CHECKREG r0, 0x5354D42C; -CHECKREG r1, 0xD42C177A; -CHECKREG r2, 0x71246305; -CHECKREG r3, 0x6305AFF8; -CHECKREG r4, 0x9FBC1C7B; -CHECKREG r5, 0x1C7B9C20; -CHECKREG r6, 0xB00C074B; -CHECKREG r7, 0x074B208C; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0x33545abd; -imm32 r1, 0x5dbcfec7; -imm32 r2, 0x71245679; -imm32 r3, 0x90060007; -imm32 r4, 0xafbc4569; -imm32 r5, 0xd235900b; -imm32 r6, 0xc00ca00d; -imm32 r7, 0x678ed00f; -A1 = R1.L * R0.L (M), R0.L = ( A0 += R1.L * R0.L ) (T); -R1 = A0.w; -A1 += R2.L * R3.H (M), R2.L = ( A0 -= R2.H * R3.L ) (T); -R3 = A0.w; -A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (T); -R5 = A0.w; -A1 -= R6.H * R7.H (M), R6.L = ( A0 += R6.L * R7.H ) (T); -R7 = A0.w; -CHECKREG r0, 0x3354066D; -CHECKREG r1, 0x066D3E62; -CHECKREG r2, 0x71240667; -CHECKREG r3, 0x06670E6A; -CHECKREG r4, 0xAFBC1CB7; -CHECKREG r5, 0x1CB733D8; -CHECKREG r6, 0xC00CCF17; -CHECKREG r7, 0xCF173844; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_tu.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_tu.s deleted file mode 100644 index 61c4670..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_tu.s +++ /dev/null @@ -1,119 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a0_tu/c_dsp32mac_dr_a0_tu.dsp -// Spec Reference: dsp32mac dr a0 tu (truncate unsigned fraction) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0xf3545abd; -imm32 r1, 0x7fbcfec7; -imm32 r2, 0xc7fff679; -imm32 r3, 0xd0799007; -imm32 r4, 0xefb79f69; -imm32 r5, 0xcd35700b; -imm32 r6, 0xe00c87fd; -imm32 r7, 0xf78e909f; -A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (TFU); -R1 = A0.w; -A1 -= R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (TFU); -R3 = A0.w; -A1 += R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ) (TFU); -R5 = A0.w; -A1 += R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (TFU); -R7 = A0.w; -CHECKREG r0, 0xF3545A4E; -CHECKREG r1, 0x5A4E0EEB; -CHECKREG r2, 0xC7FF0000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0xEFB70000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0xE00C8380; -CHECKREG r7, 0x83808956; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0xc5548abd; -imm32 r1, 0x9b5cfec7; -imm32 r2, 0xa9b55679; -imm32 r3, 0xb09b5007; -imm32 r4, 0xcfb9b5c9; -imm32 r5, 0x52359b5c; -imm32 r6, 0xe50c5098; -imm32 r7, 0x675e7509; -R0.L = ( A0 = R1.L * R0.L ) (TFU); -R1 = A0.w; -R2.L = ( A0 += R2.L * R3.H ) (TFU); -R3 = A0.w; -R4.L = ( A0 = R4.H * R5.L ) (TFU); -R5 = A0.w; -R6.L = ( A0 -= R6.H * R7.H ) (TFU); -R7 = A0.w; -CHECKREG r0, 0xC5548A13; -CHECKREG r1, 0x8A135EEB; -CHECKREG r2, 0xA9B5C5BA; -CHECKREG r3, 0xC5BAEA2E; -CHECKREG r4, 0xCFB97E0F; -CHECKREG r5, 0x7E0FA97C; -CHECKREG r6, 0xE50C2193; -CHECKREG r7, 0x2193BB14; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x4b54babd; -imm32 r1, 0x12346ec7; -imm32 r2, 0xa4bbe679; -imm32 r3, 0x8abdb707; -imm32 r4, 0x9f4b7b69; -imm32 r5, 0xa234877b; -imm32 r6, 0xb00c4887; -imm32 r7, 0xc78ea4b8; -R0.L = ( A0 -= R1.L * R0.L ) (TFU); -R1 = A0.w; -R2.L = ( A0 = R2.H * R3.L ) (TFU); -R3 = A0.w; -R4.L = ( A0 -= R4.H * R5.H ) (TFU); -R5 = A0.w; -R6.L = ( A0 += R6.L * R7.H ) (TFU); -R7 = A0.w; -CHECKREG r0, 0x4B540000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0xA4BB75C6; -CHECKREG r3, 0x75C62E1D; -CHECKREG r4, 0x9F4B10D8; -CHECKREG r5, 0x10D85CE1; -CHECKREG r6, 0xB00C4961; -CHECKREG r7, 0x496188C3; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0x1a545abd; -imm32 r1, 0x42fcfec7; -imm32 r2, 0xc53f5679; -imm32 r3, 0x9c64f007; -imm32 r4, 0xafc7ec69; -imm32 r5, 0xd23c891b; -imm32 r6, 0xc00cc602; -imm32 r7, 0x678edc7e; -A1 -= R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (TFU); -R3 = A0.w; -A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ) (TFU); -R7 = A0.w; -A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (TFU); -R5 = A0.w; -A1 -= R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (TFU); -R1 = A0.w; -CHECKREG r0, 0x1A5498EA; -CHECKREG r1, 0x98EA3745; -CHECKREG r2, 0xC53FA3AF; -CHECKREG r3, 0xA3AF97AE; -CHECKREG r4, 0xAFC7905A; -CHECKREG r5, 0x905A70A4; -CHECKREG r6, 0xC00C2ED1; -CHECKREG r7, 0x2ED15DDC; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_u.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_u.s deleted file mode 100644 index 5ca5cac..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_u.s +++ /dev/null @@ -1,119 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a0_u/c_dsp32mac_dr_a0_u.dsp -// Spec Reference: dsp32mac dr a0 u (unsigned fraction and unsigned int) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0xa3545abd; -imm32 r1, 0x9abcfec7; -imm32 r2, 0xc9a48679; -imm32 r3, 0xd09a9007; -imm32 r4, 0xefb9a569; -imm32 r5, 0xcd359a0b; -imm32 r6, 0xe00c89ad; -imm32 r7, 0xf78e909a; -A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (FU); -R1 = A0.w; -A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (FU); -R3 = A0.w; -A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (FU); -R5 = A0.w; -A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (FU); -R7 = A0.w; -CHECKREG r0, 0xA3545A4E; -CHECKREG r1, 0x5A4E0EEB; -CHECKREG r2, 0xC9A40000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0xEFB9C029; -CHECKREG r5, 0xC028C64D; -CHECKREG r6, 0xE00CFFFF; -CHECKREG r7, 0x454B0F43; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0xb8548abd; -imm32 r1, 0x7b8cfec7; -imm32 r2, 0xa1b85679; -imm32 r3, 0xb00b8007; -imm32 r4, 0xcfbcb869; -imm32 r5, 0xd235cb8b; -imm32 r6, 0xe00ca0b8; -imm32 r7, 0x678e700b; -R0.L = ( A0 = R1.L * R0.L ) (FU); -R1 = A0.w; -R2.L = ( A0 += R2.L * R3.H ) (FU); -R3 = A0.w; -R4.L = ( A0 -= R4.H * R5.L ) (FU); -R5 = A0.w; -R6.L = ( A0 = R6.H * R7.H ) (FU); -R7 = A0.w; -CHECKREG r0, 0xB8548A13; -CHECKREG r1, 0x8A135EEB; -CHECKREG r2, 0xA1B8C58A; -CHECKREG r3, 0xC58A461E; -CHECKREG r4, 0xCFBC205F; -CHECKREG r5, 0x205F670A; -CHECKREG r6, 0xE00C5AA1; -CHECKREG r7, 0x5AA11AA8; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x7b54babd; -imm32 r1, 0xb7bcdec7; -imm32 r2, 0xab7be679; -imm32 r3, 0x8ab7b007; -imm32 r4, 0x9fab7b69; -imm32 r5, 0xa23ab7bb; -imm32 r6, 0xb00cab7b; -imm32 r7, 0xc78eaab7; -R0.L = ( A0 = R1.L * R0.L ) (FU); -R1 = A0.w; -R2.L = ( A0 -= R2.H * R3.L ) (FU); -R3 = A0.w; -R4.L = ( A0 = R4.H * R5.H ) (FU); -R5 = A0.w; -R6.L = ( A0 += R6.L * R7.H ) (FU); -R7 = A0.w; -CHECKREG r0, 0x7B54A281; -CHECKREG r1, 0xA2810EEB; -CHECKREG r2, 0xAB7B2C98; -CHECKREG r3, 0x2C97CE8E; -CHECKREG r4, 0x9FAB652E; -CHECKREG r5, 0x652E62BE; -CHECKREG r6, 0xB00CEADA; -CHECKREG r7, 0xEADA1DF8; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0xea545abd; -imm32 r1, 0x5eacfec7; -imm32 r2, 0xc1ea5679; -imm32 r3, 0x9c0ea007; -imm32 r4, 0xafccea69; -imm32 r5, 0xd23c9eab; -imm32 r6, 0xc00cc0ea; -imm32 r7, 0x678edc0e; -A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (FU); -R3 = A0.w; -A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (FU); -R7 = A0.w; -A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (FU); -R5 = A0.w; -A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (FU); -R1 = A0.w; -CHECKREG r0, 0xEA540484; -CHECKREG r1, 0x04840000; -CHECKREG r2, 0xC1EAFFFF; -CHECKREG r3, 0x45282CE3; -CHECKREG r4, 0xAFCC0000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0xC00C2200; -CHECKREG r7, 0x22002A7E; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1.s deleted file mode 100644 index 33c5981..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1.s +++ /dev/null @@ -1,213 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a1/c_dsp32mac_dr_a1.dsp -// Spec Reference: dsp32mac dr_a1 -# mach: bfin - -.include "testutils.inc" - start - - - -A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; -R0.H = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L; -R1 = A1.w; -R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; -R3 = A1.w; -R4.H = ( A1 = R4.L * R5.L ), A0 += R4.H * R5.H; -R5 = A1.w; -R6.H = ( A1 += R6.L * R7.L ), A0 += R6.L * R7.H; -R7 = A1.w; -CHECKREG r0, 0xFF225ABD; -CHECKREG r1, 0xFF221DD6; -CHECKREG r2, 0x00055679; -CHECKREG r3, 0x0004BA9E; -CHECKREG r4, 0x00064569; -CHECKREG r5, 0x0005F706; -CHECKREG r6, 0x0006000D; -CHECKREG r7, 0x0005F88C; - -imm32 r0, 0x13545abd; -imm32 r1, 0xa1bcfec7; -imm32 r2, 0xa1145679; -imm32 r3, 0x00010007; -imm32 r4, 0xefbc1569; -imm32 r5, 0x1235010b; -imm32 r6, 0x000c001d; -imm32 r7, 0x678e0001; -R4.H = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L; -R5 = A1.w; -R0.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L; -R1 = A1.w; -R2.H = ( A1 = R4.L * R5.H ), A0 += R4.H * R5.H; -R3 = A1.w; -R6.H = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H; -R7 = A1.w; -CHECKREG r0, 0x00015ABD; -CHECKREG r1, 0x0000ACF2; -CHECKREG r2, 0xFFF95679; -CHECKREG r3, 0xFFF8F98C; -CHECKREG r4, 0xFFD71569; -CHECKREG r5, 0xFFD6B524; -CHECKREG r6, 0x0010001D; -CHECKREG r7, 0x00106FB8; - -imm32 r0, 0x83545abd; -imm32 r1, 0xa8bcfec7; -imm32 r2, 0xa1845679; -imm32 r3, 0x00080007; -imm32 r4, 0xefbc8569; -imm32 r5, 0x1235080b; -imm32 r6, 0x000c008d; -imm32 r7, 0x678e0008; -R6.H = ( A1 += R1.H * R0.L ), A0 = R1.L * R0.L; -R7 = A1.w; -R2.H = ( A1 = R2.H * R3.L ), A0 = R2.H * R3.L; -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H; -R5 = A1.w; -R0.H = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H; -R1 = A1.w; -CHECKREG r0, 0x1B505ABD; -CHECKREG r1, 0x1B4FC2A8; -CHECKREG r2, 0xFFFB5679; -CHECKREG r3, 0xFFFAD538; -CHECKREG r4, 0xFEFA8569; -CHECKREG r5, 0xFEFA5A28; -CHECKREG r6, 0xC234008D; -CHECKREG r7, 0xC233C550; - -imm32 r0, 0xc3545abd; -imm32 r1, 0xacbcfec7; -imm32 r2, 0xa1c45679; -imm32 r3, 0x000c0007; -imm32 r4, 0xefbcc569; -imm32 r5, 0x12350c0b; -imm32 r6, 0x000c00cd; -imm32 r7, 0x678e000c; -R6.H = ( A1 += R1.H * R0.H ), A0 = R1.L * R0.L; -R7 = A1.w; -R0.H = ( A1 = R2.H * R3.H ), A0 = R2.H * R3.L; -R1 = A1.w; -R4.H = ( A1 = R4.H * R5.H ), A0 += R4.H * R5.H; -R5 = A1.w; -R2.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H; -R3 = A1.w; -CHECKREG r0, 0xFFF75ABD; -CHECKREG r1, 0xFFF72A60; -CHECKREG r2, 0x20875679; -CHECKREG r3, 0x2086A6C8; -CHECKREG r4, 0xFDB0C569; -CHECKREG r5, 0xFDAFB3D8; -CHECKREG r6, 0x42C800CD; -CHECKREG r7, 0x42C78608; - -imm32 r0, 0x01542abd; -imm32 r1, 0x02bc4ec7; -imm32 r2, 0x03240679; -imm32 r3, 0x04061007; -imm32 r4, 0x05bc2569; -imm32 r5, 0x0635300b; -imm32 r6, 0x070c200d; -imm32 r7, 0x088e100f; -R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L; -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.L ), A0 -= R2.H * R3.L; -R3 = A1.w; -R4.H = ( A1 -= R4.L * R5.L ), A0 += R4.H * R5.H; -R5 = A1.w; -R6.H = ( A1 += R6.L * R7.L ), A0 -= R6.L * R7.H; -R7 = A1.w; -CHECKREG r0, 0x06392ABD; -CHECKREG r1, 0x063908F2; -CHECKREG r2, 0x056A0679; -CHECKREG r3, 0x05698E54; -CHECKREG r4, 0xF75F2569; -CHECKREG r5, 0xF75EF74E; -CHECKREG r6, 0xFB64200D; -CHECKREG r7, 0xFB6458D4; - -imm32 r0, 0x03545abd; -imm32 r1, 0x31bcfec7; -imm32 r2, 0x11145679; -imm32 r3, 0x00010007; -imm32 r4, 0xefbc1569; -imm32 r5, 0x1235010b; -imm32 r6, 0x000c001d; -imm32 r7, 0x678e0001; -R4.H = ( A1 += R1.L * R0.H ), A0 -= R1.L * R0.L; -R5 = A1.w; -R0.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L; -R1 = A1.w; -R2.H = ( A1 -= R4.L * R5.H ), A0 += R4.H * R5.H; -R3 = A1.w; -R6.H = ( A1 += R6.L * R7.H ), A0 -= R6.L * R7.H; -R7 = A1.w; -CHECKREG r0, 0xFB5C5ABD; -CHECKREG r1, 0xFB5B887A; -CHECKREG r2, 0xFC225679; -CHECKREG r3, 0xFC223F02; -CHECKREG r4, 0xFB5C1569; -CHECKREG r5, 0xFB5C356C; -CHECKREG r6, 0xFC3A001D; -CHECKREG r7, 0xFC39B52E; - -imm32 r0, 0x83545abd; -imm32 r1, 0xa8bcfec7; -imm32 r2, 0xa1845679; -imm32 r3, 0x00080007; -imm32 r4, 0xefbc8569; -imm32 r5, 0x1235080b; -imm32 r6, 0x000c008d; -imm32 r7, 0x678e0008; -R6.H = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L; -R7 = A1.w; -R2.H = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L; -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ), A0 -= R4.H * R5.H; -R5 = A1.w; -R0.H = ( A1 += R6.H * R7.L ), A0 -= R6.L * R7.H; -R1 = A1.w; -CHECKREG r0, 0xF9745ABD; -CHECKREG r1, 0xF9741604; -CHECKREG r2, 0xBE625679; -CHECKREG r3, 0xBE62358E; -CHECKREG r4, 0xFEFA8569; -CHECKREG r5, 0xFEFA5A28; -CHECKREG r6, 0xBE5D008D; -CHECKREG r7, 0xBE5D0AC6; - -imm32 r0, 0xc3545abd; -imm32 r1, 0xacbcfec7; -imm32 r2, 0xa1c45679; -imm32 r3, 0x000c0007; -imm32 r4, 0xefbcc569; -imm32 r5, 0x12350c0b; -imm32 r6, 0x000c00cd; -imm32 r7, 0x678e000c; -R6.H = ( A1 += R1.H * R0.H ), A0 -= R1.L * R0.L; -R7 = A1.w; -R0.H = ( A1 = R2.H * R3.H ), A0 -= R2.H * R3.L; -R1 = A1.w; -R4.H = ( A1 -= R4.H * R5.H ), A0 += R4.H * R5.H; -R5 = A1.w; -R2.H = ( A1 -= R6.H * R7.H ), A0 += R6.L * R7.H; -R3 = A1.w; -CHECKREG r0, 0xFFF75ABD; -CHECKREG r1, 0xFFF72A60; -CHECKREG r2, 0xF9D05679; -CHECKREG r3, 0xF9D00540; -CHECKREG r4, 0x0247C569; -CHECKREG r5, 0x02477688; -CHECKREG r6, 0x20EC00CD; -CHECKREG r7, 0x20EBD964; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_i.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_i.s deleted file mode 100644 index de42387..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_i.s +++ /dev/null @@ -1,273 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a1_i/c_dsp32mac_dr_a1_i.dsp -// Spec Reference: dsp32mac dr a1 i (signed int) -# mach: bfin - -.include "testutils.inc" - start - - - -A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0xa3545abd; -imm32 r1, 0xbdbcfec7; -imm32 r2, 0xc1248679; -imm32 r3, 0xd0069007; -imm32 r4, 0xefbc4569; -imm32 r5, 0xcd35500b; -imm32 r6, 0xe00c800d; -imm32 r7, 0xf78e900f; -R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (IS); -R1 = A1.w; -R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS); -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (IS); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (IS); -R7 = A1.w; -CHECKREG r0, 0x80005ABD; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0x7FFF8679; -CHECKREG r3, 0x16C676D6; -CHECKREG r4, 0x80004569; -CHECKREG r5, 0xFAEA0D14; -CHECKREG r6, 0x7FFF800D; -CHECKREG r7, 0x010DDAA8; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x63548abd; -imm32 r1, 0x7dbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0xb0069007; -imm32 r4, 0xcfbc4569; -imm32 r5, 0xFFFF8000; -imm32 r6, 0x7FFF800D; -imm32 r7, 0x00007FFF; -R0.H = ( A1 = R1.L * R0.L ) (IS); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (IS); -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ) (IS); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ) (IS); -R7 = A1.w; -CHECKREG r0, 0x7FFF8ABD; -CHECKREG r1, 0x008F5EEB; -CHECKREG r2, 0x80005679; -CHECKREG r3, 0xE58B95C1; -CHECKREG r4, 0x7FFF4569; -CHECKREG r5, 0x18220000; -CHECKREG r6, 0x0000800D; -CHECKREG r7, 0x00000000; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x5354babd; -imm32 r1, 0x6dbcdec7; -imm32 r2, 0x7124e679; -imm32 r3, 0x80067007; -imm32 r4, 0x9fbc4569; -imm32 r5, 0xa235900b; -imm32 r6, 0xb00c300d; -imm32 r7, 0xc78ea00f; - R0.H = A1 , A0 = R1.L * R0.L (IS); -R1 = A1.w; - R2.H = A1 , A0 = R2.H * R3.L (IS); -R3 = A1.w; - R4.H = A1 , A0 = R4.H * R5.H (IS); -R5 = A1.w; - R6.H = A1 , A0 += R6.L * R7.H (IS); -R7 = A1.w; -CHECKREG r0, 0x0000BABD; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x0000E679; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00004569; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x0000300D; -CHECKREG r7, 0x00000000; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0x33545abd; -imm32 r1, 0x5dbcfec7; -imm32 r2, 0x71245679; -imm32 r3, 0x90060007; -imm32 r4, 0xafbc4569; -imm32 r5, 0xd235900b; -imm32 r6, 0xc00ca00d; -imm32 r7, 0x678ed00f; -R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (IS); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (M), A0 = R2.H * R3.L (IS); -R3 = A0.w; -R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (IS); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H (IS); -R7 = A0.w; -CHECKREG r0, 0x80005ABD; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0x7FFF5679; -CHECKREG r3, 0x000317FC; -CHECKREG r4, 0x7FFF4569; -CHECKREG r5, 0x030D72D5; -CHECKREG r6, 0x8000A00D; -CHECKREG r7, 0xE78B9C22; - -// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) -imm32 r0, 0x83545abd; -imm32 r1, 0xa8bcfec7; -imm32 r2, 0xc1845679; -imm32 r3, 0x1c080007; -imm32 r4, 0xe1cc8569; -imm32 r5, 0x921c080b; -imm32 r6, 0x7901908d; -imm32 r7, 0x679e9008; -R0.H = ( A1 += R1.L * R0.L ) (M,IS); -R1 = A1.w; -R2.H = ( A1 = R2.L * R3.H ) (M,IS); -R3 = A1.w; -R4.H = ( A1 += R4.H * R5.L ) (M,IS); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ) (M,IS); -R7 = A1.w; -CHECKREG r0, 0x80005ABD; -CHECKREG r1, 0xE5B26993; -CHECKREG r2, 0x7FFF5679; -CHECKREG r3, 0x0977EFC8; -CHECKREG r4, 0x7FFF8569; -CHECKREG r5, 0x0885038C; -CHECKREG r6, 0x7FFF908D; -CHECKREG r7, 0x30FA159E; - -imm32 r0, 0x03545abd; -imm32 r1, 0x1dbcfec7; -imm32 r2, 0x21248679; -imm32 r3, 0x30069007; -imm32 r4, 0x4fbc4569; -imm32 r5, 0x5d35500b; -imm32 r6, 0x600c800d; -imm32 r7, 0x778e900f; -R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L (IS); -R1 = A1.w; -R2.H = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L (IS); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IS); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ), A0 -= R6.L * R7.H (IS); -R7 = A1.w; -CHECKREG r0, 0x7FFF5ABD; -CHECKREG r1, 0x316906B3; -CHECKREG r2, 0x80008679; -CHECKREG r3, 0xE933D6D6; -CHECKREG r4, 0x80004569; -CHECKREG r5, 0xD045A9C2; -CHECKREG r6, 0x8000800D; -CHECKREG r7, 0xA36ACF1A; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x63540abd; -imm32 r1, 0x7dbc1ec7; -imm32 r2, 0xa1242679; -imm32 r3, 0x40063007; -imm32 r4, 0x1fbc4569; -imm32 r5, 0x2FFF4000; -imm32 r6, 0x7FFF800D; -imm32 r7, 0x10007FFF; -R0.H = ( A1 -= R1.L * R0.L ) (IS); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ) (IS); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ) (IS); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ) (IS); -R7 = A1.w; -CHECKREG r0, 0x80000ABD; -CHECKREG r1, 0xA220502F; -CHECKREG r2, 0x80002679; -CHECKREG r3, 0x98812959; -CHECKREG r4, 0x80004569; -CHECKREG r5, 0x90922959; -CHECKREG r6, 0x8000800D; -CHECKREG r7, 0x88923959; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x2354babd; -imm32 r1, 0x3dbcdec7; -imm32 r2, 0x7424e679; -imm32 r3, 0x80067007; -imm32 r4, 0x95bc4569; -imm32 r5, 0xa235900b; -imm32 r6, 0xb06c300d; -imm32 r7, 0xc787a00f; - R0.H = A1 , A0 -= R1.L * R0.L (IS); -R1 = A1.w; - R2.H = A1 , A0 -= R2.H * R3.L (IS); -R3 = A1.w; - R4.H = A1 , A0 -= R4.H * R5.H (IS); -R5 = A1.w; - R6.H = A1 , A0 -= R6.L * R7.H (IS); -R7 = A1.w; -CHECKREG r0, 0x8000BABD; -CHECKREG r1, 0x88923959; -CHECKREG r2, 0x8000E679; -CHECKREG r3, 0x88923959; -CHECKREG r4, 0x80004569; -CHECKREG r5, 0x88923959; -CHECKREG r6, 0x8000300D; -CHECKREG r7, 0x88923959; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0x33545abd; -imm32 r1, 0x5dbcfec7; -imm32 r2, 0x71245679; -imm32 r3, 0x90060007; -imm32 r4, 0xafbc4569; -imm32 r5, 0xd235900b; -imm32 r6, 0xc00ca00d; -imm32 r7, 0x678ed00f; -R0.H = ( A1 -= R1.L * R0.L ) (M), A0 += R1.L * R0.L (IS); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (IS); -R3 = A0.w; -R4.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H (IS); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ) (M), A0 += R6.L * R7.H (IS); -R7 = A0.w; -CHECKREG r0, 0x80005ABD; -CHECKREG r1, 0x89012A6E; -CHECKREG r2, 0x80005679; -CHECKREG r3, 0x000317FC; -CHECKREG r4, 0x80004569; -CHECKREG r5, 0x2B3160AC; -CHECKREG r6, 0x8000A00D; -CHECKREG r7, 0xCAD78046; - -// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) -imm32 r0, 0x83545abd; -imm32 r1, 0xa8bcfec7; -imm32 r2, 0xc1845679; -imm32 r3, 0x1c080007; -imm32 r4, 0xe1cc8569; -imm32 r5, 0x921c080b; -imm32 r6, 0x7901908d; -imm32 r7, 0x679e9008; -R0.H = ( A1 -= R1.L * R0.L ) (M,IS); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ) (M,IS); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ) (M,IS); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ) (M,IS); -R7 = A1.w; -CHECKREG r0, 0x80005ABD; -CHECKREG r1, 0x457EF719; -CHECKREG r2, 0x80005679; -CHECKREG r3, 0x3C070751; -CHECKREG r4, 0x80008569; -CHECKREG r5, 0x3CF9F38D; -CHECKREG r6, 0x8000908D; -CHECKREG r7, 0x0BFFDDEF; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_ih.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_ih.s deleted file mode 100644 index ae20990..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_ih.s +++ /dev/null @@ -1,145 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a1_ih/c_dsp32mac_dr_a1_ih.dsp -// Spec Reference: dsp32mac dr_a1 ih (int multiplication with word extraction) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0x93545abd; -imm32 r1, 0x1dbcfec7; -imm32 r2, 0x52248679; -imm32 r3, 0xd6069007; -imm32 r4, 0xef7c4569; -imm32 r5, 0xcd38500b; -imm32 r6, 0xe00c900d; -imm32 r7, 0xf78e990f; -R0.H = ( A1 = R1.L * R0.L ), A0 -= R1.L * R0.L (IH); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ), A0 -= R2.H * R3.L (IH); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IH); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ), A0 = R6.L * R7.H (IH); -R7 = A1.w; -CHECKREG r0, 0xFF915ABD; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0x137E8679; -CHECKREG r3, 0x137E5BC1; -CHECKREG r4, 0x18A84569; -CHECKREG r5, 0x18A8516D; -CHECKREG r6, 0x010E900D; -CHECKREG r7, 0x010DDAA8; - -// The result accumulated in A1, and stored to a reg half (MNOP) -imm32 r0, 0x83548abd; -imm32 r1, 0x76bcfec7; -imm32 r2, 0xa1745679; -imm32 r3, 0xb0269007; -imm32 r4, 0xcfb34569; -imm32 r5, 0xd235600b; -imm32 r6, 0xe00ca70d; -imm32 r7, 0x678e708f; -R0.H = ( A1 -= R1.L * R0.L ) (IH); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (IH); -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ) (IH); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ) (IH); -R7 = A1.w; -CHECKREG r0, 0x007E8ABD; -CHECKREG r1, 0x007E7BBD; -CHECKREG r2, 0xE5865679; -CHECKREG r3, 0xE58581B3; -CHECKREG r4, 0xEDE14569; -CHECKREG r5, 0xEDE10CB1; -CHECKREG r6, 0xFACEA70D; -CHECKREG r7, 0xFACDF209; - -// The result accumulated in A1 , and stored to a reg half (MNOP) -imm32 r0, 0x5354babd; -imm32 r1, 0x9dbcdec7; -imm32 r2, 0x7724e679; -imm32 r3, 0x80567007; -imm32 r4, 0x9fb34569; -imm32 r5, 0xa235200b; -imm32 r6, 0xb00c100d; -imm32 r7, 0x9876a10f; - R0.H = A1 , A0 = R1.L * R0.L (IH); -R1 = A1.w; - R2.H = A1 , A0 += R2.H * R3.L (IH); -R3 = A1.w; - R4.H = A1 , A0 -= R4.H * R5.H (IH); -R5 = A1.w; - R6.H = A1 , A0 += R6.L * R7.H (IH); -R7 = A1.w; -CHECKREG r0, 0xFACEBABD; -CHECKREG r1, 0xFACDF209; -CHECKREG r2, 0xFACEE679; -CHECKREG r3, 0xFACDF209; -CHECKREG r4, 0xFACE4569; -CHECKREG r5, 0xFACDF209; -CHECKREG r6, 0xFACE100D; -CHECKREG r7, 0xFACDF209; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0x33545abd; -imm32 r1, 0x9dbcfec7; -imm32 r2, 0x81245679; -imm32 r3, 0x97060007; -imm32 r4, 0xaf6c4569; -imm32 r5, 0xd235900b; -imm32 r6, 0xc00c400d; -imm32 r7, 0x678ed30f; -R0.H = ( A1 = R1.L * R0.L ) (M), A0 -= R1.L * R0.L (IH); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (M), A0 += R2.H * R3.L (IH); -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ) (M), A0 += R4.H * R5.H (IH); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ) (M), A0 -= R6.L * R7.H (IH); -R7 = A1.w; -CHECKREG r0, 0xFF915ABD; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0x32945679; -CHECKREG r3, 0x329474C1; -CHECKREG r4, 0xD2A94569; -CHECKREG r5, 0xD2A949A4; -CHECKREG r6, 0xE621400D; -CHECKREG r7, 0xE6215AA8; - -// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) -imm32 r0, 0x92005ABD; -imm32 r1, 0x09300000; -imm32 r2, 0x56749679; -imm32 r3, 0x30A95000; -imm32 r4, 0xa0009669; -imm32 r5, 0x01000970; -imm32 r6, 0xdf45609D; -imm32 r7, 0x12345679; -R0.H = ( A1 -= R1.L * R0.L ) (M,IH); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (M,IH); -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ) (M,IH); -R5 = A1.w; -R6.H = ( A1 += R6.H * R7.H ) (M,IH); -R7 = A1.w; -CHECKREG r0, 0xE6215ABD; -CHECKREG r1, 0xE6215AA8; -CHECKREG r2, 0xD2129679; -CHECKREG r3, 0xD2126089; -CHECKREG r4, 0xFC769669; -CHECKREG r5, 0xFC760000; -CHECKREG r6, 0xFA22609D; -CHECKREG r7, 0xFA223404; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_is.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_is.s deleted file mode 100644 index 2d97468..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_is.s +++ /dev/null @@ -1,145 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a1_is/c_dsp32mac_dr_a1_is.dsp -// Spec Reference: dsp32mac dr_a1 is ((scale by 2 signed int) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0xa3545abd; -imm32 r1, 0xbdbcfec7; -imm32 r2, 0xc1248679; -imm32 r3, 0xd0069007; -imm32 r4, 0xefbc4569; -imm32 r5, 0xcd35500b; -imm32 r6, 0xe00c800d; -imm32 r7, 0xf78e900f; -R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (ISS2); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (ISS2); -R3 = A1.w; -R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (ISS2); -R5 = A1.w; -R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (ISS2); -R7 = A1.w; -CHECKREG r0, 0x80005ABD; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0x80008679; -CHECKREG r3, 0xE8CA9815; -CHECKREG r4, 0x80004569; -CHECKREG r5, 0xE3B4A529; -CHECKREG r6, 0x8000800D; -CHECKREG r7, 0xE4C27FD1; - -// The result accumulated in A1, and stored to a reg half (MNOP) -imm32 r0, 0x63548abd; -imm32 r1, 0x7dbcfec7; -imm32 r2, 0xC5885679; -imm32 r3, 0xC5880000; -imm32 r4, 0xcfbc4569; -imm32 r5, 0xd235c00b; -imm32 r6, 0xe00ca00d; -imm32 r7, 0x678e700f; -R0.H = ( A1 = R1.L * R0.L ) (ISS2); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (ISS2); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ) (ISS2); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ) (ISS2); -R7 = A1.w; -CHECKREG r0, 0x7FFF8ABD; -CHECKREG r1, 0x008F5EEB; -CHECKREG r2, 0x80005679; -CHECKREG r3, 0xECCF6C33; -CHECKREG r4, 0x80004569; -CHECKREG r5, 0xE0C07F1F; -CHECKREG r6, 0x8000A00D; -CHECKREG r7, 0xEDAD6477; - -// The result accumulated in A1 , and stored to a reg half (MNOP) -imm32 r0, 0x5354babd; -imm32 r1, 0x6dbcdec7; -imm32 r2, 0x7124e679; -imm32 r3, 0x80067007; -imm32 r4, 0x9fbc4569; -imm32 r5, 0xa235900b; -imm32 r6, 0xb00c300d; -imm32 r7, 0xc78ea00f; - R0.H = A1 , A0 -= R1.L * R0.L (ISS2); -R1 = A1.w; - R2.H = A1 , A0 += R2.H * R3.L (ISS2); -R3 = A1.w; - R4.H = A1 , A0 -= R4.H * R5.H (ISS2); -R5 = A1.w; - R6.H = A1 , A0 = R6.L * R7.H (ISS2); -R7 = A1.w; -CHECKREG r0, 0x8000BABD; -CHECKREG r1, 0xEDAD6477; -CHECKREG r2, 0x8000E679; -CHECKREG r3, 0xEDAD6477; -CHECKREG r4, 0x80004569; -CHECKREG r5, 0xEDAD6477; -CHECKREG r6, 0x8000300D; -CHECKREG r7, 0xEDAD6477; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0x33545abd; -imm32 r1, 0x5dbcfec7; -imm32 r2, 0x71245679; -imm32 r3, 0x90060007; -imm32 r4, 0xafbc4569; -imm32 r5, 0xd235900b; -imm32 r6, 0xc00ca00d; -imm32 r7, 0x678ed00f; -R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (ISS2); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (ISS2); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (ISS2); -R5 = A1.w; -R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (ISS2); -R7 = A1.w; -CHECKREG r0, 0x80005ABD; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0x7FFF5679; -CHECKREG r3, 0x303725C1; -CHECKREG r4, 0x7FFF4569; -CHECKREG r5, 0x5D60D8AD; -CHECKREG r6, 0x7FFFA00D; -CHECKREG r7, 0x43823355; - -// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) -imm32 r0, 0x92005ABD; -imm32 r1, 0x09300000; -imm32 r2, 0x56749679; -imm32 r3, 0x30A95000; -imm32 r4, 0xa0009669; -imm32 r5, 0x01000970; -imm32 r6, 0xdf45609D; -imm32 r7, 0x12345679; -R0.H = ( A1 += R1.L * R0.L ) (M,ISS2); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ) (M,ISS2); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ) (M,ISS2); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ) (M,ISS2); -R7 = A1.w; -CHECKREG r0, 0x7FFF5ABD; -CHECKREG r1, 0x43823355; -CHECKREG r2, 0x7FFF9679; -CHECKREG r3, 0x57912D74; -CHECKREG r4, 0x7FFF9669; -CHECKREG r5, 0x5B1B2D74; -CHECKREG r6, 0x8000609D; -CHECKREG r7, 0xFDAC3404; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_iu.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_iu.s deleted file mode 100644 index 8f36ac3..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_iu.s +++ /dev/null @@ -1,145 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a1_iu/c_dsp32mac_dr_a1_iu.dsp -// Spec Reference: dsp32mac dr_a1 iu (unsigned integer) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0x93545abd; -imm32 r1, 0x7890afc7; -imm32 r2, 0x52248679; -imm32 r3, 0xd5069007; -imm32 r4, 0xef5c4569; -imm32 r5, 0xcd35500b; -imm32 r6, 0xe00c500d; -imm32 r7, 0xf78e950f; -R0.H = ( A1 = R1.L * R0.L ), A0 += R1.L * R0.L (IU); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ), A0 = R2.H * R3.L (IU); -R3 = A1.w; -R4.H = ( A1 += R4.H * R5.L ), A0 += R4.H * R5.H (IU); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ), A0 -= R6.L * R7.H (IU); -R7 = A1.w; -CHECKREG r0, 0xFFFF5ABD; -CHECKREG r1, 0x3E4DBBEB; -CHECKREG r2, 0xFFFF8679; -CHECKREG r3, 0xAE338FC1; -CHECKREG r4, 0xFFFF4569; -CHECKREG r5, 0xF90A98B5; -CHECKREG r6, 0xFFFF500D; -CHECKREG r7, 0x2062BE0D; - -// The result accumulated in A1, and stored to a reg half (MNOP) -imm32 r0, 0xd3548abd; -imm32 r1, 0x9dbcfec7; -imm32 r2, 0xa9d45679; -imm32 r3, 0xb09d9007; -imm32 r4, 0xcfb9d569; -imm32 r5, 0xd2359d0b; -imm32 r6, 0xe00ca90d; -imm32 r7, 0x678e709f; -R0.H = ( A1 += R1.L * R0.L ) (IU); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ) (IU); -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ) (IU); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ) (IU); -R7 = A1.w; -CHECKREG r0, 0xFFFF8ABD; -CHECKREG r1, 0xAA761CF8; -CHECKREG r2, 0xFFFF5679; -CHECKREG r3, 0x6ECDE4C3; -CHECKREG r4, 0xFFFFD569; -CHECKREG r5, 0x7F6D61F3; -CHECKREG r6, 0xFFFFA90D; -CHECKREG r7, 0x24CC474B; - -// The result accumulated in A1 , and stored to a reg half (MNOP) -imm32 r0, 0xa354babd; -imm32 r1, 0x9abcdec7; -imm32 r2, 0x77a4e679; -imm32 r3, 0x805a7007; -imm32 r4, 0x9fb3a569; -imm32 r5, 0xa2352a0b; -imm32 r6, 0xb00c10ad; -imm32 r7, 0x9876a10a; - R0.H = A1 , A0 -= R1.L * R0.L (IU); -R1 = A1.w; - R2.H = A1 , A0 += R2.H * R3.L (IU); -R3 = A1.w; - R4.H = A1 , A0 = R4.H * R5.H (IU); -R5 = A1.w; - R6.H = A1 , A0 -= R6.L * R7.H (IU); -R7 = A1.w; -CHECKREG r0, 0xFFFFBABD; -CHECKREG r1, 0x24CC474B; -CHECKREG r2, 0xFFFFE679; -CHECKREG r3, 0x24CC474B; -CHECKREG r4, 0xFFFFA569; -CHECKREG r5, 0x24CC474B; -CHECKREG r6, 0xFFFF10AD; -CHECKREG r7, 0x24CC474B; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0x33545abd; -imm32 r1, 0x9dbcfec7; -imm32 r2, 0x81245679; -imm32 r3, 0x97060007; -imm32 r4, 0xaf6c4569; -imm32 r5, 0xd235900b; -imm32 r6, 0xc00c400d; -imm32 r7, 0x678ed30f; -R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (IU); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (IU); -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ) (M), A0 -= R4.H * R5.H (IU); -R5 = A1.w; -R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (IU); -R7 = A1.w; -CHECKREG r0, 0x80005ABD; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0x80005679; -CHECKREG r3, 0xCC8DA915; -CHECKREG r4, 0x80004569; -CHECKREG r5, 0xD2A949A4; -CHECKREG r6, 0x8000400D; -CHECKREG r7, 0xB8CAA44C; - -// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) -imm32 r0, 0xe2005ABD; -imm32 r1, 0x0e300000; -imm32 r2, 0x56e49679; -imm32 r3, 0x30Ae5000; -imm32 r4, 0xa000e669; -imm32 r5, 0x01000e70; -imm32 r6, 0xdf4560eD; -imm32 r7, 0x1234567e; -R0.H = ( A1 -= R1.L * R0.L ) (M,IU); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (M,IU); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ) (M,IU); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ) (M,IU); -R7 = A1.w; -CHECKREG r0, 0x80005ABD; -CHECKREG r1, 0xB8CAA44C; -CHECKREG r2, 0x80009679; -CHECKREG r3, 0xA4B99A8A; -CHECKREG r4, 0x8000E669; -CHECKREG r5, 0xAA239A8A; -CHECKREG r6, 0x800060ED; -CHECKREG r7, 0xAC776686; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_m.s deleted file mode 100644 index b44d5e6..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_m.s +++ /dev/null @@ -1,206 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a1_m/c_dsp32mac_dr_a1_m.dsp -// Spec Reference: dsp32mac dr a1 m -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0xab235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acefdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246700f; - -A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; -R0.H = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L; -R1 = A1.w; -R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L; -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H; -R5 = A1.w; -R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H; -R7 = A1.w; -CHECKREG r0, 0xFF225ABD; -CHECKREG r1, 0xFF221DD6; -CHECKREG r2, 0x00045679; -CHECKREG r3, 0x00040DAC; -CHECKREG r4, 0xFFFF4569; -CHECKREG r5, 0xFFFE9A28; -CHECKREG r6, 0x0008000D; -CHECKREG r7, 0x00084F78; - -// The result accumulated in A1, and stored to a reg half (MNOP) -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; -R0.H = ( A1 += R1.L * R0.L ); -R1 = A1.w; -R2.H = ( A1 = R2.L * R3.H ); -R3 = A1.w; -R4.H = ( A1 += R4.H * R5.L ); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ); -R7 = A1.w; -CHECKREG r0, 0xFF2A5ABD; -CHECKREG r1, 0xFF2A6D4E; -CHECKREG r2, 0x00045679; -CHECKREG r3, 0x00040DAC; -CHECKREG r4, 0x00034569; -CHECKREG r5, 0x0002A7D4; -CHECKREG r6, 0x000A000D; -CHECKREG r7, 0x0009B550; - -// The result accumulated in A1 , and stored to a reg half (MNOP) -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; - R0.H = A1 , A0 += R1.L * R0.L; -R1 = A1.w; - R2.H = A1 , A0 = R2.H * R3.L; -R3 = A1.w; - R4.H = A1 , A0 = R4.H * R5.H; -R5 = A1.w; - R6.H = A1 , A0 += R6.L * R7.H; -R7 = A1.w; -CHECKREG r0, 0x000A5ABD; -CHECKREG r1, 0x0009B550; -CHECKREG r2, 0x000A5679; -CHECKREG r3, 0x0009B550; -CHECKREG r4, 0x000A4569; -CHECKREG r5, 0x0009B550; -CHECKREG r6, 0x000A000D; -CHECKREG r7, 0x0009B550; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; -R4.H = ( A1 += R1.L * R0.L ) (M), A0 = R1.L * R0.L; -R5 = A1.w; -R6.H = ( A1 = R2.L * R3.H ) (M), A0 += R2.H * R3.L; -R7 = A1.w; -R0.H = ( A1 = R4.H * R5.L ) (M), A0 = R4.H * R5.H; -R1 = A1.w; -R2.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H; -R3 = A1.w; -CHECKREG r0, 0xFFB35ABD; -CHECKREG r1, 0xFFB294B9; -CHECKREG r2, 0x00005679; -CHECKREG r3, 0x00000004; -CHECKREG r4, 0xFF9B4569; -CHECKREG r5, 0xFF9AC43B; -CHECKREG r6, 0x0002000D; - -CHECKREG r7, 0x000206D6; - -// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) -imm32 r0, 0x83545abd; -imm32 r1, 0xa8bcfec7; -imm32 r2, 0xc1845679; -imm32 r3, 0x1c080007; -imm32 r4, 0xe1cc8569; -imm32 r5, 0x121c080b; -imm32 r6, 0x7001008d; -imm32 r7, 0x678e1008; -R6.H = ( A1 += R1.L * R0.L ) (M); -R7 = A1.w; -R2.H = ( A1 = R2.L * R3.H ) (M); -R3 = A1.w; -R0.H = ( A1 += R4.H * R5.L ) (M); -R1 = A1.w; -R4.H = ( A1 = R6.H * R7.H ) (M); -R5 = A1.w; -CHECKREG r0, 0x08855ABD; -CHECKREG r1, 0x0885038C; -CHECKREG r2, 0x09785679; -CHECKREG r3, 0x0977EFC8; -CHECKREG r4, 0xFF918569; -CHECKREG r5, 0xFF913021; -CHECKREG r6, 0xFF91008D; -CHECKREG r7, 0xFF910EEF; - -imm32 r0, 0x03545abd; -imm32 r1, 0xa0bcfec7; -imm32 r2, 0xa1045679; -imm32 r3, 0x00000007; -imm32 r4, 0xefbc0569; -imm32 r5, 0x1235100b; -imm32 r6, 0x000c020d; -imm32 r7, 0x678e003f; -R4.H = ( A1 -= R1.L * R0.L ) (M), A0 -= R1.L * R0.L; -R5 = A1.w; -R6.H = ( A1 -= R2.L * R3.H ) (M), A0 += R2.H * R3.L; -R7 = A1.w; -R0.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H; -R1 = A1.w; -R2.H = ( A1 -= R6.H * R7.H ) (M), A0 -= R6.L * R7.H; -R3 = A1.w; -CHECKREG r0, 0x00005ABD; -CHECKREG r1, 0x00002136; -CHECKREG r2, 0x00005679; -CHECKREG r3, 0x00002136; -CHECKREG r4, 0x00000569; -CHECKREG r5, 0x00002136; -CHECKREG r6, 0x0000020D; -CHECKREG r7, 0x00002136; - -// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) -imm32 r0, 0x83545abd; -imm32 r1, 0xa8bcfec7; -imm32 r2, 0xc1845679; -imm32 r3, 0x1c080007; -imm32 r4, 0xe1cc8569; -imm32 r5, 0x121c080b; -imm32 r6, 0x7001008d; -imm32 r7, 0x678e1008; -R6.H = ( A1 -= R1.L * R0.L ) (M); -R7 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ) (M); -R3 = A1.w; -R0.H = ( A1 -= R4.H * R5.L ) (M); -R1 = A1.w; -R4.H = ( A1 -= R6.H * R7.H ) (M); -R5 = A1.w; -CHECKREG r0, 0xF7EA5ABD; -CHECKREG r1, 0xF7EA0EBF; -CHECKREG r2, 0xF6F75679; -CHECKREG r3, 0xF6F72283; -CHECKREG r4, 0xF7EA8569; -CHECKREG r5, 0xF7E9DE9E; -CHECKREG r6, 0x006F008D; -CHECKREG r7, 0x006F124B; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_s.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_s.s deleted file mode 100644 index 1059673..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_s.s +++ /dev/null @@ -1,145 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a1_s/c_dsp32mac_dr_a1_s.dsp -// Spec Reference: dsp32mac dr_a1 s (scale by 2 signed fraction with round) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0xa3545abd; -imm32 r1, 0xbabcfec7; -imm32 r2, 0xc1a48679; -imm32 r3, 0xd00a9007; -imm32 r4, 0xefbca569; -imm32 r5, 0xcd355a0b; -imm32 r6, 0xe00c80ad; -imm32 r7, 0xf78e900a; -R0.H = ( A1 -= R1.L * R0.L ), A0 += R1.L * R0.L (S2RND); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ), A0 -= R2.H * R3.L (S2RND); -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ), A0 = R4.H * R5.H (S2RND); -R5 = A1.w; -R6.H = ( A1 += R6.H * R7.H ), A0 -= R6.L * R7.H (S2RND); -R7 = A1.w; -CHECKREG r0, 0x01BC5ABD; -CHECKREG r1, 0x00DDE22A; -CHECKREG r2, 0x5CCE8679; -CHECKREG r3, 0x2E67039E; -CHECKREG r4, 0xE91EA569; -CHECKREG r5, 0xF48ECA28; -CHECKREG r6, 0xED5580AD; -CHECKREG r7, 0xF6AA7F78; - -// The result accumulated in A1, and stored to a reg half (MNOP) -imm32 r0, 0x63bb8abd; -imm32 r1, 0xbdbcfec7; -imm32 r2, 0xab245679; -imm32 r3, 0xb0b69007; -imm32 r4, 0xcfbb4569; -imm32 r5, 0xd235b00b; -imm32 r6, 0xe00cab0d; -imm32 r7, 0x678e70bf; -R0.H = ( A1 += R1.L * R0.L ) (S2RND); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ) (S2RND); -R3 = A1.w; -R4.H = ( A1 += R4.H * R5.L ) (S2RND); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ) (S2RND); -R7 = A1.w; -CHECKREG r0, 0xEF928ABD; -CHECKREG r1, 0xF7C93D4E; -CHECKREG r2, 0x5AB45679; -CHECKREG r3, 0x2D59E942; -CHECKREG r4, 0x7FFF4569; -CHECKREG r5, 0x4B80E354; -CHECKREG r6, 0xCC4CAB0D; -CHECKREG r7, 0xE6263550; - -// The result accumulated in A1 , and stored to a reg half (MNOP) -imm32 r0, 0x5c54babd; -imm32 r1, 0x6dccdec7; -imm32 r2, 0xc12ce679; -imm32 r3, 0x8c06c007; -imm32 r4, 0x9fcc4c69; -imm32 r5, 0xa23c90cb; -imm32 r6, 0xb00cc00c; -imm32 r7, 0xc78eac0f; - R0.H = A1 , A0 -= R1.L * R0.L (S2RND); -R1 = A1.w; - R2.H = A1 , A0 += R2.H * R3.L (S2RND); -R3 = A1.w; - R4.H = A1 , A0 = R4.H * R5.H (S2RND); -R5 = A1.w; - R6.H = A1 , A0 += R6.L * R7.H (S2RND); -R7 = A1.w; -CHECKREG r0, 0xCC4CBABD; -CHECKREG r1, 0xE6263550; -CHECKREG r2, 0xCC4CE679; -CHECKREG r3, 0xE6263550; -CHECKREG r4, 0xCC4C4C69; -CHECKREG r5, 0xE6263550; -CHECKREG r6, 0xCC4CC00C; -CHECKREG r7, 0xE6263550; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0x3d545abd; -imm32 r1, 0x5ddcfec7; -imm32 r2, 0x712d5679; -imm32 r3, 0x9006d007; -imm32 r4, 0xafbc4d69; -imm32 r5, 0xd23590db; -imm32 r6, 0xd00ca00d; -imm32 r7, 0x6d8ed00f; -R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (S2RND); -R1 = A1.w; -R2.H = ( A1 = R2.L * R3.H ) (M), A0 -= R2.H * R3.L (S2RND); -R3 = A1.w; -R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (S2RND); -R5 = A1.w; -R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (S2RND); -R7 = A1.w; -CHECKREG r0, 0xFF225ABD; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0x614C5679; -CHECKREG r3, 0x30A616D6; -CHECKREG r4, 0x06764D69; -CHECKREG r5, 0x033B2CAA; -CHECKREG r6, 0xDD6BA00D; -CHECKREG r7, 0xEEB5AF52; - -// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) -imm32 r0, 0x83e45abd; -imm32 r1, 0xe8befec7; -imm32 r2, 0xce84e679; -imm32 r3, 0x1ce80e07; -imm32 r4, 0xe1ce85e9; -imm32 r5, 0x921ce80e; -imm32 r6, 0x79019e8d; -imm32 r7, 0x679e90e8; -R0.H = ( A1 += R1.L * R0.L ) (M,S2RND); -R1 = A1.w; -R2.H = ( A1 = R2.L * R3.H ) (M,S2RND); -R3 = A1.w; -R4.H = ( A1 += R4.H * R5.L ) (M,S2RND); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ) (M,S2RND); -R7 = A1.w; -CHECKREG r0, 0xDC8D5ABD; -CHECKREG r1, 0xEE46BE3D; -CHECKREG r2, 0xFA3CE679; -CHECKREG r3, 0xFD1E19A8; -CHECKREG r4, 0xC37E85E9; -CHECKREG r5, 0xE1BF22EC; -CHECKREG r6, 0x80009E8D; -CHECKREG r7, 0xB0C50D4E; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_t.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_t.s deleted file mode 100644 index 7dc3925..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_t.s +++ /dev/null @@ -1,274 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a1_t/c_dsp32mac_dr_a1_t.dsp -// Spec Reference: dsp32mac dr a1 t (truncation) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0xa3545abd; -imm32 r1, 0xbdbcfec7; -imm32 r2, 0xc1248679; -imm32 r3, 0xd0069007; -imm32 r4, 0xefbc4569; -imm32 r5, 0xcd35500b; -imm32 r6, 0xe00c800d; -imm32 r7, 0xf78e900f; -R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (T); -R1 = A1.w; -R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (T); -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (T); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (T); -R7 = A1.w; -CHECKREG r0, 0xFF225ABD; -CHECKREG r1, 0xFF221DD6; -CHECKREG r2, 0x2D8C8679; -CHECKREG r3, 0x2D8CEDAC; -CHECKREG r4, 0xF5D44569; -CHECKREG r5, 0xF5D41A28; -CHECKREG r6, 0x021B800D; -CHECKREG r7, 0x021BB550; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x63548abd; -imm32 r1, 0x7dbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0xb0069007; -imm32 r4, 0xcfbc4569; -imm32 r5, 0xd235c00b; -imm32 r6, 0xe00ca00d; -imm32 r7, 0x678e700f; -R0.H = ( A1 = R1.L * R0.L ) (T); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (T); -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ) (T); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ) (T); -R7 = A1.w; -CHECKREG r0, 0x011E8ABD; -CHECKREG r1, 0x011EBDD6; -CHECKREG r2, 0xCB175679; -CHECKREG r3, 0xCB172B82; -CHECKREG r4, 0x181D4569; -CHECKREG r5, 0x181DDA28; -CHECKREG r6, 0xE626A00D; -CHECKREG r7, 0xE6263550; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x5354babd; -imm32 r1, 0x6dbcdec7; -imm32 r2, 0x7124e679; -imm32 r3, 0x80067007; -imm32 r4, 0x9fbc4569; -imm32 r5, 0xa235900b; -imm32 r6, 0xb00c300d; -imm32 r7, 0xc78ea00f; - R0.H = A1 , A0 = R1.L * R0.L (T); -R1 = A1.w; - R2.H = A1 , A0 = R2.H * R3.L (T); -R3 = A1.w; - R4.H = A1 , A0 = R4.H * R5.H (T); -R5 = A1.w; - R6.H = A1 , A0 += R6.L * R7.H (T); -R7 = A1.w; -CHECKREG r0, 0xE626BABD; -CHECKREG r1, 0xE6263550; -CHECKREG r2, 0xE626E679; -CHECKREG r3, 0xE6263550; -CHECKREG r4, 0xE6264569; -CHECKREG r5, 0xE6263550; -CHECKREG r6, 0xE626300D; -CHECKREG r7, 0xE6263550; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0x33545abd; -imm32 r1, 0x5dbcfec7; -imm32 r2, 0x71245679; -imm32 r3, 0x90060007; -imm32 r4, 0xafbc4569; -imm32 r5, 0xd235900b; -imm32 r6, 0xc00ca00d; -imm32 r7, 0x678ed00f; -R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (T); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (M), A0 = R2.H * R3.L (T); -R3 = A0.w; -R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (T); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H (T); -R7 = A0.w; -CHECKREG r0, 0xFF915ABD; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0x30375679; -CHECKREG r3, 0x00062FF8; -CHECKREG r4, 0x030D4569; -CHECKREG r5, 0x030D72D5; -CHECKREG r6, 0xE621A00D; -CHECKREG r7, 0xCF173844; - -// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) -imm32 r0, 0x83545abd; -imm32 r1, 0xa8bcfec7; -imm32 r2, 0xc1845679; -imm32 r3, 0x1c080007; -imm32 r4, 0xe1cc8569; -imm32 r5, 0x921c080b; -imm32 r6, 0x7901908d; -imm32 r7, 0x679e9008; -R0.H = ( A1 += R1.L * R0.L ) (M,T); -R1 = A1.w; -R2.H = ( A1 = R2.L * R3.H ) (M,T); -R3 = A1.w; -R4.H = ( A1 += R4.H * R5.L ) (M,T); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ) (M,T); -R7 = A1.w; -CHECKREG r0, 0xE5B25ABD; -CHECKREG r1, 0xE5B26993; -CHECKREG r2, 0x09775679; -CHECKREG r3, 0x0977EFC8; -CHECKREG r4, 0x08858569; -CHECKREG r5, 0x0885038C; -CHECKREG r6, 0x30FA908D; -CHECKREG r7, 0x30FA159E; - -imm32 r0, 0x03545abd; -imm32 r1, 0xb0bcfec7; -imm32 r2, 0xc1048679; -imm32 r3, 0xd0009007; -imm32 r4, 0xefbc0569; -imm32 r5, 0xcd35510b; -imm32 r6, 0xe00c802d; -imm32 r7, 0xf78e9003; -R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L (T); -R1 = A1.w; -R2.H = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L (T); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (T); -R5 = A1.w; -R6.H = ( A1 += R6.H * R7.H ), A0 -= R6.L * R7.H (T); -R7 = A1.w; -CHECKREG r0, 0x31D75ABD; -CHECKREG r1, 0x31D7F7C8; -CHECKREG r2, 0x2D928679; -CHECKREG r3, 0x2D92A000; -CHECKREG r4, 0x37DF0569; -CHECKREG r5, 0x37DF0DD8; -CHECKREG r6, 0x39FA802D; -CHECKREG r7, 0x39FAC328; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x63548abd; -imm32 r1, 0x7dbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0xb0069007; -imm32 r4, 0xcfbc4569; -imm32 r5, 0xd235c00b; -imm32 r6, 0xe00ca00d; -imm32 r7, 0x678e700f; -R0.H = ( A1 -= R1.L * R0.L ) (T); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ) (T); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ) (T); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ) (T); -R7 = A1.w; -CHECKREG r0, 0x38DC8ABD; -CHECKREG r1, 0x38DC0552; -CHECKREG r2, 0x6EE35679; -CHECKREG r3, 0x6EE397A6; -CHECKREG r4, 0x56C54569; -CHECKREG r5, 0x56C5BD7E; -CHECKREG r6, 0x709FA00D; -CHECKREG r7, 0x709F882E; - -// The result accumulated in A , and stored to a reg half (MNOP) -imm32 r0, 0x5354babd; -imm32 r1, 0x6dbcdec7; -imm32 r2, 0x7124e679; -imm32 r3, 0x80067007; -imm32 r4, 0x9fbc4569; -imm32 r5, 0xa235900b; -imm32 r6, 0xb00c300d; -imm32 r7, 0xc78ea00f; - R0.H = A1 , A0 -= R1.L * R0.L (T); -R1 = A1.w; - R2.H = A1 , A0 -= R2.H * R3.L (T); -R3 = A1.w; - R4.H = A1 , A0 -= R4.H * R5.H (T); -R5 = A1.w; - R6.H = A1 , A0 -= R6.L * R7.H (T); -R7 = A1.w; -CHECKREG r0, 0x709FBABD; -CHECKREG r1, 0x709F882E; -CHECKREG r2, 0x709FE679; -CHECKREG r3, 0x709F882E; -CHECKREG r4, 0x709F4569; -CHECKREG r5, 0x709F882E; -CHECKREG r6, 0x709F300D; -CHECKREG r7, 0x709F882E; - -// The result accumulated in A , and stored to a reg half -imm32 r0, 0x33545abd; -imm32 r1, 0x5dbcfec7; -imm32 r2, 0x71245679; -imm32 r3, 0x90060007; -imm32 r4, 0xafbc4569; -imm32 r5, 0xd235900b; -imm32 r6, 0xc00ca00d; -imm32 r7, 0x678ed00f; -R0.H = ( A1 -= R1.L * R0.L ) (M), A0 += R1.L * R0.L (T); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ) (M), A0 -= R2.H * R3.L (T); -R3 = A0.w; -R4.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H (T); -R5 = A1.w; -R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (T); -R7 = A0.w; -CHECKREG r0, 0x710E5ABD; -CHECKREG r1, 0x710E7943; -CHECKREG r2, 0x40685679; -CHECKREG r3, 0x1ED0EB56; -CHECKREG r4, 0x133E4569; -CHECKREG r5, 0x133EAF81; -CHECKREG r6, 0xF960A00D; -CHECKREG r7, 0x4FB9B312; - -// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) -imm32 r0, 0x83545abd; -imm32 r1, 0xa8bcfec7; -imm32 r2, 0xc1845679; -imm32 r3, 0x1c080007; -imm32 r4, 0xe1cc8569; -imm32 r5, 0x921c080b; -imm32 r6, 0x7901908d; -imm32 r7, 0x679e9008; -R0.H = ( A1 -= R1.L * R0.L ) (M,T); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ) (M,T); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ) (M,T); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ) (M,T); -R7 = A1.w; -CHECKREG r0, 0xF9CE5ABD; -CHECKREG r1, 0xF9CEFB3E; -CHECKREG r2, 0xF0575679; -CHECKREG r3, 0xF0570B76; -CHECKREG r4, 0xF1498569; -CHECKREG r5, 0xF149F7B2; -CHECKREG r6, 0xC04F908D; -CHECKREG r7, 0xC04FE214; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_tu.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_tu.s deleted file mode 100644 index 259def7..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_tu.s +++ /dev/null @@ -1,145 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a1_tu/c_dsp32mac_dr_a1_tu.dsp -// Spec Reference: dsp32mac dr_a1 tu (truncate signed fraction) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0xa3545abd; -imm32 r1, 0xbdbcfec7; -imm32 r2, 0xc1248679; -imm32 r3, 0xd0069007; -imm32 r4, 0xefbc4569; -imm32 r5, 0xcd35500b; -imm32 r6, 0xe00c800d; -imm32 r7, 0xf78e900f; -R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (TFU); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (TFU); -R3 = A1.w; -R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (TFU); -R5 = A1.w; -R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (TFU); -R7 = A1.w; -CHECKREG r0, 0x5A4E5ABD; -CHECKREG r1, 0x5A4E0EEB; -CHECKREG r2, 0x00008679; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x4AF54569; -CHECKREG r5, 0x4AF50D14; -CHECKREG r6, 0xFFFF800D; -CHECKREG r7, 0x239CE7BC; - -// The result accumulated in A1, and stored to a reg half (MNOP) -imm32 r0, 0x63548abd; -imm32 r1, 0x7dbcfec7; -imm32 r2, 0xC5885679; -imm32 r3, 0xC5880000; -imm32 r4, 0xcfbc4569; -imm32 r5, 0xd235c00b; -imm32 r6, 0xe00ca00d; -imm32 r7, 0x678e700f; -R0.H = ( A1 = R1.L * R0.L ) (TFU); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (TFU); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ) (TFU); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ) (TFU); -R7 = A1.w; -CHECKREG r0, 0x8A138ABD; -CHECKREG r1, 0x8A135EEB; -CHECKREG r2, 0xCCCC5679; -CHECKREG r3, 0xCCCC6C33; -CHECKREG r4, 0x30F64569; -CHECKREG r5, 0x30F67F1F; -CHECKREG r6, 0x5AA1A00D; -CHECKREG r7, 0x5AA11AA8; - -// The result accumulated in A1 , and stored to a reg half (MNOP) -imm32 r0, 0x5354babd; -imm32 r1, 0x6dbcdec7; -imm32 r2, 0x7124e679; -imm32 r3, 0x80067007; -imm32 r4, 0x9fbc4569; -imm32 r5, 0xa235900b; -imm32 r6, 0xb00c300d; -imm32 r7, 0xc78ea00f; - R0.H = A1 , A0 -= R1.L * R0.L (TFU); -R1 = A1.w; - R2.H = A1 , A0 += R2.H * R3.L (TFU); -R3 = A1.w; - R4.H = A1 , A0 -= R4.H * R5.H (TFU); -R5 = A1.w; - R6.H = A1 , A0 = R6.L * R7.H (TFU); -R7 = A1.w; -CHECKREG r0, 0x5AA1BABD; -CHECKREG r1, 0x5AA11AA8; -CHECKREG r2, 0x5AA1E679; -CHECKREG r3, 0x5AA11AA8; -CHECKREG r4, 0x5AA14569; -CHECKREG r5, 0x5AA11AA8; -CHECKREG r6, 0x5AA1300D; -CHECKREG r7, 0x5AA11AA8; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0x33545abd; -imm32 r1, 0x5dbcfec7; -imm32 r2, 0x71245679; -imm32 r3, 0x90060007; -imm32 r4, 0xafbc4569; -imm32 r5, 0xd235900b; -imm32 r6, 0xc00ca00d; -imm32 r7, 0x678ed00f; -R0.H = ( A1 = R1.L * R0.L ) (M), A0 -= R1.L * R0.L (TFU); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (TFU); -R3 = A1.w; -R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (TFU); -R5 = A1.w; -R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (TFU); -R7 = A1.w; -CHECKREG r0, 0xFF915ABD; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0x30375679; -CHECKREG r3, 0x303725C1; -CHECKREG r4, 0x5D604569; -CHECKREG r5, 0x5D60D8AD; -CHECKREG r6, 0x4382A00D; -CHECKREG r7, 0x43823355; - -// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) -imm32 r0, 0x92005ABD; -imm32 r1, 0x09300000; -imm32 r2, 0x56749679; -imm32 r3, 0x30A95000; -imm32 r4, 0xa0009669; -imm32 r5, 0x01000970; -imm32 r6, 0xdf45609D; -imm32 r7, 0x12345679; -R0.H = ( A1 += R1.L * R0.L ) (M,TFU); -R1 = A1.w; -R2.H = ( A1 -= R2.L * R3.H ) (M,TFU); -R3 = A1.w; -R4.H = ( A1 = R4.H * R5.L ) (M,TFU); -R5 = A1.w; -R6.H = ( A1 -= R6.H * R7.H ) (M,TFU); -R7 = A1.w; -CHECKREG r0, 0x43825ABD; -CHECKREG r1, 0x43823355; -CHECKREG r2, 0x57919679; -CHECKREG r3, 0x57912D74; -CHECKREG r4, 0xFC769669; -CHECKREG r5, 0xFC760000; -CHECKREG r6, 0xFEC9609D; -CHECKREG r7, 0xFEC9CBFC; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_u.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_u.s deleted file mode 100644 index 1f78e34..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_u.s +++ /dev/null @@ -1,170 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_dr_a1_u/c_dsp32mac_dr_a1_u.dsp -// Spec Reference: dsp32mac dr_a1 u (unsigned fraction & unsigned int) -# mach: bfin - -.include "testutils.inc" - start - - - - -A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0xa3545abd; -imm32 r1, 0xbabcfec7; -imm32 r2, 0xc1a48679; -imm32 r3, 0xd00a9007; -imm32 r4, 0xefbca569; -imm32 r5, 0xcd355a0b; -imm32 r6, 0xe00c80ad; -imm32 r7, 0xf78e900a; -R0.H = ( A1 = R6.L * R7.L ), A0 += R6.L * R7.L (FU); -R1 = A1.w; -R2.H = ( A1 = R3.L * R4.H ), A0 = R3.H * R4.L (FU); -R3 = A1.w; -R4.H = ( A1 += R2.H * R5.L ), A0 = R2.H * R5.H (FU); -R5 = A1.w; -R6.H = ( A1 += R0.H * R1.H ), A0 += R0.L * R1.H (FU); -R7 = A1.w; -CHECKREG r0, 0x48665ABD; -CHECKREG r1, 0x486656C2; -CHECKREG r2, 0x86E08679; -CHECKREG r3, 0x86E04E24; -CHECKREG r4, 0xB651A569; -CHECKREG r5, 0xB650D9C4; -CHECKREG r6, 0xCACA80AD; -CHECKREG r7, 0xCACA6268; - -imm32 r0, 0x03545abd; -imm32 r1, 0x1abcfec7; -imm32 r2, 0xc2a48679; -imm32 r3, 0x300a9007; -imm32 r4, 0x54bca569; -imm32 r5, 0x6d355a0b; -imm32 r6, 0x700c80ad; -imm32 r7, 0x878e900a; -R0.H = ( A1 -= R6.L * R7.L ), A0 += R6.L * R7.L (FU); -R1 = A1.w; -R2.H = ( A1 -= R3.L * R4.H ), A0 = R3.H * R4.L (FU); -R3 = A1.w; -R4.H = ( A1 += R2.H * R5.L ), A0 -= R2.H * R5.H (FU); -R5 = A1.w; -R6.H = ( A1 -= R0.H * R1.H ), A0 += R0.L * R1.H (FU); -R7 = A1.w; -CHECKREG r0, 0x82645ABD; -CHECKREG r1, 0x82640BA6; -CHECKREG r2, 0x52B88679; -CHECKREG r3, 0x52B7FA82; -CHECKREG r4, 0x6FD0A569; -CHECKREG r5, 0x6FD0386A; -CHECKREG r6, 0x2D6780AD; -CHECKREG r7, 0x2D66815A; - -// The result accumulated in A1, and stored to a reg half (MNOP) -imm32 r0, 0xb3548abd; -imm32 r1, 0x7bbcfec7; -imm32 r2, 0xa1b45679; -imm32 r3, 0xb00b9007; -imm32 r4, 0xcfbcb569; -imm32 r5, 0xd235c00b; -imm32 r6, 0xe00cabbd; -imm32 r7, 0x678e700b; -R0.H = ( A1 = R1.L * R0.L ) (FU); -R1 = A1.w; -R2.H = ( A1 = R2.L * R6.H ) (FU); -R3 = A1.w; -R4.H = ( A1 += R3.H * R5.L ) (FU); -R5 = A1.w; -R6.H = ( A1 = R4.H * R7.H ) (FU); -R7 = A1.w; -CHECKREG r0, 0x8A138ABD; -CHECKREG r1, 0x8A135EEB; -CHECKREG r2, 0x4BAE5679; -CHECKREG r3, 0x4BADEDAC; -CHECKREG r4, 0x8473B569; -CHECKREG r5, 0x8472EE1B; -CHECKREG r6, 0x3594ABBD; -CHECKREG r7, 0x3593BCCA; - -// The result accumulated in A1 , and stored to a reg half (MNOP) -imm32 r0, 0xc354babd; -imm32 r1, 0x6cbcdec7; -imm32 r2, 0x71c4e679; -imm32 r3, 0x800c7007; -imm32 r4, 0x9fbcc569; -imm32 r5, 0xa2359c0b; -imm32 r6, 0xb00c30cd; -imm32 r7, 0xc78ea00c; - R0.H = A1 , A0 = R1.L * R0.L (FU); -R1 = A1.w; - R2.H = A1 , A0 = R2.H * R3.L (FU); -R3 = A1.w; - R4.H = A1 , A0 = R4.H * R5.H (FU); -R5 = A1.w; - R6.H = A1 , A0 = R6.L * R7.H (FU); -R7 = A1.w; -CHECKREG r0, 0x3594BABD; -CHECKREG r1, 0x3593BCCA; -CHECKREG r2, 0x3594E679; -CHECKREG r3, 0x3593BCCA; -CHECKREG r4, 0x3594C569; -CHECKREG r5, 0x3593BCCA; -CHECKREG r6, 0x359430CD; -CHECKREG r7, 0x3593BCCA; - -// The result accumulated in A1 , and stored to a reg half -imm32 r0, 0xd3545abd; -imm32 r1, 0x5dbcfec7; -imm32 r2, 0x71d45679; -imm32 r3, 0x900d0007; -imm32 r4, 0xafbcd569; -imm32 r5, 0xd2359d0b; -imm32 r6, 0xc00ca0dd; -imm32 r7, 0x678ed00d; -R0.H = ( A1 = R1.L * R2.L ) (M), A0 += R1.L * R2.L (FU); -R1 = A1.w; -R2.H = ( A1 = R3.L * R4.H ) (M), A0 = R3.H * R4.L (FU); -R3 = A1.w; -R4.H = ( A1 = R5.H * R6.L ) (M), A0 += R5.H * R6.H (FU); -R5 = A1.w; -R6.H = ( A1 += R7.H * R0.H ) (M), A0 += R7.L * R0.H (FU); -R7 = A1.w; -CHECKREG r0, 0xFF965ABD; -CHECKREG r1, 0xFF96460F; -CHECKREG r2, 0x00055679; -CHECKREG r3, 0x0004CE24; -CHECKREG r4, 0xE33AD569; -CHECKREG r5, 0xE33997C1; -CHECKREG r6, 0x4A9DA0DD; -CHECKREG r7, 0x4A9CB6F5; - -// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) -imm32 r0, 0xe3545abd; -imm32 r1, 0xaebcfec7; -imm32 r2, 0xc1e45679; -imm32 r3, 0x1c0e0007; -imm32 r4, 0xe1cce569; -imm32 r5, 0x921c0e0b; -imm32 r6, 0x790190ed; -imm32 r7, 0x679e900e; -R0.H = ( A1 = R1.L * R0.L ) (M,FU); -R1 = A1.w; -R2.H = ( A1 += R2.L * R3.H ) (M,FU); -R3 = A1.w; -R4.H = ( A1 += R4.H * R5.L ) (M,FU); -R5 = A1.w; -R6.H = ( A1 = R6.H * R7.H ) (M,FU); -R7 = A1.w; -CHECKREG r0, 0xFF915ABD; -CHECKREG r1, 0xFF910EEB; -CHECKREG r2, 0x090B5679; -CHECKREG r3, 0x090B0589; -CHECKREG r4, 0x0763E569; -CHECKREG r5, 0x0762E14D; -CHECKREG r6, 0x30FA90ED; -CHECKREG r7, 0x30FA159E; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s deleted file mode 100644 index e84f3d5..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s +++ /dev/null @@ -1,157 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0/c_dsp32mac_dr_a1a0.dsp -// Spec Reference: dsp32mac dr_a1a0 -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - R0 = 0; - ASTAT = R0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x13545abd; - imm32 r1, 0xb2bcfec7; - imm32 r2, 0xc1348679; - imm32 r3, 0xd0049007; - imm32 r4, 0xefbc5569; - imm32 r5, 0xcd35560b; - imm32 r6, 0xe00c807d; - imm32 r7, 0xf78e9008; - A1 = A0 = 0; - R6.H = (A1 += R0.L * R0.L), R6.L = (A0 = R0.L * R0.L); - P1 = A1.w; - P2 = A0.w; - R1.H = (A1 += R2.L * R3.L), R1.L = (A0 -= R2.H * R3.L); - P3 = A1.w; - P4 = A0.w; - R2.H = (A1 -= R4.L * R5.L), R2.L = (A0 += R4.H * R5.H); - P5 = A1.w; - FP = A0.w; - R3.H = (A1 += R0.L * R7.L), R3.L = (A0 += R0.L * R7.H); - R4 = A1.w; - R5 = A0.w; - CHECKREG r0, 0x13545ABD; - CHECKREG r1, 0x7FFF0964; - CHECKREG r2, 0x71380FD8; - CHECKREG r3, 0x21D909DC; - CHECKREG r4, 0x21D8C27A; - CHECKREG r5, 0x09DB89BE; - CHECKREG r6, 0x40534053; - CHECKREG r7, 0xF78E9008; - CHECKREG p1, 0x4052DF12; - CHECKREG p2, 0x4052DF12; - CHECKREG p3, 0xAAA259B0; - CHECKREG p4, 0x0963CE3A; - CHECKREG p5, 0x713876AA; - CHECKREG fp, 0x0FD82A12; - - imm32 r0, 0x13545abd; - imm32 r1, 0x22bcfec7; - imm32 r2, 0x43348679; - imm32 r3, 0x50049007; - imm32 r4, 0x6fbc5569; - imm32 r5, 0x7d35560b; - imm32 r6, 0x800c807d; - imm32 r7, 0xf98e9008; - A1 = A0 = 0; - R0.H = (A1 += R1.L * R0.H), R0.L = (A0 = R1.L * R0.L); - P1 = A1.w; - P2 = A0.w; - R6.H = (A1 += R2.L * R2.H), R6.L = (A0 -= R2.H * R2.L); - P3 = A1.w; - P4 = A0.w; - R2.H = (A1 -= R4.L * R5.H), R2.L = (A0 += R4.H * R5.H); - P5 = A1.w; - FP = A0.w; - R3.H = (A1 += R3.L * R7.H), R3.L = (A0 -= R3.L * R7.H); - R4 = A1.w; - R5 = A0.w; - CHECKREG r0, 0xFFD1FF22; - CHECKREG r1, 0x22BCFEC7; - CHECKREG r2, 0x80007FFF; - CHECKREG r3, 0x80007FFF; - CHECKREG r4, 0x721A320A; - CHECKREG r5, 0xA6989CC2; - CHECKREG r6, 0xC0033EF0; - CHECKREG r7, 0xF98E9008; - CHECKREG p1, 0xFFD0BC98; - CHECKREG p2, 0xFF221DD6; - CHECKREG p3, 0xC002B3C0; - CHECKREG p4, 0x3EF026AE; - CHECKREG p5, 0x6C76CC46; - CHECKREG fp, 0xAC3C0286; - - imm32 r0, 0x13545abd; - imm32 r1, 0x42bcfec7; - imm32 r2, 0x51348679; - imm32 r3, 0x60049007; - imm32 r4, 0x7fbc5569; - imm32 r5, 0x8d35560b; - imm32 r6, 0x900c807d; - imm32 r7, 0xa78e9008; - A1 = A0 = 0; - R0.H = (A1 -= R1.H * R0.L), R0.L = (A0 = R1.L * R0.L); - P1 = A1.w; - P2 = A0.w; - R1.H = (A1 += R2.H * R3.L), R1.L = (A0 -= R2.H * R3.L); - P3 = A1.w; - P4 = A0.w; - R2.H = (A1 = R4.H * R5.L), R2.L = (A0 += R4.H * R5.H); - P5 = A1.w; - FP = A0.w; - R3.H = (A1 -= R6.H * R7.L), R3.L = (A0 += R6.L * R7.H); - R4 = A1.w; - R5 = A0.w; - CHECKREG r0, 0xD0B1FF22; - CHECKREG r1, 0x89A8462B; - CHECKREG r2, 0x55DDD39D; - CHECKREG r3, 0xF3EF2BB9; - CHECKREG r4, 0xF3EEC968; - CHECKREG r5, 0x2BB8C982; - CHECKREG r6, 0x900C807D; - CHECKREG r7, 0xA78E9008; - CHECKREG p1, 0xD0B14668; - CHECKREG p2, 0xFF221DD6; - CHECKREG p3, 0x89A83740; - CHECKREG p4, 0x462B2CFE; - CHECKREG p5, 0x55DD4A28; - CHECKREG fp, 0xD39D28D6; - - imm32 r0, 0x03545abd; - imm32 r1, 0xb3bcfec7; - imm32 r2, 0x24348679; - imm32 r3, 0x60049007; - imm32 r4, 0x7fbc5569; - imm32 r5, 0x9d35560b; - imm32 r6, 0xa00c807d; - imm32 r7, 0x078e9008; - A1 = A0 = 0; - R0.H = (A1 += R1.H * R0.H), R0.L = (A0 -= R1.L * R0.L); - P1 = A1.w; - P2 = A0.w; - R1.H = (A1 -= R2.H * R3.H), R1.L = (A0 = R2.H * R3.L); - P3 = A1.w; - P4 = A0.w; - R2.H = (A1 = R4.H * R5.H), R2.L = (A0 += R4.H * R5.H); - P5 = A1.w; - FP = A0.w; - R3.H = (A1 += R6.H * R7.H), R3.L = (A0 -= R6.L * R7.H); - R4 = A1.w; - R5 = A0.w; - CHECKREG r0, 0xFE0400DE; - CHECKREG r1, 0xE2DCE054; - CHECKREG r2, 0x9D698000; - CHECKREG r3, 0x97C08545; - CHECKREG r4, 0x97BFB128; - CHECKREG r5, 0x85449604; - CHECKREG r6, 0xA00C807D; - CHECKREG r7, 0x078E9008; - CHECKREG p1, 0xFE045B60; - CHECKREG p2, 0x00DDE22A; - CHECKREG p3, 0xE2DC39C0; - CHECKREG p4, 0xE0547AD8; - CHECKREG p5, 0x9D697BD8; - CHECKREG fp, 0x7DBDF6B0; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s deleted file mode 100644 index 8f9e70c..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s +++ /dev/null @@ -1,157 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_iutsh/c_dsp32mac_dr_a1a0_iutsh.dsp -// Spec Reference: dsp32mac dr_a1a0 iutsh -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - R0 = 0; - ASTAT = R0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x13545abd; - imm32 r1, 0xb2bcfec7; - imm32 r2, 0xc1348679; - imm32 r3, 0xd0049007; - imm32 r4, 0x2efbc556; - imm32 r5, 0xcd35560b; - imm32 r6, 0xe00c807d; - imm32 r7, 0xf78e9008; - A1 = A0 = 0; - R6.H = (A1 += R0.L * R0.L), R6.L = (A0 = R0.L * R0.L) (IS); - P1 = A1.w; - P2 = A0.w; - R1.H = (A1 += R2.L * R3.L), R1.L = (A0 -= R2.H * R3.L) (FU); - P3 = A1.w; - P4 = A0.w; - R2.H = (A1 = R4.L * R5.L) (M), R2.L = (A0 += R4.H * R5.H) (T); - P5 = A1.w; - FP = A0.w; - R3.H = (A1 += R0.L * R7.L), R3.L = (A0 += R0.L * R7.H) (S2RND); - R4 = A1.w; - R5 = A0.w; - CHECKREG r0, 0x13545ABD; - CHECKREG r1, 0x6BD10000; - CHECKREG r2, 0xEC48ED5B; - CHECKREG r3, 0x8000CEBE; - CHECKREG r4, 0x9CE8AA82; - CHECKREG r5, 0xE75ED19A; - CHECKREG r6, 0x7FFF7FFF; - CHECKREG r7, 0xF78E9008; - CHECKREG p1, 0x20296F89; - CHECKREG p2, 0x20296F89; - CHECKREG p3, 0x6BD12CD8; - CHECKREG p4, 0x00000000; - CHECKREG p5, 0xEC485EB2; - CHECKREG fp, 0xED5B71EE; - - imm32 r0, 0x13545abd; - imm32 r1, 0x22bcfec7; - imm32 r2, 0x43348679; - imm32 r3, 0x50049007; - imm32 r4, 0x6fbc5569; - imm32 r5, 0x7d35560b; - imm32 r6, 0x800c807d; - imm32 r7, 0xf98e9008; - A1 = A0 = 0; - R0.H = (A1 += R1.L * R0.H), R0.L = (A0 = R1.L * R0.L) (IU); - P1 = A1.w; - P2 = A0.w; - R6.H = (A1 += R2.L * R2.H), R6.L = (A0 = R2.H * R2.L) (TFU); - P3 = A1.w; - P4 = A0.w; - R2.H = (A1 -= R4.L * R5.H), R2.L = (A0 += R4.H * R5.H) (ISS2); - P5 = A1.w; - FP = A0.w; - R3.H = (A1 += R3.L * R7.H), R3.L = (A0 -= R3.L * R7.H) (IH); - R4 = A1.w; - R5 = A0.w; - CHECKREG r0, 0xFFFFFFFF; - CHECKREG r1, 0x22BCFEC7; - CHECKREG r2, 0x7FFF7FFF; - CHECKREG r3, 0x0F955721; - CHECKREG r4, 0x0F951905; - CHECKREG r5, 0x5721369E; - CHECKREG r6, 0x3689234C; - CHECKREG r7, 0xF98E9008; - CHECKREG p1, 0x133C5E4C; - CHECKREG p2, 0x5A4E0EEB; - CHECKREG p3, 0x368959E0; - CHECKREG p4, 0x234CFB94; - CHECKREG p5, 0x0CC36623; - CHECKREG fp, 0x59F2E980; - - imm32 r0, 0x13545abd; - imm32 r1, 0x42bcfec7; - imm32 r2, 0x51348679; - imm32 r3, 0x60049007; - imm32 r4, 0x7fbc5569; - imm32 r5, 0x8d35560b; - imm32 r6, 0x900c807d; - imm32 r7, 0xa78e9008; - A1 = A0 = 0; - R0.H = (A1 += R1.H * R0.L), R0.L = (A0 = R1.L * R0.L) (IS); - P1 = A1.w; - P2 = A0.w; - R1.H = (A1 += R2.H * R3.L) (M), R1.L = (A0 -= R2.H * R3.L) (IU); - P3 = A1.w; - P4 = A0.w; - R2.H = (A1 = R4.H * R5.L), R2.L = (A0 += R4.H * R5.H) (ISS2); - P5 = A1.w; - FP = A0.w; - R3.H = (A1 -= R6.H * R7.L) (M), R3.L = (A0 += R6.L * R7.H) (IH); - R4 = A1.w; - R5 = A0.w; - CHECKREG r0, 0x7FFF8000; - CHECKREG r1, 0x7FFFFFFF; - CHECKREG r2, 0x7FFF8000; - CHECKREG r3, 0x69EBC4A8; - CHECKREG r4, 0x69EB64B4; - CHECKREG r5, 0xC4A864C1; - CHECKREG r6, 0x900C807D; - CHECKREG r7, 0xA78E9008; - CHECKREG p1, 0x17A75CCC; - CHECKREG p2, 0xFF910EEB; - CHECKREG p3, 0x4556D538; - CHECKREG p4, 0xD1E1967F; - CHECKREG p5, 0x2AEEA514; - CHECKREG fp, 0x989A946B; - - imm32 r0, 0x03545abd; - imm32 r1, 0xb3bcfec7; - imm32 r2, 0x24348679; - imm32 r3, 0x60049007; - imm32 r4, 0x7fbc5569; - imm32 r5, 0x9d35560b; - imm32 r6, 0xa00c807d; - imm32 r7, 0x078e9008; - A1 = A0 = 0; - R0.H = (A1 += R1.H * R0.H), R0.L = (A0 -= R1.L * R0.L) (FU); - P1 = A1.w; - P2 = A0.w; - R1.H = (A1 += R2.H * R3.H), R1.L = (A0 = R2.H * R3.L) (TFU); - P3 = A1.w; - P4 = A0.w; - R2.H = (A1 = R4.H * R5.H), R2.L = (A0 += R4.H * R5.H) (IU); - P5 = A1.w; - FP = A0.w; - R3.H = (A1 -= R6.H * R7.H) (M), R3.L = (A0 += R6.L * R7.H) (S2RND); - R4 = A1.w; - R5 = A0.w; - CHECKREG r0, 0x02560000; - CHECKREG r1, 0x0FEA145E; - CHECKREG r2, 0xFFFFFFFF; - CHECKREG r3, 0x7FFF7FFF; - CHECKREG r4, 0x5145A344; - CHECKREG r5, 0x5B485C04; - CHECKREG r6, 0xA00C807D; - CHECKREG r7, 0x078E9008; - CHECKREG p1, 0x02562DB0; - CHECKREG p2, 0x00000000; - CHECKREG p3, 0x0FEA3E80; - CHECKREG p4, 0x145E3D6C; - CHECKREG p5, 0x4E70BDEC; - CHECKREG fp, 0x62CEFB58; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s deleted file mode 100644 index 2b6f741..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s +++ /dev/null @@ -1,157 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_m/c_dsp32mac_dr_a1a0_m.dsp -// Spec Reference: dsp32mac dr_a1a0 m -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - R0 = 0; - ASTAT = R0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x13545abd; - imm32 r1, 0xb2bcfec7; - imm32 r2, 0xc1348679; - imm32 r3, 0xd0049007; - imm32 r4, 0xefbc5569; - imm32 r5, 0xcd35560b; - imm32 r6, 0xe00c807d; - imm32 r7, 0xf78e9008; - A1 = A0 = 0; - R6.H = (A1 += R0.L * R0.L) (M), R6.L = (A0 = R0.L * R0.L); - P1 = A1.w; - P2 = A0.w; - R1.H = (A1 += R2.L * R3.L) (M), R1.L = (A0 -= R2.H * R3.L); - P3 = A1.w; - P4 = A0.w; - R2.H = (A1 -= R4.L * R5.L) (M), R2.L = (A0 -= R4.H * R5.H); - P5 = A1.w; - FP = A0.w; - R3.H = (A1 += R0.L * R7.L) (M), R3.L = (A0 += R0.L * R7.H); - R4 = A1.w; - R5 = A0.w; - CHECKREG r0, 0x13545ABD; - CHECKREG r1, 0xDBCA0964; - CHECKREG r2, 0xBF1502EF; - CHECKREG r3, 0xF222FCF3; - CHECKREG r4, 0xF222613D; - CHECKREG r5, 0xFCF2D20E; - CHECKREG r6, 0x20294053; - CHECKREG r7, 0xF78E9008; - CHECKREG p1, 0x20296F89; - CHECKREG p2, 0x4052DF12; - CHECKREG p3, 0xDBCA2CD8; - CHECKREG p4, 0x0963CE3A; - CHECKREG p5, 0xBF153B55; - CHECKREG fp, 0x02EF7262; - - imm32 r0, 0x13545abd; - imm32 r1, 0x22bcfec7; - imm32 r2, 0x43348679; - imm32 r3, 0x50049007; - imm32 r4, 0x6fbc5569; - imm32 r5, 0x7d35560b; - imm32 r6, 0x800c807d; - imm32 r7, 0xf98e9008; - A1 = A0 = 0; - R0.H = (A1 += R1.L * R0.H) (M), R0.L = (A0 -= R1.L * R0.L); - P1 = A1.w; - P2 = A0.w; - R6.H = (A1 += R2.L * R2.H) (M), R6.L = (A0 = R2.H * R2.L); - P3 = A1.w; - P4 = A0.w; - R2.H = (A1 -= R4.L * R5.H) (M), R2.L = (A0 += R4.H * R5.H); - P5 = A1.w; - FP = A0.w; - R3.H = (A1 += R3.L * R7.H) (M), R3.L = (A0 -= R3.L * R7.H); - R4 = A1.w; - R5 = A0.w; - CHECKREG r0, 0xFFE800DE; - CHECKREG r1, 0x22BCFEC7; - CHECKREG r2, 0xB63B2D7E; - CHECKREG r3, 0x800027DA; - CHECKREG r4, 0x49141905; - CHECKREG r5, 0x27DA6D3C; - CHECKREG r6, 0xE001C032; - CHECKREG r7, 0xF98E9008; - CHECKREG p1, 0xFFE85E4C; - CHECKREG p2, 0x00DDE22A; - CHECKREG p3, 0xE00159E0; - CHECKREG p4, 0xC031F728; - CHECKREG p5, 0xB63B6623; - CHECKREG fp, 0x2D7DD300; - - imm32 r0, 0x13545abd; - imm32 r1, 0x42bcfec7; - imm32 r2, 0x51348679; - imm32 r3, 0x60049007; - imm32 r4, 0x7fbc5569; - imm32 r5, 0x8d35560b; - imm32 r6, 0x900c807d; - imm32 r7, 0xa78e9008; - A1 = A0 = 0; - R0.H = (A1 += R1.H * R0.L) (M), R0.L = (A0 = R1.L * R0.L); - P1 = A1.w; - P2 = A0.w; - R1.H = (A1 -= R2.H * R3.L) (M), R1.L = (A0 -= R2.H * R3.L); - P3 = A1.w; - P4 = A0.w; - R2.H = (A1 -= R4.H * R5.L) (M), R2.L = (A0 += R4.H * R5.H); - P5 = A1.w; - FP = A0.w; - R3.H = (A1 += R6.H * R7.L) (M), R3.L = (A0 += R6.L * R7.H); - R4 = A1.w; - R5 = A0.w; - CHECKREG r0, 0x17A7FF22; - CHECKREG r1, 0xE9F8462B; - CHECKREG r2, 0xBF09D39D; - CHECKREG r3, 0x800C2BB9; - CHECKREG r4, 0x800C7FAC; - CHECKREG r5, 0x2BB8C982; - CHECKREG r6, 0x900C807D; - CHECKREG r7, 0xA78E9008; - CHECKREG p1, 0x17A75CCC; - CHECKREG p2, 0xFF221DD6; - CHECKREG p3, 0xE9F7E460; - CHECKREG p4, 0x462B2CFE; - CHECKREG p5, 0xBF093F4C; - CHECKREG fp, 0xD39D28D6; - - imm32 r0, 0x03545abd; - imm32 r1, 0xb3bcfec7; - imm32 r2, 0x24348679; - imm32 r3, 0x60049007; - imm32 r4, 0x7fbc5569; - imm32 r5, 0x9d35560b; - imm32 r6, 0xa00c807d; - imm32 r7, 0x078e9008; - A1 = A0 = 0; - R0.H = (A1 += R1.H * R0.H) (M), R0.L = (A0 -= R1.L * R0.L); - P1 = A1.w; - P2 = A0.w; - R1.H = (A1 -= R2.H * R3.H) (M), R1.L = (A0 = R2.H * R3.L); - P3 = A1.w; - P4 = A0.w; - R2.H = (A1 = R4.H * R5.H) (M), R2.L = (A0 += R4.H * R5.H); - P5 = A1.w; - FP = A0.w; - R3.H = (A1 += R6.H * R7.H) (M), R3.L = (A0 += R6.L * R7.H); - R4 = A1.w; - R5 = A0.w; - CHECKREG r0, 0xFF0200DE; - CHECKREG r1, 0xF16EE054; - CHECKREG r2, 0x4E718000; - CHECKREG r3, 0x4B9C8000; - CHECKREG r4, 0x4B9BD894; - CHECKREG r5, 0x7637575C; - CHECKREG r6, 0xA00C807D; - CHECKREG r7, 0x078E9008; - CHECKREG p1, 0xFF022DB0; - CHECKREG p2, 0x00DDE22A; - CHECKREG p3, 0xF16E1CE0; - CHECKREG p4, 0xE0547AD8; - CHECKREG p5, 0x4E70BDEC; - CHECKREG fp, 0x7DBDF6B0; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_mix.s b/sim/testsuite/sim/bfin/c_dsp32mac_mix.s deleted file mode 100644 index a5a28c7..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_mix.s +++ /dev/null @@ -1,114 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_mix/c_dsp32mac_mix.dsp -// Spec Reference: dsp32mac mix -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0xab235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acefdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246700f; - -A1 = A0 = 0; -A0.L = R0.L; -A0.H = R0.H; - -// test the ROUNDING only on signed fraction T=1 -R0.H = (A1 = R4.L * R5.L), R0.L = (A0 = R4.L * R5.H) (T); -R1.H = (A1 = R4.H * R5.L), R1.L = (A0 = R4.H * R5.H) (T); -R2.H = (A1 = R6.L * R7.L), R2.L = (A0 = R6.H * R7.H) (T); -R3.H = (A1 = R6.L * R7.H), R3.L = (A0 = R6.L * R7.L) (T); -CHECKREG r0, 0x066DF95C; -CHECKREG r1, 0x0E0AF17F; -CHECKREG r2, 0x000B0001; -CHECKREG r3, 0x0001000B; - -// When two results are stored to a single register, they must be rounded -// or truncated and stored to the 2 halves of a single destination reg dst - -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; - -// The result accumulated in A0 and A1, and stored to a reg half -R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; -R3.H = A1 , A0 = R7.H * R6.L (T); -R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L; -A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2); - -CHECKREG r2, 0xFFD15679; -CHECKREG r3, 0xFFD00007; -CHECKREG r4, 0x00074569; -CHECKREG r5, 0x12358000; - -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; -// The result accumulated in A0 and A1, and stored to a reg -R5.H = (A1 = R1.L * R0.H), R5.L = (A0 = R1.H * R0.L) (TFU); -R6.H = (A1 = R3.L * R2.H) (M), R6.L = (A0 = R3.H * R2.L) (TFU); -R7.H = (A1 = R1.L * R0.H) (M), R7.L = (A0 = R1.H * R0.L) (IH); // hi-word extraction -CHECKREG r5, 0x133C3D94; -CHECKREG r6, 0x00040002; -CHECKREG r7, 0xFFE8E2D7; - - -// The result accumulated in A0 and A1, and stored to a reg pair -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; - -R3 = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; -R5 = ( A1 = R1.L * R0.H ); -R7 = ( A1 += R1.L * R0.H ) (M), A0 -= R1.H * R0.L; -CHECKREG r2, 0xA1245679; -CHECKREG r3, 0xFFD0BC98; -CHECKREG r4, 0xEFBC4569; -CHECKREG r5, 0xFFD0BC98; -CHECKREG r6, 0x000C000D; -CHECKREG r7, 0xFFB91AE4; -A1 = R1.L * R0.H, R2 = ( A0 = R1.H * R0.L ); -A1 = R1.L * R0.H (M), R6 = ( A0 -= R1.H * R0.L ); -CHECKREG r2, 0xC5AEB798; -CHECKREG r3, 0xFFD0BC98; -CHECKREG r4, 0xEFBC4569; -CHECKREG r5, 0xFFD0BC98; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0xFFB91AE4; - -imm32 r0, 0x13545abd; -imm32 r1, 0xadbcfec7; -imm32 r2, 0xa1245679; -imm32 r3, 0x00060007; -imm32 r4, 0xefbc4569; -imm32 r5, 0x1235000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x678e000f; -R3 = ( A1 -= R5.L * R4.H ), R2 = ( A0 -= R5.H * R4.L ) (S2RND); -R3 = ( A1 -= R1.L * R0.H ) (M), R2 = ( A0 += R1.H * R0.L ) (S2RND); -CHECKREG r2, 0x80000000; -CHECKREG r3, 0x0002CBB0; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0.s deleted file mode 100644 index e47600e..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0.s +++ /dev/null @@ -1,129 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0/c_dsp32mac_pair_a0.dsp -// Spec Reference: dsp32mac pair a0 -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - A1 += R1.L * R0.L, R6 = ( A0 = R1.L * R0.L ); - P1 = A1.w; - P5 = A0.w; - A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ); - P2 = A1.w; - A1 -= R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ); - P3 = A0.w; - A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ); - P4 = A0.w; - CHECKREG r0, 0xFFFB3578; - CHECKREG r1, 0x86BCFEC7; - CHECKREG r2, 0xF2CF3598; - CHECKREG r3, 0x00860007; - CHECKREG r4, 0xF70DA834; - CHECKREG r5, 0x1235860B; - CHECKREG r6, 0xFF221DD6; - CHECKREG r7, 0x678E0086; - CHECKREG p1, 0xFF221DD6; - CHECKREG p2, 0x0004BA9E; - CHECKREG p3, 0xF2CF3598; - CHECKREG p4, 0xF70DA834; - CHECKREG p5, 0xFF221DD6; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - A1 += R1.L * R0.H, R4 = ( A0 -= R1.L * R0.L ); - P1 = A0.w; - A1 = R2.L * R3.H, R0 = ( A0 = R2.H * R3.L ); - P2 = A0.w; - A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ); - P3 = A0.w; - A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ); - P4 = A0.w; - CHECKREG r0, 0xFFBC8F22; - CHECKREG r1, 0xA1BCF4C7; - CHECKREG r2, 0xFFA518F6; - CHECKREG r3, 0x00010005; - CHECKREG r4, 0xFD9B2E5E; - CHECKREG r5, 0x1235010B; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xFD9B2E5E; - CHECKREG p2, 0xFFFC4AC8; - CHECKREG p3, 0xFFA518F6; - CHECKREG p4, 0xFFBC8F22; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ); - P1 = A0.w; - A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ); - P2 = A0.w; - A1 -= R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ); - P3 = A0.w; - A1 += R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ); - P4 = A0.w; - CHECKREG r0, 0xF8876658; - CHECKREG r1, 0xABD69EC7; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x1EA0F4F8; - CHECKREG r5, 0x1225010B; - CHECKREG r6, 0x00062F18; - CHECKREG r7, 0x678E0561; - CHECKREG p1, 0xCB200616; - CHECKREG p2, 0x00062F18; - CHECKREG p3, 0xF8876658; - CHECKREG p4, 0x1EA0F4F8; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ); - P1 = A0.w; - A1 -= R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ); - P2 = A0.w; - A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ); - P3 = A0.w; - A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ); - P4 = A0.w; - CHECKREG r0, 0xFFF9EE9A; - CHECKREG r1, 0x91BCFEC7; - CHECKREG r2, 0xFF256182; - CHECKREG r3, 0xD0910007; - CHECKREG r4, 0xFF1FB35E; - CHECKREG r5, 0xD235910B; - CHECKREG r6, 0xF750102E; - CHECKREG r7, 0x67DE0009; - CHECKREG p1, 0xFFF9EE9A; - CHECKREG p2, 0xFF256182; - CHECKREG p3, 0xFF1FB35E; - CHECKREG p4, 0xF750102E; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_i.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_i.s deleted file mode 100644 index 75782f8..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_i.s +++ /dev/null @@ -1,247 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_i/c_dsp32mac_pair_a0_i.dsp -// Spec Reference: dsp32mac pair a0 I -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (IS); - P1 = A0.w; - A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (IS); - P5 = A1.w; - P2 = A0.w; - A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (IS); - P3 = A0.w; - A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (IS); - P4 = A0.w; - CHECKREG r0, 0xFFFD9ABC; - CHECKREG r1, 0x86BCFEC7; - CHECKREG r2, 0xF9679ACC; - CHECKREG r3, 0x00860007; - CHECKREG r4, 0xF857FE25; - CHECKREG r5, 0x1235860B; - CHECKREG r6, 0x006EF115; - CHECKREG r7, 0x678E0086; - CHECKREG p1, 0x006EF115; - CHECKREG p2, 0xFFFD9ABC; - CHECKREG p3, 0xF9679ACC; - CHECKREG p4, 0xF857FE25; - CHECKREG p5, 0x00025D4F; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (IS); - P1 = A0.w; - A1 -= R2.L * R3.H, R0 = ( A0 -= R2.H * R3.L ) (IS); - P2 = A0.w; - A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (IS); - P3 = A0.w; - A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (IS); - P4 = A0.w; - CHECKREG r0, 0xFC8B26EA; - CHECKREG r1, 0xA1BCF4C7; - CHECKREG r2, 0xFC7F6BD4; - CHECKREG r3, 0x00010005; - CHECKREG r4, 0xFCB93CEB; - CHECKREG r5, 0x1235010B; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xFCB93CEB; - CHECKREG p2, 0xFCBB1787; - CHECKREG p3, 0xFC7F6BD4; - CHECKREG p4, 0xFC8B26EA; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - A1 += R1.H * R0.L, R4 = ( A0 -= R1.L * R0.L ) (IS); - P1 = A0.w; - A1 -= R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (IS); - P2 = A0.w; - A1 = R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (IS); - P3 = A0.w; - A1 -= R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (IS); - P4 = A0.w; - CHECKREG r0, 0x01A40FD3; - CHECKREG r1, 0xABD69EC7; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x0B2A737B; - CHECKREG r5, 0x1225010B; - CHECKREG r6, 0x0003178C; - CHECKREG r7, 0x678E0561; - CHECKREG p1, 0x16FB23DF; - CHECKREG p2, 0x0003178C; - CHECKREG p3, 0x01A40FD3; - CHECKREG p4, 0x0B2A737B; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (IS); - P1 = A0.w; - A1 = R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ) (IS); - P2 = A0.w; - A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (IS); - P3 = A0.w; - A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (IS); - P4 = A0.w; - CHECKREG r0, 0xFFFCF74D; - CHECKREG r1, 0x91BCFEC7; - CHECKREG r2, 0xFF92B0C1; - CHECKREG r3, 0xD0910007; - CHECKREG r4, 0xFF911149; - CHECKREG r5, 0xD235910B; - CHECKREG r6, 0x007295B5; - CHECKREG r7, 0x67DE0009; - CHECKREG p1, 0xFFFCF74D; - CHECKREG p2, 0xFF92B0C1; - CHECKREG p3, 0xFF911149; - CHECKREG p4, 0x007295B5; - - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (IS); - P5 = A1.w; - P1 = A0.w; - A1 -= R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (IS); - P2 = A0.w; - A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (IS); - P3 = A0.w; - A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (IS); - P4 = A0.w; - CHECKREG r0, 0xFFFD9ABC; - CHECKREG r1, 0x86BCFEC7; - CHECKREG r2, 0xF9679ACC; - CHECKREG r3, 0x00860007; - CHECKREG r4, 0xFA773773; - CHECKREG r5, 0x1235860B; - CHECKREG r6, 0xFF910EEB; - CHECKREG r7, 0x678E0086; - CHECKREG p1, 0xFF910EEB; - CHECKREG p2, 0xFFFD9ABC; - CHECKREG p3, 0xF9679ACC; - CHECKREG p4, 0xFA773773; - CHECKREG p5, 0xFF89C73F; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R4 = ( A0 -= R1.L * R0.L ) (IS); - P1 = A0.w; - R0 = ( A0 = R2.H * R3.L ) (IS); - P2 = A0.w; - R2 = ( A0 += R4.H * R5.H ) (IS); - P3 = A0.w; - R0 = ( A0 += R6.L * R7.H ) (IS); - P4 = A0.w; - CHECKREG r0, 0xFFE0B29B; - CHECKREG r1, 0xA1BCF4C7; - CHECKREG r2, 0xFFD4F785; - CHECKREG r3, 0x00010005; - CHECKREG r4, 0xFDBDFA88; - CHECKREG r5, 0x1235010B; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xFDBDFA88; - CHECKREG p2, 0xFFFE2564; - CHECKREG p3, 0xFFD4F785; - CHECKREG p4, 0xFFE0B29B; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (IS); - P1 = A0.w; - R6 = ( A0 -= R2.H * R3.L ) (IS); - P2 = A0.w; - A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (IS); - P3 = A0.w; - R4 = ( A0 += R6.L * R7.H ) (IS); - P4 = A0.w; - CHECKREG r0, 0xE3AD394F; - CHECKREG r1, 0xABD69EC7; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0xDB61F2C1; - CHECKREG r5, 0x1225010B; - CHECKREG r6, 0xE58CEB7F; - CHECKREG r7, 0x678E0561; - CHECKREG p1, 0xE590030B; - CHECKREG p2, 0xE58CEB7F; - CHECKREG p3, 0xE3AD394F; - CHECKREG p4, 0xDB61F2C1; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R0 = ( A0 = R5.L * R3.L ) (IS); - P1 = A0.w; - A1 -= R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (IS); - P2 = A0.w; - A1 = R7.H * R0.H (M), R4 = ( A0 += R7.H * R0.H ) (IS); - P3 = A0.w; - R6 = ( A0 += R4.L * R6.H ) (IS); - P4 = A0.w; - CHECKREG r0, 0xFFFCF74D; - CHECKREG r1, 0x91BCFEC7; - CHECKREG r2, 0x006A468C; - CHECKREG r3, 0xD0910007; - CHECKREG r4, 0x0068A714; - CHECKREG r5, 0xD235910B; - CHECKREG r6, 0xFBE08004; - CHECKREG r7, 0x67DE0009; - CHECKREG p1, 0xFFFCF74D; - CHECKREG p2, 0x006A468C; - CHECKREG p3, 0x0068A714; - CHECKREG p4, 0xFBE08004; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_is.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_is.s deleted file mode 100644 index 55f6c05..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_is.s +++ /dev/null @@ -1,245 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_is/c_dsp32mac_pair_a0_is.dsp -// Spec Reference: dsp32mac pair a0 IS -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (ISS2); - P1 = A1.w; - A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (ISS2); - P2 = A1.w; - A1 -= R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (ISS2); - P3 = A1.w; - A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (ISS2); - P4 = A1.w; - CHECKREG r0, 0xFFFB3578; - CHECKREG r1, 0x86BCFEC7; - CHECKREG r2, 0xF2CF3598; - CHECKREG r3, 0x00860007; - CHECKREG r4, 0xEE90C2FC; - CHECKREG r5, 0x1235860B; - CHECKREG r6, 0x00DDE22A; - CHECKREG r7, 0x678E0086; - CHECKREG p1, 0xFF910EEB; - CHECKREG p2, 0x00025D4F; - CHECKREG p3, 0xFFCD4859; - CHECKREG p4, 0x0E03FC27; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (ISS2); - P1 = A0.w; - A1 -= R2.L * R3.H, R0 = ( A0 -= R2.H * R3.L ) (ISS2); - P2 = A0.w; - A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (ISS2); - P3 = A0.w; - A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (ISS2); - P4 = A0.w; - CHECKREG r0, 0xF89EF66E; - CHECKREG r1, 0xA1BCF4C7; - CHECKREG r2, 0xF8878042; - CHECKREG r3, 0x00010005; - CHECKREG r4, 0xF97279D6; - CHECKREG r5, 0x1235010B; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xFCB93CEB; - CHECKREG p2, 0xFCBB1787; - CHECKREG p3, 0xFC43C021; - CHECKREG p4, 0xFC4F7B37; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ) (ISS2); - P1 = A0.w; - A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (ISS2); - P2 = A0.w; - A1 -= R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (ISS2); - P3 = A0.w; - A1 += R6.H * R7.L, R4 = ( A0 -= R6.L * R7.H ) (ISS2); - P4 = A0.w; - CHECKREG r0, 0xF8876658; - CHECKREG r1, 0xABD69EC7; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0xD26DD7B8; - CHECKREG r5, 0x1225010B; - CHECKREG r6, 0x00062F18; - CHECKREG r7, 0x678E0561; - CHECKREG p1, 0xE590030B; - CHECKREG p2, 0x0003178C; - CHECKREG p3, 0xFC43B32C; - CHECKREG p4, 0xE936EBDC; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (ISS2); - P1 = A0.w; - A1 -= R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ) (ISS2); - P2 = A0.w; - A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (ISS2); - P3 = A0.w; - A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (ISS2); - P4 = A0.w; - CHECKREG r0, 0xFFF9EE9A; - CHECKREG r1, 0x91BCFEC7; - CHECKREG r2, 0xFF256182; - CHECKREG r3, 0xD0910007; - CHECKREG r4, 0xFF1FB35E; - CHECKREG r5, 0xD235910B; - CHECKREG r6, 0xF750102E; - CHECKREG r7, 0x67DE0009; - CHECKREG p1, 0xFFFCF74D; - CHECKREG p2, 0xFF92B0C1; - CHECKREG p3, 0xFF8FD9AF; - CHECKREG p4, 0xFBA80817; - - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - A1 += R1.L * R0.L (M), R6 = ( A0 -= R1.L * R0.L ) (ISS2); - P5 = A1.w; - P1 = A0.w; - A1 = R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (ISS2); - P2 = A0.w; - A1 -= R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (ISS2); - P3 = A0.w; - A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (ISS2); - P4 = A0.w; - CHECKREG r0, 0xFFFB3578; - CHECKREG r1, 0x86BCFEC7; - CHECKREG r2, 0xF2CF3598; - CHECKREG r3, 0x00860007; - CHECKREG r4, 0xF0DDEE08; - CHECKREG r5, 0x1235860B; - CHECKREG r6, 0xF82DF258; - CHECKREG r7, 0x678E0086; - CHECKREG p1, 0xFC16F92C; - CHECKREG p2, 0xFFFD9ABC; - CHECKREG p3, 0xF9679ACC; - CHECKREG p4, 0xF86EF704; - CHECKREG p5, 0xFF82C04D; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R4 = ( A0 = R1.L * R0.L ) (ISS2); - P1 = A0.w; - R0 = ( A0 -= R2.H * R3.L ) (ISS2); - P2 = A0.w; - R2 = ( A0 += R4.H * R5.H ) (ISS2); - P3 = A0.w; - R0 = ( A0 += R6.L * R7.H ) (ISS2); - P4 = A0.w; - CHECKREG r0, 0xF89EF66E; - CHECKREG r1, 0xA1BCF4C7; - CHECKREG r2, 0xF8878042; - CHECKREG r3, 0x00010005; - CHECKREG r4, 0xF97279D6; - CHECKREG r5, 0x1235010B; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xFCB93CEB; - CHECKREG p2, 0xFCBB1787; - CHECKREG p3, 0xFC43C021; - CHECKREG p4, 0xFC4F7B37; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (ISS2); - P1 = A0.w; - R6 = ( A0 = R2.H * R3.L ) (ISS2); - P2 = A0.w; - A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (ISS2); - P3 = A0.w; - R4 = ( A0 += R6.L * R7.H ) (ISS2); - P4 = A0.w; - CHECKREG r0, 0xF8876658; - CHECKREG r1, 0xABD69EC7; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x1EA0F4F8; - CHECKREG r5, 0x1225010B; - CHECKREG r6, 0x00062F18; - CHECKREG r7, 0x678E0561; - CHECKREG p1, 0xE590030B; - CHECKREG p2, 0x0003178C; - CHECKREG p3, 0xFC43B32C; - CHECKREG p4, 0x0F507A7C; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R0 = ( A0 = R5.L * R3.L ) (ISS2); - P1 = A0.w; - A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (ISS2); - P2 = A0.w; - A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (ISS2); - P3 = A0.w; - R6 = ( A0 += R4.L * R6.H ) (ISS2); - P4 = A0.w; - CHECKREG r0, 0xFFF9EE9A; - CHECKREG r1, 0x91BCFEC7; - CHECKREG r2, 0x00D48D18; - CHECKREG r3, 0xD0910007; - CHECKREG r4, 0x00DA3B3C; - CHECKREG r5, 0xD235910B; - CHECKREG r6, 0x06E3E0DC; - CHECKREG r7, 0x67DE0009; - CHECKREG p1, 0xFFFCF74D; - CHECKREG p2, 0x006A468C; - CHECKREG p3, 0x006D1D9E; - CHECKREG p4, 0x0371F06E; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_m.s deleted file mode 100644 index 075704f..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_m.s +++ /dev/null @@ -1,129 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_m/c_dsp32mac_pair_a0_m.dsp -// Spec Reference: dsp32mac pair a0 m (M, MNOP) -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ); - P5 = A1.w; - P1 = A0.w; - A1 = R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ); - P2 = A0.w; - A1 -= R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ); - P3 = A0.w; - A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ); - P4 = A0.w; - CHECKREG r0, 0xFFFB3578; - CHECKREG r1, 0x86BCFEC7; - CHECKREG r2, 0xF2CF3598; - CHECKREG r3, 0x00860007; - CHECKREG r4, 0xF70DA834; - CHECKREG r5, 0x1235860B; - CHECKREG r6, 0xFF221DD6; - CHECKREG r7, 0x678E0086; - CHECKREG p1, 0xFF221DD6; - CHECKREG p2, 0xFFFB3578; - CHECKREG p3, 0xF2CF3598; - CHECKREG p4, 0xF70DA834; - CHECKREG p5, 0xFF910EEB; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R4 = ( A0 -= R1.L * R0.L ); - P1 = A0.w; - R0 = ( A0 = R2.H * R3.L ); - P2 = A0.w; - R2 = ( A0 += R4.H * R5.H ); - P3 = A0.w; - R0 = ( A0 += R6.L * R7.H ); - P4 = A0.w; - CHECKREG r0, 0xFFBC8F22; - CHECKREG r1, 0xA1BCF4C7; - CHECKREG r2, 0xFFA518F6; - CHECKREG r3, 0x00010005; - CHECKREG r4, 0xFD9B2E5E; - CHECKREG r5, 0x1235010B; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xFD9B2E5E; - CHECKREG p2, 0xFFFC4AC8; - CHECKREG p3, 0xFFA518F6; - CHECKREG p4, 0xFFBC8F22; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ); - P1 = A0.w; - R6 = ( A0 -= R2.H * R3.L ); - P2 = A0.w; - A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ); - P3 = A0.w; - R4 = ( A0 += R6.L * R7.H ); - P4 = A0.w; - CHECKREG r0, 0xC39B0E3E; - CHECKREG r1, 0xABD69EC7; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0xA26DF406; - CHECKREG r5, 0x1225010B; - CHECKREG r6, 0xCB19D6FE; - CHECKREG r7, 0x678E0561; - CHECKREG p1, 0xCB200616; - CHECKREG p2, 0xCB19D6FE; - CHECKREG p3, 0xC39B0E3E; - CHECKREG p4, 0xA26DF406; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R0 = ( A0 = R5.L * R3.L ); - P1 = A0.w; - A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ); - P2 = A0.w; - A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ); - P3 = A0.w; - R6 = ( A0 += R4.L * R6.H ); - P4 = A0.w; - CHECKREG r0, 0xFFF9EE9A; - CHECKREG r1, 0x91BCFEC7; - CHECKREG r2, 0x00D48D18; - CHECKREG r3, 0xD0910007; - CHECKREG r4, 0x00DA3B3C; - CHECKREG r5, 0xD235910B; - CHECKREG r6, 0x06E3E0DC; - CHECKREG r7, 0x67DE0009; - CHECKREG p1, 0xFFF9EE9A; - CHECKREG p2, 0x00D48D18; - CHECKREG p3, 0x00DA3B3C; - CHECKREG p4, 0x06E3E0DC; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_s.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_s.s deleted file mode 100644 index 77e36d8..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_s.s +++ /dev/null @@ -1,245 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_s/c_dsp32mac_pair_a0_s.dsp -// Spec Reference: dsp32mac pair a0 S -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (S2RND); - P1 = A0.w; - A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (S2RND); - P2 = A0.w; - A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (S2RND); - P3 = A0.w; - A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (S2RND); - P4 = A0.w; - CHECKREG r0, 0xFFF66AF0; - CHECKREG r1, 0x86BCFEC7; - CHECKREG r2, 0xE59E6B30; - CHECKREG r3, 0x00860007; - CHECKREG r4, 0xD4A4A0C0; - CHECKREG r5, 0x1235860B; - CHECKREG r6, 0x01BBC454; - CHECKREG r7, 0x678E0086; - CHECKREG p1, 0x00DDE22A; - CHECKREG p2, 0xFFFB3578; - CHECKREG p3, 0xF2CF3598; - CHECKREG p4, 0xEA525060; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (S2RND); - P1 = A0.w; - A1 = R2.L * R3.H, R0 = ( A0 = R2.H * R3.L ) (S2RND); - P2 = A0.w; - A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (S2RND); - P3 = A0.w; - A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (S2RND); - P4 = A0.w; - CHECKREG r0, 0xFC6CC6B8; - CHECKREG r1, 0xA1BCF4C7; - CHECKREG r2, 0xFC3DDA60; - CHECKREG r3, 0x00010005; - CHECKREG r4, 0xF2E4F3AC; - CHECKREG r5, 0x1235010B; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xF97279D6; - CHECKREG p2, 0xFFFC4AC8; - CHECKREG p3, 0xFE1EED30; - CHECKREG p4, 0xFE36635C; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - A1 += R1.H * R0.L, R4 = ( A0 -= R1.L * R0.L ) (S2RND); - P1 = A0.w; - A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (S2RND); - P2 = A0.w; - A1 = R4.H * R5.L, R0 = ( A0 -= R4.H * R5.H ) (S2RND); - P3 = A0.w; - A1 += R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (S2RND); - P4 = A0.w; - CHECKREG r0, 0xE314ECC0; - CHECKREG r1, 0xABD69EC7; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x7B7B2740; - CHECKREG r5, 0x1225010B; - CHECKREG r6, 0x000C5E30; - CHECKREG r7, 0x678E0561; - CHECKREG p1, 0x33165D46; - CHECKREG p2, 0x00062F18; - CHECKREG p3, 0xF18A7660; - CHECKREG p4, 0x3DBD93A0; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (S2RND); - P1 = A0.w; - A1 -= R2.H * R1.H, R2 = ( A0 = R2.H * R1.L ) (S2RND); - P2 = A0.w; - A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (S2RND); - P3 = A0.w; - A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (S2RND); - P4 = A0.w; - CHECKREG r0, 0xFFF3DD34; - CHECKREG r1, 0x91BCFEC7; - CHECKREG r2, 0x01A91A30; - CHECKREG r3, 0xD0910007; - CHECKREG r4, 0x01940118; - CHECKREG r5, 0xD235910B; - CHECKREG r6, 0x01CD1598; - CHECKREG r7, 0x67DE0009; - CHECKREG p1, 0xFFF9EE9A; - CHECKREG p2, 0x00D48D18; - CHECKREG p3, 0x00CA008C; - CHECKREG p4, 0x00E68ACC; - - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (S2RND); - P5 = A1.w; - P1 = A0.w; - A1 -= R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (S2RND); - P2 = A0.w; - A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (S2RND); - P3 = A0.w; - A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (S2RND); - P4 = A0.w; - CHECKREG r0, 0xFFF66AF0; - CHECKREG r1, 0x86BCFEC7; - CHECKREG r2, 0xE59E6B30; - CHECKREG r3, 0x00860007; - CHECKREG r4, 0xF69835A0; - CHECKREG r5, 0x1235860B; - CHECKREG r6, 0xFE443BAC; - CHECKREG r7, 0x678E0086; - CHECKREG p1, 0xFF221DD6; - CHECKREG p2, 0xFFFB3578; - CHECKREG p3, 0xF2CF3598; - CHECKREG p4, 0xFB4C1AD0; - CHECKREG p5, 0xFFAFB03F; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R4 = ( A0 = R1.L * R0.L ) (S2RND); - P1 = A0.w; - R0 = ( A0 = R2.H * R3.L ) (S2RND); - P2 = A0.w; - R2 = ( A0 -= R4.H * R5.H ) (S2RND); - P3 = A0.w; - R0 = ( A0 += R6.L * R7.H ) (S2RND); - P4 = A0.w; - CHECKREG r0, 0x03E23D18; - CHECKREG r1, 0xA1BCF4C7; - CHECKREG r2, 0x03B350C0; - CHECKREG r3, 0x00010005; - CHECKREG r4, 0xF2E4F3AC; - CHECKREG r5, 0x1235010B; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xF97279D6; - CHECKREG p2, 0xFFFC4AC8; - CHECKREG p3, 0x01D9A860; - CHECKREG p4, 0x01F11E8C; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (S2RND); - P1 = A0.w; - R6 = ( A0 = R2.H * R3.L ) (S2RND); - P2 = A0.w; - A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (S2RND); - P3 = A0.w; - R4 = ( A0 += R6.L * R7.H ) (S2RND); - P4 = A0.w; - CHECKREG r0, 0xE2113B30; - CHECKREG r1, 0xABD69EC7; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x7A7775B0; - CHECKREG r5, 0x1225010B; - CHECKREG r6, 0x000C5E30; - CHECKREG r7, 0x678E0561; - CHECKREG p1, 0xCB200616; - CHECKREG p2, 0x00062F18; - CHECKREG p3, 0xF1089D98; - CHECKREG p4, 0x3D3BBAD8; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R0 = ( A0 -= R5.L * R3.L ) (S2RND); - P1 = A0.w; - A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (S2RND); - P2 = A0.w; - A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (S2RND); - P3 = A0.w; - R6 = ( A0 += R4.L * R6.H ) (S2RND); - P4 = A0.w; - CHECKREG r0, 0x7A83987C; - CHECKREG r1, 0x91BCFEC7; - CHECKREG r2, 0x01A91A30; - CHECKREG r3, 0xD0910007; - CHECKREG r4, 0x80000000; - CHECKREG r5, 0xD235910B; - CHECKREG r6, 0x80000000; - CHECKREG r7, 0x67DE0009; - CHECKREG p1, 0x3D41CC3E; - CHECKREG p2, 0x00D48D18; - CHECKREG p3, 0x9D6AA7E4; - CHECKREG p4, 0x9D6AA7E4; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_u.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_u.s deleted file mode 100644 index 000fe6b..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_u.s +++ /dev/null @@ -1,245 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_u/c_dsp32mac_pair_a0_u.dsp -// Spec Reference: dsp32mac pair a0 U -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (FU); - P1 = A0.w; - A1 -= R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (FU); - P2 = A0.w; - A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (FU); - P3 = A0.w; - A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (FU); - P4 = A0.w; - CHECKREG r0, 0x00049ABC; - CHECKREG r1, 0x86BCFEC7; - CHECKREG r2, 0x60FC9ACC; - CHECKREG r3, 0x00860007; - CHECKREG r4, 0x60FC9ACC; - CHECKREG r5, 0x1235860B; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x678E0086; - CHECKREG p1, 0x00000000; - CHECKREG p2, 0x00049ABC; - CHECKREG p3, 0x60FC9ACC; - CHECKREG p4, 0x60FC9ACC; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (FU); - P1 = A0.w; - A1 -= R2.L * R3.H, R0 = ( A0 = R2.H * R3.L ) (FU); - P2 = A0.w; - A1 = R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (FU); - P3 = A0.w; - A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (FU); - P4 = A0.w; - CHECKREG r0, 0x0523F7E8; - CHECKREG r1, 0xA1BCF4C7; - CHECKREG r2, 0x05183CD2; - CHECKREG r3, 0x00010005; - CHECKREG r4, 0x47763CEB; - CHECKREG r5, 0x1235010B; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0x47763CEB; - CHECKREG p2, 0x00032564; - CHECKREG p3, 0x05183CD2; - CHECKREG p4, 0x0523F7E8; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ) (FU); - P1 = A0.w; - A1 -= R2.H * R3.L, R6 = ( A0 -= R2.H * R3.L ) (FU); - P2 = A0.w; - A1 = R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (FU); - P3 = A0.w; - A1 += R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (FU); - P4 = A0.w; - CHECKREG r0, 0x2E395300; - CHECKREG r1, 0xABD69EC7; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x8D7C0C72; - CHECKREG r5, 0x1225010B; - CHECKREG r6, 0x2B29EB7F; - CHECKREG r7, 0x678E0561; - CHECKREG p1, 0x2B2D030B; - CHECKREG p2, 0x2B29EB7F; - CHECKREG p3, 0x2E395300; - CHECKREG p4, 0x8D7C0C72; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (FU); - P1 = A0.w; - A1 = R2.H * R1.H, R2 = ( A0 = R2.H * R1.L ) (FU); - P2 = A0.w; - A1 -= R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (FU); - P3 = A0.w; - A1 -= R4.H * R6.H, R6 = ( A0 -= R4.L * R6.H ) (FU); - P4 = A0.w; - CHECKREG r0, 0x0003F74D; - CHECKREG r1, 0x91BCFEC7; - CHECKREG r2, 0xA845468C; - CHECKREG r3, 0xD0910007; - CHECKREG r4, 0xA8467E26; - CHECKREG r5, 0xD235910B; - CHECKREG r6, 0xA1D8A65E; - CHECKREG r7, 0x67DE0009; - CHECKREG p1, 0x0003F74D; - CHECKREG p2, 0xA845468C; - CHECKREG p3, 0xA8467E26; - CHECKREG p4, 0xA1D8A65E; - - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (FU); - P5 = A1.w; - P1 = A0.w; - A1 = R2.L * R3.L (M), R0 = ( A0 -= R2.H * R3.L ) (FU); - P2 = A0.w; - A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (FU); - P3 = A0.w; - A1 -= R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (FU); - P4 = A0.w; - CHECKREG r0, 0x5A49742F; - CHECKREG r1, 0x86BCFEC7; - CHECKREG r2, 0xBB41743F; - CHECKREG r3, 0x00860007; - CHECKREG r4, 0xBC5110E6; - CHECKREG r5, 0x1235860B; - CHECKREG r6, 0x5A4E0EEB; - CHECKREG r7, 0x678E0086; - CHECKREG p1, 0x5A4E0EEB; - CHECKREG p2, 0x5A49742F; - CHECKREG p3, 0xBB41743F; - CHECKREG p4, 0xBC5110E6; - CHECKREG p5, 0x573CE4B9; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R4 = ( A0 -= R1.L * R0.L ) (FU); - P1 = A0.w; - R0 = ( A0 = R2.H * R3.L ) (FU); - P2 = A0.w; - R2 = ( A0 += R4.H * R5.H ) (FU); - P3 = A0.w; - R0 = ( A0 -= R6.L * R7.H ) (FU); - P4 = A0.w; - CHECKREG r0, 0x0846EF70; - CHECKREG r1, 0xA1BCF4C7; - CHECKREG r2, 0x0852AA86; - CHECKREG r3, 0x00010005; - CHECKREG r4, 0x74DAD3FB; - CHECKREG r5, 0x1235010B; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0x74DAD3FB; - CHECKREG p2, 0x00032564; - CHECKREG p3, 0x0852AA86; - CHECKREG p4, 0x0846EF70; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (FU); - P1 = A0.w; - R6 = ( A0 = R2.H * R3.L ) (FU); - P2 = A0.w; - A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (FU); - P3 = A0.w; - R4 = ( A0 += R6.L * R7.H ) (FU); - P4 = A0.w; - CHECKREG r0, 0x03127F0D; - CHECKREG r1, 0xABD69EC7; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x0C98E2B5; - CHECKREG r5, 0x1225010B; - CHECKREG r6, 0x0003178C; - CHECKREG r7, 0x678E0561; - CHECKREG p1, 0x2B2D030B; - CHECKREG p2, 0x0003178C; - CHECKREG p3, 0x03127F0D; - CHECKREG p4, 0x0C98E2B5; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R0 = ( A0 = R5.L * R3.L ) (FU); - P1 = A0.w; - A1 -= R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (FU); - P2 = A0.w; - A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (FU); - P3 = A0.w; - R6 = ( A0 += R4.L * R6.H ) (FU); - P4 = A0.w; - CHECKREG r0, 0x0003F74D; - CHECKREG r1, 0x91BCFEC7; - CHECKREG r2, 0xA845468C; - CHECKREG r3, 0xD0910007; - CHECKREG r4, 0xA8440EF2; - CHECKREG r5, 0xD235910B; - CHECKREG r6, 0xA9070C4A; - CHECKREG r7, 0x67DE0009; - CHECKREG p1, 0x0003F74D; - CHECKREG p2, 0xA845468C; - CHECKREG p3, 0xA8440EF2; - CHECKREG p4, 0xA9070C4A; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1.s deleted file mode 100644 index 36d8e2a..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1.s +++ /dev/null @@ -1,127 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1/c_dsp32mac_pair_a1.dsp -// Spec Reference: dsp32mac pair a1 -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L; - P1 = A1.w; - R1 = ( A1 = R2.L * R3.L ), A0 += R2.H * R3.L; - P2 = A1.w; - R3 = ( A1 -= R7.L * R4.L ), A0 += R7.H * R4.H; - P3 = A1.w; - R5 = ( A1 -= R6.L * R5.L ), A0 -= R6.L * R5.H; - P4 = A1.w; - CHECKREG r0, 0x63545ABD; - CHECKREG r1, 0x0004BA9E; - CHECKREG r2, 0xA8645679; - CHECKREG r3, 0xE8616512; - CHECKREG r4, 0xEFB86569; - CHECKREG r5, 0xF0688FB4; - CHECKREG r6, 0x000C086D; - CHECKREG r7, 0xFF221DD6; - CHECKREG p1, 0xFF221DD6; - CHECKREG p2, 0x0004BA9E; - CHECKREG p3, 0xE8616512; - CHECKREG p4, 0xF0688FB4; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R5 = ( A1 += R1.L * R0.H ), A0 -= R1.L * R0.L; - P1 = A1.w; - R1 = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L; - P2 = A1.w; - R3 = ( A1 -= R4.L * R5.H ), A0 += R4.H * R5.H; - P3 = A1.w; - R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H; - P4 = A1.w; - CHECKREG r0, 0x98764ABD; - CHECKREG r1, 0x012F2306; - CHECKREG r2, 0xA1145649; - CHECKREG r3, 0x0117ACDA; - CHECKREG r4, 0xEFBC1569; - CHECKREG r5, 0xF97C8728; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xF97C8728; - CHECKREG p2, 0x0000AC92; - CHECKREG p3, 0x0117ACDA; - CHECKREG p4, 0x012F2306; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - R5 = ( A1 += R1.H * R0.L ), A0 = R1.L * R0.L; - P1 = A1.w; - R7 = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L; - P2 = A1.w; - R1 = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H; - P3 = A1.w; - R5 = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H; - P4 = A1.w; - CHECKREG r0, 0x7136459D; - CHECKREG r1, 0xCABE16DA; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0xEF9C1569; - CHECKREG r5, 0xCABE9156; - CHECKREG r6, 0x0003401D; - CHECKREG r7, 0xD363146A; - CHECKREG p1, 0xD3694382; - CHECKREG p2, 0xD363146A; - CHECKREG p3, 0xCABE16DA; - CHECKREG p4, 0xCABE9156; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L; - P1 = A1.w; - R3 = ( A1 = R2.H * R1.H ), A0 -= R2.H * R1.L; - P2 = A1.w; - R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H; - P3 = A1.w; - R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H; - P4 = A1.w; - CHECKREG r0, 0x123489BD; - CHECKREG r1, 0xDBB6D160; - CHECKREG r2, 0xA9145679; - CHECKREG r3, 0x18A4A070; - CHECKREG r4, 0xEDB91569; - CHECKREG r5, 0x09DF3640; - CHECKREG r6, 0x0D0C0999; - CHECKREG r7, 0x08024998; - CHECKREG p1, 0xDBB6D160; - CHECKREG p2, 0x18A4A070; - CHECKREG p3, 0x09DF3640; - CHECKREG p4, 0x08024998; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_i.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_i.s deleted file mode 100644 index 8ac571d..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_i.s +++ /dev/null @@ -1,243 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_i/c_dsp32mac_pair_a1_i.dsp -// Spec Reference: dsp32mac pair a1 I -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half - imm32 r0, 0x93545abd; - imm32 r1, 0x89bcfec7; - imm32 r2, 0xa8945679; - imm32 r3, 0x00890007; - imm32 r4, 0xefb89569; - imm32 r5, 0x1235890b; - imm32 r6, 0x000c089d; - imm32 r7, 0x678e0089; - R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L (IS); - P1 = A1.w; - R1 = ( A1 = R2.L * R3.L ), A0 -= R2.H * R3.L (IS); - P2 = A1.w; - R3 = ( A1 = R7.L * R4.L ), A0 += R7.H * R4.H (IS); - P3 = A1.w; - R5 = ( A1 += R6.L * R5.L ), A0 += R6.L * R5.H (IS); - P4 = A1.w; - CHECKREG r0, 0x93545ABD; - CHECKREG r1, 0x00025D4F; - CHECKREG r2, 0xA8945679; - CHECKREG r3, 0xF9C9E563; - CHECKREG r4, 0xEFB89569; - CHECKREG r5, 0xF5C94922; - CHECKREG r6, 0x000C089D; - CHECKREG r7, 0xFF910EEB; - CHECKREG p1, 0xFF910EEB; - CHECKREG p2, 0x00025D4F; - CHECKREG p3, 0xF9C9E563; - CHECKREG p4, 0xF5C94922; - - imm32 r0, 0x98464abd; - imm32 r1, 0xa1b5f4c7; - imm32 r2, 0xa1146649; - imm32 r3, 0x00010805; - imm32 r4, 0xefbc1599; - imm32 r5, 0x12350100; - imm32 r6, 0x200c001d; - imm32 r7, 0x628e0001; - R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (IS); - P1 = A1.w; - R1 = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS); - P2 = A1.w; - R3 = ( A1 = R4.L * R5.H ), A0 -= R4.H * R5.H (IS); - P3 = A1.w; - R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (IS); - P4 = A1.w; - CHECKREG r0, 0x98464ABD; - CHECKREG r1, 0xFF90BFE3; - CHECKREG r2, 0xA1146649; - CHECKREG r3, 0xFF8595CD; - CHECKREG r4, 0xEFBC1599; - CHECKREG r5, 0xFA555F8C; - CHECKREG r6, 0x200C001D; - CHECKREG r7, 0x628E0001; - CHECKREG p1, 0xFA555F8C; - CHECKREG p2, 0x00006649; - CHECKREG p3, 0xFF8595CD; - CHECKREG p4, 0xFF90BFE3; - - imm32 r0, 0x713a459d; - imm32 r1, 0xabd6aec7; - imm32 r2, 0x7a145a79; - imm32 r3, 0x08a100a7; - imm32 r4, 0xef9a156a; - imm32 r5, 0x1225a10b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0a61; - R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (IS); - P1 = A1.w; - R7 = ( A1 -= R2.H * R3.L ), A0 = R2.H * R3.L (IS); - P2 = A1.w; - R1 = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IS); - P3 = A1.w; - R5 = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H (IS); - P4 = A1.w; - CHECKREG r0, 0x713A459D; - CHECKREG r1, 0xE54D2A3B; - CHECKREG r2, 0x7A145A79; - CHECKREG r3, 0x08A100A7; - CHECKREG r4, 0xEF9A156A; - CHECKREG r5, 0xE54DB17A; - CHECKREG r6, 0x0003401D; - CHECKREG r7, 0xE85E2D15; - CHECKREG p1, 0xE8ADD021; - CHECKREG p2, 0xE85E2D15; - CHECKREG p3, 0xE54D2A3B; - CHECKREG p4, 0xE54DB17A; - - imm32 r0, 0x773489bd; - imm32 r1, 0x917cfec7; - imm32 r2, 0xa9177679; - imm32 r3, 0xd0910777; - imm32 r4, 0xedb91579; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d077999; - imm32 r7, 0x677e0709; - R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (IS); - P1 = A1.w; - R3 = ( A1 -= R2.H * R1.H ), A0 = R2.H * R1.L (IS); - P2 = A1.w; - R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H (IS); - P3 = A1.w; - R7 = ( A1 += R4.H * R6.H ), A0 -= R4.L * R6.H (IS); - P4 = A1.w; - CHECKREG r0, 0x773489BD; - CHECKREG r1, 0xEDC9D17F; - CHECKREG r2, 0xA9177679; - CHECKREG r3, 0xE79AC370; - CHECKREG r4, 0xEDB91579; - CHECKREG r5, 0xB76A2BD8; - CHECKREG r6, 0x0D077999; - CHECKREG r7, 0xB67C10E7; - CHECKREG p1, 0xEDC9D17F; - CHECKREG p2, 0xE79AC370; - CHECKREG p3, 0xB76A2BD8; - CHECKREG p4, 0xB67C10E7; - - imm32 r0, 0x83547abd; - imm32 r1, 0x88bc8ec7; - imm32 r2, 0xa8895679; - imm32 r3, 0x00080007; - imm32 r4, 0xe6b86569; - imm32 r5, 0x1A35860b; - imm32 r6, 0x000c896d; - imm32 r7, 0x67Be0096; - R7 = ( A1 += R1.L * R0.L ) (IS); - P1 = A1.w; - R1 = ( A1 = R2.H * R3.L ) (IS); - P2 = A1.w; - R3 = ( A1 = R7.L * R4.H ) (IS); - P3 = A1.w; - R5 = ( A1 += R6.H * R5.H ) (IS); - P4 = A1.w; - CHECKREG r0, 0x83547ABD; - CHECKREG r1, 0xFFFD9BBF; - CHECKREG r2, 0xA8895679; - CHECKREG r3, 0xF81E0AF0; - CHECKREG r4, 0xE6B86569; - CHECKREG r5, 0xF81F456C; - CHECKREG r6, 0x000C896D; - CHECKREG r7, 0x80334FD2; - CHECKREG p1, 0x80334FD2; - CHECKREG p2, 0xFFFD9BBF; - CHECKREG p3, 0xF81E0AF0; - CHECKREG p4, 0xF81F456C; - - imm32 r0, 0x9aa64abd; - imm32 r1, 0xa1baf4c7; - imm32 r2, 0xb114a649; - imm32 r3, 0x0b010005; - imm32 r4, 0xefbcdb69; - imm32 r5, 0x123501bb; - imm32 r6, 0x000c0d1b; - imm32 r7, 0x678e0d01; - R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (IS); - P1 = A1.w; - R1 = ( A1 = R2.L * R3.H ) (M), A0 -= R2.H * R3.L (IS); - P2 = A1.w; - R3 = ( A1 -= R4.L * R5.H ) (M), A0 += R4.H * R5.H (IS); - P3 = A1.w; - R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (IS); - P4 = A1.w; - CHECKREG r0, 0x9AA64ABD; - CHECKREG r1, 0x23F08194; - CHECKREG r2, 0xB114A649; - CHECKREG r3, 0x1EA35F9A; - CHECKREG r4, 0xEFBCDB69; - CHECKREG r5, 0xF157B476; - CHECKREG r6, 0x000C0D1B; - CHECKREG r7, 0x678E0D01; - CHECKREG p1, 0xF157B476; - CHECKREG p2, 0xFC24C949; - CHECKREG p3, 0x1EA35F9A; - CHECKREG p4, 0x23F08194; - - imm32 r0, 0xd136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0xdd010007; - imm32 r4, 0xeddc1569; - imm32 r5, 0x122d010b; - imm32 r6, 0x00e3d01d; - imm32 r7, 0x678e0d61; - R5 = A1 , A0 -= R1.L * R0.L (IS); - P1 = A1.w; - R7 = A1 , A0 = R2.H * R3.L (IS); - P2 = A1.w; - R1 = A1 , A0 += R4.H * R5.H (IS); - P3 = A1.w; - R5 = A1 , A0 += R6.L * R7.H (IS); - P4 = A1.w; - CHECKREG r0, 0xD136459D; - CHECKREG r1, 0x23F08194; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0xDD010007; - CHECKREG r4, 0xEDDC1569; - CHECKREG r5, 0x23F08194; - CHECKREG r6, 0x00E3D01D; - CHECKREG r7, 0x23F08194; - CHECKREG p1, 0x23F08194; - CHECKREG p2, 0x23F08194; - CHECKREG p3, 0x23F08194; - CHECKREG p4, 0x23F08194; - - imm32 r0, 0x125489bd; - imm32 r1, 0x91b5fec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910507; - imm32 r4, 0x34567859; - imm32 r5, 0xd2359105; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = ( A1 += R5.H * R3.H ) (M,IS); - P1 = A1.w; - R3 = ( A1 = R2.H * R1.H ) (M,IS); - P2 = A1.w; - R5 = ( A1 -= R7.H * R0.H ) (M,IS); - P3 = A1.w; - R7 = ( A1 += R4.H * R6.H ) (M,IS); - P4 = A1.w; - CHECKREG r0, 0x125489BD; - CHECKREG r1, 0xFEA1A199; - CHECKREG r2, 0xA9145679; - CHECKREG r3, 0xA98B2D94; - CHECKREG r4, 0x34567859; - CHECKREG r5, 0xA21B7CBC; - CHECKREG r6, 0x0D0C0999; - CHECKREG r7, 0xA4C64EC4; - CHECKREG p1, 0xFEA1A199; - CHECKREG p2, 0xA98B2D94; - CHECKREG p3, 0xA21B7CBC; - CHECKREG p4, 0xA4C64EC4; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_is.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_is.s deleted file mode 100644 index 58d9735..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_is.s +++ /dev/null @@ -1,243 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_is/c_dsp32mac_pair_a1_is.dsp -// Spec Reference: dsp32mac pair a1 IS -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half - imm32 r0, 0x93545abd; - imm32 r1, 0x89bcfec7; - imm32 r2, 0xa8945679; - imm32 r3, 0x00890007; - imm32 r4, 0xefb89569; - imm32 r5, 0x1235890b; - imm32 r6, 0x000c089d; - imm32 r7, 0x678e0089; - R7 = ( A1 += R5.L * R0.L ), A0 = R5.L * R0.L (ISS2); - P1 = A1.w; - R1 = ( A1 = R4.L * R3.L ), A0 = R4.H * R3.L (ISS2); - P2 = A1.w; - R3 = ( A1 = R7.L * R2.L ), A0 += R7.H * R2.H (ISS2); - P3 = A1.w; - R5 = ( A1 += R6.L * R1.L ), A0 += R6.L * R1.H (ISS2); - P4 = A1.w; - CHECKREG r0, 0x93545ABD; - CHECKREG r1, 0xFFFA2BBE; - CHECKREG r2, 0xA8945679; - CHECKREG r3, 0x0F06AE9C; - CHECKREG r4, 0xEFB89569; - CHECKREG r5, 0x11F835A8; - CHECKREG r6, 0x000C089D; - CHECKREG r7, 0xABAC163E; - CHECKREG p1, 0xD5D60B1F; - CHECKREG p2, 0xFFFD15DF; - CHECKREG p3, 0x0783574E; - CHECKREG p4, 0x08FC1AD4; - - imm32 r0, 0x98464abd; - imm32 r1, 0xa1b5f4c7; - imm32 r2, 0xa1146649; - imm32 r3, 0x00010805; - imm32 r4, 0xefbc1599; - imm32 r5, 0x12350100; - imm32 r6, 0x200c001d; - imm32 r7, 0x628e0001; - R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (ISS2); - P1 = A1.w; - R1 = ( A1 -= R5.L * R3.H ), A0 = R5.H * R3.L (ISS2); - P2 = A1.w; - R3 = ( A1 -= R4.L * R2.H ), A0 += R4.H * R2.H (ISS2); - P3 = A1.w; - R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (ISS2); - P4 = A1.w; - CHECKREG r0, 0x98464ABD; - CHECKREG r1, 0x2B2A1FC8; - CHECKREG r2, 0xA1146649; - CHECKREG r3, 0x2B13CB9C; - CHECKREG r4, 0xEFBC1599; - CHECKREG r5, 0x1B10627C; - CHECKREG r6, 0x200C001D; - CHECKREG r7, 0x628E0001; - CHECKREG p1, 0x0D88313E; - CHECKREG p2, 0x0D87CEC2; - CHECKREG p3, 0x1589E5CE; - CHECKREG p4, 0x15950FE4; - - imm32 r0, 0x713a459d; - imm32 r1, 0xabd6aec7; - imm32 r2, 0x7a145a79; - imm32 r3, 0x08a100a7; - imm32 r4, 0xef9a156a; - imm32 r5, 0x1225a10b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0a61; - R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (ISS2); - P1 = A1.w; - R7 = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L (ISS2); - P2 = A1.w; - R1 = ( A1 = R7.H * R5.L ), A0 += R7.H * R5.H (ISS2); - P3 = A1.w; - R5 = ( A1 += R6.H * R4.L ), A0 += R6.L * R4.H (ISS2); - P4 = A1.w; - CHECKREG r0, 0x713A459D; - CHECKREG r1, 0xFE604820; - CHECKREG r2, 0x7A145A79; - CHECKREG r3, 0x08A100A7; - CHECKREG r4, 0xEF9A156A; - CHECKREG r5, 0xFE60C89C; - CHECKREG r6, 0x0003401D; - CHECKREG r7, 0xFCC4FA2C; - CHECKREG p1, 0xFEB22022; - CHECKREG p2, 0xFE627D16; - CHECKREG p3, 0xFF302410; - CHECKREG p4, 0xFF30644E; - - imm32 r0, 0x773489bd; - imm32 r1, 0x917cfec7; - imm32 r2, 0xa9177679; - imm32 r3, 0xd0910777; - imm32 r4, 0xedb91579; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d077999; - imm32 r7, 0x677e0709; - R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (ISS2); - P1 = A1.w; - R3 = ( A1 = R2.H * R1.H ), A0 = R2.H * R1.L (ISS2); - P2 = A1.w; - R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H (ISS2); - P3 = A1.w; - R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (ISS2); - P4 = A1.w; - CHECKREG r0, 0x773489BD; - CHECKREG r1, 0x0F5908A6; - CHECKREG r2, 0xA9177679; - CHECKREG r3, 0xF59443FE; - CHECKREG r4, 0xEDB91579; - CHECKREG r5, 0x953314CE; - CHECKREG r6, 0x0D077999; - CHECKREG r7, 0x9356DEEC; - CHECKREG p1, 0x07AC8453; - CHECKREG p2, 0xFACA21FF; - CHECKREG p3, 0xCA998A67; - CHECKREG p4, 0xC9AB6F76; - - imm32 r0, 0x83547abd; - imm32 r1, 0x88bc8ec7; - imm32 r2, 0xa8895679; - imm32 r3, 0x00080007; - imm32 r4, 0xe6b86569; - imm32 r5, 0x1A35860b; - imm32 r6, 0x000c896d; - imm32 r7, 0x67Be0096; - R7 = ( A1 += R1.L * R0.L ) (ISS2); - P1 = A1.w; - R1 = ( A1 = R2.H * R3.L ) (ISS2); - P2 = A1.w; - R3 = ( A1 -= R7.L * R4.H ) (ISS2); - P3 = A1.w; - R5 = ( A1 += R6.H * R5.H ) (ISS2); - P4 = A1.w; - CHECKREG r0, 0x83547ABD; - CHECKREG r1, 0xFFFB377E; - CHECKREG r2, 0xA8895679; - CHECKREG r3, 0xFFFB377E; - CHECKREG r4, 0xE6B86569; - CHECKREG r5, 0xFFFDAC76; - CHECKREG r6, 0x000C896D; - CHECKREG r7, 0x80000000; - CHECKREG p1, 0x9362AE61; - CHECKREG p2, 0xFFFD9BBF; - CHECKREG p3, 0xFFFD9BBF; - CHECKREG p4, 0xFFFED63B; - - imm32 r0, 0x9aa64abd; - imm32 r1, 0xa1baf4c7; - imm32 r2, 0xb114a649; - imm32 r3, 0x0b010005; - imm32 r4, 0xefbcdb69; - imm32 r5, 0x123501bb; - imm32 r6, 0x000c0d1b; - imm32 r7, 0x678e0d01; - R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (ISS2); - P1 = A1.w; - R1 = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (ISS2); - P2 = A1.w; - R3 = ( A1 = R4.L * R5.H ) (M), A0 += R4.H * R5.H (ISS2); - P3 = A1.w; - R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (ISS2); - P4 = A1.w; - CHECKREG r0, 0x9AA64ABD; - CHECKREG r1, 0xC54D5630; - CHECKREG r2, 0xB114A649; - CHECKREG r3, 0xBAB3123C; - CHECKREG r4, 0xEFBCDB69; - CHECKREG r5, 0xF26E8A8A; - CHECKREG r6, 0x000C0D1B; - CHECKREG r7, 0x678E0D01; - CHECKREG p1, 0xF9374545; - CHECKREG p2, 0xFD127BFC; - CHECKREG p3, 0xDD59891E; - CHECKREG p4, 0xE2A6AB18; - - imm32 r0, 0xd136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0xdd010007; - imm32 r4, 0xeddc1569; - imm32 r5, 0x122d010b; - imm32 r6, 0x00e3d01d; - imm32 r7, 0x678e0d61; - R5 = A1 , A0 -= R1.L * R0.L (ISS2); - P1 = A1.w; - R7 = A1 , A0 = R2.H * R3.L (ISS2); - P2 = A1.w; - R1 = A1 , A0 += R4.H * R5.H (ISS2); - P3 = A1.w; - R5 = A1 , A0 += R6.L * R7.H (ISS2); - P4 = A1.w; - CHECKREG r0, 0xD136459D; - CHECKREG r1, 0xC54D5630; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0xDD010007; - CHECKREG r4, 0xEDDC1569; - CHECKREG r5, 0xC54D5630; - CHECKREG r6, 0x00E3D01D; - CHECKREG r7, 0xC54D5630; - CHECKREG p1, 0xE2A6AB18; - CHECKREG p2, 0xE2A6AB18; - CHECKREG p3, 0xE2A6AB18; - CHECKREG p4, 0xE2A6AB18; - - imm32 r0, 0x125489bd; - imm32 r1, 0x91b5fec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910507; - imm32 r4, 0x34567859; - imm32 r5, 0xd2359105; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = ( A1 += R5.H * R3.H ) (M,ISS2); - P1 = A1.w; - R3 = ( A1 = R2.H * R1.H ) (M,ISS2); - P2 = A1.w; - R5 = ( A1 -= R7.H * R0.H ) (M,ISS2); - P3 = A1.w; - R7 = ( A1 += R4.H * R6.H ) (M,ISS2); - P4 = A1.w; - CHECKREG r0, 0x125489BD; - CHECKREG r1, 0x80000000; - CHECKREG r2, 0xA9145679; - CHECKREG r3, 0xA9140000; - CHECKREG r4, 0x34567859; - CHECKREG r5, 0x9A349E50; - CHECKREG r6, 0x0D0C0999; - CHECKREG r7, 0x9F8A4260; - CHECKREG p1, 0xBD57CB1D; - CHECKREG p2, 0xD48A0000; - CHECKREG p3, 0xCD1A4F28; - CHECKREG p4, 0xCFC52130; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_m.s deleted file mode 100644 index f93e7a5..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_m.s +++ /dev/null @@ -1,127 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_m/c_dsp32mac_pair_a1_m.dsp -// Spec Reference: dsp32mac pair a1 M MNOP -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half - imm32 r0, 0x63547abd; - imm32 r1, 0x86bc8ec7; - imm32 r2, 0xa8695679; - imm32 r3, 0x00060007; - imm32 r4, 0xe6b86569; - imm32 r5, 0x1A35860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x67Be0086; - R7 = ( A1 += R1.L * R0.L ); - P1 = A1.w; - R1 = ( A1 -= R2.H * R3.L ); - P2 = A1.w; - R3 = ( A1 = R7.L * R4.H ); - P3 = A1.w; - R5 = ( A1 += R6.H * R5.H ); - P4 = A1.w; - CHECKREG r0, 0x63547ABD; - CHECKREG r1, 0x93734818; - CHECKREG r2, 0xA8695679; - CHECKREG r3, 0xE7256BA0; - CHECKREG r4, 0xE6B86569; - CHECKREG r5, 0xE727E098; - CHECKREG r6, 0x000C086D; - CHECKREG r7, 0x936E7DD6; - CHECKREG p1, 0x936E7DD6; - CHECKREG p2, 0x93734818; - CHECKREG p3, 0xE7256BA0; - CHECKREG p4, 0xE727E098; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xb1145649; - imm32 r3, 0x0b010005; - imm32 r4, 0xefbcbb69; - imm32 r5, 0x123501bb; - imm32 r6, 0x000c001b; - imm32 r7, 0x678e0001; - R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L; - P1 = A1.w; - R1 = ( A1 = R2.L * R3.H ) (M), A0 = R2.H * R3.L; - P2 = A1.w; - R3 = ( A1 -= R4.L * R5.H ) (M), A0 += R4.H * R5.H; - P3 = A1.w; - R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H; - P4 = A1.w; - CHECKREG r0, 0x98764ABD; - CHECKREG r1, 0x3FE4AC0B; - CHECKREG r2, 0xB1145649; - CHECKREG r3, 0x3FD9C011; - CHECKREG r4, 0xEFBCBB69; - CHECKREG r5, 0xE078DC52; - CHECKREG r6, 0x000C001B; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xE078DC52; - CHECKREG p2, 0x03B57949; - CHECKREG p3, 0x3FD9C011; - CHECKREG p4, 0x3FE4AC0B; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0xd8010007; - imm32 r4, 0xeddc1569; - imm32 r5, 0x122d010b; - imm32 r6, 0x0003d01d; - imm32 r7, 0x678e0d61; - R5 = A1 , A0 = R1.L * R0.L; - P1 = A1.w; - R7 = A1 , A0 -= R2.H * R3.L; - P2 = A1.w; - R1 = A1 , A0 += R4.H * R5.H; - P3 = A1.w; - R5 = A1 , A0 += R6.L * R7.H; - P4 = A1.w; - CHECKREG r0, 0x7136459D; - CHECKREG r1, 0x3FE4AC0B; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0xD8010007; - CHECKREG r4, 0xEDDC1569; - CHECKREG r5, 0x3FE4AC0B; - CHECKREG r6, 0x0003D01D; - CHECKREG r7, 0x3FE4AC0B; - CHECKREG p1, 0x3FE4AC0B; - CHECKREG p2, 0x3FE4AC0B; - CHECKREG p3, 0x3FE4AC0B; - CHECKREG p4, 0x3FE4AC0B; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0x34567899; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = ( A1 += R5.H * R3.H ) (M); - P1 = A1.w; - R3 = ( A1 = R2.H * R1.H ) (M); - P2 = A1.w; - R5 = ( A1 -= R7.H * R0.H ) (M); - P3 = A1.w; - R7 = ( A1 += R4.H * R6.H ) (M); - P4 = A1.w; - CHECKREG r0, 0x123489BD; - CHECKREG r1, 0x1A95CC10; - CHECKREG r2, 0xA9145679; - CHECKREG r3, 0xF6F970A4; - CHECKREG r4, 0x34567899; - CHECKREG r5, 0xEF96BB8C; - CHECKREG r6, 0x0D0C0999; - CHECKREG r7, 0xF2418D94; - CHECKREG p1, 0x1A95CC10; - CHECKREG p2, 0xF6F970A4; - CHECKREG p3, 0xEF96BB8C; - CHECKREG p4, 0xF2418D94; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_s.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_s.s deleted file mode 100644 index 2cc1ec6..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_s.s +++ /dev/null @@ -1,243 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_s/c_dsp32mac_pair_a1_s.dsp -// Spec Reference: dsp32mac pair a1 S -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half - imm32 r0, 0x93545abd; - imm32 r1, 0x89bcfec7; - imm32 r2, 0xa8945679; - imm32 r3, 0x00890007; - imm32 r4, 0xefb89569; - imm32 r5, 0x1235890b; - imm32 r6, 0x000c089d; - imm32 r7, 0x678e0089; - R7 = ( A1 += R5.L * R0.L ), A0 = R5.L * R0.L (S2RND); - P1 = A1.w; - R1 = ( A1 -= R4.L * R3.L ), A0 = R4.H * R3.L (S2RND); - P2 = A1.w; - R3 = ( A1 -= R7.L * R2.L ), A0 += R7.H * R2.H (S2RND); - P3 = A1.w; - R5 = ( A1 += R6.L * R1.L ), A0 += R6.L * R1.H (S2RND); - P4 = A1.w; - CHECKREG r0, 0x93545ABD; - CHECKREG r1, 0x80000000; - CHECKREG r2, 0xA8945679; - CHECKREG r3, 0x80000000; - CHECKREG r4, 0xEFB89569; - CHECKREG r5, 0x80000000; - CHECKREG r6, 0x000C089D; - CHECKREG r7, 0x80000000; - CHECKREG p1, 0xABAC163E; - CHECKREG p2, 0xABB1EA80; - CHECKREG p3, 0xABB1EA80; - CHECKREG p4, 0xABB1EA80; - - imm32 r0, 0x98464abd; - imm32 r1, 0xa1b5f4c7; - imm32 r2, 0xa1146649; - imm32 r3, 0x00010805; - imm32 r4, 0xefbc1599; - imm32 r5, 0x12350100; - imm32 r6, 0x200c001d; - imm32 r7, 0x628e0001; - R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (S2RND); - P1 = A1.w; - R1 = ( A1 = R5.L * R3.H ), A0 -= R5.H * R3.L (S2RND); - P2 = A1.w; - R3 = ( A1 = R4.L * R2.H ), A0 += R4.H * R2.H (S2RND); - P3 = A1.w; - R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (S2RND); - P4 = A1.w; - CHECKREG r0, 0x98464ABD; - CHECKREG r1, 0xE0244C28; - CHECKREG r2, 0xA1146649; - CHECKREG r3, 0xDFF7A3D0; - CHECKREG r4, 0xEFBC1599; - CHECKREG r5, 0x80000000; - CHECKREG r6, 0x200C001D; - CHECKREG r7, 0x628E0001; - CHECKREG p1, 0xB4CA1754; - CHECKREG p2, 0x00000000; - CHECKREG p3, 0xEFFBD1E8; - CHECKREG p4, 0xF0122614; - - imm32 r0, 0x713a459d; - imm32 r1, 0xabd6aec7; - imm32 r2, 0x7a145a79; - imm32 r3, 0x08a100a7; - imm32 r4, 0xef9a156a; - imm32 r5, 0x1225a10b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0a61; - R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (S2RND); - P1 = A1.w; - R7 = ( A1 = R2.H * R3.L ), A0 -= R2.H * R3.L (S2RND); - P2 = A1.w; - R1 = ( A1 = R7.H * R5.L ), A0 += R7.H * R5.H (S2RND); - P3 = A1.w; - R5 = ( A1 += R6.H * R4.L ), A0 += R6.L * R4.H (S2RND); - P4 = A1.w; - CHECKREG r0, 0x713A459D; - CHECKREG r1, 0xFDC53700; - CHECKREG r2, 0x7A145A79; - CHECKREG r3, 0x08A100A7; - CHECKREG r4, 0xEF9A156A; - CHECKREG r5, 0xFDC637F8; - CHECKREG r6, 0x0003401D; - CHECKREG r7, 0x013E8C30; - CHECKREG p1, 0xC24C4690; - CHECKREG p2, 0x009F4618; - CHECKREG p3, 0xFEE29B80; - CHECKREG p4, 0xFEE31BFC; - - imm32 r0, 0x773489bd; - imm32 r1, 0x917cfec7; - imm32 r2, 0xa9177679; - imm32 r3, 0xd0910777; - imm32 r4, 0xedb91579; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d077999; - imm32 r7, 0x677e0709; - R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (S2RND); - P1 = A1.w; - R3 = ( A1 -= R2.H * R1.H ), A0 = R2.H * R1.L (S2RND); - P2 = A1.w; - R5 = ( A1 = R7.H * R0.H ), A0 += R7.H * R0.H (S2RND); - P3 = A1.w; - R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (S2RND); - P4 = A1.w; - CHECKREG r0, 0x773489BD; - CHECKREG r1, 0x1FB6B80C; - CHECKREG r2, 0xA9177679; - CHECKREG r3, 0x4AC6BAA4; - CHECKREG r4, 0xEDB91579; - CHECKREG r5, 0x7FFFFFFF; - CHECKREG r6, 0x0D077999; - CHECKREG r7, 0x7FFFFFFF; - CHECKREG p1, 0x0FDB5C06; - CHECKREG p2, 0x25635D52; - CHECKREG p3, 0x60612F30; - CHECKREG p4, 0x5E84F94E; - - imm32 r0, 0x83547abd; - imm32 r1, 0x88bc8ec7; - imm32 r2, 0xa8895679; - imm32 r3, 0x00080007; - imm32 r4, 0xe6b86569; - imm32 r5, 0x1A35860b; - imm32 r6, 0x000c896d; - imm32 r7, 0x67Be0096; - R7 = ( A1 += R1.L * R0.L ) (S2RND); - P1 = A1.w; - R1 = ( A1 -= R2.H * R3.L ) (S2RND); - P2 = A1.w; - R3 = ( A1 = R7.L * R4.H ) (S2RND); - P3 = A1.w; - R5 = ( A1 += R6.H * R5.H ) (S2RND); - P4 = A1.w; - CHECKREG r0, 0x83547ABD; - CHECKREG r1, 0xE3F07F4C; - CHECKREG r2, 0xA8895679; - CHECKREG r3, 0x06FFCF00; - CHECKREG r4, 0xE6B86569; - CHECKREG r5, 0x0704B8F0; - CHECKREG r6, 0x000C896D; - CHECKREG r7, 0xE3E6EE48; - CHECKREG p1, 0xF1F37724; - CHECKREG p2, 0xF1F83FA6; - CHECKREG p3, 0x037FE780; - CHECKREG p4, 0x03825C78; - - imm32 r0, 0x9aa64abd; - imm32 r1, 0xa1baf4c7; - imm32 r2, 0xb114a649; - imm32 r3, 0x0b010005; - imm32 r4, 0xefbcdb69; - imm32 r5, 0x123501bb; - imm32 r6, 0x000c0d1b; - imm32 r7, 0x678e0d01; - R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (S2RND); - P1 = A1.w; - R1 = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (S2RND); - P2 = A1.w; - R3 = ( A1 -= R4.L * R5.H ) (M), A0 -= R4.H * R5.H (S2RND); - P3 = A1.w; - R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (S2RND); - P4 = A1.w; - CHECKREG r0, 0x9AA64ABD; - CHECKREG r1, 0x5315786C; - CHECKREG r2, 0xB114A649; - CHECKREG r3, 0x487B3478; - CHECKREG r4, 0xEFBCDB69; - CHECKREG r5, 0xF9759704; - CHECKREG r6, 0x000C0D1B; - CHECKREG r7, 0x678E0D01; - CHECKREG p1, 0xFCBACB82; - CHECKREG p2, 0x00960239; - CHECKREG p3, 0x243D9A3C; - CHECKREG p4, 0x298ABC36; - - imm32 r0, 0xd136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0xdd010007; - imm32 r4, 0xeddc1569; - imm32 r5, 0x122d010b; - imm32 r6, 0x00e3d01d; - imm32 r7, 0x678e0d61; - R5 = A1 , A0 -= R1.L * R0.L (S2RND); - P1 = A1.w; - R7 = A1 , A0 = R2.H * R3.L (S2RND); - P2 = A1.w; - R1 = A1 , A0 -= R4.H * R5.H (S2RND); - P3 = A1.w; - R5 = A1 , A0 += R6.L * R7.H (S2RND); - P4 = A1.w; - CHECKREG r0, 0xD136459D; - CHECKREG r1, 0x5315786C; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0xDD010007; - CHECKREG r4, 0xEDDC1569; - CHECKREG r5, 0x5315786C; - CHECKREG r6, 0x00E3D01D; - CHECKREG r7, 0x5315786C; - CHECKREG p1, 0x298ABC36; - CHECKREG p2, 0x298ABC36; - CHECKREG p3, 0x298ABC36; - CHECKREG p4, 0x298ABC36; - - imm32 r0, 0x125489bd; - imm32 r1, 0x91b5fec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910507; - imm32 r4, 0x34567859; - imm32 r5, 0xd2359105; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = ( A1 += R5.H * R3.H ) (M,S2RND); - P1 = A1.w; - R3 = ( A1 -= R2.H * R1.H ) (M,S2RND); - P2 = A1.w; - R5 = ( A1 = R7.H * R0.H ) (M,S2RND); - P3 = A1.w; - R7 = ( A1 += R4.H * R6.H ) (M,S2RND); - P4 = A1.w; - CHECKREG r0, 0x125489BD; - CHECKREG r1, 0x0877B876; - CHECKREG r2, 0xA9145679; - CHECKREG r3, 0x0E3747DE; - CHECKREG r4, 0x34567859; - CHECKREG r5, 0x0EDF61B0; - CHECKREG r6, 0x0D0C0999; - CHECKREG r7, 0x143505C0; - CHECKREG p1, 0x043BDC3B; - CHECKREG p2, 0x071BA3EF; - CHECKREG p3, 0x076FB0D8; - CHECKREG p4, 0x0A1A82E0; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_u.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_u.s deleted file mode 100644 index 26cfbd5..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_u.s +++ /dev/null @@ -1,243 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_u/c_dsp32mac_pair_a1_u.dsp -// Spec Reference: dsp32mac pair a1 U -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A1 , and stored to a reg half - imm32 r0, 0x93545abd; - imm32 r1, 0x89bcfec7; - imm32 r2, 0xa8945679; - imm32 r3, 0x00890007; - imm32 r4, 0xefb89569; - imm32 r5, 0x1235890b; - imm32 r6, 0x000c089d; - imm32 r7, 0x678e0089; - R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L (FU); - P1 = A1.w; - R1 = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L (FU); - P2 = A1.w; - R3 = ( A1 = R7.L * R4.L ), A0 += R7.H * R4.H (FU); - P3 = A1.w; - R5 = ( A1 += R6.L * R5.L ), A0 += R6.L * R5.H (FU); - P4 = A1.w; - CHECKREG r0, 0x93545ABD; - CHECKREG r1, 0x00025D4F; - CHECKREG r2, 0xA8945679; - CHECKREG r3, 0x08B4E563; - CHECKREG r4, 0xEFB89569; - CHECKREG r5, 0x0D514922; - CHECKREG r6, 0x000C089D; - CHECKREG r7, 0x5A4E0EEB; - CHECKREG p1, 0x5A4E0EEB; - CHECKREG p2, 0x00025D4F; - CHECKREG p3, 0x08B4E563; - CHECKREG p4, 0x0D514922; - - imm32 r0, 0x98464abd; - imm32 r1, 0xa1b5f4c7; - imm32 r2, 0xa1146649; - imm32 r3, 0x00010805; - imm32 r4, 0xefbc1599; - imm32 r5, 0x12350100; - imm32 r6, 0x200c001d; - imm32 r7, 0x628e0001; - R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (FU); - P1 = A1.w; - R1 = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (FU); - P2 = A1.w; - R3 = ( A1 = R4.L * R5.H ), A0 += R4.H * R5.H (FU); - P3 = A1.w; - R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (FU); - P4 = A1.w; - CHECKREG r0, 0x98464ABD; - CHECKREG r1, 0x0D7355F0; - CHECKREG r2, 0xA1146649; - CHECKREG r3, 0x0D682BDA; - CHECKREG r4, 0xEFBC1599; - CHECKREG r5, 0x9EEA5F8C; - CHECKREG r6, 0x200C001D; - CHECKREG r7, 0x628E0001; - CHECKREG p1, 0x9EEA5F8C; - CHECKREG p2, 0x00006649; - CHECKREG p3, 0x0D682BDA; - CHECKREG p4, 0x0D7355F0; - - imm32 r0, 0x713a459d; - imm32 r1, 0xabd6aec7; - imm32 r2, 0x7a145a79; - imm32 r3, 0x08a100a7; - imm32 r4, 0xef9a156a; - imm32 r5, 0x1225a10b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0a61; - R5 = ( A1 += R7.H * R3.L ), A0 = R7.L * R3.L (FU); - P1 = A1.w; - R7 = ( A1 = R2.H * R4.L ), A0 -= R2.H * R4.L (FU); - P2 = A1.w; - R1 = ( A1 -= R0.H * R5.L ), A0 += R0.H * R5.H (FU); - P3 = A1.w; - R5 = ( A1 += R6.H * R1.L ), A0 += R6.L * R1.H (FU); - P4 = A1.w; - CHECKREG r0, 0x713A459D; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x7A145A79; - CHECKREG r3, 0x08A100A7; - CHECKREG r4, 0xEF9A156A; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x0003401D; - CHECKREG r7, 0x0A363048; - CHECKREG p1, 0x0DB6E392; - CHECKREG p2, 0x0A363048; - CHECKREG p3, 0x00000000; - CHECKREG p4, 0x00000000; - - imm32 r0, 0x773489bd; - imm32 r1, 0x917cfec7; - imm32 r2, 0xa9177679; - imm32 r3, 0xd0910777; - imm32 r4, 0xedb91579; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d077999; - imm32 r7, 0x677e0709; - R1 = ( A1 += R5.H * R3.H ), A0 -= R5.L * R3.L (FU); - P1 = A1.w; - R3 = ( A1 = R2.H * R1.H ), A0 -= R2.H * R1.L (FU); - P2 = A1.w; - R5 = ( A1 = R7.H * R0.H ), A0 += R7.H * R0.H (FU); - P3 = A1.w; - R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (FU); - P4 = A1.w; - CHECKREG r0, 0x773489BD; - CHECKREG r1, 0xAB422005; - CHECKREG r2, 0xA9177679; - CHECKREG r3, 0x711DF4EE; - CHECKREG r4, 0xEDB91579; - CHECKREG r5, 0x30309798; - CHECKREG r6, 0x0D077999; - CHECKREG r7, 0x3C497CA7; - CHECKREG p1, 0xAB422005; - CHECKREG p2, 0x711DF4EE; - CHECKREG p3, 0x30309798; - CHECKREG p4, 0x3C497CA7; - - imm32 r0, 0x83547abd; - imm32 r1, 0x88bc8ec7; - imm32 r2, 0xa8895679; - imm32 r3, 0x00080007; - imm32 r4, 0xe6b86569; - imm32 r5, 0x1A35860b; - imm32 r6, 0x000c896d; - imm32 r7, 0x67Be0096; - R7 = ( A1 += R1.L * R0.L ) (FU); - P1 = A1.w; - R1 = ( A1 = R2.H * R3.L ) (FU); - P2 = A1.w; - R3 = ( A1 -= R7.L * R4.H ) (FU); - P3 = A1.w; - R5 = ( A1 += R6.H * R5.H ) (FU); - P4 = A1.w; - CHECKREG r0, 0x83547ABD; - CHECKREG r1, 0x00049BBF; - CHECKREG r2, 0xA8895679; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0xE6B86569; - CHECKREG r5, 0x00013A7C; - CHECKREG r6, 0x000C896D; - CHECKREG r7, 0x80BDBB92; - CHECKREG p1, 0x80BDBB92; - CHECKREG p2, 0x00049BBF; - CHECKREG p3, 0x00000000; - CHECKREG p4, 0x00013A7C; - - imm32 r0, 0x9aa64abd; - imm32 r1, 0xa1baf4c7; - imm32 r2, 0xb114a649; - imm32 r3, 0x0b010005; - imm32 r4, 0xefbcdb69; - imm32 r5, 0x123501bb; - imm32 r6, 0x000c0d1b; - imm32 r7, 0x678e0d01; - R5 = ( A1 += R5.L * R0.H ) (M), A0 = R5.L * R0.L (FU); - P1 = A1.w; - R1 = ( A1 = R1.L * R3.H ) (M), A0 = R1.H * R3.L (FU); - P2 = A1.w; - R3 = ( A1 -= R2.L * R6.H ) (M), A0 += R2.H * R6.H (FU); - P3 = A1.w; - R1 = ( A1 += R4.L * R7.H ) (M), A0 += R4.L * R7.H (FU); - P4 = A1.w; - CHECKREG r0, 0x9AA64ABD; - CHECKREG r1, 0xF0BBA999; - CHECKREG r2, 0xB114A649; - CHECKREG r3, 0xFF88B65B; - CHECKREG r4, 0xEFBCDB69; - CHECKREG r5, 0x010CD7BE; - CHECKREG r6, 0x000C0D1B; - CHECKREG r7, 0x678E0D01; - CHECKREG p1, 0x010CD7BE; - CHECKREG p2, 0xFF8481C7; - CHECKREG p3, 0xFF88B65B; - CHECKREG p4, 0xF0BBA999; - - imm32 r0, 0xd136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0xdd010007; - imm32 r4, 0xeddc1569; - imm32 r5, 0x122d010b; - imm32 r6, 0x00e3d01d; - imm32 r7, 0x678e0d61; - R5 = A1 , A0 = R1.L * R0.L (FU); - P1 = A1.w; - R7 = A1 , A0 = R2.H * R3.L (FU); - P2 = A1.w; - R1 = A1 , A0 += R4.H * R5.H (FU); - P3 = A1.w; - R5 = A1 , A0 += R6.L * R7.H (FU); - P4 = A1.w; - CHECKREG r0, 0xD136459D; - CHECKREG r1, 0xFFFFFFFF; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0xDD010007; - CHECKREG r4, 0xEDDC1569; - CHECKREG r5, 0xFFFFFFFF; - CHECKREG r6, 0x00E3D01D; - CHECKREG r7, 0xFFFFFFFF; - CHECKREG p1, 0xF0BBA999; - CHECKREG p2, 0xF0BBA999; - CHECKREG p3, 0xF0BBA999; - CHECKREG p4, 0xF0BBA999; - - imm32 r0, 0x125489bd; - imm32 r1, 0x91b5fec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910507; - imm32 r4, 0x34567859; - imm32 r5, 0xd2359105; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = ( A1 += R5.H * R3.H ) (M,FU); - P1 = A1.w; - R3 = ( A1 -= R2.H * R1.H ) (M,FU); - P2 = A1.w; - R5 = ( A1 = R7.H * R0.H ) (M,FU); - P3 = A1.w; - R7 = ( A1 += R4.H * R6.H ) (M,FU); - P4 = A1.w; - CHECKREG r0, 0x125489BD; - CHECKREG r1, 0xCB6CC99E; - CHECKREG r2, 0xA9145679; - CHECKREG r3, 0x107E992E; - CHECKREG r4, 0x34567859; - CHECKREG r5, 0x076FB0D8; - CHECKREG r6, 0x0D0C0999; - CHECKREG r7, 0x0A1A82E0; - CHECKREG p1, 0xCB6CC99E; - CHECKREG p2, 0x107E992E; - CHECKREG p3, 0x076FB0D8; - CHECKREG p4, 0x0A1A82E0; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0.s deleted file mode 100644 index d7bd4b4..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0.s +++ /dev/null @@ -1,152 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0/c_dsp32mac_pair_a1a0.dsp -// Spec Reference: dsp32mac pair a1a0 -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ); - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ); - FP = A1.w; - CHECKREG r0, 0xFFFB3578; - CHECKREG r1, 0x0004BA9E; - CHECKREG r2, 0x00177258; - CHECKREG r3, 0x17A3558C; - CHECKREG r4, 0x0455E4F4; - CHECKREG r5, 0xFB35EDF0; - CHECKREG r6, 0xFF221DD6; - CHECKREG r7, 0xFF221DD6; - CHECKREG p1, 0xFF221DD6; - CHECKREG p2, 0xFF221DD6; - CHECKREG p3, 0x0004BA9E; - CHECKREG p4, 0xFFFB3578; - CHECKREG p5, 0x17A3558C; - CHECKREG sp, 0x00177258; - CHECKREG fp, 0xFB35EDF0; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 -= R2.H * R3.L ); - P2 = A0.w; - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 -= R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ); - P5 = A1.w; - SP = A0.w; - R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ); - FP = A0.w; - CHECKREG r0, 0xF955783E; - CHECKREG r1, 0xFC03F6B2; - CHECKREG r2, 0xF93E0212; - CHECKREG r3, 0xFBEC8086; - CHECKREG r4, 0xF97279D6; - CHECKREG r5, 0x0449E564; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0x0449E564; - CHECKREG p2, 0xF9762F0E; - CHECKREG p3, 0x0000AC92; - CHECKREG p4, 0xF9762F0E; - CHECKREG p5, 0xFBEC8086; - CHECKREG sp, 0xF93E0212; - CHECKREG fp, 0xF955783E; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ); - P1 = A1.w; - P2 = A0.w; - R7 = ( A1 -= R2.H * R3.L ), R6 = ( A0 -= R2.H * R3.L ); - P3 = A1.w; - P4 = A0.w; - R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H ); - FP = A0.w; - CHECKREG r0, 0xDFA7BA7E; - CHECKREG r1, 0xF66CBF80; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0xEF9AE3A2; - CHECKREG r5, 0x004EF7CC; - CHECKREG r6, 0xCB19D6FE; - CHECKREG r7, 0xCE37E816; - CHECKREG p1, 0xCE3E172E; - CHECKREG p2, 0xCB200616; - CHECKREG p3, 0xCE37E816; - CHECKREG p5, 0xF66CBF80; - CHECKREG p4, 0xCB19D6FE; - CHECKREG sp, 0xDFA7BA7E; - CHECKREG fp, 0xEF9AE3A2; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ); - P1 = A1.w; - P2 = A0.w; - R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ); - P3 = A1.w; - P4 = A0.w; - R5 = ( A1 -= R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ); - P5 = A1.w; - SP = A0.w; - R7 = ( A1 -= R4.H * R6.H ), R6 = ( A0 -= R4.L * R6.H ); - FP = A0.w; - CHECKREG r0, 0xFFF9EE9A; - CHECKREG r1, 0x114737D6; - CHECKREG r2, 0xDA154570; - CHECKREG r3, 0xF4447118; - CHECKREG r4, 0xDA0F974C; - CHECKREG r5, 0xF44A1F3C; - CHECKREG r6, 0xE4BBB02C; - CHECKREG r7, 0xF82827D4; - CHECKREG p1, 0x114737D6; - CHECKREG p2, 0xFFF9EE9A; - CHECKREG p3, 0xF4447118; - CHECKREG p4, 0xDA154570; - CHECKREG p5, 0xF44A1F3C; - CHECKREG sp, 0xDA0F974C; - CHECKREG fp, 0xE4BBB02C; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_i.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_i.s deleted file mode 100644 index 24d66fb..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_i.s +++ /dev/null @@ -1,292 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_i/c_dsp32mac_pair_a1a0_i.dsp -// Spec Reference: dsp32mac pair a1a0 I -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (IS); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (IS); - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (IS); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (IS); - FP = A1.w; - CHECKREG r0, 0xFFFD9ABC; - CHECKREG r1, 0x00025D4F; - CHECKREG r2, 0x0004A9F4; - CHECKREG r3, 0x05E8D563; - CHECKREG r4, 0x0114469B; - CHECKREG r5, 0xFECD7B7C; - CHECKREG r6, 0xFF910EEB; - CHECKREG r7, 0xFF910EEB; - CHECKREG p1, 0xFF910EEB; - CHECKREG p2, 0xFF910EEB; - CHECKREG p3, 0x00025D4F; - CHECKREG p4, 0xFFFD9ABC; - CHECKREG p5, 0x05E8D563; - CHECKREG sp, 0x0004A9F4; - CHECKREG fp, 0xFECD7B7C; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ) (IS); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 -= R2.H * R3.L ) (IS); - P2 = A0.w; - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 -= R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (IS); - P5 = A1.w; - SP = A0.w; - R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (IS); - FP = A0.w; - CHECKREG r0, 0xFCBBE07C; - CHECKREG r1, 0xFF409C82; - CHECKREG r2, 0xFCB02566; - CHECKREG r3, 0xFF34E16C; - CHECKREG r4, 0xFCB93CEB; - CHECKREG r5, 0x03577736; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0x03577736; - CHECKREG p2, 0xFCBB1787; - CHECKREG p3, 0x00005649; - CHECKREG p4, 0xFCBB1787; - CHECKREG p5, 0xFF34E16C; - CHECKREG sp, 0xFCB02566; - CHECKREG fp, 0xFCBBE07C; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (IS); - P1 = A1.w; - P2 = A0.w; - R7 = ( A1 = R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (IS); - P3 = A1.w; - P4 = A0.w; - R1 = ( A1 -= R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (IS); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H ) (IS); - FP = A0.w; - CHECKREG r0, 0x0273FCDC; - CHECKREG r1, 0xF76A2B8C; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x02744380; - CHECKREG r5, 0xF76A7230; - CHECKREG r6, 0x0003178C; - CHECKREG r7, 0x0003178C; - CHECKREG p1, 0xE85DACC0; - CHECKREG p2, 0xE590030B; - CHECKREG p3, 0x0003178C; - CHECKREG p5, 0xF76A2B8C; - CHECKREG p4, 0x0003178C; - CHECKREG sp, 0x0273FCDC; - CHECKREG fp, 0x02744380; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (IS); - P1 = A1.w; - P2 = A0.w; - R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 -= R2.H * R1.L ) (IS); - P3 = A1.w; - P4 = A0.w; - R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (IS); - P5 = A1.w; - SP = A0.w; - R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (IS); - FP = A0.w; - CHECKREG r0, 0xFFFCF74D; - CHECKREG r1, 0xFFE69235; - CHECKREG r2, 0xDAB58E29; - CHECKREG r3, 0x0008D3F8; - CHECKREG r4, 0xDAB3EEB1; - CHECKREG r5, 0xFFFE6088; - CHECKREG r6, 0xD9D21BFD; - CHECKREG r7, 0xFE17B7EC; - CHECKREG p1, 0xFFE69235; - CHECKREG p2, 0xFFFCF74D; - CHECKREG p3, 0x0008D3F8; - CHECKREG p4, 0xDAB58E29; - CHECKREG p5, 0xFFFE6088; - CHECKREG sp, 0xDAB3EEB1; - CHECKREG fp, 0xD9D21BFD; - - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (IS); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (IS); - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 -= R7.H * R4.H ) (IS); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (IS); - FP = A0.w; - CHECKREG r0, 0xFFFD9ABC; - CHECKREG r1, 0x00025D4F; - CHECKREG r2, 0xFFD771FC; - CHECKREG r3, 0x16A6FC20; - CHECKREG r4, 0x00E70EA3; - CHECKREG r5, 0x1E76A239; - CHECKREG r6, 0xFF910EEB; - CHECKREG r7, 0xFDA8C6D7; - CHECKREG p1, 0xFDA8C6D7; - CHECKREG p2, 0xFF910EEB; - CHECKREG p3, 0x00025D4F; - CHECKREG p4, 0xFFFD9ABC; - CHECKREG p5, 0x16A6FC20; - CHECKREG sp, 0xFFD771FC; - CHECKREG fp, 0x00E70EA3; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R5 = A1, R4 = ( A0 = R1.L * R0.L ) (IS); - P1 = A1.w; - P2 = A0.w; - R1 = A1, R0 = ( A0 = R2.H * R3.L ) (IS); - P3 = A1.w; - P4 = A0.w; - R3 = A1, R2 = ( A0 -= R4.H * R5.H ) (IS); - P5 = A1.w; - SP = A0.w; - R1 = A1, R0 = ( A0 += R6.L * R7.H ) (IS); - FP = A1.w; - CHECKREG r0, 0x006DB534; - CHECKREG r1, 0x1E76A239; - CHECKREG r2, 0x0061FA1E; - CHECKREG r3, 0x1E76A239; - CHECKREG r4, 0xFCB93CEB; - CHECKREG r5, 0x1E76A239; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0x1E76A239; - CHECKREG p2, 0xFCB93CEB; - CHECKREG p3, 0x1E76A239; - CHECKREG p4, 0xFFFE2564; - CHECKREG p5, 0x1E76A239; - CHECKREG sp, 0x0061FA1E; - CHECKREG fp, 0x1E76A239; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (IS); - P1 = A1.w; - P2 = A0.w; - R7 = A1, R6 = ( A0 = R2.H * R3.L ) (IS); - P3 = A1.w; - P4 = A0.w; - R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 += R4.H * R5.H ) (IS); - P5 = A1.w; - SP = A0.w; - R5 = A1, R4 = ( A0 -= R6.L * R7.H ) (IS); - FP = A1.w; - CHECKREG r0, 0xFF3AD93C; - CHECKREG r1, 0xED91D5F0; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0xFE887FD8; - CHECKREG r5, 0xED91D5F0; - CHECKREG r6, 0x0003178C; - CHECKREG r7, 0x0793B277; - CHECKREG p1, 0x0793B277; - CHECKREG p2, 0xE590030B; - CHECKREG p3, 0x0793B277; - CHECKREG p4, 0x0003178C; - CHECKREG p5, 0xED91D5F0; - CHECKREG sp, 0xFF3AD93C; - CHECKREG fp, 0xED91D5F0; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = A1, R0 = ( A0 = R5.L * R3.L ) (IS); - P1 = A1.w; - P2 = A0.w; - R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (IS); - P3 = A1.w; - P4 = A0.w; - R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (IS); - P5 = A0.w; - SP = A1.w; - R7 = A1, R6 = ( A0 += R4.L * R6.H ) (IS); - FP = A0.w; - CHECKREG r0, 0xFFFCF74D; - CHECKREG r1, 0xED91D5F0; - CHECKREG r2, 0x0E4826C0; - CHECKREG r3, 0xAF564854; - CHECKREG r4, 0x0E468748; - CHECKREG r5, 0x67DC6088; - CHECKREG r6, 0x081F86A8; - CHECKREG r7, 0x67DC6088; - CHECKREG p1, 0xED91D5F0; - CHECKREG p2, 0xFFFCF74D; - CHECKREG p3, 0xAF564854; - CHECKREG p4, 0x0E4826C0; - CHECKREG p5, 0x0E468748; - CHECKREG sp, 0x67DC6088; - CHECKREG fp, 0x081F86A8; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_is.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_is.s deleted file mode 100644 index b719318..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_is.s +++ /dev/null @@ -1,292 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_is/c_dsp32mac_pair_a1a0_is.dsp -// Spec Reference: dsp32mac pair a1a0 IS -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - R7 = ( A1 += R4.L * R0.L ), R6 = ( A0 = R4.L * R0.L ) (ISS2); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R3.L * R1.L ), R0 = ( A0 = R3.H * R1.L ) (ISS2); - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 = R7.L * R2.L ), R2 = ( A0 += R7.H * R2.H ) (ISS2); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R5.L * R6.L ), R4 = ( A0 += R5.L * R6.H ) (ISS2); - FP = A1.w; - CHECKREG r0, 0xFFFEB854; - CHECKREG r1, 0xFFFFEEE2; - CHECKREG r2, 0xCECAD1AC; - CHECKREG r3, 0xB509D374; - CHECKREG r4, 0x8A4CA32E; - CHECKREG r5, 0x1EC2C250; - CHECKREG r6, 0x47E3910A; - CHECKREG r7, 0x47E3910A; - CHECKREG p1, 0x23F1C885; - CHECKREG p2, 0x23F1C885; - CHECKREG p3, 0xFFFFF771; - CHECKREG p4, 0xFFFF5C2A; - CHECKREG p5, 0xDA84E9BA; - CHECKREG sp, 0xE76568D6; - CHECKREG fp, 0x0F616128; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R5 = ( A1 += R4.L * R0.H ), R4 = ( A0 = R4.L * R0.L ) (ISS2); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (ISS2); - P2 = A0.w; - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 = R7.L * R5.H ), R2 = ( A0 += R7.H * R5.H ) (ISS2); - P5 = A1.w; - SP = A0.w; - R1 = ( A1 += R6.L * R1.H ), R0 = ( A0 += R6.L * R1.H ) (ISS2); - FP = A0.w; - CHECKREG r0, 0x0ADC2224; - CHECKREG r1, 0x00001AE2; - CHECKREG r2, 0x0ADC2224; - CHECKREG r3, 0x00001AE2; - CHECKREG r4, 0x0C80510A; - CHECKREG r5, 0x0D712F1C; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0x06B8978E; - CHECKREG p2, 0xFFFE2564; - CHECKREG p3, 0x00005649; - CHECKREG p4, 0xFFFE2564; - CHECKREG p5, 0x00000D71; - CHECKREG sp, 0x056E1112; - CHECKREG fp, 0x056E1112; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (ISS2); - P1 = A1.w; - P2 = A0.w; - R7 = ( A1 = R6.H * R3.L ), R6 = ( A0 = R6.H * R3.L ) (ISS2); - P3 = A1.w; - P4 = A0.w; - R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (ISS2); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R2.H * R7.L ), R4 = ( A0 += R2.L * R7.H ) (ISS2); - FP = A0.w; - CHECKREG r0, 0x12E88AAA; - CHECKREG r1, 0xE779EB80; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x12E88AAA; - CHECKREG r5, 0xE79F0610; - CHECKREG r6, 0x0000002A; - CHECKREG r7, 0x0000002A; - CHECKREG p1, 0xE91D1DAF; - CHECKREG p2, 0xE590030B; - CHECKREG p3, 0x00000015; - CHECKREG p5, 0xF3BCF5C0; - CHECKREG p4, 0x00000015; - CHECKREG sp, 0x09744555; - CHECKREG fp, 0x09744555; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (ISS2); - P1 = A1.w; - P2 = A0.w; - R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (ISS2); - P3 = A1.w; - P4 = A0.w; - R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (ISS2); - P5 = A1.w; - SP = A0.w; - R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (ISS2); - FP = A0.w; - CHECKREG r0, 0xFFF9EE9A; - CHECKREG r1, 0xF897461A; - CHECKREG r2, 0xD0654810; - CHECKREG r3, 0x05083598; - CHECKREG r4, 0xD05F99EC; - CHECKREG r5, 0xFFFA51DC; - CHECKREG r6, 0xC5F8000C; - CHECKREG r7, 0xFB1F80C4; - CHECKREG p1, 0xFC4BA30D; - CHECKREG p2, 0xFFFCF74D; - CHECKREG p3, 0x02841ACC; - CHECKREG p4, 0xE832A408; - CHECKREG p5, 0xFFFD28EE; - CHECKREG sp, 0xE82FCCF6; - CHECKREG fp, 0xE2FC0006; - - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (ISS2); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (ISS2); - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 = R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (ISS2); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (ISS2); - FP = A0.w; - CHECKREG r0, 0xFFFB3578; - CHECKREG r1, 0x0004BA9E; - CHECKREG r2, 0x00B650E8; - CHECKREG r3, 0xB2D59E54; - CHECKREG r4, 0x04F4C384; - CHECKREG r5, 0xD21436B8; - CHECKREG r6, 0xFF221DD6; - CHECKREG r7, 0xFA419E9A; - CHECKREG p1, 0xFD20CF4D; - CHECKREG p2, 0xFF910EEB; - CHECKREG p3, 0x00025D4F; - CHECKREG p4, 0xFFFD9ABC; - CHECKREG p5, 0xD96ACF2A; - CHECKREG sp, 0x005B2874; - CHECKREG fp, 0x027A61C2; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R5 = A1, R4 = ( A0 = R1.L * R0.L ) (ISS2); - P1 = A1.w; - P2 = A0.w; - R1 = A1, R0 = ( A0 = R4.H * R3.L ) (ISS2); - P3 = A1.w; - P4 = A0.w; - R3 = A1, R2 = ( A0 += R2.H * R5.H ) (ISS2); - P5 = A1.w; - SP = A0.w; - R1 = A1, R0 = ( A0 += R6.L * R7.H ) (ISS2); - FP = A1.w; - CHECKREG r0, 0x22252FC0; - CHECKREG r1, 0xD21436B8; - CHECKREG r2, 0x220DB994; - CHECKREG r3, 0xD21436B8; - CHECKREG r4, 0xF97279D6; - CHECKREG r5, 0xD21436B8; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xE90A1B5C; - CHECKREG p2, 0xFCB93CEB; - CHECKREG p3, 0xE90A1B5C; - CHECKREG p4, 0xFFFFDF3A; - CHECKREG p5, 0xE90A1B5C; - CHECKREG sp, 0x1106DCCA; - CHECKREG fp, 0xE90A1B5C; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (ISS2); - P1 = A1.w; - P2 = A0.w; - R7 = A1, R6 = ( A0 = R2.H * R3.L ) (ISS2); - P3 = A1.w; - P4 = A0.w; - R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 += R4.H * R5.H ) (ISS2); - P5 = A1.w; - SP = A0.w; - R5 = A1, R4 = ( A0 += R6.L * R7.H ) (ISS2); - FP = A1.w; - CHECKREG r0, 0x25E6F698; - CHECKREG r1, 0xDBFA4500; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x042A6938; - CHECKREG r5, 0xDBFA4500; - CHECKREG r6, 0x00062F18; - CHECKREG r7, 0xA44E5734; - CHECKREG p1, 0xD2272B9A; - CHECKREG p2, 0xE590030B; - CHECKREG p3, 0xD2272B9A; - CHECKREG p4, 0x0003178C; - CHECKREG p5, 0xEDFD2280; - CHECKREG sp, 0x12F37B4C; - CHECKREG fp, 0xEDFD2280; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = A1, R0 = ( A0 = R5.L * R3.L ) (ISS2); - P1 = A1.w; - P2 = A0.w; - R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (ISS2); - P3 = A1.w; - P4 = A0.w; - R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (ISS2); - P5 = A0.w; - SP = A1.w; - R7 = A1, R6 = ( A0 += R4.L * R6.H ) (ISS2); - FP = A0.w; - CHECKREG r0, 0xFFF9EE9A; - CHECKREG r1, 0xDBFA4500; - CHECKREG r2, 0xD124C800; - CHECKREG r3, 0x80000000; - CHECKREG r4, 0xD11F19DC; - CHECKREG r5, 0x7FFFFFFF; - CHECKREG r6, 0xD3C1DE7C; - CHECKREG r7, 0x7FFFFFFF; - CHECKREG p1, 0xEDFD2280; - CHECKREG p2, 0xFFFCF74D; - CHECKREG p3, 0xB54F3988; - CHECKREG p4, 0xE8926400; - CHECKREG p5, 0xE88F8CEE; - CHECKREG sp, 0x67DB28EE; - CHECKREG fp, 0xE9E0EF3E; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_m.s deleted file mode 100644 index 2725fa9..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_m.s +++ /dev/null @@ -1,152 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_m/c_dsp32mac_pair_a1a0_m.dsp -// Spec Reference: dsp32mac pair a1a0 M MNOP -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half - - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - R7 = ( A1 += R0.L * R1.L ) (M), R6 = ( A0 = R0.L * R1.L ) (IS); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R3.L * R2.L ) (M), R0 = ( A0 = R3.H * R2.L ) (IS); - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 -= R7.L * R6.L ) (M), R2 = ( A0 += R7.H * R6.H ) (IS); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R5.L * R4.L ) (M), R4 = ( A0 += R5.L * R4.H ) (IS); - FP = A0.w; - CHECKREG r0, 0x002D4356; - CHECKREG r1, 0x00025D4F; - CHECKREG r2, 0x00061B84; - CHECKREG r3, 0xFF23D196; - CHECKREG r4, 0x07C7B86C; - CHECKREG r5, 0xCED42319; - CHECKREG r6, 0xFF910EEB; - CHECKREG r7, 0x5A4E0EEB; - CHECKREG p1, 0x5A4E0EEB; - CHECKREG p2, 0xFF910EEB; - CHECKREG p3, 0x00025D4F; - CHECKREG p4, 0x002D4356; - CHECKREG p5, 0xFF23D196; - CHECKREG sp, 0x00061B84; - CHECKREG fp, 0x07C7B86C; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R5 = A1, R4 = ( A0 = R3.L * R1.L ) (IS); - P1 = A1.w; - P2 = A0.w; - R1 = A1, R0 = ( A0 -= R0.H * R5.L ) (IS); - P3 = A1.w; - P4 = A0.w; - R3 = A1, R2 = ( A0 += R2.H * R7.H ) (IS); - P5 = A1.w; - SP = A0.w; - R1 = A1, R0 = ( A0 -= R4.L * R6.H ) (IS); - FP = A1.w; - CHECKREG r0, 0xE7CEC8D1; - CHECKREG r1, 0xCED42319; - CHECKREG r2, 0xE7CC2775; - CHECKREG r3, 0xCED42319; - CHECKREG r4, 0xFFFFC7E3; - CHECKREG r5, 0xCED42319; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xCED42319; - CHECKREG p2, 0xFFFFC7E3; - CHECKREG p3, 0xCED42319; - CHECKREG p4, 0x0E31C25D; - CHECKREG p5, 0xCED42319; - CHECKREG sp, 0xE7CC2775; - CHECKREG fp, 0xCED42319; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - R5 = ( A1 += R4.H * R3.L ) (M), R4 = ( A0 = R4.L * R3.L ) (IS); - P1 = A1.w; - P2 = A0.w; - R7 = A1, R6 = ( A0 = R5.H * R0.L ) (IS); - P3 = A1.w; - P4 = A0.w; - R1 = ( A1 = R2.H * R6.L ) (M), R0 = ( A0 += R2.H * R6.H ) (IS); - P5 = A1.w; - SP = A0.w; - R5 = A1, R4 = ( A0 += R7.L * R1.H ) (IS); - FP = A1.w; - CHECKREG r0, 0xECB84AE7; - CHECKREG r1, 0x5091B70C; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0xD3A83F94; - CHECKREG r5, 0x5091B70C; - CHECKREG r6, 0xF2A0B667; - CHECKREG r7, 0xCED3B05D; - CHECKREG p1, 0xCED3B05D; - CHECKREG p2, 0x000095DF; - CHECKREG p3, 0xCED3B05D; - CHECKREG p4, 0xF2A0B667; - CHECKREG p5, 0x5091B70C; - CHECKREG sp, 0xECB84AE7; - CHECKREG fp, 0x5091B70C; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = A1, R0 = ( A0 = R5.L * R2.L ) (IS); - P1 = A1.w; - P2 = A0.w; - R3 = ( A1 = R3.H * R1.H ) (M), R2 = ( A0 -= R3.H * R1.L ) (IS); - P3 = A1.w; - P4 = A0.w; - R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (IS); - P5 = A0.w; - SP = A1.w; - R7 = A1, R6 = ( A0 += R4.L * R6.H ) (IS); - FP = A0.w; - CHECKREG r0, 0xDA854033; - CHECKREG r1, 0x5091B70C; - CHECKREG r2, 0xCD00D267; - CHECKREG r3, 0xF1127221; - CHECKREG r4, 0xBDCBD4BD; - CHECKREG r5, 0x58A90256; - CHECKREG r6, 0xBB976699; - CHECKREG r7, 0x58A90256; - CHECKREG p1, 0x5091B70C; - CHECKREG p2, 0xDA854033; - CHECKREG p3, 0xF1127221; - CHECKREG p4, 0xCD00D267; - CHECKREG p5, 0xBDCBD4BD; - CHECKREG sp, 0x58A90256; - CHECKREG fp, 0xBB976699; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_s.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_s.s deleted file mode 100644 index ce66ae0..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_s.s +++ /dev/null @@ -1,306 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_s/c_dsp32mac_pair_a1a0_s.dsp -// Spec Reference: dsp32mac pair a1a0 S -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (S2RND); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (S2RND); - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (S2RND); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (S2RND); - FP = A1.w; - CHECKREG r0, 0xFFF66AF0; - CHECKREG r1, 0x0009753C; - CHECKREG r2, 0x00675E70; - CHECKREG r3, 0x5E8D5630; - CHECKREG r4, 0x116128E0; - CHECKREG r5, 0xECD7B7C0; - CHECKREG r6, 0xFE443BAC; - CHECKREG r7, 0xFE443BAC; - CHECKREG p1, 0xFF221DD6; - CHECKREG p2, 0xFF221DD6; - CHECKREG p3, 0x0004BA9E; - CHECKREG p4, 0xFFFB3578; - CHECKREG p5, 0x2F46AB18; - CHECKREG sp, 0x0033AF38; - CHECKREG fp, 0xF66BDBE0; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - A0 = R2; - A1 = R3; - R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ) (S2RND); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (S2RND); - P2 = A0.w; - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 = R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (S2RND); - P5 = A1.w; - SP = A0.w; - R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (S2RND); - FP = A0.w; - CHECKREG r0, 0xFC6F3BF8; - CHECKREG r1, 0xFCAF6688; - CHECKREG r2, 0xFC404FA0; - CHECKREG r3, 0xFC807A30; - CHECKREG r4, 0xF2E4F3AC; - CHECKREG r5, 0x1229EEF2; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0x0914F779; - CHECKREG p2, 0xFFFC4AC8; - CHECKREG p3, 0x0000AC92; - CHECKREG p4, 0xFFFC4AC8; - CHECKREG p5, 0xFE403D18; - CHECKREG sp, 0xFE2027D0; - CHECKREG fp, 0xFE379DFC; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - A0 = R0; - A1 = R1; - R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (S2RND); - P1 = A1.w; - P2 = A0.w; - R7 = ( A1 = R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (S2RND); - P3 = A1.w; - P4 = A0.w; - R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (S2RND); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H ) (S2RND); - FP = A0.w; - CHECKREG r0, 0x7FFFFFFF; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x7FFFFFFF; - CHECKREG r5, 0x0011A900; - CHECKREG r6, 0x000C5E30; - CHECKREG r7, 0x000C5E30; - CHECKREG p1, 0x7E10BF43; - CHECKREG p2, 0xCB200616; - CHECKREG p3, 0x00062F18; - CHECKREG p5, 0x00000000; - CHECKREG p4, 0x00062F18; - CHECKREG sp, 0x69C62F18; - CHECKREG fp, 0x69CF0398; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - A0 = R0; - A1 = R1; - R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (S2RND); - P1 = A1.w; - P2 = A0.w; - R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (S2RND); - P3 = A1.w; - P4 = A0.w; - R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (S2RND); - P5 = A1.w; - SP = A0.w; - R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (S2RND); - FP = A0.w; - CHECKREG r0, 0xFFF3DD34; - CHECKREG r1, 0x80000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x7FFFFFFF; - CHECKREG r4, 0xFFEAE6E8; - CHECKREG r5, 0xFFEAE6E8; - CHECKREG r6, 0xFACD5268; - CHECKREG r7, 0xFFE66AC8; - CHECKREG p1, 0xA2B53ED1; - CHECKREG p2, 0xFFF9EE9A; - CHECKREG p3, 0x56EC0000; - CHECKREG p4, 0x00000000; - CHECKREG p5, 0xFFF57374; - CHECKREG sp, 0xFFF57374; - CHECKREG fp, 0xFD66A934; - - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - A0 = R0; - A1 = R1; - R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (S2RND); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 -= R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (S2RND); - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (S2RND); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (S2RND); - FP = A0.w; - CHECKREG r0, 0xFFF66AF0; - CHECKREG r1, 0x80000000; - CHECKREG r2, 0x20866AF0; - CHECKREG r3, 0x80000000; - CHECKREG r4, 0x31803560; - CHECKREG r5, 0x80000000; - CHECKREG r6, 0xFE443BAC; - CHECKREG r7, 0x80000000; - CHECKREG p1, 0x864E0DB2; - CHECKREG p2, 0xFF221DD6; - CHECKREG p3, 0x864BB063; - CHECKREG p4, 0xFFFB3578; - CHECKREG p5, 0x864BB063; - CHECKREG sp, 0x10433578; - CHECKREG fp, 0x18C01AB0; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - A0 = R0; - A1 = R1; - R5 = A1, R4 = ( A0 = R3.L * R0.L ) (S2RND); - P1 = A1.w; - P2 = A0.w; - R1 = A1, R0 = ( A0 = R2.H * R1.L ) (S2RND); - P3 = A1.w; - P4 = A0.w; - R3 = A1, R2 = ( A0 += R7.H * R5.H ) (S2RND); - P5 = A1.w; - SP = A0.w; - R1 = A1, R0 = ( A0 += R4.L * R6.H ) (S2RND); - FP = A1.w; - CHECKREG r0, 0x80000000; - CHECKREG r1, 0x80000000; - CHECKREG r2, 0x80000000; - CHECKREG r3, 0x80000000; - CHECKREG r4, 0x0005D6C4; - CHECKREG r5, 0x80000000; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0xA1BCF4C7; - CHECKREG p2, 0x0002EB62; - CHECKREG p3, 0xA1BCF4C7; - CHECKREG p4, 0x08528D18; - CHECKREG p5, 0xA1BCF4C7; - CHECKREG sp, 0xA0C48D18; - CHECKREG fp, 0xA1BCF4C7; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - A0 = R0; - A1 = R1; - R5 = ( A1 += R1.H * R6.L ) (M), R4 = ( A0 = R1.L * R6.L ) (S2RND); - P1 = A1.w; - P2 = A0.w; - R7 = A1, R6 = ( A0 -= R4.H * R3.L ) (S2RND); - P3 = A1.w; - P4 = A0.w; - R1 = ( A1 = R2.H * R5.L ) (M), R0 = ( A0 += R2.H * R5.H ) (S2RND); - P5 = A1.w; - SP = A0.w; - R5 = A1, R4 = ( A0 += R0.L * R7.H ) (S2RND); - FP = A1.w; - CHECKREG r0, 0x80000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x80000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x9EA59954; - CHECKREG r7, 0x80000000; - CHECKREG p1, 0x96C29605; - CHECKREG p2, 0xCF4D7916; - CHECKREG p3, 0x96C29605; - CHECKREG p4, 0xCF52CCAA; - CHECKREG p5, 0x00000000; - CHECKREG sp, 0x5E3ECCAA; - CHECKREG fp, 0x00000000; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - A0 = R0; - A1 = R1; - R1 = A1, R0 = ( A0 -= R5.L * R3.L ) (S2RND); - P1 = A1.w; - P2 = A0.w; - R3 = ( A1 -= R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (S2RND); - P3 = A1.w; - P4 = A0.w; - R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 -= R7.H * R0.H ) (S2RND); - P5 = A0.w; - SP = A1.w; - R7 = A1, R6 = ( A0 += R4.L * R6.H ) (S2RND); - FP = A0.w; - CHECKREG r0, 0x24753646; - CHECKREG r1, 0x80000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x80000000; - CHECKREG r4, 0xC4D53E28; - CHECKREG r5, 0x1D9560EC; - CHECKREG r6, 0xD18105A8; - CHECKREG r7, 0x1D9560EC; - CHECKREG p1, 0x91BCFEC7; - CHECKREG p2, 0x123A9B23; - CHECKREG p3, 0xBD32FEC7; - CHECKREG p4, 0x00000000; - CHECKREG p5, 0xE26A9F14; - CHECKREG sp, 0x0ECAB076; - CHECKREG fp, 0xE8C082D4; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_u.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_u.s deleted file mode 100644 index 1b2707e..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_u.s +++ /dev/null @@ -1,292 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_u/c_dsp32mac_pair_a1a0_u.dsp -// Spec Reference: dsp32mac pair a1a0 U -# mach: bfin - -.include "testutils.inc" - start - - A1 = A0 = 0; - -// The result accumulated in A , and stored to a reg half - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (FU); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (FU); - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 -= R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (FU); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (FU); - FP = A1.w; - CHECKREG r0, 0x00049ABC; - CHECKREG r1, 0x00025D4F; - CHECKREG r2, 0x549454CC; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x55A3F173; - CHECKREG r5, 0x07CFA619; - CHECKREG r6, 0x5A4E0EEB; - CHECKREG r7, 0x5A4E0EEB; - CHECKREG p1, 0x5A4E0EEB; - CHECKREG p2, 0x5A4E0EEB; - CHECKREG p3, 0x00025D4F; - CHECKREG p4, 0x00049ABC; - CHECKREG p5, 0x00000000; - CHECKREG sp, 0x549454CC; - CHECKREG fp, 0x07CFA619; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 -= R1.L * R0.L ) (FU); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 -= R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (FU); - P2 = A0.w; - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 = R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (FU); - P5 = A1.w; - SP = A0.w; - R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (FU); - FP = A0.w; - CHECKREG r0, 0x089013D8; - CHECKREG r1, 0x6C5ACAC6; - CHECKREG r2, 0x088458C2; - CHECKREG r3, 0x6C4F0FB0; - CHECKREG r4, 0x0E2DB488; - CHECKREG r5, 0x9996A1D3; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0x9996A1D3; - CHECKREG p2, 0x00032564; - CHECKREG p3, 0x99964B8A; - CHECKREG p4, 0x00032564; - CHECKREG p5, 0x6C4F0FB0; - CHECKREG sp, 0x088458C2; - CHECKREG fp, 0x089013D8; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (FU); - P1 = A1.w; - P2 = A0.w; - R7 = ( A1 -= R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (FU); - P3 = A1.w; - P4 = A0.w; - R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (FU); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 -= R6.L * R7.H ) (FU); - FP = A0.w; - CHECKREG r0, 0x1A2AB610; - CHECKREG r1, 0x24F02BB4; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x0BE761C4; - CHECKREG r5, 0x24F2761C; - CHECKREG r6, 0x0003178C; - CHECKREG r7, 0x9B11C378; - CHECKREG p1, 0x9B14DB04; - CHECKREG p2, 0x2B2D030B; - CHECKREG p3, 0x9B11C378; - CHECKREG p5, 0x24F02BB4; - CHECKREG p4, 0x0003178C; - CHECKREG sp, 0x1A2AB610; - CHECKREG fp, 0x0BE761C4; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (FU); - P1 = A1.w; - P2 = A0.w; - R3 = ( A1 -= R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (FU); - P3 = A1.w; - P4 = A0.w; - R5 = ( A1 -= R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (FU); - P5 = A1.w; - SP = A0.w; - R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (FU); - FP = A0.w; - CHECKREG r0, 0x0003F74D; - CHECKREG r1, 0xD0349621; - CHECKREG r2, 0x63278394; - CHECKREG r3, 0x46B1FE11; - CHECKREG r4, 0x6328BB2E; - CHECKREG r5, 0x46B0C677; - CHECKREG r6, 0x6CB2D756; - CHECKREG r7, 0x4BBE7457; - CHECKREG p1, 0xD0349621; - CHECKREG p2, 0x0003F74D; - CHECKREG p3, 0x46B1FE11; - CHECKREG p4, 0x63278394; - CHECKREG p5, 0x46B0C677; - CHECKREG sp, 0x6328BB2E; - CHECKREG fp, 0x6CB2D756; - - imm32 r0, 0x63545abd; - imm32 r1, 0x86bcfec7; - imm32 r2, 0xa8645679; - imm32 r3, 0x00860007; - imm32 r4, 0xefb86569; - imm32 r5, 0x1235860b; - imm32 r6, 0x000c086d; - imm32 r7, 0x678e0086; - R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (FU); - P1 = A1.w; - P2 = A0.w; - R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (FU); - P3 = A1.w; - P4 = A0.w; - R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (FU); - P5 = A1.w; - SP = A0.w; - R5 = ( A1 -= R6.L * R5.L ) (M), R4 = ( A0 -= R6.L * R5.H ) (FU); - FP = A0.w; - CHECKREG r0, 0x00049ABC; - CHECKREG r1, 0x00025D4F; - CHECKREG r2, 0x46897C84; - CHECKREG r3, 0x316C7D3D; - CHECKREG r4, 0x4579DFDD; - CHECKREG r5, 0x299CD724; - CHECKREG r6, 0x5A4E0EEB; - CHECKREG r7, 0x4B4F8342; - CHECKREG p1, 0x4B4F8342; - CHECKREG p2, 0x5A4E0EEB; - CHECKREG p3, 0x00025D4F; - CHECKREG p4, 0x00049ABC; - CHECKREG p5, 0x316C7D3D; - CHECKREG sp, 0x46897C84; - CHECKREG fp, 0x4579DFDD; - - imm32 r0, 0x98764abd; - imm32 r1, 0xa1bcf4c7; - imm32 r2, 0xa1145649; - imm32 r3, 0x00010005; - imm32 r4, 0xefbc1569; - imm32 r5, 0x1235010b; - imm32 r6, 0x000c001d; - imm32 r7, 0x678e0001; - R5 = A1, R4 = ( A0 = R1.L * R0.L ) (FU); - P1 = A1.w; - P2 = A0.w; - R1 = A1, R0 = ( A0 -= R2.H * R3.L ) (FU); - P3 = A1.w; - P4 = A0.w; - R3 = A1, R2 = ( A0 += R4.H * R5.H ) (FU); - P5 = A1.w; - SP = A0.w; - R1 = A1, R0 = ( A0 -= R6.L * R7.H ) (FU); - FP = A1.w; - CHECKREG r0, 0x5304CE59; - CHECKREG r1, 0x299CD724; - CHECKREG r2, 0x5310896F; - CHECKREG r3, 0x299CD724; - CHECKREG r4, 0x47763CEB; - CHECKREG r5, 0x299CD724; - CHECKREG r6, 0x000C001D; - CHECKREG r7, 0x678E0001; - CHECKREG p1, 0x299CD724; - CHECKREG p2, 0x47763CEB; - CHECKREG p3, 0x299CD724; - CHECKREG p4, 0x47731787; - CHECKREG p5, 0x299CD724; - CHECKREG sp, 0x5310896F; - CHECKREG fp, 0x299CD724; - - imm32 r0, 0x7136459d; - imm32 r1, 0xabd69ec7; - imm32 r2, 0x71145679; - imm32 r3, 0x08010007; - imm32 r4, 0xef9c1569; - imm32 r5, 0x1225010b; - imm32 r6, 0x0003401d; - imm32 r7, 0x678e0561; - R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (FU); - P1 = A1.w; - P2 = A0.w; - R7 = A1, R6 = ( A0 = R2.H * R3.L ) (FU); - P3 = A1.w; - P4 = A0.w; - R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 -= R4.H * R5.H ) (FU); - P5 = A1.w; - SP = A0.w; - R5 = A1, R4 = ( A0 += R6.L * R7.H ) (FU); - FP = A1.w; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x2706223A; - CHECKREG r2, 0x71145679; - CHECKREG r3, 0x08010007; - CHECKREG r4, 0x01B8DC2C; - CHECKREG r5, 0x2706223A; - CHECKREG r6, 0x0003178C; - CHECKREG r7, 0x12B9E762; - CHECKREG p1, 0x12B9E762; - CHECKREG p2, 0x2B2D030B; - CHECKREG p3, 0x12B9E762; - CHECKREG p4, 0x0003178C; - CHECKREG p5, 0x2706223A; - CHECKREG sp, 0x00000000; - CHECKREG fp, 0x2706223A; - - imm32 r0, 0x123489bd; - imm32 r1, 0x91bcfec7; - imm32 r2, 0xa9145679; - imm32 r3, 0xd0910007; - imm32 r4, 0xedb91569; - imm32 r5, 0xd235910b; - imm32 r6, 0x0d0c0999; - imm32 r7, 0x67de0009; - R1 = A1, R0 = ( A0 -= R5.L * R3.L ) (FU); - P1 = A1.w; - P2 = A0.w; - R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (FU); - P3 = A1.w; - P4 = A0.w; - R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (FU); - P5 = A0.w; - SP = A1.w; - R7 = A1, R6 = ( A0 += R4.L * R6.H ) (FU); - FP = A0.w; - CHECKREG r0, 0x01B4E4DF; - CHECKREG r1, 0x2706223A; - CHECKREG r2, 0x169AF688; - CHECKREG r3, 0xF2C00278; - CHECKREG r4, 0x174BDCA0; - CHECKREG r5, 0x00B0E618; - CHECKREG r6, 0x228A5420; - CHECKREG r7, 0x00B0E618; - CHECKREG p1, 0x2706223A; - CHECKREG p2, 0x01B4E4DF; - CHECKREG p3, 0xF2C00278; - CHECKREG p4, 0x169AF688; - CHECKREG p5, 0x174BDCA0; - CHECKREG sp, 0x00B0E618; - CHECKREG fp, 0x228A5420; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_mix.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_mix.s deleted file mode 100644 index 714fedd..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mac_pair_mix.s +++ /dev/null @@ -1,69 +0,0 @@ -//Original:/testcases/core/c_dsp32mac_pair_mix/c_dsp32mac_pair_mix.dsp -// Spec Reference: dsp32mac pair mix -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00060007; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; - -A0 = 0; -ASTAT = R0; -// The result accumulated in A0 and A1, and stored to a reg pair -imm32 r0, 0x00120034; -imm32 r1, 0x00050006; - -R3 = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; -R5 = ( A1 = R1.L * R0.H ); -R7 = ( A1 = R1.L * R0.H ) (M), A0 = R1.H * R0.L; -CHECKREG r2, 0x00040005; -CHECKREG r3, 0x000000d8; -CHECKREG r4, 0x00080009; -CHECKREG r5, 0x000000d8; -CHECKREG r6, 0x000C000D; -CHECKREG r7, 0x0000006c; -A1 = R1.L * R0.H, R2 = ( A0 += R1.H * R0.L ); -A1 = R1.L * R0.H (M), R6 = ( A0 -= R1.H * R0.L ); -CHECKREG r2, 0x00000410; -CHECKREG r3, 0x000000d8; -CHECKREG r4, 0x00080009; -CHECKREG r5, 0x000000d8; -CHECKREG r6, 0x00000208; -CHECKREG r7, 0x0000006c; -R3 = ( A1 = R1.L * R0.H ), R2 = ( A0 += R1.H * R0.L ) (S2RND); -R5 = ( A1 = R1.L * R0.H ) (M), R4 = ( A0 -= R1.H * R0.L ) (S2RND); -CHECKREG r2, 0x00000820; -CHECKREG r3, 0x000001B0; -CHECKREG r4, 0x00000410; -CHECKREG r5, 0x000000D8; - -imm32 r0, 0x12345678; -imm32 r1, 0x34567897; -imm32 r2, 0x0acb1234; -imm32 r3, 0x456acb07; -imm32 r4, 0x421dbc09; -imm32 r5, 0x89acbd0b; -imm32 r6, 0x5adbcd0d; -imm32 r7, 0x9abc230f; -A1 += R7.L * R5.H, R2 = ( A0 = R7.H * R5.L ); -A1 -= R1.H * R2.L (M), R6 = ( A0 += R1.L * R2.H ) (S2RND); -CHECKREG r0, 0x12345678; -CHECKREG r1, 0x34567897; -CHECKREG r2, 0x34F8E428; -CHECKREG r3, 0x456ACB07; -CHECKREG r4, 0x421DBC09; -CHECKREG r5, 0x89ACBD0B; -CHECKREG r6, 0x7FFFFFFF; -CHECKREG r7, 0x9ABC230F; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr.s deleted file mode 100644 index 5ae44cb..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr/c_dsp32mult_dr.dsp -// Spec Reference: dsp32mult single dr -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x93ba5127; -imm32 r2, 0xa3446725; -imm32 r3, 0x00050027; -imm32 r4, 0xb0ab6d29; -imm32 r5, 0x10ace72b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467029; -R4.H = R0.L * R0.L, R4.L = R0.L * R0.L; -R5.H = R0.L * R1.L, R5.L = R0.L * R1.H; -R6.H = R1.L * R0.L, R6.L = R1.H * R0.L; -R7.H = R1.L * R1.L, R7.L = R1.H * R1.H; -R0.H = R0.L * R0.L, R0.L = R0.L * R0.L; -R1.H = R0.L * R1.L, R1.L = R0.L * R1.H; -R2.H = R1.L * R0.L, R2.L = R1.H * R0.L; -R3.H = R1.L * R1.L, R3.L = R1.H * R1.H; -CHECKREG r0, 0x39FA39FA; -CHECKREG r1, 0x24C2CEF5; -CHECKREG r2, 0xE9C910A6; -CHECKREG r3, 0x12CA0A8E; -CHECKREG r4, 0x39FA39FA; -CHECKREG r5, 0x369EB722; -CHECKREG r6, 0x369EB722; -CHECKREG r7, 0x33735B96; - -imm32 r0, 0x5b33a635; -imm32 r1, 0x6fbe5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x9006d037; -imm32 r4, 0x80abcb39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c00dd; -imm32 r7, 0x12469003; -R4.H = R2.L * R2.H, R4.L = R2.H * R2.L; -R5.H = R2.L * R3.H, R5.L = R2.H * R3.H; -R6.H = R3.L * R2.H, R6.L = R3.L * R2.L; -R7.H = R3.L * R3.H, R7.L = R3.L * R3.H; -R2.H = R2.L * R2.H, R2.L = R2.H * R2.L; -R3.H = R2.L * R3.H, R3.L = R2.H * R3.H; -R0.H = R3.L * R2.H, R0.L = R3.L * R2.L; -R1.H = R3.L * R3.H, R1.L = R3.L * R3.H; -CHECKREG r0, 0xFF31FF31; -CHECKREG r1, 0x00B500B5; -CHECKREG r2, 0xF51DF51D; -CHECKREG r3, 0x09860986; -CHECKREG r4, 0xF51DF51D; -CHECKREG r5, 0x3FAEEF41; -CHECKREG r6, 0xF8DB1B2D; -CHECKREG r7, 0x29CE29CE; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x00060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00c005d; -imm32 r7, 0x1246705f; -R0.H = R4.H * R4.L, R0.L = R4.L * R4.L; -R1.H = R4.H * R5.L, R1.L = R4.L * R5.H; -R2.H = R5.H * R4.L, R2.L = R5.H * R4.L; -R3.H = R5.H * R5.L, R3.L = R5.H * R5.H; -R4.H = R4.H * R4.L, R4.L = R4.L * R4.L; -R5.H = R4.H * R5.L, R5.L = R4.L * R5.H; -R6.H = R5.H * R4.L, R6.L = R5.H * R4.L; -R7.H = R5.H * R5.L, R7.L = R5.H * R5.H; -CHECKREG r0, 0x33491B2A; -CHECKREG r1, 0x0E7AF852; -CHECKREG r2, 0xF852F852; -CHECKREG r3, 0xFDD5022C; -CHECKREG r4, 0x33491B2A; -CHECKREG r5, 0xF955038A; -CHECKREG r6, 0xFE96FE96; -CHECKREG r7, 0xFFD10059; - -imm32 r0, 0xab235666; -imm32 r1, 0xeaba5166; -imm32 r2, 0x13d48766; -imm32 r3, 0xf00b0066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10ac5f6b; -imm32 r6, 0x800cb66d; -imm32 r7, 0x1246707f; -// test the unsigned U=1 -R0.H = R6.H * R6.H, R0.L = R6.L * R6.L; -R1.H = R6.H * R7.H, R1.L = R6.L * R7.H; -R2.H = R7.H * R6.H, R2.L = R7.H * R6.L; -R3.H = R7.H * R7.H, R3.L = R7.H * R7.H; -R6.H = R6.H * R6.H, R6.L = R6.L * R6.L; -R7.H = R6.H * R7.H, R7.L = R6.L * R7.H; -R4.H = R7.H * R6.H, R4.L = R7.H * R6.L; -R5.H = R7.H * R7.H, R5.L = R7.H * R7.H; -CHECKREG r0, 0x7FE82A4A; -CHECKREG r1, 0xEDBCF57F; -CHECKREG r2, 0xEDBCF57F; -CHECKREG r3, 0x029C029C; -CHECKREG r4, 0x12400609; -CHECKREG r5, 0x029B029B; -CHECKREG r6, 0x7FE82A4A; -CHECKREG r7, 0x1243060A; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R0.H = R0.L * R7.H (M), R0.L = R0.H * R7.L; -R1.H = R1.H * R6.H, R1.L = R1.H * R6.H; -R2.H = R2.H * R5.L, R2.L = R2.L * R5.L; -R3.H = R3.H * R4.L (M), R3.L = R3.H * R4.L; -R4.H = R4.L * R3.L, R4.L = R4.L * R3.H; -R5.H = R5.H * R2.L, R5.L = R5.H * R2.L; -R6.H = R6.L * R1.H, R6.L = R6.L * R1.L; -R7.H = R7.H * R0.L, R7.L = R7.H * R0.H; -CHECKREG r0, 0xF99C0A92; -CHECKREG r1, 0xFFFBFFFB; -CHECKREG r2, 0xFB31E621; -CHECKREG r3, 0x0005FFFE; -CHECKREG r4, 0x0001FFFE; -CHECKREG r5, 0xFCA1FCA1; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x0182FF16; - -imm32 r0, 0x9b235a75; -imm32 r1, 0xc9ba5127; -imm32 r2, 0x13946905; -imm32 r3, 0x00090007; -imm32 r4, 0x90ab9d09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d9d; -imm32 r7, 0x12467009; -R0.H = R7.H * R0.H, R0.L = R7.L * R0.L; -R1.H = R6.H * R1.L (M), R1.L = R6.H * R1.L; -R2.H = R5.H * R2.H, R2.L = R5.L * R2.L; -R3.H = R4.L * R3.H, R3.L = R4.H * R3.L; -R4.H = R3.H * R4.H, R4.L = R3.L * R4.L; -R5.H = R2.H * R5.L (M), R5.L = R2.H * R5.L; -R6.H = R1.L * R6.L, R6.L = R1.L * R6.H; -R7.H = R0.L * R7.H, R7.L = R0.H * R7.H; -CHECKREG r0, 0xF19A4F2D; -CHECKREG r1, 0x00040008; -CHECKREG r2, 0x028DEDD5; -CHECKREG r3, 0xFFF9FFFA; -CHECKREG r4, 0x00060005; -CHECKREG r5, 0x0255FF8F; -CHECKREG r6, 0x00010000; -CHECKREG r7, 0x0B4EFDF2; - -imm32 r0, 0x8b235675; -imm32 r1, 0xc8ba5127; -imm32 r2, 0x13846705; -imm32 r3, 0x00080007; -imm32 r4, 0x90ab8d09; -imm32 r5, 0x10ace8db; -imm32 r6, 0x000c008d; -imm32 r7, 0x12467008; -R2.H = R0.L * R6.L, R2.L = R0.L * R6.H; -R3.H = R1.H * R7.H (M), R3.L = R1.L * R7.L; -R0.H = R2.L * R0.L, R0.L = R2.H * R0.H; -R1.H = R3.H * R1.L, R1.L = R3.L * R1.H; -R4.H = R4.L * R2.L, R4.L = R4.L * R2.H; -R5.H = R5.L * R3.H, R5.L = R5.H * R3.L; -R6.H = R6.H * R4.L (M), R6.L = R6.L * R4.H; -R7.H = R7.L * R5.L, R7.L = R7.H * R5.H; -CHECKREG r0, 0x0005FFA9; -CHECKREG r1, 0xFD80E154; -CHECKREG r2, 0x005F0008; -CHECKREG r3, 0xFC0E4707; -CHECKREG r4, 0xFFF9FFAB; -CHECKREG r5, 0x00B70940; -CHECKREG r6, 0x000C0000; -CHECKREG r7, 0x0819001A; - -imm32 r0, 0xeb235675; -imm32 r1, 0xceba5127; -imm32 r2, 0x13e46705; -imm32 r3, 0x000e0007; -imm32 r4, 0x90abed09; -imm32 r5, 0x10aceedb; -imm32 r6, 0x000c00ed; -imm32 r7, 0x1246700e; -R4.H = R5.L * R2.L, R4.L = R5.L * R2.H; -R6.H = R6.H * R3.L (M), R6.L = R6.L * R3.H; -R0.H = R7.L * R4.H, R0.L = R7.H * R4.H; -R1.H = R0.L * R5.H, R1.L = R0.L * R5.L; -R2.H = R1.H * R6.L (M), R2.L = R1.L * R6.H; -R5.H = R2.L * R7.H, R5.L = R2.H * R7.L; -R3.H = R3.L * R0.L, R3.L = R3.L * R0.H; -R7.H = R4.L * R1.L, R7.L = R4.L * R1.H; -CHECKREG r0, 0xF3ECFE08; -CHECKREG r1, 0xFFBE0044; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x0000FFFF; -CHECKREG r4, 0xF234FD56; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0xFFFF0001; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_i.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_i.s deleted file mode 100644 index b0b34d5..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_i.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_i/c_dsp32mult_dr_i.dsp -// Spec Reference: dsp32mult single dr i -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x98ba5127; -imm32 r2, 0xa3846725; -imm32 r3, 0x00080027; -imm32 r4, 0xb0ab8d29; -imm32 r5, 0x10ace82b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467028; -R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IS); -R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IS); -R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IS); -R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IS); -R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IS); -R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IS); -R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IS); -R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IS); -CHECKREG r0, 0x7FFF7FFF; -CHECKREG r1, 0x7FFF8000; -CHECKREG r2, 0x80007FFF; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x7FFF7FFF; -CHECKREG r5, 0x7FFF8000; -CHECKREG r6, 0x7FFF8000; -CHECKREG r7, 0x7FFF7FFF; - -imm32 r0, 0x8923a635; -imm32 r1, 0x6f995137; -imm32 r2, 0x1824b735; -imm32 r3, 0x99860037; -imm32 r4, 0x8098cd39; -imm32 r5, 0xb0a98f3b; -imm32 r6, 0xa00c083d; -imm32 r7, 0x12467083; -R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IS); -R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IS); -R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IS); -R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IS); -R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IS); -R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IS); -R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IS); -R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IS); -CHECKREG r0, 0x80008000; -CHECKREG r1, 0x7FFF7FFF; -CHECKREG r2, 0x80008000; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x80008000; -CHECKREG r5, 0x7FFF8000; -CHECKREG r6, 0x80007FFF; -CHECKREG r7, 0x80008000; - -imm32 r0, 0x19235655; -imm32 r1, 0xc9ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x0a060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00a005d; -imm32 r7, 0x1246a05f; -R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IS); -R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IS); -R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IS); -R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IS); -R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IS); -R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IS); -R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IS); -R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IS); -CHECKREG r0, 0x7FFF7FFF; -CHECKREG r1, 0x7FFF8000; -CHECKREG r2, 0x80008000; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x7FFF7FFF; -CHECKREG r5, 0x80008000; -CHECKREG r6, 0x80008000; -CHECKREG r7, 0x7FFF7FFF; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xe0060066; -imm32 r4, 0x9eab9d69; -imm32 r5, 0x10ecef6b; -imm32 r6, 0x800ee06d; -imm32 r7, 0x12467e6f; -// test the unsigned U=1 -R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IS); -R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IS); -R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IS); -R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IS); -R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IS); -R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IS); -R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IS); -R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IS); -CHECKREG r0, 0x7FFF7FFF; -CHECKREG r1, 0x80008000; -CHECKREG r2, 0x80008000; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x7FFF7FFF; -CHECKREG r5, 0x7FFF7FFF; -CHECKREG r6, 0x7FFF7FFF; -CHECKREG r7, 0x7FFF7FFF; - -// mix order -imm32 r0, 0xac23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13c46705; -imm32 r3, 0xf0060007; -imm32 r4, 0x9faccd09; -imm32 r5, 0x10fcdfdb; -imm32 r6, 0x000fc00d; -imm32 r7, 0x1246ff0f; -R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (IS); -R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IS); -R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IS); -R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IS); -R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IS); -R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IS); -R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IS); -R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IS); -CHECKREG r0, 0x7FFF8000; -CHECKREG r1, 0x80007FFF; -CHECKREG r2, 0x80008000; -CHECKREG r3, 0x80008000; -CHECKREG r4, 0x7FFF7FFF; -CHECKREG r5, 0x80008000; -CHECKREG r6, 0x80008000; -CHECKREG r7, 0x80007FFF; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0xdd246905; -imm32 r3, 0x00d6d007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10aceddb; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R0.H = R5.H * R0.H, R0.L = R5.H * R0.L (IS); -R1.H = R6.H * R1.L, R1.L = R6.L * R1.L (IS); -R2.H = R7.H * R2.H, R2.L = R7.H * R2.H (IS); -R3.H = R0.L * R3.H, R3.L = R0.H * R3.L (IS); -R4.H = R1.H * R4.H, R4.L = R1.L * R4.L (IS); -R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (IS); -R6.H = R3.H * R6.H, R6.L = R3.L * R6.L (IS); -R7.H = R4.L * R7.H, R7.L = R4.H * R7.H (IS); -CHECKREG r0, 0x80007FFF; -CHECKREG r1, 0x7FFF7FFF; -CHECKREG r2, 0x80008000; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x80008000; -CHECKREG r5, 0x80007FFF; -CHECKREG r6, 0x7FFF7FFF; -CHECKREG r7, 0x80008000; - -imm32 r0, 0xfb235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13f46705; -imm32 r3, 0x000f0007; -imm32 r4, 0x90abfd09; -imm32 r5, 0x10acefdb; -imm32 r6, 0x000c00fd; -imm32 r7, 0x1246700f; -R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IS); -R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IS); -R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IS); -R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IS); -R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IS); -R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IS); -R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IS); -R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IS); -CHECKREG r0, 0x7FFF8000; -CHECKREG r1, 0x80007FFF; -CHECKREG r2, 0x7FFF7FFF; -CHECKREG r3, 0x80008000; -CHECKREG r4, 0x80008000; -CHECKREG r5, 0x7FFF8000; -CHECKREG r6, 0x80008000; -CHECKREG r7, 0x80007FFF; - -imm32 r0, 0xab2d5675; -imm32 r1, 0xcfbad127; -imm32 r2, 0x13246d05; -imm32 r3, 0x000600d7; -imm32 r4, 0x908bcd09; -imm32 r5, 0x10a9efdb; -imm32 r6, 0x000c500d; -imm32 r7, 0x1246760f; -R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (IS); -R6.H = R6.H * R3.L, R6.L = R6.H * R3.H (IS); -R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (IS); -R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (IS); -R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (IS); -R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (IS); -R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (IS); -R7.H = R4.H * R1.L, R7.L = R4.H * R1.H (IS); -CHECKREG r0, 0x80008000; -CHECKREG r1, 0x80007FFF; -CHECKREG r2, 0x7FFF7FFF; -CHECKREG r3, 0x80008000; -CHECKREG r4, 0x80008000; -CHECKREG r5, 0x7FFF7FFF; -CHECKREG r6, 0x0A140048; -CHECKREG r7, 0x80007FFF; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_ih.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_ih.s deleted file mode 100644 index 5236375..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_ih.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_ih/c_dsp32mult_dr_ih.dsp -// Spec Reference: dsp32mult single dr ih -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x98ba5127; -imm32 r2, 0xa3846725; -imm32 r3, 0x00080027; -imm32 r4, 0xb0ab8d29; -imm32 r5, 0x10ace82b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467028; -R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IH); -R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IH); -R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IH); -R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IH); -R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IH); -R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IH); -R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IH); -R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IH); -CHECKREG r0, 0x1CFD1CFD; -CHECKREG r1, 0x0930F44E; -CHECKREG r2, 0xFEAD010A; -CHECKREG r3, 0x00890054; -CHECKREG r4, 0x1CFD1CFD; -CHECKREG r5, 0x1B4FDD40; -CHECKREG r6, 0x1B4FDD40; -CHECKREG r7, 0x19BA29A9; - -imm32 r0, 0x9923a635; -imm32 r1, 0x6f995137; -imm32 r2, 0x1324b735; -imm32 r3, 0x99060037; -imm32 r4, 0x809bcd39; -imm32 r5, 0xb0a99f3b; -imm32 r6, 0xa00c093d; -imm32 r7, 0x12467093; -R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IH); -R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IH); -R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IH); -R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IH); -R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IH); -R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IH); -R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IH); -R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IH); -CHECKREG r0, 0xFFF4FFF4; -CHECKREG r1, 0x00050005; -CHECKREG r2, 0xFA8FFA8F; -CHECKREG r3, 0x02300230; -CHECKREG r4, 0xFA8FFA8F; -CHECKREG r5, 0x1D48F84D; -CHECKREG r6, 0xFFF00004; -CHECKREG r7, 0xFFEAFFEA; - -imm32 r0, 0x19235655; -imm32 r1, 0xc9ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x0a060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00a005d; -imm32 r7, 0x1246a05f; -R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IH); -R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IH); -R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IH); -R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IH); -R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IH); -R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IH); -R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IH); -R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IH); -CHECKREG r0, 0x19A50D95; -CHECKREG r1, 0x073DFC29; -CHECKREG r2, 0xFC29FC29; -CHECKREG r3, 0x01150116; -CHECKREG r4, 0x19A50D95; -CHECKREG r5, 0xFE55FF1E; -CHECKREG r6, 0xFFF4FFE9; -CHECKREG r7, 0x00010003; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xe0060066; -imm32 r4, 0x9eab9d69; -imm32 r5, 0x10ecef6b; -imm32 r6, 0x800ee06d; -imm32 r7, 0x12467e6f; -// test the unsigned U=1 -R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IH); -R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IH); -R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IH); -R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IH); -R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IH); -R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IH); -R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IH); -R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IH); -CHECKREG r0, 0x3FF203E5; -CHECKREG r1, 0xF6DEFDBF; -CHECKREG r2, 0xF6DEFDBF; -CHECKREG r3, 0x014E014E; -CHECKREG r4, 0x01240012; -CHECKREG r5, 0x00150015; -CHECKREG r6, 0x3FF203E5; -CHECKREG r7, 0x04910047; - -// mix order -imm32 r0, 0xac23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13c46705; -imm32 r3, 0x00060007; -imm32 r4, 0x90accd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000cc00d; -imm32 r7, 0x1246fc0f; -R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (IH); -R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IH); -R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IH); -R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IH); -R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IH); -R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IH); -R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IH); -R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IH); -CHECKREG r0, 0x0161FA04; -CHECKREG r1, 0xEBBA0004; -CHECKREG r2, 0xFD85FD85; -CHECKREG r3, 0xFFFFFFFF; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0xFFD7FFD7; -CHECKREG r6, 0xFFFFFFFF; -CHECKREG r7, 0xFF930019; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0xdd246905; -imm32 r3, 0x00d6d007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10aceddb; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (IH); -R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (IH); -R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (IH); -R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (IH); -R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (IH); -R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (IH); -R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (IH); -R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (IH); -CHECKREG r0, 0xF9F10675; -CHECKREG r1, 0xFFFE0423; -CHECKREG r2, 0xFDBB06D7; -CHECKREG r3, 0xFFA314DD; -CHECKREG r4, 0x00280013; -CHECKREG r5, 0xFFDA0029; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x0076FF91; - -imm32 r0, 0xfb235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13f46705; -imm32 r3, 0x000f0007; -imm32 r4, 0x90abfd09; -imm32 r5, 0x10acefdb; -imm32 r6, 0x000c00fd; -imm32 r7, 0x1246700f; -R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IH); -R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IH); -R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IH); -R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IH); -R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IH); -R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IH); -R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IH); -R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IH); -CHECKREG r0, 0x0001FFFE; -CHECKREG r1, 0xF94D00A6; -CHECKREG r2, 0x00550004; -CHECKREG r3, 0xFC8EEADF; -CHECKREG r4, 0x0000FFDB; -CHECKREG r5, 0x0038FEA0; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0xFF660004; - -imm32 r0, 0xab2d5675; -imm32 r1, 0xcfbad127; -imm32 r2, 0x13246d05; -imm32 r3, 0x000600d7; -imm32 r4, 0x908bcd09; -imm32 r5, 0x10a9efdb; -imm32 r6, 0x000c500d; -imm32 r7, 0x1246760f; -R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (IH); -R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (IH); -R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (IH); -R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (IH); -R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (IH); -R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (IH); -R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (IH); -R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (IH); -CHECKREG r0, 0xFF71FCD4; -CHECKREG r1, 0xFFCB0033; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0xFFFD0000; -CHECKREG r4, 0xF920FECB; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000002; -CHECKREG r7, 0xFFFF0000; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_is.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_is.s deleted file mode 100644 index f0813428..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_is.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_is/c_dsp32mult_dr_is.dsp -// Spec Reference: dsp32mult single dr is -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x98ba5127; -imm32 r2, 0xa3846725; -imm32 r3, 0x00080027; -imm32 r4, 0xb0ab8d29; -imm32 r5, 0x10ace82b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467028; -R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (ISS2); -R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (ISS2); -R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (ISS2); -R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (ISS2); -R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (ISS2); -R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (ISS2); -R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (ISS2); -R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (ISS2); -CHECKREG r0, 0x7FFF7FFF; -CHECKREG r1, 0x7FFF8000; -CHECKREG r2, 0x80007FFF; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x7FFF7FFF; -CHECKREG r5, 0x7FFF8000; -CHECKREG r6, 0x7FFF8000; -CHECKREG r7, 0x7FFF7FFF; - -imm32 r0, 0x9923a635; -imm32 r1, 0x6f995137; -imm32 r2, 0x1324b735; -imm32 r3, 0x99060037; -imm32 r4, 0x809bcd39; -imm32 r5, 0xb0a99f3b; -imm32 r6, 0xa00c093d; -imm32 r7, 0x12467093; -R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (ISS2); -R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (ISS2); -R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (ISS2); -R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (ISS2); -R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (ISS2); -R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (ISS2); -R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (ISS2); -R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (ISS2); -CHECKREG r0, 0x80008000; -CHECKREG r1, 0x7FFF7FFF; -CHECKREG r2, 0x80008000; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x80008000; -CHECKREG r5, 0x7FFF8000; -CHECKREG r6, 0x80007FFF; -CHECKREG r7, 0x80008000; - -imm32 r0, 0x19235655; -imm32 r1, 0xc9ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x0a060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00a005d; -imm32 r7, 0x1246a05f; -R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (ISS2); -R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (ISS2); -R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (ISS2); -R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (ISS2); -R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (ISS2); -R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (ISS2); -R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (ISS2); -R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (ISS2); -CHECKREG r0, 0x7FFF7FFF; -CHECKREG r1, 0x7FFF8000; -CHECKREG r2, 0x80008000; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x7FFF7FFF; -CHECKREG r5, 0x80008000; -CHECKREG r6, 0x80008000; -CHECKREG r7, 0x7FFF7FFF; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xe0060066; -imm32 r4, 0x9eab9d69; -imm32 r5, 0x10ecef6b; -imm32 r6, 0x800ee06d; -imm32 r7, 0x12467e6f; -// test the unsigned U=1 -R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (ISS2); -R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (ISS2); -R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (ISS2); -R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (ISS2); -R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (ISS2); -R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (ISS2); -R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (ISS2); -R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (ISS2); -CHECKREG r0, 0x7FFF7FFF; -CHECKREG r1, 0x80008000; -CHECKREG r2, 0x80008000; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x7FFF7FFF; -CHECKREG r5, 0x7FFF7FFF; -CHECKREG r6, 0x7FFF7FFF; -CHECKREG r7, 0x7FFF7FFF; - -// mix order -imm32 r0, 0xac23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13c46705; -imm32 r3, 0x00060007; -imm32 r4, 0x90accd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000cc00d; -imm32 r7, 0x1246fc0f; -R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (ISS2); -R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (ISS2); -R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (ISS2); -R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (ISS2); -R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (ISS2); -R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (ISS2); -R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (ISS2); -R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (ISS2); -CHECKREG r0, 0x7FFF8000; -CHECKREG r1, 0x80007FFF; -CHECKREG r2, 0x80008000; -CHECKREG r3, 0x80008000; -CHECKREG r4, 0x7FFF7FFF; -CHECKREG r5, 0x80008000; -CHECKREG r6, 0x80008000; -CHECKREG r7, 0x80007FFF; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0xdd246905; -imm32 r3, 0x00d6d007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10aceddb; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (ISS2); -R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (ISS2); -R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (ISS2); -R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (ISS2); -R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (ISS2); -R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (ISS2); -R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (ISS2); -R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (ISS2); -CHECKREG r0, 0x80007FFF; -CHECKREG r1, 0x80007FFF; -CHECKREG r2, 0x80007FFF; -CHECKREG r3, 0x80007FFF; -CHECKREG r4, 0x7FFF7FFF; -CHECKREG r5, 0x80007FFF; -CHECKREG r6, 0x80008000; -CHECKREG r7, 0x7FFF8000; - -imm32 r0, 0xfb235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13f46705; -imm32 r3, 0x000f0007; -imm32 r4, 0x90abfd09; -imm32 r5, 0x10acefdb; -imm32 r6, 0x000c00fd; -imm32 r7, 0x1246700f; -R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (ISS2); -R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (ISS2); -R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (ISS2); -R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (ISS2); -R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (ISS2); -R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (ISS2); -R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (ISS2); -R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (ISS2); -CHECKREG r0, 0x7FFF8000; -CHECKREG r1, 0x80007FFF; -CHECKREG r2, 0x7FFF7FFF; -CHECKREG r3, 0x80008000; -CHECKREG r4, 0x80008000; -CHECKREG r5, 0x7FFF8000; -CHECKREG r6, 0x80008000; -CHECKREG r7, 0x80007FFF; - -imm32 r0, 0xab2d5675; -imm32 r1, 0xcfbad127; -imm32 r2, 0x13246d05; -imm32 r3, 0x000600d7; -imm32 r4, 0x908bcd09; -imm32 r5, 0x10a9efdb; -imm32 r6, 0x000c500d; -imm32 r7, 0x1246760f; -R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (ISS2); -R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (ISS2); -R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (ISS2); -R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (ISS2); -R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (ISS2); -R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (ISS2); -R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (ISS2); -R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (ISS2); -CHECKREG r0, 0x80008000; -CHECKREG r1, 0x80007FFF; -CHECKREG r2, 0x7FFF7FFF; -CHECKREG r3, 0x80008000; -CHECKREG r4, 0x80008000; -CHECKREG r5, 0x7FFF7FFF; -CHECKREG r6, 0x14287FFF; -CHECKREG r7, 0x80007FFF; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_iu.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_iu.s deleted file mode 100644 index 83b1bc0..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_iu.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_iu/c_dsp32mult_dr_iu.dsp -// Spec Reference: dsp32mult single dr iu -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x00010002; -imm32 r1, 0x00023004; -imm32 r2, 0x03843725; -imm32 r3, 0x00084027; -imm32 r4, 0x00ab5d29; -imm32 r5, 0x00ac682b; -imm32 r6, 0x000c708d; -imm32 r7, 0x02462028; -R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IU); -R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IU); -R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IU); -R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IU); -R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IU); -R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IU); -R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IU); -R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IU); -CHECKREG r0, 0x00040004; -CHECKREG r1, 0xC0100008; -CHECKREG r2, 0x0020FFFF; -CHECKREG r3, 0x0040FFFF; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x60080004; -CHECKREG r6, 0x60080004; -CHECKREG r7, 0xFFFF0004; - -imm32 r0, 0x00230635; -imm32 r1, 0x00995137; -imm32 r2, 0x00240735; -imm32 r3, 0x00060037; -imm32 r4, 0x009b0239; -imm32 r5, 0x00a9933b; -imm32 r6, 0x000c093d; -imm32 r7, 0x12407093; -R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IU); -R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IU); -R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IU); -R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IU); -R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IU); -R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IU); -R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IU); -R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IU); -CHECKREG r0, 0xFFFFFFFF; -CHECKREG r1, 0xFFFFFFFF; -CHECKREG r2, 0xFFFFFFFF; -CHECKREG r3, 0xFFFFFFFF; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0x2B3E00D8; -CHECKREG r6, 0xFFFF07BC; -CHECKREG r7, 0x014A014A; - -imm32 r0, 0x09235655; -imm32 r1, 0x09ba5157; -imm32 r2, 0x03246755; -imm32 r3, 0x0a060055; -imm32 r4, 0x00ab6509; -imm32 r5, 0x00ac7f5b; -imm32 r6, 0x000a005d; -imm32 r7, 0x0246405f; -R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IU); -R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IU); -R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IU); -R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IU); -R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IU); -R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IU); -R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IU); -R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IU); -CHECKREG r0, 0xFFFFFFFF; -CHECKREG r1, 0xFFFFFFFF; -CHECKREG r2, 0xFFFFFFFF; -CHECKREG r3, 0xFFFF7390; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0xFFFFFFFF; -CHECKREG r7, 0xFFFFFFFF; - -imm32 r0, 0x00230666; -imm32 r1, 0x00ba0166; -imm32 r2, 0x00240766; -imm32 r3, 0x00060066; -imm32 r4, 0x03ab0d69; -imm32 r5, 0x10ec3f6b; -imm32 r6, 0x000e206d; -imm32 r7, 0x00460e6f; -// test the unsigned U=1 -R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IU); -R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IU); -R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IU); -R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IU); -R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IU); -R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IU); -R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IU); -R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IU); -CHECKREG r0, 0x00C4FFFF; -CHECKREG r1, 0x03D4FFFF; -CHECKREG r2, 0x03D4FFFF; -CHECKREG r3, 0x13241324; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0x00C4FFFF; -CHECKREG r7, 0x3598FFFF; - -// mix order -imm32 r0, 0x0023a675; -imm32 r1, 0x00ba5127; -imm32 r2, 0x00c46705; -imm32 r3, 0x00060007; -imm32 r4, 0x00accd09; -imm32 r5, 0x00acdfdb; -imm32 r6, 0x000cc00d; -imm32 r7, 0x0246fc0f; -R0.H = R0.L * R7.H, R0.L = R0.H * R7.H (IU); -R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IU); -R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IU); -R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IU); -R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IU); -R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IU); -R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IU); -R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IU); -CHECKREG r0, 0xFFFF4F92; -CHECKREG r1, 0xFFFFFFFF; -CHECKREG r2, 0xFFFFFFFF; -CHECKREG r3, 0xFFFFFFFF; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0xFFFFFFFF; -CHECKREG r7, 0xFFFFFFFF; - -imm32 r0, 0x00230a75; -imm32 r1, 0x00ba0127; -imm32 r2, 0x00240905; -imm32 r3, 0x00d60007; -imm32 r4, 0x00ab0d09; -imm32 r5, 0x00ac0ddb; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x0046000f; -R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (IU); -R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (IU); -R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (IU); -R3.H = R4.L * R3.H, R3.L = R4.H * R3.H (IU); -R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (IU); -R5.H = R2.H * R5.L, R5.L = R2.L * R5.H (IU); -R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (IU); -R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (IU); -CHECKREG r0, 0x0992FFFF; -CHECKREG r1, 0x08B8FFFF; -CHECKREG r2, 0x1830FFFF; -CHECKREG r3, 0xFFFF8EF2; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0x68A0FFFF; -CHECKREG r7, 0xFFFFFFFF; - -imm32 r0, 0x0b230675; -imm32 r1, 0x00ba0127; -imm32 r2, 0x03f40705; -imm32 r3, 0x000f0007; -imm32 r4, 0x00ab0d09; -imm32 r5, 0x10ac0fdb; -imm32 r6, 0x000c00fd; -imm32 r7, 0x1246000f; -R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IU); -R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IU); -R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IU); -R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IU); -R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IU); -R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IU); -R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IU); -R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IU); -CHECKREG r0, 0xFFFFFFFF; -CHECKREG r1, 0xFFFFFFFF; -CHECKREG r2, 0xFFFF4D7C; -CHECKREG r3, 0xFFFF0AE6; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0xFFFFFFFF; -CHECKREG r7, 0xFFFFFFFF; - -imm32 r0, 0x002d0675; -imm32 r1, 0x001a0027; -imm32 r2, 0x00240005; -imm32 r3, 0x000600d7; -imm32 r4, 0x008b0d09; -imm32 r5, 0x00a0000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x0006060f; -R3.H = R0.L * R2.L, R3.L = R0.L * R2.H (IU); -R4.H = R1.H * R3.L, R4.L = R1.H * R3.H (IU); -R5.H = R2.L * R4.L, R5.L = R2.L * R4.H (IU); -R6.H = R3.L * R5.H, R6.L = R3.L * R5.L (IU); -R0.H = R4.H * R6.L, R0.L = R4.H * R6.L (IU); -R1.H = R5.L * R7.H, R1.L = R5.H * R7.L (IU); -R2.H = R6.L * R0.L, R2.L = R6.L * R0.H (IU); -R7.H = R7.H * R1.L, R7.L = R7.L * R1.H (IU); -CHECKREG r0, 0xFFFFFFFF; -CHECKREG r1, 0xFFFFFFFF; -CHECKREG r2, 0xFFFFFFFF; -CHECKREG r3, 0x2049E874; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0xFFFFFFFF; -CHECKREG r7, 0xFFFFFFFF; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m.s deleted file mode 100644 index 3e42cae..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m.s +++ /dev/null @@ -1,211 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_m/c_dsp32mult_dr_m.dsp -// Spec Reference: dsp32mult single dr (mix) MUNOP -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x34235625; -imm32 r1, 0x9f7a5127; -imm32 r2, 0xa3286725; -imm32 r3, 0x00069027; -imm32 r4, 0xb0abc029; -imm32 r5, 0x10acef2b; -imm32 r6, 0xc00c00de; -imm32 r7, 0xd246712f; -R4.L = R0.L * R0.L; -R5.L = R0.L * R1.H; -R6.L = R1.H * R0.L; -R7.L = R1.H * R1.H; -R0.L = R0.L * R0.L; -R1.L = R0.L * R1.H; -R2.L = R1.H * R0.L; -R3.L = R1.H * R1.H; -CHECKREG r0, 0x342339FA; -CHECKREG r1, 0x9F7AD448; -CHECKREG r2, 0xA328D448; -CHECKREG r3, 0x000648CA; -CHECKREG r4, 0xB0AB39FA; -CHECKREG r5, 0x10ACBF0A; -CHECKREG r6, 0xC00CBF0A; -CHECKREG r7, 0xD24648CA; - -imm32 r0, 0x5b23a635; -imm32 r1, 0x6fba5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x90060037; -imm32 r4, 0x80abcd39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c003d; -imm32 r7, 0x12467003; -R4.L = R2.H * R2.L; -R5.L = R2.H * R3.H; -R6.L = R3.L * R2.L; -R7.L = R3.L * R3.H; -R0.L = R2.H * R2.L; -R1.L = R2.H * R3.H; -R2.L = R3.L * R2.L; -R3.L = R3.L * R3.H; -CHECKREG r0, 0x5B23F51D; -CHECKREG r1, 0x6FBAEF41; -CHECKREG r2, 0x1324FFE1; -CHECKREG r3, 0x9006FFD0; -CHECKREG r4, 0x80ABF51D; -CHECKREG r5, 0xB0ACEF41; -CHECKREG r6, 0xA00CFFE1; -CHECKREG r7, 0x1246FFD0; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x43246755; -imm32 r3, 0x05060055; -imm32 r4, 0x906bc509; -imm32 r5, 0x10a7ef5b; -imm32 r6, 0xb00c805d; -imm32 r7, 0x1246795f; -R0.L = R4.L * R4.L; -R1.L = R4.L * R5.H; -R2.L = R5.H * R4.L; -R3.L = R5.H * R5.H; -R4.L = R4.L * R4.L; -R5.L = R4.L * R5.H; -R6.L = R5.H * R4.L; -R7.L = R5.H * R5.H; -CHECKREG r0, 0x1B231B2A; -CHECKREG r1, 0xC4BAF854; -CHECKREG r2, 0x4324F854; -CHECKREG r3, 0x0506022B; -CHECKREG r4, 0x906B1B2A; -CHECKREG r5, 0x10A70389; -CHECKREG r6, 0xB00C0389; -CHECKREG r7, 0x1246022B; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xf0060066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10acef6b; -imm32 r6, 0x800cb06d; -imm32 r7, 0x1246706f; -// test the unsigned U=1 -R0.L = R6.L * R6.L; -R1.L = R6.L * R7.H; -R2.L = R7.H * R6.L; -R3.L = R7.H * R7.H; -R4.L = R6.L * R6.L; -R5.L = R6.L * R7.H; -R6.L = R7.H * R6.L; -R7.L = R7.H * R7.H; -CHECKREG r0, 0xBB233178; -CHECKREG r1, 0xEFBAF4A4; -CHECKREG r2, 0x1324F4A4; -CHECKREG r3, 0xF006029C; -CHECKREG r4, 0x90AB3178; -CHECKREG r5, 0x10ACF4A4; -CHECKREG r6, 0x800CF4A4; -CHECKREG r7, 0x1246029C; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R0.L = R0.H * R7.L; -R1.L = R1.H * R6.H; -R2.L = R2.L * R5.L; -R3.L = R3.H * R4.H; -R4.L = R4.L * R3.H; -R5.L = R5.H * R2.L; -R6.L = R6.L * R1.L; -R7.L = R7.H * R0.L; -CHECKREG r0, 0xAB230A92; -CHECKREG r1, 0xCFBAFFFB; -CHECKREG r2, 0x1324E621; -CHECKREG r3, 0x0006FFFB; -CHECKREG r4, 0x90ABFFFE; -CHECKREG r5, 0x10ACFCA1; -CHECKREG r6, 0x000C0000; -CHECKREG r7, 0x12460182; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246905; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R0.H = R7.H * R0.H; -R1.H = R6.H * R1.H; -R2.H = R5.H * R2.L; -R3.H = R4.H * R3.H; -R4.H = R3.L * R4.H; -R5.H = R2.H * R5.L; -R6.H = R1.H * R6.H; -R7.H = R0.L * R7.H; -CHECKREG r0, 0xF3E35A75; -CHECKREG r1, 0xFFFB5127; -CHECKREG r2, 0x0DAE6905; -CHECKREG r3, 0xFFFB0007; -CHECKREG r4, 0xFFFACD09; -CHECKREG r5, 0xFDA2E9DB; -CHECKREG r6, 0x00000D0D; -CHECKREG r7, 0x0CEA700F; - -imm32 r0, 0x9b235675; -imm32 r1, 0xc9ba5127; -imm32 r2, 0x13946705; -imm32 r3, 0x00090007; -imm32 r4, 0x90ab9d09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c009d; -imm32 r7, 0x12467009; -R2.H = R0.L * R6.L; -R3.H = R1.H * R7.L; -R0.H = R2.L * R0.L; -R1.H = R3.L * R1.H; -R4.H = R4.H * R2.H; -R5.H = R5.L * R3.H; -R6.H = R6.H * R4.L; -R7.H = R7.L * R5.H; -CHECKREG r0, 0x45965675; -CHECKREG r1, 0xFFFD5127; -CHECKREG r2, 0x006A6705; -CHECKREG r3, 0xD07F0007; -CHECKREG r4, 0xFFA49D09; -CHECKREG r5, 0x0838E9DB; -CHECKREG r6, 0xFFF7009D; -CHECKREG r7, 0x07327009; - -imm32 r0, 0xeb235675; -imm32 r1, 0xceba5127; -imm32 r2, 0x13e46705; -imm32 r3, 0x000e0007; -imm32 r4, 0x90abed09; -imm32 r5, 0x10aceedb; -imm32 r6, 0x000c00ed; -imm32 r7, 0x1246700e; -R4.H = R5.L * R2.L; -R6.H = R6.H * R3.H; -R0.H = R7.H * R4.L; -R1.H = R0.H * R5.L; -R2.H = R1.H * R6.H; -R5.H = R2.H * R7.L; -R3.H = R3.H * R0.L; -R7.H = R4.L * R1.H; -CHECKREG r0, 0xFD4B5675; -CHECKREG r1, 0x005D5127; -CHECKREG r2, 0x00006705; -CHECKREG r3, 0x00090007; -CHECKREG r4, 0xF234ED09; -CHECKREG r5, 0x0000EEDB; -CHECKREG r6, 0x000000ED; -CHECKREG r7, 0xFFF2700E; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_i.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_i.s deleted file mode 100644 index 6860a13..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_i.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_m_i/c_dsp32mult_dr_m_i.dsp -// Spec Reference: dsp32mult single dr munop i -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0xfb235625; -imm32 r1, 0x9fba5127; -imm32 r2, 0xa3ff6725; -imm32 r3, 0x0006f027; -imm32 r4, 0xb0abcd29; -imm32 r5, 0x1facef2b; -imm32 r6, 0xc0fc002d; -imm32 r7, 0xd24f702f; -R4.L = R0.H * R0.L (IS); -R5.H = R0.L * R1.L (IS); -R6.L = R1.L * R0.H (IS); -R7.L = R1.L * R1.L (IS); -R0.H = R0.L * R0.L (IS); -R1.L = R0.L * R1.L (IS); -R2.L = R1.H * R0.L (IS); -R3.H = R1.L * R1.L (IS); -CHECKREG r0, 0x7FFF5625; -CHECKREG r1, 0x9FBA7FFF; -CHECKREG r2, 0xA3FF8000; -CHECKREG r3, 0x7FFFF027; -CHECKREG r4, 0xB0AB8000; -CHECKREG r5, 0x7FFFEF2B; -CHECKREG r6, 0xC0FC8000; -CHECKREG r7, 0xD24F7FFF; - -imm32 r0, 0xeb23a635; -imm32 r1, 0x6fba5137; -imm32 r2, 0x1324b7e5; -imm32 r3, 0x9e060037; -imm32 r4, 0x80ebcd39; -imm32 r5, 0xb0aeef3b; -imm32 r6, 0xa00ce03d; -imm32 r7, 0x12467e03; -R5.H = R2.L * R2.L (IS); -R6.L = R2.L * R3.H (IS); -R7.L = R3.H * R2.L (IS); -R0.H = R3.L * R3.L (IS); -R1.H = R2.L * R2.H (IS); -R2.L = R2.H * R3.H (IS); -R3.H = R3.L * R2.L (IS); -R4.L = R3.L * R3.L (IS); -CHECKREG r0, 0x0BD1A635; -CHECKREG r1, 0x80005137; -CHECKREG r2, 0x13248000; -CHECKREG r3, 0x80000037; -CHECKREG r4, 0x80EB0BD1; -CHECKREG r5, 0x7FFFEF3B; -CHECKREG r6, 0xA00C7FFF; -CHECKREG r7, 0x12467FFF; - -imm32 r0, 0xdd235655; -imm32 r1, 0xc4dd5157; -imm32 r2, 0x6324d755; -imm32 r3, 0x00060055; -imm32 r4, 0x90dbc509; -imm32 r5, 0x10adef5b; -imm32 r6, 0xb00cd05d; -imm32 r7, 0x12467d5f; -R0.L = R4.L * R4.H (IS); -R1.H = R4.H * R5.L (IS); -R2.L = R5.H * R4.L (IS); -R3.L = R5.L * R5.L (IS); -R4.H = R4.L * R4.H (IS); -R5.L = R4.L * R5.H (IS); -R6.H = R5.H * R4.H (IS); -R7.L = R5.H * R5.H (IS); -CHECKREG r0, 0xDD237FFF; -CHECKREG r1, 0x7FFF5157; -CHECKREG r2, 0x63248000; -CHECKREG r3, 0x00067FFF; -CHECKREG r4, 0x7FFFC509; -CHECKREG r5, 0x10AD8000; -CHECKREG r6, 0x7FFFD05D; -CHECKREG r7, 0x12467FFF; - -imm32 r0, 0xcb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x1c248766; -imm32 r3, 0xf0060066; -imm32 r4, 0x90cb9d69; -imm32 r5, 0x10acef6b; -imm32 r6, 0x800cc06d; -imm32 r7, 0x12467c6f; -// test the unsigned U=1 -R0.L = R6.L * R6.L (IS); -R1.H = R6.H * R7.L (IS); -R2.L = R7.L * R6.L (IS); -R3.L = R7.L * R7.L (IS); -R6.H = R6.H * R6.H (IS); -R7.L = R6.L * R7.L (IS); -R4.H = R7.H * R6.H (IS); -R5.L = R7.L * R7.L (IS); -CHECKREG r0, 0xCB237FFF; -CHECKREG r1, 0x80005166; -CHECKREG r2, 0x1C248000; -CHECKREG r3, 0xF0067FFF; -CHECKREG r4, 0x7FFF9D69; -CHECKREG r5, 0x10AC7FFF; -CHECKREG r6, 0x7FFFC06D; -CHECKREG r7, 0x12468000; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0xe0060007; -imm32 r4, 0x9eabcd09; -imm32 r5, 0x10ecdfdb; -imm32 r6, 0x000e000d; -imm32 r7, 0x1246e00f; -R0.H = R0.L * R7.H (IS); -R1.L = R1.H * R6.H (IS); -R2.L = R2.L * R5.L (IS); -R3.H = R3.H * R4.H (IS); -R4.L = R4.L * R3.H (IS); -R5.L = R5.H * R2.H (IS); -R6.H = R6.H * R1.L (IS); -R7.L = R7.L * R0.H (IS); -CHECKREG r0, 0x8000A675; -CHECKREG r1, 0xCFBA8000; -CHECKREG r2, 0x13248000; -CHECKREG r3, 0x7FFF0007; -CHECKREG r4, 0x9EAB8000; -CHECKREG r5, 0x10EC7FFF; -CHECKREG r6, 0x8000000D; -CHECKREG r7, 0x12467FFF; - -imm32 r0, 0x9b235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0x93246905; -imm32 r3, 0x09060007; -imm32 r4, 0x909bcd09; -imm32 r5, 0x10a9e9db; -imm32 r6, 0x000c9d0d; -imm32 r7, 0x1246790f; -R0.L = R7.L * R0.H (IS); -R1.L = R6.L * R1.L (IS); -R2.H = R5.L * R2.L (IS); -R3.L = R4.H * R3.L (IS); -R4.L = R3.H * R4.H (IS); -R5.H = R2.H * R5.L (IS); -R6.L = R1.H * R6.L (IS); -R7.L = R0.L * R7.L (IS); -CHECKREG r0, 0x9B238000; -CHECKREG r1, 0xCFBA8000; -CHECKREG r2, 0x80006905; -CHECKREG r3, 0x09068000; -CHECKREG r4, 0x909B8000; -CHECKREG r5, 0x7FFFE9DB; -CHECKREG r6, 0x000C7FFF; -CHECKREG r7, 0x12468000; - -imm32 r0, 0xa9235675; -imm32 r1, 0xc8ba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x08060007; -imm32 r4, 0x908bcd09; -imm32 r5, 0x10a88fdb; -imm32 r6, 0x000c080d; -imm32 r7, 0x1246708f; -R2.L = R0.L * R6.L (IS); -R3.L = R1.H * R7.L (IS); -R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IS); -R1.H = R3.L * R1.L (IS); -R4.L = R4.H * R2.L (IS); -R5.L = R5.L * R3.L (IS); -R6.L = R6.L * R4.L (IS); -R7.H = R7.H * R5.L (IS); -CHECKREG r0, 0x7FFF8000; -CHECKREG r1, 0x80005127; -CHECKREG r2, 0x13247FFF; -CHECKREG r3, 0x08068000; -CHECKREG r4, 0x908B8000; -CHECKREG r5, 0x10A87FFF; -CHECKREG r6, 0x000C8000; -CHECKREG r7, 0x7FFF708F; - -imm32 r0, 0x7b235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x17246705; -imm32 r3, 0x00760007; -imm32 r4, 0x907bcd09; -imm32 r5, 0x10a7efdb; -imm32 r6, 0x000c700d; -imm32 r7, 0x1246770f; -R4.L = R5.L * R2.L (IS); -R6.L = R6.L * R3.H (IS); -R0.H = R7.L * R4.H (IS); -R1.L = R0.H * R5.L (IS); -R2.L = R1.L * R6.L (IS); -R5.L = R2.L * R7.H (IS); -R3.H = R3.H * R0.L (IS); -R7.L = R4.H * R1.H (IS); -CHECKREG r0, 0x80005675; -CHECKREG r1, 0xCFBA7FFF; -CHECKREG r2, 0x17247FFF; -CHECKREG r3, 0x7FFF0007; -CHECKREG r4, 0x907B8000; -CHECKREG r5, 0x10A77FFF; -CHECKREG r6, 0x000C7FFF; -CHECKREG r7, 0x12467FFF; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_iutsh.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_iutsh.s deleted file mode 100644 index 4f38460..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_iutsh.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_m_iutsh/c_dsp32mult_dr_m_iutsh.dsp -// Spec Reference: dsp32mult single dr munop iu tu is ih -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0xfb235625; -imm32 r1, 0x9fba5127; -imm32 r2, 0xa3ff6725; -imm32 r3, 0x0006f027; -imm32 r4, 0xb0abcd29; -imm32 r5, 0x1facef2b; -imm32 r6, 0xc0fc002d; -imm32 r7, 0xd24f702f; -R4.L = R0.H * R0.L (TFU); -R5.H = R0.L * R1.L (IU); -R6.L = R1.L * R0.H (TFU); -R7.L = R1.L * R1.L (TFU); -R0.H = R0.L * R0.L (IU); -R1.L = R0.L * R1.L (TFU); -R2.L = R1.H * R0.L (IU); -R3.H = R1.L * R1.L (TFU); -CHECKREG r0, 0xFFFF5625; -CHECKREG r1, 0x9FBA1B4E; -CHECKREG r2, 0xA3FFFFFF; -CHECKREG r3, 0x02E9F027; -CHECKREG r4, 0xB0AB5482; -CHECKREG r5, 0xFFFFEF2B; -CHECKREG r6, 0xC0FC4F9C; -CHECKREG r7, 0xD24F19B9; - -imm32 r0, 0xeb23a635; -imm32 r1, 0x6fba5137; -imm32 r2, 0x1324b7e5; -imm32 r3, 0x9e060037; -imm32 r4, 0x80ebcd39; -imm32 r5, 0xb0aeef3b; -imm32 r6, 0xa00ce03d; -imm32 r7, 0x12467e03; -R4.H = R2.L * R2.L (ISS2); -R5.L = R2.L * R3.H (IH); -R6.L = R3.H * R2.L (ISS2); -R7.H = R3.L * R3.L (ISS2); -R2.H = R2.L * R2.H (IH); -R3.L = R2.H * R3.H (ISS2); -R0.H = R3.L * R2.L (IH); -R1.L = R3.L * R3.L (ISS2); -CHECKREG r0, 0xDBF3A635; -CHECKREG r1, 0x6FBA7FFF; -CHECKREG r2, 0xFA9CB7E5; -CHECKREG r3, 0x9E067FFF; -CHECKREG r4, 0x7FFFCD39; -CHECKREG r5, 0xB0AE1B99; -CHECKREG r6, 0xA00C7FFF; -CHECKREG r7, 0x17A27E03; - -imm32 r0, 0xdd235655; -imm32 r1, 0xc4dd5157; -imm32 r2, 0x6324d755; -imm32 r3, 0x00060055; -imm32 r4, 0x90dbc509; -imm32 r5, 0x10adef5b; -imm32 r6, 0xb00cd05d; -imm32 r7, 0x12467d5f; -R0.L = R4.L * R4.H (IU); -R1.H = R4.H * R5.L (TFU); -R2.L = R5.H * R4.L (ISS2); -R3.L = R5.L * R5.L (IH); -R4.H = R4.L * R4.H (ISS2); -R5.L = R4.L * R5.H (TFU); -R6.H = R5.H * R4.H (IU); -R7.L = R5.H * R5.H (ISS2); -CHECKREG r0, 0xDD23FFFF; -CHECKREG r1, 0x876F5157; -CHECKREG r2, 0x63248000; -CHECKREG r3, 0x00060115; -CHECKREG r4, 0x7FFFC509; -CHECKREG r5, 0x10AD0CD5; -CHECKREG r6, 0xFFFFD05D; -CHECKREG r7, 0x12467FFF; - -imm32 r0, 0xcb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x1c248766; -imm32 r3, 0xf0060066; -imm32 r4, 0x90cb9d69; -imm32 r5, 0x10acef6b; -imm32 r6, 0x800cc06d; -imm32 r7, 0x12467c6f; -// test the unsigned U=1 -R0.L = R6.L * R6.L (TFU); -R1.H = R6.H * R7.L (IH); -R2.L = R7.L * R6.L (ISS2); -R3.L = R7.L * R7.L (IH); -R6.L = R6.L * R6.L (TFU); -R7.L = R6.L * R7.L (IH); -R4.L = R7.L * R6.L (TFU); -R5.L = R7.L * R7.L (ISS2); -CHECKREG r0, 0xCB2390A3; -CHECKREG r1, 0xC1CE5166; -CHECKREG r2, 0x1C248000; -CHECKREG r3, 0xF0063C7C; -CHECKREG r4, 0x90CB720D; -CHECKREG r5, 0x10AC7FFF; -CHECKREG r6, 0x800C90A3; -CHECKREG r7, 0x1246C9DF; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0xe0060007; -imm32 r4, 0x9eabcd09; -imm32 r5, 0x10ecdfdb; -imm32 r6, 0x000e000d; -imm32 r7, 0x1246e00f; -R0.H = R0.L * R7.H (IU); -R1.L = R1.H * R6.H (ISS2); -R2.L = R2.L * R5.L (IU); -R3.H = R3.H * R4.H (ISS2); -R4.L = R4.L * R3.H (IU); -R5.L = R5.H * R2.H (ISS2); -R6.H = R6.H * R1.L (IH); -R7.L = R7.L * R0.H (IU); -CHECKREG r0, 0xFFFFA675; -CHECKREG r1, 0xCFBA8000; -CHECKREG r2, 0x1324FFFF; -CHECKREG r3, 0x7FFF0007; -CHECKREG r4, 0x9EABFFFF; -CHECKREG r5, 0x10EC7FFF; -CHECKREG r6, 0xFFF9000D; -CHECKREG r7, 0x1246FFFF; - -imm32 r0, 0x9b235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0x93246905; -imm32 r3, 0x09060007; -imm32 r4, 0x909bcd09; -imm32 r5, 0x10a9e9db; -imm32 r6, 0x000c9d0d; -imm32 r7, 0x1246790f; -R0.L = R7.L * R0.H (TFU); -R1.L = R6.L * R1.L (TFU); -R2.H = R5.L * R2.L (TFU); -R3.L = R4.H * R3.L (TFU); -R4.L = R3.H * R4.H (TFU); -R5.H = R2.H * R5.L (TFU); -R6.L = R1.H * R6.L (TFU); -R7.L = R0.L * R7.L (TFU); -CHECKREG r0, 0x9B23495C; -CHECKREG r1, 0xCFBA31C9; -CHECKREG r2, 0x5FEF6905; -CHECKREG r3, 0x09060003; -CHECKREG r4, 0x909B0518; -CHECKREG r5, 0x57A2E9DB; -CHECKREG r6, 0x000C7F6F; -CHECKREG r7, 0x124622B0; - -imm32 r0, 0xa9235675; -imm32 r1, 0xc8ba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x08060007; -imm32 r4, 0x908bcd09; -imm32 r5, 0x10a88fdb; -imm32 r6, 0x000c080d; -imm32 r7, 0x1246708f; -R2.L = R0.L * R6.L (IU); -R3.L = R1.H * R7.L (IH); -R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IU); -R1.H = R3.L * R1.L (IH); -R4.L = R4.H * R2.L (IU); -R5.L = R5.L * R3.L (ISS2); -R6.L = R6.L * R4.L (IH); -R7.H = R7.H * R5.L (IU); -CHECKREG r0, 0xFFFFFFFF; -CHECKREG r1, 0xF84C5127; -CHECKREG r2, 0x1324FFFF; -CHECKREG r3, 0x0806E7B2; -CHECKREG r4, 0x908BFFFF; -CHECKREG r5, 0x10A87FFF; -CHECKREG r6, 0x000C0000; -CHECKREG r7, 0xFFFF708F; - -imm32 r0, 0x7b235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x17246705; -imm32 r3, 0x00760007; -imm32 r4, 0x907bcd09; -imm32 r5, 0x10a7efdb; -imm32 r6, 0x000c700d; -imm32 r7, 0x1246770f; -R4.L = R5.L * R2.L (TFU); -R6.L = R6.L * R3.H (ISS2); -R0.H = R7.L * R4.H (ISS2); -R1.L = R0.H * R5.L (ISS2); -R2.L = R1.L * R6.L (IH); -R5.L = R2.L * R7.H (TFU); -R3.H = R3.H * R0.L (IH); -R7.L = R4.H * R1.H (IU); -CHECKREG r0, 0x80005675; -CHECKREG r1, 0xCFBA7FFF; -CHECKREG r2, 0x17243FFF; -CHECKREG r3, 0x00280007; -CHECKREG r4, 0x907B6085; -CHECKREG r5, 0x10A70491; -CHECKREG r6, 0x000C7FFF; -CHECKREG r7, 0x1246FFFF; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_s.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_s.s deleted file mode 100644 index 670d9d3..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_s.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_m_s/c_dsp32mult_dr_m_s.dsp -// Spec Reference: dsp32mult single dr munop s -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0xfb235625; -imm32 r1, 0x9fba5127; -imm32 r2, 0xa3ff6725; -imm32 r3, 0x0006f027; -imm32 r4, 0xb0abcd29; -imm32 r5, 0x1facef2b; -imm32 r6, 0xc0fc002d; -imm32 r7, 0xd24f702f; -R4.L = R0.H * R0.L (S2RND); -R5.H = R0.L * R1.L (S2RND); -R6.L = R1.L * R0.H (S2RND); -R7.L = R1.L * R1.L (S2RND); -R0.H = R0.L * R0.L (S2RND); -R1.L = R0.L * R1.L (S2RND); -R2.L = R1.H * R0.L (S2RND); -R3.H = R1.L * R1.L (S2RND); -CHECKREG r0, 0x73F45625; -CHECKREG r1, 0x9FBA6D3B; -CHECKREG r2, 0xA3FF8000; -CHECKREG r3, 0x7FFFF027; -CHECKREG r4, 0xB0ABF974; -CHECKREG r5, 0x6D3BEF2B; -CHECKREG r6, 0xC0FCF9D5; -CHECKREG r7, 0xD24F66E7; - -imm32 r0, 0xeb23a635; -imm32 r1, 0x6fba5137; -imm32 r2, 0x1324b7e5; -imm32 r3, 0x9e060037; -imm32 r4, 0x80ebcd39; -imm32 r5, 0xb0aeef3b; -imm32 r6, 0xa00ce03d; -imm32 r7, 0x12467e03; -R4.H = R2.L * R2.L (S2RND); -R5.L = R2.L * R3.H (S2RND); -R6.L = R3.H * R2.L (S2RND); -R7.H = R3.L * R3.L (S2RND); -R2.H = R2.L * R2.H (S2RND); -R3.L = R2.H * R3.H (S2RND); -R0.H = R3.L * R2.L (S2RND); -R1.L = R3.L * R3.L (S2RND); -CHECKREG r0, 0xDACEA635; -CHECKREG r1, 0x6FBA1108; -CHECKREG r2, 0xEA6FB7E5; -CHECKREG r3, 0x9E062104; -CHECKREG r4, 0x513DCD39; -CHECKREG r5, 0xB0AE6E63; -CHECKREG r6, 0xA00C6E63; -CHECKREG r7, 0x00007E03; - -imm32 r0, 0xdd235655; -imm32 r1, 0xc4dd5157; -imm32 r2, 0x6324d755; -imm32 r3, 0x00060055; -imm32 r4, 0x90dbc509; -imm32 r5, 0x10adef5b; -imm32 r6, 0xb00cd05d; -imm32 r7, 0x12467d5f; -R0.L = R4.L * R4.H (S2RND); -R1.H = R4.H * R5.L (S2RND); -R2.L = R5.H * R4.L (S2RND); -R3.L = R5.L * R5.L (S2RND); -R4.H = R4.L * R4.H (S2RND); -R5.L = R4.L * R5.H (S2RND); -R6.H = R5.H * R4.H (S2RND); -R7.L = R5.H * R5.H (S2RND); -CHECKREG r0, 0xDD236666; -CHECKREG r1, 0x1CE85157; -CHECKREG r2, 0x6324F0A3; -CHECKREG r3, 0x00060454; -CHECKREG r4, 0x6666C509; -CHECKREG r5, 0x10ADF0A3; -CHECKREG r6, 0x1AAED05D; -CHECKREG r7, 0x12460458; - -imm32 r0, 0xcb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x1c248766; -imm32 r3, 0xf0060066; -imm32 r4, 0x90cb9d69; -imm32 r5, 0x10acef6b; -imm32 r6, 0x800cc06d; -imm32 r7, 0x12467c6f; -// test the unsigned U=1 -R0.L = R6.L * R6.L (S2RND); -R1.H = R6.H * R7.L (S2RND); -R2.L = R7.L * R6.L (S2RND); -R3.L = R7.L * R7.L (S2RND); -R6.L = R6.L * R6.L (S2RND); -R7.L = R6.L * R7.L (S2RND); -R4.L = R7.L * R6.L (S2RND); -R5.L = R7.L * R7.L (S2RND); -CHECKREG r0, 0xCB233F27; -CHECKREG r1, 0x80005166; -CHECKREG r2, 0x1C248465; -CHECKREG r3, 0xF0067FFF; -CHECKREG r4, 0x90CB7929; -CHECKREG r5, 0x10AC7FFF; -CHECKREG r6, 0x800C3F27; -CHECKREG r7, 0x12467AC9; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0xe0060007; -imm32 r4, 0x9eabcd09; -imm32 r5, 0x10ecdfdb; -imm32 r6, 0x000e000d; -imm32 r7, 0x1246e00f; -R0.H = R0.L * R7.H (S2RND); -R1.L = R1.H * R6.H (S2RND); -R2.L = R2.L * R5.L (S2RND); -R3.H = R3.H * R4.H (S2RND); -R4.L = R4.L * R3.H (S2RND); -R5.L = R5.H * R2.H (S2RND); -R6.H = R6.H * R1.L (S2RND); -R7.L = R7.L * R0.H (S2RND); -CHECKREG r0, 0xE66FA675; -CHECKREG r1, 0xCFBAFFF5; -CHECKREG r2, 0x1324CC42; -CHECKREG r3, 0x30A10007; -CHECKREG r4, 0x9EABD947; -CHECKREG r5, 0x10EC0510; -CHECKREG r6, 0x0000000D; -CHECKREG r7, 0x12460CC3; - -imm32 r0, 0x9b235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0x93246905; -imm32 r3, 0x09060007; -imm32 r4, 0x909bcd09; -imm32 r5, 0x10a9e9db; -imm32 r6, 0x000c9d0d; -imm32 r7, 0x1246790f; -R0.L = R7.L * R0.H (S2RND); -R1.L = R6.L * R1.L (S2RND); -R2.H = R5.L * R2.L (S2RND); -R3.L = R4.H * R3.L (S2RND); -R4.L = R3.H * R4.H (S2RND); -R5.H = R2.H * R5.L (S2RND); -R6.L = R1.H * R6.L (S2RND); -R7.L = R0.L * R7.L (S2RND); -CHECKREG r0, 0x9B238000; -CHECKREG r1, 0xCFBA8288; -CHECKREG r2, 0xDBAA6905; -CHECKREG r3, 0x0906FFF4; -CHECKREG r4, 0x909BF04B; -CHECKREG r5, 0x0C93E9DB; -CHECKREG r6, 0x000C4AA2; -CHECKREG r7, 0x12468000; - -imm32 r0, 0xa9235675; -imm32 r1, 0xc8ba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x08060007; -imm32 r4, 0x908bcd09; -imm32 r5, 0x10a88fdb; -imm32 r6, 0x000c080d; -imm32 r7, 0x1246708f; -R2.L = R4.L * R6.L (S2RND); -R3.L = R2.H * R2.L (S2RND); -R0.H = R2.L * R3.L, R0.L = R2.H * R3.H (S2RND); -R1.H = R3.L * R1.L (S2RND); -R4.L = R4.H * R0.L (S2RND); -R5.L = R5.L * R5.L (S2RND); -R6.L = R6.L * R5.H (S2RND); -R7.H = R6.H * R7.L (S2RND); -CHECKREG r0, 0x00310266; -CHECKREG r1, 0xFD915127; -CHECKREG r2, 0x1324F997; -CHECKREG r3, 0x0806FE15; -CHECKREG r4, 0x908BFBD3; -CHECKREG r5, 0x10A87FFF; -CHECKREG r6, 0x000C0218; -CHECKREG r7, 0x0015708F; - -imm32 r0, 0x7b235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x17246705; -imm32 r3, 0x00760007; -imm32 r4, 0x907bcd09; -imm32 r5, 0x10a7efdb; -imm32 r6, 0x000c700d; -imm32 r7, 0x1246770f; -R4.L = R5.L * R2.L (S2RND); -R6.L = R6.L * R3.H (S2RND); -R0.H = R7.L * R4.H (S2RND); -R1.L = R0.H * R5.L (S2RND); -R2.L = R1.L * R6.L (S2RND); -R5.L = R2.L * R7.H (S2RND); -R3.H = R3.H * R0.L (S2RND); -R7.L = R4.H * R1.H (S2RND); -CHECKREG r0, 0x80005675; -CHECKREG r1, 0xCFBA204A; -CHECKREG r2, 0x17240068; -CHECKREG r3, 0x009F0007; -CHECKREG r4, 0x907BE603; -CHECKREG r5, 0x10A7001E; -CHECKREG r6, 0x000C00CF; -CHECKREG r7, 0x1246541E; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_t.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_t.s deleted file mode 100644 index 4dc42e8..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_t.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_m_t/c_dsp32mult_dr_m_t.dsp -// Spec Reference: dsp32mult single dr munop t -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0xfb235625; -imm32 r1, 0x9fba5127; -imm32 r2, 0xa3ff6725; -imm32 r3, 0x0006f027; -imm32 r4, 0xb0abcd29; -imm32 r5, 0x1facef2b; -imm32 r6, 0xc0fc002d; -imm32 r7, 0xd24f702f; -R4.L = R0.H * R0.L (T); -R5.H = R0.L * R1.L (T); -R6.L = R1.L * R0.H (T); -R7.L = R1.L * R1.L (T); -R0.H = R0.L * R0.L (T); -R1.L = R0.L * R1.L (T); -R2.L = R1.H * R0.L (T); -R3.H = R1.L * R1.L (T); -CHECKREG r0, 0x39F95625; -CHECKREG r1, 0x9FBA369D; -CHECKREG r2, 0xA3FFBF35; -CHECKREG r3, 0x174DF027; -CHECKREG r4, 0xB0ABFCBA; -CHECKREG r5, 0x369DEF2B; -CHECKREG r6, 0xC0FCFCEA; -CHECKREG r7, 0xD24F3373; - -imm32 r0, 0xeb23a635; -imm32 r1, 0x6fba5137; -imm32 r2, 0x1324b7e5; -imm32 r3, 0x9e060037; -imm32 r4, 0x80ebcd39; -imm32 r5, 0xb0aeef3b; -imm32 r6, 0xa00ce03d; -imm32 r7, 0x12467e03; -R4.H = R2.L * R2.L (T); -R5.L = R2.L * R3.H (T); -R6.L = R3.H * R2.L (T); -R7.H = R3.L * R3.L (T); -R2.H = R2.L * R2.H (T); -R3.L = R2.H * R3.H (T); -R0.H = R3.L * R2.L (T); -R1.L = R3.L * R3.L (T); -CHECKREG r0, 0xFB59A635; -CHECKREG r1, 0x6FBA0088; -CHECKREG r2, 0xF537B7E5; -CHECKREG r3, 0x9E060841; -CHECKREG r4, 0x289ECD39; -CHECKREG r5, 0xB0AE3731; -CHECKREG r6, 0xA00C3731; -CHECKREG r7, 0x00007E03; - -imm32 r0, 0xdd235655; -imm32 r1, 0xc4dd5157; -imm32 r2, 0x6324d755; -imm32 r3, 0x00060055; -imm32 r4, 0x90dbc509; -imm32 r5, 0x10adef5b; -imm32 r6, 0xb00cd05d; -imm32 r7, 0x12467d5f; -R0.L = R4.L * R4.H (T); -R1.H = R4.H * R5.L (T); -R2.L = R5.H * R4.L (T); -R3.L = R5.L * R5.L (T); -R4.H = R4.L * R4.H (T); -R5.L = R4.L * R5.H (T); -R6.H = R5.H * R4.H (T); -R7.L = R5.H * R5.H (T); -CHECKREG r0, 0xDD233333; -CHECKREG r1, 0x0E735157; -CHECKREG r2, 0x6324F851; -CHECKREG r3, 0x0006022A; -CHECKREG r4, 0x3333C509; -CHECKREG r5, 0x10ADF851; -CHECKREG r6, 0x06ABD05D; -CHECKREG r7, 0x1246022C; - -imm32 r0, 0xcb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x1c248766; -imm32 r3, 0xf0060066; -imm32 r4, 0x90cb9d69; -imm32 r5, 0x10acef6b; -imm32 r6, 0x800cc06d; -imm32 r7, 0x12467c6f; -// test the unsigned U=1 -R0.L = R6.L * R6.L (T); -R1.H = R6.H * R7.L (T); -R2.L = R7.L * R6.L (T); -R3.L = R7.L * R7.L (T); -R6.L = R6.L * R6.L (T); -R7.L = R6.L * R7.L (T); -R4.L = R7.L * R6.L (T); -R5.L = R7.L * R7.L (T); -CHECKREG r0, 0xCB231F93; -CHECKREG r1, 0x839C5166; -CHECKREG r2, 0x1C24C232; -CHECKREG r3, 0xF00678F7; -CHECKREG r4, 0x90CB0792; -CHECKREG r5, 0x10AC075B; -CHECKREG r6, 0x800C1F93; -CHECKREG r7, 0x12461EB1; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0xe0060007; -imm32 r4, 0x9eabcd09; -imm32 r5, 0x10ecdfdb; -imm32 r6, 0x000e000d; -imm32 r7, 0x1246e00f; -R0.H = R0.L * R7.H (T); -R1.L = R1.H * R6.H (T); -R2.L = R2.L * R5.L (T); -R3.H = R3.H * R4.H (T); -R4.L = R4.L * R3.H (T); -R5.L = R5.H * R2.H (T); -R6.H = R6.H * R1.L (T); -R7.L = R7.L * R0.H (T); -CHECKREG r0, 0xF337A675; -CHECKREG r1, 0xCFBAFFFA; -CHECKREG r2, 0x1324E620; -CHECKREG r3, 0x18500007; -CHECKREG r4, 0x9EABF651; -CHECKREG r5, 0x10EC0287; -CHECKREG r6, 0xFFFF000D; -CHECKREG r7, 0x12460330; - -imm32 r0, 0x9b235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0x93246905; -imm32 r3, 0x09060007; -imm32 r4, 0x909bcd09; -imm32 r5, 0x10a9e9db; -imm32 r6, 0x000c9d0d; -imm32 r7, 0x1246790f; -R0.L = R7.L * R0.H (T); -R1.L = R6.L * R1.L (T); -R2.H = R5.L * R2.L (T); -R3.L = R4.H * R3.L (T); -R4.L = R3.H * R4.H (T); -R5.H = R2.H * R5.L (T); -R6.L = R1.H * R6.L (T); -R7.L = R0.L * R7.L (T); -CHECKREG r0, 0x9B23A09B; -CHECKREG r1, 0xCFBAC144; -CHECKREG r2, 0xEDD46905; -CHECKREG r3, 0x0906FFF9; -CHECKREG r4, 0x909BF825; -CHECKREG r5, 0x0324E9DB; -CHECKREG r6, 0x000C2551; -CHECKREG r7, 0x1246A5C7; - -imm32 r0, 0xa9235675; -imm32 r1, 0xc8ba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x08060007; -imm32 r4, 0x908bcd09; -imm32 r5, 0x10a88fdb; -imm32 r6, 0x000c080d; -imm32 r7, 0x1246708f; -R2.L = R3.L * R6.L (T); -R3.L = R4.H * R7.L (T); -R0.H = R7.L * R0.L, R0.L = R7.H * R0.H (T); -R1.H = R6.L * R1.L (T); -R4.L = R5.H * R2.L (T); -R5.L = R2.L * R3.L (T); -R6.L = R0.L * R4.L (T); -R7.H = R1.H * R5.L (T); -CHECKREG r0, 0x4C06F399; -CHECKREG r1, 0x051A5127; -CHECKREG r2, 0x13240000; -CHECKREG r3, 0x08069DFD; -CHECKREG r4, 0x908B0000; -CHECKREG r5, 0x10A80000; -CHECKREG r6, 0x000C0000; -CHECKREG r7, 0x0000708F; - -imm32 r0, 0x7b235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x17246705; -imm32 r3, 0x00760007; -imm32 r4, 0x907bcd09; -imm32 r5, 0x10a7efdb; -imm32 r6, 0x000c700d; -imm32 r7, 0x1246770f; -R4.L = R5.L * R3.L (T); -R6.L = R6.L * R4.H (T); -R0.H = R7.L * R5.H (T); -R1.L = R0.L * R6.L (T); -R2.L = R1.L * R7.H (T); -R5.L = R2.L * R2.H (T); -R3.H = R3.H * R0.L (T); -R7.L = R4.H * R1.H (T); -CHECKREG r0, 0x0F7D5675; -CHECKREG r1, 0xCFBABE0F; -CHECKREG r2, 0x1724F696; -CHECKREG r3, 0x004F0007; -CHECKREG r4, 0x907BFFFF; -CHECKREG r5, 0x10A7FE4C; -CHECKREG r6, 0x000C9E60; -CHECKREG r7, 0x12462A0E; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_u.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_u.s deleted file mode 100644 index c07b136..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_u.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_m_u/c_dsp32mult_dr_m_u.dsp -// Spec Reference: dsp32mult single dr munop u -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0xfb235625; -imm32 r1, 0x9fba5127; -imm32 r2, 0xa3ff6725; -imm32 r3, 0x0006f027; -imm32 r4, 0xb0abcd29; -imm32 r5, 0x1facef2b; -imm32 r6, 0xc0fc002d; -imm32 r7, 0xd24f702f; -R4.L = R0.H * R0.L (FU); -R5.H = R0.L * R1.L (FU); -R6.L = R1.L * R0.H (FU); -R7.L = R1.L * R1.L (FU); -R0.H = R0.L * R0.L (FU); -R1.L = R0.L * R1.L (FU); -R2.L = R1.H * R0.L (FU); -R3.H = R1.L * R1.L (FU); -CHECKREG r0, 0x1CFD5625; -CHECKREG r1, 0x9FBA1B4F; -CHECKREG r2, 0xA3FF35C0; -CHECKREG r3, 0x02EAF027; -CHECKREG r4, 0xB0AB5482; -CHECKREG r5, 0x1B4FEF2B; -CHECKREG r6, 0xC0FC4F9C; -CHECKREG r7, 0xD24F19BA; - -imm32 r0, 0xbb23a635; -imm32 r1, 0x6bba5137; -imm32 r2, 0x13b4b7e5; -imm32 r3, 0x9e0b0037; -imm32 r4, 0x80ebbd39; -imm32 r5, 0xb0aeef3b; -imm32 r6, 0xa00ceb3d; -imm32 r7, 0x12467eb3; -R4.H = R2.L * R2.L (FU); -R5.L = R2.L * R3.H (FU); -R6.L = R3.H * R2.L (FU); -R7.H = R3.L * R3.L (FU); -R2.H = R2.L * R2.H (FU); -R3.L = R2.H * R3.H (FU); -R0.H = R3.L * R2.L (FU); -R1.L = R3.L * R3.L (FU); -CHECKREG r0, 0x0647A635; -CHECKREG r1, 0x6BBA004C; -CHECKREG r2, 0x0E27B7E5; -CHECKREG r3, 0x9E0B08BD; -CHECKREG r4, 0x8419BD39; -CHECKREG r5, 0xB0AE7187; -CHECKREG r6, 0xA00C7187; -CHECKREG r7, 0x00007EB3; - -imm32 r0, 0xbd235655; -imm32 r1, 0xc4dd5157; -imm32 r2, 0x6b24d755; -imm32 r3, 0x00b60055; -imm32 r4, 0x90dbc509; -imm32 r5, 0x10adbf5b; -imm32 r6, 0xb00cdb5d; -imm32 r7, 0x12467dbf; -R0.L = R4.L * R4.H (FU); -R1.H = R4.H * R5.L (FU); -R2.L = R5.H * R4.L (FU); -R3.L = R5.L * R5.L (FU); -R4.H = R4.L * R4.H (FU); -R5.L = R4.L * R5.H (FU); -R6.H = R5.H * R4.H (FU); -R7.L = R5.H * R5.H (FU); -CHECKREG r0, 0xBD236F7E; -CHECKREG r1, 0x6C475157; -CHECKREG r2, 0x6B240CD6; -CHECKREG r3, 0x00B68F09; -CHECKREG r4, 0x6F7EC509; -CHECKREG r5, 0x10AD0CD6; -CHECKREG r6, 0x0743DB5D; -CHECKREG r7, 0x12460116; - -imm32 r0, 0xcb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x1c248766; -imm32 r3, 0xf0060066; -imm32 r4, 0x90cb9d69; -imm32 r5, 0x10acef6b; -imm32 r6, 0x800cc06d; -imm32 r7, 0x12467c6f; -// test the unsigned U=1 -R0.L = R6.L * R6.L (FU); -R1.H = R6.H * R7.L (FU); -R2.L = R7.L * R6.L (FU); -R3.L = R7.L * R7.L (FU); -R6.L = R6.L * R6.L (FU); -R7.L = R6.L * R7.L (FU); -R4.L = R7.L * R6.L (FU); -R5.L = R7.L * R7.L (FU); -CHECKREG r0, 0xCB2390A4; -CHECKREG r1, 0x3E3D5166; -CHECKREG r2, 0x1C245D88; -CHECKREG r3, 0xF0063C7C; -CHECKREG r4, 0x90CB27B9; -CHECKREG r5, 0x10AC134F; -CHECKREG r6, 0x800C90A4; -CHECKREG r7, 0x1246464E; - -// mix order -imm32 r0, 0x8b23a675; -imm32 r1, 0xc8ba5127; -imm32 r2, 0x13846705; -imm32 r3, 0xe0088807; -imm32 r4, 0x9eabcd09; -imm32 r5, 0x10ecdfdb; -imm32 r6, 0x000e008d; -imm32 r7, 0x1246e008; -R0.H = R0.L * R7.H (FU); -R1.L = R1.H * R6.H (FU); -R2.L = R2.L * R5.L (FU); -R3.H = R3.H * R4.H (FU); -R4.L = R4.L * R3.H (FU); -R5.L = R5.H * R2.H (FU); -R6.H = R6.H * R1.L (FU); -R7.L = R7.L * R0.H (FU); -CHECKREG r0, 0x0BE2A675; -CHECKREG r1, 0xC8BA000B; -CHECKREG r2, 0x13845A15; -CHECKREG r3, 0x8ADB8807; -CHECKREG r4, 0x9EAB6F36; -CHECKREG r5, 0x10EC014A; -CHECKREG r6, 0x0000008D; -CHECKREG r7, 0x12460A66; - -imm32 r0, 0x9b235a75; -imm32 r1, 0x7fba5127; -imm32 r2, 0x97246905; -imm32 r3, 0x09777007; -imm32 r4, 0x909bc779; -imm32 r5, 0x10a9e9d7; -imm32 r6, 0x000c9d0d; -imm32 r7, 0x1246790f; -R0.L = R7.L * R0.H (FU); -R1.L = R6.L * R1.L (FU); -R2.H = R5.L * R2.L (FU); -R3.L = R4.H * R3.L (FU); -R4.L = R3.H * R4.H (FU); -R5.H = R2.H * R5.L (FU); -R6.L = R1.H * R6.L (FU); -R7.L = R0.L * R7.L (FU); -CHECKREG r0, 0x9B23495D; -CHECKREG r1, 0x7FBA31C9; -CHECKREG r2, 0x5FEE6905; -CHECKREG r3, 0x09773F48; -CHECKREG r4, 0x909B0559; -CHECKREG r5, 0x57A0E9D7; -CHECKREG r6, 0x000C4E5C; -CHECKREG r7, 0x124622B1; - -imm32 r0, 0xa9235675; -imm32 r1, 0xc8ba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x08060007; -imm32 r4, 0x908bcd09; -imm32 r5, 0x10a88fdb; -imm32 r6, 0x000c080d; -imm32 r7, 0x1246708f; -R2.L = R0.L * R6.L (FU); -R3.L = R1.H * R7.H (FU); -R0.H = R2.L * R0.L, R0.L = R2.H * R0.L (FU); -R1.H = R3.L * R4.L (FU); -R4.L = R1.H * R2.L (FU); -R5.L = R5.L * R3.L (FU); -R6.L = R6.L * R4.L (FU); -R7.H = R7.H * R5.L (FU); -CHECKREG r0, 0x00EB0677; -CHECKREG r1, 0x0B7A5127; -CHECKREG r2, 0x132402B8; -CHECKREG r3, 0x08060E54; -CHECKREG r4, 0x908B001F; -CHECKREG r5, 0x10A8080D; -CHECKREG r6, 0x000C0001; -CHECKREG r7, 0x0093708F; - -imm32 r0, 0x7b235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x17246705; -imm32 r3, 0x00760007; -imm32 r4, 0x907bcd09; -imm32 r5, 0x10a7efdb; -imm32 r6, 0x000c700d; -imm32 r7, 0x1246770f; -R4.L = R5.L * R2.L (FU); -R6.L = R6.L * R3.H (FU); -R0.H = R7.L * R4.H (FU); -R1.L = R0.H * R5.L (FU); -R2.L = R1.L * R6.L (FU); -R5.L = R2.L * R7.H (FU); -R3.H = R3.H * R0.L (FU); -R7.L = R4.H * R1.H (FU); -CHECKREG r0, 0x43325675; -CHECKREG r1, 0xCFBA3EF5; -CHECKREG r2, 0x1724000D; -CHECKREG r3, 0x00280007; -CHECKREG r4, 0x907B6086; -CHECKREG r5, 0x10A70001; -CHECKREG r6, 0x000C0034; -CHECKREG r7, 0x1246753C; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_mix.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_mix.s deleted file mode 100644 index 794cbfc..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_mix.s +++ /dev/null @@ -1,196 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_mix/c_dsp32mult_dr_mix.dsp -// Spec Reference: dsp32mult single dr (mix) u i t is tu ih -# mach: bfin - -.include "testutils.inc" - start - -// test the default (signed fraction) rounding U=0 I=0 T=0 -imm32 r0, 0xab235615; -imm32 r1, 0xcfba5117; -imm32 r2, 0x13246715; -imm32 r3, 0x00060017; -imm32 r4, 0x90abcd19; -imm32 r5, 0x10acef1b; -imm32 r6, 0x000c001d; -imm32 r7, 0x1246701f; -R2.H = R1.L * R0.L, R2.L = R1.L * R0.L; -R3.L = R1.L * R0.H (ISS2); -R4.H = R1.H * R0.L; -R5.H = R1.L * R0.H (M), R5.L = R1.H * R0.H; -R6.H = R1.H * R0.L, R6.L = R1.L * R0.L; -R7.H = R1.H * R0.H (M), R7.L = R1.H * R0.H; -CHECKREG r2, 0x36893689; -CHECKREG r3, 0x00068000; -CHECKREG r4, 0xDF89CD19; -CHECKREG r5, 0x36352001; -CHECKREG r6, 0xDF893689; -CHECKREG r7, 0xDFBB2001; - -// test the signed integer U=0 I=1 -imm32 r0, 0x8b235625; -imm32 r1, 0x9fba5127; -imm32 r2, 0xa3246725; -imm32 r3, 0x00060027; -imm32 r4, 0xb0abcd29; -imm32 r5, 0x10acef2b; -imm32 r6, 0xc00c002d; -imm32 r7, 0xd246702f; -R2.H = R1.L * R0.L, R2.L = R1.L * R0.L (TFU); -R3.H = R1.L * R0.L, R3.L = R1.L * R0.H (IS); -R4.H = R1.L * R0.L, R4.L = R1.H * R0.L (ISS2); -R5.H = R1.L * R0.L, R5.L = R1.H * R0.H (IS); -R6.H = R1.L * R0.H, R6.L = R1.L * R0.L (IS); -R7.H = R1.L * R0.H, R7.L = R1.L * R0.H (IH); -CHECKREG r0, 0x8B235625; -CHECKREG r1, 0x9FBA5127; -CHECKREG r2, 0x1B4E1B4E; -CHECKREG r3, 0x7FFF8000; -CHECKREG r4, 0x7FFF8000; -CHECKREG r5, 0x7FFF7FFF; -CHECKREG r6, 0x80007FFF; -CHECKREG r7, 0xDAF4DAF4; - -imm32 r0, 0x5b23a635; -imm32 r1, 0x6fba5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x90060037; -imm32 r4, 0x80abcd39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c003d; -imm32 r7, 0x12467003; -R0.H = R3.L * R2.H, R0.L = R3.H * R2.L (IS); -R1.H = R3.L * R2.H, R1.L = R3.H * R2.H (ISS2); -R4.H = R3.H * R2.L, R4.L = R3.L * R2.L (IS); -R5.H = R3.H * R2.L, R5.L = R3.L * R2.H (IS); -R6.H = R3.H * R2.L, R6.L = R3.H * R2.L (IH); -R7.H = R3.H * R2.L, R7.L = R3.H * R2.H (IS); -CHECKREG r0, 0x7FFF7FFF; -CHECKREG r1, 0x7FFF8000; -CHECKREG r2, 0x1324B735; -CHECKREG r3, 0x90060037; -CHECKREG r4, 0x7FFF8000; -CHECKREG r5, 0x7FFF7FFF; -CHECKREG r6, 0x1FD71FD7; -CHECKREG r7, 0x7FFF8000; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x00060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00c005d; -imm32 r7, 0x1246705f; -R0.H = R5.H * R4.H, R0.L = R5.L * R4.L (IS); -R1.H = R5.H * R4.H, R1.L = R5.L * R4.H (ISS2); -R2.H = R5.H * R4.H, R2.L = R5.H * R4.L (IS); -R3.H = R5.H * R4.H, R3.L = R5.H * R4.H (IS); -R4.H = R6.H * R7.L, R4.L = R6.H * R7.L (IH); -R5.H = R6.L * R7.H, R5.L = R6.H * R7.H (IS); -CHECKREG r0, 0x80007FFF; -CHECKREG r1, 0x80007FFF; -CHECKREG r2, 0x80008000; -CHECKREG r3, 0x80008000; -CHECKREG r4, 0xDCE8DCE8; -CHECKREG r5, 0x7FFF8000; -CHECKREG r6, 0xB00C005D; -CHECKREG r7, 0x1246705F; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xf0060066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10acef6b; -imm32 r6, 0x800cb06d; -imm32 r7, 0x1246706f; -// test the unsigned U=1 -R2.H = R1.L * R0.L, R2.L = R1.L * R0.L (FU); -R3.H = R1.L * R0.L, R3.L = R1.L * R0.H (ISS2); -R4.H = R7.L * R6.L, R4.L = R7.H * R6.L (FU); -R5.H = R3.L * R2.L (M), R5.L = R3.H * R2.H (FU); -R6.H = R5.L * R4.H, R6.L = R5.L * R4.L (TFU); -R7.H = R5.L * R4.H, R7.L = R5.L * R4.H (FU); -CHECKREG r0, 0xBB235666; -CHECKREG r1, 0xEFBA5166; -CHECKREG r2, 0x1B791B79; -CHECKREG r3, 0x7FFF8000; -CHECKREG r4, 0x4D7C0C98; -CHECKREG r5, 0xF2440DBC; -CHECKREG r6, 0x042800AC; -CHECKREG r7, 0x04280428; - -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R0.H = R5.L * R4.H, R0.L = R5.H * R4.L (FU); -R1.H = R3.L * R2.H, R1.L = R3.H * R2.H (IU); -R2.H = R7.H * R6.L, R2.L = R7.L * R6.L (TFU); -R3.H = R5.H * R4.L, R3.L = R5.L * R4.H (FU); -R6.H = R1.H * R0.L, R6.L = R1.H * R0.L (IH); -R7.H = R3.H * R2.L, R7.L = R3.H * R2.H (FU); -CHECKREG r0, 0x7E810D5A; -CHECKREG r1, 0x85FC72D8; -CHECKREG r2, 0x0000000C; -CHECKREG r3, 0x0D5A7E81; -CHECKREG r4, 0x90ABCD09; -CHECKREG r5, 0x10ACDFDB; -CHECKREG r6, 0xF9A3F9A3; -CHECKREG r7, 0x00010000; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246905; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R2.H = R1.H * R0.H, R2.L = R1.L * R0.L (TFU); -R3.H = R1.H * R0.L, R3.L = R1.L * R0.H (FU); -R4.H = R6.H * R7.H, R4.L = R6.H * R7.L (ISS2); -R5.H = R6.L * R7.H, R5.L = R6.H * R7.H (FU); -CHECKREG r0, 0xAB235A75; -CHECKREG r1, 0xCFBA5127; -CHECKREG r2, 0x8ADD1CAC; -CHECKREG r3, 0x49663640; -CHECKREG r4, 0x7FFF7FFF; -CHECKREG r5, 0x00EE0001; -CHECKREG r6, 0x000C0D0D; -CHECKREG r7, 0x1246700F; - -// test the ROUNDING only on signed fraction T=1 -imm32 r0, 0xab235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acefdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246700f; -R2.H = R1.L * R0.L (M), R2.L = R1.L * R0.H (IS); -R3.H = R1.H * R0.L (M), R3.L = R1.H * R0.H (FU); -R0.H = R3.L * R2.L (M), R0.L = R3.H * R2.H (T); -R1.H = R5.L * R4.H (M), R1.L = R5.L * R4.L (S2RND); -R4.H = R7.H * R6.H (M), R4.L = R7.L * R6.L (IU); -R5.H = R7.L * R6.H (M), R5.L = R7.H * R6.L (TFU); -R6.H = R5.H * R4.L (M), R6.L = R5.L * R4.H (ISS2); -R7.H = R3.L * R2.H (M), R7.L = R3.L * R2.L (IH); -CHECKREG r0, 0xC56FEFB2; -CHECKREG r1, 0xEDC10CDB; -CHECKREG r2, 0x7FFF8000; -CHECKREG r3, 0xEFB28ADE; -CHECKREG r4, 0x7FFFFFFF; -CHECKREG r5, 0x00050000; -CHECKREG r6, 0x7FFF0000; -CHECKREG r7, 0xC56F3A91; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_s.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_s.s deleted file mode 100644 index 1f3f967..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_s.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_s/c_dsp32mult_dr_s.dsp -// Spec Reference: dsp32mult single dr s -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x98ba5127; -imm32 r2, 0xa3846725; -imm32 r3, 0x00080027; -imm32 r4, 0xb0ab8d29; -imm32 r5, 0x10ace82b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467028; -R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (S2RND); -R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (S2RND); -R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (S2RND); -R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (S2RND); -R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (S2RND); -R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (S2RND); -R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (S2RND); -R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (S2RND); -CHECKREG r0, 0x73F473F4; -CHECKREG r1, 0x7FFF8000; -CHECKREG r2, 0x80007FFF; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x73F473F4; -CHECKREG r5, 0x6D3B8000; -CHECKREG r6, 0x6D3B8000; -CHECKREG r7, 0x66E77FFF; - -imm32 r0, 0x9923a635; -imm32 r1, 0x6f995137; -imm32 r2, 0x1324b735; -imm32 r3, 0x99060037; -imm32 r4, 0x809bcd39; -imm32 r5, 0xb0a99f3b; -imm32 r6, 0xa00c093d; -imm32 r7, 0x12467093; -R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (S2RND); -R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (S2RND); -R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (S2RND); -R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (S2RND); -R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (S2RND); -R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (S2RND); -R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (S2RND); -R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (S2RND); -CHECKREG r0, 0xF416F416; -CHECKREG r1, 0x132C132C; -CHECKREG r2, 0xEA3BEA3B; -CHECKREG r3, 0x23072307; -CHECKREG r4, 0xEA3BEA3B; -CHECKREG r5, 0x7520E134; -CHECKREG r6, 0xFFC10010; -CHECKREG r7, 0xFFA8FFA8; - -imm32 r0, 0x19235655; -imm32 r1, 0xc9ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x0a060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00a005d; -imm32 r7, 0x1246a05f; -R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (S2RND); -R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (S2RND); -R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (S2RND); -R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (S2RND); -R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (S2RND); -R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (S2RND); -R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (S2RND); -R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (S2RND); -CHECKREG r0, 0x66933653; -CHECKREG r1, 0x1CF4F0A4; -CHECKREG r2, 0xF0A4F0A4; -CHECKREG r3, 0x04540458; -CHECKREG r4, 0x66933653; -CHECKREG r5, 0xE553F1DF; -CHECKREG r6, 0xF402E95B; -CHECKREG r7, 0x05E40B1E; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xe0060066; -imm32 r4, 0x9eab9d69; -imm32 r5, 0x10ecef6b; -imm32 r6, 0x800ee06d; -imm32 r7, 0x12467e6f; -// test the unsigned U=1 -R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (S2RND); -R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (S2RND); -R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (S2RND); -R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (S2RND); -R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (S2RND); -R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (S2RND); -R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (S2RND); -R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (S2RND); -CHECKREG r0, 0x7FFF0F94; -CHECKREG r1, 0xDB78F6FC; -CHECKREG r2, 0xDB78F6FC; -CHECKREG r3, 0x05380538; -CHECKREG r4, 0x491708E5; -CHECKREG r5, 0x14DF14DF; -CHECKREG r6, 0x7FFF0F94; -CHECKREG r7, 0x248C0473; - -// mix order -imm32 r0, 0xac23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13c46705; -imm32 r3, 0x00060007; -imm32 r4, 0x90accd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000cc00d; -imm32 r7, 0x1246fc0f; -R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (S2RND); -R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (S2RND); -R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (S2RND); -R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (S2RND); -R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (S2RND); -R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (S2RND); -R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (S2RND); -R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (S2RND); -CHECKREG r0, 0x0584E80E; -CHECKREG r1, 0xAEE9000F; -CHECKREG r2, 0xF613F613; -CHECKREG r3, 0xFFFAFFFA; -CHECKREG r4, 0x00050005; -CHECKREG r5, 0xFD6AFD6A; -CHECKREG r6, 0xFFF1FFF1; -CHECKREG r7, 0xF92A0193; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0xdd246905; -imm32 r3, 0x00d6d007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10aceddb; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (S2RND); -R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (S2RND); -R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (S2RND); -R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (S2RND); -R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (S2RND); -R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (S2RND); -R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (S2RND); -R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (S2RND); -CHECKREG r0, 0xE7C519D4; -CHECKREG r1, 0xFFF7108C; -CHECKREG r2, 0xF6EB1B5B; -CHECKREG r3, 0xFE8C5374; -CHECKREG r4, 0x02870128; -CHECKREG r5, 0xFDA20293; -CHECKREG r6, 0x0000FFFE; -CHECKREG r7, 0x0760F915; - -imm32 r0, 0xfb235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13f46705; -imm32 r3, 0x000f0007; -imm32 r4, 0x90abfd09; -imm32 r5, 0x10acefdb; -imm32 r6, 0x000c00fd; -imm32 r7, 0x1246700f; -R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (S2RND); -R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (S2RND); -R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (S2RND); -R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (S2RND); -R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (S2RND); -R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (S2RND); -R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (S2RND); -R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (S2RND); -CHECKREG r0, 0x0016FFE6; -CHECKREG r1, 0x94D30A65; -CHECKREG r2, 0x01560010; -CHECKREG r3, 0xF238AB7A; -CHECKREG r4, 0xFFFFFDAD; -CHECKREG r5, 0x037AE9FB; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0xD97200FE; - -imm32 r0, 0xab2d5675; -imm32 r1, 0xcfbad127; -imm32 r2, 0x13246d05; -imm32 r3, 0x000600d7; -imm32 r4, 0x908bcd09; -imm32 r5, 0x10a9efdb; -imm32 r6, 0x000c500d; -imm32 r7, 0x1246760f; -R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (S2RND); -R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (S2RND); -R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (S2RND); -R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (S2RND); -R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (S2RND); -R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (S2RND); -R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (S2RND); -R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (S2RND); -CHECKREG r0, 0xF718CD46; -CHECKREG r1, 0xF2CC0CCC; -CHECKREG r2, 0x00020000; -CHECKREG r3, 0xFF56FFE2; -CHECKREG r4, 0xE480FB2C; -CHECKREG r5, 0x00000004; -CHECKREG r6, 0x00000008; -CHECKREG r7, 0xFA8000FF; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_t.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_t.s deleted file mode 100644 index fd2fe02..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_t.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_t/c_dsp32mult_dr_t.dsp -// Spec Reference: dsp32mult single dr t -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x98ba5127; -imm32 r2, 0xa3846725; -imm32 r3, 0x00080027; -imm32 r4, 0xb0ab8d29; -imm32 r5, 0x10ace82b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467028; -R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (T); -R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (T); -R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (T); -R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (T); -R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (T); -R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (T); -R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (T); -R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (T); -CHECKREG r0, 0x39F939F9; -CHECKREG r1, 0x24C1D139; -CHECKREG r2, 0xEAD010A5; -CHECKREG r3, 0x11180A8D; -CHECKREG r4, 0x39F939F9; -CHECKREG r5, 0x369DBA7F; -CHECKREG r6, 0x369DBA7F; -CHECKREG r7, 0x33735352; - -imm32 r0, 0x9923a635; -imm32 r1, 0x6f995137; -imm32 r2, 0x1324b735; -imm32 r3, 0x99060037; -imm32 r4, 0x809bcd39; -imm32 r5, 0xb0a99f3b; -imm32 r6, 0xa00c093d; -imm32 r7, 0x12467093; -R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (T); -R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (T); -R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (T); -R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (T); -R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (T); -R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (T); -R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (T); -R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (T); -CHECKREG r0, 0xFF41FF41; -CHECKREG r1, 0x00990099; -CHECKREG r2, 0xF51DF51D; -CHECKREG r3, 0x08C208C2; -CHECKREG r4, 0xF51DF51D; -CHECKREG r5, 0x3A8FF099; -CHECKREG r6, 0xFFE00008; -CHECKREG r7, 0xFFD3FFD3; - -imm32 r0, 0x19235655; -imm32 r1, 0xc9ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x0a060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00a005d; -imm32 r7, 0x1246a05f; -R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (T); -R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (T); -R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (T); -R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (T); -R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (T); -R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (T); -R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (T); -R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (T); -CHECKREG r0, 0x33491B29; -CHECKREG r1, 0x0E7AF851; -CHECKREG r2, 0xF851F851; -CHECKREG r3, 0x022A022B; -CHECKREG r4, 0x33491B29; -CHECKREG r5, 0xF954FC77; -CHECKREG r6, 0xFF3FFE95; -CHECKREG r7, 0x002F0059; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xe0060066; -imm32 r4, 0x9eab9d69; -imm32 r5, 0x10ecef6b; -imm32 r6, 0x800ee06d; -imm32 r7, 0x12467e6f; -// test the unsigned U=1 -R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (T); -R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (T); -R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (T); -R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (T); -R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (T); -R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (T); -R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (T); -R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (T); -CHECKREG r0, 0x7FE407C9; -CHECKREG r1, 0xEDBBFB7E; -CHECKREG r2, 0xEDBBFB7E; -CHECKREG r3, 0x029B029B; -CHECKREG r4, 0x123E011C; -CHECKREG r5, 0x029A029A; -CHECKREG r6, 0x7FE407C9; -CHECKREG r7, 0x1242011C; - -// mix order -imm32 r0, 0xac23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13c46705; -imm32 r3, 0x00060007; -imm32 r4, 0x90accd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000cc00d; -imm32 r7, 0x1246fc0f; -R0.H = R5.L * R7.L, R0.L = R5.H * R7.H (T); -R1.H = R7.L * R6.L, R1.L = R7.L * R6.H (T); -R2.H = R6.H * R5.H, R2.L = R6.H * R5.L (T); -R3.H = R0.L * R4.L, R3.L = R0.L * R4.L (T); -R4.H = R1.L * R5.H, R4.L = R1.L * R5.L (T); -R5.H = R3.H * R4.L, R5.L = R3.H * R4.L (T); -R6.H = R2.L * R5.L, R6.L = R2.L * R5.L (T); -R7.H = R4.H * R0.L, R7.L = R4.H * R0.H (T); -CHECKREG r0, 0x00FD0261; -CHECKREG r1, 0x01F8FFFF; -CHECKREG r2, 0x0001FFFC; -CHECKREG r3, 0xFF0DFF0D; -CHECKREG r4, 0xFFFF0000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0xFFFFFFFF; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0xdd246905; -imm32 r3, 0x00d6d007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10aceddb; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R4.H = R7.H * R0.H, R4.L = R7.H * R0.L (T); -R5.H = R6.H * R1.H, R5.L = R6.L * R1.L (T); -R6.H = R5.H * R2.H, R6.L = R5.H * R2.L (T); -R7.H = R4.H * R3.H, R7.L = R4.H * R3.L (T); -R0.H = R3.H * R4.H, R0.L = R3.H * R4.L (T); -R2.H = R2.H * R5.H, R2.L = R2.H * R5.L (T); -R1.H = R1.H * R6.H, R1.L = R1.H * R6.L (T); -R3.H = R0.L * R7.H, R3.L = R0.H * R7.H (T); -CHECKREG r0, 0xFFEB0015; -CHECKREG r1, 0xFFFF0001; -CHECKREG r2, 0x0001FDBF; -CHECKREG r3, 0xFFFF0000; -CHECKREG r4, 0xF3E20CE9; -CHECKREG r5, 0xFFFB0846; -CHECKREG r6, 0x0001FFFB; -CHECKREG r7, 0xFFEB048A; - -imm32 r0, 0xfb235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13f46705; -imm32 r3, 0x000f0007; -imm32 r4, 0x90abfd09; -imm32 r5, 0x10acefdb; -imm32 r6, 0x000c00fd; -imm32 r7, 0x1246700f; -R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (T); -R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (T); -R0.H = R2.L * R0.L, R0.L = R2.L * R0.H (T); -R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (T); -R4.H = R4.L * R2.L, R4.L = R4.L * R2.H (T); -R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (T); -R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (T); -R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (T); -CHECKREG r0, 0x0005FFFF; -CHECKREG r1, 0xE5340299; -CHECKREG r2, 0x00AA0008; -CHECKREG r3, 0xF91BD5BD; -CHECKREG r4, 0xFFFFFFFC; -CHECKREG r5, 0x00DEFA7E; -CHECKREG r6, 0xFFFFFFFF; -CHECKREG r7, 0xFB2D001F; - -imm32 r0, 0xab2d5675; -imm32 r1, 0xcfbad127; -imm32 r2, 0x13246d05; -imm32 r3, 0x000600d7; -imm32 r4, 0x908bcd09; -imm32 r5, 0x10a9efdb; -imm32 r6, 0x000c500d; -imm32 r7, 0x1246760f; -R5.H = R5.L * R2.L, R5.L = R5.L * R2.H (T); -R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (T); -R1.H = R7.L * R4.L, R1.L = R7.L * R4.H (T); -R0.H = R1.L * R5.H, R0.L = R1.L * R5.L (T); -R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (T); -R4.H = R2.L * R7.H, R4.L = R2.H * R7.L (T); -R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (T); -R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (T); -CHECKREG r0, 0x0B0B01F1; -CHECKREG r1, 0xD0FE9933; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00030012; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0xF23FFD95; -CHECKREG r6, 0x00000003; -CHECKREG r7, 0x00000000; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_tu.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_tu.s deleted file mode 100644 index 81ad933..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_tu.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_tu/c_dsp32mult_dr_tu.dsp -// Spec Reference: dsp32mult single dr tu -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x98ba5127; -imm32 r2, 0xa3846725; -imm32 r3, 0x00080027; -imm32 r4, 0xb0ab8d29; -imm32 r5, 0x10ace82b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467028; -R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (TFU); -R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (TFU); -R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (TFU); -R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (TFU); -R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (TFU); -R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (TFU); -R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (TFU); -R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (TFU); -CHECKREG r0, 0x1CFC1CFC; -CHECKREG r1, 0x0930114A; -CHECKREG r2, 0x01F5010A; -CHECKREG r3, 0x012A0054; -CHECKREG r4, 0x1CFC1CFC; -CHECKREG r5, 0x1B4E3364; -CHECKREG r6, 0x1B4E3364; -CHECKREG r7, 0x19B95B1D; - -imm32 r0, 0x9923a635; -imm32 r1, 0x6f995137; -imm32 r2, 0x1324b735; -imm32 r3, 0x99060037; -imm32 r4, 0x809bcd39; -imm32 r5, 0xb0a99f3b; -imm32 r6, 0xa00c093d; -imm32 r7, 0x12467093; -R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (TFU); -R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (TFU); -R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (TFU); -R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (TFU); -R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (TFU); -R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (TFU); -R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (TFU); -R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (TFU); -CHECKREG r0, 0x00700070; -CHECKREG r1, 0x00420042; -CHECKREG r2, 0x0DB20DB2; -CHECKREG r3, 0x082F082F; -CHECKREG r4, 0x0DB20DB2; -CHECKREG r5, 0x6D820B70; -CHECKREG r6, 0x00270004; -CHECKREG r7, 0x00200020; - -imm32 r0, 0x19235655; -imm32 r1, 0xc9ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x0a060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00a005d; -imm32 r7, 0x1246a05f; -R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (TFU); -R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (TFU); -R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (TFU); -R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (TFU); -R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (TFU); -R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (TFU); -R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (TFU); -R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (TFU); -CHECKREG r0, 0x6F5897A6; -CHECKREG r1, 0x87430CD4; -CHECKREG r2, 0x0CD40CD4; -CHECKREG r3, 0xDFCB0115; -CHECKREG r4, 0x6F5897A6; -CHECKREG r5, 0x681A8DC9; -CHECKREG r6, 0x53FD3DAA; -CHECKREG r7, 0x39A82A55; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xe0060066; -imm32 r4, 0x9eab9d69; -imm32 r5, 0x10ecef6b; -imm32 r6, 0x800ee06d; -imm32 r7, 0x12467e6f; -// test the unsigned U=1 -R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (TFU); -R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (TFU); -R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (TFU); -R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (TFU); -R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (TFU); -R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (TFU); -R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (TFU); -R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (TFU); -CHECKREG r0, 0x400EC4BE; -CHECKREG r1, 0x09231005; -CHECKREG r2, 0x09231005; -CHECKREG r3, 0x014D014D; -CHECKREG r4, 0x01240383; -CHECKREG r5, 0x00140014; -CHECKREG r6, 0x400EC4BE; -CHECKREG r7, 0x04920E0B; - -// mix order -imm32 r0, 0xac23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13c46705; -imm32 r3, 0x00060007; -imm32 r4, 0x90accd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000cc00d; -imm32 r7, 0x1246fc0f; -R2.H = R0.L * R7.L, R2.L = R0.H * R7.H (TFU); -R5.H = R1.L * R6.L, R5.L = R1.L * R6.H (TFU); -R6.H = R2.H * R5.L, R6.L = R2.H * R5.L (TFU); -R7.H = R3.L * R4.L, R7.L = R3.L * R4.L (TFU); -R0.H = R4.L * R3.L, R0.L = R4.L * R3.L (TFU); -R1.H = R5.H * R2.L, R1.L = R5.H * R2.L (TFU); -R3.H = R6.L * R1.L, R3.L = R6.L * R1.L (TFU); -R4.H = R7.H * R0.L, R4.L = R7.H * R0.H (TFU); -CHECKREG r0, 0x00050005; -CHECKREG r1, 0x02EB02EB; -CHECKREG r2, 0xA3E40C49; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x3CE10003; -CHECKREG r6, 0x00010001; -CHECKREG r7, 0x00050005; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0xdd246905; -imm32 r3, 0x00d6d007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10aceddb; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (TFU); -R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (TFU); -R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (TFU); -R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (TFU); -R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (TFU); -R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (TFU); -R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (TFU); -R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (TFU); -CHECKREG r0, 0x0C370674; -CHECKREG r1, 0x00090423; -CHECKREG r2, 0x0E6606D6; -CHECKREG r3, 0x0078758E; -CHECKREG r4, 0x00430060; -CHECKREG r5, 0x00F00D60; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x007500DF; - -imm32 r0, 0xfb235675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13f46705; -imm32 r3, 0x000f0007; -imm32 r4, 0x90abfd09; -imm32 r5, 0x10acefdb; -imm32 r6, 0x000c00fd; -imm32 r7, 0x1246700f; -R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (TFU); -R3.H = R2.H * R7.H, R3.L = R2.H * R7.L (TFU); -R0.H = R1.L * R0.L, R0.L = R1.H * R0.H (TFU); -R1.H = R3.L * R0.L, R1.L = R3.H * R0.H (TFU); -R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (TFU); -R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (TFU); -R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (TFU); -R7.H = R7.L * R6.L, R7.L = R7.H * R6.H (TFU); -CHECKREG r0, 0x1B68CBC7; -CHECKREG r1, 0x001D0000; -CHECKREG r2, 0x00550004; -CHECKREG r3, 0x00060025; -CHECKREG r4, 0x00030030; -CHECKREG r5, 0x00050002; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0xab2d5675; -imm32 r1, 0xcfbad127; -imm32 r2, 0x13246d05; -imm32 r3, 0x000600d7; -imm32 r4, 0x908bcd09; -imm32 r5, 0x10a9efdb; -imm32 r6, 0x000c500d; -imm32 r7, 0x1246760f; -R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (TFU); -R6.H = R6.H * R3.L, R6.L = R6.H * R3.L (TFU); -R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (TFU); -R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (TFU); -R2.H = R1.L * R6.L, R2.L = R1.H * R6.H (TFU); -R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (TFU); -R3.H = R3.L * R0.L, R3.L = R3.L * R0.L (TFU); -R7.H = R4.H * R1.L, R7.L = R4.H * R1.L (TFU); -CHECKREG r0, 0x08442F1A; -CHECKREG r1, 0x03102C21; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00270027; -CHECKREG r4, 0x662411EE; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x119B119B; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_u.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_u.s deleted file mode 100644 index 47ae1b9..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_dr_u.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_dr_u/c_dsp32mult_dr_u.dsp -// Spec Reference: dsp32mult single dr u -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x98ba5127; -imm32 r2, 0xa3846725; -imm32 r3, 0x00080027; -imm32 r4, 0xb0ab8d29; -imm32 r5, 0x10ace82b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467028; -R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (FU); -R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (FU); -R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (FU); -R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (FU); -R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (FU); -R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (FU); -R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (FU); -R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (FU); -CHECKREG r0, 0x1CFD1CFD; -CHECKREG r1, 0x0930114B; -CHECKREG r2, 0x01F5010A; -CHECKREG r3, 0x012B0054; -CHECKREG r4, 0x1CFD1CFD; -CHECKREG r5, 0x1B4F3365; -CHECKREG r6, 0x1B4F3365; -CHECKREG r7, 0x19BA5B1D; - -imm32 r0, 0x9923a635; -imm32 r1, 0x6f995137; -imm32 r2, 0x1324b735; -imm32 r3, 0x99060037; -imm32 r4, 0x809bcd39; -imm32 r5, 0xb0a99f3b; -imm32 r6, 0xa00c093d; -imm32 r7, 0x12467093; -R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (FU); -R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (FU); -R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (FU); -R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (FU); -R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (FU); -R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (FU); -R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (FU); -R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (FU); -CHECKREG r0, 0x00700070; -CHECKREG r1, 0x00430043; -CHECKREG r2, 0x0DB30DB3; -CHECKREG r3, 0x08300830; -CHECKREG r4, 0x0DB30DB3; -CHECKREG r5, 0x6D830B71; -CHECKREG r6, 0x00270004; -CHECKREG r7, 0x00210021; - -imm32 r0, 0x19235655; -imm32 r1, 0xc9ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x0a060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00a005d; -imm32 r7, 0x1246a05f; -R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (FU); -R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (FU); -R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (FU); -R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (FU); -R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (FU); -R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (FU); -R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (FU); -R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (FU); -CHECKREG r0, 0x6F5997A7; -CHECKREG r1, 0x87430CD5; -CHECKREG r2, 0x0CD50CD5; -CHECKREG r3, 0xDFCB0116; -CHECKREG r4, 0x6F5997A7; -CHECKREG r5, 0x681C8DCB; -CHECKREG r6, 0x53FF3DAC; -CHECKREG r7, 0x39AA2A57; - -imm32 r0, 0xb9235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x19248766; -imm32 r3, 0xe0960066; -imm32 r4, 0x9ea99d69; -imm32 r5, 0x10ec9f6b; -imm32 r6, 0x800e906d; -imm32 r7, 0x12467e6f; -// test the unsigned U=1 -R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (FU); -R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (FU); -R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (FU); -R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (FU); -R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (FU); -R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (FU); -R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (FU); -R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (FU); -CHECKREG r0, 0x400E517B; -CHECKREG r1, 0x09240A4F; -CHECKREG r2, 0x09240A4F; -CHECKREG r3, 0x014E014E; -CHECKREG r4, 0x01250174; -CHECKREG r5, 0x00150015; -CHECKREG r6, 0x400E517B; -CHECKREG r7, 0x049205D1; - -// mix order -imm32 r0, 0x9923a675; -imm32 r1, 0xcf995127; -imm32 r2, 0x13c49705; -imm32 r3, 0x05069007; -imm32 r4, 0x90accd09; -imm32 r5, 0x10ac9fdb; -imm32 r6, 0x000cc90d; -imm32 r7, 0x1246fc9f; -R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (FU); -R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (FU); -R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (FU); -R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (FU); -R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (FU); -R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (FU); -R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (FU); -R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (FU); -CHECKREG r0, 0xA4430AEE; -CHECKREG r1, 0x3FBC0004; -CHECKREG r2, 0x0C580C58; -CHECKREG r3, 0x735B735B; -CHECKREG r4, 0x5C645C64; -CHECKREG r5, 0x00CE00CE; -CHECKREG r6, 0x00030003; -CHECKREG r7, 0x00C80BBA; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0xdd246905; -imm32 r3, 0x00d6d007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10aceddb; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (FU); -R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (FU); -R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (FU); -R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (FU); -R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (FU); -R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (FU); -R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (FU); -R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (FU); -CHECKREG r0, 0x0C370675; -CHECKREG r1, 0x000A0423; -CHECKREG r2, 0x0E6706D7; -CHECKREG r3, 0x0079758F; -CHECKREG r4, 0x00440061; -CHECKREG r5, 0x00F00D62; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x007600DF; - -imm32 r0, 0xee235675; -imm32 r1, 0xcfea5127; -imm32 r2, 0x13fe6705; -imm32 r3, 0x000fe007; -imm32 r4, 0x90abfe09; -imm32 r5, 0x10acefeb; -imm32 r6, 0x000c00fe; -imm32 r7, 0x1246700f; -R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (FU); -R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (FU); -R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (FU); -R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (FU); -R4.H = R4.L * R2.L, R4.L = R4.L * R2.H (FU); -R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (FU); -R6.H = R6.H * R5.L, R6.L = R6.L * R5.H (FU); -R7.H = R7.L * R4.L, R7.L = R7.H * R4.H (FU); -CHECKREG r0, 0x00010050; -CHECKREG r1, 0x1CDA0C0D; -CHECKREG r2, 0x00560004; -CHECKREG r3, 0x0ED75B03; -CHECKREG r4, 0x00040055; -CHECKREG r5, 0x0DE805ED; -CHECKREG r6, 0x0000000E; -CHECKREG r7, 0x00250000; - -imm32 r0, 0xfb2d5675; -imm32 r1, 0xcfbad127; -imm32 r2, 0x13f46d05; -imm32 r3, 0x000f00d7; -imm32 r4, 0x908bfd09; -imm32 r5, 0x10a9efdb; -imm32 r6, 0x000c5f0d; -imm32 r7, 0x124676ff; -R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (FU); -R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (FU); -R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (FU); -R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (FU); -R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (FU); -R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (FU); -R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (FU); -R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (FU); -CHECKREG r0, 0x08B12F7B; -CHECKREG r1, 0x03172C7C; -CHECKREG r2, 0x00010000; -CHECKREG r3, 0x00280007; -CHECKREG r4, 0x662512B2; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x11C0003A; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair.s deleted file mode 100644 index 99d3504..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_pair.s +++ /dev/null @@ -1,179 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_pair/c_dsp32mult_pair.dsp -// Spec Reference: dsp32mult pair -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x93ba5127; -imm32 r2, 0xa3446725; -imm32 r3, 0x00050027; -imm32 r4, 0xb0ab6d29; -imm32 r5, 0x10ace72b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467029; -R1 = R0.L * R0.L, R0 = R0.L * R0.L; -R3 = R0.L * R1.L, R2 = R0.L * R1.H; -R5 = R1.L * R0.L, R4 = R1.H * R0.L; -R7 = R1.L * R1.L, R6 = R1.H * R1.H; -CHECKREG r0, 0x39F9C2B2; -CHECKREG r1, 0x39F9C2B2; -CHECKREG r2, 0xE43C0244; -CHECKREG r3, 0x1D5C8788; -CHECKREG r4, 0xE43C0244; -CHECKREG r5, 0x1D5C8788; -CHECKREG r6, 0x1A41A862; -CHECKREG r7, 0x1D5C8788; - -imm32 r0, 0x5b33a635; -imm32 r1, 0x6fbe5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x9006d037; -imm32 r4, 0x80abcb39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c00dd; -imm32 r7, 0x12469003; -R1 = R2.L * R2.L, R0 = R2.L * R2.L; -R3 = R2.L * R3.L, R2 = R2.L * R3.H; -R5 = R3.L * R2.L, R4 = R3.H * R2.L; -R7 = R3.L * R3.L, R6 = R3.H * R3.H; -CHECKREG r0, 0x2965A1F2; -CHECKREG r1, 0x2965A1F2; -CHECKREG r2, 0x3FAE367C; -CHECKREG r3, 0x1B2CD8C6; -CHECKREG r4, 0x0B90E2A0; -CHECKREG r5, 0xEF4D87D0; -CHECKREG r6, 0x05C49F20; -CHECKREG r7, 0x0C057248; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x00060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00c005d; -imm32 r7, 0x1246705f; -R1 = R4.L * R4.L, R0 = R4.L * R4.L; -R3 = R4.L * R5.L, R2 = R4.L * R5.H; -R5 = R5.L * R4.L, R4 = R5.H * R4.L; -R7 = R5.L * R5.L, R6 = R5.H * R5.H; -CHECKREG r0, 0x1B29B4A2; -CHECKREG r1, 0x1B29B4A2; -CHECKREG r2, 0xF851E418; -CHECKREG r3, 0x07AAE266; -CHECKREG r4, 0xF851E418; -CHECKREG r5, 0x07AAE266; -CHECKREG r6, 0x007579C8; -CHECKREG r7, 0x06D88148; - -imm32 r0, 0xab235666; -imm32 r1, 0xeaba5166; -imm32 r2, 0x13d48766; -imm32 r3, 0xf00b0066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10ac5f6b; -imm32 r6, 0x800cb66d; -imm32 r7, 0x1246707f; -R1 = R6.L * R6.L, R0 = R6.L * R6.L; -R3 = R6.L * R7.L, R2 = R6.L * R7.H; -R5 = R7.L * R6.L, R4 = R7.H * R6.L; -R7 = R7.L * R7.L, R6 = R7.H * R7.H; -CHECKREG r0, 0x2A4A54D2; -CHECKREG r1, 0x2A4A54D2; -CHECKREG r2, 0xF57F179C; -CHECKREG r3, 0xBF566026; -CHECKREG r4, 0xF57F179C; -CHECKREG r5, 0xBF566026; -CHECKREG r6, 0x029BD648; -CHECKREG r7, 0x62DEBE02; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R1 = R3.L * R2.L (M), R0 = R3.L * R2.H; -R3 = R1.L * R0.H, R2 = R1.H * R0.L; -R5 = R7.H * R4.L, R4 = R7.H * R4.L; -R7 = R5.L * R6.L (M), R6 = R5.H * R6.L; -CHECKREG r0, 0x00010BF8; -CHECKREG r1, 0x0002D123; -CHECKREG r2, 0x00002FE0; -CHECKREG r3, 0xFFFFA246; -CHECKREG r4, 0xF8B964EC; -CHECKREG r5, 0xF8B964EC; -CHECKREG r6, 0xFFFF42CA; -CHECKREG r7, 0x00051FFC; - -imm32 r0, 0x9b235a75; -imm32 r1, 0xc9ba5127; -imm32 r2, 0x13946905; -imm32 r3, 0x00090007; -imm32 r4, 0x90ab9d09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d9d; -imm32 r7, 0x12467009; -R3 = R6.L * R5.L, R2 = R6.L * R5.H; -R1 = R3.L * R0.H (M), R0 = R3.H * R0.L; -R5 = R1.L * R4.L (M), R4 = R1.H * R4.L; -R7 = R2.H * R7.L, R6 = R2.H * R7.L; -CHECKREG r0, 0xFE55DCD2; -CHECKREG r1, 0x0C7E7B9A; -CHECKREG r2, 0x01C5EAF8; -CHECKREG r3, 0xFDA5149E; -CHECKREG r4, 0xF6576CDC; -CHECKREG r5, 0x4BD1CA6A; -CHECKREG r6, 0x018C7FDA; -CHECKREG r7, 0x018C7FDA; - -imm32 r0, 0x8b235675; -imm32 r1, 0xc8ba5127; -imm32 r2, 0x13846705; -imm32 r3, 0x00080007; -imm32 r4, 0x90ab8d09; -imm32 r5, 0x10ace8db; -imm32 r6, 0x000c008d; -imm32 r7, 0x12467008; -R3 = R6.H * R5.L, R2 = R6.L * R5.H; -R7 = R2.L * R0.H (M), R6 = R2.H * R0.L; -R5 = R1.L * R3.L (M), R4 = R1.H * R3.L; -R1 = R2.H * R7.L, R0 = R2.L * R7.H; -CHECKREG r0, 0x2517D740; -CHECKREG r1, 0xFFFDAAA0; -CHECKREG r2, 0x00125D78; -CHECKREG r3, 0xFFFDD488; -CHECKREG r4, 0x12C555A0; -CHECKREG r5, 0x435F68B8; -CHECKREG r6, 0x000C2874; -CHECKREG r7, 0x32CCEF68; - -imm32 r0, 0xeb235675; -imm32 r1, 0xceba5127; -imm32 r2, 0x13e46705; -imm32 r3, 0x000e0007; -imm32 r4, 0x90abed09; -imm32 r5, 0x10aceedb; -imm32 r6, 0x000c00ed; -imm32 r7, 0x1246700e; -R1 = R1.H * R4.L, R0 = R1.H * R4.L; -R3 = R2.L * R5.L, R2 = R2.L * R5.H; -R5 = R3.H * R6.L, R4 = R3.L * R6.L; -R7 = R4.L * R0.H, R6 = R4.H * R0.L; -CHECKREG r0, 0x074CED14; -CHECKREG r1, 0x074CED14; -CHECKREG r2, 0x0D6B0EB8; -CHECKREG r3, 0xF2338E8E; -CHECKREG r4, 0xFF2DF2EC; -CHECKREG r5, 0xFFE6726E; -CHECKREG r6, 0x001F3108; -CHECKREG r7, 0xFF412420; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_i.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_i.s deleted file mode 100644 index 2d0d320..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_pair_i.s +++ /dev/null @@ -1,179 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_pair_i/c_dsp32mult_pair_i.dsp -// Spec Reference: dsp32mult pair i -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x93ba5127; -imm32 r2, 0xa3446725; -imm32 r3, 0x00050027; -imm32 r4, 0xb0ab6d29; -imm32 r5, 0x10ace72b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467029; -R1 = R0.L * R0.L, R0 = R0.L * R0.L (IS); -R3 = R0.L * R1.L, R2 = R0.L * R1.H (IS); -R5 = R1.L * R0.L, R4 = R1.H * R0.L (IS); -R7 = R1.L * R1.L, R6 = R1.H * R1.H (IS); -CHECKREG r0, 0x1CFCE159; -CHECKREG r1, 0x1CFCE159; -CHECKREG r2, 0xFC878F9C; -CHECKREG r3, 0x03AB90F1; -CHECKREG r4, 0xFC878F9C; -CHECKREG r5, 0x03AB90F1; -CHECKREG r6, 0x03481810; -CHECKREG r7, 0x03AB90F1; - -imm32 r0, 0x5b33a635; -imm32 r1, 0x6fbe5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x9006d037; -imm32 r4, 0x80abcb39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c00dd; -imm32 r7, 0x12469003; -R1 = R2.L * R2.L, R0 = R2.L * R2.L (IS); -R3 = R2.L * R3.L, R2 = R2.L * R3.H (IS); -R5 = R3.L * R2.L, R4 = R3.H * R2.L (IS); -R7 = R3.L * R3.L, R6 = R3.H * R3.H (IS); -CHECKREG r0, 0x14B2D0F9; -CHECKREG r1, 0x14B2D0F9; -CHECKREG r2, 0x1FD71B3E; -CHECKREG r3, 0x0D966C63; -CHECKREG r4, 0x01721C54; -CHECKREG r5, 0x0B88B0FA; -CHECKREG r6, 0x00B893E4; -CHECKREG r7, 0x2DE3AE49; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x00060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00c005d; -imm32 r7, 0x1246705f; -R1 = R4.L * R4.L, R0 = R4.L * R4.L (IS); -R3 = R4.L * R5.L, R2 = R4.L * R5.H (IS); -R5 = R5.L * R4.L, R4 = R5.H * R4.L (IS); -R7 = R5.L * R5.L, R6 = R5.H * R5.H (IS); -CHECKREG r0, 0x0D94DA51; -CHECKREG r1, 0x0D94DA51; -CHECKREG r2, 0xFC28F20C; -CHECKREG r3, 0x03D57133; -CHECKREG r4, 0xFC28F20C; -CHECKREG r5, 0x03D57133; -CHECKREG r6, 0x000EAF39; -CHECKREG r7, 0x320E1029; - -imm32 r0, 0xab235666; -imm32 r1, 0xeaba5166; -imm32 r2, 0x13d48766; -imm32 r3, 0xf00b0066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10ac5f6b; -imm32 r6, 0x800cb66d; -imm32 r7, 0x1246707f; -R1 = R6.L * R6.L, R0 = R6.L * R6.L (IS); -R3 = R6.L * R7.L, R2 = R6.L * R7.H (IS); -R5 = R7.L * R6.L, R4 = R7.H * R6.L (IS); -R7 = R7.L * R7.L, R6 = R7.H * R7.H (IS); -CHECKREG r0, 0x15252A69; -CHECKREG r1, 0x15252A69; -CHECKREG r2, 0xFABF8BCE; -CHECKREG r3, 0xDFAB3013; -CHECKREG r4, 0xFABF8BCE; -CHECKREG r5, 0xDFAB3013; -CHECKREG r6, 0x014DEB24; -CHECKREG r7, 0x316F5F01; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (IS); -R3 = R1.L * R0.H, R2 = R1.H * R0.L (IS); -R5 = R7.H * R4.L, R4 = R7.H * R4.L (IS); -R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (IS); -CHECKREG r0, 0x000085FC; -CHECKREG r1, 0x0002D123; -CHECKREG r2, 0xFFFF0BF8; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0xFC5CB276; -CHECKREG r5, 0xFC5CB276; -CHECKREG r6, 0xFFFFD0AC; -CHECKREG r7, 0xFFFC0FFE; - -imm32 r0, 0x9b235a75; -imm32 r1, 0xc9ba5127; -imm32 r2, 0x13946905; -imm32 r3, 0x00090007; -imm32 r4, 0x90ab9d09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d9d; -imm32 r7, 0x12467009; -R3 = R6.L * R5.L, R2 = R6.L * R5.H (IS); -R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (IS); -R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (IS); -R7 = R2.H * R7.L, R6 = R2.H * R7.L (IS); -CHECKREG r0, 0xFF9549FA; -CHECKREG r1, 0xB8ADBDCD; -CHECKREG r2, 0x00E2F57C; -CHECKREG r3, 0xFED28A4F; -CHECKREG r4, 0x1B929715; -CHECKREG r5, 0xD7646535; -CHECKREG r6, 0x0062E7F2; -CHECKREG r7, 0x0062E7F2; - -imm32 r0, 0x8b235675; -imm32 r1, 0xc8ba5127; -imm32 r2, 0x13846705; -imm32 r3, 0x00080007; -imm32 r4, 0x90ab8d09; -imm32 r5, 0x10ace8db; -imm32 r6, 0x000c008d; -imm32 r7, 0x12467008; -R3 = R6.H * R5.L, R2 = R6.L * R5.H (IS); -R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (IS); -R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (IS); -R1 = R2.H * R7.L, R0 = R2.L * R7.H (IS); -CHECKREG r0, 0x04A2FAE8; -CHECKREG r1, 0x00043554; -CHECKREG r2, 0x00092EBC; -CHECKREG r3, 0xFFFEEA44; -CHECKREG r4, 0x04B15568; -CHECKREG r5, 0x4A43345C; -CHECKREG r6, 0x00030A1D; -CHECKREG r7, 0x196677B4; - -imm32 r0, 0xeb235675; -imm32 r1, 0xceba5127; -imm32 r2, 0x13e46705; -imm32 r3, 0x000e0007; -imm32 r4, 0x90abed09; -imm32 r5, 0x10aceedb; -imm32 r6, 0x000c00ed; -imm32 r7, 0x1246700e; -R1 = R1.H * R4.L, R0 = R1.H * R4.L (IS); -R3 = R2.L * R5.L, R2 = R2.L * R5.H (IS); -R5 = R3.H * R6.L, R4 = R3.L * R6.L (IS); -R7 = R4.L * R0.H, R6 = R4.H * R0.L (IS); -CHECKREG r0, 0x03A6768A; -CHECKREG r1, 0x03A6768A; -CHECKREG r2, 0x06B5875C; -CHECKREG r3, 0xF919C747; -CHECKREG r4, 0xFFCB7CBB; -CHECKREG r5, 0xFFF99C25; -CHECKREG r6, 0xFFE7756E; -CHECKREG r7, 0x01C71242; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_is.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_is.s deleted file mode 100644 index d4a7d88..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_pair_is.s +++ /dev/null @@ -1,179 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_pair_is/c_dsp32mult_pair_is.dsp -// Spec Reference: dsp32mult pair is -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x93ba5127; -imm32 r2, 0xa3446725; -imm32 r3, 0x00050027; -imm32 r4, 0xb0ab6d29; -imm32 r5, 0x10ace72b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467029; -R1 = R0.L * R0.L, R0 = R0.L * R0.L (ISS2); -R3 = R0.L * R1.L, R2 = R0.L * R1.H (ISS2); -R5 = R1.L * R0.L, R4 = R1.H * R0.L (ISS2); -R7 = R1.L * R1.L, R6 = R1.H * R1.H (ISS2); -CHECKREG r0, 0x39F9C2B2; -CHECKREG r1, 0x39F9C2B2; -CHECKREG r2, 0xE43C0244; -CHECKREG r3, 0x1D5C8788; -CHECKREG r4, 0xE43C0244; -CHECKREG r5, 0x1D5C8788; -CHECKREG r6, 0x1A41A862; -CHECKREG r7, 0x1D5C8788; - -imm32 r0, 0x5b33a635; -imm32 r1, 0x6fbe5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x9006d037; -imm32 r4, 0x80abcb39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c00dd; -imm32 r7, 0x12469003; -R1 = R2.L * R2.L, R0 = R2.L * R2.L (ISS2); -R3 = R2.L * R3.L, R2 = R2.L * R3.H (ISS2); -R5 = R3.L * R2.L, R4 = R3.H * R2.L (ISS2); -R7 = R3.L * R3.L, R6 = R3.H * R3.H (ISS2); -CHECKREG r0, 0x2965A1F2; -CHECKREG r1, 0x2965A1F2; -CHECKREG r2, 0x3FAE367C; -CHECKREG r3, 0x1B2CD8C6; -CHECKREG r4, 0x0B90E2A0; -CHECKREG r5, 0xEF4D87D0; -CHECKREG r6, 0x05C49F20; -CHECKREG r7, 0x0C057248; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x00060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00c005d; -imm32 r7, 0x1246705f; -R1 = R4.L * R4.L, R0 = R4.L * R4.L (ISS2); -R3 = R4.L * R5.L, R2 = R4.L * R5.H (ISS2); -R5 = R5.L * R4.L, R4 = R5.H * R4.L (ISS2); -R7 = R5.L * R5.L, R6 = R5.H * R5.H (ISS2); -CHECKREG r0, 0x1B29B4A2; -CHECKREG r1, 0x1B29B4A2; -CHECKREG r2, 0xF851E418; -CHECKREG r3, 0x07AAE266; -CHECKREG r4, 0xF851E418; -CHECKREG r5, 0x07AAE266; -CHECKREG r6, 0x007579C8; -CHECKREG r7, 0x06D88148; - -imm32 r0, 0xab235666; -imm32 r1, 0xeaba5166; -imm32 r2, 0x13d48766; -imm32 r3, 0xf00b0066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10ac5f6b; -imm32 r6, 0x800cb66d; -imm32 r7, 0x1246707f; -R1 = R6.L * R6.L, R0 = R6.L * R6.L (ISS2); -R3 = R6.L * R7.L, R2 = R6.L * R7.H (ISS2); -R5 = R7.L * R6.L, R4 = R7.H * R6.L (ISS2); -R7 = R7.L * R7.L, R6 = R7.H * R7.H (ISS2); -CHECKREG r0, 0x2A4A54D2; -CHECKREG r1, 0x2A4A54D2; -CHECKREG r2, 0xF57F179C; -CHECKREG r3, 0xBF566026; -CHECKREG r4, 0xF57F179C; -CHECKREG r5, 0xBF566026; -CHECKREG r6, 0x029BD648; -CHECKREG r7, 0x62DEBE02; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (ISS2); -R3 = R1.L * R0.H, R2 = R1.H * R0.L (ISS2); -R5 = R7.H * R4.L, R4 = R7.H * R4.L (ISS2); -R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (ISS2); -CHECKREG r0, 0x00010BF8; -CHECKREG r1, 0x0005A246; -CHECKREG r2, 0x000077B0; -CHECKREG r3, 0xFFFF448C; -CHECKREG r4, 0xF8B964EC; -CHECKREG r5, 0xF8B964EC; -CHECKREG r6, 0xFFFF42CA; -CHECKREG r7, 0x000A3FF8; - -imm32 r0, 0x9b235a75; -imm32 r1, 0xc9ba5127; -imm32 r2, 0x13946905; -imm32 r3, 0x00090007; -imm32 r4, 0x90ab9d09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d9d; -imm32 r7, 0x12467009; -R3 = R6.L * R5.L, R2 = R6.L * R5.H (ISS2); -R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (ISS2); -R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (ISS2); -R7 = R2.H * R7.L, R6 = R2.H * R7.L (ISS2); -CHECKREG r0, 0xFE55DCD2; -CHECKREG r1, 0x18FCF734; -CHECKREG r2, 0x01C5EAF8; -CHECKREG r3, 0xFDA5149E; -CHECKREG r4, 0xECAED9B8; -CHECKREG r5, 0xF53529A8; -CHECKREG r6, 0x018C7FDA; -CHECKREG r7, 0x018C7FDA; - -imm32 r0, 0x8b235675; -imm32 r1, 0xc8ba5127; -imm32 r2, 0x13846705; -imm32 r3, 0x00080007; -imm32 r4, 0x90ab8d09; -imm32 r5, 0x10ace8db; -imm32 r6, 0x000c008d; -imm32 r7, 0x12467008; -R3 = R6.H * R5.L, R2 = R6.L * R5.H (ISS2); -R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (ISS2); -R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (ISS2); -R1 = R2.H * R7.L, R0 = R2.L * R7.H (ISS2); -CHECKREG r0, 0x4A306970; -CHECKREG r1, 0xFFFB5540; -CHECKREG r2, 0x00125D78; -CHECKREG r3, 0xFFFDD488; -CHECKREG r4, 0x12C555A0; -CHECKREG r5, 0x7FFFFFFF; -CHECKREG r6, 0x000C2874; -CHECKREG r7, 0x6599DED0; - -imm32 r0, 0xeb235675; -imm32 r1, 0xceba5127; -imm32 r2, 0x13e46705; -imm32 r3, 0x000e0007; -imm32 r4, 0x90abed09; -imm32 r5, 0x10aceedb; -imm32 r6, 0x000c00ed; -imm32 r7, 0x1246700e; -R1 = R1.H * R4.L, R0 = R1.H * R4.L (ISS2); -R3 = R2.L * R5.L, R2 = R2.L * R5.H (ISS2); -R5 = R3.H * R6.L, R4 = R3.L * R6.L (ISS2); -R7 = R4.L * R0.H, R6 = R4.H * R0.L (ISS2); -CHECKREG r0, 0x074CED14; -CHECKREG r1, 0x074CED14; -CHECKREG r2, 0x0D6B0EB8; -CHECKREG r3, 0xF2338E8E; -CHECKREG r4, 0xFF2DF2EC; -CHECKREG r5, 0xFFE6726E; -CHECKREG r6, 0x001F3108; -CHECKREG r7, 0xFF412420; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m.s deleted file mode 100644 index 73ab875..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m.s +++ /dev/null @@ -1,178 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_pair_m/c_dsp32mult_pair_m.dsp -// Spec Reference: dsp32mult pair MUNOP -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x34235625; -imm32 r1, 0x9f7a5127; -imm32 r2, 0xa3286725; -imm32 r3, 0x00069027; -imm32 r4, 0xb0abc029; -imm32 r5, 0x10acef2b; -imm32 r6, 0xc00c00de; -imm32 r7, 0xd246712f; -R0 = R0.L * R0.L; -R2 = R0.L * R1.H; -R4 = R1.H * R1.H; -R6 = R0.L * R0.L; -CHECKREG r0, 0x39F9C2B2; -CHECKREG r1, 0x9F7A5127; -CHECKREG r2, 0x2E3AADA8; -CHECKREG r3, 0x00069027; -CHECKREG r4, 0x48C98C48; -CHECKREG r5, 0x10ACEF2B; -CHECKREG r6, 0x1D5C8788; -CHECKREG r7, 0xD246712F; - -imm32 r0, 0x5b23a635; -imm32 r1, 0x6fba5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x90060037; -imm32 r4, 0x80abcd39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c003d; -imm32 r7, 0x12467003; -R0 = R2.L * R2.L; -R2 = R2.L * R3.H; -R4 = R3.H * R2.H; -R6 = R2.L * R3.L; -CHECKREG r0, 0x2965A1F2; -CHECKREG r1, 0x6FBA5137; -CHECKREG r2, 0x3FAE367C; -CHECKREG r3, 0x90060037; -CHECKREG r4, 0xC84ABC28; -CHECKREG r5, 0xB0ACEF3B; -CHECKREG r6, 0x00176948; -CHECKREG r7, 0x12467003; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x43246755; -imm32 r3, 0x05060055; -imm32 r4, 0x906bc509; -imm32 r5, 0x10a7ef5b; -imm32 r6, 0xb00c805d; -imm32 r7, 0x1246795f; -R0 = R4.L * R4.L; -R2 = R4.L * R5.H; -R4 = R5.H * R5.H; -R6 = R4.L * R5.L; -CHECKREG r0, 0x1B29B4A2; -CHECKREG r1, 0xC4BA5157; -CHECKREG r2, 0xF85431BE; -CHECKREG r3, 0x05060055; -CHECKREG r4, 0x022A99E2; -CHECKREG r5, 0x10A7EF5B; -CHECKREG r6, 0x0D4762AC; -CHECKREG r7, 0x1246795F; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xf0060066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10acef6b; -imm32 r6, 0x800cb06d; -imm32 r7, 0x1246706f; -R0 = R6.L * R6.L; -R2 = R6.L * R7.H; -R4 = R7.H * R7.H; -R6 = R6.L * R7.L; -CHECKREG r0, 0x31781CD2; -CHECKREG r1, 0xEFBA5166; -CHECKREG r2, 0xF4A3CF9C; -CHECKREG r3, 0xF0060066; -CHECKREG r4, 0x029BD648; -CHECKREG r5, 0x10ACEF6B; -CHECKREG r6, 0xBA1A5E86; -CHECKREG r7, 0x1246706F; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R0 = R0.L * R7.L; -R2 = R1.L * R6.H; -R4 = R3.H * R4.H; -R6 = R4.L * R3.L; -CHECKREG r0, 0x0B26E1B6; -CHECKREG r1, 0xCFBA5127; -CHECKREG r2, 0x00079BA8; -CHECKREG r3, 0x00060007; -CHECKREG r4, 0xFFFAC804; -CHECKREG r5, 0x10ACDFDB; -CHECKREG r6, 0xFFFCF038; -CHECKREG r7, 0x1246F00F; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246905; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R1 = R7.H * R0.H; -R3 = R6.H * R1.H; -R5 = R5.H * R2.L; -R7 = R4.L * R3.H; -CHECKREG r0, 0xAB235A75; -CHECKREG r1, 0xF3E28324; -CHECKREG r2, 0x13246905; -CHECKREG r3, 0xFFFEDD30; -CHECKREG r4, 0x90ABCD09; -CHECKREG r5, 0x0DADBEB8; -CHECKREG r6, 0x000C0D0D; -CHECKREG r7, 0x0000CBDC; - -imm32 r0, 0x9b235675; -imm32 r1, 0xc9ba5127; -imm32 r2, 0x13946705; -imm32 r3, 0x00090007; -imm32 r4, 0x90ab9d09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c009d; -imm32 r7, 0x12467009; -R1 = R6.H * R4.L; -R3 = R5.L * R3.H; -R5 = R3.H * R1.L; -R7 = R1.H * R2.H; -CHECKREG r0, 0x9B235675; -CHECKREG r1, 0xFFF6B8D8; -CHECKREG r2, 0x13946705; -CHECKREG r3, 0xFFFE7166; -CHECKREG r4, 0x90AB9D09; -CHECKREG r5, 0x00011CA0; -CHECKREG r6, 0x000C009D; -CHECKREG r7, 0xFFFE7870; - -imm32 r0, 0xeb235675; -imm32 r1, 0xceba5127; -imm32 r2, 0x13e46705; -imm32 r3, 0x000e0007; -imm32 r4, 0x90abed09; -imm32 r5, 0x10aceedb; -imm32 r6, 0x000c00ed; -imm32 r7, 0x1246700e; -R1 = R4.L * R0.H; -R3 = R6.H * R1.H; -R5 = R1.L * R2.L; -R7 = R4.H * R2.L; -CHECKREG r0, 0xEB235675; -CHECKREG r1, 0x03175676; -CHECKREG r2, 0x13E46705; -CHECKREG r3, 0x00004A28; -CHECKREG r4, 0x90ABED09; -CHECKREG r5, 0x4596549C; -CHECKREG r6, 0x000C00ED; -CHECKREG r7, 0xA66540AE; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_i.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_i.s deleted file mode 100644 index b865be0..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_i.s +++ /dev/null @@ -1,178 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_pair_m_i/c_dsp32mult_pair_m_i.dsp -// Spec Reference: dsp32mult pair MUNOP i -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x34235625; -imm32 r1, 0x9f7a5127; -imm32 r2, 0xa3286725; -imm32 r3, 0x00069027; -imm32 r4, 0xb0abc029; -imm32 r5, 0x10acef2b; -imm32 r6, 0xc00c00de; -imm32 r7, 0xd246712f; -R0 = R0.L * R0.L (IS); -R2 = R0.L * R1.H (IS); -R4 = R1.H * R1.H (IS); -R6 = R0.L * R0.L (IS); -CHECKREG r0, 0x1CFCE159; -CHECKREG r1, 0x9F7A5127; -CHECKREG r2, 0x0B8EAB6A; -CHECKREG r3, 0x00069027; -CHECKREG r4, 0x2464C624; -CHECKREG r5, 0x10ACEF2B; -CHECKREG r6, 0x03AB90F1; -CHECKREG r7, 0xD246712F; - -imm32 r0, 0x5b23a635; -imm32 r1, 0x6fba5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x90060037; -imm32 r4, 0x80abcd39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c003d; -imm32 r7, 0x12467003; -R0 = R2.L * R2.L (IS); -R2 = R2.L * R3.H (IS); -R4 = R3.H * R2.H (IS); -R6 = R2.L * R3.L (IS); -CHECKREG r0, 0x14B2D0F9; -CHECKREG r1, 0x6FBA5137; -CHECKREG r2, 0x1FD71B3E; -CHECKREG r3, 0x90060037; -CHECKREG r4, 0xF212AF0A; -CHECKREG r5, 0xB0ACEF3B; -CHECKREG r6, 0x0005DA52; -CHECKREG r7, 0x12467003; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x43246755; -imm32 r3, 0x05060055; -imm32 r4, 0x906bc509; -imm32 r5, 0x10a7ef5b; -imm32 r6, 0xb00c805d; -imm32 r7, 0x1246795f; -R0 = R4.L * R4.L (IS); -R2 = R4.L * R5.H (IS); -R4 = R5.H * R5.H (IS); -R6 = R4.L * R5.L (IS); -CHECKREG r0, 0x0D94DA51; -CHECKREG r1, 0xC4BA5157; -CHECKREG r2, 0xFC2A18DF; -CHECKREG r3, 0x05060055; -CHECKREG r4, 0x01154CF1; -CHECKREG r5, 0x10A7EF5B; -CHECKREG r6, 0xFAFF58AB; -CHECKREG r7, 0x1246795F; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xf0060066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10acef6b; -imm32 r6, 0x800cb06d; -imm32 r7, 0x1246706f; -R0 = R6.L * R6.L (IS); -R2 = R6.L * R7.H (IS); -R4 = R7.H * R7.H (IS); -R6 = R6.L * R7.L (IS); -CHECKREG r0, 0x18BC0E69; -CHECKREG r1, 0xEFBA5166; -CHECKREG r2, 0xFA51E7CE; -CHECKREG r3, 0xF0060066; -CHECKREG r4, 0x014DEB24; -CHECKREG r5, 0x10ACEF6B; -CHECKREG r6, 0xDD0D2F43; -CHECKREG r7, 0x1246706F; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R0 = R0.L * R7.L (IS); -R2 = R1.L * R6.H (IS); -R4 = R3.H * R4.H (IS); -R6 = R4.L * R3.L (IS); -CHECKREG r0, 0x059370DB; -CHECKREG r1, 0xCFBA5127; -CHECKREG r2, 0x0003CDD4; -CHECKREG r3, 0x00060007; -CHECKREG r4, 0xFFFD6402; -CHECKREG r5, 0x10ACDFDB; -CHECKREG r6, 0x0002BC0E; -CHECKREG r7, 0x1246F00F; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246905; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R1 = R7.H * R0.H (IS); -R3 = R6.H * R1.H (IS); -R5 = R5.H * R2.L (IS); -R7 = R4.L * R3.H (IS); -CHECKREG r0, 0xAB235A75; -CHECKREG r1, 0xF9F14192; -CHECKREG r2, 0x13246905; -CHECKREG r3, 0xFFFFB74C; -CHECKREG r4, 0x90ABCD09; -CHECKREG r5, 0x06D6DF5C; -CHECKREG r6, 0x000C0D0D; -CHECKREG r7, 0x000032F7; - -imm32 r0, 0x9b235675; -imm32 r1, 0xc9ba5127; -imm32 r2, 0x13946705; -imm32 r3, 0x00090007; -imm32 r4, 0x90ab9d09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c009d; -imm32 r7, 0x12467009; -R1 = R6.H * R4.L (IS); -R3 = R5.L * R3.H (IS); -R5 = R3.H * R1.L (IS); -R7 = R1.H * R2.H (IS); -CHECKREG r0, 0x9B235675; -CHECKREG r1, 0xFFFB5C6C; -CHECKREG r2, 0x13946705; -CHECKREG r3, 0xFFFF38B3; -CHECKREG r4, 0x90AB9D09; -CHECKREG r5, 0xFFFFA394; -CHECKREG r6, 0x000C009D; -CHECKREG r7, 0xFFFF9E1C; - -imm32 r0, 0xeb235675; -imm32 r1, 0xceba5127; -imm32 r2, 0x13e46705; -imm32 r3, 0x000e0007; -imm32 r4, 0x90abed09; -imm32 r5, 0x10aceedb; -imm32 r6, 0x000c00ed; -imm32 r7, 0x1246700e; -R1 = R4.L * R0.H (IS); -R3 = R6.H * R1.H (IS); -R5 = R1.L * R2.L (IS); -R7 = R4.H * R2.L (IS); -CHECKREG r0, 0xEB235675; -CHECKREG r1, 0x018BAB3B; -CHECKREG r2, 0x13E46705; -CHECKREG r3, 0x00001284; -CHECKREG r4, 0x90ABED09; -CHECKREG r5, 0xDDE31527; -CHECKREG r6, 0x000C00ED; -CHECKREG r7, 0xD332A057; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_is.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_is.s deleted file mode 100644 index 073b7f3..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_is.s +++ /dev/null @@ -1,178 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_pair_m_is/c_dsp32mult_pair_m_is.dsp -// Spec Reference: dsp32mult pair MUNOP is -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x34235625; -imm32 r1, 0x9f7a5127; -imm32 r2, 0xa3286725; -imm32 r3, 0x00069027; -imm32 r4, 0xb0abc029; -imm32 r5, 0x10acef2b; -imm32 r6, 0xc00c00de; -imm32 r7, 0xd246712f; -R0 = R0.L * R0.L (ISS2); -R2 = R0.L * R1.H (ISS2); -R4 = R1.H * R1.H (ISS2); -R6 = R0.L * R0.L (ISS2); -CHECKREG r0, 0x39F9C2B2; -CHECKREG r1, 0x9F7A5127; -CHECKREG r2, 0x2E3AADA8; -CHECKREG r3, 0x00069027; -CHECKREG r4, 0x48C98C48; -CHECKREG r5, 0x10ACEF2B; -CHECKREG r6, 0x1D5C8788; -CHECKREG r7, 0xD246712F; - -imm32 r0, 0x5b23a635; -imm32 r1, 0x6fba5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x90060037; -imm32 r4, 0x80abcd39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c003d; -imm32 r7, 0x12467003; -R0 = R2.L * R2.L (ISS2); -R2 = R2.L * R3.H (ISS2); -R4 = R3.H * R2.H (ISS2); -R6 = R2.L * R3.L (ISS2); -CHECKREG r0, 0x2965A1F2; -CHECKREG r1, 0x6FBA5137; -CHECKREG r2, 0x3FAE367C; -CHECKREG r3, 0x90060037; -CHECKREG r4, 0xC84ABC28; -CHECKREG r5, 0xB0ACEF3B; -CHECKREG r6, 0x00176948; -CHECKREG r7, 0x12467003; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x43246755; -imm32 r3, 0x05060055; -imm32 r4, 0x906bc509; -imm32 r5, 0x10a7ef5b; -imm32 r6, 0xb00c805d; -imm32 r7, 0x1246795f; -R0 = R4.L * R4.L (ISS2); -R2 = R4.L * R5.H (ISS2); -R4 = R5.H * R5.H (ISS2); -R6 = R4.L * R5.L (ISS2); -CHECKREG r0, 0x1B29B4A2; -CHECKREG r1, 0xC4BA5157; -CHECKREG r2, 0xF85431BE; -CHECKREG r3, 0x05060055; -CHECKREG r4, 0x022A99E2; -CHECKREG r5, 0x10A7EF5B; -CHECKREG r6, 0x0D4762AC; -CHECKREG r7, 0x1246795F; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xf0060066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10acef6b; -imm32 r6, 0x800cb06d; -imm32 r7, 0x1246706f; -R0 = R6.L * R6.L (ISS2); -R2 = R6.L * R7.H (ISS2); -R4 = R7.H * R7.H (ISS2); -R6 = R6.L * R7.L (ISS2); -CHECKREG r0, 0x31781CD2; -CHECKREG r1, 0xEFBA5166; -CHECKREG r2, 0xF4A3CF9C; -CHECKREG r3, 0xF0060066; -CHECKREG r4, 0x029BD648; -CHECKREG r5, 0x10ACEF6B; -CHECKREG r6, 0xBA1A5E86; -CHECKREG r7, 0x1246706F; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R0 = R0.L * R7.L (ISS2); -R2 = R1.L * R6.H (ISS2); -R4 = R3.H * R4.H (ISS2); -R6 = R4.L * R3.L (ISS2); -CHECKREG r0, 0x0B26E1B6; -CHECKREG r1, 0xCFBA5127; -CHECKREG r2, 0x00079BA8; -CHECKREG r3, 0x00060007; -CHECKREG r4, 0xFFFAC804; -CHECKREG r5, 0x10ACDFDB; -CHECKREG r6, 0xFFFCF038; -CHECKREG r7, 0x1246F00F; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246905; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R1 = R7.H * R0.H (ISS2); -R3 = R6.H * R1.H (ISS2); -R5 = R5.H * R2.L (ISS2); -R7 = R4.L * R3.H (ISS2); -CHECKREG r0, 0xAB235A75; -CHECKREG r1, 0xF3E28324; -CHECKREG r2, 0x13246905; -CHECKREG r3, 0xFFFEDD30; -CHECKREG r4, 0x90ABCD09; -CHECKREG r5, 0x0DADBEB8; -CHECKREG r6, 0x000C0D0D; -CHECKREG r7, 0x0000CBDC; - -imm32 r0, 0x9b235675; -imm32 r1, 0xc9ba5127; -imm32 r2, 0x13946705; -imm32 r3, 0x00090007; -imm32 r4, 0x90ab9d09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c009d; -imm32 r7, 0x12467009; -R1 = R6.H * R4.L (ISS2); -R3 = R5.L * R3.H (ISS2); -R5 = R3.H * R1.L (ISS2); -R7 = R1.H * R2.H (ISS2); -CHECKREG r0, 0x9B235675; -CHECKREG r1, 0xFFF6B8D8; -CHECKREG r2, 0x13946705; -CHECKREG r3, 0xFFFE7166; -CHECKREG r4, 0x90AB9D09; -CHECKREG r5, 0x00011CA0; -CHECKREG r6, 0x000C009D; -CHECKREG r7, 0xFFFE7870; - -imm32 r0, 0xeb235675; -imm32 r1, 0xceba5127; -imm32 r2, 0x13e46705; -imm32 r3, 0x000e0007; -imm32 r4, 0x90abed09; -imm32 r5, 0x10aceedb; -imm32 r6, 0x000c00ed; -imm32 r7, 0x1246700e; -R1 = R4.L * R0.H (ISS2); -R3 = R6.H * R1.H (ISS2); -R5 = R1.L * R2.L (ISS2); -R7 = R4.H * R2.L (ISS2); -CHECKREG r0, 0xEB235675; -CHECKREG r1, 0x03175676; -CHECKREG r2, 0x13E46705; -CHECKREG r3, 0x00004A28; -CHECKREG r4, 0x90ABED09; -CHECKREG r5, 0x4596549C; -CHECKREG r6, 0x000C00ED; -CHECKREG r7, 0xA66540AE; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_s.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_s.s deleted file mode 100644 index 71b95eb..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_s.s +++ /dev/null @@ -1,178 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_pair_m_s/c_dsp32mult_pair_m_s.dsp -// Spec Reference: dsp32mult pair MUNOP s -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x34235625; -imm32 r1, 0x9f7a5127; -imm32 r2, 0xa3286725; -imm32 r3, 0x00069027; -imm32 r4, 0xb0abc029; -imm32 r5, 0x10acef2b; -imm32 r6, 0xc00c00de; -imm32 r7, 0xd246712f; -R0 = R0.L * R0.L (S2RND); -R2 = R0.L * R1.H (S2RND); -R4 = R1.H * R1.H (S2RND); -R6 = R0.L * R0.L (S2RND); -CHECKREG r0, 0x73F38564; -CHECKREG r1, 0x9F7A5127; -CHECKREG r2, 0x7FFFFFFF; -CHECKREG r3, 0x00069027; -CHECKREG r4, 0x7FFFFFFF; -CHECKREG r5, 0x10ACEF2B; -CHECKREG r6, 0x7FFFFFFF; -CHECKREG r7, 0xD246712F; - -imm32 r0, 0x5b23a635; -imm32 r1, 0x6fba5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x90060037; -imm32 r4, 0x80abcd39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c003d; -imm32 r7, 0x12467003; -R0 = R2.L * R2.L (S2RND); -R2 = R2.L * R3.H (S2RND); -R4 = R3.H * R2.H (S2RND); -R6 = R2.L * R3.L (S2RND); -CHECKREG r0, 0x52CB43E4; -CHECKREG r1, 0x6FBA5137; -CHECKREG r2, 0x7F5C6CF8; -CHECKREG r3, 0x90060037; -CHECKREG r4, 0x80000000; -CHECKREG r5, 0xB0ACEF3B; -CHECKREG r6, 0x005DA520; -CHECKREG r7, 0x12467003; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x43246755; -imm32 r3, 0x05060055; -imm32 r4, 0x906bc509; -imm32 r5, 0x10a7ef5b; -imm32 r6, 0xb00c805d; -imm32 r7, 0x1246795f; -R0 = R4.L * R4.L (S2RND); -R2 = R4.L * R5.H (S2RND); -R4 = R5.H * R5.H (S2RND); -R6 = R4.L * R5.L (S2RND); -CHECKREG r0, 0x36536944; -CHECKREG r1, 0xC4BA5157; -CHECKREG r2, 0xF0A8637C; -CHECKREG r3, 0x05060055; -CHECKREG r4, 0x045533C4; -CHECKREG r5, 0x10A7EF5B; -CHECKREG r6, 0xF2898AB0; -CHECKREG r7, 0x1246795F; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xf0060066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10acef6b; -imm32 r6, 0x800cb06d; -imm32 r7, 0x1246706f; -R0 = R6.L * R6.L (S2RND); -R2 = R6.L * R7.H (S2RND); -R4 = R7.H * R7.H (S2RND); -R6 = R6.L * R7.L (S2RND); -CHECKREG r0, 0x62F039A4; -CHECKREG r1, 0xEFBA5166; -CHECKREG r2, 0xE9479F38; -CHECKREG r3, 0xF0060066; -CHECKREG r4, 0x0537AC90; -CHECKREG r5, 0x10ACEF6B; -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x1246706F; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R0 = R0.L * R7.L (S2RND); -R2 = R1.L * R6.H (S2RND); -R4 = R3.H * R4.H (S2RND); -R6 = R4.L * R3.L (S2RND); -CHECKREG r0, 0x164DC36C; -CHECKREG r1, 0xCFBA5127; -CHECKREG r2, 0x000F3750; -CHECKREG r3, 0x00060007; -CHECKREG r4, 0xFFF59008; -CHECKREG r5, 0x10ACDFDB; -CHECKREG r6, 0xFFF3C0E0; -CHECKREG r7, 0x1246F00F; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246905; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R1 = R7.H * R0.H (S2RND); -R3 = R6.H * R1.H (S2RND); -R5 = R5.H * R2.L (S2RND); -R7 = R4.L * R3.H (S2RND); -CHECKREG r0, 0xAB235A75; -CHECKREG r1, 0xE7C50648; -CHECKREG r2, 0x13246905; -CHECKREG r3, 0xFFFB74F0; -CHECKREG r4, 0x90ABCD09; -CHECKREG r5, 0x1B5B7D70; -CHECKREG r6, 0x000C0D0D; -CHECKREG r7, 0x0003FB4C; - -imm32 r0, 0x9b235675; -imm32 r1, 0xc9ba5127; -imm32 r2, 0x13946705; -imm32 r3, 0x00090007; -imm32 r4, 0x90ab9d09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c009d; -imm32 r7, 0x12467009; -R1 = R6.H * R4.L (S2RND); -R3 = R5.L * R3.H (S2RND); -R5 = R3.H * R1.L (S2RND); -R7 = R1.H * R2.H (S2RND); -CHECKREG r0, 0x9B235675; -CHECKREG r1, 0xFFED71B0; -CHECKREG r2, 0x13946705; -CHECKREG r3, 0xFFFCE2CC; -CHECKREG r4, 0x90AB9D09; -CHECKREG r5, 0xFFF8E500; -CHECKREG r6, 0x000C009D; -CHECKREG r7, 0xFFFA3010; - -imm32 r0, 0xeb235675; -imm32 r1, 0xceba5127; -imm32 r2, 0x13e46705; -imm32 r3, 0x000e0007; -imm32 r4, 0x90abed09; -imm32 r5, 0x10aceedb; -imm32 r6, 0x000c00ed; -imm32 r7, 0x1246700e; -R1 = R4.L * R0.H (S2RND); -R3 = R6.H * R1.H (S2RND); -R5 = R1.L * R2.L (S2RND); -R7 = R4.H * R2.L (S2RND); -CHECKREG r0, 0xEB235675; -CHECKREG r1, 0x062EACEC; -CHECKREG r2, 0x13E46705; -CHECKREG r3, 0x000128A0; -CHECKREG r4, 0x90ABED09; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0x000C00ED; -CHECKREG r7, 0x80000000; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_u.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_u.s deleted file mode 100644 index d7f6633..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_u.s +++ /dev/null @@ -1,178 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_pair_m_u/c_dsp32mult_pair_m_u.dsp -// Spec Reference: dsp32mult pair MUNOP u -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x34235625; -imm32 r1, 0x9f7a5127; -imm32 r2, 0xa3286725; -imm32 r3, 0x00069027; -imm32 r4, 0xb0abc029; -imm32 r5, 0x10acef2b; -imm32 r6, 0xc00c00de; -imm32 r7, 0xd246712f; -R0 = R0.L * R0.L (FU); -R2 = R0.L * R1.H (FU); -R4 = R1.H * R1.H (FU); -R6 = R0.L * R0.L (FU); -CHECKREG r0, 0x1CFCE159; -CHECKREG r1, 0x9F7A5127; -CHECKREG r2, 0x8C61AB6A; -CHECKREG r3, 0x00069027; -CHECKREG r4, 0x6358C624; -CHECKREG r5, 0x10ACEF2B; -CHECKREG r6, 0xC65D90F1; -CHECKREG r7, 0xD246712F; - -imm32 r0, 0x5b23a635; -imm32 r1, 0x6fba5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x90060037; -imm32 r4, 0x80abcd39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c003d; -imm32 r7, 0x12467003; -R0 = R2.L * R2.L (FU); -R2 = R2.L * R3.H (FU); -R4 = R3.H * R2.H (FU); -R6 = R2.L * R3.L (FU); -CHECKREG r0, 0x831CD0F9; -CHECKREG r1, 0x6FBA5137; -CHECKREG r2, 0x67121B3E; -CHECKREG r3, 0x90060037; -CHECKREG r4, 0x39FC8A6C; -CHECKREG r5, 0xB0ACEF3B; -CHECKREG r6, 0x0005DA52; -CHECKREG r7, 0x12467003; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x43246755; -imm32 r3, 0x05060055; -imm32 r4, 0x906bc509; -imm32 r5, 0x10a7ef5b; -imm32 r6, 0xb00c805d; -imm32 r7, 0x1246795f; -R0 = R4.L * R4.L (FU); -R2 = R4.L * R5.H (FU); -R4 = R5.H * R5.H (FU); -R6 = R4.L * R5.L (FU); -CHECKREG r0, 0x97A6DA51; -CHECKREG r1, 0xC4BA5157; -CHECKREG r2, 0x0CD118DF; -CHECKREG r3, 0x05060055; -CHECKREG r4, 0x01154CF1; -CHECKREG r5, 0x10A7EF5B; -CHECKREG r6, 0x47F058AB; -CHECKREG r7, 0x1246795F; - -imm32 r0, 0xbb235666; -imm32 r1, 0xefba5166; -imm32 r2, 0x13248766; -imm32 r3, 0xf0060066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10acef6b; -imm32 r6, 0x800cb06d; -imm32 r7, 0x1246706f; -R0 = R6.L * R6.L (FU); -R2 = R6.L * R7.H (FU); -R4 = R7.H * R7.H (FU); -R6 = R6.L * R7.L (FU); -CHECKREG r0, 0x79960E69; -CHECKREG r1, 0xEFBA5166; -CHECKREG r2, 0x0C97E7CE; -CHECKREG r3, 0xF0060066; -CHECKREG r4, 0x014DEB24; -CHECKREG r5, 0x10ACEF6B; -CHECKREG r6, 0x4D7C2F43; -CHECKREG r7, 0x1246706F; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R0 = R0.L * R7.L (FU); -R2 = R1.L * R6.H (FU); -R4 = R3.H * R4.H (FU); -R6 = R4.L * R3.L (FU); -CHECKREG r0, 0x9C1770DB; -CHECKREG r1, 0xCFBA5127; -CHECKREG r2, 0x0003CDD4; -CHECKREG r3, 0x00060007; -CHECKREG r4, 0x00036402; -CHECKREG r5, 0x10ACDFDB; -CHECKREG r6, 0x0002BC0E; -CHECKREG r7, 0x1246F00F; - -imm32 r0, 0xab235a75; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246905; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d0d; -imm32 r7, 0x1246700f; -R1 = R7.H * R0.H (FU); -R3 = R6.H * R1.H (FU); -R5 = R5.H * R2.L (FU); -R7 = R4.L * R3.H (FU); -CHECKREG r0, 0xAB235A75; -CHECKREG r1, 0x0C374192; -CHECKREG r2, 0x13246905; -CHECKREG r3, 0x00009294; -CHECKREG r4, 0x90ABCD09; -CHECKREG r5, 0x06D6DF5C; -CHECKREG r6, 0x000C0D0D; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x9b235675; -imm32 r1, 0xc9ba5127; -imm32 r2, 0x13946705; -imm32 r3, 0x00090007; -imm32 r4, 0x90ab9d09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c009d; -imm32 r7, 0x12467009; -R1 = R6.H * R4.L (FU); -R3 = R5.L * R3.H (FU); -R5 = R3.H * R1.L (FU); -R7 = R1.H * R2.H (FU); -CHECKREG r0, 0x9B235675; -CHECKREG r1, 0x00075C6C; -CHECKREG r2, 0x13946705; -CHECKREG r3, 0x000838B3; -CHECKREG r4, 0x90AB9D09; -CHECKREG r5, 0x0002E360; -CHECKREG r6, 0x000C009D; -CHECKREG r7, 0x0000890C; - -imm32 r0, 0xeb235675; -imm32 r1, 0xceba5127; -imm32 r2, 0x13e46705; -imm32 r3, 0x000e0007; -imm32 r4, 0x90abed09; -imm32 r5, 0x10aceedb; -imm32 r6, 0x000c00ed; -imm32 r7, 0x1246700e; -R1 = R4.L * R0.H (FU); -R3 = R6.H * R1.H (FU); -R5 = R1.L * R2.L (FU); -R7 = R4.H * R2.L (FU); -CHECKREG r0, 0xEB235675; -CHECKREG r1, 0xD9B7AB3B; -CHECKREG r2, 0x13E46705; -CHECKREG r3, 0x000A3494; -CHECKREG r4, 0x90ABED09; -CHECKREG r5, 0x44E81527; -CHECKREG r6, 0x000C00ED; -CHECKREG r7, 0x3A37A057; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_s.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_s.s deleted file mode 100644 index dae1552..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_pair_s.s +++ /dev/null @@ -1,180 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_pair_s/c_dsp32mult_pair_s.dsp -// Spec Reference: dsp32mult pair s -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x93ba5127; -imm32 r2, 0xa3446725; -imm32 r3, 0x00050027; -imm32 r4, 0xb0ab6d29; -imm32 r5, 0x10ace72b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467029; -R1 = R0.L * R0.L, R0 = R0.L * R0.L (S2RND); -R3 = R0.L * R1.L, R2 = R0.L * R1.H (S2RND); -R5 = R1.L * R0.L, R4 = R1.H * R0.L (S2RND); -R7 = R1.L * R1.L, R6 = R1.H * R1.H (S2RND); -CHECKREG r0, 0x73F38564; -CHECKREG r1, 0x73F38564; -CHECKREG r2, 0x80000000; -CHECKREG r3, 0x7FFFFFFF; -CHECKREG r4, 0x80000000; -CHECKREG r5, 0x7FFFFFFF; -CHECKREG r6, 0x7FFFFFFF; -CHECKREG r7, 0x7FFFFFFF; - -imm32 r0, 0x5b33a635; -imm32 r1, 0x6fbe5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x9006d037; -imm32 r4, 0x80abcb39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c00dd; -imm32 r7, 0x12469003; -R1 = R2.L * R2.L, R0 = R2.L * R2.L (S2RND); -R3 = R2.L * R3.L, R2 = R2.L * R3.H (S2RND); -R5 = R3.L * R2.L, R4 = R3.H * R2.L (S2RND); -R7 = R3.L * R3.L, R6 = R3.H * R3.H (S2RND); -CHECKREG r0, 0x52CB43E4; -CHECKREG r1, 0x52CB43E4; -CHECKREG r2, 0x7F5C6CF8; -CHECKREG r3, 0x3659B18C; -CHECKREG r4, 0x5C88C8E0; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0x2E26ABC4; -CHECKREG r7, 0x602B9240; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x00060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00c005d; -imm32 r7, 0x1246705f; -R1 = R4.L * R4.L, R0 = R4.L * R4.L (S2RND); -R3 = R4.L * R5.L, R2 = R4.L * R5.H (S2RND); -R5 = R5.L * R4.L, R4 = R5.H * R4.L (S2RND); -R7 = R5.L * R5.L, R6 = R5.H * R5.H (S2RND); -CHECKREG r0, 0x36536944; -CHECKREG r1, 0x36536944; -CHECKREG r2, 0xF0A3C830; -CHECKREG r3, 0x0F55C4CC; -CHECKREG r4, 0xF0A3C830; -CHECKREG r5, 0x0F55C4CC; -CHECKREG r6, 0x03AC48E4; -CHECKREG r7, 0x36C40A40; - -imm32 r0, 0xab235666; -imm32 r1, 0xeaba5166; -imm32 r2, 0x13d48766; -imm32 r3, 0xf00b0066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10ac5f6b; -imm32 r6, 0x800cb66d; -imm32 r7, 0x1246707f; -R1 = R6.L * R6.L, R0 = R6.L * R6.L (S2RND); -R3 = R6.L * R7.L, R2 = R6.L * R7.H (S2RND); -R5 = R7.L * R6.L, R4 = R7.H * R6.L (S2RND); -R7 = R7.L * R7.L, R6 = R7.H * R7.H (S2RND); -CHECKREG r0, 0x5494A9A4; -CHECKREG r1, 0x5494A9A4; -CHECKREG r2, 0xEAFE2F38; -CHECKREG r3, 0x80000000; -CHECKREG r4, 0xEAFE2F38; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0x0537AC90; -CHECKREG r7, 0x7FFFFFFF; - - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (S2RND); -R3 = R1.L * R0.H, R2 = R1.H * R0.L (S2RND); -R5 = R7.H * R4.L, R4 = R7.H * R4.L (S2RND); -R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (S2RND); -CHECKREG r0, 0x000217F0; -CHECKREG r1, 0x0005A246; -CHECKREG r2, 0x0001DEC0; -CHECKREG r3, 0xFFFD1230; -CHECKREG r4, 0xF172C9D8; -CHECKREG r5, 0xF172C9D8; -CHECKREG r6, 0xFFFD0B28; -CHECKREG r7, 0xFFFA7FF0; - -imm32 r0, 0x9b235a75; -imm32 r1, 0xc9ba5127; -imm32 r2, 0x13946905; -imm32 r3, 0x00090007; -imm32 r4, 0x90ab9d09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d9d; -imm32 r7, 0x12467009; -R3 = R6.L * R5.L, R2 = R6.L * R5.H (S2RND); -R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (S2RND); -R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (S2RND); -R7 = R2.H * R7.L, R6 = R2.H * R7.L (S2RND); -CHECKREG r0, 0xF9577348; -CHECKREG r1, 0x31F9EE68; -CHECKREG r2, 0x038BD5F0; -CHECKREG r3, 0xFB4A293C; -CHECKREG r4, 0xB2B9DB04; -CHECKREG r5, 0xEA6A5350; -CHECKREG r6, 0x0633BF8C; -CHECKREG r7, 0x0633BF8C; - -imm32 r0, 0x8b235675; -imm32 r1, 0xc8ba5127; -imm32 r2, 0x13846705; -imm32 r3, 0x00080007; -imm32 r4, 0x90ab8d09; -imm32 r5, 0x10ace8db; -imm32 r6, 0x000c008d; -imm32 r7, 0x12467008; -R3 = R6.H * R5.L, R2 = R6.L * R5.H (S2RND); -R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (S2RND); -R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (S2RND); -R1 = R2.H * R7.L, R0 = R2.L * R7.H (S2RND); -CHECKREG r0, 0x510340C0; -CHECKREG r1, 0xFFDAAA00; -CHECKREG r2, 0x0024BAF0; -CHECKREG r3, 0xFFFBA910; -CHECKREG r4, 0x4B155680; -CHECKREG r5, 0x6B2FA2E0; -CHECKREG r6, 0x0030A1D0; -CHECKREG r7, 0xB4EDBDA0; - -imm32 r0, 0xeb235675; -imm32 r1, 0xceba5127; -imm32 r2, 0x13e46705; -imm32 r3, 0x000e0007; -imm32 r4, 0x90abed09; -imm32 r5, 0x10aceedb; -imm32 r6, 0x000c00ed; -imm32 r7, 0x1246700e; -R1 = R1.H * R4.L, R0 = R1.H * R4.L (S2RND); -R3 = R2.L * R5.L, R2 = R2.L * R5.H (S2RND); -R5 = R3.H * R6.L, R4 = R3.L * R6.L (S2RND); -R7 = R4.L * R0.H, R6 = R4.H * R0.L (S2RND); -CHECKREG r0, 0x0E99DA28; -CHECKREG r1, 0x0E99DA28; -CHECKREG r2, 0x1AD61D70; -CHECKREG r3, 0xE4671D1C; -CHECKREG r4, 0x006BCBB0; -CHECKREG r5, 0xFF99CD6C; -CHECKREG r6, 0xFFC0BAE0; -CHECKREG r7, 0xF41170C0; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_u.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_u.s deleted file mode 100644 index 0c570b2..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32mult_pair_u.s +++ /dev/null @@ -1,179 +0,0 @@ -//Original:/testcases/core/c_dsp32mult_pair_u/c_dsp32mult_pair_u.dsp -// Spec Reference: dsp32mult pair u -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x8b235625; -imm32 r1, 0x93ba5127; -imm32 r2, 0xa3446725; -imm32 r3, 0x00050027; -imm32 r4, 0xb0ab6d29; -imm32 r5, 0x10ace72b; -imm32 r6, 0xc00c008d; -imm32 r7, 0xd2467029; -R1 = R0.L * R0.L, R0 = R0.L * R0.L (FU); -R3 = R0.L * R1.L, R2 = R0.L * R1.H (FU); -R5 = R1.L * R0.L, R4 = R1.H * R0.L (FU); -R7 = R1.L * R1.L, R6 = R1.H * R1.H (FU); -CHECKREG r0, 0x1CFCE159; -CHECKREG r1, 0x1CFCE159; -CHECKREG r2, 0x19838F9C; -CHECKREG r3, 0xC65D90F1; -CHECKREG r4, 0x19838F9C; -CHECKREG r5, 0xC65D90F1; -CHECKREG r6, 0x03481810; -CHECKREG r7, 0xC65D90F1; - -imm32 r0, 0x5b33a635; -imm32 r1, 0x6fbe5137; -imm32 r2, 0x1324b735; -imm32 r3, 0x9006d037; -imm32 r4, 0x80abcb39; -imm32 r5, 0xb0acef3b; -imm32 r6, 0xa00c00dd; -imm32 r7, 0x12469003; -R1 = R2.L * R2.L, R0 = R2.L * R2.L (FU); -R3 = R2.L * R3.L, R2 = R2.L * R3.H (FU); -R5 = R3.L * R2.L, R4 = R3.H * R2.L (FU); -R7 = R3.L * R3.L, R6 = R3.H * R3.H (FU); -CHECKREG r0, 0x831CD0F9; -CHECKREG r1, 0x831CD0F9; -CHECKREG r2, 0x67121B3E; -CHECKREG r3, 0x95026C63; -CHECKREG r4, 0x0FDB4C7C; -CHECKREG r5, 0x0B88B0FA; -CHECKREG r6, 0x56BB5404; -CHECKREG r7, 0x2DE3AE49; - -imm32 r0, 0x1b235655; -imm32 r1, 0xc4ba5157; -imm32 r2, 0x63246755; -imm32 r3, 0x00060055; -imm32 r4, 0x90abc509; -imm32 r5, 0x10acef5b; -imm32 r6, 0xb00c005d; -imm32 r7, 0x1246705f; -R1 = R4.L * R4.L, R0 = R4.L * R4.L (FU); -R3 = R4.L * R5.L, R2 = R4.L * R5.H (FU); -R5 = R5.L * R4.L, R4 = R5.H * R4.L (FU); -R7 = R5.L * R5.L, R6 = R5.H * R5.H (FU); -CHECKREG r0, 0x97A6DA51; -CHECKREG r1, 0x97A6DA51; -CHECKREG r2, 0x0CD4F20C; -CHECKREG r3, 0xB8397133; -CHECKREG r4, 0x0CD4F20C; -CHECKREG r5, 0xB8397133; -CHECKREG r6, 0x8491FCB1; -CHECKREG r7, 0x320E1029; - -imm32 r0, 0xab235666; -imm32 r1, 0xeaba5166; -imm32 r2, 0x13d48766; -imm32 r3, 0xf00b0066; -imm32 r4, 0x90ab9d69; -imm32 r5, 0x10ac5f6b; -imm32 r6, 0x800cb66d; -imm32 r7, 0x1246707f; -R1 = R6.L * R6.L, R0 = R6.L * R6.L (FU); -R3 = R6.L * R7.L, R2 = R6.L * R7.H (FU); -R5 = R7.L * R6.L, R4 = R7.H * R6.L (FU); -R7 = R7.L * R7.L, R6 = R7.H * R7.H (FU); -CHECKREG r0, 0x81FF2A69; -CHECKREG r1, 0x81FF2A69; -CHECKREG r2, 0x0D058BCE; -CHECKREG r3, 0x502A3013; -CHECKREG r4, 0x0D058BCE; -CHECKREG r5, 0x502A3013; -CHECKREG r6, 0x014DEB24; -CHECKREG r7, 0x316F5F01; - -// mix order -imm32 r0, 0xab23a675; -imm32 r1, 0xcfba5127; -imm32 r2, 0x13246705; -imm32 r3, 0x00060007; -imm32 r4, 0x90abcd09; -imm32 r5, 0x10acdfdb; -imm32 r6, 0x000c000d; -imm32 r7, 0x1246f00f; -R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (FU); -R3 = R1.L * R0.H, R2 = R1.H * R0.L (FU); -R5 = R7.H * R4.L, R4 = R7.H * R4.L (FU); -R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (FU); -CHECKREG r0, 0x000085FC; -CHECKREG r1, 0x0002D123; -CHECKREG r2, 0x00010BF8; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x0EA2B276; -CHECKREG r5, 0x0EA2B276; -CHECKREG r6, 0x0000BE3A; -CHECKREG r7, 0xFFFC0FFE; - -imm32 r0, 0x9b235a75; -imm32 r1, 0xc9ba5127; -imm32 r2, 0x13946905; -imm32 r3, 0x00090007; -imm32 r4, 0x90ab9d09; -imm32 r5, 0x10ace9db; -imm32 r6, 0x000c0d9d; -imm32 r7, 0x12467009; -R3 = R6.L * R5.L, R2 = R6.L * R5.H (FU); -R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (FU); -R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (FU); -R7 = R2.H * R7.L, R6 = R2.H * R7.L (FU); -CHECKREG r0, 0x0464B4BB; -CHECKREG r1, 0xB8ADBDCD; -CHECKREG r2, 0x00E2F57C; -CHECKREG r3, 0x0C6F8A4F; -CHECKREG r4, 0x71489715; -CHECKREG r5, 0xD7646535; -CHECKREG r6, 0x0062E7F2; -CHECKREG r7, 0x0062E7F2; - -imm32 r0, 0x8b235675; -imm32 r1, 0xc8ba5127; -imm32 r2, 0x13846705; -imm32 r3, 0x00080007; -imm32 r4, 0x90ab8d09; -imm32 r5, 0x10ace8db; -imm32 r6, 0x000c008d; -imm32 r7, 0x12467008; -R3 = R6.H * R5.L, R2 = R6.L * R5.H (FU); -R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (FU); -R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (FU); -R1 = R2.H * R7.L, R0 = R2.L * R7.H (FU); -CHECKREG r0, 0x04A2FAE8; -CHECKREG r1, 0x00043554; -CHECKREG r2, 0x00092EBC; -CHECKREG r3, 0x000AEA44; -CHECKREG r4, 0xB7AF5568; -CHECKREG r5, 0x4A43345C; -CHECKREG r6, 0x00030A1D; -CHECKREG r7, 0x196677B4; - -imm32 r0, 0xeb235675; -imm32 r1, 0xceba5127; -imm32 r2, 0x13e46705; -imm32 r3, 0x000e0007; -imm32 r4, 0x90abed09; -imm32 r5, 0x10aceedb; -imm32 r6, 0x000c00ed; -imm32 r7, 0x1246700e; -R1 = R1.H * R4.L, R0 = R1.H * R4.L (FU); -R3 = R2.L * R5.L, R2 = R2.L * R5.H (FU); -R5 = R3.H * R6.L, R4 = R3.L * R6.L (FU); -R7 = R4.L * R0.H, R6 = R4.H * R0.L (FU); -CHECKREG r0, 0xBF69768A; -CHECKREG r1, 0xBF69768A; -CHECKREG r2, 0x06B5875C; -CHECKREG r3, 0x601EC747; -CHECKREG r4, 0x00B87CBB; -CHECKREG r5, 0x0058FBC6; -CHECKREG r6, 0x00553330; -CHECKREG r7, 0x5D42ADB3; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_a0alr.s b/sim/testsuite/sim/bfin/c_dsp32shift_a0alr.s deleted file mode 100644 index 4b625aa..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_a0alr.s +++ /dev/null @@ -1,211 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32shift_a0alr/c_dsp32shift_a0alr.dsp -// Spec Reference: dsp32shift a0 ashift, lshift, rot -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - imm32 r0, 0x11140000; - imm32 r1, 0x012C003E; - imm32 r2, 0x81359E24; - imm32 r3, 0x81459E24; - imm32 r4, 0xD159E268; - imm32 r5, 0x51626AF2; - imm32 r6, 0x9176AF36; - imm32 r7, 0xE18BFF86; - - R0.L = 0; - A0 = 0; - A0.L = R1.L; - A0.H = R1.H; - A0 = ASHIFT A0 BY R0.L; /* a0 = 0x00000000 */ - R2 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r2, 0x012C003E; - - R1.L = 1; - A0.L = R2.L; - A0.H = R2.H; - A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00000000 */ - R3 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r3, 0x0258007C; - - R2.L = 15; - A0.L = R3.L; - A0.H = R3.H; - A0 = ASHIFT A0 BY R2.L; /* a0 = 0x00000000 */ - R4 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r4, 0x003E0000; - - R3.L = 31; - A0.L = R4.L; - A0.H = R4.H; - A0 = ASHIFT A0 BY R3.L; /* a0 = 0x00000000 */ - R5 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r5, 0x00000000; - - R4.L = -1; - A0.L = R5.L; - A0.H = R5.H; - A0 = ASHIFT A0 BY R4.L; /* a0 = 0x00000000 */ - R6 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r6, 0x00000000; - - R5.L = -16; - A0 = 0; - A0.L = R6.L; - A0.H = R6.H; - A0 = ASHIFT A0 BY R5.L; /* a0 = 0x00000000 */ - R7 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r7, 0x00000000; - - R6.L = -31; - A0.L = R7.L; - A0.H = R7.H; - A0 = ASHIFT A0 BY R6.L; /* a0 = 0x00000000 */ - R0 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r0, 0x00000000; - - R7.L = -32; - A0.L = R0.L; - A0.H = R0.H; - A0 = ASHIFT A0 BY R7.L; /* a0 = 0x00000000 */ - R1 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r1, 0x00000000; - - imm32 r0, 0x12340000; - imm32 r1, 0x028C003E; - imm32 r2, 0x82159E24; - imm32 r3, 0x82159E24; - imm32 r4, 0xD259E268; - imm32 r5, 0x52E26AF2; - imm32 r6, 0x9226AF36; - imm32 r7, 0xE26BFF86; - - R0.L = 0; - A0 = 0; - A0.L = R1.L; - A0.H = R1.H; - A0 = LSHIFT A0 BY R0.L; /* a0 = 0x00000000 */ - R2 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r2, 0x028C003E; - - R1.L = 1; - A0.L = R2.L; - A0.H = R2.H; - A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00000000 */ - R3 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r3, 0x0518007C; - - R2.L = 15; - A0.L = R3.L; - A0.H = R3.H; - A0 = LSHIFT A0 BY R2.L; /* a0 = 0x00000000 */ - R4 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r4, 0x003E0000; - - R3.L = 31; - A0.L = R4.L; - A0.H = R4.H; - A0 = LSHIFT A0 BY R3.L; /* a0 = 0x00000000 */ - R5 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r5, 0x00000000; - - R4.L = -1; - A0.L = R5.L; - A0.H = R5.H; - A0 = LSHIFT A0 BY R4.L; /* a0 = 0x00000000 */ - R6 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r6, 0x00000000; - - R5.L = -16; - A0 = 0; - A0.L = R6.L; - A0.H = R6.H; - A0 = LSHIFT A0 BY R5.L; /* a0 = 0x00000000 */ - R7 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r7, 0x00000000; - - R6.L = -31; - A0.L = R7.L; - A0.H = R7.H; - A0 = LSHIFT A0 BY R6.L; /* a0 = 0x00000000 */ - R0 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r0, 0x00000000; - - R7.L = -32; - A0.L = R0.L; - A0.H = R0.H; - A0 = LSHIFT A0 BY R7.L; /* a0 = 0x00000000 */ - R1 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r1, 0x00000000; - - imm32 r0, 0x13340000; - imm32 r1, 0x038C003E; - imm32 r2, 0x83159E24; - imm32 r3, 0x83159E24; - imm32 r4, 0xD359E268; - imm32 r5, 0x53E26AF2; - imm32 r6, 0x9326AF36; - imm32 r7, 0xE36BFF86; - - R0.L = 0; - A0 = 0; - A0.L = R1.L; - A0.H = R1.H; - A0 = ROT A0 BY R0.L; /* a0 = 0x00000000 */ - R2 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r2, 0x038C003E; - - R1.L = 1; - A0.L = R2.L; - A0.H = R2.H; - A0 = ROT A0 BY R1.L; /* a0 = 0x00000000 */ - R3 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r3, 0x0718007C; - - R2.L = 15; - A0.L = R3.L; - A0.H = R3.H; - A0 = ROT A0 BY R2.L; /* a0 = 0x00000000 */ - R4 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r4, 0x003E0001; - - R3.L = 31; - A0.L = R4.L; - A0.H = R4.H; - A0 = ROT A0 BY R3.L; /* a0 = 0x00000000 */ - R5 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r5, 0xE3000F80; - - R4.L = -1; - A0.L = R5.L; - A0.H = R5.H; - A0 = ROT A0 BY R4.L; /* a0 = 0x00000000 */ - R6 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r6, 0x718007C0; - - R5.L = -16; - A0.L = R6.L; - A0.H = R6.H; - A0 = ROT A0 BY R5.L; /* a0 = 0x00000000 */ - R7 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r7, 0x80007180; - - R6.L = -31; - A0.L = R7.L; - A0.H = R7.H; - A0 = ROT A0 BY R6.L; /* a0 = 0x00000000 */ - R0 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r0, 0x01C6001F; - - R7.L = -32; - A0.L = R0.L; - A0.H = R0.H; - A0 = ROT A0 BY R7.L; /* a0 = 0x00000000 */ - R1 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r1, 0x8C003E00; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_af.s b/sim/testsuite/sim/bfin/c_dsp32shift_af.s deleted file mode 100644 index c93587b..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_af.s +++ /dev/null @@ -1,186 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32shift_af/c_dsp32shift_af.dsp -// Spec Reference: dsp32shift ashift -# mach: bfin - -.include "testutils.inc" - start - -// ashift : mix data, count (+)= (half reg) -// d_reg = ashift (d BY d_lo) -// Rx by RLx - imm32 r0, 0x01230001; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x856789ab; - imm32 r5, 0x96789abc; - imm32 r6, 0xa789abcd; - imm32 r7, 0xb89abcde; - R4 = ASHIFT R0 BY R0.L; - R5 = ASHIFT R1 BY R0.L; - R6 = ASHIFT R2 BY R0.L; - R7 = ASHIFT R3 BY R0.L; - CHECKREG r4, 0x02460002; - CHECKREG r5, 0x2468ACF0; - CHECKREG r6, 0x468ACF12; - CHECKREG r7, 0x68ACF134; - - imm32 r0, 0x01230002; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x956789ab; - imm32 r5, 0xa6789abc; - imm32 r6, 0xb789abcd; - imm32 r7, 0xc89abcde; - R1.L = 5; - R5 = ASHIFT R0 BY R1.L; - R6 = ASHIFT R1 BY R1.L; - R7 = ASHIFT R2 BY R1.L; - R4 = ASHIFT R3 BY R1.L; - CHECKREG r4, 0x8ACF1340; - CHECKREG r5, 0x24600040; - CHECKREG r6, 0x468000A0; - CHECKREG r7, 0x68ACF120; - - imm32 r0, 0x01230002; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R2 = 15; - R6 = ASHIFT R0 BY R2.L; - R7 = ASHIFT R1 BY R2.L; - R4 = ASHIFT R2 BY R2.L; - R5 = ASHIFT R3 BY R2.L; - CHECKREG r4, 0x00078000; - CHECKREG r5, 0x3C4D0000; - CHECKREG r6, 0x80010000; - CHECKREG r7, 0x2B3C0000; - - imm32 r0, 0x01230002; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0xa56789ab; - imm32 r5, 0xb6789abc; - imm32 r6, 0xc789abcd; - imm32 r7, 0xd89abcde; - R3.L = 16; - R7 = ASHIFT R0 BY R3.L; - R6 = ASHIFT R1 BY R3.L; - R5 = ASHIFT R2 BY R3.L; - R4 = ASHIFT R3 BY R3.L; - CHECKREG r4, 0x00100000; - CHECKREG r5, 0x67890000; - CHECKREG r6, 0x56780000; - CHECKREG r7, 0x00020000; - - imm32 r0, 0x01230002; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R4.L = -1; - R7 = ASHIFT R0 BY R4.L; - R0 = ASHIFT R1 BY R4.L; - R1 = ASHIFT R2 BY R4.L; - R2 = ASHIFT R3 BY R4.L; - R3 = ASHIFT R4 BY R4.L; - R4 = ASHIFT R5 BY R4.L; - R5 = ASHIFT R6 BY R4.L; - R6 = ASHIFT R7 BY R4.L; - CHECKREG r0, 0x091A2B3C; - CHECKREG r1, 0x11A2B3C4; - CHECKREG r2, 0x1A2B3C4D; - CHECKREG r3, 0x22B3FFFF; - CHECKREG r4, 0x2B3C4D5E; - CHECKREG r5, 0x40000000; - CHECKREG r6, 0x40000000; - CHECKREG r7, 0x00918001; - - imm32 r0, 0x01230002; - imm32 r1, 0x82345678; - imm32 r2, 0x93456789; - imm32 r3, 0xa456789a; - imm32 r4, 0xb56789ab; - imm32 r5, 0xc6789abc; - imm32 r6, 0xd789abcd; - imm32 r7, 0xe89abcde; - R5.L = -6; - R6 = ASHIFT R0 BY R5.L; - R7 = ASHIFT R1 BY R5.L; - R0 = ASHIFT R2 BY R5.L; - R1 = ASHIFT R3 BY R5.L; - R2 = ASHIFT R4 BY R5.L; - R3 = ASHIFT R5 BY R5.L; - R4 = ASHIFT R6 BY R5.L; - R5 = ASHIFT R7 BY R5.L; - CHECKREG r0, 0xFE4D159E; - CHECKREG r1, 0xFE9159E2; - CHECKREG r2, 0xFED59E26; - CHECKREG r3, 0xFF19E3FF; - CHECKREG r4, 0x00001230; - CHECKREG r5, 0xFFF82345; - CHECKREG r6, 0x00048C00; - CHECKREG r7, 0xFE08D159; - - imm32 r0, 0x01230002; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R6.L = -15; - R5 = ASHIFT R0 BY R6.L; - R0 = ASHIFT R1 BY R6.L; - R7 = ASHIFT R2 BY R6.L; - R0 = ASHIFT R3 BY R6.L; - R1 = ASHIFT R4 BY R6.L; - R2 = ASHIFT R5 BY R6.L; - R3 = ASHIFT R6 BY R6.L; - R6 = ASHIFT R7 BY R6.L; - CHECKREG r0, 0x000068AC; - CHECKREG r1, 0x00008ACF; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x0000CF13; - CHECKREG r4, 0x456789AB; - CHECKREG r5, 0x00000246; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x0000468A; - - imm32 r0, 0x01230002; - imm32 r1, 0x82345678; - imm32 r2, 0x93456789; - imm32 r3, 0xa456789a; - imm32 r4, 0xb56789ab; - imm32 r5, 0xc6789abc; - imm32 r6, 0xd789abcd; - imm32 r7, 0xe89abcde; - R7.L = -14; - R0 = ASHIFT R0 BY R7.L; - R1 = ASHIFT R1 BY R7.L; - R2 = ASHIFT R2 BY R7.L; - R3 = ASHIFT R3 BY R7.L; - R4 = ASHIFT R4 BY R7.L; - R5 = ASHIFT R5 BY R7.L; - R6 = ASHIFT R6 BY R7.L; - R7 = ASHIFT R7 BY R7.L; - CHECKREG r0, 0x0000048C; - CHECKREG r1, 0xFFFE08D1; - CHECKREG r2, 0xFFFE4D15; - CHECKREG r3, 0xFFFE9159; - CHECKREG r4, 0xFFFED59E; - CHECKREG r5, 0xFFFF19E2; - CHECKREG r6, 0xFFFF5E26; - CHECKREG r7, 0xFFFFA26B; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_af_s.s b/sim/testsuite/sim/bfin/c_dsp32shift_af_s.s deleted file mode 100644 index e94f7cb..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_af_s.s +++ /dev/null @@ -1,186 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32shift_af_s/c_dsp32shift_af_s.dsp -// Spec Reference: dsp32shift ashift s -# mach: bfin - -.include "testutils.inc" - start - -// ashift : mix data, count (+)= (half reg) -// d_reg = ashift (d BY d_lo) -// Rx by RLx - imm32 r0, 0x01230001; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x856789ab; - imm32 r5, 0x96789abc; - imm32 r6, 0xa789abcd; - imm32 r7, 0xb89abcde; - R4 = ASHIFT R0 BY R0.L (S); - R5 = ASHIFT R1 BY R0.L (S); - R6 = ASHIFT R2 BY R0.L (S); - R7 = ASHIFT R3 BY R0.L (S); - CHECKREG r4, 0x02460002; - CHECKREG r5, 0x2468ACF0; - CHECKREG r6, 0x468ACF12; - CHECKREG r7, 0x68ACF134; - - imm32 r0, 0x01230002; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x956789ab; - imm32 r5, 0xa6789abc; - imm32 r6, 0xb789abcd; - imm32 r7, 0xc89abcde; - R1.L = 5; - R5 = ASHIFT R0 BY R1.L (S); - R6 = ASHIFT R1 BY R1.L (S); - R7 = ASHIFT R2 BY R1.L (S); - R4 = ASHIFT R3 BY R1.L (S); - CHECKREG r4, 0x7FFFFFFF; - CHECKREG r5, 0x24600040; - CHECKREG r6, 0x7FFFFFFF; - CHECKREG r7, 0x7FFFFFFF; - - imm32 r0, 0x01230002; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R2 = 14; - R6 = ASHIFT R0 BY R2.L (S); - R7 = ASHIFT R1 BY R2.L (S); - R4 = ASHIFT R2 BY R2.L (S); - R5 = ASHIFT R3 BY R2.L (S); - CHECKREG r4, 0x00038000; - CHECKREG r5, 0x7FFFFFFF; - CHECKREG r6, 0x7FFFFFFF; - CHECKREG r7, 0x7FFFFFFF; - - imm32 r0, 0x01230002; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0xa56789ab; - imm32 r5, 0xb6789abc; - imm32 r6, 0xc789abcd; - imm32 r7, 0xd89abcde; - R3.L = 15; - R7 = ASHIFT R0 BY R3.L (S); - R6 = ASHIFT R1 BY R3.L (S); - R5 = ASHIFT R2 BY R3.L (S); - R4 = ASHIFT R3 BY R3.L (S); - CHECKREG r4, 0x7FFFFFFF; - CHECKREG r5, 0x7FFFFFFF; - CHECKREG r6, 0x7FFFFFFF; - CHECKREG r7, 0x7FFFFFFF; - - imm32 r0, 0x01230002; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R4.L = -1; - R7 = ASHIFT R0 BY R4.L; - R0 = ASHIFT R1 BY R4.L; - R1 = ASHIFT R2 BY R4.L; - R2 = ASHIFT R3 BY R4.L; - R3 = ASHIFT R4 BY R4.L; - R4 = ASHIFT R5 BY R4.L; - R5 = ASHIFT R6 BY R4.L; - R6 = ASHIFT R7 BY R4.L; - CHECKREG r0, 0x091A2B3C; - CHECKREG r1, 0x11A2B3C4; - CHECKREG r2, 0x1A2B3C4D; - CHECKREG r3, 0x22B3FFFF; - CHECKREG r4, 0x2B3C4D5E; - CHECKREG r5, 0x40000000; - CHECKREG r6, 0x40000000; - CHECKREG r7, 0x00918001; - - imm32 r0, 0x01230002; - imm32 r1, 0x82345678; - imm32 r2, 0x93456789; - imm32 r3, 0xa456789a; - imm32 r4, 0xb56789ab; - imm32 r5, 0xc6789abc; - imm32 r6, 0xd789abcd; - imm32 r7, 0xe89abcde; - R5.L = -6; - R6 = ASHIFT R0 BY R5.L (S); - R7 = ASHIFT R1 BY R5.L (S); - R0 = ASHIFT R2 BY R5.L (S); - R1 = ASHIFT R3 BY R5.L (S); - R2 = ASHIFT R4 BY R5.L (S); - R3 = ASHIFT R5 BY R5.L (S); - R4 = ASHIFT R6 BY R5.L (S); - R5 = ASHIFT R7 BY R5.L (S); - CHECKREG r0, 0xFE4D159E; - CHECKREG r1, 0xFE9159E2; - CHECKREG r2, 0xFED59E26; - CHECKREG r3, 0xFF19E3FF; - CHECKREG r4, 0x00001230; - CHECKREG r5, 0xFFF82345; - CHECKREG r6, 0x00048C00; - CHECKREG r7, 0xFE08D159; - - imm32 r0, 0x01230002; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R6.L = -15; - R5 = ASHIFT R0 BY R6.L (S); - R0 = ASHIFT R1 BY R6.L (S); - R7 = ASHIFT R2 BY R6.L (S); - R0 = ASHIFT R3 BY R6.L (S); - R1 = ASHIFT R4 BY R6.L (S); - R2 = ASHIFT R5 BY R6.L (S); - R3 = ASHIFT R6 BY R6.L (S); - R6 = ASHIFT R7 BY R6.L (S); - CHECKREG r0, 0x000068AC; - CHECKREG r1, 0x00008ACF; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x0000CF13; - CHECKREG r4, 0x456789AB; - CHECKREG r5, 0x00000246; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x0000468A; - - imm32 r0, 0x01230002; - imm32 r1, 0x82345678; - imm32 r2, 0x93456789; - imm32 r3, 0xa456789a; - imm32 r4, 0xb56789ab; - imm32 r5, 0xc6789abc; - imm32 r6, 0xd789abcd; - imm32 r7, 0xe89abcde; - R7.L = -14; - R0 = ASHIFT R0 BY R7.L (S); - R1 = ASHIFT R1 BY R7.L (S); - R2 = ASHIFT R2 BY R7.L (S); - R3 = ASHIFT R3 BY R7.L (S); - R4 = ASHIFT R4 BY R7.L (S); - R5 = ASHIFT R5 BY R7.L (S); - R6 = ASHIFT R6 BY R7.L (S); - R7 = ASHIFT R7 BY R7.L (S); - CHECKREG r0, 0x0000048C; - CHECKREG r1, 0xFFFE08D1; - CHECKREG r2, 0xFFFE4D15; - CHECKREG r3, 0xFFFE9159; - CHECKREG r4, 0xFFFED59E; - CHECKREG r5, 0xFFFF19E2; - CHECKREG r6, 0xFFFF5E26; - CHECKREG r7, 0xFFFFA26B; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln.s deleted file mode 100644 index 9a37aef..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln.s +++ /dev/null @@ -1,423 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_ahalf_ln/c_dsp32shift_ahalf_ln.dsp -// Spec Reference: dsp32shift ashift -# mach: bfin - -.include "testutils.inc" - start - - - - -// Ashift : neg data, count (+)=left (half reg) -// d_lo = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x0000c001; -imm32 r2, 0x0000c002; -imm32 r3, 0x0000c003; -imm32 r4, 0x0000c004; -imm32 r5, 0x0000c005; -imm32 r6, 0x0000c006; -imm32 r7, 0x0000c007; -R0.L = ASHIFT R0.L BY R0.L; -R1.L = ASHIFT R1.L BY R0.L; -R2.L = ASHIFT R2.L BY R0.L; -R3.L = ASHIFT R3.L BY R0.L; -R4.L = ASHIFT R4.L BY R0.L; -R5.L = ASHIFT R5.L BY R0.L; -R6.L = ASHIFT R6.L BY R0.L; -R7.L = ASHIFT R7.L BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x0000c001; -CHECKREG r2, 0x0000c002; -CHECKREG r3, 0x0000c003; -CHECKREG r4, 0x0000c004; -CHECKREG r5, 0x0000c005; -CHECKREG r6, 0x0000c006; -CHECKREG r7, 0x0000c007; - -imm32 r0, 0x00008001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000d002; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000c005; -imm32 r6, 0x0000d006; -imm32 r7, 0x0000e007; -R0.L = ASHIFT R0.L BY R1.L; -//rl1 = ashift (rl1 by rl1); -R2.L = ASHIFT R2.L BY R1.L; -R3.L = ASHIFT R3.L BY R1.L; -R4.L = ASHIFT R4.L BY R1.L; -R5.L = ASHIFT R5.L BY R1.L; -R6.L = ASHIFT R6.L BY R1.L; -R7.L = ASHIFT R7.L BY R1.L; -//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */ -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x0000a004; -CHECKREG r3, 0x0000c006; -CHECKREG r4, 0x0000e008; -CHECKREG r5, 0x0000800a; -CHECKREG r6, 0x0000a00c; -CHECKREG r7, 0x0000c00e; - - -imm32 r0, 0x0000c001; -imm32 r1, 0x0000d001; -imm32 r2, 0x0000000f; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000f005; -imm32 r6, 0x0000f006; -imm32 r7, 0x0000f007; -R0.L = ASHIFT R0.L BY R2.L; -R1.L = ASHIFT R1.L BY R2.L; -//rl2 = ashift (rl2 by rl2); -R3.L = ASHIFT R3.L BY R2.L; -R4.L = ASHIFT R4.L BY R2.L; -R5.L = ASHIFT R5.L BY R2.L; -R6.L = ASHIFT R6.L BY R2.L; -R7.L = ASHIFT R7.L BY R2.L; -CHECKREG r0, 0x00008000; -CHECKREG r1, 0x00008000; -CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x00008000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00008000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00008000; - -imm32 r0, 0x00009001; -imm32 r1, 0x0000a001; -imm32 r2, 0x0000b002; -imm32 r3, 0x00000010; -imm32 r4, 0x0000c004; -imm32 r5, 0x0000d005; -imm32 r6, 0x0000e006; -imm32 r7, 0x0000f007; -R0.L = ASHIFT R0.L BY R3.L; -R1.L = ASHIFT R1.L BY R3.L; -R2.L = ASHIFT R2.L BY R3.L; -//rl3 = ashift (rl3 by rl3); -R4.L = ASHIFT R4.L BY R3.L; -R5.L = ASHIFT R5.L BY R3.L; -R6.L = ASHIFT R6.L BY R3.L; -R7.L = ASHIFT R7.L BY R3.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ASHIFT R0.H BY R0.L; -R1.L = ASHIFT R1.H BY R0.L; -R2.L = ASHIFT R2.H BY R0.L; -R3.L = ASHIFT R3.H BY R0.L; -R4.L = ASHIFT R4.H BY R0.L; -R5.L = ASHIFT R5.H BY R0.L; -R6.L = ASHIFT R6.H BY R0.L; -R7.L = ASHIFT R7.H BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x90010000; -imm32 r1, 0x00010001; -imm32 r2, 0x90020000; -imm32 r3, 0x90030000; -imm32 r4, 0x90040000; -imm32 r5, 0x90050000; -imm32 r6, 0x90060000; -imm32 r7, 0x90070000; -R0.L = ASHIFT R0.H BY R1.L; -//rl1 = ashift (rh1 by rl1); -R2.L = ASHIFT R2.H BY R1.L; -R3.L = ASHIFT R3.H BY R1.L; -R4.L = ASHIFT R4.H BY R1.L; -R5.L = ASHIFT R5.H BY R1.L; -R6.L = ASHIFT R6.H BY R1.L; -R7.L = ASHIFT R7.H BY R1.L; -CHECKREG r0, 0x90012002; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x90022004; -CHECKREG r3, 0x90032006; -CHECKREG r4, 0x90042008; -CHECKREG r5, 0x9005200a; -CHECKREG r6, 0x9006200c; -CHECKREG r7, 0x9007200e; - - -imm32 r0, 0xa0010000; -imm32 r1, 0xa0010000; -imm32 r2, 0xa002000f; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R0.L = ASHIFT R0.H BY R2.L; -R1.L = ASHIFT R1.H BY R2.L; -//rl2 = ashift (rh2 by rl2); -R3.L = ASHIFT R3.H BY R2.L; -R4.L = ASHIFT R4.H BY R2.L; -R5.L = ASHIFT R5.H BY R2.L; -R6.L = ASHIFT R6.H BY R2.L; -R7.L = ASHIFT R7.H BY R2.L; -CHECKREG r0, 0xa0018000; -CHECKREG r1, 0xa0018000; -CHECKREG r2, 0xa002000f; -CHECKREG r3, 0xa0038000; -CHECKREG r4, 0xa0040000; -CHECKREG r5, 0xa0058000; -CHECKREG r6, 0xa0060000; -CHECKREG r7, 0xa0078000; - -imm32 r0, 0xc0010001; -imm32 r1, 0xc0010001; -imm32 r2, 0xc0020002; -imm32 r3, 0xc0030010; -imm32 r4, 0xc0040004; -imm32 r5, 0xc0050005; -imm32 r6, 0xc0060006; -imm32 r7, 0xc0070007; -R0.L = ASHIFT R0.H BY R3.L; -R1.L = ASHIFT R1.H BY R3.L; -R2.L = ASHIFT R2.H BY R3.L; -//rl3 = ashift (rh3 by rl3); -R4.L = ASHIFT R4.H BY R3.L; -R5.L = ASHIFT R5.H BY R3.L; -R6.L = ASHIFT R6.H BY R3.L; -R7.L = ASHIFT R7.H BY R3.L; -CHECKREG r0, 0xc0010000; -CHECKREG r1, 0xc0010000; -CHECKREG r2, 0xc0020000; -CHECKREG r3, 0xc0030010; -CHECKREG r4, 0xc0040000; -CHECKREG r5, 0xc0050000; -CHECKREG r6, 0xc0060000; -CHECKREG r7, 0xc0070000; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R0.L; -R1.H = ASHIFT R1.L BY R0.L; -R2.H = ASHIFT R2.L BY R0.L; -R3.H = ASHIFT R3.L BY R0.L; -R4.H = ASHIFT R4.L BY R0.L; -R5.H = ASHIFT R5.L BY R0.L; -R6.H = ASHIFT R6.L BY R0.L; -R7.H = ASHIFT R7.L BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x0000d001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000d002; -imm32 r3, 0x0000d003; -imm32 r4, 0x0000d004; -imm32 r5, 0x0000d005; -imm32 r6, 0x0000d006; -imm32 r7, 0x0000d007; -R0.H = ASHIFT R0.L BY R1.L; -R1.H = ASHIFT R1.L BY R1.L; -R2.H = ASHIFT R2.L BY R1.L; -R3.H = ASHIFT R3.L BY R1.L; -R4.H = ASHIFT R4.L BY R1.L; -R5.H = ASHIFT R5.L BY R1.L; -R6.H = ASHIFT R6.L BY R1.L; -R7.H = ASHIFT R7.L BY R1.L; -CHECKREG r0, 0xa002d001; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0xa004d002; -CHECKREG r3, 0xa006d003; -CHECKREG r4, 0xa008d004; -CHECKREG r5, 0xa00ad005; -CHECKREG r6, 0xa00cd006; -CHECKREG r7, 0xa00ed007; - - -imm32 r0, 0x0000e001; -imm32 r1, 0x0000e001; -imm32 r2, 0x0000000f; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000e004; -imm32 r5, 0x0000e005; -imm32 r6, 0x0000e006; -imm32 r7, 0x0000e007; -R0.H = ASHIFT R0.L BY R2.L; -R1.H = ASHIFT R1.L BY R2.L; -//rh2 = ashift (rl2 by rl2); -R3.H = ASHIFT R3.L BY R2.L; -R4.H = ASHIFT R4.L BY R2.L; -R5.H = ASHIFT R5.L BY R2.L; -R6.H = ASHIFT R6.L BY R2.L; -R7.H = ASHIFT R7.L BY R2.L; -CHECKREG r0, 0x8000e001; -CHECKREG r1, 0x8000e001; -CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x8000e003; -CHECKREG r4, 0x0000e004; -CHECKREG r5, 0x8000e005; -CHECKREG r6, 0x0000e006; -CHECKREG r7, 0x8000e007; - -imm32 r0, 0x0000f001; -imm32 r1, 0x0000f001; -imm32 r2, 0x0000f002; -imm32 r3, 0x00000010; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000f005; -imm32 r6, 0x0000f006; -imm32 r7, 0x0000f007; -R0.H = ASHIFT R0.L BY R3.L; -R1.H = ASHIFT R1.L BY R3.L; -R2.H = ASHIFT R2.L BY R3.L; -R3.H = ASHIFT R3.L BY R3.L; -R4.H = ASHIFT R4.L BY R3.L; -R5.H = ASHIFT R5.L BY R3.L; -R6.H = ASHIFT R6.L BY R3.L; -R7.H = ASHIFT R7.L BY R3.L; -CHECKREG r0, 0x0000f001; -CHECKREG r1, 0x0000f001; -CHECKREG r2, 0x0000f002; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x0000f004; -CHECKREG r5, 0x0000f005; -CHECKREG r6, 0x0000f006; -CHECKREG r7, 0x0000f007; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = ASHIFT R0.H BY R0.L; -R1.H = ASHIFT R1.H BY R0.L; -R2.H = ASHIFT R2.H BY R0.L; -R3.H = ASHIFT R3.H BY R0.L; -R4.H = ASHIFT R4.H BY R0.L; -R5.H = ASHIFT R5.H BY R0.L; -R6.H = ASHIFT R6.H BY R0.L; -R7.H = ASHIFT R7.H BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x00020000; -CHECKREG r3, 0x00030000; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00050000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00070000; - -imm32 r0, 0xa0010000; -imm32 r1, 0x00010001; -imm32 r2, 0xa0020000; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R0.H = ASHIFT R0.H BY R1.L; -R1.H = ASHIFT R1.H BY R1.L; -R2.H = ASHIFT R2.H BY R1.L; -R3.H = ASHIFT R3.H BY R1.L; -R4.H = ASHIFT R4.H BY R1.L; -R5.H = ASHIFT R5.H BY R1.L; -R6.H = ASHIFT R6.H BY R1.L; -R7.H = ASHIFT R7.H BY R1.L; -CHECKREG r0, 0x40020000; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0x40040000; -CHECKREG r3, 0x40060000; -CHECKREG r4, 0x40080000; -CHECKREG r5, 0x400a0000; -CHECKREG r6, 0x400c0000; -CHECKREG r7, 0x400e0000; - - -imm32 r0, 0xb0010000; -imm32 r1, 0xb0010000; -imm32 r2, 0xb002000f; -imm32 r3, 0xb0030000; -imm32 r4, 0xb0040000; -imm32 r5, 0xb0050000; -imm32 r6, 0xb0060000; -imm32 r7, 0xb0070000; -R0.L = ASHIFT R0.H BY R2.L; -R1.L = ASHIFT R1.H BY R2.L; -//rl2 = ashift (rh2 by rl2); -R3.L = ASHIFT R3.H BY R2.L; -R4.L = ASHIFT R4.H BY R2.L; -R5.L = ASHIFT R5.H BY R2.L; -R6.L = ASHIFT R6.H BY R2.L; -R7.L = ASHIFT R7.H BY R2.L; -CHECKREG r0, 0xb0018000; -CHECKREG r1, 0xb0018000; -CHECKREG r2, 0xb002000f; -CHECKREG r3, 0xb0038000; -CHECKREG r4, 0xb0040000; -CHECKREG r5, 0xb0058000; -CHECKREG r6, 0xb0060000; -CHECKREG r7, 0xb0078000; - -imm32 r0, 0xd0010000; -imm32 r1, 0xd0010000; -imm32 r2, 0xd0020000; -imm32 r3, 0xd0030010; -imm32 r4, 0xd0040000; -imm32 r5, 0xd0050000; -imm32 r6, 0xd0060000; -imm32 r7, 0xd0070000; -R0.H = ASHIFT R0.H BY R3.L; -R1.H = ASHIFT R1.H BY R3.L; -R2.H = ASHIFT R2.H BY R3.L; -R3.H = ASHIFT R3.H BY R3.L; -R4.H = ASHIFT R4.H BY R3.L; -R5.H = ASHIFT R5.H BY R3.L; -R6.H = ASHIFT R6.H BY R3.L; -R7.H = ASHIFT R7.H BY R3.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln_s.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln_s.s deleted file mode 100644 index dd6b8d4..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln_s.s +++ /dev/null @@ -1,423 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_ahalf_ln_s/c_dsp32shift_ahalf_ln_s.dsp -// Spec Reference: -# mach: bfin - -.include "testutils.inc" - start - - - -// Ashift : neg data, count (+)=left (half reg) -// d_lo = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x0000c001; -imm32 r2, 0x0000c002; -imm32 r3, 0x0000c003; -imm32 r4, 0x0000c004; -imm32 r5, 0x0000c005; -imm32 r6, 0x0000c006; -imm32 r7, 0x0000c007; -R0.L = ASHIFT R0.L BY R0.L (S); -R1.L = ASHIFT R1.L BY R0.L (S); -R2.L = ASHIFT R2.L BY R0.L (S); -R3.L = ASHIFT R3.L BY R0.L (S); -R4.L = ASHIFT R4.L BY R0.L (S); -R5.L = ASHIFT R5.L BY R0.L (S); -R6.L = ASHIFT R6.L BY R0.L (S); -R7.L = ASHIFT R7.L BY R0.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x0000c001; -CHECKREG r2, 0x0000c002; -CHECKREG r3, 0x0000c003; -CHECKREG r4, 0x0000c004; -CHECKREG r5, 0x0000c005; -CHECKREG r6, 0x0000c006; -CHECKREG r7, 0x0000c007; - -imm32 r0, 0x00008001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000d002; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000c005; -imm32 r6, 0x0000d006; -imm32 r7, 0x0000e007; -R0.L = ASHIFT R0.L BY R1.L (S); -//rl1 = ashift (rl1 by rl1); -R2.L = ASHIFT R2.L BY R1.L (S); -R3.L = ASHIFT R3.L BY R1.L (S); -R4.L = ASHIFT R4.L BY R1.L (S); -R5.L = ASHIFT R5.L BY R1.L (S); -R6.L = ASHIFT R6.L BY R1.L (S); -R7.L = ASHIFT R7.L BY R1.L (S); -//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */ -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x0000a004; -CHECKREG r3, 0x0000c006; -CHECKREG r4, 0x0000e008; -CHECKREG r5, 0x0000800a; -CHECKREG r6, 0x0000a00c; -CHECKREG r7, 0x0000c00e; - - -imm32 r0, 0x0000c001; -imm32 r1, 0x0000d001; -imm32 r2, 0x0000000f; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000f005; -imm32 r6, 0x0000f006; -imm32 r7, 0x0000f007; -R0.L = ASHIFT R0.L BY R2.L (S); -R1.L = ASHIFT R1.L BY R2.L (S); -//rl2 = ashift (rl2 by rl2); -R3.L = ASHIFT R3.L BY R2.L (S); -R4.L = ASHIFT R4.L BY R2.L (S); -R5.L = ASHIFT R5.L BY R2.L (S); -R6.L = ASHIFT R6.L BY R2.L (S); -R7.L = ASHIFT R7.L BY R2.L (S); -CHECKREG r0, 0x00008000; -CHECKREG r1, 0x00008000; -CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x00008000; -CHECKREG r4, 0x00008000; -CHECKREG r5, 0x00008000; -CHECKREG r6, 0x00008000; -CHECKREG r7, 0x00008000; - -imm32 r0, 0x00009001; -imm32 r1, 0x0000a001; -imm32 r2, 0x0000b002; -imm32 r3, 0x00000010; -imm32 r4, 0x0000c004; -imm32 r5, 0x0000d005; -imm32 r6, 0x0000e006; -imm32 r7, 0x0000f007; -R0.L = ASHIFT R0.L BY R3.L (S); -R1.L = ASHIFT R1.L BY R3.L (S); -R2.L = ASHIFT R2.L BY R3.L (S); -//rl3 = ashift (rl3 by rl3); -R4.L = ASHIFT R4.L BY R3.L (S); -R5.L = ASHIFT R5.L BY R3.L (S); -R6.L = ASHIFT R6.L BY R3.L (S); -R7.L = ASHIFT R7.L BY R3.L (S); -CHECKREG r0, 0x00008000; -CHECKREG r1, 0x00008000; -CHECKREG r2, 0x00008000; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00008000; -CHECKREG r5, 0x00008000; -CHECKREG r6, 0x00008000; -CHECKREG r7, 0x00008000; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ASHIFT R0.H BY R0.L (S); -R1.L = ASHIFT R1.H BY R0.L (S); -R2.L = ASHIFT R2.H BY R0.L (S); -R3.L = ASHIFT R3.H BY R0.L (S); -R4.L = ASHIFT R4.H BY R0.L (S); -R5.L = ASHIFT R5.H BY R0.L (S); -R6.L = ASHIFT R6.H BY R0.L (S); -R7.L = ASHIFT R7.H BY R0.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x90010000; -imm32 r1, 0x00010001; -imm32 r2, 0x90020000; -imm32 r3, 0x90030000; -imm32 r4, 0x90040000; -imm32 r5, 0x90050000; -imm32 r6, 0x90060000; -imm32 r7, 0x90070000; -R0.L = ASHIFT R0.H BY R1.L (S); -//rl1 = ashift (rh1 by rl1); -R2.L = ASHIFT R2.H BY R1.L (S); -R3.L = ASHIFT R3.H BY R1.L (S); -R4.L = ASHIFT R4.H BY R1.L (S); -R5.L = ASHIFT R5.H BY R1.L (S); -R6.L = ASHIFT R6.H BY R1.L (S); -R7.L = ASHIFT R7.H BY R1.L (S); -CHECKREG r0, 0x90018000; -//CHECKREG r1, 0x00018000; -CHECKREG r2, 0x90028000; -CHECKREG r3, 0x90038000; -CHECKREG r4, 0x90048000; -CHECKREG r5, 0x90058000; -CHECKREG r6, 0x90068000; -CHECKREG r7, 0x90078000; - - -imm32 r0, 0xa0010000; -imm32 r1, 0xa0010000; -imm32 r2, 0xa002000f; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R0.L = ASHIFT R0.H BY R2.L (S); -R1.L = ASHIFT R1.H BY R2.L (S); -//rl2 = ashift (rh2 by rl2); -R3.L = ASHIFT R3.H BY R2.L (S); -R4.L = ASHIFT R4.H BY R2.L (S); -R5.L = ASHIFT R5.H BY R2.L (S); -R6.L = ASHIFT R6.H BY R2.L (S); -R7.L = ASHIFT R7.H BY R2.L (S); -CHECKREG r0, 0xa0018000; -CHECKREG r1, 0xa0018000; -//CHECKREG r2, 0xa002000f; -CHECKREG r3, 0xa0038000; -CHECKREG r4, 0xa0048000; -CHECKREG r5, 0xa0058000; -CHECKREG r6, 0xa0068000; -CHECKREG r7, 0xa0078000; - -imm32 r0, 0xc0010001; -imm32 r1, 0xc0010001; -imm32 r2, 0xc0020002; -imm32 r3, 0xc0030010; -imm32 r4, 0xc0040004; -imm32 r5, 0xc0050005; -imm32 r6, 0xc0060006; -imm32 r7, 0xc0070007; -R0.L = ASHIFT R0.H BY R3.L (S); -R1.L = ASHIFT R1.H BY R3.L (S); -R2.L = ASHIFT R2.H BY R3.L (S); -//rl3 = ashift (rh3 by rl3); -R4.L = ASHIFT R4.H BY R3.L (S); -R5.L = ASHIFT R5.H BY R3.L (S); -R6.L = ASHIFT R6.H BY R3.L (S); -R7.L = ASHIFT R7.H BY R3.L (S); -CHECKREG r0, 0xc0018000; -CHECKREG r1, 0xc0018000; -CHECKREG r2, 0xc0028000; -CHECKREG r3, 0xc0030010; -CHECKREG r4, 0xc0048000; -CHECKREG r5, 0xc0058000; -CHECKREG r6, 0xc0068000; -CHECKREG r7, 0xc0078000; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R0.L (S); -R1.H = ASHIFT R1.L BY R0.L (S); -R2.H = ASHIFT R2.L BY R0.L (S); -R3.H = ASHIFT R3.L BY R0.L (S); -R4.H = ASHIFT R4.L BY R0.L (S); -R5.H = ASHIFT R5.L BY R0.L (S); -R6.H = ASHIFT R6.L BY R0.L (S); -R7.H = ASHIFT R7.L BY R0.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x0000d001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000d002; -imm32 r3, 0x0000d003; -imm32 r4, 0x0000d004; -imm32 r5, 0x0000d005; -imm32 r6, 0x0000d006; -imm32 r7, 0x0000d007; -R0.H = ASHIFT R0.L BY R1.L (S); -R1.H = ASHIFT R1.L BY R1.L (S); -R2.H = ASHIFT R2.L BY R1.L (S); -R3.H = ASHIFT R3.L BY R1.L (S); -R4.H = ASHIFT R4.L BY R1.L (S); -R5.H = ASHIFT R5.L BY R1.L (S); -R6.H = ASHIFT R6.L BY R1.L (S); -R7.H = ASHIFT R7.L BY R1.L (S); -CHECKREG r0, 0xa002d001; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0xa004d002; -CHECKREG r3, 0xa006d003; -CHECKREG r4, 0xa008d004; -CHECKREG r5, 0xa00ad005; -CHECKREG r6, 0xa00cd006; -CHECKREG r7, 0xa00ed007; - - -imm32 r0, 0x0000e001; -imm32 r1, 0x0000e001; -imm32 r2, 0x0000000f; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000e004; -imm32 r5, 0x0000e005; -imm32 r6, 0x0000e006; -imm32 r7, 0x0000e007; -R0.H = ASHIFT R0.L BY R2.L (S); -R1.H = ASHIFT R1.L BY R2.L (S); -//rh2 = ashift (rl2 by rl2); -R3.H = ASHIFT R3.L BY R2.L (S); -R4.H = ASHIFT R4.L BY R2.L (S); -R5.H = ASHIFT R5.L BY R2.L (S); -R6.H = ASHIFT R6.L BY R2.L (S); -R7.H = ASHIFT R7.L BY R2.L (S); -CHECKREG r0, 0x8000e001; -CHECKREG r1, 0x8000e001; -CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x8000e003; -CHECKREG r4, 0x8000e004; -CHECKREG r5, 0x8000e005; -CHECKREG r6, 0x8000e006; -CHECKREG r7, 0x8000e007; - -imm32 r0, 0x0000f001; -imm32 r1, 0x0000f001; -imm32 r2, 0x0000f002; -imm32 r3, 0x00000010; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000f005; -imm32 r6, 0x0000f006; -imm32 r7, 0x0000f007; -R0.H = ASHIFT R0.L BY R3.L (S); -R1.H = ASHIFT R1.L BY R3.L (S); -R2.H = ASHIFT R2.L BY R3.L (S); -//rh3 = ashift (rl3 by rl3) s; -R4.H = ASHIFT R4.L BY R3.L (S); -R5.H = ASHIFT R5.L BY R3.L (S); -R6.H = ASHIFT R6.L BY R3.L (S); -R7.H = ASHIFT R7.L BY R3.L (S); -CHECKREG r0, 0x8000f001; -CHECKREG r1, 0x8000f001; -CHECKREG r2, 0x8000f002; -//CHECKREG r3, 0x00000010; -CHECKREG r4, 0x8000f004; -CHECKREG r5, 0x8000f005; -CHECKREG r6, 0x8000f006; -CHECKREG r7, 0x8000f007; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = ASHIFT R0.H BY R0.L (S); -R1.H = ASHIFT R1.H BY R0.L (S); -R2.H = ASHIFT R2.H BY R0.L (S); -R3.H = ASHIFT R3.H BY R0.L (S); -R4.H = ASHIFT R4.H BY R0.L (S); -R5.H = ASHIFT R5.H BY R0.L (S); -R6.H = ASHIFT R6.H BY R0.L (S); -R7.H = ASHIFT R7.H BY R0.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x00020000; -CHECKREG r3, 0x00030000; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00050000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00070000; - -imm32 r0, 0xa0010000; -imm32 r1, 0x00010001; -imm32 r2, 0xa0020000; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R0.H = ASHIFT R0.H BY R1.L (S); -R1.H = ASHIFT R1.H BY R1.L (S); -R2.H = ASHIFT R2.H BY R1.L (S); -R3.H = ASHIFT R3.H BY R1.L (S); -R4.H = ASHIFT R4.H BY R1.L (S); -R5.H = ASHIFT R5.H BY R1.L (S); -R6.H = ASHIFT R6.H BY R1.L (S); -R7.H = ASHIFT R7.H BY R1.L (S); -CHECKREG r0, 0x80000000; -//CHECKREG r1, 0x80000000; -CHECKREG r2, 0x80000000; -CHECKREG r3, 0x80000000; -CHECKREG r4, 0x80000000; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x80000000; - - -imm32 r0, 0xb0010000; -imm32 r1, 0xb0010000; -imm32 r2, 0xb002000f; -imm32 r3, 0xb0030000; -imm32 r4, 0xb0040000; -imm32 r5, 0xb0050000; -imm32 r6, 0xb0060000; -imm32 r7, 0xb0070000; -R0.L = ASHIFT R0.H BY R2.L (S); -R1.L = ASHIFT R1.H BY R2.L (S); -//rl2 = ashift (rh2 by rl2); -R3.L = ASHIFT R3.H BY R2.L (S); -R4.L = ASHIFT R4.H BY R2.L (S); -R5.L = ASHIFT R5.H BY R2.L (S); -R6.L = ASHIFT R6.H BY R2.L (S); -R7.L = ASHIFT R7.H BY R2.L (S); -CHECKREG r0, 0xb0018000; -CHECKREG r1, 0xb0018000; -//CHECKREG r2, 0xb002000f; -CHECKREG r3, 0xb0038000; -CHECKREG r4, 0xb0048000; -CHECKREG r5, 0xb0058000; -CHECKREG r6, 0xb0068000; -CHECKREG r7, 0xb0078000; - -imm32 r0, 0xd0010000; -imm32 r1, 0xd0010000; -imm32 r2, 0xd0020000; -imm32 r3, 0xd0030010; -imm32 r4, 0xd0040000; -imm32 r5, 0xd0050000; -imm32 r6, 0xd0060000; -imm32 r7, 0xd0070000; -R0.H = ASHIFT R0.H BY R3.L (S); -R1.H = ASHIFT R1.H BY R3.L (S); -R2.H = ASHIFT R2.H BY R3.L (S); -R3.H = ASHIFT R3.H BY R3.L (S); -R4.H = ASHIFT R4.H BY R3.L (S); -R5.H = ASHIFT R5.H BY R3.L (S); -R6.H = ASHIFT R6.H BY R3.L (S); -R7.H = ASHIFT R7.H BY R3.L (S); -CHECKREG r0, 0x80000000; -CHECKREG r1, 0x80000000; -CHECKREG r2, 0x80000000; -CHECKREG r3, 0x80000010; -CHECKREG r4, 0x80000000; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x80000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp.s deleted file mode 100644 index ecfa5f6..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp.s +++ /dev/null @@ -1,423 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_ahalf_lp/c_dsp32shift_ahalf_lp.dsp -// Spec Reference: dsp32shift ashift half reg left positive -# mach: bfin - -.include "testutils.inc" - start - - - -// Ashift : positive data, count (+)=left (half reg) -// d_lo = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.L = ASHIFT R0.L BY R0.L; -R1.L = ASHIFT R1.L BY R0.L; -R2.L = ASHIFT R2.L BY R0.L; -R3.L = ASHIFT R3.L BY R0.L; -R4.L = ASHIFT R4.L BY R0.L; -R5.L = ASHIFT R5.L BY R0.L; -R6.L = ASHIFT R6.L BY R0.L; -R7.L = ASHIFT R7.L BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00000003; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x00000005; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x00000007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.L = ASHIFT R0.L BY R1.L; -//rl1 = ashift (rl1 by rl1); -R2.L = ASHIFT R2.L BY R1.L; -R3.L = ASHIFT R3.L BY R1.L; -R4.L = ASHIFT R4.L BY R1.L; -R5.L = ASHIFT R5.L BY R1.L; -R6.L = ASHIFT R6.L BY R1.L; -R7.L = ASHIFT R7.L BY R1.L; -CHECKREG r0, 0x00000002; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000004; -CHECKREG r3, 0x00000006; -CHECKREG r4, 0x00000008; -CHECKREG r5, 0x0000000a; -CHECKREG r6, 0x0000000c; -CHECKREG r7, 0x0000000e; - - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000000f; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.L = ASHIFT R0.L BY R2.L; -R1.L = ASHIFT R1.L BY R2.L; -//rl2 = ashift (rl2 by rl2); -R3.L = ASHIFT R3.L BY R2.L; -R4.L = ASHIFT R4.L BY R2.L; -R5.L = ASHIFT R5.L BY R2.L; -R6.L = ASHIFT R6.L BY R2.L; -R7.L = ASHIFT R7.L BY R2.L; -CHECKREG r0, 0x00008000; -CHECKREG r1, 0x00008000; -CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x00008000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00008000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00008000; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000010; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.L = ASHIFT R0.L BY R3.L; -R1.L = ASHIFT R1.L BY R3.L; -R2.L = ASHIFT R2.L BY R3.L; -//rl3 = ashift (rl3 by rl3); -R4.L = ASHIFT R4.L BY R3.L; -R5.L = ASHIFT R5.L BY R3.L; -R6.L = ASHIFT R6.L BY R3.L; -R7.L = ASHIFT R7.L BY R3.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ASHIFT R0.H BY R0.L; -R1.L = ASHIFT R1.H BY R0.L; -R2.L = ASHIFT R2.H BY R0.L; -R3.L = ASHIFT R3.H BY R0.L; -R4.L = ASHIFT R4.H BY R0.L; -R5.L = ASHIFT R5.H BY R0.L; -R6.L = ASHIFT R6.H BY R0.L; -R7.L = ASHIFT R7.H BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x00010000; -imm32 r1, 0x00010001; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ASHIFT R0.H BY R1.L; -//rl1 = ashift (rh1 by rl1); -R2.L = ASHIFT R2.H BY R1.L; -R3.L = ASHIFT R3.H BY R1.L; -R4.L = ASHIFT R4.H BY R1.L; -R5.L = ASHIFT R5.H BY R1.L; -R6.L = ASHIFT R6.H BY R1.L; -R7.L = ASHIFT R7.H BY R1.L; -CHECKREG r0, 0x00010002; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020004; -CHECKREG r3, 0x00030006; -CHECKREG r4, 0x00040008; -CHECKREG r5, 0x0005000a; -CHECKREG r6, 0x0006000c; -CHECKREG r7, 0x0007000e; - - -imm32 r0, 0x00010000; -imm32 r1, 0x00010000; -imm32 r2, 0x0002000f; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ASHIFT R0.H BY R2.L; -R1.L = ASHIFT R1.H BY R2.L; -//rl2 = ashift (rh2 by rl2); -R3.L = ASHIFT R3.H BY R2.L; -R4.L = ASHIFT R4.H BY R2.L; -R5.L = ASHIFT R5.H BY R2.L; -R6.L = ASHIFT R6.H BY R2.L; -R7.L = ASHIFT R7.H BY R2.L; -CHECKREG r0, 0x00018000; -CHECKREG r1, 0x00018000; -CHECKREG r2, 0x0002000f; -CHECKREG r3, 0x00038000; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00058000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00078000; - -imm32 r0, 0x00010001; -imm32 r1, 0x00010001; -imm32 r2, 0x00020002; -imm32 r3, 0x00030010; -imm32 r4, 0x00040004; -imm32 r5, 0x00050005; -imm32 r6, 0x00060006; -imm32 r7, 0x00070007; -R0.L = ASHIFT R0.H BY R3.L; -R1.L = ASHIFT R1.H BY R3.L; -R2.L = ASHIFT R2.H BY R3.L; -//rl3 = ashift (rh3 by rl3); -R4.L = ASHIFT R4.H BY R3.L; -R5.L = ASHIFT R5.H BY R3.L; -R6.L = ASHIFT R6.H BY R3.L; -R7.L = ASHIFT R7.H BY R3.L; -CHECKREG r0, 0x00010000; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x00020000; -CHECKREG r3, 0x00030010; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00050000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00070000; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R0.L; -R1.H = ASHIFT R1.L BY R0.L; -R2.H = ASHIFT R2.L BY R0.L; -R3.H = ASHIFT R3.L BY R0.L; -R4.H = ASHIFT R4.L BY R0.L; -R5.H = ASHIFT R5.L BY R0.L; -R6.H = ASHIFT R6.L BY R0.L; -R7.H = ASHIFT R7.L BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R1.L; -R1.H = ASHIFT R1.L BY R1.L; -R2.H = ASHIFT R2.L BY R1.L; -R3.H = ASHIFT R3.L BY R1.L; -R4.H = ASHIFT R4.L BY R1.L; -R5.H = ASHIFT R5.L BY R1.L; -R6.H = ASHIFT R6.L BY R1.L; -R7.H = ASHIFT R7.L BY R1.L; -CHECKREG r0, 0x00020001; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0x00040002; -CHECKREG r3, 0x00060003; -CHECKREG r4, 0x00080004; -CHECKREG r5, 0x000a0005; -CHECKREG r6, 0x000c0006; -CHECKREG r7, 0x000e0007; - - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000000f; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R2.L; -R1.H = ASHIFT R1.L BY R2.L; -//rh2 = ashift (rl2 by rl2); -R3.H = ASHIFT R3.L BY R2.L; -R4.H = ASHIFT R4.L BY R2.L; -R5.H = ASHIFT R5.L BY R2.L; -R6.H = ASHIFT R6.L BY R2.L; -R7.H = ASHIFT R7.L BY R2.L; -CHECKREG r0, 0x80000001; -CHECKREG r1, 0x80000001; -CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x80000003; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x80000005; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x80000007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000010; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R3.L; -R1.H = ASHIFT R1.L BY R3.L; -R2.H = ASHIFT R2.L BY R3.L; -R3.H = ASHIFT R3.L BY R3.L; -R4.H = ASHIFT R4.L BY R3.L; -R5.H = ASHIFT R5.L BY R3.L; -R6.H = ASHIFT R6.L BY R3.L; -R7.H = ASHIFT R7.L BY R3.L; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x00000005; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x00000007; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = ASHIFT R0.H BY R0.L; -R1.H = ASHIFT R1.H BY R0.L; -R2.H = ASHIFT R2.H BY R0.L; -R3.H = ASHIFT R3.H BY R0.L; -R4.H = ASHIFT R4.H BY R0.L; -R5.H = ASHIFT R5.H BY R0.L; -R6.H = ASHIFT R6.H BY R0.L; -R7.H = ASHIFT R7.H BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x00020000; -CHECKREG r3, 0x00030000; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00050000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00070000; - -imm32 r0, 0x00010000; -imm32 r1, 0x00010001; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = ASHIFT R0.H BY R1.L; -R1.H = ASHIFT R1.H BY R1.L; -R2.H = ASHIFT R2.H BY R1.L; -R3.H = ASHIFT R3.H BY R1.L; -R4.H = ASHIFT R4.H BY R1.L; -R5.H = ASHIFT R5.H BY R1.L; -R6.H = ASHIFT R6.H BY R1.L; -R7.H = ASHIFT R7.H BY R1.L; -CHECKREG r0, 0x00020000; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0x00040000; -CHECKREG r3, 0x00060000; -CHECKREG r4, 0x00080000; -CHECKREG r5, 0x000a0000; -CHECKREG r6, 0x000c0000; -CHECKREG r7, 0x000e0000; - - -imm32 r0, 0x00010000; -imm32 r1, 0x00010000; -imm32 r2, 0x0002000f; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ASHIFT R0.H BY R2.L; -R1.L = ASHIFT R1.H BY R2.L; -//rl2 = ashift (rh2 by rl2); -R3.L = ASHIFT R3.H BY R2.L; -R4.L = ASHIFT R4.H BY R2.L; -R5.L = ASHIFT R5.H BY R2.L; -R6.L = ASHIFT R6.H BY R2.L; -R7.L = ASHIFT R7.H BY R2.L; -CHECKREG r0, 0x00018000; -CHECKREG r1, 0x00018000; -CHECKREG r2, 0x0002000f; -CHECKREG r3, 0x00038000; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00058000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00078000; - -imm32 r0, 0x00010000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030010; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = ASHIFT R0.H BY R3.L; -R1.H = ASHIFT R1.H BY R3.L; -R2.H = ASHIFT R2.H BY R3.L; -R3.H = ASHIFT R3.H BY R3.L; -R4.H = ASHIFT R4.H BY R3.L; -R5.H = ASHIFT R5.H BY R3.L; -R6.H = ASHIFT R6.H BY R3.L; -R7.H = ASHIFT R7.H BY R3.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp_s.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp_s.s deleted file mode 100644 index b07eed8..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp_s.s +++ /dev/null @@ -1,423 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_ahalf_lp_s/c_dsp32shift_ahalf_lp_s.dsp -// Spec Reference: dsp32shift ashift s -# mach: bfin - -.include "testutils.inc" - start - - - -// Ashift : positive data, count (+)=left (half reg) -// d_lo = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.L = ASHIFT R0.L BY R0.L (S); -R1.L = ASHIFT R1.L BY R0.L (S); -R2.L = ASHIFT R2.L BY R0.L (S); -R3.L = ASHIFT R3.L BY R0.L (S); -R4.L = ASHIFT R4.L BY R0.L (S); -R5.L = ASHIFT R5.L BY R0.L (S); -R6.L = ASHIFT R6.L BY R0.L (S); -R7.L = ASHIFT R7.L BY R0.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00000003; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x00000005; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x00000007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.L = ASHIFT R0.L BY R1.L (S); -//rl1 = ashift (rl1 by rl1); -R2.L = ASHIFT R2.L BY R1.L (S); -R3.L = ASHIFT R3.L BY R1.L (S); -R4.L = ASHIFT R4.L BY R1.L (S); -R5.L = ASHIFT R5.L BY R1.L (S); -R6.L = ASHIFT R6.L BY R1.L (S); -R7.L = ASHIFT R7.L BY R1.L (S); -CHECKREG r0, 0x00000002; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000004; -CHECKREG r3, 0x00000006; -CHECKREG r4, 0x00000008; -CHECKREG r5, 0x0000000a; -CHECKREG r6, 0x0000000c; -CHECKREG r7, 0x0000000e; - - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000000f; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.L = ASHIFT R0.L BY R2.L (S); -R1.L = ASHIFT R1.L BY R2.L (S); -//rl2 = ashift (rl2 by rl2) s; -R3.L = ASHIFT R3.L BY R2.L (S); -R4.L = ASHIFT R4.L BY R2.L (S); -R5.L = ASHIFT R5.L BY R2.L (S); -R6.L = ASHIFT R6.L BY R2.L (S); -R7.L = ASHIFT R7.L BY R2.L (S); -CHECKREG r0, 0x00007fff; -CHECKREG r1, 0x00007fff; -CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x00007fff; -CHECKREG r4, 0x00007fff; -CHECKREG r5, 0x00007fff; -CHECKREG r6, 0x00007fff; -CHECKREG r7, 0x00007fff; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000010; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.L = ASHIFT R0.L BY R3.L (S); -R1.L = ASHIFT R1.L BY R3.L (S); -R2.L = ASHIFT R2.L BY R3.L (S); -//rl3 = ashift (rl3 by rl3) s; -R4.L = ASHIFT R4.L BY R3.L (S); -R5.L = ASHIFT R5.L BY R3.L (S); -R6.L = ASHIFT R6.L BY R3.L (S); -R7.L = ASHIFT R7.L BY R3.L (S); -CHECKREG r0, 0x00007fff; -CHECKREG r1, 0x00007fff; -CHECKREG r2, 0x00007fff; -//CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00007fff; -CHECKREG r5, 0x00007fff; -CHECKREG r6, 0x00007fff; -CHECKREG r7, 0x00007fff; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ASHIFT R0.H BY R0.L (S); -R1.L = ASHIFT R1.H BY R0.L (S); -R2.L = ASHIFT R2.H BY R0.L (S); -R3.L = ASHIFT R3.H BY R0.L (S); -R4.L = ASHIFT R4.H BY R0.L (S); -R5.L = ASHIFT R5.H BY R0.L (S); -R6.L = ASHIFT R6.H BY R0.L (S); -R7.L = ASHIFT R7.H BY R0.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x00010000; -imm32 r1, 0x00010001; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ASHIFT R0.H BY R1.L (S); -//rl1 = ashift (rh1 by rl1); -R2.L = ASHIFT R2.H BY R1.L (S); -R3.L = ASHIFT R3.H BY R1.L (S); -R4.L = ASHIFT R4.H BY R1.L (S); -R5.L = ASHIFT R5.H BY R1.L (S); -R6.L = ASHIFT R6.H BY R1.L (S); -R7.L = ASHIFT R7.H BY R1.L (S); -CHECKREG r0, 0x00010002; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020004; -CHECKREG r3, 0x00030006; -CHECKREG r4, 0x00040008; -CHECKREG r5, 0x0005000a; -CHECKREG r6, 0x0006000c; -CHECKREG r7, 0x0007000e; - - -imm32 r0, 0x00010000; -imm32 r1, 0x00010000; -imm32 r2, 0x0002000f; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ASHIFT R0.H BY R2.L (S); -R1.L = ASHIFT R1.H BY R2.L (S); -//rl2 = ashift (rh2 by rl2); -R3.L = ASHIFT R3.H BY R2.L (S); -R4.L = ASHIFT R4.H BY R2.L (S); -R5.L = ASHIFT R5.H BY R2.L (S); -R6.L = ASHIFT R6.H BY R2.L (S); -R7.L = ASHIFT R7.H BY R2.L (S); -CHECKREG r0, 0x00017fff; -CHECKREG r1, 0x00017fff; -CHECKREG r2, 0x0002000f; -CHECKREG r3, 0x00037fff; -CHECKREG r4, 0x00047fff; -CHECKREG r5, 0x00057fff; -CHECKREG r6, 0x00067fff; -CHECKREG r7, 0x00077fff; - -imm32 r0, 0x00010001; -imm32 r1, 0x00010001; -imm32 r2, 0x00020002; -imm32 r3, 0x00030010; -imm32 r4, 0x00040004; -imm32 r5, 0x00050005; -imm32 r6, 0x00060006; -imm32 r7, 0x00070007; -R0.L = ASHIFT R0.H BY R3.L (S); -R1.L = ASHIFT R1.H BY R3.L (S); -R2.L = ASHIFT R2.H BY R3.L (S); -//rl3 = ashift (rh3 by rl3) s; -R4.L = ASHIFT R4.H BY R3.L (S); -R5.L = ASHIFT R5.H BY R3.L (S); -R6.L = ASHIFT R6.H BY R3.L (S); -R7.L = ASHIFT R7.H BY R3.L (S); -CHECKREG r0, 0x00017fff; -CHECKREG r1, 0x00017fff; -CHECKREG r2, 0x00027fff; -CHECKREG r3, 0x00030010; -CHECKREG r4, 0x00047fff; -CHECKREG r5, 0x00057fff; -CHECKREG r6, 0x00067fff; -CHECKREG r7, 0x00077fff; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R0.L (S); -R1.H = ASHIFT R1.L BY R0.L (S); -R2.H = ASHIFT R2.L BY R0.L (S); -R3.H = ASHIFT R3.L BY R0.L (S); -R4.H = ASHIFT R4.L BY R0.L (S); -R5.H = ASHIFT R5.L BY R0.L (S); -R6.H = ASHIFT R6.L BY R0.L (S); -R7.H = ASHIFT R7.L BY R0.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R1.L (S); -R1.H = ASHIFT R1.L BY R1.L (S); -R2.H = ASHIFT R2.L BY R1.L (S); -R3.H = ASHIFT R3.L BY R1.L (S); -R4.H = ASHIFT R4.L BY R1.L (S); -R5.H = ASHIFT R5.L BY R1.L (S); -R6.H = ASHIFT R6.L BY R1.L (S); -R7.H = ASHIFT R7.L BY R1.L (S); -CHECKREG r0, 0x00020001; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0x00040002; -CHECKREG r3, 0x00060003; -CHECKREG r4, 0x00080004; -CHECKREG r5, 0x000a0005; -CHECKREG r6, 0x000c0006; -CHECKREG r7, 0x000e0007; - - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000000f; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R2.L (S); -R1.H = ASHIFT R1.L BY R2.L (S); -//rh2 = ashift (rl2 by rl2) s; -R3.H = ASHIFT R3.L BY R2.L (S); -R4.H = ASHIFT R4.L BY R2.L (S); -R5.H = ASHIFT R5.L BY R2.L (S); -R6.H = ASHIFT R6.L BY R2.L (S); -R7.H = ASHIFT R7.L BY R2.L (S); -CHECKREG r0, 0x7fff0001; -CHECKREG r1, 0x7fff0001; -//ECKREG(r2, 0x7fff000f); -CHECKREG r3, 0x7fff0003; -CHECKREG r4, 0x7fff0004; -CHECKREG r5, 0x7fff0005; -CHECKREG r6, 0x7fff0006; -CHECKREG r7, 0x7fff0007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000010; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R3.L (S); -R1.H = ASHIFT R1.L BY R3.L (S); -R2.H = ASHIFT R2.L BY R3.L (S); -R3.H = ASHIFT R3.L BY R3.L (S); -R4.H = ASHIFT R4.L BY R3.L (S); -R5.H = ASHIFT R5.L BY R3.L (S); -R6.H = ASHIFT R6.L BY R3.L (S); -R7.H = ASHIFT R7.L BY R3.L (S); -CHECKREG r0, 0x7fff0001; -CHECKREG r1, 0x7fff0001; -CHECKREG r2, 0x7fff0002; -CHECKREG r3, 0x7fff0010; -CHECKREG r4, 0x7fff0004; -CHECKREG r5, 0x7fff0005; -CHECKREG r6, 0x7fff0006; -CHECKREG r7, 0x7fff0007; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = ASHIFT R0.H BY R0.L (S); -R1.H = ASHIFT R1.H BY R0.L (S); -R2.H = ASHIFT R2.H BY R0.L (S); -R3.H = ASHIFT R3.H BY R0.L (S); -R4.H = ASHIFT R4.H BY R0.L (S); -R5.H = ASHIFT R5.H BY R0.L (S); -R6.H = ASHIFT R6.H BY R0.L (S); -R7.H = ASHIFT R7.H BY R0.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x00020000; -CHECKREG r3, 0x00030000; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00050000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00070000; - -imm32 r0, 0x00010000; -imm32 r1, 0x00010001; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = ASHIFT R0.H BY R1.L (S); -R1.H = ASHIFT R1.H BY R1.L (S); -R2.H = ASHIFT R2.H BY R1.L (S); -R3.H = ASHIFT R3.H BY R1.L (S); -R4.H = ASHIFT R4.H BY R1.L (S); -R5.H = ASHIFT R5.H BY R1.L (S); -R6.H = ASHIFT R6.H BY R1.L (S); -R7.H = ASHIFT R7.H BY R1.L (S); -CHECKREG r0, 0x00020000; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0x00040000; -CHECKREG r3, 0x00060000; -CHECKREG r4, 0x00080000; -CHECKREG r5, 0x000a0000; -CHECKREG r6, 0x000c0000; -CHECKREG r7, 0x000e0000; - - -imm32 r0, 0x00010000; -imm32 r1, 0x00010000; -imm32 r2, 0x0002000f; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ASHIFT R0.H BY R2.L (S); -R1.L = ASHIFT R1.H BY R2.L (S); -//rl2 = ashift (rh2 by rl2); -R3.L = ASHIFT R3.H BY R2.L (S); -R4.L = ASHIFT R4.H BY R2.L (S); -R5.L = ASHIFT R5.H BY R2.L (S); -R6.L = ASHIFT R6.H BY R2.L (S); -R7.L = ASHIFT R7.H BY R2.L (S); -CHECKREG r0, 0x00017fff; -CHECKREG r1, 0x00017fff; -//CHECKREG r2, 0x00027fff; -CHECKREG r3, 0x00037fff; -CHECKREG r4, 0x00047fff; -CHECKREG r5, 0x00057fff; -CHECKREG r6, 0x00067fff; -CHECKREG r7, 0x00077fff; - -imm32 r0, 0x00010000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030010; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = ASHIFT R0.H BY R3.L (S); -R1.H = ASHIFT R1.H BY R3.L (S); -R2.H = ASHIFT R2.H BY R3.L (S); -R3.H = ASHIFT R3.H BY R3.L (S); -R4.H = ASHIFT R4.H BY R3.L (S); -R5.H = ASHIFT R5.H BY R3.L (S); -R6.H = ASHIFT R6.H BY R3.L (S); -R7.H = ASHIFT R7.H BY R3.L (S); -CHECKREG r0, 0x7fff0000; -CHECKREG r1, 0x7fff0000; -CHECKREG r2, 0x7fff0000; -CHECKREG r3, 0x7fff0010; -CHECKREG r4, 0x7fff0000; -CHECKREG r5, 0x7fff0000; -CHECKREG r6, 0x7fff0000; -CHECKREG r7, 0x7fff0000; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn.s deleted file mode 100644 index aaa282c..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn.s +++ /dev/null @@ -1,423 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_ahalf_rn/c_dsp32shift_ahalf_rn.dsp -// Spec Reference: dsp32shift ashift -# mach: bfin - -.include "testutils.inc" - start - - - -// Ashift : positive data, count (+)=right (half reg) -// d_lo = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -R0.L = -1; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -//rl0 = ashift (rl0 by rl0); -R1.L = ASHIFT R1.L BY R0.L; -R2.L = ASHIFT R2.L BY R0.L; -R3.L = ASHIFT R3.L BY R0.L; -R4.L = ASHIFT R4.L BY R0.L; -R5.L = ASHIFT R5.L BY R0.L; -R6.L = ASHIFT R6.L BY R0.L; -R7.L = ASHIFT R7.L BY R0.L; -//CHECKREG r0, 0x00000000; -CHECKREG r1, 0x0000c000; -CHECKREG r2, 0x0000c001; -CHECKREG r3, 0x0000c001; -CHECKREG r4, 0x0000c002; -CHECKREG r5, 0x0000c002; -CHECKREG r6, 0x0000c003; -CHECKREG r7, 0x0000c003; - -imm32 r0, 0x00008001; -R1.L = -1; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = ASHIFT R0.L BY R1.L; -//rl1 = ashift (rl1 by rl1); -R2.L = ASHIFT R2.L BY R1.L; -R3.L = ASHIFT R3.L BY R1.L; -R4.L = ASHIFT R4.L BY R1.L; -R5.L = ASHIFT R5.L BY R1.L; -R6.L = ASHIFT R6.L BY R1.L; -R7.L = ASHIFT R7.L BY R1.L; -CHECKREG r0, 0x0000c000; -//CHECKREG r1, 0x00000001; -CHECKREG r2, 0x0000c001; -CHECKREG r3, 0x0000c001; -CHECKREG r4, 0x0000c002; -CHECKREG r5, 0x0000c002; -CHECKREG r6, 0x0000c003; -CHECKREG r7, 0x0000c003; - - -imm32 r0, 0x00008001; -imm32 r1, 0x00008001; -R2.L = -15; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = ASHIFT R0.L BY R2.L; -R1.L = ASHIFT R1.L BY R2.L; -//rl2 = ashift (rl2 by rl2); -R3.L = ASHIFT R3.L BY R2.L; -R4.L = ASHIFT R4.L BY R2.L; -R5.L = ASHIFT R5.L BY R2.L; -R6.L = ASHIFT R6.L BY R2.L; -R7.L = ASHIFT R7.L BY R2.L; -CHECKREG r0, 0x0000ffff; -CHECKREG r1, 0x0000ffff; -//CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x0000ffff; -CHECKREG r4, 0x0000ffff; -CHECKREG r5, 0x0000ffff; -CHECKREG r6, 0x0000ffff; -CHECKREG r7, 0x0000ffff; - -imm32 r0, 0x00008001; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -R3.L = -16; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = ASHIFT R0.L BY R3.L; -R1.L = ASHIFT R1.L BY R3.L; -R2.L = ASHIFT R2.L BY R3.L; -//rl3 = ashift (rl3 by rl3); -R4.L = ASHIFT R4.L BY R3.L; -R5.L = ASHIFT R5.L BY R3.L; -R6.L = ASHIFT R6.L BY R3.L; -R7.L = ASHIFT R7.L BY R3.L; -CHECKREG r0, 0x0000ffff; -CHECKREG r1, 0x0000ffff; -CHECKREG r2, 0x0000ffff; -//CHECKREG r3, 0x00000010; -CHECKREG r4, 0x0000ffff; -CHECKREG r5, 0x0000ffff; -CHECKREG r6, 0x0000ffff; -CHECKREG r7, 0x0000ffff; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x80010000; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -imm32 r4, 0x80040000; -imm32 r5, 0x80050000; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.L = ASHIFT R0.H BY R0.L; -R1.L = ASHIFT R1.H BY R0.L; -R2.L = ASHIFT R2.H BY R0.L; -R3.L = ASHIFT R3.H BY R0.L; -R4.L = ASHIFT R4.H BY R0.L; -R5.L = ASHIFT R5.H BY R0.L; -R6.L = ASHIFT R6.H BY R0.L; -R7.L = ASHIFT R7.H BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x80018001; -CHECKREG r2, 0x80028002; -CHECKREG r3, 0x80038003; -CHECKREG r4, 0x80048004; -CHECKREG r5, 0x80058005; -CHECKREG r6, 0x80068006; -CHECKREG r7, 0x80078007; - -imm32 r0, 0x80010000; -R1.L = -1; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -imm32 r4, 0x80040000; -imm32 r5, 0x80050000; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.L = ASHIFT R0.H BY R1.L; -//rl1 = ashift (rh1 by rl1); -R2.L = ASHIFT R2.H BY R1.L; -R3.L = ASHIFT R3.H BY R1.L; -R4.L = ASHIFT R4.H BY R1.L; -R5.L = ASHIFT R5.H BY R1.L; -R6.L = ASHIFT R6.H BY R1.L; -R7.L = ASHIFT R7.H BY R1.L; -CHECKREG r0, 0x8001c000; -//CHECKREG r1, 0x00010001; -CHECKREG r2, 0x8002c001; -CHECKREG r3, 0x8003c001; -CHECKREG r4, 0x8004c002; -CHECKREG r5, 0x8005c002; -CHECKREG r6, 0x8006c003; -CHECKREG r7, 0x8007c003; - - -imm32 r0, 0xa0010000; -imm32 r1, 0xa0010000; -R2.L = -15; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R0.L = ASHIFT R0.H BY R2.L; -R1.L = ASHIFT R1.H BY R2.L; -//rl2 = ashift (rh2 by rl2); -R3.L = ASHIFT R3.H BY R2.L; -R4.L = ASHIFT R4.H BY R2.L; -R5.L = ASHIFT R5.H BY R2.L; -R6.L = ASHIFT R6.H BY R2.L; -R7.L = ASHIFT R7.H BY R2.L; -CHECKREG r0, 0xa001ffff; -CHECKREG r1, 0xa001ffff; -//CHECKREG r2, 0x2002000f; -CHECKREG r3, 0xa003ffff; -CHECKREG r4, 0xa004ffff; -CHECKREG r5, 0xa005ffff; -CHECKREG r6, 0xa006ffff; -CHECKREG r7, 0xa007ffff; - -imm32 r0, 0xb0010001; -imm32 r1, 0xb0010001; -imm32 r2, 0xb0020002; -R3.L = -16; -imm32 r4, 0xb0040004; -imm32 r5, 0xb0050005; -imm32 r6, 0xb0060006; -imm32 r7, 0xb0070007; -R0.L = ASHIFT R0.H BY R3.L; -R1.L = ASHIFT R1.H BY R3.L; -R2.L = ASHIFT R2.H BY R3.L; -//rl3 = ashift (rh3 by rl3); -R4.L = ASHIFT R4.H BY R3.L; -R5.L = ASHIFT R5.H BY R3.L; -R6.L = ASHIFT R6.H BY R3.L; -R7.L = ASHIFT R7.H BY R3.L; -CHECKREG r0, 0xb001ffff; -CHECKREG r1, 0xb001ffff; -CHECKREG r2, 0xb002ffff; -//CHECKREG r3, 0x30030010; -CHECKREG r4, 0xb004ffff; -CHECKREG r5, 0xb005ffff; -CHECKREG r6, 0xb006ffff; -CHECKREG r7, 0xb007ffff; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000000; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R4.L; -R1.H = ASHIFT R1.L BY R4.L; -R2.H = ASHIFT R2.L BY R4.L; -R3.H = ASHIFT R3.L BY R4.L; -//rh4 = ashift (rl4 by rl4); -R5.H = ASHIFT R5.L BY R4.L; -R6.H = ASHIFT R6.L BY R4.L; -R7.H = ASHIFT R7.L BY R4.L; -CHECKREG r0, 0x00010001; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -//CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x00008001; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -R5.L = -1; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.H = ASHIFT R0.L BY R5.L; -R1.H = ASHIFT R1.L BY R5.L; -R2.H = ASHIFT R2.L BY R5.L; -R3.H = ASHIFT R3.L BY R5.L; -R4.H = ASHIFT R4.L BY R5.L; -//rh5 = ashift (rl5 by rl5); -R6.H = ASHIFT R6.L BY R5.L; -R7.H = ASHIFT R7.L BY R5.L; -CHECKREG r0, 0xc0008001; -CHECKREG r1, 0xc0008001; -CHECKREG r2, 0xc0018002; -CHECKREG r3, 0xc0018003; -CHECKREG r4, 0xc0028004; -//CHECKREG r5, 0x00020005; -CHECKREG r6, 0xc0038006; -CHECKREG r7, 0xc0038007; - - -imm32 r0, 0x00009001; -imm32 r1, 0x00009001; -imm32 r2, 0x00009002; -imm32 r3, 0x00009003; -imm32 r4, 0x00009004; -imm32 r5, 0x00009005; -R6.L = -15; -imm32 r7, 0x00009007; -R0.H = ASHIFT R0.L BY R6.L; -R1.H = ASHIFT R1.L BY R6.L; -R2.H = ASHIFT R2.L BY R6.L; -R3.H = ASHIFT R3.L BY R6.L; -R4.H = ASHIFT R4.L BY R6.L; -R5.H = ASHIFT R5.L BY R6.L; -//rh6 = ashift (rl6 by rl6); -R7.H = ASHIFT R7.L BY R6.L; -CHECKREG r0, 0xffff9001; -CHECKREG r1, 0xffff9001; -CHECKREG r2, 0xffff9002; -CHECKREG r3, 0xffff9003; -CHECKREG r4, 0xffff9004; -CHECKREG r5, 0xffff9005; -//CHECKREG r6, 0x00006006; -CHECKREG r7, 0xffff9007; - -imm32 r0, 0x0000a001; -imm32 r1, 0x0000a001; -imm32 r2, 0x0000a002; -imm32 r3, 0x0000a003; -imm32 r4, 0x0000a004; -imm32 r5, 0x0000a005; -imm32 r6, 0x0000a006; -R7.L = -16; -R0.H = ASHIFT R0.L BY R7.L; -R1.H = ASHIFT R1.L BY R7.L; -R2.H = ASHIFT R2.L BY R7.L; -R3.H = ASHIFT R3.L BY R7.L; -R4.H = ASHIFT R4.L BY R7.L; -R5.H = ASHIFT R5.L BY R7.L; -R6.H = ASHIFT R6.L BY R7.L; -R7.H = ASHIFT R7.L BY R7.L; -CHECKREG r0, 0xffffa001; -CHECKREG r1, 0xffffa001; -CHECKREG r2, 0xffffa002; -CHECKREG r3, 0xffffa003; -CHECKREG r4, 0xffffa004; -CHECKREG r5, 0xffffa005; -CHECKREG r6, 0xffffa006; -//CHECKREG r7, 0x00007007; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x80010000; -imm32 r1, 0x80010000; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -R4.L = -1; -imm32 r5, 0x80050000; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.H = ASHIFT R0.H BY R4.L; -R1.H = ASHIFT R1.H BY R4.L; -R2.H = ASHIFT R2.H BY R4.L; -R3.H = ASHIFT R3.H BY R4.L; -//rh4 = ashift (rh4 by rl4); -R5.H = ASHIFT R5.H BY R4.L; -R6.H = ASHIFT R6.H BY R4.L; -R7.H = ASHIFT R7.H BY R4.L; -CHECKREG r0, 0xc0000000; -CHECKREG r1, 0xc0000000; -CHECKREG r2, 0xc0010000; -CHECKREG r3, 0xc0010000; -//CHECKREG r4, 0x00020000; -CHECKREG r5, 0xc0020000; -CHECKREG r6, 0xc0030000; -CHECKREG r7, 0xc0030000; - -imm32 r0, 0x80010000; -imm32 r1, 0x80010000; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -imm32 r4, 0x80040000; -R5.L = -1; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.H = ASHIFT R0.H BY R5.L; -R1.H = ASHIFT R1.H BY R5.L; -R2.H = ASHIFT R2.H BY R5.L; -R3.H = ASHIFT R3.H BY R5.L; -R4.H = ASHIFT R4.H BY R5.L; -//rh5 = ashift (rh5 by rl5); -R6.H = ASHIFT R6.H BY R5.L; -R7.H = ASHIFT R7.H BY R5.L; -CHECKREG r0, 0xc0000000; -CHECKREG r1, 0xc0000000; -CHECKREG r2, 0xc0010000; -CHECKREG r3, 0xc0010000; -CHECKREG r4, 0xc0020000; -//CHECKREG r5, 0x28020000; -CHECKREG r6, 0xc0030000; -CHECKREG r7, 0xc0030000; - - -imm32 r0, 0xd0010000; -imm32 r1, 0xd0010000; -imm32 r2, 0xd0020000; -imm32 r3, 0xd0030000; -imm32 r4, 0xd0040000; -imm32 r5, 0xd0050000; -R6.L = -15; -imm32 r7, 0xd0070000; -R0.L = ASHIFT R0.H BY R6.L; -R1.L = ASHIFT R1.H BY R6.L; -R2.L = ASHIFT R2.H BY R6.L; -R3.L = ASHIFT R3.H BY R6.L; -R4.L = ASHIFT R4.H BY R6.L; -R5.L = ASHIFT R5.H BY R6.L; -//rl6 = ashift (rh6 by rl6); -R7.L = ASHIFT R7.H BY R6.L; -CHECKREG r0, 0xd001ffff; -CHECKREG r1, 0xd001ffff; -CHECKREG r2, 0xd002ffff; -CHECKREG r3, 0xd003ffff; -CHECKREG r4, 0xd004ffff; -CHECKREG r5, 0xd005ffff; -//CHECKREG r6, 0x60060000; -CHECKREG r7, 0xd007ffff; - -imm32 r0, 0xe0010000; -imm32 r1, 0xe0010000; -imm32 r2, 0xe0020000; -imm32 r3, 0xe0030000; -imm32 r4, 0xe0040000; -imm32 r5, 0xe0050000; -imm32 r6, 0xe0060000; -R7.L = -16; -R0.H = ASHIFT R0.H BY R7.L; -R1.H = ASHIFT R1.H BY R7.L; -R2.H = ASHIFT R2.H BY R7.L; -R3.H = ASHIFT R3.H BY R7.L; -R4.H = ASHIFT R4.H BY R7.L; -R5.H = ASHIFT R5.H BY R7.L; -R6.H = ASHIFT R6.H BY R7.L; -//rh7 = ashift (rh7 by rl7); -CHECKREG r0, 0xffff0000; -CHECKREG r1, 0xffff0000; -CHECKREG r2, 0xffff0000; -CHECKREG r3, 0xffff0000; -CHECKREG r4, 0xffff0000; -CHECKREG r5, 0xffff0000; -CHECKREG r6, 0xffff0000; -//CHECKREG r7, -16; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn_s.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn_s.s deleted file mode 100644 index 503671e..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn_s.s +++ /dev/null @@ -1,424 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_ahalf_rn_s/c_dsp32shift_ahalf_rn_s.dsp -// Spec Reference: dsp32shift ashift s -# mach: bfin - -.include "testutils.inc" - start - - - -// Ashift : positive data, count (+)=left (half reg) -// d_lo = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -R0.L = -1; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -//rl0 = ashift (rl0 by rl0); -R1.L = ASHIFT R1.L BY R0.L (S); -R2.L = ASHIFT R2.L BY R0.L (S); -R3.L = ASHIFT R3.L BY R0.L (S); -R4.L = ASHIFT R4.L BY R0.L (S); -R5.L = ASHIFT R5.L BY R0.L (S); -R6.L = ASHIFT R6.L BY R0.L (S); -R7.L = ASHIFT R7.L BY R0.L (S); -//CHECKREG r0, 0x00000000; -CHECKREG r1, 0x0000c000; -CHECKREG r2, 0x0000c001; -CHECKREG r3, 0x0000c001; -CHECKREG r4, 0x0000c002; -CHECKREG r5, 0x0000c002; -CHECKREG r6, 0x0000c003; -CHECKREG r7, 0x0000c003; - -imm32 r0, 0x00008001; -R1.L = -1; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = ASHIFT R0.L BY R1.L (S); -//rl1 = ashift (rl1 by rl1); -R2.L = ASHIFT R2.L BY R1.L (S); -R3.L = ASHIFT R3.L BY R1.L (S); -R4.L = ASHIFT R4.L BY R1.L (S); -R5.L = ASHIFT R5.L BY R1.L (S); -R6.L = ASHIFT R6.L BY R1.L (S); -R7.L = ASHIFT R7.L BY R1.L (S); -CHECKREG r0, 0x0000c000; -//CHECKREG r1, 0x00000001; -CHECKREG r2, 0x0000c001; -CHECKREG r3, 0x0000c001; -CHECKREG r4, 0x0000c002; -CHECKREG r5, 0x0000c002; -CHECKREG r6, 0x0000c003; -CHECKREG r7, 0x0000c003; - - -imm32 r0, 0x00008001; -imm32 r1, 0x00008001; -R2.L = -15; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = ASHIFT R0.L BY R2.L (S); -R1.L = ASHIFT R1.L BY R2.L (S); -//rl2 = ashift (rl2 by rl2); -R3.L = ASHIFT R3.L BY R2.L (S); -R4.L = ASHIFT R4.L BY R2.L (S); -R5.L = ASHIFT R5.L BY R2.L (S); -R6.L = ASHIFT R6.L BY R2.L (S); -R7.L = ASHIFT R7.L BY R2.L (S); -CHECKREG r0, 0x0000ffff; -CHECKREG r1, 0x0000ffff; -//CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x0000ffff; -CHECKREG r4, 0x0000ffff; -CHECKREG r5, 0x0000ffff; -CHECKREG r6, 0x0000ffff; -CHECKREG r7, 0x0000ffff; - -imm32 r0, 0x00008001; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -R3.L = -16; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = ASHIFT R0.L BY R3.L (S); -R1.L = ASHIFT R1.L BY R3.L (S); -R2.L = ASHIFT R2.L BY R3.L (S); -//rl3 = ashift (rl3 by rl3); -R4.L = ASHIFT R4.L BY R3.L (S); -R5.L = ASHIFT R5.L BY R3.L (S); -R6.L = ASHIFT R6.L BY R3.L (S); -R7.L = ASHIFT R7.L BY R3.L (S); -CHECKREG r0, 0x0000ffff; -CHECKREG r1, 0x0000ffff; -CHECKREG r2, 0x0000ffff; -//CHECKREG r3, 0x00000010; -CHECKREG r4, 0x0000ffff; -CHECKREG r5, 0x0000ffff; -CHECKREG r6, 0x0000ffff; -CHECKREG r7, 0x0000ffff; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x80010000; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -imm32 r4, 0x80040000; -imm32 r5, 0x80050000; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.L = ASHIFT R0.H BY R0.L (S); -R1.L = ASHIFT R1.H BY R0.L (S); -R2.L = ASHIFT R2.H BY R0.L (S); -R3.L = ASHIFT R3.H BY R0.L (S); -R4.L = ASHIFT R4.H BY R0.L (S); -R5.L = ASHIFT R5.H BY R0.L (S); -R6.L = ASHIFT R6.H BY R0.L (S); -R7.L = ASHIFT R7.H BY R0.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x80018001; -CHECKREG r2, 0x80028002; -CHECKREG r3, 0x80038003; -CHECKREG r4, 0x80048004; -CHECKREG r5, 0x80058005; -CHECKREG r6, 0x80068006; -CHECKREG r7, 0x80078007; - -imm32 r0, 0x80010000; -R1.L = -1; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -imm32 r4, 0x80040000; -imm32 r5, 0x80050000; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.L = ASHIFT R0.H BY R1.L (S); -//rl1 = ashift (rh1 by rl1); -R2.L = ASHIFT R2.H BY R1.L (S); -R3.L = ASHIFT R3.H BY R1.L (S); -R4.L = ASHIFT R4.H BY R1.L (S); -R5.L = ASHIFT R5.H BY R1.L (S); -R6.L = ASHIFT R6.H BY R1.L (S); -R7.L = ASHIFT R7.H BY R1.L (S); -CHECKREG r0, 0x8001c000; -//CHECKREG r1, 0x00010001; -CHECKREG r2, 0x8002c001; -CHECKREG r3, 0x8003c001; -CHECKREG r4, 0x8004c002; -CHECKREG r5, 0x8005c002; -CHECKREG r6, 0x8006c003; -CHECKREG r7, 0x8007c003; - - -imm32 r0, 0xa0010000; -imm32 r1, 0xa0010000; -R2.L = -15; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R0.L = ASHIFT R0.H BY R2.L (S); -R1.L = ASHIFT R1.H BY R2.L (S); -//rl2 = ashift (rh2 by rl2); -R3.L = ASHIFT R3.H BY R2.L (S); -R4.L = ASHIFT R4.H BY R2.L (S); -R5.L = ASHIFT R5.H BY R2.L (S); -R6.L = ASHIFT R6.H BY R2.L (S); -R7.L = ASHIFT R7.H BY R2.L (S); -CHECKREG r0, 0xa001ffff; -CHECKREG r1, 0xa001ffff; -//CHECKREG r2, 0x2002000f; -CHECKREG r3, 0xa003ffff; -CHECKREG r4, 0xa004ffff; -CHECKREG r5, 0xa005ffff; -CHECKREG r6, 0xa006ffff; -CHECKREG r7, 0xa007ffff; - -imm32 r0, 0xb0010001; -imm32 r1, 0xb0010001; -imm32 r2, 0xb0020002; -R3.L = -16; -imm32 r4, 0xb0040004; -imm32 r5, 0xb0050005; -imm32 r6, 0xb0060006; -imm32 r7, 0xb0070007; -R0.L = ASHIFT R0.H BY R3.L (S); -R1.L = ASHIFT R1.H BY R3.L (S); -R2.L = ASHIFT R2.H BY R3.L (S); -//rl3 = ashift (rh3 by rl3); -R4.L = ASHIFT R4.H BY R3.L (S); -R5.L = ASHIFT R5.H BY R3.L (S); -R6.L = ASHIFT R6.H BY R3.L (S); -R7.L = ASHIFT R7.H BY R3.L (S); -CHECKREG r0, 0xb001ffff; -CHECKREG r1, 0xb001ffff; -CHECKREG r2, 0xb002ffff; -//CHECKREG r3, 0x30030010; -CHECKREG r4, 0xb004ffff; -CHECKREG r5, 0xb005ffff; -CHECKREG r6, 0xb006ffff; -CHECKREG r7, 0xb007ffff; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000000; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R4.L (S); -R1.H = ASHIFT R1.L BY R4.L (S); -R2.H = ASHIFT R2.L BY R4.L (S); -R3.H = ASHIFT R3.L BY R4.L (S); -//rh4 = ashift (rl4 by rl4); -R5.H = ASHIFT R5.L BY R4.L (S); -R6.H = ASHIFT R6.L BY R4.L (S); -R7.H = ASHIFT R7.L BY R4.L (S); -CHECKREG r0, 0x00010001; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -//CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x00008001; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -R5.L = -1; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.H = ASHIFT R0.L BY R5.L (S); -R1.H = ASHIFT R1.L BY R5.L (S); -R2.H = ASHIFT R2.L BY R5.L (S); -R3.H = ASHIFT R3.L BY R5.L (S); -R4.H = ASHIFT R4.L BY R5.L (S); -//rh5 = ashift (rl5 by rl5); -R6.H = ASHIFT R6.L BY R5.L (S); -R7.H = ASHIFT R7.L BY R5.L (S); -CHECKREG r0, 0xc0008001; -CHECKREG r1, 0xc0008001; -CHECKREG r2, 0xc0018002; -CHECKREG r3, 0xc0018003; -CHECKREG r4, 0xc0028004; -//CHECKREG r5, 0x00020005; -CHECKREG r6, 0xc0038006; -CHECKREG r7, 0xc0038007; - - -imm32 r0, 0x00009001; -imm32 r1, 0x00009001; -imm32 r2, 0x00009002; -imm32 r3, 0x00009003; -imm32 r4, 0x00009004; -imm32 r5, 0x00009005; -R6.L = -15; -imm32 r7, 0x00009007; -R0.H = ASHIFT R0.L BY R6.L (S); -R1.H = ASHIFT R1.L BY R6.L (S); -R2.H = ASHIFT R2.L BY R6.L (S); -R3.H = ASHIFT R3.L BY R6.L (S); -R4.H = ASHIFT R4.L BY R6.L (S); -R5.H = ASHIFT R5.L BY R6.L (S); -//rh6 = ashift (rl6 by rl6); -R7.H = ASHIFT R7.L BY R6.L; -CHECKREG r0, 0xffff9001; -CHECKREG r1, 0xffff9001; -CHECKREG r2, 0xffff9002; -CHECKREG r3, 0xffff9003; -CHECKREG r4, 0xffff9004; -CHECKREG r5, 0xffff9005; -//CHECKREG r6, 0x00006006; -CHECKREG r7, 0xffff9007; - -imm32 r0, 0x0000a001; -imm32 r1, 0x0000a001; -imm32 r2, 0x0000a002; -imm32 r3, 0x0000a003; -imm32 r4, 0x0000a004; -imm32 r5, 0x0000a005; -imm32 r6, 0x0000a006; -R7.L = -16; -R0.H = ASHIFT R0.L BY R7.L (S); -R1.H = ASHIFT R1.L BY R7.L (S); -R2.H = ASHIFT R2.L BY R7.L (S); -R3.H = ASHIFT R3.L BY R7.L (S); -R4.H = ASHIFT R4.L BY R7.L (S); -R5.H = ASHIFT R5.L BY R7.L (S); -R6.H = ASHIFT R6.L BY R7.L (S); -R7.H = ASHIFT R7.L BY R7.L (S); -CHECKREG r0, 0xffffa001; -CHECKREG r1, 0xffffa001; -CHECKREG r2, 0xffffa002; -CHECKREG r3, 0xffffa003; -CHECKREG r4, 0xffffa004; -CHECKREG r5, 0xffffa005; -CHECKREG r6, 0xffffa006; -//CHECKREG r7, 0x00007007; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x80010000; -imm32 r1, 0x80010000; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -R4.L = -1; -imm32 r5, 0x80050000; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.H = ASHIFT R0.H BY R4.L (S); -R1.H = ASHIFT R1.H BY R4.L (S); -R2.H = ASHIFT R2.H BY R4.L (S); -R3.H = ASHIFT R3.H BY R4.L (S); -//rh4 = ashift (rh4 by rl4); -R5.H = ASHIFT R5.H BY R4.L (S); -R6.H = ASHIFT R6.H BY R4.L (S); -R7.H = ASHIFT R7.H BY R4.L (S); -CHECKREG r0, 0xc0000000; -CHECKREG r1, 0xc0000000; -CHECKREG r2, 0xc0010000; -CHECKREG r3, 0xc0010000; -//CHECKREG r4, 0x00020000; -CHECKREG r5, 0xc0020000; -CHECKREG r6, 0xc0030000; -CHECKREG r7, 0xc0030000; - -imm32 r0, 0x80010000; -imm32 r1, 0x80010000; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -imm32 r4, 0x80040000; -R5.L = -1; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.H = ASHIFT R0.H BY R5.L (S); -R1.H = ASHIFT R1.H BY R5.L (S); -R2.H = ASHIFT R2.H BY R5.L (S); -R3.H = ASHIFT R3.H BY R5.L (S); -R4.H = ASHIFT R4.H BY R5.L (S); -//rh5 = ashift (rh5 by rl5); -R6.H = ASHIFT R6.H BY R5.L (S); -R7.H = ASHIFT R7.H BY R5.L (S); -CHECKREG r0, 0xc0000000; -CHECKREG r1, 0xc0000000; -CHECKREG r2, 0xc0010000; -CHECKREG r3, 0xc0010000; -CHECKREG r4, 0xc0020000; -//CHECKREG r5, 0x28020000; -CHECKREG r6, 0xc0030000; -CHECKREG r7, 0xc0030000; - - -imm32 r0, 0xd0010000; -imm32 r1, 0xd0010000; -imm32 r2, 0xd0020000; -imm32 r3, 0xd0030000; -imm32 r4, 0xd0040000; -imm32 r5, 0xd0050000; -R6.L = -15; -imm32 r7, 0xd0070000; -R0.L = ASHIFT R0.H BY R6.L (S); -R1.L = ASHIFT R1.H BY R6.L (S); -R2.L = ASHIFT R2.H BY R6.L (S); -R3.L = ASHIFT R3.H BY R6.L (S); -R4.L = ASHIFT R4.H BY R6.L (S); -R5.L = ASHIFT R5.H BY R6.L (S); -//rl6 = ashift (rh6 by rl6); -R7.L = ASHIFT R7.H BY R6.L; -CHECKREG r0, 0xd001ffff; -CHECKREG r1, 0xd001ffff; -CHECKREG r2, 0xd002ffff; -CHECKREG r3, 0xd003ffff; -CHECKREG r4, 0xd004ffff; -CHECKREG r5, 0xd005ffff; -//CHECKREG r6, 0x60060000; -CHECKREG r7, 0xd007ffff; - -imm32 r0, 0xe0010000; -imm32 r1, 0xe0010000; -imm32 r2, 0xe0020000; -imm32 r3, 0xe0030000; -imm32 r4, 0xe0040000; -imm32 r5, 0xe0050000; -imm32 r6, 0xe0060000; -R7.L = -16; -R0.H = ASHIFT R0.H BY R7.L (S); -R1.H = ASHIFT R1.H BY R7.L (S); -R2.H = ASHIFT R2.H BY R7.L (S); -R3.H = ASHIFT R3.H BY R7.L (S); -R4.H = ASHIFT R4.H BY R7.L (S); -R5.H = ASHIFT R5.H BY R7.L (S); -R6.H = ASHIFT R6.H BY R7.L (S); -//rh7 = ashift (rh7 by rl7); -CHECKREG r0, 0xffff0000; -CHECKREG r1, 0xffff0000; -CHECKREG r2, 0xffff0000; -CHECKREG r3, 0xffff0000; -CHECKREG r4, 0xffff0000; -CHECKREG r5, 0xffff0000; -CHECKREG r6, 0xffff0000; -//CHECKREG r7, -16; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp.s deleted file mode 100644 index e3480d5..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp.s +++ /dev/null @@ -1,423 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_ahalf_rp/c_dsp32shift_ahalf_rp.dsp -// Spec Reference: dsp32shift ashift -# mach: bfin - -.include "testutils.inc" - start - - - -// Ashift : positive data, count (+)=right (half reg) -// d_lo = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -R0.L = -1; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -//rl0 = ashift (rl0 by rl0); -R1.L = ASHIFT R1.L BY R0.L; -R2.L = ASHIFT R2.L BY R0.L; -R3.L = ASHIFT R3.L BY R0.L; -R4.L = ASHIFT R4.L BY R0.L; -R5.L = ASHIFT R5.L BY R0.L; -R6.L = ASHIFT R6.L BY R0.L; -R7.L = ASHIFT R7.L BY R0.L; -//CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000002; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000003; -CHECKREG r7, 0x00000003; - -imm32 r0, 0x00001001; -R1.L = -1; -imm32 r2, 0x00002002; -imm32 r3, 0x00003003; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -imm32 r6, 0x00006006; -imm32 r7, 0x00007007; -R0.L = ASHIFT R0.L BY R1.L; -//rl1 = ashift (rl1 by rl1); -R2.L = ASHIFT R2.L BY R1.L; -R3.L = ASHIFT R3.L BY R1.L; -R4.L = ASHIFT R4.L BY R1.L; -R5.L = ASHIFT R5.L BY R1.L; -R6.L = ASHIFT R6.L BY R1.L; -R7.L = ASHIFT R7.L BY R1.L; -CHECKREG r0, 0x00000800; -//CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00001001; -CHECKREG r3, 0x00001801; -CHECKREG r4, 0x00002002; -CHECKREG r5, 0x00002802; -CHECKREG r6, 0x00003003; -CHECKREG r7, 0x00003803; - - -imm32 r0, 0x00001001; -imm32 r1, 0x00001001; -R2.L = -15; -imm32 r3, 0x00003003; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -imm32 r6, 0x00006006; -imm32 r7, 0x00007007; -R0.L = ASHIFT R0.L BY R2.L; -R1.L = ASHIFT R1.L BY R2.L; -//rl2 = ashift (rl2 by rl2); -R3.L = ASHIFT R3.L BY R2.L; -R4.L = ASHIFT R4.L BY R2.L; -R5.L = ASHIFT R5.L BY R2.L; -R6.L = ASHIFT R6.L BY R2.L; -R7.L = ASHIFT R7.L BY R2.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -//CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x00001001; -imm32 r1, 0x00001001; -imm32 r2, 0x00002002; -R3.L = -16; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -imm32 r6, 0x00006006; -imm32 r7, 0x00007007; -R0.L = ASHIFT R0.L BY R3.L; -R1.L = ASHIFT R1.L BY R3.L; -R2.L = ASHIFT R2.L BY R3.L; -//rl3 = ashift (rl3 by rl3); -R4.L = ASHIFT R4.L BY R3.L; -R5.L = ASHIFT R5.L BY R3.L; -R6.L = ASHIFT R6.L BY R3.L; -R7.L = ASHIFT R7.L BY R3.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -//CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ASHIFT R0.H BY R0.L; -R1.L = ASHIFT R1.H BY R0.L; -R2.L = ASHIFT R2.H BY R0.L; -R3.L = ASHIFT R3.H BY R0.L; -R4.L = ASHIFT R4.H BY R0.L; -R5.L = ASHIFT R5.H BY R0.L; -R6.L = ASHIFT R6.H BY R0.L; -R7.L = ASHIFT R7.H BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x10010000; -R1.L = -1; -imm32 r2, 0x20020000; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -imm32 r6, 0x60060000; -imm32 r7, 0x70070000; -R0.L = ASHIFT R0.H BY R1.L; -//rl1 = ashift (rh1 by rl1); -R2.L = ASHIFT R2.H BY R1.L; -R3.L = ASHIFT R3.H BY R1.L; -R4.L = ASHIFT R4.H BY R1.L; -R5.L = ASHIFT R5.H BY R1.L; -R6.L = ASHIFT R6.H BY R1.L; -R7.L = ASHIFT R7.H BY R1.L; -CHECKREG r0, 0x10010800; -//CHECKREG r1, 0x00010001; -CHECKREG r2, 0x20021001; -CHECKREG r3, 0x30031801; -CHECKREG r4, 0x40042002; -CHECKREG r5, 0x50052802; -CHECKREG r6, 0x60063003; -CHECKREG r7, 0x70073803; - - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -R2.L = -15; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -imm32 r6, 0x60060000; -imm32 r7, 0x70070000; -R0.L = ASHIFT R0.H BY R2.L; -R1.L = ASHIFT R1.H BY R2.L; -//rl2 = ashift (rh2 by rl2); -R3.L = ASHIFT R3.H BY R2.L; -R4.L = ASHIFT R4.H BY R2.L; -R5.L = ASHIFT R5.H BY R2.L; -R6.L = ASHIFT R6.H BY R2.L; -R7.L = ASHIFT R7.H BY R2.L; -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -//CHECKREG r2, 0x2002000f; -CHECKREG r3, 0x30030000; -CHECKREG r4, 0x40040000; -CHECKREG r5, 0x50050000; -CHECKREG r6, 0x60060000; -CHECKREG r7, 0x70070000; - -imm32 r0, 0x10010001; -imm32 r1, 0x10010001; -imm32 r2, 0x20020002; -R3.L = -16; -imm32 r4, 0x40040004; -imm32 r5, 0x50050005; -imm32 r6, 0x60060006; -imm32 r7, 0x70070007; -R0.L = ASHIFT R0.H BY R3.L; -R1.L = ASHIFT R1.H BY R3.L; -R2.L = ASHIFT R2.H BY R3.L; -//rl3 = ashift (rh3 by rl3); -R4.L = ASHIFT R4.H BY R3.L; -R5.L = ASHIFT R5.H BY R3.L; -R6.L = ASHIFT R6.H BY R3.L; -R7.L = ASHIFT R7.H BY R3.L; -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -CHECKREG r2, 0x20020000; -//CHECKREG r3, 0x30030010; -CHECKREG r4, 0x40040000; -CHECKREG r5, 0x50050000; -CHECKREG r6, 0x60060000; -CHECKREG r7, 0x70070000; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000000; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R4.L; -R1.H = ASHIFT R1.L BY R4.L; -R2.H = ASHIFT R2.L BY R4.L; -R3.H = ASHIFT R3.L BY R4.L; -//rh4 = ashift (rl4 by rl4); -R5.H = ASHIFT R5.L BY R4.L; -R6.H = ASHIFT R6.L BY R4.L; -R7.H = ASHIFT R7.L BY R4.L; -CHECKREG r0, 0x00010001; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -//CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -R5.L = -1; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R5.L; -R1.H = ASHIFT R1.L BY R5.L; -R2.H = ASHIFT R2.L BY R5.L; -R3.H = ASHIFT R3.L BY R5.L; -R4.H = ASHIFT R4.L BY R5.L; -//rh5 = ashift (rl5 by rl5); -R6.H = ASHIFT R6.L BY R5.L; -R7.H = ASHIFT R7.L BY R5.L; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00010002; -CHECKREG r3, 0x00010003; -CHECKREG r4, 0x00020004; -//CHECKREG r5, 0x00020005; -CHECKREG r6, 0x00030006; -CHECKREG r7, 0x00030007; - - -imm32 r0, 0x00001001; -imm32 r1, 0x00001001; -imm32 r1, 0x00002002; -imm32 r3, 0x00003003; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -R6.L = -15; -imm32 r7, 0x00007007; -R0.H = ASHIFT R0.L BY R6.L; -R1.H = ASHIFT R1.L BY R6.L; -R2.H = ASHIFT R2.L BY R6.L; -R3.H = ASHIFT R3.L BY R6.L; -R4.H = ASHIFT R4.L BY R6.L; -R5.H = ASHIFT R5.L BY R6.L; -//rh6 = ashift (rl6 by rl6); -R7.H = ASHIFT R7.L BY R6.L; -CHECKREG r0, 0x00001001; -CHECKREG r1, 0x00002002; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00003003; -CHECKREG r4, 0x00004004; -CHECKREG r5, 0x00005005; -//CHECKREG r6, 0x00006006; -CHECKREG r7, 0x00007007; - -imm32 r0, 0x00001001; -imm32 r1, 0x00002001; -imm32 r2, 0x00002002; -imm32 r3, 0x00003003; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -imm32 r6, 0x00006006; -R7.L = -16; -R0.H = ASHIFT R0.L BY R7.L; -R1.H = ASHIFT R1.L BY R7.L; -R2.H = ASHIFT R2.L BY R7.L; -R3.H = ASHIFT R3.L BY R7.L; -R4.H = ASHIFT R4.L BY R7.L; -R5.H = ASHIFT R5.L BY R7.L; -R6.H = ASHIFT R6.L BY R7.L; -R7.H = ASHIFT R7.L BY R7.L; -CHECKREG r0, 0x00001001; -CHECKREG r1, 0x00002001; -CHECKREG r2, 0x00002002; -CHECKREG r3, 0x00003003; -CHECKREG r4, 0x00004004; -CHECKREG r5, 0x00005005; -CHECKREG r6, 0x00006006; -//CHECKREG r7, 0x00007007; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00010000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -R4.L = -1; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = ASHIFT R0.H BY R4.L; -R1.H = ASHIFT R1.H BY R4.L; -R2.H = ASHIFT R2.H BY R4.L; -R3.H = ASHIFT R3.H BY R4.L; -//rh4 = ashift (rh4 by rl4); -R5.H = ASHIFT R5.H BY R4.L; -R6.H = ASHIFT R6.H BY R4.L; -R7.H = ASHIFT R7.H BY R4.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00010000; -CHECKREG r3, 0x00010000; -//CHECKREG r4, 0x00020000; -CHECKREG r5, 0x00020000; -CHECKREG r6, 0x00030000; -CHECKREG r7, 0x00030000; - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -imm32 r2, 0x20020000; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -R5.L = -1; -imm32 r6, 0x60060000; -imm32 r7, 0x70070000; -R0.H = ASHIFT R0.H BY R5.L; -R1.H = ASHIFT R1.H BY R5.L; -R2.H = ASHIFT R2.H BY R5.L; -R3.H = ASHIFT R3.H BY R5.L; -R4.H = ASHIFT R4.H BY R5.L; -//rh5 = ashift (rh5 by rl5); -R6.H = ASHIFT R6.H BY R5.L; -R7.H = ASHIFT R7.H BY R5.L; -CHECKREG r0, 0x08000000; -CHECKREG r1, 0x08000000; -CHECKREG r2, 0x10010000; -CHECKREG r3, 0x18010000; -CHECKREG r4, 0x20020000; -//CHECKREG r5, 0x28020000; -CHECKREG r6, 0x30030000; -CHECKREG r7, 0x38030000; - - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -imm32 r2, 0x20020000; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -R6.L = -15; -imm32 r7, 0x70070000; -R0.L = ASHIFT R0.H BY R6.L; -R1.L = ASHIFT R1.H BY R6.L; -R2.L = ASHIFT R2.H BY R6.L; -R3.L = ASHIFT R3.H BY R6.L; -R4.L = ASHIFT R4.H BY R6.L; -R5.L = ASHIFT R5.H BY R6.L; -//rl6 = ashift (rh6 by rl6); -R7.L = ASHIFT R7.H BY R6.L; -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -CHECKREG r2, 0x20020000; -CHECKREG r3, 0x30030000; -CHECKREG r4, 0x40040000; -CHECKREG r5, 0x50050000; -//CHECKREG r6, 0x60060000; -CHECKREG r7, 0x70070000; - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -imm32 r2, 0x20020000; -imm32 r2, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -imm32 r6, 0x60060000; -R7.L = -16; -R0.H = ASHIFT R0.H BY R7.L; -R1.H = ASHIFT R1.H BY R7.L; -R2.H = ASHIFT R2.H BY R7.L; -R3.H = ASHIFT R3.H BY R7.L; -R4.H = ASHIFT R4.H BY R7.L; -R5.H = ASHIFT R5.H BY R7.L; -R6.H = ASHIFT R6.H BY R7.L; -//rh7 = ashift (rh7 by rl7); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -//CHECKREG r7, -16; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp_s.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp_s.s deleted file mode 100644 index 3e467f2..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp_s.s +++ /dev/null @@ -1,423 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_ahalf_rp_s/c_dsp32shift_ahalf_rp_s.dsp -// Spec Reference: dsp32shift ashift -# mach: bfin - -.include "testutils.inc" - start - - - -// Ashift : positive data, count (+)=left (half reg) -// d_lo = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -R0.L = -1; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -//rl0 = ashift (rl0 by rl0); -R1.L = ASHIFT R1.L BY R0.L (S); -R2.L = ASHIFT R2.L BY R0.L (S); -R3.L = ASHIFT R3.L BY R0.L (S); -R4.L = ASHIFT R4.L BY R0.L (S); -R5.L = ASHIFT R5.L BY R0.L (S); -R6.L = ASHIFT R6.L BY R0.L (S); -R7.L = ASHIFT R7.L BY R0.L (S); -//CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000002; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000003; -CHECKREG r7, 0x00000003; - -imm32 r0, 0x00001001; -R1.L = -1; -imm32 r2, 0x00002002; -imm32 r3, 0x00003003; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -imm32 r6, 0x00006006; -imm32 r7, 0x00007007; -R0.L = ASHIFT R0.L BY R1.L (S); -//rl1 = ashift (rl1 by rl1); -R2.L = ASHIFT R2.L BY R1.L (S); -R3.L = ASHIFT R3.L BY R1.L (S); -R4.L = ASHIFT R4.L BY R1.L (S); -R5.L = ASHIFT R5.L BY R1.L (S); -R6.L = ASHIFT R6.L BY R1.L (S); -R7.L = ASHIFT R7.L BY R1.L (S); -CHECKREG r0, 0x00000800; -//CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00001001; -CHECKREG r3, 0x00001801; -CHECKREG r4, 0x00002002; -CHECKREG r5, 0x00002802; -CHECKREG r6, 0x00003003; -CHECKREG r7, 0x00003803; - - -imm32 r0, 0x00001001; -imm32 r1, 0x00001001; -R2.L = -15; -imm32 r3, 0x00003003; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -imm32 r6, 0x00006006; -imm32 r7, 0x00007007; -R0.L = ASHIFT R0.L BY R2.L (S); -R1.L = ASHIFT R1.L BY R2.L (S); -//rl2 = ashift (rl2 by rl2); -R3.L = ASHIFT R3.L BY R2.L (S); -R4.L = ASHIFT R4.L BY R2.L (S); -R5.L = ASHIFT R5.L BY R2.L (S); -R6.L = ASHIFT R6.L BY R2.L (S); -R7.L = ASHIFT R7.L BY R2.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -//CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x00001001; -imm32 r1, 0x00001001; -imm32 r2, 0x00002002; -R3.L = -16; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -imm32 r6, 0x00006006; -imm32 r7, 0x00007007; -R0.L = ASHIFT R0.L BY R3.L (S); -R1.L = ASHIFT R1.L BY R3.L (S); -R2.L = ASHIFT R2.L BY R3.L (S); -//rl3 = ashift (rl3 by rl3); -R4.L = ASHIFT R4.L BY R3.L (S); -R5.L = ASHIFT R5.L BY R3.L (S); -R6.L = ASHIFT R6.L BY R3.L (S); -R7.L = ASHIFT R7.L BY R3.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -//CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ASHIFT R0.H BY R0.L (S); -R1.L = ASHIFT R1.H BY R0.L (S); -R2.L = ASHIFT R2.H BY R0.L (S); -R3.L = ASHIFT R3.H BY R0.L (S); -R4.L = ASHIFT R4.H BY R0.L (S); -R5.L = ASHIFT R5.H BY R0.L (S); -R6.L = ASHIFT R6.H BY R0.L (S); -R7.L = ASHIFT R7.H BY R0.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x10010000; -R1.L = -1; -imm32 r2, 0x20020000; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -imm32 r6, 0x60060000; -imm32 r7, 0x70070000; -R0.L = ASHIFT R0.H BY R1.L (S); -//rl1 = ashift (rh1 by rl1); -R2.L = ASHIFT R2.H BY R1.L (S); -R3.L = ASHIFT R3.H BY R1.L (S); -R4.L = ASHIFT R4.H BY R1.L (S); -R5.L = ASHIFT R5.H BY R1.L (S); -R6.L = ASHIFT R6.H BY R1.L (S); -R7.L = ASHIFT R7.H BY R1.L (S); -CHECKREG r0, 0x10010800; -//CHECKREG r1, 0x00010001; -CHECKREG r2, 0x20021001; -CHECKREG r3, 0x30031801; -CHECKREG r4, 0x40042002; -CHECKREG r5, 0x50052802; -CHECKREG r6, 0x60063003; -CHECKREG r7, 0x70073803; - - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -R2.L = -15; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -imm32 r6, 0x60060000; -imm32 r7, 0x70070000; -R0.L = ASHIFT R0.H BY R2.L (S); -R1.L = ASHIFT R1.H BY R2.L (S); -//rl2 = ashift (rh2 by rl2); -R3.L = ASHIFT R3.H BY R2.L (S); -R4.L = ASHIFT R4.H BY R2.L (S); -R5.L = ASHIFT R5.H BY R2.L (S); -R6.L = ASHIFT R6.H BY R2.L (S); -R7.L = ASHIFT R7.H BY R2.L (S); -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -//CHECKREG r2, 0x2002000f; -CHECKREG r3, 0x30030000; -CHECKREG r4, 0x40040000; -CHECKREG r5, 0x50050000; -CHECKREG r6, 0x60060000; -CHECKREG r7, 0x70070000; - -imm32 r0, 0x10010001; -imm32 r1, 0x10010001; -imm32 r2, 0x20020002; -R3.L = -16; -imm32 r4, 0x40040004; -imm32 r5, 0x50050005; -imm32 r6, 0x60060006; -imm32 r7, 0x70070007; -R0.L = ASHIFT R0.H BY R3.L (S); -R1.L = ASHIFT R1.H BY R3.L (S); -R2.L = ASHIFT R2.H BY R3.L (S); -//rl3 = ashift (rh3 by rl3); -R4.L = ASHIFT R4.H BY R3.L (S); -R5.L = ASHIFT R5.H BY R3.L (S); -R6.L = ASHIFT R6.H BY R3.L (S); -R7.L = ASHIFT R7.H BY R3.L (S); -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -CHECKREG r2, 0x20020000; -//CHECKREG r3, 0x30030010; -CHECKREG r4, 0x40040000; -CHECKREG r5, 0x50050000; -CHECKREG r6, 0x60060000; -CHECKREG r7, 0x70070000; - -// d_hi = ashift (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000000; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R4.L (S); -R1.H = ASHIFT R1.L BY R4.L (S); -R2.H = ASHIFT R2.L BY R4.L (S); -R3.H = ASHIFT R3.L BY R4.L (S); -//rh4 = ashift (rl4 by rl4); -R5.H = ASHIFT R5.L BY R4.L (S); -R6.H = ASHIFT R6.L BY R4.L (S); -R7.H = ASHIFT R7.L BY R4.L (S); -CHECKREG r0, 0x00010001; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -//CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -R5.L = -1; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = ASHIFT R0.L BY R5.L (S); -R1.H = ASHIFT R1.L BY R5.L (S); -R2.H = ASHIFT R2.L BY R5.L (S); -R3.H = ASHIFT R3.L BY R5.L (S); -R4.H = ASHIFT R4.L BY R5.L (S); -//rh5 = ashift (rl5 by rl5); -R6.H = ASHIFT R6.L BY R5.L (S); -R7.H = ASHIFT R7.L BY R5.L (S); -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00010002; -CHECKREG r3, 0x00010003; -CHECKREG r4, 0x00020004; -//CHECKREG r5, 0x00020005; -CHECKREG r6, 0x00030006; -CHECKREG r7, 0x00030007; - - -imm32 r0, 0x00001001; -imm32 r1, 0x00001001; -imm32 r1, 0x00002002; -imm32 r3, 0x00003003; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -R6.L = -15; -imm32 r7, 0x00007007; -R0.H = ASHIFT R0.L BY R6.L (S); -R1.H = ASHIFT R1.L BY R6.L (S); -R2.H = ASHIFT R2.L BY R6.L (S); -R3.H = ASHIFT R3.L BY R6.L (S); -R4.H = ASHIFT R4.L BY R6.L (S); -R5.H = ASHIFT R5.L BY R6.L (S); -//rh6 = ashift (rl6 by rl6); -R7.H = ASHIFT R7.L BY R6.L; -CHECKREG r0, 0x00001001; -CHECKREG r1, 0x00002002; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00003003; -CHECKREG r4, 0x00004004; -CHECKREG r5, 0x00005005; -//CHECKREG r6, 0x00006006; -CHECKREG r7, 0x00007007; - -imm32 r0, 0x00001001; -imm32 r1, 0x00002001; -imm32 r2, 0x00002002; -imm32 r3, 0x00003003; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -imm32 r6, 0x00006006; -R7.L = -16; -R0.H = ASHIFT R0.L BY R7.L (S); -R1.H = ASHIFT R1.L BY R7.L (S); -R2.H = ASHIFT R2.L BY R7.L (S); -R3.H = ASHIFT R3.L BY R7.L (S); -R4.H = ASHIFT R4.L BY R7.L (S); -R5.H = ASHIFT R5.L BY R7.L (S); -R6.H = ASHIFT R6.L BY R7.L (S); -R7.H = ASHIFT R7.L BY R7.L (S); -CHECKREG r0, 0x00001001; -CHECKREG r1, 0x00002001; -CHECKREG r2, 0x00002002; -CHECKREG r3, 0x00003003; -CHECKREG r4, 0x00004004; -CHECKREG r5, 0x00005005; -CHECKREG r6, 0x00006006; -//CHECKREG r7, 0x00007007; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00010000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -R4.L = -1; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = ASHIFT R0.H BY R4.L (S); -R1.H = ASHIFT R1.H BY R4.L (S); -R2.H = ASHIFT R2.H BY R4.L (S); -R3.H = ASHIFT R3.H BY R4.L (S); -//rh4 = ashift (rh4 by rl4); -R5.H = ASHIFT R5.H BY R4.L (S); -R6.H = ASHIFT R6.H BY R4.L (S); -R7.H = ASHIFT R7.H BY R4.L (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00010000; -CHECKREG r3, 0x00010000; -//CHECKREG r4, 0x00020000; -CHECKREG r5, 0x00020000; -CHECKREG r6, 0x00030000; -CHECKREG r7, 0x00030000; - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -imm32 r2, 0x20020000; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -R5.L = -1; -imm32 r6, 0x60060000; -imm32 r7, 0x70070000; -R0.H = ASHIFT R0.H BY R5.L (S); -R1.H = ASHIFT R1.H BY R5.L (S); -R2.H = ASHIFT R2.H BY R5.L (S); -R3.H = ASHIFT R3.H BY R5.L (S); -R4.H = ASHIFT R4.H BY R5.L (S); -//rh5 = ashift (rh5 by rl5); -R6.H = ASHIFT R6.H BY R5.L (S); -R7.H = ASHIFT R7.H BY R5.L (S); -CHECKREG r0, 0x08000000; -CHECKREG r1, 0x08000000; -CHECKREG r2, 0x10010000; -CHECKREG r3, 0x18010000; -CHECKREG r4, 0x20020000; -//CHECKREG r5, 0x28020000; -CHECKREG r6, 0x30030000; -CHECKREG r7, 0x38030000; - - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -imm32 r2, 0x20020000; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -R6.L = -15; -imm32 r7, 0x70070000; -R0.L = ASHIFT R0.H BY R6.L (S); -R1.L = ASHIFT R1.H BY R6.L (S); -R2.L = ASHIFT R2.H BY R6.L (S); -R3.L = ASHIFT R3.H BY R6.L (S); -R4.L = ASHIFT R4.H BY R6.L (S); -R5.L = ASHIFT R5.H BY R6.L (S); -//rl6 = ashift (rh6 by rl6); -R7.L = ASHIFT R7.H BY R6.L; -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -CHECKREG r2, 0x20020000; -CHECKREG r3, 0x30030000; -CHECKREG r4, 0x40040000; -CHECKREG r5, 0x50050000; -//CHECKREG r6, 0x60060000; -CHECKREG r7, 0x70070000; - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -imm32 r2, 0x20020000; -imm32 r2, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -imm32 r6, 0x60060000; -R7.L = -16; -R0.H = ASHIFT R0.H BY R7.L (S); -R1.H = ASHIFT R1.H BY R7.L (S); -R2.H = ASHIFT R2.H BY R7.L (S); -R3.H = ASHIFT R3.H BY R7.L (S); -R4.H = ASHIFT R4.H BY R7.L (S); -R5.H = ASHIFT R5.H BY R7.L (S); -R6.H = ASHIFT R6.H BY R7.L (S); -//rh7 = ashift (rh7 by rl7); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -//CHECKREG r7, -16; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahh.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahh.s deleted file mode 100644 index 2051cf9..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_ahh.s +++ /dev/null @@ -1,430 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_ahh/c_dsp32shift_ahh.dsp -// Spec Reference: dsp32shift ashift/ashift -# mach: bfin - -.include "testutils.inc" - start - - - -// ashift/ashift : positive data, count (+)=left (half reg) -// d_reg = ashift/ashift (d BY d_lo) -// Rx by RLx -imm32 r0, 0x01230000; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R5 = ASHIFT R0 BY R0.L (V); -R0 = ASHIFT R1 BY R0.L (V); -R1 = ASHIFT R2 BY R0.L (V); -R2 = ASHIFT R3 BY R0.L (V); -R3 = ASHIFT R4 BY R0.L (V); -R4 = ASHIFT R5 BY R0.L (V); -R7 = ASHIFT R6 BY R0.L (V); -R6 = ASHIFT R7 BY R0.L (V); -CHECKREG r0, 0x12345678; -CHECKREG r1, 0x00230067; -CHECKREG r2, 0x00340078; -CHECKREG r3, 0x0045FF89; -CHECKREG r4, 0x00010000; -CHECKREG r5, 0x01230000; -CHECKREG r6, 0x0000FFFF; -CHECKREG r7, 0x0067FFAB; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R1.L = 5; -R2 = ASHIFT R0 BY R1.L (V); -R3 = ASHIFT R1 BY R1.L (V); -R4 = ASHIFT R2 BY R1.L (V); -R5 = ASHIFT R3 BY R1.L (V); -R6 = ASHIFT R4 BY R1.L (V); -R7 = ASHIFT R5 BY R1.L (V); -R0 = ASHIFT R6 BY R1.L (V); -R1 = ASHIFT R7 BY R1.L (V); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x24600040; -CHECKREG r3, 0x468000A0; -CHECKREG r4, 0x8C000800; -CHECKREG r5, 0xD0001400; -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x00008000; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R2 = 15; -R3 = ASHIFT R0 BY R2.L (V); -R4 = ASHIFT R1 BY R2.L (V); -R5 = ASHIFT R2 BY R2.L (V); -R6 = ASHIFT R3 BY R2.L (V); -R7 = ASHIFT R4 BY R2.L (V); -R0 = ASHIFT R5 BY R2.L (V); -R1 = ASHIFT R6 BY R2.L (V); -R2 = ASHIFT R7 BY R2.L (V); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x80000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00008000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R3.L = 16; -R4 = ASHIFT R0 BY R3.L (V); -R5 = ASHIFT R1 BY R3.L (V); -R6 = ASHIFT R2 BY R3.L (V); -R7 = ASHIFT R3 BY R3.L (V); -R0 = ASHIFT R4 BY R3.L (V); -R1 = ASHIFT R5 BY R3.L (V); -R2 = ASHIFT R6 BY R3.L (V); -R3 = ASHIFT R7 BY R3.L (V); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R4.L = -1; -R0 = ASHIFT R0 BY R4.L (V); -R1 = ASHIFT R1 BY R4.L (V); -R2 = ASHIFT R2 BY R4.L (V); -R3 = ASHIFT R3 BY R4.L (V); -R4 = ASHIFT R4 BY R4.L (V); -R5 = ASHIFT R5 BY R4.L (V); -R6 = ASHIFT R6 BY R4.L (V); -R7 = ASHIFT R7 BY R4.L (V); -CHECKREG r0, 0x00910001; -CHECKREG r1, 0x091A2B3C; -CHECKREG r2, 0x11A233C4; -CHECKREG r3, 0x1A2B3C4D; -CHECKREG r4, 0x22B3FFFF; -CHECKREG r5, 0x2B3CCD5E; -CHECKREG r6, 0x33C4D5E6; -CHECKREG r7, 0x3C4DDE6F; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R5.L = -6; -R6 = ASHIFT R0 BY R5.L (V); -R7 = ASHIFT R1 BY R5.L (V); -R0 = ASHIFT R2 BY R5.L (V); -R1 = ASHIFT R3 BY R5.L (V); -R2 = ASHIFT R4 BY R5.L (V); -R3 = ASHIFT R5 BY R5.L (V); -R4 = ASHIFT R6 BY R5.L (V); -R5 = ASHIFT R7 BY R5.L (V); -CHECKREG r0, 0x008D019E; -CHECKREG r1, 0x00D101E2; -CHECKREG r2, 0x0115FE26; -CHECKREG r3, 0x0159FFFF; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00010005; -CHECKREG r6, 0x00040000; -CHECKREG r7, 0x00480159; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R6.L = -15; -R7 = ASHIFT R0 BY R6.L (V); -R0 = ASHIFT R1 BY R6.L (V); -R1 = ASHIFT R2 BY R6.L (V); -R2 = ASHIFT R3 BY R6.L (V); -R3 = ASHIFT R4 BY R6.L (V); -R4 = ASHIFT R5 BY R6.L (V); -R5 = ASHIFT R6 BY R6.L (V); -R6 = ASHIFT R7 BY R6.L (V); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x0000FFFF; -CHECKREG r4, 0x0000FFFF; -CHECKREG r5, 0x0000FFFF; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R7.L = -16; -R0 = ASHIFT R0 BY R7.L (V); -R1 = ASHIFT R1 BY R7.L (V); -R2 = ASHIFT R2 BY R7.L (V); -R3 = ASHIFT R3 BY R7.L (V); -R4 = ASHIFT R4 BY R7.L (V); -R5 = ASHIFT R5 BY R7.L (V); -R6 = ASHIFT R6 BY R7.L (V); -R7 = ASHIFT R7 BY R7.L (V); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x0000FFFF; -CHECKREG r5, 0x0000FFFF; -CHECKREG r6, 0x0000FFFF; -CHECKREG r7, 0x0000FFFF; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R0.L = 4; -//r0 = ashift/ashift (r0 by rl0); -R1 = ASHIFT R1 BY R0.L (V); -R2 = ASHIFT R2 BY R0.L (V); -R3 = ASHIFT R3 BY R0.L (V); -R4 = ASHIFT R4 BY R0.L (V); -R5 = ASHIFT R5 BY R0.L (V); -R6 = ASHIFT R6 BY R0.L (V); -R7 = ASHIFT R7 BY R0.L (V); -CHECKREG r0, 0x01230004; -CHECKREG r1, 0x23406780; -CHECKREG r2, 0x34507890; -CHECKREG r3, 0x456089A0; -CHECKREG r4, 0x56709AB0; -CHECKREG r5, 0x6780ABC0; -CHECKREG r6, 0x7890BCD0; -CHECKREG r7, 0x89A0CDE0; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R1.L = 6; -R0 = ASHIFT R0 BY R1.L (V); -//r1 = ashift/ashift (r1 by rl1); -R2 = ASHIFT R2 BY R1.L (V); -R3 = ASHIFT R3 BY R1.L (V); -R4 = ASHIFT R4 BY R1.L (V); -R5 = ASHIFT R5 BY R1.L (V); -R6 = ASHIFT R6 BY R1.L (V); -R7 = ASHIFT R7 BY R1.L (V); -CHECKREG r0, 0x48C00080; -CHECKREG r1, 0x12340006; -CHECKREG r2, 0xD140E240; -CHECKREG r3, 0x15802680; -CHECKREG r4, 0x59C06AC0; -CHECKREG r5, 0x9E00AF00; -CHECKREG r6, 0xE240F340; -CHECKREG r7, 0x26803780; - - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R2.L = 15; -R0 = ASHIFT R0 BY R2.L (V); -R1 = ASHIFT R1 BY R2.L (V); -//r2 = ashift/ashift (r2 by rl2); -R3 = ASHIFT R3 BY R2.L (V); -R4 = ASHIFT R4 BY R2.L (V); -R5 = ASHIFT R5 BY R2.L (V); -R6 = ASHIFT R6 BY R2.L (V); -R7 = ASHIFT R7 BY R2.L (V); -CHECKREG r0, 0x80000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x2345000F; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x80008000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x80008000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R3.L = 16; -R0 = ASHIFT R0 BY R3.L (V); -R1 = ASHIFT R1 BY R3.L (V); -R2 = ASHIFT R2 BY R3.L (V); -//r3 = ashift/ashift (r3 by rl3); -R4 = ASHIFT R4 BY R3.L (V); -R5 = ASHIFT R5 BY R3.L (V); -R6 = ASHIFT R6 BY R3.L (V); -R7 = ASHIFT R7 BY R3.L (V); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x34560010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R4.L = -9; -R0 = ASHIFT R0 BY R4.L (V); -R1 = ASHIFT R1 BY R4.L (V); -R2 = ASHIFT R2 BY R4.L (V); -R3 = ASHIFT R3 BY R4.L (V); -//r4 = ashift/ashift (r4 by rl4); -R5 = ASHIFT R5 BY R4.L (V); -R6 = ASHIFT R6 BY R4.L (V); -R7 = ASHIFT R7 BY R4.L (V); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x0009002B; -CHECKREG r2, 0x00110033; -CHECKREG r3, 0x001A003C; -CHECKREG r4, 0x4567FFF7; -CHECKREG r5, 0x002BFFCD; -CHECKREG r6, 0x0033FFD5; -CHECKREG r7, 0x003CFFDE; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R5.L = -14; -R0 = ASHIFT R0 BY R5.L (V); -R1 = ASHIFT R1 BY R5.L (V); -R2 = ASHIFT R2 BY R5.L (V); -R3 = ASHIFT R3 BY R5.L (V); -R4 = ASHIFT R4 BY R5.L (V); -//r5 = ashift/ashift (r5 by rl5); -R6 = ASHIFT R6 BY R5.L (V); -R7 = ASHIFT R7 BY R5.L (V); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x0001FFFE; -CHECKREG r5, 0x5678FFF2; -CHECKREG r6, 0x0001FFFE; -CHECKREG r7, 0x0001FFFE; - - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R6.L = -15; -R0 = ASHIFT R0 BY R6.L (V); -R1 = ASHIFT R1 BY R6.L (V); -R2 = ASHIFT R2 BY R6.L (V); -R3 = ASHIFT R3 BY R6.L (V); -R4 = ASHIFT R4 BY R6.L (V); -R5 = ASHIFT R5 BY R6.L (V); -//r6 = ashift/ashift (r6 by rl6); -R7 = ASHIFT R7 BY R6.L (V); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x0000FFFF; -CHECKREG r5, 0x0000FFFF; -CHECKREG r6, 0x6789FFF1; -CHECKREG r7, 0x0000FFFF; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R7.L = -16; -R0 = ASHIFT R0 BY R7.L (V); -R1 = ASHIFT R1 BY R7.L (V); -R2 = ASHIFT R2 BY R7.L (V); -R3 = ASHIFT R3 BY R7.L (V); -R4 = ASHIFT R4 BY R7.L (V); -R5 = ASHIFT R5 BY R7.L (V); -R6 = ASHIFT R6 BY R7.L (V); -R7 = ASHIFT R7 BY R7.L (V); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x0000ffff; -CHECKREG r5, 0x0000ffff; -CHECKREG r6, 0x0000ffff; -CHECKREG r7, 0x0000ffff; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahh_s.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahh_s.s deleted file mode 100644 index b948e90..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_ahh_s.s +++ /dev/null @@ -1,430 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_ahh_s/c_dsp32shift_ahh_s.dsp -// Spec Reference: dsp32shift ashift/ashift s -# mach: bfin - -.include "testutils.inc" - start - - - -// ashift/ashift s : positive data, count (+)=left (half reg) -// d_reg = ashift/ashift (d BY d_lo) saturation -// Rx by RLx -imm32 r0, 0x01230000; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R5 = ASHIFT R0 BY R0.L (V , S); -R0 = ASHIFT R1 BY R0.L (V , S); -R1 = ASHIFT R2 BY R0.L (V , S); -R2 = ASHIFT R3 BY R0.L (V , S); -R3 = ASHIFT R4 BY R0.L (V , S); -R4 = ASHIFT R5 BY R0.L (V , S); -R7 = ASHIFT R6 BY R0.L (V , S); -R6 = ASHIFT R7 BY R0.L (V , S); -CHECKREG r0, 0x12345678; -CHECKREG r1, 0x00230067; -CHECKREG r2, 0x00340078; -CHECKREG r3, 0x0045FF89; -CHECKREG r4, 0x00010000; -CHECKREG r5, 0x01230000; -CHECKREG r6, 0x0000FFFF; -CHECKREG r7, 0x0067FFAB; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R1.L = 5; -R2 = ASHIFT R0 BY R1.L (V , S); -R3 = ASHIFT R1 BY R1.L (V , S); -R4 = ASHIFT R2 BY R1.L (V , S); -R5 = ASHIFT R3 BY R1.L (V , S); -R6 = ASHIFT R4 BY R1.L (V , S); -R7 = ASHIFT R5 BY R1.L (V , S); -R0 = ASHIFT R6 BY R1.L (V , S); -R1 = ASHIFT R7 BY R1.L (V , S); -CHECKREG r0, 0x7FFF7FFF; -CHECKREG r1, 0x7FFF7FFF; -CHECKREG r2, 0x24600040; -CHECKREG r3, 0x7FFF00A0; -CHECKREG r4, 0x7FFF0800; -CHECKREG r5, 0x7FFF1400; -CHECKREG r6, 0x7FFF7FFF; -CHECKREG r7, 0x7FFF7FFF; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R2 = 15; -R3 = ASHIFT R0 BY R2.L (V , S); -R4 = ASHIFT R1 BY R2.L (V , S); -R5 = ASHIFT R2 BY R2.L (V , S); -R6 = ASHIFT R3 BY R2.L (V , S); -R7 = ASHIFT R4 BY R2.L (V , S); -R0 = ASHIFT R5 BY R2.L (V , S); -R1 = ASHIFT R6 BY R2.L (V , S); -R2 = ASHIFT R7 BY R2.L (V , S); -CHECKREG r0, 0x00007FFF; -CHECKREG r1, 0x7FFF7FFF; -CHECKREG r2, 0x7FFF7FFF; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x7FFF7FFF; -CHECKREG r5, 0x00007FFF; -CHECKREG r6, 0x7FFF7FFF; -CHECKREG r7, 0x7FFF7FFF; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R3.L = 16; -R4 = ASHIFT R0 BY R3.L (V , S); -R5 = ASHIFT R1 BY R3.L (V , S); -R6 = ASHIFT R2 BY R3.L (V , S); -R7 = ASHIFT R3 BY R3.L (V , S); -R0 = ASHIFT R4 BY R3.L (V , S); -R1 = ASHIFT R5 BY R3.L (V , S); -R2 = ASHIFT R6 BY R3.L (V , S); -R3 = ASHIFT R7 BY R3.L (V , S); -CHECKREG r0, 0x7FFF7FFF; -CHECKREG r1, 0x7FFF7FFF; -CHECKREG r2, 0x7FFF7FFF; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x7FFF7FFF; -CHECKREG r5, 0x7FFF7FFF; -CHECKREG r6, 0x7FFF7FFF; -CHECKREG r7, 0x7FFF7FFF; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R4.L = -1; -R0 = ASHIFT R0 BY R4.L (V , S); -R1 = ASHIFT R1 BY R4.L (V , S); -R2 = ASHIFT R2 BY R4.L (V , S); -R3 = ASHIFT R3 BY R4.L (V , S); -R4 = ASHIFT R4 BY R4.L (V , S); -R5 = ASHIFT R5 BY R4.L (V , S); -R6 = ASHIFT R6 BY R4.L (V , S); -R7 = ASHIFT R7 BY R4.L (V , S); -CHECKREG r0, 0x00910001; -CHECKREG r1, 0x091A2B3C; -CHECKREG r2, 0x11A233C4; -CHECKREG r3, 0x1A2B3C4D; -CHECKREG r4, 0x22B3FFFF; -CHECKREG r5, 0x2B3CCD5E; -CHECKREG r6, 0x33C4D5E6; -CHECKREG r7, 0x3C4DDE6F; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R5.L = -6; -R6 = ASHIFT R0 BY R5.L (V , S); -R7 = ASHIFT R1 BY R5.L (V , S); -R0 = ASHIFT R2 BY R5.L (V , S); -R1 = ASHIFT R3 BY R5.L (V , S); -R2 = ASHIFT R4 BY R5.L (V , S); -R3 = ASHIFT R5 BY R5.L (V , S); -R4 = ASHIFT R6 BY R5.L (V , S); -R5 = ASHIFT R7 BY R5.L (V , S); -CHECKREG r0, 0x008D019E; -CHECKREG r1, 0x00D101E2; -CHECKREG r2, 0x0115FE26; -CHECKREG r3, 0x0159FFFF; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00010005; -CHECKREG r6, 0x00040000; -CHECKREG r7, 0x00480159; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R6.L = -15; -R7 = ASHIFT R0 BY R6.L (V , S); -R0 = ASHIFT R1 BY R6.L (V , S); -R1 = ASHIFT R2 BY R6.L (V , S); -R2 = ASHIFT R3 BY R6.L (V , S); -R3 = ASHIFT R4 BY R6.L (V , S); -R4 = ASHIFT R5 BY R6.L (V , S); -R5 = ASHIFT R6 BY R6.L (V , S); -R6 = ASHIFT R7 BY R6.L (V , S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x0000FFFF; -CHECKREG r4, 0x0000FFFF; -CHECKREG r5, 0x0000FFFF; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R7.L = -16; -R0 = ASHIFT R0 BY R7.L (V , S); -R1 = ASHIFT R1 BY R7.L (V , S); -R2 = ASHIFT R2 BY R7.L (V , S); -R3 = ASHIFT R3 BY R7.L (V , S); -R4 = ASHIFT R4 BY R7.L (V , S); -R5 = ASHIFT R5 BY R7.L (V , S); -R6 = ASHIFT R6 BY R7.L (V , S); -R7 = ASHIFT R7 BY R7.L (V , S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x0000FFFF; -CHECKREG r5, 0x0000FFFF; -CHECKREG r6, 0x0000FFFF; -CHECKREG r7, 0x0000FFFF; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R0.L = 4; -//r0 = ashift/ashift (r0 by rl0); -R1 = ASHIFT R1 BY R0.L (V , S); -R2 = ASHIFT R2 BY R0.L (V , S); -R3 = ASHIFT R3 BY R0.L (V , S); -R4 = ASHIFT R4 BY R0.L (V , S); -R5 = ASHIFT R5 BY R0.L (V , S); -R6 = ASHIFT R6 BY R0.L (V , S); -R7 = ASHIFT R7 BY R0.L (V , S); -CHECKREG r0, 0x01230004; -CHECKREG r1, 0x7FFF7FFF; -CHECKREG r2, 0x7FFF7FFF; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x7FFF8000; -CHECKREG r5, 0x7FFF8000; -CHECKREG r6, 0x7FFF8000; -CHECKREG r7, 0x7FFF8000; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R1.L = 6; -R0 = ASHIFT R0 BY R1.L (V , S); -//r1 = ashift/ashift (r1 by rl1); -R2 = ASHIFT R2 BY R1.L (V , S); -R3 = ASHIFT R3 BY R1.L (V , S); -R4 = ASHIFT R4 BY R1.L (V , S); -R5 = ASHIFT R5 BY R1.L (V , S); -R6 = ASHIFT R6 BY R1.L (V , S); -R7 = ASHIFT R7 BY R1.L (V , S); -CHECKREG r0, 0x48C00080; -CHECKREG r1, 0x12340006; -CHECKREG r2, 0x7FFF7FFF; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x7FFF8000; -CHECKREG r5, 0x7FFF8000; -CHECKREG r6, 0x7FFF8000; -CHECKREG r7, 0x7FFF8000; - - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R2.L = 15; -R0 = ASHIFT R0 BY R2.L (V , S); -R1 = ASHIFT R1 BY R2.L (V , S); -//r2 = ashift/ashift (r2 by rl2) s; -R3 = ASHIFT R3 BY R2.L (V , S); -R4 = ASHIFT R4 BY R2.L (V , S); -R5 = ASHIFT R5 BY R2.L (V , S); -R6 = ASHIFT R6 BY R2.L (V , S); -R7 = ASHIFT R7 BY R2.L (V , S); -CHECKREG r0, 0x7FFF7FFF; -CHECKREG r1, 0x7FFF7FFF; -CHECKREG r2, 0x2345000F; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x7FFF8000; -CHECKREG r5, 0x7FFF8000; -CHECKREG r6, 0x7FFF8000; -CHECKREG r7, 0x7FFF8000; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R3.L = 16; -R0 = ASHIFT R0 BY R3.L (V , S); -R1 = ASHIFT R1 BY R3.L (V , S); -R2 = ASHIFT R2 BY R3.L (V , S); -//r3 = ashift/ashift (r3 by rl3) s; -R4 = ASHIFT R4 BY R3.L (V , S); -R5 = ASHIFT R5 BY R3.L (V , S); -R6 = ASHIFT R6 BY R3.L (V , S); -R7 = ASHIFT R7 BY R3.L (V , S); -CHECKREG r0, 0x7FFF7FFF; -CHECKREG r1, 0x7FFF7FFF; -CHECKREG r2, 0x7FFF7FFF; -CHECKREG r3, 0x34560010; -CHECKREG r4, 0x7FFF8000; -CHECKREG r5, 0x7FFF8000; -CHECKREG r6, 0x7FFF8000; -CHECKREG r7, 0x7FFF8000; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R4.L = -9; -R0 = ASHIFT R0 BY R4.L (V , S); -R1 = ASHIFT R1 BY R4.L (V , S); -R2 = ASHIFT R2 BY R4.L (V , S); -R3 = ASHIFT R3 BY R4.L (V , S); -//r4 = ashift/ashift (r4 by rl4) s; -R5 = ASHIFT R5 BY R4.L (V , S); -R6 = ASHIFT R6 BY R4.L (V , S); -R7 = ASHIFT R7 BY R4.L (V , S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x0009002B; -CHECKREG r2, 0x00110033; -CHECKREG r3, 0x001A003C; -CHECKREG r4, 0x4567FFF7; -CHECKREG r5, 0x002BFFCD; -CHECKREG r6, 0x0033FFD5; -CHECKREG r7, 0x003CFFDE; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R5.L = -14; -R0 = ASHIFT R0 BY R5.L (V , S); -R1 = ASHIFT R1 BY R5.L (V , S); -R2 = ASHIFT R2 BY R5.L (V , S); -R3 = ASHIFT R3 BY R5.L (V , S); -R4 = ASHIFT R4 BY R5.L (V , S); -//r5 = ashift/ashift (r5 by rl5) s; -R6 = ASHIFT R6 BY R5.L (V , S); -R7 = ASHIFT R7 BY R5.L (V , S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x0001FFFE; -CHECKREG r5, 0x5678FFF2; -CHECKREG r6, 0x0001FFFE; -CHECKREG r7, 0x0001FFFE; - - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R6.L = -15; -R0 = ASHIFT R0 BY R6.L (V , S); -R1 = ASHIFT R1 BY R6.L (V , S); -R2 = ASHIFT R2 BY R6.L (V , S); -R3 = ASHIFT R3 BY R6.L (V , S); -R4 = ASHIFT R4 BY R6.L (V , S); -R5 = ASHIFT R5 BY R6.L (V , S); -//r6 = ashift/ashift (r6 by rl6) s; -R7 = ASHIFT R7 BY R6.L (V , S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x0000FFFF; -CHECKREG r5, 0x0000FFFF; -CHECKREG r6, 0x6789FFF1; -CHECKREG r7, 0x0000FFFF; - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R7.L = -16; -R0 = ASHIFT R0 BY R7.L (V , S); -R1 = ASHIFT R1 BY R7.L (V , S); -R2 = ASHIFT R2 BY R7.L (V , S); -R3 = ASHIFT R3 BY R7.L (V , S); -R4 = ASHIFT R4 BY R7.L (V , S); -R5 = ASHIFT R5 BY R7.L (V , S); -R6 = ASHIFT R6 BY R7.L (V , S); -R7 = ASHIFT R7 BY R7.L (V , S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x0000ffff; -CHECKREG r5, 0x0000ffff; -CHECKREG r6, 0x0000ffff; -CHECKREG r7, 0x0000ffff; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_align16.s b/sim/testsuite/sim/bfin/c_dsp32shift_align16.s deleted file mode 100644 index a6fd284..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_align16.s +++ /dev/null @@ -1,210 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_align16/c_dsp32shift_align16.dsp -// Spec Reference: dsp32shift align16 -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x00000001; -imm32 r1, 0x01000801; -imm32 r2, 0x08200802; -imm32 r3, 0x08030803; -imm32 r4, 0x08004804; -imm32 r5, 0x08000505; -imm32 r6, 0x08000866; -imm32 r7, 0x08000807; -R1 = ALIGN16 ( R1 , R0 ); -R2 = ALIGN16 ( R2 , R0 ); -R3 = ALIGN16 ( R3 , R0 ); -R4 = ALIGN16 ( R4 , R0 ); -R5 = ALIGN16 ( R5 , R0 ); -R6 = ALIGN16 ( R6 , R0 ); -R7 = ALIGN16 ( R7 , R0 ); -R0 = ALIGN16 ( R0 , R0 ); -CHECKREG r0, 0x00010000; -CHECKREG r1, 0x08010000; -CHECKREG r2, 0x08020000; -CHECKREG r3, 0x08030000; -CHECKREG r4, 0x48040000; -CHECKREG r5, 0x05050000; -CHECKREG r6, 0x08660000; -CHECKREG r7, 0x08070000; - -imm32 r0, 0x0900d001; -imm32 r1, 0x09000002; -imm32 r2, 0x09400002; -imm32 r3, 0x09100003; -imm32 r4, 0x09020004; -imm32 r5, 0x09003005; -imm32 r6, 0x09000406; -imm32 r7, 0x09000057; -R0 = ALIGN16 ( R0 , R1 ); -R2 = ALIGN16 ( R2 , R1 ); -R3 = ALIGN16 ( R3 , R1 ); -R4 = ALIGN16 ( R4 , R1 ); -R5 = ALIGN16 ( R5 , R1 ); -R6 = ALIGN16 ( R6 , R1 ); -R7 = ALIGN16 ( R7 , R1 ); -R1 = ALIGN16 ( R1 , R1 ); -CHECKREG r0, 0xD0010900; -CHECKREG r1, 0x00020900; -CHECKREG r2, 0x00020900; -CHECKREG r3, 0x00030900; -CHECKREG r4, 0x00040900; -CHECKREG r5, 0x30050900; -CHECKREG r6, 0x04060900; -CHECKREG r7, 0x00570900; - - -imm32 r0, 0x0a00e001; -imm32 r1, 0x0a00e001; -imm32 r2, 0x0a00000f; -imm32 r3, 0x0a400010; -imm32 r4, 0x0a05e004; -imm32 r5, 0x0a006005; -imm32 r6, 0x0a00e706; -imm32 r7, 0x0a00e087; -R0 = ALIGN16 ( R0 , R2 ); -R1 = ALIGN16 ( R1 , R2 ); -R3 = ALIGN16 ( R3 , R2 ); -R4 = ALIGN16 ( R4 , R2 ); -R5 = ALIGN16 ( R5 , R2 ); -R6 = ALIGN16 ( R6 , R2 ); -R7 = ALIGN16 ( R7 , R2 ); -R2 = ALIGN16 ( R2 , R2 ); -CHECKREG r0, 0xE0010A00; -CHECKREG r1, 0xE0010A00; -CHECKREG r2, 0x000F0A00; -CHECKREG r3, 0x00100A00; -CHECKREG r4, 0xE0040A00; -CHECKREG r5, 0x60050A00; -CHECKREG r6, 0xE7060A00; -CHECKREG r7, 0xE0870A00; - -imm32 r0, 0x2b00f001; -imm32 r1, 0x0300f001; -imm32 r2, 0x0b40f002; -imm32 r3, 0x0b050010; -imm32 r4, 0x0b006004; -imm32 r5, 0x0b00f705; -imm32 r6, 0x0b00f086; -imm32 r7, 0x0b00f009; -R0 = ALIGN16 ( R0 , R3 ); -R1 = ALIGN16 ( R1 , R3 ); -R2 = ALIGN16 ( R2 , R3 ); -R4 = ALIGN16 ( R4 , R3 ); -R5 = ALIGN16 ( R5 , R3 ); -R6 = ALIGN16 ( R6 , R3 ); -R7 = ALIGN16 ( R7 , R3 ); -R3 = ALIGN16 ( R3 , R3 ); -CHECKREG r0, 0xF0010B05; -CHECKREG r1, 0xF0010B05; -CHECKREG r2, 0xF0020B05; -CHECKREG r3, 0x00100B05; -CHECKREG r4, 0x60040B05; -CHECKREG r5, 0xF7050B05; -CHECKREG r6, 0xF0860B05; -CHECKREG r7, 0xF0090B05; - -imm32 r0, 0x4c0000c0; -imm32 r1, 0x050100c0; -imm32 r2, 0x0c6200c0; -imm32 r3, 0x0c0700c0; -imm32 r4, 0x0c04800c; -imm32 r5, 0x0c0509c0; -imm32 r6, 0x0c060000; -imm32 r7, 0x0c0700ca; -R0 = ALIGN16 ( R0 , R4 ); -R1 = ALIGN16 ( R1 , R4 ); -R2 = ALIGN16 ( R2 , R4 ); -R3 = ALIGN16 ( R3 , R4 ); -R5 = ALIGN16 ( R5 , R4 ); -R6 = ALIGN16 ( R6 , R4 ); -R7 = ALIGN16 ( R7 , R4 ); -R4 = ALIGN16 ( R4 , R4 ); -CHECKREG r0, 0x00C00C04; -CHECKREG r1, 0x00C00C04; -CHECKREG r2, 0x00C00C04; -CHECKREG r3, 0x00C00C04; -CHECKREG r4, 0x800C0C04; -CHECKREG r5, 0x09C00C04; -CHECKREG r6, 0x00000C04; -CHECKREG r7, 0x00CA0C04; - -imm32 r0, 0xa00100d0; -imm32 r1, 0xa00100d1; -imm32 r2, 0xa00200d0; -imm32 r3, 0xa00300d0; -imm32 r4, 0xa00400d0; -imm32 r5, 0xa0050007; -imm32 r6, 0xa00600d0; -imm32 r7, 0xa00700d0; -R0 = ALIGN16 ( R0 , R5 ); -R1 = ALIGN16 ( R1 , R5 ); -R2 = ALIGN16 ( R2 , R5 ); -R3 = ALIGN16 ( R3 , R5 ); -R4 = ALIGN16 ( R4 , R5 ); -R6 = ALIGN16 ( R6 , R5 ); -R7 = ALIGN16 ( R7 , R5 ); -R5 = ALIGN16 ( R5 , R5 ); -CHECKREG r0, 0x00D0A005; -CHECKREG r1, 0x00D1A005; -CHECKREG r2, 0x00D0A005; -CHECKREG r3, 0x00D0A005; -CHECKREG r4, 0x00D0A005; -CHECKREG r5, 0x0007A005; -CHECKREG r6, 0x00D0A005; -CHECKREG r7, 0x00D0A005; - -imm32 r0, 0xb2010000; -imm32 r1, 0xb0310000; -imm32 r2, 0xb042000f; -imm32 r3, 0xbf030000; -imm32 r4, 0xba040000; -imm32 r5, 0xbb050000; -imm32 r6, 0xbc060009; -imm32 r7, 0xb0e70000; -R0 = ALIGN16 ( R0 , R6 ); -R1 = ALIGN16 ( R1 , R6 ); -R2 = ALIGN16 ( R2 , R6 ); -R3 = ALIGN16 ( R3 , R6 ); -R4 = ALIGN16 ( R4 , R6 ); -R5 = ALIGN16 ( R5 , R6 ); -R6 = ALIGN16 ( R6 , R6 ); -R7 = ALIGN16 ( R7 , R6 ); -CHECKREG r0, 0x0000BC06; -CHECKREG r1, 0x0000BC06; -CHECKREG r2, 0x000FBC06; -CHECKREG r3, 0x0000BC06; -CHECKREG r4, 0x0000BC06; -CHECKREG r5, 0x0000BC06; -CHECKREG r6, 0x0009BC06; -CHECKREG r7, 0x00000009; - -imm32 r0, 0xd23100e0; -imm32 r1, 0xd04500e0; -imm32 r2, 0xde32f0e0; -imm32 r3, 0xd90300e0; -imm32 r4, 0xd07400e0; -imm32 r5, 0xdef500e0; -imm32 r6, 0xd06600e0; -imm32 r7, 0xd0080023; -R1 = ALIGN16 ( R0 , R7 ); -R2 = ALIGN16 ( R1 , R7 ); -R3 = ALIGN16 ( R2 , R7 ); -R4 = ALIGN16 ( R3 , R7 ); -R5 = ALIGN16 ( R4 , R7 ); -R6 = ALIGN16 ( R5 , R7 ); -R7 = ALIGN16 ( R6 , R7 ); -R0 = ALIGN16 ( R7 , R7 ); -CHECKREG r0, 0xD008D008; -CHECKREG r1, 0x00E0D008; -CHECKREG r2, 0xD008D008; -CHECKREG r3, 0xD008D008; -CHECKREG r4, 0xD008D008; -CHECKREG r5, 0xD008D008; -CHECKREG r6, 0xD008D008; -CHECKREG r7, 0xD008D008; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_align24.s b/sim/testsuite/sim/bfin/c_dsp32shift_align24.s deleted file mode 100644 index bc33c58..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_align24.s +++ /dev/null @@ -1,210 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_align24/c_dsp32shift_align24.dsp -// Spec Reference: dsp32shift align24 -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x00000001; -imm32 r1, 0x01000801; -imm32 r2, 0x08200802; -imm32 r3, 0x08030803; -imm32 r4, 0x08004804; -imm32 r5, 0x08000505; -imm32 r6, 0x08000866; -imm32 r7, 0x08000807; -R1 = ALIGN24 ( R1 , R0 ); -R2 = ALIGN24 ( R2 , R0 ); -R3 = ALIGN24 ( R3 , R0 ); -R4 = ALIGN24 ( R4 , R0 ); -R5 = ALIGN24 ( R5 , R0 ); -R6 = ALIGN24 ( R6 , R0 ); -R7 = ALIGN24 ( R7 , R0 ); -R0 = ALIGN24 ( R0 , R0 ); -CHECKREG r0, 0x00000100; -CHECKREG r1, 0x00080100; -CHECKREG r2, 0x20080200; -CHECKREG r3, 0x03080300; -CHECKREG r4, 0x00480400; -CHECKREG r5, 0x00050500; -CHECKREG r6, 0x00086600; -CHECKREG r7, 0x00080700; - -imm32 r0, 0x0900d001; -imm32 r1, 0x09000002; -imm32 r2, 0x09400002; -imm32 r3, 0x09100003; -imm32 r4, 0x09020004; -imm32 r5, 0x09003005; -imm32 r6, 0x09000406; -imm32 r7, 0x09000057; -R0 = ALIGN24 ( R0 , R1 ); -R2 = ALIGN24 ( R2 , R1 ); -R3 = ALIGN24 ( R3 , R1 ); -R4 = ALIGN24 ( R4 , R1 ); -R5 = ALIGN24 ( R5 , R1 ); -R6 = ALIGN24 ( R6 , R1 ); -R7 = ALIGN24 ( R7 , R1 ); -R1 = ALIGN24 ( R1 , R1 ); -CHECKREG r0, 0x00D00109; -CHECKREG r1, 0x00000209; -CHECKREG r2, 0x40000209; -CHECKREG r3, 0x10000309; -CHECKREG r4, 0x02000409; -CHECKREG r5, 0x00300509; -CHECKREG r6, 0x00040609; -CHECKREG r7, 0x00005709; - - -imm32 r0, 0x0a00e001; -imm32 r1, 0x0a00e001; -imm32 r2, 0x0a00000f; -imm32 r3, 0x0a400010; -imm32 r4, 0x0a05e004; -imm32 r5, 0x0a006005; -imm32 r6, 0x0a00e706; -imm32 r7, 0x0a00e087; -R0 = ALIGN24 ( R0 , R2 ); -R1 = ALIGN24 ( R1 , R2 ); -R3 = ALIGN24 ( R3 , R2 ); -R4 = ALIGN24 ( R4 , R2 ); -R5 = ALIGN24 ( R5 , R2 ); -R6 = ALIGN24 ( R6 , R2 ); -R7 = ALIGN24 ( R7 , R2 ); -R2 = ALIGN24 ( R2 , R2 ); -CHECKREG r0, 0x00E0010A; -CHECKREG r1, 0x00E0010A; -CHECKREG r2, 0x00000F0A; -CHECKREG r3, 0x4000100A; -CHECKREG r4, 0x05E0040A; -CHECKREG r5, 0x0060050A; -CHECKREG r6, 0x00E7060A; -CHECKREG r7, 0x00E0870A; - -imm32 r0, 0x2b00f001; -imm32 r1, 0x0300f001; -imm32 r2, 0x0b40f002; -imm32 r3, 0x0b050010; -imm32 r4, 0x0b006004; -imm32 r5, 0x0b00f705; -imm32 r6, 0x0b00f086; -imm32 r7, 0x0b00f009; -R0 = ALIGN24 ( R0 , R3 ); -R1 = ALIGN24 ( R1 , R3 ); -R2 = ALIGN24 ( R2 , R3 ); -R4 = ALIGN24 ( R4 , R3 ); -R5 = ALIGN24 ( R5 , R3 ); -R6 = ALIGN24 ( R6 , R3 ); -R7 = ALIGN24 ( R7 , R3 ); -R3 = ALIGN24 ( R3 , R3 ); -CHECKREG r0, 0x00F0010B; -CHECKREG r1, 0x00F0010B; -CHECKREG r2, 0x40F0020B; -CHECKREG r3, 0x0500100B; -CHECKREG r4, 0x0060040B; -CHECKREG r5, 0x00F7050B; -CHECKREG r6, 0x00F0860B; -CHECKREG r7, 0x00F0090B; - -imm32 r0, 0x4c0000c0; -imm32 r1, 0x050100c0; -imm32 r2, 0x0c6200c0; -imm32 r3, 0x0c0700c0; -imm32 r4, 0x0c04800c; -imm32 r5, 0x0c0509c0; -imm32 r6, 0x0c060000; -imm32 r7, 0x0c0700ca; -R0 = ALIGN24 ( R0 , R4 ); -R1 = ALIGN24 ( R1 , R4 ); -R2 = ALIGN24 ( R2 , R4 ); -R3 = ALIGN24 ( R3 , R4 ); -R5 = ALIGN24 ( R5 , R4 ); -R6 = ALIGN24 ( R6 , R4 ); -R7 = ALIGN24 ( R7 , R4 ); -R4 = ALIGN24 ( R4 , R4 ); -CHECKREG r0, 0x0000C00C; -CHECKREG r1, 0x0100C00C; -CHECKREG r2, 0x6200C00C; -CHECKREG r3, 0x0700C00C; -CHECKREG r4, 0x04800C0C; -CHECKREG r5, 0x0509C00C; -CHECKREG r6, 0x0600000C; -CHECKREG r7, 0x0700CA0C; - -imm32 r0, 0xa00100d0; -imm32 r1, 0xa00100d1; -imm32 r2, 0xa00200d0; -imm32 r3, 0xa00300d0; -imm32 r4, 0xa00400d0; -imm32 r5, 0xa0050007; -imm32 r6, 0xa00600d0; -imm32 r7, 0xa00700d0; -R0 = ALIGN24 ( R0 , R5 ); -R1 = ALIGN24 ( R1 , R5 ); -R2 = ALIGN24 ( R2 , R5 ); -R3 = ALIGN24 ( R3 , R5 ); -R4 = ALIGN24 ( R4 , R5 ); -R6 = ALIGN24 ( R6 , R5 ); -R7 = ALIGN24 ( R7 , R5 ); -R5 = ALIGN24 ( R5 , R5 ); -CHECKREG r0, 0x0100D0A0; -CHECKREG r1, 0x0100D1A0; -CHECKREG r2, 0x0200D0A0; -CHECKREG r3, 0x0300D0A0; -CHECKREG r4, 0x0400D0A0; -CHECKREG r5, 0x050007A0; -CHECKREG r6, 0x0600D0A0; -CHECKREG r7, 0x0700D0A0; - -imm32 r0, 0xb2010000; -imm32 r1, 0xb0310000; -imm32 r2, 0xb042000f; -imm32 r3, 0xbf030000; -imm32 r4, 0xba040000; -imm32 r5, 0xbb050000; -imm32 r6, 0xbc060009; -imm32 r7, 0xb0e70000; -R0 = ALIGN24 ( R0 , R6 ); -R1 = ALIGN24 ( R1 , R6 ); -R2 = ALIGN24 ( R2 , R6 ); -R3 = ALIGN24 ( R3 , R6 ); -R4 = ALIGN24 ( R4 , R6 ); -R5 = ALIGN24 ( R5 , R6 ); -R6 = ALIGN24 ( R6 , R6 ); -R7 = ALIGN24 ( R7 , R6 ); -CHECKREG r0, 0x010000BC; -CHECKREG r1, 0x310000BC; -CHECKREG r2, 0x42000FBC; -CHECKREG r3, 0x030000BC; -CHECKREG r4, 0x040000BC; -CHECKREG r5, 0x050000BC; -CHECKREG r6, 0x060009BC; -CHECKREG r7, 0xE7000006; - -imm32 r0, 0xd23100e0; -imm32 r1, 0xd04500e0; -imm32 r2, 0xde32f0e0; -imm32 r3, 0xd90300e0; -imm32 r4, 0xd07400e0; -imm32 r5, 0xdef500e0; -imm32 r6, 0xd06600e0; -imm32 r7, 0xd0080023; -R1 = ALIGN24 ( R0 , R7 ); -R2 = ALIGN24 ( R1 , R7 ); -R3 = ALIGN24 ( R2 , R7 ); -R4 = ALIGN24 ( R3 , R7 ); -R5 = ALIGN24 ( R4 , R7 ); -R6 = ALIGN24 ( R5 , R7 ); -R7 = ALIGN24 ( R6 , R7 ); -R0 = ALIGN24 ( R7 , R7 ); -CHECKREG r0, 0xD0D0D0D0; -CHECKREG r1, 0x3100E0D0; -CHECKREG r2, 0x00E0D0D0; -CHECKREG r3, 0xE0D0D0D0; -CHECKREG r4, 0xD0D0D0D0; -CHECKREG r5, 0xD0D0D0D0; -CHECKREG r6, 0xD0D0D0D0; -CHECKREG r7, 0xD0D0D0D0; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_align8.s b/sim/testsuite/sim/bfin/c_dsp32shift_align8.s deleted file mode 100644 index ce1f82b..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_align8.s +++ /dev/null @@ -1,210 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_align8/c_dsp32shift_align8.dsp -// Spec Reference: dsp32shift align8 -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x00000001; -imm32 r1, 0x01000801; -imm32 r2, 0x08200802; -imm32 r3, 0x08030803; -imm32 r4, 0x08004804; -imm32 r5, 0x08000505; -imm32 r6, 0x08000866; -imm32 r7, 0x08000807; -R1 = ALIGN8 ( R1 , R0 ); -R2 = ALIGN8 ( R2 , R0 ); -R3 = ALIGN8 ( R3 , R0 ); -R4 = ALIGN8 ( R4 , R0 ); -R5 = ALIGN8 ( R5 , R0 ); -R6 = ALIGN8 ( R6 , R0 ); -R7 = ALIGN8 ( R7 , R0 ); -R0 = ALIGN8 ( R0 , R0 ); -CHECKREG r0, 0x01000000; -CHECKREG r1, 0x01000000; -CHECKREG r2, 0x02000000; -CHECKREG r3, 0x03000000; -CHECKREG r4, 0x04000000; -CHECKREG r5, 0x05000000; -CHECKREG r6, 0x66000000; -CHECKREG r7, 0x07000000; - -imm32 r0, 0x0900d001; -imm32 r1, 0x09000002; -imm32 r2, 0x09400002; -imm32 r3, 0x09100003; -imm32 r4, 0x09020004; -imm32 r5, 0x09003005; -imm32 r6, 0x09000406; -imm32 r7, 0x09000057; -R0 = ALIGN8 ( R0 , R1 ); -R2 = ALIGN8 ( R2 , R1 ); -R3 = ALIGN8 ( R3 , R1 ); -R4 = ALIGN8 ( R4 , R1 ); -R5 = ALIGN8 ( R5 , R1 ); -R6 = ALIGN8 ( R6 , R1 ); -R7 = ALIGN8 ( R7 , R1 ); -R1 = ALIGN8 ( R1 , R1 ); -CHECKREG r0, 0x01090000; -CHECKREG r1, 0x02090000; -CHECKREG r2, 0x02090000; -CHECKREG r3, 0x03090000; -CHECKREG r4, 0x04090000; -CHECKREG r5, 0x05090000; -CHECKREG r6, 0x06090000; -CHECKREG r7, 0x57090000; - - -imm32 r0, 0x0a00e001; -imm32 r1, 0x0a00e001; -imm32 r2, 0x0a00000f; -imm32 r3, 0x0a400010; -imm32 r4, 0x0a05e004; -imm32 r5, 0x0a006005; -imm32 r6, 0x0a00e706; -imm32 r7, 0x0a00e087; -R0 = ALIGN8 ( R0 , R2 ); -R1 = ALIGN8 ( R1 , R2 ); -R3 = ALIGN8 ( R3 , R2 ); -R4 = ALIGN8 ( R4 , R2 ); -R5 = ALIGN8 ( R5 , R2 ); -R6 = ALIGN8 ( R6 , R2 ); -R7 = ALIGN8 ( R7 , R2 ); -R2 = ALIGN8 ( R2 , R2 ); -CHECKREG r0, 0x010A0000; -CHECKREG r1, 0x010A0000; -CHECKREG r2, 0x0F0A0000; -CHECKREG r3, 0x100A0000; -CHECKREG r4, 0x040A0000; -CHECKREG r5, 0x050A0000; -CHECKREG r6, 0x060A0000; -CHECKREG r7, 0x870A0000; - -imm32 r0, 0x2b00f001; -imm32 r1, 0x0300f001; -imm32 r2, 0x0b40f002; -imm32 r3, 0x0b050010; -imm32 r4, 0x0b006004; -imm32 r5, 0x0b00f705; -imm32 r6, 0x0b00f086; -imm32 r7, 0x0b00f009; -R0 = ALIGN8 ( R0 , R3 ); -R1 = ALIGN8 ( R1 , R3 ); -R2 = ALIGN8 ( R2 , R3 ); -R4 = ALIGN8 ( R4 , R3 ); -R5 = ALIGN8 ( R5 , R3 ); -R6 = ALIGN8 ( R6 , R3 ); -R7 = ALIGN8 ( R7 , R3 ); -R3 = ALIGN8 ( R3 , R3 ); -CHECKREG r0, 0x010B0500; -CHECKREG r1, 0x010B0500; -CHECKREG r2, 0x020B0500; -CHECKREG r3, 0x100B0500; -CHECKREG r4, 0x040B0500; -CHECKREG r5, 0x050B0500; -CHECKREG r6, 0x860B0500; -CHECKREG r7, 0x090B0500; - -imm32 r0, 0x4c0000c0; -imm32 r1, 0x050100c0; -imm32 r2, 0x0c6200c0; -imm32 r3, 0x0c0700c0; -imm32 r4, 0x0c04800c; -imm32 r5, 0x0c0509c0; -imm32 r6, 0x0c060000; -imm32 r7, 0x0c0700ca; -R0 = ALIGN8 ( R0 , R4 ); -R1 = ALIGN8 ( R1 , R4 ); -R2 = ALIGN8 ( R2 , R4 ); -R3 = ALIGN8 ( R3 , R4 ); -R5 = ALIGN8 ( R5 , R4 ); -R6 = ALIGN8 ( R6 , R4 ); -R7 = ALIGN8 ( R7 , R4 ); -R4 = ALIGN8 ( R4 , R4 ); -CHECKREG r0, 0xC00C0480; -CHECKREG r1, 0xC00C0480; -CHECKREG r2, 0xC00C0480; -CHECKREG r3, 0xC00C0480; -CHECKREG r4, 0x0C0C0480; -CHECKREG r5, 0xC00C0480; -CHECKREG r6, 0x000C0480; -CHECKREG r7, 0xCA0C0480; - -imm32 r0, 0xa00100d0; -imm32 r1, 0xa00100d1; -imm32 r2, 0xa00200d0; -imm32 r3, 0xa00300d0; -imm32 r4, 0xa00400d0; -imm32 r5, 0xa0050007; -imm32 r6, 0xa00600d0; -imm32 r7, 0xa00700d0; -R0 = ALIGN8 ( R0 , R5 ); -R1 = ALIGN8 ( R1 , R5 ); -R2 = ALIGN8 ( R2 , R5 ); -R3 = ALIGN8 ( R3 , R5 ); -R4 = ALIGN8 ( R4 , R5 ); -R6 = ALIGN8 ( R6 , R5 ); -R7 = ALIGN8 ( R7 , R5 ); -R5 = ALIGN8 ( R5 , R5 ); -CHECKREG r0, 0xD0A00500; -CHECKREG r1, 0xD1A00500; -CHECKREG r2, 0xD0A00500; -CHECKREG r3, 0xD0A00500; -CHECKREG r4, 0xD0A00500; -CHECKREG r5, 0x07A00500; -CHECKREG r6, 0xD0A00500; -CHECKREG r7, 0xD0A00500; - -imm32 r0, 0xb2010000; -imm32 r1, 0xb0310000; -imm32 r2, 0xb042000f; -imm32 r3, 0xbf030000; -imm32 r4, 0xba040000; -imm32 r5, 0xbb050000; -imm32 r6, 0xbc060009; -imm32 r7, 0xb0e70000; -R0 = ALIGN8 ( R0 , R6 ); -R1 = ALIGN8 ( R1 , R6 ); -R2 = ALIGN8 ( R2 , R6 ); -R3 = ALIGN8 ( R3 , R6 ); -R4 = ALIGN8 ( R4 , R6 ); -R5 = ALIGN8 ( R5 , R6 ); -R6 = ALIGN8 ( R6 , R6 ); -R7 = ALIGN8 ( R7 , R6 ); -CHECKREG r0, 0x00BC0600; -CHECKREG r1, 0x00BC0600; -CHECKREG r2, 0x0FBC0600; -CHECKREG r3, 0x00BC0600; -CHECKREG r4, 0x00BC0600; -CHECKREG r5, 0x00BC0600; -CHECKREG r6, 0x09BC0600; -CHECKREG r7, 0x0009BC06; - -imm32 r0, 0xd23100e0; -imm32 r1, 0xd04500e0; -imm32 r2, 0xde32f0e0; -imm32 r3, 0xd90300e0; -imm32 r4, 0xd07400e0; -imm32 r5, 0xdef500e0; -imm32 r6, 0xd06600e0; -imm32 r7, 0xd0080023; -R1 = ALIGN8 ( R0 , R7 ); -R2 = ALIGN8 ( R1 , R7 ); -R3 = ALIGN8 ( R2 , R7 ); -R4 = ALIGN8 ( R3 , R7 ); -R5 = ALIGN8 ( R4 , R7 ); -R6 = ALIGN8 ( R5 , R7 ); -R7 = ALIGN8 ( R6 , R7 ); -R0 = ALIGN8 ( R7 , R7 ); -CHECKREG r0, 0x0000D008; -CHECKREG r1, 0xE0D00800; -CHECKREG r2, 0x00D00800; -CHECKREG r3, 0x00D00800; -CHECKREG r4, 0x00D00800; -CHECKREG r5, 0x00D00800; -CHECKREG r6, 0x00D00800; -CHECKREG r7, 0x00D00800; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_amix.s b/sim/testsuite/sim/bfin/c_dsp32shift_amix.s deleted file mode 100644 index af59e3f..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_amix.s +++ /dev/null @@ -1,142 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_amix/c_dsp32shift_amix.dsp -// Spec Reference: dsp32shift ashift mix -# mach: bfin - -.include "testutils.inc" - start - -// Ashift (Arithmetic ) retain the sign bit (0-->0, 1-->1) - -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -// Ashift : positive data, count (+)=left (half reg) -imm32 r0, 0x00010001; -imm32 r1, 1; -imm32 r2, 0x00020002; -imm32 r3, 2; -R4.H = ASHIFT R0.H BY R1.L; -R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x00020002 */ -R5.H = ASHIFT R2.H BY R3.L; -R5.L = ASHIFT R2.L BY R3.L; /* r5 = 0x00080008 */ -R6 = ASHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */ -R7 = ASHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */ -CHECKREG r4, 0x00020002; -CHECKREG r5, 0x00080008; -CHECKREG r6, 0x00020002; -CHECKREG r7, 0x00080008; - -// Ashift : (full reg) -imm32 r1, 3; -imm32 r3, 4; -R6 = ASHIFT R0 BY R1.L; /* r6 = 0x00080010 */ -R7 = ASHIFT R2 BY R3.L; -CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ -CHECKREG r7, 0x00200020; - -A0 = 0; -A0.L = R0.L; -A0.H = R0.H; -A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00080008 */ -R5 = A0.w; /* r5 = 0x00080008 */ - -CHECKREG r5, 0x00080008; -imm32 r4, 0x30000003; -imm32 r1, 1; -R5 = ASHIFT R4 BY R1.L; /* r5 = 0x60000006 */ -CHECKREG r5, 0x60000006; -imm32 r1, 2; -R5 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */ -CHECKREG r5, 0xc000000c; - - -// Ashift : count (-)=right (half reg) -imm32 r0, 0x10001000; -imm32 r1, -1; -imm32 r2, 0x10001000; -imm32 r3, -2; -R4.H = ASHIFT R0.H BY R1.L; -R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x08000800 */ -R5.H = ASHIFT R2.H BY R3.L; -R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0x04000400 */ -R6 = ASHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */ -R7 = ASHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */ -CHECKREG r4, 0x08000800; -CHECKREG r5, 0x04000400; -CHECKREG r6, 0x08000800; -CHECKREG r7, 0x04000400; - -// Ashift : (full reg) -imm32 r1, -3; -imm32 r3, -4; -R6 = ASHIFT R0 BY R1.L; /* r6 = 0x02000200 */ -R7 = ASHIFT R2 BY R3.L; /* r7 = 0x01000100 */ -CHECKREG r6, 0x02000200; -CHECKREG r7, 0x01000100; - -// NEGATIVE -// Ashift : NEGATIVE data, count (+)=left (half reg) -imm32 r0, 0xc00f800f; -imm32 r1, 1; -imm32 r2, 0xe00fe00f; -imm32 r3, 2; -R4.H = ASHIFT R0.H BY R1.L; -R4.L = ASHIFT R0.L BY R1.L (S); /* r4 = 0x801e801e */ -R5.H = ASHIFT R2.H BY R3.L; -R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0x803c803c */ -CHECKREG r4, 0x801e8000; -CHECKREG r5, 0x803c803c; - -imm32 r0, 0xc80fe00f; -imm32 r2, 0xe40fe00f; -imm32 r1, 4; -imm32 r3, 5; -R6 = ASHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */ -R7 = ASHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */ -CHECKREG r6, 0x80fe00f0; -CHECKREG r7, 0x81fc01e0; - -imm32 r0, 0xf80fe00f; -imm32 r2, 0xfc0fe00f; -R6 = ASHIFT R0 BY R1.L (S); /* r6 = 0x80fe00f0 */ -R7 = ASHIFT R2 BY R3.L (S); /* r7 = 0x81fc01e0 */ -CHECKREG r6, 0x80fe00f0; -CHECKREG r7, 0x81fc01e0; - -imm32 r0, 0xc80fe00f; -imm32 r2, 0xe40fe00f; -R6 = ASHIFT R0 BY R1.L (S); /* r6 = 0x80000000 zero bubble tru MSB */ -R7 = ASHIFT R2 BY R3.L (S); /* r7 = 0x80000000 */ -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x80000000; - - -// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok -imm32 r0, 0x80f080f0; -imm32 r1, -1; -imm32 r2, 0x80f080f0; -imm32 r3, -2; -R4.H = ASHIFT R0.H BY R1.L; -R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0xc078c078 */ -R5.H = ASHIFT R2.H BY R3.L; -R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0xe03ce03c */ -CHECKREG r4, 0xc078c078; -CHECKREG r5, 0xe03ce03c; -R6 = ASHIFT R0 BY R1.L (V); /* r6 = 0xc078c078 */ -R7 = ASHIFT R2 BY R3.L (V); /* r7 = 0xe03ce03c */ -CHECKREG r6, 0xc078c078; -CHECKREG r7, 0xe03ce03c; - -// Ashift : (full reg) -imm32 r1, -3; -imm32 r3, -4; -R6 = ASHIFT R0 BY R1.L; /* r6 = 0xf01e101e */ -R7 = ASHIFT R2 BY R3.L; /* r7 = 0xf80f080f */ -CHECKREG r6, 0xf01e101e; -CHECKREG r7, 0xf80f080f; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_bitmux.s b/sim/testsuite/sim/bfin/c_dsp32shift_bitmux.s deleted file mode 100644 index d962b27..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_bitmux.s +++ /dev/null @@ -1,486 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_bitmux/c_dsp32shift_bitmux.dsp -// Spec Reference: dsp32shift bitmux -# mach: bfin - - .include "testutils.inc" - - start - - A0 = 0; - imm32 r0, 0x01230000; - imm32 r1, 0x12340678; - imm32 r2, 0x23450089; - imm32 r3, 0x3456089a; - imm32 r4, 0x456709ab; - imm32 r5, 0x56780abc; - imm32 r6, 0x67890bcd; - imm32 r7, 0x789a0cde; -//r0, r0, a0 >>= bitmux; invalid now - BITMUX( R0 , R1, A0) (ASR); - BITMUX( R0 , R2, A0) (ASR); - BITMUX( R0 , R3, A0) (ASR); - BITMUX( R0 , R4, A0) (ASR); - BITMUX( R0 , R5, A0) (ASR); - BITMUX( R0 , R6, A0) (ASR); - BITMUX( R0 , R7, A0) (ASR); - CHECKREG r1, 0x091A033C; - CHECKREG r0, 0x00024600; - CHECKREG r2, 0x11A28044; - CHECKREG r3, 0x1A2B044D; - CHECKREG r4, 0x22B384D5; - CHECKREG r5, 0x2B3C055E; - CHECKREG r6, 0x33C485E6; - CHECKREG r7, 0x3C4D066F; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0x20000000; - CHECKREG r1, 0x00000022; - - imm32 r0, 0x01231001; - imm32 r1, 0x12341678; - imm32 r2, 0x13451789; - imm32 r3, 0x1456189a; - imm32 r4, 0x156711ab; - imm32 r5, 0x16781abc; - imm32 r6, 0x17891bcd; - imm32 r7, 0x189a1cde; - BITMUX( R1 , R0, A0) (ASR); -//r1, r1, a0 >>= bitmux; - BITMUX( R1 , R2, A0) (ASR); - BITMUX( R1 , R3, A0) (ASR); - BITMUX( R1 , R4, A0) (ASR); - BITMUX( R1 , R5, A0) (ASR); - BITMUX( R1 , R6, A0) (ASR); - BITMUX( R1 , R7, A0) (ASR); - CHECKREG r0, 0x00918800; - CHECKREG r1, 0x0024682C; - CHECKREG r2, 0x09A28BC4; - CHECKREG r3, 0x0A2B0C4D; - CHECKREG r4, 0x0AB388D5; - CHECKREG r5, 0x0B3C0D5E; - CHECKREG r6, 0x0BC48DE6; - CHECKREG r7, 0x0C4D0E6F; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0x28888000; - CHECKREG r1, 0x00000077; - - imm32 r0, 0x31232002; - imm32 r1, 0x22342678; - imm32 r2, 0x23452789; - imm32 r3, 0x2456289a; - imm32 r4, 0x256729ab; - imm32 r5, 0x26782abc; - imm32 r6, 0x27892bcd; - imm32 r7, 0x289a2cde; - BITMUX( R2 , R0, A0) (ASR); - BITMUX( R2 , R1, A0) (ASR); -//r2, r2, a0 >>= bitmux; - BITMUX( R2 , R3, A0) (ASR); - BITMUX( R2 , R4, A0) (ASR); - BITMUX( R2 , R5, A0) (ASR); - BITMUX( R2 , R6, A0) (ASR); - BITMUX( R2 , R7, A0) (ASR); - CHECKREG r0, 0x18919001; - CHECKREG r1, 0x111A133C; - CHECKREG r2, 0x00468A4F; - CHECKREG r3, 0x122B144D; - CHECKREG r4, 0x12B394D5; - CHECKREG r5, 0x133C155E; - CHECKREG r6, 0x13C495E6; - CHECKREG r7, 0x144D166F; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0x05DCA222; - CHECKREG r1, 0x00000023; - - imm32 r0, 0x31230003; - imm32 r1, 0x32345378; - imm32 r2, 0x33456389; - imm32 r3, 0x3456739a; - imm32 r4, 0x356783ab; - imm32 r5, 0x367893bc; - imm32 r6, 0x3789a3cd; - imm32 r7, 0x389ab3de; - BITMUX( R3 , R0, A0) (ASR); - BITMUX( R3 , R1, A0) (ASR); - BITMUX( R3 , R2, A0) (ASR); -//r3, r3, a0 >>= bitmux; - BITMUX( R3 , R4, A0) (ASR); - BITMUX( R3 , R5, A0) (ASR); - BITMUX( R3 , R6, A0) (ASR); - BITMUX( R3 , R7, A0) (ASR); - CHECKREG r0, 0x18918001; - CHECKREG r1, 0x191A29BC; - CHECKREG r2, 0x19A2B1C4; - CHECKREG r3, 0x0068ACE7; - CHECKREG r4, 0x1AB3C1D5; - CHECKREG r5, 0x1B3C49DE; - CHECKREG r6, 0x1BC4D1E6; - CHECKREG r7, 0x1C4D59EF; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0x988C1772; - CHECKREG r1, 0x00000027; - - imm32 r0, 0x41230044; - imm32 r1, 0x42345648; - imm32 r2, 0x43456749; - imm32 r3, 0x4456784a; - imm32 r4, 0x4567894b; - imm32 r5, 0x46789a4c; - imm32 r6, 0x4789ab4d; - imm32 r7, 0x489abc44; - BITMUX( R4 , R0, A0) (ASR); - BITMUX( R4 , R1, A0) (ASR); - BITMUX( R4 , R2, A0) (ASR); - BITMUX( R4 , R3, A0) (ASR); -//r4, r4, a0 >>= bitmux; - BITMUX( R4 , R5, A0) (ASR); - BITMUX( R4 , R6, A0) (ASR); - BITMUX( R4 , R7, A0) (ASR); - CHECKREG r0, 0x20918022; - CHECKREG r1, 0x211A2B24; - CHECKREG r2, 0x21A2B3A4; - CHECKREG r3, 0x222B3C25; - CHECKREG r4, 0x008ACF12; - CHECKREG r5, 0x233C4D26; - CHECKREG r6, 0x23C4D5A6; - CHECKREG r7, 0x244D5E22; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0x949E6230; - CHECKREG r1, 0x00000061; - - imm32 r0, 0x51235005; - imm32 r1, 0x52345678; - imm32 r2, 0x53455789; - imm32 r3, 0x5456589a; - imm32 r4, 0x556759ab; - imm32 r5, 0x56785abc; - imm32 r6, 0x57895bcd; - imm32 r7, 0x589a5cde; - BITMUX( R5 , R0, A0) (ASR); - BITMUX( R5 , R1, A0) (ASR); - BITMUX( R5 , R2, A0) (ASR); - BITMUX( R5 , R3, A0) (ASR); - BITMUX( R5 , R4, A0) (ASR); -//r5, r5, a0 >>= bitmux; - BITMUX( R5 , R6, A0) (ASR); - BITMUX( R5 , R7, A0) (ASR); - CHECKREG r0, 0x2891A802; - CHECKREG r1, 0x291A2B3C; - CHECKREG r2, 0x29A2ABC4; - CHECKREG r3, 0x2A2B2C4D; - CHECKREG r4, 0x2AB3ACD5; - CHECKREG r5, 0x00ACF0B5; - CHECKREG r6, 0x2BC4ADE6; - CHECKREG r7, 0x2C4D2E6F; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0xC9865279; - CHECKREG r1, 0x0000003D; - - imm32 r0, 0x61260006; - imm32 r1, 0x62365678; - imm32 r2, 0x63466789; - imm32 r3, 0x6456789a; - imm32 r4, 0x656689ab; - imm32 r5, 0x66786abc; - imm32 r6, 0x6786abcd; - imm32 r7, 0x6896bcde; - BITMUX( R6 , R0, A0) (ASR); - BITMUX( R6 , R1, A0) (ASR); - BITMUX( R6 , R2, A0) (ASR); - BITMUX( R6 , R3, A0) (ASR); - BITMUX( R6 , R4, A0) (ASR); - BITMUX( R6 , R5, A0) (ASR); -//r6, r6, a0 >>= bitmux; - BITMUX( R6 , R7, A0) (ASR); - CHECKREG r0, 0x30930003; - CHECKREG r1, 0x311B2B3C; - CHECKREG r2, 0x31A333C4; - CHECKREG r3, 0x322B3C4D; - CHECKREG r4, 0x32B344D5; - CHECKREG r5, 0x333C355E; - CHECKREG r6, 0x00CF0D57; - CHECKREG r7, 0x344B5E6F; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0xC4F72619; - CHECKREG r1, 0x00000049; - - imm32 r0, 0x71730007; - imm32 r1, 0x72745678; - imm32 r2, 0x73756789; - imm32 r3, 0x7476789a; - imm32 r4, 0x757789ab; - imm32 r5, 0x76789abc; - imm32 r6, 0x7779abcd; - imm32 r7, 0x777abcde; - BITMUX( R7 , R0, A0) (ASR); - BITMUX( R7 , R1, A0) (ASR); - BITMUX( R7 , R2, A0) (ASR); - BITMUX( R7 , R3, A0) (ASR); - BITMUX( R7 , R4, A0) (ASR); - BITMUX( R7 , R5, A0) (ASR); - BITMUX( R7 , R6, A0) (ASR); -//r7, r7, a0 >>= bitmux; - CHECKREG r0, 0x38B98003; - CHECKREG r1, 0x393A2B3C; - CHECKREG r2, 0x39BAB3C4; - CHECKREG r3, 0x3A3B3C4D; - CHECKREG r4, 0x3ABBC4D5; - CHECKREG r5, 0x3B3C4D5E; - CHECKREG r6, 0x3BBCD5E6; - CHECKREG r7, 0x00EEF579; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0xD92713DC; - CHECKREG r1, 0xFFFFFFCD; - - imm32 r0, 0x08230080; - imm32 r1, 0x18345688; - imm32 r2, 0x28456789; - imm32 r3, 0x3856788a; - imm32 r4, 0x4867898b; - imm32 r5, 0x58789a8c; - imm32 r6, 0x6889ab8d; - imm32 r7, 0x789abc8e; -//r0, r0, a0 <<= bitmux; - BITMUX( R0 , R1, A0) (ASL); - BITMUX( R0 , R2, A0) (ASL); - BITMUX( R0 , R3, A0) (ASL); - BITMUX( R0 , R4, A0) (ASL); - BITMUX( R0 , R5, A0) (ASL); - BITMUX( R0 , R6, A0) (ASL); - BITMUX( R0 , R7, A0) (ASL); - CHECKREG r1, 0x3068AD10; - CHECKREG r0, 0x11804000; - CHECKREG r2, 0x508ACF12; - CHECKREG r3, 0x70ACF114; - CHECKREG r4, 0x90CF1316; - CHECKREG r5, 0xB0F13518; - CHECKREG r6, 0xD113571A; - CHECKREG r7, 0xF135791C; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0xC4F70010; - CHECKREG r1, 0x00000049; - - imm32 r0, 0x09230009; - imm32 r1, 0x19345679; - imm32 r2, 0x29456789; - imm32 r3, 0x39567899; - imm32 r4, 0x496789a9; - imm32 r5, 0x59789ab9; - imm32 r6, 0x6989abc9; - imm32 r7, 0x799abcd9; - BITMUX( R1 , R0, A0) (ASL); -//r1, r1, a0 <<= bitmux; - BITMUX( R1 , R2, A0) (ASL); - BITMUX( R1 , R3, A0) (ASL); - BITMUX( R1 , R4, A0) (ASL); - BITMUX( R1 , R5, A0) (ASL); - BITMUX( R1 , R6, A0) (ASL); - BITMUX( R1 , R7, A0) (ASL); - CHECKREG r0, 0x12460012; - CHECKREG r1, 0x9A2B3C80; - CHECKREG r2, 0x528ACF12; - CHECKREG r3, 0x72ACF132; - CHECKREG r4, 0x92CF1352; - CHECKREG r5, 0xB2F13572; - CHECKREG r6, 0xD3135792; - CHECKREG r7, 0xF33579B2; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0xC0040050; - CHECKREG r1, 0x0000003D; - - imm32 r0, 0x0a23000a; - imm32 r1, 0x1a34567a; - imm32 r2, 0x2a45678a; - imm32 r3, 0x3a56789a; - imm32 r4, 0x4a6789aa; - imm32 r5, 0x5aa89aba; - imm32 r6, 0x6a89abca; - imm32 r7, 0x7a9abcda; - BITMUX( R2 , R0, A0) (ASL); - BITMUX( R2 , R1, A0) (ASL); -//r2, r2, a0 <<= bitmux; - BITMUX( R2 , R3, A0) (ASL); - BITMUX( R2 , R4, A0) (ASL); - BITMUX( R2 , R5, A0) (ASL); - BITMUX( R2 , R6, A0) (ASL); - BITMUX( R2 , R7, A0) (ASL); - CHECKREG r0, 0x14460014; - CHECKREG r1, 0x3468ACF4; - CHECKREG r2, 0x22B3C500; - CHECKREG r3, 0x74ACF134; - CHECKREG r4, 0x94CF1354; - CHECKREG r5, 0xB5513574; - CHECKREG r6, 0xD5135794; - CHECKREG r7, 0xF53579B4; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0x00140111; - CHECKREG r1, 0x00000001; - - imm32 r0, 0x01b300b3; - imm32 r1, 0x12b456b8; - imm32 r2, 0x23b567b9; - imm32 r3, 0x34b678ba; - imm32 r4, 0x45b789bb; - imm32 r5, 0x56b89abc; - imm32 r6, 0x67b9abbd; - imm32 r7, 0x78babcbe; - BITMUX( R3 , R0, A0) (ASL); - BITMUX( R3 , R1, A0) (ASL); - BITMUX( R3 , R2, A0) (ASL); -//r3, r3, a0 <<= bitmux; - BITMUX( R3 , R4, A0) (ASL); - BITMUX( R3 , R5, A0) (ASL); - BITMUX( R3 , R6, A0) (ASL); - BITMUX( R3 , R7, A0) (ASL); - CHECKREG r0, 0x03660166; - CHECKREG r1, 0x2568AD70; - CHECKREG r2, 0x476ACF72; - CHECKREG r3, 0x5B3C5D00; - CHECKREG r4, 0x8B6F1376; - CHECKREG r5, 0xAD713578; - CHECKREG r6, 0xCF73577A; - CHECKREG r7, 0xF175797C; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0x00444144; - CHECKREG r1, 0x00000005; - - imm32 r0, 0x012300c4; - imm32 r1, 0x123456c8; - imm32 r2, 0x234567c9; - imm32 r3, 0x345678ca; - imm32 r4, 0x456789cb; - imm32 r5, 0x56789acc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcce; - BITMUX( R4 , R0, A0) (ASL); - BITMUX( R4 , R1, A0) (ASL); - BITMUX( R4 , R2, A0) (ASL); - BITMUX( R4 , R3, A0) (ASL); -//r4, r4, a0 <<= bitmux; - BITMUX( R4 , R5, A0) (ASL); - BITMUX( R4 , R6, A0) (ASL); - BITMUX( R4 , R7, A0) (ASL); - CHECKREG r0, 0x02460188; - CHECKREG r1, 0x2468AD90; - CHECKREG r2, 0x468ACF92; - CHECKREG r3, 0x68ACF194; - CHECKREG r4, 0xB3C4E580; - CHECKREG r5, 0xACF13598; - CHECKREG r6, 0xCF13579A; - CHECKREG r7, 0xF135799C; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0x10510404; - CHECKREG r1, 0x00000011; - - imm32 r0, 0x0c230d05; - imm32 r1, 0x1c345d78; - imm32 r2, 0x2c456d89; - imm32 r3, 0x3c567d9a; - imm32 r4, 0x4c678dab; - imm32 r5, 0x5c789dbc; - imm32 r6, 0x6c89adcd; - imm32 r7, 0x7c9abdde; - BITMUX( R5 , R0, A0) (ASL); - BITMUX( R5 , R1, A0) (ASL); - BITMUX( R5 , R2, A0) (ASL); - BITMUX( R5 , R3, A0) (ASL); - BITMUX( R5 , R4, A0) (ASL); -//r5, r5, a0 <<= bitmux; - BITMUX( R5 , R6, A0) (ASL); - BITMUX( R5 , R7, A0) (ASL); - CHECKREG r0, 0x18461A0A; - CHECKREG r1, 0x3868BAF0; - CHECKREG r2, 0x588ADB12; - CHECKREG r3, 0x78ACFB34; - CHECKREG r4, 0x98CF1B56; - CHECKREG r5, 0x3C4EDE00; - CHECKREG r6, 0xD9135B9A; - CHECKREG r7, 0xF9357BBC; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0x41010454; - CHECKREG r1, 0x00000014; - - imm32 r0, 0x0d230e06; - imm32 r1, 0x1d345e78; - imm32 r2, 0x2d456e89; - imm32 r3, 0x3d567e9a; - imm32 r4, 0x4d678eab; - imm32 r5, 0x5d789ebc; - imm32 r6, 0x6d89aecd; - imm32 r7, 0x7d9abede; - BITMUX( R6 , R0, A0) (ASL); - BITMUX( R6 , R1, A0) (ASL); - BITMUX( R6 , R2, A0) (ASL); - BITMUX( R6 , R3, A0) (ASL); - BITMUX( R6 , R4, A0) (ASL); - BITMUX( R6 , R5, A0) (ASL); -//r6, r6, a0 <<= bitmux; - BITMUX( R6 , R7, A0) (ASL); - CHECKREG r0, 0x1A461C0C; - CHECKREG r1, 0x3A68BCF0; - CHECKREG r2, 0x5A8ADD12; - CHECKREG r3, 0x7AACFD34; - CHECKREG r4, 0x9ACF1D56; - CHECKREG r5, 0xBAF13D78; - CHECKREG r6, 0xC4D76680; - CHECKREG r7, 0xFB357DBC; - - R0 = A0.w; - R1 = A0.x; - CHECKREG r0, 0x41150514; - CHECKREG r1, 0x00000040; - - imm32 r0, 0x01230007; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - BITMUX( R7 , R0, A0) (ASL); - BITMUX( R7 , R1, A0) (ASL); - BITMUX( R7 , R2, A0) (ASL); - BITMUX( R7 , R3, A0) (ASL); - BITMUX( R7 , R4, A0) (ASL); - BITMUX( R7 , R5, A0) (ASL); - BITMUX( R7 , R6, A0) (ASL); -//r7, r7, a0 <<= bitmux; - - CHECKREG r0, 0x0246000E; - CHECKREG r1, 0x2468ACF0; - CHECKREG r2, 0x468ACF12; - CHECKREG r3, 0x68ACF134; - CHECKREG r4, 0x8ACF1356; - CHECKREG r5, 0xACF13578; - CHECKREG r6, 0xCF13579A; - CHECKREG r7, 0x4D5E6F00; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_bxor.s b/sim/testsuite/sim/bfin/c_dsp32shift_bxor.s deleted file mode 100644 index 18b148b..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_bxor.s +++ /dev/null @@ -1,126 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_bxor/c_dsp32shift_bxor.dsp -// Spec Reference: dsp32shift bxor -# mach: bfin - -.include "testutils.inc" - start - -R0 = 0; -R1 = 58; -A0 = R1; -ASTAT = R0; - - -imm32 r0, 0x12345678; -imm32 r1, 0x22334455; -imm32 r2, 0x66778890; -imm32 r3, 0xaabbccdd; -imm32 r4, 0x34567890; -imm32 r5, 0xa2d3d5f6; -imm32 r6, 0x456bda06; -imm32 r7, 0x56789abc; -R0.L = CC = BXORSHIFT( A0 , R0 ); -R1.L = CC = BXORSHIFT( A0 , R1 ); -R2.L = CC = BXORSHIFT( A0 , R2 ); -R3.L = CC = BXORSHIFT( A0 , R3 ); -R4.L = CC = BXORSHIFT( A0 , R4 ); -R5.L = CC = BXORSHIFT( A0 , R5 ); -R6.L = CC = BXORSHIFT( A0 , R6 ); -R7.L = CC = BXORSHIFT( A0 , R7 ); -CHECKREG r0, 0x12340001; -CHECKREG r1, 0x22330001; -CHECKREG r2, 0x66770000; -CHECKREG r3, 0xAABB0001; -CHECKREG r4, 0x34560000; -CHECKREG r5, 0xA2D30000; -CHECKREG r6, 0x456B0000; -CHECKREG r7, 0x56780001; - -imm32 r0, 0xa1001001; -imm32 r1, 0x1b001001; -imm32 r2, 0x11c01002; -imm32 r3, 0x110d1003; -imm32 r4, 0x1100e004; -imm32 r5, 0x11001f05; -imm32 r6, 0x11001006; -imm32 r7, 0x11001001; -R5.L = CC = BXORSHIFT( A0 , R0 ); -R4.L = CC = BXORSHIFT( A0 , R1 ); -R2.L = CC = BXORSHIFT( A0 , R2 ); -R7.L = CC = BXORSHIFT( A0 , R3 ); -R0.L = CC = BXORSHIFT( A0 , R4 ); -R1.L = CC = BXORSHIFT( A0 , R5 ); -R3.L = CC = BXORSHIFT( A0 , R6 ); -R6.L = CC = BXORSHIFT( A0 , R7 ); -CHECKREG r0, 0xA1000000; -CHECKREG r1, 0x1B000000; -CHECKREG r2, 0x11C00001; -CHECKREG r3, 0x110D0000; -CHECKREG r4, 0x11000000; -CHECKREG r5, 0x11000001; -CHECKREG r6, 0x11000000; -CHECKREG r7, 0x11000001; - -imm32 r0, 0xa2001001; -imm32 r1, 0x1b341001; -imm32 r2, 0x71c01002; -imm32 r3, 0x810d1003; -imm32 r4, 0x1600e004; -imm32 r5, 0x41001405; -imm32 r6, 0x31003006; -imm32 r7, 0x21004671; -R2.L = CC = BXOR( A0 , R0 ); -R3.L = CC = BXOR( A0 , R1 ); -R5.L = CC = BXOR( A0 , R2 ); -R6.L = CC = BXOR( A0 , R3 ); -R0.L = CC = BXOR( A0 , R4 ); -R1.L = CC = BXOR( A0 , R5 ); -R7.L = CC = BXOR( A0 , R6 ); -R4.L = CC = BXOR( A0 , R7 ); -CHECKREG r0, 0xA2000000; -CHECKREG r1, 0x1B340000; -CHECKREG r2, 0x71C00000; -CHECKREG r3, 0x810D0000; -CHECKREG r4, 0x16000000; -CHECKREG r5, 0x41000000; -CHECKREG r6, 0x31000001; -CHECKREG r7, 0x21000000; - -imm32 r0, 0x4a502001; -imm32 r1, 0x6b343001; -imm32 r2, 0x71c04002; -imm32 r3, 0x810d5003; -imm32 r4, 0x5600e004; -imm32 r5, 0x47001405; -imm32 r6, 0x91003006; -imm32 r7, 0xa1004671; -A1 = R3; -R0.L = CC = BXOR( A0 , A1, CC ); -A0 = BXORSHIFT( A0 , A1, CC ); -R1.L = CC = BXOR( A0 , A1, CC ); -A0 = BXORSHIFT( A0 , A1, CC ); -R2.L = CC = BXOR( A0 , A1, CC ); -A0 = BXORSHIFT( A0 , A1, CC ); -R3.L = CC = BXOR( A0 , A1, CC ); -A0 = BXORSHIFT( A0 , A1, CC ); -R4.L = CC = BXOR( A0 , A1, CC ); -A0 = BXORSHIFT( A0 , A1, CC ); -R5.L = CC = BXOR( A0 , A1, CC ); -A0 = BXORSHIFT( A0 , A1, CC ); -R6.L = CC = BXOR( A0 , A1, CC ); -A0 = BXORSHIFT( A0 , A1, CC ); -R7.L = CC = BXOR( A0 , A1, CC ); -A0 = BXORSHIFT( A0 , A1, CC ); -CHECKREG r0, 0x4A500001; -CHECKREG r1, 0x6B340000; -CHECKREG r2, 0x71C00000; -CHECKREG r3, 0x810D0000; -CHECKREG r4, 0x56000001; -CHECKREG r5, 0x47000000; -CHECKREG r6, 0x91000001; -CHECKREG r7, 0xA1000001; - - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_expadj_h.s b/sim/testsuite/sim/bfin/c_dsp32shift_expadj_h.s deleted file mode 100644 index 30ecd61..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_expadj_h.s +++ /dev/null @@ -1,214 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_expadj_h/c_dsp32shift_expadj_h.dsp -// Spec Reference: dsp32shift expadj rh -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x80000008; -imm32 r1, 0x80010008; -imm32 r2, 0x80020008; -imm32 r3, 0x80030008; -imm32 r4, 0x80040008; -imm32 r5, 0x80050008; -imm32 r6, 0x80060008; -imm32 r7, 0x80070008; -R1.L = EXPADJ( R1.H , R0.L ); -R2.L = EXPADJ( R2.H , R0.L ); -R3.L = EXPADJ( R3.H , R0.L ); -R4.L = EXPADJ( R4.H , R0.L ); -R5.L = EXPADJ( R5.H , R0.L ); -R6.L = EXPADJ( R6.H , R0.L ); -R7.L = EXPADJ( R7.H , R0.L ); -R0.L = EXPADJ( R0.H , R0.L ); -CHECKREG r0, 0x80000000; -CHECKREG r1, 0x80010000; -CHECKREG r2, 0x80020000; -CHECKREG r3, 0x80030000; -CHECKREG r4, 0x80040000; -CHECKREG r5, 0x80050000; -CHECKREG r6, 0x80060000; -CHECKREG r7, 0x80070000; - -imm32 r0, 0x90010009; -imm32 r1, 0x00010009; -imm32 r2, 0x90020009; -imm32 r3, 0x90030009; -imm32 r4, 0x90040009; -imm32 r5, 0x90050009; -imm32 r6, 0x90060009; -imm32 r7, 0x90070009; -R0.L = EXPADJ( R0.H , R1.L ); -R2.L = EXPADJ( R2.H , R1.L ); -R3.L = EXPADJ( R3.H , R1.L ); -R4.L = EXPADJ( R4.H , R1.L ); -R5.L = EXPADJ( R5.H , R1.L ); -R6.L = EXPADJ( R6.H , R1.L ); -R7.L = EXPADJ( R7.H , R1.L ); -R1.L = EXPADJ( R1.H , R1.L ); -CHECKREG r0, 0x90010000; -CHECKREG r1, 0x00010009; -CHECKREG r2, 0x90020000; -CHECKREG r3, 0x90030000; -CHECKREG r4, 0x90040000; -CHECKREG r5, 0x90050000; -CHECKREG r6, 0x90060000; -CHECKREG r7, 0x90070000; - - -imm32 r0, 0xa001000a; -imm32 r1, 0xa001000a; -imm32 r2, 0xa002000a; -imm32 r3, 0xa003000a; -imm32 r4, 0xa004000a; -imm32 r5, 0xa005000a; -imm32 r6, 0xa006000a; -imm32 r7, 0xa007000a; -R0.L = EXPADJ( R0.H , R2.L ); -R1.L = EXPADJ( R1.H , R2.L ); -R3.L = EXPADJ( R3.H , R2.L ); -R4.L = EXPADJ( R4.H , R2.L ); -R5.L = EXPADJ( R5.H , R2.L ); -R6.L = EXPADJ( R6.H , R2.L ); -R7.L = EXPADJ( R7.H , R2.L ); -R2.L = EXPADJ( R2.H , R2.L ); -CHECKREG r0, 0xA0010000; -CHECKREG r1, 0xA0010000; -CHECKREG r2, 0xA0020000; -CHECKREG r3, 0xA0030000; -CHECKREG r4, 0xA0040000; -CHECKREG r5, 0xA0050000; -CHECKREG r6, 0xA0060000; -CHECKREG r7, 0xA0070000; - -imm32 r0, 0xc001000c; -imm32 r1, 0xc001000c; -imm32 r2, 0xc002000c; -imm32 r3, 0xc003001c; -imm32 r4, 0xc004000c; -imm32 r5, 0xc005000c; -imm32 r6, 0xc006000c; -imm32 r7, 0xc007000c; -R0.L = EXPADJ( R0.H , R3.L ); -R1.L = EXPADJ( R1.H , R3.L ); -R2.L = EXPADJ( R2.H , R3.L ); -R4.L = EXPADJ( R4.H , R3.L ); -R5.L = EXPADJ( R5.H , R3.L ); -R6.L = EXPADJ( R6.H , R3.L ); -R7.L = EXPADJ( R7.H , R3.L ); -R3.L = EXPADJ( R3.H , R3.L ); -CHECKREG r0, 0xC0010001; -CHECKREG r1, 0xC0010001; -CHECKREG r2, 0xC0020001; -CHECKREG r3, 0xC0030001; -CHECKREG r4, 0xC0040001; -CHECKREG r5, 0xC0050001; -CHECKREG r6, 0xC0060001; -CHECKREG r7, 0xC0070001; - -imm32 r0, 0xb0000008; -imm32 r1, 0xb0010008; -imm32 r2, 0xb0020008; -imm32 r3, 0xb0030008; -imm32 r4, 0xb0040008; -imm32 r5, 0xb0050008; -imm32 r6, 0xb0060008; -imm32 r7, 0xb0070008; -R0.L = EXPADJ( R1.H , R4.L ); -R1.L = EXPADJ( R2.H , R4.L ); -R2.L = EXPADJ( R3.H , R4.L ); -R3.L = EXPADJ( R4.H , R4.L ); -R5.L = EXPADJ( R5.H , R4.L ); -R6.L = EXPADJ( R6.H , R4.L ); -R7.L = EXPADJ( R7.H , R4.L ); -R4.L = EXPADJ( R0.H , R4.L ); -CHECKREG r0, 0xB0000000; -CHECKREG r1, 0xB0010000; -CHECKREG r2, 0xB0020000; -CHECKREG r3, 0xB0030000; -CHECKREG r4, 0xB0040000; -CHECKREG r5, 0xB0050000; -CHECKREG r6, 0xB0060000; -CHECKREG r7, 0xB0070000; - -imm32 r0, 0xc0010009; -imm32 r1, 0xc0010009; -imm32 r2, 0xc0020009; -imm32 r3, 0xc0030009; -imm32 r4, 0xc0040009; -imm32 r5, 0xc0050009; -imm32 r6, 0xc0060009; -imm32 r7, 0xc0070009; -R0.L = EXPADJ( R0.H , R5.L ); -R1.L = EXPADJ( R2.H , R5.L ); -R2.L = EXPADJ( R3.H , R5.L ); -R3.L = EXPADJ( R4.H , R5.L ); -R4.L = EXPADJ( R5.H , R5.L ); -R6.L = EXPADJ( R6.H , R5.L ); -R7.L = EXPADJ( R7.H , R5.L ); -R5.L = EXPADJ( R1.H , R5.L ); -CHECKREG r0, 0xC0010001; -CHECKREG r1, 0xC0010001; -CHECKREG r2, 0xC0020001; -CHECKREG r3, 0xC0030001; -CHECKREG r4, 0xC0040001; -CHECKREG r5, 0xC0050001; -CHECKREG r6, 0xC0060001; -CHECKREG r7, 0xC0070001; - - -imm32 r0, 0xe001000a; -imm32 r1, 0xe001000a; -imm32 r2, 0xe002000a; -imm32 r3, 0xe003000a; -imm32 r4, 0xe004000a; -imm32 r5, 0xe005000a; -imm32 r6, 0xe006000a; -imm32 r7, 0xe007000a; -R0.L = EXPADJ( R0.H , R6.L ); -R1.L = EXPADJ( R1.H , R6.L ); -R2.L = EXPADJ( R3.H , R6.L ); -R3.L = EXPADJ( R4.H , R6.L ); -R4.L = EXPADJ( R5.H , R6.L ); -R5.L = EXPADJ( R6.H , R6.L ); -R6.L = EXPADJ( R7.H , R6.L ); -R7.L = EXPADJ( R2.H , R6.L ); -CHECKREG r0, 0xE0010002; -CHECKREG r1, 0xE0010002; -CHECKREG r2, 0xE0020002; -CHECKREG r3, 0xE0030002; -CHECKREG r4, 0xE0040002; -CHECKREG r5, 0xE0050002; -CHECKREG r6, 0xE0060002; -CHECKREG r7, 0xE0070002; - -imm32 r0, 0xd001000c; -imm32 r1, 0xd001000c; -imm32 r2, 0xd002000c; -imm32 r3, 0xd003001c; -imm32 r4, 0xd004000c; -imm32 r5, 0xd005000c; -imm32 r6, 0xd006000c; -imm32 r7, 0xd007000c; -R0.L = EXPADJ( R0.H , R7.L ); -R1.L = EXPADJ( R1.H , R7.L ); -R2.L = EXPADJ( R2.H , R7.L ); -R3.L = EXPADJ( R4.H , R7.L ); -R4.L = EXPADJ( R5.H , R7.L ); -R5.L = EXPADJ( R6.H , R7.L ); -R6.L = EXPADJ( R7.H , R7.L ); -R7.L = EXPADJ( R3.H , R7.L ); -CHECKREG r0, 0xD0010001; -CHECKREG r1, 0xD0010001; -CHECKREG r2, 0xD0020001; -CHECKREG r3, 0xD0030001; -CHECKREG r4, 0xD0040001; -CHECKREG r5, 0xD0050001; -CHECKREG r6, 0xD0060001; -CHECKREG r7, 0xD0070001; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_expadj_l.s b/sim/testsuite/sim/bfin/c_dsp32shift_expadj_l.s deleted file mode 100644 index 237850b..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_expadj_l.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_expadj_l/c_dsp32shift_expadj_l.dsp -// Spec Reference: dsp32shift expadj rl -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x00000000; -imm32 r1, 0x0000c001; -imm32 r2, 0x0000c002; -imm32 r3, 0x0000c003; -imm32 r4, 0x0000c004; -imm32 r5, 0x0000c005; -imm32 r6, 0x0000c006; -imm32 r7, 0x0000c007; -R1.L = EXPADJ( R1.L , R0.L ); -R2.L = EXPADJ( R2.L , R0.L ); -R3.L = EXPADJ( R3.L , R0.L ); -R4.L = EXPADJ( R4.L , R0.L ); -R5.L = EXPADJ( R5.L , R0.L ); -R6.L = EXPADJ( R6.L , R0.L ); -R7.L = EXPADJ( R7.L , R0.L ); -R0.L = EXPADJ( R0.L , R0.L ); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x11001001; -imm32 r1, 0x11001001; -imm32 r2, 0x11001002; -imm32 r3, 0x11001003; -imm32 r4, 0x11001004; -imm32 r5, 0x11001005; -imm32 r6, 0x11001006; -imm32 r7, 0x11001007; -R0.L = EXPADJ( R0.L , R1.L ); -R2.L = EXPADJ( R2.L , R1.L ); -R3.L = EXPADJ( R3.L , R1.L ); -R4.L = EXPADJ( R4.L , R1.L ); -R5.L = EXPADJ( R5.L , R1.L ); -R6.L = EXPADJ( R6.L , R1.L ); -R7.L = EXPADJ( R7.L , R1.L ); -R1.L = EXPADJ( R1.L , R1.L ); -CHECKREG r0, 0x11001001; -CHECKREG r1, 0x11001001; -CHECKREG r2, 0x11001001; -CHECKREG r3, 0x11001001; -CHECKREG r4, 0x11001001; -CHECKREG r5, 0x11001001; -CHECKREG r6, 0x11001001; -CHECKREG r7, 0x11001001; - -imm32 r0, 0x2000c001; -imm32 r1, 0x2000d001; -imm32 r2, 0x2000000f; -imm32 r3, 0x2000e003; -imm32 r4, 0x2000f004; -imm32 r5, 0x2000f005; -imm32 r6, 0x2000f006; -imm32 r7, 0x2000f007; -R0.L = EXPADJ( R0.L , R2.L ); -R1.L = EXPADJ( R1.L , R2.L ); -R3.L = EXPADJ( R3.L , R2.L ); -R4.L = EXPADJ( R4.L , R2.L ); -R5.L = EXPADJ( R5.L , R2.L ); -R6.L = EXPADJ( R6.L , R2.L ); -R7.L = EXPADJ( R7.L , R2.L ); -R2.L = EXPADJ( R2.L , R2.L ); -CHECKREG r0, 0x20000001; -CHECKREG r1, 0x20000001; -CHECKREG r2, 0x2000000B; -CHECKREG r3, 0x20000002; -CHECKREG r4, 0x20000003; -CHECKREG r5, 0x20000003; -CHECKREG r6, 0x20000003; -CHECKREG r7, 0x20000003; - -imm32 r0, 0x30009001; -imm32 r1, 0x3000a001; -imm32 r2, 0x3000b002; -imm32 r3, 0x30000010; -imm32 r4, 0x3000c004; -imm32 r5, 0x3000d005; -imm32 r6, 0x3000e006; -imm32 r7, 0x3000f007; -R0.L = EXPADJ( R0.L , R3.L ); -R1.L = EXPADJ( R1.L , R3.L ); -R2.L = EXPADJ( R2.L , R3.L ); -R4.L = EXPADJ( R4.L , R3.L ); -R5.L = EXPADJ( R5.L , R3.L ); -R6.L = EXPADJ( R6.L , R3.L ); -R7.L = EXPADJ( R7.L , R3.L ); -R3.L = EXPADJ( R3.L , R3.L ); -CHECKREG r0, 0x30000010; -CHECKREG r1, 0x30000010; -CHECKREG r2, 0x30000010; -CHECKREG r3, 0x30000010; -CHECKREG r4, 0x30000010; -CHECKREG r5, 0x30000010; -CHECKREG r6, 0x30000010; -CHECKREG r7, 0x30000010; - -imm32 r0, 0x40000000; -imm32 r1, 0x4000c001; -imm32 r2, 0x4000c002; -imm32 r3, 0x4000c003; -imm32 r4, 0x4000c004; -imm32 r5, 0x4000c005; -imm32 r6, 0x4000c006; -imm32 r7, 0x4000c007; -R0.L = EXPADJ( R1.L , R4.L ); -R1.L = EXPADJ( R2.L , R4.L ); -R2.L = EXPADJ( R3.L , R4.L ); -R3.L = EXPADJ( R4.L , R4.L ); -R5.L = EXPADJ( R5.L , R4.L ); -R6.L = EXPADJ( R6.L , R4.L ); -R7.L = EXPADJ( R7.L , R4.L ); -R4.L = EXPADJ( R0.L , R4.L ); -CHECKREG r0, 0x40000001; -CHECKREG r1, 0x40000001; -CHECKREG r2, 0x40000001; -CHECKREG r3, 0x40000001; -CHECKREG r4, 0x4000C004; -CHECKREG r5, 0x40000001; -CHECKREG r6, 0x40000001; -CHECKREG r7, 0x40000001; - -imm32 r0, 0x51001001; -imm32 r1, 0x51001001; -imm32 r2, 0x51001002; -imm32 r3, 0x51001003; -imm32 r4, 0x51001004; -imm32 r5, 0x51001005; -imm32 r6, 0x51001006; -imm32 r7, 0x51001007; -R0.L = EXPADJ( R0.L , R5.L ); -R1.L = EXPADJ( R2.L , R5.L ); -R2.L = EXPADJ( R3.L , R5.L ); -R3.L = EXPADJ( R4.L , R5.L ); -R4.L = EXPADJ( R5.L , R5.L ); -R6.L = EXPADJ( R6.L , R5.L ); -R7.L = EXPADJ( R7.L , R5.L ); -R5.L = EXPADJ( R1.L , R5.L ); -CHECKREG r0, 0x51000002; -CHECKREG r1, 0x51000002; -CHECKREG r2, 0x51000002; -CHECKREG r3, 0x51000002; -CHECKREG r4, 0x51000002; -CHECKREG r5, 0x51001005; -CHECKREG r6, 0x51000002; -CHECKREG r7, 0x51000002; - -imm32 r0, 0x6000c001; -imm32 r1, 0x6000d001; -imm32 r2, 0x6000000f; -imm32 r3, 0x6000e003; -imm32 r4, 0x6000f004; -imm32 r5, 0x6000f005; -imm32 r6, 0x6000f006; -imm32 r7, 0x6000f007; -R0.L = EXPADJ( R0.L , R6.L ); -R1.L = EXPADJ( R1.L , R6.L ); -R2.L = EXPADJ( R3.L , R6.L ); -R3.L = EXPADJ( R4.L , R6.L ); -R4.L = EXPADJ( R5.L , R6.L ); -R5.L = EXPADJ( R6.L , R6.L ); -R7.L = EXPADJ( R7.L , R6.L ); -R6.L = EXPADJ( R2.L , R6.L ); -CHECKREG r0, 0x60000001; -CHECKREG r1, 0x60000001; -CHECKREG r2, 0x60000002; -CHECKREG r3, 0x60000003; -CHECKREG r4, 0x60000003; -CHECKREG r5, 0x60000003; -CHECKREG r6, 0x6000F006; -CHECKREG r7, 0x60000003; - -imm32 r0, 0x70009001; -imm32 r1, 0x7000a001; -imm32 r2, 0x7000b002; -imm32 r3, 0x70000010; -imm32 r4, 0x7000c004; -imm32 r5, 0x7000d005; -imm32 r6, 0x7000e006; -imm32 r7, 0x7000f007; -R0.L = EXPADJ( R0.L , R7.L ); -R1.L = EXPADJ( R1.L , R7.L ); -R2.L = EXPADJ( R2.L , R7.L ); -R3.L = EXPADJ( R4.L , R7.L ); -R4.L = EXPADJ( R5.L , R7.L ); -R5.L = EXPADJ( R6.L , R7.L ); -R6.L = EXPADJ( R7.L , R7.L ); -R7.L = EXPADJ( R3.L , R7.L ); -CHECKREG r0, 0x70000000; -CHECKREG r1, 0x70000000; -CHECKREG r2, 0x70000000; -CHECKREG r3, 0x70000001; -CHECKREG r4, 0x70000001; -CHECKREG r5, 0x70000002; -CHECKREG r6, 0x70000003; -CHECKREG r7, 0x7000F007; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_expadj_r.s b/sim/testsuite/sim/bfin/c_dsp32shift_expadj_r.s deleted file mode 100644 index c557cbf..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_expadj_r.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_expadj_r/c_dsp32shift_expadj_r.dsp -// Spec Reference: dsp32shift expadj r -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x08000800; -imm32 r1, 0x08000801; -imm32 r2, 0x08000802; -imm32 r3, 0x08000803; -imm32 r4, 0x08000804; -imm32 r5, 0x08000805; -imm32 r6, 0x08000806; -imm32 r7, 0x08000807; -//rl0 = expadj r0 by rl0; -R1.L = EXPADJ( R1 , R0.L ); -R2.L = EXPADJ( R2 , R0.L ); -R3.L = EXPADJ( R3 , R0.L ); -R4.L = EXPADJ( R4 , R0.L ); -R5.L = EXPADJ( R5 , R0.L ); -R6.L = EXPADJ( R6 , R0.L ); -R7.L = EXPADJ( R7 , R0.L ); -CHECKREG r0, 0x08000800; -CHECKREG r1, 0x08000800; -CHECKREG r2, 0x08000800; -CHECKREG r3, 0x08000800; -CHECKREG r4, 0x08000800; -CHECKREG r5, 0x08000800; -CHECKREG r6, 0x08000800; -CHECKREG r7, 0x08000800; - -imm32 r0, 0x0900d001; -imm32 r1, 0x09000001; -imm32 r2, 0x0900d002; -imm32 r3, 0x0900d003; -imm32 r4, 0x0900d004; -imm32 r5, 0x0900d005; -imm32 r6, 0x0900d006; -imm32 r7, 0x0900d007; -R0.L = EXPADJ( R0 , R1.L ); -R1.L = EXPADJ( R1 , R1.L ); -R2.L = EXPADJ( R2 , R1.L ); -R3.L = EXPADJ( R3 , R1.L ); -R4.L = EXPADJ( R4 , R1.L ); -R5.L = EXPADJ( R5 , R1.L ); -R6.L = EXPADJ( R6 , R1.L ); -R7.L = EXPADJ( R7 , R1.L ); -CHECKREG r0, 0x09000001; -CHECKREG r1, 0x09000001; -CHECKREG r2, 0x09000001; -CHECKREG r3, 0x09000001; -CHECKREG r4, 0x09000001; -CHECKREG r5, 0x09000001; -CHECKREG r6, 0x09000001; -CHECKREG r7, 0x09000001; - - -imm32 r0, 0x0a00e001; -imm32 r1, 0x0a00e001; -imm32 r2, 0x0a00000f; -imm32 r3, 0x0a00e003; -imm32 r4, 0x0a00e004; -imm32 r5, 0x0a00e005; -imm32 r6, 0x0a00e006; -imm32 r7, 0x0a00e007; -R0.L = EXPADJ( R0 , R2.L ); -R1.L = EXPADJ( R1 , R2.L ); -//rl2 = expadj r2 by rl2; -R3.L = EXPADJ( R3 , R2.L ); -R4.L = EXPADJ( R4 , R2.L ); -R5.L = EXPADJ( R5 , R2.L ); -R6.L = EXPADJ( R6 , R2.L ); -R7.L = EXPADJ( R7 , R2.L ); -CHECKREG r0, 0x0A000003; -CHECKREG r1, 0x0A000003; -CHECKREG r2, 0x0A00000F; -CHECKREG r3, 0x0A000003; -CHECKREG r4, 0x0A000003; -CHECKREG r5, 0x0A000003; -CHECKREG r6, 0x0A000003; -CHECKREG r7, 0x0A000003; - -imm32 r0, 0x0b00f001; -imm32 r1, 0x0b00f001; -imm32 r2, 0x0b00f002; -imm32 r3, 0x0b000010; -imm32 r4, 0x0b00f004; -imm32 r5, 0x0b00f005; -imm32 r6, 0x0b00f006; -imm32 r7, 0x0b00f007; -R0.L = EXPADJ( R0 , R3.L ); -R1.L = EXPADJ( R1 , R3.L ); -R2.L = EXPADJ( R2 , R3.L ); -R3.L = EXPADJ( R3 , R3.L ); -R4.L = EXPADJ( R4 , R3.L ); -R5.L = EXPADJ( R5 , R3.L ); -R6.L = EXPADJ( R6 , R3.L ); -R7.L = EXPADJ( R7 , R3.L ); -CHECKREG r0, 0x0B000003; -CHECKREG r1, 0x0B000003; -CHECKREG r2, 0x0B000003; -CHECKREG r3, 0x0B000003; -CHECKREG r4, 0x0B000003; -CHECKREG r5, 0x0B000003; -CHECKREG r6, 0x0B000003; -CHECKREG r7, 0x0B000003; - -imm32 r0, 0x0c0000c0; -imm32 r1, 0x0c0100c0; -imm32 r2, 0x0c0200c0; -imm32 r3, 0x0c0300c0; -imm32 r4, 0x0c0400c0; -imm32 r5, 0x0c0500c0; -imm32 r6, 0x0c0600c0; -imm32 r7, 0x0c0700c0; -R0.L = EXPADJ( R0 , R4.L ); -R1.L = EXPADJ( R1 , R4.L ); -R2.L = EXPADJ( R2 , R4.L ); -R3.L = EXPADJ( R3 , R4.L ); -R4.L = EXPADJ( R4 , R4.L ); -R5.L = EXPADJ( R5 , R4.L ); -R6.L = EXPADJ( R6 , R4.L ); -R7.L = EXPADJ( R7 , R4.L ); -CHECKREG r0, 0x0C0000C0; -CHECKREG r1, 0x0C0100C0; -CHECKREG r2, 0x0C0200C0; -CHECKREG r3, 0x0C0300C0; -CHECKREG r4, 0x0C0400C0; -CHECKREG r5, 0x0C0500C0; -CHECKREG r6, 0x0C0600C0; -CHECKREG r7, 0x0C0700C0; - -imm32 r0, 0xa00100d0; -imm32 r1, 0x000100d1; -imm32 r2, 0xa00200d0; -imm32 r3, 0xa00300d0; -imm32 r4, 0xa00400d0; -imm32 r5, 0xa00500d0; -imm32 r6, 0xa00600d0; -imm32 r7, 0xa00700d0; -R0.L = EXPADJ( R0 , R5.L ); -R1.L = EXPADJ( R1 , R5.L ); -R2.L = EXPADJ( R2 , R5.L ); -R3.L = EXPADJ( R3 , R5.L ); -R4.L = EXPADJ( R4 , R5.L ); -R5.L = EXPADJ( R5 , R5.L ); -R6.L = EXPADJ( R6 , R5.L ); -R7.L = EXPADJ( R7 , R5.L ); -CHECKREG r0, 0xA0010000; -CHECKREG r1, 0x0001000E; -CHECKREG r2, 0xA0020000; -CHECKREG r3, 0xA0030000; -CHECKREG r4, 0xA0040000; -CHECKREG r5, 0xA0050000; -CHECKREG r6, 0xA0060000; -CHECKREG r7, 0xA0070000; - -imm32 r0, 0xb0010000; -imm32 r1, 0xb0010000; -imm32 r2, 0xb002000f; -imm32 r3, 0xb0030000; -imm32 r4, 0xb0040000; -imm32 r5, 0xb0050000; -imm32 r6, 0xb0060000; -imm32 r7, 0xb0070000; -R0.L = EXPADJ( R0 , R6.L ); -R1.L = EXPADJ( R1 , R6.L ); -R2.L = EXPADJ( R2 , R6.L ); -R3.L = EXPADJ( R3 , R6.L ); -R4.L = EXPADJ( R4 , R6.L ); -R5.L = EXPADJ( R5 , R6.L ); -R6.L = EXPADJ( R6 , R6.L ); -R7.L = EXPADJ( R7 , R6.L ); -CHECKREG r0, 0xB0010000; -CHECKREG r1, 0xB0010000; -CHECKREG r2, 0xB0020000; -CHECKREG r3, 0xB0030000; -CHECKREG r4, 0xB0040000; -CHECKREG r5, 0xB0050000; -CHECKREG r6, 0xB0060000; -CHECKREG r7, 0xB0070000; - -imm32 r0, 0xd00100e0; -imm32 r1, 0xd00100e0; -imm32 r2, 0xd00200e0; -imm32 r3, 0xd00300e0; -imm32 r4, 0xd00400e0; -imm32 r5, 0xd00500e0; -imm32 r6, 0xd00600e0; -imm32 r7, 0xd00700e0; -R0.L = EXPADJ( R0 , R7.L ); -R1.L = EXPADJ( R1 , R7.L ); -R2.L = EXPADJ( R2 , R7.L ); -R3.L = EXPADJ( R3 , R7.L ); -R4.L = EXPADJ( R4 , R7.L ); -R5.L = EXPADJ( R5 , R7.L ); -R6.L = EXPADJ( R6 , R7.L ); -R7.L = EXPADJ( R7 , R7.L ); -CHECKREG r0, 0xD00100E0; -CHECKREG r1, 0xD00100E0; -CHECKREG r2, 0xD00200E0; -CHECKREG r3, 0xD00300E0; -CHECKREG r4, 0xD00400E0; -CHECKREG r5, 0xD00500E0; -CHECKREG r6, 0xD00600E0; -CHECKREG r7, 0xD00700E0; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_expexp_r.s b/sim/testsuite/sim/bfin/c_dsp32shift_expexp_r.s deleted file mode 100644 index 4e9186b..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_expexp_r.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_expexp_r/c_dsp32shift_expexp_r.dsp -// Spec Reference: dsp32shift expadj / expadj r -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x0800d001; -imm32 r1, 0x08000001; -imm32 r2, 0x0800d002; -imm32 r3, 0x0800d003; -imm32 r4, 0x0800d004; -imm32 r5, 0x0800d005; -imm32 r6, 0x0800d006; -imm32 r7, 0x0800d007; -R1.L = EXPADJ( R1 , R0.L ) (V); -R2.L = EXPADJ( R2 , R0.L ) (V); -R3.L = EXPADJ( R3 , R0.L ) (V); -R4.L = EXPADJ( R4 , R0.L ) (V); -R5.L = EXPADJ( R5 , R0.L ) (V); -R6.L = EXPADJ( R6 , R0.L ) (V); -R7.L = EXPADJ( R7 , R0.L ) (V); -R0.L = EXPADJ( R0 , R0.L ) (V); -CHECKREG r0, 0x0800D001; -CHECKREG r1, 0x0800D001; -CHECKREG r2, 0x0800D001; -CHECKREG r3, 0x0800D001; -CHECKREG r4, 0x0800D001; -CHECKREG r5, 0x0800D001; -CHECKREG r6, 0x0800D001; -CHECKREG r7, 0x0800D001; - -imm32 r0, 0x0900d001; -imm32 r1, 0x09000001; -imm32 r2, 0x0900d002; -imm32 r3, 0x0900d003; -imm32 r4, 0x0900d004; -imm32 r5, 0x0900d005; -imm32 r6, 0x0900d006; -imm32 r7, 0x0900d007; -R0.L = EXPADJ( R0 , R1.L ) (V); -R1.L = EXPADJ( R1 , R1.L ) (V); -R2.L = EXPADJ( R2 , R1.L ) (V); -R3.L = EXPADJ( R3 , R1.L ) (V); -R4.L = EXPADJ( R4 , R1.L ) (V); -R5.L = EXPADJ( R5 , R1.L ) (V); -R6.L = EXPADJ( R6 , R1.L ) (V); -R7.L = EXPADJ( R7 , R1.L ) (V); -CHECKREG r0, 0x09000001; -CHECKREG r1, 0x09000001; -CHECKREG r2, 0x09000001; -CHECKREG r3, 0x09000001; -CHECKREG r4, 0x09000001; -CHECKREG r5, 0x09000001; -CHECKREG r6, 0x09000001; -CHECKREG r7, 0x09000001; - - -imm32 r0, 0x0a00e001; -imm32 r1, 0x0a00e001; -imm32 r2, 0x0a00000f; -imm32 r3, 0x0a00e003; -imm32 r4, 0x0a00e004; -imm32 r5, 0x0a00e005; -imm32 r6, 0x0a00e006; -imm32 r7, 0x0a00e007; -R0.L = EXPADJ( R0 , R2.L ) (V); -R1.L = EXPADJ( R1 , R2.L ) (V); -R3.L = EXPADJ( R3 , R2.L ) (V); -R4.L = EXPADJ( R4 , R2.L ) (V); -R5.L = EXPADJ( R5 , R2.L ) (V); -R6.L = EXPADJ( R6 , R2.L ) (V); -R7.L = EXPADJ( R7 , R2.L ) (V); -R2.L = EXPADJ( R2 , R2.L ) (V); -CHECKREG r0, 0x0A000002; -CHECKREG r1, 0x0A000002; -CHECKREG r2, 0x0A000003; -CHECKREG r3, 0x0A000002; -CHECKREG r4, 0x0A000002; -CHECKREG r5, 0x0A000002; -CHECKREG r6, 0x0A000002; -CHECKREG r7, 0x0A000002; - -imm32 r0, 0x0b00f001; -imm32 r1, 0x0b00f001; -imm32 r2, 0x0b00f002; -imm32 r3, 0x0b000010; -imm32 r4, 0x0b00f004; -imm32 r5, 0x0b00f005; -imm32 r6, 0x0b00f006; -imm32 r7, 0x0b00f007; -R0.L = EXPADJ( R0 , R3.L ) (V); -R1.L = EXPADJ( R1 , R3.L ) (V); -R2.L = EXPADJ( R2 , R3.L ) (V); -R3.L = EXPADJ( R3 , R3.L ) (V); -R4.L = EXPADJ( R4 , R3.L ) (V); -R5.L = EXPADJ( R5 , R3.L ) (V); -R6.L = EXPADJ( R6 , R3.L ) (V); -R7.L = EXPADJ( R7 , R3.L ) (V); -CHECKREG r0, 0x0B000010; -CHECKREG r1, 0x0B000010; -CHECKREG r2, 0x0B000010; -CHECKREG r3, 0x0B000010; -CHECKREG r4, 0x0B000010; -CHECKREG r5, 0x0B000010; -CHECKREG r6, 0x0B000010; -CHECKREG r7, 0x0B000010; - -imm32 r0, 0x0c0000c0; -imm32 r1, 0x0c0100c0; -imm32 r2, 0x0c0200c0; -imm32 r3, 0x0c0300c0; -imm32 r4, 0x0c0400c0; -imm32 r5, 0x0c0500c0; -imm32 r6, 0x0c0600c0; -imm32 r7, 0x0c0700c0; -R0.L = EXPADJ( R0 , R4.L ) (V); -R1.L = EXPADJ( R1 , R4.L ) (V); -R2.L = EXPADJ( R2 , R4.L ) (V); -R3.L = EXPADJ( R3 , R4.L ) (V); -R4.L = EXPADJ( R4 , R4.L ) (V); -R5.L = EXPADJ( R5 , R4.L ) (V); -R6.L = EXPADJ( R6 , R4.L ) (V); -R7.L = EXPADJ( R7 , R4.L ) (V); -CHECKREG r0, 0x0C0000C0; -CHECKREG r1, 0x0C0100C0; -CHECKREG r2, 0x0C0200C0; -CHECKREG r3, 0x0C0300C0; -CHECKREG r4, 0x0C0400C0; -CHECKREG r5, 0x0C0500C0; -CHECKREG r6, 0x0C0600C0; -CHECKREG r7, 0x0C0700C0; - -imm32 r0, 0xa00100d0; -imm32 r1, 0x000100d1; -imm32 r2, 0xa00200d0; -imm32 r3, 0xa00300d0; -imm32 r4, 0xa00400d0; -imm32 r5, 0xa00500d0; -imm32 r6, 0xa00600d0; -imm32 r7, 0xa00700d0; -R0.L = EXPADJ( R0 , R5.L ) (V); -R1.L = EXPADJ( R1 , R5.L ) (V); -R2.L = EXPADJ( R2 , R5.L ) (V); -R3.L = EXPADJ( R3 , R5.L ) (V); -R4.L = EXPADJ( R4 , R5.L ) (V); -R5.L = EXPADJ( R5 , R5.L ) (V); -R6.L = EXPADJ( R6 , R5.L ) (V); -R7.L = EXPADJ( R7 , R5.L ) (V); -CHECKREG r0, 0xA00100D0; -CHECKREG r1, 0x000100D0; -CHECKREG r2, 0xA00200D0; -CHECKREG r3, 0xA00300D0; -CHECKREG r4, 0xA00400D0; -CHECKREG r5, 0xA00500D0; -CHECKREG r6, 0xA00600D0; -CHECKREG r7, 0xA00700D0; - -imm32 r0, 0xb0010000; -imm32 r1, 0xb0010000; -imm32 r2, 0xb002000f; -imm32 r3, 0xb0030000; -imm32 r4, 0xb0040000; -imm32 r5, 0xb0050000; -imm32 r6, 0xb0060000; -imm32 r7, 0xb0070000; -R0.L = EXPADJ( R0 , R6.L ) (V); -R1.L = EXPADJ( R1 , R6.L ) (V); -R2.L = EXPADJ( R2 , R6.L ) (V); -R3.L = EXPADJ( R3 , R6.L ) (V); -R4.L = EXPADJ( R4 , R6.L ) (V); -R5.L = EXPADJ( R5 , R6.L ) (V); -R6.L = EXPADJ( R6 , R6.L ) (V); -R7.L = EXPADJ( R7 , R6.L ) (V); -CHECKREG r0, 0xB0010000; -CHECKREG r1, 0xB0010000; -CHECKREG r2, 0xB0020000; -CHECKREG r3, 0xB0030000; -CHECKREG r4, 0xB0040000; -CHECKREG r5, 0xB0050000; -CHECKREG r6, 0xB0060000; -CHECKREG r7, 0xB0070000; - -imm32 r0, 0xd00102e7; -imm32 r1, 0xd00104e7; -imm32 r2, 0xd00206e7; -imm32 r3, 0xd00308e7; -imm32 r4, 0xd0040ae7; -imm32 r5, 0xd0050ce7; -imm32 r6, 0xd0060ee7; -imm32 r7, 0xd00707e7; -R0.L = EXPADJ( R0 , R7.L ) (V); -R1.L = EXPADJ( R1 , R7.L ) (V); -R2.L = EXPADJ( R2 , R7.L ) (V); -R3.L = EXPADJ( R3 , R7.L ) (V); -R4.L = EXPADJ( R4 , R7.L ) (V); -R5.L = EXPADJ( R5 , R7.L ) (V); -R6.L = EXPADJ( R6 , R7.L ) (V); -R7.L = EXPADJ( R7 , R7.L ) (V); -CHECKREG r0, 0xD0010001; -CHECKREG r1, 0xD0010001; -CHECKREG r2, 0xD0020001; -CHECKREG r3, 0xD0030001; -CHECKREG r4, 0xD0040001; -CHECKREG r5, 0xD0050001; -CHECKREG r6, 0xD0060001; -CHECKREG r7, 0xD0070001; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_fdepx.s b/sim/testsuite/sim/bfin/c_dsp32shift_fdepx.s deleted file mode 100644 index 5e843fe..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_fdepx.s +++ /dev/null @@ -1,210 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_fdepx/c_dsp32shift_fdepx.dsp -// Spec Reference: dsp32shift fdep x -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x00000001; -imm32 r1, 0x01000801; -imm32 r2, 0x08200802; -imm32 r3, 0x08030803; -imm32 r4, 0x08004804; -imm32 r5, 0x08000505; -imm32 r6, 0x08000866; -imm32 r7, 0x08000807; -R1 = DEPOSIT( R1, R0 ); -R2 = DEPOSIT( R2, R0 ); -R3 = DEPOSIT( R3, R0 ); -R4 = DEPOSIT( R4, R0 ) (X); -R5 = DEPOSIT( R5, R0 ); -R6 = DEPOSIT( R6, R0 ); -R7 = DEPOSIT( R7, R0 ) (X); -R0 = DEPOSIT( R0, R0 ); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x01000800; -CHECKREG r2, 0x08200802; -CHECKREG r3, 0x08030802; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x08000504; -CHECKREG r6, 0x08000866; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x0900d001; -imm32 r1, 0x09000002; -imm32 r2, 0x09000002; -imm32 r3, 0x09100003; -imm32 r4, 0x09020004; -imm32 r5, 0x09003005; -imm32 r6, 0x09000406; -imm32 r7, 0x09000057; -R0 = DEPOSIT( R0, R1 ); -R2 = DEPOSIT( R2, R1 ); -R3 = DEPOSIT( R3, R1 ); -R4 = DEPOSIT( R4, R1 ); -R5 = DEPOSIT( R5, R1 ) (X); -R6 = DEPOSIT( R6, R1 ); -R7 = DEPOSIT( R7, R1 ) (X); -R1 = DEPOSIT( R1, R1 ); -CHECKREG r0, 0x0900D000; -CHECKREG r1, 0x09000000; -CHECKREG r2, 0x09000000; -CHECKREG r3, 0x09100000; -CHECKREG r4, 0x09020004; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x09000404; -CHECKREG r7, 0x00000000; - - -imm32 r0, 0x0a00e001; -imm32 r1, 0x0a00e001; -imm32 r2, 0x0a00000f; -imm32 r3, 0x0a000010; -imm32 r4, 0x0a00e004; -imm32 r5, 0x0a00e005; -imm32 r6, 0x0a00e006; -imm32 r7, 0x0a00e007; -R0 = DEPOSIT( R0, R2 ); -R1 = DEPOSIT( R1, R2 ); -R3 = DEPOSIT( R3, R2 ); -R4 = DEPOSIT( R4, R2 ); -R5 = DEPOSIT( R5, R2 ); -R6 = DEPOSIT( R6, R2 ); -R7 = DEPOSIT( R7, R2 ); -R2 = DEPOSIT( R2, R2 ); -CHECKREG r0, 0x0A008A00; -CHECKREG r1, 0x0A008A00; -CHECKREG r2, 0x0A000A00; -CHECKREG r3, 0x0A000A00; -CHECKREG r4, 0x0A008A00; -CHECKREG r5, 0x0A008A00; -CHECKREG r6, 0x0A008A00; -CHECKREG r7, 0x0A008A00; - -imm32 r0, 0x4b00f001; -imm32 r1, 0x5b00f001; -imm32 r2, 0x6b00f002; -imm32 r3, 0x9f000010; -imm32 r4, 0x8b00f004; -imm32 r5, 0x0900f005; -imm32 r6, 0x0b00f006; -imm32 r7, 0x0b0af007; -R0 = DEPOSIT( R0, R3 ); -R1 = DEPOSIT( R1, R3 ); -R2 = DEPOSIT( R2, R3 ) (X); -R4 = DEPOSIT( R4, R3 ); -R5 = DEPOSIT( R5, R3 ); -R6 = DEPOSIT( R6, R3 ) (X); -R7 = DEPOSIT( R7, R3 ); -R3 = DEPOSIT( R3, R3 ); -CHECKREG r0, 0x4B009F00; -CHECKREG r1, 0x5B009F00; -CHECKREG r2, 0xFFFF9F00; -CHECKREG r3, 0x9F009F00; -CHECKREG r4, 0x8B009F00; -CHECKREG r5, 0x09009F00; -CHECKREG r6, 0xFFFF9F00; -CHECKREG r7, 0x0B0A9F00; - -imm32 r0, 0x0c0000c0; -imm32 r1, 0x0c0100c0; -imm32 r2, 0x0c0200c0; -imm32 r3, 0x0c0300c0; -imm32 r4, 0x0c04000c; -imm32 r5, 0x0c0500c0; -imm32 r6, 0x0c0600c0; -imm32 r7, 0x0c0700c0; -R0 = DEPOSIT( R0, R4 ); -R1 = DEPOSIT( R1, R4 ); -R2 = DEPOSIT( R2, R4 ); -R3 = DEPOSIT( R3, R4 ); -R5 = DEPOSIT( R5, R4 ) (X); -R6 = DEPOSIT( R6, R4 ); -R7 = DEPOSIT( R7, R4 ); -R4 = DEPOSIT( R4, R4 ); -CHECKREG r0, 0x0C000C04; -CHECKREG r1, 0x0C010C04; -CHECKREG r2, 0x0C020C04; -CHECKREG r3, 0x0C030C04; -CHECKREG r4, 0x0C040C04; -CHECKREG r5, 0xFFFFFC04; -CHECKREG r6, 0x0C060C04; -CHECKREG r7, 0x0C070C04; - -imm32 r0, 0xa00100d0; -imm32 r1, 0xa00100d1; -imm32 r2, 0xa00200d0; -imm32 r3, 0xa00300d0; -imm32 r4, 0xa00400d0; -imm32 r5, 0xa0050007; -imm32 r6, 0xa00600d0; -imm32 r7, 0xa00700d0; -R5 = DEPOSIT( R0, R5 ); -R6 = DEPOSIT( R1, R5 ) (X); -R7 = DEPOSIT( R2, R5 ); -R0 = DEPOSIT( R3, R5 ); -R1 = DEPOSIT( R4, R5 ) (X); -R2 = DEPOSIT( R6, R5 ); -R3 = DEPOSIT( R7, R5 ); -R4 = DEPOSIT( R5, R5 ); -CHECKREG r0, 0xA00300C1; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0xA00200C1; -CHECKREG r4, 0xA0010081; -CHECKREG r5, 0xA0010085; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0xA00200C1; - -imm32 r0, 0xb0010000; -imm32 r1, 0xb0010000; -imm32 r2, 0xb002000f; -imm32 r3, 0xb0030000; -imm32 r4, 0xb0040000; -imm32 r5, 0xb0050000; -imm32 r6, 0x00237809; -imm32 r7, 0xb0070000; -R0 = DEPOSIT( R0, R6 ); -R1 = DEPOSIT( R1, R6 ); -R2 = DEPOSIT( R2, R6 ); -R3 = DEPOSIT( R3, R6 ) (X); -R4 = DEPOSIT( R4, R6 ); -R5 = DEPOSIT( R5, R6 ); -R6 = DEPOSIT( R6, R6 ); -R7 = DEPOSIT( R7, R6 ); -CHECKREG r0, 0x23010000; -CHECKREG r1, 0x23010000; -CHECKREG r2, 0x2302000F; -CHECKREG r3, 0x23030000; -CHECKREG r4, 0x23040000; -CHECKREG r5, 0x23050000; -CHECKREG r6, 0x23237809; -CHECKREG r7, 0x23070000; - -imm32 r0, 0xd00100e0; -imm32 r1, 0xd00100e0; -imm32 r2, 0xd00200e0; -imm32 r3, 0xd00300e0; -imm32 r4, 0xd00400e0; -imm32 r5, 0xd00500e0; -imm32 r6, 0xd00600e0; -imm32 r7, 0x00012345; -R1 = DEPOSIT( R0, R7 ); -R2 = DEPOSIT( R1, R7 ); -R3 = DEPOSIT( R2, R7 ); -R4 = DEPOSIT( R3, R7 ); -R5 = DEPOSIT( R4, R7 ) (X); -R6 = DEPOSIT( R5, R7 ); -R7 = DEPOSIT( R6, R7 ) (X); -R0 = DEPOSIT( R7, R7 ); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0xD0010008; -CHECKREG r2, 0xD0010008; -CHECKREG r3, 0xD0010008; -CHECKREG r4, 0xD0010008; -CHECKREG r5, 0x00000008; -CHECKREG r6, 0x00000008; -CHECKREG r7, 0x00000008; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_fextx.s b/sim/testsuite/sim/bfin/c_dsp32shift_fextx.s deleted file mode 100644 index 13ba90c..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_fextx.s +++ /dev/null @@ -1,210 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_fextx/c_dsp32shift_fextx.dsp -// Spec Reference: dsp32shift fext x -# mach: bfin - -.include "testutils.inc" - start - -imm32 r0, 0x00000001; -imm32 r1, 0x01000801; -imm32 r2, 0x08200802; -imm32 r3, 0x08030803; -imm32 r4, 0x08004804; -imm32 r5, 0x08000505; -imm32 r6, 0x08000866; -imm32 r7, 0x08000807; -R1 = EXTRACT( R1, R0.L ) (Z); -R2 = EXTRACT( R2, R0.L ) (Z); -R3 = EXTRACT( R3, R0.L ) (Z); -R4 = EXTRACT( R4, R0.L ) (X); -R5 = EXTRACT( R5, R0.L ) (Z); -R6 = EXTRACT( R6, R0.L ) (Z); -R7 = EXTRACT( R7, R0.L ) (X); -R0 = EXTRACT( R0, R0.L ) (Z); -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0xFFFFFFFF; - -imm32 r0, 0x0900d001; -imm32 r1, 0x09000002; -imm32 r2, 0x09000002; -imm32 r3, 0x09100003; -imm32 r4, 0x09020004; -imm32 r5, 0x09003005; -imm32 r6, 0x09000406; -imm32 r7, 0x09000057; -R0 = EXTRACT( R0, R1.L ) (Z); -R2 = EXTRACT( R2, R1.L ) (Z); -R3 = EXTRACT( R3, R1.L ) (Z); -R4 = EXTRACT( R4, R1.L ) (Z); -R5 = EXTRACT( R5, R1.L ) (X); -R6 = EXTRACT( R6, R1.L ) (Z); -R7 = EXTRACT( R7, R1.L ) (X); -R1 = EXTRACT( R1, R1.L ) (Z); -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000002; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00000003; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000002; -CHECKREG r7, 0xFFFFFFFF; - - -imm32 r0, 0x0a00e001; -imm32 r1, 0x0a00e001; -imm32 r2, 0x0a00000f; -imm32 r3, 0x0a000010; -imm32 r4, 0x0a00e004; -imm32 r5, 0x0a00e005; -imm32 r6, 0x0a00e006; -imm32 r7, 0x0a00e007; -R0 = EXTRACT( R0, R2.L ) (Z); -R1 = EXTRACT( R1, R2.L ) (Z); -R3 = EXTRACT( R3, R2.L ) (Z); -R4 = EXTRACT( R4, R2.L ) (Z); -R5 = EXTRACT( R5, R2.L ) (Z); -R6 = EXTRACT( R6, R2.L ) (Z); -R7 = EXTRACT( R7, R2.L ) (Z); -R2 = EXTRACT( R2, R2.L ) (Z); -CHECKREG r0, 0x00006001; -CHECKREG r1, 0x00006001; -CHECKREG r2, 0x0000000F; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00006004; -CHECKREG r5, 0x00006005; -CHECKREG r6, 0x00006006; -CHECKREG r7, 0x00006007; - -imm32 r0, 0x0b00f001; -imm32 r1, 0x0b00f001; -imm32 r2, 0x0b00f002; -imm32 r3, 0x0b000010; -imm32 r4, 0x0b00f004; -imm32 r5, 0x0b00f005; -imm32 r6, 0x0b00f006; -imm32 r7, 0x0b00f007; -R0 = EXTRACT( R0, R3.L ) (Z); -R1 = EXTRACT( R1, R3.L ) (Z); -R2 = EXTRACT( R2, R3.L ) (X); -R4 = EXTRACT( R4, R3.L ) (Z); -R5 = EXTRACT( R5, R3.L ) (Z); -R6 = EXTRACT( R6, R3.L ) (X); -R7 = EXTRACT( R7, R3.L ) (Z); -R3 = EXTRACT( R3, R3.L ) (Z); -CHECKREG r0, 0x0000F001; -CHECKREG r1, 0x0000F001; -CHECKREG r2, 0xFFFFF002; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x0000F004; -CHECKREG r5, 0x0000F005; -CHECKREG r6, 0xFFFFF006; -CHECKREG r7, 0x0000F007; - -imm32 r0, 0x0c0000c0; -imm32 r1, 0x0c0100c0; -imm32 r2, 0x0c0200c0; -imm32 r3, 0x0c0300c0; -imm32 r4, 0x0c04000c; -imm32 r5, 0x0c0500c0; -imm32 r6, 0x0c0600c0; -imm32 r7, 0x0c0700c0; -R0 = EXTRACT( R0, R4.L ) (Z); -R1 = EXTRACT( R1, R4.L ) (Z); -R2 = EXTRACT( R2, R4.L ) (Z); -R3 = EXTRACT( R3, R4.L ) (Z); -R5 = EXTRACT( R5, R4.L ) (X); -R6 = EXTRACT( R6, R4.L ) (Z); -R7 = EXTRACT( R7, R4.L ) (Z); -R4 = EXTRACT( R4, R4.L ) (Z); -CHECKREG r0, 0x000000C0; -CHECKREG r1, 0x000000C0; -CHECKREG r2, 0x000000C0; -CHECKREG r3, 0x000000C0; -CHECKREG r4, 0x0000000C; -CHECKREG r5, 0x000000C0; -CHECKREG r6, 0x000000C0; -CHECKREG r7, 0x000000C0; - -imm32 r0, 0xa00100d0; -imm32 r1, 0xa00100d1; -imm32 r2, 0xa00200d0; -imm32 r3, 0xa00300d0; -imm32 r4, 0xa00400d0; -imm32 r5, 0xa0050007; -imm32 r6, 0xa00600d0; -imm32 r7, 0xa00700d0; -R0 = EXTRACT( R0, R5.L ) (Z); -R1 = EXTRACT( R1, R5.L ) (X); -R2 = EXTRACT( R2, R5.L ) (Z); -R3 = EXTRACT( R3, R5.L ) (Z); -R4 = EXTRACT( R4, R5.L ) (X); -R6 = EXTRACT( R6, R5.L ) (Z); -R7 = EXTRACT( R7, R5.L ) (Z); -R5 = EXTRACT( R5, R5.L ) (Z); -CHECKREG r0, 0x00000050; -CHECKREG r1, 0xFFFFFFD1; -CHECKREG r2, 0x00000050; -CHECKREG r3, 0x00000050; -CHECKREG r4, 0xFFFFFFD0; -CHECKREG r5, 0x00000007; -CHECKREG r6, 0x00000050; -CHECKREG r7, 0x00000050; - -imm32 r0, 0xb0010000; -imm32 r1, 0xb0010000; -imm32 r2, 0xb002000f; -imm32 r3, 0xb0030000; -imm32 r4, 0xb0040000; -imm32 r5, 0xb0050000; -imm32 r6, 0xb0060009; -imm32 r7, 0xb0070000; -R0 = EXTRACT( R0, R6.L ) (Z); -R1 = EXTRACT( R1, R6.L ) (Z); -R2 = EXTRACT( R2, R6.L ) (Z); -R3 = EXTRACT( R3, R6.L ) (X); -R4 = EXTRACT( R4, R6.L ) (Z); -R5 = EXTRACT( R5, R6.L ) (Z); -R6 = EXTRACT( R6, R6.L ) (Z); -R7 = EXTRACT( R7, R6.L ) (Z); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x0000000F; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000009; -CHECKREG r7, 0x00000000; - -imm32 r0, 0xd00100e0; -imm32 r1, 0xd00100e0; -imm32 r2, 0xd00200e0; -imm32 r3, 0xd00300e0; -imm32 r4, 0xd00400e0; -imm32 r5, 0xd00500e0; -imm32 r6, 0xd00600e0; -imm32 r7, 0xd0070023; -R1 = EXTRACT( R0, R7.L ) (Z); -R2 = EXTRACT( R1, R7.L ) (Z); -R3 = EXTRACT( R2, R7.L ) (Z); -R4 = EXTRACT( R3, R7.L ) (Z); -R5 = EXTRACT( R4, R7.L ) (X); -R6 = EXTRACT( R5, R7.L ) (Z); -R7 = EXTRACT( R6, R7.L ) (X); -R0 = EXTRACT( R7, R7.L ) (Z); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lf.s b/sim/testsuite/sim/bfin/c_dsp32shift_lf.s deleted file mode 100644 index 88ee774..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_lf.s +++ /dev/null @@ -1,422 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_lf/c_dsp32shift_lf.dsp -// Spec Reference: dsp32shift lshift -# mach: bfin - -.include "testutils.inc" - start - - - -// lshift : mix data, count (+)= (half reg) -// d_reg = lshift (d BY d_lo) -// Rx by RLx -imm32 r0, 0x01210001; -imm32 r1, 0x12315678; -imm32 r2, 0x23416789; -imm32 r3, 0x3451789a; -imm32 r4, 0x856189ab; -imm32 r5, 0x96719abc; -imm32 r6, 0xa781abcd; -imm32 r7, 0xb891bcde; -R7 = LSHIFT R0 BY R0.L; -R6 = LSHIFT R1 BY R0.L; -R0 = LSHIFT R2 BY R0.L; -R1 = LSHIFT R3 BY R0.L; -R2 = LSHIFT R4 BY R0.L; -R3 = LSHIFT R5 BY R0.L; -R4 = LSHIFT R6 BY R0.L; -R5 = LSHIFT R7 BY R0.L; -CHECKREG r0, 0x4682CF12; -CHECKREG r1, 0xE2680000; -CHECKREG r2, 0x26AC0000; -CHECKREG r3, 0x6AF00000; -CHECKREG r4, 0xB3C00000; -CHECKREG r5, 0x00080000; -CHECKREG r6, 0x2462ACF0; -CHECKREG r7, 0x02420002; - -imm32 r0, 0x01220002; -imm32 r1, 0x12325678; -imm32 r2, 0x23426789; -imm32 r3, 0x3452789a; -imm32 r4, 0x956289ab; -imm32 r5, 0xa6729abc; -imm32 r6, 0xb782abcd; -imm32 r7, 0xc892bcde; -R1.L = 2; -R3 = LSHIFT R0 BY R1.L; -R4 = LSHIFT R1 BY R1.L; -R5 = LSHIFT R2 BY R1.L; -R6 = LSHIFT R3 BY R1.L; -R7 = LSHIFT R4 BY R1.L; -R0 = LSHIFT R5 BY R1.L; -R1 = LSHIFT R6 BY R1.L; -R2 = LSHIFT R7 BY R1.L; -CHECKREG r0, 0x34267890; -CHECKREG r1, 0x48800080; -CHECKREG r2, 0x23200020; -CHECKREG r3, 0x04880008; -CHECKREG r4, 0x48C80008; -CHECKREG r5, 0x8D099E24; -CHECKREG r6, 0x12200020; -CHECKREG r7, 0x23200020; - -imm32 r0, 0x01230002; -imm32 r1, 0x12335678; -imm32 r2, 0x23436789; -imm32 r3, 0x3453789a; -imm32 r4, 0x456389ab; -imm32 r5, 0x56739abc; -imm32 r6, 0x6783abcd; -imm32 r7, 0x789abcde; -R2 = 14; -R0 = LSHIFT R4 BY R2.L; -R1 = LSHIFT R5 BY R2.L; -R2 = LSHIFT R6 BY R2.L; -R3 = LSHIFT R7 BY R2.L; -CHECKREG r0, 0xE26AC000; -CHECKREG r1, 0xE6AF0000; -CHECKREG r2, 0xEAF34000; -CHECKREG r3, 0x789ABCDE; - -imm32 r0, 0x01240002; -imm32 r1, 0x12345678; -imm32 r2, 0x23446789; -imm32 r3, 0x3454789a; -imm32 r4, 0xa56489ab; -imm32 r5, 0xb6749abc; -imm32 r6, 0xc784abcd; -imm32 r7, 0xd894bcde; -R3.L = 15; -R4 = LSHIFT R0 BY R3.L; -R5 = LSHIFT R1 BY R3.L; -R6 = LSHIFT R2 BY R3.L; -R7 = LSHIFT R3 BY R3.L; -R0 = LSHIFT R4 BY R3.L; -R1 = LSHIFT R5 BY R3.L; -R2 = LSHIFT R6 BY R3.L; -R3 = LSHIFT R7 BY R3.L; -CHECKREG r0, 0x80000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x40000000; -CHECKREG r3, 0xC0000000; -CHECKREG r4, 0x00010000; -CHECKREG r5, 0x2B3C0000; -CHECKREG r6, 0x33C48000; -CHECKREG r7, 0x00078000; - -imm32 r0, 0x01250002; -imm32 r1, 0x12355678; -imm32 r2, 0x23456789; -imm32 r3, 0x3455789a; -imm32 r4, 0x456589ab; -imm32 r5, 0x56759abc; -imm32 r6, 0x6785abcd; -imm32 r7, 0x7895bcde; -R4.L = -1; -R7 = LSHIFT R0 BY R4.L; -R6 = LSHIFT R1 BY R4.L; -R5 = LSHIFT R2 BY R4.L; -R3 = LSHIFT R4 BY R4.L; -R2 = LSHIFT R5 BY R4.L; -R1 = LSHIFT R6 BY R4.L; -R0 = LSHIFT R7 BY R4.L; -R4 = LSHIFT R3 BY R4.L; -CHECKREG r0, 0x00494000; -CHECKREG r1, 0x048D559E; -CHECKREG r2, 0x08D159E2; -CHECKREG r3, 0x22B2FFFF; -CHECKREG r4, 0x11597FFF; -CHECKREG r5, 0x11A2B3C4; -CHECKREG r6, 0x091AAB3C; -CHECKREG r7, 0x00928001; - -imm32 r0, 0x01260002; -imm32 r1, 0x82365678; -imm32 r2, 0x93466789; -imm32 r3, 0xa456789a; -imm32 r4, 0xb56689ab; -imm32 r5, 0xc6769abc; -imm32 r6, 0xd786abcd; -imm32 r7, 0xe896bcde; -R5.L = -8; -R6 = LSHIFT R0 BY R5.L; -R7 = LSHIFT R1 BY R5.L; -R0 = LSHIFT R2 BY R5.L; -R1 = LSHIFT R3 BY R5.L; -R2 = LSHIFT R4 BY R5.L; -R3 = LSHIFT R5 BY R5.L; -R4 = LSHIFT R6 BY R5.L; -R5 = LSHIFT R7 BY R5.L; -CHECKREG r0, 0x00934667; -CHECKREG r1, 0x00A45678; -CHECKREG r2, 0x00B56689; -CHECKREG r3, 0x00C676FF; -CHECKREG r4, 0x00000126; -CHECKREG r5, 0x00008236; -CHECKREG r6, 0x00012600; -CHECKREG r7, 0x00823656; - -imm32 r0, 0x01270002; -imm32 r1, 0x12375678; -imm32 r2, 0x23476789; -imm32 r3, 0x3457789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56779abc; -imm32 r6, 0x6787abcd; -imm32 r7, 0x7897bcde; -R6.L = -15; -R7 = LSHIFT R0 BY R6.L; -R0 = LSHIFT R1 BY R6.L; -R1 = LSHIFT R2 BY R6.L; -R2 = LSHIFT R3 BY R6.L; -R3 = LSHIFT R4 BY R6.L; -R4 = LSHIFT R5 BY R6.L; -R5 = LSHIFT R6 BY R6.L; -R6 = LSHIFT R7 BY R6.L; -CHECKREG r0, 0x0000246E; -CHECKREG r1, 0x0000468E; -CHECKREG r2, 0x000068AE; -CHECKREG r3, 0x00008ACF; -CHECKREG r4, 0x0000ACEF; -CHECKREG r5, 0x0000CF0F; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x0000024E; - -imm32 r0, 0x01280002; -imm32 r1, 0x82385678; -imm32 r2, 0x93486789; -imm32 r3, 0xa458789a; -imm32 r4, 0xb56889ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xd788abcd; -imm32 r7, 0xe898bcde; -R7.L = -16; -R0 = LSHIFT R0 BY R7.L; -R1 = LSHIFT R1 BY R7.L; -R2 = LSHIFT R2 BY R7.L; -R3 = LSHIFT R3 BY R7.L; -R4 = LSHIFT R4 BY R7.L; -R5 = LSHIFT R5 BY R7.L; -R6 = LSHIFT R6 BY R7.L; -R7 = LSHIFT R7 BY R7.L; -CHECKREG r0, 0x00000128; -CHECKREG r1, 0x00008238; -CHECKREG r2, 0x00009348; -CHECKREG r3, 0x0000A458; -CHECKREG r4, 0x0000B568; -CHECKREG r5, 0x0000C678; -CHECKREG r6, 0x0000D788; -CHECKREG r7, 0x0000E898; - -imm32 r0, 0x81290002; -imm32 r1, 0x92395678; -imm32 r2, 0xa3496789; -imm32 r3, 0xb459789a; -imm32 r4, 0xc56989ab; -imm32 r5, 0xd6799abc; -imm32 r6, 0xe789abcd; -imm32 r7, 0xf899bcde; -R0.L = 4; -//r0 = lshift (r0 by rl0); -R1 = LSHIFT R1 BY R0.L; -R2 = LSHIFT R2 BY R0.L; -R3 = LSHIFT R3 BY R0.L; -R4 = LSHIFT R4 BY R0.L; -R5 = LSHIFT R5 BY R0.L; -R6 = LSHIFT R6 BY R0.L; -R7 = LSHIFT R7 BY R0.L; -CHECKREG r1, 0x23956780; -CHECKREG r2, 0x34967890; -CHECKREG r3, 0x459789A0; -CHECKREG r4, 0x56989AB0; -CHECKREG r5, 0x6799ABC0; -CHECKREG r6, 0x789ABCD0; -CHECKREG r7, 0x899BCDE0; - -imm32 r0, 0x012a0002; -imm32 r1, 0x123a5678; -imm32 r2, 0x234a6789; -imm32 r3, 0x345a789a; -imm32 r4, 0x456a89ab; -imm32 r5, 0x567a9abc; -imm32 r6, 0x678aabcd; -imm32 r7, 0xf89abcde; -R1.L = 2; -R7 = LSHIFT R0 BY R1.L; -R6 = LSHIFT R1 BY R1.L; -R5 = LSHIFT R2 BY R1.L; -R4 = LSHIFT R3 BY R1.L; -R3 = LSHIFT R4 BY R1.L; -R2 = LSHIFT R5 BY R1.L; -R0 = LSHIFT R6 BY R1.L; -R1 = LSHIFT R7 BY R1.L; -CHECKREG r0, 0x23A00020; -CHECKREG r1, 0x12A00020; -CHECKREG r2, 0x34A67890; -CHECKREG r3, 0x45A789A0; -CHECKREG r4, 0xD169E268; -CHECKREG r5, 0x8D299E24; -CHECKREG r6, 0x48E80008; -CHECKREG r7, 0x04A80008; - - -imm32 r0, 0x012b0002; -imm32 r1, 0x123b5678; -imm32 r2, 0x234b6789; -imm32 r3, 0x345b789a; -imm32 r4, 0x456b89ab; -imm32 r5, 0x567b9abc; -imm32 r6, 0x678babcd; -imm32 r7, 0x789bbcde; -R2.L = 15; -R0 = LSHIFT R0 BY R2.L; -R1 = LSHIFT R1 BY R2.L; -R3 = LSHIFT R3 BY R2.L; -R4 = LSHIFT R4 BY R2.L; -R5 = LSHIFT R5 BY R2.L; -R6 = LSHIFT R6 BY R2.L; -R7 = LSHIFT R7 BY R2.L; -R2 = LSHIFT R2 BY R2.L; -CHECKREG r0, 0x80010000; -CHECKREG r1, 0xAB3C0000; -CHECKREG r2, 0x80078000; -CHECKREG r3, 0xBC4D0000; -CHECKREG r4, 0xC4D58000; -CHECKREG r5, 0xCD5E0000; -CHECKREG r6, 0xD5E68000; -CHECKREG r7, 0xDE6F0000; - -imm32 r0, 0x012c0002; -imm32 r1, 0x123c5678; -imm32 r2, 0x234c6789; -imm32 r3, 0x345c789a; -imm32 r4, 0x456c89ab; -imm32 r5, 0x567c9abc; -imm32 r6, 0x678cabcd; -imm32 r7, 0x789cbcde; -R3.L = 16; -R0 = LSHIFT R0 BY R3.L; -R1 = LSHIFT R1 BY R3.L; -R2 = LSHIFT R2 BY R3.L; -R4 = LSHIFT R4 BY R3.L; -R5 = LSHIFT R5 BY R3.L; -R6 = LSHIFT R6 BY R3.L; -R7 = LSHIFT R7 BY R3.L; -R3 = LSHIFT R3 BY R3.L; -CHECKREG r0, 0x00020000; -CHECKREG r1, 0x56780000; -CHECKREG r2, 0x67890000; -CHECKREG r3, 0x00100000; -CHECKREG r4, 0x89AB0000; -CHECKREG r5, 0x9ABC0000; -CHECKREG r6, 0xABCD0000; -CHECKREG r7, 0xBCDE0000; - -imm32 r0, 0x012d0002; -imm32 r1, 0x123d5678; -imm32 r2, 0x234d6789; -imm32 r3, 0x345d789a; -imm32 r4, 0x456d89ab; -imm32 r5, 0x567d9abc; -imm32 r6, 0x678dabcd; -imm32 r7, 0x789dbcde; -R4.L = -9; -R7 = LSHIFT R0 BY R4.L; -R0 = LSHIFT R1 BY R4.L; -R1 = LSHIFT R2 BY R4.L; -R2 = LSHIFT R3 BY R4.L; -//r4 = lshift (r4 by rl4); -R3 = LSHIFT R5 BY R4.L; -R5 = LSHIFT R6 BY R4.L; -R6 = LSHIFT R7 BY R4.L; -CHECKREG r0, 0x00091EAB; -CHECKREG r1, 0x0011A6B3; -CHECKREG r2, 0x001A2EBC; -CHECKREG r3, 0x002B3ECD; -CHECKREG r4, 0x456DFFF7; -CHECKREG r5, 0x0033C6D5; -CHECKREG r6, 0x0000004B; -CHECKREG r7, 0x00009680; - -imm32 r0, 0x012e0002; -imm32 r1, 0x123e5678; -imm32 r2, 0x234e6789; -imm32 r3, 0x345e789a; -imm32 r4, 0x456e89ab; -imm32 r5, 0x567e9abc; -imm32 r6, 0x678eabcd; -imm32 r7, 0x789ebcde; -R5.L = -14; -R0 = LSHIFT R0 BY R5.L; -R1 = LSHIFT R1 BY R5.L; -R2 = LSHIFT R2 BY R5.L; -R3 = LSHIFT R3 BY R5.L; -R4 = LSHIFT R4 BY R5.L; -//r5 = lshift (r5 by rl5); -R6 = LSHIFT R6 BY R5.L; -R7 = LSHIFT R7 BY R5.L; -CHECKREG r0, 0x000004B8; -CHECKREG r1, 0x000048F9; -CHECKREG r2, 0x00008D39; -CHECKREG r3, 0x0000D179; -CHECKREG r4, 0x000115BA; -CHECKREG r5, 0x567EFFF2; -CHECKREG r6, 0x00019E3A; -CHECKREG r7, 0x0001E27A; - - -imm32 r0, 0x012f0002; -imm32 r1, 0x623f5678; -imm32 r2, 0x734f6789; -imm32 r3, 0x845f789a; -imm32 r4, 0x956f89ab; -imm32 r5, 0xa67f9abc; -imm32 r6, 0xc78fabcd; -imm32 r7, 0xd89fbcde; -R6.L = -15; -R0 = LSHIFT R0 BY R6.L; -R1 = LSHIFT R1 BY R6.L; -R2 = LSHIFT R2 BY R6.L; -R3 = LSHIFT R3 BY R6.L; -R4 = LSHIFT R4 BY R6.L; -R5 = LSHIFT R5 BY R6.L; -//r6 = lshift (r6 by rl6); -R7 = LSHIFT R7 BY R6.L; -CHECKREG r0, 0x0000025E; -CHECKREG r1, 0x0000C47E; -CHECKREG r2, 0x0000E69E; -CHECKREG r3, 0x000108BE; -CHECKREG r4, 0x00012ADF; -CHECKREG r5, 0x00014CFF; -CHECKREG r6, 0xC78FFFF1; -CHECKREG r7, 0x0001B13F; - -imm32 r0, 0x71230072; -imm32 r1, 0x82345678; -imm32 r2, 0x93456779; -imm32 r3, 0xa456787a; -imm32 r4, 0xb567897b; -imm32 r5, 0xc6789a7c; -imm32 r6, 0x6789ab7d; -imm32 r7, 0x789abc7e; -R7.L = -16; -R0 = LSHIFT R0 BY R7.L; -R1 = LSHIFT R1 BY R7.L; -R2 = LSHIFT R2 BY R7.L; -R3 = LSHIFT R3 BY R7.L; -R4 = LSHIFT R4 BY R7.L; -R5 = LSHIFT R5 BY R7.L; -R6 = LSHIFT R6 BY R7.L; -R7 = LSHIFT R7 BY R7.L; -CHECKREG r0, 0x00007123; -CHECKREG r1, 0x00008234; -CHECKREG r2, 0x00009345; -CHECKREG r3, 0x0000A456; -CHECKREG r4, 0x0000B567; -CHECKREG r5, 0x0000C678; -CHECKREG r6, 0x00006789; -CHECKREG r7, 0x0000789A; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_ln.s b/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_ln.s deleted file mode 100644 index df47e33..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_ln.s +++ /dev/null @@ -1,422 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_lhalf_ln/c_dsp32shift_lhalf_ln.dsp -// Spec Reference: dsp32shift lshift -# mach: bfin - -.include "testutils.inc" - start - - - -// lshift : neg data, count (+)=left (half reg) -// d_lo = lshift (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x0000c001; -imm32 r2, 0x0000c002; -imm32 r3, 0x0000c003; -imm32 r4, 0x0000c004; -imm32 r5, 0x0000c005; -imm32 r6, 0x0000c006; -imm32 r7, 0x0000c007; -R0.L = LSHIFT R0.L BY R0.L; -R1.L = LSHIFT R1.L BY R0.L; -R2.L = LSHIFT R2.L BY R0.L; -R3.L = LSHIFT R3.L BY R0.L; -R4.L = LSHIFT R4.L BY R0.L; -R5.L = LSHIFT R5.L BY R0.L; -R6.L = LSHIFT R6.L BY R0.L; -R7.L = LSHIFT R7.L BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x0000c001; -CHECKREG r2, 0x0000c002; -CHECKREG r3, 0x0000c003; -CHECKREG r4, 0x0000c004; -CHECKREG r5, 0x0000c005; -CHECKREG r6, 0x0000c006; -CHECKREG r7, 0x0000c007; - -imm32 r0, 0x00008001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000d002; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000c005; -imm32 r6, 0x0000d006; -imm32 r7, 0x0000e007; -R0.L = LSHIFT R0.L BY R1.L; -//rl1 = lshift (rl1 by rl1); -R2.L = LSHIFT R2.L BY R1.L; -R3.L = LSHIFT R3.L BY R1.L; -R4.L = LSHIFT R4.L BY R1.L; -R5.L = LSHIFT R5.L BY R1.L; -R6.L = LSHIFT R6.L BY R1.L; -R7.L = LSHIFT R7.L BY R1.L; -//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */ -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x0000a004; -CHECKREG r3, 0x0000c006; -CHECKREG r4, 0x0000e008; -CHECKREG r5, 0x0000800a; -CHECKREG r6, 0x0000a00c; -CHECKREG r7, 0x0000c00e; - - -imm32 r0, 0x0000c001; -imm32 r1, 0x0000d001; -imm32 r2, 0x0000000f; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000f005; -imm32 r6, 0x0000f006; -imm32 r7, 0x0000f007; -R0.L = LSHIFT R0.L BY R2.L; -R1.L = LSHIFT R1.L BY R2.L; -//rl2 = lshift (rl2 by rl2); -R3.L = LSHIFT R3.L BY R2.L; -R4.L = LSHIFT R4.L BY R2.L; -R5.L = LSHIFT R5.L BY R2.L; -R6.L = LSHIFT R6.L BY R2.L; -R7.L = LSHIFT R7.L BY R2.L; -CHECKREG r0, 0x00008000; -CHECKREG r1, 0x00008000; -CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x00008000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00008000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00008000; - -imm32 r0, 0x00009001; -imm32 r1, 0x0000a001; -imm32 r2, 0x0000b002; -imm32 r3, 0x00000010; -imm32 r4, 0x0000c004; -imm32 r5, 0x0000d005; -imm32 r6, 0x0000e006; -imm32 r7, 0x0000f007; -R0.L = LSHIFT R0.L BY R3.L; -R1.L = LSHIFT R1.L BY R3.L; -R2.L = LSHIFT R2.L BY R3.L; -//rl3 = lshift (rl3 by rl3); -R4.L = LSHIFT R4.L BY R3.L; -R5.L = LSHIFT R5.L BY R3.L; -R6.L = LSHIFT R6.L BY R3.L; -R7.L = LSHIFT R7.L BY R3.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// d_lo = lshft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = LSHIFT R0.H BY R0.L; -R1.L = LSHIFT R1.H BY R0.L; -R2.L = LSHIFT R2.H BY R0.L; -R3.L = LSHIFT R3.H BY R0.L; -R4.L = LSHIFT R4.H BY R0.L; -R5.L = LSHIFT R5.H BY R0.L; -R6.L = LSHIFT R6.H BY R0.L; -R7.L = LSHIFT R7.H BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x90010000; -imm32 r1, 0x00010001; -imm32 r2, 0x90020000; -imm32 r3, 0x90030000; -imm32 r4, 0x90040000; -imm32 r5, 0x90050000; -imm32 r6, 0x90060000; -imm32 r7, 0x90070000; -R0.L = LSHIFT R0.H BY R1.L; -//rl1 = lshift (rh1 by rl1); -R2.L = LSHIFT R2.H BY R1.L; -R3.L = LSHIFT R3.H BY R1.L; -R4.L = LSHIFT R4.H BY R1.L; -R5.L = LSHIFT R5.H BY R1.L; -R6.L = LSHIFT R6.H BY R1.L; -R7.L = LSHIFT R7.H BY R1.L; -CHECKREG r0, 0x90012002; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x90022004; -CHECKREG r3, 0x90032006; -CHECKREG r4, 0x90042008; -CHECKREG r5, 0x9005200a; -CHECKREG r6, 0x9006200c; -CHECKREG r7, 0x9007200e; - - -imm32 r0, 0xa0010000; -imm32 r1, 0xa0010000; -imm32 r2, 0xa002000f; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R0.L = LSHIFT R0.H BY R2.L; -R1.L = LSHIFT R1.H BY R2.L; -//rl2 = lshift (rh2 by rl2); -R3.L = LSHIFT R3.H BY R2.L; -R4.L = LSHIFT R4.H BY R2.L; -R5.L = LSHIFT R5.H BY R2.L; -R6.L = LSHIFT R6.H BY R2.L; -R7.L = LSHIFT R7.H BY R2.L; -CHECKREG r0, 0xa0018000; -CHECKREG r1, 0xa0018000; -CHECKREG r2, 0xa002000f; -CHECKREG r3, 0xa0038000; -CHECKREG r4, 0xa0040000; -CHECKREG r5, 0xa0058000; -CHECKREG r6, 0xa0060000; -CHECKREG r7, 0xa0078000; - -imm32 r0, 0xc0010001; -imm32 r1, 0xc0010001; -imm32 r2, 0xc0020002; -imm32 r3, 0xc0030010; -imm32 r4, 0xc0040004; -imm32 r5, 0xc0050005; -imm32 r6, 0xc0060006; -imm32 r7, 0xc0070007; -R0.L = LSHIFT R0.H BY R3.L; -R1.L = LSHIFT R1.H BY R3.L; -R2.L = LSHIFT R2.H BY R3.L; -//rl3 = lshift (rh3 by rl3); -R4.L = LSHIFT R4.H BY R3.L; -R5.L = LSHIFT R5.H BY R3.L; -R6.L = LSHIFT R6.H BY R3.L; -R7.L = LSHIFT R7.H BY R3.L; -CHECKREG r0, 0xc0010000; -CHECKREG r1, 0xc0010000; -CHECKREG r2, 0xc0020000; -CHECKREG r3, 0xc0030010; -CHECKREG r4, 0xc0040000; -CHECKREG r5, 0xc0050000; -CHECKREG r6, 0xc0060000; -CHECKREG r7, 0xc0070000; - -// d_hi = lshft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = LSHIFT R0.L BY R0.L; -R1.H = LSHIFT R1.L BY R0.L; -R2.H = LSHIFT R2.L BY R0.L; -R3.H = LSHIFT R3.L BY R0.L; -R4.H = LSHIFT R4.L BY R0.L; -R5.H = LSHIFT R5.L BY R0.L; -R6.H = LSHIFT R6.L BY R0.L; -R7.H = LSHIFT R7.L BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x0000d001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000d002; -imm32 r3, 0x0000d003; -imm32 r4, 0x0000d004; -imm32 r5, 0x0000d005; -imm32 r6, 0x0000d006; -imm32 r7, 0x0000d007; -R0.H = LSHIFT R0.L BY R1.L; -R1.H = LSHIFT R1.L BY R1.L; -R2.H = LSHIFT R2.L BY R1.L; -R3.H = LSHIFT R3.L BY R1.L; -R4.H = LSHIFT R4.L BY R1.L; -R5.H = LSHIFT R5.L BY R1.L; -R6.H = LSHIFT R6.L BY R1.L; -R7.H = LSHIFT R7.L BY R1.L; -CHECKREG r0, 0xa002d001; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0xa004d002; -CHECKREG r3, 0xa006d003; -CHECKREG r4, 0xa008d004; -CHECKREG r5, 0xa00ad005; -CHECKREG r6, 0xa00cd006; -CHECKREG r7, 0xa00ed007; - - -imm32 r0, 0x0000e001; -imm32 r1, 0x0000e001; -imm32 r2, 0x0000000f; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000e004; -imm32 r5, 0x0000e005; -imm32 r6, 0x0000e006; -imm32 r7, 0x0000e007; -R0.H = LSHIFT R0.L BY R2.L; -R1.H = LSHIFT R1.L BY R2.L; -//rh2 = lshift (rl2 by rl2); -R3.H = LSHIFT R3.L BY R2.L; -R4.H = LSHIFT R4.L BY R2.L; -R5.H = LSHIFT R5.L BY R2.L; -R6.H = LSHIFT R6.L BY R2.L; -R7.H = LSHIFT R7.L BY R2.L; -CHECKREG r0, 0x8000e001; -CHECKREG r1, 0x8000e001; -CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x8000e003; -CHECKREG r4, 0x0000e004; -CHECKREG r5, 0x8000e005; -CHECKREG r6, 0x0000e006; -CHECKREG r7, 0x8000e007; - -imm32 r0, 0x0000f001; -imm32 r1, 0x0000f001; -imm32 r2, 0x0000f002; -imm32 r3, 0x00000010; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000f005; -imm32 r6, 0x0000f006; -imm32 r7, 0x0000f007; -R0.H = LSHIFT R0.L BY R3.L; -R1.H = LSHIFT R1.L BY R3.L; -R2.H = LSHIFT R2.L BY R3.L; -R3.H = LSHIFT R3.L BY R3.L; -R4.H = LSHIFT R4.L BY R3.L; -R5.H = LSHIFT R5.L BY R3.L; -R6.H = LSHIFT R6.L BY R3.L; -R7.H = LSHIFT R7.L BY R3.L; -CHECKREG r0, 0x0000f001; -CHECKREG r1, 0x0000f001; -CHECKREG r2, 0x0000f002; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x0000f004; -CHECKREG r5, 0x0000f005; -CHECKREG r6, 0x0000f006; -CHECKREG r7, 0x0000f007; - -// d_lo = lshft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = LSHIFT R0.H BY R0.L; -R1.H = LSHIFT R1.H BY R0.L; -R2.H = LSHIFT R2.H BY R0.L; -R3.H = LSHIFT R3.H BY R0.L; -R4.H = LSHIFT R4.H BY R0.L; -R5.H = LSHIFT R5.H BY R0.L; -R6.H = LSHIFT R6.H BY R0.L; -R7.H = LSHIFT R7.H BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x00020000; -CHECKREG r3, 0x00030000; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00050000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00070000; - -imm32 r0, 0xa0010000; -imm32 r1, 0x00010001; -imm32 r2, 0xa0020000; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R0.H = LSHIFT R0.H BY R1.L; -R1.H = LSHIFT R1.H BY R1.L; -R2.H = LSHIFT R2.H BY R1.L; -R3.H = LSHIFT R3.H BY R1.L; -R4.H = LSHIFT R4.H BY R1.L; -R5.H = LSHIFT R5.H BY R1.L; -R6.H = LSHIFT R6.H BY R1.L; -R7.H = LSHIFT R7.H BY R1.L; -CHECKREG r0, 0x40020000; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0x40040000; -CHECKREG r3, 0x40060000; -CHECKREG r4, 0x40080000; -CHECKREG r5, 0x400a0000; -CHECKREG r6, 0x400c0000; -CHECKREG r7, 0x400e0000; - - -imm32 r0, 0xb0010000; -imm32 r1, 0xb0010000; -imm32 r2, 0xb002000f; -imm32 r3, 0xb0030000; -imm32 r4, 0xb0040000; -imm32 r5, 0xb0050000; -imm32 r6, 0xb0060000; -imm32 r7, 0xb0070000; -R0.L = LSHIFT R0.H BY R2.L; -R1.L = LSHIFT R1.H BY R2.L; -//rl2 = lshift (rh2 by rl2); -R3.L = LSHIFT R3.H BY R2.L; -R4.L = LSHIFT R4.H BY R2.L; -R5.L = LSHIFT R5.H BY R2.L; -R6.L = LSHIFT R6.H BY R2.L; -R7.L = LSHIFT R7.H BY R2.L; -CHECKREG r0, 0xb0018000; -CHECKREG r1, 0xb0018000; -CHECKREG r2, 0xb002000f; -CHECKREG r3, 0xb0038000; -CHECKREG r4, 0xb0040000; -CHECKREG r5, 0xb0058000; -CHECKREG r6, 0xb0060000; -CHECKREG r7, 0xb0078000; - -imm32 r0, 0xd0010000; -imm32 r1, 0xd0010000; -imm32 r2, 0xd0020000; -imm32 r3, 0xd0030010; -imm32 r4, 0xd0040000; -imm32 r5, 0xd0050000; -imm32 r6, 0xd0060000; -imm32 r7, 0xd0070000; -R0.H = LSHIFT R0.H BY R3.L; -R1.H = LSHIFT R1.H BY R3.L; -R2.H = LSHIFT R2.H BY R3.L; -R3.H = LSHIFT R3.H BY R3.L; -R4.H = LSHIFT R4.H BY R3.L; -R5.H = LSHIFT R5.H BY R3.L; -R6.H = LSHIFT R6.H BY R3.L; -R7.H = LSHIFT R7.H BY R3.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_lp.s b/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_lp.s deleted file mode 100644 index 6000715..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_lp.s +++ /dev/null @@ -1,422 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_lhalf_lp/c_dsp32shift_lhalf_lp.dsp -// Spec Reference: dsp32shift lshift -# mach: bfin - -.include "testutils.inc" - start - - - -// lshift : positive data, count (+)=left (half reg) -// d_lo = lshift (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.L = LSHIFT R0.L BY R0.L; -R1.L = LSHIFT R1.L BY R0.L; -R2.L = LSHIFT R2.L BY R0.L; -R3.L = LSHIFT R3.L BY R0.L; -R4.L = LSHIFT R4.L BY R0.L; -R5.L = LSHIFT R5.L BY R0.L; -R6.L = LSHIFT R6.L BY R0.L; -R7.L = LSHIFT R7.L BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00000003; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x00000005; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x00000007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.L = LSHIFT R0.L BY R1.L; -//rl1 = lshift (rl1 by rl1); -R2.L = LSHIFT R2.L BY R1.L; -R3.L = LSHIFT R3.L BY R1.L; -R4.L = LSHIFT R4.L BY R1.L; -R5.L = LSHIFT R5.L BY R1.L; -R6.L = LSHIFT R6.L BY R1.L; -R7.L = LSHIFT R7.L BY R1.L; -CHECKREG r0, 0x00000002; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000004; -CHECKREG r3, 0x00000006; -CHECKREG r4, 0x00000008; -CHECKREG r5, 0x0000000a; -CHECKREG r6, 0x0000000c; -CHECKREG r7, 0x0000000e; - - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000000f; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.L = LSHIFT R0.L BY R2.L; -R1.L = LSHIFT R1.L BY R2.L; -//rl2 = lshift (rl2 by rl2); -R3.L = LSHIFT R3.L BY R2.L; -R4.L = LSHIFT R4.L BY R2.L; -R5.L = LSHIFT R5.L BY R2.L; -R6.L = LSHIFT R6.L BY R2.L; -R7.L = LSHIFT R7.L BY R2.L; -CHECKREG r0, 0x00008000; -CHECKREG r1, 0x00008000; -CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x00008000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00008000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00008000; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000010; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.L = LSHIFT R0.L BY R3.L; -R1.L = LSHIFT R1.L BY R3.L; -R2.L = LSHIFT R2.L BY R3.L; -//rl3 = lshift (rl3 by rl3); -R4.L = LSHIFT R4.L BY R3.L; -R5.L = LSHIFT R5.L BY R3.L; -R6.L = LSHIFT R6.L BY R3.L; -R7.L = LSHIFT R7.L BY R3.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = LSHIFT R0.H BY R0.L; -R1.L = LSHIFT R1.H BY R0.L; -R2.L = LSHIFT R2.H BY R0.L; -R3.L = LSHIFT R3.H BY R0.L; -R4.L = LSHIFT R4.H BY R0.L; -R5.L = LSHIFT R5.H BY R0.L; -R6.L = LSHIFT R6.H BY R0.L; -R7.L = LSHIFT R7.H BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x00010000; -imm32 r1, 0x00010001; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = LSHIFT R0.H BY R1.L; -//rl1 = lshift (rh1 by rl1); -R2.L = LSHIFT R2.H BY R1.L; -R3.L = LSHIFT R3.H BY R1.L; -R4.L = LSHIFT R4.H BY R1.L; -R5.L = LSHIFT R5.H BY R1.L; -R6.L = LSHIFT R6.H BY R1.L; -R7.L = LSHIFT R7.H BY R1.L; -CHECKREG r0, 0x00010002; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020004; -CHECKREG r3, 0x00030006; -CHECKREG r4, 0x00040008; -CHECKREG r5, 0x0005000a; -CHECKREG r6, 0x0006000c; -CHECKREG r7, 0x0007000e; - - -imm32 r0, 0x00010000; -imm32 r1, 0x00010000; -imm32 r2, 0x0002000f; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = LSHIFT R0.H BY R2.L; -R1.L = LSHIFT R1.H BY R2.L; -//rl2 = lshift (rh2 by rl2); -R3.L = LSHIFT R3.H BY R2.L; -R4.L = LSHIFT R4.H BY R2.L; -R5.L = LSHIFT R5.H BY R2.L; -R6.L = LSHIFT R6.H BY R2.L; -R7.L = LSHIFT R7.H BY R2.L; -CHECKREG r0, 0x00018000; -CHECKREG r1, 0x00018000; -CHECKREG r2, 0x0002000f; -CHECKREG r3, 0x00038000; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00058000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00078000; - -imm32 r0, 0x00010001; -imm32 r1, 0x00010001; -imm32 r2, 0x00020002; -imm32 r3, 0x00030010; -imm32 r4, 0x00040004; -imm32 r5, 0x00050005; -imm32 r6, 0x00060006; -imm32 r7, 0x00070007; -R0.L = LSHIFT R0.H BY R3.L; -R1.L = LSHIFT R1.H BY R3.L; -R2.L = LSHIFT R2.H BY R3.L; -//rl3 = lshift (rh3 by rl3); -R4.L = LSHIFT R4.H BY R3.L; -R5.L = LSHIFT R5.H BY R3.L; -R6.L = LSHIFT R6.H BY R3.L; -R7.L = LSHIFT R7.H BY R3.L; -CHECKREG r0, 0x00010000; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x00020000; -CHECKREG r3, 0x00030010; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00050000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00070000; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = LSHIFT R0.L BY R0.L; -R1.H = LSHIFT R1.L BY R0.L; -R2.H = LSHIFT R2.L BY R0.L; -R3.H = LSHIFT R3.L BY R0.L; -R4.H = LSHIFT R4.L BY R0.L; -R5.H = LSHIFT R5.L BY R0.L; -R6.H = LSHIFT R6.L BY R0.L; -R7.H = LSHIFT R7.L BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = LSHIFT R0.L BY R1.L; -R1.H = LSHIFT R1.L BY R1.L; -R2.H = LSHIFT R2.L BY R1.L; -R3.H = LSHIFT R3.L BY R1.L; -R4.H = LSHIFT R4.L BY R1.L; -R5.H = LSHIFT R5.L BY R1.L; -R6.H = LSHIFT R6.L BY R1.L; -R7.H = LSHIFT R7.L BY R1.L; -CHECKREG r0, 0x00020001; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0x00040002; -CHECKREG r3, 0x00060003; -CHECKREG r4, 0x00080004; -CHECKREG r5, 0x000a0005; -CHECKREG r6, 0x000c0006; -CHECKREG r7, 0x000e0007; - - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000000f; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = LSHIFT R0.L BY R2.L; -R1.H = LSHIFT R1.L BY R2.L; -//rh2 = lshift (rl2 by rl2); -R3.H = LSHIFT R3.L BY R2.L; -R4.H = LSHIFT R4.L BY R2.L; -R5.H = LSHIFT R5.L BY R2.L; -R6.H = LSHIFT R6.L BY R2.L; -R7.H = LSHIFT R7.L BY R2.L; -CHECKREG r0, 0x80000001; -CHECKREG r1, 0x80000001; -CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x80000003; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x80000005; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x80000007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000010; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = LSHIFT R0.L BY R3.L; -R1.H = LSHIFT R1.L BY R3.L; -R2.H = LSHIFT R2.L BY R3.L; -R3.H = LSHIFT R3.L BY R3.L; -R4.H = LSHIFT R4.L BY R3.L; -R5.H = LSHIFT R5.L BY R3.L; -R6.H = LSHIFT R6.L BY R3.L; -R7.H = LSHIFT R7.L BY R3.L; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x00000005; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x00000007; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = LSHIFT R0.H BY R0.L; -R1.H = LSHIFT R1.H BY R0.L; -R2.H = LSHIFT R2.H BY R0.L; -R3.H = LSHIFT R3.H BY R0.L; -R4.H = LSHIFT R4.H BY R0.L; -R5.H = LSHIFT R5.H BY R0.L; -R6.H = LSHIFT R6.H BY R0.L; -R7.H = LSHIFT R7.H BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x00020000; -CHECKREG r3, 0x00030000; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00050000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00070000; - -imm32 r0, 0x00010000; -imm32 r1, 0x00010001; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = LSHIFT R0.H BY R1.L; -R1.H = LSHIFT R1.H BY R1.L; -R2.H = LSHIFT R2.H BY R1.L; -R3.H = LSHIFT R3.H BY R1.L; -R4.H = LSHIFT R4.H BY R1.L; -R5.H = LSHIFT R5.H BY R1.L; -R6.H = LSHIFT R6.H BY R1.L; -R7.H = LSHIFT R7.H BY R1.L; -CHECKREG r0, 0x00020000; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0x00040000; -CHECKREG r3, 0x00060000; -CHECKREG r4, 0x00080000; -CHECKREG r5, 0x000a0000; -CHECKREG r6, 0x000c0000; -CHECKREG r7, 0x000e0000; - - -imm32 r0, 0x00010000; -imm32 r1, 0x00010000; -imm32 r2, 0x0002000f; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = LSHIFT R0.H BY R2.L; -R1.L = LSHIFT R1.H BY R2.L; -//rl2 = lshift (rh2 by rl2); -R3.L = LSHIFT R3.H BY R2.L; -R4.L = LSHIFT R4.H BY R2.L; -R5.L = LSHIFT R5.H BY R2.L; -R6.L = LSHIFT R6.H BY R2.L; -R7.L = LSHIFT R7.H BY R2.L; -CHECKREG r0, 0x00018000; -CHECKREG r1, 0x00018000; -CHECKREG r2, 0x0002000f; -CHECKREG r3, 0x00038000; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00058000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00078000; - -imm32 r0, 0x00010000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030010; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = LSHIFT R0.H BY R3.L; -R1.H = LSHIFT R1.H BY R3.L; -R2.H = LSHIFT R2.H BY R3.L; -R3.H = LSHIFT R3.H BY R3.L; -R4.H = LSHIFT R4.H BY R3.L; -R5.H = LSHIFT R5.H BY R3.L; -R6.H = LSHIFT R6.H BY R3.L; -R7.H = LSHIFT R7.H BY R3.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rn.s b/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rn.s deleted file mode 100644 index a5b6563..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rn.s +++ /dev/null @@ -1,425 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_lhalf_rn/c_dsp32shift_lhalf_rn.dsp -// Spec Reference: dsp32shift lshift -# mach: bfin - -.include "testutils.inc" - start - - - - -// lshift : positive data, count (+)=left (half reg) -// d_lo = lshift (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -R0.L = -1; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -//rl0 = lshift (rl0 by rl0); -R1.L = LSHIFT R1.L BY R0.L; -R2.L = LSHIFT R2.L BY R0.L; -R3.L = LSHIFT R3.L BY R0.L; -R4.L = LSHIFT R4.L BY R0.L; -R5.L = LSHIFT R5.L BY R0.L; -R6.L = LSHIFT R6.L BY R0.L; -R7.L = LSHIFT R7.L BY R0.L; -//CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00004000; -CHECKREG r2, 0x00004001; -CHECKREG r3, 0x00004001; -CHECKREG r4, 0x00004002; -CHECKREG r5, 0x00004002; -CHECKREG r6, 0x00004003; -CHECKREG r7, 0x00004003; - -imm32 r0, 0x00008001; -R1.L = -1; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = LSHIFT R0.L BY R1.L; -//rl1 = lshift (rl1 by rl1); -R2.L = LSHIFT R2.L BY R1.L; -R3.L = LSHIFT R3.L BY R1.L; -R4.L = LSHIFT R4.L BY R1.L; -R5.L = LSHIFT R5.L BY R1.L; -R6.L = LSHIFT R6.L BY R1.L; -R7.L = LSHIFT R7.L BY R1.L; -CHECKREG r0, 0x00004000; -//CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00004001; -CHECKREG r3, 0x00004001; -CHECKREG r4, 0x00004002; -CHECKREG r5, 0x00004002; -CHECKREG r6, 0x00004003; -CHECKREG r7, 0x00004003; - - -imm32 r0, 0x00008001; -imm32 r1, 0x00008001; -R2.L = -15; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = LSHIFT R0.L BY R2.L; -R1.L = LSHIFT R1.L BY R2.L; -//rl2 = lshift (rl2 by rl2); -R3.L = LSHIFT R3.L BY R2.L; -R4.L = LSHIFT R4.L BY R2.L; -R5.L = LSHIFT R5.L BY R2.L; -R6.L = LSHIFT R6.L BY R2.L; -R7.L = LSHIFT R7.L BY R2.L; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -//CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000001; - -imm32 r0, 0x00008001; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -R3.L = -16; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = LSHIFT R0.L BY R3.L; -R1.L = LSHIFT R1.L BY R3.L; -R2.L = LSHIFT R2.L BY R3.L; -//rl3 = lshift (rl3 by rl3); -R4.L = LSHIFT R4.L BY R3.L; -R5.L = LSHIFT R5.L BY R3.L; -R6.L = LSHIFT R6.L BY R3.L; -R7.L = LSHIFT R7.L BY R3.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -//CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x80010000; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -imm32 r4, 0x80040000; -imm32 r5, 0x80050000; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.L = LSHIFT R0.H BY R0.L; -R1.L = LSHIFT R1.H BY R0.L; -R2.L = LSHIFT R2.H BY R0.L; -R3.L = LSHIFT R3.H BY R0.L; -R4.L = LSHIFT R4.H BY R0.L; -R5.L = LSHIFT R5.H BY R0.L; -R6.L = LSHIFT R6.H BY R0.L; -R7.L = LSHIFT R7.H BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x80018001; -CHECKREG r2, 0x80028002; -CHECKREG r3, 0x80038003; -CHECKREG r4, 0x80048004; -CHECKREG r5, 0x80058005; -CHECKREG r6, 0x80068006; -CHECKREG r7, 0x80078007; - -imm32 r0, 0x80010000; -R1.L = -1; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -imm32 r4, 0x80040000; -imm32 r5, 0x80050000; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.L = LSHIFT R0.H BY R1.L; -//rl1 = lshift (rh1 by rl1); -R2.L = LSHIFT R2.H BY R1.L; -R3.L = LSHIFT R3.H BY R1.L; -R4.L = LSHIFT R4.H BY R1.L; -R5.L = LSHIFT R5.H BY R1.L; -R6.L = LSHIFT R6.H BY R1.L; -R7.L = LSHIFT R7.H BY R1.L; -CHECKREG r0, 0x80014000; -//CHECKREG r1, 0x00010001; -CHECKREG r2, 0x80024001; -CHECKREG r3, 0x80034001; -CHECKREG r4, 0x80044002; -CHECKREG r5, 0x80054002; -CHECKREG r6, 0x80064003; -CHECKREG r7, 0x80074003; - - -imm32 r0, 0xa0010000; -imm32 r1, 0xa0010000; -R2.L = -15; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R0.L = LSHIFT R0.H BY R2.L; -R1.L = LSHIFT R1.H BY R2.L; -//rl2 = lshift (rh2 by rl2); -R3.L = LSHIFT R3.H BY R2.L; -R4.L = LSHIFT R4.H BY R2.L; -R5.L = LSHIFT R5.H BY R2.L; -R6.L = LSHIFT R6.H BY R2.L; -R7.L = LSHIFT R7.H BY R2.L; -CHECKREG r0, 0xa0010001; -CHECKREG r1, 0xa0010001; -//CHECKREG r2, 0x2002000f; -CHECKREG r3, 0xa0030001; -CHECKREG r4, 0xa0040001; -CHECKREG r5, 0xa0050001; -CHECKREG r6, 0xa0060001; -CHECKREG r7, 0xa0070001; - -imm32 r0, 0xb0010001; -imm32 r1, 0xb0010001; -imm32 r2, 0xb0020002; -R3.L = -16; -imm32 r4, 0xb0040004; -imm32 r5, 0xb0050005; -imm32 r6, 0xb0060006; -imm32 r7, 0xb0070007; -R0.L = LSHIFT R0.H BY R3.L; -R1.L = LSHIFT R1.H BY R3.L; -R2.L = LSHIFT R2.H BY R3.L; -//rl3 = lshift (rh3 by rl3); -R4.L = LSHIFT R4.H BY R3.L; -R5.L = LSHIFT R5.H BY R3.L; -R6.L = LSHIFT R6.H BY R3.L; -R7.L = LSHIFT R7.H BY R3.L; -CHECKREG r0, 0xb0010000; -CHECKREG r1, 0xb0010000; -CHECKREG r2, 0xb0020000; -//CHECKREG r3, 0x30030010; -CHECKREG r4, 0xb0040000; -CHECKREG r5, 0xb0050000; -CHECKREG r6, 0xb0060000; -CHECKREG r7, 0xb0070000; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000000; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = LSHIFT R0.L BY R4.L; -R1.H = LSHIFT R1.L BY R4.L; -R2.H = LSHIFT R2.L BY R4.L; -R3.H = LSHIFT R3.L BY R4.L; -//rh4 = lshift (rl4 by rl4); -R5.H = LSHIFT R5.L BY R4.L; -R6.H = LSHIFT R6.L BY R4.L; -R7.H = LSHIFT R7.L BY R4.L; -CHECKREG r0, 0x00010001; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -//CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x00008001; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -R5.L = -1; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.H = LSHIFT R0.L BY R5.L; -R1.H = LSHIFT R1.L BY R5.L; -R2.H = LSHIFT R2.L BY R5.L; -R3.H = LSHIFT R3.L BY R5.L; -R4.H = LSHIFT R4.L BY R5.L; -//rh5 = lshift (rl5 by rl5); -R6.H = LSHIFT R6.L BY R5.L; -R7.H = LSHIFT R7.L BY R5.L; -CHECKREG r0, 0x40008001; -CHECKREG r1, 0x40008001; -CHECKREG r2, 0x40018002; -CHECKREG r3, 0x40018003; -CHECKREG r4, 0x40028004; -//CHECKREG r5, 0x00020005; -CHECKREG r6, 0x40038006; -CHECKREG r7, 0x40038007; - - -imm32 r0, 0x00009001; -imm32 r1, 0x00009001; -imm32 r2, 0x00009002; -imm32 r3, 0x00009003; -imm32 r4, 0x00009004; -imm32 r5, 0x00009005; -R6.L = -15; -imm32 r7, 0x00009007; -R0.H = LSHIFT R0.L BY R6.L; -R1.H = LSHIFT R1.L BY R6.L; -R2.H = LSHIFT R2.L BY R6.L; -R3.H = LSHIFT R3.L BY R6.L; -R4.H = LSHIFT R4.L BY R6.L; -R5.H = LSHIFT R5.L BY R6.L; -//rh6 = lshift (rl6 by rl6); -R7.H = LSHIFT R7.L BY R6.L; -CHECKREG r0, 0x00019001; -CHECKREG r1, 0x00019001; -CHECKREG r2, 0x00019002; -CHECKREG r3, 0x00019003; -CHECKREG r4, 0x00019004; -CHECKREG r5, 0x00019005; -//CHECKREG r6, 0x00006006; -CHECKREG r7, 0x00019007; - -imm32 r0, 0x0000a001; -imm32 r1, 0x0000a001; -imm32 r2, 0x0000a002; -imm32 r3, 0x0000a003; -imm32 r4, 0x0000a004; -imm32 r5, 0x0000a005; -imm32 r6, 0x0000a006; -R7.L = -16; -R0.H = LSHIFT R0.L BY R7.L; -R1.H = LSHIFT R1.L BY R7.L; -R2.H = LSHIFT R2.L BY R7.L; -R3.H = LSHIFT R3.L BY R7.L; -R4.H = LSHIFT R4.L BY R7.L; -R5.H = LSHIFT R5.L BY R7.L; -R6.H = LSHIFT R6.L BY R7.L; -R7.H = LSHIFT R7.L BY R7.L; -CHECKREG r0, 0x0000a001; -CHECKREG r1, 0x0000a001; -CHECKREG r2, 0x0000a002; -CHECKREG r3, 0x0000a003; -CHECKREG r4, 0x0000a004; -CHECKREG r5, 0x0000a005; -CHECKREG r6, 0x0000a006; -//CHECKREG r7, 0x00007007; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x80010000; -imm32 r1, 0x80010000; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -R4.L = -1; -imm32 r5, 0x80050000; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.H = LSHIFT R0.H BY R4.L; -R1.H = LSHIFT R1.H BY R4.L; -R2.H = LSHIFT R2.H BY R4.L; -R3.H = LSHIFT R3.H BY R4.L; -//rh4 = lshift (rh4 by rl4); -R5.H = LSHIFT R5.H BY R4.L; -R6.H = LSHIFT R6.H BY R4.L; -R7.H = LSHIFT R7.H BY R4.L; -CHECKREG r0, 0x40000000; -CHECKREG r1, 0x40000000; -CHECKREG r2, 0x40010000; -CHECKREG r3, 0x40010000; -//CHECKREG r4, 0x00020000; -CHECKREG r5, 0x40020000; -CHECKREG r6, 0x40030000; -CHECKREG r7, 0x40030000; - -imm32 r0, 0x80010000; -imm32 r1, 0x80010000; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -imm32 r4, 0x80040000; -R5.L = -1; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.H = LSHIFT R0.H BY R5.L; -R1.H = LSHIFT R1.H BY R5.L; -R2.H = LSHIFT R2.H BY R5.L; -R3.H = LSHIFT R3.H BY R5.L; -R4.H = LSHIFT R4.H BY R5.L; -//rh5 = lshift (rh5 by rl5); -R6.H = LSHIFT R6.H BY R5.L; -R7.H = LSHIFT R7.H BY R5.L; -CHECKREG r0, 0x40000000; -CHECKREG r1, 0x40000000; -CHECKREG r2, 0x40010000; -CHECKREG r3, 0x40010000; -CHECKREG r4, 0x40020000; -//CHECKREG r5, 0x28020000; -CHECKREG r6, 0x40030000; -CHECKREG r7, 0x40030000; - - -imm32 r0, 0xd0010000; -imm32 r1, 0xd0010000; -imm32 r2, 0xd0020000; -imm32 r3, 0xd0030000; -imm32 r4, 0xd0040000; -imm32 r5, 0xd0050000; -R6.L = -15; -imm32 r7, 0xd0070000; -R0.L = LSHIFT R0.H BY R6.L; -R1.L = LSHIFT R1.H BY R6.L; -R2.L = LSHIFT R2.H BY R6.L; -R3.L = LSHIFT R3.H BY R6.L; -R4.L = LSHIFT R4.H BY R6.L; -R5.L = LSHIFT R5.H BY R6.L; -//rl6 = lshift (rh6 by rl6); -R7.L = LSHIFT R7.H BY R6.L; -CHECKREG r0, 0xd0010001; -CHECKREG r1, 0xd0010001; -CHECKREG r2, 0xd0020001; -CHECKREG r3, 0xd0030001; -CHECKREG r4, 0xd0040001; -CHECKREG r5, 0xd0050001; -//CHECKREG r6, 0x60060000; -CHECKREG r7, 0xd0070001; - -imm32 r0, 0xe0010000; -imm32 r1, 0xe0010000; -imm32 r2, 0xe0020000; -imm32 r3, 0xe0030000; -imm32 r4, 0xe0040000; -imm32 r5, 0xe0050000; -imm32 r6, 0xe0060000; -R7.L = -16; -R0.H = LSHIFT R0.H BY R7.L; -R1.H = LSHIFT R1.H BY R7.L; -R2.H = LSHIFT R2.H BY R7.L; -R3.H = LSHIFT R3.H BY R7.L; -R4.H = LSHIFT R4.H BY R7.L; -R5.H = LSHIFT R5.H BY R7.L; -R6.H = LSHIFT R6.H BY R7.L; -//rh7 = lshift (rh7 by rl7); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -//CHECKREG r7, -16; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rp.s b/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rp.s deleted file mode 100644 index 45fa6a0..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rp.s +++ /dev/null @@ -1,423 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_lhalf_rp/c_dsp32shift_lhalf_rp.dsp -// Spec Reference: dsp32shift lshift -# mach: bfin - -.include "testutils.inc" - start - - - -// lshift : positive data, count (+)=left (half reg) -// d_lo = lshift (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -R0.L = -1; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -//rl0 = lshift (rl0 by rl0); -R1.L = LSHIFT R1.L BY R0.L; -R2.L = LSHIFT R2.L BY R0.L; -R3.L = LSHIFT R3.L BY R0.L; -R4.L = LSHIFT R4.L BY R0.L; -R5.L = LSHIFT R5.L BY R0.L; -R6.L = LSHIFT R6.L BY R0.L; -R7.L = LSHIFT R7.L BY R0.L; -//CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000002; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000003; -CHECKREG r7, 0x00000003; - -imm32 r0, 0x00001001; -R1.L = -1; -imm32 r2, 0x00002002; -imm32 r3, 0x00003003; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -imm32 r6, 0x00006006; -imm32 r7, 0x00007007; -R0.L = LSHIFT R0.L BY R1.L; -//rl1 = lshift (rl1 by rl1); -R2.L = LSHIFT R2.L BY R1.L; -R3.L = LSHIFT R3.L BY R1.L; -R4.L = LSHIFT R4.L BY R1.L; -R5.L = LSHIFT R5.L BY R1.L; -R6.L = LSHIFT R6.L BY R1.L; -R7.L = LSHIFT R7.L BY R1.L; -CHECKREG r0, 0x00000800; -//CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00001001; -CHECKREG r3, 0x00001801; -CHECKREG r4, 0x00002002; -CHECKREG r5, 0x00002802; -CHECKREG r6, 0x00003003; -CHECKREG r7, 0x00003803; - - -imm32 r0, 0x00001001; -imm32 r1, 0x00001001; -R2.L = -15; -imm32 r3, 0x00003003; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -imm32 r6, 0x00006006; -imm32 r7, 0x00007007; -R0.L = LSHIFT R0.L BY R2.L; -R1.L = LSHIFT R1.L BY R2.L; -//rl2 = lshift (rl2 by rl2); -R3.L = LSHIFT R3.L BY R2.L; -R4.L = LSHIFT R4.L BY R2.L; -R5.L = LSHIFT R5.L BY R2.L; -R6.L = LSHIFT R6.L BY R2.L; -R7.L = LSHIFT R7.L BY R2.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -//CHECKREG r2, 0x0000000f; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x00001001; -imm32 r1, 0x00001001; -imm32 r2, 0x00002002; -R3.L = -16; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -imm32 r6, 0x00006006; -imm32 r7, 0x00007007; -R0.L = LSHIFT R0.L BY R3.L; -R1.L = LSHIFT R1.L BY R3.L; -R2.L = LSHIFT R2.L BY R3.L; -//rl3 = lshift (rl3 by rl3); -R4.L = LSHIFT R4.L BY R3.L; -R5.L = LSHIFT R5.L BY R3.L; -R6.L = LSHIFT R6.L BY R3.L; -R7.L = LSHIFT R7.L BY R3.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -//CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = LSHIFT R0.H BY R0.L; -R1.L = LSHIFT R1.H BY R0.L; -R2.L = LSHIFT R2.H BY R0.L; -R3.L = LSHIFT R3.H BY R0.L; -R4.L = LSHIFT R4.H BY R0.L; -R5.L = LSHIFT R5.H BY R0.L; -R6.L = LSHIFT R6.H BY R0.L; -R7.L = LSHIFT R7.H BY R0.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x10010000; -R1.L = -1; -imm32 r2, 0x20020000; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -imm32 r6, 0x60060000; -imm32 r7, 0x70070000; -R0.L = LSHIFT R0.H BY R1.L; -//rl1 = lshift (rh1 by rl1); -R2.L = LSHIFT R2.H BY R1.L; -R3.L = LSHIFT R3.H BY R1.L; -R4.L = LSHIFT R4.H BY R1.L; -R5.L = LSHIFT R5.H BY R1.L; -R6.L = LSHIFT R6.H BY R1.L; -R7.L = LSHIFT R7.H BY R1.L; -CHECKREG r0, 0x10010800; -//CHECKREG r1, 0x00010001; -CHECKREG r2, 0x20021001; -CHECKREG r3, 0x30031801; -CHECKREG r4, 0x40042002; -CHECKREG r5, 0x50052802; -CHECKREG r6, 0x60063003; -CHECKREG r7, 0x70073803; - - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -R2.L = -15; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -imm32 r6, 0x60060000; -imm32 r7, 0x70070000; -R0.L = LSHIFT R0.H BY R2.L; -R1.L = LSHIFT R1.H BY R2.L; -//rl2 = lshift (rh2 by rl2); -R3.L = LSHIFT R3.H BY R2.L; -R4.L = LSHIFT R4.H BY R2.L; -R5.L = LSHIFT R5.H BY R2.L; -R6.L = LSHIFT R6.H BY R2.L; -R7.L = LSHIFT R7.H BY R2.L; -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -//CHECKREG r2, 0x2002000f; -CHECKREG r3, 0x30030000; -CHECKREG r4, 0x40040000; -CHECKREG r5, 0x50050000; -CHECKREG r6, 0x60060000; -CHECKREG r7, 0x70070000; - -imm32 r0, 0x10010001; -imm32 r1, 0x10010001; -imm32 r2, 0x20020002; -R3.L = -16; -imm32 r4, 0x40040004; -imm32 r5, 0x50050005; -imm32 r6, 0x60060006; -imm32 r7, 0x70070007; -R0.L = LSHIFT R0.H BY R3.L; -R1.L = LSHIFT R1.H BY R3.L; -R2.L = LSHIFT R2.H BY R3.L; -//rl3 = lshift (rh3 by rl3); -R4.L = LSHIFT R4.H BY R3.L; -R5.L = LSHIFT R5.H BY R3.L; -R6.L = LSHIFT R6.H BY R3.L; -R7.L = LSHIFT R7.H BY R3.L; -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -CHECKREG r2, 0x20020000; -//CHECKREG r3, 0x30030010; -CHECKREG r4, 0x40040000; -CHECKREG r5, 0x50050000; -CHECKREG r6, 0x60060000; -CHECKREG r7, 0x70070000; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000000; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = LSHIFT R0.L BY R4.L; -R1.H = LSHIFT R1.L BY R4.L; -R2.H = LSHIFT R2.L BY R4.L; -R3.H = LSHIFT R3.L BY R4.L; -//rh4 = lshift (rl4 by rl4); -R5.H = LSHIFT R5.L BY R4.L; -R6.H = LSHIFT R6.L BY R4.L; -R7.H = LSHIFT R7.L BY R4.L; -CHECKREG r0, 0x00010001; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -//CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -R5.L = -1; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = LSHIFT R0.L BY R5.L; -R1.H = LSHIFT R1.L BY R5.L; -R2.H = LSHIFT R2.L BY R5.L; -R3.H = LSHIFT R3.L BY R5.L; -R4.H = LSHIFT R4.L BY R5.L; -//rh5 = lshift (rl5 by rl5); -R6.H = LSHIFT R6.L BY R5.L; -R7.H = LSHIFT R7.L BY R5.L; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00010002; -CHECKREG r3, 0x00010003; -CHECKREG r4, 0x00020004; -//CHECKREG r5, 0x00020005; -CHECKREG r6, 0x00030006; -CHECKREG r7, 0x00030007; - - -imm32 r0, 0x00001001; -imm32 r1, 0x00001001; -imm32 r1, 0x00002002; -imm32 r3, 0x00003003; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -R6.L = -15; -imm32 r7, 0x00007007; -R0.H = LSHIFT R0.L BY R6.L; -R1.H = LSHIFT R1.L BY R6.L; -R2.H = LSHIFT R2.L BY R6.L; -R3.H = LSHIFT R3.L BY R6.L; -R4.H = LSHIFT R4.L BY R6.L; -R5.H = LSHIFT R5.L BY R6.L; -//rh6 = lshift (rl6 by rl6); -R7.H = LSHIFT R7.L BY R6.L; -CHECKREG r0, 0x00001001; -CHECKREG r1, 0x00002002; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00003003; -CHECKREG r4, 0x00004004; -CHECKREG r5, 0x00005005; -//CHECKREG r6, 0x00006006; -CHECKREG r7, 0x00007007; - -imm32 r0, 0x00001001; -imm32 r1, 0x00002001; -imm32 r2, 0x00002002; -imm32 r3, 0x00003003; -imm32 r4, 0x00004004; -imm32 r5, 0x00005005; -imm32 r6, 0x00006006; -R7.L = -16; -R0.H = LSHIFT R0.L BY R7.L; -R1.H = LSHIFT R1.L BY R7.L; -R2.H = LSHIFT R2.L BY R7.L; -R3.H = LSHIFT R3.L BY R7.L; -R4.H = LSHIFT R4.L BY R7.L; -R5.H = LSHIFT R5.L BY R7.L; -R6.H = LSHIFT R6.L BY R7.L; -R7.H = LSHIFT R7.L BY R7.L; -CHECKREG r0, 0x00001001; -CHECKREG r1, 0x00002001; -CHECKREG r2, 0x00002002; -CHECKREG r3, 0x00003003; -CHECKREG r4, 0x00004004; -CHECKREG r5, 0x00005005; -CHECKREG r6, 0x00006006; -//CHECKREG r7, 0x00007007; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00010000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -R4.L = -1; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = LSHIFT R0.H BY R4.L; -R1.H = LSHIFT R1.H BY R4.L; -R2.H = LSHIFT R2.H BY R4.L; -R3.H = LSHIFT R3.H BY R4.L; -//rh4 = lshift (rh4 by rl4); -R5.H = LSHIFT R5.H BY R4.L; -R6.H = LSHIFT R6.H BY R4.L; -R7.H = LSHIFT R7.H BY R4.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00010000; -CHECKREG r3, 0x00010000; -//CHECKREG r4, 0x00020000; -CHECKREG r5, 0x00020000; -CHECKREG r6, 0x00030000; -CHECKREG r7, 0x00030000; - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -imm32 r2, 0x20020000; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -R5.L = -1; -imm32 r6, 0x60060000; -imm32 r7, 0x70070000; -R0.H = LSHIFT R0.H BY R5.L; -R1.H = LSHIFT R1.H BY R5.L; -R2.H = LSHIFT R2.H BY R5.L; -R3.H = LSHIFT R3.H BY R5.L; -R4.H = LSHIFT R4.H BY R5.L; -//rh5 = lshift (rh5 by rl5); -R6.H = LSHIFT R6.H BY R5.L; -R7.H = LSHIFT R7.H BY R5.L; -CHECKREG r0, 0x08000000; -CHECKREG r1, 0x08000000; -CHECKREG r2, 0x10010000; -CHECKREG r3, 0x18010000; -CHECKREG r4, 0x20020000; -//CHECKREG r5, 0x28020000; -CHECKREG r6, 0x30030000; -CHECKREG r7, 0x38030000; - - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -imm32 r2, 0x20020000; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -R6.L = -15; -imm32 r7, 0x70070000; -R0.L = LSHIFT R0.H BY R6.L; -R1.L = LSHIFT R1.H BY R6.L; -R2.L = LSHIFT R2.H BY R6.L; -R3.L = LSHIFT R3.H BY R6.L; -R4.L = LSHIFT R4.H BY R6.L; -R5.L = LSHIFT R5.H BY R6.L; -//rl6 = lshift (rh6 by rl6); -R7.L = LSHIFT R7.H BY R6.L; -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -CHECKREG r2, 0x20020000; -CHECKREG r3, 0x30030000; -CHECKREG r4, 0x40040000; -CHECKREG r5, 0x50050000; -//CHECKREG r6, 0x60060000; -CHECKREG r7, 0x70070000; - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -imm32 r2, 0x20020000; -imm32 r2, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -imm32 r6, 0x60060000; -R7.L = -16; -R0.H = LSHIFT R0.H BY R7.L; -R1.H = LSHIFT R1.H BY R7.L; -R2.H = LSHIFT R2.H BY R7.L; -R3.H = LSHIFT R3.H BY R7.L; -R4.H = LSHIFT R4.H BY R7.L; -R5.H = LSHIFT R5.H BY R7.L; -R6.H = LSHIFT R6.H BY R7.L; -//rh7 = lshift (rh7 by rl7); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -//CHECKREG r7, -16; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lhh.s b/sim/testsuite/sim/bfin/c_dsp32shift_lhh.s deleted file mode 100644 index 4722987..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_lhh.s +++ /dev/null @@ -1,311 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_lhh/c_dsp32shift_lhh.dsp -// Spec Reference: dsp32shift lshift/lshift -# mach: bfin - -.include "testutils.inc" - start - - - -// lshift/lshift : = (half reg) -// d_reg = lshift/lshift (d BY d_lo) -// Rx by RLx -imm32 r0, 0x01230000; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R1 = LSHIFT R0 BY R0.L (V); -R2 = LSHIFT R1 BY R0.L (V); -R3 = LSHIFT R2 BY R0.L (V); -R4 = LSHIFT R3 BY R0.L (V); -R5 = LSHIFT R4 BY R0.L (V); -R6 = LSHIFT R5 BY R0.L (V); -R7 = LSHIFT R6 BY R0.L (V); -R0 = LSHIFT R7 BY R0.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R1.L = 5; -R2 = LSHIFT R0 BY R1.L (V); -R3 = LSHIFT R1 BY R1.L (V); -R4 = LSHIFT R2 BY R1.L (V); -R5 = LSHIFT R3 BY R1.L (V); -R6 = LSHIFT R4 BY R1.L (V); -R7 = LSHIFT R5 BY R1.L (V); -R0 = LSHIFT R6 BY R1.L (V); -R1 = LSHIFT R7 BY R1.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R2 = 15; -R3 = LSHIFT R0 BY R2.L (V); -R4 = LSHIFT R1 BY R2.L (V); -R5 = LSHIFT R2 BY R2.L (V); -R6 = LSHIFT R3 BY R2.L (V); -R7 = LSHIFT R4 BY R2.L (V); -R0 = LSHIFT R5 BY R2.L (V); -R1 = LSHIFT R6 BY R2.L (V); -R2 = LSHIFT R7 BY R2.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R3.L = 16; -R4 = LSHIFT R0 BY R3.L (V); -R5 = LSHIFT R1 BY R3.L (V); -R6 = LSHIFT R2 BY R3.L (V); -R7 = LSHIFT R3 BY R3.L (V); -R0 = LSHIFT R4 BY R3.L (V); -R1 = LSHIFT R5 BY R3.L (V); -R2 = LSHIFT R6 BY R3.L (V); -R3 = LSHIFT R7 BY R3.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R4.L = -1; -R0 = LSHIFT R0 BY R4.L (V); -R1 = LSHIFT R1 BY R4.L (V); -R2 = LSHIFT R2 BY R4.L (V); -R3 = LSHIFT R3 BY R4.L (V); -R4 = LSHIFT R4 BY R4.L (V); -R5 = LSHIFT R5 BY R4.L (V); -R6 = LSHIFT R6 BY R4.L (V); -R7 = LSHIFT R7 BY R4.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R5.L = -6; -R6 = LSHIFT R0 BY R5.L (V); -R7 = LSHIFT R1 BY R5.L (V); -R0 = LSHIFT R2 BY R5.L (V); -R1 = LSHIFT R3 BY R5.L (V); -R2 = LSHIFT R4 BY R5.L (V); -R3 = LSHIFT R5 BY R5.L (V); -R4 = LSHIFT R6 BY R5.L (V); -R5 = LSHIFT R7 BY R5.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R6.L = -15; -R7 = LSHIFT R0 BY R6.L (V); -R0 = LSHIFT R1 BY R6.L (V); -R1 = LSHIFT R2 BY R6.L (V); -R2 = LSHIFT R3 BY R6.L (V); -R3 = LSHIFT R4 BY R6.L (V); -R4 = LSHIFT R5 BY R6.L (V); -R5 = LSHIFT R6 BY R6.L (V); -R6 = LSHIFT R7 BY R6.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R7.L = -16; -R0 = LSHIFT R0 BY R7.L (V); -R1 = LSHIFT R1 BY R7.L (V); -R2 = LSHIFT R2 BY R7.L (V); -R3 = LSHIFT R3 BY R7.L (V); -R4 = LSHIFT R4 BY R7.L (V); -R5 = LSHIFT R5 BY R7.L (V); -R6 = LSHIFT R6 BY R7.L (V); -R7 = LSHIFT R7 BY R7.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R0.L = 4; -//r0 = lshift/lshift (r0 by rl0); -R1 = LSHIFT R1 BY R0.L (V); -R2 = LSHIFT R2 BY R0.L (V); -R3 = LSHIFT R3 BY R0.L (V); -R4 = LSHIFT R4 BY R0.L (V); -R5 = LSHIFT R5 BY R0.L (V); -R6 = LSHIFT R6 BY R0.L (V); -R7 = LSHIFT R7 BY R0.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R1.L = 6; -R0 = LSHIFT R0 BY R1.L (V); -//r1 = lshift/lshift (r1 by rl1); -R2 = LSHIFT R2 BY R1.L (V); -R3 = LSHIFT R3 BY R1.L (V); -R4 = LSHIFT R4 BY R1.L (V); -R5 = LSHIFT R5 BY R1.L (V); -R6 = LSHIFT R6 BY R1.L (V); -R7 = LSHIFT R7 BY R1.L (V); - - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R2.L = 15; -R0 = LSHIFT R0 BY R2.L (V); -R1 = LSHIFT R1 BY R2.L (V); -//r2 = lshift/lshift (r2 by rl2); -R3 = LSHIFT R3 BY R2.L (V); -R4 = LSHIFT R4 BY R2.L (V); -R5 = LSHIFT R5 BY R2.L (V); -R6 = LSHIFT R6 BY R2.L (V); -R7 = LSHIFT R7 BY R2.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R3.L = 16; -R0 = LSHIFT R0 BY R3.L (V); -R1 = LSHIFT R1 BY R3.L (V); -R2 = LSHIFT R2 BY R3.L (V); -//r3 = lshift/lshift (r3 by rl3); -R4 = LSHIFT R4 BY R3.L (V); -R5 = LSHIFT R5 BY R3.L (V); -R6 = LSHIFT R6 BY R3.L (V); -R7 = LSHIFT R7 BY R3.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R4.L = -9; -R0 = LSHIFT R0 BY R4.L (V); -R1 = LSHIFT R1 BY R4.L (V); -R2 = LSHIFT R2 BY R4.L (V); -R3 = LSHIFT R3 BY R4.L (V); -//r4 = lshift/lshift (r4 by rl4); -R5 = LSHIFT R5 BY R4.L (V); -R6 = LSHIFT R6 BY R4.L (V); -R7 = LSHIFT R7 BY R4.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R5.L = -14; -R0 = LSHIFT R0 BY R5.L (V); -R1 = LSHIFT R1 BY R5.L (V); -R2 = LSHIFT R2 BY R5.L (V); -R3 = LSHIFT R3 BY R5.L (V); -R4 = LSHIFT R4 BY R5.L (V); -//r5 = lshift/lshift (r5 by rl5); -R6 = LSHIFT R6 BY R5.L (V); -R7 = LSHIFT R7 BY R5.L (V); - - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R6.L = -15; -R0 = LSHIFT R0 BY R6.L (V); -R1 = LSHIFT R1 BY R6.L (V); -R2 = LSHIFT R2 BY R6.L (V); -R3 = LSHIFT R3 BY R6.L (V); -R4 = LSHIFT R4 BY R6.L (V); -R5 = LSHIFT R5 BY R6.L (V); -//r6 = lshift/lshift (r6 by rl6); -R7 = LSHIFT R7 BY R6.L (V); - -imm32 r0, 0x01230002; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R7.L = -16; -R0 = LSHIFT R0 BY R7.L (V); -R1 = LSHIFT R1 BY R7.L (V); -R2 = LSHIFT R2 BY R7.L (V); -R3 = LSHIFT R3 BY R7.L (V); -R4 = LSHIFT R4 BY R7.L (V); -R5 = LSHIFT R5 BY R7.L (V); -R6 = LSHIFT R6 BY R7.L (V); -R7 = LSHIFT R7 BY R7.L (V); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lmix.s b/sim/testsuite/sim/bfin/c_dsp32shift_lmix.s deleted file mode 100644 index 2a3c360..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_lmix.s +++ /dev/null @@ -1,136 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_lmix/c_dsp32shift_lmix.dsp -// Spec Reference: dsp32shift lshift: mix -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -// lshift : positive data, count (+)=left (half reg) -imm32 r0, 0x00010001; -imm32 r1, 1; -imm32 r2, 0x00020002; -imm32 r3, 2; -R4.H = LSHIFT R0.H BY R1.L; -R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x00020002 */ -R5.H = LSHIFT R2.H BY R3.L; -R5.L = LSHIFT R2.L BY R3.L; /* r5 = 0x00080008 */ -R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */ -R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */ -CHECKREG r4, 0x00020002; -CHECKREG r5, 0x00080008; -CHECKREG r6, 0x00020002; -CHECKREG r7, 0x00080008; - -// lshift : (full reg) -imm32 r1, 3; -imm32 r3, 4; -R6 = LSHIFT R0 BY R1.L; /* r6 = 0x00080010 */ -R7 = LSHIFT R2 BY R3.L; -CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ -CHECKREG r7, 0x00200020; - -A0 = 0; -A0.L = R0.L; -A0.H = R0.H; -A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00080008 */ -R5 = A0.w; /* r5 = 0x00080008 */ -CHECKREG r5, 0x00080008; - -imm32 r4, 0x30000003; -imm32 r1, 1; -R6 = LSHIFT R4 BY R1.L; /* r5 = 0x60000006 */ -imm32 r1, 2; -R7 = LSHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */ -CHECKREG r6, 0x60000006; -CHECKREG r7, 0xc000000c; - - -// lshift : count (-)=right (half reg) -imm32 r0, 0x10001000; -imm32 r1, -1; -imm32 r2, 0x10001000; -imm32 r3, -2; -R4.H = LSHIFT R0.H BY R1.L; -R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x08000800 */ -R5.H = LSHIFT R2.H BY R3.L; -R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x04000400 */ -R6 = LSHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */ -R7 = LSHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */ -CHECKREG r4, 0x08000800; -CHECKREG r5, 0x04000400; -CHECKREG r6, 0x08000800; -CHECKREG r7, 0x04000400; - -// lshift : (full reg) -imm32 r1, -3; -imm32 r3, -4; -R6 = LSHIFT R0 BY R1.L; /* r6 = 0x02000200 */ -R7 = LSHIFT R2 BY R3.L; /* r7 = 0x01000100 */ -CHECKREG r6, 0x02000200; -CHECKREG r7, 0x01000100; - -// NEGATIVE -// lshift : NEGATIVE data, count (+)=left (half reg) -imm32 r0, 0xc00f800f; -imm32 r1, 1; -imm32 r2, 0xe00fe00f; -imm32 r3, 2; -R4.H = LSHIFT R0.H BY R1.L; -R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x801e001e */ -R5.H = LSHIFT R2.H BY R3.L; -R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x803c803c */ -CHECKREG r4, 0x801e001e; -CHECKREG r5, 0x803c803c; - -imm32 r0, 0xc80fe00f; -imm32 r2, 0xe40fe00f; -imm32 r1, 4; -imm32 r3, 5; -R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */ -R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */ -CHECKREG r6, 0x80fe00f0; -CHECKREG r7, 0x81fc01e0; - -imm32 r0, 0xf80fe00f; -imm32 r2, 0xfc0fe00f; -R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */ -R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */ -CHECKREG r6, 0x80fe00f0; -CHECKREG r7, 0x81fc01e0; - - - -// lshift : NEGATIVE data, count (-)=right (half reg) Working ok -imm32 r0, 0x80f080f0; -imm32 r1, -1; -imm32 r2, 0x80f080f0; -imm32 r3, -2; -R4.H = LSHIFT R0.H BY R1.L; -R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x40784078 */ -R5.H = LSHIFT R2.H BY R3.L; -R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x203c203c */ -CHECKREG r4, 0x40784078; -CHECKREG r5, 0x203c203c; -R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x40784078 */ -R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x203c203c */ -CHECKREG r6, 0x40784078; -CHECKREG r7, 0x203c203c; - -// lshift : (full reg) -imm32 r1, -3; -imm32 r3, -4; -R6 = LSHIFT R0 BY R1.L; /* r6 = 0x101e101e */ -R7 = LSHIFT R2 BY R3.L; /* r7 = 0x080f080f */ -CHECKREG r6, 0x101e101e; -CHECKREG r7, 0x080f080f; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ones.s b/sim/testsuite/sim/bfin/c_dsp32shift_ones.s deleted file mode 100644 index 4097777..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_ones.s +++ /dev/null @@ -1,214 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_ones/c_dsp32shift_ones.dsp -// Spec Reference: dsp32shift ones -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x88880000; -imm32 r1, 0x34560001; -imm32 r2, 0x08000002; -imm32 r3, 0x08000003; -imm32 r4, 0x08000004; -imm32 r5, 0x08000005; -imm32 r6, 0x08000006; -imm32 r7, 0x08000007; -R7.L = ONES R0; -R1.L = ONES R0; -R2.L = ONES R0; -R3.L = ONES R0; -R4.L = ONES R0; -R5.L = ONES R0; -R6.L = ONES R0; -R0.L = ONES R0; -CHECKREG r1, 0x34560004; -CHECKREG r0, 0x88880004; -CHECKREG r2, 0x08000004; -CHECKREG r3, 0x08000004; -CHECKREG r4, 0x08000004; -CHECKREG r5, 0x08000004; -CHECKREG r6, 0x08000004; -CHECKREG r7, 0x08000004; - -imm32 r0, 0x9999d001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000d002; -imm32 r3, 0x0000d003; -imm32 r4, 0x0000d004; -imm32 r5, 0x0000d005; -imm32 r6, 0x0000d006; -imm32 r7, 0x0000d007; -R0.L = ONES R1; -R7.L = ONES R1; -R2.L = ONES R1; -R3.L = ONES R1; -R4.L = ONES R1; -R5.L = ONES R1; -R6.L = ONES R1; -R1.L = ONES R1; -CHECKREG r0, 0x99990001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000001; - - -imm32 r0, 0xaaaae001; -imm32 r1, 0x0000e001; -imm32 r2, 0xaaaa000f; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000e004; -imm32 r5, 0x0000e005; -imm32 r6, 0x0000e006; -imm32 r7, 0x0000e007; -R0.L = ONES R2; -R1.L = ONES R2; -R7.L = ONES R2; -R3.L = ONES R2; -R4.L = ONES R2; -R5.L = ONES R2; -R6.L = ONES R2; -R2.L = ONES R2; -CHECKREG r0, 0xAAAA000C; -CHECKREG r1, 0x0000000C; -CHECKREG r2, 0xAAAA000C; -CHECKREG r3, 0x0000000C; -CHECKREG r4, 0x0000000C; -CHECKREG r5, 0x0000000C; -CHECKREG r6, 0x0000000C; -CHECKREG r7, 0x0000000C; - -imm32 r0, 0x0000f001; -imm32 r1, 0x0000f001; -imm32 r2, 0x0000f002; -imm32 r3, 0xbbbb0010; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000f005; -imm32 r6, 0x0000f006; -imm32 r7, 0x0000f007; -R0.L = ONES R3; -R1.L = ONES R3; -R2.L = ONES R3; -R7.L = ONES R3; -R4.L = ONES R3; -R5.L = ONES R3; -R6.L = ONES R3; -R3.L = ONES R3; -CHECKREG r0, 0x0000000D; -CHECKREG r1, 0x0000000D; -CHECKREG r2, 0x0000000D; -CHECKREG r3, 0xBBBB000D; -CHECKREG r4, 0x0000000D; -CHECKREG r5, 0x0000000D; -CHECKREG r6, 0x0000000D; -CHECKREG r7, 0x0000000D; - -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0xcccc0000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = ONES R4; -R1.L = ONES R4; -R2.L = ONES R4; -R3.L = ONES R4; -R7.L = ONES R4; -R5.L = ONES R4; -R6.L = ONES R4; -R4.L = ONES R4; -CHECKREG r0, 0x00000008; -CHECKREG r1, 0x00010008; -CHECKREG r2, 0x00020008; -CHECKREG r3, 0x00030008; -CHECKREG r4, 0xCCCC0008; -CHECKREG r5, 0x00050008; -CHECKREG r6, 0x00060008; -CHECKREG r7, 0x00070008; - -imm32 r0, 0xa0010000; -imm32 r1, 0xa0010001; -imm32 r2, 0xa0020000; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xaddd0000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R0.L = ONES R5; -R1.L = ONES R5; -R2.L = ONES R5; -R3.L = ONES R5; -R4.L = ONES R5; -R7.L = ONES R5; -R6.L = ONES R5; -R5.L = ONES R5; -CHECKREG r0, 0xA001000B; -CHECKREG r1, 0xA001000B; -CHECKREG r2, 0xA002000B; -CHECKREG r3, 0xA003000B; -CHECKREG r4, 0xA004000B; -CHECKREG r5, 0xADDD000B; -CHECKREG r6, 0xA006000B; -CHECKREG r7, 0xA007000B; - - -imm32 r0, 0xb0010000; -imm32 r1, 0xb0010000; -imm32 r2, 0xb002000f; -imm32 r3, 0xb0030000; -imm32 r4, 0xb0040000; -imm32 r5, 0xb0050000; -imm32 r6, 0xeeee0000; -imm32 r7, 0xb0070000; -R0.L = ONES R6; -R1.L = ONES R6; -R2.L = ONES R6; -R3.L = ONES R6; -R4.L = ONES R6; -R5.L = ONES R6; -R7.L = ONES R6; -R6.L = ONES R6; -CHECKREG r0, 0xB001000C; -CHECKREG r1, 0xB001000C; -CHECKREG r2, 0xB002000C; -CHECKREG r3, 0xB003000C; -CHECKREG r4, 0xB004000C; -CHECKREG r5, 0xB005000C; -CHECKREG r6, 0xEEEE000C; -CHECKREG r7, 0xB007000C; - -imm32 r0, 0xd0010001; -imm32 r1, 0xd0010002; -imm32 r2, 0xd0020003; -imm32 r3, 0xd0030014; -imm32 r4, 0xd0040005; -imm32 r5, 0xd0050000; -imm32 r6, 0xd0060007; -imm32 r7, 0xffff0000; -R0.L = ONES R7; -R1.L = ONES R7; -R2.L = ONES R7; -R3.L = ONES R7; -R4.L = ONES R7; -R5.L = ONES R7; -R6.L = ONES R7; -R7.L = ONES R7; - -CHECKREG r0, 0xD0010010; -CHECKREG r1, 0xD0010010; -CHECKREG r2, 0xD0020010; -CHECKREG r3, 0xD0030010; -CHECKREG r4, 0xD0040010; -CHECKREG r5, 0xD0050010; -CHECKREG r6, 0xD0060010; -CHECKREG r7, 0xFFFF0010; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_pack.s b/sim/testsuite/sim/bfin/c_dsp32shift_pack.s deleted file mode 100644 index 5647309..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_pack.s +++ /dev/null @@ -1,411 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_pack/c_dsp32shift_pack.dsp -// Spec Reference: dsp32shift pack -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x01230000; -imm32 r1, 0x02345678; -imm32 r2, 0x03456789; -imm32 r3, 0x0456789a; -imm32 r4, 0x056789ab; -imm32 r5, 0x06789abc; -imm32 r6, 0x0789abcd; -imm32 r7, 0x089abcde; -R1 = PACK( R0.L , R0.L ); -R2 = PACK( R1.L , R0.H ); -R3 = PACK( R2.H , R0.L ); -R4 = PACK( R3.H , R0.H ); -R5 = PACK( R4.L , R0.L ); -R6 = PACK( R5.L , R0.H ); -R7 = PACK( R6.H , R0.L ); -R0 = PACK( R7.H , R0.H ); -CHECKREG r1, 0x00000000; -CHECKREG r0, 0x00000123; -CHECKREG r2, 0x00000123; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000123; -CHECKREG r5, 0x01230000; -CHECKREG r6, 0x00000123; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x11230001; -imm32 r1, 0x12345678; -imm32 r2, 0x1bcdef12; -imm32 r3, 0x1456789a; -imm32 r4, 0x1cdef012; -imm32 r5, 0x1456789a; -imm32 r6, 0x1789abcd; -imm32 r7, 0x189abcde; -R2 = PACK( R0.L , R1.L ); -R3 = PACK( R1.L , R1.H ); -R4 = PACK( R2.H , R1.L ); -R5 = PACK( R3.H , R1.H ); -R6 = PACK( R4.L , R1.L ); -R7 = PACK( R5.L , R1.H ); -R0 = PACK( R6.H , R1.L ); -R1 = PACK( R7.H , R1.H ); -CHECKREG r0, 0x56785678; -CHECKREG r1, 0x12341234; -CHECKREG r2, 0x00015678; -CHECKREG r3, 0x56781234; -CHECKREG r4, 0x00015678; -CHECKREG r5, 0x56781234; -CHECKREG r6, 0x56785678; -CHECKREG r7, 0x12341234; - -imm32 r0, 0x20230002; -imm32 r1, 0x21345678; -imm32 r2, 0x22456789; -imm32 r3, 0x2356789a; -imm32 r4, 0x246789ab; -imm32 r5, 0x25789abc; -imm32 r6, 0x2689abcd; -imm32 r7, 0x279abcde; -R3 = PACK( R0.L , R2.L ); -R4 = PACK( R1.L , R2.H ); -R5 = PACK( R2.H , R2.L ); -R6 = PACK( R3.H , R2.H ); -R7 = PACK( R4.L , R2.L ); -R0 = PACK( R5.L , R2.H ); -R1 = PACK( R6.H , R2.L ); -R2 = PACK( R7.H , R2.H ); -CHECKREG r0, 0x67892245; -CHECKREG r1, 0x00026789; -CHECKREG r2, 0x22452245; -CHECKREG r3, 0x00026789; -CHECKREG r4, 0x56782245; -CHECKREG r5, 0x22456789; -CHECKREG r6, 0x00022245; -CHECKREG r7, 0x22456789; - -imm32 r0, 0x31230003; -imm32 r1, 0x31345678; -imm32 r2, 0x31456789; -imm32 r3, 0x3156789a; -imm32 r4, 0x316789ab; -imm32 r5, 0x31789abc; -imm32 r6, 0x3189abcd; -imm32 r7, 0x311abcde; -R4 = PACK( R0.L , R3.L ); -R5 = PACK( R1.L , R3.H ); -R6 = PACK( R2.H , R3.L ); -R7 = PACK( R3.H , R3.H ); -R0 = PACK( R4.L , R3.L ); -R1 = PACK( R5.L , R3.H ); -R2 = PACK( R6.H , R3.L ); -R3 = PACK( R7.H , R3.H ); -CHECKREG r0, 0x789A789A; -CHECKREG r1, 0x31563156; -CHECKREG r2, 0x3145789A; -CHECKREG r3, 0x31563156; -CHECKREG r4, 0x0003789A; -CHECKREG r5, 0x56783156; -CHECKREG r6, 0x3145789A; -CHECKREG r7, 0x31563156; - -imm32 r0, 0x41230004; -imm32 r1, 0x42345678; -imm32 r2, 0x43456789; -imm32 r3, 0x4456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x46789abc; -imm32 r6, 0x4789abcd; -imm32 r7, 0x489abcde; -R0 = PACK( R0.L , R4.L ); -R1 = PACK( R1.L , R4.H ); -R2 = PACK( R2.H , R4.L ); -R3 = PACK( R3.H , R4.H ); -R4 = PACK( R4.L , R4.L ); -R5 = PACK( R5.L , R4.H ); -R6 = PACK( R6.H , R4.L ); -R7 = PACK( R7.H , R4.H ); -CHECKREG r0, 0x000489AB; -CHECKREG r1, 0x56784567; -CHECKREG r2, 0x434589AB; -CHECKREG r3, 0x44564567; -CHECKREG r4, 0x89AB89AB; -CHECKREG r5, 0x9ABC89AB; -CHECKREG r6, 0x478989AB; -CHECKREG r7, 0x489A89AB; - -imm32 r0, 0x51230005; -imm32 r1, 0x52345678; -imm32 r2, 0x53456789; -imm32 r3, 0x5456789a; -imm32 r4, 0x556789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x5789abcd; -imm32 r7, 0x589abcde; -R6 = PACK( R0.L , R5.L ); -R7 = PACK( R1.L , R5.H ); -R0 = PACK( R2.H , R5.L ); -R1 = PACK( R3.H , R5.H ); -R2 = PACK( R4.L , R5.L ); -R3 = PACK( R5.L , R5.H ); -R4 = PACK( R6.H , R5.L ); -R5 = PACK( R7.H , R5.H ); -CHECKREG r0, 0x53459ABC; -CHECKREG r1, 0x54565678; -CHECKREG r2, 0x89AB9ABC; -CHECKREG r3, 0x9ABC5678; -CHECKREG r4, 0x00059ABC; -CHECKREG r5, 0x56785678; -CHECKREG r6, 0x00059ABC; -CHECKREG r7, 0x56785678; - -imm32 r0, 0x61230006; -imm32 r1, 0x62345678; -imm32 r2, 0x63456789; -imm32 r3, 0x6456789a; -imm32 r4, 0x656789ab; -imm32 r5, 0x66789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x689abcde; -R7 = PACK( R0.L , R6.L ); -R0 = PACK( R1.L , R6.H ); -R1 = PACK( R2.H , R6.L ); -R2 = PACK( R3.H , R6.H ); -R3 = PACK( R4.L , R6.L ); -R4 = PACK( R5.L , R6.H ); -R5 = PACK( R6.H , R6.L ); -R6 = PACK( R7.H , R6.H ); -CHECKREG r0, 0x56786789; -CHECKREG r1, 0x6345ABCD; -CHECKREG r2, 0x64566789; -CHECKREG r3, 0x89ABABCD; -CHECKREG r4, 0x9ABC6789; -CHECKREG r5, 0x6789ABCD; -CHECKREG r6, 0x00066789; -CHECKREG r7, 0x0006ABCD; - -imm32 r0, 0x71230007; -imm32 r1, 0x72345678; -imm32 r2, 0x73456789; -imm32 r3, 0x7456789a; -imm32 r4, 0x756789ab; -imm32 r5, 0x76789abc; -imm32 r6, 0x7789abcd; -imm32 r7, 0x789abcde; -R0 = PACK( R0.L , R7.L ); -R1 = PACK( R1.L , R7.H ); -R2 = PACK( R2.H , R7.L ); -R3 = PACK( R3.H , R7.H ); -R4 = PACK( R4.L , R7.L ); -R5 = PACK( R5.L , R7.H ); -R6 = PACK( R6.H , R7.L ); -R7 = PACK( R7.H , R7.H ); -CHECKREG r0, 0x0007BCDE; -CHECKREG r1, 0x5678789A; -CHECKREG r2, 0x7345BCDE; -CHECKREG r3, 0x7456789A; -CHECKREG r4, 0x89ABBCDE; -CHECKREG r5, 0x9ABC789A; -CHECKREG r6, 0x7789BCDE; -CHECKREG r7, 0x789A789A; - -imm32 r0, 0x81230008; -imm32 r1, 0x82345678; -imm32 r2, 0x83456789; -imm32 r3, 0x8456789a; -imm32 r4, 0x856789ab; -imm32 r5, 0x86789abc; -imm32 r6, 0x8789abcd; -imm32 r7, 0x889abcde; -R0 = PACK( R0.L , R0.L ); -R1 = PACK( R1.L , R0.H ); -R2 = PACK( R2.H , R0.L ); -R3 = PACK( R3.H , R0.H ); -R4 = PACK( R4.L , R0.L ); -R5 = PACK( R5.L , R0.H ); -R6 = PACK( R6.H , R0.L ); -R7 = PACK( R7.H , R0.H ); -CHECKREG r0, 0x00080008; -CHECKREG r1, 0x56780008; -CHECKREG r2, 0x83450008; -CHECKREG r3, 0x84560008; -CHECKREG r4, 0x89AB0008; -CHECKREG r5, 0x9ABC0008; -CHECKREG r6, 0x87890008; -CHECKREG r7, 0x889A0008; - -imm32 r0, 0x91230009; -imm32 r1, 0x92345678; -imm32 r2, 0x93456789; -imm32 r3, 0x9456789a; -imm32 r4, 0x956789ab; -imm32 r5, 0x96789abc; -imm32 r6, 0x9789abcd; -imm32 r7, 0x989abcde; -R0 = PACK( R0.L , R1.L ); -R1 = PACK( R1.L , R1.H ); -R2 = PACK( R2.H , R1.L ); -R3 = PACK( R3.H , R1.H ); -R4 = PACK( R4.L , R1.L ); -R5 = PACK( R5.L , R1.H ); -R6 = PACK( R6.H , R1.L ); -R7 = PACK( R7.H , R1.H ); -CHECKREG r0, 0x00095678; -CHECKREG r1, 0x56789234; -CHECKREG r2, 0x93459234; -CHECKREG r3, 0x94565678; -CHECKREG r4, 0x89AB9234; -CHECKREG r5, 0x9ABC5678; -CHECKREG r6, 0x97899234; -CHECKREG r7, 0x989A5678; - - -imm32 r0, 0xa123000a; -imm32 r1, 0xa2345678; -imm32 r2, 0xa3456789; -imm32 r3, 0xa456789a; -imm32 r4, 0xa56789ab; -imm32 r5, 0xa6789abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xa89abcde; -R0 = PACK( R0.L , R2.L ); -R1 = PACK( R1.L , R2.H ); -R2 = PACK( R2.H , R2.L ); -R3 = PACK( R3.H , R2.H ); -R4 = PACK( R4.L , R2.L ); -R5 = PACK( R5.L , R2.H ); -R6 = PACK( R6.H , R2.L ); -R7 = PACK( R7.H , R2.H ); -CHECKREG r0, 0x000A6789; -CHECKREG r1, 0x5678A345; -CHECKREG r2, 0xA3456789; -CHECKREG r3, 0xA456A345; -CHECKREG r4, 0x89AB6789; -CHECKREG r5, 0x9ABCA345; -CHECKREG r6, 0xA7896789; -CHECKREG r7, 0xA89AA345; - -imm32 r0, 0xb123000b; -imm32 r1, 0xb2345678; -imm32 r2, 0xb3456789; -imm32 r3, 0xb456789a; -imm32 r4, 0xb56789ab; -imm32 r5, 0xb6789abc; -imm32 r6, 0xb789abcd; -imm32 r7, 0xb89abcde; -R0 = PACK( R0.L , R3.L ); -R1 = PACK( R1.L , R3.H ); -R2 = PACK( R2.H , R3.L ); -R3 = PACK( R3.H , R3.H ); -R4 = PACK( R4.L , R3.L ); -R5 = PACK( R5.L , R3.H ); -R6 = PACK( R6.H , R3.L ); -R7 = PACK( R7.H , R3.H ); -CHECKREG r0, 0x000B789A; -CHECKREG r1, 0x5678B456; -CHECKREG r2, 0xB345789A; -CHECKREG r3, 0xB456B456; -CHECKREG r4, 0x89ABB456; -CHECKREG r5, 0x9ABCB456; -CHECKREG r6, 0xB789B456; -CHECKREG r7, 0xB89AB456; - -imm32 r0, 0xc123000c; -imm32 r1, 0xc2345678; -imm32 r2, 0xc3456789; -imm32 r3, 0xc456789a; -imm32 r4, 0xc56789ab; -imm32 r5, 0xc6789abc; -imm32 r6, 0xc789abcd; -imm32 r7, 0xc89abcde; -R0 = PACK( R0.L , R4.L ); -R1 = PACK( R1.L , R4.H ); -R2 = PACK( R2.H , R4.L ); -R3 = PACK( R3.H , R4.H ); -R4 = PACK( R4.L , R4.L ); -R5 = PACK( R5.L , R4.H ); -R6 = PACK( R6.H , R4.L ); -R7 = PACK( R7.H , R4.H ); -CHECKREG r0, 0x000C89AB; -CHECKREG r1, 0x5678C567; -CHECKREG r2, 0xC34589AB; -CHECKREG r3, 0xC456C567; -CHECKREG r4, 0x89AB89AB; -CHECKREG r5, 0x9ABC89AB; -CHECKREG r6, 0xC78989AB; -CHECKREG r7, 0xC89A89AB; - -imm32 r0, 0xd123000d; -imm32 r1, 0xd2345678; -imm32 r2, 0xd3456789; -imm32 r3, 0xd456789a; -imm32 r4, 0xd56789ab; -imm32 r5, 0xd6789abc; -imm32 r6, 0xd789abcd; -imm32 r7, 0xd89abcde; -R0 = PACK( R0.L , R5.L ); -R1 = PACK( R1.L , R5.H ); -R2 = PACK( R2.H , R5.L ); -R3 = PACK( R3.H , R5.H ); -R4 = PACK( R4.L , R5.L ); -R5 = PACK( R5.L , R5.H ); -R6 = PACK( R6.H , R5.L ); -R7 = PACK( R7.H , R5.H ); -CHECKREG r0, 0x000D9ABC; -CHECKREG r1, 0x5678D678; -CHECKREG r2, 0xD3459ABC; -CHECKREG r3, 0xD456D678; -CHECKREG r4, 0x89AB9ABC; -CHECKREG r5, 0x9ABCD678; -CHECKREG r6, 0xD789D678; -CHECKREG r7, 0xD89A9ABC; - - -imm32 r0, 0xe123000e; -imm32 r1, 0xe2345678; -imm32 r2, 0xe3456789; -imm32 r3, 0xe456789a; -imm32 r4, 0xe56789ab; -imm32 r5, 0xe6789abc; -imm32 r6, 0xe789abcd; -imm32 r7, 0xe89abcde; -R0 = PACK( R0.L , R6.L ); -R1 = PACK( R1.L , R6.H ); -R2 = PACK( R2.H , R6.L ); -R3 = PACK( R3.H , R6.H ); -R4 = PACK( R4.L , R6.L ); -R5 = PACK( R5.L , R6.H ); -R6 = PACK( R6.H , R6.L ); -R7 = PACK( R7.H , R6.H ); -CHECKREG r0, 0x000EABCD; -CHECKREG r1, 0x5678E789; -CHECKREG r2, 0xE345ABCD; -CHECKREG r3, 0xE456E789; -CHECKREG r4, 0x89ABABCD; -CHECKREG r5, 0x9ABCE789; -CHECKREG r6, 0xE789ABCD; -CHECKREG r7, 0xE89AE789; - -imm32 r0, 0xf123000f; -imm32 r1, 0xf2345678; -imm32 r2, 0xf3456789; -imm32 r3, 0xf456789a; -imm32 r4, 0xf56789ab; -imm32 r5, 0xf6789abc; -imm32 r6, 0xf789abcd; -imm32 r7, 0xf89abcde; -R0 = PACK( R0.L , R7.L ); -R1 = PACK( R1.L , R7.H ); -R2 = PACK( R2.H , R7.L ); -R3 = PACK( R3.H , R7.H ); -R4 = PACK( R4.L , R7.L ); -R5 = PACK( R5.L , R7.H ); -R6 = PACK( R6.H , R7.L ); -R7 = PACK( R7.H , R7.H ); -CHECKREG r0, 0x000FBCDE; -CHECKREG r1, 0x5678F89A; -CHECKREG r2, 0xF345BCDE; -CHECKREG r3, 0xF456F89A; -CHECKREG r4, 0x89ABBCDE; -CHECKREG r5, 0x9ABCF89A; -CHECKREG r6, 0xF789BCDE; -CHECKREG r7, 0xF89AF89A; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_rot.s b/sim/testsuite/sim/bfin/c_dsp32shift_rot.s deleted file mode 100644 index d4b2ff2..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_rot.s +++ /dev/null @@ -1,427 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot/c_dsp32shift_rot.dsp -// Spec Reference: dsp32shift rot -# mach: bfin - -.include "testutils.inc" - start - - - R0 = 0; - ASTAT = R0; - - imm32 r0, 0x01230001; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R1 = ROT R0 BY R0.L; - R2 = ROT R1 BY R0.L; - R3 = ROT R2 BY R0.L; - R4 = ROT R3 BY R0.L; - R5 = ROT R4 BY R0.L; - R6 = ROT R5 BY R0.L; - R7 = ROT R6 BY R0.L; - R0 = ROT R7 BY R0.L; - CHECKREG r1, 0x02460002; - CHECKREG r0, 0x23000100; - CHECKREG r2, 0x048C0004; - CHECKREG r3, 0x09180008; - CHECKREG r4, 0x12300010; - CHECKREG r5, 0x24600020; - CHECKREG r6, 0x48C00040; - CHECKREG r7, 0x91800080; - - imm32 r0, 0x01230001; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R1.L = 15; - R2 = ROT R0 BY R1.L; - R3 = ROT R1 BY R1.L; - R4 = ROT R2 BY R1.L; - R5 = ROT R3 BY R1.L; - R6 = ROT R4 BY R1.L; - R7 = ROT R5 BY R1.L; - R0 = ROT R6 BY R1.L; - R1 = ROT R7 BY R1.L; - CHECKREG r0, 0x2C04C400; - CHECKREG r1, 0x5C489000; - CHECKREG r2, 0x8000C048; - CHECKREG r3, 0x0007C48D; - CHECKREG r4, 0x60242000; - CHECKREG r5, 0xE2468001; - CHECKREG r6, 0x10005809; - CHECKREG r7, 0x4000B891; - - imm32 r0, 0x01230002; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R2 = 16; - R3 = ROT R0 BY R2.L; - R4 = ROT R1 BY R2.L; - R5 = ROT R2 BY R2.L; - R6 = ROT R3 BY R2.L; - R7 = ROT R4 BY R2.L; - R0 = ROT R5 BY R2.L; - R1 = ROT R6 BY R2.L; - R2 = ROT R7 BY R2.L; - CHECKREG r0, 0x00000008; - CHECKREG r1, 0x00010048; - CHECKREG r2, 0x2B3CC48D; - CHECKREG r3, 0x00020091; - CHECKREG r4, 0x5678891A; - CHECKREG r5, 0x00100000; - CHECKREG r6, 0x00910001; - CHECKREG r7, 0x891A2B3C; - - imm32 r0, 0x01230003; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R3.L = 31; - R4 = ROT R0 BY R3.L; - R5 = ROT R1 BY R3.L; - R6 = ROT R2 BY R3.L; - R7 = ROT R3 BY R3.L; - R0 = ROT R4 BY R3.L; - R1 = ROT R5 BY R3.L; - R2 = ROT R6 BY R3.L; - R3 = ROT R7 BY R3.L; - CHECKREG r0, 0x60123000; - CHECKREG r1, 0x11234567; - CHECKREG r2, 0x62345678; - CHECKREG r3, 0xE3456001; - CHECKREG r4, 0x8048C000; - CHECKREG r5, 0x448D159E; - CHECKREG r6, 0x88D159E2; - CHECKREG r7, 0x8D158007; - - imm32 r0, 0x01230004; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R4.L = -1; - R0 = ROT R0 BY R4.L; - R1 = ROT R1 BY R4.L; - R2 = ROT R2 BY R4.L; - R3 = ROT R3 BY R4.L; - R4 = ROT R4 BY R4.L; - R5 = ROT R5 BY R4.L; - R6 = ROT R6 BY R4.L; - R7 = ROT R7 BY R4.L; - CHECKREG r0, 0x80918002; - CHECKREG r1, 0x091A2B3C; - CHECKREG r2, 0x11A2B3C4; - CHECKREG r3, 0x9A2B3C4D; - CHECKREG r4, 0x22B3FFFF; - CHECKREG r5, 0xAB3C4D5E; - CHECKREG r6, 0x33C4D5E6; - CHECKREG r7, 0xBC4D5E6F; - - imm32 r0, 0x01230005; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R5.L = -15; - R6 = ROT R0 BY R5.L; - R7 = ROT R1 BY R5.L; - R0 = ROT R2 BY R5.L; - R1 = ROT R3 BY R5.L; - R2 = ROT R4 BY R5.L; - R3 = ROT R5 BY R5.L; - R4 = ROT R6 BY R5.L; - R5 = ROT R7 BY R5.L; - CHECKREG r0, 0x9E26468A; - CHECKREG r1, 0xE26A68AC; - CHECKREG r2, 0x26AE8ACF; - CHECKREG r3, 0xFFC4ACF1; - CHECKREG r4, 0x091A0028; - CHECKREG r5, 0x91A0B3C0; - CHECKREG r6, 0x00140246; - CHECKREG r7, 0x59E02468; - - imm32 r0, 0x01230006; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R6.L = -16; - R7 = ROT R0 BY R6.L; - R0 = ROT R1 BY R6.L; - R1 = ROT R2 BY R6.L; - R2 = ROT R3 BY R6.L; - R3 = ROT R4 BY R6.L; - R4 = ROT R5 BY R6.L; - R5 = ROT R6 BY R6.L; - R6 = ROT R7 BY R6.L; - CHECKREG r0, 0xACF01234; - CHECKREG r1, 0xCF122345; - CHECKREG r2, 0xF1343456; - CHECKREG r3, 0x13564567; - CHECKREG r4, 0x35795678; - CHECKREG r5, 0xFFE16789; - CHECKREG r6, 0x0247000C; - CHECKREG r7, 0x000C0123; - - imm32 r0, 0x01230007; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R7.L = -27; - R0 = ROT R0 BY R7.L; - R1 = ROT R1 BY R7.L; - R2 = ROT R2 BY R7.L; - R3 = ROT R3 BY R7.L; - R4 = ROT R4 BY R7.L; - R5 = ROT R5 BY R7.L; - R6 = ROT R6 BY R7.L; - R7 = ROT R7 BY R7.L; - CHECKREG r0, 0x48C001C0; - CHECKREG r1, 0x8D159E02; - CHECKREG r2, 0xD159E244; - CHECKREG r3, 0x159E2686; - CHECKREG r4, 0x59E26AE8; - CHECKREG r5, 0x9E26AF2A; - CHECKREG r6, 0xE26AF36C; - CHECKREG r7, 0x26BFF96F; - - imm32 r0, 0x01230008; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R0.L = 7; -//r0 = rot (r0 by rl0); - R1 = ROT R1 BY R0.L; - R2 = ROT R2 BY R0.L; - R3 = ROT R3 BY R0.L; - R4 = ROT R4 BY R0.L; - R5 = ROT R5 BY R0.L; - R6 = ROT R6 BY R0.L; - R7 = ROT R7 BY R0.L; - CHECKREG r0, 0x01230007; - CHECKREG r1, 0x1A2B3C04; - CHECKREG r2, 0xA2B3C4C8; - CHECKREG r3, 0x2B3C4D4D; - CHECKREG r4, 0xB3C4D591; - CHECKREG r5, 0x3C4D5E15; - CHECKREG r6, 0xC4D5E6D9; - CHECKREG r7, 0x4D5E6F5E; - - imm32 r0, 0x01230009; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R1.L = 16; - R0 = ROT R0 BY R1.L; -//r1 = rot (r1 by rl1); - R2 = ROT R2 BY R1.L; - R3 = ROT R3 BY R1.L; - R4 = ROT R4 BY R1.L; - R5 = ROT R5 BY R1.L; - R6 = ROT R6 BY R1.L; - R7 = ROT R7 BY R1.L; - CHECKREG r0, 0x00090091; - CHECKREG r1, 0x12340010; - CHECKREG r2, 0x678991A2; - CHECKREG r3, 0x789A9A2B; - CHECKREG r4, 0x89AB22B3; - CHECKREG r5, 0x9ABCAB3C; - CHECKREG r6, 0xABCD33C4; - CHECKREG r7, 0xBCDEBC4D; - - imm32 r0, 0x0123000a; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R2.L = 30; - R0 = ROT R0 BY R2.L; - R1 = ROT R1 BY R2.L; -//r2 = rot (r2 by rl2); - R3 = ROT R3 BY R2.L; - R4 = ROT R4 BY R2.L; - R5 = ROT R5 BY R2.L; - R6 = ROT R6 BY R2.L; - R7 = ROT R7 BY R2.L; - CHECKREG r0, 0x80246001; - CHECKREG r1, 0x02468ACF; - CHECKREG r2, 0x2345001E; - CHECKREG r3, 0x868ACF13; - CHECKREG r4, 0xC8ACF135; - CHECKREG r5, 0x0ACF1357; - CHECKREG r6, 0x6CF13579; - CHECKREG r7, 0xAF13579B; - - imm32 r0, 0x0123000b; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R3.L = 31; - R0 = ROT R0 BY R3.L; - R1 = ROT R1 BY R3.L; - R2 = ROT R2 BY R3.L; -//r3 = rot (r3 by rl3); - R4 = ROT R4 BY R3.L; - R5 = ROT R5 BY R3.L; - R6 = ROT R6 BY R3.L; - R7 = ROT R7 BY R3.L; - CHECKREG r0, 0xC048C002; - CHECKREG r1, 0x448D159E; - CHECKREG r2, 0x88D159E2; - CHECKREG r3, 0x3456001F; - CHECKREG r4, 0x9159E26A; - CHECKREG r5, 0x559E26AF; - CHECKREG r6, 0x99E26AF3; - CHECKREG r7, 0x1E26AF37; - - imm32 r0, 0x0123000c; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R4.L = -2; - R0 = ROT R0 BY R4.L; - R1 = ROT R1 BY R4.L; - R2 = ROT R2 BY R4.L; - R3 = ROT R3 BY R4.L; -//r4 = rot (r4 by rl4); - R5 = ROT R5 BY R4.L; - R6 = ROT R6 BY R4.L; - R7 = ROT R7 BY R4.L; - CHECKREG r0, 0x4048C003; - CHECKREG r1, 0x048D159E; - CHECKREG r2, 0x88D159E2; - CHECKREG r3, 0x0D159E26; - CHECKREG r4, 0x4567FFFE; - CHECKREG r5, 0x559E26AF; - CHECKREG r6, 0x99E26AF3; - CHECKREG r7, 0x1E26AF37; - - imm32 r0, 0x0123000d; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R5.L = -17; - R0 = ROT R0 BY R5.L; - R1 = ROT R1 BY R5.L; - R2 = ROT R2 BY R5.L; - R3 = ROT R3 BY R5.L; - R4 = ROT R4 BY R5.L; -//r5 = rot (r5 by rl5); - R6 = ROT R6 BY R5.L; - R7 = ROT R7 BY R5.L; - CHECKREG r0, 0x000D8091; - CHECKREG r1, 0x5678891A; - CHECKREG r2, 0x678911A2; - CHECKREG r3, 0x789A9A2B; - CHECKREG r4, 0x89AB22B3; - CHECKREG r5, 0x5678FFEF; - CHECKREG r6, 0xABCDB3C4; - CHECKREG r7, 0xBCDEBC4D; - - imm32 r0, 0x0123000e; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R6.L = -30; - R0 = ROT R0 BY R6.L; - R1 = ROT R1 BY R6.L; - R2 = ROT R2 BY R6.L; - R3 = ROT R3 BY R6.L; - R4 = ROT R4 BY R6.L; - R5 = ROT R5 BY R6.L; -//r6 = rot (r6 by rl6); - R7 = ROT R7 BY R6.L; - CHECKREG r0, 0x09180070; - CHECKREG r1, 0x91A2B3C0; - CHECKREG r2, 0x1A2B3C48; - CHECKREG r3, 0xA2B3C4D4; - CHECKREG r4, 0x2B3C4D5D; - CHECKREG r5, 0xB3C4D5E1; - CHECKREG r6, 0x6789FFE2; - CHECKREG r7, 0xC4D5E6F1; - - imm32 r0, 0x0123000f; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R7.L = -31; - R0 = ROT R0 BY R7.L; - R1 = ROT R1 BY R7.L; - R2 = ROT R2 BY R7.L; - R3 = ROT R3 BY R7.L; - R4 = ROT R4 BY R7.L; - R5 = ROT R5 BY R7.L; - R6 = ROT R6 BY R7.L; - R7 = ROT R7 BY R7.L; - CHECKREG r0, 0x048C003E; - CHECKREG r1, 0x48D159E0; - CHECKREG r2, 0x8D159E24; - CHECKREG r3, 0xD159E268; - CHECKREG r4, 0x159E26AC; - CHECKREG r5, 0x59E26AF2; - CHECKREG r6, 0x9E26AF36; - CHECKREG r7, 0xE26BFF86; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_rot_mix.s b/sim/testsuite/sim/bfin/c_dsp32shift_rot_mix.s deleted file mode 100644 index 7639b99..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_rot_mix.s +++ /dev/null @@ -1,437 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot_mix/c_dsp32shift_rot_mix.dsp -// Spec Reference: dsp32shift rot -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - - imm32 r0, 0x01230000; - imm32 r1, 0x12345678; - imm32 r2, 0x83456789; - imm32 r3, 0x9456789a; - imm32 r4, 0xa56789ab; - imm32 r5, 0xb6789abc; - imm32 r6, 0xc789abcd; - imm32 r7, 0xd89abcde; - R1 = ROT R0 BY R0.L; - R2 = ROT R1 BY R0.L; - R3 = ROT R2 BY R0.L; - R4 = ROT R3 BY R0.L; - R5 = ROT R4 BY R0.L; - R6 = ROT R5 BY R0.L; - R7 = ROT R6 BY R0.L; - R0 = ROT R7 BY R0.L; - CHECKREG r0, 0x01230000; - CHECKREG r1, 0x01230000; - CHECKREG r2, 0x01230000; - CHECKREG r3, 0x01230000; - CHECKREG r4, 0x01230000; - CHECKREG r5, 0x01230000; - CHECKREG r6, 0x01230000; - CHECKREG r7, 0x01230000; - - A0 = 0; - A0.L = R0.L; - A0.H = R0.H; - A0 = ROT A0 BY R1.L; - R6 = A0.w; - imm32 r4, 0x30003000; - imm32 r1, 5; - R7 = ROT R4 BY R1.L; - CHECKREG r6, 0x01230000; - CHECKREG r7, 0x00060003; - - imm32 r0, 0x11230001; - imm32 r1, 0xc2345678; - imm32 r2, 0xd3456789; - imm32 r3, 0xb456789a; - imm32 r4, 0x056789ab; - imm32 r5, 0x36789abc; - imm32 r6, 0x1789abcd; - imm32 r7, 0x189abcde; - R1.L = 5; - R2 = ROT R0 BY R1.L; - R3 = ROT R1 BY R1.L; - R4 = ROT R2 BY R1.L; - R5 = ROT R3 BY R1.L; - R6 = ROT R4 BY R1.L; - R7 = ROT R5 BY R1.L; - R0 = ROT R6 BY R1.L; - R1 = ROT R7 BY R1.L; - CHECKREG r0, 0x00108908; - CHECKREG r1, 0x005613A0; - CHECKREG r2, 0x24600021; - CHECKREG r3, 0x468000AC; - CHECKREG r4, 0x8C000422; - CHECKREG r5, 0xD0001584; - CHECKREG r6, 0x80008448; - CHECKREG r7, 0x0002B09D; - - imm32 r0, 0x01230002; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x8456789a; - imm32 r4, 0x956789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0xc789abcd; - imm32 r7, 0x789abcde; - R2 = 15; - R3 = ROT R0 BY R2.L; - R4 = ROT R1 BY R2.L; - R5 = ROT R2 BY R2.L; - R6 = ROT R3 BY R2.L; - R7 = ROT R4 BY R2.L; - R0 = ROT R5 BY R2.L; - R1 = ROT R6 BY R2.L; - R2 = ROT R7 BY R2.L; - CHECKREG r0, 0xC0000001; - CHECKREG r1, 0x10006009; - CHECKREG r2, 0x45678891; - CHECKREG r3, 0x80010048; - CHECKREG r4, 0x2B3C448D; - CHECKREG r5, 0x00078000; - CHECKREG r6, 0x80242000; - CHECKREG r7, 0x22468ACF; - - imm32 r0, 0x21230003; - imm32 r1, 0x22345678; - imm32 r2, 0x23456789; - imm32 r3, 0x2456789a; - imm32 r4, 0x256789ab; - imm32 r5, 0x26789abc; - imm32 r6, 0x2789abcd; - imm32 r7, 0x289abcde; - R3.L = 24; - R4 = ROT R0 BY R3.L; - R5 = ROT R1 BY R3.L; - R6 = ROT R2 BY R3.L; - R7 = ROT R3 BY R3.L; - R0 = ROT R4 BY R3.L; - R1 = ROT R5 BY R3.L; - R2 = ROT R6 BY R3.L; - R3 = ROT R7 BY R3.L; - CHECKREG r0, 0x8001C848; - CHECKREG r1, 0x2BBC088D; - CHECKREG r2, 0xB34488D1; - CHECKREG r3, 0x000C4915; - CHECKREG r4, 0x03909180; - CHECKREG r5, 0x78111A2B; - CHECKREG r6, 0x8911A2B3; - CHECKREG r7, 0x18922B00; - - imm32 r0, 0x01230004; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R4.L = -1; - R0 = ROT R0 BY R4.L; - R1 = ROT R1 BY R4.L; - R2 = ROT R2 BY R4.L; - R3 = ROT R3 BY R4.L; - R4 = ROT R4 BY R4.L; - R5 = ROT R5 BY R4.L; - R6 = ROT R6 BY R4.L; - R7 = ROT R7 BY R4.L; - CHECKREG r0, 0x80918002; - CHECKREG r1, 0x091A2B3C; - CHECKREG r2, 0x11A2B3C4; - CHECKREG r3, 0x9A2B3C4D; - CHECKREG r4, 0x22B3FFFF; - CHECKREG r5, 0xAB3C4D5E; - CHECKREG r6, 0x33C4D5E6; - CHECKREG r7, 0xBC4D5E6F; - - imm32 r0, 0x01230005; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R5.L = -6; - R6 = ROT R0 BY R5.L; - R7 = ROT R1 BY R5.L; - R0 = ROT R2 BY R5.L; - R1 = ROT R3 BY R5.L; - R2 = ROT R4 BY R5.L; - R3 = ROT R5 BY R5.L; - R4 = ROT R6 BY R5.L; - R5 = ROT R7 BY R5.L; - CHECKREG r0, 0x4C8D159E; - CHECKREG r1, 0xD0D159E2; - CHECKREG r2, 0x59159E26; - CHECKREG r3, 0xD559E3FF; - CHECKREG r4, 0x04A01230; - CHECKREG r5, 0xCB012345; - CHECKREG r6, 0x28048C00; - CHECKREG r7, 0xC048D159; - - imm32 r0, 0x01230006; - imm32 r1, 0x82345678; - imm32 r2, 0x73456789; - imm32 r3, 0x3456789a; - imm32 r4, 0xd56789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0xc789abcd; - imm32 r7, 0x789abcde; - R6.L = -15; - R7 = ROT R0 BY R6.L; - R0 = ROT R1 BY R6.L; - R1 = ROT R2 BY R6.L; - R2 = ROT R3 BY R6.L; - R3 = ROT R4 BY R6.L; - R4 = ROT R5 BY R6.L; - R5 = ROT R6 BY R6.L; - R6 = ROT R7 BY R6.L; - CHECKREG r0, 0x59E10468; - CHECKREG r1, 0x9E26E68A; - CHECKREG r2, 0xE26A68AC; - CHECKREG r3, 0x26AFAACF; - CHECKREG r4, 0x6AF0ACF1; - CHECKREG r5, 0xFFC58F13; - CHECKREG r6, 0x091A0030; - CHECKREG r7, 0x00180246; - - imm32 r0, 0x01230007; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R7.L = -27; - R0 = ROT R0 BY R7.L; - R1 = ROT R1 BY R7.L; - R2 = ROT R2 BY R7.L; - R3 = ROT R3 BY R7.L; - R4 = ROT R4 BY R7.L; - R5 = ROT R5 BY R7.L; - R6 = ROT R6 BY R7.L; - R7 = ROT R7 BY R7.L; - CHECKREG r0, 0x48C001C0; - CHECKREG r1, 0x8D159E02; - CHECKREG r2, 0xD159E244; - CHECKREG r3, 0x159E2686; - CHECKREG r4, 0x59E26AE8; - CHECKREG r5, 0x9E26AF2A; - CHECKREG r6, 0xE26AF36C; - CHECKREG r7, 0x26BFF96F; - - imm32 r0, 0x01230008; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R0.L = 7; -//r0 = rot (r0 by rl0); - R1 = ROT R1 BY R0.L; - R2 = ROT R2 BY R0.L; - R3 = ROT R3 BY R0.L; - R4 = ROT R4 BY R0.L; - R5 = ROT R5 BY R0.L; - R6 = ROT R6 BY R0.L; - R7 = ROT R7 BY R0.L; - CHECKREG r0, 0x01230007; - CHECKREG r1, 0x1A2B3C04; - CHECKREG r2, 0xA2B3C4C8; - CHECKREG r3, 0x2B3C4D4D; - CHECKREG r4, 0xB3C4D591; - CHECKREG r5, 0x3C4D5E15; - CHECKREG r6, 0xC4D5E6D9; - CHECKREG r7, 0x4D5E6F5E; - - imm32 r0, 0x01230009; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R1.L = 16; - R0 = ROT R0 BY R1.L; -//r1 = rot (r1 by rl1); - R2 = ROT R2 BY R1.L; - R3 = ROT R3 BY R1.L; - R4 = ROT R4 BY R1.L; - R5 = ROT R5 BY R1.L; - R6 = ROT R6 BY R1.L; - R7 = ROT R7 BY R1.L; - CHECKREG r0, 0x00090091; - CHECKREG r1, 0x12340010; - CHECKREG r2, 0x678991A2; - CHECKREG r3, 0x789A9A2B; - CHECKREG r4, 0x89AB22B3; - CHECKREG r5, 0x9ABCAB3C; - CHECKREG r6, 0xABCD33C4; - CHECKREG r7, 0xBCDEBC4D; - - imm32 r0, 0x0123000a; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R2.L = 31; - R0 = ROT R0 BY R2.L; - R1 = ROT R1 BY R2.L; -//r2 = rot (r2 by rl2); - R3 = ROT R3 BY R2.L; - R4 = ROT R4 BY R2.L; - R5 = ROT R5 BY R2.L; - R6 = ROT R6 BY R2.L; - R7 = ROT R7 BY R2.L; - CHECKREG r0, 0x0048C002; - CHECKREG r1, 0x448D159E; - CHECKREG r2, 0x2345001F; - CHECKREG r3, 0x0D159E26; - CHECKREG r4, 0xD159E26A; - CHECKREG r5, 0x559E26AF; - CHECKREG r6, 0x99E26AF3; - CHECKREG r7, 0x1E26AF37; - - imm32 r0, 0x0123000b; - imm32 r1, 0x92345678; - imm32 r2, 0x93456789; - imm32 r3, 0xc456789a; - imm32 r4, 0xa56789ab; - imm32 r5, 0xb6789abc; - imm32 r6, 0xe789abcd; - imm32 r7, 0xf89abcde; - R3.L = 33; - R0 = ROT R0 BY R3.L; - R1 = ROT R1 BY R3.L; - R2 = ROT R2 BY R3.L; -//r3 = rot (r3 by rl3); - R4 = ROT R4 BY R3.L; - R5 = ROT R5 BY R3.L; - R6 = ROT R6 BY R3.L; - R7 = ROT R7 BY R3.L; - CHECKREG r0, 0x048C002E; - CHECKREG r1, 0x48D159E1; - CHECKREG r2, 0x4D159E25; - CHECKREG r3, 0xC4560021; - CHECKREG r4, 0x959E26AD; - CHECKREG r5, 0xD9E26AF1; - CHECKREG r6, 0x9E26AF35; - CHECKREG r7, 0xE26AF37B; - - imm32 r0, 0x0123000c; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R4.L = -2; - R0 = ROT R0 BY R4.L; - R1 = ROT R1 BY R4.L; - R2 = ROT R2 BY R4.L; - R3 = ROT R3 BY R4.L; -//r4 = rot (r4 by rl4); - R5 = ROT R5 BY R4.L; - R6 = ROT R6 BY R4.L; - R7 = ROT R7 BY R4.L; - CHECKREG r0, 0x4048C003; - CHECKREG r1, 0x048D159E; - CHECKREG r2, 0x88D159E2; - CHECKREG r3, 0x0D159E26; - CHECKREG r4, 0x4567FFFE; - CHECKREG r5, 0x559E26AF; - CHECKREG r6, 0x99E26AF3; - CHECKREG r7, 0x1E26AF37; - - imm32 r0, 0x0123000d; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R5.L = -14; - R0 = ROT R0 BY R5.L; - R1 = ROT R1 BY R5.L; - R2 = ROT R2 BY R5.L; - R3 = ROT R3 BY R5.L; - R4 = ROT R4 BY R5.L; -//r5 = rot (r5 by rl5); - R6 = ROT R6 BY R5.L; - R7 = ROT R7 BY R5.L; - CHECKREG r0, 0x006C048C; - CHECKREG r1, 0xB3C048D1; - CHECKREG r2, 0x3C488D15; - CHECKREG r3, 0xC4D4D159; - CHECKREG r4, 0x4D5D159E; - CHECKREG r5, 0x5678FFF2; - CHECKREG r6, 0x5E699E26; - CHECKREG r7, 0xE6F5E26A; - - imm32 r0, 0x0123000e; - imm32 r1, 0x12345678; - imm32 r2, 0x23456789; - imm32 r3, 0x3456789a; - imm32 r4, 0x456789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x6789abcd; - imm32 r7, 0x789abcde; - R6.L = -16; - R0 = ROT R0 BY R6.L; - R1 = ROT R1 BY R6.L; - R2 = ROT R2 BY R6.L; - R3 = ROT R3 BY R6.L; - R4 = ROT R4 BY R6.L; - R5 = ROT R5 BY R6.L; -//r6 = rot (r6 by rl6); - R7 = ROT R7 BY R6.L; - CHECKREG r0, 0x001D0123; - CHECKREG r1, 0xACF01234; - CHECKREG r2, 0xCF122345; - CHECKREG r3, 0xF1343456; - CHECKREG r4, 0x13564567; - CHECKREG r5, 0x35795678; - CHECKREG r6, 0x6789FFF0; - CHECKREG r7, 0x79BD789A; - - imm32 r0, 0x0123000f; - imm32 r1, 0x12345678; - imm32 r2, 0x83456789; - imm32 r3, 0x3456789a; - imm32 r4, 0xd56789ab; - imm32 r5, 0x56789abc; - imm32 r6, 0x9789abcd; - imm32 r7, 0x789abcde; - R7.L = -32; - R0 = ROT R0 BY R7.L; - R1 = ROT R1 BY R7.L; - R2 = ROT R2 BY R7.L; - R3 = ROT R3 BY R7.L; - R4 = ROT R4 BY R7.L; - R5 = ROT R5 BY R7.L; - R6 = ROT R6 BY R7.L; - R7 = ROT R7 BY R7.L; - CHECKREG r0, 0x0246001f; - CHECKREG r1, 0x2468ACF0; - CHECKREG r2, 0x068ACF12; - CHECKREG r3, 0x68ACF135; - CHECKREG r4, 0xAACF1356; - CHECKREG r5, 0xACF13579; - CHECKREG r6, 0x2F13579A; - CHECKREG r7, 0xF135FFC1; - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_signbits_r.s b/sim/testsuite/sim/bfin/c_dsp32shift_signbits_r.s deleted file mode 100644 index 6bdb7a0..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_signbits_r.s +++ /dev/null @@ -1,214 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_signbits_r/c_dsp32shift_signbits_r.dsp -// Spec Reference: dsp32shift signbits dregs -# mach: bfin - -.include "testutils.inc" - start - - - - - -imm32 r0, 0x88880000; -imm32 r1, 0x34560001; -imm32 r2, 0x08000002; -imm32 r3, 0x08000003; -imm32 r4, 0x08000004; -imm32 r5, 0x08000005; -imm32 r6, 0x08000006; -imm32 r7, 0x08000007; -R7.L = SIGNBITS R0; -R1.L = SIGNBITS R0; -R2.L = SIGNBITS R0; -R3.L = SIGNBITS R0; -R4.L = SIGNBITS R0; -R5.L = SIGNBITS R0; -R6.L = SIGNBITS R0; -R0.L = SIGNBITS R0; -CHECKREG r0, 0x88880000; -CHECKREG r1, 0x34560000; -CHECKREG r2, 0x08000000; -CHECKREG r3, 0x08000000; -CHECKREG r4, 0x08000000; -CHECKREG r5, 0x08000000; -CHECKREG r6, 0x08000000; -CHECKREG r7, 0x08000000; - -imm32 r0, 0x9999001E; -imm32 r1, 0x0000001E; -imm32 r2, 0x0000001E; -imm32 r3, 0x0000001E; -imm32 r4, 0x0000001E; -imm32 r5, 0x0000001E; -imm32 r6, 0x0000001E; -imm32 r7, 0x0000001E; -R0.L = SIGNBITS R1; -R7.L = SIGNBITS R1; -R2.L = SIGNBITS R1; -R3.L = SIGNBITS R1; -R4.L = SIGNBITS R1; -R5.L = SIGNBITS R1; -R6.L = SIGNBITS R1; -R1.L = SIGNBITS R1; -CHECKREG r0, 0x9999001A; -CHECKREG r1, 0x0000001A; -CHECKREG r2, 0x0000001A; -CHECKREG r3, 0x0000001A; -CHECKREG r4, 0x0000001A; -CHECKREG r5, 0x0000001A; -CHECKREG r6, 0x0000001A; -CHECKREG r7, 0x0000001A; - - -imm32 r0, 0x0aaae001; -imm32 r1, 0x0000e001; -imm32 r2, 0xaaaa000f; -imm32 r3, 0x0a00e003; -imm32 r4, 0x00a0e004; -imm32 r5, 0x00a0e005; -imm32 r6, 0x0a00e006; -imm32 r7, 0x0b00e007; -R0.L = SIGNBITS R2; -R1.L = SIGNBITS R2; -R7.L = SIGNBITS R2; -R3.L = SIGNBITS R2; -R4.L = SIGNBITS R2; -R5.L = SIGNBITS R2; -R6.L = SIGNBITS R2; -R2.L = SIGNBITS R2; -CHECKREG r0, 0x0AAA0000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0xAAAA0000; -CHECKREG r3, 0x0A000000; -CHECKREG r4, 0x00A00000; -CHECKREG r5, 0x00A00000; -CHECKREG r6, 0x0A000000; -CHECKREG r7, 0x0B000000; - -imm32 r0, 0x0b00f001; -imm32 r1, 0x0a00f001; -imm32 r2, 0x0b00f002; -imm32 r3, 0xbbbb0010; -imm32 r4, 0x0b00f004; -imm32 r5, 0x0b00f005; -imm32 r6, 0x0b00f006; -imm32 r7, 0x00b0f007; -R0.L = SIGNBITS R3; -R1.L = SIGNBITS R3; -R2.L = SIGNBITS R3; -R7.L = SIGNBITS R3; -R4.L = SIGNBITS R3; -R5.L = SIGNBITS R3; -R6.L = SIGNBITS R3; -R3.L = SIGNBITS R3; -CHECKREG r0, 0x0B000000; -CHECKREG r1, 0x0A000000; -CHECKREG r2, 0x0B000000; -CHECKREG r3, 0xBBBB0000; -CHECKREG r4, 0x0B000000; -CHECKREG r5, 0x0B000000; -CHECKREG r6, 0x0B000000; -CHECKREG r7, 0x00B00000; - -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0xcccc0000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = SIGNBITS R4; -R1.L = SIGNBITS R4; -R2.L = SIGNBITS R4; -R3.L = SIGNBITS R4; -R7.L = SIGNBITS R4; -R5.L = SIGNBITS R4; -R6.L = SIGNBITS R4; -R4.L = SIGNBITS R4; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020001; -CHECKREG r3, 0x00030001; -CHECKREG r4, 0xCCCC0001; -CHECKREG r5, 0x00050001; -CHECKREG r6, 0x00060001; -CHECKREG r7, 0x00070001; - -imm32 r0, 0xa0010000; -imm32 r1, 0x00010001; -imm32 r2, 0xa0020000; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xdddd0000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R0.L = SIGNBITS R5; -R1.L = SIGNBITS R5; -R2.L = SIGNBITS R5; -R3.L = SIGNBITS R5; -R4.L = SIGNBITS R5; -R7.L = SIGNBITS R5; -R6.L = SIGNBITS R5; -R5.L = SIGNBITS R5; -CHECKREG r0, 0xA0010001; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0xA0020001; -CHECKREG r3, 0xA0030001; -CHECKREG r4, 0xA0040001; -CHECKREG r5, 0xDDDD0001; -CHECKREG r6, 0xA0060001; -CHECKREG r7, 0xA0070001; - - -imm32 r0, 0xb0010000; -imm32 r1, 0xb0010000; -imm32 r2, 0xb002000f; -imm32 r3, 0xb0030000; -imm32 r4, 0xb0040000; -imm32 r5, 0xb0050000; -imm32 r6, 0xeeee0000; -imm32 r7, 0xb0070000; -R0.L = SIGNBITS R6; -R1.L = SIGNBITS R6; -R2.L = SIGNBITS R6; -R3.L = SIGNBITS R6; -R4.L = SIGNBITS R6; -R5.L = SIGNBITS R6; -R7.L = SIGNBITS R6; -R6.L = SIGNBITS R6; -CHECKREG r0, 0xB0010002; -CHECKREG r1, 0xB0010002; -CHECKREG r2, 0xB0020002; -CHECKREG r3, 0xB0030002; -CHECKREG r4, 0xB0040002; -CHECKREG r5, 0xB0050002; -CHECKREG r6, 0xEEEE0002; -CHECKREG r7, 0xB0070002; - -imm32 r0, 0xd0010000; -imm32 r1, 0xd0010000; -imm32 r2, 0xd0020000; -imm32 r3, 0xd0030010; -imm32 r4, 0xd0040000; -imm32 r5, 0xd0050000; -imm32 r6, 0xd0060000; -imm32 r7, 0xffff0000; -R0.L = SIGNBITS R7; -R1.L = SIGNBITS R7; -R2.L = SIGNBITS R7; -R3.L = SIGNBITS R7; -R4.L = SIGNBITS R7; -R5.L = SIGNBITS R7; -R6.L = SIGNBITS R7; -R7.L = SIGNBITS R7; - -CHECKREG r0, 0xD001000F; -CHECKREG r1, 0xD001000F; -CHECKREG r2, 0xD002000F; -CHECKREG r3, 0xD003000F; -CHECKREG r4, 0xD004000F; -CHECKREG r5, 0xD005000F; -CHECKREG r6, 0xD006000F; -CHECKREG r7, 0xFFFF000F; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rh.s b/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rh.s deleted file mode 100644 index 8ae46ae..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rh.s +++ /dev/null @@ -1,214 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_signbits_rh/c_dsp32shift_signbits_rh.dsp -// Spec Reference: dsp32shift signbits dregs_hi -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0xd1000000; -imm32 r1, 0xd2000001; -imm32 r2, 0xd3000002; -imm32 r3, 0xd4000003; -imm32 r4, 0xd5000004; -imm32 r5, 0xd6000005; -imm32 r6, 0xd7000006; -imm32 r7, 0xd8000007; -R0.L = SIGNBITS R0.H; -R1.L = SIGNBITS R0.H; -R2.L = SIGNBITS R0.H; -R3.L = SIGNBITS R0.H; -R4.L = SIGNBITS R0.H; -R5.L = SIGNBITS R0.H; -R6.L = SIGNBITS R0.H; -R7.L = SIGNBITS R0.H; -CHECKREG r0, 0xD1000001; -CHECKREG r1, 0xD2000001; -CHECKREG r2, 0xD3000001; -CHECKREG r3, 0xD4000001; -CHECKREG r4, 0xD5000001; -CHECKREG r5, 0xD6000001; -CHECKREG r6, 0xD7000001; -CHECKREG r7, 0xD8000001; - -imm32 r0, 0xe200d001; -imm32 r1, 0xe2000001; -imm32 r2, 0xe200d002; -imm32 r3, 0xe200d003; -imm32 r4, 0xe200d004; -imm32 r5, 0xe200d005; -imm32 r6, 0xe200d006; -imm32 r7, 0xe200d007; -R0.L = SIGNBITS R1.H; -R1.L = SIGNBITS R1.H; -R2.L = SIGNBITS R1.H; -R3.L = SIGNBITS R1.H; -R4.L = SIGNBITS R1.H; -R5.L = SIGNBITS R1.H; -R6.L = SIGNBITS R1.H; -R7.L = SIGNBITS R1.H; -CHECKREG r0, 0xE2000002; -CHECKREG r1, 0xE2000002; -CHECKREG r2, 0xE2000002; -CHECKREG r3, 0xE2000002; -CHECKREG r4, 0xE2000002; -CHECKREG r5, 0xE2000002; -CHECKREG r6, 0xE2000002; -CHECKREG r7, 0xE2000002; - - -imm32 r0, 0x0000e001; -imm32 r1, 0x0000e001; -imm32 r2, 0xf000000f; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000e004; -imm32 r5, 0x0000e005; -imm32 r6, 0x0000e006; -imm32 r7, 0x0000e007; -R0.L = SIGNBITS R2.H; -R1.L = SIGNBITS R2.H; -R2.L = SIGNBITS R2.H; -R3.L = SIGNBITS R2.H; -R4.L = SIGNBITS R2.H; -R5.L = SIGNBITS R2.H; -R6.L = SIGNBITS R2.H; -R7.L = SIGNBITS R2.H; -CHECKREG r0, 0x00000003; -CHECKREG r1, 0x00000003; -CHECKREG r2, 0xF0000003; -CHECKREG r3, 0x00000003; -CHECKREG r4, 0x00000003; -CHECKREG r5, 0x00000003; -CHECKREG r6, 0x00000003; -CHECKREG r7, 0x00000003; - -imm32 r0, 0x0100f001; -imm32 r1, 0x0100f001; -imm32 r2, 0x0100f002; -imm32 r3, 0x01000010; -imm32 r4, 0x0100f004; -imm32 r5, 0x0100f005; -imm32 r6, 0x0100f006; -imm32 r7, 0x0100f007; -R0.L = SIGNBITS R3.H; -R1.L = SIGNBITS R3.H; -R2.L = SIGNBITS R3.H; -R3.L = SIGNBITS R3.H; -R4.L = SIGNBITS R3.H; -R5.L = SIGNBITS R3.H; -R6.L = SIGNBITS R3.H; -R7.L = SIGNBITS R3.H; -CHECKREG r0, 0x01000006; -CHECKREG r1, 0x01000006; -CHECKREG r2, 0x01000006; -CHECKREG r3, 0x01000006; -CHECKREG r4, 0x01000006; -CHECKREG r5, 0x01000006; -CHECKREG r6, 0x01000006; -CHECKREG r7, 0x01000006; - -imm32 r0, 0x04000000; -imm32 r1, 0x04010000; -imm32 r2, 0x04020000; -imm32 r3, 0x04030000; -imm32 r4, 0x04040000; -imm32 r5, 0x04050000; -imm32 r6, 0x04060000; -imm32 r7, 0x04070000; -R0.L = SIGNBITS R4.H; -R1.L = SIGNBITS R4.H; -R2.L = SIGNBITS R4.H; -R3.L = SIGNBITS R4.H; -R4.L = SIGNBITS R4.H; -R5.L = SIGNBITS R4.H; -R6.L = SIGNBITS R4.H; -R7.L = SIGNBITS R4.H; -CHECKREG r0, 0x04000004; -CHECKREG r1, 0x04010004; -CHECKREG r2, 0x04020004; -CHECKREG r3, 0x04030004; -CHECKREG r4, 0x04040004; -CHECKREG r5, 0x04050004; -CHECKREG r6, 0x04060004; -CHECKREG r7, 0x04070004; - -imm32 r0, 0xa5010000; -imm32 r1, 0xa5010001; -imm32 r2, 0xa5020000; -imm32 r3, 0xa5030000; -imm32 r4, 0xa5540000; -imm32 r5, 0xa5550000; -imm32 r6, 0xa5060000; -imm32 r7, 0xa5070000; -R0.L = SIGNBITS R5.H; -R1.L = SIGNBITS R5.H; -R2.L = SIGNBITS R5.H; -R3.L = SIGNBITS R5.H; -R4.L = SIGNBITS R5.H; -R5.L = SIGNBITS R5.H; -R6.L = SIGNBITS R5.H; -R7.L = SIGNBITS R5.H; -CHECKREG r0, 0xA5010000; -CHECKREG r1, 0xA5010000; -CHECKREG r2, 0xA5020000; -CHECKREG r3, 0xA5030000; -CHECKREG r4, 0xA5540000; -CHECKREG r5, 0xA5550000; -CHECKREG r6, 0xA5060000; -CHECKREG r7, 0xA5070000; - - -imm32 r0, 0xb6010000; -imm32 r1, 0xb6010000; -imm32 r2, 0xb602000f; -imm32 r3, 0xb6030000; -imm32 r4, 0xb6040000; -imm32 r5, 0xb6050000; -imm32 r6, 0xb6060000; -imm32 r7, 0xb6670000; -R0.L = SIGNBITS R6.H; -R1.L = SIGNBITS R6.H; -R2.L = SIGNBITS R6.H; -R3.L = SIGNBITS R6.H; -R4.L = SIGNBITS R6.H; -R5.L = SIGNBITS R6.H; -R6.L = SIGNBITS R6.H; -R7.L = SIGNBITS R6.H; -CHECKREG r0, 0xB6010000; -CHECKREG r1, 0xB6010000; -CHECKREG r2, 0xB6020000; -CHECKREG r3, 0xB6030000; -CHECKREG r4, 0xB6040000; -CHECKREG r5, 0xB6050000; -CHECKREG r6, 0xB6060000; -CHECKREG r7, 0xB6670000; - -imm32 r0, 0xd7010000; -imm32 r1, 0xd7010000; -imm32 r2, 0xd7020000; -imm32 r3, 0xd7030010; -imm32 r4, 0xd7040000; -imm32 r5, 0xd7050000; -imm32 r6, 0xd7060000; -imm32 r7, 0xd7070000; -R0.L = SIGNBITS R7.H; -R1.L = SIGNBITS R7.H; -R2.L = SIGNBITS R7.H; -R3.L = SIGNBITS R7.H; -R4.L = SIGNBITS R7.H; -R5.L = SIGNBITS R7.H; -R6.L = SIGNBITS R7.H; -R7.L = SIGNBITS R7.H; -CHECKREG r0, 0xD7010001; -CHECKREG r1, 0xD7010001; -CHECKREG r2, 0xD7020001; -CHECKREG r3, 0xD7030001; -CHECKREG r4, 0xD7040001; -CHECKREG r5, 0xD7050001; -CHECKREG r6, 0xD7060001; -CHECKREG r7, 0xD7070001; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rl.s b/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rl.s deleted file mode 100644 index 3f3ccfd..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rl.s +++ /dev/null @@ -1,210 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_signbits_rl/c_dsp32shift_signbits_rl.dsp -// Spec Reference: dsp32shift signbits dregs_lo -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x0000c001; -imm32 r2, 0x0000c002; -imm32 r3, 0x0000c003; -imm32 r4, 0x0000c004; -imm32 r5, 0x0000c005; -imm32 r6, 0x0000c006; -imm32 r7, 0x0000c007; -R7.L = SIGNBITS R0.L; -R1.L = SIGNBITS R0.L; -R2.L = SIGNBITS R0.L; -R3.L = SIGNBITS R0.L; -R4.L = SIGNBITS R0.L; -R5.L = SIGNBITS R0.L; -R6.L = SIGNBITS R0.L; -R0.L = SIGNBITS R0.L; -CHECKREG r1, 0x0000000F; -CHECKREG r0, 0x0000000F; -CHECKREG r2, 0x0000000F; -CHECKREG r3, 0x0000000F; -CHECKREG r4, 0x0000000F; -CHECKREG r5, 0x0000000F; -CHECKREG r6, 0x0000000F; -CHECKREG r7, 0x0000000F; - -imm32 r0, 0x00000001; -imm32 r1, 0x00008001; -imm32 r2, 0x0000d002; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000c005; -imm32 r6, 0x0000d006; -imm32 r7, 0x0000e007; -R0.L = SIGNBITS R1.L; -R7.L = SIGNBITS R1.L; -R2.L = SIGNBITS R1.L; -R3.L = SIGNBITS R1.L; -R4.L = SIGNBITS R1.L; -R5.L = SIGNBITS R1.L; -R6.L = SIGNBITS R1.L; -R1.L = SIGNBITS R1.L; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - - -imm32 r0, 0x0000c001; -imm32 r1, 0x0000d001; -imm32 r2, 0x0000c00f; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000f005; -imm32 r6, 0x0000f006; -imm32 r7, 0x0000f007; -R0.L = SIGNBITS R2.L; -R1.L = SIGNBITS R2.L; -R7.L = SIGNBITS R2.L; -R3.L = SIGNBITS R2.L; -R4.L = SIGNBITS R2.L; -R5.L = SIGNBITS R2.L; -R6.L = SIGNBITS R2.L; -R2.L = SIGNBITS R2.L; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000001; - -imm32 r0, 0x00009001; -imm32 r1, 0x0000a001; -imm32 r2, 0x0000b002; -imm32 r3, 0x00000e10; -imm32 r4, 0x0000c004; -imm32 r5, 0x0000d005; -imm32 r6, 0x0000e006; -imm32 r7, 0x0000f007; -R0.L = SIGNBITS R3.L; -R1.L = SIGNBITS R3.L; -R2.L = SIGNBITS R3.L; -R7.L = SIGNBITS R3.L; -R4.L = SIGNBITS R3.L; -R5.L = SIGNBITS R3.L; -R6.L = SIGNBITS R3.L; -R3.L = SIGNBITS R3.L; -CHECKREG r0, 0x00000003; -CHECKREG r1, 0x00000003; -CHECKREG r2, 0x00000003; -CHECKREG r3, 0x00000003; -CHECKREG r4, 0x00000003; -CHECKREG r5, 0x00000003; -CHECKREG r6, 0x00000003; -CHECKREG r7, 0x00000003; - -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x0000f000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.L = SIGNBITS R4.L; -R1.L = SIGNBITS R4.L; -R2.L = SIGNBITS R4.L; -R3.L = SIGNBITS R4.L; -R7.L = SIGNBITS R4.L; -R5.L = SIGNBITS R4.L; -R6.L = SIGNBITS R4.L; -R4.L = SIGNBITS R4.L; -CHECKREG r0, 0x00000003; -CHECKREG r1, 0x00010003; -CHECKREG r2, 0x00020003; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00000003; -CHECKREG r5, 0x00050003; -CHECKREG r6, 0x00060003; -CHECKREG r7, 0x00070003; - -imm32 r0, 0x90010000; -imm32 r1, 0x00010001; -imm32 r2, 0x90020000; -imm32 r3, 0x90030000; -imm32 r4, 0x90040000; -imm32 r5, 0x9008f000; -imm32 r6, 0x90060000; -imm32 r7, 0x90070000; -R0.L = SIGNBITS R5.L; -R1.L = SIGNBITS R5.L; -R2.L = SIGNBITS R5.L; -R3.L = SIGNBITS R5.L; -R4.L = SIGNBITS R5.L; -R7.L = SIGNBITS R5.L; -R6.L = SIGNBITS R5.L; -R5.L = SIGNBITS R5.L; -CHECKREG r0, 0x90010003; -CHECKREG r1, 0x00010003; -CHECKREG r2, 0x90020003; -CHECKREG r3, 0x90030003; -CHECKREG r4, 0x90040003; -CHECKREG r5, 0x90080003; -CHECKREG r6, 0x90060003; -CHECKREG r7, 0x90070003; - -imm32 r1, 0xa0010000; -imm32 r2, 0xa002000f; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa000fc00; -imm32 r7, 0xa0070000; -R0.L = SIGNBITS R6.L; -R1.L = SIGNBITS R6.L; -R2.L = SIGNBITS R6.L; -R3.L = SIGNBITS R6.L; -R4.L = SIGNBITS R6.L; -R5.L = SIGNBITS R6.L; -R7.L = SIGNBITS R6.L; -R6.L = SIGNBITS R6.L; -CHECKREG r0, 0x90010005; -CHECKREG r1, 0xA0010005; -CHECKREG r2, 0xA0020005; -CHECKREG r3, 0xA0030005; -CHECKREG r4, 0xA0040005; -CHECKREG r5, 0xA0050005; -CHECKREG r6, 0xA0000005; -CHECKREG r7, 0xA0070005; - -imm32 r0, 0xc0010001; -imm32 r1, 0xc0010001; -imm32 r2, 0xc0020002; -imm32 r3, 0xc0030010; -imm32 r4, 0xc0040004; -imm32 r5, 0xc0050005; -imm32 r6, 0xc0060006; -imm32 r7, 0xc007e007; -R0.L = SIGNBITS R7.L; -R1.L = SIGNBITS R7.L; -R2.L = SIGNBITS R7.L; -R3.L = SIGNBITS R7.L; -R4.L = SIGNBITS R7.L; -R5.L = SIGNBITS R7.L; -R6.L = SIGNBITS R7.L; -R7.L = SIGNBITS R7.L; -CHECKREG r0, 0xC0010002; -CHECKREG r1, 0xC0010002; -CHECKREG r2, 0xC0020002; -CHECKREG r3, 0xC0030002; -CHECKREG r4, 0xC0040002; -CHECKREG r5, 0xC0050002; -CHECKREG r6, 0xC0060002; -CHECKREG r7, 0xC0070002; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_vmax.s b/sim/testsuite/sim/bfin/c_dsp32shift_vmax.s deleted file mode 100644 index 4f3ccd1..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_vmax.s +++ /dev/null @@ -1,113 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_vmax/c_dsp32shift_vmax.dsp -// Spec Reference: dsp32shift vmax -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x11001001; -imm32 r1, 0x11001001; -imm32 r2, 0x12345678; -imm32 r3, 0x11001003; -imm32 r4, 0x11001004; -imm32 r5, 0x11001005; -imm32 r6, 0x11001006; -imm32 r7, 0x11001007; -A0 = R2; -R0.L = VIT_MAX( R0 ) (ASL); -R1.L = VIT_MAX( R1 ) (ASL); -R2.L = VIT_MAX( R2 ) (ASL); -R3.L = VIT_MAX( R3 ) (ASL); -R4.L = VIT_MAX( R4 ) (ASL); -R5.L = VIT_MAX( R5 ) (ASL); -R6.L = VIT_MAX( R6 ) (ASL); -R7.L = VIT_MAX( R7 ) (ASL); -CHECKREG r0, 0x11001100; -CHECKREG r1, 0x11001100; -CHECKREG r2, 0x12345678; -CHECKREG r3, 0x11001100; -CHECKREG r4, 0x11001100; -CHECKREG r5, 0x11001100; -CHECKREG r6, 0x11001100; -CHECKREG r7, 0x11001100; - -imm32 r0, 0xa1001001; -imm32 r1, 0x1b001001; -imm32 r2, 0x11c01002; -imm32 r3, 0x110d1003; -imm32 r4, 0x1100e004; -imm32 r5, 0x11001f05; -imm32 r6, 0x11001006; -imm32 r7, 0x11001001; -R1.L = VIT_MAX( R0 ) (ASL); -R2.L = VIT_MAX( R1 ) (ASL); -R3.L = VIT_MAX( R2 ) (ASL); -R4.L = VIT_MAX( R3 ) (ASL); -R5.L = VIT_MAX( R4 ) (ASL); -R6.L = VIT_MAX( R5 ) (ASL); -R7.L = VIT_MAX( R6 ) (ASL); -R0.L = VIT_MAX( R7 ) (ASL); -CHECKREG r0, 0xA1001B00; -CHECKREG r1, 0x1B001001; -CHECKREG r2, 0x11C01B00; -CHECKREG r3, 0x110D1B00; -CHECKREG r4, 0x11001B00; -CHECKREG r5, 0x11001B00; -CHECKREG r6, 0x11001B00; -CHECKREG r7, 0x11001B00; - - -imm32 r0, 0x20000000; -imm32 r1, 0x4300c001; -imm32 r2, 0x4040c002; -imm32 r3, 0x40056003; -imm32 r4, 0x4000c704; -imm32 r5, 0x4000c085; -imm32 r6, 0x4000c096; -imm32 r7, 0x4000c000; -R0.L = VIT_MAX( R0 ) (ASR); -R1.L = VIT_MAX( R1 ) (ASR); -R2.L = VIT_MAX( R2 ) (ASR); -R3.L = VIT_MAX( R3 ) (ASR); -R4.L = VIT_MAX( R4 ) (ASR); -R5.L = VIT_MAX( R5 ) (ASR); -R6.L = VIT_MAX( R6 ) (ASR); -R7.L = VIT_MAX( R7 ) (ASR); -CHECKREG r0, 0x20002000; -CHECKREG r1, 0x4300C001; -CHECKREG r2, 0x4040C002; -CHECKREG r3, 0x40056003; -CHECKREG r4, 0x40004000; -CHECKREG r5, 0x40004000; -CHECKREG r6, 0x40004000; -CHECKREG r7, 0x4000C000; - -imm32 r0, 0x10000000; -imm32 r1, 0x4200c001; -imm32 r2, 0x4030c002; -imm32 r3, 0x4004c003; -imm32 r4, 0x40005004; -imm32 r5, 0x4000c605; -imm32 r6, 0x4000c076; -imm32 r7, 0x4000c008; -R2.L = VIT_MAX( R0 ) (ASR); -R3.L = VIT_MAX( R1 ) (ASR); -R4.L = VIT_MAX( R2 ) (ASR); -R5.L = VIT_MAX( R3 ) (ASR); -R6.L = VIT_MAX( R4 ) (ASR); -R7.L = VIT_MAX( R5 ) (ASR); -R0.L = VIT_MAX( R6 ) (ASR); -R1.L = VIT_MAX( R7 ) (ASR); -CHECKREG r0, 0x10004030; -CHECKREG r1, 0x42004000; -CHECKREG r2, 0x40301000; -CHECKREG r3, 0x4004C001; -CHECKREG r4, 0x40004030; -CHECKREG r5, 0x4000C001; -CHECKREG r6, 0x40004030; -CHECKREG r7, 0x40004000; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s b/sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s deleted file mode 100644 index 0d4722a..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s +++ /dev/null @@ -1,113 +0,0 @@ -//Original:/testcases/core/c_dsp32shift_vmaxvmax/c_dsp32shift_vmaxvmax.dsp -// Spec Reference: dsp32shift vmax / vmax -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x11002001; -imm32 r1, 0x12001001; -imm32 r2, 0x11301302; -imm32 r3, 0x43001003; -imm32 r4, 0x11601604; -imm32 r5, 0x71001705; -imm32 r6, 0x81008006; -imm32 r7, 0x1900b007; -A0 = R3; -R1 = VIT_MAX( R1 , R0 ) (ASL); -R2 = VIT_MAX( R2 , R1 ) (ASL); -R3 = VIT_MAX( R3 , R2 ) (ASL); -R4 = VIT_MAX( R4 , R3 ) (ASL); -R5 = VIT_MAX( R5 , R4 ) (ASL); -R6 = VIT_MAX( R6 , R5 ) (ASL); -R7 = VIT_MAX( R7 , R6 ) (ASL); -R0 = VIT_MAX( R0 , R7 ) (ASL); -CHECKREG r0, 0x20018100; -CHECKREG r1, 0x12002001; -CHECKREG r2, 0x13022001; -CHECKREG r3, 0x43002001; -CHECKREG r4, 0x16044300; -CHECKREG r5, 0x71004300; -CHECKREG r6, 0x81007100; -CHECKREG r7, 0x19008100; - -imm32 r0, 0x11002001; -imm32 r1, 0xd2001001; -imm32 r2, 0x14301302; -imm32 r3, 0x43001003; -imm32 r4, 0x11f01604; -imm32 r5, 0xb1001705; -imm32 r6, 0xd1008006; -imm32 r7, 0x39056707; -R1 = VIT_MAX( R1 , R3 ) (ASL); -R2 = VIT_MAX( R2 , R4 ) (ASL); -R3 = VIT_MAX( R3 , R6 ) (ASL); -R4 = VIT_MAX( R4 , R5 ) (ASL); -R5 = VIT_MAX( R5 , R7 ) (ASL); -R6 = VIT_MAX( R6 , R0 ) (ASL); -R7 = VIT_MAX( R7 , R1 ) (ASL); -R0 = VIT_MAX( R0 , R2 ) (ASL); -CHECKREG r0, 0x20011604; -CHECKREG r1, 0x10014300; -CHECKREG r2, 0x14301604; -CHECKREG r3, 0x4300D100; -CHECKREG r4, 0x16041705; -CHECKREG r5, 0x17056707; -CHECKREG r6, 0xD1002001; -CHECKREG r7, 0x67074300; - -imm32 r0, 0xa1011001; -imm32 r1, 0x1b002001; -imm32 r2, 0x81c01302; -imm32 r3, 0x910d1403; -imm32 r4, 0x2100e504; -imm32 r5, 0x31007f65; -imm32 r6, 0x41007006; -imm32 r7, 0x15001801; -R1 = VIT_MAX( R1 , R0 ) (ASR); -R2 = VIT_MAX( R2 , R1 ) (ASR); -R3 = VIT_MAX( R3 , R2 ) (ASR); -R4 = VIT_MAX( R4 , R3 ) (ASR); -R5 = VIT_MAX( R5 , R4 ) (ASR); -R6 = VIT_MAX( R6 , R5 ) (ASR); -R7 = VIT_MAX( R7 , R6 ) (ASR); -R0 = VIT_MAX( R0 , R7 ) (ASR); -CHECKREG r0, 0x1001910D; -CHECKREG r1, 0x20011001; -CHECKREG r2, 0x81C02001; -CHECKREG r3, 0x910D81C0; -CHECKREG r4, 0x2100910D; -CHECKREG r5, 0x7F65910D; -CHECKREG r6, 0x7006910D; -CHECKREG r7, 0x1801910D; - -imm32 r0, 0xe1011001; -imm32 r1, 0x4b002001; -imm32 r2, 0x8fc01302; -imm32 r3, 0x910d1403; -imm32 r4, 0xb100e504; -imm32 r5, 0x41007f65; -imm32 r6, 0xaf007006; -imm32 r7, 0x16001801; -R0 = VIT_MAX( R4 , R0 ) (ASR); -R1 = VIT_MAX( R5 , R1 ) (ASR); -R2 = VIT_MAX( R6 , R2 ) (ASR); -R3 = VIT_MAX( R7 , R3 ) (ASR); -R4 = VIT_MAX( R0 , R4 ) (ASR); -R5 = VIT_MAX( R1 , R5 ) (ASR); -R6 = VIT_MAX( R2 , R6 ) (ASR); -R7 = VIT_MAX( R3 , R7 ) (ASR); -CHECKREG r0, 0xE5041001; -CHECKREG r1, 0x7F654B00; -CHECKREG r2, 0xAF008FC0; -CHECKREG r3, 0x1801910D; -CHECKREG r4, 0x1001E504; -CHECKREG r5, 0x7F657F65; -CHECKREG r6, 0xAF00AF00; -CHECKREG r7, 0x910D1801; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_a0alr.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_a0alr.s deleted file mode 100644 index 13bd532..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_a0alr.s +++ /dev/null @@ -1,213 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_a0alr/c_dsp32shiftim_a0alr.dsp -// Spec Reference: dsp32shift a0 ashift, lshift, rot -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - imm32 r0, 0x11140000; - imm32 r1, 0x012C003E; - imm32 r2, 0x81359E24; - imm32 r3, 0x81459E24; - imm32 r4, 0xD159E268; - imm32 r5, 0x51626AF2; - imm32 r6, 0x9176AF36; - imm32 r7, 0xE18BFF86; - - R0.L = 0; - A0 = 0; - A0.L = R1.L; - A0.H = R1.H; - A0 = A0 << 0; /* a0 = 0x00000000 */ - R1 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r1, 0x012C003E; - - R1.L = 1; - A0.L = R2.L; - A0.H = R2.H; - A0 = A0 << 1; /* a0 = 0x00000000 */ - R2 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r2, 0x026B3C48; - - R2.L = 15; - A0.L = R3.L; - A0.H = R3.H; - A0 = A0 << 15; /* a0 = 0x00000000 */ - R3 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r3, 0xCF120000; - - R3.L = 31; - A0.L = R4.L; - A0.H = R4.H; - A0 = A0 << 31; /* a0 = 0x00000000 */ - R4 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r4, 0x00000000; - - R4.L = -1; - A0.L = R5.L; - A0.H = R5.H; - A0 = A0 >>> 1; /* a0 = 0x00000000 */ - R5 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r5, 0x28B13579; - - R5.L = -16; - A0 = 0; - A0.L = R6.L; - A0.H = R6.H; - A0 = A0 >>> 16; /* a0 = 0x00000000 */ - R6 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r6, 0x00009176; - - R6.L = -31; - A0.L = R7.L; - A0.H = R7.H; - A0 = A0 >>> 31; /* a0 = 0x00000000 */ - R0 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r0, 0x00000001; - - R7.L = -32; - A0.L = R0.L; - A0.H = R0.H; - .dw 0xC683 // .dw 0xC683 // A0 = A0 >>> 32; - .dw 0x0100 - R7 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r7, 0x00000000; - - imm32 r0, 0x12340000; - imm32 r1, 0x028C003E; - imm32 r2, 0x82159E24; - imm32 r3, 0x82159E24; - imm32 r4, 0xD259E268; - imm32 r5, 0x52E26AF2; - imm32 r6, 0x9226AF36; - imm32 r7, 0xE26BFF86; - - R0.L = 0; - A0 = 0; - A0.L = R1.L; - A0.H = R1.H; - A0 = A0 << 0; /* a0 = 0x00000000 */ - R1 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r1, 0x028C003E; - - R1.L = 1; - A0.L = R2.L; - A0.H = R2.H; - A0 = A0 << 3; /* a0 = 0x00000000 */ - R2 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r2, 0x10ACF120; - - R2.L = 15; - A0.L = R3.L; - A0.H = R3.H; - A0 = A0 << 15; /* a0 = 0x00000000 */ - R3 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r3, 0xCF120000; - - R3.L = 31; - A0.L = R4.L; - A0.H = R4.H; - A0 = A0 << 31; /* a0 = 0x00000000 */ - R4 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r4, 0x00000000; - - R4.L = -1; - A0.L = R5.L; - A0.H = R5.H; - A0 = A0 >> 1; /* a0 = 0x00000000 */ - R5 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r5, 0x29713579; - - R5.L = -16; - A0 = 0; - A0.L = R6.L; - A0.H = R6.H; - A0 = A0 >> 16; /* a0 = 0x00000000 */ - R6 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r6, 0x00009226; - - R6.L = -31; - A0.L = R7.L; - A0.H = R7.H; - A0 = A0 >> 31; /* a0 = 0x00000000 */ - R7 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r7, 0x00000001; - - R7.L = -32; - A0.L = R0.L; - A0.H = R0.H; - .dw 0xC683 - .dw 0x4100 // A0 = A0 >> 32; - R0 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r0, 0x00000000; - - imm32 r0, 0x13340000; - imm32 r1, 0x038C003E; - imm32 r2, 0x83159E24; - imm32 r3, 0x83159E24; - imm32 r4, 0xD359E268; - imm32 r5, 0x53E26AF2; - imm32 r6, 0x9326AF36; - imm32 r7, 0xE36BFF86; - - R0.L = 0; - A0 = 0; - A0.L = R1.L; - A0.H = R1.H; - A0 = ROT A0 BY 0; /* a0 = 0x00000000 */ - R1 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r1, 0x038C003E; - - R1.L = 1; - A0.L = R2.L; - A0.H = R2.H; - A0 = ROT A0 BY 1; /* a0 = 0x00000000 */ - R2 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r2, 0x062B3C48; - - R2.L = 15; - A0.L = R3.L; - A0.H = R3.H; - A0 = ROT A0 BY 15; /* a0 = 0x00000000 */ - R3 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r3, 0xCF120060; - - R3.L = 31; - A0.L = R4.L; - A0.H = R4.H; - A0 = ROT A0 BY 31; /* a0 = 0x00000000 */ - R4 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r4, 0x62B4D678; - - R4.L = -1; - A0.L = R5.L; - A0.H = R5.H; - A0 = ROT A0 BY -1; /* a0 = 0x00000000 */ - R5 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r5, 0x29F13579; - - R5.L = -16; - A0.L = R6.L; - A0.H = R6.H; - A0 = ROT A0 BY -16; /* a0 = 0x00000000 */ - R6 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r6, 0x6C9A9326; - - R6.L = -31; - A0.L = R7.L; - A0.H = R7.H; - A0 = ROT A0 BY -31; /* a0 = 0x00000000 */ - R7 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r7, 0xAFFE1ABD; - - R7.L = -32; - A0.L = R0.L; - A0.H = R0.H; - A0 = ROT A0 BY -32; /* a0 = 0x00000000 */ - R0 = A0.w; /* r5 = 0x00000000 */ - CHECKREG r0, 0x6800018D; - - pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_af.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_af.s deleted file mode 100644 index 1c994f4..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_af.s +++ /dev/null @@ -1,63 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_af/c_dsp32shiftim_af.dsp -# mach: bfin - -.include "testutils.inc" - start - - -// Spec Reference: dsp32shiftimm ashift: ashift - - -imm32 r0, 0xa1230001; -imm32 r1, 0x1b345678; -imm32 r2, 0x23c56789; -imm32 r3, 0x34d6789a; -imm32 r4, 0x85a789ab; -imm32 r5, 0x967c9abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb8912cde; -R0 = R0 << 0; -R1 = R1 << 3; -R2 = R2 << 7; -R3 = R3 << 8; -R4 = R4 << 15; -R5 = R5 << 24; -R6 = R6 << 31; -R7 = R7 << 20; -CHECKREG r0, 0xA1230001; -CHECKREG r1, 0xD9A2B3C0; -CHECKREG r2, 0xE2B3C480; -CHECKREG r3, 0xD6789A00; -CHECKREG r4, 0xC4D58000; -CHECKREG r5, 0xBC000000; -CHECKREG r6, 0x80000000; -CHECKREG r7, 0xCDE00000; - -imm32 r0, 0xa1230001; -imm32 r1, 0x1b345678; -imm32 r2, 0x23c56789; -imm32 r3, 0x34d6789a; -imm32 r4, 0x85a789ab; -imm32 r5, 0x967c9abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb8912cde; -R6 = R0 >>> 1; -R7 = R1 >>> 3; -R0 = R2 >>> 7; -R1 = R3 >>> 8; -R2 = R4 >>> 15; -R3 = R5 >>> 24; -R4 = R6 >>> 31; -R5 = R7 >>> 20; -CHECKREG r0, 0x00478ACF; -CHECKREG r1, 0x0034D678; -CHECKREG r2, 0xFFFF0B4F; -CHECKREG r3, 0xFFFFFF96; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0x00000036; -CHECKREG r6, 0xD0918000; -CHECKREG r7, 0x03668ACF; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s deleted file mode 100644 index 5fdf02a..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s +++ /dev/null @@ -1,63 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_af_s/c_dsp32shiftim_af_s.dsp -# mach: bfin - -.include "testutils.inc" - start - - -// Spec Reference: dsp32shiftimm ashift: ashift saturated - - -imm32 r0, 0x81230001; -imm32 r1, 0x19345678; -imm32 r2, 0x23c56789; -imm32 r3, 0x3ed6789a; -imm32 r4, 0x85d789ab; -imm32 r5, 0x967f9abc; -imm32 r6, 0xa789bbcd; -imm32 r7, 0xb891acde; -R0 = R0 << 0 (S); -R1 = R1 << 3 (S); -R2 = R2 << 7 (S); -R3 = R3 << 8 (S); -R4 = R4 << 15 (S); -R5 = R5 << 24 (S); -R6 = R6 << 31 (S); -R7 = R7 << 20 (S); -CHECKREG r0, 0x81230001; -CHECKREG r1, 0x7FFFFFFF; -CHECKREG r2, 0x7FFFFFFF; -CHECKREG r3, 0x7FFFFFFF; -CHECKREG r4, 0x80000000; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x80000000; - -imm32 r0, 0xa1230001; -imm32 r1, 0x1e345678; -imm32 r2, 0x23f56789; -imm32 r3, 0x34db789a; -imm32 r4, 0x85a7a9ab; -imm32 r5, 0x967c9abc; -imm32 r6, 0xa78dabcd; -imm32 r7, 0xb8914cde; -R6 = R0 >>> 1; -R7 = R1 >>> 3; -R0 = R2 >>> 7; -R1 = R3 >>> 8; -R2 = R4 >>> 15; -R3 = R5 >>> 24; -R4 = R6 >>> 31; -R5 = R7 >>> 20; -CHECKREG r0, 0x0047EACF; -CHECKREG r1, 0x0034DB78; -CHECKREG r2, 0xFFFF0B4F; -CHECKREG r3, 0xFFFFFF96; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0x0000003C; -CHECKREG r6, 0xD0918000; -CHECKREG r7, 0x03C68ACF; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln.s deleted file mode 100644 index e911d3a..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln.s +++ /dev/null @@ -1,406 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_ahalf_ln/c_dsp32shiftim_ahalf_ln.dsp -// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) -# mach: bfin - -.include "testutils.inc" - start - -// Ashift : neg data, count (+)=left (half reg) -// d_lo = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x1000c000; -imm32 r1, 0x1000c001; -imm32 r2, 0x1000c002; -imm32 r3, 0x1000c003; -imm32 r4, 0x1000c004; -imm32 r5, 0x1000c005; -imm32 r6, 0x1000c006; -imm32 r7, 0x1000c007; -R0.L = R0.L << 1; -R1.L = R1.L << 1; -R2.L = R2.L << 1; -R3.L = R3.L << 1; -R4.L = R4.L << 1; -R5.L = R5.L << 1; -R6.L = R6.L << 1; -R7.L = R7.L << 1; -CHECKREG r0, 0x10008000; -CHECKREG r1, 0x10008002; -CHECKREG r2, 0x10008004; -CHECKREG r3, 0x10008006; -CHECKREG r4, 0x10008008; -CHECKREG r5, 0x1000800A; -CHECKREG r6, 0x1000800C; -CHECKREG r7, 0x1000800E; - -imm32 r0, 0x20008001; -imm32 r1, 0x20000001; -imm32 r2, 0x2000d002; -imm32 r3, 0x2000e003; -imm32 r4, 0x2000f004; -imm32 r5, 0x2000c005; -imm32 r6, 0x2000d006; -imm32 r7, 0x2000e007; -R7.L = R0.L << 1; -R6.L = R1.L << 1; -R5.L = R2.L << 1; -R4.L = R3.L << 1; -R3.L = R4.L << 1; -R2.L = R5.L << 1; -R1.L = R6.L << 1; -R0.L = R7.L << 1; - -imm32 r0, 0x3000c001; -imm32 r1, 0x3000d001; -imm32 r2, 0x3000000f; -imm32 r3, 0x3000e003; -imm32 r4, 0x3000f004; -imm32 r5, 0x3000f005; -imm32 r6, 0x3000f006; -imm32 r7, 0x3000f007; -R6.L = R0.L << 12; -R7.L = R1.L << 12; -R5.L = R2.L << 12; -R4.L = R3.L << 12; -R3.L = R4.L << 12; -R2.L = R5.L << 12; -R1.L = R6.L << 12; -R0.L = R7.L << 12; -CHECKREG r1, 0x30000000; -CHECKREG r0, 0x30000000; -CHECKREG r2, 0x30000000; -CHECKREG r3, 0x30000000; -CHECKREG r4, 0x30003000; -CHECKREG r5, 0x3000F000; -CHECKREG r6, 0x30001000; -CHECKREG r7, 0x30001000; - -imm32 r0, 0x40009001; -imm32 r1, 0x4000a001; -imm32 r2, 0x4000b002; -imm32 r3, 0x40000010; -imm32 r4, 0x4000c004; -imm32 r5, 0x4000d005; -imm32 r6, 0x4000e006; -imm32 r7, 0x4000f007; -R5.L = R0.L << 13; -R6.L = R1.L << 13; -R7.L = R2.L << 13; -R0.L = R3.L << 13; -R1.L = R4.L << 13; -R2.L = R5.L << 13; -R3.L = R6.L << 13; -R4.L = R7.L << 13; -CHECKREG r0, 0x40000000; -CHECKREG r1, 0x40008000; -CHECKREG r2, 0x40000000; -CHECKREG r3, 0x40000000; -CHECKREG r4, 0x40000000; -CHECKREG r5, 0x40002000; -CHECKREG r6, 0x40002000; -CHECKREG r7, 0x40004000; - -imm32 r0, 0x00005000; -imm32 r1, 0x00015000; -imm32 r2, 0x00025000; -imm32 r3, 0x00035000; -imm32 r4, 0x00045000; -imm32 r5, 0x00055000; -imm32 r6, 0x00065000; -imm32 r7, 0x00075500; -R0.L = R0.H << 10; -R1.L = R1.H << 10; -R2.L = R2.H << 10; -R3.L = R3.H << 10; -R4.L = R4.H << 10; -R5.L = R5.H << 10; -R6.L = R6.H << 10; -R7.L = R7.H << 10; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010400; -CHECKREG r2, 0x00020800; -CHECKREG r3, 0x00030C00; -CHECKREG r4, 0x00041000; -CHECKREG r5, 0x00051400; -CHECKREG r6, 0x00061800; -CHECKREG r7, 0x00071C00; - -imm32 r0, 0x90010000; -imm32 r1, 0x90010001; -imm32 r2, 0x90020000; -imm32 r3, 0x90030000; -imm32 r4, 0x90040000; -imm32 r5, 0x90050000; -imm32 r6, 0x90060000; -imm32 r7, 0x90070000; -R2.L = R0.H << 11; -R3.L = R1.H << 11; -R4.L = R2.H << 11; -R5.L = R3.H << 11; -R6.L = R4.H << 11; -R7.L = R5.H << 11; -R0.L = R6.H << 11; -R1.L = R7.H << 11; -CHECKREG r0, 0x90013000; -CHECKREG r1, 0x90013800; -CHECKREG r2, 0x90020800; -CHECKREG r3, 0x90030800; -CHECKREG r4, 0x90041000; -CHECKREG r5, 0x90051800; -CHECKREG r6, 0x90062000; -CHECKREG r7, 0x90072800; - - -imm32 r0, 0xa0010600; -imm32 r1, 0xa0010600; -imm32 r2, 0xa002060f; -imm32 r3, 0xa0030600; -imm32 r4, 0xa0040600; -imm32 r5, 0xa0050600; -imm32 r6, 0xa0060600; -imm32 r7, 0xa0070600; -R0.L = R0.H << 12; -R1.L = R1.H << 12; -R2.L = R2.H << 12; -R3.L = R3.H << 12; -R4.L = R4.H << 12; -R5.L = R5.H << 12; -R6.L = R6.H << 12; -R7.L = R7.H << 12; -CHECKREG r0, 0xA0011000; -CHECKREG r1, 0xA0011000; -CHECKREG r2, 0xA0022000; -CHECKREG r3, 0xA0033000; -CHECKREG r4, 0xA0044000; -CHECKREG r5, 0xA0055000; -CHECKREG r6, 0xA0066000; -CHECKREG r7, 0xA0077000; - -imm32 r0, 0xc0010701; -imm32 r1, 0xc0010701; -imm32 r2, 0xc0020702; -imm32 r3, 0xc0030710; -imm32 r4, 0xc0040704; -imm32 r5, 0xc0050705; -imm32 r6, 0xc0060706; -imm32 r7, 0xc0070707; -R0.L = R0.H << 13; -R1.L = R1.H << 13; -R2.L = R2.H << 13; -R3.L = R3.H << 13; -R4.L = R4.H << 13; -R5.L = R5.H << 13; -R6.L = R6.H << 13; -R7.L = R7.H << 13; -CHECKREG r0, 0xC0012000; -CHECKREG r1, 0xC0012000; -CHECKREG r2, 0xC0024000; -CHECKREG r3, 0xC0036000; -CHECKREG r4, 0xC0048000; -CHECKREG r5, 0xC005A000; -CHECKREG r6, 0xC006C000; -CHECKREG r7, 0xC007E000; - -imm32 r0, 0x00008000; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.H = R0.L << 0; -R1.H = R1.L << 1; -R2.H = R2.L << 2; -R3.H = R3.L << 3; -R4.H = R4.L << 4; -R5.H = R5.L << 5; -R6.H = R6.L << 6; -R7.H = R7.L << 7; -CHECKREG r0, 0x80008000; -CHECKREG r1, 0x00028001; -CHECKREG r2, 0x00088002; -CHECKREG r3, 0x00188003; -CHECKREG r4, 0x00408004; -CHECKREG r5, 0x00A08005; -CHECKREG r6, 0x01808006; -CHECKREG r7, 0x03808007; - -imm32 r0, 0x0000d001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000d002; -imm32 r3, 0x0000d003; -imm32 r4, 0x0000d004; -imm32 r5, 0x0000d005; -imm32 r6, 0x0000d006; -imm32 r7, 0x0000d007; -R2.H = R0.L << 8; -R3.H = R1.L << 9; -R4.H = R2.L << 10; -R5.H = R3.L << 11; -R6.H = R4.L << 12; -R7.H = R5.L << 13; -R0.H = R6.L << 14; -R1.H = R7.L << 15; -CHECKREG r0, 0x8000D001; -CHECKREG r1, 0x80000001; -CHECKREG r2, 0x0100D002; -CHECKREG r3, 0x0200D003; -CHECKREG r4, 0x0800D004; -CHECKREG r5, 0x1800D005; -CHECKREG r6, 0x4000D006; -CHECKREG r7, 0xA000D007; - -imm32 r0, 0x0000e001; -imm32 r1, 0x0000e001; -imm32 r2, 0x0000000f; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000e004; -imm32 r5, 0x0000e005; -imm32 r6, 0x0000e006; -imm32 r7, 0x0000e007; -R0.H = R0.L << 12; -R1.H = R1.L << 12; -R2.H = R2.L << 12; -R3.H = R3.L << 12; -R4.H = R4.L << 12; -R5.H = R5.L << 12; -R6.H = R6.L << 12; -R7.H = R7.L << 12; -CHECKREG r0, 0x1000E001; -CHECKREG r1, 0x1000E001; -CHECKREG r2, 0xF000000F; -CHECKREG r3, 0x3000E003; -CHECKREG r4, 0x4000E004; -CHECKREG r5, 0x5000E005; -CHECKREG r6, 0x6000E006; -CHECKREG r7, 0x7000E007; - -imm32 r0, 0x0000f001; -imm32 r1, 0x0000f001; -imm32 r2, 0x0000f002; -imm32 r3, 0x00000010; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000f005; -imm32 r6, 0x0000f006; -imm32 r7, 0x0000f007; -R5.H = R0.L << 13; -R6.H = R1.L << 13; -R7.H = R2.L << 13; -R0.H = R3.L << 13; -R1.H = R4.L << 13; -R2.H = R5.L << 13; -R3.H = R6.L << 13; -R4.H = R7.L << 13; -CHECKREG r0, 0x0000F001; -CHECKREG r1, 0x8000F001; -CHECKREG r2, 0xA000F002; -CHECKREG r3, 0xC0000010; -CHECKREG r4, 0xE000F004; -CHECKREG r5, 0x2000F005; -CHECKREG r6, 0x2000F006; -CHECKREG r7, 0x4000F007; - -// d_lo = ashift (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x90000000; -imm32 r1, 0x90010000; -imm32 r2, 0x90020000; -imm32 r3, 0x90030000; -imm32 r4, 0x90040000; -imm32 r5, 0x90050000; -imm32 r6, 0x90060000; -imm32 r7, 0x90070000; -R4.H = R0.H << 10; -R5.H = R1.H << 10; -R6.H = R2.H << 10; -R7.H = R3.H << 10; -R0.H = R4.H << 10; -R1.H = R5.H << 10; -R2.H = R6.H << 10; -R3.H = R7.H << 10; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x04000000; -CHECKREG r6, 0x08000000; -CHECKREG r7, 0x0C000000; - -imm32 r0, 0xa0010000; -imm32 r1, 0x00010001; -imm32 r2, 0xa0020000; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R7.H = R0.H << 11; -R0.H = R1.H << 11; -R1.H = R2.H << 11; -R2.H = R3.H << 11; -R3.H = R4.H << 11; -R4.H = R5.H << 11; -R5.H = R6.H << 11; -R6.H = R7.H << 11; -CHECKREG r0, 0x08000000; -CHECKREG r1, 0x10000001; -CHECKREG r2, 0x18000000; -CHECKREG r3, 0x20000000; -CHECKREG r4, 0x28000000; -CHECKREG r5, 0x30000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x08000000; - - -imm32 r0, 0xb0010000; -imm32 r1, 0xb0010000; -imm32 r2, 0xb002000f; -imm32 r3, 0xb0030000; -imm32 r4, 0xb0040000; -imm32 r5, 0xb0050000; -imm32 r6, 0xb0060000; -imm32 r7, 0xb0070000; -R6.H = R0.H << 12; -R7.H = R1.H << 12; -R0.H = R2.H << 12; -R1.H = R3.H << 12; -R2.H = R4.H << 12; -R3.H = R5.H << 12; -R4.H = R6.H << 12; -R5.H = R7.H << 12; -CHECKREG r0, 0x20000000; -CHECKREG r1, 0x30000000; -CHECKREG r2, 0x4000000F; -CHECKREG r3, 0x50000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x10000000; -CHECKREG r7, 0x10000000; - -imm32 r0, 0xd0010000; -imm32 r1, 0xd0010000; -imm32 r2, 0xd0020000; -imm32 r3, 0xd0030010; -imm32 r4, 0xd0040000; -imm32 r5, 0xd0050000; -imm32 r6, 0xd0060000; -imm32 r7, 0xd0070000; -R5.H = R0.H << 3; -R6.H = R1.H << 3; -R7.H = R2.H << 3; -R0.H = R3.H << 3; -R1.H = R4.H << 3; -R2.H = R5.H << 3; -R3.H = R6.H << 3; -R4.H = R7.H << 3; -CHECKREG r0, 0x80180000; -CHECKREG r1, 0x80200000; -CHECKREG r2, 0x00400000; -CHECKREG r3, 0x00400010; -CHECKREG r4, 0x00800000; -CHECKREG r5, 0x80080000; -CHECKREG r6, 0x80080000; -CHECKREG r7, 0x80100000; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln_s.s deleted file mode 100644 index aa28f3f..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln_s.s +++ /dev/null @@ -1,408 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_ahalf_ln_s/c_dsp32shiftim_ahalf_ln_s.dsp -// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated -# mach: bfin - -.include "testutils.inc" - start - - - -// Ashift : neg data, count (+)=left (half reg) -// d_lo = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x1000c000; -imm32 r1, 0x1000c001; -imm32 r2, 0x1000c002; -imm32 r3, 0x1000c003; -imm32 r4, 0x1000c004; -imm32 r5, 0x1000c005; -imm32 r6, 0x1000c006; -imm32 r7, 0x1000c007; -R0.L = R0.L << 1 (S); -R1.L = R1.L << 1 (S); -R2.L = R2.L << 1 (S); -R3.L = R3.L << 1 (S); -R4.L = R4.L << 1 (S); -R5.L = R5.L << 1 (S); -R6.L = R6.L << 1 (S); -R7.L = R7.L << 1 (S); -CHECKREG r0, 0x10008000; -CHECKREG r1, 0x10008002; -CHECKREG r2, 0x10008004; -CHECKREG r3, 0x10008006; -CHECKREG r4, 0x10008008; -CHECKREG r5, 0x1000800A; -CHECKREG r6, 0x1000800C; -CHECKREG r7, 0x1000800E; - -imm32 r0, 0x20008001; -imm32 r1, 0x20000001; -imm32 r2, 0x2000d002; -imm32 r3, 0x2000e003; -imm32 r4, 0x2000f004; -imm32 r5, 0x2000c005; -imm32 r6, 0x2000d006; -imm32 r7, 0x2000e007; -R7.L = R0.L << 1 (S); -R6.L = R1.L << 1 (S); -R5.L = R2.L << 1 (S); -R4.L = R3.L << 1 (S); -R3.L = R4.L << 1 (S); -R2.L = R5.L << 1 (S); -R1.L = R6.L << 1 (S); -R0.L = R7.L << 1 (S); - -imm32 r0, 0x3000c001; -imm32 r1, 0x3000d001; -imm32 r2, 0x3000000f; -imm32 r3, 0x3000e003; -imm32 r4, 0x3000f004; -imm32 r5, 0x3000f005; -imm32 r6, 0x3000f006; -imm32 r7, 0x3000f007; -R6.L = R0.L << 12 (S); -R7.L = R1.L << 12 (S); -R5.L = R2.L << 12 (S); -R4.L = R3.L << 12 (S); -R3.L = R4.L << 12 (S); -R2.L = R5.L << 12 (S); -R1.L = R6.L << 12 (S); -R0.L = R7.L << 12 (S); -CHECKREG r1, 0x30008000; -CHECKREG r0, 0x30008000; -CHECKREG r2, 0x30007FFF; -CHECKREG r3, 0x30008000; -CHECKREG r4, 0x30008000; -CHECKREG r5, 0x30007FFF; -CHECKREG r6, 0x30008000; -CHECKREG r7, 0x30008000; - -imm32 r0, 0x40009001; -imm32 r1, 0x4000a001; -imm32 r2, 0x4000b002; -imm32 r3, 0x40000010; -imm32 r4, 0x4000c004; -imm32 r5, 0x4000d005; -imm32 r6, 0x4000e006; -imm32 r7, 0x4000f007; -R5.L = R0.L << 13 (S); -R6.L = R1.L << 13 (S); -R7.L = R2.L << 13 (S); -R0.L = R3.L << 13 (S); -R1.L = R4.L << 13 (S); -R2.L = R5.L << 13 (S); -R3.L = R6.L << 13 (S); -R4.L = R7.L << 13 (S); -CHECKREG r0, 0x40007FFF; -CHECKREG r1, 0x40008000; -CHECKREG r2, 0x40008000; -CHECKREG r3, 0x40008000; -CHECKREG r4, 0x40008000; -CHECKREG r5, 0x40008000; -CHECKREG r6, 0x40008000; -CHECKREG r7, 0x40008000; - -imm32 r0, 0x00005000; -imm32 r1, 0x00015000; -imm32 r2, 0x00025000; -imm32 r3, 0x00035000; -imm32 r4, 0x00045000; -imm32 r5, 0x00055000; -imm32 r6, 0x00065000; -imm32 r7, 0x00075500; -R0.L = R0.H << 10 (S); -R1.L = R1.H << 10 (S); -R2.L = R2.H << 10 (S); -R3.L = R3.H << 10 (S); -R4.L = R4.H << 10 (S); -R5.L = R5.H << 10 (S); -R6.L = R6.H << 10 (S); -R7.L = R7.H << 10 (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010400; -CHECKREG r2, 0x00020800; -CHECKREG r3, 0x00030C00; -CHECKREG r4, 0x00041000; -CHECKREG r5, 0x00051400; -CHECKREG r6, 0x00061800; -CHECKREG r7, 0x00071C00; - -imm32 r0, 0x90010000; -imm32 r1, 0x90010001; -imm32 r2, 0x90020000; -imm32 r3, 0x90030000; -imm32 r4, 0x90040000; -imm32 r5, 0x90050000; -imm32 r6, 0x90060000; -imm32 r7, 0x90070000; -R2.L = R0.H << 11 (S); -R3.L = R1.H << 11 (S); -R4.L = R2.H << 11 (S); -R5.L = R3.H << 11 (S); -R6.L = R4.H << 11 (S); -R7.L = R5.H << 11 (S); -R0.L = R6.H << 11 (S); -R1.L = R7.H << 11 (S); -CHECKREG r0, 0x90018000; -CHECKREG r1, 0x90018000; -CHECKREG r2, 0x90028000; -CHECKREG r3, 0x90038000; -CHECKREG r4, 0x90048000; -CHECKREG r5, 0x90058000; -CHECKREG r6, 0x90068000; -CHECKREG r7, 0x90078000; - - -imm32 r0, 0xa0010600; -imm32 r1, 0xa0010600; -imm32 r2, 0xa002060f; -imm32 r3, 0xa0030600; -imm32 r4, 0xa0040600; -imm32 r5, 0xa0050600; -imm32 r6, 0xa0060600; -imm32 r7, 0xa0070600; -R0.L = R0.H << 12 (S); -R1.L = R1.H << 12 (S); -R2.L = R2.H << 12 (S); -R3.L = R3.H << 12 (S); -R4.L = R4.H << 12 (S); -R5.L = R5.H << 12 (S); -R6.L = R6.H << 12 (S); -R7.L = R7.H << 12 (S); -CHECKREG r0, 0xA0018000; -CHECKREG r1, 0xA0018000; -CHECKREG r2, 0xA0028000; -CHECKREG r3, 0xA0038000; -CHECKREG r4, 0xA0048000; -CHECKREG r5, 0xA0058000; -CHECKREG r6, 0xA0068000; -CHECKREG r7, 0xA0078000; - -imm32 r0, 0xc0010701; -imm32 r1, 0xc0010701; -imm32 r2, 0xc0020702; -imm32 r3, 0xc0030710; -imm32 r4, 0xc0040704; -imm32 r5, 0xc0050705; -imm32 r6, 0xc0060706; -imm32 r7, 0xc0070707; -R0.L = R0.H << 13 (S); -R1.L = R1.H << 13 (S); -R2.L = R2.H << 13 (S); -R3.L = R3.H << 13 (S); -R4.L = R4.H << 13 (S); -R5.L = R5.H << 13 (S); -R6.L = R6.H << 13 (S); -R7.L = R7.H << 13 (S); -CHECKREG r0, 0xC0018000; -CHECKREG r1, 0xC0018000; -CHECKREG r2, 0xC0028000; -CHECKREG r3, 0xC0038000; -CHECKREG r4, 0xC0048000; -CHECKREG r5, 0xC0058000; -CHECKREG r6, 0xC0068000; -CHECKREG r7, 0xC0078000; - -imm32 r0, 0x00008000; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.H = R0.L << 0 (S); -R1.H = R1.L << 1 (S); -R2.H = R2.L << 2 (S); -R3.H = R3.L << 3 (S); -R4.H = R4.L << 4 (S); -R5.H = R5.L << 5 (S); -R6.H = R6.L << 6 (S); -R7.H = R7.L << 7 (S); -CHECKREG r0, 0x80008000; -CHECKREG r1, 0x80008001; -CHECKREG r2, 0x80008002; -CHECKREG r3, 0x80008003; -CHECKREG r4, 0x80008004; -CHECKREG r5, 0x80008005; -CHECKREG r6, 0x80008006; -CHECKREG r7, 0x80008007; - -imm32 r0, 0x0000d001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000d002; -imm32 r3, 0x0000d003; -imm32 r4, 0x0000d004; -imm32 r5, 0x0000d005; -imm32 r6, 0x0000d006; -imm32 r7, 0x0000d007; -R2.H = R0.L << 8 (S); -R3.H = R1.L << 9 (S); -R4.H = R2.L << 10 (S); -R5.H = R3.L << 11 (S); -R6.H = R4.L << 12 (S); -R7.H = R5.L << 13 (S); -R0.H = R6.L << 14 (S); -R1.H = R7.L << 15 (S); -CHECKREG r0, 0x8000D001; -CHECKREG r1, 0x80000001; -CHECKREG r2, 0x8000D002; -CHECKREG r3, 0x0200D003; -CHECKREG r4, 0x8000D004; -CHECKREG r5, 0x8000D005; -CHECKREG r6, 0x8000D006; -CHECKREG r7, 0x8000D007; - -imm32 r0, 0x0000e001; -imm32 r1, 0x0000e001; -imm32 r2, 0x0000000f; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000e004; -imm32 r5, 0x0000e005; -imm32 r6, 0x0000e006; -imm32 r7, 0x0000e007; -R0.H = R0.L << 12 (S); -R1.H = R1.L << 12 (S); -R2.H = R2.L << 12 (S); -R3.H = R3.L << 12 (S); -R4.H = R4.L << 12 (S); -R5.H = R5.L << 12 (S); -R6.H = R6.L << 12 (S); -R7.H = R7.L << 12 (S); -CHECKREG r0, 0x8000E001; -CHECKREG r1, 0x8000E001; -CHECKREG r2, 0x7FFF000F; -CHECKREG r3, 0x8000E003; -CHECKREG r4, 0x8000E004; -CHECKREG r5, 0x8000E005; -CHECKREG r6, 0x8000E006; -CHECKREG r7, 0x8000E007; - -imm32 r0, 0x0000f001; -imm32 r1, 0x0000f001; -imm32 r2, 0x0000f002; -imm32 r3, 0x00000010; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000f005; -imm32 r6, 0x0000f006; -imm32 r7, 0x0000f007; -R5.H = R0.L << 13 (S); -R6.H = R1.L << 13 (S); -R7.H = R2.L << 13 (S); -R0.H = R3.L << 13 (S); -R1.H = R4.L << 13 (S); -R2.H = R5.L << 13 (S); -R3.H = R6.L << 13 (S); -R4.H = R7.L << 13 (S); -CHECKREG r0, 0x7FFFF001; -CHECKREG r1, 0x8000F001; -CHECKREG r2, 0x8000F002; -CHECKREG r3, 0x80000010; -CHECKREG r4, 0x8000F004; -CHECKREG r5, 0x8000F005; -CHECKREG r6, 0x8000F006; -CHECKREG r7, 0x8000F007; - -// d_lo = ashift (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x90000000; -imm32 r1, 0x90010000; -imm32 r2, 0x90020000; -imm32 r3, 0x90030000; -imm32 r4, 0x90040000; -imm32 r5, 0x90050000; -imm32 r6, 0x90060000; -imm32 r7, 0x90070000; -R4.H = R0.H << 10 (S); -R5.H = R1.H << 10 (S); -R6.H = R2.H << 10 (S); -R7.H = R3.H << 10 (S); -R0.H = R4.H << 10 (S); -R1.H = R5.H << 10 (S); -R2.H = R6.H << 10 (S); -R3.H = R7.H << 10 (S); -CHECKREG r0, 0x80000000; -CHECKREG r1, 0x80000000; -CHECKREG r2, 0x80000000; -CHECKREG r3, 0x80000000; -CHECKREG r4, 0x80000000; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x80000000; - -imm32 r0, 0xa0010000; -imm32 r1, 0x00010001; -imm32 r2, 0xa0020000; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R7.H = R0.H << 11 (S); -R0.H = R1.H << 11 (S); -R1.H = R2.H << 11 (S); -R2.H = R3.H << 11 (S); -R3.H = R4.H << 11 (S); -R4.H = R5.H << 11 (S); -R5.H = R6.H << 11 (S); -R6.H = R7.H << 11 (S); -CHECKREG r0, 0x08000000; -CHECKREG r1, 0x80000001; -CHECKREG r2, 0x80000000; -CHECKREG r3, 0x80000000; -CHECKREG r4, 0x80000000; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x80000000; - - -imm32 r0, 0xb0010000; -imm32 r1, 0xb0010000; -imm32 r2, 0xb002000f; -imm32 r3, 0xb0030000; -imm32 r4, 0xb0040000; -imm32 r5, 0xb0050000; -imm32 r6, 0xb0060000; -imm32 r7, 0xb0070000; -R6.H = R0.H << 12 (S); -R7.H = R1.H << 12 (S); -R0.H = R2.H << 12 (S); -R1.H = R3.H << 12 (S); -R2.H = R4.H << 12 (S); -R3.H = R5.H << 12 (S); -R4.H = R6.H << 12 (S); -R5.H = R7.H << 12 (S); -CHECKREG r0, 0x80000000; -CHECKREG r1, 0x80000000; -CHECKREG r2, 0x8000000F; -CHECKREG r3, 0x80000000; -CHECKREG r4, 0x80000000; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x80000000; - -imm32 r0, 0xd0010000; -imm32 r1, 0xd0010000; -imm32 r2, 0xd0020000; -imm32 r3, 0xd0030010; -imm32 r4, 0xd0040000; -imm32 r5, 0xd0050000; -imm32 r6, 0xd0060000; -imm32 r7, 0xd0070000; -R5.H = R0.H << 3 (S); -R6.H = R1.H << 3 (S); -R7.H = R2.H << 3 (S); -R0.H = R3.H << 3 (S); -R1.H = R4.H << 3 (S); -R2.H = R5.H << 3 (S); -R3.H = R6.H << 3 (S); -R4.H = R7.H << 3 (S); -CHECKREG r0, 0x80000000; -CHECKREG r1, 0x80000000; -CHECKREG r2, 0x80000000; -CHECKREG r3, 0x80000010; -CHECKREG r4, 0x80000000; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x80000000; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp.s deleted file mode 100644 index 44e8882..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp.s +++ /dev/null @@ -1,418 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_ahalf_lp/c_dsp32shiftim_ahalf_lp.dsp -// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) -# mach: bfin - -.include "testutils.inc" - start - -// Ashift : positive data, count (+)=left (half reg) -// d_lo = ashift (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x01010100; -imm32 r1, 0x01020101; -imm32 r2, 0x01030102; -imm32 r3, 0x01040103; -imm32 r4, 0x01050104; -imm32 r5, 0x01060105; -imm32 r6, 0x01070106; -imm32 r7, 0x01080107; -R0.L = R0.L << 0; -R1.L = R1.L << 1; -R2.L = R2.L << 2; -R3.L = R3.L << 3; -R4.L = R4.L << 4; -R5.L = R5.L << 5; -R6.L = R6.L << 6; -R7.L = R7.L << 7; -CHECKREG r0, 0x01010100; -CHECKREG r1, 0x01020202; -CHECKREG r2, 0x01030408; -CHECKREG r3, 0x01040818; -CHECKREG r4, 0x01051040; -CHECKREG r5, 0x010620A0; -CHECKREG r6, 0x01074180; -CHECKREG r7, 0x01088380; - -imm32 r0, 0x00090201; -imm32 r1, 0x00100201; -imm32 r2, 0x00110202; -imm32 r3, 0x00120203; -imm32 r4, 0x00130204; -imm32 r5, 0x00140205; -imm32 r6, 0x00150206; -imm32 r7, 0x00160207; -R7.L = R0.L << 8; -R6.L = R1.L << 9; -R5.L = R2.L << 10; -R4.L = R3.L << 11; -R3.L = R4.L << 12; -R2.L = R5.L << 13; -R1.L = R6.L << 14; -R0.L = R7.L << 15; -CHECKREG r1, 0x00100000; -CHECKREG r0, 0x00090000; -CHECKREG r2, 0x00110000; -CHECKREG r3, 0x00120000; -CHECKREG r4, 0x00131800; -CHECKREG r5, 0x00140800; -CHECKREG r6, 0x00150200; -CHECKREG r7, 0x00160100; - - -imm32 r0, 0x00170401; -imm32 r1, 0x00180401; -imm32 r2, 0x0019040f; -imm32 r3, 0x00200403; -imm32 r4, 0x00210404; -imm32 r5, 0x00220405; -imm32 r6, 0x00230406; -imm32 r7, 0x00244407; -R6.L = R0.L << 15; -R5.L = R1.L << 15; -R4.L = R2.L << 15; -R3.L = R3.L << 15; -R2.L = R4.L << 15; -R1.L = R5.L << 15; -R0.L = R6.L << 15; -R7.L = R7.L << 15; -CHECKREG r0, 0x00170000; -CHECKREG r1, 0x00180000; -CHECKREG r2, 0x00190000; -CHECKREG r3, 0x00208000; -CHECKREG r4, 0x00218000; -CHECKREG r5, 0x00228000; -CHECKREG r6, 0x00238000; -CHECKREG r7, 0x00248000; - -imm32 r0, 0x00005001; -imm32 r1, 0x00005001; -imm32 r2, 0x00005002; -imm32 r3, 0x00005010; -imm32 r4, 0x00005004; -imm32 r5, 0x00005005; -imm32 r6, 0x00000506; -imm32 r7, 0x00000507; -R5.L = R0.L << 13; -R6.L = R1.L << 13; -R7.L = R2.L << 13; -R0.L = R3.L << 13; -R1.L = R4.L << 13; -R2.L = R5.L << 13; -R3.L = R6.L << 13; -R4.L = R7.L << 13; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00008000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00002000; -CHECKREG r6, 0x00002000; -CHECKREG r7, 0x00004000; - -// RHx by RLx -imm32 r0, 0x00006010; -imm32 r1, 0x00016020; -imm32 r2, 0x00026030; -imm32 r3, 0x00036040; -imm32 r4, 0x00046050; -imm32 r5, 0x00056060; -imm32 r6, 0x00066070; -imm32 r7, 0x00076080; -R0.L = R0.H << 10; -R1.L = R1.H << 10; -R2.L = R2.H << 10; -R3.L = R3.H << 10; -R4.L = R4.H << 10; -R5.L = R5.H << 10; -R6.L = R6.H << 10; -R7.L = R7.H << 10; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010400; -CHECKREG r2, 0x00020800; -CHECKREG r3, 0x00030C00; -CHECKREG r4, 0x00041000; -CHECKREG r5, 0x00051400; -CHECKREG r6, 0x00061800; -CHECKREG r7, 0x00071C00; - -imm32 r0, 0x00010090; -imm32 r1, 0x00010111; -imm32 r2, 0x00020120; -imm32 r3, 0x00030130; -imm32 r4, 0x00040140; -imm32 r5, 0x00050150; -imm32 r6, 0x00060160; -imm32 r7, 0x00070170; -R1.L = R0.H << 1; -R2.L = R1.H << 1; -R3.L = R2.H << 1; -R4.L = R3.H << 1; -R5.L = R4.H << 1; -R6.L = R5.H << 1; -R7.L = R6.H << 1; -R0.L = R7.H << 1; -CHECKREG r1, 0x00010002; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030004; -CHECKREG r4, 0x00040006; -CHECKREG r5, 0x00050008; -CHECKREG r6, 0x0006000A; -CHECKREG r7, 0x0007000C; -CHECKREG r0, 0x0001000E; - - -imm32 r0, 0x0a010000; -imm32 r1, 0x0b010000; -imm32 r2, 0x0c02000f; -imm32 r3, 0x0d030000; -imm32 r4, 0x0e040000; -imm32 r5, 0x0f050000; -imm32 r6, 0x01060000; -imm32 r7, 0x02070000; -R2.L = R0.H << 12; -R3.L = R1.H << 12; -R4.L = R2.H << 12; -R5.L = R3.H << 12; -R6.L = R4.H << 12; -R7.L = R5.H << 12; -R0.L = R6.H << 12; -R1.L = R7.H << 12; -CHECKREG r0, 0x0A016000; -CHECKREG r1, 0x0B017000; -CHECKREG r2, 0x0C021000; -CHECKREG r3, 0x0D031000; -CHECKREG r4, 0x0E042000; -CHECKREG r5, 0x0F053000; -CHECKREG r6, 0x01064000; -CHECKREG r7, 0x02075000; - -imm32 r0, 0x01010001; -imm32 r1, 0x02010001; -imm32 r2, 0x03020002; -imm32 r3, 0x04030010; -imm32 r4, 0x05040004; -imm32 r5, 0x06050005; -imm32 r6, 0x07060006; -imm32 r7, 0x08070007; -R3.L = R0.H << 13; -R4.L = R1.H << 13; -R5.L = R2.H << 13; -R6.L = R3.H << 13; -R7.L = R4.H << 13; -R0.L = R5.H << 13; -R1.L = R6.H << 13; -R2.L = R7.H << 13; -CHECKREG r0, 0x0101A000; -CHECKREG r1, 0x0201C000; -CHECKREG r2, 0x0302E000; -CHECKREG r3, 0x04032000; -CHECKREG r4, 0x05042000; -CHECKREG r5, 0x06054000; -CHECKREG r6, 0x07066000; -CHECKREG r7, 0x08078000; - -// RLx by RLx -imm32 r0, 0xa0000400; -imm32 r1, 0xbb000401; -imm32 r2, 0xc0000402; -imm32 r3, 0xd0000403; -imm32 r4, 0xe0000404; -imm32 r5, 0xf0000405; -imm32 r6, 0x10000406; -imm32 r7, 0x20000407; -R0.H = R0.L << 14; -R1.H = R1.L << 14; -R2.H = R2.L << 14; -R3.H = R3.L << 14; -R4.H = R4.L << 14; -R5.H = R5.L << 14; -R6.H = R6.L << 14; -R7.H = R7.L << 14; -CHECKREG r0, 0x00000400; -CHECKREG r1, 0x40000401; -CHECKREG r2, 0x80000402; -CHECKREG r3, 0xC0000403; -CHECKREG r4, 0x00000404; -CHECKREG r5, 0x40000405; -CHECKREG r6, 0x80000406; -CHECKREG r7, 0xC0000407; - -imm32 r0, 0x0a000001; -imm32 r1, 0x0b000001; -imm32 r2, 0x0cd00002; -imm32 r3, 0x0d000003; -imm32 r4, 0x0e000004; -imm32 r5, 0x0f000005; -imm32 r6, 0x03000006; -imm32 r7, 0x04000007; -R1.H = R0.L << 15; -R2.H = R1.L << 15; -R3.H = R2.L << 15; -R4.H = R3.L << 15; -R5.H = R4.L << 15; -R6.H = R5.L << 15; -R7.H = R6.L << 15; -R0.H = R7.L << 15; -CHECKREG r1, 0x80000001; -CHECKREG r2, 0x80000002; -CHECKREG r3, 0x00000003; -CHECKREG r4, 0x80000004; -CHECKREG r5, 0x00000005; -CHECKREG r6, 0x80000006; -CHECKREG r7, 0x00000007; -CHECKREG r0, 0x80000001; - - -imm32 r0, 0x10000001; -imm32 r1, 0x02000001; -imm32 r2, 0x0300000f; -imm32 r3, 0x04000003; -imm32 r4, 0x05000004; -imm32 r5, 0x06000005; -imm32 r6, 0x07000006; -imm32 r7, 0x00800007; -R2.H = R0.L << 2; -R3.H = R1.L << 2; -R4.H = R2.L << 2; -R5.H = R3.L << 2; -R6.H = R4.L << 2; -R7.H = R5.L << 2; -R0.H = R6.L << 2; -R1.H = R7.L << 2; -CHECKREG r0, 0x00180001; -CHECKREG r1, 0x001C0001; -CHECKREG r2, 0x0004000F; -CHECKREG r3, 0x00040003; -CHECKREG r4, 0x003C0004; -CHECKREG r5, 0x000C0005; -CHECKREG r6, 0x00100006; -CHECKREG r7, 0x00140007; - -imm32 r0, 0x00000801; -imm32 r1, 0x00000801; -imm32 r2, 0x00000802; -imm32 r3, 0x00000810; -imm32 r4, 0x00000804; -imm32 r5, 0x00000805; -imm32 r6, 0x00000806; -imm32 r7, 0x00000807; -R3.H = R0.L << 3; -R4.H = R1.L << 3; -R5.H = R2.L << 3; -R6.H = R3.L << 3; -R7.H = R4.L << 3; -R0.H = R5.L << 3; -R1.H = R6.L << 3; -R2.H = R7.L << 3; -CHECKREG r0, 0x40280801; -CHECKREG r1, 0x40300801; -CHECKREG r2, 0x40380802; -CHECKREG r3, 0x40080810; -CHECKREG r4, 0x40080804; -CHECKREG r5, 0x40100805; -CHECKREG r6, 0x40800806; -CHECKREG r7, 0x40200807; - -// RHx by RLx -imm32 r0, 0x00000400; -imm32 r1, 0x00010500; -imm32 r2, 0x00020060; -imm32 r3, 0x00030070; -imm32 r4, 0x00040800; -imm32 r5, 0x00050090; -imm32 r6, 0x00060d00; -imm32 r7, 0x00070a00; -R7.H = R0.H << 10; -R6.H = R1.H << 10; -R5.H = R2.H << 10; -R4.H = R3.H << 10; -R3.H = R4.H << 10; -R2.H = R5.H << 10; -R1.H = R6.H << 10; -R0.H = R7.H << 10; -CHECKREG r1, 0x00000500; -CHECKREG r2, 0x00000060; -CHECKREG r3, 0x00000070; -CHECKREG r4, 0x0C000800; -CHECKREG r5, 0x08000090; -CHECKREG r6, 0x04000D00; -CHECKREG r7, 0x00000A00; -CHECKREG r0, 0x00000400; - -imm32 r0, 0x00010000; -imm32 r1, 0x00010001; -imm32 r2, 0x00020001; -imm32 r3, 0x00030002; -imm32 r4, 0x00040003; -imm32 r5, 0x00050004; -imm32 r6, 0x00060005; -imm32 r7, 0x00070006; -R6.H = R0.H << 11; -R5.H = R1.H << 11; -R4.H = R2.H << 11; -R3.H = R3.H << 11; -R2.H = R4.H << 11; -R1.H = R5.H << 11; -R7.H = R6.H << 11; -R0.H = R7.H << 11; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x18000002; -CHECKREG r4, 0x10000003; -CHECKREG r5, 0x08000004; -CHECKREG r6, 0x08000005; -CHECKREG r7, 0x00000006; -CHECKREG r0, 0x00000000; - - -imm32 r0, 0x00010060; -imm32 r1, 0x00010060; -imm32 r2, 0x0002006f; -imm32 r3, 0x00030060; -imm32 r4, 0x00040060; -imm32 r5, 0x00050060; -imm32 r6, 0x00060060; -imm32 r7, 0x00070060; -R4.H = R0.H << 12; -R5.H = R1.H << 12; -R6.H = R2.H << 12; -R7.H = R3.H << 12; -R0.H = R4.H << 12; -R1.H = R5.H << 12; -R2.H = R6.H << 12; -R3.H = R7.H << 12; -CHECKREG r0, 0x00000060; -CHECKREG r1, 0x00000060; -CHECKREG r2, 0x0000006F; -CHECKREG r3, 0x00000060; -CHECKREG r4, 0x10000060; -CHECKREG r5, 0x10000060; -CHECKREG r6, 0x20000060; -CHECKREG r7, 0x30000060; - -imm32 r0, 0x12010070; -imm32 r1, 0x23010070; -imm32 r2, 0x34020070; -imm32 r3, 0x45030070; -imm32 r4, 0x56040070; -imm32 r5, 0x67050070; -imm32 r6, 0x78060070; -imm32 r7, 0x09070070; -R4.H = R0.H << 3; -R5.H = R1.H << 3; -R6.H = R2.H << 3; -R7.H = R3.H << 3; -R0.H = R4.H << 3; -R1.H = R5.H << 3; -R2.H = R6.H << 3; -R3.H = R7.H << 3; -CHECKREG r0, 0x80400070; -CHECKREG r1, 0xC0400070; -CHECKREG r2, 0x00800070; -CHECKREG r3, 0x40C00070; -CHECKREG r4, 0x90080070; -CHECKREG r5, 0x18080070; -CHECKREG r6, 0xA0100070; -CHECKREG r7, 0x28180070; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp_s.s deleted file mode 100644 index 45b2a7e..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp_s.s +++ /dev/null @@ -1,415 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_ahalf_lp_s/c_dsp32shiftim_ahalf_lp_s.dsp -// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00100a00; -imm32 r1, 0x00100a01; -imm32 r2, 0x00100a02; -imm32 r3, 0x00100a03; -imm32 r4, 0x00100a04; -imm32 r5, 0x00100a05; -imm32 r6, 0x00100a06; -imm32 r7, 0x00100a07; -R7.L = R0.L << 0 (S); -R0.L = R1.L << 1 (S); -R1.L = R2.L << 2 (S); -R2.L = R3.L << 3 (S); -R3.L = R4.L << 4 (S); -R4.L = R5.L << 5 (S); -R5.L = R6.L << 6 (S); -R6.L = R7.L << 7 (S); -CHECKREG r1, 0x00102808; -CHECKREG r0, 0x00101402; -CHECKREG r2, 0x00105018; -CHECKREG r3, 0x00107FFF; -CHECKREG r4, 0x00107FFF; -CHECKREG r5, 0x00107FFF; -CHECKREG r6, 0x00107FFF; -CHECKREG r7, 0x00100A00; - -imm32 r0, 0x00200018; -imm32 r1, 0x00200019; -imm32 r2, 0x0020001a; -imm32 r3, 0x0020001b; -imm32 r4, 0x0020001c; -imm32 r5, 0x0020001d; -imm32 r6, 0x0020001e; -imm32 r7, 0x0020001f; -R2.L = R0.L << 8 (S); -R3.L = R1.L << 9 (S); -R4.L = R2.L << 10 (S); -R5.L = R3.L << 11 (S); -R6.L = R4.L << 12 (S); -R7.L = R5.L << 13 (S); -R0.L = R6.L << 14 (S); -R1.L = R7.L << 15 (S); -CHECKREG r0, 0x00207FFF; -CHECKREG r1, 0x00207FFF; -CHECKREG r2, 0x00201800; -CHECKREG r3, 0x00203200; -CHECKREG r4, 0x00207FFF; -CHECKREG r5, 0x00207FFF; -CHECKREG r6, 0x00207FFF; -CHECKREG r7, 0x00207FFF; - -imm32 r0, 0x05002001; -imm32 r1, 0x05002001; -imm32 r2, 0x0500000f; -imm32 r3, 0x05002003; -imm32 r4, 0x05002004; -imm32 r5, 0x05002005; -imm32 r6, 0x05002006; -imm32 r7, 0x05002007; -R3.L = R0.L << 0 (S); -R4.L = R1.L << 1 (S); -R5.L = R2.L << 2 (S); -R6.L = R3.L << 3 (S); -R7.L = R4.L << 4 (S); -R0.L = R5.L << 5 (S); -R1.L = R6.L << 6 (S); -R2.L = R7.L << 7 (S); -CHECKREG r0, 0x05000780; -CHECKREG r1, 0x05007FFF; -CHECKREG r2, 0x05007FFF; -CHECKREG r3, 0x05002001; -CHECKREG r4, 0x05004002; -CHECKREG r5, 0x0500003C; -CHECKREG r6, 0x05007FFF; -CHECKREG r7, 0x05007FFF; - -imm32 r0, 0x03000031; -imm32 r1, 0x03000031; -imm32 r2, 0x03000032; -imm32 r3, 0x03000030; -imm32 r4, 0x03000034; -imm32 r5, 0x03000035; -imm32 r6, 0x03000036; -imm32 r7, 0x03000037; -R4.L = R0.L << 8 (S); -R5.L = R1.L << 9 (S); -R6.L = R2.L << 10 (S); -R7.L = R3.L << 11 (S); -R0.L = R4.L << 12 (S); -R1.L = R5.L << 13 (S); -R2.L = R6.L << 14 (S); -R3.L = R7.L << 15 (S); -CHECKREG r0, 0x03007FFF; -CHECKREG r1, 0x03007FFF; -CHECKREG r2, 0x03007FFF; -CHECKREG r3, 0x03007FFF; -CHECKREG r4, 0x03003100; -CHECKREG r5, 0x03006200; -CHECKREG r6, 0x03007FFF; -CHECKREG r7, 0x03007FFF; -// RHx by RLx -imm32 r0, 0x03000000; -imm32 r1, 0x03000000; -imm32 r2, 0x03000000; -imm32 r3, 0x03000000; -imm32 r4, 0x03003100; -imm32 r5, 0x03006200; -imm32 r6, 0x0300C800; -imm32 r7, 0x03008000; -R5.L = R0.H << 0 (S); -R6.L = R1.H << 1 (S); -R7.L = R2.H << 2 (S); -R0.L = R3.H << 3 (S); -R1.L = R4.H << 4 (S); -R2.L = R5.H << 5 (S); -R3.L = R6.H << 6 (S); -R4.L = R7.H << 7 (S); -CHECKREG r0, 0x03001800; -CHECKREG r1, 0x03003000; -CHECKREG r2, 0x03006000; -CHECKREG r3, 0x03007FFF; -CHECKREG r4, 0x03007FFF; -CHECKREG r5, 0x03000300; -CHECKREG r6, 0x03000600; -CHECKREG r7, 0x03000C00; - -imm32 r0, 0x05018000; -imm32 r1, 0x05018001; -imm32 r2, 0x05028000; -imm32 r3, 0x05038000; -imm32 r4, 0x05048000; -imm32 r5, 0x05058000; -imm32 r6, 0x05068000; -imm32 r7, 0x05078000; -R6.L = R0.H << 8 (S); -R7.L = R1.H << 9 (S); -R0.L = R2.H << 10 (S); -R1.L = R3.H << 11 (S); -R2.L = R4.H << 12 (S); -R3.L = R5.H << 13 (S); -R4.L = R6.H << 14 (S); -R5.L = R7.H << 15 (S); -CHECKREG r0, 0x05017FFF; -CHECKREG r1, 0x05017FFF; -CHECKREG r2, 0x05027FFF; -CHECKREG r3, 0x05037FFF; -CHECKREG r4, 0x05047FFF; -CHECKREG r5, 0x05057FFF; -CHECKREG r6, 0x05067FFF; -CHECKREG r7, 0x05077FFF; - - -imm32 r0, 0x60019000; -imm32 r1, 0x60019000; -imm32 r2, 0x6002900f; -imm32 r3, 0x60039000; -imm32 r4, 0x60049000; -imm32 r5, 0x60059000; -imm32 r6, 0x60069000; -imm32 r7, 0x60079000; -R7.L = R0.H << 0 (S); -R0.L = R1.H << 1 (S); -R1.L = R2.H << 2 (S); -R2.L = R3.H << 3 (S); -R3.L = R4.H << 4 (S); -R4.L = R5.H << 5 (S); -R5.L = R6.H << 6 (S); -R6.L = R7.H << 7 (S); -CHECKREG r0, 0x60017FFF; -CHECKREG r1, 0x60017FFF; -CHECKREG r2, 0x60027FFF; -CHECKREG r3, 0x60037FFF; -CHECKREG r4, 0x60047FFF; -CHECKREG r5, 0x60057FFF; -CHECKREG r6, 0x60067FFF; -CHECKREG r7, 0x60076001; - -imm32 r0, 0x70010001; -imm32 r1, 0x70010001; -imm32 r2, 0x70020002; -imm32 r3, 0x77030010; -imm32 r4, 0x70040004; -imm32 r5, 0x70050005; -imm32 r6, 0x70060006; -imm32 r7, 0x70070007; -R0.L = R0.H << 8 (S); -R1.L = R1.H << 9 (S); -R2.L = R2.H << 10 (S); -R3.L = R3.H << 11 (S); -R4.L = R4.H << 12 (S); -R5.L = R5.H << 13 (S); -R6.L = R6.H << 14 (S); -R7.L = R7.H << 15 (S); -CHECKREG r0, 0x70017FFF; -CHECKREG r1, 0x70017FFF; -CHECKREG r2, 0x70027FFF; -CHECKREG r3, 0x77037FFF; -CHECKREG r4, 0x70047FFF; -CHECKREG r5, 0x70057FFF; -CHECKREG r6, 0x70067FFF; -CHECKREG r7, 0x70077FFF; - -// d_hi = lshft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0xa8000000; -imm32 r1, 0xa8000001; -imm32 r2, 0xa8000002; -imm32 r3, 0xa8000003; -imm32 r4, 0xa8000004; -imm32 r5, 0xa8000005; -imm32 r6, 0xa8000006; -imm32 r7, 0xa8000007; -R0.H = R0.L << 0 (S); -R1.H = R1.L << 1 (S); -R2.H = R2.L << 2 (S); -R3.H = R3.L << 3 (S); -R4.H = R4.L << 4 (S); -R5.H = R5.L << 5 (S); -R6.H = R6.L << 6 (S); -R7.H = R7.L << 7 (S); -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0x00080002; -CHECKREG r3, 0x00180003; -CHECKREG r4, 0x00400004; -CHECKREG r5, 0x00A00005; -CHECKREG r6, 0x01800006; -CHECKREG r7, 0x03800007; - -imm32 r0, 0xf0090001; -imm32 r1, 0xf0090001; -imm32 r2, 0xf0090002; -imm32 r3, 0xf0090003; -imm32 r4, 0xf0090004; -imm32 r5, 0xf0090005; -imm32 r6, 0xf0000006; -imm32 r7, 0xf0000007; -R1.H = R0.L << 8 (S); -R2.H = R1.L << 9 (S); -R3.H = R2.L << 10 (S); -R4.H = R3.L << 11 (S); -R5.H = R4.L << 12 (S); -R6.H = R5.L << 13 (S); -R7.H = R6.L << 14 (S); -R0.H = R7.L << 15 (S); -CHECKREG r1, 0x01000001; -CHECKREG r2, 0x02000002; -CHECKREG r3, 0x08000003; -CHECKREG r4, 0x18000004; -CHECKREG r5, 0x40000005; -CHECKREG r6, 0x7FFF0006; -CHECKREG r7, 0x7FFF0007; -CHECKREG r0, 0x7FFF0001; - - -imm32 r0, 0x07000001; -imm32 r1, 0x07000001; -imm32 r2, 0x0700000f; -imm32 r3, 0x07000003; -imm32 r4, 0x07000004; -imm32 r5, 0x07000005; -imm32 r6, 0x07000006; -imm32 r7, 0x07000007; -R3.H = R0.L << 0 (S); -R4.H = R1.L << 1 (S); -R5.H = R2.L << 2 (S); -R6.H = R3.L << 3 (S); -R7.H = R4.L << 4 (S); -R0.H = R5.L << 5 (S); -R1.H = R6.L << 6 (S); -R2.H = R7.L << 7 (S); -CHECKREG r0, 0x00A00001; -CHECKREG r1, 0x01800001; -CHECKREG r2, 0x0380000F; -CHECKREG r3, 0x00010003; -CHECKREG r4, 0x00020004; -CHECKREG r5, 0x003C0005; -CHECKREG r6, 0x00180006; -CHECKREG r7, 0x00400007; - -imm32 r0, 0x00000501; -imm32 r1, 0x00000501; -imm32 r2, 0x00000502; -imm32 r3, 0x00000510; -imm32 r4, 0x00000504; -imm32 r5, 0x00000505; -imm32 r6, 0x00000506; -imm32 r7, 0x00000507; -R4.H = R0.L << 8 (S); -R5.H = R1.L << 9 (S); -R6.H = R2.L << 10 (S); -R7.H = R3.L << 11 (S); -R0.H = R4.L << 12 (S); -R1.H = R5.L << 13 (S); -R2.H = R6.L << 14 (S); -R3.H = R7.L << 15 (S); -CHECKREG r0, 0x7FFF0501; -CHECKREG r1, 0x7FFF0501; -CHECKREG r2, 0x7FFF0502; -CHECKREG r3, 0x7FFF0510; -CHECKREG r4, 0x7FFF0504; -CHECKREG r5, 0x7FFF0505; -CHECKREG r6, 0x7FFF0506; -CHECKREG r7, 0x7FFF0507; - -imm32 r0, 0x00a00800; -imm32 r1, 0x00a10800; -imm32 r2, 0x00a20800; -imm32 r3, 0x00a30800; -imm32 r4, 0x00a40800; -imm32 r5, 0x00a50800; -imm32 r6, 0x00a60800; -imm32 r7, 0x00a70800; -R5.H = R0.H << 0 (S); -R6.H = R1.H << 1 (S); -R7.H = R2.H << 2 (S); -R0.H = R3.H << 3 (S); -R1.H = R4.H << 4 (S); -R2.H = R5.H << 5 (S); -R3.H = R6.H << 6 (S); -R4.H = R7.H << 7 (S); -CHECKREG r0, 0x05180800; -CHECKREG r1, 0x0A400800; -CHECKREG r2, 0x14000800; -CHECKREG r3, 0x50800800; -CHECKREG r4, 0x7FFF0800; -CHECKREG r5, 0x00A00800; -CHECKREG r6, 0x01420800; -CHECKREG r7, 0x02880800; - -imm32 r0, 0x0c010000; -imm32 r1, 0x0c010001; -imm32 r2, 0x0c020000; -imm32 r3, 0x0c030000; -imm32 r4, 0x0c040000; -imm32 r5, 0x0c050000; -imm32 r6, 0x0c060000; -imm32 r7, 0x0c070000; -R6.H = R0.H << 8 (S); -R7.H = R1.H << 9 (S); -R0.H = R2.H << 10 (S); -R1.H = R3.H << 11 (S); -R2.H = R4.H << 12 (S); -R3.H = R5.H << 13 (S); -R4.H = R6.H << 14 (S); -R5.H = R7.H << 15 (S); -CHECKREG r0, 0x7FFF0000; -CHECKREG r1, 0x7FFF0001; -CHECKREG r2, 0x7FFF0000; -CHECKREG r3, 0x7FFF0000; -CHECKREG r4, 0x7FFF0000; -CHECKREG r5, 0x7FFF0000; -CHECKREG r6, 0x7FFF0000; -CHECKREG r7, 0x7FFF0000; - - -imm32 r0, 0x00b10000; -imm32 r1, 0x00b10000; -imm32 r2, 0x00b2000f; -imm32 r3, 0x00b30000; -imm32 r4, 0x00b40000; -imm32 r5, 0x00b50000; -imm32 r6, 0x00b60000; -imm32 r7, 0x00b70000; -R7.L = R0.H << 0 (S); -R0.L = R1.H << 1 (S); -R1.L = R2.H << 2 (S); -R2.L = R3.H << 3 (S); -R3.L = R4.H << 4 (S); -R4.L = R5.H << 5 (S); -R5.L = R6.H << 6 (S); -R6.L = R7.H << 7 (S); -CHECKREG r0, 0x00B10162; -CHECKREG r1, 0x00B102C8; -CHECKREG r2, 0x00B20598; -CHECKREG r3, 0x00B30B40; -CHECKREG r4, 0x00B416A0; -CHECKREG r5, 0x00B52D80; -CHECKREG r6, 0x00B65B80; -CHECKREG r7, 0x00B700B1; - -imm32 r0, 0x0a010700; -imm32 r1, 0x0a010700; -imm32 r2, 0x0a020700; -imm32 r3, 0x0a030710; -imm32 r4, 0x0a040700; -imm32 r5, 0x0a050700; -imm32 r6, 0x0a060700; -imm32 r7, 0x0a070700; -R0.H = R0.H << 8 (S); -R1.H = R1.H << 9 (S); -R2.H = R2.H << 10 (S); -R3.H = R3.H << 11 (S); -R4.H = R4.H << 12 (S); -R5.H = R5.H << 13 (S); -R6.H = R6.H << 14 (S); -R7.H = R7.H << 15 (S); -CHECKREG r0, 0x7FFF0700; -CHECKREG r1, 0x7FFF0700; -CHECKREG r2, 0x7FFF0700; -CHECKREG r3, 0x7FFF0710; -CHECKREG r4, 0x7FFF0700; -CHECKREG r5, 0x7FFF0700; -CHECKREG r6, 0x7FFF0700; -CHECKREG r7, 0x7FFF0700; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn.s deleted file mode 100644 index 30d84f2..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn.s +++ /dev/null @@ -1,418 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_ahalf_rn/c_dsp32shiftim_ahalf_rn.dsp -// Spec Reference: dsp32shift ashift -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -R0.L = -1; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = R0.L >>> 10; -R1.L = R1.L >>> 10; -R2.L = R2.L >>> 10; -R3.L = R3.L >>> 10; -R4.L = R4.L >>> 10; -R5.L = R5.L >>> 10; -R6.L = R6.L >>> 10; -R7.L = R7.L >>> 10; -CHECKREG r0, 0x0000FFFF; -CHECKREG r1, 0x0000FFE0; -CHECKREG r2, 0x0000FFE0; -CHECKREG r3, 0x0000FFE0; -CHECKREG r4, 0x0000FFE0; -CHECKREG r5, 0x0000FFE0; -CHECKREG r6, 0x0000FFE0; -CHECKREG r7, 0x0000FFE0; - -imm32 r0, 0x02008020; -imm32 r0, 0x02008021; -imm32 r2, 0x02008022; -imm32 r3, 0x02008023; -imm32 r4, 0x02008024; -imm32 r5, 0x02008025; -imm32 r6, 0x02008026; -imm32 r7, 0x02008027; -R0.L = R0.L >>> 11; -R1.L = R1.L >>> 11; -R2.L = R2.L >>> 11; -R3.L = R3.L >>> 11; -R4.L = R4.L >>> 11; -R5.L = R5.L >>> 11; -R6.L = R6.L >>> 11; -R7.L = R7.L >>> 11; -CHECKREG r0, 0x0200FFF0; -CHECKREG r1, 0x0000FFFF; -CHECKREG r2, 0x0200FFF0; -CHECKREG r3, 0x0200FFF0; -CHECKREG r4, 0x0200FFF0; -CHECKREG r5, 0x0200FFF0; -CHECKREG r6, 0x0200FFF0; -CHECKREG r7, 0x0200FFF0; - - -imm32 r0, 0x00308001; -imm32 r1, 0x00308001; -R2.L = -15; -imm32 r3, 0x00308003; -imm32 r4, 0x00308004; -imm32 r5, 0x00308005; -imm32 r6, 0x00308006; -imm32 r7, 0x00308007; -R0.L = R0.L >>> 12; -R1.L = R1.L >>> 12; -R2.L = R2.L >>> 12; -R3.L = R3.L >>> 12; -R4.L = R4.L >>> 12; -R5.L = R5.L >>> 12; -R6.L = R6.L >>> 12; -R7.L = R7.L >>> 12; -CHECKREG r0, 0x0030FFF8; -CHECKREG r1, 0x0030FFF8; -CHECKREG r2, 0x0200FFFF; -CHECKREG r3, 0x0030FFF8; -CHECKREG r4, 0x0030FFF8; -CHECKREG r5, 0x0030FFF8; -CHECKREG r6, 0x0030FFF8; -CHECKREG r7, 0x0030FFF8; - -imm32 r0, 0x00008401; -imm32 r1, 0x00008401; -imm32 r2, 0x00008402; -R3.L = -16; -imm32 r4, 0x00008404; -imm32 r5, 0x00008405; -imm32 r6, 0x00008406; -imm32 r7, 0x00008407; -R0.L = R0.L >>> 3; -R1.L = R1.L >>> 3; -R2.L = R2.L >>> 3; -R3.L = R3.L >>> 3; -R4.L = R4.L >>> 3; -R5.L = R5.L >>> 3; -R6.L = R6.L >>> 3; -R7.L = R7.L >>> 3; -CHECKREG r0, 0x0000F080; -CHECKREG r1, 0x0000F080; -CHECKREG r2, 0x0000F080; -CHECKREG r3, 0x0030FFFE; -CHECKREG r4, 0x0000F080; -CHECKREG r5, 0x0000F080; -CHECKREG r6, 0x0000F080; -CHECKREG r7, 0x0000F080; - -// d_lo = ashift (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x05000500; -imm32 r1, 0x85010500; -imm32 r2, 0x85020500; -imm32 r3, 0x85030500; -imm32 r4, 0x85040500; -imm32 r5, 0x85050500; -imm32 r6, 0x85060500; -imm32 r7, 0x85070500; -R0.L = R0.H >>> 10; -R1.L = R1.H >>> 10; -R2.L = R2.H >>> 10; -R3.L = R3.H >>> 10; -R4.L = R4.H >>> 10; -R5.L = R5.H >>> 10; -R6.L = R6.H >>> 10; -R7.L = R7.H >>> 10; -CHECKREG r0, 0x05000001; -CHECKREG r1, 0x8501FFE1; -CHECKREG r2, 0x8502FFE1; -CHECKREG r3, 0x8503FFE1; -CHECKREG r4, 0x8504FFE1; -CHECKREG r5, 0x8505FFE1; -CHECKREG r6, 0x8506FFE1; -CHECKREG r7, 0x8507FFE1; - -imm32 r0, 0x80610000; -R1.L = -1; -imm32 r2, 0x80620000; -imm32 r3, 0x80630000; -imm32 r4, 0x80640000; -imm32 r5, 0x80650000; -imm32 r6, 0x80660000; -imm32 r7, 0x80670000; -R0.L = R0.H >>> 11; -R1.L = R1.H >>> 11; -R2.L = R2.H >>> 11; -R3.L = R3.H >>> 11; -R4.L = R4.H >>> 11; -R5.L = R5.H >>> 11; -R6.L = R6.H >>> 11; -R7.L = R7.H >>> 11; -CHECKREG r0, 0x8061FFF0; -CHECKREG r1, 0x8501FFF0; -CHECKREG r2, 0x8062FFF0; -CHECKREG r3, 0x8063FFF0; -CHECKREG r4, 0x8064FFF0; -CHECKREG r5, 0x8065FFF0; -CHECKREG r6, 0x8066FFF0; -CHECKREG r7, 0x8067FFF0; - - -imm32 r0, 0xa0010070; -imm32 r1, 0xa0010070; -R2.L = -15; -imm32 r3, 0xa0030070; -imm32 r4, 0xa0040070; -imm32 r5, 0xa0050070; -imm32 r6, 0xa0060070; -imm32 r7, 0xa0070070; -R0.L = R0.H >>> 12; -R1.L = R1.H >>> 12; -R2.L = R2.H >>> 12; -R3.L = R3.H >>> 12; -R4.L = R4.H >>> 12; -R5.L = R5.H >>> 12; -R6.L = R6.H >>> 12; -R7.L = R7.H >>> 12; -CHECKREG r0, 0xA001FFFA; -CHECKREG r1, 0xA001FFFA; -CHECKREG r2, 0x8062FFF8; -CHECKREG r3, 0xA003FFFA; -CHECKREG r4, 0xA004FFFA; -CHECKREG r5, 0xA005FFFA; -CHECKREG r6, 0xA006FFFA; -CHECKREG r7, 0xA007FFFA; - -imm32 r0, 0xb8010001; -imm32 r1, 0xb8010001; -imm32 r2, 0xb8020002; -R3.L = -16; -imm32 r4, 0xb8040004; -imm32 r5, 0xb8050005; -imm32 r6, 0xb8060006; -imm32 r7, 0xb8070007; -R0.L = R0.H >>> 13; -R1.L = R1.H >>> 13; -R2.L = R2.H >>> 13; -R3.L = R3.H >>> 13; -R4.L = R4.H >>> 13; -R5.L = R5.H >>> 13; -R6.L = R6.H >>> 13; -R7.L = R7.H >>> 13; -CHECKREG r0, 0xB801FFFD; -CHECKREG r1, 0xB801FFFD; -CHECKREG r2, 0xB802FFFD; -CHECKREG r3, 0xA003FFFD; -CHECKREG r4, 0xB804FFFD; -CHECKREG r5, 0xB805FFFD; -CHECKREG r6, 0xB806FFFD; -CHECKREG r7, 0xB807FFFD; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00009001; -imm32 r1, 0x00009001; -imm32 r2, 0x00009002; -imm32 r3, 0x00009003; -imm32 r4, 0x00009000; -imm32 r5, 0x00009005; -imm32 r6, 0x00009006; -imm32 r7, 0x00009007; -R0.H = R0.L >>> 14; -R1.H = R1.L >>> 14; -R2.H = R2.L >>> 14; -R3.H = R3.L >>> 14; -R4.H = R4.L >>> 14; -R5.H = R5.L >>> 14; -R6.H = R6.L >>> 14; -R7.H = R7.L >>> 14; -CHECKREG r0, 0xFFFE9001; -CHECKREG r1, 0xFFFE9001; -CHECKREG r2, 0xFFFE9002; -CHECKREG r3, 0xFFFE9003; -CHECKREG r4, 0xFFFE9000; -CHECKREG r5, 0xFFFE9005; -CHECKREG r6, 0xFFFE9006; -CHECKREG r7, 0xFFFE9007; - -imm32 r0, 0xa0008001; -imm32 r1, 0xa0008001; -imm32 r2, 0xa0008002; -imm32 r3, 0xa0008003; -imm32 r4, 0xa0008004; -R5.L = -1; -imm32 r6, 0xa0008006; -imm32 r7, 0xa0008007; -R0.H = R0.L >>> 5; -R1.H = R1.L >>> 5; -R2.H = R2.L >>> 5; -R3.H = R3.L >>> 5; -R4.H = R4.L >>> 5; -R5.H = R5.L >>> 5; -R6.H = R6.L >>> 5; -R7.H = R7.L >>> 5; -CHECKREG r0, 0xFC008001; -CHECKREG r1, 0xFC008001; -CHECKREG r2, 0xFC008002; -CHECKREG r3, 0xFC008003; -CHECKREG r4, 0xFC008004; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0xFC008006; -CHECKREG r7, 0xFC008007; - - -imm32 r0, 0x00009b01; -imm32 r1, 0x00009b01; -imm32 r2, 0x00009b02; -imm32 r3, 0x00009b03; -imm32 r4, 0x00009b04; -imm32 r5, 0x00009b05; -R6.L = -15; -imm32 r7, 0x00009007; -R0.H = R0.L >>> 6; -R1.H = R1.L >>> 6; -R2.H = R2.L >>> 6; -R3.H = R3.L >>> 6; -R4.H = R4.L >>> 6; -R5.H = R5.L >>> 6; -R6.H = R6.L >>> 6; -R7.H = R7.L >>> 6; -CHECKREG r0, 0xFE6C9B01; -CHECKREG r1, 0xFE6C9B01; -CHECKREG r2, 0xFE6C9B02; -CHECKREG r3, 0xFE6C9B03; -CHECKREG r4, 0xFE6C9B04; -CHECKREG r5, 0xFE6C9B05; -CHECKREG r6, 0xFFFFFFF1; -CHECKREG r7, 0xFE409007; - -imm32 r0, 0x0000a0c1; -imm32 r1, 0x0000a0c1; -imm32 r2, 0x0000a0c2; -imm32 r3, 0x0000a0c3; -imm32 r4, 0x0000a0c4; -imm32 r5, 0x0000a0c5; -imm32 r6, 0x0000a0c6; -R7.L = -16; -R0.H = R0.L >>> 7; -R1.H = R1.L >>> 7; -R2.H = R2.L >>> 7; -R3.H = R3.L >>> 7; -R4.H = R4.L >>> 7; -R5.H = R5.L >>> 7; -R6.H = R6.L >>> 7; -R7.H = R7.L >>> 7; -CHECKREG r0, 0xFF41A0C1; -CHECKREG r1, 0xFF41A0C1; -CHECKREG r2, 0xFF41A0C2; -CHECKREG r3, 0xFF41A0C3; -CHECKREG r4, 0xFF41A0C4; -CHECKREG r5, 0xFF41A0C5; -CHECKREG r6, 0xFF41A0C6; -CHECKREG r7, 0xFFFFFFF0; - -imm32 r0, 0x80010d00; -imm32 r1, 0x80010d00; -imm32 r2, 0x80020d00; -imm32 r3, 0x80030d00; -R4.L = -1; -imm32 r5, 0x80050d00; -imm32 r6, 0x80060d00; -imm32 r7, 0x80070d00; -R0.H = R0.H >>> 14; -R1.H = R1.H >>> 14; -R2.H = R2.H >>> 14; -R3.H = R3.H >>> 14; -R4.H = R4.H >>> 14; -R5.H = R5.H >>> 14; -R6.H = R6.H >>> 14; -R7.H = R7.H >>> 14; -CHECKREG r0, 0xFFFE0D00; -CHECKREG r1, 0xFFFE0D00; -CHECKREG r2, 0xFFFE0D00; -CHECKREG r3, 0xFFFE0D00; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0xFFFE0D00; -CHECKREG r6, 0xFFFE0D00; -CHECKREG r7, 0xFFFE0D00; - -imm32 r0, 0x8d010000; -imm32 r1, 0x8d010000; -imm32 r2, 0x8d020000; -imm32 r3, 0x8d030000; -imm32 r4, 0x8d040000; -R5.L = -1; -imm32 r6, 0x8d060000; -imm32 r7, 0x8d070000; -R0.H = R0.H >>> 15; -R1.H = R1.H >>> 15; -R2.H = R2.H >>> 15; -R3.H = R3.H >>> 15; -R4.H = R4.H >>> 15; -R5.H = R5.H >>> 15; -R6.H = R6.H >>> 15; -R7.H = R7.H >>> 15; -CHECKREG r0, 0xFFFF0000; -CHECKREG r1, 0xFFFF0000; -CHECKREG r2, 0xFFFF0000; -CHECKREG r3, 0xFFFF0000; -CHECKREG r4, 0xFFFF0000; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0xFFFF0000; -CHECKREG r7, 0xFFFF0000; - - -imm32 r0, 0xde010000; -imm32 r1, 0xde010000; -imm32 r2, 0xde020000; -imm32 r3, 0xde030000; -imm32 r4, 0xde040000; -imm32 r5, 0xde050000; -R6.L = -15; -imm32 r7, 0xd0070000; -R0.L = R0.H >>> 10; -R1.L = R1.H >>> 10; -R2.L = R2.H >>> 10; -R3.L = R3.H >>> 10; -R4.L = R4.H >>> 10; -R5.L = R5.H >>> 10; -R6.L = R6.H >>> 10; -R7.L = R7.H >>> 10; -CHECKREG r0, 0xDE01FFF7; -CHECKREG r1, 0xDE01FFF7; -CHECKREG r2, 0xDE02FFF7; -CHECKREG r3, 0xDE03FFF7; -CHECKREG r4, 0xDE04FFF7; -CHECKREG r5, 0xDE05FFF7; -CHECKREG r6, 0xFFFFFFFF; -CHECKREG r7, 0xD007FFF4; - -imm32 r0, 0x9f010c00; -imm32 r1, 0xaf010c00; -imm32 r2, 0xbf020c00; -imm32 r3, 0xcf030c00; -imm32 r4, 0xdf040c00; -imm32 r5, 0xef050c00; -imm32 r6, 0xff060c00; -R7.L = -16; -R0.H = R0.H >>> 5; -R1.H = R1.H >>> 5; -R2.H = R2.H >>> 5; -R3.H = R3.H >>> 5; -R4.H = R4.H >>> 5; -R5.H = R5.H >>> 5; -R6.H = R6.H >>> 5; -R7.H = R7.H >>> 5; -CHECKREG r0, 0xFCF80C00; -CHECKREG r1, 0xFD780C00; -CHECKREG r2, 0xFDF80C00; -CHECKREG r3, 0xFE780C00; -CHECKREG r4, 0xFEF80C00; -CHECKREG r5, 0xFF780C00; -CHECKREG r6, 0xFFF80C00; -CHECKREG r7, 0xFE80FFF0; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn_s.s deleted file mode 100644 index 20770d5..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn_s.s +++ /dev/null @@ -1,418 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_ahalf_rn_s/c_dsp32shiftim_ahalf_rn_s.dsp -// Spec Reference: dsp32shift ashift -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -R0.L = -1; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = R0.L >>> 10; -R1.L = R1.L >>> 10; -R2.L = R2.L >>> 10; -R3.L = R3.L >>> 10; -R4.L = R4.L >>> 10; -R5.L = R5.L >>> 10; -R6.L = R6.L >>> 10; -R7.L = R7.L >>> 10; -CHECKREG r0, 0x0000FFFF; -CHECKREG r1, 0x0000FFE0; -CHECKREG r2, 0x0000FFE0; -CHECKREG r3, 0x0000FFE0; -CHECKREG r4, 0x0000FFE0; -CHECKREG r5, 0x0000FFE0; -CHECKREG r6, 0x0000FFE0; -CHECKREG r7, 0x0000FFE0; - -imm32 r0, 0x02008020; -imm32 r0, 0x02008021; -imm32 r2, 0x02008022; -imm32 r3, 0x02008023; -imm32 r4, 0x02008024; -imm32 r5, 0x02008025; -imm32 r6, 0x02008026; -imm32 r7, 0x02008027; -R0.L = R0.L >>> 11; -R1.L = R1.L >>> 11; -R2.L = R2.L >>> 11; -R3.L = R3.L >>> 11; -R4.L = R4.L >>> 11; -R5.L = R5.L >>> 11; -R6.L = R6.L >>> 11; -R7.L = R7.L >>> 11; -CHECKREG r0, 0x0200FFF0; -CHECKREG r1, 0x0000FFFF; -CHECKREG r2, 0x0200FFF0; -CHECKREG r3, 0x0200FFF0; -CHECKREG r4, 0x0200FFF0; -CHECKREG r5, 0x0200FFF0; -CHECKREG r6, 0x0200FFF0; -CHECKREG r7, 0x0200FFF0; - - -imm32 r0, 0x00308001; -imm32 r1, 0x00308001; -R2.L = -15; -imm32 r3, 0x00308003; -imm32 r4, 0x00308004; -imm32 r5, 0x00308005; -imm32 r6, 0x00308006; -imm32 r7, 0x00308007; -R0.L = R0.L >>> 12; -R1.L = R1.L >>> 12; -R2.L = R2.L >>> 12; -R3.L = R3.L >>> 12; -R4.L = R4.L >>> 12; -R5.L = R5.L >>> 12; -R6.L = R6.L >>> 12; -R7.L = R7.L >>> 12; -CHECKREG r0, 0x0030FFF8; -CHECKREG r1, 0x0030FFF8; -CHECKREG r2, 0x0200FFFF; -CHECKREG r3, 0x0030FFF8; -CHECKREG r4, 0x0030FFF8; -CHECKREG r5, 0x0030FFF8; -CHECKREG r6, 0x0030FFF8; -CHECKREG r7, 0x0030FFF8; - -imm32 r0, 0x00008401; -imm32 r1, 0x00008401; -imm32 r2, 0x00008402; -R3.L = -16; -imm32 r4, 0x00008404; -imm32 r5, 0x00008405; -imm32 r6, 0x00008406; -imm32 r7, 0x00008407; -R0.L = R0.L >>> 3; -R1.L = R1.L >>> 3; -R2.L = R2.L >>> 3; -R3.L = R3.L >>> 3; -R4.L = R4.L >>> 3; -R5.L = R5.L >>> 3; -R6.L = R6.L >>> 3; -R7.L = R7.L >>> 3; -CHECKREG r0, 0x0000F080; -CHECKREG r1, 0x0000F080; -CHECKREG r2, 0x0000F080; -CHECKREG r3, 0x0030FFFE; -CHECKREG r4, 0x0000F080; -CHECKREG r5, 0x0000F080; -CHECKREG r6, 0x0000F080; -CHECKREG r7, 0x0000F080; - -// d_lo = ashift (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x05000500; -imm32 r1, 0x85010500; -imm32 r2, 0x85020500; -imm32 r3, 0x85030500; -imm32 r4, 0x85040500; -imm32 r5, 0x85050500; -imm32 r6, 0x85060500; -imm32 r7, 0x85070500; -R0.L = R0.H >>> 10; -R1.L = R1.H >>> 10; -R2.L = R2.H >>> 10; -R3.L = R3.H >>> 10; -R4.L = R4.H >>> 10; -R5.L = R5.H >>> 10; -R6.L = R6.H >>> 10; -R7.L = R7.H >>> 10; -CHECKREG r0, 0x05000001; -CHECKREG r1, 0x8501FFE1; -CHECKREG r2, 0x8502FFE1; -CHECKREG r3, 0x8503FFE1; -CHECKREG r4, 0x8504FFE1; -CHECKREG r5, 0x8505FFE1; -CHECKREG r6, 0x8506FFE1; -CHECKREG r7, 0x8507FFE1; - -imm32 r0, 0x80610000; -R1.L = -1; -imm32 r2, 0x80620000; -imm32 r3, 0x80630000; -imm32 r4, 0x80640000; -imm32 r5, 0x80650000; -imm32 r6, 0x80660000; -imm32 r7, 0x80670000; -R0.L = R0.H >>> 11; -R1.L = R1.H >>> 11; -R2.L = R2.H >>> 11; -R3.L = R3.H >>> 11; -R4.L = R4.H >>> 11; -R5.L = R5.H >>> 11; -R6.L = R6.H >>> 11; -R7.L = R7.H >>> 11; -CHECKREG r0, 0x8061FFF0; -CHECKREG r1, 0x8501FFF0; -CHECKREG r2, 0x8062FFF0; -CHECKREG r3, 0x8063FFF0; -CHECKREG r4, 0x8064FFF0; -CHECKREG r5, 0x8065FFF0; -CHECKREG r6, 0x8066FFF0; -CHECKREG r7, 0x8067FFF0; - - -imm32 r0, 0xa0010070; -imm32 r1, 0xa0010070; -R2.L = -15; -imm32 r3, 0xa0030070; -imm32 r4, 0xa0040070; -imm32 r5, 0xa0050070; -imm32 r6, 0xa0060070; -imm32 r7, 0xa0070070; -R0.L = R0.H >>> 12; -R1.L = R1.H >>> 12; -R2.L = R2.H >>> 12; -R3.L = R3.H >>> 12; -R4.L = R4.H >>> 12; -R5.L = R5.H >>> 12; -R6.L = R6.H >>> 12; -R7.L = R7.H >>> 12; -CHECKREG r0, 0xA001FFFA; -CHECKREG r1, 0xA001FFFA; -CHECKREG r2, 0x8062FFF8; -CHECKREG r3, 0xA003FFFA; -CHECKREG r4, 0xA004FFFA; -CHECKREG r5, 0xA005FFFA; -CHECKREG r6, 0xA006FFFA; -CHECKREG r7, 0xA007FFFA; - -imm32 r0, 0xb8010001; -imm32 r1, 0xb8010001; -imm32 r2, 0xb8020002; -R3.L = -16; -imm32 r4, 0xb8040004; -imm32 r5, 0xb8050005; -imm32 r6, 0xb8060006; -imm32 r7, 0xb8070007; -R0.L = R0.H >>> 13; -R1.L = R1.H >>> 13; -R2.L = R2.H >>> 13; -R3.L = R3.H >>> 13; -R4.L = R4.H >>> 13; -R5.L = R5.H >>> 13; -R6.L = R6.H >>> 13; -R7.L = R7.H >>> 13; -CHECKREG r0, 0xB801FFFD; -CHECKREG r1, 0xB801FFFD; -CHECKREG r2, 0xB802FFFD; -CHECKREG r3, 0xA003FFFD; -CHECKREG r4, 0xB804FFFD; -CHECKREG r5, 0xB805FFFD; -CHECKREG r6, 0xB806FFFD; -CHECKREG r7, 0xB807FFFD; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00009001; -imm32 r1, 0x00009001; -imm32 r2, 0x00009002; -imm32 r3, 0x00009003; -imm32 r4, 0x00009000; -imm32 r5, 0x00009005; -imm32 r6, 0x00009006; -imm32 r7, 0x00009007; -R0.H = R0.L >>> 14; -R1.H = R1.L >>> 14; -R2.H = R2.L >>> 14; -R3.H = R3.L >>> 14; -R4.H = R4.L >>> 14; -R5.H = R5.L >>> 14; -R6.H = R6.L >>> 14; -R7.H = R7.L >>> 14; -CHECKREG r0, 0xFFFE9001; -CHECKREG r1, 0xFFFE9001; -CHECKREG r2, 0xFFFE9002; -CHECKREG r3, 0xFFFE9003; -CHECKREG r4, 0xFFFE9000; -CHECKREG r5, 0xFFFE9005; -CHECKREG r6, 0xFFFE9006; -CHECKREG r7, 0xFFFE9007; - -imm32 r0, 0xa0008001; -imm32 r1, 0xa0008001; -imm32 r2, 0xa0008002; -imm32 r3, 0xa0008003; -imm32 r4, 0xa0008004; -R5.L = -1; -imm32 r6, 0xa0008006; -imm32 r7, 0xa0008007; -R0.H = R0.L >>> 5; -R1.H = R1.L >>> 5; -R2.H = R2.L >>> 5; -R3.H = R3.L >>> 5; -R4.H = R4.L >>> 5; -R5.H = R5.L >>> 5; -R6.H = R6.L >>> 5; -R7.H = R7.L >>> 5; -CHECKREG r0, 0xFC008001; -CHECKREG r1, 0xFC008001; -CHECKREG r2, 0xFC008002; -CHECKREG r3, 0xFC008003; -CHECKREG r4, 0xFC008004; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0xFC008006; -CHECKREG r7, 0xFC008007; - - -imm32 r0, 0x00009b01; -imm32 r1, 0x00009b01; -imm32 r2, 0x00009b02; -imm32 r3, 0x00009b03; -imm32 r4, 0x00009b04; -imm32 r5, 0x00009b05; -R6.L = -15; -imm32 r7, 0x00009007; -R0.H = R0.L >>> 6; -R1.H = R1.L >>> 6; -R2.H = R2.L >>> 6; -R3.H = R3.L >>> 6; -R4.H = R4.L >>> 6; -R5.H = R5.L >>> 6; -R6.H = R6.L >>> 6; -R7.H = R7.L >>> 6; -CHECKREG r0, 0xFE6C9B01; -CHECKREG r1, 0xFE6C9B01; -CHECKREG r2, 0xFE6C9B02; -CHECKREG r3, 0xFE6C9B03; -CHECKREG r4, 0xFE6C9B04; -CHECKREG r5, 0xFE6C9B05; -CHECKREG r6, 0xFFFFFFF1; -CHECKREG r7, 0xFE409007; - -imm32 r0, 0x0000a0c1; -imm32 r1, 0x0000a0c1; -imm32 r2, 0x0000a0c2; -imm32 r3, 0x0000a0c3; -imm32 r4, 0x0000a0c4; -imm32 r5, 0x0000a0c5; -imm32 r6, 0x0000a0c6; -R7.L = -16; -R0.H = R0.L >>> 7; -R1.H = R1.L >>> 7; -R2.H = R2.L >>> 7; -R3.H = R3.L >>> 7; -R4.H = R4.L >>> 7; -R5.H = R5.L >>> 7; -R6.H = R6.L >>> 7; -R7.H = R7.L >>> 7; -CHECKREG r0, 0xFF41A0C1; -CHECKREG r1, 0xFF41A0C1; -CHECKREG r2, 0xFF41A0C2; -CHECKREG r3, 0xFF41A0C3; -CHECKREG r4, 0xFF41A0C4; -CHECKREG r5, 0xFF41A0C5; -CHECKREG r6, 0xFF41A0C6; -CHECKREG r7, 0xFFFFFFF0; - -imm32 r0, 0x80010d00; -imm32 r1, 0x80010d00; -imm32 r2, 0x80020d00; -imm32 r3, 0x80030d00; -R4.L = -1; -imm32 r5, 0x80050d00; -imm32 r6, 0x80060d00; -imm32 r7, 0x80070d00; -R0.H = R0.H >>> 14; -R1.H = R1.H >>> 14; -R2.H = R2.H >>> 14; -R3.H = R3.H >>> 14; -R4.H = R4.H >>> 14; -R5.H = R5.H >>> 14; -R6.H = R6.H >>> 14; -R7.H = R7.H >>> 14; -CHECKREG r0, 0xFFFE0D00; -CHECKREG r1, 0xFFFE0D00; -CHECKREG r2, 0xFFFE0D00; -CHECKREG r3, 0xFFFE0D00; -CHECKREG r4, 0xFFFFFFFF; -CHECKREG r5, 0xFFFE0D00; -CHECKREG r6, 0xFFFE0D00; -CHECKREG r7, 0xFFFE0D00; - -imm32 r0, 0x8d010000; -imm32 r1, 0x8d010000; -imm32 r2, 0x8d020000; -imm32 r3, 0x8d030000; -imm32 r4, 0x8d040000; -R5.L = -1; -imm32 r6, 0x8d060000; -imm32 r7, 0x8d070000; -R0.H = R0.H >>> 15; -R1.H = R1.H >>> 15; -R2.H = R2.H >>> 15; -R3.H = R3.H >>> 15; -R4.H = R4.H >>> 15; -R5.H = R5.H >>> 15; -R6.H = R6.H >>> 15; -R7.H = R7.H >>> 15; -CHECKREG r0, 0xFFFF0000; -CHECKREG r1, 0xFFFF0000; -CHECKREG r2, 0xFFFF0000; -CHECKREG r3, 0xFFFF0000; -CHECKREG r4, 0xFFFF0000; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0xFFFF0000; -CHECKREG r7, 0xFFFF0000; - - -imm32 r0, 0xde010000; -imm32 r1, 0xde010000; -imm32 r2, 0xde020000; -imm32 r3, 0xde030000; -imm32 r4, 0xde040000; -imm32 r5, 0xde050000; -R6.L = -15; -imm32 r7, 0xd0070000; -R0.L = R0.H >>> 10; -R1.L = R1.H >>> 10; -R2.L = R2.H >>> 10; -R3.L = R3.H >>> 10; -R4.L = R4.H >>> 10; -R5.L = R5.H >>> 10; -R6.L = R6.H >>> 10; -R7.L = R7.H >>> 10; -CHECKREG r0, 0xDE01FFF7; -CHECKREG r1, 0xDE01FFF7; -CHECKREG r2, 0xDE02FFF7; -CHECKREG r3, 0xDE03FFF7; -CHECKREG r4, 0xDE04FFF7; -CHECKREG r5, 0xDE05FFF7; -CHECKREG r6, 0xFFFFFFFF; -CHECKREG r7, 0xD007FFF4; - -imm32 r0, 0x9f010c00; -imm32 r1, 0xaf010c00; -imm32 r2, 0xbf020c00; -imm32 r3, 0xcf030c00; -imm32 r4, 0xdf040c00; -imm32 r5, 0xef050c00; -imm32 r6, 0xff060c00; -R7.L = -16; -R0.H = R0.H >>> 5; -R1.H = R1.H >>> 5; -R2.H = R2.H >>> 5; -R3.H = R3.H >>> 5; -R4.H = R4.H >>> 5; -R5.H = R5.H >>> 5; -R6.H = R6.H >>> 5; -R7.H = R7.H >>> 5; -CHECKREG r0, 0xFCF80C00; -CHECKREG r1, 0xFD780C00; -CHECKREG r2, 0xFDF80C00; -CHECKREG r3, 0xFE780C00; -CHECKREG r4, 0xFEF80C00; -CHECKREG r5, 0xFF780C00; -CHECKREG r6, 0xFFF80C00; -CHECKREG r7, 0xFE80FFF0; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp.s deleted file mode 100644 index 471795e..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp.s +++ /dev/null @@ -1,420 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_ahalf_rp/c_dsp32shiftim_ahalf_rp.dsp -// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) -# mach: bfin - -.include "testutils.inc" - start - -// Ashift : positive data, count (+)=right (half reg) -// d_lo = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -R0.L = -1; -imm32 r1, 0x00010001; -imm32 r2, 0x00010002; -imm32 r3, 0x00010003; -imm32 r4, 0x00010004; -imm32 r5, 0x00010005; -imm32 r6, 0x00010006; -imm32 r7, 0x00010007; -R0.L = R0.L >>> 1; -R1.L = R1.L >>> 1; -R2.L = R2.L >>> 1; -R3.L = R3.L >>> 1; -R4.L = R4.L >>> 1; -R5.L = R5.L >>> 1; -R6.L = R6.L >>> 1; -R7.L = R7.L >>> 1; -CHECKREG r0, 0x0000FFFF; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x00010001; -CHECKREG r3, 0x00010001; -CHECKREG r4, 0x00010002; -CHECKREG r5, 0x00010002; -CHECKREG r6, 0x00010003; -CHECKREG r7, 0x00010003; - -imm32 r0, 0x00201001; -R1.L = -1; -imm32 r2, 0x00202002; -imm32 r3, 0x00203003; -imm32 r4, 0x00204004; -imm32 r5, 0x00205005; -imm32 r6, 0x00206006; -imm32 r7, 0x00207007; -R7.L = R0.L >>> 5; -R0.L = R1.L >>> 5; -R1.L = R2.L >>> 5; -R2.L = R3.L >>> 5; -R3.L = R4.L >>> 5; -R4.L = R5.L >>> 5; -R5.L = R6.L >>> 5; -R6.L = R7.L >>> 5; -CHECKREG r0, 0x0020FFFF; -CHECKREG r1, 0x00010100; -CHECKREG r2, 0x00200180; -CHECKREG r3, 0x00200200; -CHECKREG r4, 0x00200280; -CHECKREG r5, 0x00200300; -CHECKREG r6, 0x00200004; -CHECKREG r7, 0x00200080; - - -imm32 r0, 0x03001001; -imm32 r1, 0x03001001; -R2.L = -15; -imm32 r3, 0x03003003; -imm32 r4, 0x03004004; -imm32 r5, 0x03005005; -imm32 r6, 0x03006006; -imm32 r7, 0x03007007; -R6.L = R0.L >>> 2; -R7.L = R1.L >>> 2; -R0.L = R2.L >>> 2; -R1.L = R3.L >>> 2; -R2.L = R4.L >>> 2; -R3.L = R5.L >>> 2; -R4.L = R6.L >>> 2; -R5.L = R7.L >>> 2; -CHECKREG r0, 0x0300FFFC; -CHECKREG r1, 0x03000C00; -CHECKREG r2, 0x00201001; -CHECKREG r3, 0x03001401; -CHECKREG r4, 0x03000100; -CHECKREG r5, 0x03000100; -CHECKREG r6, 0x03000400; -CHECKREG r7, 0x03000400; - -imm32 r0, 0x40001001; -imm32 r1, 0x40001001; -imm32 r2, 0x40002002; -R3.L = -16; -imm32 r4, 0x40004004; -imm32 r5, 0x40005005; -imm32 r6, 0x40006006; -imm32 r7, 0x40007007; -R5.L = R0.L >>> 13; -R6.L = R1.L >>> 13; -R7.L = R2.L >>> 13; -R0.L = R3.L >>> 13; -R1.L = R4.L >>> 13; -R2.L = R5.L >>> 13; -R3.L = R6.L >>> 13; -R4.L = R7.L >>> 13; -CHECKREG r0, 0x4000FFFF; -CHECKREG r1, 0x40000002; -CHECKREG r2, 0x40000000; -CHECKREG r3, 0x03000000; -CHECKREG r4, 0x40000000; -CHECKREG r5, 0x40000000; -CHECKREG r6, 0x40000000; -CHECKREG r7, 0x40000001; - -// d_lo = ashift (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x50000000; -imm32 r1, 0x50010000; -imm32 r2, 0x50020000; -imm32 r3, 0x50030000; -imm32 r4, 0x50040000; -imm32 r5, 0x50050000; -imm32 r6, 0x50060000; -imm32 r7, 0x50070000; -R3.L = R0.H >>> 10; -R4.L = R1.H >>> 10; -R5.L = R2.H >>> 10; -R6.L = R3.H >>> 10; -R7.L = R4.H >>> 10; -R0.L = R5.H >>> 10; -R1.L = R6.H >>> 10; -R2.L = R7.H >>> 10; -CHECKREG r0, 0x50000014; -CHECKREG r1, 0x50010014; -CHECKREG r2, 0x50020014; -CHECKREG r3, 0x50030014; -CHECKREG r4, 0x50040014; -CHECKREG r5, 0x50050014; -CHECKREG r6, 0x50060014; -CHECKREG r7, 0x50070014; - -imm32 r0, 0x10016000; -R1.L = -1; -imm32 r2, 0x20026000; -imm32 r3, 0x30036000; -imm32 r4, 0x40046000; -imm32 r5, 0x50056000; -imm32 r6, 0x60060000; -imm32 r7, 0x70076000; -R0.L = R0.H >>> 11; -R1.L = R1.H >>> 11; -R2.L = R2.H >>> 11; -R3.L = R3.H >>> 11; -R4.L = R4.H >>> 11; -R5.L = R5.H >>> 11; -R6.L = R6.H >>> 11; -R7.L = R7.H >>> 11; -CHECKREG r0, 0x10010002; -CHECKREG r1, 0x5001000A; -CHECKREG r2, 0x20020004; -CHECKREG r3, 0x30030006; -CHECKREG r4, 0x40040008; -CHECKREG r5, 0x5005000A; -CHECKREG r6, 0x6006000C; -CHECKREG r7, 0x7007000E; - - -imm32 r0, 0x10010700; -imm32 r1, 0x10010700; -R2.L = -15; -imm32 r3, 0x30030700; -imm32 r4, 0x40040000; -imm32 r5, 0x50050700; -imm32 r6, 0x60060000; -imm32 r7, 0x70070700; -R0.L = R0.H >>> 15; -R1.L = R1.H >>> 15; -R2.L = R2.H >>> 15; -R3.L = R3.H >>> 15; -R4.L = R4.H >>> 15; -R5.L = R5.H >>> 15; -R6.L = R6.H >>> 15; -R7.L = R7.H >>> 15; -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -CHECKREG r2, 0x20020000; -CHECKREG r3, 0x30030000; -CHECKREG r4, 0x40040000; -CHECKREG r5, 0x50050000; -CHECKREG r6, 0x60060000; -CHECKREG r7, 0x70070000; - -imm32 r0, 0x18010001; -imm32 r1, 0x18010001; -imm32 r2, 0x28020002; -R3.L = -16; -imm32 r4, 0x48040004; -imm32 r5, 0x58050005; -imm32 r6, 0x68060006; -imm32 r7, 0x78070007; -R0.L = R0.H >>> 13; -R1.L = R1.H >>> 13; -R2.L = R2.H >>> 13; -R3.L = R3.H >>> 13; -R4.L = R4.H >>> 13; -R5.L = R5.H >>> 13; -R6.L = R6.H >>> 13; -R7.L = R7.H >>> 13; -CHECKREG r0, 0x18010000; -CHECKREG r1, 0x18010000; -CHECKREG r2, 0x28020001; -CHECKREG r3, 0x30030001; -CHECKREG r4, 0x48040002; -CHECKREG r5, 0x58050002; -CHECKREG r6, 0x68060003; -CHECKREG r7, 0x78070003; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x09000091; -imm32 r1, 0x09000091; -imm32 r2, 0x09000092; -imm32 r3, 0x09000093; -imm32 r4, 0x09000090; -imm32 r5, 0x09000095; -imm32 r6, 0x09000096; -imm32 r7, 0x09000097; -R0.H = R0.L >>> 14; -R1.H = R1.L >>> 14; -R2.H = R2.L >>> 14; -R3.H = R3.L >>> 14; -R4.H = R4.L >>> 14; -R5.H = R5.L >>> 14; -R6.H = R6.L >>> 14; -R7.H = R7.L >>> 14; -CHECKREG r0, 0x00000091; -CHECKREG r1, 0x00000091; -CHECKREG r2, 0x00000092; -CHECKREG r3, 0x00000093; -CHECKREG r4, 0x00000090; -CHECKREG r5, 0x00000095; -CHECKREG r6, 0x00000096; -CHECKREG r7, 0x00000097; - -imm32 r0, 0xa0000001; -imm32 r1, 0xa0000001; -imm32 r2, 0xa0000002; -imm32 r3, 0xa0000003; -imm32 r4, 0xa0000004; -R5.L = -1; -imm32 r6, 0xa0000006; -imm32 r7, 0xa0000007; -R0.H = R0.L >>> 15; -R1.H = R1.L >>> 15; -R2.H = R2.L >>> 15; -R3.H = R3.L >>> 15; -R4.H = R4.L >>> 15; -R5.H = R5.L >>> 15; -R6.H = R6.L >>> 15; -R7.H = R7.L >>> 15; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00000003; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x00000007; - - -imm32 r0, 0xb0001001; -imm32 r1, 0xb0001001; -imm32 r1, 0xb0002002; -imm32 r3, 0xb0003003; -imm32 r4, 0xb0004004; -imm32 r5, 0xb0005005; -R6.L = -15; -imm32 r7, 0xb0007007; -R0.H = R0.L >>> 6; -R1.H = R1.L >>> 6; -R2.H = R2.L >>> 6; -R3.H = R3.L >>> 6; -R4.H = R4.L >>> 6; -R5.H = R5.L >>> 6; -R6.H = R6.L >>> 6; -R7.H = R7.L >>> 6; -CHECKREG r0, 0x00401001; -CHECKREG r1, 0x00802002; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00C03003; -CHECKREG r4, 0x01004004; -CHECKREG r5, 0x01405005; -CHECKREG r6, 0xFFFFFFF1; -CHECKREG r7, 0x01C07007; - -imm32 r0, 0x0c001c01; -imm32 r1, 0x0c002c01; -imm32 r2, 0x0c002c02; -imm32 r3, 0x0c003c03; -imm32 r4, 0x0c004c04; -imm32 r5, 0x0c005c05; -imm32 r6, 0x0c006c06; -R7.L = -16; -R0.H = R0.L >>> 7; -R1.H = R1.L >>> 7; -R2.H = R2.L >>> 7; -R3.H = R3.L >>> 7; -R4.H = R4.L >>> 7; -R5.H = R5.L >>> 7; -R6.H = R6.L >>> 7; -R7.H = R7.L >>> 7; -CHECKREG r0, 0x00381C01; -CHECKREG r1, 0x00582C01; -CHECKREG r2, 0x00582C02; -CHECKREG r3, 0x00783C03; -CHECKREG r4, 0x00984C04; -CHECKREG r5, 0x00B85C05; -CHECKREG r6, 0x00D86C06; -CHECKREG r7, 0xFFFFFFF0; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x0d01d000; -imm32 r1, 0x0d01d000; -imm32 r2, 0x0d02d000; -imm32 r3, 0x0d03d000; -R4.L = -1; -imm32 r5, 0x0d05d000; -imm32 r6, 0x0d06d000; -imm32 r7, 0x0d07d000; -R0.H = R0.H >>> 4; -R1.H = R1.H >>> 4; -R2.H = R2.H >>> 4; -R3.H = R3.H >>> 4; -R4.H = R4.H >>> 4; -R5.H = R5.H >>> 4; -R6.H = R6.H >>> 4; -R7.H = R6.H >>> 4; -CHECKREG r0, 0x00D0D000; -CHECKREG r1, 0x00D0D000; -CHECKREG r2, 0x00D0D000; -CHECKREG r3, 0x00D0D000; -CHECKREG r4, 0x0009FFFF; -CHECKREG r5, 0x00D0D000; -CHECKREG r6, 0x00D0D000; -CHECKREG r7, 0x000DD000; - -imm32 r0, 0x1e010000; -imm32 r1, 0x1e010000; -imm32 r2, 0x2e020000; -imm32 r3, 0x3e030000; -imm32 r4, 0x4e040000; -R5.L = -1; -imm32 r6, 0x6e060000; -imm32 r7, 0x7e070000; -R7.H = R0.H >>> 15; -R6.H = R1.H >>> 15; -R0.H = R2.H >>> 15; -R1.H = R3.H >>> 15; -R2.H = R4.H >>> 15; -R3.H = R5.H >>> 15; -R4.H = R6.H >>> 15; -R5.H = R7.H >>> 15; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x0000FFFF; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x1f010000; -imm32 r1, 0x1f010000; -imm32 r2, 0x2f020000; -imm32 r3, 0x3f030000; -imm32 r4, 0x4f040000; -imm32 r5, 0x5f050000; -R6.L = -15; -imm32 r7, 0x70070000; -R6.H = R0.H >>> 6; -R7.H = R1.H >>> 6; -R5.H = R2.H >>> 6; -R0.H = R3.H >>> 6; -R1.H = R4.H >>> 6; -R2.H = R5.H >>> 6; -R3.H = R6.H >>> 6; -R4.H = R7.H >>> 6; -CHECKREG r0, 0x00FC0000; -CHECKREG r1, 0x013C0000; -CHECKREG r2, 0x00020000; -CHECKREG r3, 0x00010000; -CHECKREG r4, 0x00010000; -CHECKREG r5, 0x00BC0000; -CHECKREG r6, 0x007CFFF1; -CHECKREG r7, 0x007C0000; - -imm32 r0, 0x11010a00; -imm32 r1, 0x11010b00; -imm32 r2, 0x21020d00; -imm32 r2, 0x31030c00; -imm32 r4, 0x41040d00; -imm32 r5, 0x51050e00; -imm32 r6, 0x610600f0; -R7.L = -16; -R5.H = R0.H >>> 7; -R6.H = R1.H >>> 7; -R7.H = R2.H >>> 7; -R2.H = R3.H >>> 7; -R3.H = R4.H >>> 7; -R4.H = R5.H >>> 7; -R0.H = R6.H >>> 7; -R1.H = R7.H >>> 7; -CHECKREG r0, 0x00000A00; -CHECKREG r1, 0x00000B00; -CHECKREG r2, 0x00000C00; -CHECKREG r3, 0x00820000; -CHECKREG r4, 0x00000D00; -CHECKREG r5, 0x00220E00; -CHECKREG r6, 0x002200F0; -CHECKREG r7, 0x0062FFF0; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp_s.s deleted file mode 100644 index 6429fb1..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp_s.s +++ /dev/null @@ -1,422 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_ahalf_rp_s/c_dsp32shiftim_ahalf_rp_s.dsp -// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated -# mach: bfin - -.include "testutils.inc" - start - - - -// Ashift : positive data, count (+)=right (half reg) -// d_lo = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -R0.L = -1; -imm32 r1, 0x00010001; -imm32 r2, 0x00010002; -imm32 r3, 0x00010003; -imm32 r4, 0x00010004; -imm32 r5, 0x00010005; -imm32 r6, 0x00010006; -imm32 r7, 0x00010007; -R0.L = R0.L >>> 1; -R1.L = R1.L >>> 1; -R2.L = R2.L >>> 1; -R3.L = R3.L >>> 1; -R4.L = R4.L >>> 1; -R5.L = R5.L >>> 1; -R6.L = R6.L >>> 1; -R7.L = R7.L >>> 1; -CHECKREG r0, 0x0000FFFF; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x00010001; -CHECKREG r3, 0x00010001; -CHECKREG r4, 0x00010002; -CHECKREG r5, 0x00010002; -CHECKREG r6, 0x00010003; -CHECKREG r7, 0x00010003; - -imm32 r0, 0x00201001; -R1.L = -1; -imm32 r2, 0x00202002; -imm32 r3, 0x00203003; -imm32 r4, 0x00204004; -imm32 r5, 0x00205005; -imm32 r6, 0x00206006; -imm32 r7, 0x00207007; -R7.L = R0.L >>> 5; -R0.L = R1.L >>> 5; -R1.L = R2.L >>> 5; -R2.L = R3.L >>> 5; -R3.L = R4.L >>> 5; -R4.L = R5.L >>> 5; -R5.L = R6.L >>> 5; -R6.L = R7.L >>> 5; -CHECKREG r0, 0x0020FFFF; -CHECKREG r1, 0x00010100; -CHECKREG r2, 0x00200180; -CHECKREG r3, 0x00200200; -CHECKREG r4, 0x00200280; -CHECKREG r5, 0x00200300; -CHECKREG r6, 0x00200004; -CHECKREG r7, 0x00200080; - - -imm32 r0, 0x03001001; -imm32 r1, 0x03001001; -R2.L = -15; -imm32 r3, 0x03003003; -imm32 r4, 0x03004004; -imm32 r5, 0x03005005; -imm32 r6, 0x03006006; -imm32 r7, 0x03007007; -R6.L = R0.L >>> 2; -R7.L = R1.L >>> 2; -R0.L = R2.L >>> 2; -R1.L = R3.L >>> 2; -R2.L = R4.L >>> 2; -R3.L = R5.L >>> 2; -R4.L = R6.L >>> 2; -R5.L = R7.L >>> 2; -CHECKREG r0, 0x0300FFFC; -CHECKREG r1, 0x03000C00; -CHECKREG r2, 0x00201001; -CHECKREG r3, 0x03001401; -CHECKREG r4, 0x03000100; -CHECKREG r5, 0x03000100; -CHECKREG r6, 0x03000400; -CHECKREG r7, 0x03000400; - -imm32 r0, 0x40001001; -imm32 r1, 0x40001001; -imm32 r2, 0x40002002; -R3.L = -16; -imm32 r4, 0x40004004; -imm32 r5, 0x40005005; -imm32 r6, 0x40006006; -imm32 r7, 0x40007007; -R5.L = R0.L >>> 13; -R6.L = R1.L >>> 13; -R7.L = R2.L >>> 13; -R0.L = R3.L >>> 13; -R1.L = R4.L >>> 13; -R2.L = R5.L >>> 13; -R3.L = R6.L >>> 13; -R4.L = R7.L >>> 13; -CHECKREG r0, 0x4000FFFF; -CHECKREG r1, 0x40000002; -CHECKREG r2, 0x40000000; -CHECKREG r3, 0x03000000; -CHECKREG r4, 0x40000000; -CHECKREG r5, 0x40000000; -CHECKREG r6, 0x40000000; -CHECKREG r7, 0x40000001; - -// d_lo = ashift (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x50000000; -imm32 r1, 0x50010000; -imm32 r2, 0x50020000; -imm32 r3, 0x50030000; -imm32 r4, 0x50040000; -imm32 r5, 0x50050000; -imm32 r6, 0x50060000; -imm32 r7, 0x50070000; -R3.L = R0.H >>> 10; -R4.L = R1.H >>> 10; -R5.L = R2.H >>> 10; -R6.L = R3.H >>> 10; -R7.L = R4.H >>> 10; -R0.L = R5.H >>> 10; -R1.L = R6.H >>> 10; -R2.L = R7.H >>> 10; -CHECKREG r0, 0x50000014; -CHECKREG r1, 0x50010014; -CHECKREG r2, 0x50020014; -CHECKREG r3, 0x50030014; -CHECKREG r4, 0x50040014; -CHECKREG r5, 0x50050014; -CHECKREG r6, 0x50060014; -CHECKREG r7, 0x50070014; - -imm32 r0, 0x10016000; -R1.L = -1; -imm32 r2, 0x20026000; -imm32 r3, 0x30036000; -imm32 r4, 0x40046000; -imm32 r5, 0x50056000; -imm32 r6, 0x60060000; -imm32 r7, 0x70076000; -R0.L = R0.H >>> 11; -R1.L = R1.H >>> 11; -R2.L = R2.H >>> 11; -R3.L = R3.H >>> 11; -R4.L = R4.H >>> 11; -R5.L = R5.H >>> 11; -R6.L = R6.H >>> 11; -R7.L = R7.H >>> 11; -CHECKREG r0, 0x10010002; -CHECKREG r1, 0x5001000A; -CHECKREG r2, 0x20020004; -CHECKREG r3, 0x30030006; -CHECKREG r4, 0x40040008; -CHECKREG r5, 0x5005000A; -CHECKREG r6, 0x6006000C; -CHECKREG r7, 0x7007000E; - - -imm32 r0, 0x10010700; -imm32 r1, 0x10010700; -R2.L = -15; -imm32 r3, 0x30030700; -imm32 r4, 0x40040000; -imm32 r5, 0x50050700; -imm32 r6, 0x60060000; -imm32 r7, 0x70070700; -R0.L = R0.H >>> 15; -R1.L = R1.H >>> 15; -R2.L = R2.H >>> 15; -R3.L = R3.H >>> 15; -R4.L = R4.H >>> 15; -R5.L = R5.H >>> 15; -R6.L = R6.H >>> 15; -R7.L = R7.H >>> 15; -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -CHECKREG r2, 0x20020000; -CHECKREG r3, 0x30030000; -CHECKREG r4, 0x40040000; -CHECKREG r5, 0x50050000; -CHECKREG r6, 0x60060000; -CHECKREG r7, 0x70070000; - -imm32 r0, 0x18010001; -imm32 r1, 0x18010001; -imm32 r2, 0x28020002; -R3.L = -16; -imm32 r4, 0x48040004; -imm32 r5, 0x58050005; -imm32 r6, 0x68060006; -imm32 r7, 0x78070007; -R0.L = R0.H >>> 13; -R1.L = R1.H >>> 13; -R2.L = R2.H >>> 13; -R3.L = R3.H >>> 13; -R4.L = R4.H >>> 13; -R5.L = R5.H >>> 13; -R6.L = R6.H >>> 13; -R7.L = R7.H >>> 13; -CHECKREG r0, 0x18010000; -CHECKREG r1, 0x18010000; -CHECKREG r2, 0x28020001; -CHECKREG r3, 0x30030001; -CHECKREG r4, 0x48040002; -CHECKREG r5, 0x58050002; -CHECKREG r6, 0x68060003; -CHECKREG r7, 0x78070003; - -// d_hi = ashft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x09000091; -imm32 r1, 0x09000091; -imm32 r2, 0x09000092; -imm32 r3, 0x09000093; -imm32 r4, 0x09000090; -imm32 r5, 0x09000095; -imm32 r6, 0x09000096; -imm32 r7, 0x09000097; -R0.H = R0.L >>> 14; -R1.H = R1.L >>> 14; -R2.H = R2.L >>> 14; -R3.H = R3.L >>> 14; -R4.H = R4.L >>> 14; -R5.H = R5.L >>> 14; -R6.H = R6.L >>> 14; -R7.H = R7.L >>> 14; -CHECKREG r0, 0x00000091; -CHECKREG r1, 0x00000091; -CHECKREG r2, 0x00000092; -CHECKREG r3, 0x00000093; -CHECKREG r4, 0x00000090; -CHECKREG r5, 0x00000095; -CHECKREG r6, 0x00000096; -CHECKREG r7, 0x00000097; - -imm32 r0, 0xa0000001; -imm32 r1, 0xa0000001; -imm32 r2, 0xa0000002; -imm32 r3, 0xa0000003; -imm32 r4, 0xa0000004; -R5.L = -1; -imm32 r6, 0xa0000006; -imm32 r7, 0xa0000007; -R0.H = R0.L >>> 15; -R1.H = R1.L >>> 15; -R2.H = R2.L >>> 15; -R3.H = R3.L >>> 15; -R4.H = R4.L >>> 15; -R5.H = R5.L >>> 15; -R6.H = R6.L >>> 15; -R7.H = R7.L >>> 15; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00000003; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0xFFFFFFFF; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x00000007; - - -imm32 r0, 0xb0001001; -imm32 r1, 0xb0001001; -imm32 r1, 0xb0002002; -imm32 r3, 0xb0003003; -imm32 r4, 0xb0004004; -imm32 r5, 0xb0005005; -R6.L = -15; -imm32 r7, 0xb0007007; -R0.H = R0.L >>> 6; -R1.H = R1.L >>> 6; -R2.H = R2.L >>> 6; -R3.H = R3.L >>> 6; -R4.H = R4.L >>> 6; -R5.H = R5.L >>> 6; -R6.H = R6.L >>> 6; -R7.H = R7.L >>> 6; -CHECKREG r0, 0x00401001; -CHECKREG r1, 0x00802002; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00C03003; -CHECKREG r4, 0x01004004; -CHECKREG r5, 0x01405005; -CHECKREG r6, 0xFFFFFFF1; -CHECKREG r7, 0x01C07007; - -imm32 r0, 0x0c001c01; -imm32 r1, 0x0c002c01; -imm32 r2, 0x0c002c02; -imm32 r3, 0x0c003c03; -imm32 r4, 0x0c004c04; -imm32 r5, 0x0c005c05; -imm32 r6, 0x0c006c06; -R7.L = -16; -R0.H = R0.L >>> 7; -R1.H = R1.L >>> 7; -R2.H = R2.L >>> 7; -R3.H = R3.L >>> 7; -R4.H = R4.L >>> 7; -R5.H = R5.L >>> 7; -R6.H = R6.L >>> 7; -R7.H = R7.L >>> 7; -CHECKREG r0, 0x00381C01; -CHECKREG r1, 0x00582C01; -CHECKREG r2, 0x00582C02; -CHECKREG r3, 0x00783C03; -CHECKREG r4, 0x00984C04; -CHECKREG r5, 0x00B85C05; -CHECKREG r6, 0x00D86C06; -CHECKREG r7, 0xFFFFFFF0; - -// d_lo = ashft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x0d01d000; -imm32 r1, 0x0d01d000; -imm32 r2, 0x0d02d000; -imm32 r3, 0x0d03d000; -R4.L = -1; -imm32 r5, 0x0d05d000; -imm32 r6, 0x0d06d000; -imm32 r7, 0x0d07d000; -R0.H = R0.H >>> 4; -R1.H = R1.H >>> 4; -R2.H = R2.H >>> 4; -R3.H = R3.H >>> 4; -R4.H = R4.H >>> 4; -R5.H = R5.H >>> 4; -R6.H = R6.H >>> 4; -R7.H = R6.H >>> 4; -CHECKREG r0, 0x00D0D000; -CHECKREG r1, 0x00D0D000; -CHECKREG r2, 0x00D0D000; -CHECKREG r3, 0x00D0D000; -CHECKREG r4, 0x0009FFFF; -CHECKREG r5, 0x00D0D000; -CHECKREG r6, 0x00D0D000; -CHECKREG r7, 0x000DD000; - -imm32 r0, 0x1e010000; -imm32 r1, 0x1e010000; -imm32 r2, 0x2e020000; -imm32 r3, 0x3e030000; -imm32 r4, 0x4e040000; -R5.L = -1; -imm32 r6, 0x6e060000; -imm32 r7, 0x7e070000; -R7.H = R0.H >>> 15; -R6.H = R1.H >>> 15; -R0.H = R2.H >>> 15; -R1.H = R3.H >>> 15; -R2.H = R4.H >>> 15; -R3.H = R5.H >>> 15; -R4.H = R6.H >>> 15; -R5.H = R7.H >>> 15; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x0000FFFF; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0x1f010000; -imm32 r1, 0x1f010000; -imm32 r2, 0x2f020000; -imm32 r3, 0x3f030000; -imm32 r4, 0x4f040000; -imm32 r5, 0x5f050000; -R6.L = -15; -imm32 r7, 0x70070000; -R6.H = R0.H >>> 6; -R7.H = R1.H >>> 6; -R5.H = R2.H >>> 6; -R0.H = R3.H >>> 6; -R1.H = R4.H >>> 6; -R2.H = R5.H >>> 6; -R3.H = R6.H >>> 6; -R4.H = R7.H >>> 6; -CHECKREG r0, 0x00FC0000; -CHECKREG r1, 0x013C0000; -CHECKREG r2, 0x00020000; -CHECKREG r3, 0x00010000; -CHECKREG r4, 0x00010000; -CHECKREG r5, 0x00BC0000; -CHECKREG r6, 0x007CFFF1; -CHECKREG r7, 0x007C0000; - -imm32 r0, 0x11010a00; -imm32 r1, 0x11010b00; -imm32 r2, 0x21020d00; -imm32 r2, 0x31030c00; -imm32 r4, 0x41040d00; -imm32 r5, 0x51050e00; -imm32 r6, 0x610600f0; -R7.L = -16; -R5.H = R0.H >>> 7; -R6.H = R1.H >>> 7; -R7.H = R2.H >>> 7; -R2.H = R3.H >>> 7; -R3.H = R4.H >>> 7; -R4.H = R5.H >>> 7; -R0.H = R6.H >>> 7; -R1.H = R7.H >>> 7; -CHECKREG r0, 0x00000A00; -CHECKREG r1, 0x00000B00; -CHECKREG r2, 0x00000C00; -CHECKREG r3, 0x00820000; -CHECKREG r4, 0x00000D00; -CHECKREG r5, 0x00220E00; -CHECKREG r6, 0x002200F0; -CHECKREG r7, 0x0062FFF0; -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh.s deleted file mode 100644 index 79d1924..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh.s +++ /dev/null @@ -1,65 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_ahh/c_dsp32shiftim_ahh.dsp -# mach: bfin - -.include "testutils.inc" - start - - -// Spec Reference: dsp32shiftimm ashift: ashift / ashift - - - -imm32 r0, 0x01230abc; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R0 = R0 << 0 (V); -R1 = R1 << 3 (V); -R2 = R2 << 5 (V); -R3 = R3 << 8 (V); -R4 = R4 << 9 (V); -R5 = R5 << 15 (V); -R6 = R6 << 7 (V); -R7 = R7 << 13 (V); -CHECKREG r0, 0x01230ABC; -CHECKREG r1, 0x91A0B3C0; -CHECKREG r2, 0x68A0F120; -CHECKREG r3, 0x56009A00; -CHECKREG r4, 0xCE005600; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0xC480E680; -CHECKREG r7, 0x4000C000; - -imm32 r0, 0x01230000; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R7 = R0 >>> 1 (V); -R0 = R1 >>> 8 (V); -R1 = R2 >>> 14 (V); -R2 = R3 >>> 15 (V); -R3 = R4 >>> 11 (V); -R4 = R5 >>> 4 (V); -R5 = R6 >>> 9 (V); -R6 = R7 >>> 6 (V); -CHECKREG r0, 0x00120056; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x0008FFF1; -CHECKREG r4, 0x0567F9AB; -CHECKREG r5, 0x0033FFD5; -CHECKREG r6, 0x00020000; -CHECKREG r7, 0x00910000; - - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh_s.s deleted file mode 100644 index 9e69f2a..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh_s.s +++ /dev/null @@ -1,65 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_ahh_s/c_dsp32shiftim_ahh_s.dsp -# mach: bfin - -.include "testutils.inc" - start - - -// Spec Reference: dsp32shiftimm ashift: ashift / ashift saturated - - - -imm32 r0, 0x01230abc; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R0 = R0 << 0 (V , S); -R1 = R1 << 3 (V , S); -R2 = R2 << 5 (V , S); -R3 = R3 << 8 (V , S); -R4 = R4 << 9 (V , S); -R5 = R5 << 15 (V , S); -R6 = R6 << 7 (V , S); -R7 = R7 << 13 (V , S); -CHECKREG r0, 0x01230ABC; -CHECKREG r1, 0x7FFF7FFF; -CHECKREG r2, 0x7FFF7FFF; -CHECKREG r3, 0x7FFF7FFF; -CHECKREG r4, 0x7FFF8000; -CHECKREG r5, 0x7FFF8000; -CHECKREG r6, 0x7FFF8000; -CHECKREG r7, 0x7FFF8000; - -imm32 r0, 0x01230000; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R7 = R0 >>> 1 (V, S); -R0 = R1 >>> 8 (V, S); -R1 = R2 >>> 14 (V, S); -R2 = R3 >>> 15 (V, S); -R3 = R4 >>> 11 (V, S); -R4 = R5 >>> 4 (V, S); -R5 = R6 >>> 9 (V, S); -R6 = R7 >>> 6 (V, S); -CHECKREG r0, 0x00120056; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x0008FFF1; -CHECKREG r4, 0x0567F9AB; -CHECKREG r5, 0x0033FFD5; -CHECKREG r6, 0x00020000; -CHECKREG r7, 0x00910000; - - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s deleted file mode 100644 index d1c0c20..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s +++ /dev/null @@ -1,149 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp -# mach: bfin - -.include "testutils.inc" - start - - -// Spec Reference: dsp32shiftimm ashift: mix - - - -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -// Ashift : positive data, count (+)=left (half reg) -imm32 r0, 0x00010001; -imm32 r1, 1; -imm32 r2, 0x00020002; -imm32 r3, 2; -R4.H = R0.H << 1; -R4.L = R0.L << 1; /* r4 = 0x00020002 */ -R5.H = R2.H << 2; -R5.L = R2.L << 2; /* r5 = 0x00080008 */ -R6 = R0 << 1 (V); /* r6 = 0x00020002 */ -R7 = R2 << 2 (V); /* r7 = 0x00080008 */ -CHECKREG r4, 0x00020002; -CHECKREG r5, 0x00080008; -CHECKREG r6, 0x00020002; -CHECKREG r7, 0x00080008; - -imm32 r1, 3; -imm32 r3, 4; -R6 = R0 << 3; /* r6 = 0x00080010 */ -R7 = R2 << 4; -CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ -CHECKREG r7, 0x00200020; - -A0 = 0; -A0.L = R0.L; -A0.H = R0.H; -A0 = A0 << 3; /* a0 = 0x00080008 */ -R5 = A0.w; /* r5 = 0x00080008 */ -CHECKREG r5, 0x00080008; - -imm32 r4, 0x30000003; -imm32 r1, 1; -R5 = R4 << 1; /* r5 = 0x60000006 */ - -imm32 r1, 2; -R6 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */ -CHECKREG r5, 0x60000006; -CHECKREG r6, 0xc000000c; - - -// Ashift : count (-)=right (half reg) -imm32 r0, 0x10001000; -imm32 r1, -1; -imm32 r2, 0x10001000; -imm32 r3, -2; -R4.H = R0.H >>> 1; -R4.L = R0.L >>> 1; /* r4 = 0x08000800 */ -R5.H = R2.H >>> 2; -R5.L = R2.L >>> 2; /* r4 = 0x04000400 */ -R6 = R0 >>> 1 (V); /* r4 = 0x08000800 */ -R7 = R2 >>> 2 (V); /* r4 = 0x04000400 */ -CHECKREG r4, 0x08000800; -CHECKREG r5, 0x04000400; -CHECKREG r6, 0x08000800; -CHECKREG r7, 0x04000400; - -// Ashift : (full reg) -imm32 r1, -3; -imm32 r3, -4; -R6 = R0 >>> 3; /* r6 = 0x02000200 */ -R7 = R2 >>> 4; /* r7 = 0x01000100 */ -CHECKREG r6, 0x02000200; -CHECKREG r7, 0x01000100; - -// NEGATIVE -// Ashift : NEGATIVE data, count (+)=left (half reg) -imm32 r0, 0xc00f800f; -imm32 r1, 1; -imm32 r2, 0xe00fe00f; -imm32 r3, 2; -R4.H = R0.H << 1; -R4.L = R0.L << 1 (S); /* r4 = 0x801e801e */ -R5.H = R2.H << 2; -R5.L = R2.L << 2; /* r4 = 0x803c803c */ -CHECKREG r4, 0x801e8000; -CHECKREG r5, 0x803c803c; - -imm32 r0, 0xc80fe00f; -imm32 r2, 0xe40fe00f; -imm32 r1, 4; -imm32 r3, 5; -R6 = R0 << 4; /* r6 = 0x80fe00f0 */ -R7 = R2 << 5; /* r7 = 0x81fc01e0 */ -CHECKREG r6, 0x80fe00f0; -CHECKREG r7, 0x81fc01e0; - -imm32 r0, 0xf80fe00f; -imm32 r2, 0xfc0fe00f; -R6 = R0 << 4 (S); /* r6 = 0x80fe00f0 */ -R7 = R2 << 5 (S); /* r7 = 0x81fc01e0 */ -CHECKREG r6, 0x80fe00f0; -CHECKREG r7, 0x81fc01e0; - -imm32 r0, 0xc80fe00f; -imm32 r2, 0xe40fe00f; -R6 = R0 << 4 (S); /* r6 = 0x80000000 zero bubble tru MSB */ -R7 = R2 << 5 (S); /* r7 = 0x80000000 */ -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x80000000; - -imm32 r0, 0xFFFFFFF4; -imm32 r2, 0xFFF00001; -R6 = R0 << 31 (S); /* r6 = 0x80000000 */ -R7 = R2 << 31 (S); /* r7 = 0x80000000 */ -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x80000000; - - -// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok -imm32 r0, 0x80f080f0; -imm32 r1, -1; -imm32 r2, 0x80f080f0; -imm32 r3, -2; -R4.H = R0.H >>> 1; -R4.L = R0.L >>> 1; /* r4 = 0xc078c078 */ -R5.H = R2.H >>> 2; -R5.L = R2.L >>> 2; /* r4 = 0xe03ce03c */ -CHECKREG r4, 0xc078c078; -CHECKREG r5, 0xe03ce03c; -R6 = R0 >>> 1 (V); /* r6 = 0xc078c078 */ -R7 = R2 >>> 2 (V); /* r7 = 0xe03ce03c */ -CHECKREG r6, 0xc078c078; -CHECKREG r7, 0xe03ce03c; - -imm32 r1, -3; -imm32 r3, -4; -R6 = R0 >>> 3; /* r6 = 0xf01e101e */ -R7 = R2 >>> 4; /* r7 = 0xf80f080f */ -CHECKREG r6, 0xf01e101e; -CHECKREG r7, 0xf80f080f; - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lf.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lf.s deleted file mode 100644 index 3083173..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_lf.s +++ /dev/null @@ -1,63 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_lf/c_dsp32shiftim_lf.dsp -# mach: bfin - -.include "testutils.inc" - start - - -// Spec Reference: dsp32shiftimm lshift: lshift - - -imm32 r0, 0xa1230001; -imm32 r1, 0x1b345678; -imm32 r2, 0x23c56789; -imm32 r3, 0x34d6789a; -imm32 r4, 0x85a789ab; -imm32 r5, 0x967c9abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb8912cde; -R0 = R0 << 0; -R1 = R1 << 3; -R2 = R2 << 7; -R3 = R3 << 8; -R4 = R4 << 15; -R5 = R5 << 24; -R6 = R6 << 31; -R7 = R7 << 20; -CHECKREG r0, 0xA1230001; -CHECKREG r1, 0xD9A2B3C0; -CHECKREG r2, 0xE2B3C480; -CHECKREG r3, 0xD6789A00; -CHECKREG r4, 0xC4D58000; -CHECKREG r5, 0xBC000000; -CHECKREG r6, 0x80000000; -CHECKREG r7, 0xCDE00000; - -imm32 r0, 0xa1230001; -imm32 r1, 0x1b345678; -imm32 r2, 0x23c56789; -imm32 r3, 0x34d6789a; -imm32 r4, 0x85a789ab; -imm32 r5, 0x967c9abc; -imm32 r6, 0xa789abcd; -imm32 r7, 0xb8912cde; -R6 = R0 >> 1; -R7 = R1 >> 3; -R0 = R2 >> 7; -R1 = R3 >> 8; -R2 = R4 >> 15; -R3 = R5 >> 24; -R4 = R6 >> 31; -R5 = R7 >> 20; -CHECKREG r0, 0x00478ACF; -CHECKREG r1, 0x0034D678; -CHECKREG r2, 0x00010B4F; -CHECKREG r3, 0x00000096; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000036; -CHECKREG r6, 0x50918000; -CHECKREG r7, 0x03668ACF; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_ln.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_ln.s deleted file mode 100644 index 36004fd..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_ln.s +++ /dev/null @@ -1,401 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_lhalf_ln/c_dsp32shiftim_lhalf_ln.dsp -// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) -# mach: bfin - -.include "testutils.inc" - start - - - -// lshift : neg data, count (+)=left (half reg) -// d_lo = lshift (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x0000c001; -imm32 r2, 0x0000c002; -imm32 r3, 0x0000c003; -imm32 r4, 0x0000c004; -imm32 r5, 0x0000c005; -imm32 r6, 0x0000c006; -imm32 r7, 0x0000c007; -R0.L = R0.L << 1; -R1.L = R1.L << 0; -R2.L = R2.L << 0; -R3.L = R3.L << 0; -R4.L = R4.L << 0; -R5.L = R5.L << 0; -R6.L = R6.L << 0; -R7.L = R7.L << 0; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x0000C001; -CHECKREG r2, 0x0000C002; -CHECKREG r3, 0x0000C003; -CHECKREG r4, 0x0000C004; -CHECKREG r5, 0x0000C005; -CHECKREG r6, 0x0000C006; -CHECKREG r7, 0x0000C007; - -imm32 r0, 0x00008001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000d002; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000c005; -imm32 r6, 0x0000d006; -imm32 r7, 0x0000e007; -R1.L = R0.L << 1; -R2.L = R1.L << 2; -R3.L = R2.L << 3; -R4.L = R3.L << 4; -R5.L = R4.L << 5; -R6.L = R5.L << 6; -R7.L = R6.L << 7; -R0.L = R7.L << 8; -imm32 r1, 0x2000d001; -imm32 r2, 0x2000000f; -imm32 r3, 0x2000e003; -imm32 r4, 0x2000f004; -imm32 r5, 0x2200f005; -imm32 r6, 0x2000f006; -imm32 r7, 0x2000f007; -imm32 r0, 0x2000c001; - -R2.L = R0.L << 10; -R3.L = R1.L << 12; -R4.L = R2.L << 13; -R5.L = R3.L << 14; -R6.L = R4.L << 15; -R7.L = R5.L << 15; -R0.L = R6.L << 2; -R1.L = R7.L << 3; -CHECKREG r0, 0x20000000; -CHECKREG r1, 0x20000000; -CHECKREG r2, 0x20000400; -CHECKREG r3, 0x20001000; -CHECKREG r4, 0x20000000; -CHECKREG r5, 0x22000000; -CHECKREG r6, 0x20000000; -CHECKREG r7, 0x20000000; - -imm32 r0, 0x30009001; -imm32 r1, 0x3000a001; -imm32 r2, 0x3000b002; -imm32 r3, 0x30000010; -imm32 r4, 0x3000c004; -imm32 r5, 0x3000d005; -imm32 r6, 0x3000e006; -imm32 r7, 0x3000f007; -R3.L = R0.L << 12; -R4.L = R1.L << 13; -R5.L = R2.L << 14; -R6.L = R3.L << 15; -R7.L = R4.L << 11; -R0.L = R5.L << 12; -R1.L = R6.L << 13; -R2.L = R7.L << 15; -CHECKREG r0, 0x30000000; -CHECKREG r1, 0x30000000; -CHECKREG r2, 0x30000000; -CHECKREG r3, 0x30001000; -CHECKREG r4, 0x30002000; -CHECKREG r5, 0x30008000; -CHECKREG r6, 0x30000000; -CHECKREG r7, 0x30000000; -// RHx by RLx -imm32 r0, 0x00000040; -imm32 r1, 0x00010040; -imm32 r2, 0x00020040; -imm32 r3, 0x00030040; -imm32 r4, 0x00040040; -imm32 r5, 0x00050040; -imm32 r6, 0x00060040; -imm32 r7, 0x00070040; -R0.L = R0.H << 0; -R1.L = R1.H << 1; -R2.L = R2.H << 2; -R3.L = R3.H << 3; -R4.L = R4.H << 4; -R5.L = R5.H << 5; -R6.L = R6.H << 6; -R7.L = R7.H << 7; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010002; -CHECKREG r2, 0x00020008; -CHECKREG r3, 0x00030018; -CHECKREG r4, 0x00040040; -CHECKREG r5, 0x000500A0; -CHECKREG r6, 0x00060180; -CHECKREG r7, 0x00070380; - -imm32 r0, 0x90010000; -imm32 r1, 0x00010001; -imm32 r2, 0x90020000; -imm32 r3, 0x90030000; -imm32 r4, 0x90040000; -imm32 r5, 0x90050000; -imm32 r6, 0x90060000; -imm32 r7, 0x90070000; -R1.L = R0.H << 1; -R2.L = R1.H << 2; -R3.L = R2.H << 3; -R4.L = R3.H << 4; -R5.L = R4.H << 5; -R6.L = R5.H << 6; -R7.L = R6.H << 7; -R0.L = R7.H << 8; -CHECKREG r1, 0x00012002; -CHECKREG r2, 0x90020004; -CHECKREG r3, 0x90038010; -CHECKREG r4, 0x90040030; -CHECKREG r5, 0x90050080; -CHECKREG r6, 0x90060140; -CHECKREG r7, 0x90070300; -CHECKREG r0, 0x90010700; - - -imm32 r0, 0xa0010000; -imm32 r1, 0xa0010000; -imm32 r2, 0xa002000f; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R2.L = R0.H << 15; -R3.L = R1.H << 15; -R4.L = R2.H << 15; -R5.L = R3.H << 15; -R6.L = R4.H << 15; -R7.L = R5.H << 15; -R0.L = R6.H << 15; -R1.L = R7.H << 15; -CHECKREG r0, 0xA0010000; -CHECKREG r1, 0xA0018000; -CHECKREG r2, 0xA0028000; -CHECKREG r3, 0xA0038000; -CHECKREG r4, 0xA0040000; -CHECKREG r5, 0xA0058000; -CHECKREG r6, 0xA0060000; -CHECKREG r7, 0xA0078000; - -imm32 r0, 0xc0010001; -imm32 r1, 0xc0010001; -imm32 r2, 0xc0020002; -imm32 r3, 0xc0030010; -imm32 r4, 0xc0040004; -imm32 r5, 0xc0050005; -imm32 r6, 0xc0060006; -imm32 r7, 0xc0070007; -R3.L = R0.H << 14; -R4.L = R1.H << 14; -R5.L = R2.H << 14; -R6.L = R3.H << 14; -R7.L = R4.H << 14; -R0.L = R5.H << 14; -R1.L = R6.H << 14; -R2.L = R7.H << 14; -CHECKREG r0, 0xC0014000; -CHECKREG r1, 0xC0018000; -CHECKREG r2, 0xC002C000; -CHECKREG r3, 0xC0034000; -CHECKREG r4, 0xC0044000; -CHECKREG r5, 0xC0058000; -CHECKREG r6, 0xC006C000; -CHECKREG r7, 0xC0070000; - -// RLx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = R0.L << 12; -R1.H = R1.L << 12; -R2.H = R2.L << 13; -R3.H = R3.L << 14; -R4.H = R4.L << 15; -R5.H = R5.L << 14; -R6.H = R6.L << 7; -R7.H = R7.L << 8; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x10000001; -CHECKREG r2, 0x40000002; -CHECKREG r3, 0xC0000003; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x40000005; -CHECKREG r6, 0x03000006; -CHECKREG r7, 0x07000007; - -imm32 r0, 0x0000d001; -imm32 r1, 0x00000001; -imm32 r2, 0x0000d002; -imm32 r3, 0x0000d003; -imm32 r4, 0x0000d004; -imm32 r5, 0x0000d005; -imm32 r6, 0x0000d006; -imm32 r7, 0x0000d007; -R1.H = R0.L << 3; -R2.H = R1.L << 4; -R3.H = R2.L << 5; -R4.H = R3.L << 6; -R5.H = R4.L << 7; -R6.H = R5.L << 8; -R7.H = R6.L << 9; -R0.H = R7.L << 8; -CHECKREG r1, 0x80080001; -CHECKREG r2, 0x0010D002; -CHECKREG r3, 0x0040D003; -CHECKREG r4, 0x00C0D004; -CHECKREG r5, 0x0200D005; -CHECKREG r6, 0x0500D006; -CHECKREG r7, 0x0C00D007; -CHECKREG r0, 0x0700D001; - - -imm32 r0, 0x0000e001; -imm32 r1, 0x0000e001; -imm32 r2, 0x0000000f; -imm32 r3, 0x0000e003; -imm32 r4, 0x0000e004; -imm32 r5, 0x0000e005; -imm32 r6, 0x0000e006; -imm32 r7, 0x0000e007; -R2.H = R0.L << 15; -R3.H = R1.L << 15; -R4.H = R2.L << 15; -R5.H = R3.L << 15; -R6.H = R4.L << 15; -R7.H = R5.L << 15; -R0.H = R6.L << 15; -R1.H = R7.L << 15; -CHECKREG r0, 0x0000E001; -CHECKREG r1, 0x8000E001; -CHECKREG r2, 0x8000000F; -CHECKREG r3, 0x8000E003; -CHECKREG r4, 0x8000E004; -CHECKREG r5, 0x8000E005; -CHECKREG r6, 0x0000E006; -CHECKREG r7, 0x8000E007; - -imm32 r0, 0x0000f001; -imm32 r1, 0x0000f001; -imm32 r2, 0x0000f002; -imm32 r3, 0x00000010; -imm32 r4, 0x0000f004; -imm32 r5, 0x0000f005; -imm32 r6, 0x0000f006; -imm32 r7, 0x0000f007; -R3.H = R0.L << 13; -R4.H = R1.L << 13; -R5.H = R2.L << 13; -R6.H = R3.L << 13; -R7.H = R4.L << 13; -R0.H = R5.L << 13; -R1.H = R6.L << 13; -R2.H = R7.L << 13; -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x00010000; -imm32 r2, 0x00020000; -imm32 r3, 0x00030000; -imm32 r4, 0x00040000; -imm32 r5, 0x00050000; -imm32 r6, 0x00060000; -imm32 r7, 0x00070000; -R0.H = R0.H << 0; -R1.H = R1.H << 0; -R2.H = R2.H << 0; -R3.H = R3.H << 0; -R4.H = R4.H << 0; -R5.H = R5.H << 0; -R6.H = R6.H << 0; -R7.H = R7.H << 0; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x00020000; -CHECKREG r3, 0x00030000; -CHECKREG r4, 0x00040000; -CHECKREG r5, 0x00050000; -CHECKREG r6, 0x00060000; -CHECKREG r7, 0x00070000; - -imm32 r0, 0xa0010000; -imm32 r1, 0x00010001; -imm32 r2, 0xa0020000; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R1.H = R0.H << 1; -R2.H = R1.H << 1; -R3.H = R2.H << 1; -R4.H = R3.H << 1; -R5.H = R4.H << 1; -R6.H = R5.H << 1; -R7.H = R6.H << 1; -R0.H = R7.H << 1; -CHECKREG r1, 0x40020001; -CHECKREG r2, 0x80040000; -CHECKREG r3, 0x00080000; -CHECKREG r4, 0x00100000; -CHECKREG r5, 0x00200000; -CHECKREG r6, 0x00400000; -CHECKREG r7, 0x00800000; -CHECKREG r0, 0x01000000; - - -imm32 r0, 0xb0010000; -imm32 r1, 0xb0010000; -imm32 r2, 0xb002000f; -imm32 r3, 0xb0030000; -imm32 r4, 0xb0040000; -imm32 r5, 0xb0050000; -imm32 r6, 0xb0060000; -imm32 r7, 0xb0070000; -R2.H = R0.H << 15; -R3.H = R1.H << 15; -R4.H = R2.H << 15; -R5.H = R3.H << 15; -R6.H = R4.H << 15; -R7.H = R5.H << 15; -R0.H = R6.H << 15; -R1.H = R7.H << 15; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x8000000F; -CHECKREG r3, 0x80000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -imm32 r0, 0xd0010000; -imm32 r1, 0xd0010000; -imm32 r2, 0xd0020000; -imm32 r3, 0xd0030010; -imm32 r4, 0xd0040000; -imm32 r5, 0xd0050000; -imm32 r6, 0xd0060000; -imm32 r7, 0xd0070000; -R6.H = R0.H << 12; -R7.H = R1.H << 12; -R0.H = R2.H << 12; -R1.H = R3.H << 12; -R2.H = R4.H << 12; -R3.H = R5.H << 12; -R4.H = R6.H << 12; -R5.H = R7.H << 12; -CHECKREG r0, 0x20000000; -CHECKREG r1, 0x30000000; -CHECKREG r2, 0x40000000; -CHECKREG r3, 0x50000010; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x10000000; -CHECKREG r7, 0x10000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_lp.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_lp.s deleted file mode 100644 index 53e53f2..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_lp.s +++ /dev/null @@ -1,418 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_lhalf_lp/c_dsp32shiftim_lhalf_lp.dsp -// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) -# mach: bfin - -.include "testutils.inc" - start - - - -// lshift : positive data, count (+)=left (half reg) -// d_lo = lshift (d_lo BY imm5) -// RLx by imm5 -imm32 r0, 0x00100a00; -imm32 r1, 0x00100a01; -imm32 r2, 0x00100a02; -imm32 r3, 0x00100a03; -imm32 r4, 0x00100a04; -imm32 r5, 0x00100a05; -imm32 r6, 0x00100a06; -imm32 r7, 0x00100a07; -R7.L = R0.L << 0; -R0.L = R1.L << 1; -R1.L = R2.L << 2; -R2.L = R3.L << 3; -R3.L = R4.L << 4; -R4.L = R5.L << 5; -R5.L = R6.L << 6; -R6.L = R7.L << 7; -CHECKREG r1, 0x00102808; -CHECKREG r0, 0x00101402; -CHECKREG r2, 0x00105018; -CHECKREG r3, 0x0010A040; -CHECKREG r4, 0x001040A0; -CHECKREG r5, 0x00108180; -CHECKREG r6, 0x00100000; -CHECKREG r7, 0x00100A00; - -imm32 r0, 0x00200018; -imm32 r1, 0x00200019; -imm32 r2, 0x0020001a; -imm32 r3, 0x0020001b; -imm32 r4, 0x0020001c; -imm32 r5, 0x0020001d; -imm32 r6, 0x0020001e; -imm32 r7, 0x0020001f; -R2.L = R0.L << 8; -R3.L = R1.L << 9; -R4.L = R2.L << 10; -R5.L = R3.L << 11; -R6.L = R4.L << 12; -R7.L = R5.L << 13; -R0.L = R6.L << 14; -R1.L = R7.L << 15; -CHECKREG r0, 0x00200000; -CHECKREG r1, 0x00200000; -CHECKREG r2, 0x00201800; -CHECKREG r3, 0x00203200; -CHECKREG r4, 0x00200000; -CHECKREG r5, 0x00200000; -CHECKREG r6, 0x00200000; -CHECKREG r7, 0x00200000; - -imm32 r0, 0x05002001; -imm32 r1, 0x05002001; -imm32 r2, 0x0500000f; -imm32 r3, 0x05002003; -imm32 r4, 0x05002004; -imm32 r5, 0x05002005; -imm32 r6, 0x05002006; -imm32 r7, 0x05002007; -R3.L = R0.L << 0; -R4.L = R1.L << 1; -R5.L = R2.L << 2; -R6.L = R3.L << 3; -R7.L = R4.L << 4; -R0.L = R5.L << 5; -R1.L = R6.L << 6; -R2.L = R7.L << 7; -CHECKREG r0, 0x05000780; -CHECKREG r1, 0x05000200; -CHECKREG r2, 0x05001000; -CHECKREG r3, 0x05002001; -CHECKREG r4, 0x05004002; -CHECKREG r5, 0x0500003C; -CHECKREG r6, 0x05000008; -CHECKREG r7, 0x05000020; - -imm32 r0, 0x03000031; -imm32 r1, 0x03000031; -imm32 r2, 0x03000032; -imm32 r3, 0x03000030; -imm32 r4, 0x03000034; -imm32 r5, 0x03000035; -imm32 r6, 0x03000036; -imm32 r7, 0x03000037; -R4.L = R0.L << 8; -R5.L = R1.L << 9; -R6.L = R2.L << 10; -R7.L = R3.L << 11; -R0.L = R4.L << 12; -R1.L = R5.L << 13; -R2.L = R6.L << 14; -R3.L = R7.L << 15; -CHECKREG r0, 0x03000000; -CHECKREG r1, 0x03000000; -CHECKREG r2, 0x03000000; -CHECKREG r3, 0x03000000; -CHECKREG r4, 0x03003100; -CHECKREG r5, 0x03006200; -CHECKREG r6, 0x0300C800; -CHECKREG r7, 0x03008000; -// RHx by RLx -imm32 r0, 0x03000000; -imm32 r1, 0x03000000; -imm32 r2, 0x03000000; -imm32 r3, 0x03000000; -imm32 r4, 0x03003100; -imm32 r5, 0x03006200; -imm32 r6, 0x0300C800; -imm32 r7, 0x03008000; -R5.L = R0.H << 0; -R6.L = R1.H << 1; -R7.L = R2.H << 2; -R0.L = R3.H << 3; -R1.L = R4.H << 4; -R2.L = R5.H << 5; -R3.L = R6.H << 6; -R4.L = R7.H << 7; -CHECKREG r0, 0x03001800; -CHECKREG r1, 0x03003000; -CHECKREG r2, 0x03006000; -CHECKREG r3, 0x0300C000; -CHECKREG r4, 0x03008000; -CHECKREG r5, 0x03000300; -CHECKREG r6, 0x03000600; -CHECKREG r7, 0x03000C00; - -imm32 r0, 0x05018000; -imm32 r1, 0x05018001; -imm32 r2, 0x05028000; -imm32 r3, 0x05038000; -imm32 r4, 0x05048000; -imm32 r5, 0x05058000; -imm32 r6, 0x05068000; -imm32 r7, 0x05078000; -R6.L = R0.H << 8; -R7.L = R1.H << 9; -R0.L = R2.H << 10; -R1.L = R3.H << 11; -R2.L = R4.H << 12; -R3.L = R5.H << 13; -R4.L = R6.H << 14; -R5.L = R7.H << 15; -CHECKREG r0, 0x05010800; -CHECKREG r1, 0x05011800; -CHECKREG r2, 0x05024000; -CHECKREG r3, 0x0503A000; -CHECKREG r4, 0x05048000; -CHECKREG r5, 0x05058000; -CHECKREG r6, 0x05060100; -CHECKREG r7, 0x05070200; - - -imm32 r0, 0x60019000; -imm32 r1, 0x60019000; -imm32 r2, 0x6002900f; -imm32 r3, 0x60039000; -imm32 r4, 0x60049000; -imm32 r5, 0x60059000; -imm32 r6, 0x60069000; -imm32 r7, 0x60079000; -R7.L = R0.H << 0; -R0.L = R1.H << 1; -R1.L = R2.H << 2; -R2.L = R3.H << 3; -R3.L = R4.H << 4; -R4.L = R5.H << 5; -R5.L = R6.H << 6; -R6.L = R7.H << 7; -CHECKREG r0, 0x6001C002; -CHECKREG r1, 0x60018008; -CHECKREG r2, 0x60020018; -CHECKREG r3, 0x60030040; -CHECKREG r4, 0x600400A0; -CHECKREG r5, 0x60050180; -CHECKREG r6, 0x60060380; -CHECKREG r7, 0x60076001; - -imm32 r0, 0x70010001; -imm32 r1, 0x70010001; -imm32 r2, 0x70020002; -imm32 r3, 0x77030010; -imm32 r4, 0x70040004; -imm32 r5, 0x70050005; -imm32 r6, 0x70060006; -imm32 r7, 0x70070007; -R0.L = R0.H << 8; -R1.L = R1.H << 9; -R2.L = R2.H << 10; -R3.L = R3.H << 11; -R4.L = R4.H << 12; -R5.L = R5.H << 13; -R6.L = R6.H << 14; -R7.L = R7.H << 15; -CHECKREG r0, 0x70010100; -CHECKREG r1, 0x70010200; -CHECKREG r2, 0x70020800; -CHECKREG r3, 0x77031800; -CHECKREG r4, 0x70044000; -CHECKREG r5, 0x7005A000; -CHECKREG r6, 0x70068000; -CHECKREG r7, 0x70078000; - -// d_hi = lshft (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0xa8000000; -imm32 r1, 0xa8000001; -imm32 r2, 0xa8000002; -imm32 r3, 0xa8000003; -imm32 r4, 0xa8000004; -imm32 r5, 0xa8000005; -imm32 r6, 0xa8000006; -imm32 r7, 0xa8000007; -R0.H = R0.L << 0; -R1.H = R1.L << 1; -R2.H = R2.L << 2; -R3.H = R3.L << 3; -R4.H = R4.L << 4; -R5.H = R5.L << 5; -R6.H = R6.L << 6; -R7.H = R7.L << 7; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0x00080002; -CHECKREG r3, 0x00180003; -CHECKREG r4, 0x00400004; -CHECKREG r5, 0x00A00005; -CHECKREG r6, 0x01800006; -CHECKREG r7, 0x03800007; - -imm32 r0, 0xf0090001; -imm32 r1, 0xf0090001; -imm32 r2, 0xf0090002; -imm32 r3, 0xf0090003; -imm32 r4, 0xf0090004; -imm32 r5, 0xf0090005; -imm32 r6, 0xf0000006; -imm32 r7, 0xf0000007; -R1.H = R0.L << 8; -R2.H = R1.L << 9; -R3.H = R2.L << 10; -R4.H = R3.L << 11; -R5.H = R4.L << 12; -R6.H = R5.L << 13; -R7.H = R6.L << 14; -R0.H = R7.L << 15; -CHECKREG r1, 0x01000001; -CHECKREG r2, 0x02000002; -CHECKREG r3, 0x08000003; -CHECKREG r4, 0x18000004; -CHECKREG r5, 0x40000005; -CHECKREG r6, 0xA0000006; -CHECKREG r7, 0x80000007; -CHECKREG r0, 0x80000001; - - -imm32 r0, 0x07000001; -imm32 r1, 0x07000001; -imm32 r2, 0x0700000f; -imm32 r3, 0x07000003; -imm32 r4, 0x07000004; -imm32 r5, 0x07000005; -imm32 r6, 0x07000006; -imm32 r7, 0x07000007; -R3.H = R0.L << 0; -R4.H = R1.L << 1; -R5.H = R2.L << 2; -R6.H = R3.L << 3; -R7.H = R4.L << 4; -R0.H = R5.L << 5; -R1.H = R6.L << 6; -R2.H = R7.L << 7; -CHECKREG r0, 0x00A00001; -CHECKREG r1, 0x01800001; -CHECKREG r2, 0x0380000F; -CHECKREG r3, 0x00010003; -CHECKREG r4, 0x00020004; -CHECKREG r5, 0x003C0005; -CHECKREG r6, 0x00180006; -CHECKREG r7, 0x00400007; - -imm32 r0, 0x00000501; -imm32 r1, 0x00000501; -imm32 r2, 0x00000502; -imm32 r3, 0x00000510; -imm32 r4, 0x00000504; -imm32 r5, 0x00000505; -imm32 r6, 0x00000506; -imm32 r7, 0x00000507; -R4.H = R0.L << 8; -R5.H = R1.L << 9; -R6.H = R2.L << 10; -R7.H = R3.L << 11; -R0.H = R4.L << 12; -R1.H = R5.L << 13; -R2.H = R6.L << 14; -R3.H = R7.L << 15; -CHECKREG r0, 0x40000501; -CHECKREG r1, 0xA0000501; -CHECKREG r2, 0x80000502; -CHECKREG r3, 0x80000510; -CHECKREG r4, 0x01000504; -CHECKREG r5, 0x02000505; -CHECKREG r6, 0x08000506; -CHECKREG r7, 0x80000507; - -imm32 r0, 0x00a00800; -imm32 r1, 0x00a10800; -imm32 r2, 0x00a20800; -imm32 r3, 0x00a30800; -imm32 r4, 0x00a40800; -imm32 r5, 0x00a50800; -imm32 r6, 0x00a60800; -imm32 r7, 0x00a70800; -R5.H = R0.H << 0; -R6.H = R1.H << 1; -R7.H = R2.H << 2; -R0.H = R3.H << 3; -R1.H = R4.H << 4; -R2.H = R5.H << 5; -R3.H = R6.H << 6; -R4.H = R7.H << 7; -CHECKREG r0, 0x05180800; -CHECKREG r1, 0x0A400800; -CHECKREG r2, 0x14000800; -CHECKREG r3, 0x50800800; -CHECKREG r4, 0x44000800; -CHECKREG r5, 0x00A00800; -CHECKREG r6, 0x01420800; -CHECKREG r7, 0x02880800; - -imm32 r0, 0x0c010000; -imm32 r1, 0x0c010001; -imm32 r2, 0x0c020000; -imm32 r3, 0x0c030000; -imm32 r4, 0x0c040000; -imm32 r5, 0x0c050000; -imm32 r6, 0x0c060000; -imm32 r7, 0x0c070000; -R6.H = R0.H << 8; -R7.H = R1.H << 9; -R0.H = R2.H << 10; -R1.H = R3.H << 11; -R2.H = R4.H << 12; -R3.H = R5.H << 13; -R4.H = R6.H << 14; -R5.H = R7.H << 15; -CHECKREG r0, 0x08000000; -CHECKREG r1, 0x18000001; -CHECKREG r2, 0x40000000; -CHECKREG r3, 0xA0000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x01000000; -CHECKREG r7, 0x02000000; - - -imm32 r0, 0x00b10000; -imm32 r1, 0x00b10000; -imm32 r2, 0x00b2000f; -imm32 r3, 0x00b30000; -imm32 r4, 0x00b40000; -imm32 r5, 0x00b50000; -imm32 r6, 0x00b60000; -imm32 r7, 0x00b70000; -R7.L = R0.H << 0; -R0.L = R1.H << 1; -R1.L = R2.H << 2; -R2.L = R3.H << 3; -R3.L = R4.H << 4; -R4.L = R5.H << 5; -R5.L = R6.H << 6; -R6.L = R7.H << 7; -CHECKREG r0, 0x00B10162; -CHECKREG r1, 0x00B102C8; -CHECKREG r2, 0x00B20598; -CHECKREG r3, 0x00B30B40; -CHECKREG r4, 0x00B416A0; -CHECKREG r5, 0x00B52D80; -CHECKREG r6, 0x00B65B80; -CHECKREG r7, 0x00B700B1; - -imm32 r0, 0x0a010700; -imm32 r1, 0x0a010700; -imm32 r2, 0x0a020700; -imm32 r3, 0x0a030710; -imm32 r4, 0x0a040700; -imm32 r5, 0x0a050700; -imm32 r6, 0x0a060700; -imm32 r7, 0x0a070700; -R0.H = R0.H << 8; -R1.H = R1.H << 9; -R2.H = R2.H << 10; -R3.H = R3.H << 11; -R4.H = R4.H << 12; -R5.H = R5.H << 13; -R6.H = R6.H << 14; -R7.H = R7.H << 15; -CHECKREG r0, 0x01000700; -CHECKREG r1, 0x02000700; -CHECKREG r2, 0x08000700; -CHECKREG r3, 0x18000710; -CHECKREG r4, 0x40000700; -CHECKREG r5, 0xA0000700; -CHECKREG r6, 0x80000700; -CHECKREG r7, 0x80000700; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rn.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rn.s deleted file mode 100644 index a14a4c3..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rn.s +++ /dev/null @@ -1,424 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_lhalf_rn/c_dsp32shiftim_lhalf_rn.dsp -// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) -# mach: bfin - -.include "testutils.inc" - start - - - -// lshift : neg data, count (+)=left (half reg) -// d_lo = lshift (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -R0.L = -1; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = R0.L >> 1; -R1.L = R1.L >> 2; -R2.L = R2.L >> 3; -R3.L = R3.L >> 4; -R4.L = R4.L >> 5; -R5.L = R5.L >> 6; -R6.L = R6.L >> 7; -R7.L = R7.L >> 8; -CHECKREG r0, 0x00007FFF; -CHECKREG r1, 0x00002000; -CHECKREG r2, 0x00001000; -CHECKREG r3, 0x00000800; -CHECKREG r4, 0x00000400; -CHECKREG r5, 0x00000200; -CHECKREG r6, 0x00000100; -CHECKREG r7, 0x00000080; - -imm32 r0, 0x00008001; -R1.L = -1; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R0.L = R0.L >> 9; -R1.L = R1.L >> 10; -R2.L = R2.L >> 11; -R3.L = R3.L >> 12; -R4.L = R4.L >> 13; -R5.L = R5.L >> 14; -R6.L = R6.L >> 15; -R7.L = R7.L >> 10; -CHECKREG r0, 0x00000040; -CHECKREG r1, 0x0000003F; -CHECKREG r2, 0x00000010; -CHECKREG r3, 0x00000008; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000020; - - -imm32 r0, 0x30008001; -imm32 r1, 0x30008001; -R2.L = -15; -imm32 r3, 0x30008003; -imm32 r4, 0x30008004; -imm32 r5, 0x30008005; -imm32 r6, 0x30008006; -imm32 r7, 0x30008007; -R7.L = R0.L >> 1; -R6.L = R1.L >> 2; -R5.L = R2.L >> 3; -R4.L = R3.L >> 4; -R3.L = R4.L >> 5; -R2.L = R5.L >> 6; -R0.L = R7.L >> 8; -R1.L = R6.L >> 7; -CHECKREG r0, 0x30000040; -CHECKREG r1, 0x30000040; -CHECKREG r2, 0x0000007F; -CHECKREG r3, 0x30000040; -CHECKREG r4, 0x30000800; -CHECKREG r5, 0x30001FFE; -CHECKREG r6, 0x30002000; -CHECKREG r7, 0x30004000; - -imm32 r0, 0x00008001; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -R3.L = -16; -imm32 r4, 0x00008004; -imm32 r5, 0x00008005; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R6.L = R0.L >> 13; -R5.L = R1.L >> 13; -R4.L = R2.L >> 13; -R3.L = R3.L >> 13; -R2.L = R4.L >> 13; -R1.L = R5.L >> 13; -R0.L = R6.L >> 13; -R7.L = R7.L >> 13; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x30000007; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x00000004; -CHECKREG r6, 0x00000004; -CHECKREG r7, 0x00000004; - -// d_lo = lshift (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x00000000; -imm32 r1, 0x80010000; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -imm32 r4, 0x80040000; -imm32 r5, 0x80050000; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.L = R0.H >> 1; -R1.L = R1.H >> 1; -R2.L = R2.H >> 1; -R3.L = R3.H >> 1; -R4.L = R4.H >> 1; -R5.L = R5.H >> 1; -R6.L = R6.H >> 1; -R7.L = R7.H >> 1; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x80014000; -CHECKREG r2, 0x80024001; -CHECKREG r3, 0x80034001; -CHECKREG r4, 0x80044002; -CHECKREG r5, 0x80054002; -CHECKREG r6, 0x80064003; -CHECKREG r7, 0x80074003; - -imm32 r0, 0x80010000; -R1.L = -1; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -imm32 r4, 0x80040000; -imm32 r5, 0x80050000; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R1.L = R0.H >> 10; -R2.L = R1.H >> 11; -R3.L = R2.H >> 12; -R4.L = R3.H >> 13; -R5.L = R4.H >> 14; -R6.L = R5.H >> 15; -R0.L = R7.H >> 15; -R7.L = R6.H >> 15; -CHECKREG r0, 0x80010001; -CHECKREG r1, 0x80010020; -CHECKREG r2, 0x80020010; -CHECKREG r3, 0x80030008; -CHECKREG r4, 0x80040004; -CHECKREG r5, 0x80050002; -CHECKREG r6, 0x80060001; -CHECKREG r7, 0x80070001; - - -imm32 r0, 0xa0010000; -imm32 r1, 0xa0010000; -R2.L = -15; -imm32 r3, 0xa0030000; -imm32 r4, 0xa0040000; -imm32 r5, 0xa0050000; -imm32 r6, 0xa0060000; -imm32 r7, 0xa0070000; -R2.L = R0.H >> 2; -R3.L = R1.H >> 2; -R4.L = R2.H >> 2; -R5.L = R3.H >> 2; -R6.L = R4.H >> 2; -R7.L = R5.H >> 2; -R0.L = R6.H >> 2; -R1.L = R7.H >> 2; -CHECKREG r0, 0xA0012801; -CHECKREG r1, 0xA0012801; -CHECKREG r2, 0x80022800; -CHECKREG r3, 0xA0032800; -CHECKREG r4, 0xA0042000; -CHECKREG r5, 0xA0052800; -CHECKREG r6, 0xA0062801; -CHECKREG r7, 0xA0072801; - -imm32 r0, 0xb0010001; -imm32 r1, 0xb0010001; -imm32 r2, 0xb0020002; -R3.L = -16; -imm32 r4, 0xb0040004; -imm32 r5, 0xb0050005; -imm32 r6, 0xb0060006; -imm32 r7, 0xb0070007; -R3.L = R0.H >> 13; -R4.L = R1.H >> 13; -R5.L = R2.H >> 13; -R6.L = R3.H >> 13; -R7.L = R4.H >> 13; -R0.L = R5.H >> 13; -R1.L = R6.H >> 13; -R2.L = R7.H >> 13; -CHECKREG r0, 0xB0010005; -CHECKREG r1, 0xB0010005; -CHECKREG r2, 0xB0020005; -CHECKREG r3, 0xA0030005; -CHECKREG r4, 0xB0040005; -CHECKREG r5, 0xB0050005; -CHECKREG r6, 0xB0060005; -CHECKREG r7, 0xB0070005; - -// d_hi = lshift (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000001; -imm32 r1, 0x00000001; -imm32 r2, 0x00000002; -imm32 r3, 0x00000003; -imm32 r4, 0x00000004; -imm32 r5, 0x00000005; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = R0.L >> 14; -R1.H = R1.L >> 14; -R2.H = R2.L >> 14; -R3.H = R3.L >> 14; -R4.H = R4.L >> 14; -R5.H = R5.L >> 14; -R6.H = R6.L >> 14; -R7.H = R7.L >> 14; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000002; -CHECKREG r3, 0x00000003; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x00000005; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x00000007; - -imm32 r0, 0x00008001; -imm32 r1, 0x00008001; -imm32 r2, 0x00008002; -imm32 r3, 0x00008003; -imm32 r4, 0x00008004; -R5.L = -1; -imm32 r6, 0x00008006; -imm32 r7, 0x00008007; -R1.H = R0.L >> 5; -R0.H = R7.L >> 5; -R2.H = R1.L >> 5; -R3.H = R2.L >> 5; -R4.H = R3.L >> 5; -R5.H = R4.L >> 5; -R6.H = R5.L >> 5; -R7.H = R6.L >> 5; -CHECKREG r0, 0x04008001; -CHECKREG r1, 0x04008001; -CHECKREG r2, 0x04008002; -CHECKREG r3, 0x04008003; -CHECKREG r4, 0x04008004; -CHECKREG r5, 0x0400FFFF; -CHECKREG r6, 0x07FF8006; -CHECKREG r7, 0x04008007; - - -imm32 r0, 0x00009001; -imm32 r1, 0x00009001; -imm32 r2, 0x00009002; -imm32 r3, 0x00009003; -imm32 r4, 0x00009004; -imm32 r5, 0x00009005; -R6.L = -15; -imm32 r7, 0x00009007; -R3.H = R0.L >> 14; -R4.H = R1.L >> 14; -R5.H = R2.L >> 14; -R6.H = R3.L >> 14; -R7.H = R4.L >> 14; -R0.H = R5.L >> 14; -R1.H = R6.L >> 14; -R2.H = R7.L >> 14; -CHECKREG r0, 0x00029001; -CHECKREG r1, 0x00039001; -CHECKREG r2, 0x00029002; -CHECKREG r3, 0x00029003; -CHECKREG r4, 0x00029004; -CHECKREG r5, 0x00029005; -CHECKREG r6, 0x0002FFF1; -CHECKREG r7, 0x00029007; - -imm32 r0, 0x0000a001; -imm32 r1, 0x0000a001; -imm32 r2, 0x0000a002; -imm32 r3, 0x0000a003; -imm32 r4, 0x0000a004; -imm32 r5, 0x0000a005; -imm32 r6, 0x0000a006; -R7.L = -16; -R4.H = R0.L >> 15; -R5.H = R1.L >> 15; -R6.H = R2.L >> 15; -R7.H = R3.L >> 15; -R0.H = R4.L >> 15; -R1.H = R5.L >> 15; -R2.H = R6.L >> 15; -R3.H = R7.L >> 15; -CHECKREG r0, 0x0001A001; -CHECKREG r1, 0x0001A001; -CHECKREG r2, 0x0001A002; -CHECKREG r3, 0x0001A003; -CHECKREG r4, 0x0001A004; -CHECKREG r5, 0x0001A005; -CHECKREG r6, 0x0001A006; -CHECKREG r7, 0x0001FFF0; - -// d_lo = lshft (d_hi BY d_lo) -// RHx by RLx -imm32 r0, 0x80010000; -imm32 r1, 0x80010000; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -R4.L = -1; -imm32 r5, 0x80050000; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R0.H = R0.H >> 4; -R1.H = R1.H >> 4; -R2.H = R2.H >> 4; -R3.H = R3.H >> 4; -R4.H = R4.H >> 4; -R5.H = R5.H >> 4; -R6.H = R6.H >> 4; -R7.H = R7.H >> 4; -CHECKREG r0, 0x08000000; -CHECKREG r1, 0x08000000; -CHECKREG r2, 0x08000000; -CHECKREG r3, 0x08000000; -CHECKREG r4, 0x0000FFFF; -CHECKREG r5, 0x08000000; -CHECKREG r6, 0x08000000; -CHECKREG r7, 0x08000000; - -imm32 r0, 0x80010000; -imm32 r1, 0x80010000; -imm32 r2, 0x80020000; -imm32 r3, 0x80030000; -imm32 r4, 0x80040000; -R5.L = -1; -imm32 r6, 0x80060000; -imm32 r7, 0x80070000; -R1.H = R0.H >> 15; -R2.H = R1.H >> 15; -R3.H = R2.H >> 15; -R4.H = R3.H >> 15; -R5.H = R4.H >> 15; -R6.H = R5.H >> 15; -R0.H = R7.H >> 15; -R7.H = R6.H >> 15; -CHECKREG r0, 0x00010000; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x0000FFFF; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - - -imm32 r0, 0xd0010000; -imm32 r1, 0xd0010000; -imm32 r2, 0xd0020000; -imm32 r3, 0xd0030000; -imm32 r4, 0xd0040000; -imm32 r5, 0xd0050000; -R6.L = -15; -imm32 r7, 0xd0070000; -R3.H = R0.H >> 6; -R4.H = R1.H >> 6; -R5.H = R2.H >> 6; -R6.H = R3.H >> 6; -R7.H = R4.H >> 6; -R0.H = R5.H >> 6; -R1.H = R6.H >> 6; -R2.H = R7.H >> 6; -CHECKREG r0, 0x000D0000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x03400000; -CHECKREG r4, 0x03400000; -CHECKREG r5, 0x03400000; -CHECKREG r6, 0x000DFFF1; -CHECKREG r7, 0x000D0000; - -imm32 r0, 0xe0010000; -imm32 r1, 0xe0010000; -imm32 r2, 0xe0020000; -imm32 r3, 0xe0030000; -imm32 r4, 0xe0040000; -imm32 r5, 0xe0050000; -imm32 r6, 0xe0060000; -R7.L = -16; -R4.H = R0.H >> 7; -R5.H = R1.H >> 7; -R6.H = R2.H >> 7; -R7.H = R3.H >> 7; -R0.H = R4.H >> 7; -R1.H = R5.H >> 7; -R2.H = R6.H >> 7; -R3.H = R7.H >> 7; -CHECKREG r0, 0x00030000; -CHECKREG r1, 0x00030000; -CHECKREG r2, 0x00030000; -CHECKREG r3, 0x00030000; -CHECKREG r4, 0x01C00000; -CHECKREG r5, 0x01C00000; -CHECKREG r6, 0x01C00000; -CHECKREG r7, 0x01C0FFF0; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rp.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rp.s deleted file mode 100644 index a26a3eb..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rp.s +++ /dev/null @@ -1,421 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_lhalf_rp/c_dsp32shiftim_lhalf_rp.dsp -// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) -# mach: bfin - -.include "testutils.inc" - start - - - -// lshift : positive data, count (+)=left (half reg) -// d_lo = lshift (d_lo BY d_lo) -// RLx by RLx -imm32 r0, 0x00000000; -R0.L = -1; -imm32 r1, 0x90000001; -imm32 r2, 0x90000002; -imm32 r3, 0x90000003; -imm32 r4, 0x90000004; -imm32 r5, 0x90000005; -imm32 r6, 0x90000006; -imm32 r7, 0x90000007; -R0.L = R0.L << 0; -R1.L = R1.L >> 1; -R2.L = R2.L >> 2; -R3.L = R3.L >> 3; -R4.L = R4.L >> 4; -R5.L = R5.L >> 5; -R6.L = R6.L >> 6; -R7.L = R7.L >> 7; -CHECKREG r0, 0x0000FFFF; -CHECKREG r1, 0x90000000; -CHECKREG r2, 0x90000000; -CHECKREG r3, 0x90000000; -CHECKREG r4, 0x90000000; -CHECKREG r5, 0x90000000; -CHECKREG r6, 0x90000000; -CHECKREG r7, 0x90000000; - -imm32 r0, 0x00001001; -R1.L = -1; -imm32 r2, 0xa0002002; -imm32 r3, 0xa0003003; -imm32 r4, 0xa0004004; -imm32 r5, 0xa0005005; -imm32 r6, 0xa0006006; -imm32 r7, 0xa0007007; -R0.L = R0.L >> 1; -R1.L = R1.L >> 1; -R2.L = R2.L >> 1; -R3.L = R3.L >> 1; -R4.L = R4.L >> 1; -R5.L = R5.L >> 1; -R6.L = R6.L >> 1; -R7.L = R7.L >> 1; -CHECKREG r0, 0x00000800; -CHECKREG r1, 0x90007FFF; -CHECKREG r2, 0xA0001001; -CHECKREG r3, 0xA0001801; -CHECKREG r4, 0xA0002002; -CHECKREG r5, 0xA0002802; -CHECKREG r6, 0xA0003003; -CHECKREG r7, 0xA0003803; - - -imm32 r0, 0xb0001001; -imm32 r1, 0xb0001001; -R2.L = -15; -imm32 r3, 0xb0003003; -imm32 r4, 0xb0004004; -imm32 r5, 0xb0005005; -imm32 r6, 0xb0006006; -imm32 r7, 0xb0007007; -R0.L = R0.L >> 15; -R1.L = R1.L >> 15; -R2.L = LSHIFT R2.L BY R2.L; -R3.L = R3.L >> 15; -R4.L = R4.L >> 15; -R5.L = R5.L >> 15; -R6.L = R6.L >> 15; -R7.L = R7.L >> 15; -CHECKREG r0, 0xb0000000; -CHECKREG r1, 0xb0000000; -CHECKREG r2, 0xA0000001; -CHECKREG r3, 0xB0000000; -CHECKREG r4, 0xb0000000; -CHECKREG r5, 0xb0000000; -CHECKREG r6, 0xb0000000; -CHECKREG r7, 0xB0000000; - -imm32 r0, 0xc0001001; -imm32 r1, 0xc0001001; -imm32 r2, 0xc0002002; -R3.L = -16; -imm32 r4, 0xc0004004; -imm32 r5, 0xc0005005; -imm32 r6, 0xc0006006; -imm32 r7, 0xc0007007; -R0.L = R0.L >> 13; -R1.L = R1.L >> 13; -R2.L = R2.L >> 13; -R3.L = R3.L >> 13; -R4.L = R4.L >> 13; -R5.L = R5.L >> 13; -R6.L = R6.L >> 13; -R7.L = R7.L >> 13; -CHECKREG r0, 0xc0000000; -CHECKREG r1, 0xc0000000; -CHECKREG r2, 0xC0000001; -CHECKREG r3, 0xB0000007; -CHECKREG r4, 0xC0000002; -CHECKREG r5, 0xC0000002; -CHECKREG r6, 0xC0000003; -CHECKREG r7, 0xC0000003; - -// RHx by RLx -imm32 r0, 0x0000c000; -imm32 r1, 0x0001c000; -imm32 r2, 0x0002c000; -imm32 r3, 0x0003c000; -imm32 r4, 0x0004c000; -imm32 r5, 0x0005c000; -imm32 r6, 0x0006c000; -imm32 r7, 0x0007c000; -R0.L = R0.H << 0; -R1.L = R1.H << 0; -R2.L = R2.H << 0; -R3.L = R3.H << 0; -R4.L = R4.H << 0; -R5.L = R5.H << 0; -R6.L = R6.H << 0; -R7.L = R7.H << 0; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00010001; -CHECKREG r2, 0x00020002; -CHECKREG r3, 0x00030003; -CHECKREG r4, 0x00040004; -CHECKREG r5, 0x00050005; -CHECKREG r6, 0x00060006; -CHECKREG r7, 0x00070007; - -imm32 r0, 0x10010000; -R1.L = -1; -imm32 r2, 0x20020000; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -imm32 r6, 0x60060000; -imm32 r7, 0x70070000; -R0.L = R0.H >> 1; -R1.L = R1.H >> 1; -R2.L = R2.H >> 1; -R3.L = R3.H >> 1; -R4.L = R4.H >> 1; -R5.L = R5.H >> 1; -R6.L = R6.H >> 1; -R7.L = R7.H >> 1; -CHECKREG r0, 0x10010800; -CHECKREG r1, 0x00010000; -CHECKREG r2, 0x20021001; -CHECKREG r3, 0x30031801; -CHECKREG r4, 0x40042002; -CHECKREG r5, 0x50052802; -CHECKREG r6, 0x60063003; -CHECKREG r7, 0x70073803; - - -imm32 r0, 0x1001e000; -imm32 r1, 0x1001e000; -R2.L = -15; -imm32 r3, 0x3003e000; -imm32 r4, 0x4004e000; -imm32 r5, 0x5005e000; -imm32 r6, 0x6006e000; -imm32 r7, 0x7007e000; -R0.L = R0.H >> 15; -R1.L = R1.H >> 15; -R2.L = R2.H >> 15; -R3.L = R3.H >> 15; -R4.L = R4.H >> 15; -R5.L = R5.H >> 15; -R6.L = R6.H >> 15; -R7.L = R7.H >> 15; -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -CHECKREG r2, 0x20020000; -CHECKREG r3, 0x30030000; -CHECKREG r4, 0x40040000; -CHECKREG r5, 0x50050000; -CHECKREG r6, 0x60060000; -CHECKREG r7, 0x70070000; - -imm32 r0, 0x1001f001; -imm32 r1, 0x1001f001; -imm32 r2, 0x2002f002; -R3.L = -16; -imm32 r4, 0x4004f004; -imm32 r5, 0x5005f005; -imm32 r6, 0x6006f006; -imm32 r7, 0x7007f007; -R0.L = R0.H >> 13; -R1.L = R1.H >> 13; -R2.L = R2.H >> 13; -R3.L = R3.H >> 13; -R4.L = R4.H >> 13; -R5.L = R5.H >> 13; -R6.L = R6.H >> 13; -R7.L = R7.H >> 13; -CHECKREG r0, 0x10010000; -CHECKREG r1, 0x10010000; -CHECKREG r2, 0x20020001; -CHECKREG r3, 0x30030001; -CHECKREG r4, 0x40040002; -CHECKREG r5, 0x50050002; -CHECKREG r6, 0x60060003; -CHECKREG r7, 0x70070003; - -// RLx by RLx -imm32 r0, 0x00001001; -imm32 r1, 0x00001001; -imm32 r2, 0x00001002; -imm32 r3, 0x00001003; -imm32 r4, 0x00001000; -imm32 r5, 0x00001005; -imm32 r6, 0x00001006; -imm32 r7, 0x00001007; -R0.H = R0.L >> 14; -R1.H = R1.L >> 14; -R2.H = R2.L >> 14; -R3.H = R3.L >> 14; -R4.H = R4.L >> 14; -R5.H = R5.L >> 14; -R6.H = R6.L >> 14; -R7.H = R7.L >> 14; -CHECKREG r0, 0x00001001; -CHECKREG r1, 0x00001001; -CHECKREG r2, 0x00001002; -CHECKREG r3, 0x00001003; -CHECKREG r4, 0x00001000; -CHECKREG r5, 0x00001005; -CHECKREG r6, 0x00001006; -CHECKREG r7, 0x00001007; - -imm32 r0, 0x00002001; -imm32 r1, 0x00002001; -imm32 r2, 0x00002002; -imm32 r3, 0x00002003; -imm32 r4, 0x00002004; -R5.L = -1; -imm32 r6, 0x00000006; -imm32 r7, 0x00000007; -R0.H = R0.L >> 5; -R1.H = R1.L >> 5; -R2.H = R2.L >> 5; -R3.H = R3.L >> 5; -R4.H = R4.L >> 5; -R5.H = R5.L >> 5; -R6.H = R6.L >> 5; -R7.H = R7.L >> 5; -CHECKREG r0, 0x01002001; -CHECKREG r1, 0x01002001; -CHECKREG r2, 0x01002002; -CHECKREG r3, 0x01002003; -CHECKREG r4, 0x01002004; -CHECKREG r5, 0x07FFFFFF; -CHECKREG r6, 0x00000006; -CHECKREG r7, 0x00000007; - - -imm32 r0, 0x30001001; -imm32 r1, 0x30001001; -imm32 r1, 0x30002002; -imm32 r3, 0x30003003; -imm32 r4, 0x30004004; -imm32 r5, 0x30005005; -R6.L = -15; -imm32 r7, 0x00007007; -R0.H = R0.L >> 15; -R1.H = R1.L >> 15; -R2.H = R2.L >> 15; -R3.H = R3.L >> 15; -R4.H = R4.L >> 15; -R5.H = R5.L >> 15; -R6.H = R6.L >> 15; -R7.H = R7.L >> 15; -CHECKREG r0, 0x00001001; -CHECKREG r1, 0x00002002; -CHECKREG r2, 0x00002002; -CHECKREG r3, 0x00003003; -CHECKREG r4, 0x00004004; -CHECKREG r5, 0x00005005; -CHECKREG r6, 0x0001FFF1; -CHECKREG r7, 0x00007007; - -imm32 r0, 0x40001001; -imm32 r1, 0x40002001; -imm32 r2, 0x40002002; -imm32 r3, 0x40003003; -imm32 r4, 0x40004004; -imm32 r5, 0x40005005; -imm32 r6, 0x40006006; -R7.L = -16; -R0.H = R0.L >> 7; -R1.H = R1.L >> 7; -R2.H = R2.L >> 7; -R3.H = R3.L >> 7; -R4.H = R4.L >> 7; -R5.H = R5.L >> 7; -R6.H = R6.L >> 7; -R7.H = R7.L >> 7; -CHECKREG r0, 0x00201001; -CHECKREG r1, 0x00402001; -CHECKREG r2, 0x00402002; -CHECKREG r3, 0x00603003; -CHECKREG r4, 0x00804004; -CHECKREG r5, 0x00A05005; -CHECKREG r6, 0x00C06006; -CHECKREG r7, 0x01FFFFF0; - -// RHx by RLx -imm32 r0, 0x50010000; -imm32 r1, 0x50010000; -imm32 r2, 0x50020000; -imm32 r3, 0x50030000; -R4.L = -1; -imm32 r5, 0x50050000; -imm32 r6, 0x50060000; -imm32 r7, 0x50070000; -R0.H = R0.H >> 1; -R1.H = R1.H >> 1; -R2.H = R2.H >> 1; -R3.H = R3.H >> 1; -R4.H = R4.H >> 1; -R5.H = R5.H >> 1; -R6.H = R6.H >> 1; -R7.H = R7.H >> 1; -CHECKREG r0, 0x28000000; -CHECKREG r1, 0x28000000; -CHECKREG r2, 0x28010000; -CHECKREG r3, 0x28010000; -CHECKREG r4, 0x0040FFFF; -CHECKREG r5, 0x28020000; -CHECKREG r6, 0x28030000; -CHECKREG r7, 0x28030000; - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -imm32 r2, 0x20020000; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -R5.L = -1; -imm32 r6, 0x60060000; -imm32 r7, 0x70070000; -R0.H = R0.H >> 5; -R1.H = R1.H >> 5; -R2.H = R2.H >> 5; -R3.H = R3.H >> 5; -R4.H = R4.H >> 5; -R5.H = R5.H >> 5; -R6.H = R6.H >> 5; -R7.H = R7.H >> 5; -CHECKREG r0, 0x00800000; -CHECKREG r1, 0x00800000; -CHECKREG r2, 0x01000000; -CHECKREG r3, 0x01800000; -CHECKREG r4, 0x02000000; -CHECKREG r5, 0x0140FFFF; -CHECKREG r6, 0x03000000; -CHECKREG r7, 0x03800000; - - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -imm32 r2, 0x20020000; -imm32 r3, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -R6.L = -15; -imm32 r7, 0x70070000; -R0.L = R0.H >> 6; -R1.L = R1.H >> 6; -R2.L = R2.H >> 6; -R3.L = R3.H >> 6; -R4.L = R4.H >> 6; -R5.L = R5.H >> 6; -R6.L = R6.H >> 6; -R7.L = R7.H >> 6; -CHECKREG r0, 0x10010040; -CHECKREG r1, 0x10010040; -CHECKREG r2, 0x20020080; -CHECKREG r3, 0x300300C0; -CHECKREG r4, 0x40040100; -CHECKREG r5, 0x50050140; -CHECKREG r6, 0x0300000C; -CHECKREG r7, 0x700701C0; - -imm32 r0, 0x10010000; -imm32 r1, 0x10010000; -imm32 r2, 0x20020000; -imm32 r2, 0x30030000; -imm32 r4, 0x40040000; -imm32 r5, 0x50050000; -imm32 r6, 0x60060000; -R7.L = -16; -R0.H = R0.H >> 15; -R1.H = R1.H >> 15; -R2.H = R2.H >> 15; -R3.H = R3.H >> 15; -R4.H = R4.H >> 15; -R5.H = R5.H >> 15; -R6.H = R6.H >> 15; -R7.H = R7.H >> 15; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x000000C0; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x0000FFF0; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhh.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhh.s deleted file mode 100644 index e129dca..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhh.s +++ /dev/null @@ -1,65 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_lhh/c_dsp32shiftim_lhh.dsp -# mach: bfin - -.include "testutils.inc" - start - - -// Spec Reference: dsp32shiftimm lshift: lshift / lshift - - - -imm32 r0, 0x01230abc; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R0 = R0 << 0 (V); -R1 = R1 << 3 (V); -R2 = R2 << 5 (V); -R3 = R3 << 8 (V); -R4 = R4 << 9 (V); -R5 = R5 << 15 (V); -R6 = R6 << 7 (V); -R7 = R7 << 13 (V); -CHECKREG r0, 0x01230ABC; -CHECKREG r1, 0x91A0B3C0; -CHECKREG r2, 0x68A0F120; -CHECKREG r3, 0x56009A00; -CHECKREG r4, 0xCE005600; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0xC480E680; -CHECKREG r7, 0x4000C000; - -imm32 r0, 0x01230000; -imm32 r1, 0x12345678; -imm32 r2, 0x23456789; -imm32 r3, 0x3456789a; -imm32 r4, 0x456789ab; -imm32 r5, 0x56789abc; -imm32 r6, 0x6789abcd; -imm32 r7, 0x789abcde; -R7 = R0 >> 11 (V); -R0 = R1 >> 8 (V); -R1 = R2 >> 14 (V); -R2 = R3 >> 15 (V); -R3 = R4 >> 10 (V); -R4 = R5 >> 2 (V); -R5 = R6 >> 9 (V); -R6 = R7 >> 6 (V); -CHECKREG r0, 0x00120056; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00110022; -CHECKREG r4, 0x159E26AF; -CHECKREG r5, 0x00330055; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - - - - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lmix.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lmix.s deleted file mode 100644 index 82845ff..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_lmix.s +++ /dev/null @@ -1,138 +0,0 @@ -//Original:/testcases/core/c_dsp32shiftim_lmix/c_dsp32shiftim_lmix.dsp -# mach: bfin - -.include "testutils.inc" - start - - -// Spec Reference: dsp32shiftimm lshift: mix - - - - -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - - -// Lshift (Logical ) -// Lshift : positive data, count (+)=left (half reg) -imm32 r0, 0x00010001; -imm32 r1, 1; -imm32 r2, 0x00020002; -imm32 r3, 2; -R4.H = R0.H << 1; -R4.L = R0.L << 1; /* r4 = 0x00020002 */ -R5.H = R2.H << 2; -R5.L = R2.L << 2; /* r5 = 0x00080008 */ -R6 = R0 << 1 (V); /* r6 = 0x00020002 */ -R7 = R2 << 2 (V); /* r7 = 0x00080008 */ -CHECKREG r4, 0x00020002; -CHECKREG r5, 0x00080008; -CHECKREG r6, 0x00020002; -CHECKREG r7, 0x00080008; - -// Lshift : (full reg) -imm32 r1, 3; -imm32 r3, 4; -R6 = R0 << 3; /* r6 = 0x00080010 */ -R7 = R2 << 4; -CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ -CHECKREG r7, 0x00200020; - -A0 = 0; -A0.L = R0.L; -A0.H = R0.H; -A0 = A0 << 3; /* a0 = 0x00080008 */ -R5 = A0.w; /* r5 = 0x00080008 */ -CHECKREG r5, 0x00080008; - -imm32 r4, 0x30000003; -imm32 r1, 1; -R5 = R4 << 1; /* r5 = 0x60000006 */ -imm32 r1, 2; -R6 = R4 << 2; /* r6 = 0xc000000c like LSHIFT */ -CHECKREG r5, 0x60000006; -CHECKREG r6, 0xc000000c; - - -// lshift : count (-)=right (half reg) -imm32 r0, 0x10001000; -imm32 r1, -1; -imm32 r2, 0x10001000; -imm32 r3, -2; -R4.H = R0.H >> 1; -R4.L = R0.L >> 1; /* r4 = 0x08000800 */ -R5.H = R2.H >> 2; -R5.L = R2.L >> 2; /* r4 = 0x04000400 */ -R6 = R0 >> 1 (V); /* r4 = 0x08000800 */ -R7 = R2 >> 2 (V); /* r4 = 0x04000400 */ -CHECKREG r4, 0x08000800; -CHECKREG r5, 0x04000400; -CHECKREG r6, 0x08000800; -CHECKREG r7, 0x04000400; - -// lshift : (full reg) -imm32 r1, -3; -imm32 r3, -4; -R6 = R0 >> 3; /* r6 = 0x02000200 */ -R7 = R2 >> 4; /* r7 = 0x01000100 */ -CHECKREG r6, 0x02000200; -CHECKREG r7, 0x01000100; - -// NEGATIVE -// lshift : NEGATIVE data, count (+)=left (half reg) -imm32 r0, 0xc00f800f; -imm32 r1, 1; -imm32 r2, 0xe00fe00f; -imm32 r3, 2; -R4.H = R0.H << 1; -R4.L = R0.L << 1; /* r4 = 0x801e001e */ -R5.H = R2.H << 2; -R5.L = R2.L << 2; /* r4 = 0x803c803c */ -CHECKREG r4, 0x801e001e; -CHECKREG r5, 0x803c803c; - -imm32 r0, 0xc80fe00f; -imm32 r2, 0xe40fe00f; -imm32 r1, 4; -imm32 r3, 5; -R6 = R0 << 4; /* r6 = 0x80fe00f0 */ -R7 = R2 << 5; /* r7 = 0x81fc01e0 */ -CHECKREG r6, 0x80fe00f0; -CHECKREG r7, 0x81fc01e0; - -imm32 r0, 0xf80fe00f; -imm32 r2, 0xfc0fe00f; -R6 = R0 << 4; /* r6 = 0x80fe00f0 */ -R7 = R2 << 5; /* r7 = 0x81fc01e0 */ -CHECKREG r6, 0x80fe00f0; -CHECKREG r7, 0x81fc01e0; - - - -// lshift : NEGATIVE data, count (-)=right (half reg) Working ok -imm32 r0, 0x80f080f0; -imm32 r1, -1; -imm32 r2, 0x80f080f0; -imm32 r3, -2; -R4.H = R0.H >> 1; -R4.L = R0.L >> 1; /* r4 = 0x40784078 */ -R5.H = R2.H >> 2; -R5.L = R2.L >> 2; /* r4 = 0x203c203c */ -CHECKREG r4, 0x40784078; -CHECKREG r5, 0x203c203c; -R6 = R0 >> 1 (V); /* r6 = 0x40784078 */ -R7 = R2 >> 2 (V); /* r7 = 0x203c203c */ -CHECKREG r6, 0x40784078; -CHECKREG r7, 0x203c203c; - -imm32 r1, -3; -imm32 r3, -4; -R6 = R0 >> 3; /* r6 = 0x101e101e */ -R7 = R2 >> 4; /* r7 = 0x080f080f */ -CHECKREG r6, 0x101e101e; -CHECKREG r7, 0x080f080f; - -pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s deleted file mode 100644 index 0b47eda..0000000 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s +++ /dev/null @@ -1,62 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_rot/c_dsp32shiftim_rot.dsp -// Spec Reference: dsp32shiftimm rot: -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - - imm32 r0, 0xa1230001; - imm32 r1, 0x1b345678; - imm32 r2, 0x23c56789; - imm32 r3, 0x34d6789a; - imm32 r4, 0x85a789ab; - imm32 r5, 0x967c9abc; - imm32 r6, 0xa789abcd; - imm32 r7, 0xb8912cde; - R0 = ROT R0 BY 1; - R1 = ROT R1 BY 5; - R2 = ROT R2 BY 9; - R3 = ROT R3 BY 8; - R4 = ROT R4 BY 24; - R5 = ROT R5 BY 31; - R6 = ROT R6 BY 14; - R7 = ROT R7 BY 25; - CHECKREG r0, 0x42460002; - CHECKREG r1, 0x668ACF11; - CHECKREG r2, 0x8ACF1323; - CHECKREG r3, 0xD6789A9A; - CHECKREG r4, 0xAB42D3C4; - CHECKREG r5, 0x659F26AF; - CHECKREG r6, 0x6AF354F1; - CHECKREG r7, 0xBCB8912C; - - imm32 r0, 0xa1230001; - imm32 r1, 0x1b345678; - imm32 r2, 0x23c56789; - imm32 r3, 0x34d6789a; - imm32 r4, 0x85a789ab; - imm32 r5, 0x967c9abc; - imm32 r6, 0xa789abcd; - imm32 r7, 0xb8912cde; - R6 = ROT R0 BY -3; - R7 = ROT R1 BY -9; - R0 = ROT R2 BY -8; - R1 = ROT R3 BY -7; - R2 = ROT R4 BY -15; - R3 = ROT R5 BY -24; - R4 = ROT R6 BY -31; - R5 = ROT R7 BY -22; - CHECKREG r0, 0x1223C567; - CHECKREG r1, 0x6A69ACF1; - CHECKREG r2, 0x26AD0B4F; - CHECKREG r3, 0xF9357896; - CHECKREG r4, 0xD0918000; - CHECKREG r5, 0x6CD15DE0; - CHECKREG r6, 0x74246000; - CHECKREG r7, 0x780D9A2B; - - pass diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_dr_i.s b/sim/testsuite/sim/bfin/c_dspldst_ld_dr_i.s deleted file mode 100644 index 02743cc..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_ld_dr_i.s +++ /dev/null @@ -1,168 +0,0 @@ -//Original:/testcases/core/c_dspldst_ld_dr_i/c_dspldst_ld_dr_i.dsp -# mach: bfin - -.include "testutils.inc" - start - - -// Spec Reference: c_dspldst ld_dr_i - - -// set all regs - - INIT_R_REGS 0; - -// initial values - loadsym I0, DATA1 - loadsym I1, DATA2 - loadsym I2, DATA3 - loadsym I3, DATA4 - - R0 = [ I0 ]; - R1 = [ I1 ]; - R2 = [ I2 ]; - R3 = [ I3 ]; - R4 = [ I0 ]; - R5 = [ I1 ]; - R6 = [ I2 ]; - R7 = [ I3 ]; - CHECKREG r0, 0x00010203; - CHECKREG r1, 0x20212223; - CHECKREG r2, 0x40414243; - CHECKREG r3, 0x60616263; - CHECKREG r4, 0x00010203; - CHECKREG r5, 0x20212223; - CHECKREG r6, 0x40414243; - CHECKREG r7, 0x60616263; - R1 = [ I0 ]; - R2 = [ I1 ]; - R3 = [ I2 ]; - R4 = [ I3 ]; - R5 = [ I0 ]; - R6 = [ I1 ]; - R7 = [ I2 ]; - R0 = [ I3 ]; - CHECKREG r0, 0x60616263; - CHECKREG r1, 0x00010203; - CHECKREG r2, 0x20212223; - CHECKREG r3, 0x40414243; - CHECKREG r4, 0x60616263; - CHECKREG r5, 0x00010203; - CHECKREG r6, 0x20212223; - CHECKREG r7, 0x40414243; - R2 = [ I0 ]; - R3 = [ I1 ]; - R4 = [ I2 ]; - R5 = [ I3 ]; - R6 = [ I0 ]; - R7 = [ I1 ]; - R0 = [ I2 ]; - R1 = [ I3 ]; - CHECKREG r0, 0x40414243; - CHECKREG r1, 0x60616263; - CHECKREG r2, 0x00010203; - CHECKREG r3, 0x20212223; - CHECKREG r4, 0x40414243; - CHECKREG r5, 0x60616263; - CHECKREG r6, 0x00010203; - CHECKREG r7, 0x20212223; - - R3 = [ I0 ]; - R4 = [ I1 ]; - R5 = [ I2 ]; - R6 = [ I3 ]; - R7 = [ I0 ]; - R0 = [ I1 ]; - R1 = [ I2 ]; - R2 = [ I3 ]; - CHECKREG r0, 0x20212223; - CHECKREG r1, 0x40414243; - CHECKREG r2, 0x60616263; - CHECKREG r3, 0x00010203; - CHECKREG r4, 0x20212223; - CHECKREG r5, 0x40414243; - CHECKREG r6, 0x60616263; - CHECKREG r7, 0x00010203; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - -DATA2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - -DATA3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - -DATA4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - -DATA6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ipp.s b/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ipp.s deleted file mode 100644 index d94dfc2..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ipp.s +++ /dev/null @@ -1,348 +0,0 @@ -//Original:/testcases/core/c_dspldst_ld_dr_ipp/c_dspldst_ld_dr_ipp.dsp -// Spec Reference: c_dspldst ld_dr_i++/-- -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - - R0 = [ I0 ++ ]; - R1 = [ I1 ++ ]; - R2 = [ I2 ++ ]; - R3 = [ I3 ++ ]; - R4 = [ I0 ++ ]; - R5 = [ I1 ++ ]; - R6 = [ I2 ++ ]; - R7 = [ I3 ++ ]; - CHECKREG r0, 0x00010203; - CHECKREG r1, 0x20212223; - CHECKREG r2, 0x40414243; - CHECKREG r3, 0x60616263; - CHECKREG r4, 0x04050607; - CHECKREG r5, 0x24252627; - CHECKREG r6, 0x44454647; - CHECKREG r7, 0x64656667; - R1 = [ I0 ++ ]; - R2 = [ I1 ++ ]; - R3 = [ I2 ++ ]; - R4 = [ I3 ++ ]; - R5 = [ I0 ++ ]; - R6 = [ I1 ++ ]; - R7 = [ I2 ++ ]; - R0 = [ I3 ++ ]; - CHECKREG r0, 0x6C6D6E6F; - CHECKREG r1, 0x08090A0B; - CHECKREG r2, 0x28292A2B; - CHECKREG r3, 0x48494A4B; - CHECKREG r4, 0x68696A6B; - CHECKREG r5, 0x0C0D0E0F; - CHECKREG r6, 0x2C2D2E2F; - CHECKREG r7, 0x4C4D4E4F; - R2 = [ I0 ++ ]; - R3 = [ I1 ++ ]; - R4 = [ I2 ++ ]; - R5 = [ I3 ++ ]; - R6 = [ I0 ++ ]; - R7 = [ I1 ++ ]; - R0 = [ I2 ++ ]; - R1 = [ I3 ++ ]; - CHECKREG r0, 0x54555657; - CHECKREG r1, 0x74757677; - CHECKREG r2, 0x10111213; - CHECKREG r3, 0x30313233; - CHECKREG r4, 0x50515253; - CHECKREG r5, 0x70717273; - CHECKREG r6, 0x14151617; - CHECKREG r7, 0x34353637; - - R3 = [ I0 ++ ]; - R4 = [ I1 ++ ]; - R5 = [ I2 ++ ]; - R6 = [ I3 ++ ]; - R7 = [ I0 ++ ]; - R0 = [ I1 ++ ]; - R1 = [ I2 ++ ]; - R2 = [ I3 ++ ]; - CHECKREG r0, 0x3C3D3E3F; - CHECKREG r1, 0xC5C6C7C8; - CHECKREG r2, 0x7C7D7E7F; - CHECKREG r3, 0x18191A1B; - CHECKREG r4, 0x38393A3B; - CHECKREG r5, 0x58595A5B; - CHECKREG r6, 0x78797A7B; - CHECKREG r7, 0x1C1D1E1F; - -// reverse to minus mninus i-- - R0 = [ I0 -- ]; - R1 = [ I1 -- ]; - R2 = [ I2 -- ]; - R3 = [ I3 -- ]; - R4 = [ I0 -- ]; - R5 = [ I1 -- ]; - R6 = [ I2 -- ]; - R7 = [ I3 -- ]; - CHECKREG r0, 0x11223344; - CHECKREG r1, 0x91929394; - CHECKREG r2, 0xC9CACBCD; - CHECKREG r3, 0xEBECEDEE; - CHECKREG r4, 0x1C1D1E1F; - CHECKREG r5, 0x3C3D3E3F; - CHECKREG r6, 0xC5C6C7C8; - CHECKREG r7, 0x7C7D7E7F; - R1 = [ I0 -- ]; - R2 = [ I1 -- ]; - R3 = [ I2 -- ]; - R4 = [ I3 -- ]; - R5 = [ I0 -- ]; - R6 = [ I1 -- ]; - R7 = [ I2 -- ]; - R0 = [ I3 -- ]; - CHECKREG r0, 0x74757677; - CHECKREG r1, 0x18191A1B; - CHECKREG r2, 0x38393A3B; - CHECKREG r3, 0x58595A5B; - CHECKREG r4, 0x78797A7B; - CHECKREG r5, 0x14151617; - CHECKREG r6, 0x34353637; - CHECKREG r7, 0x54555657; - R2 = [ I0 -- ]; - R3 = [ I1 -- ]; - R4 = [ I2 -- ]; - R5 = [ I3 -- ]; - R6 = [ I0 -- ]; - R7 = [ I1 -- ]; - R0 = [ I2 -- ]; - R1 = [ I3 -- ]; - CHECKREG r0, 0x4C4D4E4F; - CHECKREG r1, 0x6C6D6E6F; - CHECKREG r2, 0x10111213; - CHECKREG r3, 0x30313233; - CHECKREG r4, 0x50515253; - CHECKREG r5, 0x70717273; - CHECKREG r6, 0x0C0D0E0F; - CHECKREG r7, 0x2C2D2E2F; - - R3 = [ I0 -- ]; - R4 = [ I1 -- ]; - R5 = [ I2 -- ]; - R6 = [ I3 -- ]; - R7 = [ I0 -- ]; - R0 = [ I1 -- ]; - R1 = [ I2 -- ]; - R2 = [ I3 -- ]; - CHECKREG r0, 0x24252627; - CHECKREG r1, 0x44454647; - CHECKREG r2, 0x64656667; - CHECKREG r3, 0x08090A0B; - CHECKREG r4, 0x28292A2B; - CHECKREG r5, 0x48494A4B; - CHECKREG r6, 0x68696A6B; - CHECKREG r7, 0x04050607; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xBC0DBE26 - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ippm.s b/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ippm.s deleted file mode 100644 index abdc823..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ippm.s +++ /dev/null @@ -1,328 +0,0 @@ -//Original:/testcases/core/c_dspldst_ld_dr_ippm/c_dspldst_ld_dr_ippm.dsp -// Spec Reference: c_dspldst ld_dr_i++m -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - M0 = 0 (X); - M1 = 0x4 (X); - M2 = 0x0 (X); - M3 = 0x4 (X); - - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - - R0 = [ I0 ++ M0 ]; - R1 = [ I1 ++ M1 ]; - R2 = [ I2 ++ M2 ]; - R3 = [ I3 ++ M3 ]; - R4 = [ I0 ++ M1 ]; - R5 = [ I1 ++ M2 ]; - R6 = [ I2 ++ M3 ]; - R7 = [ I3 ++ M0 ]; - CHECKREG r0, 0x00010203; - CHECKREG r1, 0x20212223; - CHECKREG r2, 0x40414243; - CHECKREG r3, 0x60616263; - CHECKREG r4, 0x00010203; - CHECKREG r5, 0x24252627; - CHECKREG r6, 0x40414243; - CHECKREG r7, 0x64656667; - R1 = [ I0 ++ M2 ]; - R2 = [ I1 ++ M3 ]; - R3 = [ I2 ++ M0 ]; - R4 = [ I3 ++ M1 ]; - R5 = [ I0 ++ M3 ]; - R6 = [ I1 ++ M0 ]; - R7 = [ I2 ++ M1 ]; - R0 = [ I3 ++ M2 ]; - CHECKREG r0, 0x68696A6B; - CHECKREG r1, 0x04050607; - CHECKREG r2, 0x24252627; - CHECKREG r3, 0x44454647; - CHECKREG r4, 0x64656667; - CHECKREG r5, 0x04050607; - CHECKREG r6, 0x28292A2B; - CHECKREG r7, 0x44454647; - - M0 = 4 (X); - M1 = 0x0 (X); - M2 = 0x4 (X); - M3 = 0x0 (X); - R2 = [ I0 ++ M0 ]; - R3 = [ I1 ++ M1 ]; - R4 = [ I2 ++ M2 ]; - R5 = [ I3 ++ M3 ]; - R6 = [ I0 ++ M1 ]; - R7 = [ I1 ++ M2 ]; - R0 = [ I2 ++ M3 ]; - R1 = [ I3 ++ M0 ]; - CHECKREG r0, 0x4C4D4E4F; - CHECKREG r1, 0x68696A6B; - CHECKREG r2, 0x08090A0B; - CHECKREG r3, 0x28292A2B; - CHECKREG r4, 0x48494A4B; - CHECKREG r5, 0x68696A6B; - CHECKREG r6, 0x0C0D0E0F; - CHECKREG r7, 0x28292A2B; - - R3 = [ I0 ++ M2 ]; - R4 = [ I1 ++ M3 ]; - R5 = [ I2 ++ M0 ]; - R6 = [ I3 ++ M1 ]; - R7 = [ I0 ++ M3 ]; - R0 = [ I1 ++ M0 ]; - R1 = [ I2 ++ M1 ]; - R2 = [ I3 ++ M2 ]; - CHECKREG r0, 0x2C2D2E2F; - CHECKREG r1, 0x50515253; - CHECKREG r2, 0x6C6D6E6F; - CHECKREG r3, 0x0C0D0E0F; - CHECKREG r4, 0x2C2D2E2F; - CHECKREG r5, 0x4C4D4E4F; - CHECKREG r6, 0x6C6D6E6F; - CHECKREG r7, 0x10111213; - - R5 = [ I0 ++ M2 ]; - R6 = [ I1 ++ M3 ]; - R7 = [ I2 ++ M0 ]; - R0 = [ I3 ++ M1 ]; - R1 = [ I0 ++ M3 ]; - R2 = [ I1 ++ M0 ]; - R3 = [ I2 ++ M1 ]; - R4 = [ I3 ++ M2 ]; - CHECKREG r0, 0x70717273; - CHECKREG r1, 0x14151617; - CHECKREG r2, 0x30313233; - CHECKREG r3, 0x54555657; - CHECKREG r4, 0x70717273; - CHECKREG r5, 0x10111213; - CHECKREG r6, 0x30313233; - CHECKREG r7, 0x50515253; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_i.s b/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_i.s deleted file mode 100644 index 3ada175..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_i.s +++ /dev/null @@ -1,168 +0,0 @@ -//Original:/testcases/core/c_dspldst_ld_drhi_i/c_dspldst_ld_drhi_i.dsp -// Spec Reference: c_dspldst ld_drhi_i -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - - INIT_R_REGS 0; - - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - -// Load upper half of Dregs - R0.H = W [ I0 ]; - R1.H = W [ I1 ]; - R2.H = W [ I2 ]; - R3.H = W [ I3 ]; - R4.H = W [ I0 ]; - R5.H = W [ I1 ]; - R6.H = W [ I2 ]; - R7.H = W [ I3 ]; - CHECKREG r0, 0x02030000; - CHECKREG r1, 0x22230000; - CHECKREG r2, 0x42430000; - CHECKREG r3, 0x62630000; - CHECKREG r4, 0x02030000; - CHECKREG r5, 0x22230000; - CHECKREG r6, 0x42430000; - CHECKREG r7, 0x62630000; - - R1.H = W [ I0 ]; - R2.H = W [ I1 ]; - R3.H = W [ I2 ]; - R4.H = W [ I3 ]; - R5.H = W [ I0 ]; - R6.H = W [ I1 ]; - R7.H = W [ I2 ]; - R0.H = W [ I3 ]; - CHECKREG r0, 0x62630000; - CHECKREG r1, 0x02030000; - CHECKREG r2, 0x22230000; - CHECKREG r3, 0x42430000; - CHECKREG r4, 0x62630000; - CHECKREG r5, 0x02030000; - CHECKREG r6, 0x22230000; - CHECKREG r7, 0x42430000; - - R2.H = W [ I0 ]; - R3.H = W [ I1 ]; - R4.H = W [ I2 ]; - R5.H = W [ I3 ]; - R6.H = W [ I0 ]; - R7.H = W [ I1 ]; - R0.H = W [ I2 ]; - R1.H = W [ I3 ]; - CHECKREG r0, 0x42430000; - CHECKREG r1, 0x62630000; - CHECKREG r2, 0x02030000; - CHECKREG r3, 0x22230000; - CHECKREG r4, 0x42430000; - CHECKREG r5, 0x62630000; - CHECKREG r6, 0x02030000; - CHECKREG r7, 0x22230000; - - R3.H = W [ I0 ]; - R4.H = W [ I1 ]; - R5.H = W [ I2 ]; - R6.H = W [ I3 ]; - R7.H = W [ I0 ]; - R0.H = W [ I1 ]; - R1.H = W [ I2 ]; - R2.H = W [ I3 ]; - - CHECKREG r0, 0x22230000; - CHECKREG r1, 0x42430000; - CHECKREG r2, 0x62630000; - CHECKREG r3, 0x02030000; - CHECKREG r4, 0x22230000; - CHECKREG r5, 0x42430000; - CHECKREG r6, 0x62630000; - CHECKREG r7, 0x02030000; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data - -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_ipp.s b/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_ipp.s deleted file mode 100644 index e4531af..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_ipp.s +++ /dev/null @@ -1,364 +0,0 @@ -//Original:/testcases/core/c_dspldst_ld_drhi_ipp/c_dspldst_ld_drhi_ipp.dsp -// Spec Reference: c_dspldst ld_drhi_i++/-- -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - - INIT_R_REGS 0; - -// initial values -//i0=0x3000; -//i1=0x4000; -//i2=0x5000; -//i3=0x6000; - loadsym I0, DATA_ADDR_3; - loadsym I1, DATA_ADDR_4; - loadsym I2, DATA_ADDR_5; - loadsym I3, DATA_ADDR_6; - -// Load Upper half of Dregs - R0.H = W [ I0 ++ ]; - R1.H = W [ I1 ++ ]; - R2.H = W [ I2 ++ ]; - R3.H = W [ I3 ++ ]; - R4.H = W [ I0 ++ ]; - R5.H = W [ I1 ++ ]; - R6.H = W [ I2 ++ ]; - R7.H = W [ I3 ++ ]; - CHECKREG r0, 0x02030000; - CHECKREG r1, 0x22230000; - CHECKREG r2, 0x42430000; - CHECKREG r3, 0x62630000; - CHECKREG r4, 0x00010000; - CHECKREG r5, 0x20210000; - CHECKREG r6, 0x40410000; - CHECKREG r7, 0x60610000; - - R1.H = W [ I0 ++ ]; - R2.H = W [ I1 ++ ]; - R3.H = W [ I2 ++ ]; - R4.H = W [ I3 ++ ]; - R5.H = W [ I0 ++ ]; - R6.H = W [ I1 ++ ]; - R7.H = W [ I2 ++ ]; - R0.H = W [ I3 ++ ]; - CHECKREG r0, 0x64650000; - CHECKREG r1, 0x06070000; - CHECKREG r2, 0x26270000; - CHECKREG r3, 0x46470000; - CHECKREG r4, 0x66670000; - CHECKREG r5, 0x04050000; - CHECKREG r6, 0x24250000; - CHECKREG r7, 0x44450000; - - R2.H = W [ I0 ++ ]; - R3.H = W [ I1 ++ ]; - R4.H = W [ I2 ++ ]; - R5.H = W [ I3 ++ ]; - R6.H = W [ I0 ++ ]; - R7.H = W [ I1 ++ ]; - R0.H = W [ I2 ++ ]; - R1.H = W [ I3 ++ ]; - CHECKREG r0, 0x48490000; - CHECKREG r1, 0x68690000; - CHECKREG r2, 0x0A0B0000; - CHECKREG r3, 0x2A2B0000; - CHECKREG r4, 0x4A4B0000; - CHECKREG r5, 0x6A6B0000; - CHECKREG r6, 0x08090000; - CHECKREG r7, 0x28290000; - - R3.H = W [ I0 ++ ]; - R4.H = W [ I1 ++ ]; - R5.H = W [ I2 ++ ]; - R6.H = W [ I3 ++ ]; - R7.H = W [ I0 ++ ]; - R0.H = W [ I1 ++ ]; - R1.H = W [ I2 ++ ]; - R2.H = W [ I3 ++ ]; - - CHECKREG r0, 0x2C2D0000; - CHECKREG r1, 0x4C4D0000; - CHECKREG r2, 0x6C6D0000; - CHECKREG r3, 0x0E0F0000; - CHECKREG r4, 0x2E2F0000; - CHECKREG r5, 0x4E4F0000; - CHECKREG r6, 0x6E6F0000; - CHECKREG r7, 0x0C0D0000; - -// reverse to minus mninus i-- -// Load Upper half of Dregs - R0.H = W [ I0 -- ]; - R1.H = W [ I1 -- ]; - R2.H = W [ I2 -- ]; - R3.H = W [ I3 -- ]; - R4.H = W [ I0 -- ]; - R5.H = W [ I1 -- ]; - R6.H = W [ I2 -- ]; - R7.H = W [ I3 -- ]; - CHECKREG r0, 0x12130000; - CHECKREG r1, 0x32330000; - CHECKREG r2, 0x52530000; - CHECKREG r3, 0x72730000; - CHECKREG r4, 0x0C0D0000; - CHECKREG r5, 0x2C2D0000; - CHECKREG r6, 0x4C4D0000; - CHECKREG r7, 0x6C6D0000; - - R1.H = W [ I0 -- ]; - R2.H = W [ I1 -- ]; - R3.H = W [ I2 -- ]; - R4.H = W [ I3 -- ]; - R5.H = W [ I0 -- ]; - R6.H = W [ I1 -- ]; - R7.H = W [ I2 -- ]; - R0.H = W [ I3 -- ]; - CHECKREG r0, 0x68690000; - CHECKREG r1, 0x0E0F0000; - CHECKREG r2, 0x2E2F0000; - CHECKREG r3, 0x4E4F0000; - CHECKREG r4, 0x6E6F0000; - CHECKREG r5, 0x08090000; - CHECKREG r6, 0x28290000; - CHECKREG r7, 0x48490000; - - R2.H = W [ I0 -- ]; - R3.H = W [ I1 -- ]; - R4.H = W [ I2 -- ]; - R5.H = W [ I3 -- ]; - R6.H = W [ I0 -- ]; - R7.H = W [ I1 -- ]; - R0.H = W [ I2 -- ]; - R1.H = W [ I3 -- ]; - CHECKREG r0, 0x44450000; - CHECKREG r1, 0x64650000; - CHECKREG r2, 0x0A0B0000; - CHECKREG r3, 0x2A2B0000; - CHECKREG r4, 0x4A4B0000; - CHECKREG r5, 0x6A6B0000; - CHECKREG r6, 0x04050000; - CHECKREG r7, 0x24250000; - - R3.H = W [ I0 -- ]; - R4.H = W [ I1 -- ]; - R5.H = W [ I2 -- ]; - R6.H = W [ I3 -- ]; - R7.H = W [ I0 -- ]; - R0.H = W [ I1 -- ]; - R1.H = W [ I2 -- ]; - R2.H = W [ I3 -- ]; - - CHECKREG r0, 0x20210000; - CHECKREG r1, 0x40410000; - CHECKREG r2, 0x60610000; - CHECKREG r3, 0x06070000; - CHECKREG r4, 0x26270000; - CHECKREG r5, 0x46470000; - CHECKREG r6, 0x66670000; - CHECKREG r7, 0x00010000; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data - -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xBC0DBE26 - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_i.s b/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_i.s deleted file mode 100644 index aec575c..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_i.s +++ /dev/null @@ -1,164 +0,0 @@ -//Original:/testcases/core/c_dspldst_ld_drlo_i/c_dspldst_ld_drlo_i.dsp -// Spec Reference: c_dspldst ld_drlo_i -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - -// Load Lower half of Dregs - R0.L = W [ I0 ]; - R1.L = W [ I1 ]; - R2.L = W [ I2 ]; - R3.L = W [ I3 ]; - R4.L = W [ I0 ]; - R5.L = W [ I1 ]; - R6.L = W [ I2 ]; - R7.L = W [ I3 ]; - CHECKREG r0, 0x00000203; - CHECKREG r1, 0x00002223; - CHECKREG r2, 0x00004243; - CHECKREG r3, 0x00006263; - CHECKREG r4, 0x00000203; - CHECKREG r5, 0x00002223; - CHECKREG r6, 0x00004243; - CHECKREG r7, 0x00006263; - - R1.L = W [ I0 ]; - R2.L = W [ I1 ]; - R3.L = W [ I2 ]; - R4.L = W [ I3 ]; - R5.L = W [ I0 ]; - R6.L = W [ I1 ]; - R7.L = W [ I2 ]; - R0.L = W [ I3 ]; - CHECKREG r0, 0x00006263; - CHECKREG r1, 0x00000203; - CHECKREG r2, 0x00002223; - CHECKREG r3, 0x00004243; - CHECKREG r4, 0x00006263; - CHECKREG r5, 0x00000203; - CHECKREG r6, 0x00002223; - CHECKREG r7, 0x00004243; - - R2.L = W [ I0 ]; - R3.L = W [ I1 ]; - R4.L = W [ I2 ]; - R5.L = W [ I3 ]; - R6.L = W [ I0 ]; - R7.L = W [ I1 ]; - R0.L = W [ I2 ]; - R1.L = W [ I3 ]; - CHECKREG r0, 0x00004243; - CHECKREG r1, 0x00006263; - CHECKREG r2, 0x00000203; - CHECKREG r3, 0x00002223; - CHECKREG r4, 0x00004243; - CHECKREG r5, 0x00006263; - CHECKREG r6, 0x00000203; - CHECKREG r7, 0x00002223; - - R3.L = W [ I0 ]; - R4.L = W [ I1 ]; - R5.L = W [ I2 ]; - R6.L = W [ I3 ]; - R7.L = W [ I0 ]; - R0.L = W [ I1 ]; - R1.L = W [ I2 ]; - R2.L = W [ I3 ]; - CHECKREG r0, 0x00002223; - CHECKREG r1, 0x00004243; - CHECKREG r2, 0x00006263; - CHECKREG r3, 0x00000203; - CHECKREG r4, 0x00002223; - CHECKREG r5, 0x00004243; - CHECKREG r6, 0x00006263; - CHECKREG r7, 0x00000203; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_ipp.s b/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_ipp.s deleted file mode 100644 index d47b6b8..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_ipp.s +++ /dev/null @@ -1,355 +0,0 @@ -//Original:/testcases/core/c_dspldst_ld_drlo_ipp/c_dspldst_ld_drlo_ipp.dsp -// Spec Reference: c_dspldst ld_drlo_i++/-- -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - -// Load Lower half of Dregs - R0.L = W [ I0 ++ ]; - R1.L = W [ I1 ++ ]; - R2.L = W [ I2 ++ ]; - R3.L = W [ I3 ++ ]; - R4.L = W [ I0 ++ ]; - R5.L = W [ I1 ++ ]; - R6.L = W [ I2 ++ ]; - R7.L = W [ I3 ++ ]; - CHECKREG r0, 0x00000203; - CHECKREG r1, 0x00002223; - CHECKREG r2, 0x00004243; - CHECKREG r3, 0x00006263; - CHECKREG r4, 0x00000001; - CHECKREG r5, 0x00002021; - CHECKREG r6, 0x00004041; - CHECKREG r7, 0x00006061; - - R1.L = W [ I0 ++ ]; - R2.L = W [ I1 ++ ]; - R3.L = W [ I2 ++ ]; - R4.L = W [ I3 ++ ]; - R5.L = W [ I0 ++ ]; - R6.L = W [ I1 ++ ]; - R7.L = W [ I2 ++ ]; - R0.L = W [ I3 ++ ]; - CHECKREG r0, 0x00006465; - CHECKREG r1, 0x00000607; - CHECKREG r2, 0x00002627; - CHECKREG r3, 0x00004647; - CHECKREG r4, 0x00006667; - CHECKREG r5, 0x00000405; - CHECKREG r6, 0x00002425; - CHECKREG r7, 0x00004445; - - R2.L = W [ I0 ++ ]; - R3.L = W [ I1 ++ ]; - R4.L = W [ I2 ++ ]; - R5.L = W [ I3 ++ ]; - R6.L = W [ I0 ++ ]; - R7.L = W [ I1 ++ ]; - R0.L = W [ I2 ++ ]; - R1.L = W [ I3 ++ ]; - CHECKREG r0, 0x00004849; - CHECKREG r1, 0x00006869; - CHECKREG r2, 0x00000A0B; - CHECKREG r3, 0x00002A2B; - CHECKREG r4, 0x00004A4B; - CHECKREG r5, 0x00006A6B; - CHECKREG r6, 0x00000809; - CHECKREG r7, 0x00002829; - - R3.L = W [ I0 ++ ]; - R4.L = W [ I1 ++ ]; - R5.L = W [ I2 ++ ]; - R6.L = W [ I3 ++ ]; - R7.L = W [ I0 ++ ]; - R0.L = W [ I1 ++ ]; - R1.L = W [ I2 ++ ]; - R2.L = W [ I3 ++ ]; - CHECKREG r0, 0x00002C2D; - CHECKREG r1, 0x00004C4D; - CHECKREG r2, 0x00006C6D; - CHECKREG r3, 0x00000E0F; - CHECKREG r4, 0x00002E2F; - CHECKREG r5, 0x00004E4F; - CHECKREG r6, 0x00006E6F; - CHECKREG r7, 0x00000C0D; - -// reverse to minus mninus i-- - -// Load Lower half of Dregs - R0.L = W [ I0 -- ]; - R1.L = W [ I1 -- ]; - R2.L = W [ I2 -- ]; - R3.L = W [ I3 -- ]; - R4.L = W [ I0 -- ]; - R5.L = W [ I1 -- ]; - R6.L = W [ I2 -- ]; - R7.L = W [ I3 -- ]; - CHECKREG r0, 0x00001213; - CHECKREG r1, 0x00003233; - CHECKREG r2, 0x00005253; - CHECKREG r3, 0x00007273; - CHECKREG r4, 0x00000C0D; - CHECKREG r5, 0x00002C2D; - CHECKREG r6, 0x00004C4D; - CHECKREG r7, 0x00006C6D; - - R1.L = W [ I0 -- ]; - R2.L = W [ I1 -- ]; - R3.L = W [ I2 -- ]; - R4.L = W [ I3 -- ]; - R5.L = W [ I0 -- ]; - R6.L = W [ I1 -- ]; - R7.L = W [ I2 -- ]; - R0.L = W [ I3 -- ]; - CHECKREG r0, 0x00006869; - CHECKREG r1, 0x00000E0F; - CHECKREG r2, 0x00002E2F; - CHECKREG r3, 0x00004E4F; - CHECKREG r4, 0x00006E6F; - CHECKREG r5, 0x00000809; - CHECKREG r6, 0x00002829; - CHECKREG r7, 0x00004849; - - R2.L = W [ I0 -- ]; - R3.L = W [ I1 -- ]; - R4.L = W [ I2 -- ]; - R5.L = W [ I3 -- ]; - R6.L = W [ I0 -- ]; - R7.L = W [ I1 -- ]; - R0.L = W [ I2 -- ]; - R1.L = W [ I3 -- ]; - CHECKREG r0, 0x00004445; - CHECKREG r1, 0x00006465; - CHECKREG r2, 0x00000A0B; - CHECKREG r3, 0x00002A2B; - CHECKREG r4, 0x00004A4B; - CHECKREG r5, 0x00006A6B; - CHECKREG r6, 0x00000405; - CHECKREG r7, 0x00002425; - - R3.L = W [ I0 -- ]; - R4.L = W [ I1 -- ]; - R5.L = W [ I2 -- ]; - R6.L = W [ I3 -- ]; - R7.L = W [ I0 -- ]; - R0.L = W [ I1 -- ]; - R1.L = W [ I2 -- ]; - R2.L = W [ I3 -- ]; - CHECKREG r0, 0x00002021; - CHECKREG r1, 0x00004041; - CHECKREG r2, 0x00006061; - CHECKREG r3, 0x00000607; - CHECKREG r4, 0x00002627; - CHECKREG r5, 0x00004647; - CHECKREG r6, 0x00006667; - CHECKREG r7, 0x00000001; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xBC0DBE26 - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_dr_i.s b/sim/testsuite/sim/bfin/c_dspldst_st_dr_i.s deleted file mode 100644 index 7434607..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_st_dr_i.s +++ /dev/null @@ -1,185 +0,0 @@ -//Original:/testcases/core/c_dspldst_st_dr_i/c_dspldst_st_dr_i.dsp -// Spec Reference: c_dspldst st_dr_i -# mach: bfin - -.include "testutils.inc" - start - - - imm32 r0, 0x0a234507; - imm32 r1, 0x1b345618; - imm32 r2, 0x2c456729; - imm32 r3, 0x3d56783a; - imm32 r4, 0x4e67894b; - imm32 r5, 0x5f789a5c; - imm32 r6, 0x6089ab6d; - imm32 r7, 0x719abc7e; - - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - - [ I0 ] = R0; - [ I1 ] = R1; - [ I2 ] = R2; - [ I3 ] = R3; - R4 = [ I0 ]; - R5 = [ I1 ]; - R6 = [ I2 ]; - R7 = [ I3 ]; - CHECKREG r4, 0x0a234507; - CHECKREG r5, 0x1b345618; - CHECKREG r6, 0x2c456729; - CHECKREG r7, 0x3d56783a; - imm32 r4, 0x4e67894b; - imm32 r5, 0x5f789a5c; - imm32 r6, 0x6089ab6d; - imm32 r7, 0x719abc7e; - [ I0 ] = R1; - [ I1 ] = R2; - [ I2 ] = R3; - [ I3 ] = R4; - R4 = [ I0 ]; - R5 = [ I1 ]; - R6 = [ I2 ]; - R7 = [ I3 ]; - CHECKREG r4, 0x1b345618; - CHECKREG r5, 0x2c456729; - CHECKREG r6, 0x3d56783a; - CHECKREG r7, 0x4e67894b; - - imm32 r4, 0x4e67894b; - imm32 r5, 0x5f789a5c; - imm32 r6, 0x6089ab6d; - imm32 r7, 0x719abc7e; - - [ I0 ] = R2; - [ I1 ] = R3; - [ I2 ] = R4; - [ I3 ] = R5; - R4 = [ I0 ]; - R5 = [ I1 ]; - R6 = [ I2 ]; - R7 = [ I3 ]; - CHECKREG r4, 0x2c456729; - CHECKREG r5, 0x3d56783a; - CHECKREG r6, 0x4e67894b; - CHECKREG r7, 0x5f789a5c; - - imm32 r4, 0x4e67894b; - imm32 r5, 0x5f789a5c; - imm32 r6, 0x6089ab6d; - imm32 r7, 0x719abc7e; - [ I0 ] = R3; - [ I1 ] = R4; - [ I2 ] = R5; - [ I3 ] = R6; - R4 = [ I0 ]; - R5 = [ I1 ]; - R6 = [ I2 ]; - R7 = [ I3 ]; - CHECKREG r4, 0x3d56783a; - CHECKREG r5, 0x4e67894b; - CHECKREG r6, 0x5f789a5c; - CHECKREG r7, 0x6089ab6d; - - imm32 r4, 0x4e67894b; - imm32 r5, 0x5f789a5c; - imm32 r6, 0x6089ab6d; - imm32 r7, 0x719abc7e; - [ I0 ] = R4; - [ I1 ] = R5; - [ I2 ] = R6; - [ I3 ] = R7; - R0 = [ I0 ]; - R1 = [ I1 ]; - R2 = [ I2 ]; - R3 = [ I3 ]; - CHECKREG r0, 0x4e67894b; - CHECKREG r1, 0x5f789a5c; - CHECKREG r2, 0x6089ab6d; - CHECKREG r3, 0x719abc7e; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data - -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_dr_ipp.s b/sim/testsuite/sim/bfin/c_dspldst_st_dr_ipp.s deleted file mode 100644 index 87404a1..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_st_dr_ipp.s +++ /dev/null @@ -1,326 +0,0 @@ -//Original:testcases/core/c_dspldst_st_dr_ipp/c_dspldst_st_dr_ipp.dsp -// Spec Reference: c_dspldst st_dr_ipp -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -//INIT_I_REGS -1; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; - - imm32 r0, 0x0a234507; - imm32 r1, 0x1b345618; - imm32 r2, 0x2c456729; - imm32 r3, 0x3d56783a; - imm32 r4, 0x4e67894b; - imm32 r5, 0x5f789a5c; - imm32 r6, 0x6089ab6d; - imm32 r7, 0x719abc7e; - -// initial values - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - - [ I0 ++ ] = R0; - [ I1 ++ ] = R1; - [ I2 ++ ] = R2; - [ I3 ++ ] = R3; - - [ I0 ++ ] = R1; - [ I1 ++ ] = R2; - [ I2 ++ ] = R3; - [ I3 ++ ] = R4; - - [ I0 ++ ] = R3; - [ I1 ++ ] = R4; - [ I2 ++ ] = R5; - [ I3 ++ ] = R6; - - [ I0 ++ ] = R4; - [ I1 ++ ] = R5; - [ I2 ++ ] = R6; - [ I3 ++ ] = R7; - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - R0 = [ I0 ++ ]; - R1 = [ I1 ++ ]; - R2 = [ I2 ++ ]; - R3 = [ I3 ++ ]; - R4 = [ I0 ++ ]; - R5 = [ I1 ++ ]; - R6 = [ I2 ++ ]; - R7 = [ I3 ++ ]; - CHECKREG r0, 0x0a234507; - CHECKREG r1, 0x1b345618; - CHECKREG r2, 0x2c456729; - CHECKREG r3, 0x3d56783a; - CHECKREG r4, 0x1B345618; - CHECKREG r5, 0x2C456729; - CHECKREG r6, 0x3D56783A; - CHECKREG r7, 0x4E67894B; - R0 = [ I0 ++ ]; - R1 = [ I1 ++ ]; - R2 = [ I2 ++ ]; - R3 = [ I3 ++ ]; - R4 = [ I0 ++ ]; - R5 = [ I1 ++ ]; - R6 = [ I2 ++ ]; - R7 = [ I3 ++ ]; - CHECKREG r0, 0x3D56783A; - CHECKREG r1, 0x4E67894B; - CHECKREG r2, 0x5F789A5C; - CHECKREG r3, 0x6089AB6D; - CHECKREG r4, 0x4E67894B; - CHECKREG r5, 0x5F789A5C; - CHECKREG r6, 0x6089AB6D; - CHECKREG r7, 0x719ABC7E; - -// initial values - - imm32 r0, 0xa0b2c3d4; - imm32 r1, 0x1b245618; - imm32 r2, 0x22b36729; - imm32 r3, 0xbd3c483a; - imm32 r4, 0xde64d54b; - imm32 r5, 0x5f785e6c; - imm32 r6, 0x30896bf7; - imm32 r7, 0x719ab770; - loadsym i0, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym i2, DATA_ADDR_5, 0x20; - loadsym i3, DATA_ADDR_6, 0x20; - - [ I0 -- ] = R0; - [ I1 -- ] = R1; - [ I2 -- ] = R2; - [ I3 -- ] = R3; - [ I0 -- ] = R4; - [ I1 -- ] = R5; - [ I2 -- ] = R6; - [ I3 -- ] = R7; - loadsym i0, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym i2, DATA_ADDR_5, 0x20; - loadsym i3, DATA_ADDR_6, 0x20; - R0 = [ I0 -- ]; - R1 = [ I1 -- ]; - R2 = [ I2 -- ]; - R3 = [ I3 -- ]; - R4 = [ I0 -- ]; - R5 = [ I1 -- ]; - R6 = [ I2 -- ]; - R7 = [ I3 -- ]; - CHECKREG r0, 0xA0B2C3D4; - CHECKREG r1, 0x1B245618; - CHECKREG r2, 0x22B36729; - CHECKREG r3, 0xBD3C483A; - CHECKREG r4, 0xDE64D54B; - CHECKREG r5, 0x5F785E6C; - CHECKREG r6, 0x30896BF7; - CHECKREG r7, 0x719AB770; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_dr_ippm.s b/sim/testsuite/sim/bfin/c_dspldst_st_dr_ippm.s deleted file mode 100644 index 9b08838..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_st_dr_ippm.s +++ /dev/null @@ -1,279 +0,0 @@ -//Original:/testcases/core/c_dspldst_st_dr_ippm/c_dspldst_st_dr_ippm.dsp -// Spec Reference: c_dspldst st_dr_ippm -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x0a234507; - imm32 r1, 0x1b345618; - imm32 r2, 0x2c456729; - imm32 r3, 0x3d56783a; - imm32 r4, 0x4e67894b; - imm32 r5, 0x5f789a5c; - imm32 r6, 0x6089ab6d; - imm32 r7, 0x719abc7e; - - M0 = 4 (X); - M1 = 0x4 (X); - M2 = 0x4 (X); - M3 = 0x4 (X); - - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - - [ I0 ++ M0 ] = R0; - [ I1 ++ M1 ] = R1; - [ I2 ++ M2 ] = R2; - [ I3 ++ M3 ] = R3; - [ I0 ++ M1 ] = R1; - [ I1 ++ M2 ] = R2; - [ I2 ++ M3 ] = R3; - [ I3 ++ M0 ] = R4; - - [ I0 ++ M2 ] = R3; - [ I1 ++ M3 ] = R4; - [ I2 ++ M0 ] = R5; - [ I3 ++ M1 ] = R6; - [ I0 ++ M3 ] = R4; - [ I1 ++ M0 ] = R5; - [ I2 ++ M1 ] = R6; - [ I3 ++ M2 ] = R7; - - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - - R0 = [ I0 ++ M0 ]; - R1 = [ I1 ++ M1 ]; - R2 = [ I2 ++ M2 ]; - R3 = [ I3 ++ M3 ]; - R4 = [ I0 ++ M1 ]; - R5 = [ I1 ++ M2 ]; - R6 = [ I2 ++ M3 ]; - R7 = [ I3 ++ M0 ]; - CHECKREG r0, 0x0A234507; - CHECKREG r1, 0x1B345618; - CHECKREG r2, 0x2C456729; - CHECKREG r3, 0x3D56783A; - CHECKREG r4, 0x1B345618; - CHECKREG r5, 0x2C456729; - CHECKREG r6, 0x3D56783A; - CHECKREG r7, 0x4E67894B; - R0 = [ I0 ++ M2 ]; - R1 = [ I1 ++ M3 ]; - R2 = [ I2 ++ M0 ]; - R3 = [ I3 ++ M1 ]; - R4 = [ I0 ++ M3 ]; - R5 = [ I1 ++ M0 ]; - R6 = [ I2 ++ M1 ]; - R7 = [ I3 ++ M2 ]; - CHECKREG r0, 0x3D56783A; - CHECKREG r1, 0x4E67894B; - CHECKREG r2, 0x5F789A5C; - CHECKREG r3, 0x6089AB6D; - CHECKREG r4, 0x4E67894B; - CHECKREG r5, 0x5F789A5C; - CHECKREG r6, 0x6089AB6D; - CHECKREG r7, 0x719ABC7E; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_drhi_i.s b/sim/testsuite/sim/bfin/c_dspldst_st_drhi_i.s deleted file mode 100644 index a5aefc8..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_st_drhi_i.s +++ /dev/null @@ -1,161 +0,0 @@ -//Original:/testcases/core/c_dspldst_st_drhi_i/c_dspldst_st_drhi_i.dsp -// Spec Reference: c_dspldst st_drhi_i -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x0a234507; - imm32 r1, 0x1b345618; - imm32 r2, 0x2c456729; - imm32 r3, 0x3d56783a; - imm32 r4, 0x4e67894b; - imm32 r5, 0x5f789a5c; - imm32 r6, 0x6089ab6d; - imm32 r7, 0x719abc7e; - - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - - W [ I0 ] = R0.H; - W [ I1 ] = R1.H; - W [ I2 ] = R2.H; - W [ I3 ] = R3.H; - R4 = [ I0 ]; - R5 = [ I1 ]; - R6 = [ I2 ]; - R7 = [ I3 ]; - CHECKREG r4, 0x00010A23; - CHECKREG r5, 0x20211B34; - CHECKREG r6, 0x40412C45; - CHECKREG r7, 0x60613D56; - W [ I0 ] = R1.H; - W [ I1 ] = R2.H; - W [ I2 ] = R3.H; - W [ I3 ] = R4.H; - R4 = [ I0 ]; - R5 = [ I1 ]; - R6 = [ I2 ]; - R7 = [ I3 ]; - CHECKREG r4, 0x00011B34; - CHECKREG r5, 0x20212C45; - CHECKREG r6, 0x40413D56; - CHECKREG r7, 0x60610001; - - imm32 r0, 0x0a234507; - imm32 r1, 0x1b345618; - imm32 r2, 0x2c456729; - imm32 r3, 0x3d56783a; - imm32 r4, 0x4e67894b; - imm32 r5, 0x5f789a5c; - imm32 r6, 0x6089ab6d; - imm32 r7, 0x719abc7e; - W [ I0 ] = R2.H; - W [ I1 ] = R3.H; - W [ I2 ] = R4.H; - W [ I3 ] = R5.H; - R0 = [ I0 ]; - R1 = [ I1 ]; - R6 = [ I2 ]; - R7 = [ I3 ]; - CHECKREG r0, 0x00012C45; - CHECKREG r1, 0x20213D56; - CHECKREG r6, 0x40414E67; - CHECKREG r7, 0x60615F78; - - W [ I0 ] = R4.H; - W [ I1 ] = R5.H; - W [ I2 ] = R6.H; - W [ I3 ] = R7.H; - R0 = [ I0 ]; - R1 = [ I1 ]; - R2 = [ I2 ]; - R3 = [ I3 ]; - CHECKREG r0, 0x00014E67; - CHECKREG r1, 0x20215F78; - CHECKREG r6, 0x40414E67; - CHECKREG r7, 0x60615F78; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_drhi_ipp.s b/sim/testsuite/sim/bfin/c_dspldst_st_drhi_ipp.s deleted file mode 100644 index 4e25d9d..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_st_drhi_ipp.s +++ /dev/null @@ -1,355 +0,0 @@ -//Original:testcases/core/c_dspldst_st_drhi_ipp/c_dspldst_st_drhi_ipp.dsp -// Spec Reference: c_dspldst st_drhi_ipp -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -INIT_I_REGS -1; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; - -// Half reg 16 bit mem store - - imm32 r0, 0x0a123456; - imm32 r1, 0x11b12345; - imm32 r2, 0x222c1234; - imm32 r3, 0x3344d012; - imm32 r4, 0x5566e012; - imm32 r5, 0x789abf01; - imm32 r6, 0xabcd0123; - imm32 r7, 0x01234567; - -// initial values - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - - W [ I0 ++ ] = R0.H; - W [ I1 ++ ] = R1.H; - W [ I2 ++ ] = R2.H; - W [ I3 ++ ] = R3.H; - W [ I0 ++ ] = R1.H; - W [ I1 ++ ] = R2.H; - W [ I2 ++ ] = R3.H; - W [ I3 ++ ] = R4.H; - - W [ I0 ++ ] = R3.H; - W [ I1 ++ ] = R4.H; - W [ I2 ++ ] = R5.H; - W [ I3 ++ ] = R6.H; - - W [ I0 ++ ] = R4.H; - W [ I1 ++ ] = R5.H; - W [ I2 ++ ] = R6.H; - W [ I3 ++ ] = R7.H; - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - R0 = [ I0 ++ ]; - R1 = [ I1 ++ ]; - R2 = [ I2 ++ ]; - R3 = [ I3 ++ ]; - R4 = [ I0 ++ ]; - R5 = [ I1 ++ ]; - R6 = [ I2 ++ ]; - R7 = [ I3 ++ ]; - CHECKREG r0, 0x11B10A12; - CHECKREG r1, 0x222C11B1; - CHECKREG r2, 0x3344222C; - CHECKREG r3, 0x55663344; - CHECKREG r4, 0x55663344; - CHECKREG r5, 0x789A5566; - CHECKREG r6, 0xABCD789A; - CHECKREG r7, 0x0123ABCD; - - R0 = [ I0 ++ ]; - R1 = [ I1 ++ ]; - R2 = [ I2 ++ ]; - R3 = [ I3 ++ ]; - R4 = [ I0 ++ ]; - R5 = [ I1 ++ ]; - R6 = [ I2 ++ ]; - R7 = [ I3 ++ ]; - CHECKREG r0, 0x08090A0B; - CHECKREG r1, 0x28292A2B; - CHECKREG r2, 0x48494A4B; - CHECKREG r3, 0x68696A6B; - CHECKREG r4, 0x0C0D0E0F; - CHECKREG r5, 0x2C2D2E2F; - CHECKREG r6, 0x4C4D4E4F; - CHECKREG r7, 0x6C6D6E6F; - -// initial values - - imm32 r0, 0x01b2c3d4; - imm32 r1, 0x10145618; - imm32 r2, 0xa2016729; - imm32 r3, 0xbb30183a; - imm32 r4, 0xdec4014b; - imm32 r5, 0x5f7d501c; - imm32 r6, 0x3089eb01; - imm32 r7, 0x719abf70; - - loadsym i0, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym i2, DATA_ADDR_5, 0x20; - loadsym i3, DATA_ADDR_6, 0x20; - - W [ I0 -- ] = R0.H; - W [ I1 -- ] = R1.H; - W [ I2 -- ] = R2.H; - W [ I3 -- ] = R3.H; - W [ I0 -- ] = R1.H; - W [ I1 -- ] = R2.H; - W [ I2 -- ] = R3.H; - W [ I3 -- ] = R4.H; - - W [ I0 -- ] = R3.H; - W [ I1 -- ] = R4.H; - W [ I2 -- ] = R5.H; - W [ I3 -- ] = R6.H; - W [ I0 -- ] = R4.H; - W [ I1 -- ] = R5.H; - W [ I2 -- ] = R6.H; - W [ I3 -- ] = R7.H; - loadsym i0, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym i2, DATA_ADDR_5, 0x20; - loadsym i3, DATA_ADDR_6, 0x20; - R0 = [ I0 -- ]; - R1 = [ I1 -- ]; - R2 = [ I2 -- ]; - R3 = [ I3 -- ]; - R4 = [ I0 -- ]; - R5 = [ I1 -- ]; - R6 = [ I2 -- ]; - R7 = [ I3 -- ]; - CHECKREG r0, 0x000001B2; - CHECKREG r1, 0x00001014; - CHECKREG r2, 0x0000A201; - CHECKREG r3, 0x0000BB30; - CHECKREG r4, 0x1014BB30; - CHECKREG r5, 0xA201DEC4; - CHECKREG r6, 0xBB305F7D; - CHECKREG r7, 0xDEC43089; - - R0 = [ I0 -- ]; - R1 = [ I1 -- ]; - R2 = [ I2 -- ]; - R3 = [ I3 -- ]; - R4 = [ I0 -- ]; - R5 = [ I1 -- ]; - R6 = [ I2 -- ]; - R7 = [ I3 -- ]; - CHECKREG r0, 0xDEC41A1B; - CHECKREG r1, 0x5F7D3A3B; - CHECKREG r2, 0x30895A5B; - CHECKREG r3, 0x719A7A7B; - CHECKREG r4, 0x14151617; - CHECKREG r5, 0x34353637; - CHECKREG r6, 0x54555657; - CHECKREG r7, 0x74757677; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_drlo_i.s b/sim/testsuite/sim/bfin/c_dspldst_st_drlo_i.s deleted file mode 100644 index 7b36691..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_st_drlo_i.s +++ /dev/null @@ -1,163 +0,0 @@ -//Original:/testcases/core/c_dspldst_st_drlo_i/c_dspldst_st_drlo_i.dsp -// Spec Reference: c_dspldst st_drlo_i -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x0a234507; - imm32 r1, 0x1b345618; - imm32 r2, 0x2c456729; - imm32 r3, 0x3d56783a; - imm32 r4, 0x4e67894b; - imm32 r5, 0x5f789a5c; - imm32 r6, 0x6089ab6d; - imm32 r7, 0x719abc7e; - - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - - W [ I0 ] = R0.L; - W [ I1 ] = R1.L; - W [ I2 ] = R2.L; - W [ I3 ] = R3.L; - R4 = [ I0 ]; - R5 = [ I1 ]; - R6 = [ I2 ]; - R7 = [ I3 ]; - CHECKREG r4, 0x00014507; - CHECKREG r5, 0x20215618; - CHECKREG r6, 0x40416729; - CHECKREG r7, 0x6061783A; - W [ I0 ] = R3.L; - W [ I1 ] = R2.L; - W [ I2 ] = R1.L; - W [ I3 ] = R0.L; - R4 = [ I0 ]; - R5 = [ I1 ]; - R6 = [ I2 ]; - R7 = [ I3 ]; - CHECKREG r4, 0x0001783A; - CHECKREG r5, 0x20216729; - CHECKREG r6, 0x40415618; - CHECKREG r7, 0x60614507; - - imm32 r0, 0x1a334507; - imm32 r1, 0x12345618; - imm32 r2, 0x2c3e6729; - imm32 r3, 0x3d54f83a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f789c5c; - imm32 r6, 0x6089ad7d; - imm32 r7, 0x739abc88; - - W [ I0 ] = R4.L; - W [ I1 ] = R5.L; - W [ I2 ] = R6.L; - W [ I3 ] = R7.L; - R0 = [ I0 ]; - R1 = [ I1 ]; - R2 = [ I2 ]; - R3 = [ I3 ]; - CHECKREG r0, 0x0001594B; - CHECKREG r1, 0x20219C5C; - CHECKREG r2, 0x4041AD7D; - CHECKREG r3, 0x6061BC88; - - W [ I0 ] = R7.L; - W [ I1 ] = R6.L; - W [ I2 ] = R5.L; - W [ I3 ] = R4.L; - R0 = [ I0 ]; - R1 = [ I1 ]; - R2 = [ I2 ]; - R3 = [ I3 ]; - CHECKREG r0, 0x0001BC88; - CHECKREG r1, 0x2021AD7D; - CHECKREG r2, 0x40419C5C; - CHECKREG r3, 0x6061594B; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data - -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_drlo_ipp.s b/sim/testsuite/sim/bfin/c_dspldst_st_drlo_ipp.s deleted file mode 100644 index 08483e3..0000000 --- a/sim/testsuite/sim/bfin/c_dspldst_st_drlo_ipp.s +++ /dev/null @@ -1,351 +0,0 @@ -//Original:testcases/core/c_dspldst_st_drlo_ipp/c_dspldst_st_drlo_ipp.dsp -// Spec Reference: c_dspldst st_drlo_ipp -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -INIT_I_REGS -1; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; - -// Half reg 16 bit mem store - - imm32 r0, 0x0a123456; - imm32 r1, 0x11b12345; - imm32 r2, 0x222c1234; - imm32 r3, 0x3344d012; - imm32 r4, 0x5566e012; - imm32 r5, 0x789abf01; - imm32 r6, 0xabcd0123; - imm32 r7, 0x01234567; - -// initial values - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - - W [ I0 ++ ] = R0.L; - W [ I1 ++ ] = R1.L; - W [ I2 ++ ] = R2.L; - W [ I3 ++ ] = R3.L; - W [ I0 ++ ] = R1.L; - W [ I1 ++ ] = R2.L; - W [ I2 ++ ] = R3.L; - W [ I3 ++ ] = R4.L; - - W [ I0 ++ ] = R3.L; - W [ I1 ++ ] = R4.L; - W [ I2 ++ ] = R5.L; - W [ I3 ++ ] = R6.L; - W [ I0 ++ ] = R4.L; - W [ I1 ++ ] = R5.L; - W [ I2 ++ ] = R6.L; - W [ I3 ++ ] = R7.L; - loadsym i0, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym i2, DATA_ADDR_5; - loadsym i3, DATA_ADDR_6; - R0 = [ I0 ++ ]; - R1 = [ I1 ++ ]; - R2 = [ I2 ++ ]; - R3 = [ I3 ++ ]; - R4 = [ I0 ++ ]; - R5 = [ I1 ++ ]; - R6 = [ I2 ++ ]; - R7 = [ I3 ++ ]; - CHECKREG r0, 0x23453456; - CHECKREG r1, 0x12342345; - CHECKREG r2, 0xD0121234; - CHECKREG r3, 0xE012D012; - CHECKREG r4, 0xE012D012; - CHECKREG r5, 0xBF01E012; - CHECKREG r6, 0x0123BF01; - CHECKREG r7, 0x45670123; - - R0 = [ I0 ++ ]; - R1 = [ I1 ++ ]; - R2 = [ I2 ++ ]; - R3 = [ I3 ++ ]; - R4 = [ I0 ++ ]; - R5 = [ I1 ++ ]; - R6 = [ I2 ++ ]; - R7 = [ I3 ++ ]; - CHECKREG r0, 0x08090A0B; - CHECKREG r1, 0x28292A2B; - CHECKREG r2, 0x48494A4B; - CHECKREG r3, 0x68696A6B; - CHECKREG r4, 0x0C0D0E0F; - CHECKREG r5, 0x2C2D2E2F; - CHECKREG r6, 0x4C4D4E4F; - CHECKREG r7, 0x6C6D6E6F; - -// initial values - - imm32 r0, 0x01b2c3d4; - imm32 r1, 0x10145618; - imm32 r2, 0xa2016729; - imm32 r3, 0xbb30183a; - imm32 r4, 0xdec4014b; - imm32 r5, 0x5f7d501c; - imm32 r6, 0x3089eb01; - imm32 r7, 0x719abf70; - loadsym i0, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym i2, DATA_ADDR_5, 0x20; - loadsym i3, DATA_ADDR_6, 0x20; - - W [ I0 -- ] = R0.L; - W [ I1 -- ] = R1.L; - W [ I2 -- ] = R2.L; - W [ I3 -- ] = R3.L; - W [ I0 -- ] = R1.L; - W [ I1 -- ] = R2.L; - W [ I2 -- ] = R3.L; - W [ I3 -- ] = R4.L; - - W [ I0 -- ] = R3.L; - W [ I1 -- ] = R4.L; - W [ I2 -- ] = R5.L; - W [ I3 -- ] = R6.L; - W [ I0 -- ] = R4.L; - W [ I1 -- ] = R5.L; - W [ I2 -- ] = R6.L; - W [ I3 -- ] = R7.L; - loadsym i0, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym i2, DATA_ADDR_5, 0x20; - loadsym i3, DATA_ADDR_6, 0x20; - R0 = [ I0 -- ]; - R1 = [ I1 -- ]; - R2 = [ I2 -- ]; - R3 = [ I3 -- ]; - R4 = [ I0 -- ]; - R5 = [ I1 -- ]; - R6 = [ I2 -- ]; - R7 = [ I3 -- ]; - CHECKREG r0, 0x0000C3D4; - CHECKREG r1, 0x00005618; - CHECKREG r2, 0x00006729; - CHECKREG r3, 0x0000183A; - CHECKREG r4, 0x5618183A; - CHECKREG r5, 0x6729014B; - CHECKREG r6, 0x183A501C; - CHECKREG r7, 0x014BEB01; - R0 = [ I0 -- ]; - R1 = [ I1 -- ]; - R2 = [ I2 -- ]; - R3 = [ I3 -- ]; - R4 = [ I0 -- ]; - R5 = [ I1 -- ]; - R6 = [ I2 -- ]; - R7 = [ I3 -- ]; - CHECKREG r0, 0x014B1A1B; - CHECKREG r1, 0x501C3A3B; - CHECKREG r2, 0xEB015A5B; - CHECKREG r3, 0xBF707A7B; - CHECKREG r4, 0x14151617; - CHECKREG r5, 0x34353637; - CHECKREG r6, 0x54555657; - CHECKREG r7, 0x74757677; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_3: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_4: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_5: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_6: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_8: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_except_illopcode.S b/sim/testsuite/sim/bfin/c_except_illopcode.S deleted file mode 100644 index bf6c66d..0000000 --- a/sim/testsuite/sim/bfin/c_except_illopcode.S +++ /dev/null @@ -1,99 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_except_illopcode/c_except_illopcode.dsp -// Spec Reference: c_exception illegal opcode -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -// load address of exception handler - -P0 = 0x200C (Z); // 0xFFE0200C EVT3 EXCEPTION -P0.H = 0xFFE0; -R0 = exception_handler (Z); // wr address of exception handler to MMR EVT3 -R0.H = exception_handler; -[ P0 ] = R0; - -// Jump to User mode and enable exceptions - -R0 = MidUserCode (Z); -R0.H = MidUserCode; -RETI = R0; -RTI; // cause it to go to Midusercode, .dd cause exception - -BeginUserCode: -P1 = 1; -P2 = 2; -P3 = 3; -P4 = 4; - -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000001); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000003); -// CHECKREG(r4, 0x00000098); -CHECKREG(r5, 0x00000005); -CHECKREG(r6, 0x00000006); -CHECKREG(r7, 0x00000007); -CHECKREG(p1, 0x00000001); -CHECKREG(p2, 0x00000002); -CHECKREG(p3, 0x00000003); -CHECKREG(p4, 0x00000004); - -dbg_pass; -//jump 2; -//jump -2; -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF - -//dbg_pass; - -MidUserCode: -.dd 0xFFFFFFFF -R0 = 0; -R1 = 1; -R2 = 2; -R3 = 3; -CC = R0; -IF !CC JUMP BeginUserCode; - -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF - -//.code 0x800 - -exception_handler: -R4 = RETX; // error handler: RETX has the address of the same Illegal instr -R5 = 5; -R6 = 6; -R7 = 7; -R4 += 4; // we have to add 4 to point to next instr after return -RETX = R4; - -RTX; // return from exception - //nop; - -.section MEM_DATA_ADDR_1,"aw" -.dd 0xDEADBEEF -.dd 0xBAD00BAD diff --git a/sim/testsuite/sim/bfin/c_except_sys_sstep.S b/sim/testsuite/sim/bfin/c_except_sys_sstep.S deleted file mode 100644 index c719555..0000000 --- a/sim/testsuite/sim/bfin/c_except_sys_sstep.S +++ /dev/null @@ -1,252 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_except_sys_sstep/c_except_sys_sstep.dsp -// Spec Reference: Single Step Supervisor Exception Test (NO REGTRACE!) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -// - -////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -// CHECK_INIT(p2, 0x2000); -include(symtable.inc) -CHECK_INIT_DEF(p2); - - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - R0 = 1; -SYSCFG = r0; // Enable Supervisor Single Step - R4 = 0; - -LD32_LABEL(r0, START); -RETI = r0; // We need to load the return address - -RTI; - - -START: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - R0 = 0; - R1 = 1; - R2 = 2; - R3 = 3; - R5 = 5; - R6 = 6; - R7 = 7; - -EXCPT 3; // turn off single step via handler - -CHECKREG(r4, 0x0b); // 11 instrs are executed before single step = disabled -CHECKREG(r0, 0x00); -CHECKREG(r1, 0x03); -CHECKREG(r2, 0x10); -CHECKREG(r3, 0x04); -CHECKREG(r5, 0x09); -CHECKREG(r6, 0x06); -CHECKREG(r7, 0x07); - - - // PUT YOUR TEST HERE! - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - [ -- SP ] = ASTAT; // save ASTAT - R1 = SEQSTAT; - R1 <<= 26; - R1 >>= 26; // only want EXCAUSE - R2 = 0x10; // EXCAUSE 0x10 means Single Step (exception) -CC = r1 == r2; -IF CC JUMP SSCOUNT; // Go to Single Step Handler - -SYSCFG = r0; // otherwise must be an EXCPT, so turn off singlestep - R3 += 1; - -JUMP.S EXIT; - -SSCOUNT: - R4 += 1; // R4 counts single step events - -EXIT: -ASTAT = [sp++]; - R5 += 1; - -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_except_user_mode.S b/sim/testsuite/sim/bfin/c_except_user_mode.S deleted file mode 100644 index 8c71bd7f..0000000 --- a/sim/testsuite/sim/bfin/c_except_user_mode.S +++ /dev/null @@ -1,349 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_except_user_mode/c_except_user_mode.dsp -// Spec Reference: except_mode_user -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -// - -////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -// JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; // execute this instr put us in USER mode - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // USER MODE & go to different RAISE in USER mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! - // Can't Raise 0, 3, or 4 - // Raise 1 requires some intelligence so the test - // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) -RAISE 2; // RTN // exception because we execute this in USER mode -RAISE 5; // RTI -RAISE 6; // RTI -RAISE 7; // RTI -RAISE 8; // RTI -RAISE 9; // RTI -RAISE 10; // RTI -RAISE 11; // RTI -RAISE 12; // RTI -RAISE 13; // RTI -RAISE 14; // RTI - -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; - - -CHECKREG(r0, 0x00000018); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x00000000); -CHECKREG(r4, 0x00000000); -CHECKREG(r5, 0x00000000); -CHECKREG(r6, 0x00000000); -CHECKREG(r7, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = RETN; - R0 += 2; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; -RETN = r0; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = RETX; - I0 += 2; - R1 += 2; // for return address -RETX = r1; -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = RETI; - R2 += 2; - I0 += 2; - I1 += 2; -RETI = r2; -RTI; - -THANDLE: // Timer Handler 6 - R3 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - R3 += 2; -RETI = r3; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = RETI; - I0 += 2; - I1 += 2; - I3 += 2; - R4 += 2; -RETI = r4; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - R5 += 2; -RETI = r5; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - R6 += 2; -RETI = r6; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - R7 += 2; -RETI = r7; -RTI; - -I11HANDLE: // IVG 11 Handler - R0 = RETI; - R0 += 2; - M0 = I0; - M1 = I1; - M2 = I2; - M3 = I3; -RETI = r0; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - R1 += 2; -RETI = r1; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - R2 += 2; -RETI = r2; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - R3 += 2; -RETI = r3; -RTI; - -I15HANDLE: // IVG 15 Handler - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; -RTI; - -// nop;nop;nop;nop;nop;nop;nop; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: -// .space (STACKSIZE); // adding this may solve the problem diff --git a/sim/testsuite/sim/bfin/c_interr_disable.S b/sim/testsuite/sim/bfin/c_interr_disable.S deleted file mode 100644 index 5a64623..0000000 --- a/sim/testsuite/sim/bfin/c_interr_disable.S +++ /dev/null @@ -1,323 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_interr_disable/c_interr_disable.dsp -// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Include Files -// - -include(std.inc) -include(selfcheck.inc) - -// Defines - -#ifndef TCNTL -#define TCNTL 0xFFE03000 -#endif -#ifndef TPERIOD -#define TPERIOD 0xFFE03004 -#endif -#ifndef TSCALE -#define TSCALE 0xFFE03008 -#endif -#ifndef TCOUNT -#define TCOUNT 0xFFE0300c -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203c -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0x000FF000 -#endif -#ifndef PROGRAM_STACK -#define PROGRAM_STACK 0x000FF100 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000300 -#endif - -// Boot code - - BOOT : -INIT_R_REGS(0); // Initialize Dregs -INIT_P_REGS(0); // Initialize Pregs - - // CHECK_INIT(p5, 0x00BFFFFC); - // CHECK_INIT(p5, 0xE0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - - -LD32(sp, 0x000FF200); -LD32(p0, EVT); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE); // IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE); // IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE); // IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE); // IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE); // IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE); // IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -LD32_LABEL(p1, START); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; -RAISE 15; // after we RTI, INT 15 should be taken - -LD32_LABEL(r7, START); -RETI = r7; -NOP; // Workaround for Bug 217 -RTI; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -DUMMY: - NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - -//.code 0x200 - START : - R7 = 0x0; - R6 = 0x1; - [ -- SP ] = RETI; // Enable Nested Interrupts - -CLI R1; // stop interrupt -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) -WR_MMR(TPERIOD, 0x00000050, p0, r0); -WR_MMR(TCOUNT, 0x00000013, p0, r0); -WR_MMR(TSCALE, 0x00000000, p0, r0); -CSYNC; - // Read the contents of the Timer - -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000050); - -// RD_MMR(TCOUNT, p0, r3); -// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 - - -WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) -CSYNC; - -RD_MMR(TPERIOD, p0, r4); -CHECKREG(r4, 0x00000050); - -// RD_MMR(TCNTL, p0, r5); -// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -NOP; -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power -WR_MMR(TPERIOD, 0x00000015, p0, r0); -WR_MMR(TCOUNT, 0x00000013, p0, r0); -WR_MMR(TSCALE, 0x00000002, p0, r0); -WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) -CSYNC; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -JUMP.S label4; - R4.L = 0x1111; // Will be killed - R4.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -label5: R5.H = 0x7777; - R5.L = 0x7888; -JUMP.S label6; - R5.L = 0x1111; // Will be killed - R5.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -label4: R4.H = 0x5555; - R4.L = 0x6666; -NOP; -JUMP.S label5; - R5.L = 0x2222; // Will be killed - R5.H = 0x2222; // Will be killed -NOP; -NOP; -NOP; -NOP; -label6: R3.H = 0x7999; - R3.L = 0x7aaa; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - // With auto reload - // Read the contents of the Timer - -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000015); - -// RD_MMR(TCNTL , p0, r3); -// CHECKREG(r3, 0x0000000F); -CHECKREG(r7, 0x00000000); // no interrupt being serviced -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -STI R1; -NOP; -CHECKREG(r7, 0x00000001); // interrupt being serviced -// WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -// csync; -NOP; - - - - - -dbg_pass; // Call Endtest Macro - - - -//********************************************************************* -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 - R7 = R7 + R6; -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler - R5 = RETI; - P0 = R5; -JUMP ( P0 ); -RTI; - -.section MEM_DATA_ADDR_1,"aw" - -.space (STACKSIZE); -STACK: -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_interr_disable_enable.S b/sim/testsuite/sim/bfin/c_interr_disable_enable.S deleted file mode 100644 index ac28cdb..0000000 --- a/sim/testsuite/sim/bfin/c_interr_disable_enable.S +++ /dev/null @@ -1,344 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_interr_disable_enable/c_interr_disable_enable.dsp -// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Include Files -// - -include(std.inc) -include(selfcheck.inc) - -// Defines - -#ifndef TCNTL -#define TCNTL 0xFFE03000 -#endif -#ifndef TPERIOD -#define TPERIOD 0xFFE03004 -#endif -#ifndef TSCALE -#define TSCALE 0xFFE03008 -#endif -#ifndef TCOUNT -#define TCOUNT 0xFFE0300c -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203c -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0x000FF000 -#endif -#ifndef PROGRAM_STACK -#define PROGRAM_STACK 0x000FF100 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000300 -#endif - -// Boot code - - BOOT : -INIT_R_REGS(0); // Initialize Dregs -INIT_P_REGS(0); // Initialize Pregs - - // CHECK_INIT(p5, 0x00BFFFFC); - // CHECK_INIT(p5, 0xE0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - - // LD32(sp, 0x000FF200); -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE); // IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE); // IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE); // IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE); // IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE); // IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE); // IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -LD32_LABEL(p1, START); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; -RAISE 15; // after we RTI, INT 15 should be taken - -LD32_LABEL(r7, START); -RETI = r7; -NOP; // Workaround for Bug 217 -RTI; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -DUMMY: - NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - -//.code 0x200 - START : - P1 = 0; - R7 = 0x0; - R6 = 0x1; - [ -- SP ] = RETI; // Enable Nested Interrupts - -CLI R1; // stop interrupt -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) -WR_MMR(TPERIOD, 0x00000050, p0, r0); -WR_MMR(TCOUNT, 0x00000013, p0, r0); -WR_MMR(TSCALE, 0x00000000, p0, r0); -CSYNC; - // Read the contents of the Timer - -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000050); - -// RD_MMR(TCOUNT, p0, r3); -// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 - - -WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) -CSYNC; - -RD_MMR(TPERIOD, p0, r4); -CHECKREG(r4, 0x00000050); - -// RD_MMR(TCNTL, p0, r5); -// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -NOP; -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power -WR_MMR(TPERIOD, 0x00000015, p0, r0); -WR_MMR(TCOUNT, 0x00000013, p0, r0); -WR_MMR(TSCALE, 0x00000002, p0, r0); -WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) -CSYNC; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -JUMP.S label4; - R4.L = 0x1111; // Will be killed - R4.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -label5: R5.H = 0x7777; - R5.L = 0x7888; -JUMP.S label6; - R5.L = 0x1111; // Will be killed - R5.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -label4: R4.H = 0x5555; - R4.L = 0x6666; -NOP; -JUMP.S label5; - R5.L = 0x2222; // Will be killed - R5.H = 0x2222; // Will be killed -NOP; -NOP; -NOP; -NOP; -label6: R3.H = 0x7999; - R3.L = 0x7aaa; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - // With auto reload - // Read the contents of the Timer - -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000015); - -// RD_MMR(TCNTL , p0, r3); -// CHECKREG(r3, 0x0000000F); -CHECKREG(r7, 0x00000000); // no interrupt being serviced -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -STI R1; -NOP; -CHECKREG(r7, 0x00000001); // interrupt being serviced -WR_MMR(TCOUNT, 0x00000005, p0, r0); -WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) -CSYNC; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -CHECKREG(r7, 0x00000002); // interrupt being serviced -RAISE 7; -NOP; NOP; -CHECKREG(p1, 0x00000001); // interrupt being serviced - - - - - -dbg_pass; // Call Endtest Macro - - - -//********************************************************************* -// -// Handlers for Events -// -//.code ITABLE - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 - R7 = R7 + R6; -RTI; - -I7HANDLE: // IVG 7 Handler - P1 += 1; -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler - R5 = RETI; - P0 = R5; -JUMP ( P0 ); -RTI; - -.data - -.space (STACKSIZE); -KSTACK: -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_interr_excpt.S b/sim/testsuite/sim/bfin/c_interr_excpt.S deleted file mode 100644 index 911a78e..0000000 --- a/sim/testsuite/sim/bfin/c_interr_excpt.S +++ /dev/null @@ -1,290 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_interr_excpt/c_interr_excpt.dsp -// Spec Reference: interr excpt -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: - - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! - // Can't Raise 0, 3, or 4 - // Raise 1 requires some intelligence so the test - // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) - - R0 = 1; - R1 = 2; - R2 = 3; - R3 = 4; - - -EXCPT 1; // RTX -EXCPT 2; // RTX -EXCPT 3; // RTX -EXCPT 4; // RTX -EXCPT 5; // RTX -EXCPT 5; // RTX -EXCPT 6; // RTX -EXCPT 7; // RTX -EXCPT 8; // RTX -EXCPT 9; // RTX -EXCPT 10; // RTX -EXCPT 11; // RTX -EXCPT 12; // RTX -EXCPT 13; // RTX -EXCPT 14; // RTX -EXCPT 15; // RTX - -CHECKREG(r0, 0x33333333); -CHECKREG(r1, 0xCCCCCCCD); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x33333333); -CHECKREG(r4, 0x00000000); -CHECKREG(r5, 0x00000000); -CHECKREG(r6, 0x00000000); -CHECKREG(r7, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = 2; -RTN; - -XHANDLE: // Exception Handler 3 - R0 = R1 + R2; - R1 = R2 + R3; - R2 = R0 + R1; - R3 = R0 + R2; -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = 5; -RTI; - -THANDLE: // Timer Handler 6 - R3 = 6; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = 7; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = 8; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = 9; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -//.data 0xF0000000 -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_interr_loopsetup_stld.S b/sim/testsuite/sim/bfin/c_interr_loopsetup_stld.S deleted file mode 100644 index 824b53e..0000000 --- a/sim/testsuite/sim/bfin/c_interr_loopsetup_stld.S +++ /dev/null @@ -1,224 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_interr_loopsetup_stld/c_interr_loopsetup_stld.dsp -// Spec Reference: interrupt loopsetup_ldst -# mach: bfin - -#include "test.h" -.include "testutils.inc" -start - - A0 = 0; // reset accumulators - A1 = 0; - -P1 = 3; -P2 = 4; - -LD32(r0, 0x00200005); -LD32(r1, 0x00300010); -LD32(r2, 0x00500012); -LD32(r3, 0x00600024); -LD32(r4, 0x00700016); -LD32(r5, 0x00900028); -LD32(r6, 0x0a000030); -LD32(r7, 0x00b00044); - -loadsym I0, DATA0; -loadsym I1, DATA1; -R0 = [ I0 ++ ]; -R1 = [ I1 ++ ]; -LSETUP ( start1 , end1 ) LC0 = P1; -start1: R0 += 1; - R1 += 2; - A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; // dsp32mac dual - // a1 += h*h, a0 += l*l (r0,r1) ; r0 = [i0++]; r1 = [i1++]; // dsp32mac - R2 = ( R2 + R5 ) << 1; // alu2op -DIVQ ( R5 , R3 ); - R1 <<= R5; - R1 >>>= R1; - R6 = ~ R0; - //MY_GEN_INT(10, 1) -DIVQ ( R5 , R2 ); - R0 = R3.B (X); -DIVS ( R7 , R0 ); -end1: R2 += 3; - R3 = ( A0 += A1 ); -CHECKREG(r0, 0x00000024); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x0670098D); -CHECKREG(r3, 0x000015EC); -CHECKREG(r4, 0x00700016); -CHECKREG(r5, 0x0B240A39); -CHECKREG(r6, 0xFFF2FFFC); -CHECKREG(r7, 0x05800220); - -A0 = 0; -A1 = 0; -LSETUP ( start2 , end2 ) LC0 = P2; -start2: R4 += 4; - //a1 += h*h, a0 += l*l (r0,r1), r0 = [i0--], r1 = [i1--]; - A1 += R0.H * R1.H, A0 += R0.L * R1.L; R0 = [ I0 -- ]; R1 = [ I1 -- ]; - R1 <<= R5; - R6 = R7.B (Z); - R2 = - R6; - R3 = R4.L (Z); -DIVS ( R1 , R1 ); - R6 = - R0; - R0 >>= R0; -DIVS ( R4 , R7 ); - //MY_GEN_INT(13, 1) - R1 = R2.L (Z); -end2: R5 += -5; - R6 = ( A0 += A1 ); -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x0000FFE0); -CHECKREG(r2, 0xFFFFFFE0); -CHECKREG(r3, 0x000000EC); -CHECKREG(r4, 0x070001D8); -CHECKREG(r5, 0x0B240A25); -CHECKREG(r6, 0x00000000); -CHECKREG(r7, 0x05800220); -LD32(r0, 0x01200805); -LD32(r1, 0x02300710); -LD32(r2, 0x03500612); -LD32(r3, 0x04600524); -LD32(r4, 0x05700416); -LD32(r5, 0x06900328); -LD32(r6, 0x0a700230); -LD32(r7, 0x08b00044); - -loadsym I2, DATA0; -loadsym I3, DATA1; -[ I2 ++ ] = R0; -[ I3 ++ ] = R1; -LSETUP ( start3 , end3 ) LC0 = P1; -start3: - [ I2 ++ ] = R2; - [ I3 ++ ] = R3; - R2 += 1; -end3: - R3 += 1; - -A0 = 0; -A1 = 0; -LSETUP ( start4 , end4 ) LC0 = P2; -R0 = [ I0 -- ]; -R1 = [ I1 -- ]; -start4: - // a1 += h*h, a0 += l*l (r0,r1), r0 = [i2--], r1 = [i3--]; - A1 += R0.H * R1.H, A0 += R0.L * R1.L; R0 = [ I2 -- ]; R1 = [ I3 -- ]; - R4 = R4 + R0; // comp3op - R5 = R7.L (Z); - R4 >>>= R5; - R0 = R7.B (X); -DIVQ ( R6 , R6 ); - //MY_GEN_INT(7, 1) -end4: R5 = R5 + R1; - R6 = ( A0 += A1 ); - R7 = ( A0 += A1 ); -CHECKREG(r0, 0x00000044); -CHECKREG(r1, 0x04600524); -CHECKREG(r2, 0x03500615); -CHECKREG(r3, 0x04600527); -CHECKREG(r4, 0x00000000); -CHECKREG(r5, 0x04600568); -CHECKREG(r6, 0x007C3498); -CHECKREG(r7, 0x00812098); - - -pass; // End the test - -// -// Data Segment -// - - - -.data - -DATA0: -.dd 0x000a0000 -.dd 0x000b0001 -.dd 0x000c0002 -.dd 0x000d0003 -.dd 0x000e0004 -.dd 0x000f0005 -.dd 0x00100006 -.dd 0x00200007 -.dd 0x00300008 -.dd 0x00400009 -.dd 0x0050000a -.dd 0x0060000b -.dd 0x0070000c -.dd 0x0080000d -.dd 0x0090000e -.dd 0x0100000f -.dd 0x02000010 -.dd 0x03000011 -.dd 0x04000012 -.dd 0x05000013 -.dd 0x06000014 -.dd 0x001a0000 -.dd 0x001b0001 -.dd 0x001c0002 -.dd 0x001d0003 -.dd 0x00010004 -.dd 0x00010005 -.dd 0x02100006 -.dd 0x02200007 -.dd 0x02300008 -.dd 0x02200009 -.dd 0x0250000a -.dd 0x0260000b -.dd 0x0270000c -.dd 0x0280000d -.dd 0x0290000e -.dd 0x2100000f -.dd 0x22000010 -.dd 0x22000011 -.dd 0x24000012 -.dd 0x25000013 -.dd 0x26000014 - -DATA1: -.dd 0x00f00100 -.dd 0x00e00101 -.dd 0x00d00102 -.dd 0x00c00103 -.dd 0x00b00104 -.dd 0x00a00105 -.dd 0x00900106 -.dd 0x00800107 -.dd 0x00100108 -.dd 0x00200109 -.dd 0x0030010a -.dd 0x0040010b -.dd 0x0050011c -.dd 0x0060010d -.dd 0x0070010e -.dd 0x0080010f -.dd 0x00900110 -.dd 0x01000111 -.dd 0x02000112 -.dd 0x03000113 -.dd 0x04000114 -.dd 0x05000115 -.dd 0x03f00100 -.dd 0x03e00101 -.dd 0x03d00102 -.dd 0x03c00103 -.dd 0x03b00104 -.dd 0x03a00105 -.dd 0x03900106 -.dd 0x03800107 -.dd 0x03100108 -.dd 0x03200109 -.dd 0x0330010a -.dd 0x0330010b -.dd 0x0350011c -.dd 0x0360010d -.dd 0x0370010e -.dd 0x0380010f -.dd 0x03900110 -.dd 0x31000111 -.dd 0x32000112 -.dd 0x33000113 -.dd 0x34000114 diff --git a/sim/testsuite/sim/bfin/c_interr_nested.S b/sim/testsuite/sim/bfin/c_interr_nested.S deleted file mode 100644 index 55af970..0000000 --- a/sim/testsuite/sim/bfin/c_interr_nested.S +++ /dev/null @@ -1,289 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_interr_nested/c_interr_nested.dsp -// Spec Reference: interrupt nested using raises -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: - - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! - // Can't Raise 0, 3, or 4 - // Raise 1 requires some intelligence so the test - // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) -RAISE 2; // RTN -// RAISE 5; // RTI -RAISE 6; // RTI -RAISE 7; // RTI -// RAISE 8; // RTI -RAISE 9; // RTI -RAISE 10; // RTI -RAISE 11; // RTI -// RAISE 12; // RTI -RAISE 13; // RTI -RAISE 14; // RTI -RAISE 15; // RTI - -CHECKREG(r0, 0x0000000B); -CHECKREG(r1, 0x0000000C); -CHECKREG(r2, 0x0000000D); -CHECKREG(r3, 0x0000000E); -CHECKREG(r4, 0x00000007); -CHECKREG(r5, 0x00000008); -CHECKREG(r6, 0x00000009); -CHECKREG(r7, 0x0000000A); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -CHECKREG(r0, 0x00000002); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000005); -CHECKREG(r3, 0x00000006); -CHECKREG(r4, 0x00000007); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = 5; -RTI; - -THANDLE: // Timer Handler 6 - R3 = 6; -RAISE 5; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = 7; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = 8; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = 9; -RAISE 8; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RAISE 12; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_interr_nmi.S b/sim/testsuite/sim/bfin/c_interr_nmi.S deleted file mode 100644 index 5124494..0000000 --- a/sim/testsuite/sim/bfin/c_interr_nmi.S +++ /dev/null @@ -1,318 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_interr_nmi/c_interr_nmi.dsp -// Spec Reference: progctrl raise rti rtn -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: - - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; -RAISE 15; // after we RTI, INT 15 should be taken - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! - // Can't Raise 0, 3, or 4 - // Raise 1 requires some intelligence so the test - // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) -R0 = 0; -R1 = 0; -R2 = 0; -R3 = 0; -R4 = 0; -R5 = 0; -R6 = 0; -R7 = 0; - -RAISE 2; // RTN -RAISE 5; // RTI -RAISE 6; // RTI -RAISE 7; // RTI -RAISE 8; // RTI -RAISE 9; // RTI -RAISE 10; // RTI -RAISE 11; // RTI -RAISE 12; // RTI -RAISE 13; // RTI -RAISE 14; // RTI -RAISE 15; // RTI - -CHECKREG(r0, 0x0000000B); -CHECKREG(r1, 0x0000001A); -CHECKREG(r2, 0x00000024); -CHECKREG(r3, 0x00000028); -CHECKREG(r4, 0x0000000E); -CHECKREG(r5, 0x00000010); -CHECKREG(r6, 0x00000012); -CHECKREG(r7, 0x00000014); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -CHECKREG(r0, 0x0000000B); -CHECKREG(r1, 0x0000000E); -CHECKREG(r2, 0x00000017); -CHECKREG(r3, 0x0000001A); -CHECKREG(r4, 0x0000000E); - -( R7:0 ) = [ SP ++ ]; // pop - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x00000000); -CHECKREG(r4, 0x00000000); -CHECKREG(r5, 0x00000000); -CHECKREG(r6, 0x00000000); -CHECKREG(r7, 0x00000000); -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 += 1; - R1 += 2; -RAISE 5; // RTI -RAISE 6; // RTI -RAISE 7; // RTI -RAISE 8; // RTI -RAISE 9; // RTI -RAISE 10; // RTI -RAISE 11; // RTI -RAISE 12; // RTI -RAISE 13; // RTI -RAISE 14; // RTI -RAISE 15; // RTI - [ -- SP ] = ( R7:0 ); // push -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 += 5; -RTI; - -THANDLE: // Timer Handler 6 - R3 += 6; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 += 7; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 += 8; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 += 9; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 += 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 += 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 += 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 += 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 += 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_interr_pending.S b/sim/testsuite/sim/bfin/c_interr_pending.S deleted file mode 100644 index 96b5a96..0000000 --- a/sim/testsuite/sim/bfin/c_interr_pending.S +++ /dev/null @@ -1,324 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_interr_pending/c_interr_pending.dsp -// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Include Files -// - -include(std.inc) -include(selfcheck.inc) - -// Defines - -#ifndef TCNTL -#define TCNTL 0xFFE03000 -#endif -#ifndef TPERIOD -#define TPERIOD 0xFFE03004 -#endif -#ifndef TSCALE -#define TSCALE 0xFFE03008 -#endif -#ifndef TCOUNT -#define TCOUNT 0xFFE0300c -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203c -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0x000FF000 -#endif -#ifndef PROGRAM_STACK -#define PROGRAM_STACK 0x000FF100 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000300 -#endif - -// Boot code - - BOOT : -INIT_R_REGS(0); // Initialize Dregs -INIT_P_REGS(0); // Initialize Pregs - - // CHECK_INIT(p5, 0x00BFFFFC); - // CHECK_INIT(p5, 0xE0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -LD32(sp, 0x000FF200); -LD32(p0, EVT); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE); // IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE); // IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE); // IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE); // IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE); // IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE); // IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -LD32_LABEL(p1, START); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; -RAISE 15; // after we RTI, INT 15 should be taken - -LD32_LABEL(r7, START); -RETI = r7; -NOP; // Workaround for Bug 217 -RTI; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -DUMMY: - NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - -//.code 0x200 - START : - P1 = 0x0; - R7 = 0x0; - R6 = 0x1; - [ -- SP ] = RETI; // Enable Nested Interrupts - -CLI R1; // stop interrupt -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) -WR_MMR(TPERIOD, 0x00000050, p0, r0); -WR_MMR(TCOUNT, 0x00000013, p0, r0); -WR_MMR(TSCALE, 0x00000000, p0, r0); -CSYNC; - // Read the contents of the Timer - -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000050); - -// RD_MMR(TCOUNT, p0, r3); -// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 - - -WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) -CSYNC; - -RD_MMR(TPERIOD, p0, r4); -CHECKREG(r4, 0x00000050); - -// RD_MMR(TCNTL, p0, r5); -// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -NOP; -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power -WR_MMR(TPERIOD, 0x00000015, p0, r0); -WR_MMR(TCOUNT, 0x00000013, p0, r0); -WR_MMR(TSCALE, 0x00000002, p0, r0); -WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) -CSYNC; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -JUMP.S label4; - R4.L = 0x1111; // Will be killed - R4.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -label5: R5.H = 0x7777; - R5.L = 0x7888; -JUMP.S label6; - R5.L = 0x1111; // Will be killed - R5.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -label4: R4.H = 0x5555; - R4.L = 0x6666; -NOP; -JUMP.S label5; - R5.L = 0x2222; // Will be killed - R5.H = 0x2222; // Will be killed -NOP; -NOP; -NOP; -NOP; -label6: R3.H = 0x7999; - R3.L = 0x7aaa; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - // With auto reload - // Read the contents of the Timer -RAISE 7; -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000015); - -CHECKREG(p1, 0x00000000); // no interrupt being serviced -CHECKREG(r7, 0x00000000); // no interrupt being serviced -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -STI R1; -NOP; NOP; NOP; -CHECKREG(r7, 0x00000001); // interrupt being serviced -CHECKREG(p1, 0x00000001); // interrupt being serviced -NOP; - - - - - -dbg_pass; // Call Endtest Macro - - - -//********************************************************************* -// -// Handlers for Events -// -//.code ITABLE - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 - R7 = R7 + R6; -RTI; - -I7HANDLE: // IVG 7 Handler - P1 += 1; - -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler - R5 = RETI; - P0 = R5; -JUMP ( P0 ); -RTI; - -.section MEM_DATA_ADDR_1,"aw" - -.space (STACKSIZE); -STACK: -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_interr_pending_2.S b/sim/testsuite/sim/bfin/c_interr_pending_2.S deleted file mode 100644 index 2f1cf6c..0000000 --- a/sim/testsuite/sim/bfin/c_interr_pending_2.S +++ /dev/null @@ -1,268 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_interr_pending_2/c_interr_pending_2.dsp -// Spec Reference: interr pending (raise) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -// - -////MY_GEN_INT_INIT(0x000f0000) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - //CHECK_INIT(p5, 0x00002000); -include(symtable.inc) -CHECK_INIT_DEF(p0); - - -LD32(r0, 0x8b235625); -LD32(r1, 0x93ba5127); -LD32(r2, 0xa3446725); -LD32(r3, 0x00050027); -LD32(r4, 0xb0ab6d29); -LD32(r5, 0x10ace72b); -LD32(r6, 0xc00c008d); -LD32(r7, 0xd2467029); -R4.H = R0.L * R1.L, R4.L = R0.L * R1.L; -CLI R0; -R5.H = R2.H * R3.L, R5.L = R2.L * R3.H; -RAISE 8; -RAISE 9; -CHECKREG(r4, 0x369E369E); -CHECKREG(r5, 0xFFE40004); -SSYNC; -STI R0; -R6.H = R1.L * R2.L, R6.L = R1.H * R2.L; -R7.H = R1.L * R3.H, R7.L = R1.H * R3.H; - -CHECKREG(r4, 0x369E369F); -CHECKREG(r5, 0xFFE40005); -CHECKREG(r6, 0x4165A8C0); -CHECKREG(r7, 0x0003FFFC); - - - -END: -dbg_pass; // End the test - -//********************************************************************* -// -// Handlers for Events -// -//.code 0x000f0000 - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler - R4 += 1; -RTI; - -I9HANDLE: // IVG 9 Handler - R5 += 1; -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" - -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_interr_timer.S b/sim/testsuite/sim/bfin/c_interr_timer.S deleted file mode 100644 index 181213e..0000000 --- a/sim/testsuite/sim/bfin/c_interr_timer.S +++ /dev/null @@ -1,384 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_interr_timer/c_interr_timer.dsp -// Spec Reference: interrupt on HW TIMER -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Include Files -// - -include(std.inc) -include(selfcheck.inc) - -// Defines - -#ifndef TCNTL -#define TCNTL 0xFFE03000 -#endif -#ifndef TPERIOD -#define TPERIOD 0xFFE03004 -#endif -#ifndef TSCALE -#define TSCALE 0xFFE03008 -#endif -#ifndef TCOUNT -#define TCOUNT 0xFFE0300c -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203c -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0x000FF000 -#endif -#ifndef PROGRAM_STACK -#define PROGRAM_STACK 0x000FF100 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000300 -#endif - -// Boot code - - BOOT : -INIT_R_REGS(0); // Initialize Dregs -INIT_P_REGS(0); // Initialize Pregs - - // CHECK_INIT(p5, 0xE0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - - -LD32(sp, 0x000FF200); -LD32(p0, EVT); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE); // IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE); // IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE); // IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE); // IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE); // IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE); // IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -LD32_LABEL(p1, START); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; -RAISE 15; // after we RTI, INT 15 should be taken - -LD32_LABEL(r7, START); -RETI = r7; -NOP; // Workaround for Bug 217 -RTI; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -DUMMY: - NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - -//.code 0x200 - START : - R7 = 0x0; - R6 = 0x1; - [ -- SP ] = RETI; // Enable Nested Interrupts - -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR(0) (active state) -WR_MMR(TPERIOD, 0x00000050, p0, r0); - // WR_MMR(TCOUNT, 0x00000013, p0, r0); -WR_MMR(TCOUNT, 0x00000000, p0, r0); -WR_MMR(TSCALE, 0x00000000, p0, r0); -CSYNC; - // Read the contents of the Timer - -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000050); - - -WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR(0), TMREN(1)) -CSYNC; // TIMER interrupt - -RD_MMR(TCOUNT, p0, r3); -CSYNC; -CHECKREG(r3, 0x00000000); -CHECKREG(r7, 0x00000001); -WR_MMR(TCNTL, 0x00000001, p0, r0); // enable Timer (TMPWR(0), TMREN(1)=0) -WR_MMR(TCOUNT, 0x00000013, p0, r0); -WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR(0), TMREN(1)) -CSYNC; -NOP; NOP; NOP; -NOP; NOP; NOP; -NOP; NOP; NOP; -NOP; NOP; NOP; -NOP; NOP; NOP; -NOP; NOP; NOP; -NOP; NOP; NOP; -NOP; NOP; NOP; -RD_MMR(TCOUNT, p0, r4); -CHECKREG(r4, 0x00000000); - -RD_MMR(TCNTL, p0, r5); -CHECKREG(r5, 0x0000000B); - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -NOP; -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power -WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Power, EN -> interr -CSYNC; -CHECKREG(r7, 0x00000003); // 3 interr already happened - R7 = 0; // reset r7 -WR_MMR(TPERIOD, 0x00000040, p0, r0); -WR_MMR(TCOUNT, 0x00000013, p0, r0); -WR_MMR(TSCALE, 0x00000002, p0, r0); -WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auto load -CSYNC; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -JUMP.S label4; - R4.L = 0x1111; // Will be killed - R4.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -label5: R5.H = 0x7777; - R5.L = 0x7888; -JUMP.S label6; - R5.L = 0x1111; // Will be killed - R5.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -label4: R4.H = 0x5555; - R4.L = 0x6666; -NOP; -JUMP.S label5; - R5.L = 0x2222; // Will be killed - R5.H = 0x2222; // Will be killed -NOP; -NOP; -NOP; -NOP; -label6: R3.H = 0x7999; - R3.L = 0x7aaa; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - // With auto reload - // Read the contents of the Timer - -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000040); - -// CHECKREG(r7, 0x00000002); -CC = R7 == 0; -IF !CC JUMP LABEL1; -WR_MMR(TPERIOD, 0x00000030, p0, r0); // SHOULD NOT EXECUTE - -LABEL1: - -NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; - - -RD_MMR(TCNTL , p0, r3); -CHECKREG(r3, 0x0000000F); - - -WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer -CSYNC; -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000040); - - -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; -RD_MMR(TCOUNT, p0, r4); -CHECKREG(r4, 0x00000000); - -RD_MMR(TCNTL, p0, r5); -CHECKREG(r5, 0x0000000B); - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -NOP; NOP; NOP; - -WR_MMR(TPERIOD, 0x00000060, p0, r0); -CSYNC; -NOP; -RD_MMR(TPERIOD, p0, r6); -CHECKREG(r6, 0x00000060); - - - - -dbg_pass; // Call Endtest Macro - - - -//********************************************************************* -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 - R7 = R7 + R6; -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler - R5 = RETI; - P0 = R5; -JUMP ( P0 ); -RTI; - -.section MEM_DATA_ADDR_1,"aw" - -.space (STACKSIZE); -STACK: -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_interr_timer_reload.S b/sim/testsuite/sim/bfin/c_interr_timer_reload.S deleted file mode 100644 index d84e5f5..0000000 --- a/sim/testsuite/sim/bfin/c_interr_timer_reload.S +++ /dev/null @@ -1,286 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_interr_timer_reload/c_interr_timer_reload.dsp -// Spec Reference: interrupt on HW TIMER auto-reload -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Include Files -// - -include(std.inc) -include(selfcheck.inc) - -// Defines - -#ifndef TCNTL -#define TCNTL 0xFFE03000 -#endif -#ifndef TPERIOD -#define TPERIOD 0xFFE03004 -#endif -#ifndef TSCALE -#define TSCALE 0xFFE03008 -#endif -#ifndef TCOUNT -#define TCOUNT 0xFFE0300c -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203c -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0x000FF000 -#endif -#ifndef PROGRAM_STACK -#define PROGRAM_STACK 0x000FF100 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000300 -#endif - -// Boot code - - BOOT : -INIT_R_REGS(0); // Initialize Dregs -INIT_P_REGS(0); // Initialize Pregs - - // CHECK_INIT(p5, 0x00BFFFFC); - // CHECK_INIT(p5, 0xE0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - - -LD32(sp, 0x000FF200); -LD32(p0, EVT); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE); // IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE); // IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE); // IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE); // IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE); // IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE); // IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -LD32_LABEL(p1, START); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; - -RAISE 15; // after we RTI, INT 15 should be taken - -LD32_LABEL(r7, START); -RETI = r7; -NOP; // Workaround for Bug 217 -RTI; -NOP; -NOP; - -//.code 0x200 - START : - R7 = 0x0; - R6 = 0x1; - [ -- SP ] = RETI; // Enable Nested Interrupts - -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) -WR_MMR(TPERIOD, 0x00000020, p0, r0); -WR_MMR(TCOUNT, 0x00000002, p0, r0); -WR_MMR(TSCALE, 0x00000005, p0, r0); -CSYNC; - // Read the contents of the Timer - -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000020); - -RD_MMR(TCOUNT, p0, r3); -CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace - - -WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) -CSYNC; - - - -NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; - -RD_MMR(TCOUNT, p0, r4); -CHECKREG(r4, 0x00000000); - -RD_MMR(TCNTL, p0, r5); -CHECKREG(r5, 0x0000000B); - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -CHECKREG(r7, 0x00000001); - R7 = 0; -NOP; -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power -WR_MMR(TPERIOD, 0x00000020, p0, r0); -WR_MMR(TCOUNT, 0x00000003, p0, r0); -WR_MMR(TSCALE, 0x00000002, p0, r0); -WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auo-reload -CSYNC; -NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; - // With auto reload - // Read the contents of the Timer - -// CHECKREG(r7, 0x00000002); -CC = R7 == 0; -IF !CC JUMP LABEL1; -WR_MMR(TPERIOD, 0x00000030, p0, r0); // SHOULD NOT EXECUTE - -LABEL1: - - -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000020); - -RD_MMR(TCNTL , p0, r3); -CHECKREG(r3, 0x0000000F); - -WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer but not auto-reload -CSYNC; - -NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; -RD_MMR(TCOUNT, p0, r4); -CHECKREG(r4, 0x00000000); - -RD_MMR(TCNTL, p0, r5); -CHECKREG(r5, 0x0000000B); - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -NOP; NOP; NOP; - - - - - -dbg_pass; // Call Endtest Macro - - - -//********************************************************************* -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 - R7 = R7 + R6; -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler - R5 = RETI; - P0 = R5; -JUMP ( P0 ); -RTI; - -.section MEM_DATA_ADDR_1,"aw" - -.space (STACKSIZE); -STACK: -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_interr_timer_tcount.S b/sim/testsuite/sim/bfin/c_interr_timer_tcount.S deleted file mode 100644 index cc8fddc..0000000 --- a/sim/testsuite/sim/bfin/c_interr_timer_tcount.S +++ /dev/null @@ -1,242 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_interr_timer_tcount/c_interr_timer_tcount.dsp -// Spec Reference: interrupt on HW TIMER tcount -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Include Files -// - -include(std.inc) -include(selfcheck.inc) - -// Defines - -#ifndef TCNTL -#define TCNTL 0xFFE03000 -#endif -#ifndef TPERIOD -#define TPERIOD 0xFFE03004 -#endif -#ifndef TSCALE -#define TSCALE 0xFFE03008 -#endif -#ifndef TCOUNT -#define TCOUNT 0xFFE0300c -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203c -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0x000FF000 -#endif -#ifndef PROGRAM_STACK -#define PROGRAM_STACK 0x000FF100 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000300 -#endif - -// Boot code - - BOOT : -INIT_R_REGS(0); // Initialize Dregs -INIT_P_REGS(0); // Initialize Pregs - - // CHECK_INIT(p5, 0x00BFFFFC); - // CHECK_INIT(p5, 0xE0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - - -LD32(sp, 0x000FF200); -LD32(p0, EVT); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE); // IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE); // IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE); // IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE); // IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE); // IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE); // IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -LD32_LABEL(p1, START); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; - -RAISE 15; // after we RTI, INT 15 should be taken - -LD32_LABEL(r7, START); -RETI = r7; -NOP; // Workaround for Bug 217 -RTI; -NOP; -NOP; - -//.code 0x200 - START : - R7 = 0x0; - R6 = 0x1; - [ -- SP ] = RETI; // Enable Nested Interrupts - -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) -WR_MMR(TPERIOD, 0x00000010, p0, r0); -WR_MMR(TCOUNT, 0x00000002, p0, r0); -WR_MMR(TSCALE, 0x00000001, p0, r0); -WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) -CSYNC; - - -RD_MMR(TCNTL, p0, r5); -CHECKREG(r5, 0x0000000B); - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -CHECKREG(r7, 0x00000001); - R7 = 0; -NOP; -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power -WR_MMR(TPERIOD, 0x00000010, p0, r0); -WR_MMR(TCOUNT, 0x00000002, p0, r0); -WR_MMR(TSCALE, 0x00000003, p0, r0); -WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer -CSYNC; -NOP; -NOP; - // Read the contents of the Timer - - -RD_MMR(TCNTL , p0, r3); -CHECKREG(r3, 0x0000000B); - -CHECKREG(r7, 0x00000001); - - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -NOP; NOP; NOP; - - - - - -dbg_pass; // Call Endtest Macro - - - -//********************************************************************* -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 - R7 = R7 + R6; -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler - R5 = RETI; - P0 = R5; -JUMP ( P0 ); -RTI; - -.section MEM_DATA_ADDR_1,"aw" - -.space (STACKSIZE); -STACK: -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_interr_timer_tscale.S b/sim/testsuite/sim/bfin/c_interr_timer_tscale.S deleted file mode 100644 index f8a87ac..0000000 --- a/sim/testsuite/sim/bfin/c_interr_timer_tscale.S +++ /dev/null @@ -1,304 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_interr_timer_tscale/c_interr_timer_tscale.dsp -// Spec Reference: interrupt on HW TIMER tscale -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Include Files -// - -include(std.inc) -include(selfcheck.inc) - -// Defines - -#ifndef TCNTL -#define TCNTL 0xFFE03000 -#endif -#ifndef TPERIOD -#define TPERIOD 0xFFE03004 -#endif -#ifndef TSCALE -#define TSCALE 0xFFE03008 -#endif -#ifndef TCOUNT -#define TCOUNT 0xFFE0300c -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203c -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0x000FF000 -#endif -#ifndef PROGRAM_STACK -#define PROGRAM_STACK 0x000FF100 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000300 -#endif - -// Boot code - - BOOT : -INIT_R_REGS(0); // Initialize Dregs -INIT_P_REGS(0); // Initialize Pregs - - // CHECK_INIT(p5, 0x00BFFFFC); - // CHECK_INIT(p5, 0xE0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - - -LD32(sp, 0x000FF200); -LD32(p0, EVT); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE); // IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE); // IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE); // IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE); // IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE); // IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE); // IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -LD32_LABEL(p1, START); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; -RAISE 15; // after we RTI, INT 15 should be taken - -LD32_LABEL(r7, START); -RETI = r7; -NOP; // Workaround for Bug 217 -RTI; -NOP; -NOP; - -//.code 0x200 - START : - R7 = 0x0; - R6 = 0x1; - [ -- SP ] = RETI; // Enable Nested Interrupts - -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) -WR_MMR(TPERIOD, 0x00000010, p0, r0); -WR_MMR(TCOUNT, 0x00000002, p0, r0); -WR_MMR(TSCALE, 0x00000001, p0, r0); -CSYNC; - // Read the contents of the Timer -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000010); - -RD_MMR(TCOUNT, p0, r3); -CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace -seed 8b8db910 - - -WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) -CSYNC; - -RD_MMR(TCOUNT, p0, r4); -CHECKREG(r4, 0x00000000); - -RD_MMR(TCNTL, p0, r5); -CHECKREG(r5, 0x0000000B); - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -CHECKREG(r7, 0x00000001); - R7 = 0; -NOP; -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power -WR_MMR(TPERIOD, 0x00000010, p0, r0); -WR_MMR(TCOUNT, 0x00000003, p0, r0); -WR_MMR(TSCALE, 0x00000128, p0, r0); -WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer -CSYNC; -NOP; -NOP; -label5: R5.H = 0x7777; - R5.L = 0x7888; -JUMP.S label6; - R5.L = 0x1111; // Will be killed - R5.H = 0x1111; // Will be killed -NOP; -label4: R4.H = 0x5555; - R4.L = 0x6666; -NOP; -JUMP.S label5; - R5.L = 0x2222; // Will be killed - R5.H = 0x2222; // Will be killed -NOP; -label6: R3.H = 0x7999; - R3.L = 0x7aaa; -NOP; - // With auto reload - // Read the contents of the Timer - -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000010); - -RD_MMR(TCNTL , p0, r3); -CHECKREG(r3, 0x0000000b); - -CHECKREG(r7, 0x00000001); - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn ON Timer auto-reload -WR_MMR(TPERIOD, 0x00000020, p0, r0); -WR_MMR(TSCALE, 0x00000003, p0, r0); -WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auto-reload - -NOP; NOP; - R7 = 0; -CSYNC; - -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; -NOP; NOP; NOP; NOP; NOP; NOP; - R1 = 1; - R2 = 1; - R3 = 2; -RD_MMR(TCNTL, p0, r5); -CHECKREG(r5, 0x0000000F); -CC = R1 < R7; -IF CC R2 = R3; - -CHECKREG(r2, 0x00000002); - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -NOP; NOP; NOP; - - - - - -dbg_pass; // Call Endtest Macro - - - -//********************************************************************* -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 - R7 = R7 + R6; -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler - R5 = RETI; - P0 = R5; -JUMP ( P0 ); -RTI; - -.section MEM_DATA_ADDR_1,"aw" - -.space (STACKSIZE); -STACK: -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_dreg.s b/sim/testsuite/sim/bfin/c_ldimmhalf_dreg.s deleted file mode 100644 index b39e4e1..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_dreg.s +++ /dev/null @@ -1,60 +0,0 @@ -//Original:/testcases/core/c_ldimmhalf_dreg/c_ldimmhalf_dreg.dsp -// Spec Reference: ldimmhalf dreg imm16 -# mach: bfin - -.include "testutils.inc" - start - - - -INIT_R_REGS -1; - -// test Dreg -R0 = 0x0123 (X); -R1 = 0x1234 (X); -R2 = 0x2345 (X); -R3 = 0x3456 (X); -R4 = 0x4567 (X); -R5 = 0x5678 (X); -R6 = 0x6789 (X); -R7 = 0x789a (X); -CHECKREG r0, 0x00000123; -CHECKREG r1, 0x00001234; -CHECKREG r2, 0x00002345; -CHECKREG r3, 0x00003456; -CHECKREG r4, 0x00004567; -CHECKREG r5, 0x00005678; -CHECKREG r6, 0x00006789; -CHECKREG r7, 0x0000789A; - -R0 = -32768 (X); -R1 = -1111 (X); -R2 = -2222 (X); -R3 = -3333 (X); -R4 = -4444 (X); -R5 = -5555 (X); -R6 = -6666 (X); -R7 = -7777 (X); -CHECKREG r0, 0xFFFF8000; -CHECKREG r1, 0xFFFFFBA9; -CHECKREG r2, 0xFFFFF752; -CHECKREG r3, 0xFFFFF2FB; -CHECKREG r4, 0xFFFFEEA4; -CHECKREG r5, 0xFFFFEA4D; -CHECKREG r6, 0xFFFFE5F6; -CHECKREG r7, 0xFFFFE19F; - -R0 = 0x7fff (X); -R1 = 0x7ffe (X); -R2 = 32767 (X); -R3 = 32766 (X); -R4 = -32768 (X); -R5 = -32767 (X); -CHECKREG r0, 0x00007fff; -CHECKREG r1, 0x00007ffe; -CHECKREG r2, 0x00007fff; -CHECKREG r3, 0x00007ffe; -CHECKREG r4, 0xFFFF8000; -CHECKREG r5, 0xFFFF8001; - -pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s b/sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s deleted file mode 100644 index 3b7194a..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s +++ /dev/null @@ -1,85 +0,0 @@ -//Original:/testcases/core/c_ldimmhalf_drhi/c_ldimmhalf_drhi.dsp -// Spec Reference: ldimmhalf dreg hi -# mach: bfin - -.include "testutils.inc" - start - - - -INIT_R_REGS -1; - -// test Dreg -R0.H = 0x0001; -R1.H = 0x0003; -R2.H = 0x0005; -R3.H = 0x0007; -R4.H = 0x0009; -R5.H = 0x000b; -R6.H = 0x000d; -R7.H = 0x000f; -CHECKREG r0, 0x0001FFFF; -CHECKREG r1, 0x0003FFFF; -CHECKREG r2, 0x0005FFFF; -CHECKREG r3, 0x0007FFFF; -CHECKREG r4, 0x0009FFFF; -CHECKREG r5, 0x000bFFFF; -CHECKREG r6, 0x000dFFFF; -CHECKREG r7, 0x000fFFFF; - -R0.H = 0x0020; -R1.H = 0x0040; -R2.H = 0x0060; -R3.H = 0x0080; -R4.H = 0x00a0; -R5.H = 0x00b0; -R6.H = 0x00c0; -R7.H = 0x00d0; -CHECKREG r0, 0x0020FFFF; -CHECKREG r1, 0x0040FFFF; -CHECKREG r2, 0x0060FFFF; -CHECKREG r3, 0x0080FFFF; -CHECKREG r4, 0x00a0FFFF; -CHECKREG r5, 0x00b0FFFF; -CHECKREG r6, 0x00c0FFFF; -CHECKREG r7, 0x00d0FFFF; - -R0.H = 0x0100; -R1.H = 0x0200; -R2.H = 0x0300; -R3.H = 0x0400; -R4.H = 0x0500; -R5.H = 0x0600; -R6.H = 0x0700; -R7.H = 0x0800; -CHECKREG r0, 0x0100FFFF; -CHECKREG r1, 0x0200FFFF; -CHECKREG r2, 0x0300FFFF; -CHECKREG r3, 0x0400FFFF; -CHECKREG r4, 0x0500FFFF; -CHECKREG r5, 0x0600FFFF; -CHECKREG r6, 0x0700FFFF; -CHECKREG r7, 0x0800FFFF; - -R0 = 0; -R1 = 0; -R2 = 0; -R3 = 0; -R4 = 0; -R5 = 0; -R6 = 0; -R7 = 0; -R0.H = 0x7fff; -R1.H = 0x7ffe; -R2.H = 32767; -R3.H = 32766; -R4.H = -32768; -R5.H = -32767; -CHECKREG r0, 0x7fff0000; -CHECKREG r1, 0x7ffe0000; -CHECKREG r2, 0x7fff0000; -CHECKREG r3, 0x7ffe0000; -CHECKREG r4, 0x80000000; -CHECKREG r5, 0x80010000; - -pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s b/sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s deleted file mode 100644 index 0a33d4a..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s +++ /dev/null @@ -1,89 +0,0 @@ -//Original:/testcases/core/c_ldimmhalf_drlo/c_ldimmhalf_drlo.dsp -// Spec Reference: ldimmhalf dreg lo -# mach: bfin - -.include "testutils.inc" - start - - - -INIT_R_REGS -1; - -// test Dreg -R0.L = 0x0001; -R1.L = 0x0003; -R2.L = 0x0005; -R3.L = 0x0007; -R4.L = 0x0009; -R5.L = 0x000b; -R6.L = 0x000d; -R7.L = 0x000f; -CHECKREG r0, 0xFFFF0001; -CHECKREG r1, 0xFFFF0003; -CHECKREG r2, 0xFFFF0005; -CHECKREG r3, 0xFFFF0007; -CHECKREG r4, 0xFFFF0009; -CHECKREG r5, 0xFFFF000b; -CHECKREG r6, 0xFFFF000D; -CHECKREG r7, 0xFFFF000F; - -R0.L = 0x0020; -R1.L = 0x0040; -R2.L = 0x0060; -R3.L = 0x0080; -R4.L = 0x00a0; -R5.L = 0x00b0; -R6.L = 0x00c0; -R7.L = 0x00d0; -CHECKREG r0, 0xFFFF0020; -CHECKREG r1, 0xFFFF0040; -CHECKREG r2, 0xFFFF0060; -CHECKREG r3, 0xFFFF0080; -CHECKREG r4, 0xFFFF00a0; -CHECKREG r5, 0xFFFF00b0; -CHECKREG r6, 0xFFFF00c0; -CHECKREG r7, 0xFFFF00d0; - -R0.L = 0x0100; -R1.L = 0x0200; -R2.L = 0x0300; -R3.L = 0x0400; -R4.L = 0x0500; -R5.L = 0x0600; -R6.L = 0x0700; -R7.L = 0x0800; -CHECKREG r0, 0xFFFF0100; -CHECKREG r1, 0xFFFF0200; -CHECKREG r2, 0xFFFF0300; -CHECKREG r3, 0xFFFF0400; -CHECKREG r4, 0xFFFF0500; -CHECKREG r5, 0xFFFF0600; -CHECKREG r6, 0xFFFF0700; -CHECKREG r7, 0xFFFF0800; - -R0 = 0; -R1 = 0; -R2 = 0; -R3 = 0; -R4 = 0; -R5 = 0; -R6 = 0; -R7 = 0; -R0.L = 0x7fff; -R1.L = 0x7ffe; -R2.L = -32768; -R3.L = -32767; -R4.L = 32767; -R5.L = 32766; -R6.L = 32765; -R7.L = 32764; -CHECKREG r0, 0x00007fff; -CHECKREG r1, 0x00007ffe; -CHECKREG r2, 0x00008000; -CHECKREG r3, 0x00008001; -CHECKREG r4, 0x00007FFF; -CHECKREG r5, 0x00007FFE; -CHECKREG r6, 0x00007FFD; -CHECKREG r7, 0x00007FFC; - -pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_h_dr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_h_dr.s deleted file mode 100644 index 83e60db..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_h_dr.s +++ /dev/null @@ -1,82 +0,0 @@ -//Original:/testcases/core/c_ldimmhalf_h_dr/c_ldimmhalf_h_dr.dsp -// Spec Reference: ldimmhalf h dreg -# mach: bfin - -.include "testutils.inc" - start - - - -INIT_R_REGS -1; - - -// test Dreg -R0.H = 0x0000; -R1.H = 0x0002; -R2.H = 0x0004; -R3.H = 0x0006; -R4.H = 0x0008; -R5.H = 0x000a; -R6.H = 0x000c; -R7.H = 0x000e; -CHECKREG r0, 0x0000ffff; -CHECKREG r1, 0x0002ffff; -CHECKREG r2, 0x0004ffff; -CHECKREG r3, 0x0006ffff; -CHECKREG r4, 0x0008ffff; -CHECKREG r5, 0x000affff; -CHECKREG r6, 0x000cffff; -CHECKREG r7, 0x000effff; - -R0.H = 0x0000; -R1.H = 0x0020; -R2.H = 0x0040; -R3.H = 0x0060; -R4.H = 0x0080; -R5.H = 0x00a0; -R6.H = 0x00c0; -R7.H = 0x00e0; -CHECKREG r0, 0x0000ffff; -CHECKREG r1, 0x0020ffff; -CHECKREG r2, 0x0040ffff; -CHECKREG r3, 0x0060ffff; -CHECKREG r4, 0x0080ffff; -CHECKREG r5, 0x00a0ffff; -CHECKREG r6, 0x00c0ffff; -CHECKREG r7, 0x00e0ffff; - -R0.H = 0x0000; -R1.H = 0x0200; -R2.H = 0x0400; -R3.H = 0x0600; -R4.H = 0x0800; -R5.H = 0x0a00; -R6.H = 0x0c00; -R7.H = 0x0e00; -CHECKREG r0, 0x0000ffff; -CHECKREG r1, 0x0200ffff; -CHECKREG r2, 0x0400ffff; -CHECKREG r3, 0x0600ffff; -CHECKREG r4, 0x0800ffff; -CHECKREG r5, 0x0a00ffff; -CHECKREG r6, 0x0c00ffff; -CHECKREG r7, 0x0e00ffff; - -R0.H = 0x0000; -R1.H = 0x2000; -R2.H = 0x4000; -R3.H = 0x6000; -R4.H = 0x8000; -R5.H = 0xa000; -R6.H = 0xc000; -R7.H = 0xe000; -CHECKREG r0, 0x0000ffff; -CHECKREG r1, 0x2000ffff; -CHECKREG r2, 0x4000ffff; -CHECKREG r3, 0x6000ffff; -CHECKREG r4, 0x8000ffff; -CHECKREG r5, 0xa000ffff; -CHECKREG r6, 0xc000ffff; -CHECKREG r7, 0xe000ffff; - -pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_h_ibml.s b/sim/testsuite/sim/bfin/c_ldimmhalf_h_ibml.s deleted file mode 100644 index 8aedc09..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_h_ibml.s +++ /dev/null @@ -1,165 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_ibml/c_ldimmhalf_h_ibml.dsp -// Spec Reference: ldimmhalf h ibml -# mach: bfin - -.include "testutils.inc" - start - - INIT_I_REGS -1; - INIT_L_REGS -1; - INIT_B_REGS -1; - INIT_M_REGS -1; - - I0.H = 0x2000; - I1.H = 0x2002; - I2.H = 0x2004; - I3.H = 0x2006; - L0.H = 0x2008; - L1.H = 0x200a; - L2.H = 0x200c; - L3.H = 0x200e; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = L0; - R5 = L1; - R6 = L2; - R7 = L3; - CHECKREG r0, 0x2000ffff; - CHECKREG r1, 0x2002ffff; - CHECKREG r2, 0x2004ffff; - CHECKREG r3, 0x2006ffff; - CHECKREG r4, 0x2008ffff; - CHECKREG r5, 0x200affff; - CHECKREG r6, 0x200cffff; - CHECKREG r7, 0x200effff; - - I0.H = 0x0111; - I1.H = 0x1111; - I2.H = 0x2222; - I3.H = 0x3333; - L0.H = 0x4444; - L1.H = 0x5555; - L2.H = 0x6666; - L3.H = 0x7777; - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = L0; - R5 = L1; - R6 = L2; - R7 = L3; - CHECKREG r0, 0x0111ffff; - CHECKREG r1, 0x1111ffff; - CHECKREG r2, 0x2222ffff; - CHECKREG r3, 0x3333ffff; - CHECKREG r4, 0x4444ffff; - CHECKREG r5, 0x5555ffff; - CHECKREG r6, 0x6666ffff; - CHECKREG r7, 0x7777ffff; - - I0.H = 0x8888; - I1.H = 0x9aaa; - I2.H = 0xabbb; - I3.H = 0xbccc; - L0.H = 0xcddd; - L1.H = 0xdeee; - L2.H = 0xefff; - L3.H = 0xf111; - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = L0; - R5 = L1; - R6 = L2; - R7 = L3; - CHECKREG r0, 0x8888ffff; - CHECKREG r1, 0x9aaaffff; - CHECKREG r2, 0xabbbffff; - CHECKREG r3, 0xbcccffff; - CHECKREG r4, 0xcdddffff; - CHECKREG r5, 0xdeeeffff; - CHECKREG r6, 0xefffffff; - CHECKREG r7, 0xf111ffff; - - B0.H = 0x3000; - B1.H = 0x3002; - B2.H = 0x3004; - B3.H = 0x3006; - M0.H = 0x3008; - M1.H = 0x300a; - M2.H = 0x300c; - M3.H = 0x300e; - - R0 = B0; - R1 = B1; - R2 = B2; - R3 = B3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - CHECKREG r0, 0x3000ffff; - CHECKREG r1, 0x3002ffff; - CHECKREG r2, 0x3004ffff; - CHECKREG r3, 0x3006ffff; - CHECKREG r4, 0x3008ffff; - CHECKREG r5, 0x300Affff; - CHECKREG r6, 0x300cffff; - CHECKREG r7, 0x300effff; - - B0.H = 0x0110; - B1.H = 0x1110; - B2.H = 0x2220; - B3.H = 0x3330; - M0.H = 0x4440; - M1.H = 0x5550; - M2.H = 0x6660; - M3.H = 0x7770; - R0 = B0; - R1 = B1; - R2 = B2; - R3 = B3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - CHECKREG r0, 0x0110FFFF; - CHECKREG r1, 0x1110FFFF; - CHECKREG r2, 0x2220FFFF; - CHECKREG r3, 0x3330FFFF; - CHECKREG r4, 0x4440FFFF; - CHECKREG r5, 0x5550FFFF; - CHECKREG r6, 0x6660FFFF; - CHECKREG r7, 0x7770FFFF; - - B0.H = 0xf880; - B1.H = 0xfaa0; - B2.H = 0xfbb0; - B3.H = 0xfcc0; - M0.H = 0xfdd0; - M1.H = 0xfee0; - M2.H = 0xfff0; - M3.H = 0xf110; - R0 = B0; - R1 = B1; - R2 = B2; - R3 = B3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - CHECKREG r0, 0xf880ffff; - CHECKREG r1, 0xfaa0ffff; - CHECKREG r2, 0xfbb0ffff; - CHECKREG r3, 0xfcc0ffff; - CHECKREG r4, 0xfdd0ffff; - CHECKREG r5, 0xfee0ffff; - CHECKREG r6, 0xfff0ffff; - CHECKREG r7, 0xf110ffff; - - pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_h_pr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_h_pr.s deleted file mode 100644 index cf7fb41..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_h_pr.s +++ /dev/null @@ -1,74 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_pr/c_ldimmhalf_h_pr.dsp -// Spec Reference: ldimmhalf h preg -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS -1; - INIT_P_REGS -1; - imm32 sp, 0xffffffff; - imm32 fp, 0xffffffff; - -// test Preg - P1.H = 0x0002; - P2.H = 0x0004; - P3.H = 0x0006; - P4.H = 0x0008; - P5.H = 0x000a; - FP.H = 0x000c; - SP.H = 0x000e; - CHECKREG p1, 0x0002ffff; - CHECKREG p2, 0x0004ffff; - CHECKREG p3, 0x0006ffff; - CHECKREG p4, 0x0008ffff; - CHECKREG p5, 0x000affff; - CHECKREG fp, 0x000cffff; - CHECKREG sp, 0x000effff; - - P1.H = 0x0020; - P2.H = 0x0040; - P3.H = 0x0060; - P4.H = 0x0080; - P5.H = 0x00a0; - FP.H = 0x00c0; - SP.H = 0x00e0; - CHECKREG p1, 0x0020ffff; - CHECKREG p2, 0x0040ffff; - CHECKREG p3, 0x0060ffff; - CHECKREG p4, 0x0080ffff; - CHECKREG p5, 0x00a0ffff; - CHECKREG fp, 0x00c0ffff; - CHECKREG sp, 0x00e0ffff; - - P1.H = 0x0200; - P2.H = 0x0400; - P3.H = 0x0600; - P4.H = 0x0800; - P5.H = 0x0a00; - FP.H = 0x0c00; - SP.H = 0x0e00; - CHECKREG p1, 0x0200ffff; - CHECKREG p2, 0x0400ffff; - CHECKREG p3, 0x0600ffff; - CHECKREG p4, 0x0800ffff; - CHECKREG p5, 0x0a00ffff; - CHECKREG fp, 0x0c00ffff; - CHECKREG sp, 0x0e00ffff; - - P1.H = 0x2000; - P2.H = 0x4000; - P3.H = 0x6000; - P4.H = 0x8000; - P5.H = 0xa000; - FP.H = 0xc000; - SP.H = 0xe000; - CHECKREG p1, 0x2000ffff; - CHECKREG p2, 0x4000ffff; - CHECKREG p3, 0x6000ffff; - CHECKREG p4, 0x8000ffff; - CHECKREG p5, 0xa000ffff; - CHECKREG fp, 0xc000ffff; - CHECKREG sp, 0xe000ffff; - - pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_l_dr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_l_dr.s deleted file mode 100644 index b47284d..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_l_dr.s +++ /dev/null @@ -1,82 +0,0 @@ -//Original:/testcases/core/c_ldimmhalf_l_dr/c_ldimmhalf_l_dr.dsp -// Spec Reference: ldimmhalf l dreg -# mach: bfin - -.include "testutils.inc" - start - - - -INIT_R_REGS -1; - - -// test Dreg -R0.L = 0x0001; -R1.L = 0x0003; -R2.L = 0x0005; -R3.L = 0x0007; -R4.L = 0x0009; -R5.L = 0x000b; -R6.L = 0x000d; -R7.L = 0x000f; -CHECKREG r0, 0xffff0001; -CHECKREG r1, 0xffff0003; -CHECKREG r2, 0xffff0005; -CHECKREG r3, 0xffff0007; -CHECKREG r4, 0xffff0009; -CHECKREG r5, 0xffff000b; -CHECKREG r6, 0xffff000d; -CHECKREG r7, 0xffff000f; - -R0.L = 0x0010; -R1.L = 0x0030; -R2.L = 0x0050; -R3.L = 0x0070; -R4.L = 0x0090; -R5.L = 0x00b0; -R6.L = 0x00d0; -R7.L = 0x00f0; -CHECKREG r0, 0xffff0010; -CHECKREG r1, 0xffff0030; -CHECKREG r2, 0xffff0050; -CHECKREG r3, 0xffff0070; -CHECKREG r4, 0xffff0090; -CHECKREG r5, 0xffff00b0; -CHECKREG r6, 0xffff00d0; -CHECKREG r7, 0xffff00f0; - -R0.L = 0x0100; -R1.L = 0x0300; -R2.L = 0x0500; -R3.L = 0x0700; -R4.L = 0x0900; -R5.L = 0x0b00; -R6.L = 0x0d00; -R7.L = 0x0f00; -CHECKREG r0, 0xffff0100; -CHECKREG r1, 0xffff0300; -CHECKREG r2, 0xffff0500; -CHECKREG r3, 0xffff0700; -CHECKREG r4, 0xffff0900; -CHECKREG r5, 0xffff0b00; -CHECKREG r6, 0xffff0d00; -CHECKREG r7, 0xffff0f00; - -R0.L = 0x1000; -R1.L = 0x3000; -R2.L = 0x5000; -R3.L = 0x7000; -R4.L = 0x9000; -R5.L = 0xb000; -R6.L = 0xd000; -R7.L = 0xf000; -CHECKREG r0, 0xffff1000; -CHECKREG r1, 0xffff3000; -CHECKREG r2, 0xffff5000; -CHECKREG r3, 0xffff7000; -CHECKREG r4, 0xffff9000; -CHECKREG r5, 0xffffb000; -CHECKREG r6, 0xffffd000; -CHECKREG r7, 0xfffff000; - -pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_l_ibml.s b/sim/testsuite/sim/bfin/c_ldimmhalf_l_ibml.s deleted file mode 100644 index 66f83b0..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_l_ibml.s +++ /dev/null @@ -1,165 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_ibml/c_ldimmhalf_l_ibml.dsp -// Spec Reference: ldimmhalf l ibml -# mach: bfin - -.include "testutils.inc" - start - - INIT_I_REGS -1; - INIT_L_REGS -1; - INIT_M_REGS -1; - INIT_B_REGS -1; - - I0.L = 0x2001; - I1.L = 0x2003; - I2.L = 0x2005; - I3.L = 0x2007; - L0.L = 0x2009; - L1.L = 0x200b; - L2.L = 0x200d; - L3.L = 0x200f; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = L0; - R5 = L1; - R6 = L2; - R7 = L3; - CHECKREG r0, 0xffff2001; - CHECKREG r1, 0xffff2003; - CHECKREG r2, 0xffff2005; - CHECKREG r3, 0xffff2007; - CHECKREG r4, 0xffff2009; - CHECKREG r5, 0xffff200b; - CHECKREG r6, 0xffff200d; - CHECKREG r7, 0xffff200f; - - I0.L = 0x0111; - I1.L = 0x1111; - I2.L = 0x2222; - I3.L = 0x3333; - L0.L = 0x4444; - L1.L = 0x5555; - L2.L = 0x6666; - L3.L = 0x7777; - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = L0; - R5 = L1; - R6 = L2; - R7 = L3; - CHECKREG r0, 0xffff0111; - CHECKREG r1, 0xffff1111; - CHECKREG r2, 0xffff2222; - CHECKREG r3, 0xffff3333; - CHECKREG r4, 0xffff4444; - CHECKREG r5, 0xffff5555; - CHECKREG r6, 0xffff6666; - CHECKREG r7, 0xffff7777; - - I0.L = 0x8888; - I1.L = 0x9aaa; - I2.L = 0xabbb; - I3.L = 0xbccc; - L0.L = 0xcddd; - L1.L = 0xdeee; - L2.L = 0xefff; - L3.L = 0xf111; - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = L0; - R5 = L1; - R6 = L2; - R7 = L3; - CHECKREG r0, 0xffff8888; - CHECKREG r1, 0xffff9aaa; - CHECKREG r2, 0xffffabbb; - CHECKREG r3, 0xffffbccc; - CHECKREG r4, 0xffffcddd; - CHECKREG r5, 0xffffdeee; - CHECKREG r6, 0xffffefff; - CHECKREG r7, 0xfffff111; - - B0.L = 0x3001; - B1.L = 0x3003; - B2.L = 0x3005; - B3.L = 0x3007; - M0.L = 0x3009; - M1.L = 0x300b; - M2.L = 0x300d; - M3.L = 0x300f; - - R0 = B0; - R1 = B1; - R2 = B2; - R3 = B3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - CHECKREG r0, 0xffff3001; - CHECKREG r1, 0xffff3003; - CHECKREG r2, 0xffff3005; - CHECKREG r3, 0xffff3007; - CHECKREG r4, 0xffff3009; - CHECKREG r5, 0xffff300B; - CHECKREG r6, 0xffff300d; - CHECKREG r7, 0xffff300f; - - B0.L = 0x0110; - B1.L = 0x1110; - B2.L = 0x2220; - B3.L = 0x3330; - M0.L = 0x4440; - M1.L = 0x5550; - M2.L = 0x6660; - M3.L = 0x7770; - R0 = B0; - R1 = B1; - R2 = B2; - R3 = B3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - CHECKREG r0, 0xffff0110; - CHECKREG r1, 0xffff1110; - CHECKREG r2, 0xffff2220; - CHECKREG r3, 0xffff3330; - CHECKREG r4, 0xffff4440; - CHECKREG r5, 0xffff5550; - CHECKREG r6, 0xffff6660; - CHECKREG r7, 0xffff7770; - - B0.L = 0xf880; - B1.L = 0xfaa0; - B2.L = 0xfbb0; - B3.L = 0xfcc0; - M0.L = 0xfdd0; - M1.L = 0xfee0; - M2.L = 0xfff0; - M3.L = 0xf110; - R0 = B0; - R1 = B1; - R2 = B2; - R3 = B3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - CHECKREG r0, 0xfffff880; - CHECKREG r1, 0xfffffaa0; - CHECKREG r2, 0xfffffbb0; - CHECKREG r3, 0xfffffcc0; - CHECKREG r4, 0xfffffdd0; - CHECKREG r5, 0xfffffee0; - CHECKREG r6, 0xfffffff0; - CHECKREG r7, 0xfffff110; - - pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_l_pr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_l_pr.s deleted file mode 100644 index c067862..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_l_pr.s +++ /dev/null @@ -1,76 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_pr/c_ldimmhalf_l_pr.dsp -// Spec Reference: ldimmhalf l preg -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS -1; - INIT_P_REGS -1; - - imm32 sp, 0xffffffff; - imm32 fp, 0xffffffff; - -// test Preg - P1.L = 0x0003; - P2.L = 0x0005; - P3.L = 0x0007; - P4.L = 0x0009; - P5.L = 0x000b; - FP.L = 0x000d; - SP.L = 0x000f; - CHECKREG p1, 0xffff0003; - CHECKREG p2, 0xffff0005; - CHECKREG p3, 0xffff0007; - CHECKREG p4, 0xffff0009; - CHECKREG p5, 0xffff000b; - CHECKREG fp, 0xffff000d; - CHECKREG sp, 0xffff000f; - - P1.L = 0x0030; - P2.L = 0x0050; - P3.L = 0x0070; - P4.L = 0x0090; - P5.L = 0x00b0; - FP.L = 0x00d0; - SP.L = 0x00f0; -//CHECKREG p0, 0x00000010; - CHECKREG p1, 0xffff0030; - CHECKREG p2, 0xffff0050; - CHECKREG p3, 0xffff0070; - CHECKREG p4, 0xffff0090; - CHECKREG p5, 0xffff00b0; - CHECKREG fp, 0xffff00d0; - CHECKREG sp, 0xffff00f0; - - P1.L = 0x0300; - P2.L = 0x0500; - P3.L = 0x0700; - P4.L = 0x0900; - P5.L = 0x0b00; - FP.L = 0x0d00; - SP.L = 0x0f00; - CHECKREG p1, 0xffff0300; - CHECKREG p2, 0xffff0500; - CHECKREG p3, 0xffff0700; - CHECKREG p4, 0xffff0900; - CHECKREG p5, 0xffff0b00; - CHECKREG fp, 0xffff0d00; - CHECKREG sp, 0xffff0f00; - - P1.L = 0x3000; - P2.L = 0x5000; - P3.L = 0x7000; - P4.L = 0x9000; - P5.L = 0xb000; - FP.L = 0xd000; - SP.L = 0xf000; - CHECKREG p1, 0xffff3000; - CHECKREG p2, 0xffff5000; - CHECKREG p3, 0xffff7000; - CHECKREG p4, 0xffff9000; - CHECKREG p5, 0xffffb000; - CHECKREG fp, 0xffffd000; - CHECKREG sp, 0xfffff000; - - pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_lz_dr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_lz_dr.s deleted file mode 100644 index a2ae95f..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_lz_dr.s +++ /dev/null @@ -1,81 +0,0 @@ -//Original:/testcases/core/c_ldimmhalf_lz_dr/c_ldimmhalf_lz_dr.dsp -// Spec Reference: ldimmhalf lz dreg -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS -1; - - -// test Dreg -R0 = 0x0001 (Z); -R1 = 0x0003 (Z); -R2 = 0x0005 (Z); -R3 = 0x0007 (Z); -R4 = 0x0009 (Z); -R5 = 0x000b (Z); -R6 = 0x000d (Z); -R7 = 0x000f (Z); -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000003; -CHECKREG r2, 0x00000005; -CHECKREG r3, 0x00000007; -CHECKREG r4, 0x00000009; -CHECKREG r5, 0x0000000b; -CHECKREG r6, 0x0000000d; -CHECKREG r7, 0x0000000f; - -R0 = 0x0010 (Z); -R1 = 0x0030 (Z); -R2 = 0x0050 (Z); -R3 = 0x0070 (Z); -R4 = 0x0090 (Z); -R5 = 0x00b0 (Z); -R6 = 0x00d0 (Z); -R7 = 0x00f0 (Z); -CHECKREG r0, 0x00000010; -CHECKREG r1, 0x00000030; -CHECKREG r2, 0x00000050; -CHECKREG r3, 0x00000070; -CHECKREG r4, 0x00000090; -CHECKREG r5, 0x000000b0; -CHECKREG r6, 0x000000d0; -CHECKREG r7, 0x000000f0; - -R0 = 0x0100 (Z); -R1 = 0x0300 (Z); -R2 = 0x0500 (Z); -R3 = 0x0700 (Z); -R4 = 0x0900 (Z); -R5 = 0x0b00 (Z); -R6 = 0x0d00 (Z); -R7 = 0x0f00 (Z); -CHECKREG r0, 0x00000100; -CHECKREG r1, 0x00000300; -CHECKREG r2, 0x00000500; -CHECKREG r3, 0x00000700; -CHECKREG r4, 0x00000900; -CHECKREG r5, 0x00000b00; -CHECKREG r6, 0x00000d00; -CHECKREG r7, 0x00000f00; - -R0 = 0x1000 (Z); -R1 = 0x3000 (Z); -R2 = 0x5000 (Z); -R3 = 0x7000 (Z); -R4 = 0x9000 (Z); -R5 = 0xb000 (Z); -R6 = 0xd000 (Z); -R7 = 0xf000 (Z); -CHECKREG r0, 0x00001000; -CHECKREG r1, 0x00003000; -CHECKREG r2, 0x00005000; -CHECKREG r3, 0x00007000; -CHECKREG r4, 0x00009000; -CHECKREG r5, 0x0000b000; -CHECKREG r6, 0x0000d000; -CHECKREG r7, 0x0000f000; - -pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_lz_ibml.s b/sim/testsuite/sim/bfin/c_ldimmhalf_lz_ibml.s deleted file mode 100644 index efe77ae..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_lz_ibml.s +++ /dev/null @@ -1,168 +0,0 @@ -//Original:/testcases/core/c_ldimmhalf_lz_ibml/c_ldimmhalf_lz_ibml.dsp -# mach: bfin - -.include "testutils.inc" - start - - -// Spec Reference: ldimmhalf lz ibml - - - - -I0 = 0x2001 (Z); -I1 = 0x2003 (Z); -I2 = 0x2005 (Z); -I3 = 0x2007 (Z); -L0 = 0x2009 (Z); -L1 = 0x200b (Z); -L2 = 0x200d (Z); -L3 = 0x200f (Z); - - -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = L0; -R5 = L1; -R6 = L2; -R7 = L3; -CHECKREG r0, 0x00002001; -CHECKREG r1, 0x00002003; -CHECKREG r2, 0x00002005; -CHECKREG r3, 0x00002007; -CHECKREG r4, 0x00002009; -CHECKREG r5, 0x0000200b; -CHECKREG r6, 0x0000200d; -CHECKREG r7, 0x0000200f; - -I0 = 0x0111 (Z); -I1 = 0x1111 (Z); -I2 = 0x2222 (Z); -I3 = 0x3333 (Z); -L0 = 0x4444 (Z); -L1 = 0x5555 (Z); -L2 = 0x6666 (Z); -L3 = 0x7777 (Z); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = L0; -R5 = L1; -R6 = L2; -R7 = L3; -CHECKREG r0, 0x00000111; -CHECKREG r1, 0x00001111; -CHECKREG r2, 0x00002222; -CHECKREG r3, 0x00003333; -CHECKREG r4, 0x00004444; -CHECKREG r5, 0x00005555; -CHECKREG r6, 0x00006666; -CHECKREG r7, 0x00007777; - -I0 = 0x8888 (Z); -I1 = 0x9aaa (Z); -I2 = 0xabbb (Z); -I3 = 0xbccc (Z); -L0 = 0xcddd (Z); -L1 = 0xdeee (Z); -L2 = 0xefff (Z); -L3 = 0xf111 (Z); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = L0; -R5 = L1; -R6 = L2; -R7 = L3; -CHECKREG r0, 0x00008888; -CHECKREG r1, 0x00009aaa; -CHECKREG r2, 0x0000abbb; -CHECKREG r3, 0x0000bccc; -CHECKREG r4, 0x0000cddd; -CHECKREG r5, 0x0000deee; -CHECKREG r6, 0x0000efff; -CHECKREG r7, 0x0000f111; - -B0 = 0x3001 (Z); -B1 = 0x3003 (Z); -B2 = 0x3005 (Z); -B3 = 0x3007 (Z); -M0 = 0x3009 (Z); -M1 = 0x300b (Z); -M2 = 0x300d (Z); -M3 = 0x300f (Z); - -R0 = B0; -R1 = B1; -R2 = B2; -R3 = B3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x00003001; -CHECKREG r1, 0x00003003; -CHECKREG r2, 0x00003005; -CHECKREG r3, 0x00003007; -CHECKREG r4, 0x00003009; -CHECKREG r5, 0x0000300B; -CHECKREG r6, 0x0000300d; -CHECKREG r7, 0x0000300f; - - -B0 = 0x0110 (Z); -B1 = 0x1110 (Z); -B2 = 0x2220 (Z); -B3 = 0x3330 (Z); -M0 = 0x4440 (Z); -M1 = 0x5550 (Z); -M2 = 0x6660 (Z); -M3 = 0x7770 (Z); -R0 = B0; -R1 = B1; -R2 = B2; -R3 = B3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x00000110; -CHECKREG r1, 0x00001110; -CHECKREG r2, 0x00002220; -CHECKREG r3, 0x00003330; -CHECKREG r4, 0x00004440; -CHECKREG r5, 0x00005550; -CHECKREG r6, 0x00006660; -CHECKREG r7, 0x00007770; - -B0 = 0xf880 (Z); -B1 = 0xfaa0 (Z); -B2 = 0xfbb0 (Z); -B3 = 0xfcc0 (Z); -M0 = 0xfdd0 (Z); -M1 = 0xfee0 (Z); -M2 = 0xfff0 (Z); -M3 = 0xf110 (Z); -R0 = B0; -R1 = B1; -R2 = B2; -R3 = B3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x0000f880; -CHECKREG r1, 0x0000faa0; -CHECKREG r2, 0x0000fbb0; -CHECKREG r3, 0x0000fcc0; -CHECKREG r4, 0x0000fdd0; -CHECKREG r5, 0x0000fee0; -CHECKREG r6, 0x0000fff0; -CHECKREG r7, 0x0000f110; - - -pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_lz_pr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_lz_pr.s deleted file mode 100644 index 23d3191..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_lz_pr.s +++ /dev/null @@ -1,72 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lz_pr/c_ldimmhalf_lz_pr.dsp -// Spec Reference: ldimmhalf lz preg -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS -1; - -// test Preg - P1 = 0x0003 (Z); - P2 = 0x0005 (Z); - P3 = 0x0007 (Z); - P4 = 0x0009 (Z); - P5 = 0x000b (Z); - FP = 0x000d (Z); - SP = 0x000f (Z); - CHECKREG p1, 0x00000003; - CHECKREG p2, 0x00000005; - CHECKREG p3, 0x00000007; - CHECKREG p4, 0x00000009; - CHECKREG p5, 0x0000000b; - CHECKREG fp, 0x0000000d; - CHECKREG sp, 0x0000000f; - - P1 = 0x0030 (Z); - P2 = 0x0050 (Z); - P3 = 0x0070 (Z); - P4 = 0x0090 (Z); - P5 = 0x00b0 (Z); - FP = 0x00d0 (Z); - SP = 0x00f0 (Z); -//CHECKREG p0, 0x00000010; - CHECKREG p1, 0x00000030; - CHECKREG p2, 0x00000050; - CHECKREG p3, 0x00000070; - CHECKREG p4, 0x00000090; - CHECKREG p5, 0x000000b0; - CHECKREG fp, 0x000000d0; - CHECKREG sp, 0x000000f0; - - P1 = 0x0300 (Z); - P2 = 0x0500 (Z); - P3 = 0x0700 (Z); - P4 = 0x0900 (Z); - P5 = 0x0b00 (Z); - FP = 0x0d00 (Z); - SP = 0x0f00 (Z); - CHECKREG p1, 0x00000300; - CHECKREG p2, 0x00000500; - CHECKREG p3, 0x00000700; - CHECKREG p4, 0x00000900; - CHECKREG p5, 0x00000b00; - CHECKREG fp, 0x00000d00; - CHECKREG sp, 0x00000f00; - - P1 = 0x3000 (Z); - P2 = 0x5000 (Z); - P3 = 0x7000 (Z); - P4 = 0x9000 (Z); - P5 = 0xb000 (Z); - FP = 0xd000 (Z); - SP = 0xf000 (Z); - CHECKREG p1, 0x00003000; - CHECKREG p2, 0x00005000; - CHECKREG p3, 0x00007000; - CHECKREG p4, 0x00009000; - CHECKREG p5, 0x0000b000; - CHECKREG fp, 0x0000d000; - CHECKREG sp, 0x0000f000; - - pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_dr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_dr.s deleted file mode 100644 index 67e652a..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_dr.s +++ /dev/null @@ -1,113 +0,0 @@ -//Original:/testcases/core/c_ldimmhalf_lzhi_dr/c_ldimmhalf_lzhi_dr.dsp -// Spec Reference: ldimmhalf lz & hi dreg -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS -1; - - -// test Dreg -R0 = 0x0001 (Z); -R0.H = 0x0000; -R1 = 0x0003 (Z); -R1.H = 0x0002; -R2 = 0x0005 (Z); -R2.H = 0x0004; -R3 = 0x0007 (Z); -R3.H = 0x0006; -R4 = 0x0009 (Z); -R4.H = 0x0008; -R5 = 0x000b (Z); -R5.H = 0x000a; -R6 = 0x000d (Z); -R6.H = 0x000c; -R7 = 0x000f (Z); -R7.H = 0x000e; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00020003; -CHECKREG r2, 0x00040005; -CHECKREG r3, 0x00060007; -CHECKREG r4, 0x00080009; -CHECKREG r5, 0x000a000b; -CHECKREG r6, 0x000c000d; -CHECKREG r7, 0x000e000f; - -R0 = 0x0010 (Z); -R0.H = 0x0000; -R1 = 0x0030 (Z); -R1.H = 0x0020; -R2 = 0x0050 (Z); -R2.H = 0x0040; -R3 = 0x0070 (Z); -R3.H = 0x0060; -R4 = 0x0090 (Z); -R4.H = 0x0080; -R5 = 0x00b0 (Z); -R5.H = 0x00a0; -R6 = 0x00d0 (Z); -R6.H = 0x00c0; -R7 = 0x00f0 (Z); -R7.H = 0x00e0; -CHECKREG r0, 0x00000010; -CHECKREG r1, 0x00200030; -CHECKREG r2, 0x00400050; -CHECKREG r3, 0x00600070; -CHECKREG r4, 0x00800090; -CHECKREG r5, 0x00a000b0; -CHECKREG r6, 0x00c000d0; -CHECKREG r7, 0x00e000f0; - -R0 = 0x0100 (Z); -R0.H = 0x0000; -R1 = 0x0300 (Z); -R1.H = 0x0200; -R2 = 0x0500 (Z); -R2.H = 0x0400; -R3 = 0x0700 (Z); -R3.H = 0x0600; -R4 = 0x0900 (Z); -R4.H = 0x0800; -R5 = 0x0b00 (Z); -R5.H = 0x0a00; -R6 = 0x0d00 (Z); -R6.H = 0x0c00; -R7 = 0x0f00 (Z); -R7.H = 0x0e00; -CHECKREG r0, 0x00000100; -CHECKREG r1, 0x02000300; -CHECKREG r2, 0x04000500; -CHECKREG r3, 0x06000700; -CHECKREG r4, 0x08000900; -CHECKREG r5, 0x0a000b00; -CHECKREG r6, 0x0c000d00; -CHECKREG r7, 0x0e000f00; - -R0 = 0x1000 (Z); -R0.H = 0x0000; -R1 = 0x3000 (Z); -R1.H = 0x2000; -R2 = 0x5000 (Z); -R2.H = 0x4000; -R3 = 0x7000 (Z); -R3.H = 0x6000; -R4 = 0x9000 (Z); -R4.H = 0x8000; -R5 = 0xb000 (Z); -R5.H = 0xa000; -R6 = 0xd000 (Z); -R6.H = 0xc000; -R7 = 0xf000 (Z); -R7.H = 0xe000; -CHECKREG r0, 0x00001000; -CHECKREG r1, 0x20003000; -CHECKREG r2, 0x40005000; -CHECKREG r3, 0x60007000; -CHECKREG r4, 0x80009000; -CHECKREG r5, 0xa000b000; -CHECKREG r6, 0xc000d000; -CHECKREG r7, 0xe000f000; - -pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_ibml.s b/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_ibml.s deleted file mode 100644 index 6f5720b..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_ibml.s +++ /dev/null @@ -1,216 +0,0 @@ -//Original:/testcases/core/c_ldimmhalf_lzhi_ibml/c_ldimmhalf_lzhi_ibml.dsp -# mach: bfin - -.include "testutils.inc" - start - - -// Spec Reference: ldimmhalf lzhi ibml - - - - -I0 = 0x2001 (Z); -I0.H = 0x2000; -I1 = 0x2003 (Z); -I1.H = 0x2002; -I2 = 0x2005 (Z); -I2.H = 0x2004; -I3 = 0x2007 (Z); -I3.H = 0x2006; -L0 = 0x2009 (Z); -L0.H = 0x2008; -L1 = 0x200b (Z); -L1.H = 0x200a; -L2 = 0x200d (Z); -L2.H = 0x200c; -L3 = 0x200f (Z); -L3.H = 0x200e; - - -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = L0; -R5 = L1; -R6 = L2; -R7 = L3; -CHECKREG r0, 0x20002001; -CHECKREG r1, 0x20022003; -CHECKREG r2, 0x20042005; -CHECKREG r3, 0x20062007; -CHECKREG r4, 0x20082009; -CHECKREG r5, 0x200a200b; -CHECKREG r6, 0x200c200d; -CHECKREG r7, 0x200e200f; - -I0 = 0x0111 (Z); -I0.H = 0x1000; -I1 = 0x1111 (Z); -I1.H = 0x1000; -I2 = 0x2222 (Z); -I2.H = 0x2000; -I3 = 0x3333 (Z); -I3.H = 0x3000; -L0 = 0x4444 (Z); -L0.H = 0x4000; -L1 = 0x5555 (Z); -L1.H = 0x5000; -L2 = 0x6666 (Z); -L2.H = 0x6000; -L3 = 0x7777 (Z); -L3.H = 0x7000; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = L0; -R5 = L1; -R6 = L2; -R7 = L3; -CHECKREG r0, 0x10000111; -CHECKREG r1, 0x10001111; -CHECKREG r2, 0x20002222; -CHECKREG r3, 0x30003333; -CHECKREG r4, 0x40004444; -CHECKREG r5, 0x50005555; -CHECKREG r6, 0x60006666; -CHECKREG r7, 0x70007777; - -I0 = 0x8888 (Z); -I0.H = 0x8000; -I1 = 0x9aaa (Z); -I1.H = 0x9000; -I2 = 0xabbb (Z); -I2.H = 0xa000; -I3 = 0xbccc (Z); -I3.H = 0xb000; -L0 = 0xcddd (Z); -L0.H = 0xc000; -L1 = 0xdeee (Z); -L1.H = 0xd000; -L2 = 0xefff (Z); -L2.H = 0xe000; -L3 = 0xf111 (Z); -L3.H = 0xf000; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = L0; -R5 = L1; -R6 = L2; -R7 = L3; -CHECKREG r0, 0x80008888; -CHECKREG r1, 0x90009aaa; -CHECKREG r2, 0xa000abbb; -CHECKREG r3, 0xb000bccc; -CHECKREG r4, 0xc000cddd; -CHECKREG r5, 0xd000deee; -CHECKREG r6, 0xe000efff; -CHECKREG r7, 0xf000f111; - -B0 = 0x3001 (Z); -B0.H = 0x3000; -B1 = 0x3003 (Z); -B1.H = 0x3002; -B2 = 0x3005 (Z); -B2.H = 0x3004; -B3 = 0x3007 (Z); -B3.H = 0x3006; -M0 = 0x3009 (Z); -M0.H = 0x3008; -M1 = 0x300b (Z); -M1.H = 0x300a; -M2 = 0x300d (Z); -M2.H = 0x300c; -M3 = 0x300f (Z); -M3.H = 0x300e; - -R0 = B0; -R1 = B1; -R2 = B2; -R3 = B3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x30003001; -CHECKREG r1, 0x30023003; -CHECKREG r2, 0x30043005; -CHECKREG r3, 0x30063007; -CHECKREG r4, 0x30083009; -CHECKREG r5, 0x300A300B; -CHECKREG r6, 0x300c300d; -CHECKREG r7, 0x300e300f; - - -B0 = 0x0110 (Z); -B0.H = 0x1000; -B1 = 0x1110 (Z); -B1.H = 0x1000; -B2 = 0x2220 (Z); -B2.H = 0x2000; -B3 = 0x3330 (Z); -B3.H = 0x3000; -M0 = 0x4440 (Z); -M0.H = 0x4000; -M1 = 0x5550 (Z); -M1.H = 0x5000; -M2 = 0x6660 (Z); -M2.H = 0x6000; -M3 = 0x7770 (Z); -M3.H = 0x7000; -R0 = B0; -R1 = B1; -R2 = B2; -R3 = B3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x10000110; -CHECKREG r1, 0x10001110; -CHECKREG r2, 0x20002220; -CHECKREG r3, 0x30003330; -CHECKREG r4, 0x40004440; -CHECKREG r5, 0x50005550; -CHECKREG r6, 0x60006660; -CHECKREG r7, 0x70007770; - -B0 = 0xf880 (Z); -B0.H = 0x8000; -B1 = 0xfaa0 (Z); -B1.H = 0xa000; -B2 = 0xfbb0 (Z); -B2.H = 0xb000; -B3 = 0xfcc0 (Z); -B3.H = 0xc000; -M0 = 0xfdd0 (Z); -M0.H = 0xd000; -M1 = 0xfee0 (Z); -M1.H = 0xe000; -M2 = 0xfff0 (Z); -M2.H = 0xf000; -M3 = 0xf110 (Z); -M3.H = 0x1000; -R0 = B0; -R1 = B1; -R2 = B2; -R3 = B3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x8000f880; -CHECKREG r1, 0xa000faa0; -CHECKREG r2, 0xb000fbb0; -CHECKREG r3, 0xc000fcc0; -CHECKREG r4, 0xd000fdd0; -CHECKREG r5, 0xe000fee0; -CHECKREG r6, 0xf000fff0; -CHECKREG r7, 0x1000f110; - - -pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_pr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_pr.s deleted file mode 100644 index 9276d36..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_pr.s +++ /dev/null @@ -1,102 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lzhi_pr/c_ldimmhalf_lzhi_pr.dsp -// Spec Reference: ldimmhalf lzhi preg -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS -1; - -// test Preg -//lz(p0)=0x0001; -//h(p0) =0x0000; - P1 = 0x0003 (Z); - P1.H = 0x0002; - P2 = 0x0005 (Z); - P2.H = 0x0004; - P3 = 0x0007 (Z); - P3.H = 0x0006; - P4 = 0x0009 (Z); - P4.H = 0x0008; - P5 = 0x000b (Z); - P5.H = 0x000a; - FP = 0x000d (Z); - FP.H = 0x000c; - SP = 0x000f (Z); - SP.H = 0x000e; - CHECKREG p1, 0x00020003; - CHECKREG p2, 0x00040005; - CHECKREG p3, 0x00060007; - CHECKREG p4, 0x00080009; - CHECKREG p5, 0x000a000b; - CHECKREG fp, 0x000c000d; - CHECKREG sp, 0x000e000f; - - P1 = 0x0030 (Z); - P1.H = 0x0020; - P2 = 0x0050 (Z); - P2.H = 0x0040; - P3 = 0x0070 (Z); - P3.H = 0x0060; - P4 = 0x0090 (Z); - P4.H = 0x0080; - P5 = 0x00b0 (Z); - P5.H = 0x00a0; - FP = 0x00d0 (Z); - FP.H = 0x00c0; - SP = 0x00f0 (Z); - SP.H = 0x00e0; -//CHECKREG p0, 0x00000010; - CHECKREG p1, 0x00200030; - CHECKREG p2, 0x00400050; - CHECKREG p3, 0x00600070; - CHECKREG p4, 0x00800090; - CHECKREG p5, 0x00a000b0; - CHECKREG fp, 0x00c000d0; - CHECKREG sp, 0x00e000f0; - - P1 = 0x0300 (Z); - P1.H = 0x0200; - P2 = 0x0500 (Z); - P2.H = 0x0400; - P3 = 0x0700 (Z); - P3.H = 0x0600; - P4 = 0x0900 (Z); - P4.H = 0x0800; - P5 = 0x0b00 (Z); - P5.H = 0x0a00; - FP = 0x0d00 (Z); - FP.H = 0x0c00; - SP = 0x0f00 (Z); - SP.H = 0x0e00; - CHECKREG p1, 0x02000300; - CHECKREG p2, 0x04000500; - CHECKREG p3, 0x06000700; - CHECKREG p4, 0x08000900; - CHECKREG p5, 0x0a000b00; - CHECKREG fp, 0x0c000d00; - CHECKREG sp, 0x0e000f00; - - P1 = 0x3000 (Z); - P1.H = 0x2000; - P2 = 0x5000 (Z); - P2.H = 0x4000; - P3 = 0x7000 (Z); - P3.H = 0x6000; - P4 = 0x9000 (Z); - P4.H = 0x8000; - P5 = 0xb000 (Z); - P5.H = 0xa000; - FP = 0xd000 (Z); - FP.H = 0xc000; - SP = 0xf000 (Z); - SP.H = 0xe000; - CHECKREG p1, 0x20003000; - CHECKREG p2, 0x40005000; - CHECKREG p3, 0x60007000; - CHECKREG p4, 0x80009000; - CHECKREG p5, 0xa000b000; - CHECKREG fp, 0xc000d000; - CHECKREG sp, 0xe000f000; - - pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_pibml.s b/sim/testsuite/sim/bfin/c_ldimmhalf_pibml.s deleted file mode 100644 index a7e8f8b..0000000 --- a/sim/testsuite/sim/bfin/c_ldimmhalf_pibml.s +++ /dev/null @@ -1,212 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_pibml/c_ldimmhalf_pibml.dsp -// Spec Reference: ldimmhalf p i b m l -# mach: bfin - -.include "testutils.inc" - start - -// set all reg=-1 - - -//p0 =0x0123; - P1 = 0x1234 (X); - P2 = 0x2345 (X); - P3 = 0x3456 (X); - P4 = 0x4567 (X); - P5 = 0x5678 (X); - FP = 0x6789 (X); - SP = 0x789a (X); -//CHECKREG p0, 0x00000123; - CHECKREG p1, 0x00001234; - CHECKREG p2, 0x00002345; - CHECKREG p3, 0x00003456; - CHECKREG p4, 0x00004567; - CHECKREG p5, 0x00005678; - CHECKREG fp, 0x00006789; - CHECKREG sp, 0x0000789A; - -//p0 = -32768; - P1 = -32768 (X); - P2 = -2222 (X); - P3 = -3333 (X); - P4 = -4444 (X); - P5 = -5555 (X); - FP = -6666 (X); - SP = -7777 (X); -//CHECKREG r0, 0xFFFF8000; - CHECKREG p1, 0xFFFF8000; - CHECKREG p2, 0xFFFFF752; - CHECKREG p3, 0xFFFFF2FB; - CHECKREG p4, 0xFFFFEEA4; - CHECKREG p5, 0xFFFFEA4D; - CHECKREG fp, 0xFFFFE5F6; - CHECKREG sp, 0xFFFFE19F; - -//p0 =0x0123; - P1 = 0x7abc (X); - P2 = 0x6def (X); - P3 = 0x5f56 (X); - P4 = 0x7dd7 (X); - P5 = 0x4abd (X); - FP = 0x7fff (X); - SP = 0x7ffa (X); -//CHECKREG p0, 0x00000123; - CHECKREG p1, 0x00007abc; - CHECKREG p2, 0x00006def; - CHECKREG p3, 0x00005f56; - CHECKREG p4, 0x00007dd7; - CHECKREG p5, 0x00004abd; - CHECKREG fp, 0x00007fff; - CHECKREG sp, 0x00007ffa; - - I0 = 0x0123 (X); - I1 = 0x1234 (X); - I2 = 0x2345 (X); - I3 = 0x3456 (X); - B0 = 0x0567 (X); - B1 = 0x1678 (X); - B2 = 0x2789 (X); - B3 = 0x389a (X); - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - CHECKREG r0, 0x00000123; - CHECKREG r1, 0x00001234; - CHECKREG r2, 0x00002345; - CHECKREG r3, 0x00003456; - CHECKREG r4, 0x00000567; - CHECKREG r5, 0x00001678; - CHECKREG r6, 0x00002789; - CHECKREG r7, 0x0000389A; - - I0 = -32768 (X); - I1 = -12345 (X); - I2 = -23456 (X); - I3 = -3456 (X); - B0 = -4567 (X); - B1 = -5678 (X); - B2 = -6678 (X); - B3 = -7012 (X); - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - CHECKREG r0, 0xFFFF8000; - CHECKREG r1, 0xFFFFCFC7; - CHECKREG r2, 0xFFFFA460; - CHECKREG r3, 0xFFFFF280; - CHECKREG r4, 0xFFFFEE29; - CHECKREG r5, 0xFFFFE9D2; - CHECKREG r6, 0xFFFFE5EA; - CHECKREG r7, 0xFFFFE49C; - - I0 = 0x7abd (X); - I1 = 0x7bf4 (X); - I2 = 0x6c45 (X); - I3 = 0x7d56 (X); - B0 = 0x7e67 (X); - B1 = 0x7f78 (X); - B2 = 0x7ff9 (X); - B3 = 0x7fff (X); - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - CHECKREG r0, 0x00007abd; - CHECKREG r1, 0x00007bf4; - CHECKREG r2, 0x00006c45; - CHECKREG r3, 0x00007d56; - CHECKREG r4, 0x00007e67; - CHECKREG r5, 0x00007f78; - CHECKREG r6, 0x00007ff9; - CHECKREG r7, 0x00007fff; - - M0 = 0x7123 (X); - M1 = 0x7234 (X); - M2 = 0x7345 (X); - M3 = 0x7456 (X); - L0 = 0x7567 (X); - L1 = 0x7678 (X); - L2 = 0x7789 (X); - L3 = 0x789a (X); - R0 = M0; - R1 = M1; - R2 = M2; - R3 = M3; - R4 = L0; - R5 = L1; - R6 = L2; - R7 = L3; - CHECKREG r0, 0x00007123; - CHECKREG r1, 0x00007234; - CHECKREG r2, 0x00007345; - CHECKREG r3, 0x00007456; - CHECKREG r4, 0x00007567; - CHECKREG r5, 0x00007678; - CHECKREG r6, 0x00007789; - CHECKREG r7, 0x0000789A; - - M0 = -32768 (X); - M1 = -123 (X); - M2 = -234 (X); - M3 = -345 (X); - L0 = -456 (X); - L1 = -567 (X); - L2 = -667 (X); - L3 = -701 (X); - R0 = M0; - R1 = M1; - R2 = M2; - R3 = M3; - R4 = L0; - R5 = L1; - R6 = L2; - R7 = L3; - CHECKREG r0, 0xFFFF8000; - CHECKREG r1, 0xFFFFFF85; - CHECKREG r2, 0xFFFFFF16; - CHECKREG r3, 0xFFFFFEA7; - CHECKREG r4, 0xFFFFFE38; - CHECKREG r5, 0xFFFFFDC9; - CHECKREG r6, 0xFFFFFD65; - CHECKREG r7, 0xFFFFFD43; - - M0 = 0x7aaa (X); - M1 = 0x7bbb (X); - M2 = 0x7ccc (X); - M3 = 0x7ddd (X); - L0 = 0x7eee (X); - L1 = 0x7fa8 (X); - L2 = 0x7fb9 (X); - L3 = 0x7fcc (X); - R0 = M0; - R1 = M1; - R2 = M2; - R3 = M3; - R4 = L0; - R5 = L1; - R6 = L2; - R7 = L3; - CHECKREG r0, 0x00007aaa; - CHECKREG r1, 0x00007bbb; - CHECKREG r2, 0x00007ccc; - CHECKREG r3, 0x00007ddd; - CHECKREG r4, 0x00007eee; - CHECKREG r5, 0x00007fa8; - CHECKREG r6, 0x00007fb9; - CHECKREG r7, 0x00007fcc; - - pass diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p.s deleted file mode 100644 index 1183e44..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p.s +++ /dev/null @@ -1,372 +0,0 @@ -//Original:/testcases/core/c_ldst_ld_d_p/c_ldst_ld_d_p.dsp -// Spec Reference: c_ldst ld d [p] -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym p1, DATA_ADDR_1; - loadsym p2, DATA_ADDR_2; - loadsym p4, DATA_ADDR_4; - loadsym p5, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ P5 ]; - R6 = [ FP ]; - CHECKREG r0, 0x00010203; - CHECKREG r1, 0x20212223; - CHECKREG r3, 0x60616263; - CHECKREG r4, 0x80818283; - CHECKREG r5, 0x80818283; - CHECKREG r6, 0x00010203; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - R7 = [ P1 ]; - CHECKREG r0, 0x00010203; - CHECKREG r1, 0x20212223; - CHECKREG r3, 0x60616263; - CHECKREG r4, 0x80818283; - CHECKREG r5, 0x00010203; - CHECKREG r7, 0x00010203; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - R7 = [ P1 ]; - R0 = [ P2 ]; - CHECKREG r0, 0x20212223; - CHECKREG r1, 0x20212223; - CHECKREG r3, 0x60616263; - CHECKREG r4, 0x80818283; - CHECKREG r5, 0x00010203; - CHECKREG r7, 0x00010203; - - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - R7 = [ P1 ]; - R0 = [ P2 ]; - CHECKREG r0, 0x20212223; - CHECKREG r3, 0x60616263; - CHECKREG r4, 0x80818283; - CHECKREG r5, 0x00010203; - CHECKREG r7, 0x00010203; - - R4 = [ P5 ]; - R5 = [ FP ]; - R7 = [ P1 ]; - R0 = [ P2 ]; - R2 = [ P4 ]; - CHECKREG r0, 0x20212223; - CHECKREG r2, 0x60616263; - CHECKREG r3, 0x60616263; - CHECKREG r4, 0x80818283; - CHECKREG r5, 0x00010203; - CHECKREG r7, 0x00010203; - - R5 = [ FP ]; - R7 = [ P1 ]; - R0 = [ P2 ]; - R2 = [ P4 ]; - R3 = [ P5 ]; - CHECKREG r0, 0x20212223; - CHECKREG r2, 0x60616263; - CHECKREG r3, 0x80818283; - CHECKREG r4, 0x80818283; - CHECKREG r5, 0x00010203; - CHECKREG r7, 0x00010203; - - R7 = [ P1 ]; - R0 = [ P2 ]; - R2 = [ P4 ]; - R3 = [ P5 ]; - R4 = [ FP ]; - CHECKREG r0, 0x20212223; - CHECKREG r2, 0x60616263; - CHECKREG r3, 0x80818283; - CHECKREG r4, 0x00010203; - CHECKREG r5, 0x00010203; - CHECKREG r7, 0x00010203; - - R7 = [ P1 ]; - R0 = [ P2 ]; - R2 = [ P4 ]; - R3 = [ P5 ]; - R4 = [ FP ]; - CHECKREG r0, 0x20212223; - CHECKREG r2, 0x60616263; - CHECKREG r3, 0x80818283; - CHECKREG r4, 0x00010203; - CHECKREG r6, 0x00010203; - CHECKREG r7, 0x00010203; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_b.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_b.s deleted file mode 100644 index 369bb6d..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_b.s +++ /dev/null @@ -1,353 +0,0 @@ -//Original:/testcases/core/c_ldst_ld_d_p_b/c_ldst_ld_d_p_b.dsp -// Spec Reference: c_ldst ld d [p] b -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym p1, DATA_ADDR_1; - loadsym p2, DATA_ADDR_2; -.ifndef BFIN_HOST - loadsym p3, DATA_ADDR_3; -.endif - loadsym p4, DATA_ADDR_4; - loadsym p5, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - -// load 8 bits from memory, and zero extend into 32-bit reg - R0 = B [ P1 ] (Z); - R1 = B [ P2 ] (Z); -.ifndef BFIN_HOST - R2 = B [ P3 ] (Z); -.else - R2 = 0x43 (Z); -.endif - R3 = B [ P4 ] (Z); - R4 = B [ P5 ] (Z); - R5 = B [ P5 ] (Z); - R6 = B [ FP ] (Z); - CHECKREG r0, 0x00000003; - CHECKREG r1, 0x00000023; - CHECKREG r2, 0x00000043; - CHECKREG r3, 0x00000063; - CHECKREG r4, 0x00000083; - CHECKREG r5, 0x00000083; - CHECKREG r6, 0x00000003; - R1 = B [ P2 ] (Z); -.ifndef BFIN_HOST - R2 = B [ P3 ] (Z); -.else - R2 = 0x43 (Z); -.endif - R3 = B [ P4 ] (Z); - R4 = B [ P5 ] (Z); - R5 = B [ FP ] (Z); - R7 = B [ P1 ] (Z); - CHECKREG r0, 0x00000003; - CHECKREG r1, 0x00000023; - CHECKREG r2, 0x00000043; - CHECKREG r3, 0x00000063; - CHECKREG r4, 0x00000083; - CHECKREG r5, 0x00000003; - CHECKREG r7, 0x00000003; -.ifndef BFIN_HOST - R2 = B [ P3 ] (Z); -.else - R2 = 0x43 (Z); -.endif - R3 = B [ P4 ] (Z); - R4 = B [ P5 ] (Z); - R5 = B [ FP ] (Z); - R7 = B [ P1 ] (Z); - R0 = B [ P2 ] (Z); - CHECKREG r0, 0x00000023; - CHECKREG r1, 0x00000023; - CHECKREG r2, 0x00000043; - CHECKREG r3, 0x00000063; - CHECKREG r4, 0x00000083; - CHECKREG r5, 0x00000003; - CHECKREG r7, 0x00000003; - - R3 = B [ P4 ] (Z); - R4 = B [ P5 ] (Z); - R5 = B [ FP ] (Z); - R7 = B [ P1 ] (Z); - R0 = B [ P2 ] (Z); -.ifndef BFIN_HOST - R1 = B [ P3 ] (Z); -.else - R1 = 0x43; -.endif - CHECKREG r0, 0x00000023; - CHECKREG r1, 0x00000043; - CHECKREG r2, 0x00000043; - CHECKREG r3, 0x00000063; - CHECKREG r4, 0x00000083; - CHECKREG r5, 0x00000003; - CHECKREG r7, 0x00000003; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_h.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_h.s deleted file mode 100644 index fb68de5..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_h.s +++ /dev/null @@ -1,351 +0,0 @@ -//Original:/testcases/core/c_ldst_ld_d_p_h/c_ldst_ld_d_p_h.dsp -// Spec Reference: c_ldst ld d [p] h -# mach: bfin - -.include "testutils.inc" - start - - loadsym p1, DATA_ADDR_1; - loadsym p2, DATA_ADDR_2; -.ifndef BFIN_HOST - loadsym p3, DATA_ADDR_3; -.endif - loadsym p4, DATA_ADDR_4; - loadsym p5, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - -// load 16 bits from memory and zero extend into 32-bit reg - R0 = W [ P1 ] (Z); - R1 = W [ P2 ] (Z); -.ifndef BFIN_HOST - R2 = W [ P3 ] (Z); -.else - R2 = 0x4243(Z); -.endif - R3 = W [ P4 ] (Z); - R4 = W [ P5 ] (Z); - R5 = W [ P5 ] (Z); - R6 = W [ FP ] (Z); - CHECKREG r0, 0x00000203; - CHECKREG r1, 0x00002223; - CHECKREG r2, 0x00004243; - CHECKREG r3, 0x00006263; - CHECKREG r4, 0x00008283; - CHECKREG r5, 0x00008283; - CHECKREG r6, 0x00000203; - R1 = W [ P2 ] (Z); -.ifndef BFIN_HOST - R2 = W [ P3 ] (Z); -.else - R2 = 0x4243 (Z); -.endif - R3 = W [ P4 ] (Z); - R4 = W [ P5 ] (Z); - R5 = W [ FP ] (Z); - R7 = W [ P1 ] (Z); - CHECKREG r0, 0x00000203; - CHECKREG r1, 0x00002223; - CHECKREG r2, 0x00004243; - CHECKREG r3, 0x00006263; - CHECKREG r4, 0x00008283; - CHECKREG r5, 0x00000203; - CHECKREG r7, 0x00000203; -.ifndef BFIN_HOST - R2 = W [ P3 ] (Z); -.else - R2 = 0x4243 (Z); -.endif - R3 = W [ P4 ] (Z); - R4 = W [ P5 ] (Z); - R5 = W [ FP ] (Z); - R7 = W [ P1 ] (Z); - R0 = W [ P2 ] (Z); - CHECKREG r0, 0x00002223; - CHECKREG r1, 0x00002223; - CHECKREG r2, 0x00004243; - CHECKREG r3, 0x00006263; - CHECKREG r4, 0x00008283; - CHECKREG r5, 0x00000203; - CHECKREG r7, 0x00000203; - - R3 = W [ P4 ] (Z); - R4 = W [ P5 ] (Z); - R5 = W [ FP ] (Z); - R7 = W [ P1 ] (Z); - R0 = W [ P2 ] (Z); -.ifndef BFIN_HOST - R1 = W [ P3 ] (Z); -.else - R1 = 0x4243 (Z); -.endif - CHECKREG r0, 0x00002223; - CHECKREG r1, 0x00004243; - CHECKREG r2, 0x00004243; - CHECKREG r3, 0x00006263; - CHECKREG r4, 0x00008283; - CHECKREG r5, 0x00000203; - CHECKREG r7, 0x00000203; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm.s deleted file mode 100644 index 56e49a4..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm.s +++ /dev/null @@ -1,417 +0,0 @@ -//Original:testcases/core/c_ldst_ld_d_p_mm/c_ldst_ld_d_p_mm.dsp -// Spec Reference: c_ldst ld d [p--] -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -INIT_I_REGS -1; -INIT_R_REGS 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x20; - loadsym p1, DATA_ADDR_2, 0x20; - loadsym p2, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym p4, DATA_ADDR_5, 0x20; - loadsym fp, DATA_ADDR_6, 0x20; - loadsym i3, DATA_ADDR_7, 0x20; - P3 = I1; SP = I3; - - R0 = [ P5 -- ]; - R1 = [ P1 -- ]; - R2 = [ P2 -- ]; - R3 = [ P3 -- ]; - R4 = [ P4 -- ]; - R5 = [ FP -- ]; - R6 = [ SP -- ]; - CHECKREG r0, 0x11223344; - CHECKREG r1, 0x91929394; - CHECKREG r2, 0xC9CACBCD; - CHECKREG r3, 0xEBECEDEE; - CHECKREG r4, 0x0F101213; - CHECKREG r5, 0x20212223; - CHECKREG r6, 0xA0A1A2A3; - R1 = [ P5 -- ]; - R2 = [ P1 -- ]; - R3 = [ P2 -- ]; - R4 = [ P3 -- ]; - R5 = [ P4 -- ]; - R6 = [ FP -- ]; - R7 = [ SP -- ]; - CHECKREG r0, 0x11223344; - CHECKREG r1, 0x1C1D1E1F; - CHECKREG r2, 0x3C3D3E3F; - CHECKREG r3, 0xC5C6C7C8; - CHECKREG r4, 0x7C7D7E7F; - CHECKREG r5, 0x9C9D9E9F; - CHECKREG r6, 0x1C1D1E1F; - CHECKREG r7, 0x9C9D9E9F; - R2 = [ P5 -- ]; - R3 = [ P1 -- ]; - R4 = [ P2 -- ]; - R5 = [ P3 -- ]; - R6 = [ P4 -- ]; - R7 = [ FP -- ]; - R0 = [ SP -- ]; - CHECKREG r0, 0x98999A9B; - CHECKREG r1, 0x1C1D1E1F; - CHECKREG r2, 0x18191A1B; - CHECKREG r3, 0x38393A3B; - CHECKREG r4, 0x58595A5B; - CHECKREG r5, 0x78797A7B; - CHECKREG r6, 0x98999A9B; - CHECKREG r7, 0x18191A1B; - - R3 = [ P5 -- ]; - R4 = [ P1 -- ]; - R5 = [ P2 -- ]; - R6 = [ P3 -- ]; - R7 = [ P4 -- ]; - R0 = [ FP -- ]; - R1 = [ SP -- ]; - CHECKREG r0, 0x14151617; - CHECKREG r1, 0x94959697; - CHECKREG r2, 0x18191A1B; - CHECKREG r3, 0x14151617; - CHECKREG r4, 0x34353637; - CHECKREG r5, 0x54555657; - CHECKREG r6, 0x74757677; - CHECKREG r7, 0x94959697; - - R4 = [ P5 -- ]; - R5 = [ P1 -- ]; - R6 = [ P2 -- ]; - R7 = [ P3 -- ]; - R0 = [ P4 -- ]; - R1 = [ FP -- ]; - R2 = [ SP -- ]; - CHECKREG r0, 0x90919293; - CHECKREG r1, 0x10111213; - CHECKREG r2, 0x90919293; - CHECKREG r3, 0x14151617; - CHECKREG r4, 0x10111213; - CHECKREG r5, 0x30313233; - CHECKREG r6, 0x50515253; - CHECKREG r7, 0x70717273; - - R5 = [ P5 -- ]; - R6 = [ P1 -- ]; - R7 = [ P2 -- ]; - R0 = [ P3 -- ]; - R1 = [ P4 -- ]; - R2 = [ FP -- ]; - R3 = [ SP -- ]; - CHECKREG r0, 0x6C6D6E6F; - CHECKREG r1, 0x8C8D8E8F; - CHECKREG r2, 0x0C0D0E0F; - CHECKREG r3, 0x8C8D8E8F; - CHECKREG r4, 0x10111213; - CHECKREG r5, 0x0C0D0E0F; - CHECKREG r6, 0x2C2D2E2F; - CHECKREG r7, 0x4C4D4E4F; - - R6 = [ P5 -- ]; - R7 = [ P1 -- ]; - R0 = [ P2 -- ]; - R1 = [ P3 -- ]; - R2 = [ P4 -- ]; - R3 = [ FP -- ]; - R4 = [ SP -- ]; - CHECKREG r0, 0x48494A4B; - CHECKREG r1, 0x68696A6B; - CHECKREG r2, 0x88898A8B; - CHECKREG r3, 0x08090A0B; - CHECKREG r4, 0x88898A8B; - CHECKREG r5, 0x0C0D0E0F; - CHECKREG r6, 0x08090A0B; - CHECKREG r7, 0x28292A2B; - - R7 = [ P5 -- ]; - R0 = [ P1 -- ]; - R1 = [ P2 -- ]; - R2 = [ P3 -- ]; - R3 = [ P4 -- ]; - R4 = [ FP -- ]; - R5 = [ SP -- ]; - CHECKREG r0, 0x24252627; - CHECKREG r1, 0x44454647; - CHECKREG r2, 0x64656667; - CHECKREG r3, 0x84858687; - CHECKREG r4, 0x04050607; - CHECKREG r5, 0x84858687; - CHECKREG r6, 0x08090A0B; - CHECKREG r7, 0x04050607; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_b.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_b.s deleted file mode 100644 index f571553..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_b.s +++ /dev/null @@ -1,353 +0,0 @@ -//Original:testcases/core/c_ldst_ld_d_p_mm_b/c_ldst_ld_d_p_mm_b.dsp -// Spec Reference: c_ldst ld d [p--] b -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -INIT_I_REGS -1; -INIT_R_REGS 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x14; - loadsym p1, DATA_ADDR_2, 0x14; - loadsym p2, DATA_ADDR_3, 0x14; - loadsym i1, DATA_ADDR_4, 0x14; - loadsym p4, DATA_ADDR_5, 0x14; - loadsym fp, DATA_ADDR_6, 0x14; - loadsym i3, DATA_ADDR_7, 0x14; - P3 = I1; SP = I3; - - R0 = B [ P5 -- ] (Z); - R1 = B [ P1 -- ] (Z); - R2 = B [ P2 -- ] (Z); - R3 = B [ P3 -- ] (Z); - R4 = B [ P4 -- ] (Z); - R5 = B [ FP -- ] (Z); - R6 = B [ SP -- ] (Z); - CHECKREG r0, 0x00000017; - CHECKREG r1, 0x00000037; - CHECKREG r2, 0x00000057; - CHECKREG r3, 0x00000077; - CHECKREG r4, 0x00000097; - CHECKREG r5, 0x00000017; - CHECKREG r6, 0x00000097; - R1 = B [ P5 -- ] (Z); - R2 = B [ P1 -- ] (Z); - R3 = B [ P2 -- ] (Z); - R4 = B [ P3 -- ] (Z); - R5 = B [ P4 -- ] (Z); - R6 = B [ FP -- ] (Z); - R7 = B [ SP -- ] (Z); - CHECKREG r0, 0x00000017; - CHECKREG r1, 0x00000010; - CHECKREG r2, 0x00000030; - CHECKREG r3, 0x00000050; - CHECKREG r4, 0x00000070; - CHECKREG r5, 0x00000090; - CHECKREG r6, 0x00000010; - CHECKREG r7, 0x00000090; - R2 = B [ P5 -- ] (Z); - R3 = B [ P1 -- ] (Z); - R4 = B [ P2 -- ] (Z); - R5 = B [ P3 -- ] (Z); - R6 = B [ P4 -- ] (Z); - R7 = B [ FP -- ] (Z); - R0 = B [ SP -- ] (Z); - CHECKREG r0, 0x00000091; - CHECKREG r1, 0x00000010; - CHECKREG r2, 0x00000011; - CHECKREG r3, 0x00000031; - CHECKREG r4, 0x00000051; - CHECKREG r5, 0x00000071; - CHECKREG r6, 0x00000091; - CHECKREG r7, 0x00000011; - - R3 = B [ P5 -- ] (Z); - R4 = B [ P1 -- ] (Z); - R5 = B [ P2 -- ] (Z); - R6 = B [ P3 -- ] (Z); - R7 = B [ P4 -- ] (Z); - R0 = B [ FP -- ] (Z); - R1 = B [ SP -- ] (Z); - CHECKREG r0, 0x00000012; - CHECKREG r1, 0x00000092; - CHECKREG r2, 0x00000011; - CHECKREG r3, 0x00000012; - CHECKREG r4, 0x00000032; - CHECKREG r5, 0x00000052; - CHECKREG r6, 0x00000072; - CHECKREG r7, 0x00000092; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_h.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_h.s deleted file mode 100644 index 207f93a..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_h.s +++ /dev/null @@ -1,330 +0,0 @@ -//Original:testcases/core/c_ldst_ld_d_p_mm_h/c_ldst_ld_d_p_mm_h.dsp -// Spec Reference: c_ldst ld d [p--] h -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -INIT_I_REGS -1; -INIT_R_REGS 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; - -// initial values - loadsym p5, DATA_ADDR_1, 0x10; - loadsym p1, DATA_ADDR_2, 0x10; - loadsym p2, DATA_ADDR_3, 0x10; - loadsym p4, DATA_ADDR_5, 0x10; - loadsym fp, DATA_ADDR_6, 0x10; - - R0 = W [ P5 -- ] (Z); - R1 = W [ P1 -- ] (Z); - R2 = W [ P2 -- ] (Z); - R4 = W [ P4 -- ] (Z); - R5 = W [ FP -- ] (Z); - CHECKREG r0, 0x00001213; - CHECKREG r1, 0x00003233; - CHECKREG r2, 0x00005253; - CHECKREG r4, 0x00009293; - CHECKREG r5, 0x00001213; - R1 = W [ P5 -- ] (Z); - R2 = W [ P1 -- ] (Z); - R3 = W [ P2 -- ] (Z); - R5 = W [ P4 -- ] (Z); - R6 = W [ FP -- ] (Z); - CHECKREG r0, 0x00001213; - CHECKREG r1, 0x00000C0D; - CHECKREG r2, 0x00002C2D; - CHECKREG r3, 0x00004C4D; - CHECKREG r5, 0x00008C8D; - CHECKREG r6, 0x00000C0D; - R2 = W [ P5 -- ] (Z); - R3 = W [ P1 -- ] (Z); - R4 = W [ P2 -- ] (Z); - R6 = W [ P4 -- ] (Z); - R7 = W [ FP -- ] (Z); - CHECKREG r1, 0x00000C0D; - CHECKREG r2, 0x00000E0F; - CHECKREG r3, 0x00002E2F; - CHECKREG r4, 0x00004E4F; - CHECKREG r6, 0x00008E8F; - CHECKREG r7, 0x00000E0F; - - R3 = W [ P5 -- ] (Z); - R4 = W [ P1 -- ] (Z); - R5 = W [ P2 -- ] (Z); - R7 = W [ P4 -- ] (Z); - R0 = W [ FP -- ] (Z); - CHECKREG r0, 0x00000809; - CHECKREG r2, 0x00000E0F; - CHECKREG r3, 0x00000809; - CHECKREG r4, 0x00002829; - CHECKREG r5, 0x00004849; - CHECKREG r7, 0x00008889; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xb.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xb.s deleted file mode 100644 index e545ca8..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xb.s +++ /dev/null @@ -1,341 +0,0 @@ -//Original:testcases/core/c_ldst_ld_d_p_mm_xb/c_ldst_ld_d_p_mm_xb.dsp -// Spec Reference: c_ldst ld d [p--] xb - -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -INIT_I_REGS -1; -INIT_R_REGS 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x20; - loadsym p1, DATA_ADDR_2, 0x20; - loadsym p2, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym p4, DATA_ADDR_5, 0x20; - loadsym fp, DATA_ADDR_6, 0x20; - loadsym i3, DATA_ADDR_7, 0x20; - P3 = I1; SP = I3; - - R5 = B [ P5 -- ] (X); - R6 = B [ P1 -- ] (X); - R7 = B [ P2 -- ] (X); - R0 = B [ P3 -- ] (X); - R1 = B [ P4 -- ] (X); - R2 = B [ FP -- ] (X); - R3 = B [ SP -- ] (X); - CHECKREG r0, 0xFFFFFFEE; - CHECKREG r1, 0x00000013; - CHECKREG r2, 0x00000023; - CHECKREG r3, 0xFFFFFFA3; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000044; - CHECKREG r6, 0xFFFFFF94; - CHECKREG r7, 0xFFFFFFCD; - - R6 = B [ P5 -- ] (X); - R7 = B [ P1 -- ] (X); - R0 = B [ P2 -- ] (X); - R1 = B [ P3 -- ] (X); - R2 = B [ P4 -- ] (X); - R3 = B [ FP -- ] (X); - R4 = B [ SP -- ] (X); - CHECKREG r0, 0xFFFFFFC5; - CHECKREG r1, 0x0000007C; - CHECKREG r2, 0xFFFFFF9C; - CHECKREG r3, 0x0000001C; - CHECKREG r4, 0xFFFFFF9C; - CHECKREG r5, 0x00000044; - CHECKREG r6, 0x0000001C; - CHECKREG r7, 0x0000003C; - - R7 = B [ P5 -- ] (X); - R0 = B [ P1 -- ] (X); - R1 = B [ P2 -- ] (X); - R2 = B [ P3 -- ] (X); - R3 = B [ P4 -- ] (X); - R4 = B [ FP -- ] (X); - R5 = B [ SP -- ] (X); - CHECKREG r0, 0x0000003D; - CHECKREG r1, 0xFFFFFFC6; - CHECKREG r2, 0x0000007D; - CHECKREG r3, 0xFFFFFF9D; - CHECKREG r4, 0x0000001D; - CHECKREG r5, 0xFFFFFF9D; - CHECKREG r6, 0x0000001C; - CHECKREG r7, 0x0000001D; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xh.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xh.s deleted file mode 100644 index 16676a5..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xh.s +++ /dev/null @@ -1,355 +0,0 @@ -//Original:testcases/core/c_ldst_ld_d_p_mm_xh/c_ldst_ld_d_p_mm_xh.dsp -// Spec Reference: c_ldst ld d [p++/--] h b xh xb -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -INIT_I_REGS -1; -INIT_R_REGS 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x08; - loadsym p1, DATA_ADDR_2, 0x08; - loadsym p2, DATA_ADDR_3, 0x08; - loadsym i1, DATA_ADDR_4, 0x08; - loadsym p4, DATA_ADDR_5, 0x08; - loadsym fp, DATA_ADDR_6, 0x08; - loadsym i3, DATA_ADDR_7, 0x08; - P3 = I1; SP = I3; - - R4 = W [ P5 -- ] (X); - R5 = W [ P1 -- ] (X); - R6 = W [ P2 -- ] (X); - R7 = W [ P3 -- ] (X); - R0 = W [ P4 -- ] (X); - R1 = W [ FP -- ] (X); - R2 = W [ SP -- ] (X); - CHECKREG r0, 0xFFFF8A8B; - CHECKREG r1, 0x00000A0B; - CHECKREG r2, 0xFFFF8A8B; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00002A2B; - CHECKREG r6, 0x00004A4B; - CHECKREG r7, 0x00006A6B; - - R5 = W [ P5 -- ] (X); - R6 = W [ P1 -- ] (X); - R7 = W [ P2 -- ] (X); - R0 = W [ P3 -- ] (X); - R1 = W [ P4 -- ] (X); - R2 = W [ FP -- ] (X); - R3 = W [ SP -- ] (X); - CHECKREG r0, 0x00006465; - CHECKREG r1, 0xFFFF8485; - CHECKREG r2, 0x00000405; - CHECKREG r3, 0xFFFF8485; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00000405; - CHECKREG r6, 0x00002425; - CHECKREG r7, 0x00004445; - - R6 = W [ P5 -- ] (X); - R7 = W [ P1 -- ] (X); - R0 = W [ P2 -- ] (X); - R1 = W [ P3 -- ] (X); - R2 = W [ P4 -- ] (X); - R3 = W [ FP -- ] (X); - R4 = W [ SP -- ] (X); - CHECKREG r0, 0x00004647; - CHECKREG r1, 0x00006667; - CHECKREG r2, 0xFFFF8687; - CHECKREG r3, 0x00000607; - CHECKREG r4, 0xFFFF8687; - CHECKREG r5, 0x00000405; - CHECKREG r6, 0x00000607; - CHECKREG r7, 0x00002627; - - R7 = W [ P5 -- ] (X); - R0 = W [ P1 -- ] (X); - R1 = W [ P2 -- ] (X); - R2 = W [ P3 -- ] (X); - R3 = W [ P4 -- ] (X); - R4 = W [ FP -- ] (X); - R5 = W [ SP -- ] (X); - CHECKREG r0, 0x00002021; - CHECKREG r1, 0x00004041; - CHECKREG r2, 0x00006061; - CHECKREG r3, 0xFFFF8081; - CHECKREG r4, 0x00000001; - CHECKREG r5, 0xFFFF8081; - CHECKREG r6, 0x00000607; - CHECKREG r7, 0x00000001; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp.s deleted file mode 100644 index c03ed68..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp.s +++ /dev/null @@ -1,371 +0,0 @@ -//Original:/testcases/core/c_ldst_ld_d_p_pp/c_ldst_ld_d_p_pp.dsp -// Spec Reference: c_ldst ld d [p++] -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - R0 = [ P5 ++ ]; - R1 = [ P1 ++ ]; - R2 = [ P2 ++ ]; - R4 = [ P4 ++ ]; - R5 = [ FP ++ ]; - CHECKREG r0, 0x00010203; - CHECKREG r1, 0x20212223; - CHECKREG r2, 0x40414243; - CHECKREG r4, 0x80818283; - CHECKREG r5, 0x00010203; - R1 = [ P5 ++ ]; - R2 = [ P1 ++ ]; - R3 = [ P2 ++ ]; - R5 = [ P4 ++ ]; - R6 = [ FP ++ ]; - CHECKREG r0, 0x00010203; - CHECKREG r1, 0x04050607; - CHECKREG r2, 0x24252627; - CHECKREG r3, 0x44454647; - CHECKREG r5, 0x84858687; - CHECKREG r6, 0x04050607; - R2 = [ P5 ++ ]; - R3 = [ P1 ++ ]; - R4 = [ P2 ++ ]; - R6 = [ P4 ++ ]; - R7 = [ FP ++ ]; - CHECKREG r1, 0x04050607; - CHECKREG r2, 0x08090A0B; - CHECKREG r3, 0x28292A2B; - CHECKREG r4, 0x48494A4B; - CHECKREG r6, 0x88898A8B; - CHECKREG r7, 0x08090A0B; - - R3 = [ P5 ++ ]; - R4 = [ P1 ++ ]; - R5 = [ P2 ++ ]; - R7 = [ P4 ++ ]; - R0 = [ FP ++ ]; - CHECKREG r0, 0x0C0D0E0F; - CHECKREG r2, 0x08090A0B; - CHECKREG r3, 0x0C0D0E0F; - CHECKREG r4, 0x2C2D2E2F; - CHECKREG r5, 0x4C4D4E4F; - CHECKREG r7, 0x8C8D8E8F; - - R4 = [ P5 ++ ]; - R5 = [ P1 ++ ]; - R6 = [ P2 ++ ]; - R0 = [ P4 ++ ]; - R1 = [ FP ++ ]; - CHECKREG r0, 0x90919293; - CHECKREG r1, 0x10111213; - CHECKREG r3, 0x0C0D0E0F; - CHECKREG r4, 0x10111213; - CHECKREG r5, 0x30313233; - CHECKREG r6, 0x50515253; - - R5 = [ P5 ++ ]; - R6 = [ P1 ++ ]; - R7 = [ P2 ++ ]; - R1 = [ P4 ++ ]; - R2 = [ FP ++ ]; - CHECKREG r1, 0x94959697; - CHECKREG r2, 0x14151617; - CHECKREG r4, 0x10111213; - CHECKREG r5, 0x14151617; - CHECKREG r6, 0x34353637; - CHECKREG r7, 0x54555657; - - R6 = [ P5 ++ ]; - R7 = [ P1 ++ ]; - R0 = [ P2 ++ ]; - R2 = [ P4 ++ ]; - R3 = [ FP ++ ]; - CHECKREG r0, 0x58595A5B; - CHECKREG r2, 0x98999A9B; - CHECKREG r3, 0x18191A1B; - CHECKREG r5, 0x14151617; - CHECKREG r6, 0x18191A1B; - CHECKREG r7, 0x38393A3B; - - R7 = [ P5 ++ ]; - R0 = [ P1 ++ ]; - R1 = [ P2 ++ ]; - R3 = [ P4 ++ ]; - R4 = [ FP ++ ]; - CHECKREG r0, 0x3C3D3E3F; - CHECKREG r1, 0xC5C6C7C8; - CHECKREG r3, 0x9C9D9E9F; - CHECKREG r4, 0x1C1D1E1F; - CHECKREG r6, 0x18191A1B; - CHECKREG r7, 0x1C1D1E1F; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_b.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_b.s deleted file mode 100644 index 492ef3c..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_b.s +++ /dev/null @@ -1,324 +0,0 @@ -//Original:/testcases/core/c_ldst_ld_d_p_pp_b/c_ldst_ld_d_p_pp_b.dsp -// Spec Reference: c_ldst ld d [p++] b -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - R0 = B [ P5 ++ ] (Z); - R1 = B [ P1 ++ ] (Z); - R2 = B [ P2 ++ ] (Z); - R4 = B [ P4 ++ ] (Z); - R5 = B [ FP ++ ] (Z); - - CHECKREG r0, 0x00000003; - CHECKREG r1, 0x00000023; - CHECKREG r2, 0x00000043; - CHECKREG r4, 0x00000083; - CHECKREG r5, 0x00000003; - R1 = B [ P5 ++ ] (Z); - R2 = B [ P1 ++ ] (Z); - R3 = B [ P2 ++ ] (Z); - R5 = B [ P4 ++ ] (Z); - R6 = B [ FP ++ ] (Z); - CHECKREG r0, 0x00000003; - CHECKREG r1, 0x00000002; - CHECKREG r2, 0x00000022; - CHECKREG r3, 0x00000042; - CHECKREG r5, 0x00000082; - CHECKREG r6, 0x00000002; - R2 = B [ P5 ++ ] (Z); - R3 = B [ P1 ++ ] (Z); - R4 = B [ P2 ++ ] (Z); - R6 = B [ P4 ++ ] (Z); - R7 = B [ FP ++ ] (Z); - CHECKREG r1, 0x00000002; - CHECKREG r2, 0x00000001; - CHECKREG r3, 0x00000021; - CHECKREG r4, 0x00000041; - CHECKREG r6, 0x00000081; - CHECKREG r7, 0x00000001; - - R3 = B [ P5 ++ ] (Z); - R4 = B [ P1 ++ ] (Z); - R5 = B [ P2 ++ ] (Z); - R7 = B [ P4 ++ ] (Z); - R0 = B [ FP ++ ] (Z); - CHECKREG r0, 0x00000000; - CHECKREG r2, 0x00000001; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000020; - CHECKREG r5, 0x00000040; - CHECKREG r7, 0x00000080; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_h.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_h.s deleted file mode 100644 index b5bd84f..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_h.s +++ /dev/null @@ -1,350 +0,0 @@ -//Original:/testcases/core/c_ldst_ld_d_p_pp_h/c_ldst_ld_d_p_pp_h.dsp -// Spec Reference: c_ldst ld d [p++] h -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; -.ifndef BFIN_HOST - loadsym p3, DATA_ADDR_4; -.endif - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - R0 = W [ P5 ++ ] (Z); - R1 = W [ P1 ++ ] (Z); - R2 = W [ P2 ++ ] (Z); -.ifndef BFIN_HOST - R3 = W [ P3 ++ ] (Z); -.endif - R4 = W [ P4 ++ ] (Z); - R5 = W [ FP ++ ] (Z); - CHECKREG r0, 0x00000203; - CHECKREG r1, 0x00002223; - CHECKREG r2, 0x00004243; -.ifndef BFIN_HOST - CHECKREG r3, 0x00006263; -.endif - CHECKREG r4, 0x00008283; - CHECKREG r5, 0x00000203; - R1 = W [ P5 ++ ] (Z); - R2 = W [ P1 ++ ] (Z); - R3 = W [ P2 ++ ] (Z); -.ifndef BFIN_HOST - R4 = W [ P3 ++ ] (Z); -.endif - R5 = W [ P4 ++ ] (Z); - R6 = W [ FP ++ ] (Z); - CHECKREG r0, 0x00000203; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00002021; - CHECKREG r3, 0x00004041; -.ifndef BFIN_HOST - CHECKREG r4, 0x00006061; -.endif - CHECKREG r5, 0x00008081; - CHECKREG r6, 0x00000001; - R2 = W [ P5 ++ ] (Z); - R3 = W [ P1 ++ ] (Z); - R4 = W [ P2 ++ ] (Z); -.ifndef BFIN_HOST - R5 = W [ P3 ++ ] (Z); -.endif - R6 = W [ P4 ++ ] (Z); - R7 = W [ FP ++ ] (Z); - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00000607; - CHECKREG r3, 0x00002627; - CHECKREG r4, 0x00004647; -.ifndef BFIN_HOST - CHECKREG r5, 0x00006667; -.endif - CHECKREG r6, 0x00008687; - CHECKREG r7, 0x00000607; - - R3 = W [ P5 ++ ] (Z); - R4 = W [ P1 ++ ] (Z); - R5 = W [ P2 ++ ] (Z); -.ifndef BFIN_HOST - R6 = W [ P3 ++ ] (Z); -.endif - R7 = W [ P4 ++ ] (Z); - R0 = W [ FP ++ ] (Z); - CHECKREG r0, 0x00000405; - CHECKREG r2, 0x00000607; - CHECKREG r3, 0x00000405; - CHECKREG r4, 0x00002425; -.ifndef BFIN_HOST - CHECKREG r5, 0x00004445; - CHECKREG r6, 0x00006465; -.endif - CHECKREG r7, 0x00008485; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xb.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xb.s deleted file mode 100644 index 834508b..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xb.s +++ /dev/null @@ -1,355 +0,0 @@ -//Original:testcases/core/c_ldst_ld_d_p_pp_xb/c_ldst_ld_d_p_pp_xb.dsp -// Spec Reference: c_ldst ld d [p++] xb -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -INIT_I_REGS -1; -INIT_R_REGS 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x04; - loadsym p1, DATA_ADDR_2, 0x04; - loadsym p2, DATA_ADDR_3, 0x04; - loadsym i1, DATA_ADDR_4, 0x04; - loadsym p4, DATA_ADDR_5, 0x04; - loadsym fp, DATA_ADDR_6, 0x04; - loadsym i3, DATA_ADDR_7, 0x04; - P3 = I1; SP = I3; - - R4 = B [ P5 ++ ] (X); - R5 = B [ P1 ++ ] (X); - R6 = B [ P2 ++ ] (X); - R7 = B [ P3 ++ ] (X); - R0 = B [ P4 ++ ] (X); - R1 = B [ FP ++ ] (X); - R2 = B [ SP ++ ] (X); - CHECKREG r0, 0xFFFFFF87; - CHECKREG r1, 0x00000007; - CHECKREG r2, 0xFFFFFF87; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000007; - CHECKREG r5, 0x00000027; - CHECKREG r6, 0x00000047; - CHECKREG r7, 0x00000067; - - R5 = B [ P5 ++ ] (X); - R6 = B [ P1 ++ ] (X); - R7 = B [ P2 ++ ] (X); - R0 = B [ P3 ++ ] (X); - R1 = B [ P4 ++ ] (X); - R2 = B [ FP ++ ] (X); - R3 = B [ SP ++ ] (X); - CHECKREG r0, 0x00000066; - CHECKREG r1, 0xFFFFFF86; - CHECKREG r2, 0x00000006; - CHECKREG r3, 0xFFFFFF86; - CHECKREG r4, 0x00000007; - CHECKREG r5, 0x00000006; - CHECKREG r6, 0x00000026; - CHECKREG r7, 0x00000046; - - R6 = B [ P5 ++ ] (X); - R7 = B [ P1 ++ ] (X); - R0 = B [ P2 ++ ] (X); - R1 = B [ P3 ++ ] (X); - R2 = B [ P4 ++ ] (X); - R3 = B [ FP ++ ] (X); - R4 = B [ SP ++ ] (X); - CHECKREG r0, 0x00000045; - CHECKREG r1, 0x00000065; - CHECKREG r2, 0xFFFFFF85; - CHECKREG r3, 0x00000005; - CHECKREG r4, 0xFFFFFF85; - CHECKREG r5, 0x00000006; - CHECKREG r6, 0x00000005; - CHECKREG r7, 0x00000025; - - R7 = B [ P5 ++ ] (X); - R0 = B [ P1 ++ ] (X); - R1 = B [ P2 ++ ] (X); - R2 = B [ P3 ++ ] (X); - R3 = B [ P4 ++ ] (X); - R4 = B [ FP ++ ] (X); - R5 = B [ SP ++ ] (X); - CHECKREG r0, 0x00000024; - CHECKREG r1, 0x00000044; - CHECKREG r2, 0x00000064; - CHECKREG r3, 0xFFFFFF84; - CHECKREG r4, 0x00000004; - CHECKREG r5, 0xFFFFFF84; - CHECKREG r6, 0x00000005; - CHECKREG r7, 0x00000004; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xh.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xh.s deleted file mode 100644 index bab5d78..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xh.s +++ /dev/null @@ -1,333 +0,0 @@ -//Original:testcases/core/c_ldst_ld_d_p_pp_xh/c_ldst_ld_d_p_pp_xh.dsp -// Spec Reference: c_ldst ld d [p++] xh -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -INIT_I_REGS -1; -INIT_R_REGS 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; - -// initial values - loadsym p5, DATA_ADDR_1, 0x08; - loadsym p1, DATA_ADDR_2, 0x08; - loadsym p2, DATA_ADDR_3, 0x08; - loadsym p4, DATA_ADDR_5, 0x08; - loadsym fp, DATA_ADDR_6, 0x08; - - R4 = W [ P5 ++ ] (X); - R5 = W [ P1 ++ ] (X); - R6 = W [ P2 ++ ] (X); - R0 = W [ P4 ++ ] (X); - R1 = W [ FP ++ ] (X); - CHECKREG r0, 0xFFFF8A8B; - CHECKREG r1, 0x00000A0B; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00002A2B; - CHECKREG r6, 0x00004A4B; - - R5 = W [ P5 ++ ] (X); - R6 = W [ P1 ++ ] (X); - R7 = W [ P2 ++ ] (X); - R1 = W [ P4 ++ ] (X); - R2 = W [ FP ++ ] (X); - CHECKREG r1, 0xFFFF8889; - CHECKREG r2, 0x00000809; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00000809; - CHECKREG r6, 0x00002829; - CHECKREG r7, 0x00004849; - - R6 = W [ P5 ++ ] (X); - R7 = W [ P1 ++ ] (X); - R0 = W [ P2 ++ ] (X); - R2 = W [ P4 ++ ] (X); - R3 = W [ FP ++ ] (X); - CHECKREG r0, 0x00004E4F; - CHECKREG r2, 0xFFFF8E8F; - CHECKREG r3, 0x00000E0F; - CHECKREG r5, 0x00000809; - CHECKREG r6, 0x00000E0F; - CHECKREG r7, 0x00002E2F; - - R7 = W [ P5 ++ ] (X); - R0 = W [ P1 ++ ] (X); - R1 = W [ P2 ++ ] (X); - R3 = W [ P4 ++ ] (X); - R4 = W [ FP ++ ] (X); - CHECKREG r0, 0x00002C2D; - CHECKREG r1, 0x00004C4D; - CHECKREG r3, 0xFFFF8C8D; - CHECKREG r4, 0x00000C0D; - CHECKREG r6, 0x00000E0F; - CHECKREG r7, 0x00000C0D; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_ppmm_hbx.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_ppmm_hbx.s deleted file mode 100644 index f782e83..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_ppmm_hbx.s +++ /dev/null @@ -1,656 +0,0 @@ -//Original:/testcases/core/c_ldst_ld_d_p_ppmm_hbx/c_ldst_ld_d_p_ppmm_hbx.dsp -// Spec Reference: c_ldst ld d [p++/--] h b xh xb -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - R0 = W [ P5 ++ ] (Z); - R1 = W [ P1 ++ ] (Z); - R2 = W [ P2 ++ ] (Z); - R4 = W [ P4 ++ ] (Z); - R5 = W [ FP ++ ] (Z); - CHECKREG r0, 0x00000203; - CHECKREG r1, 0x00002223; - CHECKREG r2, 0x00004243; - CHECKREG r4, 0x00008283; - CHECKREG r5, 0x00000203; - R1 = W [ P5 ++ ] (Z); - R2 = W [ P1 ++ ] (Z); - R3 = W [ P2 ++ ] (Z); - R5 = W [ P4 ++ ] (Z); - R6 = W [ FP ++ ] (Z); - CHECKREG r0, 0x00000203; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00002021; - CHECKREG r3, 0x00004041; - CHECKREG r5, 0x00008081; - CHECKREG r6, 0x00000001; - R2 = W [ P5 ++ ] (Z); - R3 = W [ P1 ++ ] (Z); - R4 = W [ P2 ++ ] (Z); - R6 = W [ P4 ++ ] (Z); - R7 = W [ FP ++ ] (Z); - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00000607; - CHECKREG r3, 0x00002627; - CHECKREG r4, 0x00004647; - CHECKREG r6, 0x00008687; - CHECKREG r7, 0x00000607; - - R3 = W [ P5 ++ ] (Z); - R4 = W [ P1 ++ ] (Z); - R5 = W [ P2 ++ ] (Z); - R7 = W [ P4 ++ ] (Z); - R0 = W [ FP ++ ] (Z); - CHECKREG r0, 0x00000405; - CHECKREG r2, 0x00000607; - CHECKREG r3, 0x00000405; - CHECKREG r4, 0x00002425; - CHECKREG r5, 0x00004445; - CHECKREG r7, 0x00008485; - - R4 = W [ P5 ++ ] (X); - R5 = W [ P1 ++ ] (X); - R6 = W [ P2 ++ ] (X); - R0 = W [ P4 ++ ] (X); - R1 = W [ FP ++ ] (X); - CHECKREG r0, 0xFFFF8A8B; - CHECKREG r1, 0x00000A0B; - CHECKREG r3, 0x00000405; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00002A2B; - CHECKREG r6, 0x00004A4B; - - R5 = W [ P5 ++ ] (X); - R6 = W [ P1 ++ ] (X); - R7 = W [ P2 ++ ] (X); - R1 = W [ P4 ++ ] (X); - R2 = W [ FP ++ ] (X); - CHECKREG r1, 0xFFFF8889; - CHECKREG r2, 0x00000809; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00000809; - CHECKREG r6, 0x00002829; - CHECKREG r7, 0x00004849; - - R6 = W [ P5 ++ ] (X); - R7 = W [ P1 ++ ] (X); - R0 = W [ P2 ++ ] (X); - R2 = W [ P4 ++ ] (X); - R3 = W [ FP ++ ] (X); - CHECKREG r0, 0x00004E4F; - CHECKREG r2, 0xFFFF8E8F; - CHECKREG r3, 0x00000E0F; - CHECKREG r5, 0x00000809; - CHECKREG r6, 0x00000E0F; - CHECKREG r7, 0x00002E2F; - - R7 = W [ P5 ++ ] (X); - R0 = W [ P1 ++ ] (X); - R1 = W [ P2 ++ ] (X); - R3 = W [ P4 ++ ] (X); - R4 = W [ FP ++ ] (X); - CHECKREG r0, 0x00002C2D; - CHECKREG r1, 0x00004C4D; - CHECKREG r3, 0xFFFF8C8D; - CHECKREG r4, 0x00000C0D; - CHECKREG r6, 0x00000E0F; - CHECKREG r7, 0x00000C0D; - - R0 = W [ P5 -- ] (Z); - R1 = W [ P1 -- ] (Z); - R2 = W [ P2 -- ] (Z); - R4 = W [ P4 -- ] (Z); - R5 = W [ FP -- ] (Z); - CHECKREG r0, 0x00001213; - CHECKREG r1, 0x00003233; - CHECKREG r2, 0x00005253; - CHECKREG r4, 0x00009293; - CHECKREG r5, 0x00001213; - R1 = W [ P5 -- ] (Z); - R2 = W [ P1 -- ] (Z); - R3 = W [ P2 -- ] (Z); - R5 = W [ P4 -- ] (Z); - R6 = W [ FP -- ] (Z); - CHECKREG r0, 0x00001213; - CHECKREG r1, 0x00000C0D; - CHECKREG r2, 0x00002C2D; - CHECKREG r3, 0x00004C4D; - CHECKREG r5, 0x00008C8D; - CHECKREG r6, 0x00000C0D; - R2 = W [ P5 -- ] (Z); - R3 = W [ P1 -- ] (Z); - R4 = W [ P2 -- ] (Z); - R6 = W [ P4 -- ] (Z); - R7 = W [ FP -- ] (Z); - CHECKREG r1, 0x00000C0D; - CHECKREG r2, 0x00000E0F; - CHECKREG r3, 0x00002E2F; - CHECKREG r4, 0x00004E4F; - CHECKREG r6, 0x00008E8F; - CHECKREG r7, 0x00000E0F; - - R3 = W [ P5 -- ] (Z); - R4 = W [ P1 -- ] (Z); - R5 = W [ P2 -- ] (Z); - R7 = W [ P4 -- ] (Z); - R0 = W [ FP -- ] (Z); - CHECKREG r0, 0x00000809; - CHECKREG r2, 0x00000E0F; - CHECKREG r3, 0x00000809; - CHECKREG r4, 0x00002829; - CHECKREG r5, 0x00004849; - CHECKREG r7, 0x00008889; - - R4 = W [ P5 -- ] (X); - R5 = W [ P1 -- ] (X); - R6 = W [ P2 -- ] (X); - R0 = W [ P4 -- ] (X); - R1 = W [ FP -- ] (X); - CHECKREG r0, 0xFFFF8A8B; - CHECKREG r1, 0x00000A0B; - CHECKREG r3, 0x00000809; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00002A2B; - CHECKREG r6, 0x00004A4B; - - R5 = W [ P5 -- ] (X); - R6 = W [ P1 -- ] (X); - R7 = W [ P2 -- ] (X); - R1 = W [ P4 -- ] (X); - R2 = W [ FP -- ] (X); - CHECKREG r1, 0xFFFF8485; - CHECKREG r2, 0x00000405; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00000405; - CHECKREG r6, 0x00002425; - CHECKREG r7, 0x00004445; - - R6 = W [ P5 -- ] (X); - R7 = W [ P1 -- ] (X); - R0 = W [ P2 -- ] (X); - R2 = W [ P4 -- ] (X); - R3 = W [ FP -- ] (X); - CHECKREG r0, 0x00004647; - CHECKREG r2, 0xFFFF8687; - CHECKREG r3, 0x00000607; - CHECKREG r5, 0x00000405; - CHECKREG r6, 0x00000607; - CHECKREG r7, 0x00002627; - - R7 = W [ P5 -- ] (X); - R0 = W [ P1 -- ] (X); - R1 = W [ P2 -- ] (X); - R3 = W [ P4 -- ] (X); - R4 = W [ FP -- ] (X); - CHECKREG r0, 0x00002021; - CHECKREG r1, 0x00004041; - CHECKREG r3, 0xFFFF8081; - CHECKREG r4, 0x00000001; - CHECKREG r6, 0x00000607; - CHECKREG r7, 0x00000001; - - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - R0 = B [ P5 ++ ] (Z); - R1 = B [ P1 ++ ] (Z); - R2 = B [ P2 ++ ] (Z); - R4 = B [ P4 ++ ] (Z); - R5 = B [ FP ++ ] (Z); - CHECKREG r0, 0x00000003; - CHECKREG r1, 0x00000023; - CHECKREG r2, 0x00000043; - CHECKREG r4, 0x00000083; - CHECKREG r5, 0x00000003; - R1 = B [ P5 ++ ] (Z); - R2 = B [ P1 ++ ] (Z); - R3 = B [ P2 ++ ] (Z); - R5 = B [ P4 ++ ] (Z); - R6 = B [ FP ++ ] (Z); - CHECKREG r0, 0x00000003; - CHECKREG r1, 0x00000002; - CHECKREG r2, 0x00000022; - CHECKREG r3, 0x00000042; - CHECKREG r5, 0x00000082; - CHECKREG r6, 0x00000002; - R2 = B [ P5 ++ ] (Z); - R3 = B [ P1 ++ ] (Z); - R4 = B [ P2 ++ ] (Z); - R6 = B [ P4 ++ ] (Z); - R7 = B [ FP ++ ] (Z); - CHECKREG r1, 0x00000002; - CHECKREG r2, 0x00000001; - CHECKREG r3, 0x00000021; - CHECKREG r4, 0x00000041; - CHECKREG r6, 0x00000081; - CHECKREG r7, 0x00000001; - - R3 = B [ P5 ++ ] (Z); - R4 = B [ P1 ++ ] (Z); - R5 = B [ P2 ++ ] (Z); - R7 = B [ P4 ++ ] (Z); - R0 = B [ FP ++ ] (Z); - CHECKREG r0, 0x00000000; - CHECKREG r2, 0x00000001; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000020; - CHECKREG r5, 0x00000040; - CHECKREG r7, 0x00000080; - - R4 = B [ P5 ++ ] (X); - R5 = B [ P1 ++ ] (X); - R6 = B [ P2 ++ ] (X); - R0 = B [ P4 ++ ] (X); - R1 = B [ FP ++ ] (X); - CHECKREG r0, 0xFFFFFF87; - CHECKREG r1, 0x00000007; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000007; - CHECKREG r5, 0x00000027; - CHECKREG r6, 0x00000047; - - R5 = B [ P5 ++ ] (X); - R6 = B [ P1 ++ ] (X); - R7 = B [ P2 ++ ] (X); - R1 = B [ P4 ++ ] (X); - R2 = B [ FP ++ ] (X); - CHECKREG r1, 0xFFFFFF86; - CHECKREG r2, 0x00000006; - CHECKREG r4, 0x00000007; - CHECKREG r5, 0x00000006; - CHECKREG r6, 0x00000026; - CHECKREG r7, 0x00000046; - - R6 = B [ P5 ++ ] (X); - R7 = B [ P1 ++ ] (X); - R0 = B [ P2 ++ ] (X); - R2 = B [ P4 ++ ] (X); - R3 = B [ FP ++ ] (X); - CHECKREG r0, 0x00000045; - CHECKREG r2, 0xFFFFFF85; - CHECKREG r3, 0x00000005; - CHECKREG r5, 0x00000006; - CHECKREG r6, 0x00000005; - CHECKREG r7, 0x00000025; - - R7 = B [ P5 ++ ] (X); - R0 = B [ P1 ++ ] (X); - R1 = B [ P2 ++ ] (X); - R3 = B [ P4 ++ ] (X); - R4 = B [ FP ++ ] (X); - CHECKREG r0, 0x00000024; - CHECKREG r1, 0x00000044; - CHECKREG r3, 0xFFFFFF84; - CHECKREG r4, 0x00000004; - CHECKREG r6, 0x00000005; - CHECKREG r7, 0x00000004; - - R0 = B [ P5 -- ] (Z); - R1 = B [ P1 -- ] (Z); - R2 = B [ P2 -- ] (Z); - R4 = B [ P4 -- ] (Z); - R5 = B [ FP -- ] (Z); - CHECKREG r0, 0x0000000B; - CHECKREG r1, 0x0000002B; - CHECKREG r2, 0x0000004B; - CHECKREG r4, 0x0000008B; - CHECKREG r5, 0x0000000B; - R1 = B [ P5 -- ] (Z); - R2 = B [ P1 -- ] (Z); - R3 = B [ P2 -- ] (Z); - R5 = B [ P4 -- ] (Z); - R6 = B [ FP -- ] (Z); - CHECKREG r0, 0x0000000B; - CHECKREG r1, 0x00000004; - CHECKREG r2, 0x00000024; - CHECKREG r3, 0x00000044; - CHECKREG r5, 0x00000084; - CHECKREG r6, 0x00000004; - R2 = B [ P5 -- ] (Z); - R3 = B [ P1 -- ] (Z); - R4 = B [ P2 -- ] (Z); - R6 = B [ P4 -- ] (Z); - R7 = B [ FP -- ] (Z); - CHECKREG r1, 0x00000004; - CHECKREG r2, 0x00000005; - CHECKREG r3, 0x00000025; - CHECKREG r4, 0x00000045; - CHECKREG r6, 0x00000085; - CHECKREG r7, 0x00000005; - - R3 = B [ P5 -- ] (Z); - R4 = B [ P1 -- ] (Z); - R5 = B [ P2 -- ] (Z); - R7 = B [ P4 -- ] (Z); - R0 = B [ FP -- ] (Z); - CHECKREG r0, 0x00000006; - CHECKREG r2, 0x00000005; - CHECKREG r3, 0x00000006; - CHECKREG r4, 0x00000026; - CHECKREG r5, 0x00000046; - CHECKREG r7, 0x00000086; - - R4 = B [ P5 -- ] (X); - R5 = B [ P1 -- ] (X); - R6 = B [ P2 -- ] (X); - R0 = B [ P4 -- ] (X); - R1 = B [ FP -- ] (X); - CHECKREG r0, 0xFFFFFF87; - CHECKREG r1, 0x00000007; - CHECKREG r3, 0x00000006; - CHECKREG r4, 0x00000007; - CHECKREG r5, 0x00000027; - CHECKREG r6, 0x00000047; - - R5 = B [ P5 -- ] (X); - R6 = B [ P1 -- ] (X); - R7 = B [ P2 -- ] (X); - R1 = B [ P4 -- ] (X); - R2 = B [ FP -- ] (X); - CHECKREG r1, 0xFFFFFF80; - CHECKREG r2, 0x00000000; - CHECKREG r4, 0x00000007; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000020; - CHECKREG r7, 0x00000040; - - R6 = B [ P5 -- ] (X); - R7 = B [ P1 -- ] (X); - R0 = B [ P2 -- ] (X); - R2 = B [ P4 -- ] (X); - R3 = B [ FP -- ] (X); - CHECKREG r0, 0x00000041; - CHECKREG r2, 0xFFFFFF81; - CHECKREG r3, 0x00000001; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000001; - CHECKREG r7, 0x00000021; - - R7 = B [ P5 -- ] (X); - R0 = B [ P1 -- ] (X); - R1 = B [ P2 -- ] (X); - R3 = B [ P4 -- ] (X); - R4 = B [ FP -- ] (X); - CHECKREG r0, 0x00000022; - CHECKREG r1, 0x00000042; - CHECKREG r3, 0xFFFFFF82; - CHECKREG r4, 0x00000002; - CHECKREG r6, 0x00000001; - CHECKREG r7, 0x00000002; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xb.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xb.s deleted file mode 100644 index 2337a7a..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xb.s +++ /dev/null @@ -1,326 +0,0 @@ -//Original:/testcases/core/c_ldst_ld_d_p_xb/c_ldst_ld_d_p_xb.dsp -// Spec Reference: c_ldst ld d [p] xb -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym p1, DATA_ADDR_1; - loadsym p2, DATA_ADDR_2; - loadsym p4, DATA_ADDR_4; - loadsym p5, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - -// load 8 bits from memory & sign extend into 32-bit reg - R4 = B [ P5 ] (X); - R5 = B [ FP ] (X); - R7 = B [ P1 ] (X); - R0 = B [ P2 ] (X); - R2 = B [ P4 ] (X); - CHECKREG r0, 0x00000023; - CHECKREG r2, 0x00000063; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0xFFFFFF83; - CHECKREG r5, 0x00000003; - CHECKREG r7, 0x00000003; - - R5 = B [ FP ] (X); - R7 = B [ P1 ] (X); - R0 = B [ P2 ] (X); - R2 = B [ P4 ] (X); - R3 = B [ P5 ] (X); - CHECKREG r0, 0x00000023; - CHECKREG r2, 0x00000063; - CHECKREG r3, 0xFFFFFF83; - CHECKREG r4, 0xFFFFFF83; - CHECKREG r5, 0x00000003; - CHECKREG r7, 0x00000003; - - R7 = B [ P1 ] (X); - R0 = B [ P2 ] (X); - R2 = B [ P4 ] (X); - R3 = B [ P5 ] (X); - R4 = B [ FP ] (X); - CHECKREG r0, 0x00000023; - CHECKREG r2, 0x00000063; - CHECKREG r3, 0xFFFFFF83; - CHECKREG r4, 0x00000003; - CHECKREG r5, 0x00000003; - CHECKREG r7, 0x00000003; - - R7 = B [ P1 ] (X); - R0 = B [ P2 ] (X); - R2 = B [ P4 ] (X); - R3 = B [ P5 ] (X); - R4 = B [ FP ] (X); - CHECKREG r0, 0x00000023; - CHECKREG r2, 0x00000063; - CHECKREG r3, 0xFFFFFF83; - CHECKREG r4, 0x00000003; - CHECKREG r7, 0x00000003; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - .data - -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xh.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xh.s deleted file mode 100644 index 480a98d..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xh.s +++ /dev/null @@ -1,354 +0,0 @@ -//Original:/testcases/core/c_ldst_ld_d_p_xh/c_ldst_ld_d_p_xh.dsp -// Spec Reference: c_ldst ld d [p] xh -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym p1, DATA_ADDR_1; - loadsym p2, DATA_ADDR_2; -.ifndef BFIN_HOST - loadsym p3, DATA_ADDR_3; -.endif - loadsym p4, DATA_ADDR_4; - loadsym p5, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - -// load 16 bits from memory and sign extend into 32-bit reg - R4 = W [ P5 ] (X); - R5 = W [ FP ] (X); - R7 = W [ P1 ] (X); - R0 = W [ P2 ] (X); -.ifndef BFIN_HOST - R1 = W [ P3 ] (X); -.else - imm32 r1, 0x00004243; -.endif - R2 = W [ P4 ] (X); - CHECKREG r0, 0x00002223; - CHECKREG r1, 0x00004243; - CHECKREG r2, 0x00006263; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0xFFFF8283; - CHECKREG r5, 0x00000203; - CHECKREG r7, 0x00000203; - - R5 = W [ FP ] (X); - R7 = W [ P1 ] (X); - R0 = W [ P2 ] (X); -.ifndef BFIN_HOST - R1 = W [ P3 ] (X); -.else - imm32 R1, 0x00004243; -.endif - R2 = W [ P4 ] (X); - R3 = W [ P5 ] (X); - CHECKREG r0, 0x00002223; - CHECKREG r1, 0x00004243; - CHECKREG r2, 0x00006263; - CHECKREG r3, 0xFFFF8283; - CHECKREG r4, 0xFFFF8283; - CHECKREG r5, 0x00000203; - CHECKREG r7, 0x00000203; - - R7 = W [ P1 ] (X); - R0 = W [ P2 ] (X); -.ifndef BFIN_HOST - R1 = W [ P3 ] (X); -.else - imm32 R1, 0x00004243; -.endif - R2 = W [ P4 ] (X); - R3 = W [ P5 ] (X); - R4 = W [ FP ] (X); - CHECKREG r0, 0x00002223; - CHECKREG r1, 0x00004243; - CHECKREG r2, 0x00006263; - CHECKREG r3, 0xFFFF8283; - CHECKREG r4, 0x00000203; - CHECKREG r5, 0x00000203; - CHECKREG r7, 0x00000203; - - R7 = W [ P1 ] (X); - R0 = W [ P2 ] (X); -.ifndef BFIN_HOST - R1 = W [ P3 ] (X); -.else - imm32 R1, 0x00004243; -.endif - R2 = W [ P4 ] (X); - R3 = W [ P5 ] (X); - R4 = W [ FP ] (X); - CHECKREG r0, 0x00002223; - CHECKREG r1, 0x00004243; - CHECKREG r2, 0x00006263; - CHECKREG r3, 0xFFFF8283; - CHECKREG r4, 0x00000203; - CHECKREG r7, 0x00000203; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data - -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_p_p.s b/sim/testsuite/sim/bfin/c_ldst_ld_p_p.s deleted file mode 100644 index 96658b5..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_p_p.s +++ /dev/null @@ -1,327 +0,0 @@ -//Original:/testcases/core/c_ldst_ld_p_p/c_ldst_ld_p_p.dsp -// Spec Reference: c_ldst ld p [p] -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym p1, DATA_ADDR_1; - loadsym p2, DATA_ADDR_2; - loadsym p4, DATA_ADDR_4; - loadsym p5, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - P2 = [ P1 ]; - P4 = [ P1 ]; - P5 = [ P1 ]; - FP = [ P1 ]; - CHECKREG p2, 0x78910213; - CHECKREG p4, 0x78910213; - CHECKREG p5, 0x78910213; - CHECKREG fp, 0x78910213; - - loadsym p2, DATA_ADDR_2; - P1 = [ P2 ]; - P4 = [ P2 ]; - P5 = [ P2 ]; - FP = [ P2 ]; - CHECKREG p1, 0x20212223; - CHECKREG p4, 0x20212223; - CHECKREG p5, 0x20212223; - CHECKREG fp, 0x20212223; - - loadsym p4, DATA_ADDR_4; - P1 = [ P4 ]; - P2 = [ P4 ]; - P5 = [ P4 ]; - FP = [ P4 ]; - CHECKREG p1, 0x60616263; - CHECKREG p2, 0x60616263; - CHECKREG p5, 0x60616263; - CHECKREG fp, 0x60616263; - - loadsym p5, DATA_ADDR_5; - P1 = [ P5 ]; - P2 = [ P5 ]; - P4 = [ P5 ]; - FP = [ P5 ]; - CHECKREG p1, 0x8A8B8C8D; - CHECKREG p2, 0x8A8B8C8D; - CHECKREG p4, 0x8A8B8C8D; - CHECKREG fp, 0x8A8B8C8D; - - loadsym fp, DATA_ADDR_7; - P1 = [ FP ]; - P2 = [ FP ]; - P4 = [ FP ]; - P5 = [ FP ]; - CHECKREG p1, 0x80818283; - CHECKREG p2, 0x80818283; - CHECKREG p4, 0x80818283; - CHECKREG p5, 0x80818283; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x78910213 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x8A8B8C8D - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_p_p_mm.s b/sim/testsuite/sim/bfin/c_ldst_ld_p_p_mm.s deleted file mode 100644 index 75471c8..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_p_p_mm.s +++ /dev/null @@ -1,406 +0,0 @@ -//Original:testcases/core/c_ldst_ld_p_p_mm/c_ldst_ld_p_p_mm.dsp -// Spec Reference: c_ldst ld p [p--] -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -INIT_I_REGS -1; -INIT_R_REGS 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x18; - loadsym p2, DATA_ADDR_2, 0x18; - loadsym i1, DATA_ADDR_3, 0x18; - loadsym p4, DATA_ADDR_4, 0x18; - loadsym p5, DATA_ADDR_5, 0x18; - loadsym fp, DATA_ADDR_6, 0x18; - loadsym i3, DATA_ADDR_7, 0x18; - P3 = I1; SP = I3; - - P2 = [ P1 -- ]; - P3 = [ P1 -- ]; - P4 = [ P1 -- ]; - P5 = [ P1 -- ]; - SP = [ P1 -- ]; - FP = [ P1 -- ]; - CHECKREG p2, 0x18191A1B; - CHECKREG p3, 0x14151617; - CHECKREG p4, 0x10111213; - CHECKREG p5, 0x0C0D0E0F; - CHECKREG sp, 0x08090A0B; - CHECKREG fp, 0x04050607; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p2, DATA_ADDR_2, 0x18; - P3 = I1; SP = I3; - - P1 = [ P2 -- ]; - P3 = [ P2 -- ]; - P4 = [ P2 -- ]; - P5 = [ P2 -- ]; - SP = [ P2 -- ]; - FP = [ P2 -- ]; - CHECKREG p1, 0x38393A3B; - CHECKREG p3, 0x34353637; - CHECKREG p4, 0x30313233; - CHECKREG p5, 0x2C2D2E2F; - CHECKREG sp, 0x28292A2B; - CHECKREG fp, 0x24252627; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i1, DATA_ADDR_3, 0x18; - P3 = I1; SP = I3; - - P1 = [ P3 -- ]; - P2 = [ P3 -- ]; - P4 = [ P3 -- ]; - P5 = [ P3 -- ]; - SP = [ P3 -- ]; - FP = [ P3 -- ]; - CHECKREG p1, 0x58595A5B; - CHECKREG p2, 0x54555657; - CHECKREG p4, 0x50515253; - CHECKREG p5, 0x4C4D4E4F; - CHECKREG sp, 0x48494A4B; - CHECKREG fp, 0x44454647; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p4, DATA_ADDR_4, 0x18; - P3 = I1; SP = I3; - - P1 = [ P4 -- ]; - P2 = [ P4 -- ]; - P3 = [ P4 -- ]; - P5 = [ P4 -- ]; - SP = [ P4 -- ]; - FP = [ P4 -- ]; - CHECKREG p1, 0x78797A7B; - CHECKREG p2, 0x74757677; - CHECKREG p3, 0x70717273; - CHECKREG p5, 0x6C6D6E6F; - CHECKREG sp, 0x68696A6B; - CHECKREG fp, 0x64656667; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_5, 0x18; - P3 = I1; SP = I3; - - P1 = [ P5 -- ]; - P2 = [ P5 -- ]; - P3 = [ P5 -- ]; - P4 = [ P5 -- ]; - SP = [ P5 -- ]; - FP = [ P5 -- ]; - CHECKREG p1, 0x98999A9B; - CHECKREG p2, 0x94959697; - CHECKREG p3, 0x90919293; - CHECKREG p4, 0x8C8D8E8F; - CHECKREG sp, 0x88898A8B; - CHECKREG fp, 0x84858687; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i3, DATA_ADDR_6, 0x18; - P3 = I1; SP = I3; - - P1 = [ SP -- ]; - P2 = [ SP -- ]; - P3 = [ SP -- ]; - P4 = [ SP -- ]; - P5 = [ SP -- ]; - FP = [ SP -- ]; - CHECKREG p1, 0x18191A1B; - CHECKREG p2, 0x14151617; - CHECKREG p3, 0x10111213; - CHECKREG p4, 0x0C0D0E0F; - CHECKREG p5, 0x08090A0B; - CHECKREG fp, 0x04050607; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_7, 0x18; - P3 = I1; SP = I3; - - P1 = [ FP -- ]; - P2 = [ FP -- ]; - P3 = [ FP -- ]; - P4 = [ FP -- ]; - P5 = [ FP -- ]; - SP = [ FP -- ]; - CHECKREG p1, 0x98999A9B; - CHECKREG p2, 0x94959697; - CHECKREG p3, 0x90919293; - CHECKREG p4, 0x8C8D8E8F; - CHECKREG p5, 0x88898A8B; - CHECKREG sp, 0x84858687; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x78910213 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x8A8B8C8D - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_p_p_pp.s b/sim/testsuite/sim/bfin/c_ldst_ld_p_p_pp.s deleted file mode 100644 index c66440a..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_ld_p_p_pp.s +++ /dev/null @@ -1,335 +0,0 @@ -//Original:/testcases/core/c_ldst_ld_p_p_pp/c_ldst_ld_p_p_pp.dsp -// Spec Reference: c_ldst ld p [p++] -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - loadsym p1, DATA_ADDR_1; - loadsym p2, DATA_ADDR_2; - loadsym p4, DATA_ADDR_4; - loadsym p5, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - P2 = [ P1 ++ ]; - P1 += 4; - P4 = [ P1 ++ ]; - P5 = [ P1 ++ ]; - P1 += 4; - FP = [ P1 ++ ]; - CHECKREG p2, 0x78910213; - CHECKREG p4, 0x08090A0B; - CHECKREG p5, 0x0C0D0E0F; - CHECKREG fp, 0x14151617; - - loadsym p2, DATA_ADDR_2; - P1 = [ P2 ++ ]; - P2 += 4; - P4 = [ P2 ++ ]; - P5 = [ P2 ++ ]; - P2 += 4; - FP = [ P2 ++ ]; - CHECKREG p1, 0x20212223; - CHECKREG p4, 0x28292A2B; - CHECKREG p5, 0x2C2D2E2F; - CHECKREG fp, 0x34353637; - - loadsym p4, DATA_ADDR_4; - P1 = [ P4 ++ ]; - P2 = [ P4 ++ ]; - P4 += 4; - P5 = [ P4 ++ ]; - P4 += 4; - FP = [ P4 ++ ]; - CHECKREG p1, 0x60616263; - CHECKREG p2, 0x64656667; - CHECKREG p5, 0x6C6D6E6F; - CHECKREG fp, 0x74757677; - - loadsym p5, DATA_ADDR_5; - P1 = [ P5 ++ ]; - P2 = [ P5 ++ ]; - P5 += 4; - P4 = [ P5 ++ ]; - P5 += 4; - FP = [ P5 ++ ]; - CHECKREG p1, 0x8A8B8C8D; - CHECKREG p2, 0x84858687; - CHECKREG p4, 0x8C8D8E8F; - CHECKREG fp, 0x94959697; - - loadsym fp, DATA_ADDR_7; - P1 = [ FP ++ ]; - P2 = [ FP ++ ]; - FP += 4; - P4 = [ FP ++ ]; - P5 = [ FP ++ ]; - CHECKREG p1, 0x80818283; - CHECKREG p2, 0x84858687; - CHECKREG p4, 0x8C8D8E8F; - CHECKREG p5, 0x90919293; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - .data -DATA_ADDR_1: - .dd 0x78910213 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xAB0CAD0E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x8A8B8C8D - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d.s deleted file mode 100644 index 504b027..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_st_p_d.s +++ /dev/null @@ -1,299 +0,0 @@ -//Original:/testcases/core/c_ldst_st_p_d/c_ldst_st_p_d.dsp -// Spec Reference: c_ldst st_p_d -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x0a231507; - imm32 r1, 0x1b342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f786a5c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c7e; - - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - [ P5 ] = R0; - [ P1 ] = R1; - [ P2 ] = R2; - [ P4 ] = R4; - [ FP ] = R5; - - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x1B342618; - CHECKREG r1, 0x2C453729; - CHECKREG r3, 0x4E67594B; - CHECKREG r4, 0x0A231507; - CHECKREG r5, 0x5F786A5C; - CHECKREG r7, 0x719A8C7E; - - imm32 r0, 0x1a231507; - imm32 r1, 0x12342618; - imm32 r2, 0x2c353729; - imm32 r3, 0x3d54483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f78665c; - imm32 r6, 0x60897b7d; - imm32 r7, 0x719a8c78; - [ P5 ] = R1; - [ P1 ] = R2; - [ P2 ] = R3; - [ P4 ] = R5; - [ FP ] = R6; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x2C353729; - CHECKREG r1, 0x3D54483A; - CHECKREG r3, 0x5F78665C; - CHECKREG r4, 0x12342618; - CHECKREG r5, 0x60897B7D; - CHECKREG r7, 0x719A8C78; - - imm32 r0, 0x2a231507; - imm32 r1, 0x12342618; - imm32 r2, 0x2c253729; - imm32 r3, 0x3d52483a; - imm32 r4, 0x4e67294b; - imm32 r5, 0x5f78625c; - imm32 r6, 0x60897b2d; - imm32 r7, 0x719a8c72; - [ P5 ] = R2; - [ P1 ] = R3; - [ P2 ] = R4; - [ P4 ] = R6; - [ FP ] = R7; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x3D52483A; - CHECKREG r1, 0x4E67294B; - CHECKREG r3, 0x60897B2D; - CHECKREG r4, 0x2C253729; - CHECKREG r5, 0x719A8C72; - CHECKREG r7, 0x719A8C72; - - imm32 r0, 0x3a231507; - imm32 r1, 0x13342618; - imm32 r2, 0x2c353729; - imm32 r3, 0x3d53483a; - imm32 r4, 0x4e67394b; - imm32 r5, 0x5f78635c; - imm32 r6, 0x60897b3d; - imm32 r7, 0x719a8c73; - [ P5 ] = R3; - [ P1 ] = R4; - [ P2 ] = R5; - [ P4 ] = R7; - [ FP ] = R0; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x4E67394B; - CHECKREG r1, 0x5F78635C; - CHECKREG r3, 0x719A8C73; - CHECKREG r4, 0x3D53483A; - CHECKREG r5, 0x3A231507; - CHECKREG r7, 0x719A8C73; - - imm32 r0, 0x4a231507; - imm32 r1, 0x14342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d54483a; - imm32 r4, 0x4e67494b; - imm32 r5, 0x5f78645c; - imm32 r6, 0x60897b4d; - imm32 r7, 0x719a8c74; - [ P5 ] = R4; - [ P1 ] = R5; - [ P2 ] = R6; - [ P4 ] = R0; - [ FP ] = R1; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x5F78645C; - CHECKREG r1, 0x60897B4D; - CHECKREG r3, 0x4A231507; - CHECKREG r4, 0x4E67494B; - CHECKREG r5, 0x14342618; - CHECKREG r7, 0x719A8C74; - - imm32 r0, 0x5a231507; - imm32 r1, 0x15342618; - imm32 r2, 0x2c553729; - imm32 r3, 0x3d55483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f78655c; - imm32 r6, 0x60897b5d; - imm32 r7, 0x719a8c75; - [ P5 ] = R5; - [ P1 ] = R6; - [ P2 ] = R7; - [ P4 ] = R1; - [ FP ] = R2; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x60897B5D; - CHECKREG r1, 0x719A8C75; - CHECKREG r3, 0x15342618; - CHECKREG r4, 0x5F78655C; - CHECKREG r5, 0x2C553729; - CHECKREG r7, 0x719A8C75; - - imm32 r0, 0x6a231507; - imm32 r1, 0x16342618; - imm32 r2, 0x2c653729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67694b; - imm32 r5, 0x5f78665c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c76; - [ P5 ] = R6; - [ P1 ] = R7; - [ P2 ] = R0; - [ P4 ] = R2; - [ FP ] = R3; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x719A8C76; - CHECKREG r1, 0x6A231507; - CHECKREG r3, 0x2C653729; - CHECKREG r4, 0x60897B6D; - CHECKREG r5, 0x3D56483A; - CHECKREG r7, 0x719A8C76; - - imm32 r0, 0x7a231507; - imm32 r1, 0x17342618; - imm32 r2, 0x2c753729; - imm32 r3, 0x3d57483a; - imm32 r4, 0x4e67794b; - imm32 r5, 0x5f78675c; - imm32 r6, 0x60897b7d; - imm32 r7, 0x719a8c77; - [ P5 ] = R7; - [ P1 ] = R0; - [ P2 ] = R1; - [ P4 ] = R3; - [ FP ] = R4; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x7A231507; - CHECKREG r1, 0x17342618; - CHECKREG r3, 0x3D57483A; - CHECKREG r4, 0x719A8C77; - CHECKREG r5, 0x4E67794B; - CHECKREG r7, 0x719A8C77; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data - -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - -DATA_ADDR_6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - -DATA_ADDR_7: - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_b.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_b.s deleted file mode 100644 index 1575c00..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_st_p_d_b.s +++ /dev/null @@ -1,300 +0,0 @@ -//Original:/testcases/core/c_ldst_st_p_d_b/c_ldst_st_p_d_b.dsp -// Spec Reference: c_ldst st_p d b -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - imm32 r0, 0x0a231507; - imm32 r1, 0x1b342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f786a5c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c7e; - - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - B [ P5 ] = R0; - B [ P1 ] = R1; - B [ P2 ] = R2; - B [ P4 ] = R4; - B [ FP ] = R5; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x20212218; - CHECKREG r1, 0x40414229; - CHECKREG r3, 0x8081824B; - CHECKREG r4, 0x00010207; - CHECKREG r5, 0xA0A1A25C; - CHECKREG r7, 0x719A8C7E; - - imm32 r0, 0x1a231507; - imm32 r1, 0x11342618; - imm32 r2, 0x2c153729; - imm32 r3, 0x3d51483a; - imm32 r4, 0x4e67194b; - imm32 r5, 0x5f78615c; - imm32 r6, 0x60897b1d; - imm32 r7, 0x719a8c71; - B [ P5 ] = R1; - B [ P1 ] = R2; - B [ P2 ] = R3; - B [ P4 ] = R5; - B [ FP ] = R6; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x20212229; - CHECKREG r1, 0x4041423A; - CHECKREG r3, 0x8081825C; - CHECKREG r4, 0x00010218; - CHECKREG r5, 0xA0A1A21D; - CHECKREG r7, 0x719A8C71; - - imm32 r0, 0x2a231507; - imm32 r1, 0x12342618; - imm32 r2, 0x2c253729; - imm32 r3, 0x3d52483a; - imm32 r4, 0x4e67294b; - imm32 r5, 0x5f78625c; - imm32 r6, 0x60897b2d; - imm32 r7, 0x719a8c72; - B [ P5 ] = R2; - B [ P1 ] = R3; - B [ P2 ] = R4; - B [ P4 ] = R6; - B [ FP ] = R7; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x2021223A; - CHECKREG r1, 0x4041424B; - CHECKREG r2, 0x2c253729; - CHECKREG r3, 0x8081822D; - CHECKREG r4, 0x00010229; - CHECKREG r5, 0xA0A1A272; - CHECKREG r7, 0x719A8C72; - - imm32 r0, 0x3a231507; - imm32 r1, 0x13342618; - imm32 r3, 0x3d53483a; - imm32 r4, 0x4e67394b; - imm32 r5, 0x5f78635c; - imm32 r6, 0x60897b3d; - imm32 r7, 0x719a8c73; - B [ P5 ] = R3; - B [ P1 ] = R4; - B [ P2 ] = R5; - B [ P4 ] = R7; - B [ FP ] = R0; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x2021224B; - CHECKREG r1, 0x4041425C; - CHECKREG r3, 0x80818273; - CHECKREG r4, 0x0001023A; - CHECKREG r5, 0xA0A1A207; - CHECKREG r7, 0x719A8C73; - - imm32 r0, 0x4a231507; - imm32 r1, 0x14342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d54483a; - imm32 r4, 0x4e67494b; - imm32 r5, 0x5f78645c; - imm32 r6, 0x60897b4d; - imm32 r7, 0x719a8c74; - B [ P5 ] = R4; - B [ P1 ] = R5; - B [ P2 ] = R6; - B [ P4 ] = R0; - B [ FP ] = R1; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x2021225C; - CHECKREG r1, 0x4041424D; - CHECKREG r3, 0x80818207; - CHECKREG r4, 0x0001024B; - CHECKREG r5, 0xA0A1A218; - CHECKREG r7, 0x719A8C74; - - imm32 r0, 0x5a231507; - imm32 r1, 0x15342618; - imm32 r2, 0x2c553729; - imm32 r3, 0x3d55483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f78655c; - imm32 r6, 0x60897b5d; - imm32 r7, 0x719a8c75; - B [ P5 ] = R5; - B [ P1 ] = R6; - B [ P2 ] = R7; - B [ P4 ] = R1; - B [ FP ] = R2; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x2021225D; - CHECKREG r1, 0x40414275; - CHECKREG r3, 0x80818218; - CHECKREG r4, 0x0001025C; - CHECKREG r5, 0xA0A1A229; - CHECKREG r7, 0x719A8C75; - - imm32 r0, 0x6a231507; - imm32 r1, 0x16342618; - imm32 r2, 0x2c653729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67694b; - imm32 r5, 0x5f78665c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c76; - B [ P5 ] = R6; - B [ P1 ] = R7; - B [ P2 ] = R0; - B [ P4 ] = R2; - B [ FP ] = R3; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x20212276; - CHECKREG r1, 0x40414207; - CHECKREG r3, 0x80818229; - CHECKREG r4, 0x0001026D; - CHECKREG r5, 0xA0A1A23A; - CHECKREG r7, 0x719A8C76; - - imm32 r0, 0x7a231507; - imm32 r1, 0x17342618; - imm32 r2, 0x2c753729; - imm32 r3, 0x3d57483a; - imm32 r4, 0x4e67794b; - imm32 r5, 0x5f78675c; - imm32 r6, 0x60897b7d; - imm32 r7, 0x719a8c77; - B [ P5 ] = R7; - B [ P1 ] = R0; - B [ P2 ] = R1; - B [ P4 ] = R3; - B [ FP ] = R4; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x20212207; - CHECKREG r1, 0x40414218; - CHECKREG r3, 0x8081823A; - CHECKREG r4, 0x00010277; - CHECKREG r5, 0xA0A1A24B; - CHECKREG r7, 0x719A8C77; - - pass - -// Pre-load memory witb known data -// More data is defined than will actually be used - - .data - -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - -DATA_ADDR_6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - -DATA_ADDR_7: - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_h.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_h.s deleted file mode 100644 index dc0906c..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_st_p_d_h.s +++ /dev/null @@ -1,280 +0,0 @@ -//Original:/testcases/core/c_ldst_st_p_d_h/c_ldst_st_p_d_h.dsp -// Spec Reference: c_ldst st_p d h -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - imm32 r0, 0x0a231507; - imm32 r1, 0x1b342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f786a5c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c7e; - - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - W [ P5 ] = R0; - W [ P1 ] = R1; - W [ P2 ] = R2; - W [ P4 ] = R4; - W [ FP ] = R5; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x20212618; - CHECKREG r1, 0x40413729; - CHECKREG r3, 0x8081594B; - CHECKREG r4, 0x00011507; - CHECKREG r5, 0xA0A16A5C; - CHECKREG r7, 0x719A8C7E; - - imm32 r0, 0x1a231507; - imm32 r1, 0x11342618; - imm32 r2, 0x2c153729; - imm32 r3, 0x3d51483a; - imm32 r4, 0x4e67194b; - imm32 r5, 0x5f78615c; - imm32 r6, 0x60897b1d; - imm32 r7, 0x719a8c71; - W [ P5 ] = R1; - W [ P1 ] = R2; - W [ P2 ] = R3; - W [ P4 ] = R5; - W [ FP ] = R6; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x20213729; - CHECKREG r1, 0x4041483A; - CHECKREG r3, 0x8081615C; - CHECKREG r4, 0x00012618; - CHECKREG r5, 0xA0A17B1D; - CHECKREG r6, 0x60897b1d; - - imm32 r0, 0x2a231507; - imm32 r1, 0x12342618; - imm32 r2, 0x2c253729; - imm32 r3, 0x3d52483a; - imm32 r4, 0x4e67294b; - imm32 r5, 0x5f78625c; - imm32 r6, 0x60897b2d; - imm32 r7, 0x719a8c72; - W [ P5 ] = R2; - W [ P1 ] = R3; - W [ P2 ] = R4; - W [ P4 ] = R6; - W [ FP ] = R7; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x2021483A; - CHECKREG r1, 0x4041294B; - CHECKREG r3, 0x80817B2D; - CHECKREG r4, 0x00013729; - CHECKREG r5, 0xA0A18C72; - CHECKREG r7, 0x719A8C72; - - imm32 r0, 0x3a231507; - imm32 r1, 0x13342618; - imm32 r2, 0x2c353729; - imm32 r3, 0x3d53483a; - imm32 r4, 0x4e67394b; - imm32 r5, 0x5f78635c; - imm32 r6, 0x60897b3d; - imm32 r7, 0x719a8c73; - W [ P5 ] = R3; - W [ P1 ] = R4; - W [ P2 ] = R5; - W [ P4 ] = R7; - W [ FP ] = R0; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x2021394B; - CHECKREG r1, 0x4041635C; - CHECKREG r3, 0x80818C73; - CHECKREG r4, 0x0001483A; - CHECKREG r5, 0xA0A11507; - CHECKREG r7, 0x719A8C73; - - imm32 r0, 0x4a231507; - imm32 r1, 0x14342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d54483a; - imm32 r4, 0x4e67494b; - imm32 r5, 0x5f78645c; - imm32 r6, 0x60897b4d; - imm32 r7, 0x719a8c74; - W [ P5 ] = R4; - W [ P1 ] = R5; - W [ P2 ] = R6; - W [ P4 ] = R0; - W [ FP ] = R1; - - W [ P5 ] = R5; - W [ P1 ] = R6; - W [ P2 ] = R7; - W [ P4 ] = R1; - W [ FP ] = R2; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x20217B4D; - CHECKREG r1, 0x40418C74; - CHECKREG r3, 0x80812618; - CHECKREG r4, 0x0001645C; - CHECKREG r5, 0xA0A13729; - CHECKREG r7, 0x719A8C74; - - imm32 r0, 0x5a231507; - imm32 r1, 0x15342618; - imm32 r2, 0x2c553729; - imm32 r3, 0x3d55483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f78655c; - imm32 r6, 0x60897b5d; - imm32 r7, 0x719a8c75; - W [ P5 ] = R6; - W [ P1 ] = R7; - W [ P2 ] = R0; - W [ P4 ] = R2; - W [ FP ] = R3; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x20218C75; - CHECKREG r1, 0x40411507; - CHECKREG r3, 0x80813729; - CHECKREG r4, 0x00017B5D; - CHECKREG r5, 0xA0A1483A; - CHECKREG r7, 0x719A8C75; - - imm32 r0, 0x6a231507; - imm32 r1, 0x16342618; - imm32 r2, 0x2c653729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67694b; - imm32 r5, 0x5f78665c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c76; - W [ P5 ] = R7; - W [ P1 ] = R0; - W [ P2 ] = R1; - W [ P4 ] = R3; - W [ FP ] = R4; - R0 = [ P1 ]; - R1 = [ P2 ]; - R3 = [ P4 ]; - R4 = [ P5 ]; - R5 = [ FP ]; - CHECKREG r0, 0x20211507; - CHECKREG r1, 0x40412618; - CHECKREG r3, 0x8081483A; - CHECKREG r4, 0x00018C76; - CHECKREG r5, 0xA0A1694B; - CHECKREG r7, 0x719A8C76; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - .data - -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - -DATA_ADDR_6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - -DATA_ADDR_7: - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm.s deleted file mode 100644 index 54d7faa..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm.s +++ /dev/null @@ -1,601 +0,0 @@ -//Original:testcases/core/c_ldst_st_p_d_mm/c_ldst_st_p_d_mm.dsp -// Spec Reference: c_ldst st_p++/p-- -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -INIT_I_REGS -1; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; -I0 = P3; -I2 = SP; - - imm32 r0, 0x0a231507; - imm32 r1, 0x1b342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f786a5c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c7e; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - loadsym i3, DATA_ADDR_7; - P3 = I1; SP = I3; - - [ P5 ++ ] = R0; - [ P1 ++ ] = R1; - [ P2 ++ ] = R2; - [ P3 ++ ] = R3; - [ P4 ++ ] = R4; - [ FP ++ ] = R5; - [ SP ++ ] = R6; - - [ P5 ++ ] = R2; - [ P1 ++ ] = R3; - [ P2 ++ ] = R4; - [ P3 ++ ] = R5; - [ P4 ++ ] = R6; - [ FP ++ ] = R7; - [ SP ++ ] = R0; - - [ P5 ++ ] = R5; - [ P1 ++ ] = R6; - [ P2 ++ ] = R7; - [ P3 ++ ] = R0; - [ P4 ++ ] = R1; - [ FP ++ ] = R2; - [ SP ++ ] = R3; - - [ P5 ++ ] = R7; - [ P1 ++ ] = R0; - [ P2 ++ ] = R1; - [ P3 ++ ] = R2; - [ P4 ++ ] = R3; - [ FP ++ ] = R4; - [ SP ++ ] = R5; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - loadsym i3, DATA_ADDR_7; - P3 = I1; SP = I3; - - R0 = [ P1 ++ ]; - R1 = [ P2 ++ ]; - R2 = [ P3 ++ ]; - R3 = [ P4 ++ ]; - R4 = [ P5 ++ ]; - R5 = [ FP ++ ]; - R6 = [ SP ++ ]; - CHECKREG r0, 0x1B342618; - CHECKREG r1, 0x2C453729; - CHECKREG r2, 0x3D56483A; - CHECKREG r3, 0x4E67594B; - CHECKREG r4, 0x0A231507; - CHECKREG r5, 0x5F786A5C; - CHECKREG r6, 0x60897B6D; - CHECKREG r7, 0x719A8C7E; - R0 = [ P1 ++ ]; - R1 = [ P2 ++ ]; - R2 = [ P3 ++ ]; - R3 = [ P4 ++ ]; - R4 = [ P5 ++ ]; - R5 = [ FP ++ ]; - R6 = [ SP ++ ]; - CHECKREG r0, 0x3D56483A; - CHECKREG r1, 0x4E67594B; - CHECKREG r2, 0x5F786A5C; - CHECKREG r3, 0x60897B6D; - CHECKREG r4, 0x2C453729; - CHECKREG r5, 0x719A8C7E; - CHECKREG r6, 0x0A231507; - CHECKREG r7, 0x719A8C7E; - R1 = [ P1 ++ ]; - R2 = [ P2 ++ ]; - R3 = [ P3 ++ ]; - R4 = [ P4 ++ ]; - R5 = [ P5 ++ ]; - R6 = [ FP ++ ]; - R7 = [ SP ++ ]; - CHECKREG r0, 0x3D56483A; - CHECKREG r1, 0x60897B6D; - CHECKREG r2, 0x719A8C7E; - CHECKREG r3, 0x0A231507; - CHECKREG r4, 0x1B342618; - CHECKREG r5, 0x5F786A5C; - CHECKREG r6, 0x2C453729; - CHECKREG r7, 0x3D56483A; - R3 = [ P1 ++ ]; - R4 = [ P2 ++ ]; - R5 = [ P3 ++ ]; - R6 = [ P4 ++ ]; - R7 = [ P5 ++ ]; - R0 = [ FP ++ ]; - R1 = [ SP ++ ]; - CHECKREG r0, 0x4E67594B; - CHECKREG r1, 0x5F786A5C; - CHECKREG r2, 0x719A8C7E; - CHECKREG r3, 0x0A231507; - CHECKREG r4, 0x1B342618; - CHECKREG r5, 0x2C453729; - CHECKREG r6, 0x3D56483A; - CHECKREG r7, 0x719A8C7E; - -// reset values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x20; - loadsym p1, DATA_ADDR_2, 0x20; - loadsym p2, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym p4, DATA_ADDR_5, 0x20; - loadsym fp, DATA_ADDR_6, 0x20; - loadsym i3, DATA_ADDR_7, 0x20; - P3 = I1; SP = I3; - - [ P5 -- ] = R0; - [ P1 -- ] = R1; - [ P2 -- ] = R2; - [ P3 -- ] = R3; - [ P4 -- ] = R4; - [ FP -- ] = R5; - [ SP -- ] = R6; - - [ P5 -- ] = R2; - [ P1 -- ] = R3; - [ P2 -- ] = R4; - [ P3 -- ] = R5; - [ P4 -- ] = R6; - [ FP -- ] = R7; - [ SP -- ] = R0; - - [ P5 -- ] = R5; - [ P1 -- ] = R6; - [ P2 -- ] = R7; - [ P3 -- ] = R0; - [ P4 -- ] = R1; - [ FP -- ] = R2; - [ SP -- ] = R3; - - [ P5 -- ] = R6; - [ P1 -- ] = R7; - [ P2 -- ] = R0; - [ P3 -- ] = R1; - [ P4 -- ] = R2; - [ FP -- ] = R3; - [ SP -- ] = R4; - [ P1 -- ] = R0; - [ P2 -- ] = R1; - [ P3 -- ] = R2; - [ P4 -- ] = R3; - [ FP -- ] = R4; - [ SP -- ] = R5; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x20; - loadsym p1, DATA_ADDR_2, 0x20; - loadsym p2, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym p4, DATA_ADDR_5, 0x20; - loadsym fp, DATA_ADDR_6, 0x20; - loadsym i3, DATA_ADDR_7, 0x20; - P3 = I1; SP = I3; - - R0 = [ P1 -- ]; - R1 = [ P2 -- ]; - R2 = [ P3 -- ]; - R3 = [ P4 -- ]; - R4 = [ P5 -- ]; - R5 = [ FP -- ]; - R6 = [ SP -- ]; - CHECKREG r0, 0x5F786A5C; - CHECKREG r1, 0x719A8C7E; - CHECKREG r2, 0x0A231507; - CHECKREG r3, 0x1B342618; - CHECKREG r4, 0x4E67594B; - CHECKREG r5, 0x2C453729; - CHECKREG r6, 0x3D56483A; - CHECKREG r7, 0x719A8C7E; - R2 = [ P1 -- ]; - R3 = [ P2 -- ]; - R4 = [ P3 -- ]; - R5 = [ P4 -- ]; - R6 = [ P5 -- ]; - R7 = [ FP -- ]; - R0 = [ SP -- ]; - CHECKREG r0, 0x4E67594B; - CHECKREG r1, 0x719A8C7E; - CHECKREG r2, 0x0A231507; - CHECKREG r3, 0x1B342618; - CHECKREG r4, 0x2C453729; - CHECKREG r5, 0x3D56483A; - CHECKREG r6, 0x719A8C7E; - R3 = [ P1 -- ]; - R4 = [ P2 -- ]; - R5 = [ P3 -- ]; - R6 = [ P4 -- ]; - R7 = [ P5 -- ]; - R0 = [ FP -- ]; - R1 = [ SP -- ]; - CHECKREG r0, 0x719A8C7E; - CHECKREG r1, 0x0A231507; - CHECKREG r2, 0x0A231507; - CHECKREG r3, 0x3D56483A; - CHECKREG r4, 0x719A8C7E; - CHECKREG r5, 0x4E67594B; - CHECKREG r6, 0x5F786A5C; - CHECKREG r7, 0x2C453729; - R5 = [ P1 -- ]; - R6 = [ P2 -- ]; - R7 = [ P3 -- ]; - R0 = [ P4 -- ]; - R1 = [ P5 -- ]; - R2 = [ FP -- ]; - R3 = [ SP -- ]; - CHECKREG r0, 0x719A8C7E; - CHECKREG r1, 0x3D56483A; - CHECKREG r2, 0x0A231507; - CHECKREG r3, 0x1B342618; - CHECKREG r4, 0x719A8C7E; - CHECKREG r5, 0x719A8C7E; - CHECKREG r6, 0x4E67594B; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_7: - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_b.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_b.s deleted file mode 100644 index 1a2c3a9..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_b.s +++ /dev/null @@ -1,498 +0,0 @@ -//Original:testcases/core/c_ldst_st_p_d_mm_b/c_ldst_st_p_d_mm_b.dsp -// Spec Reference: c_ldst st_p-- b byte -# mach: bfin - -.include "testutils.inc" - start - - -// set all regs -INIT_I_REGS -1; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; -I0 = P3; -I2 = SP; - - imm32 r0, 0x0a231507; - imm32 r1, 0x1b342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f786a5c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c7e; - -// reset values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x20; - loadsym p1, DATA_ADDR_2, 0x20; - loadsym p2, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym p4, DATA_ADDR_5, 0x20; - loadsym fp, DATA_ADDR_6, 0x20; - loadsym i3, DATA_ADDR_7, 0x20; - P3 = I1; SP = I3; - - B [ P5 -- ] = R0; - B [ P1 -- ] = R1; - B [ P2 -- ] = R2; - B [ P3 -- ] = R3; - B [ P4 -- ] = R4; - B [ FP -- ] = R5; - B [ SP -- ] = R6; - - B [ P5 -- ] = R1; - B [ P1 -- ] = R2; - B [ P2 -- ] = R3; - B [ P3 -- ] = R4; - B [ P4 -- ] = R5; - B [ FP -- ] = R6; - B [ SP -- ] = R7; - - B [ P5 -- ] = R2; - B [ P1 -- ] = R3; - B [ P2 -- ] = R4; - B [ P3 -- ] = R5; - B [ P4 -- ] = R6; - B [ FP -- ] = R7; - B [ SP -- ] = R0; - - B [ P5 -- ] = R3; - B [ P1 -- ] = R4; - B [ P2 -- ] = R5; - B [ P3 -- ] = R6; - B [ P4 -- ] = R7; - B [ FP -- ] = R0; - B [ SP -- ] = R1; - - B [ P5 -- ] = R4; - B [ P1 -- ] = R5; - B [ P2 -- ] = R6; - B [ P3 -- ] = R7; - B [ P4 -- ] = R0; - B [ FP -- ] = R1; - B [ SP -- ] = R2; - - B [ P5 -- ] = R5; - B [ P1 -- ] = R6; - B [ P2 -- ] = R7; - B [ P3 -- ] = R0; - B [ P4 -- ] = R1; - B [ FP -- ] = R2; - B [ SP -- ] = R3; - - B [ P5 -- ] = R6; - B [ P1 -- ] = R7; - B [ P2 -- ] = R0; - B [ P3 -- ] = R1; - B [ P4 -- ] = R2; - B [ FP -- ] = R3; - B [ SP -- ] = R4; - - B [ P5 -- ] = R7; - B [ P1 -- ] = R0; - B [ P2 -- ] = R1; - B [ P3 -- ] = R2; - B [ P4 -- ] = R3; - B [ FP -- ] = R4; - B [ SP -- ] = R5; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x20; - loadsym p1, DATA_ADDR_2, 0x20; - loadsym p2, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym p4, DATA_ADDR_5, 0x20; - loadsym fp, DATA_ADDR_6, 0x20; - loadsym i3, DATA_ADDR_7, 0x20; - P3 = I1; SP = I3; - - R0 = [ P1 -- ]; - R1 = [ P2 -- ]; - R2 = [ P3 -- ]; - R3 = [ P4 -- ]; - R4 = [ P5 -- ]; - R5 = [ FP -- ]; - R6 = [ SP -- ]; - CHECKREG r1, 0x00000029; - CHECKREG r2, 0x0000003A; - CHECKREG r3, 0x0000004B; - CHECKREG r4, 0x00000007; - CHECKREG r5, 0x0000005C; - CHECKREG r6, 0xE0E1E26D; - CHECKREG r7, 0x719A8C7E; - R1 = [ P1 -- ]; - R2 = [ P2 -- ]; - R3 = [ P3 -- ]; - R4 = [ P4 -- ]; - R5 = [ P5 -- ]; - R6 = [ FP -- ]; - R7 = [ SP -- ]; - CHECKREG r1, 0x293A4B5C; - CHECKREG r2, 0x3A4B5C6D; - CHECKREG r3, 0x4B5C6D7E; - CHECKREG r4, 0x5C6D7E07; - CHECKREG r5, 0x18293A4B; - CHECKREG r6, 0x6D7E0718; - CHECKREG r7, 0x7E071829; - R3 = [ P1 -- ]; - R4 = [ P2 -- ]; - R5 = [ P3 -- ]; - R6 = [ P4 -- ]; - R7 = [ P5 -- ]; - R0 = [ FP -- ]; - R1 = [ SP -- ]; - CHECKREG r1, 0x3A4B5CDB; - CHECKREG r2, 0x3A4B5C6D; - CHECKREG r3, 0x6D7E073B; - CHECKREG r4, 0x7E07185B; - CHECKREG r5, 0x0718297B; - CHECKREG r6, 0x18293A9B; - CHECKREG r7, 0x5C6D7E1B; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_7: - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_h.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_h.s deleted file mode 100644 index 883bf35..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_h.s +++ /dev/null @@ -1,554 +0,0 @@ -//Original:testcases/core/c_ldst_st_p_d_mm_h/c_ldst_st_p_d_mm_h.dsp -// Spec Reference: c_ldst st_p-- h half -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -INIT_I_REGS -1; -INIT_R_REGS 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; -I0 = P3; -I2 = SP; - - imm32 r0, 0x0a231507; - imm32 r1, 0x1b342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f786a5c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c7e; - -// reset values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x20; - loadsym p1, DATA_ADDR_2, 0x20; - loadsym p2, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym p4, DATA_ADDR_5, 0x20; - loadsym fp, DATA_ADDR_6, 0x20; - loadsym i3, DATA_ADDR_7, 0x20; - P3 = I1; SP = I3; - - W [ P5 -- ] = R0; - W [ P1 -- ] = R1; - W [ P2 -- ] = R2; - W [ P3 -- ] = R3; - W [ P4 -- ] = R4; - W [ FP -- ] = R5; - W [ SP -- ] = R6; - - W [ P5 -- ] = R1; - W [ P1 -- ] = R2; - W [ P2 -- ] = R3; - W [ P3 -- ] = R4; - W [ P4 -- ] = R5; - W [ FP -- ] = R6; - W [ SP -- ] = R7; - - W [ P5 -- ] = R2; - W [ P1 -- ] = R3; - W [ P2 -- ] = R4; - W [ P3 -- ] = R5; - W [ P4 -- ] = R6; - W [ FP -- ] = R7; - W [ SP -- ] = R0; - - W [ P5 -- ] = R3; - W [ P1 -- ] = R4; - W [ P2 -- ] = R5; - W [ P3 -- ] = R6; - W [ P4 -- ] = R7; - W [ FP -- ] = R0; - W [ SP -- ] = R1; - - W [ P5 -- ] = R4; - W [ P1 -- ] = R5; - W [ P2 -- ] = R6; - W [ P3 -- ] = R7; - W [ P4 -- ] = R0; - W [ FP -- ] = R1; - W [ SP -- ] = R2; - - W [ P5 -- ] = R5; - W [ P1 -- ] = R6; - W [ P2 -- ] = R7; - W [ P3 -- ] = R0; - W [ P4 -- ] = R1; - W [ FP -- ] = R2; - W [ SP -- ] = R3; - - W [ P5 -- ] = R6; - W [ P1 -- ] = R7; - W [ P2 -- ] = R0; - W [ P3 -- ] = R1; - W [ P4 -- ] = R2; - W [ FP -- ] = R3; - W [ SP -- ] = R4; - - W [ P5 -- ] = R7; - W [ P1 -- ] = R0; - W [ P2 -- ] = R1; - W [ P3 -- ] = R2; - W [ P4 -- ] = R3; - W [ FP -- ] = R4; - W [ SP -- ] = R5; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x20; - loadsym p1, DATA_ADDR_2, 0x20; - loadsym p2, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym p4, DATA_ADDR_5, 0x20; - loadsym fp, DATA_ADDR_6, 0x20; - loadsym i3, DATA_ADDR_7, 0x20; - P3 = I1; SP = I3; - - R0 = [ P1 -- ]; - R1 = [ P2 -- ]; - R2 = [ P3 -- ]; - R3 = [ P4 -- ]; - R4 = [ P5 -- ]; - R5 = [ FP -- ]; - R6 = [ SP -- ]; - CHECKREG r1, 0x00003729; - CHECKREG r2, 0x0000483A; - CHECKREG r3, 0x0000594B; - CHECKREG r4, 0x00001507; - CHECKREG r5, 0x00006A5C; - CHECKREG r6, 0xE0E17B6D; - CHECKREG r7, 0x719A8C7E; - R1 = [ P1 -- ]; - R2 = [ P2 -- ]; - R3 = [ P3 -- ]; - R4 = [ P4 -- ]; - R5 = [ P5 -- ]; - R6 = [ FP -- ]; - R7 = [ SP -- ]; - CHECKREG r1, 0x3729483A; - CHECKREG r2, 0x483A594B; - CHECKREG r3, 0x594B6A5C; - CHECKREG r4, 0x6A5C7B6D; - CHECKREG r5, 0x26183729; - CHECKREG r6, 0x7B6D8C7E; - CHECKREG r7, 0x8C7E1507; - R3 = [ P1 -- ]; - R4 = [ P2 -- ]; - R5 = [ P3 -- ]; - R6 = [ P4 -- ]; - R7 = [ P5 -- ]; - R0 = [ FP -- ]; - R1 = [ SP -- ]; - CHECKREG r1, 0x26183729; - CHECKREG r2, 0x483A594B; - CHECKREG r3, 0x594B6A5C; - CHECKREG r4, 0x6A5C7B6D; - CHECKREG r5, 0x7B6D8C7E; - CHECKREG r6, 0x8C7E1507; - CHECKREG r7, 0x483A594B; - R3 = [ P1 -- ]; - R4 = [ P2 -- ]; - R5 = [ P3 -- ]; - R6 = [ P4 -- ]; - R7 = [ P5 -- ]; - R0 = [ FP -- ]; - R1 = [ SP -- ]; - CHECKREG r1, 0x483A594B; - CHECKREG r2, 0x483A594B; - CHECKREG r3, 0x7B6D8C7E; - CHECKREG r4, 0x8C7E1507; - CHECKREG r5, 0x15072618; - CHECKREG r6, 0x26183729; - CHECKREG r7, 0x6A5C7B6D; - R4 = [ P1 -- ]; - R5 = [ P2 -- ]; - R6 = [ P3 -- ]; - R7 = [ P4 -- ]; - R0 = [ P5 -- ]; - R1 = [ FP -- ]; - R2 = [ SP -- ]; - CHECKREG r1, 0x594BB2B3; - CHECKREG r2, 0x6A5CD2D3; - CHECKREG r3, 0x7B6D8C7E; - CHECKREG r4, 0x15073233; - CHECKREG r5, 0x26185253; - CHECKREG r6, 0x37297273; - CHECKREG r7, 0x483A9293; - R5 = [ P1 -- ]; - R6 = [ P2 -- ]; - R7 = [ P3 -- ]; - R0 = [ P4 -- ]; - R1 = [ P5 -- ]; - R2 = [ FP -- ]; - R3 = [ SP -- ]; - CHECKREG r1, 0x0C0D0E0F; - CHECKREG r2, 0xACADAEAF; - CHECKREG r3, 0xCCCDCECF; - CHECKREG r4, 0x15073233; - CHECKREG r5, 0x2C2D2E2F; - CHECKREG r6, 0x4C4D4E4F; - CHECKREG r7, 0x6C6D6E6F; - R6 = [ P1 -- ]; - R7 = [ P2 -- ]; - R0 = [ P3 -- ]; - R1 = [ P4 -- ]; - R2 = [ P5 -- ]; - R3 = [ FP -- ]; - R0 = [ SP -- ]; - CHECKREG r1, 0x88898A8B; - CHECKREG r2, 0x08090A0B; - CHECKREG r3, 0xA8A9AAAB; - CHECKREG r4, 0x15073233; - CHECKREG r5, 0x2C2D2E2F; - CHECKREG r6, 0x28292A2B; - CHECKREG r7, 0x48494A4B; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_7: - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp.s deleted file mode 100644 index 05e96bc..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp.s +++ /dev/null @@ -1,804 +0,0 @@ -//Original:testcases/core/c_ldst_st_p_d_pp/c_ldst_st_p_d_pp.dsp -// Spec Reference: c_ldst st_p++ d -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -INIT_I_REGS -1; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; -I0 = P3; -I2 = SP; - - imm32 r0, 0x0a231507; - imm32 r1, 0x1b342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f786a5c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c7e; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - loadsym i3, DATA_ADDR_7; - P3 = I1; SP = I3; - - [ P5 ++ ] = R0; - [ P1 ++ ] = R1; - [ P2 ++ ] = R2; - [ P3 ++ ] = R3; - [ P4 ++ ] = R4; - [ FP ++ ] = R5; - [ SP ++ ] = R6; - - [ P5 ++ ] = R1; - [ P1 ++ ] = R2; - [ P2 ++ ] = R3; - [ P3 ++ ] = R4; - [ P4 ++ ] = R5; - [ FP ++ ] = R6; - [ SP ++ ] = R7; - - [ P5 ++ ] = R2; - [ P1 ++ ] = R3; - [ P2 ++ ] = R4; - [ P3 ++ ] = R5; - [ P4 ++ ] = R6; - [ FP ++ ] = R7; - [ SP ++ ] = R0; - - [ P5 ++ ] = R3; - [ P1 ++ ] = R4; - [ P2 ++ ] = R5; - [ P3 ++ ] = R6; - [ P4 ++ ] = R7; - [ FP ++ ] = R0; - [ SP ++ ] = R1; - - [ P5 ++ ] = R4; - [ P1 ++ ] = R5; - [ P2 ++ ] = R6; - [ P3 ++ ] = R7; - [ P4 ++ ] = R0; - [ FP ++ ] = R1; - [ SP ++ ] = R2; - - [ P5 ++ ] = R5; - [ P1 ++ ] = R6; - [ P2 ++ ] = R7; - [ P3 ++ ] = R0; - [ P4 ++ ] = R1; - [ FP ++ ] = R2; - [ SP ++ ] = R3; - - [ P5 ++ ] = R6; - [ P1 ++ ] = R7; - [ P2 ++ ] = R0; - [ P3 ++ ] = R1; - [ P4 ++ ] = R2; - [ FP ++ ] = R3; - [ SP ++ ] = R4; - - [ P5 ++ ] = R7; - [ P1 ++ ] = R0; - [ P2 ++ ] = R1; - [ P3 ++ ] = R2; - [ P4 ++ ] = R3; - [ FP ++ ] = R4; - [ SP ++ ] = R5; - -// Read back and check - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym i1, DATA_ADDR_4; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - loadsym i3, DATA_ADDR_7; - P3 = I1; SP = I3; - - R0 = [ P1 ++ ]; - R1 = [ P2 ++ ]; - R2 = [ P3 ++ ]; - R3 = [ P4 ++ ]; - R4 = [ P5 ++ ]; - R5 = [ FP ++ ]; - R6 = [ SP ++ ]; - CHECKREG r0, 0x1B342618; - CHECKREG r1, 0x2C453729; - CHECKREG r2, 0x3D56483A; - CHECKREG r3, 0x4E67594B; - CHECKREG r4, 0x0A231507; - CHECKREG r5, 0x5F786A5C; - CHECKREG r6, 0x60897B6D; - CHECKREG r7, 0x719A8C7E; - - R1 = [ P1 ++ ]; - R2 = [ P2 ++ ]; - R3 = [ P3 ++ ]; - R4 = [ P4 ++ ]; - R5 = [ P5 ++ ]; - R6 = [ FP ++ ]; - R7 = [ SP ++ ]; - CHECKREG r0, 0x1B342618; - CHECKREG r1, 0x2C453729; - CHECKREG r2, 0x3D56483A; - CHECKREG r3, 0x4E67594B; - CHECKREG r4, 0x5F786A5C; - CHECKREG r5, 0x1B342618; - CHECKREG r6, 0x60897B6D; - CHECKREG r7, 0x719A8C7E; - - R2 = [ P1 ++ ]; - R3 = [ P2 ++ ]; - R4 = [ P3 ++ ]; - R5 = [ P4 ++ ]; - R6 = [ P5 ++ ]; - R7 = [ FP ++ ]; - R0 = [ SP ++ ]; - CHECKREG r0, 0x0A231507; - CHECKREG r1, 0x2C453729; - CHECKREG r2, 0x3D56483A; - CHECKREG r3, 0x4E67594B; - CHECKREG r4, 0x5F786A5C; - CHECKREG r5, 0x60897B6D; - CHECKREG r6, 0x2C453729; - CHECKREG r7, 0x719A8C7E; - - R3 = [ P1 ++ ]; - R4 = [ P2 ++ ]; - R5 = [ P3 ++ ]; - R6 = [ P4 ++ ]; - R7 = [ P5 ++ ]; - R0 = [ FP ++ ]; - R1 = [ SP ++ ]; - CHECKREG r0, 0x0A231507; - CHECKREG r1, 0x1B342618; - CHECKREG r2, 0x3D56483A; - CHECKREG r3, 0x4E67594B; - CHECKREG r4, 0x5F786A5C; - CHECKREG r5, 0x60897B6D; - CHECKREG r6, 0x719A8C7E; - CHECKREG r7, 0x3D56483A; - - R4 = [ P1 ++ ]; - R5 = [ P2 ++ ]; - R6 = [ P3 ++ ]; - R7 = [ P4 ++ ]; - R0 = [ P5 ++ ]; - R1 = [ FP ++ ]; - R2 = [ SP ++ ]; - CHECKREG r0, 0x4E67594B; - CHECKREG r1, 0x1B342618; - CHECKREG r2, 0x2C453729; - CHECKREG r3, 0x4E67594B; - CHECKREG r4, 0x5F786A5C; - CHECKREG r5, 0x60897B6D; - CHECKREG r6, 0x719A8C7E; - CHECKREG r7, 0x0A231507; - - R5 = [ P1 ++ ]; - R6 = [ P2 ++ ]; - R7 = [ P3 ++ ]; - R0 = [ P4 ++ ]; - R1 = [ P5 ++ ]; - R2 = [ FP ++ ]; - R3 = [ SP ++ ]; - CHECKREG r0, 0x1B342618; - CHECKREG r1, 0x5F786A5C; - CHECKREG r2, 0x2C453729; - CHECKREG r3, 0x3D56483A; - CHECKREG r4, 0x5F786A5C; - CHECKREG r5, 0x60897B6D; - CHECKREG r6, 0x719A8C7E; - CHECKREG r7, 0x0A231507; - - R6 = [ P1 ++ ]; - R7 = [ P2 ++ ]; - R0 = [ P3 ++ ]; - R1 = [ P4 ++ ]; - R2 = [ P5 ++ ]; - R3 = [ FP ++ ]; - R4 = [ SP ++ ]; - CHECKREG r0, 0x1B342618; - CHECKREG r1, 0x2C453729; - CHECKREG r2, 0x60897B6D; - CHECKREG r3, 0x3D56483A; - CHECKREG r4, 0x4E67594B; - CHECKREG r5, 0x60897B6D; - CHECKREG r6, 0x719A8C7E; - CHECKREG r7, 0x0A231507; - - R7 = [ P1 ++ ]; - R0 = [ P2 ++ ]; - R1 = [ P3 ++ ]; - R2 = [ P4 ++ ]; - R3 = [ P5 ++ ]; - R4 = [ FP ++ ]; - R5 = [ SP ++ ]; - CHECKREG r0, 0x1B342618; - CHECKREG r1, 0x2C453729; - CHECKREG r2, 0x3D56483A; - CHECKREG r3, 0x719A8C7E; - CHECKREG r4, 0x4E67594B; - CHECKREG r5, 0x5F786A5C; - CHECKREG r6, 0x719A8C7E; - CHECKREG r7, 0x0A231507; - -// reset values - imm32 r0, 0x1a235507; - imm32 r1, 0x12342518; - imm32 r2, 0x23353729; - imm32 r3, 0x3f54483a; - imm32 r4, 0x4467694b; - imm32 r5, 0x5ff86a5c; - imm32 r6, 0x608b7b1d; - imm32 r7, 0x719a8c71; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x20; - loadsym p1, DATA_ADDR_2, 0x20; - loadsym p2, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym p4, DATA_ADDR_5, 0x20; - loadsym fp, DATA_ADDR_6, 0x20; - loadsym i3, DATA_ADDR_7, 0x20; - P3 = I1; SP = I3; - - [ P5 -- ] = R0; - [ P1 -- ] = R1; - [ P2 -- ] = R2; - [ P3 -- ] = R3; - [ P4 -- ] = R4; - [ FP -- ] = R5; - [ SP -- ] = R6; - - [ P5 -- ] = R1; - [ P1 -- ] = R2; - [ P2 -- ] = R3; - [ P3 -- ] = R4; - [ P4 -- ] = R5; - [ FP -- ] = R6; - [ SP -- ] = R7; - - [ P5 -- ] = R2; - [ P1 -- ] = R3; - [ P2 -- ] = R4; - [ P3 -- ] = R5; - [ P4 -- ] = R6; - [ FP -- ] = R7; - [ SP -- ] = R0; - - [ P5 -- ] = R3; - [ P1 -- ] = R4; - [ P2 -- ] = R5; - [ P3 -- ] = R6; - [ P4 -- ] = R7; - [ FP -- ] = R0; - [ SP -- ] = R1; - - [ P5 -- ] = R4; - [ P1 -- ] = R5; - [ P2 -- ] = R6; - [ P3 -- ] = R7; - [ P4 -- ] = R0; - [ FP -- ] = R1; - [ SP -- ] = R2; - - [ P5 -- ] = R5; - [ P1 -- ] = R6; - [ P2 -- ] = R7; - [ P3 -- ] = R0; - [ P4 -- ] = R1; - [ FP -- ] = R2; - [ SP -- ] = R3; - - [ P5 -- ] = R6; - [ P1 -- ] = R7; - [ P2 -- ] = R0; - [ P3 -- ] = R1; - [ P4 -- ] = R2; - [ FP -- ] = R3; - [ SP -- ] = R4; - - [ P5 -- ] = R7; - [ P1 -- ] = R0; - [ P2 -- ] = R1; - [ P3 -- ] = R2; - [ P4 -- ] = R3; - [ FP -- ] = R4; - [ SP -- ] = R5; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x20; - loadsym p1, DATA_ADDR_2, 0x20; - loadsym p2, DATA_ADDR_3, 0x20; - loadsym i1, DATA_ADDR_4, 0x20; - loadsym p4, DATA_ADDR_5, 0x20; - loadsym fp, DATA_ADDR_6, 0x20; - loadsym i3, DATA_ADDR_7, 0x20; - P3 = I1; SP = I3; - - R0 = [ P1 -- ]; - R1 = [ P2 -- ]; - R2 = [ P3 -- ]; - R3 = [ P4 -- ]; - R4 = [ P5 -- ]; - R5 = [ FP -- ]; - R6 = [ SP -- ]; - CHECKREG r0, 0x12342518; - CHECKREG r1, 0x23353729; - CHECKREG r2, 0x3F54483A; - CHECKREG r3, 0x4467694B; - CHECKREG r4, 0x1A235507; - CHECKREG r5, 0x5FF86A5C; - CHECKREG r6, 0x608B7B1D; - CHECKREG r7, 0x719A8C71; - - R1 = [ P1 -- ]; - R2 = [ P2 -- ]; - R3 = [ P3 -- ]; - R4 = [ P4 -- ]; - R5 = [ P5 -- ]; - R6 = [ FP -- ]; - R7 = [ SP -- ]; - CHECKREG r0, 0x12342518; - CHECKREG r1, 0x23353729; - CHECKREG r2, 0x3F54483A; - CHECKREG r3, 0x4467694B; - CHECKREG r4, 0x5FF86A5C; - CHECKREG r5, 0x12342518; - CHECKREG r6, 0x608B7B1D; - CHECKREG r7, 0x719A8C71; - - R2 = [ P1 -- ]; - R3 = [ P2 -- ]; - R4 = [ P3 -- ]; - R5 = [ P4 -- ]; - R6 = [ P5 -- ]; - R7 = [ FP -- ]; - R0 = [ SP -- ]; - CHECKREG r0, 0x1A235507; - CHECKREG r1, 0x23353729; - CHECKREG r2, 0x3F54483A; - CHECKREG r3, 0x4467694B; - CHECKREG r4, 0x5FF86A5C; - CHECKREG r5, 0x608B7B1D; - CHECKREG r6, 0x23353729; - CHECKREG r7, 0x719A8C71; - - R3 = [ P1 -- ]; - R4 = [ P2 -- ]; - R5 = [ P3 -- ]; - R6 = [ P4 -- ]; - R7 = [ P5 -- ]; - R0 = [ FP -- ]; - R1 = [ SP -- ]; - CHECKREG r0, 0x1A235507; - CHECKREG r1, 0x12342518; - CHECKREG r2, 0x3F54483A; - CHECKREG r3, 0x4467694B; - CHECKREG r4, 0x5FF86A5C; - CHECKREG r5, 0x608B7B1D; - CHECKREG r6, 0x719A8C71; - CHECKREG r7, 0x3F54483A; - - R4 = [ P1 -- ]; - R5 = [ P2 -- ]; - R6 = [ P3 -- ]; - R7 = [ P4 -- ]; - R0 = [ P5 -- ]; - R1 = [ FP -- ]; - R2 = [ SP -- ]; - CHECKREG r0, 0x4467694B; - CHECKREG r1, 0x12342518; - CHECKREG r2, 0x23353729; - CHECKREG r3, 0x4467694B; - CHECKREG r4, 0x5FF86A5C; - CHECKREG r5, 0x608B7B1D; - CHECKREG r6, 0x719A8C71; - CHECKREG r7, 0x1A235507; - - R5 = [ P1 -- ]; - R6 = [ P2 -- ]; - R7 = [ P3 -- ]; - R0 = [ P4 -- ]; - R1 = [ P5 -- ]; - R2 = [ FP -- ]; - R3 = [ SP -- ]; - CHECKREG r0, 0x12342518; - CHECKREG r1, 0x5FF86A5C; - CHECKREG r2, 0x23353729; - CHECKREG r3, 0x3F54483A; - CHECKREG r4, 0x5FF86A5C; - CHECKREG r5, 0x608B7B1D; - CHECKREG r6, 0x719A8C71; - CHECKREG r7, 0x1A235507; - - R6 = [ P1 -- ]; - R7 = [ P2 -- ]; - R0 = [ P3 -- ]; - R1 = [ P4 -- ]; - R2 = [ P5 -- ]; - R3 = [ FP -- ]; - R4 = [ SP -- ]; - CHECKREG r0, 0x12342518; - CHECKREG r1, 0x23353729; - CHECKREG r2, 0x608B7B1D; - CHECKREG r3, 0x3F54483A; - CHECKREG r4, 0x4467694B; - CHECKREG r5, 0x608B7B1D; - CHECKREG r6, 0x719A8C71; - CHECKREG r7, 0x1A235507; - - R7 = [ P1 -- ]; - R0 = [ P2 -- ]; - R1 = [ P3 -- ]; - R2 = [ P4 -- ]; - R3 = [ P5 -- ]; - R4 = [ FP -- ]; - R5 = [ SP -- ]; - CHECKREG r0, 0x12342518; - CHECKREG r1, 0x23353729; - CHECKREG r2, 0x3F54483A; - CHECKREG r3, 0x719A8C71; - CHECKREG r4, 0x4467694B; - CHECKREG r5, 0x5FF86A5C; - CHECKREG r6, 0x719A8C71; - CHECKREG r7, 0x1A235507; - - P3 = I1; SP = I3; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_7: - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_b.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_b.s deleted file mode 100644 index 823aa9b..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_b.s +++ /dev/null @@ -1,455 +0,0 @@ -//Original:/testcases/core/c_ldst_st_p_d_pp_b/c_ldst_st_p_d_pp_b.dsp -// Spec Reference: c_ldst st_p++ b byte -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x0a231507; - imm32 r1, 0x1b342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f786a5c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c7e; - - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - -// store incremented by 1 loc - B [ P5 ++ ] = R0; - B [ P1 ++ ] = R1; - B [ P2 ++ ] = R2; - B [ P4 ++ ] = R4; - B [ FP ++ ] = R5; - - B [ P5 ++ ] = R1; - B [ P1 ++ ] = R2; - B [ P2 ++ ] = R3; - B [ P4 ++ ] = R5; - B [ FP ++ ] = R6; - - B [ P5 ++ ] = R2; - B [ P1 ++ ] = R3; - B [ P2 ++ ] = R4; - B [ P4 ++ ] = R6; - B [ FP ++ ] = R7; - - B [ P5 ++ ] = R3; - B [ P1 ++ ] = R4; - B [ P2 ++ ] = R5; - B [ P4 ++ ] = R7; - B [ FP ++ ] = R0; - - B [ P5 ++ ] = R4; - B [ P1 ++ ] = R5; - B [ P2 ++ ] = R6; - B [ P4 ++ ] = R0; - B [ FP ++ ] = R1; - - B [ P5 ++ ] = R5; - B [ P1 ++ ] = R6; - B [ P2 ++ ] = R7; - B [ P4 ++ ] = R1; - B [ FP ++ ] = R2; - - B [ P5 ++ ] = R6; - B [ P1 ++ ] = R7; - B [ P2 ++ ] = R0; - B [ P4 ++ ] = R2; - B [ FP ++ ] = R3; - - B [ P5 ++ ] = R7; - B [ P1 ++ ] = R0; - B [ P2 ++ ] = R1; - B [ P4 ++ ] = R3; - B [ FP ++ ] = R4; - -// Read back and check - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - R0 = [ P1 ++ ]; - R1 = [ P2 ++ ]; - R3 = [ P4 ++ ]; - R4 = [ P5 ++ ]; - R5 = [ FP ++ ]; - CHECKREG r0, 0x4B3A2918; - CHECKREG r1, 0x5C4B3A29; - CHECKREG r3, 0x7E6D5C4B; - CHECKREG r4, 0x3A291807; - CHECKREG r5, 0x077E6D5C; - CHECKREG r7, 0x719A8C7E; - R1 = [ P1 ++ ]; - R2 = [ P2 ++ ]; - R4 = [ P4 ++ ]; - R5 = [ P5 ++ ]; - R6 = [ FP ++ ]; - CHECKREG r0, 0x4B3A2918; - CHECKREG r1, 0x077E6D5C; - CHECKREG r2, 0x18077E6D; - CHECKREG r4, 0x3A291807; - CHECKREG r5, 0x7E6D5C4B; - CHECKREG r6, 0x4B3A2918; - R2 = [ P1 ++ ]; - R3 = [ P2 ++ ]; - R5 = [ P4 ++ ]; - R6 = [ P5 ++ ]; - R7 = [ FP ++ ]; - CHECKREG r1, 0x077E6D5C; - CHECKREG r2, 0x28292A2B; - CHECKREG r3, 0x48494A4B; - CHECKREG r5, 0x88898A8B; - CHECKREG r6, 0x08090A0B; - CHECKREG r7, 0xA8A9AAAB; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - .data - -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_7: - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_h.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_h.s deleted file mode 100644 index c8b453a..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_h.s +++ /dev/null @@ -1,457 +0,0 @@ -//Original:/testcases/core/c_ldst_st_p_d_pp_h/c_ldst_st_p_d_pp_h.dsp -// Spec Reference: c_ldst st_p++/p-- h half -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - imm32 r0, 0x0a231507; - imm32 r1, 0x1b342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f786a5c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c7e; - - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - -// half word 16-bit store incremented by 2 - W [ P5 ++ ] = R0; - W [ P1 ++ ] = R1; - W [ P2 ++ ] = R2; - W [ P4 ++ ] = R4; - W [ FP ++ ] = R5; - - W [ P5 ++ ] = R1; - W [ P1 ++ ] = R2; - W [ P2 ++ ] = R3; - W [ P4 ++ ] = R5; - W [ FP ++ ] = R6; - - W [ P5 ++ ] = R2; - W [ P1 ++ ] = R3; - W [ P2 ++ ] = R4; - W [ P4 ++ ] = R6; - W [ FP ++ ] = R7; - - W [ P5 ++ ] = R3; - W [ P1 ++ ] = R4; - W [ P2 ++ ] = R5; - W [ P4 ++ ] = R7; - W [ FP ++ ] = R0; - - W [ P5 ++ ] = R4; - W [ P1 ++ ] = R5; - W [ P2 ++ ] = R6; - W [ P4 ++ ] = R0; - W [ FP ++ ] = R1; - - W [ P5 ++ ] = R5; - W [ P1 ++ ] = R6; - W [ P2 ++ ] = R7; - W [ P4 ++ ] = R1; - W [ FP ++ ] = R2; - - W [ P5 ++ ] = R6; - W [ P1 ++ ] = R7; - W [ P2 ++ ] = R0; - W [ P4 ++ ] = R2; - W [ FP ++ ] = R3; - - W [ P5 ++ ] = R7; - W [ P1 ++ ] = R0; - W [ P2 ++ ] = R1; - W [ P4 ++ ] = R3; - W [ FP ++ ] = R4; - -// Read back and check - loadsym p5, DATA_ADDR_1; - loadsym p1, DATA_ADDR_2; - loadsym p2, DATA_ADDR_3; - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - R0 = [ P1 ++ ]; - R1 = [ P2 ++ ]; - R3 = [ P4 ++ ]; - R4 = [ P5 ++ ]; - R5 = [ FP ++ ]; - CHECKREG r0, 0x37292618; - CHECKREG r1, 0x483A3729; - CHECKREG r3, 0x6A5C594B; - CHECKREG r4, 0x26181507; - CHECKREG r5, 0x7B6D6A5C; - CHECKREG r7, 0x719A8C7E; - R1 = [ P1 ++ ]; - R2 = [ P2 ++ ]; - R4 = [ P4 ++ ]; - R5 = [ P5 ++ ]; - R6 = [ FP ++ ]; - CHECKREG r0, 0x37292618; - CHECKREG r1, 0x594B483A; - CHECKREG r2, 0x6A5C594B; - CHECKREG r4, 0x8C7E7B6D; - CHECKREG r5, 0x483A3729; - CHECKREG r6, 0x15078C7E; - R2 = [ P1 ++ ]; - R3 = [ P2 ++ ]; - R5 = [ P4 ++ ]; - R6 = [ P5 ++ ]; - R7 = [ FP ++ ]; - CHECKREG r1, 0x594B483A; - CHECKREG r2, 0x7B6D6A5C; - CHECKREG r3, 0x8C7E7B6D; - CHECKREG r5, 0x26181507; - CHECKREG r6, 0x6A5C594B; - CHECKREG r7, 0x37292618; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - .data - -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_7: - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_p.s b/sim/testsuite/sim/bfin/c_ldst_st_p_p.s deleted file mode 100644 index 1cc87a1..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_st_p_p.s +++ /dev/null @@ -1,128 +0,0 @@ -//Original:/testcases/core/c_ldst_st_p_p/c_ldst_st_p_p.dsp -// Spec Reference: c_ldst st_p_p -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x0a231507; - imm32 r1, 0x1b342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f786a5c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c7e; - -// initial values p-p - imm32 p5, 0x0a231507; - imm32 p1, 0x1b342618; - imm32 p2, 0x2c453729; - - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - [ P4 ] = P1; - [ FP ] = P2; - R5 = [ P4 ]; - R6 = [ FP ]; - CHECKREG r5, 0x1B342618; - CHECKREG r6, 0x2C453729; - - [ P4 ] = P2; - [ FP ] = R3; - R5 = [ P4 ]; - R6 = [ FP ]; - CHECKREG r5, 0x2C453729; - CHECKREG r6, 0x3D56483A; - - [ P4 ] = R3; - [ FP ] = P5; - R5 = [ P4 ]; - R6 = [ FP ]; - CHECKREG r5, 0x3D56483A; - CHECKREG r6, 0x0A231507; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - .data - -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - -DATA_ADDR_6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - -DATA_ADDR_7: - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_p_mm.s b/sim/testsuite/sim/bfin/c_ldst_st_p_p_mm.s deleted file mode 100644 index e7dd3cd..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_st_p_p_mm.s +++ /dev/null @@ -1,428 +0,0 @@ -//Original:testcases/core/c_ldst_st_p_p_mm/c_ldst_st_p_p_mm.dsp -// Spec Reference: c_ldst st p-- p -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -INIT_I_REGS -1; -init_b_regs 0; -init_l_regs 0; -init_m_regs -1; -I0 = P3; -I2 = SP; - - imm32 r0, 0x0a231507; - imm32 r1, 0x1b342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f786a5c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c7e; - -// initial values p-p - imm32 p5, 0x0a231507; - imm32 p1, 0x1b342618; - imm32 p2, 0x2c453729; - imm32 p3, 0x4356789a; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p4, DATA_ADDR_5, 0x18; - loadsym fp, DATA_ADDR_6, 0x18; - loadsym i3, DATA_ADDR_7, 0x18; - P3 = I1; SP = I3; - - [ P4 -- ] = P1; - [ FP -- ] = P2; - [ SP -- ] = R3; - - [ P4 -- ] = P2; - [ FP -- ] = P3; - [ SP -- ] = P5; - - [ P4 -- ] = P3; - [ FP -- ] = P5; - [ SP -- ] = P1; - - [ P4 -- ] = P5; - [ FP -- ] = P1; - [ SP -- ] = P2; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p4, DATA_ADDR_5, 0x18; - loadsym fp, DATA_ADDR_6, 0x18; - loadsym i3, DATA_ADDR_7, 0x18; - P3 = I1; SP = I3; - - R1 = [ P4 -- ]; - R2 = [ FP -- ]; - R3 = [ SP -- ]; - R4 = [ P4 -- ]; - R5 = [ FP -- ]; - R6 = [ SP -- ]; - CHECKREG r1, 0x1B342618; - CHECKREG r2, 0x2C453729; - CHECKREG r3, 0x3D56483A; - CHECKREG r4, 0x2C453729; - CHECKREG r5, 0x4356789A; - CHECKREG r6, 0x0A231507; - R1 = [ P4 -- ]; - R2 = [ FP -- ]; - R3 = [ SP -- ]; - R4 = [ P4 -- ]; - R5 = [ FP -- ]; - R6 = [ SP -- ]; - CHECKREG r1, 0x4356789A; - CHECKREG r2, 0x0A231507; - CHECKREG r3, 0x1B342618; - CHECKREG r4, 0x0A231507; - CHECKREG r5, 0x1B342618; - CHECKREG r6, 0x2C453729; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x10000080 - .dd 0x02000800 - .dd 0x00207000 - .dd 0x000d0000 - .dd 0x0006b000 - .dd 0x00500a00 - .dd 0x0d0000f0 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0x10006000 - .dd 0xa2050800 - .dd 0x0c30db00 - .dd 0x00b40000 - .dd 0xa0045000 - .dd 0x0000f600 - .dd 0x00d00070 - .dd 0x00000008 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_7: - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF - .dd 0x10000000 - .dd 0x0d000000 - .dd 0x00400000 - .dd 0x000b0000 - .dd 0x000d0b00 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_p_pp.s b/sim/testsuite/sim/bfin/c_ldst_st_p_p_pp.s deleted file mode 100644 index c8068de..0000000 --- a/sim/testsuite/sim/bfin/c_ldst_st_p_p_pp.s +++ /dev/null @@ -1,397 +0,0 @@ -//Original:/testcases/core/c_ldst_st_p_p_pp/c_ldst_st_p_p_pp.dsp -// Spec Reference: c_ldst st p++ p -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x0a231507; - imm32 r1, 0x1b342618; - imm32 r2, 0x2c453729; - imm32 r3, 0x3d56483a; - imm32 r4, 0x4e67594b; - imm32 r5, 0x5f786a5c; - imm32 r6, 0x60897b6d; - imm32 r7, 0x719a8c7e; - -// initial values p-p - imm32 p5, 0x0a231507; - imm32 p1, 0x1b342618; - imm32 p2, 0x2c453729; - imm32 p0, 0x125afbd3; - - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - - [ P4 ++ ] = P1; - [ FP ++ ] = P2; - - [ P4 ++ ] = P2; - [ FP ++ ] = P0; - - [ P4 ++ ] = P0; - [ FP ++ ] = P5; - - loadsym p4, DATA_ADDR_5; - loadsym fp, DATA_ADDR_6; - R1 = [ P4 ++ ]; - R2 = [ FP ++ ]; - R4 = [ P4 ++ ]; - R5 = [ FP ++ ]; - CHECKREG r1, 0x1B342618; - CHECKREG r2, 0x2C453729; - CHECKREG r4, 0x2C453729; - CHECKREG r5, 0x125AFBD3; - R1 = [ P4 ++ ]; - R2 = [ FP ++ ]; - R4 = [ P4 ++ ]; - R5 = [ FP ++ ]; - CHECKREG r1, 0x125AFBD3; - CHECKREG r2, 0x0A231507; - CHECKREG r4, 0x8C8D8E8F; - CHECKREG r5, 0xACADAEAF; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - .data - -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_6: - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -DATA_ADDR_7: - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_b.s b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_b.s deleted file mode 100644 index 74b4222..0000000 --- a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_b.s +++ /dev/null @@ -1,554 +0,0 @@ -//Original:testcases/core/c_ldstidxl_ld_dr_b/c_ldstidxl_ld_dr_b.dsp -// Spec Reference: c_ldstidxl load dreg B (ld with indexed addressing) -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; - -// initial values - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0xA0; - loadsym p4, DATA_ADDR_2, 0x70; - loadsym p5, DATA_ADDR_1, 0x70; - loadsym fp, DATA_ADDR_2, 0x70; - - R0 = B [ P1 + 151 ] (Z); - R1 = B [ P1 + 83 ] (Z); - R2 = B [ P1 + 45 ] (Z); - R3 = B [ P1 + 17 ] (Z); - R4 = B [ P1 + 39 ] (Z); - R5 = B [ P1 + 21 ] (Z); - R6 = B [ P1 + 123 ] (Z); - R7 = B [ P1 + 155 ] (Z); - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000018; - CHECKREG r2, 0x00000076; - CHECKREG r3, 0x00000012; - CHECKREG r4, 0x00000055; - CHECKREG r5, 0x00000016; - CHECKREG r6, 0x00000058; - CHECKREG r7, 0x00000004; - - R0 = B [ P2 + -121 ] (Z); - R1 = B [ P2 + -113 ] (Z); - R2 = B [ P2 + -35 ] (Z); - R3 = B [ P2 + -27 ] (Z); - R4 = B [ P2 + -49 ] (Z); - R5 = B [ P2 + -5 ] (Z); - R6 = B [ P2 + -51 ] (Z); - R7 = B [ P2 + -147 ] (Z); - CHECKREG r0, 0x000000CF; - CHECKREG r1, 0x000000D7; - CHECKREG r2, 0x00000056; - CHECKREG r3, 0x00000064; - CHECKREG r4, 0x00000094; - CHECKREG r5, 0x0000004C; - CHECKREG r6, 0x00000099; - CHECKREG r7, 0x0000004E; - - R0 = B [ P4 + 47 ] (Z); - R1 = B [ P4 + -41 ] (Z); - R2 = B [ P4 + 38 ] (Z); - R3 = B [ P4 + -31 ] (Z); - R4 = B [ P4 + 28 ] (Z); - R5 = B [ P4 + 26 ] (Z); - R6 = B [ P4 + -22 ] (Z); - R7 = B [ P4 + 105 ] (Z); - CHECKREG r0, 0x00000050; - CHECKREG r1, 0x00000093; - CHECKREG r2, 0x00000049; - CHECKREG r3, 0x00000099; - CHECKREG r4, 0x00000043; - CHECKREG r5, 0x00000067; - CHECKREG r6, 0x000000E8; - CHECKREG r7, 0x00000099; - - R0 = B [ P5 + -14 ] (Z); - R1 = B [ P5 + 12 ] (Z); - R2 = B [ P5 + -6 ] (Z); - R3 = B [ P5 + 4 ] (Z); - R4 = B [ P5 + 0 ] (Z); - R5 = B [ P5 + -2 ] (Z); - R6 = B [ P5 + 8 ] (Z); - R7 = B [ P5 + -107 ] (Z); - CHECKREG r0, 0x00000035; - CHECKREG r1, 0x00000065; - CHECKREG r2, 0x00000043; - CHECKREG r3, 0x00000057; - CHECKREG r4, 0x00000053; - CHECKREG r5, 0x00000047; - CHECKREG r6, 0x00000061; - CHECKREG r7, 0x00000006; - - R0 = B [ FP + 99 ] (Z); - R1 = B [ FP + -15 ] (Z); - R2 = B [ FP + 41 ] (Z); - R3 = B [ FP + -65 ] (Z); - R4 = B [ FP + 25 ] (Z); - R5 = B [ FP + -34 ] (Z); - R6 = B [ FP + 37 ] (Z); - R7 = B [ FP + -97 ] (Z); - CHECKREG r0, 0x00000093; - CHECKREG r1, 0x00000099; - CHECKREG r2, 0x0000004E; - CHECKREG r3, 0x000000D7; - CHECKREG r4, 0x00000068; - CHECKREG r5, 0x000000E8; - CHECKREG r6, 0x0000004A; - CHECKREG r7, 0x0000004C; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - -DATA_ADDR_2: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_h.s b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_h.s deleted file mode 100644 index 334ad17..0000000 --- a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_h.s +++ /dev/null @@ -1,595 +0,0 @@ -//Original:testcases/core/c_ldstidxl_ld_dr_h/c_ldstidxl_ld_dr_h.dsp -// Spec Reference: c_ldstidxl load dreg H (ld with indexed addressing) -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0xA0; - loadsym i1, DATA_ADDR_1, 0x70; - loadsym p4, DATA_ADDR_2, 0x70; - loadsym p5, DATA_ADDR_1, 0x70; - loadsym fp, DATA_ADDR_2, 0x70; - loadsym i3, DATA_ADDR_1, 0x70; - P3 = I1; SP = I3; - - R0 = W [ P1 + 154 ] (Z); - R1 = W [ P1 + 84 ] (Z); - R2 = W [ P1 + 48 ] (Z); - R3 = W [ P1 + 10 ] (Z); - R4 = W [ P1 + 34 ] (Z); - R5 = W [ P1 + 20 ] (Z); - R6 = W [ P1 + 126 ] (Z); - R7 = W [ P1 + 154 ] (Z); - CHECKREG r0, 0x00000405; - CHECKREG r1, 0x00002425; - CHECKREG r2, 0x00008485; - CHECKREG r3, 0x00000809; - CHECKREG r4, 0x00001122; - CHECKREG r5, 0x00001617; - CHECKREG r6, 0x00006263; - CHECKREG r7, 0x00000405; - - R0 = W [ P2 + -120 ] (Z); - R1 = W [ P2 + -114 ] (Z); - R2 = W [ P2 + -36 ] (Z); - R3 = W [ P2 + -22 ] (Z); - R4 = W [ P2 + -44 ] (Z); - R5 = W [ P2 + -6 ] (Z); - R6 = W [ P2 + -52 ] (Z); - R7 = W [ P2 + -146 ] (Z); - CHECKREG r0, 0x0000D5D6; - CHECKREG r1, 0x0000D7D8; - CHECKREG r2, 0x0000565A; - CHECKREG r3, 0x0000A667; - CHECKREG r4, 0x000099EA; - CHECKREG r5, 0x00004C4D; - CHECKREG r6, 0x000099EA; - CHECKREG r7, 0x00004C4D; - - R0 = W [ P3 + 56 ] (Z); - R1 = W [ P3 + 62 ] (Z); - R2 = W [ P3 + -64 ] (Z); - R3 = W [ P3 + 60 ] (Z); - R4 = W [ P3 + -56 ] (Z); - R5 = W [ P3 + 10 ] (Z); - R6 = W [ P3 + -28 ] (Z); - R7 = W [ P3 + -110 ] (Z); - CHECKREG r0, 0x00001617; - CHECKREG r1, 0x00001819; - CHECKREG r2, 0x00008485; - CHECKREG r3, 0x00001A1B; - CHECKREG r4, 0x00008283; - CHECKREG r5, 0x00005859; - CHECKREG r6, 0x00002425; - CHECKREG r7, 0x00000001; - - R0 = W [ P4 + 42 ] (Z); - R1 = W [ P4 + -40 ] (Z); - R2 = W [ P4 + 38 ] (Z); - R3 = W [ P4 + -32 ] (Z); - R4 = W [ P4 + 28 ] (Z); - R5 = W [ P4 + 26 ] (Z); - R6 = W [ P4 + -22 ] (Z); - R7 = W [ P4 + 106 ] (Z); - CHECKREG r0, 0x00004C4D; - CHECKREG r1, 0x000099EA; - CHECKREG r2, 0x00004849; - CHECKREG r3, 0x000099EA; - CHECKREG r4, 0x00004243; - CHECKREG r5, 0x0000A667; - CHECKREG r6, 0x000098E8; - CHECKREG r7, 0x000095E8; - - R0 = W [ P5 + -14 ] (Z); - R1 = W [ P5 + 12 ] (Z); - R2 = W [ P5 + -6 ] (Z); - R3 = W [ P5 + 4 ] (Z); - R4 = W [ P5 + 0 ] (Z); - R5 = W [ P5 + -2 ] (Z); - R6 = W [ P5 + 8 ] (Z); - R7 = W [ P5 + -108 ] (Z); - CHECKREG r0, 0x00003435; - CHECKREG r1, 0x00006465; - CHECKREG r2, 0x00004243; - CHECKREG r3, 0x00005657; - CHECKREG r4, 0x00005253; - CHECKREG r5, 0x00004647; - CHECKREG r6, 0x00006061; - CHECKREG r7, 0x00000607; - - R0 = W [ FP + 90 ] (Z); - R1 = W [ FP + -14 ] (Z); - R2 = W [ FP + 42 ] (Z); - R3 = W [ FP + -66 ] (Z); - R4 = W [ FP + 26 ] (Z); - R5 = W [ FP + -34 ] (Z); - R6 = W [ FP + 38 ] (Z); - R7 = W [ FP + -98 ] (Z); - CHECKREG r0, 0x000091E8; - CHECKREG r1, 0x000091E8; - CHECKREG r2, 0x00004C4D; - CHECKREG r3, 0x0000D7D8; - CHECKREG r4, 0x0000A667; - CHECKREG r5, 0x000095E8; - CHECKREG r6, 0x00004849; - CHECKREG r7, 0x00004C4D; - - R0 = W [ SP + 46 ] (Z); - R1 = W [ SP + -42 ] (Z); - R2 = W [ SP + 48 ] (Z); - R3 = W [ SP + 50 ] (Z); - R4 = W [ SP + -102 ] (Z); - R5 = W [ SP + 82 ] (Z); - R6 = W [ SP + 62 ] (Z); - R7 = W [ SP + 46 ] (Z); - CHECKREG r0, 0x00000809; - CHECKREG r1, 0x00000506; - CHECKREG r2, 0x00000E0F; - CHECKREG r3, 0x00000C0D; - CHECKREG r4, 0x00000809; - CHECKREG r5, 0x00007475; - CHECKREG r6, 0x00001819; - CHECKREG r7, 0x00000809; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - -DATA_ADDR_2: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xb.s b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xb.s deleted file mode 100644 index e5a3515..0000000 --- a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xb.s +++ /dev/null @@ -1,594 +0,0 @@ -//Original:testcases/core/c_ldstidxl_ld_dr_xb/c_ldstidxl_ld_dr_xb.dsp -// Spec Reference: c_ldstidxl load dreg XB (ld with indexed addressing) -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0xA0; - loadsym i1, DATA_ADDR_1, 0x70; - loadsym p4, DATA_ADDR_2, 0x70; - loadsym p5, DATA_ADDR_1, 0x70; - loadsym fp, DATA_ADDR_2, 0x70; - loadsym i3, DATA_ADDR_1, 0x70; - P3 = I1; SP = I3; - - R0 = B [ P1 + 151 ] (X); - R1 = B [ P1 + 83 ] (X); - R2 = B [ P1 + 45 ] (X); - R3 = B [ P1 + 17 ] (X); - R4 = B [ P1 + 39 ] (X); - R5 = B [ P1 + 21 ] (X); - R6 = B [ P1 + 123 ] (X); - R7 = B [ P1 + 155 ] (X); - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000018; - CHECKREG r2, 0x00000076; - CHECKREG r3, 0x00000012; - CHECKREG r4, 0x00000055; - CHECKREG r5, 0x00000016; - CHECKREG r6, 0x00000058; - CHECKREG r7, 0x00000004; - - R0 = B [ P2 + -121 ] (X); - R1 = B [ P2 + -113 ] (X); - R2 = B [ P2 + -35 ] (X); - R3 = B [ P2 + -27 ] (X); - R4 = B [ P2 + -49 ] (X); - R5 = B [ P2 + -5 ] (X); - R6 = B [ P2 + -51 ] (X); - R7 = B [ P2 + -147 ] (X); - CHECKREG r0, 0xFFFFFFCF; - CHECKREG r1, 0xFFFFFFD7; - CHECKREG r2, 0x00000056; - CHECKREG r3, 0x00000064; - CHECKREG r4, 0xFFFFFF94; - CHECKREG r5, 0x0000004C; - CHECKREG r6, 0xFFFFFF99; - CHECKREG r7, 0x0000004E; - - R0 = B [ P3 + 56 ] (X); - R1 = B [ P3 + 62 ] (X); - R2 = B [ P3 + -63 ] (X); - R3 = B [ P3 + 61 ] (X); - R4 = B [ P3 + -59 ] (X); - R5 = B [ P3 + 11 ] (X); - R6 = B [ P3 + -23 ] (X); - R7 = B [ P3 + -111 ] (X); - CHECKREG r0, 0x00000017; - CHECKREG r1, 0x00000019; - CHECKREG r2, 0xFFFFFF84; - CHECKREG r3, 0x0000001A; - CHECKREG r4, 0xFFFFFF88; - CHECKREG r5, 0x00000058; - CHECKREG r6, 0x00000028; - CHECKREG r7, 0x00000002; - - R0 = B [ P4 + 47 ] (X); - R1 = B [ P4 + -41 ] (X); - R2 = B [ P4 + 38 ] (X); - R3 = B [ P4 + -31 ] (X); - R4 = B [ P4 + 28 ] (X); - R5 = B [ P4 + 26 ] (X); - R6 = B [ P4 + -22 ] (X); - R7 = B [ P4 + 105 ] (X); - CHECKREG r0, 0x00000050; - CHECKREG r1, 0xFFFFFF93; - CHECKREG r2, 0x00000049; - CHECKREG r3, 0xFFFFFF99; - CHECKREG r4, 0x00000043; - CHECKREG r5, 0x00000067; - CHECKREG r6, 0xFFFFFFE8; - CHECKREG r7, 0xFFFFFF99; - - R0 = B [ P5 + -14 ] (X); - R1 = B [ P5 + 12 ] (X); - R2 = B [ P5 + -6 ] (X); - R3 = B [ P5 + 4 ] (X); - R4 = B [ P5 + 0 ] (X); - R5 = B [ P5 + -2 ] (X); - R6 = B [ P5 + 8 ] (X); - R7 = B [ P5 + -107 ] (X); - CHECKREG r0, 0x00000035; - CHECKREG r1, 0x00000065; - CHECKREG r2, 0x00000043; - CHECKREG r3, 0x00000057; - CHECKREG r4, 0x00000053; - CHECKREG r5, 0x00000047; - CHECKREG r6, 0x00000061; - CHECKREG r7, 0x00000006; - - R0 = B [ FP + 99 ] (X); - R1 = B [ FP + -15 ] (X); - R2 = B [ FP + 41 ] (X); - R3 = B [ FP + -65 ] (X); - R4 = B [ FP + 25 ] (X); - R5 = B [ FP + -34 ] (X); - R6 = B [ FP + 37 ] (X); - R7 = B [ FP + -97 ] (X); - CHECKREG r0, 0xFFFFFF93; - CHECKREG r1, 0xFFFFFF99; - CHECKREG r2, 0x0000004E; - CHECKREG r3, 0xFFFFFFD7; - CHECKREG r4, 0x00000068; - CHECKREG r5, 0xFFFFFFE8; - CHECKREG r6, 0x0000004A; - CHECKREG r7, 0x0000004C; - - R0 = B [ SP + 46 ] (X); - R1 = B [ SP + -41 ] (X); - R2 = B [ SP + 48 ] (X); - R3 = B [ SP + 51 ] (X); - R4 = B [ SP + -102 ] (X); - R5 = B [ SP + 89 ] (X); - R6 = B [ SP + 62 ] (X); - R7 = B [ SP + 43 ] (X); - CHECKREG r0, 0x00000009; - CHECKREG r1, 0x00000005; - CHECKREG r2, 0x0000000F; - CHECKREG r3, 0x0000000C; - CHECKREG r4, 0x00000009; - CHECKREG r5, 0xFFFFFF88; - CHECKREG r6, 0x00000019; - CHECKREG r7, 0x00000004; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - -DATA_ADDR_2: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s deleted file mode 100644 index 7d1dda1..0000000 --- a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s +++ /dev/null @@ -1,595 +0,0 @@ -//Original:testcases/core/c_ldstidxl_ld_dr_xh/c_ldstidxl_ld_dr_xh.dsp -// Spec Reference: c_ldstidxl load dreg XH (ld with indexed addressing) -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0xA0; - loadsym i1, DATA_ADDR_1, 0x70; - loadsym p4, DATA_ADDR_2, 0x70; - loadsym p5, DATA_ADDR_1, 0x70; - loadsym fp, DATA_ADDR_2, 0x70; - loadsym i3, DATA_ADDR_1, 0x70; - P3 = I1; SP = I3; - - R0 = W [ P1 + 154 ] (X); - R1 = W [ P1 + 84 ] (X); - R2 = W [ P1 + 48 ] (X); - R3 = W [ P1 + 10 ] (X); - R4 = W [ P1 + 34 ] (X); - R5 = W [ P1 + 20 ] (X); - R6 = W [ P1 + 126 ] (X); - R7 = W [ P1 + 154 ] (X); - CHECKREG r0, 0x00000405; - CHECKREG r1, 0x00002425; - CHECKREG r2, 0xFFFF8485; - CHECKREG r3, 0x00000809; - CHECKREG r4, 0x00001122; - CHECKREG r5, 0x00001617; - CHECKREG r6, 0x00006263; - CHECKREG r7, 0x00000405; - - R0 = W [ P2 + -120 ] (X); - R1 = W [ P2 + -114 ] (X); - R2 = W [ P2 + -36 ] (X); - R3 = W [ P2 + -22 ] (X); - R4 = W [ P2 + -44 ] (X); - R5 = W [ P2 + -6 ] (X); - R6 = W [ P2 + -52 ] (X); - R7 = W [ P2 + -146 ] (X); - CHECKREG r0, 0xFFFFD5D6; - CHECKREG r1, 0xFFFFD7D8; - CHECKREG r2, 0x0000565A; - CHECKREG r3, 0xFFFFA667; - CHECKREG r4, 0xFFFF99EA; - CHECKREG r5, 0x00004C4D; - CHECKREG r6, 0xFFFF99EA; - CHECKREG r7, 0x00004C4D; - - R0 = W [ P3 + 56 ] (X); - R1 = W [ P3 + 62 ] (X); - R2 = W [ P3 + -64 ] (X); - R3 = W [ P3 + 60 ] (X); - R4 = W [ P3 + -56 ] (X); - R5 = W [ P3 + 10 ] (X); - R6 = W [ P3 + -28 ] (X); - R7 = W [ P3 + -110 ] (X); - CHECKREG r0, 0x00001617; - CHECKREG r1, 0x00001819; - CHECKREG r2, 0xFFFF8485; - CHECKREG r3, 0x00001A1B; - CHECKREG r4, 0xFFFF8283; - CHECKREG r5, 0x00005859; - CHECKREG r6, 0x00002425; - CHECKREG r7, 0x00000001; - - R0 = W [ P4 + 42 ] (X); - R1 = W [ P4 + -40 ] (X); - R2 = W [ P4 + 38 ] (X); - R3 = W [ P4 + -32 ] (X); - R4 = W [ P4 + 28 ] (X); - R5 = W [ P4 + 26 ] (X); - R6 = W [ P4 + -22 ] (X); - R7 = W [ P4 + 106 ] (X); - CHECKREG r0, 0x00004C4D; - CHECKREG r1, 0xFFFF99EA; - CHECKREG r2, 0x00004849; - CHECKREG r3, 0xFFFF99EA; - CHECKREG r4, 0x00004243; - CHECKREG r5, 0xFFFFA667; - CHECKREG r6, 0xFFFF98E8; - CHECKREG r7, 0xFFFF95E8; - - R0 = W [ P5 + -14 ] (X); - R1 = W [ P5 + 12 ] (X); - R2 = W [ P5 + -6 ] (X); - R3 = W [ P5 + 4 ] (X); - R4 = W [ P5 + 0 ] (X); - R5 = W [ P5 + -2 ] (X); - R6 = W [ P5 + 8 ] (X); - R7 = W [ P5 + -108 ] (X); - CHECKREG r0, 0x00003435; - CHECKREG r1, 0x00006465; - CHECKREG r2, 0x00004243; - CHECKREG r3, 0x00005657; - CHECKREG r4, 0x00005253; - CHECKREG r5, 0x00004647; - CHECKREG r6, 0x00006061; - CHECKREG r7, 0x00000607; - - R0 = W [ FP + 90 ] (X); - R1 = W [ FP + -14 ] (X); - R2 = W [ FP + 42 ] (X); - R3 = W [ FP + -66 ] (X); - R4 = W [ FP + 26 ] (X); - R5 = W [ FP + -34 ] (X); - R6 = W [ FP + 38 ] (X); - R7 = W [ FP + -98 ] (X); - CHECKREG r0, 0xFFFF91E8; - CHECKREG r1, 0xFFFF91E8; - CHECKREG r2, 0x00004C4D; - CHECKREG r3, 0xFFFFD7D8; - CHECKREG r4, 0xFFFFA667; - CHECKREG r5, 0xFFFF95E8; - CHECKREG r6, 0x00004849; - CHECKREG r7, 0x00004C4D; - - R0 = W [ SP + 46 ] (X); - R1 = W [ SP + -42 ] (X); - R2 = W [ SP + 48 ] (X); - R3 = W [ SP + 50 ] (X); - R4 = W [ SP + -102 ] (X); - R5 = W [ SP + 82 ] (X); - R6 = W [ SP + 62 ] (X); - R7 = W [ SP + 46 ] (X); - CHECKREG r0, 0x00000809; - CHECKREG r1, 0x00000506; - CHECKREG r2, 0x00000E0F; - CHECKREG r3, 0x00000C0D; - CHECKREG r4, 0x00000809; - CHECKREG r5, 0x00007475; - CHECKREG r6, 0x00001819; - CHECKREG r7, 0x00000809; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - -DATA_ADDR_2: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dreg.s b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dreg.s deleted file mode 100644 index 4c25099..0000000 --- a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dreg.s +++ /dev/null @@ -1,554 +0,0 @@ -//Original:testcases/core/c_ldstidxl_ld_dreg/c_ldstidxl_ld_dreg.dsp -// Spec Reference: c_ldstidxl load dreg (ld with indexed addressing) -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; - -// initial values - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0xA0; - loadsym p4, DATA_ADDR_2, 0x70; - loadsym p5, DATA_ADDR_1, 0x70; - loadsym fp, DATA_ADDR_2, 0x70; - - R0 = [ P1 + 156 ]; - R1 = [ P1 + 84 ]; - R2 = [ P1 + 48 ]; - R3 = [ P1 + 12 ]; - R4 = [ P1 + 36 ]; - R5 = [ P1 + 20 ]; - R6 = [ P1 + 128 ]; - R7 = [ P1 + 156 ]; - CHECKREG r0, 0x08090A0B; - CHECKREG r1, 0x22232425; - CHECKREG r2, 0x82838485; - CHECKREG r3, 0x0C0D0E0F; - CHECKREG r4, 0x55667788; - CHECKREG r5, 0x14151617; - CHECKREG r6, 0x66676869; - CHECKREG r7, 0x08090A0B; - - R0 = [ P2 + -120 ]; - R1 = [ P2 + -112 ]; - R2 = [ P2 + -36 ]; - R3 = [ P2 + -24 ]; - R4 = [ P2 + -44 ]; - R5 = [ P2 + -8 ]; - R6 = [ P2 + -52 ]; - R7 = [ P2 + -148 ]; - CHECKREG r0, 0xD3D4D5D6; - CHECKREG r1, 0xDBDCDDDE; - CHECKREG r2, 0xA455565A; - CHECKREG r3, 0xA667686A; - CHECKREG r4, 0x96E899EA; - CHECKREG r5, 0x4C4D4E4F; - CHECKREG r6, 0x94E899EA; - CHECKREG r7, 0x4C4D4E4F; - - R0 = [ P4 + 44 ]; - R1 = [ P4 + -40 ]; - R2 = [ P4 + 36 ]; - R3 = [ P4 + -32 ]; - R4 = [ P4 + 28 ]; - R5 = [ P4 + 24 ]; - R6 = [ P4 + -20 ]; - R7 = [ P4 + 108 ]; - CHECKREG r0, 0x50515253; - CHECKREG r1, 0x94E899EA; - CHECKREG r2, 0x48494A4B; - CHECKREG r3, 0x96E899EA; - CHECKREG r4, 0x40414243; - CHECKREG r5, 0xA667686A; - CHECKREG r6, 0x99E899EA; - CHECKREG r7, 0x96E899EA; - - R0 = [ P5 + -16 ]; - R1 = [ P5 + 12 ]; - R2 = [ P5 + -8 ]; - R3 = [ P5 + 4 ]; - R4 = [ P5 + 0 ]; - R5 = [ P5 + -4 ]; - R6 = [ P5 + 8 ]; - R7 = [ P5 + -108 ]; - CHECKREG r0, 0x34353637; - CHECKREG r1, 0x62636465; - CHECKREG r2, 0x42434445; - CHECKREG r3, 0x54555657; - CHECKREG r4, 0x50515253; - CHECKREG r5, 0x46474849; - CHECKREG r6, 0x58596061; - CHECKREG r7, 0x04050607; - - R0 = [ FP + 92 ]; - R1 = [ FP + -16 ]; - R2 = [ FP + 40 ]; - R3 = [ FP + -64 ]; - R4 = [ FP + 28 ]; - R5 = [ FP + -32 ]; - R6 = [ FP + 36 ]; - R7 = [ FP + -96 ]; - CHECKREG r0, 0x92E899EA; - CHECKREG r1, 0x91E899EA; - CHECKREG r2, 0x4C4D4E4F; - CHECKREG r3, 0xDBDCDDDE; - CHECKREG r4, 0x40414243; - CHECKREG r5, 0x96E899EA; - CHECKREG r6, 0x48494A4B; - CHECKREG r7, 0x50515253; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - -DATA_ADDR_2: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_preg.s b/sim/testsuite/sim/bfin/c_ldstidxl_ld_preg.s deleted file mode 100644 index 503c24e..0000000 --- a/sim/testsuite/sim/bfin/c_ldstidxl_ld_preg.s +++ /dev/null @@ -1,672 +0,0 @@ -//Original:testcases/core/c_ldstidxl_ld_preg/c_ldstidxl_ld_preg.dsp -// Spec Reference: c_ldstidxl load dreg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0xA0; - loadsym i1, DATA_ADDR_1, 0x70; - loadsym p4, DATA_ADDR_2, 0x70; - loadsym p5, DATA_ADDR_1, 0x70; - loadsym fp, DATA_ADDR_2, 0x70; - loadsym i3, DATA_ADDR_1, 0x70; - P3 = I1; SP = I3; - - P2 = [ P1 + 12 ]; - P3 = [ P1 + 44 ]; - P4 = [ P1 + 8 ]; - P5 = [ P1 + 156 ]; - SP = [ P1 + 16 ]; - FP = [ P1 + 120 ]; - P1 = [ P1 + 24 ]; - CHECKREG p1, 0x18191A1B; - CHECKREG p2, 0x0C0D0E0F; - CHECKREG p3, 0x74757677; - CHECKREG p4, 0x08090A0B; - CHECKREG p5, 0x08090A0B; - CHECKREG sp, 0x10111213; - CHECKREG fp, 0x58596061; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p2, DATA_ADDR_2, 0xA0; - P3 = I1; SP = I3; - - P1 = [ P2 + -128 ]; - P3 = [ P2 + -36 ]; - P4 = [ P2 + -40 ]; - P5 = [ P2 + -144 ]; - SP = [ P2 + -48 ]; - FP = [ P2 + 52 ]; - P2 = [ P2 + -132 ]; - CHECKREG p1, 0xEBECEDEE; - CHECKREG p2, 0x7C7D7E7F; - CHECKREG p3, 0xA60CAD7E; - CHECKREG p4, 0xA50CAD6E; - CHECKREG p5, 0x70717273; - CHECKREG sp, 0xA30CAD4E; - CHECKREG fp, 0x64656667; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i1, DATA_ADDR_1, 0x70; - P3 = I1; SP = I3; - P1 = [ P3 + 56 ]; - P2 = [ P3 + -104 ]; - P4 = [ P3 + 80 ]; - P5 = [ P3 + -56 ]; - SP = [ P3 + 52 ]; - FP = [ P3 + -48 ]; - P3 = [ P3 + 84 ]; - CHECKREG p1, 0x14151617; - CHECKREG p2, 0x08090A0B; - CHECKREG p3, 0x82838485; - CHECKREG p4, 0x74757677; - CHECKREG p5, 0x80818283; - CHECKREG sp, 0x10111213; - CHECKREG fp, 0x01020304; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p4, DATA_ADDR_2, 0x70; - P3 = I1; SP = I3; - P1 = [ P4 + 44 ]; - P2 = [ P4 + -40 ]; - P3 = [ P4 + -96 ]; - P5 = [ P4 + -68 ]; - SP = [ P4 + 84 ]; - FP = [ P4 + 108 ]; - P4 = [ P4 + -32 ]; - CHECKREG p1, 0x6C6D6E6F; - CHECKREG p2, 0xAB0CAD03; - CHECKREG p3, 0x70717273; - CHECKREG p4, 0xAB0CAD05; - CHECKREG p5, 0xFBFCFDFE; - CHECKREG sp, 0x03040506; - CHECKREG fp, 0x6C6D6E6F; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x70; - P3 = I1; SP = I3; - - P1 = [ P5 + 16 ]; - P2 = [ P5 + 12 ]; - P3 = [ P5 + 96 ]; - P4 = [ P5 + 0 ]; - SP = [ P5 + -44 ]; - FP = [ P5 + 28 ]; - P5 = [ P5 + -84 ]; - CHECKREG p1, 0x66676869; - CHECKREG p2, 0x62636465; - CHECKREG p3, 0x84858687; - CHECKREG p4, 0x50515253; - CHECKREG p5, 0x1C1D1E1F; - CHECKREG sp, 0x05060708; - CHECKREG fp, 0x72636467; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i3, DATA_ADDR_2, 0x70; - P3 = I1; SP = I3; - - P1 = [ SP + -72 ]; - P2 = [ SP + 16 ]; - P3 = [ SP + -80 ]; - P4 = [ SP + 92 ]; - P5 = [ SP + -28 ]; - FP = [ SP + 32 ]; - SP = [ SP + -36 ]; - CHECKREG p1, 0xF7F8F9FA; - CHECKREG p2, 0xB455565B; - CHECKREG p3, 0xEBECEDEE; - CHECKREG p4, 0x0B0CAD0E; - CHECKREG p5, 0xAB0CAD06; - CHECKREG sp, 0xAB0CAD04; - CHECKREG fp, 0x60616263; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_2, 0x70; - P3 = I1; SP = I3; - - P1 = [ FP + 40 ]; - P2 = [ FP + 44 ]; - P3 = [ FP + 96 ]; - P4 = [ FP + 52 ]; - P5 = [ FP + 104 ]; - SP = [ FP + 60 ]; - FP = [ FP + 64 ]; - CHECKREG p1, 0x68696A6B; - CHECKREG p2, 0x6C6D6E6F; - CHECKREG p3, 0x60616263; - CHECKREG p4, 0x74757677; - CHECKREG p5, 0x68696A6B; - CHECKREG sp, 0x7C7D7E7F; - CHECKREG fp, 0xEBECEDEE; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xa667686a - -DATA_ADDR_2: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_b.s b/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_b.s deleted file mode 100644 index 5ed1a11..0000000 --- a/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_b.s +++ /dev/null @@ -1,612 +0,0 @@ -//Original:testcases/core/c_ldstidxl_st_dr_b/c_ldstidxl_st_dr_b.dsp -// Spec Reference: c_ldstidxl store dreg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -I0 = P3; -I2 = SP; - -// initial values - imm32 r0, 0x105f5080; - imm32 r1, 0x204e6091; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80b3; - imm32 r4, 0x501b90c4; - imm32 r5, 0x600aa0d5; - imm32 r6, 0x7019b0e6; - imm32 r7, 0xd028c0f7; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0xc8; - loadsym i1, DATA_ADDR_1, 0x10; - loadsym p4, DATA_ADDR_2, 0xc8; - loadsym p5, DATA_ADDR_1, 0x00; - loadsym fp, DATA_ADDR_2, 0xc8; - loadsym i3, DATA_ADDR_1, 0x00; - P3 = I1; SP = I3; - - B [ P1 + 0x1101 ] = R0; - B [ P1 + 0x1013 ] = R1; - B [ P1 + 0x1015 ] = R2; - B [ P1 + 0x1007 ] = R3; - B [ P2 + -0x1019 ] = R4; - B [ P2 + -0x1011 ] = R5; - B [ P2 + -0x1013 ] = R6; - B [ P2 + -0x1015 ] = R7; - R6 = B [ P1 + 0x1101 ] (Z); - R5 = B [ P1 + 0x1013 ] (Z); - R4 = B [ P1 + 0x1015 ] (Z); - R3 = B [ P1 + 0x1007 ] (Z); - R2 = B [ P2 + -0x1019 ] (Z); - R7 = B [ P2 + -0x1011 ] (Z); - R0 = B [ P2 + -0x1013 ] (Z); - R1 = B [ P2 + -0x1015 ] (Z); - CHECKREG r0, 0x000000E6; - CHECKREG r1, 0x000000F7; - CHECKREG r2, 0x000000C4; - CHECKREG r3, 0x000000B3; - CHECKREG r4, 0x000000A2; - CHECKREG r5, 0x00000091; - CHECKREG r6, 0x00000080; - CHECKREG r7, 0x000000D5; - - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x60baa0b5; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - B [ P3 + 0x1011 ] = R0; - B [ P3 + 0x1023 ] = R1; - B [ P3 + 0x1025 ] = R2; - B [ P3 + 0x1027 ] = R3; - B [ P4 + -0x1029 ] = R4; - B [ P4 + -0x1021 ] = R5; - B [ P4 + -0x1033 ] = R6; - B [ P4 + -0x1035 ] = R7; - R3 = B [ P3 + 0x1011 ] (Z); - R4 = B [ P3 + 0x1023 ] (Z); - R0 = B [ P3 + 0x1025 ] (Z); - R1 = B [ P3 + 0x1027 ] (Z); - R2 = B [ P4 + -0x1029 ] (Z); - R5 = B [ P4 + -0x1021 ] (Z); - R6 = B [ P4 + -0x1033 ] (Z); - R7 = B [ P4 + -0x1035 ] (Z); - CHECKREG r0, 0x000000B2; - CHECKREG r1, 0x000000B3; - CHECKREG r2, 0x000000B4; - CHECKREG r3, 0x000000B0; - CHECKREG r4, 0x000000B1; - CHECKREG r5, 0x000000B5; - CHECKREG r6, 0x000000B6; - CHECKREG r7, 0x000000B7; - -// initial values - imm32 r0, 0x10cf50c0; - imm32 r1, 0x20ce60c1; - imm32 r2, 0x30c370c2; - imm32 r3, 0x40cc80c3; - imm32 r4, 0x50cb90c4; - imm32 r5, 0x60caa0c5; - imm32 r6, 0x70c9b0c6; - imm32 r7, 0xd0c8c0c7; - B [ P5 + 0x1031 ] = R0; - B [ P5 + 0x1033 ] = R1; - B [ P5 + 0x1035 ] = R2; - B [ P5 + 0x1047 ] = R3; - B [ SP + -0x1049 ] = R4; - B [ SP + -0x1041 ] = R5; - B [ SP + -0x1043 ] = R6; - B [ SP + -0x1045 ] = R7; - R6 = B [ P5 + 0x1031 ] (Z); - R5 = B [ P5 + 0x1033 ] (Z); - R4 = B [ P5 + 0x1035 ] (Z); - R3 = B [ P5 + 0x1047 ] (Z); - R2 = B [ SP + -0x1049 ] (Z); - R0 = B [ SP + -0x1041 ] (Z); - R7 = B [ SP + -0x1043 ] (Z); - R1 = B [ SP + -0x1045 ] (Z); - CHECKREG r0, 0x000000C5; - CHECKREG r1, 0x000000C7; - CHECKREG r2, 0x000000C4; - CHECKREG r3, 0x000000C3; - CHECKREG r4, 0x000000C2; - CHECKREG r5, 0x000000C1; - CHECKREG r6, 0x000000C0; - -// initial values - imm32 r0, 0x60df50d0; - imm32 r1, 0x70de60d1; - imm32 r2, 0x80dd70d2; - imm32 r3, 0x90dc80d3; - imm32 r4, 0xa0db90d4; - imm32 r5, 0xb0daa0d5; - imm32 r6, 0xc0d9b0d6; - imm32 r7, 0xd0d8c0d7; - B [ FP + 0x1051 ] = R0; - B [ FP + 0x1053 ] = R1; - B [ FP + 0x1055 ] = R2; - B [ FP + 0x1057 ] = R3; - B [ FP + 0x1059 ] = R4; - B [ FP + 0x1061 ] = R5; - B [ FP + 0x1063 ] = R6; - B [ FP + 0x1065 ] = R7; - R3 = B [ FP + 0x1051 ] (Z); - R4 = B [ FP + 0x1053 ] (Z); - R0 = B [ FP + 0x1055 ] (Z); - R1 = B [ FP + 0x1057 ] (Z); - R2 = B [ FP + 0x1059 ] (Z); - R5 = B [ FP + 0x1061 ] (Z); - R6 = B [ FP + 0x1063 ] (Z); - R7 = B [ FP + 0x1065 ] (Z); - CHECKREG r0, 0x000000D2; - CHECKREG r1, 0x000000D3; - CHECKREG r2, 0x000000D4; - CHECKREG r3, 0x000000D0; - CHECKREG r4, 0x000000D1; - CHECKREG r5, 0x000000D5; - CHECKREG r6, 0x000000D6; - CHECKREG r7, 0x000000D7; - - P3 = I0; SP = I2; - pass - -// Pre-load memory witb known data -// More data is defined than will actually be used - - .data -// Make sure there is space between the text and data sections - .space (0x2000); - -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF - -// Make sure there is space for us to scribble - .space (0x2000); diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_h.s b/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_h.s deleted file mode 100644 index 114d192..0000000 --- a/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_h.s +++ /dev/null @@ -1,609 +0,0 @@ -//Original:testcases/core/c_ldstidxl_st_dr_h/c_ldstidxl_st_dr_h.dsp -// Spec Reference: c_ldstidxl store dreg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -I0 = P3; -I2 = SP; - -// initial values - imm32 r0, 0x105f50a0; - imm32 r1, 0x204e60a1; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80a3; - imm32 r4, 0x501b90a4; - imm32 r5, 0x600aa0a5; - imm32 r6, 0x7019b0a6; - imm32 r7, 0xd028c0a7; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0xc8; - loadsym i1, DATA_ADDR_1, 0x10; - loadsym p4, DATA_ADDR_2, 0xc8; - loadsym p5, DATA_ADDR_1, 0x00; - loadsym fp, DATA_ADDR_2, 0xc8; - loadsym i3, DATA_ADDR_1, 0x00; - P3 = I1; SP = I3; - - W [ P1 + 0x1002 ] = R0; - W [ P1 + 0x1004 ] = R1; - W [ P1 + 0x1006 ] = R2; - W [ P1 + 0x1008 ] = R3; - W [ P2 + -0x1010 ] = R4; - W [ P2 + -0x1022 ] = R5; - W [ P2 + -0x1034 ] = R6; - W [ P2 + -0x1046 ] = R7; - R6 = W [ P1 + 0x1002 ] (Z); - R5 = W [ P1 + 0x1004 ] (Z); - R4 = W [ P1 + 0x1006 ] (Z); - R3 = W [ P1 + 0x1008 ] (Z); - R2 = W [ P2 + -0x1010 ] (Z); - R7 = W [ P2 + -0x1022 ] (Z); - R0 = W [ P2 + -0x1034 ] (Z); - R1 = W [ P2 + -0x1046 ] (Z); - CHECKREG r0, 0x0000B0A6; - CHECKREG r1, 0x0000C0A7; - CHECKREG r2, 0x000090A4; - CHECKREG r3, 0x000080A3; - CHECKREG r4, 0x000070A2; - CHECKREG r5, 0x000060A1; - CHECKREG r6, 0x000050A0; - CHECKREG r7, 0x0000A0A5; - - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x60baa0b5; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - W [ P3 + 0x1018 ] = R0; - W [ P3 + 0x1020 ] = R1; - W [ P3 + 0x1022 ] = R2; - W [ P3 + 0x1024 ] = R3; - W [ P4 + -0x1026 ] = R4; - W [ P4 + -0x1028 ] = R5; - W [ P4 + -0x1030 ] = R6; - W [ P4 + -0x1052 ] = R7; - R3 = W [ P3 + 0x1018 ] (Z); - R4 = W [ P3 + 0x1020 ] (Z); - R0 = W [ P3 + 0x1022 ] (Z); - R1 = W [ P3 + 0x1024 ] (Z); - R2 = W [ P4 + -0x1026 ] (Z); - R5 = W [ P4 + -0x1028 ] (Z); - R6 = W [ P4 + -0x1030 ] (Z); - R7 = W [ P4 + -0x1052 ] (Z); - CHECKREG r0, 0x000070B2; - CHECKREG r1, 0x000080B3; - CHECKREG r2, 0x000090B4; - CHECKREG r3, 0x000050B0; - CHECKREG r4, 0x000060B1; - CHECKREG r5, 0x0000A0B5; - CHECKREG r6, 0x0000B0B6; - CHECKREG r7, 0x0000C0B7; - -// initial values - imm32 r0, 0x10cf50c0; - imm32 r1, 0x20ce60c1; - imm32 r2, 0x30c370c2; - imm32 r3, 0x40cc80c3; - imm32 r4, 0x50cb90c4; - imm32 r5, 0x60caa0c5; - imm32 r6, 0x70c9b0c6; - imm32 r7, 0xd0c8c0c7; - W [ P5 + 0x1034 ] = R0; - W [ P5 + 0x1036 ] = R1; - W [ P5 + 0x1038 ] = R2; - W [ P5 + 0x1040 ] = R3; - W [ SP + -0x1042 ] = R4; - W [ SP + -0x1054 ] = R5; - W [ SP + -0x1066 ] = R6; - W [ SP + -0x1078 ] = R7; - R6 = W [ P5 + 0x1034 ] (Z); - R5 = W [ P5 + 0x1036 ] (Z); - R4 = W [ P5 + 0x1038 ] (Z); - R3 = W [ P5 + 0x1040 ] (Z); - R2 = W [ SP + -0x1042 ] (Z); - R0 = W [ SP + -0x1054 ] (Z); - R7 = W [ SP + -0x1066 ] (Z); - R1 = W [ SP + -0x1078 ] (Z); - CHECKREG r0, 0x0000A0C5; - CHECKREG r1, 0x0000C0C7; - CHECKREG r2, 0x000090C4; - CHECKREG r3, 0x000080C3; - CHECKREG r4, 0x000070C2; - CHECKREG r5, 0x000060C1; - CHECKREG r6, 0x000050C0; - -// initial values - imm32 r0, 0x60df50d0; - imm32 r1, 0x70de60d1; - imm32 r2, 0x80dd70d2; - imm32 r3, 0x90dc80d3; - imm32 r4, 0xa0db90d4; - imm32 r5, 0xb0daa0d5; - imm32 r6, 0xc0d9b0d6; - imm32 r7, 0xd0d8c0d7; - W [ FP + 0x1050 ] = R0; - W [ FP + 0x1052 ] = R1; - W [ FP + 0x1054 ] = R2; - W [ FP + 0x1056 ] = R3; - W [ FP + 0x1058 ] = R4; - W [ FP + 0x1060 ] = R5; - W [ FP + 0x1062 ] = R6; - W [ FP + 0x1064 ] = R7; - R3 = W [ FP + 0x1050 ] (Z); - R4 = W [ FP + 0x1052 ] (Z); - R0 = W [ FP + 0x1054 ] (Z); - R1 = W [ FP + 0x1056 ] (Z); - R2 = W [ FP + 0x1058 ] (Z); - R5 = W [ FP + 0x1060 ] (Z); - R6 = W [ FP + 0x1062 ] (Z); - R7 = W [ FP + 0x1064 ] (Z); - CHECKREG r0, 0x000070D2; - CHECKREG r1, 0x000080D3; - CHECKREG r2, 0x000090D4; - CHECKREG r3, 0x000050D0; - CHECKREG r4, 0x000060D1; - CHECKREG r5, 0x0000A0D5; - CHECKREG r6, 0x0000B0D6; - CHECKREG r7, 0x0000C0D7; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data - .space (0x2000); -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF - -// Make sure there is space for us to scribble - .space (0x2000); diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_st_dreg.s b/sim/testsuite/sim/bfin/c_ldstidxl_st_dreg.s deleted file mode 100644 index ac1f028..0000000 --- a/sim/testsuite/sim/bfin/c_ldstidxl_st_dreg.s +++ /dev/null @@ -1,780 +0,0 @@ -//Original:testcases/core/c_ldstidxl_st_dreg/c_ldstidxl_st_dreg.dsp -// Spec Reference: c_ldstidxl store dreg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -I0 = P3; -I2 = SP; - -// initial values - imm32 r0, 0x105f50a0; - imm32 r1, 0x204e60a1; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80a3; - imm32 r4, 0x501b90a4; - imm32 r5, 0x600aa0a5; - imm32 r6, 0x7019b0a6; - imm32 r7, 0xd028c0a7; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0xc8; - loadsym i1, DATA_ADDR_1, 0x10; - loadsym p4, DATA_ADDR_2, 0xc8; - loadsym p5, DATA_ADDR_1, 0x00; - loadsym fp, DATA_ADDR_2, 0xc8; - loadsym i3, DATA_ADDR_1, 0x00; - P3 = I1; SP = I3; - - [ P1 + 0x1004 ] = R0; - [ P1 + 0x1008 ] = R1; - [ P1 + 0x1010 ] = R2; - [ P1 + 0x1014 ] = R3; - [ P2 + -0x1020 ] = R4; - [ P2 + -0x1024 ] = R5; - [ P2 + -0x1028 ] = R6; - [ P2 + -0x1030 ] = R7; - R6 = [ P1 + 0x1004 ]; - R5 = [ P1 + 0x1008 ]; - R4 = [ P1 + 0x1010 ]; - R3 = [ P1 + 0x1014 ]; - R2 = [ P2 + -0x1020 ]; - R7 = [ P2 + -0x1024 ]; - R0 = [ P2 + -0x1028 ]; - R1 = [ P2 + -0x1030 ]; - CHECKREG r0, 0x7019B0A6; - CHECKREG r1, 0xD028C0A7; - CHECKREG r2, 0x501B90A4; - CHECKREG r3, 0x402C80A3; - CHECKREG r4, 0x300370A2; - CHECKREG r5, 0x204E60A1; - CHECKREG r6, 0x105F50A0; - CHECKREG r7, 0x600AA0A5; - - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x60baa0b5; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - [ P3 + 0x1034 ] = R0; - [ P3 + 0x1040 ] = R1; - [ P3 + 0x1044 ] = R2; - [ P3 + 0x1048 ] = R3; - [ P4 + -0x1050 ] = R4; - [ P4 + -0x1054 ] = R5; - [ P4 + -0x1060 ] = R6; - [ P4 + -0x1064 ] = R7; - R3 = [ P3 + 0x1034 ]; - R4 = [ P3 + 0x1040 ]; - R0 = [ P3 + 0x1044 ]; - R1 = [ P3 + 0x1048 ]; - R2 = [ P4 + -0x1050 ]; - R5 = [ P4 + -0x1054 ]; - R6 = [ P4 + -0x1060 ]; - R7 = [ P4 + -0x1064 ]; - CHECKREG r0, 0x30BD70B2; - CHECKREG r1, 0x40BC80B3; - CHECKREG r2, 0x55BB90B4; - CHECKREG r3, 0x10BF50B0; - CHECKREG r4, 0x20BE60B1; - CHECKREG r5, 0x60BAA0B5; - CHECKREG r6, 0x70B9B0B6; - CHECKREG r7, 0x80B8C0B7; - -// initial values - imm32 r0, 0x10cf50c0; - imm32 r1, 0x20ce60c1; - imm32 r2, 0x30c370c2; - imm32 r3, 0x40cc80c3; - imm32 r4, 0x50cb90c4; - imm32 r5, 0x60caa0c5; - imm32 r6, 0x70c9b0c6; - imm32 r7, 0xd0c8c0c7; - [ P5 + 1004 ] = R0; - [ P5 + 1008 ] = R1; - [ P5 + 1012 ] = R2; - [ P5 + 1016 ] = R3; - [ SP + -0x1020 ] = R4; - [ SP + -0x1024 ] = R5; - [ SP + -0x1028 ] = R6; - [ SP + -0x1030 ] = R7; - R6 = [ P5 + 1004 ]; - R4 = [ P5 + 1008 ]; - R5 = [ P5 + 1012 ]; - R3 = [ P5 + 1016 ]; - R2 = [ SP + -0x1020 ]; - R0 = [ SP + -0x1024 ]; - R7 = [ SP + -0x1028 ]; - R1 = [ SP + -0x1030 ]; - CHECKREG r0, 0x60CAA0C5; - CHECKREG r1, 0xD0C8C0C7; - CHECKREG r2, 0x50CB90C4; - CHECKREG r3, 0x40CC80C3; - CHECKREG r4, 0x20CE60C1; - CHECKREG r5, 0x30C370C2; - CHECKREG r6, 0x10CF50C0; - -// initial values - imm32 r0, 0x60df50d0; - imm32 r1, 0x70de60d1; - imm32 r2, 0x80dd70d2; - imm32 r3, 0x90dc80d3; - imm32 r4, 0xa0db90d4; - imm32 r5, 0xb0daa0d5; - imm32 r6, 0xc0d9b0d6; - imm32 r7, 0xd0d8c0d7; - [ FP + 0x1034 ] = R0; - [ FP + 0x1040 ] = R1; - [ FP + 0x1044 ] = R2; - [ FP + 0x1048 ] = R3; - [ FP + 0x1050 ] = R4; - [ FP + 0x1054 ] = R5; - [ FP + 0x1060 ] = R6; - [ FP + 0x1064 ] = R7; - - R3 = [ FP + 0x1034 ]; - R4 = [ FP + 0x1040 ]; - R0 = [ FP + 0x1044 ]; - R1 = [ FP + 0x1048 ]; - R2 = [ FP + 0x1050 ]; - R5 = [ FP + 0x1054 ]; - R6 = [ FP + 0x1060 ]; - R7 = [ FP + 0x1064 ]; - CHECKREG r0, 0x80DD70D2; - CHECKREG r1, 0x90DC80D3; - CHECKREG r2, 0xA0DB90D4; - CHECKREG r3, 0x60DF50D0; - CHECKREG r4, 0x70DE60D1; - CHECKREG r5, 0xB0DAA0D5; - CHECKREG r6, 0xC0D9B0D6; - CHECKREG r7, 0xD0D8C0D7; - - P3 = I0; SP = I2; - pass - - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -// Make sure there is space between the text section, and the data section - .space (0x2000); - -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_2: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xa263646a - .dd 0xa667686a - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF - -// Make sure there is space for us to scribble - .space (0x2000); diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_st_preg.s b/sim/testsuite/sim/bfin/c_ldstidxl_st_preg.s deleted file mode 100644 index 6520f82..0000000 --- a/sim/testsuite/sim/bfin/c_ldstidxl_st_preg.s +++ /dev/null @@ -1,709 +0,0 @@ -//Original:testcases/core/c_ldstidxl_st_preg/c_ldstidxl_st_preg.dsp -// Spec Reference: c_ldstidxl store preg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -I0 = P3; -I2 = SP; - -// initial values - imm32 r0, 0x105f50a0; - imm32 r1, 0x204e60a1; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80a3; - imm32 r4, 0x501b90a4; - imm32 r5, 0x600aa0a5; - imm32 r6, 0x7019b0a6; - imm32 r7, 0xd028c0a7; - - P3 = 0x0123 (X); - P4 = 0x4567 (X); - P5 = 0x79ab (X); - FP = 0x6def (X); - SP = 0x1ace (X); - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x0000; - loadsym p2, DATA_ADDR_2, 0x00c8; - P3 = I1; SP = I3; - - [ P1 + 0x1004 ] = P5; - [ P1 + 0x1008 ] = P3; - [ P1 + 0x1014 ] = P4; - [ P1 + 0x1018 ] = P3; - [ P2 + -0x1020 ] = P4; - [ P2 + -0x1024 ] = P5; - [ P2 + -0x1028 ] = SP; - [ P2 + -0x1034 ] = FP; - R6 = [ P1 + 0x1004 ]; - R5 = [ P1 + 0x1008 ]; - R4 = [ P1 + 0x1014 ]; - R3 = [ P1 + 0x1018 ]; - R2 = [ P2 + -0x1020 ]; - R7 = [ P2 + -0x1024 ]; - R0 = [ P2 + -0x1028 ]; - R1 = [ P2 + -0x1034 ]; - CHECKREG r0, 0x00001ACE; - CHECKREG r1, 0x00006DEF; - CHECKREG r2, 0x00004567; - CHECKREG r3, 0x00000123; - CHECKREG r4, 0x00004567; - CHECKREG r5, 0x00000123; - CHECKREG r6, 0x000079AB; - CHECKREG r7, 0x000079AB; - - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x60baa0b5; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - P1 = 0x3456 (X); - P2 = 0x1234 (X); - P5 = 0x5e23 (X); - FP = 0x2ac5 (X); - SP = 0x6378 (X); - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i1, DATA_ADDR_1, 0x0000; - loadsym p4, DATA_ADDR_2, 0x00c8; - P3 = I1; SP = I3; - - [ P3 + 0x1034 ] = P2; - [ P3 + 0x1040 ] = P1; - [ P3 + 0x1044 ] = P2; - [ P3 + 0x1048 ] = P1; - [ P4 + -0x1054 ] = P2; - [ P4 + -0x1058 ] = P5; - [ P4 + -0x1060 ] = SP; - [ P4 + -0x1064 ] = FP; - R3 = [ P3 + 0x1034 ]; - R4 = [ P3 + 0x1040 ]; - R0 = [ P3 + 0x1044 ]; - R1 = [ P3 + 0x1048 ]; - R2 = [ P4 + -0x1054 ]; - R5 = [ P4 + -0x1058 ]; - R6 = [ P4 + -0x1060 ]; - R7 = [ P4 + -0x1064 ]; - CHECKREG r0, 0x00001234; - CHECKREG r1, 0x00003456; - CHECKREG r2, 0x00001234; - CHECKREG r3, 0x00001234; - CHECKREG r4, 0x00003456; - CHECKREG r5, 0x00005E23; - CHECKREG r6, 0x00006378; - CHECKREG r7, 0x00002AC5; - -// initial values - imm32 r0, 0x10cf50c0; - imm32 r1, 0x20ce60c1; - imm32 r2, 0x30c370c2; - imm32 r3, 0x40cc80c3; - imm32 r4, 0x50cb90c4; - imm32 r5, 0x60caa0c5; - imm32 r6, 0x70c9b0c6; - imm32 r7, 0xd0c8c0c7; - P1 = 0x2125 (X); - P2 = 0x7345 (X); - P3 = 0x3230 (X); - P4 = 0x5789 (X); - FP = 0x5bcd (X); - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x0000; - loadsym i3, DATA_ADDR_2, 0x00c8; - P3 = I1; SP = I3; - - [ P5 + 0x1004 ] = P2; - [ P5 + 0x1008 ] = P1; - [ P5 + 0x1014 ] = P2; - [ P5 + 0x1018 ] = P3; - [ SP + -0x1020 ] = P4; - [ SP + -0x1024 ] = P2; - [ SP + -0x1028 ] = P3; - [ SP + -0x1034 ] = FP; - R6 = [ P5 + 0x1004 ]; - R5 = [ P5 + 0x1008 ]; - R4 = [ P5 + 0x1014 ]; - R3 = [ P5 + 0x1018 ]; - R2 = [ SP + -0x1020 ]; - R0 = [ SP + -0x1024 ]; - R7 = [ SP + -0x1028 ]; - R1 = [ SP + -0x1034 ]; - CHECKREG r0, 0x00007345; - CHECKREG r1, 0x00005BCD; - CHECKREG r2, 0x00005789; - CHECKREG r3, 0x00003230; - CHECKREG r4, 0x00007345; - CHECKREG r5, 0x00002125; - CHECKREG r6, 0x00007345; - CHECKREG r7, 0x00003230; - -// initial values - imm32 r0, 0x60df50d0; - imm32 r1, 0x70de60d1; - imm32 r2, 0x80dd70d2; - imm32 r3, 0x90dc80d3; - imm32 r4, 0xa0db90d4; - imm32 r5, 0xb0daa0d5; - imm32 r6, 0xc0d9b0d6; - imm32 r7, 0xd0d8c0d7; - P1 = 0x5bcd (X); - P2 = 0x1122 (X); - P3 = 0x3455 (X); - P4 = 0x6677 (X); - P5 = 0x58ab (X); - SP = 0x1ace (X); - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_1, 0x0010; - P3 = I1; SP = I3; - [ FP + 0x1034 ] = P1; - [ FP + 0x2040 ] = P1; - [ FP + 0x1144 ] = P2; - [ FP + 0x2048 ] = P3; - [ FP + 0x1050 ] = P4; - [ FP + 0x2058 ] = P5; - [ FP + 0x1160 ] = P2; - [ FP + 0x2064 ] = SP; - R3 = [ FP + 0x1034 ]; - R4 = [ FP + 0x2040 ]; - R0 = [ FP + 0x1144 ]; - R1 = [ FP + 0x2048 ]; - R2 = [ FP + 0x1050 ]; - R5 = [ FP + 0x2058 ]; - R6 = [ FP + 0x1160 ]; - R7 = [ FP + 0x2064 ]; - CHECKREG r0, 0x00001122; - CHECKREG r1, 0x00003455; - CHECKREG r2, 0x00006677; - CHECKREG r3, 0x00005BCD; - CHECKREG r4, 0x00005BCD; - CHECKREG r5, 0x000058AB; - CHECKREG r6, 0x00001122; - CHECKREG r7, 0x00001ace; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -// Make sure there is space between the text and data sections - .space (0x2000); - -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_2: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF - -// Make sure there is space for us to scribble - .space (0x2000); diff --git a/sim/testsuite/sim/bfin/c_ldstii_ld_dr_h.s b/sim/testsuite/sim/bfin/c_ldstii_ld_dr_h.s deleted file mode 100644 index a2daecd..0000000 --- a/sim/testsuite/sim/bfin/c_ldstii_ld_dr_h.s +++ /dev/null @@ -1,541 +0,0 @@ -//Original:testcases/core/c_ldstii_ld_dr_h/c_ldstii_ld_dr_h.dsp -// Spec Reference: c_ldstii load dreg h -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0x04; - loadsym i1, DATA_ADDR_3, 0x04; - loadsym p4, DATA_ADDR_1, 0x00; - loadsym p5, DATA_ADDR_2, 0x00; - loadsym fp, DATA_ADDR_3, 0x00; - loadsym i3, DATA_ADDR_4, 0x00; - P3 = I1; SP = I3; - - R0 = W [ P1 + 0 ] (Z); - R1 = W [ P1 + 4 ] (Z); - R2 = W [ P1 + 8 ] (Z); - R3 = W [ P1 + 12 ] (Z); - R4 = W [ P1 + 16 ] (Z); - R5 = W [ P1 + 20 ] (Z); - R6 = W [ P1 + 24 ] (Z); - CHECKREG r0, 0x00000203; - CHECKREG r1, 0x00000607; - CHECKREG r2, 0x00000A0B; - CHECKREG r3, 0x00000E0F; - CHECKREG r4, 0x00001213; - CHECKREG r5, 0x00001617; - CHECKREG r6, 0x00001A1B; - - R0 = W [ P2 + 28 ] (Z); - R1 = W [ P2 + 32 ] (Z); - R2 = W [ P2 + 36 ] (Z); - R3 = W [ P2 + 40 ] (Z); - R4 = W [ P2 + 44 ] (Z); - R5 = W [ P2 + 48 ] (Z); - R6 = W [ P2 + 52 ] (Z); - CHECKREG r0, 0x00009394; - CHECKREG r1, 0x00009798; - CHECKREG r2, 0x0000A2A3; - CHECKREG r3, 0x0000A7A8; - CHECKREG r4, 0x0000B1B2; - CHECKREG r5, 0x0000B5B6; - CHECKREG r6, 0x0000B9C0; - - R0 = W [ P3 + 56 ] (Z); - R1 = W [ P3 + 60 ] (Z); - R2 = W [ P3 + 64 ] (Z); - R3 = W [ P3 + 60 ] (Z); - R4 = W [ P3 + 56 ] (Z); - R5 = W [ P3 + 52 ] (Z); - R6 = W [ P3 + 48 ] (Z); - CHECKREG r0, 0x000099EA; - CHECKREG r1, 0x000099EA; - CHECKREG r2, 0x000099EA; - CHECKREG r3, 0x000099EA; - CHECKREG r4, 0x000099EA; - CHECKREG r5, 0x0000E5E6; - CHECKREG r6, 0x0000E1E2; - - R0 = W [ P4 + 44 ] (Z); - R1 = W [ P4 + 40 ] (Z); - R2 = W [ P4 + 36 ] (Z); - R3 = W [ P4 + 32 ] (Z); - R4 = W [ P4 + 28 ] (Z); - R5 = W [ P4 + 24 ] (Z); - R6 = W [ P4 + 20 ] (Z); - CHECKREG r0, 0x00007677; - CHECKREG r1, 0x00007273; - CHECKREG r2, 0x00007788; - CHECKREG r3, 0x00003344; - CHECKREG r4, 0x00001E1F; - CHECKREG r5, 0x00001A1B; - CHECKREG r6, 0x00001617; - - R0 = W [ P5 + 16 ] (Z); - R1 = W [ P5 + 12 ] (Z); - R2 = W [ P5 + 8 ] (Z); - R3 = W [ P5 + 4 ] (Z); - R4 = W [ P5 + 0 ] (Z); - R5 = W [ P5 + 4 ] (Z); - R6 = W [ P5 + 8 ] (Z); - CHECKREG r0, 0x00003233; - CHECKREG r1, 0x00002E2F; - CHECKREG r2, 0x00002A2B; - CHECKREG r3, 0x00002627; - CHECKREG r4, 0x00002223; - CHECKREG r5, 0x00002627; - CHECKREG r6, 0x00002A2B; - - R0 = W [ FP + 12 ] (Z); - R1 = W [ FP + 16 ] (Z); - R2 = W [ FP + 20 ] (Z); - R3 = W [ FP + 24 ] (Z); - R4 = W [ FP + 28 ] (Z); - R5 = W [ FP + 32 ] (Z); - R6 = W [ FP + 36 ] (Z); - CHECKREG r0, 0x00004E4F; - CHECKREG r1, 0x00005253; - CHECKREG r2, 0x00005657; - CHECKREG r3, 0x00005A5B; - CHECKREG r4, 0x0000C7C8; - CHECKREG r5, 0x0000CBCD; - CHECKREG r6, 0x0000D1D2; - - R0 = W [ SP + 40 ] (Z); - R1 = W [ SP + 44 ] (Z); - R2 = W [ SP + 48 ] (Z); - R3 = W [ SP + 52 ] (Z); - R4 = W [ SP + 56 ] (Z); - R5 = W [ SP + 60 ] (Z); - R6 = W [ SP + 64 ] (Z); - CHECKREG r0, 0x0000F9FA; - CHECKREG r1, 0x0000FDFE; - CHECKREG r2, 0x00000102; - CHECKREG r3, 0x00000506; - CHECKREG r4, 0x0000090A; - CHECKREG r5, 0x0000AD0E; - CHECKREG r6, 0x0000AD01; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstii_ld_dr_xh.s b/sim/testsuite/sim/bfin/c_ldstii_ld_dr_xh.s deleted file mode 100644 index 07b097f..0000000 --- a/sim/testsuite/sim/bfin/c_ldstii_ld_dr_xh.s +++ /dev/null @@ -1,541 +0,0 @@ -//Original:testcases/core/c_ldstii_ld_dr_xh/c_ldstii_ld_dr_xh.dsp -// Spec Reference: c_ldstii load dreg xh -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0x04; - loadsym i1, DATA_ADDR_3, 0x04; - loadsym p4, DATA_ADDR_1, 0x00; - loadsym p5, DATA_ADDR_2, 0x00; - loadsym fp, DATA_ADDR_3, 0x00; - loadsym i3, DATA_ADDR_4, 0x00; - P3 = I1; SP = I3; - - R0 = W [ P1 + 0 ] (X); - R1 = W [ P1 + 4 ] (X); - R2 = W [ P1 + 8 ] (X); - R3 = W [ P1 + 12 ] (X); - R4 = W [ P1 + 16 ] (X); - R5 = W [ P1 + 20 ] (X); - R6 = W [ P1 + 24 ] (X); - CHECKREG r0, 0x00000203; - CHECKREG r1, 0x00000607; - CHECKREG r2, 0x00000A0B; - CHECKREG r3, 0x00000E0F; - CHECKREG r4, 0x00001213; - CHECKREG r5, 0x00001617; - CHECKREG r6, 0x00001A1B; - - R0 = W [ P2 + 28 ] (X); - R1 = W [ P2 + 32 ] (X); - R2 = W [ P2 + 36 ] (X); - R3 = W [ P2 + 40 ] (X); - R4 = W [ P2 + 44 ] (X); - R5 = W [ P2 + 48 ] (X); - R6 = W [ P2 + 52 ] (X); - CHECKREG r0, 0xFFFF9394; - CHECKREG r1, 0xFFFF9798; - CHECKREG r2, 0xFFFFA2A3; - CHECKREG r3, 0xFFFFA7A8; - CHECKREG r4, 0xFFFFB1B2; - CHECKREG r5, 0xFFFFB5B6; - CHECKREG r6, 0xFFFFB9C0; - - R0 = W [ P3 + 56 ] (X); - R1 = W [ P3 + 60 ] (X); - R2 = W [ P3 + 64 ] (X); - R3 = W [ P3 + 60 ] (X); - R4 = W [ P3 + 56 ] (X); - R5 = W [ P3 + 52 ] (X); - R6 = W [ P3 + 48 ] (X); - CHECKREG r0, 0xFFFF99EA; - CHECKREG r1, 0xFFFF99EA; - CHECKREG r2, 0xFFFF99EA; - CHECKREG r3, 0xFFFF99EA; - CHECKREG r4, 0xFFFF99EA; - CHECKREG r5, 0xFFFFE5E6; - CHECKREG r6, 0xFFFFE1E2; - - R0 = W [ P4 + 44 ] (X); - R1 = W [ P4 + 40 ] (X); - R2 = W [ P4 + 36 ] (X); - R3 = W [ P4 + 32 ] (X); - R4 = W [ P4 + 28 ] (X); - R5 = W [ P4 + 24 ] (X); - R6 = W [ P4 + 20 ] (X); - CHECKREG r0, 0x00007677; - CHECKREG r1, 0x00007273; - CHECKREG r2, 0x00007788; - CHECKREG r3, 0x00003344; - CHECKREG r4, 0x00001E1F; - CHECKREG r5, 0x00001A1B; - CHECKREG r6, 0x00001617; - - R0 = W [ P5 + 16 ] (X); - R1 = W [ P5 + 12 ] (X); - R2 = W [ P5 + 8 ] (X); - R3 = W [ P5 + 4 ] (X); - R4 = W [ P5 + 0 ] (X); - R5 = W [ P5 + 4 ] (X); - R6 = W [ P5 + 8 ] (X); - CHECKREG r0, 0x00003233; - CHECKREG r1, 0x00002E2F; - CHECKREG r2, 0x00002A2B; - CHECKREG r3, 0x00002627; - CHECKREG r4, 0x00002223; - CHECKREG r5, 0x00002627; - CHECKREG r6, 0x00002A2B; - - R0 = W [ FP + 12 ] (X); - R1 = W [ FP + 16 ] (X); - R2 = W [ FP + 20 ] (X); - R3 = W [ FP + 24 ] (X); - R4 = W [ FP + 28 ] (X); - R5 = W [ FP + 32 ] (X); - R6 = W [ FP + 36 ] (X); - CHECKREG r0, 0x00004E4F; - CHECKREG r1, 0x00005253; - CHECKREG r2, 0x00005657; - CHECKREG r3, 0x00005A5B; - CHECKREG r4, 0xFFFFC7C8; - CHECKREG r5, 0xFFFFCBCD; - CHECKREG r6, 0xFFFFD1D2; - - R0 = W [ SP + 40 ] (X); - R1 = W [ SP + 44 ] (X); - R2 = W [ SP + 48 ] (X); - R3 = W [ SP + 52 ] (X); - R4 = W [ SP + 56 ] (X); - R5 = W [ SP + 60 ] (X); - R6 = W [ SP + 64 ] (X); - CHECKREG r0, 0xFFFFF9FA; - CHECKREG r1, 0xFFFFFDFE; - CHECKREG r2, 0x00000102; - CHECKREG r3, 0x00000506; - CHECKREG r4, 0x0000090A; - CHECKREG r5, 0xFFFFAD0E; - CHECKREG r6, 0xFFFFAD01; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstii_ld_dreg.s b/sim/testsuite/sim/bfin/c_ldstii_ld_dreg.s deleted file mode 100644 index 00757f3..0000000 --- a/sim/testsuite/sim/bfin/c_ldstii_ld_dreg.s +++ /dev/null @@ -1,540 +0,0 @@ -//Original:testcases/core/c_ldstii_ld_dreg/c_ldstii_ld_dreg.dsp -// Spec Reference: c_ldstii load dreg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0x04; - loadsym i1, DATA_ADDR_3, 0x04; - loadsym p4, DATA_ADDR_1, 0x00; - loadsym p5, DATA_ADDR_2, 0x00; - loadsym fp, DATA_ADDR_3, 0x00; - loadsym i3, DATA_ADDR_4, 0x00; - P3 = I1; SP = I3; - - R0 = [ P1 + 0 ]; - R1 = [ P1 + 4 ]; - R2 = [ P1 + 8 ]; - R3 = [ P1 + 12 ]; - R4 = [ P1 + 16 ]; - R5 = [ P1 + 20 ]; - R6 = [ P1 + 24 ]; - CHECKREG r0, 0x00010203; - CHECKREG r1, 0x04050607; - CHECKREG r2, 0x08090A0B; - CHECKREG r3, 0x0C0D0E0F; - CHECKREG r4, 0x10111213; - CHECKREG r5, 0x14151617; - CHECKREG r6, 0x18191A1B; - - R0 = [ P2 + 28 ]; - R1 = [ P2 + 32 ]; - R2 = [ P2 + 36 ]; - R3 = [ P2 + 40 ]; - R4 = [ P2 + 44 ]; - R5 = [ P2 + 48 ]; - R6 = [ P2 + 52 ]; - CHECKREG r0, 0x91929394; - CHECKREG r1, 0x95969798; - CHECKREG r2, 0x99A1A2A3; - CHECKREG r3, 0xA5A6A7A8; - CHECKREG r4, 0xA9B0B1B2; - CHECKREG r5, 0xB3B4B5B6; - CHECKREG r6, 0xB7B8B9C0; - - R0 = [ P3 + 56 ]; - R1 = [ P3 + 60 ]; - R2 = [ P3 + 64 ]; - R3 = [ P3 + 60 ]; - R4 = [ P3 + 56 ]; - R5 = [ P3 + 52 ]; - R6 = [ P3 + 48 ]; - CHECKREG r0, 0x91E899EA; - CHECKREG r1, 0x92E899EA; - CHECKREG r2, 0x93E899EA; - CHECKREG r3, 0x92E899EA; - CHECKREG r4, 0x91E899EA; - CHECKREG r5, 0xE3E4E5E6; - CHECKREG r6, 0xDFE0E1E2; - - R0 = [ P4 + 44 ]; - R1 = [ P4 + 40 ]; - R2 = [ P4 + 36 ]; - R3 = [ P4 + 32 ]; - R4 = [ P4 + 28 ]; - R5 = [ P4 + 24 ]; - R6 = [ P4 + 20 ]; - CHECKREG r0, 0x74757677; - CHECKREG r1, 0x99717273; - CHECKREG r2, 0x55667788; - CHECKREG r3, 0x11223344; - CHECKREG r4, 0x1C1D1E1F; - CHECKREG r5, 0x18191A1B; - CHECKREG r6, 0x14151617; - - R0 = [ P5 + 16 ]; - R1 = [ P5 + 12 ]; - R2 = [ P5 + 8 ]; - R3 = [ P5 + 4 ]; - R4 = [ P5 + 0 ]; - R5 = [ P5 + 4 ]; - R6 = [ P5 + 8 ]; - CHECKREG r0, 0x30313233; - CHECKREG r1, 0x2C2D2E2F; - CHECKREG r2, 0x28292A2B; - CHECKREG r3, 0x24252627; - CHECKREG r4, 0x20212223; - CHECKREG r5, 0x24252627; - CHECKREG r6, 0x28292A2B; - - R0 = [ FP + 12 ]; - R1 = [ FP + 16 ]; - R2 = [ FP + 20 ]; - R3 = [ FP + 24 ]; - R4 = [ FP + 28 ]; - R5 = [ FP + 32 ]; - R6 = [ FP + 36 ]; - CHECKREG r0, 0x4C4D4E4F; - CHECKREG r1, 0x50515253; - CHECKREG r2, 0x54555657; - CHECKREG r3, 0x58595A5B; - CHECKREG r4, 0xC5C6C7C8; - CHECKREG r5, 0xC9CACBCD; - CHECKREG r6, 0xCFD0D1D2; - - R0 = [ SP + 40 ]; - R1 = [ SP + 44 ]; - R2 = [ SP + 48 ]; - R3 = [ SP + 52 ]; - R4 = [ SP + 56 ]; - R5 = [ SP + 60 ]; - R6 = [ SP + 64 ]; - CHECKREG r0, 0xF7F8F9FA; - CHECKREG r1, 0xFBFCFDFE; - CHECKREG r2, 0xFF000102; - CHECKREG r3, 0x03040506; - CHECKREG r4, 0x0708090A; - CHECKREG r5, 0x0B0CAD0E; - CHECKREG r6, 0xAB0CAD01; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstii_ld_preg.s b/sim/testsuite/sim/bfin/c_ldstii_ld_preg.s deleted file mode 100644 index 961b7d3..0000000 --- a/sim/testsuite/sim/bfin/c_ldstii_ld_preg.s +++ /dev/null @@ -1,564 +0,0 @@ -//Original:testcases/core/c_ldstii_ld_preg/c_ldstii_ld_preg.dsp -// Spec Reference: c_ldstii load preg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0x04; - loadsym i1, DATA_ADDR_3, 0x04; - loadsym p4, DATA_ADDR_1, 0x00; - loadsym p5, DATA_ADDR_2, 0x00; - loadsym fp, DATA_ADDR_3, 0x00; - loadsym i3, DATA_ADDR_4, 0x00; - P3 = I1; SP = I3; - - P2 = [ P1 + 0 ]; - P3 = [ P1 + 4 ]; - P4 = [ P1 + 8 ]; - P5 = [ P1 + 12 ]; - SP = [ P1 + 16 ]; - FP = [ P1 + 20 ]; - P1 = [ P1 + 24 ]; - CHECKREG p1, 0x18191A1B; - CHECKREG p2, 0x00010203; - CHECKREG p3, 0x04050607; - CHECKREG p4, 0x08090A0B; - CHECKREG p5, 0x0C0D0E0F; - CHECKREG sp, 0x10111213; - CHECKREG fp, 0x14151617; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p2, DATA_ADDR_2, 0x04; - P3 = I1; SP = I3; - - P1 = [ P2 + 28 ]; - P3 = [ P2 + 36 ]; - P4 = [ P2 + 40 ]; - P5 = [ P2 + 44 ]; - SP = [ P2 + 48 ]; - FP = [ P2 + 52 ]; - P2 = [ P2 + 32 ]; - CHECKREG p1, 0x91929394; - CHECKREG p2, 0x95969798; - CHECKREG p3, 0x99A1A2A3; - CHECKREG p4, 0xA5A6A7A8; - CHECKREG p5, 0xA9B0B1B2; - CHECKREG sp, 0xB3B4B5B6; - CHECKREG fp, 0xB7B8B9C0; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i1, DATA_ADDR_3, 0x00; - P3 = I1; SP = I3; - - P1 = [ P3 + 56 ]; - P2 = [ P3 + 60 ]; - P4 = [ P3 + 60 ]; - P5 = [ P3 + 56 ]; - SP = [ P3 + 52 ]; - FP = [ P3 + 48 ]; - P3 = [ P3 + 64 ]; - CHECKREG p1, 0xE3E4E5E6; - CHECKREG p2, 0x91E899EA; - CHECKREG p3, 0x92E899EA; - CHECKREG p4, 0x91E899EA; - CHECKREG p5, 0xE3E4E5E6; - CHECKREG sp, 0xDFE0E1E2; - CHECKREG fp, 0xDBDCDDDE; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p4, DATA_ADDR_4, 0x00; - P3 = I1; SP = I3; - - P1 = [ P4 + 44 ]; - P2 = [ P4 + 40 ]; - P3 = [ P4 + 36 ]; - P5 = [ P4 + 28 ]; - SP = [ P4 + 24 ]; - FP = [ P4 + 20 ]; - P4 = [ P4 + 32 ]; - CHECKREG p1, 0xFBFCFDFE; - CHECKREG p2, 0xF7F8F9FA; - CHECKREG p3, 0xF3F4F5F6; - CHECKREG p4, 0xEBECEDEE; - CHECKREG p5, 0x7C7D7E7F; - CHECKREG sp, 0x78797A7B; - CHECKREG fp, 0x74757677; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x00; - P3 = I1; SP = I3; - - P1 = [ P5 + 16 ]; - P2 = [ P5 + 12 ]; - P3 = [ P5 + 8 ]; - P4 = [ P5 + 0 ]; - SP = [ P5 + 4 ]; - FP = [ P5 + 8 ]; - P5 = [ P5 + 4 ]; - CHECKREG p1, 0x10111213; - CHECKREG p2, 0x0C0D0E0F; - CHECKREG p3, 0x08090A0B; - CHECKREG p4, 0x00010203; - CHECKREG p5, 0x04050607; - CHECKREG sp, 0x04050607; - CHECKREG fp, 0x08090A0B; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i3, DATA_ADDR_2, 0x00; - P3 = I1; SP = I3; - - P1 = [ SP + 12 ]; - P2 = [ SP + 16 ]; - P3 = [ SP + 20 ]; - P4 = [ SP + 24 ]; - P5 = [ SP + 28 ]; - FP = [ SP + 32 ]; - SP = [ SP + 36 ]; - CHECKREG p1, 0x2C2D2E2F; - CHECKREG p2, 0x30313233; - CHECKREG p3, 0x34353637; - CHECKREG p4, 0x38393A3B; - CHECKREG p5, 0x3C3D3E3F; - CHECKREG sp, 0x95969798; - CHECKREG fp, 0x91929394; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_3, 0x00; - P3 = I1; SP = I3; - - P1 = [ FP + 40 ]; - P2 = [ FP + 44 ]; - P3 = [ FP + 48 ]; - P4 = [ FP + 52 ]; - P5 = [ FP + 56 ]; - SP = [ FP + 60 ]; - FP = [ FP + 64 ]; - CHECKREG p1, 0xD3D4D5D6; - CHECKREG p2, 0xD7D8D9DA; - CHECKREG p3, 0xDBDCDDDE; - CHECKREG p4, 0xDFE0E1E2; - CHECKREG p5, 0xE3E4E5E6; - CHECKREG sp, 0x91E899EA; - CHECKREG fp, 0x92E899EA; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstii_st_dr_h.s b/sim/testsuite/sim/bfin/c_ldstii_st_dr_h.s deleted file mode 100644 index 2f85534..0000000 --- a/sim/testsuite/sim/bfin/c_ldstii_st_dr_h.s +++ /dev/null @@ -1,605 +0,0 @@ -//Original:/testcases/core/c_ldstii_st_dr_h/c_ldstii_st_dr_h.dsp -// Spec Reference: c_ldstii store dreg -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x105f50a0; - imm32 r1, 0x204e60a1; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80a3; - imm32 r4, 0x501b90a4; - imm32 r5, 0x600aa0a5; - imm32 r6, 0x7019b0a6; - imm32 r7, 0xd028c0a7; - - loadsym p1, DATA_ADDR_1; - loadsym p2, DATA_ADDR_2; -.ifndef BFIN_HOST - loadsym p3, DATA_ADDR_3; -.endif - loadsym p4, DATA_ADDR_4; - loadsym p5, DATA_ADDR_1; - loadsym fp, DATA_ADDR_2; -.ifndef BFIN_HOST - loadsym sp, DATA_ADDR_3; -.endif - - W [ P1 + 2 ] = R0; - W [ P1 + 4 ] = R1; - W [ P1 + 6 ] = R2; - W [ P1 + 8 ] = R3; - W [ P2 + 10 ] = R4; - W [ P2 + 12 ] = R5; - W [ P2 + 14 ] = R6; - W [ P2 + 16 ] = R7; - R6 = W [ P1 + 2 ] (Z); - R5 = W [ P1 + 4 ] (Z); - R4 = W [ P1 + 6 ] (Z); - R3 = W [ P1 + 8 ] (Z); - R2 = W [ P2 + 10 ] (Z); - R7 = W [ P2 + 12 ] (Z); - R0 = W [ P2 + 14 ] (Z); - R1 = W [ P2 + 16 ] (Z); - CHECKREG r0, 0x0000B0A6; - CHECKREG r1, 0x0000C0A7; - CHECKREG r2, 0x000090A4; - CHECKREG r3, 0x000080A3; - CHECKREG r4, 0x000070A2; - CHECKREG r5, 0x000060A1; - CHECKREG r6, 0x000050A0; - CHECKREG r7, 0x0000A0A5; - -.ifndef BFIN_HOST - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x60baa0b5; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - W [ P3 + 18 ] = R0; - W [ P3 + 20 ] = R1; - W [ P3 + 22 ] = R2; - W [ P3 + 24 ] = R3; - W [ P4 + 26 ] = R4; - W [ P4 + 28 ] = R5; - W [ P4 + 30 ] = R6; - W [ P4 + 32 ] = R7; - R3 = W [ P3 + 18 ] (Z); - R4 = W [ P3 + 20 ] (Z); - R0 = W [ P3 + 22 ] (Z); - R1 = W [ P3 + 24 ] (Z); - R2 = W [ P4 + 26 ] (Z); - R5 = W [ P4 + 28 ] (Z); - R6 = W [ P4 + 30 ] (Z); - R7 = W [ P4 + 32 ] (Z); - CHECKREG r0, 0x000070B2; - CHECKREG r1, 0x000080B3; - CHECKREG r2, 0x000090B4; - CHECKREG r3, 0x000050B0; - CHECKREG r4, 0x000060B1; - CHECKREG r5, 0x0000A0B5; - CHECKREG r6, 0x0000B0B6; - CHECKREG r7, 0x0000C0B7; -.endif - -// initial values - imm32 r0, 0x10cf50c0; - imm32 r1, 0x20ce60c1; - imm32 r2, 0x30c370c2; - imm32 r3, 0x40cc80c3; - imm32 r4, 0x50cb90c4; - imm32 r5, 0x60caa0c5; - imm32 r6, 0x70c9b0c6; - imm32 r7, 0xd0c8c0c7; - W [ P5 + 34 ] = R0; - W [ P5 + 36 ] = R1; - W [ P5 + 38 ] = R2; - W [ P5 + 40 ] = R3; -.ifndef BFIN_HOST - W [ SP + 42 ] = R4; - W [ SP + 44 ] = R5; - W [ SP + 46 ] = R6; - W [ SP + 48 ] = R7; -.endif - R6 = W [ P5 + 34 ] (Z); - R5 = W [ P5 + 36 ] (Z); - R4 = W [ P5 + 38 ] (Z); - R3 = W [ P5 + 40 ] (Z); -.ifndef BFIN_HOST - R2 = W [ SP + 42 ] (Z); - R0 = W [ SP + 44 ] (Z); - R7 = W [ SP + 46 ] (Z); - R1 = W [ SP + 48 ] (Z); - - CHECKREG r0, 0x0000A0C5; - CHECKREG r1, 0x0000C0C7; - CHECKREG r2, 0x000090C4; -.endif - CHECKREG r3, 0x000080C3; - CHECKREG r4, 0x000070C2; - CHECKREG r5, 0x000060C1; - CHECKREG r6, 0x000050C0; - -// initial values - imm32 r0, 0x60df50d0; - imm32 r1, 0x70de60d1; - imm32 r2, 0x80dd70d2; - imm32 r3, 0x90dc80d3; - imm32 r4, 0xa0db90d4; - imm32 r5, 0xb0daa0d5; - imm32 r6, 0xc0d9b0d6; - imm32 r7, 0xd0d8c0d7; - W [ FP + 50 ] = R0; - W [ FP + 52 ] = R1; - W [ FP + 54 ] = R2; - W [ FP + 56 ] = R3; - W [ FP + 58 ] = R4; - W [ FP + 60 ] = R5; - W [ FP + 62 ] = R6; - W [ FP + 64 ] = R7; - R3 = W [ FP + 50 ] (Z); - R4 = W [ FP + 52 ] (Z); - R0 = W [ FP + 54 ] (Z); - R1 = W [ FP + 56 ] (Z); - R2 = W [ FP + 58 ] (Z); - R5 = W [ FP + 60 ] (Z); - R6 = W [ FP + 62 ] (Z); - R7 = W [ FP + 64 ] (Z); - CHECKREG r0, 0x000070D2; - CHECKREG r1, 0x000080D3; - CHECKREG r2, 0x000090D4; - CHECKREG r3, 0x000050D0; - CHECKREG r4, 0x000060D1; - CHECKREG r5, 0x0000A0D5; - CHECKREG r6, 0x0000B0D6; - CHECKREG r7, 0x0000C0D7; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstii_st_dreg.s b/sim/testsuite/sim/bfin/c_ldstii_st_dreg.s deleted file mode 100644 index af04cd5..0000000 --- a/sim/testsuite/sim/bfin/c_ldstii_st_dreg.s +++ /dev/null @@ -1,640 +0,0 @@ -//Original:/testcases/core/c_ldstii_st_dreg/c_ldstii_st_dreg.dsp -// Spec Reference: c_ldstii store dreg -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x105f50a0; - imm32 r1, 0x204e60a1; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80a3; - imm32 r4, 0x501b90a4; - imm32 r5, 0x600aa0a5; - imm32 r6, 0x7019b0a6; - imm32 r7, 0xd028c0a7; - - loadsym p1, DATA_ADDR_1; - loadsym p2, DATA_ADDR_2; -.ifndef BFIN_HOST - loadsym p3, DATA_ADDR_3; -.endif - loadsym p4, DATA_ADDR_4; - loadsym p5, DATA_ADDR_1; - loadsym fp, DATA_ADDR_2; -.ifndef BFIN_HOST - loadsym sp, DATA_ADDR_3; -.endif - - [ P1 + 4 ] = R0; - [ P1 + 8 ] = R1; - [ P1 + 12 ] = R2; - [ P1 + 16 ] = R3; - [ P2 + 20 ] = R4; - [ P2 + 24 ] = R5; - [ P2 + 28 ] = R6; - [ P2 + 32 ] = R7; - R6 = [ P1 + 4 ]; - R5 = [ P1 + 8 ]; - R4 = [ P1 + 12 ]; - R3 = [ P1 + 16 ]; - R2 = [ P2 + 20 ]; - R7 = [ P2 + 24 ]; - R0 = [ P2 + 28 ]; - R1 = [ P2 + 32 ]; - CHECKREG r0, 0x7019B0A6; - CHECKREG r1, 0xD028C0A7; - CHECKREG r2, 0x501B90A4; - CHECKREG r3, 0x402C80A3; - CHECKREG r4, 0x300370A2; - CHECKREG r5, 0x204E60A1; - CHECKREG r6, 0x105F50A0; - CHECKREG r7, 0x600AA0A5; - -.ifndef BFIN_HOST - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x60baa0b5; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - [ P3 + 36 ] = R0; - [ P3 + 40 ] = R1; - [ P3 + 44 ] = R2; - [ P3 + 48 ] = R3; - [ P4 + 52 ] = R4; - [ P4 + 56 ] = R5; - [ P4 + 60 ] = R6; - [ P4 + 64 ] = R7; - R3 = [ P3 + 36 ]; - R4 = [ P3 + 40 ]; - R0 = [ P3 + 44 ]; - R1 = [ P3 + 48 ]; - R2 = [ P4 + 52 ]; - R5 = [ P4 + 56 ]; - R6 = [ P4 + 60 ]; - R7 = [ P4 + 64 ]; - CHECKREG r0, 0x30BD70B2; - CHECKREG r1, 0x40BC80B3; - CHECKREG r2, 0x55BB90B4; - CHECKREG r3, 0x10BF50B0; - CHECKREG r4, 0x20BE60B1; - CHECKREG r5, 0x60BAA0B5; - CHECKREG r6, 0x70B9B0B6; - CHECKREG r7, 0x80B8C0B7; -.endif - -// initial values - imm32 r0, 0x10cf50c0; - imm32 r1, 0x20ce60c1; - imm32 r2, 0x30c370c2; - imm32 r3, 0x40cc80c3; - imm32 r4, 0x50cb90c4; - imm32 r5, 0x60caa0c5; - imm32 r6, 0x70c9b0c6; - imm32 r7, 0xd0c8c0c7; - [ P5 + 4 ] = R0; - [ P5 + 8 ] = R1; - [ P5 + 12 ] = R2; - [ P5 + 16 ] = R3; -.ifndef BFIN_HOST - [ SP + 20 ] = R4; - [ SP + 24 ] = R5; - [ SP + 28 ] = R6; - [ SP + 32 ] = R7; -.endif - R6 = [ P5 + 4 ]; - R5 = [ P5 + 8 ]; - R4 = [ P5 + 12 ]; - R3 = [ P5 + 16 ]; -.ifndef BFIN_HOST - R2 = [ SP + 20 ]; - R0 = [ SP + 24 ]; - R7 = [ SP + 28 ]; - R1 = [ SP + 32 ]; - CHECKREG r0, 0x60CAA0C5; - CHECKREG r1, 0xD0C8C0C7; - CHECKREG r2, 0x50CB90C4; -.endif - CHECKREG r3, 0x40CC80C3; - CHECKREG r4, 0x30C370C2; - CHECKREG r5, 0x20CE60C1; - CHECKREG r6, 0x10CF50C0; - -// initial values - imm32 r0, 0x60df50d0; - imm32 r1, 0x70de60d1; - imm32 r2, 0x80dd70d2; - imm32 r3, 0x90dc80d3; - imm32 r4, 0xa0db90d4; - imm32 r5, 0xb0daa0d5; - imm32 r6, 0xc0d9b0d6; - imm32 r7, 0xd0d8c0d7; - [ FP + 36 ] = R0; - [ FP + 40 ] = R1; - [ FP + 44 ] = R2; - [ FP + 48 ] = R3; - [ FP + 52 ] = R4; - [ FP + 56 ] = R5; - [ FP + 60 ] = R6; - [ FP + 64 ] = R7; - R3 = [ FP + 36 ]; - R4 = [ FP + 40 ]; - R0 = [ FP + 44 ]; - R1 = [ FP + 48 ]; - R2 = [ FP + 52 ]; - R5 = [ FP + 56 ]; - R6 = [ FP + 60 ]; - R7 = [ FP + 64 ]; - CHECKREG r0, 0x80DD70D2; - CHECKREG r1, 0x90DC80D3; - CHECKREG r2, 0xA0DB90D4; - CHECKREG r3, 0x60DF50D0; - CHECKREG r4, 0x70DE60D1; - CHECKREG r5, 0xB0DAA0D5; - CHECKREG r6, 0xC0D9B0D6; - CHECKREG r7, 0xD0D8C0D7; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstii_st_preg.s b/sim/testsuite/sim/bfin/c_ldstii_st_preg.s deleted file mode 100644 index 126bd4d..0000000 --- a/sim/testsuite/sim/bfin/c_ldstii_st_preg.s +++ /dev/null @@ -1,603 +0,0 @@ -//Original:/testcases/core/c_ldstii_st_preg/c_ldstii_st_preg.dsp -// Spec Reference: c_ldstii store preg -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x105f50a0; - imm32 r1, 0x204e60a1; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80a3; - imm32 r4, 0x501b90a4; - imm32 r5, 0x600aa0a5; - imm32 r6, 0x7019b0a6; - imm32 r7, 0xd028c0a7; - - P4 = 0x4567 (X); - P5 = 0x79ab (X); - FP = 0x6def (X); - - loadsym p1, DATA_ADDR_1; - loadsym p2, DATA_ADDR_2; - - [ P1 + 8 ] = P4; - [ P1 + 12 ] = P5; - [ P2 + 20 ] = P4; - [ P2 + 24 ] = P5; - [ P2 + 32 ] = FP; - R5 = [ P1 + 8 ]; - R4 = [ P1 + 12 ]; - R2 = [ P2 + 20 ]; - R7 = [ P2 + 24 ]; - R1 = [ P2 + 32 ]; - CHECKREG r1, 0x00006DEF; - CHECKREG r2, 0x00004567; - CHECKREG r4, 0x000079AB; - CHECKREG r5, 0x00004567; - CHECKREG r7, 0x000079AB; - - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x60baa0b5; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - P1 = 0x3456 (X); - P2 = 0x1234 (X); - P5 = 0x5e23 (X); - FP = 0x2ac5 (X); - loadsym p4, DATA_ADDR_4; - - [ P4 + 52 ] = P2; - [ P4 + 56 ] = P5; - [ P4 + 64 ] = FP; - R2 = [ P4 + 52 ]; - R5 = [ P4 + 56 ]; - R7 = [ P4 + 64 ]; - CHECKREG r2, 0x00001234; - CHECKREG r5, 0x00005E23; - CHECKREG r7, 0x00002AC5; - -// initial values - imm32 r0, 0x10cf50c0; - imm32 r1, 0x20ce60c1; - imm32 r2, 0x30c370c2; - imm32 r3, 0x40cc80c3; - imm32 r4, 0x50cb90c4; - imm32 r5, 0x60caa0c5; - imm32 r6, 0x70c9b0c6; - imm32 r7, 0xd0c8c0c7; - P1 = 0x2125 (X); - P2 = 0x7345 (X); - P4 = 0x5789 (X); - FP = 0x5bcd (X); - loadsym p5, DATA_ADDR_1; - - [ P5 + 4 ] = P2; - [ P5 + 8 ] = P1; - [ P5 + 12 ] = P2; - R6 = [ P5 + 4 ]; - R5 = [ P5 + 8 ]; - R4 = [ P5 + 12 ]; - CHECKREG r4, 0x00007345; - CHECKREG r5, 0x00002125; - CHECKREG r6, 0x00007345; - -// initial values - imm32 r0, 0x60df50d0; - imm32 r1, 0x70de60d1; - imm32 r2, 0x80dd70d2; - imm32 r3, 0x90dc80d3; - imm32 r4, 0xa0db90d4; - imm32 r5, 0xb0daa0d5; - imm32 r6, 0xc0d9b0d6; - imm32 r7, 0xd0d8c0d7; - P1 = 0x5bcd (X); - P2 = 0x1122 (X); - P4 = 0x6677 (X); - P5 = 0x58ab (X); - loadsym fp, DATA_ADDR_2; - [ FP + 36 ] = P4; - [ FP + 40 ] = P1; - [ FP + 44 ] = P2; - [ FP + 52 ] = P4; - [ FP + 56 ] = P5; - [ FP + 64 ] = P2; - R3 = [ FP + 36 ]; - R4 = [ FP + 40 ]; - R0 = [ FP + 44 ]; - R2 = [ FP + 52 ]; - R5 = [ FP + 56 ]; - R7 = [ FP + 64 ]; - CHECKREG r0, 0x00001122; - CHECKREG r2, 0x00006677; - CHECKREG r3, 0x00006677; - CHECKREG r4, 0x00005BCD; - CHECKREG r5, 0x000058AB; - CHECKREG r7, 0x00001122; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstiifp_ld_dreg.s b/sim/testsuite/sim/bfin/c_ldstiifp_ld_dreg.s deleted file mode 100644 index ad5cb82..0000000 --- a/sim/testsuite/sim/bfin/c_ldstiifp_ld_dreg.s +++ /dev/null @@ -1,528 +0,0 @@ -//Original:testcases/core/c_ldstiifp_ld_dreg/c_ldstiifp_ld_dreg.dsp -// Spec Reference: c_ldstiifp load dreg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - P1 = 0x0000; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0000; - P5 = 0x0000; - SP = 0x0000; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_1, 0xc8; - P3 = I1; SP = I3; - - r0 = [ fp + 0 ]; - R1 = [ FP + 4 ]; - R2 = [ FP + 8 ]; - R3 = [ FP + 12 ]; - R4 = [ FP + 16 ]; - R5 = [ FP + 20 ]; - R6 = [ FP + 24 ]; - R7 = [ FP + 28 ]; - CHECKREG r0, 0x86878889; - CHECKREG r1, 0x80818283; - CHECKREG r2, 0x84858687; - CHECKREG r3, 0x01020304; - CHECKREG r4, 0x05060708; - CHECKREG r5, 0x09101112; - CHECKREG r6, 0x14151617; - - R0 = [ FP + 32 ]; - R1 = [ FP + 36 ]; - R2 = [ FP + 40 ]; - R3 = [ FP + 44 ]; - R4 = [ FP + 48 ]; - R5 = [ FP + 52 ]; - R7 = [ FP + 56 ]; - CHECKREG r0, 0x22232425; - CHECKREG r1, 0x26272829; - CHECKREG r2, 0x30313233; - CHECKREG r3, 0x34353637; - CHECKREG r4, 0x38394041; - CHECKREG r5, 0x42434445; - CHECKREG r6, 0x14151617; - - R0 = [ FP + 56 ]; - R1 = [ FP + 60 ]; - R2 = [ FP + 64 ]; - R3 = [ FP + 68 ]; - R4 = [ FP + 72 ]; - R5 = [ FP + 76 ]; - R6 = [ FP + 80 ]; - CHECKREG r0, 0x46474849; - CHECKREG r1, 0x50515253; - CHECKREG r2, 0x54555657; - CHECKREG r3, 0x58596061; - CHECKREG r4, 0x62636465; - CHECKREG r5, 0x66676869; - CHECKREG r6, 0x74555657; - - R0 = [ FP + 84 ]; - R1 = [ FP + 88 ]; - R2 = [ FP + 92 ]; - R3 = [ FP + 96 ]; - R4 = [ FP + 100 ]; - R5 = [ FP + 104 ]; - R6 = [ FP + 108 ]; - CHECKREG r0, 0x78596067; - CHECKREG r1, 0x72636467; - CHECKREG r2, 0x76676867; - CHECKREG r3, 0x20212223; - CHECKREG r4, 0x24252627; - CHECKREG r5, 0x28292A2B; - CHECKREG r6, 0x2C2D2E2F; - - R0 = [ FP + 112 ]; - R1 = [ FP + 116 ]; - R2 = [ FP + 120 ]; - R3 = [ FP + 124 ]; - R4 = [ FP + 128 ]; - R5 = [ FP + -4 ]; - R6 = [ FP + -8 ]; - CHECKREG r0, 0x30313233; - CHECKREG r1, 0x34353637; - CHECKREG r2, 0x38393A3B; - CHECKREG r3, 0x3C3D3E3F; - CHECKREG r4, 0x91929394; - CHECKREG r5, 0x82838485; - CHECKREG r6, 0x74757677; - - R0 = [ FP + -12 ]; - R1 = [ FP + -16 ]; - R2 = [ FP + -20 ]; - R3 = [ FP + -24 ]; - R4 = [ FP + -28 ]; - R5 = [ FP + -32 ]; - R6 = [ FP + -36 ]; - CHECKREG r0, 0x99717273; - CHECKREG r1, 0x55667788; - CHECKREG r2, 0x11223344; - CHECKREG r3, 0x1C1D1E1F; - CHECKREG r4, 0x18191A1B; - CHECKREG r5, 0x14151617; - CHECKREG r6, 0x10111213; - - R0 = [ FP + -40 ]; - R1 = [ FP + -44 ]; - R2 = [ FP + -48 ]; - R3 = [ FP + -64 ]; - R4 = [ FP + -88 ]; - R5 = [ FP + -96 ]; - R6 = [ FP + -128 ]; - CHECKREG r0, 0x0C0D0E0F; - CHECKREG r1, 0x08090A0B; - CHECKREG r2, 0x04050607; - CHECKREG r3, 0x78596067; - CHECKREG r4, 0x50515253; - CHECKREG r5, 0x42434445; - CHECKREG r6, 0x09101112; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstiifp_ld_preg.s b/sim/testsuite/sim/bfin/c_ldstiifp_ld_preg.s deleted file mode 100644 index 7945d30..0000000 --- a/sim/testsuite/sim/bfin/c_ldstiifp_ld_preg.s +++ /dev/null @@ -1,511 +0,0 @@ -//Original:testcases/core/c_ldstiifp_ld_preg/c_ldstiifp_ld_preg.dsp -// Spec Reference: c_ldstiifp load preg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_1, 0xc8; - P3 = I1; SP = I3; - - P3 = I1; SP = I3; - p1 = [ fp + 0 ]; - P2 = [ FP + -4 ]; - P3 = [ FP + -8 ]; - P4 = [ FP + -12 ]; - P5 = [ FP + -16 ]; - SP = [ FP + -20 ]; - FP = [ FP + -24 ]; - CHECKREG p1, 0x86878889; - CHECKREG p2, 0x82838485; - CHECKREG p3, 0x74757677; - CHECKREG p4, 0x99717273; - CHECKREG p5, 0x55667788; - CHECKREG sp, 0x11223344; - CHECKREG fp, 0x1C1D1E1F; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_1, 0xc8; - P3 = I1; SP = I3; - - P1 = [ FP + -28 ]; - P2 = [ FP + -32 ]; - P3 = [ FP + -36 ]; - P4 = [ FP + -40 ]; - P5 = [ FP + -44 ]; - SP = [ FP + -48 ]; - FP = [ FP + -52 ]; - CHECKREG p1, 0x18191A1B; - CHECKREG p2, 0x14151617; - CHECKREG p3, 0x10111213; - CHECKREG p4, 0x0C0D0E0F; - CHECKREG p5, 0x08090A0B; - CHECKREG sp, 0x04050607; - CHECKREG fp, 0x00010203; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_1, 0xc8; - P3 = I1; SP = I3; - - P1 = [ FP + -56 ]; - P2 = [ FP + -60 ]; - P3 = [ FP + -64 ]; - P4 = [ FP + -68 ]; - P5 = [ FP + -72 ]; - SP = [ FP + -76 ]; - FP = [ FP + -80 ]; - CHECKREG p1, 0x76676867; - CHECKREG p2, 0x72636467; - CHECKREG p3, 0x78596067; - CHECKREG p4, 0x74555657; - CHECKREG p5, 0x66676869; - CHECKREG sp, 0x62636465; - CHECKREG fp, 0x58596061; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_1, 0xc8; - P3 = I1; SP = I3; - - P1 = [ FP + -84 ]; - P2 = [ FP + -88 ]; - P3 = [ FP + -92 ]; - P4 = [ FP + -96 ]; - P5 = [ FP + -100 ]; - SP = [ FP + -104 ]; - FP = [ FP + -108 ]; - CHECKREG p1, 0x54555657; - CHECKREG p2, 0x50515253; - CHECKREG p3, 0x46474849; - CHECKREG p4, 0x42434445; - CHECKREG p5, 0x38394041; - CHECKREG sp, 0x34353637; - CHECKREG fp, 0x30313233; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_1, 0xc8; - P3 = I1; SP = I3; - - P1 = [ FP + -112 ]; - P2 = [ FP + -116 ]; - P3 = [ FP + -120 ]; - P4 = [ FP + -124 ]; - P5 = [ FP + -128 ]; - SP = [ FP + -4 ]; - FP = [ FP + -8 ]; - CHECKREG p1, 0x26272829; - CHECKREG p2, 0x22232425; - CHECKREG p3, 0x18192021; - CHECKREG p4, 0x14151617; - CHECKREG p5, 0x09101112; - CHECKREG sp, 0x82838485; - CHECKREG fp, 0x74757677; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstiifp_st_dreg.s b/sim/testsuite/sim/bfin/c_ldstiifp_st_dreg.s deleted file mode 100644 index 4d1a363..0000000 --- a/sim/testsuite/sim/bfin/c_ldstiifp_st_dreg.s +++ /dev/null @@ -1,641 +0,0 @@ -//Original:testcases/core/c_ldstiifp_st_dreg/c_ldstiifp_st_dreg.dsp -// Spec Reference: c_ldstiifp store dreg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -I0 = P3; -I2 = SP; - -// initial values - imm32 r0, 0x105f50a0; - imm32 r1, 0x204e60a1; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80a3; - imm32 r4, 0x501b90a4; - imm32 r5, 0x600aa0a5; - imm32 r6, 0x7019b0a6; - imm32 r7, 0xd028c0a7; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0x00; - loadsym i1, DATA_ADDR_3, 0x00; - loadsym p4, DATA_ADDR_4, 0x00; - loadsym p5, DATA_ADDR_1, 0x00; - loadsym i3, DATA_ADDR_3, 0x00; - loadsym fp, DATA_ADDR_1, 0xC8; - P3 = I1; SP = I3; - - [ FP + -4 ] = R0; - [ FP + -8 ] = R1; - [ FP + -12 ] = R2; - [ FP + -16 ] = R3; - [ FP + -20 ] = R4; - [ FP + -24 ] = R5; - [ FP + -28 ] = R6; - [ FP + -32 ] = R7; - R6 = [ FP + -4 ]; - R5 = [ FP + -8 ]; - R4 = [ FP + -12 ]; - R3 = [ FP + -16 ]; - R2 = [ FP + -20 ]; - R7 = [ FP + -24 ]; - R0 = [ FP + -28 ]; - R1 = [ FP + -32 ]; - CHECKREG r0, 0x7019B0A6; - CHECKREG r1, 0xD028C0A7; - CHECKREG r2, 0x501B90A4; - CHECKREG r3, 0x402C80A3; - CHECKREG r4, 0x300370A2; - CHECKREG r5, 0x204E60A1; - CHECKREG r6, 0x105F50A0; - CHECKREG r7, 0x600AA0A5; - - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x60baa0b5; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - [ FP + -36 ] = R0; - [ FP + -40 ] = R1; - [ FP + -44 ] = R2; - [ FP + -48 ] = R3; - [ FP + -52 ] = R4; - [ FP + -56 ] = R5; - [ FP + -60 ] = R6; - [ FP + -64 ] = R7; - R3 = [ FP + -36 ]; - R4 = [ FP + -40 ]; - R0 = [ FP + -44 ]; - R1 = [ FP + -48 ]; - R2 = [ FP + -52 ]; - R5 = [ FP + -56 ]; - R6 = [ FP + -60 ]; - R7 = [ FP + -64 ]; - CHECKREG r0, 0x30BD70B2; - CHECKREG r1, 0x40BC80B3; - CHECKREG r2, 0x55BB90B4; - CHECKREG r3, 0x10BF50B0; - CHECKREG r4, 0x20BE60B1; - CHECKREG r5, 0x60BAA0B5; - CHECKREG r6, 0x70B9B0B6; - CHECKREG r7, 0x80B8C0B7; - -// initial values - imm32 r0, 0x10cf50c0; - imm32 r1, 0x20ce60c1; - imm32 r2, 0x30c370c2; - imm32 r3, 0x40cc80c3; - imm32 r4, 0x50cb90c4; - imm32 r5, 0x60caa0c5; - imm32 r6, 0x70c9b0c6; - imm32 r7, 0xd0c8c0c7; - [ FP + -68 ] = R0; - [ FP + -72 ] = R1; - [ FP + -76 ] = R2; - [ FP + -80 ] = R3; - [ FP + -84 ] = R4; - [ FP + -88 ] = R5; - [ FP + -92 ] = R6; - [ FP + -96 ] = R7; - R6 = [ FP + -68 ]; - R5 = [ FP + -72 ]; - R4 = [ FP + -76 ]; - R3 = [ FP + -80 ]; - R2 = [ FP + -84 ]; - R0 = [ FP + -88 ]; - R7 = [ FP + -92 ]; - R1 = [ FP + -96 ]; - CHECKREG r0, 0x60CAA0C5; - CHECKREG r1, 0xD0C8C0C7; - CHECKREG r2, 0x50CB90C4; - CHECKREG r3, 0x40CC80C3; - CHECKREG r4, 0x30C370C2; - CHECKREG r5, 0x20CE60C1; - CHECKREG r6, 0x10CF50C0; - -// initial values - imm32 r0, 0x60df50d0; - imm32 r1, 0x70de60d1; - imm32 r2, 0x80dd70d2; - imm32 r3, 0x90dc80d3; - imm32 r4, 0xa0db90d4; - imm32 r5, 0xb0daa0d5; - imm32 r6, 0xc0d9b0d6; - imm32 r7, 0xd0d8c0d7; - [ FP + -100 ] = R0; - [ FP + -104 ] = R1; - [ FP + -108 ] = R2; - [ FP + -112 ] = R3; - [ FP + -116 ] = R4; - [ FP + -120 ] = R5; - [ FP + -124 ] = R6; - [ FP + -128 ] = R7; - R3 = [ FP + -100 ]; - R4 = [ FP + -104 ]; - R0 = [ FP + -108 ]; - R1 = [ FP + -112 ]; - R2 = [ FP + -116 ]; - R5 = [ FP + -120 ]; - R6 = [ FP + -124 ]; - R7 = [ FP + -128 ]; - CHECKREG r0, 0x80DD70D2; - CHECKREG r1, 0x90DC80D3; - CHECKREG r2, 0xA0DB90D4; - CHECKREG r3, 0x60DF50D0; - CHECKREG r4, 0x70DE60D1; - CHECKREG r5, 0xB0DAA0D5; - CHECKREG r6, 0xC0D9B0D6; - CHECKREG r7, 0xD0D8C0D7; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstiifp_st_preg.s b/sim/testsuite/sim/bfin/c_ldstiifp_st_preg.s deleted file mode 100644 index 3a132dc..0000000 --- a/sim/testsuite/sim/bfin/c_ldstiifp_st_preg.s +++ /dev/null @@ -1,618 +0,0 @@ -//Original:testcases/core/c_ldstiifp_st_preg/c_ldstiifp_st_preg.dsp -// Spec Reference: c_ldstiifp store preg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; - -// initial values - imm32 r0, 0x105f50a0; - imm32 r1, 0x204e60a1; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80a3; - imm32 r4, 0x501b90a4; - imm32 r5, 0x600aa0a5; - imm32 r6, 0x7019b0a6; - imm32 r7, 0xd028c0a7; - imm32 p1, 0x12345678; - imm32 p2, 0x6789abcd; - imm32 p4, 0x24680123; - imm32 p5, 0x57913597; - - loadsym fp, DATA_ADDR_1, 0xC8; - [ FP + -4 ] = P2; - [ FP + -8 ] = P1; - [ FP + -12 ] = P2; - [ FP + -20 ] = P4; - [ FP + -24 ] = P5; - [ FP + -32 ] = P5; - R6 = [ FP + -4 ]; - R5 = [ FP + -8 ]; - R4 = [ FP + -12 ]; - R2 = [ FP + -20 ]; - R7 = [ FP + -24 ]; - R1 = [ FP + -32 ]; - CHECKREG r1, 0x57913597; - CHECKREG r2, 0x24680123; - CHECKREG r4, 0x6789ABCD; - CHECKREG r5, 0x12345678; - CHECKREG r6, 0x6789ABCD; - CHECKREG r7, 0x57913597; - - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x60baa0b5; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - imm32 p1, 0x11223344; - imm32 p2, 0x2349abcd; - imm32 p4, 0x44556623; - imm32 p5, 0x57913597; - [ FP + -36 ] = P4; - [ FP + -40 ] = P1; - [ FP + -44 ] = P2; - [ FP + -52 ] = P4; - [ FP + -56 ] = P5; - [ FP + -64 ] = P1; - R3 = [ FP + -36 ]; - R4 = [ FP + -40 ]; - R0 = [ FP + -44 ]; - R2 = [ FP + -52 ]; - R5 = [ FP + -56 ]; - R7 = [ FP + -64 ]; - CHECKREG r0, 0x2349ABCD; - CHECKREG r2, 0x44556623; - CHECKREG r3, 0x44556623; - CHECKREG r4, 0x11223344; - CHECKREG r5, 0x57913597; - CHECKREG r7, 0x11223344; - -// initial values - imm32 r0, 0x10cf50c0; - imm32 r1, 0x20ce60c1; - imm32 r2, 0x30c370c2; - imm32 r3, 0x40cc80c3; - imm32 r4, 0x50cb90c4; - imm32 r5, 0x60caa0c5; - imm32 r6, 0x70c9b0c6; - imm32 r7, 0xd0c8c0c7; - imm32 p1, 0x19012345; - imm32 p2, 0x2146abcd; - imm32 p4, 0x24680123; - imm32 p5, 0x57913597; - [ FP + -68 ] = P2; - [ FP + -72 ] = P1; - [ FP + -76 ] = P2; - [ FP + -84 ] = P4; - [ FP + -88 ] = P5; - [ FP + -96 ] = P2; - R6 = [ FP + -68 ]; - R5 = [ FP + -72 ]; - R4 = [ FP + -76 ]; - R2 = [ FP + -84 ]; - R0 = [ FP + -88 ]; - R1 = [ FP + -96 ]; - CHECKREG r0, 0x57913597; - CHECKREG r1, 0x2146ABCD; - CHECKREG r2, 0x24680123; - CHECKREG r4, 0x2146ABCD; - CHECKREG r5, 0x19012345; - CHECKREG r6, 0x2146ABCD; - -// initial values - imm32 r0, 0x60df50d0; - imm32 r1, 0x70de60d1; - imm32 r2, 0x80dd70d2; - imm32 r3, 0x90dc80d3; - imm32 r4, 0xa0db90d4; - imm32 r5, 0xb0daa0d5; - imm32 r6, 0xc0d9b0d6; - imm32 r7, 0xd0d8c0d7; - imm32 p1, 0x13579678; - imm32 p2, 0x2468abcd; - imm32 p4, 0x45678123; - imm32 p5, 0x57913597; - [ FP + -104 ] = P1; - [ FP + -108 ] = P2; - [ FP + -116 ] = P4; - [ FP + -120 ] = P5; - R4 = [ FP + -104 ]; - R0 = [ FP + -108 ]; - R2 = [ FP + -116 ]; - R5 = [ FP + -120 ]; - CHECKREG r0, 0x2468ABCD; - CHECKREG r2, 0x45678123; - CHECKREG r4, 0x13579678; - CHECKREG r5, 0x57913597; - - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_hi.s b/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_hi.s deleted file mode 100644 index 982444e..0000000 --- a/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_hi.s +++ /dev/null @@ -1,411 +0,0 @@ -//Original:testcases/core/c_ldstpmod_ld_dr_hi/c_ldstpmod_ld_dr_hi.dsp -// Spec Reference: c_ldstpmod load dr hi -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_2, 0x04; - loadsym p2, DATA_ADDR_3, 0x04; - loadsym i1, DATA_ADDR_4, 0x04; - loadsym p4, DATA_ADDR_5, 0x08; - loadsym p5, DATA_ADDR_1, 0x08; - loadsym fp, DATA_ADDR_6, 0x08; - loadsym i3, DATA_ADDR_7, 0x0c; - P3 = I1; SP = I3; - - R0.H = W [ P1 ]; - R1.H = W [ P1 ]; - R2.H = W [ P1 ]; - R3.H = W [ P1 ]; - R4.H = W [ P1 ]; - R5.H = W [ P1 ]; - R6.H = W [ P1 ]; - R7.H = W [ P1 ]; - CHECKREG r0, 0x26270000; - CHECKREG r1, 0x26270000; - CHECKREG r2, 0x26270000; - CHECKREG r3, 0x26270000; - CHECKREG r4, 0x26270000; - CHECKREG r5, 0x26270000; - CHECKREG r6, 0x26270000; - CHECKREG r7, 0x26270000; - - R0.H = W [ P2 ]; - R1.H = W [ P2 ]; - R2.H = W [ P2 ]; - R3.H = W [ P2 ]; - R4.H = W [ P2 ]; - R5.H = W [ P2 ]; - R6.H = W [ P2 ]; - R7.H = W [ P2 ]; - CHECKREG r0, 0x46470000; - CHECKREG r1, 0x46470000; - CHECKREG r2, 0x46470000; - CHECKREG r3, 0x46470000; - CHECKREG r4, 0x46470000; - CHECKREG r5, 0x46470000; - CHECKREG r6, 0x46470000; - CHECKREG r7, 0x46470000; - - R0.H = W [ P3 ]; - R1.H = W [ P3 ]; - R2.H = W [ P3 ]; - R3.H = W [ P3 ]; - R4.H = W [ P3 ]; - R5.H = W [ P3 ]; - R6.H = W [ P3 ]; - R7.H = W [ P3 ]; - CHECKREG r0, 0x66670000; - CHECKREG r1, 0x66670000; - CHECKREG r2, 0x66670000; - CHECKREG r3, 0x66670000; - CHECKREG r4, 0x66670000; - CHECKREG r5, 0x66670000; - CHECKREG r6, 0x66670000; - CHECKREG r7, 0x66670000; - - R0.H = W [ P4 ]; - R1.H = W [ P4 ]; - R2.H = W [ P4 ]; - R3.H = W [ P4 ]; - R4.H = W [ P4 ]; - R5.H = W [ P4 ]; - R6.H = W [ P4 ]; - R7.H = W [ P4 ]; - CHECKREG r0, 0x8A8B0000; - CHECKREG r1, 0x8A8B0000; - CHECKREG r2, 0x8A8B0000; - CHECKREG r3, 0x8A8B0000; - CHECKREG r4, 0x8A8B0000; - CHECKREG r5, 0x8A8B0000; - CHECKREG r6, 0x8A8B0000; - CHECKREG r7, 0x8A8B0000; - - R0.H = W [ P5 ]; - R1.H = W [ P5 ]; - R2.H = W [ P5 ]; - R3.H = W [ P5 ]; - R4.H = W [ P5 ]; - R5.H = W [ P5 ]; - R6.H = W [ P5 ]; - R7.H = W [ P5 ]; - CHECKREG r0, 0x0A0B0000; - CHECKREG r1, 0x0A0B0000; - CHECKREG r2, 0x0A0B0000; - CHECKREG r3, 0x0A0B0000; - CHECKREG r4, 0x0A0B0000; - CHECKREG r5, 0x0A0B0000; - CHECKREG r6, 0x0A0B0000; - CHECKREG r7, 0x0A0B0000; - - R0.H = W [ SP ]; - R1.H = W [ SP ]; - R2.H = W [ SP ]; - R3.H = W [ SP ]; - R4.H = W [ SP ]; - R5.H = W [ SP ]; - R6.H = W [ SP ]; - R7.H = W [ SP ]; - CHECKREG r0, 0x8E8F0000; - CHECKREG r1, 0x8E8F0000; - CHECKREG r2, 0x8E8F0000; - CHECKREG r3, 0x8E8F0000; - CHECKREG r4, 0x8E8F0000; - CHECKREG r5, 0x8E8F0000; - CHECKREG r6, 0x8E8F0000; - CHECKREG r7, 0x8E8F0000; - - R0.H = W [ FP ]; - R1.H = W [ FP ]; - R2.H = W [ FP ]; - R3.H = W [ FP ]; - R4.H = W [ FP ]; - R5.H = W [ FP ]; - R6.H = W [ FP ]; - R7.H = W [ FP ]; - CHECKREG r0, 0x0A0B0000; - CHECKREG r1, 0x0A0B0000; - CHECKREG r2, 0x0A0B0000; - CHECKREG r3, 0x0A0B0000; - CHECKREG r4, 0x0A0B0000; - CHECKREG r5, 0x0A0B0000; - CHECKREG r6, 0x0A0B0000; - CHECKREG r7, 0x0A0B0000; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_lo.s b/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_lo.s deleted file mode 100644 index e399a24..0000000 --- a/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_lo.s +++ /dev/null @@ -1,410 +0,0 @@ -//Original:testcases/core/c_ldstpmod_ld_dr_lo/c_ldstpmod_ld_dr_lo.dsp -// Spec Reference: c_ldstpmod load dr lo -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS(0); -I0 = P3; -I2 = SP; - -// initial values - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_2, 0x04; - loadsym p2, DATA_ADDR_3, 0x04; - loadsym i1, DATA_ADDR_4, 0x04; - loadsym p4, DATA_ADDR_5, 0x08; - loadsym p5, DATA_ADDR_1, 0x08; - loadsym fp, DATA_ADDR_6, 0x08; - loadsym i3, DATA_ADDR_7, 0x0c; - P3 = I1; SP = I3; - - R0.L = W [ P1 ]; - R1.L = W [ P1 ]; - R2.L = W [ P1 ]; - R3.L = W [ P1 ]; - R4.L = W [ P1 ]; - R5.L = W [ P1 ]; - R6.L = W [ P1 ]; - R7.L = W [ P1 ]; - CHECKREG r0, 0x00002627; - CHECKREG r1, 0x00002627; - CHECKREG r2, 0x00002627; - CHECKREG r3, 0x00002627; - CHECKREG r4, 0x00002627; - CHECKREG r5, 0x00002627; - CHECKREG r6, 0x00002627; - CHECKREG r7, 0x00002627; - - R0.L = W [ P2 ]; - R1.L = W [ P2 ]; - R2.L = W [ P2 ]; - R3.L = W [ P2 ]; - R4.L = W [ P2 ]; - R5.L = W [ P2 ]; - R6.L = W [ P2 ]; - R7.L = W [ P2 ]; - CHECKREG r0, 0x00004647; - CHECKREG r1, 0x00004647; - CHECKREG r2, 0x00004647; - CHECKREG r3, 0x00004647; - CHECKREG r4, 0x00004647; - CHECKREG r5, 0x00004647; - CHECKREG r6, 0x00004647; - CHECKREG r7, 0x00004647; - - R0.L = W [ P3 ]; - R1.L = W [ P3 ]; - R2.L = W [ P3 ]; - R3.L = W [ P3 ]; - R4.L = W [ P3 ]; - R5.L = W [ P3 ]; - R6.L = W [ P3 ]; - R7.L = W [ P3 ]; - CHECKREG r0, 0x00006667; - CHECKREG r1, 0x00006667; - CHECKREG r2, 0x00006667; - CHECKREG r3, 0x00006667; - CHECKREG r4, 0x00006667; - CHECKREG r5, 0x00006667; - CHECKREG r6, 0x00006667; - CHECKREG r7, 0x00006667; - - R0.L = W [ P4 ]; - R1.L = W [ P4 ]; - R2.L = W [ P4 ]; - R3.L = W [ P4 ]; - R4.L = W [ P4 ]; - R5.L = W [ P4 ]; - R6.L = W [ P4 ]; - R7.L = W [ P4 ]; - CHECKREG r0, 0x00008A8B; - CHECKREG r1, 0x00008A8B; - CHECKREG r2, 0x00008A8B; - CHECKREG r3, 0x00008A8B; - CHECKREG r4, 0x00008A8B; - CHECKREG r5, 0x00008A8B; - CHECKREG r6, 0x00008A8B; - CHECKREG r7, 0x00008A8B; - - R0.L = W [ P5 ]; - R1.L = W [ P5 ]; - R2.L = W [ P5 ]; - R3.L = W [ P5 ]; - R4.L = W [ P5 ]; - R5.L = W [ P5 ]; - R6.L = W [ P5 ]; - R7.L = W [ P5 ]; - CHECKREG r0, 0x00000A0B; - CHECKREG r1, 0x00000A0B; - CHECKREG r2, 0x00000A0B; - CHECKREG r3, 0x00000A0B; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00000A0B; - CHECKREG r6, 0x00000A0B; - CHECKREG r7, 0x00000A0B; - - R0.L = W [ SP ]; - R1.L = W [ SP ]; - R2.L = W [ SP ]; - R3.L = W [ SP ]; - R4.L = W [ SP ]; - R5.L = W [ SP ]; - R6.L = W [ SP ]; - R7.L = W [ SP ]; - CHECKREG r0, 0x00008E8F; - CHECKREG r1, 0x00008E8F; - CHECKREG r2, 0x00008E8F; - CHECKREG r3, 0x00008E8F; - CHECKREG r4, 0x00008E8F; - CHECKREG r5, 0x00008E8F; - CHECKREG r6, 0x00008E8F; - CHECKREG r7, 0x00008E8F; - - R0.L = W [ FP ]; - R1.L = W [ FP ]; - R2.L = W [ FP ]; - R3.L = W [ FP ]; - R4.L = W [ FP ]; - R5.L = W [ FP ]; - R6.L = W [ FP ]; - R7.L = W [ FP ]; - CHECKREG r0, 0x00000A0B; - CHECKREG r1, 0x00000A0B; - CHECKREG r2, 0x00000A0B; - CHECKREG r3, 0x00000A0B; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00000A0B; - CHECKREG r6, 0x00000A0B; - CHECKREG r7, 0x00000A0B; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_ld_dreg.s b/sim/testsuite/sim/bfin/c_ldstpmod_ld_dreg.s deleted file mode 100644 index cfcdf1d..0000000 --- a/sim/testsuite/sim/bfin/c_ldstpmod_ld_dreg.s +++ /dev/null @@ -1,462 +0,0 @@ -//Original:testcases/core/c_ldstpmod_ld_dreg/c_ldstpmod_ld_dreg.dsp -// Spec Reference: c_ldstpmod load dreg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -I0 = P3; -I2 = SP; - -// initial values - P1 = 0x0004; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0008; - FP = 0x0008; - SP = 0x000c; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x00; - P3 = I1; SP = I3; - - R0 = [ P5 ++ P3 ]; - R1 = [ P5 ++ P1 ]; - R2 = [ P5 ++ P2 ]; - R3 = [ P5 ++ P3 ]; - R4 = [ P5 ++ P4 ]; - R5 = [ P5 ++ SP ]; - R6 = [ P5 ++ FP ]; - CHECKREG r0, 0x00010203; - CHECKREG r1, 0x04050607; - CHECKREG r2, 0x08090A0B; - CHECKREG r3, 0x0C0D0E0F; - CHECKREG r4, 0x10111213; - CHECKREG r5, 0x18191A1B; - CHECKREG r6, 0x55667788; - -// initial values - P5 = 0x0000; - P2 = 0x0004; - P3 = 0x0008; - P4 = 0x0008; - FP = 0x000c; - SP = 0x000c; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x04; - P3 = I1; SP = I3; - - R0 = [ P1 ++ P5 ]; - R1 = [ P1 ++ P3 ]; - R2 = [ P1 ++ P2 ]; - R3 = [ P1 ++ P3 ]; - R4 = [ P1 ++ P4 ]; - R5 = [ P1 ++ SP ]; - R6 = [ P1 ++ FP ]; - CHECKREG r0, 0x04050607; - CHECKREG r1, 0x04050607; - CHECKREG r2, 0x0C0D0E0F; - CHECKREG r3, 0x10111213; - CHECKREG r4, 0x18191A1B; - CHECKREG r5, 0x11223344; - CHECKREG r6, 0x74757677; - -// initial values - P5 = 0x0000; - P1 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0008; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p2, DATA_ADDR_3, 0x00; - P3 = I1; SP = I3; - - R0 = [ P2 ++ P5 ]; - R1 = [ P2 ++ P1 ]; - R2 = [ P2 ++ P4 ]; - R3 = [ P2 ++ P3 ]; - R4 = [ P2 ++ P4 ]; - R5 = [ P2 ++ SP ]; - R6 = [ P2 ++ FP ]; - CHECKREG r0, 0x40414243; - CHECKREG r1, 0x40414243; - CHECKREG r2, 0x44454647; - CHECKREG r3, 0x48494A4B; - CHECKREG r4, 0x4C4D4E4F; - CHECKREG r5, 0x50515253; - CHECKREG r6, 0x54555657; - -// initial values - P5 = 0x0010; - P1 = 0x0004; - P2 = 0x0004; - P4 = 0x0004; - FP = 0x0004; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i1, DATA_ADDR_1, 0x04; - P3 = I1; SP = I3; - - R0 = [ P3 ++ P5 ]; - R1 = [ P3 ++ P1 ]; - R2 = [ P3 ++ P2 ]; - R3 = [ P3 ++ P1 ]; - R4 = [ P3 ++ P4 ]; - R5 = [ P3 ++ SP ]; - R6 = [ P3 ++ FP ]; - CHECKREG r0, 0x04050607; - CHECKREG r1, 0x14151617; - CHECKREG r2, 0x18191A1B; - CHECKREG r3, 0x1C1D1E1F; - CHECKREG r4, 0x11223344; - CHECKREG r5, 0x55667788; - CHECKREG r6, 0x99717273; - -// initial values - P5 = 0x0004; - P1 = 0x0008; - P2 = 0x000C; - P3 = 0x0004; - FP = 0x0008; - SP = 0x0008; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p4, DATA_ADDR_2, 0x04; - P3 = I1; SP = I3; - - R0 = [ P4 ++ P5 ]; - R1 = [ P4 ++ P1 ]; - R2 = [ P4 ++ P2 ]; - R3 = [ P4 ++ P3 ]; - R4 = [ P4 ++ P2 ]; - R5 = [ P4 ++ SP ]; - R6 = [ P4 ++ FP ]; - CHECKREG r0, 0x24252627; - CHECKREG r1, 0x28292A2B; - CHECKREG r2, 0x30313233; - CHECKREG r3, 0x3C3D3E3F; - CHECKREG r4, 0x91929394; - CHECKREG r5, 0xA5A6A7A8; - CHECKREG r6, 0xB3B4B5B6; - -// initial values - P5 = 0x0000; - P1 = 0x0010; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - SP = 0x0008; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_1, 0x04; - P3 = I1; SP = I3; - - R0 = [ FP ++ P5 ]; - R1 = [ FP ++ P1 ]; - R2 = [ FP ++ P2 ]; - R3 = [ FP ++ P3 ]; - R4 = [ FP ++ P4 ]; - R5 = [ FP ++ SP ]; - R6 = [ FP ++ SP ]; - CHECKREG r0, 0x04050607; - CHECKREG r1, 0x04050607; - CHECKREG r2, 0x14151617; - CHECKREG r3, 0x18191A1B; - CHECKREG r4, 0x1C1D1E1F; - CHECKREG r5, 0x11223344; - CHECKREG r6, 0x99717273; - -// initial values - P5 = 0x0000; - P1 = 0x0004; - P2 = 0x0008; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i3, DATA_ADDR_1, 0x08; - P3 = I1; SP = I3; - - R0 = [ SP ++ P5 ]; - R1 = [ SP ++ P1 ]; - R2 = [ SP ++ P2 ]; - R3 = [ SP ++ P3 ]; - R4 = [ SP ++ P4 ]; - R5 = [ SP ++ FP ]; - R6 = [ SP ++ FP ]; - CHECKREG r0, 0x08090A0B; - CHECKREG r1, 0x08090A0B; - CHECKREG r2, 0x0C0D0E0F; - CHECKREG r3, 0x14151617; - CHECKREG r4, 0x18191A1B; - CHECKREG r5, 0x1C1D1E1F; - CHECKREG r6, 0x11223344; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_ld_h_xh.s b/sim/testsuite/sim/bfin/c_ldstpmod_ld_h_xh.s deleted file mode 100644 index c3c4eda..0000000 --- a/sim/testsuite/sim/bfin/c_ldstpmod_ld_h_xh.s +++ /dev/null @@ -1,458 +0,0 @@ -//Original:testcases/core/c_ldstpmod_ld_h_xh/c_ldstpmod_ld_h_xh.dsp -// Spec Reference: c_ldstpmod load dreg h & xh -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - P4 = 0x0002; - FP = 0x0002; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x00; - P3 = I1; SP = I3; - R0 = W [ P5 ++ P1 ] (Z); - R1 = W [ P5 ++ P1 ] (Z); - R2 = W [ P5 ++ P2 ] (Z); - R3 = W [ P5 ++ P3 ] (Z); - R4 = W [ P5 ++ P4 ] (Z); - R5 = W [ P5 ++ SP ] (Z); - R6 = W [ P5 ++ FP ] (Z); - CHECKREG r0, 0x0000A203; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x0000B607; - CHECKREG r3, 0x00009405; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00000809; - CHECKREG r6, 0x0000CE0F; - -// initial values - P5 = 0x0002; - P2 = 0x0002; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0004; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - P3 = I1; SP = I3; - R0 = W [ P1 ++ P5 ] (X); - R1 = W [ P1 ++ P2 ] (X); - R2 = W [ P1 ++ P2 ] (X); - R3 = W [ P1 ++ P3 ] (X); - R4 = W [ P1 ++ P4 ] (X); - R5 = W [ P1 ++ SP ] (X); - R6 = W [ P1 ++ FP ] (X); - CHECKREG r0, 0xFFFFA203; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0xFFFFB607; - CHECKREG r3, 0xFFFF9405; - CHECKREG r4, 0x00000809; - CHECKREG r5, 0xFFFFAC0D; - CHECKREG r6, 0x00001011; - -// initial values - P5 = 0x0002; - P1 = 0x0002; - P3 = 0x0002; - P4 = 0x0004; - FP = 0x0006; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p2, DATA_ADDR_3, 0x06; - P3 = I1; SP = I3; - R0 = W [ P2 ++ P5 ] (Z); - R1 = W [ P2 ++ P1 ] (Z); - R2 = W [ P2 ++ P2 ] (Z); - R3 = W [ P2 ++ P3 ] (Z); - R4 = W [ P2 ++ P4 ] (Z); - R5 = W [ P2 ++ SP ] (Z); - R6 = W [ P2 ++ FP ] (Z); - CHECKREG r0, 0x00008445; - CHECKREG r1, 0x00004A4B; - CHECKREG r2, 0x00004849; - CHECKREG r3, 0x00004849; - CHECKREG r4, 0x00004E4F; - CHECKREG r5, 0x00005253; - CHECKREG r6, 0x00005051; - -// initial values - P5 = 0x0004; - P1 = 0x0002; - P2 = 0x0002; - P4 = 0x0004; - FP = 0x1002 (X); - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i1, DATA_ADDR_1, 0x02; - P3 = I1; SP = I3; - R0 = W [ P3 ++ P5 ] (X); - R1 = W [ P3 ++ P1 ] (X); - R2 = W [ P3 ++ P2 ] (X); - R3 = W [ P3 ++ P3 ] (X); - R4 = W [ P3 ++ P4 ] (X); - R5 = W [ P3 ++ SP ] (X); - R6 = W [ P3 ++ FP ] (X); - CHECKREG r0, 0x00000001; - CHECKREG r1, 0xFFFF9405; - CHECKREG r2, 0x00000A0B; - CHECKREG r3, 0x00000809; - CHECKREG r4, 0x00000809; - CHECKREG r5, 0xFFFFAC0D; - CHECKREG r6, 0x00001213; - -// initial values - P5 = 0x0002; - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - FP = 0x0002; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p4, DATA_ADDR_2, 0x00; - P3 = I1; SP = I3; - R0 = W [ P4 ++ P5 ] (Z); - R1 = W [ P4 ++ P1 ] (X); - R2 = W [ P4 ++ P2 ] (X); - R3 = W [ P4 ++ P3 ] (Z); - R4 = W [ P4 ++ P4 ] (Z); - R5 = W [ P4 ++ SP ] (X); - R6 = W [ P4 ++ FP ] (X); - CHECKREG r0, 0x00002223; - CHECKREG r1, 0x00002021; - CHECKREG r2, 0x00002627; - CHECKREG r3, 0x0000A425; - CHECKREG r4, 0x00002A2B; - CHECKREG r5, 0x00002A2B; - CHECKREG r6, 0xFFFF8829; - -// initial values - P5 = 0x0000; - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - P4 = 0x0002; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_1, 0x02; - P3 = I1; SP = I3; - R0 = W [ FP ++ P5 ] (X); - R1 = W [ FP ++ P1 ] (X); - R2 = W [ FP ++ P2 ] (X); - R3 = W [ FP ++ P3 ] (X); - R4 = W [ FP ++ P4 ] (Z); - R5 = W [ FP ++ SP ] (Z); - R6 = W [ FP ++ FP ] (X); - CHECKREG r0, 0x00000001; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0xFFFFB607; - CHECKREG r3, 0xFFFF9405; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00000809; - CHECKREG r6, 0xFFFFAC0D; - -// initial values - P5 = 0x0000; - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - P4 = 0x0002; - FP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i3, DATA_ADDR_1, 0x04; - P3 = I1; SP = I3; - - R0 = W [ SP ++ P5 ] (Z); - R1 = W [ SP ++ P1 ] (X); - R2 = W [ SP ++ P2 ] (Z); - R3 = W [ SP ++ P3 ] (X); - R4 = W [ SP ++ P4 ] (Z); - R5 = W [ SP ++ P1 ] (X); - R6 = W [ SP ++ FP ] (Z); - CHECKREG r0, 0x0000B607; - CHECKREG r1, 0xFFFFB607; - CHECKREG r2, 0x00009405; - CHECKREG r3, 0x00000A0B; - CHECKREG r4, 0x00000809; - CHECKREG r5, 0xFFFFCE0F; - CHECKREG r6, 0x0000AC0D; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data - .space (0x2000); - -DATA_ADDR_1: - .dd 0x0001a203 - .dd 0x9405b607 - .dd 0x08090A0B - .dd 0xaC0DcE0F - .dd 0x10111213 - .dd 0xb415c617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0xa5060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0xc8192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0xb0313233 - .dd 0x34353637 - .dd 0xd8394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0xf0515253 - .dd 0x54555657 - .dd 0xe8596061 - .dd 0x62636465 - .dd 0xf6676869 - .dd 0x74555657 - .dd 0xa8596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0xa4252627 - .dd 0x88292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x84454647 - .dd 0x48494A4B - .dd 0x9C4D4E4F - .dd 0x50515253 - .dd 0xa4555657 - .dd 0xb8595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x90616263 - .dd 0x64656667 - .dd 0xa8696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0xd4757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x08898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x54959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0xa4050607 - .dd 0x08090A0B - .dd 0xfC0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x98191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x74252627 - .dd 0x28292A2B - .dd 0x8C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x98393A3B - .dd 0x3C3D3E3F - .dd 0xb0414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0xdC4D4E4F - .dd 0x50515253 - .dd 0x94555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0xf0616263 - .dd 0xf4656667 - .dd 0xf8696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x10919293 - .dd 0x24959697 - .dd 0x38999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0x54A5A6A7 - .dd 0x68A9AAAB - .dd 0x7CADAEAF - .dd 0xB0B1B2B3 - .dd 0x84B5B6B7 - .dd 0xB8B9BABB - .dd 0x4CBDBEBF - .dd 0xC0C1C2C3 - .dd 0x34C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0x20D1D2D3 - .dd 0xD4D5D6D7 - .dd 0x18D9DADB - .dd 0xDCDDDEDF - .dd 0x00E1E2E3 - .dd 0xE4E5E6E7 - .dd 0x18E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_ld_lohi.s b/sim/testsuite/sim/bfin/c_ldstpmod_ld_lohi.s deleted file mode 100644 index 4223e59..0000000 --- a/sim/testsuite/sim/bfin/c_ldstpmod_ld_lohi.s +++ /dev/null @@ -1,462 +0,0 @@ -//Original:testcases/core/c_ldstpmod_ld_lohi/c_ldstpmod_ld_lohi.dsp -// Spec Reference: c_ldstpmod load dreg lo & hi -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -INIT_R_REGS 0; -I0 = P3; -I2 = SP; - -// initial values - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - P4 = 0x0002; - FP = 0x0002; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_1, 0x00; - P3 = I1; SP = I3; - - R0.L = W [ P5 ++ P1 ]; - R1.L = W [ P5 ++ P1 ]; - R2.L = W [ P5 ++ P2 ]; - R3.L = W [ P5 ++ P3 ]; - R4.L = W [ P5 ++ P4 ]; - R5.L = W [ P5 ++ SP ]; - R6.L = W [ P5 ++ FP ]; - CHECKREG r0, 0x00000203; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00000607; - CHECKREG r3, 0x00000405; - CHECKREG r4, 0x00000A0B; - CHECKREG r5, 0x00000809; - CHECKREG r6, 0x00000E0F; - -// initial values - P5 = 0x0000; - P2 = 0x0002; - P3 = 0x0002; - P4 = 0x0002; - FP = 0x0002; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_2, 0x00; - P3 = I1; SP = I3; - - R0.H = W [ P1 ++ P5 ]; - R1.H = W [ P1 ++ P2 ]; - R2.H = W [ P1 ++ P2 ]; - R3.H = W [ P1 ++ P3 ]; - R4.H = W [ P1 ++ P4 ]; - R5.H = W [ P1 ++ SP ]; - R6.H = W [ P1 ++ FP ]; - CHECKREG r0, 0x22230203; - CHECKREG r1, 0x22230001; - CHECKREG r2, 0x20210607; - CHECKREG r3, 0x26270405; - CHECKREG r4, 0x24250A0B; - CHECKREG r5, 0x2A2B0809; - CHECKREG r6, 0x28290E0F; - -// initial values - P5 = 0x0002; - P1 = 0x0002; - P3 = 0x0002; - P4 = 0x0002; - FP = 0x0002; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p2, DATA_ADDR_2, 0x02; - P3 = I1; SP = I3; - - R0.L = W [ P2 ++ P5 ]; - R0.H = W [ P2 ++ P1 ]; - R1.L = W [ P2 ++ P1 ]; - R1.H = W [ P2 ++ P3 ]; - R2.H = W [ P2 ++ P4 ]; - R2.L = W [ P2 ++ SP ]; - R3.L = W [ P2 ++ FP ]; - CHECKREG r0, 0x26272021; - CHECKREG r1, 0x2A2B2425; - CHECKREG r2, 0x28292E2F; - CHECKREG r3, 0x26272C2D; - CHECKREG r4, 0x24250A0B; - CHECKREG r5, 0x2A2B0809; - CHECKREG r6, 0x28290E0F; - -// initial values - P5 = 0x0002; - P1 = 0x0002; - P2 = 0x0002; - P4 = 0x0002; - FP = 0x0002; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i1, DATA_ADDR_3, 0x00; - P3 = I1; SP = I3; - - R3.L = W [ P3 ++ P5 ]; - R3.H = W [ P3 ++ P1 ]; - R4.L = W [ P3 ++ P2 ]; - R5.H = W [ P3 ++ P1 ]; - R5.L = W [ P3 ++ P4 ]; - R6.H = W [ P3 ++ SP ]; - R6.L = W [ P3 ++ FP ]; - CHECKREG r0, 0x26272021; - CHECKREG r1, 0x2A2B2425; - CHECKREG r2, 0x28292E2F; - CHECKREG r3, 0x40414243; - CHECKREG r4, 0x24254647; - CHECKREG r5, 0x44454A4B; - CHECKREG r6, 0x48494E4F; - -// initial values - P5 = 0x0002; - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - FP = 0x0002; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p4, DATA_ADDR_4, 0x00; - P3 = I1; SP = I3; - - R0.H = W [ P4 ++ P5 ]; - R0.L = W [ P4 ++ P1 ]; - R1.L = W [ P4 ++ P2 ]; - R1.H = W [ P4 ++ P3 ]; - R2.H = W [ P4 ++ P4 ]; - R3.L = W [ P4 ++ SP ]; - R3.H = W [ P4 ++ FP ]; - CHECKREG r0, 0x62636061; - CHECKREG r1, 0x64656667; - CHECKREG r2, 0x6A6B2E2F; - CHECKREG r3, 0x68696A6B; - CHECKREG r4, 0x24254647; - CHECKREG r5, 0x44454A4B; - CHECKREG r6, 0x48494E4F; - -// initial values - P5 = 0x0002; - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - P4 = 0x0002; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_5, 0x00; - P3 = I1; SP = I3; - - R0.H = W [ FP ++ P5 ]; - R1.L = W [ FP ++ P1 ]; - R2.H = W [ FP ++ P2 ]; - R3.H = W [ FP ++ P3 ]; - R4.L = W [ FP ++ P4 ]; - R5.H = W [ FP ++ SP ]; - R6.L = W [ FP ++ P1 ]; - CHECKREG r0, 0x82836061; - CHECKREG r1, 0x64658081; - CHECKREG r2, 0x86872E2F; - CHECKREG r3, 0x84856A6B; - CHECKREG r4, 0x24258A8B; - CHECKREG r5, 0x88894A4B; - CHECKREG r6, 0x48498E8F; - -// initial values - P5 = 0x0000; - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - P4 = 0x0002; - FP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i3, DATA_ADDR_6, 0x00; - P3 = I1; SP = I3; - - R0.L = W [ SP ++ P5 ]; - R1.H = W [ SP ++ P1 ]; - R2.H = W [ SP ++ P2 ]; - R3.L = W [ SP ++ P3 ]; - R4.H = W [ SP ++ P4 ]; - R5.L = W [ SP ++ P5 ]; - R6.H = W [ SP ++ FP ]; - CHECKREG r0, 0x82830203; - CHECKREG r1, 0x02038081; - CHECKREG r2, 0x00012E2F; - CHECKREG r3, 0x84850607; - CHECKREG r4, 0x04058A8B; - CHECKREG r5, 0x88890A0B; - CHECKREG r6, 0x0A0B8E8F; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_hi.s b/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_hi.s deleted file mode 100644 index 4e19e60..0000000 --- a/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_hi.s +++ /dev/null @@ -1,400 +0,0 @@ -//Original:testcases/core/c_ldstpmod_st_dr_hi/c_ldstpmod_st_dr_hi.dsp -// Spec Reference: c_ldstpmod store dreg hi -# mach: bfin - -.include "testutils.inc" - start - -// set all regs - -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -I0 = P3; -I2 = SP; - -// initial values - imm32 r0, 0x600f5000; - imm32 r1, 0x700e6001; - imm32 r2, 0x800d7002; - imm32 r3, 0x900c8003; - imm32 r4, 0xa00b9004; - imm32 r5, 0xb00aa005; - imm32 r6, 0xc009b006; - imm32 r7, 0xd008c007; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0x02; - loadsym i1, DATA_ADDR_3, 0x04; - loadsym p4, DATA_ADDR_4, 0x06; - loadsym p5, DATA_ADDR_5, 0x08; - loadsym fp, DATA_ADDR_6, 0x0a; - loadsym i3, DATA_ADDR_7, 0x0c; - P3 = I1; SP = I3; - W [ P1 ] = R1.H; - W [ P2 ] = R2.H; - W [ P3 ] = R3.H; - W [ P4 ] = R4.H; - W [ P5 ] = R5.H; - W [ SP ] = R6.H; - W [ FP ] = R0.H; - R6.H = W [ P1 ]; - R5.H = W [ P2 ]; - R4.H = W [ P3 ]; - R3.H = W [ P4 ]; - R2.H = W [ P5 ]; - R0.H = W [ SP ]; - R1.H = W [ FP ]; - CHECKREG r0, 0xC0095000; - CHECKREG r1, 0x600F6001; - CHECKREG r2, 0xB00A7002; - CHECKREG r3, 0xA00B8003; - CHECKREG r4, 0x900C9004; - CHECKREG r5, 0x800DA005; - CHECKREG r6, 0x700EB006; - -// initial values - imm32 r0, 0x105f50a0; - imm32 r1, 0x204e60a1; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80a3; - imm32 r4, 0x501b90a4; - imm32 r5, 0x600aa0a5; - imm32 r6, 0x7019b0a6; - imm32 r7, 0xd028c0a7; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x0c; - loadsym p2, DATA_ADDR_2, 0x0a; - loadsym i1, DATA_ADDR_3, 0x08; - loadsym p4, DATA_ADDR_4, 0x06; - loadsym p5, DATA_ADDR_5, 0x04; - loadsym fp, DATA_ADDR_6, 0x02; - loadsym i3, DATA_ADDR_7, 0x00; - P3 = I1; SP = I3; - W [ P1 ] = R2.H; - W [ P2 ] = R3.H; - W [ P3 ] = R4.H; - W [ P4 ] = R5.H; - W [ P5 ] = R6.H; - W [ SP ] = R7.H; - W [ FP ] = R1.H; - R1.L = W [ P1 ]; - R2.L = W [ P2 ]; - R3.L = W [ P3 ]; - R4.L = W [ P4 ]; - R5.L = W [ P5 ]; - R6.L = W [ SP ]; - R0.L = W [ FP ]; - CHECKREG r0, 0x105F204E; - CHECKREG r1, 0x204E3003; - CHECKREG r2, 0x3003402C; - CHECKREG r3, 0x402C501B; - CHECKREG r4, 0x501B600A; - CHECKREG r5, 0x600A7019; - CHECKREG r6, 0x7019D028; - -// initial values - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x12345675; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x10; - loadsym p2, DATA_ADDR_2, 0x02; - loadsym i1, DATA_ADDR_3, 0x00; - loadsym p4, DATA_ADDR_4, 0x08; - loadsym p5, DATA_ADDR_5, 0x04; - loadsym fp, DATA_ADDR_6, 0x06; - loadsym i3, DATA_ADDR_7, 0x02; - P3 = I1; SP = I3; - W [ P1 ] = R5.H; - W [ P2 ] = R6.H; - W [ P3 ] = R7.H; - W [ P4 ] = R0.H; - W [ P5 ] = R1.H; - W [ SP ] = R2.H; - W [ FP ] = R3.H; - R5.H = W [ P1 ]; - R4.H = W [ P2 ]; - R3.H = W [ P3 ]; - R2.H = W [ P4 ]; - R1.H = W [ P5 ]; - R0.H = W [ SP ]; - R6.H = W [ FP ]; - CHECKREG r0, 0x30BD50B0; - CHECKREG r1, 0x20BE60B1; - CHECKREG r2, 0x10BF70B2; - CHECKREG r3, 0x80B880B3; - CHECKREG r4, 0x70B990B4; - CHECKREG r5, 0x12345675; - CHECKREG r6, 0x40BCB0B6; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_lo.s b/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_lo.s deleted file mode 100644 index b005545..0000000 --- a/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_lo.s +++ /dev/null @@ -1,401 +0,0 @@ -//Original:testcases/core/c_ldstpmod_st_dr_lo/c_ldstpmod_st_dr_lo.dsp -// Spec Reference: c_ldstpmod store dreg lo -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -I0 = P3; -I2 = SP; - -// initial values - imm32 r0, 0x600f5000; - imm32 r1, 0x700e6001; - imm32 r2, 0x800d7002; - imm32 r3, 0x900c8003; - imm32 r4, 0xa00b9004; - imm32 r5, 0xb00aa005; - imm32 r6, 0xc009b006; - imm32 r7, 0xd008c007; - - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - loadsym p2, DATA_ADDR_2, 0x02; - loadsym i1, DATA_ADDR_3, 0x04; - loadsym p4, DATA_ADDR_4, 0x06; - loadsym p5, DATA_ADDR_5, 0x08; - loadsym fp, DATA_ADDR_6, 0x0a; - loadsym i3, DATA_ADDR_7, 0x0c; - P3 = I1; SP = I3; - - W [ P1 ] = R1.L; - W [ P2 ] = R2.L; - W [ P3 ] = R3.L; - W [ P4 ] = R4.L; - W [ P5 ] = R5.L; - W [ SP ] = R6.L; - W [ FP ] = R0.L; - R6.L = W [ P1 ]; - R5.L = W [ P2 ]; - R4.L = W [ P3 ]; - R3.L = W [ P4 ]; - R2.L = W [ P5 ]; - R0.L = W [ SP ]; - R1.L = W [ FP ]; - CHECKREG r0, 0x600FB006; - CHECKREG r1, 0x700E5000; - CHECKREG r2, 0x800DA005; - CHECKREG r3, 0x900C9004; - CHECKREG r4, 0xA00B8003; - CHECKREG r5, 0xB00A7002; - CHECKREG r6, 0xC0096001; - -// initial values - imm32 r0, 0x105f50a0; - imm32 r1, 0x204e60a1; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80a3; - imm32 r4, 0x501b90a4; - imm32 r5, 0x600aa0a5; - imm32 r6, 0x7019b0a6; - imm32 r7, 0xd028c0a7; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x0c; - loadsym p2, DATA_ADDR_2, 0x0a; - loadsym i1, DATA_ADDR_3, 0x08; - loadsym p4, DATA_ADDR_4, 0x06; - loadsym p5, DATA_ADDR_5, 0x04; - loadsym fp, DATA_ADDR_6, 0x02; - loadsym i3, DATA_ADDR_7, 0x00; - P3 = I1; SP = I3; - W [ P1 ] = R2.L; - W [ P2 ] = R3.L; - W [ P3 ] = R4.L; - W [ P4 ] = R5.L; - W [ P5 ] = R6.L; - W [ SP ] = R7.L; - W [ FP ] = R1.L; - R1.L = W [ P1 ]; - R2.L = W [ P2 ]; - R3.L = W [ P3 ]; - R4.L = W [ P4 ]; - R5.L = W [ P5 ]; - R6.L = W [ SP ]; - R0.L = W [ FP ]; - CHECKREG r0, 0x105F60A1; - CHECKREG r1, 0x204E70A2; - CHECKREG r2, 0x300380A3; - CHECKREG r3, 0x402C90A4; - CHECKREG r4, 0x501BA0A5; - CHECKREG r5, 0x600AB0A6; - CHECKREG r6, 0x7019C0A7; - -// initial values - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x60baa0b5; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x10; - loadsym p2, DATA_ADDR_2, 0x02; - loadsym i1, DATA_ADDR_3, 0x00; - loadsym p4, DATA_ADDR_4, 0x08; - loadsym p5, DATA_ADDR_5, 0x04; - loadsym fp, DATA_ADDR_6, 0x06; - loadsym i3, DATA_ADDR_7, 0x02; - P3 = I1; SP = I3; - W [ P1 ] = R5.L; - W [ P2 ] = R6.L; - W [ P3 ] = R7.L; - W [ P4 ] = R0.L; - W [ P5 ] = R1.L; - W [ SP ] = R2.L; - W [ FP ] = R3.L; - R5.L = W [ P1 ]; - R4.L = W [ P2 ]; - R3.L = W [ P3 ]; - R2.L = W [ P4 ]; - R1.L = W [ P5 ]; - R0.L = W [ SP ]; - R6.L = W [ FP ]; - CHECKREG r0, 0x10BF70B2; - CHECKREG r1, 0x20BE60B1; - CHECKREG r2, 0x30BD50B0; - CHECKREG r3, 0x40BCC0B7; - CHECKREG r4, 0x55BBB0B6; - CHECKREG r5, 0x60BAA0B5; - CHECKREG r6, 0x70B980B3; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_st_dreg.s b/sim/testsuite/sim/bfin/c_ldstpmod_st_dreg.s deleted file mode 100644 index e1ec36f..0000000 --- a/sim/testsuite/sim/bfin/c_ldstpmod_st_dreg.s +++ /dev/null @@ -1,623 +0,0 @@ -//Original:testcases/core/c_ldstpmod_st_dreg/c_ldstpmod_st_dreg.dsp -// Spec Reference: c_ldstpmod store dreg -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -I0 = P3; -I2 = SP; - -// initial values - imm32 r0, 0x600f5000; - imm32 r1, 0x700e6001; - imm32 r2, 0x800d7002; - imm32 r3, 0x900c8003; - imm32 r4, 0xa00b9004; - imm32 r5, 0xb00aa005; - imm32 r6, 0xc009b006; - imm32 r7, 0xd008c007; - P1 = 0x0004; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0004; - SP = 0x0008; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_5, 0x00; - P3 = I1; SP = I3; - [ P5 ++ P1 ] = R0; - [ P5 ++ P1 ] = R1; - [ P5 ++ P2 ] = R2; - [ P5 ++ P3 ] = R3; - [ P5 ++ P4 ] = R4; - [ P5 ++ SP ] = R5; - [ P5 ++ FP ] = R6; - P1 = 0x0004; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0004; - SP = 0x0008; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_5, 0x00; - P3 = I1; SP = I3; - R6 = [ P5 ++ P1 ]; - R5 = [ P5 ++ P1 ]; - R4 = [ P5 ++ P2 ]; - R3 = [ P5 ++ P3 ]; - R2 = [ P5 ++ P4 ]; - R0 = [ P5 ++ SP ]; - R1 = [ P5 ++ FP ]; - CHECKREG r0, 0xB00AA005; - CHECKREG r1, 0xC009B006; - CHECKREG r2, 0xA00B9004; - CHECKREG r3, 0x900C8003; - CHECKREG r4, 0x800D7002; - CHECKREG r5, 0x700E6001; - CHECKREG r6, 0x600F5000; - -// initial values - imm32 r0, 0x105f50a0; - imm32 r1, 0x204e60a1; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80a3; - imm32 r4, 0x501b90a4; - imm32 r5, 0x600aa0a5; - imm32 r6, 0x7019b0a6; - imm32 r7, 0xd028c0a7; - P5 = 0x0004; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0008; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - P3 = I1; SP = I3; - [ P1 ++ P5 ] = R0; - [ P1 ++ P5 ] = R1; - [ P1 ++ P2 ] = R2; - [ P1 ++ P3 ] = R3; - [ P1 ++ P4 ] = R4; - [ P1 ++ SP ] = R5; - [ P1 ++ FP ] = R6; - P5 = 0x0004; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0008; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - P3 = I1; SP = I3; - R6 = [ P1 ++ P5 ]; - R5 = [ P1 ++ P5 ]; - R4 = [ P1 ++ P2 ]; - R3 = [ P1 ++ P3 ]; - R2 = [ P1 ++ P4 ]; - R0 = [ P1 ++ SP ]; - R1 = [ P1 ++ FP ]; - CHECKREG r0, 0x600AA0A5; - CHECKREG r1, 0x7019B0A6; - CHECKREG r2, 0x501B90A4; - CHECKREG r3, 0x402C80A3; - CHECKREG r4, 0x300370A2; - CHECKREG r5, 0x204E60A1; - CHECKREG r6, 0x105F50A0; - -// initial values - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x60baa0b5; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - P5 = 0x0004; - P1 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0004; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p2, DATA_ADDR_2, 0x00; - P3 = I1; SP = I3; - [ P2 ++ P5 ] = R0; - [ P2 ++ P1 ] = R1; - [ P2 ++ P1 ] = R2; - [ P2 ++ P3 ] = R3; - [ P2 ++ P4 ] = R4; - [ P2 ++ SP ] = R5; - [ P2 ++ FP ] = R6; - P5 = 0x0004; - P1 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0004; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p2, DATA_ADDR_2, 0x00; - P3 = I1; SP = I3; - R3 = [ P2 ++ P5 ]; - R4 = [ P2 ++ P1 ]; - R0 = [ P2 ++ P1 ]; - R1 = [ P2 ++ P3 ]; - R2 = [ P2 ++ P4 ]; - R5 = [ P2 ++ SP ]; - R6 = [ P2 ++ FP ]; - CHECKREG r0, 0x30BD70B2; - CHECKREG r1, 0x40BC80B3; - CHECKREG r2, 0x55BB90B4; - CHECKREG r3, 0x10BF50B0; - CHECKREG r4, 0x20BE60B1; - CHECKREG r5, 0x60BAA0B5; - CHECKREG r6, 0x70B9B0B6; - -// initial values - imm32 r0, 0x10cf50c0; - imm32 r1, 0x20ce60c1; - imm32 r2, 0x30c370c2; - imm32 r3, 0x40cc80c3; - imm32 r4, 0x50cb90c4; - imm32 r5, 0x60caa0c5; - imm32 r6, 0x70c9b0c6; - imm32 r7, 0xd0c8c0c7; - P5 = 0x0004; - P1 = 0x0004; - P2 = 0x0004; - P4 = 0x0004; - FP = 0x0004; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i1, DATA_ADDR_3, 0x00; - P3 = I1; SP = I3; - [ P3 ++ P5 ] = R0; - [ P3 ++ P1 ] = R1; - [ P3 ++ P2 ] = R2; - [ P3 ++ P1 ] = R3; - [ P3 ++ P4 ] = R4; - [ P3 ++ SP ] = R5; - [ P3 ++ FP ] = R6; - P5 = 0x0004; - P1 = 0x0004; - P2 = 0x0004; - P4 = 0x0004; - FP = 0x0004; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i1, DATA_ADDR_3, 0x00; - P3 = I1; SP = I3; - R6 = [ P3 ++ P5 ]; - R5 = [ P3 ++ P1 ]; - R4 = [ P3 ++ P2 ]; - R3 = [ P3 ++ P1 ]; - R2 = [ P3 ++ P4 ]; - R0 = [ P3 ++ SP ]; - R1 = [ P3 ++ FP ]; - CHECKREG r0, 0x60CAA0C5; - CHECKREG r1, 0x70C9B0C6; - CHECKREG r2, 0x50CB90C4; - CHECKREG r3, 0x40CC80C3; - CHECKREG r4, 0x30C370C2; - CHECKREG r5, 0x20CE60C1; - CHECKREG r6, 0x10CF50C0; - -// initial values - imm32 r0, 0x60df50d0; - imm32 r1, 0x70de60d1; - imm32 r2, 0x80dd70d2; - imm32 r3, 0x90dc80d3; - imm32 r4, 0xa0db90d4; - imm32 r5, 0xb0daa0d5; - imm32 r6, 0xc0d9b0d6; - imm32 r7, 0xd0d8c0d7; - P5 = 0x0004; - P1 = 0x0004; - P2 = 0x0004; - P3 = 0x0004; - FP = 0x0004; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p4, DATA_ADDR_4, 0x00; - P3 = I1; SP = I3; - [ P4 ++ P5 ] = R0; - [ P4 ++ P1 ] = R1; - [ P4 ++ P2 ] = R2; - [ P4 ++ P3 ] = R3; - [ P4 ++ P1 ] = R4; - [ P4 ++ SP ] = R5; - [ P4 ++ FP ] = R6; - P5 = 0x0004; - P1 = 0x0004; - P2 = 0x0004; - P3 = 0x0004; - FP = 0x0004; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p4, DATA_ADDR_4, 0x00; - P3 = I1; SP = I3; - R5 = [ P4 ++ P5 ]; - R6 = [ P4 ++ P1 ]; - R0 = [ P4 ++ P2 ]; - R1 = [ P4 ++ P3 ]; - R2 = [ P4 ++ P1 ]; - R3 = [ P4 ++ SP ]; - R4 = [ P4 ++ FP ]; - CHECKREG r0, 0x80DD70D2; - CHECKREG r1, 0x90DC80D3; - CHECKREG r2, 0xA0DB90D4; - CHECKREG r3, 0xB0DAA0D5; - CHECKREG r4, 0xC0D9B0D6; - CHECKREG r5, 0x60DF50D0; - CHECKREG r6, 0x70DE60D1; - -// initial values - imm32 r0, 0x1e5f50e0; - imm32 r1, 0x2e4e60e1; - imm32 r2, 0x3e0370e2; - imm32 r3, 0x4e2c80e3; - imm32 r4, 0x5e1b90e4; - imm32 r5, 0x6e0aa0e5; - imm32 r6, 0x7e19b0e6; - imm32 r7, 0xde28c0e7; - P5 = 0x0004; - P1 = 0x0004; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i3, DATA_ADDR_6, 0x00; - P3 = I1; SP = I3; - [ SP ++ P5 ] = R0; - [ SP ++ P1 ] = R1; - [ SP ++ P2 ] = R2; - [ SP ++ P3 ] = R3; - [ SP ++ P4 ] = R4; - [ SP ++ P1 ] = R5; - [ SP ++ FP ] = R6; - P5 = 0x0004; - P1 = 0x0004; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i3, DATA_ADDR_6, 0x00; - P3 = I1; SP = I3; - R6 = [ SP ++ P5 ]; - R5 = [ SP ++ P1 ]; - R4 = [ SP ++ P2 ]; - R3 = [ SP ++ P3 ]; - R2 = [ SP ++ P4 ]; - R0 = [ SP ++ P1 ]; - R1 = [ SP ++ FP ]; - CHECKREG r0, 0x6E0AA0E5; - CHECKREG r1, 0x7E19B0E6; - CHECKREG r2, 0x5E1B90E4; - CHECKREG r3, 0x4E2C80E3; - CHECKREG r4, 0x3E0370E2; - CHECKREG r5, 0x2E4E60E1; - CHECKREG r6, 0x1E5F50E0; - -// initial values - imm32 r0, 0x10ff50f0; - imm32 r1, 0x20fe60f1; - imm32 r2, 0x30fd70f2; - imm32 r3, 0x40fc80f3; - imm32 r4, 0x55fb90f4; - imm32 r5, 0x60faa0f5; - imm32 r6, 0x70f9b0f6; - imm32 r7, 0x80f8c0f7; - P5 = 0x0004; - P1 = 0x0004; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x1004 (X); - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_7, 0x00; - P3 = I1; SP = I3; - [ FP ++ P5 ] = R0; - [ FP ++ P1 ] = R1; - [ FP ++ P2 ] = R2; - [ FP ++ P3 ] = R3; - [ FP ++ P4 ] = R4; - [ FP ++ SP ] = R5; - [ FP ++ P1 ] = R6; - P5 = 0x0004; - P1 = 0x0004; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_7, 0x00; - P3 = I1; SP = I3; - R3 = [ FP ++ P5 ]; - R4 = [ FP ++ P1 ]; - R0 = [ FP ++ P2 ]; - R1 = [ FP ++ P3 ]; - R2 = [ FP ++ P4 ]; - R5 = [ FP ++ SP ]; - R6 = [ FP ++ P1 ]; - CHECKREG r0, 0x30FD70F2; - CHECKREG r1, 0x40FC80F3; - CHECKREG r2, 0x55FB90F4; - CHECKREG r3, 0x10FF50F0; - CHECKREG r4, 0x20FE60F1; - CHECKREG r5, 0x60FAA0F5; - CHECKREG r6, 0x70F9B0F6; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_st_lohi.s b/sim/testsuite/sim/bfin/c_ldstpmod_st_lohi.s deleted file mode 100644 index 58990ad..0000000 --- a/sim/testsuite/sim/bfin/c_ldstpmod_st_lohi.s +++ /dev/null @@ -1,625 +0,0 @@ -//Original:testcases/core/c_ldstpmod_st_lohi/c_ldstpmod_st_lohi.dsp -// Spec Reference: c_ldstpmod store dreg lo & hi -# mach: bfin - -.include "testutils.inc" - start - -// set all regs -init_i_regs 0; -init_b_regs 0; -init_l_regs 0; -init_m_regs 0; -I0 = P3; -I2 = SP; - -// initial values - imm32 r0, 0x600f5000; - imm32 r1, 0x700e6001; - imm32 r2, 0x800d7002; - imm32 r3, 0x900c8003; - imm32 r4, 0xa00b9004; - imm32 r5, 0xb00aa005; - imm32 r6, 0xc009b006; - imm32 r7, 0xd008c007; - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - P4 = 0x0002; - FP = 0x0002; - SP = 0x0006; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_5, 0x00; - P3 = I1; SP = I3; - - W [ P5 ++ P1 ] = R0.L; - W [ P5 ++ P1 ] = R1.L; - W [ P5 ++ P2 ] = R2.L; - W [ P5 ++ P3 ] = R3.L; - W [ P5 ++ P4 ] = R4.L; - W [ P5 ++ SP ] = R5.L; - W [ P5 ++ FP ] = R6.L; - - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - P4 = 0x0002; - FP = 0x0002; - SP = 0x0006; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p5, DATA_ADDR_5, 0x00; - P3 = I1; SP = I3; - - R6.L = W [ P5 ++ P1 ]; - R5.L = W [ P5 ++ P1 ]; - R4.L = W [ P5 ++ P2 ]; - R3.L = W [ P5 ++ P3 ]; - R2.L = W [ P5 ++ P4 ]; - R0.L = W [ P5 ++ SP ]; - R1.L = W [ P5 ++ FP ]; - CHECKREG r0, 0x600FA005; - CHECKREG r1, 0x700EB006; - CHECKREG r2, 0x800D9004; - CHECKREG r3, 0x900C8003; - CHECKREG r4, 0xA00B7002; - CHECKREG r5, 0xB00A6001; - CHECKREG r6, 0xC0095000; - -// initial values - imm32 r0, 0x105f50a0; - imm32 r1, 0x204e60a1; - imm32 r2, 0x300370a2; - imm32 r3, 0x402c80a3; - imm32 r4, 0x501b90a4; - imm32 r5, 0x204EA0A5; - imm32 r6, 0x7019b0a6; - imm32 r7, 0xd028c0a7; - P5 = 0x0002; - P2 = 0x0002; - P3 = 0x0004; - P4 = 0x0002; - FP = 0x0006; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - P3 = I1; SP = I3; - W [ P1 ++ P5 ] = R0.H; - W [ P1 ++ P2 ] = R1.H; - W [ P1 ++ P2 ] = R2.H; - W [ P1 ++ P3 ] = R3.H; - W [ P1 ++ P4 ] = R4.H; - W [ P1 ++ SP ] = R5.H; - W [ P1 ++ FP ] = R6.H; - P5 = 0x0002; - P2 = 0x0002; - P3 = 0x0004; - P4 = 0x0002; - FP = 0x0006; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p1, DATA_ADDR_1, 0x00; - P3 = I1; SP = I3; - R6.H = W [ P1 ++ P5 ]; - R5.H = W [ P1 ++ P2 ]; - R4.H = W [ P1 ++ P2 ]; - R3.H = W [ P1 ++ P3 ]; - R2.H = W [ P1 ++ P4 ]; - R0.H = W [ P1 ++ SP ]; - R1.H = W [ P1 ++ FP ]; - CHECKREG r0, 0x204E50A0; - CHECKREG r1, 0x701960A1; - CHECKREG r2, 0x501B70A2; - CHECKREG r3, 0x402C80A3; - CHECKREG r4, 0x300390A4; - CHECKREG r5, 0x204EA0A5; - CHECKREG r6, 0x105FB0A6; - -// initial values - imm32 r0, 0x10bf50b0; - imm32 r1, 0x20be60b1; - imm32 r2, 0x30bd70b2; - imm32 r3, 0x40bc80b3; - imm32 r4, 0x55bb90b4; - imm32 r5, 0x60baa0b5; - imm32 r6, 0x70b9b0b6; - imm32 r7, 0x80b8c0b7; - P5 = 0x0002; - P1 = 0x0002; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0006; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p2, DATA_ADDR_2, 0x02; - P3 = I1; SP = I3; - W [ P2 ++ P5 ] = R0.L; - W [ P2 ++ P1 ] = R0.H; - W [ P2 ++ P2 ] = R2.H; - W [ P2 ++ P3 ] = R2.H; - W [ P2 ++ P4 ] = R4.L; - W [ P2 ++ SP ] = R4.H; - W [ P2 ++ FP ] = R6.L; - P5 = 0x0002; - P1 = 0x0002; - P3 = 0x0002; - P4 = 0x0004; - FP = 0x0006; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p2, DATA_ADDR_2, 0x02; - P3 = I1; SP = I3; - R3.L = W [ P2 ++ P5 ]; - R3.H = W [ P2 ++ P1 ]; - R0.L = W [ P2 ++ P2 ]; - R0.H = W [ P2 ++ P3 ]; - R2.L = W [ P2 ++ P4 ]; - R2.H = W [ P2 ++ SP ]; - R6.L = W [ P2 ++ FP ]; - CHECKREG r0, 0x30BD30BD; - CHECKREG r1, 0x20BE60B1; - CHECKREG r2, 0x2E2F2A2B; - CHECKREG r3, 0x10BF50B0; - CHECKREG r4, 0x55BB90B4; - CHECKREG r5, 0x60BAA0B5; - CHECKREG r6, 0x70B955BB; - -// initial values - imm32 r0, 0x10cf50c0; - imm32 r1, 0x20ce60c1; - imm32 r2, 0x30c370c2; - imm32 r3, 0x40cc80c3; - imm32 r4, 0x50cb90c4; - imm32 r5, 0x60caa0c5; - imm32 r6, 0x70c9b0c6; - imm32 r7, 0xd0c8c0c7; - P5 = 0x0002; - P1 = 0x0002; - P2 = 0x0002; - P4 = 0x0004; - FP = 0x0006; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i1, DATA_ADDR_3, 0x02; - P3 = I1; SP = I3; - W [ P3 ++ P5 ] = R1.H; - W [ P3 ++ P1 ] = R1.L; - W [ P3 ++ P2 ] = R3.L; - W [ P3 ++ P2 ] = R3.H; - W [ P3 ++ P4 ] = R5.H; - W [ P3 ++ SP ] = R6.H; - W [ P3 ++ FP ] = R6.L; - P5 = 0x0002; - P1 = 0x0002; - P2 = 0x0002; - P4 = 0x0004; - FP = 0x0006; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i1, DATA_ADDR_3, 0x02; - P3 = I1; SP = I3; - R6.L = W [ P3 ++ P5 ]; - R6.H = W [ P3 ++ P1 ]; - R4.H = W [ P3 ++ P2 ]; - R4.L = W [ P3 ++ P2 ]; - R5.L = W [ P3 ++ P4 ]; - R5.H = W [ P3 ++ SP ]; - R1.L = W [ P3 ++ FP ]; - CHECKREG r0, 0x10CF50C0; - CHECKREG r1, 0x20CEB0C6; - CHECKREG r2, 0x30C370C2; - CHECKREG r3, 0x40CC80C3; - CHECKREG r4, 0x80C340CC; - CHECKREG r5, 0x70C960CA; - CHECKREG r6, 0x60C120CE; - -// initial values - imm32 r0, 0x60df50d0; - imm32 r1, 0x70de60d1; - imm32 r2, 0x80dd70d2; - imm32 r3, 0x90dc80d3; - imm32 r4, 0xa0db90d4; - imm32 r5, 0xb0daa0d5; - imm32 r6, 0xc0d9b0d6; - imm32 r7, 0xd0d8c0d7; - P5 = 0x0002; - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - FP = 0x0002; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p4, DATA_ADDR_4, 0x02; - P3 = I1; SP = I3; - W [ P4 ++ P5 ] = R0.L; - W [ P4 ++ P1 ] = R1.H; - W [ P4 ++ P2 ] = R2.L; - W [ P4 ++ P3 ] = R3.H; - W [ P4 ++ P3 ] = R4.H; - W [ P4 ++ SP ] = R5.L; - W [ P4 ++ FP ] = R6.H; - P5 = 0x0002; - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - FP = 0x0002; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym p4, DATA_ADDR_4, 0x02; - P3 = I1; SP = I3; - R5.L = W [ P4 ++ P5 ]; - R6.L = W [ P4 ++ P1 ]; - R0.H = W [ P4 ++ P2 ]; - R1.L = W [ P4 ++ P3 ]; - R2.L = W [ P4 ++ P3 ]; - R3.H = W [ P4 ++ SP ]; - R4.H = W [ P4 ++ FP ]; - CHECKREG r0, 0x70D250D0; - CHECKREG r1, 0x70DE90DC; - CHECKREG r2, 0x80DDA0DB; - CHECKREG r3, 0xA0D580D3; - CHECKREG r4, 0xC0D990D4; - CHECKREG r5, 0xB0DA50D0; - CHECKREG r6, 0xC0D970DE; - -// initial values - imm32 r0, 0x1e5f50e0; - imm32 r1, 0x2e4e60e1; - imm32 r2, 0x3e0370e2; - imm32 r3, 0x4e2c80e3; - imm32 r4, 0x5e1b90e4; - imm32 r5, 0x6e0aa0e5; - imm32 r6, 0x7e19b0e6; - imm32 r7, 0xde28c0e7; - P5 = 0x0002; - P1 = 0x0002; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0002; - FP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i3, DATA_ADDR_6, 0x02; - P3 = I1; SP = I3; - W [ SP ++ P5 ] = R0.H; - W [ SP ++ P1 ] = R1.H; - W [ SP ++ P2 ] = R2.L; - W [ SP ++ P3 ] = R3.L; - W [ SP ++ P4 ] = R4.H; - W [ SP ++ FP ] = R5.H; - W [ SP ++ FP ] = R6.L; - P5 = 0x0002; - P1 = 0x0002; - P2 = 0x0004; - P3 = 0x0004; - P4 = 0x0004; - FP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym i3, DATA_ADDR_6, 0x02; - P3 = I1; SP = I3; - R6.H = W [ SP ++ P5 ]; - R5.H = W [ SP ++ P1 ]; - R4.H = W [ SP ++ P2 ]; - R3.H = W [ SP ++ P3 ]; - R3.L = W [ SP ++ P4 ]; - R0.L = W [ SP ++ FP ]; - R1.L = W [ SP ++ FP ]; - CHECKREG r0, 0x1E5FB0E6; - CHECKREG r1, 0x2E4E1617; - CHECKREG r2, 0x3E0370E2; - CHECKREG r3, 0x80E35E1B; - CHECKREG r4, 0x70E290E4; - CHECKREG r5, 0x2E4EA0E5; - CHECKREG r6, 0x1E5FB0E6; - -// initial values - imm32 r0, 0x10ff50f0; - imm32 r1, 0x20fe60f1; - imm32 r2, 0x30fd70f2; - imm32 r3, 0x40fc80f3; - imm32 r4, 0x55fb90f4; - imm32 r5, 0x60faa0f5; - imm32 r6, 0x70f9b0f6; - imm32 r7, 0x80f8c0f7; - P5 = 0x0002; - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - P4 = 0x0004; - SP = 0x0002; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_7, 0x02; - P3 = I1; SP = I3; - W [ FP ++ P5 ] = R0.L; - W [ FP ++ P1 ] = R1.H; - W [ FP ++ P2 ] = R2.H; - W [ FP ++ P3 ] = R3.H; - W [ FP ++ P4 ] = R4.L; - W [ FP ++ SP ] = R5.L; - W [ FP ++ SP ] = R6.L; - P5 = 0x0002; - P1 = 0x0002; - P2 = 0x0002; - P3 = 0x0002; - P4 = 0x0004; - SP = 0x0004; - I1 = P3; P3 = I0; I3 = SP; SP = I2; - loadsym fp, DATA_ADDR_7, 0x02; - P3 = I1; SP = I3; - R3.L = W [ FP ++ P5 ]; - R4.L = W [ FP ++ P1 ]; - R0.H = W [ FP ++ P2 ]; - R1.H = W [ FP ++ P3 ]; - R2.L = W [ FP ++ P4 ]; - R5.H = W [ FP ++ SP ]; - R6.H = W [ FP ++ SP ]; - CHECKREG r0, 0x30FD50F0; - CHECKREG r1, 0x40FC60F1; - CHECKREG r2, 0x30FD90F4; - CHECKREG r3, 0x40FC50F0; - CHECKREG r4, 0x55FB20FE; - CHECKREG r5, 0xA0F5A0F5; - CHECKREG r6, 0x9091B0F6; - - P3 = I0; SP = I2; - pass - -// Pre-load memory with known data -// More data is defined than will actually be used - - .data -DATA_ADDR_1: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x11223344 - .dd 0x55667788 - .dd 0x99717273 - .dd 0x74757677 - .dd 0x82838485 - .dd 0x86878889 - .dd 0x80818283 - .dd 0x84858687 - .dd 0x01020304 - .dd 0x05060708 - .dd 0x09101112 - .dd 0x14151617 - .dd 0x18192021 - .dd 0x22232425 - .dd 0x26272829 - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38394041 - .dd 0x42434445 - .dd 0x46474849 - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58596061 - .dd 0x62636465 - .dd 0x66676869 - .dd 0x74555657 - .dd 0x78596067 - .dd 0x72636467 - .dd 0x76676867 - -DATA_ADDR_2: - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x91929394 - .dd 0x95969798 - .dd 0x99A1A2A3 - .dd 0xA5A6A7A8 - .dd 0xA9B0B1B2 - .dd 0xB3B4B5B6 - .dd 0xB7B8B9C0 - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78798081 - .dd 0x82838485 - .dd 0x86C283C4 - .dd 0x81C283C4 - .dd 0x82C283C4 - .dd 0x83C283C4 - .dd 0x84C283C4 - .dd 0x85C283C4 - .dd 0x86C283C4 - .dd 0x87C288C4 - .dd 0x88C283C4 - .dd 0x89C283C4 - .dd 0x80C283C4 - .dd 0x81C283C4 - .dd 0x82C288C4 - .dd 0x94555659 - .dd 0x98596069 - .dd 0x92636469 - .dd 0x96676869 - -DATA_ADDR_3: - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0xC5C6C7C8 - .dd 0xC9CACBCD - .dd 0xCFD0D1D2 - .dd 0xD3D4D5D6 - .dd 0xD7D8D9DA - .dd 0xDBDCDDDE - .dd 0xDFE0E1E2 - .dd 0xE3E4E5E6 - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x97E899EA - .dd 0x98E899EA - .dd 0x99E899EA - .dd 0x91E899EA - .dd 0x92E899EA - .dd 0x93E899EA - .dd 0x94E899EA - .dd 0x95E899EA - .dd 0x96E899EA - .dd 0x977899EA - .dd 0xa455565a - .dd 0xa859606a - .dd 0xa263646a - .dd 0xa667686a - -DATA_ADDR_4: - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - .dd 0xEBECEDEE - .dd 0xF3F4F5F6 - .dd 0xF7F8F9FA - .dd 0xFBFCFDFE - .dd 0xFF000102 - .dd 0x03040506 - .dd 0x0708090A - .dd 0x0B0CAD0E - .dd 0xAB0CAD01 - .dd 0xAB0CAD02 - .dd 0xAB0CAD03 - .dd 0xAB0CAD04 - .dd 0xAB0CAD05 - .dd 0xAB0CAD06 - .dd 0xAB0CAA07 - .dd 0xAB0CAD08 - .dd 0xAB0CAD09 - .dd 0xA00CAD1E - .dd 0xA10CAD2E - .dd 0xA20CAD3E - .dd 0xA30CAD4E - .dd 0xA40CAD5E - .dd 0xA50CAD6E - .dd 0xA60CAD7E - .dd 0xB455565B - .dd 0xB859606B - .dd 0xB263646B - .dd 0xB667686B - -DATA_ADDR_5: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0x0F101213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0xBC0DBE21 - .dd 0xBC1DBE22 - .dd 0xBC2DBE23 - .dd 0xBC3DBE24 - .dd 0xBC4DBE65 - .dd 0xBC5DBE27 - .dd 0xBC6DBE28 - .dd 0xBC7DBE29 - .dd 0xBC8DBE2F - .dd 0xBC9DBE20 - .dd 0xBCADBE21 - .dd 0xBCBDBE2F - .dd 0xBCCDBE23 - .dd 0xBCDDBE24 - .dd 0xBCFDBE25 - .dd 0xC455565C - .dd 0xC859606C - .dd 0xC263646C - .dd 0xC667686C - .dd 0xCC0DBE2C - -DATA_ADDR_6: - .dd 0x00010203 - .dd 0x04050607 - .dd 0x08090A0B - .dd 0x0C0D0E0F - .dd 0x10111213 - .dd 0x14151617 - .dd 0x18191A1B - .dd 0x1C1D1E1F - .dd 0x20212223 - .dd 0x24252627 - .dd 0x28292A2B - .dd 0x2C2D2E2F - .dd 0x30313233 - .dd 0x34353637 - .dd 0x38393A3B - .dd 0x3C3D3E3F - .dd 0x40414243 - .dd 0x44454647 - .dd 0x48494A4B - .dd 0x4C4D4E4F - .dd 0x50515253 - .dd 0x54555657 - .dd 0x58595A5B - .dd 0x5C5D5E5F - .dd 0x60616263 - .dd 0x64656667 - .dd 0x68696A6B - .dd 0x6C6D6E6F - .dd 0x70717273 - .dd 0x74757677 - .dd 0x78797A7B - .dd 0x7C7D7E7F - -DATA_ADDR_7: - .dd 0x80818283 - .dd 0x84858687 - .dd 0x88898A8B - .dd 0x8C8D8E8F - .dd 0x90919293 - .dd 0x94959697 - .dd 0x98999A9B - .dd 0x9C9D9E9F - .dd 0xA0A1A2A3 - .dd 0xA4A5A6A7 - .dd 0xA8A9AAAB - .dd 0xACADAEAF - .dd 0xB0B1B2B3 - .dd 0xB4B5B6B7 - .dd 0xB8B9BABB - .dd 0xBCBDBEBF - .dd 0xC0C1C2C3 - .dd 0xC4C5C6C7 - .dd 0xC8C9CACB - .dd 0xCCCDCECF - .dd 0xD0D1D2D3 - .dd 0xD4D5D6D7 - .dd 0xD8D9DADB - .dd 0xDCDDDEDF - .dd 0xE0E1E2E3 - .dd 0xE4E5E6E7 - .dd 0xE8E9EAEB - .dd 0xECEDEEEF - .dd 0xF0F1F2F3 - .dd 0xF4F5F6F7 - .dd 0xF8F9FAFB - .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_linkage.s b/sim/testsuite/sim/bfin/c_linkage.s deleted file mode 100644 index d7d673e..0000000 --- a/sim/testsuite/sim/bfin/c_linkage.s +++ /dev/null @@ -1,60 +0,0 @@ -//Original:testcases/core/c_linkage/c_linkage.dsp -// Spec Reference: linkage (link & unlnk) -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS(0); - - loadsym sp, DATA_ADDR_1, 0x24; - p0 = sp; - - FP = 0x0064 (X); - R0 = 5; - RETS = R0; - - LINK 4; // push rets, push fp, fp=sp, sp=sp-framesize (4) - - R1 = 3; - RETS = R1; // initialize rets by a different value - - loadsym p1, SUBR - CALL ( P1 ); - - SP = 0x3333 (X); - - UNLINK; // sp = fp, fp = pop (old fp), rets = pop(old rets), - - R2 = RETS; // for checking - - CHECKREG r0, 0x00000005; - CHECKREG r1, 0x00000003; - CHECKREG r2, 0x00000005; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00001111; - CHECKREG r7, 0x00000000; - CHECKREG fp, 0x00000064; - CC = SP == P0; - if CC JUMP 1f; - fail; -1: - pass - -SUBR: // should jump here - R6.L = 0x1111; - RTS; - R7.L = 0x2222; // should not go here - RTS; - - .data -DATA_ADDR_1: -DATA: - .space (0x0100); - -// Stack Segments - - .space (0x100); -KSTACK: diff --git a/sim/testsuite/sim/bfin/c_logi2op_alshft_mix.s b/sim/testsuite/sim/bfin/c_logi2op_alshft_mix.s deleted file mode 100644 index 7e42664..0000000 --- a/sim/testsuite/sim/bfin/c_logi2op_alshft_mix.s +++ /dev/null @@ -1,143 +0,0 @@ -//Original:/testcases/core/c_logi2op_alshft_mix/c_logi2op_alshft_mix.dsp -// Spec Reference: Logi2op >>>=, >>=, <<= -# mach: bfin - -.include "testutils.inc" - start - -// Arithmetic >>>= : positive data -imm32 r0, 0x40000000; -imm32 r1, 0x01111111; -imm32 r2, 0x22222222; -imm32 r3, 0x33333333; -imm32 r4, 0x44444444; -imm32 r5, 0x55555555; -imm32 r6, 0x66666666; -imm32 r7, 0x77777777; -R0 >>>= 1; /* r0 = 0x20000000 */ -R1 >>>= 1; /* r1 = 0x00888888 */ -R2 >>>= 2; /* r2 = 0x08888888 */ -R3 >>>= 8; /* r3 = 0x00333333 */ -R4 >>>= 1; /* r4 = 0x22222222 */ -R5 >>>= 27; /* r5 = 0x0000000a */ -R6 >>>= 30; /* r5 = 0x00000001 */ -R7 >>>= 31; /* r5 = 0x00000000 */ -CHECKREG r0, 0x20000000; -CHECKREG r1, 0x00888888; -CHECKREG r2, 0x08888888; -CHECKREG r3, 0x00333333; -CHECKREG r4, 0x22222222; -CHECKREG r5, 0x0000000a; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; - - - -// Arithmetic >>>= : negative data , -imm32 r0, 0x80000000; -imm32 r1, 0x81111111; -imm32 r2, 0xa2222222; -imm32 r3, 0xb3333333; -imm32 r4, 0xc4444444; -imm32 r5, 0xd5555555; -imm32 r6, 0xe6666666; -imm32 r7, 0xf7777777; -R0 >>>= 1; /* r0 = 0xc0000000 */ -R1 >>>= 1; /* r1 = 0xc0888888 */ -R2 >>>= 2; /* r2 = 0xe8888888 */ -R3 >>>= 8; /* r3 = 0x00333333 */ -R4 >>>= 1; /* r4 = 0x22222222 */ -R5 >>>= 27; /* r5 = 0x0000000a */ -R6 >>>= 30; /* r5 = 0x00000001 */ -R7 >>>= 31; /* r5 = 0x00000000 */ -CHECKREG r0, 0xc0000000; -CHECKREG r1, 0xc0888888; -CHECKREG r2, 0xe8888888; -CHECKREG r3, 0xffb33333; -CHECKREG r4, 0xe2222222; -CHECKREG r5, 0xfffffffa; -CHECKREG r6, 0xffffffff; -CHECKREG r7, 0xffffffff; - - -// Logical >>>= : positive data -imm32 r0, 0x40000000; -imm32 r1, 0x01111111; -imm32 r2, 0x22222222; -imm32 r3, 0x33333333; -imm32 r4, 0x44444444; -imm32 r5, 0x55555555; -imm32 r6, 0x66666666; -imm32 r7, 0x77777777; -R0 >>= 1; /* r0 = 0x20000000 */ -R1 >>= 1; /* r1 = 0x00888888 */ -R2 >>= 2; /* r2 = 0x08888888 */ -R3 >>= 8; /* r3 = 0x00333333 */ -R4 >>= 1; /* r4 = 0x22222222 */ -R5 >>= 27; /* r5 = 0x0000000a */ -R6 >>= 30; /* r5 = 0x00000001 */ -R7 >>= 31; /* r5 = 0x00000000 */ -CHECKREG r0, 0x20000000; -CHECKREG r1, 0x00888888; -CHECKREG r2, 0x08888888; -CHECKREG r3, 0x00333333; -CHECKREG r4, 0x22222222; -CHECKREG r5, 0x0000000a; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; - -// Logical >>= : negative data , -imm32 r0, 0x80000000; -imm32 r1, 0x81111111; -imm32 r2, 0xa2222222; -imm32 r3, 0xb3333333; -imm32 r4, 0xc4444444; -imm32 r5, 0xd5555555; -imm32 r6, 0xe6666666; -imm32 r7, 0xf7777777; -R0 >>= 1; /* r0 = 0x40000000 */ -R1 >>= 1; /* r1 = 0x40888888 */ -R2 >>= 2; /* r2 = 0x48888888 */ -R3 >>= 8; /* r3 = 0x40333333 */ -R4 >>= 1; /* r4 = 0xa2222222 */ -R5 >>= 27; /* r5 = 0x0000000a */ -R6 >>= 30; /* r5 = 0x00000001 */ -R7 >>= 31; /* r5 = 0x00000000 */ -CHECKREG r0, 0x40000000; -CHECKREG r1, 0x40888888; -CHECKREG r2, 0x28888888; -CHECKREG r3, 0x00b33333; -CHECKREG r4, 0x62222222; -CHECKREG r5, 0x0000001a; -CHECKREG r6, 0x00000003; -CHECKREG r7, 0x00000001; - - -// Logical <<= : negative data , -imm32 r0, 0x80000000; -imm32 r1, 0x81111111; -imm32 r2, 0xa2222222; -imm32 r3, 0xb3333333; -imm32 r4, 0xc4444444; -imm32 r5, 0xd5555555; -imm32 r6, 0xe6666666; -imm32 r7, 0xf7777777; -R0 <<= 1; /* r0 = 0x00000000 */ -R1 <<= 1; /* r1 = 0x40888888 */ -R2 <<= 2; /* r2 = 0x88888888 */ -R3 <<= 8; /* r3 = 0x33333300 */ -R4 <<= 1; /* r4 = 0x88888888 */ -R5 <<= 27; /* r5 = 0xa8000000 */ -R6 <<= 30; /* r5 = 0x80000000 */ -R7 <<= 31; /* r5 = 0x80000000 */ -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x02222222; -CHECKREG r2, 0x88888888; -CHECKREG r3, 0x33333300; -CHECKREG r4, 0x88888888; -CHECKREG r5, 0xa8000000; -CHECKREG r6, 0x80000000; -CHECKREG r7, 0x80000000; - // hlt; - -pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_arith_shft.s b/sim/testsuite/sim/bfin/c_logi2op_arith_shft.s deleted file mode 100644 index 110feee..0000000 --- a/sim/testsuite/sim/bfin/c_logi2op_arith_shft.s +++ /dev/null @@ -1,223 +0,0 @@ -//Original:/testcases/core/c_logi2op_arith_shft/c_logi2op_arith_shft.dsp -// Spec Reference: Logi2op >>>= -# mach: bfin - -.include "testutils.inc" - start - - - - - -// Arithmetic >>>= : negative data -// bit 0-7 -imm32 r0, 0x81111111; -imm32 r1, 0x81111111; -imm32 r2, 0x81111111; -imm32 r3, 0x81111111; -imm32 r4, 0x81111111; -imm32 r5, 0x81111111; -imm32 r6, 0x81111111; -imm32 r7, 0x81111111; -R0 >>>= 0; /* r0 = 0x81111111 */ -R1 >>>= 1; /* r1 = 0xC0888888 */ -R2 >>>= 2; /* r2 = 0xE0444444 */ -R3 >>>= 3; /* r3 = 0xF0222222 */ -R4 >>>= 4; /* r4 = 0xF8111111 */ -R5 >>>= 5; /* r5 = 0xFC088888 */ -R6 >>>= 6; /* r6 = 0xFE044444 */ -R7 >>>= 7; /* r7 = 0xFF022222 */ -CHECKREG r0, 0x81111111; -CHECKREG r1, 0xC0888888; -CHECKREG r2, 0xE0444444; -CHECKREG r3, 0xF0222222; -CHECKREG r4, 0xF8111111; -CHECKREG r5, 0xFC088888; -CHECKREG r6, 0xFE044444; -CHECKREG r7, 0xFF022222; - -// bit 8-15 -imm32 r0, 0x82222222; -imm32 r1, 0x82222222; -imm32 r2, 0x82222222; -imm32 r3, 0x82222222; -imm32 r4, 0x82222222; -imm32 r5, 0x82222222; -imm32 r6, 0x82222222; -imm32 r7, 0x82222222; -R0 >>>= 8; /* r0 = 0xFF822222 */ -R1 >>>= 9; /* r1 = 0xFFC11111 */ -R2 >>>= 10; /* r2 = 0xFFE08888 */ -R3 >>>= 11; /* r3 = 0xFFF04444 */ -R4 >>>= 12; /* r4 = 0xFFF82222 */ -R5 >>>= 13; /* r5 = 0xFFFC1111 */ -R6 >>>= 14; /* r6 = 0xFFFE0888 */ -R7 >>>= 15; /* r7 = 0xFFFF0444 */ -CHECKREG r0, 0xFF822222; -CHECKREG r1, 0xFFC11111; -CHECKREG r2, 0xFFE08888; -CHECKREG r3, 0xFFF04444; -CHECKREG r4, 0xFFF82222; -CHECKREG r5, 0xFFFC1111; -CHECKREG r6, 0xFFFE0888; -CHECKREG r7, 0xFFFF0444; - -// bit 16-23 -imm32 r0, 0x83333333; -imm32 r1, 0x83333333; -imm32 r2, 0x83333333; -imm32 r3, 0x83333333; -imm32 r4, 0x83333333; -imm32 r5, 0x83333333; -imm32 r6, 0x83333333; -imm32 r7, 0x83333333; -R0 >>>= 16; /* r0 = 0xFFFF8333 */ -R1 >>>= 17; /* r1 = 0xFFFFC199 */ -R2 >>>= 18; /* r2 = 0xFFFFE0CC */ -R3 >>>= 19; /* r3 = 0xFFFFF066 */ -R4 >>>= 20; /* r4 = 0xFFFFF833 */ -R5 >>>= 21; /* r5 = 0xFFFFFC19 */ -R6 >>>= 22; /* r6 = 0xFFFFFE0C */ -R7 >>>= 23; /* r7 = 0xFFFFFF06 */ -CHECKREG r0, 0xFFFF8333; -CHECKREG r1, 0xFFFFC199; -CHECKREG r2, 0xFFFFE0CC; -CHECKREG r3, 0xFFFFF066; -CHECKREG r4, 0xFFFFF833; -CHECKREG r5, 0xFFFFFC19; -CHECKREG r6, 0xFFFFFE0C; -CHECKREG r7, 0xFFFFFF06; - -// bit 24-31 -imm32 r0, 0x84444444; -imm32 r1, 0x84444444; -imm32 r2, 0x84444444; -imm32 r3, 0x84444444; -imm32 r4, 0x84444444; -imm32 r5, 0x84444444; -imm32 r6, 0x84444444; -imm32 r7, 0x84444444; -R0 >>>= 24; /* r0 = 0xFFFFFF84 */ -R1 >>>= 25; /* r1 = 0xFFFFFFC2 */ -R2 >>>= 26; /* r2 = 0xFFFFFFE1 */ -R3 >>>= 27; /* r3 = 0xFFFFFFF0 */ -R4 >>>= 28; /* r4 = 0xFFFFFFF8 */ -R5 >>>= 29; /* r5 = 0xFFFFFFFC */ -R6 >>>= 30; /* r6 = 0xFFFFFFFE */ -R7 >>>= 31; /* r7 = 0xFFFFFFFF */ -CHECKREG r0, 0xFFFFFF84; -CHECKREG r1, 0xFFFFFFC2; -CHECKREG r2, 0xFFFFFFE1; -CHECKREG r3, 0xFFFFFFF0; -CHECKREG r4, 0xFFFFFFF8; -CHECKREG r5, 0xFFFFFFFC; -CHECKREG r6, 0xFFFFFFFE; -CHECKREG r7, 0xFFFFFFFF; - -// Arithmetic >>>= : positive data -// bit 0-7 -imm32 r0, 0x41111111; -imm32 r1, 0x41111111; -imm32 r2, 0x41111111; -imm32 r3, 0x41111111; -imm32 r4, 0x41111111; -imm32 r5, 0x41111111; -imm32 r6, 0x41111111; -imm32 r7, 0x41111111; -R0 >>>= 0; /* r0 = 0x41111111 */ -R1 >>>= 1; /* r1 = 0x20888888 */ -R2 >>>= 2; /* r2 = 0x10444444 */ -R3 >>>= 3; /* r3 = 0x08222222 */ -R4 >>>= 4; /* r4 = 0x04111111 */ -R5 >>>= 5; /* r5 = 0x02088888 */ -R6 >>>= 6; /* r6 = 0x01044444 */ -R7 >>>= 7; /* r7 = 0x00822222 */ -CHECKREG r0, 0x41111111; -CHECKREG r1, 0x20888888; -CHECKREG r2, 0x10444444; -CHECKREG r3, 0x08222222; -CHECKREG r4, 0x04111111; -CHECKREG r5, 0x02088888; -CHECKREG r6, 0x01044444; -CHECKREG r7, 0x00822222; - -// bit 8-15 -imm32 r0, 0x42222222; -imm32 r1, 0x42222222; -imm32 r2, 0x42222222; -imm32 r3, 0x42222222; -imm32 r4, 0x42222222; -imm32 r5, 0x42222222; -imm32 r6, 0x42222222; -imm32 r7, 0x42222222; -R0 >>>= 8; /* r0 = 0x00422222 */ -R1 >>>= 9; /* r1 = 0x00211111 */ -R2 >>>= 10; /* r2 = 0x00108888 */ -R3 >>>= 11; /* r3 = 0x00084444 */ -R4 >>>= 12; /* r4 = 0x00042222 */ -R5 >>>= 13; /* r5 = 0x00021111 */ -R6 >>>= 14; /* r6 = 0x00010888 */ -R7 >>>= 15; /* r7 = 0x00008444 */ -CHECKREG r0, 0x00422222; -CHECKREG r1, 0x00211111; -CHECKREG r2, 0x00108888; -CHECKREG r3, 0x00084444; -CHECKREG r4, 0x00042222; -CHECKREG r5, 0x00021111; -CHECKREG r6, 0x00010888; -CHECKREG r7, 0x00008444; - -// bit 16-23 -imm32 r0, 0x43333333; -imm32 r1, 0x43333333; -imm32 r2, 0x43333333; -imm32 r3, 0x43333333; -imm32 r4, 0x43333333; -imm32 r5, 0x43333333; -imm32 r6, 0x43333333; -imm32 r7, 0x43333333; -R0 >>>= 16; /* r0 = 0x00004333 */ -R1 >>>= 17; /* r1 = 0x00002199 */ -R2 >>>= 18; /* r2 = 0x000010CC */ -R3 >>>= 19; /* r3 = 0x00000866 */ -R4 >>>= 20; /* r4 = 0x00000433 */ -R5 >>>= 21; /* r5 = 0x00000219 */ -R6 >>>= 22; /* r6 = 0x0000010C */ -R7 >>>= 23; /* r7 = 0x00000086 */ -CHECKREG r0, 0x00004333; -CHECKREG r1, 0x00002199; -CHECKREG r2, 0x000010CC; -CHECKREG r3, 0x00000866; -CHECKREG r4, 0x00000433; -CHECKREG r5, 0x00000219; -CHECKREG r6, 0x0000010C; -CHECKREG r7, 0x00000086; - -// bit 24-31 -imm32 r0, 0x44444444; -imm32 r1, 0x44444444; -imm32 r2, 0x44444444; -imm32 r3, 0x44444444; -imm32 r4, 0x44444444; -imm32 r5, 0x44444444; -imm32 r6, 0x44444444; -imm32 r7, 0x44444444; -R0 >>>= 24; /* r0 = 0x00000044 */ -R1 >>>= 25; /* r1 = 0x00000022 */ -R2 >>>= 26; /* r2 = 0x00000011 */ -R3 >>>= 27; /* r3 = 0x00000008 */ -R4 >>>= 28; /* r4 = 0x00000004 */ -R5 >>>= 29; /* r5 = 0x00000002 */ -R6 >>>= 30; /* r6 = 0x00000001 */ -R7 >>>= 31; /* r7 = 0x00000000 */ -CHECKREG r0, 0x00000044; -CHECKREG r1, 0x00000022; -CHECKREG r2, 0x00000011; -CHECKREG r3, 0x00000008; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; - - -pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_bitclr.s b/sim/testsuite/sim/bfin/c_logi2op_bitclr.s deleted file mode 100644 index b5ca481..0000000 --- a/sim/testsuite/sim/bfin/c_logi2op_bitclr.s +++ /dev/null @@ -1,92 +0,0 @@ -//Original:/testcases/core/c_logi2op_bitclr/c_logi2op_bitclr.dsp -// Spec Reference: Logi2op functions: bitclr -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0xffffffff; -imm32 r1, 0xffffffff; -imm32 r2, 0xffffffff; -imm32 r3, 0xffffffff; -imm32 r4, 0xffffffff; -imm32 r5, 0xffffffff; -imm32 r6, 0xffffffff; -imm32 r7, 0xffffffff; - -// bit clr -BITCLR( R0 , 0 ); /* r0 = 0x00000001 */ -BITCLR( R1 , 1 ); /* r1 = 0x00000002 */ -BITCLR( R2 , 2 ); /* r2 = 0x00000004 */ -BITCLR( R3 , 3 ); /* r3 = 0x00000008 */ -BITCLR( R4 , 4 ); /* r4 = 0x00000010 */ -BITCLR( R5 , 5 ); /* r5 = 0x00000020 */ -BITCLR( R6 , 6 ); /* r6 = 0x00000040 */ -BITCLR( R7 , 7 ); /* r7 = 0x00000080 */ -CHECKREG r0, 0xfffffffe; -CHECKREG r1, 0xfffffffd; -CHECKREG r2, 0xfffffffb; -CHECKREG r3, 0xfffffff7; -CHECKREG r4, 0xffffffef; -CHECKREG r5, 0xffffffdf; -CHECKREG r6, 0xffffffbf; -CHECKREG r7, 0xffffff7f; - -// bit clr -BITCLR( R0 , 8 ); /* r0 = 0x00000100 */ -BITCLR( R1 , 9 ); /* r1 = 0x00000200 */ -BITCLR( R2 , 10 ); /* r2 = 0x00000400 */ -BITCLR( R3 , 11 ); /* r3 = 0x00000800 */ -BITCLR( R4 , 12 ); /* r4 = 0x00001000 */ -BITCLR( R5 , 13 ); /* r5 = 0x00002000 */ -BITCLR( R6 , 14 ); /* r6 = 0x00004000 */ -BITCLR( R7 , 15 ); /* r7 = 0x00008000 */ -CHECKREG r0, 0xfffffefe; -CHECKREG r1, 0xfffffdfd; -CHECKREG r2, 0xfffffbfb; -CHECKREG r3, 0xfffff7f7; -CHECKREG r4, 0xffffefef; -CHECKREG r5, 0xffffdfdf; -CHECKREG r6, 0xffffbfbf; -CHECKREG r7, 0xffff7f7f; - -// bit clr -BITCLR( R0 , 16 ); /* r0 = 0x00000100 */ -BITCLR( R1 , 17 ); /* r1 = 0x00000200 */ -BITCLR( R2 , 18 ); /* r2 = 0x00000400 */ -BITCLR( R3 , 19 ); /* r3 = 0x00000800 */ -BITCLR( R4 , 20 ); /* r4 = 0x00001000 */ -BITCLR( R5 , 21 ); /* r5 = 0x00002000 */ -BITCLR( R6 , 22 ); /* r6 = 0x00004000 */ -BITCLR( R7 , 23 ); /* r7 = 0x00008000 */ -CHECKREG r0, 0xfffefefe; -CHECKREG r1, 0xfffdfdfd; -CHECKREG r2, 0xfffbfbfb; -CHECKREG r3, 0xfff7f7f7; -CHECKREG r4, 0xffefefef; -CHECKREG r5, 0xffdfdfdf; -CHECKREG r6, 0xffbfbfbf; -CHECKREG r7, 0xff7f7f7f; - -// bit clr -BITCLR( R0 , 24 ); /* r0 = 0x00000100 */ -BITCLR( R1 , 25 ); /* r1 = 0x00000200 */ -BITCLR( R2 , 26 ); /* r2 = 0x00000400 */ -BITCLR( R3 , 27 ); /* r3 = 0x00000800 */ -BITCLR( R4 , 28 ); /* r4 = 0x00001000 */ -BITCLR( R5 , 29 ); /* r5 = 0x00002000 */ -BITCLR( R6 , 30 ); /* r6 = 0x00004000 */ -BITCLR( R7 , 31 ); /* r7 = 0x00008000 */ -CHECKREG r0, 0xfefefefe; -CHECKREG r1, 0xfdfdfdfd; -CHECKREG r2, 0xfbfbfbfb; -CHECKREG r3, 0xf7f7f7f7; -CHECKREG r4, 0xefefefef; -CHECKREG r5, 0xdfdfdfdf; -CHECKREG r6, 0xbfbfbfbf; -CHECKREG r7, 0x7f7f7f7f; - - -pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_bitset.s b/sim/testsuite/sim/bfin/c_logi2op_bitset.s deleted file mode 100644 index ce86d67..0000000 --- a/sim/testsuite/sim/bfin/c_logi2op_bitset.s +++ /dev/null @@ -1,92 +0,0 @@ -//Original:/testcases/core/c_logi2op_bitset/c_logi2op_bitset.dsp -// Spec Reference: Logi2op -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -// bit set -BITSET( R0 , 0 ); /* r0 = 0x00000001 */ -BITSET( R1 , 1 ); /* r1 = 0x00000002 */ -BITSET( R2 , 2 ); /* r2 = 0x00000004 */ -BITSET( R3 , 3 ); /* r3 = 0x00000008 */ -BITSET( R4 , 4 ); /* r4 = 0x00000010 */ -BITSET( R5 , 5 ); /* r5 = 0x00000020 */ -BITSET( R6 , 6 ); /* r6 = 0x00000040 */ -BITSET( R7 , 7 ); /* r7 = 0x00000080 */ -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000002; -CHECKREG r2, 0x00000004; -CHECKREG r3, 0x00000008; -CHECKREG r4, 0x00000010; -CHECKREG r5, 0x00000020; -CHECKREG r6, 0x00000040; -CHECKREG r7, 0x00000080; - -// bit set -BITSET( R0 , 8 ); /* r0 = 0x00000100 */ -BITSET( R1 , 9 ); /* r1 = 0x00000200 */ -BITSET( R2 , 10 ); /* r2 = 0x00000400 */ -BITSET( R3 , 11 ); /* r3 = 0x00000800 */ -BITSET( R4 , 12 ); /* r4 = 0x00001000 */ -BITSET( R5 , 13 ); /* r5 = 0x00002000 */ -BITSET( R6 , 14 ); /* r6 = 0x00004000 */ -BITSET( R7 , 15 ); /* r7 = 0x00008000 */ -CHECKREG r0, 0x00000101; -CHECKREG r1, 0x00000202; -CHECKREG r2, 0x00000404; -CHECKREG r3, 0x00000808; -CHECKREG r4, 0x00001010; -CHECKREG r5, 0x00002020; -CHECKREG r6, 0x00004040; -CHECKREG r7, 0x00008080; - -// bit set -BITSET( R0 , 16 ); /* r0 = 0x00000100 */ -BITSET( R1 , 17 ); /* r1 = 0x00000200 */ -BITSET( R2 , 18 ); /* r2 = 0x00000400 */ -BITSET( R3 , 19 ); /* r3 = 0x00000800 */ -BITSET( R4 , 20 ); /* r4 = 0x00001000 */ -BITSET( R5 , 21 ); /* r5 = 0x00002000 */ -BITSET( R6 , 22 ); /* r6 = 0x00004000 */ -BITSET( R7 , 23 ); /* r7 = 0x00008000 */ -CHECKREG r0, 0x00010101; -CHECKREG r1, 0x00020202; -CHECKREG r2, 0x00040404; -CHECKREG r3, 0x00080808; -CHECKREG r4, 0x00101010; -CHECKREG r5, 0x00202020; -CHECKREG r6, 0x00404040; -CHECKREG r7, 0x00808080; - -// bit set -BITSET( R0 , 24 ); /* r0 = 0x00000100 */ -BITSET( R1 , 25 ); /* r1 = 0x00000200 */ -BITSET( R2 , 26 ); /* r2 = 0x00000400 */ -BITSET( R3 , 27 ); /* r3 = 0x00000800 */ -BITSET( R4 , 28 ); /* r4 = 0x00001000 */ -BITSET( R5 , 29 ); /* r5 = 0x00002000 */ -BITSET( R6 , 30 ); /* r6 = 0x00004000 */ -BITSET( R7 , 31 ); /* r7 = 0x00008000 */ -CHECKREG r0, 0x01010101; -CHECKREG r1, 0x02020202; -CHECKREG r2, 0x04040404; -CHECKREG r3, 0x08080808; -CHECKREG r4, 0x10101010; -CHECKREG r5, 0x20202020; -CHECKREG r6, 0x40404040; -CHECKREG r7, 0x80808080; - - -pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_bittgl.s b/sim/testsuite/sim/bfin/c_logi2op_bittgl.s deleted file mode 100644 index ca9fe41..0000000 --- a/sim/testsuite/sim/bfin/c_logi2op_bittgl.s +++ /dev/null @@ -1,165 +0,0 @@ -//Original:/testcases/core/c_logi2op_bittgl/c_logi2op_bittgl.dsp -// Spec Reference: Logi2op functions: bittgl -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -// bit 0-7 -BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ -BITTGL( R1 , 1 ); /* r1 = 0x00000002 */ -BITTGL( R2 , 2 ); /* r2 = 0x00000004 */ -BITTGL( R3 , 3 ); /* r3 = 0x00000008 */ -BITTGL( R4 , 4 ); /* r4 = 0x00000010 */ -BITTGL( R5 , 5 ); /* r5 = 0x00000020 */ -BITTGL( R6 , 6 ); /* r6 = 0x00000040 */ -BITTGL( R7 , 7 ); /* r7 = 0x00000080 */ -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000002; -CHECKREG r2, 0x00000004; -CHECKREG r3, 0x00000008; -CHECKREG r4, 0x00000010; -CHECKREG r5, 0x00000020; -CHECKREG r6, 0x00000040; -CHECKREG r7, 0x00000080; - -// bit 8-15 -BITTGL( R0 , 8 ); /* r0 = 0x00000100 */ -BITTGL( R1 , 9 ); /* r1 = 0x00000200 */ -BITTGL( R2 , 10 ); /* r2 = 0x00000400 */ -BITTGL( R3 , 11 ); /* r3 = 0x00000800 */ -BITTGL( R4 , 12 ); /* r4 = 0x00001000 */ -BITTGL( R5 , 13 ); /* r5 = 0x00002000 */ -BITTGL( R6 , 14 ); /* r6 = 0x00004000 */ -BITTGL( R7 , 15 ); /* r7 = 0x00008000 */ -CHECKREG r0, 0x00000101; -CHECKREG r1, 0x00000202; -CHECKREG r2, 0x00000404; -CHECKREG r3, 0x00000808; -CHECKREG r4, 0x00001010; -CHECKREG r5, 0x00002020; -CHECKREG r6, 0x00004040; -CHECKREG r7, 0x00008080; - -// bit 16-23 -BITTGL( R0 , 16 ); /* r0 = 0x00000100 */ -BITTGL( R1 , 17 ); /* r1 = 0x00000200 */ -BITTGL( R2 , 18 ); /* r2 = 0x00000400 */ -BITTGL( R3 , 19 ); /* r3 = 0x00000800 */ -BITTGL( R4 , 20 ); /* r4 = 0x00001000 */ -BITTGL( R5 , 21 ); /* r5 = 0x00002000 */ -BITTGL( R6 , 22 ); /* r6 = 0x00004000 */ -BITTGL( R7 , 23 ); /* r7 = 0x00008000 */ -CHECKREG r0, 0x00010101; -CHECKREG r1, 0x00020202; -CHECKREG r2, 0x00040404; -CHECKREG r3, 0x00080808; -CHECKREG r4, 0x00101010; -CHECKREG r5, 0x00202020; -CHECKREG r6, 0x00404040; -CHECKREG r7, 0x00808080; - -// bit 24-31 -BITTGL( R0 , 24 ); /* r0 = 0x00000100 */ -BITTGL( R1 , 25 ); /* r1 = 0x00000200 */ -BITTGL( R2 , 26 ); /* r2 = 0x00000400 */ -BITTGL( R3 , 27 ); /* r3 = 0x00000800 */ -BITTGL( R4 , 28 ); /* r4 = 0x00001000 */ -BITTGL( R5 , 29 ); /* r5 = 0x00002000 */ -BITTGL( R6 , 30 ); /* r6 = 0x00004000 */ -BITTGL( R7 , 31 ); /* r7 = 0x00008000 */ -CHECKREG r0, 0x01010101; -CHECKREG r1, 0x02020202; -CHECKREG r2, 0x04040404; -CHECKREG r3, 0x08080808; -CHECKREG r4, 0x10101010; -CHECKREG r5, 0x20202020; -CHECKREG r6, 0x40404040; -CHECKREG r7, 0x80808080; - -// bit 0-7 -BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ -BITTGL( R1 , 1 ); /* r1 = 0x00000002 */ -BITTGL( R2 , 2 ); /* r2 = 0x00000004 */ -BITTGL( R3 , 3 ); /* r3 = 0x00000008 */ -BITTGL( R4 , 4 ); /* r4 = 0x00000010 */ -BITTGL( R5 , 5 ); /* r5 = 0x00000020 */ -BITTGL( R6 , 6 ); /* r6 = 0x00000040 */ -BITTGL( R7 , 7 ); /* r7 = 0x00000080 */ -CHECKREG r0, 0x01010100; -CHECKREG r1, 0x02020200; -CHECKREG r2, 0x04040400; -CHECKREG r3, 0x08080800; -CHECKREG r4, 0x10101000; -CHECKREG r5, 0x20202000; -CHECKREG r6, 0x40404000; -CHECKREG r7, 0x80808000; - -// bit 8-15 -BITTGL( R0 , 8 ); /* r0 = 0x00000100 */ -BITTGL( R1 , 9 ); /* r1 = 0x00000200 */ -BITTGL( R2 , 10 ); /* r2 = 0x00000400 */ -BITTGL( R3 , 11 ); /* r3 = 0x00000800 */ -BITTGL( R4 , 12 ); /* r4 = 0x00001000 */ -BITTGL( R5 , 13 ); /* r5 = 0x00002000 */ -BITTGL( R6 , 14 ); /* r6 = 0x00004000 */ -BITTGL( R7 , 15 ); /* r7 = 0x00008000 */ -CHECKREG r0, 0x01010000; -CHECKREG r1, 0x02020000; -CHECKREG r2, 0x04040000; -CHECKREG r3, 0x08080000; -CHECKREG r4, 0x10100000; -CHECKREG r5, 0x20200000; -CHECKREG r6, 0x40400000; -CHECKREG r7, 0x80800000; - -// bit 16-23 -BITTGL( R0 , 16 ); /* r0 = 0x00000100 */ -BITTGL( R1 , 17 ); /* r1 = 0x00000200 */ -BITTGL( R2 , 18 ); /* r2 = 0x00000400 */ -BITTGL( R3 , 19 ); /* r3 = 0x00000800 */ -BITTGL( R4 , 20 ); /* r4 = 0x00001000 */ -BITTGL( R5 , 21 ); /* r5 = 0x00002000 */ -BITTGL( R6 , 22 ); /* r6 = 0x00004000 */ -BITTGL( R7 , 23 ); /* r7 = 0x00008000 */ -CHECKREG r0, 0x01000000; -CHECKREG r1, 0x02000000; -CHECKREG r2, 0x04000000; -CHECKREG r3, 0x08000000; -CHECKREG r4, 0x10000000; -CHECKREG r5, 0x20000000; -CHECKREG r6, 0x40000000; -CHECKREG r7, 0x80000000; - -// bit 24-31 -BITTGL( R0 , 24 ); /* r0 = 0x00000100 */ -BITTGL( R1 , 25 ); /* r1 = 0x00000200 */ -BITTGL( R2 , 26 ); /* r2 = 0x00000400 */ -BITTGL( R3 , 27 ); /* r3 = 0x00000800 */ -BITTGL( R4 , 28 ); /* r4 = 0x00001000 */ -BITTGL( R5 , 29 ); /* r5 = 0x00002000 */ -BITTGL( R6 , 30 ); /* r6 = 0x00004000 */ -BITTGL( R7 , 31 ); /* r7 = 0x00008000 */ -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - - - -pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_bittst.s b/sim/testsuite/sim/bfin/c_logi2op_bittst.s deleted file mode 100644 index cce9df5..0000000 --- a/sim/testsuite/sim/bfin/c_logi2op_bittst.s +++ /dev/null @@ -1,583 +0,0 @@ -//Original:/testcases/core/c_logi2op_bittst/c_logi2op_bittst.dsp -// Spec Reference: Logi2op functions: bittst -# mach: bfin - -.include "testutils.inc" - start - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -// bit(0-7) tst set clr toggle -CC = BITTST ( R0 , 0 ); /* cc = 0 */ -BITSET( R0 , 0 ); /* r0 = 0x00000001 */ -R1 = CC; -CC = BITTST ( R0 , 0 ); /* cc = 1 */ -R2 = CC; -BITCLR( R0 , 0 ); /* r0 = 0x00000000 */ -CC = BITTST ( R0 , 0 ); /* cc = 1 */ -R3 = CC; -BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ -CC = BITTST ( R0 , 0 ); /* cc = 1 */ -R4 = CC; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000001; - -CC = BITTST ( R1 , 1 ); /* cc = 0 */ -R2 = CC; -BITSET( R1 , 1 ); /* r1 = 0x00000002 */ -CC = BITTST ( R1 , 1 ); /* cc = 1 */ -R3 = CC; -BITCLR( R1 , 1 ); /* r1 = 0x00000000 */ -CC = BITTST ( R1 , 1 ); /* cc = 1 */ -R4 = CC; -BITTGL( R1 , 1 ); /* r1 = 0x00000002 */ -CC = BITTST ( R1 , 1 ); /* cc = 1 */ -R5 = CC; -CHECKREG r1, 0x00000002; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; - -CC = BITTST ( R2 , 2 ); /* cc = 0 */ -R3 = CC; -BITSET( R2 , 2 ); /* r2 = 0x00000004 */ -CC = BITTST ( R2 , 2 ); /* cc = 1 */ -R4 = CC; -BITCLR( R2 , 2 ); /* r2 = 0x00000000 */ -CC = BITTST ( R2 , 2 ); /* cc = 1 */ -R5 = CC; -BITTGL( R2 , 2 ); /* r2 = 0x00000004 */ -CC = BITTST ( R2 , 2 ); /* cc = 1 */ -R6 = CC; -CHECKREG r2, 0x00000004; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000001; - -CC = BITTST ( R3 , 3 ); /* cc = 0 */ -R4 = CC; -BITSET( R3 , 3 ); /* r3 = 0x00000008 */ -CC = BITTST ( R3 , 3 ); /* cc = 1 */ -R5 = CC; -BITCLR( R3 , 3 ); /* r3 = 0x00000000 */ -CC = BITTST ( R3 , 3 ); /* cc = 1 */ -R6 = CC; -BITTGL( R3 , 3 ); /* r3 = 0x00000008 */ -CC = BITTST ( R3 , 3 ); /* cc = 1 */ -R7 = CC; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000002; -CHECKREG r2, 0x00000004; -CHECKREG r3, 0x00000008; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; - -CC = BITTST ( R4 , 4 ); /* cc = 0 */ -R5 = CC; -BITSET( R4 , 4 ); /* r4 = 0x00000010 */ -CC = BITTST ( R4 , 4 ); /* cc = 1 */ -R6 = CC; -BITCLR( R4 , 4 ); /* r4 = 0x00000000 */ -CC = BITTST ( R4 , 4 ); /* cc = 1 */ -R7 = CC; -BITTGL( R4 , 4 ); /* r4 = 0x00000010 */ -CC = BITTST ( R4 , 4 ); /* cc = 1 */ -R0 = CC; -CHECKREG r4, 0x00000010; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; -CHECKREG r0, 0x00000001; - -CC = BITTST ( R5 , 5 ); /* cc = 0 */ -R6 = CC; -BITSET( R5 , 5 ); /* r5 = 0x00000020 */ -CC = BITTST ( R5 , 5 ); /* cc = 1 */ -R7 = CC; -BITCLR( R5 , 5 ); /* r5 = 0x00000000 */ -CC = BITTST ( R5 , 5 ); /* cc = 1 */ -R0 = CC; -BITTGL( R5 , 5 ); /* r5 = 0x00000020 */ -CC = BITTST ( R5 , 5 ); /* cc = 1 */ -R1 = CC; -CHECKREG r5, 0x00000020; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; - -CC = BITTST ( R6 , 6 ); /* cc = 0 */ -R7 = CC; -BITSET( R6 , 6 ); /* r6 = 0x00000040 */ -CC = BITTST ( R6 , 6 ); /* cc = 1 */ -R0 = CC; -BITCLR( R6 , 6 ); /* r6 = 0x00000000 */ -CC = BITTST ( R6 , 6 ); /* cc = 1 */ -R1 = CC; -BITTGL( R6 , 6 ); /* r6 = 0x00000040 */ -CC = BITTST ( R6 , 6 ); /* cc = 1 */ -R2 = CC; -CHECKREG r6, 0x00000040; -CHECKREG r7, 0x00000000; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; - -CC = BITTST ( R7 , 7 ); /* cc = 0 */ -R0 = CC; -BITSET( R7 , 7 ); /* r7 = 0x00000080 */ -CC = BITTST ( R7 , 7 ); /* cc = 1 */ -R1 = CC; -BITCLR( R7 , 7 ); /* r7 = 0x00000000 */ -CC = BITTST ( R7 , 7 ); /* cc = 1 */ -R2 = CC; -BITTGL( R7 , 7 ); /* r7 = 0x00000080 */ -CC = BITTST ( R7 , 7 ); /* cc = 1 */ -R3 = CC; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; - -CHECKREG r4, 0x00000010; -CHECKREG r5, 0x00000020; -CHECKREG r6, 0x00000040; -CHECKREG r7, 0x00000080; - -// bit(8-15) tst set clr toggle -CC = BITTST ( R0 , 8 ); /* cc = 0 */ -R1 = CC; -BITSET( R0 , 8 ); /* r0 = 0x00000101 */ -CC = BITTST ( R0 , 8 ); /* cc = 1 */ -R2 = CC; -BITCLR( R0 , 8 ); /* r0 = 0x00000000 */ -CC = BITTST ( R0 , 8 ); /* cc = 1 */ -R3 = CC; -BITTGL( R0 , 8 ); /* r0 = 0x00000101 */ -CC = BITTST ( R0 , 8 ); /* cc = 1 */ -R4 = CC; -CHECKREG r0, 0x00000100; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000001; - -CC = BITTST ( R1 , 9 ); /* cc = 0 */ -R2 = CC; -BITSET( R1 , 9 ); /* r1 = 0x00000200 */ -CC = BITTST ( R1 , 9 ); /* cc = 1 */ -R3 = CC; -BITCLR( R1 , 9 ); /* r1 = 0x00000000 */ -CC = BITTST ( R1 , 9 ); /* cc = 1 */ -R4 = CC; -BITTGL( R1 , 9 ); /* r1 = 0x00000200 */ -CC = BITTST ( R1 , 9 ); /* cc = 1 */ -R5 = CC; -CHECKREG r1, 0x00000200; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; - -CC = BITTST ( R2 , 10 ); /* cc = 0 */ -R3 = CC; -BITSET( R2 , 10 ); /* r2 = 0x00000400 */ -CC = BITTST ( R2 , 10 ); /* cc = 1 */ -R4 = CC; -BITCLR( R2 , 10 ); /* r2 = 0x00000000 */ -CC = BITTST ( R2 , 10 ); /* cc = 1 */ -R5 = CC; -BITTGL( R2 , 10 ); /* r2 = 0x00000400 */ -CC = BITTST ( R2 , 10 ); /* cc = 1 */ -R6 = CC; -CHECKREG r2, 0x00000400; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000001; - -CC = BITTST ( R3 , 11 ); /* cc = 0 */ -R4 = CC; -BITSET( R3 , 11 ); /* r3 = 0x00000800 */ -CC = BITTST ( R3 , 11 ); /* cc = 1 */ -R5 = CC; -BITCLR( R3 , 11 ); /* r3 = 0x00000000 */ -CC = BITTST ( R3 , 11 ); /* cc = 1 */ -R6 = CC; -BITTGL( R3 , 11 ); /* r3 = 0x00000800 */ -CC = BITTST ( R3 , 11 ); /* cc = 1 */ -R7 = CC; -CHECKREG r3, 0x00000800; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; - -CC = BITTST ( R4 , 12 ); /* cc = 0 */ -R5 = CC; -BITSET( R4 , 12 ); /* r4 = 0x00001000 */ -CC = BITTST ( R4 , 12 ); /* cc = 1 */ -R6 = CC; -BITCLR( R4 , 12 ); /* r4 = 0x00000000 */ -CC = BITTST ( R4 , 12 ); /* cc = 1 */ -R7 = CC; -BITTGL( R4 , 12 ); /* r4 = 0x00001000 */ -CC = BITTST ( R4 , 12 ); /* cc = 1 */ -R0 = CC; -CHECKREG r4, 0x00001000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; -CHECKREG r0, 0x00000001; - -CC = BITTST ( R5 , 13 ); /* cc = 0 */ -R6 = CC; -BITSET( R5 , 13 ); /* r5 = 0x00002000 */ -CC = BITTST ( R5 , 13 ); /* cc = 1 */ -R7 = CC; -BITCLR( R5 , 13 ); /* r5 = 0x00000000 */ -CC = BITTST ( R5 , 13 ); /* cc = 1 */ -R0 = CC; -BITTGL( R5 , 13 ); /* r5 = 0x00002000 */ -CC = BITTST ( R5 , 13 ); /* cc = 1 */ -R1 = CC; -CHECKREG r5, 0x00002000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; - -CC = BITTST ( R6 , 14 ); /* cc = 0 */ -R7 = CC; -BITSET( R6 , 14 ); /* r6 = 0x00004000 */ -CC = BITTST ( R6 , 14 ); /* cc = 1 */ -R0 = CC; -BITCLR( R6 , 14 ); /* r6 = 0x00000000 */ -CC = BITTST ( R6 , 14 ); /* cc = 1 */ -R1 = CC; -BITTGL( R6 , 14 ); /* r6 = 0x00004000 */ -CC = BITTST ( R6 , 14 ); /* cc = 1 */ -R2 = CC; -CHECKREG r6, 0x00004000; -CHECKREG r7, 0x00000000; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; - -CC = BITTST ( R7 , 15 ); /* cc = 0 */ -R0 = CC; -BITSET( R7 , 15 ); /* r7 = 0x00008000 */ -CC = BITTST ( R7 , 15 ); /* cc = 1 */ -R1 = CC; -BITCLR( R7 , 15 ); /* r7 = 0x00000000 */ -CC = BITTST ( R7 , 15 ); /* cc = 1 */ -R2 = CC; -BITTGL( R7 , 15 ); /* r7 = 0x00008000 */ -CC = BITTST ( R7 , 15 ); /* cc = 1 */ -R3 = CC; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00001000; -CHECKREG r5, 0x00002000; -CHECKREG r6, 0x00004000; -CHECKREG r7, 0x00008000; - -// bit(16-23) tst set clr toggle -CC = BITTST ( R0 , 16 ); /* cc = 0 */ -R1 = CC; -BITSET( R0 , 16 ); /* r0 = 0x00010000 */ -CC = BITTST ( R0 , 16 ); /* cc = 1 */ -R2 = CC; -BITCLR( R0 , 16 ); /* r0 = 0x00000000 */ -CC = BITTST ( R0 , 16 ); /* cc = 1 */ -R3 = CC; -BITTGL( R0 , 16 ); /* r0 = 0x00010000 */ -CC = BITTST ( R0 , 16 ); /* cc = 1 */ -R4 = CC; -CHECKREG r0, 0x00010000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000001; - -CC = BITTST ( R1 , 17 ); /* cc = 0 */ -R2 = CC; -BITSET( R1 , 17 ); /* r1 = 0x00020000 */ -CC = BITTST ( R1 , 17 ); /* cc = 1 */ -R3 = CC; -BITCLR( R1 , 17 ); /* r1 = 0x00000000 */ -CC = BITTST ( R1 , 17 ); /* cc = 1 */ -R4 = CC; -BITTGL( R1 , 17 ); /* r1 = 0x00020000 */ -CC = BITTST ( R1 , 17 ); /* cc = 1 */ -R5 = CC; -CHECKREG r1, 0x00020000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; - -CC = BITTST ( R2 , 18 ); /* cc = 0 */ -R3 = CC; -BITSET( R2 , 18 ); /* r2 = 0x00020000 */ -CC = BITTST ( R2 , 18 ); /* cc = 1 */ -R4 = CC; -BITCLR( R2 , 18 ); /* r2 = 0x00000000 */ -CC = BITTST ( R2 , 18 ); /* cc = 1 */ -R4 = CC; -BITTGL( R2 , 18 ); /* r2 = 0x00020000 */ -CC = BITTST ( R2 , 18 ); /* cc = 1 */ -R5 = CC; -CHECKREG r2, 0x00040000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00004000; - -CC = BITTST ( R3 , 19 ); /* cc = 0 */ -R4 = CC; -BITSET( R3 , 19 ); /* r3 = 0x00080000 */ -CC = BITTST ( R3 , 19 ); /* cc = 1 */ -R5 = CC; -BITCLR( R3 , 19 ); /* r3 = 0x00000000 */ -CC = BITTST ( R3 , 19 ); /* cc = 1 */ -R6 = CC; -BITTGL( R3 , 19 ); /* r3 = 0x00080000 */ -CC = BITTST ( R3 , 19 ); /* cc = 1 */ -R7 = CC; -CHECKREG r3, 0x00080000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; - -CC = BITTST ( R4 , 20 ); /* cc = 0 */ -R5 = CC; -BITSET( R4 , 20 ); /* r4 = 0x00100000 */ -CC = BITTST ( R4 , 20 ); /* cc = 1 */ -R6 = CC; -BITCLR( R4 , 20 ); /* r4 = 0x00000000 */ -CC = BITTST ( R4 , 20 ); /* cc = 1 */ -R7 = CC; -BITTGL( R4 , 20 ); /* r4 = 0x00100000 */ -CC = BITTST ( R4 , 20 ); /* cc = 1 */ -R0 = CC; -CHECKREG r4, 0x00100000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; -CHECKREG r0, 0x00000001; - -CC = BITTST ( R5 , 21 ); /* cc = 0 */ -R6 = CC; -BITSET( R5 , 21 ); /* r5 = 0x00200000 */ -CC = BITTST ( R5 , 21 ); /* cc = 1 */ -R7 = CC; -BITCLR( R5 , 21 ); /* r5 = 0x00000000 */ -CC = BITTST ( R5 , 21 ); /* cc = 1 */ -R0 = CC; -BITTGL( R5 , 21 ); /* r5 = 0x00200000 */ -CC = BITTST ( R5 , 21 ); /* cc = 1 */ -R1 = CC; -CHECKREG r5, 0x00200000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; - -CC = BITTST ( R6 , 22 ); /* cc = 0 */ -R7 = CC; -BITSET( R6 , 22 ); /* r6 = 0x00400000 */ -CC = BITTST ( R6 , 22 ); /* cc = 1 */ -R0 = CC; -BITCLR( R6 , 22 ); /* r6 = 0x00000000 */ -CC = BITTST ( R6 , 22 ); /* cc = 1 */ -R1 = CC; -BITTGL( R6 , 22 ); /* r6 = 0x00400000 */ -CC = BITTST ( R6 , 22 ); /* cc = 1 */ -R2 = CC; -CHECKREG r6, 0x00400000; -CHECKREG r7, 0x00000000; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; - -CC = BITTST ( R7 , 23 ); /* cc = 0 */ -R0 = CC; -BITSET( R7 , 23 ); /* r7 = 0x00800000 */ -CC = BITTST ( R7 , 23 ); /* cc = 1 */ -R1 = CC; -BITCLR( R7 , 23 ); /* r7 = 0x00000000 */ -CC = BITTST ( R7 , 23 ); /* cc = 1 */ -R2 = CC; -BITTGL( R7 , 23 ); /* r7 = 0x00800000 */ -CC = BITTST ( R7 , 23 ); /* cc = 1 */ -R3 = CC; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00100000; -CHECKREG r5, 0x00200000; -CHECKREG r6, 0x00400000; -CHECKREG r7, 0x00800000; - -// bit(24-31) tst set clr toggle -CC = BITTST ( R0 , 24 ); /* cc = 0 */ -R1 = CC; -BITSET( R0 , 24 ); /* r0 = 0x00000101 */ -CC = BITTST ( R0 , 24 ); /* cc = 1 */ -R2 = CC; -BITCLR( R0 , 24 ); /* r0 = 0x01000000 */ -CC = BITTST ( R0 , 24 ); /* cc = 1 */ -R3 = CC; -BITTGL( R0 , 24 ); /* r0 = 0x01000000 */ -CC = BITTST ( R0 , 24 ); /* cc = 1 */ -R4 = CC; -CHECKREG r0, 0x01000000; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000001; - -CC = BITTST ( R1 , 25 ); /* cc = 0 */ -R2 = CC; -BITSET( R1 , 25 ); /* r1 = 0x02000000 */ -CC = BITTST ( R1 , 25 ); /* cc = 1 */ -R3 = CC; -BITCLR( R1 , 25 ); /* r1 = 0x00000000 */ -CC = BITTST ( R1 , 25 ); /* cc = 1 */ -R4 = CC; -BITTGL( R1 , 25 ); /* r1 = 0x02000000 */ -CC = BITTST ( R1 , 25 ); /* cc = 1 */ -R5 = CC; -CHECKREG r1, 0x02000000; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; - -CC = BITTST ( R2 , 26 ); /* cc = 0 */ -R3 = CC; -BITSET( R2 , 26 ); /* r2 = 0x04000000 */ -CC = BITTST ( R2 , 26 ); /* cc = 1 */ -R4 = CC; -BITCLR( R2 , 26 ); /* r2 = 0x00000000 */ -CC = BITTST ( R2 , 26 ); /* cc = 1 */ -R5 = CC; -BITTGL( R2 , 26 ); /* r2 = 0x04000000 */ -CC = BITTST ( R2 , 26 ); /* cc = 1 */ -R6 = CC; -CHECKREG r2, 0x04000000; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000001; - -CC = BITTST ( R3 , 27 ); /* cc = 0 */ -R4 = CC; -BITSET( R3 , 27 ); /* r3 = 0x08000000 */ -CC = BITTST ( R3 , 27 ); /* cc = 1 */ -R5 = CC; -BITCLR( R3 , 27 ); /* r3 = 0x00000000 */ -CC = BITTST ( R3 , 27 ); /* cc = 1 */ -R6 = CC; -BITTGL( R3 , 27 ); /* r3 = 0x08000000 */ -CC = BITTST ( R3 , 27 ); /* cc = 1 */ -R7 = CC; -CHECKREG r3, 0x08000000; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; - -CC = BITTST ( R4 , 28 ); /* cc = 0 */ -R5 = CC; -BITSET( R4 , 28 ); /* r4 = 0x10000000 */ -CC = BITTST ( R4 , 28 ); /* cc = 1 */ -R6 = CC; -BITCLR( R4 , 28 ); /* r4 = 0x00000000 */ -CC = BITTST ( R4 , 28 ); /* cc = 1 */ -R7 = CC; -BITTGL( R4 , 28 ); /* r4 = 0x10000000 */ -CC = BITTST ( R4 , 28 ); /* cc = 1 */ -R0 = CC; -CHECKREG r4, 0x10000000; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; -CHECKREG r0, 0x00000001; - -CC = BITTST ( R5 , 29 ); /* cc = 0 */ -R6 = CC; -BITSET( R5 , 29 ); /* r5 = 0x20000000 */ -CC = BITTST ( R5 , 29 ); /* cc = 1 */ -R7 = CC; -BITCLR( R5 , 29 ); /* r5 = 0x00000000 */ -CC = BITTST ( R5 , 29 ); /* cc = 1 */ -R0 = CC; -BITTGL( R5 , 29 ); /* r5 = 0x20000000 */ -CC = BITTST ( R5 , 29 ); /* cc = 1 */ -R1 = CC; -CHECKREG r5, 0x20000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; - -CC = BITTST ( R6 , 30 ); /* cc = 0 */ -R7 = CC; -BITSET( R6 , 30 ); /* r6 = 0x40000000 */ -CC = BITTST ( R6 , 30 ); /* cc = 1 */ -R0 = CC; -BITCLR( R6 , 30 ); /* r6 = 0x00000000 */ -CC = BITTST ( R6 , 30 ); /* cc = 1 */ -R1 = CC; -BITTGL( R6 , 30 ); /* r6 = 0x40000000 */ -CC = BITTST ( R6 , 30 ); /* cc = 1 */ -R2 = CC; -CHECKREG r6, 0x40000000; -CHECKREG r7, 0x00000000; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; - -CC = BITTST ( R7 , 31 ); /* cc = 0 */ -R0 = CC; -BITSET( R7 , 31 ); /* r7 = 0x80000000 */ -CC = BITTST ( R7 , 31 ); /* cc = 1 */ -R1 = CC; -BITCLR( R7 , 31 ); /* r7 = 0x00000000 */ -CC = BITTST ( R7 , 31 ); /* cc = 1 */ -R2 = CC; -BITTGL( R7 , 31 ); /* r7 = 0x80000000 */ -CC = BITTST ( R7 , 31 ); /* cc = 1 */ -R3 = CC; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x10000000; -CHECKREG r5, 0x20000000; -CHECKREG r6, 0x40000000; -CHECKREG r7, 0x80000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_log_l_shft.s b/sim/testsuite/sim/bfin/c_logi2op_log_l_shft.s deleted file mode 100644 index 46a457a..0000000 --- a/sim/testsuite/sim/bfin/c_logi2op_log_l_shft.s +++ /dev/null @@ -1,222 +0,0 @@ -//Original:/testcases/core/c_logi2op_log_l_shft/c_logi2op_log_l_shft.dsp -// Spec Reference: Logi2op <<= -# mach: bfin - -.include "testutils.inc" - start - - - - -// Logical <<= : negative data -// bit 0-7 -imm32 r0, 0x81111111; -imm32 r1, 0x81111111; -imm32 r2, 0x81111111; -imm32 r3, 0x81111111; -imm32 r4, 0x81111111; -imm32 r5, 0x81111111; -imm32 r6, 0x81111111; -imm32 r7, 0x81111111; -R0 <<= 0; /* r0 = 0x81111111 */ -R1 <<= 1; /* r1 = 0x40888888 */ -R2 <<= 2; /* r2 = 0x20444444 */ -R3 <<= 3; /* r3 = 0x10222222 */ -R4 <<= 4; /* r4 = 0x08111111 */ -R5 <<= 5; /* r5 = 0x04088888 */ -R6 <<= 6; /* r6 = 0x02044444 */ -R7 <<= 7; /* r7 = 0x01022222 */ -CHECKREG r0, 0x81111111; -CHECKREG r1, 0x02222222; -CHECKREG r2, 0x04444444; -CHECKREG r3, 0x08888888; -CHECKREG r4, 0x11111110; -CHECKREG r5, 0x22222220; -CHECKREG r6, 0x44444440; -CHECKREG r7, 0x88888880; - -// bit 8-15 -imm32 r0, 0x82222222; -imm32 r1, 0x82222222; -imm32 r2, 0x82222222; -imm32 r3, 0x82222222; -imm32 r4, 0x82222222; -imm32 r5, 0x82222222; -imm32 r6, 0x82222222; -imm32 r7, 0x82222222; -R0 <<= 8; -R1 <<= 9; -R2 <<= 10; -R3 <<= 11; -R4 <<= 12; -R5 <<= 13; -R6 <<= 14; -R7 <<= 15; -CHECKREG r0, 0x22222200; -CHECKREG r1, 0x44444400; -CHECKREG r2, 0x88888800; -CHECKREG r3, 0x11111000; -CHECKREG r4, 0x22222000; -CHECKREG r5, 0x44444000; -CHECKREG r6, 0x88888000; -CHECKREG r7, 0x11110000; - -// bit 16-23 -imm32 r0, 0x83333333; -imm32 r1, 0x83333333; -imm32 r2, 0x83333333; -imm32 r3, 0x83333333; -imm32 r4, 0x83333333; -imm32 r5, 0x83333333; -imm32 r6, 0x83333333; -imm32 r7, 0x83333333; -R0 <<= 16; -R1 <<= 17; -R2 <<= 18; -R3 <<= 19; -R4 <<= 20; -R5 <<= 21; -R6 <<= 22; -R7 <<= 23; -CHECKREG r0, 0x33330000; -CHECKREG r1, 0x66660000; -CHECKREG r2, 0xCCCC0000; -CHECKREG r3, 0x99980000; -CHECKREG r4, 0x33300000; -CHECKREG r5, 0x66600000; -CHECKREG r6, 0xCCC00000; -CHECKREG r7, 0x99800000; - -// bit 24-31 -imm32 r0, 0x84444444; -imm32 r1, 0x84444444; -imm32 r2, 0x84444444; -imm32 r3, 0x84444444; -imm32 r4, 0x84444444; -imm32 r5, 0x84444444; -imm32 r6, 0x84444444; -imm32 r7, 0x84444444; -R0 <<= 24; -R1 <<= 25; -R2 <<= 26; -R3 <<= 27; -R4 <<= 28; -R5 <<= 29; -R6 <<= 30; -R7 <<= 31; -CHECKREG r0, 0x44000000; -CHECKREG r1, 0x88000000; -CHECKREG r2, 0x10000000; -CHECKREG r3, 0x20000000; -CHECKREG r4, 0x40000000; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -// Arithmetic <<= : positive data -// bit 0-7 -imm32 r0, 0x41111111; -imm32 r1, 0x41111111; -imm32 r2, 0x41111111; -imm32 r3, 0x41111111; -imm32 r4, 0x41111111; -imm32 r5, 0x41111111; -imm32 r6, 0x41111111; -imm32 r7, 0x41111111; -R0 <<= 0; -R1 <<= 1; -R2 <<= 2; -R3 <<= 3; -R4 <<= 4; -R5 <<= 5; -R6 <<= 6; -R7 <<= 7; -CHECKREG r0, 0x41111111; -CHECKREG r1, 0x82222222; -CHECKREG r2, 0x04444444; -CHECKREG r3, 0x08888888; -CHECKREG r4, 0x11111110; -CHECKREG r5, 0x22222220; -CHECKREG r6, 0x44444440; -CHECKREG r7, 0x88888880; - -// bit 8-15 -imm32 r0, 0x42222222; -imm32 r1, 0x42222222; -imm32 r2, 0x42222222; -imm32 r3, 0x42222222; -imm32 r4, 0x42222222; -imm32 r5, 0x42222222; -imm32 r6, 0x42222222; -imm32 r7, 0x42222222; -R0 <<= 8; -R1 <<= 9; -R2 <<= 10; -R3 <<= 11; -R4 <<= 12; -R5 <<= 13; -R6 <<= 14; -R7 <<= 15; -CHECKREG r0, 0x22222200; -CHECKREG r1, 0x44444400; -CHECKREG r2, 0x88888800; -CHECKREG r3, 0x11111000; -CHECKREG r4, 0x22222000; -CHECKREG r5, 0x44444000; -CHECKREG r6, 0x88888000; -CHECKREG r7, 0x11110000; - -// bit 16-23 -imm32 r0, 0x43333333; -imm32 r1, 0x43333333; -imm32 r2, 0x43333333; -imm32 r3, 0x43333333; -imm32 r4, 0x43333333; -imm32 r5, 0x43333333; -imm32 r6, 0x43333333; -imm32 r7, 0x43333333; -R0 <<= 16; -R1 <<= 17; -R2 <<= 18; -R3 <<= 19; -R4 <<= 20; -R5 <<= 21; -R6 <<= 22; -R7 <<= 23; -CHECKREG r0, 0x33330000; -CHECKREG r1, 0x66660000; -CHECKREG r2, 0xCCCC0000; -CHECKREG r3, 0x99980000; -CHECKREG r4, 0x33300000; -CHECKREG r5, 0x66600000; -CHECKREG r6, 0xCCC00000; -CHECKREG r7, 0x99800000; - -// bit 24-31 -imm32 r0, 0x44444444; -imm32 r1, 0x44444444; -imm32 r2, 0x44444444; -imm32 r3, 0x44444444; -imm32 r4, 0x44444444; -imm32 r5, 0x44444444; -imm32 r6, 0x44444444; -imm32 r7, 0x44444444; -R0 <<= 24; -R1 <<= 25; -R2 <<= 26; -R3 <<= 27; -R4 <<= 28; -R5 <<= 29; -R6 <<= 30; -R7 <<= 31; -CHECKREG r0, 0x44000000; -CHECKREG r1, 0x88000000; -CHECKREG r2, 0x10000000; -CHECKREG r3, 0x20000000; -CHECKREG r4, 0x40000000; -CHECKREG r5, 0x80000000; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - - -pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_log_l_shft_astat.S b/sim/testsuite/sim/bfin/c_logi2op_log_l_shft_astat.S deleted file mode 100644 index 6b3e8ca..0000000 --- a/sim/testsuite/sim/bfin/c_logi2op_log_l_shft_astat.S +++ /dev/null @@ -1,82 +0,0 @@ -# Test ASTAT bits with logical left shift (<<=) -# mach: bfin - -.include "testutils.inc" -#include "test.h" -start - -.macro __do val:req, shift:req, exp:req - # First test when ASTAT starts with all bits cleared - imm32 R2, \val; - ASTAT = R0; - R2 <<= \shift; - R3 = ASTAT; - CHECKREG R2, (\val << \shift); - CHECKREG R3, \exp; - - # Then test when ASTAT starts with all bits set - imm32 R2, \val; - ASTAT = R1; - R2 <<= \shift; - R3 = ASTAT; - CHECKREG R3, (\exp) | ~(_AZ|_AN|_V|_V_COPY); -.endm - -.macro _do shift:req, val:req - # Automatically test all shifted values - .if ((\val << \shift) & 0xffffffff) == 0 - __do \val, \shift, _AZ - .else - .if (\val << \shift) == 0x80000000 - __do \val, \shift, _AN - .else - __do \val, \shift, 0 - .endif - .endif - .if (\val << 1) & 0xffffffff - _do \shift, (\val << 1) - .endif -.endm - -.macro do shift:req -_l_shft_\shift: - _do \shift, 1 -.endm - -R0 = 0; -R1 = -1; - -do 0 -do 1 -do 2 -do 3 -do 4 -do 5 -do 6 -do 7 -do 8 -do 9 -do 10 -do 11 -do 12 -do 13 -do 14 -do 15 -do 16 -do 17 -do 18 -do 19 -do 20 -do 21 -do 22 -do 23 -do 24 -do 25 -do 26 -do 27 -do 28 -do 29 -do 30 -do 31 - -pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_log_r_shft.s b/sim/testsuite/sim/bfin/c_logi2op_log_r_shft.s deleted file mode 100644 index af4eb73..0000000 --- a/sim/testsuite/sim/bfin/c_logi2op_log_r_shft.s +++ /dev/null @@ -1,222 +0,0 @@ -//Original:/testcases/core/c_logi2op_log_r_shft/c_logi2op_log_r_shft.dsp -// Spec Reference: Logi2op >>= -# mach: bfin - -.include "testutils.inc" - start - - - - -// Logical >>= : negative data -// bit 0-7 -imm32 r0, 0x81111111; -imm32 r1, 0x81111111; -imm32 r2, 0x81111111; -imm32 r3, 0x81111111; -imm32 r4, 0x81111111; -imm32 r5, 0x81111111; -imm32 r6, 0x81111111; -imm32 r7, 0x81111111; -R0 >>= 0; /* r0 = 0x81111111 */ -R1 >>= 1; /* r1 = 0x40888888 */ -R2 >>= 2; /* r2 = 0x20444444 */ -R3 >>= 3; /* r3 = 0x10222222 */ -R4 >>= 4; /* r4 = 0x08111111 */ -R5 >>= 5; /* r5 = 0x04088888 */ -R6 >>= 6; /* r6 = 0x02044444 */ -R7 >>= 7; /* r7 = 0x01022222 */ -CHECKREG r0, 0x81111111; -CHECKREG r1, 0x40888888; -CHECKREG r2, 0x20444444; -CHECKREG r3, 0x10222222; -CHECKREG r4, 0x08111111; -CHECKREG r5, 0x04088888; -CHECKREG r6, 0x02044444; -CHECKREG r7, 0x01022222; - -// bit 8-15 -imm32 r0, 0x82222222; -imm32 r1, 0x82222222; -imm32 r2, 0x82222222; -imm32 r3, 0x82222222; -imm32 r4, 0x82222222; -imm32 r5, 0x82222222; -imm32 r6, 0x82222222; -imm32 r7, 0x82222222; -R0 >>= 8; /* r0 = 0x00822222 */ -R1 >>= 9; /* r1 = 0x00411111 */ -R2 >>= 10; /* r2 = 0x00208888 */ -R3 >>= 11; /* r3 = 0x00104444 */ -R4 >>= 12; /* r4 = 0x00082222 */ -R5 >>= 13; /* r5 = 0x00041111 */ -R6 >>= 14; /* r6 = 0x00020888 */ -R7 >>= 15; /* r7 = 0x00010444 */ -CHECKREG r0, 0x00822222; -CHECKREG r1, 0x00411111; -CHECKREG r2, 0x00208888; -CHECKREG r3, 0x00104444; -CHECKREG r4, 0x00082222; -CHECKREG r5, 0x00041111; -CHECKREG r6, 0x00020888; -CHECKREG r7, 0x00010444; - -// bit 16-23 -imm32 r0, 0x83333333; -imm32 r1, 0x83333333; -imm32 r2, 0x83333333; -imm32 r3, 0x83333333; -imm32 r4, 0x83333333; -imm32 r5, 0x83333333; -imm32 r6, 0x83333333; -imm32 r7, 0x83333333; -R0 >>= 16; /* r0 = 0x00008333 */ -R1 >>= 17; /* r1 = 0x00004199 */ -R2 >>= 18; /* r2 = 0x000020CC */ -R3 >>= 19; /* r3 = 0x00001066 */ -R4 >>= 20; /* r4 = 0x00000833 */ -R5 >>= 21; /* r5 = 0x00000419 */ -R6 >>= 22; /* r6 = 0x0000020C */ -R7 >>= 23; /* r7 = 0x00000106 */ -CHECKREG r0, 0x00008333; -CHECKREG r1, 0x00004199; -CHECKREG r2, 0x000020CC; -CHECKREG r3, 0x00001066; -CHECKREG r4, 0x00000833; -CHECKREG r5, 0x00000419; -CHECKREG r6, 0x0000020C; -CHECKREG r7, 0x00000106; - -// bit 24-31 -imm32 r0, 0x84444444; -imm32 r1, 0x84444444; -imm32 r2, 0x84444444; -imm32 r3, 0x84444444; -imm32 r4, 0x84444444; -imm32 r5, 0x84444444; -imm32 r6, 0x84444444; -imm32 r7, 0x84444444; -R0 >>= 24; /* r0 = 0x00000084 */ -R1 >>= 25; /* r1 = 0x00000042 */ -R2 >>= 26; /* r2 = 0x00000021 */ -R3 >>= 27; /* r3 = 0x00000010 */ -R4 >>= 28; /* r4 = 0x00000008 */ -R5 >>= 29; /* r5 = 0x00000004 */ -R6 >>= 30; /* r6 = 0x00000002 */ -R7 >>= 31; /* r7 = 0x00000001 */ -CHECKREG r0, 0x00000084; -CHECKREG r1, 0x00000042; -CHECKREG r2, 0x00000021; -CHECKREG r3, 0x00000010; -CHECKREG r4, 0x00000008; -CHECKREG r5, 0x00000004; -CHECKREG r6, 0x00000002; -CHECKREG r7, 0x00000001; - -// Arithmetic >>= : positive data -// bit 0-7 -imm32 r0, 0x41111111; -imm32 r1, 0x41111111; -imm32 r2, 0x41111111; -imm32 r3, 0x41111111; -imm32 r4, 0x41111111; -imm32 r5, 0x41111111; -imm32 r6, 0x41111111; -imm32 r7, 0x41111111; -R0 >>= 0; /* r0 = 0x41111111 */ -R1 >>= 1; /* r1 = 0x20888888 */ -R2 >>= 2; /* r2 = 0x10444444 */ -R3 >>= 3; /* r3 = 0x08222222 */ -R4 >>= 4; /* r4 = 0x04111111 */ -R5 >>= 5; /* r5 = 0x02088888 */ -R6 >>= 6; /* r6 = 0x01044444 */ -R7 >>= 7; /* r7 = 0x00822222 */ -CHECKREG r0, 0x41111111; -CHECKREG r1, 0x20888888; -CHECKREG r2, 0x10444444; -CHECKREG r3, 0x08222222; -CHECKREG r4, 0x04111111; -CHECKREG r5, 0x02088888; -CHECKREG r6, 0x01044444; -CHECKREG r7, 0x00822222; - -// bit 8-15 -imm32 r0, 0x42222222; -imm32 r1, 0x42222222; -imm32 r2, 0x42222222; -imm32 r3, 0x42222222; -imm32 r4, 0x42222222; -imm32 r5, 0x42222222; -imm32 r6, 0x42222222; -imm32 r7, 0x42222222; -R0 >>= 8; /* r0 = 0x00422222 */ -R1 >>= 9; /* r1 = 0x00211111 */ -R2 >>= 10; /* r2 = 0x00108888 */ -R3 >>= 11; /* r3 = 0x00084444 */ -R4 >>= 12; /* r4 = 0x00042222 */ -R5 >>= 13; /* r5 = 0x00021111 */ -R6 >>= 14; /* r6 = 0x00010888 */ -R7 >>= 15; /* r7 = 0x00008444 */ -CHECKREG r0, 0x00422222; -CHECKREG r1, 0x00211111; -CHECKREG r2, 0x00108888; -CHECKREG r3, 0x00084444; -CHECKREG r4, 0x00042222; -CHECKREG r5, 0x00021111; -CHECKREG r6, 0x00010888; -CHECKREG r7, 0x00008444; - -// bit 16-23 -imm32 r0, 0x43333333; -imm32 r1, 0x43333333; -imm32 r2, 0x43333333; -imm32 r3, 0x43333333; -imm32 r4, 0x43333333; -imm32 r5, 0x43333333; -imm32 r6, 0x43333333; -imm32 r7, 0x43333333; -R0 >>= 16; /* r0 = 0x00004333 */ -R1 >>= 17; /* r1 = 0x00002199 */ -R2 >>= 18; /* r2 = 0x000010CC */ -R3 >>= 19; /* r3 = 0x00000866 */ -R4 >>= 20; /* r4 = 0x00000433 */ -R5 >>= 21; /* r5 = 0x00000219 */ -R6 >>= 22; /* r6 = 0x0000010C */ -R7 >>= 23; /* r7 = 0x00000086 */ -CHECKREG r0, 0x00004333; -CHECKREG r1, 0x00002199; -CHECKREG r2, 0x000010CC; -CHECKREG r3, 0x00000866; -CHECKREG r4, 0x00000433; -CHECKREG r5, 0x00000219; -CHECKREG r6, 0x0000010C; -CHECKREG r7, 0x00000086; - -// bit 24-31 -imm32 r0, 0x44444444; -imm32 r1, 0x44444444; -imm32 r2, 0x44444444; -imm32 r3, 0x44444444; -imm32 r4, 0x44444444; -imm32 r5, 0x44444444; -imm32 r6, 0x44444444; -imm32 r7, 0x44444444; -R0 >>= 24; /* r0 = 0x00000044 */ -R1 >>= 25; /* r1 = 0x00000022 */ -R2 >>= 26; /* r2 = 0x00000011 */ -R3 >>= 27; /* r3 = 0x00000008 */ -R4 >>= 28; /* r4 = 0x00000004 */ -R5 >>= 29; /* r5 = 0x00000002 */ -R6 >>= 30; /* r6 = 0x00000001 */ -R7 >>= 31; /* r7 = 0x00000000 */ -CHECKREG r0, 0x00000044; -CHECKREG r1, 0x00000022; -CHECKREG r2, 0x00000011; -CHECKREG r3, 0x00000008; -CHECKREG r4, 0x00000004; -CHECKREG r5, 0x00000002; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; - - -pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_log_r_shft_astat.S b/sim/testsuite/sim/bfin/c_logi2op_log_r_shft_astat.S deleted file mode 100644 index 4f2a22b..0000000 --- a/sim/testsuite/sim/bfin/c_logi2op_log_r_shft_astat.S +++ /dev/null @@ -1,82 +0,0 @@ -# Test ASTAT bits with logical right shift (>>=) -# mach: bfin - -.include "testutils.inc" -#include "test.h" -start - -.macro __do val:req, shift:req, exp:req - # First test when ASTAT starts with all bits cleared - imm32 R2, \val; - ASTAT = R0; - R2 >>= \shift; - R3 = ASTAT; - CHECKREG R2, (\val >> \shift); - CHECKREG R3, \exp; - - # Then test when ASTAT starts with all bits set - imm32 R2, \val; - ASTAT = R1; - R2 >>= \shift; - R3 = ASTAT; - CHECKREG R3, (\exp) | ~(_AZ|_AN|_V|_V_COPY); -.endm - -.macro _do shift:req, val:req - # Automatically test all shifted values - .if ((\val >> \shift) & 0xffffffff) == 0 - __do \val, \shift, _AZ - .else - .if (\val >> \shift) == 0x80000000 - __do \val, \shift, _AN - .else - __do \val, \shift, 0 - .endif - .endif - .if (\val >> 1) & 0xffffffff - _do \shift, (\val >> 1) - .endif -.endm - -.macro do shift:req -_l_shft_\shift: - _do \shift, 0x80000000 -.endm - -R0 = 0; -R1 = -1; - -do 0 -do 1 -do 2 -do 3 -do 4 -do 5 -do 6 -do 7 -do 8 -do 9 -do 10 -do 11 -do 12 -do 13 -do 14 -do 15 -do 16 -do 17 -do 18 -do 19 -do 20 -do 21 -do 22 -do 23 -do 24 -do 25 -do 26 -do 27 -do 28 -do 29 -do 30 -do 31 - -pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_nbittst.s b/sim/testsuite/sim/bfin/c_logi2op_nbittst.s deleted file mode 100644 index b881c2b..0000000 --- a/sim/testsuite/sim/bfin/c_logi2op_nbittst.s +++ /dev/null @@ -1,584 +0,0 @@ -//Original:/testcases/core/c_logi2op_nbittst/c_logi2op_nbittst.dsp -// Spec Reference: Logi2op !bittst -# mach: bfin - -.include "testutils.inc" - start - - - - -imm32 r0, 0x00000000; -imm32 r1, 0x00000000; -imm32 r2, 0x00000000; -imm32 r3, 0x00000000; -imm32 r4, 0x00000000; -imm32 r5, 0x00000000; -imm32 r6, 0x00000000; -imm32 r7, 0x00000000; - -// bit(0-7) tst set clr toggle -CC = ! BITTST( R0 , 0 ); /* cc = 0 */ -BITSET( R0 , 0 ); /* r0 = 0x00000001 */ -R1 = CC; -CC = ! BITTST( R0 , 0 ); /* cc = 1 */ -R2 = CC; -BITCLR( R0 , 0 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R0 , 0 ); /* cc = 1 */ -R3 = CC; -BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ -CC = ! BITTST( R0 , 0 ); /* cc = 1 */ -R4 = CC; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; - -CC = ! BITTST( R1 , 1 ); /* cc = 0 */ -R2 = CC; -BITSET( R1 , 1 ); /* r0 = 0x00000002 */ -CC = ! BITTST( R1 , 1 ); /* cc = 1 */ -R3 = CC; -BITCLR( R1 , 1 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R1 , 1 ); /* cc = 1 */ -R4 = CC; -BITTGL( R1 , 1 ); /* r0 = 0x00000002 */ -CC = ! BITTST( R1 , 1 ); /* cc = 1 */ -R5 = CC; -CHECKREG r1, 0x00000003; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000000; - -CC = ! BITTST( R2 , 2 ); /* cc = 0 */ -R3 = CC; -BITSET( R2 , 2 ); /* r0 = 0x00000004 */ -CC = ! BITTST( R2 , 2 ); /* cc = 1 */ -R4 = CC; -BITCLR( R2 , 2 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R2 , 2 ); /* cc = 1 */ -R5 = CC; -BITTGL( R2 , 2 ); /* r0 = 0x00000004 */ -CC = ! BITTST( R2 , 2 ); /* cc = 1 */ -R6 = CC; -CHECKREG r2, 0x00000005; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000000; - -CC = ! BITTST( R3 , 3 ); /* cc = 0 */ -R4 = CC; -BITSET( R3 , 3 ); /* r0 = 0x00000008 */ -CC = ! BITTST( R3 , 3 ); /* cc = 1 */ -R5 = CC; -BITCLR( R3 , 3 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R3 , 3 ); /* cc = 1 */ -R6 = CC; -BITTGL( R3 , 3 ); /* r0 = 0x00000008 */ -CC = ! BITTST( R3 , 3 ); /* cc = 1 */ -R7 = CC; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000003; -CHECKREG r2, 0x00000005; -CHECKREG r3, 0x00000009; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; - -CC = ! BITTST( R4 , 4 ); /* cc = 0 */ -R5 = CC; -BITSET( R4 , 4 ); /* r0 = 0x00000010 */ -CC = ! BITTST( R4 , 4 ); /* cc = 1 */ -R6 = CC; -BITCLR( R4 , 4 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R4 , 4 ); /* cc = 1 */ -R7 = CC; -BITTGL( R4 , 4 ); /* r0 = 0x00000010 */ -CC = ! BITTST( R4 , 4 ); /* cc = 1 */ -R0 = CC; -CHECKREG r4, 0x00000011; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; -CHECKREG r0, 0x00000000; - -CC = ! BITTST( R5 , 5 ); /* cc = 0 */ -R6 = CC; -BITSET( R5 , 5 ); /* r0 = 0x00000020 */ -CC = ! BITTST( R5 , 5 ); /* cc = 1 */ -R7 = CC; -BITCLR( R5 , 5 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R5 , 5 ); /* cc = 1 */ -R0 = CC; -BITTGL( R5 , 5 ); /* r0 = 0x00000020 */ -CC = ! BITTST( R5 , 5 ); /* cc = 1 */ -R1 = CC; -CHECKREG r5, 0x00000021; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; - -CC = ! BITTST( R6 , 6 ); /* cc = 0 */ -R7 = CC; -BITSET( R6 , 6 ); /* r0 = 0x00000040 */ -CC = ! BITTST( R6 , 6 ); /* cc = 1 */ -R0 = CC; -BITCLR( R6 , 6 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R6 , 6 ); /* cc = 1 */ -R1 = CC; -BITTGL( R6 , 6 ); /* r0 = 0x00000040 */ -CC = ! BITTST( R6 , 6 ); /* cc = 1 */ -R2 = CC; -CHECKREG r6, 0x00000041; -CHECKREG r7, 0x00000001; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; - -CC = ! BITTST( R7 , 7 ); /* cc = 0 */ -R0 = CC; -BITSET( R7 , 7 ); /* r0 = 0x00000080 */ -CC = ! BITTST( R7 , 7 ); /* cc = 1 */ -R1 = CC; -BITCLR( R7 , 7 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R7 , 7 ); /* cc = 1 */ -R2 = CC; -BITTGL( R7 , 7 ); /* r0 = 0x00000080 */ -CC = ! BITTST( R7 , 7 ); /* cc = 1 */ -R3 = CC; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000000; - -CHECKREG r4, 0x00000011; -CHECKREG r5, 0x00000021; -CHECKREG r6, 0x00000041; -CHECKREG r7, 0x00000081; - -// bit(8-15) tst set clr toggle -CC = ! BITTST( R0 , 8 ); /* cc = 0 */ -R1 = CC; -BITSET( R0 , 8 ); /* r0 = 0x00000101 */ -CC = ! BITTST( R0 , 8 ); /* cc = 1 */ -R2 = CC; -BITCLR( R0 , 8 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R0 , 8 ); /* cc = 1 */ -R3 = CC; -BITTGL( R0 , 8 ); /* r0 = 0x00000101 */ -CC = ! BITTST( R0 , 8 ); /* cc = 1 */ -R4 = CC; -CHECKREG r0, 0x00000101; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; - -CC = ! BITTST( R1 , 9 ); /* cc = 0 */ -R2 = CC; -BITSET( R1 , 9 ); /* r0 = 0x00000202 */ -CC = ! BITTST( R1 , 9 ); /* cc = 1 */ -R3 = CC; -BITCLR( R1 , 9 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R1 , 9 ); /* cc = 1 */ -R4 = CC; -BITTGL( R1 , 9 ); /* r0 = 0x00000202 */ -CC = ! BITTST( R1 , 9 ); /* cc = 1 */ -R5 = CC; -CHECKREG r1, 0x00000201; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000000; - -CC = ! BITTST( R2 , 10 ); /* cc = 0 */ -R3 = CC; -BITSET( R2 , 10 ); /* r0 = 0x00000404 */ -CC = ! BITTST( R2 , 10 ); /* cc = 1 */ -R4 = CC; -BITCLR( R2 , 10 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R2 , 10 ); /* cc = 1 */ -R5 = CC; -BITTGL( R2 , 10 ); /* r0 = 0x00000404 */ -CC = ! BITTST( R2 , 10 ); /* cc = 1 */ -R6 = CC; -CHECKREG r2, 0x00000401; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000000; - -CC = ! BITTST( R3 , 11 ); /* cc = 0 */ -R4 = CC; -BITSET( R3 , 11 ); /* r0 = 0x00000808 */ -CC = ! BITTST( R3 , 11 ); /* cc = 1 */ -R5 = CC; -BITCLR( R3 , 11 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R3 , 11 ); /* cc = 1 */ -R6 = CC; -BITTGL( R3 , 11 ); /* r0 = 0x00000808 */ -CC = ! BITTST( R3 , 11 ); /* cc = 1 */ -R7 = CC; -CHECKREG r3, 0x00000801; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; - -CC = ! BITTST( R4 , 12 ); /* cc = 0 */ -R5 = CC; -BITSET( R4 , 12 ); /* r0 = 0x00001010 */ -CC = ! BITTST( R4 , 12 ); /* cc = 1 */ -R6 = CC; -BITCLR( R4 , 12 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R4 , 12 ); /* cc = 1 */ -R7 = CC; -BITTGL( R4 , 12 ); /* r0 = 0x00001010 */ -CC = ! BITTST( R4 , 12 ); /* cc = 1 */ -R0 = CC; -CHECKREG r4, 0x00001001; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; -CHECKREG r0, 0x00000000; - -CC = ! BITTST( R5 , 13 ); /* cc = 0 */ -R6 = CC; -BITSET( R5 , 13 ); /* r0 = 0x00002020 */ -CC = ! BITTST( R5 , 13 ); /* cc = 1 */ -R7 = CC; -BITCLR( R5 , 13 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R5 , 13 ); /* cc = 1 */ -R0 = CC; -BITTGL( R5 , 13 ); /* r0 = 0x00002020 */ -CC = ! BITTST( R5 , 13 ); /* cc = 1 */ -R1 = CC; -CHECKREG r5, 0x00002001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; - -CC = ! BITTST( R6 , 14 ); /* cc = 0 */ -R7 = CC; -BITSET( R6 , 14 ); /* r0 = 0x00004040 */ -CC = ! BITTST( R6 , 14 ); /* cc = 1 */ -R0 = CC; -BITCLR( R6 , 14 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R6 , 14 ); /* cc = 1 */ -R1 = CC; -BITTGL( R6 , 14 ); /* r0 = 0x00004040 */ -CC = ! BITTST( R6 , 14 ); /* cc = 1 */ -R2 = CC; -CHECKREG r6, 0x00004001; -CHECKREG r7, 0x00000001; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; - -CC = ! BITTST( R7 , 15 ); /* cc = 0 */ -R0 = CC; -BITSET( R7 , 15 ); /* r0 = 0x00008080 */ -CC = ! BITTST( R7 , 15 ); /* cc = 1 */ -R1 = CC; -BITCLR( R7 , 15 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R7 , 15 ); /* cc = 1 */ -R2 = CC; -BITTGL( R7 , 15 ); /* r0 = 0x00008080 */ -CC = ! BITTST( R7 , 15 ); /* cc = 1 */ -R3 = CC; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00001001; -CHECKREG r5, 0x00002001; -CHECKREG r6, 0x00004001; -CHECKREG r7, 0x00008001; - -// bit(16-23) tst set clr toggle -CC = ! BITTST( R0 , 16 ); /* cc = 0 */ -R1 = CC; -BITSET( R0 , 16 ); /* r0 = 0x00000001 */ -CC = ! BITTST( R0 , 16 ); /* cc = 1 */ -R2 = CC; -BITCLR( R0 , 16 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R0 , 16 ); /* cc = 1 */ -R3 = CC; -BITTGL( R0 , 16 ); /* r0 = 0x00000001 */ -CC = ! BITTST( R0 , 16 ); /* cc = 1 */ -R4 = CC; -CHECKREG r0, 0x00010001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; - -CC = ! BITTST( R1 , 17 ); /* cc = 0 */ -R2 = CC; -BITSET( R1 , 17 ); /* r0 = 0x00000002 */ -CC = ! BITTST( R1 , 17 ); /* cc = 1 */ -R3 = CC; -BITCLR( R1 , 17 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R1 , 17 ); /* cc = 1 */ -R4 = CC; -BITTGL( R1 , 17 ); /* r0 = 0x00000002 */ -CC = ! BITTST( R1 , 17 ); /* cc = 1 */ -R5 = CC; -CHECKREG r1, 0x00020001; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000000; - -CC = ! BITTST( R2 , 18 ); /* cc = 0 */ -R3 = CC; -BITSET( R2 , 18 ); /* r0 = 0x00000004 */ -CC = ! BITTST( R2 , 18 ); /* cc = 1 */ -R4 = CC; -BITCLR( R2 , 18 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R2 , 18 ); /* cc = 1 */ -R4 = CC; -BITTGL( R2 , 18 ); /* r0 = 0x00000004 */ -CC = ! BITTST( R2 , 18 ); /* cc = 1 */ -R5 = CC; -CHECKREG r2, 0x00040001; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00004001; - -CC = ! BITTST( R3 , 19 ); /* cc = 0 */ -R4 = CC; -BITSET( R3 , 19 ); /* r0 = 0x00000008 */ -CC = ! BITTST( R3 , 19 ); /* cc = 1 */ -R5 = CC; -BITCLR( R3 , 19 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R3 , 19 ); /* cc = 1 */ -R6 = CC; -BITTGL( R3 , 19 ); /* r0 = 0x00000008 */ -CC = ! BITTST( R3 , 19 ); /* cc = 1 */ -R7 = CC; -CHECKREG r3, 0x00080001; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; - -CC = ! BITTST( R4 , 20 ); /* cc = 0 */ -R5 = CC; -BITSET( R4 , 20 ); /* r0 = 0x00000010 */ -CC = ! BITTST( R4 , 20 ); /* cc = 1 */ -R6 = CC; -BITCLR( R4 , 20 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R4 , 20 ); /* cc = 1 */ -R7 = CC; -BITTGL( R4 , 20 ); /* r0 = 0x00000010 */ -CC = ! BITTST( R4 , 20 ); /* cc = 1 */ -R0 = CC; -CHECKREG r4, 0x00100001; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; -CHECKREG r0, 0x00000000; - -CC = ! BITTST( R5 , 21 ); /* cc = 0 */ -R6 = CC; -BITSET( R5 , 21 ); /* r0 = 0x00000020 */ -CC = ! BITTST( R5 , 21 ); /* cc = 1 */ -R7 = CC; -BITCLR( R5 , 21 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R5 , 21 ); /* cc = 1 */ -R0 = CC; -BITTGL( R5 , 21 ); /* r0 = 0x00000020 */ -CC = ! BITTST( R5 , 21 ); /* cc = 1 */ -R1 = CC; -CHECKREG r5, 0x00200001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; - -CC = ! BITTST( R6 , 22 ); /* cc = 0 */ -R7 = CC; -BITSET( R6 , 22 ); /* r0 = 0x00000040 */ -CC = ! BITTST( R6 , 22 ); /* cc = 1 */ -R0 = CC; -BITCLR( R6 , 22 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R6 , 22 ); /* cc = 1 */ -R1 = CC; -BITTGL( R6 , 22 ); /* r0 = 0x00000040 */ -CC = ! BITTST( R6 , 22 ); /* cc = 1 */ -R2 = CC; -CHECKREG r6, 0x00400001; -CHECKREG r7, 0x00000001; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; - -CC = ! BITTST( R7 , 23 ); /* cc = 0 */ -R0 = CC; -BITSET( R7 , 23 ); /* r0 = 0x00000080 */ -CC = ! BITTST( R7 , 23 ); /* cc = 1 */ -R1 = CC; -BITCLR( R7 , 23 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R7 , 23 ); /* cc = 1 */ -R2 = CC; -BITTGL( R7 , 23 ); /* r0 = 0x00000080 */ -CC = ! BITTST( R7 , 23 ); /* cc = 1 */ -R3 = CC; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00100001; -CHECKREG r5, 0x00200001; -CHECKREG r6, 0x00400001; -CHECKREG r7, 0x00800001; - -// bit(24-31) tst set clr toggle -CC = ! BITTST( R0 , 24 ); /* cc = 0 */ -R1 = CC; -BITSET( R0 , 24 ); /* r0 = 0x00000101 */ -CC = ! BITTST( R0 , 24 ); /* cc = 1 */ -R2 = CC; -BITCLR( R0 , 24 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R0 , 24 ); /* cc = 1 */ -R3 = CC; -BITTGL( R0 , 24 ); /* r0 = 0x00000101 */ -CC = ! BITTST( R0 , 24 ); /* cc = 1 */ -R4 = CC; -CHECKREG r0, 0x01000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; - -CC = ! BITTST( R1 , 25 ); /* cc = 0 */ -R2 = CC; -BITSET( R1 , 25 ); /* r0 = 0x00000202 */ -CC = ! BITTST( R1 , 25 ); /* cc = 1 */ -R3 = CC; -BITCLR( R1 , 25 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R1 , 25 ); /* cc = 1 */ -R4 = CC; -BITTGL( R1 , 25 ); /* r0 = 0x00000202 */ -CC = ! BITTST( R1 , 25 ); /* cc = 1 */ -R5 = CC; -CHECKREG r1, 0x02000001; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000000; - -CC = ! BITTST( R2 , 26 ); /* cc = 0 */ -R3 = CC; -BITSET( R2 , 26 ); /* r0 = 0x00000404 */ -CC = ! BITTST( R2 , 26 ); /* cc = 1 */ -R4 = CC; -BITCLR( R2 , 26 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R2 , 26 ); /* cc = 1 */ -R5 = CC; -BITTGL( R2 , 26 ); /* r0 = 0x00000404 */ -CC = ! BITTST( R2 , 26 ); /* cc = 1 */ -R6 = CC; -CHECKREG r2, 0x04000001; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000000; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000000; - -CC = ! BITTST( R3 , 27 ); /* cc = 0 */ -R4 = CC; -BITSET( R3 , 27 ); /* r0 = 0x00000808 */ -CC = ! BITTST( R3 , 27 ); /* cc = 1 */ -R5 = CC; -BITCLR( R3 , 27 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R3 , 27 ); /* cc = 1 */ -R6 = CC; -BITTGL( R3 , 27 ); /* r0 = 0x00000808 */ -CC = ! BITTST( R3 , 27 ); /* cc = 1 */ -R7 = CC; -CHECKREG r3, 0x08000001; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; - -CC = ! BITTST( R4 , 28 ); /* cc = 0 */ -R5 = CC; -BITSET( R4 , 28 ); /* r0 = 0x00001010 */ -CC = ! BITTST( R4 , 28 ); /* cc = 1 */ -R6 = CC; -BITCLR( R4 , 28 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R4 , 28 ); /* cc = 1 */ -R7 = CC; -BITTGL( R4 , 28 ); /* r0 = 0x00001010 */ -CC = ! BITTST( R4 , 28 ); /* cc = 1 */ -R0 = CC; -CHECKREG r4, 0x10000001; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000001; -CHECKREG r0, 0x00000000; - -CC = ! BITTST( R5 , 29 ); /* cc = 0 */ -R6 = CC; -BITSET( R5 , 29 ); /* r0 = 0x00002020 */ -CC = ! BITTST( R5 , 29 ); /* cc = 1 */ -R7 = CC; -BITCLR( R5 , 29 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R5 , 29 ); /* cc = 1 */ -R0 = CC; -BITTGL( R5 , 29 ); /* r0 = 0x00002020 */ -CC = ! BITTST( R5 , 29 ); /* cc = 1 */ -R1 = CC; -CHECKREG r5, 0x20000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000000; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; - -CC = ! BITTST( R6 , 30 ); /* cc = 0 */ -R7 = CC; -BITSET( R6 , 30 ); /* r0 = 0x00004040 */ -CC = ! BITTST( R6 , 30 ); /* cc = 1 */ -R0 = CC; -BITCLR( R6 , 30 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R6 , 30 ); /* cc = 1 */ -R1 = CC; -BITTGL( R6 , 30 ); /* r0 = 0x00004040 */ -CC = ! BITTST( R6 , 30 ); /* cc = 1 */ -R2 = CC; -CHECKREG r6, 0x40000001; -CHECKREG r7, 0x00000001; -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000000; - -CC = ! BITTST( R7 , 31 ); /* cc = 0 */ -R0 = CC; -BITSET( R7 , 31 ); /* r0 = 0x00008080 */ -CC = ! BITTST( R7 , 31 ); /* cc = 1 */ -R1 = CC; -BITCLR( R7 , 31 ); /* r0 = 0x00000000 */ -CC = ! BITTST( R7 , 31 ); /* cc = 1 */ -R2 = CC; -BITTGL( R7 , 31 ); /* r0 = 0x80808080 */ -CC = ! BITTST( R7 , 31 ); /* cc = 1 */ -R3 = CC; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000000; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000000; -CHECKREG r4, 0x10000001; -CHECKREG r5, 0x20000001; -CHECKREG r6, 0x40000001; -CHECKREG r7, 0x80000001; - -pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_nested.s b/sim/testsuite/sim/bfin/c_loopsetup_nested.s deleted file mode 100644 index b351bc5..0000000 --- a/sim/testsuite/sim/bfin/c_loopsetup_nested.s +++ /dev/null @@ -1,166 +0,0 @@ -//Original:/testcases/core/c_loopsetup_nested/c_loopsetup_nested.dsp -// Spec Reference: loopsetup nested inside -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -ASTAT = r0; - -//p0 = 2; -P1 = 3; -P2 = 4; -P3 = 5; -P4 = 6; -P5 = 7; -SP = 8; -FP = 9; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start1 , end1 ) LC0 = P1; -start1: R0 += 1; - R1 += -2; -LSETUP ( start2 , end2 ) LC1 = P2; -start2: R4 += 4; -end2: R5 += -5; - R3 += 1; -end1: R2 += 3; - R3 += 4; -LSETUP ( start3 , end3 ) LC1 = P3; -start3: R6 += 6; -LSETUP ( start4 , end4 ) LC0 = P4 >> 1; -start4: R0 += 1; - R1 += -2; -end4: R2 += 3; - R3 += 4; -end3: R7 += -7; - R3 += 1; -CHECKREG r0, 0x00000017; -CHECKREG r1, 0xFFFFFFEC; -CHECKREG r2, 0x00000056; -CHECKREG r3, 0x0000004C; -CHECKREG r4, 0x00000070; -CHECKREG r5, 0x00000014; -CHECKREG r6, 0x0000007E; -CHECKREG r7, 0x0000004D; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start5 , end5 ) LC0 = P5; -start5: R4 += 1; -LSETUP ( start6 , end6 ) LC1 = SP >> 1; -start6: R6 += 4; -end6: R7 += -5; - R3 += 6; -end5: R5 += -2; - R3 += 3; -CHECKREG r0, 0x00000005; -CHECKREG r1, 0x00000010; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x0000005D; -CHECKREG r4, 0x00000047; -CHECKREG r5, 0x00000042; -CHECKREG r6, 0x000000D0; -CHECKREG r7, 0xFFFFFFE4; -LSETUP ( start7 , end7 ) LC0 = FP; -start7: R4 += 4; -end7: R5 += -5; - R3 += 6; -CHECKREG r0, 0x00000005; -CHECKREG r1, 0x00000010; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000063; -CHECKREG r4, 0x0000006B; -CHECKREG r5, 0x00000015; -CHECKREG r6, 0x000000D0; -CHECKREG r7, 0xFFFFFFE4; - -P1 = 12; -P2 = 14; -P3 = 16; -P4 = 18; -P5 = 20; -SP = 22; -FP = 24; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start11 , end11 ) LC1 = P1; -start11: R0 += 1; - R1 += -1; -LSETUP ( start15 , end15 ) LC0 = P5; -start15: R4 += 1; -end15: R5 += -1; - R3 += 1; -end11: R2 += 1; - R3 += 1; -LSETUP ( start13 , end13 ) LC1 = P3; -start13: R6 += 1; -LSETUP ( start12 , end12 ) LC0 = P2; -start12: R4 += 1; -end12: R5 += -1; - R3 += 1; -end13: R7 += -1; - R3 += 1; -CHECKREG r0, 0x00000011; -CHECKREG r1, 0x00000004; -CHECKREG r2, 0x0000002C; -CHECKREG r3, 0x0000004E; -CHECKREG r4, 0x00000210; -CHECKREG r5, 0xFFFFFE80; -CHECKREG r6, 0x00000070; -CHECKREG r7, 0x00000060; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start14 , end14 ) LC0 = P4; -start14: R0 += 1; - R1 += -1; -LSETUP ( start16 , end16 ) LC1 = SP; -start16: R6 += 1; -end16: R7 += -1; - R3 += 1; -LSETUP ( start17 , end17 ) LC1 = FP >> 1; -start17: R4 += 1; -end17: R5 += -1; - R3 += 1; -end14: R2 += 1; - R3 += 1; -CHECKREG r0, 0x00000017; -CHECKREG r1, 0xFFFFFFFE; -CHECKREG r2, 0x00000032; -CHECKREG r3, 0x00000055; -CHECKREG r4, 0x00000118; -CHECKREG r5, 0xFFFFFF78; -CHECKREG r6, 0x000001EC; -CHECKREG r7, 0xFFFFFEE4; - -pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_nested_bot.s b/sim/testsuite/sim/bfin/c_loopsetup_nested_bot.s deleted file mode 100644 index 118b6d2..0000000 --- a/sim/testsuite/sim/bfin/c_loopsetup_nested_bot.s +++ /dev/null @@ -1,165 +0,0 @@ -//Original:/testcases/core/c_loopsetup_nested_bot/c_loopsetup_nested_bot.dsp -// Spec Reference: loopsetup nested same bottom -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; -ASTAT = r0; - -//p0 = 2; -P1 = 2; -P2 = 4; -P3 = 6; -P4 = 8; -P5 = 10; -SP = 12; -FP = 14; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x32; -R4 = 0x46 (X); -R5 = 0x50 (X); -R6 = 0x68 (X); -R7 = 0x72 (X); -LSETUP ( start1 , end1 ) LC0 = P1; -start1: R0 += 1; - R1 += -2; -LSETUP ( start2 , end2 ) LC1 = P2; -start2: R4 += 4; -end2: R5 += -5; - R3 += 1; -end1: R2 += 3; - R3 += 4; -LSETUP ( start3 , end3 ) LC1 = P3; -start3: R6 += 6; -LSETUP ( start4 , end3 ) LC0 = P4 >> 1; -start4: R0 += 1; - R1 += -2; -end4: R2 += 3; - R3 += 4; -end3: R7 += -7; - R3 += 1; -CHECKREG r0, 0x00000010; -CHECKREG r1, 0xFFFFFFFA; -CHECKREG r2, 0x00000041; -CHECKREG r3, 0x0000005D; -CHECKREG r4, 0x00000066; -CHECKREG r5, 0x00000028; -CHECKREG r6, 0x0000008C; -CHECKREG r7, 0x00000033; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x14; -R3 = 0x18; -R4 = 0x20; -R5 = 0x12; -R6 = 0x24; -R7 = 0x16; -LSETUP ( start5 , end5 ) LC0 = P5; -start5: R4 += 1; -LSETUP ( start6 , end5 ) LC1 = SP >> 1; -start6: R6 += 4; -end6: R7 += -5; - R3 += 6; -end5: R5 += -2; - R3 += 3; -CHECKREG r0, 0x00000005; -CHECKREG r1, 0x00000010; -CHECKREG r2, 0x00000014; -CHECKREG r3, 0x00000183; -CHECKREG r4, 0x0000002A; -CHECKREG r5, 0xFFFFFF9A; -CHECKREG r6, 0x00000114; -CHECKREG r7, 0xFFFFFEEA; -LSETUP ( start7 , end7 ) LC0 = FP; -start7: R4 += 4; -end7: R5 += -5; - R3 += 6; -CHECKREG r0, 0x00000005; -CHECKREG r1, 0x00000010; -CHECKREG r2, 0x00000014; -CHECKREG r3, 0x00000189; -CHECKREG r4, 0x00000062; -CHECKREG r5, 0xFFFFFF54; -CHECKREG r6, 0x00000114; -CHECKREG r7, 0xFFFFFEEA; - -P1 = 04; -P2 = 08; -P3 = 10; -P4 = 12; -P5 = 14; -SP = 16; -FP = 18; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x12; -R3 = 0x20; -R4 = 0x18; -R5 = 0x14; -R6 = 0x16; -R7 = 0x28; -LSETUP ( start11 , end11 ) LC0 = P5; -start11: R0 += 1; - R1 += -1; -LSETUP ( start15 , end15 ) LC1 = P1; -start15: R4 += 1; -end15: R5 += -1; - R3 += 1; -end11: R2 += 1; - R3 += 1; -LSETUP ( start13 , end12 ) LC0 = P2; -start13: R6 += 1; -LSETUP ( start12 , end12 ) LC1 = P3; -start12: R4 += 1; -end12: R5 += -1; - R3 += 1; -end13: R7 += -1; - R3 += 1; -CHECKREG r0, 0x00000013; -CHECKREG r1, 0x00000002; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000031; -CHECKREG r4, 0x0000005A; -CHECKREG r5, 0xFFFFFFD2; -CHECKREG r6, 0x00000017; -CHECKREG r7, 0x00000027; - -R0 = 0x05; -R1 = 0x08; -R2 = 0x12; -R3 = 0x24; -R4 = 0x18; -R5 = 0x20; -R6 = 0x32; -R7 = 0x46 (X); -LSETUP ( start14 , end14 ) LC0 = P4; -start14: R0 += 1; - R1 += -1; -LSETUP ( start16 , end16 ) LC1 = SP; -start16: R6 += 1; -end16: R7 += -1; - R3 += 1; -LSETUP ( start17 , end14 ) LC1 = FP >> 1; -start17: R4 += 1; -end17: R5 += -1; - R3 += 1; -end14: R2 += 1; - R3 += 1; -CHECKREG r0, 0x00000011; -CHECKREG r1, 0xFFFFFFFC; -CHECKREG r2, 0x0000007E; -CHECKREG r3, 0x0000009D; -CHECKREG r4, 0x00000084; -CHECKREG r5, 0xFFFFFFB4; -CHECKREG r6, 0x000000F2; -CHECKREG r7, 0xFFFFFF86; - -pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s b/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s deleted file mode 100644 index f7de63c..0000000 --- a/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s +++ /dev/null @@ -1,184 +0,0 @@ -//Original:/testcases/core/c_loopsetup_nested_prelc/c_loopsetup_nested_prelc.dsp -// Spec Reference: loopsetup nested preload lc0 lc1 -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -ASTAT = r0; - -//p0 = 2; -P1 = 3; -P2 = 4; -P3 = 5; -P4 = 6; -P5 = 7; -SP = 8; -FP = 9; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x12; -R3 = 0x14; -R4 = 0x18; -R5 = 0x16; -R6 = 0x16; -R7 = 0x18; - -LC0 = R0; -LC1 = R1; -LSETUP ( start1 , end1 ) LC0; -start1: R0 += 1; - R1 += -2; -LSETUP ( start2 , end2 ) LC1; -start2: R4 += 4; -end2: R5 += -5; - R3 += 1; -end1: R2 += 3; - R3 += 4; -LC0 = R7; -LC1 = R6; -LSETUP ( start3 , end3 ) LC0; -start3: R6 += 6; -LSETUP ( start4 , end4 ) LC1; -start4: R0 += 1; - R1 += -2; -end4: R2 += 3; - R3 += 4; -end3: R7 += -7; - R3 += 1; -CHECKREG r0, 0x00000037; -CHECKREG r1, 0xFFFFFFAC; -CHECKREG r2, 0x000000A8; -CHECKREG r3, 0x0000007E; -CHECKREG r4, 0x00000068; -CHECKREG r5, 0xFFFFFFB2; -CHECKREG r6, 0x000000A6; -CHECKREG r7, 0xFFFFFF70; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x08; -R3 = 0x0C; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); - -LC0 = R2; -LC1 = R3; -LSETUP ( start5 , end5 ) LC0; -start5: R4 += 1; -LSETUP ( start6 , end6 ) LC1; -start6: R6 += 4; -end6: R7 += -5; - R3 += 6; -end5: R5 += -2; - R3 += 3; -CHECKREG r0, 0x00000005; -CHECKREG r1, 0x00000010; -CHECKREG r2, 0x00000008; -CHECKREG r3, 0x0000003F; -CHECKREG r4, 0x00000048; -CHECKREG r5, 0x00000040; -CHECKREG r6, 0x000000AC; -CHECKREG r7, 0x00000011; -LSETUP ( start7 , end7 ) LC0; -start7: R4 += 4; -end7: R5 += -5; - R3 += 6; -CHECKREG r0, 0x00000005; -CHECKREG r1, 0x00000010; -CHECKREG r2, 0x00000008; -CHECKREG r3, 0x00000045; -CHECKREG r4, 0x0000004C; -CHECKREG r5, 0x0000003B; -CHECKREG r6, 0x000000AC; -CHECKREG r7, 0x00000011; - -P1 = 12; -P2 = 14; -P3 = 16; -P4 = 18; -P5 = 12; -SP = 14; -FP = 16; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x14; -R3 = 0x18; -R4 = 0x16; -R5 = 0x04; -R6 = 0x30; -R7 = 0x30; - -LC0 = R5; -LC1 = R4; -LSETUP ( start11 , end11 ) LC0; -start11: R0 += 1; - R1 += -1; -LSETUP ( start15 , end15 ) LC1; -start15: R4 += 1; -end15: R5 += -1; - R3 += 1; -end11: R2 += 1; - R3 += 1; - - -LSETUP ( start13 , end13 ) LC0 = P5; -start13: R6 += 1; -LSETUP ( start12 , end12 ) LC1 = P2; -start12: R4 += 1; -end12: R5 += -1; - R3 += 1; -end13: R7 += -1; - R3 += 1; -CHECKREG r0, 0x00000009; -CHECKREG r1, 0x0000000C; -CHECKREG r2, 0x00000018; -CHECKREG r3, 0x0000002A; -CHECKREG r4, 0x000000D7; -CHECKREG r5, 0xFFFFFF43; -CHECKREG r6, 0x0000003C; -CHECKREG r7, 0x00000024; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x14; -R7 = 0x08; -P4 = 6; -FP = 8; - -LC0 = R6; -LC1 = R7; -LSETUP ( start14 , end14 ) LC0 = P4; -start14: R0 += 1; - R1 += -1; -LSETUP ( start16 , end16 ) LC1; -start16: R6 += 1; -end16: R7 += -1; - R3 += 1; -LSETUP ( start17 , end17 ) LC1 = FP >> 1; -start17: R4 += 1; -end17: R5 += -1; - R3 += 1; -end14: R2 += 1; - R3 += 1; -CHECKREG r0, 0x0000000B; -CHECKREG r1, 0x0000000A; -CHECKREG r2, 0x00000026; -CHECKREG r3, 0x0000003D; -CHECKREG r4, 0x00000058; -CHECKREG r5, 0x00000038; -CHECKREG r6, 0x00000021; -CHECKREG r7, 0xFFFFFFFB; - -pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_nested_top.s b/sim/testsuite/sim/bfin/c_loopsetup_nested_top.s deleted file mode 100644 index 54146a3..0000000 --- a/sim/testsuite/sim/bfin/c_loopsetup_nested_top.s +++ /dev/null @@ -1,166 +0,0 @@ -//Original:/testcases/core/c_loopsetup_nested_top/c_loopsetup_nested_top.dsp -// Spec Reference: loopsetup nested top -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -ASTAT = r0; - -//p0 = 2; -P1 = 3; -P2 = 4; -P3 = 5; -P4 = 6; -P5 = 7; -SP = 8; -FP = 9; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start1 , end1 ) LC0 = P1; -start1: R0 += 1; - R1 += -2; -LSETUP ( start2 , end2 ) LC1 = P2; -start2: R4 += 4; -end2: R5 += -5; - R3 += 1; -end1: R2 += 3; - R3 += 4; -LSETUP ( start3 , end3 ) LC1 = P3; -LSETUP ( start3 , end4 ) LC0 = P4; -start3: R6 += 6; - R0 += 1; - R1 += -2; -end4: R2 += 3; - R3 += 4; -end3: R7 += -7; - R3 += 1; -CHECKREG r0, 0x00000012; -CHECKREG r1, 0xFFFFFFF6; -CHECKREG r2, 0x00000047; -CHECKREG r3, 0x0000004C; -CHECKREG r4, 0x00000070; -CHECKREG r5, 0x00000014; -CHECKREG r6, 0x0000009C; -CHECKREG r7, 0x0000004D; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start5 , end5 ) LC0 = P5; -LSETUP ( start5 , end6 ) LC1 = SP >> 1; -start5: R4 += 1; - R6 += 4; -end6: R7 += -5; - R3 += 6; -end5: R5 += -2; - R3 += 3; -CHECKREG r0, 0x00000005; -CHECKREG r1, 0x00000010; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x0000005D; -CHECKREG r4, 0x0000004A; -CHECKREG r5, 0x00000042; -CHECKREG r6, 0x00000088; -CHECKREG r7, 0x0000003E; -LSETUP ( start7 , end7 ) LC0 = FP; -start7: R4 += 4; -end7: R5 += -5; - R3 += 6; -CHECKREG r0, 0x00000005; -CHECKREG r1, 0x00000010; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000063; -CHECKREG r4, 0x0000006E; -CHECKREG r5, 0x00000015; -CHECKREG r6, 0x00000088; -CHECKREG r7, 0x0000003E; - -P1 = 8; -P2 = 10; -P3 = 12; -P4 = 14; -P5 = 16; -SP = 18; -FP = 20; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start11 , end11 ) LC1 = P1 >> 1; -LSETUP ( start11 , end15 ) LC0 = P5; -start11: R0 += 1; - R1 += -1; - R4 += 1; -end15: R5 += -1; - R3 += 1; -end11: R2 += 1; - R3 += 1; -LSETUP ( start12 , end12 ) LC1 = P3 >> 1; -LSETUP ( start12 , end13 ) LC0 = P2 >> 1; -start12: R6 += 1; - R4 += 1; -end13: R5 += -1; - R3 += 1; -end12: R7 += -1; - R3 += 1; -CHECKREG r0, 0x00000018; -CHECKREG r1, 0xFFFFFFFD; -CHECKREG r2, 0x00000024; -CHECKREG r3, 0x0000003C; -CHECKREG r4, 0x0000005D; -CHECKREG r5, 0x00000033; -CHECKREG r6, 0x0000006A; -CHECKREG r7, 0x0000006A; - -R0 = 0x04; -R1 = 0x06; -R2 = 0x08; -R3 = 0x10; -R4 = 0x12; -R5 = 0x14; -R6 = 0x16; -R7 = 0x18; -LSETUP ( start14 , end14 ) LC0 = P4; -LSETUP ( start14 , end16 ) LC1 = SP >> 1; -start14: R0 += 1; - R1 += -1; - R6 += 1; -end16: R7 += -1; - R3 += 1; -LSETUP ( start17 , end17 ) LC1 = FP >> 1; -start17: R4 += 1; -end17: R5 += -1; - R3 += 1; -end14: R2 += 1; - R3 += 1; -CHECKREG r0, 0x0000001A; -CHECKREG r1, 0xFFFFFFF0; -CHECKREG r2, 0x00000016; -CHECKREG r3, 0x0000002D; -CHECKREG r4, 0x0000009E; -CHECKREG r5, 0xFFFFFF88; -CHECKREG r6, 0x0000002C; -CHECKREG r7, 0x00000002; - -pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_overlap.s b/sim/testsuite/sim/bfin/c_loopsetup_overlap.s deleted file mode 100644 index ff3b343..0000000 --- a/sim/testsuite/sim/bfin/c_loopsetup_overlap.s +++ /dev/null @@ -1,167 +0,0 @@ -//Original:/testcases/core/c_loopsetup_overlap/c_loopsetup_overlap.dsp -// Spec Reference: loopsetup overlap -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -ASTAT = r0; - -//p0 = 2; -P1 = 3; -P2 = 4; -P3 = 5; -P4 = 6; -P5 = 7; -SP = 8; -FP = 9; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start1 , end1 ) LC0 = P1; -start1: R0 += 1; - R1 += -2; -LSETUP ( start2 , end2 ) LC1 = P2; -start2: R4 += 4; -end2: R5 += -5; - R3 += 1; -end1: R2 += 3; - R3 += 4; - -LSETUP ( start3 , end3 ) LC1 = P3; -start3: R6 += 6; -LSETUP ( start4 , end4 ) LC0 = P4 >> 1; -start4: R0 += 1; - R1 += -2; -end3: R2 += 3; - R3 += 4; -end4: R7 += -7; - R3 += 1; -CHECKREG r0, 0x0000000F; -CHECKREG r1, 0xFFFFFFFC; -CHECKREG r2, 0x0000003E; -CHECKREG r3, 0x00000044; -CHECKREG r4, 0x00000070; -CHECKREG r5, 0x00000014; -CHECKREG r6, 0x0000007E; -CHECKREG r7, 0x0000005B; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start5 , end5 ) LC0 = P5; -start5: R4 += 1; -LSETUP ( start6 , end6 ) LC1 = SP >> 1; -start6: R6 += 4; -end5: R7 += -5; - R3 += 6; -end6: R5 += -2; - R3 += 3; -CHECKREG r0, 0x00000005; -CHECKREG r1, 0x00000010; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x0000004B; -CHECKREG r4, 0x00000047; -CHECKREG r5, 0x00000048; -CHECKREG r6, 0x00000088; -CHECKREG r7, 0x0000003E; -LSETUP ( start7 , end7 ) LC0 = FP; -start7: R4 += 4; -end7: R5 += -5; - R3 += 6; -CHECKREG r0, 0x00000005; -CHECKREG r1, 0x00000010; -CHECKREG r2, 0x00000020; -CHECKREG r3, 0x00000051; -CHECKREG r4, 0x0000006B; -CHECKREG r5, 0x0000001B; -CHECKREG r6, 0x00000088; -CHECKREG r7, 0x0000003E; - -P1 = 8; -P2 = 10; -P3 = 12; -P4 = 14; -P5 = 16; -SP = 18; -FP = 20; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start11 , end11 ) LC1 = P1; -start11: R0 += 1; - R1 += -1; -LSETUP ( start15 , end15 ) LC0 = P5; -start15: R4 += 5; -end11: R5 += -14; - R3 += 1; -end15: R2 += 17; - R3 += 12; -LSETUP ( start13 , end13 ) LC1 = P3; -start13: R6 += 1; -LSETUP ( start12 , end12 ) LC0 = P2; -start12: R4 += 22; -end13: R5 += -11; - R3 += 13; -end12: R7 += -1; - R3 += 14; -CHECKREG r0, 0x0000000D; -CHECKREG r1, 0x00000008; -CHECKREG r2, 0x00000130; -CHECKREG r3, 0x000000DC; -CHECKREG r4, 0x00000281; -CHECKREG r5, 0xFFFFFE27; -CHECKREG r6, 0x0000006C; -CHECKREG r7, 0x00000066; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start14 , end14 ) LC0 = P4; -start14: R0 += 21; - R1 += -11; -LSETUP ( start16 , end16 ) LC1 = SP; -start16: R6 += 10; -end16: R7 += -12; - R3 += 1; -LSETUP ( start17 , end17 ) LC1 = FP >> 1; -start17: R4 += 31; -end14: R5 += -1; - R3 += 11; -end17: R2 += 41; - R3 += 1; -CHECKREG r0, 0x0000012B; -CHECKREG r1, 0xFFFFFF76; -CHECKREG r2, 0x000001BA; -CHECKREG r3, 0x000000AD; -CHECKREG r4, 0x00000309; -CHECKREG r5, 0x00000039; -CHECKREG r6, 0x00000A38; -CHECKREG r7, 0xFFFFF4A0; - -pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc0.s b/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc0.s deleted file mode 100644 index b147659..0000000 --- a/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc0.s +++ /dev/null @@ -1,95 +0,0 @@ -//Original:/testcases/core/c_loopsetup_preg_div2_lc0/c_loopsetup_preg_div2_lc0.dsp -// Spec Reference: loopsetup preg lc0 / 2 -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -ASTAT = r0; - -P5 = 20; -P1 = 30; -P2 = 40; -P3 = 50; -P4 = 60; -//p5 = 7; -SP = 80 (X); -FP = 90 (X); - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start1 , end1 ) LC0 = P1 >> 1; -start1: R0 += 1; - R1 += -2; -end1: R2 += 3; - R3 += 4; -LSETUP ( start2 , end2 ) LC0 = P2 >> 1; -start2: R4 += 4; -end2: R5 += -5; - R3 += 1; -LSETUP ( start3 , end3 ) LC0 = P3 >> 1; -start3: R6 += 6; -end3: R7 += -7; - R3 += 1; -CHECKREG r0, 0x00000014; -CHECKREG r1, 0xFFFFFFF2; -CHECKREG r2, 0x0000004D; -CHECKREG r3, 0x00000036; -CHECKREG r4, 0x00000090; -CHECKREG r5, 0xFFFFFFEC; -CHECKREG r6, 0x000000F6; -CHECKREG r7, 0xFFFFFFC1; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start4 , end4 ) LC0 = P4 >> 1; -start4: R0 += 1; - R1 += -2; -end4: R2 += 3; - R3 += 4; -LSETUP ( start5 , end5 ) LC0 = P5 >> 1; -start5: R4 += 1; -end5: R5 += -2; - R3 += 3; -LSETUP ( start6 , end6 ) LC0 = SP >> 1; -start6: R6 += 4; -end6: R7 += -5; - R3 += 6; -CHECKREG r0, 0x00000023; -CHECKREG r1, 0xFFFFFFD4; -CHECKREG r2, 0x0000007A; -CHECKREG r3, 0x0000003D; -CHECKREG r4, 0x0000004A; -CHECKREG r5, 0x0000003C; -CHECKREG r6, 0x00000100; -CHECKREG r7, 0xFFFFFFA8; -LSETUP ( start7 , end7 ) LC0 = FP >> 1; -start7: R4 += 4; -end7: R5 += -5; - R3 += 6; -CHECKREG r0, 0x00000023; -CHECKREG r1, 0xFFFFFFD4; -CHECKREG r2, 0x0000007A; -CHECKREG r3, 0x00000043; -CHECKREG r4, 0x000000FE; -CHECKREG r5, 0xFFFFFF5B; -CHECKREG r6, 0x00000100; -CHECKREG r7, 0xFFFFFFA8; - - -pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc1.s b/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc1.s deleted file mode 100644 index 73c7aa0..0000000 --- a/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc1.s +++ /dev/null @@ -1,94 +0,0 @@ -//Original:/testcases/core/c_loopsetup_preg_div2_lc1/c_loopsetup_preg_div2_lc1.dsp -// Spec Reference: loopsetup preg lc1 / 2 -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -ASTAT = r0; - - -P1 = 12; -P2 = 14; -P3 = 16; -P4 = 18; -P5 = 20; -SP = 22; -FP = 24; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start11 , end11 ) LC1 = P1 >> 1; -start11: R0 += 1; - R1 += -1; -end11: R2 += 1; - R3 += 1; -LSETUP ( start12 , end12 ) LC1 = P2 >> 1; -start12: R4 += 1; -end12: R5 += -1; - R3 += 1; -LSETUP ( start13 , end13 ) LC1 = P3 >> 1; -start13: R6 += 1; -end13: R7 += -1; - R3 += 1; -CHECKREG r0, 0x0000000B; -CHECKREG r1, 0x0000000A; -CHECKREG r2, 0x00000026; -CHECKREG r3, 0x00000033; -CHECKREG r4, 0x00000047; -CHECKREG r5, 0x00000049; -CHECKREG r6, 0x00000068; -CHECKREG r7, 0x00000068; - -R0 = 0x06; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start14 , end14 ) LC1 = P4 >> 1; -start14: R0 += 1; - R1 += -1; -end14: R2 += 1; - R3 += 1; -LSETUP ( start15 , end15 ) LC1 = P5 >> 1; -start15: R4 += 1; -end15: R5 += -1; - R3 += 1; -LSETUP ( start16 , end16 ) LC1 = SP >> 1; -start16: R6 += 1; -end16: R7 += -1; - R3 += 1; -CHECKREG r0, 0x0000000F; -CHECKREG r1, 0x00000007; -CHECKREG r2, 0x00000029; -CHECKREG r3, 0x00000033; -CHECKREG r4, 0x0000004A; -CHECKREG r5, 0x00000046; -CHECKREG r6, 0x0000006B; -CHECKREG r7, 0x00000065; -LSETUP ( start17 , end17 ) LC1 = FP >> 1; -start17: R4 += 1; -end17: R5 += -1; - R3 += 1; -CHECKREG r0, 0x0000000F; -CHECKREG r1, 0x00000007; -CHECKREG r2, 0x00000029; -CHECKREG r3, 0x00000034; -CHECKREG r4, 0x00000056; -CHECKREG r5, 0x0000003A; -CHECKREG r6, 0x0000006B; -CHECKREG r7, 0x00000065; - -pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_preg_lc0.s b/sim/testsuite/sim/bfin/c_loopsetup_preg_lc0.s deleted file mode 100644 index 4429b1e..0000000 --- a/sim/testsuite/sim/bfin/c_loopsetup_preg_lc0.s +++ /dev/null @@ -1,95 +0,0 @@ -//Original:/testcases/core/c_loopsetup_preg_lc0/c_loopsetup_preg_lc0.dsp -// Spec Reference: loopsetup preg lc0 -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -ASTAT = r0; - -//p0 = 2; -P1 = 3; -P2 = 4; -P3 = 5; -P4 = 6; -P5 = 7; -SP = 8; -FP = 9; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start1 , end1 ) LC0 = P1; -start1: R0 += 1; - R1 += -2; -end1: R2 += 3; - R3 += 4; -LSETUP ( start2 , end2 ) LC0 = P2; -start2: R4 += 4; -end2: R5 += -5; - R3 += 1; -LSETUP ( start3 , end3 ) LC0 = P3; -start3: R6 += 6; -end3: R7 += -7; - R3 += 1; -CHECKREG r0, 0x00000008; -CHECKREG r1, 0x0000000A; -CHECKREG r2, 0x00000029; -CHECKREG r3, 0x00000036; -CHECKREG r4, 0x00000050; -CHECKREG r5, 0x0000003C; -CHECKREG r6, 0x0000007E; -CHECKREG r7, 0x0000004D; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start4 , end4 ) LC0 = P4; -start4: R0 += 1; - R1 += -2; -end4: R2 += 3; - R3 += 4; -LSETUP ( start5 , end5 ) LC0 = P5; -start5: R4 += 1; -end5: R5 += -2; - R3 += 3; -LSETUP ( start6 , end6 ) LC0 = SP; -start6: R6 += 4; -end6: R7 += -5; - R3 += 6; -CHECKREG r0, 0x0000000B; -CHECKREG r1, 0x00000004; -CHECKREG r2, 0x00000032; -CHECKREG r3, 0x0000003D; -CHECKREG r4, 0x00000047; -CHECKREG r5, 0x00000042; -CHECKREG r6, 0x00000080; -CHECKREG r7, 0x00000048; -LSETUP ( start7 , end7 ) LC0 = FP; -start7: R4 += 4; -end7: R5 += -5; - R3 += 6; -CHECKREG r0, 0x0000000B; -CHECKREG r1, 0x00000004; -CHECKREG r2, 0x00000032; -CHECKREG r3, 0x00000043; -CHECKREG r4, 0x0000006B; -CHECKREG r5, 0x00000015; -CHECKREG r6, 0x00000080; -CHECKREG r7, 0x00000048; - - -pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_preg_lc1.s b/sim/testsuite/sim/bfin/c_loopsetup_preg_lc1.s deleted file mode 100644 index 8970f40..0000000 --- a/sim/testsuite/sim/bfin/c_loopsetup_preg_lc1.s +++ /dev/null @@ -1,93 +0,0 @@ -//Original:/testcases/core/c_loopsetup_preg_lc1/c_loopsetup_preg_lc1.dsp -// Spec Reference: loopsetup preg lc1 -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -ASTAT = r0; - -P1 = 12; -P2 = 14; -P3 = 16; -P4 = 18; -P5 = 20; -SP = 22; -FP = 24; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start11 , end11 ) LC1 = P1; -start11: R0 += 1; - R1 += -1; -end11: R2 += 1; - R3 += 1; -LSETUP ( start12 , end12 ) LC1 = P2; -start12: R4 += 1; -end12: R5 += -1; - R3 += 1; -LSETUP ( start13 , end13 ) LC1 = P3; -start13: R6 += 1; -end13: R7 += -1; - R3 += 1; -CHECKREG r0, 0x00000011; -CHECKREG r1, 0x00000004; -CHECKREG r2, 0x0000002C; -CHECKREG r3, 0x00000033; -CHECKREG r4, 0x0000004E; -CHECKREG r5, 0x00000042; -CHECKREG r6, 0x00000070; -CHECKREG r7, 0x00000060; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); -LSETUP ( start14 , end14 ) LC1 = P4; -start14: R0 += 1; - R1 += -1; -end14: R2 += 1; - R3 += 1; -LSETUP ( start15 , end15 ) LC1 = P5; -start15: R4 += 1; -end15: R5 += -1; - R3 += 1; -LSETUP ( start16 , end16 ) LC1 = SP; -start16: R6 += 1; -end16: R7 += -1; - R3 += 1; -CHECKREG r0, 0x00000017; -CHECKREG r1, 0xFFFFFFFE; -CHECKREG r2, 0x00000032; -CHECKREG r3, 0x00000033; -CHECKREG r4, 0x00000054; -CHECKREG r5, 0x0000003c; -CHECKREG r6, 0x00000076; -CHECKREG r7, 0x0000005A; -LSETUP ( start17 , end17 ) LC1 = FP; -start17: R4 += 1; -end17: R5 += -1; - R3 += 1; -CHECKREG r0, 0x00000017; -CHECKREG r1, 0xFFFFFFFE; -CHECKREG r2, 0x00000032; -CHECKREG r3, 0x00000034; -CHECKREG r4, 0x0000006c; -CHECKREG r5, 0x00000024; -CHECKREG r6, 0x00000076; -CHECKREG r7, 0x0000005A; - -pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_preg_stld.s b/sim/testsuite/sim/bfin/c_loopsetup_preg_stld.s deleted file mode 100644 index ab549a6..0000000 --- a/sim/testsuite/sim/bfin/c_loopsetup_preg_stld.s +++ /dev/null @@ -1,194 +0,0 @@ -//Original:/testcases/core/c_loopsetup_preg_stld/c_loopsetup_preg_stld.dsp -// Spec Reference: loopsetup preg st & ld -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - A0 = 0; - A1 = 0; - ASTAT = r0; - - P1 = 9; - P2 = 8; - P0 = 7; - P4 = 6; - P5 = 5; - FP = 3; - - imm32 r0, 0x00200005; - imm32 r1, 0x00300010; - imm32 r2, 0x00500012; - imm32 r3, 0x00600024; - imm32 r4, 0x00700016; - imm32 r5, 0x00900028; - imm32 r6, 0x0a000030; - imm32 r7, 0x00b00044; - - loadsym I0, DATA0; - loadsym I1, DATA1; - R0 = [ I0 ++ ]; - R1 = [ I1 ++ ]; - LSETUP ( start1 , end1 ) LC0 = P1; -start1: - R0 += 1; - R1 += 2; - A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; -end1: - R2 += 3; - - R3 = ( A0 += A1 ); - - A0 = 0; - A1 = 0; - LSETUP ( start2 , end2 ) LC0 = P2; -start2: - R4 += 4; - A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 -- ] || R1 = [ I1 -- ]; -end2: - R5 += -5; - R6 = ( A0 += A1 ); - CHECKREG r0, 0x000D0003; - CHECKREG r1, 0x00C00103; - CHECKREG r2, 0x0050002D; - CHECKREG r3, 0x00010794; - CHECKREG r4, 0x00700036; - CHECKREG r5, 0x00900000; - CHECKREG r6, 0x00011388; - CHECKREG r7, 0x00B00044; - - imm32 r0, 0x01200805; - imm32 r1, 0x02300710; - imm32 r2, 0x03500612; - imm32 r3, 0x04600524; - imm32 r4, 0x05700416; - imm32 r5, 0x06900328; - imm32 r6, 0x0a700230; - imm32 r7, 0x08b00044; - - loadsym I2, DATA0; - loadsym I3, DATA1; - [ I2 ++ ] = R0; - [ I3 ++ ] = R1; - LSETUP ( start3 , end3 ) LC0 = P1; -start3: - [ I2 ++ ] = R2; - [ I3 ++ ] = R3; - R2 += 1; -end3: - R3 += 1; - - A0 = 0; - A1 = 0; - LSETUP ( start4 , end4 ) LC0 = P2; - R0 = [ I0 -- ]; - R1 = [ I1 -- ]; -start4: - A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I2 -- ] || R1 = [ I3 -- ]; - R4 = R4 + R0; // comp3op -end4: - R5 = R5 + R1; - - R6 = ( A0 += A1 ); - CHECKREG r0, 0x03500614; - CHECKREG r1, 0x04600526; - CHECKREG r2, 0x0350061B; - CHECKREG r3, 0x0460052D; - CHECKREG r4, 0x1CF02EC1; - CHECKREG r5, 0x25602851; - CHECKREG r6, 0x0282F220; - CHECKREG r7, 0x08B00044; - - pass - - .data -DATA0: - .dd 0x000a0000 - .dd 0x000b0001 - .dd 0x000c0002 - .dd 0x000d0003 - .dd 0x000e0004 - .dd 0x000f0005 - .dd 0x00100006 - .dd 0x00200007 - .dd 0x00300008 - .dd 0x00400009 - .dd 0x0050000a - .dd 0x0060000b - .dd 0x0070000c - .dd 0x0080000d - .dd 0x0090000e - .dd 0x0100000f - .dd 0x02000010 - .dd 0x03000011 - .dd 0x04000012 - .dd 0x05000013 - .dd 0x06000014 - .dd 0x001a0000 - .dd 0x001b0001 - .dd 0x001c0002 - .dd 0x001d0003 - .dd 0x00010004 - .dd 0x00010005 - .dd 0x02100006 - .dd 0x02200007 - .dd 0x02300008 - .dd 0x02200009 - .dd 0x0250000a - .dd 0x0260000b - .dd 0x0270000c - .dd 0x0280000d - .dd 0x0290000e - .dd 0x2100000f - .dd 0x22000010 - .dd 0x22000011 - .dd 0x24000012 - .dd 0x25000013 - .dd 0x26000014 - -DATA1: - .dd 0x00f00100 - .dd 0x00e00101 - .dd 0x00d00102 - .dd 0x00c00103 - .dd 0x00b00104 - .dd 0x00a00105 - .dd 0x00900106 - .dd 0x00800107 - .dd 0x00100108 - .dd 0x00200109 - .dd 0x0030010a - .dd 0x0040010b - .dd 0x0050011c - .dd 0x0060010d - .dd 0x0070010e - .dd 0x0080010f - .dd 0x00900110 - .dd 0x01000111 - .dd 0x02000112 - .dd 0x03000113 - .dd 0x04000114 - .dd 0x05000115 - .dd 0x03f00100 - .dd 0x03e00101 - .dd 0x03d00102 - .dd 0x03c00103 - .dd 0x03b00104 - .dd 0x03a00105 - .dd 0x03900106 - .dd 0x03800107 - .dd 0x03100108 - .dd 0x03200109 - .dd 0x0330010a - .dd 0x0330010b - .dd 0x0350011c - .dd 0x0360010d - .dd 0x0370010e - .dd 0x0380010f - .dd 0x03900110 - .dd 0x31000111 - .dd 0x32000112 - .dd 0x33000113 - .dd 0x34000114 diff --git a/sim/testsuite/sim/bfin/c_loopsetup_prelc.s b/sim/testsuite/sim/bfin/c_loopsetup_prelc.s deleted file mode 100644 index 527988a..0000000 --- a/sim/testsuite/sim/bfin/c_loopsetup_prelc.s +++ /dev/null @@ -1,145 +0,0 @@ -//Original:/testcases/core/c_loopsetup_prelc/c_loopsetup_prelc.dsp -// Spec Reference: loopsetup preload lc0 lc1 -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -ASTAT = r0; - -//p0 = 2; -P1 = 3; -P2 = 4; -P3 = 5; -P4 = 6; -P5 = 7; -SP = 8; -FP = 9; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); - -LC0 = R0; -LC1 = R1; - -LSETUP ( start1 , end1 ) LC0; -start1: R0 += 1; - R1 += -2; -end1: R2 += 3; - R3 += 4; -LSETUP ( start2 , end2 ) LC1; -start2: R4 += 4; -end2: R5 += -5; - R3 += 1; -LSETUP ( start3 , end3 ) LC0 = P3; -start3: R6 += 6; -end3: R7 += -7; - R3 += 1; -CHECKREG r0, 0x0000000a; -CHECKREG r1, 0x00000006; -CHECKREG r2, 0x0000002f; -CHECKREG r3, 0x00000036; -CHECKREG r4, 0x00000080; -CHECKREG r5, 0x00000000; -CHECKREG r6, 0x0000007E; -CHECKREG r7, 0x0000004D; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x60 (X); -R7 = 0x70 (X); - -LC0 = R2; -LC1 = R3; - -LSETUP ( start4 , end4 ) LC0; -start4: R0 += 1; - R1 += -2; -end4: R2 += 3; - R3 += 4; -LSETUP ( start5 , end5 ) LC1; -start5: R4 += 1; -end5: R5 += -2; - R3 += 3; - -LSETUP ( start6 , end6 ) LC0 = P2; -start6: R6 += 4; -end6: R7 += -5; - R3 += 6; -CHECKREG r0, 0x00000025; -CHECKREG r1, 0xFFFFFFD0; -CHECKREG r2, 0x00000080; -CHECKREG r3, 0x0000003D; -CHECKREG r4, 0x00000070; -CHECKREG r5, 0xFFFFFFF0; -CHECKREG r6, 0x00000070; -CHECKREG r7, 0x0000005C; -LSETUP ( start7 , end7 ) LC1; -start7: R4 += 4; -end7: R5 += -5; - R3 += 6; -CHECKREG r0, 0x00000025; -CHECKREG r1, 0xFFFFFFD0; -CHECKREG r2, 0x00000080; -CHECKREG r3, 0x00000043; -CHECKREG r4, 0x00000074; -CHECKREG r5, 0xFFFFFFEB; -CHECKREG r6, 0x00000070; -CHECKREG r7, 0x0000005C; - -P1 = 12; -P2 = 14; -P3 = 16; -P4 = 18; -P5 = 20; -SP = 22; -FP = 24; - -R0 = 0x05; -R1 = 0x10; -R2 = 0x20; -R3 = 0x30; -R4 = 0x40 (X); -R5 = 0x50 (X); -R6 = 0x25; -R7 = 0x32; - -LC0 = R6; -LC1 = R7; -LSETUP ( start11 , end11 ) LC0; -start11: R0 += 1; - R1 += -1; -end11: R2 += 1; - R3 += 1; -LSETUP ( start12 , end12 ) LC1; -start12: R4 += 1; -end12: R5 += -1; - R3 += 1; -LSETUP ( start13 , end13 ) LC1 = P4; -start13: R6 += 1; -end13: R7 += -1; - R3 += 1; -CHECKREG r0, 0x0000002A; -CHECKREG r1, 0xFFFFFFEB; -CHECKREG r2, 0x00000045; -CHECKREG r3, 0x00000033; -CHECKREG r4, 0x00000072; -CHECKREG r5, 0x0000001E; -CHECKREG r6, 0x00000037; -CHECKREG r7, 0x00000020; - - -pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_topbotcntr.s b/sim/testsuite/sim/bfin/c_loopsetup_topbotcntr.s deleted file mode 100644 index dc19b7d..0000000 --- a/sim/testsuite/sim/bfin/c_loopsetup_topbotcntr.s +++ /dev/null @@ -1,110 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_loopsetup_topbotcntr/c_loopsetup_topbotcntr.dsp -// Spec Reference: loopsetup top bot counter -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - - ASTAT = r0; - - R1 = 0x10; - R2 = 0x20; - R3 = 0x30; - R4 = 0x40 (X); - R5 = 0x08; - - loadsym R6, start1; - loadsym R7, end1; - - LT0 = R6; - LB0 = R7; - LC0 = R5; -//start immmediately -start1: R0 += 1; - R1 += -2; -end1: R2 += 3; - R3 += 4; - - CHECKREG r0, 0x00000008; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000038; - CHECKREG r3, 0x00000034; - CHECKREG r4, 0x00000040; - CHECKREG r5, 0x00000008; -//CHECKREG r6, 0x00000090; -//CHECKREG r7, 0x00000094; - - R0 = 0x05; - R1 = 0x10; - R2 = 0x10; - R3 = 0x10; - R4 = 0x20; - R5 = 0x20; - R6 = 0x30; - R7 = 0x30; - - loadsym R1, start2; - R0 = R1; - loadsym R1, end2; - LT1 = R0; - LB1 = R1; - LC1 = R2; - -start2: R4 += 1; - R5 += 2; -end2: R6 += -3; - R7 += 4; - CHECKREG r3, 0x00000010; - CHECKREG r4, 0x00000030; - CHECKREG r5, 0x00000040; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000034; - - R0 = 0x05; - R1 = 0x10; - R2 = 0x20; - R3 = 0x30; - R4 = 0x40 (X); - R5 = 0x50 (X); - R6 = 0x60 (X); - R7 = 0x70 (X); - - loadsym R1, start3 - r0 = r1; - loadsym r1, end3; - LT0 = R0; - LB0 = R1; - LC0 = R2; - loadsym r3, start4; - loadsym r4, end4; - LT1 = R3; - LB1 = R4; - LC1 = R5; - - R0 = 0x10; - R1 = 0x15; - R2 = 0x20; - R3 = 0x26; - R4 = 0x30; - R5 = 0x40 (X); - -start3: R0 += 1; - R1 += -2; -start4: R2 += 3; - R3 += 4; -end4: R6 += 5; -end3: R7 += -6; - - CHECKREG r0, 0x00000030; - CHECKREG r1, 0xFFFFFFD5; - CHECKREG r2, 0x0000016D; - CHECKREG r3, 0x000001E2; - CHECKREG r4, 0x00000030; - CHECKREG r5, 0x00000040; - CHECKREG r6, 0x0000028B; - CHECKREG r7, 0xFFFFFFB0; - - pass diff --git a/sim/testsuite/sim/bfin/c_mmr_interr_ctl.s b/sim/testsuite/sim/bfin/c_mmr_interr_ctl.s deleted file mode 100644 index ad4d88b..0000000 --- a/sim/testsuite/sim/bfin/c_mmr_interr_ctl.s +++ /dev/null @@ -1,398 +0,0 @@ -# Blackfin testcase for the CEC -# mach: bfin -# sim: --environment operating - - .include "testutils.inc" - - start - - INIT_R_REGS 0; - INIT_P_REGS 0; - INIT_I_REGS 0; - INIT_M_REGS 0; - INIT_L_REGS 0; - INIT_B_REGS 0; - - CLI R1; // inhibit events during MMR writes - - loadsym sp, USTACK; // setup the user stack pointer - usp = sp; // and frame pointer - - loadsym sp, KSTACK; // setup the stack pointer - fp = sp; // and frame pointer - - imm32 p0, 0xFFE02000; - loadsym r0, EHANDLE; // Emulation Handler (Int0) - [p0++] = r0; - - loadsym r0, RHANDLE; // Reset Handler (Int1) - [p0++] = r0; - - loadsym r0, NHANDLE; // NMI Handler (Int2) - [p0++] = r0; - - loadsym r0, XHANDLE; // Exception Handler (Int3) - [p0++] = r0; - - [p0++] = r0; // EVT4 not used global Interr Enable (INT4) - - loadsym r0, HWHANDLE; // HW Error Handler (Int5) - [p0++] = r0; - - loadsym r0, THANDLE; // Timer Handler (Int6) - [p0++] = r0; - - loadsym r0, I7HANDLE; // IVG7 Handler - [p0++] = r0; - - loadsym r0, I8HANDLE; // IVG8 Handler - [p0++] = r0; - - loadsym r0, I9HANDLE; // IVG9 Handler - [p0++] = r0; - - loadsym r0, I10HANDLE;// IVG10 Handler - [p0++] = r0; - - loadsym r0, I11HANDLE;// IVG11 Handler - [p0++] = r0; - - loadsym r0, I12HANDLE;// IVG12 Handler - [p0++] = r0; - - loadsym r0, I13HANDLE;// IVG13 Handler - [p0++] = r0; - - loadsym r0, I14HANDLE;// IVG14 Handler - [p0++] = r0; - - loadsym r0, I15HANDLE;// IVG15 Handler - [p0++] = r0; - - imm32 p0, 0xFFE02100 // EVT_OVERRIDE - r0 = 0; - [p0++] = r0; - - r1 = -1; // Change this to mask interrupts (*) - csync; // wait for MMR writes to finish - sti r1; // sync and reenable events (implicit write to IMASK) - - imm32 p0, 0xFFE02104; - r0 = [p0]; - // ckeck that sti allows the lower 5 bits of imask to be written - CHECKREG r0, 0xffff; - -DUMMY: - - r0 = 0 (z); - - LT0 = r0; // set loop counters to something deterministic - LB0 = r0; - LC0 = r0; - LT1 = r0; - LB1 = r0; - LC1 = r0; - - ASTAT = r0; // reset other internal regs - SYSCFG = r0; - RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - - loadsym r0, STARTUSER;// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) - RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - - JUMP STARTSUP; // jump to code start for SUPERVISOR mode - - RTI; - -STARTSUP: - loadsym p1, BEGIN; - - imm32 p0, (0xFFE02000 + 4 * 15); - - CLI R1; // inhibit events during write to MMR - [p0] = p1; // IVG15 (General) handler (Int 15) load with start - csync; // wait for it - sti r1; // reenable events with proper imask - - RAISE 15; // after we RTI, INT 15 should be taken - - RTI; - -// -// The Main Program -// -STARTUSER: - LINK 0; // change for how much stack frame space you need. - - JUMP BEGIN; - -// ********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [--sp] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** -// EVTx - // wrt-rd EVT0: 0 bits, rw=0 = 0xFFE02000 - imm32 p0, 0xFFE02000; - imm32 r0, 0x00000000 - [p0] = r0; - - // wrt-rd EVT1: 32 bits, rw=0 = 0xFFE02004 - imm32 p0, 0xFFE02004; - imm32 r0, 0x00000000 - [p0] = r0; - - // wrt-rd EVT2 = 0xFFE02008 - imm32 p0, 0xFFE02008 - imm32 r0, 0xE1DE5D1C - [p0] = r0; - - // wrt-rd EVT3 = 0xFFE0200C - imm32 p0, 0xFFE0200C - imm32 r0, 0x9CC20332 - [p0] = r0; - - // wrt-rd EVT4 = 0xFFE02010 - imm32 p0, 0xFFE02010 - imm32 r0, 0x00000000 - [p0] = r0; - - // wrt-rd EVT5 = 0xFFE02014 - imm32 p0, 0xFFE02014 - imm32 r0, 0x55552345 - [p0] = r0; - - // wrt-rd EVT6 = 0xFFE02018 - imm32 p0, 0xFFE02018 - imm32 r0, 0x66663456 - [p0] = r0; - - // wrt-rd EVT7 = 0xFFE0201C - imm32 p0, 0xFFE0201C - imm32 r0, 0x77774567 - [p0] = r0; - - // wrt-rd EVT8 = 0xFFE02020 - imm32 p0, 0xFFE02020 - imm32 r0, 0x88885678 - [p0] = r0; - - // wrt-rd EVT9 = 0xFFE02024 - imm32 p0, 0xFFE02024 - imm32 r0, 0x99996789 - [p0] = r0; - - // wrt-rd EVT10 = 0xFFE02028 - imm32 p0, 0xFFE02028 - imm32 r0, 0xaaaa1234 - [p0] = r0; - - // wrt-rd EVT11 = 0xFFE0202C - imm32 p0, 0xFFE0202C - imm32 r0, 0xBBBBABC6 - [p0] = r0; - - // wrt-rd EVT12 = 0xFFE02030 - imm32 p0, 0xFFE02030 - imm32 r0, 0xCCCCABC6 - [p0] = r0; - - // wrt-rd EVT13 = 0xFFE02034 - imm32 p0, 0xFFE02034 - imm32 r0, 0xDDDDABC6 - [p0] = r0; - - // wrt-rd EVT14 = 0xFFE02038 - imm32 p0, 0xFFE02038 - imm32 r0, 0xEEEEABC6 - [p0] = r0; - - // wrt-rd EVT15 = 0xFFE0203C - imm32 p0, 0xFFE0203C - imm32 r0, 0xFFFFABC6 - [p0] = r0; - - // wrt-rd EVT_OVERRIDE:9 bits = 0xFFE02100 - imm32 p0, 0xFFE02100 - imm32 r0, 0x000001ff - [p0] = r0; - - // wrt-rd IMASK: 16 bits = 0xFFE02104 - imm32 p0, 0xFFE02104 - imm32 r0, 0x00000fff - [p0] = r0; - - // wrt-rd IPEND: 16 bits, rw=0 = 0xFFE02108 - imm32 p0, 0xFFE02108 - imm32 r0, 0x00000000 - //[p0] = r0; - raise 12; - raise 13; - - // wrt-rd ILAT: 16 bits, rw=0 = 0xFFE0210C - imm32 p0, 0xFFE0210C - imm32 r0, 0x00000000 - //[p0] = r0; - csync; - - // *** read ops - imm32 p0, 0xFFE02000 - r0 = [p0]; - CHECKREG r0, 0; - - imm32 p0, 0xFFE02004 - r1 = [p0]; - CHECKREG r1, 0; - - imm32 p0, 0xFFE02008 - r2 = [p0]; - CHECKREG r2, 0xE1DE5D1C; - - imm32 p0, 0xFFE0200C - r3 = [p0]; - CHECKREG r3, 0x9CC20332; - - imm32 p0, 0xFFE02014 - r4 = [p0]; - imm32 p0, 0xFFE02018 - r5 = [p0]; - imm32 p0, 0xFFE0201C - r6 = [p0]; - imm32 p0, 0xFFE02020 /* EVT8 */ - r7 = [p0]; -CHECKREG r0, 0x00000000; -//CHECKREG(r1, 0x00000000); /// mismatch = 00 -CHECKREG r2, 0xE1DE5D1C; -CHECKREG r3, 0x9CC20332; -CHECKREG r4, 0x55552345; -CHECKREG r5, 0x66663456; -CHECKREG r6, 0x77774567; -CHECKREG r7, 0x88885678; - - imm32 p0, 0xFFE02024 /* EVT9 */ - r0 = [p0]; - imm32 p0, 0xFFE02028 /* EVT10 */ - r1 = [p0]; - imm32 p0, 0xFFE0202C /* EVT11 */ - r2 = [p0]; - imm32 p0, 0xFFE02030 /* EVT12 */ - r3 = [p0]; - imm32 p0, 0xFFE02034 /* EVT13 */ - r4 = [p0]; - imm32 p0, 0xFFE02038 /* EVT14 */ - r5 = [p0]; - imm32 p0, 0xFFE0203C /* EVT15 */ - r6 = [p0]; -CHECKREG r0, 0x99996789; -CHECKREG r1, 0xaaaa1234; -CHECKREG r2, 0xBBBBABC6; -CHECKREG r3, 0xCCCCABC6; -CHECKREG r4, 0xDDDDABC6; -CHECKREG r5, 0xEEEEABC6; -CHECKREG r6, 0xFFFFABC6; - - imm32 p0, 0xFFE02100 /* EVT_OVERRIDE */ - r0 = [p0]; - imm32 p0, 0xFFE02104 /* IMASK */ - r1 = [p0]; - imm32 p0, 0xFFE02108 /* IPEND */ - r2 = [p0]; - imm32 p0, 0xFFE0210C /* ILAT */ - r3 = [p0]; -CHECKREG r0, 0x000001ff; -CHECKREG r1, 0x00000fff; /* XXX: original had 0xfe0 ?? */ -CHECKREG r2, 0x00008000; -CHECKREG r3, 0x00003000; - - dbg_pass; - -// ********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 - RTE; - -RHANDLE: // Reset Handler 1 - RTI; - -NHANDLE: // NMI Handler 2 - r0 = 2; - RTN; - -XHANDLE: // Exception Handler 3 - - RTX; - -HWHANDLE: // HW Error Handler 5 - r2 = 5; - RTI; - -THANDLE: // Timer Handler 6 - r3 = 6; - RTI; - -I7HANDLE: // IVG 7 Handler - r4 = 7; - RTI; - -I8HANDLE: // IVG 8 Handler - r5 = 8; - RTI; - -I9HANDLE: // IVG 9 Handler - r6 = 9; - RTI; - -I10HANDLE: // IVG 10 Handler - r7 = 10; - RTI; - -I11HANDLE: // IVG 11 Handler - r0 = 11; - RTI; - -I12HANDLE: // IVG 12 Handler - r1 = 12; - RTI; - -I13HANDLE: // IVG 13 Handler - r2 = 13; - RTI; - -I14HANDLE: // IVG 14 Handler - r3 = 14; - RTI; - -I15HANDLE: // IVG 15 Handler - r4 = 15; - RTI; - - nop;nop;nop;nop;nop;nop;nop; // needed for icache bug - -// -// Data Segment -// - -.data -// Stack Segments (Both Kernel and User) - -.rep 0x10 -.byte 0 -.endr -KSTACK: - -.rep 0x10 -.byte 0 -.endr -USTACK: diff --git a/sim/testsuite/sim/bfin/c_mmr_loop.S b/sim/testsuite/sim/bfin/c_mmr_loop.S deleted file mode 100644 index b0fa404..0000000 --- a/sim/testsuite/sim/bfin/c_mmr_loop.S +++ /dev/null @@ -1,417 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_mmr_loop/c_mmr_loop.dsp -// Spec Reference: mmr loop (interr control) no exception -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -// - -////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we set the processor operating modes, initialize registers -// etc.) -// - -BOOT: - -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - //CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; // and frame pointer - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// -STARTUSER: -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - - - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** -// EVTx - // wrt-rd EVT0: 0 bits, rw=0 = 0xFFE02000 -LD32(p0, 0xFFE02000); -LD32(r0, 0x00000000); - [ P0 ] = R0; - - // wrt-rd EVT1: 32 bits, rw=0 = 0xFFE02004 -LD32(p0, 0xFFE02004); -LD32(r0, 0x00000000); - [ P0 ] = R0; - - // wrt-rd EVT2 = 0xFFE02008 -LD32(p0, 0xFFE02008); -LD32(r0, 0xE1DE5D1C); - [ P0 ] = R0; - - // wrt-rd EVT3 = 0xFFE0200C -LD32(p0, 0xFFE0200C); -LD32(r0, 0x9CC20332); - [ P0 ] = R0; - - // wrt-rd EVT4 = 0xFFE02010 -LD32(p0, 0xFFE02010); -LD32(r0, 0x00000000); // not implemented - [ P0 ] = R0; - - // wrt-rd EVT5 = 0xFFE02014 -LD32(p0, 0xFFE02014); -LD32(r0, 0x55552345); - [ P0 ] = R0; - - // wrt-rd EVT6 = 0xFFE02018 -LD32(p0, 0xFFE02018); -LD32(r0, 0x66663456); - [ P0 ] = R0; - - // wrt-rd EVT7 = 0xFFE0201C -LD32(p0, 0xFFE0201C); -LD32(r0, 0x77774567); - [ P0 ] = R0; - - // wrt-rd EVT8 = 0xFFE02020 -LD32(p0, 0xFFE02020); -LD32(r0, 0x88885678); - [ P0 ] = R0; - - // wrt-rd EVT9 = 0xFFE02024 -LD32(p0, 0xFFE02024); -LD32(r0, 0x99996789); - [ P0 ] = R0; - - // wrt-rd EVT10 = 0xFFE02028 -LD32(p0, 0xFFE02028); -LD32(r0, 0xaaaa1234); - [ P0 ] = R0; - - // wrt-rd EVT11 = 0xFFE0202C -LD32(p0, 0xFFE0202C); -LD32(r0, 0xBBBBABC6); - [ P0 ] = R0; - - // wrt-rd EVT12 = 0xFFE02030 -LD32(p0, 0xFFE02030); -LD32(r0, 0xCCCCABC6); - [ P0 ] = R0; - - // wrt-rd EVT13 = 0xFFE02034 -LD32(p0, 0xFFE02034); -LD32(r0, 0xDDDDABC6); - [ P0 ] = R0; - - // wrt-rd EVT14 = 0xFFE02038 -LD32(p0, 0xFFE02038); -LD32(r0, 0xEEEEABC6); - [ P0 ] = R0; - - // wrt-rd EVT15 = 0xFFE0203C -LD32(p0, 0xFFE0203C); -LD32(r0, 0xFFFFABC6); - [ P0 ] = R0; - - // wrt-rd EVT_OVERRIDE:9 bits = 0xFFE02100 -LD32(p0, 0xFFE02100); -LD32(r0, 0x000001ff); - [ P0 ] = R0; - - // wrt-rd IMASK: 16 bits = 0xFFE02104 -LD32(p0, 0xFFE02104); -LD32(r0, 0x00000fe0); - [ P0 ] = R0; - - - // wrt-rd IPEND: 16 bits, rw=0 = 0xFFE02108 -LD32(p0, 0xFFE02108); -LD32(r0, 0x00000000); - //[p0] = r0; -RAISE 12; -RAISE 13; - - // wrt-rd ILAT: 16 bits, rw=0 = 0xFFE0210C -LD32(p0, 0xFFE0210C); -LD32(r0, 0x00000000); - //[p0] = r0; -CSYNC; -//*** read ops -P1.L = DATA0; -P1.H = DATA0; - -LD32(p0, 0xFFE02000); - P2 = 16; -LSETUP ( start1 , end1 ) LC0 = P2; -start1: - R0 = [ P0 ++ ]; -end1: [ P1 ++ ] = R0; -//nop; -P1.L = DATA0; -P1.H = DATA0; - R0 = [ P1 ++ ]; - R1 = [ P1 ++ ]; - R2 = [ P1 ++ ]; - R3 = [ P1 ++ ]; - R4 = [ P1 ++ ]; - R5 = [ P1 ++ ]; - R6 = [ P1 ++ ]; - R7 = [ P1 ++ ]; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0xE1DE5D1C); -CHECKREG(r3, 0x9CC20332); -CHECKREG(r4, 0x00000000); -CHECKREG(r5, 0x55552345); -CHECKREG(r6, 0x66663456); -CHECKREG(r7, 0x77774567); - R0 = [ P1 ++ ]; - R1 = [ P1 ++ ]; - R2 = [ P1 ++ ]; - R3 = [ P1 ++ ]; - R4 = [ P1 ++ ]; - R5 = [ P1 ++ ]; - R6 = [ P1 ++ ]; - R7 = [ P1 ++ ]; -CHECKREG(r0, 0x88885678); -CHECKREG(r1, 0x99996789); -CHECKREG(r2, 0xAAAA1234); -CHECKREG(r3, 0xBBBBABC6); -CHECKREG(r4, 0xCCCCABC6); -CHECKREG(r5, 0xDDDDABC6); -CHECKREG(r6, 0xEEEEABC6); -CHECKREG(r7, 0xFFFFABC6); - -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = 2; -RTN; - -XHANDLE: // Exception Handler 3 - R7 = 0x00006789 (X); -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = 5; -RTI; - -THANDLE: // Timer Handler 6 - R3 = 6; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = 7; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = 8; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = 9; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" -DATA0: -.dd 0x000a0000 -.dd 0x000b0001 -.dd 0x000c0002 -.dd 0x000d0003 -.dd 0x000e0004 -.dd 0x000f0005 -.dd 0x00100006 -.dd 0x00200007 -.dd 0x00300008 -.dd 0x00400009 -.dd 0x0050000a -.dd 0x0060000b -.dd 0x0070000c -.dd 0x0080000d -.dd 0x0090000e -.dd 0x0100000f -.dd 0x02000010 -.dd 0x03000011 -.dd 0x04000012 -.dd 0x05000013 -.dd 0x06000014 -.dd 0x001a0000 -.dd 0x001b0001 -.dd 0x001c0002 -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_mmr_loop_user_except.S b/sim/testsuite/sim/bfin/c_mmr_loop_user_except.S deleted file mode 100644 index 7e0bc40..0000000 --- a/sim/testsuite/sim/bfin/c_mmr_loop_user_except.S +++ /dev/null @@ -1,325 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_mmr_loop_user_except/c_mmr_loop_user_except.dsp -// Spec Reference: c_mmr_loop_user_except -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we set the processor operating modes, initialize registers -// etc.) -// - -BOOT: - -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - //CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - - - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; // and frame pointer - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) - - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -// LD32_LABEL(r0, I13HANDLE);// IVG13 Handler -// [p0++] = r0; - -// LD32_LABEL(r0, I14HANDLE);// IVG14 Handler -// [p0++] = r0; - -//***************** - // wrt-rd EVT13 = 0xFFE02034 -LD32(p0, 0xFFE02034); -LD32(r0, 0xDDDDABC6); - [ P0 ] = R0; - - // wrt-rd EVT14 = 0xFFE02038 -LD32(p0, 0xFFE02038); -LD32(r0, 0xEEEEABC6); - [ P0 ] = R0; -//***************** -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -// JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; // execute this instr put us in USER mode - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // USER MODE & go to different RAISE in USER mode - // until the end of the test. - -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -// LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! - // Can't Raise 0, 3, or 4 - // Raise 1 requires some intelligence so the test - // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) -// RAISE 2; // RTN // exception because we execute this in USER mode - R0 = 0; -LD32(p0, 0xFFE02034); - P2 = 2; -LSETUP ( start1 , end1 ) LC0 = P2; -start1: - R0 = [ P0 ++ ]; // 16 bit instr -end1: R1 = R0; - -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000000); -//CHECKREG(r3, 0x00000030); -CHECKREG(r4, 0x0000000F); -CHECKREG(r5, 0x00000012); -CHECKREG(r6, 0x00000015); -CHECKREG(r7, 0x00000018); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = RETN; - R0 += 2; -RETN = r0; -RTN; - -XHANDLE: // Exception Handler 3 - R3 = RETX; - R4 += 5; - R5 += 6; - R6 += 7; - R7 += 8; - R3 += 2; // for resturn address -RETX = r3; -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = RETI; - R2 += 2; -RETI = r2; -RTI; - -THANDLE: // Timer Handler 6 - R3 = RETI; - R3 += 2; -RETI = r3; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = RETI; - R4 += 2; -RETI = r4; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = RETI; - R5 += 2; -RETI = r5; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = RETI; - R6 += 2; -RETI = r6; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = RETI; - R7 += 2; -RETI = r7; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = RETI; - R0 += 2; -RETI = r0; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = RETI; - R1 += 2; -RETI = r1; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = RETI; - R2 += 2; -RETI = r2; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = RETI; - R3 += 2; -RETI = r3; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: -// .space (STACKSIZE); // adding this may solve the problem diff --git a/sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S b/sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S deleted file mode 100644 index 82bb45d..0000000 --- a/sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S +++ /dev/null @@ -1,307 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_mmr_ppop_illegal_adr/c_mmr_ppop_illegal_adr.dsp -// Spec Reference: mmr ppop illegal address -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we set the processor operating modes, initialize registers -// etc.) -// - -BOOT: - -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - //CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; // and frame pointer - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// -STARTUSER: -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - - - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - -LD32(r0, 0206037020); -LD32(r1, 0x10070030); -LD32(r2, 0xe2000043); -LD32(r3, 0x30305050); -LD32(r4, 0x0f040860); -LD32(r5, 0x0a0050d0); -LD32(r6, 0x00000000); -LD32(r7, 0x0f060071); -// LD32(sp, 0xFFE02104); -// [--sp] = (r7-r6); - [ -- SP ] = R7; - [ -- SP ] = R6; -.dd 0xffff - R1 += 2; - -CHECKREG(r1, 0x10070034); -CHECKREG(r2, 0xE2000046); -CHECKREG(r3, 0x30305054); -CHECKREG(r4, 0x0f040865); -CHECKREG(r5, 0x0a0050d6); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x0f060079); - R7 = [ SP ++ ]; -CHECKREG(r7, 0x00000000); - -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = 2; -RTN; - -XHANDLE: // Exception Handler 3 -R0 = RETX; // error handler:RETX has the address of the same Illegal instr - R1 += 2; - R2 += 3; - R3 += 4; - R4 += 5; - R5 += 6; - R6 += 7; - R7 += 8; -R0 += 2; // we have to add 2 to point to next instr after return (16-bit illegal instr) -RETX = R0; -NOP; NOP; NOP; NOP; - - -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = 5; -RTI; - -THANDLE: // Timer Handler 6 - R3 = 6; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = 7; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = 8; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = 9; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" -DATA0: -.dd 0x000a0000 -.dd 0x000b0001 -.dd 0x000c0002 -.dd 0x000d0003 -.dd 0x000e0004 -.dd 0x000f0005 -.dd 0x00100006 -.dd 0x00200007 -.dd 0x00300008 -.dd 0x00400009 -.dd 0x0050000a -.dd 0x0060000b -.dd 0x0070000c -.dd 0x0080000d -.dd 0x0090000e -.dd 0x0100000f -.dd 0x02000010 -.dd 0x03000011 -.dd 0x04000012 -.dd 0x05000013 -.dd 0x06000014 -.dd 0x001a0000 -.dd 0x001b0001 -.dd 0x001c0002 -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S b/sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S deleted file mode 100644 index 0b78d5e..0000000 --- a/sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S +++ /dev/null @@ -1,308 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_mmr_ppopm_illegal_adr/c_mmr_ppopm_illegal_adr.dsp -// Spec Reference: mmr ppopm illegal address -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we set the processor operating modes, initialize registers -// etc.) -// - -BOOT: - -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - //CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; // and frame pointer - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// -STARTUSER: -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - - - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - -LD32(r0, 0206037020); -LD32(r1, 0x10070030); -LD32(r2, 0xe2000043); -LD32(r3, 0x30305050); -LD32(r4, 0x0f040860); -LD32(r5, 0x0a0050d0); -LD32(r6, 0x00000000); -LD32(r7, 0x0f060071); - [ -- SP ] = ( R7:7 ); -LD32(r7, 0x123456af); - [ -- SP ] = ( R7:6 ); -// [--sp] = r7; -// [--sp] = r6; -.dd 0xffff - R1 += 2; - -CHECKREG(r1, 0x10070034); -CHECKREG(r2, 0xE2000046); -CHECKREG(r3, 0x30305054); -CHECKREG(r4, 0x0f040865); -CHECKREG(r5, 0x0a0050d6); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x123456b7); - R7 = [ SP ++ ]; -CHECKREG(r7, 0x123456af); - -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = 2; -RTN; - -XHANDLE: // Exception Handler 3 -R0 = RETX; // error handler:RETX has the address of the same Illegal instr - R1 += 2; - R2 += 3; - R3 += 4; - R4 += 5; - R5 += 6; - R6 += 7; - R7 += 8; -R0 += 2; // we have to add 2 to point to next instr after return (16-bit illegal instr) -RETX = R0; -NOP; NOP; NOP; NOP; - - -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = 5; -RTI; - -THANDLE: // Timer Handler 6 - R3 = 6; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = 7; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = 8; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = 9; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" -DATA0: -.dd 0x000a0000 -.dd 0x000b0001 -.dd 0x000c0002 -.dd 0x000d0003 -.dd 0x000e0004 -.dd 0x000f0005 -.dd 0x00100006 -.dd 0x00200007 -.dd 0x00300008 -.dd 0x00400009 -.dd 0x0050000a -.dd 0x0060000b -.dd 0x0070000c -.dd 0x0080000d -.dd 0x0090000e -.dd 0x0100000f -.dd 0x02000010 -.dd 0x03000011 -.dd 0x04000012 -.dd 0x05000013 -.dd 0x06000014 -.dd 0x001a0000 -.dd 0x001b0001 -.dd 0x001c0002 -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_mmr_timer.S b/sim/testsuite/sim/bfin/c_mmr_timer.S deleted file mode 100644 index ac34e17..0000000 --- a/sim/testsuite/sim/bfin/c_mmr_timer.S +++ /dev/null @@ -1,282 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_mmr_timer/c_mmr_timer.dsp -// Spec Reference: mmr timer -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -// - -////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we set the processor operating modes, initialize registers -// etc.) -// - -BOOT: - -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - //CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; // and frame pointer - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// -STARTUSER: -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - // TCNTL: 4 bits, rw=1 = 0xFFE03000 -LD32(p0, 0xFFE03000); -LD32(r0, 0x0000000D); - [ P0 ] = R0; -CSYNC; // without this it read out zero - R1 = [ P0 ]; - - // TPERIOD: 32 bits, rw=1 = 0xFFE03004 -LD32(p0, 0xFFE03004); -LD32(r0, 0x11112222); - [ P0 ] = R0; -CSYNC; // without this it read out zero - R2 = [ P0 ]; - - // TSCALE: 8 bits, rw=1 = 0xFFE03008 -LD32(p0, 0xFFE03008); -LD32(r0, 0x00000050); - [ P0 ] = R0; -CSYNC; // without this it read out zero - R3 = [ P0 ]; - - - // TCOUNT: 32 bits, rw=1 = 0xFFE0300C -LD32(p0, 0xFFE0300C); -LD32(r0, 0x00000100); - [ P0 ] = R0; -CSYNC; // without this it read out zero - R4 = [ P0 ]; - - -CHECKREG(r1, 0x0000000D); -CHECKREG(r2, 0x11112222); -CHECKREG(r3, 0x00000050); -CHECKREG(r4, 0x00000100); - -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = 2; -RTN; - -XHANDLE: // Exception Handler 3 - -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = 5; -RTI; - -THANDLE: // Timer Handler 6 - R3 = 6; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = 7; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = 8; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = 9; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: - -//.data 0xFFE03000 -//.dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_mode_supervisor.S b/sim/testsuite/sim/bfin/c_mode_supervisor.S deleted file mode 100644 index 4ea0d6c..0000000 --- a/sim/testsuite/sim/bfin/c_mode_supervisor.S +++ /dev/null @@ -1,287 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_mode_supervisor/c_mode_supervisor.dsp -// Spec Reference: mode_supervisor -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -// - -////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! - // Can't Raise 0, 3, or 4 - // Raise 1 requires some intelligence so the test - // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) -RAISE 2; // RTN -RAISE 5; // RTI -RAISE 6; // RTI -RAISE 7; // RTI -RAISE 8; // RTI -RAISE 9; // RTI -RAISE 10; // RTI -RAISE 11; // RTI -RAISE 12; // RTI -RAISE 13; // RTI -RAISE 14; // RTI -RAISE 15; // RTI - -CHECKREG(r0, 0x0000000B); -CHECKREG(r1, 0x0000000C); -CHECKREG(r2, 0x0000000D); -CHECKREG(r3, 0x0000000E); -CHECKREG(r4, 0x00000007); -CHECKREG(r5, 0x00000008); -CHECKREG(r6, 0x00000009); -CHECKREG(r7, 0x0000000A); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -CHECKREG(r0, 0x00000002); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000005); -CHECKREG(r3, 0x00000006); -CHECKREG(r4, 0x00000007); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = 5; -RTI; - -THANDLE: // Timer Handler 6 - R3 = 6; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = 7; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = 8; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = 9; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_mode_user.S b/sim/testsuite/sim/bfin/c_mode_user.S deleted file mode 100644 index 1b72035..0000000 --- a/sim/testsuite/sim/bfin/c_mode_user.S +++ /dev/null @@ -1,338 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_mode_user/c_mode_user.dsp -// Spec Reference: mode_user -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -// - -////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - A0 = 0; // reset accumulators - A1 = 0; - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -// JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; // execute this instr put us in USER mode - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // USER MODE & go to different RAISE in USER mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -A1 = A0 = 0; -ASTAT = R0; - - -// R-reg to P-reg to R reg: stall -LD32(r0, 0x1357bdad); -LD32(r1, 0x02dfe804); -LD32(r2, 0x12345679); -LD32(r3, 0x34751975); -LD32(r4, 0x08810990); -LD32(r5, 0x01a1b0b0); -LD32(r6, 0x01c1dd00); -LD32(r7, 0x01e1fff0); -R5 = R3.L * R1.L, R4 = R3.L * R1.L; // dsp32mult_pair -P4 = R5; -R6 = P4; -R1 = ( A1 += R5.L * R6.H ), A0 = R5.H * R6.L; // dsp32mac_pair -P3 = A0.w; -P4 = A1.w; -A1 = A1 (S), A0 = A0 (S); // dsp32alu_sat_aa -R6 = A0.w; -R7 = A1.w; -R0 = R7; -R2 = R0; // regmv -R2 >>>= R3; // c_alu2op_arith_r_sft.dsp -R4 = R2 - R1; -R5.L = ASHIFT R4.L BY R3.L; -R6 += -3; //c_compi2opd_dr_add_i7_n.dsp -I2 = R6; -I2 += 2; -I2 += M1; -R7 = I2; - - -CHECKREG(r0, 0x015AF820); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x34751975); -CHECKREG(r4, 0xFEA507E0); -CHECKREG(r5, 0xFB3A0000); -CHECKREG(r6, 0x015AF81D); -CHECKREG(r7, 0x015AF81F); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x015AF81F); -CHECKREG(r3, 0x00000000); -CHECKREG(r4, 0xFEA507E0); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = RETN; - R0 += 2; -RETN = r0; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = RETX; - R0 += 1; - R1 += 2; - R2 += 1; - R3 += 1; - R4 += 1; - R5 += 1; - R6 += 1; - R7 += 1; -RETX = r1; -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = RETI; - R2 += 2; -RETI = r2; -RTI; - -THANDLE: // Timer Handler 6 - R3 = RETI; - R3 += 2; -RETI = r3; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = RETI; - R4 += 2; -RETI = r4; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = RETI; - R5 += 2; -RETI = r5; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = RETI; - R6 += 2; -RETI = r6; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = RETI; - R7 += 2; -RETI = r7; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = RETI; - R0 += 2; -RETI = r0; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = RETI; - R1 += 2; -RETI = r1; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = RETI; - R2 += 2; -RETI = r2; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = RETI; - R3 += 2; -RETI = r3; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: -// .space (STACKSIZE); // adding this may solve the problem diff --git a/sim/testsuite/sim/bfin/c_mode_user_superivsor.S b/sim/testsuite/sim/bfin/c_mode_user_superivsor.S deleted file mode 100644 index ef8a2b4..0000000 --- a/sim/testsuite/sim/bfin/c_mode_user_superivsor.S +++ /dev/null @@ -1,353 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_mode_user_superivsor/c_mode_user_superivsor.dsp -// Spec Reference: mode_user_supervisor -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -// - -////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -// JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; // execute this instr put us in USER mode - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // USER MODE & go to different RAISE in USER mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! - // Can't Raise 0, 3, or 4 -RAISE 2; // RTN -RAISE 5; // RTI -RAISE 6; // RTI -RAISE 7; // RTI -RAISE 8; // RTI -RAISE 9; // RTI -RAISE 10; // RTI -RAISE 11; // RTI -RAISE 12; // RTI -RAISE 13; // RTI -RAISE 14; // RTI - -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; - -CHECKREG(r0, 0x00000018); -CHECKREG(r1, 0x00000018); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x00000018); -CHECKREG(r4, 0x00000000); -CHECKREG(r5, 0x00000000); -CHECKREG(r6, 0x00000000); -CHECKREG(r7, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = RETN; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - R0 += 2; -RETN = r0; -RTN; - -XHANDLE: // Exception Handler 3 - R0 = RETX; - I0 += 2; - I1 += 2; - I3 += 2; - R0 += 2; -RETX = r0; -RTX; - -HWHANDLE: // HW Error Handler 5 - R0 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - R0 += 2; -RETI = r0; -RTI; - -THANDLE: // Timer Handler 6 - R0 = RETI; - R0 += 2; -RETI = r0; -RTI; - -I7HANDLE: // IVG 7 Handler - R0 = RETI; - I0 += 2; - I1 += 2; - I3 += 2; - R0 += 2; -RETI = r0; -RTI; - -I8HANDLE: // IVG 8 Handler - R0 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - M0 = I0; - M1 = I1; - M2 = I2; - M3 = I3; - R0 += 2; -RETI = r0; -RTI; - -I9HANDLE: // IVG 9 Handler - R0 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - R0 += 2; -RETI = r0; -RTI; - -I10HANDLE: // IVG 10 Handler - R0 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - R0 += 2; -RETI = r0; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - M0 = R4; - R0 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - R0 += 2; -RETI = r0; -RTI; - -I12HANDLE: // IVG 12 Handler - R0 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - R0 += 2; -RETI = r0; -RTI; - -I13HANDLE: // IVG 13 Handler - R0 = RETI; - I0 += 2; - I1 += 2; - I2 += 2; - I3 += 2; - R0 += 2; -RETI = r0; -RTI; - -I14HANDLE: // IVG 14 Handler - R0 = RETI; - I1 += 2; - I2 += 2; - I3 += 2; - R0 += 2; -RETI = r0; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; - I1 += 2; - I2 += 2; -RTI; - -// nop;nop;nop;nop;nop;nop;nop; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: -// .space (STACKSIZE); // adding this may solve the problem diff --git a/sim/testsuite/sim/bfin/c_multi_issue_dsp_ld_ld.s b/sim/testsuite/sim/bfin/c_multi_issue_dsp_ld_ld.s deleted file mode 100644 index 1af87dc..0000000 --- a/sim/testsuite/sim/bfin/c_multi_issue_dsp_ld_ld.s +++ /dev/null @@ -1,197 +0,0 @@ -//Original:/testcases/core/c_multi_issue_dsp_ld_ld/c_multi_issue_dsp_ld_ld.dsp -// Spec Reference: dsp32mac and 2 loads -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - imm32 r0, 0x00000000; - A0 = 0; - A1 = 0; - ASTAT = r0; - - loadsym I0, DATA0 - loadsym I1, DATA1 - - loadsym P1, DATA0 - loadsym P2, DATA1 - -// test the default (signed fraction : left ) - imm32 r0, 0x12345678; - imm32 r1, 0x33456789; - imm32 r2, 0x5556789a; - imm32 r3, 0x75678912; - imm32 r4, 0x86789123; - imm32 r5, 0xa7891234; - imm32 r6, 0xc1234567; - imm32 r7, 0xf1234567; - A1 = R0.L * R1.L, A0 = R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; - A1 += R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ I0 ++ ] || R3 = [ I1 ++ ]; - A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = [ P1 ++ ] || R5 = [ I1 ++ ]; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x000A0000; - CHECKREG r1, 0x00F00100; - CHECKREG r2, 0x000B0001; - CHECKREG r3, 0x00E00101; - CHECKREG r4, 0x000A0000; - CHECKREG r5, 0x00D00102; - CHECKREG r6, 0x92793486; - CHECKREG r7, 0xDD2F9BAA; - - imm32 r0, 0x12245618; - imm32 r1, 0x23256719; - imm32 r2, 0x3426781a; - imm32 r3, 0x45278912; - imm32 r4, 0x56289113; - imm32 r5, 0x67291214; - imm32 r6, 0xa1234517; - imm32 r7, 0xc1234517; - A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = [ P1 ++ ] || R6 = [ I0 ++ ]; - A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ P2 ++ ] || R3 = [ I1 ++ ]; - A1 += R4.H * R6.H, A0 -= R4.H * R6.L || [ P2 ++ ] = R5 || R7 = [ I1 ++ ]; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x12245618; - CHECKREG r1, 0x23256719; - CHECKREG r2, 0x00F00100; - CHECKREG r3, 0x00C00103; - CHECKREG r4, 0x000B0001; - CHECKREG r5, 0x67291214; - CHECKREG r6, 0x863ABC70; - CHECKREG r7, 0xB4EF6A10; - - imm32 r0, 0x15245648; - imm32 r1, 0x25256749; - imm32 r2, 0x3526784a; - imm32 r3, 0x45278942; - imm32 r4, 0x55389143; - imm32 r5, 0x65391244; - imm32 r6, 0xa5334547; - imm32 r7, 0xc5334547; - A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = [ P1 ++ ] || R0 = [ I1 -- ]; - A1 += R2.H * R3.H, A0 += R2.L * R3.H || NOP || R4 = [ I0 ++ ]; - A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = [ P2 -- ] || R5 = [ I0 -- ]; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x00A00105; - CHECKREG r1, 0x25256749; - CHECKREG r2, 0x000C0002; - CHECKREG r3, 0x00D00102; - CHECKREG r4, 0x000D0003; - CHECKREG r5, 0x000E0004; - CHECKREG r6, 0xCBDCD104; - CHECKREG r7, 0x0001DAE8; - - imm32 r1, 0x02450789; - imm32 r2, 0x0356089a; - imm32 r3, 0x04670912; - imm32 r4, 0x05780123; - imm32 r5, 0x06890234; - imm32 r6, 0x07230567; - imm32 r7, 0x00230567; - R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R1 = [ I1 ++ ] || R0 = [ I0 -- ]; - R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = [ P1 ] || R3 = [ I0 -- ]; - R5 = R4 +|+ R2, R0 = R4 -|- R2 (CO) || NOP || R4 = [ I0 ++ ]; - CHECKREG r0, 0xFA99FFDD; - CHECKREG r1, 0x0B8A0E79; - CHECKREG r2, 0x00610336; - CHECKREG r3, 0x000C0002; - CHECKREG r4, 0x000B0001; - CHECKREG r5, 0x009F0105; - CHECKREG r6, 0x000D0003; - CHECKREG r7, 0x00230567; - - pass - - .data -DATA0: - .dd 0x000a0000 - .dd 0x000b0001 - .dd 0x000c0002 - .dd 0x000d0003 - .dd 0x000e0004 - .dd 0x000f0005 - .dd 0x00100006 - .dd 0x00200007 - .dd 0x00300008 - .dd 0x00400009 - .dd 0x0050000a - .dd 0x0060000b - .dd 0x0070000c - .dd 0x0080000d - .dd 0x0090000e - .dd 0x0100000f - .dd 0x02000010 - .dd 0x03000011 - .dd 0x04000012 - .dd 0x05000013 - .dd 0x06000014 - .dd 0x001a0000 - .dd 0x001b0001 - .dd 0x001c0002 - .dd 0x001d0003 - .dd 0x00010004 - .dd 0x00010005 - .dd 0x02100006 - .dd 0x02200007 - .dd 0x02300008 - .dd 0x02200009 - .dd 0x0250000a - .dd 0x0260000b - .dd 0x0270000c - .dd 0x0280000d - .dd 0x0290000e - .dd 0x2100000f - .dd 0x22000010 - .dd 0x22000011 - .dd 0x24000012 - .dd 0x25000013 - .dd 0x26000014 - -DATA1: - .dd 0x00f00100 - .dd 0x00e00101 - .dd 0x00d00102 - .dd 0x00c00103 - .dd 0x00b00104 - .dd 0x00a00105 - .dd 0x00900106 - .dd 0x00800107 - .dd 0x00100108 - .dd 0x00200109 - .dd 0x0030010a - .dd 0x0040010b - .dd 0x0050011c - .dd 0x0060010d - .dd 0x0070010e - .dd 0x0080010f - .dd 0x00900110 - .dd 0x01000111 - .dd 0x02000112 - .dd 0x03000113 - .dd 0x04000114 - .dd 0x05000115 - .dd 0x03f00100 - .dd 0x03e00101 - .dd 0x03d00102 - .dd 0x03c00103 - .dd 0x03b00104 - .dd 0x03a00105 - .dd 0x03900106 - .dd 0x03800107 - .dd 0x03100108 - .dd 0x03200109 - .dd 0x0330010a - .dd 0x0330010b - .dd 0x0350011c - .dd 0x0360010d - .dd 0x0370010e - .dd 0x0380010f - .dd 0x03900110 - .dd 0x31000111 - .dd 0x32000112 - .dd 0x33000113 - .dd 0x34000114 diff --git a/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_1.s b/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_1.s deleted file mode 100644 index 8dc8373..0000000 --- a/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_1.s +++ /dev/null @@ -1,198 +0,0 @@ -//Original:/testcases/core/c_multi_issue_dsp_ldst_1/c_multi_issue_dsp_ldst_1.dsp -// Spec Reference: dsp32mac and 2 load/store -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - - imm32 r0, 0x00000000; - A0 = 0; - A1 = 0; - ASTAT = r0; - - loadsym I0, DATA0; - loadsym I1, DATA1; - - loadsym P1, DATA0; - loadsym P2, DATA1; - -// test the default (signed fraction : left ) - imm32 r0, 0x12345678; - imm32 r1, 0x33456789; - imm32 r2, 0x5556789a; - imm32 r3, 0x75678912; - imm32 r4, 0x86789123; - imm32 r5, 0xa7891234; - imm32 r6, 0xc1234567; - imm32 r7, 0xf1234567; - A1 = R0.L * R1.L, A0 = R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; - A1 += R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ I0 ++ ] || R3 = [ I1 ++ ]; - A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = [ P1 ++ ] || [ I1 ++ ] = R5; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x000A0000; - CHECKREG r1, 0x00F00100; - CHECKREG r2, 0x000B0001; - CHECKREG r3, 0x00E00101; - CHECKREG r4, 0x000A0000; - CHECKREG r5, 0xA7891234; - CHECKREG r6, 0x92793486; - CHECKREG r7, 0xDD2F9BAA; - - imm32 r0, 0x12245618; - imm32 r1, 0x23256719; - imm32 r2, 0x3426781a; - imm32 r3, 0x45278912; - imm32 r4, 0x56289113; - imm32 r5, 0x67291214; - imm32 r6, 0xa1234517; - imm32 r7, 0xc1234517; - A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = [ P1 ++ ] || [ I0 ++ ] = R6; - A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ P2 ++ ] || [ I1 ++ ] = R3; - A1 += R4.H * R6.H, A0 -= R4.H * R6.L || [ P2 ++ ] = R5 || R7 = [ I1 ++ ]; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x12245618; - CHECKREG r1, 0x23256719; - CHECKREG r2, 0x00F00100; - CHECKREG r3, 0x45278912; - CHECKREG r4, 0x000B0001; - CHECKREG r5, 0x67291214; - CHECKREG r6, 0x8634CCA2; - CHECKREG r7, 0xB4E7420A; - - imm32 r0, 0x15245648; - imm32 r1, 0x25256749; - imm32 r2, 0x3526784a; - imm32 r3, 0x45278942; - imm32 r4, 0x55389143; - imm32 r5, 0x65391244; - imm32 r6, 0xa5334547; - imm32 r7, 0xc5334547; - A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = [ P1 ++ ] || [ I1 -- ] = R3; - A1 += R2.H * R3.H, A0 += R2.L * R3.H || NOP || [ I0 ++ ] = R2; - A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = [ P2 -- ] || R6 = [ I0 -- ]; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x15245648; - CHECKREG r1, 0x25256749; - CHECKREG r2, 0xA1234517; - CHECKREG r3, 0xA7891234; - CHECKREG r4, 0x55389143; - CHECKREG r5, 0x65391244; - CHECKREG r6, 0xFD508A74; - CHECKREG r7, 0x0C2925C0; - - imm32 r1, 0x02450789; - imm32 r2, 0x0356089a; - imm32 r3, 0x04670912; - imm32 r4, 0x05780123; - imm32 r5, 0x06890234; - imm32 r6, 0x07230567; - imm32 r7, 0x00230567; - R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R0 = [ I1 ++ ] || [ I0 -- ] = R2; - R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = [ P1 ] || [ I0 -- ] = R3; - R5 = R4 +|+ R2, R0 = R4 -|- R2 (CO) || NOP || [ I0 ++ ] = R5; - CHECKREG r0, 0xFA99FFDD; - CHECKREG r1, 0x0B8A0E79; - CHECKREG r2, 0x0AA32DD7; - CHECKREG r3, 0x04670912; - CHECKREG r4, 0x0A802870; - CHECKREG r5, 0x15235647; - CHECKREG r6, 0x0356089A; - CHECKREG r7, 0x00230567; - - pass - - .data -DATA0: - .dd 0x000a0000 - .dd 0x000b0001 - .dd 0x000c0002 - .dd 0x000d0003 - .dd 0x000e0004 - .dd 0x000f0005 - .dd 0x00100006 - .dd 0x00200007 - .dd 0x00300008 - .dd 0x00400009 - .dd 0x0050000a - .dd 0x0060000b - .dd 0x0070000c - .dd 0x0080000d - .dd 0x0090000e - .dd 0x0100000f - .dd 0x02000010 - .dd 0x03000011 - .dd 0x04000012 - .dd 0x05000013 - .dd 0x06000014 - .dd 0x001a0000 - .dd 0x001b0001 - .dd 0x001c0002 - .dd 0x001d0003 - .dd 0x00010004 - .dd 0x00010005 - .dd 0x02100006 - .dd 0x02200007 - .dd 0x02300008 - .dd 0x02200009 - .dd 0x0250000a - .dd 0x0260000b - .dd 0x0270000c - .dd 0x0280000d - .dd 0x0290000e - .dd 0x2100000f - .dd 0x22000010 - .dd 0x22000011 - .dd 0x24000012 - .dd 0x25000013 - .dd 0x26000014 - -DATA1: - .dd 0x00f00100 - .dd 0x00e00101 - .dd 0x00d00102 - .dd 0x00c00103 - .dd 0x00b00104 - .dd 0x00a00105 - .dd 0x00900106 - .dd 0x00800107 - .dd 0x00100108 - .dd 0x00200109 - .dd 0x0030010a - .dd 0x0040010b - .dd 0x0050011c - .dd 0x0060010d - .dd 0x0070010e - .dd 0x0080010f - .dd 0x00900110 - .dd 0x01000111 - .dd 0x02000112 - .dd 0x03000113 - .dd 0x04000114 - .dd 0x05000115 - .dd 0x03f00100 - .dd 0x03e00101 - .dd 0x03d00102 - .dd 0x03c00103 - .dd 0x03b00104 - .dd 0x03a00105 - .dd 0x03900106 - .dd 0x03800107 - .dd 0x03100108 - .dd 0x03200109 - .dd 0x0330010a - .dd 0x0330010b - .dd 0x0350011c - .dd 0x0360010d - .dd 0x0370010e - .dd 0x0380010f - .dd 0x03900110 - .dd 0x31000111 - .dd 0x32000112 - .dd 0x33000113 - .dd 0x34000114 diff --git a/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_2.s b/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_2.s deleted file mode 100644 index 16fd3e5..0000000 --- a/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_2.s +++ /dev/null @@ -1,198 +0,0 @@ -//Original:/testcases/core/c_multi_issue_dsp_ldst_2/c_multi_issue_dsp_ldst_2.dsp -// Spec Reference: dsp32mac and 2 load/store -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - INIT_R_REGS 0; - - imm32 r0, 0x00000000; - A0 = 0; - A1 = 0; - ASTAT = r0; - - loadsym I0, DATA0; - loadsym I1, DATA1; - - loadsym P1, DATA0; - loadsym P2, DATA1; - -// test the default (signed fraction : left ) - imm32 r0, 0x12345678; - imm32 r1, 0x33456789; - imm32 r2, 0x5556789a; - imm32 r3, 0x75678912; - imm32 r4, 0x86789123; - imm32 r5, 0xa7891234; - imm32 r6, 0xc1234567; - imm32 r7, 0xf1234567; - A1 = R0.L * R1.L, A0 = R0.L * R1.L || R2 = B [ P1 ++ ] (X) || R3 = [ I1 ++ ]; - A1 += R2.L * R3.L, A0 += R2.L * R3.H || R0 = B [ P1 ++ ] (X) || R1 = [ I1 ++ ]; - A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = B [ P2 ++ ] (X) || [ I1 ++ ] = R5; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00E00101; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00F00100; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0xA7891234; - CHECKREG r6, 0x23DB649A; - CHECKREG r7, 0x4D3DD202; - - imm32 r0, 0x12245618; - imm32 r1, 0x23256719; - imm32 r2, 0x3426781a; - imm32 r3, 0x45278912; - imm32 r4, 0x56289113; - imm32 r5, 0x67291214; - imm32 r6, 0xa1234517; - imm32 r7, 0xc1234517; - A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = B [ P1 ++ ] (X) || [ I0 ++ ] = R6; - A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = B [ P2 ++ ] (X) || [ I1 ++ ] = R3; - A1 += R4.H * R6.H, A0 -= R4.H * R6.L || R5 = B [ P2 ++ ] (X) || R7 = [ I1 ++ ]; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x12245618; - CHECKREG r1, 0x23256719; - CHECKREG r2, 0x00000001; - CHECKREG r3, 0x45278912; - CHECKREG r4, 0x0000000A; - CHECKREG r5, 0xFFFFFFF0; - CHECKREG r6, 0x863ABC9C; - CHECKREG r7, 0xB4EF6908; - - imm32 r0, 0x15245648; - imm32 r1, 0x25256749; - imm32 r2, 0x3526784a; - imm32 r3, 0x45278942; - imm32 r4, 0x55389143; - imm32 r5, 0x65391244; - imm32 r6, 0xa5334547; - imm32 r7, 0xc5334547; - A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = B [ P1 ++ ] (X) || [ I1 -- ] = R3; - A1 += R2.H * R3.H, A0 += R2.L * R3.H || R0 = B [ P2 -- ] (X) || [ I0 ++ ] = R2; - A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = B [ P2 ++ ] (X) || R1 = [ I0 -- ]; - R6 = A0.w; - R7 = A1.w; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x000C0002; - CHECKREG r2, 0xFFFFFFA1; - CHECKREG r3, 0xFFFFFFF0; - CHECKREG r4, 0x55389143; - CHECKREG r5, 0x65391244; - CHECKREG r6, 0xD7CFB47A; - CHECKREG r7, 0x0C2925C0; - - imm32 r1, 0x02450789; - imm32 r2, 0x0356089a; - imm32 r3, 0x04670912; - imm32 r4, 0x05780123; - imm32 r5, 0x06890234; - imm32 r6, 0x07230567; - imm32 r7, 0x00230567; - R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R0 = B [ P1 ++ ] (X) || [ I0 -- ] = R2; - R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = B [ P1 ] (X) || [ I0 -- ] = R3; - R5 = R4 +|+ R2, R0 = R4 -|- R2 || R3 = B [ P2 ++ ] (X) || R7 = [ I1 ++ ]; - CHECKREG r0, 0xFFDDFA99; - CHECKREG r1, 0x0B8A0E79; - CHECKREG r2, 0x001102B3; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0xFFEEFD4C; - CHECKREG r5, 0xFFFFFFFF; - CHECKREG r6, 0x00000008; - CHECKREG r7, 0x00B00104; - - pass - - .data -DATA0: - .dd 0x000a0000 - .dd 0x000b0001 - .dd 0x000c0002 - .dd 0x000d0003 - .dd 0x000e0004 - .dd 0x000f0005 - .dd 0x00100006 - .dd 0x00200007 - .dd 0x00300008 - .dd 0x00400009 - .dd 0x0050000a - .dd 0x0060000b - .dd 0x0070000c - .dd 0x0080000d - .dd 0x0090000e - .dd 0x0100000f - .dd 0x02000010 - .dd 0x03000011 - .dd 0x04000012 - .dd 0x05000013 - .dd 0x06000014 - .dd 0x001a0000 - .dd 0x001b0001 - .dd 0x001c0002 - .dd 0x001d0003 - .dd 0x00010004 - .dd 0x00010005 - .dd 0x02100006 - .dd 0x02200007 - .dd 0x02300008 - .dd 0x02200009 - .dd 0x0250000a - .dd 0x0260000b - .dd 0x0270000c - .dd 0x0280000d - .dd 0x0290000e - .dd 0x2100000f - .dd 0x22000010 - .dd 0x22000011 - .dd 0x24000012 - .dd 0x25000013 - .dd 0x26000014 - -DATA1: - .dd 0x00f00100 - .dd 0x00e00101 - .dd 0x00d00102 - .dd 0x00c00103 - .dd 0x00b00104 - .dd 0x00a00105 - .dd 0x00900106 - .dd 0x00800107 - .dd 0x00100108 - .dd 0x00200109 - .dd 0x0030010a - .dd 0x0040010b - .dd 0x0050011c - .dd 0x0060010d - .dd 0x0070010e - .dd 0x0080010f - .dd 0x00900110 - .dd 0x01000111 - .dd 0x02000112 - .dd 0x03000113 - .dd 0x04000114 - .dd 0x05000115 - .dd 0x03f00100 - .dd 0x03e00101 - .dd 0x03d00102 - .dd 0x03c00103 - .dd 0x03b00104 - .dd 0x03a00105 - .dd 0x03900106 - .dd 0x03800107 - .dd 0x03100108 - .dd 0x03200109 - .dd 0x0330010a - .dd 0x0330010b - .dd 0x0350011c - .dd 0x0360010d - .dd 0x0370010e - .dd 0x0380010f - .dd 0x03900110 - .dd 0x31000111 - .dd 0x32000112 - .dd 0x33000113 - .dd 0x34000114 diff --git a/sim/testsuite/sim/bfin/c_progctrl_call_pcpr.s b/sim/testsuite/sim/bfin/c_progctrl_call_pcpr.s deleted file mode 100644 index 4cc5b29..0000000 --- a/sim/testsuite/sim/bfin/c_progctrl_call_pcpr.s +++ /dev/null @@ -1,63 +0,0 @@ -//Original:/testcases/core/c_progctrl_call_pcpr/c_progctrl_call_pcpr.dsp -// Spec Reference: progctrl call (pc+pr) -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - ASTAT = r0; - - FP = SP; - - P2 = 0x0006; - -JMP: - CALL ( PC + P2 ); - JUMP.S JMP; - -STOP: - JUMP.S END; - -LAB1: - P2 = 0x000e; - R1 = 0x1111 (X); - RTS; - -LAB2: - P2 = 0x0016; - R2 = 0x2222 (X); - RTS; - -LAB3: - P2 = 0x001e; - R3 = 0x3333 (X); - RTS; - -LAB4: - P2 = 0x0026; - R4 = 0x4444 (X); - RTS; - -LAB5: - P2 = 0x0004; - R5 = 0x5555 (X); - RTS; - -END: - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00001111; - CHECKREG r2, 0x00002222; - CHECKREG r3, 0x00003333; - CHECKREG r4, 0x00004444; - CHECKREG r5, 0x00005555; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000000; - - pass - - .data -DATA: - .space (0x0100); diff --git a/sim/testsuite/sim/bfin/c_progctrl_call_pr.s b/sim/testsuite/sim/bfin/c_progctrl_call_pr.s deleted file mode 100644 index be8278e..0000000 --- a/sim/testsuite/sim/bfin/c_progctrl_call_pr.s +++ /dev/null @@ -1,32 +0,0 @@ -//Original:/testcases/core/c_progctrl_call_pr/c_progctrl_call_pr.dsp -// Spec Reference: progctrl call (pr) -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - ASTAT = r0; - - FP = SP; - - loadsym P1, SUBR; - CALL ( P1 ); - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00001111; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000000; - - pass - -SUBR: // should jump here - R1.L = 0x1111; - RTS; - R2.L = 0x2222; // should not go here - RTS; diff --git a/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S b/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S deleted file mode 100644 index 78d6e67..0000000 --- a/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S +++ /dev/null @@ -1,330 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_progctrl_clisti_interr/c_progctrl_clisti_interr.dsp -// Spec Reference: CLI STI interrupt on HW TIMER -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Include Files -// - -include(std.inc) -include(selfcheck.inc) - -// Defines - -#ifndef TCNTL -#define TCNTL 0xFFE03000 -#endif -#ifndef TPERIOD -#define TPERIOD 0xFFE03004 -#endif -#ifndef TSCALE -#define TSCALE 0xFFE03008 -#endif -#ifndef TCOUNT -#define TCOUNT 0xFFE0300c -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203c -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0x000FF000 -#endif -#ifndef PROGRAM_STACK -#define PROGRAM_STACK 0x000FF100 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000300 -#endif - -// Boot code - - -INIT_R_REGS(0); // Initialize Dregs -INIT_P_REGS(0); // Initialize Pregs - - //CHECK_INIT(p5, 0xE0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - BOOT : - -LD32(sp, 0x000FF200); -LD32(p0, EVT); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE); // IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE); // IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE); // IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE); // IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE); // IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE); // IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -LD32_LABEL(p1, START); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken - -LD32_LABEL(r7, START); -RETI = r7; -NOP; // Workaround for Bug 217 -RTI; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -DUMMY: - NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - - START : - R7 = 0x0; - R6 = 0x1; - [ -- SP ] = RETI; // Enable Nested Interrupts - -CLI R1; // stop interrupt -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) -WR_MMR(TPERIOD, 0x00000050, p0, r0); -WR_MMR(TCOUNT, 0x00000013, p0, r0); -WR_MMR(TSCALE, 0x00000000, p0, r0); -CSYNC; - // Read the contents of the Timer - -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000050); - -// RD_MMR(TCOUNT, p0, r3); -// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 - - -WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) -CSYNC; - -NOP; NOP; NOP; -NOP; NOP; NOP; -NOP; NOP; NOP; -NOP; NOP; NOP; -NOP; NOP; NOP; -NOP; NOP; NOP; -NOP; NOP; NOP; -NOP; NOP; NOP; -RD_MMR(TPERIOD, p0, r4); -CHECKREG(r4, 0x00000050); - -// RD_MMR(TCNTL, p0, r5); -// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen - -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -NOP; -WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power -WR_MMR(TPERIOD, 0x00000015, p0, r0); -WR_MMR(TCOUNT, 0x00000013, p0, r0); -WR_MMR(TSCALE, 0x00000002, p0, r0); -WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) -CSYNC; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -JUMP.S label4; - R4.L = 0x1111; // Will be killed - R4.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -label5: R5.H = 0x7777; - R5.L = 0x7888; -JUMP.S label6; - R5.L = 0x1111; // Will be killed - R5.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -label4: R4.H = 0x5555; - R4.L = 0x6666; -NOP; -JUMP.S label5; - R5.L = 0x2222; // Will be killed - R5.H = 0x2222; // Will be killed -NOP; -NOP; -NOP; -NOP; -label6: R3.H = 0x7999; - R3.L = 0x7aaa; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - // With auto reload - // Read the contents of the Timer - -RD_MMR(TPERIOD, p0, r2); -CHECKREG(r2, 0x00000015); - -// RD_MMR(TCNTL , p0, r3); -// CHECKREG(r3, 0x0000000F); -NOP; -CHECKREG(r7, 0x00000000); // no interrupt being serviced -NOP; -STI R1; - -NOP; NOP; NOP; -NOP; NOP; NOP; -WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer -CSYNC; -NOP; NOP; NOP; - - - - - -dbg_pass; // Call Endtest Macro - - - -//********************************************************************* -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 - R7 = R7 + R6; -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler - R5 = RETI; - P0 = R5; -JUMP ( P0 ); -RTI; - -.section MEM_PROGRAM_STACK,"aw" - -.space (STACKSIZE); -STACK: -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S b/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S deleted file mode 100644 index 0aeccde..0000000 --- a/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S +++ /dev/null @@ -1,280 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_progctrl_csync_mmr/c_progctrl_csync_mmr.dsp -// Spec Reference: csync mmr timer -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -INIT_R_REGS(-1); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: - - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - // TCNTL: 4 bits, rw=1 = 0xFFE03000 -LD32(p0, 0xFFE03000); -LD32(r0, 0x00000001); - [ P0 ] = R0; -LD32(r0, 0x0000000D); - [ P0 ] = R0; -CSYNC; // without this it read out zero - R1 = [ P0 ]; - - // TPERIOD: 32 bits, rw=1 = 0xFFE03004 -LD32(p0, 0xFFE03004); -LD32(r0, 0x11112222); - [ P0 ] = R0; -CSYNC; // without this it read out zero - R2 = [ P0 ]; - - // TSCALE: 8 bits, rw=1 = 0xFFE03008 -LD32(p0, 0xFFE03008); -LD32(r0, 0x00000050); - [ P0 ] = R0; -CSYNC; // without this it read out zero - R3 = [ P0 ]; - - - // TCOUNT: 32 bits, rw=1 = 0xFFE0300C -LD32(p0, 0xFFE0300C); -LD32(r0, 0x00000100); - [ P0 ] = R0; -CSYNC; // without this it read out zero - R4 = [ P0 ]; - - -CHECKREG(r1, 0x0000000D); -CHECKREG(r2, 0x11112222); -CHECKREG(r3, 0x00000050); -CHECKREG(r4, 0x00000100); - -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = 2; -RTN; - -XHANDLE: // Exception Handler 3 - -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = 5; -RTI; - -THANDLE: // Timer Handler 6 - R3 = 6; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = 7; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = 8; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = 9; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_progctrl_except_rtx.S b/sim/testsuite/sim/bfin/c_progctrl_except_rtx.S deleted file mode 100644 index 9cacc28..0000000 --- a/sim/testsuite/sim/bfin/c_progctrl_except_rtx.S +++ /dev/null @@ -1,96 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_progctrl_except_rtx/c_progctrl_except_rtx.dsp -// Spec Reference: c_progctrl_except_rtx -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); -// load address of exception handler - -P0 = 0x200C (Z); // 0xFFE0200C EVT3 EXCEPTION -P0.H = 0xFFE0; -R0 = exception_handler (Z); // wr address of exception handler to MMR EVT3 -R0.H = exception_handler; -[ P0 ] = R0; - -// Jump to User mode and enable exceptions - -R0 = MidUserCode (Z); -R0.H = MidUserCode; -RETI = R0; -RTI; // cause it to go to Midusercode, .dd cause exception - -BeginUserCode: -P1 = 1; -P2 = 2; -P3 = 3; -P4 = 4; - -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000001); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000003); -CHECKREG(r5, 0x00000000); -CHECKREG(r6, 0x00000000); -CHECKREG(r7, 0x00000000); -CHECKREG(p1, 0x00000001); -CHECKREG(p2, 0x00000002); -CHECKREG(p3, 0x00000003); -CHECKREG(p4, 0x00000004); - -dbg_pass; -//jump 2; -//jump -2; -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF - -//dbg_pass; - -MidUserCode: -.dd 0xFFFFFFFF -R0 = 0; -R1 = 1; -R2 = 2; -R3 = 3; -CC = R0; -IF !CC JUMP BeginUserCode; - -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF -.dd 0xFFFFFFFF - - -exception_handler: -R4 = RETX; // error handler: RETX has the address of the same Illegal instr -R1 += 1; -R2 += 2; -R3 += 3; -R1 += 1; -R4 += 4; // we have to add 4 to point to next instr after return -RETX = R4; - -RTX; // return from exception - -.section MEM_DATA_ADDR_1,"aw" -.dd 0xDEADBEEF -.dd 0xBAD00BAD diff --git a/sim/testsuite/sim/bfin/c_progctrl_excpt.S b/sim/testsuite/sim/bfin/c_progctrl_excpt.S deleted file mode 100644 index 625a5c0..0000000 --- a/sim/testsuite/sim/bfin/c_progctrl_excpt.S +++ /dev/null @@ -1,261 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_progctrl_excpt/c_progctrl_excpt.dsp -// Spec Reference: progctrl excpt uimm4 -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: - - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -EXCPT 2; // RETX RTX - -CHECKREG(r0, 0x0000000A); -CHECKREG(r1, 0x0000000B); -CHECKREG(r2, 0x0000000C); -CHECKREG(r3, 0x0000000D); -CHECKREG(r4, 0x00000000); -CHECKREG(r5, 0x00000000); -CHECKREG(r6, 0x00000000); -CHECKREG(r7, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = 2; -RTN; - -XHANDLE: // Exception Handler 3 - R0 = 10; - R1 = 11; - R2 = 12; - R3 = 13; -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = 5; -RTI; - -THANDLE: // Timer Handler 6 - R3 = 6; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = 7; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = 8; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = 9; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s b/sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s deleted file mode 100644 index 727025c..0000000 --- a/sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s +++ /dev/null @@ -1,58 +0,0 @@ -//Original:/testcases/core/c_progctrl_jump_pcpr/c_progctrl_jump_pcpr.dsp -// Spec Reference: progctrl jump pc+pr -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -ASTAT = r0; - - P2 = 0x0004; - -JMP: - JUMP ( PC + P2 ); -// jump JMP; - -STOP: -JUMP.S END; - -LAB1: - P2 = 0x000c; - R1 = 0x1111 (X); -JUMP.S JMP; - -LAB2: - P2 = 0x0014; - R2 = 0x2222 (X); -JUMP.S JMP; - -LAB3: - P2 = 0x001c; - R3 = 0x3333 (X); -JUMP.S JMP; - -LAB4: - P2 = 0x0024; - R4 = 0x4444 (X); -JUMP.S JMP; - -LAB5: - P2 = 0x0002; - R5 = 0x5555 (X); -JUMP.S JMP; - -END: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00001111; -CHECKREG r2, 0x00002222; -CHECKREG r3, 0x00003333; -CHECKREG r4, 0x00004444; -CHECKREG r5, 0x00005555; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/c_progctrl_jump_pr.s b/sim/testsuite/sim/bfin/c_progctrl_jump_pr.s deleted file mode 100644 index 8b77c31..0000000 --- a/sim/testsuite/sim/bfin/c_progctrl_jump_pr.s +++ /dev/null @@ -1,56 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_progctrl_jump_pr/c_progctrl_jump_pr.dsp -// Spec Reference: progctrl jump(p) -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - ASTAT = r0; - - loadsym p1, LAB1; - loadsym p2, LAB2; - loadsym fp, LAB3; - loadsym p4, LAB4; - loadsym p5, LAB5; - - JUMP ( P1 ); - -STOP: - JUMP.S END; - -LAB1: - R1 = 0x1111 (X); - JUMP ( P5 ); - R6 = 0x6666 (X); - -LAB2: - R2 = 0x2222 (X); - JUMP.S STOP; - -LAB3: - R3 = 0x3333 (X); - JUMP ( P2 ); - R7 = 0x7777 (X); - -LAB4: - R4 = 0x4444 (X); - JUMP ( FP ); - -LAB5: - R5 = 0x5555 (X); - JUMP ( P4 ); - -END: - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00001111; - CHECKREG r2, 0x00002222; - CHECKREG r3, 0x00003333; - CHECKREG r4, 0x00004444; - CHECKREG r5, 0x00005555; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000000; - - pass diff --git a/sim/testsuite/sim/bfin/c_progctrl_nop.s b/sim/testsuite/sim/bfin/c_progctrl_nop.s deleted file mode 100644 index 77f744b..0000000 --- a/sim/testsuite/sim/bfin/c_progctrl_nop.s +++ /dev/null @@ -1,55 +0,0 @@ -//Original:/testcases/core/c_progctrl_nop/c_progctrl_nop.dsp -// Spec Reference: progctrl nop -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - - -I0 = 0x1122 (Z); -NOP; -R0 = I0; - -I1 = 0x3344 (Z); -NOP; -R1 = I1; - -I2 = 0x5566 (Z); -NOP; -R2 = I2; - -I3 = 0x7788 (Z); -NOP; -R3 = I3; - - -P2 = 0x99aa (Z); -NOP; NOP; -R4 = P2; - -P3 = 0xbbcc (Z); -NOP; NOP; -R5 = P3; - -P4 = 0xddee (Z); -NOP; NOP; -R6 = P4; - -P5 = 0x1234 (Z); -NOP; NOP; -R7 = P5; - -CHECKREG r0, 0x00001122; -CHECKREG r1, 0x00003344; -CHECKREG r2, 0x00005566; -CHECKREG r3, 0x00007788; -CHECKREG r4, 0x000099AA; -CHECKREG r5, 0x0000BBCC; -CHECKREG r6, 0x0000DDEE; -CHECKREG r7, 0x00001234; - - -pass diff --git a/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S b/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S deleted file mode 100644 index 9444f5d..0000000 --- a/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S +++ /dev/null @@ -1,285 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_progctrl_raise_rt_i_n/c_progctrl_raise_rt_i_n.dsp -// Spec Reference: progctrl raise rti rtn -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -CHECK_INIT(p5, 0xe0000000); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: - - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! - // Can't Raise 0, 3, or 4 - // Raise 1 requires some intelligence so the test - // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) -RAISE 2; // RTN -RAISE 5; // RTI -RAISE 6; // RTI -RAISE 7; // RTI -RAISE 8; // RTI -RAISE 9; // RTI -RAISE 10; // RTI -RAISE 11; // RTI -RAISE 12; // RTI -RAISE 13; // RTI -RAISE 14; // RTI -RAISE 15; // RTI - -CHECKREG(r0, 0x0000000B); -CHECKREG(r1, 0x0000000C); -CHECKREG(r2, 0x0000000D); -CHECKREG(r3, 0x0000000E); -CHECKREG(r4, 0x00000007); -CHECKREG(r5, 0x00000008); -CHECKREG(r6, 0x00000009); -CHECKREG(r7, 0x0000000A); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -CHECKREG(r0, 0x00000002); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000005); -CHECKREG(r3, 0x00000006); -CHECKREG(r4, 0x00000007); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R0 = 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - R2 = 5; -RTI; - -THANDLE: // Timer Handler 6 - R3 = 6; -RTI; - -I7HANDLE: // IVG 7 Handler - R4 = 7; -RTI; - -I8HANDLE: // IVG 8 Handler - R5 = 8; -RTI; - -I9HANDLE: // IVG 9 Handler - R6 = 9; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_progctrl_rts.s b/sim/testsuite/sim/bfin/c_progctrl_rts.s deleted file mode 100644 index 3aa3bed..0000000 --- a/sim/testsuite/sim/bfin/c_progctrl_rts.s +++ /dev/null @@ -1,36 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_progctrl_rts/c_progctrl_rts.dsp -// Spec Reference: progctrl rts -# mach: bfin - -.include "testutils.inc" - start - - INIT_R_REGS 0; - - ASTAT = r0; - - loadsym R2, SUBR; - RETS = R2; - RTS; - -STOP: - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r4, 0x00004444; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000000; - - pass - -SUBR: // should jump here - loadsym R3, STOP; - RETS = R3; - R4.L = 0x4444; - RTS; - RETS = R3; - R5.L = 0x5555; // should not go here - RTS; - - fail diff --git a/sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s b/sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s deleted file mode 100644 index 2d27849..0000000 --- a/sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s +++ /dev/null @@ -1,163 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_neg_pr/c_ptr2op_pr_neg_pr.dsp -// Spec Reference: ptr2op preg -= preg -# mach: bfin - -.include "testutils.inc" - start - -// check p-reg to p-reg move - imm32 p1, 0xf0021003; - imm32 p2, 0x2e041005; - imm32 p3, 0x20d61007; - imm32 p4, 0x200a1009; - imm32 p5, 0x200a300b; - imm32 sp, 0x200c180d; - imm32 fp, 0x200e109f; - P1 -= P1; - P2 -= P1; - P3 -= P1; - P4 -= P1; - P5 -= P1; - SP -= P1; - FP -= P1; - CHECKREG p1, 0x00000000; - CHECKREG p2, 0x2E041005; - CHECKREG p3, 0x20D61007; - CHECKREG p4, 0x200A1009; - CHECKREG p5, 0x200A300B; - CHECKREG sp, 0x200C180D; - CHECKREG fp, 0x200E109F; - - imm32 p1, 0x50021003; - imm32 p2, 0x26041005; - imm32 p3, 0x20761007; - imm32 p4, 0x20081009; - imm32 p5, 0x200a900b; - imm32 sp, 0x200c1a0d; - imm32 fp, 0x200e10bf; - P1 -= P2; - P2 -= P2; - P3 -= P2; - P4 -= P2; - P5 -= P2; - SP -= P2; - FP -= P2; - CHECKREG p1, 0x29FDFFFE; - CHECKREG p2, 0x00000000; - CHECKREG p3, 0x20761007; - CHECKREG p4, 0x20081009; - CHECKREG p5, 0x200A900B; - CHECKREG sp, 0x200C1A0D; - CHECKREG fp, 0x200E10BF; - - imm32 p1, 0x20021003; - imm32 p2, 0x20041005; - imm32 p3, 0x20061007; - imm32 p4, 0x20081009; - imm32 p5, 0x200a100b; - imm32 sp, 0x200c100d; - imm32 fp, 0x200e100f; - P1 -= P3; - P2 -= P3; - P3 -= P3; - P4 -= P3; - P5 -= P3; - SP -= P3; - FP -= P3; - CHECKREG p1, 0xFFFBFFFC; - CHECKREG p2, 0xFFFDFFFE; - CHECKREG p3, 0x00000000; - CHECKREG p4, 0x20081009; - CHECKREG p5, 0x200A100B; - CHECKREG sp, 0x200C100D; - CHECKREG fp, 0x200E100F; - - imm32 p1, 0xa0021003; - imm32 p2, 0x2c041005; - imm32 p3, 0x20b61007; - imm32 p4, 0x200d1009; - imm32 p5, 0x200ae00b; - imm32 sp, 0x200c110d; - imm32 fp, 0x200e104f; - P1 -= P4; - P2 -= P4; - P3 -= P4; - P4 -= P4; - P5 -= P4; - SP -= P4; - FP -= P4; - CHECKREG p1, 0x7FF4FFFA; - CHECKREG p2, 0x0BF6FFFC; - CHECKREG p3, 0x00A8FFFE; - CHECKREG p4, 0x00000000; - CHECKREG p5, 0x200AE00B; - CHECKREG sp, 0x200C110D; - CHECKREG fp, 0x200E104F; - - imm32 p1, 0x10021003; - imm32 p2, 0x22041005; - imm32 p3, 0x20361007; - imm32 p4, 0x20041009; - imm32 p5, 0x200aa00b; - imm32 sp, 0x200c1b0d; - imm32 fp, 0x200e10cf; - P1 -= P5; - P2 -= P5; - P3 -= P5; - P4 -= P5; - P5 -= P5; - SP -= P5; - FP -= P5; - CHECKREG p1, 0xEFF76FF8; - CHECKREG p2, 0x01F96FFA; - CHECKREG p3, 0x002B6FFC; - CHECKREG p4, 0xFFF96FFE; - CHECKREG p5, 0x00000000; - CHECKREG sp, 0x200C1B0D; - CHECKREG fp, 0x200E10CF; - - imm32 p1, 0x20021003; - imm32 p2, 0x20041005; - imm32 p3, 0x20061007; - imm32 p4, 0x20081009; - imm32 p5, 0x200a100b; - imm32 sp, 0x200c100d; - imm32 fp, 0x200e100f; - P1 -= SP; - P2 -= SP; - P3 -= SP; - P4 -= SP; - P5 -= SP; - SP -= SP; - FP -= SP; - CHECKREG p1, 0xFFF5FFF6; - CHECKREG p2, 0xFFF7FFF8; - CHECKREG p3, 0xFFF9FFFA; - CHECKREG p4, 0xFFFBFFFC; - CHECKREG p5, 0xFFFDFFFE; - CHECKREG sp, 0x00000000; - CHECKREG fp, 0x200E100F; - - imm32 p1, 0x20021003; - imm32 p2, 0x20041005; - imm32 p3, 0x20061007; - imm32 p4, 0x20081009; - imm32 p5, 0x200a100b; - imm32 sp, 0x200c100d; - imm32 fp, 0x200e100f; - P1 -= FP; - P2 -= FP; - P3 -= FP; - P4 -= FP; - P5 -= FP; - SP -= FP; - FP -= FP; - CHECKREG p1, 0xFFF3FFF4; - CHECKREG p2, 0xFFF5FFF6; - CHECKREG p3, 0xFFF7FFF8; - CHECKREG p4, 0xFFF9FFFA; - CHECKREG p5, 0xFFFBFFFC; - CHECKREG sp, 0xFFFDFFFE; - CHECKREG fp, 0x00000000; - - pass diff --git a/sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s b/sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s deleted file mode 100644 index dabd216..0000000 --- a/sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s +++ /dev/null @@ -1,162 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_sft_2_1/c_ptr2op_pr_sft_2_1.dsp -// Spec Reference: ptr2op preg = preg << 2 (>>2, >> 1) -# mach: bfin - -.include "testutils.inc" - start -// check p-reg to p-reg move - imm32 p1, 0xf0921203; - imm32 p2, 0xbe041305; - imm32 p3, 0xd0d61407; - imm32 p4, 0xa00a1089; - imm32 p5, 0x400a300b; - imm32 sp, 0xe07c180d; - imm32 fp, 0x206e109f; - P1 = P1 << 2; - P2 = P1 >> 2; - P3 = P1 << 2; - P4 = P1 >> 1; - P5 = P1 >> 2; - SP = P1 << 2; - FP = P1 >> 1; - CHECKREG p1, 0xC248480C; - CHECKREG p2, 0x30921203; - CHECKREG p3, 0x09212030; - CHECKREG p4, 0x61242406; - CHECKREG p5, 0x30921203; - CHECKREG sp, 0x09212030; - CHECKREG fp, 0x61242406; - - imm32 p1, 0x50021003; - imm32 p2, 0x26041005; - imm32 p3, 0x60761007; - imm32 p4, 0x20081009; - imm32 p5, 0xf00a900b; - imm32 sp, 0xb00c1a0d; - imm32 fp, 0x200e10bf; - P1 = P2; - P2 = P2; - P3 = P2; - P4 = P2; - P5 = P2; - SP = P2; - FP = P2; - CHECKREG p1, 0x26041005; - CHECKREG p2, 0x26041005; - CHECKREG p3, 0x26041005; - CHECKREG p4, 0x26041005; - CHECKREG p5, 0x26041005; - CHECKREG sp, 0x26041005; - CHECKREG fp, 0x26041005; - - imm32 p1, 0x20021003; - imm32 p2, 0x20041005; - imm32 p3, 0x20061007; - imm32 p4, 0x20081009; - imm32 p5, 0x200a100b; - imm32 sp, 0x200c100d; - imm32 fp, 0x200e100f; - P1 = P3 << 2; - P2 = P3 >> 1; - P3 = P3 >> 2; - P4 = P3 << 2; - P5 = P3 << 2; - SP = P3 >> 1; - FP = P3 << 2; - CHECKREG p1, 0x8018401C; - CHECKREG p2, 0x10030803; - CHECKREG p3, 0x08018401; - CHECKREG p4, 0x20061004; - CHECKREG p5, 0x20061004; - CHECKREG sp, 0x0400C200; - CHECKREG fp, 0x20061004; - - imm32 p1, 0xa0021003; - imm32 p2, 0x2c041005; - imm32 p3, 0x40b61007; - imm32 p4, 0x250d1009; - imm32 p5, 0x260ae00b; - imm32 sp, 0x700c110d; - imm32 fp, 0x900e104f; - P1 = P4 >> 1; - P2 = P4 << 2; - P3 = P4 << 2; - P4 = P4 >> 2; - P5 = P4 << 2; - SP = P4 >> 2; - FP = P4 << 2; - CHECKREG p1, 0x12868804; - CHECKREG p2, 0x94344024; - CHECKREG p3, 0x94344024; - CHECKREG p4, 0x09434402; - CHECKREG p5, 0x250D1008; - CHECKREG sp, 0x0250D100; - CHECKREG fp, 0x250D1008; - - imm32 p1, 0x10021003; - imm32 p2, 0x22041005; - imm32 p3, 0x20361007; - imm32 p4, 0x20041009; - imm32 p5, 0x200aa00b; - imm32 sp, 0x200c1b0d; - imm32 fp, 0x200e10cf; - P1 = P5 << 2; - P2 = P5 >> 2; - P3 = P5 << 2; - P4 = P5 << 2; - P5 = P5 >> 1; - SP = P5 >> 2; - FP = P5 << 2; - CHECKREG p1, 0x802A802C; - CHECKREG p2, 0x0802A802; - CHECKREG p3, 0x802A802C; - CHECKREG p4, 0x802A802C; - CHECKREG p5, 0x10055005; - CHECKREG sp, 0x04015401; - CHECKREG fp, 0x40154014; - - imm32 p1, 0x50021003; - imm32 p2, 0x62041005; - imm32 p3, 0x70e61007; - imm32 p4, 0x290f1009; - imm32 p5, 0x700ab00b; - imm32 sp, 0x2a0c1d0d; - imm32 fp, 0xb00e1e0f; - P1 = SP << 2; - P2 = SP << 2; - P3 = SP >> 2; - P4 = SP << 2; - P5 = SP >> 2; - SP = SP >> 1; - FP = SP >> 2; - CHECKREG p1, 0xA8307434; - CHECKREG p2, 0xA8307434; - CHECKREG p3, 0x0A830743; - CHECKREG p4, 0xA8307434; - CHECKREG p5, 0x0A830743; - CHECKREG sp, 0x15060E86; - CHECKREG fp, 0x054183A1; - - imm32 p1, 0x32002003; - imm32 p2, 0x24004005; - imm32 p3, 0x20506007; - imm32 p4, 0x20068009; - imm32 p5, 0x200ae00b; - imm32 sp, 0x200c1f0d; - imm32 fp, 0x200e10bf; - P1 = FP >> 2; - P2 = FP >> 1; - P3 = FP << 2; - P4 = FP >> 2; - P5 = FP << 2; - SP = FP >> 2; - FP = FP << 2; - CHECKREG p1, 0x0803842F; - CHECKREG p2, 0x1007085F; - CHECKREG p3, 0x803842FC; - CHECKREG p4, 0x0803842F; - CHECKREG p5, 0x803842FC; - CHECKREG sp, 0x0803842F; - CHECKREG fp, 0x803842FC; - - pass diff --git a/sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s b/sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s deleted file mode 100644 index dc6e2e8..0000000 --- a/sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s +++ /dev/null @@ -1,167 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_shadd_1_2/c_ptr2op_pr_shadd_1_2.dsp -// Spec Reference: ptr2op shadd preg, pregs, 1 (2) -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - -// check p-reg to p-reg move - - imm32 p1, 0xf0921203; - imm32 p2, 0xbe041305; - imm32 p3, 0xd0d61407; - imm32 p4, 0xa00a1089; - imm32 p5, 0x400a300b; - imm32 sp, 0xe07c180d; - imm32 fp, 0x206e109f; - P1 = ( P1 + P1 ) << 2; - P2 = ( P2 + P1 ) << 2; - P3 = ( P3 + P1 ) << 2; - P4 = ( P4 + P1 ) << 1; - P5 = ( P5 + P1 ) << 2; - SP = ( SP + P1 ) << 2; - FP = ( FP + P1 ) << 1; - CHECKREG p1, 0x84909018; - CHECKREG p2, 0x0A528C74; - CHECKREG p3, 0x559A907C; - CHECKREG p4, 0x49354142; - CHECKREG p5, 0x126B008C; - CHECKREG sp, 0x9432A094; - CHECKREG fp, 0x49FD416E; - - imm32 p1, 0x50021003; - imm32 p2, 0x26041005; - imm32 p3, 0x60761007; - imm32 p4, 0x20081009; - imm32 p5, 0xf00a900b; - imm32 sp, 0xb00c1a0d; - imm32 fp, 0x200e10bf; - P1 = ( P1 + P2 ) << 1; - P2 = ( P2 + P2 ) << 2; - P3 = ( P3 + P2 ) << 1; - P4 = ( P4 + P2 ) << 2; - P5 = ( P5 + P2 ) << 2; - SP = ( SP + P2 ) << 1; - FP = ( FP + P2 ) << 2; - CHECKREG p1, 0xEC0C4010; - CHECKREG p2, 0x30208028; - CHECKREG p3, 0x212D205E; - CHECKREG p4, 0x40A240C4; - CHECKREG p5, 0x80AC40CC; - CHECKREG sp, 0xC059346A; - CHECKREG fp, 0x40BA439C; - - imm32 p1, 0x30026003; - imm32 p2, 0x40051005; - imm32 p3, 0x20e65057; - imm32 p4, 0x2d081089; - imm32 p5, 0xf00ab07b; - imm32 sp, 0x200c1b0d; - imm32 fp, 0x200e100f; - P1 = ( P1 + P3 ) << 2; - P2 = ( P2 + P3 ) << 1; - P3 = ( P3 + P3 ) << 2; - P4 = ( P4 + P3 ) << 2; - P5 = ( P5 + P3 ) << 2; - SP = ( SP + P3 ) << 1; - FP = ( FP + P3 ) << 2; - CHECKREG p1, 0x43A2C168; - CHECKREG p2, 0xC1D6C0B8; - CHECKREG p3, 0x073282B8; - CHECKREG p4, 0xD0EA4D04; - CHECKREG p5, 0xDCF4CCCC; - CHECKREG sp, 0x4E7D3B8A; - CHECKREG fp, 0x9D024B1C; - - imm32 p1, 0xa0021003; - imm32 p2, 0x2c041005; - imm32 p3, 0x40b61007; - imm32 p4, 0x250d1009; - imm32 p5, 0x260ae00b; - imm32 sp, 0x700c110d; - imm32 fp, 0x900e104f; - P1 = ( P1 + P4 ) << 1; - P2 = ( P2 + P4 ) << 2; - P3 = ( P3 + P4 ) << 2; - P4 = ( P4 + P4 ) << 2; - P5 = ( P5 + P4 ) << 1; - SP = ( SP + P4 ) << 2; - FP = ( FP + P4 ) << 2; - CHECKREG p1, 0x8A1E4018; - CHECKREG p2, 0x44448038; - CHECKREG p3, 0x970C8040; - CHECKREG p4, 0x28688048; - CHECKREG p5, 0x9CE6C0A6; - CHECKREG sp, 0x61D24554; - CHECKREG fp, 0xE1DA425C; - - imm32 p1, 0xae021003; - imm32 p2, 0x22041705; - imm32 p3, 0x20361487; - imm32 p4, 0x90743009; - imm32 p5, 0xa60aa00b; - imm32 sp, 0xb00c1b0d; - imm32 fp, 0x200e10cf; - P1 = ( P1 + P5 ) << 2; - P2 = ( P2 + P5 ) << 2; - P3 = ( P3 + P5 ) << 2; - P4 = ( P4 + P5 ) << 2; - P5 = ( P5 + P5 ) << 1; - SP = ( SP + P5 ) << 2; - FP = ( FP + P5 ) << 2; - CHECKREG p1, 0x5032C038; - CHECKREG p2, 0x203ADC40; - CHECKREG p3, 0x1902D248; - CHECKREG p4, 0xD9FB4050; - CHECKREG p5, 0x982A802C; - CHECKREG sp, 0x20DA6CE4; - CHECKREG fp, 0xE0E243EC; - - imm32 p1, 0x50021003; - imm32 p2, 0x62041005; - imm32 p3, 0x70e61007; - imm32 p4, 0x290f1009; - imm32 p5, 0x700ab00b; - imm32 sp, 0x2a0c1d0d; - imm32 fp, 0xb00e1e0f; - P1 = ( P1 + SP ) << 2; - P2 = ( P2 + SP ) << 1; - P3 = ( P3 + SP ) << 2; - P4 = ( P4 + SP ) << 2; - P5 = ( P5 + SP ) << 2; - SP = ( SP + SP ) << 1; - FP = ( FP + SP ) << 2; - CHECKREG p1, 0xE838B440; - CHECKREG p2, 0x18205A24; - CHECKREG p3, 0x6BC8B450; - CHECKREG p4, 0x4C6CB458; - CHECKREG p5, 0x685B3460; - CHECKREG sp, 0xA8307434; - CHECKREG fp, 0x60FA490C; - - imm32 p1, 0x32002003; - imm32 p2, 0x24004005; - imm32 p3, 0xe0506007; - imm32 p4, 0xd0068009; - imm32 p5, 0x230ae00b; - imm32 sp, 0x205c1f0d; - imm32 fp, 0x200e10bf; - P1 = ( P1 + FP ) << 2; - P2 = ( P2 + FP ) << 1; - P3 = ( P3 + FP ) << 2; - P4 = ( P4 + FP ) << 2; - P5 = ( P5 + FP ) << 2; - SP = ( SP + FP ) << 2; - FP = ( FP + FP ) << 2; - CHECKREG p1, 0x4838C308; - CHECKREG p2, 0x881CA188; - CHECKREG p3, 0x0179C318; - CHECKREG p4, 0xC0524320; - CHECKREG p5, 0x0C63C328; - CHECKREG sp, 0x01A8BF30; - CHECKREG fp, 0x007085F8; - - pass diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s b/sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s deleted file mode 100644 index 5d7de57..0000000 --- a/sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s +++ /dev/null @@ -1,213 +0,0 @@ -//Original:/testcases/core/c_pushpopmultiple_dp/c_pushpopmultiple_dp.dsp -// Spec Reference: pushpopmultiple dreg preg single group -# mach: bfin - -.include "testutils.inc" - start - - FP = SP; - - imm32 r0, 0x00000000; - ASTAT = r0; - - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - - P1 = 0xa1 (X); - P2 = 0xa2 (X); - P3 = 0xa3 (X); - P4 = 0xa4 (X); - P5 = 0xa5 (X); - [ -- SP ] = ( R7:0 ); - [ -- SP ] = ( P5:1 ); - - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - - P2 = 0xb2 (X); - P3 = 0xb3 (X); - P4 = 0xb4 (X); - P5 = 0xb5 (X); - [ -- SP ] = ( R7:1 ); - [ -- SP ] = ( P5:2 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - - P3 = 0xc3 (X); - P4 = 0xc4 (X); - P5 = 0xc5 (X); - [ -- SP ] = ( R7:2 ); - [ -- SP ] = ( P5:3 ); - - R3 = 0x34; - R4 = 0x35; - R5 = 0x36; - R6 = 0x37; - R7 = 0x38; - - P4 = 0xd4 (X); - P5 = 0xd5 (X); - [ -- SP ] = ( R7:3 ); - [ -- SP ] = ( P5:4 ); - - R4 = 0x45 (X); - R5 = 0x46 (X); - R6 = 0x47 (X); - R7 = 0x48 (X); - P5 = 0xe5 (X); - [ -- SP ] = ( R7:4 ); - [ -- SP ] = ( P5:5 ); - - R5 = 0x56 (X); - R6 = 0x57 (X); - R7 = 0x58 (X); - [ -- SP ] = ( R7:5 ); - R6 = 0x67 (X); - R7 = 0x68 (X); - [ -- SP ] = ( R7:6 ); - R7 = 0x78 (X); - [ -- SP ] = ( R7:7 ); - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - R4 = 0; - R5 = 0; - R6 = 0; - R7 = 0; - P1 = 0; - P2 = 0; - P3 = 0; - P4 = 0; - P5 = 0; - ( R7:7 ) = [ SP ++ ]; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000078; - - ( R7:6 ) = [ SP ++ ]; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000067; - CHECKREG r7, 0x00000068; - - ( R7:5 ) = [ SP ++ ]; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000056; - CHECKREG r6, 0x00000057; - CHECKREG r7, 0x00000058; - - ( P5:5 ) = [ SP ++ ]; - ( R7:4 ) = [ SP ++ ]; - CHECKREG p1, 0x00000000; - CHECKREG p2, 0x00000000; - CHECKREG p3, 0x00000000; - CHECKREG p4, 0x00000000; - CHECKREG p5, 0x000000e5; - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000045; - CHECKREG r5, 0x00000046; - CHECKREG r6, 0x00000047; - CHECKREG r7, 0x00000048; - - ( P5:4 ) = [ SP ++ ]; - ( R7:3 ) = [ SP ++ ]; - CHECKREG p1, 0x00000000; - CHECKREG p2, 0x00000000; - CHECKREG p3, 0x00000000; - CHECKREG p4, 0x000000d4; - CHECKREG p5, 0x000000d5; - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000034; - CHECKREG r4, 0x00000035; - CHECKREG r5, 0x00000036; - CHECKREG r6, 0x00000037; - CHECKREG r7, 0x00000038; - - ( P5:3 ) = [ SP ++ ]; - ( R7:2 ) = [ SP ++ ]; - CHECKREG p1, 0x00000000; - CHECKREG p2, 0x00000000; - CHECKREG p3, 0x000000c3; - CHECKREG p4, 0x000000c4; - CHECKREG p5, 0x000000c5; - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000023; - CHECKREG r3, 0x00000024; - CHECKREG r4, 0x00000025; - CHECKREG r5, 0x00000026; - CHECKREG r6, 0x00000027; - CHECKREG r7, 0x00000028; - - ( P5:2 ) = [ SP ++ ]; - ( R7:1 ) = [ SP ++ ]; - CHECKREG p1, 0x00000000; - CHECKREG p2, 0x000000b2; - CHECKREG p3, 0x000000b3; - CHECKREG p4, 0x000000b4; - CHECKREG p5, 0x000000b5; - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000012; - CHECKREG r2, 0x00000013; - CHECKREG r3, 0x00000014; - CHECKREG r4, 0x00000015; - CHECKREG r5, 0x00000016; - CHECKREG r6, 0x00000017; - CHECKREG r7, 0x00000018; - - ( P5:1 ) = [ SP ++ ]; - ( R7:0 ) = [ SP ++ ]; - CHECKREG p1, 0x000000a1; - CHECKREG p2, 0x000000a2; - CHECKREG p3, 0x000000a3; - CHECKREG p4, 0x000000a4; - CHECKREG p5, 0x000000a5; - - CHECKREG r0, 0x00000001; - CHECKREG r1, 0x00000002; - CHECKREG r2, 0x00000003; - CHECKREG r3, 0x00000004; - CHECKREG r4, 0x00000005; - CHECKREG r5, 0x00000006; - CHECKREG r6, 0x00000007; - CHECKREG r7, 0x00000008; - pass diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s b/sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s deleted file mode 100644 index 78dae01..0000000 --- a/sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s +++ /dev/null @@ -1,203 +0,0 @@ -//Original:/testcases/core/c_pushpopmultiple_dp_pair/c_pushpopmultiple_dp_pair.dsp -// Spec Reference: pushpopmultiple dreg preg in group pair -# mach: bfin - -.include "testutils.inc" - start - - FP = SP; - - imm32 r0, 0x00000000; - ASTAT = r0; - - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - - P1 = 0xa1 (X); - P2 = 0xa2 (X); - P3 = 0xa3 (X); - P4 = 0xa4 (X); - P5 = 0xa5 (X); - [ -- SP ] = ( R7:0, P5:1 ); - - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - - P2 = 0xb2 (X); - P3 = 0xb3 (X); - P4 = 0xb4 (X); - P5 = 0xb5 (X); - [ -- SP ] = ( R7:1, P5:2 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - - P3 = 0xc3 (X); - P4 = 0xc4 (X); - P5 = 0xc5 (X); - [ -- SP ] = ( R7:2, P5:3 ); - - R3 = 0x34; - R4 = 0x35; - R5 = 0x36; - R6 = 0x37; - R7 = 0x38; - - P4 = 0xd4 (X); - P5 = 0xd5 (X); - [ -- SP ] = ( R7:3, P5:4 ); - - R4 = 0x45 (X); - R5 = 0x46 (X); - R6 = 0x47 (X); - R7 = 0x48 (X); - P5 = 0xe5 (X); - [ -- SP ] = ( R7:4, P5:5 ); - - R5 = 0x56 (X); - R6 = 0x57 (X); - R7 = 0x58 (X); - [ -- SP ] = ( R7:5 ); - R6 = 0x67 (X); - R7 = 0x68 (X); - [ -- SP ] = ( R7:6 ); - R7 = 0x78 (X); - [ -- SP ] = ( R7:7 ); - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - R4 = 0; - R5 = 0; - R6 = 0; - R7 = 0; - P1 = 0; - P2 = 0; - P3 = 0; - P4 = 0; - P5 = 0; - ( R7:7 ) = [ SP ++ ]; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000000; - CHECKREG r7, 0x00000078; - - ( R7:6 ) = [ SP ++ ]; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000067; - CHECKREG r7, 0x00000068; - - ( R7:5 ) = [ SP ++ ]; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000056; - CHECKREG r6, 0x00000057; - CHECKREG r7, 0x00000058; - - ( R7:4, P5:5 ) = [ SP ++ ]; - CHECKREG p1, 0x00000000; - CHECKREG p2, 0x00000000; - CHECKREG p3, 0x00000000; - CHECKREG p4, 0x00000000; - CHECKREG p5, 0x000000e5; - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000045; - CHECKREG r5, 0x00000046; - CHECKREG r6, 0x00000047; - CHECKREG r7, 0x00000048; - - ( R7:3, P5:4 ) = [ SP ++ ]; - CHECKREG p1, 0x00000000; - CHECKREG p2, 0x00000000; - CHECKREG p3, 0x00000000; - CHECKREG p4, 0x000000d4; - CHECKREG p5, 0x000000d5; - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000000; - CHECKREG r3, 0x00000034; - CHECKREG r4, 0x00000035; - CHECKREG r5, 0x00000036; - CHECKREG r6, 0x00000037; - CHECKREG r7, 0x00000038; - - ( R7:2, P5:3 ) = [ SP ++ ]; - CHECKREG p1, 0x00000000; - CHECKREG p2, 0x00000000; - CHECKREG p3, 0x000000c3; - CHECKREG p4, 0x000000c4; - CHECKREG p5, 0x000000c5; - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000000; - CHECKREG r2, 0x00000023; - CHECKREG r3, 0x00000024; - CHECKREG r4, 0x00000025; - CHECKREG r5, 0x00000026; - CHECKREG r6, 0x00000027; - CHECKREG r7, 0x00000028; - - ( R7:1, P5:2 ) = [ SP ++ ]; - CHECKREG p1, 0x00000000; - CHECKREG p2, 0x000000b2; - CHECKREG p3, 0x000000b3; - CHECKREG p4, 0x000000b4; - CHECKREG p5, 0x000000b5; - - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x00000012; - CHECKREG r2, 0x00000013; - CHECKREG r3, 0x00000014; - CHECKREG r4, 0x00000015; - CHECKREG r5, 0x00000016; - CHECKREG r6, 0x00000017; - CHECKREG r7, 0x00000018; - - ( R7:0, P5:1 ) = [ SP ++ ]; - CHECKREG p1, 0x000000a1; - CHECKREG p2, 0x000000a2; - CHECKREG p3, 0x000000a3; - CHECKREG p4, 0x000000a4; - CHECKREG p5, 0x000000a5; - - CHECKREG r0, 0x00000001; - CHECKREG r1, 0x00000002; - CHECKREG r2, 0x00000003; - CHECKREG r3, 0x00000004; - CHECKREG r4, 0x00000005; - CHECKREG r5, 0x00000006; - CHECKREG r6, 0x00000007; - CHECKREG r7, 0x00000008; - pass diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s b/sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s deleted file mode 100644 index ca1ebf1..0000000 --- a/sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s +++ /dev/null @@ -1,173 +0,0 @@ -//Original:/testcases/core/c_pushpopmultiple_dreg/c_pushpopmultiple_dreg.dsp -// Spec Reference: pushpopmultiple dreg -# mach: bfin - -.include "testutils.inc" - start - - FP = SP; - - imm32 r0, 0x00000000; - ASTAT = r0; - - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - [ -- SP ] = ( R7:0 ); - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - R4 = 0; - R5 = 0; - R6 = 0; - R7 = 0; - ( R7:0 ) = [ SP ++ ]; - CHECKREG r0, 0x00000001; - CHECKREG r1, 0x00000002; - CHECKREG r2, 0x00000003; - CHECKREG r3, 0x00000004; - CHECKREG r4, 0x00000005; - CHECKREG r5, 0x00000006; - CHECKREG r6, 0x00000007; - CHECKREG r7, 0x00000008; - - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - [ -- SP ] = ( R7:1 ); - R1 = 0; - R2 = 0; - R3 = 0; - R4 = 0; - R5 = 0; - R6 = 0; - R7 = 0; - ( R7:1 ) = [ SP ++ ]; - CHECKREG r0, 0x00000001; - CHECKREG r1, 0x00000012; - CHECKREG r2, 0x00000013; - CHECKREG r3, 0x00000014; - CHECKREG r4, 0x00000015; - CHECKREG r5, 0x00000016; - CHECKREG r6, 0x00000017; - CHECKREG r7, 0x00000018; - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - [ -- SP ] = ( R7:2 ); - R2 = 0; - R3 = 0; - R4 = 0; - R5 = 0; - R6 = 0; - R7 = 0; - ( R7:2 ) = [ SP ++ ]; - CHECKREG r0, 0x00000001; - CHECKREG r1, 0x00000012; - CHECKREG r2, 0x00000023; - CHECKREG r3, 0x00000024; - CHECKREG r4, 0x00000025; - CHECKREG r5, 0x00000026; - CHECKREG r6, 0x00000027; - CHECKREG r7, 0x00000028; - - R3 = 0x34; - R4 = 0x35; - R5 = 0x36; - R6 = 0x37; - R7 = 0x38; - [ -- SP ] = ( R7:3 ); - R3 = 0; - R4 = 0; - R5 = 0; - R6 = 0; - R7 = 0; - ( R7:3 ) = [ SP ++ ]; - CHECKREG r0, 0x00000001; - CHECKREG r1, 0x00000012; - CHECKREG r2, 0x00000023; - CHECKREG r3, 0x00000034; - CHECKREG r4, 0x00000035; - CHECKREG r5, 0x00000036; - CHECKREG r6, 0x00000037; - CHECKREG r7, 0x00000038; - - R4 = 0x45 (X); - R5 = 0x46 (X); - R6 = 0x47 (X); - R7 = 0x48 (X); - [ -- SP ] = ( R7:4 ); - R4 = 0; - R5 = 0; - R6 = 0; - R7 = 0; - ( R7:4 ) = [ SP ++ ]; - CHECKREG r0, 0x00000001; - CHECKREG r1, 0x00000012; - CHECKREG r2, 0x00000023; - CHECKREG r3, 0x00000034; - CHECKREG r4, 0x00000045; - CHECKREG r5, 0x00000046; - CHECKREG r6, 0x00000047; - CHECKREG r7, 0x00000048; - - R5 = 0x56 (X); - R6 = 0x57 (X); - R7 = 0x58 (X); - [ -- SP ] = ( R7:5 ); - R5 = 0; - R6 = 0; - R7 = 0; - ( R7:5 ) = [ SP ++ ]; - CHECKREG r0, 0x00000001; - CHECKREG r1, 0x00000012; - CHECKREG r2, 0x00000023; - CHECKREG r3, 0x00000034; - CHECKREG r4, 0x00000045; - CHECKREG r5, 0x00000056; - CHECKREG r6, 0x00000057; - CHECKREG r7, 0x00000058; - - R6 = 0x67 (X); - R7 = 0x68 (X); - [ -- SP ] = ( R7:6 ); - R6 = 0; - R7 = 0; - ( R7:6 ) = [ SP ++ ]; - CHECKREG r0, 0x00000001; - CHECKREG r1, 0x00000012; - CHECKREG r2, 0x00000023; - CHECKREG r3, 0x00000034; - CHECKREG r4, 0x00000045; - CHECKREG r5, 0x00000056; - CHECKREG r6, 0x00000067; - CHECKREG r7, 0x00000068; - - R7 = 0x78 (X); - [ -- SP ] = ( R7:7 ); - R7 = 0; - ( R7:7 ) = [ SP ++ ]; - CHECKREG r0, 0x00000001; - CHECKREG r1, 0x00000012; - CHECKREG r2, 0x00000023; - CHECKREG r3, 0x00000034; - CHECKREG r4, 0x00000045; - CHECKREG r5, 0x00000056; - CHECKREG r6, 0x00000067; - CHECKREG r7, 0x00000078; - - pass diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s b/sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s deleted file mode 100644 index 15c1937..0000000 --- a/sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s +++ /dev/null @@ -1,83 +0,0 @@ -//Original:/testcases/core/c_pushpopmultiple_preg/c_pushpopmultiple_preg.dsp -// Spec Reference: pushpopmultiple preg -# mach: bfin - -.include "testutils.inc" - start - - FP = SP; - - imm32 r0, 0x00000000; - ASTAT = r0; - - P1 = 0xa1 (X); - P2 = 0xa2 (X); - P3 = 0xa3 (X); - P4 = 0xa4 (X); - P5 = 0xa5 (X); - [ -- SP ] = ( P5:1 ); - P1 = 0; - P2 = 0; - P3 = 0; - P4 = 0; - P5 = 0; - ( P5:1 ) = [ SP ++ ]; - CHECKREG p1, 0x000000a1; - CHECKREG p2, 0x000000a2; - CHECKREG p3, 0x000000a3; - CHECKREG p4, 0x000000a4; - CHECKREG p5, 0x000000a5; - - P2 = 0xb2 (X); - P3 = 0xb3 (X); - P4 = 0xb4 (X); - P5 = 0xb5 (X); - [ -- SP ] = ( P5:2 ); - P2 = 0; - P3 = 0; - P4 = 0; - P5 = 0; - ( P5:2 ) = [ SP ++ ]; - CHECKREG p1, 0x000000a1; - CHECKREG p2, 0x000000b2; - CHECKREG p3, 0x000000b3; - CHECKREG p4, 0x000000b4; - CHECKREG p5, 0x000000b5; - - P3 = 0xc3 (X); - P4 = 0xc4 (X); - P5 = 0xc5 (X); - [ -- SP ] = ( P5:3 ); - P3 = 0; - P4 = 0; - P5 = 0; - ( P5:3 ) = [ SP ++ ]; - CHECKREG p1, 0x000000a1; - CHECKREG p2, 0x000000b2; - CHECKREG p3, 0x000000c3; - CHECKREG p4, 0x000000c4; - CHECKREG p5, 0x000000c5; - - P4 = 0xd4 (X); - P5 = 0xd5 (X); - [ -- SP ] = ( P5:4 ); - P4 = 0; - P5 = 0; - ( P5:4 ) = [ SP ++ ]; - CHECKREG p1, 0x000000a1; - CHECKREG p2, 0x000000b2; - CHECKREG p3, 0x000000c3; - CHECKREG p4, 0x000000d4; - CHECKREG p5, 0x000000d5; - - P5 = 0xe5 (X); - [ -- SP ] = ( P5:5 ); - P5 = 0; - ( P5:5 ) = [ SP ++ ]; - CHECKREG p1, 0x000000a1; - CHECKREG p2, 0x000000b2; - CHECKREG p3, 0x000000c3; - CHECKREG p4, 0x000000d4; - CHECKREG p5, 0x000000e5; - - pass diff --git a/sim/testsuite/sim/bfin/c_regmv_acc_acc.s b/sim/testsuite/sim/bfin/c_regmv_acc_acc.s deleted file mode 100644 index 08e4414..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_acc_acc.s +++ /dev/null @@ -1,125 +0,0 @@ -//Original:/testcases/core/c_regmv_acc_acc/c_regmv_acc_acc.dsp -// Spec Reference: regmv acc-acc -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0xa9627911; - imm32 r1, 0xd0158978; - imm32 r2, 0xc1234567; - imm32 r3, 0x10060007; - imm32 r4, 0x02080009; - imm32 r5, 0x003a000b; - imm32 r6, 0x0004000d; - imm32 r7, 0x000e500f; - A0 = R0; - - A1 = A0; - R2 = A1.w; - R3 = A1.x; - - A1.x = A0.w; - A1.w = A0.w; - A0.x = A0.w; - A0.w = A0.w; - R4 = A0.w; - R5 = A0.x; - R6 = A1.w; - R7 = A1.x; - - CHECKREG r0, 0xA9627911; - CHECKREG r1, 0xD0158978; - CHECKREG r2, 0xA9627911; - CHECKREG r3, 0xFFFFFFFF; - CHECKREG r4, 0xA9627911; - CHECKREG r5, 0x00000011; - CHECKREG r6, 0xA9627911; - CHECKREG r7, 0x00000011; - - imm32 r0, 0x90ba7911; - imm32 r1, 0xe3458978; - imm32 r2, 0xc1234567; - imm32 r3, 0x10060007; - imm32 r4, 0x56080009; - imm32 r5, 0x783a000b; - imm32 r6, 0xf247890d; - imm32 r7, 0x489e534f; - A1 = R0; - - A0 = A1; - R2 = A0.w; - R3 = A0.x; - - A0.x = A1.w; - A0.w = A1.w; - A1.x = A1.w; - A1.w = A1.w; - R4 = A0.w; - R5 = A0.x; - R6 = A1.w; - R7 = A1.x; - CHECKREG r0, 0x90BA7911; - CHECKREG r1, 0xE3458978; - CHECKREG r2, 0x90BA7911; - CHECKREG r3, 0xFFFFFFFF; - CHECKREG r4, 0x90BA7911; - CHECKREG r5, 0x00000011; - CHECKREG r6, 0x90BA7911; - CHECKREG r7, 0x00000011; - - imm32 r0, 0xf9627911; - imm32 r1, 0xd0158978; - imm32 r2, 0xc1234567; - imm32 r3, 0x10060007; - imm32 r4, 0x02080009; - imm32 r5, 0x003a000b; - imm32 r6, 0xf247890d; - imm32 r7, 0x789e534f; - A0 = R0; - - A0.x = A0.x; - A0.w = A0.x; - A1.w = A0.x; - A1.x = A0.x; - R4 = A0.w; - R5 = A0.x; - R6 = A1.w; - R7 = A1.x; - CHECKREG r0, 0xF9627911; - CHECKREG r1, 0xD0158978; - CHECKREG r2, 0xC1234567; - CHECKREG r3, 0x10060007; - CHECKREG r4, 0xFFFFFFFF; - CHECKREG r5, 0xFFFFFFFF; - CHECKREG r6, 0xFFFFFFFF; - CHECKREG r7, 0xFFFFFFFF; - - imm32 r0, 0x90ba7911; - imm32 r1, 0xe3458978; - imm32 r2, 0xc1234567; - imm32 r3, 0x10060007; - imm32 r4, 0x56080009; - imm32 r5, 0x783a000b; - imm32 r6, 0xf247890d; - imm32 r7, 0x489e534f; - A1 = R0; - - A0.x = A1.x; - A0.w = A1.x; - A1.w = A1.x; - A1.x = A1.x; - R4 = A0.w; - R5 = A0.x; - R6 = A1.w; - R7 = A1.x; - CHECKREG r0, 0x90BA7911; - CHECKREG r1, 0xE3458978; - CHECKREG r2, 0xC1234567; - CHECKREG r3, 0x10060007; - CHECKREG r4, 0xFFFFFFFF; - CHECKREG r5, 0xFFFFFFFF; - CHECKREG r6, 0xFFFFFFFF; - CHECKREG r7, 0xFFFFFFFF; - - pass diff --git a/sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s b/sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s deleted file mode 100644 index fb95a73..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s +++ /dev/null @@ -1,148 +0,0 @@ -//Original:/testcases/core/c_regmv_dag_lz_dep/c_regmv_dag_lz_dep.dsp -// Spec Reference: regmv dag lz dep forward -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -imm32 r0, 0x11111111; -imm32 r1, 0x22223331; -imm32 r2, 0x44445551; -imm32 r3, 0x66667771; -imm32 r4, 0x88889991; -imm32 r5, 0xaaaabbb1; -imm32 r6, 0xccccddd1; -imm32 r7, 0xeeeefff1; - -I0 = R0; -I0 = 0x1122 (Z); -R0 = I0; - -I1 = R1; -I1 = 0x3344 (Z); -R1 = I1; - -I2 = R2; -I2 = 0x5566 (Z); -R2 = I2; - -I3 = R3; -I3 = 0x7788 (Z); -R3 = I3; - - -B0 = R4; -B0 = 0x99aa (Z); -R4 = B0; - -B1 = R5; -B1 = 0xbbcc (Z); -R5 = B1; - -B2 = R6; -B2 = 0xddee (Z); -R6 = B2; - -B3 = R7; -B3 = 0xff01 (Z); -R7 = B3; - -CHECKREG r0, 0x00001122; -CHECKREG r1, 0x00003344; -CHECKREG r2, 0x00005566; -CHECKREG r3, 0x00007788; -CHECKREG r4, 0x000099AA; -CHECKREG r5, 0x0000BBCC; -CHECKREG r6, 0x0000DDEE; -CHECKREG r7, 0x0000FF01; - -imm32 r0, 0x11111112; -imm32 r1, 0x22223332; -imm32 r2, 0x44445552; -imm32 r3, 0x66667772; -imm32 r4, 0x88889992; -imm32 r5, 0xaaaabbb2; -imm32 r6, 0xccccddd2; -imm32 r7, 0xeeeefff2; -M0 = R0; -M0 = 0xa1a2 (Z); -R0 = M0; - -M1 = R1; -M1 = 0xb1b2 (Z); -R1 = M1; - -M2 = R2; -M2 = 0xc1c2 (Z); -R2 = M2; - -M3 = R3; -M3 = 0xd1d2 (Z); -R3 = M3; - - -L0 = R4; -L0 = 0xe1e2 (Z); -R4 = L0; - -L1 = R5; -L1 = 0xf1f2 (Z); -R5 = L1; - -L2 = R6; -L2 = 0x1112 (Z); -R6 = L2; - -L3 = R7; -L3 = 0x2122 (Z); -R7 = L3; - -CHECKREG r0, 0x0000A1A2; -CHECKREG r1, 0x0000B1B2; -CHECKREG r2, 0x0000C1C2; -CHECKREG r3, 0x0000D1D2; -CHECKREG r4, 0x0000E1E2; -CHECKREG r5, 0x0000F1F2; -CHECKREG r6, 0x00001112; -CHECKREG r7, 0x00002122; - -imm32 r0, 0x11111113; -imm32 r1, 0x22223333; -imm32 r2, 0x44445553; -imm32 r3, 0x66667773; -imm32 r4, 0x88889993; -imm32 r5, 0xaaaabbb3; -imm32 r6, 0xccccddd3; -imm32 r7, 0xeeeefff3; - -P1 = R1; -P1 = 0x3A3B (Z); -R1 = P1; - - -P2 = R2; -P2 = 0x4A4B (Z); -R2 = P2; - -P3 = R3; -P3 = 0x5A5B (Z); -R3 = P3; - -P4 = R4; -P4 = 0x6A6B (Z); -R4 = P4; - -P5 = R5; -P5 = 0x7A7B (Z); -R5 = P5; - -CHECKREG r1, 0x00003A3B; -CHECKREG r2, 0x00004A4B; -CHECKREG r3, 0x00005A5B; -CHECKREG r4, 0x00006A6B; -CHECKREG r5, 0x00007A7B; - -pass diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s b/sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s deleted file mode 100644 index 6af3d04..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s +++ /dev/null @@ -1,191 +0,0 @@ -//Original:/testcases/core/c_regmv_dr_acc_acc/c_regmv_dr_acc_acc.dsp -// Spec Reference: regmv dreg-acc-acc -# mach: bfin - -.include "testutils.inc" - start - - - -// check R-reg to ACC - imm32 r0, 0x00000000; - imm32 r1, 0x12345678; - imm32 r2, 0x91234567; - imm32 r3, 0x00060007; - imm32 r4, 0x00080009; - imm32 r5, 0x000a000b; - imm32 r6, 0x000c000d; - imm32 r7, 0x000e000f; - A0 = R0; - A1 = R0; - A0 = R1; - A1 = R2; - - R3 = A0.w; - R4 = A0.x; - R5 = A1.w; - R6 = A1.x; - CHECKREG r0, 0x00000000; - CHECKREG r1, 0x12345678; - CHECKREG r2, 0x91234567; - CHECKREG r3, 0x12345678; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x91234567; - CHECKREG r6, 0xFFFFFFFF; - CHECKREG r7, 0x000E000F; - - A1 = A0 = 0; - R3 = A0.w; - R4 = A0.x; - R5 = A1.w; - R6 = A1.x; - CHECKREG r3, 0x00000000; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x00000000; - - imm32 r0, 0xa5678901; - imm32 r1, 0xb0158978; - imm32 r2, 0x91234567; - imm32 r3, 0x10060007; - imm32 r4, 0x02080009; - imm32 r5, 0x003a000b; - imm32 r6, 0x0004000d; - imm32 r7, 0x000e500f; - A0 = R0; - A1 = R1; - - R3 = A0.w; - R4 = A0.x; - R5 = A1.w; - R6 = A1.x; - CHECKREG r0, 0xA5678901; - CHECKREG r1, 0xB0158978; - CHECKREG r2, 0x91234567; - CHECKREG r3, 0xA5678901; - CHECKREG r4, 0xFFFFFFFF; - CHECKREG r5, 0xB0158978; - CHECKREG r6, 0xFFFFFFFF; - CHECKREG r7, 0x000E500F; - - imm32 r0, 0xe9627911; - imm32 r1, 0xd0158978; - imm32 r2, 0xc1234567; - imm32 r3, 0x10060007; - imm32 r4, 0x02080009; - imm32 r5, 0x003a000b; - imm32 r6, 0x0004000d; - imm32 r7, 0x000e500f; - A0 = R0; - A1 = A0; - - imm32 r0, 0x90ba7911; - imm32 r1, 0xe3458978; - imm32 r2, 0xc1234567; - imm32 r3, 0x10060007; - imm32 r4, 0x56080009; - imm32 r5, 0x783a000b; - imm32 r6, 0xf247890d; - imm32 r7, 0x489e534f; - A0.w = R0; - A0.x = R1; - A1.w = R2; - A1.x = R3; - - R4 = A0.w; - R5 = A0.x; - R6 = A1.w; - R7 = A1.x; - - CHECKREG r0, 0x90BA7911; - CHECKREG r1, 0xE3458978; - CHECKREG r2, 0xC1234567; - CHECKREG r3, 0x10060007; - CHECKREG r4, 0x90BA7911; - CHECKREG r5, 0x00000078; - CHECKREG r6, 0xC1234567; - CHECKREG r7, 0x00000007; - - R3 = A0.w; - R4 = A0.x; - R5 = A1.w; - R6 = A1.x; - CHECKREG r0, 0x90BA7911; - CHECKREG r1, 0xE3458978; - CHECKREG r2, 0xC1234567; - CHECKREG r3, 0x90BA7911; - CHECKREG r4, 0x00000078; - CHECKREG r5, 0xC1234567; - CHECKREG r6, 0x00000007; - CHECKREG r7, 0x00000007; - - imm32 r0, 0xf9627911; - imm32 r1, 0xd0158978; - imm32 r2, 0xc1234567; - imm32 r3, 0x10060007; - imm32 r4, 0x02080009; - imm32 r5, 0x003a000b; - imm32 r6, 0xf247890d; - imm32 r7, 0x789e534f; - A0 = R6; - A1.w = A0.w; - A1.x = A0.x; - - R0 = A0.w; - R1 = A0.x; - R2 = A1.w; - R3 = A1.x; - - A1 = R7; - A0.w = A1.w; - A0.x = A1.x; - - R4 = A0.w; - R5 = A0.x; - R6 = A1.w; - R7 = A1.x; - - CHECKREG r0, 0xF247890D; - CHECKREG r1, 0xFFFFFFFF; - CHECKREG r2, 0xF247890D; - CHECKREG r3, 0xFFFFFFFF; - CHECKREG r4, 0x789E534F; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0x789E534F; - CHECKREG r7, 0x00000000; - - imm32 r0, 0x90ba7911; - imm32 r1, 0xe3458978; - imm32 r2, 0xc1234567; - imm32 r3, 0x10060007; - imm32 r4, 0x56080009; - imm32 r5, 0x783a000b; - imm32 r6, 0xf247890d; - imm32 r7, 0x489e534f; - A0.w = A1.x; - A0.x = A1.x; - R4 = A0.w; - R5 = A0.x; - - A0 = R2; - A1.w = A0.x; - A1.x = A0.x; - - R6 = A1.w; - R7 = A1.x; - - A0.x = A1.w; - A1.x = A0.w; - R0 = A0.x; - R1 = A1.x; - - CHECKREG r0, 0xFFFFFFFF; - CHECKREG r1, 0x00000067; - CHECKREG r2, 0xC1234567; - CHECKREG r3, 0x10060007; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x00000000; - CHECKREG r6, 0xFFFFFFFF; - CHECKREG r7, 0xFFFFFFFF; - - pass diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s b/sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s deleted file mode 100644 index 118274d..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s +++ /dev/null @@ -1,245 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_regmv_dr_dep_nostall/c_regmv_dr_dep_nostall.dsp -// Spec Reference: regmv dr-dep no stall -# mach: bfin - -.include "testutils.inc" - start - - imm32 r0, 0x00000001; - imm32 r1, 0x00110001; - imm32 r2, 0x00220002; - imm32 r3, 0x00330003; - imm32 r4, 0x00440004; - imm32 r5, 0x00550005; - imm32 r6, 0x00660006; - imm32 r7, 0x00770007; -// R-reg to R-reg: no stall - R0 = R0; - R1 = R0; - R2 = R1; - R3 = R2; - R4 = R3; - R5 = R4; - R6 = R5; - R7 = R6; - R0 = R7; - - CHECKREG r0, 0x00000001; - CHECKREG r1, 0x00000001; - CHECKREG r2, 0x00000001; - CHECKREG r3, 0x00000001; - CHECKREG r4, 0x00000001; - CHECKREG r5, 0x00000001; - CHECKREG r6, 0x00000001; - CHECKREG r7, 0x00000001; - -//imm32 p0, 0x00001111; - imm32 p1, 0x22223333; - imm32 p2, 0x44445555; - imm32 p3, 0x66667777; - imm32 p4, 0x88889999; - imm32 p5, 0xaaaabbbb; - imm32 fp, 0xccccdddd; - imm32 sp, 0xeeeeffff; - -// P-reg to R-reg to I,M reg: no stall - R0 = P0; - I0 = R0; - R1 = P1; - I1 = R1; - R2 = P2; - I2 = R2; - R3 = P3; - I3 = R3; - R4 = P4; - M0 = R4; - R5 = P5; - M1 = R5; - R6 = FP; - M2 = R6; - R7 = SP; - M3 = R7; - - CHECKREG r1, 0x22223333; - CHECKREG r2, 0x44445555; - CHECKREG r3, 0x66667777; - CHECKREG r4, 0x88889999; - CHECKREG r5, 0xAAAABBBB; - CHECKREG r6, 0xCCCCDDDD; - CHECKREG r7, 0xEEEEFFFF; - - R0 = M3; - R1 = M2; - R2 = M1; - R3 = M0; - R4 = I3; - R5 = I2; - R6 = I1; - R7 = I0; - CHECKREG r0, 0xEEEEFFFF; - CHECKREG r1, 0xCCCCDDDD; - CHECKREG r2, 0xAAAABBBB; - CHECKREG r3, 0x88889999; - CHECKREG r4, 0x66667777; - CHECKREG r5, 0x44445555; - CHECKREG r6, 0x22223333; - - imm32 i0, 0x00001111; - imm32 i1, 0x22223333; - imm32 i2, 0x44445555; - imm32 i3, 0x66667777; - imm32 m0, 0x88889999; - imm32 m0, 0xaaaabbbb; - imm32 m0, 0xccccdddd; - imm32 m0, 0xeeeeffff; - -// I,M-reg to R-reg to P-reg: no stall - R0 = I0; - P1 = R0; - R1 = I1; - P1 = R1; - R2 = I2; - P2 = R2; - R3 = I3; - P3 = R3; - R4 = M0; - P4 = R4; - R5 = M1; - P5 = R5; - R6 = M2; - SP = R6; - R7 = M3; - FP = R7; - - CHECKREG p1, 0x22223333; - CHECKREG p2, 0x44445555; - CHECKREG p3, 0x66667777; - CHECKREG p4, 0xEEEEFFFF; - CHECKREG p5, 0xAAAABBBB; - CHECKREG sp, 0xCCCCDDDD; - CHECKREG fp, 0xEEEEFFFF; - - imm32 i0, 0x10001111; - imm32 i1, 0x12221333; - imm32 i2, 0x14441555; - imm32 i3, 0x16661777; - imm32 m0, 0x18881999; - imm32 m1, 0x1aaa1bbb; - imm32 m2, 0x1ccc1ddd; - imm32 m3, 0x1eee1fff; - -// I,M-reg to R-reg to L,B reg: no stall - R0 = I0; - L0 = R0; - R1 = I1; - L1 = R1; - R2 = I2; - L2 = R2; - R3 = I3; - L3 = R3; - R4 = M0; - B0 = R4; - R5 = M1; - B1 = R5; - R6 = M2; - B2 = R6; - R7 = M3; - B3 = R7; - - CHECKREG r0, 0x10001111; - CHECKREG r1, 0x12221333; - CHECKREG r2, 0x14441555; - CHECKREG r3, 0x16661777; - CHECKREG r4, 0x18881999; - CHECKREG r5, 0x1AAA1BBB; - CHECKREG r6, 0x1CCC1DDD; - CHECKREG r7, 0x1EEE1FFF; - - R0 = L3; - R1 = L2; - R2 = L1; - R3 = L0; - R4 = B3; - R5 = B2; - R6 = B1; - R7 = B0; - CHECKREG r0, 0x16661777; - CHECKREG r1, 0x14441555; - CHECKREG r2, 0x12221333; - CHECKREG r3, 0x10001111; - CHECKREG r4, 0x1EEE1FFF; - CHECKREG r5, 0x1CCC1DDD; - CHECKREG r6, 0x1AAA1BBB; - CHECKREG r7, 0x18881999; - - imm32 l0, 0x20003111; - imm32 l1, 0x22223333; - imm32 l2, 0x24443555; - imm32 l3, 0x26663777; - imm32 b0, 0x28883999; - imm32 b0, 0x2aaa3bbb; - imm32 b0, 0x2ccc3ddd; - imm32 b0, 0x2eee3fff; - -// L,B-reg to R-reg to I,M reg: no stall - R0 = L0; - I0 = R0; - R1 = L1; - I1 = R1; - R2 = L2; - I2 = R2; - R3 = L3; - I3 = R3; - R4 = B0; - M0 = R4; - R5 = B1; - M1 = R5; - R6 = B2; - M2 = R6; - R7 = B3; - M3 = R7; - - R0 = M3; - R1 = M2; - R2 = M1; - R3 = M0; - R4 = I3; - R5 = I2; - R6 = I1; - R7 = I0; - CHECKREG r0, 0x1EEE1FFF; - CHECKREG r1, 0x1CCC1DDD; - CHECKREG r2, 0x1AAA1BBB; - CHECKREG r3, 0x2EEE3FFF; - CHECKREG r4, 0x26663777; - CHECKREG r5, 0x24443555; - CHECKREG r6, 0x22223333; - CHECKREG r7, 0x20003111; - - imm32 r0, 0x00000030; - imm32 r1, 0x00000031; - imm32 r2, 0x00000003; - imm32 r3, 0x00330003; - imm32 r4, 0x00440004; - imm32 r5, 0x00550005; - imm32 r6, 0x00660006; - imm32 r7, 0x00770007; - -// R-reg to R-reg to sysreg to Reg: no stall - R3 = R0; - ASTAT = R3; - R6 = ASTAT; - R4 = R1; - RETS = R4; - R7 = RETS; - - CHECKREG r0, 0x00000030; - CHECKREG r1, 0x00000031; - CHECKREG r2, 0x00000003; - CHECKREG r3, 0x00000030; - CHECKREG r4, 0x00000031; - CHECKREG r5, 0x00550005; - CHECKREG r6, 0x00000030; - CHECKREG r7, 0x00000031; - - pass diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_dr.s b/sim/testsuite/sim/bfin/c_regmv_dr_dr.s deleted file mode 100644 index e1fb658..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_dr_dr.s +++ /dev/null @@ -1,209 +0,0 @@ -//Original:/testcases/core/c_regmv_dr_dr/c_regmv_dr_dr.dsp -// Spec Reference: regmv dreg-to-dreg -# mach: bfin - -.include "testutils.inc" - start - -// check R-reg to R-reg move -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -R0 = R0; -R1 = R0; -R2 = R0; -R3 = R0; -R4 = R0; -R5 = R0; -R6 = R0; -R7 = R0; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000001; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -R0 = R1; -R1 = R1; -R2 = R1; -R3 = R1; -R4 = R1; -R5 = R1; -R6 = R1; -R7 = R1; -CHECKREG r0, 0x00020003; -CHECKREG r1, 0x00020003; -CHECKREG r2, 0x00020003; -CHECKREG r3, 0x00020003; -CHECKREG r4, 0x00020003; -CHECKREG r5, 0x00020003; -CHECKREG r6, 0x00020003; -CHECKREG r7, 0x00020003; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -R0 = R2; -R1 = R2; -R2 = R2; -R3 = R2; -R4 = R2; -R5 = R2; -R6 = R2; -R7 = R2; -CHECKREG r0, 0x00040005; -CHECKREG r1, 0x00040005; -CHECKREG r2, 0x00040005; -CHECKREG r3, 0x00040005; -CHECKREG r4, 0x00040005; -CHECKREG r5, 0x00040005; -CHECKREG r6, 0x00040005; -CHECKREG r7, 0x00040005; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -R0 = R3; -R1 = R3; -R2 = R3; -R3 = R3; -R4 = R3; -R5 = R3; -R6 = R3; -R7 = R3; -CHECKREG r0, 0x00060007; -CHECKREG r1, 0x00060007; -CHECKREG r2, 0x00060007; -CHECKREG r3, 0x00060007; -CHECKREG r4, 0x00060007; -CHECKREG r5, 0x00060007; -CHECKREG r6, 0x00060007; -CHECKREG r7, 0x00060007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -R0 = R4; -R1 = R4; -R2 = R4; -R3 = R4; -R4 = R4; -R5 = R4; -R6 = R4; -R7 = R4; -CHECKREG r0, 0x00080009; -CHECKREG r1, 0x00080009; -CHECKREG r2, 0x00080009; -CHECKREG r3, 0x00080009; -CHECKREG r4, 0x00080009; -CHECKREG r5, 0x00080009; -CHECKREG r6, 0x00080009; -CHECKREG r7, 0x00080009; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -R0 = R5; -R1 = R5; -R2 = R5; -R3 = R5; -R4 = R5; -R5 = R5; -R6 = R5; -R7 = R5; -CHECKREG r0, 0x000a000b; -CHECKREG r1, 0x000a000b; -CHECKREG r2, 0x000a000b; -CHECKREG r3, 0x000a000b; -CHECKREG r4, 0x000a000b; -CHECKREG r5, 0x000a000b; -CHECKREG r6, 0x000a000b; -CHECKREG r7, 0x000a000b; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -R0 = R6; -R1 = R6; -R2 = R6; -R3 = R6; -R4 = R6; -R5 = R6; -R6 = R6; -R7 = R6; -CHECKREG r0, 0x000c000d; -CHECKREG r1, 0x000c000d; -CHECKREG r2, 0x000c000d; -CHECKREG r3, 0x000c000d; -CHECKREG r4, 0x000c000d; -CHECKREG r5, 0x000c000d; -CHECKREG r6, 0x000c000d; -CHECKREG r7, 0x000c000d; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -R0 = R7; -R1 = R7; -R2 = R7; -R3 = R7; -R4 = R7; -R5 = R7; -R6 = R7; -R7 = R7; -CHECKREG r0, 0x000e000f; -CHECKREG r1, 0x000e000f; -CHECKREG r2, 0x000e000f; -CHECKREG r3, 0x000e000f; -CHECKREG r4, 0x000e000f; -CHECKREG r5, 0x000e000f; -CHECKREG r6, 0x000e000f; -CHECKREG r7, 0x000e000f; - -pass diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_imlb.s b/sim/testsuite/sim/bfin/c_regmv_dr_imlb.s deleted file mode 100644 index 01650b0..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_dr_imlb.s +++ /dev/null @@ -1,539 +0,0 @@ -//Original:/testcases/core/c_regmv_dr_imlb/c_regmv_dr_imlb.dsp -// Spec Reference: regmv dreg-to-imlb -# mach: bfin - -.include "testutils.inc" - start - -// check DR-reg to imlb-reg move -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -I0 = R0; -I1 = R0; -I2 = R0; -I3 = R0; -M0 = R0; -M1 = R0; -M2 = R0; -M3 = R0; - -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000001; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -I0 = R1; -I1 = R1; -I2 = R1; -I3 = R1; -M0 = R1; -M1 = R1; -M2 = R1; -M3 = R1; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x00020003; -CHECKREG r1, 0x00020003; -CHECKREG r2, 0x00020003; -CHECKREG r3, 0x00020003; -CHECKREG r4, 0x00020003; -CHECKREG r5, 0x00020003; -CHECKREG r6, 0x00020003; -CHECKREG r7, 0x00020003; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -I0 = R2; -I1 = R2; -I2 = R2; -I3 = R2; -M0 = R2; -M1 = R2; -M2 = R2; -M3 = R2; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x00040005; -CHECKREG r1, 0x00040005; -CHECKREG r2, 0x00040005; -CHECKREG r3, 0x00040005; -CHECKREG r4, 0x00040005; -CHECKREG r5, 0x00040005; -CHECKREG r6, 0x00040005; -CHECKREG r7, 0x00040005; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -I0 = R3; -I1 = R3; -I2 = R3; -I3 = R3; -M0 = R3; -M1 = R3; -M2 = R3; -M3 = R3; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x00060007; -CHECKREG r1, 0x00060007; -CHECKREG r2, 0x00060007; -CHECKREG r3, 0x00060007; -CHECKREG r4, 0x00060007; -CHECKREG r5, 0x00060007; -CHECKREG r6, 0x00060007; -CHECKREG r7, 0x00060007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -I0 = R4; -I1 = R4; -I2 = R4; -I3 = R4; -M0 = R4; -M1 = R4; -M2 = R4; -M3 = R4; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x00080009; -CHECKREG r1, 0x00080009; -CHECKREG r2, 0x00080009; -CHECKREG r3, 0x00080009; -CHECKREG r4, 0x00080009; -CHECKREG r5, 0x00080009; -CHECKREG r6, 0x00080009; -CHECKREG r7, 0x00080009; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -I0 = R5; -I1 = R5; -I2 = R5; -I3 = R5; -M0 = R5; -M1 = R5; -M2 = R5; -M3 = R5; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x000a000b; -CHECKREG r1, 0x000a000b; -CHECKREG r2, 0x000a000b; -CHECKREG r3, 0x000a000b; -CHECKREG r4, 0x000a000b; -CHECKREG r5, 0x000a000b; -CHECKREG r6, 0x000a000b; -CHECKREG r7, 0x000a000b; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -I0 = R6; -I1 = R6; -I2 = R6; -I3 = R6; -M0 = R6; -M1 = R6; -M2 = R6; -M3 = R6; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x000c000d; -CHECKREG r1, 0x000c000d; -CHECKREG r2, 0x000c000d; -CHECKREG r3, 0x000c000d; -CHECKREG r4, 0x000c000d; -CHECKREG r5, 0x000c000d; -CHECKREG r6, 0x000c000d; -CHECKREG r7, 0x000c000d; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -I0 = R7; -I1 = R7; -I2 = R7; -I3 = R7; -M0 = R7; -M1 = R7; -M2 = R7; -M3 = R7; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x000e000f; -CHECKREG r1, 0x000e000f; -CHECKREG r2, 0x000e000f; -CHECKREG r3, 0x000e000f; -CHECKREG r4, 0x000e000f; -CHECKREG r5, 0x000e000f; -CHECKREG r6, 0x000e000f; -CHECKREG r7, 0x000e000f; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -L0 = R0; -L1 = R0; -L2 = R0; -L3 = R0; -B0 = R0; -B1 = R0; -B2 = R0; -B3 = R0; - -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x00000001; -CHECKREG r1, 0x00000001; -CHECKREG r2, 0x00000001; -CHECKREG r3, 0x00000001; -CHECKREG r4, 0x00000001; -CHECKREG r5, 0x00000001; -CHECKREG r6, 0x00000001; -CHECKREG r7, 0x00000001; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -L0 = R1; -L1 = R1; -L2 = R1; -L3 = R1; -B0 = R1; -B1 = R1; -B2 = R1; -B3 = R1; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x00020003; -CHECKREG r1, 0x00020003; -CHECKREG r2, 0x00020003; -CHECKREG r3, 0x00020003; -CHECKREG r4, 0x00020003; -CHECKREG r5, 0x00020003; -CHECKREG r6, 0x00020003; -CHECKREG r7, 0x00020003; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -L0 = R2; -L1 = R2; -L2 = R2; -L3 = R2; -B0 = R2; -B1 = R2; -B2 = R2; -B3 = R2; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x00040005; -CHECKREG r1, 0x00040005; -CHECKREG r2, 0x00040005; -CHECKREG r3, 0x00040005; -CHECKREG r4, 0x00040005; -CHECKREG r5, 0x00040005; -CHECKREG r6, 0x00040005; -CHECKREG r7, 0x00040005; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -L0 = R3; -L1 = R3; -L2 = R3; -L3 = R3; -B0 = R3; -B1 = R3; -B2 = R3; -B3 = R3; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x00060007; -CHECKREG r1, 0x00060007; -CHECKREG r2, 0x00060007; -CHECKREG r3, 0x00060007; -CHECKREG r4, 0x00060007; -CHECKREG r5, 0x00060007; -CHECKREG r6, 0x00060007; -CHECKREG r7, 0x00060007; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -L0 = R4; -L1 = R4; -L2 = R4; -L3 = R4; -B0 = R4; -B1 = R4; -B2 = R4; -B3 = R4; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x00080009; -CHECKREG r1, 0x00080009; -CHECKREG r2, 0x00080009; -CHECKREG r3, 0x00080009; -CHECKREG r4, 0x00080009; -CHECKREG r5, 0x00080009; -CHECKREG r6, 0x00080009; -CHECKREG r7, 0x00080009; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -L0 = R5; -L1 = R5; -L2 = R5; -L3 = R5; -B0 = R5; -B1 = R5; -B2 = R5; -B3 = R5; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x000a000b; -CHECKREG r1, 0x000a000b; -CHECKREG r2, 0x000a000b; -CHECKREG r3, 0x000a000b; -CHECKREG r4, 0x000a000b; -CHECKREG r5, 0x000a000b; -CHECKREG r6, 0x000a000b; -CHECKREG r7, 0x000a000b; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -L0 = R6; -L1 = R6; -L2 = R6; -L3 = R6; -B0 = R6; -B1 = R6; -B2 = R6; -B3 = R6; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x000c000d; -CHECKREG r1, 0x000c000d; -CHECKREG r2, 0x000c000d; -CHECKREG r3, 0x000c000d; -CHECKREG r4, 0x000c000d; -CHECKREG r5, 0x000c000d; -CHECKREG r6, 0x000c000d; -CHECKREG r7, 0x000c000d; - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; -L0 = R7; -L1 = R7; -L2 = R7; -L3 = R7; -B0 = R7; -B1 = R7; -B2 = R7; -B3 = R7; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x000e000f; -CHECKREG r1, 0x000e000f; -CHECKREG r2, 0x000e000f; -CHECKREG r3, 0x000e000f; -CHECKREG r4, 0x000e000f; -CHECKREG r5, 0x000e000f; -CHECKREG r6, 0x000e000f; -CHECKREG r7, 0x000e000f; - -pass diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_pr.s b/sim/testsuite/sim/bfin/c_regmv_dr_pr.s deleted file mode 100644 index fd8967c..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_dr_pr.s +++ /dev/null @@ -1,107 +0,0 @@ -//Original:/testcases/core/c_regmv_dr_pr/c_regmv_dr_pr.dsp -// Spec Reference: regmv dreg-to-preg -# mach: bfin - -.include "testutils.inc" - start - -// check R-reg to R-reg move - imm32 r0, 0x20001001; - imm32 r1, 0x20021003; - imm32 r2, 0x20041005; - imm32 r3, 0x20061007; - imm32 r4, 0x20081009; - imm32 r5, 0x200a100b; - imm32 r6, 0x200c100d; - imm32 r7, 0x200e100f; - - P1 = R0; - P2 = R0; - P4 = R0; - P5 = R0; - FP = R0; - CHECKREG p1, 0x20001001; - CHECKREG p2, 0x20001001; - CHECKREG p4, 0x20001001; - CHECKREG p5, 0x20001001; - CHECKREG fp, 0x20001001; - - P1 = R1; - P2 = R1; - P4 = R1; - P5 = R1; - FP = R1; - CHECKREG p1, 0x20021003; - CHECKREG p2, 0x20021003; - CHECKREG p4, 0x20021003; - CHECKREG p5, 0x20021003; - CHECKREG fp, 0x20021003; - - P1 = R2; - P2 = R2; - P4 = R2; - P5 = R2; - FP = R2; - CHECKREG p1, 0x20041005; - CHECKREG p2, 0x20041005; - CHECKREG p4, 0x20041005; - CHECKREG p5, 0x20041005; - CHECKREG fp, 0x20041005; - - P1 = R3; - P2 = R3; - P4 = R3; - P5 = R3; - FP = R3; - CHECKREG p1, 0x20061007; - CHECKREG p2, 0x20061007; - CHECKREG p4, 0x20061007; - CHECKREG p5, 0x20061007; - CHECKREG fp, 0x20061007; - - P1 = R4; - P2 = R4; - P4 = R4; - P5 = R4; - FP = R4; - CHECKREG p1, 0x20081009; - CHECKREG p2, 0x20081009; - CHECKREG p4, 0x20081009; - CHECKREG p5, 0x20081009; - CHECKREG fp, 0x20081009; - - P1 = R5; - P2 = R5; - P4 = R5; - P5 = R5; - FP = R5; - CHECKREG p1, 0x200a100b; - CHECKREG p2, 0x200a100b; - CHECKREG p4, 0x200a100b; - CHECKREG p5, 0x200a100b; - CHECKREG fp, 0x200a100b; - - P1 = R6; - P2 = R6; - P4 = R6; - P5 = R6; - FP = R6; - CHECKREG p1, 0x200c100d; - CHECKREG p2, 0x200c100d; - CHECKREG p4, 0x200c100d; - CHECKREG p5, 0x200c100d; - CHECKREG fp, 0x200c100d; - - P1 = R7; - P2 = R7; - P4 = R7; - P5 = R7; - FP = R7; - CHECKREG p1, 0x200e100f; - CHECKREG p2, 0x200e100f; - CHECKREG p4, 0x200e100f; - CHECKREG p5, 0x200e100f; - CHECKREG fp, 0x200e100f; - -End: - pass diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s b/sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s deleted file mode 100644 index cda1fb1..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s +++ /dev/null @@ -1,664 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_nostall/c_regmv_imlb_dep_nostall.dsp -// Spec Reference: regmv imlb-dep no stall -# mach: bfin - -.include "testutils.inc" - start - -// P-reg to I,M-reg to R-reg: no stall -//imm32 p0, 0x00001111; - imm32 p1, 0x12213330; - imm32 p2, 0x14415550; - imm32 p3, 0x16617770; - imm32 p4, 0x18819990; - imm32 p5, 0x1aa1bbb0; - imm32 fp, 0x1cc1ddd0; - imm32 sp, 0x1ee1fff0; - I0 = P0; - R0 = I0; - I1 = P1; - R1 = I1; - I2 = P2; - R2 = I2; - I3 = P3; - R3 = I3; - M0 = P4; - R4 = M0; - M1 = P5; - R5 = M1; - M2 = SP; - R6 = M2; - M3 = FP; - R7 = M3; - - CHECKREG r1, 0x12213330; - CHECKREG r2, 0x14415550; - CHECKREG r3, 0x16617770; - CHECKREG r4, 0x18819990; - CHECKREG r5, 0x1aa1bbb0; - CHECKREG r6, 0x1EE1FFF0; - CHECKREG r7, 0x1CC1DDD0; - - R0 = M3; - R1 = M2; - R2 = M1; - R3 = M0; - R4 = I3; - R5 = I2; - R6 = I1; - R7 = I0; - CHECKREG r0, 0x1CC1DDD0; - CHECKREG r1, 0x1EE1FFF0; - CHECKREG r2, 0x1AA1BBB0; - CHECKREG r3, 0x18819990; - CHECKREG r4, 0x16617770; - CHECKREG r5, 0x14415550; - CHECKREG r6, 0x12213330; - -// P-reg to L,B-reg to R-reg: no stall -//imm32 p0, 0x00001111; - imm32 p1, 0x21213331; - imm32 p2, 0x21415551; - imm32 p3, 0x21617771; - imm32 p4, 0x21819991; - imm32 p5, 0x21a1bbb1; - imm32 fp, 0x21c1ddd1; - imm32 sp, 0x21e1fff1; - L0 = P0; - R0 = L0; - L1 = P1; - R1 = L1; - L2 = P2; - R2 = L2; - L3 = P3; - R3 = L3; - B0 = P4; - R4 = B0; - B1 = P5; - R5 = B1; - B2 = SP; - R6 = B2; - B3 = FP; - R7 = B3; - - CHECKREG r1, 0x21213331; - CHECKREG r2, 0x21415551; - CHECKREG r3, 0x21617771; - CHECKREG r4, 0x21819991; - CHECKREG r5, 0x21a1bbb1; - CHECKREG r6, 0x21E1FFF1; - CHECKREG r7, 0x21C1DDD1; - - R0 = L3; - R1 = L2; - R2 = L1; - R3 = L0; - R4 = B3; - R5 = B2; - R6 = B1; - R7 = B0; - CHECKREG r0, 0x21617771; - CHECKREG r1, 0x21415551; - CHECKREG r2, 0x21213331; - CHECKREG r4, 0x21C1DDD1; - CHECKREG r5, 0x21E1FFF1; - CHECKREG r6, 0x21A1BBB1; - CHECKREG r7, 0x21819991; - -// P-reg to I,M-reg to L,B-reg: no stall -//imm32 p0, 0x00001111; - imm32 p1, 0x72213337; - imm32 p2, 0x74415557; - imm32 p3, 0x76617777; - imm32 p4, 0x78819997; - imm32 p5, 0x7aa1bbb7; - imm32 fp, 0x7cc1ddd7; - imm32 sp, 0x77e1fff7; - I0 = P0; - L0 = I0; - I1 = P1; - L1 = I1; - I2 = P2; - L2 = I2; - I3 = P3; - L3 = I3; - M0 = P4; - B0 = M0; - M1 = P5; - B1 = M1; - M2 = SP; - B2 = M2; - M3 = FP; - B3 = M3; - - R0 = L3; - R1 = L2; - R2 = L1; - R3 = L0; - R4 = B3; - R5 = B2; - R6 = B1; - R7 = B0; - CHECKREG r0, 0x76617777; - CHECKREG r1, 0x74415557; - CHECKREG r2, 0x72213337; - CHECKREG r4, 0x7CC1DDD7; - CHECKREG r5, 0x77E1FFF7; - CHECKREG r6, 0x7AA1BBB7; - CHECKREG r7, 0x78819997; - - R0 = M3; - R1 = M2; - R2 = M1; - R3 = M0; - R4 = I3; - R5 = I2; - R6 = I1; - R7 = I0; - CHECKREG r0, 0x7CC1DDD7; - CHECKREG r1, 0x77E1FFF7; - CHECKREG r2, 0x7AA1BBB7; - CHECKREG r3, 0x78819997; - CHECKREG r4, 0x76617777; - CHECKREG r5, 0x74415557; - CHECKREG r6, 0x72213337; - -// P-reg to L,B-reg to I,Mreg: no stall -//imm32 p0, 0x00001111; - imm32 p1, 0x81213338; - imm32 p2, 0x81415558; - imm32 p3, 0x81617778; - imm32 p4, 0x81819998; - imm32 p5, 0x81a1bbb8; - imm32 fp, 0x81c1ddd8; - imm32 sp, 0x81e1fff8; - L0 = P0; - I0 = L0; - L1 = P1; - I1 = L1; - L2 = P2; - I2 = L2; - L3 = P3; - I3 = L3; - B0 = P4; - M0 = B0; - B1 = P5; - M1 = B1; - B2 = SP; - M2 = B2; - B3 = FP; - M3 = B3; - - R0 = M0; - R1 = M1; - R2 = M2; - R3 = M3; - R4 = I0; - R5 = I1; - R6 = I2; - R7 = I3; - CHECKREG r0, 0x81819998; - CHECKREG r1, 0x81A1BBB8; - CHECKREG r2, 0x81E1FFF8; - CHECKREG r3, 0x81C1DDD8; - CHECKREG r5, 0x81213338; - CHECKREG r6, 0x81415558; - CHECKREG r7, 0x81617778; - - R0 = L3; - R1 = L2; - R2 = L1; - R3 = L0; - R4 = B3; - R5 = B2; - R6 = B1; - R7 = B0; - CHECKREG r0, 0x81617778; - CHECKREG r1, 0x81415558; - CHECKREG r2, 0x81213338; - CHECKREG r4, 0x81C1DDD8; - CHECKREG r5, 0x81E1FFF8; - CHECKREG r6, 0x81A1BBB8; - CHECKREG r7, 0x81819998; - -// I-to-M, I-to-I and to R-reg: no stall - imm32 i0, 0x30001111; - imm32 i1, 0x23213332; - imm32 i2, 0x14315552; - imm32 i3, 0x01637772; - imm32 m0, 0x80113992; - imm32 m1, 0xaa01b3b2; - imm32 m2, 0xccc01d32; - imm32 m3, 0xeee101f3; - M0 = I0; - R4 = M0; - M1 = I1; - R5 = M1; - M2 = I2; - R6 = M2; - M3 = I3; - R7 = M3; - I0 = I3; - R0 = I0; - I1 = I2; - R1 = I1; - I3 = I0; - R2 = I3; - I2 = I1; - R3 = I2; - - CHECKREG r0, 0x01637772; - CHECKREG r1, 0x14315552; - CHECKREG r2, 0x01637772; - CHECKREG r3, 0x14315552; - CHECKREG r4, 0x30001111; - CHECKREG r5, 0x23213332; - CHECKREG r6, 0x14315552; - CHECKREG r7, 0x01637772; - R0 = M0; - R1 = M1; - R2 = M2; - R3 = M3; - R4 = I0; - R5 = I1; - R6 = I2; - R7 = I3; - CHECKREG r0, 0x30001111; - CHECKREG r1, 0x23213332; - CHECKREG r2, 0x14315552; - CHECKREG r3, 0x01637772; - CHECKREG r4, 0x01637772; - CHECKREG r5, 0x14315552; - CHECKREG r6, 0x14315552; - CHECKREG r7, 0x01637772; - -// I-to-M, I-to-I and to P-reg: no stall - imm32 i0, 0x00001111; - imm32 i1, 0x42213342; - imm32 i2, 0x44415542; - imm32 i3, 0x46617742; - imm32 m0, 0x48819942; - imm32 m1, 0x4aa1bb42; - imm32 m2, 0x4cc1dd42; - imm32 m3, 0x4ee1ff42; - M0 = I0; - R0 = M0; - M1 = I1; - P1 = M1; - M2 = I2; - P2 = M2; - M3 = I3; - P3 = M3; - I0 = I3; - P4 = I0; - I1 = I2; - P5 = I1; - I2 = I0; - SP = I2; - I3 = I1; - FP = I3; - - CHECKREG r0, 0x00001111; - CHECKREG p1, 0x42213342; - CHECKREG p2, 0x44415542; - CHECKREG p3, 0x46617742; - CHECKREG p4, 0x46617742; - CHECKREG p5, 0x44415542; - CHECKREG sp, 0x46617742; - CHECKREG fp, 0x44415542; - R0 = M0; - R1 = M1; - R2 = M2; - R3 = M3; - R4 = I0; - R5 = I1; - R6 = I2; - R7 = I3; - CHECKREG r0, 0x00001111; - CHECKREG r1, 0x42213342; - CHECKREG r2, 0x44415542; - CHECKREG r3, 0x46617742; - CHECKREG r4, 0x46617742; - CHECKREG r5, 0x44415542; - CHECKREG r6, 0x46617742; - CHECKREG r7, 0x44415542; - -// L-to-B, L-to-L and to R-reg: no stall - imm32 l0, 0x40001114; - imm32 l1, 0x24213334; - imm32 l2, 0x54415554; - imm32 l3, 0x05647774; - imm32 b0, 0x60514994; - imm32 b1, 0xa605b4b4; - imm32 b2, 0xcc605d44; - imm32 b3, 0xeee605f4; - B0 = L0; - R4 = B0; - B1 = L1; - R5 = B1; - B2 = L2; - R6 = B2; - B3 = L3; - R7 = B3; - L0 = L3; - R0 = L0; - L1 = L2; - R1 = L1; - L3 = L0; - R2 = L3; - L2 = L1; - R3 = L2; - - CHECKREG r0, 0x05647774; - CHECKREG r1, 0x54415554; - CHECKREG r2, 0x05647774; - CHECKREG r3, 0x54415554; - CHECKREG r4, 0x40001114; - CHECKREG r5, 0x24213334; - CHECKREG r6, 0x54415554; - CHECKREG r7, 0x05647774; - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - CHECKREG r0, 0x05647774; - CHECKREG r1, 0x54415554; - CHECKREG r2, 0x54415554; - CHECKREG r3, 0x05647774; - CHECKREG r4, 0x40001114; - CHECKREG r5, 0x24213334; - CHECKREG r6, 0x54415554; - CHECKREG r7, 0x05647774; - -// L-to-B, L-to-L and to P-reg: no stall - imm32 l0, 0x60001116; - imm32 l1, 0x46213346; - imm32 l2, 0x74615546; - imm32 l3, 0x47667746; - imm32 b0, 0x48716946; - imm32 b1, 0x8aa7b646; - imm32 b2, 0x48c17d66; - imm32 b3, 0x4e81f746; - M0 = I0; - R0 = M0; - M1 = I1; - P1 = M1; - M2 = I2; - P2 = M2; - M3 = I3; - P3 = M3; - I0 = I3; - P4 = I0; - I1 = I2; - P5 = I1; - I2 = I0; - SP = I2; - I3 = I1; - FP = I3; - - CHECKREG r0, 0x46617742; - CHECKREG p1, 0x44415542; - CHECKREG p2, 0x46617742; - CHECKREG p3, 0x44415542; - CHECKREG p4, 0x44415542; - CHECKREG p5, 0x46617742; - CHECKREG sp, 0x44415542; - CHECKREG fp, 0x46617742; - R0 = M0; - R1 = M1; - R2 = M2; - R3 = M3; - R4 = I0; - R5 = I1; - R6 = I2; - R7 = I3; - CHECKREG r0, 0x46617742; - CHECKREG r1, 0x44415542; - CHECKREG r2, 0x46617742; - CHECKREG r3, 0x44415542; - CHECKREG r4, 0x44415542; - CHECKREG r5, 0x46617742; - CHECKREG r6, 0x44415542; - CHECKREG r7, 0x46617742; - -// I-to-M-to-L, I-to-I-to-B -reg: no stall - imm32 i0, 0x90001119; - imm32 i1, 0x93213339; - imm32 i2, 0x94315559; - imm32 i3, 0x91637779; - imm32 m0, 0x90113999; - imm32 m1, 0x9a01b3b9; - imm32 m2, 0x9cc01d39; - imm32 m3, 0x9ee101f9; - M0 = I0; - L0 = M0; - M1 = I1; - L1 = M1; - M2 = I2; - L2 = M2; - M3 = I3; - L3 = M3; - I0 = I3; - B0 = I0; - I1 = I2; - B1 = I1; - I3 = I0; - B2 = I3; - I2 = I1; - B3 = I2; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - CHECKREG r0, 0x90001119; - CHECKREG r1, 0x93213339; - CHECKREG r2, 0x94315559; - CHECKREG r3, 0x91637779; - CHECKREG r4, 0x91637779; - CHECKREG r5, 0x94315559; - CHECKREG r6, 0x91637779; - CHECKREG r7, 0x94315559; - R0 = M0; - R1 = M1; - R2 = M2; - R3 = M3; - R4 = I0; - R5 = I1; - R6 = I2; - R7 = I3; - CHECKREG r0, 0x90001119; - CHECKREG r1, 0x93213339; - CHECKREG r2, 0x94315559; - CHECKREG r3, 0x91637779; - CHECKREG r4, 0x91637779; - CHECKREG r5, 0x94315559; - CHECKREG r6, 0x94315559; - CHECKREG r7, 0x91637779; - -// I-to-M-B, I-to-I-L reg: no stall - imm32 i0, 0xa000111a; - imm32 i1, 0xaa21334a; - imm32 i2, 0xa4a1554a; - imm32 i3, 0xa66a774a; - imm32 m0, 0xa881a94a; - imm32 m1, 0xaaa1ba4a; - imm32 m2, 0xacc1ddaa; - imm32 m3, 0xaee1ff4a; - M0 = I0; - B3 = M0; - M1 = I1; - B2 = M1; - M2 = I2; - B1 = M2; - M3 = I3; - B0 = M3; - I0 = I3; - L1 = I0; - I1 = I2; - L2 = I1; - I2 = I0; - L3 = I2; - I3 = I1; - L0 = I3; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - CHECKREG r0, 0xA4A1554A; - CHECKREG r1, 0xA66A774A; - CHECKREG r2, 0xA4A1554A; - CHECKREG r3, 0xA66A774A; - CHECKREG r4, 0xA66A774A; - CHECKREG r5, 0xA4A1554A; - CHECKREG r6, 0xAA21334A; - CHECKREG r7, 0xA000111A; - R0 = M0; - R1 = M1; - R2 = M2; - R3 = M3; - R4 = I0; - R5 = I1; - R6 = I2; - R7 = I3; - CHECKREG r0, 0xA000111A; - CHECKREG r1, 0xAA21334A; - CHECKREG r2, 0xA4A1554A; - CHECKREG r3, 0xA66A774A; - CHECKREG r4, 0xA66A774A; - CHECKREG r5, 0xA4A1554A; - CHECKREG r6, 0xA66A774A; - CHECKREG r7, 0xA4A1554A; - -// L-to-B-to-I, L-to-L-to-M reg: no stall - imm32 l0, 0xb000111b; - imm32 l1, 0xb421333b; - imm32 l2, 0xb441555b; - imm32 l3, 0xb564777b; - imm32 b0, 0xb051499b; - imm32 b1, 0xb605b4bb; - imm32 b2, 0xbc605d4b; - imm32 b3, 0xbee605fb; - B0 = L0; - I2 = B0; - B1 = L1; - I3 = B1; - B2 = L2; - I0 = B2; - B3 = L3; - I1 = B3; - L0 = L3; - M0 = L0; - L1 = L2; - M1 = L1; - L3 = L0; - M2 = L3; - L2 = L1; - M3 = L2; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - CHECKREG r0, 0xB441555B; - CHECKREG r1, 0xB564777B; - CHECKREG r2, 0xB000111B; - CHECKREG r3, 0xB421333B; - CHECKREG r4, 0xB564777B; - CHECKREG r5, 0xB441555B; - CHECKREG r6, 0xB564777B; - CHECKREG r7, 0xB441555B; - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - CHECKREG r0, 0xB564777B; - CHECKREG r1, 0xB441555B; - CHECKREG r2, 0xB441555B; - CHECKREG r3, 0xB564777B; - CHECKREG r4, 0xB000111B; - CHECKREG r5, 0xB421333B; - CHECKREG r6, 0xB441555B; - CHECKREG r7, 0xB564777B; - -// B-to-L-to-M, B-to-B-to-I reg: no stall - imm32 l0, 0xc000111c; - imm32 l1, 0xc621334c; - imm32 l2, 0xc461554c; - imm32 l3, 0xc766774c; - imm32 b0, 0xc871694c; - imm32 b1, 0xcaa7b64c; - imm32 b2, 0xc8c17d6c; - imm32 b3, 0xce81f74c; - L0 = B0; - M1 = L0; - L1 = B1; - M2 = L1; - L2 = B2; - M3 = L2; - L3 = B3; - M0 = L3; - B3 = B0; - I0 = B3; - B0 = B1; - I1 = B0; - B1 = B2; - I2 = B1; - B2 = B3; - I3 = B2; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - CHECKREG r0, 0xC871694C; - CHECKREG r1, 0xCAA7B64C; - CHECKREG r2, 0xC8C17D6C; - CHECKREG r3, 0xCE81F74C; - CHECKREG r4, 0xCAA7B64C; - CHECKREG r5, 0xC8C17D6C; - CHECKREG r6, 0xC871694C; - CHECKREG r7, 0xC871694C; - R0 = M0; - R1 = M1; - R2 = M2; - R3 = M3; - R4 = I0; - R5 = I1; - R6 = I2; - R7 = I3; - CHECKREG r0, 0xCE81F74C; - CHECKREG r1, 0xC871694C; - CHECKREG r2, 0xCAA7B64C; - CHECKREG r3, 0xC8C17D6C; - CHECKREG r4, 0xC871694C; - CHECKREG r5, 0xCAA7B64C; - CHECKREG r6, 0xC8C17D6C; - CHECKREG r7, 0xC871694C; - - pass diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_dep_stall.s b/sim/testsuite/sim/bfin/c_regmv_imlb_dep_stall.s deleted file mode 100644 index 8fd2235..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_imlb_dep_stall.s +++ /dev/null @@ -1,335 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_stall/c_regmv_imlb_dep_stall.dsp -// Spec Reference: regmv imlb-depepency stall -# mach: bfin - -.include "testutils.inc" - start - -// R-reg to I,M-reg to R-reg: stall - imm32 r0, 0x00001110; - imm32 r1, 0x00213330; - imm32 r2, 0x04015550; - imm32 r3, 0x06607770; - imm32 r4, 0x08010990; - imm32 r5, 0x0a01b0b0; - imm32 r6, 0x0c01dd00; - imm32 r7, 0x0e01f0f0; - I0 = R0; - R7 = I0; - I1 = R1; - R0 = I1; - I2 = R2; - R1 = I2; - I3 = R3; - R2 = I3; - M0 = R4; - R3 = M0; - M1 = R5; - R4 = M1; - M2 = R6; - R5 = M2; - M3 = R7; - R6 = M3; - - CHECKREG r0, 0x00213330; - CHECKREG r1, 0x04015550; - CHECKREG r2, 0x06607770; - CHECKREG r3, 0x08010990; - CHECKREG r4, 0x0A01B0B0; - CHECKREG r5, 0x0C01DD00; - CHECKREG r6, 0x00001110; - CHECKREG r7, 0x00001110; - - R0 = M3; - R1 = M2; - R2 = M1; - R3 = M0; - R4 = I3; - R5 = I2; - R6 = I1; - R7 = I0; - CHECKREG r0, 0x00001110; - CHECKREG r1, 0x0C01DD00; - CHECKREG r2, 0x0A01B0B0; - CHECKREG r3, 0x08010990; - CHECKREG r4, 0x06607770; - CHECKREG r5, 0x04015550; - CHECKREG r6, 0x00213330; - CHECKREG r7, 0x00001110; - -// R-to-M,I and to P-reg: stall - imm32 i0, 0x00001111; - imm32 i1, 0x12213341; - imm32 i2, 0x14415541; - imm32 i3, 0x16617741; - imm32 m0, 0x18819941; - imm32 m1, 0x1aa1bb41; - imm32 m2, 0x1cc1dd41; - imm32 m3, 0x1ee1ff41; - M0 = R0; - R0 = M0; - M1 = R1; - P1 = M1; - M2 = R2; - P2 = M2; - M3 = R3; - P3 = M3; - I0 = R4; - P4 = I0; - I1 = R5; - P5 = I1; - I2 = R6; - SP = I2; - I3 = R7; - FP = I3; - - CHECKREG r0, 0x00001110; - CHECKREG p1, 0x0C01DD00; - CHECKREG p2, 0x0A01B0B0; - CHECKREG p3, 0x08010990; - CHECKREG p4, 0x06607770; - CHECKREG p5, 0x04015550; - CHECKREG sp, 0x00213330; - CHECKREG fp, 0x00001110; - R0 = M0; - R1 = M1; - R2 = M2; - R3 = M3; - R4 = I0; - R5 = I1; - R6 = I2; - R7 = I3; - CHECKREG r0, 0x00001110; - CHECKREG r1, 0x0C01DD00; - CHECKREG r2, 0x0A01B0B0; - CHECKREG r3, 0x08010990; - CHECKREG r4, 0x06607770; - CHECKREG r5, 0x04015550; - CHECKREG r6, 0x00213330; - CHECKREG r7, 0x00001110; - -// R-reg to L,B-reg to R-reg: stall - imm32 r0, 0x20001112; - imm32 r1, 0x22213332; - imm32 r2, 0x21215552; - imm32 r3, 0x21627772; - imm32 r4, 0x21812992; - imm32 r5, 0x21a1b2b2; - imm32 r6, 0x21c1d222; - imm32 r7, 0x21e1ff22; - L0 = R1; - R0 = L0; - L1 = R2; - R1 = L1; - L2 = R3; - R2 = L2; - L3 = R4; - R3 = L3; - B0 = R5; - R4 = B0; - B1 = R6; - R5 = B1; - B2 = R7; - R6 = B2; - B3 = R0; - R7 = B3; - - CHECKREG r0, 0x22213332; - CHECKREG r1, 0x21215552; - CHECKREG r2, 0x21627772; - CHECKREG r3, 0x21812992; - CHECKREG r4, 0x21A1B2B2; - CHECKREG r5, 0x21C1D222; - CHECKREG r6, 0x21E1FF22; - CHECKREG r7, 0x22213332; - - R0 = L3; - R1 = L2; - R2 = L1; - R3 = L0; - R4 = B3; - R5 = B2; - R6 = B1; - R7 = B0; - CHECKREG r0, 0x21812992; - CHECKREG r1, 0x21627772; - CHECKREG r2, 0x21215552; - CHECKREG r3, 0x22213332; - CHECKREG r4, 0x22213332; - CHECKREG r5, 0x21E1FF22; - CHECKREG r6, 0x21C1D222; - CHECKREG r7, 0x21A1B2B2; - -// R-reg to L,B-reg to P-reg: stall - imm32 r0, 0x50001115; - imm32 r1, 0x51213335; - imm32 r2, 0x51415555; - imm32 r3, 0x51617775; - imm32 r4, 0x51819995; - imm32 r5, 0x51a1bbb5; - imm32 r6, 0x51c1ddd5; - imm32 r7, 0x51e1fff5; - L0 = R1; - R0 = L0; - L1 = R2; - SP = L1; - L2 = R3; - FP = L2; - L3 = R4; - P1 = L3; - B0 = R5; - P2 = B0; - B1 = R6; - P3 = B1; - B2 = R7; - P4 = B2; - B3 = R0; - P5 = B3; - - CHECKREG r0, 0x51213335; - CHECKREG p1, 0x51819995; - CHECKREG p2, 0x51A1BBB5; - CHECKREG p3, 0x51C1DDD5; - CHECKREG p4, 0x51E1FFF5; - CHECKREG p5, 0x51213335; - CHECKREG sp, 0x51415555; - CHECKREG fp, 0x51617775; - - R0 = L3; - R1 = L2; - R2 = L1; - R3 = L0; - R4 = B3; - R5 = B2; - R6 = B1; - R7 = B0; - CHECKREG r0, 0x51819995; - CHECKREG r1, 0x51617775; - CHECKREG r2, 0x51415555; - CHECKREG r3, 0x51213335; - CHECKREG r4, 0x51213335; - CHECKREG r5, 0x51E1FFF5; - CHECKREG r6, 0x51C1DDD5; - CHECKREG r7, 0x51A1BBB5; - -// R-reg to I,M-reg to L,B-reg: stall - imm32 r0, 0x00001111; - imm32 r1, 0x72213337; - imm32 r2, 0x74415557; - imm32 r3, 0x76617777; - imm32 r4, 0x78819997; - imm32 r5, 0x7aa1bbb7; - imm32 r6, 0x7cc1ddd7; - imm32 r7, 0x77e1fff7; - I0 = R0; - L0 = I0; - I1 = R1; - L1 = I1; - I2 = R2; - L2 = I2; - I3 = R3; - L3 = I3; - M0 = R4; - B0 = M0; - M1 = R5; - B1 = M1; - M2 = R6; - B2 = M2; - M3 = R7; - B3 = M3; - - R0 = L3; - R1 = L2; - R2 = L1; - R3 = L0; - R4 = B3; - R5 = B2; - R6 = B1; - R7 = B0; - CHECKREG r0, 0x76617777; - CHECKREG r1, 0x74415557; - CHECKREG r2, 0x72213337; - CHECKREG r3, 0x00001111; - CHECKREG r4, 0x77E1FFF7; - CHECKREG r5, 0x7CC1DDD7; - CHECKREG r6, 0x7AA1BBB7; - CHECKREG r7, 0x78819997; - - R0 = M3; - R1 = M2; - R2 = M1; - R3 = M0; - R4 = I3; - R5 = I2; - R6 = I1; - R7 = I0; - CHECKREG r0, 0x77E1FFF7; - CHECKREG r1, 0x7CC1DDD7; - CHECKREG r2, 0x7AA1BBB7; - CHECKREG r3, 0x78819997; - CHECKREG r4, 0x76617777; - CHECKREG r5, 0x74415557; - CHECKREG r6, 0x72213337; - CHECKREG r7, 0x00001111; - -// R-reg to L,B-reg to I,M reg: stall - imm32 r0, 0x00001111; - imm32 r1, 0x81213338; - imm32 r2, 0x81415558; - imm32 r3, 0x81617778; - imm32 r4, 0x81819998; - imm32 r5, 0x81a1bbb8; - imm32 r6, 0x81c1ddd8; - imm32 r7, 0x81e1fff8; - L0 = R0; - I0 = L0; - L1 = R1; - I1 = L1; - L2 = R2; - I2 = L2; - L3 = R3; - I3 = L3; - B0 = R4; - M0 = B0; - B1 = R5; - M1 = B1; - B2 = R6; - M2 = B2; - B3 = R7; - M3 = B3; - - R0 = M0; - R1 = M1; - R2 = M2; - R3 = M3; - R4 = I0; - R5 = I1; - R6 = I2; - R7 = I3; - CHECKREG r0, 0x81819998; - CHECKREG r1, 0x81A1BBB8; - CHECKREG r2, 0x81C1DDD8; - CHECKREG r3, 0x81E1FFF8; - CHECKREG r4, 0x00001111; - CHECKREG r5, 0x81213338; - CHECKREG r6, 0x81415558; - CHECKREG r7, 0x81617778; - - R0 = L3; - R1 = L2; - R2 = L1; - R3 = L0; - R4 = B3; - R5 = B2; - R6 = B1; - R7 = B0; - CHECKREG r0, 0x81617778; - CHECKREG r1, 0x81415558; - CHECKREG r2, 0x81213338; - CHECKREG r3, 0x00001111; - CHECKREG r4, 0x81E1FFF8; - CHECKREG r5, 0x81C1DDD8; - CHECKREG r6, 0x81A1BBB8; - CHECKREG r7, 0x81819998; - - pass diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_dr.s b/sim/testsuite/sim/bfin/c_regmv_imlb_dr.s deleted file mode 100644 index ec15df0..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_imlb_dr.s +++ /dev/null @@ -1,313 +0,0 @@ -//Original:/testcases/core/c_regmv_imlb_dr/c_regmv_imlb_dr.dsp -// Spec Reference: regmv imlb to dr -# mach: bfin - -.include "testutils.inc" - start - - - - - - -// initialize source regs -imm32 i0, 0x11111111; -imm32 i1, 0x22222222; -imm32 i2, 0x33333333; -imm32 i3, 0x44444444; - - -// i to dreg -R0 = I0; -R1 = I0; -R2 = I0; -R3 = I0; -R4 = I1; -R5 = I1; -R6 = I1; -R7 = I1; -CHECKREG r0, 0x11111111; -CHECKREG r1, 0x11111111; -CHECKREG r2, 0x11111111; -CHECKREG r3, 0x11111111; -CHECKREG r4, 0x22222222; -CHECKREG r5, 0x22222222; -CHECKREG r6, 0x22222222; -CHECKREG r7, 0x22222222; - -R0 = I1; -R1 = I1; -R2 = I1; -R3 = I1; -R4 = I0; -R5 = I0; -R6 = I0; -R7 = I0; -CHECKREG r0, 0x22222222; -CHECKREG r1, 0x22222222; -CHECKREG r2, 0x22222222; -CHECKREG r3, 0x22222222; -CHECKREG r4, 0x11111111; -CHECKREG r5, 0x11111111; -CHECKREG r6, 0x11111111; -CHECKREG r7, 0x11111111; - - -// i to dreg -R0 = I2; -R1 = I2; -R2 = I2; -R3 = I2; -R4 = I3; -R5 = I3; -R6 = I3; -R7 = I3; -CHECKREG r0, 0x33333333; -CHECKREG r1, 0x33333333; -CHECKREG r2, 0x33333333; -CHECKREG r3, 0x33333333; -CHECKREG r4, 0x44444444; -CHECKREG r5, 0x44444444; -CHECKREG r6, 0x44444444; -CHECKREG r7, 0x44444444; - -R0 = I3; -R1 = I3; -R2 = I3; -R3 = I3; -R4 = I2; -R5 = I2; -R6 = I2; -R7 = I2; -CHECKREG r0, 0x44444444; -CHECKREG r1, 0x44444444; -CHECKREG r2, 0x44444444; -CHECKREG r3, 0x44444444; -CHECKREG r4, 0x33333333; -CHECKREG r5, 0x33333333; -CHECKREG r6, 0x33333333; -CHECKREG r7, 0x33333333; - - -imm32 m0, 0x55555555; -imm32 m1, 0x66666666; -imm32 m2, 0x77777777; -imm32 m3, 0x88888888; -// m to dreg -R0 = M0; -R1 = M0; -R2 = M0; -R3 = M0; -R4 = M1; -R5 = M1; -R6 = M1; -R7 = M1; -CHECKREG r0, 0x55555555; -CHECKREG r1, 0x55555555; -CHECKREG r2, 0x55555555; -CHECKREG r3, 0x55555555; -CHECKREG r4, 0x66666666; -CHECKREG r5, 0x66666666; -CHECKREG r6, 0x66666666; -CHECKREG r7, 0x66666666; - -R0 = M1; -R1 = M1; -R2 = M1; -R3 = M1; -R4 = M0; -R5 = M0; -R6 = M0; -R7 = M0; -CHECKREG r0, 0x66666666; -CHECKREG r1, 0x66666666; -CHECKREG r2, 0x66666666; -CHECKREG r3, 0x66666666; -CHECKREG r4, 0x55555555; -CHECKREG r5, 0x55555555; -CHECKREG r6, 0x55555555; -CHECKREG r7, 0x55555555; - -R0 = M2; -R1 = M2; -R2 = M2; -R3 = M2; -R4 = M3; -R5 = M3; -R6 = M3; -R7 = M3; -CHECKREG r0, 0x77777777; -CHECKREG r1, 0x77777777; -CHECKREG r2, 0x77777777; -CHECKREG r3, 0x77777777; -CHECKREG r4, 0x88888888; -CHECKREG r5, 0x88888888; -CHECKREG r6, 0x88888888; -CHECKREG r7, 0x88888888; - -R0 = M3; -R1 = M3; -R2 = M3; -R3 = M3; -R4 = M2; -R5 = M2; -R6 = M2; -R7 = M2; -CHECKREG r0, 0x88888888; -CHECKREG r1, 0x88888888; -CHECKREG r2, 0x88888888; -CHECKREG r3, 0x88888888; -CHECKREG r4, 0x77777777; -CHECKREG r5, 0x77777777; -CHECKREG r6, 0x77777777; -CHECKREG r7, 0x77777777; - -imm32 l0, 0x99999999; -imm32 l1, 0xaaaaaaaa; -imm32 l2, 0xbbbbbbbb; -imm32 l3, 0xcccccccc; -// l to dreg -R0 = L0; -R1 = L0; -R2 = L0; -R3 = L0; -R4 = L1; -R5 = L1; -R6 = L1; -R7 = L1; -CHECKREG r0, 0x99999999; -CHECKREG r1, 0x99999999; -CHECKREG r2, 0x99999999; -CHECKREG r3, 0x99999999; -CHECKREG r4, 0xaaaaaaaa; -CHECKREG r5, 0xaaaaaaaa; -CHECKREG r6, 0xaaaaaaaa; -CHECKREG r7, 0xaaaaaaaa; - -R0 = L1; -R1 = L1; -R2 = L1; -R3 = L1; -R4 = L0; -R5 = L0; -R6 = L0; -R7 = L0; -CHECKREG r0, 0xaaaaaaaa; -CHECKREG r1, 0xaaaaaaaa; -CHECKREG r2, 0xaaaaaaaa; -CHECKREG r3, 0xaaaaaaaa; -CHECKREG r4, 0x99999999; -CHECKREG r5, 0x99999999; -CHECKREG r6, 0x99999999; -CHECKREG r7, 0x99999999; - - -R0 = L2; -R1 = L2; -R2 = L2; -R3 = L2; -R4 = L3; -R5 = L3; -R6 = L3; -R7 = L3; -CHECKREG r0, 0xbbbbbbbb; -CHECKREG r1, 0xbbbbbbbb; -CHECKREG r2, 0xbbbbbbbb; -CHECKREG r3, 0xbbbbbbbb; -CHECKREG r4, 0xcccccccc; -CHECKREG r5, 0xcccccccc; -CHECKREG r6, 0xcccccccc; -CHECKREG r7, 0xcccccccc; - -R0 = L3; -R1 = L3; -R2 = L3; -R3 = L3; -R4 = L2; -R5 = L2; -R6 = L2; -R7 = L2; -CHECKREG r0, 0xcccccccc; -CHECKREG r1, 0xcccccccc; -CHECKREG r2, 0xcccccccc; -CHECKREG r3, 0xcccccccc; -CHECKREG r4, 0xbbbbbbbb; -CHECKREG r5, 0xbbbbbbbb; -CHECKREG r6, 0xbbbbbbbb; -CHECKREG r7, 0xbbbbbbbb; - - -imm32 b0, 0xdddddddd; -imm32 b1, 0xeeeeeeee; -imm32 b2, 0xffffffff; -imm32 b3, 0x12345678; -// b to dreg -R0 = B0; -R1 = B0; -R2 = B0; -R3 = B0; -R4 = B1; -R5 = B1; -R6 = B1; -R7 = B1; -CHECKREG r0, 0xdddddddd; -CHECKREG r1, 0xdddddddd; -CHECKREG r2, 0xdddddddd; -CHECKREG r3, 0xdddddddd; -CHECKREG r4, 0xeeeeeeee; -CHECKREG r5, 0xeeeeeeee; -CHECKREG r6, 0xeeeeeeee; -CHECKREG r7, 0xeeeeeeee; - -R0 = B1; -R1 = B1; -R2 = B1; -R3 = B1; -R4 = B0; -R5 = B0; -R6 = B0; -R7 = B0; -CHECKREG r0, 0xeeeeeeee; -CHECKREG r1, 0xeeeeeeee; -CHECKREG r2, 0xeeeeeeee; -CHECKREG r3, 0xeeeeeeee; -CHECKREG r4, 0xdddddddd; -CHECKREG r5, 0xdddddddd; -CHECKREG r6, 0xdddddddd; -CHECKREG r7, 0xdddddddd; - -R0 = B2; -R1 = B2; -R2 = B2; -R3 = B2; -R4 = B3; -R5 = B3; -R6 = B3; -R7 = B3; -CHECKREG r0, 0xffffffff; -CHECKREG r1, 0xffffffff; -CHECKREG r2, 0xffffffff; -CHECKREG r3, 0xffffffff; -CHECKREG r4, 0x12345678; -CHECKREG r5, 0x12345678; -CHECKREG r6, 0x12345678; -CHECKREG r7, 0x12345678; - -R0 = B3; -R1 = B3; -R2 = B3; -R3 = B3; -R4 = B2; -R5 = B2; -R6 = B2; -R7 = B2; -CHECKREG r0, 0x12345678; -CHECKREG r1, 0x12345678; -CHECKREG r2, 0x12345678; -CHECKREG r3, 0x12345678; -CHECKREG r4, 0xffffffff; -CHECKREG r5, 0xffffffff; -CHECKREG r6, 0xffffffff; -CHECKREG r7, 0xffffffff; - -pass diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_imlb.s b/sim/testsuite/sim/bfin/c_regmv_imlb_imlb.s deleted file mode 100644 index 35146ec..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_imlb_imlb.s +++ /dev/null @@ -1,925 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_imlb/c_regmv_imlb_imlb.dsp -// Spec Reference: regmv imlb-imlb -# mach: bfin - -.include "testutils.inc" - start - -// initialize source regs - imm32 i0, 0x11111111; - imm32 i1, 0x22222222; - imm32 i2, 0x33333333; - imm32 i3, 0x44444444; - imm32 m0, 0x55555555; - imm32 m1, 0x66666666; - imm32 m2, 0x77777777; - imm32 m3, 0x88888888; - imm32 l0, 0x99999999; - imm32 l1, 0xAAAAAAAA; - imm32 l2, 0xBBBBBBBB; - imm32 l3, 0xCCCCCCCC; - imm32 b0, 0xDDDDDDDD; - imm32 b1, 0xEEEEEEEE; - imm32 b2, 0xFFFFFFFF; - imm32 b3, 0x12345667; - -//*******************i-i & m-m, i-m & m-i, l-l & b-b, l-b & b-l -// i to i & m to m - I0 = I0; - I1 = I1; - I2 = I2; - I3 = I3; - M0 = M0; - M1 = M1; - M2 = M2; - M3 = M3; - - I0 = I1; - I1 = I2; - I2 = I3; - I3 = I0; - M0 = M1; - M1 = M2; - M2 = M3; - M3 = M0; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0x22222222; - CHECKREG r1, 0x33333333; - CHECKREG r2, 0x44444444; - CHECKREG r3, 0x22222222; - CHECKREG r4, 0x66666666; - CHECKREG r5, 0x77777777; - CHECKREG r6, 0x88888888; - CHECKREG r7, 0x66666666; - - I0 = I2; - I1 = I3; - I2 = I0; - I3 = I1; - M0 = M2; - M1 = M3; - M2 = M0; - M3 = M1; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0x44444444; - CHECKREG r1, 0x22222222; - CHECKREG r2, 0x44444444; - CHECKREG r3, 0x22222222; - CHECKREG r4, 0x88888888; - CHECKREG r5, 0x66666666; - CHECKREG r6, 0x88888888; - CHECKREG r7, 0x66666666; - - I0 = I3; - I1 = I0; - I2 = I1; - I3 = I2; - M0 = M3; - M1 = M0; - M2 = M1; - M3 = M2; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0x22222222; - CHECKREG r1, 0x22222222; - CHECKREG r2, 0x22222222; - CHECKREG r3, 0x22222222; - CHECKREG r4, 0x66666666; - CHECKREG r5, 0x66666666; - CHECKREG r6, 0x66666666; - CHECKREG r7, 0x66666666; - - imm32 i0, 0xa1111110; - imm32 i1, 0xb2222220; - imm32 i2, 0xc3333330; - imm32 i3, 0xd4444440; - imm32 m0, 0xe5555550; - imm32 m1, 0xf6666660; - imm32 m2, 0x17777770; - imm32 m3, 0x28888888; - -// m to i & i to m - I0 = M0; - I1 = M1; - I2 = M2; - I3 = M3; - M0 = I0; - M1 = I1; - M2 = I2; - M3 = I3; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0xE5555550; - CHECKREG r1, 0xF6666660; - CHECKREG r2, 0x17777770; - CHECKREG r3, 0x28888888; - CHECKREG r4, 0xE5555550; - CHECKREG r5, 0xF6666660; - CHECKREG r6, 0x17777770; - CHECKREG r7, 0x28888888; - - I0 = M1; - I1 = M2; - I2 = M3; - I3 = M0; - M0 = I1; - M1 = I2; - M2 = I3; - M3 = I0; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0xF6666660; - CHECKREG r1, 0x17777770; - CHECKREG r2, 0x28888888; - CHECKREG r3, 0xE5555550; - CHECKREG r4, 0x17777770; - CHECKREG r5, 0x28888888; - CHECKREG r6, 0xE5555550; - CHECKREG r7, 0xF6666660; - - I0 = M2; - I1 = M3; - I2 = M0; - I3 = M1; - M0 = I2; - M1 = I3; - M2 = I0; - M3 = I1; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0xE5555550; - CHECKREG r1, 0xF6666660; - CHECKREG r2, 0x17777770; - CHECKREG r3, 0x28888888; - CHECKREG r4, 0x17777770; - CHECKREG r5, 0x28888888; - CHECKREG r6, 0xE5555550; - CHECKREG r7, 0xF6666660; - - I0 = M3; - I1 = M0; - I2 = M1; - I3 = M2; - M0 = I3; - M1 = I0; - M2 = I1; - M3 = I2; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0xF6666660; - CHECKREG r1, 0x17777770; - CHECKREG r2, 0x28888888; - CHECKREG r3, 0xE5555550; - CHECKREG r4, 0xE5555550; - CHECKREG r5, 0xF6666660; - CHECKREG r6, 0x17777770; - CHECKREG r7, 0x28888888; - -// l to l & b to b - L0 = L0; - L1 = L1; - L2 = L2; - L3 = L3; - B0 = B0; - B1 = B1; - B2 = B2; - B3 = B3; - - L0 = L1; - L1 = L2; - L2 = L3; - L3 = L0; - B0 = B1; - B1 = B2; - B2 = B3; - B3 = B0; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - - CHECKREG r0, 0xAAAAAAAA; - CHECKREG r1, 0xBBBBBBBB; - CHECKREG r2, 0xCCCCCCCC; - CHECKREG r3, 0xAAAAAAAA; - CHECKREG r4, 0xEEEEEEEE; - CHECKREG r5, 0xFFFFFFFF; - CHECKREG r6, 0x12345667; - CHECKREG r7, 0xEEEEEEEE; - - L0 = L2; - L1 = L3; - L2 = L0; - L3 = L1; - B0 = B2; - B1 = B3; - B2 = B0; - B3 = B1; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - - CHECKREG r0, 0xCCCCCCCC; - CHECKREG r1, 0xAAAAAAAA; - CHECKREG r2, 0xCCCCCCCC; - CHECKREG r3, 0xAAAAAAAA; - CHECKREG r4, 0x12345667; - CHECKREG r5, 0xEEEEEEEE; - CHECKREG r6, 0x12345667; - CHECKREG r7, 0xEEEEEEEE; - - imm32 l0, 0x09499091; - imm32 l1, 0x0A55A0A2; - imm32 l2, 0x0B6BB0B3; - imm32 l3, 0x0C7CC0C4; - imm32 b0, 0x0D8DD0D5; - imm32 b1, 0x0E9EE0E6; - imm32 b2, 0x0F0FF0F7; - imm32 b3, 0x12145068; - - L0 = L3; - L1 = L0; - L2 = L1; - L3 = L2; - B0 = B3; - B1 = B0; - B2 = B1; - B3 = B2; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - - CHECKREG r0, 0x0C7CC0C4; - CHECKREG r1, 0x0C7CC0C4; - CHECKREG r2, 0x0C7CC0C4; - CHECKREG r3, 0x0C7CC0C4; - CHECKREG r4, 0x12145068; - CHECKREG r5, 0x12145068; - CHECKREG r6, 0x12145068; - CHECKREG r7, 0x12145068; - -// b to l & l to b - L0 = B0; - L1 = B1; - L2 = B2; - L3 = B3; - B0 = L0; - B1 = L1; - B2 = L2; - B3 = L3; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0xF6666660; - CHECKREG r1, 0x17777770; - CHECKREG r2, 0x28888888; - CHECKREG r3, 0xE5555550; - CHECKREG r4, 0xE5555550; - CHECKREG r5, 0xF6666660; - CHECKREG r6, 0x17777770; - CHECKREG r7, 0x28888888; - - imm32 l0, 0x01909910; - imm32 l1, 0x12A11220; - imm32 l2, 0x23B25530; - imm32 l3, 0x34C36640; - imm32 b0, 0x45D47750; - imm32 b1, 0x56E58860; - imm32 b2, 0x67F66676; - imm32 b3, 0x78375680; - - L0 = B1; - L1 = B2; - L2 = B3; - L3 = B0; - B0 = L1; - B1 = L2; - B2 = L3; - B3 = L0; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - - CHECKREG r0, 0x56E58860; - CHECKREG r1, 0x67F66676; - CHECKREG r2, 0x78375680; - CHECKREG r3, 0x45D47750; - CHECKREG r4, 0x67F66676; - CHECKREG r5, 0x78375680; - CHECKREG r6, 0x45D47750; - CHECKREG r7, 0x56E58860; - - imm32 l0, 0x09909990; - imm32 l1, 0x1AA11230; - imm32 l2, 0x2BB25550; - imm32 l3, 0x3CC36660; - imm32 b0, 0x4DD47770; - imm32 b1, 0x5EE58880; - imm32 b2, 0x6FF66666; - imm32 b3, 0x72375660; - - L0 = B2; - L1 = B3; - L2 = B0; - L3 = B1; - B0 = L2; - B1 = L3; - B2 = L0; - B3 = L1; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - - CHECKREG r0, 0x6FF66666; - CHECKREG r1, 0x72375660; - CHECKREG r2, 0x4DD47770; - CHECKREG r3, 0x5EE58880; - CHECKREG r4, 0x4DD47770; - CHECKREG r5, 0x5EE58880; - CHECKREG r6, 0x6FF66666; - CHECKREG r7, 0x72375660; - - L0 = B3; - L1 = B0; - L2 = B1; - L3 = B2; - B0 = L3; - B1 = L0; - B2 = L1; - B3 = L2; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - - CHECKREG r0, 0x72375660; - CHECKREG r1, 0x4DD47770; - CHECKREG r2, 0x5EE58880; - CHECKREG r3, 0x6FF66666; - CHECKREG r4, 0x6FF66666; - CHECKREG r5, 0x72375660; - CHECKREG r6, 0x4DD47770; - CHECKREG r7, 0x5EE58880; - - imm32 l0, 0x09999990; - imm32 l1, 0x1AAAAAA0; - imm32 l2, 0x2BBBBBB0; - imm32 l3, 0x3CCCCCC0; - imm32 b0, 0x4DDDDDD0; - imm32 b1, 0x5EEEEEE0; - imm32 b2, 0x6FFFFFF0; - imm32 b3, 0x72345660; - -//*******************l-i & l-m, b-i & b-m, i-l & i-b, m-l & m-b -// l to i & l to m - I0 = L0; - I1 = L1; - I2 = L2; - I3 = L3; - M0 = L0; - M1 = L1; - M2 = L2; - M3 = L3; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0x09999990; - CHECKREG r1, 0x1AAAAAA0; - CHECKREG r2, 0x2BBBBBB0; - CHECKREG r3, 0x3CCCCCC0; - CHECKREG r4, 0x09999990; - CHECKREG r5, 0x1AAAAAA0; - CHECKREG r6, 0x2BBBBBB0; - CHECKREG r7, 0x3CCCCCC0; - - I0 = L1; - I1 = L2; - I2 = L3; - I3 = L0; - M0 = L1; - M1 = L2; - M2 = L3; - M3 = L0; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0x1AAAAAA0; - CHECKREG r1, 0x2BBBBBB0; - CHECKREG r2, 0x3CCCCCC0; - CHECKREG r3, 0x09999990; - CHECKREG r4, 0x1AAAAAA0; - CHECKREG r5, 0x2BBBBBB0; - CHECKREG r6, 0x3CCCCCC0; - CHECKREG r7, 0x09999990; - - I0 = L2; - I1 = L3; - I2 = L0; - I3 = L1; - M0 = L2; - M1 = L3; - M2 = L0; - M3 = L1; - - R4 = I0; - R5 = I1; - R6 = I2; - R7 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0x1AAAAAA0; - CHECKREG r1, 0x2BBBBBB0; - CHECKREG r2, 0x3CCCCCC0; - CHECKREG r3, 0x09999990; - CHECKREG r4, 0x2BBBBBB0; - CHECKREG r5, 0x3CCCCCC0; - CHECKREG r6, 0x09999990; - CHECKREG r7, 0x1AAAAAA0; - - I0 = L3; - I1 = L0; - I2 = L1; - I3 = L2; - M0 = L3; - M1 = L0; - M2 = L1; - M3 = L2; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0x3CCCCCC0; - CHECKREG r1, 0x09999990; - CHECKREG r2, 0x1AAAAAA0; - CHECKREG r3, 0x2BBBBBB0; - CHECKREG r4, 0x3CCCCCC0; - CHECKREG r5, 0x09999990; - CHECKREG r6, 0x1AAAAAA0; - CHECKREG r7, 0x2BBBBBB0; - -// b to i & b to m - I0 = B0; - I1 = B1; - I2 = B2; - I3 = B3; - M0 = B0; - M1 = B1; - M2 = B2; - M3 = B3; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0x4DDDDDD0; - CHECKREG r1, 0x5EEEEEE0; - CHECKREG r2, 0x6FFFFFF0; - CHECKREG r3, 0x72345660; - CHECKREG r4, 0x4DDDDDD0; - CHECKREG r5, 0x5EEEEEE0; - CHECKREG r6, 0x6FFFFFF0; - CHECKREG r7, 0x72345660; - - I0 = B1; - I1 = B2; - I2 = B3; - I3 = B0; - M0 = B1; - M1 = B2; - M2 = B3; - M3 = B0; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0x5EEEEEE0; - CHECKREG r1, 0x6FFFFFF0; - CHECKREG r2, 0x72345660; - CHECKREG r3, 0x4DDDDDD0; - CHECKREG r4, 0x5EEEEEE0; - CHECKREG r5, 0x6FFFFFF0; - CHECKREG r6, 0x72345660; - CHECKREG r7, 0x4DDDDDD0; - - I0 = B2; - I1 = B3; - I2 = B0; - I3 = B1; - M0 = B2; - M1 = B3; - M2 = B0; - M3 = B1; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0x6FFFFFF0; - CHECKREG r1, 0x72345660; - CHECKREG r2, 0x4DDDDDD0; - CHECKREG r3, 0x5EEEEEE0; - CHECKREG r4, 0x6FFFFFF0; - CHECKREG r5, 0x72345660; - CHECKREG r6, 0x4DDDDDD0; - CHECKREG r7, 0x5EEEEEE0; - - I0 = B3; - I1 = B0; - I2 = B1; - I3 = B2; - M0 = B3; - M1 = B0; - M2 = B1; - M3 = B2; - - P1 = I1; - P2 = I2; - P3 = I3; - P4 = M0; - P5 = M1; - FP = M2; - SP = M3; - - CHECKREG p1, 0x4DDDDDD0; - CHECKREG p2, 0x5EEEEEE0; - CHECKREG p3, 0x6FFFFFF0; - CHECKREG p4, 0x72345660; - CHECKREG p5, 0x4DDDDDD0; - CHECKREG fp, 0x5EEEEEE0; - CHECKREG sp, 0x6FFFFFF0; - -// i to l & i to b - imm32 i0, 0x09999990; - imm32 i1, 0x1AAAAAA0; - imm32 i2, 0x2BBBBBB0; - imm32 i3, 0x3CCCCCC0; - - L0 = I0; - L1 = I1; - L2 = I2; - L3 = I3; - B0 = I0; - B1 = I1; - B2 = I2; - B3 = I3; - - L0 = I1; - L1 = I2; - L2 = I3; - L3 = I0; - B0 = I1; - B1 = I2; - B2 = I3; - B3 = I0; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - - CHECKREG r0, 0x1AAAAAA0; - CHECKREG r1, 0x2BBBBBB0; - CHECKREG r2, 0x3CCCCCC0; - CHECKREG r3, 0x09999990; - CHECKREG r4, 0x1AAAAAA0; - CHECKREG r5, 0x2BBBBBB0; - CHECKREG r6, 0x3CCCCCC0; - CHECKREG r7, 0x09999990; - - L0 = I2; - L1 = I3; - L2 = I0; - L3 = I1; - B0 = I2; - B1 = I3; - B2 = I0; - B3 = I1; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - - CHECKREG r0, 0x2BBBBBB0; - CHECKREG r1, 0x3CCCCCC0; - CHECKREG r2, 0x09999990; - CHECKREG r3, 0x1AAAAAA0; - CHECKREG r4, 0x2BBBBBB0; - CHECKREG r5, 0x3CCCCCC0; - CHECKREG r6, 0x09999990; - CHECKREG r7, 0x1AAAAAA0; - - imm32 l0, 0x09499091; - imm32 l1, 0x0A55A0A2; - imm32 l2, 0x0B6BB0B3; - imm32 l3, 0x0C7CC0C4; - imm32 b0, 0x0D8DD0D5; - imm32 b1, 0x0E9EE0E6; - imm32 b2, 0x0F0FF0F7; - imm32 b3, 0x12145068; - - L0 = I3; - L1 = I0; - L2 = I1; - L3 = I2; - B0 = I3; - B1 = I0; - B2 = I1; - B3 = I2; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - - CHECKREG r0, 0x3CCCCCC0; - CHECKREG r1, 0x09999990; - CHECKREG r2, 0x1AAAAAA0; - CHECKREG r3, 0x2BBBBBB0; - CHECKREG r4, 0x3CCCCCC0; - CHECKREG r5, 0x09999990; - CHECKREG r6, 0x1AAAAAA0; - CHECKREG r7, 0x2BBBBBB0; - -// m to l & m to b - imm32 m0, 0x4DDDDDD0; - imm32 m1, 0x5EEEEEE0; - imm32 m2, 0x6FFFFFF0; - imm32 m3, 0x72345660; - L0 = M0; - L1 = M1; - L2 = M2; - L3 = M3; - B0 = M0; - B1 = M1; - B2 = M2; - B3 = M3; - - R0 = I0; - R1 = I1; - R2 = I2; - R3 = I3; - R4 = M0; - R5 = M1; - R6 = M2; - R7 = M3; - - CHECKREG r0, 0x09999990; - CHECKREG r1, 0x1AAAAAA0; - CHECKREG r2, 0x2BBBBBB0; - CHECKREG r3, 0x3CCCCCC0; - CHECKREG r4, 0x4DDDDDD0; - CHECKREG r5, 0x5EEEEEE0; - CHECKREG r6, 0x6FFFFFF0; - CHECKREG r7, 0x72345660; - - imm32 l0, 0x01909910; - imm32 l1, 0x12A11220; - imm32 l2, 0x23B25530; - imm32 l3, 0x34C36640; - imm32 b0, 0x45D47750; - imm32 b1, 0x56E58860; - imm32 b2, 0x67F66676; - imm32 b3, 0x78375680; - - L0 = M1; - L1 = M2; - L2 = M3; - L3 = M0; - B0 = M1; - B1 = M2; - B2 = M3; - B3 = M0; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - - CHECKREG r0, 0x5EEEEEE0; - CHECKREG r1, 0x6FFFFFF0; - CHECKREG r2, 0x72345660; - CHECKREG r3, 0x4DDDDDD0; - CHECKREG r4, 0x5EEEEEE0; - CHECKREG r5, 0x6FFFFFF0; - CHECKREG r6, 0x72345660; - CHECKREG r7, 0x4DDDDDD0; - - imm32 l0, 0x09909990; - imm32 l1, 0x1AA11230; - imm32 l2, 0x2BB25550; - imm32 l3, 0x3CC36660; - imm32 b0, 0x4DD47770; - imm32 b1, 0x5EE58880; - imm32 b2, 0x6FF66666; - imm32 b3, 0x72375660; - - L0 = M2; - L1 = M3; - L2 = M0; - L3 = M1; - B0 = M2; - B1 = M3; - B2 = M0; - B3 = M1; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - - CHECKREG r0, 0x6FFFFFF0; - CHECKREG r1, 0x72345660; - CHECKREG r2, 0x4DDDDDD0; - CHECKREG r3, 0x5EEEEEE0; - CHECKREG r4, 0x6FFFFFF0; - CHECKREG r5, 0x72345660; - CHECKREG r6, 0x4DDDDDD0; - CHECKREG r7, 0x5EEEEEE0; - - L0 = M3; - L1 = M0; - L2 = M1; - L3 = M2; - B0 = M3; - B1 = M0; - B2 = M1; - B3 = M2; - - R0 = L0; - R1 = L1; - R2 = L2; - R3 = L3; - R4 = B0; - R5 = B1; - R6 = B2; - R7 = B3; - - CHECKREG r0, 0x72345660; - CHECKREG r1, 0x4DDDDDD0; - CHECKREG r2, 0x5EEEEEE0; - CHECKREG r3, 0x6FFFFFF0; - CHECKREG r4, 0x72345660; - CHECKREG r5, 0x4DDDDDD0; - CHECKREG r6, 0x5EEEEEE0; - CHECKREG r7, 0x6FFFFFF0; - - pass diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_pr.s b/sim/testsuite/sim/bfin/c_regmv_imlb_pr.s deleted file mode 100644 index 7e32a29..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_imlb_pr.s +++ /dev/null @@ -1,302 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_pr/c_regmv_imlb_pr.dsp -// Spec Reference: regmv imlb to dr -# mach: bfin - -.include "testutils.inc" - start - -// initialize source regs - imm32 i0, 0x11111111; - imm32 i1, 0x22222222; - imm32 i2, 0x33333333; - imm32 i3, 0x44444444; - -// i to preg - R0 = I0; - P1 = I0; - P2 = I0; - P3 = I0; - P4 = I1; - P5 = I1; - SP = I1; - FP = I1; - CHECKREG r0, 0x11111111; - CHECKREG p1, 0x11111111; - CHECKREG p2, 0x11111111; - CHECKREG p3, 0x11111111; - CHECKREG p4, 0x22222222; - CHECKREG p5, 0x22222222; - CHECKREG sp, 0x22222222; - CHECKREG fp, 0x22222222; - - R0 = I1; - P1 = I1; - P2 = I1; - P3 = I1; - P4 = I0; - P5 = I0; - SP = I0; - FP = I0; - CHECKREG r0, 0x22222222; - CHECKREG p1, 0x22222222; - CHECKREG p2, 0x22222222; - CHECKREG p3, 0x22222222; - CHECKREG p4, 0x11111111; - CHECKREG p5, 0x11111111; - CHECKREG sp, 0x11111111; - CHECKREG fp, 0x11111111; - - R0 = I2; - P1 = I2; - P2 = I2; - P3 = I2; - P4 = I3; - P5 = I3; - SP = I3; - FP = I3; - CHECKREG r0, 0x33333333; - CHECKREG p1, 0x33333333; - CHECKREG p2, 0x33333333; - CHECKREG p3, 0x33333333; - CHECKREG p4, 0x44444444; - CHECKREG p5, 0x44444444; - CHECKREG sp, 0x44444444; - CHECKREG fp, 0x44444444; - - R0 = I3; - P1 = I3; - P2 = I3; - P3 = I3; - P4 = I2; - P5 = I2; - SP = I2; - FP = I2; - CHECKREG r0, 0x44444444; - CHECKREG p1, 0x44444444; - CHECKREG p2, 0x44444444; - CHECKREG p3, 0x44444444; - CHECKREG p4, 0x33333333; - CHECKREG p5, 0x33333333; - CHECKREG sp, 0x33333333; - CHECKREG fp, 0x33333333; - - imm32 m0, 0x55555555; - imm32 m1, 0x66666666; - imm32 m2, 0x77777777; - imm32 m3, 0x88888888; -// m to preg - R0 = M0; - P1 = M0; - P2 = M0; - P3 = M0; - P4 = M1; - P5 = M1; - SP = M1; - FP = M1; - CHECKREG r0, 0x55555555; - CHECKREG p1, 0x55555555; - CHECKREG p2, 0x55555555; - CHECKREG p3, 0x55555555; - CHECKREG p4, 0x66666666; - CHECKREG p5, 0x66666666; - CHECKREG sp, 0x66666666; - CHECKREG fp, 0x66666666; - - R0 = M1; - P1 = M1; - P2 = M1; - P3 = M1; - P4 = M0; - P5 = M0; - SP = M0; - FP = M0; - CHECKREG r0, 0x66666666; - CHECKREG p1, 0x66666666; - CHECKREG p2, 0x66666666; - CHECKREG p3, 0x66666666; - CHECKREG p4, 0x55555555; - CHECKREG p5, 0x55555555; - CHECKREG sp, 0x55555555; - CHECKREG fp, 0x55555555; - - R0 = M2; - P1 = M2; - P2 = M2; - P3 = M2; - P4 = M3; - P5 = M3; - SP = M3; - FP = M3; - CHECKREG r0, 0x77777777; - CHECKREG p1, 0x77777777; - CHECKREG p2, 0x77777777; - CHECKREG p3, 0x77777777; - CHECKREG p4, 0x88888888; - CHECKREG p5, 0x88888888; - CHECKREG sp, 0x88888888; - CHECKREG fp, 0x88888888; - - R0 = M3; - P1 = M3; - P2 = M3; - P3 = M3; - P4 = M2; - P5 = M2; - SP = M2; - FP = M2; - CHECKREG r0, 0x88888888; - CHECKREG p1, 0x88888888; - CHECKREG p2, 0x88888888; - CHECKREG p3, 0x88888888; - CHECKREG p4, 0x77777777; - CHECKREG p5, 0x77777777; - CHECKREG sp, 0x77777777; - CHECKREG fp, 0x77777777; - - imm32 l0, 0x99999999; - imm32 l1, 0xaaaaaaaa; - imm32 l2, 0xbbbbbbbb; - imm32 l3, 0xcccccccc; -// l to preg - R0 = L0; - P1 = L0; - P2 = L0; - P3 = L0; - P4 = L1; - P5 = L1; - SP = L1; - FP = L1; - CHECKREG r0, 0x99999999; - CHECKREG p1, 0x99999999; - CHECKREG p2, 0x99999999; - CHECKREG p3, 0x99999999; - CHECKREG p4, 0xaaaaaaaa; - CHECKREG p5, 0xaaaaaaaa; - CHECKREG sp, 0xaaaaaaaa; - CHECKREG fp, 0xaaaaaaaa; - - R0 = L1; - P1 = L1; - P2 = L1; - P3 = L1; - P4 = L0; - P5 = L0; - SP = L0; - FP = L0; - CHECKREG r0, 0xaaaaaaaa; - CHECKREG p1, 0xaaaaaaaa; - CHECKREG p2, 0xaaaaaaaa; - CHECKREG p3, 0xaaaaaaaa; - CHECKREG p4, 0x99999999; - CHECKREG p5, 0x99999999; - CHECKREG sp, 0x99999999; - CHECKREG fp, 0x99999999; - - R0 = L2; - P1 = L2; - P2 = L2; - P3 = L2; - P4 = L3; - P5 = L3; - SP = L3; - FP = L3; - CHECKREG r0, 0xbbbbbbbb; - CHECKREG p1, 0xbbbbbbbb; - CHECKREG p2, 0xbbbbbbbb; - CHECKREG p3, 0xbbbbbbbb; - CHECKREG p4, 0xcccccccc; - CHECKREG p5, 0xcccccccc; - CHECKREG sp, 0xcccccccc; - CHECKREG fp, 0xcccccccc; - - R0 = L3; - P1 = L3; - P2 = L3; - P3 = L3; - P4 = L2; - P5 = L2; - SP = L2; - FP = L2; - CHECKREG r0, 0xcccccccc; - CHECKREG p1, 0xcccccccc; - CHECKREG p2, 0xcccccccc; - CHECKREG p3, 0xcccccccc; - CHECKREG p4, 0xbbbbbbbb; - CHECKREG p5, 0xbbbbbbbb; - CHECKREG sp, 0xbbbbbbbb; - CHECKREG fp, 0xbbbbbbbb; - - imm32 b0, 0xdddddddd; - imm32 b1, 0xeeeeeeee; - imm32 b2, 0xffffffff; - imm32 b3, 0x12345678; -// b to preg - R0 = B0; - P1 = B0; - P2 = B0; - P3 = B0; - P4 = B1; - P5 = B1; - SP = B1; - FP = B1; - CHECKREG r0, 0xdddddddd; - CHECKREG p1, 0xdddddddd; - CHECKREG p2, 0xdddddddd; - CHECKREG p3, 0xdddddddd; - CHECKREG p4, 0xeeeeeeee; - CHECKREG p5, 0xeeeeeeee; - CHECKREG sp, 0xeeeeeeee; - CHECKREG fp, 0xeeeeeeee; - - R0 = B1; - P1 = B1; - P2 = B1; - P3 = B1; - P4 = B0; - P5 = B0; - SP = B0; - FP = B0; - CHECKREG r0, 0xeeeeeeee; - CHECKREG p1, 0xeeeeeeee; - CHECKREG p2, 0xeeeeeeee; - CHECKREG p3, 0xeeeeeeee; - CHECKREG p4, 0xdddddddd; - CHECKREG p5, 0xdddddddd; - CHECKREG sp, 0xdddddddd; - CHECKREG fp, 0xdddddddd; - - R0 = B2; - P1 = B2; - P2 = B2; - P3 = B2; - P4 = B3; - P5 = B3; - SP = B3; - FP = B3; - CHECKREG r0, 0xffffffff; - CHECKREG p1, 0xffffffff; - CHECKREG p2, 0xffffffff; - CHECKREG p3, 0xffffffff; - CHECKREG p4, 0x12345678; - CHECKREG p5, 0x12345678; - CHECKREG sp, 0x12345678; - CHECKREG fp, 0x12345678; - - R0 = B3; - P1 = B3; - P2 = B3; - P3 = B3; - P4 = B2; - P5 = B2; - SP = B2; - FP = B2; - CHECKREG r0, 0x12345678; - CHECKREG p1, 0x12345678; - CHECKREG p2, 0x12345678; - CHECKREG p3, 0x12345678; - CHECKREG p4, 0xffffffff; - CHECKREG p5, 0xffffffff; - CHECKREG sp, 0xffffffff; - CHECKREG fp, 0xffffffff; - - pass diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_dep_nostall.s b/sim/testsuite/sim/bfin/c_regmv_pr_dep_nostall.s deleted file mode 100644 index 5525bea..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_pr_dep_nostall.s +++ /dev/null @@ -1,280 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_nostall/c_regmv_pr_dep_nostall.dsp -// Spec Reference: regmv pr-dep no stall -# mach: bfin - -.include "testutils.inc" - start - -//imm32 p0, 0x00001111; - imm32 p1, 0x32213330; - imm32 p2, 0x34415550; - imm32 p3, 0x36617770; - imm32 p4, 0x38819990; - imm32 p5, 0x3aa1bbb0; - imm32 fp, 0x3cc1ddd0; - imm32 sp, 0x3ee1fff0; -// P-reg to P-reg to R-reg: no stall - P4 = P1; - R1 = P4; - SP = P5; - R2 = SP; - P1 = FP; - R3 = P1; - CHECKREG r1, 0x32213330; - CHECKREG r2, 0x3AA1BBB0; - CHECKREG r3, 0x3CC1DDD0; - -//imm32 p0, 0x00001111; - imm32 p1, 0x22213332; - imm32 p2, 0x44415552; - imm32 p3, 0x66617772; - imm32 p4, 0x88819992; - imm32 p5, 0xaaa1bbb2; - imm32 fp, 0xccc1ddd2; - imm32 sp, 0xeee1fff2; - -// P-reg to P-reg to I reg: no stall - P1 = P2; - I0 = P1; - P3 = P2; - I1 = P3; - P5 = P4; - I2 = P5; - FP = SP; - I3 = FP; - - R4 = I3; - R5 = I2; - R6 = I1; - R7 = I0; - CHECKREG r4, 0xEEE1FFF2; - CHECKREG r5, 0x88819992; - CHECKREG r6, 0x44415552; - CHECKREG r7, 0x44415552; - -//imm32 p0, 0x00001111; - imm32 p1, 0x22213332; - imm32 p2, 0x44415552; - imm32 p3, 0x66617772; - imm32 p4, 0x88819992; - imm32 p5, 0xaaa1bbb2; - imm32 fp, 0xccc1ddd2; - imm32 sp, 0xe111fff2; - -// P-reg to P-reg to M reg: no stall - P1 = P4; - M0 = P1; - P3 = P2; - M1 = P3; - P5 = P4; - M2 = P5; - FP = SP; - M3 = FP; - - R4 = M3; - R5 = M2; - R6 = M1; - R7 = M0; - CHECKREG r4, 0xE111FFF2; - CHECKREG r5, 0x88819992; - CHECKREG r6, 0x44415552; - CHECKREG r7, 0x88819992; - -//imm32 p0, 0x00001111; - imm32 p1, 0x22213332; - imm32 p2, 0x44215552; - imm32 p3, 0x66217772; - imm32 p4, 0x88219992; - imm32 p5, 0xaa21bbb2; - imm32 fp, 0xcc21ddd2; - imm32 sp, 0xee21fff2; - -// P-reg to P-reg to L reg: no stall - P1 = P0; - L0 = P1; - P3 = P2; - L1 = P3; - P5 = P4; - L2 = P5; - FP = SP; - L3 = FP; - - R4 = L3; - R5 = L2; - R6 = L1; - R7 = L0; - CHECKREG r4, 0xEE21FFF2; - CHECKREG r5, 0x88219992; - CHECKREG r6, 0x44215552; - -//imm32 p0, 0x00001111; - imm32 p1, 0x22213332; - imm32 p2, 0x44415532; - imm32 p3, 0x66617732; - imm32 p4, 0x88819932; - imm32 p5, 0xaaa1bb32; - imm32 fp, 0xccc1dd32; - imm32 sp, 0xeee1ff32; - -// P-reg to P-reg to B reg: no stall - P1 = FP; - B0 = P1; - P3 = P2; - B1 = P3; - P5 = P4; - B2 = P5; - FP = SP; - B3 = FP; - - R4 = B3; - R5 = B2; - R6 = B1; - R7 = B0; - CHECKREG r4, 0xEEE1FF32; - CHECKREG r5, 0x88819932; - CHECKREG r6, 0x44415532; - CHECKREG r7, 0xccc1dd32; - - imm32 i0, 0x03001131; - imm32 i1, 0x23223333; - imm32 i2, 0x43445535; - imm32 i3, 0x63667737; - imm32 m0, 0x83889939; - imm32 m1, 0xa3aabb3b; - imm32 m2, 0xc3ccdd3d; - imm32 m3, 0xe3eeff3f; - -// I,M-reg to P-reg to R-reg: no stall - P1 = I0; - R0 = P1; - P2 = I1; - R1 = P2; - P3 = I2; - R2 = P3; - P4 = I3; - R3 = P4; - P5 = M0; - R4 = P5; - SP = M1; - R5 = SP; - FP = M2; - R6 = FP; - FP = M3; - R7 = FP; - - CHECKREG r0, 0x03001131; - CHECKREG r1, 0x23223333; - CHECKREG r2, 0x43445535; - CHECKREG r3, 0x63667737; - CHECKREG r4, 0x83889939; - CHECKREG r5, 0xA3AABB3B; - CHECKREG r6, 0xC3CCDD3D; - CHECKREG r7, 0xE3EEFF3F; - - imm32 i0, 0x12001111; - imm32 i1, 0x12221333; - imm32 i2, 0x12441555; - imm32 i3, 0x12661777; - imm32 m0, 0x12881999; - imm32 m1, 0x12aa1bbb; - imm32 m2, 0x12cc1ddd; - imm32 m3, 0x12ee1fff; - -// I,M-reg to P-reg to L,B reg: no stall - P1 = I0; - L0 = P1; - P1 = I1; - L1 = P1; - P2 = I2; - L2 = P2; - P3 = I3; - L3 = P3; - P4 = M0; - B0 = P4; - P5 = M1; - B1 = P5; - SP = M2; - B2 = SP; - FP = M3; - B3 = FP; - -//CHECKREG r0, 0x12001111; - CHECKREG p1, 0x12221333; - CHECKREG p2, 0x12441555; - CHECKREG p3, 0x12661777; - CHECKREG p4, 0x12881999; - CHECKREG p5, 0x12AA1BBB; - CHECKREG sp, 0x12CC1DDD; - CHECKREG fp, 0x12EE1FFF; - - R0 = L3; - R1 = L2; - R2 = L1; - R3 = L0; - R4 = B3; - R5 = B2; - R6 = B1; - R7 = B0; - CHECKREG r0, 0x12661777; - CHECKREG r1, 0x12441555; - CHECKREG r2, 0x12221333; - CHECKREG r3, 0x12001111; - CHECKREG r4, 0x12EE1FFF; - CHECKREG r5, 0x12CC1DDD; - CHECKREG r6, 0x12AA1BBB; - CHECKREG r7, 0x12881999; - - imm32 l0, 0x23003111; - imm32 l1, 0x23223333; - imm32 l2, 0x23443555; - imm32 l3, 0x23663777; - imm32 b0, 0x23883999; - imm32 b0, 0x23aa3bbb; - imm32 b0, 0x23cc3ddd; - imm32 b0, 0x23ee3fff; - -// L,B-reg to P-reg to I,M reg: no stall - P1 = L0; - I0 = P1; - P1 = L1; - I1 = P1; - P2 = L2; - I2 = P2; - P3 = L3; - I3 = P3; - P4 = B0; - M0 = P4; - P5 = B1; - M1 = P5; - SP = B2; - M2 = SP; - FP = B3; - M3 = FP; - - R0 = M3; - R1 = M2; - R2 = M1; - R3 = M0; - R4 = I3; - R5 = I2; - R6 = I1; - R7 = I0; -//CHECKREG r0, 0x1EEE1FFF; - CHECKREG p1, 0x23223333; - CHECKREG p2, 0x23443555; - CHECKREG p3, 0x23663777; - CHECKREG p4, 0x23EE3FFF; - CHECKREG p5, 0x12AA1BBB; - CHECKREG sp, 0x12CC1DDD; - CHECKREG fp, 0x12EE1FFF; - - CHECKREG r0, 0x12EE1FFF; - CHECKREG r1, 0x12CC1DDD; - CHECKREG r2, 0x12AA1BBB; - CHECKREG r3, 0x23EE3FFF; - CHECKREG r4, 0x23663777; - CHECKREG r5, 0x23443555; - CHECKREG r6, 0x23223333; - CHECKREG r7, 0x23003111; - - pass diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_dep_stall.s b/sim/testsuite/sim/bfin/c_regmv_pr_dep_stall.s deleted file mode 100644 index 91dd0f8..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_pr_dep_stall.s +++ /dev/null @@ -1,237 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_stall/c_regmv_pr_dep_stall.dsp -// Spec Reference: regmv pr-dependency stall -# mach: bfin - -.include "testutils.inc" - start - - INIT_M_REGS 0; - -// R-reg to P-reg to R reg: stall - imm32 r0, 0x00001110; - imm32 r1, 0x00213330; - imm32 r2, 0x04015550; - imm32 r3, 0x06607770; - imm32 r4, 0x08810990; - imm32 r5, 0x01a1b0b0; - imm32 r6, 0x01c1dd00; - imm32 r7, 0x01e1fff0; - P1 = R1; - R0 = P1; - P2 = R2; - R1 = P2; - P3 = R3; - R2 = P3; - P4 = R4; - R3 = P4; - P5 = R5; - R4 = P5; - SP = R6; - R5 = P2; - FP = R7; - R6 = P3; - - CHECKREG r0, 0x00213330; - CHECKREG r1, 0x04015550; - CHECKREG r2, 0x06607770; - CHECKREG r3, 0x08810990; - CHECKREG r4, 0x01A1B0B0; - CHECKREG r5, 0x04015550; - CHECKREG r6, 0x06607770; - CHECKREG r7, 0x01E1FFF0; - -// R-reg to P-reg to I,M reg: stall - imm32 r0, 0x10001111; - imm32 r1, 0x11213331; - imm32 r2, 0x14115551; - imm32 r3, 0x16617771; - imm32 r4, 0x18811991; - imm32 r5, 0x11a1b1b1; - imm32 r6, 0x11c1dd11; - imm32 r7, 0x11e1fff1; - P1 = R0; - I0 = P1; - P2 = R1; - I1 = P2; - P3 = R2; - I2 = P3; - P4 = R3; - I3 = P4; - P5 = R4; - M0 = P5; - SP = R5; - M1 = SP; - FP = R6; - M2 = FP; - - R0 = I3; - R1 = I2; - R2 = I1; - R3 = I0; - R4 = M3; - R5 = M2; - R6 = M1; - R7 = M0; - CHECKREG r0, 0x16617771; - CHECKREG r1, 0x14115551; - CHECKREG r2, 0x11213331; - CHECKREG r3, 0x10001111; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x11C1DD11; - CHECKREG r6, 0x11A1B1B1; - CHECKREG r7, 0x18811991; - - CHECKREG p1, 0x10001111; - CHECKREG p2, 0x11213331; - CHECKREG p3, 0x14115551; - CHECKREG p4, 0x16617771; - CHECKREG p5, 0x18811991; - CHECKREG sp, 0x11A1B1B1; - CHECKREG fp, 0x11C1DD11; - - imm32 r0, 0x20001112; - imm32 r1, 0x21213332; - imm32 r2, 0x24115552; - imm32 r3, 0x26617772; - imm32 r4, 0x28811992; - imm32 r5, 0x21a1b1b2; - imm32 r6, 0x21c1dd12; - imm32 r7, 0x21e1fff2; - P1 = R3; - I3 = P1; - P2 = R4; - I0 = P2; - P3 = R5; - I1 = P3; - P4 = R6; - I2 = P4; - P5 = R7; - M1 = P5; - SP = R0; - M2 = SP; - FP = R1; - M3 = FP; - - R0 = I3; - R1 = I2; - R2 = I1; - R3 = I0; - R4 = M3; - R5 = M2; - R6 = M1; - R7 = M0; - CHECKREG r0, 0x26617772; - CHECKREG r1, 0x21C1DD12; - CHECKREG r2, 0x21A1B1B2; - CHECKREG r3, 0x28811992; - CHECKREG r4, 0x21213332; - CHECKREG r5, 0x20001112; - CHECKREG r6, 0x21E1FFF2; - CHECKREG r7, 0x18811991; - - CHECKREG p1, 0x26617772; - CHECKREG p2, 0x28811992; - CHECKREG p3, 0x21A1B1B2; - CHECKREG p4, 0x21C1DD12; - CHECKREG p5, 0x21E1FFF2; - CHECKREG sp, 0x20001112; - CHECKREG fp, 0x21213332; - -// R-reg to P-reg to L,B reg: stall - imm32 r0, 0x30001113; - imm32 r1, 0x31213333; - imm32 r2, 0x34115553; - imm32 r3, 0x36617773; - imm32 r4, 0x38811993; - imm32 r5, 0x31a1b1b3; - imm32 r6, 0x31c1dd13; - imm32 r7, 0x31e1fff3; - P1 = R4; - L0 = P1; - P2 = R5; - L1 = P2; - P3 = R6; - L2 = P3; - P4 = R7; - L3 = P4; - P5 = R0; - B0 = P5; - SP = R1; - B1 = SP; - FP = R2; - B2 = FP; - - R0 = L3; - R1 = L2; - R2 = L1; - R3 = L0; - R4 = B3; - R5 = B2; - R6 = B1; - R7 = B0; - CHECKREG r0, 0x31E1FFF3; - CHECKREG r1, 0x31C1DD13; - CHECKREG r2, 0x31A1B1B3; - CHECKREG r3, 0x38811993; - CHECKREG r4, 0x00000000; - CHECKREG r5, 0x34115553; - CHECKREG r6, 0x31213333; - CHECKREG r7, 0x30001113; - - CHECKREG p1, 0x38811993; - CHECKREG p2, 0x31A1B1B3; - CHECKREG p3, 0x31C1DD13; - CHECKREG p4, 0x31E1FFF3; - CHECKREG p5, 0x30001113; - CHECKREG sp, 0x31213333; - CHECKREG fp, 0x34115553; - - imm32 r0, 0x40001114; - imm32 r1, 0x44213334; - imm32 r2, 0x44415554; - imm32 r3, 0x46647774; - imm32 r4, 0x48814994; - imm32 r5, 0x41a1b4b4; - imm32 r6, 0x41c1dd44; - imm32 r7, 0x41e1fff4; - P1 = R5; - L2 = P1; - P2 = R6; - L3 = P2; - P3 = R7; - L0 = P3; - P4 = R0; - L1 = P4; - P5 = R1; - B2 = P5; - SP = R2; - B3 = SP; - FP = R3; - B0 = FP; - - R0 = L3; - R1 = L2; - R2 = L1; - R3 = L0; - R4 = B3; - R5 = B2; - R6 = B1; - R7 = B0; - CHECKREG r0, 0x41C1DD44; - CHECKREG r1, 0x41A1B4B4; - CHECKREG r2, 0x40001114; - CHECKREG r3, 0x41E1FFF4; - CHECKREG r4, 0x44415554; - CHECKREG r5, 0x44213334; - CHECKREG r6, 0x31213333; - CHECKREG r7, 0x46647774; - - CHECKREG p1, 0x41A1B4B4; - CHECKREG p2, 0x41C1DD44; - CHECKREG p3, 0x41E1FFF4; - CHECKREG p4, 0x40001114; - CHECKREG p5, 0x44213334; - CHECKREG sp, 0x44415554; - CHECKREG fp, 0x46647774; - - pass diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_dr.s b/sim/testsuite/sim/bfin/c_regmv_pr_dr.s deleted file mode 100644 index fe1826f..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_pr_dr.s +++ /dev/null @@ -1,147 +0,0 @@ -//Original:/testcases/core/c_regmv_pr_dr/c_regmv_pr_dr.dsp -// Spec Reference: regmv preg to dreg -# mach: bfin - -.include "testutils.inc" - start - - - - - -imm32 r0, 0x00000001; -imm32 r1, 0x00020003; -imm32 r2, 0x00040005; -imm32 r3, 0x00060007; -imm32 r4, 0x00080009; -imm32 r5, 0x000a000b; -imm32 r6, 0x000c000d; -imm32 r7, 0x000e000f; - -//imm32 p0, 0x00000001; -imm32 p1, 0x10082001; -imm32 p2, 0x10092002; -imm32 p3, 0x100a2003; -imm32 p4, 0x100b2004; -imm32 p5, 0x100c2005; -imm32 sp, 0x100d2006; -imm32 fp, 0x100e2007; - -//--------- Preg to dreg : Rx <= Px ------ - - -R0 = P1; -R1 = P1; -R2 = P1; -R3 = P1; -R4 = P1; -R5 = P1; -R6 = P1; -R7 = P1; -CHECKREG r1, 0x10082001; -CHECKREG r2, 0x10082001; -CHECKREG r3, 0x10082001; -CHECKREG r4, 0x10082001; -CHECKREG r5, 0x10082001; -CHECKREG r6, 0x10082001; -CHECKREG r7, 0x10082001; - -R0 = P2; -R1 = P2; -R2 = P2; -R3 = P2; -R4 = P2; -R5 = P2; -R6 = P2; -R7 = P2; -CHECKREG r0, 0x10092002; -CHECKREG r1, 0x10092002; -CHECKREG r2, 0x10092002; -CHECKREG r3, 0x10092002; -CHECKREG r4, 0x10092002; -CHECKREG r5, 0x10092002; -CHECKREG r6, 0x10092002; -CHECKREG r7, 0x10092002; - -R0 = P3; -R1 = P3; -R2 = P3; -R3 = P3; -R4 = P3; -R5 = P3; -R6 = P3; -R7 = P3; -CHECKREG r1, 0x100a2003; -CHECKREG r2, 0x100a2003; -CHECKREG r3, 0x100a2003; -CHECKREG r4, 0x100a2003; -CHECKREG r5, 0x100a2003; -CHECKREG r6, 0x100a2003; -CHECKREG r7, 0x100a2003; - -R0 = P4; -R1 = P4; -R2 = P4; -R3 = P4; -R4 = P4; -R5 = P4; -R6 = P4; -R7 = P4; -CHECKREG r0, 0x100b2004; -CHECKREG r1, 0x100b2004; -CHECKREG r2, 0x100b2004; -CHECKREG r3, 0x100b2004; -CHECKREG r4, 0x100b2004; -CHECKREG r5, 0x100b2004; -CHECKREG r6, 0x100b2004; -CHECKREG r7, 0x100b2004; - -R1 = P5; -R2 = P5; -R3 = P5; -R4 = P5; -R5 = P5; -R6 = P5; -R7 = P5; -CHECKREG r1, 0x100c2005; -CHECKREG r2, 0x100c2005; -CHECKREG r3, 0x100c2005; -CHECKREG r4, 0x100c2005; -CHECKREG r5, 0x100c2005; -CHECKREG r6, 0x100c2005; -CHECKREG r7, 0x100c2005; - -R0 = SP; -R1 = SP; -R2 = SP; -R3 = SP; -R4 = SP; -R5 = SP; -R6 = SP; -R7 = SP; -CHECKREG r0, 0x100d2006; -CHECKREG r1, 0x100d2006; -CHECKREG r2, 0x100d2006; -CHECKREG r3, 0x100d2006; -CHECKREG r4, 0x100d2006; -CHECKREG r5, 0x100d2006; -CHECKREG r6, 0x100d2006; -CHECKREG r7, 0x100d2006; - -R0 = FP; -R1 = FP; -R2 = FP; -R3 = FP; -R4 = FP; -R5 = FP; -R6 = FP; -R7 = FP; -CHECKREG r1, 0x100e2007; -CHECKREG r2, 0x100e2007; -CHECKREG r3, 0x100e2007; -CHECKREG r4, 0x100e2007; -CHECKREG r5, 0x100e2007; -CHECKREG r6, 0x100e2007; -CHECKREG r7, 0x100e2007; - -pass diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_imlb.s b/sim/testsuite/sim/bfin/c_regmv_pr_imlb.s deleted file mode 100644 index 31ff3e9..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_pr_imlb.s +++ /dev/null @@ -1,382 +0,0 @@ -//Original:/testcases/core/c_regmv_pr_imlb/c_regmv_pr_imlb.dsp -// Spec Reference: regmv preg-to-imlb reg -# mach: bfin - -.include "testutils.inc" - start - -// check R-reg to imlb-reg move - -imm32 r0, 0x00000001; -imm32 p1, 0x00020003; -imm32 p2, 0x00040005; -imm32 p3, 0x00060007; -imm32 p4, 0x00080009; -imm32 p5, 0x000a000b; -imm32 sp, 0x000c000d; -imm32 fp, 0x000e000f; -I0 = P1; -I1 = P1; -I2 = P1; -I3 = P1; -M0 = P1; -M1 = P1; -M2 = P1; -M3 = P1; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x00020003; -CHECKREG r1, 0x00020003; -CHECKREG r2, 0x00020003; -CHECKREG r3, 0x00020003; -CHECKREG r4, 0x00020003; -CHECKREG r5, 0x00020003; -CHECKREG r6, 0x00020003; -CHECKREG r7, 0x00020003; - -imm32 p2, 0x00040005; -I0 = P2; -I1 = P2; -I2 = P2; -I3 = P2; -M0 = P2; -M1 = P2; -M2 = P2; -M3 = P2; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x00040005; -CHECKREG r1, 0x00040005; -CHECKREG r2, 0x00040005; -CHECKREG r3, 0x00040005; -CHECKREG r4, 0x00040005; -CHECKREG r5, 0x00040005; -CHECKREG r6, 0x00040005; -CHECKREG r7, 0x00040005; - -imm32 p3, 0x00060007; -I0 = P3; -I1 = P3; -I2 = P3; -I3 = P3; -M0 = P3; -M1 = P3; -M2 = P3; -M3 = P3; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x00060007; -CHECKREG r1, 0x00060007; -CHECKREG r2, 0x00060007; -CHECKREG r3, 0x00060007; -CHECKREG r4, 0x00060007; -CHECKREG r5, 0x00060007; -CHECKREG r6, 0x00060007; -CHECKREG r7, 0x00060007; - -imm32 p4, 0x00080009; -I0 = P4; -I1 = P4; -I2 = P4; -I3 = P4; -M0 = P4; -M1 = P4; -M2 = P4; -M3 = P4; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x00080009; -CHECKREG r1, 0x00080009; -CHECKREG r2, 0x00080009; -CHECKREG r3, 0x00080009; -CHECKREG r4, 0x00080009; -CHECKREG r5, 0x00080009; -CHECKREG r6, 0x00080009; -CHECKREG r7, 0x00080009; - -imm32 p5, 0x000a000b; -I0 = P5; -I1 = P5; -I2 = P5; -I3 = P5; -M0 = P5; -M1 = P5; -M2 = P5; -M3 = P5; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x000a000b; -CHECKREG r1, 0x000a000b; -CHECKREG r2, 0x000a000b; -CHECKREG r3, 0x000a000b; -CHECKREG r4, 0x000a000b; -CHECKREG r5, 0x000a000b; -CHECKREG r6, 0x000a000b; -CHECKREG r7, 0x000a000b; - -imm32 sp, 0x000c000d; -I0 = SP; -I1 = SP; -I2 = SP; -I3 = SP; -M0 = SP; -M1 = SP; -M2 = SP; -M3 = SP; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x000c000d; -CHECKREG r1, 0x000c000d; -CHECKREG r2, 0x000c000d; -CHECKREG r3, 0x000c000d; -CHECKREG r4, 0x000c000d; -CHECKREG r5, 0x000c000d; -CHECKREG r6, 0x000c000d; -CHECKREG r7, 0x000c000d; - -imm32 fp, 0x000e000f; -I0 = FP; -I1 = FP; -I2 = FP; -I3 = FP; -M0 = FP; -M1 = FP; -M2 = FP; -M3 = FP; -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -R4 = M0; -R5 = M1; -R6 = M2; -R7 = M3; -CHECKREG r0, 0x000e000f; -CHECKREG r1, 0x000e000f; -CHECKREG r2, 0x000e000f; -CHECKREG r3, 0x000e000f; -CHECKREG r4, 0x000e000f; -CHECKREG r5, 0x000e000f; -CHECKREG r6, 0x000e000f; -CHECKREG r7, 0x000e000f; - - -imm32 p1, 0x00020003; -L0 = P1; -L1 = P1; -L2 = P1; -L3 = P1; -B0 = P1; -B1 = P1; -B2 = P1; -B3 = P1; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x00020003; -CHECKREG r1, 0x00020003; -CHECKREG r2, 0x00020003; -CHECKREG r3, 0x00020003; -CHECKREG r4, 0x00020003; -CHECKREG r5, 0x00020003; -CHECKREG r6, 0x00020003; -CHECKREG r7, 0x00020003; - -imm32 p2, 0x00040005; -L0 = P2; -L1 = P2; -L2 = P2; -L3 = P2; -B0 = P2; -B1 = P2; -B2 = P2; -B3 = P2; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x00040005; -CHECKREG r1, 0x00040005; -CHECKREG r2, 0x00040005; -CHECKREG r3, 0x00040005; -CHECKREG r4, 0x00040005; -CHECKREG r5, 0x00040005; -CHECKREG r6, 0x00040005; -CHECKREG r7, 0x00040005; - -imm32 p3, 0x00060007; -L0 = P3; -L1 = P3; -L2 = P3; -L3 = P3; -B0 = P3; -B1 = P3; -B2 = P3; -B3 = P3; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x00060007; -CHECKREG r1, 0x00060007; -CHECKREG r2, 0x00060007; -CHECKREG r3, 0x00060007; -CHECKREG r4, 0x00060007; -CHECKREG r5, 0x00060007; -CHECKREG r6, 0x00060007; -CHECKREG r7, 0x00060007; - -imm32 p4, 0x00080009; -L0 = P4; -L1 = P4; -L2 = P4; -L3 = P4; -B0 = P4; -B1 = P4; -B2 = P4; -B3 = P4; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x00080009; -CHECKREG r1, 0x00080009; -CHECKREG r2, 0x00080009; -CHECKREG r3, 0x00080009; -CHECKREG r4, 0x00080009; -CHECKREG r5, 0x00080009; -CHECKREG r6, 0x00080009; -CHECKREG r7, 0x00080009; - -imm32 p5, 0x000a000b; -L0 = P5; -L1 = P5; -L2 = P5; -L3 = P5; -B0 = P5; -B1 = P5; -B2 = P5; -B3 = P5; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x000a000b; -CHECKREG r1, 0x000a000b; -CHECKREG r2, 0x000a000b; -CHECKREG r3, 0x000a000b; -CHECKREG r4, 0x000a000b; -CHECKREG r5, 0x000a000b; -CHECKREG r6, 0x000a000b; -CHECKREG r7, 0x000a000b; - -imm32 sp, 0x000c000d; -L0 = SP; -L1 = SP; -L2 = SP; -L3 = SP; -B0 = SP; -B1 = SP; -B2 = SP; -B3 = SP; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x000c000d; -CHECKREG r1, 0x000c000d; -CHECKREG r2, 0x000c000d; -CHECKREG r3, 0x000c000d; -CHECKREG r4, 0x000c000d; -CHECKREG r5, 0x000c000d; -CHECKREG r6, 0x000c000d; -CHECKREG r7, 0x000c000d; - -imm32 fp, 0x000e000f; -L0 = FP; -L1 = FP; -L2 = FP; -L3 = FP; -B0 = FP; -B1 = FP; -B2 = FP; -B3 = FP; -R0 = L0; -R1 = L1; -R2 = L2; -R3 = L3; -R4 = B0; -R5 = B1; -R6 = B2; -R7 = B3; -CHECKREG r0, 0x000e000f; -CHECKREG r1, 0x000e000f; -CHECKREG r2, 0x000e000f; -CHECKREG r3, 0x000e000f; -CHECKREG r4, 0x000e000f; -CHECKREG r5, 0x000e000f; -CHECKREG r6, 0x000e000f; -CHECKREG r7, 0x000e000f; - -pass diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_pr.s b/sim/testsuite/sim/bfin/c_regmv_pr_pr.s deleted file mode 100644 index 9fb83f6..0000000 --- a/sim/testsuite/sim/bfin/c_regmv_pr_pr.s +++ /dev/null @@ -1,95 +0,0 @@ -//Original:/testcases/core/c_regmv_pr_pr/c_regmv_pr_pr.dsp -// Spec Reference: regmv preg-to-preg -# mach: bfin - -.include "testutils.inc" - start - -// check p-reg to p-reg move - imm32 p1, 0x20021003; - imm32 p2, 0x20041005; - imm32 p4, 0x20081009; - imm32 p5, 0x200a100b; - imm32 fp, 0x200e100f; - - imm32 p1, 0x20021003; - imm32 p2, 0x20041005; - imm32 p4, 0x20081009; - imm32 p5, 0x200a100b; - imm32 fp, 0x200e100f; - P1 = P1; - P2 = P1; - P4 = P1; - P5 = P1; - FP = P1; - CHECKREG p1, 0x20021003; - CHECKREG p2, 0x20021003; - CHECKREG p4, 0x20021003; - CHECKREG p5, 0x20021003; - CHECKREG fp, 0x20021003; - - imm32 p1, 0x20021003; - imm32 p2, 0x20041005; - imm32 p4, 0x20081009; - imm32 p5, 0x200a100b; - imm32 fp, 0x200e100f; - P1 = P2; - P2 = P2; - P4 = P2; - P5 = P2; - FP = P2; - CHECKREG p1, 0x20041005; - CHECKREG p2, 0x20041005; - CHECKREG p4, 0x20041005; - CHECKREG p5, 0x20041005; - CHECKREG fp, 0x20041005; - - imm32 p1, 0x20021003; - imm32 p2, 0x20041005; - imm32 p4, 0x20081009; - imm32 p5, 0x200a100b; - imm32 fp, 0x200e100f; - P1 = P4; - P2 = P4; - P4 = P4; - P5 = P4; - FP = P4; - CHECKREG p1, 0x20081009; - CHECKREG p2, 0x20081009; - CHECKREG p4, 0x20081009; - CHECKREG p5, 0x20081009; - CHECKREG fp, 0x20081009; - - imm32 p1, 0x20021003; - imm32 p2, 0x20041005; - imm32 p4, 0x20081009; - imm32 p5, 0x200a100b; - imm32 fp, 0x200e100f; - P1 = P5; - P2 = P5; - P4 = P5; - P5 = P5; - FP = P5; - CHECKREG p1, 0x200a100b; - CHECKREG p2, 0x200a100b; - CHECKREG p4, 0x200a100b; - CHECKREG p5, 0x200a100b; - CHECKREG fp, 0x200a100b; - - imm32 p1, 0x20021003; - imm32 p2, 0x20041005; - imm32 p4, 0x20081009; - imm32 p5, 0x200a100b; - imm32 fp, 0x200e100f; - P1 = FP; - P2 = FP; - P4 = FP; - P5 = FP; - FP = FP; - CHECKREG p1, 0x200e100f; - CHECKREG p2, 0x200e100f; - CHECKREG p4, 0x200e100f; - CHECKREG p5, 0x200e100f; - CHECKREG fp, 0x200e100f; - - pass diff --git a/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S b/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S deleted file mode 100644 index fb231d3..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S +++ /dev/null @@ -1,342 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv/c_seq_ac_raise_mv.dsp -// Spec Reference: sequencer stage AC (raise + regmv) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH - R0 = 0xa01 (X); - R1 = 0xb02 (X); - R2 = 0xc03 (X); - R3 = 0xd04 (X); - R4 = 0xe05 (X); - R5 = 0xf06 (X); - R6 = 0x107 (X); - R7 = 0x208 (X); -LD32(p1, 0x12345678); -LD32(p2, 0x05612496); -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - - -RAISE 2; // RTN - P1 = R7; - R0 = P1; -// [--sp] = (r7-r0); - -RAISE 5; // RTI - P2 = R6; - R1 = P2; - -// [--sp] = (r7-r1); - - -RAISE 6; // RTI - P3 = R5; - R2 = P3; - [ -- SP ] = ( R7:2 ); -// POP - -RAISE 7; // RTI - P4 = R4; - R3 = P4; -// (r7-r2) = [sp++]; - - - -CHECKREG(r0, 0x00000208); -CHECKREG(r1, 0x00000107); -CHECKREG(r2, 0x00000F06); -CHECKREG(r3, 0x00000E05); -CHECKREG(r4, 0x00000E05); -CHECKREG(r5, 0x00000F06); -CHECKREG(r6, 0x00000107); -CHECKREG(r7, 0x00000208); - - R0 = 0xa41 (X); - R1 = 0xb52 (X); - R2 = 0xc63 (X); - R3 = 0xd74 (X); - R4 = 0xe85 (X); - R5 = 0xf96 (X); - R6 = 0x1a7 (X); - R7 = 0x2b8 (X); -RAISE 8; // RTI - P1 = R0; - R6 = P1; -// (r7-r1) = [sp++]; -CHECKREG(r0, 0x00000A41); -CHECKREG(r1, 0x00000B52); -CHECKREG(r2, 0x00000C63); -CHECKREG(r3, 0x00000D74); -CHECKREG(r4, 0x00000E85); -CHECKREG(r5, 0x00000F96); -CHECKREG(r6, 0x00000A41); -CHECKREG(r7, 0x000002B8); - -RAISE 9; // RTI - P2 = R1; - R7 = P2; -// (r7-r0) = [sp++]; - -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000006); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000002); -CHECKREG(r4, 0x00000E85); -CHECKREG(r5, 0x00000F96); -CHECKREG(r6, 0x00000A41); -CHECKREG(r7, 0x00000B52); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I0 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I1 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I2 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I3 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S b/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S deleted file mode 100644 index f5fdd4a..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S +++ /dev/null @@ -1,359 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv_ppop/c_seq_ac_raise_mv_ppop.dsp -// Spec Reference: sequencer stage AC (raise + regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; -LD32(p1, 0x12345678); -LD32(p2, 0x05612496); -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - - -RAISE 2; // RTN - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:1 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -RAISE 6; // RTI - P3 = R3; - R4 = P3; - [ -- SP ] = ( R7:2 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -RAISE 7; // RTI - P4 = R4; - R5 = P4; - ( R7:2 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x00000024); -CHECKREG(r5, 0x00000026); -CHECKREG(r6, 0x00000027); -CHECKREG(r7, 0x00000028); - -RAISE 8; // RTI - P1 = R1; - R5 = P1; - ( R7:1 ) = [ SP ++ ]; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000012); -CHECKREG(r2, 0x00000013); -CHECKREG(r3, 0x00000013); -CHECKREG(r4, 0x00000015); -CHECKREG(r5, 0x00000016); -CHECKREG(r6, 0x00000017); -CHECKREG(r7, 0x00000018); - -RAISE 9; // RTI - P2 = R2; - R5 = P2; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000006); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000002); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S b/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S deleted file mode 100644 index 163b2ed..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S +++ /dev/null @@ -1,359 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ac_regmv_pushpop/c_seq_ac_regmv_pushpop.dsp -// Spec Reference: sequencer stage AC (regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; -LD32(p1, 0x12345678); -LD32(p2, 0x05612496); -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - - - //RAISE 2; // RTN - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - - //RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:1 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - - //RAISE 6; // RTI - P3 = R3; - R4 = P3; - [ -- SP ] = ( R7:2 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - - //RAISE 7; // RTI - P4 = R4; - R5 = P4; - ( R7:2 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x00000024); -CHECKREG(r5, 0x00000026); -CHECKREG(r6, 0x00000027); -CHECKREG(r7, 0x00000028); - - //RAISE 8; // RTI - P1 = R1; - R5 = P1; - ( R7:1 ) = [ SP ++ ]; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000012); -CHECKREG(r2, 0x00000013); -CHECKREG(r3, 0x00000013); -CHECKREG(r4, 0x00000015); -CHECKREG(r5, 0x00000016); -CHECKREG(r6, 0x00000017); -CHECKREG(r7, 0x00000018); - - //RAISE 9; // RTI - P2 = R2; - R5 = P2; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S b/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S deleted file mode 100644 index 6ac5d60..0000000 --- a/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S +++ /dev/null @@ -1,341 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_dec_raise_pushpop/c_seq_dec_raise_pushpop.dsp -// Spec Reference: sequencer stage DEC (raise + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - -RAISE 2; // RTN - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -RAISE 5; // RTI - [ -- SP ] = ( R7:1 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -RAISE 6; // RTI - [ -- SP ] = ( R7:2 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -RAISE 7; // RTI - ( R7:2 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x00000025); -CHECKREG(r5, 0x00000026); -CHECKREG(r6, 0x00000027); -CHECKREG(r7, 0x00000028); - -RAISE 8; // RTI - ( R7:1 ) = [ SP ++ ]; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000012); -CHECKREG(r2, 0x00000013); -CHECKREG(r3, 0x00000014); -CHECKREG(r4, 0x00000015); -CHECKREG(r5, 0x00000016); -CHECKREG(r6, 0x00000017); -CHECKREG(r7, 0x00000018); - -RAISE 9; // RTI - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000006); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000002); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S deleted file mode 100644 index be9be51..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S +++ /dev/null @@ -1,377 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex1_brcc_mv_pop/c_seq_ex1_brcc_mv_pop.dsp -// Spec Reference: sequencer stage ex1 ( brcc + regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -R0 = 0; -ASTAT = R0; - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; -LD32(p1, 0x12345678); -LD32(p2, 0x05612496); -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - - - [ -- SP ] = ( R7:0 ); -// RAISE 2; // RTN -IF !CC JUMP LABEL1 (BP); - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -// RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// RAISE 6; // RTI -IF !CC JUMP LABEL2 (BP); - P3 = R3; - R4 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -// RAISE 7; // RTI -IF CC JUMP LABEL4; // SHOULD NOT EXECUTE - P4 = R4; - R5 = P4; - ( R7:0 ) = [ SP ++ ]; - -LABEL4: - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000003); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); - -// RAISE 8; // RTI -IF !CC JUMP LABEL3 (BP); - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -// RAISE 9; // RTI - P2 = R6; - R7 = P2; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S deleted file mode 100644 index d55d61d..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S +++ /dev/null @@ -1,393 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex1_call_mv_pop/c_seq_ex1_call_mv_pop.dsp -// Spec Reference: sequencer stage ex1 ( call + regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - -LD32_LABEL(p1, SUBR1); - - - // PUT YOUR TEST HERE! -// PUSH - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - - - [ -- SP ] = ( R7:0 ); -// RAISE 2; // RTN -CALL (p1); - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -// RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// RAISE 6; // RTI -CALL SUBR2; - P1 = R3; - R4 = P1; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -// RAISE 7; // RTI - P4 = R4; - R5 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000012); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x00000024); -CHECKREG(r5, 0x00000026); -CHECKREG(r6, 0x00000027); -CHECKREG(r7, 0x00000028); - -// RAISE 8; // RTI -CALL SUBR3; - P3 = R5; - R6 = P3; - ( R7:0 ) = [ SP ++ ]; -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000012); -CHECKREG(r2, 0x00000013); -CHECKREG(r3, 0x00000013); -CHECKREG(r4, 0x00000015); -CHECKREG(r5, 0x00000016); -CHECKREG(r6, 0x00000017); -CHECKREG(r7, 0x00000018); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -// RAISE 9; // RTI - P4 = R6; - R7 = P4; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000002); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000000); - - -END: -dbg_pass; // End the test - - -SUBR1: // should jump here - I0 += 2; - RTS; - I3 += 2; // should not go here - RTS; - -SUBR2: // should jump here - I1 += 2; - RTS; - I3 += 2; // should not go here - RTS; - -SUBR3: // should jump here - I2 += 2; - RTS; - I3 += 2; // should not go here - RTS; - - - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S deleted file mode 100644 index 089c300..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S +++ /dev/null @@ -1,375 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex1_j_mv_pop/c_seq_ex1_j_mv_pop.dsp -// Spec Reference: sequencer stage ex1 (jump + regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; -LD32(p1, 0x12345678); -LD32(p2, 0x05612496); -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - - - [ -- SP ] = ( R7:0 ); -// RAISE 2; // RTN -JUMP.S LABEL1; - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -// RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// RAISE 6; // RTI -JUMP.S LABEL2; - P3 = R3; - R4 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -// RAISE 7; // RTI - P4 = R4; - R5 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000003); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); - -// RAISE 8; // RTI -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -// RAISE 9; // RTI - P2 = R6; - R7 = P2; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S deleted file mode 100644 index 059a61b..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S +++ /dev/null @@ -1,377 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_brcc_mv_pop/c_seq_ex1_raise_brcc_mv_pop.dsp -// Spec Reference: sequencer stage ex1 (raise+ brcc + regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -R0 = 0; -ASTAT = R0; - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; -LD32(p1, 0x12345678); -LD32(p2, 0x05612496); -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - - - [ -- SP ] = ( R7:0 ); -RAISE 2; // RTN -IF !CC JUMP LABEL1; - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -RAISE 6; // RTI -IF !CC JUMP LABEL2; - P3 = R3; - R4 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -RAISE 7; // RTI -IF CC JUMP LABEL4; // SHOULD NOT EXECUTE - P4 = R4; - R5 = P4; - ( R7:0 ) = [ SP ++ ]; - -LABEL4: - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000003); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); - -RAISE 8; // RTI -IF !CC JUMP LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -RAISE 9; // RTI - P2 = R6; - R7 = P2; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000006); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000002); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S deleted file mode 100644 index 1b70686..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S +++ /dev/null @@ -1,393 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_call_mv_pop/c_seq_ex1_raise_call_mv_pop.dsp -// Spec Reference: sequencer stage ex1 (raise+ call + regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - -LD32_LABEL(p1, SUBR1); - - - // PUT YOUR TEST HERE! -// PUSH - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - - - [ -- SP ] = ( R7:0 ); -RAISE 2; // RTN -CALL (p1); - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -RAISE 6; // RTI -CALL SUBR2; - P1 = R3; - R4 = P1; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -RAISE 7; // RTI - P4 = R4; - R5 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000012); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x00000024); -CHECKREG(r5, 0x00000026); -CHECKREG(r6, 0x00000027); -CHECKREG(r7, 0x00000028); - -RAISE 8; // RTI -CALL SUBR3; - P3 = R5; - R6 = P3; - ( R7:0 ) = [ SP ++ ]; -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000012); -CHECKREG(r2, 0x00000013); -CHECKREG(r3, 0x00000013); -CHECKREG(r4, 0x00000015); -CHECKREG(r5, 0x00000016); -CHECKREG(r6, 0x00000017); -CHECKREG(r7, 0x00000018); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -RAISE 9; // RTI - P4 = R6; - R7 = P4; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000008); -CHECKREG(r1, 0x00000004); -CHECKREG(r2, 0x00000004); -CHECKREG(r3, 0x00000002); - - -END: -dbg_pass; // End the test - - -SUBR1: // should jump here - I0 += 2; - RTS; - I3 += 2; // should not go here - RTS; - -SUBR2: // should jump here - I1 += 2; - RTS; - I3 += 2; // should not go here - RTS; - -SUBR3: // should jump here - I2 += 2; - RTS; - I3 += 2; // should not go here - RTS; - - - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S deleted file mode 100644 index 2d88bb4..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S +++ /dev/null @@ -1,375 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_j_mv_pop/c_seq_ex1_raise_j_mv_pop.dsp -// Spec Reference: sequencer stage ex1 (raise+ jump + regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; -LD32(p1, 0x12345678); -LD32(p2, 0x05612496); -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - - - [ -- SP ] = ( R7:0 ); -RAISE 2; // RTN -JUMP.S LABEL1; - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -RAISE 6; // RTI -JUMP.S LABEL2; - P3 = R3; - R4 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -RAISE 7; // RTI - P4 = R4; - R5 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000003); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); - -RAISE 8; // RTI -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -RAISE 9; // RTI - P2 = R6; - R7 = P2; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000006); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000002); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S deleted file mode 100644 index c32d062..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S +++ /dev/null @@ -1,377 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex2_brcc_mp_mv_pop/c_seq_ex2_brcc_mp_mv_pop.dsp -// Spec Reference: sequencer stage ex2 ( brcc (mis-pred)+ regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -R0 = 0; -ASTAT = R0; - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; -LD32(p1, 0x12345678); -LD32(p2, 0x05612496); -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - - - [ -- SP ] = ( R7:0 ); -// RAISE 2; // RTN -IF CC JUMP LABEL1 (BP); - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -// RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// RAISE 6; // RTI -IF !CC JUMP LABEL2 (BP); - P3 = R3; - R4 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -// RAISE 7; // RTI -IF CC JUMP LABEL4 (BP); // SHOULD NOT EXECUTE - P4 = R4; - R5 = P4; - ( R7:0 ) = [ SP ++ ]; - -LABEL4: - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000012); -CHECKREG(r2, 0x00000013); -CHECKREG(r3, 0x00000013); -CHECKREG(r4, 0x00000015); -CHECKREG(r5, 0x00000016); -CHECKREG(r6, 0x00000017); -CHECKREG(r7, 0x00000018); - -// RAISE 8; // RTI -IF !CC JUMP LABEL3 (BP); - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -// RAISE 9; // RTI - P2 = R6; - R7 = P2; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S b/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S deleted file mode 100644 index 6e156d7..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S +++ /dev/null @@ -1,386 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmr_mvpop/c_seq_ex2_mmr_mvpop.dsp -// Spec Reference: sequencer stage ex2 (mmr + regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; -LD32(p1, 0x12345678); -LD32(p2, 0x05612496); -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - - -// [--sp] = (r7-r0); -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -LD32(r0, 0x55552345); -// RAISE 2; // RTN - [ P1 ] = R0; -// jump LABEL1; - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -// RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; -CSYNC; -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -// RAISE 6; // RTI - R0 = [ P1 ]; -// jump LABEL2; - P3 = R3; - R4 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -//CHECKREG(r0, 0x55552345); -// RAISE 7; // RTI - P4 = R4; - R5 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x55552345); -CHECKREG(r1, 0x00000012); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x00000024); -CHECKREG(r5, 0x00000026); -CHECKREG(r6, 0x00000027); -CHECKREG(r7, 0x00000028); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -// RAISE 8; // RTI - R0 = [ P1 ]; -// jump LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -CSYNC; -CHECKREG(r0, 0x55552345); // CHECKREG can not be skipped -CHECKREG(r1, 0x00000012); // so they cannot appear here -CHECKREG(r2, 0x00000013); -CHECKREG(r3, 0x00000013); -CHECKREG(r4, 0x00000015); -CHECKREG(r5, 0x00000016); -CHECKREG(r6, 0x00000017); -CHECKREG(r7, 0x00000018); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -//CHECKREG(r0, 0x55552345); -// RAISE 9; // RTI - P2 = R6; - R7 = P2; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x55552345); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S b/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S deleted file mode 100644 index 11eba1a..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S +++ /dev/null @@ -1,386 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmrj_mvpop/c_seq_ex2_mmrj_mvpop.dsp -// Spec Reference: sequencer stage ex2 ( mmr + jump + regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -LD32(p2, DATA_ADDR_1); -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - -LD32(r2, 0x14789232); - [ P1 ] = R2; -CSYNC; - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - - [ -- SP ] = ( R7:0 ); -// RAISE 2; // RTN - [ P1 ] = R0; -JUMP.S LABEL1; - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -// RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -// RAISE 6; // RTI - R0 = [ P1 ]; -JUMP.S LABEL2; - P3 = R3; - R4 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -CHECKREG(r0, 0x00000001); -// RAISE 7; // RTI - P4 = R4; - R5 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000003); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -// RAISE 8; // RTI - R0 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -CHECKREG(r0, 0x00000001); -// RAISE 9; // RTI - P2 = R6; - R7 = P2; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S b/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S deleted file mode 100644 index 5f86570..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S +++ /dev/null @@ -1,385 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmr_mvpop/c_seq_ex2_raise_mmr_mvpop.dsp -// Spec Reference: sequencer stage ex2 (raise+ mmr + regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; -LD32(p1, 0x12345678); -LD32(p2, 0x05612496); -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - - -// [--sp] = (r7-r0); -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -LD32(r0, 0x55552345); -RAISE 2; // RTN - [ P1 ] = R0; -// jump LABEL1; - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; -CSYNC; -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -RAISE 6; // RTI - R0 = [ P1 ]; -// jump LABEL2; - P3 = R3; - R4 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -RAISE 7; // RTI - P4 = R4; - R5 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x55552345); -CHECKREG(r1, 0x00000012); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x00000024); -CHECKREG(r5, 0x00000026); -CHECKREG(r6, 0x00000027); -CHECKREG(r7, 0x00000028); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -RAISE 8; // RTI - R0 = [ P1 ]; -// jump LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -CSYNC; -CHECKREG(r0, 0x55552345); // CHECKREG can not be skipped -CHECKREG(r1, 0x00000012); // so they cannot appear here -CHECKREG(r2, 0x00000013); -CHECKREG(r3, 0x00000013); -CHECKREG(r4, 0x00000015); -CHECKREG(r5, 0x00000016); -CHECKREG(r6, 0x00000017); -CHECKREG(r7, 0x00000018); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -//CHECKREG(r0, 0x55552345); -RAISE 9; // RTI - P2 = R6; - R7 = P2; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x55552345); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000006); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000002); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S b/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S deleted file mode 100644 index f32ec69..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S +++ /dev/null @@ -1,385 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmrj_mvpop/c_seq_ex2_raise_mmrj_mvpop.dsp -// Spec Reference: sequencer stage ex2 (raise+ mmr + jump+ regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; -LD32(p1, 0x12345678); -LD32(p2, 0x05612496); -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - - - [ -- SP ] = ( R7:0 ); -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -LD32(r0, 0x55552345); -RAISE 2; // RTN - [ P1 ] = R0; -JUMP.S LABEL1; - P1 = R1; - R2 = P1; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -RAISE 5; // RTI - P2 = R2; - R3 = P2; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; -CSYNC; -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -RAISE 6; // RTI - R0 = [ P1 ]; -JUMP.S LABEL2; - P3 = R3; - R4 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -CHECKREG(r0, 0x55552345); -RAISE 7; // RTI - P4 = R4; - R5 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x55552345); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000003); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -RAISE 8; // RTI - R0 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -CHECKREG(r0, 0x55552345); -RAISE 9; // RTI - P2 = R6; - R7 = P2; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000006); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000002); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S b/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S deleted file mode 100644 index d64de59..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S +++ /dev/null @@ -1,440 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_brcc_mvp/c_seq_ex3_ls_brcc_mvp.dsp -// Spec Reference: sequencer stage ex3 (ldst + brcc + regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** -R0 = 0; -ASTAT = R0; - // PUT YOUR TEST HERE! -// PUSH - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - - - [ -- SP ] = ( R7:0 ); -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -//LD32(p2, DATA_ADDR_1); -loadsym p2, DATA; -LD32(r0, 0x55552345); -// RAISE 2; // RTN -// r0 = [p2++]; - R1 = [ P1 ]; -IF !CC JUMP LABEL1 (BP); - - P3 = R7; - R4 = P3; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -// RAISE 5; // RTI -// r2 = [p2++]; - R3 = [ P1 ]; -IF CC JUMP LABEL2 (BP); // not taken - - P4 = R6; - R4 = P4; - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -// RAISE 6; // RTI -// r4 = [p2++]; - R5 = [ P1 ]; -IF !CC JUMP LABEL2 (BP); - P3 = R3; - R6 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -CSYNC; -CHECKREG(r0, 0x55552345); -//CHECKREG(r1, 0x000002B8); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x00000025); -//CHECKREG(r5, 0x000002B8); -// RAISE 7; // RTI -// r0 = [p2++]; - R1 = [ P1 ]; - P4 = R4; - R2 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x55552345); -//CHECKREG(r1, 0x000002B8); -CHECKREG(r2, 0x00000003); -//CHECKREG(r3, 0x000002B8); -CHECKREG(r4, 0x00000007); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -// RAISE 8; // RTI -// r0 = [p2++]; - R1 = [ P1 ]; -IF !CC JUMP LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -CSYNC; -CHECKREG(r0, 0x55552345); -//CHECKREG(r1, 0x000002B8); -// RAISE 9; // RTI - P3 = R6; - R7 = P3; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" -DATA: -// .space (0x10); -.dd 0x00010203 -.dd 0x04050607 -.dd 0x08090A0B -.dd 0x0C0D0E0F -.dd 0x10111213 -.dd 0x14151617 -.dd 0x18191A1B -.dd 0x1C1D1E1F -.dd 0x11223344 -.dd 0x55667788 -.dd 0x99717273 -.dd 0x74757677 -.dd 0x82838485 -.dd 0x86878889 -.dd 0x80818283 -.dd 0x84858687 -.dd 0x01020304 -.dd 0x05060708 -.dd 0x09101112 -.dd 0x14151617 -.dd 0x18192021 - - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: - -.section MEM_DATA_ADDR_2,"aw" -.dd 0x20212223 -.dd 0x24252627 -.dd 0x28292A2B -.dd 0x2C2D2E2F -.dd 0x30313233 -.dd 0x34353637 -.dd 0x38393A3B -.dd 0x3C3D3E3F -.dd 0x91929394 -.dd 0x95969798 -.dd 0x99A1A2A3 -.dd 0xA5A6A7A8 -.dd 0xA9B0B1B2 -.dd 0xB3B4B5B6 -.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S b/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S deleted file mode 100644 index 1b0d7b5..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S +++ /dev/null @@ -1,442 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmr_mvp/c_seq_ex3_ls_mmr_mvp.dsp -// Spec Reference: sequencer stage ex3 (ldst + mmr regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** -R0 = 0; -ASTAT = R0; - // PUT YOUR TEST HERE! -// PUSH -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -//LD32(p2, DATA_ADDR_1); -loadsym p2, DATA; -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - -LD32(r2, 0x14789232); - [ P1 ] = R2; - - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - - [ -- SP ] = ( R7:0 ); -// RAISE 2; // RTN - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -// brf LABEL1 (bp); - - P3 = R7; - R4 = P3; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -// RAISE 5; // RTI - R2 = [ P2 ++ ]; - R3 = [ P1 ]; -// brt LABEL2 (bp); // not taken - - P4 = R6; - R4 = P4; - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -// RAISE 6; // RTI - R4 = [ P2 ++ ]; - R5 = [ P1 ]; -// brf LABEL2 (bp) ; - P3 = R3; - R6 = P3; - [ -- SP ] = ( R7:0 ); -// POP -// r0 = 0x00; -// r1 = 0x00; -// r2 = 0x00; -// r3 = 0x00; -// r4 = 0x00; -// r5 = 0x00; -// r6 = 0x00; -// r7 = 0x00; - -LABEL2: -CSYNC; -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x00000012); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x00000016); -CHECKREG(r5, 0x14789232); -// RAISE 7; // RTI - R0 = [ P2 ++ ]; - R1 = [ P1 ]; - P4 = R4; - R2 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x00000012); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x00000016); -CHECKREG(r5, 0x14789232); -CHECKREG(r6, 0x00000024); -CHECKREG(r7, 0x00000028); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -// RAISE 8; // RTI - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -// brf LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -CHECKREG(r0, 0x00010203); // CHECKREG can not be skipped -CHECKREG(r1, 0x00000012); // so they cannot appear here -CHECKREG(r2, 0x04050607); -CHECKREG(r3, 0x14789232); -CHECKREG(r4, 0x00000017); -CHECKREG(r5, 0x00000016); -CHECKREG(r6, 0x00000017); -CHECKREG(r7, 0x00000018); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -CSYNC; -CHECKREG(r0, 0x0000000C); -CHECKREG(r1, 0x0000000D); -// RAISE 9; // RTI - P3 = R6; - R7 = P3; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000008); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" -DATA: -// .space (0x10); -.dd 0x00010203 -.dd 0x04050607 -.dd 0x08090A0B -.dd 0x0C0D0E0F -.dd 0x10111213 -.dd 0x14151617 -.dd 0x18191A1B -.dd 0x1C1D1E1F -.dd 0x11223344 -.dd 0x55667788 -.dd 0x99717273 -.dd 0x74757677 -.dd 0x82838485 -.dd 0x86878889 -.dd 0x80818283 -.dd 0x84858687 -.dd 0x01020304 -.dd 0x05060708 -.dd 0x09101112 -.dd 0x14151617 -.dd 0x18192021 - - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: - -.section MEM_DATA_ADDR_2,"aw" -.dd 0x20212223 -.dd 0x24252627 -.dd 0x28292A2B -.dd 0x2C2D2E2F -.dd 0x30313233 -.dd 0x34353637 -.dd 0x38393A3B -.dd 0x3C3D3E3F -.dd 0x91929394 -.dd 0x95969798 -.dd 0x99A1A2A3 -.dd 0xA5A6A7A8 -.dd 0xA9B0B1B2 -.dd 0xB3B4B5B6 -.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S deleted file mode 100644 index 96543f4..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S +++ /dev/null @@ -1,443 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmrj_mvp/c_seq_ex3_ls_mmrj_mvp.dsp -// Spec Reference: sequencer stage ex3 (ldst + mmr + jump+ regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -//LD32(p2, DATA_ADDR_1); -loadsym p2, DATA; -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - -LD32(r2, 0x14789232); - [ P1 ] = R2; -CSYNC; - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - - - [ -- SP ] = ( R7:0 ); -// RAISE 2; // RTN - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL1; - P3 = R7; - R4 = P3; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -// RAISE 5; // RTI - R2 = [ P2 ++ ]; - - P4 = R6; - R3 = P4; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -RAISE 6; // RTI - R4 = [ P2 ++ ]; - R5 = [ P1 ]; -JUMP.S LABEL2; - P3 = R3; - R6 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -CSYNC; -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x08090A0B); -CHECKREG(r5, 0x14789232); -CHECKREG(r6, 0x00000027); -// RAISE 7; // RTI - R0 = [ P2 ++ ]; - R1 = [ P1 ]; - P4 = R4; - R2 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x04050607); -CHECKREG(r3, 0x00000007); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -// RAISE 8; // RTI - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -CSYNC; -CHECKREG(r0, 0x10111213); -CHECKREG(r1, 0x14789232); -// RAISE 9; // RTI - P3 = R6; - R7 = P3; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" -DATA: -// .space (0x10); -.dd 0x00010203 -.dd 0x04050607 -.dd 0x08090A0B -.dd 0x0C0D0E0F -.dd 0x10111213 -.dd 0x14151617 -.dd 0x18191A1B -.dd 0x1C1D1E1F -.dd 0x11223344 -.dd 0x55667788 -.dd 0x99717273 -.dd 0x74757677 -.dd 0x82838485 -.dd 0x86878889 -.dd 0x80818283 -.dd 0x84858687 -.dd 0x01020304 -.dd 0x05060708 -.dd 0x09101112 -.dd 0x14151617 -.dd 0x18192021 - - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: - -.section MEM_DATA_ADDR_2,"aw" -.dd 0x20212223 -.dd 0x24252627 -.dd 0x28292A2B -.dd 0x2C2D2E2F -.dd 0x30313233 -.dd 0x34353637 -.dd 0x38393A3B -.dd 0x3C3D3E3F -.dd 0x91929394 -.dd 0x95969798 -.dd 0x99A1A2A3 -.dd 0xA5A6A7A8 -.dd 0xA9B0B1B2 -.dd 0xB3B4B5B6 -.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S deleted file mode 100644 index 35abb66..0000000 --- a/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S +++ /dev/null @@ -1,442 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_ex3_raise_ls_mmrj_mvp/c_seq_ex3_raise_ls_mmrj_mvp.dsp -// Spec Reference: sequencer stage ex3 (raise+ ldst + mmr + jump+ regmv + pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -//LD32(p2, DATA_ADDR_1); -loadsym p2, DATA; -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - -LD32(r2, 0x14789232); - [ P1 ] = R2; -CSYNC; - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - - [ -- SP ] = ( R7:0 ); -RAISE 2; // RTN - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL1; - P3 = R7; - R4 = P3; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -RAISE 5; // RTI - R2 = [ P2 ++ ]; - - P4 = R6; - R3 = P4; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -RAISE 6; // RTI - R4 = [ P2 ++ ]; - R5 = [ P1 ]; -JUMP.S LABEL2; - P3 = R3; - R6 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -CSYNC; -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x08090A0B); -CHECKREG(r5, 0x14789232); -CHECKREG(r6, 0x00000027); -RAISE 7; // RTI - R0 = [ P2 ++ ]; - R1 = [ P1 ]; - P4 = R4; - R2 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x04050607); -CHECKREG(r3, 0x00000007); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -RAISE 8; // RTI - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -CSYNC; -CHECKREG(r0, 0x10111213); -CHECKREG(r1, 0x14789232); -RAISE 9; // RTI - P3 = R6; - R7 = P3; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000006); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000002); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" -DATA: -// .space (0x10); -.dd 0x00010203 -.dd 0x04050607 -.dd 0x08090A0B -.dd 0x0C0D0E0F -.dd 0x10111213 -.dd 0x14151617 -.dd 0x18191A1B -.dd 0x1C1D1E1F -.dd 0x11223344 -.dd 0x55667788 -.dd 0x99717273 -.dd 0x74757677 -.dd 0x82838485 -.dd 0x86878889 -.dd 0x80818283 -.dd 0x84858687 -.dd 0x01020304 -.dd 0x05060708 -.dd 0x09101112 -.dd 0x14151617 -.dd 0x18192021 - - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: - -.section MEM_DATA_ADDR_2,"aw" -.dd 0x20212223 -.dd 0x24252627 -.dd 0x28292A2B -.dd 0x2C2D2E2F -.dd 0x30313233 -.dd 0x34353637 -.dd 0x38393A3B -.dd 0x3C3D3E3F -.dd 0x91929394 -.dd 0x95969798 -.dd 0x99A1A2A3 -.dd 0xA5A6A7A8 -.dd 0xA9B0B1B2 -.dd 0xB3B4B5B6 -.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S deleted file mode 100644 index bf2a33f..0000000 --- a/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S +++ /dev/null @@ -1,446 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_wb_cs_lsmmrj_mvp/c_seq_wb_cs_lsmmrj_mvp.dsp -// Spec Reference: sequencer:wb ( csync ldst mmr jump regmv pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -//LD32(p2, DATA_ADDR_1); -loadsym P2, DATA; -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - -LD32(r2, 0x14789232); - [ P1 ] = R2; - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - [ -- SP ] = ( R7:0 ); -// RAISE 2; // RTN -CSYNC; - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL1; - P3 = R7; - R4 = P3; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -// RAISE 5; // RTI -CSYNC; - R2 = [ P2 ++ ]; - - P4 = R6; - R3 = P4; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -// RAISE 6; // RTI -CSYNC; - R4 = [ P2 ++ ]; - R6 = [ P1 ]; -JUMP.S LABEL2; - P3 = R3; - R5 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -CSYNC; -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x08090A0B); -CHECKREG(r5, 0x00000026); -CHECKREG(r6, 0x14789232); -// RAISE 7; // RTI -CSYNC; - R0 = [ P2 ++ ]; - R1 = [ P1 ]; - P4 = R4; - R2 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x04050607); -CHECKREG(r3, 0x00000007); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -// RAISE 8; // RTI -CSYNC; - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -CSYNC; -CHECKREG(r0, 0x10111213); -CHECKREG(r1, 0x14789232); -// RAISE 9; // RTI -CSYNC; - P3 = R6; - R7 = P3; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000000); -CHECKREG(r1, 0x00000000); -CHECKREG(r2, 0x00000000); -CHECKREG(r3, 0x00000000); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" -DATA: -// .space (0x10); -.dd 0x00010203 -.dd 0x04050607 -.dd 0x08090A0B -.dd 0x0C0D0E0F -.dd 0x10111213 -.dd 0x14151617 -.dd 0x18191A1B -.dd 0x1C1D1E1F -.dd 0x11223344 -.dd 0x55667788 -.dd 0x99717273 -.dd 0x74757677 -.dd 0x82838485 -.dd 0x86878889 -.dd 0x80818283 -.dd 0x84858687 -.dd 0x01020304 -.dd 0x05060708 -.dd 0x09101112 -.dd 0x14151617 -.dd 0x18192021 - - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: - -.section MEM_DATA_ADDR_2,"aw" -.dd 0x20212223 -.dd 0x24252627 -.dd 0x28292A2B -.dd 0x2C2D2E2F -.dd 0x30313233 -.dd 0x34353637 -.dd 0x38393A3B -.dd 0x3C3D3E3F -.dd 0x91929394 -.dd 0x95969798 -.dd 0x99A1A2A3 -.dd 0xA5A6A7A8 -.dd 0xA9B0B1B2 -.dd 0xB3B4B5B6 -.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S deleted file mode 100644 index cbcf9ed..0000000 --- a/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S +++ /dev/null @@ -1,446 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_wb_raisecs_lsmmrj_mvp/c_seq_wb_raisecs_lsmmrj_mvp.dsp -// Spec Reference: sequencer:wb (raise csync ldst mmr jump regmv pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -//LD32(p2, DATA_ADDR_1); -loadsym P2, DATA; -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - -LD32(r2, 0x14789232); - [ P1 ] = R2; - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - [ -- SP ] = ( R7:0 ); -RAISE 2; // RTN -CSYNC; - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL1; - P3 = R7; - R4 = P3; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -RAISE 5; // RTI -CSYNC; - R2 = [ P2 ++ ]; - - P4 = R6; - R3 = P4; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -RAISE 6; // RTI -CSYNC; - R4 = [ P2 ++ ]; - R6 = [ P1 ]; -JUMP.S LABEL2; - P3 = R3; - R5 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -CSYNC; -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x08090A0B); -CHECKREG(r5, 0x00000026); -CHECKREG(r6, 0x14789232); -RAISE 7; // RTI -CSYNC; - R0 = [ P2 ++ ]; - R1 = [ P1 ]; - P4 = R4; - R2 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x04050607); -CHECKREG(r3, 0x00000007); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -RAISE 8; // RTI -CSYNC; - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -CSYNC; -CHECKREG(r0, 0x10111213); -CHECKREG(r1, 0x14789232); -RAISE 9; // RTI -CSYNC; - P3 = R6; - R7 = P3; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000006); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000002); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" -DATA: -// .space (0x10); -.dd 0x00010203 -.dd 0x04050607 -.dd 0x08090A0B -.dd 0x0C0D0E0F -.dd 0x10111213 -.dd 0x14151617 -.dd 0x18191A1B -.dd 0x1C1D1E1F -.dd 0x11223344 -.dd 0x55667788 -.dd 0x99717273 -.dd 0x74757677 -.dd 0x82838485 -.dd 0x86878889 -.dd 0x80818283 -.dd 0x84858687 -.dd 0x01020304 -.dd 0x05060708 -.dd 0x09101112 -.dd 0x14151617 -.dd 0x18192021 - - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: - -.section MEM_DATA_ADDR_2,"aw" -.dd 0x20212223 -.dd 0x24252627 -.dd 0x28292A2B -.dd 0x2C2D2E2F -.dd 0x30313233 -.dd 0x34353637 -.dd 0x38393A3B -.dd 0x3C3D3E3F -.dd 0x91929394 -.dd 0x95969798 -.dd 0x99A1A2A3 -.dd 0xA5A6A7A8 -.dd 0xA9B0B1B2 -.dd 0xB3B4B5B6 -.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S deleted file mode 100644 index 4b97bee..0000000 --- a/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S +++ /dev/null @@ -1,455 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_wb_rti_lsmmrj_mvp/c_seq_wb_rti_lsmmrj_mvp.dsp -// Spec Reference: sequencer:wb ( rti ldst mmr jump regmv pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -//LD32(p2, DATA_ADDR_1); -loadsym P2, DATA; -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - -LD32(r2, 0x14789232); - [ P1 ] = R2; - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - [ -- SP ] = ( R7:0 ); -RAISE 2; // RTN - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL1; - P3 = R7; - R4 = P3; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -RAISE 5; // RTI - R2 = [ P2 ++ ]; - - P4 = R6; - R3 = P4; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -RAISE 6; // RTI - R4 = [ P2 ++ ]; - R6 = [ P1 ]; -JUMP.S LABEL2; - P3 = R3; - R5 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -CSYNC; -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x08090A0B); -CHECKREG(r5, 0x00000026); -CHECKREG(r6, 0x14789232); -RAISE 7; // RTI - R0 = [ P2 ++ ]; - R1 = [ P1 ]; - P4 = R4; - R2 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x04050607); -CHECKREG(r3, 0x00000007); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -RAISE 8; // RTI - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -CSYNC; -CHECKREG(r0, 0x10111213); -CHECKREG(r1, 0x14789232); -RAISE 9; // RTI - P3 = R6; - R7 = P3; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000006); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000002); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; - // *********** - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; - // *********** -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - // *********** - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; - // *********** - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" -DATA: -// .space (0x10); -.dd 0x00010203 -.dd 0x04050607 -.dd 0x08090A0B -.dd 0x0C0D0E0F -.dd 0x10111213 -.dd 0x14151617 -.dd 0x18191A1B -.dd 0x1C1D1E1F -.dd 0x11223344 -.dd 0x55667788 -.dd 0x99717273 -.dd 0x74757677 -.dd 0x82838485 -.dd 0x86878889 -.dd 0x80818283 -.dd 0x84858687 -.dd 0x01020304 -.dd 0x05060708 -.dd 0x09101112 -.dd 0x14151617 -.dd 0x18192021 - - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: - -.section MEM_DATA_ADDR_2,"aw" -.dd 0x20212223 -.dd 0x24252627 -.dd 0x28292A2B -.dd 0x2C2D2E2F -.dd 0x30313233 -.dd 0x34353637 -.dd 0x38393A3B -.dd 0x3C3D3E3F -.dd 0x91929394 -.dd 0x95969798 -.dd 0x99A1A2A3 -.dd 0xA5A6A7A8 -.dd 0xA9B0B1B2 -.dd 0xB3B4B5B6 -.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S deleted file mode 100644 index b18a52f..0000000 --- a/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S +++ /dev/null @@ -1,447 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_wb_rtn_lsmmrj_mvp/c_seq_wb_rtn_lsmmrj_mvp.dsp -// Spec Reference: sequencer:wb ( rtn ldst mmr jump regmv pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -//LD32(p2, DATA_ADDR_1); -loadsym P2, DATA; -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - -LD32(r2, 0x14789232); - [ P1 ] = R2; - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - [ -- SP ] = ( R7:0 ); -RAISE 2; // RTN - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL1; - P3 = R7; - R4 = P3; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -RAISE 5; // RTI - R2 = [ P2 ++ ]; - - P4 = R6; - R3 = P4; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -RAISE 6; // RTI - R4 = [ P2 ++ ]; - R6 = [ P1 ]; -JUMP.S LABEL2; - P3 = R3; - R5 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -CSYNC; -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x00000023); -CHECKREG(r3, 0x00000024); -CHECKREG(r4, 0x08090A0B); -CHECKREG(r5, 0x00000026); -CHECKREG(r6, 0x14789232); -RAISE 7; // RTI - R0 = [ P2 ++ ]; - R1 = [ P1 ]; - P4 = R4; - R2 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x04050607); -CHECKREG(r3, 0x00000007); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -RAISE 8; // RTI - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -CSYNC; -CHECKREG(r0, 0x10111213); -CHECKREG(r1, 0x14789232); -RAISE 9; // RTI - P3 = R6; - R7 = P3; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000006); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000002); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - // *********** - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; - // *********** - -XHANDLE: // Exception Handler 3 - R1 = 3; -RTX; - -HWHANDLE: // HW Error Handler 5 - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler - I3 += 2; -RTI; -I8HANDLE: // IVG 8 Handler - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" -DATA: -// .space (0x10); -.dd 0x00010203 -.dd 0x04050607 -.dd 0x08090A0B -.dd 0x0C0D0E0F -.dd 0x10111213 -.dd 0x14151617 -.dd 0x18191A1B -.dd 0x1C1D1E1F -.dd 0x11223344 -.dd 0x55667788 -.dd 0x99717273 -.dd 0x74757677 -.dd 0x82838485 -.dd 0x86878889 -.dd 0x80818283 -.dd 0x84858687 -.dd 0x01020304 -.dd 0x05060708 -.dd 0x09101112 -.dd 0x14151617 -.dd 0x18192021 - - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: - -.section MEM_DATA_ADDR_2,"aw" -.dd 0x20212223 -.dd 0x24252627 -.dd 0x28292A2B -.dd 0x2C2D2E2F -.dd 0x30313233 -.dd 0x34353637 -.dd 0x38393A3B -.dd 0x3C3D3E3F -.dd 0x91929394 -.dd 0x95969798 -.dd 0x99A1A2A3 -.dd 0xA5A6A7A8 -.dd 0xA9B0B1B2 -.dd 0xB3B4B5B6 -.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S deleted file mode 100644 index 52eb6c8..0000000 --- a/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S +++ /dev/null @@ -1,466 +0,0 @@ -//Original:/proj/frio/dv/testcases/core/c_seq_wb_rtx_lsmmrj_mvp/c_seq_wb_rtx_lsmmrj_mvp.dsp -// Spec Reference: sequencer:wb ( rtx ldst mmr jump regmv pushpopmultiple) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(selfcheck.inc) -include(gen_int.inc) -INIT_R_REGS(0); -INIT_P_REGS(0); -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); -//CHECK_INIT(p5, 0xe0000000); -include(symtable.inc) -CHECK_INIT_DEF(p5); - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE DATA_ADDR_1 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// - -BOOT: - - // in reset mode now -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in - // SUPERVISOR MODE & go to different RAISE in supervisor mode - // until the end of the test. - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - - - // PUT YOUR TEST HERE! -// PUSH -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -//LD32(p2, DATA_ADDR_1); -loadsym P2, DATA; -LD32(p3, 0xab5fd490); -LD32(p4, 0xa581bd94); - -LD32(r2, 0x14789232); - [ P1 ] = R2; - R0 = 0x01; - R1 = 0x02; - R2 = 0x03; - R3 = 0x04; - R4 = 0x05; - R5 = 0x06; - R6 = 0x07; - R7 = 0x08; - [ -- SP ] = ( R7:0 ); -RAISE 2; // RTN - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL1; - P3 = R7; - R4 = P3; - [ -- SP ] = ( R7:0 ); - R1 = 0x12; - R2 = 0x13; - R3 = 0x14; - R4 = 0x15; - R5 = 0x16; - R6 = 0x17; - R7 = 0x18; - -LABEL1: -RAISE 5; // RTI - R2 = [ P2 ++ ]; - - P4 = R6; - R3 = P4; - - [ -- SP ] = ( R7:0 ); - - R2 = 0x23; - R3 = 0x24; - R4 = 0x25; - R5 = 0x26; - R6 = 0x27; - R7 = 0x28; - -// wrt-rd EVT5 = 0xFFE02034 -LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 -RAISE 6; // RTI - R4 = [ P2 ++ ]; - R6 = [ P1 ]; -JUMP.S LABEL2; - P3 = R3; - R5 = P3; - [ -- SP ] = ( R7:0 ); -// POP - R0 = 0x00; - R1 = 0x00; - R2 = 0x00; - R3 = 0x00; - R4 = 0x00; - R5 = 0x00; - R6 = 0x00; - R7 = 0x00; - -LABEL2: -CSYNC; -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789234); -CHECKREG(r2, 0x00000024); -CHECKREG(r3, 0x00000025); -CHECKREG(r4, 0x08090A0B); -CHECKREG(r5, 0x00000027); -CHECKREG(r6, 0x14789232); -RAISE 7; // RTI - R0 = [ P2 ++ ]; - R1 = [ P1 ]; - P4 = R4; - R2 = P4; - ( R7:0 ) = [ SP ++ ]; - - - -CHECKREG(r0, 0x00010203); -CHECKREG(r1, 0x14789233); -CHECKREG(r2, 0x04050607); -CHECKREG(r3, 0x00000008); -//CHECKREG(r4, 0x000002CC); -CHECKREG(r5, 0x00000007); -CHECKREG(r6, 0x00000008); -CHECKREG(r7, 0x00000009); -// wrt-rd EVT13 = 0xFFE02034 -LD32(p1, 0xFFE02034); -RAISE 8; // RTI - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; -//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped -//CHECKREG(r1, 0x000000b2); // so they cannot appear here -//CHECKREG(r2, 0x000000c3); -//CHECKREG(r3, 0x000000d4); -//CHECKREG(r4, 0x000000e5); -//CHECKREG(r5, 0x000000f6); -//CHECKREG(r6, 0x00000017); -//CHECKREG(r7, 0x00000028); - R0 = 12; - R1 = 13; - R2 = 14; - R3 = 15; - R4 = 16; - R5 = 17; - R6 = 18; - R7 = 19; - - -LABEL3: -CSYNC; -CHECKREG(r0, 0x10111213); -CHECKREG(r1, 0x14789232); -CHECKREG(r2, 0x04050608); -CHECKREG(r3, 0x00000009); -//CHECKREG(r4, 0x000002E4); -CHECKREG(r5, 0x00000008); -CHECKREG(r6, 0x00000009); -CHECKREG(r7, 0x0000000A); -RAISE 9; // RTI - P3 = R6; - R7 = P3; - ( R7:0 ) = [ SP ++ ]; - -CHECKREG(r0, 0x00000001); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000003); -CHECKREG(r3, 0x00000004); -CHECKREG(r4, 0x00000005); -CHECKREG(r5, 0x00000006); -CHECKREG(r6, 0x00000007); -CHECKREG(r7, 0x00000008); -R0 = I0; -R1 = I1; -R2 = I2; -R3 = I3; -CHECKREG(r0, 0x00000006); -CHECKREG(r1, 0x00000002); -CHECKREG(r2, 0x00000002); -CHECKREG(r3, 0x00000002); - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - I0 += 2; -RTN; - -XHANDLE: // Exception Handler 3 -R4 = RETX; // error handler: RETX has the address of the same Illegal instr - R1 += 1; - R2 += 1; - R3 += 1; - R5 += 1; - R6 += 1; - R7 += 1; -R4 += 4; // we have to add 4 to point to next instr after return -RETX = R4; -RTX; - // *********** - R0 = [ P2 ++ ]; - R1 = [ P1 ]; -JUMP.S LABEL3; - P1 = R5; - R6 = P1; - ( R7:0 ) = [ SP ++ ]; - // *********** - -HWHANDLE: // HW Error Handler 5 -.dd 0xFFFFFFFF - I1 += 2; -RTI; - -THANDLE: // Timer Handler 6 -.dd 0xFFFFFFFF - I2 += 2; -RTI; - -I7HANDLE: // IVG 7 Handler -.dd 0xFFFFFFFF - I3 += 2; -RTI; -I8HANDLE: // IVG 8 Handler -.dd 0xFFFFFFFF - I0 += 2; -RTI; - -I9HANDLE: // IVG 9 Handler -.dd 0xFFFFFFFF - I0 += 2; -RTI; - -I10HANDLE: // IVG 10 Handler - R7 = 10; -RTI; - -I11HANDLE: // IVG 11 Handler - I0 = R0; - I1 = R1; - I2 = R2; - I3 = R3; - M0 = R4; - R0 = 11; -RTI; - -I12HANDLE: // IVG 12 Handler - R1 = 12; -RTI; - -I13HANDLE: // IVG 13 Handler - R2 = 13; -RTI; - -I14HANDLE: // IVG 14 Handler - R3 = 14; -RTI; - -I15HANDLE: // IVG 15 Handler - R4 = 15; -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1,"aw" -DATA: -// .space (0x10); -.dd 0x00010203 -.dd 0x04050607 -.dd 0x08090A0B -.dd 0x0C0D0E0F -.dd 0x10111213 -.dd 0x14151617 -.dd 0x18191A1B -.dd 0x1C1D1E1F -.dd 0x11223344 -.dd 0x55667788 -.dd 0x99717273 -.dd 0x74757677 -.dd 0x82838485 -.dd 0x86878889 -.dd 0x80818283 -.dd 0x84858687 -.dd 0x01020304 -.dd 0x05060708 -.dd 0x09101112 -.dd 0x14151617 -.dd 0x18192021 - - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: - -.section MEM_DATA_ADDR_2,"aw" -.dd 0x20212223 -.dd 0x24252627 -.dd 0x28292A2B -.dd 0x2C2D2E2F -.dd 0x30313233 -.dd 0x34353637 -.dd 0x38393A3B -.dd 0x3C3D3E3F -.dd 0x91929394 -.dd 0x95969798 -.dd 0x99A1A2A3 -.dd 0xA5A6A7A8 -.dd 0xA9B0B1B2 -.dd 0xB3B4B5B6 -.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_ujump.s b/sim/testsuite/sim/bfin/c_ujump.s deleted file mode 100644 index 65dcf5e..0000000 --- a/sim/testsuite/sim/bfin/c_ujump.s +++ /dev/null @@ -1,52 +0,0 @@ -//Original:/testcases/core/c_ujump/c_ujump.dsp -// Spec Reference: ujump -# mach: bfin - -.include "testutils.inc" - start - - -INIT_R_REGS 0; - -ASTAT = r0; - -JUMP.S LAB1; - - -STOP: -JUMP.S END; - -LAB1: - R1 = 0x1111 (X); -JUMP.S LAB5; - R6 = 0x6666 (X); - -LAB2: - R2 = 0x2222 (X); -JUMP.S STOP; - -LAB3: - R3 = 0x3333 (X); -JUMP.S LAB2; - R7 = 0x7777 (X); - -LAB4: - R4 = 0x4444 (X); -JUMP.S LAB3; - -LAB5: - R5 = 0x5555 (X); -JUMP.S LAB4; - -END: - -CHECKREG r0, 0x00000000; -CHECKREG r1, 0x00001111; -CHECKREG r2, 0x00002222; -CHECKREG r3, 0x00003333; -CHECKREG r4, 0x00004444; -CHECKREG r5, 0x00005555; -CHECKREG r6, 0x00000000; -CHECKREG r7, 0x00000000; - -pass diff --git a/sim/testsuite/sim/bfin/cc-alu.S b/sim/testsuite/sim/bfin/cc-alu.S deleted file mode 100644 index 089fbe7..0000000 --- a/sim/testsuite/sim/bfin/cc-alu.S +++ /dev/null @@ -1,126 +0,0 @@ -# Blackfin testcase for CC/A0/A1 compares -# mach: bfin - -#include "test.h" - .include "testutils.inc" - - start - -/* Clear ASTAT before test */ -#define CHECK_ASTAT(op, exp) ASTAT = R2; CC = A0 op A1; check_astat exp - .macro check_astat exp:req - R5 = ASTAT; - R6 = \exp; - CC = R5 == R6; - IF !CC JUMP 1f; - .endm - - .macro _acc_test exp_eq:req, exp_le:req, exp_lt:req - CHECK_ASTAT(==, \exp_eq) - CHECK_ASTAT(<=, \exp_le) - CHECK_ASTAT(<, \exp_lt) - - jump 2f; -1: fail -2: - .endm - - .macro acc_test acc0:req, acc1:req, eq:req, le:req, lt:req - dmm32 A0, \acc0 - dmm32 A1, \acc1 - _acc_test \eq, \le, \lt - .endm - - .macro acc_ex_test a0x:req, a0w:req, a1x:req, a1w:req, eq:req, le:req, lt:req - imm32 R0, \a0w - A0.W = R0; - R0 = \a0x; - A0.X = R0; - imm32 R1, \a1w - A1.W = R1; - R1 = \a1x; - A1.X = R1; - _acc_test \eq, \le, \lt - .endm - - # Keep R2 with a value of 0 - imm32 R2, 0 - -#define _EQ _AC0|_CC|_AC0_COPY|_AZ, _AC0|_CC|_AC0_COPY|_AZ, _AC0| _AC0_COPY|_AZ -#define _POS_GT _AN, _CC| _AN, _CC| _AN -#define _POS_LT _AC0| _AC0_COPY , _AC0| _AC0_COPY , _AC0| _AC0_COPY -#define _NEG_GT _AC0| _AC0_COPY|_AN, _AC0|_CC|_AC0_COPY|_AN, _AC0|_CC|_AC0_COPY|_AN -#define _NEG_LT 0, 0, 0 - - # Simple tests around zero - acc_test 0, 0, _EQ - acc_test 0, 1, _POS_GT - acc_test 0, 10000, _POS_GT - acc_test 1, 0, _POS_LT - acc_test 10000, 0, _POS_LT - acc_test 0, -1, _NEG_LT - acc_test 0, -10000, _NEG_LT - acc_test -1, 0, _NEG_GT - acc_test -10000, 0, _NEG_GT - - # Simple positive-only tests - acc_test 1, 1, _EQ - acc_test 10000, 10000, _EQ - acc_test 1, 2, _POS_GT - acc_test 1, 20000, _POS_GT - acc_test 2, 1, _POS_LT - acc_test 20000, 1, _POS_LT - - # Simple negative-only tests - acc_test -1, -1, _EQ - acc_test -10000, -10000, _EQ - acc_test -1, -2, _POS_LT - acc_test -1, -20000, _POS_LT - acc_test -2, -1, _POS_GT - acc_test -20000, -1, _POS_GT - - # Simple postitive/negative tests - acc_test 1, -1, _NEG_LT - acc_test -1, 1, _NEG_GT - acc_test 1, -10000, _NEG_LT - acc_test -10000, 1, _NEG_GT - acc_test -1, 10000, _NEG_GT - acc_test 10000, -1, _NEG_LT - acc_test -10000, 10000, _NEG_GT - acc_test 10000, -10000, _NEG_LT - - # Max boundary limits -#define MAX_POS 0x7f, 0xffffffff -#define MAX_NEG 0x80, 0x00000000 - acc_ex_test 0, 0, MAX_POS, _POS_GT - acc_ex_test MAX_POS, 0, 0, _POS_LT - acc_ex_test 0, 1, MAX_POS, _POS_GT - acc_ex_test MAX_POS, 0, 1, _POS_LT - acc_ex_test -1, -1, MAX_POS, _NEG_GT - acc_ex_test MAX_POS, -1, -1, _NEG_LT - acc_ex_test MAX_POS, MAX_POS, _EQ - acc_ex_test 0, 0, MAX_POS, _POS_GT - acc_ex_test MAX_POS, 0, 0, _POS_LT - acc_ex_test 0, 1, MAX_POS, _POS_GT - acc_ex_test MAX_POS, 0, 1, _POS_LT - acc_ex_test -1, -1, MAX_POS, _NEG_GT - acc_ex_test MAX_POS, -1, -1, _NEG_LT - - acc_ex_test 0, 0, MAX_NEG, _NEG_LT - acc_ex_test MAX_NEG, 0, 0, _NEG_GT - acc_ex_test 0, 1, MAX_NEG, _NEG_LT - acc_ex_test MAX_NEG, 0, 1, _NEG_GT - acc_ex_test -1, -1, MAX_NEG, _POS_LT - acc_ex_test MAX_NEG, -1, -1, _POS_GT - acc_ex_test MAX_NEG, MAX_NEG, _EQ - acc_ex_test 0, 0, MAX_NEG, _NEG_LT - acc_ex_test MAX_NEG, 0, 0, _NEG_GT - acc_ex_test 0, 1, MAX_NEG, _NEG_LT - acc_ex_test MAX_NEG, 0, 1, _NEG_GT - acc_ex_test -1, -1, MAX_NEG, _POS_LT - acc_ex_test MAX_NEG, -1, -1, _POS_GT - - acc_ex_test MAX_POS, MAX_NEG, _NEG_LT - acc_ex_test MAX_NEG, MAX_POS, _NEG_GT - - pass diff --git a/sim/testsuite/sim/bfin/cc-astat-bits.s b/sim/testsuite/sim/bfin/cc-astat-bits.s deleted file mode 100644 index 1c7d485..0000000 --- a/sim/testsuite/sim/bfin/cc-astat-bits.s +++ /dev/null @@ -1,101 +0,0 @@ -# Blackfin testcase for setting all ASTAT bits via CC -# mach: bfin - -# We encode the opcodes directly since we test reserved bits -# which lack an insn in the ISA for it. It's a 16bit insn; -# the low 8 bits are always 0x03 while the encoding for the -# high 8 bits are: -# bit 7 - direction -# 0: CC=...; -# 1: ...=CC; -# bit 6/5 - operation -# 0: = assignment -# 1: | bit or -# 2: & bit and -# 3: ^ bit xor -# bit 4-0 - the bit in ASTAT to access - - .include "testutils.inc" - - .macro _do dir:req, op:req, bit:req, bit_in:req, cc_in:req, bg_val:req, bit_out:req, cc_out:req - /* CC = CC; is invalid, so skip it */ - .if \bit != 5 - - /* Calculate the before and after ASTAT values */ - imm32 R1, (\bg_val & ~((1 << \bit) | (1 << 5))) | (\bit_in << \bit) | (\cc_in << 5); - imm32 R3, (\bg_val & ~((1 << \bit) | (1 << 5))) | (\bit_out << \bit) | (\cc_out << 5); - - /* Test the actual opcode */ - ASTAT = R1; - .byte (\dir << 7) | (\op << 5) | \bit - .byte 0x03 - R2 = ASTAT; - - /* Make sure things line up */ - CC = R3 == R2; - IF !CC JUMP 1f; - JUMP 2f; -1: fail -2: - .endif - - /* Recurse through all the bits */ - .if \bit > 0 - _do \dir, \op, \bit - 1, \bit_in, \cc_in, \bg_val, \bit_out, \cc_out - .endif - .endm - - /* Test different background fields on ASTAT */ - .macro do dir:req, op:req, bit_in:req, cc_in:req, bit_out:req, cc_out:req - _do \dir, \op, 31, \bit_in, \cc_in, 0, \bit_out, \cc_out - _do \dir, \op, 31, \bit_in, \cc_in, -1, \bit_out, \cc_out - .endm - - start - nop; - -_cc_eq_bit: /* CC = bit */ - do 0, 0, 0, 0, 0, 0 - do 0, 0, 0, 1, 0, 0 - do 0, 0, 1, 0, 1, 1 - do 0, 0, 1, 1, 1, 1 -_bit_eq_cc: /* bit = CC */ - do 1, 0, 0, 0, 0, 0 - do 1, 0, 0, 1, 1, 1 - do 1, 0, 1, 0, 0, 0 - do 1, 0, 1, 1, 1, 1 - -_cc_or_bit: /* CC |= bit */ - do 0, 1, 0, 0, 0, 0 - do 0, 1, 0, 1, 0, 1 - do 0, 1, 1, 0, 1, 1 - do 0, 1, 1, 1, 1, 1 -_bit_or_cc: /* bit |= CC */ - do 1, 1, 0, 0, 0, 0 - do 1, 1, 0, 1, 1, 1 - do 1, 1, 1, 0, 1, 0 - do 1, 1, 1, 1, 1, 1 - -_cc_and_bit: /* CC &= bit */ - do 0, 2, 0, 0, 0, 0 - do 0, 2, 0, 1, 0, 0 - do 0, 2, 1, 0, 1, 0 - do 0, 2, 1, 1, 1, 1 -_bit_and_cc: /* bit &= CC */ - do 1, 2, 0, 0, 0, 0 - do 1, 2, 0, 1, 0, 1 - do 1, 2, 1, 0, 0, 0 - do 1, 2, 1, 1, 1, 1 - -_cc_xor_bit: /* CC ^= bit */ - do 0, 3, 0, 0, 0, 0 - do 0, 3, 0, 1, 0, 1 - do 0, 3, 1, 0, 1, 1 - do 0, 3, 1, 1, 1, 0 -_bit_xor_cc: /* bit ^= CC */ - do 1, 3, 0, 0, 0, 0 - do 1, 3, 0, 1, 1, 1 - do 1, 3, 1, 0, 1, 0 - do 1, 3, 1, 1, 0, 1 - - pass diff --git a/sim/testsuite/sim/bfin/cc0.s b/sim/testsuite/sim/bfin/cc0.s deleted file mode 100644 index 3fee01e..0000000 --- a/sim/testsuite/sim/bfin/cc0.s +++ /dev/null @@ -1,30 +0,0 @@ -# Blackfin testcase for overflow -# mach: bfin - - .include "testutils.inc" - - start - - # add 0x80000000 + 0x80000000 - R1 = 1; - R1 <<= 31; - R0 = R1; - R0 = R0 + R1; - CC = V; // check to see if av0 and ac get set - CC &= AC0; - IF !CC JUMP art; - R1 = 0; - R1 += 0; - CC = AZ; - IF !CC JUMP art; - pass - -art: - R0 = CC; - R1 = 1 (Z); - - CC = R1 == R0 - if CC jump 1f; - fail -1: - pass diff --git a/sim/testsuite/sim/bfin/cc1.s b/sim/testsuite/sim/bfin/cc1.s deleted file mode 100644 index d5d86d8..0000000 --- a/sim/testsuite/sim/bfin/cc1.s +++ /dev/null @@ -1,26 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - R0 = 0x1234 (X); - CC = BITTST ( R0 , 2 ); - IF !CC JUMP s$0; - R0 += 1; -s$0: - nop; - DBGA ( R0.L , 0x1235 ); - CC = BITTST ( R0 , 1 ); - IF !CC JUMP s$1; - R0 += 1; -s$1: - nop; - DBGA ( R0.L , 0x1235 ); - CC = BITTST ( R0 , 12 ); - IF !CC JUMP s$3; - R0 = - R0; -s$3: - nop; - DBGA ( R0.L , 0xedcb ); - pass diff --git a/sim/testsuite/sim/bfin/cc5.S b/sim/testsuite/sim/bfin/cc5.S deleted file mode 100644 index 593b3bd..0000000 --- a/sim/testsuite/sim/bfin/cc5.S +++ /dev/null @@ -1,90 +0,0 @@ -// ALU test program. -// Test instructions reg = (A0+=A1) - -#include "test.h" -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - loadsym P0, data0; - - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// add accums and transfer result - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R6 = ( A0 += A1 ); - CHECKREG R6, 0x22222222; - R6 = A0.w; - CHECKREG R6, 0x22222222; - R7 = A0.x; - CHECKREG R7, 0; - R6 = A1.w; - CHECKREG R6, 0x11111111; - R7 = A1.x; - CHECKREG R7, 0; - -// add accums and transfer result (saturate positive) - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1.w = R1; - A0.w = R1; - R6 = ( A0 += A1 ); - CHECKREG R6, 0x7fffffff; - R6 = A0.w; - CHECKREG R6, 0xfffffffe; - R7 = A0.x; - CHECKREG R7, 0; - R6 = A1.w; - CHECKREG R6, 0x7fffffff; - _DBG ASTAT; - R7 = A1.x; - _DBG ASTAT; - CHECKREG R7, 0; - R7 = ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY); - -// add accums and transfer result (saturate negative) - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1.w = R2; - A0.w = R2; - A1.x = R3.L; - A0.x = R3.L; - R6 = ( A0 += A1 ); - CHECKREG R6, 0x80000000; - R6 = A0.w; - CHECKREG R6, 0x00000000; - R7 = A0.x; - CHECKREG R6, 0; - R6 = A1.w; - CHECKREG R6, 0x80000000; - R7 = A1.x; - CHECKREG R7, 0xffffffff; - R7 = ASTAT; - _DBG ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); - - pass - - .data -data0: - .dw 0x1111 - .dw 0x1111 - .dw 0xffff - .dw 0x7fff - .dw 0x0000 - .dw 0x8000 - .dw 0x00ff - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/cec-exact-exception.S b/sim/testsuite/sim/bfin/cec-exact-exception.S deleted file mode 100644 index fd22f94..0000000 --- a/sim/testsuite/sim/bfin/cec-exact-exception.S +++ /dev/null @@ -1,54 +0,0 @@ -# Blackfin testcase for aborting an excepting insn immediately -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - - # This test keeps P5 as the base of the EVT table - - .macro set_evt lvl:req, sym:req - loadsym R1, \sym; - [P5 + 4 * \lvl\()] = R1; - .endm - - start - - # Set up exception handler - imm32 P4, EVT3; - loadsym R1, _evx; - [P4] = R1; - - # Lower ourselves to userspace - loadsym R1, _user; - RETI = R1; - RTI; - -_user: - imm32 R0, 0x12345678; - R1 = R0; - imm32 P0, 0xffffffff; - P1 = P0; -_user_fail: - # Sometimes this even causes immediate double faults when - # exceptions are not exact since this may trigger multiple - R0 = [P0++]; - - JUMP fail_lvl; - -_evx: - # RETX should be pointing to the right place - loadsym R6, _user_fail; - R7 = RETX; - CC = R6 == R7; - IF !CC JUMP fail_lvl; - - # R0 and P0 should be unchanged - CC = R1 == R0; - IF !CC JUMP fail_lvl; - CC = P1 == P0; - IF !CC JUMP fail_lvl; - - dbg_pass -fail_lvl: - dbg_fail diff --git a/sim/testsuite/sim/bfin/cec-ifetch.S b/sim/testsuite/sim/bfin/cec-ifetch.S deleted file mode 100644 index 5ed54b5..0000000 --- a/sim/testsuite/sim/bfin/cec-ifetch.S +++ /dev/null @@ -1,69 +0,0 @@ -# Blackfin testcase for making sure RETX is the excepting insn -# and not the target of the insn (like indirect jumps) -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - - start - - # Set our handler - imm32 P5, EVT3; - loadsym R1, _evtx; - [P5] = R1; - - # Lower ourselves below EVT3 - loadsym R4, _i_rts; - RETI = R4; - RAISE 12; - RTI; - -_i_rts: - # Check unaligned RETS - loadsym R6, 1f; - loadsym R5, 2f; - R0 = 1; - RETS = R0; -1: RTS; -2: - -_i_jump: - # Check unaligned indirect jump - loadsym R6, 1f; - loadsym R5, 2f; - P0 = 1; -1: JUMP (P0); -2: - -_i_jump_off: - # Check unaligned indirect jump (pc-relative) - loadsym R6, 1f; - loadsym R5, 2f; - P0 = 1; -1: JUMP (PC + P0); -2: - -_i_call: - # Check unaligned indirect call - loadsym R6, 1f; - loadsym R5, 2f; - P0 = 1; -1: CALL (P0); -2: - -_pass_lvl: - dbg_pass - -_evtx: - # Make sure R6 matches RETX - R7 = RETX; - CC = R6 == R7; - if !CC jump _fail_lvl; - - # Move on to next test - RETX = R5; - RTX; - -_fail_lvl: - dbg_fail diff --git a/sim/testsuite/sim/bfin/cec-multi-pending.S b/sim/testsuite/sim/bfin/cec-multi-pending.S deleted file mode 100644 index 63f3780..0000000 --- a/sim/testsuite/sim/bfin/cec-multi-pending.S +++ /dev/null @@ -1,182 +0,0 @@ -# Blackfin testcase for multiple pending IVGs vs masked state -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - - # This test keeps P5 as the base of the EVT table - - .macro set_evt lvl:req, sym:req - loadsym R1, \sym; - [P5 + 4 * \lvl\()] = R1; - .endm - - .macro check_cec mmr:req, valid:req - imm32 P3, \mmr; - R0 = [P3]; - R1 = ~0x1f; - R0 = R0 & R1; - imm32 R1, \valid; - CC = R1 == R0; - IF CC JUMP 1f; - dbg_fail -1: - .endm - - .macro delay cnt:req - imm32 P2, \cnt - LSETUP (1f, 1f) LC1 = P2; -1: mnop; - .endm - - start - - # First mark all EVTs as fails (they shouldn't be activated) - imm32 P5, EVT0; - P1 = P5; - loadsym R1, fail_lvl - imm32 P2, 16 - LSETUP (1f, 1f) LC0 = P2; -1: [P1++] = R1; - - # Lower ourselves to EVT15 - set_evt 15, evt15; - R7 = 0 (x); - BITSET (R7, 15); - sti R7; - loadsym R1, wait; - RETI = R1; - RAISE 15; - RTI; - -wait: - jump wait; - -evt15: - # We shouldn't come back here - set_evt 15, fail_lvl; - - # Activate interrupt nesting early - [--SP] = RETI; - - # Raise some higher levels, but they should be masked and so - # they should never be activated ... - RAISE 6; - RAISE 5; - RAISE 9; - RAISE 12; - - # Only IVG15 should be pending - check_cec IPEND, (1<<15); - - # But all should be latched - check_cec ILAT, (1<<5) | (1<<6) | (1<<9) | (1<<12); - - # Delay a little in case a higher level wrongly activates - delay 30 - - # If we're still here, things are still good. So let's - # transition up *slightly*, but not to the highest latched. - set_evt 12, evt12; - cli R7; - BITSET (R7, 12); - sti R7; - - # Let CEC raise us to IVG12 - delay 30 - # CEC should have been faster than this ... - dbg_fail - -evt12: - # We shouldn't come back here - set_evt 12, fail_lvl; - - # Raise some higher levels, but they should be masked and so - # they should never be activated ... - RAISE 11; - - # Both IVG15 and IVG12 should be pending - check_cec IPEND, (1<<15) | (1<<12); - - # But all should be latched - check_cec ILAT, (1<<5) | (1<<6) | (1<<9) | (1<<11); - - # Activate interrupt nesting a little later - [--SP] = RETI; - - # Still here, so unmask a higher IVG again to move up - set_evt 9, evt9; - cli R7; - BITSET (R7, 9); - sti R7; - delay 30 - - # CEC should have been faster than this ... - dbg_fail - -evt9: - # We shouldn't come back here - set_evt 9, fail_lvl; - - # IVG9 should also be pending now - check_cec IPEND, (1<<15) | (1<<12) | (1<<9); - - # But all should be latched - check_cec ILAT, (1<<5) | (1<<6) | (1<<11); - - # Unmask the next level, but IPEND[4] is set, so we should stay here - set_evt 6, evt6; - cli R7; - BITSET (R7, 6); - sti R7; - - # Delay a little in case a higher level wrongly activates - delay 30 - - # Good, now unmask things globally - [--SP] = RETI; - delay 30 - - # CEC should have been faster than this ... - dbg_fail - -evt6: - # We shouldn't come back here - set_evt 6, fail_lvl; - - # IVG6 should also be pending now - check_cec IPEND, (1<<15) | (1<<12) | (1<<9) | (1<<6); - - # But all should be latched - check_cec ILAT, (1<<5) | (1<<11); - - # Activate interrupt nesting a little later - [--SP] = RETI; - - # Unmask the next level, but do it via IMASK - set_evt 5, evt5; - imm32 P2, IMASK; - R7 = [P2]; - BITSET (R7, 5); - [P2] = R7; - delay 30 - - # CEC should have been faster than this ... - dbg_fail - -evt5: - # We shouldn't come back here - set_evt 5, fail_lvl; - - # IVG5 should also be pending now - check_cec IPEND, (1<<15) | (1<<12) | (1<<9) | (1<<6) | (1<<5); - - # But all should be latched - check_cec ILAT, (1<<11); - - # All good! - dbg_pass; - -fail_lvl: - dbg_fail; diff --git a/sim/testsuite/sim/bfin/cec-no-snen-reti.S b/sim/testsuite/sim/bfin/cec-no-snen-reti.S deleted file mode 100644 index bb9557d..0000000 --- a/sim/testsuite/sim/bfin/cec-no-snen-reti.S +++ /dev/null @@ -1,128 +0,0 @@ -# Blackfin testcase for having RETI LSB set correctly when not self nested -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - - start - - # Set our handler - imm32 P5, EVT11; - loadsym R1, _ivg11; - [P5] = R1; - loadsym R1, _fail_lvl; - [P5 + 4] = R1; /* IVG12 */ - [P5 + 12] = R1; /* IVG14 */ - loadsym R1, _ivg13; - [P5 + 8] = R1; - - # Disable self nesting - R2 = SYSCFG; - BITCLR (R2, 2); - SYSCFG = R2; - CSYNC; - - # Enable IVG11/IVG13/IVG14 but not IVG12 - cli R3; - BITSET (R3, 11); - BITCLR (R3, 12); - BITSET (R3, 13); - BITSET (R3, 14); - sti R3; - - # Counters to keep track of nesting depth - R7 = 0; - R5 = 0; - - # Lower ourselves to IVG11 - loadsym R4, _fail_lvl; - RETI = R4; - RAISE 11; - RAISE 12; - RAISE 13; - RAISE 14; - RTI; - -# This IVG makes sure we don't re-enter when self RAISE is pending -_ivg11: - R0 = RETI; - - # Make sure we are indeed at IVG11 - imm32 P0, IPEND; - R1 = [P0]; - CC = BITTST (R1, 11); - IF !CC JUMP _fail_lvl; - - # Should not be re-entering - CC = R5 == 0; - IF !CC JUMP _fail_lvl; - - # Make sure LSB of RETI is not set - CC = BITTST (R0, 0); - IF CC JUMP _fail_lvl; - - # Try to avoid nesting a few times - R5 += 1; - R6 = 3; - CC = R7 < R6; - IF !CC JUMP 1f; - [--sp] = RETI; - R7 += 1; - RAISE 11; - MNOP;NOP;MNOP;NOP; - R5 = 0; - RTI; - - # Move down to IVG13 for next test -1: loadsym R4, _fail_lvl; - RETI = R4; - RTI; - -# This IVG makes sure RETI LSB is ignored on transition out (RTI) -_ivg13: - R0 = RETI; - - # Make sure we are indeed at IVG13 - imm32 P0, IPEND; - R1 = [P0]; - CC = BITTST (R1, 13); - IF !CC JUMP _fail_lvl; - - # RETI LSB should not be set when entering IVG13 - CC = BITTST (R0, 0); - IF CC JUMP _fail_lvl; - - # Should get here only after a few IVG11 tests - CC = R7 == R6; - IF !CC JUMP _fail_lvl; - - # Make sure IVG13 isn't pending - imm32 P0, ILAT; - R1 = [P0]; - CC = BITTST (R1, 13); - IF CC JUMP _fail_lvl; - - # Manually set RETI to with LSB set so we should stay at IVG13 - # even though SNEN is disabled - loadsym R1, 1f; - BITSET (R1, 0); - RETI = R1; - R7 += 1; - RTI; - -1: # Make sure we get here in right number of tests - R6 = 4; - CC = R7 == R6; - IF !CC JUMP _fail_lvl; - - # Make sure we are still at IVG13 - imm32 P0, IPEND; - R1 = [P0]; - CC = BITTST (R1, 13); - IF !CC JUMP _fail_lvl; - - dbg_pass - -_fail_lvl: - dbg_fail; diff --git a/sim/testsuite/sim/bfin/cec-non-operating-env.s b/sim/testsuite/sim/bfin/cec-non-operating-env.s deleted file mode 100644 index a35344c..0000000 --- a/sim/testsuite/sim/bfin/cec-non-operating-env.s +++ /dev/null @@ -1,37 +0,0 @@ -# Make sure the sim doesn't segfault when doing things that don't -# make much sense in a non-operating environment -# mach: bfin - - .include "testutils.inc" - - start - - csync; - ssync; - idle; - raise 12; - cli r0; - sti r0; - - loadsym r0, .Lreti; - reti = r0; - rti; - fail; -.Lreti: - - loadsym r0, .Lretx; - retx = r0; - rtx; - fail; -.Lretx: - - loadsym r0, .Lretn; - retn = r0; - rtn; - fail; -.Lretn: - - usp = p0; - p0 = usp; - - pass; diff --git a/sim/testsuite/sim/bfin/cec-raise-reti.S b/sim/testsuite/sim/bfin/cec-raise-reti.S deleted file mode 100644 index 1735ab8..0000000 --- a/sim/testsuite/sim/bfin/cec-raise-reti.S +++ /dev/null @@ -1,111 +0,0 @@ -# Blackfin testcase for having RETI set correctly -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - - # This test keeps P5 as the base of the EVT table - - .macro set_evt lvl:req, sym:req - loadsym R1, \sym; - [P5 + 4 * \lvl\()] = R1; - .endm - - start - - # First mark all EVTs as fails (they shouldn't be activated) - imm32 P5, EVT0; - P1 = P5; - loadsym R1, fail_lvl - imm32 P2, 16 - LSETUP (1f, 1f) LC0 = P2; -1: [P1++] = R1; - - # We'll bounce up a few - set_evt 6, evt6; - set_evt 7, evt7; - set_evt 8, evt8; - set_evt 9, evt9; - - # Lower ourselves down so we can RAISE up - set_evt 14, evt14; - loadsym R1, wait; - RETI = R1; - RAISE 14; - R7 = -1; - sti R7; - RTI; - -wait: - jump wait; - -evt14: - # Activate interrupt nesting early - [--SP] = RETI; - - # We activate the interrupt here ... - loadsym R1, 1f; - RAISE 9; - # ... but we should RETI here -1: JUMP fail_lvl; - -evt9: - R2 = RETI; - CC = R1 == R2; - IF !CC JUMP fail_lvl; - - # We activate the interrupt here ... - loadsym R1, 1f; - RAISE 8; - [--SP] = RETI; - # ... but we should RETI here -1: JUMP fail_lvl; - -evt8: - R2 = RETI; - CC = R1 == R2; - IF !CC JUMP fail_lvl; - - # Activate interrupt nesting early - [--SP] = RETI; - - # We activate the interrupt here ... - loadsym R1, 1f; - cli R7; - RAISE 7; - sti R7; - # ... but we should RETI here -1: JUMP fail_lvl; - -evt7: - R2 = RETI; - CC = R1 == R2; - IF !CC JUMP fail_lvl; - - # Activate interrupt nesting early - [--SP] = RETI; - - # We activate the interrupt here ... - imm32 P0, IMASK - R7 = [P0]; - R6 = 0; - [P0] = R6; - loadsym R1, 1f; - RAISE 6; - [P0] = R7; - # ... but we should RETI here - # don't jump to fail_lvl as the pipeline might advance - # the PC to the fail_lvl point before the ivg actually - # gets a chance to fire -1: JUMP 1b; - -evt6: - R2 = RETI; - CC = R1 == R2; - IF !CC JUMP fail_lvl; - - dbg_pass - -fail_lvl: - dbg_fail; diff --git a/sim/testsuite/sim/bfin/cec-snen-reti.S b/sim/testsuite/sim/bfin/cec-snen-reti.S deleted file mode 100644 index 306d99b..0000000 --- a/sim/testsuite/sim/bfin/cec-snen-reti.S +++ /dev/null @@ -1,122 +0,0 @@ -# Blackfin testcase for having RETI LSB set correctly when self nested -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - - start - - # Set our handler - imm32 P5, EVT11; - loadsym R1, _ivg11; - [P5] = R1; - loadsym R1, _fail_lvl; - [P5 + 4] = R1; /* IVG12 */ - [P5 + 12] = R1; /* IVG14 */ - loadsym R1, _ivg13; - [P5 + 8] = R1; - - # Enable self nesting - R2 = SYSCFG; - BITSET (R2, 2); - SYSCFG = R2; - CSYNC; - - # Enable IVG11/IVG13/IVG14 but not IVG12 - cli R3; - BITSET (R3, 11); - BITCLR (R3, 12); - BITSET (R3, 13); - BITSET (R3, 14); - sti R3; - - # Counter to keep track of nesting depth - R7 = 0; - - # Lower ourselves to IVG11 - loadsym R4, _fail_lvl; - RETI = R4; - RAISE 11; - RAISE 12; - RAISE 13; - RAISE 14; - RTI; - -# This IVG makes sure RETI LSB is set correctly on transition in (RAISE) -_ivg11: - R0 = RETI; - - # Make sure we are indeed at IVG11 - imm32 P0, IPEND; - R1 = [P0]; - CC = BITTST (R1, 11); - IF !CC JUMP _fail_lvl; - - # Make sure LSB of RETI is set only on first pass - CC = ! BITTST (R0, 0); - R1 = CC; - CC = R7 == 0; - R2 = CC; - CC = R1 == R2; - IF !CC JUMP _fail_lvl; - - # Nest ourselves a few times - R6 = 3; - CC = R7 < R6; - IF !CC JUMP 1f; - [--sp] = RETI; - R7 += 1; - RAISE 11; - MNOP; - JUMP _fail_lvl; - - # Move down to IVG13 for next test -1: loadsym R4, _fail_lvl; - RETI = R4; - RTI; - -# This IVG makes sure RETI LSB is respected on transition out (RTI) -_ivg13: - R0 = RETI; - - # Make sure we are indeed at IVG13 - imm32 P0, IPEND; - R1 = [P0]; - CC = BITTST (R1, 13); - IF !CC JUMP _fail_lvl; - - # RETI LSB should be set when re-entering IVG13 - CC = ! BITTST (R0, 0); - R1 = CC; - CC = R7 == R6; - R2 = CC; - CC = R1 == R2; - IF !CC JUMP _fail_lvl; - - # Should get here only after a few IVG11 tests - CC = R7 < R6; - IF CC JUMP _fail_lvl; - - # Make sure IVG13 isn't pending - imm32 P0, ILAT; - R1 = [P0]; - CC = BITTST (R1, 13); - IF CC JUMP _fail_lvl; - - # Manually set RETI to with LSB set so we return there - R5 = R6; - R5 += 3; - CC = R7 < R5; - IF !CC JUMP 1f; - loadsym R1, _ivg13; - BITSET (R1, 0); - RETI = R1; - R7 += 1; - RTI; - - # All done! -1: dbg_pass - -_fail_lvl: - dbg_fail; diff --git a/sim/testsuite/sim/bfin/cec-syscfg-ssstep.S b/sim/testsuite/sim/bfin/cec-syscfg-ssstep.S deleted file mode 100644 index 169a605..0000000 --- a/sim/testsuite/sim/bfin/cec-syscfg-ssstep.S +++ /dev/null @@ -1,72 +0,0 @@ -# Blackfin testcase for hardware single stepping -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - - start - - # Set up exception handler - imm32 P4, EVT3; - loadsym R1, _evx; - [P4] = R1; - - # Enable single stepping - R0 = 1; - SYSCFG = R0; - - # Lower to the code we want to single step through - R1 = 1; - imm32 R5, 0xffff - R6 = 0; - R7 = 0; - loadsym R1, _usr; - RETI = R1; - RTI; - -_usr: - # Single step and set a new bit every time - BITSET (R7, 0); - BITSET (R7, 1); - BITSET (R7, 2); - BITSET (R7, 3); - BITSET (R7, 4); - BITSET (R7, 5); - BITSET (R7, 6); - BITSET (R7, 7); - BITSET (R7, 8); - BITSET (R7, 9); - BITSET (R7, 10); - BITSET (R7, 11); - BITSET (R7, 12); - BITSET (R7, 13); - BITSET (R7, 14); - BITSET (R7, 15); - JUMP fail_lvl; - -_evx: - # Make sure exception reason is single step - R3 = SEQSTAT; - R4 = 0x3f; - R3 = R3 & R4; - R4 = 0x10; - CC = R3 == R4; - IF !CC JUMP fail_lvl; - - # Set a new bit in R6 every single step to match R7 - CC = R1; - R6 = ROT R6 BY 1; - CC = R6 == R7; - IF !CC JUMP fail_lvl; - - # Do it through each bit - CC = R5 == R6; - IF CC JUMP pass_lvl; - - RTX; - -pass_lvl: - dbg_pass; -fail_lvl: - dbg_fail; diff --git a/sim/testsuite/sim/bfin/cec-system-call.S b/sim/testsuite/sim/bfin/cec-system-call.S deleted file mode 100644 index 6aaf3ca..0000000 --- a/sim/testsuite/sim/bfin/cec-system-call.S +++ /dev/null @@ -1,64 +0,0 @@ -# Blackfin testcase for returning to the right place while bouncing between -# multiple CEC levels (like in a Linux system call) -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - - # This test keeps P5 as the base of the EVT table - - .macro set_evt lvl:req, sym:req - loadsym R1, \sym; - [P5 + 4 * \lvl\()] = R1; - .endm - - start - - # First mark all EVTs as fails (they shouldn't be activated) - imm32 P5, EVT0; - P1 = P5; - loadsym R1, fail_lvl - imm32 P2, 16 - LSETUP (1f, 1f) LC0 = P2; -1: [P1++] = R1; - - # The OS exception handler - set_evt 3, _evx; - # The OS system call handler - set_evt 15, _evt15; - - # Lower ourselves to userspace - loadsym R1, _user; - loadsym R2, _next_user; - RETI = R1; - R7 = -1; - sti R7; - RTI; - -_user: - EXCPT 0; -_next_user: - dbg_pass - -_evx: - # RETX should be pointing to the right place - R1 = RETX; - CC = R1 == R2; - IF !CC JUMP fail_lvl; - - # Lower ourselves to the system call handler - RAISE 15; - RTX; - -_evt15: - # RETI should be pointing to the right place - R1 = RETI; - CC = R1 == R2; - IF !CC JUMP fail_lvl; - - # Return to userspace now - RTI; - -fail_lvl: - dbg_fail diff --git a/sim/testsuite/sim/bfin/cir.s b/sim/testsuite/sim/bfin/cir.s deleted file mode 100644 index efbb9d4..0000000 --- a/sim/testsuite/sim/bfin/cir.s +++ /dev/null @@ -1,20 +0,0 @@ -# Blackfin testcase for circular buffer limits -# mach: bfin - - .include "testutils.inc" - - start - - B0 = 0 (X); - I0 = 0x1100 (X); - L0 = 0x10c0 (X); - M0 = 0 (X); - I0 += M0; - R0 = I0; - - R1 = 0x40 (Z); - CC = R1 == R0 - if CC jump 1f; - fail -1: - pass diff --git a/sim/testsuite/sim/bfin/cir1.s b/sim/testsuite/sim/bfin/cir1.s deleted file mode 100644 index 78381ac..0000000 --- a/sim/testsuite/sim/bfin/cir1.s +++ /dev/null @@ -1,84 +0,0 @@ -# Blackfin testcase for circular buffers -# mach: bfin - - .include "testutils.inc" - - .macro daginit i:req, b:req, l:req, m:req - imm32 I0, \i - imm32 B0, \b - imm32 L0, \l - imm32 M0, \m - .endm - .macro dagcheck newi:req - DBGA ( I0.L, \newi & 0xFFFF ); - DBGA ( I0.H, \newi >> 16 ); - .endm - - .macro dagadd i:req, b:req, l:req, m:req, newi:req - daginit \i, \b, \l, \m - I0 += M0; - dagcheck \newi - .endm - - .macro dagsub i:req, b:req, l:req, m:req, newi:req - daginit \i, \b, \l, \m - I0 -= M0; - dagcheck \newi - .endm - - .macro dag i:req, b:req, l:req, m:req, addi:req, subi:req - daginit \i, \b, \l, \m - I0 += M0; - dagcheck \addi - imm32 I0, \i - I0 -= M0; - dagcheck \subi - .endm - - start - - init_l_regs 0 - init_i_regs 0 - init_b_regs 0 - init_m_regs 0 - -_zero_len: - dag 0, 0, 0, 0, 0, 0 - dag 100, 0, 0, 0, 100, 100 - dag 100, 0, 0, 11, 111, 89 - dag 100, 0xaa00ff00, 0, 0, 100, 100 - dag 100, 0xaa00ff00, 0, 11, 111, 89 - -_zero_base: - dag 0, 0, 100, 10, 10, 90 - dag 50, 0, 100, 10, 60, 40 - dag 99, 0, 100, 10, 9, 89 - dag 50, 0, 100, 50, 0, 0 - dag 50, 0, 100, 100, 50, 50 - dag 50, 0, 100, 200, 150, -50 - dag 50, 0, 100, 2100, 2050, -1950 - dag 1000, 0, 100, 0, 900, 1000 - dag 1000, 0, 1000, 0, 0, 1000 - - dag 0xffff1000, 0, 0x1000, 0, 0xffff0000, 0xffff1000 - dag 0xaaaa1000, 0, 0xaaa1000, 0, 0xa0000000, 0xaaaa1000 - dag 0xaaaa1000, 0, 0xaaa1000, 0x1000, 0xa0001000, 0xaaaa0000 - dag 0xffff1000, 0, 0xffff0000, 0xffffff, 0x1000fff, 0xfeff1001 - -_positive_base: - dag 0, 100, 100, 10, 10, 90 - dag 90, 100, 100, 10, 100, 180 - dag 90, 100, 100, 2100, 2090, -1910 - dag 100, 100, 100, 100, 100, 100 - dag 0xfffff000, 0xffffff00, 0x10, 0xffff, 0xefef, 0xfffef011 - -_large_base_len: - dag 0, 0xffffff00, 0xffffff00, 0x00000100, 0x00000200, 0xfffffe00 - dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0x88888887, 0x77777779 - dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0x4ccccccc, 0x91111111, 0x6eeeeeef - dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0x00000000, 0x44444445, 0xbbbbbbbb - dag 0, 0xdddddddd, 0x7bbbbbbb, 0xcccccccc, 0xcccccccc, 0xb7777779 - dag 0, 0xbbbbbbbb, 0x7bbbbbbb, 0x4ccccccc, 0x4ccccccc, 0xb3333334 - dag 0, 0xbbbbbbbb, 0x7bbbbbbb, 0x00000000, 0x84444445, 0x7bbbbbbb - - pass diff --git a/sim/testsuite/sim/bfin/cli-sti.s b/sim/testsuite/sim/bfin/cli-sti.s deleted file mode 100644 index 9e775cb..0000000 --- a/sim/testsuite/sim/bfin/cli-sti.s +++ /dev/null @@ -1,25 +0,0 @@ -# Blackfin testcase for cli/sti instructions -# mach: bfin -# sim: --environment operating - - .include "testutils.inc" - - start - - # Make sure we can't mask <=EVT4 - R0 = 0; - sti R0; - cli R1; - R2 = 0x1f; - CC = R1 == R2; - IF !CC JUMP 1f; - - # Make sure we can mask >=EVT5 - R0 = 0xff; - sti R0; - cli R1; - CC = R0 == R1; - IF !CC JUMP 1f; - - dbg_pass -1: dbg_fail diff --git a/sim/testsuite/sim/bfin/cmpacc.s b/sim/testsuite/sim/bfin/cmpacc.s deleted file mode 100644 index ed31f62..0000000 --- a/sim/testsuite/sim/bfin/cmpacc.s +++ /dev/null @@ -1,50 +0,0 @@ -# Blackfin testcase for the accumulator and compares -# mach: bfin - - .include "testutils.inc" - - start - -r7=0; -astat=r7; -r7.l=0x80; -A1.x=r7.l; -r0 = 0; -A1.w=r0; -r1.l = 0xffff; -r1.h =0xffff; -A0.w=r1; -r7.l=0x7f; -A0.x=r7.l; -#dbg A0; -#dbg A1; -#dbg astat; -cc = A0==A1; -#dbg astat; -r7=astat; -dbga (r7.h, 0x0); -dbga (r7.l, 0x0); -astat=r0; -#dbg astat; -r7.l=0x80; -A0.x=r7.l; -r0 = 0; -A0.w=r0; -r1.l = 0xffff; -r1.h =0xffff; -A1.w=r1; -r7.l=0x7f; -A1.x=r7.l; -cc = A0 G0 -// | | | | -// +------------------------------+ -// | b0 b1 b2 b3 b14 b15 | <- in -// +------------------------------+ -// | | | | | -// ----- XOR------------> G1 -// Instruction BXOR computes the bit G0 or G1 and stores it into CC -// and also into a destination reg half. Here, we take CC and rotate it -// into an output register. -// However, one can also store the output bit directly by storing -// the register half where this bit is placed. This would result -// in an output structure similar to the one in the original function -// Convolutional_Encode(), where an entire half word holds a bit. -// The resulting execution speed would be roughly twice as fast, -// since there is no need to rotate output bit via CC. - -.include "testutils.inc" - start - - loadsym P0, input; - loadsym P1, output; - - R1 = 0; R2 = 0;R3 = 0; - - R2.L = 0; - R2.H = 0xa01d; // polynom 0 - R3.L = 0; - R3.H = 0x12f4; // polynom 1 - - // load and CurrentState to upper half of A0 - A1 = A0 = 0; - R0 = 0x0000; - A0.w = R0; - A0 = A0 << 16; - - // l-loop counter is in P4 - P4 = 2(Z); - // **** START l-LOOP ***** -l$0: - - // insert 16 bits of input into lower half of A0 - // and advance input pointer - R0 = W [ P0 ++ ] (Z); - A0.L = R0.L; - - P5 = 2 (Z); - LSETUP ( m$0 , m$0end ) LC0 = P5; // **** BEGIN m-LOOP ***** -m$0: - - P5 = 8 (Z); - LSETUP ( i$1 , i$1end ) LC1 = P5; // **** BEGIN i-LOOP ***** -i$1: - R4.L = CC = BXORSHIFT( A0 , R2 ); // polynom0 -> CC - R1 = ROT R1 BY 1; // CC -> R1 - R4.L = CC = BXOR( A0 , R3 ); // polynom1 -> CC -i$1end: - R1 = ROT R1 BY 1; // CC -> R1 - - // store 16 bits of outdata RL1 -m$0end: - W [ P1 ++ ] = R1; - - P4 += -1; - CC = P4 == 0; - IF !CC JUMP l$0; // **** END l-LOOP ***** - - // Check results - loadsym I2, output; - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x8c62 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x262e ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5b4d ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x834f ); - pass - - .data -input: - .dw 0x999f - .dw 0x1999 - -output: - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/cycles.s b/sim/testsuite/sim/bfin/cycles.s deleted file mode 100644 index bdea7eb..0000000 --- a/sim/testsuite/sim/bfin/cycles.s +++ /dev/null @@ -1,41 +0,0 @@ -# Blackfin testcase for playing with CYCLES -# mach: bfin - - .include "testutils.inc" - - start - - R0 = 0; - R1 = 1; - CYCLES = R0; - CYCLES2 = R1; - - /* CYCLES should be "small" while CYCLES2 should be R1 still */ - R2 = CYCLES; - CC = R2 <= 3; - if ! CC jump 1f; - - R3 = CYCLES2; - CC = R3 == 1; - if ! CC jump 1f; - - nop; - mnop; - nop; - mnop; - - /* Test the "shadowed" CYCLES2 -- only a read of CYCLES reloads it */ - imm32 R1, 0x12345678 - CYCLES2 = R1; - R2 = CYCLES2; - CC = R2 == R3; - if ! CC jump 1f; - - R2 = CYCLES; - R2 = CYCLES2; - CC = R2 == R1; - if ! CC jump 1f; - - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/d0.s b/sim/testsuite/sim/bfin/d0.s deleted file mode 100644 index 5e13959..0000000 --- a/sim/testsuite/sim/bfin/d0.s +++ /dev/null @@ -1,31 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - I1 = 0x4 (X); - B1 = 0x0 (X); - L1 = 0x10 (X); - M0 = 8 (X); - I1 -= M0; - R0 = I1; - DBGA ( R0.L , 0xc ); - - I1 = 0xf0 (X); - B1 = 0x100 (X); - L1 = 0x10 (X); - M0 = 2 (X); - I1 += M0; - R0 = I1; - DBGA ( R0.L , 0xf2 ); - - I2 = 0x1000 (X); - B2.L = 0; - B2.H = 0x9000; - L2 = 0x10 (X); - M2 = 0 (X); - I2 += M2; - R0 = I2; - DBGA ( R0.L , 0x1000 ); - - pass diff --git a/sim/testsuite/sim/bfin/d1.s b/sim/testsuite/sim/bfin/d1.s deleted file mode 100644 index ea56330..0000000 --- a/sim/testsuite/sim/bfin/d1.s +++ /dev/null @@ -1,17 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - I0 = 0x1100 (X); - L0 = 0x10c0 (X); - M0 = 0 (X); - B0 = 0 (X); - I0 += M0; - R0 = I0; - DBGA ( R0.L , 0x40 ); - - pass diff --git a/sim/testsuite/sim/bfin/d2.s b/sim/testsuite/sim/bfin/d2.s deleted file mode 100644 index 2634f4b..0000000 --- a/sim/testsuite/sim/bfin/d2.s +++ /dev/null @@ -1,56 +0,0 @@ -# Blackfin testcase for circular buffers and BREV -# mach: bfin - - .include "testutils.inc" - - start - - I0 = 0 (X); - M0 = 0x8 (X); - P0 = 16; - loadsym R1, vals; - -aaa: - I0 += M0 (BREV); - P0 += -1; - - R2 = I0; - R0 = R1 + R2 - P1 = R0; - R0 = B[P1] (Z); - - R3 = P0; - - CC = R0 == R3; - if !CC JUMP _fail; - - CC = P0 == 0; - IF !CC JUMP aaa (BP); - R0 = I0; - - DBGA(R0.L, 0x0000); - DBGA(R0.H, 0x0000); - - pass - -_fail: - fail - - .data -vals: -.db 0x0 /* 0 */ -.db 0x8 -.db 0xc -.db 0x4 /* 4 */ -.db 0xe -.db 0x6 -.db 0xa -.db 0x2 /* 8 */ -.db 0xf -.db 0x7 -.db 0xB -.db 0x3 /* c */ -.db 0xD -.db 0x5 -.db 0x9 /* f */ -.db 0x1 diff --git a/sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S b/sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S deleted file mode 100644 index a86ecdc..0000000 --- a/sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S +++ /dev/null @@ -1,545 +0,0 @@ -//Original:/proj/frio/dv/testcases/debug/dbg_brprd_ntkn_src_kill/dbg_brprd_ntkn_src_kill.dsp -// Description: This test checks that the trace buffer keeps track of a -// branch source instruction that is predicted but not taken getting killed -// at each stage in the pipe. The test consists of 8 instances of an EXCPT -// instruction followed by 0 to 7 NOPs and a BRF instruction (and bp), with -// the trace buffer enabled. -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000020 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - - // Save all the registers used in the ISR - [ -- SP ] = R0; - [ -- SP ] = R1; - [ -- SP ] = P0; - [ -- SP ] = P1; - [ -- SP ] = LC0; - [ -- SP ] = LB0; - [ -- SP ] = LT0; - [ -- SP ] = ASTAT; - - // Get EXCAUSE bits out of SEQSTAT - R0 = SEQSTAT; - R0 = R0 << 26; - R0 = R0 >> 26; - - // Check for Trace Exception - // Load r1 with EXCAUSE for Trace Exception - R1 = 0x0011 (Z); - // Check for Trace Exception -CC = R0 == R1; - // Branch to OUT if the EXCAUSE is not TRACE. -IF !CC JUMP OUT; - - // Read out the Trace Buffer. -LD32(p0, TBUFSTAT); - // Read TBUFSTAT MMR - P1 = [ P0 ]; - - // if p1 is zero skip the loop. -CC = P1 == 0; -IF CC JUMP OUT; - - // Read out the Entire Trace Buffer. -LD32(p0, TBUF); -LSETUP ( l0s , l0e ) LC0 = P1; -l0s:R0 = [ P0 ]; -l0e:R0 = [ P0 ]; - -OUT: - // Check for other exception, if any. - - // Restore all saved registers. -ASTAT = [ SP ++ ]; -LT0 = [ SP ++ ]; -LB0 = [ SP ++ ]; -LC0 = [ SP ++ ]; - P1 = [ SP ++ ]; - P0 = [ SP ++ ]; - R1 = [ SP ++ ]; - R0 = [ SP ++ ]; - - // Return -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -WR_MMR(TBUFCTL, 0x7, p0, r0); // Enable trace buffer & overflow - -CSYNC; // Wait for MMR write to complete - -CC = R7 == R6; // Set CC -EXCPT 1; -IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in WB stage -NOP; -NOP; - -EXCPT 2; -NOP; -IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in EX3 stage -NOP; -NOP; - -EXCPT 3; -NOP; -NOP; -IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in EX2 stage -NOP; -NOP; - -EXCPT 4; -NOP; -NOP; -NOP; -IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in EX1 stage -NOP; -NOP; - -EXCPT 5; -NOP; -NOP; -NOP; -NOP; -IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in AC stage -NOP; -NOP; - -EXCPT 6; -NOP; -NOP; -NOP; -NOP; -NOP; -IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in DEC stage -NOP; -NOP; - -EXCPT 7; NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in IF2 stage -NOP; -NOP; - -EXCPT 8; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in IF1 stage -NOP; -NOP; - - // Read out the Rest of the Trace Buffer. -LD32(p0, TBUFSTAT); - // Read TBUFSTAT MMR - P1 = [ P0 ]; - - // if p1 is zero skip the loop. -CC = P1 == 0; -IF CC JUMP OUT1; - - // Read out the Entire Trace Buffer. -LD32(p0, TBUF); -LSETUP ( l1s , l1e ) LC0 = P1; -l1s:R0 = [ P0 ]; -l1e:R0 = [ P0 ]; - - // Don't RTI if you never wish to go to User Mode - // use END_TEST instead. - -OUT1: -dbg_pass; - -// rti; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - - // YOUR USER CODE GOES HERE. - -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; -.dd 0x05050505; -.dd 0x06060606; -.dd 0x07070707; -.dd 0x08080808; -.dd 0x09090909; -.dd 0x0a0a0a0a; -.dd 0x0b0b0b0b; -.dd 0x0c0c0c0c; -.dd 0x0d0d0d0d; -.dd 0x0e0e0e0e; -.dd 0x0f0f0f0f; - -// Define Kernal Stack -.section MEM_DATA_ADDR_2 //.data 0x00F00210,"aw" - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S b/sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S deleted file mode 100644 index 812c8c7..0000000 --- a/sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S +++ /dev/null @@ -1,544 +0,0 @@ -//Original:/proj/frio/dv/testcases/debug/dbg_brtkn_nprd_src_kill/dbg_brtkn_nprd_src_kill.dsp -// Description: This test checks that the trace buffer keeps track of a -// branch source instruction that is taken but not predicted getting killed -// at each stage in the pipe. The test consists of 8 instances of an EXCPT -// instruction followed by 0 to 7 NOPs and a BRT instruction (no bp), with -// the trace buffer enabled. -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000020 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - - // Save all the registers used in the ISR - [ -- SP ] = R0; - [ -- SP ] = R1; - [ -- SP ] = P0; - [ -- SP ] = P1; - [ -- SP ] = LC0; - [ -- SP ] = LB0; - [ -- SP ] = LT0; - [ -- SP ] = ASTAT; - - // Get EXCAUSE bits out of SEQSTAT - R0 = SEQSTAT; - R0 = R0 << 26; - R0 = R0 >> 26; - - // Check for Trace Exception - // Load r1 with EXCAUSE for Trace Exception - R1 = 0x0011 (Z); - // Check for Trace Exception -CC = R0 == R1; - // Branch to OUT if the EXCAUSE is not TRACE. -IF !CC JUMP OUT; - - // Read out the Trace Buffer. -LD32(p0, TBUFSTAT); - // Read TBUFSTAT MMR - P1 = [ P0 ]; - - // if p1 is zero skip the loop. -CC = P1 == 0; -IF CC JUMP OUT; - - // Read out the Entire Trace Buffer. -LD32(p0, TBUF); -LSETUP ( l0s , l0e ) LC0 = P1; -l0s:R0 = [ P0 ]; -l0e:R0 = [ P0 ]; - -OUT: - // Check for other exception, if any. - - // Restore all saved registers. -ASTAT = [ SP ++ ]; -LT0 = [ SP ++ ]; -LB0 = [ SP ++ ]; -LC0 = [ SP ++ ]; - P1 = [ SP ++ ]; - P0 = [ SP ++ ]; - R1 = [ SP ++ ]; - R0 = [ SP ++ ]; - - // Return -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -WR_MMR(TBUFCTL, 0x7, p0, r0); // Enable trace buffer & overflow - -CSYNC; // Wait for MMR write to complete - -CC = R7 == R6; // Set CC -EXCPT 1; -IF CC JUMP 4; // Mispredicted branch gets killed in WB stage -NOP; -NOP; - -EXCPT 2; -NOP; -IF CC JUMP 4; // Mispredicted branch gets killed in EX3 stage -NOP; -NOP; - -EXCPT 3; -NOP; -NOP; -IF CC JUMP 4; // Mispredicted branch gets killed in EX2 stage -NOP; -NOP; - -EXCPT 4; -NOP; -NOP; -NOP; -IF CC JUMP 4; // Mispredicted branch gets killed in EX1 stage -NOP; -NOP; - -EXCPT 5; -NOP; -NOP; -NOP; -NOP; -IF CC JUMP 4; // Mispredicted branch gets killed in AC stage -NOP; -NOP; - -EXCPT 6; -NOP; -NOP; -NOP; -NOP; -NOP; -IF CC JUMP 4; // Mispredicted branch gets killed in DEC stage -NOP; -NOP; - -EXCPT 7; NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -IF CC JUMP 4; // Mispredicted branch gets killed in IF2 stage -NOP; -NOP; - -EXCPT 8; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -IF CC JUMP 4; // Mispredicted branch gets killed in IF1 stage -NOP; -NOP; - - // Read out the Rest of the Trace Buffer. -LD32(p0, TBUFSTAT); - // Read TBUFSTAT MMR - P1 = [ P0 ]; - - // if p1 is zero skip the loop. -CC = P1 == 0; -IF CC JUMP OUT1; - - // Read out the Entire Trace Buffer. -LD32(p0, TBUF); -LSETUP ( l1s , l1e ) LC0 = P1; -l1s:R0 = [ P0 ]; -l1e:R0 = [ P0 ]; - - // Don't RTI if you never wish to go to User Mode - // use END_TEST instead. - -OUT1: -dbg_pass; - -// rti; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - - // YOUR USER CODE GOES HERE. - -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; -.dd 0x05050505; -.dd 0x06060606; -.dd 0x07070707; -.dd 0x08080808; -.dd 0x09090909; -.dd 0x0a0a0a0a; -.dd 0x0b0b0b0b; -.dd 0x0c0c0c0c; -.dd 0x0d0d0d0d; -.dd 0x0e0e0e0e; -.dd 0x0f0f0f0f; - -// Define Kernal Stack -.section MEM_DATA_ADDR_2 //.data 0x00F00210,"aw" - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/dbg_jmp_src_kill.S b/sim/testsuite/sim/bfin/dbg_jmp_src_kill.S deleted file mode 100644 index c0caf5b..0000000 --- a/sim/testsuite/sim/bfin/dbg_jmp_src_kill.S +++ /dev/null @@ -1,543 +0,0 @@ -//Original:/proj/frio/dv/testcases/debug/dbg_jmp_src_kill/dbg_jmp_src_kill.dsp -// Description: This test checks that the trace buffer keeps track of a JUMP -// source instruction getting killed at each stage in the pipe. The test -// consists of 8 instances of an EXCPT instruction followed by 0 to 7 NOPs -// and a JUMP, with the trace buffer enabled. -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000020 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - - // Save all the registers used in the ISR - [ -- SP ] = R0; - [ -- SP ] = R1; - [ -- SP ] = P0; - [ -- SP ] = P1; - [ -- SP ] = LC0; - [ -- SP ] = LB0; - [ -- SP ] = LT0; - [ -- SP ] = ASTAT; - - // Get EXCAUSE bits out of SEQSTAT - R0 = SEQSTAT; - R0 = R0 << 26; - R0 = R0 >> 26; - - // Check for Trace Exception - // Load r1 with EXCAUSE for Trace Exception - R1 = 0x0011 (Z); - // Check for Trace Exception -CC = R0 == R1; - // Branch to OUT if the EXCAUSE is not TRACE. -IF !CC JUMP OUT; - - // Read out the Trace Buffer. -LD32(p0, TBUFSTAT); - // Read TBUFSTAT MMR - P1 = [ P0 ]; - - // if p1 is zero skip the loop. -CC = P1 == 0; -IF CC JUMP OUT; - - // Read out the Entire Trace Buffer. -LD32(p0, TBUF); -LSETUP ( l0s , l0e ) LC0 = P1; -l0s:R0 = [ P0 ]; -l0e:R0 = [ P0 ]; - -OUT: - // Check for other exception, if any. - - // Restore all saved registers. -ASTAT = [ SP ++ ]; -LT0 = [ SP ++ ]; -LB0 = [ SP ++ ]; -LC0 = [ SP ++ ]; - P1 = [ SP ++ ]; - P0 = [ SP ++ ]; - R1 = [ SP ++ ]; - R0 = [ SP ++ ]; - - // Return -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -WR_MMR(TBUFCTL, 0x7, p0, r0); // Enable trace buffer & overflow - -CSYNC; // Wait for MMR write to complete - -EXCPT 1; -JUMP 4; // Jump gets killed in WB stage -NOP; -NOP; - -EXCPT 2; -NOP; -JUMP 4; // Jump gets killed in EX3 stage -NOP; -NOP; - -EXCPT 3; -NOP; -NOP; -JUMP 4; // Jump gets killed in EX2 stage -NOP; -NOP; - -EXCPT 4; -NOP; -NOP; -NOP; -JUMP 4; // Jump gets killed in EX1 stage -NOP; -NOP; - -EXCPT 5; -NOP; -NOP; -NOP; -NOP; -JUMP 4; // Jump gets killed in AC stage -NOP; -NOP; - -EXCPT 6; -NOP; -NOP; -NOP; -NOP; -NOP; -JUMP 4; // Jump gets killed in DEC stage -NOP; -NOP; - -EXCPT 7; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -JUMP 4; // Jump gets killed in IF2 stage -NOP; -NOP; - -EXCPT 8; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -JUMP 4; // Jump gets killed in IF1 stage -NOP; -NOP; - - // Read out the Rest of the Trace Buffer. -LD32(p0, TBUFSTAT); - // Read TBUFSTAT MMR - P1 = [ P0 ]; - - // if p1 is zero skip the loop. -CC = P1 == 0; -IF CC JUMP OUT1; - - // Read out the Entire Trace Buffer. -LD32(p0, TBUF); -LSETUP ( l1s , l1e ) LC0 = P1; -l1s:R0 = [ P0 ]; -l1e:R0 = [ P0 ]; - - // Don't RTI if you never wish to go to User Mode - // use END_TEST instead. - -OUT1: -dbg_pass; - -// rti; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - - // YOUR USER CODE GOES HERE. - -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; -.dd 0x05050505; -.dd 0x06060606; -.dd 0x07070707; -.dd 0x08080808; -.dd 0x09090909; -.dd 0x0a0a0a0a; -.dd 0x0b0b0b0b; -.dd 0x0c0c0c0c; -.dd 0x0d0d0d0d; -.dd 0x0e0e0e0e; -.dd 0x0f0f0f0f; - -// Define Kernal Stack -.section MEM_DATA_ADDR_2 //.data 0x00F00210,"aw" - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/dbg_tr_basic.S b/sim/testsuite/sim/bfin/dbg_tr_basic.S deleted file mode 100644 index b7fa5b6..0000000 --- a/sim/testsuite/sim/bfin/dbg_tr_basic.S +++ /dev/null @@ -1,272 +0,0 @@ -//Original:/proj/frio/dv/testcases/debug/dbg_tr_basic/dbg_tr_basic.dsp -// Description: Verify the basic functionality of TBUFPWR and TBUFEN in -// Supervisor mode -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(mmrs.inc) -include(selfcheck.inc) - -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -// This test embeds .text offsets, so pad our test so it lines up. -.space 0x70 - -// Boot code - - BOOT : -INIT_R_REGS(0); // Initialize Dregs -INIT_P_REGS(0); // Initialize Pregs - -CHECK_INIT(p5, 0x00BFFFFC); - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE); // IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE); // IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE); // IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE); // IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE); // IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE); // IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -LD32_LABEL(p1, START); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -LD32_LABEL(r7, DUMMY); -RETI = r7; -RAISE 15; // after we RTI, INT 15 should be taken - -NOP; // Workaround for Bug 217 -RTI; -NOP; -NOP; -NOP; -DUMMY: - NOP; -NOP; -NOP; -NOP; - - - - START : -WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn ON trace Buffer - // TBUFPWR = 0 - // TBUFEN = 0 - // TBUFOVF = 0 - // CMPLP = 0 -NOP; -NOP; -NOP; -NOP; -NOP; - NOP; -NOP; -JUMP.S label1; // - R4.L = 0x1111; // Will be killed - R4.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -label2: R5.H = 0x7777; // - R5.L = 0x7888; -JUMP.S label3; // - R6.L = 0x1111; // Will be killed - R6.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -NOP; -NOP; -label1: R4.H = 0x5555; // - R4.L = 0x6666; -NOP; -WR_MMR(TBUFCTL, 0x00000002, p0, r0); // - // TBUFPWR = 0 - // TBUFEN = 1 - // TBUFOVF = 0 - // CMPLP = 0 -NOP; -NOP; -NOP; -NOP; -JUMP.S label2; // - R5.L = 0x1111; // Will be killed - R5.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -NOP; -label3: R6.H = 0x7999; // - R6.L = 0x7aaa; -NOP; -NOP; -WR_MMR(TBUFCTL, 0x00000001, p0, r0); - NOP; - NOP; - NOP; -WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer - // TBUFPWR = 1 - // TBUFEN = 1 - // TBUFOVF = 0 - // CMPLP = 0 -NOP; -NOP; -NOP; -NOP; -JUMP.S label4; // - R5.L = 0x1111; // Will be killed - R5.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -NOP; - -label4: R6.H = 0x1aaa; // - R6.L = 0x2222; -NOP; -NOP; -NOP; -NOP; - -WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn OFF trace Buffer - -NOP; -NOP; -NOP; -NOP; - // Read the contents of the Trace Buffer - -RD_MMR(TBUFSTAT, p0, r2); -CHECKREG(r2, 0x00000001); - - // Read 3rd Entry of the Trace Buffer -RD_MMR(TBUF, p0, r0); -CHECKREG(r0, 0x000002d2); - -RD_MMR(TBUFSTAT, p0, r2); -CHECKREG(r2, 0x00000001); - -RD_MMR(TBUF, p0, r1); -CHECKREG(r1, 0x000002c0); - -RD_MMR(TBUFSTAT, p0, r2); -CHECKREG(r2, 0x00000000); - - -WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn OFF trace Buffer Power - -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - - - -//********************************************************************* -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; diff --git a/sim/testsuite/sim/bfin/dbg_tr_simplejp.S b/sim/testsuite/sim/bfin/dbg_tr_simplejp.S deleted file mode 100644 index 8fe5f20..0000000 --- a/sim/testsuite/sim/bfin/dbg_tr_simplejp.S +++ /dev/null @@ -1,267 +0,0 @@ -//Original:/proj/frio/dv/testcases/debug/dbg_tr_simplejp/dbg_tr_simplejp.dsp -// Description: This test performs simple jumps and verifies the trace buffer -// recording for simple jumps. -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(mmrs.inc) -include(selfcheck.inc) -include(symtable.inc) - -#ifndef ITABLE -#define ITABLE CODE_ADDR_1 // -#endif - -// This test embeds .text offsets, so pad our test so it lines up. -.space 0x5e - -// Boot code - - BOOT : -INIT_R_REGS(0); // Initialize Dregs -INIT_P_REGS(0); // Initialize Pregs - -CHECK_INIT_DEF(p5); // CHECK_INIT(p5, 0x00BFFFFC); - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE); // IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE); // IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE); // IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE); // IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE); // IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE); // IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -LD32_LABEL(p1, START); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -LD32_LABEL(r7, DUMMY); -RETI = r7; -RAISE 15; // after we RTI, INT 15 should be taken - -NOP; // Workaround for Bug 217 -RTI; -NOP; -NOP; -NOP; -DUMMY: - NOP; -NOP; -NOP; -NOP; - - - - START : -WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer - // TBUFPWR = 1 - // TBUFEN = 1 - // TBUFOVF = 0 - // CMPLP = 0 -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -JUMP.S label1; // 0x0224 - R4.L = 0x1111; // Will be killed - R4.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -label2: R5.H = 0x7777; // 0x0234 - R5.L = 0x7888; -JUMP.S label3; //0x023c - R6.L = 0x1111; // Will be killed - R6.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -NOP; -NOP; -label1: R4.H = 0x5555; // 0x0250 - R4.L = 0x6666; -NOP; -JUMP.S label2; // 0x0258 - R5.L = 0x1111; // Will be killed - R5.H = 0x1111; // Will be killed -NOP; -NOP; -NOP; -NOP; -label3: R6.H = 0x7999; //0x026c - R6.L = 0x7aaa; -NOP; -NOP; -NOP; -NOP; - -WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn OFF trace Buffer - -NOP; -NOP; -NOP; -NOP; -NOP; - // Read the contents of the Trace Buffer - -RD_MMR(TBUFSTAT, p0, r2); -CHECKREG(r2, 0x00000003); - - // Read 3rd Entry of the Trace Buffer -RD_MMR(TBUF, p0, r0); -CHECKREG(r0, 0x0000026c); - -RD_MMR(TBUFSTAT, p0, r2); -CHECKREG(r2, 0x00000003); - -RD_MMR(TBUF, p0, r1); -CHECKREG(r1, 0x0000023c); - -RD_MMR(TBUFSTAT, p0, r2); -CHECKREG(r2, 0x00000002); - - // Read 2nd Entry of the Trace Buffer -RD_MMR(TBUF, p0, r0); -CHECKREG(r0, 0x00000234); - -RD_MMR(TBUFSTAT, p0, r2); -CHECKREG(r2, 0x00000002); - -RD_MMR(TBUF, p0, r1); -CHECKREG(r1, 0x0000025a); - -RD_MMR(TBUFSTAT, p0, r2); -CHECKREG(r2, 0x00000001); - - // Read ist Entry of the Trace Buffer -RD_MMR(TBUF, p0, r0); -CHECKREG(r0, 0x00000250); - -RD_MMR(TBUFSTAT, p0, r2); -CHECKREG(r2, 0x00000001); - -RD_MMR(TBUF, p0, r1); -CHECKREG(r1, 0x00000224); - -RD_MMR(TBUFSTAT, p0, r2); -CHECKREG(r2, 0x00000000); - -WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn OFF trace Buffer Power - -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - - - -//********************************************************************* -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; diff --git a/sim/testsuite/sim/bfin/dbg_tr_tbuf0.S b/sim/testsuite/sim/bfin/dbg_tr_tbuf0.S deleted file mode 100644 index 82ca6ce..0000000 --- a/sim/testsuite/sim/bfin/dbg_tr_tbuf0.S +++ /dev/null @@ -1,262 +0,0 @@ -//Original:/proj/frio/dv/testcases/debug/dbg_tr_tbuf0/dbg_tr_tbuf0.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(mmrs.inc) -include(selfcheck.inc) - -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -// This test embeds .text offsets, so pad our test so it lines up. -.space 0x64 - -// Boot code - - BOOT : -INIT_R_REGS(0); // Initialize Dregs -INIT_P_REGS(0); // Initialize Pregs - -CHECK_INIT(p5, 0x00BFFFFC); - - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE); // IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE); // IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE); // IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE); // IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE); // IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE); // IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -LD32_LABEL(p1, START); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -LD32_LABEL(r7, DUMMY); -RETI = r7; -RAISE 15; // after we RTI, INT 15 should be taken - -NOP; // Workaround for Bug 217 -RTI; -NOP; -NOP; -NOP; -DUMMY: - NOP; -NOP; -NOP; -NOP; - - - - START : - -WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn ON trace Buffer -WR_MMR(TBUFCTL, 0x0000000b, p0, r0); // Turn ON trace Buffer - // TBUFPWR = 1 - // TBUFEN = 1 - // TBUFOVF = 0 - // CMPLP = 01 -NOP; -NOP; -NOP; - NOP; - NOP; - R6 = 0; - R7 = 10; - -JMP: - JUMP.S LABEL0; - NOP; - NOP; - -LABEL0: - P1 = 0x0006; - JUMP (PC+P1); - -LABEL1: - LD32(R3, 0xBADD); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - -LABEL2: - CC = R7 == R6; - IF CC JUMP END; - R6 += 1; - JUMP LABEL2; - -LABEL3: - NOP; - -LABEL4: - LD32(R4, 0xBADD); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - - - - -END: - R0 = 1; - NOP; - NOP; - NOP; - -CHECKREG(r3, 0x00000000); -CHECKREG(r4, 0x00000000); - // Read the contents of the Trace Buffer - -RD_MMR(TBUFSTAT, p0, r0); -CHECKREG(r0, 0x00000004); - - // Read last entry of the Trace Buffer -RD_MMR(TBUF, p0, r1); -CHECKREG(r1, 0x00000256); - -RD_MMR(TBUF, p0, r2); -CHECKREG(r2, 0x00000246); - -RD_MMR(TBUFSTAT, p0, r0); -CHECKREG(r0, 0x00000003); - - // Read last entry of the Trace Buffer -RD_MMR(TBUF, p0, r1); -CHECKREG(r1, 0x00000245); - -RD_MMR(TBUF, p0, r2); -CHECKREG(r2, 0x0000024a); - -RD_MMR(TBUFSTAT, p0, r0); -CHECKREG(r0, 0x00000002); - - // Read last entry of the Trace Buffer -RD_MMR(TBUF, p0, r1); -CHECKREG(r1, 0x00000240); - -RD_MMR(TBUF, p0, r2); -CHECKREG(r2, 0x0000023a); - -RD_MMR(TBUFSTAT, p0, r0); -CHECKREG(r0, 0x00000001); - - // Read last entry of the Trace Buffer -RD_MMR(TBUF, p0, r1); -CHECKREG(r1, 0x00000238); - -RD_MMR(TBUF, p0, r2); -CHECKREG(r2, 0x00000232); - - - -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - - - -//********************************************************************* -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - -RTX; - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; diff --git a/sim/testsuite/sim/bfin/dbg_tr_umode.S b/sim/testsuite/sim/bfin/dbg_tr_umode.S deleted file mode 100644 index 83c3f74..0000000 --- a/sim/testsuite/sim/bfin/dbg_tr_umode.S +++ /dev/null @@ -1,314 +0,0 @@ -//Original:/proj/frio/dv/testcases/debug/dbg_tr_umode/dbg_tr_umode.dsp -// Description: Verify the basic functionality of TBUFPWR and TBUFEN in -// Supervisor mode -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(std.inc) -include(mmrs.inc) -include(selfcheck.inc) - -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x20 -#endif - -// This test embeds .text offsets, so pad our test so it lines up. -.space 0x64 - -// Boot code - - BOOT : -INIT_R_REGS(0); // Initialize Dregs -INIT_P_REGS(0); // Initialize Pregs - -CHECK_INIT(p5, 0x00BFFFFC); - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE); // IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE); // IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE); // IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE); // IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE); // IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE); // IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -LD32_LABEL(p1, START); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -LD32_LABEL(r7, DUMMY); -RETI = r7; -RAISE 15; // after we RTI, INT 15 should be taken - -NOP; // Workaround for Bug 217 -RTI; -NOP; -NOP; -NOP; -DUMMY: - NOP; -NOP; -NOP; -NOP; - -// .code 0x200 -START: -WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn ON trace Buffer -WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer - // TBUFPWR = 1 - // TBUFEN = 1 - // TBUFOVF = 0 - // CMPLP = 0 -NOP; -NOP; -NOP; -NOP; - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -RTI; - -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - -NOP; - NOP; -NOP; -JUMP.S label1; - R4.L = 0x1111; - R4.H = 0x1111; -NOP; -NOP; -NOP; -label2: R5.H = 0x7777; - R5.L = 0x7888; -JUMP.S label3; - R6.L = 0x1111; - R6.H = 0x1111; -NOP; -NOP; -NOP; -NOP; -NOP; -label1: R4.H = 0x5555; - R4.L = 0x6666; -NOP; -NOP; -NOP; -NOP; -NOP; -JUMP.S label2; - R5.L = 0x1111; - R5.H = 0x1111; -NOP; -NOP; -NOP; -NOP; -label3: - NOP; -NOP; -NOP; - NOP; - NOP; - NOP; -NOP; -NOP; - // Checks the contents of the Trace Buffer - - EXCPT 0; - NOP; NOP; NOP; NOP; -CHECKREG(r2, 0x00000006); -CHECKREG(r1, 0x00000416); -CHECKREG(r0, 0x000002aa); -CHECKREG(r3, 0x0000029a); -CHECKREG(r4, 0x00000262); -CHECKREG(r5, 0x00000004); -CHECKREG(r6, 0x0000025a); -CHECKREG(r7, 0x00000288); - NOP; NOP; NOP; NOP; - NOP; NOP; NOP; NOP; - - EXCPT 1; - NOP; NOP; NOP; NOP; - CHECKREG(r2, 0x00000005); -CHECKREG(r1, 0x00000416); -CHECKREG(r0, 0x00000304); -CHECKREG(r3, 0x000002ac); -CHECKREG(r4, 0x00000470); -CHECKREG(r5, 0x00000003); -CHECKREG(r6, 0x00000276); -CHECKREG(r7, 0x0000024a); - NOP; NOP; NOP; NOP; - NOP; NOP; NOP; NOP; - - EXCPT 2; - NOP; NOP; NOP; NOP; - CHECKREG(r2, 0x00000004); -CHECKREG(r1, 0x00000416); -CHECKREG(r0, 0x0000035e); -CHECKREG(r3, 0x00000306); -CHECKREG(r4, 0x00000470); -CHECKREG(r5, 0x00000002); -CHECKREG(r6, 0x00000244); -CHECKREG(r7, 0x00000242); - NOP; NOP; NOP; NOP; - - EXCPT 3; - NOP; NOP; NOP; NOP; - CHECKREG(r2, 0x00000003); -CHECKREG(r1, 0x00000416); -CHECKREG(r0, 0x000003b0); -CHECKREG(r3, 0x00000360); -CHECKREG(r4, 0x00000470); -CHECKREG(r5, 0x00000001); -CHECKREG(r6, 0x00000238); -CHECKREG(r7, 0x00000236); - - - -NOP; -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - - - -//********************************************************************* -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - R7 = SEQSTAT; - -RD_MMR(TBUFSTAT, p0, r2); -RD_MMR(TBUF, p0, r1); -RD_MMR(TBUF, p0, r0); -RD_MMR(TBUF, p0, r3); -RD_MMR(TBUF, p0, r4); -RD_MMR(TBUFSTAT, p0, r5); -RD_MMR(TBUF, p0, r6); -RD_MMR(TBUF, p0, r7); - - NOP; NOP; NOP; NOP; - -RTX; - - NOP; NOP; NOP; NOP; - NOP; NOP; NOP; NOP; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/disalnexcpt_implicit.S b/sim/testsuite/sim/bfin/disalnexcpt_implicit.S deleted file mode 100644 index 9f6c83c..0000000 --- a/sim/testsuite/sim/bfin/disalnexcpt_implicit.S +++ /dev/null @@ -1,122 +0,0 @@ -# Blackfin testcase for insns that implicitly have DISALGNEXCPT behavior -# when used in parallel insns -# mach: bfin - -#include "test.h" - .include "testutils.inc" - - start - - LINK 0x100; - - # Set up I0/I1/I2/I3 to be unaligned by 0/1/2/3 bytes - init_l_regs 0 - init_m_regs 0 - R0 = SP; - BITCLR (R0, 0); - BITCLR (R0, 1); - I0 = R0; - B0 = R0; - R1 = 1; - R1 = R0 + R1; - I1 = R1; - B1 = R1; - R2 = 2; - R2 = R0 + R2; - I2 = R2; - B2 = R2; - R3 = 3; - R3 = R0 + R3; - I3 = R3; - B3 = R3; - -#define EXP_VAL 0x12345678 -#define EXP(r, n) CHECKREG (r, EXP_VAL); r = 0; I##n = B##n - imm32 R5, EXP_VAL; - imm32 R6, 0x9abcdef0; - imm32 R7, 0x0a1b2c3e; - [SP] = R5; - [SP - 4] = R6; - [SP + 4] = R7; - -#define BYTEPACK(n) \ - R7 = BYTEPACK (R0, R1) || R4 = [I##n]; EXP (R4, n); \ - R6 = BYTEPACK (R0, R1) || R5 = [I##n ++ M##n]; EXP (R5, n); \ - R5 = BYTEPACK (R0, R1) || R6 = [I##n++]; EXP (R6, n); \ - R4 = BYTEPACK (R0, R1) || R7 = [I##n--]; EXP (R7, n); - BYTEPACK(0) - BYTEPACK(1) - BYTEPACK(2) - BYTEPACK(3) - -#define BYTEUNPACK(n) \ - (R7, R5) = BYTEUNPACK R1:0 || R4 = [I##n]; EXP (R4, n); \ - (R6, R7) = BYTEUNPACK R3:2 || R5 = [I##n ++ M##n]; EXP (R5, n); \ - (R5, R4) = BYTEUNPACK R1:0 || R6 = [I##n++]; EXP (R6, n); \ - (R4, R6) = BYTEUNPACK R3:2 || R7 = [I##n--]; EXP (R7, n); - BYTEUNPACK(0) - BYTEUNPACK(1) - BYTEUNPACK(2) - BYTEUNPACK(3) - -#define SAA(n) \ - SAA (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \ - SAA (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \ - SAA (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \ - SAA (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n); - SAA(0) - SAA(1) - SAA(2) - SAA(3) - -#define BYTEOP1P(n) \ - R7 = BYTEOP1P (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \ - R6 = BYTEOP1P (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \ - R5 = BYTEOP1P (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \ - R4 = BYTEOP1P (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n); - BYTEOP1P(0) - BYTEOP1P(1) - BYTEOP1P(2) - BYTEOP1P(3) - -#define BYTEOP2P(n) \ - R7 = BYTEOP2P (R1:0, R3:2) (TL) || R4 = [I##n]; EXP (R4, n); \ - R6 = BYTEOP2P (R1:0, R3:2) (TH) || R5 = [I##n ++ M##n]; EXP (R5, n); \ - R5 = BYTEOP2P (R1:0, R3:2) (RNDL) || R6 = [I##n++]; EXP (R6, n); \ - R4 = BYTEOP2P (R1:0, R3:2) (RNDH) || R7 = [I##n--]; EXP (R7, n); - BYTEOP2P(0) - BYTEOP2P(1) - BYTEOP2P(2) - BYTEOP2P(3) - -#define BYTEOP3P(n) \ - R7 = BYTEOP3P (R1:0, R3:2) (LO) || R4 = [I##n]; EXP (R4, n); \ - R6 = BYTEOP3P (R1:0, R3:2) (HI) || R5 = [I##n ++ M##n]; EXP (R5, n); \ - R5 = BYTEOP3P (R1:0, R3:2) (LO) || R6 = [I##n++]; EXP (R6, n); \ - R4 = BYTEOP3P (R1:0, R3:2) (HI) || R7 = [I##n--]; EXP (R7, n); - BYTEOP3P(0) - BYTEOP3P(1) - BYTEOP3P(2) - BYTEOP3P(3) - -#define BYTEOP16P(n) \ - (R7, R6) = BYTEOP16P (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \ - (R6, R4) = BYTEOP16P (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \ - (R5, R7) = BYTEOP16P (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \ - (R4, R6) = BYTEOP16P (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n); - BYTEOP16P(0) - BYTEOP16P(1) - BYTEOP16P(2) - BYTEOP16P(3) - -#define BYTEOP16M(n) \ - (R7, R5) = BYTEOP16M (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \ - (R6, R7) = BYTEOP16M (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \ - (R5, R4) = BYTEOP16M (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \ - (R4, R5) = BYTEOP16M (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n); - BYTEOP16M(0) - BYTEOP16M(1) - BYTEOP16M(2) - BYTEOP16M(3) - - pass diff --git a/sim/testsuite/sim/bfin/div0.s b/sim/testsuite/sim/bfin/div0.s deleted file mode 100644 index e52fe45..0000000 --- a/sim/testsuite/sim/bfin/div0.s +++ /dev/null @@ -1,37 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - R0 = 70 (X); - R1 = 5; - - P2 = 16; - DIVS ( R0 , R1 ); - LSETUP ( s0 , s0 ) LC0 = P2; -s0: - DIVQ ( R0 , R1 ); - - DBGA ( R0.L , 14 ); - - R0 = 3272 (X); - R1 = 55; - - DIVS ( R0 , R1 ); - LSETUP ( s1 , s1 ) LC0 = P2; -s1: - DIVQ ( R0 , R1 ); - - DBGA ( R0.L , 59 ); - - R0 = 32767 (X); - R1 = 55; - DIVS ( R0 , R1 ); - - LSETUP ( s2 , s2 ) LC0 = P2; -s2: - DIVQ ( R0 , R1 ); - - DBGA ( R0.L , 595 ); - - pass diff --git a/sim/testsuite/sim/bfin/divq.s b/sim/testsuite/sim/bfin/divq.s deleted file mode 100644 index 6cb881b..0000000 --- a/sim/testsuite/sim/bfin/divq.s +++ /dev/null @@ -1,1322 +0,0 @@ -# Blackfin testcase for divide instructions -# mach: bfin - - - .include "testutils.inc" - - start - - /* - * Evaluate given a signed integer dividend and signed interger divisor - * input is: - * r0 = dividend, or numerator - * r1 = divisor, or denominator - * output is: - * r0 = quotient (16-bits) - */ - .macro divide num:req, den:req - imm32 r0 \num - r1 = \den (Z); - - r0 <<= 1; /* Left shift dividend by 1 needed for integer division */ - p0 = 15; /* Evaluate the quotient to 16 bits. */ - - /* Initialize AQ status bit and dividend for the DIVQ loop. */ - divs (r0, r1); - - /* Evaluate DIVQ p0=15 times. */ - lsetup (1f, 1f) lc0=p0; -1: - divq (r0, r1); - - /* Sign extend the 16-bit quotient to 32bits. */ - r0 = r0.l (x); - - imm32 r1, (\num / \den); - CC = r0 == r1 - if CC jump 2f; - fail -2: - .endm - - /* test a bunch of values, making sure not to : - * - exceed a signed 16-bit divisor - * - exceed a signed 16-bit answer - */ - divide 0x00000001, 0x0001 /* expect 0x0001 */ - divide 0x00000001, 0x0002 /* expect 0x0000 */ - divide 0x00000001, 0x0003 /* expect 0x0000 */ - divide 0x00000001, 0x0004 /* expect 0x0000 */ - divide 0x00000001, 0x0007 /* expect 0x0000 */ - divide 0x00000001, 0x0008 /* expect 0x0000 */ - divide 0x00000001, 0x000f /* expect 0x0000 */ - divide 0x00000001, 0x0010 /* expect 0x0000 */ - divide 0x00000001, 0x001f /* expect 0x0000 */ - divide 0x00000001, 0x0020 /* expect 0x0000 */ - divide 0x00000001, 0x003f /* expect 0x0000 */ - divide 0x00000001, 0x0040 /* expect 0x0000 */ - divide 0x00000001, 0x007f /* expect 0x0000 */ - divide 0x00000001, 0x0080 /* expect 0x0000 */ - divide 0x00000001, 0x00ff /* expect 0x0000 */ - divide 0x00000001, 0x0100 /* expect 0x0000 */ - divide 0x00000001, 0x01ff /* expect 0x0000 */ - divide 0x00000001, 0x0200 /* expect 0x0000 */ - divide 0x00000001, 0x03ff /* expect 0x0000 */ - divide 0x00000001, 0x0400 /* expect 0x0000 */ - divide 0x00000001, 0x07ff /* expect 0x0000 */ - divide 0x00000001, 0x0800 /* expect 0x0000 */ - divide 0x00000001, 0x0fff /* expect 0x0000 */ - divide 0x00000001, 0x1000 /* expect 0x0000 */ - divide 0x00000001, 0x1fff /* expect 0x0000 */ - divide 0x00000001, 0x2000 /* expect 0x0000 */ - divide 0x00000001, 0x3fff /* expect 0x0000 */ - divide 0x00000001, 0x4000 /* expect 0x0000 */ - divide 0x00000001, 0x7fff /* expect 0x0000 */ - divide 0x00000002, 0x0001 /* expect 0x0002 */ - divide 0x00000002, 0x0002 /* expect 0x0001 */ - divide 0x00000002, 0x0003 /* expect 0x0000 */ - divide 0x00000002, 0x0004 /* expect 0x0000 */ - divide 0x00000002, 0x0007 /* expect 0x0000 */ - divide 0x00000002, 0x0008 /* expect 0x0000 */ - divide 0x00000002, 0x000f /* expect 0x0000 */ - divide 0x00000002, 0x0010 /* expect 0x0000 */ - divide 0x00000002, 0x001f /* expect 0x0000 */ - divide 0x00000002, 0x0020 /* expect 0x0000 */ - divide 0x00000002, 0x003f /* expect 0x0000 */ - divide 0x00000002, 0x0040 /* expect 0x0000 */ - divide 0x00000002, 0x007f /* expect 0x0000 */ - divide 0x00000002, 0x0080 /* expect 0x0000 */ - divide 0x00000002, 0x00ff /* expect 0x0000 */ - divide 0x00000002, 0x0100 /* expect 0x0000 */ - divide 0x00000002, 0x01ff /* expect 0x0000 */ - divide 0x00000002, 0x0200 /* expect 0x0000 */ - divide 0x00000002, 0x03ff /* expect 0x0000 */ - divide 0x00000002, 0x0400 /* expect 0x0000 */ - divide 0x00000002, 0x07ff /* expect 0x0000 */ - divide 0x00000002, 0x0800 /* expect 0x0000 */ - divide 0x00000002, 0x0fff /* expect 0x0000 */ - divide 0x00000002, 0x1000 /* expect 0x0000 */ - divide 0x00000002, 0x1fff /* expect 0x0000 */ - divide 0x00000002, 0x2000 /* expect 0x0000 */ - divide 0x00000002, 0x3fff /* expect 0x0000 */ - divide 0x00000002, 0x4000 /* expect 0x0000 */ - divide 0x00000002, 0x7fff /* expect 0x0000 */ - divide 0x00000003, 0x0001 /* expect 0x0003 */ - divide 0x00000003, 0x0002 /* expect 0x0001 */ - divide 0x00000003, 0x0003 /* expect 0x0001 */ - divide 0x00000003, 0x0004 /* expect 0x0000 */ - divide 0x00000003, 0x0007 /* expect 0x0000 */ - divide 0x00000003, 0x0008 /* expect 0x0000 */ - divide 0x00000003, 0x000f /* expect 0x0000 */ - divide 0x00000003, 0x0010 /* expect 0x0000 */ - divide 0x00000003, 0x001f /* expect 0x0000 */ - divide 0x00000003, 0x0020 /* expect 0x0000 */ - divide 0x00000003, 0x003f /* expect 0x0000 */ - divide 0x00000003, 0x0040 /* expect 0x0000 */ - divide 0x00000003, 0x007f /* expect 0x0000 */ - divide 0x00000003, 0x0080 /* expect 0x0000 */ - divide 0x00000003, 0x00ff /* expect 0x0000 */ - divide 0x00000003, 0x0100 /* expect 0x0000 */ - divide 0x00000003, 0x01ff /* expect 0x0000 */ - divide 0x00000003, 0x0200 /* expect 0x0000 */ - divide 0x00000003, 0x03ff /* expect 0x0000 */ - divide 0x00000003, 0x0400 /* expect 0x0000 */ - divide 0x00000003, 0x07ff /* expect 0x0000 */ - divide 0x00000003, 0x0800 /* expect 0x0000 */ - divide 0x00000003, 0x0fff /* expect 0x0000 */ - divide 0x00000003, 0x1000 /* expect 0x0000 */ - divide 0x00000003, 0x1fff /* expect 0x0000 */ - divide 0x00000003, 0x2000 /* expect 0x0000 */ - divide 0x00000003, 0x3fff /* expect 0x0000 */ - divide 0x00000003, 0x4000 /* expect 0x0000 */ - divide 0x00000003, 0x7fff /* expect 0x0000 */ - divide 0x00000004, 0x0001 /* expect 0x0004 */ - divide 0x00000004, 0x0002 /* expect 0x0002 */ - divide 0x00000004, 0x0003 /* expect 0x0001 */ - divide 0x00000004, 0x0004 /* expect 0x0001 */ - divide 0x00000004, 0x0007 /* expect 0x0000 */ - divide 0x00000004, 0x0008 /* expect 0x0000 */ - divide 0x00000004, 0x000f /* expect 0x0000 */ - divide 0x00000004, 0x0010 /* expect 0x0000 */ - divide 0x00000004, 0x001f /* expect 0x0000 */ - divide 0x00000004, 0x0020 /* expect 0x0000 */ - divide 0x00000004, 0x003f /* expect 0x0000 */ - divide 0x00000004, 0x0040 /* expect 0x0000 */ - divide 0x00000004, 0x007f /* expect 0x0000 */ - divide 0x00000004, 0x0080 /* expect 0x0000 */ - divide 0x00000004, 0x00ff /* expect 0x0000 */ - divide 0x00000004, 0x0100 /* expect 0x0000 */ - divide 0x00000004, 0x01ff /* expect 0x0000 */ - divide 0x00000004, 0x0200 /* expect 0x0000 */ - divide 0x00000004, 0x03ff /* expect 0x0000 */ - divide 0x00000004, 0x0400 /* expect 0x0000 */ - divide 0x00000004, 0x07ff /* expect 0x0000 */ - divide 0x00000004, 0x0800 /* expect 0x0000 */ - divide 0x00000004, 0x0fff /* expect 0x0000 */ - divide 0x00000004, 0x1000 /* expect 0x0000 */ - divide 0x00000004, 0x1fff /* expect 0x0000 */ - divide 0x00000004, 0x2000 /* expect 0x0000 */ - divide 0x00000004, 0x3fff /* expect 0x0000 */ - divide 0x00000004, 0x4000 /* expect 0x0000 */ - divide 0x00000004, 0x7fff /* expect 0x0000 */ - divide 0x00000007, 0x0001 /* expect 0x0007 */ - divide 0x00000007, 0x0002 /* expect 0x0003 */ - divide 0x00000007, 0x0003 /* expect 0x0002 */ - divide 0x00000007, 0x0004 /* expect 0x0001 */ - divide 0x00000007, 0x0007 /* expect 0x0001 */ - divide 0x00000007, 0x0008 /* expect 0x0000 */ - divide 0x00000007, 0x000f /* expect 0x0000 */ - divide 0x00000007, 0x0010 /* expect 0x0000 */ - divide 0x00000007, 0x001f /* expect 0x0000 */ - divide 0x00000007, 0x0020 /* expect 0x0000 */ - divide 0x00000007, 0x003f /* expect 0x0000 */ - divide 0x00000007, 0x0040 /* expect 0x0000 */ - divide 0x00000007, 0x007f /* expect 0x0000 */ - divide 0x00000007, 0x0080 /* expect 0x0000 */ - divide 0x00000007, 0x00ff /* expect 0x0000 */ - divide 0x00000007, 0x0100 /* expect 0x0000 */ - divide 0x00000007, 0x01ff /* expect 0x0000 */ - divide 0x00000007, 0x0200 /* expect 0x0000 */ - divide 0x00000007, 0x03ff /* expect 0x0000 */ - divide 0x00000007, 0x0400 /* expect 0x0000 */ - divide 0x00000007, 0x07ff /* expect 0x0000 */ - divide 0x00000007, 0x0800 /* expect 0x0000 */ - divide 0x00000007, 0x0fff /* expect 0x0000 */ - divide 0x00000007, 0x1000 /* expect 0x0000 */ - divide 0x00000007, 0x1fff /* expect 0x0000 */ - divide 0x00000007, 0x2000 /* expect 0x0000 */ - divide 0x00000007, 0x3fff /* expect 0x0000 */ - divide 0x00000007, 0x4000 /* expect 0x0000 */ - divide 0x00000007, 0x7fff /* expect 0x0000 */ - divide 0x00000008, 0x0001 /* expect 0x0008 */ - divide 0x00000008, 0x0002 /* expect 0x0004 */ - divide 0x00000008, 0x0003 /* expect 0x0002 */ - divide 0x00000008, 0x0004 /* expect 0x0002 */ - divide 0x00000008, 0x0007 /* expect 0x0001 */ - divide 0x00000008, 0x0008 /* expect 0x0001 */ - divide 0x00000008, 0x000f /* expect 0x0000 */ - divide 0x00000008, 0x0010 /* expect 0x0000 */ - divide 0x00000008, 0x001f /* expect 0x0000 */ - divide 0x00000008, 0x0020 /* expect 0x0000 */ - divide 0x00000008, 0x003f /* expect 0x0000 */ - divide 0x00000008, 0x0040 /* expect 0x0000 */ - divide 0x00000008, 0x007f /* expect 0x0000 */ - divide 0x00000008, 0x0080 /* expect 0x0000 */ - divide 0x00000008, 0x00ff /* expect 0x0000 */ - divide 0x00000008, 0x0100 /* expect 0x0000 */ - divide 0x00000008, 0x01ff /* expect 0x0000 */ - divide 0x00000008, 0x0200 /* expect 0x0000 */ - divide 0x00000008, 0x03ff /* expect 0x0000 */ - divide 0x00000008, 0x0400 /* expect 0x0000 */ - divide 0x00000008, 0x07ff /* expect 0x0000 */ - divide 0x00000008, 0x0800 /* expect 0x0000 */ - divide 0x00000008, 0x0fff /* expect 0x0000 */ - divide 0x00000008, 0x1000 /* expect 0x0000 */ - divide 0x00000008, 0x1fff /* expect 0x0000 */ - divide 0x00000008, 0x2000 /* expect 0x0000 */ - divide 0x00000008, 0x3fff /* expect 0x0000 */ - divide 0x00000008, 0x4000 /* expect 0x0000 */ - divide 0x00000008, 0x7fff /* expect 0x0000 */ - divide 0x0000000f, 0x0001 /* expect 0x000f */ - divide 0x0000000f, 0x0002 /* expect 0x0007 */ - divide 0x0000000f, 0x0003 /* expect 0x0005 */ - divide 0x0000000f, 0x0004 /* expect 0x0003 */ - divide 0x0000000f, 0x0007 /* expect 0x0002 */ - divide 0x0000000f, 0x0008 /* expect 0x0001 */ - divide 0x0000000f, 0x000f /* expect 0x0001 */ - divide 0x0000000f, 0x0010 /* expect 0x0000 */ - divide 0x0000000f, 0x001f /* expect 0x0000 */ - divide 0x0000000f, 0x0020 /* expect 0x0000 */ - divide 0x0000000f, 0x003f /* expect 0x0000 */ - divide 0x0000000f, 0x0040 /* expect 0x0000 */ - divide 0x0000000f, 0x007f /* expect 0x0000 */ - divide 0x0000000f, 0x0080 /* expect 0x0000 */ - divide 0x0000000f, 0x00ff /* expect 0x0000 */ - divide 0x0000000f, 0x0100 /* expect 0x0000 */ - divide 0x0000000f, 0x01ff /* expect 0x0000 */ - divide 0x0000000f, 0x0200 /* expect 0x0000 */ - divide 0x0000000f, 0x03ff /* expect 0x0000 */ - divide 0x0000000f, 0x0400 /* expect 0x0000 */ - divide 0x0000000f, 0x07ff /* expect 0x0000 */ - divide 0x0000000f, 0x0800 /* expect 0x0000 */ - divide 0x0000000f, 0x0fff /* expect 0x0000 */ - divide 0x0000000f, 0x1000 /* expect 0x0000 */ - divide 0x0000000f, 0x1fff /* expect 0x0000 */ - divide 0x0000000f, 0x2000 /* expect 0x0000 */ - divide 0x0000000f, 0x3fff /* expect 0x0000 */ - divide 0x0000000f, 0x4000 /* expect 0x0000 */ - divide 0x0000000f, 0x7fff /* expect 0x0000 */ - divide 0x00000010, 0x0001 /* expect 0x0010 */ - divide 0x00000010, 0x0002 /* expect 0x0008 */ - divide 0x00000010, 0x0003 /* expect 0x0005 */ - divide 0x00000010, 0x0004 /* expect 0x0004 */ - divide 0x00000010, 0x0007 /* expect 0x0002 */ - divide 0x00000010, 0x0008 /* expect 0x0002 */ - divide 0x00000010, 0x000f /* expect 0x0001 */ - divide 0x00000010, 0x0010 /* expect 0x0001 */ - divide 0x00000010, 0x001f /* expect 0x0000 */ - divide 0x00000010, 0x0020 /* expect 0x0000 */ - divide 0x00000010, 0x003f /* expect 0x0000 */ - divide 0x00000010, 0x0040 /* expect 0x0000 */ - divide 0x00000010, 0x007f /* expect 0x0000 */ - divide 0x00000010, 0x0080 /* expect 0x0000 */ - divide 0x00000010, 0x00ff /* expect 0x0000 */ - divide 0x00000010, 0x0100 /* expect 0x0000 */ - divide 0x00000010, 0x01ff /* expect 0x0000 */ - divide 0x00000010, 0x0200 /* expect 0x0000 */ - divide 0x00000010, 0x03ff /* expect 0x0000 */ - divide 0x00000010, 0x0400 /* expect 0x0000 */ - divide 0x00000010, 0x07ff /* expect 0x0000 */ - divide 0x00000010, 0x0800 /* expect 0x0000 */ - divide 0x00000010, 0x0fff /* expect 0x0000 */ - divide 0x00000010, 0x1000 /* expect 0x0000 */ - divide 0x00000010, 0x1fff /* expect 0x0000 */ - divide 0x00000010, 0x2000 /* expect 0x0000 */ - divide 0x00000010, 0x3fff /* expect 0x0000 */ - divide 0x00000010, 0x4000 /* expect 0x0000 */ - divide 0x00000010, 0x7fff /* expect 0x0000 */ - divide 0x0000001f, 0x0001 /* expect 0x001f */ - divide 0x0000001f, 0x0002 /* expect 0x000f */ - divide 0x0000001f, 0x0003 /* expect 0x000a */ - divide 0x0000001f, 0x0004 /* expect 0x0007 */ - divide 0x0000001f, 0x0007 /* expect 0x0004 */ - divide 0x0000001f, 0x0008 /* expect 0x0003 */ - divide 0x0000001f, 0x000f /* expect 0x0002 */ - divide 0x0000001f, 0x0010 /* expect 0x0001 */ - divide 0x0000001f, 0x001f /* expect 0x0001 */ - divide 0x0000001f, 0x0020 /* expect 0x0000 */ - divide 0x0000001f, 0x003f /* expect 0x0000 */ - divide 0x0000001f, 0x0040 /* expect 0x0000 */ - divide 0x0000001f, 0x007f /* expect 0x0000 */ - divide 0x0000001f, 0x0080 /* expect 0x0000 */ - divide 0x0000001f, 0x00ff /* expect 0x0000 */ - divide 0x0000001f, 0x0100 /* expect 0x0000 */ - divide 0x0000001f, 0x01ff /* expect 0x0000 */ - divide 0x0000001f, 0x0200 /* expect 0x0000 */ - divide 0x0000001f, 0x03ff /* expect 0x0000 */ - divide 0x0000001f, 0x0400 /* expect 0x0000 */ - divide 0x0000001f, 0x07ff /* expect 0x0000 */ - divide 0x0000001f, 0x0800 /* expect 0x0000 */ - divide 0x0000001f, 0x0fff /* expect 0x0000 */ - divide 0x0000001f, 0x1000 /* expect 0x0000 */ - divide 0x0000001f, 0x1fff /* expect 0x0000 */ - divide 0x0000001f, 0x2000 /* expect 0x0000 */ - divide 0x0000001f, 0x3fff /* expect 0x0000 */ - divide 0x0000001f, 0x4000 /* expect 0x0000 */ - divide 0x0000001f, 0x7fff /* expect 0x0000 */ - divide 0x00000020, 0x0001 /* expect 0x0020 */ - divide 0x00000020, 0x0002 /* expect 0x0010 */ - divide 0x00000020, 0x0003 /* expect 0x000a */ - divide 0x00000020, 0x0004 /* expect 0x0008 */ - divide 0x00000020, 0x0007 /* expect 0x0004 */ - divide 0x00000020, 0x0008 /* expect 0x0004 */ - divide 0x00000020, 0x000f /* expect 0x0002 */ - divide 0x00000020, 0x0010 /* expect 0x0002 */ - divide 0x00000020, 0x001f /* expect 0x0001 */ - divide 0x00000020, 0x0020 /* expect 0x0001 */ - divide 0x00000020, 0x003f /* expect 0x0000 */ - divide 0x00000020, 0x0040 /* expect 0x0000 */ - divide 0x00000020, 0x007f /* expect 0x0000 */ - divide 0x00000020, 0x0080 /* expect 0x0000 */ - divide 0x00000020, 0x00ff /* expect 0x0000 */ - divide 0x00000020, 0x0100 /* expect 0x0000 */ - divide 0x00000020, 0x01ff /* expect 0x0000 */ - divide 0x00000020, 0x0200 /* expect 0x0000 */ - divide 0x00000020, 0x03ff /* expect 0x0000 */ - divide 0x00000020, 0x0400 /* expect 0x0000 */ - divide 0x00000020, 0x07ff /* expect 0x0000 */ - divide 0x00000020, 0x0800 /* expect 0x0000 */ - divide 0x00000020, 0x0fff /* expect 0x0000 */ - divide 0x00000020, 0x1000 /* expect 0x0000 */ - divide 0x00000020, 0x1fff /* expect 0x0000 */ - divide 0x00000020, 0x2000 /* expect 0x0000 */ - divide 0x00000020, 0x3fff /* expect 0x0000 */ - divide 0x00000020, 0x4000 /* expect 0x0000 */ - divide 0x00000020, 0x7fff /* expect 0x0000 */ - divide 0x0000003f, 0x0001 /* expect 0x003f */ - divide 0x0000003f, 0x0002 /* expect 0x001f */ - divide 0x0000003f, 0x0003 /* expect 0x0015 */ - divide 0x0000003f, 0x0004 /* expect 0x000f */ - divide 0x0000003f, 0x0007 /* expect 0x0009 */ - divide 0x0000003f, 0x0008 /* expect 0x0007 */ - divide 0x0000003f, 0x000f /* expect 0x0004 */ - divide 0x0000003f, 0x0010 /* expect 0x0003 */ - divide 0x0000003f, 0x001f /* expect 0x0002 */ - divide 0x0000003f, 0x0020 /* expect 0x0001 */ - divide 0x0000003f, 0x003f /* expect 0x0001 */ - divide 0x0000003f, 0x0040 /* expect 0x0000 */ - divide 0x0000003f, 0x007f /* expect 0x0000 */ - divide 0x0000003f, 0x0080 /* expect 0x0000 */ - divide 0x0000003f, 0x00ff /* expect 0x0000 */ - divide 0x0000003f, 0x0100 /* expect 0x0000 */ - divide 0x0000003f, 0x01ff /* expect 0x0000 */ - divide 0x0000003f, 0x0200 /* expect 0x0000 */ - divide 0x0000003f, 0x03ff /* expect 0x0000 */ - divide 0x0000003f, 0x0400 /* expect 0x0000 */ - divide 0x0000003f, 0x07ff /* expect 0x0000 */ - divide 0x0000003f, 0x0800 /* expect 0x0000 */ - divide 0x0000003f, 0x0fff /* expect 0x0000 */ - divide 0x0000003f, 0x1000 /* expect 0x0000 */ - divide 0x0000003f, 0x1fff /* expect 0x0000 */ - divide 0x0000003f, 0x2000 /* expect 0x0000 */ - divide 0x0000003f, 0x3fff /* expect 0x0000 */ - divide 0x0000003f, 0x4000 /* expect 0x0000 */ - divide 0x0000003f, 0x7fff /* expect 0x0000 */ - divide 0x00000040, 0x0001 /* expect 0x0040 */ - divide 0x00000040, 0x0002 /* expect 0x0020 */ - divide 0x00000040, 0x0003 /* expect 0x0015 */ - divide 0x00000040, 0x0004 /* expect 0x0010 */ - divide 0x00000040, 0x0007 /* expect 0x0009 */ - divide 0x00000040, 0x0008 /* expect 0x0008 */ - divide 0x00000040, 0x000f /* expect 0x0004 */ - divide 0x00000040, 0x0010 /* expect 0x0004 */ - divide 0x00000040, 0x001f /* expect 0x0002 */ - divide 0x00000040, 0x0020 /* expect 0x0002 */ - divide 0x00000040, 0x003f /* expect 0x0001 */ - divide 0x00000040, 0x0040 /* expect 0x0001 */ - divide 0x00000040, 0x007f /* expect 0x0000 */ - divide 0x00000040, 0x0080 /* expect 0x0000 */ - divide 0x00000040, 0x00ff /* expect 0x0000 */ - divide 0x00000040, 0x0100 /* expect 0x0000 */ - divide 0x00000040, 0x01ff /* expect 0x0000 */ - divide 0x00000040, 0x0200 /* expect 0x0000 */ - divide 0x00000040, 0x03ff /* expect 0x0000 */ - divide 0x00000040, 0x0400 /* expect 0x0000 */ - divide 0x00000040, 0x07ff /* expect 0x0000 */ - divide 0x00000040, 0x0800 /* expect 0x0000 */ - divide 0x00000040, 0x0fff /* expect 0x0000 */ - divide 0x00000040, 0x1000 /* expect 0x0000 */ - divide 0x00000040, 0x1fff /* expect 0x0000 */ - divide 0x00000040, 0x2000 /* expect 0x0000 */ - divide 0x00000040, 0x3fff /* expect 0x0000 */ - divide 0x00000040, 0x4000 /* expect 0x0000 */ - divide 0x00000040, 0x7fff /* expect 0x0000 */ - divide 0x0000007f, 0x0001 /* expect 0x007f */ - divide 0x0000007f, 0x0002 /* expect 0x003f */ - divide 0x0000007f, 0x0003 /* expect 0x002a */ - divide 0x0000007f, 0x0004 /* expect 0x001f */ - divide 0x0000007f, 0x0007 /* expect 0x0012 */ - divide 0x0000007f, 0x0008 /* expect 0x000f */ - divide 0x0000007f, 0x000f /* expect 0x0008 */ - divide 0x0000007f, 0x0010 /* expect 0x0007 */ - divide 0x0000007f, 0x001f /* expect 0x0004 */ - divide 0x0000007f, 0x0020 /* expect 0x0003 */ - divide 0x0000007f, 0x003f /* expect 0x0002 */ - divide 0x0000007f, 0x0040 /* expect 0x0001 */ - divide 0x0000007f, 0x007f /* expect 0x0001 */ - divide 0x0000007f, 0x0080 /* expect 0x0000 */ - divide 0x0000007f, 0x00ff /* expect 0x0000 */ - divide 0x0000007f, 0x0100 /* expect 0x0000 */ - divide 0x0000007f, 0x01ff /* expect 0x0000 */ - divide 0x0000007f, 0x0200 /* expect 0x0000 */ - divide 0x0000007f, 0x03ff /* expect 0x0000 */ - divide 0x0000007f, 0x0400 /* expect 0x0000 */ - divide 0x0000007f, 0x07ff /* expect 0x0000 */ - divide 0x0000007f, 0x0800 /* expect 0x0000 */ - divide 0x0000007f, 0x0fff /* expect 0x0000 */ - divide 0x0000007f, 0x1000 /* expect 0x0000 */ - divide 0x0000007f, 0x1fff /* expect 0x0000 */ - divide 0x0000007f, 0x2000 /* expect 0x0000 */ - divide 0x0000007f, 0x3fff /* expect 0x0000 */ - divide 0x0000007f, 0x4000 /* expect 0x0000 */ - divide 0x0000007f, 0x7fff /* expect 0x0000 */ - divide 0x00000080, 0x0001 /* expect 0x0080 */ - divide 0x00000080, 0x0002 /* expect 0x0040 */ - divide 0x00000080, 0x0003 /* expect 0x002a */ - divide 0x00000080, 0x0004 /* expect 0x0020 */ - divide 0x00000080, 0x0007 /* expect 0x0012 */ - divide 0x00000080, 0x0008 /* expect 0x0010 */ - divide 0x00000080, 0x000f /* expect 0x0008 */ - divide 0x00000080, 0x0010 /* expect 0x0008 */ - divide 0x00000080, 0x001f /* expect 0x0004 */ - divide 0x00000080, 0x0020 /* expect 0x0004 */ - divide 0x00000080, 0x003f /* expect 0x0002 */ - divide 0x00000080, 0x0040 /* expect 0x0002 */ - divide 0x00000080, 0x007f /* expect 0x0001 */ - divide 0x00000080, 0x0080 /* expect 0x0001 */ - divide 0x00000080, 0x00ff /* expect 0x0000 */ - divide 0x00000080, 0x0100 /* expect 0x0000 */ - divide 0x00000080, 0x01ff /* expect 0x0000 */ - divide 0x00000080, 0x0200 /* expect 0x0000 */ - divide 0x00000080, 0x03ff /* expect 0x0000 */ - divide 0x00000080, 0x0400 /* expect 0x0000 */ - divide 0x00000080, 0x07ff /* expect 0x0000 */ - divide 0x00000080, 0x0800 /* expect 0x0000 */ - divide 0x00000080, 0x0fff /* expect 0x0000 */ - divide 0x00000080, 0x1000 /* expect 0x0000 */ - divide 0x00000080, 0x1fff /* expect 0x0000 */ - divide 0x00000080, 0x2000 /* expect 0x0000 */ - divide 0x00000080, 0x3fff /* expect 0x0000 */ - divide 0x00000080, 0x4000 /* expect 0x0000 */ - divide 0x00000080, 0x7fff /* expect 0x0000 */ - divide 0x000000ff, 0x0001 /* expect 0x00ff */ - divide 0x000000ff, 0x0002 /* expect 0x007f */ - divide 0x000000ff, 0x0003 /* expect 0x0055 */ - divide 0x000000ff, 0x0004 /* expect 0x003f */ - divide 0x000000ff, 0x0007 /* expect 0x0024 */ - divide 0x000000ff, 0x0008 /* expect 0x001f */ - divide 0x000000ff, 0x000f /* expect 0x0011 */ - divide 0x000000ff, 0x0010 /* expect 0x000f */ - divide 0x000000ff, 0x001f /* expect 0x0008 */ - divide 0x000000ff, 0x0020 /* expect 0x0007 */ - divide 0x000000ff, 0x003f /* expect 0x0004 */ - divide 0x000000ff, 0x0040 /* expect 0x0003 */ - divide 0x000000ff, 0x007f /* expect 0x0002 */ - divide 0x000000ff, 0x0080 /* expect 0x0001 */ - divide 0x000000ff, 0x00ff /* expect 0x0001 */ - divide 0x000000ff, 0x0100 /* expect 0x0000 */ - divide 0x000000ff, 0x01ff /* expect 0x0000 */ - divide 0x000000ff, 0x0200 /* expect 0x0000 */ - divide 0x000000ff, 0x03ff /* expect 0x0000 */ - divide 0x000000ff, 0x0400 /* expect 0x0000 */ - divide 0x000000ff, 0x07ff /* expect 0x0000 */ - divide 0x000000ff, 0x0800 /* expect 0x0000 */ - divide 0x000000ff, 0x0fff /* expect 0x0000 */ - divide 0x000000ff, 0x1000 /* expect 0x0000 */ - divide 0x000000ff, 0x1fff /* expect 0x0000 */ - divide 0x000000ff, 0x2000 /* expect 0x0000 */ - divide 0x000000ff, 0x3fff /* expect 0x0000 */ - divide 0x000000ff, 0x4000 /* expect 0x0000 */ - divide 0x000000ff, 0x7fff /* expect 0x0000 */ - divide 0x00000100, 0x0001 /* expect 0x0100 */ - divide 0x00000100, 0x0002 /* expect 0x0080 */ - divide 0x00000100, 0x0003 /* expect 0x0055 */ - divide 0x00000100, 0x0004 /* expect 0x0040 */ - divide 0x00000100, 0x0007 /* expect 0x0024 */ - divide 0x00000100, 0x0008 /* expect 0x0020 */ - divide 0x00000100, 0x000f /* expect 0x0011 */ - divide 0x00000100, 0x0010 /* expect 0x0010 */ - divide 0x00000100, 0x001f /* expect 0x0008 */ - divide 0x00000100, 0x0020 /* expect 0x0008 */ - divide 0x00000100, 0x003f /* expect 0x0004 */ - divide 0x00000100, 0x0040 /* expect 0x0004 */ - divide 0x00000100, 0x007f /* expect 0x0002 */ - divide 0x00000100, 0x0080 /* expect 0x0002 */ - divide 0x00000100, 0x00ff /* expect 0x0001 */ - divide 0x00000100, 0x0100 /* expect 0x0001 */ - divide 0x00000100, 0x01ff /* expect 0x0000 */ - divide 0x00000100, 0x0200 /* expect 0x0000 */ - divide 0x00000100, 0x03ff /* expect 0x0000 */ - divide 0x00000100, 0x0400 /* expect 0x0000 */ - divide 0x00000100, 0x07ff /* expect 0x0000 */ - divide 0x00000100, 0x0800 /* expect 0x0000 */ - divide 0x00000100, 0x0fff /* expect 0x0000 */ - divide 0x00000100, 0x1000 /* expect 0x0000 */ - divide 0x00000100, 0x1fff /* expect 0x0000 */ - divide 0x00000100, 0x2000 /* expect 0x0000 */ - divide 0x00000100, 0x3fff /* expect 0x0000 */ - divide 0x00000100, 0x4000 /* expect 0x0000 */ - divide 0x00000100, 0x7fff /* expect 0x0000 */ - divide 0x000001ff, 0x0001 /* expect 0x01ff */ - divide 0x000001ff, 0x0002 /* expect 0x00ff */ - divide 0x000001ff, 0x0003 /* expect 0x00aa */ - divide 0x000001ff, 0x0004 /* expect 0x007f */ - divide 0x000001ff, 0x0007 /* expect 0x0049 */ - divide 0x000001ff, 0x0008 /* expect 0x003f */ - divide 0x000001ff, 0x000f /* expect 0x0022 */ - divide 0x000001ff, 0x0010 /* expect 0x001f */ - divide 0x000001ff, 0x001f /* expect 0x0010 */ - divide 0x000001ff, 0x0020 /* expect 0x000f */ - divide 0x000001ff, 0x003f /* expect 0x0008 */ - divide 0x000001ff, 0x0040 /* expect 0x0007 */ - divide 0x000001ff, 0x007f /* expect 0x0004 */ - divide 0x000001ff, 0x0080 /* expect 0x0003 */ - divide 0x000001ff, 0x00ff /* expect 0x0002 */ - divide 0x000001ff, 0x0100 /* expect 0x0001 */ - divide 0x000001ff, 0x01ff /* expect 0x0001 */ - divide 0x000001ff, 0x0200 /* expect 0x0000 */ - divide 0x000001ff, 0x03ff /* expect 0x0000 */ - divide 0x000001ff, 0x0400 /* expect 0x0000 */ - divide 0x000001ff, 0x07ff /* expect 0x0000 */ - divide 0x000001ff, 0x0800 /* expect 0x0000 */ - divide 0x000001ff, 0x0fff /* expect 0x0000 */ - divide 0x000001ff, 0x1000 /* expect 0x0000 */ - divide 0x000001ff, 0x1fff /* expect 0x0000 */ - divide 0x000001ff, 0x2000 /* expect 0x0000 */ - divide 0x000001ff, 0x3fff /* expect 0x0000 */ - divide 0x000001ff, 0x4000 /* expect 0x0000 */ - divide 0x000001ff, 0x7fff /* expect 0x0000 */ - divide 0x00000200, 0x0001 /* expect 0x0200 */ - divide 0x00000200, 0x0002 /* expect 0x0100 */ - divide 0x00000200, 0x0003 /* expect 0x00aa */ - divide 0x00000200, 0x0004 /* expect 0x0080 */ - divide 0x00000200, 0x0007 /* expect 0x0049 */ - divide 0x00000200, 0x0008 /* expect 0x0040 */ - divide 0x00000200, 0x000f /* expect 0x0022 */ - divide 0x00000200, 0x0010 /* expect 0x0020 */ - divide 0x00000200, 0x001f /* expect 0x0010 */ - divide 0x00000200, 0x0020 /* expect 0x0010 */ - divide 0x00000200, 0x003f /* expect 0x0008 */ - divide 0x00000200, 0x0040 /* expect 0x0008 */ - divide 0x00000200, 0x007f /* expect 0x0004 */ - divide 0x00000200, 0x0080 /* expect 0x0004 */ - divide 0x00000200, 0x00ff /* expect 0x0002 */ - divide 0x00000200, 0x0100 /* expect 0x0002 */ - divide 0x00000200, 0x01ff /* expect 0x0001 */ - divide 0x00000200, 0x0200 /* expect 0x0001 */ - divide 0x00000200, 0x03ff /* expect 0x0000 */ - divide 0x00000200, 0x0400 /* expect 0x0000 */ - divide 0x00000200, 0x07ff /* expect 0x0000 */ - divide 0x00000200, 0x0800 /* expect 0x0000 */ - divide 0x00000200, 0x0fff /* expect 0x0000 */ - divide 0x00000200, 0x1000 /* expect 0x0000 */ - divide 0x00000200, 0x1fff /* expect 0x0000 */ - divide 0x00000200, 0x2000 /* expect 0x0000 */ - divide 0x00000200, 0x3fff /* expect 0x0000 */ - divide 0x00000200, 0x4000 /* expect 0x0000 */ - divide 0x00000200, 0x7fff /* expect 0x0000 */ - divide 0x000003ff, 0x0001 /* expect 0x03ff */ - divide 0x000003ff, 0x0002 /* expect 0x01ff */ - divide 0x000003ff, 0x0003 /* expect 0x0155 */ - divide 0x000003ff, 0x0004 /* expect 0x00ff */ - divide 0x000003ff, 0x0007 /* expect 0x0092 */ - divide 0x000003ff, 0x0008 /* expect 0x007f */ - divide 0x000003ff, 0x000f /* expect 0x0044 */ - divide 0x000003ff, 0x0010 /* expect 0x003f */ - divide 0x000003ff, 0x001f /* expect 0x0021 */ - divide 0x000003ff, 0x0020 /* expect 0x001f */ - divide 0x000003ff, 0x003f /* expect 0x0010 */ - divide 0x000003ff, 0x0040 /* expect 0x000f */ - divide 0x000003ff, 0x007f /* expect 0x0008 */ - divide 0x000003ff, 0x0080 /* expect 0x0007 */ - divide 0x000003ff, 0x00ff /* expect 0x0004 */ - divide 0x000003ff, 0x0100 /* expect 0x0003 */ - divide 0x000003ff, 0x01ff /* expect 0x0002 */ - divide 0x000003ff, 0x0200 /* expect 0x0001 */ - divide 0x000003ff, 0x03ff /* expect 0x0001 */ - divide 0x000003ff, 0x0400 /* expect 0x0000 */ - divide 0x000003ff, 0x07ff /* expect 0x0000 */ - divide 0x000003ff, 0x0800 /* expect 0x0000 */ - divide 0x000003ff, 0x0fff /* expect 0x0000 */ - divide 0x000003ff, 0x1000 /* expect 0x0000 */ - divide 0x000003ff, 0x1fff /* expect 0x0000 */ - divide 0x000003ff, 0x2000 /* expect 0x0000 */ - divide 0x000003ff, 0x3fff /* expect 0x0000 */ - divide 0x000003ff, 0x4000 /* expect 0x0000 */ - divide 0x000003ff, 0x7fff /* expect 0x0000 */ - divide 0x00000400, 0x0001 /* expect 0x0400 */ - divide 0x00000400, 0x0002 /* expect 0x0200 */ - divide 0x00000400, 0x0003 /* expect 0x0155 */ - divide 0x00000400, 0x0004 /* expect 0x0100 */ - divide 0x00000400, 0x0007 /* expect 0x0092 */ - divide 0x00000400, 0x0008 /* expect 0x0080 */ - divide 0x00000400, 0x000f /* expect 0x0044 */ - divide 0x00000400, 0x0010 /* expect 0x0040 */ - divide 0x00000400, 0x001f /* expect 0x0021 */ - divide 0x00000400, 0x0020 /* expect 0x0020 */ - divide 0x00000400, 0x003f /* expect 0x0010 */ - divide 0x00000400, 0x0040 /* expect 0x0010 */ - divide 0x00000400, 0x007f /* expect 0x0008 */ - divide 0x00000400, 0x0080 /* expect 0x0008 */ - divide 0x00000400, 0x00ff /* expect 0x0004 */ - divide 0x00000400, 0x0100 /* expect 0x0004 */ - divide 0x00000400, 0x01ff /* expect 0x0002 */ - divide 0x00000400, 0x0200 /* expect 0x0002 */ - divide 0x00000400, 0x03ff /* expect 0x0001 */ - divide 0x00000400, 0x0400 /* expect 0x0001 */ - divide 0x00000400, 0x07ff /* expect 0x0000 */ - divide 0x00000400, 0x0800 /* expect 0x0000 */ - divide 0x00000400, 0x0fff /* expect 0x0000 */ - divide 0x00000400, 0x1000 /* expect 0x0000 */ - divide 0x00000400, 0x1fff /* expect 0x0000 */ - divide 0x00000400, 0x2000 /* expect 0x0000 */ - divide 0x00000400, 0x3fff /* expect 0x0000 */ - divide 0x00000400, 0x4000 /* expect 0x0000 */ - divide 0x00000400, 0x7fff /* expect 0x0000 */ - divide 0x000007ff, 0x0001 /* expect 0x07ff */ - divide 0x000007ff, 0x0002 /* expect 0x03ff */ - divide 0x000007ff, 0x0003 /* expect 0x02aa */ - divide 0x000007ff, 0x0004 /* expect 0x01ff */ - divide 0x000007ff, 0x0007 /* expect 0x0124 */ - divide 0x000007ff, 0x0008 /* expect 0x00ff */ - divide 0x000007ff, 0x000f /* expect 0x0088 */ - divide 0x000007ff, 0x0010 /* expect 0x007f */ - divide 0x000007ff, 0x001f /* expect 0x0042 */ - divide 0x000007ff, 0x0020 /* expect 0x003f */ - divide 0x000007ff, 0x003f /* expect 0x0020 */ - divide 0x000007ff, 0x0040 /* expect 0x001f */ - divide 0x000007ff, 0x007f /* expect 0x0010 */ - divide 0x000007ff, 0x0080 /* expect 0x000f */ - divide 0x000007ff, 0x00ff /* expect 0x0008 */ - divide 0x000007ff, 0x0100 /* expect 0x0007 */ - divide 0x000007ff, 0x01ff /* expect 0x0004 */ - divide 0x000007ff, 0x0200 /* expect 0x0003 */ - divide 0x000007ff, 0x03ff /* expect 0x0002 */ - divide 0x000007ff, 0x0400 /* expect 0x0001 */ - divide 0x000007ff, 0x07ff /* expect 0x0001 */ - divide 0x000007ff, 0x0800 /* expect 0x0000 */ - divide 0x000007ff, 0x0fff /* expect 0x0000 */ - divide 0x000007ff, 0x1000 /* expect 0x0000 */ - divide 0x000007ff, 0x1fff /* expect 0x0000 */ - divide 0x000007ff, 0x2000 /* expect 0x0000 */ - divide 0x000007ff, 0x3fff /* expect 0x0000 */ - divide 0x000007ff, 0x4000 /* expect 0x0000 */ - divide 0x000007ff, 0x7fff /* expect 0x0000 */ - divide 0x00000800, 0x0001 /* expect 0x0800 */ - divide 0x00000800, 0x0002 /* expect 0x0400 */ - divide 0x00000800, 0x0003 /* expect 0x02aa */ - divide 0x00000800, 0x0004 /* expect 0x0200 */ - divide 0x00000800, 0x0007 /* expect 0x0124 */ - divide 0x00000800, 0x0008 /* expect 0x0100 */ - divide 0x00000800, 0x000f /* expect 0x0088 */ - divide 0x00000800, 0x0010 /* expect 0x0080 */ - divide 0x00000800, 0x001f /* expect 0x0042 */ - divide 0x00000800, 0x0020 /* expect 0x0040 */ - divide 0x00000800, 0x003f /* expect 0x0020 */ - divide 0x00000800, 0x0040 /* expect 0x0020 */ - divide 0x00000800, 0x007f /* expect 0x0010 */ - divide 0x00000800, 0x0080 /* expect 0x0010 */ - divide 0x00000800, 0x00ff /* expect 0x0008 */ - divide 0x00000800, 0x0100 /* expect 0x0008 */ - divide 0x00000800, 0x01ff /* expect 0x0004 */ - divide 0x00000800, 0x0200 /* expect 0x0004 */ - divide 0x00000800, 0x03ff /* expect 0x0002 */ - divide 0x00000800, 0x0400 /* expect 0x0002 */ - divide 0x00000800, 0x07ff /* expect 0x0001 */ - divide 0x00000800, 0x0800 /* expect 0x0001 */ - divide 0x00000800, 0x0fff /* expect 0x0000 */ - divide 0x00000800, 0x1000 /* expect 0x0000 */ - divide 0x00000800, 0x1fff /* expect 0x0000 */ - divide 0x00000800, 0x2000 /* expect 0x0000 */ - divide 0x00000800, 0x3fff /* expect 0x0000 */ - divide 0x00000800, 0x4000 /* expect 0x0000 */ - divide 0x00000800, 0x7fff /* expect 0x0000 */ - divide 0x00000fff, 0x0001 /* expect 0x0fff */ - divide 0x00000fff, 0x0002 /* expect 0x07ff */ - divide 0x00000fff, 0x0003 /* expect 0x0555 */ - divide 0x00000fff, 0x0004 /* expect 0x03ff */ - divide 0x00000fff, 0x0007 /* expect 0x0249 */ - divide 0x00000fff, 0x0008 /* expect 0x01ff */ - divide 0x00000fff, 0x000f /* expect 0x0111 */ - divide 0x00000fff, 0x0010 /* expect 0x00ff */ - divide 0x00000fff, 0x001f /* expect 0x0084 */ - divide 0x00000fff, 0x0020 /* expect 0x007f */ - divide 0x00000fff, 0x003f /* expect 0x0041 */ - divide 0x00000fff, 0x0040 /* expect 0x003f */ - divide 0x00000fff, 0x007f /* expect 0x0020 */ - divide 0x00000fff, 0x0080 /* expect 0x001f */ - divide 0x00000fff, 0x00ff /* expect 0x0010 */ - divide 0x00000fff, 0x0100 /* expect 0x000f */ - divide 0x00000fff, 0x01ff /* expect 0x0008 */ - divide 0x00000fff, 0x0200 /* expect 0x0007 */ - divide 0x00000fff, 0x03ff /* expect 0x0004 */ - divide 0x00000fff, 0x0400 /* expect 0x0003 */ - divide 0x00000fff, 0x07ff /* expect 0x0002 */ - divide 0x00000fff, 0x0800 /* expect 0x0001 */ - divide 0x00000fff, 0x0fff /* expect 0x0001 */ - divide 0x00000fff, 0x1000 /* expect 0x0000 */ - divide 0x00000fff, 0x1fff /* expect 0x0000 */ - divide 0x00000fff, 0x2000 /* expect 0x0000 */ - divide 0x00000fff, 0x3fff /* expect 0x0000 */ - divide 0x00000fff, 0x4000 /* expect 0x0000 */ - divide 0x00000fff, 0x7fff /* expect 0x0000 */ - divide 0x00001000, 0x0001 /* expect 0x1000 */ - divide 0x00001000, 0x0002 /* expect 0x0800 */ - divide 0x00001000, 0x0003 /* expect 0x0555 */ - divide 0x00001000, 0x0004 /* expect 0x0400 */ - divide 0x00001000, 0x0007 /* expect 0x0249 */ - divide 0x00001000, 0x0008 /* expect 0x0200 */ - divide 0x00001000, 0x000f /* expect 0x0111 */ - divide 0x00001000, 0x0010 /* expect 0x0100 */ - divide 0x00001000, 0x001f /* expect 0x0084 */ - divide 0x00001000, 0x0020 /* expect 0x0080 */ - divide 0x00001000, 0x003f /* expect 0x0041 */ - divide 0x00001000, 0x0040 /* expect 0x0040 */ - divide 0x00001000, 0x007f /* expect 0x0020 */ - divide 0x00001000, 0x0080 /* expect 0x0020 */ - divide 0x00001000, 0x00ff /* expect 0x0010 */ - divide 0x00001000, 0x0100 /* expect 0x0010 */ - divide 0x00001000, 0x01ff /* expect 0x0008 */ - divide 0x00001000, 0x0200 /* expect 0x0008 */ - divide 0x00001000, 0x03ff /* expect 0x0004 */ - divide 0x00001000, 0x0400 /* expect 0x0004 */ - divide 0x00001000, 0x07ff /* expect 0x0002 */ - divide 0x00001000, 0x0800 /* expect 0x0002 */ - divide 0x00001000, 0x0fff /* expect 0x0001 */ - divide 0x00001000, 0x1000 /* expect 0x0001 */ - divide 0x00001000, 0x1fff /* expect 0x0000 */ - divide 0x00001000, 0x2000 /* expect 0x0000 */ - divide 0x00001000, 0x3fff /* expect 0x0000 */ - divide 0x00001000, 0x4000 /* expect 0x0000 */ - divide 0x00001000, 0x7fff /* expect 0x0000 */ - divide 0x00001fff, 0x0001 /* expect 0x1fff */ - divide 0x00001fff, 0x0002 /* expect 0x0fff */ - divide 0x00001fff, 0x0003 /* expect 0x0aaa */ - divide 0x00001fff, 0x0004 /* expect 0x07ff */ - divide 0x00001fff, 0x0007 /* expect 0x0492 */ - divide 0x00001fff, 0x0008 /* expect 0x03ff */ - divide 0x00001fff, 0x000f /* expect 0x0222 */ - divide 0x00001fff, 0x0010 /* expect 0x01ff */ - divide 0x00001fff, 0x001f /* expect 0x0108 */ - divide 0x00001fff, 0x0020 /* expect 0x00ff */ - divide 0x00001fff, 0x003f /* expect 0x0082 */ - divide 0x00001fff, 0x0040 /* expect 0x007f */ - divide 0x00001fff, 0x007f /* expect 0x0040 */ - divide 0x00001fff, 0x0080 /* expect 0x003f */ - divide 0x00001fff, 0x00ff /* expect 0x0020 */ - divide 0x00001fff, 0x0100 /* expect 0x001f */ - divide 0x00001fff, 0x01ff /* expect 0x0010 */ - divide 0x00001fff, 0x0200 /* expect 0x000f */ - divide 0x00001fff, 0x03ff /* expect 0x0008 */ - divide 0x00001fff, 0x0400 /* expect 0x0007 */ - divide 0x00001fff, 0x07ff /* expect 0x0004 */ - divide 0x00001fff, 0x0800 /* expect 0x0003 */ - divide 0x00001fff, 0x0fff /* expect 0x0002 */ - divide 0x00001fff, 0x1000 /* expect 0x0001 */ - divide 0x00001fff, 0x1fff /* expect 0x0001 */ - divide 0x00001fff, 0x2000 /* expect 0x0000 */ - divide 0x00001fff, 0x3fff /* expect 0x0000 */ - divide 0x00001fff, 0x4000 /* expect 0x0000 */ - divide 0x00001fff, 0x7fff /* expect 0x0000 */ - divide 0x00002000, 0x0001 /* expect 0x2000 */ - divide 0x00002000, 0x0002 /* expect 0x1000 */ - divide 0x00002000, 0x0003 /* expect 0x0aaa */ - divide 0x00002000, 0x0004 /* expect 0x0800 */ - divide 0x00002000, 0x0007 /* expect 0x0492 */ - divide 0x00002000, 0x0008 /* expect 0x0400 */ - divide 0x00002000, 0x000f /* expect 0x0222 */ - divide 0x00002000, 0x0010 /* expect 0x0200 */ - divide 0x00002000, 0x001f /* expect 0x0108 */ - divide 0x00002000, 0x0020 /* expect 0x0100 */ - divide 0x00002000, 0x003f /* expect 0x0082 */ - divide 0x00002000, 0x0040 /* expect 0x0080 */ - divide 0x00002000, 0x007f /* expect 0x0040 */ - divide 0x00002000, 0x0080 /* expect 0x0040 */ - divide 0x00002000, 0x00ff /* expect 0x0020 */ - divide 0x00002000, 0x0100 /* expect 0x0020 */ - divide 0x00002000, 0x01ff /* expect 0x0010 */ - divide 0x00002000, 0x0200 /* expect 0x0010 */ - divide 0x00002000, 0x03ff /* expect 0x0008 */ - divide 0x00002000, 0x0400 /* expect 0x0008 */ - divide 0x00002000, 0x07ff /* expect 0x0004 */ - divide 0x00002000, 0x0800 /* expect 0x0004 */ - divide 0x00002000, 0x0fff /* expect 0x0002 */ - divide 0x00002000, 0x1000 /* expect 0x0002 */ - divide 0x00002000, 0x1fff /* expect 0x0001 */ - divide 0x00002000, 0x2000 /* expect 0x0001 */ - divide 0x00002000, 0x3fff /* expect 0x0000 */ - divide 0x00002000, 0x4000 /* expect 0x0000 */ - divide 0x00002000, 0x7fff /* expect 0x0000 */ - divide 0x00003fff, 0x0001 /* expect 0x3fff */ - divide 0x00003fff, 0x0002 /* expect 0x1fff */ - divide 0x00003fff, 0x0003 /* expect 0x1555 */ - divide 0x00003fff, 0x0004 /* expect 0x0fff */ - divide 0x00003fff, 0x0007 /* expect 0x0924 */ - divide 0x00003fff, 0x0008 /* expect 0x07ff */ - divide 0x00003fff, 0x000f /* expect 0x0444 */ - divide 0x00003fff, 0x0010 /* expect 0x03ff */ - divide 0x00003fff, 0x001f /* expect 0x0210 */ - divide 0x00003fff, 0x0020 /* expect 0x01ff */ - divide 0x00003fff, 0x003f /* expect 0x0104 */ - divide 0x00003fff, 0x0040 /* expect 0x00ff */ - divide 0x00003fff, 0x007f /* expect 0x0081 */ - divide 0x00003fff, 0x0080 /* expect 0x007f */ - divide 0x00003fff, 0x00ff /* expect 0x0040 */ - divide 0x00003fff, 0x0100 /* expect 0x003f */ - divide 0x00003fff, 0x01ff /* expect 0x0020 */ - divide 0x00003fff, 0x0200 /* expect 0x001f */ - divide 0x00003fff, 0x03ff /* expect 0x0010 */ - divide 0x00003fff, 0x0400 /* expect 0x000f */ - divide 0x00003fff, 0x07ff /* expect 0x0008 */ - divide 0x00003fff, 0x0800 /* expect 0x0007 */ - divide 0x00003fff, 0x0fff /* expect 0x0004 */ - divide 0x00003fff, 0x1000 /* expect 0x0003 */ - divide 0x00003fff, 0x1fff /* expect 0x0002 */ - divide 0x00003fff, 0x2000 /* expect 0x0001 */ - divide 0x00003fff, 0x3fff /* expect 0x0001 */ - divide 0x00003fff, 0x4000 /* expect 0x0000 */ - divide 0x00003fff, 0x7fff /* expect 0x0000 */ - divide 0x00004000, 0x0001 /* expect 0x4000 */ - divide 0x00004000, 0x0002 /* expect 0x2000 */ - divide 0x00004000, 0x0003 /* expect 0x1555 */ - divide 0x00004000, 0x0004 /* expect 0x1000 */ - divide 0x00004000, 0x0007 /* expect 0x0924 */ - divide 0x00004000, 0x0008 /* expect 0x0800 */ - divide 0x00004000, 0x000f /* expect 0x0444 */ - divide 0x00004000, 0x0010 /* expect 0x0400 */ - divide 0x00004000, 0x001f /* expect 0x0210 */ - divide 0x00004000, 0x0020 /* expect 0x0200 */ - divide 0x00004000, 0x003f /* expect 0x0104 */ - divide 0x00004000, 0x0040 /* expect 0x0100 */ - divide 0x00004000, 0x007f /* expect 0x0081 */ - divide 0x00004000, 0x0080 /* expect 0x0080 */ - divide 0x00004000, 0x00ff /* expect 0x0040 */ - divide 0x00004000, 0x0100 /* expect 0x0040 */ - divide 0x00004000, 0x01ff /* expect 0x0020 */ - divide 0x00004000, 0x0200 /* expect 0x0020 */ - divide 0x00004000, 0x03ff /* expect 0x0010 */ - divide 0x00004000, 0x0400 /* expect 0x0010 */ - divide 0x00004000, 0x07ff /* expect 0x0008 */ - divide 0x00004000, 0x0800 /* expect 0x0008 */ - divide 0x00004000, 0x0fff /* expect 0x0004 */ - divide 0x00004000, 0x1000 /* expect 0x0004 */ - divide 0x00004000, 0x1fff /* expect 0x0002 */ - divide 0x00004000, 0x2000 /* expect 0x0002 */ - divide 0x00004000, 0x3fff /* expect 0x0001 */ - divide 0x00004000, 0x4000 /* expect 0x0001 */ - divide 0x00004000, 0x7fff /* expect 0x0000 */ - divide 0x00007fff, 0x0001 /* expect 0x7fff */ - divide 0x00007fff, 0x0002 /* expect 0x3fff */ - divide 0x00007fff, 0x0003 /* expect 0x2aaa */ - divide 0x00007fff, 0x0004 /* expect 0x1fff */ - divide 0x00007fff, 0x0007 /* expect 0x1249 */ - divide 0x00007fff, 0x0008 /* expect 0x0fff */ - divide 0x00007fff, 0x000f /* expect 0x0888 */ - divide 0x00007fff, 0x0010 /* expect 0x07ff */ - divide 0x00007fff, 0x001f /* expect 0x0421 */ - divide 0x00007fff, 0x0020 /* expect 0x03ff */ - divide 0x00007fff, 0x003f /* expect 0x0208 */ - divide 0x00007fff, 0x0040 /* expect 0x01ff */ - divide 0x00007fff, 0x007f /* expect 0x0102 */ - divide 0x00007fff, 0x0080 /* expect 0x00ff */ - divide 0x00007fff, 0x00ff /* expect 0x0080 */ - divide 0x00007fff, 0x0100 /* expect 0x007f */ - divide 0x00007fff, 0x01ff /* expect 0x0040 */ - divide 0x00007fff, 0x0200 /* expect 0x003f */ - divide 0x00007fff, 0x03ff /* expect 0x0020 */ - divide 0x00007fff, 0x0400 /* expect 0x001f */ - divide 0x00007fff, 0x07ff /* expect 0x0010 */ - divide 0x00007fff, 0x0800 /* expect 0x000f */ - divide 0x00007fff, 0x0fff /* expect 0x0008 */ - divide 0x00007fff, 0x1000 /* expect 0x0007 */ - divide 0x00007fff, 0x1fff /* expect 0x0004 */ - divide 0x00007fff, 0x2000 /* expect 0x0003 */ - divide 0x00007fff, 0x3fff /* expect 0x0002 */ - divide 0x00007fff, 0x4000 /* expect 0x0001 */ - divide 0x00007fff, 0x7fff /* expect 0x0001 */ - divide 0x00008000, 0x0002 /* expect 0x4000 */ - divide 0x00008000, 0x0003 /* expect 0x2aaa */ - divide 0x00008000, 0x0004 /* expect 0x2000 */ - divide 0x00008000, 0x0007 /* expect 0x1249 */ - divide 0x00008000, 0x0008 /* expect 0x1000 */ - divide 0x00008000, 0x000f /* expect 0x0888 */ - divide 0x00008000, 0x0010 /* expect 0x0800 */ - divide 0x00008000, 0x001f /* expect 0x0421 */ - divide 0x00008000, 0x0020 /* expect 0x0400 */ - divide 0x00008000, 0x003f /* expect 0x0208 */ - divide 0x00008000, 0x0040 /* expect 0x0200 */ - divide 0x00008000, 0x007f /* expect 0x0102 */ - divide 0x00008000, 0x0080 /* expect 0x0100 */ - divide 0x00008000, 0x00ff /* expect 0x0080 */ - divide 0x00008000, 0x0100 /* expect 0x0080 */ - divide 0x00008000, 0x01ff /* expect 0x0040 */ - divide 0x00008000, 0x0200 /* expect 0x0040 */ - divide 0x00008000, 0x03ff /* expect 0x0020 */ - divide 0x00008000, 0x0400 /* expect 0x0020 */ - divide 0x00008000, 0x07ff /* expect 0x0010 */ - divide 0x00008000, 0x0800 /* expect 0x0010 */ - divide 0x00008000, 0x0fff /* expect 0x0008 */ - divide 0x00008000, 0x1000 /* expect 0x0008 */ - divide 0x00008000, 0x1fff /* expect 0x0004 */ - divide 0x00008000, 0x2000 /* expect 0x0004 */ - divide 0x00008000, 0x3fff /* expect 0x0002 */ - divide 0x00008000, 0x4000 /* expect 0x0002 */ - divide 0x00008000, 0x7fff /* expect 0x0001 */ - divide 0x0000ffff, 0x0002 /* expect 0x7fff */ - divide 0x0000ffff, 0x0003 /* expect 0x5555 */ - divide 0x0000ffff, 0x0004 /* expect 0x3fff */ - divide 0x0000ffff, 0x0007 /* expect 0x2492 */ - divide 0x0000ffff, 0x0008 /* expect 0x1fff */ - divide 0x0000ffff, 0x000f /* expect 0x1111 */ - divide 0x0000ffff, 0x0010 /* expect 0x0fff */ - divide 0x0000ffff, 0x001f /* expect 0x0842 */ - divide 0x0000ffff, 0x0020 /* expect 0x07ff */ - divide 0x0000ffff, 0x003f /* expect 0x0410 */ - divide 0x0000ffff, 0x0040 /* expect 0x03ff */ - divide 0x0000ffff, 0x007f /* expect 0x0204 */ - divide 0x0000ffff, 0x0080 /* expect 0x01ff */ - divide 0x0000ffff, 0x00ff /* expect 0x0101 */ - divide 0x0000ffff, 0x0100 /* expect 0x00ff */ - divide 0x0000ffff, 0x01ff /* expect 0x0080 */ - divide 0x0000ffff, 0x0200 /* expect 0x007f */ - divide 0x0000ffff, 0x03ff /* expect 0x0040 */ - divide 0x0000ffff, 0x0400 /* expect 0x003f */ - divide 0x0000ffff, 0x07ff /* expect 0x0020 */ - divide 0x0000ffff, 0x0800 /* expect 0x001f */ - divide 0x0000ffff, 0x0fff /* expect 0x0010 */ - divide 0x0000ffff, 0x1000 /* expect 0x000f */ - divide 0x0000ffff, 0x1fff /* expect 0x0008 */ - divide 0x0000ffff, 0x2000 /* expect 0x0007 */ - divide 0x0000ffff, 0x3fff /* expect 0x0004 */ - divide 0x0000ffff, 0x4000 /* expect 0x0003 */ - divide 0x0000ffff, 0x7fff /* expect 0x0002 */ - divide 0x00010000, 0x0003 /* expect 0x5555 */ - divide 0x00010000, 0x0004 /* expect 0x4000 */ - divide 0x00010000, 0x0007 /* expect 0x2492 */ - divide 0x00010000, 0x0008 /* expect 0x2000 */ - divide 0x00010000, 0x000f /* expect 0x1111 */ - divide 0x00010000, 0x0010 /* expect 0x1000 */ - divide 0x00010000, 0x001f /* expect 0x0842 */ - divide 0x00010000, 0x0020 /* expect 0x0800 */ - divide 0x00010000, 0x003f /* expect 0x0410 */ - divide 0x00010000, 0x0040 /* expect 0x0400 */ - divide 0x00010000, 0x007f /* expect 0x0204 */ - divide 0x00010000, 0x0080 /* expect 0x0200 */ - divide 0x00010000, 0x00ff /* expect 0x0101 */ - divide 0x00010000, 0x0100 /* expect 0x0100 */ - divide 0x00010000, 0x01ff /* expect 0x0080 */ - divide 0x00010000, 0x0200 /* expect 0x0080 */ - divide 0x00010000, 0x03ff /* expect 0x0040 */ - divide 0x00010000, 0x0400 /* expect 0x0040 */ - divide 0x00010000, 0x07ff /* expect 0x0020 */ - divide 0x00010000, 0x0800 /* expect 0x0020 */ - divide 0x00010000, 0x0fff /* expect 0x0010 */ - divide 0x00010000, 0x1000 /* expect 0x0010 */ - divide 0x00010000, 0x1fff /* expect 0x0008 */ - divide 0x00010000, 0x2000 /* expect 0x0008 */ - divide 0x00010000, 0x3fff /* expect 0x0004 */ - divide 0x00010000, 0x4000 /* expect 0x0004 */ - divide 0x00010000, 0x7fff /* expect 0x0002 */ - divide 0x0001ffff, 0x0004 /* expect 0x7fff */ - divide 0x0001ffff, 0x0007 /* expect 0x4924 */ - divide 0x0001ffff, 0x0008 /* expect 0x3fff */ - divide 0x0001ffff, 0x000f /* expect 0x2222 */ - divide 0x0001ffff, 0x0010 /* expect 0x1fff */ - divide 0x0001ffff, 0x001f /* expect 0x1084 */ - divide 0x0001ffff, 0x0020 /* expect 0x0fff */ - divide 0x0001ffff, 0x003f /* expect 0x0820 */ - divide 0x0001ffff, 0x0040 /* expect 0x07ff */ - divide 0x0001ffff, 0x007f /* expect 0x0408 */ - divide 0x0001ffff, 0x0080 /* expect 0x03ff */ - divide 0x0001ffff, 0x00ff /* expect 0x0202 */ - divide 0x0001ffff, 0x0100 /* expect 0x01ff */ - divide 0x0001ffff, 0x01ff /* expect 0x0100 */ - divide 0x0001ffff, 0x0200 /* expect 0x00ff */ - divide 0x0001ffff, 0x03ff /* expect 0x0080 */ - divide 0x0001ffff, 0x0400 /* expect 0x007f */ - divide 0x0001ffff, 0x07ff /* expect 0x0040 */ - divide 0x0001ffff, 0x0800 /* expect 0x003f */ - divide 0x0001ffff, 0x0fff /* expect 0x0020 */ - divide 0x0001ffff, 0x1000 /* expect 0x001f */ - divide 0x0001ffff, 0x1fff /* expect 0x0010 */ - divide 0x0001ffff, 0x2000 /* expect 0x000f */ - divide 0x0001ffff, 0x3fff /* expect 0x0008 */ - divide 0x0001ffff, 0x4000 /* expect 0x0007 */ - divide 0x0001ffff, 0x7fff /* expect 0x0004 */ - divide 0x00020000, 0x0007 /* expect 0x4924 */ - divide 0x00020000, 0x0008 /* expect 0x4000 */ - divide 0x00020000, 0x000f /* expect 0x2222 */ - divide 0x00020000, 0x0010 /* expect 0x2000 */ - divide 0x00020000, 0x001f /* expect 0x1084 */ - divide 0x00020000, 0x0020 /* expect 0x1000 */ - divide 0x00020000, 0x003f /* expect 0x0820 */ - divide 0x00020000, 0x0040 /* expect 0x0800 */ - divide 0x00020000, 0x007f /* expect 0x0408 */ - divide 0x00020000, 0x0080 /* expect 0x0400 */ - divide 0x00020000, 0x00ff /* expect 0x0202 */ - divide 0x00020000, 0x0100 /* expect 0x0200 */ - divide 0x00020000, 0x01ff /* expect 0x0100 */ - divide 0x00020000, 0x0200 /* expect 0x0100 */ - divide 0x00020000, 0x03ff /* expect 0x0080 */ - divide 0x00020000, 0x0400 /* expect 0x0080 */ - divide 0x00020000, 0x07ff /* expect 0x0040 */ - divide 0x00020000, 0x0800 /* expect 0x0040 */ - divide 0x00020000, 0x0fff /* expect 0x0020 */ - divide 0x00020000, 0x1000 /* expect 0x0020 */ - divide 0x00020000, 0x1fff /* expect 0x0010 */ - divide 0x00020000, 0x2000 /* expect 0x0010 */ - divide 0x00020000, 0x3fff /* expect 0x0008 */ - divide 0x00020000, 0x4000 /* expect 0x0008 */ - divide 0x00020000, 0x7fff /* expect 0x0004 */ - divide 0x0003ffff, 0x0008 /* expect 0x7fff */ - divide 0x0003ffff, 0x000f /* expect 0x4444 */ - divide 0x0003ffff, 0x0010 /* expect 0x3fff */ - divide 0x0003ffff, 0x001f /* expect 0x2108 */ - divide 0x0003ffff, 0x0020 /* expect 0x1fff */ - divide 0x0003ffff, 0x003f /* expect 0x1041 */ - divide 0x0003ffff, 0x0040 /* expect 0x0fff */ - divide 0x0003ffff, 0x007f /* expect 0x0810 */ - divide 0x0003ffff, 0x0080 /* expect 0x07ff */ - divide 0x0003ffff, 0x00ff /* expect 0x0404 */ - divide 0x0003ffff, 0x0100 /* expect 0x03ff */ - divide 0x0003ffff, 0x01ff /* expect 0x0201 */ - divide 0x0003ffff, 0x0200 /* expect 0x01ff */ - divide 0x0003ffff, 0x03ff /* expect 0x0100 */ - divide 0x0003ffff, 0x0400 /* expect 0x00ff */ - divide 0x0003ffff, 0x07ff /* expect 0x0080 */ - divide 0x0003ffff, 0x0800 /* expect 0x007f */ - divide 0x0003ffff, 0x0fff /* expect 0x0040 */ - divide 0x0003ffff, 0x1000 /* expect 0x003f */ - divide 0x0003ffff, 0x1fff /* expect 0x0020 */ - divide 0x0003ffff, 0x2000 /* expect 0x001f */ - divide 0x0003ffff, 0x3fff /* expect 0x0010 */ - divide 0x0003ffff, 0x4000 /* expect 0x000f */ - divide 0x0003ffff, 0x7fff /* expect 0x0008 */ - divide 0x00040000, 0x000f /* expect 0x4444 */ - divide 0x00040000, 0x0010 /* expect 0x4000 */ - divide 0x00040000, 0x001f /* expect 0x2108 */ - divide 0x00040000, 0x0020 /* expect 0x2000 */ - divide 0x00040000, 0x003f /* expect 0x1041 */ - divide 0x00040000, 0x0040 /* expect 0x1000 */ - divide 0x00040000, 0x007f /* expect 0x0810 */ - divide 0x00040000, 0x0080 /* expect 0x0800 */ - divide 0x00040000, 0x00ff /* expect 0x0404 */ - divide 0x00040000, 0x0100 /* expect 0x0400 */ - divide 0x00040000, 0x01ff /* expect 0x0201 */ - divide 0x00040000, 0x0200 /* expect 0x0200 */ - divide 0x00040000, 0x03ff /* expect 0x0100 */ - divide 0x00040000, 0x0400 /* expect 0x0100 */ - divide 0x00040000, 0x07ff /* expect 0x0080 */ - divide 0x00040000, 0x0800 /* expect 0x0080 */ - divide 0x00040000, 0x0fff /* expect 0x0040 */ - divide 0x00040000, 0x1000 /* expect 0x0040 */ - divide 0x00040000, 0x1fff /* expect 0x0020 */ - divide 0x00040000, 0x2000 /* expect 0x0020 */ - divide 0x00040000, 0x3fff /* expect 0x0010 */ - divide 0x00040000, 0x4000 /* expect 0x0010 */ - divide 0x00040000, 0x7fff /* expect 0x0008 */ - divide 0x0007ffff, 0x0010 /* expect 0x7fff */ - divide 0x0007ffff, 0x001f /* expect 0x4210 */ - divide 0x0007ffff, 0x0020 /* expect 0x3fff */ - divide 0x0007ffff, 0x003f /* expect 0x2082 */ - divide 0x0007ffff, 0x0040 /* expect 0x1fff */ - divide 0x0007ffff, 0x007f /* expect 0x1020 */ - divide 0x0007ffff, 0x0080 /* expect 0x0fff */ - divide 0x0007ffff, 0x00ff /* expect 0x0808 */ - divide 0x0007ffff, 0x0100 /* expect 0x07ff */ - divide 0x0007ffff, 0x01ff /* expect 0x0402 */ - divide 0x0007ffff, 0x0200 /* expect 0x03ff */ - divide 0x0007ffff, 0x03ff /* expect 0x0200 */ - divide 0x0007ffff, 0x0400 /* expect 0x01ff */ - divide 0x0007ffff, 0x07ff /* expect 0x0100 */ - divide 0x0007ffff, 0x0800 /* expect 0x00ff */ - divide 0x0007ffff, 0x0fff /* expect 0x0080 */ - divide 0x0007ffff, 0x1000 /* expect 0x007f */ - divide 0x0007ffff, 0x1fff /* expect 0x0040 */ - divide 0x0007ffff, 0x2000 /* expect 0x003f */ - divide 0x0007ffff, 0x3fff /* expect 0x0020 */ - divide 0x0007ffff, 0x4000 /* expect 0x001f */ - divide 0x0007ffff, 0x7fff /* expect 0x0010 */ - divide 0x00080000, 0x001f /* expect 0x4210 */ - divide 0x00080000, 0x0020 /* expect 0x4000 */ - divide 0x00080000, 0x003f /* expect 0x2082 */ - divide 0x00080000, 0x0040 /* expect 0x2000 */ - divide 0x00080000, 0x007f /* expect 0x1020 */ - divide 0x00080000, 0x0080 /* expect 0x1000 */ - divide 0x00080000, 0x00ff /* expect 0x0808 */ - divide 0x00080000, 0x0100 /* expect 0x0800 */ - divide 0x00080000, 0x01ff /* expect 0x0402 */ - divide 0x00080000, 0x0200 /* expect 0x0400 */ - divide 0x00080000, 0x03ff /* expect 0x0200 */ - divide 0x00080000, 0x0400 /* expect 0x0200 */ - divide 0x00080000, 0x07ff /* expect 0x0100 */ - divide 0x00080000, 0x0800 /* expect 0x0100 */ - divide 0x00080000, 0x0fff /* expect 0x0080 */ - divide 0x00080000, 0x1000 /* expect 0x0080 */ - divide 0x00080000, 0x1fff /* expect 0x0040 */ - divide 0x00080000, 0x2000 /* expect 0x0040 */ - divide 0x00080000, 0x3fff /* expect 0x0020 */ - divide 0x00080000, 0x4000 /* expect 0x0020 */ - divide 0x00080000, 0x7fff /* expect 0x0010 */ - divide 0x000fffff, 0x0020 /* expect 0x7fff */ - divide 0x000fffff, 0x003f /* expect 0x4104 */ - divide 0x000fffff, 0x0040 /* expect 0x3fff */ - divide 0x000fffff, 0x007f /* expect 0x2040 */ - divide 0x000fffff, 0x0080 /* expect 0x1fff */ - divide 0x000fffff, 0x00ff /* expect 0x1010 */ - divide 0x000fffff, 0x0100 /* expect 0x0fff */ - divide 0x000fffff, 0x01ff /* expect 0x0804 */ - divide 0x000fffff, 0x0200 /* expect 0x07ff */ - divide 0x000fffff, 0x03ff /* expect 0x0401 */ - divide 0x000fffff, 0x0400 /* expect 0x03ff */ - divide 0x000fffff, 0x07ff /* expect 0x0200 */ - divide 0x000fffff, 0x0800 /* expect 0x01ff */ - divide 0x000fffff, 0x0fff /* expect 0x0100 */ - divide 0x000fffff, 0x1000 /* expect 0x00ff */ - divide 0x000fffff, 0x1fff /* expect 0x0080 */ - divide 0x000fffff, 0x2000 /* expect 0x007f */ - divide 0x000fffff, 0x3fff /* expect 0x0040 */ - divide 0x000fffff, 0x4000 /* expect 0x003f */ - divide 0x000fffff, 0x7fff /* expect 0x0020 */ - divide 0x00100000, 0x003f /* expect 0x4104 */ - divide 0x00100000, 0x0040 /* expect 0x4000 */ - divide 0x00100000, 0x007f /* expect 0x2040 */ - divide 0x00100000, 0x0080 /* expect 0x2000 */ - divide 0x00100000, 0x00ff /* expect 0x1010 */ - divide 0x00100000, 0x0100 /* expect 0x1000 */ - divide 0x00100000, 0x01ff /* expect 0x0804 */ - divide 0x00100000, 0x0200 /* expect 0x0800 */ - divide 0x00100000, 0x03ff /* expect 0x0401 */ - divide 0x00100000, 0x0400 /* expect 0x0400 */ - divide 0x00100000, 0x07ff /* expect 0x0200 */ - divide 0x00100000, 0x0800 /* expect 0x0200 */ - divide 0x00100000, 0x0fff /* expect 0x0100 */ - divide 0x00100000, 0x1000 /* expect 0x0100 */ - divide 0x00100000, 0x1fff /* expect 0x0080 */ - divide 0x00100000, 0x2000 /* expect 0x0080 */ - divide 0x00100000, 0x3fff /* expect 0x0040 */ - divide 0x00100000, 0x4000 /* expect 0x0040 */ - divide 0x00100000, 0x7fff /* expect 0x0020 */ - divide 0x001fffff, 0x0040 /* expect 0x7fff */ - divide 0x001fffff, 0x007f /* expect 0x4081 */ - divide 0x001fffff, 0x0080 /* expect 0x3fff */ - divide 0x001fffff, 0x00ff /* expect 0x2020 */ - divide 0x001fffff, 0x0100 /* expect 0x1fff */ - divide 0x001fffff, 0x01ff /* expect 0x1008 */ - divide 0x001fffff, 0x0200 /* expect 0x0fff */ - divide 0x001fffff, 0x03ff /* expect 0x0802 */ - divide 0x001fffff, 0x0400 /* expect 0x07ff */ - divide 0x001fffff, 0x07ff /* expect 0x0400 */ - divide 0x001fffff, 0x0800 /* expect 0x03ff */ - divide 0x001fffff, 0x0fff /* expect 0x0200 */ - divide 0x001fffff, 0x1000 /* expect 0x01ff */ - divide 0x001fffff, 0x1fff /* expect 0x0100 */ - divide 0x001fffff, 0x2000 /* expect 0x00ff */ - divide 0x001fffff, 0x3fff /* expect 0x0080 */ - divide 0x001fffff, 0x4000 /* expect 0x007f */ - divide 0x001fffff, 0x7fff /* expect 0x0040 */ - divide 0x00200000, 0x007f /* expect 0x4081 */ - divide 0x00200000, 0x0080 /* expect 0x4000 */ - divide 0x00200000, 0x00ff /* expect 0x2020 */ - divide 0x00200000, 0x0100 /* expect 0x2000 */ - divide 0x00200000, 0x01ff /* expect 0x1008 */ - divide 0x00200000, 0x0200 /* expect 0x1000 */ - divide 0x00200000, 0x03ff /* expect 0x0802 */ - divide 0x00200000, 0x0400 /* expect 0x0800 */ - divide 0x00200000, 0x07ff /* expect 0x0400 */ - divide 0x00200000, 0x0800 /* expect 0x0400 */ - divide 0x00200000, 0x0fff /* expect 0x0200 */ - divide 0x00200000, 0x1000 /* expect 0x0200 */ - divide 0x00200000, 0x1fff /* expect 0x0100 */ - divide 0x00200000, 0x2000 /* expect 0x0100 */ - divide 0x00200000, 0x3fff /* expect 0x0080 */ - divide 0x00200000, 0x4000 /* expect 0x0080 */ - divide 0x00200000, 0x7fff /* expect 0x0040 */ - divide 0x003fffff, 0x0080 /* expect 0x7fff */ - divide 0x003fffff, 0x00ff /* expect 0x4040 */ - divide 0x003fffff, 0x0100 /* expect 0x3fff */ - divide 0x003fffff, 0x01ff /* expect 0x2010 */ - divide 0x003fffff, 0x0200 /* expect 0x1fff */ - divide 0x003fffff, 0x03ff /* expect 0x1004 */ - divide 0x003fffff, 0x0400 /* expect 0x0fff */ - divide 0x003fffff, 0x07ff /* expect 0x0801 */ - divide 0x003fffff, 0x0800 /* expect 0x07ff */ - divide 0x003fffff, 0x0fff /* expect 0x0400 */ - divide 0x003fffff, 0x1000 /* expect 0x03ff */ - divide 0x003fffff, 0x1fff /* expect 0x0200 */ - divide 0x003fffff, 0x2000 /* expect 0x01ff */ - divide 0x003fffff, 0x3fff /* expect 0x0100 */ - divide 0x003fffff, 0x4000 /* expect 0x00ff */ - divide 0x003fffff, 0x7fff /* expect 0x0080 */ - divide 0x00400000, 0x00ff /* expect 0x4040 */ - divide 0x00400000, 0x0100 /* expect 0x4000 */ - divide 0x00400000, 0x01ff /* expect 0x2010 */ - divide 0x00400000, 0x0200 /* expect 0x2000 */ - divide 0x00400000, 0x03ff /* expect 0x1004 */ - divide 0x00400000, 0x0400 /* expect 0x1000 */ - divide 0x00400000, 0x07ff /* expect 0x0801 */ - divide 0x00400000, 0x0800 /* expect 0x0800 */ - divide 0x00400000, 0x0fff /* expect 0x0400 */ - divide 0x00400000, 0x1000 /* expect 0x0400 */ - divide 0x00400000, 0x1fff /* expect 0x0200 */ - divide 0x00400000, 0x2000 /* expect 0x0200 */ - divide 0x00400000, 0x3fff /* expect 0x0100 */ - divide 0x00400000, 0x4000 /* expect 0x0100 */ - divide 0x00400000, 0x7fff /* expect 0x0080 */ - divide 0x007fffff, 0x0100 /* expect 0x7fff */ - divide 0x007fffff, 0x01ff /* expect 0x4020 */ - divide 0x007fffff, 0x0200 /* expect 0x3fff */ - divide 0x007fffff, 0x03ff /* expect 0x2008 */ - divide 0x007fffff, 0x0400 /* expect 0x1fff */ - divide 0x007fffff, 0x07ff /* expect 0x1002 */ - divide 0x007fffff, 0x0800 /* expect 0x0fff */ - divide 0x007fffff, 0x0fff /* expect 0x0800 */ - divide 0x007fffff, 0x1000 /* expect 0x07ff */ - divide 0x007fffff, 0x1fff /* expect 0x0400 */ - divide 0x007fffff, 0x2000 /* expect 0x03ff */ - divide 0x007fffff, 0x3fff /* expect 0x0200 */ - divide 0x007fffff, 0x4000 /* expect 0x01ff */ - divide 0x007fffff, 0x7fff /* expect 0x0100 */ - divide 0x00800000, 0x01ff /* expect 0x4020 */ - divide 0x00800000, 0x0200 /* expect 0x4000 */ - divide 0x00800000, 0x03ff /* expect 0x2008 */ - divide 0x00800000, 0x0400 /* expect 0x2000 */ - divide 0x00800000, 0x07ff /* expect 0x1002 */ - divide 0x00800000, 0x0800 /* expect 0x1000 */ - divide 0x00800000, 0x0fff /* expect 0x0800 */ - divide 0x00800000, 0x1000 /* expect 0x0800 */ - divide 0x00800000, 0x1fff /* expect 0x0400 */ - divide 0x00800000, 0x2000 /* expect 0x0400 */ - divide 0x00800000, 0x3fff /* expect 0x0200 */ - divide 0x00800000, 0x4000 /* expect 0x0200 */ - divide 0x00800000, 0x7fff /* expect 0x0100 */ - divide 0x00ffffff, 0x0200 /* expect 0x7fff */ - divide 0x00ffffff, 0x03ff /* expect 0x4010 */ - divide 0x00ffffff, 0x0400 /* expect 0x3fff */ - divide 0x00ffffff, 0x07ff /* expect 0x2004 */ - divide 0x00ffffff, 0x0800 /* expect 0x1fff */ - divide 0x00ffffff, 0x0fff /* expect 0x1001 */ - divide 0x00ffffff, 0x1000 /* expect 0x0fff */ - divide 0x00ffffff, 0x1fff /* expect 0x0800 */ - divide 0x00ffffff, 0x2000 /* expect 0x07ff */ - divide 0x00ffffff, 0x3fff /* expect 0x0400 */ - divide 0x00ffffff, 0x4000 /* expect 0x03ff */ - divide 0x00ffffff, 0x7fff /* expect 0x0200 */ - divide 0x01000000, 0x03ff /* expect 0x4010 */ - divide 0x01000000, 0x0400 /* expect 0x4000 */ - divide 0x01000000, 0x07ff /* expect 0x2004 */ - divide 0x01000000, 0x0800 /* expect 0x2000 */ - divide 0x01000000, 0x0fff /* expect 0x1001 */ - divide 0x01000000, 0x1000 /* expect 0x1000 */ - divide 0x01000000, 0x1fff /* expect 0x0800 */ - divide 0x01000000, 0x2000 /* expect 0x0800 */ - divide 0x01000000, 0x3fff /* expect 0x0400 */ - divide 0x01000000, 0x4000 /* expect 0x0400 */ - divide 0x01000000, 0x7fff /* expect 0x0200 */ - divide 0x01ffffff, 0x0400 /* expect 0x7fff */ - divide 0x01ffffff, 0x07ff /* expect 0x4008 */ - divide 0x01ffffff, 0x0800 /* expect 0x3fff */ - divide 0x01ffffff, 0x0fff /* expect 0x2002 */ - divide 0x01ffffff, 0x1000 /* expect 0x1fff */ - divide 0x01ffffff, 0x1fff /* expect 0x1000 */ - divide 0x01ffffff, 0x2000 /* expect 0x0fff */ - divide 0x01ffffff, 0x3fff /* expect 0x0800 */ - divide 0x01ffffff, 0x4000 /* expect 0x07ff */ - divide 0x01ffffff, 0x7fff /* expect 0x0400 */ - divide 0x02000000, 0x07ff /* expect 0x4008 */ - divide 0x02000000, 0x0800 /* expect 0x4000 */ - divide 0x02000000, 0x0fff /* expect 0x2002 */ - divide 0x02000000, 0x1000 /* expect 0x2000 */ - divide 0x02000000, 0x1fff /* expect 0x1000 */ - divide 0x02000000, 0x2000 /* expect 0x1000 */ - divide 0x02000000, 0x3fff /* expect 0x0800 */ - divide 0x02000000, 0x4000 /* expect 0x0800 */ - divide 0x02000000, 0x7fff /* expect 0x0400 */ - divide 0x03ffffff, 0x0800 /* expect 0x7fff */ - divide 0x03ffffff, 0x0fff /* expect 0x4004 */ - divide 0x03ffffff, 0x1000 /* expect 0x3fff */ - divide 0x03ffffff, 0x1fff /* expect 0x2001 */ - divide 0x03ffffff, 0x2000 /* expect 0x1fff */ - divide 0x03ffffff, 0x3fff /* expect 0x1000 */ - divide 0x03ffffff, 0x4000 /* expect 0x0fff */ - divide 0x03ffffff, 0x7fff /* expect 0x0800 */ - divide 0x04000000, 0x0fff /* expect 0x4004 */ - divide 0x04000000, 0x1000 /* expect 0x4000 */ - divide 0x04000000, 0x1fff /* expect 0x2001 */ - divide 0x04000000, 0x2000 /* expect 0x2000 */ - divide 0x04000000, 0x3fff /* expect 0x1000 */ - divide 0x04000000, 0x4000 /* expect 0x1000 */ - divide 0x04000000, 0x7fff /* expect 0x0800 */ - divide 0x07ffffff, 0x1000 /* expect 0x7fff */ - divide 0x07ffffff, 0x1fff /* expect 0x4002 */ - divide 0x07ffffff, 0x2000 /* expect 0x3fff */ - divide 0x07ffffff, 0x3fff /* expect 0x2000 */ - divide 0x07ffffff, 0x4000 /* expect 0x1fff */ - divide 0x07ffffff, 0x7fff /* expect 0x1000 */ - divide 0x08000000, 0x1fff /* expect 0x4002 */ - divide 0x08000000, 0x2000 /* expect 0x4000 */ - divide 0x08000000, 0x3fff /* expect 0x2000 */ - divide 0x08000000, 0x4000 /* expect 0x2000 */ - divide 0x08000000, 0x7fff /* expect 0x1000 */ - divide 0x0fffffff, 0x2000 /* expect 0x7fff */ - divide 0x0fffffff, 0x3fff /* expect 0x4001 */ - divide 0x0fffffff, 0x4000 /* expect 0x3fff */ - divide 0x0fffffff, 0x7fff /* expect 0x2000 */ - divide 0x10000000, 0x3fff /* expect 0x4001 */ - divide 0x10000000, 0x4000 /* expect 0x4000 */ - divide 0x10000000, 0x7fff /* expect 0x2000 */ - divide 0x1fffffff, 0x4000 /* expect 0x7fff */ - divide 0x1fffffff, 0x7fff /* expect 0x4000 */ - divide 0x20000000, 0x7fff /* expect 0x4000 */ - - pass diff --git a/sim/testsuite/sim/bfin/dotproduct.s b/sim/testsuite/sim/bfin/dotproduct.s deleted file mode 100644 index bfae545..0000000 --- a/sim/testsuite/sim/bfin/dotproduct.s +++ /dev/null @@ -1,304 +0,0 @@ -# Blackfin testcase for a simple vector dot product using hard -# wired input buffers of 128 samples each. These values are in -# 1.15 signed . - -# mach: bfin - - .include "testutils.inc" - - start - - loadsym P0, _buf0 - loadsym P1, _buf1 - - /* loop control - * number of loop iterations is 2^N with r4|=1< 32 - - A1 = R0.H * R1.L (M), A0 = R0.L * R1.L (FU); - A1 += R1.H * R0.L (M,IS); - A0 = A0 >>> 16; - A0 += A1; - A0 = A0 >>> 16; - A0 += R0.H * R1.H (IS); - R7 = A0.w; - -loop1end: - [ P2 ++ ] = R7; // store 32 bit output - - // test results - loadsym P1, output; - R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xab6b ); - R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xa627 ); - R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xa0e3 ); - R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0x9b9f ); - pass - - .data -input_a: - .dw 0x0000 - .dw 0xfabc - .dw 0x0000 - .dw 0xfabc - .dw 0x0000 - .dw 0xfabc - .dw 0x0000 - .dw 0xfabc - .dw 0x0000 - .dw 0xfabc - .dw 0x0000 - .dw 0xfabc - .dw 0x0000 - .dw 0xfabc - .dw 0x0000 - .dw 0xfabc - .dw 0x0000 - .dw 0xfabc - .dw 0x0000 - .dw 0xfabc - .align 4; -input_b: - .dw 0x1000 - .dw 0x4010 - .dw 0x1000 - .dw 0x4011 - .dw 0x1000 - .dw 0x4012 - .dw 0x1000 - .dw 0x4013 - .dw 0x1000 - .dw 0x4014 - .dw 0x1000 - .dw 0x4015 - .dw 0x1000 - .dw 0x4016 - .dw 0x1000 - .dw 0x4017 - .dw 0x1000 - .dw 0x4018 - .dw 0x1000 - .dw 0x4019 - .align 4; -output: - .space (40); diff --git a/sim/testsuite/sim/bfin/dsp_a4.s b/sim/testsuite/sim/bfin/dsp_a4.s deleted file mode 100644 index fdafcdf..0000000 --- a/sim/testsuite/sim/bfin/dsp_a4.s +++ /dev/null @@ -1,113 +0,0 @@ -/* ALU test program. - * Test instructions - * r3= + (r0,r0); - * r3= + (r0,r0) s; - * r3= - (r0,r0); - * r3= - (r0,r0) s; - */ -# mach: bfin - -.include "testutils.inc" - start - - -// overflow positive - R0.L = 0xffff; - R0.H = 0x7fff; - R7 = 0; - ASTAT = R7; - R3 = R0 + R0 (NS); - DBGA ( R3.L , 0xfffe ); - DBGA ( R3.H , 0xffff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - -// overflow negative - R0.L = 0x0000; - R0.H = 0x8000; - R7 = 0; - ASTAT = R7; - R3 = R0 + R0 (NS); - DBGA ( R3.L , 0x0000 ); - DBGA ( R3.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// zero - R0.L = 0xffff; - R0.H = 0xffff; - R1.L = 0x0001; - R1.H = 0x0000; - R7 = 0; - ASTAT = R7; - R3 = R1 + R0 (NS); - DBGA ( R3.L , 0x0000 ); - DBGA ( R3.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// saturate positive - R0.L = 0; - R0.H = 0x7fff; - R7 = 0; - ASTAT = R7; - R3 = R0 + R0 (S); - DBGA ( R3.L , 0xffff ); - DBGA ( R3.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - -// saturate negative - R0.L = 0; - R0.H = 0x8000; - R7 = 0; - ASTAT = R7; - R3 = R0 + R0 (S); - DBGA ( R3.L , 0x0000 ); - DBGA ( R3.H , 0x8000 ); - - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// saturate positive with subtraction - R0.L = 0xffff; - R0.H = 0xffff; - R1.L = 0xffff; - R1.H = 0x7fff; - R7 = 0; - ASTAT = R7; - R3 = R1 - R0 (S); - DBGA ( R3.L , 0xffff ); - DBGA ( R3.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - -// saturate negative with subtraction - R0.L = 0x1; - R0.H = 0x0; - R1.L = 0x0000; - R1.H = 0x8000; - R7 = 0; - ASTAT = R7; - R3 = R1 - R0 (S); - DBGA ( R3.L , 0x0000 ); - DBGA ( R3.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - - pass diff --git a/sim/testsuite/sim/bfin/dsp_a7.s b/sim/testsuite/sim/bfin/dsp_a7.s deleted file mode 100644 index 075fbc7..0000000 --- a/sim/testsuite/sim/bfin/dsp_a7.s +++ /dev/null @@ -1,103 +0,0 @@ -/* ALU test program. - * Test instructions - * r7 = +/- (r0,r1); - * r7 = -/+ (r0,r1); - * r7 = -/- (r0,r1); - */ - -# mach: bfin - -.include "testutils.inc" - start - -// test subtraction - R0.L = 0x000f; - R0.H = 0x0010; - R1.L = 0x000f; - R1.H = 0x0010; - R7 = 0; - ASTAT = R7; - R7 = R0 +|- R1; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0020 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// test overflow negative on subtraction - R0.L = 0x8000; - R0.H = 0x0010; - R1.L = 0x0001; - R1.H = 0x0010; - R7 = 0; - ASTAT = R7; - R7 = R0 +|- R1; - DBGA ( R7.L , 0x7fff ); - DBGA ( R7.H , 0x0020 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// test saturate negative on subtraction +/- - R0.L = 0x8000; - R0.H = 0x0010; - R1.L = 0x0001; - R1.H = 0x0010; - R7 = 0; - ASTAT = R7; - R7 = R0 +|- R1 (S); - DBGA ( R7.L , 0x8000 ); - DBGA ( R7.H , 0x0020 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// test saturate negative on subtraction -/+ - R0.L = 0x8000; - R0.H = 0x8000; - R1.L = 0x0001; - R1.H = 0x0001; - R7 = 0; - ASTAT = R7; - R7 = R0 -|+ R1 (S); - DBGA ( R7.L , 0x8001 ); - DBGA ( R7.H , 0x8000 ); - CC = AZ; R5 = CC; DBGA ( R5.L , 0x0 ); - CC = AN; R5 = CC; DBGA ( R5.L , 0x1 ); - CC = V; R5 = CC; DBGA ( R5.L , 0x1 ); - CC = AC0; R5 = CC; DBGA ( R5.L , 0x0 ); - -// test saturate negative on subtraction -/- - R0.L = 0x8000; - R0.H = 0x8000; - R1.L = 0x0001; - R1.H = 0x0001; - R7 = 0; - ASTAT = R7; - R7 = R0 -|- R1 (S); - DBGA ( R7.L , 0x8000 ); - DBGA ( R7.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// test saturate positive on subtraction -/+ - R0.L = 0x7fff; - R0.H = 0x7fff; - R1.L = 0xffff; - R1.H = 0xffff; - R7 = 0; - ASTAT = R7; - R7 = R0 -|+ R1 (S); - DBGA ( R7.L , 0x7ffe ); - DBGA ( R7.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - - pass diff --git a/sim/testsuite/sim/bfin/dsp_a8.s b/sim/testsuite/sim/bfin/dsp_a8.s deleted file mode 100644 index 0383e20..0000000 --- a/sim/testsuite/sim/bfin/dsp_a8.s +++ /dev/null @@ -1,80 +0,0 @@ -/* ALU test program. - * Test instructions - * (r7,r6) = +/- (r0,r1); - * (r7,r6) = +/- (r0,r1)s; - */ -# mach: bfin - -.include "testutils.inc" - start - - -// test positive overflow - R0.L = 0xffff; - R0.H = 0x7fff; - R1.L = 0x0001; - R1.H = 0x0000; - R7 = 0; - ASTAT = R7; - R6 = R0 + R1, R7 = R0 - R1 (NS); - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8000 ); - DBGA ( R7.L , 0xfffe ); - DBGA ( R7.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// test positive overflow - R0.L = 0xffff; - R0.H = 0x7fff; - R1.L = 0x0001; - R1.H = 0x0000; - R7 = 0; - ASTAT = R7; - R7 = R0 + R1, R6 = R0 - R1 (NS); - DBGA ( R6.L , 0xfffe ); - DBGA ( R6.H , 0x7fff ); - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// test positive sat - R0.L = 0xffff; - R0.H = 0x7fff; - R1.L = 0x0001; - R1.H = 0x0000; - R7 = 0; - ASTAT = R7; - R6 = R0 + R1, R7 = R0 - R1 (S); - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0x7fff ); - DBGA ( R7.L , 0xfffe ); - DBGA ( R7.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - -// test positive sat - R0.L = 0xffff; - R0.H = 0x7fff; - R1.L = 0x0001; - R1.H = 0x0000; - R7 = 0; - ASTAT = R7; - R7 = R0 + R1, R6 = R0 - R1 (S); - DBGA ( R6.L , 0xfffe ); - DBGA ( R6.H , 0x7fff ); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); - - pass diff --git a/sim/testsuite/sim/bfin/dsp_d0.s b/sim/testsuite/sim/bfin/dsp_d0.s deleted file mode 100644 index ff7aaf0..0000000 --- a/sim/testsuite/sim/bfin/dsp_d0.s +++ /dev/null @@ -1,31 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - loadsym I0, vec; - - R0 = [ I0 ++ ]; - DBGA ( R0.L , 1 ); DBGA ( R0.H , 2 ); - R0 = [ I0 ++ ]; - DBGA ( R0.L , 2 ); DBGA ( R0.H , 3 ); - - loadsym I3, vec; - R0 = 4; - M1 = R0; - - _DBG I3; - R0 = [ I3 ++ M1 ]; - DBGA ( R0.L , 1 ); DBGA ( R0.H , 2 ); - _DBG I3; - R0 = [ I3 ++ M1 ]; - DBGA ( R0.L , 2 ); DBGA ( R0.H , 3 ); - - pass - - .data -vec: - .dw 1 - .dw 2 - .dw 2 - .dw 3 diff --git a/sim/testsuite/sim/bfin/dsp_d1.s b/sim/testsuite/sim/bfin/dsp_d1.s deleted file mode 100644 index c045ba5..0000000 --- a/sim/testsuite/sim/bfin/dsp_d1.s +++ /dev/null @@ -1,117 +0,0 @@ -/* DAG test program. - * Test circular buffers - */ -# mach: bfin - -.include "testutils.inc" - start - - loadsym I0, foo; - loadsym B0, foo; - loadsym R2, foo; - L0 = 0x10 (X); - M1 = 8 (X); - R0 = [ I0 ++ M1 ]; - R7 = I0; - R1 = R7 - R2 - DBGA ( R1.L , 0x0008 ); - R0 = [ I0 ++ M1 ]; - R7 = I0; - - R1 = R7 - R2; - DBGA ( R1.L , 0x0000 ); - R0 = [ I0 ++ M1 ]; - R7 = I0; - R1 = R7 - R2 - DBGA ( R1.L , 0x0008 ); - - loadsym I0, foo; - loadsym B0, foo; - loadsym R2, foo; - L0 = 0x10 (X); - M1 = -4 (X); - R0 = [ I0 ++ M1 ]; - R7 = I0; - R1 = R7 - R2 - DBGA ( R1.L , 0x000c ); - R0 = [ I0 ++ M1 ]; - R7 = I0; - R1 = R7 - R2 - DBGA ( R1.L , 0x0008 ); - R0 = [ I0 ++ M1 ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0004 ); - R0 = [ I0 ++ M1 ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0000 ); - R0 = [ I0 ++ M1 ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x000c ); - - loadsym I0, foo; - loadsym B0, foo; - loadsym R2, foo; - L0 = 0x8 (X); - R0 = [ I0 ++ ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0004 ); - R0 = [ I0 ++ ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0000 ); - R0 = [ I0 ++ ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0004 ); - - loadsym I0, foo; - loadsym B0, foo; - loadsym R2, foo; - L0 = 0x8 (X); - R0.L = W [ I0 ++ ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0002 ); - R0.L = W [ I0 ++ ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0004 ); - R0.L = W [ I0 ++ ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0006 ); - R0.L = W [ I0 ++ ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0000 ); - R0.L = W [ I0 ++ ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0002 ); - - loadsym I0, foo; - loadsym B0, foo; - loadsym R2, foo; - L0 = 0x8 (X); - R0 = [ I0 -- ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0004 ); - R0 = [ I0 -- ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0000 ); - R0 = [ I0 -- ]; - R7 = I0; - R1 = R7 - R2; - DBGA ( R1.L , 0x0004 ); - - pass - - .data -foo: - .space (0x10); diff --git a/sim/testsuite/sim/bfin/dsp_neg.S b/sim/testsuite/sim/bfin/dsp_neg.S deleted file mode 100644 index a6ec10a..0000000 --- a/sim/testsuite/sim/bfin/dsp_neg.S +++ /dev/null @@ -1,36 +0,0 @@ -// ALU test program. -// Test instructions: -// dreg = -dreg (ns); -// dreg = -dreg (s); -// dspalu32 negate instruction -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - -// CHECK MULTI ISSUE - r1=0x5; - loadsym i0, data0; - r2 = -r1 (ns) || r3=[i0++]; - checkreg r2, 0xfffffffb; - r3 = astat - checkreg r3, (_AN); - - r1.h = 0x8000; - r1.l = 0x0; - r2 = -r1 (s); - checkreg r2, 0x7fffffff; - - r3 = astat; - _dbg astat; - checkreg r3, (_VS|_V|_V_COPY); - - pass - - .data -data0: - .space (0x10); diff --git a/sim/testsuite/sim/bfin/dsp_s1.s b/sim/testsuite/sim/bfin/dsp_s1.s deleted file mode 100644 index 70d8a5d..0000000 --- a/sim/testsuite/sim/bfin/dsp_s1.s +++ /dev/null @@ -1,85 +0,0 @@ -/* SHIFT test program. - * Test r0, r1, A0 >>= BITMUX; - */ -# mach: bfin - -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = r0; - -// load r0=0x80000009 -// load r1=0x10000009 -// load r2=0x0000000f -// load r3=0x00000000 -// load r4=0x80000008 -// load r5=0x00000000 - loadsym P0, data0; - loadsym P1, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - R5 = [ P0 ++ ]; - -// insert two bits, both equal to 1 -// A0: 00 0000 000f -> c0 0000 0003 -// r0: 8000 0009 -> 4000 0004 -// r1: 1000 0009 -> 0800 0004 - R0 = [ P1 + 0 ]; - R1 = [ P1 + 4 ]; - A0.w = R2; - A0.x = R3.L; - BITMUX( R0 , R1, A0) (ASR); - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0x0003 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0xffc0 ); - DBGA ( R0.L , 0x0004 ); - DBGA ( R0.H , 0x4000 ); - DBGA ( R1.L , 0x0004 ); - DBGA ( R1.H , 0x0800 ); - -// insert two bits, one equal to 1, other to 0 -// A0: 00 0000 000f -> 40 0000 0003 -// r0: 8000 0009 -> 4000 0004 -// r4: 8000 0008 -> 4000 0004 - R0 = [ P1 + 0 ]; - R4 = [ P1 + 16 ]; - A0.w = R2; - A0.x = R3.L; - BITMUX( R0 , R4, A0) (ASR); - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0x0003 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x0040 ); - DBGA ( R0.L , 0x0004 ); - DBGA ( R0.H , 0x4000 ); - DBGA ( R4.L , 0x0004 ); - DBGA ( R4.H , 0x4000 ); - - pass - - .data -data0: - .dw 0x0009 - .dw 0x8000 - - .dw 0x0009 - .dw 0x1000 - - .dw 0x000f - .dw 0x0000 - - .dw 0x0000 - .dw 0x0000 - - .dw 0x0008 - .dw 0x8000 - - .dw 0x0000 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/e0.s b/sim/testsuite/sim/bfin/e0.s deleted file mode 100644 index bdcd71b..0000000 --- a/sim/testsuite/sim/bfin/e0.s +++ /dev/null @@ -1,51 +0,0 @@ -// assert that we can issue a software exception -// and that the expt number is passed correctly through -// SEQSTAT. -# mach: bfin -# sim: --environment operating - - .include "testutils.inc" - - start -.ifndef BFIN_HOST - imm32 p0, 0xFFE02000; /* EVT0 */ - P1 = re (Z); // load a pointer to ihandler interrupt 1 - P1.H = re; - [ P0 + (4*3) ] = P1; - - R0 = -1; /* unmask all interrupts */ - imm32 p1, 0xFFE02104; - [P1] = R0; - - R0 = start_uspace (Z); - R0.H = start_uspace; - RETI = R0; - RTI; -start_uspace: - EXCPT 10; - - DBGA ( R1.L , 0x1238 ); - - dbg_pass; - - // ihandler -re: - R0 = SEQSTAT; - R0 <<= (32-6); - R0 >>= (32-6); - R2 = 0x20; - CC = R0 < R2; - IF !CC JUMP _error; - DBGA ( R0.L , 0xa ); - R1 = 0x1234 (X); - R1 += 1; - R1 += 1; - R1 += 1; - R1 += 1; - RTX; - -_error: - DBGA ( R0.L , EXCPT_PROTVIOL ); - dbg_fail; - -.endif diff --git a/sim/testsuite/sim/bfin/edn_snafu.s b/sim/testsuite/sim/bfin/edn_snafu.s deleted file mode 100644 index b97d7e8..0000000 --- a/sim/testsuite/sim/bfin/edn_snafu.s +++ /dev/null @@ -1,45 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - - loadsym r7, foo; - - p0 = r7; - - r0.h=0x2a2a; - r0.l=0x2a2a; - - [p0++]=r0; - [p0++]=r0; - r0=0; - [p0++]=r0; - - p0 = r7; - p1=-1; - - lsetup(lstart, lend) lc0=p1; - -lstart: - _dbg p0; - r1=b[p0++] (z); - cc = r1 == 0; - if cc jump ldone; -lend: - nop; - -ldone: - - r1=b[p0++](z); - r1=p0; - r6 = r1 - r7; - - DBGA (R6.L, 0xA); - - pass; - - .data -foo: - .space (0x100) diff --git a/sim/testsuite/sim/bfin/eu_dsp32mac_s.s b/sim/testsuite/sim/bfin/eu_dsp32mac_s.s deleted file mode 100644 index 6935aa6..0000000 --- a/sim/testsuite/sim/bfin/eu_dsp32mac_s.s +++ /dev/null @@ -1,38 +0,0 @@ -// Check MAC with scaling -# mach: bfin - -.include "testutils.inc" - start - - - R0 = 0; - R1 = 0; - R2 = 0; - A1 = A0 = 0; -// The result accumulated in A1, and stored to a reg half - R0.L = 23229; - R0.H = -23724; - R1.L = -313; - R1.H = -17732; - R2.H = ( A1 = R1.L * R0.L ), A0 += R1.L * R0.L (S2RND); - _DBG R2; - DBGA ( R2.H , 0xfe44 ); - - R0 = 0; - ASTAT = R0; // clear all flags - A0 = 0; - A1 = 0; - R0.H = 0x8000; - R0.L = 0x7fff; - R1.H = 0x7fff; - R1.L = 0x8000; - A1 = R0.H * R1.H (M), R0.L = ( A0 -= R0.H * R1.H ) (ISS2); - _DBG R0; - DBGA ( R0.L , 0x7fff ); - - R0 += 0; // clear flags - NOP; - NOP; - NOP; - NOP; - pass diff --git a/sim/testsuite/sim/bfin/events.s b/sim/testsuite/sim/bfin/events.s deleted file mode 100644 index 689f47b..0000000 --- a/sim/testsuite/sim/bfin/events.s +++ /dev/null @@ -1,44 +0,0 @@ -# Blackfin testcase for event processing -# mach: bfin - - .include "testutils.inc" - - start - - # Run enough instructions to trigger event processing - # and thus cpu stopping/restarting - - R0 = 0; - imm32 R1, 100000 - -3: - R0 += 1; # 1 - R0 += 1; - R0 += 1; # 3 - R0 += 1; - R0 += 1; # 5 - R0 += 1; - R0 += 1; # 7 - R0 += 1; - R0 += 1; # 9 - R0 += 1; - R0 += 1; # 11 - R0 += 1; - R0 += 1; # 13 - R0 += 1; - R0 += 1; # 15 - R0 += 1; - R0 += 1; # 17 - R0 += 1; - R0 += 1; # 19 - R0 += 1; - - CC = R0 < R1; - IF CC JUMP 3b; - - CC = R0 == R1; - IF !CC JUMP 1f; - - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/f221.s b/sim/testsuite/sim/bfin/f221.s deleted file mode 100644 index 7968843..0000000 --- a/sim/testsuite/sim/bfin/f221.s +++ /dev/null @@ -1,56 +0,0 @@ -# Blackfin testcase for the CEC (handling exceptions from usermode) -# mach: bfin -# sim: --environment operating - - .include "testutils.inc" - - start -.ifndef BFIN_HOST - // load address of exception handler - imm32 p0, 0xFFE02000; /* EVT0 */ - R0 = exception_handler (Z); - R0.H = exception_handler; - [ P0 + (4*3) ] = R0; - // Jump to User mode and enable exceptions - R0 = UserCode (Z); - R0.H = UserCode; - RETI = R0; - RTI; - -UserCode: - R4 = 0xec39 (Z); - R0 = 0xcafe (Z); - L3 = 0xf41f (Z); - L3.H = 0x1ce9; - I3 = 0xfe10 (Z); - I3.H = 0x20a9; - B3 = 0x4552 (Z); - B3.H = 0x15f0; - - // should except - r4 dep - // R4 = R4 >> 25 || W [ I3 ++ ] = R0.H || R4 = [ I3 ]; -.Lskip_start: - .rep 8 - .byte 0xff - .endr - dbg_fail; -.Lskip_end: - NOP; - NOP; - NOP; - NOP; - NOP; - dbg_pass; - -exception_handler: - // just skip over excepting instructions - R0 = RETX; - R1.L = .Lskip_start; - R1.H = .Lskip_start; - R2.L = .Lskip_end; - R2.H = .Lskip_end; - R2 = R2 - R1; - R0 = R0 + R2; - RETX = R0; - RTX; -.endif diff --git a/sim/testsuite/sim/bfin/fact.s b/sim/testsuite/sim/bfin/fact.s deleted file mode 100644 index aed8153..0000000 --- a/sim/testsuite/sim/bfin/fact.s +++ /dev/null @@ -1,51 +0,0 @@ -# Blackfin testcase for factorial -# mach: bfin - - .include "testutils.inc" - - start - - .macro factorial num:req answer:req - R0 = \num (Z); - CALL _fact; - imm32 r1, \answer; - CC = R1 == R0; - if CC JUMP 1f; - fail -1: - .endm - -_test: - factorial 1 1 - factorial 2 2 - factorial 3 6 - factorial 4 24 - factorial 5 120 - factorial 6 720 - factorial 7 5040 - factorial 8 40320 - factorial 9 362880 - factorial 10 3628800 - factorial 11 39916800 - factorial 12 479001600 -# This is the real answer, but it overflows 32bits. Since gas itself -# likes to choke on 64bit values when compiled for 32bit systems, just -# specify the truncated 32bit value since that's what the Blackfin will -# come up with too. -# factorial 13 6227020800 - factorial 13 1932053504 - pass - -_fact: - LINK 0; - [ -- SP ] = R7; - CC = R0 < 2; - IF CC JUMP 1f; - R7 = R0; - R0 += -1; - CALL _fact; - R0 *= R7; -1: - R7 = [ SP ++ ]; - UNLINK; - RTS; diff --git a/sim/testsuite/sim/bfin/fir.s b/sim/testsuite/sim/bfin/fir.s deleted file mode 100644 index 0ba4d2f..0000000 --- a/sim/testsuite/sim/bfin/fir.s +++ /dev/null @@ -1,201 +0,0 @@ -# mach: bfin - -// FIR FILTER COMPTUED DIRECTLY ON INPUT WITH NO -// INTERNAL STATE -// TWO OUTPUTS PER ITERATION -// This program computes a FIR filter without maintaining a buffer of internal -// state. -// This example computes two output samples per inner loop. The following -// diagram shows the alignment required for signal x and coefficients c: -// x0 x1 x2 x3 x4 x5 -// c0 c1 c2 c3 c4 -> output z(0)=x0*c0 + x1*c1 + ... -// c0 c1 c2 c3 c4 -> z(1)=x1*c0 + x2*c1 + ... -// L-1 -// --- -// Z(k) = \ c(n) * x(n+k) -// / -// --- -// n=0 -// Naive, first stab at spliting this for dual MACS. -// L/2-1 L/2-1 -// --- --- -// R(k) = \ (x(2n) * y(2n+k)) + \ (x(2n-1) * y(2n-1+k)) -// / / -// --- --- -// n=0 n=0 -// Alternate, better partitioning for the machine. -// L-1 -// --- -// R(0) = \ x(n) * y(n) -// / -// --- -// n=0 -// L-1 -// --- -// R(1) = \ x(n) * y(n+1) -// / -// --- -// n=0 -// L-1 -// --- -// R(2) = \ x(n) * y(n+2) -// / -// --- -// n=0 -// L-1 -// --- -// R(3) = \ x(n) * y(n+3) -// / -// --- -// n=0 -// . -// . -// . -// . -// Okay in this verion the inner loop will compute R(2k) and R(2k+1) in parallel -// L-1 -// --- -// R(2k) = \ x(n) * y(n+2k) -// / -// --- -// n=0 -// L-1 -// --- -// R(2k+1) = \ x(n) * y(n+2k+1) -// / -// --- -// n=0 -// Implementation -// -------------- -// Sample pair x1 x0 is loaded into register R0, and coefficients c1 c0 -// is loaded into register R1: -// +-------+ R0 -// | x1 x0 | -// +-------+ -// +-------+ R1 -// | c1 c0 | compute two MACs: z(0)+=x0*c0, and z(1)+=x1*c0 -// +-------+ -// Now load x2 into lo half of R0, and compute the next two MACs: -// +-------+ R0 -// | x1 x2 | -// +-------+ -// +-------+ R1 -// | c1 c0 | compute z(0)+=x1*c1 and z(1)+=x2*c1 (c0 not used) -// +-------+ -// Meanwhile, load coefficient pair c3 c2 into R2, and x3 into hi half of R0: -// +-------+ R0 -// | x3 x2 | -// +-------+ -// +-------+ R2 -// | c3 c2 | compute z(0)+=x2*c2 and z(1)+=x3*c2 (c3 not used) -// +-------+ -// Load x4 into low half of R0: -// +-------+ R0 -// | x3 x4 | -// +-------+ -// +-------+ R1 -// | c3 c2 | compute z(0)+=x3*c3 and z(1)+=x4*c3 (c2 not used) -// +-------+ -// //This is a reference FIR function used to test: */ -//void firf (float input[], float output[], float coeffs[], -// long input_size, long coeffs_size) -//{ -// long i, k; -// for(i=0; i< input_size; i++){ -// output[i] = 0; -// for(k=0; k < coeffs_size; k++) -// output[i] += input[k+i] * coeffs[k]; -// } -//} - -.include "testutils.inc" - start - - - R0 = 0; R1 = 0; R2 = 0; - P1 = 128 (X); // Load loop bounds in R5, R6, and divide by 2 - P2 = 64 (X); - - // P0 holds pointer to input data in one memory - // bank. Increments by 2 after each inner-loop iter - loadsym P0, input; - - // Pointer to coeffs in alternate memory bank. - loadsym I1, coef; - - // Pointer to outputs in any memory bank. - loadsym I2, output; - - // Setup outer do-loop for M/2 iterations - // (2 outputs are computed per pass) - - LSETUP ( L$0 , L$0end ) LC0 = P1 >> 1; - -L$0: - loadsym I1, coef; - I0 = P0; - // Set-up inner do-loop for L/2 iterations - // (2 MACs are computed per pass) - - LSETUP ( L$1 , L$1end ) LC1 = P2 >> 1; - - // Load first two data elements in r0, - // and two coeffs into r1: - - R0.L = W [ I0 ++ ]; - A1 = A0 = 0 || R0.H = W [ I0 ++ ] || R1 = [ I1 ++ ]; - -L$1: - A1 += R0.H * R1.L, A0 += R0.L * R1.L || R0.L = W [ I0 ++ ] || NOP; -L$1end: - A1 += R0.L * R1.H, A0 += R0.H * R1.H || R0.H = W [ I0 ++ ] || R1 = [ I1 ++ ]; - - // Line 1: do 2 MACs and load next data element into RL0. - // Line 2: do 2 MACs, load next data element into RH0, - // and load next 2 coeffs - - R0.H = A1, R0.L = A0; - - // advance data pointer by 2 16b elements - P0 += 4; - -L$0end: - [ I2 ++ ] = R0; // store 2 outputs - - // Check results - loadsym I2, output; - - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0800 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1000 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x2000 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1000 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0800 ); - pass - - .data -input: - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x4000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .space ((128-10)*2); // must pad with zeros or uninitialized values. - - .data -coef: - .dw 0x1000 - .dw 0x2000 - .dw 0x4000 - .dw 0x2000 - .dw 0x1000 - .dw 0x0000 - .space ((64-6)*2); // must pad with zeros or uninitialized values. - - .data -output: - .space (128*4) diff --git a/sim/testsuite/sim/bfin/fsm.s b/sim/testsuite/sim/bfin/fsm.s deleted file mode 100644 index a15ffa0..0000000 --- a/sim/testsuite/sim/bfin/fsm.s +++ /dev/null @@ -1,57 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - R1 = 0; - R0 = R1; - R7 = 7; -L$10: - CC = R0 == 1; - IF CC JUMP L$14; - CC = R0 <= 1; - IF !CC JUMP L$30; - CC = R0 == 0; - IF CC JUMP L$12; - JUMP.S L$25; -L$30: - CC = R0 == R7; - IF CC JUMP L$16; - R5 = 17; - CC = R0 == R5; - IF CC JUMP L$23; - JUMP.S L$25; -L$12: - R1 += 5; - R0 = 1; - JUMP.S L$8; -L$14: - R1 <<= 4; - R0 = 4; - JUMP.S L$8; -L$16: - CC = BITTST ( R1 , 3 ); - IF CC JUMP L$17; - BITSET( R1 , 3 ); - R0 = 4; - JUMP.S L$20; -L$17: - BITSET( R1 , 5 ); - R0 = 14; -L$20: - JUMP.S L$8; -L$23: - R5 = 13; - R1 = R1 ^ R5; - R0 = 20; - JUMP.S L$8; -L$25: - R1 += 1; - R0 += 1; -L$8: - R5 = 19; - CC = R0 <= R5; - IF CC JUMP L$10 (BP); - DBGA ( R0.L , 20 ); DBGA ( R1.L , 140 ); - pass diff --git a/sim/testsuite/sim/bfin/greg2.s b/sim/testsuite/sim/bfin/greg2.s deleted file mode 100644 index 7135130..0000000 --- a/sim/testsuite/sim/bfin/greg2.s +++ /dev/null @@ -1,18 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - r3.l=0x5678; - r3.h=0x1234; - - p5=8; - - p5=r3; - p5.l =4; - - r5=p5; - dbga( r5.h, 0x1234); - -_halt: - pass; diff --git a/sim/testsuite/sim/bfin/hwloop-bits.S b/sim/testsuite/sim/bfin/hwloop-bits.S deleted file mode 100644 index 76d9003..0000000 --- a/sim/testsuite/sim/bfin/hwloop-bits.S +++ /dev/null @@ -1,104 +0,0 @@ -# Blackfin testcase for HW Loops and user->super transitions -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - - .macro check_hwloop_regs lc:req, lt:req, lb:req - R0 = LC0; - CC = R0 == \lc; - IF !CC JUMP fail; - - R0 = LT0; - CC = R0 == \lt; - IF !CC JUMP fail; - - R0 = LB0; - CC = R0 == \lb; - IF !CC JUMP fail; - - R0 = LC1; - CC = R0 == \lc; - IF !CC JUMP fail; - - R0 = LT1; - CC = R0 == \lt; - IF !CC JUMP fail; - - R0 = LB1; - CC = R0 == \lb; - IF !CC JUMP fail; - .endm - - start - - imm32 P0, EVT3; - loadsym R0, exception; - [P0] = R0; - - imm32 P0, EVT2; - loadsym R0, nmi; - [P0] = R0; - - loadsym R0, usermode; - RETI = R0; - - # Set the LC/LB/LT up with LSB set - # - Hardware clears LT LSB, but LB remains until we lower - imm32 R6, 0xaaaa5555 - R4 = R6; - BITCLR (R4, 0); - imm32 R7, 0xaa55aa55 - R5 = R7; - BITCLR (R5, 0); - - LC0 = R6; - LT0 = R6; - LB0 = R7; - LC1 = R6; - LT1 = R6; - LB1 = R7; - - # Sanity check - check_hwloop_regs R6, R4, R7 - - RTI; - -usermode: - # Make sure LSB has been cleared in LB - check_hwloop_regs R6, R4, R5 - - # Clear LSB in all LC/LT/LB - LC0 = R4; - LT0 = R4; - LB0 = R5; - LC1 = R4; - LT1 = R4; - LB1 = R5; - - # Now move back up to supervisor - EXCPT 4; - -exception: - # Make sure LSB is set in LB - check_hwloop_regs R4, R4, R7 - - # Clear the LSB and move up another supervisor level - LC0 = R4; - LT0 = R4; - LB0 = R5; - LC1 = R4; - LT1 = R4; - LB1 = R5; - - RAISE 2; - -nmi: - # Make sure LSB stayed clear - check_hwloop_regs R4, R4, R5 - - dbg_pass - -fail: - dbg_fail diff --git a/sim/testsuite/sim/bfin/hwloop-branch-in.s b/sim/testsuite/sim/bfin/hwloop-branch-in.s deleted file mode 100644 index c477c94..0000000 --- a/sim/testsuite/sim/bfin/hwloop-branch-in.s +++ /dev/null @@ -1,99 +0,0 @@ -# Blackfin testcase for branching into the middle of a hardware loop -# mach: bfin - - .include "testutils.inc" - - .macro test_prep lc:req - loadsym P5, 1f; - dmm32 LC0, \lc - R5 = 0; - R6 = 0; - R7 = 0; - .endm - - .macro test_check exp5:req, exp6:req, exp7:req, expLC:req -1: - imm32 R4, \exp5; - CC = R4 == R5; - IF !CC JUMP 2f; - imm32 R4, \exp6; - CC = R4 == R6; - IF !CC JUMP 2f; - imm32 R4, \exp7; - CC = R4 == R7; - IF !CC JUMP 2f; - R3 = LC0; - imm32 R4, \expLC; - CC = R4 == R3; - IF !CC JUMP 2f; - JUMP 3f; -2: fail -3: - .endm - - .macro test_rts entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req - loadsym R1, \entry; - RETS = R1; - test_prep \lc - RTS; - test_check \exp5, \exp6, \exp7, \expLC - .endm - - .macro test_jump entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req - loadsym P1, \entry; - test_prep \lc - JUMP (P1); - test_check \exp5, \exp6, \exp7, \expLC - .endm - - start - - loadsym R1, hws; - LT0 = R1; - loadsym R1, hwe; - LB0 = R1; - - test_rts hws, 0, 1, 1, 1, 0 - test_rts hws, 1, 1, 1, 1, 0 - test_rts hws, 2, 2, 2, 2, 0 - test_rts hws, 20, 20, 20, 20, 0 - - test_rts hwm, 0, 0, 1, 1, 0 - test_rts hwm, 1, 0, 1, 1, 0 - test_rts hwm, 2, 1, 2, 2, 0 - test_rts hwm, 20, 19, 20, 20, 0 - - test_rts hwe, 0, 0, 0, 1, 0 - test_rts hwe, 1, 0, 0, 1, 0 - test_rts hwe, 2, 1, 1, 2, 0 - test_rts hwe, 20, 19, 19, 20, 0 - - test_rts hwp, 0, 0, 0, 0, 0 - test_rts hwp, 1, 0, 0, 0, 1 - test_rts hwp, 2, 0, 0, 0, 2 - - test_jump hws, 0, 1, 1, 1, 0 - test_jump hws, 1, 1, 1, 1, 0 - test_jump hws, 2, 2, 2, 2, 0 - test_jump hws, 20, 20, 20, 20, 0 - - test_jump hwm, 0, 0, 1, 1, 0 - test_jump hwm, 1, 0, 1, 1, 0 - test_jump hwm, 2, 1, 2, 2, 0 - test_jump hwm, 20, 19, 20, 20, 0 - - test_jump hwe, 0, 0, 0, 1, 0 - test_jump hwe, 1, 0, 0, 1, 0 - test_jump hwe, 2, 1, 1, 2, 0 - test_jump hwe, 20, 19, 19, 20, 0 - - test_jump hwp, 0, 0, 0, 0, 0 - test_jump hwp, 1, 0, 0, 0, 1 - test_jump hwp, 2, 0, 0, 0, 2 - - pass - -hws: R5 += 1; -hwm: R6 += 1; -hwe: R7 += 1; -hwp: JUMP (P5); diff --git a/sim/testsuite/sim/bfin/hwloop-branch-out.s b/sim/testsuite/sim/bfin/hwloop-branch-out.s deleted file mode 100644 index 54f712b..0000000 --- a/sim/testsuite/sim/bfin/hwloop-branch-out.s +++ /dev/null @@ -1,129 +0,0 @@ -# Blackfin testcase for branching out of the middle of a hardware loop -# mach: bfin - - .include "testutils.inc" - - .macro test_prep lc:req, sym:req - imm32 P0, \lc - loadsym P1, \sym - R5 = 0; - R6 = 0; - R7 = 0; - LSETUP (1f, 2f) LC0 = P0; - .endm - - .macro test_check exp5:req, exp6:req, exp7:req, expLC - imm32 R4, \exp5; - CC = R4 == R5; - IF !CC JUMP 2f; - imm32 R4, \exp6; - CC = R4 == R6; - IF !CC JUMP 2f; - imm32 R4, \exp7; - CC = R4 == R7; - IF !CC JUMP 2f; - R3 = LC0; - imm32 R4, \expLC; - CC = R4 == R3; - IF !CC JUMP 2f; - JUMP 3f; -2: fail -3: - .endm - - start - mnop; - -test_jump_s: - .macro test_jump_s lc:req - test_prep \lc, 3f -1: JUMP (P1); - R5 += 1; -2: R6 += 1; - fail -3: R7 += 1; - test_check 0, 0, 1, \lc - .endm - test_jump_s 0 - test_jump_s 1 - test_jump_s 2 - test_jump_s 10 - -test_jump_m: - .macro test_jump_m lc:req - test_prep \lc, 3f -1: R5 += 1; - JUMP (P1); -2: R6 += 1; - fail -3: R7 += 1; - test_check 1, 0, 1, \lc - .endm - test_jump_m 0 - test_jump_m 1 - test_jump_m 2 - test_jump_m 10 - -test_jump_e: - .macro test_jump_e lc:req, lcend:req - test_prep \lc, 3f -1: R5 += 1; - R6 += 1; -2: JUMP (P1); - fail -3: R7 += 1; - test_check 1, 1, 1, \lcend - .endm - test_jump_e 0, 0 - test_jump_e 1, 0 - test_jump_e 2, 1 - test_jump_e 10, 9 - -test_call_s: - .macro test_call_s lc:req, exp5:req, exp6:req, exp7:req - test_prep \lc, __ret -1: CALL (P1); - R5 += 1; -2: R6 += 1; -3: R7 += 1; - test_check \exp5, \exp6, \exp7, 0 - .endm - test_call_s 0, 1, 1, 2 - test_call_s 1, 1, 1, 2 - test_call_s 2, 2, 2, 3 - test_call_s 10, 10, 10, 11 - -test_call_m: - .macro test_call_m lc:req, exp5:req, exp6:req, exp7:req - test_prep \lc, __ret -1: R5 += 1; - CALL (P1); -2: R6 += 1; -3: R7 += 1; - test_check \exp5, \exp6, \exp7, 0 - .endm - test_call_m 0, 1, 1, 2 - test_call_m 1, 1, 1, 2 - test_call_m 2, 2, 2, 3 - test_call_m 10, 10, 10, 11 - -test_call_e: - .macro test_call_e lc:req, exp5:req, exp6:req, exp7:req - test_prep \lc, __ret -1: R5 += 1; - R6 += 1; -2: CALL (P1); -3: R7 += 1; - test_check \exp5, \exp6, \exp7, 0 - .endm - test_call_e 0, 1, 1, 2 - test_call_e 1, 1, 1, 2 - test_call_e 2, 2, 2, 3 - test_call_e 10, 10, 10, 11 - - pass - -__ret: - nop;nop;nop; - R7 += 1; - rts; diff --git a/sim/testsuite/sim/bfin/hwloop-lt-bits.s b/sim/testsuite/sim/bfin/hwloop-lt-bits.s deleted file mode 100644 index dd21c8a..0000000 --- a/sim/testsuite/sim/bfin/hwloop-lt-bits.s +++ /dev/null @@ -1,25 +0,0 @@ -# Blackfin testcase for HW Loops (LT) LSB behavior -# mach: bfin - - .include "testutils.inc" - - start - - # Loading LT should always clear LSB - imm32 R6, 0xaaaa5555 - R4 = R6; - BITCLR (R4, 0); - - LT0 = R6; - LT1 = R6; - - R0 = LT0; - CC = R0 == R4; - IF ! CC JUMP 1f; - - R0 = LT1; - CC = R0 == R4; - IF ! CC JUMP 1f; - - pass -1: fail diff --git a/sim/testsuite/sim/bfin/hwloop-nested.s b/sim/testsuite/sim/bfin/hwloop-nested.s deleted file mode 100644 index 9d1b71c..0000000 --- a/sim/testsuite/sim/bfin/hwloop-nested.s +++ /dev/null @@ -1,33 +0,0 @@ -# Blackfin testcase for overlapping nested hwloops (LB) -# mach: bfin - - .include "testutils.inc" - - start - - R0 = 0; - R1 = 0; - P0 = 2; - P1 = 2; - LSETUP (1f, 3f) LC0 = P0; -1: R0 += 1; - - LSETUP (2f, 3f) LC1 = P1; -2: R1 += 1; - - CC = R1 == 2; - IF !CC JUMP 3f; - CC = R0 == 1; - IF !CC JUMP fail; - R3 = LC0; - CC = R3 == 2; - IF !CC JUMP fail; - R3 = LC1; - CC = R3 == 1; - IF !CC JUMP fail; - pass - -3: nop; - -fail: - fail diff --git a/sim/testsuite/sim/bfin/i0.s b/sim/testsuite/sim/bfin/i0.s deleted file mode 100644 index 89c7fd5..0000000 --- a/sim/testsuite/sim/bfin/i0.s +++ /dev/null @@ -1,57 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - - R0.L = 0x1234; - R0.H = 0x7765; - DBGA ( R0.L , 0x1234 ); - DBGA ( R0.H , 0x7765 ); - R0.L = -1; - DBGA ( R0.H , 0x7765 ); - DBGA ( R0.L , 0xffff ); - - R0.L = 0x5555; - R0.H = 0xAAAA; - DBGA ( R0.H , 0xAAAA ); - DBGA ( R0.L , 0x5555 ); - - I0.L = 0x1234; - I0.H = 0x256; - R0 = I0; - DBGA ( R0.L , 0x1234 ); - DBGA ( R0.H , 0x256 ); - - R0 = -50; - R1 = -77 (X); - R2 = -99 (X); - R3 = 32767 (X); - R4 = -32768 (X); - R5 = 256 (X); - R6 = 128 (X); - R7 = 1023 (X); - DBGA ( R0.L , 0xffce ); - DBGA ( R1.L , 0xffb3 ); - DBGA ( R2.L , 0xff9d ); - DBGA ( R3.L , 0x7fff ); - DBGA ( R4.L , 0x8000 ); - DBGA ( R5.L , 256 ); - DBGA ( R6.L , 128 ); - DBGA ( R7.L , 1023 ); - - R6 = -1; - DBGA ( R6.L , 0xffff ); - - R0.L = 0x5555; - R1.L = 0xaaaa; - - DBGA ( R0.L , 0x5555 ); - DBGA ( R1.L , 0xaaaa ); - - R0 = R0 + R1; - DBGA ( R0.H , 0xfffe ); - - pass diff --git a/sim/testsuite/sim/bfin/iir.s b/sim/testsuite/sim/bfin/iir.s deleted file mode 100644 index b1cb420..0000000 --- a/sim/testsuite/sim/bfin/iir.s +++ /dev/null @@ -1,207 +0,0 @@ -# mach: bfin - -// GENERIC BIQUAD: -// --------------- -// x ---------+---------|---------+-------y -// | |t1 | -// | D | -// | a1 | b1 | -// +---<-----|---->----+ -// | | | -// | D | D's are delays -// | a2 | b2 | ">" represent multiplications -// +---<-----|---->----+ -// To test this routine, use a biquad with a pole pair at z = (0.7 +- 0.1j), -// and a double zero at z = -1.0, which is a low-pass. The transfer function is: -// 1 + 2z^-1 + z^-2 -// H(z) = ---------------------- -// 1 - 1.4z^-1 + 0.5z^-2 -// a1 = 1.4 -// a2 = -0.5 -// b1 = 2 -// b2 = 1 -// This filter conforms to the biquad test in BDT, since it has coefficients -// larger than 1.0 in magnitude, and b0=1. (Note that the a's have a negative -// sign.) -// This filter can be simulated in matlab. To simulate one biquad, use -// A = [1.0, -1.4, 0.5] -// B = [1, 2, 1] -// Y=filter(B,A,X) -// To simulate two cascaded biquads, use -// Y=filter(B,A,filter(B,A,X)) -// SCALED COEFFICIENTS: -// -------------------- -// In order to conform to 1.15 representation, must scale coeffs by 0.5. -// This requires an additional internal re-scale. The equations for the Type II -// filter are: -// t1 = x + a1*t1*z^-1 + a2*t1*z^-2 -// y = b0*t1 + b1*t1*z^-1 + b2*t1*z^-2 -// (Note inclusion of term b0, which in the example is b0 = 1.) -// If all coeffs are replaced by -// ai --> ai' = 0.5*a1 -// then the two equations become -// t1 = x + 2*a1'*t1*z^-1 + 2*a2'*t1*z^-2 -// 0.5*y = b0'*t1 + b1'*t1*z^-1 + b2'*t1*z^-2 -// which can be implemented as: -// 2.0 b0'=0.5 -// x ---------+--->-----|---->----+-------y -// | |t1 | -// | D | -// | a1' | b1' | -// +---<-----|---->----+ -// | | | -// | D | -// | a2' | b2' | -// +---<-----|---->----+ -// But, b0' can be eliminated by: -// x ---------+---------|---------+-------y -// | | | -// | V 2.0 | -// | | | -// | |t1 | -// | D | -// | a1' | b1' | -// +---<-----|---->----+ -// | | | -// | D | -// | a2' | b2' | -// +---<-----|---->----+ -// Function biquadf() computes this implementation on float data. -// CASCADED BIQUADS -// ---------------- -// Cascaded biquads are simulated by simply cascading copies of the -// filter defined above. However, one must be careful with the resulting -// filter, as it is not very stable numerically (double poles in the -// vecinity of +1). It would of course be better to cascade different -// filters, as that would result in more stable structures. -// The functions biquadf() and biquadR() have been tested with up to 3 -// stages using this technique, with inputs having small signal amplitude -// (less than 0.001) and under 300 samples. -// -// In order to pipeline, need to maintain two pointers into the state -// array: one to load (I0) and one to store (I2). This is required since -// the load of iteration i+1 is hoisted above the store of iteration i. - -.include "testutils.inc" - start - - - // I3 points to input buffer - loadsym I3, input; - - // P1 points to output buffer - loadsym P1, output; - - R0 = 0; R7 = 0; - - P2 = 10; - LSETUP ( L$0 , L$0end ) LC0 = P2; -L$0: - - // I0 and I2 are pointers to state - loadsym I0, state; - I2 = I0; - - // pointer to coeffs - loadsym I1, Coeff; - - R0.H = W [ I3 ++ ]; // load input value into RH0 - A0.w = R0; // A0 holds x - - P2 = 2; - LSETUP ( L$1 , L$1end ) LC1 = P2; - - // load 2 coeffs into R1 and R2 - // load state into R3 - R1 = [ I1 ++ ]; - MNOP || R2 = [ I1 ++ ] || R3 = [ I0 ++ ]; - -L$1: - - // A1=b1*s0 A0=a1*s0+x - A1 = R1.L * R3.L, A0 += R1.H * R3.L || R1 = [ I1 ++ ] || NOP; - - // A1+=b2*s1 A0+=a2*s1 - // and move scaled value in A0 (t1) into RL4 - A1 += R2.L * R3.H, R4.L = ( A0 += R2.H * R3.H ) (S2RND) || R2 = [ I1 ++ ] || NOP; - - // Advance state. before: - // R4 = uuuu t1 - // R3 = stat[1] stat[0] - // after PACKLL: - // R3 = stat[0] t1 - R5 = PACK( R3.L , R4.L ) || R3 = [ I0 ++ ] || NOP; - - // collect output into A0, and move to RL0. - // Keep output value in A0, since it is also - // the accumulator used to store the input to - // the next stage. Also, store updated state -L$1end: - R0.L = ( A0 += A1 ) || [ I2 ++ ] = R5 || NOP; - - // store output -L$0end: - W [ P1 ++ ] = R0; - - // Check results - loadsym I2, output; - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0028 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0110 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0373 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x075b ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0c00 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1064 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x13d3 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x15f2 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x16b9 ); - R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1650 ); - - pass - - .data -state: - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - - .data -Coeff: - .dw 0x7fff - .dw 0x5999 - .dw 0x4000 - .dw 0xe000 - .dw 0x7fff - .dw 0x5999 - .dw 0x4000 - .dw 0xe000 -input: - .dw 0x0028 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 -output: - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/issue103.s b/sim/testsuite/sim/bfin/issue103.s deleted file mode 100644 index 6244a7f..0000000 --- a/sim/testsuite/sim/bfin/issue103.s +++ /dev/null @@ -1,34 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - A0 = 0; - A1 = 0; - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - R4 = 0; - R5 = 0; - R2.H = 0xf12e; - R2.L = 0xbeaa; - R3.L = 0x00ff; - A1.w = R2; - A1.x = R3; - R0.H = 0xd136; - R0.L = 0x459d; - R1.H = 0xabd6; - R1.L = 0x9ec7; - - _DBG A1; - R5 = A1 , A0 = R1.L * R0.L (FU); - - DBGA ( R5.H , 0xffff ); - DBGA ( R5.L , 0xffff ); - - NOP; - NOP; - NOP; - NOP; - pass diff --git a/sim/testsuite/sim/bfin/issue109.s b/sim/testsuite/sim/bfin/issue109.s deleted file mode 100644 index 65b78b7..0000000 --- a/sim/testsuite/sim/bfin/issue109.s +++ /dev/null @@ -1,16 +0,0 @@ -//Statement of problem... -//16-bit ashift and lshift uses a 6-bit signed magnitude, which gives a -//range from -32 to 31. test the boundary. -# mach: bfin - -.include "testutils.inc" - start - - - R1.L = 0x8000; - R0.L = -32; - R2.L = ASHIFT R1.L BY R0.L; - - DBGA ( R2.L , 0xffff ); - - pass diff --git a/sim/testsuite/sim/bfin/issue112.s b/sim/testsuite/sim/bfin/issue112.s deleted file mode 100644 index e116936..0000000 --- a/sim/testsuite/sim/bfin/issue112.s +++ /dev/null @@ -1,38 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - A0 = 0; - A1 = 0; - R2.H = 0xfafa; - R2.L = 0xf5f6; - R3.L = 0x00ff; - A0.w = R2; - A0.x = R3; - R2.H = 0x7ebc; - R2.L = 0xd051; - R3 = 0; - A1.w = R2; - A1.x = R3; - R1.H = 0x7fff; - R1.L = 0x8000; - R0.H = 0x8000; - R0.L = 0x7fff; - A1 += R0.L * R1.L (M), R0.L = ( A0 = R0.H * R1.H ) (IH); - - _DBG A1; - R0 = A1.w; - R1 = A1.x; - DBGA ( R0.L , 0xffff ); - DBGA ( R0.H , 0x7fff ); - DBGA ( R1.L , 0 ); - - NOP; - NOP; - pass diff --git a/sim/testsuite/sim/bfin/issue113.s b/sim/testsuite/sim/bfin/issue113.s deleted file mode 100644 index 4bebaea..0000000 --- a/sim/testsuite/sim/bfin/issue113.s +++ /dev/null @@ -1,18 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - A0 = 0; - R0.L = 0x10; - A0.x = R0; - - R0.L = 0x0038; - R0.H = 0x0006; - - R0.L = SIGNBITS A0; - - DBGA ( R0.L , 0xfffa ); - DBGA ( R0.H , 0x0006 ); - - pass diff --git a/sim/testsuite/sim/bfin/issue117.s b/sim/testsuite/sim/bfin/issue117.s deleted file mode 100644 index 00e92b7..0000000 --- a/sim/testsuite/sim/bfin/issue117.s +++ /dev/null @@ -1,19 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - -// issue 117 - - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - A0 = 0; - A1 = 0; - R0.L = 0x0400; - R1.L = 0x0010; - R2.L = ( A0 = R0.L * R1.L ) (S2RND); - - DBGA ( R2.L , 0x1 ); - pass diff --git a/sim/testsuite/sim/bfin/issue118.s b/sim/testsuite/sim/bfin/issue118.s deleted file mode 100644 index bc455b3..0000000 --- a/sim/testsuite/sim/bfin/issue118.s +++ /dev/null @@ -1,41 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - -// issue 118 - - R0 = 1; - R1 = 0; - A0.x = R1; - A0.w = R0; - - A0 = - A0; - - _DBG A0; - _DBG ASTAT; - -//R0 = ASTAT; -//DBGA ( R0.L , 0x2 ); - - cc = az; - r0 = cc; - dbga( r0.l, 0); - cc = an; - r0 = cc; - dbga( r0.l, 1); - cc = av0; - r0 = cc; - dbga( r0.l, 0); - cc = av0s; - r0 = cc; - dbga( r0.l, 0); - cc = av1; - r0 = cc; - dbga( r0.l, 0); - cc = av1s; - r0 = cc; - dbga( r0.l, 0); - - pass diff --git a/sim/testsuite/sim/bfin/issue119.s b/sim/testsuite/sim/bfin/issue119.s deleted file mode 100644 index ade8818..0000000 --- a/sim/testsuite/sim/bfin/issue119.s +++ /dev/null @@ -1,26 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - R0.L = -32768; - R0.H = 32767; - R1.L = 32767; - R1.H = -32768; - R2.H = (A1 = R0.L * R1.H) (M), R2.L = (A0 = R0.L * R1.L) (TFU); - - _DBG R2; - DBGA ( R2.L , 0x3fff ); - DBGA ( R2.H , 0xc000 ); - - R3 = ( A1 = R0.L * R1.H ) (M), R2 = ( A0 = R0.L * R1.L ) (FU); - - _DBG R3; - DBGA ( R3.L , 0 ); - DBGA ( R3.H , 0xc000 ); - - pass diff --git a/sim/testsuite/sim/bfin/issue121.s b/sim/testsuite/sim/bfin/issue121.s deleted file mode 100644 index 7e609cd..0000000 --- a/sim/testsuite/sim/bfin/issue121.s +++ /dev/null @@ -1,40 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - R0.L = 32767; - R0.H = 32767; - R1.L = -32768; - R1.H = -32768; - R0.L = R0 + R1 (RND12); - - _DBG R0; - _DBG ASTAT; -//R1 = ASTAT; -//_DBG R1; - -//DBGA ( R1.H , 0x0 ); -//DBGA ( R1.L , 0x0001 ); - cc = az; - r0 = cc; - dbga( r0.l, 1); - cc = an; - r0 = cc; - dbga( r0.l, 0); - cc = av0; - r0 = cc; - dbga( r0.l, 0); - cc = av0s; - r0 = cc; - dbga( r0.l, 0); - cc = av1; - r0 = cc; - dbga( r0.l, 0); - cc = av1s; - r0 = cc; - dbga( r0.l, 0); - - pass diff --git a/sim/testsuite/sim/bfin/issue123.s b/sim/testsuite/sim/bfin/issue123.s deleted file mode 100644 index 9f40c3f..0000000 --- a/sim/testsuite/sim/bfin/issue123.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - R0.L = 0x7bb8; - R0.H = 0x8d5e; - R4.L = 0x7e1c; - R4.H = 0x9e22; -// end load regs and acc; - R6.H = R4.H * R0.L (M), R6.L = R4.L * R0.H (ISS2); - - _DBG R6; - - DBGA ( R6.L , 0x8000 ); - DBGA ( R6.H , 0x8000 ); - -//------------- - - pass diff --git a/sim/testsuite/sim/bfin/issue124.s b/sim/testsuite/sim/bfin/issue124.s deleted file mode 100644 index b28f141..0000000 --- a/sim/testsuite/sim/bfin/issue124.s +++ /dev/null @@ -1,26 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - -// issue 124 - - R0 = 0; - R1.L = 0x80; - - A0.w = R0; - A0.x = R1; - - A1.w = R0; - A1.x = R1; - - _DBG A0; - _DBG A1; - - R5 = ( A0 += A1 ); - - _DBG A0; - R7 = A0.w; DBGA ( R7.H , 0 ); DBGA ( R7.L , 0 ); - R7 = A0.x; DBGA ( R7.L , 0xff80 ); - - pass diff --git a/sim/testsuite/sim/bfin/issue125.s b/sim/testsuite/sim/bfin/issue125.s deleted file mode 100644 index 826bf7f..0000000 --- a/sim/testsuite/sim/bfin/issue125.s +++ /dev/null @@ -1,75 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - A0 = 0; - A1 = 0; - R0 = -1; - R1 = 0; - R1.L = 0x007f; - A0.w = R0; - A0.x = R1; - A1.w = R0; - A1.x = R1; - _DBG A0; - _DBG A1; - _DBG astat; - A0 += A1; - - _DBG A0; -// _DBG ASTAT; -// R0 = ASTAT; -// _DBG R0; -// DBGA ( R0.L , 0x0 ); -// DBGA ( R0.H , 0x3 ); - cc = az; - r0 = cc; - dbga( r0.l, 0); - cc = an; - r0 = cc; - dbga( r0.l, 0); - cc = av0; - r0 = cc; - dbga( r0.l, 1); - cc = av0s; - r0 = cc; - dbga( r0.l, 1); - cc = av1; - r0 = cc; - dbga( r0.l, 0); - cc = av1s; - r0 = cc; - dbga( r0.l, 0); - - A1 = 0; - _DBG A0; - A0 += A1; - - _DBG A0; -// _DBG ASTAT; -// R0 = ASTAT; -// _DBG R0; - -// DBGA ( R0.L , 0 ); -// DBGA ( R0.H , 2 ); - cc = az; - r0 = cc; - dbga( r0.l, 0); - cc = an; - r0 = cc; - dbga( r0.l, 0); - cc = av0; - r0 = cc; - dbga( r0.l, 0); - cc = av0s; - r0 = cc; - dbga( r0.l, 1); - cc = av1; - r0 = cc; - dbga( r0.l, 0); - cc = av1s; - r0 = cc; - dbga( r0.l, 0); - - pass diff --git a/sim/testsuite/sim/bfin/issue126.s b/sim/testsuite/sim/bfin/issue126.s deleted file mode 100644 index ff15bac..0000000 --- a/sim/testsuite/sim/bfin/issue126.s +++ /dev/null @@ -1,19 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - P1 = R0; - P2 = R0; - - R0 = R0; - P1 = ( P1 + P0 ) << 2; - P2 = ( P2 + P0 ) << 1; - - _DBG ASTAT; - R5 = ASTAT; - DBGA ( R5.H , 0 ); DBGA ( R5.L , 0 ); - - pass diff --git a/sim/testsuite/sim/bfin/issue127.s b/sim/testsuite/sim/bfin/issue127.s deleted file mode 100644 index 811bc37..0000000 --- a/sim/testsuite/sim/bfin/issue127.s +++ /dev/null @@ -1,35 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - -// load acc with values; - R0.L = 0x5d8c; - R0.H = 0x90c4; - A0.w = R0; - R0.L = 0x8308; - A0.x = R0; - R0.L = 0x32da; - R0.H = 0xa6ec; - A1.w = R0; - R0.L = 0x1772; - A1.x = R0; -// load regs with values; - R0.L = 0x83de; - R0.H = 0x7070; - R1.L = 0x8b86; - R1.H = 0x85ac; - R2.L = 0x2398; - R2.H = 0x3adc; - R3.L = 0x1480; - R3.H = 0x7f90; -// end load regs and acc; - SAA ( R1:0 , R3:2 ) (R); - - _DBG A0; - _DBG A1; - - R0 = A0.x; DBGA ( R0.L , 0 ); - R0 = A1.x; DBGA ( R0.L , 0 ); - - pass diff --git a/sim/testsuite/sim/bfin/issue129.s b/sim/testsuite/sim/bfin/issue129.s deleted file mode 100644 index f9653a8..0000000 --- a/sim/testsuite/sim/bfin/issue129.s +++ /dev/null @@ -1,36 +0,0 @@ -# Blackfin testcase for PREGS and BREV -# mach: bfin - - .include "testutils.inc" - - start - -// issue 129 - - P0.L = 0x0000; - P0.H = 0x8000; - - P4.L = 0x0000; - P4.H = 0x8000; - - P4 += P0 (BREV); - - R0 = P4; - DBGA ( R0.H , 0x4000 ); - DBGA ( R0.L , 0 ); - -//-------------- - - P0.L = 0x0000; - P0.H = 0xE000; - - P4.L = 0x1f09; - P4.H = 0x9008; - - P4 += P0 (BREV); - - R0 = P4; - DBGA ( R0.H , 0x0808 ); - DBGA ( R0.L , 0x1f09 ); - - pass diff --git a/sim/testsuite/sim/bfin/issue139.S b/sim/testsuite/sim/bfin/issue139.S deleted file mode 100644 index 8df28ba..0000000 --- a/sim/testsuite/sim/bfin/issue139.S +++ /dev/null @@ -1,108 +0,0 @@ -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - R4 = 0; - R5 = 0; - R6 = 0; - R7 = 0; - ASTAT = R0; - R0.L = 0x33; - R0.H = 0x55; - R1.L = 0x66; - R1.H = 0x77; - R7 = R1 +|+ R0, R6 = R1 -|- R0 (SCO , ASR); - - _DBG R7; - CHECKREG R7, 0x0066004c; - CHECKREG R6, 0x00190011; - R7 = ASTAT - CHECKREG R7, 0; - -//----------------------- - - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - R4 = 0; - R5 = 0; - R6 = 0; - R7 = 0; - R0.L = 0x33; - R0.H = 0x55; - R1.L = 0x66; - R1.H = 0x77; - R3 = R1 +|+ R0, R2 = R1 -|- R0 (ASR); - - R7 = ASTAT; - CHECKREG R7, 0; - -//----------------------- - - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - R4 = 0; - R5 = 0; - R6 = 0; - R7 = 0; - R0.L = 0x33; - R0.H = 0x55; - R1.L = 0x66; - R1.H = 0x77; - R5 = R1 +|+ R0, R4 = R1 -|- R0 (CO , ASR); - - R7 = ASTAT; - CHECKREG R7, 0; - -//----------------------- - - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - R4 = 0; - R5 = 0; - R6 = 0; - R7 = 0; - R0.L = 0x33; - R0.H = 0x55; - R1.L = 0x66; - R1.H = 0x77; - R3 = R1 +|+ R0, R2 = R1 -|- R0 (ASL); - CHECKREG R3, 0x01980132; - CHECKREG R2, 0x00440066; - - R7 = ASTAT; - CHECKREG R7, 0; - -//----------------------- - - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - R4 = 0; - R5 = 0; - R6 = 0; - R7 = 0; - R0.L = 0x33; - R0.H = 0x55; - R1.L = 0x7fff; - R1.H = 0x77; - R3 = R1 +|+ R0, R2 = R1 -|- R0 (S , ASL); - CHECKREG R3, 0x01987fff; - CHECKREG R2, 0x00447fff; - - R7 = ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/issue140.S b/sim/testsuite/sim/bfin/issue140.S deleted file mode 100644 index df27517..0000000 --- a/sim/testsuite/sim/bfin/issue140.S +++ /dev/null @@ -1,22 +0,0 @@ -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - - R6.L = -32768; - R6.H = -32768; - R1.L = -32768; - R1.H = -32768; - - R4 = R6.L * R1.H; - - _DBG ASTAT; - - R7 = ASTAT; - CHECKREG R7, (_VS|_V|_V_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/issue142.s b/sim/testsuite/sim/bfin/issue142.s deleted file mode 100644 index be290b5..0000000 --- a/sim/testsuite/sim/bfin/issue142.s +++ /dev/null @@ -1,34 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - -// load acc with values; - imm32 R0, 0x7d647b42; - A0.w = R0; - R0 = 0x0000 (Z); - A0.x = R0; - - imm32 R0, 0x7be27f50; - A1.w = R0; - R0 = 0x0000 (Z); - A1.x = R0; - -// load regs with values; - I1 = 0 (X); - I0 = 1 (X); - imm32 R2, 0xefef1212; - imm32 R3, 0xf23c0189; - - SAA ( R3:2 , R3:2 ) (R); - - R0 = A0.w - CHECKREG R0, 0x7d9f7bca; - R0 = A0.x - CHECKREG R0, 0; - R1 = A1.w; - CHECKREG R1, 0x7cc28006; - R1 = A1.x; - CHECKREG R1, 0; - - pass diff --git a/sim/testsuite/sim/bfin/issue144.s b/sim/testsuite/sim/bfin/issue144.s deleted file mode 100644 index 3c029a3..0000000 --- a/sim/testsuite/sim/bfin/issue144.s +++ /dev/null @@ -1,31 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - a0=0; - R0.L = 1; - R0.H = 0; - R0 *= R0; - _DBG R0; - _DBG A0; - - R7 = A0.w; - DBGA ( R7.H , 0 ); DBGA ( R7.L , 0 ); - - R0.L = -1; - R0.H = 32767; - - _DBG R0; - - a0=0; - R0 *= R0; - - _DBG R0; - _DBG A0; - R7 = A0.w; - DBGA ( R7.H , 0 ); DBGA ( R7.L , 0 ); - R7 = A0.x; - DBGA ( R7.L , 0x0 ); - - pass diff --git a/sim/testsuite/sim/bfin/issue146.S b/sim/testsuite/sim/bfin/issue146.S deleted file mode 100644 index b14e78c..0000000 --- a/sim/testsuite/sim/bfin/issue146.S +++ /dev/null @@ -1,32 +0,0 @@ -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - -// razor issue 146 - - A0 = 0; - A1 = 0; - R0 = 0; - ASTAT = R0; - R1 = 0; - R0.L = 0x891b; - R0.H = 0x8537; - R1.L = 0xab2d; - R1.H = 0x3759; - A0 = R0; - A1 = R1; - - _DBG A0; - _DBG A1; - - R3 = A1 + A0, R7 = A1 - A0 (S); - _DBG R3; - _DBG R7; - - _DBG ASTAT; - R0 = ASTAT; - CHECKREG R0, (_VS|_V|_V_COPY|_AN); - - pass diff --git a/sim/testsuite/sim/bfin/issue175.s b/sim/testsuite/sim/bfin/issue175.s deleted file mode 100644 index 3073823..0000000 --- a/sim/testsuite/sim/bfin/issue175.s +++ /dev/null @@ -1,34 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - R0 = 0; - ASTAT = R0; - imm32 R1, 0x80007fff; - imm32 R0, 0x00010001; - R0 = R1 +|+ R0, R2 = R1 -|- R0 (S , ASL); - _DBG R0; - _DBG R2; - CHECKREG R0, 0x80007fff; - CHECKREG R2, 0x80007fff; - - R0 = ASTAT; - _dbg r0; - DBGA ( R0.L , 0x000a ); - DBGA ( R0.H , 0x0300 ); - - R0 = 0; - R1 = 0; - R4 = 0; - ASTAT = R0; - R4 = R1 +|+ R0, R0 = R1 -|- R0 (S , ASL); - _DBG R4; - _DBG R0; - R7 = ASTAT; - _DBG R7; - _DBG ASTAT; - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0000 ); - - pass diff --git a/sim/testsuite/sim/bfin/issue205.s b/sim/testsuite/sim/bfin/issue205.s deleted file mode 100644 index 44cb1e0..0000000 --- a/sim/testsuite/sim/bfin/issue205.s +++ /dev/null @@ -1,66 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - R0 = 0; R1 = 0; R2 = 0; R3 = 0; R4 = 0; R5 = 0; R6 = 0; R7 = 0; - P0 = 0; P1 = 0; P2 = 0; P4 = 0; P5 = 0; - I0 = 0 (X); I1 = 0 (X); I2 = 0 (X); I3 = 0 (X); - M0 = 0 (X); M1 = 0 (X); M2 = 0 (X); M3 = 0 (X); - L0 = 0 (X); L1 = 0 (X); L2 = 0 (X); L3 = 0 (X); - B0 = 0 (X); B1 = 0 (X); B2 = 0 (X); B3 = 0 (X); - - R0 = -1; - R1 = 0x1234 (X); - R2 = -2000 (X); - R3 = 2000 (X); - R4 = 0; - R5 = 1; - R6 = 5555 (X); - R7 = -1000 (X); - - loadsym P1, tmp0; - loadsym P2, tmp1; - loadsym P4, tmp2; - - I1 = P1; - I2 = P2; - I3 = P4; - - - R0.L = 0x0017; - R0.H = 0xffff; - R0.L = EXPADJ( R2 , R1.L ) || [ P2 ] = R0 || NOP; - R6 = [ P2 ]; - DBGA ( R6.L , 0x17 ); - DBGA ( R6.H , 0xffff ); - - DBGA ( R0.L , 0x1234 ); - DBGA ( R0.H , 0xffff ); - - pass - - .data -tmp0: - .dd 0x12345678 // 0x1000 - .dd 0x10101010 // 0x1004 - .dd 0x55555555 // 0x1008 - .dd 0xaaaaaaaa // 0x100c - .dd 0xffffffff // 0x1010 - - .data -tmp1: - .dd 0xabcdefef // 0x2000 - .dd 0x12121212 // 0x2004 - .dd 0x45454545 // 0x2008 - .dd 0xabababab // 0x200c - .dd 0x0f0f0f0f // 0x2010 - - .data -tmp2: - .dd 0xff00ff00 // 0x3000 - .dd 0x02020202 // 0x3004 - .dd 0x4f4f4f45 // 0x3008 - .dd 0xafafafaf // 0x300c - .dd 0x1f1f1f1f // 0x3010 diff --git a/sim/testsuite/sim/bfin/issue257.s b/sim/testsuite/sim/bfin/issue257.s deleted file mode 100644 index 01f0396..0000000 --- a/sim/testsuite/sim/bfin/issue257.s +++ /dev/null @@ -1,28 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - R0 = 0; - R1 = 0; - R2 = 0; - R0.H = 0xfffe; - R0.L = 0x9be8; - R1.L = 0xeb53; - R2.H = R0 - R1 (RND20); - - _DBG R2; - _DBG ASTAT; - DBGA ( R2.H , 0 ); - - R0 = ASTAT; -//DBGA ( R0.L , 1 ); - cc = az; - r0 = cc; - dbga( r0.l, 1); - cc = an; - r0 = cc; - dbga( r0.l, 0); - - pass diff --git a/sim/testsuite/sim/bfin/issue272.S b/sim/testsuite/sim/bfin/issue272.S deleted file mode 100644 index ee8ec38..0000000 --- a/sim/testsuite/sim/bfin/issue272.S +++ /dev/null @@ -1,23 +0,0 @@ -// When the RND12 instruction produces large negative results, the AV0 flag is -// should not be set. -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - - R0.H = 0xcef4; - R0.L = 0x3ed6; - R1.H = 0x56f4; - R1.L = 0x417a; - R2.H = R0 - R1 (RND12); - - _DBG ASTAT; - R0 = ASTAT; - CHECKREG R0, (_VS|_V|_V_COPY|_AN); - CHECKREG R2, 0x80000000; - - pass diff --git a/sim/testsuite/sim/bfin/issue83.s b/sim/testsuite/sim/bfin/issue83.s deleted file mode 100644 index 2474d4b..0000000 --- a/sim/testsuite/sim/bfin/issue83.s +++ /dev/null @@ -1,93 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - R0.H = -32768; - R0.L = 0; - R0 >>= 0x1; - - _DBG R0; - R7 = ASTAT; - _DBG R7; - -//DBGA ( R7.H , 0x0000 ); -//DBGA ( R7.L , 0x0000 ); - cc = az; - r0 = cc; - dbga( r0.l, 0); - cc = an; - r0 = cc; - dbga( r0.l, 0); - cc = av0; - r0 = cc; - dbga( r0.l, 0); - cc = av0s; - r0 = cc; - dbga( r0.l, 0); - cc = av1; - r0 = cc; - dbga( r0.l, 0); - cc = av1s; - r0 = cc; - dbga( r0.l, 0); - - R0.H = 0; - R0.L = 1; - R0 <<= 0x1f; - - _DBG R0; - R7 = ASTAT; - _DBG R7; -//DBGA ( R7.H , 0x0000 ); -//DBGA ( R7.L , 0x0002 ); - cc = az; - r0 = cc; - dbga( r0.l, 0); - cc = an; - r0 = cc; - dbga( r0.l, 1); - cc = av0; - r0 = cc; - dbga( r0.l, 0); - cc = av0s; - r0 = cc; - dbga( r0.l, 0); - cc = av1; - r0 = cc; - dbga( r0.l, 0); - cc = av1s; - r0 = cc; - dbga( r0.l, 0); - - R1.L = -1; - R1.H = 32767; - R0 = 31; - R1 >>= R0; - - _DBG R1; - R7 = ASTAT; - _DBG R7; -//DBGA ( R7.H , 0x0000 ); -//DBGA ( R7.L , 0x0001 ); - cc = az; - r0 = cc; - dbga( r0.l, 1); - cc = an; - r0 = cc; - dbga( r0.l, 0); - cc = av0; - r0 = cc; - dbga( r0.l, 0); - cc = av0s; - r0 = cc; - dbga( r0.l, 0); - cc = av1; - r0 = cc; - dbga( r0.l, 0); - cc = av1s; - r0 = cc; - dbga( r0.l, 0); - - pass diff --git a/sim/testsuite/sim/bfin/issue89.s b/sim/testsuite/sim/bfin/issue89.s deleted file mode 100644 index 24d0517..0000000 --- a/sim/testsuite/sim/bfin/issue89.s +++ /dev/null @@ -1,30 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - - R2.L = 0x000f; - R2.H = 0x038c; - _DBG R2; - - R7.L = 0x007c; - R7.H = 0x0718; - A0 = 0; - A0.w = R7; - _DBG A0; - - A0 = ROT A0 BY R2.L; - - _DBG A0; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x003e ); - DBGA ( R4.L , 0x0001 ); - DBGA ( R5.H , 0xffff ); - DBGA ( R5.L , 0xff8c ); - - pass diff --git a/sim/testsuite/sim/bfin/l0.s b/sim/testsuite/sim/bfin/l0.s deleted file mode 100644 index 88fcb59..0000000 --- a/sim/testsuite/sim/bfin/l0.s +++ /dev/null @@ -1,137 +0,0 @@ -// simple test to ensure that we can load data from memory. -# mach: bfin - -.include "testutils.inc" - start - - loadsym P0, tab; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - R5 = [ P0 ++ ]; - R6 = [ P0 ++ ]; - R7 = [ P0 ++ ]; - - DBGA ( R0.H , 0x1111 ); - DBGA ( R1.H , 0x2222 ); - DBGA ( R2.H , 0x3333 ); - DBGA ( R3.H , 0x4444 ); - DBGA ( R4.H , 0x5555 ); - DBGA ( R5.H , 0x6666 ); - DBGA ( R6.H , 0x7777 ); - DBGA ( R7.H , 0x8888 ); - - loadsym P0, tab2; - - R0 = W [ P0 ++ ] (Z); - DBGA ( R0.L , 0x1111 ); - - R1 = W [ P0 ++ ] (Z); - DBGA ( R1.L , 0x8888 ); - - R2 = W [ P0 ++ ] (Z); - DBGA ( R2.L , 0x2222 ); - - R3 = W [ P0 ++ ] (Z); - DBGA ( R3.L , 0x7777 ); - - R4 = W [ P0 ++ ] (Z); - DBGA ( R4.L , 0x3333 ); - - R5 = W [ P0 ++ ] (Z); - DBGA ( R5.L , 0x6666 ); - - R0 = B [ P0 ++ ] (Z); - DBGA ( R0.L , 0x44 ); - R1 = B [ P0 ++ ] (Z); - DBGA ( R1.L , 0x44 ); - R2 = B [ P0 ++ ] (Z); - DBGA ( R2.L , 0x55 ); - R3 = B [ P0 ++ ] (Z); - DBGA ( R3.L , 0x55 ); - - R0 = B [ P0 ++ ] (X); - DBGA ( R0.L , 0x55 ); - - R1 = B [ P0 ++ ] (X); - DBGA ( R1.L , 0x55 ); - - R0 = W [ P0 ++ ] (X); - DBGA ( R0.L , 0x4444 ); - - R1 = [ P0 ++ ]; - DBGA ( R1.L , 0x6666 ); - DBGA ( R1.H , 0x3333 ); - - P1 = [ P0 ++ ]; - R0 = P1; - DBGA ( R0.L , 0x7777 ); - DBGA ( R0.H , 0x2222 ); - - P1 = [ P0 ++ ]; - R0 = P1; - DBGA ( R0.L , 0x8888 ); - DBGA ( R0.H , 0x1111 ); - - loadsym P5, tab3; - - R0 = B [ P5 ++ ] (X); - DBGA ( R0.H , 0 ); - DBGA ( R0.L , 0 ); - - R0 = B [ P5 ++ ] (X); - DBGA ( R0.H , 0xffff ); - DBGA ( R0.L , 0xffff ); - - R1 = W [ P5 ++ ] (X); - DBGA ( R1.H , 0xffff ); - DBGA ( R1.L , 0xffff ); - - pass - - .data -tab: - .dw 0 - .dw 0x1111 - .dw 0 - .dw 0x2222 - .dw 0 - .dw 0x3333 - .dw 0 - .dw 0x4444 - .dw 0 - .dw 0x5555 - .dw 0 - .dw 0x6666 - .dw 0 - .dw 0x7777 - .dw 0 - .dw 0x8888 - .dw 0 - .dw 0 - .dw 0 - .dw 0 - -tab2: - .dw 0x1111 - .dw 0x8888 - .dw 0x2222 - .dw 0x7777 - .dw 0x3333 - .dw 0x6666 - .dw 0x4444 - .dw 0x5555 - .dw 0x5555 - .dw 0x4444 - .dw 0x6666 - .dw 0x3333 - .dw 0x7777 - .dw 0x2222 - .dw 0x8888 - .dw 0x1111 - -tab3: - .dw 0xff00 - .dw 0xffff diff --git a/sim/testsuite/sim/bfin/l0shift.s b/sim/testsuite/sim/bfin/l0shift.s deleted file mode 100644 index 3f5dc2c..0000000 --- a/sim/testsuite/sim/bfin/l0shift.s +++ /dev/null @@ -1,13 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - r5 = 0; - r2.L = 0xadbd; - r2.h = 0xfedc; - r5 = r2 >> 0; - dbga (r5.l, 0xadbd); - dbga (r5.h, 0xfedc); - pass diff --git a/sim/testsuite/sim/bfin/l2_loop.s b/sim/testsuite/sim/bfin/l2_loop.s deleted file mode 100644 index a6cde54..0000000 --- a/sim/testsuite/sim/bfin/l2_loop.s +++ /dev/null @@ -1,28 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - p0=10; - loadsym i0, foo; - - R2 = i0; - r0.l = 0x5678; - r0.h = 0x1234; - - lsetup(lstart, lend) lc0=p0; - -lstart: - [i0++] = r0; -lend: - [i0++] = r0; - - r0=i0; - R0 = R0 - R2; - dbga(r0.l, 0x0050); - - pass - - .data -foo: - .space (0x100) diff --git a/sim/testsuite/sim/bfin/link-2.s b/sim/testsuite/sim/bfin/link-2.s deleted file mode 100644 index ac711c6..0000000 --- a/sim/testsuite/sim/bfin/link-2.s +++ /dev/null @@ -1,24 +0,0 @@ -# Blackfin testcase for link/unlink instructions -# mach: bfin - - .include "testutils.inc" - - start - - /* Make sure size arg to LINK works */ - R0 = SP; - LINK 0x20; - R1 = SP; - R1 += 0x8 + 0x20; - CC = R1 == R0; - IF !CC JUMP 1f; - - /* Make sure UNLINK restores old SP */ - UNLINK - R1 = SP; - CC = R1 == R0; - IF !CC JUMP 1f; - - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/link.s b/sim/testsuite/sim/bfin/link.s deleted file mode 100644 index c92ae1b..0000000 --- a/sim/testsuite/sim/bfin/link.s +++ /dev/null @@ -1,67 +0,0 @@ -# Blackfin testcase for link/unlink instructions -# mach: bfin - - .include "testutils.inc" - - start - - /* give FP/RETS known/different values */ - R7.H = 0xdead; - R7.L = 0x1234; - RETS = R7; - R6 = R7; - R6 += 0x23; - FP = R6; - - /* SP should have moved by -8 bytes (to push FP/RETS) */ - R0 = SP; - LINK 0; - R1 = SP; - R1 += 8; - CC = R0 == R1; - IF !CC JUMP 1f; - - /* FP should now have the same value as SP */ - R1 = SP; - R2 = FP; - CC = R1 == R2; - IF !CC JUMP 1f; - - /* make sure FP/RETS on the stack have our known values */ - R1 = [SP]; - CC = R1 == R6; - IF !CC JUMP 1f; - - R1 = [SP + 4]; - CC = R1 == R7; - IF !CC JUMP 1f; - - /* UNLINK should: - * assign SP to current FP - * adjust SP by -8 bytes - * restore RETS/FP from the stack - */ - R4 = 0; - RETS = R4; - R0 = SP; - UNLINK; - - /* Check new SP */ - R1 = SP; - R1 += -0x8; - CC = R1 == R0; - IF !CC JUMP 1f; - - /* Check restored RETS */ - R1 = RETS; - CC = R1 == R7; - IF !CC JUMP 1f; - - /* Check restored FP */ - R1 = FP; - CC = R1 == R6; - IF !CC JUMP 1f; - - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/lmu_cplb_multiple0.S b/sim/testsuite/sim/bfin/lmu_cplb_multiple0.S deleted file mode 100644 index 9399c43..0000000 --- a/sim/testsuite/sim/bfin/lmu_cplb_multiple0.S +++ /dev/null @@ -1,2678 +0,0 @@ -//Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple0/lmu_cplb_multiple0.dsp -// Description: Multiple CPLB Hit exceptions -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) - -//------------------------------------- - -// Test LMU/CPLB exceptions - -// Basic outline: -// Set exception handler -// program CPLB Entries -// Enable CPLB in DMEM_CNTL -// perform access -// verify exception occurred - -CHECK_INIT(p5, 0xEFFFFFFC); - -//------------------------- -// Zero the CPLB Address and Data regs. - - LD32(p0, DCPLB_ADDR0); - R0 = 0; - [ P0 ++ ] = R0; // 0 - [ P0 ++ ] = R0; // 1 - [ P0 ++ ] = R0; // 2 - [ P0 ++ ] = R0; // 3 - [ P0 ++ ] = R0; // 4 - [ P0 ++ ] = R0; // 5 - [ P0 ++ ] = R0; // 6 - [ P0 ++ ] = R0; // 7 - [ P0 ++ ] = R0; // 8 - [ P0 ++ ] = R0; // 9 - [ P0 ++ ] = R0; // 10 - [ P0 ++ ] = R0; // 11 - [ P0 ++ ] = R0; // 12 - [ P0 ++ ] = R0; // 13 - [ P0 ++ ] = R0; // 14 - [ P0 ++ ] = R0; // 15 - - LD32(p0, DCPLB_DATA0); - [ P0 ++ ] = R0; // 0 - [ P0 ++ ] = R0; // 1 - [ P0 ++ ] = R0; // 2 - [ P0 ++ ] = R0; // 3 - [ P0 ++ ] = R0; // 4 - [ P0 ++ ] = R0; // 5 - [ P0 ++ ] = R0; // 6 - [ P0 ++ ] = R0; // 7 - [ P0 ++ ] = R0; // 8 - [ P0 ++ ] = R0; // 9 - [ P0 ++ ] = R0; // 10 - [ P0 ++ ] = R0; // 11 - [ P0 ++ ] = R0; // 12 - [ P0 ++ ] = R0; // 13 - [ P0 ++ ] = R0; // 14 - [ P0 ++ ] = R0; // 15 - - // Now set the CPLB entries we will need - - - - - // Data area for the desired error - WR_MMR(DCPLB_ADDR0, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR1, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR2, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR3, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR4, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR5, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR6, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR7, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR8, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR9, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR10, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR11, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR12, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR13, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR14, 0x10000000, p0, r0); - - // MMR space - WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); - WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); - - // setup interrupt controller with exception handler address - WR_MMR_LABEL(EVT3, handler, p0, r1); - WR_MMR_LABEL(EVT15, int_15, p0, r1); - WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); - WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); - CSYNC; - - // go to user mode. and enable exceptions - LD32_LABEL(r0, User); - RETI = R0; - - // But first raise interrupt 15 so we can do one test - // in supervisor mode. - RAISE 15; - NOP; - - RTI; - - // Nops to work around ICache bug - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - -handler: - // generic protection exception handler - // Inputs: - // p2: addr of CPLB entry to be modified ( current test) - // - // Outputs: - // r4: SEQSTAT - // r5: DCPLB_FAULT_ADDR - // r6: DCPLB_STATUS - // r7: RETX (instruction addr where exception occurred) - - - R4 = SEQSTAT; // Get exception cause - R4 <<= 24; // Clear HWERRCAUSE + SFTRESET - R4 >>= 24; - - // read data addr which caused exception - RD_MMR(DCPLB_FAULT_ADDR, p0, r5); - - RD_MMR(DCPLB_STATUS, p0, r6); - - R7 = RETX; // get address of excepting instruction - - // disable the offending CPLB entries - R2 = 0; - [ P2 ] = R2; - - CSYNC; - - // return from exception and re-execute offending instruction - RTX; - - // Nops to work around ICache bug - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - - -int_15: - // Interrupt 15 handler - test will run in supervisor mode - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x41C6 (Z); - LD32(p2, DCPLB_DATA1); - -X0_1: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB1)); - CHECKREG_SYM(r7, X0_1, r0); // RETX should be value of X0_1 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x167E (Z); - LD32(p2, DCPLB_DATA2); - -X0_2: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB2)); - CHECKREG_SYM(r7, X0_2, r0); // RETX should be value of X0_2 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2781 (Z); - LD32(p2, DCPLB_DATA3); - -X0_3: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB3)); - CHECKREG_SYM(r7, X0_3, r0); // RETX should be value of X0_3 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x446B (Z); - LD32(p2, DCPLB_DATA4); - -X0_4: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB4)); - CHECKREG_SYM(r7, X0_4, r0); // RETX should be value of X0_4 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x794B (Z); - LD32(p2, DCPLB_DATA5); - -X0_5: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB5)); - CHECKREG_SYM(r7, X0_5, r0); // RETX should be value of X0_5 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x15FB (Z); - LD32(p2, DCPLB_DATA6); - -X0_6: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB6)); - CHECKREG_SYM(r7, X0_6, r0); // RETX should be value of X0_6 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x59E2 (Z); - LD32(p2, DCPLB_DATA7); - -X0_7: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB7)); - CHECKREG_SYM(r7, X0_7, r0); // RETX should be value of X0_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1CFB (Z); - LD32(p2, DCPLB_DATA8); - -X0_8: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB8)); - CHECKREG_SYM(r7, X0_8, r0); // RETX should be value of X0_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x3F54 (Z); - LD32(p2, DCPLB_DATA9); - -X0_9: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB9)); - CHECKREG_SYM(r7, X0_9, r0); // RETX should be value of X0_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0FF6 (Z); - LD32(p2, DCPLB_DATA10); - -X0_10: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB10)); - CHECKREG_SYM(r7, X0_10, r0); // RETX should be value of X0_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0ABD (Z); - LD32(p2, DCPLB_DATA11); - -X0_11: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB11)); - CHECKREG_SYM(r7, X0_11, r0); // RETX should be value of X0_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x31DF (Z); - LD32(p2, DCPLB_DATA12); - -X0_12: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB12)); - CHECKREG_SYM(r7, X0_12, r0); // RETX should be value of X0_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x237C (Z); - LD32(p2, DCPLB_DATA13); - -X0_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB13)); - CHECKREG_SYM(r7, X0_13, r0); // RETX should be value of X0_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2F1C (Z); - LD32(p2, DCPLB_DATA14); - -X0_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB14)); - CHECKREG_SYM(r7, X0_14, r0); // RETX should be value of X0_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7DE1 (Z); - LD32(p2, DCPLB_DATA2); - -X1_2: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB2)); - CHECKREG_SYM(r7, X1_2, r0); // RETX should be value of X1_2 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x4487 (Z); - LD32(p2, DCPLB_DATA3); - -X1_3: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB3)); - CHECKREG_SYM(r7, X1_3, r0); // RETX should be value of X1_3 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6201 (Z); - LD32(p2, DCPLB_DATA4); - -X1_4: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB4)); - CHECKREG_SYM(r7, X1_4, r0); // RETX should be value of X1_4 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x52BF (Z); - LD32(p2, DCPLB_DATA5); - -X1_5: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB5)); - CHECKREG_SYM(r7, X1_5, r0); // RETX should be value of X1_5 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6231 (Z); - LD32(p2, DCPLB_DATA6); - -X1_6: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB6)); - CHECKREG_SYM(r7, X1_6, r0); // RETX should be value of X1_6 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x63DE (Z); - LD32(p2, DCPLB_DATA7); - -X1_7: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB7)); - CHECKREG_SYM(r7, X1_7, r0); // RETX should be value of X1_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6956 (Z); - LD32(p2, DCPLB_DATA8); - -X1_8: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB8)); - CHECKREG_SYM(r7, X1_8, r0); // RETX should be value of X1_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1372 (Z); - LD32(p2, DCPLB_DATA9); - -X1_9: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB9)); - CHECKREG_SYM(r7, X1_9, r0); // RETX should be value of X1_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x500F (Z); - LD32(p2, DCPLB_DATA10); - -X1_10: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB10)); - CHECKREG_SYM(r7, X1_10, r0); // RETX should be value of X1_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2847 (Z); - LD32(p2, DCPLB_DATA11); - -X1_11: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB11)); - CHECKREG_SYM(r7, X1_11, r0); // RETX should be value of X1_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2C67 (Z); - LD32(p2, DCPLB_DATA12); - -X1_12: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB12)); - CHECKREG_SYM(r7, X1_12, r0); // RETX should be value of X1_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7566 (Z); - LD32(p2, DCPLB_DATA13); - -X1_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB13)); - CHECKREG_SYM(r7, X1_13, r0); // RETX should be value of X1_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x4287 (Z); - LD32(p2, DCPLB_DATA14); - -X1_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB14)); - CHECKREG_SYM(r7, X1_14, r0); // RETX should be value of X1_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x3359 (Z); - LD32(p2, DCPLB_DATA3); - -X2_3: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB3)); - CHECKREG_SYM(r7, X2_3, r0); // RETX should be value of X2_3 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x4DAA (Z); - LD32(p2, DCPLB_DATA4); - -X2_4: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB4)); - CHECKREG_SYM(r7, X2_4, r0); // RETX should be value of X2_4 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6488 (Z); - LD32(p2, DCPLB_DATA5); - -X2_5: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB5)); - CHECKREG_SYM(r7, X2_5, r0); // RETX should be value of X2_5 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x773C (Z); - LD32(p2, DCPLB_DATA6); - -X2_6: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB6)); - CHECKREG_SYM(r7, X2_6, r0); // RETX should be value of X2_6 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6F59 (Z); - LD32(p2, DCPLB_DATA7); - -X2_7: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB7)); - CHECKREG_SYM(r7, X2_7, r0); // RETX should be value of X2_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6EEA (Z); - LD32(p2, DCPLB_DATA8); - -X2_8: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB8)); - CHECKREG_SYM(r7, X2_8, r0); // RETX should be value of X2_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5656 (Z); - LD32(p2, DCPLB_DATA9); - -X2_9: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB9)); - CHECKREG_SYM(r7, X2_9, r0); // RETX should be value of X2_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6113 (Z); - LD32(p2, DCPLB_DATA10); - -X2_10: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB10)); - CHECKREG_SYM(r7, X2_10, r0); // RETX should be value of X2_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x4A7B (Z); - LD32(p2, DCPLB_DATA11); - -X2_11: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB11)); - CHECKREG_SYM(r7, X2_11, r0); // RETX should be value of X2_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x31D2 (Z); - LD32(p2, DCPLB_DATA12); - -X2_12: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB12)); - CHECKREG_SYM(r7, X2_12, r0); // RETX should be value of X2_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2D85 (Z); - LD32(p2, DCPLB_DATA13); - -X2_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB13)); - CHECKREG_SYM(r7, X2_13, r0); // RETX should be value of X2_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x19A1 (Z); - LD32(p2, DCPLB_DATA14); - -X2_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB14)); - CHECKREG_SYM(r7, X2_14, r0); // RETX should be value of X2_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x69D8 (Z); - LD32(p2, DCPLB_DATA4); - -X3_4: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB4)); - CHECKREG_SYM(r7, X3_4, r0); // RETX should be value of X3_4 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x353C (Z); - LD32(p2, DCPLB_DATA5); - -X3_5: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB5)); - CHECKREG_SYM(r7, X3_5, r0); // RETX should be value of X3_5 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x3B54 (Z); - LD32(p2, DCPLB_DATA6); - -X3_6: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB6)); - CHECKREG_SYM(r7, X3_6, r0); // RETX should be value of X3_6 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7D55 (Z); - LD32(p2, DCPLB_DATA7); - -X3_7: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB7)); - CHECKREG_SYM(r7, X3_7, r0); // RETX should be value of X3_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x102F (Z); - LD32(p2, DCPLB_DATA8); - -X3_8: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB8)); - CHECKREG_SYM(r7, X3_8, r0); // RETX should be value of X3_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1B37 (Z); - LD32(p2, DCPLB_DATA9); - -X3_9: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB9)); - CHECKREG_SYM(r7, X3_9, r0); // RETX should be value of X3_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7AAE (Z); - LD32(p2, DCPLB_DATA10); - -X3_10: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB10)); - CHECKREG_SYM(r7, X3_10, r0); // RETX should be value of X3_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5E65 (Z); - LD32(p2, DCPLB_DATA11); - -X3_11: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB11)); - CHECKREG_SYM(r7, X3_11, r0); // RETX should be value of X3_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x345B (Z); - LD32(p2, DCPLB_DATA12); - -X3_12: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB12)); - CHECKREG_SYM(r7, X3_12, r0); // RETX should be value of X3_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x63DA (Z); - LD32(p2, DCPLB_DATA13); - -X3_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB13)); - CHECKREG_SYM(r7, X3_13, r0); // RETX should be value of X3_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6102 (Z); - LD32(p2, DCPLB_DATA14); - -X3_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB14)); - CHECKREG_SYM(r7, X3_14, r0); // RETX should be value of X3_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7A79 (Z); - LD32(p2, DCPLB_DATA5); - -X4_5: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB5)); - CHECKREG_SYM(r7, X4_5, r0); // RETX should be value of X4_5 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0398 (Z); - LD32(p2, DCPLB_DATA6); - -X4_6: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB6)); - CHECKREG_SYM(r7, X4_6, r0); // RETX should be value of X4_6 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x28CC (Z); - LD32(p2, DCPLB_DATA7); - -X4_7: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB7)); - CHECKREG_SYM(r7, X4_7, r0); // RETX should be value of X4_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x60E3 (Z); - LD32(p2, DCPLB_DATA8); - -X4_8: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB8)); - CHECKREG_SYM(r7, X4_8, r0); // RETX should be value of X4_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1F1A (Z); - LD32(p2, DCPLB_DATA9); - -X4_9: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB9)); - CHECKREG_SYM(r7, X4_9, r0); // RETX should be value of X4_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x4B76 (Z); - LD32(p2, DCPLB_DATA10); - -X4_10: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB10)); - CHECKREG_SYM(r7, X4_10, r0); // RETX should be value of X4_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x058E (Z); - LD32(p2, DCPLB_DATA11); - -X4_11: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB11)); - CHECKREG_SYM(r7, X4_11, r0); // RETX should be value of X4_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7A5F (Z); - LD32(p2, DCPLB_DATA12); - -X4_12: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB12)); - CHECKREG_SYM(r7, X4_12, r0); // RETX should be value of X4_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x28D9 (Z); - LD32(p2, DCPLB_DATA13); - -X4_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB13)); - CHECKREG_SYM(r7, X4_13, r0); // RETX should be value of X4_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0799 (Z); - LD32(p2, DCPLB_DATA14); - -X4_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB14)); - CHECKREG_SYM(r7, X4_14, r0); // RETX should be value of X4_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x388F (Z); - LD32(p2, DCPLB_DATA6); - -X5_6: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB6)); - CHECKREG_SYM(r7, X5_6, r0); // RETX should be value of X5_6 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x751F (Z); - LD32(p2, DCPLB_DATA7); - -X5_7: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB7)); - CHECKREG_SYM(r7, X5_7, r0); // RETX should be value of X5_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x493F (Z); - LD32(p2, DCPLB_DATA8); - -X5_8: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB8)); - CHECKREG_SYM(r7, X5_8, r0); // RETX should be value of X5_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0F36 (Z); - LD32(p2, DCPLB_DATA9); - -X5_9: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB9)); - CHECKREG_SYM(r7, X5_9, r0); // RETX should be value of X5_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x48EE (Z); - LD32(p2, DCPLB_DATA10); - -X5_10: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB10)); - CHECKREG_SYM(r7, X5_10, r0); // RETX should be value of X5_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2043 (Z); - LD32(p2, DCPLB_DATA11); - -X5_11: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB11)); - CHECKREG_SYM(r7, X5_11, r0); // RETX should be value of X5_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x3F78 (Z); - LD32(p2, DCPLB_DATA12); - -X5_12: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB12)); - CHECKREG_SYM(r7, X5_12, r0); // RETX should be value of X5_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1E4D (Z); - LD32(p2, DCPLB_DATA13); - -X5_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB13)); - CHECKREG_SYM(r7, X5_13, r0); // RETX should be value of X5_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x3D0D (Z); - LD32(p2, DCPLB_DATA14); - -X5_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB14)); - CHECKREG_SYM(r7, X5_14, r0); // RETX should be value of X5_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x33FA (Z); - LD32(p2, DCPLB_DATA7); - -X6_7: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB7)); - CHECKREG_SYM(r7, X6_7, r0); // RETX should be value of X6_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6FBE (Z); - LD32(p2, DCPLB_DATA8); - -X6_8: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB8)); - CHECKREG_SYM(r7, X6_8, r0); // RETX should be value of X6_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x36A6 (Z); - LD32(p2, DCPLB_DATA9); - -X6_9: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB9)); - CHECKREG_SYM(r7, X6_9, r0); // RETX should be value of X6_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2DDA (Z); - LD32(p2, DCPLB_DATA10); - -X6_10: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB10)); - CHECKREG_SYM(r7, X6_10, r0); // RETX should be value of X6_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x30E4 (Z); - LD32(p2, DCPLB_DATA11); - -X6_11: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB11)); - CHECKREG_SYM(r7, X6_11, r0); // RETX should be value of X6_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0586 (Z); - LD32(p2, DCPLB_DATA12); - -X6_12: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB12)); - CHECKREG_SYM(r7, X6_12, r0); // RETX should be value of X6_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x148E (Z); - LD32(p2, DCPLB_DATA13); - -X6_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB13)); - CHECKREG_SYM(r7, X6_13, r0); // RETX should be value of X6_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x42DC (Z); - LD32(p2, DCPLB_DATA14); - -X6_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB14)); - CHECKREG_SYM(r7, X6_14, r0); // RETX should be value of X6_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5929 (Z); - LD32(p2, DCPLB_DATA8); - -X7_8: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB8)); - CHECKREG_SYM(r7, X7_8, r0); // RETX should be value of X7_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0C6D (Z); - LD32(p2, DCPLB_DATA9); - -X7_9: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB9)); - CHECKREG_SYM(r7, X7_9, r0); // RETX should be value of X7_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x334E (Z); - LD32(p2, DCPLB_DATA10); - -X7_10: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB10)); - CHECKREG_SYM(r7, X7_10, r0); // RETX should be value of X7_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x62FF (Z); - LD32(p2, DCPLB_DATA11); - -X7_11: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB11)); - CHECKREG_SYM(r7, X7_11, r0); // RETX should be value of X7_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1F56 (Z); - LD32(p2, DCPLB_DATA12); - -X7_12: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB12)); - CHECKREG_SYM(r7, X7_12, r0); // RETX should be value of X7_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2BE1 (Z); - LD32(p2, DCPLB_DATA13); - -X7_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB13)); - CHECKREG_SYM(r7, X7_13, r0); // RETX should be value of X7_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1D70 (Z); - LD32(p2, DCPLB_DATA14); - -X7_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB14)); - CHECKREG_SYM(r7, X7_14, r0); // RETX should be value of X7_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2620 (Z); - LD32(p2, DCPLB_DATA9); - -X8_9: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA8, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB9)); - CHECKREG_SYM(r7, X8_9, r0); // RETX should be value of X8_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x26FB (Z); - LD32(p2, DCPLB_DATA10); - -X8_10: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA8, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB10)); - CHECKREG_SYM(r7, X8_10, r0); // RETX should be value of X8_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x718F (Z); - LD32(p2, DCPLB_DATA11); - -X8_11: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA8, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB11)); - CHECKREG_SYM(r7, X8_11, r0); // RETX should be value of X8_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x04B1 (Z); - LD32(p2, DCPLB_DATA12); - -X8_12: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA8, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB12)); - CHECKREG_SYM(r7, X8_12, r0); // RETX should be value of X8_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5358 (Z); - LD32(p2, DCPLB_DATA13); - -X8_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA8, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB13)); - CHECKREG_SYM(r7, X8_13, r0); // RETX should be value of X8_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x3305 (Z); - LD32(p2, DCPLB_DATA14); - -X8_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA8, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB14)); - CHECKREG_SYM(r7, X8_14, r0); // RETX should be value of X8_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5690 (Z); - LD32(p2, DCPLB_DATA10); - -X9_10: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA9, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB10)); - CHECKREG_SYM(r7, X9_10, r0); // RETX should be value of X9_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5DC5 (Z); - LD32(p2, DCPLB_DATA11); - -X9_11: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA9, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB11)); - CHECKREG_SYM(r7, X9_11, r0); // RETX should be value of X9_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7809 (Z); - LD32(p2, DCPLB_DATA12); - -X9_12: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA9, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB12)); - CHECKREG_SYM(r7, X9_12, r0); // RETX should be value of X9_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1DDC (Z); - LD32(p2, DCPLB_DATA13); - -X9_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA9, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB13)); - CHECKREG_SYM(r7, X9_13, r0); // RETX should be value of X9_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6B53 (Z); - LD32(p2, DCPLB_DATA14); - -X9_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA9, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB14)); - CHECKREG_SYM(r7, X9_14, r0); // RETX should be value of X9_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7BCD (Z); - LD32(p2, DCPLB_DATA11); - -X10_11: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA10, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB11)); - CHECKREG_SYM(r7, X10_11, r0); // RETX should be value of X10_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x63AA (Z); - LD32(p2, DCPLB_DATA12); - -X10_12: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA10, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB12)); - CHECKREG_SYM(r7, X10_12, r0); // RETX should be value of X10_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x373B (Z); - LD32(p2, DCPLB_DATA13); - -X10_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA10, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB13)); - CHECKREG_SYM(r7, X10_13, r0); // RETX should be value of X10_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5648 (Z); - LD32(p2, DCPLB_DATA14); - -X10_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA10, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB14)); - CHECKREG_SYM(r7, X10_14, r0); // RETX should be value of X10_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6799 (Z); - LD32(p2, DCPLB_DATA12); - -X11_12: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA11, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB12)); - CHECKREG_SYM(r7, X11_12, r0); // RETX should be value of X11_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1452 (Z); - LD32(p2, DCPLB_DATA13); - -X11_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA11, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB13)); - CHECKREG_SYM(r7, X11_13, r0); // RETX should be value of X11_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x23D3 (Z); - LD32(p2, DCPLB_DATA14); - -X11_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA11, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB14)); - CHECKREG_SYM(r7, X11_14, r0); // RETX should be value of X11_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1152 (Z); - LD32(p2, DCPLB_DATA13); - -X12_13: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA12, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB13)); - CHECKREG_SYM(r7, X12_13, r0); // RETX should be value of X12_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6E9D (Z); - LD32(p2, DCPLB_DATA14); - -X12_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA12, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB14)); - CHECKREG_SYM(r7, X12_14, r0); // RETX should be value of X12_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6006 (Z); - LD32(p2, DCPLB_DATA14); - -X13_14: [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA13, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB13|FAULT_CPLB14)); - CHECKREG_SYM(r7, X13_14, r0); // RETX should be value of X13_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- -User: - NOP; - dbg_pass; diff --git a/sim/testsuite/sim/bfin/lmu_cplb_multiple1.S b/sim/testsuite/sim/bfin/lmu_cplb_multiple1.S deleted file mode 100644 index cf8cdf4..0000000 --- a/sim/testsuite/sim/bfin/lmu_cplb_multiple1.S +++ /dev/null @@ -1,2680 +0,0 @@ -//Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple1/lmu_cplb_multiple1.dsp -// Description: Multiple CPLB Hit exceptions (DAG1) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) - -//------------------------------------- - -// Test LMU/CPLB exceptions - -// Basic outline: -// Set exception handler -// program CPLB Entries -// Enable CPLB in DMEM_CNTL -// perform access -// verify exception occurred - -CHECK_INIT(p5, 0xEFFFFFFC); - -//------------------------- -// Zero the CPLB Address and Data regs. - - LD32(p0, DCPLB_ADDR0); - R0 = 0; - [ P0 ++ ] = R0; // 0 - [ P0 ++ ] = R0; // 1 - [ P0 ++ ] = R0; // 2 - [ P0 ++ ] = R0; // 3 - [ P0 ++ ] = R0; // 4 - [ P0 ++ ] = R0; // 5 - [ P0 ++ ] = R0; // 6 - [ P0 ++ ] = R0; // 7 - [ P0 ++ ] = R0; // 8 - [ P0 ++ ] = R0; // 9 - [ P0 ++ ] = R0; // 10 - [ P0 ++ ] = R0; // 11 - [ P0 ++ ] = R0; // 12 - [ P0 ++ ] = R0; // 13 - [ P0 ++ ] = R0; // 14 - [ P0 ++ ] = R0; // 15 - - LD32(p0, DCPLB_DATA0); - [ P0 ++ ] = R0; // 0 - [ P0 ++ ] = R0; // 1 - [ P0 ++ ] = R0; // 2 - [ P0 ++ ] = R0; // 3 - [ P0 ++ ] = R0; // 4 - [ P0 ++ ] = R0; // 5 - [ P0 ++ ] = R0; // 6 - [ P0 ++ ] = R0; // 7 - [ P0 ++ ] = R0; // 8 - [ P0 ++ ] = R0; // 9 - [ P0 ++ ] = R0; // 10 - [ P0 ++ ] = R0; // 11 - [ P0 ++ ] = R0; // 12 - [ P0 ++ ] = R0; // 13 - [ P0 ++ ] = R0; // 14 - [ P0 ++ ] = R0; // 15 - - // Now set the CPLB entries we will need - - - - - // Data area for the desired error - WR_MMR(DCPLB_ADDR0, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR1, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR2, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR3, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR4, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR5, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR6, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR7, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR8, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR9, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR10, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR11, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR12, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR13, 0x10000000, p0, r0); - WR_MMR(DCPLB_ADDR14, 0x10000000, p0, r0); - - // MMR space - WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); - WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); - - // setup interrupt controller with exception handler address - WR_MMR_LABEL(EVT3, handler, p0, r1); - WR_MMR_LABEL(EVT15, int_15, p0, r1); - WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); - WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); - CSYNC; - - A0 = 0; - - // go to user mode. and enable exceptions - LD32_LABEL(r0, User); - RETI = R0; - - // But first raise interrupt 15 so we can do one test - // in supervisor mode. - RAISE 15; - NOP; - - RTI; - - // Nops to work around ICache bug - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - -handler: - // generic protection exception handler - // Inputs: - // p2: addr of CPLB entry to be modified ( current test) - // - // Outputs: - // r4: SEQSTAT - // r5: DCPLB_FAULT_ADDR - // r6: DCPLB_STATUS - // r7: RETX (instruction addr where exception occurred) - - - R4 = SEQSTAT; // Get exception cause - R4 <<= 24; // Clear HWERRCAUSE + SFTRESET - R4 >>= 24; - - // read data addr which caused exception - RD_MMR(DCPLB_FAULT_ADDR, p0, r5); - - RD_MMR(DCPLB_STATUS, p0, r6); - - R7 = RETX; // get address of excepting instruction - - // disable the offending CPLB entries - R2 = 0; - [ P2 ] = R2; - - CSYNC; - - // return from exception and re-execute offending instruction - RTX; - - // Nops to work around ICache bug - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - - -int_15: - // Interrupt 15 handler - test will run in supervisor mode - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x41C6 (Z); - LD32(p2, DCPLB_DATA1); - -X0_1: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB1)); - CHECKREG_SYM(r7, X0_1, r0); // RETX should be value of X0_1 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x167E (Z); - LD32(p2, DCPLB_DATA2); - -X0_2: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB2)); - CHECKREG_SYM(r7, X0_2, r0); // RETX should be value of X0_2 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2781 (Z); - LD32(p2, DCPLB_DATA3); - -X0_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB3)); - CHECKREG_SYM(r7, X0_3, r0); // RETX should be value of X0_3 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x446B (Z); - LD32(p2, DCPLB_DATA4); - -X0_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB4)); - CHECKREG_SYM(r7, X0_4, r0); // RETX should be value of X0_4 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x794B (Z); - LD32(p2, DCPLB_DATA5); - -X0_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB5)); - CHECKREG_SYM(r7, X0_5, r0); // RETX should be value of X0_5 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x15FB (Z); - LD32(p2, DCPLB_DATA6); - -X0_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB6)); - CHECKREG_SYM(r7, X0_6, r0); // RETX should be value of X0_6 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x59E2 (Z); - LD32(p2, DCPLB_DATA7); - -X0_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB7)); - CHECKREG_SYM(r7, X0_7, r0); // RETX should be value of X0_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1CFB (Z); - LD32(p2, DCPLB_DATA8); - -X0_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB8)); - CHECKREG_SYM(r7, X0_8, r0); // RETX should be value of X0_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x3F54 (Z); - LD32(p2, DCPLB_DATA9); - -X0_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB9)); - CHECKREG_SYM(r7, X0_9, r0); // RETX should be value of X0_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0FF6 (Z); - LD32(p2, DCPLB_DATA10); - -X0_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB10)); - CHECKREG_SYM(r7, X0_10, r0); // RETX should be value of X0_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0ABD (Z); - LD32(p2, DCPLB_DATA11); - -X0_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB11)); - CHECKREG_SYM(r7, X0_11, r0); // RETX should be value of X0_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x31DF (Z); - LD32(p2, DCPLB_DATA12); - -X0_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB12)); - CHECKREG_SYM(r7, X0_12, r0); // RETX should be value of X0_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x237C (Z); - LD32(p2, DCPLB_DATA13); - -X0_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB13)); - CHECKREG_SYM(r7, X0_13, r0); // RETX should be value of X0_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2F1C (Z); - LD32(p2, DCPLB_DATA14); - -X0_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA0, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB14)); - CHECKREG_SYM(r7, X0_14, r0); // RETX should be value of X0_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7DE1 (Z); - LD32(p2, DCPLB_DATA2); - -X1_2: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB2)); - CHECKREG_SYM(r7, X1_2, r0); // RETX should be value of X1_2 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x4487 (Z); - LD32(p2, DCPLB_DATA3); - -X1_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB3)); - CHECKREG_SYM(r7, X1_3, r0); // RETX should be value of X1_3 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6201 (Z); - LD32(p2, DCPLB_DATA4); - -X1_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB4)); - CHECKREG_SYM(r7, X1_4, r0); // RETX should be value of X1_4 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x52BF (Z); - LD32(p2, DCPLB_DATA5); - -X1_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB5)); - CHECKREG_SYM(r7, X1_5, r0); // RETX should be value of X1_5 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6231 (Z); - LD32(p2, DCPLB_DATA6); - -X1_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB6)); - CHECKREG_SYM(r7, X1_6, r0); // RETX should be value of X1_6 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x63DE (Z); - LD32(p2, DCPLB_DATA7); - -X1_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB7)); - CHECKREG_SYM(r7, X1_7, r0); // RETX should be value of X1_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6956 (Z); - LD32(p2, DCPLB_DATA8); - -X1_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB8)); - CHECKREG_SYM(r7, X1_8, r0); // RETX should be value of X1_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1372 (Z); - LD32(p2, DCPLB_DATA9); - -X1_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB9)); - CHECKREG_SYM(r7, X1_9, r0); // RETX should be value of X1_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x500F (Z); - LD32(p2, DCPLB_DATA10); - -X1_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB10)); - CHECKREG_SYM(r7, X1_10, r0); // RETX should be value of X1_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2847 (Z); - LD32(p2, DCPLB_DATA11); - -X1_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB11)); - CHECKREG_SYM(r7, X1_11, r0); // RETX should be value of X1_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2C67 (Z); - LD32(p2, DCPLB_DATA12); - -X1_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB12)); - CHECKREG_SYM(r7, X1_12, r0); // RETX should be value of X1_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7566 (Z); - LD32(p2, DCPLB_DATA13); - -X1_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB13)); - CHECKREG_SYM(r7, X1_13, r0); // RETX should be value of X1_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x4287 (Z); - LD32(p2, DCPLB_DATA14); - -X1_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA1, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB14)); - CHECKREG_SYM(r7, X1_14, r0); // RETX should be value of X1_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x3359 (Z); - LD32(p2, DCPLB_DATA3); - -X2_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB3)); - CHECKREG_SYM(r7, X2_3, r0); // RETX should be value of X2_3 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x4DAA (Z); - LD32(p2, DCPLB_DATA4); - -X2_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB4)); - CHECKREG_SYM(r7, X2_4, r0); // RETX should be value of X2_4 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6488 (Z); - LD32(p2, DCPLB_DATA5); - -X2_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB5)); - CHECKREG_SYM(r7, X2_5, r0); // RETX should be value of X2_5 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x773C (Z); - LD32(p2, DCPLB_DATA6); - -X2_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB6)); - CHECKREG_SYM(r7, X2_6, r0); // RETX should be value of X2_6 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6F59 (Z); - LD32(p2, DCPLB_DATA7); - -X2_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB7)); - CHECKREG_SYM(r7, X2_7, r0); // RETX should be value of X2_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6EEA (Z); - LD32(p2, DCPLB_DATA8); - -X2_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB8)); - CHECKREG_SYM(r7, X2_8, r0); // RETX should be value of X2_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5656 (Z); - LD32(p2, DCPLB_DATA9); - -X2_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB9)); - CHECKREG_SYM(r7, X2_9, r0); // RETX should be value of X2_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6113 (Z); - LD32(p2, DCPLB_DATA10); - -X2_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB10)); - CHECKREG_SYM(r7, X2_10, r0); // RETX should be value of X2_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x4A7B (Z); - LD32(p2, DCPLB_DATA11); - -X2_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB11)); - CHECKREG_SYM(r7, X2_11, r0); // RETX should be value of X2_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x31D2 (Z); - LD32(p2, DCPLB_DATA12); - -X2_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB12)); - CHECKREG_SYM(r7, X2_12, r0); // RETX should be value of X2_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2D85 (Z); - LD32(p2, DCPLB_DATA13); - -X2_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB13)); - CHECKREG_SYM(r7, X2_13, r0); // RETX should be value of X2_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x19A1 (Z); - LD32(p2, DCPLB_DATA14); - -X2_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA2, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB14)); - CHECKREG_SYM(r7, X2_14, r0); // RETX should be value of X2_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x69D8 (Z); - LD32(p2, DCPLB_DATA4); - -X3_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB4)); - CHECKREG_SYM(r7, X3_4, r0); // RETX should be value of X3_4 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x353C (Z); - LD32(p2, DCPLB_DATA5); - -X3_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB5)); - CHECKREG_SYM(r7, X3_5, r0); // RETX should be value of X3_5 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x3B54 (Z); - LD32(p2, DCPLB_DATA6); - -X3_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB6)); - CHECKREG_SYM(r7, X3_6, r0); // RETX should be value of X3_6 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7D55 (Z); - LD32(p2, DCPLB_DATA7); - -X3_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB7)); - CHECKREG_SYM(r7, X3_7, r0); // RETX should be value of X3_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x102F (Z); - LD32(p2, DCPLB_DATA8); - -X3_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB8)); - CHECKREG_SYM(r7, X3_8, r0); // RETX should be value of X3_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1B37 (Z); - LD32(p2, DCPLB_DATA9); - -X3_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB9)); - CHECKREG_SYM(r7, X3_9, r0); // RETX should be value of X3_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7AAE (Z); - LD32(p2, DCPLB_DATA10); - -X3_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB10)); - CHECKREG_SYM(r7, X3_10, r0); // RETX should be value of X3_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5E65 (Z); - LD32(p2, DCPLB_DATA11); - -X3_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB11)); - CHECKREG_SYM(r7, X3_11, r0); // RETX should be value of X3_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x345B (Z); - LD32(p2, DCPLB_DATA12); - -X3_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB12)); - CHECKREG_SYM(r7, X3_12, r0); // RETX should be value of X3_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x63DA (Z); - LD32(p2, DCPLB_DATA13); - -X3_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB13)); - CHECKREG_SYM(r7, X3_13, r0); // RETX should be value of X3_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6102 (Z); - LD32(p2, DCPLB_DATA14); - -X3_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA3, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB14)); - CHECKREG_SYM(r7, X3_14, r0); // RETX should be value of X3_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7A79 (Z); - LD32(p2, DCPLB_DATA5); - -X4_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB5)); - CHECKREG_SYM(r7, X4_5, r0); // RETX should be value of X4_5 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0398 (Z); - LD32(p2, DCPLB_DATA6); - -X4_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB6)); - CHECKREG_SYM(r7, X4_6, r0); // RETX should be value of X4_6 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x28CC (Z); - LD32(p2, DCPLB_DATA7); - -X4_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB7)); - CHECKREG_SYM(r7, X4_7, r0); // RETX should be value of X4_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x60E3 (Z); - LD32(p2, DCPLB_DATA8); - -X4_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB8)); - CHECKREG_SYM(r7, X4_8, r0); // RETX should be value of X4_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1F1A (Z); - LD32(p2, DCPLB_DATA9); - -X4_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB9)); - CHECKREG_SYM(r7, X4_9, r0); // RETX should be value of X4_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x4B76 (Z); - LD32(p2, DCPLB_DATA10); - -X4_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB10)); - CHECKREG_SYM(r7, X4_10, r0); // RETX should be value of X4_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x058E (Z); - LD32(p2, DCPLB_DATA11); - -X4_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB11)); - CHECKREG_SYM(r7, X4_11, r0); // RETX should be value of X4_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7A5F (Z); - LD32(p2, DCPLB_DATA12); - -X4_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB12)); - CHECKREG_SYM(r7, X4_12, r0); // RETX should be value of X4_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x28D9 (Z); - LD32(p2, DCPLB_DATA13); - -X4_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB13)); - CHECKREG_SYM(r7, X4_13, r0); // RETX should be value of X4_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0799 (Z); - LD32(p2, DCPLB_DATA14); - -X4_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA4, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB14)); - CHECKREG_SYM(r7, X4_14, r0); // RETX should be value of X4_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x388F (Z); - LD32(p2, DCPLB_DATA6); - -X5_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB6)); - CHECKREG_SYM(r7, X5_6, r0); // RETX should be value of X5_6 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x751F (Z); - LD32(p2, DCPLB_DATA7); - -X5_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB7)); - CHECKREG_SYM(r7, X5_7, r0); // RETX should be value of X5_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x493F (Z); - LD32(p2, DCPLB_DATA8); - -X5_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB8)); - CHECKREG_SYM(r7, X5_8, r0); // RETX should be value of X5_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0F36 (Z); - LD32(p2, DCPLB_DATA9); - -X5_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB9)); - CHECKREG_SYM(r7, X5_9, r0); // RETX should be value of X5_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x48EE (Z); - LD32(p2, DCPLB_DATA10); - -X5_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB10)); - CHECKREG_SYM(r7, X5_10, r0); // RETX should be value of X5_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2043 (Z); - LD32(p2, DCPLB_DATA11); - -X5_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB11)); - CHECKREG_SYM(r7, X5_11, r0); // RETX should be value of X5_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x3F78 (Z); - LD32(p2, DCPLB_DATA12); - -X5_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB12)); - CHECKREG_SYM(r7, X5_12, r0); // RETX should be value of X5_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1E4D (Z); - LD32(p2, DCPLB_DATA13); - -X5_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB13)); - CHECKREG_SYM(r7, X5_13, r0); // RETX should be value of X5_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x3D0D (Z); - LD32(p2, DCPLB_DATA14); - -X5_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA5, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB14)); - CHECKREG_SYM(r7, X5_14, r0); // RETX should be value of X5_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x33FA (Z); - LD32(p2, DCPLB_DATA7); - -X6_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB7)); - CHECKREG_SYM(r7, X6_7, r0); // RETX should be value of X6_7 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6FBE (Z); - LD32(p2, DCPLB_DATA8); - -X6_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB8)); - CHECKREG_SYM(r7, X6_8, r0); // RETX should be value of X6_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x36A6 (Z); - LD32(p2, DCPLB_DATA9); - -X6_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB9)); - CHECKREG_SYM(r7, X6_9, r0); // RETX should be value of X6_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2DDA (Z); - LD32(p2, DCPLB_DATA10); - -X6_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB10)); - CHECKREG_SYM(r7, X6_10, r0); // RETX should be value of X6_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x30E4 (Z); - LD32(p2, DCPLB_DATA11); - -X6_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB11)); - CHECKREG_SYM(r7, X6_11, r0); // RETX should be value of X6_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0586 (Z); - LD32(p2, DCPLB_DATA12); - -X6_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB12)); - CHECKREG_SYM(r7, X6_12, r0); // RETX should be value of X6_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x148E (Z); - LD32(p2, DCPLB_DATA13); - -X6_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB13)); - CHECKREG_SYM(r7, X6_13, r0); // RETX should be value of X6_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x42DC (Z); - LD32(p2, DCPLB_DATA14); - -X6_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA6, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB14)); - CHECKREG_SYM(r7, X6_14, r0); // RETX should be value of X6_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5929 (Z); - LD32(p2, DCPLB_DATA8); - -X7_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB8)); - CHECKREG_SYM(r7, X7_8, r0); // RETX should be value of X7_8 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x0C6D (Z); - LD32(p2, DCPLB_DATA9); - -X7_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB9)); - CHECKREG_SYM(r7, X7_9, r0); // RETX should be value of X7_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x334E (Z); - LD32(p2, DCPLB_DATA10); - -X7_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB10)); - CHECKREG_SYM(r7, X7_10, r0); // RETX should be value of X7_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x62FF (Z); - LD32(p2, DCPLB_DATA11); - -X7_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB11)); - CHECKREG_SYM(r7, X7_11, r0); // RETX should be value of X7_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1F56 (Z); - LD32(p2, DCPLB_DATA12); - -X7_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB12)); - CHECKREG_SYM(r7, X7_12, r0); // RETX should be value of X7_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2BE1 (Z); - LD32(p2, DCPLB_DATA13); - -X7_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB13)); - CHECKREG_SYM(r7, X7_13, r0); // RETX should be value of X7_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1D70 (Z); - LD32(p2, DCPLB_DATA14); - -X7_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA7, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB14)); - CHECKREG_SYM(r7, X7_14, r0); // RETX should be value of X7_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x2620 (Z); - LD32(p2, DCPLB_DATA9); - -X8_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA8, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB9)); - CHECKREG_SYM(r7, X8_9, r0); // RETX should be value of X8_9 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x26FB (Z); - LD32(p2, DCPLB_DATA10); - -X8_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA8, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB10)); - CHECKREG_SYM(r7, X8_10, r0); // RETX should be value of X8_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x718F (Z); - LD32(p2, DCPLB_DATA11); - -X8_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA8, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB11)); - CHECKREG_SYM(r7, X8_11, r0); // RETX should be value of X8_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x04B1 (Z); - LD32(p2, DCPLB_DATA12); - -X8_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA8, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB12)); - CHECKREG_SYM(r7, X8_12, r0); // RETX should be value of X8_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5358 (Z); - LD32(p2, DCPLB_DATA13); - -X8_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA8, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB13)); - CHECKREG_SYM(r7, X8_13, r0); // RETX should be value of X8_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x3305 (Z); - LD32(p2, DCPLB_DATA14); - -X8_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA8, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB14)); - CHECKREG_SYM(r7, X8_14, r0); // RETX should be value of X8_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5690 (Z); - LD32(p2, DCPLB_DATA10); - -X9_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA9, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB10)); - CHECKREG_SYM(r7, X9_10, r0); // RETX should be value of X9_10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5DC5 (Z); - LD32(p2, DCPLB_DATA11); - -X9_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA9, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB11)); - CHECKREG_SYM(r7, X9_11, r0); // RETX should be value of X9_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7809 (Z); - LD32(p2, DCPLB_DATA12); - -X9_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA9, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB12)); - CHECKREG_SYM(r7, X9_12, r0); // RETX should be value of X9_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1DDC (Z); - LD32(p2, DCPLB_DATA13); - -X9_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA9, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB13)); - CHECKREG_SYM(r7, X9_13, r0); // RETX should be value of X9_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6B53 (Z); - LD32(p2, DCPLB_DATA14); - -X9_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA9, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB14)); - CHECKREG_SYM(r7, X9_14, r0); // RETX should be value of X9_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x7BCD (Z); - LD32(p2, DCPLB_DATA11); - -X10_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA10, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB11)); - CHECKREG_SYM(r7, X10_11, r0); // RETX should be value of X10_11 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x63AA (Z); - LD32(p2, DCPLB_DATA12); - -X10_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA10, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB12)); - CHECKREG_SYM(r7, X10_12, r0); // RETX should be value of X10_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x373B (Z); - LD32(p2, DCPLB_DATA13); - -X10_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA10, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB13)); - CHECKREG_SYM(r7, X10_13, r0); // RETX should be value of X10_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x5648 (Z); - LD32(p2, DCPLB_DATA14); - -X10_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA10, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB14)); - CHECKREG_SYM(r7, X10_14, r0); // RETX should be value of X10_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6799 (Z); - LD32(p2, DCPLB_DATA12); - -X11_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA11, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB12)); - CHECKREG_SYM(r7, X11_12, r0); // RETX should be value of X11_12 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1452 (Z); - LD32(p2, DCPLB_DATA13); - -X11_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA11, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB13)); - CHECKREG_SYM(r7, X11_13, r0); // RETX should be value of X11_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x23D3 (Z); - LD32(p2, DCPLB_DATA14); - -X11_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA11, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB14)); - CHECKREG_SYM(r7, X11_14, r0); // RETX should be value of X11_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x1152 (Z); - LD32(p2, DCPLB_DATA13); - -X12_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA12, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB13)); - CHECKREG_SYM(r7, X12_13, r0); // RETX should be value of X12_13 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6E9D (Z); - LD32(p2, DCPLB_DATA14); - -X12_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA12, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB14)); - CHECKREG_SYM(r7, X12_14, r0); // RETX should be value of X12_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - CSYNC; - - LD32(i1, 0x10000000); - R1 = 0x6006 (Z); - LD32(p2, DCPLB_DATA14); - -X13_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); - CSYNC; - WR_MMR(DCPLB_DATA13, 0, p0, r0); - - // Now check that handler read correct values - CHECKREG(r4,0x27); // supv and EXCPT_PROT - CHECKREG(r5, 0x10000000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB13|FAULT_CPLB14)); - CHECKREG_SYM(r7, X13_14, r0); // RETX should be value of X13_14 (HARDCODED ADDR!!) - - //------------------------------------------------------- -User: - NOP; - dbg_pass; diff --git a/sim/testsuite/sim/bfin/lmu_excpt_align.S b/sim/testsuite/sim/bfin/lmu_excpt_align.S deleted file mode 100644 index b978155..0000000 --- a/sim/testsuite/sim/bfin/lmu_excpt_align.S +++ /dev/null @@ -1,345 +0,0 @@ -//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_align/lmu_excpt_align.dsp -// Description: LMU data alignment exceptions -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) - -CHECK_INIT(p5, 0xE0000000); - - // test address for DAG0 - // test address for DAG1 - - // setup interrupt controller with exception handler address - WR_MMR_LABEL(EVT3, handler, p0, r1); - - // Write fault addr MMR to known state - WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6); - - //nop;nop;nop;nop;nop; // in lieu of CSYNC - CSYNC; - - A0 = 0; - - // go to user mode. and enable exceptions - LD32_LABEL(r0, User); - RETI = R0; - RTI; - - // Nops to work around ICache bug - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - - -User: - NOP;NOP;NOP;NOP;NOP; - - //------------------------------------------------------- - // First do stores - //------------------------------------------------------- - // 16-bit alignment, DAG0 - - - - LD32(i1, ((0x1000 + 1))); - LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X01: W [ I1 ] = R1.L; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 32-bit alignment, DAG0 - - - - LD32(i1, ((0x1000 + 1))); - LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X02: [ I1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 32-bit alignment, DAG0 - - - - LD32(i1, ((0x1000 + 2))); - LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X03: [ I1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 32-bit alignment, DAG0 - - - - LD32(i1, ((0x1000 + 3))); - LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X04: [ I1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 16-bit alignment, DAG1 - - - - LD32(i1, ((0x1000 + 1))); - LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X05: A0 = 0 || NOP || W [ I1 ] = R1.L; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X05, r0); // RETX should be value of X05 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 32-bit alignment, DAG1 - - - - LD32(i1, ((0x1000 + 1))); - LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X06: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X06, r0); // RETX should be value of X06 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 32-bit alignment, DAG1 - - - - LD32(i1, ((0x1000 + 2))); - LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X07: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X07, r0); // RETX should be value of X07 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 32-bit alignment, DAG1 - - - - LD32(i1, ((0x1000 + 3))); - LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X08: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X08, r0); // RETX should be value of X08 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // Now repeat for Loads - //------------------------------------------------------- - // 16-bit alignment, DAG0 - - - - LD32(i1, ((0x1000 + 1))); - LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X11: R1.L = W [ I1 ]; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X11, r0); // RETX should be value of X11 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 32-bit alignment, DAG0 - - - - LD32(i1, ((0x1000 + 1))); - LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X12: R1 = [ I1 ]; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X12, r0); // RETX should be value of X12 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 32-bit alignment, DAG0 - - - - LD32(i1, ((0x1000 + 2))); - LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X13: R1 = [ I1 ]; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X13, r0); // RETX should be value of X13 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 32-bit alignment, DAG0 - - - - LD32(i1, ((0x1000 + 3))); - LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X14: R1 = [ I1 ]; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X14, r0); // RETX should be value of X14 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 16-bit alignment, DAG1 - - - - LD32(i1, ((0x1000 + 1))); - LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X15: A0 = 0 || NOP || R1.L = W [ I1 ]; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X15, r0); // RETX should be value of X15 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 32-bit alignment, DAG1 - - - - LD32(i1, ((0x1000 + 1))); - LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X16, r0); // RETX should be value of X16 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 32-bit alignment, DAG1 - - - - LD32(i1, ((0x1000 + 2))); - LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X17: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X17, r0); // RETX should be value of X17 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // 32-bit alignment, DAG1 - - - - LD32(i1, ((0x1000 + 3))); - LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X18: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here - - CHECKREG(r5,0x24); // supv and EXCPT_ALIGN - CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address - CHECKREG_SYM(r7, X18, r0); // RETX should be value of X18 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - dbg_pass; - - -handler: - R5 = SEQSTAT; // Get exception cause - - // read and check fail addr (addr_which_causes_exception) - // should not be set for alignment exception - RD_MMR(DCPLB_FAULT_ADDR, p0, r6); - - R7 = RETX; // get address of excepting instruction - - // align the offending address - I1 = P2; - - RTX; - // Nops to work around ICache bug - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - - -.section MEM_0x1000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/lmu_excpt_default.S b/sim/testsuite/sim/bfin/lmu_excpt_default.S deleted file mode 100644 index 9b8a14f..0000000 --- a/sim/testsuite/sim/bfin/lmu_excpt_default.S +++ /dev/null @@ -1,307 +0,0 @@ -//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_default/lmu_excpt_default.dsp -// Description: Default protection checks (CPLB disabled) -// - MMR access in User mode -// - DAG1 Access MMRs (supv/user mode, read/write) -// - DAG1 Access Scratch SRAM (user or supervisor mode, read/write) -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) - -#define EXCPT_PROTVIOL 0x23 -#define OMODE_SUPV 0 // not used in the hardware - - - - CHECK_INIT(p5, 0xE0000000); - - // setup interrupt controller with exception handler address - WR_MMR_LABEL(EVT3, handler, p0, r1); - WR_MMR_LABEL(EVT15, Supv, p0, r1); - WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); - WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); - CSYNC; - - A0 = 0; - - // go to user mode. and enable exceptions - LD32_LABEL(r0, User); - RETI = R0; - - // But first raise interrupt 15 so we can run in supervisor mode. - RAISE 15; - - RTI; - -Supv: - - //------------------------------------------------------- - // DAG1 MMR Write access - - - - LD32(i1, (DCPLB_ADDR0)); - LD32_LABEL(p2, Y01); // Exception handler will return to this address - LD32(r0, 0xdeadbeef); - - - R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first -X01: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here -Y01: - - // Now check that handler read correct values - CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT - CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS - CHECKREG_SYM(r7, X01, r0); // RETX X01: (HARDCODED ADDR!!) - - //------------------------------------------------------- - // DAG1 MMR Read access - - - - LD32(i1, (DCPLB_ADDR1)); - LD32_LABEL(p2, Y02); // Exception handler will return to this address - - - R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first -X02: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here -Y02: - - // Now check that handler read correct values - CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT - CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS - CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS - CHECKREG_SYM(r7, X02, r0); // RETX X02: (HARDCODED ADDR!!) - -#if 0 - //------------------------------------------------------- - // DAG1 Scratch SRAM Write access - - - - LD32(i1, (( 0xFF800000 + 0x300000))); - LD32_LABEL(p2, Y03); // Exception handler will return to this address - LD32(r1, 0xdeadbeef); - - - R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first -X03: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here -Y03: - - // Now check that handler read correct values - CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT - CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS - CHECKREG_SYM(r7, X03, r0); // RETX X03: (HARDCODED ADDR!!) - - //------------------------------------------------------- - // DAG1 Scratch SRAM Read access - - - - LD32(i1, ((( 0xFF800000 + 0x300000) + 4))); - LD32_LABEL(p2, Y04); // Exception handler will return to this address - - - R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first -X04: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here -Y04: - - // Now check that handler read correct values - CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT - CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS - CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS - CHECKREG_SYM(r7, X04, r0); // RETX X04: (HARDCODED ADDR!!) -#endif - - //------------------------------------------------------- - - // Now, go to User mode - LD32_LABEL(r0, User); - RETI = R0; - RTI; - - -User: - - //------------------------------------------------------- - // DAG0 MMR Write access (multi-issue) - - - - LD32(i1, (DCPLB_ADDR0)); - LD32_LABEL(p2, Y11); // Exception handler will return to this address - LD32(r0, 0xdeadbeef); - - - R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first -X11: A0 = 0 || [ I1 ] = R1 || NOP; // Exception should occur here -Y11: - - // Now check that handler read correct values - CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT - CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS - CHECKREG_SYM(r7, X11, r0); // RETX X11: (HARDCODED ADDR!!) - - //------------------------------------------------------- - // DAG0 MMR Read access (multi-issue) - - - - LD32(i1, (DCPLB_ADDR1)); - LD32_LABEL(p2, Y12); // Exception handler will return to this address - - - R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first -X12: A0 = 0 || R1 = [ I1 ] || NOP; // Exception should occur here -Y12: - - // Now check that handler read correct values - CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT - CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS - CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS - CHECKREG_SYM(r7, X12, r0); // RETX X12: (HARDCODED ADDR!!) - - //------------------------------------------------------- - // DAG1 MMR Write access - - - - LD32(i1, (DCPLB_ADDR0)); - LD32_LABEL(p2, Y13); // Exception handler will return to this address - LD32(r0, 0xdeadbeef); - - - R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first -X13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here -Y13: - - // Now check that handler read correct values - CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT - CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS - CHECKREG_SYM(r7, X13, r0); // RETX X13: (HARDCODED ADDR!!) - - //------------------------------------------------------- - // DAG1 MMR Read access - - - - LD32(i1, (DCPLB_ADDR1)); - LD32_LABEL(p2, Y14); // Exception handler will return to this address - - - R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first -X14: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here -Y14: - - // Now check that handler read correct values - CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT - CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS - CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS - CHECKREG_SYM(r7, X14, r0); // RETX X14: (HARDCODED ADDR!!) - -#if 0 - //------------------------------------------------------- - // DAG1 Scratch SRAM Write access - - - - LD32(i1, (( 0xFF800000 + 0x300000))); - LD32_LABEL(p2, Y15); // Exception handler will return to this address - LD32(r1, 0xdeadbeef); - - - R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first -X15: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here -Y15: - - // Now check that handler read correct values - CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT - CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS - CHECKREG_SYM(r7, X15, r0); // RETX X15: (HARDCODED ADDR!!) - - //------------------------------------------------------- - // DAG1 Scratch SRAM Read access - - - - LD32(i1, ((( 0xFF800000 + 0x300000) + 4))); - LD32_LABEL(p2, Y16); // Exception handler will return to this address - - - R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first -X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here -Y16: - - // Now check that handler read correct values - CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT - CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS - CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS - CHECKREG_SYM(r7, X16, r0); // RETX X16: (HARDCODED ADDR!!) -#endif - - //------------------------------------------------------- - // DAG0 MMR Write access (single-issue) - - - - LD32(i1, (DCPLB_ADDR0)); - LD32_LABEL(p2, Y17); // Exception handler will return to this address - LD32(r0, 0xdeadbeef); - - - R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first -X17: [ I1 ] = R1; // Exception should occur here -Y17: - - // Now check that handler read correct values - CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT - CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS - CHECKREG_SYM(r7, X17, r0); // RETX X17: (HARDCODED ADDR!!) - - //------------------------------------------------------- - // DAG0 MMR Read access (single-issue) - - - - LD32(i1, (DCPLB_ADDR1)); - LD32_LABEL(p2, Y18); // Exception handler will return to this address - - - R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first -X18: R1 = [ I1 ]; // Exception should occur here -Y18: - - // Now check that handler read correct values - CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT - CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS - CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS - CHECKREG_SYM(r7, X18, r0); // RETX X18: (HARDCODED ADDR!!) - - //------------------------------------------------------- - dbg_pass; - - -handler: - R4 = SEQSTAT; // Get exception cause - - // read and check fail addr (addr_which_causes_exception) - // should not be set for alignment exception - RD_MMR(DCPLB_FAULT_ADDR, p0, r5); - RD_MMR(DCPLB_STATUS, p0, r6); - R7 = RETX; // get address of excepting instruction - - RETX = P2; - - RTX; diff --git a/sim/testsuite/sim/bfin/lmu_excpt_illaddr.S b/sim/testsuite/sim/bfin/lmu_excpt_illaddr.S deleted file mode 100644 index 7c84b64..0000000 --- a/sim/testsuite/sim/bfin/lmu_excpt_illaddr.S +++ /dev/null @@ -1,337 +0,0 @@ -//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_illaddr/lmu_excpt_illaddr.dsp -// Description: LMU illegal address exceptions -// Illegal core MMR: addr[19:16] != 0 -// Illegal core MMR: Illegal peripheral -// Illegal core MMR: Illegal addr in peripheral -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) - -#ifndef SR_BASE -#define SR_BASE 0xFF800000 // must match value used for sram_baddr inputs -#endif -#ifndef A_SRAM_BASE -#define A_SRAM_BASE SR_BASE -#endif -#ifndef B_SRAM_BASE -#define B_SRAM_BASE SR_BASE + 0x100000 -#endif -#ifndef I_SRAM_BASE -#define I_SRAM_BASE SR_BASE + 0x200000 -#endif -#ifndef SCRATCH_SRAM_BASE -#define SCRATCH_SRAM_BASE SR_BASE + 0x300000 -#endif - -#ifndef A_SRAM_SIZE -#define A_SRAM_SIZE 0x4000 -#endif -#ifndef B_SRAM_SIZE -#define B_SRAM_SIZE 0x4000 -#endif -#ifndef I_SRAM_SIZE -#define I_SRAM_SIZE 0x4000 -#endif -#ifndef SCRATCH_SRAM_SIZE -#define SCRATCH_SRAM_SIZE 0x1000 -#endif - -CHECK_INIT(p5, 0xE0000000); - - // setup interrupt controller with exception handler address - WR_MMR_LABEL(EVT3, handler, p0, r1); - WR_MMR_LABEL(EVT15, int15, p0, r1); - WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); - WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); - - // Set up CPLB - - WR_MMR(DCPLB_ADDR1, SR_BASE, p0, r0); // SRAM segment: Non-cacheable - WR_MMR(DCPLB_DATA1, ( CPLB_VALID | CPLB_L1SRAM | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0); - - WR_MMR(DCPLB_ADDR2, 0xE0000000, p0, r0); // CHECKREG segment: Non-cacheable - WR_MMR(DCPLB_DATA2, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0); - - WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); // MMRs: Non-cacheable - WR_MMR(DCPLB_DATA15, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0); - - WR_MMR(DMEM_CONTROL, (DMC_AB_SRAM | ENDCPLB | ENDM), p0, r0); - - CSYNC; - - // Write fault addr MMR to known state - WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6); - NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC - - // go to user mode. and enable exceptions - LD32_LABEL(r0, User); - RETI = R0; - - // But first raise interrupt 15 so we will run in supervisor mode. - RAISE 15; - NOP; - RTI; - - // Nops to work around ICache bug - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - -int15: - NOP;NOP;NOP;NOP;NOP; - - //------------------------------------------------------- - // First do stores - //------------------------------------------------------- - // - - // illegal core MMR: addr[19] !=0 - - - LD32(p1, 0xFFE80000); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X01: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE80000); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: addr[18] !=0 - - - LD32(p1, 0xFFE40000); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X02: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE40000); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: addr[17] !=0 - - - LD32(p1, 0xFFE20000); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X03: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE20000); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: addr[16] !=0 - - - LD32(p1, 0xFFE10000); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X04: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE10000); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: illegal periperal (addr[15:12] > 8) - - - LD32(p1, 0xFFE09000); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X10: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE09000); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X10, r0); // RETX should be value of X10 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: illegal addr in peripheral 00 - - - LD32(p1, 0xFFE00408); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X20: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE00408); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X20, r0); // RETX should be value of X20 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: illegal addr in peripheral 01 - - - LD32(p1, 0xFFE01408); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X21: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE01408); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X21, r0); // RETX should be value of X21 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: illegal addr in peripheral 02 - - - LD32(p1, 0xFFE02114); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X22: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE02114); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X22, r0); // RETX should be value of X22 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: illegal addr in peripheral 03 - - - LD32(p1, 0xFFE03010); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X23: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE03010); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X23, r0); // RETX should be value of X23 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: illegal addr in peripheral 04 - - - LD32(p1, 0xFFE04008); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X24: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE04008); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X24, r0); // RETX should be value of X24 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: illegal addr in peripheral 05 - - - LD32(p1, 0xFFE05010); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X25: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE05010); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X25, r0); // RETX should be value of X25 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: illegal addr in peripheral 06 - - - LD32(p1, 0xFFE06104); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X26: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE06104); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X26, r0); // RETX should be value of X26 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: illegal addr in peripheral 07 - - - LD32(p1, 0xFFE07204); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X27: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE07204); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X27, r0); // RETX should be value of X27 (HARDCODED ADDR!!) - - //------------------------------------------------------- - - // illegal core MMR: illegal addr in peripheral 08 - - - LD32(p1, 0xFFE08108); - LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) - LD32(r1, 0xDEADBEEF); - R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first - -X28: [ P1 ] = R1; // Exception should occur here - - CHECKREG(r5,0x2e); // supv and EXCPT_PROT - CHECKREG(r6, 0xFFE08108); // FAULT_ADDR should contain test address - CHECKREG_SYM(r7, X28, r0); // RETX should be value of X28 (HARDCODED ADDR!!) - - //------------------------------------------------------- -User: - dbg_pass; - - - //------------------------------------------------------- -handler: - R5 = SEQSTAT; // Get exception cause - - // read and check fail addr (addr_which_causes_exception) - // should not be set for alignment exception - RD_MMR(DCPLB_FAULT_ADDR, p0, r6); - - R7 = RETX; // get address of excepting instruction - - // align the offending address - P1 = P2; - - RTX; - // Nops to work around ICache bug - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; diff --git a/sim/testsuite/sim/bfin/lmu_excpt_prot0.S b/sim/testsuite/sim/bfin/lmu_excpt_prot0.S deleted file mode 100644 index 279cc02..0000000 --- a/sim/testsuite/sim/bfin/lmu_excpt_prot0.S +++ /dev/null @@ -1,392 +0,0 @@ -//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot0/lmu_excpt_prot0.dsp -// Description: LMU protection exceptions -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) - -//------------------------------------- - -// Test LMU/CPLB exceptions - -// Basic outline: -// Set exception handler -// program CPLB Entries -// Enable CPLB in DMEM_CNTL -// perform access -// verify exception occurred - -CHECK_INIT(p5, 0xEFFFFFFC); - -//------------------------- -// Zero the CPLB Address and Data regs. - - LD32(p0, DCPLB_ADDR0); - R0 = 0; - [ P0 ++ ] = R0; // 0 - [ P0 ++ ] = R0; // 1 - [ P0 ++ ] = R0; // 2 - [ P0 ++ ] = R0; // 3 - [ P0 ++ ] = R0; // 4 - [ P0 ++ ] = R0; // 5 - [ P0 ++ ] = R0; // 6 - [ P0 ++ ] = R0; // 7 - [ P0 ++ ] = R0; // 8 - [ P0 ++ ] = R0; // 9 - [ P0 ++ ] = R0; // 10 - [ P0 ++ ] = R0; // 11 - [ P0 ++ ] = R0; // 12 - [ P0 ++ ] = R0; // 13 - [ P0 ++ ] = R0; // 14 - [ P0 ++ ] = R0; // 15 - - LD32(p0, DCPLB_DATA0); - [ P0 ++ ] = R0; // 0 - [ P0 ++ ] = R0; // 1 - [ P0 ++ ] = R0; // 2 - [ P0 ++ ] = R0; // 3 - [ P0 ++ ] = R0; // 4 - [ P0 ++ ] = R0; // 5 - [ P0 ++ ] = R0; // 6 - [ P0 ++ ] = R0; // 7 - [ P0 ++ ] = R0; // 8 - [ P0 ++ ] = R0; // 9 - [ P0 ++ ] = R0; // 10 - [ P0 ++ ] = R0; // 11 - [ P0 ++ ] = R0; // 12 - [ P0 ++ ] = R0; // 13 - [ P0 ++ ] = R0; // 14 - [ P0 ++ ] = R0; // 15 - - // Now set the CPLB entries we will need - - - - - - - - - - - - - - - - - - - - - - - - - - // Data area for the desired error - WR_MMR(DCPLB_ADDR0, 0x800, p0, r0); - WR_MMR(DCPLB_ADDR1, 0x1000, p0, r0); - WR_MMR(DCPLB_DATA0, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW, p0, r0); - WR_MMR(DCPLB_ADDR2, 0x2000, p0, r0); - WR_MMR(DCPLB_ADDR3, 0x3000, p0, r0); - WR_MMR(DCPLB_ADDR4, 0x4000, p0, r0); - WR_MMR(DCPLB_ADDR5, 0x5000, p0, r0); - WR_MMR(DCPLB_ADDR6, 0x6000, p0, r0); - WR_MMR(DCPLB_ADDR7, 0x7000, p0, r0); - - // CHECKREG segment - WR_MMR(DCPLB_ADDR14, 0xEFFFFC00, p0, r0); - WR_MMR(DCPLB_DATA14, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_WT|CPLB_L1_CACHABLE|CPLB_SUPV_WR|CPLB_USER_RW, p0, r0); - - // MMR space - WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); - WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); - - // setup interrupt controller with exception handler address - WR_MMR_LABEL(EVT3, handler, p0, r1); - WR_MMR_LABEL(EVT15, int_15, p0, r1); - WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); - WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); - - // enable CPLB - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC - - // go to user mode. and enable exceptions - LD32_LABEL(r0, User); - RETI = R0; - - // But first raise interrupt 15 so we can do one test - // in supervisor mode. - RAISE 15; - NOP; - - RTI; - - // Nops to work around ICache bug - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - - -int_15: - // Interrupt 15 handler - needed to try supervisor access with exceptions enabled - //------------------------------------------------------- - // Protection violation - Illegal Supervisor Write Access - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - LD32(p1, 0x800); - LD32(r1, 0xDEADBEEF); - - LD32(p2, DCPLB_DATA0); - LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); - - LD32(p3, DCPLB_DATA1); - LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); - - -X0: [ P1 ] = R1; // Exception should occur here - - - // Now check that handler read correct values - CHECKREG(r4,0x23); // supv and EXCPT_PROT - CHECKREG(r5, 0x800); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0)); - CHECKREG_SYM(r7, X0, r0); // RETX should be value of X0 (HARDCODED ADDR!!) - - // go to user mode. and enable exceptions - LD32_LABEL(r0, User); - RTI; - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - - -User: - NOP;NOP;NOP;NOP;NOP; - - //------------------------------------------------------- - // Protection violation - Illegal User Write Access - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - LD32(p1, 0x1000); - LD32(r1, 0xDEADBEEF); - - - // values to fix up current test - LD32(p2, DCPLB_DATA1); - LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); - - // values for next test - LD32(p3, DCPLB_DATA2); - LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE); - -X1: [ P1 ] = R1; // Exception should occur here - - // Now check that handler read correct values - - CHECKREG(r4,0x23); // supv and EXCPT_PROT - CHECKREG(r5, 0x1000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER | FAULT_CPLB1)); - CHECKREG_SYM(r7, X1, r0); // RETX should be value of X1 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // Protection violation - Illegal User Read Access - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - LD32(p1, 0x2000); - LD32(r1, 0xDEADBEEF); - - LD32(p2, DCPLB_DATA2); - LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RO|CPLB_SUPV_WR); - - LD32(p3, DCPLB_DATA3); - LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); - -X2: //[p1] = r1; // Exception should occur here - R0 = [ P1 ]; - - - // Now check that handler read correct values - CHECKREG(r4,0x23); // supv and EXCPT_PROT - CHECKREG(r5, 0x2000); - CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER | FAULT_CPLB2)); - CHECKREG_SYM(r7, X2, r0); // RETX should be value of X2 (HARDCODED ADDR!!) - - //------------------------------------------------------- - // Protection violation - Illegal Dirty Page Access - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - LD32(p1, 0x3000); - LD32(r1, 0xDEADBEEF); - - LD32(p2, DCPLB_DATA3); - LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); - - LD32(p3, DCPLB_DATA4); - LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DA0ACC|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); - - -X3: [ P1 ] = R1; // Exception should occur here - - - // Now check that handler read correct values - CHECKREG(r4,0x23); // supv and EXCPT_PROT - CHECKREG(r5, 0x3000); - CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER | FAULT_CPLB3)); - CHECKREG_SYM(r7, X3, r0); // RETX should be value of X3 (HARDCODED ADDR!!) - - //------------------------------------------------------- - // Protection violation - Illegal DAG1 Access - // Since this test uses DAG0, there shouldn't be any exception - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - LD32(p1, 0x4000); - LD32(r1, 0xDEADBEEF); - - LD32(p2, DCPLB_DATA4); - LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); - - LD32(p3, DCPLB_DATA5); - LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); - - -X4: [ P1 ] = R1; // Exception should NOT occur here - - - // Now check that handler read correct values - // Handler shouldn't have been invoked, so registers should - // remain unchanged. - CHECKREG(r4,0); // supv and EXCPT_PROT - CHECKREG(r5, 0); - CHECKREG(r6, 0); - CHECKREG(r7, 0); // RETX should NOT be value of X4 (HARDCODED ADDR!!) - - //------------------------------------------------------- - // L1Miss not implemented yet - skip for now.... - -// //------------------------------------------------------- -// // Protection violation - L1 Miss -// r0=0;r1=0;r2=0;r3=0;r4=0;r5=0;r6=0;r7=0; -// -// LD32(p1, 0x5000); -// LD32(r1, 0xDEADBEEF); -// -// LD32(p2, DCPLB_DATA5); -// LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); -// -// LD32(p3, DCPLB_DATA6); -// LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_USER_RW|CPLB_SUPV_WR); -// -// -//X5: //[p1] = r1; // Exception should occur here -// r0 = [p1]; -// -// -// // Now check that handler read correct values -// CHECKREG(r4,0x23); // supv and EXCPT_PROT -// CHECKREG(r5, 0x5000); -// // CHECKREG(r6, FAULT_DATA | FAULT_CPLB5); -// CHECKREG_SYM(r7, X5, r0); // RETX should be value of X5 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - dbg_pass; - - -handler: - // generic protection exception handler - // Inputs: - // p2: addr of CPLB entry to be modified ( current test) - // r2: new data for CPLB entry - // - // p3: addr of CPLB entry to be modified ( next test) - // r3: new data for CPLB entry - // - // Outputs: - // r4: SEQSTAT - // r5: DCPLB_FAULT_ADDR - // r6: DCPLB_STATUS - // r7: RETX (instruction addr where exception occurred) - - - R4 = SEQSTAT; // Get exception cause - - // read data addr which caused exception - RD_MMR(DCPLB_FAULT_ADDR, p0, r5); - - RD_MMR(DCPLB_STATUS, p0, r6); - - R7 = RETX; // get address of excepting instruction - - - // modify CPLB to allow access. Main pgm passes in addr and data - [ P2 ] = R2; - - // Set up for next test - [ P3 ] = R3; - - NOP;NOP;NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC; - - // return from exception and re-execute offending instruction - RTX; - - // Nops to work around ICache bug - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - - -.section MEM_0x800,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -.section MEM_0x1000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -.section MEM_0x2000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -.section MEM_0x3000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -.section MEM_0x4000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -.section MEM_0x5000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -// Need illegal SRAM addr to test CPLB_L1SRAM -//.data 0x6000 -// .dd 0x00000000 -// .dd 0x00000000 -// .dd 0x00000000 -// .dd 0x00000000 - -.section MEM_0x7000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/lmu_excpt_prot1.S b/sim/testsuite/sim/bfin/lmu_excpt_prot1.S deleted file mode 100644 index 5ffa680..0000000 --- a/sim/testsuite/sim/bfin/lmu_excpt_prot1.S +++ /dev/null @@ -1,401 +0,0 @@ -//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot1/lmu_excpt_prot1.dsp -// Description: LMU protection exceptions -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) - -//------------------------------------- - -// Test LMU/CPLB exceptions - -// Basic outline: -// Set exception handler -// program CPLB Entries -// Enable CPLB in DMEM_CNTL -// perform access -// verify exception occurred - -CHECK_INIT(p5, 0xEFFFFFFC); - - A0 = 0; - -//------------------------- -// Zero the CPLB Address and Data regs. - - LD32(p0, DCPLB_ADDR0); - R0 = 0; - [ P0 ++ ] = R0; // 0 - [ P0 ++ ] = R0; // 1 - [ P0 ++ ] = R0; // 2 - [ P0 ++ ] = R0; // 3 - [ P0 ++ ] = R0; // 4 - [ P0 ++ ] = R0; // 5 - [ P0 ++ ] = R0; // 6 - [ P0 ++ ] = R0; // 7 - [ P0 ++ ] = R0; // 8 - [ P0 ++ ] = R0; // 9 - [ P0 ++ ] = R0; // 10 - [ P0 ++ ] = R0; // 11 - [ P0 ++ ] = R0; // 12 - [ P0 ++ ] = R0; // 13 - [ P0 ++ ] = R0; // 14 - [ P0 ++ ] = R0; // 15 - - LD32(p0, DCPLB_DATA0); - [ P0 ++ ] = R0; // 0 - [ P0 ++ ] = R0; // 1 - [ P0 ++ ] = R0; // 2 - [ P0 ++ ] = R0; // 3 - [ P0 ++ ] = R0; // 4 - [ P0 ++ ] = R0; // 5 - [ P0 ++ ] = R0; // 6 - [ P0 ++ ] = R0; // 7 - [ P0 ++ ] = R0; // 8 - [ P0 ++ ] = R0; // 9 - [ P0 ++ ] = R0; // 10 - [ P0 ++ ] = R0; // 11 - [ P0 ++ ] = R0; // 12 - [ P0 ++ ] = R0; // 13 - [ P0 ++ ] = R0; // 14 - [ P0 ++ ] = R0; // 15 - - // Now set the CPLB entries we will need - - - - - - - - - - - - - - - - - - - - - - - - - - // Data area for the desired error - WR_MMR(DCPLB_ADDR0, 0x800, p0, r0); - WR_MMR(DCPLB_ADDR1, 0x1000, p0, r0); - WR_MMR(DCPLB_DATA0, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE, p0, r0); - WR_MMR(DCPLB_ADDR2, 0x2000, p0, r0); - WR_MMR(DCPLB_ADDR3, 0x3000, p0, r0); - WR_MMR(DCPLB_ADDR4, 0x4000, p0, r0); - WR_MMR(DCPLB_ADDR5, 0x5000, p0, r0); - WR_MMR(DCPLB_ADDR6, 0x6000, p0, r0); - WR_MMR(DCPLB_ADDR7, 0x7000, p0, r0); - - // CHECKREG segment - WR_MMR(DCPLB_ADDR14, 0xEFFFFC00, p0, r0); - WR_MMR(DCPLB_DATA14, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_WT|CPLB_L1_CACHABLE|CPLB_SUPV_WR|CPLB_USER_RW, p0, r0); - - // MMR space - WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); - WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); - - // setup interrupt controller with exception handler address - WR_MMR_LABEL(EVT3, handler, p0, r1); - WR_MMR_LABEL(EVT15, int_15, p0, r1); - WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); - WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); - - // enable CPLB - WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); - NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC - - // Address for slot 0 accesses - // LD32(p4, 0xEFFFFFF8); - - // go to user mode. and enable exceptions - LD32_LABEL(r0, User); - RETI = R0; - - // But first raise interrupt 15 so we can do one test - // in supervisor mode. - RAISE 15; - NOP; - - RTI; - - // Nops to work around ICache bug - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - - -int_15: - // Interrupt 15 handler - needed to try supervisor access with exceptions enabled - //------------------------------------------------------- - // Protection violation - Illegal Supervisor Write Access - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - LD32(i1, 0x800); - LD32(r1, 0xDEADBEEF); - - LD32(p2, DCPLB_DATA0); - LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); - - LD32(p3, DCPLB_DATA1); - LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); - - -X0: //[p1] = r1; // Exception should occur here - A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1 - - - // Now check that handler read correct values - CHECKREG(r4,0x23); // supv and EXCPT_PROT - CHECKREG(r5, 0x800); - CHECKREG(r6, (FAULT_SUPV|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB0)); - CHECKREG_SYM(r7, X0, r0); // RETX should be value of X0 (HARDCODED ADDR!!) - - // go to user mode. and enable exceptions - LD32_LABEL(r0, User); - RTI; - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - - -User: - NOP;NOP;NOP;NOP;NOP; - - //------------------------------------------------------- - // Protection violation - Illegal User Write Access - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - LD32(i1, 0x1000); - LD32(r1, 0xDEADBEEF); - - - // values to fix up current test - LD32(p2, DCPLB_DATA1); - LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); - - // values for next test - LD32(p3, DCPLB_DATA2); - LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE); - -X1: //[p1] = r1; // Exception should occur here - A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1 - - // Now check that handler read correct values - - CHECKREG(r4,0x23); // supv and EXCPT_PROT - CHECKREG(r5, 0x1000); - CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB1)); - CHECKREG_SYM(r7, X1, r0); // RETX should be value of X1 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - // Protection violation - Illegal User Read Access - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - LD32(i1, 0x2000); - LD32(r1, 0xDEADBEEF); - - LD32(p2, DCPLB_DATA2); - LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RO|CPLB_SUPV_WR); - - LD32(p3, DCPLB_DATA3); - LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); - -X2: //[p1] = r1; // Exception should occur here - A0 = 0 || NOP || R0 = [ I1 ]; // test access with DAG1 - - - // Now check that handler read correct values - CHECKREG(r4,0x23); // supv and EXCPT_PROT - CHECKREG(r5, 0x2000); - CHECKREG(r6, (FAULT_USER|FAULT_READ|FAULT_DAG1 | FAULT_CPLB2)); - CHECKREG_SYM(r7, X2, r0); // RETX should be value of X2 (HARDCODED ADDR!!) - - //------------------------------------------------------- - // Protection violation - Illegal Dirty Page Access - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - LD32(i1, 0x3000); - LD32(r1, 0xDEADBEEF); - - LD32(p2, DCPLB_DATA3); - LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); - - LD32(p3, DCPLB_DATA4); - LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DA0ACC|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); - - -X3: //[p1] = r1; // Exception should occur here - A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1 - - - // Now check that handler read correct values - CHECKREG(r4,0x23); // supv and EXCPT_PROT - CHECKREG(r5, 0x3000); - CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB3)); - CHECKREG_SYM(r7, X3, r0); // RETX should be value of X3 (HARDCODED ADDR!!) - - //------------------------------------------------------- - // Protection violation - Illegal DAG1 Access - R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; - - LD32(i1, 0x4000); - LD32(r1, 0xDEADBEEF); - - LD32(p2, DCPLB_DATA4); - LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); - - LD32(p3, DCPLB_DATA5); - LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); - - -X4: //[p1] = r1; // Exception should occur here - A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1 - - - // Now check that handler read correct values - CHECKREG(r4,0x23); // supv and EXCPT_PROT - CHECKREG(r5, 0x4000); - CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB4)); - CHECKREG_SYM(r7, X4, r0); // RETX should be value of X4 (HARDCODED ADDR!!) - - //------------------------------------------------------- - // L1Miss not implemented yet - skip for now.... - -// //------------------------------------------------------- -// // Protection violation - L1 Miss -// r0=0;r1=0;r2=0;r3=0;r4=0;r5=0;r6=0;r7=0; -// -// LD32(p1, 0x6000); -// LD32(r1, 0xDEADBEEF); -// -// LD32(p2, DCPLB_DATA6); -// LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); -// -// LD32(p3, DCPLB_DATA7); -// LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_USER_RW|CPLB_SUPV_WR); -// -// -//X6: //[p1] = r1; // Exception should occur here -// r0 = [p1]; -// -// -// // Now check that handler read correct values -// CHECKREG(r4,0x23); // supv and EXCPT_PROT -// CHECKREG(r5, 0x6000); -// // CHECKREG(r6, FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB6); -// CHECKREG_SYM(r7, X6, r0); // RETX should be value of X6 (HARDCODED ADDR!!) - - - //------------------------------------------------------- - dbg_pass; - - -handler: - // generic protection exception handler - // Inputs: - // p2: addr of CPLB entry to be modified ( current test) - // r2: new data for CPLB entry - // - // p3: addr of CPLB entry to be modified ( next test) - // r3: new data for CPLB entry - // - // Outputs: - // r4: SEQSTAT - // r5: DCPLB_FAULT_ADDR - // r6: DCPLB_STATUS - // r7: RETX (instruction addr where exception occurred) - - - R4 = SEQSTAT; // Get exception cause - - // read data addr which caused exception - RD_MMR(DCPLB_FAULT_ADDR, p0, r5); - RD_MMR(DCPLB_STATUS, p0, r6); - - // Reset status regs - WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r0); - WR_MMR(DCPLB_STATUS, 0, p0, r0); - - R7 = RETX; // get address of excepting instruction - - - // modify CPLB to allow access. Main pgm passes in addr and data - [ P2 ] = R2; - - // Set up for next test - [ P3 ] = R3; - - NOP;NOP;NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC; - - // return from exception and re-execute offending instruction - RTX; - - // Nops to work around ICache bug - NOP;NOP;NOP;NOP;NOP; - NOP;NOP;NOP;NOP;NOP; - - -.section MEM_0x800,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -.section MEM_0x1000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -.section MEM_0x2000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -.section MEM_0x3000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -.section MEM_0x4000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -.section MEM_0x5000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - -// Need a cache miss to test CPLB_L1REF -//.data 0x6000 -// .dd 0x00000000 -// .dd 0x00000000 -// .dd 0x00000000 -// .dd 0x00000000 - -.section MEM_0x7000,"aw" - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 - .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/load.s b/sim/testsuite/sim/bfin/load.s deleted file mode 100644 index 2fca3de..0000000 --- a/sim/testsuite/sim/bfin/load.s +++ /dev/null @@ -1,239 +0,0 @@ -# Blackfin testcase for register load instructions -# mach: bfin - - - .include "testutils.inc" - - start - - .macro load32 num:req, reg0:req, reg1:req - imm32 \reg0 \num - imm32 \reg1 \num - CC = \reg0 == \reg1 - if CC jump 2f; - fail -2: - .endm - - .macro load32p num:req preg:req - imm32 r0 \num - imm32 \preg \num - r1 = \preg - cc = r0 == r1 - if CC jump 3f; - fail -3: - imm32 \preg 0 - .endm - - .macro load16z num:req reg0:req reg1:req - \reg0 = \num (Z); - imm32 \reg1 \num - CC = \reg0 == \reg1 - if CC jump 4f; - fail -4: - .endm - - .macro load16zp num:req reg:req - \reg = \num (Z); - imm32 r1 \num; - r0 = \reg; - cc = r0 == r1 - if CC jump 5f; - fail -5: - .endm - - .macro load16x num:req reg0:req reg1:req - \reg0 = \num (X); - imm32 \reg1, \num - CC = \reg0 == \reg1 - if CC jump 6f; - fail -6: - .endm - - /* Clobbers R0 */ - .macro loadinc preg0:req, preg1:req, dreg:req - loadsym \preg0, _buf - \preg1 = \preg0; - \dreg = \preg0; - [\preg0\()++] = \preg0; - \dreg += 4; - R0 = \preg0; - CC = \dreg == R0; - if CC jump 7f; - fail -7: - R0 = [ \preg1\() ]; - \dreg += -4; - CC = \dreg == R0; - if CC jump 8f; - fail -8: - .endm - - /* test a bunch of values */ - - /* load_immediate (Half-Word Load) - * register = constant - * reg_lo = uimm16; - * reg_hi = uimm16; - */ - - load32 0 R0 R1 - load32 0xFFFFFFFF R0 R1 - load32 0x55aaaa55 r0 r1 - load32 0x12345678 r0 r1 - load32 0x12345678 R0 R2 - load32 0x23456789 R0 R3 - load32 0x3456789a R0 R4 - load32 0x456789ab R0 R5 - load32 0x56789abc R0 R6 - load32 0x6789abcd R0 R7 - load32 0x789abcde R0 R0 - load32 0x89abcdef R1 R0 - load32 0x9abcdef0 R2 R0 - load32 0xabcdef01 R3 R0 - load32 0xbcdef012 R4 R0 - load32 0xcdef0123 R5 R0 - load32 0xdef01234 R6 R0 - load32 0xef012345 R7 R0 - - load32p 0xf0123456 P0 - load32p 0x01234567 P1 - load32p 0x12345678 P2 -.ifndef BFIN_HOST - load32p 0x23456789 P3 -.endif - load32p 0x3456789a P4 - load32p 0x456789ab P5 - load32p 0x56789abc SP - load32p 0x6789abcd FP - - load32p 0x789abcde I0 - load32p 0x89abcdef I1 - load32p 0x9abcdef0 I2 - load32p 0xabcdef01 I3 - load32p 0xbcdef012 M0 - load32p 0xcdef0123 M1 - load32p 0xdef01234 M2 - load32p 0xef012345 M3 - - load32p 0xf0123456 B0 - load32p 0x01234567 B1 - load32p 0x12345678 B2 - load32p 0x23456789 B3 - load32p 0x3456789a L0 - load32p 0x456789ab L1 - load32p 0x56789abc L2 - load32p 0x6789abcd L3 - - /* Zero Extended */ - load16z 0x1234 R0 R1 - load16z 0x2345 R0 R1 - load16z 0x3456 R0 R2 - load16z 0x4567 R0 R3 - load16z 0x5678 R0 R4 - load16z 0x6789 R0 R5 - load16z 0x789a R0 R6 - load16z 0x89ab R0 R7 - load16z 0x9abc R1 R0 - load16z 0xabcd R2 R0 - load16z 0xbcde R3 R0 - load16z 0xcdef R4 R0 - load16z 0xdef0 R5 R0 - load16z 0xef01 R6 R0 - load16z 0xf012 R7 R0 - - load16zp 0x0123 P0 - load16zp 0x1234 P1 - load16zp 0x1234 p2 -.ifndef BFIN_HOST - load16zp 0x2345 p3 -.endif - load16zp 0x3456 p4 - load16zp 0x4567 p5 - load16zp 0x5678 sp - load16zp 0x6789 fp - load16zp 0x789a i0 - load16zp 0x89ab i1 - load16zp 0x9abc i2 - load16zp 0xabcd i3 - load16zp 0xbcde m0 - load16zp 0xcdef m1 - load16zp 0xdef0 m2 - load16zp 0xef01 m3 - load16zp 0xf012 b0 - load16zp 0x0123 b1 - load16zp 0x1234 b2 - load16zp 0x2345 b3 - load16zp 0x3456 l0 - load16zp 0x4567 l1 - load16zp 0x5678 l2 - load16zp 0x6789 l3 - - /* Sign Extended */ - load16x 0x20 R0 R1 - load16x 0x3F R0 R1 - load16x -0x20 R0 R1 - load16x -0x3F R0 R1 - load16x 0x1234 R0 R1 - load16x 0x2345 R0 R1 - load16x 0x3456 R0 R2 - load16x 0x4567 R0 R3 - load16x 0x5678 R0 R4 - load16x 0x6789 R0 R5 - load16x 0x789a R0 R6 - load16x 0x09ab R0 R7 - load16x -0x1abc R1 R0 - load16x -0x2bcd R2 R0 - load16x -0x3cde R3 R0 - load16x -0x4def R4 R0 - load16x -0x5ef0 R5 R0 - load16x -0x6f01 R6 R0 - load16x -0x7012 R7 R0 - - loadinc P0, P1, R1 - loadinc P1, P2, R1 - loadinc P2, P1, R2 -.ifndef BFIN_HOST - loadinc P3, P4, R3 -.endif - loadinc P4, P5, R4 - loadinc FP, P0, R7 - loadinc P0, I0, R1 - loadinc P1, I1, R1 - loadinc P2, I2, R1 -.ifndef BFIN_HOST - loadinc P3, I0, R1 -.endif - loadinc P4, I2, R1 - loadinc P5, I3, R1 - - A1 = A0 = 0; - R0 = 0x01 (Z); - A0.x = R0; - imm32 r4, 0x32e02d1a - A1.x = R4; - A0.w = A1.x; - R3 = A0.w; - R2 = A0.x; - imm32 r0, 0x0000001a - imm32 r1, 0x00000001 - CC = R1 == R2; - if CC jump 1f; - fail -1: - CC = R0 == R3 - if CC jump 2f; - fail -2: - pass - -.data -_buf: - .rept 0x80 - .long 0 - .endr diff --git a/sim/testsuite/sim/bfin/logic.s b/sim/testsuite/sim/bfin/logic.s deleted file mode 100644 index 9a41ccd..0000000 --- a/sim/testsuite/sim/bfin/logic.s +++ /dev/null @@ -1,64 +0,0 @@ -// test program for microcontroller instructions -// Test instructions -// r4 = r2 & r3; -// r4 = r2 | r3; -// r4 = r2 ^ r3; -// r4 = ~ r2; -# mach: bfin - -.include "testutils.inc" - start - - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - - R7 = R0 & R1; - DBGA ( R7.L , 0x1111 ); - DBGA ( R7.H , 0x1111 ); - - R7 = R2 & R3; - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0000 ); - - R7 = R0 | R1; - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0xffff ); - - R7 = R2 | R3; - DBGA ( R7.L , 0x000f ); - DBGA ( R7.H , 0x0000 ); - - R7 = R0 ^ R1; - DBGA ( R7.L , 0xeeee ); - DBGA ( R7.H , 0xeeee ); - - R7 = R2 ^ R3; - DBGA ( R7.L , 0x000e ); - DBGA ( R7.H , 0x0000 ); - - R7 = ~ R0; - DBGA ( R7.L , 0xeeee ); - DBGA ( R7.H , 0xeeee ); - - R7 = ~ R2; - DBGA ( R7.L , 0xfffe ); - DBGA ( R7.H , 0xffff ); - - pass - - .data -data0: - .dw 0x1111 - .dw 0x1111 - .dw 0xffff - .dw 0xffff - .dw 0x0001 - .dw 0x0000 - .dw 0x000f - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/loop_snafu.s b/sim/testsuite/sim/bfin/loop_snafu.s deleted file mode 100644 index b1e3664..0000000 --- a/sim/testsuite/sim/bfin/loop_snafu.s +++ /dev/null @@ -1,28 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - r5=10; - p1=r5; - r7=20; - lsetup (lstart, lend) lc0=p1; - -lstart: - nop; - nop; - nop; - nop; - jump lend; - nop; - nop; - nop; -lend: - r7 += -1; - - nop; - nop; - - dbga( r7.l,10); - - pass diff --git a/sim/testsuite/sim/bfin/loop_strncpy.s b/sim/testsuite/sim/bfin/loop_strncpy.s deleted file mode 100644 index 13b3711..0000000 --- a/sim/testsuite/sim/bfin/loop_strncpy.s +++ /dev/null @@ -1,76 +0,0 @@ -# Blackfin testcase for loop counter values when jumping out from the last insn -# mach: bfin - -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - - loadsym r1, dest; - r0 = r1; - loadsym r1, src; - r2 = 0x10; - -_strncpy: - CC = R2 == 0; - if CC JUMP 4f; - - P2 = R2 ; /* size */ - P0 = R0 ; /* dst*/ - P1 = R1 ; /* src*/ - - LSETUP (1f, 2f) LC0 = P2; -1: - R1 = B [P1++] (Z); - B [P0++] = R1; - CC = R1 == 0; -2: - if CC jump 3f; - - fail - - /* if src is shorter than n, we need to null pad bytes in dest - * but, we can get here when the last byte is zero, and we don't - * want to copy an extra byte at the end, so we need to check - */ -3: - R2 = LC0; - CHECKREG R2, 0x0a; - - CC = R2 - if ! CC jump 4f; - - LSETUP(5f, 5f) LC0; -5: - B [P0++] = R1; - -4: - loadsym P1, answer; - P0 = R0; - p2 = 0x20; - LSETUP (6f, 7f) LC0 = P2; -6: - R1 = B [P0++]; - R2 = B [P1++]; - CC = R1 == R2 - IF ! CC JUMP wrong; -7: - NOP; - - pass - -wrong: - fail - - .data -dest: - .db 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F - .db 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F - -src: - .db 0x21, 0x22, 0x23, 0x24, 0x25, 0x00, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30 - -answer: - .db 0x21, 0x22, 0x23, 0x24, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - .db 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F diff --git a/sim/testsuite/sim/bfin/lp0.s b/sim/testsuite/sim/bfin/lp0.s deleted file mode 100644 index dd7bc30..0000000 --- a/sim/testsuite/sim/bfin/lp0.s +++ /dev/null @@ -1,17 +0,0 @@ -// Assert that loops can have coincidental loop ends. -# mach: bfin - -.include "testutils.inc" - start - - - P0 = 3; - R1 = 0; - LSETUP ( out0 , out1 ) LC0 = P0; -out0: - LSETUP ( out1 , out1 ) LC1 = P0; -out1: - R1 += 1; - - DBGA ( R1.L , 9 ); - pass diff --git a/sim/testsuite/sim/bfin/lp1.s b/sim/testsuite/sim/bfin/lp1.s deleted file mode 100644 index 89fa2a9..0000000 --- a/sim/testsuite/sim/bfin/lp1.s +++ /dev/null @@ -1,16 +0,0 @@ -# mach: bfin -.include "testutils.inc" - start - - P0 = 10; - - LSETUP ( xxx , yyy ) LC0 = P0; -xxx: - R1 += 1; - CC = R1 == 3; -yyy: - IF CC JUMP zzz; - R3 = 7; -zzz: - DBGA ( R1.L , 3 ); - pass diff --git a/sim/testsuite/sim/bfin/lsetup.s b/sim/testsuite/sim/bfin/lsetup.s deleted file mode 100644 index ac39613..0000000 --- a/sim/testsuite/sim/bfin/lsetup.s +++ /dev/null @@ -1,109 +0,0 @@ -# Blackfin testcase for playing with LSETUP -# mach: bfin - - .include "testutils.inc" - - start - - R0 = 0x123; - P0 = R0; - LSETUP (.L1, .L1) LC0 = P0; -.L1: - R0 += -1; - - R1 = 0; - CC = R1 == R0; - IF CC JUMP 1f; - fail -1: - p0=10; - loadsym i0, _buf - imm32 r0, 0x12345678 - LSETUP(.L2, .L3) lc0 = p0; -.L2: - [i0++] = r0; -.L3: - [i0++] = r0; - - loadsym R1, _buf - R0 = 0x50; - R1 = R0 + R1; - R0 = I0; - CC = R0 == R1; - if CC JUMP 2f; - fail -2: - - r5=10; - p1=r5; - r7=20; - lsetup (.L4, .L5) lc0=p1; -.L4: - nop; - nop; - nop; - nop; - jump .L5; - nop; - nop; - nop; -.L5: - r7 += -1; - - R0 = 10 (Z); - CC = R7 == R0; - if CC jump 3f; - fail -3: - r1 = 1; - r2 = 2; - r0 = 0; - p1 = 10; - loadsym p0, _buf; - lsetup (.L6, .L7) lc0 = p1; -.L6: - [p0++] = r1; -.L7: - [p0++] = r2; - - r3 = P0; - loadsym r1, _buf - r0 = 80; - r1 = r1 + r0; - CC = R1 == R3 - if CC jump 4f; - fail -4: - - R0 = 1; - R1 = 2; - R2 = 3; - R4 = 4; - P1 = R1; - LSETUP (.L8, .L8) LC0 = P1; - R5 = 5; - R6 = 6; - R7 = 7; -.L8: - R1 += 1; - - R7 = 4; - CC = R7 == R1; - if CC jump 5f; - fail -5: - P1 = R1; - LSETUP (.L9, .L9 ) LC1 = P1; -.L9: - R1 += 1; - R7 = 8; - if CC jump 6f; - fail -6: - pass - -.data -_buf: - .rept 0x80 - .long 0 - .endr diff --git a/sim/testsuite/sim/bfin/m0boundary.s b/sim/testsuite/sim/bfin/m0boundary.s deleted file mode 100644 index 5995d88..0000000 --- a/sim/testsuite/sim/bfin/m0boundary.s +++ /dev/null @@ -1,46 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - -// setup a circular buffer calculation based on illegal register values - I0 = 0xf2ef (Z); - I0.H = 0xff88; - - L0 = 0xbd5f (Z); - L0.H = 0xea9b; - - M0 = 0x0000 (Z); - M0.H = 0x8000; - - B0 = 0x3fb9 (Z); - B0.H = 0xff80; - -op1: - I0 -= M0; - - R0 = I0; - DBGA ( R0.H , 0x7f88 ); - DBGA ( R0.L , 0xf2ef ); - -// setup a circular buffer calculation based on illegal register values - I0 = 0xf2ef (Z); - I0.H = 0xff88; - - L0 = 0xbd5f (Z); - L0.H = 0xea9b; - - M0 = 0x0001 (Z); - M0.H = 0x8000; - - B0 = 0x3fb9 (Z); - B0.H = 0xff80; - -op2: - I0 -= M0; - - R0 = I0; - DBGA ( R0.H , 0x7f88 ); - DBGA ( R0.L , 0xf2ee ); - - pass diff --git a/sim/testsuite/sim/bfin/m1.S b/sim/testsuite/sim/bfin/m1.S deleted file mode 100644 index 5ddc5d3..0000000 --- a/sim/testsuite/sim/bfin/m1.S +++ /dev/null @@ -1,58 +0,0 @@ -// MAC test program. -// Test for positive and negative saturation using -// SIGNED FRACTIONAL mode. -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - -// load r0=0x00007fff -// load r1=0x00007fff - loadsym p0, data0 - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - - R5 = 0; - R4 = 0; - BITSET( R4 , 9 ); - A1 = A0 = 0; - -LOOP1: - A1 -= R0.L * R1.L, A0 += R0.L * R1.L; -//_DBG a1; -//_DBG a0; - R4 += -1; - CC = R4 == R5; - IF !CC JUMP LOOP1; -R3 = ASTAT; -CHECKREG R3, (_AV1S|_AV1|_AV0S|_AV0|_AC0|_AC0_COPY|_CC|_AZ); - - _DBG A1; - _DBG A0; - - R6 = A1.w; - _DBG ASTAT; - R7.L = A1.x; - R3 = ASTAT; - _DBG r3; - CHECKREG R3, (_AV1S|_AV1|_AV0S|_AV0|_AC0|_AC0_COPY|_CC|_AZ); - - CHECKREG R6, 0; - CHECKREG R7, 0x0000FF80; - R6 = A0.w; - R7.L = A0.x; - CHECKREG R6, 0xffffffff; - CHECKREG R7, 0x7f; - - pass - - .data 0x1000; -data0: - .dw 0x7fff - .dw 0x0000 - .dw 0x7fff - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m10.s b/sim/testsuite/sim/bfin/m10.s deleted file mode 100644 index 5feb42f..0000000 --- a/sim/testsuite/sim/bfin/m10.s +++ /dev/null @@ -1,63 +0,0 @@ -# mach: bfin - -// Test extraction from accumulators: -// ROUND/TRUNCATE in UNSIGNED FRACTIONAL mode -// test ops: "+=" - -.include "testutils.inc" - start - - -// load r0=0xfffef000 -// load r1=0xfffff000 -// load r2=0x00008000 -// load r3=0x00018000 -// load r4=0x0000007f - loadsym P0, data0 - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// round -// 0x00fffef000 -> 0xffff - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R5.H = A1, R5.L = A0 (FU); - DBGA ( R5.L , 0xffff ); - DBGA ( R5.H , 0xffff ); - -// truncate -// 0x00fffef00 -> 0xfffe - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R5.H = A1, R5.L = A0 (TFU); - DBGA ( R5.L , 0xfffe ); - DBGA ( R5.H , 0xfffe ); - -// round -// 0x00fffff000 -> 0xffff - A1 = A0 = 0; - A1.w = R1; - A0.w = R1; - R5.H = A1, R5.L = A0 (FU); - DBGA ( R5.L , 0xffff ); - DBGA ( R5.H , 0xffff ); - - pass - - .data; -data0: - .dw 0xf000 - .dw 0xfffe - .dw 0xf000 - .dw 0xffff - .dw 0x8000 - .dw 0x0000 - .dw 0x8000 - .dw 0x0001 - .dw 0x007f - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m11.s b/sim/testsuite/sim/bfin/m11.s deleted file mode 100644 index 843c0ab..0000000 --- a/sim/testsuite/sim/bfin/m11.s +++ /dev/null @@ -1,72 +0,0 @@ -// Test extraction from accumulators: -// SCALE in SIGNED FRACTIONAL mode -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x3fff0000 -// load r1=0x0fffc000 -// load r2=0x7ff00000 -// load r3=0x80100000 -// load r4=0x000000ff - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// SCALE -// 0x003fff0000 -> SCALE 0x7ffe - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R5.H = A1, R5.L = A0 (S2RND); - DBGA ( R5.L , 0x7ffe ); - DBGA ( R5.H , 0x7ffe ); - -// SCALE -// 0x000fffc000 -> SCALE 0x2000 - A1 = A0 = 0; - A1.w = R1; - A0.w = R1; - R5.H = A1, R5.L = A0 (S2RND); - DBGA ( R5.L , 0x2000 ); - DBGA ( R5.H , 0x2000 ); - -// SCALE -// 0x007ff00000 -> SCALE 0x7fff - A1 = A0 = 0; - A1.w = R2; - A0.w = R2; - R5.H = A1, R5.L = A0 (S2RND); - DBGA ( R5.L , 0x7fff ); - DBGA ( R5.H , 0x7fff ); - -// SCALE -// 0xff80100000 -> SCALE 0x8000 - A1 = A0 = 0; - A1.w = R3; - A0.w = R3; - A1.x = R4.L; - A0.x = R4.L; - R5.H = A1, R5.L = A0 (S2RND); - DBGA ( R5.L , 0x8000 ); - DBGA ( R5.H , 0x8000 ); - - pass - - .data; -data0: - .dw 0x0000 - .dw 0x3fff - .dw 0xc000 - .dw 0x0fff - .dw 0x0000 - .dw 0x7ff0 - .dw 0x0000 - .dw 0x8010 - .dw 0x00ff - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m12.s b/sim/testsuite/sim/bfin/m12.s deleted file mode 100644 index 37306e7..0000000 --- a/sim/testsuite/sim/bfin/m12.s +++ /dev/null @@ -1,74 +0,0 @@ -// Test extraction from accumulators: -// SCALE in SIGNED INTEGER mode -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x00000fff -// load r1=0x00007fff -// load r2=0xffffffff -// load r3=0xffff0fff -// load r4=0x000000ff - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// SCALE -// 0x0000000fff -> SCALE 0x1ffe - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R5.H = A1, R5.L = A0 (ISS2); - DBGA ( R5.L , 0x1ffe ); - DBGA ( R5.H , 0x1ffe ); - -// SCALE -// 0x0000007fff -> SCALE 0x7fff - A1 = A0 = 0; - A1.w = R1; - A0.w = R1; - R5.H = A1, R5.L = A0 (ISS2); - DBGA ( R5.L , 0x7fff ); - DBGA ( R5.H , 0x7fff ); - -// SCALE -// 0xffffffffff -> SCALE 0xfffe - A1 = A0 = 0; - A1.w = R2; - A0.w = R2; - A1.x = R4.L; - A0.x = R4.L; - R5.H = A1, R5.L = A0 (ISS2); - DBGA ( R5.L , 0xfffe ); - DBGA ( R5.H , 0xfffe ); - -// SCALE -// 0xffffff0fff -> SCALE 0x8000 - A1 = A0 = 0; - A1.w = R3; - A0.w = R3; - A1.x = R4.L; - A0.x = R4.L; - R5.H = A1, R5.L = A0 (ISS2); - DBGA ( R5.L , 0x8000 ); - DBGA ( R5.H , 0x8000 ); - - pass - - .data -data0: - .dw 0x0fff - .dw 0x0000 - .dw 0x7fff - .dw 0x0000 - .dw 0xffff - .dw 0xffff - .dw 0x0fff - .dw 0xffff - .dw 0x00ff - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m13.s b/sim/testsuite/sim/bfin/m13.s deleted file mode 100644 index 05547a7..0000000 --- a/sim/testsuite/sim/bfin/m13.s +++ /dev/null @@ -1,93 +0,0 @@ -// Test extraction from accumulators: -// SIGNED FRACTIONAL and SIGNED INT mode into register PAIR -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x7ffffff0 -// load r1=0xfffffff0 -// load r2=0x0fffffff -// load r3=0x80100000 -// load r4=0x000000ff - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// extract -// 0x007ffffff0 -> 0x7fffffff0 - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R7 = A1, R6 = A0; - DBGA ( R7.L , 0xfff0 ); - DBGA ( R7.H , 0x7fff ); - DBGA ( R6.L , 0xfff0 ); - DBGA ( R6.H , 0x7fff ); - -// extract with saturate -// 0x00fffffff0 -> 0x7ffffffff - A1 = A0 = 0; - A1.w = R1; - A0.w = R1; - R7 = A1, R6 = A0; - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x7fff ); - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0x7fff ); - -// extract with saturate negative -// 0xff0ffffff0 -> 0x80000000 - A1 = A0 = 0; - A1.w = R2; - A0.w = R2; - A1.x = R4.L; - A0.x = R4.L; - R7 = A1, R6 = A0; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x8000 ); - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8000 ); - -// extract integer (same as fract) -// 0x007ffffff0 -> 0x7fffffff0 - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R7 = A1, R6 = A0 (IS); - DBGA ( R7.L , 0xfff0 ); - DBGA ( R7.H , 0x7fff ); - DBGA ( R6.L , 0xfff0 ); - DBGA ( R6.H , 0x7fff ); - -// extract with saturate negative -// 0xff0ffffff0 -> 0x80000000 - A1 = A0 = 0; - A1.w = R2; - A0.w = R2; - A1.x = R4.L; - A0.x = R4.L; - R7 = A1, R6 = A0 (IS); - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x8000 ); - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8000 ); - - pass - - .data -data0: - .dw 0xfff0 - .dw 0x7fff - .dw 0xfff0 - .dw 0xffff - .dw 0xffff - .dw 0x0fff - .dw 0x0000 - .dw 0x8010 - .dw 0x00ff - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m14.s b/sim/testsuite/sim/bfin/m14.s deleted file mode 100644 index bd3134e..0000000 --- a/sim/testsuite/sim/bfin/m14.s +++ /dev/null @@ -1,82 +0,0 @@ -// Test extraction from accumulators: -// UNSIGNED FRACTIONAL and SIGNED INT mode into register PAIR -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x7ffffff0 -// load r1=0xfffffff0 -// load r2=0x0fffffff -// load r3=0x00000001 -// load r4=0x000000ff - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// extract -// 0x00fffffff0 -> 0xffffffff0 - A1 = A0 = 0; - A1.w = R1; - A0.w = R1; - R7 = A1, R6 = A0 (FU); - DBGA ( R7.L , 0xfff0 ); - DBGA ( R7.H , 0xffff ); - DBGA ( R6.L , 0xfff0 ); - DBGA ( R6.H , 0xffff ); - -// extract with saturation -// 0x01fffffff0 -> 0xfffffffff - A1 = A0 = 0; - A1.w = R1; - A0.w = R1; - A1.x = R3.L; - A0.x = R3.L; - R7 = A1, R6 = A0 (FU); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0xffff ); - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0xffff ); - -// extract with saturation -// 0xfffffffff0 -> 0xfffffffff - A1 = A0 = 0; - A1.w = R1; - A0.w = R1; - A1.x = R4.L; - A0.x = R4.L; - R7 = A1, R6 = A0 (FU); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0xffff ); - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0xffff ); - -// extract unsigned -// 0x00fffffff0 -> 0xffffffff0 - A1 = A0 = 0; - A1.w = R1; - A0.w = R1; - R7 = A1, R6 = A0 (FU); - DBGA ( R7.L , 0xfff0 ); - DBGA ( R7.H , 0xffff ); - DBGA ( R6.L , 0xfff0 ); - DBGA ( R6.H , 0xffff ); - - pass - - .data -data0: - .dw 0xfff0 - .dw 0x7fff - .dw 0xfff0 - .dw 0xffff - .dw 0xffff - .dw 0x0fff - .dw 0x0001 - .dw 0x0000 - .dw 0x00ff - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m15.s b/sim/testsuite/sim/bfin/m15.s deleted file mode 100644 index e429232..0000000 --- a/sim/testsuite/sim/bfin/m15.s +++ /dev/null @@ -1,80 +0,0 @@ -// Test extraction from accumulators: -// SIGNED FRACTIONAL and SIGNED INT mode into register PAIR with SCALE -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x0ffffff0 -// load r1=0x7ffffff0 -// load r2=0x0fffffff -// load r3=0x80100000 -// load r4=0x000000ff - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// extract -// 0x000ffffff0 -> 0x1ffffffe0 - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R7 = A1, R6 = A0 (S2RND); - DBGA ( R7.L , 0xffe0 ); - DBGA ( R7.H , 0x1fff ); - DBGA ( R6.L , 0xffe0 ); - DBGA ( R6.H , 0x1fff ); - -// extract (saturate) -// 0x007ffffff0 -> 0x7ffffffff - A1 = A0 = 0; - A1.w = R1; - A0.w = R1; - R7 = A1, R6 = A0 (S2RND); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x7fff ); - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0x7fff ); - -// extract (saturate negative) -// 0xff0ffffff0 -> 0x80000000 - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - A1.x = R4.L; - A0.x = R4.L; - R7 = A1, R6 = A0 (S2RND); - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x8000 ); - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8000 ); - -// extract int -// 0x000ffffff0 -> 0x1ffffffe0 - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R7 = A1, R6 = A0 (ISS2); - DBGA ( R7.L , 0xffe0 ); - DBGA ( R7.H , 0x1fff ); - DBGA ( R6.L , 0xffe0 ); - DBGA ( R6.H , 0x1fff ); - - pass - - .data -data0: - .dw 0xfff0 - .dw 0x0fff - .dw 0xfff0 - .dw 0x7fff - .dw 0xffff - .dw 0x0fff - .dw 0x0000 - .dw 0x8010 - .dw 0x00ff - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m16.s b/sim/testsuite/sim/bfin/m16.s deleted file mode 100644 index 9cbc57c..0000000 --- a/sim/testsuite/sim/bfin/m16.s +++ /dev/null @@ -1,65 +0,0 @@ -// Test various moves to single register half -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x7fffffff -// load r1=0x00ffffff -// load r2=0xf0000000 -// load r3=0x0000007f -// load r4=0x00000080 - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// extract only to high half - R5 = 0; - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R5.H = A1; - DBGA ( R5.L , 0x0000 ); - DBGA ( R5.H , 0x7fff ); - -// extract only to low half - R5 = 0; - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R5.L = A0; - DBGA ( R5.L , 0x7fff ); - DBGA ( R5.H , 0x0000 ); - -// extract only to high half - R5 = 0; - A1 = A0 = 0; - R5.H = ( A1 += R0.H * R0.H ), A0 += R0.H * R0.H; - DBGA ( R5.L , 0x0000 ); - DBGA ( R5.H , 0x7ffe ); - -// extract only to low half - R5 = 0; - A1 = A0 = 0; - A1 += R0.H * R0.H, R5.L = ( A0 += R0.H * R0.H ); - DBGA ( R5.L , 0x7ffe ); - DBGA ( R5.H , 0x0000 ); - - pass - - .data -data0: - .dw 0xffff - .dw 0x7fff - .dw 0xffff - .dw 0x00ff - .dw 0x0000 - .dw 0xf000 - .dw 0x007f - .dw 0x0000 - .dw 0x0080 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m17.s b/sim/testsuite/sim/bfin/m17.s deleted file mode 100644 index c7aec4b..0000000 --- a/sim/testsuite/sim/bfin/m17.s +++ /dev/null @@ -1,74 +0,0 @@ -// Test various moves to single register -# mach: bfin - - -.include "testutils.inc" - start - - -// load r0=0x7fffffff -// load r1=0x00ffffff -// load r2=0xf0000000 -// load r3=0x0000007f - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - -// extract only to high register - R5 = 0; - R4 = 0; - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R5 = A1; - DBGA ( R4.L , 0x0000 ); - DBGA ( R4.H , 0x0000 ); - DBGA ( R5.L , 0xffff ); - DBGA ( R5.H , 0x7fff ); - -// extract only to low register - R5 = 0; - R4 = 0; - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R4 = A0; - DBGA ( R4.L , 0xffff ); - DBGA ( R4.H , 0x7fff ); - DBGA ( R5.L , 0x0000 ); - DBGA ( R5.H , 0x0000 ); - -// extract only to high reg - R5 = 0; - R4 = 0; - A1 = A0 = 0; - R5 = ( A1 += R0.H * R0.H ), A0 += R0.H * R0.H; - DBGA ( R4.L , 0x0000 ); - DBGA ( R4.H , 0x0000 ); - DBGA ( R5.L , 0x0002 ); - DBGA ( R5.H , 0x7ffe ); - -// extract only to low reg - R5 = 0; - R4 = 0; - A1 = A0 = 0; - A1 += R0.H * R0.H, R4 = ( A0 += R0.H * R0.H ); - DBGA ( R4.L , 0x0002 ); - DBGA ( R4.H , 0x7ffe ); - DBGA ( R5.L , 0x0000 ); - DBGA ( R5.H , 0x0000 ); - - pass - - .data -data0: - .dw 0xffff - .dw 0x7fff - .dw 0xffff - .dw 0x00ff - .dw 0x0000 - .dw 0xf000 - .dw 0x007f - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m2.s b/sim/testsuite/sim/bfin/m2.s deleted file mode 100644 index 2ff155c..0000000 --- a/sim/testsuite/sim/bfin/m2.s +++ /dev/null @@ -1,263 +0,0 @@ -// MAC test program. -// Test basic edge values -// SIGNED FRACTIONAL mode -// test ops: "+=" "-=" "=" "NOP" -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x80007fff -// load r1=0x80007fff -// load r2=0xf0000000 -// load r3=0x0000007f -// load r4=0x00000080 - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// 0x7fff * 0x7fff = 0x007ffe0002 - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1 += R0.L * R1.L, A0 += R0.L * R1.L; - R6 = A1.w; - _DBG ASTAT; - _DBG A0; - R7.L = A1.x; - _DBG ASTAT; - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x7ffe ); - DBGA ( R7.L , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// 0x8000 * 0x7fff = 0xff80010000 - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1 += R0.H * R1.L, A0 += R0.H * R1.L; - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8001 ); - DBGA ( R7.L , 0xffff ); - _DBG ASTAT; - R7 = ASTAT; - DBGA (R7.H, 0x0); - DBGA (R7.L, 0x0); - -// 0x8000 * 0x8000 = 0x007fffffff - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1 += R0.H * R1.H, A0 += R0.H * R1.H; - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8000 ); - DBGA ( R7.L , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// saturate positive by first loading large value into accums -// expected value is 0x7fffffffff - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1.w = R2; - A1.x = R3.L; - A0.w = R2; - A0.x = R3.L; - A1 += R0.L * R1.L, A0 += R0.L * R1.L; - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0xffff ); - DBGA ( R7.L , 0x007f ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 ); - -// saturate negative -// expected value is 0x8000000000 - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1.x = R4.L; - A0.x = R4.L; - A1 += R0.L * R1.H, A0 += R0.L * R1.H; - R6 = A1.w; - _DBG ASTAT; - R7.L = A1.x; - _DBG ASTAT; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0xff80 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 ); - -// saturate positive with "-=" -// expected value is 0x7fffffffff - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1.w = R2; - A1.x = R3.L; - A0.w = R2; - A0.x = R3.L; - A1 -= R0.H * R1.L, A0 -= R0.H * R1.L; - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0xffff ); - DBGA ( R7.L , 0x007f ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 ); - -// saturate negative with "-=" -// expected value is 0x8000000000 - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1.x = R4.L; - A0.x = R4.L; - A1 -= R0.L * R1.L, A0 -= R0.L * R1.L; - R6 = A1.w; - _DBG ASTAT; - R7.L = A1.x; - _DBG ASTAT; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0xff80 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 ); - -// 0x8000 * 0x8000 = 0xff80000001 with "-=" - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1 -= R0.H * R1.H, A0 -= R0.H * R1.H; - R6 = A1.w; - _DBG ASTAT; - R7.L = A1.x; - _DBG ASTAT; - - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8000 ); - DBGA ( R7.L , 0xffff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// 0x7fff * 0x7fff = 0x007ffe0002 with "=" - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1 += R0.L * R1.L, A0 += R0.L * R1.L; - A1 = R0.L * R1.L, A0 = R0.L * R1.L; - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x7ffe ); - DBGA ( R7.L , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// 0x7fff * 0x7fff = 0x007ffe0002 with "NOP" - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1 += R0.L * R1.L; - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x7ffe ); - DBGA ( R7.L , 0x0000 ); - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// 0x8000 * 0x8000 = 0x007fffffff with "NOP" - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1 += R0.H * R1.H; - _DBG A1; - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8000 ); - DBGA ( R7.L , 0x0000 ); - - R6 = A0.w; - _DBG ASTAT; - R7.L = A0.x; - _DBG ASTAT; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x0000 ); - R7 = ASTAT; _dbg astat; -//AV1 AV1S should be 0. - DBGA ( R7.H , 0x0000 ); - DBGA ( R7.L , 0x0000 ); - - _DBG ASTAT; - A1 = A0 = 0; - _DBG A1; - _DBG R0; _DBG R1; - A1 += R0.L * R1.L; // make sure overflow flag is not set to zero - _DBG A1; - _DBG ASTAT; - R7 = ASTAT; -//AV1S should be 0. - DBGA ( R7.H, 0x0000 ); - DBGA ( R7.L, 0x0000 ); - - pass - - .data -data0: - .dw 0x7fff - .dw 0x8000 - .dw 0x7fff - .dw 0x8000 - .dw 0x0000 - .dw 0xf000 - .dw 0x007f - .dw 0x0000 - .dw 0x0080 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m3.s b/sim/testsuite/sim/bfin/m3.s deleted file mode 100644 index 116263c..0000000 --- a/sim/testsuite/sim/bfin/m3.s +++ /dev/null @@ -1,138 +0,0 @@ -// MAC test program. -// Test basic edge values -// UNSIGNED FRACTIONAL mode U -// test ops: "+=" "-=" -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x80007fff -// load r1=0x80007fff -// load r2=0xf0000000 -// load r3=0x0000007f -// load r4=0x00000080 -// load r5=0xffffffff - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - R5 = [ P0 ++ ]; - - dbga(r0.h, 0x8000); - dbga(r0.l, 0x7fff); - dbga(r1.h, 0x8000); - dbga(r1.l, 0x7fff); - dbga(r2.h, 0xf000); - dbga(r2.l, 0); - -// 0x8000 * 0x7fff = 0x003fff8000 - A1 = A0 = 0; - A1 += R0.H * R1.L, A0 += R0.H * R1.L (FU); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x8000 ); - DBGA ( R6.H , 0x3fff ); - DBGA ( R7.L , 0x0000 ); - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0x8000 ); - DBGA ( R6.H , 0x3fff ); - DBGA ( R7.L , 0x0000 ); - -// 0x8000 * 0x8000 = 0x0040000000 - A1 = A0 = 0; - A1 += R0.H * R1.H, A0 += R0.H * R1.H (FU); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x4000 ); - DBGA ( R7.L , 0x0000 ); - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x4000 ); - DBGA ( R7.L , 0x0000 ); - -// 0xffff * 0xffff = 0x00fffe0001 - A1 = A0 = 0; - A1 += R5.H * R5.H, A0 += R5.H * R5.H (FU); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0001 ); - DBGA ( R6.H , 0xfffe ); - DBGA ( R7.L , 0x0000 ); - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0x0001 ); - DBGA ( R6.H , 0xfffe ); - DBGA ( R7.L , 0x0000 ); - -// saturate high by first loading large value into accums -// expected value is 0xffffffffff - A1 = A0 = 0; - A1.w = R5; - A1.x = R5.L; - A0.w = R5; - A0.x = R5.L; - A1 += R5.H * R5.H, A0 += R5.H * R5.H (FU); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0xffff ); - DBGA ( R7.L , 0xffff ); - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0xffff ); - DBGA ( R7.L , 0xffff ); - -// saturate low with "-=" -// expected value is 0x0000000000 - A1 = A0 = 0; - A1 -= R4.L * R4.L, A0 -= R4.L * R4.L (FU); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x0000 ); - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x0000 ); - -// saturate low with "-=" -// expected value is 0x0000000000 - A1 = A0 = 0; - A1 -= R1.H * R0.H, A0 -= R1.H * R0.H (FU); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x0000 ); - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x0000 ); - - pass - - .data -data0: - .dw 0x7fff - .dw 0x8000 - .dw 0x7fff - .dw 0x8000 - .dw 0x0000 - .dw 0xf000 - .dw 0x007f - .dw 0x0000 - .dw 0x0080 - .dw 0x0000 - .dw 0xffff - .dw 0xffff diff --git a/sim/testsuite/sim/bfin/m4.s b/sim/testsuite/sim/bfin/m4.s deleted file mode 100644 index 8977063..0000000 --- a/sim/testsuite/sim/bfin/m4.s +++ /dev/null @@ -1,124 +0,0 @@ -// MAC test program. -// Test basic edge values -// SIGNED INTEGER mode -// test ops: "+=" "-=" "=" "NOP" -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x80007fff -// load r1=0x80007fff -// load r2=0xf0000000 -// load r3=0x0000007f -// load r4=0x00000080 - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// 0x7fff * 0x7fff = 0x003fff0001 - A1 = A0 = 0; - A1 += R0.L * R1.L, A0 += R0.L * R1.L (IS); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0001 ); - DBGA ( R6.H , 0x3fff ); - DBGA ( R7.L , 0x0000 ); - -// 0x8000 * 0x7fff = 0xffc0008000 - A1 = A0 = 0; - A1 += R0.H * R1.L, A0 += R0.H * R1.L (IS); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x8000 ); - DBGA ( R6.H , 0xc000 ); - DBGA ( R7.L , 0xffff ); - -// 0x8000 * 0x8000 = 0x0040000000 - A1 = A0 = 0; - A1 += R0.H * R1.H, A0 += R0.H * R1.H (IS); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x4000 ); - DBGA ( R7.L , 0x0000 ); - -// saturate positive by first loading large value into accums -// expected value is 0x7fffffffff - A1 = A0 = 0; - A1.w = R2; - A1.x = R3.L; - A0.w = R2; - A0.x = R3.L; - A1 += R0.L * R1.L, A0 += R0.L * R1.L (IS); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0xffff ); - DBGA ( R7.L , 0x007f ); - -// saturate negative -// expected value is 0x8000000000 - A1 = A0 = 0; - A1.x = R4.L; - A0.x = R4.L; - A1 += R0.L * R1.H, A0 += R0.L * R1.H (IS); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0xff80 ); - -// saturate positive with "-=" -// expected value is 0x7fffffffff - A1 = A0 = 0; - A1.w = R2; - A1.x = R3.L; - A0.w = R2; - A0.x = R3.L; - A1 -= R0.H * R1.L, A0 -= R0.H * R1.L (IS); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0xffff ); - DBGA ( R7.L , 0x007f ); - -// saturate negative with "-=" -// expected value is 0x8000000000 - A1 = A0 = 0; - A1.x = R4.L; - A0.x = R4.L; - A1 -= R0.L * R1.L, A0 -= R0.L * R1.L (IS); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0xff80 ); - -// 0x8000 * 0x8000 = 0xffc0000000 with "-=" - A1 = A0 = 0; - A1 -= R0.H * R1.H, A0 -= R0.H * R1.H (IS); - R6 = A1.w; - R7.L = A1.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0xc000 ); - DBGA ( R7.L , 0xffff ); - - pass - - .data 0x1000; -data0: - .dw 0x7fff - .dw 0x8000 - .dw 0x7fff - .dw 0x8000 - .dw 0x0000 - .dw 0xf000 - .dw 0x007f - .dw 0x0000 - .dw 0x0080 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m5.s b/sim/testsuite/sim/bfin/m5.s deleted file mode 100644 index e39a2e0..0000000 --- a/sim/testsuite/sim/bfin/m5.s +++ /dev/null @@ -1,153 +0,0 @@ -// Test result extraction of mac instructions. -// Test basic edge values -// SIGNED FRACTIONAL mode into SINGLE destination register -// test ops: "+=" -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x80007fff -// load r1=0x80007fff -// load r2=0xf0000000 -// load r3=0x0000007f -// load r4=0x00000080 - loadsym p0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// simple extraction with no saturation -// 0x7fff * 0x7fff = 0x007ffe0002 -> 0x7ffe - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - R5.H = (A1 += R0.L * R1.L), R5.L = (A0 += R0.L * R1.L); - DBGA ( R5.L , 0x7ffe ); - DBGA ( R5.H , 0x7ffe ); - _DBG ASTAT; - R7 = ASTAT; - DBGA (R7.H, 0x0); - DBGA (R7.L, 0x0); - -// positive saturation at 32 bits -// 0x0 * 0x0 + 0x7ff0000000 -> 0x7fff - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1.w = R2; - A1.x = R3.L; - A0.x = R3.L; - A0.w = R2; - R5.H = (A1 += R0.L * R2.L), R5.L = (A0 += R0.L * R2.L); - _DBG A1; - _DBG A0; - DBGA ( R5.L , 0x7fff ); - DBGA ( R5.H , 0x7fff ); - _DBG ASTAT; - R7 = ASTAT; - _DBG R7; - DBGA (R7.H, 0x300); - DBGA (R7.L, 0x8); - -// positive saturation at 32 bits -// 0x7fff * 0x7fff + 0x7ff0000000 -> 0x7fff - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1.w = R2; - A1.x = R3.L; - A0.w = R2; - A0.x = R3.L; - R5.H = (A1 += R0.L * R1.L), R5.L = (A0 += R0.L * R1.L); - DBGA ( R5.L , 0x7fff ); - DBGA ( R5.H , 0x7fff ); - _DBG ASTAT; - R7 = ASTAT; - DBGA (R7.H, 0x30f); - DBGA (R7.L, 0x8); - -// negative saturation at 32 bits -// 0x0 * 0x0 + 0x80f0000000 -> 0x8000 - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1.w = R2; - A1.x = R4.L; - A0.w = R2; - A0.x = R4.L; - R5.H = (A1 += R0.L * R2.L), R5.L = (A0 += R0.L * R2.L); - DBGA ( R5.L , 0x8000 ); - DBGA ( R5.H , 0x8000 ); - _DBG A1; - _DBG A0; - _DBG ASTAT; - R7=ASTAT; - _DBG R7; - DBGA (R7.H, 0x300); - DBGA (R7.L, 0x0008); - -// negative saturation at 32 bits -// 0x7fff * 0x8000 + 0x80f0000000 -> 0x8000 - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A1.w = R2; - A1.x = R4.L; - A0.w = R2; - A0.x = R4.L; - R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L); - DBGA ( R5.L , 0x8000 ); - DBGA ( R5.H , 0x8000 ); - R7=ASTAT; - _DBG ASTAT; - DBGA (R7.H, 0x300); - DBGA (R7.L, 0x0008); - -// negative saturation at 32 bits on MAC only -// 0x7fff * 0x8000 + 0x80f0000000 -> 0x8000 - R7 = 0; - ASTAT = R7; - A1 = A0 = 0; - A0.w = R2; - A0.x = R4.L; - _DBG ASTAT; - R5.H = A1, R5.L = (A0 += R0.H * R1.L); - _DBG A0; - DBGA ( R5.L , 0x8000 ); - DBGA ( R5.H , 0x0000 ); - R7=ASTAT; - _DBG ASTAT; - DBGA (R7.H, 0x300); - DBGA (R7.L, 0x0009); - -// 0x0100 * 0x0100 = 0x00020000 -> 0x0002 - R7 = 0; - ASTAT = R7; - R0.L = 0x0100; - R1.L = 0x0100; - A1 = A0 = 0; - R5.H = (A1 = R0.L * R1.L), R5.L = (A0 = R0.L * R1.L) (T); - DBGA ( R5.L , 0x0002 ); - DBGA ( R5.H , 0x0002 ); - R7 = ASTAT; - DBGA (R7.H, 0x000); - DBGA (R7.L, 0x000); - - pass - - .data -data0: - .dw 0x7fff - .dw 0x8000 - .dw 0x7fff - .dw 0x8000 - .dw 0x0000 - .dw 0xf000 - .dw 0x007f - .dw 0x0000 - .dw 0x0080 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m6.s b/sim/testsuite/sim/bfin/m6.s deleted file mode 100644 index 738d623..0000000 --- a/sim/testsuite/sim/bfin/m6.s +++ /dev/null @@ -1,57 +0,0 @@ -// Test result extraction of mac instructions. -// Test basic edge values -// SIGNED INTEGER mode into SINGLE destination register -// test ops: "+=" -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x80000001 -// load r1=0x80007fff -// load r2=0xf0000000 -// load r3=0x0000007f -// load r4=0x00000080 - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// integer extraction with no saturation -// 0x1 * 0x1 = 0x0000000001 -> 0x1 - A1 = A0 = 0; - R5.H = (A1 += R0.L * R0.L), R5.L = (A0 += R0.L * R0.L) (IS); - DBGA ( R5.L , 0x1 ); - DBGA ( R5.H , 0x1 ); - -// integer extraction with positive saturation -// 0x7fff * 0x7f -> 0x7fff - A1 = A0 = 0; - R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IS); - DBGA ( R5.L , 0x7fff ); - DBGA ( R5.H , 0x7fff ); - -// integer extraction with negative saturation -// 0x8000 * 0x7f -> 0x8000 - A1 = A0 = 0; - R5.H = (A1 += R1.H * R3.L), R5.L = (A0 += R1.H * R3.L) (IS); - DBGA ( R5.L , 0x8000 ); - DBGA ( R5.H , 0x8000 ); - - pass - - .data; -data0: - .dw 0x0001 - .dw 0x8000 - .dw 0x7fff - .dw 0x8000 - .dw 0x0000 - .dw 0xf000 - .dw 0x007f - .dw 0x0000 - .dw 0x0080 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m7.s b/sim/testsuite/sim/bfin/m7.s deleted file mode 100644 index 07e664e..0000000 --- a/sim/testsuite/sim/bfin/m7.s +++ /dev/null @@ -1,66 +0,0 @@ -// Test result extraction of mac instructions. -// Test basic edge values -// UNSIGNED FRACTIONAL mode into SINGLE destination register -// test ops: "+=" -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x80000001 -// load r1=0x80007fff -// load r2=0xf000ffff -// load r3=0x0000007f -// load r4=0x00000080 - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// extraction with no saturation (truncate) -// 0x8000 * 0x7fff = 0x003fff8000 -> 0x3fff - A1 = A0 = 0; - R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L) (TFU); - DBGA ( R5.L , 0x3fff ); - DBGA ( R5.H , 0x3fff ); - -// extraction with no saturation (round) -// 0x8000 * 0x7fff = 0x003fff8000 -> 0x4000 - A1 = A0 = 0; - R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L) (FU); - DBGA ( R5.L , 0x4000 ); - DBGA ( R5.H , 0x4000 ); - -// extraction with no saturation -// 0xffff * 0xffff = 0x00fffe0001 -> 0xfffe - A1 = A0 = 0; - R5.H = (A1 += R2.L * R2.L), R5.L = (A0 += R2.L * R2.L) (FU); - DBGA ( R5.L , 0xfffe ); - DBGA ( R5.H , 0xfffe ); - -// extraction with saturation -//0x7ffffe0001 -> 0xffff - A1 = A0 = 0; - A1.x = R3.L; - A0.x = R3.L; - R5.H = (A1 += R2.L * R2.L), R5.L = (A0 += R2.L * R2.L) (FU); - DBGA ( R5.L , 0xffff ); - DBGA ( R5.H , 0xffff ); - - pass - - .data -data0: - .dw 0x0001 - .dw 0x8000 - .dw 0x7fff - .dw 0x8000 - .dw 0xffff - .dw 0xf000 - .dw 0x007f - .dw 0x0000 - .dw 0x0080 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m8.s b/sim/testsuite/sim/bfin/m8.s deleted file mode 100644 index fe8507f..0000000 --- a/sim/testsuite/sim/bfin/m8.s +++ /dev/null @@ -1,54 +0,0 @@ -// MAC test program. -// Test result extraction of mac instructions. -// Test basic edge values -// UNSIGNED INTEGER mode into SINGLE destination register -// test ops: "+=" -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x80000002 -// load r1=0x80007fff -// load r2=0xf0000000 -// load r3=0x0000007f -// load r4=0x00000080 -// load r5=0xffffffff - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - R5 = [ P0 ++ ]; - -// 0x0002 * 0x0002 = 0x0000000004 -> 0x0004 - A1 = A0 = 0; - R5.H = (A1 += R0.L * R0.L), R5.L = (A0 += R0.L * R0.L) (IU); - DBGA ( R5.L , 0x4 ); - DBGA ( R5.H , 0x4 ); - -// 0x7fff * 0x007f = 0x00003f7f81 -> 0xffff - A1 = A0 = 0; - R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IU); - R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IU); - DBGA ( R5.L , 0xffff ); - DBGA ( R5.H , 0xffff ); - - pass - - .data; -data0: - .dw 0x0002 - .dw 0x8000 - .dw 0x7fff - .dw 0x8000 - .dw 0x0000 - .dw 0xf000 - .dw 0x007f - .dw 0x0000 - .dw 0x0080 - .dw 0x0000 - .dw 0xffff - .dw 0xffff diff --git a/sim/testsuite/sim/bfin/m9.s b/sim/testsuite/sim/bfin/m9.s deleted file mode 100644 index 79cab4c..0000000 --- a/sim/testsuite/sim/bfin/m9.s +++ /dev/null @@ -1,91 +0,0 @@ -// Test extraction from accumulators: -// ROUND/TRUNCATE in SIGNED FRACTIONAL mode -// test ops: "+=" -# mach: bfin - -.include "testutils.inc" - start - - -// load r0=0x7ffef000 -// load r1=0x7ffff000 -// load r2=0x00008000 -// load r3=0x00018000 -// load r4=0x0000007f - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - -// round -// 0x007ffef00 -> 0x7fff - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R5.H = A1, R5.L = A0; - DBGA ( R5.L , 0x7fff ); - DBGA ( R5.H , 0x7fff ); - -// round with ovflw -// 0x007ffff00 -> 0x7fff - A1 = A0 = 0; - A1.w = R1; - A0.w = R1; - R5.H = A1, R5.L = A0; - DBGA ( R5.L , 0x7fff ); - DBGA ( R5.H , 0x7fff ); - -// trunc -// 0x007ffef00 -> 0x7ffe - A1 = A0 = 0; - A1.w = R0; - A0.w = R0; - R5.H = A1, R5.L = A0 (T); - DBGA ( R5.L , 0x7ffe ); - DBGA ( R5.H , 0x7ffe ); - -// round with ovflw -// 0x7f7ffff00 -> 0x7fff - A1 = A0 = 0; - A1.w = R1; - A1.x = R4.L; - A0.w = R1; - A0.x = R4.L; - R5.H = A1, R5.L = A0; - DBGA ( R5.L , 0x7fff ); - DBGA ( R5.H , 0x7fff ); - -// round, nearest even is zero -// 0x0000008000 -> 0x0000 - A1 = A0 = 0; - A1.w = R2; - A0.w = R2; - R5.H = A1, R5.L = A0; - DBGA ( R5.L , 0x0 ); - DBGA ( R5.H , 0x0 ); - -// round, nearest even is 2 -// 0x00000018000 -> 0x0002 - A1 = A0 = 0; - A1.w = R3; - A0.w = R3; - R5.H = A1, R5.L = A0; - DBGA ( R5.L , 0x2 ); - DBGA ( R5.H , 0x2 ); - - pass - - .data -data0: - .dw 0xf000 - .dw 0x7ffe - .dw 0xf000 - .dw 0x7ffe - .dw 0x8000 - .dw 0x0000 - .dw 0x8000 - .dw 0x0001 - .dw 0x007f - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/mac2halfreg.S b/sim/testsuite/sim/bfin/mac2halfreg.S deleted file mode 100644 index 0a73dd3..0000000 --- a/sim/testsuite/sim/bfin/mac2halfreg.S +++ /dev/null @@ -1,27 +0,0 @@ -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - - r3.h=0x8000; - r2.h=0x8000; - r7=0; - r6.l=0x7f; - a0.x=r6.l; - r6.h=0x7fff; - r6.l=0xffff; - a0.w=r6; - _dbg a0; - r3.l=(a0+=r3.h*r2.h); - r7=ASTAT; - _dbg A0; - _dbg r3; - _dbg ASTAT; -//AV0 does not overflow - checkreg r7, (_VS|_V|_V_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/math.s b/sim/testsuite/sim/bfin/math.s deleted file mode 100644 index bd88f70..0000000 --- a/sim/testsuite/sim/bfin/math.s +++ /dev/null @@ -1,66 +0,0 @@ -# Blackfin testcase for ashift -# mach: bfin - - .include "testutils.inc" - - start - - R0 = 5; - R0 += -1; - R1 = 4; - CC = R0 == R1; - if CC jump 1f; - fail -1: - - imm32 r2, 0xff901234 - r4=8; - i2=r2; - m2 = 4; - a0 = 0; - r1.l = (a0 += r4.l *r4.l) (IS) || I2 += m2 || nop; - r0 = i2; - imm32 r1, 0xff901238; - CC = r1 == r0; - if CC jump 2f; - fail -2: - - A0 = 0; - A1 = 0; - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - R4 = 0; - R5 = 0; - R2.H = 0xf12e; - R2.L = 0xbeaa; - R3.L = 0x00ff; - A1.w = R2; - A1.x = R3; - R0.H = 0xd136; - R0.L = 0x459d; - R1.H = 0xabd6; - R1.L = 0x9ec7; - - R5 = A1 , A0 = R1.L * R0.L (FU); - - R0 = -1 (X); - CC = r5 == r0; - if CC jump 3f; - fail -3: - - R0.L = 0x7bb8; - R0.H = 0x8d5e; - R4.L = 0x7e1c; - R4.H = 0x9e22; - R6.H = R4.H * R0.L (M), R6.L = R4.L * R0.H (ISS2); - - imm32 r0, 0x80008000 - CC = r6 == r0; - if CC jump 4f; - fail -4: - pass diff --git a/sim/testsuite/sim/bfin/max_min_flags.s b/sim/testsuite/sim/bfin/max_min_flags.s deleted file mode 100644 index a4ad33b..0000000 --- a/sim/testsuite/sim/bfin/max_min_flags.s +++ /dev/null @@ -1,275 +0,0 @@ -// Check Flag Settings for MAX/MIN -# mach: bfin - -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - - r0=1; - r1= -1; - r2=min(r1,r0); - _DBG ASTAT; -//r3=ASTAT; -//dbga (r3.l, 0x2); -//dbga (r3.h, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 1); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - dbga (r2.l, 0xffff); - dbga (r2.h, 0xffff); - - r2=min(r0,r1); - _DBG ASTAT; -//r3=ASTAT; -//dbga (r3.l, 0x2); -//dbga (r3.h, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 1); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - dbga (r2.l, 0xffff); - dbga (r2.h, 0xffff); - - r2=max(r1,r0); - _DBG ASTAT; -//r3=ASTAT; -//dbga (r3.l, 0x0); -//dbga (r3.h, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - dbga (r2.l, 0x1); - dbga (r2.h, 0x0); - - r2=max(r0,r1); - _DBG ASTAT; -//r3=ASTAT; -//dbga (r3.l, 0x0); -//dbga (r3.h, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - dbga (r2.l, 0x1); - dbga (r2.h, 0x0); - - r0.h=1; - r2=min(r1,r0) (v); - _DBG ASTAT; -//r3=ASTAT; -//dbga (r3.l, 0x2); -//dbga (r3.h, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 1); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - dbga (r2.l, 0xffff); - dbga (r2.h, 0xffff); - - r2=min(r0,r1) (v); - _DBG ASTAT; -//r3=ASTAT; -//dbga (r3.l, 0x2); -//dbga (r3.h, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 1); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - dbga (r2.l, 0xffff); - dbga (r2.h, 0xffff); - - r2=max(r1,r0) (v); - _DBG ASTAT; -//r3=ASTAT; -//dbga (r3.l, 0x0); -//dbga (r3.h, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - dbga (r2.l, 0x1); - dbga (r2.h, 0x1); - - r2=max(r0,r1) (v); - _DBG ASTAT; -//r3=ASTAT; -//dbga (r3.l, 0x0); -//dbga (r3.h, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 0); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - dbga (r2.l, 0x1); - dbga (r2.h, 0x1); - - r0=0; - r2=max(r1,r0); - _DBG ASTAT; -//r3=ASTAT; -//dbga (r3.l, 0x1); -//dbga (r3.h, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 1); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - dbga (r2.l, 0x0); - dbga (r2.h, 0x0); - - r0.h=1; - r2=max(r1,r0) (v); - _DBG ASTAT; -//r3=ASTAT; -//dbga (r3.l, 0x1); -//dbga (r3.h, 0x0); - cc = az; - r7 = cc; - dbga( r7.l, 1); - cc = an; - r7 = cc; - dbga( r7.l, 0); - cc = av0; - r7 = cc; - dbga( r7.l, 0); - cc = av0s; - r7 = cc; - dbga( r7.l, 0); - cc = av1; - r7 = cc; - dbga( r7.l, 0); - cc = av1s; - r7 = cc; - dbga( r7.l, 0); - dbga (r2.l, 0x0); - dbga (r2.h, 0x1); - - pass diff --git a/sim/testsuite/sim/bfin/mc_s2.s b/sim/testsuite/sim/bfin/mc_s2.s deleted file mode 100644 index 024ee92..0000000 --- a/sim/testsuite/sim/bfin/mc_s2.s +++ /dev/null @@ -1,78 +0,0 @@ -/* SHIFT test program. - * Test r0, r1, A0 <<= BITMUX; - */ -# mach: bfin - -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - -// load r0=0x90000001 -// load r1=0x90000002 -// load r2=0x00000000 -// load r3=0x00000000 -// load r4=0x20000002 -// load r5=0x00000000 - loadsym P1, data0; - -// insert two bits, both equal to 1 -// A0: 00 0000 0000 -> 00 0000 0003 -// r0: 9000 0001 -> 2000 0002 -// r1: 9000 0002 -> 2000 0004 - R0 = [ P1 + 0 ]; - R1 = [ P1 + 4 ]; - A0.w = R2; - A0.x = R3.L; - BITMUX( R0 , R1, A0) (ASL); - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0x0003 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x0000 ); - DBGA ( R0.L , 0x0002 ); - DBGA ( R0.H , 0x2000 ); - DBGA ( R1.L , 0x0004 ); - DBGA ( R1.H , 0x2000 ); - -// insert two bits, one equal to 1, other to 0 -// A0: 00 0000 0000 -> 00 0000 0001 -// r0: 9000 0001 -> 2000 0002 -// r4: 2000 0002 -> 4000 0004 - R0 = [ P1 + 0 ]; - R4 = [ P1 + 16 ]; - A0.w = R2; - A0.x = R3.L; - BITMUX( R0 , R4, A0) (ASL); - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0x0001 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x0000 ); - DBGA ( R0.L , 0x0002 ); - DBGA ( R0.H , 0x2000 ); - DBGA ( R4.L , 0x0004 ); - DBGA ( R4.H , 0x4000 ); - - pass - - .data -data0: - .dw 0x0001 - .dw 0x9000 - - .dw 0x0002 - .dw 0x9000 - - .dw 0x0000 - .dw 0x0000 - - .dw 0x0000 - .dw 0x0000 - - .dw 0x0002 - .dw 0x2000 - - .dw 0x0000 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/mdma-32bit-1d-neg-count.c b/sim/testsuite/sim/bfin/mdma-32bit-1d-neg-count.c deleted file mode 100644 index e380254..0000000 --- a/sim/testsuite/sim/bfin/mdma-32bit-1d-neg-count.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Basic MDMA device tests. -# mach: bfin -# cc: -mcpu=bf537 -nostdlib -lc -# sim: --env operating --model bf537 -*/ - -#include "test.h" - -static volatile struct bfin_dma *s = (void *)MDMA_S1_NEXT_DESC_PTR; -static volatile struct bfin_dma *d = (void *)MDMA_D1_NEXT_DESC_PTR; - -#include "mdma-skel.h" - -void mdma_memcpy (bu32 dst, bu32 src, bu32 size) -{ - /* Negative transfers start at end of buffer. */ - _mdma_memcpy (dst + size - 4, src + size - 4, size, -4); -} diff --git a/sim/testsuite/sim/bfin/mdma-32bit-1d.c b/sim/testsuite/sim/bfin/mdma-32bit-1d.c deleted file mode 100644 index acb891e..0000000 --- a/sim/testsuite/sim/bfin/mdma-32bit-1d.c +++ /dev/null @@ -1,17 +0,0 @@ -/* Basic MDMA device tests. -# mach: bfin -# cc: -mcpu=bf537 -nostdlib -lc -# sim: --env operating --model bf537 -*/ - -#include "test.h" - -static volatile struct bfin_dma *s = (void *)MDMA_S0_NEXT_DESC_PTR; -static volatile struct bfin_dma *d = (void *)MDMA_D0_NEXT_DESC_PTR; - -#include "mdma-skel.h" - -void mdma_memcpy (bu32 dst, bu32 src, bu32 size) -{ - _mdma_memcpy (dst, src, size, 4); -} diff --git a/sim/testsuite/sim/bfin/mdma-8bit-1d-neg-count.c b/sim/testsuite/sim/bfin/mdma-8bit-1d-neg-count.c deleted file mode 100644 index 26ba577..0000000 --- a/sim/testsuite/sim/bfin/mdma-8bit-1d-neg-count.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Basic MDMA device tests. -# mach: bfin -# cc: -mcpu=bf537 -nostdlib -lc -# sim: --env operating --model bf537 -*/ - -#include "test.h" - -static volatile struct bfin_dma *s = (void *)MDMA_S1_NEXT_DESC_PTR; -static volatile struct bfin_dma *d = (void *)MDMA_D1_NEXT_DESC_PTR; - -#include "mdma-skel.h" - -void mdma_memcpy (bu32 dst, bu32 src, bu32 size) -{ - /* Negative transfers start at end of buffer. */ - _mdma_memcpy (dst + size - 1, src + size - 1, size, -1); -} diff --git a/sim/testsuite/sim/bfin/mdma-8bit-1d.c b/sim/testsuite/sim/bfin/mdma-8bit-1d.c deleted file mode 100644 index 8384093..0000000 --- a/sim/testsuite/sim/bfin/mdma-8bit-1d.c +++ /dev/null @@ -1,17 +0,0 @@ -/* Basic MDMA device tests. -# mach: bfin -# cc: -mcpu=bf537 -nostdlib -lc -# sim: --env operating --model bf537 -*/ - -#include "test.h" - -static volatile struct bfin_dma *s = (void *)MDMA_S0_NEXT_DESC_PTR; -static volatile struct bfin_dma *d = (void *)MDMA_D0_NEXT_DESC_PTR; - -#include "mdma-skel.h" - -void mdma_memcpy (bu32 dst, bu32 src, bu32 size) -{ - _mdma_memcpy (dst, src, size, 1); -} diff --git a/sim/testsuite/sim/bfin/mdma-skel.h b/sim/testsuite/sim/bfin/mdma-skel.h deleted file mode 100644 index 920eff2..0000000 --- a/sim/testsuite/sim/bfin/mdma-skel.h +++ /dev/null @@ -1,80 +0,0 @@ -#include -#include - -void _mdma_memcpy (bu32 dst, bu32 src, bu32 size, bs16 mod) -{ - bu32 count = size >> (abs (mod) / 2); - bu16 wdsize; - switch (abs (mod)) - { - case 4: wdsize = WDSIZE_32; break; - case 2: wdsize = WDSIZE_16; break; - default: wdsize = WDSIZE_8; break; - } - - s->config = d->config = 0; - - d->irq_status = DMA_DONE | DMA_ERR; - - /* Destination */ - d->start_addr = dst; - d->x_count = count; - d->x_modify = mod; - d->irq_status = DMA_DONE | DMA_ERR; - - /* Source */ - s->start_addr = src; - s->x_count = count; - s->x_modify = mod; - s->irq_status = DMA_DONE | DMA_ERR; - - /* Enable */ - s->config = DMAEN | wdsize; - d->config = WNR | DI_EN | DMAEN | wdsize; - - while (!(d->irq_status & DMA_DONE)) - continue; -} - -void mdma_memcpy (bu32 dst, bu32 src, bu32 size); - -#ifndef MAX_LEN -#define MAX_LEN 0x40000 -#endif -bu32 _data[(MAX_LEN / 4) * 2 + 3]; -char *data = (char *)(_data + 1); - -int _start (void) -{ - char *src, *dst; - bu32 len, canary, *canaries[3]; - - canary = 0x12345678; - - len = 4; - while (len < MAX_LEN) - { - src = data; - dst = data + len + 4; - /* Set up the canaries. */ - canaries[0] = (void *)&src[-4]; - canaries[1] = (void *)&dst[-4]; - canaries[2] = (void *)&dst[len]; - *canaries[0] = *canaries[1] = *canaries[2] = canary; - - memset (src, 0xad, len); - memset (dst, 0x00, len); - - mdma_memcpy ((bu32)dst, (bu32)src, len); - if (memcmp (src, dst, len)) - DBG_FAIL; - - if (*canaries[0] != canary || - *canaries[1] != canary || - *canaries[2] != canary) - DBG_FAIL; - - len <<= 4; - } - DBG_PASS; -} diff --git a/sim/testsuite/sim/bfin/mem3.s b/sim/testsuite/sim/bfin/mem3.s deleted file mode 100644 index da070e0..0000000 --- a/sim/testsuite/sim/bfin/mem3.s +++ /dev/null @@ -1,42 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - R0.H = 0x1234; - R0.L = 0x5678; - loadsym P0, data0; - - [ P0 ] = R0; - P1 = [ P0 ]; - _DBG P1; - R1 = [ P0 ]; - _DBG R1; - CC = R0 == R1; - IF !CC JUMP abrt; - - W [ P0 ] = R0; - R1 = W [ P0 ] (Z); - R2 = R0; - R2 <<= 16; - R2 >>= 16; - _DBG R1; - CC = R2 == R1; - IF !CC JUMP abrt; - - B [ P0 ] = R0; - R1 = B [ P0 ] (Z); - R2 = R0; - R2 <<= 24; - R2 >>= 24; - _DBG R1; - CC = R2 == R1; - IF !CC JUMP abrt; - pass -abrt: - fail; - - .data -data0: - .dd 0xDEADBEAF; diff --git a/sim/testsuite/sim/bfin/mmr-exception.s b/sim/testsuite/sim/bfin/mmr-exception.s deleted file mode 100644 index 5e9a268..0000000 --- a/sim/testsuite/sim/bfin/mmr-exception.s +++ /dev/null @@ -1,43 +0,0 @@ -# Blackfin testcase for MMR exceptions in a lower EVT -# mach: bfin -# sim: --environment operating - - .include "testutils.inc" - - start - - imm32 P0, 0xFFE02000 - loadsym R1, _evx - [P0 + (4 * 3)] = R1; - loadsym R1, _ivg9 - [P0 + (4 * 9)] = R1; - CSYNC; - - RETI = R1; - RAISE 9; - R0 = -1; - STI R0; - RTI; - dbg_fail - -_ivg9: - # Invalid MMR - imm32 P0, 0xFFEE0000 -1: [P0] = R0; -9: dbg_fail - -_evx: - # Make sure SEQSTAT is set to correct value - R0 = SEQSTAT; - R0 = R0.B; - R1 = 0x2e (x); - CC = R0 == R1; - IF !CC JUMP 9b; - - # Make sure RETX is set to correct address - loadsym R0, 1b; - R1 = RETX; - CC = R0 == R1; - IF !CC JUMP 9b; - - dbg_pass diff --git a/sim/testsuite/sim/bfin/move.s b/sim/testsuite/sim/bfin/move.s deleted file mode 100644 index b8f41c8..0000000 --- a/sim/testsuite/sim/bfin/move.s +++ /dev/null @@ -1,36 +0,0 @@ -# Blackfin testcase for register move instructions -# mach: bfin - - - .include "testutils.inc" - - start - - .macro move reg0:req, reg1:req, clobber:req - imm32 \reg0, 0x5555aaaa - imm32 \reg1, 0x12345678 - imm32 \clobber, 0x12345678 - \reg0 = \reg1; - CC = \reg0 == \clobber; - if CC jump 1f; - fail -1: - .endm - - move R0, R1, R2 - move R0, R2, R3 - move R0, R2, R4 - move R0, R3, R5 - move R0, R4, R6 - move R0, R5, R7 - move R0, R6, R1 - move R0, R7, R2 - move R7, R0, R1 - move R7, R1, R2 - move R7, R2, R3 - move R7, R3, R4 - move R7, R4, R5 - move R7, R5, R6 - move R7, R6, R0 - - pass diff --git a/sim/testsuite/sim/bfin/msa_acp_5.10.S b/sim/testsuite/sim/bfin/msa_acp_5.10.S deleted file mode 100644 index 75e50e3..0000000 --- a/sim/testsuite/sim/bfin/msa_acp_5.10.S +++ /dev/null @@ -1,40 +0,0 @@ -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - init_r_regs 0 - astat = r0; - - r1.l = 0x0; - r1.h = 0x8000; - A0.w=r1; - _dbg a1; - a0 = a0 << 8; - _dbg a0; - _dbg astat; - - - A0 = - A0; - _dbg astat; - _dbg a0; - r7 = astat; - checkreg r7, (_AV0|_AV0S); - - r1.l = 0x0; - r1.h = 0x8000; - A1.w=r1; - _dbg a0; - a1 = a1 << 8; - _dbg a1; - _dbg astat; - r7 = astat; - checkreg r7, (_AV0|_AV0S|_AN); - - A1 = - A1; - r7 = astat; - checkreg r7, (_AV1|_AV1S|_AV0|_AV0S); - _dbg astat; - _dbg a1; - pass; diff --git a/sim/testsuite/sim/bfin/msa_acp_5.12_1.S b/sim/testsuite/sim/bfin/msa_acp_5.12_1.S deleted file mode 100644 index d65496d..0000000 --- a/sim/testsuite/sim/bfin/msa_acp_5.12_1.S +++ /dev/null @@ -1,71 +0,0 @@ -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - - init_r_regs 0; - ASTAT = r0; - - r0 = -1; - A0 = r0; - _dbg astat; - r0 +=1; - _dbg astat; - A0 = A0 (S); - r7 = astat; - checkreg r7, (_AC0|_AC0_COPY|_AN) - _dbg a0; - _dbg astat; - A0 = 0; - A0 = A0 (S); - r7 = astat; - checkreg r7, (_AC0|_AC0_COPY|_AZ) - _dbg a0; - _dbg astat; - - r0 = -1; - A1 = r0; - _dbg astat; - r0 +=1; - r7 = astat; - checkreg r7, (_AC0|_AC0_COPY|_AZ); - _dbg astat; - A1 = A1 (S); - r7 = astat; - _dbg astat; - checkreg r7, (_AC0|_AC0_COPY|_AN) - _dbg a1; - _dbg astat; - A1 = 0; - A1 = A1 (S); - r7 = astat; - checkreg r7, (_AC0|_AC0_COPY|_AZ) - _dbg a1; - _dbg astat; - - r1.l = 0x0; - r1.h = 0x8000; - a1 = r1; - a1 = a1 << 8; - _dbg a1; - r7 = astat; - checkreg r7, (_AC0|_AC0_COPY|_AN) - a1 = a1(s); - _dbg astat; - _dbg a1; - r7 = astat; - checkreg r7, (_AV1S|_AV1|_AC0|_AC0_COPY|_AN) - - r1.l = 0x0; - r1.h = 0x8000; - a0 = r1; - a0 = a0 << 8; - _dbg a0; - a0 = a0(s); - _dbg astat; - _dbg a0; - r7 = astat; - checkreg r7, (_AV1S|_AV1|_AV0S|_AV0|_AC0|_AC0_COPY|_AN) - pass diff --git a/sim/testsuite/sim/bfin/msa_acp_5.12_2.S b/sim/testsuite/sim/bfin/msa_acp_5.12_2.S deleted file mode 100644 index e965ad1..0000000 --- a/sim/testsuite/sim/bfin/msa_acp_5.12_2.S +++ /dev/null @@ -1,58 +0,0 @@ -# mach: bfin - -#include "test.h" -.include "testutils.inc" - start - - r0 = 0; - ASTAT = R0; - - r0 = -1; - A0 = r0; - A1 = 0; - _dbg astat; - r0 +=1; - _dbg astat; - A1 = A1(S), A0 = A0 (S); - r7 = astat; - checkreg r7, (_AC0|_AC0_COPY|_AN|_AZ); - _dbg a0; - _dbg astat; - - r0.l = 0x0; - r0.h = 0x8000; - r1 = 1; - a0 = r0; - a0 = a0 << 8; - a1 = r1; - r7 = astat; - checkreg r7, (_AC0|_AC0_COPY|_AN); - dbga(r7.l,0x1006); - dbga(r7.h,0); - - A1 = A1(S), A0 = A0(S); - _dbg a0; - _dbg a1; - _dbg astat; - r7 = astat; - checkreg r7, (_AV0S|_AV0|_AC0|_AC0_COPY|_AN); - - r0.l = 0x0; - r0.h = 0x8000; - r1 = 0; - a1 = r0; - a1 = a1 << 8; - a0 = r1; - r7 = astat; - - A1 = A1(S), A0 = A0(S); - _dbg a0; - _dbg a1; - _dbg astat; - r7 = astat; - checkreg r7, (_AV1S|_AV1|_AV0S|_AC0|_AC0_COPY|_AN|_AZ); - dbga(r7.l,0x1007); - - dbga(r7.h,0xe); - - pass; diff --git a/sim/testsuite/sim/bfin/msa_acp_5_10.s b/sim/testsuite/sim/bfin/msa_acp_5_10.s deleted file mode 100644 index eae4277..0000000 --- a/sim/testsuite/sim/bfin/msa_acp_5_10.s +++ /dev/null @@ -1,69 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - r1.l = 0x0; - r1.h = 0x8000; - A0.w=r1; - _dbg a1; - a0 = a0 << 8; - _dbg a0; - _dbg astat; - - A0 = - A0; - _dbg astat; - _dbg a0; - r7 = astat; - - cc = az; - r7 = cc; - dbga(r7.l, 0); - cc = an; - r7 = cc; - dbga(r7.l, 0); - cc = av0; - r7 = cc; - dbga(r7.l, 1); - cc = av0s; - r7 = cc; - dbga(r7.l, 1); - cc = av1; - r7 = cc; - dbga(r7.l, 0); - cc = av1s; - r7 = cc; - dbga(r7.l, 0); - - r1.l = 0x0; - r1.h = 0x8000; - A1.w=r1; - _dbg a0; - a1 = a1 << 8; - _dbg a1; - _dbg astat; - - A1 = - A1; - cc = az; - r7 = cc; - dbga(r7.l, 0); - cc = an; - r7 = cc; - dbga(r7.l, 0); - cc = av0; - r7 = cc; - dbga(r7.l, 1); - cc = av0s; - r7 = cc; - dbga(r7.l, 1); - cc = av1; - r7 = cc; - dbga(r7.l, 1); - cc = av1s; - r7 = cc; - dbga(r7.l, 1); - - _dbg astat; - _dbg a1; - pass diff --git a/sim/testsuite/sim/bfin/mult.s b/sim/testsuite/sim/bfin/mult.s deleted file mode 100644 index 26bb55e..0000000 --- a/sim/testsuite/sim/bfin/mult.s +++ /dev/null @@ -1,22 +0,0 @@ -# Blackfin testcase for multiply -# mach: bfin - - .include "testutils.inc" - - start - - R0 = 0; - R1 = 0; - R2 = 0; - R3 = 0; - A0 = 0; - A1 = 0; - R0.L = 0x0400; - R1.L = 0x0010; - R2.L = ( A0 = R0.L * R1.L ) (S2RND); - R3 = 0x1 (Z); - CC = R3 == R2; - if CC jump 1f; - fail -1: - pass diff --git a/sim/testsuite/sim/bfin/neg-2.S b/sim/testsuite/sim/bfin/neg-2.S deleted file mode 100644 index 4430171..0000000 --- a/sim/testsuite/sim/bfin/neg-2.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for negate instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x8000; - R0.L = 0x0000; - R1 = -R0; - R7 = ASTAT; - R2.H = 0x8000; - R2.L = 0x0000; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AZ AC0 AC0_COPY */ - R3.H = HI(_AZ|_AC0|_AC0_COPY); - R3.L = LO(_AZ|_AC0|_AC0_COPY); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: AN V V_COPY VS */ - R3.H = HI(_AN|_V|_V_COPY|_VS); - R3.L = LO(_AN|_V|_V_COPY|_VS); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC1 */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC1); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC1); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/neg-3.S b/sim/testsuite/sim/bfin/neg-3.S deleted file mode 100644 index f1f0a2f..0000000 --- a/sim/testsuite/sim/bfin/neg-3.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for negate instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x0; - R0.L = 0x0; - R1 = -R0; - R7 = ASTAT; - R2.H = 0x0; - R2.L = 0x0; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AN V V_COPY */ - R3.H = HI(_AN|_V|_V_COPY); - R3.L = LO(_AN|_V|_V_COPY); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: AZ AC0 AC0_COPY */ - R3.H = HI(_AZ|_AC0|_AC0_COPY); - R3.L = LO(_AZ|_AC0|_AC0_COPY); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC1 */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/neg.S b/sim/testsuite/sim/bfin/neg.S deleted file mode 100644 index 45649a1..0000000 --- a/sim/testsuite/sim/bfin/neg.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for negate instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x1234; - R0.L = 0x5678; - R1 = -R0; - R7 = ASTAT; - R2.H = 0xedcb; - R2.L = 0xa988; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AZ V V_COPY AC0 AC0_COPY */ - R3.H = HI(_AZ|_V|_V_COPY|_AC0|_AC0_COPY); - R3.L = LO(_AZ|_V|_V_COPY|_AC0|_AC0_COPY); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: AN */ - R3.H = HI(_AN); - R3.L = LO(_AN); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC1 */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/nshift.s b/sim/testsuite/sim/bfin/nshift.s deleted file mode 100644 index f9e345b..0000000 --- a/sim/testsuite/sim/bfin/nshift.s +++ /dev/null @@ -1,33 +0,0 @@ -// ACP 5.18: Shifter uses wrong shift value -# mach: bfin - -.include "testutils.inc" - start - - - r0=0; - r0.h=0x8000; - r1=0x20 (z); - r0 >>>= r1; - dbga (r0.h, 0xffff); - dbga (r0.l, 0xffff); - - r0=0; - r0.h=0x7fff; - r0 >>>= r1; - dbga (r0.h, 0x0000); - dbga (r0.l, 0x0000); - - r0.l=0xffff; - r0.h=0xffff; - r0 >>= r1; - dbga (r0.h, 0x0000); - dbga (r0.l, 0x0000); - - r0.l=0xffff; - r0.h=0xffff; - r0 <<= r1; - dbga (r0.h, 0x0000); - dbga (r0.l, 0x0000); - - pass; diff --git a/sim/testsuite/sim/bfin/pr.s b/sim/testsuite/sim/bfin/pr.s deleted file mode 100644 index d290184..0000000 --- a/sim/testsuite/sim/bfin/pr.s +++ /dev/null @@ -1,81 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - loadsym R3, foo; - I1 = R3; - - R4 = 0x10 - R4 = R4 + R3; - P0 = R4; - - R4 = 0x14; - R4 = R4 + R3; - I0 = R4; - - r0 = 0x22; - loadsym P1, bar; - - [i0] = r0; - [i1] = r0; - -doItAgain: - - p2 = 4; - r5=0; - - LSETUP ( lstart , lend) LC0 = P2; -lstart: - - MNOP || R2 = [ I0 ++ ] || R1 = [ I1 ++ ]; - CC = R1 == R2; - IF CC JUMP lend; - R1 = [ P1 + 0x0 ]; - R1 = R1 + R0; - [ P1 + 0x0 ] = R1; - -lend: - NOP; - - if !cc jump _halt0; - cc = r5 == 0; - if !cc jump _halt0; - - r4=1; - r5=r5+r4; - r1=i0; - R4 = 0x24; - R4 = R3 + R4 - CC = R1 == R4 - if !CC JUMP _fail; - - i2=i0; - r2=0x1234; - [i2++]=r2; - [i2++]=r2; - [i2++]=r2; - [i2++]=r2; - [i2++]=r2; - [i2++]=r2; - [i2++]=r2; - jump doItAgain; - -_halt0: - r0=i0; - R4 = 0x34; - R4 = R4 + R3; - CC = R0 == R4; - IF !CC JUMP _fail; - - pass; - -_fail: - fail; - - .data -foo: - .space (0x100); - -bar: - .space (0x1000); diff --git a/sim/testsuite/sim/bfin/push-pop-multiple.s b/sim/testsuite/sim/bfin/push-pop-multiple.s deleted file mode 100644 index 2a2b356..0000000 --- a/sim/testsuite/sim/bfin/push-pop-multiple.s +++ /dev/null @@ -1,169 +0,0 @@ -# Blackfin testcase for push/pop multiples instructions -# mach: bfin - - .include "testutils.inc" - - # Tests follow the pattern: - # - do the push multiple - # - write a garbage value to all registers pushed - # - do the pop multiple - # - check all registers popped against known values - - start - - # Repeat the same operation multiple times, so this: - # do_x moo, R, 1 - # becomes this: - # moo R1, 0x11111111 - # moo R0, 0x00000000 - .macro _do_x func:req, reg:req, max:req, x:req - .ifle (\max - \x) - \func \reg\()\x, 0x\x\x\x\x\x\x\x\x - .endif - .endm - .macro do_x func:req, reg:req, max:req - .ifc \reg, R - _do_x \func, \reg, \max, 7 - _do_x \func, \reg, \max, 6 - .endif - _do_x \func, \reg, \max, 5 - _do_x \func, \reg, \max, 4 - _do_x \func, \reg, \max, 3 - _do_x \func, \reg, \max, 2 - _do_x \func, \reg, \max, 1 - _do_x \func, \reg, \max, 0 - .endm - - # Keep the garbage value in I0 - .macro loadi reg:req, val:req - \reg = I0; - .endm - imm32 I0, 0xAABCDEFF - - # - # Test push/pop multiples with (R7:x) syntax - # - - _push_r_tests: - - # initialize all Rx regs with a known value - do_x imm32, R, 0 - - .macro checkr tochk:req, val:req - P0 = \tochk; - imm32 P1, \val - CC = P0 == P1; - IF !CC JUMP 8f; - .endm - - .macro pushr maxr:req - _push_r\maxr: - [--SP] = (R7:\maxr); - do_x loadi, R, \maxr - (R7:\maxr) = [SP++]; - do_x checkr, R, \maxr - # need to do a long jump to avoid PCREL issues - jump 9f; - 8: jump.l 1f; - 9: - .endm - - pushr 7 - pushr 6 - pushr 5 - pushr 4 - pushr 3 - pushr 2 - pushr 1 - pushr 0 - - # - # Test push/pop multiples with (P5:x) syntax - # - - _push_p_tests: - - # initialize all Px regs with a known value - do_x imm32, P, 0 - - .macro checkp tochk:req, val:req - R0 = \tochk; - imm32 R1, \val - CC = R0 == R1; - IF !CC JUMP 8f; - .endm - - .macro pushp maxp:req - _push_p\maxp: - [--SP] = (P5:\maxp); - do_x loadi, P, \maxp - (P5:\maxp) = [SP++]; - do_x checkp, P, \maxp - # need to do a long jump to avoid PCREL issues - jump 9f; - 8: jump.l 1f; - 9: - .endm - - # checkp func clobbers R0/R1 - L0 = R0; - L1 = R1; - pushp 5 - pushp 4 - pushp 3 - pushp 2 - pushp 1 - pushp 0 - R0 = L0; - R1 = L1; - - # - # Test push/pop multiples with (R7:x, P5:x) syntax - # - - _push_rp_tests: - - .macro _pushrp maxr:req, maxp:req - _push_r\maxr\()_p\maxp: - [--SP] = (R7:\maxr, P5:\maxp); - do_x loadi, R, \maxr - do_x loadi, P, \maxp - (R7:\maxr, P5:\maxp) = [SP++]; - # checkr func clobbers P0/P1 - L0 = P0; - L1 = P1; - do_x checkr, R, \maxr - P1 = L1; - P0 = L0; - # checkp func clobbers R0/R1 - L0 = R0; - L1 = R1; - do_x checkp, P, \maxp - R0 = L0; - R1 = L1; - # need to do a long jump to avoid PCREL issues - jump 9f; - 8: jump.l 1f; - 9: - .endm - .macro pushrp maxr:req - _pushrp \maxr, 5 - _pushrp \maxr, 4 - _pushrp \maxr, 3 - _pushrp \maxr, 2 - _pushrp \maxr, 1 - _pushrp \maxr, 0 - .endm - - pushrp 7 - pushrp 6 - pushrp 5 - pushrp 4 - pushrp 3 - pushrp 2 - pushrp 1 - pushrp 0 - - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/push-pop.s b/sim/testsuite/sim/bfin/push-pop.s deleted file mode 100644 index bd6eda8..0000000 --- a/sim/testsuite/sim/bfin/push-pop.s +++ /dev/null @@ -1,95 +0,0 @@ -# Blackfin testcase for push/pop instructions -# mach: bfin - - .include "testutils.inc" - - start - - # This uses R0/R1 as scratch ... assume those work fine in general - .macro check loader:req, reg:req - \loader \reg, 0x12345678 - [--SP] = \reg; - R0 = [SP]; - R1 = \reg; - CC = R0 == R1; - IF !CC JUMP 8f; - \loader \reg, 0x87654321 - \reg = [SP++]; - CC = R0 == R1; - IF !CC JUMP 8f; - # need to do a long jump to avoid PCREL issues - jump 9f; - 8: jump 1f; - 9: - .endm - .macro imm_check reg:req - check imm32, \reg - .endm - .macro dmm_check reg:req - check dmm32, \reg - .endm - - imm_check R2 - imm_check R3 - imm_check R4 - imm_check R5 - imm_check R6 - imm_check R7 - imm_check P0 - imm_check P1 - imm_check P2 - imm_check P3 - imm_check P4 - imm_check P5 - imm_check FP - imm_check I0 - imm_check I1 - imm_check I2 - imm_check I3 - imm_check M0 - imm_check M1 - imm_check M2 - imm_check M3 - imm_check B0 - imm_check B1 - imm_check B2 - imm_check B3 - imm_check L0 - imm_check L1 - imm_check L2 - imm_check L3 - dmm_check A0.X - dmm_check A0.W - dmm_check A1.X - dmm_check A1.W - dmm_check LC0 - dmm_check LC1 - # Make sure the top/bottom regs have bit 1 set - dmm_check LT0 - dmm_check LT1 - dmm_check LB0 - dmm_check LB1 - dmm_check RETS - - # These require supervisor resources -.ifndef BFIN_HOST - dmm_check RETI - dmm_check RETX - dmm_check RETN - # RETE likes to change on the fly with an ICE - # dmm_check RETE - # CYCLES can be user mode, but screws kernel - dmm_check CYCLES - dmm_check CYCLES2 - dmm_check USP - - # No one pushes/pops these -# dmm_check EMUDAT - dmm_check SEQSTAT - dmm_check SYSCFG -.endif - dmm_check ASTAT - - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/pushpopreg_1.s b/sim/testsuite/sim/bfin/pushpopreg_1.s deleted file mode 100644 index 5bf4aa6..0000000 --- a/sim/testsuite/sim/bfin/pushpopreg_1.s +++ /dev/null @@ -1,292 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - r0.l = 0x1111; - r0.h = 0x0011; - r1.l = 0x2222; - r1.h = 0x0022; - r2.l = 0x3333; - r2.h = 0x0033; - r3.l = 0x4444; - r3.h = 0x0044; - r4.l = 0x5555; - r4.h = 0x0055; - r5.l = 0x6666; - r5.h = 0x0066; - r6.l = 0x7777; - r6.h = 0x0077; - r7.l = 0x8888; - r7.h = 0x0088; - p1.l = 0x5a5a; - p1.h = 0x005a; - p2.l = 0x6363; - p2.h = 0x0063; - p3.l = 0x7777; - p3.h = 0x0077; - p4.l = 0x7878; - p4.h = 0x0078; - p5.l = 0x3e3e; - p5.h = 0x003e; - sp = 0x4000(x); - - jump.s prog_start; - - nop; - nop; // ADD reg update to roll back - nop; - -prog_start: - nop; - [--sp] = r0; - [--sp] = r1; - [--sp] = r2; - [--sp] = r3; - [--sp] = r4; - [--sp] = r5; - [--sp] = r6; - [--sp] = r7; - [--sp] = p0; - [--sp] = p1; - [--sp] = p2; - [--sp] = p3; - [--sp] = p4; - [--sp] = p5; - - nop; - nop; - nop; - nop; - r0.l = 0xdead; - r0.h = 0xdead; - r1.l = 0xdead; - r1.h = 0xdead; - r2.l = 0xdead; - r2.h = 0xdead; - r3.l = 0xdead; - r3.h = 0xdead; - r4.l = 0xdead; - r4.h = 0xdead; - r5.l = 0xdead; - r5.h = 0xdead; - r6.l = 0xdead; - r6.h = 0xdead; - r7.l = 0xdead; - r7.h = 0xdead; - p1.l = 0xdead; - p1.h = 0xdead; - p2.l = 0xdead; - p2.h = 0xdead; - p3.l = 0xdead; - p3.h = 0xdead; - p4.l = 0xdead; - p4.h = 0xdead; - p5.l = 0xdead; - p5.h = 0xdead; - nop; - nop; - nop; - r0 = [sp++]; - r1 = [sp++]; - r2 = [sp++]; - r3 = [sp++]; - r4 = [sp++]; - r5 = [sp++]; - r6 = [sp++]; - r7 = [sp++]; - p0 = [sp++]; - p1 = [sp++]; - p2 = [sp++]; - p3 = [sp++]; - p4 = [sp++]; - p5 = [sp++]; - - nop; - nop; - nop; - nop; - nop; - nop; - nop; -_tp1: - nop; - nop; - nop; - nop; - nop; - nop; - nop; - [--sp] = r0; - [--sp] = r1; - [--sp] = r2; - [--sp] = r3; - [--sp] = r4; - [--sp] = r5; - [--sp] = r6; - [--sp] = r7; - [--sp] = p0; - [--sp] = p1; - [--sp] = p2; - [--sp] = p3; - [--sp] = p4; - [--sp] = p5; - - nop; - nop; - nop; - nop; - r0.l = 0xdead; - r0.h = 0xdead; - r1.l = 0xdead; - r1.h = 0xdead; - r2.l = 0xdead; - r2.h = 0xdead; - r3.l = 0xdead; - r3.h = 0xdead; - r4.l = 0xdead; - r4.h = 0xdead; - r5.l = 0xdead; - r5.h = 0xdead; - r6.l = 0xdead; - r6.h = 0xdead; - r7.l = 0xdead; - r7.h = 0xdead; - p1.l = 0xdead; - p1.h = 0xdead; - p2.l = 0xdead; - p2.h = 0xdead; - p3.l = 0xdead; - p3.h = 0xdead; - p4.l = 0xdead; - p4.h = 0xdead; - p5.l = 0xdead; - p5.h = 0xdead; - nop; - nop; - nop; - r0 = [sp++]; - r1 = [sp++]; - r2 = [sp++]; - r3 = [sp++]; - r4 = [sp++]; - r5 = [sp++]; - r6 = [sp++]; - r7 = [sp++]; - p0 = [sp++]; - p1 = [sp++]; - a0.x = [sp++]; - - a1.w = r0; //preserve r0 - - r0 = a0.x; - DBGA(r0.l,0x0063); - - a0.w = [sp++]; - r0 = a0.w; - DBGA(r0.l,0x7777); - DBGA(r0.h,0x0077); - - a0 = a1; //perserver r0, still - - a1.x = [sp++]; - r0 = a1.x; - DBGA(r0.l,0x0078); - - a1.w = [sp++]; - r0 = a1.w; - DBGA(r0.l,0x3e3e); - DBGA(r0.h,0x003e); - - r0 = a0.w; //restore r0 - - nop; - nop; - nop; - nop; - nop; - nop; - nop; -_tp2: - nop; - nop; - nop; - [--sp] = r0; - [--sp] = r1; - [--sp] = r2; - [--sp] = r3; - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = a1.x; - [--sp] = a1.w; - [--sp] = p0; - [--sp] = p1; - [--sp] = p2; - [--sp] = p3; - [--sp] = p4; - [--sp] = p5; - - nop; - nop; - nop; - nop; - r0.l = 0xdead; - r0.h = 0xdead; - r1.l = 0xdead; - r1.h = 0xdead; - r2.l = 0xdead; - r2.h = 0xdead; - r3.l = 0xdead; - r3.h = 0xdead; - r4.l = 0xdead; - r4.h = 0xdead; - r5.l = 0xdead; - r5.h = 0xdead; - r6.l = 0xdead; - r6.h = 0xdead; - r7.l = 0xdead; - r7.h = 0xdead; - p1.l = 0xdead; - p1.h = 0xdead; - p2.l = 0xdead; - p2.h = 0xdead; - p3.l = 0xdead; - p3.h = 0xdead; - p4.l = 0xdead; - p4.h = 0xdead; - p5.l = 0xdead; - p5.h = 0xdead; - nop; - nop; - nop; - r0 = [sp++]; - r1 = [sp++]; - r2 = [sp++]; - r3 = [sp++]; - r4 = [sp++]; - r5 = [sp++]; - r6 = [sp++]; - r7 = [sp++]; - p0 = [sp++]; - p1 = [sp++]; - p2 = [sp++]; - p3 = [sp++]; - p4 = [sp++]; - p5 = [sp++]; - - nop; - nop; - nop; - nop; - nop; - nop; - nop; -_tp3: - nop; - nop; - nop; - nop; - nop; -_halt: - pass; diff --git a/sim/testsuite/sim/bfin/quadaddsub.s b/sim/testsuite/sim/bfin/quadaddsub.s deleted file mode 100644 index 1502179..0000000 --- a/sim/testsuite/sim/bfin/quadaddsub.s +++ /dev/null @@ -1,58 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - R6.L = 32767; - R6.H = 2768; - R1.L = 2767; - R1.H = 2768; - - r7=0; - astat = r7; - r3 = r6 -|- r1; - _DBG r3; - _DBG ASTAT; - r7=ASTAT; - _DBG R7; - DBGA (R7.H, 0x0); - DBGA (R7.L, 0x3005); - - r7=0; - astat=r7; - r2 = r6 +|+ r1; - _DBG r2; - _DBG ASTAT; - r7=ASTAT; - _DBG R7; - DBGA (R7.H, 0x0300); - DBGA (R7.L, 0x000a); - - r7=0; - astat=r7; - r2 = r6 +|+ r1, r3 = r6 -|- r1; - - _DBG r2; - _DBG r3; - _DBG ASTAT; - - R7 = ASTAT; - _DBG R7; - DBGA (R7.H, 0x0300); - DBGA (R7.L, 0x000b); - - r7=0; - astat=r7; - r2 = r6 +|- r1, r3 = r6 -|+ r1; - - _DBG r2; - _DBG r3; - _DBG ASTAT; - - R7 = ASTAT; - _DBG R7; - DBGA (R7.H, 0x0300); - DBGA (R7.L, 0x000b); - - pass diff --git a/sim/testsuite/sim/bfin/random_0001.s b/sim/testsuite/sim/bfin/random_0001.s deleted file mode 100644 index 3cc946f..0000000 --- a/sim/testsuite/sim/bfin/random_0001.s +++ /dev/null @@ -1,13 +0,0 @@ -# Test for saturation behavior with fract multiplication -# mach: bfin - -.include "testutils.inc" - - start - - dmm32 A0.w, 0x45c1969f; - dmm32 A0.x, 0x00000000; - R4 = A0 (IU); - checkreg R4, 0x45c1969f; - - pass diff --git a/sim/testsuite/sim/bfin/random_0002.S b/sim/testsuite/sim/bfin/random_0002.S deleted file mode 100644 index 3567ae0..0000000 --- a/sim/testsuite/sim/bfin/random_0002.S +++ /dev/null @@ -1,25 +0,0 @@ -# Test for ASTAT V overflows with dsp mult insns -# mach: bfin - -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x54604e00 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY); - imm32 R1, 0x47f491c5; - imm32 R3, 0xfe4cfc98; - imm32 R7, 0x77aa2b21; - R3.L = R7.H * R1.H (IU); - checkreg R3, 0xfe4cffff; - checkreg ASTAT, (0x54604e00 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x10f00200 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AN); - imm32 R0, 0x24f45737; - imm32 R1, 0x6752f56b; - imm32 R4, 0x3f939925; - R4.H = R0.L * R1.H (IS); - checkreg R4, 0x7fff9925; - checkreg ASTAT, (0x10f00200 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0003.S b/sim/testsuite/sim/bfin/random_0003.S deleted file mode 100644 index d9852f2..0000000 --- a/sim/testsuite/sim/bfin/random_0003.S +++ /dev/null @@ -1,48 +0,0 @@ -# Test for ASTAT AN setting when overflows occur -# mach: bfin - -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x18204a80 | _AV1S | _AV0 | _AQ | _CC | _AC0_COPY | _AN | _AZ); - dmm32 A1.w, 0x1098e30b; - dmm32 A1.x, 0x0000001f; - imm32 R0, 0x440ed6ae; - imm32 R5, 0x3272c296; - R0.H = (A1 += R0.L * R5.H); - checkreg R0, 0x7fffd6ae; - checkreg A1.w, 0x00500e03; - checkreg A1.x, 0x0000001f; - checkreg ASTAT, (0x18204a80 | _VS | _V | _AV1S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x28c08e90 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN); - dmm32 A0.w, 0xb9da9f02; - dmm32 A0.x, 0x00000010; - imm32 R0, 0xc104b252; - R0.L = A0 (IS); - checkreg R0, 0xc1047fff; - checkreg ASTAT, (0x28c08e90 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x3cc04000 | _AV0S | _AV0 | _CC | _AC0_COPY | _AZ); - dmm32 A0.w, 0x2cc20f30; - dmm32 A0.x, 0xffffffd0; - imm32 R2, 0x367adfeb; - imm32 R5, 0x53eeff3c; - A0 += R5.H * R2.H (IS); - checkreg A0.w, 0x3e9e429c; - checkreg A0.x, 0xffffffd0; - checkreg ASTAT, (0x3cc04000 | _AV0S | _CC | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x18c0ca90 | _V | _AV1S | _AV1 | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ); - dmm32 A1.w, 0x0614ca96; - dmm32 A1.x, 0x00000053; - imm32 R3, 0x6c490457; - R3 = (A1 -= R3.L * R3.L) (M, S2RND); - checkreg R3, 0x7fffffff; - checkreg A1.w, 0x0601f505; - checkreg A1.x, 0x00000053; - checkreg ASTAT, (0x18c0ca90 | _VS | _V | _AV1S | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ); - - pass diff --git a/sim/testsuite/sim/bfin/random_0004.S b/sim/testsuite/sim/bfin/random_0004.S deleted file mode 100644 index fddabbc..0000000 --- a/sim/testsuite/sim/bfin/random_0004.S +++ /dev/null @@ -1,33 +0,0 @@ -# Test for ASTAT bits being written when they shouldn't (only a reg mov) -# mach: bfin - -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x1c304e90 | _VS | _V | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0x74d5f9df; - dmm32 A0.x, 0x0000005e; - imm32 R4, 0x00b47e9b; - R4 = A0; - checkreg R4, 0x7fffffff; - checkreg ASTAT, (0x1c304e90 | _VS | _V | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x6cd08a00 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _AN | _AZ); - dmm32 A1.w, 0x124e2817; - dmm32 A1.x, 0x00000011; - imm32 R2, 0x545a7c91; - R2.H = A1; - checkreg R2, 0x7fff7c91; - checkreg ASTAT, (0x6cd08a00 | _VS | _V | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x60700280 | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN); - dmm32 A0.w, 0x02184a1c; - dmm32 A0.x, 0xffffffc0; - imm32 R5, 0x60dc408a; - R5.L = A0 (IS); - checkreg R5, 0x60dc8000; - checkreg ASTAT, (0x60700280 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0005.S b/sim/testsuite/sim/bfin/random_0005.S deleted file mode 100644 index 8980dfe..0000000 --- a/sim/testsuite/sim/bfin/random_0005.S +++ /dev/null @@ -1,24 +0,0 @@ -# Test for ASTAT AZ bit update with 16 bit add and sub insns -# mach: bfin - -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x10a04e10 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY); - imm32 R3, 0x05fd7405; - imm32 R7, 0x7fff7fff; - R3.H = R7.L - R7.H (NS); - checkreg R3, 0x00007405; - checkreg ASTAT, (0x10a04e10 | _VS | _AV1S | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x64200e10 | _VS | _AV0S | _AC1 | _AC0 | _AZ); - imm32 R1, 0x2c388489; - imm32 R3, 0x38f39dcc; - imm32 R5, 0x27ed8efa; - R3.H = R1.L + R5.L (NS); - checkreg R3, 0x13839dcc; - checkreg ASTAT, (0x64200e10 | _VS | _V | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/random_0006.S b/sim/testsuite/sim/bfin/random_0006.S deleted file mode 100644 index bafe19a..0000000 --- a/sim/testsuite/sim/bfin/random_0006.S +++ /dev/null @@ -1,23 +0,0 @@ -# Test BYTEOP[123]P behavior when source reg pairs match -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - imm32 R0, (0x18204e10 | _VS | _AV1S | _AV0S | _AC1 | _CC); ASTAT = R0; - imm32 R1, 0x05b931c4; - imm32 R4, 0x05f205f2; - R4 = BYTEOP1P (R1:0, R1:0) (T, R); - - imm32 R0, (0x3470cc10 | _VS | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); ASTAT = R0; - imm32 R1, 0x00000000; - imm32 R6, 0x0000007f; - R6 = BYTEOP2P (R1:0, R1:0) (RNDH); - - imm32 R0, (0x1c708c90 | _VS | _V | _AV1S | _AC0 | _V_COPY | _AC0_COPY | _AN); ASTAT = R0; - imm32 R0, 0x3e2a80ca; - imm32 R1, 0x20dec740; - R0 = BYTEOP3P (R1:0, R1:0) (LO); - - pass diff --git a/sim/testsuite/sim/bfin/random_0007.S b/sim/testsuite/sim/bfin/random_0007.S deleted file mode 100644 index eb98e07..0000000 --- a/sim/testsuite/sim/bfin/random_0007.S +++ /dev/null @@ -1,60 +0,0 @@ -# Make sure the acc regs are updated even when the search criteria is not met -# (this implicitly affects the top 8 bits) -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x08e00690 | _VS | _AC1 | _AN); - dmm32 A0.w, 0x42357aea; - dmm32 A0.x, 0x00000001; - dmm32 A1.w, 0x3a3f0000; - dmm32 A1.x, 0x00000000; - imm32 P0, 0x7119f94d; - imm32 R4, 0xcdeea690; - imm32 R5, 0xffb58000; - imm32 R6, 0x72252b1e; - (R4, R5) = SEARCH R6 (GE); - checkreg R4, 0x7119f94d; - checkreg A0.w, 0x00007aea; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0x00007225; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x08e00690 | _VS | _AC1 | _AN); - - dmm32 ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0x4193c6bc; - dmm32 A0.x, 0xffffffd4; - dmm32 A1.w, 0xa97e7452; - dmm32 A1.x, 0xffffffff; - imm32 P0, 0x51e152a5; - imm32 R1, 0x36deeb9a; - imm32 R5, 0x386ab3f7; - imm32 R7, 0x2a3d5114; - (R5, R1) = SEARCH R7 (GT); - checkreg R1, 0x51e152a5; - checkreg A0.w, 0x00005114; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0x00007452; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0x4193c6bc; - dmm32 A0.x, 0xffffffd4; - dmm32 A1.w, 0x0000ffff; - dmm32 A1.x, 0x00000000; - imm32 P0, 0x51e152a5; - imm32 R1, 0x36deeb9a; - imm32 R5, 0x386ab3f7; - imm32 R7, 0xFa3d5114; - (R5, R1) = SEARCH R7 (GT); - checkreg R1, 0x51e152a5; - checkreg A0.w, 0x00005114; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/random_0008.S b/sim/testsuite/sim/bfin/random_0008.S deleted file mode 100644 index d856b0c..0000000 --- a/sim/testsuite/sim/bfin/random_0008.S +++ /dev/null @@ -1,44 +0,0 @@ -# check ASTAT ac/av flags are handled correctly when doing Acc = -Acc -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x5020ca80 | _VS | _AV1S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0x549e07b3; - dmm32 A1.x, 0x0000002a; - A1 = -A1; - checkreg A1.w, 0xab61f84d; - checkreg A1.x, 0xffffffd5; - checkreg ASTAT, (0x5020ca80 | _VS | _AV1S | _AC0 | _AQ | _CC | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x48908a10 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AN); - dmm32 A0.w, 0x3c57e100; - dmm32 A0.x, 0xfffffff2; - dmm32 A1.w, 0xfb63b8a0; - dmm32 A1.x, 0xffffffff; - A1 = -A0; - checkreg A1.w, 0xc3a81f00; - checkreg A1.x, 0x0000000d; - checkreg ASTAT, (0x48908a10 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY); - - dmm32 ASTAT, (0x10900880 | _V | _AC0 | _CC | _AC0_COPY); - dmm32 A0.w, 0x4ca147ce; - dmm32 A0.x, 0xffffff9d; - dmm32 A1.w, 0x0e2534b9; - dmm32 A1.x, 0xffffff85; - A0 = -A1; - checkreg A0.w, 0xf1dacb47; - checkreg A0.x, 0x0000007a; - checkreg ASTAT, (0x10900880 | _V | _CC); - - dmm32 ASTAT, (0x34904e90 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN); - dmm32 A0.w, 0x7826f07d; - dmm32 A0.x, 0xffffffc2; - A0 = -A0; - checkreg A0.w, 0x87d90f83; - checkreg A0.x, 0x0000003d; - checkreg ASTAT, (0x34904e90 | _VS | _V | _AV1S | _AC1 | _V_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/random_0009.S b/sim/testsuite/sim/bfin/random_0009.S deleted file mode 100644 index 6b3960a..0000000 --- a/sim/testsuite/sim/bfin/random_0009.S +++ /dev/null @@ -1,103 +0,0 @@ -# Verify ASTAT bits are set correctly during dsp mac insns -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - dmm32 A0.w, 0x16ba2677; - dmm32 A0.x, 0x00000000; - imm32 R4, 0x80007fff; - A0 -= R4.H * R4.H (W32); - checkreg A0.w, 0x96ba2678; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x3c30c800 | _VS | _AV0S | _AC1 | _CC); - dmm32 A0.w, 0xf170d0c7; - dmm32 A0.x, 0xffffffff; - imm32 R2, 0x80008000; - A0 -= R2.H * R2.L (W32); - checkreg A0.w, 0x80000000; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x3c30c800 | _VS | _AV0S | _AV0 | _AC1 | _CC); - - dmm32 ASTAT, (0x6c200880 | _VS | _AV1S | _AC1 | _AC0 | _CC | _AN); - dmm32 A0.x, 0x560a1c52; - dmm32 A0.x, 0xffffffbb; - imm32 R5, 0x8000ffff; - A0 = R5.H * R5.H (W32); - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x6c200880 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _AN); - - dmm32 ASTAT, (0x58908a90 | _VS | _AC1 | _AC0 | _AQ); - dmm32 A0.w, 0x00c5a4e0; - dmm32 A0.x, 0x00000000; - imm32 R0, 0xffffb33a; - imm32 R2, 0xffffb33a; - imm32 R3, 0xb33a4cc6; - R2 = (A0 -= R0.L * R3.H) (FU); - checkreg R2, 0x00000000; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x58908a90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x2cc00c90 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY); - dmm32 A0.w, 0x00a38000; - dmm32 A0.x, 0x00000000; - imm32 R0, 0x2aa2ffff; - imm32 R1, 0xff5c711e; - imm32 R4, 0x2913dc90; - R0 = (A0 -= R4.L * R1.L) (IU); - checkreg R0, 0x00000000; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x2cc00c90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x3880c280 | _VS | _AC1 | _AZ); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R4, 0x139ad315; - imm32 R6, 0x7fff0000; - R4.L = (A0 -= R6.H * R6.H) (FU); - checkreg R4, 0x139a0000; - checkreg ASTAT, (0x3880c280 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AZ); - - dmm32 ASTAT, (0x48408290 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY); - dmm32 A0.w, 0x6b426a69; - dmm32 A0.x, 0xffffffba; - imm32 R0, 0x24038000; - imm32 R2, 0xf62c7780; - imm32 R3, 0x5a64f8e8; - R2.L = (A0 -= R3.L * R0.L) (IH); - checkreg R2, 0xf62c8000; - checkreg A0.w, 0x80000000; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x48408290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x7c00c210 | _VS | _AC1 | _AN); - dmm32 A1.w, 0x730173e9; - dmm32 A1.x, 0xffffffae; - imm32 R4, 0x8000ffff; - imm32 R5, 0x738559e8; - R5.H = (A1 -= R4.L * R5.L) (M, IH); - checkreg R5, 0x800059e8; - checkreg A1.w, 0x80000000; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x7c00c210 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY | _AN); - - dmm32 ASTAT, (0x4830c400 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AZ); - dmm32 A0.w, 0x033a05f0; - dmm32 A0.x, 0x00000000; - imm32 R3, 0x5992dd5a; - imm32 R4, 0x098a889e; - imm32 R6, 0x8000de08; - R6.L = (A0 -= R4.L * R3.H) (TFU); - checkreg R6, 0x80000000; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x4830c400 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _CC | _V_COPY | _AZ); - - pass diff --git a/sim/testsuite/sim/bfin/random_0010.S b/sim/testsuite/sim/bfin/random_0010.S deleted file mode 100644 index c434edb..0000000 --- a/sim/testsuite/sim/bfin/random_0010.S +++ /dev/null @@ -1,78 +0,0 @@ -# Test logical left shift (vector) insns with larger shift values -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x30400e90 | _VS | _AV0S | _AC1 | _AQ | _AN); - imm32 R5, 0xb0b40000; - imm32 R6, 0xf43a5d3c; - R6 = R5 << 0x19 (V, S); - checkreg R6, 0xff610000; - checkreg ASTAT, (0x30400e90 | _VS | _AV0S | _AC1 | _AQ | _AN | _AZ); - - dmm32 ASTAT, (0x34104410 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN); - imm32 R2, 0xff2abd08; - imm32 R5, 0xf610ffff; - R2 = R5 << 0x11 (V, S); - checkreg R2, 0xffffffff; - checkreg ASTAT, (0x34104410 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN); - - dmm32 ASTAT, (0x6cd0c680 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - imm32 R0, 0x760ecf8e; - imm32 R1, 0x3f5c8af5; - R0 = R1 << 0x17 (V, S); - checkreg R0, 0x001fffc5; - checkreg ASTAT, (0x6cd0c680 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x44a04280 | _AV1S | _AV1 | _AC1 | _AC0 | _CC); - imm32 R4, 0x520cb3d4; - imm32 R6, 0x67141e28; - R6 = R4 << 0x14 (V, S); - checkreg R6, 0x0005fffb; - checkreg ASTAT, (0x44a04280 | _AV1S | _AV1 | _AC1 | _AC0 | _CC | _AN); - - dmm32 ASTAT, (0x14600c10 | _VS | _AV1S | _AC1 | _AC0 | _AN); - imm32 R3, 0x40407f7e; - imm32 R4, 0xc081e040; - R3 = R4 << 0x1a (V, S); - checkreg R3, 0xff02ff81; - checkreg ASTAT, (0x14600c10 | _VS | _AV1S | _AC1 | _AC0 | _AN); - - dmm32 ASTAT, (0x04f00490 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY); - imm32 R5, 0x63654235; - imm32 R7, 0x00008000; - R5 = R7 << 0x18 (V, S); - checkreg R5, 0x0000ff80; - checkreg ASTAT, (0x04f00490 | _VS | _AV0S | _AC1 | _AQ | _AN | _AZ); - - dmm32 ASTAT, (0x3830ca90 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AN); - imm32 R1, 0x40000000; - imm32 R2, 0x7fffffff; - R1 = R2 << 0x16 (V, S); - checkreg R1, 0x001fffff; - checkreg ASTAT, (0x3830ca90 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN); - - dmm32 ASTAT, (0x24e08890 | _VS | _AV0S | _AC1 | _CC | _AN | _AZ); - imm32 R2, 0xfffe0000; - imm32 R3, 0xd9d90000; - R2 = R3 << 0x19 (V, S); - checkreg R2, 0xffb30000; - checkreg ASTAT, (0x24e08890 | _VS | _AV0S | _AC1 | _CC | _AN | _AZ); - - dmm32 ASTAT, (0x30f0c200 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AZ); - imm32 R0, 0x32590000; - imm32 R2, 0x708bb53f; - R0 = R2 << 0x1c (V, S); - checkreg R0, 0x0708fb53; - checkreg ASTAT, (0x30f0c200 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x4cc00080 | _VS | _V | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN); - imm32 R3, 0x3563cfa3; - imm32 R7, 0x027e2255; - R7 = R3 << 0x1f (V, S); - checkreg R7, 0x1ab1e7d1; - checkreg ASTAT, (0x4cc00080 | _VS | _AC1 | _AQ | _AC0_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0011.S b/sim/testsuite/sim/bfin/random_0011.S deleted file mode 100644 index 0b0ccac..0000000 --- a/sim/testsuite/sim/bfin/random_0011.S +++ /dev/null @@ -1,102 +0,0 @@ -# test acc shifts larger than they should be, and ASTAT flags -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x7cc0c090 | _VS | _V | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ); - dmm32 A0.w, 0x1890bdbc; - dmm32 A0.x, 0x00000079; - A0 = A0 << 0x2; - checkreg A0.w, 0x6242f6f0; - checkreg A0.x, 0xffffffe4; - checkreg ASTAT, (0x7cc0c090 | _VS | _V | _AC1 | _AQ | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x50508600 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); - dmm32 A1.w, 0x02fe375e; - dmm32 A1.x, 0x00000000; - A1 = A1 >> 0x21; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0xffffffaf; - checkreg ASTAT, (0x50508600 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x7c800a10 | _VS | _AV0S | _AV0 | _AC1); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - A0 = A0 << 0x1f; - checkreg ASTAT, (0x7c800a10 | _VS | _AV0S | _AC1 | _AZ); - - dmm32 ASTAT, (0x4440c080 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - dmm32 A0.w, 0x2e4b0bba; - dmm32 A0.x, 0xffffff8c; - A0 = A0 >> 0x25; - checkreg A0.w, 0xd0000000; - checkreg A0.x, 0x0000005d; - checkreg ASTAT, (0x4440c080 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x4c90c680 | _VS | _AV1S | _AV0S | _AC0 | _CC); - dmm32 A1.w, 0x3ae26599; - dmm32 A1.x, 0xfffffff3; - A1 = A1 >> 0x25; - checkreg A1.w, 0xc8000000; - checkreg A1.x, 0x0000002c; - checkreg ASTAT, (0x4c90c680 | _VS | _AV1S | _AV0S | _AC0 | _CC); - - dmm32 ASTAT, (0x3c204000 | _AV1 | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC); - dmm32 A1.w, 0x1686a378; - dmm32 A1.x, 0x0000006a; - A1 = A1 >> 0x16; - checkreg A1.w, 0x0001a85a; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x3c204000 | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC); - - dmm32 ASTAT, (0x30500800 | _VS | _AV0S | _AQ); - dmm32 A1.w, 0x6575285f; - dmm32 A1.x, 0x00000000; - A1 = A1 >> 0x2e; - checkreg A1.w, 0xa17c0000; - checkreg A1.x, 0xffffffd4; - checkreg ASTAT, (0x30500800 | _VS | _AV0S | _AQ | _AN); - - dmm32 ASTAT, (0x70c04010 | _VS | _AV0S | _AQ | _CC); - dmm32 A1.w, 0x0c7da4e2; - dmm32 A1.x, 0x00000000; - A1 = A1 >> 0x29; - checkreg A1.w, 0x71000000; - checkreg A1.x, 0xffffffd2; - checkreg ASTAT, (0x70c04010 | _VS | _AV0S | _AQ | _CC | _AN); - - dmm32 ASTAT, (0x74000600 | _VS | _AC1 | _AQ); - dmm32 A0.w, 0xd0e47afa; - dmm32 A0.x, 0x00000006; - A0 = A0 >> 0x32; - checkreg A0.w, 0x1ebe8000; - checkreg A0.x, 0x00000039; - checkreg ASTAT, (0x74000600 | _VS | _AC1 | _AQ); - - dmm32 ASTAT, (0x4ce08200 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ); - dmm32 A1.w, 0x1b158860; - dmm32 A1.x, 0x00000068; - A1 = A1 >> 0x21; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000030; - checkreg ASTAT, (0x4ce08200 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ); - - dmm32 ASTAT, (0x48c00610 | _VS | _AV1S | _AQ | _CC | _AN); - dmm32 A1.w, 0x0a2c41e4; - dmm32 A1.x, 0x00000000; - A1 = A1 >> 0x25; - checkreg A1.w, 0x20000000; - checkreg A1.x, 0x0000000f; - checkreg ASTAT, (0x48c00610 | _VS | _AV1S | _AQ | _CC); - - dmm32 ASTAT, (0x08700400 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY | _AZ); - dmm32 A0.w, 0xec125059; - dmm32 A0.x, 0xffffffff; - A0 = A0 >> 0x32; - checkreg A0.w, 0x94164000; - checkreg A0.x, 0x00000004; - checkreg ASTAT, (0x08700400 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/random_0012.S b/sim/testsuite/sim/bfin/random_0012.S deleted file mode 100644 index cedf359..0000000 --- a/sim/testsuite/sim/bfin/random_0012.S +++ /dev/null @@ -1,52 +0,0 @@ -# test VIT_MAX behavior when high Acc bits are set -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x5860c690 | _VS | _AV0S | _AC1 | _AQ | _CC | _AC0_COPY); - dmm32 A0.w, 0xd81562e8; - dmm32 A0.x, 0xffffffff; - imm32 R4, 0x15c2d815; - imm32 R5, 0xc9bd3a6b; - R4.L = VIT_MAX (R5) (ASR); - checkreg R4, 0x15c23a6b; - checkreg A0.w, 0x6c0ab174; - checkreg A0.x, 0x0000007f; - checkreg ASTAT, (0x5860c690 | _VS | _AV0S | _AC1 | _AQ | _CC | _AC0_COPY); - - dmm32 ASTAT, (0x48308090 | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0x715cf6e6; - dmm32 A0.x, 0xffffffb6; - imm32 R3, 0x3a89c7ed; - imm32 R4, 0x4819bbf9; - R3.L = VIT_MAX (R4) (ASR); - checkreg R3, 0x3a89bbf9; - checkreg A0.w, 0x38ae7b73; - checkreg A0.x, 0x0000005b; - checkreg ASTAT, (0x48308090 | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x18104c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); - dmm32 A0.w, 0xea06f130; - dmm32 A0.x, 0xffffffff; - imm32 R2, 0x62ce98f1; - imm32 R5, 0x045415f9; - R2.L = VIT_MAX (R5) (ASR); - checkreg R2, 0x62ce15f9; - checkreg A0.w, 0x75037898; - checkreg A0.x, 0x0000007f; - checkreg ASTAT, (0x18104c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x0090ce10 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A0.w, 0xffffffff; - dmm32 A0.x, 0xffffffff; - imm32 R0, 0xc9647fff; - imm32 R6, 0x1d4baeb8; - R6.L = VIT_MAX (R0) (ASR); - checkreg R6, 0x1d4bc964; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0x0000007f; - checkreg ASTAT, (0x0090ce10 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0013.S b/sim/testsuite/sim/bfin/random_0013.S deleted file mode 100644 index 9a427b3..0000000 --- a/sim/testsuite/sim/bfin/random_0013.S +++ /dev/null @@ -1,417 +0,0 @@ -# Ensure that dsp insns with IH modifiers saturate first, then round -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x24304400 | _VS | _AV1S | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ); - dmm32 A0.w, 0x3883de11; - dmm32 A0.x, 0x00000025; - imm32 R2, 0xeb641947; - imm32 R3, 0x66d10863; - imm32 R5, 0x00d44f5a; - R5.L = (A0 += R3.L * R2.L) (IH); - checkreg R5, 0x00d47fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x24304400 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x04b04e10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY); - dmm32 A0.w, 0x1e069e1a; - dmm32 A0.x, 0xfffffff5; - imm32 R3, 0xffff0001; - R3.L = A0 (IH); - checkreg R3, 0xffff8000; - checkreg ASTAT, (0x04b04e10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x14f08600 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - dmm32 A0.w, 0x766c79cc; - dmm32 A0.x, 0xffffffd9; - imm32 R4, 0x14801bff; - R4.L = A0 (IH); - checkreg R4, 0x14808000; - checkreg ASTAT, (0x14f08600 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x6060c600 | _VS | _AV1S | _AV0S | _AC1 | _V_COPY | _AN | _AZ); - dmm32 A0.w, 0x1e7461de; - dmm32 A0.x, 0xffffff91; - imm32 R6, 0x1ba08a9e; - R6.L = A0 (IH); - checkreg R6, 0x1ba08000; - checkreg ASTAT, (0x6060c600 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AN); - - dmm32 ASTAT, (0x28700e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); - dmm32 A0.w, 0xfb5acc4e; - dmm32 A0.x, 0xfffffffe; - imm32 R4, 0x15baf604; - R4.L = A0 (IH); - checkreg R4, 0x15ba8000; - checkreg ASTAT, (0x28700e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x24708610 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A0.w, 0x0de70c92; - dmm32 A0.x, 0xffffffde; - imm32 R3, 0x0f323c4c; - R3.L = A0 (IH); - checkreg R3, 0x0f328000; - checkreg ASTAT, (0x24708610 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x6800c880 | _AV1 | _AV0 | _AQ | _AZ); - dmm32 A0.w, 0x482bfb59; - dmm32 A0.x, 0x0000005e; - imm32 R6, 0x4616e4ad; - imm32 R7, 0x4a88b2b1; - R6.L = (A0 += R6.H * R7.L) (IH); - checkreg R6, 0x46167fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x6800c880 | _VS | _V | _AV1 | _AV0S | _AV0 | _AQ | _V_COPY | _AZ); - - dmm32 ASTAT, (0x44d08280 | _VS | _V | _AQ | _V_COPY | _AZ); - dmm32 A0.w, 0xf29e3a4c; - dmm32 A0.x, 0x0000003b; - imm32 R2, 0x004027d0; - imm32 R4, 0x44761fd1; - imm32 R7, 0x7fff0001; - R7.L = (A0 -= R4.H * R2.H) (IH); - checkreg R7, 0x7fff7fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x44d08280 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AZ); - - dmm32 ASTAT, (0x18a00680 | _VS | _AV1S | _AQ | _CC); - dmm32 A0.w, 0x174c203a; - dmm32 A0.x, 0x00000060; - imm32 R3, 0x1f100000; - R3.L = A0 (IH); - checkreg R3, 0x1f107fff; - checkreg ASTAT, (0x18a00680 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x38e04090 | _VS | _AV0S | _AQ | _AN | _AZ); - dmm32 A0.w, 0x5db9b913; - dmm32 A0.x, 0x00000048; - imm32 R0, 0xd513ffff; - imm32 R2, 0xfcee02ff; - R0.L = (A0 -= R2.H * R0.H) (IH); - checkreg R0, 0xd5137fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x38e04090 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x2030c680 | _VS | _V | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0x113de06e; - dmm32 A0.x, 0x00000006; - imm32 R3, 0x3de9b335; - R3.L = A0 (IH); - checkreg R3, 0x3de97fff; - checkreg ASTAT, (0x2030c680 | _VS | _V | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x14300210 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0x3219dde5; - dmm32 A0.x, 0xfffffffe; - imm32 R2, 0x8000ffde; - R2.L = A0 (IH); - checkreg R2, 0x80008000; - checkreg ASTAT, (0x14300210 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x5c304e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN); - dmm32 A0.w, 0x500d8a96; - dmm32 A0.x, 0x00000071; - imm32 R2, 0x47bc6a2d; - R2.L = A0 (IH); - checkreg R2, 0x47bc7fff; - checkreg ASTAT, (0x5c304e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x40d04410 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - dmm32 A0.w, 0xed76198b; - dmm32 A0.x, 0xffffffdd; - imm32 R4, 0x485f8000; - R4.L = A0 (IH); - checkreg ASTAT, (0x40d04410 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x34f00290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - dmm32 A0.w, 0xc0000000; - dmm32 A0.x, 0x00000000; - imm32 R0, 0x80008000; - imm32 R3, 0x2cb77eda; - R0.L = (A0 += R3.H * R3.H) (IH); - checkreg R0, 0x80007fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x34f00290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x2490c610 | _VS | _V | _V_COPY | _AN); - dmm32 A0.w, 0xc2375c00; - dmm32 A0.x, 0x00000000; - imm32 R0, 0x8000ffff; - imm32 R1, 0xac86b35f; - imm32 R6, 0x3cb137de; - R0.L = (A0 -= R6.H * R1.H) (IH); - checkreg R0, 0x80007fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x2490c610 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AN); - - dmm32 ASTAT, (0x3000c810 | _VS | _AC0 | _AQ | _CC | _AN); - dmm32 A0.w, 0x44fe7a9d; - dmm32 A0.x, 0x0000006e; - imm32 R2, 0xbb4f8000; - imm32 R4, 0xfe2d7fff; - imm32 R7, 0x5da7ea43; - R7.L = (A0 += R4.L * R2.L) (IH); - checkreg R7, 0x5da77fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x3000c810 | _VS | _V | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x1c708000 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AZ); - dmm32 A0.w, 0x6ad001aa; - dmm32 A0.x, 0x0000002a; - imm32 R6, 0x7fff65d9; - R6.L = A0 (IH); - checkreg R6, 0x7fff7fff; - checkreg ASTAT, (0x1c708000 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x1430cc80 | _AV0S | _AC0 | _AQ | _AN | _AZ); - dmm32 A0.w, 0x5c04c87a; - dmm32 A0.x, 0x00000002; - imm32 R1, 0x6752c24c; - imm32 R7, 0x21f7c24f; - R1.L = (A0 -= R1.H * R7.H) (IH); - checkreg R1, 0x67527fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x1430cc80 | _VS | _V | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x44500c80 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A0.w, 0x603980cf; - dmm32 A0.x, 0xffffffff; - imm32 R3, 0xffffffff; - R3.L = A0 (IH); - checkreg R3, 0xffff8000; - checkreg ASTAT, (0x44500c80 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x70508c90 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY); - dmm32 A0.w, 0x097b558d; - dmm32 A0.x, 0x00000005; - imm32 R1, 0x80002c0a; - R1.L = A0 (IH); - checkreg R1, 0x80007fff; - checkreg ASTAT, (0x70508c90 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x1820c410 | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); - dmm32 A0.w, 0x69470e6b; - dmm32 A0.x, 0x0000005a; - imm32 R1, 0x3a0e82ef; - imm32 R4, 0x2c0af024; - imm32 R6, 0x5a301523; - R1.L = (A0 += R6.L * R4.L) (IH); - checkreg R1, 0x3a0e7fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x1820c410 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x14a04e10 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0xaaa829c8; - dmm32 A0.x, 0x0000000f; - imm32 R3, 0x901b7fff; - imm32 R4, 0xf8d50755; - imm32 R6, 0x0a98c742; - R4.L = (A0 += R3.L * R6.L) (IH); - checkreg R4, 0xf8d57fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x14a04e10 | _VS | _V | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x7c70c800 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY); - dmm32 A0.w, 0x3875c265; - dmm32 A0.x, 0x0000000e; - imm32 R0, 0x8000af00; - imm32 R3, 0x071fe97d; - imm32 R5, 0x72d82b4b; - R0.L = (A0 += R3.H * R5.H) (IH); - checkreg R0, 0x80007fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x7c70c800 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x04508a80 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY); - dmm32 A0.w, 0x5055d0b1; - dmm32 A0.x, 0x00000009; - imm32 R2, 0x7b9b1a96; - imm32 R4, 0x56a17f45; - R4.L = (A0 -= R4.L * R2.L) (IH); - checkreg R4, 0x56a17fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x04508a80 | _VS | _V | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x60408c90 | _VS | _AV1 | _CC | _AC0_COPY); - dmm32 A1.w, 0x4d722bbd; - dmm32 A1.x, 0x0000000a; - imm32 R1, 0x31c46841; - imm32 R4, 0xe31521b2; - imm32 R6, 0x49d747d4; - R6.H = (A1 -= R1.L * R4.L) (M, IH); - checkreg R6, 0x7fff47d4; - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x60408c90 | _VS | _V | _AV1S | _AV1 | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x7c808690 | _VS | _AV1S | _AC1 | _AC0 | _AC0_COPY); - dmm32 A0.w, 0x48379e0d; - dmm32 A0.x, 0x00000061; - imm32 R0, 0x272c8000; - imm32 R4, 0x7fff7fff; - R0.L = (A0 += R4.L * R4.H) (IH); - checkreg R0, 0x272c7fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x7c808690 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x10308800 | _VS | _AC1 | _AC0 | _AQ | _AN); - dmm32 A1.w, 0x9ddbf339; - dmm32 A1.x, 0x00000010; - imm32 R1, 0x00679160; - imm32 R5, 0x1fa0ffff; - imm32 R6, 0x4312c2cd; - R6.H = (A1 -= R1.L * R5.H) (IH); - checkreg R6, 0x7fffc2cd; - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x10308800 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x3040ca90 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC | _AN | _AZ); - dmm32 A0.w, 0x2d631ab7; - dmm32 A0.x, 0x00000066; - imm32 R5, 0x325c8000; - R5.L = A0 (IH); - checkreg R5, 0x325c7fff; - checkreg ASTAT, (0x3040ca90 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x5ca08c90 | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); - dmm32 A0.w, 0x86fce74b; - dmm32 A0.x, 0x0000007f; - imm32 R1, 0x3e9e0014; - imm32 R7, 0x6d73d06c; - R7.L = (A0 += R1.L * R7.H) (IH); - checkreg R7, 0x6d737fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x5ca08c90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x50e0c880 | _VS | _AC1); - dmm32 A0.w, 0x9e40a194; - dmm32 A0.x, 0x00000000; - imm32 R5, 0x6ba7ac29; - imm32 R6, 0x50a97ffe; - R5.L = (A0 += R6.L * R5.H) (IH); - checkreg R5, 0x6ba77fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x50e0c880 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY); - - dmm32 ASTAT, (0x3ce0c810 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN); - dmm32 A0.w, 0x9abe32ae; - dmm32 A0.x, 0xffffffc2; - imm32 R2, 0x8000e9a0; - R2.L = A0 (IH); - checkreg R2, 0x80008000; - checkreg ASTAT, (0x3ce0c810 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x6090c010 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY); - dmm32 A0.w, 0x53e97a53; - dmm32 A0.x, 0x0000004d; - imm32 R1, 0x289e2e4e; - R1.L = A0 (IH); - checkreg R1, 0x289e7fff; - checkreg ASTAT, (0x6090c010 | _VS | _V | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x34708800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); - dmm32 A0.w, 0x1035b3fa; - dmm32 A0.x, 0x00000001; - imm32 R1, 0xec227fff; - R1.L = A0 (IH); - checkreg ASTAT, (0x34708800 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x30200c00 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _V_COPY); - imm32 R1, 0x30d07fff; - imm32 R2, 0x007f1105; - imm32 R4, 0x7fffffff; - R1.H = R2.L * R4.L (M, IH); - checkreg R1, 0x11057fff; - checkreg ASTAT, (0x30200c00 | _VS | _AV1S | _AV0S | _AV0 | _AC1); - - dmm32 ASTAT, (0x1c008200 | _VS | _V | _AV1S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); - dmm32 A0.w, 0x46ccaead; - dmm32 A0.x, 0x0000006b; - imm32 R4, 0x80003753; - imm32 R5, 0x128216a3; - imm32 R6, 0x7c3455c4; - R4.L = (A0 += R5.L * R6.H) (IH); - checkreg R4, 0x80007fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x1c008200 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x14304e10 | _VS | _AV0S | _AV0 | _AC0); - dmm32 A0.w, 0x7fc17d70; - dmm32 A0.x, 0x0000000f; - imm32 R3, 0x5cb72991; - imm32 R4, 0x3a823142; - imm32 R7, 0xde5bf5a2; - R7.L = (A0 += R4.H * R3.H) (IH); - checkreg R7, 0xde5b7fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x14304e10 | _VS | _V | _AV0S | _AV0 | _AC0 | _V_COPY); - - dmm32 ASTAT, (0x10900290 | _VS | _V | _AQ | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0x7fb16a1d; - dmm32 A0.x, 0x00000052; - imm32 R0, 0x1e4a7fff; - imm32 R2, 0x62b886f4; - imm32 R3, 0x80004104; - R3.L = (A0 -= R2.H * R0.H) (IH); - checkreg R3, 0x80007fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x10900290 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x18608400 | _VS | _AV1S | _AQ | _AC0_COPY | _AN); - dmm32 A1.w, 0x62fcbde0; - dmm32 A1.x, 0x0000006a; - imm32 R2, 0x60339fcc; - imm32 R3, 0x5fa9f612; - imm32 R4, 0x6f006000; - R2.H = (A1 += R3.L * R4.H) (IH); - checkreg R2, 0x7fff9fcc; - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x18608400 | _VS | _V | _AV1S | _AV1 | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x60100210 | _VS | _V | _CC | _V_COPY | _AN); - dmm32 A0.w, 0x52a9b75e; - dmm32 A0.x, 0x00000003; - imm32 R0, 0xffff349c; - imm32 R6, 0x0084550f; - R0.L = (A0 += R6.L * R0.H) (IH); - checkreg R0, 0xffff7fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x60100210 | _VS | _V | _AV0S | _AV0 | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x7840cc10 | _VS | _V | _AV0 | _AC1 | _V_COPY | _AN | _AZ); - dmm32 A0.w, 0x22aa6b49; - dmm32 A0.x, 0x0000006a; - imm32 R1, 0x17528642; - imm32 R5, 0x8000a49b; - imm32 R6, 0x03ec4bb6; - R5.L = (A0 -= R1.H * R6.H) (IH); - checkreg R5, 0x80007fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x7840cc10 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN | _AZ); - - pass diff --git a/sim/testsuite/sim/bfin/random_0014.S b/sim/testsuite/sim/bfin/random_0014.S deleted file mode 100644 index c77b305..0000000 --- a/sim/testsuite/sim/bfin/random_0014.S +++ /dev/null @@ -1,82 +0,0 @@ -# Test a few corner cases with various shift insns -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x38404290 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN); - dmm32 A0.w, 0xf53d356e; - dmm32 A0.x, 0xffffffff; - imm32 R5, 0xaa156b54; - A0 = ASHIFT A0 BY R5.L; - checkreg A0.w, 0x56e00000; - checkreg A0.x, 0xffffffd3; - checkreg ASTAT, (0x38404290 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x28e00410 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY); - dmm32 A0.w, 0x1dfd2a85; - dmm32 A0.x, 0xffffffbe; - imm32 R2, 0x4b7cf707; - A0 = LSHIFT A0 BY R2.L; - checkreg A0.w, 0xfe954280; - checkreg A0.x, 0x0000000e; - checkreg ASTAT, (0x28e00410 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY); - - dmm32 ASTAT, (0x60404e00 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0xd4aa6e10; - dmm32 A1.x, 0xffffffff; - imm32 R4, 0xb4bb3054; - A1 = ASHIFT A1 BY R4.L; - checkreg A1.w, 0xe1000000; - checkreg A1.x, 0xffffffa6; - checkreg ASTAT, (0x60404e00 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x00608810 | _V | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0x0dbadb4f; - dmm32 A1.x, 0x00000035; - imm32 R3, 0x3cc3f7db; - A1 = LSHIFT A1 BY R3.L; - checkreg A1.w, 0x78000000; - checkreg A1.x, 0xffffffda; - checkreg ASTAT, (0x00608810 | _V | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x14900e10 | _VS | _AC0 | _CC | _AC0_COPY); - imm32 R0, 0x6286ee56; - imm32 R7, 0x5cd969c5; - R0 = ASHIFT R0 BY R7.L; - checkreg R0, 0x50ddcac0; - checkreg ASTAT, (0x14900e10 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x28904a90 | _VS | _V | _AV0S | _V_COPY | _AZ); - imm32 R0, 0x00000000; - imm32 R5, 0x00008000; - imm32 R6, 0x03488f9a; - R0.L = ASHIFT R5.L BY R6.L; - checkreg ASTAT, (0x28904a90 | _VS | _V | _AV0S | _V_COPY | _AZ); - - dmm32 ASTAT, (0x3c10c890 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY); - imm32 R1, 0x29162006; - imm32 R3, 0xffff0345; - imm32 R4, 0x8ff5e6bb; - R1.H = ASHIFT R4.H BY R3.L; - checkreg R1, 0xfea02006; - checkreg ASTAT, (0x3c10c890 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x78600e00 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC); - imm32 R0, 0xd5b1804d; - imm32 R1, 0x522c817d; - imm32 R5, 0xfca6f990; - R1.H = ASHIFT R5.H BY R0.L; - checkreg R1, 0xc000817d; - checkreg ASTAT, (0x78600e00 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x64b04890 | _VS | _V | _AV0S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - imm32 R4, 0x80000000; - imm32 R6, 0x4e840a3e; - imm32 R7, 0x20102e48; - R6.L = ASHIFT R4.H BY R7.L; - checkreg R6, 0x4e840000; - checkreg ASTAT, (0x64b04890 | _VS | _V | _AV0S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); - - pass diff --git a/sim/testsuite/sim/bfin/random_0015.S b/sim/testsuite/sim/bfin/random_0015.S deleted file mode 100644 index 60d6317..0000000 --- a/sim/testsuite/sim/bfin/random_0015.S +++ /dev/null @@ -1,25 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x5c70c410 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN); - dmm32 A1.w, 0xb7cc6ddd; - dmm32 A1.x, 0x00000004; - imm32 R3, 0x3f225ae3; - A1 = ASHIFT A1 BY R3.L; - checkreg A1.w, 0x00000025; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x5c70c410 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY); - - dmm32 ASTAT, (0x4810ca80 | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY | _AN); - dmm32 A1.w, 0x7396e11c; - dmm32 A1.x, 0xffffffba; - imm32 R3, 0x6e5f9f48; - A1 = ASHIFT A1 BY R3.L; - checkreg A1.w, 0x96e11c00; - checkreg A1.x, 0x00000073; - checkreg ASTAT, (0x4810ca80 | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/random_0016.S b/sim/testsuite/sim/bfin/random_0016.S deleted file mode 100644 index 0b45074..0000000 --- a/sim/testsuite/sim/bfin/random_0016.S +++ /dev/null @@ -1,26 +0,0 @@ -# Test LSHIFT values and ASTAT flags -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x7ce00000 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY | _AN); - dmm32 A0.w, 0xe1a3909e; - dmm32 A0.x, 0xffffffff; - imm32 R2, 0x214a26f6; - A0 = LSHIFT A0 BY R2.L; - checkreg A0.w, 0x3ff868e4; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x7ce00000 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x64008a00 | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _CC | _AN); - dmm32 A0.w, 0x72af1593; - dmm32 A0.x, 0xfffffffd; - imm32 R2, 0x6505b40c; - A0 = LSHIFT A0 BY R2.L; - checkreg A0.w, 0xf1593000; - checkreg A0.x, 0x0000002a; - checkreg ASTAT, (0x64008a00 | _AV1 | _AV0S | _AC0 | _AQ | _CC); - - pass diff --git a/sim/testsuite/sim/bfin/random_0017.S b/sim/testsuite/sim/bfin/random_0017.S deleted file mode 100644 index edfb650..0000000 --- a/sim/testsuite/sim/bfin/random_0017.S +++ /dev/null @@ -1,23 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x68000a10 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0x2771851d; - dmm32 A0.x, 0xffffffc9; - A0 = A0 >>> 0x1b; - checkreg A0.w, 0xfffff924; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x68000a10 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x74804c10 | _VS | _AC1 | _AC0 | _CC | _AN | _AZ); - dmm32 A1.w, 0xda2eb5c0; - dmm32 A1.x, 0xffffffff; - A1 = A1 >>> 0x11; - checkreg A1.w, 0xffffed17; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x74804c10 | _VS | _AC1 | _AC0 | _CC | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0018.S b/sim/testsuite/sim/bfin/random_0018.S deleted file mode 100644 index f6ec033..0000000 --- a/sim/testsuite/sim/bfin/random_0018.S +++ /dev/null @@ -1,69 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x40204090 | _AV1S | _AV0S | _AV0 | _AQ | _AN | _AZ); - imm32 R1, 0x33e91405; - imm32 R4, 0x3fa1377c; - R4.H = R1.H >>> 0x1d; - checkreg R4, 0x9f48377c; - checkreg ASTAT, (0x40204090 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x64800010 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY); - imm32 R0, 0xf64722bc; - R0.L = R0.L >>> 0xd (S); - checkreg R0, 0xf6470001; - checkreg ASTAT, (0x64800010 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY); - - dmm32 ASTAT, (0x70300e10 | _VS | _AQ | _AC0_COPY | _AN); - imm32 R5, 0x2a8771ff; - R5 = R5 >>> 0x1d (V); - checkreg R5, 0x54388ff8; - checkreg ASTAT, (0x70300e10 | _VS | _V | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x04600000 | _VS | _AV1S | _AC0 | _AQ | _CC | _AC0_COPY); - imm32 R6, 0x0c3a7fff; - imm32 R7, 0x03460f23; - R6.H = R7.L >>> 0x1f (S); - checkreg R6, 0x1e467fff; - checkreg ASTAT, (0x04600000 | _VS | _AV1S | _AC0 | _AQ | _CC | _AC0_COPY); - - dmm32 ASTAT, (0x40704010 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - imm32 R3, 0xfa2cee19; - imm32 R5, 0xfa2cee17; - R3.L = R5.H >>> 0xd (S); - checkreg R3, 0xfa2cffff; - checkreg ASTAT, (0x40704010 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x20308c90 | _VS | _AV1S | _AV0S | _CC | _AN); - imm32 R2, 0xd4b70c2f; - imm32 R5, 0x0279838b; - R5.H = R2.H >>> 0x1f (S); - checkreg R5, 0xa96e838b; - checkreg ASTAT, (0x20308c90 | _VS | _AV1S | _AV0S | _CC | _AN); - - dmm32 ASTAT, (0x10a08690 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - imm32 R4, 0x5cae64fc; - imm32 R6, 0x288e1461; - R4.H = R6.L >>> 0x1e (S); - checkreg R4, 0x518464fc; - checkreg ASTAT, (0x10a08690 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY); - - dmm32 ASTAT, (0x48908010 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC); - imm32 R1, 0x4f8f004a; - imm32 R5, 0x7fff70c1; - R5.L = R1.L >>> 0x1e (S); - checkreg R5, 0x7fff0128; - checkreg ASTAT, (0x48908010 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC); - - dmm32 ASTAT, (0x00f00490 | _VS | _AV0S | _AV0 | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A0.w, 0x32b127c8; - dmm32 A0.x, 0x0000001a; - A0 = A0 >>> 0x6; - checkreg A0.w, 0x68cac49f; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x00f00490 | _VS | _AV0S | _AQ | _CC | _AC0_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/random_0019.S b/sim/testsuite/sim/bfin/random_0019.S deleted file mode 100644 index 2da09c4..0000000 --- a/sim/testsuite/sim/bfin/random_0019.S +++ /dev/null @@ -1,216 +0,0 @@ -# Test a few (W32) corner cases -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x68b0ca90 | _VS | _AV1S | _AV0S | _CC | _AC0_COPY | _AN | _AZ); - dmm32 A1.w, 0x70da33ff; - dmm32 A1.x, 0x0000000f; - imm32 R0, 0x5e29f819; - imm32 R1, 0x3f59520b; - A1 += R0.L * R1.L (M, W32); - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x68b0ca90 | _VS | _AV1S | _AV1 | _AV0S | _CC | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x18300c10 | _VS | _AV1S | _AN); - dmm32 A0.w, 0x1096b1c1; - dmm32 A0.x, 0xfffffff1; - imm32 R6, 0x3a0178ee; - imm32 R7, 0x17c95e45; - A0 -= R6.L * R7.L (W32); - checkreg A0.w, 0x80000000; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x18300c10 | _VS | _AV1S | _AV0S | _AV0 | _AN); - - dmm32 ASTAT, (0x68508800 | _VS | _AV1S | _AV0S | _CC | _AZ); - dmm32 A0.w, 0x30c8f917; - dmm32 A0.x, 0xffffffc8; - imm32 R3, 0x7ad1091c; - imm32 R4, 0x80002874; - A0 -= R3.L * R4.L (W32); - checkreg A0.w, 0x80000000; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x68508800 | _VS | _AV1S | _AV0S | _AV0 | _CC | _AZ); - - dmm32 ASTAT, (0x58708e90 | _VS | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY); - dmm32 A0.w, 0x13de4c3d; - dmm32 A0.x, 0xffffffa5; - imm32 R0, 0xf70f956f; - imm32 R2, 0xf837e08c; - A0 -= R0.L * R2.H (W32); - checkreg A0.w, 0x80000000; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x58708e90 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY); - - dmm32 ASTAT, (0x70800280 | _VS | _AV1S | _AC1 | _AQ | _CC | _AC0_COPY); - dmm32 A0.w, 0x80140410; - dmm32 A0.x, 0x00000000; - imm32 R1, 0x028b09a4; - imm32 R4, 0x00007ffc; - A0 += R4.L * R1.H (W32); - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x70800280 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY); - - dmm32 ASTAT, (0x0060c610 | _VS | _AC1 | _AC0 | _AC0_COPY | _AN | _AZ); - dmm32 A1.w, 0x1794b937; - dmm32 A1.x, 0xfffffff5; - imm32 R6, 0x008e1c0d; - A1 -= R6.L * R6.L (W32); - checkreg A1.w, 0x80000000; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x0060c610 | _VS | _AV1S | _AV1 | _AC1 | _AC0 | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x2c600410 | _VS | _AV0S | _AC1 | _CC | _AN); - dmm32 A1.w, 0x2d03ef79; - dmm32 A1.x, 0x00000079; - imm32 R5, 0x15d1b500; - imm32 R6, 0xf7962b39; - A1 += R6.L * R5.H (W32); - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x2c600410 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _CC | _AN); - - dmm32 ASTAT, (0x5cf04e10 | _VS | _AV0S | _AC1 | _CC | _AC0_COPY); - dmm32 A0.w, 0x4d50b3f0; - dmm32 A0.x, 0xfffffffc; - imm32 R4, 0x6671002a; - imm32 R7, 0x00288000; - A0 += R4.L * R7.L (W32); - checkreg A0.w, 0x80000000; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x5cf04e10 | _VS | _AV0S | _AV0 | _AC1 | _CC | _AC0_COPY); - - - dmm32 ASTAT, (0x28908000 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AN); - dmm32 A1.w, 0xc94e99f1; - dmm32 A1.x, 0x00000021; - imm32 R4, 0x7fff52b7; - imm32 R7, 0x3ebb26c6; - A1 += R7.L * R4.L (M, W32); - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x28908000 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x34708a00 | _VS | _AV0S | _AQ | _CC | _AC0_COPY); - dmm32 A1.w, 0xf61f316d; - dmm32 A1.x, 0x00000061; - imm32 R1, 0x86f0ffff; - imm32 R3, 0x791048c5; - A1 += R1.L * R3.L (M, W32); - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x34708a00 | _VS | _AV1S | _AV1 | _AV0S | _AQ | _CC | _AC0_COPY); - - dmm32 ASTAT, (0x5020c280 | _VS | _V | _AC1 | _AC0 | _V_COPY); - dmm32 A1.w, 0x8700591f; - dmm32 A1.x, 0x00000007; - imm32 R2, 0x145b00b1; - imm32 R3, 0x7fffffff; - A1 -= R3.L * R2.H (M, W32); - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x5020c280 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _V_COPY); - - dmm32 ASTAT, (0x00000290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); - dmm32 A0.w, 0xfe84e1ec; - dmm32 A0.x, 0xffffffff; - imm32 R1, 0x07e73e7b; - imm32 R3, 0x00033e7b; - A0 -= R3.L * R1.H (W32); - checkreg A0.w, 0xfaa965f2; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x00000290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x78204a80 | _VS | _AV1S | _CC | _AN); - dmm32 A0.w, 0xca398210; - dmm32 A0.x, 0xffffffff; - imm32 R3, 0xffff0000; - imm32 R7, 0x00000000; - A0 += R7.L * R3.L (W32); - checkreg ASTAT, (0x78204a80 | _VS | _AV1S | _CC | _AN); - - dmm32 ASTAT, (0x04208890 | _VS | _AC1 | _AC0_COPY); - dmm32 A0.w, 0x224cbaee; - dmm32 A0.x, 0x00000000; - imm32 R3, 0x3db86584; - imm32 R6, 0xdb505ed8; - A0 -= R6.L * R3.H (W32); - checkreg A0.w, 0xf491746e; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x04208890 | _VS | _AC1 | _AC0_COPY); - - dmm32 ASTAT, (0x3c908600 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY); - dmm32 A0.w, 0x03f7c0ec; - dmm32 A0.x, 0x00000000; - imm32 R1, 0x1c25c7b4; - imm32 R5, 0x3f7da612; - A0 -= R5.L * R1.L (W32); - checkreg A0.w, 0xdc6a3b9c; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x3c908600 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY); - - dmm32 ASTAT, (0x7cb08680 | _VS | _AQ | _CC | _AN); - dmm32 A0.w, 0xdc7c243c; - dmm32 A0.x, 0xffffffff; - imm32 R0, 0xe2ccef4c; - imm32 R5, 0x7fff8000; - A0 += R5.L * R0.L (W32); - checkreg A0.w, 0xed30243c; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x7cb08680 | _VS | _AQ | _CC | _AN); - - dmm32 ASTAT, (0x78f00080 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AN); - dmm32 A0.w, 0x39180f38; - dmm32 A0.x, 0x00000000; - imm32 R4, 0x01308ac1; - imm32 R6, 0x7ffff8fd; - A0 = R6.L * R4.H (W32); - checkreg A0.w, 0xffef58e0; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x78f00080 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x7050c090 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0x010909b0; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x80000000; - imm32 R6, 0x6ad06150; - A1 = R6.L * R0.H (W32); - checkreg A1.w, 0x9eb00000; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x7050c090 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x68c04c10 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AN); - dmm32 A0.w, 0x43687862; - dmm32 A0.x, 0x00000000; - imm32 R2, 0xff278000; - imm32 R4, 0x0000436a; - A0 += R2.L * R4.L (W32); - checkreg A0.w, 0xfffe7862; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x68c04c10 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x74a00200 | _AV1 | _AV0S | _AV0 | _AC1 | _V_COPY | _AC0_COPY | _AN | _AZ); - dmm32 A1.w, 0x64c15e6b; - dmm32 A1.x, 0xffffff87; - imm32 R4, 0x30b3e20d; - imm32 R7, 0x4a562069; - A1 = R4.L * R7.H (M, W32); - checkreg A1.w, 0xf74db25e; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x74a00200 | _AV0S | _AV0 | _AC1 | _V_COPY | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x70f08410 | _AV0 | _AC1 | _AC0_COPY | _AN | _AZ); - dmm32 A0.w, 0x5f011b0d; - dmm32 A0.x, 0xffffff86; - imm32 R3, 0x21f93a90; - imm32 R4, 0x1c82d429; - A0 = R3.H * R4.L (W32); - checkreg A0.w, 0xf45d49c2; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x70f08410 | _AC1 | _AC0_COPY | _AN | _AZ); - - pass diff --git a/sim/testsuite/sim/bfin/random_0020.S b/sim/testsuite/sim/bfin/random_0020.S deleted file mode 100644 index d140fb1..0000000 --- a/sim/testsuite/sim/bfin/random_0020.S +++ /dev/null @@ -1,434 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x0cb08810 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); - dmm32 A1.w, 0xfcdbede4; - dmm32 A1.x, 0xffffffff; - imm32 R5, 0x14c5c1c7; - imm32 R7, 0x006a5040; - R5 = (A1 += R7.L * R7.H) (M, IU); - checkreg R5, 0xfcfd2864; - checkreg A1.w, 0xfcfd2864; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x0cb08810 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); - - dmm32 ASTAT, (0x6c508a90 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); - dmm32 A1.w, 0x0bcd165c; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x439a7ef1; - imm32 R3, 0x47670015; - imm32 R6, 0x00008000; - R3 = (A1 += R6.L * R0.L) (M, IU); - checkreg R3, 0xcc54965c; - checkreg A1.w, 0xcc54965c; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x6c508a90 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY); - - dmm32 ASTAT, (0x38900480 | _VS | _AV0S | _AN); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R1, 0x8000ffff; - imm32 R3, 0x0000ffff; - imm32 R6, 0xcb2cf810; - R3 = (A1 += R6.L * R1.L) (M, IU); - checkreg R3, 0xf81007f0; - checkreg A1.w, 0xf81007f0; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x38900480 | _VS | _AV0S | _AN); - - dmm32 ASTAT, (0x20100610 | _VS | _AC1 | _AQ | _AN); - dmm32 A1.w, 0x36491cf0; - dmm32 A1.x, 0x00000000; - imm32 R1, 0x10771108; - imm32 R2, 0x7fb14fe2; - imm32 R7, 0x3649ffff; - R1 = (A1 = R7.L * R2.H) (M, IU); - checkreg R1, 0xffff804f; - checkreg A1.w, 0xffff804f; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x20100610 | _VS | _AC1 | _AQ | _AN); - - dmm32 ASTAT, (0x6c304400 | _VS | _AV1S | _AC1 | _AQ); - dmm32 A1.w, 0xd831c3b7; - dmm32 A1.x, 0xffffffff; - imm32 R3, 0x3a98144b; - imm32 R7, 0xd831c3b7; - R7 = (A1 -= R3.L * R3.H) (M, IU); - checkreg R7, 0xd38cb92f; - checkreg A1.w, 0xd38cb92f; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x6c304400 | _VS | _AV1S | _AC1 | _AQ); - - dmm32 ASTAT, (0x3c50c810 | _VS | _AV1S | _AN | _AZ); - dmm32 A0.w, 0x13cd1c6c; - dmm32 A0.x, 0x00000000; - imm32 R2, 0x4000e935; - imm32 R3, 0xe0b313cd; - R3.L = (A0 += R3.H * R2.L) (IU); - checkreg R3, 0xe0b3ffff; - checkreg A0.w, 0xe07e8c7b; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x3c50c810 | _VS | _V | _AV1S | _V_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x7c900280 | _AV1S | _AV0S | _AC1 | _AQ); - dmm32 A0.w, 0x057e5874; - dmm32 A0.x, 0x00000000; - imm32 R0, 0x1c0af520; - imm32 R6, 0x7caea317; - imm32 R7, 0x107e8ce4; - R6.L = (A0 += R7.L * R0.L) (IU); - checkreg R6, 0x7caeffff; - checkreg A0.w, 0x8c6628f4; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x7c900280 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x6cf04090 | _VS | _AV1S | _AV0S | _AC1 | _AZ); - dmm32 A0.w, 0xdc7d7b8c; - dmm32 A0.x, 0x00000000; - imm32 R0, 0x788e00d2; - imm32 R6, 0x03666070; - R0.L = (A0 -= R6.H * R6.H) (IU); - checkreg R0, 0x788effff; - checkreg A0.w, 0xdc71eee8; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x6cf04090 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AZ); - - dmm32 ASTAT, (0x4cc04c80 | _VS | _CC); - dmm32 A1.w, 0x41620ea7; - dmm32 A1.x, 0x00000057; - imm32 R1, 0xf611262c; - imm32 R3, 0x7fff7fff; - imm32 R4, 0x247ee19c; - R1 = (A1 += R4.L * R3.L) (IU); - checkreg R1, 0xffffffff; - checkreg A1.w, 0xb22f2d0b; - checkreg A1.x, 0x00000057; - checkreg ASTAT, (0x4cc04c80 | _VS | _V | _CC | _V_COPY); - - dmm32 ASTAT, (0x28e04610 | _VS | _AV0S | _AC1 | _AC0 | _AN); - dmm32 A0.w, 0xe1753d16; - dmm32 A0.x, 0xffffffff; - imm32 R0, 0x7fffffff; - imm32 R5, 0x2792ffff; - imm32 R7, 0xffffd6fa; - R7.L = (A0 = R0.L * R5.L) (IU); - checkreg R7, 0xffffffff; - checkreg A0.w, 0xfffe0001; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x28e04610 | _VS | _V | _AV0S | _AC1 | _AC0 | _V_COPY | _AN); - - dmm32 ASTAT, (0x7c900280 | _AV1S | _AV0S | _AC1 | _AQ); - dmm32 A0.w, 0x057e5874; - dmm32 A0.x, 0x00000000; - imm32 R0, 0x1c0af520; - imm32 R6, 0x7caea317; - imm32 R7, 0x107e8ce4; - R6.L = (A0 += R7.L * R0.L) (IU); - checkreg R6, 0x7caeffff; - checkreg A0.w, 0x8c6628f4; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x7c900280 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x00304000 | _VS | _AV1S | _AQ | _AZ); - dmm32 A0.w, 0x615bac86; - dmm32 A0.x, 0x00000000; - imm32 R2, 0x6d2cbec6; - imm32 R3, 0xe09db667; - R3.L = (A0 += R3.H * R2.H) (IU); - checkreg R3, 0xe09dffff; - checkreg A0.w, 0xc1252082; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x00304000 | _VS | _V | _AV1S | _AQ | _V_COPY | _AZ); - - dmm32 ASTAT, (0x5cc00080 | _VS | _AV1S | _AC0 | _CC); - dmm32 A1.w, 0x70d9985a; - dmm32 A1.x, 0xffffffd6; - imm32 R1, 0x8000fdeb; - imm32 R2, 0x20e07e89; - R1.H = (A1 += R2.L * R1.L) (M, IU); - checkreg A1.w, 0xee5b251d; - checkreg A1.x, 0xffffffd6; - checkreg ASTAT, (0x5cc00080 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY); - - dmm32 ASTAT, (0x60e0ce80 | _VS | _AC0 | _AQ | _CC); - dmm32 A1.w, 0x67798cf6; - dmm32 A1.x, 0x00000044; - imm32 R0, 0x00000000; - imm32 R1, 0x00008e16; - imm32 R7, 0x00000000; - R7 = (A1 -= R0.L * R1.L) (M, IU); - checkreg R7, 0x7fffffff; - checkreg A1.w, 0x67798cf6; - checkreg A1.x, 0x00000044; - checkreg ASTAT, (0x60e0ce80 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x00500210 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - dmm32 A1.w, 0x6f47fe74; - dmm32 A1.x, 0x00000022; - imm32 R5, 0x3482aa64; - imm32 R6, 0x48320cd9; - R5.H = (A1 -= R6.L * R5.L) (M, IU); - checkreg R5, 0x7fffaa64; - checkreg A1.w, 0x66badfb0; - checkreg A1.x, 0x00000022; - checkreg ASTAT, (0x00500210 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x60f04890 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AC0_COPY); - dmm32 A1.w, 0x43fdb94f; - dmm32 A1.x, 0xffffff97; - imm32 R1, 0x80000000; - imm32 R7, 0x0f9b234b; - R1.H = (A1 += R7.L * R1.H) (M, IU); - checkreg A1.w, 0x55a3394f; - checkreg A1.x, 0xffffff97; - checkreg ASTAT, (0x60f04890 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x60f0c280 | _V | _AV1S | _AV1 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); - dmm32 A1.w, 0x33205f9e; - dmm32 A1.x, 0xfffffffc; - imm32 R3, 0x39e0545d; - imm32 R6, 0x0e133731; - R3 = (A1 -= R3.L * R6.H) (M, IU); - checkreg R3, 0x80000000; - checkreg A1.w, 0x2e7d06b7; - checkreg A1.x, 0xfffffffc; - checkreg ASTAT, (0x60f0c280 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x6c300490 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0x2a477a36; - dmm32 A1.x, 0xfffffff8; - imm32 R0, 0xff020000; - imm32 R5, 0x00000000; - imm32 R7, 0xffff8000; - R5.H = (A1 -= R0.L * R7.H) (M, IU); - checkreg R5, 0x80000000; - checkreg ASTAT, (0x6c300490 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x1400c210 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AN); - dmm32 A1.w, 0x68033dca; - dmm32 A1.x, 0xffffffff; - imm32 R1, 0x00000000; - imm32 R3, 0x00a36a42; - imm32 R7, 0x3afd7fff; - R3.H = (A1 -= R1.L * R7.H) (M, IU); - checkreg R3, 0x80006a42; - checkreg ASTAT, (0x1400c210 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x00104810 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN); - dmm32 A1.w, 0xeb4e9a1d; - dmm32 A1.x, 0xffffff8c; - imm32 R1, 0xffffec05; - imm32 R5, 0x80000000; - imm32 R6, 0x5ffa604a; - R1.H = (A1 += R6.L * R5.H) (M, IU); - checkreg R1, 0x8000ec05; - checkreg A1.w, 0x1b739a1d; - checkreg A1.x, 0xffffff8d; - checkreg ASTAT, (0x00104810 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x48600280 | _VS | _AV1S | _AV0 | _AC1 | _CC | _AC0_COPY); - dmm32 A1.w, 0x54463e5f; - dmm32 A1.x, 0xffffff94; - imm32 R1, 0x2e0d6820; - imm32 R4, 0x37855c3d; - imm32 R6, 0x7b3ca7a0; - R6.H = (A1 += R4.L * R1.L) (M, IU); - checkreg R6, 0x8000a7a0; - checkreg A1.w, 0x79ca8dff; - checkreg A1.x, 0xffffff94; - checkreg ASTAT, (0x48600280 | _VS | _V | _AV1S | _AV0 | _AC1 | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x3c008480 | _VS | _AV1S | _AC1 | _AC0 | _CC); - dmm32 A0.w, 0xcdff712a; - dmm32 A0.x, 0xffffffff; - imm32 R0, 0x2f3dfc31; - imm32 R2, 0x1b1a4b4c; - imm32 R6, 0x7cbed409; - R2 = (A0 += R6.H * R0.L) (IU); - checkreg R2, 0xffffffff; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x3c008480 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY); - - dmm32 ASTAT, (0x4ce0ce80 | _VS | _AC1 | _AC0 | _CC); - dmm32 A0.w, 0xfefe27a4; - dmm32 A0.x, 0xffffffff; - imm32 R0, 0x08270055; - imm32 R1, 0x0000ffc2; - imm32 R6, 0x5ca7213b; - R6.L = (A0 += R1.L * R0.H) (IU); - checkreg R6, 0x5ca7ffff; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x4ce0ce80 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY); - - dmm32 ASTAT, (0x7020ca10 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY); - dmm32 A0.w, 0xec60b144; - dmm32 A0.x, 0xffffffff; - imm32 R0, 0x147e9190; - imm32 R1, 0x2b813e9e; - imm32 R4, 0xab65ffff; - R0 = (A0 += R1.L * R4.H) (IU); - checkreg R0, 0xffffffff; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x7020ca10 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x28e08210 | _VS | _AQ | _AN); - dmm32 A0.w, 0xe650ec98; - dmm32 A0.x, 0xffffffff; - imm32 R1, 0xcca1b6ef; - imm32 R2, 0xd762b783; - imm32 R3, 0xef34e465; - R2 = (A0 += R3.L * R1.H) (IU); - checkreg R2, 0xffffffff; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x28e08210 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x58904e00 | _VS | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); - dmm32 A0.w, 0xb84b0e88; - dmm32 A0.x, 0xffffffff; - imm32 R0, 0x8367ffff; - imm32 R1, 0xb6a1af0a; - R1.L = (A0 += R0.H * R1.H) (IU); - checkreg R1, 0xb6a1ffff; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x58904e00 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x30900810 | _VS | _AV1S | _AC1 | _AQ | _CC); - dmm32 A1.w, 0xd0762eff; - dmm32 A1.x, 0xffffffff; - imm32 R0, 0x00000000; - imm32 R1, 0x1d9b7fff; - imm32 R3, 0xf32bf32b; - R0.H = (A1 += R1.L * R3.L) (M, IU); - checkreg R0, 0x7fff0000; - checkreg A1.w, 0x4a0abbd4; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x30900810 | _VS | _V | _AV1S | _AC1 | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x74408290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY); - dmm32 A1.w, 0xf1008000; - dmm32 A1.x, 0xffffffff; - imm32 R3, 0x0bb78001; - imm32 R5, 0x0be78000; - imm32 R7, 0x17cd9a40; - R3.H = (A1 += R7.L * R5.L) (M, IU); - checkreg R3, 0x80008001; - checkreg A1.w, 0xbe208000; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x74408290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x40900490 | _VS | _AV1S); - dmm32 A1.w, 0xa9d97d12; - dmm32 A1.x, 0xffffffff; - imm32 R0, 0x4e01ffff; - imm32 R3, 0x12abdd35; - imm32 R7, 0xa9d966d6; - R7.H = (A1 += R0.L * R3.L) (M, IU); - checkreg R7, 0x800066d6; - checkreg A1.w, 0xa9d89fdd; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x40900490 | _VS | _V | _AV1S | _V_COPY); - - dmm32 ASTAT, (0x20a04290 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN); - dmm32 A1.w, 0xe552d880; - dmm32 A1.x, 0xffffffff; - imm32 R3, 0xfe6bf901; - imm32 R5, 0xfae40000; - imm32 R6, 0x3917f106; - R5.H = (A1 += R6.L * R3.H) (M, IU); - checkreg R5, 0x80000000; - checkreg A1.w, 0xd6708a02; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x20a04290 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x2050c490 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0xfcd2b056; - dmm32 A1.x, 0xffffffff; - imm32 R2, 0xff36c118; - imm32 R4, 0xfffe0001; - imm32 R7, 0x7fff00f4; - R7.H = (A1 += R2.L * R4.H) (M, IU); - checkreg R7, 0x800000f4; - checkreg A1.w, 0xbdeb2e26; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x2050c490 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x30708290 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ); - dmm32 A1.w, 0x391f1bbc; - dmm32 A1.x, 0x0000004d; - imm32 R3, 0xae387ec2; - imm32 R4, 0x7fff99ff; - imm32 R5, 0x46730cf4; - R5 = (A1 += R4.L * R3.H) (M, IU); - checkreg R5, 0x7fffffff; - checkreg A1.w, 0xf3b41d84; - checkreg A1.x, 0x0000004c; - checkreg ASTAT, (0x30708290 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x60d00200 | _VS | _AV1S | _CC); - dmm32 A1.w, 0x002b5780; - dmm32 A1.x, 0x00000000; - imm32 R1, 0xa07dffff; - imm32 R2, 0xf90db994; - imm32 R4, 0x46150060; - R2.H = (A1 -= R1.L * R4.L) (M, IU); - checkreg R2, 0x7fffb994; - checkreg A1.w, 0x002b57e0; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x60d00200 | _VS | _V | _AV1S | _CC | _V_COPY); - - dmm32 ASTAT, (0x5c600a80 | _VS | _V | _AV1S | _AV1 | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0x52768086; - dmm32 A1.x, 0x00000035; - imm32 R2, 0x1e89d049; - imm32 R6, 0x5312dd14; - imm32 R7, 0x02e3d1f4; - R7 = (A1 += R2.L * R6.L) (M, IU); - checkreg R7, 0x7fffffff; - checkreg A1.w, 0x2941cb3a; - checkreg A1.x, 0x00000035; - checkreg ASTAT, (0x5c600a80 | _VS | _V | _AV1S | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x60908080 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ); - dmm32 A1.w, 0x00005d96; - dmm32 A1.x, 0x00000000; - imm32 R1, 0x00006828; - imm32 R5, 0xfffe5480; - imm32 R7, 0x40000009; - R5 = (A1 -= R1.L * R7.H) (M, IU); - checkreg R5, 0xe5f65d96; - checkreg A1.w, 0xe5f65d96; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x60908080 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x3cb08080 | _VS | _AC1 | _CC | _AC0_COPY | _AZ); - dmm32 A1.w, 0x8b063fca; - dmm32 A1.x, 0xffffffa2; - imm32 R3, 0x5f5b566b; - imm32 R4, 0x800022e6; - imm32 R5, 0x741acdad; - R3 = (A1 += R5.L * R4.L) (M, IU); - checkreg R3, 0x80000000; - checkreg A1.w, 0x842a0338; - checkreg A1.x, 0xffffffa2; - checkreg ASTAT, (0x3cb08080 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x60d08a00 | _VS | _AC0 | _AQ | _AN); - dmm32 A1.w, 0x54eebd9e; - dmm32 A1.x, 0x00000000; - imm32 R5, 0x05fa881c; - imm32 R7, 0xb0728448; - R5 = (A1 -= R7.L * R5.L) (M, IU); - checkreg R5, 0x7fffffff; - checkreg A1.w, 0x96b605be; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x60d08a00 | _VS | _V | _AC0 | _AQ | _V_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0021.S b/sim/testsuite/sim/bfin/random_0021.S deleted file mode 100644 index 2497a44..0000000 --- a/sim/testsuite/sim/bfin/random_0021.S +++ /dev/null @@ -1,45 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x5c604280 | _VS | _AV1S | _AV0S); - imm32 R3, 0xfe0103fe; - imm32 R5, 0x1e53cdd8; - R3.H = R5.L * R3.H (M, IU); - checkreg R3, 0x800003fe; - checkreg ASTAT, (0x5c604280 | _VS | _V | _AV1S | _AV0S | _V_COPY); - - dmm32 ASTAT, (0x74a04c00 | _VS | _AV1S | _CC | _AN); - imm32 R4, 0xfffeffff; - imm32 R5, 0x174e174e; - R5.H = R4.L * R5.H (M, IU); - checkreg R5, 0xe8b2174e; - checkreg ASTAT, (0x74a04c00 | _VS | _AV1S | _CC | _AN); - - dmm32 ASTAT, (0x34308890 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AN); - imm32 R3, 0x7fffffff; - imm32 R4, 0x077b8000; - imm32 R7, 0x03bd03bd; - R3.H = R4.L * R7.H (M, IU); - checkreg R3, 0x8000ffff; - checkreg ASTAT, (0x34308890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x58700a90 | _VS | _AV1S | _AC1 | _AQ | _CC | _AN); - imm32 R1, 0x58978212; - imm32 R3, 0x62b5775a; - imm32 R6, 0x4c9c9ee3; - R6.H = R1.L * R3.L (M, IU); - checkreg R6, 0x80009ee3; - checkreg ASTAT, (0x58700a90 | _VS | _V | _AV1S | _AC1 | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x40204e00 | _VS | _AV1S | _AV0S | _CC | _AN); - imm32 R3, 0x297fee00; - imm32 R5, 0x79aa9d21; - imm32 R6, 0xfffe7484; - R6.H = R5.L * R3.L (M, IU); - checkreg R6, 0x80007484; - checkreg ASTAT, (0x40204e00 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0022.S b/sim/testsuite/sim/bfin/random_0022.S deleted file mode 100644 index fce2803..0000000 --- a/sim/testsuite/sim/bfin/random_0022.S +++ /dev/null @@ -1,212 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x2090c600 | _VS | _AC1 | _AQ | _CC | _AN); - dmm32 A0.w, 0xf041e418; - dmm32 A0.x, 0xffffffff; - imm32 R4, 0x51296cc2; - imm32 R7, 0xca05cb74; - R4.L = (A0 += R7.H * R4.L) (TFU); - checkreg R4, 0x5129ffff; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x2090c600 | _VS | _V | _AV0S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x68508090 | _VS | _AV0S | _AC1 | _AC0_COPY); - dmm32 A1.w, 0xf934c2ea; - dmm32 A1.x, 0xffffffff; - imm32 R0, 0x4c8c85a2; - imm32 R1, 0x13507fff; - imm32 R7, 0x1bd0df6a; - R0.H = (A1 += R7.L * R1.L) (TFU); - checkreg R0, 0xffff85a2; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x68508090 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x54e0c200 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY); - dmm32 A0.w, 0xed4a5c88; - dmm32 A0.x, 0xffffffff; - imm32 R1, 0x1332a428; - imm32 R4, 0x59fd2452; - imm32 R6, 0x001fffc3; - R4.L = (A0 += R1.H * R6.L) (TFU); - checkreg R4, 0x59fdffff; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x54e0c200 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x70500000 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN); - dmm32 A0.w, 0xb959adf4; - dmm32 A0.x, 0xffffffff; - imm32 R0, 0xffc20000; - imm32 R4, 0x9b83ffff; - R0.L = (A0 += R4.L * R4.H) (TFU); - checkreg R0, 0xffc2ffff; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x70500000 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x58f04890 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); - dmm32 A0.w, 0xfd1277cc; - dmm32 A0.x, 0xffffffff; - imm32 R5, 0xfffdffe2; - imm32 R7, 0x1a9bcac8; - R5.L = (A0 += R5.H * R7.L) (TFU); - checkreg R5, 0xfffdffff; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x58f04890 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x2840ce90 | _VS | _AV0S | _AC1 | _AC0 | _AC0_COPY); - dmm32 A1.w, 0x1543f138; - dmm32 A1.x, 0xffffffce; - imm32 R3, 0xf4620000; - imm32 R4, 0x80008000; - imm32 R7, 0x0d156000; - R4.H = (A1 -= R3.L * R7.L) (M, TFU); - checkreg R4, 0x80008000; - checkreg A1.w, 0x1543f138; - checkreg A1.x, 0xffffffce; - checkreg ASTAT, (0x2840ce90 | _VS | _V | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x04000c90 | _AV0S | _AC0 | _AC0_COPY | _AN); - dmm32 A1.w, 0x7c7b42a9; - dmm32 A1.x, 0x00000027; - imm32 R2, 0x28454c31; - imm32 R5, 0xf220f1b0; - imm32 R6, 0x257ab18b; - R2.H = (A1 -= R5.L * R6.L) (M, TFU); - checkreg R2, 0x7fff4c31; - checkreg A1.w, 0x86685819; - checkreg A1.x, 0x00000027; - checkreg ASTAT, (0x04000c90 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x6810ce80 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x00008000; - imm32 R6, 0x5857bcbe; - R6.H = (A1 = R6.L * R0.L) (M, TFU); - checkreg R6, 0xde5fbcbe; - checkreg A1.w, 0xde5f0000; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x6810ce80 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x78c00c80 | _VS | _V | _AC0 | _V_COPY | _AN); - dmm32 A1.w, 0x63391186; - dmm32 A1.x, 0x0000005e; - imm32 R2, 0x34a8b6ef; - imm32 R7, 0x7c8142e2; - R7.H = (A1 = R2.L * R2.H) (M, TFU); - checkreg R7, 0xf0f842e2; - checkreg A1.w, 0xf0f898d8; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x78c00c80 | _VS | _AC0 | _AN); - - dmm32 ASTAT, (0x70704410 | _VS | _V | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - dmm32 A1.w, 0x3fff0001; - dmm32 A1.x, 0x00000000; - imm32 R0, 0xffffffff; - imm32 R7, 0x80007fff; - R7.H = (A1 = R0.L * R7.L) (M, TFU); - checkreg R7, 0xffff7fff; - checkreg A1.w, 0xffff8001; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x70704410 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); - - dmm32 ASTAT, (0x00b08610 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0xe75e6c55; - dmm32 A1.x, 0xffffffff; - imm32 R1, 0x5073b60d; - imm32 R3, 0x1c5eecaf; - R1.H = (A1 = R3.L * R3.H) (M, TFU); - checkreg R1, 0xfddcb60d; - checkreg A1.w, 0xfddc0c42; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x00b08610 | _VS | _AV1S | _AV0S | _AV0 | _AQ | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x00304690 | _AV1 | _AV0S | _AV0 | _AQ | _AZ); - dmm32 A1.w, 0x2ef1b58e; - dmm32 A1.x, 0xffffffd7; - imm32 R3, 0x37807856; - imm32 R4, 0x2cd7d02c; - imm32 R5, 0x4435ba51; - R4.H = (A1 -= R3.L * R5.L) (M, TFU); - checkreg R4, 0x8000d02c; - checkreg A1.w, 0xd75d2658; - checkreg A1.x, 0xffffffd6; - checkreg ASTAT, (0x00304690 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AZ); - - dmm32 ASTAT, (0x74c0c600 | _VS | _AV1 | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0x4325067d; - dmm32 A1.x, 0xffffffee; - imm32 R0, 0x35ca7288; - imm32 R5, 0x5ec6e257; - R0.H = (A1 += R0.L * R5.H) (M, TFU); - checkreg R0, 0x80007288; - checkreg A1.w, 0x6d8b8bad; - checkreg A1.x, 0xffffffee; - checkreg ASTAT, (0x74c0c600 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x50704690 | _VS | _AQ); - dmm32 A1.w, 0xd0cea2a8; - dmm32 A1.x, 0xffffffff; - imm32 R0, 0x11b4e24e; - imm32 R2, 0xecd6793c; - imm32 R7, 0x329c2dd6; - R0.H = (A1 -= R7.L * R2.L) (M, TFU); - checkreg R0, 0xbb19e24e; - checkreg A1.w, 0xbb19be80; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x50704690 | _VS | _AQ); - - dmm32 ASTAT, (0x10d08000 | _VS | _AC1 | _AN); - dmm32 A1.w, 0x32dd86a1; - dmm32 A1.x, 0xffffffd7; - imm32 R1, 0xb2310000; - imm32 R3, 0xd63992d2; - imm32 R5, 0x2b93b27f; - R5.H = (A1 += R3.L * R1.L) (M, TFU); - checkreg R5, 0x8000b27f; - checkreg A1.w, 0x32dd86a1; - checkreg A1.x, 0xffffffd7; - checkreg ASTAT, (0x10d08000 | _VS | _V | _AC1 | _V_COPY | _AN); - - dmm32 ASTAT, (0x3010c600 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY | _AC0_COPY); - dmm32 A1.w, 0xf99eabd6; - dmm32 A1.x, 0xffffffff; - imm32 R2, 0x0c196618; - imm32 R5, 0x00008000; - imm32 R6, 0x6617ffff; - R5.H = (A1 -= R6.L * R2.L) (M, TFU); - checkreg R5, 0xf99f8000; - checkreg A1.w, 0xf99f11ee; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x3010c600 | _VS | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _AC0_COPY); - - dmm32 ASTAT, (0x30f0ca80 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AN); - dmm32 A0.w, 0x74ea7d56; - dmm32 A0.x, 0xffffffff; - imm32 R0, 0x29abffff; - imm32 R2, 0xade1ffff; - imm32 R7, 0x20ada3b8; - R0.L = (A0 += R2.L * R7.L) (TFU); - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x30f0ca80 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AN); - - dmm32 ASTAT, (0x48608210 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AN); - dmm32 A0.w, 0x120f0000; - dmm32 A0.x, 0xffffffff; - imm32 R3, 0xfeacf0c4; - R3.L = (A0 += R3.H * R3.H) (TFU); - checkreg R3, 0xfeacffff; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x48608210 | _VS | _V | _AV1S | _AV0S | _AV0 | _CC | _V_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0023.S b/sim/testsuite/sim/bfin/random_0023.S deleted file mode 100644 index 9dd2d1a..0000000 --- a/sim/testsuite/sim/bfin/random_0023.S +++ /dev/null @@ -1,97 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x60608a90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY); - dmm32 A1.w, 0xf41fbf3f; - dmm32 A1.x, 0x00000000; - imm32 R5, 0xd8d95310; - imm32 R6, 0xd0457fff; - R5.H = (A1 -= R6.L * R6.H) (M, FU); - checkreg R5, 0x7fff5310; - checkreg A1.w, 0x8bfe0f84; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x60608a90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x54b0ca90 | _VS | _AV1S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0xf88288c8; - dmm32 A1.x, 0xffffffff; - imm32 R0, 0xfffe6736; - imm32 R2, 0x8000f882; - imm32 R3, 0xffff8391; - R0.H = (A1 += R3.L * R2.L) (M, FU); - checkreg R0, 0x80006736; - checkreg A1.w, 0x7fb7d06a; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x54b0ca90 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x1c500480 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0x9083dd08; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x00000000; - imm32 R4, 0x00002492; - R4.H = (A1 += R4.L * R0.H) (M, FU); - checkreg R4, 0x7fff2492; - checkreg ASTAT, (0x1c500480 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x7c00c810 | _AV1S | _AC1 | _AC0); - dmm32 A1.w, 0x69e86d3f; - dmm32 A1.x, 0xffffffc2; - imm32 R1, 0x64f42c5b; - imm32 R3, 0x4128529d; - R3 = (A1 -= R3.L * R1.L) (M, FU); - checkreg R3, 0x80000000; - checkreg A1.w, 0x5b981370; - checkreg A1.x, 0xffffffc2; - checkreg ASTAT, (0x7c00c810 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY); - - dmm32 ASTAT, (0x5cc0c480 | _VS | _AQ | _CC); - dmm32 A1.w, 0x34bbe964; - dmm32 A1.x, 0x00000036; - imm32 R1, 0x7fffffff; - imm32 R5, 0x7fff427e; - A1 -= R5.L * R1.L (M, FU); - checkreg A1.w, 0xf23e2be2; - checkreg A1.x, 0x00000035; - checkreg ASTAT, (0x5cc0c480 | _VS | _AQ | _CC); - -# here the result is zero, and the _V bit is set - dmm32 ASTAT, 0x0; - dmm32 A0.w, 0x00008492; - dmm32 A0.x, 0x00000000; - imm32 R2, 0x7fff0002; - imm32 R3, 0xfa6e8492; - imm32 R6, 0xffff0002; - R6 = (A0 -= R3.L * R2.L) (FU); - checkreg R6, 0x00000000; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, ( _VS | _V | _AV0S | _AV0 | _V_COPY); - -# here the result is zero, and the _V bit is not set - dmm32 ASTAT, (_V | _V_COPY); - dmm32 A0.w, 0x1fffc000; - dmm32 A0.x, 0x00000000; - imm32 R0, 0x80004000; - imm32 R4, 0x1fffffff; - imm32 R6, 0x80000000; - R4.L = (A0 -= R0.L * R6.H) (FU); - checkreg R4, 0x1fff0000; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (_AV0S | _AV0); - - dmm32 ASTAT, (0x0c108610 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); - dmm32 A0.w, 0x0000eaf0; - dmm32 A0.x, 0x00000000; - imm32 R1, 0x00010000; - imm32 R6, 0xfbf10001; - R1.L = (A0 -= R6.H * R1.H) (FU); - checkreg R1, 0x00010000; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x0c108610 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0024.S b/sim/testsuite/sim/bfin/random_0024.S deleted file mode 100644 index dab8880..0000000 --- a/sim/testsuite/sim/bfin/random_0024.S +++ /dev/null @@ -1,264 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x3ce00800 | _VS | _AV1S | _AV0S | _AQ | _AZ); - imm32 R2, 0x00000000; - imm32 R4, 0x00000000; - imm32 R7, 0x00000000; - R2 = ASHIFT R7 BY R4.L (S); - checkreg ASTAT, (0x3ce00800 | _VS | _AV1S | _AV0S | _AQ | _AZ); - checkreg R2, 0x00000000; - checkreg R4, 0x00000000; - checkreg R7, 0x00000000; - - dmm32 ASTAT, (0x7c104680 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ); - imm32 R7, 0x00000000; - R7 = R7 << 0xe (S); - checkreg R7, 0x00000000; - checkreg ASTAT, (0x7c104680 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x10d08690 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); - imm32 R2, 0x0000ffff; - imm32 R5, 0x00000000; - R2 = R5 << 0x1a (S); - checkreg R2, 0x00000000; - checkreg ASTAT, (0x10d08690 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x30f08e90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); - imm32 R6, 0x00000000; - R6 = ASHIFT R6 BY R6.L (S); - checkreg ASTAT, (0x30f08e90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); - checkreg R6, 0x00000000; - - dmm32 ASTAT, (0x4060c800 | _VS | _AV0S | _AC1 | _CC | _AZ); - imm32 R5, 0x00000000; - imm32 R7, 0x00000000; - R5 = R7 << 0x15 (S); - checkreg ASTAT, (0x4060c800 | _VS | _AV0S | _AC1 | _CC | _AZ); - checkreg R5, 0x00000000; - checkreg R7, 0x00000000; - - dmm32 ASTAT, (0x78604a10 | _VS | _AN); - imm32 R1, 0x00000000; - imm32 R4, 0xe1a88000; - R4 = R1 << 0xb (S); - checkreg R4, 0x00000000; - checkreg ASTAT, (0x78604a10 | _VS | _AZ); - - dmm32 ASTAT, (0x64304800 | _VS | _AV1S | _AV0S | _AC0_COPY); - imm32 R2, 0x00000000; - imm32 R7, 0x00000000; - R7 = R2 << 0xa (S); - checkreg ASTAT, (0x64304800 | _VS | _AV1S | _AV0S | _AC0_COPY | _AZ); - checkreg R2, 0x00000000; - checkreg R7, 0x00000000; - - dmm32 ASTAT, (0x68f0c280 | _VS | _AC1 | _AC0_COPY | _AN); - imm32 R2, 0x00000000; - imm32 R5, 0x0000f74a; - R5 = R2 << 0x10 (S); - checkreg R5, 0x00000000; - checkreg ASTAT, (0x68f0c280 | _VS | _AC1 | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x54200c80 | _VS | _AV1S | _AV0S | _AQ); - imm32 R1, 0x00000000; - imm32 R2, 0x00000000; - R2 = R1 << 0xa (S); - checkreg ASTAT, (0x54200c80 | _VS | _AV1S | _AV0S | _AQ | _AZ); - checkreg R1, 0x00000000; - checkreg R2, 0x00000000; - - dmm32 ASTAT, (0x20300a80 | _VS | _AV1S | _CC | _AZ); - imm32 R2, 0x00000000; - imm32 R7, 0x00000000; - R7 = R2 << 0x8 (S); - checkreg ASTAT, (0x20300a80 | _VS | _AV1S | _CC | _AZ); - checkreg R2, 0x00000000; - checkreg R7, 0x00000000; - - dmm32 ASTAT, (0x14408e10 | _VS | _AV0S | _AQ | _CC | _AZ); - imm32 R4, 0x0000007f; - imm32 R6, 0x00000000; - R4 = R6 << 0x3 (S); - checkreg R4, 0x00000000; - checkreg ASTAT, (0x14408e10 | _VS | _AV0S | _AQ | _CC | _AZ); - - dmm32 ASTAT, (0x2850c490 | _VS | _AV1S | _AV0S | _AZ); - imm32 R5, 0x00000000; - imm32 R7, 0xf67f0000; - R7 = ASHIFT R5 BY R7.L (S); - checkreg R7, 0x00000000; - checkreg ASTAT, (0x2850c490 | _VS | _AV1S | _AV0S | _AZ); - - dmm32 ASTAT, (0x24a00400 | _VS | _AV1S | _AC0 | _AC0_COPY | _AN); - imm32 R4, 0x00001e68; - imm32 R6, 0x00000000; - R4 = R6 << 0x8 (S); - checkreg R4, 0x00000000; - checkreg ASTAT, (0x24a00400 | _VS | _AV1S | _AC0 | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x34608e00 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY | _AN); - imm32 R1, 0x00000000; - imm32 R5, 0x272beb60; - R5 = R1 << 0xa (S); - checkreg R5, 0x00000000; - checkreg ASTAT, (0x34608e00 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AZ); - - dmm32 ASTAT, (0x20800c90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AN); - imm32 R3, 0x532993ba; - imm32 R5, 0x00000000; - R3 = R5 << 0x9 (S); - checkreg R3, 0x00000000; - checkreg ASTAT, (0x20800c90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x5430c090 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY); - imm32 R1, 0xb1510802; - imm32 R6, 0x00000000; - R1 = R6 << 0x1e (S); - checkreg R1, 0x00000000; - checkreg ASTAT, (0x5430c090 | _VS | _AV0S | _AC0 | _AQ | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x5cf04c90 | _VS | _AV1S | _AC1 | _AQ | _AC0_COPY); - dmm32 A1.w, 0xf9bc55b7; - dmm32 A1.x, 0x0000002a; - imm32 R0, 0x002d0024; - imm32 R1, 0x16970042; - A1 += R0.L * R1.L; - checkreg A1.w, 0xf9bc6847; - checkreg A1.x, 0x0000002a; - checkreg ASTAT, (0x5cf04c90 | _VS | _AV1S | _AC1 | _AQ | _AC0_COPY); - - dmm32 ASTAT, (0x7c804090 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); - imm32 R5, 0x00000000; - imm32 R7, 0xfe773828; - R7 = R5 << 0x19 (S); - checkreg R7, 0x00000000; - checkreg ASTAT, (0x7c804090 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x30f04e90 | _VS | _AV0S | _AC0 | _AQ); - imm32 R3, 0x00000000; - imm32 R7, 0x00000372; - R7 = R3 << 0x6 (S); - checkreg R7, 0x00000000; - checkreg ASTAT, (0x30f04e90 | _VS | _AV0S | _AC0 | _AQ | _AZ); - - dmm32 ASTAT, (0x04708210 | _VS | _AV1S | _AC0 | _AQ | _AN); - imm32 R5, 0x00000000; - imm32 R7, 0x79b3d220; - R7 = R5 << 0x13 (S); - checkreg R7, 0x00000000; - checkreg ASTAT, (0x04708210 | _VS | _AV1S | _AC0 | _AQ | _AZ); - - dmm32 ASTAT, (0x24e08680 | _VS | _AV0S | _AC1 | _CC | _AZ); - imm32 R0, 0x00000000; - imm32 R6, 0x00000000; - imm32 R7, 0xa820afc0; - R6 = ASHIFT R0 BY R7.L (S); - checkreg ASTAT, (0x24e08680 | _VS | _AV0S | _AC1 | _CC | _AZ); - checkreg R0, 0x00000000; - checkreg R6, 0x00000000; - checkreg R7, 0xa820afc0; - - dmm32 ASTAT, (0x0ca0c090 | _VS | _AQ | _AZ); - imm32 R6, 0x00000000; - imm32 R7, 0x0000001f; - R7 = R6 << 0x14 (S); - checkreg R7, 0x00000000; - checkreg ASTAT, (0x0ca0c090 | _VS | _AQ | _AZ); - - dmm32 ASTAT, (0x20204680 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY); - imm32 R6, 0x00000000; - R6 = R6 << 0x15 (S); - checkreg ASTAT, (0x20204680 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AZ); - checkreg R6, 0x00000000; - - dmm32 ASTAT, (0x14f08c00 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ); - imm32 R2, 0x00000000; - imm32 R6, 0x00007fff; - R6 = R2 << 0x1b (S); - checkreg R6, 0x00000000; - checkreg ASTAT, (0x14f08c00 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x50b08c00 | _VS | _AC1 | _AQ | _CC | _AN); - imm32 R1, 0x00000000; - imm32 R4, 0x0000fffd; - R4 = R1 << 0x9 (S); - checkreg R4, 0x00000000; - checkreg ASTAT, (0x50b08c00 | _VS | _AC1 | _AQ | _CC | _AZ); - - dmm32 ASTAT, (0x1cb04200 | _VS | _AV0S | _AC1 | _CC); - imm32 R0, 0x00000000; - imm32 R2, 0xdeab0000; - R2 = R0 << 0x1e (S); - checkreg R2, 0x00000000; - checkreg ASTAT, (0x1cb04200 | _VS | _AV0S | _AC1 | _CC | _AZ); - - dmm32 ASTAT, (0x54c0ca00 | _VS | _AV1S | _AV0S | _AC1); - imm32 R6, 0x00000000; - imm32 R7, 0x9ec9c597; - R7 = R6 << 0x8 (S); - checkreg R7, 0x00000000; - checkreg ASTAT, (0x54c0ca00 | _VS | _AV1S | _AV0S | _AC1 | _AZ); - - dmm32 ASTAT, (0x18804400 | _VS | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AN); - imm32 R7, 0x00000000; - R7 = R7 << 0x1d (S); - checkreg ASTAT, (0x18804400 | _VS | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ); - checkreg R7, 0x00000000; - - dmm32 ASTAT, (0x40c08e90 | _VS | _AV1S | _AV0S | _CC); - imm32 R2, 0x00000000; - imm32 R5, 0x80000000; - imm32 R7, 0x00000000; - R5 = ASHIFT R2 BY R7.L (S); - checkreg R5, 0x00000000; - checkreg ASTAT, (0x40c08e90 | _VS | _AV1S | _AV0S | _CC | _AZ); - - dmm32 ASTAT, (0x70b04290 | _VS | _AV1S | _AV0S | _AQ | _AZ); - imm32 R5, 0x8000c2d0; - imm32 R6, 0x00000000; - R5 = R6 << 0x2 (S); - checkreg R5, 0x00000000; - checkreg ASTAT, (0x70b04290 | _VS | _AV1S | _AV0S | _AQ | _AZ); - - dmm32 ASTAT, (0x7cf04480 | _VS | _AV0S | _AC0 | _AC0_COPY | _AZ); - imm32 R3, 0x00000000; - imm32 R7, 0x00000000; - R7 = ASHIFT R3 BY R7.L (S); - checkreg ASTAT, (0x7cf04480 | _VS | _AV0S | _AC0 | _AC0_COPY | _AZ); - checkreg R3, 0x00000000; - checkreg R7, 0x00000000; - - dmm32 ASTAT, (0x78d0c290 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); - imm32 R1, 0x7c98345a; - imm32 R4, 0x00000000; - R1 = ASHIFT R4 BY R1.L (S); - checkreg R1, 0x00000000; - checkreg ASTAT, (0x78d0c290 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x58400e80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY); - imm32 R2, 0x00000000; - imm32 R4, 0x7fffffff; - R4 = R2 << 0x8 (S); - checkreg R4, 0x00000000; - checkreg ASTAT, (0x58400e80 | _VS | _AV0S | _AQ | _CC | _AZ); - - dmm32 ASTAT, (0x4c804080 | _VS | _V | _AV1S | _AV0S | _AV0 | _V_COPY); - imm32 R3, 0x00000000; - imm32 R7, 0x3d196b66; - R7 = ASHIFT R3 BY R3.L (S); - checkreg R7, 0x00000000; - checkreg ASTAT, (0x4c804080 | _VS | _AV1S | _AV0S | _AV0 | _AZ); - - dmm32 ASTAT, (0x44304a10 | _VS | _AV0S | _AQ | _AZ); - imm32 R4, 0x00000000; - imm32 R6, 0x00000000; - R6 = R4 << 0x11 (S); - checkreg ASTAT, (0x44304a10 | _VS | _AV0S | _AQ | _AZ); - checkreg R4, 0x00000000; - checkreg R6, 0x00000000; - - pass diff --git a/sim/testsuite/sim/bfin/random_0025.S b/sim/testsuite/sim/bfin/random_0025.S deleted file mode 100644 index 14cf049..0000000 --- a/sim/testsuite/sim/bfin/random_0025.S +++ /dev/null @@ -1,681 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x74f00490 | _VS | _V | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - imm32 R0, 0x10cfffff; - imm32 R6, 0x06a1ea20; - R0.H = R6.H >>> 0x1b; - checkreg R0, 0xd420ffff; - checkreg ASTAT, (0x74f00490 | _VS | _V | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x78704000 | _VS | _V | _AC0 | _V_COPY); - imm32 R3, 0x80007fff; - R3.L = R3.L >>> 0x1f; - checkreg R3, 0x8000fffe; - checkreg ASTAT, (0x78704000 | _VS | _V | _AC0 | _V_COPY | _AN); - - dmm32 ASTAT, (0x5ce08c00 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AN); - imm32 R3, 0xef9f04f4; - imm32 R6, 0x11037fff; - R3.L = R6.H >>> 0x1d; - checkreg R3, 0xef9f8818; - checkreg ASTAT, (0x5ce08c00 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x14904890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - imm32 R2, 0x00af03a2; - imm32 R7, 0x0b470440; - R7.L = R2.L >>> 0x1a; - checkreg R7, 0x0b47e880; - checkreg ASTAT, (0x14904890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x3040ca00 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AN); - imm32 R1, 0x3bd8d8ef; - imm32 R7, 0x7b15ffff; - R1.H = R7.H >>> 0x1f; - checkreg R1, 0xf62ad8ef; - checkreg ASTAT, (0x3040ca00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x68404600 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AZ); - imm32 R0, 0xfffffffc; - imm32 R1, 0x7ffffffe; - R0.H = R1.H >>> 0x1f; - checkreg R0, 0xfffefffc; - checkreg ASTAT, (0x68404600 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AN); - - dmm32 ASTAT, (0x54108890 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - imm32 R1, 0x30b38b8d; - imm32 R3, 0x1c830bb1; - R1.H = R3.L >>> 0x1c; - checkreg R1, 0xbb108b8d; - checkreg ASTAT, (0x54108890 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x3cc00e80 | _VS | _AV1S | _AC0); - imm32 R6, 0x1b42549c; - R6.L = R6.L >>> 0x1f; - checkreg R6, 0x1b42a938; - checkreg ASTAT, (0x3cc00e80 | _VS | _V | _AV1S | _AC0 | _V_COPY | _AN); - - dmm32 ASTAT, (0x1ca04490 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY); - imm32 R0, 0x0b040a99; - imm32 R6, 0x2716ffff; - R6.H = R0.L >>> 0x1c; - checkreg R6, 0xa990ffff; - checkreg ASTAT, (0x1ca04490 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x14800880 | _VS | _AC0 | _AN | _AZ); - imm32 R2, 0x7fff7fff; - imm32 R7, 0x0a014f10; - R7 = R2 >>> 0x1f (V); - checkreg R7, 0xfffefffe; - checkreg ASTAT, (0x14800880 | _VS | _V | _AC0 | _V_COPY | _AN); - - dmm32 ASTAT, (0x04a08000 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); - imm32 R7, 0x7fffffff; - R7 = R7 >>> 0x10 (V); - checkreg R7, 0x0000ffff; - checkreg ASTAT, (0x04a08000 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x4c204090 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY); - imm32 R2, 0x00030003; - imm32 R6, 0x2c962c96; - R6 = R2 >>> 0x10 (V); - checkreg R6, 0x00000000; - checkreg ASTAT, (0x4c204090 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x14400e00 | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AQ | _AC0_COPY); - imm32 R0, 0x3a567ee8; - imm32 R4, 0x7e163337; - R0 = R4 >>> 0x10 (V); - checkreg R0, 0x00000000; - checkreg ASTAT, (0x14400e00 | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AQ | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x30200a10 | _VS | _AN); - imm32 R2, 0xffff0f44; - R2 = R2 >>> 0x1c (V); - checkreg R2, 0xfff0f440; - checkreg ASTAT, (0x30200a10 | _VS | _V | _V_COPY | _AN); - - dmm32 ASTAT, (0x10c0c080 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); - imm32 R1, 0x1d4571f3; - imm32 R2, 0x1d45ffff; - R2 = R1 >>> 0x10 (V); - checkreg R2, 0x00000000; - checkreg ASTAT, (0x10c0c080 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x4cd08c90 | _VS | _AV1S | _AV0S | _CC); - imm32 R2, 0x8000ffff; - imm32 R3, 0x0f757fff; - R3 = R2 >>> 0x10 (V); - checkreg R3, 0xffffffff; - checkreg ASTAT, (0x4cd08c90 | _VS | _AV1S | _AV0S | _CC | _AN); - - dmm32 ASTAT, (0x68004a00 | _VS | _AV0S | _AQ | _AN); - imm32 R6, 0x366a7fff; - imm32 R7, 0xe4ca366a; - R7 = R6 >>> 0x1f (V); - checkreg R7, 0x6cd4fffe; - checkreg ASTAT, (0x68004a00 | _VS | _V | _AV0S | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x14c0ca80 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); - imm32 R6, 0x3468e405; - imm32 R7, 0x0fd2ee59; - R7 = R6 >>> 0x10 (V); - checkreg R7, 0x0000ffff; - checkreg ASTAT, (0x14c0ca80 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x1460cc90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN | _AZ); - imm32 R3, 0x2b8ffe22; - imm32 R4, 0x2f17d9d2; - R4 = R3 >>> 0x1e (V); - checkreg R4, 0xae3cf888; - checkreg ASTAT, (0x1460cc90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x30d04290 | _VS | _AC1 | _AQ | _CC); - imm32 R1, 0x3afe2bd0; - imm32 R4, 0x57e37450; - R4 = R1 >>> 0x10 (V); - checkreg R4, 0x00000000; - checkreg ASTAT, (0x30d04290 | _VS | _AC1 | _AQ | _CC | _AZ); - - dmm32 ASTAT, (0x04600600 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN); - imm32 R0, 0xedbbfffe; - imm32 R4, 0x169330ac; - R0 = R4 >>> 0x1e (V); - checkreg R0, 0x5a4cc2b0; - checkreg ASTAT, (0x04600600 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY | _AN); - - dmm32 ASTAT, (0x64c0c290 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _CC | _AN); - imm32 R1, 0x788b2d30; - imm32 R6, 0x78f61ce9; - R6 = R1 >>> 0x10 (V); - checkreg R6, 0x00000000; - checkreg ASTAT, (0x64c0c290 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _CC | _AZ); - - dmm32 ASTAT, (0x74d04680 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY); - imm32 R0, 0x0b7d1dc6; - imm32 R7, 0x3d27f3e5; - R7 = R0 >>> 0x10 (V); - checkreg R7, 0x00000000; - checkreg ASTAT, (0x74d04680 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x74900000 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC); - imm32 R5, 0xffc70074; - imm32 R7, 0xf49916ce; - R5 = R7 >>> 0x10 (V); - checkreg R5, 0xffff0000; - checkreg ASTAT, (0x74900000 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AN | _AZ); - - dmm32 ASTAT, (0x6ca0c400 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN); - imm32 R0, 0x1e0287a7; - imm32 R4, 0x30aa2286; - R0 = R4 >>> 0x10 (V); - checkreg R0, 0x00000000; - checkreg ASTAT, (0x6ca0c400 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x10204a00 | _VS | _CC | _AN); - imm32 R5, 0xa6b04dd0; - imm32 R6, 0xfedb4cd8; - R5 = R6 >>> 0x1f (V); - checkreg R5, 0xfdb699b0; - checkreg ASTAT, (0x10204a00 | _VS | _V | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x30e04290 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY); - imm32 R2, 0x0c55766f; - imm32 R3, 0x28c00004; - R2 = R3 >>> 0x10 (V); - checkreg R2, 0x00000000; - checkreg ASTAT, (0x30e04290 | _VS | _AV1S | _AV0S | _AC1 | _AZ); - - dmm32 ASTAT, (0x34b0c410 | _VS | _AQ | _CC); - imm32 R7, 0x0f7b2928; - R7 = R7 >>> 0x1e (V); - checkreg R7, 0x3deca4a0; - checkreg ASTAT, (0x34b0c410 | _VS | _V | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x18504800 | _VS | _AV1S | _AC1 | _AC0_COPY); - imm32 R4, 0x0baad54f; - imm32 R7, 0x05bf0c50; - R4 = R7 >>> 0x10 (V); - checkreg R4, 0x00000000; - checkreg ASTAT, (0x18504800 | _VS | _AV1S | _AC1 | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x2cd04290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY); - imm32 R0, 0x1199ca48; - imm32 R7, 0x4ee24366; - R7 = R0 >>> 0x10 (V); - checkreg R7, 0x0000ffff; - checkreg ASTAT, (0x2cd04290 | _VS | _AV1S | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x24304c90 | _VS | _AV0S | _AC1 | _AC0 | _CC); - imm32 R3, 0x528af4b6; - imm32 R6, 0x18d26b4a; - R3 = R6 >>> 0x10 (V); - checkreg R3, 0x00000000; - checkreg ASTAT, (0x24304c90 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AZ); - - dmm32 ASTAT, (0x70504200 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ); - imm32 R1, 0x255f0000; - imm32 R4, 0x96e0e654; - imm32 R6, 0x255fd442; - R4 = ASHIFT R1 BY R6.L; - checkreg R4, 0x957c0000; - checkreg ASTAT, (0x70504200 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x10004210 | _VS | _AV1S | _AC1 | _AQ); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R3, 0x13f865f4; - A1 = ASHIFT A1 BY R3.L; - checkreg ASTAT, (0x10004210 | _VS | _AV1S | _AC1 | _AQ | _AZ); - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg R3, 0x13f865f4; - - dmm32 ASTAT, (0x1c90c400 | _VS | _AV0S | _AC1 | _AZ); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R3, 0x00000000; - A0 = ASHIFT A0 BY R3.L; - checkreg ASTAT, (0x1c90c400 | _VS | _AV0S | _AC1 | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R3, 0x00000000; - - dmm32 ASTAT, (0x4820c280 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AN); - dmm32 A1.w, 0x00000001; - dmm32 A1.x, 0x00000000; - imm32 R3, 0x4a4a7fff; - A1 = LSHIFT A1 BY R3.L; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x4820c280 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AZ); - - dmm32 ASTAT, (0x1c20cc10 | _VS | _AC1 | _AN); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x00000000; - A1 = LSHIFT A1 BY R0.L; - checkreg ASTAT, (0x1c20cc10 | _VS | _AC1 | _AZ); - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg R0, 0x00000000; - - dmm32 ASTAT, (0x1c608e90 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AC0_COPY | _AZ); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R4, 0x10cb0000; - A0 = ASHIFT A0 BY R4.L; - checkreg ASTAT, (0x1c608e90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R4, 0x10cb0000; - - dmm32 ASTAT, (0x6870ce00 | _VS | _AC1 | _AC0_COPY | _AZ); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R4, 0x00000000; - A1 = LSHIFT A1 BY R4.L; - checkreg ASTAT, (0x6870ce00 | _VS | _AC1 | _AC0_COPY | _AZ); - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg R4, 0x00000000; - - dmm32 ASTAT, (0x04200290 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AZ); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R2, 0x00000000; - A0 = LSHIFT A0 BY R2.L; - checkreg ASTAT, (0x04200290 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R2, 0x00000000; - - dmm32 ASTAT, (0x0c404e80 | _VS | _V | _V_COPY); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R7, 0xc400e200; - A0 = ASHIFT A0 BY R7.L; - checkreg ASTAT, (0x0c404e80 | _VS | _V | _V_COPY | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R7, 0xc400e200; - - dmm32 ASTAT, (0x04e00800 | _VS | _AV1S | _AV0S); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R0, 0xe603ffff; - A0 = LSHIFT A0 BY R0.L; - checkreg ASTAT, (0x04e00800 | _VS | _AV1S | _AV0S | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R0, 0xe603ffff; - - dmm32 ASTAT, (0x40904090 | _VS | _AV0S | _AC1 | _CC | _AZ); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R6, 0x00000000; - A1 = LSHIFT A1 BY R6.L; - checkreg ASTAT, (0x40904090 | _VS | _AV0S | _AC1 | _CC | _AZ); - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg R6, 0x00000000; - - dmm32 ASTAT, (0x24f04c10 | _VS | _V | _AC1 | _V_COPY | _AC0_COPY | _AN); - dmm32 A0.w, 0x023d0ac0; - dmm32 A0.x, 0x00000000; - imm32 R2, 0xfffe05e0; - A0 = ASHIFT A0 BY R2.L; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x24f04c10 | _VS | _V | _AC1 | _V_COPY | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x2860c410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AC0_COPY); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R4, 0x00000000; - A1 = ASHIFT A1 BY R4.L; - checkreg ASTAT, (0x2860c410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AC0_COPY | _AZ); - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg R4, 0x00000000; - - dmm32 ASTAT, (0x40000a00 | _VS | _V | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AN); - imm32 R2, 0x4e59ffff; - imm32 R6, 0x2c450001; - R6 = ASHIFT R2 BY R6.L (V); - checkreg R6, 0x9cb2fffe; - checkreg ASTAT, (0x40000a00 | _VS | _V | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x3c700410 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AC0_COPY | _AZ); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R6, 0x0d1144c0; - A0 = LSHIFT A0 BY R6.L; - checkreg ASTAT, (0x3c700410 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R6, 0x0d1144c0; - - dmm32 ASTAT, (0x5c10ca80 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ); - dmm32 A1.w, 0x80000000; - dmm32 A1.x, 0x00000000; - imm32 R7, 0x472d2397; - A1 = LSHIFT A1 BY R7.L; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x5c10ca80 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x10004c00 | _VS | _AQ | _AZ); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R2, 0x80000000; - A1 = LSHIFT A1 BY R2.L; - checkreg ASTAT, (0x10004c00 | _VS | _AQ | _AZ); - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg R2, 0x80000000; - - dmm32 ASTAT, (0x30308480 | _VS | _AV0S | _AQ); - dmm32 A0.w, 0x19b289d0; - dmm32 A0.x, 0x00000000; - imm32 R6, 0xffff0ce2; - A0 = LSHIFT A0 BY R6.L; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x30308480 | _VS | _AV0S | _AQ | _AZ); - - dmm32 ASTAT, (0x28708280 | _VS | _AV1S | _AC1 | _AQ | _CC | _AC0_COPY); - dmm32 A0.w, 0x3f050000; - dmm32 A0.x, 0x00000000; - imm32 R6, 0xc0fb081a; - A0 = LSHIFT A0 BY R6.L; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x28708280 | _VS | _AV1S | _AC1 | _AQ | _CC | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x18708280 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AN); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R3, 0xeca83337; - A0 = LSHIFT A0 BY R3.L; - checkreg ASTAT, (0x18708280 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R3, 0xeca83337; - - dmm32 ASTAT, (0x78b0c010 | _VS | _AV1S | _AC1 | _AC0 | _AN); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R5, 0x00000000; - A1 = ASHIFT A1 BY R5.L; - checkreg ASTAT, (0x78b0c010 | _VS | _AV1S | _AC1 | _AC0 | _AZ); - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg R5, 0x00000000; - - dmm32 ASTAT, (0x50d00680 | _VS | _AV1S | _AV0S | _AC1 | _AQ); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R3, 0x05600000; - A1 = LSHIFT A1 BY R3.L; - checkreg ASTAT, (0x50d00680 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AZ); - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg R3, 0x05600000; - - dmm32 ASTAT, (0x04108880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC); - dmm32 A0.w, 0x046b40e7; - dmm32 A0.x, 0x00000000; - imm32 R3, 0x20a220a2; - A0 = ASHIFT A0 BY R3.L; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x04108880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AZ); - - dmm32 ASTAT, (0x6850cc80 | _VS | _AV1S | _AV0S | _AV0 | _AC0_COPY | _AN); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R1, 0x623d1bad; - A0 = ASHIFT A0 BY R1.L; - checkreg ASTAT, (0x6850cc80 | _VS | _AV1S | _AV0S | _AC0_COPY | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R1, 0x623d1bad; - - dmm32 ASTAT, (0x44d04a80 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R4, 0x211b1629; - A1 = LSHIFT A1 BY R4.L; - checkreg ASTAT, (0x44d04a80 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ); - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg R4, 0x211b1629; - - dmm32 ASTAT, (0x1c304480 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _AZ); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R1, 0xffffa0e5; - A0 = ASHIFT A0 BY R1.L; - checkreg ASTAT, (0x1c304480 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R1, 0xffffa0e5; - - dmm32 ASTAT, (0x54c00c90 | _VS | _AV0S | _AC1 | _CC | _AZ); - dmm32 A1.w, 0x01cdbb21; - dmm32 A1.x, 0x00000000; - imm32 R7, 0x696f3de3; - A1 = ASHIFT A1 BY R7.L; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x54c00c90 | _VS | _AV0S | _AC1 | _CC | _AZ); - - dmm32 ASTAT, (0x7c30c690 | _VS | _AV1S | _AV0S | _AC1 | _AC0_COPY | _AN); - dmm32 A1.w, 0x00007400; - dmm32 A1.x, 0x00000000; - imm32 R4, 0x6fc3cc21; - A1 = LSHIFT A1 BY R4.L; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x7c30c690 | _VS | _AV1S | _AV0S | _AC1 | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x1c404200 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AN); - imm32 R2, 0x1e000001; - imm32 R4, 0x037b7038; - imm32 R5, 0x57beffff; - R4.L = ASHIFT R5.H BY R2.L; - checkreg R4, 0x037baf7c; - checkreg ASTAT, (0x1c404200 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x24e08c80 | _VS | _AV1S | _CC); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R6, 0x11f23024; - A0 = LSHIFT A0 BY R6.L; - checkreg ASTAT, (0x24e08c80 | _VS | _AV1S | _CC | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R6, 0x11f23024; - - dmm32 ASTAT, (0x3ce04080 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R2, 0x00000000; - A0 = ASHIFT A0 BY R2.L; - checkreg ASTAT, (0x3ce04080 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R2, 0x00000000; - - dmm32 ASTAT, (0x28800280 | _VS | _AV1S | _AV0S | _CC | _AZ); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R0, 0x00000000; - A0 = LSHIFT A0 BY R0.L; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x28800280 | _VS | _AV1S | _AV0S | _CC | _AZ); - - dmm32 ASTAT, (0x68708810 | _VS | _V | _AV1S | _AV0S | _AV1 | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0x80000000; - dmm32 A1.x, 0xffffffea; - imm32 R2, 0x0121e8d9; - A1 = ASHIFT A1 BY R2.L; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x68708810 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x24c00890 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x1b9411f4; - A1 = LSHIFT A1 BY R0.L; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x24c00890 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x4480ce00 | _VS | _AC1); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - A1 = A1 << 0x5; - checkreg ASTAT, (0x4480ce00 | _VS | _AC1 | _AZ); - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - - dmm32 ASTAT, (0x6cf0cc10 | _VS | _AC0 | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - A1 = A1 >> 0x3b; - checkreg ASTAT, (0x6cf0cc10 | _VS | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - - dmm32 ASTAT, (0x50d00a80 | _VS | _AV1S | _AV0S | _AC1 | _AN); - dmm32 A1.w, 0x028ab5f4; - dmm32 A1.x, 0x00000000; - A1 = A1 >> 0x1f; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x50d00a80 | _VS | _AV1S | _AV0S | _AC1 | _AZ); - - dmm32 ASTAT, (0x14c00490 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY); - dmm32 A1.w, 0x0001f0f0; - dmm32 A1.x, 0x00000000; - A1 = A1 >> 0x14; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x14c00490 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x14808a80 | _VS | _AV1S | _AV0S | _AC1 | _AN); - dmm32 A0.w, 0x000fc1a6; - dmm32 A0.x, 0x00000000; - A0 = A0 >> 0x1f; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x14808a80 | _VS | _AV1S | _AV0S | _AC1 | _AZ); - - dmm32 ASTAT, (0x3c80ca90 | _VS | _AV0S | _AC0 | _AQ | _CC | _AZ); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - A1 = A1 >>> 0x1e; - checkreg ASTAT, (0x3c80ca90 | _VS | _AV0S | _AC0 | _AQ | _CC | _AZ); - checkreg A1.w, 0x00000000; - checkreg A1.x, 0x00000000; - - dmm32 ASTAT, (0x4c200c90 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ); - imm32 R2, 0xf1815f1a; - imm32 R7, 0x0a917fff; - R7.L = R2.L >>> 0x13; - checkreg R7, 0x0a914000; - checkreg ASTAT, (0x4c200c90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x0cf0cc80 | _VS | _AV0S | _AC0_COPY | _AZ); - imm32 R0, 0x000081ad; - imm32 R2, 0x00000000; - R2.H = R0.L >>> 0x19; - checkreg R2, 0xd6800000; - checkreg ASTAT, (0x0cf0cc80 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x04304c10 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY | _AN); - imm32 R1, 0x33dd7fff; - imm32 R7, 0xae86a2f4; - R1 = R7 >>> 0x13 (V); - checkreg R1, 0xc0008000; - checkreg ASTAT, (0x04304c10 | _VS | _V | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x7850c800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN); - imm32 R4, 0x0000fffe; - imm32 R7, 0x5906fc4f; - R4.L = R7.H >>> 0x15; - checkreg R4, 0x00003000; - checkreg ASTAT, (0x7850c800 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY); - - dmm32 ASTAT, (0x64804c90 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN); - imm32 R1, 0x000009e3; - imm32 R4, 0x44418b70; - R1.H = R4.L >>> 0x17; - checkreg R1, 0xe00009e3; - checkreg ASTAT, (0x64804c90 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x2c508410 | _VS | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY | _AZ); - imm32 R0, 0x43d731e2; - imm32 R4, 0x60995f48; - R0.L = R4.H >>> 0x17; - checkreg R0, 0x43d73200; - checkreg ASTAT, (0x2c508410 | _VS | _V | _AV1 | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x0c900010 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - A0 = A0 >>> 0xc; - checkreg ASTAT, (0x0c900010 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - - dmm32 ASTAT, (0x40c00e80 | _VS | _AV1 | _AV0S | _CC | _AN | _AZ); - imm32 R1, 0x0bf14680; - imm32 R3, 0x1875266d; - R3.H = R1.L >>> 0x1d; - checkreg R3, 0x3400266d; - checkreg ASTAT, (0x40c00e80 | _VS | _V | _AV1 | _AV0S | _CC | _V_COPY); - - dmm32 ASTAT, (0x78100a00 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AC0_COPY | _AN); - imm32 R4, 0x67c0a470; - imm32 R7, 0x000026c0; - R4 = R7 >>> 0x1d (V); - checkreg R4, 0x00003600; - checkreg ASTAT, (0x78100a00 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x6cd04610 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY); - imm32 R0, 0x0f9535a6; - imm32 R5, 0x31018b62; - R0 = R5 >>> 0x12 (V); - checkreg R0, 0x40008000; - checkreg ASTAT, (0x6cd04610 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x58a08800 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - imm32 R2, 0x023cffff; - imm32 R6, 0x0d6d8000; - R6.L = R2.H >>> 0x18; - checkreg R6, 0x0d6d3c00; - checkreg ASTAT, (0x58a08800 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x5cc00600 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); - imm32 R2, 0xa9d7c2fd; - imm32 R4, 0xfffed266; - R2.L = R4.L >>> 0x12; - checkreg R2, 0xa9d78000; - checkreg ASTAT, (0x5cc00600 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x5c900400 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY | _AN); - imm32 R1, 0xf37e61a8; - imm32 R4, 0x5522a41c; - R4 = R1 >>> 0x12 (V); - checkreg R4, 0x80000000; - checkreg ASTAT, (0x5c900400 | _VS | _V | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ); - - pass diff --git a/sim/testsuite/sim/bfin/random_0026.S b/sim/testsuite/sim/bfin/random_0026.S deleted file mode 100644 index 526b007..0000000 --- a/sim/testsuite/sim/bfin/random_0026.S +++ /dev/null @@ -1,195 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x4c60c810 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY); - dmm32 A0.w, 0x7fffffff; - dmm32 A0.x, 0x00000000; - imm32 R0, 0x00000000; - imm32 R5, 0x00007fff; - imm32 R7, 0x00000000; - R7.L = (A0 += R0.L * R5.L) (IH); - checkreg R7, 0x00007fff; - checkreg A0.w, 0x7fffffff; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x4c60c810 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x00500680 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN); - dmm32 A0.w, 0x80000000; - dmm32 A0.x, 0xffffffff; - imm32 R2, 0xffffffff; - imm32 R4, 0xa8dd8000; - imm32 R7, 0x80000000; - R4.L = (A0 -= R2.L * R7.H) (IH); - checkreg A0.w, 0x80000000; - checkreg A0.x, 0xffffffff; - checkreg R4, 0xa8dd8000; - checkreg ASTAT, (0x00500680 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x50408c90 | _VS | _V | _AV1S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AN); - dmm32 A1.w, 0xfa400000; - dmm32 A1.x, 0xffffffad; - imm32 R0, 0x366b1c84; - imm32 R3, 0x7fffffff; - imm32 R7, 0x32528aa5; - R3.H = (A1 += R0.L * R7.L) (M, IH); - checkreg R3, 0x8000ffff; - checkreg A1.w, 0x80000000; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x50408c90 | _VS | _V | _AV1S | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x0c400c10 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0xef56cbd3; - dmm32 A1.x, 0x00000000; - imm32 R3, 0x7fff0003; - imm32 R4, 0x385cffff; - imm32 R7, 0x680dffff; - R7.H = (A1 -= R4.L * R3.H) (M, IH); - checkreg R7, 0x7fffffff; - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x0c400c10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x2c604c00 | _AV1S | _AV0 | _AC1); - dmm32 A1.w, 0xf54ee9bb; - dmm32 A1.x, 0x0000004a; - imm32 R3, 0x10bb4bdc; - imm32 R4, 0x7f29c57d; - imm32 R7, 0x2c03f00a; - R4.H = (A1 -= R3.L * R7.H) (M, IH); - checkreg R4, 0x7fffc57d; - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x2c604c00 | _VS | _V | _AV1S | _AV1 | _AV0 | _AC1 | _V_COPY); - - dmm32 ASTAT, (0x2c304800 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY); - dmm32 A1.w, 0xc1a6b608; - dmm32 A1.x, 0x00000056; - imm32 R2, 0xd0457fff; - imm32 R6, 0xf4b2ffff; - R6.H = (A1 += R2.L * R6.H) (M, IH); - checkreg R6, 0x7fffffff; - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x2c304800 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY); - - dmm32 ASTAT, (0x04a08810 | _VS | _AV1S | _AC1 | _AC0 | _AN); - dmm32 A1.w, 0xe9574334; - dmm32 A1.x, 0x00000056; - imm32 R3, 0xffffb2bc; - imm32 R5, 0x03eb4d44; - imm32 R6, 0x33852750; - R5.H = (A1 -= R6.L * R3.L) (M, IH); - checkreg R5, 0x7fff4d44; - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x04a08810 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _V_COPY | _AN); - - dmm32 ASTAT, (0x5860c210 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY); - dmm32 A1.w, 0xd5030654; - dmm32 A1.x, 0x0000001c; - imm32 R0, 0x20ccb6ee; - imm32 R2, 0x74c21675; - imm32 R4, 0x7fff7fff; - R2.H = (A1 -= R0.L * R4.L) (M, IH); - checkreg R2, 0x7fff1675; - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x5860c210 | _VS | _V | _AV1S | _AV1 | _AC1 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x34800e00 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0xf0b59d3f; - dmm32 A1.x, 0xffffffef; - imm32 R4, 0x28bd7772; - imm32 R6, 0xef66ce6a; - imm32 R7, 0x80000000; - R6.H = (A1 -= R4.L * R7.H) (M, IH); - checkreg R6, 0x8000ce6a; - checkreg A1.w, 0x80000000; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x34800e00 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x5c804a90 | _VS | _AV1S | _AV0S | _AQ | _AN); - dmm32 A1.w, 0xc90d8c2f; - dmm32 A1.x, 0xffffffee; - imm32 R0, 0x80006a2f; - imm32 R3, 0x80000000; - R3.H = (A1 += R0.L * R0.H) (M, IH); - checkreg A1.w, 0x80000000; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x5c804a90 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x5c90c010 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AN); - dmm32 A1.w, 0x80ca2186; - dmm32 A1.x, 0x00000000; - imm32 R1, 0xf3ec0000; - imm32 R3, 0x5a859a0a; - imm32 R6, 0x19e852d9; - R3.H = (A1 -= R1.L * R6.L) (M, IH); - checkreg R3, 0x7fff9a0a; - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x5c90c010 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC0 | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x00f00a10 | _VS | _V | _AV0S | _CC | _V_COPY | _AN); - dmm32 A1.w, 0x9f5baab0; - dmm32 A1.x, 0x00000019; - imm32 R1, 0x1bb2489b; - imm32 R6, 0x0aa80127; - R1.H = (A1 -= R6.L * R6.H) (M, IH); - checkreg R1, 0x7fff489b; - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x00f00a10 | _VS | _V | _AV1S | _AV1 | _AV0S | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x3c808210 | _VS | _V | _AV1S | _V_COPY | _AN); - dmm32 A1.w, 0xe09f1e24; - dmm32 A1.x, 0x00000025; - imm32 R1, 0x255b55bc; - imm32 R2, 0x7f1bd115; - imm32 R3, 0xbc978902; - R2.H = (A1 -= R3.L * R1.H) (M, IH); - checkreg R2, 0x7fffd115; - checkreg A1.w, 0x7fffffff; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x3c808210 | _VS | _V | _AV1S | _AV1 | _V_COPY | _AN); - - dmm32 ASTAT, (0x1ca04600 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY); - dmm32 A1.w, 0xb80e1ddd; - dmm32 A1.x, 0xffffffca; - imm32 R0, 0x2155a4b5; - imm32 R1, 0x5dd905c2; - imm32 R2, 0x769083dc; - R1.H = (A1 -= R2.L * R0.H) (M, IH); - checkreg R1, 0x800005c2; - checkreg A1.w, 0x80000000; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x1ca04600 | _VS | _V | _AV1S | _AV1 | _AV0S | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x1cb0cc90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0xfc7c3973; - dmm32 A1.x, 0xffffff8a; - imm32 R1, 0x58a6c4e7; - imm32 R4, 0x19b16033; - imm32 R6, 0x301ff2ba; - R6.H = (A1 -= R4.L * R1.H) (M, IH); - checkreg R6, 0x8000f2ba; - checkreg A1.w, 0x80000000; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x1cb0cc90 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x2c800810 | _VS | _AV1S | _AQ | _CC | _AN); - dmm32 A1.w, 0xd86a7676; - dmm32 A1.x, 0xffffff97; - imm32 R3, 0x443fea83; - imm32 R4, 0x47ed4ac3; - imm32 R6, 0x7fffffff; - R4.H = (A1 += R3.L * R6.L) (M, IH); - checkreg R4, 0x80004ac3; - checkreg A1.w, 0x80000000; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x2c800810 | _VS | _V | _AV1S | _AV1 | _AQ | _CC | _V_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0027.S b/sim/testsuite/sim/bfin/random_0027.S deleted file mode 100644 index 06ea3c8..0000000 --- a/sim/testsuite/sim/bfin/random_0027.S +++ /dev/null @@ -1,266 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x2850c890 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY); - dmm32 A1.w, 0xa605868e; - dmm32 A1.x, 0x00000000; - imm32 R1, 0x56dd0982; - imm32 R4, 0x50e37862; - imm32 R5, 0x597fc81a; - R4.H = (A1 -= R5.L * R1.L) (M, IS); - checkreg R4, 0x7fff7862; - checkreg A1.w, 0xa818ff5a; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x2850c890 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x08100a00 | _VS | _AC1 | _AC0 | _CC); - dmm32 A1.w, 0xeb710132; - dmm32 A1.x, 0xffffffcf; - imm32 R4, 0x750d92cc; - imm32 R7, 0xf9a22cee; - R4.H = (A1 -= R7.L * R7.H) (M, IS); - checkreg R4, 0x800092cc; - checkreg A1.w, 0xbfa11496; - checkreg A1.x, 0xffffffcf; - checkreg ASTAT, (0x08100a00 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY); - - dmm32 ASTAT, (0x44e00410 | _VS | _AV0S | _AQ | _AN); - dmm32 A1.w, 0x95489ea8; - dmm32 A1.x, 0x00000000; - imm32 R1, 0x360dca41; - imm32 R4, 0x7fffe848; - imm32 R7, 0x278abda8; - R7 = (A1 -= R4.L * R1.L) (M, IS); - checkreg R7, 0x7fffffff; - checkreg A1.w, 0xa805d460; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x44e00410 | _VS | _V | _AV0S | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x0480c800 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ); - dmm32 A1.w, 0xcfa4f43b; - dmm32 A1.x, 0x0000006c; - imm32 R3, 0x0903dd55; - imm32 R7, 0x7fffc2b1; - A1 -= R3.L * R7.L (M, IS); - checkreg A1.w, 0xea028276; - checkreg A1.x, 0x0000006c; - checkreg ASTAT, (0x0480c800 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x3c204410 | _VS | _AV0S | _AN); - dmm32 A1.w, 0x928b984e; - dmm32 A1.x, 0xffffffd5; - imm32 R5, 0x00003ddd; - imm32 R7, 0x8000ffff; - A1 += R5.L * R7.L (M, IS); - checkreg A1.w, 0xd0685a71; - checkreg A1.x, 0xffffffd5; - checkreg ASTAT, (0x3c204410 | _VS | _AV0S | _AN); - - dmm32 ASTAT, (0x4840c890 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN); - dmm32 A1.w, 0x8837abf1; - dmm32 A1.x, 0x00000000; - imm32 R3, 0x10c90000; - imm32 R7, 0x7fffe6b8; - A1 += R7.L * R3.H (M, IS); - checkreg A1.w, 0x868f5269; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x4840c890 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x78604a80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY); - dmm32 A1.w, 0xdca875cf; - dmm32 A1.x, 0x0000002c; - imm32 R3, 0x4c0892ef; - imm32 R5, 0x001fea98; - R5.H = (A1 += R5.L * R3.H) (M, IS); - checkreg R5, 0x7fffea98; - checkreg A1.w, 0xd64cea8f; - checkreg A1.x, 0x0000002c; - checkreg ASTAT, (0x78604a80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x00a04210 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0xec5ef880; - dmm32 A1.x, 0xfffffffe; - imm32 R0, 0x229657d6; - imm32 R7, 0xedd48000; - A1 += R0.L * R7.L (M, IS); - checkreg A1.w, 0x1849f880; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x00a04210 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x0840ce80 | _VS | _AV1S | _AV0S | _AC1 | _AQ); - dmm32 A1.w, 0xe4a5a6e1; - dmm32 A1.x, 0x00000078; - imm32 R0, 0xf059329d; - imm32 R7, 0x7fff7512; - A1 += R7.L * R0.L (M, IS); - checkreg A1.w, 0xfbcaf6eb; - checkreg A1.x, 0x00000078; - checkreg ASTAT, (0x0840ce80 | _VS | _AV1S | _AV0S | _AC1 | _AQ); - - dmm32 ASTAT, (0x60100810 | _VS | _AV0S | _AQ | _AC0_COPY | _AZ); - dmm32 A1.w, 0xd56a8232; - dmm32 A1.x, 0x00000033; - imm32 R0, 0x09b22c69; - imm32 R7, 0x434f1d64; - A1 -= R0.L * R7.L (M, IS); - checkreg A1.w, 0xd051442e; - checkreg A1.x, 0x00000033; - checkreg ASTAT, (0x60100810 | _VS | _AV0S | _AQ | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x58e08410 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0x86c9a59e; - dmm32 A1.x, 0xffffff9a; - imm32 R1, 0x22573f31; - imm32 R6, 0x2d0c0155; - A1 += R1.L * R6.H (M, IS); - checkreg A1.w, 0x91e838ea; - checkreg A1.x, 0xffffff9a; - checkreg ASTAT, (0x58e08410 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x64a0c690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN); - dmm32 A1.w, 0xc5c840aa; - dmm32 A1.x, 0x00000000; - imm32 R4, 0xffff7fff; - imm32 R7, 0x658e833f; - A1 -= R7.L * R4.H (M, IS); - checkreg A1.w, 0x4288c3e9; - checkreg A1.x, 0x00000001; - checkreg ASTAT, (0x64a0c690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x08804610 | _VS | _V | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AN); - dmm32 A1.w, 0xf1000000; - dmm32 A1.x, 0x00000040; - imm32 R3, 0x0cd4edf1; - imm32 R6, 0x4dfc08b8; - R6.H = (A1 += R6.L * R3.H) (M, IS); - checkreg R6, 0x7fff08b8; - checkreg A1.w, 0xf16fd860; - checkreg A1.x, 0x00000040; - checkreg ASTAT, (0x08804610 | _VS | _V | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x7c004690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN); - dmm32 A1.w, 0xd4deb886; - dmm32 A1.x, 0x00000001; - imm32 R1, 0x80008000; - imm32 R6, 0x22fb6e50; - imm32 R7, 0x3fcb147f; - R1.H = (A1 -= R7.L * R6.L) (M, IS); - checkreg R1, 0x7fff8000; - checkreg A1.w, 0xcc09bed6; - checkreg A1.x, 0x00000001; - checkreg ASTAT, (0x7c004690 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x40a00400 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN); - dmm32 A1.w, 0x9698e35b; - dmm32 A1.x, 0xfffffffc; - imm32 R5, 0x8000038c; - imm32 R6, 0x3152ffff; - A1 -= R6.L * R5.L (M, IS); - checkreg A1.w, 0x9698e6e7; - checkreg A1.x, 0xfffffffc; - checkreg ASTAT, (0x40a00400 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x54c00810 | _VS | _V | _AC1 | _CC | _V_COPY | _AN | _AZ); - dmm32 A1.w, 0x9b02b9c6; - dmm32 A1.x, 0xffffffd4; - imm32 R2, 0xff020105; - imm32 R3, 0xa8ff8000; - R3.H = (A1 -= R2.L * R3.L) (M, IS); - checkreg R3, 0x80008000; - checkreg A1.w, 0x9a8039c6; - checkreg A1.x, 0xffffffd4; - checkreg ASTAT, (0x54c00810 | _VS | _V | _AC1 | _CC | _V_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x58808680 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0x990456b2; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x2b76c7b2; - imm32 R3, 0x659803c8; - imm32 R7, 0x7fffffff; - R3.H = (A1 += R7.L * R0.L) (M, IS); - checkreg R3, 0x7fff03c8; - checkreg A1.w, 0x99038f00; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x58808680 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x3ce04690 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY); - dmm32 A1.w, 0x95d1d45a; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x4331b012; - imm32 R5, 0x7fff8000; - A1 -= R0.L * R5.H (M, IS); - checkreg A1.w, 0xbdc8846c; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x3ce04690 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY); - - dmm32 ASTAT, (0x30e04410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC); - dmm32 A1.w, 0xcf49e4c9; - dmm32 A1.x, 0x00000000; - imm32 R1, 0xe968a740; - imm32 R3, 0xd7383cd5; - imm32 R6, 0x5a87c89b; - R1 = (A1 += R3.L * R6.H) (M, IS); - checkreg R1, 0x7fffffff; - checkreg A1.w, 0xe4ccdb1c; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x30e04410 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x2cb04890 | _VS | _AC1 | _AQ | _AC0_COPY); - dmm32 A1.w, 0x8bdaf471; - dmm32 A1.x, 0xffffffbd; - imm32 R3, 0x728d99b1; - imm32 R7, 0x181d83c2; - A1 -= R7.L * R3.L (M, IS); - checkreg A1.w, 0xd671e94f; - checkreg A1.x, 0xffffffbd; - checkreg ASTAT, (0x2cb04890 | _VS | _AC1 | _AQ | _AC0_COPY); - - dmm32 ASTAT, (0x20908680 | _VS | _AV0S | _AC1 | _AQ | _CC | _AZ); - dmm32 A1.w, 0xc1cb8a00; - dmm32 A1.x, 0x00000000; - imm32 R1, 0xc1e98ea8; - imm32 R7, 0x0000961f; - A1 -= R7.L * R1.L (M, IS); - checkreg A1.w, 0xfccbd3a8; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x20908680 | _VS | _AV0S | _AC1 | _AQ | _CC | _AZ); - - dmm32 ASTAT, (0x64a0cc80 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AZ); - dmm32 A1.w, 0xfb328cb4; - dmm32 A1.x, 0xffffff9b; - imm32 R2, 0x8000ffff; - imm32 R3, 0x64d21863; - imm32 R6, 0x3b7618a6; - R2.H = (A1 += R3.L * R6.H) (M, IS); - checkreg A1.w, 0x00dc9b56; - checkreg A1.x, 0xffffff9c; - checkreg ASTAT, (0x64a0cc80 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AZ); - - dmm32 ASTAT, (0x3c00ca90 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0xbfb4c632; - dmm32 A1.x, 0x00000044; - imm32 R1, 0x7fffffff; - imm32 R3, 0xf3e9182e; - imm32 R5, 0x3c94d844; - R5.H = (A1 += R1.L * R3.H) (M, IS); - checkreg R5, 0x7fffd844; - checkreg A1.w, 0xbfb3d249; - checkreg A1.x, 0x00000044; - checkreg ASTAT, (0x3c00ca90 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x48c0cc10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); - dmm32 A1.w, 0x83144651; - dmm32 A1.x, 0x00000000; - imm32 R3, 0x04d0ffff; - imm32 R4, 0x9dc8f8d8; - imm32 R7, 0x23180d75; - R3 = (A1 += R4.L * R7.L) (M, IS); - checkreg R3, 0x7fffffff; - checkreg A1.w, 0x82b3f909; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x48c0cc10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/random_0028.S b/sim/testsuite/sim/bfin/random_0028.S deleted file mode 100644 index 2fd31c9..0000000 --- a/sim/testsuite/sim/bfin/random_0028.S +++ /dev/null @@ -1,220 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x44004010 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY); - dmm32 A1.w, 0x851fa4fc; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x00000000; - imm32 R2, 0x80000000; - imm32 R5, 0x139d77b4; - R5.H = (A1 += R2.L * R0.L) (M, S2RND); - checkreg R5, 0x7fff77b4; - checkreg A1.w, 0x851fa4fc; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x44004010 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x48000600 | _VS | _V | _AV1S | _CC | _V_COPY); - dmm32 A1.w, 0xc5ee7420; - dmm32 A1.x, 0x00000000; - imm32 R1, 0x45f17fff; - imm32 R2, 0x00000000; - imm32 R4, 0xffffffff; - R1 = (A1 -= R2.L * R4.H) (M, S2RND); - checkreg R1, 0x7fffffff; - checkreg A1.w, 0xc5ee7420; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x48000600 | _VS | _V | _AV1S | _CC | _V_COPY); - - dmm32 ASTAT, (0x48500a10 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AZ); - dmm32 A1.w, 0x965cddab; - dmm32 A1.x, 0x00000063; - imm32 R1, 0x1d4cc3e7; - imm32 R3, 0xe7ce9d8e; - imm32 R6, 0x3cc80b2f; - R6.H = (A1 -= R3.L * R1.L) (M, S2RND); - checkreg R6, 0x7fff0b2f; - checkreg A1.w, 0xe1b28889; - checkreg A1.x, 0x00000063; - checkreg ASTAT, (0x48500a10 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x44308410 | _VS | _AV0S | _CC | _AN); - dmm32 A1.w, 0x92315df7; - dmm32 A1.x, 0x0000007e; - imm32 R1, 0x9e4b24e0; - imm32 R4, 0xe3da8000; - imm32 R7, 0x00ba086c; - R1.H = (A1 -= R7.L * R4.H) (M, S2RND); - checkreg R1, 0x7fff24e0; - checkreg A1.w, 0x8ab26dff; - checkreg A1.x, 0x0000007e; - checkreg ASTAT, (0x44308410 | _VS | _V | _AV0S | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x10a00090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - dmm32 A1.w, 0x8ed084bf; - dmm32 A1.x, 0xffffffbe; - imm32 R0, 0x8000ffff; - imm32 R3, 0xbb4e34ef; - imm32 R5, 0x7af8492d; - R5 = (A1 += R3.L * R0.L) (M, S2RND); - checkreg R5, 0x80000000; - checkreg A1.w, 0xc3bf4fd0; - checkreg A1.x, 0xffffffbe; - checkreg ASTAT, (0x10a00090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x10f04e10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AN | _AZ); - dmm32 A1.w, 0x81becdd8; - dmm32 A1.x, 0x00000058; - imm32 R2, 0x14946201; - imm32 R4, 0x1a162edd; - R2.H = (A1 -= R2.L * R4.L) (M, S2RND); - checkreg R2, 0x7fff6201; - checkreg A1.w, 0x6fce04fb; - checkreg A1.x, 0x00000058; - checkreg ASTAT, (0x10f04e10 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x20f04c80 | _VS | _AV0S | _AN); - dmm32 A1.w, 0xe9cc0041; - dmm32 A1.x, 0x00000079; - imm32 R1, 0x0f62a5a2; - imm32 R3, 0x4e8e9bdd; - imm32 R7, 0x6630d991; - R1 = (A1 -= R3.L * R7.H) (M, S2RND); - checkreg R1, 0x7fffffff; - checkreg A1.w, 0x11c4b8d1; - checkreg A1.x, 0x0000007a; - checkreg ASTAT, (0x20f04c80 | _VS | _V | _AV0S | _V_COPY | _AN); - - dmm32 ASTAT, (0x20104e00 | _VS | _AC1 | _AC0 | _AQ | _AN); - dmm32 A1.w, 0xadeb5c67; - dmm32 A1.x, 0xffffffa6; - imm32 R1, 0x07911840; - imm32 R7, 0x01070000; - R7 = (A1 += R1.L * R7.H) (M, S2RND); - checkreg R7, 0x80000000; - checkreg A1.w, 0xae044627; - checkreg A1.x, 0xffffffa6; - checkreg ASTAT, (0x20104e00 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x08e04010 | _VS | _AV0S); - dmm32 A1.w, 0xff80f384; - dmm32 A1.x, 0x00000003; - imm32 R1, 0x00000000; - imm32 R2, 0x8000387c; - imm32 R3, 0x1e547fff; - R2.H = (A1 -= R1.L * R3.L) (M, S2RND); - checkreg R2, 0x7fff387c; - checkreg A1.w, 0xff80f384; - checkreg A1.x, 0x00000003; - checkreg ASTAT, (0x08e04010 | _VS | _V | _AV0S | _V_COPY); - - dmm32 ASTAT, (0x0cf08280 | _VS | _AV1S | _AC1 | _CC | _AN); - dmm32 A1.w, 0x80000000; - dmm32 A1.x, 0xffffff80; - imm32 R2, 0xecc35cac; - imm32 R4, 0x00007fff; - imm32 R7, 0x80000000; - R7 = (A1 -= R4.L * R2.L) (M, S2RND); - checkreg R7, 0x80000000; - checkreg A1.w, 0x51aa5cac; - checkreg A1.x, 0xffffff80; - checkreg ASTAT, (0x0cf08280 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x40c08090 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0xfcbe6525; - dmm32 A1.x, 0x00000039; - imm32 R0, 0x0003f3c0; - imm32 R2, 0xfffffffc; - imm32 R6, 0xffff0000; - R0.H = (A1 -= R2.L * R6.H) (M, S2RND); - checkreg R0, 0x7ffff3c0; - checkreg A1.w, 0xfcc26521; - checkreg A1.x, 0x00000039; - checkreg ASTAT, (0x40c08090 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x00704c10 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY); - dmm32 A1.w, 0xdfbb3c19; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x50407788; - imm32 R4, 0x50407788; - imm32 R6, 0x0d3f0c0a; - R6.H = (A1 -= R4.L * R0.L) (M, S2RND); - checkreg R6, 0x7fff0c0a; - checkreg A1.w, 0xa7eb83d9; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x00704c10 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x3c50c610 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); - dmm32 A1.w, 0xbc7ca70b; - dmm32 A1.x, 0xffffff80; - imm32 R1, 0x76b3a772; - imm32 R2, 0x5cc87864; - imm32 R5, 0x33169c34; - R1 = (A1 += R2.L * R5.H) (M, S2RND); - checkreg R1, 0x80000000; - checkreg A1.w, 0xd482eba3; - checkreg A1.x, 0xffffff80; - checkreg ASTAT, (0x3c50c610 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x50008480 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY); - dmm32 A1.w, 0xd843bd0f; - dmm32 A1.x, 0x00000027; - imm32 R0, 0xc5d36b7c; - imm32 R7, 0x7fff8000; - R0.H = (A1 += R0.L * R7.L) (M, S2RND); - checkreg R0, 0x7fff6b7c; - checkreg A1.w, 0x0e01bd0f; - checkreg A1.x, 0x00000028; - checkreg ASTAT, (0x50008480 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x50208610 | _VS | _V | _AV1S | _AV0S | _V_COPY | _AN); - dmm32 A1.w, 0xcf30f0be; - dmm32 A1.x, 0xffffffad; - imm32 R0, 0x6d8f3470; - imm32 R4, 0x4174b386; - imm32 R6, 0x0793b3dd; - R0.H = (A1 -= R4.L * R6.H) (M, S2RND); - checkreg R0, 0x80003470; - checkreg A1.w, 0xd17430cc; - checkreg A1.x, 0xffffffad; - checkreg ASTAT, (0x50208610 | _VS | _V | _AV1S | _AV0S | _V_COPY | _AN); - - dmm32 ASTAT, (0x60700c10 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY); - dmm32 A1.w, 0xc867b111; - dmm32 A1.x, 0xffffff90; - imm32 R4, 0x580f445e; - imm32 R5, 0x1fb2e64b; - imm32 R6, 0xb6bc814b; - R6.H = (A1 += R5.L * R4.L) (M, S2RND); - checkreg R6, 0x8000814b; - checkreg A1.w, 0xc18a2c9b; - checkreg A1.x, 0xffffff90; - checkreg ASTAT, (0x60700c10 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x4070c080 | _AV0S | _CC); - dmm32 A1.w, 0xe1239b9f; - dmm32 A1.x, 0xffffffcd; - imm32 R4, 0xe4d2beb4; - imm32 R5, 0x1c919600; - imm32 R6, 0x18356124; - R5.H = (A1 -= R4.L * R6.L) (M, S2RND); - checkreg R5, 0x80009600; - checkreg A1.w, 0xf9ea964f; - checkreg A1.x, 0xffffffcd; - checkreg ASTAT, (0x4070c080 | _VS | _V | _AV0S | _CC | _V_COPY); - - dmm32 ASTAT, (0x50608210 | _VS | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0xe8c00d5a; - dmm32 A1.x, 0xffffffbe; - imm32 R1, 0x2baf99f2; - imm32 R4, 0x03e69887; - imm32 R7, 0x07f45a0f; - R1 = (A1 -= R7.L * R4.H) (M, S2RND); - checkreg R1, 0x80000000; - checkreg A1.w, 0xe760f6e0; - checkreg A1.x, 0xffffffbe; - checkreg ASTAT, (0x50608210 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0029.S b/sim/testsuite/sim/bfin/random_0029.S deleted file mode 100644 index c754995..0000000 --- a/sim/testsuite/sim/bfin/random_0029.S +++ /dev/null @@ -1,184 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x2030ca00 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); - dmm32 A1.w, 0xdf7ce5c7; - dmm32 A1.x, 0xffffff9c; - imm32 R0, 0x098ecb70; - imm32 R1, 0x80000000; - R1.H = (A1 += R0.L * R1.H) (M, ISS2); - checkreg R1, 0x80000000; - checkreg A1.w, 0xc534e5c7; - checkreg A1.x, 0xffffff9c; - checkreg ASTAT, (0x2030ca00 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x00100600 | _VS | _AQ | _AZ); - dmm32 A1.w, 0xdf39474d; - dmm32 A1.x, 0xffffffd9; - imm32 R2, 0x64864b87; - imm32 R3, 0x61a97f85; - imm32 R6, 0x1bcacb1a; - R2.H = (A1 -= R6.L * R3.L) (M, ISS2); - checkreg R2, 0x80004b87; - checkreg A1.w, 0xf992dccb; - checkreg A1.x, 0xffffffd9; - checkreg ASTAT, (0x00100600 | _VS | _V | _AQ | _V_COPY | _AZ); - - dmm32 ASTAT, (0x50f0c290 | _VS | _AC0 | _AQ | _CC | _AC0_COPY); - dmm32 A1.w, 0xb0a49eb4; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x1a1607f3; - imm32 R1, 0x6dcc7fff; - imm32 R6, 0x80008000; - R6.H = (A1 -= R1.L * R0.H) (M, ISS2); - checkreg R6, 0x7fff8000; - checkreg A1.w, 0xa399b8ca; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x50f0c290 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x48b04c10 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0x91b35cde; - dmm32 A1.x, 0x0000006c; - imm32 R1, 0xf473c458; - imm32 R5, 0x1358b0c2; - imm32 R7, 0xfbf00410; - R5.H = (A1 -= R1.L * R7.H) (M, ISS2); - checkreg R5, 0x7fffb0c2; - checkreg A1.w, 0xcc69025e; - checkreg A1.x, 0x0000006c; - checkreg ASTAT, (0x48b04c10 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x1ca04210 | _VS | _AC0 | _AQ | _AN | _AZ); - dmm32 A1.w, 0xf516677c; - dmm32 A1.x, 0x00000015; - imm32 R5, 0x218d4960; - imm32 R6, 0xfa8c8000; - R5 = (A1 -= R6.L * R5.H) (M, ISS2); - checkreg R5, 0x7fffffff; - checkreg A1.w, 0x05dce77c; - checkreg A1.x, 0x00000016; - checkreg ASTAT, (0x1ca04210 | _VS | _V | _AC0 | _AQ | _V_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x04004490 | _VS | _AC1 | _AN); - dmm32 A1.w, 0xd1795d0a; - dmm32 A1.x, 0x00000000; - imm32 R2, 0x67bd270e; - imm32 R3, 0xda302534; - imm32 R7, 0x7fffa2af; - R2.H = (A1 += R7.L * R3.L) (M, ISS2); - checkreg R2, 0x7fff270e; - checkreg A1.w, 0xc3e9b396; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x04004490 | _VS | _V | _AC1 | _V_COPY | _AN); - - dmm32 ASTAT, (0x60600490 | _VS | _AV1S | _AC1 | _CC | _AC0_COPY | _AZ); - dmm32 A1.w, 0xeb8abaea; - dmm32 A1.x, 0x00000036; - imm32 R1, 0x111687e8; - imm32 R5, 0x111687e8; - R1 = (A1 += R1.L * R5.L) (M, ISS2); - checkreg R1, 0x7fffffff; - checkreg A1.w, 0xabc93d2a; - checkreg A1.x, 0x00000036; - checkreg ASTAT, (0x60600490 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ); - - dmm32 ASTAT, (0x30200e80 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY | _AN); - dmm32 A1.w, 0xd3275e78; - dmm32 A1.x, 0xffffff89; - imm32 R3, 0xfee80d8d; - imm32 R6, 0x1c1a8000; - imm32 R7, 0x00000000; - R3 = (A1 += R7.L * R6.L) (M, ISS2); - checkreg R3, 0x80000000; - checkreg A1.w, 0xd3275e78; - checkreg A1.x, 0xffffff89; - checkreg ASTAT, (0x30200e80 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x50208610 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY); - dmm32 A1.w, 0xb3b71810; - dmm32 A1.x, 0x00000000; - imm32 R4, 0xfc2f7ffe; - imm32 R5, 0x7fffffff; - imm32 R7, 0x3488c040; - R7.H = (A1 -= R4.L * R5.H) (M, ISS2); - checkreg R7, 0x7fffc040; - checkreg A1.w, 0x73b8980e; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x50208610 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x48d04410 | _VS | _AV1S | _AV0S | _AC0 | _AQ); - dmm32 A1.w, 0xeb066305; - dmm32 A1.x, 0xffffff9c; - imm32 R0, 0x80002105; - imm32 R4, 0xf4fbe11e; - imm32 R7, 0xffffb83a; - R7 = (A1 += R0.L * R4.L) (M, ISS2); - checkreg R7, 0x80000000; - checkreg A1.w, 0x080fa69b; - checkreg A1.x, 0xffffff9d; - checkreg ASTAT, (0x48d04410 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x3850c090 | _VS | _AV1S | _AV0S | _AC1 | _CC); - dmm32 A1.w, 0xdfed6537; - dmm32 A1.x, 0xffffffae; - imm32 R0, 0xe962c700; - imm32 R4, 0x32c97fff; - imm32 R7, 0x28da7373; - R4.H = (A1 += R7.L * R0.H) (M, ISS2); - checkreg R4, 0x80007fff; - checkreg A1.w, 0x492d423d; - checkreg A1.x, 0xffffffaf; - checkreg ASTAT, (0x3850c090 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY); - - dmm32 ASTAT, (0x78a0ce00 | _VS | _AV1S | _AC0 | _AQ | _CC); - dmm32 A1.w, 0x8c733a78; - dmm32 A1.x, 0x0000002d; - imm32 R1, 0x3840acb0; - imm32 R3, 0x47b843ad; - imm32 R7, 0x7fff4d00; - R7 = (A1 += R1.L * R3.H) (M, ISS2); - checkreg R7, 0x7fffffff; - checkreg A1.w, 0x751c28f8; - checkreg A1.x, 0x0000002d; - checkreg ASTAT, (0x78a0ce00 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x3cf08880 | _VS | _AV1S | _AV0S | _AC0); - dmm32 A1.w, 0xbde0b55f; - dmm32 A1.x, 0xfffffffd; - imm32 R0, 0x80002300; - imm32 R5, 0x635db45a; - imm32 R7, 0x67e67af3; - R7 = (A1 += R0.L * R5.L) (M, ISS2); - checkreg R7, 0x80000000; - checkreg A1.w, 0xd689035f; - checkreg A1.x, 0xfffffffd; - checkreg ASTAT, (0x3cf08880 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY); - - dmm32 ASTAT, (0x58608410 | _VS | _AQ | _CC | _AZ); - dmm32 A1.w, 0xe4660b32; - dmm32 A1.x, 0xffffff84; - imm32 R1, 0x2c6c9118; - imm32 R2, 0x007793ad; - imm32 R7, 0x526c17d9; - R1.H = (A1 -= R2.L * R7.L) (M, ISS2); - checkreg R1, 0x80009118; - checkreg A1.w, 0xee7d528d; - checkreg A1.x, 0xffffff84; - checkreg ASTAT, (0x58608410 | _VS | _V | _AQ | _CC | _V_COPY | _AZ); - - dmm32 ASTAT, (0x2020c210 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN); - dmm32 A1.w, 0x8da6c28f; - dmm32 A1.x, 0x00000000; - imm32 R1, 0x0000fff7; - imm32 R4, 0xf85a0000; - imm32 R7, 0x7fff0000; - R7 = (A1 += R4.L * R1.L) (M, ISS2); - checkreg R7, 0x7fffffff; - checkreg A1.w, 0x8da6c28f; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x2020c210 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0030.S b/sim/testsuite/sim/bfin/random_0030.S deleted file mode 100644 index 417fb28..0000000 --- a/sim/testsuite/sim/bfin/random_0030.S +++ /dev/null @@ -1,177 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x00a0cc80 | _VS | _AV1S | _AQ | _CC | _AN); - dmm32 A1.w, 0x8f7fea28; - dmm32 A1.x, 0x00000005; - imm32 R2, 0x000014f2; - imm32 R4, 0x7fff7fff; - imm32 R7, 0x14d3a258; - R7.H = (A1 -= R4.L * R2.H) (M, T); - checkreg R7, 0x7fffa258; - checkreg A1.w, 0x8f7fea28; - checkreg A1.x, 0x00000005; - checkreg ASTAT, (0x00a0cc80 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x7c90c410 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY); - dmm32 A1.w, 0xbfed6ffc; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x7fffffff; - imm32 R5, 0x00000000; - imm32 R6, 0xf70a7fff; - R0.H = (A1 -= R5.L * R6.L) (M, T); - checkreg ASTAT, (0x7c90c410 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY); - checkreg A1.w, 0xbfed6ffc; - checkreg A1.x, 0x00000000; - checkreg R0, 0x7fffffff; - checkreg R5, 0x00000000; - checkreg R6, 0xf70a7fff; - - dmm32 ASTAT, (0x2c508a10 | _VS | _AV1S | _AV0S | _AC1 | _AQ); - dmm32 A1.w, 0xfffd8001; - dmm32 A1.x, 0x00000000; - imm32 R3, 0x00018000; - imm32 R4, 0x7fff8000; - imm32 R5, 0x7fff0002; - R3.H = (A1 += R5.L * R4.L) (M, T); - checkreg R3, 0x7fff8000; - checkreg A1.w, 0xfffe8001; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x2c508a10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x28408c90 | _VS | _AV1S | _AC0 | _AQ | _AC0_COPY | _AN); - dmm32 A1.w, 0x842fbc0a; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x04c44422; - imm32 R3, 0x40f67fff; - imm32 R7, 0x448c0856; - R7.H = (A1 -= R3.L * R0.H) (M, T); - checkreg R7, 0x7fff0856; - checkreg A1.w, 0x81cdc0ce; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x28408c90 | _VS | _V | _AV1S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x44708c10 | _AV1S | _CC | _AC0_COPY | _AN); - dmm32 A1.w, 0xaa016cf5; - dmm32 A1.x, 0xffffffdb; - imm32 R2, 0x25908079; - imm32 R5, 0x46eabfcd; - imm32 R7, 0x67066230; - R2.H = (A1 += R5.L * R7.H) (M, T); - checkreg R2, 0x80008079; - checkreg A1.w, 0x902b66c3; - checkreg A1.x, 0xffffffdb; - checkreg ASTAT, (0x44708c10 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x3c604090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - dmm32 A1.w, 0x8eef28b0; - dmm32 A1.x, 0x00000023; - imm32 R0, 0x000156b2; - imm32 R1, 0xfc1a8000; - imm32 R5, 0x7fff7fff; - R5.H = (A1 += R1.L * R0.H) (M, T); - checkreg A1.w, 0x8eeea8b0; - checkreg A1.x, 0x00000023; - checkreg ASTAT, (0x3c604090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x74208e00 | _VS | _AV0S | _AC0 | _AQ | _AC0_COPY); - dmm32 A1.w, 0xed3c9973; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x80000000; - imm32 R1, 0x7fff8000; - imm32 R2, 0x00000000; - R1.H = (A1 -= R2.L * R0.H) (M, T); - checkreg ASTAT, (0x74208e00 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY); - checkreg A1.w, 0xed3c9973; - checkreg A1.x, 0x00000000; - checkreg R0, 0x80000000; - checkreg R1, 0x7fff8000; - checkreg R2, 0x00000000; - - dmm32 ASTAT, (0x10308800 | _VS | _AV0S | _AC0 | _AC0_COPY); - dmm32 A1.w, 0x8b345e6e; - dmm32 A1.x, 0x00000000; - imm32 R3, 0xc40c1663; - imm32 R4, 0xd0347fff; - imm32 R7, 0x4249da20; - R3.H = (A1 += R4.L * R7.H) (M, T); - checkreg R3, 0x7fff1663; - checkreg A1.w, 0xac589c25; - checkreg A1.x, 0x00000000; - checkreg ASTAT, (0x10308800 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x1c104880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AZ); - dmm32 A1.w, 0xa333ecbc; - dmm32 A1.x, 0xffffffea; - imm32 R2, 0x7fffffff; - imm32 R3, 0x72ea7fff; - imm32 R4, 0x07348ad1; - R4.H = (A1 += R2.L * R3.L) (M, T); - checkreg R4, 0x80008ad1; - checkreg A1.w, 0xa3336cbd; - checkreg A1.x, 0xffffffea; - checkreg ASTAT, (0x1c104880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AZ); - - dmm32 ASTAT, (0x44904e00 | _VS); - dmm32 A1.w, 0x90202372; - dmm32 A1.x, 0xffffffc4; - imm32 R2, 0x138ac9fc; - imm32 R3, 0x720a427f; - imm32 R4, 0x800000f5; - R3.H = (A1 += R4.L * R2.H) (M, T); - checkreg R3, 0x8000427f; - checkreg A1.w, 0x9032d684; - checkreg A1.x, 0xffffffc4; - checkreg ASTAT, (0x44904e00 | _VS | _V | _V_COPY); - - dmm32 ASTAT, (0x48f04c90 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN); - dmm32 A1.w, 0xe9c97364; - dmm32 A1.x, 0xffffffef; - imm32 R2, 0x001dffe9; - imm32 R3, 0x50f06d20; - imm32 R6, 0x6179b75b; - R6.H = (A1 -= R3.L * R2.L) (M, T); - checkreg R6, 0x8000b75b; - checkreg A1.w, 0x7cb34144; - checkreg A1.x, 0xffffffef; - checkreg ASTAT, (0x48f04c90 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x68d00e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - dmm32 A1.w, 0xf3d34812; - dmm32 A1.x, 0xffffff95; - imm32 R1, 0xf7419a18; - imm32 R6, 0x0fdf83b3; - imm32 R7, 0x0b831070; - R7.H = (A1 -= R6.L * R1.H) (M, T); - checkreg R7, 0x80001070; - checkreg A1.w, 0x6be1229f; - checkreg A1.x, 0xffffff96; - checkreg ASTAT, (0x68d00e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x3060ce80 | _VS | _AV1S | _AC1 | _CC | _AN); - dmm32 A1.w, 0xe0c1fc60; - dmm32 A1.x, 0x00000000; - imm32 R1, 0x00e97fff; - imm32 R7, 0x3fff0001; - R1.H = (A1 += R1.L * R7.H) (M, T); - checkreg R1, 0x7fff7fff; - checkreg A1.w, 0x00c13c61; - checkreg A1.x, 0x00000001; - checkreg ASTAT, (0x3060ce80 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x3c80c000 | _VS | _AV0S | _AC0_COPY | _AN); - dmm32 A1.w, 0xb0e43973; - dmm32 A1.x, 0xffffffbc; - imm32 R0, 0x511a6fe3; - imm32 R1, 0x43fe2c80; - imm32 R2, 0x424b5c19; - R0.H = (A1 -= R2.L * R1.H) (M, T); - checkreg R0, 0x80006fe3; - checkreg A1.w, 0x986e4da5; - checkreg A1.x, 0xffffffbc; - checkreg ASTAT, (0x3c80c000 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0031.S b/sim/testsuite/sim/bfin/random_0031.S deleted file mode 100644 index 4a849e1..0000000 --- a/sim/testsuite/sim/bfin/random_0031.S +++ /dev/null @@ -1,185 +0,0 @@ -# Check that VS in ASTAT is set with add/sub insns (and not just V) -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x2810c010 | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - imm32 R0, 0x27f3a149; - imm32 R3, 0x3cae7c58; - imm32 R4, 0x33c97634; - R3.H = R0.L - R4.H (NS); - checkreg R3, 0x6d807c58; - checkreg ASTAT, (0x2810c010 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x64c00680 | _AQ | _AC0_COPY); - imm32 R1, 0x1b7b025c; - imm32 R5, 0x1ba46ce6; - R5.L = R5.L + R1.H (NS); - checkreg R5, 0x1ba48861; - checkreg ASTAT, (0x64c00680 | _VS | _V | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x68b04200 | _AV1S | _AV0 | _AC0 | _AQ | _AN); - imm32 R3, 0x4b91870f; - imm32 R6, 0x5972bae0; - imm32 R7, 0x31f7dfb7; - R7.H = R6.L + R3.L (S); - checkreg R7, 0x8000dfb7; - checkreg ASTAT, (0x68b04200 | _VS | _V | _AV1S | _AV0 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x78208e90 | _CC | _AN); - imm32 R3, 0x40b63bc7; - imm32 R5, 0x49c89df9; - R3.H = R5.L - R3.H (NS); - checkreg R3, 0x5d433bc7; - checkreg ASTAT, (0x78208e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x00904680 | _AV1S | _AV1 | _AV0 | _AC1 | _AQ | _AZ); - imm32 R2, 0x23a2c115; - imm32 R4, 0x6977581e; - imm32 R6, 0x41900942; - R4.L = R2.L - R6.H (NS); - checkreg R4, 0x69777f85; - checkreg ASTAT, (0x00904680 | _VS | _V | _AV1S | _AV1 | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x78d08210 | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ); - imm32 R0, 0x4317139e; - imm32 R1, 0x49ed40d6; - R0.L = R1.L + R0.H (NS); - checkreg R0, 0x431783ed; - checkreg ASTAT, (0x78d08210 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AN); - - dmm32 ASTAT, (0x58d00e10 | _AV1 | _AQ | _CC); - imm32 R0, 0x09ea77a2; - imm32 R1, 0x6ccd0b05; - imm32 R2, 0x761c63af; - R1.H = R0.L + R2.H (NS); - checkreg R1, 0xedbe0b05; - checkreg ASTAT, (0x58d00e10 | _VS | _V | _AV1 | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x30c08000 | _AC0 | _AQ | _AC0_COPY); - imm32 R4, 0x36d243cb; - imm32 R5, 0xcd127add; - R4.H = R5.L + R4.L (NS); - checkreg R4, 0xbea843cb; - checkreg ASTAT, (0x30c08000 | _VS | _V | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x74108400 | _V | _AV1 | _AC1 | _AC0 | _AC0_COPY); - imm32 R0, 0x4e1893ea; - imm32 R1, 0x13cf5cc8; - imm32 R3, 0x7441949e; - R1.L = R0.L - R3.H (NS); - checkreg R1, 0x13cf1fa9; - checkreg ASTAT, (0x74108400 | _VS | _V | _AV1 | _AC1 | _AC0 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x7420ce10 | _AV1S | _AV1 | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN | _AZ); - imm32 R4, 0x532c8fb1; - imm32 R6, 0x582420d2; - R6.H = R4.L - R4.H (NS); - checkreg R6, 0x3c8520d2; - checkreg ASTAT, (0x7420ce10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x74704010 | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY); - imm32 R3, 0x6f6a7429; - imm32 R5, 0x2ea5c47e; - R5.H = R5.L - R3.H (NS); - checkreg R5, 0x5514c47e; - checkreg ASTAT, (0x74704010 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x0ce08490 | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AZ); - imm32 R1, 0xfd18a0b0; - imm32 R4, 0x259e2151; - R4.L = R1.L - R4.H (NS); - checkreg R4, 0x259e7b12; - checkreg ASTAT, (0x0ce08490 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x54b08810 | _V | _AV1S | _AV0S | _AC0_COPY | _AN); - imm32 R3, 0x7a763675; - imm32 R6, 0x23c4a335; - R3.L = R6.L + R6.L (NS); - checkreg R3, 0x7a76466a; - checkreg ASTAT, (0x54b08810 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x70f0c080 | _AV1S | _AV0S | _AC0); - imm32 R4, 0x55fab7e4; - imm32 R5, 0x7dbd9b06; - R5.H = R5.L - R4.H (S); - checkreg R5, 0x80009b06; - checkreg ASTAT, (0x70f0c080 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x5ce04680 | _AV0 | _AC0 | _V_COPY | _AC0_COPY | _AN); - imm32 R0, 0x19cacbdb; - imm32 R2, 0x151cb293; - imm32 R4, 0x571c351a; - R0.H = R4.L - R2.L (S); - checkreg R0, 0x7fffcbdb; - checkreg ASTAT, (0x5ce04680 | _VS | _V | _AV0 | _V_COPY); - - dmm32 ASTAT, (0x0c604a00 | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AZ); - imm32 R3, 0x5432c45d; - imm32 R6, 0x62519952; - R3.L = R6.L + R6.L (S); - checkreg R3, 0x54328000; - checkreg ASTAT, (0x0c604a00 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x58708c90 | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN | _AZ); - imm32 R0, 0x1f3f3c0e; - imm32 R4, 0x5fae58d2; - R0.H = R0.L + R4.L (NS); - checkreg R0, 0x94e03c0e; - checkreg ASTAT, (0x58708c90 | _VS | _V | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x34b00a00 | _V | _AV1S | _AC1 | _CC | _V_COPY | _AZ); - imm32 R3, 0x6ea226dc; - imm32 R4, 0x045c6d64; - imm32 R7, 0x7e599a25; - R7.L = R3.L + R4.L (NS); - checkreg R7, 0x7e599440; - checkreg ASTAT, (0x34b00a00 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x40a0c010 | _AV1S | _AC0); - imm32 R2, 0x641501ef; - imm32 R7, 0x3acb49aa; - R2.H = R7.L + R7.H (NS); - checkreg R2, 0x847501ef; - checkreg ASTAT, (0x40a0c010 | _VS | _V | _AV1S | _V_COPY | _AN); - - dmm32 ASTAT, (0x78f04090 | _AV1S | _AC1 | _AQ | _CC | _AZ); - imm32 R2, 0x65681fdf; - imm32 R3, 0x5fffe0d3; - imm32 R5, 0x37df99cd; - R2.H = R5.L - R3.H (NS); - checkreg R2, 0x39ce1fdf; - checkreg ASTAT, (0x78f04090 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x0cc04e10 | _AV1S | _AQ | _CC); - imm32 R3, 0x571977df; - imm32 R4, 0x029671d0; - R3.L = R4.L + R3.H (NS); - checkreg R3, 0x5719c8e9; - checkreg ASTAT, (0x0cc04e10 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x00104880 | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); - imm32 R0, 0x4c98aa07; - imm32 R4, 0x5e9da59f; - R4.H = R0.L + R0.L (S); - checkreg R4, 0x8000a59f; - checkreg ASTAT, (0x00104880 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x08008c00 | _AV1S | _AV0S | _AV0 | _CC | _AC0_COPY); - imm32 R4, 0x58ee2400; - imm32 R6, 0x2e97af3e; - R4.L = R6.L + R6.L (NS); - checkreg R4, 0x58ee5e7c; - checkreg ASTAT, (0x08008c00 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x2ce0c290 | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); - imm32 R2, 0x2d467e64; - imm32 R6, 0x31aeb601; - imm32 R7, 0x1523a746; - R7.L = R2.L - R6.L (S); - checkreg R7, 0x15237fff; - checkreg ASTAT, (0x2ce0c290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/random_0032.S b/sim/testsuite/sim/bfin/random_0032.S deleted file mode 100644 index bfded41..0000000 --- a/sim/testsuite/sim/bfin/random_0032.S +++ /dev/null @@ -1,154 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x74308400 | _VS | _AV1S | _AV0S | _CC | _AN); - dmm32 A0.w, 0x5d4cf98c; - dmm32 A0.x, 0xffffffff; - imm32 R0, 0xba16ffff; - imm32 R4, 0x8000109d; - imm32 R6, 0x8000b212; - R6.L = (A0 -= R4.L * R0.L) (IH); - checkreg R6, 0x80008000; - checkreg A0.w, 0x80000000; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x74308400 | _VS | _V | _AV1S | _AV0S | _AV0 | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x34e0ce80 | _VS | _V | _AV1S | _V_COPY | _AN); - dmm32 A0.w, 0x64bb88af; - dmm32 A0.x, 0xffffffff; - imm32 R5, 0x00008000; - imm32 R7, 0x0001ad69; - R5.L = (A0 += R7.H * R7.L) (IH); - checkreg A0.w, 0x80000000; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x34e0ce80 | _VS | _V | _AV1S | _AV0S | _AV0 | _V_COPY | _AN); - - dmm32 ASTAT, (0x4c204c10 | _VS | _V | _AV0S | _AQ | _V_COPY | _AN); - dmm32 A1.w, 0x75642aaf; - dmm32 A1.x, 0xffffffff; - imm32 R2, 0x133dffff; - imm32 R4, 0xc00006aa; - imm32 R7, 0x7fffffff; - R4.H = (A1 -= R2.L * R7.H) (IH); - checkreg R4, 0x800006aa; - checkreg A1.w, 0x80000000; - checkreg A1.x, 0xffffffff; - checkreg ASTAT, (0x4c204c10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x48600400 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AN); - dmm32 A0.w, 0x534a596c; - dmm32 A0.x, 0xffffffff; - imm32 R1, 0x7fff86a7; - imm32 R5, 0x1163d244; - R1.L = (A0 -= R5.L * R1.L) (IH); - checkreg R1, 0x7fff8000; - checkreg A0.w, 0x80000000; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x48600400 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY | _AN); - - dmm32 ASTAT, (0x38008c90 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); - dmm32 A1.w, 0x80000000; - dmm32 A1.x, 0xffffffff; - imm32 R0, 0x7fffffff; - imm32 R1, 0xdee9214c; - imm32 R4, 0x79f3c80a; - R1.H = (A1 += R0.L * R4.H) (M, IH); - checkreg R1, 0x8000214c; - checkreg ASTAT, (0x38008c90 | _VS | _AV1S | _AV1 | _AC1 | _CC | _AN); - - dmm32 ASTAT, (0x4cb00a00 | _VS | _AV1S | _AV0S | _AC1 | _AN); - dmm32 A0.w, 0x804e7e2f; - dmm32 A0.x, 0xffffffff; - imm32 R1, 0x3fccdf09; - imm32 R2, 0x09e71015; - imm32 R6, 0x761ac984; - R2.L = (A0 += R6.L * R1.H) (IH); - checkreg R2, 0x09e78000; - checkreg A0.w, 0x80000000; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x4cb00a00 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _V_COPY | _AN); - - dmm32 ASTAT, (0x08904c00 | _VS | _AV0S | _AQ | _AZ); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R1, 0x80000000; - imm32 R2, 0x0001de54; - imm32 R5, 0x80000000; - R1.L = (A0 -= R5.H * R2.H) (TFU); - checkreg ASTAT, (0x08904c00 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R1, 0x80000000; - checkreg R2, 0x0001de54; - checkreg R5, 0x80000000; - - dmm32 ASTAT, (0x00d04810 | _VS | _AV0S | _CC | _AC0_COPY | _AZ); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R4, 0x00020000; - imm32 R5, 0x35a26677; - R4.L = (A0 -= R5.H * R4.H) (TFU); - checkreg ASTAT, (0x00d04810 | _VS | _V | _AV0S | _AV0 | _CC | _V_COPY | _AC0_COPY | _AZ); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg R4, 0x00020000; - checkreg R5, 0x35a26677; - - dmm32 ASTAT, (0x08100a80 | _VS | _AV0S | _AQ | _CC); - dmm32 A0.w, 0x00000000; - dmm32 A0.x, 0x00000000; - imm32 R0, 0x000300cc; - imm32 R4, 0x00029150; - imm32 R7, 0x00ff00ff; - R4.L = (A0 -= R0.L * R7.L) (IU); - checkreg R4, 0x00020000; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x08100a80 | _VS | _V | _AV0S | _AV0 | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x6c20c400 | _VS | _AV1S | _AV0S | _CC); - dmm32 A0.w, 0x860c9ac9; - dmm32 A0.x, 0xffffffff; - imm32 R2, 0x860c9a1b; - R2.L = (A0 -= R2.H * R2.L) (IH); - checkreg R2, 0x860c8000; - checkreg A0.w, 0x80000000; - checkreg A0.x, 0xffffffff; - checkreg ASTAT, (0x6c20c400 | _VS | _V | _AV1S | _AV0S | _AV0 | _CC | _V_COPY); - - dmm32 ASTAT, (0x20f00c10 | _VS | _AV0S | _AQ); - dmm32 A0.w, 0x0000de90; - dmm32 A0.x, 0x00000000; - imm32 R0, 0x00000003; - imm32 R1, 0xfffd8000; - imm32 R5, 0x4a31921c; - R1.L = (A0 -= R5.L * R0.L) (FU); - checkreg R1, 0xfffd0000; - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg ASTAT, (0x20f00c10 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x38700690 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY); - dmm32 A1.w, 0x00000000; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x58863d39; - imm32 R1, 0x45377355; - imm32 R6, 0x00030000; - R1.H = (A1 -= R0.L * R6.H) (TFU); - checkreg R1, 0x00007355; - checkreg ASTAT, (0x38700690 | _VS | _V | _AV1S | _AV1 | _AC1 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x48704880 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); - dmm32 A0.w, 0x7fffd68a; - dmm32 A0.x, 0xffffffff; - imm32 R7, 0x06d88000; - R7.L = A0 (IH); - checkreg A0.w, 0x7fffd68a; - checkreg A0.x, 0xffffffff; - checkreg R7, 0x06d88000; - checkreg ASTAT, (0x48704880 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0033.S b/sim/testsuite/sim/bfin/random_0033.S deleted file mode 100644 index 4835396..0000000 --- a/sim/testsuite/sim/bfin/random_0033.S +++ /dev/null @@ -1,64 +0,0 @@ -# Verify registers saturate and ASTAT bits are updated correctly -# with the RND12 subtract insn -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x24a00410 | _VS | _AV1S | _AV0 | _AC0 | _AC0_COPY | _AN); - imm32 R5, 0x0fb35119; - imm32 R6, 0xffffffff; - imm32 R7, 0x80000000; - R6.H = R5 - R7 (RND12); - checkreg R6, 0x7fffffff; - checkreg ASTAT, (0x24a00410 | _VS | _V | _AV1S | _AV0 | _AC0 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x08c08000 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); - imm32 R3, 0x80003f8f; - imm32 R5, 0x6267c92c; - imm32 R6, 0x80000000; - R5.L = R3 - R6 (RND12); - checkreg R5, 0x62670004; - checkreg ASTAT, (0x08c08000 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); - - dmm32 ASTAT, (0x04200c10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY); - imm32 R1, 0x7fff0000; - imm32 R5, 0x80000000; - R1.L = R5 - R5 (RND12); - checkreg ASTAT, (0x04200c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AZ); - checkreg R1, 0x7fff0000; - checkreg R5, 0x80000000; - - dmm32 ASTAT, (0x40600e90 | _VS | _AV1S | _AV0S | _AQ | _CC); - imm32 R1, 0x80000000; - imm32 R5, 0x00008000; - imm32 R6, 0x00000000; - R5.L = R6 - R1 (RND12); - checkreg R5, 0x00007fff; - checkreg ASTAT, (0x40600e90 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY); - - dmm32 ASTAT, (0x68300880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ); - imm32 R1, 0xf8ed0000; - imm32 R6, 0x80000000; - R1.H = R1 - R6 (RND12); - checkreg R1, 0x7fff0000; - checkreg ASTAT, (0x68300880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x70d0c410 | _VS | _AV0S | _AQ); - imm32 R0, 0x80000000; - imm32 R1, 0x71455f95; - imm32 R4, 0xd4871012; - R4.H = R1 - R0 (RND12); - checkreg R4, 0x7fff1012; - checkreg ASTAT, (0x70d0c410 | _VS | _V | _AV0S | _AQ | _V_COPY); - - dmm32 ASTAT, (0x34500e00 | _VS | _AV0S | _AC1 | _CC | _AZ); - imm32 R2, 0x00000000; - imm32 R5, 0x00000000; - imm32 R6, 0x80000000; - R2.L = R5 - R6 (RND12); - checkreg R2, 0x00007fff; - checkreg ASTAT, (0x34500e00 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/random_0034.S b/sim/testsuite/sim/bfin/random_0034.S deleted file mode 100644 index 7aeaadb..0000000 --- a/sim/testsuite/sim/bfin/random_0034.S +++ /dev/null @@ -1,129 +0,0 @@ -# Verify sign extension behavior with simultaneous acc additions, and -# verify that no ASTAT bits get changed as a result -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ); - dmm32 A0.w, 0x589145b7; - dmm32 A0.x, 0xffffffee; - dmm32 A1.w, 0x0b247b05; - dmm32 A1.x, 0x0000005a; - imm32 R3, 0x1e414332; - imm32 R4, 0x351715b7; - R3 = A1.L + A1.H, R4 = A0.L + A0.H; - checkreg R3, 0x00008629; - checkreg R4, 0x00009e48; - checkreg ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ); - - dmm32 ASTAT, (0x40e0cc00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0xb2c58001; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xe999dc28; - dmm32 A1.x, 0xffffffff; - imm32 R0, 0xe58d5ffa; - imm32 R4, 0x7fff7fff; - R0 = A1.L + A1.H, R4 = A0.L + A0.H; - checkreg R0, 0xffffc5c1; - checkreg R4, 0xffff32c6; - checkreg ASTAT, (0x40e0cc00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x3420ca80 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC); - dmm32 A0.w, 0xeff48350; - dmm32 A0.x, 0xffffffff; - dmm32 A1.w, 0x5a3f623a; - dmm32 A1.x, 0xffffffff; - imm32 R4, 0xffff152f; - imm32 R6, 0xdd13218a; - R4 = A1.L + A1.H, R6 = A0.L + A0.H; - checkreg R4, 0x0000bc79; - checkreg R6, 0xffff7344; - checkreg ASTAT, (0x3420ca80 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC); - - dmm32 ASTAT, (0x10204880 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AN); - dmm32 A0.w, 0x6da679bb; - dmm32 A0.x, 0xffffff96; - dmm32 A1.w, 0x1f5fb024; - dmm32 A1.x, 0x00000000; - imm32 R3, 0x3ebf8000; - imm32 R6, 0x025f2e8c; - R6 = A1.L + A1.H, R3 = A0.L + A0.H; - checkreg R3, 0x0000e761; - checkreg R6, 0xffffcf83; - checkreg ASTAT, (0x10204880 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AN); - - dmm32 ASTAT, (0x6ca00c90 | _V | _AV1S | _AV1 | _AC0_COPY | _AN | _AZ); - dmm32 A0.w, 0x59abaa84; - dmm32 A0.x, 0xffffffe1; - dmm32 A1.w, 0x71541efe; - dmm32 A1.x, 0x00000009; - imm32 R0, 0x2c41e797; - imm32 R5, 0x7bfa5e8a; - R0 = A1.L + A1.H, R5 = A0.L + A0.H; - checkreg R0, 0x00009052; - checkreg R5, 0x0000042f; - checkreg ASTAT, (0x6ca00c90 | _V | _AV1S | _AV1 | _AC0_COPY | _AN | _AZ); - - dmm32 ASTAT, (0x1c50c290 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AN); - dmm32 A0.w, 0xffffffff; - dmm32 A0.x, 0xffffffff; - dmm32 A1.w, 0xc49ca8db; - dmm32 A1.x, 0xffffffff; - imm32 R3, 0x0f62ffff; - imm32 R4, 0x09505188; - R4 = A1.L + A1.H, R3 = A0.L + A0.H; - checkreg R3, 0xfffffffe; - checkreg R4, 0xffff6d77; - checkreg ASTAT, (0x1c50c290 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AN); - - dmm32 ASTAT, (0x70e04a90 | _VS | _AV0S | _AQ); - dmm32 A0.w, 0xd827823e; - dmm32 A0.x, 0xffffffff; - dmm32 A1.w, 0x303d11ba; - dmm32 A1.x, 0x00000000; - imm32 R1, 0x80007fff; - imm32 R6, 0xffc4feb3; - R6 = A1.L + A1.H, R1 = A0.L + A0.H; - checkreg R1, 0xffff5a65; - checkreg R6, 0x000041f7; - checkreg ASTAT, (0x70e04a90 | _VS | _AV0S | _AQ); - - dmm32 ASTAT, (0x5c80c200 | _VS | _AV0S | _AQ | _AC0_COPY | _AN); - dmm32 A0.w, 0x97049850; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xffffa014; - dmm32 A1.x, 0xffffffff; - imm32 R0, 0x04828378; - imm32 R5, 0x3d9effff; - R0 = A1.L + A1.H, R5 = A0.L + A0.H; - checkreg R0, 0xffffa013; - checkreg R5, 0xffff2f54; - checkreg ASTAT, (0x5c80c200 | _VS | _AV0S | _AQ | _AC0_COPY | _AN); - - dmm32 ASTAT, (0x6c604600 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AZ); - dmm32 A0.w, 0xac43c455; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0x03de6f39; - dmm32 A1.x, 0x00000000; - imm32 R0, 0x5bbfd2d1; - imm32 R3, 0x22425ebc; - R3 = A1.L + A1.H, R0 = A0.L + A0.H; - checkreg R0, 0xffff7098; - checkreg R3, 0x00007317; - checkreg ASTAT, (0x6c604600 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AZ); - - dmm32 ASTAT, (0x7cd04280 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - dmm32 A0.w, 0xb63ac8f5; - dmm32 A0.x, 0xffffffe0; - dmm32 A1.w, 0x358b94e8; - dmm32 A1.x, 0x00000000; - imm32 R1, 0x80007fff; - imm32 R6, 0x4f4a8883; - R6 = A1.L + A1.H, R1 = A0.L + A0.H; - checkreg R1, 0xffff7f2f; - checkreg R6, 0xffffca73; - checkreg ASTAT, (0x7cd04280 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); - - pass diff --git a/sim/testsuite/sim/bfin/random_0035.S b/sim/testsuite/sim/bfin/random_0035.S deleted file mode 100644 index 7c10517..0000000 --- a/sim/testsuite/sim/bfin/random_0035.S +++ /dev/null @@ -1,31 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x3080ca10 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY); - dmm32 A0.w, 0xee917987; - dmm32 A0.x, 0x0000007f; - dmm32 A1.w, 0x116e8678; - dmm32 A1.x, 0x00000000; - imm32 R1, 0x4d56fd82; - R1.L = (A0 += A1); - checkreg R1, 0x4d567fff; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0x0000007f; - checkreg ASTAT, (0x3080ca10 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY); - - dmm32 ASTAT, (0x00c04290 | _VS | _V | _AV0S | _V_COPY); - dmm32 A0.w, 0xe4f8e4c1; - dmm32 A0.x, 0x0000007f; - dmm32 A1.w, 0x1b071b3e; - dmm32 A1.x, 0x00000000; - imm32 R1, 0x4b5126c6; - R1.L = (A0 += A1); - checkreg R1, 0x4b517fff; - checkreg A0.w, 0xffffffff; - checkreg A0.x, 0x0000007f; - checkreg ASTAT, (0x00c04290 | _VS | _V | _AV0S | _V_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/random_0036.S b/sim/testsuite/sim/bfin/random_0036.S deleted file mode 100644 index 7e75da9..0000000 --- a/sim/testsuite/sim/bfin/random_0036.S +++ /dev/null @@ -1,309 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x3ce04490 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY); - dmm32 A0.w, 0x7d8d8272; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xe0004138; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0x7d8e7fff; - imm32 R2, 0xffff8001; - A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); - checkreg A0.w, 0xfd8c0273; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x3ce04490 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY); - - dmm32 ASTAT, (0x70b0c800 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0x53931540; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xf07795da; - dmm32 A1.x, 0x0000007f; - imm32 R2, 0x8931da0a; - imm32 R4, 0xffff41eb; - imm32 R5, 0x7fff41eb; - A1 += R5.L * R4.H (M), R2 = (A0 -= R5.L * R4.H) (FU); - checkreg R2, 0x11a8572b; - checkreg A0.w, 0x11a8572b; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x70b0c800 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AC0_COPY); - - dmm32 ASTAT, (0x58100410 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0xaeba0d61; - dmm32 A0.x, 0x00000041; - dmm32 A1.w, 0xbb313d2f; - dmm32 A1.x, 0x0000007f; - imm32 R4, 0x1ea2588d; - imm32 R7, 0xffffffff; - A1 += R4.L * R7.H (M), A0 += R4.L * R7.L (FU); - checkreg A0.w, 0x0746b4d4; - checkreg A0.x, 0x00000042; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x58100410 | _VS | _V | _AV1S | _AV1 | _AC0 | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x58704200 | _VS | _AV1S | _AV0S); - dmm32 A0.w, 0xb7ab4854; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xe0002429; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0xb7ac8000; - imm32 R2, 0x80008001; - A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); - checkreg A0.w, 0xf7ab4854; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x58704200 | _VS | _AV1S | _AV1 | _AV0S); - - dmm32 ASTAT, (0x38d0c800 | _VS | _AV1S | _AV0S); - dmm32 A0.w, 0xfffe0001; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xffff4001; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0xffffffff; - imm32 R2, 0xffffffff; - A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); - checkreg A0.w, 0xfffc0002; - checkreg A0.x, 0x00000001; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x38d0c800 | _VS | _AV1S | _AV1 | _AV0S); - - dmm32 ASTAT, (0x24e0ca80 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY); - dmm32 A0.w, 0x0000000a; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xff5439dc; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0x3ea961c5; - imm32 R6, 0xffff0510; - A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x24e0ca80 | _VS | _V | _AV1S | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x7800cc80 | _VS | _AC1 | _AC0 | _CC | _AC0_COPY); - dmm32 A0.w, 0xfffe0001; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xffff4001; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0xffffffff; - imm32 R2, 0x0000ffff; - A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x7800cc80 | _VS | _AV1S | _AV1 | _AC1 | _AC0 | _CC | _AC0_COPY); - - dmm32 ASTAT, (0x50200800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY); - dmm32 A0.w, 0x6970968f; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xe0004b47; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0x69717fff; - imm32 R2, 0xffff8001; - A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); - checkreg A0.w, 0xe96f1690; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x50200800 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AC0_COPY); - - dmm32 ASTAT, (0x34704080 | _VS | _AV1S | _AV1 | _AV0S | _AQ | _CC | _AC0_COPY); - dmm32 A0.w, 0x0839a708; - dmm32 A0.x, 0xffffff80; - dmm32 A1.w, 0xffffffff; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0x0c8c109a; - imm32 R2, 0x109a0c8c; - imm32 R5, 0x006dd6ac; - A1 -= R5.L * R0.L (M), R2.L = (A0 += R5.H * R0.L) (FU); - checkreg R2, 0x109affff; - checkreg A0.w, 0x0840b89a; - checkreg A0.x, 0xffffff80; - checkreg ASTAT, (0x34704080 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x78108090 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY); - dmm32 A0.w, 0x21edde12; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xe0006f08; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0x21ee7fff; - imm32 R2, 0xffff8001; - A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); - checkreg A0.w, 0xa1ec5e13; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x78108090 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY); - - dmm32 ASTAT, (0x50b08a10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0x00000007; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xf8b109fc; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0x27827703; - imm32 R6, 0xffff03ca; - A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x50b08a10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x34e0c800 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY); - dmm32 A0.w, 0xffffffff; - dmm32 A0.x, 0xffffffff; - dmm32 A1.w, 0xefc2be42; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0x53574850; - imm32 R6, 0xffff1400; - A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU); - checkreg A0.w, 0xaca95356; - checkreg A0.x, 0xffffffff; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x34e0c800 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY); - - dmm32 ASTAT, (0x24608c80 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY); - dmm32 A0.w, 0x0f03f0fc; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xe000787d; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0x0f04ffff; - imm32 R2, 0xffff8001; - A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); - checkreg A0.w, 0x0f01f0fd; - checkreg A0.x, 0x00000001; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x24608c80 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY); - - dmm32 ASTAT, (0x58404690 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); - dmm32 A0.w, 0x1e65e19a; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xe00070cc; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0x1e66ffff; - imm32 R2, 0xffff8001; - A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); - checkreg A0.w, 0x1e63e19b; - checkreg A0.x, 0x00000001; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x58404690 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); - - dmm32 ASTAT, (0x08004a10 | _VS | _AV1S | _AV1 | _AC0 | _CC | _AC0_COPY); - dmm32 A1.w, 0xffffffff; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0x293a8000; - imm32 R3, 0xd0e6382b; - A1 += R3.L * R0.H (M, FU); - checkreg ASTAT, (0x08004a10 | _VS | _AV1S | _AV1 | _AC0 | _CC | _AC0_COPY); - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg R0, 0x293a8000; - checkreg R3, 0xd0e6382b; - - dmm32 ASTAT, (0x28e00e00 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY); - dmm32 A0.w, 0xfffe0001; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xffff4001; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0xffffffff; - imm32 R2, 0x0000ffff; - A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x28e00e00 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY); - - dmm32 ASTAT, (0x14004690 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); - dmm32 A1.w, 0xffffffff; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0x369a8000; - imm32 R3, 0xf023457e; - A1 += R3.L * R0.H (M, FU); - checkreg ASTAT, (0x14004690 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg R0, 0x369a8000; - checkreg R3, 0xf023457e; - - dmm32 ASTAT, (0x5c600680 | _VS | _AV1S | _AQ | _CC); - dmm32 A0.w, 0xfffe0001; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xffff4001; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0xffffffff; - imm32 R2, 0xffffffff; - A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); - checkreg A0.w, 0xfffc0002; - checkreg A0.x, 0x00000001; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x5c600680 | _VS | _AV1S | _AV1 | _AQ | _CC); - - dmm32 ASTAT, (0x7cd00800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY); - dmm32 A0.w, 0xfffe0001; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xffff4001; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0xffffffff; - imm32 R2, 0x0000ffff; - A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x7cd00800 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AC0_COPY); - - dmm32 ASTAT, (0x78e0cc10 | _VS | _AV1S | _AV0S | _AC1); - dmm32 A0.w, 0xfffe0001; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xffff4001; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0xffffffff; - imm32 R2, 0xffffffff; - A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); - checkreg A0.w, 0xfffc0002; - checkreg A0.x, 0x00000001; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x78e0cc10 | _VS | _AV1S | _AV1 | _AV0S | _AC1); - - dmm32 ASTAT, (0x1cd04c80 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0x00000015; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xfeeaa91d; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0x50246875; - imm32 R6, 0xffff0aab; - A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU); - checkreg A0.w, 0x00000000; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x1cd04c80 | _VS | _V | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x18304890 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); - dmm32 A0.w, 0xfffffffe; - dmm32 A0.x, 0xffffffff; - dmm32 A1.w, 0xffffca85; - dmm32 A1.x, 0x0000007f; - imm32 R0, 0xffffffff; - imm32 R3, 0xffffdc58; - imm32 R7, 0xffff950a; - A1 -= R7.L * R0.H (M), R3.L = (A0 -= R7.L * R0.H) (FU); - checkreg R3, 0xffffffff; - checkreg A0.w, 0x6af69508; - checkreg A0.x, 0xffffffff; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x18304890 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/random_0037.S b/sim/testsuite/sim/bfin/random_0037.S deleted file mode 100644 index 05eae8a..0000000 --- a/sim/testsuite/sim/bfin/random_0037.S +++ /dev/null @@ -1,84 +0,0 @@ -# mach: bfin -#include "test.h" -.include "testutils.inc" - - start - - dmm32 ASTAT, (0x1880c200 | _VS | _AV1S | _AV0S | _AC1); - dmm32 A0.w, 0x2b9a5661; - dmm32 A0.x, 0x00000032; - dmm32 A1.w, 0x1a0c4c8c; - dmm32 A1.x, 0xffffff80; - imm32 R0, 0x694a9cb0; - imm32 R6, 0x651cc0dd; - A1 += R0.L * R0.H (M), R6.L = (A0 += R0.L * R0.H) (TFU); - checkreg R6, 0x651cffff; - checkreg A0.w, 0x6c0bd141; - checkreg A0.x, 0x00000032; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0xffffff80; - checkreg ASTAT, (0x1880c200 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _V_COPY); - - dmm32 ASTAT, (0x14104490 | _VS | _AV1S | _AZ); - dmm32 A0.w, 0x6ec017a0; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xff6f5846; - dmm32 A1.x, 0x0000007f; - imm32 R3, 0x256a8306; - imm32 R6, 0x6a8ca1e4; - imm32 R7, 0x2e579ce0; - R6.H = (A1 -= R3.L * R7.L) (M), A0 = R3.L * R7.L (TFU); - checkreg R6, 0x7fffa1e4; - checkreg A0.w, 0x504a4d40; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x14104490 | _VS | _V | _AV1S | _AV1 | _V_COPY | _AZ); - - dmm32 ASTAT, (0x20008080 | _VS | _V | _AV1S | _AV0 | _AC1 | _AC0 | _AQ); - dmm32 A0.w, 0x58b9bdf1; - dmm32 A0.x, 0xffffffe2; - dmm32 A1.w, 0x42c9fae8; - dmm32 A1.x, 0xffffff80; - imm32 R1, 0x68df1898; - imm32 R2, 0x3ae1b1f0; - imm32 R5, 0x61c3f5ef; - A1 += R2.L * R5.L (M), R1.L = (A0 -= R2.L * R5.L) (TFU); - checkreg R1, 0x68dfffff; - checkreg A0.w, 0xadc8eee1; - checkreg A0.x, 0xffffffe1; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0xffffff80; - checkreg ASTAT, (0x20008080 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _AQ | _V_COPY); - - dmm32 ASTAT, (0x1c70ca90 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AC0_COPY); - dmm32 A0.w, 0x082c2157; - dmm32 A0.x, 0xffffff9f; - dmm32 A1.w, 0x275e1474; - dmm32 A1.x, 0xffffff80; - imm32 R1, 0x7d3179fd; - imm32 R2, 0x5b41566f; - R2.H = (A1 -= R1.L * R1.H) (M), R2.L = (A0 = R1.L * R1.L) (TFU); - checkreg R2, 0x80003a21; - checkreg A0.w, 0x3a212409; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0x00000000; - checkreg A1.x, 0xffffff80; - checkreg ASTAT, (0x1c70ca90 | _VS | _V | _AV1S | _AV1 | _AV0S | _CC | _V_COPY | _AC0_COPY); - - dmm32 ASTAT, (0x7460cc10 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY); - dmm32 A0.w, 0x7fffffff; - dmm32 A0.x, 0x00000000; - dmm32 A1.w, 0xf20b4000; - dmm32 A1.x, 0x0000007f; - imm32 R1, 0x2ca2d045; - imm32 R6, 0x6e516a3c; - R1.H = (A1 -= R1.L * R6.H) (M), A0 = R1.L * R6.H (TFU); - checkreg R1, 0x7fffd045; - checkreg A0.w, 0x59bf8bd5; - checkreg A0.x, 0x00000000; - checkreg A1.w, 0xffffffff; - checkreg A1.x, 0x0000007f; - checkreg ASTAT, (0x7460cc10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _CC | _V_COPY); - - pass diff --git a/sim/testsuite/sim/bfin/run-tests.sh b/sim/testsuite/sim/bfin/run-tests.sh deleted file mode 100755 index c5ee777..0000000 --- a/sim/testsuite/sim/bfin/run-tests.sh +++ /dev/null @@ -1,249 +0,0 @@ -#!/bin/sh - -usage() { - cat <<-EOF - Usage: $0 [-rs] [-rj ] [-rh ] [tests] - - If no tests are specified, all tests are processed. - - Options: - -rs Run on simulator - -rj Run on board via JTAG - -rh Run on board ip - -j Num jobs to run - EOF - exit ${1:-1} -} - -: ${MAKE:=make} -boardip= -boardjtag= -run_sim=false -run_jtag=false -run_host=false -jobs=`getconf _NPROCESSORS_ONLN 2>/dev/null || echo 1` -: $(( jobs += 1 )) -while [ -n "$1" ] ; do - case $1 in - -rs) run_sim=true;; - -rj) boardjtag=$2; shift; run_jtag=true;; - -rh) boardip=$2; shift; run_host=true;; - -j) jobs=$2; shift;; - -*) usage;; - *) break;; - esac - shift -done -${run_jtag} || ${run_host} || ${run_sim} || run_sim=true - -if ${run_host} && [ -z "${boardip}" ] ; then - usage -fi - -cd "${0%/*}" || exit 1 - -dorsh() { - # rsh sucks and does not pass up its exit status, so we have to: - # on board: - # - send all output to stdout - # - send exit status to stderr - # on host: - # - swap stdout and stderr - # - pass exit status to `exit` - # - send stderr back to stdout and up - (exit \ - $(rsh -l root $boardip \ - '(/tmp/'$1') 2>&1; ret=$?; echo $ret 1>&2; [ $ret -eq 0 ] && rm -f /tmp/'$1 \ - 3>&1 1>&2 2>&3) \ - 2>&1) 2>&1 -} - -dojtag() { - if grep -q CHECKREG ${1%.x} ; then - echo "DBGA does not work via JTAG" - exit 77 - fi - - cat <<-EOF > commands - target remote localhost:2000 - load - - b *_pass - commands - exit 0 - end - - b *_fail - commands - exit 1 - end - - # we're executing at EVT1, so this doesn't really help ... - set ((long *)0xFFE02000)[3] = _fail - set ((long *)0xFFE02000)[5] = _fail - - c - EOF - bfin-elf-gdb -x commands "$1" - ret=$? - rm -f commands - exit ${ret} -} - -testit() { - local name=$1 x=$2 y=`echo $2 | sed 's:\.[xX]$::'` out rsh_out addr - shift; shift - local fail=`grep xfail ${y}` - if [ "${name}" = "HOST" -a ! -f $x ] ; then - return - fi - printf '%-5s %-40s' ${name} ${x} - out=`"$@" ${x} 2>&1` - (pf "${out}") - if [ $? -ne 0 ] ; then - if [ "${name}" = "SIM" ] ; then - tmp=`echo ${out} | awk '{print $3}' | sed 's/://'` - tmp1=`expr index "${out}" "program stopped with signal 4"` - if [ ${tmp1} -eq 1 ] ; then - printf 'illegal instruction\n' - elif [ -n "${tmp}" ] ; then - printf 'FAIL at line ' - addr=`echo $out | sed 's:^[A-Za-z ]*::' | sed 's:^0x[0-9][0-9] ::' | sed 's:^[A-Za-z ]*::' | awk '{print $1}'` - bfin-elf-addr2line -e ${x} ${addr} | awk -F "/" '{print $NF}' - fi - elif [ "${name}" = "HOST" ] ; then - rsh_out=`rsh -l root $boardip '/bin/dmesg -c | /bin/grep -e DBGA -e "FAULT "'` - tmp=`echo ${rsh_out} | sed 's:\].*$::' | awk '{print $NF}' | awk -F ":" '{print $NF}'` - if [ -n "${tmp}" ] ; then - echo "${rsh_out}" - printf 'FAIL at line ' - bfin-elf-addr2line -e ${x} $(echo ${rsh_out} | sed 's:\].*$::' | awk '{print $NF}') | awk -F "/" '{print $NF}' - fi - fi - ret=$(( ret + 1 )) - if [ -z "${fail}" ] ; then - unexpected_fail=$(( unexpected_fail + 1 )) - echo "!!!Expected Pass, but fail" - fi - else - if [ ! -z "${fail}" ] ; then - unexpected_pass=$(( unexpected_pass + 1 )) - echo "!!!Expected fail, but pass" - else - expected_pass=$(( expected_pass + 1 )) - fi - fi -} - -pf() { - local ret=$? - if [ ${ret} -eq 0 ] ; then - echo "PASS" - elif [ ${ret} -eq 77 ] ; then - echo "SKIP $*" - else - echo "FAIL! $*" - exit 1 - fi -} - -[ $# -eq 0 ] && set -- *.[Ss] -bins_hw=$( (${run_sim} || ${run_jtag}) && printf '%s.x ' "$@") -if ${run_host} ; then - for files in "$@" ; do - tmp=`grep -e CYCLES -e TESTSET -e CLI -e STI -e RTX -e RTI -e SEQSTAT $files -l` - if [ -z "${tmp}" ] ; then - bins_host=`echo "${bins_host} ${files}.X"` - else - echo "skipping ${files}, since it isn't userspace friendly" - fi - done -fi -if [ -n "${bins_hw}" ] ; then - bins_all="${bins_hw}" -fi - -if [ -n "${bins_host}" ] ; then - bins_all="${bins_all} ${bins_host}" -fi - -if [ -z "${bins_all}" ] ; then - exit -fi - -printf 'Compiling tests: ' -${MAKE} -s -j ${bins_all} -pf - -if ${run_jtag} ; then - printf 'Setting up gdbproxy (see gdbproxy.log): ' - killall -q bfin-gdbproxy - bfin-gdbproxy -q bfin --reset --board=${boardjtag} --init-sdram >gdbproxy.log 2>&1 & - t=0 - while [ ${t} -lt 5 ] ; do - if netstat -nap 2>&1 | grep -q ^tcp.*:2000.*gdbproxy ; then - break - else - : $(( t += 1 )) - sleep 1 - fi - done - pf -fi - -if ${run_host} ; then - printf 'Uploading tests to board "%s": ' "${boardip}" - rcp ${bins_host} root@${boardip}:/tmp/ - pf - rsh -l root $boardip '/bin/dmesg -c' > /dev/null -fi - -SIM="../../../bfin/run" -if [ ! -x ${SIM} ] ; then - SIM="bfin-elf-run" -fi -echo "Using sim: ${SIM}" - -ret=0 -unexpected_fail=0 -unexpected_pass=0 -expected_pass=0 -pids=() -for s in "$@" ; do - ( - out=$( - ${run_sim} && testit SIM ${s}.x ${SIM} `sed -n '/^# sim:/s|^[^:]*:||p' ${s}` - ${run_jtag} && testit JTAG ${s}.x dojtag - ${run_host} && testit HOST ${s}.X dorsh - ) - case $out in - *PASS*) ;; - *) echo "$out" ;; - esac - ) & - pids+=( $! ) - if [[ ${#pids[@]} -gt ${jobs} ]] ; then - wait ${pids[0]} - pids=( ${pids[@]:1} ) - fi -done -wait - -killall -q bfin-gdbproxy -if [ ${ret} -eq 0 ] ; then - rm -f gdbproxy.log -# ${MAKE} -s clean & - exit 0 -else - echo number of failures ${ret} - if [ ${unexpected_pass} -gt 0 ] ; then - echo "Unexpected passes: ${unexpected_pass}" - fi - if [ ${unexpected_fail} -gt 0 ] ; then - echo "Unexpected fails: ${unexpected_fail}" - fi - if [ ${expected_pass} -gt 0 ] ; then - echo "passes : ${expected_pass}" - fi - exit 1 -fi diff --git a/sim/testsuite/sim/bfin/s0.s b/sim/testsuite/sim/bfin/s0.s deleted file mode 100644 index 8fa53f2..0000000 --- a/sim/testsuite/sim/bfin/s0.s +++ /dev/null @@ -1,12 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - R0 = 10; - P0 = R0; - LSETUP ( ls0 , ls0 ) LC0 = P0; -ls0: - R0 += -1; - DBGA ( R0.L , 0 ); - pass diff --git a/sim/testsuite/sim/bfin/s1.s b/sim/testsuite/sim/bfin/s1.s deleted file mode 100644 index 262dc06..0000000 --- a/sim/testsuite/sim/bfin/s1.s +++ /dev/null @@ -1,25 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - R0 = 1; - R1 = 2; - R2 = 3; - R4 = 4; - P1 = R1; - LSETUP ( ls0 , ls0 ) LC0 = P1; - R5 = 5; - R6 = 6; - R7 = 7; - -ls0: R1 += 1; - - DBGA ( R1.L , 4 ); - P1 = R1; - LSETUP ( ls1 , ls1 ) LC1 = P1; -ls1: R1 += 1; - - DBGA ( R1.L , 8 ); - - pass diff --git a/sim/testsuite/sim/bfin/s10.s b/sim/testsuite/sim/bfin/s10.s deleted file mode 100644 index 503cabf..0000000 --- a/sim/testsuite/sim/bfin/s10.s +++ /dev/null @@ -1,77 +0,0 @@ -// Shifter test program. -// Test instructions -// RL0 = SIGNBITS R1; -// RL0 = SIGNBITS RL1; -// RL0 = SIGNBITS RH1; - -# mach: bfin - -.include "testutils.inc" - start - - -// on 32-b word - - R1.L = 0xffff; - R1.H = 0x7fff; - R0.L = SIGNBITS R1; - DBGA ( R0.L , 0x0000 ); - - R1.L = 0xffff; - R1.H = 0x30ff; - R0.L = SIGNBITS R1; - DBGA ( R0.L , 0x0001 ); - - R1.L = 0xff0f; - R1.H = 0x10ff; - R0.L = SIGNBITS R1; - DBGA ( R0.L , 0x0002 ); - - R1.L = 0xff0f; - R1.H = 0xe0ff; - R0.L = SIGNBITS R1; - DBGA ( R0.L , 0x0002 ); - - R1.L = 0x0001; - R1.H = 0x0000; - R0.L = SIGNBITS R1; - DBGA ( R0.L , 0x0001e ); - - R1.L = 0xfffe; - R1.H = 0xffff; - R0.L = SIGNBITS R1; - DBGA ( R0.L , 0x0001e ); - - R1.L = 0xffff; // return largest norm for -1 - R1.H = 0xffff; - R0.L = SIGNBITS R1; - DBGA ( R0.L , 0x0001f ); - - R1.L = 0; // return largest norm for zero - R1.H = 0; - R0.L = SIGNBITS R1; - DBGA ( R0.L , 0x001f ); - -// on 16-b word - - R1.L = 0x7fff; - R1.H = 0xffff; - R0.L = SIGNBITS R1.L; - DBGA ( R0.L , 0x0000 ); - - R1.L = 0x0fff; - R1.H = 0x0001; - R0.L = SIGNBITS R1.H; - DBGA ( R0.L , 0x000e ); - - R1.L = 0x0fff; - R1.H = 0xffff; - R0.L = SIGNBITS R1.H; - DBGA ( R0.L , 0x000f ); - - R1.L = 0x0fff; - R1.H = 0xfffe; - R0.L = SIGNBITS R1.H; - DBGA ( R0.L , 0x000e ); - - pass diff --git a/sim/testsuite/sim/bfin/s11.s b/sim/testsuite/sim/bfin/s11.s deleted file mode 100644 index 16a57eb..0000000 --- a/sim/testsuite/sim/bfin/s11.s +++ /dev/null @@ -1,177 +0,0 @@ -# mach: bfin - -// Shift test program. -// Test instructions -// RL0 = CC = BXOR (A0 AND R1) << 1; -// RL0 = CC = BXOR A0 AND R1; -// A0 <<=1 (BXOR A0 AND A1 CC); -// RL3 = CC = BXOR A0 AND A1 CC; - -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - -// RL0 = CC = BXOR (A0 AND R1) << 1; - R0.L = 0x1000; - R0.H = 0x0000; - A0.w = R0; - R0.L = 0x0000; - A0.x = R0.L; - R1.L = 0xffff; - R1.H = 0xffff; - R2.L = CC = BXORSHIFT( A0 , R1 ); - R0 = A0.w; - DBGA ( R0.L , 0x2000 ); - DBGA ( R0.H , 0x0000 ); - R0.L = A0.x; - DBGA ( R0.L , 0x0000 ); - R0 = CC; - DBGA ( R0.L , 0x0001 ); - DBGA ( R0.H , 0x0000 ); - DBGA ( R2.L , 0x0001 ); - - R0.L = 0x1000; - R0.H = 0x0001; - A0.w = R0; - R0.L = 0x0000; - A0.x = R0.L; - R1.L = 0xffff; - R1.H = 0xffff; - R2.L = CC = BXORSHIFT( A0 , R1 ); - R0 = A0.w; - DBGA ( R0.L , 0x2000 ); - DBGA ( R0.H , 0x0002 ); - R0.L = A0.x; - DBGA ( R0.L , 0x0000 ); - R0 = CC; - DBGA ( R0.L , 0x0000 ); - DBGA ( R0.H , 0x0000 ); - DBGA ( R2.L , 0x0000 ); - - R0.L = 0xffff; - R0.H = 0xffff; - A0.w = R0; - R0.L = 0x00ff; - A0.x = R0.L; - R1.L = 0xffff; - R1.H = 0xffff; - R2.L = CC = BXORSHIFT( A0 , R1 ); - R0 = A0.w; - DBGA ( R0.L , 0xfffe ); - DBGA ( R0.H , 0xffff ); - R0.L = A0.x; - DBGA ( R0.L , 0xffff ); - R0 = CC; - DBGA ( R0.L , 0x0001 ); - DBGA ( R0.H , 0x0000 ); - DBGA ( R2.L , 0x0001 ); - -// no - R0.L = 0xffff; - R0.H = 0xffff; - A0.w = R0; - R0.L = 0x00ff; - A0.x = R0.L; - R1.L = 0xffff; - R1.H = 0xffff; - R2.L = CC = BXOR( A0 , R1 ); - R0 = A0.w; - DBGA ( R0.L , 0xffff ); - DBGA ( R0.H , 0xffff ); - R0.L = A0.x; - DBGA ( R0.L , 0xffff ); - R0 = CC; - DBGA ( R0.L , 0x0000 ); - DBGA ( R0.H , 0x0000 ); - DBGA ( R2.H , 0x0000 ); - -// A0 <<=1 (BXOR A0 AND A1 CC); - - R0.L = 0x1000; - R0.H = 0x0000; - A0.w = R0; - R0.L = 0x0000; - A0.x = R0.L; - R0.L = 0xffff; - R0.H = 0xffff; - A1.w = R0; - R0.L = 0x00ff; - A1.x = R0.L; - R0.L = 0x0000; - R0.H = 0x0000; - CC = R0; - A0 = BXORSHIFT( A0 , A1, CC ); - R0 = A0.w; - DBGA ( R0.L , 0x2001 ); - DBGA ( R0.H , 0x0000 ); - R0.L = A0.x; - DBGA ( R0.L , 0x0000 ); - - R0.L = 0x1000; - R0.H = 0x0000; - A0.w = R0; - R0.L = 0x0000; - A0.x = R0.L; - R0.L = 0x0fff; - R0.H = 0xffff; - A1.w = R0; - R0.L = 0x00ff; - A1.x = R0.L; - R0.L = 0x0000; - R0.H = 0x0000; - CC = R0; - A0 = BXORSHIFT( A0 , A1, CC ); - R0 = A0.w; - DBGA ( R0.L , 0x2000 ); - DBGA ( R0.H , 0x0000 ); - R0.L = A0.x; - DBGA ( R0.L , 0x0000 ); - - R0.L = 0x1000; - R0.H = 0x0000; - A0.w = R0; - R0.L = 0x0000; - A0.x = R0.L; - R0.L = 0xffff; - R0.H = 0xffff; - A1.w = R0; - R0.L = 0x00ff; - A1.x = R0.L; - R0.L = 0x0001; - R0.H = 0x0000; - CC = R0; - A0 = BXORSHIFT( A0 , A1, CC ); - R0 = A0.w; - DBGA ( R0.L , 0x2000 ); - DBGA ( R0.H , 0x0000 ); - R0.L = A0.x; - DBGA ( R0.L , 0x0000 ); - -// no - - R0.L = 0x1000; - R0.H = 0x0000; - A0.w = R0; - R0.L = 0x0000; - A0.x = R0.L; - R0.L = 0xffff; - R0.H = 0xffff; - A1.w = R0; - R0.L = 0x00ff; - A1.x = R0.L; - R0.L = 0x0000; - R0.H = 0x0000; - CC = R0; - R2.L = CC = BXOR( A0 , A1, CC ); - R0 = A0.w; - DBGA ( R0.L , 0x1000 ); - DBGA ( R0.H , 0x0000 ); - R0.L = A0.x; - DBGA ( R0.L , 0x0000 ); - DBGA ( R2.L , 0x0001 ); - R0 = CC; - DBGA ( R0.L , 0x0001 ); - - pass diff --git a/sim/testsuite/sim/bfin/s12.s b/sim/testsuite/sim/bfin/s12.s deleted file mode 100644 index 2f66798..0000000 --- a/sim/testsuite/sim/bfin/s12.s +++ /dev/null @@ -1,84 +0,0 @@ -// Shifter test program. -// Test instructions -// RL5 = EXPADJ R4 BY RL2; -# mach: bfin - -.include "testutils.inc" - start - - - R0.L = 30; // large norm of small value - R0.H = 1; // make sure high half is not used - R1.L = 0x0000; - R1.H = 0x1000; // small norm (2) of large value - R7.L = EXPADJ( R1 , R0.L ); - DBGA ( R7.L , 0x0002 ); - - R0.L = 3; // small norm of large value - R0.H = 1; // make sure high half is not used - R1.L = 0x0000; - R1.H = 0xff00; // small norm (2) of large value - R7.L = EXPADJ( R1 , R0.L ); - DBGA ( R7.L , 0x0003 ); - - R0.L = 3; - R0.H = 1; - R1.L = 0xffff; - R1.H = 0xffff; - R7.L = EXPADJ( R1 , R0.L ); - DBGA ( R7.L , 0x0003 ); - - R0.L = 31; - R0.H = 1; - R1.L = 0x0000; // norm=0 - R1.H = 0x8000; - R7.L = EXPADJ( R1 , R0.L ); - DBGA ( R7.L , 0x0000 ); - -// RL5 = EXPADJ/EXPADJ R4 BY RL2; - - R0.L = 15; - R1.L = 0x0800; - R1.H = 0x1000; - R7.L = EXPADJ( R1 , R0.L ) (V); - DBGA ( R7.L , 0x0002 ); - - R0.L = 15; - R1.L = 0x1000; - R1.H = 0x0800; - R7.L = EXPADJ( R1 , R0.L ) (V); - DBGA ( R7.L , 0x0002 ); - - R0.L = 1; - R1.L = 0x0800; - R1.H = 0x1000; - R7.L = EXPADJ( R1 , R0.L ) (V); - DBGA ( R7.L , 0x0001 ); - - R0.L = 14; - R1.L = 0xff00; - R1.H = 0xfff0; - R7.L = EXPADJ( R1 , R0.L ) (V); - DBGA ( R7.L , 0x0007 ); - -// RL5 = EXPADJ RL4 BY RL2; - - R0.L = 14; - R1.L = 0xff00; - R1.H = 0x1000; - R7.L = EXPADJ( R1.L , R0.L ); - DBGA ( R7.L , 0x0007 ); - - R0.L = 3; - R1.L = 0xff00; - R1.H = 0x1000; - R7.L = EXPADJ( R1.L , R0.L ); - DBGA ( R7.L , 0x0003 ); - - R0.L = 14; - R1.L = 0x1000; - R1.H = 0xff00; - R7.L = EXPADJ( R1.H , R0.L ); - DBGA ( R7.L , 0x0007 ); - - pass diff --git a/sim/testsuite/sim/bfin/s13.s b/sim/testsuite/sim/bfin/s13.s deleted file mode 100644 index 22b77b7..0000000 --- a/sim/testsuite/sim/bfin/s13.s +++ /dev/null @@ -1,215 +0,0 @@ -// Test rl3 = ashift (rh0 by r5; -// Test rl3 = lshift (rh0 by r5); -# mach: bfin - -.include "testutils.inc" - start - - init_r_regs 0; - - R0 = 0; - ASTAT = R0; - R0.L = 0x1; - R0.H = 0x1; - R5.L = 4; - R7.L = ASHIFT R0.L BY R5.L; - DBGA ( R7.L , 0x0010 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R0.L = 0x8000; - R0.H = 0x1; - R5.L = -4; - R5.H = 0; - R7.L = ASHIFT R0.L BY R5.L; - DBGA ( R7.L , 0xf800 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R0.L = 0x0; - R0.H = 0x1; - R5.L = 0; - R5.H = 0; - R7.L = ASHIFT R0.L BY R5.L; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 0; - R0.L = 0x1; - R0.H = 0x8000; - R5.L = -4; - R5.H = 0; - R7.H = ASHIFT R0.H BY R5.L; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0xf800 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 0; - R0.L = 0x1; - R0.H = 0x8000; - R5.L = -4; - R5.H = 0; - R7.L = ASHIFT R0.H BY R5.L; - DBGA ( R7.L , 0xf800 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 0; - R0.L = 0x1; - R0.H = 0xffff; - R5.L = 31; // should accept mag of +31 - R5.H = 0; - R7.L = ASHIFT R0.H BY R5.L; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 0; - R0.L = 0x1; - R0.H = 0x0100; - R5.L = 63; // mag of 63 will appear as -1 since 6 bits are masked - R5.H = 0; - R7.L = ASHIFT R0.H BY R5.L; - DBGA ( R7.L , 0x0080 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// logic shifts - R0 = 0; - ASTAT = R0; - R7 = 0; - R0.L = 0x1; - R0.H = 0x8000; - R5.L = -4; - R5.H = 0; - R7.L = LSHIFT R0.H BY R5.L; - DBGA ( R7.L , 0x0800 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 0; - R0.L = 0x1; - R0.H = 0x1; - R5.L = 4; - R5.H = 0; - R7.H = LSHIFT R0.L BY R5.L; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0010 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 1; - R0.L = 0x0; - R0.H = 0x0; - R5.L = 0; - R5.H = 0; - R7.L = LSHIFT R0.L BY R5.L; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 1; - R0.L = 0x1; - R0.H = 0x0; - R5.L = 15; - R5.H = 0; - R7.L = LSHIFT R0.L BY R5.L; - DBGA ( R7.L , 0x8000 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 1; - R0.L = 0x0100; - R0.H = 0x0; - R5.L = 63; // mag of 63 will appear as -1 since 6 bits are masked - R5.H = 0; - R7.L = LSHIFT R0.L BY R5.L; - DBGA ( R7.L , 0x0080 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 1; - R0.L = 0x0100; - R0.H = 0x0; - R5.L = 31; // should accept mag of +31 - R5.H = 0; - R7.L = LSHIFT R0.L BY R5.L; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - pass diff --git a/sim/testsuite/sim/bfin/s14.s b/sim/testsuite/sim/bfin/s14.s deleted file mode 100644 index 99814ee..0000000 --- a/sim/testsuite/sim/bfin/s14.s +++ /dev/null @@ -1,350 +0,0 @@ -// reg-based SHIFT test program. -// Test r4 = ASHIFT (r2 by rl3); -// Test r4 = LSHIFT (r2 by rl3); -# mach: bfin - -.include "testutils.inc" - start - - - R0.L = 0x0001; - R0.H = 0x8000; - -// arithmetic -// left by 31 -// 8000 0001 -> 8000 0000 - R7 = 0; - ASTAT = R7; - R3.L = 31; - R3.H = 0; - R6 = ASHIFT R0 BY R3.L; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by 32 -// 8000 0001 -> 8000 0000 - R7 = 0; - ASTAT = R7; - R3.L = 32; - R3.H = 0; - R6 = ASHIFT R0 BY R3.L; - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0xffff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by 40 -// 8000 0001 -> 8000 0000 - R7 = 0; - ASTAT = R7; - R3.L = 40; - R3.H = 0; - R6 = ASHIFT R0 BY R3.L; - DBGA ( R6.L , 0xFF80 ); - DBGA ( R6.H , 0xFFFF ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by -32 -// 8000 0001 -> 8000 0000 - R7 = 0; - ASTAT = R7; - R3.L = -32; - R3.H = 0; - R6 = ASHIFT R0 BY R3.L; - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0xffff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by 63 (off scale) -// 8000 0001 -> 0000 0000 - R7 = 0; - ASTAT = R7; - R0.L = 1; - R0.H = 0; - R3.L = 63; - R3.H = 0; - R6 = ASHIFT R0 BY R3.L; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by 255 looks like -1 (mask 7 bits) -// 8000 0001 -> 0000 0000 - R7 = 0; - ASTAT = R7; - R0.L = 0x0100; - R0.H = 0; - R3.L = 255; - R3.H = 0; - R6 = ASHIFT R0 BY R3.L; - DBGA ( R6.L , 0x0080 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by 1 -// 8000 0001 -> 0000 0002 - R0.L = 0x0001; - R0.H = 0x8000; - R3.L = 1; - R3.H = 0; - R6 = ASHIFT R0 BY R3.L; - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// right by 1 -// 8000 0001 -> 0000 0002 - R0.L = 0x0001; - R0.H = 0x8000; - R3.L = -1; - R3.H = 0; - R6 = ASHIFT R0 BY R3.L; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0xc000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// right by -31 -// 8000 0001 -> ffff ffff - R0.L = 0x0001; - R0.H = 0x8000; - R3.L = -31; - R3.H = 0; - R6 = ASHIFT R0 BY R3.L; - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0xffff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// logic -// left by largest positive magnitude of 31 (0x1f) -// 8000 0001 -> 8000 0000 - R0.L = 0x0001; - R0.H = 0x8000; - R3.L = 31; - R3.H = 0; - R6 = ASHIFT R0 BY R3.L; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// logic -// left by 1 -// 8000 0001 -> 0000 0002 - R0.L = 0x0001; - R0.H = 0x8000; - R3.L = 1; - R3.H = 0; - R6 = LSHIFT R0 BY R3.L; - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// logic -// right by 1 -// 8000 0001 -> 4000 0000 - R0.L = 0x0001; - R0.H = 0x8000; - R3.L = -1; - R3.H = 0; - R6 = LSHIFT R0 BY R3.L; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x4000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// logic -// right by largest negative magnitude of -31 -// 8000 0001 -> 0000 0001 - R0.L = 0x0001; - R0.H = 0x8000; - R3.L = -31; - R3.H = 0; - R6 = LSHIFT R0 BY R3.L; - DBGA ( R6.L , 0x0001 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// logic -// right by -32 -// 8000 0001 -> 0000 0001 - R0.L = 0x0001; - R0.H = 0x8000; - R3.L = -32; - R3.H = 0; - R6 = LSHIFT R0 BY R3.L; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// logic -// by +40 -// 8000 0001 -> 0000 0001 - R0.L = 0x0001; - R0.H = 0x8000; - R3.L = 40; - R3.H = 0; - R6 = LSHIFT R0 BY R3.L; - DBGA ( R6.L , 0x0080 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// rot -// left by 1 -// 8000 0001 -> 0000 0002 cc=1 - R7 = 0; - CC = R7; - R6 = ROT R0 BY 1; - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; DBGA ( R7.L , 0x0001 ); - -// rot -// right by -1 -// 8000 0001 -> 4000 0000 cc=1 - R7 = 0; - CC = R7; - R6 = ROT R0 BY -1; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x4000 ); - R7 = CC; DBGA ( R7.L , 0x0001 ); - -// rot -// right by largest positive magnitude of 31 -// 8000 0001 -> a000 0000 cc=0 - R7 = 0; - CC = R7; - R6 = ROT R0 BY 31; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0xa000 ); - R7 = CC; DBGA ( R7.L , 0x0000 ); - -// rot -// right by largest positive magnitude of 31 with cc=1 -// 8000 0001 cc=1 -> a000 0000 cc=0 - R7 = 1; - CC = R7; - R6 = ROT R0 BY 31; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0xe000 ); - R7 = CC; DBGA ( R7.L , 0x0000 ); - -// rot -// right by largest negative magnitude of -31 -// 8000 0001 -> 0000 0005 cc=0 - R7 = 0; - CC = R7; - R6 = ROT R0 BY -31; - DBGA ( R6.L , 0x0005 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; DBGA ( R7.L , 0x0000 ); - -// rot -// right by largest negative magnitude of -31 with cc=1 -// 8000 0001 cc=1 -> 0000 0007 cc=0 - R7 = 1; - CC = R7; - R6 = ROT R0 BY -31; - DBGA ( R6.L , 0x0007 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; DBGA ( R7.L , 0x0000 ); - -// rot -// left by 7 -// 8000 0001 cc=1 -> 0000 00e0 cc=0 - R7 = 1; - CC = R7; - R6 = ROT R0 BY 7; - DBGA ( R6.L , 0x00e0 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; DBGA ( R7.L , 0x0000 ); - -// rot by zero -// 8000 0001 -> 8000 000 - R7 = 1; - CC = R7; - R6 = ROT R0 BY 0; - DBGA ( R6.L , 0x0001 ); - DBGA ( R6.H , 0x8000 ); - R7 = CC; DBGA ( R7.L , 0x0001 ); - -// 0 by 1 - R7 = 0; - R0 = 0; - ASTAT = R7; - R6 = R0 << 1; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - pass diff --git a/sim/testsuite/sim/bfin/s15.s b/sim/testsuite/sim/bfin/s15.s deleted file mode 100644 index 9c32d48..0000000 --- a/sim/testsuite/sim/bfin/s15.s +++ /dev/null @@ -1,149 +0,0 @@ -// reg-based SHIFT test program. -# mach: bfin - -.include "testutils.inc" - start - - -// Test FEXT with no sign extension - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x0810; // pos=8 len=16 - R7 = EXTRACT( R0, R1.L ) (Z); - DBGA ( R7.L , 0x34de ); - DBGA ( R7.H , 0 ); - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x0814; // pos=8 len=20 - R7 = EXTRACT( R0, R1.L ) (Z); - DBGA ( R7.L , 0x34de ); - DBGA ( R7.H , 0x0002 ); - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x0800; // pos=8 len=0 - R7 = EXTRACT( R0, R1.L ) (Z); - DBGA ( R7.L , 0 ); - DBGA ( R7.H , 0 ); - - R0.L = 0xfff1; - R0.H = 0xffff; - R1.L = 0x0001; // pos=0 len=1 - R7 = EXTRACT( R0, R1.L ) (Z); - DBGA ( R7.L , 0x1 ); - DBGA ( R7.H , 0 ); - - R0.L = 0xfff1; - R0.H = 0xffff; - R1.L = 0x0101; // pos=1 len=1 - R7 = EXTRACT( R0, R1.L ) (Z); - DBGA ( R7.L , 0 ); - DBGA ( R7.H , 0 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0xfff1; - R0.H = 0xffff; - R1.L = 0x1810; // pos=24 len=16 - R7 = EXTRACT( R0, R1.L ) (Z); - DBGA ( R7.L , 0x00ff ); - DBGA ( R7.H , 0 ); - - R0.L = 0xfff1; - R0.H = 0xffff; - R1.L = 0x0020; // pos=0 len=32 is like pos=0 len=0 - R7 = EXTRACT( R0, R1.L ) (Z); - DBGA ( R7.L , 0x0 ); - DBGA ( R7.H , 0x0 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0xfff1; - R0.H = 0xffff; - R1.L = 0x2020; // pos=32 len=32 is like pos=0 len=0 - R7 = EXTRACT( R0, R1.L ) (Z); - DBGA ( R7.L , 0 ); - DBGA ( R7.H , 0 ); - - R0.L = 0xfff1; - R0.H = 0xffff; - R1.L = 0x1f01; // pos=31 len=1 - R7 = EXTRACT( R0, R1.L ) (Z); - DBGA ( R7.L , 0x1 ); - DBGA ( R7.H , 0 ); - - R0.L = 0xfff1; - R0.H = 0xffff; - R1.L = 0x1000; // pos=16 len=0 - R7 = EXTRACT( R0, R1.L ) (Z); - DBGA ( R7.L , 0 ); - DBGA ( R7.H , 0 ); - -// Test FEXT with sign extension - - R0.L = 0xdead; - R0.H = 0x12f4; - R1.L = 0x0810; // pos=8 len=16 - R7 = EXTRACT( R0, R1.L ) (X); - DBGA ( R7.L , 0xf4de ); - DBGA ( R7.H , 0xffff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x0810; // pos=8 len=16 - R7 = EXTRACT( R0, R1.L ) (X); - DBGA ( R7.L , 0x34de ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0xdead; - R0.H = 0xf234; - R1.L = 0x1f01; // pos=31 len=1 - R7 = EXTRACT( R0, R1.L ) (X); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0xffff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - - R0.L = 0xdead; - R0.H = 0xf234; - R1.L = 0x1f02; // pos=31 len=2 - R7 = EXTRACT( R0, R1.L ) (X); - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0xffff; - R0.H = 0xffff; - R1.L = 0x101f; // pos=16 len=31 - R7 = EXTRACT( R0, R1.L ) (X); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0xffff; - R0.H = 0xffff; - R1.L = 0x1001; // pos=16 len=1 - R7 = EXTRACT( R0, R1.L ) (X); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0xffff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - - R0.L = 0xffff; - R0.H = 0xffff; - R1.L = 0x1000; // pos=16 len=0 - R7 = EXTRACT( R0, R1.L ) (X); - DBGA ( R7.L , 0 ); - DBGA ( R7.H , 0 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - - pass diff --git a/sim/testsuite/sim/bfin/s16.s b/sim/testsuite/sim/bfin/s16.s deleted file mode 100644 index 6741cf3..0000000 --- a/sim/testsuite/sim/bfin/s16.s +++ /dev/null @@ -1,170 +0,0 @@ -// reg-based SHIFT test program. -# mach: bfin - -.include "testutils.inc" - start - - -// Test FDEP with no sign extension - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x0c08; // pos=12 len=8 - R1.H = 0x00ff; - R7 = DEPOSIT( R0, R1 ); - DBGA ( R7.L , 0xfead ); - DBGA ( R7.H , 0x123f ); - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x0c04; // pos=12 len=4 - R1.H = 0x00ff; - R7 = DEPOSIT( R0, R1 ); - DBGA ( R7.L , 0xfead ); - DBGA ( R7.H , 0x1234 ); - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x0c05; // pos=12 len=5 - R1.H = 0x00ff; - R7 = DEPOSIT( R0, R1 ); - DBGA ( R7.L , 0xfead ); - DBGA ( R7.H , 0x1235 ); - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x0010; // pos=0 len=16 - R1.H = 0xffff; - R7 = DEPOSIT( R0, R1 ); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x1234 ); - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x0011; // pos=0 len=17 - R1.H = 0xffff; - R7 = DEPOSIT( R0, R1 ); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x1234 ); - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x0114; // pos=1 len=20 - R1.H = 0xffff; - R7 = DEPOSIT( R0, R1 ); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x1235 ); - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x001f; // pos=0 len=31 - R1.H = 0xffff; - R7 = DEPOSIT( R0, R1 ); - DBGA ( R7.L , 0xffff ); - DBGA ( R7.H , 0x1234 ); - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x1c04; // pos=28 len=4 - R1.H = 0xffff; - R7 = DEPOSIT( R0, R1 ); - DBGA ( R7.L , 0xdead ); - DBGA ( R7.H , 0xf234 ); - - R0.L = 0xdead; - R0.H = 0x0234; - R1.L = 0x1d04; // pos=29 len=4 - R1.H = 0xffff; - R7 = DEPOSIT( R0, R1 ); - DBGA ( R7.L , 0xdead ); - DBGA ( R7.H , 0xe234 ); - - R0.L = 0xdead; - R0.H = 0x0234; - R1.L = 0x1f04; // pos=31 len=4 - R1.H = 0xffff; - R7 = DEPOSIT( R0, R1 ); - DBGA ( R7.L , 0xdead ); - DBGA ( R7.H , 0x8234 ); - - R0.L = 0xdead; - R0.H = 0x0234; - R1.L = 0x2004; // pos=32 len=4, same as pos=0 len=4 - R1.H = 0xffff; - R7 = DEPOSIT( R0, R1 ); - DBGA ( R7.L , 0xdeaf ); - DBGA ( R7.H , 0x0234 ); - -// Test FDEP with sign extension - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x0c08; // pos=12 len=8 - R1.H = 0x00ff; - R7 = DEPOSIT( R0, R1 ) (X); - DBGA ( R7.L , 0xfead ); - DBGA ( R7.H , 0xffff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - - R0.L = 0xdead; - R0.H = 0x1234; - R1.L = 0x0c08; // pos=12 len=8 - R1.H = 0x007f; - R7 = DEPOSIT( R0, R1 ) (X); - DBGA ( R7.L , 0xfead ); - DBGA ( R7.H , 0x0007 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0xdea0; - R0.H = 0x1234; - R1.L = 0x0110; // pos=1 len=16 - R1.H = 0xffff; - R7 = DEPOSIT( R0, R1 ) (X); - DBGA ( R7.L , 0xfffe ); - DBGA ( R7.H , 0xffff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - - R0.L = 0xdea0; - R0.H = 0x1234; - R1.L = 0x0101; // pos=1 len=1 - R1.H = 0xffff; - R7 = DEPOSIT( R0, R1 ) (X); - DBGA ( R7.L , 0xfffe ); - DBGA ( R7.H , 0xffff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - - R0.L = 0xdea0; - R0.H = 0x1234; - R1.L = 0x0102; // pos=1 len=2 - R1.H = 0x0001; - R7 = DEPOSIT( R0, R1 ) (X); - DBGA ( R7.L , 0x0002 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0xdea0; - R0.H = 0x1234; - R1.L = 0x0002; // pos=0 len=2 - R1.H = 0x0001; - R7 = DEPOSIT( R0, R1 ) (X); - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0xdea0; - R0.H = 0x1234; - R1.L = 0x0000; // pos=0 len=0 - R1.H = 0x000f; - R7 = DEPOSIT( R0, R1 ) (X); - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - - pass diff --git a/sim/testsuite/sim/bfin/s17.s b/sim/testsuite/sim/bfin/s17.s deleted file mode 100644 index 530a93b..0000000 --- a/sim/testsuite/sim/bfin/s17.s +++ /dev/null @@ -1,46 +0,0 @@ -// shifter test program. -// Test instructions ONES -# mach: bfin - -.include "testutils.inc" - start - - - R7 = 0; - ASTAT = R7; - R0.L = 0x1; - R0.H = 0x0; - R7.L = ONES R0; - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0.L = 0x0000; - R0.H = 0x8000; - R7.L = ONES R0; - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0000 ); - - R0.L = 0x0001; - R0.H = 0x8000; - R7.L = ONES R0; - DBGA ( R7.L , 0x0002 ); - DBGA ( R7.H , 0x0000 ); - - R0.L = 0xffff; - R0.H = 0xffff; - R7.L = ONES R0; - DBGA ( R7.L , 0x0020 ); - DBGA ( R7.H , 0x0000 ); - - R0.L = 0x0000; - R0.H = 0x0000; - R7.L = ONES R0; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - - pass diff --git a/sim/testsuite/sim/bfin/s18.s b/sim/testsuite/sim/bfin/s18.s deleted file mode 100644 index 6f26cc8..0000000 --- a/sim/testsuite/sim/bfin/s18.s +++ /dev/null @@ -1,132 +0,0 @@ -// Immediate dual 16b SHIFT test program. -// Test r4 = ASHIFT/ASHIFT (r2 by 10); -// Test r4 = ASHIFT/ASHIFT (r2 by 10) S; -// Test r4 = LSHIFT/LSHIFT (r2 by 10); -# mach: bfin - -.include "testutils.inc" - start - - -// arithmetic -// left by largest positive magnitude of 15 (0xf) -// 8001 -> 8000 - R7 = 0; - ASTAT = R7; - R0.L = 0x8001; - R0.H = 0x0100; - R6 = R0 << 15 (V); - DBGA ( R6.L , 0x8000 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by largest positive magnitude of 15 (0xf) with saturation - R7 = 0; - ASTAT = R7; - R0.L = 0x8001; - R0.H = 0x0100; - R6 = R0 << 15 (V , S); - DBGA ( R6.L , 0x8000 ); - DBGA ( R6.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by 1 - R7 = 0; - ASTAT = R7; - R0.L = 0x8001; - R0.H = 0x0100; - R6 = R0 << 1 (V); - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x0200 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by 1 saturating - R7 = 0; - ASTAT = R7; - R0.L = 0x8001; - R0.H = 0x0100; - R6 = R0 << 1 (V , S); - DBGA ( R6.L , 0x8000 ); - DBGA ( R6.H , 0x0200 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by 15 saturating - R7 = 0; - ASTAT = R7; - R0.L = 0xfff0; - R0.H = 0x0000; - R6 = R0 << 15 (V , S); - DBGA ( R6.L , 0x8000 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// right by 15 - R7 = 0; - ASTAT = R7; - R0.L = 0x8000; - R0.H = 0x0100; - R6 = R0 >>> 15 (V); - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// right by 15 (sat has no effect) - R7 = 0; - ASTAT = R7; - R0.L = 0x8000; - R0.H = 0x0100; - R6 = R0 >>> 15 (V); - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// logic -// right by 15 - R7 = 0; - ASTAT = R7; - R0.L = 0x8000; - R0.H = 0x0100; - R6 = R0 >> 15 (V); - DBGA ( R6.L , 0x0001 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - pass diff --git a/sim/testsuite/sim/bfin/s19.s b/sim/testsuite/sim/bfin/s19.s deleted file mode 100644 index 8e37ca2..0000000 --- a/sim/testsuite/sim/bfin/s19.s +++ /dev/null @@ -1,140 +0,0 @@ -// REG-BASED dual 16b SHIFT test program. -// Test r4 = ASHIFT/ASHIFT (r2 by rl1); -// Test r4 = ASHIFT/ASHIFT (r2 by rl1) S; -// Test r4 = LSHIFT/LSHIFT (r2 by rl1); -# mach: bfin - -.include "testutils.inc" - start - - -// arithmetic -// left by largest positive magnitude of 15 (0xf) -// 8001 -> 8000 - R7 = 0; - ASTAT = R7; - R0.L = 0x8001; - R0.H = 0x0100; - R1.L = 15; - R6 = ASHIFT R0 BY R1.L (V); - DBGA ( R6.L , 0x8000 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by largest positive magnitude of 15 (0xf) with saturation - R7 = 0; - ASTAT = R7; - R0.L = 0x8001; - R0.H = 0x0100; - R1.L = 15; - R6 = ASHIFT R0 BY R1.L (V , S); - DBGA ( R6.L , 0x8000 ); - DBGA ( R6.H , 0x7fff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by 1 - R7 = 0; - ASTAT = R7; - R0.L = 0x8001; - R0.H = 0x0100; - R1.L = 1; - R6 = ASHIFT R0 BY R1.L (V); - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x0200 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by 1 saturating - R7 = 0; - ASTAT = R7; - R0.L = 0x8001; - R0.H = 0x0100; - R1.L = 1; - R6 = ASHIFT R0 BY R1.L (V , S); - DBGA ( R6.L , 0x8000 ); - DBGA ( R6.H , 0x0200 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by 15 saturating - R7 = 0; - ASTAT = R7; - R0.L = 0xfff0; - R0.H = 0x0000; - R1.L = 15; - R6 = ASHIFT R0 BY R1.L (V , S); - DBGA ( R6.L , 0x8000 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// right by 15 - R7 = 0; - ASTAT = R7; - R0.L = 0x8000; - R0.H = 0x0100; - R1.L = -15; - R6 = ASHIFT R0 BY R1.L (V); - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// right by 15 (sat has no effect) - R7 = 0; - ASTAT = R7; - R0.L = 0x8000; - R0.H = 0x0100; - R1.L = -15; - R6 = ASHIFT R0 BY R1.L (V , S); - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// logic -// right by 15 - R7 = 0; - ASTAT = R7; - R0.L = 0x8000; - R0.H = 0x0100; - R1.L = -15; - R6 = LSHIFT R0 BY R1.L (V); - DBGA ( R6.L , 0x0001 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - pass diff --git a/sim/testsuite/sim/bfin/s2.s b/sim/testsuite/sim/bfin/s2.s deleted file mode 100644 index 4b8ab2d..0000000 --- a/sim/testsuite/sim/bfin/s2.s +++ /dev/null @@ -1,47 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - -// Test pc relative indirect branches. - P4 = 0; - loadsym P1 jtab; - -LL1: - P2 = P1 + ( P4 << 1 ); - R0 = W [ P2 ] (Z); - P0 = R0; - R2 = P4; - -jp: - JUMP ( PC + P0 ); - - DBGA ( R2.L , 0 ); - JUMP.L done; - - DBGA ( R2.L , 1 ); - JUMP.L done; - - DBGA ( R2.L , 2 ); - JUMP.L done; - - DBGA ( R2.L , 3 ); - JUMP.L done; - - DBGA ( R2.L , 4 ); - JUMP.L done; - -done: - P4 += 1; - CC = P4 < 4 (IU); - IF CC JUMP LL1; - pass - - .data - -jtab: - .dw 2; //.dw (2+0*8) - .dw 10; //.dw (2+1*8) - .dw 18; //.dw (2+2*8) - .dw 26; //.dw (2+3*8) - .dw 34; //.dw (2+4*8) diff --git a/sim/testsuite/sim/bfin/s20.s b/sim/testsuite/sim/bfin/s20.s deleted file mode 100644 index 7f97d22..0000000 --- a/sim/testsuite/sim/bfin/s20.s +++ /dev/null @@ -1,25 +0,0 @@ -// Test byte-align instructions -# mach: bfin - -.include "testutils.inc" - start - - - R0.L = 0xabcd; - R0.H = 0x1234; - R1.L = 0x4567; - R1.H = 0xdead; - - R2 = ALIGN8 ( R1 , R0 ); - DBGA ( R2.L , 0x34ab ); - DBGA ( R2.H , 0x6712 ); - - R2 = ALIGN16 ( R1 , R0 ); - DBGA ( R2.L , 0x1234 ); - DBGA ( R2.H , 0x4567 ); - - R2 = ALIGN24 ( R1 , R0 ); - DBGA ( R2.L , 0x6712 ); - DBGA ( R2.H , 0xad45 ); - - pass diff --git a/sim/testsuite/sim/bfin/s21.s b/sim/testsuite/sim/bfin/s21.s deleted file mode 100644 index b528dd9..0000000 --- a/sim/testsuite/sim/bfin/s21.s +++ /dev/null @@ -1,298 +0,0 @@ -// Copyright (c) 1997,1998,1999 Analog Devices Inc., All Rights Reserved -// Test A0 = ROT (A0 by imm6); -# mach: bfin - -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT = R0; - A0 = A1 = 0; - -// rot -// left by 1 -// 00 8000 0001 -> 01 0000 0002 cc=0 - R0.L = 0x0001; - R0.H = 0x8000; - R7 = 0; - CC = R7; - A1 = A0 = 0; - A0.w = R0; - A0 = ROT A0 BY 1; - R1 = A0.w; - DBGA ( R1.L , 0x0002 ); - DBGA ( R1.H , 0x0000 ); - R1.L = A0.x; - DBGA ( R1.L , 0x0001 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// left by 1 -// 80 0000 0001 -> 00 0000 0002 cc=1 - R7 = 0; - CC = R7; - R0.L = 0x0001; - R0.H = 0x0000; - R1.L = 0x0080; - A1 = A0 = 0; - A0.w = R0; - A0.x = R1.L; - A0 = ROT A0 BY 1; - R1 = A0.w; - DBGA ( R1.L , 0x0002 ); - DBGA ( R1.H , 0x0000 ); - R1.L = A0.x; - DBGA ( R1.L , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0001 ); - -// rot -// left by 1 with cc=1 -// 80 8000 0001 -> 01 0000 0003 cc=1 - R7 = 1; - CC = R7; - R0.L = 0x0001; - R0.H = 0x8000; - R1.L = 0x0080; - A1 = A0 = 0; - A0.w = R0; - A0.x = R1.L; - A0 = ROT A0 BY 1; - R1 = A0.w; - DBGA ( R1.L , 0x0003 ); - DBGA ( R1.H , 0x0000 ); - R1.L = A0.x; - DBGA ( R1.L , 0x0001 ); - R7 = CC; - DBGA ( R7.L , 0x0001 ); - -// rot -// left by 2 with cc=1 -// 80 0000 0001 -> 00 0000 0007 cc=0 - R7 = 1; - CC = R7; - R0.L = 0x0001; - R0.H = 0x0000; - R1.L = 0x0080; - A1 = A0 = 0; - A0.w = R0; - A0.x = R1.L; - A0 = ROT A0 BY 2; - R1 = A0.w; - DBGA ( R1.L , 0x0007 ); - DBGA ( R1.H , 0x0000 ); - R1.L = A0.x; - DBGA ( R1.L , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// left by 3 with cc=0 - R7 = 0; - CC = R7; - R0.L = 0x0001; - R0.H = 0x0000; - R1.L = 0x0080; - A1 = A0 = 0; - A0.w = R0; - A0.x = R1.L; - A0 = ROT A0 BY 3; - R1 = A0.w; - DBGA ( R1.L , 0x000a ); - DBGA ( R1.H , 0x0000 ); - R1.L = A0.x; - DBGA ( R1.L , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// left by largest positive magnitude of 31 -// 80 0000 0001 -> 00 a000 0000 cc=0 - R7 = 0; - CC = R7; - R0.L = 0x0001; - R0.H = 0x0000; - R1.L = 0x0080; - A1 = A0 = 0; - A0.w = R0; - A0.x = R1.L; - A0 = ROT A0 BY 31; - R1 = A0.w; - DBGA ( R1.L , 0x0000 ); - DBGA ( R1.H , 0xa000 ); - R1.L = A0.x; - DBGA ( R1.L , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// right by 1 -// 80 0000 0001 -> 40 0000 0000 cc=1 - R7 = 0; - CC = R7; - R0.L = 0x0001; - R0.H = 0x0000; - R1.L = 0x0080; - A1 = A0 = 0; - A0.w = R0; - A0.x = R1.L; - A0 = ROT A0 BY -1; - R1 = A0.w; - DBGA ( R1.L , 0x0000 ); - DBGA ( R1.H , 0x0000 ); - R1.L = A0.x; - DBGA ( R1.L , 0x0040 ); - R7 = CC; - DBGA ( R7.L , 0x0001 ); - -// rot -// right by 1 -// 80 0000 0001 -> c0 0000 0000 cc=1 - R7 = 1; - CC = R7; - R0.L = 0x0001; - R0.H = 0x0000; - R1.L = 0x0080; - A1 = A0 = 0; - A0.w = R0; - A0.x = R1.L; - A0 = ROT A0 BY -1; - R1 = A0.w; - DBGA ( R1.L , 0x0000 ); - DBGA ( R1.H , 0x0000 ); - R1.L = A0.x; - DBGA ( R1.L , 0xffc0 ); - R7 = CC; - DBGA ( R7.L , 0x0001 ); - -// rot -// right by 2 -// 80 0000 0001 -> e0 0000 0000 cc=0 - R7 = 1; - CC = R7; - R0.L = 0x0001; - R0.H = 0x0000; - R1.L = 0x0080; - A1 = A0 = 0; - A0.w = R0; - A0.x = R1.L; - A0 = ROT A0 BY -2; - R1 = A0.w; - DBGA ( R1.L , 0x0000 ); - DBGA ( R1.H , 0x0000 ); - R1.L = A0.x; - DBGA ( R1.L , 0xffe0 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// right by 9 -// 80 0000 0001 -> 01 c000 0000 cc=0 - R7 = 1; - CC = R7; - R0.L = 0x0001; - R0.H = 0x0000; - R1.L = 0x0080; - A1 = A0 = 0; - A0.w = R0; - A0.x = R1.L; - A0 = ROT A0 BY -9; - R1 = A0.w; - DBGA ( R1.L , 0x0000 ); - DBGA ( R1.H , 0xc000 ); - R1.L = A0.x; - DBGA ( R1.L , 0x0001 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// right by 9 with reg -// 80 0000 0001 -> 01 c000 0000 cc=0 - R7 = 1; - CC = R7; - R0.L = 0x0001; - R0.H = 0x0000; - R1.L = 0x0080; - A1 = A0 = 0; - A0.w = R0; - A0.x = R1.L; - R5 = -9; - A0 = ROT A0 BY R5.L; - R1 = A0.w; - DBGA ( R1.L , 0x0000 ); - DBGA ( R1.H , 0xc000 ); - R1.L = A0.x; - DBGA ( R1.L , 0x0001 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot left by 4 with cc=1 - R0.L = 0x789a; - R0.H = 0x3456; - A0.w = R0; - R0.L = 0x12; - A0.x = R0; - - R0 = 1; - CC = R0; - - A0 = ROT A0 BY 4; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x4567 ); DBGA ( R4.L , 0x89a8 ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0023 ); - -// rot left by 28 with cc=1 - R0.L = 0x789a; - R0.H = 0x3456; - A0.w = R0; - R0.L = 0x12; - A0.x = R0; - - R0 = 1; - CC = R0; - - A0 = ROT A0 BY 28; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0xa891 ); DBGA ( R4.L , 0xa2b3 ); - DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff89 ); - -// rot right by 4 with cc=1 - R0.L = 0x789a; - R0.H = 0x3456; - A0.w = R0; - R0.L = 0x12; - A0.x = R0; - - R0 = 1; - CC = R0; - - A0 = ROT A0 BY -4; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x2345 ); DBGA ( R4.L , 0x6789 ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0051 ); - -// rot right by 8 with cc=1 - R0.L = 0x789a; - R0.H = 0x3456; - A0.w = R0; - R0.L = 0x12; - A0.x = R0; - - R0 = 1; - CC = R0; - - A0 = ROT A0 BY -28; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0xcf13 ); DBGA ( R4.L , 0x5123 ); - DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff8a ); - - pass diff --git a/sim/testsuite/sim/bfin/s3.s b/sim/testsuite/sim/bfin/s3.s deleted file mode 100644 index d3178a4..0000000 --- a/sim/testsuite/sim/bfin/s3.s +++ /dev/null @@ -1,88 +0,0 @@ -// SHIFT test program. -// Test A0 = ASHIFT (A0 by r3); -# mach: bfin - -.include "testutils.inc" - start - -// load r0=0x0000001f -// load r1=0x00000020 -// load r2=0x00000000 -// load r3=0x00000000 -// load r4=0x00000001 -// load r5=0x00000080 - loadsym P0, data0; - P1 = P0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - R5 = [ P0 ++ ]; - -// left by largest positive magnitude of 31 (0x1f) -// A0: 80 0000 0001 -> 80 0000 0000 - R7 = 0; - ASTAT = R7; - A0.w = R4; - A0.x = R5.L; - A0 = ASHIFT A0 BY R0.L; - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8000 ); - DBGA ( R7.L , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// left by largest positive magnitude + 1 = 32 (0x20), which is -32 -// A0: 80 0000 0001 -> - R7 = 0; - ASTAT = R7; - A0.w = R4; - A0.x = R5.L; - A0 = ASHIFT A0 BY R1.L; - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0xff80 ); - DBGA ( R6.H , 0xffff ); - DBGA ( R7.L , 0xffff ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// by -1 -// A0: 80 0000 0001 -> c0 0000 0000 - A0.w = R4; - A0.x = R5.L; - - R3.L = 0x00ff; - - A0 = ASHIFT A0 BY R3.L; - R6 = A0.w; - R7.L = A0.x; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0xffc0 ); - - pass - - .data -data0: - .dw 0x001f - .dw 0x0000 - .dw 0x0020 - .dw 0x0000 - .dw 0x0059 - .dw 0x0000 - .dw 0x005a - .dw 0x0000 - .dw 0x0001 - .dw 0x0000 - .dw 0x0080 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/s30.s b/sim/testsuite/sim/bfin/s30.s deleted file mode 100644 index 4ec6ef4..0000000 --- a/sim/testsuite/sim/bfin/s30.s +++ /dev/null @@ -1,152 +0,0 @@ -// Test signbits40 -# mach: bfin - -.include "testutils.inc" - start - - -// positive value in accum, smaller than 1.0 - A1 = A0 = 0; - R0.L = 0xffff; - R0.H = 0x0000; - A0.w = R0; - R0.L = 0x0000; - A0.x = R0; - - R5.L = SIGNBITS A0; - _DBG R5; - A0 = ASHIFT A0 BY R5.L; - _DBG A0; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0x8000 ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); - -// neg value in accum, larger than -1.0 - A1 = A0 = 0; - R0.L = 0x0000; - R0.H = 0xffff; - A0.w = R0; - R0.L = 0x00ff; - A0.x = R0; - - R5.L = SIGNBITS A0; - _DBG R5; - A0 = ASHIFT A0 BY R5.L; - _DBG A0; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 ); - DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); - -// positive value in accum, larger than 1.0 - A1 = A0 = 0; - R0.L = 0xffff; - R0.H = 0xffff; - A0.w = R0; - R0.L = 0x000f; - A0.x = R0; - - R5.L = SIGNBITS A0; - _DBG R5; - A0 = ASHIFT A0 BY R5.L; - _DBG A0; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0xffff ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); - -// negative value in accum, smaller than -1.0 - A1 = A0 = 0; - R0.L = 0x0000; - R0.H = 0x0000; - A0.w = R0; - R0.L = 0x0080; - A0.x = R0; - - R5.L = SIGNBITS A0; - _DBG R5; - A0 = ASHIFT A0 BY R5.L; - _DBG A0; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 ); - DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); - -// no normalization - A1 = A0 = 0; - R0.L = 0xfffa; - R0.H = 0x7fff; - A0.w = R0; - R0.L = 0x0000; - A0.x = R0; - - R5.L = SIGNBITS A0; - _DBG R5; - A0 = ASHIFT A0 BY R5.L; - _DBG A0; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0xfffa ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); - -// no normalization (-1.0) - A1 = A0 = 0; - R0.L = 0x0000; - R0.H = 0x8000; - A0.w = R0; - R0.L = 0x00ff; - A0.x = R0; - - R5.L = SIGNBITS A0; - _DBG R5; - A0 = ASHIFT A0 BY R5.L; - _DBG A0; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 ); - DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); - -// norm by 1 - A1 = A0 = 0; - R0.L = 0x0000; - R0.H = 0x8000; - A0.w = R0; - R0.L = 0x0000; - A0.x = R0; - - R5.L = SIGNBITS A0; - _DBG R5; - A0 = ASHIFT A0 BY R5.L; - _DBG A0; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x4000 ); DBGA ( R4.L , 0x0000 ); - DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); - -// norm by 1 - A1 = A0 = 0; - R0.L = 0x0000; - R0.H = 0x0000; - A0.w = R0; - R0.L = 0x00ff; - A0.x = R0; - - R5.L = SIGNBITS A0; - _DBG R5; - A0 = ASHIFT A0 BY R5.L; - _DBG A0; - - R4 = A0.w; - R5 = A0.x; - DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 ); - DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); - - pass diff --git a/sim/testsuite/sim/bfin/s4.s b/sim/testsuite/sim/bfin/s4.s deleted file mode 100644 index 784c57d..0000000 --- a/sim/testsuite/sim/bfin/s4.s +++ /dev/null @@ -1,214 +0,0 @@ -// Immediate SHIFT test program. -// Test r4 = ASHIFT (r2 by 10); -// Test r4 = LSHIFT (r2 by 10); -// Test r4 = ROT (r2 by 10); -# mach: bfin - -.include "testutils.inc" - start - - - init_r_regs 0; - ASTAT = R0; - -// load r0=0x80000001 -// load r1=0x00000000 -// load r2=0x00000000 -// load r3=0x00000000 -// load r4=0x00000000 -// load r5=0x00000000 - loadsym P0, data0; - R0 = [ P0 ++ ]; - R1 = [ P0 ++ ]; - R2 = [ P0 ++ ]; - R3 = [ P0 ++ ]; - R4 = [ P0 ++ ]; - R5 = [ P0 ++ ]; - -// arithmetic -// left by largest positive magnitude of 31 (0x1f) -// 8000 0001 -> 8000 0000 - R7 = 0; - ASTAT = R7; - R6 = R0 << 31; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// left by 1 -// 8000 0001 -> 0000 0002 - R6 = R0 << 1; - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// right by 1 -// 8000 0001 -> c000 0000 - R7 = 0; - ASTAT = R7; - R6 = R0 >>> 1; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0xc000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// arithmetic -// right by largest negative magnitude of -31 -// 8000 0001 -> ffff ffff - R6 = R0 >>> 31; - DBGA ( R6.L , 0xffff ); - DBGA ( R6.H , 0xffff ); - -// logic -// left by largest positive magnitude of 31 (0x1f) -// 8000 0001 -> 8000 0000 - R6 = R0 << 31; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x8000 ); - -// logic -// left by 1 -// 8000 0001 -> 0000 0002 - R6 = R0 << 1; - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x0000 ); - -// logic -// right by 1 -// 8000 0001 -> 4000 0000 - R6 = R0 >> 1; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x4000 ); - -// logic -// right by largest negative magnitude of -31 -// 8000 0001 -> 0000 0001 - R6 = R0 >> 31; - DBGA ( R6.L , 0x0001 ); - DBGA ( R6.H , 0x0000 ); - -// rot -// left by 1 -// 8000 0001 -> 0000 0002 cc=1 - R7 = 0; - CC = R7; - R6 = ROT R0 BY 1; - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0001 ); - -// rot -// right by -1 -// 8000 0001 -> 4000 0000 cc=1 - R7 = 0; - CC = R7; - R6 = ROT R0 BY -1; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x4000 ); - R7 = CC; - DBGA ( R7.L , 0x0001 ); - -// rot -// right by largest positive magnitude of 31 -// 8000 0001 -> a000 0000 cc=0 - R7 = 0; - CC = R7; - R6 = ROT R0 BY 31; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0xa000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// right by largest positive magnitude of 31 with cc=1 -// 8000 0001 cc=1 -> a000 0000 cc=0 - R7 = 1; - CC = R7; - R6 = ROT R0 BY 31; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0xe000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// right by largest negative magnitude of -31 -// 8000 0001 -> 0000 0005 cc=0 - R7 = 0; - CC = R7; - R6 = ROT R0 BY -31; - DBGA ( R6.L , 0x0005 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// right by largest negative magnitude of -31 with cc=1 -// 8000 0001 cc=1 -> 0000 0007 cc=0 - R7 = 1; - CC = R7; - R6 = ROT R0 BY -31; - DBGA ( R6.L , 0x0007 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// left by 7 -// 8000 0001 cc=1 -> 0000 00e0 cc=0 - R7 = 1; - CC = R7; - R6 = ROT R0 BY 7; - DBGA ( R6.L , 0x00e0 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot by zero -// 8000 0001 -> 8000 000 - R7 = 1; - CC = R7; - R6 = ROT R0 BY 0; - DBGA ( R6.L , 0x0001 ); - DBGA ( R6.H , 0x8000 ); - R7 = CC; - DBGA ( R7.L , 0x0001 ); - -// 0 by 1 - R7 = 0; - R0 = 0; - ASTAT = R7; - R6 = R0 << 1; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - pass - - .data -data0: - .dw 0x0001 - .dw 0x8000 - .dd 0x0000 - .dd 0x0 - .dd 0x0 - .dd 0x0 - .dd 0x0 - .dd 0x0 diff --git a/sim/testsuite/sim/bfin/s5.s b/sim/testsuite/sim/bfin/s5.s deleted file mode 100644 index 7f38cd4..0000000 --- a/sim/testsuite/sim/bfin/s5.s +++ /dev/null @@ -1,118 +0,0 @@ -// Test r4 = ROT (r2 by r3); -# mach: bfin - -.include "testutils.inc" - start - - - R0.L = 0x0001; - R0.H = 0x8000; - -// rot -// left by 1 -// 8000 0001 -> 0000 0002 cc=1 - R7 = 0; - CC = R7; - R1 = 1; - R6 = ROT R0 BY R1.L; - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0001 ); - -// rot -// right by -1 -// 8000 0001 -> 4000 0000 cc=1 - R7 = 0; - CC = R7; - R1.L = 0xffff; // check alternate mechanism for immediates - R1.H = 0xffff; - R6 = ROT R0 BY R1.L; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x4000 ); - R7 = CC; - DBGA ( R7.L , 0x0001 ); - -// rot -// right by largest positive magnitude of 31 -// 8000 0001 -> a000 0000 cc=0 - R7 = 0; - CC = R7; - R1 = 31; - R6 = ROT R0 BY R1.L; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0xa000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// right by largest positive magnitude of 31 with cc=1 -// 8000 0001 cc=1 -> a000 0000 cc=0 - R7 = 1; - CC = R7; - R1 = 31; - R6 = ROT R0 BY R1.L; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0xe000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// right by largest negative magnitude of -31 -// 8000 0001 -> 0000 0005 cc=0 - R7 = 0; - CC = R7; - R1 = -31; - R6 = ROT R0 BY R1.L; - DBGA ( R6.L , 0x0005 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// right by largest negative magnitude of -31 with cc=1 -// 8000 0001 cc=1 -> 0000 0007 cc=0 - R7 = 1; - CC = R7; - R1 = -31; - R6 = ROT R0 BY R1.L; - DBGA ( R6.L , 0x0007 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot -// left by 7 -// 8000 0001 cc=1 -> 0000 00e0 cc=0 - R7 = 1; - CC = R7; - R1 = 7; - R6 = ROT R0 BY R1.L; - DBGA ( R6.L , 0x00e0 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0000 ); - -// rot by zero -// 8000 0001 -> 8000 0000 - R7 = 1; - CC = R7; - R1 = 0; - R6 = ROT R0 BY R1.L; - DBGA ( R6.L , 0x0001 ); - DBGA ( R6.H , 0x8000 ); - R7 = CC; - DBGA ( R7.L , 0x0001 ); - -// rot by 0b1100 0001 is the same as by 1 (mask 6 bits) -// 8000 0001 -> 0000 0002 cc=1 - R7 = 0; - CC = R7; - R1 = 0xc1 (X); - R6 = ROT R0 BY R1.L; - DBGA ( R6.L , 0x0002 ); - DBGA ( R6.H , 0x0000 ); - R7 = CC; - DBGA ( R7.L , 0x0001 ); - - pass diff --git a/sim/testsuite/sim/bfin/s6.s b/sim/testsuite/sim/bfin/s6.s deleted file mode 100644 index 6fc9a2b..0000000 --- a/sim/testsuite/sim/bfin/s6.s +++ /dev/null @@ -1,83 +0,0 @@ -// Test r4 = VMAX/VMAX (r5,r1) A0<<2; -# mach: bfin - -.include "testutils.inc" - start - - -// Both max values are in high half, hence both bits -// into A0 are 1 - A0 = 0; - R1.L = 0x2; // max in r1 is 3 - R1.H = 0x3; - - R0.L = 0x6; // max in r0 is 7 - R0.H = 0x7; - - R6 = VIT_MAX( R1 , R0 ) (ASL); - - DBGA ( R6.L , 0x0007 ); - DBGA ( R6.H , 0x0003 ); - R7 = A0.w; - DBGA ( R7.L , 0x0003 ); - DBGA ( R7.H , 0x0000 ); - R7.L = A0.x; - DBGA ( R7.L , 0x0000 ); - -// max value in r1 is in low, so second bit into A0 is zero - A0 = 0; - R1.L = 0x3; // max in r1 is 3 - R1.H = 0x2; - - R0.L = 0x6; // max in r0 is 7 - R0.H = 0x7; - - R6 = VIT_MAX( R1 , R0 ) (ASL); - - DBGA ( R6.L , 0x0007 ); - DBGA ( R6.H , 0x0003 ); - R7 = A0.w; - DBGA ( R7.L , 0x0002 ); - DBGA ( R7.H , 0x0000 ); - R7.L = A0.x; - DBGA ( R7.L , 0x0000 ); - -// both max values in low, so both bits into A0 are zero - R0.L = 0x8000; - R0.H = 0x0; - A0.w = R0; - R1.L = 0x3; // max in r1 is 3 - R1.H = 0x2; - - R0.L = 0x7; // max in r0 is 7 - R0.H = 0x6; - - R6 = VIT_MAX( R1 , R0 ) (ASL); - - DBGA ( R6.L , 0x0007 ); - DBGA ( R6.H , 0x0003 ); - R7 = A0.w; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0002 ); - R7.L = A0.x; - DBGA ( R7.L , 0x0000 ); - -// Test for correct max when one value overflows - A0 = 0; - R1.L = 0x7fff; // max in r1 is 0x8001 (overflowed) - R1.H = 0x8001; - - R0.L = 0x6; // max in r0 is 7 - R0.H = 0x7; - - R6 = VIT_MAX( R1 , R0 ) (ASL); - - DBGA ( R6.L , 0x0007 ); - DBGA ( R6.H , 0x8001 ); - R7 = A0.w; - DBGA ( R7.L , 0x0003 ); - DBGA ( R7.H , 0x0000 ); - R7.L = A0.x; - DBGA ( R7.L , 0x0000 ); - - pass diff --git a/sim/testsuite/sim/bfin/s7.s b/sim/testsuite/sim/bfin/s7.s deleted file mode 100644 index 0cda60e..0000000 --- a/sim/testsuite/sim/bfin/s7.s +++ /dev/null @@ -1,83 +0,0 @@ -// Test r4 = VMAX/VMAX (r5,r1) A0>>2; -# mach: bfin - -.include "testutils.inc" - start - - -// Both max values are in high half, hence both bits -// into A0 are 1 - A0 = 0; - R1.L = 0x2; // max in r1 is 3 - R1.H = 0x3; - - R0.L = 0x6; // max in r0 is 7 - R0.H = 0x7; - - R6 = VIT_MAX( R1 , R0 ) (ASR); - - DBGA ( R6.L , 0x0007 ); - DBGA ( R6.H , 0x0003 ); - R7 = A0.w; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0xc000 ); - R7.L = A0.x; - DBGA ( R7.L , 0x0000 ); - -// max value in r1 is in low, so second bit into A0 is zero - A0 = 0; - R1.L = 0x3; // max in r1 is 3 - R1.H = 0x2; - - R0.L = 0x6; // max in r0 is 7 - R0.H = 0x7; - - R6 = VIT_MAX( R1 , R0 ) (ASR); - - DBGA ( R6.L , 0x0007 ); - DBGA ( R6.H , 0x0003 ); - R7 = A0.w; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x4000 ); - R7.L = A0.x; - DBGA ( R7.L , 0x0000 ); - -// both max values in low, so both bits into A0 are zero - R0.L = 0x8000; - R0.H = 0x0; - A0.w = R0; - R1.L = 0x3; // max in r1 is 3 - R1.H = 0x2; - - R0.L = 0x7; // max in r0 is 7 - R0.H = 0x6; - - R6 = VIT_MAX( R1 , R0 ) (ASR); - - DBGA ( R6.L , 0x0007 ); - DBGA ( R6.H , 0x0003 ); - R7 = A0.w; - DBGA ( R7.L , 0x2000 ); - DBGA ( R7.H , 0x0000 ); - R7.L = A0.x; - DBGA ( R7.L , 0x0000 ); - -// Test for correct max when one value overflows - A0 = 0; - R1.L = 0x7fff; // max in r1 is 0x8001 (overflowed) - R1.H = 0x8001; - - R0.L = 0x6; // max in r0 is 7 - R0.H = 0x7; - - R6 = VIT_MAX( R1 , R0 ) (ASR); - - DBGA ( R6.L , 0x0007 ); - DBGA ( R6.H , 0x8001 ); - R7 = A0.w; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0xc000 ); - R7.L = A0.x; - DBGA ( R7.L , 0x0000 ); - - pass diff --git a/sim/testsuite/sim/bfin/s8.s b/sim/testsuite/sim/bfin/s8.s deleted file mode 100644 index 46d156e..0000000 --- a/sim/testsuite/sim/bfin/s8.s +++ /dev/null @@ -1,55 +0,0 @@ -// Test rl4 = VMAX r5 A0<<1; -// Test rl4 = VMAX r5 A0>>1; -# mach: bfin - -.include "testutils.inc" - start - - -// max value in high half, hence bit into A0 is one - A0 = 0; - R1.L = 0x2; // max in r1 is 3 - R1.H = 0x3; - - R6.L = VIT_MAX( R1 ) (ASL); - - DBGA ( R6.L , 0x0003 ); - R7 = A0.w; - DBGA ( R7.L , 0x0001 ); - DBGA ( R7.H , 0x0000 ); - R7.L = A0.x; - DBGA ( R7.L , 0x0000 ); - -// max value in low half, hence bit into A0 is zero - R0.L = 0x8000; - R0.H = 0x8000; - A0.w = R0; - R1.L = 0x8001; // max in r1 is 8001 - R1.H = 0x7f00; - - R6.L = VIT_MAX( R1 ) (ASL); - - DBGA ( R6.L , 0x8001 ); - R7 = A0.w; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0001 ); - R7.L = A0.x; - DBGA ( R7.L , 0x0001 ); - -// max value in high half, hence bit into A0 is one - R0.L = 0x8000; - R0.H = 0x0000; - A0.w = R0; - R1.L = 0x7fff; // max in r1 is 8001 - R1.H = 0x8001; - - R6.L = VIT_MAX( R1 ) (ASR); - - DBGA ( R6.L , 0x8001 ); - R7 = A0.w; - DBGA ( R7.L , 0x4000 ); - DBGA ( R7.H , 0x8000 ); - R7.L = A0.x; - DBGA ( R7.L , 0x0000 ); - - pass diff --git a/sim/testsuite/sim/bfin/s9.s b/sim/testsuite/sim/bfin/s9.s deleted file mode 100644 index 7293e3a..0000000 --- a/sim/testsuite/sim/bfin/s9.s +++ /dev/null @@ -1,134 +0,0 @@ -// Test rl3 = ashift (rh0 by 7); -// Test rl3 = lshift (rh0 by 7); -# mach: bfin - -.include "testutils.inc" - start - - init_r_regs 0; - - R0 = 0; - ASTAT = R0; - R0.L = 0x1; - R0.H = 0x1; - R7.L = R0.L << 4; - DBGA ( R7.L , 0x0010 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R0.L = 0x8000; - R0.H = 0x1; - R7.L = R0.L >>> 4; - DBGA ( R7.L , 0xf800 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R0.L = 0x0; - R0.H = 0x1; - R7.L = R0.L << 0; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 0; - R0.L = 0x1; - R0.H = 0x8000; - R7.H = R0.H >>> 4; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0xf800 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 0; - R0.L = 0x1; - R0.H = 0x8000; - R7.L = R0.H >>> 4; - DBGA ( R7.L , 0xf800 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - -// logic shifts - R0 = 0; - ASTAT = R0; - R7 = 0; - R0.L = 0x1; - R0.H = 0x8000; - R7.L = R0.H >> 4; - DBGA ( R7.L , 0x0800 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 0; - R0.L = 0x1; - R0.H = 0x1; - R7.H = R0.L << 4; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0010 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 1; - R0.L = 0x0; - R0.H = 0x0; - R7.L = R0.L << 0; - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - R0 = 0; - ASTAT = R0; - R7 = 1; - R0.L = 0x1; - R0.H = 0x0; - R7.L = R0.L << 15; - DBGA ( R7.L , 0x8000 ); - DBGA ( R7.H , 0x0000 ); - CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); - CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); - CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); - - pass diff --git a/sim/testsuite/sim/bfin/saatest.s b/sim/testsuite/sim/bfin/saatest.s deleted file mode 100644 index 3957627..0000000 --- a/sim/testsuite/sim/bfin/saatest.s +++ /dev/null @@ -1,222 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - I0 = 0 (X); - I1 = 0 (X); - A0 = A1 = 0; - init_r_regs 0; - ASTAT = R0; - -// This section of code will test the SAA instructions and sum of accumulators; - - loadsym I0, tstvecI; - - R0 = [ I0 ++ ]; - R2 = [ I0 ++ ]; - -// +++++++++++++++ TG11.001 +++++++++++++ // -// // -// HH HL LH LL // -// Input: r0 ==> 15 15 15 15 // -// r1 ==> 0 0 0 0 // -// // -// Output:r2 ==> 0 0 0 30 // -// r3 ==> 0 0 0 30 // -// ++++++++++++++++++++++++++++++++++++++++++ // - - SAA ( R1:0 , R3:2 ); - R6 = A1.L + A1.H, R7 = A0.L + A0.H; - DBGA ( R6.L , 0x001e ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x001e ); - DBGA ( R7.H , 0x0000 ); - - A1 = A0 = 0; - -// +++++++++++++++ TG11.002 +++++++++++++ // -// // -// HH HL LH LL // -// Input: r0 ==> 15 15 15 15 // -// r1 ==> 0 0 0 0 // -// // -// Output:r2 ==> 0 0 0 30 // -// r3 ==> 0 0 0 30 // -// ++++++++++++++++++++++++++++++++++++++++++ // - - SAA ( R1:0 , R3:2 ); - R6 = A1.L + A1.H, R7 = A0.L + A0.H; - DBGA ( R6.L , 0x001e ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x001e ); - DBGA ( R7.H , 0x0000 ); - - A1 = A0 = 0; - -// +++++++++++++++ TG11.003 +++++++++++++ // -// // -// HH HL LH LL // -// Input: r0 ==> 240 240 240 240 // -// r1 ==> 0 0 0 0 // -// // -// Output:r2 ==> 0 480 // -// r3 ==> 0 480 // -// ++++++++++++++++++++++++++++++++++++++++++ // - - R0 = [ I0 ++ ]; - R2 = [ I0 ++ ]; - - SAA ( R3:2 , R1:0 ); - R6 = A1.L + A1.H, R7 = A0.L + A0.H; - DBGA ( R6.L , 0x01e0 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x01e0 ); - DBGA ( R7.H , 0x0000 ); - - A1 = A0 = 0; - -// +++++++++++++++ TG11.004 +++++++++++++ // -// // -// HH HL LH LL // -// Input: r0 ==> 240 240 240 240 // -// r1 ==> 0 0 0 0 // -// // -// Output:r2 ==> 0 480 // -// r3 ==> 0 480 // -// ++++++++++++++++++++++++++++++++++++++++++ // - - SAA ( R1:0 , R3:2 ); - R6 = A1.L + A1.H, R7 = A0.L + A0.H; - DBGA ( R6.L , 0x01e0 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x01e0 ); - DBGA ( R7.H , 0x0000 ); - - A1 = A0 = 0; -// +++++++++++++++ TG11.005 +++++++++++++ // -// // -// HH HL LH LL // -// Input: r0 ==> 0 0 0 0 // -// r1 ==> 0 0 0 0 // -// // -// Output:r2 ==> 0 0 // -// r3 ==> 0 0 // -// ++++++++++++++++++++++++++++++++++++++++++ // - - R0 = [ I0 ++ ]; - R2 = [ I0 ++ ]; - - SAA ( R1:0 , R3:2 ); - R6 = A1.L + A1.H, R7 = A0.L + A0.H; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - -// +++++++++++++++ TG11.006 +++++++++++++ // -// // -// HH HL LH LL // -// Input: r0 ==> 255 255 255 255 // -// r1 ==> 255 255 255 255 // -// // -// Output:r2 ==> 0 0 // -// r3 ==> 0 0 // -// ++++++++++++++++++++++++++++++++++++++++++ // - - SAA ( R3:2 , R1:0 ); - R6 = A1.L + A1.H, R7 = A0.L + A0.H; - DBGA ( R6.L , 0x0000 ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0x0000 ); - DBGA ( R7.H , 0x0000 ); - - A1 = A0 = 0; - -// +++++++++++++++ TG12.001 +++++++++++++ // -// // -// HH HL LH LL // -// Input: r0 ==> 255 255 255 255 // -// r1 ==> 255 255 255 255 // -// // -// Output:r2 ==> 0 0 // -// r3 ==> 0 0 // -// ++++++++++++++++++++++++++++++++++++++++++ // - - loadsym I0, tstvecK; - B0 = I0; - L0.L = 4; - loadsym I1, tstvecJ; - B1 = I1; - L1.L = 4; - - P0 = 64 (X); - R0 = [ I0 ++ ]; - R2 = [ I1 ++ ]; - LSETUP ( l$1 , l$1 ) LC0 = P0; -l$1: - SAA ( R1:0 , R3:2 ) || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; - - R2 = A1.L + A1.H, R3 = A0.L + A0.H; - R7 = R2 + R3 (NS); - DBGA ( R7.L , 0xff00 ); - DBGA ( R7.H , 0x0000 ); - - R5.L = 0xfffa; - A1 = R5; - R5.H = 0xfff0; - A0 = R5; - - loadsym I0, tstvecI; - R0 = [ I0 ++ ]; - R2 = [ I0 ++ ]; - SAA ( R1:0 , R3:2 ); - R6 = A1.L + A1.H, R7 = A0.L + A0.H; - DBGA ( R6.L , 0x000e ); - DBGA ( R6.H , 0x0000 ); - DBGA ( R7.L , 0xfffe ); - DBGA ( R7.H , 0xffff ); - - pass - - .data -tstvecI: - .dw 0x0000 - .dw 0x0000 - .dw 0x0f0f - .dw 0x0f0f - .dw 0x0000 - .dw 0x0000 - .dw 0xf0f0 - .dw 0xf0f0 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0xffff - .dw 0xffff - .dw 0xffff - .dw 0xffff - - .data -tstvecJ: - .dw 0xffff - .dw 0xffff - .dw 0xffff - .dw 0xffff - .dw 0xffff - .dw 0xffff - .dw 0xffff - .dw 0xffff - - .data -tstvecK: - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 - .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/se_all16bitopcodes.S b/sim/testsuite/sim/bfin/se_all16bitopcodes.S deleted file mode 100644 index 042621e..0000000 --- a/sim/testsuite/sim/bfin/se_all16bitopcodes.S +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Blackfin testcase for testing illegal/legal 16-bit opcodes from userspace - * we track all instructions which cause some sort of exception when run from - * userspace, this is normally EXCAUSE : - * - 0x21 : illegal instruction - * - 0x22 : illegal instruction combination - * - 0x2e : use of supervisor resource from userspace - * and walk every instruction from 0x0000 to 0xbfff - */ - -# mach: bfin -# sim: --environment operating - -#include "test.h" - -#define SE_ALL_BITS 16 -#define SE_ALL_NEW_INSN_STUB -#include "se_allopcodes.h" - .include "testutils.inc" - -.macro se_all_load_insn - R2 = W[P5]; - R0 = R2; -.endm - -.macro se_all_next_insn - /* increment, and go again. */ - R0 = R2; - - R0 += 1; - /* finish once we hit the 32bit limit */ - R1 = 0xC000 (Z); - CC = R1 == R0; - IF CC JUMP pass_lvl; - - W[P5] = R0; -.endm - -.macro se_all_new_insn_stub - jump _legal_instruction; -.endm - -.macro se_all_insn_init - .dw 0x0000; -.endm -.macro se_all_insn_table - /* this table must be sorted, and end with zero */ - /* start end SEQSTAT */ - .dw 0x0001, 0x000f, 0x21 - .dw 0x0011, 0x0013, 0x2e -.ifndef BFIN_JTAG - .dw 0x0014, 0x0014, 0x2e /* anomaly - RTX works when emulator attached */ -.endif - .dw 0x0015, 0x001F, 0x21 - .dw 0x0021, 0x0022, 0x21 - .dw 0x0026, 0x0026, 0x21 -.ifndef BFIN_JTAG - .dw 0x0027, 0x0027, 0x21 /* anomaly 492 - unknown */ -.endif - .dw 0x0028, 0x002F, 0x21 - .dw 0x0030, 0x0037, 0x2e - .dw 0x0038, 0x003F, 0x21 - .dw 0x0040, 0x0047, 0x2e - .dw 0x0048, 0x004F, 0x21 - .dw 0x0058, 0x005F, 0x21 - .dw 0x0068, 0x006F, 0x21 - .dw 0x0078, 0x007F, 0x21 - .dw 0x0088, 0x008F, 0x21 - .dw 0x0090, 0x009F, 0x2E - .dw 0x00a0, 0x00a0, 0x00 - .dw 0x00a1, 0x00a1, 0x01 - .dw 0x00a2, 0x00a2, 0x02 - .dw 0x00a3, 0x00a3, 0x03 - .dw 0x00a4, 0x00a4, 0x04 - .dw 0x00a5, 0x00a5, 0x05 - .dw 0x00a6, 0x00a6, 0x06 - .dw 0x00a7, 0x00a7, 0x07 - .dw 0x00a8, 0x00a8, 0x08 - .dw 0x00a9, 0x00a9, 0x09 - .dw 0x00aa, 0x00aa, 0x0a - .dw 0x00ab, 0x00ab, 0x0b - .dw 0x00ac, 0x00ac, 0x0c - .dw 0x00ad, 0x00ad, 0x0d - .dw 0x00ae, 0x00ae, 0x0e - .dw 0x00af, 0x00af, 0x0f - .dw 0x00b6, 0x010f, 0x21 - .dw 0x0124, 0x0124, 0x21 -.ifndef BFIN_JTAG - .dw 0x0125, 0x0125, 0x21 /* anomaly 492 res = [SP++] */ -.endif - .dw 0x0128, 0x012F, 0x21 - .dw 0x0138, 0x0138, 0x22 - .dw 0x0139, 0x013F, 0x2E - .dw 0x0164, 0x0164, 0x21 -.ifndef BFIN_JTAG - .dw 0x0165, 0x0165, 0x21 /* anomaly 492 [--SP] = res */ -.endif - .dw 0x0168, 0x016F, 0x21 - .dw 0x0178, 0x017F, 0x2E - .dw 0x0180, 0x01FF, 0x21 - .dw 0x0210, 0x0217, 0x21 -.ifndef BFIN_JTAG - .dw 0x0219, 0x021F, 0x21 /* anomaly 492 CC = !CC opcode is 0000 0010 0001 1xxx */ -.endif - .dw 0x0220, 0x023F, 0x21 - .dw 0x0280, 0x02FF, 0x21 - .dw 0x0305, 0x0305, 0x21 - .dw 0x0325, 0x0325, 0x21 - .dw 0x0345, 0x0345, 0x21 - .dw 0x0365, 0x0365, 0x21 - .dw 0x0385, 0x0385, 0x21 - .dw 0x03a5, 0x03a5, 0x21 - .dw 0x03c5, 0x03c5, 0x21 - .dw 0x03e5, 0x03e5, 0x21 - .dw 0x0400, 0x047F, 0x21 - .dw 0x0486, 0x04Bf, 0x21 - .dw 0x04c6, 0x04FF, 0x21 - .dw 0x0501, 0x0507, 0x21 - .dw 0x0509, 0x050F, 0x21 - .dw 0x0511, 0x0517, 0x21 - .dw 0x0519, 0x051F, 0x21 - .dw 0x0521, 0x0527, 0x21 - .dw 0x0529, 0x052F, 0x21 - .dw 0x0531, 0x0537, 0x21 - .dw 0x0539, 0x053F, 0x21 - .dw 0x0541, 0x0547, 0x21 - .dw 0x0549, 0x054F, 0x21 - .dw 0x0551, 0x0557, 0x21 - .dw 0x0559, 0x055F, 0x21 - .dw 0x0561, 0x0567, 0x21 - .dw 0x0569, 0x056F, 0x21 - .dw 0x0571, 0x0577, 0x21 - .dw 0x0579, 0x057F, 0x21 - .dw 0x0586, 0x0587, 0x21 - .dw 0x058e, 0x058F, 0x21 - .dw 0x0596, 0x0597, 0x21 - .dw 0x059e, 0x059f, 0x21 - .dw 0x05a6, 0x05a7, 0x21 - .dw 0x05ae, 0x05af, 0x21 - .dw 0x05b6, 0x05b7, 0x21 - .dw 0x05be, 0x05bf, 0x21 - .dw 0x05c6, 0x05c7, 0x21 - .dw 0x05ce, 0x05cf, 0x21 - .dw 0x05d6, 0x05d7, 0x21 - .dw 0x05de, 0x05df, 0x21 - .dw 0x05e6, 0x05e7, 0x21 - .dw 0x05ee, 0x05ef, 0x21 - .dw 0x05f6, 0x05f7, 0x21 - .dw 0x05fe, 0x05ff, 0x21 - .dw 0x0a81, 0x0aff, 0x21 - .dw 0x0b01, 0x0b7f, 0x21 - .dw 0x0b81, 0x0bff, 0x21 - .dw 0x0e80, 0x0fff, 0x21 - .dw 0x3104, 0x3105, 0x21 - .dw 0x310c, 0x310d, 0x21 - .dw 0x3114, 0x3115, 0x21 - .dw 0x311c, 0x311d, 0x21 - .dw 0x3124, 0x3125, 0x21 - .dw 0x312c, 0x312d, 0x21 - .dw 0x3134, 0x3135, 0x21 - .dw 0x313c, 0x313d, 0x21 - .dw 0x3140, 0x317F, 0x21 - .dw 0x31c0, 0x31ff, 0x2E - .dw 0x3304, 0x3305, 0x21 - .dw 0x330c, 0x330d, 0x21 - .dw 0x3314, 0x3315, 0x21 - .dw 0x331c, 0x331d, 0x21 - .dw 0x3324, 0x3325, 0x21 - .dw 0x332c, 0x332d, 0x21 - .dw 0x3334, 0x3335, 0x21 - .dw 0x333c, 0x333d, 0x21 - .dw 0x3340, 0x337f, 0x21 - .dw 0x33c0, 0x33ff, 0x2e - .dw 0x3504, 0x3507, 0x21 - .dw 0x350c, 0x350F, 0x21 - .dw 0x3514, 0x3517, 0x21 - .dw 0x351c, 0x351F, 0x21 - .dw 0x3524, 0x3527, 0x21 - .dw 0x352c, 0x352f, 0x21 - .dw 0x3534, 0x3537, 0x21 - .dw 0x353c, 0x353f, 0x21 - .dw 0x3540, 0x35c6, 0x21 - .dw 0x35c7, 0x35c7, 0x2e - .dw 0x35c8, 0x35ce, 0x21 - .dw 0x35cf, 0x35cf, 0x2e - .dw 0x35d0, 0x35d6, 0x21 - .dw 0x35d7, 0x35d7, 0x2e - .dw 0x35d8, 0x35de, 0x21 - .dw 0x35df, 0x35df, 0x2e - .dw 0x35e0, 0x35e6, 0x21 - .dw 0x35e7, 0x35e7, 0x2e - .dw 0x35e8, 0x35ee, 0x21 - .dw 0x35ef, 0x35ef, 0x2e - .dw 0x35f0, 0x35f6, 0x21 - .dw 0x35f7, 0x35f7, 0x2e - .dw 0x35f8, 0x35fe, 0x21 - .dw 0x35ff, 0x35ff, 0x2e - .dw 0x3704, 0x3707, 0x21 - .dw 0x370c, 0x370f, 0x21 - .dw 0x3714, 0x3717, 0x21 - .dw 0x371c, 0x371f, 0x21 - .dw 0x3724, 0x3727, 0x21 - .dw 0x372c, 0x372f, 0x21 - .dw 0x3734, 0x3737, 0x21 - .dw 0x373c, 0x37c6, 0x21 - .dw 0x37c7, 0x37c7, 0x2e - .dw 0x37c8, 0x37ce, 0x21 - .dw 0x37cf, 0x37cf, 0x2e - .dw 0x37d0, 0x37d6, 0x21 - .dw 0x37d7, 0x37d7, 0x2e - .dw 0x37d8, 0x37de, 0x21 - .dw 0x37df, 0x37df, 0x2e - .dw 0x37e0, 0x37e6, 0x21 - .dw 0x37e7, 0x37e7, 0x2e - .dw 0x37e8, 0x37ee, 0x21 - .dw 0x37ef, 0x37ef, 0x2e - .dw 0x37f0, 0x37f6, 0x21 - .dw 0x37f7, 0x37f7, 0x2e - .dw 0x37f8, 0x37fe, 0x21 - .dw 0x37ff, 0x37ff, 0x2e - .dw 0x3820, 0x382f, 0x21 - .dw 0x3860, 0x386f, 0x21 - .dw 0x38a0, 0x38af, 0x21 - .dw 0x38b0, 0x38bf, 0x21 - .dw 0x38e0, 0x38ef, 0x21 - .dw 0x38f0, 0x38ff, 0x21 - .dw 0x3904, 0x3907, 0x21 - .dw 0x390c, 0x390f, 0x21 - .dw 0x3914, 0x3917, 0x21 - .dw 0x391c, 0x392f, 0x21 - .dw 0x3934, 0x3937, 0x21 - .dw 0x393c, 0x39bf, 0x21 - .dw 0x397f, 0x397f, 0x2e - .dw 0x3980, 0x39bf, 0x21 - .dw 0x39c0, 0x39c0, 0x2e - .dw 0x39c1, 0x39c7, 0x21 - .dw 0x39c8, 0x39c8, 0x2e - .dw 0x39c9, 0x39cf, 0x21 - .dw 0x39d0, 0x39d0, 0x2e - .dw 0x39d1, 0x39d7, 0x21 - .dw 0x39d8, 0x39d8, 0x2e - .dw 0x39d9, 0x39ef, 0x21 - .dw 0x39f0, 0x39f0, 0x2e - .dw 0x39f1, 0x39f6, 0x21 - .dw 0x39f7, 0x39f8, 0x2e - .dw 0x39f9, 0x39fe, 0x21 - .dw 0x39ff, 0x39ff, 0x2e - .dw 0x3a00, 0x3bff, 0x21 - .dw 0x3c80, 0x3cff, 0x21 - .dw 0x3d04, 0x3d07, 0x21 - .dw 0x3d0c, 0x3d0f, 0x21 - .dw 0x3d14, 0x3d17, 0x21 - .dw 0x3d1c, 0x3d1f, 0x21 - .dw 0x3d24, 0x3d27, 0x21 - .dw 0x3d2c, 0x3d2f, 0x21 - .dw 0x3d34, 0x3d37, 0x21 - .dw 0x3d3c, 0x3dbf, 0X21 - .dw 0x3dc0, 0x3dc0, 0x2e - .dw 0x3dc1, 0x3dc6, 0x21 - .dw 0x3dc7, 0x3dc8, 0x2e - .dw 0x3dc9, 0x3dce, 0x21 - .dw 0x3dcf, 0x3dd0, 0x2e - .dw 0x3dd1, 0x3dd6, 0x21 - .dw 0x3dd7, 0x3dd8, 0x2e - .dw 0x3dd9, 0x3dde, 0x21 - .dw 0x3ddf, 0x3de0, 0x2e - .dw 0x3de1, 0x3de6, 0x21 - .dw 0x3de7, 0x3de8, 0x2e - .dw 0x3de9, 0x3dee, 0x21 - .dw 0x3def, 0x3df0, 0x2e - .dw 0x3df1, 0x3df6, 0x21 - .dw 0x3df7, 0x3df8, 0x2e - .dw 0x3df9, 0x3dfe, 0x21 - .dw 0x3dff, 0x3e7f, 0x2e - .dw 0x3e80, 0x3eb7, 0x21 - .dw 0x3eb8, 0x3ebf, 0x2e - .dw 0x3ec0, 0x3ef7, 0x21 - .dw 0x3ef8, 0x3f03, 0x2e - .dw 0x3f04, 0x3f07, 0x21 - .dw 0x3f08, 0x3f0b, 0x2e - .dw 0x3f0c, 0x3f0f, 0x21 - .dw 0x3f10, 0x3f13, 0x2e - .dw 0x3f14, 0x3f17, 0x21 - .dw 0x3f18, 0x3f1b, 0x2e - .dw 0x3f1c, 0x3f1f, 0x21 - .dw 0x3f20, 0x3f23, 0x2e - .dw 0x3f24, 0x3f27, 0x21 - .dw 0x3f28, 0x3f2b, 0x2e - .dw 0x3f2c, 0x3f2f, 0x21 - .dw 0x3f30, 0x3f33, 0x2e - .dw 0x3f34, 0x3f37, 0x21 - .dw 0x3f38, 0x3f3b, 0x2e - .dw 0x3f3c, 0x3f3d, 0x21 - .dw 0x3f3e, 0x3f3f, 0x2e - .dw 0x3f40, 0x3fb7, 0x21 - .dw 0x3fb8, 0x3fc0, 0x2e - .dw 0x3fc1, 0x3fc6, 0x21 - .dw 0x3fc7, 0x3fc8, 0x2e - .dw 0x3fc9, 0x3fce, 0x21 - .dw 0x3fcf, 0x3fd0, 0x2e - .dw 0x3fd1, 0x3fd6, 0x21 - .dw 0x3fd7, 0x3fd8, 0x2e - .dw 0x3fd9, 0x3fde, 0x21 - .dw 0x3fdf, 0x3fe0, 0x2e - .dw 0x3fe1, 0x3fe6, 0x21 - .dw 0x3fe7, 0x3fe8, 0x2e - .dw 0x3fe9, 0x3fee, 0x21 - .dw 0x3fef, 0x3ff0, 0x2e - .dw 0x3ff1, 0x3ff6, 0x21 - .dw 0x3ff7, 0x3fff, 0x2e - .dw 0x4180, 0x41FF, 0x21 - .dw 0x4480, 0x44bF, 0x21 - .dw 0x4600, 0x47FF, 0x21 - .dw 0x7000, 0x7FFF, 0x21 - .dw 0x9040, 0x9040, 0x22 - .dw 0x9049, 0x9049, 0x22 - .dw 0x9052, 0x9052, 0x22 - .dw 0x905b, 0x905b, 0x22 - .dw 0x9064, 0x9064, 0x22 - .dw 0x906d, 0x906d, 0x22 - .dw 0x9076, 0x9076, 0x22 - .dw 0x907f, 0x907f, 0x22 - .dw 0x90c0, 0x90c0, 0x22 - .dw 0x90c9, 0x90c9, 0x22 - .dw 0x90d2, 0x90d2, 0x22 - .dw 0x90db, 0x90db, 0x22 - .dw 0x90e4, 0x90e4, 0x22 - .dw 0x90ed, 0x90ed, 0x22 - .dw 0x90f6, 0x90f6, 0x22 - .dw 0x90ff, 0x90ff, 0x22 - .dw 0x9180, 0x91ff, 0x21 - .dw 0x9380, 0x93ff, 0x21 - .dw 0x9580, 0x95ff, 0x21 - .dw 0x9640, 0x967f, 0x21 - .dw 0x96c0, 0x96ff, 0x21 - .dw 0x9740, 0x97ff, 0x21 - .dw 0x9980, 0x99ff, 0x21 - .dw 0x9a40, 0x9a7f, 0x21 - .dw 0x9ac0, 0x9aff, 0x21 - .dw 0x9b40, 0x9bff, 0x21 - .dw 0x9c60, 0x9c7f, 0x21 - .dw 0x9ce0, 0x9cff, 0x21 - .dw 0x9d60, 0x9d7f, 0x21 - .dw 0x9ef0, 0x9eff, 0x21 - .dw 0x9f70, 0x9f7f, 0x21 - .dw 0x0000, 0x0000, 0x00 -.endm - - se_all_test diff --git a/sim/testsuite/sim/bfin/se_all32bitopcodes.S b/sim/testsuite/sim/bfin/se_all32bitopcodes.S deleted file mode 100644 index 6ffe6d1..0000000 --- a/sim/testsuite/sim/bfin/se_all32bitopcodes.S +++ /dev/null @@ -1,34184 +0,0 @@ -/* - * Blackfin testcase for testing illegal/legal 32-bit opcodes from userspace - * we track all instructions which cause some sort of exception when run from - * userspace, this is normally EXCAUSE : - * - 0x21 : illegal instruction - * - 0x22 : illegal instruction combination - * - 0x2e : use of supervisor resource from userspace - * and walk every instruction from 0x00000000 to 0xffffffff (and have 0xc000 set) - */ - -# Don't want to enable for normal `make check` as it takes way too long in -# the sim -- executes over 3 billion insns, and even at 10 MIPS, that's 10+ -# minutes. Useful for directed testing, but that's about it. -# mach: none -# sim: --environment operating -# xfail: too many invalid insns are decoded as valid - -#include "test.h" - -#define SE_ALL_BITS 32 -#include "se_allopcodes.h" - .include "testutils.inc" - -.macro se_all_load_insn - R2 = [P5]; - R0 = R2 << 16; - R1 = R2 >> 16; - R0 = R0 | R1; -.endm - -.macro se_all_next_insn - /* increment, and go again. */ - R0 = R2; - - /* Is this the last insn we'll execute ? */ - imm32 R1, 0xfffff7ff; - CC = R1 == R0; - IF CC JUMP pass_lvl; - - /* cut across the opcode space in an efficient manner: - * increment the high 16bits first since the low 16bits encode - * the type of insn ... */ - imm32 R1, 0x10000; - R0 = R1 + R0; - CC = R1 < R0 (IU); - IF CC jump 1f (bp); - - R0 += 1; - /* skip any 16bit insn chunks */ - R1 = R0; - R1.L = 0xC000; - CC = R0 < R1 (IU); - IF CC R0 = R1; -1: - - /* skip parallel insns */ - R1 = R0; - R1.L = 0xe800; /* allow linkage insns */ - CC = R0 == R1; - IF CC jump 1f; - CC = BITTST (R0, 11); - IF !CC jump 1f (bp); - R1 = 0x800; - R0 = R0 + R1; -1: - -.ifndef BFIN_JTAG - /* Skip debug insns when running in the sim. */ - R1.L = 0xff00; - R1.H = 0x0000; - R2 = R0 & R1; - R1.L = 0xf000; - CC = R1 == R2; - IF !CC jump 1f (bp); - R0.L = 0xf100; - R0.H = 0x0000; -1: -.endif - - [P5] = R0; -.endm - -.macro se_all_insn_init - .dw 0xc000; - .dw 0x0000; -.endm -.macro se_all_insn_table - /* this table must be sorted, and end with zero */ - /* start end SEQSTAT */ - .dw 0x1a00, 0xc000, 0x1fff, 0xc000, 0x21, 0 - .dw 0x3a00, 0xc000, 0x3fff, 0xc000, 0x21, 0 - .dw 0x5a00, 0xc000, 0x5fff, 0xc000, 0x21, 0 - .dw 0x7a00, 0xc000, 0x7fff, 0xc000, 0x21, 0 - .dw 0x9a00, 0xc000, 0x9fff, 0xc000, 0x21, 0 - .dw 0xba00, 0xc000, 0xbfff, 0xc000, 0x21, 0 - .dw 0xda00, 0xc000, 0xdfff, 0xc000, 0x21, 0 - .dw 0xfa00, 0xc000, 0xffff, 0xc000, 0x21, 0 - .dw 0x1a00, 0xc001, 0x1fff, 0xc001, 0x21, 0 - .dw 0x3a00, 0xc001, 0x3fff, 0xc001, 0x21, 0 - .dw 0x5a00, 0xc001, 0x5fff, 0xc001, 0x21, 0 - .dw 0x7a00, 0xc001, 0x7fff, 0xc001, 0x21, 0 - .dw 0x9a00, 0xc001, 0x9fff, 0xc001, 0x21, 0 - .dw 0xba00, 0xc001, 0xbfff, 0xc001, 0x21, 0 - .dw 0xda00, 0xc001, 0xdfff, 0xc001, 0x21, 0 - .dw 0xfa00, 0xc001, 0xffff, 0xc001, 0x21, 0 - .dw 0x1a00, 0xc002, 0x1fff, 0xc002, 0x21, 0 - .dw 0x3a00, 0xc002, 0x3fff, 0xc002, 0x21, 0 - .dw 0x5a00, 0xc002, 0x5fff, 0xc002, 0x21, 0 - .dw 0x7a00, 0xc002, 0x7fff, 0xc002, 0x21, 0 - .dw 0x9a00, 0xc002, 0x9fff, 0xc002, 0x21, 0 - .dw 0xba00, 0xc002, 0xbfff, 0xc002, 0x21, 0 - .dw 0xda00, 0xc002, 0xdfff, 0xc002, 0x21, 0 - .dw 0xfa00, 0xc002, 0xffff, 0xc002, 0x21, 0 - .dw 0x1a00, 0xc003, 0x1fff, 0xc003, 0x21, 0 - .dw 0x3a00, 0xc003, 0xffff, 0xc003, 0x21, 0 - .dw 0x1a00, 0xc004, 0x1fff, 0xc004, 0x21, 0 - .dw 0x3a00, 0xc004, 0x3fff, 0xc004, 0x21, 0 - .dw 0x5a00, 0xc004, 0x5fff, 0xc004, 0x21, 0 - .dw 0x7a00, 0xc004, 0x7fff, 0xc004, 0x21, 0 - .dw 0x9a00, 0xc004, 0x9fff, 0xc004, 0x21, 0 - .dw 0xba00, 0xc004, 0xbfff, 0xc004, 0x21, 0 - .dw 0xda00, 0xc004, 0xdfff, 0xc004, 0x21, 0 - .dw 0xfa00, 0xc004, 0xffff, 0xc004, 0x21, 0 - .dw 0x1a00, 0xc005, 0x1fff, 0xc005, 0x21, 0 - .dw 0x3a00, 0xc005, 0x3fff, 0xc005, 0x21, 0 - .dw 0x5a00, 0xc005, 0x5fff, 0xc005, 0x21, 0 - .dw 0x7a00, 0xc005, 0x7fff, 0xc005, 0x21, 0 - .dw 0x9a00, 0xc005, 0x9fff, 0xc005, 0x21, 0 - .dw 0xba00, 0xc005, 0xbfff, 0xc005, 0x21, 0 - .dw 0xda00, 0xc005, 0xdfff, 0xc005, 0x21, 0 - .dw 0xfa00, 0xc005, 0xffff, 0xc005, 0x21, 0 - .dw 0x1a00, 0xc006, 0x1fff, 0xc006, 0x21, 0 - .dw 0x3a00, 0xc006, 0x3fff, 0xc006, 0x21, 0 - .dw 0x5a00, 0xc006, 0x5fff, 0xc006, 0x21, 0 - .dw 0x7a00, 0xc006, 0x7fff, 0xc006, 0x21, 0 - .dw 0x9a00, 0xc006, 0x9fff, 0xc006, 0x21, 0 - .dw 0xba00, 0xc006, 0xbfff, 0xc006, 0x21, 0 - .dw 0xda00, 0xc006, 0xdfff, 0xc006, 0x21, 0 - .dw 0xfa00, 0xc006, 0xffff, 0xc006, 0x21, 0 - .dw 0x1a00, 0xc007, 0x1fff, 0xc007, 0x21, 0 - .dw 0x3a00, 0xc007, 0x1fff, 0xc008, 0x21, 0 - .dw 0x2040, 0xc008, 0x207f, 0xc008, 0x21, 0 - .dw 0x20c0, 0xc008, 0x20ff, 0xc008, 0x21, 0 - .dw 0x2140, 0xc008, 0x217f, 0xc008, 0x21, 0 - .dw 0x21c0, 0xc008, 0x21ff, 0xc008, 0x21, 0 - .dw 0x2240, 0xc008, 0x227f, 0xc008, 0x21, 0 - .dw 0x22c0, 0xc008, 0x22ff, 0xc008, 0x21, 0 - .dw 0x2340, 0xc008, 0x237f, 0xc008, 0x21, 0 - .dw 0x23c0, 0xc008, 0x23ff, 0xc008, 0x21, 0 - .dw 0x2440, 0xc008, 0x247f, 0xc008, 0x21, 0 - .dw 0x24c0, 0xc008, 0x24ff, 0xc008, 0x21, 0 - .dw 0x2540, 0xc008, 0x257f, 0xc008, 0x21, 0 - .dw 0x25c0, 0xc008, 0x25ff, 0xc008, 0x21, 0 - .dw 0x2640, 0xc008, 0x267f, 0xc008, 0x21, 0 - .dw 0x26c0, 0xc008, 0x26ff, 0xc008, 0x21, 0 - .dw 0x2740, 0xc008, 0x277f, 0xc008, 0x21, 0 - .dw 0x27c0, 0xc008, 0x27ff, 0xc008, 0x21, 0 - .dw 0x2840, 0xc008, 0x287f, 0xc008, 0x21, 0 - .dw 0x28c0, 0xc008, 0x28ff, 0xc008, 0x21, 0 - .dw 0x2940, 0xc008, 0x297f, 0xc008, 0x21, 0 - .dw 0x29c0, 0xc008, 0x29ff, 0xc008, 0x21, 0 - .dw 0x2a40, 0xc008, 0x2a7f, 0xc008, 0x21, 0 - .dw 0x2ac0, 0xc008, 0x2aff, 0xc008, 0x21, 0 - .dw 0x2b40, 0xc008, 0x2b7f, 0xc008, 0x21, 0 - .dw 0x2bc0, 0xc008, 0x2bff, 0xc008, 0x21, 0 - .dw 0x2c40, 0xc008, 0x2c7f, 0xc008, 0x21, 0 - .dw 0x2cc0, 0xc008, 0x2cff, 0xc008, 0x21, 0 - .dw 0x2d40, 0xc008, 0x2d7f, 0xc008, 0x21, 0 - .dw 0x2dc0, 0xc008, 0x2dff, 0xc008, 0x21, 0 - .dw 0x2e40, 0xc008, 0x2e7f, 0xc008, 0x21, 0 - .dw 0x2ec0, 0xc008, 0x2eff, 0xc008, 0x21, 0 - .dw 0x2f40, 0xc008, 0x2f7f, 0xc008, 0x21, 0 - .dw 0x2fc0, 0xc008, 0x2fff, 0xc008, 0x21, 0 - .dw 0x3040, 0xc008, 0x307f, 0xc008, 0x21, 0 - .dw 0x30c0, 0xc008, 0x30ff, 0xc008, 0x21, 0 - .dw 0x3140, 0xc008, 0x317f, 0xc008, 0x21, 0 - .dw 0x31c0, 0xc008, 0x31ff, 0xc008, 0x21, 0 - .dw 0x3240, 0xc008, 0x327f, 0xc008, 0x21, 0 - .dw 0x32c0, 0xc008, 0x32ff, 0xc008, 0x21, 0 - .dw 0x3340, 0xc008, 0x337f, 0xc008, 0x21, 0 - .dw 0x33c0, 0xc008, 0x33ff, 0xc008, 0x21, 0 - .dw 0x3440, 0xc008, 0x347f, 0xc008, 0x21, 0 - .dw 0x34c0, 0xc008, 0x34ff, 0xc008, 0x21, 0 - .dw 0x3540, 0xc008, 0x357f, 0xc008, 0x21, 0 - .dw 0x35c0, 0xc008, 0x35ff, 0xc008, 0x21, 0 - .dw 0x3640, 0xc008, 0x367f, 0xc008, 0x21, 0 - .dw 0x36c0, 0xc008, 0x36ff, 0xc008, 0x21, 0 - .dw 0x3740, 0xc008, 0x377f, 0xc008, 0x21, 0 - .dw 0x37c0, 0xc008, 0x37ff, 0xc008, 0x21, 0 - .dw 0x3840, 0xc008, 0x387f, 0xc008, 0x21, 0 - .dw 0x38c0, 0xc008, 0x38ff, 0xc008, 0x21, 0 - .dw 0x3940, 0xc008, 0x397f, 0xc008, 0x21, 0 - .dw 0x39c0, 0xc008, 0x5fff, 0xc008, 0x21, 0 - .dw 0x6040, 0xc008, 0x607f, 0xc008, 0x21, 0 - .dw 0x60c0, 0xc008, 0x60ff, 0xc008, 0x21, 0 - .dw 0x6140, 0xc008, 0x617f, 0xc008, 0x21, 0 - .dw 0x61c0, 0xc008, 0x61ff, 0xc008, 0x21, 0 - .dw 0x6240, 0xc008, 0x627f, 0xc008, 0x21, 0 - .dw 0x62c0, 0xc008, 0x62ff, 0xc008, 0x21, 0 - .dw 0x6340, 0xc008, 0x637f, 0xc008, 0x21, 0 - .dw 0x63c0, 0xc008, 0x63ff, 0xc008, 0x21, 0 - .dw 0x6440, 0xc008, 0x647f, 0xc008, 0x21, 0 - .dw 0x64c0, 0xc008, 0x64ff, 0xc008, 0x21, 0 - .dw 0x6540, 0xc008, 0x657f, 0xc008, 0x21, 0 - .dw 0x65c0, 0xc008, 0x65ff, 0xc008, 0x21, 0 - .dw 0x6640, 0xc008, 0x667f, 0xc008, 0x21, 0 - .dw 0x66c0, 0xc008, 0x66ff, 0xc008, 0x21, 0 - .dw 0x6740, 0xc008, 0x677f, 0xc008, 0x21, 0 - .dw 0x67c0, 0xc008, 0x67ff, 0xc008, 0x21, 0 - .dw 0x6840, 0xc008, 0x687f, 0xc008, 0x21, 0 - .dw 0x68c0, 0xc008, 0x68ff, 0xc008, 0x21, 0 - .dw 0x6940, 0xc008, 0x697f, 0xc008, 0x21, 0 - .dw 0x69c0, 0xc008, 0x69ff, 0xc008, 0x21, 0 - .dw 0x6a40, 0xc008, 0x6a7f, 0xc008, 0x21, 0 - .dw 0x6ac0, 0xc008, 0x6aff, 0xc008, 0x21, 0 - .dw 0x6b40, 0xc008, 0x6b7f, 0xc008, 0x21, 0 - .dw 0x6bc0, 0xc008, 0x6bff, 0xc008, 0x21, 0 - .dw 0x6c40, 0xc008, 0x6c7f, 0xc008, 0x21, 0 - .dw 0x6cc0, 0xc008, 0x6cff, 0xc008, 0x21, 0 - .dw 0x6d40, 0xc008, 0x6d7f, 0xc008, 0x21, 0 - .dw 0x6dc0, 0xc008, 0x6dff, 0xc008, 0x21, 0 - .dw 0x6e40, 0xc008, 0x6e7f, 0xc008, 0x21, 0 - .dw 0x6ec0, 0xc008, 0x6eff, 0xc008, 0x21, 0 - .dw 0x6f40, 0xc008, 0x6f7f, 0xc008, 0x21, 0 - .dw 0x6fc0, 0xc008, 0x6fff, 0xc008, 0x21, 0 - .dw 0x7040, 0xc008, 0x707f, 0xc008, 0x21, 0 - .dw 0x70c0, 0xc008, 0x70ff, 0xc008, 0x21, 0 - .dw 0x7140, 0xc008, 0x717f, 0xc008, 0x21, 0 - .dw 0x71c0, 0xc008, 0x71ff, 0xc008, 0x21, 0 - .dw 0x7240, 0xc008, 0x727f, 0xc008, 0x21, 0 - .dw 0x72c0, 0xc008, 0x72ff, 0xc008, 0x21, 0 - .dw 0x7340, 0xc008, 0x737f, 0xc008, 0x21, 0 - .dw 0x73c0, 0xc008, 0x73ff, 0xc008, 0x21, 0 - .dw 0x7440, 0xc008, 0x747f, 0xc008, 0x21, 0 - .dw 0x74c0, 0xc008, 0x74ff, 0xc008, 0x21, 0 - .dw 0x7540, 0xc008, 0x757f, 0xc008, 0x21, 0 - .dw 0x75c0, 0xc008, 0x75ff, 0xc008, 0x21, 0 - .dw 0x7640, 0xc008, 0x767f, 0xc008, 0x21, 0 - .dw 0x76c0, 0xc008, 0x76ff, 0xc008, 0x21, 0 - .dw 0x7740, 0xc008, 0x777f, 0xc008, 0x21, 0 - .dw 0x77c0, 0xc008, 0x77ff, 0xc008, 0x21, 0 - .dw 0x7840, 0xc008, 0x787f, 0xc008, 0x21, 0 - .dw 0x78c0, 0xc008, 0x78ff, 0xc008, 0x21, 0 - .dw 0x7940, 0xc008, 0x797f, 0xc008, 0x21, 0 - .dw 0x79c0, 0xc008, 0x9fff, 0xc008, 0x21, 0 - .dw 0xa040, 0xc008, 0xa07f, 0xc008, 0x21, 0 - .dw 0xa0c0, 0xc008, 0xa0ff, 0xc008, 0x21, 0 - .dw 0xa140, 0xc008, 0xa17f, 0xc008, 0x21, 0 - .dw 0xa1c0, 0xc008, 0xa1ff, 0xc008, 0x21, 0 - .dw 0xa240, 0xc008, 0xa27f, 0xc008, 0x21, 0 - .dw 0xa2c0, 0xc008, 0xa2ff, 0xc008, 0x21, 0 - .dw 0xa340, 0xc008, 0xa37f, 0xc008, 0x21, 0 - .dw 0xa3c0, 0xc008, 0xa3ff, 0xc008, 0x21, 0 - .dw 0xa440, 0xc008, 0xa47f, 0xc008, 0x21, 0 - .dw 0xa4c0, 0xc008, 0xa4ff, 0xc008, 0x21, 0 - .dw 0xa540, 0xc008, 0xa57f, 0xc008, 0x21, 0 - .dw 0xa5c0, 0xc008, 0xa5ff, 0xc008, 0x21, 0 - .dw 0xa640, 0xc008, 0xa67f, 0xc008, 0x21, 0 - .dw 0xa6c0, 0xc008, 0xa6ff, 0xc008, 0x21, 0 - .dw 0xa740, 0xc008, 0xa77f, 0xc008, 0x21, 0 - .dw 0xa7c0, 0xc008, 0xa7ff, 0xc008, 0x21, 0 - .dw 0xa840, 0xc008, 0xa87f, 0xc008, 0x21, 0 - .dw 0xa8c0, 0xc008, 0xa8ff, 0xc008, 0x21, 0 - .dw 0xa940, 0xc008, 0xa97f, 0xc008, 0x21, 0 - .dw 0xa9c0, 0xc008, 0xa9ff, 0xc008, 0x21, 0 - .dw 0xaa40, 0xc008, 0xaa7f, 0xc008, 0x21, 0 - .dw 0xaac0, 0xc008, 0xaaff, 0xc008, 0x21, 0 - .dw 0xab40, 0xc008, 0xab7f, 0xc008, 0x21, 0 - .dw 0xabc0, 0xc008, 0xabff, 0xc008, 0x21, 0 - .dw 0xac40, 0xc008, 0xac7f, 0xc008, 0x21, 0 - .dw 0xacc0, 0xc008, 0xacff, 0xc008, 0x21, 0 - .dw 0xad40, 0xc008, 0xad7f, 0xc008, 0x21, 0 - .dw 0xadc0, 0xc008, 0xadff, 0xc008, 0x21, 0 - .dw 0xae40, 0xc008, 0xae7f, 0xc008, 0x21, 0 - .dw 0xaec0, 0xc008, 0xaeff, 0xc008, 0x21, 0 - .dw 0xaf40, 0xc008, 0xaf7f, 0xc008, 0x21, 0 - .dw 0xafc0, 0xc008, 0xafff, 0xc008, 0x21, 0 - .dw 0xb040, 0xc008, 0xb07f, 0xc008, 0x21, 0 - .dw 0xb0c0, 0xc008, 0xb0ff, 0xc008, 0x21, 0 - .dw 0xb140, 0xc008, 0xb17f, 0xc008, 0x21, 0 - .dw 0xb1c0, 0xc008, 0xb1ff, 0xc008, 0x21, 0 - .dw 0xb240, 0xc008, 0xb27f, 0xc008, 0x21, 0 - .dw 0xb2c0, 0xc008, 0xb2ff, 0xc008, 0x21, 0 - .dw 0xb340, 0xc008, 0xb37f, 0xc008, 0x21, 0 - .dw 0xb3c0, 0xc008, 0xb3ff, 0xc008, 0x21, 0 - .dw 0xb440, 0xc008, 0xb47f, 0xc008, 0x21, 0 - .dw 0xb4c0, 0xc008, 0xb4ff, 0xc008, 0x21, 0 - .dw 0xb540, 0xc008, 0xb57f, 0xc008, 0x21, 0 - .dw 0xb5c0, 0xc008, 0xb5ff, 0xc008, 0x21, 0 - .dw 0xb640, 0xc008, 0xb67f, 0xc008, 0x21, 0 - .dw 0xb6c0, 0xc008, 0xb6ff, 0xc008, 0x21, 0 - .dw 0xb740, 0xc008, 0xb77f, 0xc008, 0x21, 0 - .dw 0xb7c0, 0xc008, 0xb7ff, 0xc008, 0x21, 0 - .dw 0xb840, 0xc008, 0xb87f, 0xc008, 0x21, 0 - .dw 0xb8c0, 0xc008, 0xb8ff, 0xc008, 0x21, 0 - .dw 0xb940, 0xc008, 0xb97f, 0xc008, 0x21, 0 - .dw 0xb9c0, 0xc008, 0xdfff, 0xc008, 0x21, 0 - .dw 0xe040, 0xc008, 0xe07f, 0xc008, 0x21, 0 - .dw 0xe0c0, 0xc008, 0xe0ff, 0xc008, 0x21, 0 - .dw 0xe140, 0xc008, 0xe17f, 0xc008, 0x21, 0 - .dw 0xe1c0, 0xc008, 0xe1ff, 0xc008, 0x21, 0 - .dw 0xe240, 0xc008, 0xe27f, 0xc008, 0x21, 0 - .dw 0xe2c0, 0xc008, 0xe2ff, 0xc008, 0x21, 0 - .dw 0xe340, 0xc008, 0xe37f, 0xc008, 0x21, 0 - .dw 0xe3c0, 0xc008, 0xe3ff, 0xc008, 0x21, 0 - .dw 0xe440, 0xc008, 0xe47f, 0xc008, 0x21, 0 - .dw 0xe4c0, 0xc008, 0xe4ff, 0xc008, 0x21, 0 - .dw 0xe540, 0xc008, 0xe57f, 0xc008, 0x21, 0 - .dw 0xe5c0, 0xc008, 0xe5ff, 0xc008, 0x21, 0 - .dw 0xe640, 0xc008, 0xe67f, 0xc008, 0x21, 0 - .dw 0xe6c0, 0xc008, 0xe6ff, 0xc008, 0x21, 0 - .dw 0xe740, 0xc008, 0xe77f, 0xc008, 0x21, 0 - .dw 0xe7c0, 0xc008, 0xe7ff, 0xc008, 0x21, 0 - .dw 0xe840, 0xc008, 0xe87f, 0xc008, 0x21, 0 - .dw 0xe8c0, 0xc008, 0xe8ff, 0xc008, 0x21, 0 - .dw 0xe940, 0xc008, 0xe97f, 0xc008, 0x21, 0 - .dw 0xe9c0, 0xc008, 0xe9ff, 0xc008, 0x21, 0 - .dw 0xea40, 0xc008, 0xea7f, 0xc008, 0x21, 0 - .dw 0xeac0, 0xc008, 0xeaff, 0xc008, 0x21, 0 - .dw 0xeb40, 0xc008, 0xeb7f, 0xc008, 0x21, 0 - .dw 0xebc0, 0xc008, 0xebff, 0xc008, 0x21, 0 - .dw 0xec40, 0xc008, 0xec7f, 0xc008, 0x21, 0 - .dw 0xecc0, 0xc008, 0xecff, 0xc008, 0x21, 0 - .dw 0xed40, 0xc008, 0xed7f, 0xc008, 0x21, 0 - .dw 0xedc0, 0xc008, 0xedff, 0xc008, 0x21, 0 - .dw 0xee40, 0xc008, 0xee7f, 0xc008, 0x21, 0 - .dw 0xeec0, 0xc008, 0xeeff, 0xc008, 0x21, 0 - .dw 0xef40, 0xc008, 0xef7f, 0xc008, 0x21, 0 - .dw 0xefc0, 0xc008, 0xefff, 0xc008, 0x21, 0 - .dw 0xf040, 0xc008, 0xf07f, 0xc008, 0x21, 0 - .dw 0xf0c0, 0xc008, 0xf0ff, 0xc008, 0x21, 0 - .dw 0xf140, 0xc008, 0xf17f, 0xc008, 0x21, 0 - .dw 0xf1c0, 0xc008, 0xf1ff, 0xc008, 0x21, 0 - .dw 0xf240, 0xc008, 0xf27f, 0xc008, 0x21, 0 - .dw 0xf2c0, 0xc008, 0xf2ff, 0xc008, 0x21, 0 - .dw 0xf340, 0xc008, 0xf37f, 0xc008, 0x21, 0 - .dw 0xf3c0, 0xc008, 0xf3ff, 0xc008, 0x21, 0 - .dw 0xf440, 0xc008, 0xf47f, 0xc008, 0x21, 0 - .dw 0xf4c0, 0xc008, 0xf4ff, 0xc008, 0x21, 0 - .dw 0xf540, 0xc008, 0xf57f, 0xc008, 0x21, 0 - .dw 0xf5c0, 0xc008, 0xf5ff, 0xc008, 0x21, 0 - .dw 0xf640, 0xc008, 0xf67f, 0xc008, 0x21, 0 - .dw 0xf6c0, 0xc008, 0xf6ff, 0xc008, 0x21, 0 - .dw 0xf740, 0xc008, 0xf77f, 0xc008, 0x21, 0 - .dw 0xf7c0, 0xc008, 0xf7ff, 0xc008, 0x21, 0 - .dw 0xf840, 0xc008, 0xf87f, 0xc008, 0x21, 0 - .dw 0xf8c0, 0xc008, 0xf8ff, 0xc008, 0x21, 0 - .dw 0xf940, 0xc008, 0xf97f, 0xc008, 0x21, 0 - .dw 0xf9c0, 0xc008, 0x1fff, 0xc009, 0x21, 0 - .dw 0x2040, 0xc009, 0x207f, 0xc009, 0x21, 0 - .dw 0x20c0, 0xc009, 0x20ff, 0xc009, 0x21, 0 - .dw 0x2140, 0xc009, 0x217f, 0xc009, 0x21, 0 - .dw 0x21c0, 0xc009, 0x21ff, 0xc009, 0x21, 0 - .dw 0x2240, 0xc009, 0x227f, 0xc009, 0x21, 0 - .dw 0x22c0, 0xc009, 0x22ff, 0xc009, 0x21, 0 - .dw 0x2340, 0xc009, 0x237f, 0xc009, 0x21, 0 - .dw 0x23c0, 0xc009, 0x23ff, 0xc009, 0x21, 0 - .dw 0x2440, 0xc009, 0x247f, 0xc009, 0x21, 0 - .dw 0x24c0, 0xc009, 0x24ff, 0xc009, 0x21, 0 - .dw 0x2540, 0xc009, 0x257f, 0xc009, 0x21, 0 - .dw 0x25c0, 0xc009, 0x25ff, 0xc009, 0x21, 0 - .dw 0x2640, 0xc009, 0x267f, 0xc009, 0x21, 0 - .dw 0x26c0, 0xc009, 0x26ff, 0xc009, 0x21, 0 - .dw 0x2740, 0xc009, 0x277f, 0xc009, 0x21, 0 - .dw 0x27c0, 0xc009, 0x27ff, 0xc009, 0x21, 0 - .dw 0x2840, 0xc009, 0x287f, 0xc009, 0x21, 0 - .dw 0x28c0, 0xc009, 0x28ff, 0xc009, 0x21, 0 - .dw 0x2940, 0xc009, 0x297f, 0xc009, 0x21, 0 - .dw 0x29c0, 0xc009, 0x29ff, 0xc009, 0x21, 0 - .dw 0x2a40, 0xc009, 0x2a7f, 0xc009, 0x21, 0 - .dw 0x2ac0, 0xc009, 0x2aff, 0xc009, 0x21, 0 - .dw 0x2b40, 0xc009, 0x2b7f, 0xc009, 0x21, 0 - .dw 0x2bc0, 0xc009, 0x2bff, 0xc009, 0x21, 0 - .dw 0x2c40, 0xc009, 0x2c7f, 0xc009, 0x21, 0 - .dw 0x2cc0, 0xc009, 0x2cff, 0xc009, 0x21, 0 - .dw 0x2d40, 0xc009, 0x2d7f, 0xc009, 0x21, 0 - .dw 0x2dc0, 0xc009, 0x2dff, 0xc009, 0x21, 0 - .dw 0x2e40, 0xc009, 0x2e7f, 0xc009, 0x21, 0 - .dw 0x2ec0, 0xc009, 0x2eff, 0xc009, 0x21, 0 - .dw 0x2f40, 0xc009, 0x2f7f, 0xc009, 0x21, 0 - .dw 0x2fc0, 0xc009, 0x2fff, 0xc009, 0x21, 0 - .dw 0x3040, 0xc009, 0x307f, 0xc009, 0x21, 0 - .dw 0x30c0, 0xc009, 0x30ff, 0xc009, 0x21, 0 - .dw 0x3140, 0xc009, 0x317f, 0xc009, 0x21, 0 - .dw 0x31c0, 0xc009, 0x31ff, 0xc009, 0x21, 0 - .dw 0x3240, 0xc009, 0x327f, 0xc009, 0x21, 0 - .dw 0x32c0, 0xc009, 0x32ff, 0xc009, 0x21, 0 - .dw 0x3340, 0xc009, 0x337f, 0xc009, 0x21, 0 - .dw 0x33c0, 0xc009, 0x33ff, 0xc009, 0x21, 0 - .dw 0x3440, 0xc009, 0x347f, 0xc009, 0x21, 0 - .dw 0x34c0, 0xc009, 0x34ff, 0xc009, 0x21, 0 - .dw 0x3540, 0xc009, 0x357f, 0xc009, 0x21, 0 - .dw 0x35c0, 0xc009, 0x35ff, 0xc009, 0x21, 0 - .dw 0x3640, 0xc009, 0x367f, 0xc009, 0x21, 0 - .dw 0x36c0, 0xc009, 0x36ff, 0xc009, 0x21, 0 - .dw 0x3740, 0xc009, 0x377f, 0xc009, 0x21, 0 - .dw 0x37c0, 0xc009, 0x37ff, 0xc009, 0x21, 0 - .dw 0x3840, 0xc009, 0x387f, 0xc009, 0x21, 0 - .dw 0x38c0, 0xc009, 0x38ff, 0xc009, 0x21, 0 - .dw 0x3940, 0xc009, 0x397f, 0xc009, 0x21, 0 - .dw 0x39c0, 0xc009, 0x5fff, 0xc009, 0x21, 0 - .dw 0x6040, 0xc009, 0x607f, 0xc009, 0x21, 0 - .dw 0x60c0, 0xc009, 0x60ff, 0xc009, 0x21, 0 - .dw 0x6140, 0xc009, 0x617f, 0xc009, 0x21, 0 - .dw 0x61c0, 0xc009, 0x61ff, 0xc009, 0x21, 0 - .dw 0x6240, 0xc009, 0x627f, 0xc009, 0x21, 0 - .dw 0x62c0, 0xc009, 0x62ff, 0xc009, 0x21, 0 - .dw 0x6340, 0xc009, 0x637f, 0xc009, 0x21, 0 - .dw 0x63c0, 0xc009, 0x63ff, 0xc009, 0x21, 0 - .dw 0x6440, 0xc009, 0x647f, 0xc009, 0x21, 0 - .dw 0x64c0, 0xc009, 0x64ff, 0xc009, 0x21, 0 - .dw 0x6540, 0xc009, 0x657f, 0xc009, 0x21, 0 - .dw 0x65c0, 0xc009, 0x65ff, 0xc009, 0x21, 0 - .dw 0x6640, 0xc009, 0x667f, 0xc009, 0x21, 0 - .dw 0x66c0, 0xc009, 0x66ff, 0xc009, 0x21, 0 - .dw 0x6740, 0xc009, 0x677f, 0xc009, 0x21, 0 - .dw 0x67c0, 0xc009, 0x67ff, 0xc009, 0x21, 0 - .dw 0x6840, 0xc009, 0x687f, 0xc009, 0x21, 0 - .dw 0x68c0, 0xc009, 0x68ff, 0xc009, 0x21, 0 - .dw 0x6940, 0xc009, 0x697f, 0xc009, 0x21, 0 - .dw 0x69c0, 0xc009, 0x69ff, 0xc009, 0x21, 0 - .dw 0x6a40, 0xc009, 0x6a7f, 0xc009, 0x21, 0 - .dw 0x6ac0, 0xc009, 0x6aff, 0xc009, 0x21, 0 - .dw 0x6b40, 0xc009, 0x6b7f, 0xc009, 0x21, 0 - .dw 0x6bc0, 0xc009, 0x6bff, 0xc009, 0x21, 0 - .dw 0x6c40, 0xc009, 0x6c7f, 0xc009, 0x21, 0 - .dw 0x6cc0, 0xc009, 0x6cff, 0xc009, 0x21, 0 - .dw 0x6d40, 0xc009, 0x6d7f, 0xc009, 0x21, 0 - .dw 0x6dc0, 0xc009, 0x6dff, 0xc009, 0x21, 0 - .dw 0x6e40, 0xc009, 0x6e7f, 0xc009, 0x21, 0 - .dw 0x6ec0, 0xc009, 0x6eff, 0xc009, 0x21, 0 - .dw 0x6f40, 0xc009, 0x6f7f, 0xc009, 0x21, 0 - .dw 0x6fc0, 0xc009, 0x6fff, 0xc009, 0x21, 0 - .dw 0x7040, 0xc009, 0x707f, 0xc009, 0x21, 0 - .dw 0x70c0, 0xc009, 0x70ff, 0xc009, 0x21, 0 - .dw 0x7140, 0xc009, 0x717f, 0xc009, 0x21, 0 - .dw 0x71c0, 0xc009, 0x71ff, 0xc009, 0x21, 0 - .dw 0x7240, 0xc009, 0x727f, 0xc009, 0x21, 0 - .dw 0x72c0, 0xc009, 0x72ff, 0xc009, 0x21, 0 - .dw 0x7340, 0xc009, 0x737f, 0xc009, 0x21, 0 - .dw 0x73c0, 0xc009, 0x73ff, 0xc009, 0x21, 0 - .dw 0x7440, 0xc009, 0x747f, 0xc009, 0x21, 0 - .dw 0x74c0, 0xc009, 0x74ff, 0xc009, 0x21, 0 - .dw 0x7540, 0xc009, 0x757f, 0xc009, 0x21, 0 - .dw 0x75c0, 0xc009, 0x75ff, 0xc009, 0x21, 0 - .dw 0x7640, 0xc009, 0x767f, 0xc009, 0x21, 0 - .dw 0x76c0, 0xc009, 0x76ff, 0xc009, 0x21, 0 - .dw 0x7740, 0xc009, 0x777f, 0xc009, 0x21, 0 - .dw 0x77c0, 0xc009, 0x77ff, 0xc009, 0x21, 0 - .dw 0x7840, 0xc009, 0x787f, 0xc009, 0x21, 0 - .dw 0x78c0, 0xc009, 0x78ff, 0xc009, 0x21, 0 - .dw 0x7940, 0xc009, 0x797f, 0xc009, 0x21, 0 - .dw 0x79c0, 0xc009, 0x9fff, 0xc009, 0x21, 0 - .dw 0xa040, 0xc009, 0xa07f, 0xc009, 0x21, 0 - .dw 0xa0c0, 0xc009, 0xa0ff, 0xc009, 0x21, 0 - .dw 0xa140, 0xc009, 0xa17f, 0xc009, 0x21, 0 - .dw 0xa1c0, 0xc009, 0xa1ff, 0xc009, 0x21, 0 - .dw 0xa240, 0xc009, 0xa27f, 0xc009, 0x21, 0 - .dw 0xa2c0, 0xc009, 0xa2ff, 0xc009, 0x21, 0 - .dw 0xa340, 0xc009, 0xa37f, 0xc009, 0x21, 0 - .dw 0xa3c0, 0xc009, 0xa3ff, 0xc009, 0x21, 0 - .dw 0xa440, 0xc009, 0xa47f, 0xc009, 0x21, 0 - .dw 0xa4c0, 0xc009, 0xa4ff, 0xc009, 0x21, 0 - .dw 0xa540, 0xc009, 0xa57f, 0xc009, 0x21, 0 - .dw 0xa5c0, 0xc009, 0xa5ff, 0xc009, 0x21, 0 - .dw 0xa640, 0xc009, 0xa67f, 0xc009, 0x21, 0 - .dw 0xa6c0, 0xc009, 0xa6ff, 0xc009, 0x21, 0 - .dw 0xa740, 0xc009, 0xa77f, 0xc009, 0x21, 0 - .dw 0xa7c0, 0xc009, 0xa7ff, 0xc009, 0x21, 0 - .dw 0xa840, 0xc009, 0xa87f, 0xc009, 0x21, 0 - .dw 0xa8c0, 0xc009, 0xa8ff, 0xc009, 0x21, 0 - .dw 0xa940, 0xc009, 0xa97f, 0xc009, 0x21, 0 - .dw 0xa9c0, 0xc009, 0xa9ff, 0xc009, 0x21, 0 - .dw 0xaa40, 0xc009, 0xaa7f, 0xc009, 0x21, 0 - .dw 0xaac0, 0xc009, 0xaaff, 0xc009, 0x21, 0 - .dw 0xab40, 0xc009, 0xab7f, 0xc009, 0x21, 0 - .dw 0xabc0, 0xc009, 0xabff, 0xc009, 0x21, 0 - .dw 0xac40, 0xc009, 0xac7f, 0xc009, 0x21, 0 - .dw 0xacc0, 0xc009, 0xacff, 0xc009, 0x21, 0 - .dw 0xad40, 0xc009, 0xad7f, 0xc009, 0x21, 0 - .dw 0xadc0, 0xc009, 0xadff, 0xc009, 0x21, 0 - .dw 0xae40, 0xc009, 0xae7f, 0xc009, 0x21, 0 - .dw 0xaec0, 0xc009, 0xaeff, 0xc009, 0x21, 0 - .dw 0xaf40, 0xc009, 0xaf7f, 0xc009, 0x21, 0 - .dw 0xafc0, 0xc009, 0xafff, 0xc009, 0x21, 0 - .dw 0xb040, 0xc009, 0xb07f, 0xc009, 0x21, 0 - .dw 0xb0c0, 0xc009, 0xb0ff, 0xc009, 0x21, 0 - .dw 0xb140, 0xc009, 0xb17f, 0xc009, 0x21, 0 - .dw 0xb1c0, 0xc009, 0xb1ff, 0xc009, 0x21, 0 - .dw 0xb240, 0xc009, 0xb27f, 0xc009, 0x21, 0 - .dw 0xb2c0, 0xc009, 0xb2ff, 0xc009, 0x21, 0 - .dw 0xb340, 0xc009, 0xb37f, 0xc009, 0x21, 0 - .dw 0xb3c0, 0xc009, 0xb3ff, 0xc009, 0x21, 0 - .dw 0xb440, 0xc009, 0xb47f, 0xc009, 0x21, 0 - .dw 0xb4c0, 0xc009, 0xb4ff, 0xc009, 0x21, 0 - .dw 0xb540, 0xc009, 0xb57f, 0xc009, 0x21, 0 - .dw 0xb5c0, 0xc009, 0xb5ff, 0xc009, 0x21, 0 - .dw 0xb640, 0xc009, 0xb67f, 0xc009, 0x21, 0 - .dw 0xb6c0, 0xc009, 0xb6ff, 0xc009, 0x21, 0 - .dw 0xb740, 0xc009, 0xb77f, 0xc009, 0x21, 0 - .dw 0xb7c0, 0xc009, 0xb7ff, 0xc009, 0x21, 0 - .dw 0xb840, 0xc009, 0xb87f, 0xc009, 0x21, 0 - .dw 0xb8c0, 0xc009, 0xb8ff, 0xc009, 0x21, 0 - .dw 0xb940, 0xc009, 0xb97f, 0xc009, 0x21, 0 - .dw 0xb9c0, 0xc009, 0xdfff, 0xc009, 0x21, 0 - .dw 0xe040, 0xc009, 0xe07f, 0xc009, 0x21, 0 - .dw 0xe0c0, 0xc009, 0xe0ff, 0xc009, 0x21, 0 - .dw 0xe140, 0xc009, 0xe17f, 0xc009, 0x21, 0 - .dw 0xe1c0, 0xc009, 0xe1ff, 0xc009, 0x21, 0 - .dw 0xe240, 0xc009, 0xe27f, 0xc009, 0x21, 0 - .dw 0xe2c0, 0xc009, 0xe2ff, 0xc009, 0x21, 0 - .dw 0xe340, 0xc009, 0xe37f, 0xc009, 0x21, 0 - .dw 0xe3c0, 0xc009, 0xe3ff, 0xc009, 0x21, 0 - .dw 0xe440, 0xc009, 0xe47f, 0xc009, 0x21, 0 - .dw 0xe4c0, 0xc009, 0xe4ff, 0xc009, 0x21, 0 - .dw 0xe540, 0xc009, 0xe57f, 0xc009, 0x21, 0 - .dw 0xe5c0, 0xc009, 0xe5ff, 0xc009, 0x21, 0 - .dw 0xe640, 0xc009, 0xe67f, 0xc009, 0x21, 0 - .dw 0xe6c0, 0xc009, 0xe6ff, 0xc009, 0x21, 0 - .dw 0xe740, 0xc009, 0xe77f, 0xc009, 0x21, 0 - .dw 0xe7c0, 0xc009, 0xe7ff, 0xc009, 0x21, 0 - .dw 0xe840, 0xc009, 0xe87f, 0xc009, 0x21, 0 - .dw 0xe8c0, 0xc009, 0xe8ff, 0xc009, 0x21, 0 - .dw 0xe940, 0xc009, 0xe97f, 0xc009, 0x21, 0 - .dw 0xe9c0, 0xc009, 0xe9ff, 0xc009, 0x21, 0 - .dw 0xea40, 0xc009, 0xea7f, 0xc009, 0x21, 0 - .dw 0xeac0, 0xc009, 0xeaff, 0xc009, 0x21, 0 - .dw 0xeb40, 0xc009, 0xeb7f, 0xc009, 0x21, 0 - .dw 0xebc0, 0xc009, 0xebff, 0xc009, 0x21, 0 - .dw 0xec40, 0xc009, 0xec7f, 0xc009, 0x21, 0 - .dw 0xecc0, 0xc009, 0xecff, 0xc009, 0x21, 0 - .dw 0xed40, 0xc009, 0xed7f, 0xc009, 0x21, 0 - .dw 0xedc0, 0xc009, 0xedff, 0xc009, 0x21, 0 - .dw 0xee40, 0xc009, 0xee7f, 0xc009, 0x21, 0 - .dw 0xeec0, 0xc009, 0xeeff, 0xc009, 0x21, 0 - .dw 0xef40, 0xc009, 0xef7f, 0xc009, 0x21, 0 - .dw 0xefc0, 0xc009, 0xefff, 0xc009, 0x21, 0 - .dw 0xf040, 0xc009, 0xf07f, 0xc009, 0x21, 0 - .dw 0xf0c0, 0xc009, 0xf0ff, 0xc009, 0x21, 0 - .dw 0xf140, 0xc009, 0xf17f, 0xc009, 0x21, 0 - .dw 0xf1c0, 0xc009, 0xf1ff, 0xc009, 0x21, 0 - .dw 0xf240, 0xc009, 0xf27f, 0xc009, 0x21, 0 - .dw 0xf2c0, 0xc009, 0xf2ff, 0xc009, 0x21, 0 - .dw 0xf340, 0xc009, 0xf37f, 0xc009, 0x21, 0 - .dw 0xf3c0, 0xc009, 0xf3ff, 0xc009, 0x21, 0 - .dw 0xf440, 0xc009, 0xf47f, 0xc009, 0x21, 0 - .dw 0xf4c0, 0xc009, 0xf4ff, 0xc009, 0x21, 0 - .dw 0xf540, 0xc009, 0xf57f, 0xc009, 0x21, 0 - .dw 0xf5c0, 0xc009, 0xf5ff, 0xc009, 0x21, 0 - .dw 0xf640, 0xc009, 0xf67f, 0xc009, 0x21, 0 - .dw 0xf6c0, 0xc009, 0xf6ff, 0xc009, 0x21, 0 - .dw 0xf740, 0xc009, 0xf77f, 0xc009, 0x21, 0 - .dw 0xf7c0, 0xc009, 0xf7ff, 0xc009, 0x21, 0 - .dw 0xf840, 0xc009, 0xf87f, 0xc009, 0x21, 0 - .dw 0xf8c0, 0xc009, 0xf8ff, 0xc009, 0x21, 0 - .dw 0xf940, 0xc009, 0xf97f, 0xc009, 0x21, 0 - .dw 0xf9c0, 0xc009, 0x1fff, 0xc00a, 0x21, 0 - .dw 0x2040, 0xc00a, 0x207f, 0xc00a, 0x21, 0 - .dw 0x20c0, 0xc00a, 0x20ff, 0xc00a, 0x21, 0 - .dw 0x2140, 0xc00a, 0x217f, 0xc00a, 0x21, 0 - .dw 0x21c0, 0xc00a, 0x21ff, 0xc00a, 0x21, 0 - .dw 0x2240, 0xc00a, 0x227f, 0xc00a, 0x21, 0 - .dw 0x22c0, 0xc00a, 0x22ff, 0xc00a, 0x21, 0 - .dw 0x2340, 0xc00a, 0x237f, 0xc00a, 0x21, 0 - .dw 0x23c0, 0xc00a, 0x23ff, 0xc00a, 0x21, 0 - .dw 0x2440, 0xc00a, 0x247f, 0xc00a, 0x21, 0 - .dw 0x24c0, 0xc00a, 0x24ff, 0xc00a, 0x21, 0 - .dw 0x2540, 0xc00a, 0x257f, 0xc00a, 0x21, 0 - .dw 0x25c0, 0xc00a, 0x25ff, 0xc00a, 0x21, 0 - .dw 0x2640, 0xc00a, 0x267f, 0xc00a, 0x21, 0 - .dw 0x26c0, 0xc00a, 0x26ff, 0xc00a, 0x21, 0 - .dw 0x2740, 0xc00a, 0x277f, 0xc00a, 0x21, 0 - .dw 0x27c0, 0xc00a, 0x27ff, 0xc00a, 0x21, 0 - .dw 0x2840, 0xc00a, 0x287f, 0xc00a, 0x21, 0 - .dw 0x28c0, 0xc00a, 0x28ff, 0xc00a, 0x21, 0 - .dw 0x2940, 0xc00a, 0x297f, 0xc00a, 0x21, 0 - .dw 0x29c0, 0xc00a, 0x29ff, 0xc00a, 0x21, 0 - .dw 0x2a40, 0xc00a, 0x2a7f, 0xc00a, 0x21, 0 - .dw 0x2ac0, 0xc00a, 0x2aff, 0xc00a, 0x21, 0 - .dw 0x2b40, 0xc00a, 0x2b7f, 0xc00a, 0x21, 0 - .dw 0x2bc0, 0xc00a, 0x2bff, 0xc00a, 0x21, 0 - .dw 0x2c40, 0xc00a, 0x2c7f, 0xc00a, 0x21, 0 - .dw 0x2cc0, 0xc00a, 0x2cff, 0xc00a, 0x21, 0 - .dw 0x2d40, 0xc00a, 0x2d7f, 0xc00a, 0x21, 0 - .dw 0x2dc0, 0xc00a, 0x2dff, 0xc00a, 0x21, 0 - .dw 0x2e40, 0xc00a, 0x2e7f, 0xc00a, 0x21, 0 - .dw 0x2ec0, 0xc00a, 0x2eff, 0xc00a, 0x21, 0 - .dw 0x2f40, 0xc00a, 0x2f7f, 0xc00a, 0x21, 0 - .dw 0x2fc0, 0xc00a, 0x2fff, 0xc00a, 0x21, 0 - .dw 0x3040, 0xc00a, 0x307f, 0xc00a, 0x21, 0 - .dw 0x30c0, 0xc00a, 0x30ff, 0xc00a, 0x21, 0 - .dw 0x3140, 0xc00a, 0x317f, 0xc00a, 0x21, 0 - .dw 0x31c0, 0xc00a, 0x31ff, 0xc00a, 0x21, 0 - .dw 0x3240, 0xc00a, 0x327f, 0xc00a, 0x21, 0 - .dw 0x32c0, 0xc00a, 0x32ff, 0xc00a, 0x21, 0 - .dw 0x3340, 0xc00a, 0x337f, 0xc00a, 0x21, 0 - .dw 0x33c0, 0xc00a, 0x33ff, 0xc00a, 0x21, 0 - .dw 0x3440, 0xc00a, 0x347f, 0xc00a, 0x21, 0 - .dw 0x34c0, 0xc00a, 0x34ff, 0xc00a, 0x21, 0 - .dw 0x3540, 0xc00a, 0x357f, 0xc00a, 0x21, 0 - .dw 0x35c0, 0xc00a, 0x35ff, 0xc00a, 0x21, 0 - .dw 0x3640, 0xc00a, 0x367f, 0xc00a, 0x21, 0 - .dw 0x36c0, 0xc00a, 0x36ff, 0xc00a, 0x21, 0 - .dw 0x3740, 0xc00a, 0x377f, 0xc00a, 0x21, 0 - .dw 0x37c0, 0xc00a, 0x37ff, 0xc00a, 0x21, 0 - .dw 0x3840, 0xc00a, 0x387f, 0xc00a, 0x21, 0 - .dw 0x38c0, 0xc00a, 0x38ff, 0xc00a, 0x21, 0 - .dw 0x3940, 0xc00a, 0x397f, 0xc00a, 0x21, 0 - .dw 0x39c0, 0xc00a, 0x5fff, 0xc00a, 0x21, 0 - .dw 0x6040, 0xc00a, 0x607f, 0xc00a, 0x21, 0 - .dw 0x60c0, 0xc00a, 0x60ff, 0xc00a, 0x21, 0 - .dw 0x6140, 0xc00a, 0x617f, 0xc00a, 0x21, 0 - .dw 0x61c0, 0xc00a, 0x61ff, 0xc00a, 0x21, 0 - .dw 0x6240, 0xc00a, 0x627f, 0xc00a, 0x21, 0 - .dw 0x62c0, 0xc00a, 0x62ff, 0xc00a, 0x21, 0 - .dw 0x6340, 0xc00a, 0x637f, 0xc00a, 0x21, 0 - .dw 0x63c0, 0xc00a, 0x63ff, 0xc00a, 0x21, 0 - .dw 0x6440, 0xc00a, 0x647f, 0xc00a, 0x21, 0 - .dw 0x64c0, 0xc00a, 0x64ff, 0xc00a, 0x21, 0 - .dw 0x6540, 0xc00a, 0x657f, 0xc00a, 0x21, 0 - .dw 0x65c0, 0xc00a, 0x65ff, 0xc00a, 0x21, 0 - .dw 0x6640, 0xc00a, 0x667f, 0xc00a, 0x21, 0 - .dw 0x66c0, 0xc00a, 0x66ff, 0xc00a, 0x21, 0 - .dw 0x6740, 0xc00a, 0x677f, 0xc00a, 0x21, 0 - .dw 0x67c0, 0xc00a, 0x67ff, 0xc00a, 0x21, 0 - .dw 0x6840, 0xc00a, 0x687f, 0xc00a, 0x21, 0 - .dw 0x68c0, 0xc00a, 0x68ff, 0xc00a, 0x21, 0 - .dw 0x6940, 0xc00a, 0x697f, 0xc00a, 0x21, 0 - .dw 0x69c0, 0xc00a, 0x69ff, 0xc00a, 0x21, 0 - .dw 0x6a40, 0xc00a, 0x6a7f, 0xc00a, 0x21, 0 - .dw 0x6ac0, 0xc00a, 0x6aff, 0xc00a, 0x21, 0 - .dw 0x6b40, 0xc00a, 0x6b7f, 0xc00a, 0x21, 0 - .dw 0x6bc0, 0xc00a, 0x6bff, 0xc00a, 0x21, 0 - .dw 0x6c40, 0xc00a, 0x6c7f, 0xc00a, 0x21, 0 - .dw 0x6cc0, 0xc00a, 0x6cff, 0xc00a, 0x21, 0 - .dw 0x6d40, 0xc00a, 0x6d7f, 0xc00a, 0x21, 0 - .dw 0x6dc0, 0xc00a, 0x6dff, 0xc00a, 0x21, 0 - .dw 0x6e40, 0xc00a, 0x6e7f, 0xc00a, 0x21, 0 - .dw 0x6ec0, 0xc00a, 0x6eff, 0xc00a, 0x21, 0 - .dw 0x6f40, 0xc00a, 0x6f7f, 0xc00a, 0x21, 0 - .dw 0x6fc0, 0xc00a, 0x6fff, 0xc00a, 0x21, 0 - .dw 0x7040, 0xc00a, 0x707f, 0xc00a, 0x21, 0 - .dw 0x70c0, 0xc00a, 0x70ff, 0xc00a, 0x21, 0 - .dw 0x7140, 0xc00a, 0x717f, 0xc00a, 0x21, 0 - .dw 0x71c0, 0xc00a, 0x71ff, 0xc00a, 0x21, 0 - .dw 0x7240, 0xc00a, 0x727f, 0xc00a, 0x21, 0 - .dw 0x72c0, 0xc00a, 0x72ff, 0xc00a, 0x21, 0 - .dw 0x7340, 0xc00a, 0x737f, 0xc00a, 0x21, 0 - .dw 0x73c0, 0xc00a, 0x73ff, 0xc00a, 0x21, 0 - .dw 0x7440, 0xc00a, 0x747f, 0xc00a, 0x21, 0 - .dw 0x74c0, 0xc00a, 0x74ff, 0xc00a, 0x21, 0 - .dw 0x7540, 0xc00a, 0x757f, 0xc00a, 0x21, 0 - .dw 0x75c0, 0xc00a, 0x75ff, 0xc00a, 0x21, 0 - .dw 0x7640, 0xc00a, 0x767f, 0xc00a, 0x21, 0 - .dw 0x76c0, 0xc00a, 0x76ff, 0xc00a, 0x21, 0 - .dw 0x7740, 0xc00a, 0x777f, 0xc00a, 0x21, 0 - .dw 0x77c0, 0xc00a, 0x77ff, 0xc00a, 0x21, 0 - .dw 0x7840, 0xc00a, 0x787f, 0xc00a, 0x21, 0 - .dw 0x78c0, 0xc00a, 0x78ff, 0xc00a, 0x21, 0 - .dw 0x7940, 0xc00a, 0x797f, 0xc00a, 0x21, 0 - .dw 0x79c0, 0xc00a, 0x9fff, 0xc00a, 0x21, 0 - .dw 0xa040, 0xc00a, 0xa07f, 0xc00a, 0x21, 0 - .dw 0xa0c0, 0xc00a, 0xa0ff, 0xc00a, 0x21, 0 - .dw 0xa140, 0xc00a, 0xa17f, 0xc00a, 0x21, 0 - .dw 0xa1c0, 0xc00a, 0xa1ff, 0xc00a, 0x21, 0 - .dw 0xa240, 0xc00a, 0xa27f, 0xc00a, 0x21, 0 - .dw 0xa2c0, 0xc00a, 0xa2ff, 0xc00a, 0x21, 0 - .dw 0xa340, 0xc00a, 0xa37f, 0xc00a, 0x21, 0 - .dw 0xa3c0, 0xc00a, 0xa3ff, 0xc00a, 0x21, 0 - .dw 0xa440, 0xc00a, 0xa47f, 0xc00a, 0x21, 0 - .dw 0xa4c0, 0xc00a, 0xa4ff, 0xc00a, 0x21, 0 - .dw 0xa540, 0xc00a, 0xa57f, 0xc00a, 0x21, 0 - .dw 0xa5c0, 0xc00a, 0xa5ff, 0xc00a, 0x21, 0 - .dw 0xa640, 0xc00a, 0xa67f, 0xc00a, 0x21, 0 - .dw 0xa6c0, 0xc00a, 0xa6ff, 0xc00a, 0x21, 0 - .dw 0xa740, 0xc00a, 0xa77f, 0xc00a, 0x21, 0 - .dw 0xa7c0, 0xc00a, 0xa7ff, 0xc00a, 0x21, 0 - .dw 0xa840, 0xc00a, 0xa87f, 0xc00a, 0x21, 0 - .dw 0xa8c0, 0xc00a, 0xa8ff, 0xc00a, 0x21, 0 - .dw 0xa940, 0xc00a, 0xa97f, 0xc00a, 0x21, 0 - .dw 0xa9c0, 0xc00a, 0xa9ff, 0xc00a, 0x21, 0 - .dw 0xaa40, 0xc00a, 0xaa7f, 0xc00a, 0x21, 0 - .dw 0xaac0, 0xc00a, 0xaaff, 0xc00a, 0x21, 0 - .dw 0xab40, 0xc00a, 0xab7f, 0xc00a, 0x21, 0 - .dw 0xabc0, 0xc00a, 0xabff, 0xc00a, 0x21, 0 - .dw 0xac40, 0xc00a, 0xac7f, 0xc00a, 0x21, 0 - .dw 0xacc0, 0xc00a, 0xacff, 0xc00a, 0x21, 0 - .dw 0xad40, 0xc00a, 0xad7f, 0xc00a, 0x21, 0 - .dw 0xadc0, 0xc00a, 0xadff, 0xc00a, 0x21, 0 - .dw 0xae40, 0xc00a, 0xae7f, 0xc00a, 0x21, 0 - .dw 0xaec0, 0xc00a, 0xaeff, 0xc00a, 0x21, 0 - .dw 0xaf40, 0xc00a, 0xaf7f, 0xc00a, 0x21, 0 - .dw 0xafc0, 0xc00a, 0xafff, 0xc00a, 0x21, 0 - .dw 0xb040, 0xc00a, 0xb07f, 0xc00a, 0x21, 0 - .dw 0xb0c0, 0xc00a, 0xb0ff, 0xc00a, 0x21, 0 - .dw 0xb140, 0xc00a, 0xb17f, 0xc00a, 0x21, 0 - .dw 0xb1c0, 0xc00a, 0xb1ff, 0xc00a, 0x21, 0 - .dw 0xb240, 0xc00a, 0xb27f, 0xc00a, 0x21, 0 - .dw 0xb2c0, 0xc00a, 0xb2ff, 0xc00a, 0x21, 0 - .dw 0xb340, 0xc00a, 0xb37f, 0xc00a, 0x21, 0 - .dw 0xb3c0, 0xc00a, 0xb3ff, 0xc00a, 0x21, 0 - .dw 0xb440, 0xc00a, 0xb47f, 0xc00a, 0x21, 0 - .dw 0xb4c0, 0xc00a, 0xb4ff, 0xc00a, 0x21, 0 - .dw 0xb540, 0xc00a, 0xb57f, 0xc00a, 0x21, 0 - .dw 0xb5c0, 0xc00a, 0xb5ff, 0xc00a, 0x21, 0 - .dw 0xb640, 0xc00a, 0xb67f, 0xc00a, 0x21, 0 - .dw 0xb6c0, 0xc00a, 0xb6ff, 0xc00a, 0x21, 0 - .dw 0xb740, 0xc00a, 0xb77f, 0xc00a, 0x21, 0 - .dw 0xb7c0, 0xc00a, 0xb7ff, 0xc00a, 0x21, 0 - .dw 0xb840, 0xc00a, 0xb87f, 0xc00a, 0x21, 0 - .dw 0xb8c0, 0xc00a, 0xb8ff, 0xc00a, 0x21, 0 - .dw 0xb940, 0xc00a, 0xb97f, 0xc00a, 0x21, 0 - .dw 0xb9c0, 0xc00a, 0xdfff, 0xc00a, 0x21, 0 - .dw 0xe040, 0xc00a, 0xe07f, 0xc00a, 0x21, 0 - .dw 0xe0c0, 0xc00a, 0xe0ff, 0xc00a, 0x21, 0 - .dw 0xe140, 0xc00a, 0xe17f, 0xc00a, 0x21, 0 - .dw 0xe1c0, 0xc00a, 0xe1ff, 0xc00a, 0x21, 0 - .dw 0xe240, 0xc00a, 0xe27f, 0xc00a, 0x21, 0 - .dw 0xe2c0, 0xc00a, 0xe2ff, 0xc00a, 0x21, 0 - .dw 0xe340, 0xc00a, 0xe37f, 0xc00a, 0x21, 0 - .dw 0xe3c0, 0xc00a, 0xe3ff, 0xc00a, 0x21, 0 - .dw 0xe440, 0xc00a, 0xe47f, 0xc00a, 0x21, 0 - .dw 0xe4c0, 0xc00a, 0xe4ff, 0xc00a, 0x21, 0 - .dw 0xe540, 0xc00a, 0xe57f, 0xc00a, 0x21, 0 - .dw 0xe5c0, 0xc00a, 0xe5ff, 0xc00a, 0x21, 0 - .dw 0xe640, 0xc00a, 0xe67f, 0xc00a, 0x21, 0 - .dw 0xe6c0, 0xc00a, 0xe6ff, 0xc00a, 0x21, 0 - .dw 0xe740, 0xc00a, 0xe77f, 0xc00a, 0x21, 0 - .dw 0xe7c0, 0xc00a, 0xe7ff, 0xc00a, 0x21, 0 - .dw 0xe840, 0xc00a, 0xe87f, 0xc00a, 0x21, 0 - .dw 0xe8c0, 0xc00a, 0xe8ff, 0xc00a, 0x21, 0 - .dw 0xe940, 0xc00a, 0xe97f, 0xc00a, 0x21, 0 - .dw 0xe9c0, 0xc00a, 0xe9ff, 0xc00a, 0x21, 0 - .dw 0xea40, 0xc00a, 0xea7f, 0xc00a, 0x21, 0 - .dw 0xeac0, 0xc00a, 0xeaff, 0xc00a, 0x21, 0 - .dw 0xeb40, 0xc00a, 0xeb7f, 0xc00a, 0x21, 0 - .dw 0xebc0, 0xc00a, 0xebff, 0xc00a, 0x21, 0 - .dw 0xec40, 0xc00a, 0xec7f, 0xc00a, 0x21, 0 - .dw 0xecc0, 0xc00a, 0xecff, 0xc00a, 0x21, 0 - .dw 0xed40, 0xc00a, 0xed7f, 0xc00a, 0x21, 0 - .dw 0xedc0, 0xc00a, 0xedff, 0xc00a, 0x21, 0 - .dw 0xee40, 0xc00a, 0xee7f, 0xc00a, 0x21, 0 - .dw 0xeec0, 0xc00a, 0xeeff, 0xc00a, 0x21, 0 - .dw 0xef40, 0xc00a, 0xef7f, 0xc00a, 0x21, 0 - .dw 0xefc0, 0xc00a, 0xefff, 0xc00a, 0x21, 0 - .dw 0xf040, 0xc00a, 0xf07f, 0xc00a, 0x21, 0 - .dw 0xf0c0, 0xc00a, 0xf0ff, 0xc00a, 0x21, 0 - .dw 0xf140, 0xc00a, 0xf17f, 0xc00a, 0x21, 0 - .dw 0xf1c0, 0xc00a, 0xf1ff, 0xc00a, 0x21, 0 - .dw 0xf240, 0xc00a, 0xf27f, 0xc00a, 0x21, 0 - .dw 0xf2c0, 0xc00a, 0xf2ff, 0xc00a, 0x21, 0 - .dw 0xf340, 0xc00a, 0xf37f, 0xc00a, 0x21, 0 - .dw 0xf3c0, 0xc00a, 0xf3ff, 0xc00a, 0x21, 0 - .dw 0xf440, 0xc00a, 0xf47f, 0xc00a, 0x21, 0 - .dw 0xf4c0, 0xc00a, 0xf4ff, 0xc00a, 0x21, 0 - .dw 0xf540, 0xc00a, 0xf57f, 0xc00a, 0x21, 0 - .dw 0xf5c0, 0xc00a, 0xf5ff, 0xc00a, 0x21, 0 - .dw 0xf640, 0xc00a, 0xf67f, 0xc00a, 0x21, 0 - .dw 0xf6c0, 0xc00a, 0xf6ff, 0xc00a, 0x21, 0 - .dw 0xf740, 0xc00a, 0xf77f, 0xc00a, 0x21, 0 - .dw 0xf7c0, 0xc00a, 0xf7ff, 0xc00a, 0x21, 0 - .dw 0xf840, 0xc00a, 0xf87f, 0xc00a, 0x21, 0 - .dw 0xf8c0, 0xc00a, 0xf8ff, 0xc00a, 0x21, 0 - .dw 0xf940, 0xc00a, 0xf97f, 0xc00a, 0x21, 0 - .dw 0xf9c0, 0xc00a, 0x1fff, 0xc00b, 0x21, 0 - .dw 0x2040, 0xc00b, 0x207f, 0xc00b, 0x21, 0 - .dw 0x20c0, 0xc00b, 0x20ff, 0xc00b, 0x21, 0 - .dw 0x2140, 0xc00b, 0x217f, 0xc00b, 0x21, 0 - .dw 0x21c0, 0xc00b, 0x21ff, 0xc00b, 0x21, 0 - .dw 0x2240, 0xc00b, 0x227f, 0xc00b, 0x21, 0 - .dw 0x22c0, 0xc00b, 0x22ff, 0xc00b, 0x21, 0 - .dw 0x2340, 0xc00b, 0x237f, 0xc00b, 0x21, 0 - .dw 0x23c0, 0xc00b, 0x23ff, 0xc00b, 0x21, 0 - .dw 0x2440, 0xc00b, 0x247f, 0xc00b, 0x21, 0 - .dw 0x24c0, 0xc00b, 0x24ff, 0xc00b, 0x21, 0 - .dw 0x2540, 0xc00b, 0x257f, 0xc00b, 0x21, 0 - .dw 0x25c0, 0xc00b, 0x25ff, 0xc00b, 0x21, 0 - .dw 0x2640, 0xc00b, 0x267f, 0xc00b, 0x21, 0 - .dw 0x26c0, 0xc00b, 0x26ff, 0xc00b, 0x21, 0 - .dw 0x2740, 0xc00b, 0x277f, 0xc00b, 0x21, 0 - .dw 0x27c0, 0xc00b, 0x27ff, 0xc00b, 0x21, 0 - .dw 0x2840, 0xc00b, 0x287f, 0xc00b, 0x21, 0 - .dw 0x28c0, 0xc00b, 0x28ff, 0xc00b, 0x21, 0 - .dw 0x2940, 0xc00b, 0x297f, 0xc00b, 0x21, 0 - .dw 0x29c0, 0xc00b, 0x29ff, 0xc00b, 0x21, 0 - .dw 0x2a40, 0xc00b, 0x2a7f, 0xc00b, 0x21, 0 - .dw 0x2ac0, 0xc00b, 0x2aff, 0xc00b, 0x21, 0 - .dw 0x2b40, 0xc00b, 0x2b7f, 0xc00b, 0x21, 0 - .dw 0x2bc0, 0xc00b, 0x2bff, 0xc00b, 0x21, 0 - .dw 0x2c40, 0xc00b, 0x2c7f, 0xc00b, 0x21, 0 - .dw 0x2cc0, 0xc00b, 0x2cff, 0xc00b, 0x21, 0 - .dw 0x2d40, 0xc00b, 0x2d7f, 0xc00b, 0x21, 0 - .dw 0x2dc0, 0xc00b, 0x2dff, 0xc00b, 0x21, 0 - .dw 0x2e40, 0xc00b, 0x2e7f, 0xc00b, 0x21, 0 - .dw 0x2ec0, 0xc00b, 0x2eff, 0xc00b, 0x21, 0 - .dw 0x2f40, 0xc00b, 0x2f7f, 0xc00b, 0x21, 0 - .dw 0x2fc0, 0xc00b, 0x2fff, 0xc00b, 0x21, 0 - .dw 0x3040, 0xc00b, 0x307f, 0xc00b, 0x21, 0 - .dw 0x30c0, 0xc00b, 0x30ff, 0xc00b, 0x21, 0 - .dw 0x3140, 0xc00b, 0x317f, 0xc00b, 0x21, 0 - .dw 0x31c0, 0xc00b, 0x31ff, 0xc00b, 0x21, 0 - .dw 0x3240, 0xc00b, 0x327f, 0xc00b, 0x21, 0 - .dw 0x32c0, 0xc00b, 0x32ff, 0xc00b, 0x21, 0 - .dw 0x3340, 0xc00b, 0x337f, 0xc00b, 0x21, 0 - .dw 0x33c0, 0xc00b, 0x33ff, 0xc00b, 0x21, 0 - .dw 0x3440, 0xc00b, 0x347f, 0xc00b, 0x21, 0 - .dw 0x34c0, 0xc00b, 0x34ff, 0xc00b, 0x21, 0 - .dw 0x3540, 0xc00b, 0x357f, 0xc00b, 0x21, 0 - .dw 0x35c0, 0xc00b, 0x35ff, 0xc00b, 0x21, 0 - .dw 0x3640, 0xc00b, 0x367f, 0xc00b, 0x21, 0 - .dw 0x36c0, 0xc00b, 0x36ff, 0xc00b, 0x21, 0 - .dw 0x3740, 0xc00b, 0x377f, 0xc00b, 0x21, 0 - .dw 0x37c0, 0xc00b, 0x37ff, 0xc00b, 0x21, 0 - .dw 0x3840, 0xc00b, 0x387f, 0xc00b, 0x21, 0 - .dw 0x38c0, 0xc00b, 0x38ff, 0xc00b, 0x21, 0 - .dw 0x3940, 0xc00b, 0x397f, 0xc00b, 0x21, 0 - .dw 0x39c0, 0xc00b, 0xffff, 0xc00b, 0x21, 0 - .dw 0x0040, 0xc00c, 0x007f, 0xc00c, 0x21, 0 - .dw 0x00c0, 0xc00c, 0x00ff, 0xc00c, 0x21, 0 - .dw 0x0140, 0xc00c, 0x017f, 0xc00c, 0x21, 0 - .dw 0x01c0, 0xc00c, 0x01ff, 0xc00c, 0x21, 0 - .dw 0x0240, 0xc00c, 0x027f, 0xc00c, 0x21, 0 - .dw 0x02c0, 0xc00c, 0x02ff, 0xc00c, 0x21, 0 - .dw 0x0340, 0xc00c, 0x037f, 0xc00c, 0x21, 0 - .dw 0x03c0, 0xc00c, 0x03ff, 0xc00c, 0x21, 0 - .dw 0x0440, 0xc00c, 0x047f, 0xc00c, 0x21, 0 - .dw 0x04c0, 0xc00c, 0x04ff, 0xc00c, 0x21, 0 - .dw 0x0540, 0xc00c, 0x057f, 0xc00c, 0x21, 0 - .dw 0x05c0, 0xc00c, 0x05ff, 0xc00c, 0x21, 0 - .dw 0x0640, 0xc00c, 0x067f, 0xc00c, 0x21, 0 - .dw 0x06c0, 0xc00c, 0x06ff, 0xc00c, 0x21, 0 - .dw 0x0740, 0xc00c, 0x077f, 0xc00c, 0x21, 0 - .dw 0x07c0, 0xc00c, 0x07ff, 0xc00c, 0x21, 0 - .dw 0x0840, 0xc00c, 0x087f, 0xc00c, 0x21, 0 - .dw 0x08c0, 0xc00c, 0x08ff, 0xc00c, 0x21, 0 - .dw 0x0940, 0xc00c, 0x097f, 0xc00c, 0x21, 0 - .dw 0x09c0, 0xc00c, 0x09ff, 0xc00c, 0x21, 0 - .dw 0x0a40, 0xc00c, 0x0a7f, 0xc00c, 0x21, 0 - .dw 0x0ac0, 0xc00c, 0x0aff, 0xc00c, 0x21, 0 - .dw 0x0b40, 0xc00c, 0x0b7f, 0xc00c, 0x21, 0 - .dw 0x0bc0, 0xc00c, 0x0bff, 0xc00c, 0x21, 0 - .dw 0x0c40, 0xc00c, 0x0c7f, 0xc00c, 0x21, 0 - .dw 0x0cc0, 0xc00c, 0x0cff, 0xc00c, 0x21, 0 - .dw 0x0d40, 0xc00c, 0x0d7f, 0xc00c, 0x21, 0 - .dw 0x0dc0, 0xc00c, 0x0dff, 0xc00c, 0x21, 0 - .dw 0x0e40, 0xc00c, 0x0e7f, 0xc00c, 0x21, 0 - .dw 0x0ec0, 0xc00c, 0x0eff, 0xc00c, 0x21, 0 - .dw 0x0f40, 0xc00c, 0x0f7f, 0xc00c, 0x21, 0 - .dw 0x0fc0, 0xc00c, 0x0fff, 0xc00c, 0x21, 0 - .dw 0x1040, 0xc00c, 0x107f, 0xc00c, 0x21, 0 - .dw 0x10c0, 0xc00c, 0x10ff, 0xc00c, 0x21, 0 - .dw 0x1140, 0xc00c, 0x117f, 0xc00c, 0x21, 0 - .dw 0x11c0, 0xc00c, 0x11ff, 0xc00c, 0x21, 0 - .dw 0x1240, 0xc00c, 0x127f, 0xc00c, 0x21, 0 - .dw 0x12c0, 0xc00c, 0x12ff, 0xc00c, 0x21, 0 - .dw 0x1340, 0xc00c, 0x137f, 0xc00c, 0x21, 0 - .dw 0x13c0, 0xc00c, 0x13ff, 0xc00c, 0x21, 0 - .dw 0x1440, 0xc00c, 0x147f, 0xc00c, 0x21, 0 - .dw 0x14c0, 0xc00c, 0x14ff, 0xc00c, 0x21, 0 - .dw 0x1540, 0xc00c, 0x157f, 0xc00c, 0x21, 0 - .dw 0x15c0, 0xc00c, 0x15ff, 0xc00c, 0x21, 0 - .dw 0x1640, 0xc00c, 0x167f, 0xc00c, 0x21, 0 - .dw 0x16c0, 0xc00c, 0x16ff, 0xc00c, 0x21, 0 - .dw 0x1740, 0xc00c, 0x177f, 0xc00c, 0x21, 0 - .dw 0x17c0, 0xc00c, 0x17ff, 0xc00c, 0x21, 0 - .dw 0x1840, 0xc00c, 0x187f, 0xc00c, 0x21, 0 - .dw 0x18c0, 0xc00c, 0x18ff, 0xc00c, 0x21, 0 - .dw 0x1940, 0xc00c, 0x197f, 0xc00c, 0x21, 0 - .dw 0x19c0, 0xc00c, 0x1fff, 0xc00c, 0x21, 0 - .dw 0x2040, 0xc00c, 0x207f, 0xc00c, 0x21, 0 - .dw 0x20c0, 0xc00c, 0x20ff, 0xc00c, 0x21, 0 - .dw 0x2140, 0xc00c, 0x217f, 0xc00c, 0x21, 0 - .dw 0x21c0, 0xc00c, 0x21ff, 0xc00c, 0x21, 0 - .dw 0x2240, 0xc00c, 0x227f, 0xc00c, 0x21, 0 - .dw 0x22c0, 0xc00c, 0x22ff, 0xc00c, 0x21, 0 - .dw 0x2340, 0xc00c, 0x237f, 0xc00c, 0x21, 0 - .dw 0x23c0, 0xc00c, 0x23ff, 0xc00c, 0x21, 0 - .dw 0x2440, 0xc00c, 0x247f, 0xc00c, 0x21, 0 - .dw 0x24c0, 0xc00c, 0x24ff, 0xc00c, 0x21, 0 - .dw 0x2540, 0xc00c, 0x257f, 0xc00c, 0x21, 0 - .dw 0x25c0, 0xc00c, 0x25ff, 0xc00c, 0x21, 0 - .dw 0x2640, 0xc00c, 0x267f, 0xc00c, 0x21, 0 - .dw 0x26c0, 0xc00c, 0x26ff, 0xc00c, 0x21, 0 - .dw 0x2740, 0xc00c, 0x277f, 0xc00c, 0x21, 0 - .dw 0x27c0, 0xc00c, 0x27ff, 0xc00c, 0x21, 0 - .dw 0x2840, 0xc00c, 0x287f, 0xc00c, 0x21, 0 - .dw 0x28c0, 0xc00c, 0x28ff, 0xc00c, 0x21, 0 - .dw 0x2940, 0xc00c, 0x297f, 0xc00c, 0x21, 0 - .dw 0x29c0, 0xc00c, 0x29ff, 0xc00c, 0x21, 0 - .dw 0x2a40, 0xc00c, 0x2a7f, 0xc00c, 0x21, 0 - .dw 0x2ac0, 0xc00c, 0x2aff, 0xc00c, 0x21, 0 - .dw 0x2b40, 0xc00c, 0x2b7f, 0xc00c, 0x21, 0 - .dw 0x2bc0, 0xc00c, 0x2bff, 0xc00c, 0x21, 0 - .dw 0x2c40, 0xc00c, 0x2c7f, 0xc00c, 0x21, 0 - .dw 0x2cc0, 0xc00c, 0x2cff, 0xc00c, 0x21, 0 - .dw 0x2d40, 0xc00c, 0x2d7f, 0xc00c, 0x21, 0 - .dw 0x2dc0, 0xc00c, 0x2dff, 0xc00c, 0x21, 0 - .dw 0x2e40, 0xc00c, 0x2e7f, 0xc00c, 0x21, 0 - .dw 0x2ec0, 0xc00c, 0x2eff, 0xc00c, 0x21, 0 - .dw 0x2f40, 0xc00c, 0x2f7f, 0xc00c, 0x21, 0 - .dw 0x2fc0, 0xc00c, 0x2fff, 0xc00c, 0x21, 0 - .dw 0x3040, 0xc00c, 0x307f, 0xc00c, 0x21, 0 - .dw 0x30c0, 0xc00c, 0x30ff, 0xc00c, 0x21, 0 - .dw 0x3140, 0xc00c, 0x317f, 0xc00c, 0x21, 0 - .dw 0x31c0, 0xc00c, 0x31ff, 0xc00c, 0x21, 0 - .dw 0x3240, 0xc00c, 0x327f, 0xc00c, 0x21, 0 - .dw 0x32c0, 0xc00c, 0x32ff, 0xc00c, 0x21, 0 - .dw 0x3340, 0xc00c, 0x337f, 0xc00c, 0x21, 0 - .dw 0x33c0, 0xc00c, 0x33ff, 0xc00c, 0x21, 0 - .dw 0x3440, 0xc00c, 0x347f, 0xc00c, 0x21, 0 - .dw 0x34c0, 0xc00c, 0x34ff, 0xc00c, 0x21, 0 - .dw 0x3540, 0xc00c, 0x357f, 0xc00c, 0x21, 0 - .dw 0x35c0, 0xc00c, 0x35ff, 0xc00c, 0x21, 0 - .dw 0x3640, 0xc00c, 0x367f, 0xc00c, 0x21, 0 - .dw 0x36c0, 0xc00c, 0x36ff, 0xc00c, 0x21, 0 - .dw 0x3740, 0xc00c, 0x377f, 0xc00c, 0x21, 0 - .dw 0x37c0, 0xc00c, 0x37ff, 0xc00c, 0x21, 0 - .dw 0x3840, 0xc00c, 0x387f, 0xc00c, 0x21, 0 - .dw 0x38c0, 0xc00c, 0x38ff, 0xc00c, 0x21, 0 - .dw 0x3940, 0xc00c, 0x397f, 0xc00c, 0x21, 0 - .dw 0x39c0, 0xc00c, 0x3fff, 0xc00c, 0x21, 0 - .dw 0x4040, 0xc00c, 0x407f, 0xc00c, 0x21, 0 - .dw 0x40c0, 0xc00c, 0x40ff, 0xc00c, 0x21, 0 - .dw 0x4140, 0xc00c, 0x417f, 0xc00c, 0x21, 0 - .dw 0x41c0, 0xc00c, 0x41ff, 0xc00c, 0x21, 0 - .dw 0x4240, 0xc00c, 0x427f, 0xc00c, 0x21, 0 - .dw 0x42c0, 0xc00c, 0x42ff, 0xc00c, 0x21, 0 - .dw 0x4340, 0xc00c, 0x437f, 0xc00c, 0x21, 0 - .dw 0x43c0, 0xc00c, 0x43ff, 0xc00c, 0x21, 0 - .dw 0x4440, 0xc00c, 0x447f, 0xc00c, 0x21, 0 - .dw 0x44c0, 0xc00c, 0x44ff, 0xc00c, 0x21, 0 - .dw 0x4540, 0xc00c, 0x457f, 0xc00c, 0x21, 0 - .dw 0x45c0, 0xc00c, 0x45ff, 0xc00c, 0x21, 0 - .dw 0x4640, 0xc00c, 0x467f, 0xc00c, 0x21, 0 - .dw 0x46c0, 0xc00c, 0x46ff, 0xc00c, 0x21, 0 - .dw 0x4740, 0xc00c, 0x477f, 0xc00c, 0x21, 0 - .dw 0x47c0, 0xc00c, 0x47ff, 0xc00c, 0x21, 0 - .dw 0x4840, 0xc00c, 0x487f, 0xc00c, 0x21, 0 - .dw 0x48c0, 0xc00c, 0x48ff, 0xc00c, 0x21, 0 - .dw 0x4940, 0xc00c, 0x497f, 0xc00c, 0x21, 0 - .dw 0x49c0, 0xc00c, 0x49ff, 0xc00c, 0x21, 0 - .dw 0x4a40, 0xc00c, 0x4a7f, 0xc00c, 0x21, 0 - .dw 0x4ac0, 0xc00c, 0x4aff, 0xc00c, 0x21, 0 - .dw 0x4b40, 0xc00c, 0x4b7f, 0xc00c, 0x21, 0 - .dw 0x4bc0, 0xc00c, 0x4bff, 0xc00c, 0x21, 0 - .dw 0x4c40, 0xc00c, 0x4c7f, 0xc00c, 0x21, 0 - .dw 0x4cc0, 0xc00c, 0x4cff, 0xc00c, 0x21, 0 - .dw 0x4d40, 0xc00c, 0x4d7f, 0xc00c, 0x21, 0 - .dw 0x4dc0, 0xc00c, 0x4dff, 0xc00c, 0x21, 0 - .dw 0x4e40, 0xc00c, 0x4e7f, 0xc00c, 0x21, 0 - .dw 0x4ec0, 0xc00c, 0x4eff, 0xc00c, 0x21, 0 - .dw 0x4f40, 0xc00c, 0x4f7f, 0xc00c, 0x21, 0 - .dw 0x4fc0, 0xc00c, 0x4fff, 0xc00c, 0x21, 0 - .dw 0x5040, 0xc00c, 0x507f, 0xc00c, 0x21, 0 - .dw 0x50c0, 0xc00c, 0x50ff, 0xc00c, 0x21, 0 - .dw 0x5140, 0xc00c, 0x517f, 0xc00c, 0x21, 0 - .dw 0x51c0, 0xc00c, 0x51ff, 0xc00c, 0x21, 0 - .dw 0x5240, 0xc00c, 0x527f, 0xc00c, 0x21, 0 - .dw 0x52c0, 0xc00c, 0x52ff, 0xc00c, 0x21, 0 - .dw 0x5340, 0xc00c, 0x537f, 0xc00c, 0x21, 0 - .dw 0x53c0, 0xc00c, 0x53ff, 0xc00c, 0x21, 0 - .dw 0x5440, 0xc00c, 0x547f, 0xc00c, 0x21, 0 - .dw 0x54c0, 0xc00c, 0x54ff, 0xc00c, 0x21, 0 - .dw 0x5540, 0xc00c, 0x557f, 0xc00c, 0x21, 0 - .dw 0x55c0, 0xc00c, 0x55ff, 0xc00c, 0x21, 0 - .dw 0x5640, 0xc00c, 0x567f, 0xc00c, 0x21, 0 - .dw 0x56c0, 0xc00c, 0x56ff, 0xc00c, 0x21, 0 - .dw 0x5740, 0xc00c, 0x577f, 0xc00c, 0x21, 0 - .dw 0x57c0, 0xc00c, 0x57ff, 0xc00c, 0x21, 0 - .dw 0x5840, 0xc00c, 0x587f, 0xc00c, 0x21, 0 - .dw 0x58c0, 0xc00c, 0x58ff, 0xc00c, 0x21, 0 - .dw 0x5940, 0xc00c, 0x597f, 0xc00c, 0x21, 0 - .dw 0x59c0, 0xc00c, 0x5fff, 0xc00c, 0x21, 0 - .dw 0x6040, 0xc00c, 0x607f, 0xc00c, 0x21, 0 - .dw 0x60c0, 0xc00c, 0x60ff, 0xc00c, 0x21, 0 - .dw 0x6140, 0xc00c, 0x617f, 0xc00c, 0x21, 0 - .dw 0x61c0, 0xc00c, 0x61ff, 0xc00c, 0x21, 0 - .dw 0x6240, 0xc00c, 0x627f, 0xc00c, 0x21, 0 - .dw 0x62c0, 0xc00c, 0x62ff, 0xc00c, 0x21, 0 - .dw 0x6340, 0xc00c, 0x637f, 0xc00c, 0x21, 0 - .dw 0x63c0, 0xc00c, 0x63ff, 0xc00c, 0x21, 0 - .dw 0x6440, 0xc00c, 0x647f, 0xc00c, 0x21, 0 - .dw 0x64c0, 0xc00c, 0x64ff, 0xc00c, 0x21, 0 - .dw 0x6540, 0xc00c, 0x657f, 0xc00c, 0x21, 0 - .dw 0x65c0, 0xc00c, 0x65ff, 0xc00c, 0x21, 0 - .dw 0x6640, 0xc00c, 0x667f, 0xc00c, 0x21, 0 - .dw 0x66c0, 0xc00c, 0x66ff, 0xc00c, 0x21, 0 - .dw 0x6740, 0xc00c, 0x677f, 0xc00c, 0x21, 0 - .dw 0x67c0, 0xc00c, 0x67ff, 0xc00c, 0x21, 0 - .dw 0x6840, 0xc00c, 0x687f, 0xc00c, 0x21, 0 - .dw 0x68c0, 0xc00c, 0x68ff, 0xc00c, 0x21, 0 - .dw 0x6940, 0xc00c, 0x697f, 0xc00c, 0x21, 0 - .dw 0x69c0, 0xc00c, 0x69ff, 0xc00c, 0x21, 0 - .dw 0x6a40, 0xc00c, 0x6a7f, 0xc00c, 0x21, 0 - .dw 0x6ac0, 0xc00c, 0x6aff, 0xc00c, 0x21, 0 - .dw 0x6b40, 0xc00c, 0x6b7f, 0xc00c, 0x21, 0 - .dw 0x6bc0, 0xc00c, 0x6bff, 0xc00c, 0x21, 0 - .dw 0x6c40, 0xc00c, 0x6c7f, 0xc00c, 0x21, 0 - .dw 0x6cc0, 0xc00c, 0x6cff, 0xc00c, 0x21, 0 - .dw 0x6d40, 0xc00c, 0x6d7f, 0xc00c, 0x21, 0 - .dw 0x6dc0, 0xc00c, 0x6dff, 0xc00c, 0x21, 0 - .dw 0x6e40, 0xc00c, 0x6e7f, 0xc00c, 0x21, 0 - .dw 0x6ec0, 0xc00c, 0x6eff, 0xc00c, 0x21, 0 - .dw 0x6f40, 0xc00c, 0x6f7f, 0xc00c, 0x21, 0 - .dw 0x6fc0, 0xc00c, 0x6fff, 0xc00c, 0x21, 0 - .dw 0x7040, 0xc00c, 0x707f, 0xc00c, 0x21, 0 - .dw 0x70c0, 0xc00c, 0x70ff, 0xc00c, 0x21, 0 - .dw 0x7140, 0xc00c, 0x717f, 0xc00c, 0x21, 0 - .dw 0x71c0, 0xc00c, 0x71ff, 0xc00c, 0x21, 0 - .dw 0x7240, 0xc00c, 0x727f, 0xc00c, 0x21, 0 - .dw 0x72c0, 0xc00c, 0x72ff, 0xc00c, 0x21, 0 - .dw 0x7340, 0xc00c, 0x737f, 0xc00c, 0x21, 0 - .dw 0x73c0, 0xc00c, 0x73ff, 0xc00c, 0x21, 0 - .dw 0x7440, 0xc00c, 0x747f, 0xc00c, 0x21, 0 - .dw 0x74c0, 0xc00c, 0x74ff, 0xc00c, 0x21, 0 - .dw 0x7540, 0xc00c, 0x757f, 0xc00c, 0x21, 0 - .dw 0x75c0, 0xc00c, 0x75ff, 0xc00c, 0x21, 0 - .dw 0x7640, 0xc00c, 0x767f, 0xc00c, 0x21, 0 - .dw 0x76c0, 0xc00c, 0x76ff, 0xc00c, 0x21, 0 - .dw 0x7740, 0xc00c, 0x777f, 0xc00c, 0x21, 0 - .dw 0x77c0, 0xc00c, 0x77ff, 0xc00c, 0x21, 0 - .dw 0x7840, 0xc00c, 0x787f, 0xc00c, 0x21, 0 - .dw 0x78c0, 0xc00c, 0x78ff, 0xc00c, 0x21, 0 - .dw 0x7940, 0xc00c, 0x797f, 0xc00c, 0x21, 0 - .dw 0x79c0, 0xc00c, 0x7fff, 0xc00c, 0x21, 0 - .dw 0x8040, 0xc00c, 0x807f, 0xc00c, 0x21, 0 - .dw 0x80c0, 0xc00c, 0x80ff, 0xc00c, 0x21, 0 - .dw 0x8140, 0xc00c, 0x817f, 0xc00c, 0x21, 0 - .dw 0x81c0, 0xc00c, 0x81ff, 0xc00c, 0x21, 0 - .dw 0x8240, 0xc00c, 0x827f, 0xc00c, 0x21, 0 - .dw 0x82c0, 0xc00c, 0x82ff, 0xc00c, 0x21, 0 - .dw 0x8340, 0xc00c, 0x837f, 0xc00c, 0x21, 0 - .dw 0x83c0, 0xc00c, 0x83ff, 0xc00c, 0x21, 0 - .dw 0x8440, 0xc00c, 0x847f, 0xc00c, 0x21, 0 - .dw 0x84c0, 0xc00c, 0x84ff, 0xc00c, 0x21, 0 - .dw 0x8540, 0xc00c, 0x857f, 0xc00c, 0x21, 0 - .dw 0x85c0, 0xc00c, 0x85ff, 0xc00c, 0x21, 0 - .dw 0x8640, 0xc00c, 0x867f, 0xc00c, 0x21, 0 - .dw 0x86c0, 0xc00c, 0x86ff, 0xc00c, 0x21, 0 - .dw 0x8740, 0xc00c, 0x877f, 0xc00c, 0x21, 0 - .dw 0x87c0, 0xc00c, 0x87ff, 0xc00c, 0x21, 0 - .dw 0x8840, 0xc00c, 0x887f, 0xc00c, 0x21, 0 - .dw 0x88c0, 0xc00c, 0x88ff, 0xc00c, 0x21, 0 - .dw 0x8940, 0xc00c, 0x897f, 0xc00c, 0x21, 0 - .dw 0x89c0, 0xc00c, 0x89ff, 0xc00c, 0x21, 0 - .dw 0x8a40, 0xc00c, 0x8a7f, 0xc00c, 0x21, 0 - .dw 0x8ac0, 0xc00c, 0x8aff, 0xc00c, 0x21, 0 - .dw 0x8b40, 0xc00c, 0x8b7f, 0xc00c, 0x21, 0 - .dw 0x8bc0, 0xc00c, 0x8bff, 0xc00c, 0x21, 0 - .dw 0x8c40, 0xc00c, 0x8c7f, 0xc00c, 0x21, 0 - .dw 0x8cc0, 0xc00c, 0x8cff, 0xc00c, 0x21, 0 - .dw 0x8d40, 0xc00c, 0x8d7f, 0xc00c, 0x21, 0 - .dw 0x8dc0, 0xc00c, 0x8dff, 0xc00c, 0x21, 0 - .dw 0x8e40, 0xc00c, 0x8e7f, 0xc00c, 0x21, 0 - .dw 0x8ec0, 0xc00c, 0x8eff, 0xc00c, 0x21, 0 - .dw 0x8f40, 0xc00c, 0x8f7f, 0xc00c, 0x21, 0 - .dw 0x8fc0, 0xc00c, 0x8fff, 0xc00c, 0x21, 0 - .dw 0x9040, 0xc00c, 0x907f, 0xc00c, 0x21, 0 - .dw 0x90c0, 0xc00c, 0x90ff, 0xc00c, 0x21, 0 - .dw 0x9140, 0xc00c, 0x917f, 0xc00c, 0x21, 0 - .dw 0x91c0, 0xc00c, 0x91ff, 0xc00c, 0x21, 0 - .dw 0x9240, 0xc00c, 0x927f, 0xc00c, 0x21, 0 - .dw 0x92c0, 0xc00c, 0x92ff, 0xc00c, 0x21, 0 - .dw 0x9340, 0xc00c, 0x937f, 0xc00c, 0x21, 0 - .dw 0x93c0, 0xc00c, 0x93ff, 0xc00c, 0x21, 0 - .dw 0x9440, 0xc00c, 0x947f, 0xc00c, 0x21, 0 - .dw 0x94c0, 0xc00c, 0x94ff, 0xc00c, 0x21, 0 - .dw 0x9540, 0xc00c, 0x957f, 0xc00c, 0x21, 0 - .dw 0x95c0, 0xc00c, 0x95ff, 0xc00c, 0x21, 0 - .dw 0x9640, 0xc00c, 0x967f, 0xc00c, 0x21, 0 - .dw 0x96c0, 0xc00c, 0x96ff, 0xc00c, 0x21, 0 - .dw 0x9740, 0xc00c, 0x977f, 0xc00c, 0x21, 0 - .dw 0x97c0, 0xc00c, 0x97ff, 0xc00c, 0x21, 0 - .dw 0x9840, 0xc00c, 0x987f, 0xc00c, 0x21, 0 - .dw 0x98c0, 0xc00c, 0x98ff, 0xc00c, 0x21, 0 - .dw 0x9940, 0xc00c, 0x997f, 0xc00c, 0x21, 0 - .dw 0x99c0, 0xc00c, 0x9fff, 0xc00c, 0x21, 0 - .dw 0xa040, 0xc00c, 0xa07f, 0xc00c, 0x21, 0 - .dw 0xa0c0, 0xc00c, 0xa0ff, 0xc00c, 0x21, 0 - .dw 0xa140, 0xc00c, 0xa17f, 0xc00c, 0x21, 0 - .dw 0xa1c0, 0xc00c, 0xa1ff, 0xc00c, 0x21, 0 - .dw 0xa240, 0xc00c, 0xa27f, 0xc00c, 0x21, 0 - .dw 0xa2c0, 0xc00c, 0xa2ff, 0xc00c, 0x21, 0 - .dw 0xa340, 0xc00c, 0xa37f, 0xc00c, 0x21, 0 - .dw 0xa3c0, 0xc00c, 0xa3ff, 0xc00c, 0x21, 0 - .dw 0xa440, 0xc00c, 0xa47f, 0xc00c, 0x21, 0 - .dw 0xa4c0, 0xc00c, 0xa4ff, 0xc00c, 0x21, 0 - .dw 0xa540, 0xc00c, 0xa57f, 0xc00c, 0x21, 0 - .dw 0xa5c0, 0xc00c, 0xa5ff, 0xc00c, 0x21, 0 - .dw 0xa640, 0xc00c, 0xa67f, 0xc00c, 0x21, 0 - .dw 0xa6c0, 0xc00c, 0xa6ff, 0xc00c, 0x21, 0 - .dw 0xa740, 0xc00c, 0xa77f, 0xc00c, 0x21, 0 - .dw 0xa7c0, 0xc00c, 0xa7ff, 0xc00c, 0x21, 0 - .dw 0xa840, 0xc00c, 0xa87f, 0xc00c, 0x21, 0 - .dw 0xa8c0, 0xc00c, 0xa8ff, 0xc00c, 0x21, 0 - .dw 0xa940, 0xc00c, 0xa97f, 0xc00c, 0x21, 0 - .dw 0xa9c0, 0xc00c, 0xa9ff, 0xc00c, 0x21, 0 - .dw 0xaa40, 0xc00c, 0xaa7f, 0xc00c, 0x21, 0 - .dw 0xaac0, 0xc00c, 0xaaff, 0xc00c, 0x21, 0 - .dw 0xab40, 0xc00c, 0xab7f, 0xc00c, 0x21, 0 - .dw 0xabc0, 0xc00c, 0xabff, 0xc00c, 0x21, 0 - .dw 0xac40, 0xc00c, 0xac7f, 0xc00c, 0x21, 0 - .dw 0xacc0, 0xc00c, 0xacff, 0xc00c, 0x21, 0 - .dw 0xad40, 0xc00c, 0xad7f, 0xc00c, 0x21, 0 - .dw 0xadc0, 0xc00c, 0xadff, 0xc00c, 0x21, 0 - .dw 0xae40, 0xc00c, 0xae7f, 0xc00c, 0x21, 0 - .dw 0xaec0, 0xc00c, 0xaeff, 0xc00c, 0x21, 0 - .dw 0xaf40, 0xc00c, 0xaf7f, 0xc00c, 0x21, 0 - .dw 0xafc0, 0xc00c, 0xafff, 0xc00c, 0x21, 0 - .dw 0xb040, 0xc00c, 0xb07f, 0xc00c, 0x21, 0 - .dw 0xb0c0, 0xc00c, 0xb0ff, 0xc00c, 0x21, 0 - .dw 0xb140, 0xc00c, 0xb17f, 0xc00c, 0x21, 0 - .dw 0xb1c0, 0xc00c, 0xb1ff, 0xc00c, 0x21, 0 - .dw 0xb240, 0xc00c, 0xb27f, 0xc00c, 0x21, 0 - .dw 0xb2c0, 0xc00c, 0xb2ff, 0xc00c, 0x21, 0 - .dw 0xb340, 0xc00c, 0xb37f, 0xc00c, 0x21, 0 - .dw 0xb3c0, 0xc00c, 0xb3ff, 0xc00c, 0x21, 0 - .dw 0xb440, 0xc00c, 0xb47f, 0xc00c, 0x21, 0 - .dw 0xb4c0, 0xc00c, 0xb4ff, 0xc00c, 0x21, 0 - .dw 0xb540, 0xc00c, 0xb57f, 0xc00c, 0x21, 0 - .dw 0xb5c0, 0xc00c, 0xb5ff, 0xc00c, 0x21, 0 - .dw 0xb640, 0xc00c, 0xb67f, 0xc00c, 0x21, 0 - .dw 0xb6c0, 0xc00c, 0xb6ff, 0xc00c, 0x21, 0 - .dw 0xb740, 0xc00c, 0xb77f, 0xc00c, 0x21, 0 - .dw 0xb7c0, 0xc00c, 0xb7ff, 0xc00c, 0x21, 0 - .dw 0xb840, 0xc00c, 0xb87f, 0xc00c, 0x21, 0 - .dw 0xb8c0, 0xc00c, 0xb8ff, 0xc00c, 0x21, 0 - .dw 0xb940, 0xc00c, 0xb97f, 0xc00c, 0x21, 0 - .dw 0xb9c0, 0xc00c, 0xbfff, 0xc00c, 0x21, 0 - .dw 0xc040, 0xc00c, 0xc07f, 0xc00c, 0x21, 0 - .dw 0xc0c0, 0xc00c, 0xc0ff, 0xc00c, 0x21, 0 - .dw 0xc140, 0xc00c, 0xc17f, 0xc00c, 0x21, 0 - .dw 0xc1c0, 0xc00c, 0xc1ff, 0xc00c, 0x21, 0 - .dw 0xc240, 0xc00c, 0xc27f, 0xc00c, 0x21, 0 - .dw 0xc2c0, 0xc00c, 0xc2ff, 0xc00c, 0x21, 0 - .dw 0xc340, 0xc00c, 0xc37f, 0xc00c, 0x21, 0 - .dw 0xc3c0, 0xc00c, 0xc3ff, 0xc00c, 0x21, 0 - .dw 0xc440, 0xc00c, 0xc47f, 0xc00c, 0x21, 0 - .dw 0xc4c0, 0xc00c, 0xc4ff, 0xc00c, 0x21, 0 - .dw 0xc540, 0xc00c, 0xc57f, 0xc00c, 0x21, 0 - .dw 0xc5c0, 0xc00c, 0xc5ff, 0xc00c, 0x21, 0 - .dw 0xc640, 0xc00c, 0xc67f, 0xc00c, 0x21, 0 - .dw 0xc6c0, 0xc00c, 0xc6ff, 0xc00c, 0x21, 0 - .dw 0xc740, 0xc00c, 0xc77f, 0xc00c, 0x21, 0 - .dw 0xc7c0, 0xc00c, 0xc7ff, 0xc00c, 0x21, 0 - .dw 0xc840, 0xc00c, 0xc87f, 0xc00c, 0x21, 0 - .dw 0xc8c0, 0xc00c, 0xc8ff, 0xc00c, 0x21, 0 - .dw 0xc940, 0xc00c, 0xc97f, 0xc00c, 0x21, 0 - .dw 0xc9c0, 0xc00c, 0xc9ff, 0xc00c, 0x21, 0 - .dw 0xca40, 0xc00c, 0xca7f, 0xc00c, 0x21, 0 - .dw 0xcac0, 0xc00c, 0xcaff, 0xc00c, 0x21, 0 - .dw 0xcb40, 0xc00c, 0xcb7f, 0xc00c, 0x21, 0 - .dw 0xcbc0, 0xc00c, 0xcbff, 0xc00c, 0x21, 0 - .dw 0xcc40, 0xc00c, 0xcc7f, 0xc00c, 0x21, 0 - .dw 0xccc0, 0xc00c, 0xccff, 0xc00c, 0x21, 0 - .dw 0xcd40, 0xc00c, 0xcd7f, 0xc00c, 0x21, 0 - .dw 0xcdc0, 0xc00c, 0xcdff, 0xc00c, 0x21, 0 - .dw 0xce40, 0xc00c, 0xce7f, 0xc00c, 0x21, 0 - .dw 0xcec0, 0xc00c, 0xceff, 0xc00c, 0x21, 0 - .dw 0xcf40, 0xc00c, 0xcf7f, 0xc00c, 0x21, 0 - .dw 0xcfc0, 0xc00c, 0xcfff, 0xc00c, 0x21, 0 - .dw 0xd040, 0xc00c, 0xd07f, 0xc00c, 0x21, 0 - .dw 0xd0c0, 0xc00c, 0xd0ff, 0xc00c, 0x21, 0 - .dw 0xd140, 0xc00c, 0xd17f, 0xc00c, 0x21, 0 - .dw 0xd1c0, 0xc00c, 0xd1ff, 0xc00c, 0x21, 0 - .dw 0xd240, 0xc00c, 0xd27f, 0xc00c, 0x21, 0 - .dw 0xd2c0, 0xc00c, 0xd2ff, 0xc00c, 0x21, 0 - .dw 0xd340, 0xc00c, 0xd37f, 0xc00c, 0x21, 0 - .dw 0xd3c0, 0xc00c, 0xd3ff, 0xc00c, 0x21, 0 - .dw 0xd440, 0xc00c, 0xd47f, 0xc00c, 0x21, 0 - .dw 0xd4c0, 0xc00c, 0xd4ff, 0xc00c, 0x21, 0 - .dw 0xd540, 0xc00c, 0xd57f, 0xc00c, 0x21, 0 - .dw 0xd5c0, 0xc00c, 0xd5ff, 0xc00c, 0x21, 0 - .dw 0xd640, 0xc00c, 0xd67f, 0xc00c, 0x21, 0 - .dw 0xd6c0, 0xc00c, 0xd6ff, 0xc00c, 0x21, 0 - .dw 0xd740, 0xc00c, 0xd77f, 0xc00c, 0x21, 0 - .dw 0xd7c0, 0xc00c, 0xd7ff, 0xc00c, 0x21, 0 - .dw 0xd840, 0xc00c, 0xd87f, 0xc00c, 0x21, 0 - .dw 0xd8c0, 0xc00c, 0xd8ff, 0xc00c, 0x21, 0 - .dw 0xd940, 0xc00c, 0xd97f, 0xc00c, 0x21, 0 - .dw 0xd9c0, 0xc00c, 0xdfff, 0xc00c, 0x21, 0 - .dw 0xe040, 0xc00c, 0xe07f, 0xc00c, 0x21, 0 - .dw 0xe0c0, 0xc00c, 0xe0ff, 0xc00c, 0x21, 0 - .dw 0xe140, 0xc00c, 0xe17f, 0xc00c, 0x21, 0 - .dw 0xe1c0, 0xc00c, 0xe1ff, 0xc00c, 0x21, 0 - .dw 0xe240, 0xc00c, 0xe27f, 0xc00c, 0x21, 0 - .dw 0xe2c0, 0xc00c, 0xe2ff, 0xc00c, 0x21, 0 - .dw 0xe340, 0xc00c, 0xe37f, 0xc00c, 0x21, 0 - .dw 0xe3c0, 0xc00c, 0xe3ff, 0xc00c, 0x21, 0 - .dw 0xe440, 0xc00c, 0xe47f, 0xc00c, 0x21, 0 - .dw 0xe4c0, 0xc00c, 0xe4ff, 0xc00c, 0x21, 0 - .dw 0xe540, 0xc00c, 0xe57f, 0xc00c, 0x21, 0 - .dw 0xe5c0, 0xc00c, 0xe5ff, 0xc00c, 0x21, 0 - .dw 0xe640, 0xc00c, 0xe67f, 0xc00c, 0x21, 0 - .dw 0xe6c0, 0xc00c, 0xe6ff, 0xc00c, 0x21, 0 - .dw 0xe740, 0xc00c, 0xe77f, 0xc00c, 0x21, 0 - .dw 0xe7c0, 0xc00c, 0xe7ff, 0xc00c, 0x21, 0 - .dw 0xe840, 0xc00c, 0xe87f, 0xc00c, 0x21, 0 - .dw 0xe8c0, 0xc00c, 0xe8ff, 0xc00c, 0x21, 0 - .dw 0xe940, 0xc00c, 0xe97f, 0xc00c, 0x21, 0 - .dw 0xe9c0, 0xc00c, 0xe9ff, 0xc00c, 0x21, 0 - .dw 0xea40, 0xc00c, 0xea7f, 0xc00c, 0x21, 0 - .dw 0xeac0, 0xc00c, 0xeaff, 0xc00c, 0x21, 0 - .dw 0xeb40, 0xc00c, 0xeb7f, 0xc00c, 0x21, 0 - .dw 0xebc0, 0xc00c, 0xebff, 0xc00c, 0x21, 0 - .dw 0xec40, 0xc00c, 0xec7f, 0xc00c, 0x21, 0 - .dw 0xecc0, 0xc00c, 0xecff, 0xc00c, 0x21, 0 - .dw 0xed40, 0xc00c, 0xed7f, 0xc00c, 0x21, 0 - .dw 0xedc0, 0xc00c, 0xedff, 0xc00c, 0x21, 0 - .dw 0xee40, 0xc00c, 0xee7f, 0xc00c, 0x21, 0 - .dw 0xeec0, 0xc00c, 0xeeff, 0xc00c, 0x21, 0 - .dw 0xef40, 0xc00c, 0xef7f, 0xc00c, 0x21, 0 - .dw 0xefc0, 0xc00c, 0xefff, 0xc00c, 0x21, 0 - .dw 0xf040, 0xc00c, 0xf07f, 0xc00c, 0x21, 0 - .dw 0xf0c0, 0xc00c, 0xf0ff, 0xc00c, 0x21, 0 - .dw 0xf140, 0xc00c, 0xf17f, 0xc00c, 0x21, 0 - .dw 0xf1c0, 0xc00c, 0xf1ff, 0xc00c, 0x21, 0 - .dw 0xf240, 0xc00c, 0xf27f, 0xc00c, 0x21, 0 - .dw 0xf2c0, 0xc00c, 0xf2ff, 0xc00c, 0x21, 0 - .dw 0xf340, 0xc00c, 0xf37f, 0xc00c, 0x21, 0 - .dw 0xf3c0, 0xc00c, 0xf3ff, 0xc00c, 0x21, 0 - .dw 0xf440, 0xc00c, 0xf47f, 0xc00c, 0x21, 0 - .dw 0xf4c0, 0xc00c, 0xf4ff, 0xc00c, 0x21, 0 - .dw 0xf540, 0xc00c, 0xf57f, 0xc00c, 0x21, 0 - .dw 0xf5c0, 0xc00c, 0xf5ff, 0xc00c, 0x21, 0 - .dw 0xf640, 0xc00c, 0xf67f, 0xc00c, 0x21, 0 - .dw 0xf6c0, 0xc00c, 0xf6ff, 0xc00c, 0x21, 0 - .dw 0xf740, 0xc00c, 0xf77f, 0xc00c, 0x21, 0 - .dw 0xf7c0, 0xc00c, 0xf7ff, 0xc00c, 0x21, 0 - .dw 0xf840, 0xc00c, 0xf87f, 0xc00c, 0x21, 0 - .dw 0xf8c0, 0xc00c, 0xf8ff, 0xc00c, 0x21, 0 - .dw 0xf940, 0xc00c, 0xf97f, 0xc00c, 0x21, 0 - .dw 0xf9c0, 0xc00c, 0xffff, 0xc00c, 0x21, 0 - .dw 0x0040, 0xc00d, 0x007f, 0xc00d, 0x21, 0 - .dw 0x00c0, 0xc00d, 0x00ff, 0xc00d, 0x21, 0 - .dw 0x0140, 0xc00d, 0x017f, 0xc00d, 0x21, 0 - .dw 0x01c0, 0xc00d, 0x01ff, 0xc00d, 0x21, 0 - .dw 0x0240, 0xc00d, 0x027f, 0xc00d, 0x21, 0 - .dw 0x02c0, 0xc00d, 0x02ff, 0xc00d, 0x21, 0 - .dw 0x0340, 0xc00d, 0x037f, 0xc00d, 0x21, 0 - .dw 0x03c0, 0xc00d, 0x03ff, 0xc00d, 0x21, 0 - .dw 0x0440, 0xc00d, 0x047f, 0xc00d, 0x21, 0 - .dw 0x04c0, 0xc00d, 0x04ff, 0xc00d, 0x21, 0 - .dw 0x0540, 0xc00d, 0x057f, 0xc00d, 0x21, 0 - .dw 0x05c0, 0xc00d, 0x05ff, 0xc00d, 0x21, 0 - .dw 0x0640, 0xc00d, 0x067f, 0xc00d, 0x21, 0 - .dw 0x06c0, 0xc00d, 0x06ff, 0xc00d, 0x21, 0 - .dw 0x0740, 0xc00d, 0x077f, 0xc00d, 0x21, 0 - .dw 0x07c0, 0xc00d, 0x07ff, 0xc00d, 0x21, 0 - .dw 0x0840, 0xc00d, 0x087f, 0xc00d, 0x21, 0 - .dw 0x08c0, 0xc00d, 0x08ff, 0xc00d, 0x21, 0 - .dw 0x0940, 0xc00d, 0x097f, 0xc00d, 0x21, 0 - .dw 0x09c0, 0xc00d, 0x09ff, 0xc00d, 0x21, 0 - .dw 0x0a40, 0xc00d, 0x0a7f, 0xc00d, 0x21, 0 - .dw 0x0ac0, 0xc00d, 0x0aff, 0xc00d, 0x21, 0 - .dw 0x0b40, 0xc00d, 0x0b7f, 0xc00d, 0x21, 0 - .dw 0x0bc0, 0xc00d, 0x0bff, 0xc00d, 0x21, 0 - .dw 0x0c40, 0xc00d, 0x0c7f, 0xc00d, 0x21, 0 - .dw 0x0cc0, 0xc00d, 0x0cff, 0xc00d, 0x21, 0 - .dw 0x0d40, 0xc00d, 0x0d7f, 0xc00d, 0x21, 0 - .dw 0x0dc0, 0xc00d, 0x0dff, 0xc00d, 0x21, 0 - .dw 0x0e40, 0xc00d, 0x0e7f, 0xc00d, 0x21, 0 - .dw 0x0ec0, 0xc00d, 0x0eff, 0xc00d, 0x21, 0 - .dw 0x0f40, 0xc00d, 0x0f7f, 0xc00d, 0x21, 0 - .dw 0x0fc0, 0xc00d, 0x0fff, 0xc00d, 0x21, 0 - .dw 0x1040, 0xc00d, 0x107f, 0xc00d, 0x21, 0 - .dw 0x10c0, 0xc00d, 0x10ff, 0xc00d, 0x21, 0 - .dw 0x1140, 0xc00d, 0x117f, 0xc00d, 0x21, 0 - .dw 0x11c0, 0xc00d, 0x11ff, 0xc00d, 0x21, 0 - .dw 0x1240, 0xc00d, 0x127f, 0xc00d, 0x21, 0 - .dw 0x12c0, 0xc00d, 0x12ff, 0xc00d, 0x21, 0 - .dw 0x1340, 0xc00d, 0x137f, 0xc00d, 0x21, 0 - .dw 0x13c0, 0xc00d, 0x13ff, 0xc00d, 0x21, 0 - .dw 0x1440, 0xc00d, 0x147f, 0xc00d, 0x21, 0 - .dw 0x14c0, 0xc00d, 0x14ff, 0xc00d, 0x21, 0 - .dw 0x1540, 0xc00d, 0x157f, 0xc00d, 0x21, 0 - .dw 0x15c0, 0xc00d, 0x15ff, 0xc00d, 0x21, 0 - .dw 0x1640, 0xc00d, 0x167f, 0xc00d, 0x21, 0 - .dw 0x16c0, 0xc00d, 0x16ff, 0xc00d, 0x21, 0 - .dw 0x1740, 0xc00d, 0x177f, 0xc00d, 0x21, 0 - .dw 0x17c0, 0xc00d, 0x17ff, 0xc00d, 0x21, 0 - .dw 0x1840, 0xc00d, 0x187f, 0xc00d, 0x21, 0 - .dw 0x18c0, 0xc00d, 0x18ff, 0xc00d, 0x21, 0 - .dw 0x1940, 0xc00d, 0x197f, 0xc00d, 0x21, 0 - .dw 0x19c0, 0xc00d, 0x1fff, 0xc00d, 0x21, 0 - .dw 0x2040, 0xc00d, 0x207f, 0xc00d, 0x21, 0 - .dw 0x20c0, 0xc00d, 0x20ff, 0xc00d, 0x21, 0 - .dw 0x2140, 0xc00d, 0x217f, 0xc00d, 0x21, 0 - .dw 0x21c0, 0xc00d, 0x21ff, 0xc00d, 0x21, 0 - .dw 0x2240, 0xc00d, 0x227f, 0xc00d, 0x21, 0 - .dw 0x22c0, 0xc00d, 0x22ff, 0xc00d, 0x21, 0 - .dw 0x2340, 0xc00d, 0x237f, 0xc00d, 0x21, 0 - .dw 0x23c0, 0xc00d, 0x23ff, 0xc00d, 0x21, 0 - .dw 0x2440, 0xc00d, 0x247f, 0xc00d, 0x21, 0 - .dw 0x24c0, 0xc00d, 0x24ff, 0xc00d, 0x21, 0 - .dw 0x2540, 0xc00d, 0x257f, 0xc00d, 0x21, 0 - .dw 0x25c0, 0xc00d, 0x25ff, 0xc00d, 0x21, 0 - .dw 0x2640, 0xc00d, 0x267f, 0xc00d, 0x21, 0 - .dw 0x26c0, 0xc00d, 0x26ff, 0xc00d, 0x21, 0 - .dw 0x2740, 0xc00d, 0x277f, 0xc00d, 0x21, 0 - .dw 0x27c0, 0xc00d, 0x27ff, 0xc00d, 0x21, 0 - .dw 0x2840, 0xc00d, 0x287f, 0xc00d, 0x21, 0 - .dw 0x28c0, 0xc00d, 0x28ff, 0xc00d, 0x21, 0 - .dw 0x2940, 0xc00d, 0x297f, 0xc00d, 0x21, 0 - .dw 0x29c0, 0xc00d, 0x29ff, 0xc00d, 0x21, 0 - .dw 0x2a40, 0xc00d, 0x2a7f, 0xc00d, 0x21, 0 - .dw 0x2ac0, 0xc00d, 0x2aff, 0xc00d, 0x21, 0 - .dw 0x2b40, 0xc00d, 0x2b7f, 0xc00d, 0x21, 0 - .dw 0x2bc0, 0xc00d, 0x2bff, 0xc00d, 0x21, 0 - .dw 0x2c40, 0xc00d, 0x2c7f, 0xc00d, 0x21, 0 - .dw 0x2cc0, 0xc00d, 0x2cff, 0xc00d, 0x21, 0 - .dw 0x2d40, 0xc00d, 0x2d7f, 0xc00d, 0x21, 0 - .dw 0x2dc0, 0xc00d, 0x2dff, 0xc00d, 0x21, 0 - .dw 0x2e40, 0xc00d, 0x2e7f, 0xc00d, 0x21, 0 - .dw 0x2ec0, 0xc00d, 0x2eff, 0xc00d, 0x21, 0 - .dw 0x2f40, 0xc00d, 0x2f7f, 0xc00d, 0x21, 0 - .dw 0x2fc0, 0xc00d, 0x2fff, 0xc00d, 0x21, 0 - .dw 0x3040, 0xc00d, 0x307f, 0xc00d, 0x21, 0 - .dw 0x30c0, 0xc00d, 0x30ff, 0xc00d, 0x21, 0 - .dw 0x3140, 0xc00d, 0x317f, 0xc00d, 0x21, 0 - .dw 0x31c0, 0xc00d, 0x31ff, 0xc00d, 0x21, 0 - .dw 0x3240, 0xc00d, 0x327f, 0xc00d, 0x21, 0 - .dw 0x32c0, 0xc00d, 0x32ff, 0xc00d, 0x21, 0 - .dw 0x3340, 0xc00d, 0x337f, 0xc00d, 0x21, 0 - .dw 0x33c0, 0xc00d, 0x33ff, 0xc00d, 0x21, 0 - .dw 0x3440, 0xc00d, 0x347f, 0xc00d, 0x21, 0 - .dw 0x34c0, 0xc00d, 0x34ff, 0xc00d, 0x21, 0 - .dw 0x3540, 0xc00d, 0x357f, 0xc00d, 0x21, 0 - .dw 0x35c0, 0xc00d, 0x35ff, 0xc00d, 0x21, 0 - .dw 0x3640, 0xc00d, 0x367f, 0xc00d, 0x21, 0 - .dw 0x36c0, 0xc00d, 0x36ff, 0xc00d, 0x21, 0 - .dw 0x3740, 0xc00d, 0x377f, 0xc00d, 0x21, 0 - .dw 0x37c0, 0xc00d, 0x37ff, 0xc00d, 0x21, 0 - .dw 0x3840, 0xc00d, 0x387f, 0xc00d, 0x21, 0 - .dw 0x38c0, 0xc00d, 0x38ff, 0xc00d, 0x21, 0 - .dw 0x3940, 0xc00d, 0x397f, 0xc00d, 0x21, 0 - .dw 0x39c0, 0xc00d, 0x3fff, 0xc00d, 0x21, 0 - .dw 0x4040, 0xc00d, 0x407f, 0xc00d, 0x21, 0 - .dw 0x40c0, 0xc00d, 0x40ff, 0xc00d, 0x21, 0 - .dw 0x4140, 0xc00d, 0x417f, 0xc00d, 0x21, 0 - .dw 0x41c0, 0xc00d, 0x41ff, 0xc00d, 0x21, 0 - .dw 0x4240, 0xc00d, 0x427f, 0xc00d, 0x21, 0 - .dw 0x42c0, 0xc00d, 0x42ff, 0xc00d, 0x21, 0 - .dw 0x4340, 0xc00d, 0x437f, 0xc00d, 0x21, 0 - .dw 0x43c0, 0xc00d, 0x43ff, 0xc00d, 0x21, 0 - .dw 0x4440, 0xc00d, 0x447f, 0xc00d, 0x21, 0 - .dw 0x44c0, 0xc00d, 0x44ff, 0xc00d, 0x21, 0 - .dw 0x4540, 0xc00d, 0x457f, 0xc00d, 0x21, 0 - .dw 0x45c0, 0xc00d, 0x45ff, 0xc00d, 0x21, 0 - .dw 0x4640, 0xc00d, 0x467f, 0xc00d, 0x21, 0 - .dw 0x46c0, 0xc00d, 0x46ff, 0xc00d, 0x21, 0 - .dw 0x4740, 0xc00d, 0x477f, 0xc00d, 0x21, 0 - .dw 0x47c0, 0xc00d, 0x47ff, 0xc00d, 0x21, 0 - .dw 0x4840, 0xc00d, 0x487f, 0xc00d, 0x21, 0 - .dw 0x48c0, 0xc00d, 0x48ff, 0xc00d, 0x21, 0 - .dw 0x4940, 0xc00d, 0x497f, 0xc00d, 0x21, 0 - .dw 0x49c0, 0xc00d, 0x49ff, 0xc00d, 0x21, 0 - .dw 0x4a40, 0xc00d, 0x4a7f, 0xc00d, 0x21, 0 - .dw 0x4ac0, 0xc00d, 0x4aff, 0xc00d, 0x21, 0 - .dw 0x4b40, 0xc00d, 0x4b7f, 0xc00d, 0x21, 0 - .dw 0x4bc0, 0xc00d, 0x4bff, 0xc00d, 0x21, 0 - .dw 0x4c40, 0xc00d, 0x4c7f, 0xc00d, 0x21, 0 - .dw 0x4cc0, 0xc00d, 0x4cff, 0xc00d, 0x21, 0 - .dw 0x4d40, 0xc00d, 0x4d7f, 0xc00d, 0x21, 0 - .dw 0x4dc0, 0xc00d, 0x4dff, 0xc00d, 0x21, 0 - .dw 0x4e40, 0xc00d, 0x4e7f, 0xc00d, 0x21, 0 - .dw 0x4ec0, 0xc00d, 0x4eff, 0xc00d, 0x21, 0 - .dw 0x4f40, 0xc00d, 0x4f7f, 0xc00d, 0x21, 0 - .dw 0x4fc0, 0xc00d, 0x4fff, 0xc00d, 0x21, 0 - .dw 0x5040, 0xc00d, 0x507f, 0xc00d, 0x21, 0 - .dw 0x50c0, 0xc00d, 0x50ff, 0xc00d, 0x21, 0 - .dw 0x5140, 0xc00d, 0x517f, 0xc00d, 0x21, 0 - .dw 0x51c0, 0xc00d, 0x51ff, 0xc00d, 0x21, 0 - .dw 0x5240, 0xc00d, 0x527f, 0xc00d, 0x21, 0 - .dw 0x52c0, 0xc00d, 0x52ff, 0xc00d, 0x21, 0 - .dw 0x5340, 0xc00d, 0x537f, 0xc00d, 0x21, 0 - .dw 0x53c0, 0xc00d, 0x53ff, 0xc00d, 0x21, 0 - .dw 0x5440, 0xc00d, 0x547f, 0xc00d, 0x21, 0 - .dw 0x54c0, 0xc00d, 0x54ff, 0xc00d, 0x21, 0 - .dw 0x5540, 0xc00d, 0x557f, 0xc00d, 0x21, 0 - .dw 0x55c0, 0xc00d, 0x55ff, 0xc00d, 0x21, 0 - .dw 0x5640, 0xc00d, 0x567f, 0xc00d, 0x21, 0 - .dw 0x56c0, 0xc00d, 0x56ff, 0xc00d, 0x21, 0 - .dw 0x5740, 0xc00d, 0x577f, 0xc00d, 0x21, 0 - .dw 0x57c0, 0xc00d, 0x57ff, 0xc00d, 0x21, 0 - .dw 0x5840, 0xc00d, 0x587f, 0xc00d, 0x21, 0 - .dw 0x58c0, 0xc00d, 0x58ff, 0xc00d, 0x21, 0 - .dw 0x5940, 0xc00d, 0x597f, 0xc00d, 0x21, 0 - .dw 0x59c0, 0xc00d, 0x5fff, 0xc00d, 0x21, 0 - .dw 0x6040, 0xc00d, 0x607f, 0xc00d, 0x21, 0 - .dw 0x60c0, 0xc00d, 0x60ff, 0xc00d, 0x21, 0 - .dw 0x6140, 0xc00d, 0x617f, 0xc00d, 0x21, 0 - .dw 0x61c0, 0xc00d, 0x61ff, 0xc00d, 0x21, 0 - .dw 0x6240, 0xc00d, 0x627f, 0xc00d, 0x21, 0 - .dw 0x62c0, 0xc00d, 0x62ff, 0xc00d, 0x21, 0 - .dw 0x6340, 0xc00d, 0x637f, 0xc00d, 0x21, 0 - .dw 0x63c0, 0xc00d, 0x63ff, 0xc00d, 0x21, 0 - .dw 0x6440, 0xc00d, 0x647f, 0xc00d, 0x21, 0 - .dw 0x64c0, 0xc00d, 0x64ff, 0xc00d, 0x21, 0 - .dw 0x6540, 0xc00d, 0x657f, 0xc00d, 0x21, 0 - .dw 0x65c0, 0xc00d, 0x65ff, 0xc00d, 0x21, 0 - .dw 0x6640, 0xc00d, 0x667f, 0xc00d, 0x21, 0 - .dw 0x66c0, 0xc00d, 0x66ff, 0xc00d, 0x21, 0 - .dw 0x6740, 0xc00d, 0x677f, 0xc00d, 0x21, 0 - .dw 0x67c0, 0xc00d, 0x67ff, 0xc00d, 0x21, 0 - .dw 0x6840, 0xc00d, 0x687f, 0xc00d, 0x21, 0 - .dw 0x68c0, 0xc00d, 0x68ff, 0xc00d, 0x21, 0 - .dw 0x6940, 0xc00d, 0x697f, 0xc00d, 0x21, 0 - .dw 0x69c0, 0xc00d, 0x69ff, 0xc00d, 0x21, 0 - .dw 0x6a40, 0xc00d, 0x6a7f, 0xc00d, 0x21, 0 - .dw 0x6ac0, 0xc00d, 0x6aff, 0xc00d, 0x21, 0 - .dw 0x6b40, 0xc00d, 0x6b7f, 0xc00d, 0x21, 0 - .dw 0x6bc0, 0xc00d, 0x6bff, 0xc00d, 0x21, 0 - .dw 0x6c40, 0xc00d, 0x6c7f, 0xc00d, 0x21, 0 - .dw 0x6cc0, 0xc00d, 0x6cff, 0xc00d, 0x21, 0 - .dw 0x6d40, 0xc00d, 0x6d7f, 0xc00d, 0x21, 0 - .dw 0x6dc0, 0xc00d, 0x6dff, 0xc00d, 0x21, 0 - .dw 0x6e40, 0xc00d, 0x6e7f, 0xc00d, 0x21, 0 - .dw 0x6ec0, 0xc00d, 0x6eff, 0xc00d, 0x21, 0 - .dw 0x6f40, 0xc00d, 0x6f7f, 0xc00d, 0x21, 0 - .dw 0x6fc0, 0xc00d, 0x6fff, 0xc00d, 0x21, 0 - .dw 0x7040, 0xc00d, 0x707f, 0xc00d, 0x21, 0 - .dw 0x70c0, 0xc00d, 0x70ff, 0xc00d, 0x21, 0 - .dw 0x7140, 0xc00d, 0x717f, 0xc00d, 0x21, 0 - .dw 0x71c0, 0xc00d, 0x71ff, 0xc00d, 0x21, 0 - .dw 0x7240, 0xc00d, 0x727f, 0xc00d, 0x21, 0 - .dw 0x72c0, 0xc00d, 0x72ff, 0xc00d, 0x21, 0 - .dw 0x7340, 0xc00d, 0x737f, 0xc00d, 0x21, 0 - .dw 0x73c0, 0xc00d, 0x73ff, 0xc00d, 0x21, 0 - .dw 0x7440, 0xc00d, 0x747f, 0xc00d, 0x21, 0 - .dw 0x74c0, 0xc00d, 0x74ff, 0xc00d, 0x21, 0 - .dw 0x7540, 0xc00d, 0x757f, 0xc00d, 0x21, 0 - .dw 0x75c0, 0xc00d, 0x75ff, 0xc00d, 0x21, 0 - .dw 0x7640, 0xc00d, 0x767f, 0xc00d, 0x21, 0 - .dw 0x76c0, 0xc00d, 0x76ff, 0xc00d, 0x21, 0 - .dw 0x7740, 0xc00d, 0x777f, 0xc00d, 0x21, 0 - .dw 0x77c0, 0xc00d, 0x77ff, 0xc00d, 0x21, 0 - .dw 0x7840, 0xc00d, 0x787f, 0xc00d, 0x21, 0 - .dw 0x78c0, 0xc00d, 0x78ff, 0xc00d, 0x21, 0 - .dw 0x7940, 0xc00d, 0x797f, 0xc00d, 0x21, 0 - .dw 0x79c0, 0xc00d, 0x7fff, 0xc00d, 0x21, 0 - .dw 0x8040, 0xc00d, 0x807f, 0xc00d, 0x21, 0 - .dw 0x80c0, 0xc00d, 0x80ff, 0xc00d, 0x21, 0 - .dw 0x8140, 0xc00d, 0x817f, 0xc00d, 0x21, 0 - .dw 0x81c0, 0xc00d, 0x81ff, 0xc00d, 0x21, 0 - .dw 0x8240, 0xc00d, 0x827f, 0xc00d, 0x21, 0 - .dw 0x82c0, 0xc00d, 0x82ff, 0xc00d, 0x21, 0 - .dw 0x8340, 0xc00d, 0x837f, 0xc00d, 0x21, 0 - .dw 0x83c0, 0xc00d, 0x83ff, 0xc00d, 0x21, 0 - .dw 0x8440, 0xc00d, 0x847f, 0xc00d, 0x21, 0 - .dw 0x84c0, 0xc00d, 0x84ff, 0xc00d, 0x21, 0 - .dw 0x8540, 0xc00d, 0x857f, 0xc00d, 0x21, 0 - .dw 0x85c0, 0xc00d, 0x85ff, 0xc00d, 0x21, 0 - .dw 0x8640, 0xc00d, 0x867f, 0xc00d, 0x21, 0 - .dw 0x86c0, 0xc00d, 0x86ff, 0xc00d, 0x21, 0 - .dw 0x8740, 0xc00d, 0x877f, 0xc00d, 0x21, 0 - .dw 0x87c0, 0xc00d, 0x87ff, 0xc00d, 0x21, 0 - .dw 0x8840, 0xc00d, 0x887f, 0xc00d, 0x21, 0 - .dw 0x88c0, 0xc00d, 0x88ff, 0xc00d, 0x21, 0 - .dw 0x8940, 0xc00d, 0x897f, 0xc00d, 0x21, 0 - .dw 0x89c0, 0xc00d, 0x89ff, 0xc00d, 0x21, 0 - .dw 0x8a40, 0xc00d, 0x8a7f, 0xc00d, 0x21, 0 - .dw 0x8ac0, 0xc00d, 0x8aff, 0xc00d, 0x21, 0 - .dw 0x8b40, 0xc00d, 0x8b7f, 0xc00d, 0x21, 0 - .dw 0x8bc0, 0xc00d, 0x8bff, 0xc00d, 0x21, 0 - .dw 0x8c40, 0xc00d, 0x8c7f, 0xc00d, 0x21, 0 - .dw 0x8cc0, 0xc00d, 0x8cff, 0xc00d, 0x21, 0 - .dw 0x8d40, 0xc00d, 0x8d7f, 0xc00d, 0x21, 0 - .dw 0x8dc0, 0xc00d, 0x8dff, 0xc00d, 0x21, 0 - .dw 0x8e40, 0xc00d, 0x8e7f, 0xc00d, 0x21, 0 - .dw 0x8ec0, 0xc00d, 0x8eff, 0xc00d, 0x21, 0 - .dw 0x8f40, 0xc00d, 0x8f7f, 0xc00d, 0x21, 0 - .dw 0x8fc0, 0xc00d, 0x8fff, 0xc00d, 0x21, 0 - .dw 0x9040, 0xc00d, 0x907f, 0xc00d, 0x21, 0 - .dw 0x90c0, 0xc00d, 0x90ff, 0xc00d, 0x21, 0 - .dw 0x9140, 0xc00d, 0x917f, 0xc00d, 0x21, 0 - .dw 0x91c0, 0xc00d, 0x91ff, 0xc00d, 0x21, 0 - .dw 0x9240, 0xc00d, 0x927f, 0xc00d, 0x21, 0 - .dw 0x92c0, 0xc00d, 0x92ff, 0xc00d, 0x21, 0 - .dw 0x9340, 0xc00d, 0x937f, 0xc00d, 0x21, 0 - .dw 0x93c0, 0xc00d, 0x93ff, 0xc00d, 0x21, 0 - .dw 0x9440, 0xc00d, 0x947f, 0xc00d, 0x21, 0 - .dw 0x94c0, 0xc00d, 0x94ff, 0xc00d, 0x21, 0 - .dw 0x9540, 0xc00d, 0x957f, 0xc00d, 0x21, 0 - .dw 0x95c0, 0xc00d, 0x95ff, 0xc00d, 0x21, 0 - .dw 0x9640, 0xc00d, 0x967f, 0xc00d, 0x21, 0 - .dw 0x96c0, 0xc00d, 0x96ff, 0xc00d, 0x21, 0 - .dw 0x9740, 0xc00d, 0x977f, 0xc00d, 0x21, 0 - .dw 0x97c0, 0xc00d, 0x97ff, 0xc00d, 0x21, 0 - .dw 0x9840, 0xc00d, 0x987f, 0xc00d, 0x21, 0 - .dw 0x98c0, 0xc00d, 0x98ff, 0xc00d, 0x21, 0 - .dw 0x9940, 0xc00d, 0x997f, 0xc00d, 0x21, 0 - .dw 0x99c0, 0xc00d, 0x9fff, 0xc00d, 0x21, 0 - .dw 0xa040, 0xc00d, 0xa07f, 0xc00d, 0x21, 0 - .dw 0xa0c0, 0xc00d, 0xa0ff, 0xc00d, 0x21, 0 - .dw 0xa140, 0xc00d, 0xa17f, 0xc00d, 0x21, 0 - .dw 0xa1c0, 0xc00d, 0xa1ff, 0xc00d, 0x21, 0 - .dw 0xa240, 0xc00d, 0xa27f, 0xc00d, 0x21, 0 - .dw 0xa2c0, 0xc00d, 0xa2ff, 0xc00d, 0x21, 0 - .dw 0xa340, 0xc00d, 0xa37f, 0xc00d, 0x21, 0 - .dw 0xa3c0, 0xc00d, 0xa3ff, 0xc00d, 0x21, 0 - .dw 0xa440, 0xc00d, 0xa47f, 0xc00d, 0x21, 0 - .dw 0xa4c0, 0xc00d, 0xa4ff, 0xc00d, 0x21, 0 - .dw 0xa540, 0xc00d, 0xa57f, 0xc00d, 0x21, 0 - .dw 0xa5c0, 0xc00d, 0xa5ff, 0xc00d, 0x21, 0 - .dw 0xa640, 0xc00d, 0xa67f, 0xc00d, 0x21, 0 - .dw 0xa6c0, 0xc00d, 0xa6ff, 0xc00d, 0x21, 0 - .dw 0xa740, 0xc00d, 0xa77f, 0xc00d, 0x21, 0 - .dw 0xa7c0, 0xc00d, 0xa7ff, 0xc00d, 0x21, 0 - .dw 0xa840, 0xc00d, 0xa87f, 0xc00d, 0x21, 0 - .dw 0xa8c0, 0xc00d, 0xa8ff, 0xc00d, 0x21, 0 - .dw 0xa940, 0xc00d, 0xa97f, 0xc00d, 0x21, 0 - .dw 0xa9c0, 0xc00d, 0xa9ff, 0xc00d, 0x21, 0 - .dw 0xaa40, 0xc00d, 0xaa7f, 0xc00d, 0x21, 0 - .dw 0xaac0, 0xc00d, 0xaaff, 0xc00d, 0x21, 0 - .dw 0xab40, 0xc00d, 0xab7f, 0xc00d, 0x21, 0 - .dw 0xabc0, 0xc00d, 0xabff, 0xc00d, 0x21, 0 - .dw 0xac40, 0xc00d, 0xac7f, 0xc00d, 0x21, 0 - .dw 0xacc0, 0xc00d, 0xacff, 0xc00d, 0x21, 0 - .dw 0xad40, 0xc00d, 0xad7f, 0xc00d, 0x21, 0 - .dw 0xadc0, 0xc00d, 0xadff, 0xc00d, 0x21, 0 - .dw 0xae40, 0xc00d, 0xae7f, 0xc00d, 0x21, 0 - .dw 0xaec0, 0xc00d, 0xaeff, 0xc00d, 0x21, 0 - .dw 0xaf40, 0xc00d, 0xaf7f, 0xc00d, 0x21, 0 - .dw 0xafc0, 0xc00d, 0xafff, 0xc00d, 0x21, 0 - .dw 0xb040, 0xc00d, 0xb07f, 0xc00d, 0x21, 0 - .dw 0xb0c0, 0xc00d, 0xb0ff, 0xc00d, 0x21, 0 - .dw 0xb140, 0xc00d, 0xb17f, 0xc00d, 0x21, 0 - .dw 0xb1c0, 0xc00d, 0xb1ff, 0xc00d, 0x21, 0 - .dw 0xb240, 0xc00d, 0xb27f, 0xc00d, 0x21, 0 - .dw 0xb2c0, 0xc00d, 0xb2ff, 0xc00d, 0x21, 0 - .dw 0xb340, 0xc00d, 0xb37f, 0xc00d, 0x21, 0 - .dw 0xb3c0, 0xc00d, 0xb3ff, 0xc00d, 0x21, 0 - .dw 0xb440, 0xc00d, 0xb47f, 0xc00d, 0x21, 0 - .dw 0xb4c0, 0xc00d, 0xb4ff, 0xc00d, 0x21, 0 - .dw 0xb540, 0xc00d, 0xb57f, 0xc00d, 0x21, 0 - .dw 0xb5c0, 0xc00d, 0xb5ff, 0xc00d, 0x21, 0 - .dw 0xb640, 0xc00d, 0xb67f, 0xc00d, 0x21, 0 - .dw 0xb6c0, 0xc00d, 0xb6ff, 0xc00d, 0x21, 0 - .dw 0xb740, 0xc00d, 0xb77f, 0xc00d, 0x21, 0 - .dw 0xb7c0, 0xc00d, 0xb7ff, 0xc00d, 0x21, 0 - .dw 0xb840, 0xc00d, 0xb87f, 0xc00d, 0x21, 0 - .dw 0xb8c0, 0xc00d, 0xb8ff, 0xc00d, 0x21, 0 - .dw 0xb940, 0xc00d, 0xb97f, 0xc00d, 0x21, 0 - .dw 0xb9c0, 0xc00d, 0xbfff, 0xc00d, 0x21, 0 - .dw 0xc040, 0xc00d, 0xc07f, 0xc00d, 0x21, 0 - .dw 0xc0c0, 0xc00d, 0xc0ff, 0xc00d, 0x21, 0 - .dw 0xc140, 0xc00d, 0xc17f, 0xc00d, 0x21, 0 - .dw 0xc1c0, 0xc00d, 0xc1ff, 0xc00d, 0x21, 0 - .dw 0xc240, 0xc00d, 0xc27f, 0xc00d, 0x21, 0 - .dw 0xc2c0, 0xc00d, 0xc2ff, 0xc00d, 0x21, 0 - .dw 0xc340, 0xc00d, 0xc37f, 0xc00d, 0x21, 0 - .dw 0xc3c0, 0xc00d, 0xc3ff, 0xc00d, 0x21, 0 - .dw 0xc440, 0xc00d, 0xc47f, 0xc00d, 0x21, 0 - .dw 0xc4c0, 0xc00d, 0xc4ff, 0xc00d, 0x21, 0 - .dw 0xc540, 0xc00d, 0xc57f, 0xc00d, 0x21, 0 - .dw 0xc5c0, 0xc00d, 0xc5ff, 0xc00d, 0x21, 0 - .dw 0xc640, 0xc00d, 0xc67f, 0xc00d, 0x21, 0 - .dw 0xc6c0, 0xc00d, 0xc6ff, 0xc00d, 0x21, 0 - .dw 0xc740, 0xc00d, 0xc77f, 0xc00d, 0x21, 0 - .dw 0xc7c0, 0xc00d, 0xc7ff, 0xc00d, 0x21, 0 - .dw 0xc840, 0xc00d, 0xc87f, 0xc00d, 0x21, 0 - .dw 0xc8c0, 0xc00d, 0xc8ff, 0xc00d, 0x21, 0 - .dw 0xc940, 0xc00d, 0xc97f, 0xc00d, 0x21, 0 - .dw 0xc9c0, 0xc00d, 0xc9ff, 0xc00d, 0x21, 0 - .dw 0xca40, 0xc00d, 0xca7f, 0xc00d, 0x21, 0 - .dw 0xcac0, 0xc00d, 0xcaff, 0xc00d, 0x21, 0 - .dw 0xcb40, 0xc00d, 0xcb7f, 0xc00d, 0x21, 0 - .dw 0xcbc0, 0xc00d, 0xcbff, 0xc00d, 0x21, 0 - .dw 0xcc40, 0xc00d, 0xcc7f, 0xc00d, 0x21, 0 - .dw 0xccc0, 0xc00d, 0xccff, 0xc00d, 0x21, 0 - .dw 0xcd40, 0xc00d, 0xcd7f, 0xc00d, 0x21, 0 - .dw 0xcdc0, 0xc00d, 0xcdff, 0xc00d, 0x21, 0 - .dw 0xce40, 0xc00d, 0xce7f, 0xc00d, 0x21, 0 - .dw 0xcec0, 0xc00d, 0xceff, 0xc00d, 0x21, 0 - .dw 0xcf40, 0xc00d, 0xcf7f, 0xc00d, 0x21, 0 - .dw 0xcfc0, 0xc00d, 0xcfff, 0xc00d, 0x21, 0 - .dw 0xd040, 0xc00d, 0xd07f, 0xc00d, 0x21, 0 - .dw 0xd0c0, 0xc00d, 0xd0ff, 0xc00d, 0x21, 0 - .dw 0xd140, 0xc00d, 0xd17f, 0xc00d, 0x21, 0 - .dw 0xd1c0, 0xc00d, 0xd1ff, 0xc00d, 0x21, 0 - .dw 0xd240, 0xc00d, 0xd27f, 0xc00d, 0x21, 0 - .dw 0xd2c0, 0xc00d, 0xd2ff, 0xc00d, 0x21, 0 - .dw 0xd340, 0xc00d, 0xd37f, 0xc00d, 0x21, 0 - .dw 0xd3c0, 0xc00d, 0xd3ff, 0xc00d, 0x21, 0 - .dw 0xd440, 0xc00d, 0xd47f, 0xc00d, 0x21, 0 - .dw 0xd4c0, 0xc00d, 0xd4ff, 0xc00d, 0x21, 0 - .dw 0xd540, 0xc00d, 0xd57f, 0xc00d, 0x21, 0 - .dw 0xd5c0, 0xc00d, 0xd5ff, 0xc00d, 0x21, 0 - .dw 0xd640, 0xc00d, 0xd67f, 0xc00d, 0x21, 0 - .dw 0xd6c0, 0xc00d, 0xd6ff, 0xc00d, 0x21, 0 - .dw 0xd740, 0xc00d, 0xd77f, 0xc00d, 0x21, 0 - .dw 0xd7c0, 0xc00d, 0xd7ff, 0xc00d, 0x21, 0 - .dw 0xd840, 0xc00d, 0xd87f, 0xc00d, 0x21, 0 - .dw 0xd8c0, 0xc00d, 0xd8ff, 0xc00d, 0x21, 0 - .dw 0xd940, 0xc00d, 0xd97f, 0xc00d, 0x21, 0 - .dw 0xd9c0, 0xc00d, 0xdfff, 0xc00d, 0x21, 0 - .dw 0xe040, 0xc00d, 0xe07f, 0xc00d, 0x21, 0 - .dw 0xe0c0, 0xc00d, 0xe0ff, 0xc00d, 0x21, 0 - .dw 0xe140, 0xc00d, 0xe17f, 0xc00d, 0x21, 0 - .dw 0xe1c0, 0xc00d, 0xe1ff, 0xc00d, 0x21, 0 - .dw 0xe240, 0xc00d, 0xe27f, 0xc00d, 0x21, 0 - .dw 0xe2c0, 0xc00d, 0xe2ff, 0xc00d, 0x21, 0 - .dw 0xe340, 0xc00d, 0xe37f, 0xc00d, 0x21, 0 - .dw 0xe3c0, 0xc00d, 0xe3ff, 0xc00d, 0x21, 0 - .dw 0xe440, 0xc00d, 0xe47f, 0xc00d, 0x21, 0 - .dw 0xe4c0, 0xc00d, 0xe4ff, 0xc00d, 0x21, 0 - .dw 0xe540, 0xc00d, 0xe57f, 0xc00d, 0x21, 0 - .dw 0xe5c0, 0xc00d, 0xe5ff, 0xc00d, 0x21, 0 - .dw 0xe640, 0xc00d, 0xe67f, 0xc00d, 0x21, 0 - .dw 0xe6c0, 0xc00d, 0xe6ff, 0xc00d, 0x21, 0 - .dw 0xe740, 0xc00d, 0xe77f, 0xc00d, 0x21, 0 - .dw 0xe7c0, 0xc00d, 0xe7ff, 0xc00d, 0x21, 0 - .dw 0xe840, 0xc00d, 0xe87f, 0xc00d, 0x21, 0 - .dw 0xe8c0, 0xc00d, 0xe8ff, 0xc00d, 0x21, 0 - .dw 0xe940, 0xc00d, 0xe97f, 0xc00d, 0x21, 0 - .dw 0xe9c0, 0xc00d, 0xe9ff, 0xc00d, 0x21, 0 - .dw 0xea40, 0xc00d, 0xea7f, 0xc00d, 0x21, 0 - .dw 0xeac0, 0xc00d, 0xeaff, 0xc00d, 0x21, 0 - .dw 0xeb40, 0xc00d, 0xeb7f, 0xc00d, 0x21, 0 - .dw 0xebc0, 0xc00d, 0xebff, 0xc00d, 0x21, 0 - .dw 0xec40, 0xc00d, 0xec7f, 0xc00d, 0x21, 0 - .dw 0xecc0, 0xc00d, 0xecff, 0xc00d, 0x21, 0 - .dw 0xed40, 0xc00d, 0xed7f, 0xc00d, 0x21, 0 - .dw 0xedc0, 0xc00d, 0xedff, 0xc00d, 0x21, 0 - .dw 0xee40, 0xc00d, 0xee7f, 0xc00d, 0x21, 0 - .dw 0xeec0, 0xc00d, 0xeeff, 0xc00d, 0x21, 0 - .dw 0xef40, 0xc00d, 0xef7f, 0xc00d, 0x21, 0 - .dw 0xefc0, 0xc00d, 0xefff, 0xc00d, 0x21, 0 - .dw 0xf040, 0xc00d, 0xf07f, 0xc00d, 0x21, 0 - .dw 0xf0c0, 0xc00d, 0xf0ff, 0xc00d, 0x21, 0 - .dw 0xf140, 0xc00d, 0xf17f, 0xc00d, 0x21, 0 - .dw 0xf1c0, 0xc00d, 0xf1ff, 0xc00d, 0x21, 0 - .dw 0xf240, 0xc00d, 0xf27f, 0xc00d, 0x21, 0 - .dw 0xf2c0, 0xc00d, 0xf2ff, 0xc00d, 0x21, 0 - .dw 0xf340, 0xc00d, 0xf37f, 0xc00d, 0x21, 0 - .dw 0xf3c0, 0xc00d, 0xf3ff, 0xc00d, 0x21, 0 - .dw 0xf440, 0xc00d, 0xf47f, 0xc00d, 0x21, 0 - .dw 0xf4c0, 0xc00d, 0xf4ff, 0xc00d, 0x21, 0 - .dw 0xf540, 0xc00d, 0xf57f, 0xc00d, 0x21, 0 - .dw 0xf5c0, 0xc00d, 0xf5ff, 0xc00d, 0x21, 0 - .dw 0xf640, 0xc00d, 0xf67f, 0xc00d, 0x21, 0 - .dw 0xf6c0, 0xc00d, 0xf6ff, 0xc00d, 0x21, 0 - .dw 0xf740, 0xc00d, 0xf77f, 0xc00d, 0x21, 0 - .dw 0xf7c0, 0xc00d, 0xf7ff, 0xc00d, 0x21, 0 - .dw 0xf840, 0xc00d, 0xf87f, 0xc00d, 0x21, 0 - .dw 0xf8c0, 0xc00d, 0xf8ff, 0xc00d, 0x21, 0 - .dw 0xf940, 0xc00d, 0xf97f, 0xc00d, 0x21, 0 - .dw 0xf9c0, 0xc00d, 0xffff, 0xc00d, 0x21, 0 - .dw 0x0040, 0xc00e, 0x007f, 0xc00e, 0x21, 0 - .dw 0x00c0, 0xc00e, 0x00ff, 0xc00e, 0x21, 0 - .dw 0x0140, 0xc00e, 0x017f, 0xc00e, 0x21, 0 - .dw 0x01c0, 0xc00e, 0x01ff, 0xc00e, 0x21, 0 - .dw 0x0240, 0xc00e, 0x027f, 0xc00e, 0x21, 0 - .dw 0x02c0, 0xc00e, 0x02ff, 0xc00e, 0x21, 0 - .dw 0x0340, 0xc00e, 0x037f, 0xc00e, 0x21, 0 - .dw 0x03c0, 0xc00e, 0x03ff, 0xc00e, 0x21, 0 - .dw 0x0440, 0xc00e, 0x047f, 0xc00e, 0x21, 0 - .dw 0x04c0, 0xc00e, 0x04ff, 0xc00e, 0x21, 0 - .dw 0x0540, 0xc00e, 0x057f, 0xc00e, 0x21, 0 - .dw 0x05c0, 0xc00e, 0x05ff, 0xc00e, 0x21, 0 - .dw 0x0640, 0xc00e, 0x067f, 0xc00e, 0x21, 0 - .dw 0x06c0, 0xc00e, 0x06ff, 0xc00e, 0x21, 0 - .dw 0x0740, 0xc00e, 0x077f, 0xc00e, 0x21, 0 - .dw 0x07c0, 0xc00e, 0x07ff, 0xc00e, 0x21, 0 - .dw 0x0840, 0xc00e, 0x087f, 0xc00e, 0x21, 0 - .dw 0x08c0, 0xc00e, 0x08ff, 0xc00e, 0x21, 0 - .dw 0x0940, 0xc00e, 0x097f, 0xc00e, 0x21, 0 - .dw 0x09c0, 0xc00e, 0x09ff, 0xc00e, 0x21, 0 - .dw 0x0a40, 0xc00e, 0x0a7f, 0xc00e, 0x21, 0 - .dw 0x0ac0, 0xc00e, 0x0aff, 0xc00e, 0x21, 0 - .dw 0x0b40, 0xc00e, 0x0b7f, 0xc00e, 0x21, 0 - .dw 0x0bc0, 0xc00e, 0x0bff, 0xc00e, 0x21, 0 - .dw 0x0c40, 0xc00e, 0x0c7f, 0xc00e, 0x21, 0 - .dw 0x0cc0, 0xc00e, 0x0cff, 0xc00e, 0x21, 0 - .dw 0x0d40, 0xc00e, 0x0d7f, 0xc00e, 0x21, 0 - .dw 0x0dc0, 0xc00e, 0x0dff, 0xc00e, 0x21, 0 - .dw 0x0e40, 0xc00e, 0x0e7f, 0xc00e, 0x21, 0 - .dw 0x0ec0, 0xc00e, 0x0eff, 0xc00e, 0x21, 0 - .dw 0x0f40, 0xc00e, 0x0f7f, 0xc00e, 0x21, 0 - .dw 0x0fc0, 0xc00e, 0x0fff, 0xc00e, 0x21, 0 - .dw 0x1040, 0xc00e, 0x107f, 0xc00e, 0x21, 0 - .dw 0x10c0, 0xc00e, 0x10ff, 0xc00e, 0x21, 0 - .dw 0x1140, 0xc00e, 0x117f, 0xc00e, 0x21, 0 - .dw 0x11c0, 0xc00e, 0x11ff, 0xc00e, 0x21, 0 - .dw 0x1240, 0xc00e, 0x127f, 0xc00e, 0x21, 0 - .dw 0x12c0, 0xc00e, 0x12ff, 0xc00e, 0x21, 0 - .dw 0x1340, 0xc00e, 0x137f, 0xc00e, 0x21, 0 - .dw 0x13c0, 0xc00e, 0x13ff, 0xc00e, 0x21, 0 - .dw 0x1440, 0xc00e, 0x147f, 0xc00e, 0x21, 0 - .dw 0x14c0, 0xc00e, 0x14ff, 0xc00e, 0x21, 0 - .dw 0x1540, 0xc00e, 0x157f, 0xc00e, 0x21, 0 - .dw 0x15c0, 0xc00e, 0x15ff, 0xc00e, 0x21, 0 - .dw 0x1640, 0xc00e, 0x167f, 0xc00e, 0x21, 0 - .dw 0x16c0, 0xc00e, 0x16ff, 0xc00e, 0x21, 0 - .dw 0x1740, 0xc00e, 0x177f, 0xc00e, 0x21, 0 - .dw 0x17c0, 0xc00e, 0x17ff, 0xc00e, 0x21, 0 - .dw 0x1840, 0xc00e, 0x187f, 0xc00e, 0x21, 0 - .dw 0x18c0, 0xc00e, 0x18ff, 0xc00e, 0x21, 0 - .dw 0x1940, 0xc00e, 0x197f, 0xc00e, 0x21, 0 - .dw 0x19c0, 0xc00e, 0x1fff, 0xc00e, 0x21, 0 - .dw 0x2040, 0xc00e, 0x207f, 0xc00e, 0x21, 0 - .dw 0x20c0, 0xc00e, 0x20ff, 0xc00e, 0x21, 0 - .dw 0x2140, 0xc00e, 0x217f, 0xc00e, 0x21, 0 - .dw 0x21c0, 0xc00e, 0x21ff, 0xc00e, 0x21, 0 - .dw 0x2240, 0xc00e, 0x227f, 0xc00e, 0x21, 0 - .dw 0x22c0, 0xc00e, 0x22ff, 0xc00e, 0x21, 0 - .dw 0x2340, 0xc00e, 0x237f, 0xc00e, 0x21, 0 - .dw 0x23c0, 0xc00e, 0x23ff, 0xc00e, 0x21, 0 - .dw 0x2440, 0xc00e, 0x247f, 0xc00e, 0x21, 0 - .dw 0x24c0, 0xc00e, 0x24ff, 0xc00e, 0x21, 0 - .dw 0x2540, 0xc00e, 0x257f, 0xc00e, 0x21, 0 - .dw 0x25c0, 0xc00e, 0x25ff, 0xc00e, 0x21, 0 - .dw 0x2640, 0xc00e, 0x267f, 0xc00e, 0x21, 0 - .dw 0x26c0, 0xc00e, 0x26ff, 0xc00e, 0x21, 0 - .dw 0x2740, 0xc00e, 0x277f, 0xc00e, 0x21, 0 - .dw 0x27c0, 0xc00e, 0x27ff, 0xc00e, 0x21, 0 - .dw 0x2840, 0xc00e, 0x287f, 0xc00e, 0x21, 0 - .dw 0x28c0, 0xc00e, 0x28ff, 0xc00e, 0x21, 0 - .dw 0x2940, 0xc00e, 0x297f, 0xc00e, 0x21, 0 - .dw 0x29c0, 0xc00e, 0x29ff, 0xc00e, 0x21, 0 - .dw 0x2a40, 0xc00e, 0x2a7f, 0xc00e, 0x21, 0 - .dw 0x2ac0, 0xc00e, 0x2aff, 0xc00e, 0x21, 0 - .dw 0x2b40, 0xc00e, 0x2b7f, 0xc00e, 0x21, 0 - .dw 0x2bc0, 0xc00e, 0x2bff, 0xc00e, 0x21, 0 - .dw 0x2c40, 0xc00e, 0x2c7f, 0xc00e, 0x21, 0 - .dw 0x2cc0, 0xc00e, 0x2cff, 0xc00e, 0x21, 0 - .dw 0x2d40, 0xc00e, 0x2d7f, 0xc00e, 0x21, 0 - .dw 0x2dc0, 0xc00e, 0x2dff, 0xc00e, 0x21, 0 - .dw 0x2e40, 0xc00e, 0x2e7f, 0xc00e, 0x21, 0 - .dw 0x2ec0, 0xc00e, 0x2eff, 0xc00e, 0x21, 0 - .dw 0x2f40, 0xc00e, 0x2f7f, 0xc00e, 0x21, 0 - .dw 0x2fc0, 0xc00e, 0x2fff, 0xc00e, 0x21, 0 - .dw 0x3040, 0xc00e, 0x307f, 0xc00e, 0x21, 0 - .dw 0x30c0, 0xc00e, 0x30ff, 0xc00e, 0x21, 0 - .dw 0x3140, 0xc00e, 0x317f, 0xc00e, 0x21, 0 - .dw 0x31c0, 0xc00e, 0x31ff, 0xc00e, 0x21, 0 - .dw 0x3240, 0xc00e, 0x327f, 0xc00e, 0x21, 0 - .dw 0x32c0, 0xc00e, 0x32ff, 0xc00e, 0x21, 0 - .dw 0x3340, 0xc00e, 0x337f, 0xc00e, 0x21, 0 - .dw 0x33c0, 0xc00e, 0x33ff, 0xc00e, 0x21, 0 - .dw 0x3440, 0xc00e, 0x347f, 0xc00e, 0x21, 0 - .dw 0x34c0, 0xc00e, 0x34ff, 0xc00e, 0x21, 0 - .dw 0x3540, 0xc00e, 0x357f, 0xc00e, 0x21, 0 - .dw 0x35c0, 0xc00e, 0x35ff, 0xc00e, 0x21, 0 - .dw 0x3640, 0xc00e, 0x367f, 0xc00e, 0x21, 0 - .dw 0x36c0, 0xc00e, 0x36ff, 0xc00e, 0x21, 0 - .dw 0x3740, 0xc00e, 0x377f, 0xc00e, 0x21, 0 - .dw 0x37c0, 0xc00e, 0x37ff, 0xc00e, 0x21, 0 - .dw 0x3840, 0xc00e, 0x387f, 0xc00e, 0x21, 0 - .dw 0x38c0, 0xc00e, 0x38ff, 0xc00e, 0x21, 0 - .dw 0x3940, 0xc00e, 0x397f, 0xc00e, 0x21, 0 - .dw 0x39c0, 0xc00e, 0x3fff, 0xc00e, 0x21, 0 - .dw 0x4040, 0xc00e, 0x407f, 0xc00e, 0x21, 0 - .dw 0x40c0, 0xc00e, 0x40ff, 0xc00e, 0x21, 0 - .dw 0x4140, 0xc00e, 0x417f, 0xc00e, 0x21, 0 - .dw 0x41c0, 0xc00e, 0x41ff, 0xc00e, 0x21, 0 - .dw 0x4240, 0xc00e, 0x427f, 0xc00e, 0x21, 0 - .dw 0x42c0, 0xc00e, 0x42ff, 0xc00e, 0x21, 0 - .dw 0x4340, 0xc00e, 0x437f, 0xc00e, 0x21, 0 - .dw 0x43c0, 0xc00e, 0x43ff, 0xc00e, 0x21, 0 - .dw 0x4440, 0xc00e, 0x447f, 0xc00e, 0x21, 0 - .dw 0x44c0, 0xc00e, 0x44ff, 0xc00e, 0x21, 0 - .dw 0x4540, 0xc00e, 0x457f, 0xc00e, 0x21, 0 - .dw 0x45c0, 0xc00e, 0x45ff, 0xc00e, 0x21, 0 - .dw 0x4640, 0xc00e, 0x467f, 0xc00e, 0x21, 0 - .dw 0x46c0, 0xc00e, 0x46ff, 0xc00e, 0x21, 0 - .dw 0x4740, 0xc00e, 0x477f, 0xc00e, 0x21, 0 - .dw 0x47c0, 0xc00e, 0x47ff, 0xc00e, 0x21, 0 - .dw 0x4840, 0xc00e, 0x487f, 0xc00e, 0x21, 0 - .dw 0x48c0, 0xc00e, 0x48ff, 0xc00e, 0x21, 0 - .dw 0x4940, 0xc00e, 0x497f, 0xc00e, 0x21, 0 - .dw 0x49c0, 0xc00e, 0x49ff, 0xc00e, 0x21, 0 - .dw 0x4a40, 0xc00e, 0x4a7f, 0xc00e, 0x21, 0 - .dw 0x4ac0, 0xc00e, 0x4aff, 0xc00e, 0x21, 0 - .dw 0x4b40, 0xc00e, 0x4b7f, 0xc00e, 0x21, 0 - .dw 0x4bc0, 0xc00e, 0x4bff, 0xc00e, 0x21, 0 - .dw 0x4c40, 0xc00e, 0x4c7f, 0xc00e, 0x21, 0 - .dw 0x4cc0, 0xc00e, 0x4cff, 0xc00e, 0x21, 0 - .dw 0x4d40, 0xc00e, 0x4d7f, 0xc00e, 0x21, 0 - .dw 0x4dc0, 0xc00e, 0x4dff, 0xc00e, 0x21, 0 - .dw 0x4e40, 0xc00e, 0x4e7f, 0xc00e, 0x21, 0 - .dw 0x4ec0, 0xc00e, 0x4eff, 0xc00e, 0x21, 0 - .dw 0x4f40, 0xc00e, 0x4f7f, 0xc00e, 0x21, 0 - .dw 0x4fc0, 0xc00e, 0x4fff, 0xc00e, 0x21, 0 - .dw 0x5040, 0xc00e, 0x507f, 0xc00e, 0x21, 0 - .dw 0x50c0, 0xc00e, 0x50ff, 0xc00e, 0x21, 0 - .dw 0x5140, 0xc00e, 0x517f, 0xc00e, 0x21, 0 - .dw 0x51c0, 0xc00e, 0x51ff, 0xc00e, 0x21, 0 - .dw 0x5240, 0xc00e, 0x527f, 0xc00e, 0x21, 0 - .dw 0x52c0, 0xc00e, 0x52ff, 0xc00e, 0x21, 0 - .dw 0x5340, 0xc00e, 0x537f, 0xc00e, 0x21, 0 - .dw 0x53c0, 0xc00e, 0x53ff, 0xc00e, 0x21, 0 - .dw 0x5440, 0xc00e, 0x547f, 0xc00e, 0x21, 0 - .dw 0x54c0, 0xc00e, 0x54ff, 0xc00e, 0x21, 0 - .dw 0x5540, 0xc00e, 0x557f, 0xc00e, 0x21, 0 - .dw 0x55c0, 0xc00e, 0x55ff, 0xc00e, 0x21, 0 - .dw 0x5640, 0xc00e, 0x567f, 0xc00e, 0x21, 0 - .dw 0x56c0, 0xc00e, 0x56ff, 0xc00e, 0x21, 0 - .dw 0x5740, 0xc00e, 0x577f, 0xc00e, 0x21, 0 - .dw 0x57c0, 0xc00e, 0x57ff, 0xc00e, 0x21, 0 - .dw 0x5840, 0xc00e, 0x587f, 0xc00e, 0x21, 0 - .dw 0x58c0, 0xc00e, 0x58ff, 0xc00e, 0x21, 0 - .dw 0x5940, 0xc00e, 0x597f, 0xc00e, 0x21, 0 - .dw 0x59c0, 0xc00e, 0x5fff, 0xc00e, 0x21, 0 - .dw 0x6040, 0xc00e, 0x607f, 0xc00e, 0x21, 0 - .dw 0x60c0, 0xc00e, 0x60ff, 0xc00e, 0x21, 0 - .dw 0x6140, 0xc00e, 0x617f, 0xc00e, 0x21, 0 - .dw 0x61c0, 0xc00e, 0x61ff, 0xc00e, 0x21, 0 - .dw 0x6240, 0xc00e, 0x627f, 0xc00e, 0x21, 0 - .dw 0x62c0, 0xc00e, 0x62ff, 0xc00e, 0x21, 0 - .dw 0x6340, 0xc00e, 0x637f, 0xc00e, 0x21, 0 - .dw 0x63c0, 0xc00e, 0x63ff, 0xc00e, 0x21, 0 - .dw 0x6440, 0xc00e, 0x647f, 0xc00e, 0x21, 0 - .dw 0x64c0, 0xc00e, 0x64ff, 0xc00e, 0x21, 0 - .dw 0x6540, 0xc00e, 0x657f, 0xc00e, 0x21, 0 - .dw 0x65c0, 0xc00e, 0x65ff, 0xc00e, 0x21, 0 - .dw 0x6640, 0xc00e, 0x667f, 0xc00e, 0x21, 0 - .dw 0x66c0, 0xc00e, 0x66ff, 0xc00e, 0x21, 0 - .dw 0x6740, 0xc00e, 0x677f, 0xc00e, 0x21, 0 - .dw 0x67c0, 0xc00e, 0x67ff, 0xc00e, 0x21, 0 - .dw 0x6840, 0xc00e, 0x687f, 0xc00e, 0x21, 0 - .dw 0x68c0, 0xc00e, 0x68ff, 0xc00e, 0x21, 0 - .dw 0x6940, 0xc00e, 0x697f, 0xc00e, 0x21, 0 - .dw 0x69c0, 0xc00e, 0x69ff, 0xc00e, 0x21, 0 - .dw 0x6a40, 0xc00e, 0x6a7f, 0xc00e, 0x21, 0 - .dw 0x6ac0, 0xc00e, 0x6aff, 0xc00e, 0x21, 0 - .dw 0x6b40, 0xc00e, 0x6b7f, 0xc00e, 0x21, 0 - .dw 0x6bc0, 0xc00e, 0x6bff, 0xc00e, 0x21, 0 - .dw 0x6c40, 0xc00e, 0x6c7f, 0xc00e, 0x21, 0 - .dw 0x6cc0, 0xc00e, 0x6cff, 0xc00e, 0x21, 0 - .dw 0x6d40, 0xc00e, 0x6d7f, 0xc00e, 0x21, 0 - .dw 0x6dc0, 0xc00e, 0x6dff, 0xc00e, 0x21, 0 - .dw 0x6e40, 0xc00e, 0x6e7f, 0xc00e, 0x21, 0 - .dw 0x6ec0, 0xc00e, 0x6eff, 0xc00e, 0x21, 0 - .dw 0x6f40, 0xc00e, 0x6f7f, 0xc00e, 0x21, 0 - .dw 0x6fc0, 0xc00e, 0x6fff, 0xc00e, 0x21, 0 - .dw 0x7040, 0xc00e, 0x707f, 0xc00e, 0x21, 0 - .dw 0x70c0, 0xc00e, 0x70ff, 0xc00e, 0x21, 0 - .dw 0x7140, 0xc00e, 0x717f, 0xc00e, 0x21, 0 - .dw 0x71c0, 0xc00e, 0x71ff, 0xc00e, 0x21, 0 - .dw 0x7240, 0xc00e, 0x727f, 0xc00e, 0x21, 0 - .dw 0x72c0, 0xc00e, 0x72ff, 0xc00e, 0x21, 0 - .dw 0x7340, 0xc00e, 0x737f, 0xc00e, 0x21, 0 - .dw 0x73c0, 0xc00e, 0x73ff, 0xc00e, 0x21, 0 - .dw 0x7440, 0xc00e, 0x747f, 0xc00e, 0x21, 0 - .dw 0x74c0, 0xc00e, 0x74ff, 0xc00e, 0x21, 0 - .dw 0x7540, 0xc00e, 0x757f, 0xc00e, 0x21, 0 - .dw 0x75c0, 0xc00e, 0x75ff, 0xc00e, 0x21, 0 - .dw 0x7640, 0xc00e, 0x767f, 0xc00e, 0x21, 0 - .dw 0x76c0, 0xc00e, 0x76ff, 0xc00e, 0x21, 0 - .dw 0x7740, 0xc00e, 0x777f, 0xc00e, 0x21, 0 - .dw 0x77c0, 0xc00e, 0x77ff, 0xc00e, 0x21, 0 - .dw 0x7840, 0xc00e, 0x787f, 0xc00e, 0x21, 0 - .dw 0x78c0, 0xc00e, 0x78ff, 0xc00e, 0x21, 0 - .dw 0x7940, 0xc00e, 0x797f, 0xc00e, 0x21, 0 - .dw 0x79c0, 0xc00e, 0x7fff, 0xc00e, 0x21, 0 - .dw 0x8040, 0xc00e, 0x807f, 0xc00e, 0x21, 0 - .dw 0x80c0, 0xc00e, 0x80ff, 0xc00e, 0x21, 0 - .dw 0x8140, 0xc00e, 0x817f, 0xc00e, 0x21, 0 - .dw 0x81c0, 0xc00e, 0x81ff, 0xc00e, 0x21, 0 - .dw 0x8240, 0xc00e, 0x827f, 0xc00e, 0x21, 0 - .dw 0x82c0, 0xc00e, 0x82ff, 0xc00e, 0x21, 0 - .dw 0x8340, 0xc00e, 0x837f, 0xc00e, 0x21, 0 - .dw 0x83c0, 0xc00e, 0x83ff, 0xc00e, 0x21, 0 - .dw 0x8440, 0xc00e, 0x847f, 0xc00e, 0x21, 0 - .dw 0x84c0, 0xc00e, 0x84ff, 0xc00e, 0x21, 0 - .dw 0x8540, 0xc00e, 0x857f, 0xc00e, 0x21, 0 - .dw 0x85c0, 0xc00e, 0x85ff, 0xc00e, 0x21, 0 - .dw 0x8640, 0xc00e, 0x867f, 0xc00e, 0x21, 0 - .dw 0x86c0, 0xc00e, 0x86ff, 0xc00e, 0x21, 0 - .dw 0x8740, 0xc00e, 0x877f, 0xc00e, 0x21, 0 - .dw 0x87c0, 0xc00e, 0x87ff, 0xc00e, 0x21, 0 - .dw 0x8840, 0xc00e, 0x887f, 0xc00e, 0x21, 0 - .dw 0x88c0, 0xc00e, 0x88ff, 0xc00e, 0x21, 0 - .dw 0x8940, 0xc00e, 0x897f, 0xc00e, 0x21, 0 - .dw 0x89c0, 0xc00e, 0x89ff, 0xc00e, 0x21, 0 - .dw 0x8a40, 0xc00e, 0x8a7f, 0xc00e, 0x21, 0 - .dw 0x8ac0, 0xc00e, 0x8aff, 0xc00e, 0x21, 0 - .dw 0x8b40, 0xc00e, 0x8b7f, 0xc00e, 0x21, 0 - .dw 0x8bc0, 0xc00e, 0x8bff, 0xc00e, 0x21, 0 - .dw 0x8c40, 0xc00e, 0x8c7f, 0xc00e, 0x21, 0 - .dw 0x8cc0, 0xc00e, 0x8cff, 0xc00e, 0x21, 0 - .dw 0x8d40, 0xc00e, 0x8d7f, 0xc00e, 0x21, 0 - .dw 0x8dc0, 0xc00e, 0x8dff, 0xc00e, 0x21, 0 - .dw 0x8e40, 0xc00e, 0x8e7f, 0xc00e, 0x21, 0 - .dw 0x8ec0, 0xc00e, 0x8eff, 0xc00e, 0x21, 0 - .dw 0x8f40, 0xc00e, 0x8f7f, 0xc00e, 0x21, 0 - .dw 0x8fc0, 0xc00e, 0x8fff, 0xc00e, 0x21, 0 - .dw 0x9040, 0xc00e, 0x907f, 0xc00e, 0x21, 0 - .dw 0x90c0, 0xc00e, 0x90ff, 0xc00e, 0x21, 0 - .dw 0x9140, 0xc00e, 0x917f, 0xc00e, 0x21, 0 - .dw 0x91c0, 0xc00e, 0x91ff, 0xc00e, 0x21, 0 - .dw 0x9240, 0xc00e, 0x927f, 0xc00e, 0x21, 0 - .dw 0x92c0, 0xc00e, 0x92ff, 0xc00e, 0x21, 0 - .dw 0x9340, 0xc00e, 0x937f, 0xc00e, 0x21, 0 - .dw 0x93c0, 0xc00e, 0x93ff, 0xc00e, 0x21, 0 - .dw 0x9440, 0xc00e, 0x947f, 0xc00e, 0x21, 0 - .dw 0x94c0, 0xc00e, 0x94ff, 0xc00e, 0x21, 0 - .dw 0x9540, 0xc00e, 0x957f, 0xc00e, 0x21, 0 - .dw 0x95c0, 0xc00e, 0x95ff, 0xc00e, 0x21, 0 - .dw 0x9640, 0xc00e, 0x967f, 0xc00e, 0x21, 0 - .dw 0x96c0, 0xc00e, 0x96ff, 0xc00e, 0x21, 0 - .dw 0x9740, 0xc00e, 0x977f, 0xc00e, 0x21, 0 - .dw 0x97c0, 0xc00e, 0x97ff, 0xc00e, 0x21, 0 - .dw 0x9840, 0xc00e, 0x987f, 0xc00e, 0x21, 0 - .dw 0x98c0, 0xc00e, 0x98ff, 0xc00e, 0x21, 0 - .dw 0x9940, 0xc00e, 0x997f, 0xc00e, 0x21, 0 - .dw 0x99c0, 0xc00e, 0x9fff, 0xc00e, 0x21, 0 - .dw 0xa040, 0xc00e, 0xa07f, 0xc00e, 0x21, 0 - .dw 0xa0c0, 0xc00e, 0xa0ff, 0xc00e, 0x21, 0 - .dw 0xa140, 0xc00e, 0xa17f, 0xc00e, 0x21, 0 - .dw 0xa1c0, 0xc00e, 0xa1ff, 0xc00e, 0x21, 0 - .dw 0xa240, 0xc00e, 0xa27f, 0xc00e, 0x21, 0 - .dw 0xa2c0, 0xc00e, 0xa2ff, 0xc00e, 0x21, 0 - .dw 0xa340, 0xc00e, 0xa37f, 0xc00e, 0x21, 0 - .dw 0xa3c0, 0xc00e, 0xa3ff, 0xc00e, 0x21, 0 - .dw 0xa440, 0xc00e, 0xa47f, 0xc00e, 0x21, 0 - .dw 0xa4c0, 0xc00e, 0xa4ff, 0xc00e, 0x21, 0 - .dw 0xa540, 0xc00e, 0xa57f, 0xc00e, 0x21, 0 - .dw 0xa5c0, 0xc00e, 0xa5ff, 0xc00e, 0x21, 0 - .dw 0xa640, 0xc00e, 0xa67f, 0xc00e, 0x21, 0 - .dw 0xa6c0, 0xc00e, 0xa6ff, 0xc00e, 0x21, 0 - .dw 0xa740, 0xc00e, 0xa77f, 0xc00e, 0x21, 0 - .dw 0xa7c0, 0xc00e, 0xa7ff, 0xc00e, 0x21, 0 - .dw 0xa840, 0xc00e, 0xa87f, 0xc00e, 0x21, 0 - .dw 0xa8c0, 0xc00e, 0xa8ff, 0xc00e, 0x21, 0 - .dw 0xa940, 0xc00e, 0xa97f, 0xc00e, 0x21, 0 - .dw 0xa9c0, 0xc00e, 0xa9ff, 0xc00e, 0x21, 0 - .dw 0xaa40, 0xc00e, 0xaa7f, 0xc00e, 0x21, 0 - .dw 0xaac0, 0xc00e, 0xaaff, 0xc00e, 0x21, 0 - .dw 0xab40, 0xc00e, 0xab7f, 0xc00e, 0x21, 0 - .dw 0xabc0, 0xc00e, 0xabff, 0xc00e, 0x21, 0 - .dw 0xac40, 0xc00e, 0xac7f, 0xc00e, 0x21, 0 - .dw 0xacc0, 0xc00e, 0xacff, 0xc00e, 0x21, 0 - .dw 0xad40, 0xc00e, 0xad7f, 0xc00e, 0x21, 0 - .dw 0xadc0, 0xc00e, 0xadff, 0xc00e, 0x21, 0 - .dw 0xae40, 0xc00e, 0xae7f, 0xc00e, 0x21, 0 - .dw 0xaec0, 0xc00e, 0xaeff, 0xc00e, 0x21, 0 - .dw 0xaf40, 0xc00e, 0xaf7f, 0xc00e, 0x21, 0 - .dw 0xafc0, 0xc00e, 0xafff, 0xc00e, 0x21, 0 - .dw 0xb040, 0xc00e, 0xb07f, 0xc00e, 0x21, 0 - .dw 0xb0c0, 0xc00e, 0xb0ff, 0xc00e, 0x21, 0 - .dw 0xb140, 0xc00e, 0xb17f, 0xc00e, 0x21, 0 - .dw 0xb1c0, 0xc00e, 0xb1ff, 0xc00e, 0x21, 0 - .dw 0xb240, 0xc00e, 0xb27f, 0xc00e, 0x21, 0 - .dw 0xb2c0, 0xc00e, 0xb2ff, 0xc00e, 0x21, 0 - .dw 0xb340, 0xc00e, 0xb37f, 0xc00e, 0x21, 0 - .dw 0xb3c0, 0xc00e, 0xb3ff, 0xc00e, 0x21, 0 - .dw 0xb440, 0xc00e, 0xb47f, 0xc00e, 0x21, 0 - .dw 0xb4c0, 0xc00e, 0xb4ff, 0xc00e, 0x21, 0 - .dw 0xb540, 0xc00e, 0xb57f, 0xc00e, 0x21, 0 - .dw 0xb5c0, 0xc00e, 0xb5ff, 0xc00e, 0x21, 0 - .dw 0xb640, 0xc00e, 0xb67f, 0xc00e, 0x21, 0 - .dw 0xb6c0, 0xc00e, 0xb6ff, 0xc00e, 0x21, 0 - .dw 0xb740, 0xc00e, 0xb77f, 0xc00e, 0x21, 0 - .dw 0xb7c0, 0xc00e, 0xb7ff, 0xc00e, 0x21, 0 - .dw 0xb840, 0xc00e, 0xb87f, 0xc00e, 0x21, 0 - .dw 0xb8c0, 0xc00e, 0xb8ff, 0xc00e, 0x21, 0 - .dw 0xb940, 0xc00e, 0xb97f, 0xc00e, 0x21, 0 - .dw 0xb9c0, 0xc00e, 0xbfff, 0xc00e, 0x21, 0 - .dw 0xc040, 0xc00e, 0xc07f, 0xc00e, 0x21, 0 - .dw 0xc0c0, 0xc00e, 0xc0ff, 0xc00e, 0x21, 0 - .dw 0xc140, 0xc00e, 0xc17f, 0xc00e, 0x21, 0 - .dw 0xc1c0, 0xc00e, 0xc1ff, 0xc00e, 0x21, 0 - .dw 0xc240, 0xc00e, 0xc27f, 0xc00e, 0x21, 0 - .dw 0xc2c0, 0xc00e, 0xc2ff, 0xc00e, 0x21, 0 - .dw 0xc340, 0xc00e, 0xc37f, 0xc00e, 0x21, 0 - .dw 0xc3c0, 0xc00e, 0xc3ff, 0xc00e, 0x21, 0 - .dw 0xc440, 0xc00e, 0xc47f, 0xc00e, 0x21, 0 - .dw 0xc4c0, 0xc00e, 0xc4ff, 0xc00e, 0x21, 0 - .dw 0xc540, 0xc00e, 0xc57f, 0xc00e, 0x21, 0 - .dw 0xc5c0, 0xc00e, 0xc5ff, 0xc00e, 0x21, 0 - .dw 0xc640, 0xc00e, 0xc67f, 0xc00e, 0x21, 0 - .dw 0xc6c0, 0xc00e, 0xc6ff, 0xc00e, 0x21, 0 - .dw 0xc740, 0xc00e, 0xc77f, 0xc00e, 0x21, 0 - .dw 0xc7c0, 0xc00e, 0xc7ff, 0xc00e, 0x21, 0 - .dw 0xc840, 0xc00e, 0xc87f, 0xc00e, 0x21, 0 - .dw 0xc8c0, 0xc00e, 0xc8ff, 0xc00e, 0x21, 0 - .dw 0xc940, 0xc00e, 0xc97f, 0xc00e, 0x21, 0 - .dw 0xc9c0, 0xc00e, 0xc9ff, 0xc00e, 0x21, 0 - .dw 0xca40, 0xc00e, 0xca7f, 0xc00e, 0x21, 0 - .dw 0xcac0, 0xc00e, 0xcaff, 0xc00e, 0x21, 0 - .dw 0xcb40, 0xc00e, 0xcb7f, 0xc00e, 0x21, 0 - .dw 0xcbc0, 0xc00e, 0xcbff, 0xc00e, 0x21, 0 - .dw 0xcc40, 0xc00e, 0xcc7f, 0xc00e, 0x21, 0 - .dw 0xccc0, 0xc00e, 0xccff, 0xc00e, 0x21, 0 - .dw 0xcd40, 0xc00e, 0xcd7f, 0xc00e, 0x21, 0 - .dw 0xcdc0, 0xc00e, 0xcdff, 0xc00e, 0x21, 0 - .dw 0xce40, 0xc00e, 0xce7f, 0xc00e, 0x21, 0 - .dw 0xcec0, 0xc00e, 0xceff, 0xc00e, 0x21, 0 - .dw 0xcf40, 0xc00e, 0xcf7f, 0xc00e, 0x21, 0 - .dw 0xcfc0, 0xc00e, 0xcfff, 0xc00e, 0x21, 0 - .dw 0xd040, 0xc00e, 0xd07f, 0xc00e, 0x21, 0 - .dw 0xd0c0, 0xc00e, 0xd0ff, 0xc00e, 0x21, 0 - .dw 0xd140, 0xc00e, 0xd17f, 0xc00e, 0x21, 0 - .dw 0xd1c0, 0xc00e, 0xd1ff, 0xc00e, 0x21, 0 - .dw 0xd240, 0xc00e, 0xd27f, 0xc00e, 0x21, 0 - .dw 0xd2c0, 0xc00e, 0xd2ff, 0xc00e, 0x21, 0 - .dw 0xd340, 0xc00e, 0xd37f, 0xc00e, 0x21, 0 - .dw 0xd3c0, 0xc00e, 0xd3ff, 0xc00e, 0x21, 0 - .dw 0xd440, 0xc00e, 0xd47f, 0xc00e, 0x21, 0 - .dw 0xd4c0, 0xc00e, 0xd4ff, 0xc00e, 0x21, 0 - .dw 0xd540, 0xc00e, 0xd57f, 0xc00e, 0x21, 0 - .dw 0xd5c0, 0xc00e, 0xd5ff, 0xc00e, 0x21, 0 - .dw 0xd640, 0xc00e, 0xd67f, 0xc00e, 0x21, 0 - .dw 0xd6c0, 0xc00e, 0xd6ff, 0xc00e, 0x21, 0 - .dw 0xd740, 0xc00e, 0xd77f, 0xc00e, 0x21, 0 - .dw 0xd7c0, 0xc00e, 0xd7ff, 0xc00e, 0x21, 0 - .dw 0xd840, 0xc00e, 0xd87f, 0xc00e, 0x21, 0 - .dw 0xd8c0, 0xc00e, 0xd8ff, 0xc00e, 0x21, 0 - .dw 0xd940, 0xc00e, 0xd97f, 0xc00e, 0x21, 0 - .dw 0xd9c0, 0xc00e, 0xdfff, 0xc00e, 0x21, 0 - .dw 0xe040, 0xc00e, 0xe07f, 0xc00e, 0x21, 0 - .dw 0xe0c0, 0xc00e, 0xe0ff, 0xc00e, 0x21, 0 - .dw 0xe140, 0xc00e, 0xe17f, 0xc00e, 0x21, 0 - .dw 0xe1c0, 0xc00e, 0xe1ff, 0xc00e, 0x21, 0 - .dw 0xe240, 0xc00e, 0xe27f, 0xc00e, 0x21, 0 - .dw 0xe2c0, 0xc00e, 0xe2ff, 0xc00e, 0x21, 0 - .dw 0xe340, 0xc00e, 0xe37f, 0xc00e, 0x21, 0 - .dw 0xe3c0, 0xc00e, 0xe3ff, 0xc00e, 0x21, 0 - .dw 0xe440, 0xc00e, 0xe47f, 0xc00e, 0x21, 0 - .dw 0xe4c0, 0xc00e, 0xe4ff, 0xc00e, 0x21, 0 - .dw 0xe540, 0xc00e, 0xe57f, 0xc00e, 0x21, 0 - .dw 0xe5c0, 0xc00e, 0xe5ff, 0xc00e, 0x21, 0 - .dw 0xe640, 0xc00e, 0xe67f, 0xc00e, 0x21, 0 - .dw 0xe6c0, 0xc00e, 0xe6ff, 0xc00e, 0x21, 0 - .dw 0xe740, 0xc00e, 0xe77f, 0xc00e, 0x21, 0 - .dw 0xe7c0, 0xc00e, 0xe7ff, 0xc00e, 0x21, 0 - .dw 0xe840, 0xc00e, 0xe87f, 0xc00e, 0x21, 0 - .dw 0xe8c0, 0xc00e, 0xe8ff, 0xc00e, 0x21, 0 - .dw 0xe940, 0xc00e, 0xe97f, 0xc00e, 0x21, 0 - .dw 0xe9c0, 0xc00e, 0xe9ff, 0xc00e, 0x21, 0 - .dw 0xea40, 0xc00e, 0xea7f, 0xc00e, 0x21, 0 - .dw 0xeac0, 0xc00e, 0xeaff, 0xc00e, 0x21, 0 - .dw 0xeb40, 0xc00e, 0xeb7f, 0xc00e, 0x21, 0 - .dw 0xebc0, 0xc00e, 0xebff, 0xc00e, 0x21, 0 - .dw 0xec40, 0xc00e, 0xec7f, 0xc00e, 0x21, 0 - .dw 0xecc0, 0xc00e, 0xecff, 0xc00e, 0x21, 0 - .dw 0xed40, 0xc00e, 0xed7f, 0xc00e, 0x21, 0 - .dw 0xedc0, 0xc00e, 0xedff, 0xc00e, 0x21, 0 - .dw 0xee40, 0xc00e, 0xee7f, 0xc00e, 0x21, 0 - .dw 0xeec0, 0xc00e, 0xeeff, 0xc00e, 0x21, 0 - .dw 0xef40, 0xc00e, 0xef7f, 0xc00e, 0x21, 0 - .dw 0xefc0, 0xc00e, 0xefff, 0xc00e, 0x21, 0 - .dw 0xf040, 0xc00e, 0xf07f, 0xc00e, 0x21, 0 - .dw 0xf0c0, 0xc00e, 0xf0ff, 0xc00e, 0x21, 0 - .dw 0xf140, 0xc00e, 0xf17f, 0xc00e, 0x21, 0 - .dw 0xf1c0, 0xc00e, 0xf1ff, 0xc00e, 0x21, 0 - .dw 0xf240, 0xc00e, 0xf27f, 0xc00e, 0x21, 0 - .dw 0xf2c0, 0xc00e, 0xf2ff, 0xc00e, 0x21, 0 - .dw 0xf340, 0xc00e, 0xf37f, 0xc00e, 0x21, 0 - .dw 0xf3c0, 0xc00e, 0xf3ff, 0xc00e, 0x21, 0 - .dw 0xf440, 0xc00e, 0xf47f, 0xc00e, 0x21, 0 - .dw 0xf4c0, 0xc00e, 0xf4ff, 0xc00e, 0x21, 0 - .dw 0xf540, 0xc00e, 0xf57f, 0xc00e, 0x21, 0 - .dw 0xf5c0, 0xc00e, 0xf5ff, 0xc00e, 0x21, 0 - .dw 0xf640, 0xc00e, 0xf67f, 0xc00e, 0x21, 0 - .dw 0xf6c0, 0xc00e, 0xf6ff, 0xc00e, 0x21, 0 - .dw 0xf740, 0xc00e, 0xf77f, 0xc00e, 0x21, 0 - .dw 0xf7c0, 0xc00e, 0xf7ff, 0xc00e, 0x21, 0 - .dw 0xf840, 0xc00e, 0xf87f, 0xc00e, 0x21, 0 - .dw 0xf8c0, 0xc00e, 0xf8ff, 0xc00e, 0x21, 0 - .dw 0xf940, 0xc00e, 0xf97f, 0xc00e, 0x21, 0 - .dw 0xf9c0, 0xc00e, 0xffff, 0xc00e, 0x21, 0 - .dw 0x0040, 0xc00f, 0x007f, 0xc00f, 0x21, 0 - .dw 0x00c0, 0xc00f, 0x00ff, 0xc00f, 0x21, 0 - .dw 0x0140, 0xc00f, 0x017f, 0xc00f, 0x21, 0 - .dw 0x01c0, 0xc00f, 0x01ff, 0xc00f, 0x21, 0 - .dw 0x0240, 0xc00f, 0x027f, 0xc00f, 0x21, 0 - .dw 0x02c0, 0xc00f, 0x02ff, 0xc00f, 0x21, 0 - .dw 0x0340, 0xc00f, 0x037f, 0xc00f, 0x21, 0 - .dw 0x03c0, 0xc00f, 0x03ff, 0xc00f, 0x21, 0 - .dw 0x0440, 0xc00f, 0x047f, 0xc00f, 0x21, 0 - .dw 0x04c0, 0xc00f, 0x04ff, 0xc00f, 0x21, 0 - .dw 0x0540, 0xc00f, 0x057f, 0xc00f, 0x21, 0 - .dw 0x05c0, 0xc00f, 0x05ff, 0xc00f, 0x21, 0 - .dw 0x0640, 0xc00f, 0x067f, 0xc00f, 0x21, 0 - .dw 0x06c0, 0xc00f, 0x06ff, 0xc00f, 0x21, 0 - .dw 0x0740, 0xc00f, 0x077f, 0xc00f, 0x21, 0 - .dw 0x07c0, 0xc00f, 0x07ff, 0xc00f, 0x21, 0 - .dw 0x0840, 0xc00f, 0x087f, 0xc00f, 0x21, 0 - .dw 0x08c0, 0xc00f, 0x08ff, 0xc00f, 0x21, 0 - .dw 0x0940, 0xc00f, 0x097f, 0xc00f, 0x21, 0 - .dw 0x09c0, 0xc00f, 0x09ff, 0xc00f, 0x21, 0 - .dw 0x0a40, 0xc00f, 0x0a7f, 0xc00f, 0x21, 0 - .dw 0x0ac0, 0xc00f, 0x0aff, 0xc00f, 0x21, 0 - .dw 0x0b40, 0xc00f, 0x0b7f, 0xc00f, 0x21, 0 - .dw 0x0bc0, 0xc00f, 0x0bff, 0xc00f, 0x21, 0 - .dw 0x0c40, 0xc00f, 0x0c7f, 0xc00f, 0x21, 0 - .dw 0x0cc0, 0xc00f, 0x0cff, 0xc00f, 0x21, 0 - .dw 0x0d40, 0xc00f, 0x0d7f, 0xc00f, 0x21, 0 - .dw 0x0dc0, 0xc00f, 0x0dff, 0xc00f, 0x21, 0 - .dw 0x0e40, 0xc00f, 0x0e7f, 0xc00f, 0x21, 0 - .dw 0x0ec0, 0xc00f, 0x0eff, 0xc00f, 0x21, 0 - .dw 0x0f40, 0xc00f, 0x0f7f, 0xc00f, 0x21, 0 - .dw 0x0fc0, 0xc00f, 0x0fff, 0xc00f, 0x21, 0 - .dw 0x1040, 0xc00f, 0x107f, 0xc00f, 0x21, 0 - .dw 0x10c0, 0xc00f, 0x10ff, 0xc00f, 0x21, 0 - .dw 0x1140, 0xc00f, 0x117f, 0xc00f, 0x21, 0 - .dw 0x11c0, 0xc00f, 0x11ff, 0xc00f, 0x21, 0 - .dw 0x1240, 0xc00f, 0x127f, 0xc00f, 0x21, 0 - .dw 0x12c0, 0xc00f, 0x12ff, 0xc00f, 0x21, 0 - .dw 0x1340, 0xc00f, 0x137f, 0xc00f, 0x21, 0 - .dw 0x13c0, 0xc00f, 0x13ff, 0xc00f, 0x21, 0 - .dw 0x1440, 0xc00f, 0x147f, 0xc00f, 0x21, 0 - .dw 0x14c0, 0xc00f, 0x14ff, 0xc00f, 0x21, 0 - .dw 0x1540, 0xc00f, 0x157f, 0xc00f, 0x21, 0 - .dw 0x15c0, 0xc00f, 0x15ff, 0xc00f, 0x21, 0 - .dw 0x1640, 0xc00f, 0x167f, 0xc00f, 0x21, 0 - .dw 0x16c0, 0xc00f, 0x16ff, 0xc00f, 0x21, 0 - .dw 0x1740, 0xc00f, 0x177f, 0xc00f, 0x21, 0 - .dw 0x17c0, 0xc00f, 0x17ff, 0xc00f, 0x21, 0 - .dw 0x1840, 0xc00f, 0x187f, 0xc00f, 0x21, 0 - .dw 0x18c0, 0xc00f, 0x18ff, 0xc00f, 0x21, 0 - .dw 0x1940, 0xc00f, 0x197f, 0xc00f, 0x21, 0 - .dw 0x19c0, 0xc00f, 0x1fff, 0xc00f, 0x21, 0 - .dw 0x2040, 0xc00f, 0x207f, 0xc00f, 0x21, 0 - .dw 0x20c0, 0xc00f, 0x20ff, 0xc00f, 0x21, 0 - .dw 0x2140, 0xc00f, 0x217f, 0xc00f, 0x21, 0 - .dw 0x21c0, 0xc00f, 0x21ff, 0xc00f, 0x21, 0 - .dw 0x2240, 0xc00f, 0x227f, 0xc00f, 0x21, 0 - .dw 0x22c0, 0xc00f, 0x22ff, 0xc00f, 0x21, 0 - .dw 0x2340, 0xc00f, 0x237f, 0xc00f, 0x21, 0 - .dw 0x23c0, 0xc00f, 0x23ff, 0xc00f, 0x21, 0 - .dw 0x2440, 0xc00f, 0x247f, 0xc00f, 0x21, 0 - .dw 0x24c0, 0xc00f, 0x24ff, 0xc00f, 0x21, 0 - .dw 0x2540, 0xc00f, 0x257f, 0xc00f, 0x21, 0 - .dw 0x25c0, 0xc00f, 0x25ff, 0xc00f, 0x21, 0 - .dw 0x2640, 0xc00f, 0x267f, 0xc00f, 0x21, 0 - .dw 0x26c0, 0xc00f, 0x26ff, 0xc00f, 0x21, 0 - .dw 0x2740, 0xc00f, 0x277f, 0xc00f, 0x21, 0 - .dw 0x27c0, 0xc00f, 0x27ff, 0xc00f, 0x21, 0 - .dw 0x2840, 0xc00f, 0x287f, 0xc00f, 0x21, 0 - .dw 0x28c0, 0xc00f, 0x28ff, 0xc00f, 0x21, 0 - .dw 0x2940, 0xc00f, 0x297f, 0xc00f, 0x21, 0 - .dw 0x29c0, 0xc00f, 0x29ff, 0xc00f, 0x21, 0 - .dw 0x2a40, 0xc00f, 0x2a7f, 0xc00f, 0x21, 0 - .dw 0x2ac0, 0xc00f, 0x2aff, 0xc00f, 0x21, 0 - .dw 0x2b40, 0xc00f, 0x2b7f, 0xc00f, 0x21, 0 - .dw 0x2bc0, 0xc00f, 0x2bff, 0xc00f, 0x21, 0 - .dw 0x2c40, 0xc00f, 0x2c7f, 0xc00f, 0x21, 0 - .dw 0x2cc0, 0xc00f, 0x2cff, 0xc00f, 0x21, 0 - .dw 0x2d40, 0xc00f, 0x2d7f, 0xc00f, 0x21, 0 - .dw 0x2dc0, 0xc00f, 0x2dff, 0xc00f, 0x21, 0 - .dw 0x2e40, 0xc00f, 0x2e7f, 0xc00f, 0x21, 0 - .dw 0x2ec0, 0xc00f, 0x2eff, 0xc00f, 0x21, 0 - .dw 0x2f40, 0xc00f, 0x2f7f, 0xc00f, 0x21, 0 - .dw 0x2fc0, 0xc00f, 0x2fff, 0xc00f, 0x21, 0 - .dw 0x3040, 0xc00f, 0x307f, 0xc00f, 0x21, 0 - .dw 0x30c0, 0xc00f, 0x30ff, 0xc00f, 0x21, 0 - .dw 0x3140, 0xc00f, 0x317f, 0xc00f, 0x21, 0 - .dw 0x31c0, 0xc00f, 0x31ff, 0xc00f, 0x21, 0 - .dw 0x3240, 0xc00f, 0x327f, 0xc00f, 0x21, 0 - .dw 0x32c0, 0xc00f, 0x32ff, 0xc00f, 0x21, 0 - .dw 0x3340, 0xc00f, 0x337f, 0xc00f, 0x21, 0 - .dw 0x33c0, 0xc00f, 0x33ff, 0xc00f, 0x21, 0 - .dw 0x3440, 0xc00f, 0x347f, 0xc00f, 0x21, 0 - .dw 0x34c0, 0xc00f, 0x34ff, 0xc00f, 0x21, 0 - .dw 0x3540, 0xc00f, 0x357f, 0xc00f, 0x21, 0 - .dw 0x35c0, 0xc00f, 0x35ff, 0xc00f, 0x21, 0 - .dw 0x3640, 0xc00f, 0x367f, 0xc00f, 0x21, 0 - .dw 0x36c0, 0xc00f, 0x36ff, 0xc00f, 0x21, 0 - .dw 0x3740, 0xc00f, 0x377f, 0xc00f, 0x21, 0 - .dw 0x37c0, 0xc00f, 0x37ff, 0xc00f, 0x21, 0 - .dw 0x3840, 0xc00f, 0x387f, 0xc00f, 0x21, 0 - .dw 0x38c0, 0xc00f, 0x38ff, 0xc00f, 0x21, 0 - .dw 0x3940, 0xc00f, 0x397f, 0xc00f, 0x21, 0 - .dw 0x39c0, 0xc00f, 0xffff, 0xc00f, 0x21, 0 - .dw 0x1a00, 0xc010, 0x1fff, 0xc010, 0x21, 0 - .dw 0x3a00, 0xc010, 0x3fff, 0xc010, 0x21, 0 - .dw 0x5a00, 0xc010, 0x5fff, 0xc010, 0x21, 0 - .dw 0x7a00, 0xc010, 0x7fff, 0xc010, 0x21, 0 - .dw 0x9a00, 0xc010, 0x9fff, 0xc010, 0x21, 0 - .dw 0xba00, 0xc010, 0xbfff, 0xc010, 0x21, 0 - .dw 0xda00, 0xc010, 0xdfff, 0xc010, 0x21, 0 - .dw 0xfa00, 0xc010, 0xffff, 0xc010, 0x21, 0 - .dw 0x1a00, 0xc011, 0x1fff, 0xc011, 0x21, 0 - .dw 0x3a00, 0xc011, 0x3fff, 0xc011, 0x21, 0 - .dw 0x5a00, 0xc011, 0x5fff, 0xc011, 0x21, 0 - .dw 0x7a00, 0xc011, 0x7fff, 0xc011, 0x21, 0 - .dw 0x9a00, 0xc011, 0x9fff, 0xc011, 0x21, 0 - .dw 0xba00, 0xc011, 0xbfff, 0xc011, 0x21, 0 - .dw 0xda00, 0xc011, 0xdfff, 0xc011, 0x21, 0 - .dw 0xfa00, 0xc011, 0xffff, 0xc011, 0x21, 0 - .dw 0x1a00, 0xc012, 0x1fff, 0xc012, 0x21, 0 - .dw 0x3a00, 0xc012, 0x3fff, 0xc012, 0x21, 0 - .dw 0x5a00, 0xc012, 0x5fff, 0xc012, 0x21, 0 - .dw 0x7a00, 0xc012, 0x7fff, 0xc012, 0x21, 0 - .dw 0x9a00, 0xc012, 0x9fff, 0xc012, 0x21, 0 - .dw 0xba00, 0xc012, 0xbfff, 0xc012, 0x21, 0 - .dw 0xda00, 0xc012, 0xdfff, 0xc012, 0x21, 0 - .dw 0xfa00, 0xc012, 0xffff, 0xc013, 0x21, 0 - .dw 0x1a00, 0xc014, 0x1fff, 0xc014, 0x21, 0 - .dw 0x3a00, 0xc014, 0x3fff, 0xc014, 0x21, 0 - .dw 0x5a00, 0xc014, 0x5fff, 0xc014, 0x21, 0 - .dw 0x7a00, 0xc014, 0x7fff, 0xc014, 0x21, 0 - .dw 0x9a00, 0xc014, 0x9fff, 0xc014, 0x21, 0 - .dw 0xba00, 0xc014, 0xbfff, 0xc014, 0x21, 0 - .dw 0xda00, 0xc014, 0xdfff, 0xc014, 0x21, 0 - .dw 0xfa00, 0xc014, 0xffff, 0xc014, 0x21, 0 - .dw 0x1a00, 0xc015, 0x1fff, 0xc015, 0x21, 0 - .dw 0x3a00, 0xc015, 0x3fff, 0xc015, 0x21, 0 - .dw 0x5a00, 0xc015, 0x5fff, 0xc015, 0x21, 0 - .dw 0x7a00, 0xc015, 0x7fff, 0xc015, 0x21, 0 - .dw 0x9a00, 0xc015, 0x9fff, 0xc015, 0x21, 0 - .dw 0xba00, 0xc015, 0xbfff, 0xc015, 0x21, 0 - .dw 0xda00, 0xc015, 0xdfff, 0xc015, 0x21, 0 - .dw 0xfa00, 0xc015, 0xffff, 0xc015, 0x21, 0 - .dw 0x1a00, 0xc016, 0x1fff, 0xc016, 0x21, 0 - .dw 0x3a00, 0xc016, 0x3fff, 0xc016, 0x21, 0 - .dw 0x5a00, 0xc016, 0x5fff, 0xc016, 0x21, 0 - .dw 0x7a00, 0xc016, 0x7fff, 0xc016, 0x21, 0 - .dw 0x9a00, 0xc016, 0x9fff, 0xc016, 0x21, 0 - .dw 0xba00, 0xc016, 0xbfff, 0xc016, 0x21, 0 - .dw 0xda00, 0xc016, 0xdfff, 0xc016, 0x21, 0 - .dw 0xfa00, 0xc016, 0xffff, 0xc016, 0x21, 0 - .dw 0x1a00, 0xc017, 0x1fff, 0xc017, 0x21, 0 - .dw 0x3a00, 0xc017, 0x1fff, 0xc018, 0x21, 0 - .dw 0x2040, 0xc018, 0x207f, 0xc018, 0x21, 0 - .dw 0x20c0, 0xc018, 0x20ff, 0xc018, 0x21, 0 - .dw 0x2140, 0xc018, 0x217f, 0xc018, 0x21, 0 - .dw 0x21c0, 0xc018, 0x21ff, 0xc018, 0x21, 0 - .dw 0x2240, 0xc018, 0x227f, 0xc018, 0x21, 0 - .dw 0x22c0, 0xc018, 0x22ff, 0xc018, 0x21, 0 - .dw 0x2340, 0xc018, 0x237f, 0xc018, 0x21, 0 - .dw 0x23c0, 0xc018, 0x23ff, 0xc018, 0x21, 0 - .dw 0x2440, 0xc018, 0x247f, 0xc018, 0x21, 0 - .dw 0x24c0, 0xc018, 0x24ff, 0xc018, 0x21, 0 - .dw 0x2540, 0xc018, 0x257f, 0xc018, 0x21, 0 - .dw 0x25c0, 0xc018, 0x25ff, 0xc018, 0x21, 0 - .dw 0x2640, 0xc018, 0x267f, 0xc018, 0x21, 0 - .dw 0x26c0, 0xc018, 0x26ff, 0xc018, 0x21, 0 - .dw 0x2740, 0xc018, 0x277f, 0xc018, 0x21, 0 - .dw 0x27c0, 0xc018, 0x27ff, 0xc018, 0x21, 0 - .dw 0x2840, 0xc018, 0x287f, 0xc018, 0x21, 0 - .dw 0x28c0, 0xc018, 0x28ff, 0xc018, 0x21, 0 - .dw 0x2940, 0xc018, 0x297f, 0xc018, 0x21, 0 - .dw 0x29c0, 0xc018, 0x29ff, 0xc018, 0x21, 0 - .dw 0x2a40, 0xc018, 0x2a7f, 0xc018, 0x21, 0 - .dw 0x2ac0, 0xc018, 0x2aff, 0xc018, 0x21, 0 - .dw 0x2b40, 0xc018, 0x2b7f, 0xc018, 0x21, 0 - .dw 0x2bc0, 0xc018, 0x2bff, 0xc018, 0x21, 0 - .dw 0x2c40, 0xc018, 0x2c7f, 0xc018, 0x21, 0 - .dw 0x2cc0, 0xc018, 0x2cff, 0xc018, 0x21, 0 - .dw 0x2d40, 0xc018, 0x2d7f, 0xc018, 0x21, 0 - .dw 0x2dc0, 0xc018, 0x2dff, 0xc018, 0x21, 0 - .dw 0x2e40, 0xc018, 0x2e7f, 0xc018, 0x21, 0 - .dw 0x2ec0, 0xc018, 0x2eff, 0xc018, 0x21, 0 - .dw 0x2f40, 0xc018, 0x2f7f, 0xc018, 0x21, 0 - .dw 0x2fc0, 0xc018, 0x2fff, 0xc018, 0x21, 0 - .dw 0x3040, 0xc018, 0x307f, 0xc018, 0x21, 0 - .dw 0x30c0, 0xc018, 0x30ff, 0xc018, 0x21, 0 - .dw 0x3140, 0xc018, 0x317f, 0xc018, 0x21, 0 - .dw 0x31c0, 0xc018, 0x31ff, 0xc018, 0x21, 0 - .dw 0x3240, 0xc018, 0x327f, 0xc018, 0x21, 0 - .dw 0x32c0, 0xc018, 0x32ff, 0xc018, 0x21, 0 - .dw 0x3340, 0xc018, 0x337f, 0xc018, 0x21, 0 - .dw 0x33c0, 0xc018, 0x33ff, 0xc018, 0x21, 0 - .dw 0x3440, 0xc018, 0x347f, 0xc018, 0x21, 0 - .dw 0x34c0, 0xc018, 0x34ff, 0xc018, 0x21, 0 - .dw 0x3540, 0xc018, 0x357f, 0xc018, 0x21, 0 - .dw 0x35c0, 0xc018, 0x35ff, 0xc018, 0x21, 0 - .dw 0x3640, 0xc018, 0x367f, 0xc018, 0x21, 0 - .dw 0x36c0, 0xc018, 0x36ff, 0xc018, 0x21, 0 - .dw 0x3740, 0xc018, 0x377f, 0xc018, 0x21, 0 - .dw 0x37c0, 0xc018, 0x37ff, 0xc018, 0x21, 0 - .dw 0x3840, 0xc018, 0x387f, 0xc018, 0x21, 0 - .dw 0x38c0, 0xc018, 0x38ff, 0xc018, 0x21, 0 - .dw 0x3940, 0xc018, 0x397f, 0xc018, 0x21, 0 - .dw 0x39c0, 0xc018, 0x5fff, 0xc018, 0x21, 0 - .dw 0x6040, 0xc018, 0x607f, 0xc018, 0x21, 0 - .dw 0x60c0, 0xc018, 0x60ff, 0xc018, 0x21, 0 - .dw 0x6140, 0xc018, 0x617f, 0xc018, 0x21, 0 - .dw 0x61c0, 0xc018, 0x61ff, 0xc018, 0x21, 0 - .dw 0x6240, 0xc018, 0x627f, 0xc018, 0x21, 0 - .dw 0x62c0, 0xc018, 0x62ff, 0xc018, 0x21, 0 - .dw 0x6340, 0xc018, 0x637f, 0xc018, 0x21, 0 - .dw 0x63c0, 0xc018, 0x63ff, 0xc018, 0x21, 0 - .dw 0x6440, 0xc018, 0x647f, 0xc018, 0x21, 0 - .dw 0x64c0, 0xc018, 0x64ff, 0xc018, 0x21, 0 - .dw 0x6540, 0xc018, 0x657f, 0xc018, 0x21, 0 - .dw 0x65c0, 0xc018, 0x65ff, 0xc018, 0x21, 0 - .dw 0x6640, 0xc018, 0x667f, 0xc018, 0x21, 0 - .dw 0x66c0, 0xc018, 0x66ff, 0xc018, 0x21, 0 - .dw 0x6740, 0xc018, 0x677f, 0xc018, 0x21, 0 - .dw 0x67c0, 0xc018, 0x67ff, 0xc018, 0x21, 0 - .dw 0x6840, 0xc018, 0x687f, 0xc018, 0x21, 0 - .dw 0x68c0, 0xc018, 0x68ff, 0xc018, 0x21, 0 - .dw 0x6940, 0xc018, 0x697f, 0xc018, 0x21, 0 - .dw 0x69c0, 0xc018, 0x69ff, 0xc018, 0x21, 0 - .dw 0x6a40, 0xc018, 0x6a7f, 0xc018, 0x21, 0 - .dw 0x6ac0, 0xc018, 0x6aff, 0xc018, 0x21, 0 - .dw 0x6b40, 0xc018, 0x6b7f, 0xc018, 0x21, 0 - .dw 0x6bc0, 0xc018, 0x6bff, 0xc018, 0x21, 0 - .dw 0x6c40, 0xc018, 0x6c7f, 0xc018, 0x21, 0 - .dw 0x6cc0, 0xc018, 0x6cff, 0xc018, 0x21, 0 - .dw 0x6d40, 0xc018, 0x6d7f, 0xc018, 0x21, 0 - .dw 0x6dc0, 0xc018, 0x6dff, 0xc018, 0x21, 0 - .dw 0x6e40, 0xc018, 0x6e7f, 0xc018, 0x21, 0 - .dw 0x6ec0, 0xc018, 0x6eff, 0xc018, 0x21, 0 - .dw 0x6f40, 0xc018, 0x6f7f, 0xc018, 0x21, 0 - .dw 0x6fc0, 0xc018, 0x6fff, 0xc018, 0x21, 0 - .dw 0x7040, 0xc018, 0x707f, 0xc018, 0x21, 0 - .dw 0x70c0, 0xc018, 0x70ff, 0xc018, 0x21, 0 - .dw 0x7140, 0xc018, 0x717f, 0xc018, 0x21, 0 - .dw 0x71c0, 0xc018, 0x71ff, 0xc018, 0x21, 0 - .dw 0x7240, 0xc018, 0x727f, 0xc018, 0x21, 0 - .dw 0x72c0, 0xc018, 0x72ff, 0xc018, 0x21, 0 - .dw 0x7340, 0xc018, 0x737f, 0xc018, 0x21, 0 - .dw 0x73c0, 0xc018, 0x73ff, 0xc018, 0x21, 0 - .dw 0x7440, 0xc018, 0x747f, 0xc018, 0x21, 0 - .dw 0x74c0, 0xc018, 0x74ff, 0xc018, 0x21, 0 - .dw 0x7540, 0xc018, 0x757f, 0xc018, 0x21, 0 - .dw 0x75c0, 0xc018, 0x75ff, 0xc018, 0x21, 0 - .dw 0x7640, 0xc018, 0x767f, 0xc018, 0x21, 0 - .dw 0x76c0, 0xc018, 0x76ff, 0xc018, 0x21, 0 - .dw 0x7740, 0xc018, 0x777f, 0xc018, 0x21, 0 - .dw 0x77c0, 0xc018, 0x77ff, 0xc018, 0x21, 0 - .dw 0x7840, 0xc018, 0x787f, 0xc018, 0x21, 0 - .dw 0x78c0, 0xc018, 0x78ff, 0xc018, 0x21, 0 - .dw 0x7940, 0xc018, 0x797f, 0xc018, 0x21, 0 - .dw 0x79c0, 0xc018, 0x9fff, 0xc018, 0x21, 0 - .dw 0xa040, 0xc018, 0xa07f, 0xc018, 0x21, 0 - .dw 0xa0c0, 0xc018, 0xa0ff, 0xc018, 0x21, 0 - .dw 0xa140, 0xc018, 0xa17f, 0xc018, 0x21, 0 - .dw 0xa1c0, 0xc018, 0xa1ff, 0xc018, 0x21, 0 - .dw 0xa240, 0xc018, 0xa27f, 0xc018, 0x21, 0 - .dw 0xa2c0, 0xc018, 0xa2ff, 0xc018, 0x21, 0 - .dw 0xa340, 0xc018, 0xa37f, 0xc018, 0x21, 0 - .dw 0xa3c0, 0xc018, 0xa3ff, 0xc018, 0x21, 0 - .dw 0xa440, 0xc018, 0xa47f, 0xc018, 0x21, 0 - .dw 0xa4c0, 0xc018, 0xa4ff, 0xc018, 0x21, 0 - .dw 0xa540, 0xc018, 0xa57f, 0xc018, 0x21, 0 - .dw 0xa5c0, 0xc018, 0xa5ff, 0xc018, 0x21, 0 - .dw 0xa640, 0xc018, 0xa67f, 0xc018, 0x21, 0 - .dw 0xa6c0, 0xc018, 0xa6ff, 0xc018, 0x21, 0 - .dw 0xa740, 0xc018, 0xa77f, 0xc018, 0x21, 0 - .dw 0xa7c0, 0xc018, 0xa7ff, 0xc018, 0x21, 0 - .dw 0xa840, 0xc018, 0xa87f, 0xc018, 0x21, 0 - .dw 0xa8c0, 0xc018, 0xa8ff, 0xc018, 0x21, 0 - .dw 0xa940, 0xc018, 0xa97f, 0xc018, 0x21, 0 - .dw 0xa9c0, 0xc018, 0xa9ff, 0xc018, 0x21, 0 - .dw 0xaa40, 0xc018, 0xaa7f, 0xc018, 0x21, 0 - .dw 0xaac0, 0xc018, 0xaaff, 0xc018, 0x21, 0 - .dw 0xab40, 0xc018, 0xab7f, 0xc018, 0x21, 0 - .dw 0xabc0, 0xc018, 0xabff, 0xc018, 0x21, 0 - .dw 0xac40, 0xc018, 0xac7f, 0xc018, 0x21, 0 - .dw 0xacc0, 0xc018, 0xacff, 0xc018, 0x21, 0 - .dw 0xad40, 0xc018, 0xad7f, 0xc018, 0x21, 0 - .dw 0xadc0, 0xc018, 0xadff, 0xc018, 0x21, 0 - .dw 0xae40, 0xc018, 0xae7f, 0xc018, 0x21, 0 - .dw 0xaec0, 0xc018, 0xaeff, 0xc018, 0x21, 0 - .dw 0xaf40, 0xc018, 0xaf7f, 0xc018, 0x21, 0 - .dw 0xafc0, 0xc018, 0xafff, 0xc018, 0x21, 0 - .dw 0xb040, 0xc018, 0xb07f, 0xc018, 0x21, 0 - .dw 0xb0c0, 0xc018, 0xb0ff, 0xc018, 0x21, 0 - .dw 0xb140, 0xc018, 0xb17f, 0xc018, 0x21, 0 - .dw 0xb1c0, 0xc018, 0xb1ff, 0xc018, 0x21, 0 - .dw 0xb240, 0xc018, 0xb27f, 0xc018, 0x21, 0 - .dw 0xb2c0, 0xc018, 0xb2ff, 0xc018, 0x21, 0 - .dw 0xb340, 0xc018, 0xb37f, 0xc018, 0x21, 0 - .dw 0xb3c0, 0xc018, 0xb3ff, 0xc018, 0x21, 0 - .dw 0xb440, 0xc018, 0xb47f, 0xc018, 0x21, 0 - .dw 0xb4c0, 0xc018, 0xb4ff, 0xc018, 0x21, 0 - .dw 0xb540, 0xc018, 0xb57f, 0xc018, 0x21, 0 - .dw 0xb5c0, 0xc018, 0xb5ff, 0xc018, 0x21, 0 - .dw 0xb640, 0xc018, 0xb67f, 0xc018, 0x21, 0 - .dw 0xb6c0, 0xc018, 0xb6ff, 0xc018, 0x21, 0 - .dw 0xb740, 0xc018, 0xb77f, 0xc018, 0x21, 0 - .dw 0xb7c0, 0xc018, 0xb7ff, 0xc018, 0x21, 0 - .dw 0xb840, 0xc018, 0xb87f, 0xc018, 0x21, 0 - .dw 0xb8c0, 0xc018, 0xb8ff, 0xc018, 0x21, 0 - .dw 0xb940, 0xc018, 0xb97f, 0xc018, 0x21, 0 - .dw 0xb9c0, 0xc018, 0xdfff, 0xc018, 0x21, 0 - .dw 0xe040, 0xc018, 0xe07f, 0xc018, 0x21, 0 - .dw 0xe0c0, 0xc018, 0xe0ff, 0xc018, 0x21, 0 - .dw 0xe140, 0xc018, 0xe17f, 0xc018, 0x21, 0 - .dw 0xe1c0, 0xc018, 0xe1ff, 0xc018, 0x21, 0 - .dw 0xe240, 0xc018, 0xe27f, 0xc018, 0x21, 0 - .dw 0xe2c0, 0xc018, 0xe2ff, 0xc018, 0x21, 0 - .dw 0xe340, 0xc018, 0xe37f, 0xc018, 0x21, 0 - .dw 0xe3c0, 0xc018, 0xe3ff, 0xc018, 0x21, 0 - .dw 0xe440, 0xc018, 0xe47f, 0xc018, 0x21, 0 - .dw 0xe4c0, 0xc018, 0xe4ff, 0xc018, 0x21, 0 - .dw 0xe540, 0xc018, 0xe57f, 0xc018, 0x21, 0 - .dw 0xe5c0, 0xc018, 0xe5ff, 0xc018, 0x21, 0 - .dw 0xe640, 0xc018, 0xe67f, 0xc018, 0x21, 0 - .dw 0xe6c0, 0xc018, 0xe6ff, 0xc018, 0x21, 0 - .dw 0xe740, 0xc018, 0xe77f, 0xc018, 0x21, 0 - .dw 0xe7c0, 0xc018, 0xe7ff, 0xc018, 0x21, 0 - .dw 0xe840, 0xc018, 0xe87f, 0xc018, 0x21, 0 - .dw 0xe8c0, 0xc018, 0xe8ff, 0xc018, 0x21, 0 - .dw 0xe940, 0xc018, 0xe97f, 0xc018, 0x21, 0 - .dw 0xe9c0, 0xc018, 0xe9ff, 0xc018, 0x21, 0 - .dw 0xea40, 0xc018, 0xea7f, 0xc018, 0x21, 0 - .dw 0xeac0, 0xc018, 0xeaff, 0xc018, 0x21, 0 - .dw 0xeb40, 0xc018, 0xeb7f, 0xc018, 0x21, 0 - .dw 0xebc0, 0xc018, 0xebff, 0xc018, 0x21, 0 - .dw 0xec40, 0xc018, 0xec7f, 0xc018, 0x21, 0 - .dw 0xecc0, 0xc018, 0xecff, 0xc018, 0x21, 0 - .dw 0xed40, 0xc018, 0xed7f, 0xc018, 0x21, 0 - .dw 0xedc0, 0xc018, 0xedff, 0xc018, 0x21, 0 - .dw 0xee40, 0xc018, 0xee7f, 0xc018, 0x21, 0 - .dw 0xeec0, 0xc018, 0xeeff, 0xc018, 0x21, 0 - .dw 0xef40, 0xc018, 0xef7f, 0xc018, 0x21, 0 - .dw 0xefc0, 0xc018, 0xefff, 0xc018, 0x21, 0 - .dw 0xf040, 0xc018, 0xf07f, 0xc018, 0x21, 0 - .dw 0xf0c0, 0xc018, 0xf0ff, 0xc018, 0x21, 0 - .dw 0xf140, 0xc018, 0xf17f, 0xc018, 0x21, 0 - .dw 0xf1c0, 0xc018, 0xf1ff, 0xc018, 0x21, 0 - .dw 0xf240, 0xc018, 0xf27f, 0xc018, 0x21, 0 - .dw 0xf2c0, 0xc018, 0xf2ff, 0xc018, 0x21, 0 - .dw 0xf340, 0xc018, 0xf37f, 0xc018, 0x21, 0 - .dw 0xf3c0, 0xc018, 0xf3ff, 0xc018, 0x21, 0 - .dw 0xf440, 0xc018, 0xf47f, 0xc018, 0x21, 0 - .dw 0xf4c0, 0xc018, 0xf4ff, 0xc018, 0x21, 0 - .dw 0xf540, 0xc018, 0xf57f, 0xc018, 0x21, 0 - .dw 0xf5c0, 0xc018, 0xf5ff, 0xc018, 0x21, 0 - .dw 0xf640, 0xc018, 0xf67f, 0xc018, 0x21, 0 - .dw 0xf6c0, 0xc018, 0xf6ff, 0xc018, 0x21, 0 - .dw 0xf740, 0xc018, 0xf77f, 0xc018, 0x21, 0 - .dw 0xf7c0, 0xc018, 0xf7ff, 0xc018, 0x21, 0 - .dw 0xf840, 0xc018, 0xf87f, 0xc018, 0x21, 0 - .dw 0xf8c0, 0xc018, 0xf8ff, 0xc018, 0x21, 0 - .dw 0xf940, 0xc018, 0xf97f, 0xc018, 0x21, 0 - .dw 0xf9c0, 0xc018, 0x1fff, 0xc019, 0x21, 0 - .dw 0x2040, 0xc019, 0x207f, 0xc019, 0x21, 0 - .dw 0x20c0, 0xc019, 0x20ff, 0xc019, 0x21, 0 - .dw 0x2140, 0xc019, 0x217f, 0xc019, 0x21, 0 - .dw 0x21c0, 0xc019, 0x21ff, 0xc019, 0x21, 0 - .dw 0x2240, 0xc019, 0x227f, 0xc019, 0x21, 0 - .dw 0x22c0, 0xc019, 0x22ff, 0xc019, 0x21, 0 - .dw 0x2340, 0xc019, 0x237f, 0xc019, 0x21, 0 - .dw 0x23c0, 0xc019, 0x23ff, 0xc019, 0x21, 0 - .dw 0x2440, 0xc019, 0x247f, 0xc019, 0x21, 0 - .dw 0x24c0, 0xc019, 0x24ff, 0xc019, 0x21, 0 - .dw 0x2540, 0xc019, 0x257f, 0xc019, 0x21, 0 - .dw 0x25c0, 0xc019, 0x25ff, 0xc019, 0x21, 0 - .dw 0x2640, 0xc019, 0x267f, 0xc019, 0x21, 0 - .dw 0x26c0, 0xc019, 0x26ff, 0xc019, 0x21, 0 - .dw 0x2740, 0xc019, 0x277f, 0xc019, 0x21, 0 - .dw 0x27c0, 0xc019, 0x27ff, 0xc019, 0x21, 0 - .dw 0x2840, 0xc019, 0x287f, 0xc019, 0x21, 0 - .dw 0x28c0, 0xc019, 0x28ff, 0xc019, 0x21, 0 - .dw 0x2940, 0xc019, 0x297f, 0xc019, 0x21, 0 - .dw 0x29c0, 0xc019, 0x29ff, 0xc019, 0x21, 0 - .dw 0x2a40, 0xc019, 0x2a7f, 0xc019, 0x21, 0 - .dw 0x2ac0, 0xc019, 0x2aff, 0xc019, 0x21, 0 - .dw 0x2b40, 0xc019, 0x2b7f, 0xc019, 0x21, 0 - .dw 0x2bc0, 0xc019, 0x2bff, 0xc019, 0x21, 0 - .dw 0x2c40, 0xc019, 0x2c7f, 0xc019, 0x21, 0 - .dw 0x2cc0, 0xc019, 0x2cff, 0xc019, 0x21, 0 - .dw 0x2d40, 0xc019, 0x2d7f, 0xc019, 0x21, 0 - .dw 0x2dc0, 0xc019, 0x2dff, 0xc019, 0x21, 0 - .dw 0x2e40, 0xc019, 0x2e7f, 0xc019, 0x21, 0 - .dw 0x2ec0, 0xc019, 0x2eff, 0xc019, 0x21, 0 - .dw 0x2f40, 0xc019, 0x2f7f, 0xc019, 0x21, 0 - .dw 0x2fc0, 0xc019, 0x2fff, 0xc019, 0x21, 0 - .dw 0x3040, 0xc019, 0x307f, 0xc019, 0x21, 0 - .dw 0x30c0, 0xc019, 0x30ff, 0xc019, 0x21, 0 - .dw 0x3140, 0xc019, 0x317f, 0xc019, 0x21, 0 - .dw 0x31c0, 0xc019, 0x31ff, 0xc019, 0x21, 0 - .dw 0x3240, 0xc019, 0x327f, 0xc019, 0x21, 0 - .dw 0x32c0, 0xc019, 0x32ff, 0xc019, 0x21, 0 - .dw 0x3340, 0xc019, 0x337f, 0xc019, 0x21, 0 - .dw 0x33c0, 0xc019, 0x33ff, 0xc019, 0x21, 0 - .dw 0x3440, 0xc019, 0x347f, 0xc019, 0x21, 0 - .dw 0x34c0, 0xc019, 0x34ff, 0xc019, 0x21, 0 - .dw 0x3540, 0xc019, 0x357f, 0xc019, 0x21, 0 - .dw 0x35c0, 0xc019, 0x35ff, 0xc019, 0x21, 0 - .dw 0x3640, 0xc019, 0x367f, 0xc019, 0x21, 0 - .dw 0x36c0, 0xc019, 0x36ff, 0xc019, 0x21, 0 - .dw 0x3740, 0xc019, 0x377f, 0xc019, 0x21, 0 - .dw 0x37c0, 0xc019, 0x37ff, 0xc019, 0x21, 0 - .dw 0x3840, 0xc019, 0x387f, 0xc019, 0x21, 0 - .dw 0x38c0, 0xc019, 0x38ff, 0xc019, 0x21, 0 - .dw 0x3940, 0xc019, 0x397f, 0xc019, 0x21, 0 - .dw 0x39c0, 0xc019, 0x5fff, 0xc019, 0x21, 0 - .dw 0x6040, 0xc019, 0x607f, 0xc019, 0x21, 0 - .dw 0x60c0, 0xc019, 0x60ff, 0xc019, 0x21, 0 - .dw 0x6140, 0xc019, 0x617f, 0xc019, 0x21, 0 - .dw 0x61c0, 0xc019, 0x61ff, 0xc019, 0x21, 0 - .dw 0x6240, 0xc019, 0x627f, 0xc019, 0x21, 0 - .dw 0x62c0, 0xc019, 0x62ff, 0xc019, 0x21, 0 - .dw 0x6340, 0xc019, 0x637f, 0xc019, 0x21, 0 - .dw 0x63c0, 0xc019, 0x63ff, 0xc019, 0x21, 0 - .dw 0x6440, 0xc019, 0x647f, 0xc019, 0x21, 0 - .dw 0x64c0, 0xc019, 0x64ff, 0xc019, 0x21, 0 - .dw 0x6540, 0xc019, 0x657f, 0xc019, 0x21, 0 - .dw 0x65c0, 0xc019, 0x65ff, 0xc019, 0x21, 0 - .dw 0x6640, 0xc019, 0x667f, 0xc019, 0x21, 0 - .dw 0x66c0, 0xc019, 0x66ff, 0xc019, 0x21, 0 - .dw 0x6740, 0xc019, 0x677f, 0xc019, 0x21, 0 - .dw 0x67c0, 0xc019, 0x67ff, 0xc019, 0x21, 0 - .dw 0x6840, 0xc019, 0x687f, 0xc019, 0x21, 0 - .dw 0x68c0, 0xc019, 0x68ff, 0xc019, 0x21, 0 - .dw 0x6940, 0xc019, 0x697f, 0xc019, 0x21, 0 - .dw 0x69c0, 0xc019, 0x69ff, 0xc019, 0x21, 0 - .dw 0x6a40, 0xc019, 0x6a7f, 0xc019, 0x21, 0 - .dw 0x6ac0, 0xc019, 0x6aff, 0xc019, 0x21, 0 - .dw 0x6b40, 0xc019, 0x6b7f, 0xc019, 0x21, 0 - .dw 0x6bc0, 0xc019, 0x6bff, 0xc019, 0x21, 0 - .dw 0x6c40, 0xc019, 0x6c7f, 0xc019, 0x21, 0 - .dw 0x6cc0, 0xc019, 0x6cff, 0xc019, 0x21, 0 - .dw 0x6d40, 0xc019, 0x6d7f, 0xc019, 0x21, 0 - .dw 0x6dc0, 0xc019, 0x6dff, 0xc019, 0x21, 0 - .dw 0x6e40, 0xc019, 0x6e7f, 0xc019, 0x21, 0 - .dw 0x6ec0, 0xc019, 0x6eff, 0xc019, 0x21, 0 - .dw 0x6f40, 0xc019, 0x6f7f, 0xc019, 0x21, 0 - .dw 0x6fc0, 0xc019, 0x6fff, 0xc019, 0x21, 0 - .dw 0x7040, 0xc019, 0x707f, 0xc019, 0x21, 0 - .dw 0x70c0, 0xc019, 0x70ff, 0xc019, 0x21, 0 - .dw 0x7140, 0xc019, 0x717f, 0xc019, 0x21, 0 - .dw 0x71c0, 0xc019, 0x71ff, 0xc019, 0x21, 0 - .dw 0x7240, 0xc019, 0x727f, 0xc019, 0x21, 0 - .dw 0x72c0, 0xc019, 0x72ff, 0xc019, 0x21, 0 - .dw 0x7340, 0xc019, 0x737f, 0xc019, 0x21, 0 - .dw 0x73c0, 0xc019, 0x73ff, 0xc019, 0x21, 0 - .dw 0x7440, 0xc019, 0x747f, 0xc019, 0x21, 0 - .dw 0x74c0, 0xc019, 0x74ff, 0xc019, 0x21, 0 - .dw 0x7540, 0xc019, 0x757f, 0xc019, 0x21, 0 - .dw 0x75c0, 0xc019, 0x75ff, 0xc019, 0x21, 0 - .dw 0x7640, 0xc019, 0x767f, 0xc019, 0x21, 0 - .dw 0x76c0, 0xc019, 0x76ff, 0xc019, 0x21, 0 - .dw 0x7740, 0xc019, 0x777f, 0xc019, 0x21, 0 - .dw 0x77c0, 0xc019, 0x77ff, 0xc019, 0x21, 0 - .dw 0x7840, 0xc019, 0x787f, 0xc019, 0x21, 0 - .dw 0x78c0, 0xc019, 0x78ff, 0xc019, 0x21, 0 - .dw 0x7940, 0xc019, 0x797f, 0xc019, 0x21, 0 - .dw 0x79c0, 0xc019, 0x9fff, 0xc019, 0x21, 0 - .dw 0xa040, 0xc019, 0xa07f, 0xc019, 0x21, 0 - .dw 0xa0c0, 0xc019, 0xa0ff, 0xc019, 0x21, 0 - .dw 0xa140, 0xc019, 0xa17f, 0xc019, 0x21, 0 - .dw 0xa1c0, 0xc019, 0xa1ff, 0xc019, 0x21, 0 - .dw 0xa240, 0xc019, 0xa27f, 0xc019, 0x21, 0 - .dw 0xa2c0, 0xc019, 0xa2ff, 0xc019, 0x21, 0 - .dw 0xa340, 0xc019, 0xa37f, 0xc019, 0x21, 0 - .dw 0xa3c0, 0xc019, 0xa3ff, 0xc019, 0x21, 0 - .dw 0xa440, 0xc019, 0xa47f, 0xc019, 0x21, 0 - .dw 0xa4c0, 0xc019, 0xa4ff, 0xc019, 0x21, 0 - .dw 0xa540, 0xc019, 0xa57f, 0xc019, 0x21, 0 - .dw 0xa5c0, 0xc019, 0xa5ff, 0xc019, 0x21, 0 - .dw 0xa640, 0xc019, 0xa67f, 0xc019, 0x21, 0 - .dw 0xa6c0, 0xc019, 0xa6ff, 0xc019, 0x21, 0 - .dw 0xa740, 0xc019, 0xa77f, 0xc019, 0x21, 0 - .dw 0xa7c0, 0xc019, 0xa7ff, 0xc019, 0x21, 0 - .dw 0xa840, 0xc019, 0xa87f, 0xc019, 0x21, 0 - .dw 0xa8c0, 0xc019, 0xa8ff, 0xc019, 0x21, 0 - .dw 0xa940, 0xc019, 0xa97f, 0xc019, 0x21, 0 - .dw 0xa9c0, 0xc019, 0xa9ff, 0xc019, 0x21, 0 - .dw 0xaa40, 0xc019, 0xaa7f, 0xc019, 0x21, 0 - .dw 0xaac0, 0xc019, 0xaaff, 0xc019, 0x21, 0 - .dw 0xab40, 0xc019, 0xab7f, 0xc019, 0x21, 0 - .dw 0xabc0, 0xc019, 0xabff, 0xc019, 0x21, 0 - .dw 0xac40, 0xc019, 0xac7f, 0xc019, 0x21, 0 - .dw 0xacc0, 0xc019, 0xacff, 0xc019, 0x21, 0 - .dw 0xad40, 0xc019, 0xad7f, 0xc019, 0x21, 0 - .dw 0xadc0, 0xc019, 0xadff, 0xc019, 0x21, 0 - .dw 0xae40, 0xc019, 0xae7f, 0xc019, 0x21, 0 - .dw 0xaec0, 0xc019, 0xaeff, 0xc019, 0x21, 0 - .dw 0xaf40, 0xc019, 0xaf7f, 0xc019, 0x21, 0 - .dw 0xafc0, 0xc019, 0xafff, 0xc019, 0x21, 0 - .dw 0xb040, 0xc019, 0xb07f, 0xc019, 0x21, 0 - .dw 0xb0c0, 0xc019, 0xb0ff, 0xc019, 0x21, 0 - .dw 0xb140, 0xc019, 0xb17f, 0xc019, 0x21, 0 - .dw 0xb1c0, 0xc019, 0xb1ff, 0xc019, 0x21, 0 - .dw 0xb240, 0xc019, 0xb27f, 0xc019, 0x21, 0 - .dw 0xb2c0, 0xc019, 0xb2ff, 0xc019, 0x21, 0 - .dw 0xb340, 0xc019, 0xb37f, 0xc019, 0x21, 0 - .dw 0xb3c0, 0xc019, 0xb3ff, 0xc019, 0x21, 0 - .dw 0xb440, 0xc019, 0xb47f, 0xc019, 0x21, 0 - .dw 0xb4c0, 0xc019, 0xb4ff, 0xc019, 0x21, 0 - .dw 0xb540, 0xc019, 0xb57f, 0xc019, 0x21, 0 - .dw 0xb5c0, 0xc019, 0xb5ff, 0xc019, 0x21, 0 - .dw 0xb640, 0xc019, 0xb67f, 0xc019, 0x21, 0 - .dw 0xb6c0, 0xc019, 0xb6ff, 0xc019, 0x21, 0 - .dw 0xb740, 0xc019, 0xb77f, 0xc019, 0x21, 0 - .dw 0xb7c0, 0xc019, 0xb7ff, 0xc019, 0x21, 0 - .dw 0xb840, 0xc019, 0xb87f, 0xc019, 0x21, 0 - .dw 0xb8c0, 0xc019, 0xb8ff, 0xc019, 0x21, 0 - .dw 0xb940, 0xc019, 0xb97f, 0xc019, 0x21, 0 - .dw 0xb9c0, 0xc019, 0xdfff, 0xc019, 0x21, 0 - .dw 0xe040, 0xc019, 0xe07f, 0xc019, 0x21, 0 - .dw 0xe0c0, 0xc019, 0xe0ff, 0xc019, 0x21, 0 - .dw 0xe140, 0xc019, 0xe17f, 0xc019, 0x21, 0 - .dw 0xe1c0, 0xc019, 0xe1ff, 0xc019, 0x21, 0 - .dw 0xe240, 0xc019, 0xe27f, 0xc019, 0x21, 0 - .dw 0xe2c0, 0xc019, 0xe2ff, 0xc019, 0x21, 0 - .dw 0xe340, 0xc019, 0xe37f, 0xc019, 0x21, 0 - .dw 0xe3c0, 0xc019, 0xe3ff, 0xc019, 0x21, 0 - .dw 0xe440, 0xc019, 0xe47f, 0xc019, 0x21, 0 - .dw 0xe4c0, 0xc019, 0xe4ff, 0xc019, 0x21, 0 - .dw 0xe540, 0xc019, 0xe57f, 0xc019, 0x21, 0 - .dw 0xe5c0, 0xc019, 0xe5ff, 0xc019, 0x21, 0 - .dw 0xe640, 0xc019, 0xe67f, 0xc019, 0x21, 0 - .dw 0xe6c0, 0xc019, 0xe6ff, 0xc019, 0x21, 0 - .dw 0xe740, 0xc019, 0xe77f, 0xc019, 0x21, 0 - .dw 0xe7c0, 0xc019, 0xe7ff, 0xc019, 0x21, 0 - .dw 0xe840, 0xc019, 0xe87f, 0xc019, 0x21, 0 - .dw 0xe8c0, 0xc019, 0xe8ff, 0xc019, 0x21, 0 - .dw 0xe940, 0xc019, 0xe97f, 0xc019, 0x21, 0 - .dw 0xe9c0, 0xc019, 0xe9ff, 0xc019, 0x21, 0 - .dw 0xea40, 0xc019, 0xea7f, 0xc019, 0x21, 0 - .dw 0xeac0, 0xc019, 0xeaff, 0xc019, 0x21, 0 - .dw 0xeb40, 0xc019, 0xeb7f, 0xc019, 0x21, 0 - .dw 0xebc0, 0xc019, 0xebff, 0xc019, 0x21, 0 - .dw 0xec40, 0xc019, 0xec7f, 0xc019, 0x21, 0 - .dw 0xecc0, 0xc019, 0xecff, 0xc019, 0x21, 0 - .dw 0xed40, 0xc019, 0xed7f, 0xc019, 0x21, 0 - .dw 0xedc0, 0xc019, 0xedff, 0xc019, 0x21, 0 - .dw 0xee40, 0xc019, 0xee7f, 0xc019, 0x21, 0 - .dw 0xeec0, 0xc019, 0xeeff, 0xc019, 0x21, 0 - .dw 0xef40, 0xc019, 0xef7f, 0xc019, 0x21, 0 - .dw 0xefc0, 0xc019, 0xefff, 0xc019, 0x21, 0 - .dw 0xf040, 0xc019, 0xf07f, 0xc019, 0x21, 0 - .dw 0xf0c0, 0xc019, 0xf0ff, 0xc019, 0x21, 0 - .dw 0xf140, 0xc019, 0xf17f, 0xc019, 0x21, 0 - .dw 0xf1c0, 0xc019, 0xf1ff, 0xc019, 0x21, 0 - .dw 0xf240, 0xc019, 0xf27f, 0xc019, 0x21, 0 - .dw 0xf2c0, 0xc019, 0xf2ff, 0xc019, 0x21, 0 - .dw 0xf340, 0xc019, 0xf37f, 0xc019, 0x21, 0 - .dw 0xf3c0, 0xc019, 0xf3ff, 0xc019, 0x21, 0 - .dw 0xf440, 0xc019, 0xf47f, 0xc019, 0x21, 0 - .dw 0xf4c0, 0xc019, 0xf4ff, 0xc019, 0x21, 0 - .dw 0xf540, 0xc019, 0xf57f, 0xc019, 0x21, 0 - .dw 0xf5c0, 0xc019, 0xf5ff, 0xc019, 0x21, 0 - .dw 0xf640, 0xc019, 0xf67f, 0xc019, 0x21, 0 - .dw 0xf6c0, 0xc019, 0xf6ff, 0xc019, 0x21, 0 - .dw 0xf740, 0xc019, 0xf77f, 0xc019, 0x21, 0 - .dw 0xf7c0, 0xc019, 0xf7ff, 0xc019, 0x21, 0 - .dw 0xf840, 0xc019, 0xf87f, 0xc019, 0x21, 0 - .dw 0xf8c0, 0xc019, 0xf8ff, 0xc019, 0x21, 0 - .dw 0xf940, 0xc019, 0xf97f, 0xc019, 0x21, 0 - .dw 0xf9c0, 0xc019, 0x1fff, 0xc01a, 0x21, 0 - .dw 0x2040, 0xc01a, 0x207f, 0xc01a, 0x21, 0 - .dw 0x20c0, 0xc01a, 0x20ff, 0xc01a, 0x21, 0 - .dw 0x2140, 0xc01a, 0x217f, 0xc01a, 0x21, 0 - .dw 0x21c0, 0xc01a, 0x21ff, 0xc01a, 0x21, 0 - .dw 0x2240, 0xc01a, 0x227f, 0xc01a, 0x21, 0 - .dw 0x22c0, 0xc01a, 0x22ff, 0xc01a, 0x21, 0 - .dw 0x2340, 0xc01a, 0x237f, 0xc01a, 0x21, 0 - .dw 0x23c0, 0xc01a, 0x23ff, 0xc01a, 0x21, 0 - .dw 0x2440, 0xc01a, 0x247f, 0xc01a, 0x21, 0 - .dw 0x24c0, 0xc01a, 0x24ff, 0xc01a, 0x21, 0 - .dw 0x2540, 0xc01a, 0x257f, 0xc01a, 0x21, 0 - .dw 0x25c0, 0xc01a, 0x25ff, 0xc01a, 0x21, 0 - .dw 0x2640, 0xc01a, 0x267f, 0xc01a, 0x21, 0 - .dw 0x26c0, 0xc01a, 0x26ff, 0xc01a, 0x21, 0 - .dw 0x2740, 0xc01a, 0x277f, 0xc01a, 0x21, 0 - .dw 0x27c0, 0xc01a, 0x27ff, 0xc01a, 0x21, 0 - .dw 0x2840, 0xc01a, 0x287f, 0xc01a, 0x21, 0 - .dw 0x28c0, 0xc01a, 0x28ff, 0xc01a, 0x21, 0 - .dw 0x2940, 0xc01a, 0x297f, 0xc01a, 0x21, 0 - .dw 0x29c0, 0xc01a, 0x29ff, 0xc01a, 0x21, 0 - .dw 0x2a40, 0xc01a, 0x2a7f, 0xc01a, 0x21, 0 - .dw 0x2ac0, 0xc01a, 0x2aff, 0xc01a, 0x21, 0 - .dw 0x2b40, 0xc01a, 0x2b7f, 0xc01a, 0x21, 0 - .dw 0x2bc0, 0xc01a, 0x2bff, 0xc01a, 0x21, 0 - .dw 0x2c40, 0xc01a, 0x2c7f, 0xc01a, 0x21, 0 - .dw 0x2cc0, 0xc01a, 0x2cff, 0xc01a, 0x21, 0 - .dw 0x2d40, 0xc01a, 0x2d7f, 0xc01a, 0x21, 0 - .dw 0x2dc0, 0xc01a, 0x2dff, 0xc01a, 0x21, 0 - .dw 0x2e40, 0xc01a, 0x2e7f, 0xc01a, 0x21, 0 - .dw 0x2ec0, 0xc01a, 0x2eff, 0xc01a, 0x21, 0 - .dw 0x2f40, 0xc01a, 0x2f7f, 0xc01a, 0x21, 0 - .dw 0x2fc0, 0xc01a, 0x2fff, 0xc01a, 0x21, 0 - .dw 0x3040, 0xc01a, 0x307f, 0xc01a, 0x21, 0 - .dw 0x30c0, 0xc01a, 0x30ff, 0xc01a, 0x21, 0 - .dw 0x3140, 0xc01a, 0x317f, 0xc01a, 0x21, 0 - .dw 0x31c0, 0xc01a, 0x31ff, 0xc01a, 0x21, 0 - .dw 0x3240, 0xc01a, 0x327f, 0xc01a, 0x21, 0 - .dw 0x32c0, 0xc01a, 0x32ff, 0xc01a, 0x21, 0 - .dw 0x3340, 0xc01a, 0x337f, 0xc01a, 0x21, 0 - .dw 0x33c0, 0xc01a, 0x33ff, 0xc01a, 0x21, 0 - .dw 0x3440, 0xc01a, 0x347f, 0xc01a, 0x21, 0 - .dw 0x34c0, 0xc01a, 0x34ff, 0xc01a, 0x21, 0 - .dw 0x3540, 0xc01a, 0x357f, 0xc01a, 0x21, 0 - .dw 0x35c0, 0xc01a, 0x35ff, 0xc01a, 0x21, 0 - .dw 0x3640, 0xc01a, 0x367f, 0xc01a, 0x21, 0 - .dw 0x36c0, 0xc01a, 0x36ff, 0xc01a, 0x21, 0 - .dw 0x3740, 0xc01a, 0x377f, 0xc01a, 0x21, 0 - .dw 0x37c0, 0xc01a, 0x37ff, 0xc01a, 0x21, 0 - .dw 0x3840, 0xc01a, 0x387f, 0xc01a, 0x21, 0 - .dw 0x38c0, 0xc01a, 0x38ff, 0xc01a, 0x21, 0 - .dw 0x3940, 0xc01a, 0x397f, 0xc01a, 0x21, 0 - .dw 0x39c0, 0xc01a, 0x5fff, 0xc01a, 0x21, 0 - .dw 0x6040, 0xc01a, 0x607f, 0xc01a, 0x21, 0 - .dw 0x60c0, 0xc01a, 0x60ff, 0xc01a, 0x21, 0 - .dw 0x6140, 0xc01a, 0x617f, 0xc01a, 0x21, 0 - .dw 0x61c0, 0xc01a, 0x61ff, 0xc01a, 0x21, 0 - .dw 0x6240, 0xc01a, 0x627f, 0xc01a, 0x21, 0 - .dw 0x62c0, 0xc01a, 0x62ff, 0xc01a, 0x21, 0 - .dw 0x6340, 0xc01a, 0x637f, 0xc01a, 0x21, 0 - .dw 0x63c0, 0xc01a, 0x63ff, 0xc01a, 0x21, 0 - .dw 0x6440, 0xc01a, 0x647f, 0xc01a, 0x21, 0 - .dw 0x64c0, 0xc01a, 0x64ff, 0xc01a, 0x21, 0 - .dw 0x6540, 0xc01a, 0x657f, 0xc01a, 0x21, 0 - .dw 0x65c0, 0xc01a, 0x65ff, 0xc01a, 0x21, 0 - .dw 0x6640, 0xc01a, 0x667f, 0xc01a, 0x21, 0 - .dw 0x66c0, 0xc01a, 0x66ff, 0xc01a, 0x21, 0 - .dw 0x6740, 0xc01a, 0x677f, 0xc01a, 0x21, 0 - .dw 0x67c0, 0xc01a, 0x67ff, 0xc01a, 0x21, 0 - .dw 0x6840, 0xc01a, 0x687f, 0xc01a, 0x21, 0 - .dw 0x68c0, 0xc01a, 0x68ff, 0xc01a, 0x21, 0 - .dw 0x6940, 0xc01a, 0x697f, 0xc01a, 0x21, 0 - .dw 0x69c0, 0xc01a, 0x69ff, 0xc01a, 0x21, 0 - .dw 0x6a40, 0xc01a, 0x6a7f, 0xc01a, 0x21, 0 - .dw 0x6ac0, 0xc01a, 0x6aff, 0xc01a, 0x21, 0 - .dw 0x6b40, 0xc01a, 0x6b7f, 0xc01a, 0x21, 0 - .dw 0x6bc0, 0xc01a, 0x6bff, 0xc01a, 0x21, 0 - .dw 0x6c40, 0xc01a, 0x6c7f, 0xc01a, 0x21, 0 - .dw 0x6cc0, 0xc01a, 0x6cff, 0xc01a, 0x21, 0 - .dw 0x6d40, 0xc01a, 0x6d7f, 0xc01a, 0x21, 0 - .dw 0x6dc0, 0xc01a, 0x6dff, 0xc01a, 0x21, 0 - .dw 0x6e40, 0xc01a, 0x6e7f, 0xc01a, 0x21, 0 - .dw 0x6ec0, 0xc01a, 0x6eff, 0xc01a, 0x21, 0 - .dw 0x6f40, 0xc01a, 0x6f7f, 0xc01a, 0x21, 0 - .dw 0x6fc0, 0xc01a, 0x6fff, 0xc01a, 0x21, 0 - .dw 0x7040, 0xc01a, 0x707f, 0xc01a, 0x21, 0 - .dw 0x70c0, 0xc01a, 0x70ff, 0xc01a, 0x21, 0 - .dw 0x7140, 0xc01a, 0x717f, 0xc01a, 0x21, 0 - .dw 0x71c0, 0xc01a, 0x71ff, 0xc01a, 0x21, 0 - .dw 0x7240, 0xc01a, 0x727f, 0xc01a, 0x21, 0 - .dw 0x72c0, 0xc01a, 0x72ff, 0xc01a, 0x21, 0 - .dw 0x7340, 0xc01a, 0x737f, 0xc01a, 0x21, 0 - .dw 0x73c0, 0xc01a, 0x73ff, 0xc01a, 0x21, 0 - .dw 0x7440, 0xc01a, 0x747f, 0xc01a, 0x21, 0 - .dw 0x74c0, 0xc01a, 0x74ff, 0xc01a, 0x21, 0 - .dw 0x7540, 0xc01a, 0x757f, 0xc01a, 0x21, 0 - .dw 0x75c0, 0xc01a, 0x75ff, 0xc01a, 0x21, 0 - .dw 0x7640, 0xc01a, 0x767f, 0xc01a, 0x21, 0 - .dw 0x76c0, 0xc01a, 0x76ff, 0xc01a, 0x21, 0 - .dw 0x7740, 0xc01a, 0x777f, 0xc01a, 0x21, 0 - .dw 0x77c0, 0xc01a, 0x77ff, 0xc01a, 0x21, 0 - .dw 0x7840, 0xc01a, 0x787f, 0xc01a, 0x21, 0 - .dw 0x78c0, 0xc01a, 0x78ff, 0xc01a, 0x21, 0 - .dw 0x7940, 0xc01a, 0x797f, 0xc01a, 0x21, 0 - .dw 0x79c0, 0xc01a, 0x9fff, 0xc01a, 0x21, 0 - .dw 0xa040, 0xc01a, 0xa07f, 0xc01a, 0x21, 0 - .dw 0xa0c0, 0xc01a, 0xa0ff, 0xc01a, 0x21, 0 - .dw 0xa140, 0xc01a, 0xa17f, 0xc01a, 0x21, 0 - .dw 0xa1c0, 0xc01a, 0xa1ff, 0xc01a, 0x21, 0 - .dw 0xa240, 0xc01a, 0xa27f, 0xc01a, 0x21, 0 - .dw 0xa2c0, 0xc01a, 0xa2ff, 0xc01a, 0x21, 0 - .dw 0xa340, 0xc01a, 0xa37f, 0xc01a, 0x21, 0 - .dw 0xa3c0, 0xc01a, 0xa3ff, 0xc01a, 0x21, 0 - .dw 0xa440, 0xc01a, 0xa47f, 0xc01a, 0x21, 0 - .dw 0xa4c0, 0xc01a, 0xa4ff, 0xc01a, 0x21, 0 - .dw 0xa540, 0xc01a, 0xa57f, 0xc01a, 0x21, 0 - .dw 0xa5c0, 0xc01a, 0xa5ff, 0xc01a, 0x21, 0 - .dw 0xa640, 0xc01a, 0xa67f, 0xc01a, 0x21, 0 - .dw 0xa6c0, 0xc01a, 0xa6ff, 0xc01a, 0x21, 0 - .dw 0xa740, 0xc01a, 0xa77f, 0xc01a, 0x21, 0 - .dw 0xa7c0, 0xc01a, 0xa7ff, 0xc01a, 0x21, 0 - .dw 0xa840, 0xc01a, 0xa87f, 0xc01a, 0x21, 0 - .dw 0xa8c0, 0xc01a, 0xa8ff, 0xc01a, 0x21, 0 - .dw 0xa940, 0xc01a, 0xa97f, 0xc01a, 0x21, 0 - .dw 0xa9c0, 0xc01a, 0xa9ff, 0xc01a, 0x21, 0 - .dw 0xaa40, 0xc01a, 0xaa7f, 0xc01a, 0x21, 0 - .dw 0xaac0, 0xc01a, 0xaaff, 0xc01a, 0x21, 0 - .dw 0xab40, 0xc01a, 0xab7f, 0xc01a, 0x21, 0 - .dw 0xabc0, 0xc01a, 0xabff, 0xc01a, 0x21, 0 - .dw 0xac40, 0xc01a, 0xac7f, 0xc01a, 0x21, 0 - .dw 0xacc0, 0xc01a, 0xacff, 0xc01a, 0x21, 0 - .dw 0xad40, 0xc01a, 0xad7f, 0xc01a, 0x21, 0 - .dw 0xadc0, 0xc01a, 0xadff, 0xc01a, 0x21, 0 - .dw 0xae40, 0xc01a, 0xae7f, 0xc01a, 0x21, 0 - .dw 0xaec0, 0xc01a, 0xaeff, 0xc01a, 0x21, 0 - .dw 0xaf40, 0xc01a, 0xaf7f, 0xc01a, 0x21, 0 - .dw 0xafc0, 0xc01a, 0xafff, 0xc01a, 0x21, 0 - .dw 0xb040, 0xc01a, 0xb07f, 0xc01a, 0x21, 0 - .dw 0xb0c0, 0xc01a, 0xb0ff, 0xc01a, 0x21, 0 - .dw 0xb140, 0xc01a, 0xb17f, 0xc01a, 0x21, 0 - .dw 0xb1c0, 0xc01a, 0xb1ff, 0xc01a, 0x21, 0 - .dw 0xb240, 0xc01a, 0xb27f, 0xc01a, 0x21, 0 - .dw 0xb2c0, 0xc01a, 0xb2ff, 0xc01a, 0x21, 0 - .dw 0xb340, 0xc01a, 0xb37f, 0xc01a, 0x21, 0 - .dw 0xb3c0, 0xc01a, 0xb3ff, 0xc01a, 0x21, 0 - .dw 0xb440, 0xc01a, 0xb47f, 0xc01a, 0x21, 0 - .dw 0xb4c0, 0xc01a, 0xb4ff, 0xc01a, 0x21, 0 - .dw 0xb540, 0xc01a, 0xb57f, 0xc01a, 0x21, 0 - .dw 0xb5c0, 0xc01a, 0xb5ff, 0xc01a, 0x21, 0 - .dw 0xb640, 0xc01a, 0xb67f, 0xc01a, 0x21, 0 - .dw 0xb6c0, 0xc01a, 0xb6ff, 0xc01a, 0x21, 0 - .dw 0xb740, 0xc01a, 0xb77f, 0xc01a, 0x21, 0 - .dw 0xb7c0, 0xc01a, 0xb7ff, 0xc01a, 0x21, 0 - .dw 0xb840, 0xc01a, 0xb87f, 0xc01a, 0x21, 0 - .dw 0xb8c0, 0xc01a, 0xb8ff, 0xc01a, 0x21, 0 - .dw 0xb940, 0xc01a, 0xb97f, 0xc01a, 0x21, 0 - .dw 0xb9c0, 0xc01a, 0xdfff, 0xc01a, 0x21, 0 - .dw 0xe040, 0xc01a, 0xe07f, 0xc01a, 0x21, 0 - .dw 0xe0c0, 0xc01a, 0xe0ff, 0xc01a, 0x21, 0 - .dw 0xe140, 0xc01a, 0xe17f, 0xc01a, 0x21, 0 - .dw 0xe1c0, 0xc01a, 0xe1ff, 0xc01a, 0x21, 0 - .dw 0xe240, 0xc01a, 0xe27f, 0xc01a, 0x21, 0 - .dw 0xe2c0, 0xc01a, 0xe2ff, 0xc01a, 0x21, 0 - .dw 0xe340, 0xc01a, 0xe37f, 0xc01a, 0x21, 0 - .dw 0xe3c0, 0xc01a, 0xe3ff, 0xc01a, 0x21, 0 - .dw 0xe440, 0xc01a, 0xe47f, 0xc01a, 0x21, 0 - .dw 0xe4c0, 0xc01a, 0xe4ff, 0xc01a, 0x21, 0 - .dw 0xe540, 0xc01a, 0xe57f, 0xc01a, 0x21, 0 - .dw 0xe5c0, 0xc01a, 0xe5ff, 0xc01a, 0x21, 0 - .dw 0xe640, 0xc01a, 0xe67f, 0xc01a, 0x21, 0 - .dw 0xe6c0, 0xc01a, 0xe6ff, 0xc01a, 0x21, 0 - .dw 0xe740, 0xc01a, 0xe77f, 0xc01a, 0x21, 0 - .dw 0xe7c0, 0xc01a, 0xe7ff, 0xc01a, 0x21, 0 - .dw 0xe840, 0xc01a, 0xe87f, 0xc01a, 0x21, 0 - .dw 0xe8c0, 0xc01a, 0xe8ff, 0xc01a, 0x21, 0 - .dw 0xe940, 0xc01a, 0xe97f, 0xc01a, 0x21, 0 - .dw 0xe9c0, 0xc01a, 0xe9ff, 0xc01a, 0x21, 0 - .dw 0xea40, 0xc01a, 0xea7f, 0xc01a, 0x21, 0 - .dw 0xeac0, 0xc01a, 0xeaff, 0xc01a, 0x21, 0 - .dw 0xeb40, 0xc01a, 0xeb7f, 0xc01a, 0x21, 0 - .dw 0xebc0, 0xc01a, 0xebff, 0xc01a, 0x21, 0 - .dw 0xec40, 0xc01a, 0xec7f, 0xc01a, 0x21, 0 - .dw 0xecc0, 0xc01a, 0xecff, 0xc01a, 0x21, 0 - .dw 0xed40, 0xc01a, 0xed7f, 0xc01a, 0x21, 0 - .dw 0xedc0, 0xc01a, 0xedff, 0xc01a, 0x21, 0 - .dw 0xee40, 0xc01a, 0xee7f, 0xc01a, 0x21, 0 - .dw 0xeec0, 0xc01a, 0xeeff, 0xc01a, 0x21, 0 - .dw 0xef40, 0xc01a, 0xef7f, 0xc01a, 0x21, 0 - .dw 0xefc0, 0xc01a, 0xefff, 0xc01a, 0x21, 0 - .dw 0xf040, 0xc01a, 0xf07f, 0xc01a, 0x21, 0 - .dw 0xf0c0, 0xc01a, 0xf0ff, 0xc01a, 0x21, 0 - .dw 0xf140, 0xc01a, 0xf17f, 0xc01a, 0x21, 0 - .dw 0xf1c0, 0xc01a, 0xf1ff, 0xc01a, 0x21, 0 - .dw 0xf240, 0xc01a, 0xf27f, 0xc01a, 0x21, 0 - .dw 0xf2c0, 0xc01a, 0xf2ff, 0xc01a, 0x21, 0 - .dw 0xf340, 0xc01a, 0xf37f, 0xc01a, 0x21, 0 - .dw 0xf3c0, 0xc01a, 0xf3ff, 0xc01a, 0x21, 0 - .dw 0xf440, 0xc01a, 0xf47f, 0xc01a, 0x21, 0 - .dw 0xf4c0, 0xc01a, 0xf4ff, 0xc01a, 0x21, 0 - .dw 0xf540, 0xc01a, 0xf57f, 0xc01a, 0x21, 0 - .dw 0xf5c0, 0xc01a, 0xf5ff, 0xc01a, 0x21, 0 - .dw 0xf640, 0xc01a, 0xf67f, 0xc01a, 0x21, 0 - .dw 0xf6c0, 0xc01a, 0xf6ff, 0xc01a, 0x21, 0 - .dw 0xf740, 0xc01a, 0xf77f, 0xc01a, 0x21, 0 - .dw 0xf7c0, 0xc01a, 0xf7ff, 0xc01a, 0x21, 0 - .dw 0xf840, 0xc01a, 0xf87f, 0xc01a, 0x21, 0 - .dw 0xf8c0, 0xc01a, 0xf8ff, 0xc01a, 0x21, 0 - .dw 0xf940, 0xc01a, 0xf97f, 0xc01a, 0x21, 0 - .dw 0xf9c0, 0xc01a, 0xffff, 0xc01b, 0x21, 0 - .dw 0x0040, 0xc01c, 0x007f, 0xc01c, 0x21, 0 - .dw 0x00c0, 0xc01c, 0x00ff, 0xc01c, 0x21, 0 - .dw 0x0140, 0xc01c, 0x017f, 0xc01c, 0x21, 0 - .dw 0x01c0, 0xc01c, 0x01ff, 0xc01c, 0x21, 0 - .dw 0x0240, 0xc01c, 0x027f, 0xc01c, 0x21, 0 - .dw 0x02c0, 0xc01c, 0x02ff, 0xc01c, 0x21, 0 - .dw 0x0340, 0xc01c, 0x037f, 0xc01c, 0x21, 0 - .dw 0x03c0, 0xc01c, 0x03ff, 0xc01c, 0x21, 0 - .dw 0x0440, 0xc01c, 0x047f, 0xc01c, 0x21, 0 - .dw 0x04c0, 0xc01c, 0x04ff, 0xc01c, 0x21, 0 - .dw 0x0540, 0xc01c, 0x057f, 0xc01c, 0x21, 0 - .dw 0x05c0, 0xc01c, 0x05ff, 0xc01c, 0x21, 0 - .dw 0x0640, 0xc01c, 0x067f, 0xc01c, 0x21, 0 - .dw 0x06c0, 0xc01c, 0x06ff, 0xc01c, 0x21, 0 - .dw 0x0740, 0xc01c, 0x077f, 0xc01c, 0x21, 0 - .dw 0x07c0, 0xc01c, 0x07ff, 0xc01c, 0x21, 0 - .dw 0x0840, 0xc01c, 0x087f, 0xc01c, 0x21, 0 - .dw 0x08c0, 0xc01c, 0x08ff, 0xc01c, 0x21, 0 - .dw 0x0940, 0xc01c, 0x097f, 0xc01c, 0x21, 0 - .dw 0x09c0, 0xc01c, 0x09ff, 0xc01c, 0x21, 0 - .dw 0x0a40, 0xc01c, 0x0a7f, 0xc01c, 0x21, 0 - .dw 0x0ac0, 0xc01c, 0x0aff, 0xc01c, 0x21, 0 - .dw 0x0b40, 0xc01c, 0x0b7f, 0xc01c, 0x21, 0 - .dw 0x0bc0, 0xc01c, 0x0bff, 0xc01c, 0x21, 0 - .dw 0x0c40, 0xc01c, 0x0c7f, 0xc01c, 0x21, 0 - .dw 0x0cc0, 0xc01c, 0x0cff, 0xc01c, 0x21, 0 - .dw 0x0d40, 0xc01c, 0x0d7f, 0xc01c, 0x21, 0 - .dw 0x0dc0, 0xc01c, 0x0dff, 0xc01c, 0x21, 0 - .dw 0x0e40, 0xc01c, 0x0e7f, 0xc01c, 0x21, 0 - .dw 0x0ec0, 0xc01c, 0x0eff, 0xc01c, 0x21, 0 - .dw 0x0f40, 0xc01c, 0x0f7f, 0xc01c, 0x21, 0 - .dw 0x0fc0, 0xc01c, 0x0fff, 0xc01c, 0x21, 0 - .dw 0x1040, 0xc01c, 0x107f, 0xc01c, 0x21, 0 - .dw 0x10c0, 0xc01c, 0x10ff, 0xc01c, 0x21, 0 - .dw 0x1140, 0xc01c, 0x117f, 0xc01c, 0x21, 0 - .dw 0x11c0, 0xc01c, 0x11ff, 0xc01c, 0x21, 0 - .dw 0x1240, 0xc01c, 0x127f, 0xc01c, 0x21, 0 - .dw 0x12c0, 0xc01c, 0x12ff, 0xc01c, 0x21, 0 - .dw 0x1340, 0xc01c, 0x137f, 0xc01c, 0x21, 0 - .dw 0x13c0, 0xc01c, 0x13ff, 0xc01c, 0x21, 0 - .dw 0x1440, 0xc01c, 0x147f, 0xc01c, 0x21, 0 - .dw 0x14c0, 0xc01c, 0x14ff, 0xc01c, 0x21, 0 - .dw 0x1540, 0xc01c, 0x157f, 0xc01c, 0x21, 0 - .dw 0x15c0, 0xc01c, 0x15ff, 0xc01c, 0x21, 0 - .dw 0x1640, 0xc01c, 0x167f, 0xc01c, 0x21, 0 - .dw 0x16c0, 0xc01c, 0x16ff, 0xc01c, 0x21, 0 - .dw 0x1740, 0xc01c, 0x177f, 0xc01c, 0x21, 0 - .dw 0x17c0, 0xc01c, 0x17ff, 0xc01c, 0x21, 0 - .dw 0x1840, 0xc01c, 0x187f, 0xc01c, 0x21, 0 - .dw 0x18c0, 0xc01c, 0x18ff, 0xc01c, 0x21, 0 - .dw 0x1940, 0xc01c, 0x197f, 0xc01c, 0x21, 0 - .dw 0x19c0, 0xc01c, 0x1fff, 0xc01c, 0x21, 0 - .dw 0x2040, 0xc01c, 0x207f, 0xc01c, 0x21, 0 - .dw 0x20c0, 0xc01c, 0x20ff, 0xc01c, 0x21, 0 - .dw 0x2140, 0xc01c, 0x217f, 0xc01c, 0x21, 0 - .dw 0x21c0, 0xc01c, 0x21ff, 0xc01c, 0x21, 0 - .dw 0x2240, 0xc01c, 0x227f, 0xc01c, 0x21, 0 - .dw 0x22c0, 0xc01c, 0x22ff, 0xc01c, 0x21, 0 - .dw 0x2340, 0xc01c, 0x237f, 0xc01c, 0x21, 0 - .dw 0x23c0, 0xc01c, 0x23ff, 0xc01c, 0x21, 0 - .dw 0x2440, 0xc01c, 0x247f, 0xc01c, 0x21, 0 - .dw 0x24c0, 0xc01c, 0x24ff, 0xc01c, 0x21, 0 - .dw 0x2540, 0xc01c, 0x257f, 0xc01c, 0x21, 0 - .dw 0x25c0, 0xc01c, 0x25ff, 0xc01c, 0x21, 0 - .dw 0x2640, 0xc01c, 0x267f, 0xc01c, 0x21, 0 - .dw 0x26c0, 0xc01c, 0x26ff, 0xc01c, 0x21, 0 - .dw 0x2740, 0xc01c, 0x277f, 0xc01c, 0x21, 0 - .dw 0x27c0, 0xc01c, 0x27ff, 0xc01c, 0x21, 0 - .dw 0x2840, 0xc01c, 0x287f, 0xc01c, 0x21, 0 - .dw 0x28c0, 0xc01c, 0x28ff, 0xc01c, 0x21, 0 - .dw 0x2940, 0xc01c, 0x297f, 0xc01c, 0x21, 0 - .dw 0x29c0, 0xc01c, 0x29ff, 0xc01c, 0x21, 0 - .dw 0x2a40, 0xc01c, 0x2a7f, 0xc01c, 0x21, 0 - .dw 0x2ac0, 0xc01c, 0x2aff, 0xc01c, 0x21, 0 - .dw 0x2b40, 0xc01c, 0x2b7f, 0xc01c, 0x21, 0 - .dw 0x2bc0, 0xc01c, 0x2bff, 0xc01c, 0x21, 0 - .dw 0x2c40, 0xc01c, 0x2c7f, 0xc01c, 0x21, 0 - .dw 0x2cc0, 0xc01c, 0x2cff, 0xc01c, 0x21, 0 - .dw 0x2d40, 0xc01c, 0x2d7f, 0xc01c, 0x21, 0 - .dw 0x2dc0, 0xc01c, 0x2dff, 0xc01c, 0x21, 0 - .dw 0x2e40, 0xc01c, 0x2e7f, 0xc01c, 0x21, 0 - .dw 0x2ec0, 0xc01c, 0x2eff, 0xc01c, 0x21, 0 - .dw 0x2f40, 0xc01c, 0x2f7f, 0xc01c, 0x21, 0 - .dw 0x2fc0, 0xc01c, 0x2fff, 0xc01c, 0x21, 0 - .dw 0x3040, 0xc01c, 0x307f, 0xc01c, 0x21, 0 - .dw 0x30c0, 0xc01c, 0x30ff, 0xc01c, 0x21, 0 - .dw 0x3140, 0xc01c, 0x317f, 0xc01c, 0x21, 0 - .dw 0x31c0, 0xc01c, 0x31ff, 0xc01c, 0x21, 0 - .dw 0x3240, 0xc01c, 0x327f, 0xc01c, 0x21, 0 - .dw 0x32c0, 0xc01c, 0x32ff, 0xc01c, 0x21, 0 - .dw 0x3340, 0xc01c, 0x337f, 0xc01c, 0x21, 0 - .dw 0x33c0, 0xc01c, 0x33ff, 0xc01c, 0x21, 0 - .dw 0x3440, 0xc01c, 0x347f, 0xc01c, 0x21, 0 - .dw 0x34c0, 0xc01c, 0x34ff, 0xc01c, 0x21, 0 - .dw 0x3540, 0xc01c, 0x357f, 0xc01c, 0x21, 0 - .dw 0x35c0, 0xc01c, 0x35ff, 0xc01c, 0x21, 0 - .dw 0x3640, 0xc01c, 0x367f, 0xc01c, 0x21, 0 - .dw 0x36c0, 0xc01c, 0x36ff, 0xc01c, 0x21, 0 - .dw 0x3740, 0xc01c, 0x377f, 0xc01c, 0x21, 0 - .dw 0x37c0, 0xc01c, 0x37ff, 0xc01c, 0x21, 0 - .dw 0x3840, 0xc01c, 0x387f, 0xc01c, 0x21, 0 - .dw 0x38c0, 0xc01c, 0x38ff, 0xc01c, 0x21, 0 - .dw 0x3940, 0xc01c, 0x397f, 0xc01c, 0x21, 0 - .dw 0x39c0, 0xc01c, 0x3fff, 0xc01c, 0x21, 0 - .dw 0x4040, 0xc01c, 0x407f, 0xc01c, 0x21, 0 - .dw 0x40c0, 0xc01c, 0x40ff, 0xc01c, 0x21, 0 - .dw 0x4140, 0xc01c, 0x417f, 0xc01c, 0x21, 0 - .dw 0x41c0, 0xc01c, 0x41ff, 0xc01c, 0x21, 0 - .dw 0x4240, 0xc01c, 0x427f, 0xc01c, 0x21, 0 - .dw 0x42c0, 0xc01c, 0x42ff, 0xc01c, 0x21, 0 - .dw 0x4340, 0xc01c, 0x437f, 0xc01c, 0x21, 0 - .dw 0x43c0, 0xc01c, 0x43ff, 0xc01c, 0x21, 0 - .dw 0x4440, 0xc01c, 0x447f, 0xc01c, 0x21, 0 - .dw 0x44c0, 0xc01c, 0x44ff, 0xc01c, 0x21, 0 - .dw 0x4540, 0xc01c, 0x457f, 0xc01c, 0x21, 0 - .dw 0x45c0, 0xc01c, 0x45ff, 0xc01c, 0x21, 0 - .dw 0x4640, 0xc01c, 0x467f, 0xc01c, 0x21, 0 - .dw 0x46c0, 0xc01c, 0x46ff, 0xc01c, 0x21, 0 - .dw 0x4740, 0xc01c, 0x477f, 0xc01c, 0x21, 0 - .dw 0x47c0, 0xc01c, 0x47ff, 0xc01c, 0x21, 0 - .dw 0x4840, 0xc01c, 0x487f, 0xc01c, 0x21, 0 - .dw 0x48c0, 0xc01c, 0x48ff, 0xc01c, 0x21, 0 - .dw 0x4940, 0xc01c, 0x497f, 0xc01c, 0x21, 0 - .dw 0x49c0, 0xc01c, 0x49ff, 0xc01c, 0x21, 0 - .dw 0x4a40, 0xc01c, 0x4a7f, 0xc01c, 0x21, 0 - .dw 0x4ac0, 0xc01c, 0x4aff, 0xc01c, 0x21, 0 - .dw 0x4b40, 0xc01c, 0x4b7f, 0xc01c, 0x21, 0 - .dw 0x4bc0, 0xc01c, 0x4bff, 0xc01c, 0x21, 0 - .dw 0x4c40, 0xc01c, 0x4c7f, 0xc01c, 0x21, 0 - .dw 0x4cc0, 0xc01c, 0x4cff, 0xc01c, 0x21, 0 - .dw 0x4d40, 0xc01c, 0x4d7f, 0xc01c, 0x21, 0 - .dw 0x4dc0, 0xc01c, 0x4dff, 0xc01c, 0x21, 0 - .dw 0x4e40, 0xc01c, 0x4e7f, 0xc01c, 0x21, 0 - .dw 0x4ec0, 0xc01c, 0x4eff, 0xc01c, 0x21, 0 - .dw 0x4f40, 0xc01c, 0x4f7f, 0xc01c, 0x21, 0 - .dw 0x4fc0, 0xc01c, 0x4fff, 0xc01c, 0x21, 0 - .dw 0x5040, 0xc01c, 0x507f, 0xc01c, 0x21, 0 - .dw 0x50c0, 0xc01c, 0x50ff, 0xc01c, 0x21, 0 - .dw 0x5140, 0xc01c, 0x517f, 0xc01c, 0x21, 0 - .dw 0x51c0, 0xc01c, 0x51ff, 0xc01c, 0x21, 0 - .dw 0x5240, 0xc01c, 0x527f, 0xc01c, 0x21, 0 - .dw 0x52c0, 0xc01c, 0x52ff, 0xc01c, 0x21, 0 - .dw 0x5340, 0xc01c, 0x537f, 0xc01c, 0x21, 0 - .dw 0x53c0, 0xc01c, 0x53ff, 0xc01c, 0x21, 0 - .dw 0x5440, 0xc01c, 0x547f, 0xc01c, 0x21, 0 - .dw 0x54c0, 0xc01c, 0x54ff, 0xc01c, 0x21, 0 - .dw 0x5540, 0xc01c, 0x557f, 0xc01c, 0x21, 0 - .dw 0x55c0, 0xc01c, 0x55ff, 0xc01c, 0x21, 0 - .dw 0x5640, 0xc01c, 0x567f, 0xc01c, 0x21, 0 - .dw 0x56c0, 0xc01c, 0x56ff, 0xc01c, 0x21, 0 - .dw 0x5740, 0xc01c, 0x577f, 0xc01c, 0x21, 0 - .dw 0x57c0, 0xc01c, 0x57ff, 0xc01c, 0x21, 0 - .dw 0x5840, 0xc01c, 0x587f, 0xc01c, 0x21, 0 - .dw 0x58c0, 0xc01c, 0x58ff, 0xc01c, 0x21, 0 - .dw 0x5940, 0xc01c, 0x597f, 0xc01c, 0x21, 0 - .dw 0x59c0, 0xc01c, 0x5fff, 0xc01c, 0x21, 0 - .dw 0x6040, 0xc01c, 0x607f, 0xc01c, 0x21, 0 - .dw 0x60c0, 0xc01c, 0x60ff, 0xc01c, 0x21, 0 - .dw 0x6140, 0xc01c, 0x617f, 0xc01c, 0x21, 0 - .dw 0x61c0, 0xc01c, 0x61ff, 0xc01c, 0x21, 0 - .dw 0x6240, 0xc01c, 0x627f, 0xc01c, 0x21, 0 - .dw 0x62c0, 0xc01c, 0x62ff, 0xc01c, 0x21, 0 - .dw 0x6340, 0xc01c, 0x637f, 0xc01c, 0x21, 0 - .dw 0x63c0, 0xc01c, 0x63ff, 0xc01c, 0x21, 0 - .dw 0x6440, 0xc01c, 0x647f, 0xc01c, 0x21, 0 - .dw 0x64c0, 0xc01c, 0x64ff, 0xc01c, 0x21, 0 - .dw 0x6540, 0xc01c, 0x657f, 0xc01c, 0x21, 0 - .dw 0x65c0, 0xc01c, 0x65ff, 0xc01c, 0x21, 0 - .dw 0x6640, 0xc01c, 0x667f, 0xc01c, 0x21, 0 - .dw 0x66c0, 0xc01c, 0x66ff, 0xc01c, 0x21, 0 - .dw 0x6740, 0xc01c, 0x677f, 0xc01c, 0x21, 0 - .dw 0x67c0, 0xc01c, 0x67ff, 0xc01c, 0x21, 0 - .dw 0x6840, 0xc01c, 0x687f, 0xc01c, 0x21, 0 - .dw 0x68c0, 0xc01c, 0x68ff, 0xc01c, 0x21, 0 - .dw 0x6940, 0xc01c, 0x697f, 0xc01c, 0x21, 0 - .dw 0x69c0, 0xc01c, 0x69ff, 0xc01c, 0x21, 0 - .dw 0x6a40, 0xc01c, 0x6a7f, 0xc01c, 0x21, 0 - .dw 0x6ac0, 0xc01c, 0x6aff, 0xc01c, 0x21, 0 - .dw 0x6b40, 0xc01c, 0x6b7f, 0xc01c, 0x21, 0 - .dw 0x6bc0, 0xc01c, 0x6bff, 0xc01c, 0x21, 0 - .dw 0x6c40, 0xc01c, 0x6c7f, 0xc01c, 0x21, 0 - .dw 0x6cc0, 0xc01c, 0x6cff, 0xc01c, 0x21, 0 - .dw 0x6d40, 0xc01c, 0x6d7f, 0xc01c, 0x21, 0 - .dw 0x6dc0, 0xc01c, 0x6dff, 0xc01c, 0x21, 0 - .dw 0x6e40, 0xc01c, 0x6e7f, 0xc01c, 0x21, 0 - .dw 0x6ec0, 0xc01c, 0x6eff, 0xc01c, 0x21, 0 - .dw 0x6f40, 0xc01c, 0x6f7f, 0xc01c, 0x21, 0 - .dw 0x6fc0, 0xc01c, 0x6fff, 0xc01c, 0x21, 0 - .dw 0x7040, 0xc01c, 0x707f, 0xc01c, 0x21, 0 - .dw 0x70c0, 0xc01c, 0x70ff, 0xc01c, 0x21, 0 - .dw 0x7140, 0xc01c, 0x717f, 0xc01c, 0x21, 0 - .dw 0x71c0, 0xc01c, 0x71ff, 0xc01c, 0x21, 0 - .dw 0x7240, 0xc01c, 0x727f, 0xc01c, 0x21, 0 - .dw 0x72c0, 0xc01c, 0x72ff, 0xc01c, 0x21, 0 - .dw 0x7340, 0xc01c, 0x737f, 0xc01c, 0x21, 0 - .dw 0x73c0, 0xc01c, 0x73ff, 0xc01c, 0x21, 0 - .dw 0x7440, 0xc01c, 0x747f, 0xc01c, 0x21, 0 - .dw 0x74c0, 0xc01c, 0x74ff, 0xc01c, 0x21, 0 - .dw 0x7540, 0xc01c, 0x757f, 0xc01c, 0x21, 0 - .dw 0x75c0, 0xc01c, 0x75ff, 0xc01c, 0x21, 0 - .dw 0x7640, 0xc01c, 0x767f, 0xc01c, 0x21, 0 - .dw 0x76c0, 0xc01c, 0x76ff, 0xc01c, 0x21, 0 - .dw 0x7740, 0xc01c, 0x777f, 0xc01c, 0x21, 0 - .dw 0x77c0, 0xc01c, 0x77ff, 0xc01c, 0x21, 0 - .dw 0x7840, 0xc01c, 0x787f, 0xc01c, 0x21, 0 - .dw 0x78c0, 0xc01c, 0x78ff, 0xc01c, 0x21, 0 - .dw 0x7940, 0xc01c, 0x797f, 0xc01c, 0x21, 0 - .dw 0x79c0, 0xc01c, 0x7fff, 0xc01c, 0x21, 0 - .dw 0x8040, 0xc01c, 0x807f, 0xc01c, 0x21, 0 - .dw 0x80c0, 0xc01c, 0x80ff, 0xc01c, 0x21, 0 - .dw 0x8140, 0xc01c, 0x817f, 0xc01c, 0x21, 0 - .dw 0x81c0, 0xc01c, 0x81ff, 0xc01c, 0x21, 0 - .dw 0x8240, 0xc01c, 0x827f, 0xc01c, 0x21, 0 - .dw 0x82c0, 0xc01c, 0x82ff, 0xc01c, 0x21, 0 - .dw 0x8340, 0xc01c, 0x837f, 0xc01c, 0x21, 0 - .dw 0x83c0, 0xc01c, 0x83ff, 0xc01c, 0x21, 0 - .dw 0x8440, 0xc01c, 0x847f, 0xc01c, 0x21, 0 - .dw 0x84c0, 0xc01c, 0x84ff, 0xc01c, 0x21, 0 - .dw 0x8540, 0xc01c, 0x857f, 0xc01c, 0x21, 0 - .dw 0x85c0, 0xc01c, 0x85ff, 0xc01c, 0x21, 0 - .dw 0x8640, 0xc01c, 0x867f, 0xc01c, 0x21, 0 - .dw 0x86c0, 0xc01c, 0x86ff, 0xc01c, 0x21, 0 - .dw 0x8740, 0xc01c, 0x877f, 0xc01c, 0x21, 0 - .dw 0x87c0, 0xc01c, 0x87ff, 0xc01c, 0x21, 0 - .dw 0x8840, 0xc01c, 0x887f, 0xc01c, 0x21, 0 - .dw 0x88c0, 0xc01c, 0x88ff, 0xc01c, 0x21, 0 - .dw 0x8940, 0xc01c, 0x897f, 0xc01c, 0x21, 0 - .dw 0x89c0, 0xc01c, 0x89ff, 0xc01c, 0x21, 0 - .dw 0x8a40, 0xc01c, 0x8a7f, 0xc01c, 0x21, 0 - .dw 0x8ac0, 0xc01c, 0x8aff, 0xc01c, 0x21, 0 - .dw 0x8b40, 0xc01c, 0x8b7f, 0xc01c, 0x21, 0 - .dw 0x8bc0, 0xc01c, 0x8bff, 0xc01c, 0x21, 0 - .dw 0x8c40, 0xc01c, 0x8c7f, 0xc01c, 0x21, 0 - .dw 0x8cc0, 0xc01c, 0x8cff, 0xc01c, 0x21, 0 - .dw 0x8d40, 0xc01c, 0x8d7f, 0xc01c, 0x21, 0 - .dw 0x8dc0, 0xc01c, 0x8dff, 0xc01c, 0x21, 0 - .dw 0x8e40, 0xc01c, 0x8e7f, 0xc01c, 0x21, 0 - .dw 0x8ec0, 0xc01c, 0x8eff, 0xc01c, 0x21, 0 - .dw 0x8f40, 0xc01c, 0x8f7f, 0xc01c, 0x21, 0 - .dw 0x8fc0, 0xc01c, 0x8fff, 0xc01c, 0x21, 0 - .dw 0x9040, 0xc01c, 0x907f, 0xc01c, 0x21, 0 - .dw 0x90c0, 0xc01c, 0x90ff, 0xc01c, 0x21, 0 - .dw 0x9140, 0xc01c, 0x917f, 0xc01c, 0x21, 0 - .dw 0x91c0, 0xc01c, 0x91ff, 0xc01c, 0x21, 0 - .dw 0x9240, 0xc01c, 0x927f, 0xc01c, 0x21, 0 - .dw 0x92c0, 0xc01c, 0x92ff, 0xc01c, 0x21, 0 - .dw 0x9340, 0xc01c, 0x937f, 0xc01c, 0x21, 0 - .dw 0x93c0, 0xc01c, 0x93ff, 0xc01c, 0x21, 0 - .dw 0x9440, 0xc01c, 0x947f, 0xc01c, 0x21, 0 - .dw 0x94c0, 0xc01c, 0x94ff, 0xc01c, 0x21, 0 - .dw 0x9540, 0xc01c, 0x957f, 0xc01c, 0x21, 0 - .dw 0x95c0, 0xc01c, 0x95ff, 0xc01c, 0x21, 0 - .dw 0x9640, 0xc01c, 0x967f, 0xc01c, 0x21, 0 - .dw 0x96c0, 0xc01c, 0x96ff, 0xc01c, 0x21, 0 - .dw 0x9740, 0xc01c, 0x977f, 0xc01c, 0x21, 0 - .dw 0x97c0, 0xc01c, 0x97ff, 0xc01c, 0x21, 0 - .dw 0x9840, 0xc01c, 0x987f, 0xc01c, 0x21, 0 - .dw 0x98c0, 0xc01c, 0x98ff, 0xc01c, 0x21, 0 - .dw 0x9940, 0xc01c, 0x997f, 0xc01c, 0x21, 0 - .dw 0x99c0, 0xc01c, 0x9fff, 0xc01c, 0x21, 0 - .dw 0xa040, 0xc01c, 0xa07f, 0xc01c, 0x21, 0 - .dw 0xa0c0, 0xc01c, 0xa0ff, 0xc01c, 0x21, 0 - .dw 0xa140, 0xc01c, 0xa17f, 0xc01c, 0x21, 0 - .dw 0xa1c0, 0xc01c, 0xa1ff, 0xc01c, 0x21, 0 - .dw 0xa240, 0xc01c, 0xa27f, 0xc01c, 0x21, 0 - .dw 0xa2c0, 0xc01c, 0xa2ff, 0xc01c, 0x21, 0 - .dw 0xa340, 0xc01c, 0xa37f, 0xc01c, 0x21, 0 - .dw 0xa3c0, 0xc01c, 0xa3ff, 0xc01c, 0x21, 0 - .dw 0xa440, 0xc01c, 0xa47f, 0xc01c, 0x21, 0 - .dw 0xa4c0, 0xc01c, 0xa4ff, 0xc01c, 0x21, 0 - .dw 0xa540, 0xc01c, 0xa57f, 0xc01c, 0x21, 0 - .dw 0xa5c0, 0xc01c, 0xa5ff, 0xc01c, 0x21, 0 - .dw 0xa640, 0xc01c, 0xa67f, 0xc01c, 0x21, 0 - .dw 0xa6c0, 0xc01c, 0xa6ff, 0xc01c, 0x21, 0 - .dw 0xa740, 0xc01c, 0xa77f, 0xc01c, 0x21, 0 - .dw 0xa7c0, 0xc01c, 0xa7ff, 0xc01c, 0x21, 0 - .dw 0xa840, 0xc01c, 0xa87f, 0xc01c, 0x21, 0 - .dw 0xa8c0, 0xc01c, 0xa8ff, 0xc01c, 0x21, 0 - .dw 0xa940, 0xc01c, 0xa97f, 0xc01c, 0x21, 0 - .dw 0xa9c0, 0xc01c, 0xa9ff, 0xc01c, 0x21, 0 - .dw 0xaa40, 0xc01c, 0xaa7f, 0xc01c, 0x21, 0 - .dw 0xaac0, 0xc01c, 0xaaff, 0xc01c, 0x21, 0 - .dw 0xab40, 0xc01c, 0xab7f, 0xc01c, 0x21, 0 - .dw 0xabc0, 0xc01c, 0xabff, 0xc01c, 0x21, 0 - .dw 0xac40, 0xc01c, 0xac7f, 0xc01c, 0x21, 0 - .dw 0xacc0, 0xc01c, 0xacff, 0xc01c, 0x21, 0 - .dw 0xad40, 0xc01c, 0xad7f, 0xc01c, 0x21, 0 - .dw 0xadc0, 0xc01c, 0xadff, 0xc01c, 0x21, 0 - .dw 0xae40, 0xc01c, 0xae7f, 0xc01c, 0x21, 0 - .dw 0xaec0, 0xc01c, 0xaeff, 0xc01c, 0x21, 0 - .dw 0xaf40, 0xc01c, 0xaf7f, 0xc01c, 0x21, 0 - .dw 0xafc0, 0xc01c, 0xafff, 0xc01c, 0x21, 0 - .dw 0xb040, 0xc01c, 0xb07f, 0xc01c, 0x21, 0 - .dw 0xb0c0, 0xc01c, 0xb0ff, 0xc01c, 0x21, 0 - .dw 0xb140, 0xc01c, 0xb17f, 0xc01c, 0x21, 0 - .dw 0xb1c0, 0xc01c, 0xb1ff, 0xc01c, 0x21, 0 - .dw 0xb240, 0xc01c, 0xb27f, 0xc01c, 0x21, 0 - .dw 0xb2c0, 0xc01c, 0xb2ff, 0xc01c, 0x21, 0 - .dw 0xb340, 0xc01c, 0xb37f, 0xc01c, 0x21, 0 - .dw 0xb3c0, 0xc01c, 0xb3ff, 0xc01c, 0x21, 0 - .dw 0xb440, 0xc01c, 0xb47f, 0xc01c, 0x21, 0 - .dw 0xb4c0, 0xc01c, 0xb4ff, 0xc01c, 0x21, 0 - .dw 0xb540, 0xc01c, 0xb57f, 0xc01c, 0x21, 0 - .dw 0xb5c0, 0xc01c, 0xb5ff, 0xc01c, 0x21, 0 - .dw 0xb640, 0xc01c, 0xb67f, 0xc01c, 0x21, 0 - .dw 0xb6c0, 0xc01c, 0xb6ff, 0xc01c, 0x21, 0 - .dw 0xb740, 0xc01c, 0xb77f, 0xc01c, 0x21, 0 - .dw 0xb7c0, 0xc01c, 0xb7ff, 0xc01c, 0x21, 0 - .dw 0xb840, 0xc01c, 0xb87f, 0xc01c, 0x21, 0 - .dw 0xb8c0, 0xc01c, 0xb8ff, 0xc01c, 0x21, 0 - .dw 0xb940, 0xc01c, 0xb97f, 0xc01c, 0x21, 0 - .dw 0xb9c0, 0xc01c, 0xbfff, 0xc01c, 0x21, 0 - .dw 0xc040, 0xc01c, 0xc07f, 0xc01c, 0x21, 0 - .dw 0xc0c0, 0xc01c, 0xc0ff, 0xc01c, 0x21, 0 - .dw 0xc140, 0xc01c, 0xc17f, 0xc01c, 0x21, 0 - .dw 0xc1c0, 0xc01c, 0xc1ff, 0xc01c, 0x21, 0 - .dw 0xc240, 0xc01c, 0xc27f, 0xc01c, 0x21, 0 - .dw 0xc2c0, 0xc01c, 0xc2ff, 0xc01c, 0x21, 0 - .dw 0xc340, 0xc01c, 0xc37f, 0xc01c, 0x21, 0 - .dw 0xc3c0, 0xc01c, 0xc3ff, 0xc01c, 0x21, 0 - .dw 0xc440, 0xc01c, 0xc47f, 0xc01c, 0x21, 0 - .dw 0xc4c0, 0xc01c, 0xc4ff, 0xc01c, 0x21, 0 - .dw 0xc540, 0xc01c, 0xc57f, 0xc01c, 0x21, 0 - .dw 0xc5c0, 0xc01c, 0xc5ff, 0xc01c, 0x21, 0 - .dw 0xc640, 0xc01c, 0xc67f, 0xc01c, 0x21, 0 - .dw 0xc6c0, 0xc01c, 0xc6ff, 0xc01c, 0x21, 0 - .dw 0xc740, 0xc01c, 0xc77f, 0xc01c, 0x21, 0 - .dw 0xc7c0, 0xc01c, 0xc7ff, 0xc01c, 0x21, 0 - .dw 0xc840, 0xc01c, 0xc87f, 0xc01c, 0x21, 0 - .dw 0xc8c0, 0xc01c, 0xc8ff, 0xc01c, 0x21, 0 - .dw 0xc940, 0xc01c, 0xc97f, 0xc01c, 0x21, 0 - .dw 0xc9c0, 0xc01c, 0xc9ff, 0xc01c, 0x21, 0 - .dw 0xca40, 0xc01c, 0xca7f, 0xc01c, 0x21, 0 - .dw 0xcac0, 0xc01c, 0xcaff, 0xc01c, 0x21, 0 - .dw 0xcb40, 0xc01c, 0xcb7f, 0xc01c, 0x21, 0 - .dw 0xcbc0, 0xc01c, 0xcbff, 0xc01c, 0x21, 0 - .dw 0xcc40, 0xc01c, 0xcc7f, 0xc01c, 0x21, 0 - .dw 0xccc0, 0xc01c, 0xccff, 0xc01c, 0x21, 0 - .dw 0xcd40, 0xc01c, 0xcd7f, 0xc01c, 0x21, 0 - .dw 0xcdc0, 0xc01c, 0xcdff, 0xc01c, 0x21, 0 - .dw 0xce40, 0xc01c, 0xce7f, 0xc01c, 0x21, 0 - .dw 0xcec0, 0xc01c, 0xceff, 0xc01c, 0x21, 0 - .dw 0xcf40, 0xc01c, 0xcf7f, 0xc01c, 0x21, 0 - .dw 0xcfc0, 0xc01c, 0xcfff, 0xc01c, 0x21, 0 - .dw 0xd040, 0xc01c, 0xd07f, 0xc01c, 0x21, 0 - .dw 0xd0c0, 0xc01c, 0xd0ff, 0xc01c, 0x21, 0 - .dw 0xd140, 0xc01c, 0xd17f, 0xc01c, 0x21, 0 - .dw 0xd1c0, 0xc01c, 0xd1ff, 0xc01c, 0x21, 0 - .dw 0xd240, 0xc01c, 0xd27f, 0xc01c, 0x21, 0 - .dw 0xd2c0, 0xc01c, 0xd2ff, 0xc01c, 0x21, 0 - .dw 0xd340, 0xc01c, 0xd37f, 0xc01c, 0x21, 0 - .dw 0xd3c0, 0xc01c, 0xd3ff, 0xc01c, 0x21, 0 - .dw 0xd440, 0xc01c, 0xd47f, 0xc01c, 0x21, 0 - .dw 0xd4c0, 0xc01c, 0xd4ff, 0xc01c, 0x21, 0 - .dw 0xd540, 0xc01c, 0xd57f, 0xc01c, 0x21, 0 - .dw 0xd5c0, 0xc01c, 0xd5ff, 0xc01c, 0x21, 0 - .dw 0xd640, 0xc01c, 0xd67f, 0xc01c, 0x21, 0 - .dw 0xd6c0, 0xc01c, 0xd6ff, 0xc01c, 0x21, 0 - .dw 0xd740, 0xc01c, 0xd77f, 0xc01c, 0x21, 0 - .dw 0xd7c0, 0xc01c, 0xd7ff, 0xc01c, 0x21, 0 - .dw 0xd840, 0xc01c, 0xd87f, 0xc01c, 0x21, 0 - .dw 0xd8c0, 0xc01c, 0xd8ff, 0xc01c, 0x21, 0 - .dw 0xd940, 0xc01c, 0xd97f, 0xc01c, 0x21, 0 - .dw 0xd9c0, 0xc01c, 0xdfff, 0xc01c, 0x21, 0 - .dw 0xe040, 0xc01c, 0xe07f, 0xc01c, 0x21, 0 - .dw 0xe0c0, 0xc01c, 0xe0ff, 0xc01c, 0x21, 0 - .dw 0xe140, 0xc01c, 0xe17f, 0xc01c, 0x21, 0 - .dw 0xe1c0, 0xc01c, 0xe1ff, 0xc01c, 0x21, 0 - .dw 0xe240, 0xc01c, 0xe27f, 0xc01c, 0x21, 0 - .dw 0xe2c0, 0xc01c, 0xe2ff, 0xc01c, 0x21, 0 - .dw 0xe340, 0xc01c, 0xe37f, 0xc01c, 0x21, 0 - .dw 0xe3c0, 0xc01c, 0xe3ff, 0xc01c, 0x21, 0 - .dw 0xe440, 0xc01c, 0xe47f, 0xc01c, 0x21, 0 - .dw 0xe4c0, 0xc01c, 0xe4ff, 0xc01c, 0x21, 0 - .dw 0xe540, 0xc01c, 0xe57f, 0xc01c, 0x21, 0 - .dw 0xe5c0, 0xc01c, 0xe5ff, 0xc01c, 0x21, 0 - .dw 0xe640, 0xc01c, 0xe67f, 0xc01c, 0x21, 0 - .dw 0xe6c0, 0xc01c, 0xe6ff, 0xc01c, 0x21, 0 - .dw 0xe740, 0xc01c, 0xe77f, 0xc01c, 0x21, 0 - .dw 0xe7c0, 0xc01c, 0xe7ff, 0xc01c, 0x21, 0 - .dw 0xe840, 0xc01c, 0xe87f, 0xc01c, 0x21, 0 - .dw 0xe8c0, 0xc01c, 0xe8ff, 0xc01c, 0x21, 0 - .dw 0xe940, 0xc01c, 0xe97f, 0xc01c, 0x21, 0 - .dw 0xe9c0, 0xc01c, 0xe9ff, 0xc01c, 0x21, 0 - .dw 0xea40, 0xc01c, 0xea7f, 0xc01c, 0x21, 0 - .dw 0xeac0, 0xc01c, 0xeaff, 0xc01c, 0x21, 0 - .dw 0xeb40, 0xc01c, 0xeb7f, 0xc01c, 0x21, 0 - .dw 0xebc0, 0xc01c, 0xebff, 0xc01c, 0x21, 0 - .dw 0xec40, 0xc01c, 0xec7f, 0xc01c, 0x21, 0 - .dw 0xecc0, 0xc01c, 0xecff, 0xc01c, 0x21, 0 - .dw 0xed40, 0xc01c, 0xed7f, 0xc01c, 0x21, 0 - .dw 0xedc0, 0xc01c, 0xedff, 0xc01c, 0x21, 0 - .dw 0xee40, 0xc01c, 0xee7f, 0xc01c, 0x21, 0 - .dw 0xeec0, 0xc01c, 0xeeff, 0xc01c, 0x21, 0 - .dw 0xef40, 0xc01c, 0xef7f, 0xc01c, 0x21, 0 - .dw 0xefc0, 0xc01c, 0xefff, 0xc01c, 0x21, 0 - .dw 0xf040, 0xc01c, 0xf07f, 0xc01c, 0x21, 0 - .dw 0xf0c0, 0xc01c, 0xf0ff, 0xc01c, 0x21, 0 - .dw 0xf140, 0xc01c, 0xf17f, 0xc01c, 0x21, 0 - .dw 0xf1c0, 0xc01c, 0xf1ff, 0xc01c, 0x21, 0 - .dw 0xf240, 0xc01c, 0xf27f, 0xc01c, 0x21, 0 - .dw 0xf2c0, 0xc01c, 0xf2ff, 0xc01c, 0x21, 0 - .dw 0xf340, 0xc01c, 0xf37f, 0xc01c, 0x21, 0 - .dw 0xf3c0, 0xc01c, 0xf3ff, 0xc01c, 0x21, 0 - .dw 0xf440, 0xc01c, 0xf47f, 0xc01c, 0x21, 0 - .dw 0xf4c0, 0xc01c, 0xf4ff, 0xc01c, 0x21, 0 - .dw 0xf540, 0xc01c, 0xf57f, 0xc01c, 0x21, 0 - .dw 0xf5c0, 0xc01c, 0xf5ff, 0xc01c, 0x21, 0 - .dw 0xf640, 0xc01c, 0xf67f, 0xc01c, 0x21, 0 - .dw 0xf6c0, 0xc01c, 0xf6ff, 0xc01c, 0x21, 0 - .dw 0xf740, 0xc01c, 0xf77f, 0xc01c, 0x21, 0 - .dw 0xf7c0, 0xc01c, 0xf7ff, 0xc01c, 0x21, 0 - .dw 0xf840, 0xc01c, 0xf87f, 0xc01c, 0x21, 0 - .dw 0xf8c0, 0xc01c, 0xf8ff, 0xc01c, 0x21, 0 - .dw 0xf940, 0xc01c, 0xf97f, 0xc01c, 0x21, 0 - .dw 0xf9c0, 0xc01c, 0xffff, 0xc01c, 0x21, 0 - .dw 0x0040, 0xc01d, 0x007f, 0xc01d, 0x21, 0 - .dw 0x00c0, 0xc01d, 0x00ff, 0xc01d, 0x21, 0 - .dw 0x0140, 0xc01d, 0x017f, 0xc01d, 0x21, 0 - .dw 0x01c0, 0xc01d, 0x01ff, 0xc01d, 0x21, 0 - .dw 0x0240, 0xc01d, 0x027f, 0xc01d, 0x21, 0 - .dw 0x02c0, 0xc01d, 0x02ff, 0xc01d, 0x21, 0 - .dw 0x0340, 0xc01d, 0x037f, 0xc01d, 0x21, 0 - .dw 0x03c0, 0xc01d, 0x03ff, 0xc01d, 0x21, 0 - .dw 0x0440, 0xc01d, 0x047f, 0xc01d, 0x21, 0 - .dw 0x04c0, 0xc01d, 0x04ff, 0xc01d, 0x21, 0 - .dw 0x0540, 0xc01d, 0x057f, 0xc01d, 0x21, 0 - .dw 0x05c0, 0xc01d, 0x05ff, 0xc01d, 0x21, 0 - .dw 0x0640, 0xc01d, 0x067f, 0xc01d, 0x21, 0 - .dw 0x06c0, 0xc01d, 0x06ff, 0xc01d, 0x21, 0 - .dw 0x0740, 0xc01d, 0x077f, 0xc01d, 0x21, 0 - .dw 0x07c0, 0xc01d, 0x07ff, 0xc01d, 0x21, 0 - .dw 0x0840, 0xc01d, 0x087f, 0xc01d, 0x21, 0 - .dw 0x08c0, 0xc01d, 0x08ff, 0xc01d, 0x21, 0 - .dw 0x0940, 0xc01d, 0x097f, 0xc01d, 0x21, 0 - .dw 0x09c0, 0xc01d, 0x09ff, 0xc01d, 0x21, 0 - .dw 0x0a40, 0xc01d, 0x0a7f, 0xc01d, 0x21, 0 - .dw 0x0ac0, 0xc01d, 0x0aff, 0xc01d, 0x21, 0 - .dw 0x0b40, 0xc01d, 0x0b7f, 0xc01d, 0x21, 0 - .dw 0x0bc0, 0xc01d, 0x0bff, 0xc01d, 0x21, 0 - .dw 0x0c40, 0xc01d, 0x0c7f, 0xc01d, 0x21, 0 - .dw 0x0cc0, 0xc01d, 0x0cff, 0xc01d, 0x21, 0 - .dw 0x0d40, 0xc01d, 0x0d7f, 0xc01d, 0x21, 0 - .dw 0x0dc0, 0xc01d, 0x0dff, 0xc01d, 0x21, 0 - .dw 0x0e40, 0xc01d, 0x0e7f, 0xc01d, 0x21, 0 - .dw 0x0ec0, 0xc01d, 0x0eff, 0xc01d, 0x21, 0 - .dw 0x0f40, 0xc01d, 0x0f7f, 0xc01d, 0x21, 0 - .dw 0x0fc0, 0xc01d, 0x0fff, 0xc01d, 0x21, 0 - .dw 0x1040, 0xc01d, 0x107f, 0xc01d, 0x21, 0 - .dw 0x10c0, 0xc01d, 0x10ff, 0xc01d, 0x21, 0 - .dw 0x1140, 0xc01d, 0x117f, 0xc01d, 0x21, 0 - .dw 0x11c0, 0xc01d, 0x11ff, 0xc01d, 0x21, 0 - .dw 0x1240, 0xc01d, 0x127f, 0xc01d, 0x21, 0 - .dw 0x12c0, 0xc01d, 0x12ff, 0xc01d, 0x21, 0 - .dw 0x1340, 0xc01d, 0x137f, 0xc01d, 0x21, 0 - .dw 0x13c0, 0xc01d, 0x13ff, 0xc01d, 0x21, 0 - .dw 0x1440, 0xc01d, 0x147f, 0xc01d, 0x21, 0 - .dw 0x14c0, 0xc01d, 0x14ff, 0xc01d, 0x21, 0 - .dw 0x1540, 0xc01d, 0x157f, 0xc01d, 0x21, 0 - .dw 0x15c0, 0xc01d, 0x15ff, 0xc01d, 0x21, 0 - .dw 0x1640, 0xc01d, 0x167f, 0xc01d, 0x21, 0 - .dw 0x16c0, 0xc01d, 0x16ff, 0xc01d, 0x21, 0 - .dw 0x1740, 0xc01d, 0x177f, 0xc01d, 0x21, 0 - .dw 0x17c0, 0xc01d, 0x17ff, 0xc01d, 0x21, 0 - .dw 0x1840, 0xc01d, 0x187f, 0xc01d, 0x21, 0 - .dw 0x18c0, 0xc01d, 0x18ff, 0xc01d, 0x21, 0 - .dw 0x1940, 0xc01d, 0x197f, 0xc01d, 0x21, 0 - .dw 0x19c0, 0xc01d, 0x1fff, 0xc01d, 0x21, 0 - .dw 0x2040, 0xc01d, 0x207f, 0xc01d, 0x21, 0 - .dw 0x20c0, 0xc01d, 0x20ff, 0xc01d, 0x21, 0 - .dw 0x2140, 0xc01d, 0x217f, 0xc01d, 0x21, 0 - .dw 0x21c0, 0xc01d, 0x21ff, 0xc01d, 0x21, 0 - .dw 0x2240, 0xc01d, 0x227f, 0xc01d, 0x21, 0 - .dw 0x22c0, 0xc01d, 0x22ff, 0xc01d, 0x21, 0 - .dw 0x2340, 0xc01d, 0x237f, 0xc01d, 0x21, 0 - .dw 0x23c0, 0xc01d, 0x23ff, 0xc01d, 0x21, 0 - .dw 0x2440, 0xc01d, 0x247f, 0xc01d, 0x21, 0 - .dw 0x24c0, 0xc01d, 0x24ff, 0xc01d, 0x21, 0 - .dw 0x2540, 0xc01d, 0x257f, 0xc01d, 0x21, 0 - .dw 0x25c0, 0xc01d, 0x25ff, 0xc01d, 0x21, 0 - .dw 0x2640, 0xc01d, 0x267f, 0xc01d, 0x21, 0 - .dw 0x26c0, 0xc01d, 0x26ff, 0xc01d, 0x21, 0 - .dw 0x2740, 0xc01d, 0x277f, 0xc01d, 0x21, 0 - .dw 0x27c0, 0xc01d, 0x27ff, 0xc01d, 0x21, 0 - .dw 0x2840, 0xc01d, 0x287f, 0xc01d, 0x21, 0 - .dw 0x28c0, 0xc01d, 0x28ff, 0xc01d, 0x21, 0 - .dw 0x2940, 0xc01d, 0x297f, 0xc01d, 0x21, 0 - .dw 0x29c0, 0xc01d, 0x29ff, 0xc01d, 0x21, 0 - .dw 0x2a40, 0xc01d, 0x2a7f, 0xc01d, 0x21, 0 - .dw 0x2ac0, 0xc01d, 0x2aff, 0xc01d, 0x21, 0 - .dw 0x2b40, 0xc01d, 0x2b7f, 0xc01d, 0x21, 0 - .dw 0x2bc0, 0xc01d, 0x2bff, 0xc01d, 0x21, 0 - .dw 0x2c40, 0xc01d, 0x2c7f, 0xc01d, 0x21, 0 - .dw 0x2cc0, 0xc01d, 0x2cff, 0xc01d, 0x21, 0 - .dw 0x2d40, 0xc01d, 0x2d7f, 0xc01d, 0x21, 0 - .dw 0x2dc0, 0xc01d, 0x2dff, 0xc01d, 0x21, 0 - .dw 0x2e40, 0xc01d, 0x2e7f, 0xc01d, 0x21, 0 - .dw 0x2ec0, 0xc01d, 0x2eff, 0xc01d, 0x21, 0 - .dw 0x2f40, 0xc01d, 0x2f7f, 0xc01d, 0x21, 0 - .dw 0x2fc0, 0xc01d, 0x2fff, 0xc01d, 0x21, 0 - .dw 0x3040, 0xc01d, 0x307f, 0xc01d, 0x21, 0 - .dw 0x30c0, 0xc01d, 0x30ff, 0xc01d, 0x21, 0 - .dw 0x3140, 0xc01d, 0x317f, 0xc01d, 0x21, 0 - .dw 0x31c0, 0xc01d, 0x31ff, 0xc01d, 0x21, 0 - .dw 0x3240, 0xc01d, 0x327f, 0xc01d, 0x21, 0 - .dw 0x32c0, 0xc01d, 0x32ff, 0xc01d, 0x21, 0 - .dw 0x3340, 0xc01d, 0x337f, 0xc01d, 0x21, 0 - .dw 0x33c0, 0xc01d, 0x33ff, 0xc01d, 0x21, 0 - .dw 0x3440, 0xc01d, 0x347f, 0xc01d, 0x21, 0 - .dw 0x34c0, 0xc01d, 0x34ff, 0xc01d, 0x21, 0 - .dw 0x3540, 0xc01d, 0x357f, 0xc01d, 0x21, 0 - .dw 0x35c0, 0xc01d, 0x35ff, 0xc01d, 0x21, 0 - .dw 0x3640, 0xc01d, 0x367f, 0xc01d, 0x21, 0 - .dw 0x36c0, 0xc01d, 0x36ff, 0xc01d, 0x21, 0 - .dw 0x3740, 0xc01d, 0x377f, 0xc01d, 0x21, 0 - .dw 0x37c0, 0xc01d, 0x37ff, 0xc01d, 0x21, 0 - .dw 0x3840, 0xc01d, 0x387f, 0xc01d, 0x21, 0 - .dw 0x38c0, 0xc01d, 0x38ff, 0xc01d, 0x21, 0 - .dw 0x3940, 0xc01d, 0x397f, 0xc01d, 0x21, 0 - .dw 0x39c0, 0xc01d, 0x3fff, 0xc01d, 0x21, 0 - .dw 0x4040, 0xc01d, 0x407f, 0xc01d, 0x21, 0 - .dw 0x40c0, 0xc01d, 0x40ff, 0xc01d, 0x21, 0 - .dw 0x4140, 0xc01d, 0x417f, 0xc01d, 0x21, 0 - .dw 0x41c0, 0xc01d, 0x41ff, 0xc01d, 0x21, 0 - .dw 0x4240, 0xc01d, 0x427f, 0xc01d, 0x21, 0 - .dw 0x42c0, 0xc01d, 0x42ff, 0xc01d, 0x21, 0 - .dw 0x4340, 0xc01d, 0x437f, 0xc01d, 0x21, 0 - .dw 0x43c0, 0xc01d, 0x43ff, 0xc01d, 0x21, 0 - .dw 0x4440, 0xc01d, 0x447f, 0xc01d, 0x21, 0 - .dw 0x44c0, 0xc01d, 0x44ff, 0xc01d, 0x21, 0 - .dw 0x4540, 0xc01d, 0x457f, 0xc01d, 0x21, 0 - .dw 0x45c0, 0xc01d, 0x45ff, 0xc01d, 0x21, 0 - .dw 0x4640, 0xc01d, 0x467f, 0xc01d, 0x21, 0 - .dw 0x46c0, 0xc01d, 0x46ff, 0xc01d, 0x21, 0 - .dw 0x4740, 0xc01d, 0x477f, 0xc01d, 0x21, 0 - .dw 0x47c0, 0xc01d, 0x47ff, 0xc01d, 0x21, 0 - .dw 0x4840, 0xc01d, 0x487f, 0xc01d, 0x21, 0 - .dw 0x48c0, 0xc01d, 0x48ff, 0xc01d, 0x21, 0 - .dw 0x4940, 0xc01d, 0x497f, 0xc01d, 0x21, 0 - .dw 0x49c0, 0xc01d, 0x49ff, 0xc01d, 0x21, 0 - .dw 0x4a40, 0xc01d, 0x4a7f, 0xc01d, 0x21, 0 - .dw 0x4ac0, 0xc01d, 0x4aff, 0xc01d, 0x21, 0 - .dw 0x4b40, 0xc01d, 0x4b7f, 0xc01d, 0x21, 0 - .dw 0x4bc0, 0xc01d, 0x4bff, 0xc01d, 0x21, 0 - .dw 0x4c40, 0xc01d, 0x4c7f, 0xc01d, 0x21, 0 - .dw 0x4cc0, 0xc01d, 0x4cff, 0xc01d, 0x21, 0 - .dw 0x4d40, 0xc01d, 0x4d7f, 0xc01d, 0x21, 0 - .dw 0x4dc0, 0xc01d, 0x4dff, 0xc01d, 0x21, 0 - .dw 0x4e40, 0xc01d, 0x4e7f, 0xc01d, 0x21, 0 - .dw 0x4ec0, 0xc01d, 0x4eff, 0xc01d, 0x21, 0 - .dw 0x4f40, 0xc01d, 0x4f7f, 0xc01d, 0x21, 0 - .dw 0x4fc0, 0xc01d, 0x4fff, 0xc01d, 0x21, 0 - .dw 0x5040, 0xc01d, 0x507f, 0xc01d, 0x21, 0 - .dw 0x50c0, 0xc01d, 0x50ff, 0xc01d, 0x21, 0 - .dw 0x5140, 0xc01d, 0x517f, 0xc01d, 0x21, 0 - .dw 0x51c0, 0xc01d, 0x51ff, 0xc01d, 0x21, 0 - .dw 0x5240, 0xc01d, 0x527f, 0xc01d, 0x21, 0 - .dw 0x52c0, 0xc01d, 0x52ff, 0xc01d, 0x21, 0 - .dw 0x5340, 0xc01d, 0x537f, 0xc01d, 0x21, 0 - .dw 0x53c0, 0xc01d, 0x53ff, 0xc01d, 0x21, 0 - .dw 0x5440, 0xc01d, 0x547f, 0xc01d, 0x21, 0 - .dw 0x54c0, 0xc01d, 0x54ff, 0xc01d, 0x21, 0 - .dw 0x5540, 0xc01d, 0x557f, 0xc01d, 0x21, 0 - .dw 0x55c0, 0xc01d, 0x55ff, 0xc01d, 0x21, 0 - .dw 0x5640, 0xc01d, 0x567f, 0xc01d, 0x21, 0 - .dw 0x56c0, 0xc01d, 0x56ff, 0xc01d, 0x21, 0 - .dw 0x5740, 0xc01d, 0x577f, 0xc01d, 0x21, 0 - .dw 0x57c0, 0xc01d, 0x57ff, 0xc01d, 0x21, 0 - .dw 0x5840, 0xc01d, 0x587f, 0xc01d, 0x21, 0 - .dw 0x58c0, 0xc01d, 0x58ff, 0xc01d, 0x21, 0 - .dw 0x5940, 0xc01d, 0x597f, 0xc01d, 0x21, 0 - .dw 0x59c0, 0xc01d, 0x5fff, 0xc01d, 0x21, 0 - .dw 0x6040, 0xc01d, 0x607f, 0xc01d, 0x21, 0 - .dw 0x60c0, 0xc01d, 0x60ff, 0xc01d, 0x21, 0 - .dw 0x6140, 0xc01d, 0x617f, 0xc01d, 0x21, 0 - .dw 0x61c0, 0xc01d, 0x61ff, 0xc01d, 0x21, 0 - .dw 0x6240, 0xc01d, 0x627f, 0xc01d, 0x21, 0 - .dw 0x62c0, 0xc01d, 0x62ff, 0xc01d, 0x21, 0 - .dw 0x6340, 0xc01d, 0x637f, 0xc01d, 0x21, 0 - .dw 0x63c0, 0xc01d, 0x63ff, 0xc01d, 0x21, 0 - .dw 0x6440, 0xc01d, 0x647f, 0xc01d, 0x21, 0 - .dw 0x64c0, 0xc01d, 0x64ff, 0xc01d, 0x21, 0 - .dw 0x6540, 0xc01d, 0x657f, 0xc01d, 0x21, 0 - .dw 0x65c0, 0xc01d, 0x65ff, 0xc01d, 0x21, 0 - .dw 0x6640, 0xc01d, 0x667f, 0xc01d, 0x21, 0 - .dw 0x66c0, 0xc01d, 0x66ff, 0xc01d, 0x21, 0 - .dw 0x6740, 0xc01d, 0x677f, 0xc01d, 0x21, 0 - .dw 0x67c0, 0xc01d, 0x67ff, 0xc01d, 0x21, 0 - .dw 0x6840, 0xc01d, 0x687f, 0xc01d, 0x21, 0 - .dw 0x68c0, 0xc01d, 0x68ff, 0xc01d, 0x21, 0 - .dw 0x6940, 0xc01d, 0x697f, 0xc01d, 0x21, 0 - .dw 0x69c0, 0xc01d, 0x69ff, 0xc01d, 0x21, 0 - .dw 0x6a40, 0xc01d, 0x6a7f, 0xc01d, 0x21, 0 - .dw 0x6ac0, 0xc01d, 0x6aff, 0xc01d, 0x21, 0 - .dw 0x6b40, 0xc01d, 0x6b7f, 0xc01d, 0x21, 0 - .dw 0x6bc0, 0xc01d, 0x6bff, 0xc01d, 0x21, 0 - .dw 0x6c40, 0xc01d, 0x6c7f, 0xc01d, 0x21, 0 - .dw 0x6cc0, 0xc01d, 0x6cff, 0xc01d, 0x21, 0 - .dw 0x6d40, 0xc01d, 0x6d7f, 0xc01d, 0x21, 0 - .dw 0x6dc0, 0xc01d, 0x6dff, 0xc01d, 0x21, 0 - .dw 0x6e40, 0xc01d, 0x6e7f, 0xc01d, 0x21, 0 - .dw 0x6ec0, 0xc01d, 0x6eff, 0xc01d, 0x21, 0 - .dw 0x6f40, 0xc01d, 0x6f7f, 0xc01d, 0x21, 0 - .dw 0x6fc0, 0xc01d, 0x6fff, 0xc01d, 0x21, 0 - .dw 0x7040, 0xc01d, 0x707f, 0xc01d, 0x21, 0 - .dw 0x70c0, 0xc01d, 0x70ff, 0xc01d, 0x21, 0 - .dw 0x7140, 0xc01d, 0x717f, 0xc01d, 0x21, 0 - .dw 0x71c0, 0xc01d, 0x71ff, 0xc01d, 0x21, 0 - .dw 0x7240, 0xc01d, 0x727f, 0xc01d, 0x21, 0 - .dw 0x72c0, 0xc01d, 0x72ff, 0xc01d, 0x21, 0 - .dw 0x7340, 0xc01d, 0x737f, 0xc01d, 0x21, 0 - .dw 0x73c0, 0xc01d, 0x73ff, 0xc01d, 0x21, 0 - .dw 0x7440, 0xc01d, 0x747f, 0xc01d, 0x21, 0 - .dw 0x74c0, 0xc01d, 0x74ff, 0xc01d, 0x21, 0 - .dw 0x7540, 0xc01d, 0x757f, 0xc01d, 0x21, 0 - .dw 0x75c0, 0xc01d, 0x75ff, 0xc01d, 0x21, 0 - .dw 0x7640, 0xc01d, 0x767f, 0xc01d, 0x21, 0 - .dw 0x76c0, 0xc01d, 0x76ff, 0xc01d, 0x21, 0 - .dw 0x7740, 0xc01d, 0x777f, 0xc01d, 0x21, 0 - .dw 0x77c0, 0xc01d, 0x77ff, 0xc01d, 0x21, 0 - .dw 0x7840, 0xc01d, 0x787f, 0xc01d, 0x21, 0 - .dw 0x78c0, 0xc01d, 0x78ff, 0xc01d, 0x21, 0 - .dw 0x7940, 0xc01d, 0x797f, 0xc01d, 0x21, 0 - .dw 0x79c0, 0xc01d, 0x7fff, 0xc01d, 0x21, 0 - .dw 0x8040, 0xc01d, 0x807f, 0xc01d, 0x21, 0 - .dw 0x80c0, 0xc01d, 0x80ff, 0xc01d, 0x21, 0 - .dw 0x8140, 0xc01d, 0x817f, 0xc01d, 0x21, 0 - .dw 0x81c0, 0xc01d, 0x81ff, 0xc01d, 0x21, 0 - .dw 0x8240, 0xc01d, 0x827f, 0xc01d, 0x21, 0 - .dw 0x82c0, 0xc01d, 0x82ff, 0xc01d, 0x21, 0 - .dw 0x8340, 0xc01d, 0x837f, 0xc01d, 0x21, 0 - .dw 0x83c0, 0xc01d, 0x83ff, 0xc01d, 0x21, 0 - .dw 0x8440, 0xc01d, 0x847f, 0xc01d, 0x21, 0 - .dw 0x84c0, 0xc01d, 0x84ff, 0xc01d, 0x21, 0 - .dw 0x8540, 0xc01d, 0x857f, 0xc01d, 0x21, 0 - .dw 0x85c0, 0xc01d, 0x85ff, 0xc01d, 0x21, 0 - .dw 0x8640, 0xc01d, 0x867f, 0xc01d, 0x21, 0 - .dw 0x86c0, 0xc01d, 0x86ff, 0xc01d, 0x21, 0 - .dw 0x8740, 0xc01d, 0x877f, 0xc01d, 0x21, 0 - .dw 0x87c0, 0xc01d, 0x87ff, 0xc01d, 0x21, 0 - .dw 0x8840, 0xc01d, 0x887f, 0xc01d, 0x21, 0 - .dw 0x88c0, 0xc01d, 0x88ff, 0xc01d, 0x21, 0 - .dw 0x8940, 0xc01d, 0x897f, 0xc01d, 0x21, 0 - .dw 0x89c0, 0xc01d, 0x89ff, 0xc01d, 0x21, 0 - .dw 0x8a40, 0xc01d, 0x8a7f, 0xc01d, 0x21, 0 - .dw 0x8ac0, 0xc01d, 0x8aff, 0xc01d, 0x21, 0 - .dw 0x8b40, 0xc01d, 0x8b7f, 0xc01d, 0x21, 0 - .dw 0x8bc0, 0xc01d, 0x8bff, 0xc01d, 0x21, 0 - .dw 0x8c40, 0xc01d, 0x8c7f, 0xc01d, 0x21, 0 - .dw 0x8cc0, 0xc01d, 0x8cff, 0xc01d, 0x21, 0 - .dw 0x8d40, 0xc01d, 0x8d7f, 0xc01d, 0x21, 0 - .dw 0x8dc0, 0xc01d, 0x8dff, 0xc01d, 0x21, 0 - .dw 0x8e40, 0xc01d, 0x8e7f, 0xc01d, 0x21, 0 - .dw 0x8ec0, 0xc01d, 0x8eff, 0xc01d, 0x21, 0 - .dw 0x8f40, 0xc01d, 0x8f7f, 0xc01d, 0x21, 0 - .dw 0x8fc0, 0xc01d, 0x8fff, 0xc01d, 0x21, 0 - .dw 0x9040, 0xc01d, 0x907f, 0xc01d, 0x21, 0 - .dw 0x90c0, 0xc01d, 0x90ff, 0xc01d, 0x21, 0 - .dw 0x9140, 0xc01d, 0x917f, 0xc01d, 0x21, 0 - .dw 0x91c0, 0xc01d, 0x91ff, 0xc01d, 0x21, 0 - .dw 0x9240, 0xc01d, 0x927f, 0xc01d, 0x21, 0 - .dw 0x92c0, 0xc01d, 0x92ff, 0xc01d, 0x21, 0 - .dw 0x9340, 0xc01d, 0x937f, 0xc01d, 0x21, 0 - .dw 0x93c0, 0xc01d, 0x93ff, 0xc01d, 0x21, 0 - .dw 0x9440, 0xc01d, 0x947f, 0xc01d, 0x21, 0 - .dw 0x94c0, 0xc01d, 0x94ff, 0xc01d, 0x21, 0 - .dw 0x9540, 0xc01d, 0x957f, 0xc01d, 0x21, 0 - .dw 0x95c0, 0xc01d, 0x95ff, 0xc01d, 0x21, 0 - .dw 0x9640, 0xc01d, 0x967f, 0xc01d, 0x21, 0 - .dw 0x96c0, 0xc01d, 0x96ff, 0xc01d, 0x21, 0 - .dw 0x9740, 0xc01d, 0x977f, 0xc01d, 0x21, 0 - .dw 0x97c0, 0xc01d, 0x97ff, 0xc01d, 0x21, 0 - .dw 0x9840, 0xc01d, 0x987f, 0xc01d, 0x21, 0 - .dw 0x98c0, 0xc01d, 0x98ff, 0xc01d, 0x21, 0 - .dw 0x9940, 0xc01d, 0x997f, 0xc01d, 0x21, 0 - .dw 0x99c0, 0xc01d, 0x9fff, 0xc01d, 0x21, 0 - .dw 0xa040, 0xc01d, 0xa07f, 0xc01d, 0x21, 0 - .dw 0xa0c0, 0xc01d, 0xa0ff, 0xc01d, 0x21, 0 - .dw 0xa140, 0xc01d, 0xa17f, 0xc01d, 0x21, 0 - .dw 0xa1c0, 0xc01d, 0xa1ff, 0xc01d, 0x21, 0 - .dw 0xa240, 0xc01d, 0xa27f, 0xc01d, 0x21, 0 - .dw 0xa2c0, 0xc01d, 0xa2ff, 0xc01d, 0x21, 0 - .dw 0xa340, 0xc01d, 0xa37f, 0xc01d, 0x21, 0 - .dw 0xa3c0, 0xc01d, 0xa3ff, 0xc01d, 0x21, 0 - .dw 0xa440, 0xc01d, 0xa47f, 0xc01d, 0x21, 0 - .dw 0xa4c0, 0xc01d, 0xa4ff, 0xc01d, 0x21, 0 - .dw 0xa540, 0xc01d, 0xa57f, 0xc01d, 0x21, 0 - .dw 0xa5c0, 0xc01d, 0xa5ff, 0xc01d, 0x21, 0 - .dw 0xa640, 0xc01d, 0xa67f, 0xc01d, 0x21, 0 - .dw 0xa6c0, 0xc01d, 0xa6ff, 0xc01d, 0x21, 0 - .dw 0xa740, 0xc01d, 0xa77f, 0xc01d, 0x21, 0 - .dw 0xa7c0, 0xc01d, 0xa7ff, 0xc01d, 0x21, 0 - .dw 0xa840, 0xc01d, 0xa87f, 0xc01d, 0x21, 0 - .dw 0xa8c0, 0xc01d, 0xa8ff, 0xc01d, 0x21, 0 - .dw 0xa940, 0xc01d, 0xa97f, 0xc01d, 0x21, 0 - .dw 0xa9c0, 0xc01d, 0xa9ff, 0xc01d, 0x21, 0 - .dw 0xaa40, 0xc01d, 0xaa7f, 0xc01d, 0x21, 0 - .dw 0xaac0, 0xc01d, 0xaaff, 0xc01d, 0x21, 0 - .dw 0xab40, 0xc01d, 0xab7f, 0xc01d, 0x21, 0 - .dw 0xabc0, 0xc01d, 0xabff, 0xc01d, 0x21, 0 - .dw 0xac40, 0xc01d, 0xac7f, 0xc01d, 0x21, 0 - .dw 0xacc0, 0xc01d, 0xacff, 0xc01d, 0x21, 0 - .dw 0xad40, 0xc01d, 0xad7f, 0xc01d, 0x21, 0 - .dw 0xadc0, 0xc01d, 0xadff, 0xc01d, 0x21, 0 - .dw 0xae40, 0xc01d, 0xae7f, 0xc01d, 0x21, 0 - .dw 0xaec0, 0xc01d, 0xaeff, 0xc01d, 0x21, 0 - .dw 0xaf40, 0xc01d, 0xaf7f, 0xc01d, 0x21, 0 - .dw 0xafc0, 0xc01d, 0xafff, 0xc01d, 0x21, 0 - .dw 0xb040, 0xc01d, 0xb07f, 0xc01d, 0x21, 0 - .dw 0xb0c0, 0xc01d, 0xb0ff, 0xc01d, 0x21, 0 - .dw 0xb140, 0xc01d, 0xb17f, 0xc01d, 0x21, 0 - .dw 0xb1c0, 0xc01d, 0xb1ff, 0xc01d, 0x21, 0 - .dw 0xb240, 0xc01d, 0xb27f, 0xc01d, 0x21, 0 - .dw 0xb2c0, 0xc01d, 0xb2ff, 0xc01d, 0x21, 0 - .dw 0xb340, 0xc01d, 0xb37f, 0xc01d, 0x21, 0 - .dw 0xb3c0, 0xc01d, 0xb3ff, 0xc01d, 0x21, 0 - .dw 0xb440, 0xc01d, 0xb47f, 0xc01d, 0x21, 0 - .dw 0xb4c0, 0xc01d, 0xb4ff, 0xc01d, 0x21, 0 - .dw 0xb540, 0xc01d, 0xb57f, 0xc01d, 0x21, 0 - .dw 0xb5c0, 0xc01d, 0xb5ff, 0xc01d, 0x21, 0 - .dw 0xb640, 0xc01d, 0xb67f, 0xc01d, 0x21, 0 - .dw 0xb6c0, 0xc01d, 0xb6ff, 0xc01d, 0x21, 0 - .dw 0xb740, 0xc01d, 0xb77f, 0xc01d, 0x21, 0 - .dw 0xb7c0, 0xc01d, 0xb7ff, 0xc01d, 0x21, 0 - .dw 0xb840, 0xc01d, 0xb87f, 0xc01d, 0x21, 0 - .dw 0xb8c0, 0xc01d, 0xb8ff, 0xc01d, 0x21, 0 - .dw 0xb940, 0xc01d, 0xb97f, 0xc01d, 0x21, 0 - .dw 0xb9c0, 0xc01d, 0xbfff, 0xc01d, 0x21, 0 - .dw 0xc040, 0xc01d, 0xc07f, 0xc01d, 0x21, 0 - .dw 0xc0c0, 0xc01d, 0xc0ff, 0xc01d, 0x21, 0 - .dw 0xc140, 0xc01d, 0xc17f, 0xc01d, 0x21, 0 - .dw 0xc1c0, 0xc01d, 0xc1ff, 0xc01d, 0x21, 0 - .dw 0xc240, 0xc01d, 0xc27f, 0xc01d, 0x21, 0 - .dw 0xc2c0, 0xc01d, 0xc2ff, 0xc01d, 0x21, 0 - .dw 0xc340, 0xc01d, 0xc37f, 0xc01d, 0x21, 0 - .dw 0xc3c0, 0xc01d, 0xc3ff, 0xc01d, 0x21, 0 - .dw 0xc440, 0xc01d, 0xc47f, 0xc01d, 0x21, 0 - .dw 0xc4c0, 0xc01d, 0xc4ff, 0xc01d, 0x21, 0 - .dw 0xc540, 0xc01d, 0xc57f, 0xc01d, 0x21, 0 - .dw 0xc5c0, 0xc01d, 0xc5ff, 0xc01d, 0x21, 0 - .dw 0xc640, 0xc01d, 0xc67f, 0xc01d, 0x21, 0 - .dw 0xc6c0, 0xc01d, 0xc6ff, 0xc01d, 0x21, 0 - .dw 0xc740, 0xc01d, 0xc77f, 0xc01d, 0x21, 0 - .dw 0xc7c0, 0xc01d, 0xc7ff, 0xc01d, 0x21, 0 - .dw 0xc840, 0xc01d, 0xc87f, 0xc01d, 0x21, 0 - .dw 0xc8c0, 0xc01d, 0xc8ff, 0xc01d, 0x21, 0 - .dw 0xc940, 0xc01d, 0xc97f, 0xc01d, 0x21, 0 - .dw 0xc9c0, 0xc01d, 0xc9ff, 0xc01d, 0x21, 0 - .dw 0xca40, 0xc01d, 0xca7f, 0xc01d, 0x21, 0 - .dw 0xcac0, 0xc01d, 0xcaff, 0xc01d, 0x21, 0 - .dw 0xcb40, 0xc01d, 0xcb7f, 0xc01d, 0x21, 0 - .dw 0xcbc0, 0xc01d, 0xcbff, 0xc01d, 0x21, 0 - .dw 0xcc40, 0xc01d, 0xcc7f, 0xc01d, 0x21, 0 - .dw 0xccc0, 0xc01d, 0xccff, 0xc01d, 0x21, 0 - .dw 0xcd40, 0xc01d, 0xcd7f, 0xc01d, 0x21, 0 - .dw 0xcdc0, 0xc01d, 0xcdff, 0xc01d, 0x21, 0 - .dw 0xce40, 0xc01d, 0xce7f, 0xc01d, 0x21, 0 - .dw 0xcec0, 0xc01d, 0xceff, 0xc01d, 0x21, 0 - .dw 0xcf40, 0xc01d, 0xcf7f, 0xc01d, 0x21, 0 - .dw 0xcfc0, 0xc01d, 0xcfff, 0xc01d, 0x21, 0 - .dw 0xd040, 0xc01d, 0xd07f, 0xc01d, 0x21, 0 - .dw 0xd0c0, 0xc01d, 0xd0ff, 0xc01d, 0x21, 0 - .dw 0xd140, 0xc01d, 0xd17f, 0xc01d, 0x21, 0 - .dw 0xd1c0, 0xc01d, 0xd1ff, 0xc01d, 0x21, 0 - .dw 0xd240, 0xc01d, 0xd27f, 0xc01d, 0x21, 0 - .dw 0xd2c0, 0xc01d, 0xd2ff, 0xc01d, 0x21, 0 - .dw 0xd340, 0xc01d, 0xd37f, 0xc01d, 0x21, 0 - .dw 0xd3c0, 0xc01d, 0xd3ff, 0xc01d, 0x21, 0 - .dw 0xd440, 0xc01d, 0xd47f, 0xc01d, 0x21, 0 - .dw 0xd4c0, 0xc01d, 0xd4ff, 0xc01d, 0x21, 0 - .dw 0xd540, 0xc01d, 0xd57f, 0xc01d, 0x21, 0 - .dw 0xd5c0, 0xc01d, 0xd5ff, 0xc01d, 0x21, 0 - .dw 0xd640, 0xc01d, 0xd67f, 0xc01d, 0x21, 0 - .dw 0xd6c0, 0xc01d, 0xd6ff, 0xc01d, 0x21, 0 - .dw 0xd740, 0xc01d, 0xd77f, 0xc01d, 0x21, 0 - .dw 0xd7c0, 0xc01d, 0xd7ff, 0xc01d, 0x21, 0 - .dw 0xd840, 0xc01d, 0xd87f, 0xc01d, 0x21, 0 - .dw 0xd8c0, 0xc01d, 0xd8ff, 0xc01d, 0x21, 0 - .dw 0xd940, 0xc01d, 0xd97f, 0xc01d, 0x21, 0 - .dw 0xd9c0, 0xc01d, 0xdfff, 0xc01d, 0x21, 0 - .dw 0xe040, 0xc01d, 0xe07f, 0xc01d, 0x21, 0 - .dw 0xe0c0, 0xc01d, 0xe0ff, 0xc01d, 0x21, 0 - .dw 0xe140, 0xc01d, 0xe17f, 0xc01d, 0x21, 0 - .dw 0xe1c0, 0xc01d, 0xe1ff, 0xc01d, 0x21, 0 - .dw 0xe240, 0xc01d, 0xe27f, 0xc01d, 0x21, 0 - .dw 0xe2c0, 0xc01d, 0xe2ff, 0xc01d, 0x21, 0 - .dw 0xe340, 0xc01d, 0xe37f, 0xc01d, 0x21, 0 - .dw 0xe3c0, 0xc01d, 0xe3ff, 0xc01d, 0x21, 0 - .dw 0xe440, 0xc01d, 0xe47f, 0xc01d, 0x21, 0 - .dw 0xe4c0, 0xc01d, 0xe4ff, 0xc01d, 0x21, 0 - .dw 0xe540, 0xc01d, 0xe57f, 0xc01d, 0x21, 0 - .dw 0xe5c0, 0xc01d, 0xe5ff, 0xc01d, 0x21, 0 - .dw 0xe640, 0xc01d, 0xe67f, 0xc01d, 0x21, 0 - .dw 0xe6c0, 0xc01d, 0xe6ff, 0xc01d, 0x21, 0 - .dw 0xe740, 0xc01d, 0xe77f, 0xc01d, 0x21, 0 - .dw 0xe7c0, 0xc01d, 0xe7ff, 0xc01d, 0x21, 0 - .dw 0xe840, 0xc01d, 0xe87f, 0xc01d, 0x21, 0 - .dw 0xe8c0, 0xc01d, 0xe8ff, 0xc01d, 0x21, 0 - .dw 0xe940, 0xc01d, 0xe97f, 0xc01d, 0x21, 0 - .dw 0xe9c0, 0xc01d, 0xe9ff, 0xc01d, 0x21, 0 - .dw 0xea40, 0xc01d, 0xea7f, 0xc01d, 0x21, 0 - .dw 0xeac0, 0xc01d, 0xeaff, 0xc01d, 0x21, 0 - .dw 0xeb40, 0xc01d, 0xeb7f, 0xc01d, 0x21, 0 - .dw 0xebc0, 0xc01d, 0xebff, 0xc01d, 0x21, 0 - .dw 0xec40, 0xc01d, 0xec7f, 0xc01d, 0x21, 0 - .dw 0xecc0, 0xc01d, 0xecff, 0xc01d, 0x21, 0 - .dw 0xed40, 0xc01d, 0xed7f, 0xc01d, 0x21, 0 - .dw 0xedc0, 0xc01d, 0xedff, 0xc01d, 0x21, 0 - .dw 0xee40, 0xc01d, 0xee7f, 0xc01d, 0x21, 0 - .dw 0xeec0, 0xc01d, 0xeeff, 0xc01d, 0x21, 0 - .dw 0xef40, 0xc01d, 0xef7f, 0xc01d, 0x21, 0 - .dw 0xefc0, 0xc01d, 0xefff, 0xc01d, 0x21, 0 - .dw 0xf040, 0xc01d, 0xf07f, 0xc01d, 0x21, 0 - .dw 0xf0c0, 0xc01d, 0xf0ff, 0xc01d, 0x21, 0 - .dw 0xf140, 0xc01d, 0xf17f, 0xc01d, 0x21, 0 - .dw 0xf1c0, 0xc01d, 0xf1ff, 0xc01d, 0x21, 0 - .dw 0xf240, 0xc01d, 0xf27f, 0xc01d, 0x21, 0 - .dw 0xf2c0, 0xc01d, 0xf2ff, 0xc01d, 0x21, 0 - .dw 0xf340, 0xc01d, 0xf37f, 0xc01d, 0x21, 0 - .dw 0xf3c0, 0xc01d, 0xf3ff, 0xc01d, 0x21, 0 - .dw 0xf440, 0xc01d, 0xf47f, 0xc01d, 0x21, 0 - .dw 0xf4c0, 0xc01d, 0xf4ff, 0xc01d, 0x21, 0 - .dw 0xf540, 0xc01d, 0xf57f, 0xc01d, 0x21, 0 - .dw 0xf5c0, 0xc01d, 0xf5ff, 0xc01d, 0x21, 0 - .dw 0xf640, 0xc01d, 0xf67f, 0xc01d, 0x21, 0 - .dw 0xf6c0, 0xc01d, 0xf6ff, 0xc01d, 0x21, 0 - .dw 0xf740, 0xc01d, 0xf77f, 0xc01d, 0x21, 0 - .dw 0xf7c0, 0xc01d, 0xf7ff, 0xc01d, 0x21, 0 - .dw 0xf840, 0xc01d, 0xf87f, 0xc01d, 0x21, 0 - .dw 0xf8c0, 0xc01d, 0xf8ff, 0xc01d, 0x21, 0 - .dw 0xf940, 0xc01d, 0xf97f, 0xc01d, 0x21, 0 - .dw 0xf9c0, 0xc01d, 0xffff, 0xc01d, 0x21, 0 - .dw 0x0040, 0xc01e, 0x007f, 0xc01e, 0x21, 0 - .dw 0x00c0, 0xc01e, 0x00ff, 0xc01e, 0x21, 0 - .dw 0x0140, 0xc01e, 0x017f, 0xc01e, 0x21, 0 - .dw 0x01c0, 0xc01e, 0x01ff, 0xc01e, 0x21, 0 - .dw 0x0240, 0xc01e, 0x027f, 0xc01e, 0x21, 0 - .dw 0x02c0, 0xc01e, 0x02ff, 0xc01e, 0x21, 0 - .dw 0x0340, 0xc01e, 0x037f, 0xc01e, 0x21, 0 - .dw 0x03c0, 0xc01e, 0x03ff, 0xc01e, 0x21, 0 - .dw 0x0440, 0xc01e, 0x047f, 0xc01e, 0x21, 0 - .dw 0x04c0, 0xc01e, 0x04ff, 0xc01e, 0x21, 0 - .dw 0x0540, 0xc01e, 0x057f, 0xc01e, 0x21, 0 - .dw 0x05c0, 0xc01e, 0x05ff, 0xc01e, 0x21, 0 - .dw 0x0640, 0xc01e, 0x067f, 0xc01e, 0x21, 0 - .dw 0x06c0, 0xc01e, 0x06ff, 0xc01e, 0x21, 0 - .dw 0x0740, 0xc01e, 0x077f, 0xc01e, 0x21, 0 - .dw 0x07c0, 0xc01e, 0x07ff, 0xc01e, 0x21, 0 - .dw 0x0840, 0xc01e, 0x087f, 0xc01e, 0x21, 0 - .dw 0x08c0, 0xc01e, 0x08ff, 0xc01e, 0x21, 0 - .dw 0x0940, 0xc01e, 0x097f, 0xc01e, 0x21, 0 - .dw 0x09c0, 0xc01e, 0x09ff, 0xc01e, 0x21, 0 - .dw 0x0a40, 0xc01e, 0x0a7f, 0xc01e, 0x21, 0 - .dw 0x0ac0, 0xc01e, 0x0aff, 0xc01e, 0x21, 0 - .dw 0x0b40, 0xc01e, 0x0b7f, 0xc01e, 0x21, 0 - .dw 0x0bc0, 0xc01e, 0x0bff, 0xc01e, 0x21, 0 - .dw 0x0c40, 0xc01e, 0x0c7f, 0xc01e, 0x21, 0 - .dw 0x0cc0, 0xc01e, 0x0cff, 0xc01e, 0x21, 0 - .dw 0x0d40, 0xc01e, 0x0d7f, 0xc01e, 0x21, 0 - .dw 0x0dc0, 0xc01e, 0x0dff, 0xc01e, 0x21, 0 - .dw 0x0e40, 0xc01e, 0x0e7f, 0xc01e, 0x21, 0 - .dw 0x0ec0, 0xc01e, 0x0eff, 0xc01e, 0x21, 0 - .dw 0x0f40, 0xc01e, 0x0f7f, 0xc01e, 0x21, 0 - .dw 0x0fc0, 0xc01e, 0x0fff, 0xc01e, 0x21, 0 - .dw 0x1040, 0xc01e, 0x107f, 0xc01e, 0x21, 0 - .dw 0x10c0, 0xc01e, 0x10ff, 0xc01e, 0x21, 0 - .dw 0x1140, 0xc01e, 0x117f, 0xc01e, 0x21, 0 - .dw 0x11c0, 0xc01e, 0x11ff, 0xc01e, 0x21, 0 - .dw 0x1240, 0xc01e, 0x127f, 0xc01e, 0x21, 0 - .dw 0x12c0, 0xc01e, 0x12ff, 0xc01e, 0x21, 0 - .dw 0x1340, 0xc01e, 0x137f, 0xc01e, 0x21, 0 - .dw 0x13c0, 0xc01e, 0x13ff, 0xc01e, 0x21, 0 - .dw 0x1440, 0xc01e, 0x147f, 0xc01e, 0x21, 0 - .dw 0x14c0, 0xc01e, 0x14ff, 0xc01e, 0x21, 0 - .dw 0x1540, 0xc01e, 0x157f, 0xc01e, 0x21, 0 - .dw 0x15c0, 0xc01e, 0x15ff, 0xc01e, 0x21, 0 - .dw 0x1640, 0xc01e, 0x167f, 0xc01e, 0x21, 0 - .dw 0x16c0, 0xc01e, 0x16ff, 0xc01e, 0x21, 0 - .dw 0x1740, 0xc01e, 0x177f, 0xc01e, 0x21, 0 - .dw 0x17c0, 0xc01e, 0x17ff, 0xc01e, 0x21, 0 - .dw 0x1840, 0xc01e, 0x187f, 0xc01e, 0x21, 0 - .dw 0x18c0, 0xc01e, 0x18ff, 0xc01e, 0x21, 0 - .dw 0x1940, 0xc01e, 0x197f, 0xc01e, 0x21, 0 - .dw 0x19c0, 0xc01e, 0x1fff, 0xc01e, 0x21, 0 - .dw 0x2040, 0xc01e, 0x207f, 0xc01e, 0x21, 0 - .dw 0x20c0, 0xc01e, 0x20ff, 0xc01e, 0x21, 0 - .dw 0x2140, 0xc01e, 0x217f, 0xc01e, 0x21, 0 - .dw 0x21c0, 0xc01e, 0x21ff, 0xc01e, 0x21, 0 - .dw 0x2240, 0xc01e, 0x227f, 0xc01e, 0x21, 0 - .dw 0x22c0, 0xc01e, 0x22ff, 0xc01e, 0x21, 0 - .dw 0x2340, 0xc01e, 0x237f, 0xc01e, 0x21, 0 - .dw 0x23c0, 0xc01e, 0x23ff, 0xc01e, 0x21, 0 - .dw 0x2440, 0xc01e, 0x247f, 0xc01e, 0x21, 0 - .dw 0x24c0, 0xc01e, 0x24ff, 0xc01e, 0x21, 0 - .dw 0x2540, 0xc01e, 0x257f, 0xc01e, 0x21, 0 - .dw 0x25c0, 0xc01e, 0x25ff, 0xc01e, 0x21, 0 - .dw 0x2640, 0xc01e, 0x267f, 0xc01e, 0x21, 0 - .dw 0x26c0, 0xc01e, 0x26ff, 0xc01e, 0x21, 0 - .dw 0x2740, 0xc01e, 0x277f, 0xc01e, 0x21, 0 - .dw 0x27c0, 0xc01e, 0x27ff, 0xc01e, 0x21, 0 - .dw 0x2840, 0xc01e, 0x287f, 0xc01e, 0x21, 0 - .dw 0x28c0, 0xc01e, 0x28ff, 0xc01e, 0x21, 0 - .dw 0x2940, 0xc01e, 0x297f, 0xc01e, 0x21, 0 - .dw 0x29c0, 0xc01e, 0x29ff, 0xc01e, 0x21, 0 - .dw 0x2a40, 0xc01e, 0x2a7f, 0xc01e, 0x21, 0 - .dw 0x2ac0, 0xc01e, 0x2aff, 0xc01e, 0x21, 0 - .dw 0x2b40, 0xc01e, 0x2b7f, 0xc01e, 0x21, 0 - .dw 0x2bc0, 0xc01e, 0x2bff, 0xc01e, 0x21, 0 - .dw 0x2c40, 0xc01e, 0x2c7f, 0xc01e, 0x21, 0 - .dw 0x2cc0, 0xc01e, 0x2cff, 0xc01e, 0x21, 0 - .dw 0x2d40, 0xc01e, 0x2d7f, 0xc01e, 0x21, 0 - .dw 0x2dc0, 0xc01e, 0x2dff, 0xc01e, 0x21, 0 - .dw 0x2e40, 0xc01e, 0x2e7f, 0xc01e, 0x21, 0 - .dw 0x2ec0, 0xc01e, 0x2eff, 0xc01e, 0x21, 0 - .dw 0x2f40, 0xc01e, 0x2f7f, 0xc01e, 0x21, 0 - .dw 0x2fc0, 0xc01e, 0x2fff, 0xc01e, 0x21, 0 - .dw 0x3040, 0xc01e, 0x307f, 0xc01e, 0x21, 0 - .dw 0x30c0, 0xc01e, 0x30ff, 0xc01e, 0x21, 0 - .dw 0x3140, 0xc01e, 0x317f, 0xc01e, 0x21, 0 - .dw 0x31c0, 0xc01e, 0x31ff, 0xc01e, 0x21, 0 - .dw 0x3240, 0xc01e, 0x327f, 0xc01e, 0x21, 0 - .dw 0x32c0, 0xc01e, 0x32ff, 0xc01e, 0x21, 0 - .dw 0x3340, 0xc01e, 0x337f, 0xc01e, 0x21, 0 - .dw 0x33c0, 0xc01e, 0x33ff, 0xc01e, 0x21, 0 - .dw 0x3440, 0xc01e, 0x347f, 0xc01e, 0x21, 0 - .dw 0x34c0, 0xc01e, 0x34ff, 0xc01e, 0x21, 0 - .dw 0x3540, 0xc01e, 0x357f, 0xc01e, 0x21, 0 - .dw 0x35c0, 0xc01e, 0x35ff, 0xc01e, 0x21, 0 - .dw 0x3640, 0xc01e, 0x367f, 0xc01e, 0x21, 0 - .dw 0x36c0, 0xc01e, 0x36ff, 0xc01e, 0x21, 0 - .dw 0x3740, 0xc01e, 0x377f, 0xc01e, 0x21, 0 - .dw 0x37c0, 0xc01e, 0x37ff, 0xc01e, 0x21, 0 - .dw 0x3840, 0xc01e, 0x387f, 0xc01e, 0x21, 0 - .dw 0x38c0, 0xc01e, 0x38ff, 0xc01e, 0x21, 0 - .dw 0x3940, 0xc01e, 0x397f, 0xc01e, 0x21, 0 - .dw 0x39c0, 0xc01e, 0x3fff, 0xc01e, 0x21, 0 - .dw 0x4040, 0xc01e, 0x407f, 0xc01e, 0x21, 0 - .dw 0x40c0, 0xc01e, 0x40ff, 0xc01e, 0x21, 0 - .dw 0x4140, 0xc01e, 0x417f, 0xc01e, 0x21, 0 - .dw 0x41c0, 0xc01e, 0x41ff, 0xc01e, 0x21, 0 - .dw 0x4240, 0xc01e, 0x427f, 0xc01e, 0x21, 0 - .dw 0x42c0, 0xc01e, 0x42ff, 0xc01e, 0x21, 0 - .dw 0x4340, 0xc01e, 0x437f, 0xc01e, 0x21, 0 - .dw 0x43c0, 0xc01e, 0x43ff, 0xc01e, 0x21, 0 - .dw 0x4440, 0xc01e, 0x447f, 0xc01e, 0x21, 0 - .dw 0x44c0, 0xc01e, 0x44ff, 0xc01e, 0x21, 0 - .dw 0x4540, 0xc01e, 0x457f, 0xc01e, 0x21, 0 - .dw 0x45c0, 0xc01e, 0x45ff, 0xc01e, 0x21, 0 - .dw 0x4640, 0xc01e, 0x467f, 0xc01e, 0x21, 0 - .dw 0x46c0, 0xc01e, 0x46ff, 0xc01e, 0x21, 0 - .dw 0x4740, 0xc01e, 0x477f, 0xc01e, 0x21, 0 - .dw 0x47c0, 0xc01e, 0x47ff, 0xc01e, 0x21, 0 - .dw 0x4840, 0xc01e, 0x487f, 0xc01e, 0x21, 0 - .dw 0x48c0, 0xc01e, 0x48ff, 0xc01e, 0x21, 0 - .dw 0x4940, 0xc01e, 0x497f, 0xc01e, 0x21, 0 - .dw 0x49c0, 0xc01e, 0x49ff, 0xc01e, 0x21, 0 - .dw 0x4a40, 0xc01e, 0x4a7f, 0xc01e, 0x21, 0 - .dw 0x4ac0, 0xc01e, 0x4aff, 0xc01e, 0x21, 0 - .dw 0x4b40, 0xc01e, 0x4b7f, 0xc01e, 0x21, 0 - .dw 0x4bc0, 0xc01e, 0x4bff, 0xc01e, 0x21, 0 - .dw 0x4c40, 0xc01e, 0x4c7f, 0xc01e, 0x21, 0 - .dw 0x4cc0, 0xc01e, 0x4cff, 0xc01e, 0x21, 0 - .dw 0x4d40, 0xc01e, 0x4d7f, 0xc01e, 0x21, 0 - .dw 0x4dc0, 0xc01e, 0x4dff, 0xc01e, 0x21, 0 - .dw 0x4e40, 0xc01e, 0x4e7f, 0xc01e, 0x21, 0 - .dw 0x4ec0, 0xc01e, 0x4eff, 0xc01e, 0x21, 0 - .dw 0x4f40, 0xc01e, 0x4f7f, 0xc01e, 0x21, 0 - .dw 0x4fc0, 0xc01e, 0x4fff, 0xc01e, 0x21, 0 - .dw 0x5040, 0xc01e, 0x507f, 0xc01e, 0x21, 0 - .dw 0x50c0, 0xc01e, 0x50ff, 0xc01e, 0x21, 0 - .dw 0x5140, 0xc01e, 0x517f, 0xc01e, 0x21, 0 - .dw 0x51c0, 0xc01e, 0x51ff, 0xc01e, 0x21, 0 - .dw 0x5240, 0xc01e, 0x527f, 0xc01e, 0x21, 0 - .dw 0x52c0, 0xc01e, 0x52ff, 0xc01e, 0x21, 0 - .dw 0x5340, 0xc01e, 0x537f, 0xc01e, 0x21, 0 - .dw 0x53c0, 0xc01e, 0x53ff, 0xc01e, 0x21, 0 - .dw 0x5440, 0xc01e, 0x547f, 0xc01e, 0x21, 0 - .dw 0x54c0, 0xc01e, 0x54ff, 0xc01e, 0x21, 0 - .dw 0x5540, 0xc01e, 0x557f, 0xc01e, 0x21, 0 - .dw 0x55c0, 0xc01e, 0x55ff, 0xc01e, 0x21, 0 - .dw 0x5640, 0xc01e, 0x567f, 0xc01e, 0x21, 0 - .dw 0x56c0, 0xc01e, 0x56ff, 0xc01e, 0x21, 0 - .dw 0x5740, 0xc01e, 0x577f, 0xc01e, 0x21, 0 - .dw 0x57c0, 0xc01e, 0x57ff, 0xc01e, 0x21, 0 - .dw 0x5840, 0xc01e, 0x587f, 0xc01e, 0x21, 0 - .dw 0x58c0, 0xc01e, 0x58ff, 0xc01e, 0x21, 0 - .dw 0x5940, 0xc01e, 0x597f, 0xc01e, 0x21, 0 - .dw 0x59c0, 0xc01e, 0x5fff, 0xc01e, 0x21, 0 - .dw 0x6040, 0xc01e, 0x607f, 0xc01e, 0x21, 0 - .dw 0x60c0, 0xc01e, 0x60ff, 0xc01e, 0x21, 0 - .dw 0x6140, 0xc01e, 0x617f, 0xc01e, 0x21, 0 - .dw 0x61c0, 0xc01e, 0x61ff, 0xc01e, 0x21, 0 - .dw 0x6240, 0xc01e, 0x627f, 0xc01e, 0x21, 0 - .dw 0x62c0, 0xc01e, 0x62ff, 0xc01e, 0x21, 0 - .dw 0x6340, 0xc01e, 0x637f, 0xc01e, 0x21, 0 - .dw 0x63c0, 0xc01e, 0x63ff, 0xc01e, 0x21, 0 - .dw 0x6440, 0xc01e, 0x647f, 0xc01e, 0x21, 0 - .dw 0x64c0, 0xc01e, 0x64ff, 0xc01e, 0x21, 0 - .dw 0x6540, 0xc01e, 0x657f, 0xc01e, 0x21, 0 - .dw 0x65c0, 0xc01e, 0x65ff, 0xc01e, 0x21, 0 - .dw 0x6640, 0xc01e, 0x667f, 0xc01e, 0x21, 0 - .dw 0x66c0, 0xc01e, 0x66ff, 0xc01e, 0x21, 0 - .dw 0x6740, 0xc01e, 0x677f, 0xc01e, 0x21, 0 - .dw 0x67c0, 0xc01e, 0x67ff, 0xc01e, 0x21, 0 - .dw 0x6840, 0xc01e, 0x687f, 0xc01e, 0x21, 0 - .dw 0x68c0, 0xc01e, 0x68ff, 0xc01e, 0x21, 0 - .dw 0x6940, 0xc01e, 0x697f, 0xc01e, 0x21, 0 - .dw 0x69c0, 0xc01e, 0x69ff, 0xc01e, 0x21, 0 - .dw 0x6a40, 0xc01e, 0x6a7f, 0xc01e, 0x21, 0 - .dw 0x6ac0, 0xc01e, 0x6aff, 0xc01e, 0x21, 0 - .dw 0x6b40, 0xc01e, 0x6b7f, 0xc01e, 0x21, 0 - .dw 0x6bc0, 0xc01e, 0x6bff, 0xc01e, 0x21, 0 - .dw 0x6c40, 0xc01e, 0x6c7f, 0xc01e, 0x21, 0 - .dw 0x6cc0, 0xc01e, 0x6cff, 0xc01e, 0x21, 0 - .dw 0x6d40, 0xc01e, 0x6d7f, 0xc01e, 0x21, 0 - .dw 0x6dc0, 0xc01e, 0x6dff, 0xc01e, 0x21, 0 - .dw 0x6e40, 0xc01e, 0x6e7f, 0xc01e, 0x21, 0 - .dw 0x6ec0, 0xc01e, 0x6eff, 0xc01e, 0x21, 0 - .dw 0x6f40, 0xc01e, 0x6f7f, 0xc01e, 0x21, 0 - .dw 0x6fc0, 0xc01e, 0x6fff, 0xc01e, 0x21, 0 - .dw 0x7040, 0xc01e, 0x707f, 0xc01e, 0x21, 0 - .dw 0x70c0, 0xc01e, 0x70ff, 0xc01e, 0x21, 0 - .dw 0x7140, 0xc01e, 0x717f, 0xc01e, 0x21, 0 - .dw 0x71c0, 0xc01e, 0x71ff, 0xc01e, 0x21, 0 - .dw 0x7240, 0xc01e, 0x727f, 0xc01e, 0x21, 0 - .dw 0x72c0, 0xc01e, 0x72ff, 0xc01e, 0x21, 0 - .dw 0x7340, 0xc01e, 0x737f, 0xc01e, 0x21, 0 - .dw 0x73c0, 0xc01e, 0x73ff, 0xc01e, 0x21, 0 - .dw 0x7440, 0xc01e, 0x747f, 0xc01e, 0x21, 0 - .dw 0x74c0, 0xc01e, 0x74ff, 0xc01e, 0x21, 0 - .dw 0x7540, 0xc01e, 0x757f, 0xc01e, 0x21, 0 - .dw 0x75c0, 0xc01e, 0x75ff, 0xc01e, 0x21, 0 - .dw 0x7640, 0xc01e, 0x767f, 0xc01e, 0x21, 0 - .dw 0x76c0, 0xc01e, 0x76ff, 0xc01e, 0x21, 0 - .dw 0x7740, 0xc01e, 0x777f, 0xc01e, 0x21, 0 - .dw 0x77c0, 0xc01e, 0x77ff, 0xc01e, 0x21, 0 - .dw 0x7840, 0xc01e, 0x787f, 0xc01e, 0x21, 0 - .dw 0x78c0, 0xc01e, 0x78ff, 0xc01e, 0x21, 0 - .dw 0x7940, 0xc01e, 0x797f, 0xc01e, 0x21, 0 - .dw 0x79c0, 0xc01e, 0x7fff, 0xc01e, 0x21, 0 - .dw 0x8040, 0xc01e, 0x807f, 0xc01e, 0x21, 0 - .dw 0x80c0, 0xc01e, 0x80ff, 0xc01e, 0x21, 0 - .dw 0x8140, 0xc01e, 0x817f, 0xc01e, 0x21, 0 - .dw 0x81c0, 0xc01e, 0x81ff, 0xc01e, 0x21, 0 - .dw 0x8240, 0xc01e, 0x827f, 0xc01e, 0x21, 0 - .dw 0x82c0, 0xc01e, 0x82ff, 0xc01e, 0x21, 0 - .dw 0x8340, 0xc01e, 0x837f, 0xc01e, 0x21, 0 - .dw 0x83c0, 0xc01e, 0x83ff, 0xc01e, 0x21, 0 - .dw 0x8440, 0xc01e, 0x847f, 0xc01e, 0x21, 0 - .dw 0x84c0, 0xc01e, 0x84ff, 0xc01e, 0x21, 0 - .dw 0x8540, 0xc01e, 0x857f, 0xc01e, 0x21, 0 - .dw 0x85c0, 0xc01e, 0x85ff, 0xc01e, 0x21, 0 - .dw 0x8640, 0xc01e, 0x867f, 0xc01e, 0x21, 0 - .dw 0x86c0, 0xc01e, 0x86ff, 0xc01e, 0x21, 0 - .dw 0x8740, 0xc01e, 0x877f, 0xc01e, 0x21, 0 - .dw 0x87c0, 0xc01e, 0x87ff, 0xc01e, 0x21, 0 - .dw 0x8840, 0xc01e, 0x887f, 0xc01e, 0x21, 0 - .dw 0x88c0, 0xc01e, 0x88ff, 0xc01e, 0x21, 0 - .dw 0x8940, 0xc01e, 0x897f, 0xc01e, 0x21, 0 - .dw 0x89c0, 0xc01e, 0x89ff, 0xc01e, 0x21, 0 - .dw 0x8a40, 0xc01e, 0x8a7f, 0xc01e, 0x21, 0 - .dw 0x8ac0, 0xc01e, 0x8aff, 0xc01e, 0x21, 0 - .dw 0x8b40, 0xc01e, 0x8b7f, 0xc01e, 0x21, 0 - .dw 0x8bc0, 0xc01e, 0x8bff, 0xc01e, 0x21, 0 - .dw 0x8c40, 0xc01e, 0x8c7f, 0xc01e, 0x21, 0 - .dw 0x8cc0, 0xc01e, 0x8cff, 0xc01e, 0x21, 0 - .dw 0x8d40, 0xc01e, 0x8d7f, 0xc01e, 0x21, 0 - .dw 0x8dc0, 0xc01e, 0x8dff, 0xc01e, 0x21, 0 - .dw 0x8e40, 0xc01e, 0x8e7f, 0xc01e, 0x21, 0 - .dw 0x8ec0, 0xc01e, 0x8eff, 0xc01e, 0x21, 0 - .dw 0x8f40, 0xc01e, 0x8f7f, 0xc01e, 0x21, 0 - .dw 0x8fc0, 0xc01e, 0x8fff, 0xc01e, 0x21, 0 - .dw 0x9040, 0xc01e, 0x907f, 0xc01e, 0x21, 0 - .dw 0x90c0, 0xc01e, 0x90ff, 0xc01e, 0x21, 0 - .dw 0x9140, 0xc01e, 0x917f, 0xc01e, 0x21, 0 - .dw 0x91c0, 0xc01e, 0x91ff, 0xc01e, 0x21, 0 - .dw 0x9240, 0xc01e, 0x927f, 0xc01e, 0x21, 0 - .dw 0x92c0, 0xc01e, 0x92ff, 0xc01e, 0x21, 0 - .dw 0x9340, 0xc01e, 0x937f, 0xc01e, 0x21, 0 - .dw 0x93c0, 0xc01e, 0x93ff, 0xc01e, 0x21, 0 - .dw 0x9440, 0xc01e, 0x947f, 0xc01e, 0x21, 0 - .dw 0x94c0, 0xc01e, 0x94ff, 0xc01e, 0x21, 0 - .dw 0x9540, 0xc01e, 0x957f, 0xc01e, 0x21, 0 - .dw 0x95c0, 0xc01e, 0x95ff, 0xc01e, 0x21, 0 - .dw 0x9640, 0xc01e, 0x967f, 0xc01e, 0x21, 0 - .dw 0x96c0, 0xc01e, 0x96ff, 0xc01e, 0x21, 0 - .dw 0x9740, 0xc01e, 0x977f, 0xc01e, 0x21, 0 - .dw 0x97c0, 0xc01e, 0x97ff, 0xc01e, 0x21, 0 - .dw 0x9840, 0xc01e, 0x987f, 0xc01e, 0x21, 0 - .dw 0x98c0, 0xc01e, 0x98ff, 0xc01e, 0x21, 0 - .dw 0x9940, 0xc01e, 0x997f, 0xc01e, 0x21, 0 - .dw 0x99c0, 0xc01e, 0x9fff, 0xc01e, 0x21, 0 - .dw 0xa040, 0xc01e, 0xa07f, 0xc01e, 0x21, 0 - .dw 0xa0c0, 0xc01e, 0xa0ff, 0xc01e, 0x21, 0 - .dw 0xa140, 0xc01e, 0xa17f, 0xc01e, 0x21, 0 - .dw 0xa1c0, 0xc01e, 0xa1ff, 0xc01e, 0x21, 0 - .dw 0xa240, 0xc01e, 0xa27f, 0xc01e, 0x21, 0 - .dw 0xa2c0, 0xc01e, 0xa2ff, 0xc01e, 0x21, 0 - .dw 0xa340, 0xc01e, 0xa37f, 0xc01e, 0x21, 0 - .dw 0xa3c0, 0xc01e, 0xa3ff, 0xc01e, 0x21, 0 - .dw 0xa440, 0xc01e, 0xa47f, 0xc01e, 0x21, 0 - .dw 0xa4c0, 0xc01e, 0xa4ff, 0xc01e, 0x21, 0 - .dw 0xa540, 0xc01e, 0xa57f, 0xc01e, 0x21, 0 - .dw 0xa5c0, 0xc01e, 0xa5ff, 0xc01e, 0x21, 0 - .dw 0xa640, 0xc01e, 0xa67f, 0xc01e, 0x21, 0 - .dw 0xa6c0, 0xc01e, 0xa6ff, 0xc01e, 0x21, 0 - .dw 0xa740, 0xc01e, 0xa77f, 0xc01e, 0x21, 0 - .dw 0xa7c0, 0xc01e, 0xa7ff, 0xc01e, 0x21, 0 - .dw 0xa840, 0xc01e, 0xa87f, 0xc01e, 0x21, 0 - .dw 0xa8c0, 0xc01e, 0xa8ff, 0xc01e, 0x21, 0 - .dw 0xa940, 0xc01e, 0xa97f, 0xc01e, 0x21, 0 - .dw 0xa9c0, 0xc01e, 0xa9ff, 0xc01e, 0x21, 0 - .dw 0xaa40, 0xc01e, 0xaa7f, 0xc01e, 0x21, 0 - .dw 0xaac0, 0xc01e, 0xaaff, 0xc01e, 0x21, 0 - .dw 0xab40, 0xc01e, 0xab7f, 0xc01e, 0x21, 0 - .dw 0xabc0, 0xc01e, 0xabff, 0xc01e, 0x21, 0 - .dw 0xac40, 0xc01e, 0xac7f, 0xc01e, 0x21, 0 - .dw 0xacc0, 0xc01e, 0xacff, 0xc01e, 0x21, 0 - .dw 0xad40, 0xc01e, 0xad7f, 0xc01e, 0x21, 0 - .dw 0xadc0, 0xc01e, 0xadff, 0xc01e, 0x21, 0 - .dw 0xae40, 0xc01e, 0xae7f, 0xc01e, 0x21, 0 - .dw 0xaec0, 0xc01e, 0xaeff, 0xc01e, 0x21, 0 - .dw 0xaf40, 0xc01e, 0xaf7f, 0xc01e, 0x21, 0 - .dw 0xafc0, 0xc01e, 0xafff, 0xc01e, 0x21, 0 - .dw 0xb040, 0xc01e, 0xb07f, 0xc01e, 0x21, 0 - .dw 0xb0c0, 0xc01e, 0xb0ff, 0xc01e, 0x21, 0 - .dw 0xb140, 0xc01e, 0xb17f, 0xc01e, 0x21, 0 - .dw 0xb1c0, 0xc01e, 0xb1ff, 0xc01e, 0x21, 0 - .dw 0xb240, 0xc01e, 0xb27f, 0xc01e, 0x21, 0 - .dw 0xb2c0, 0xc01e, 0xb2ff, 0xc01e, 0x21, 0 - .dw 0xb340, 0xc01e, 0xb37f, 0xc01e, 0x21, 0 - .dw 0xb3c0, 0xc01e, 0xb3ff, 0xc01e, 0x21, 0 - .dw 0xb440, 0xc01e, 0xb47f, 0xc01e, 0x21, 0 - .dw 0xb4c0, 0xc01e, 0xb4ff, 0xc01e, 0x21, 0 - .dw 0xb540, 0xc01e, 0xb57f, 0xc01e, 0x21, 0 - .dw 0xb5c0, 0xc01e, 0xb5ff, 0xc01e, 0x21, 0 - .dw 0xb640, 0xc01e, 0xb67f, 0xc01e, 0x21, 0 - .dw 0xb6c0, 0xc01e, 0xb6ff, 0xc01e, 0x21, 0 - .dw 0xb740, 0xc01e, 0xb77f, 0xc01e, 0x21, 0 - .dw 0xb7c0, 0xc01e, 0xb7ff, 0xc01e, 0x21, 0 - .dw 0xb840, 0xc01e, 0xb87f, 0xc01e, 0x21, 0 - .dw 0xb8c0, 0xc01e, 0xb8ff, 0xc01e, 0x21, 0 - .dw 0xb940, 0xc01e, 0xb97f, 0xc01e, 0x21, 0 - .dw 0xb9c0, 0xc01e, 0xbfff, 0xc01e, 0x21, 0 - .dw 0xc040, 0xc01e, 0xc07f, 0xc01e, 0x21, 0 - .dw 0xc0c0, 0xc01e, 0xc0ff, 0xc01e, 0x21, 0 - .dw 0xc140, 0xc01e, 0xc17f, 0xc01e, 0x21, 0 - .dw 0xc1c0, 0xc01e, 0xc1ff, 0xc01e, 0x21, 0 - .dw 0xc240, 0xc01e, 0xc27f, 0xc01e, 0x21, 0 - .dw 0xc2c0, 0xc01e, 0xc2ff, 0xc01e, 0x21, 0 - .dw 0xc340, 0xc01e, 0xc37f, 0xc01e, 0x21, 0 - .dw 0xc3c0, 0xc01e, 0xc3ff, 0xc01e, 0x21, 0 - .dw 0xc440, 0xc01e, 0xc47f, 0xc01e, 0x21, 0 - .dw 0xc4c0, 0xc01e, 0xc4ff, 0xc01e, 0x21, 0 - .dw 0xc540, 0xc01e, 0xc57f, 0xc01e, 0x21, 0 - .dw 0xc5c0, 0xc01e, 0xc5ff, 0xc01e, 0x21, 0 - .dw 0xc640, 0xc01e, 0xc67f, 0xc01e, 0x21, 0 - .dw 0xc6c0, 0xc01e, 0xc6ff, 0xc01e, 0x21, 0 - .dw 0xc740, 0xc01e, 0xc77f, 0xc01e, 0x21, 0 - .dw 0xc7c0, 0xc01e, 0xc7ff, 0xc01e, 0x21, 0 - .dw 0xc840, 0xc01e, 0xc87f, 0xc01e, 0x21, 0 - .dw 0xc8c0, 0xc01e, 0xc8ff, 0xc01e, 0x21, 0 - .dw 0xc940, 0xc01e, 0xc97f, 0xc01e, 0x21, 0 - .dw 0xc9c0, 0xc01e, 0xc9ff, 0xc01e, 0x21, 0 - .dw 0xca40, 0xc01e, 0xca7f, 0xc01e, 0x21, 0 - .dw 0xcac0, 0xc01e, 0xcaff, 0xc01e, 0x21, 0 - .dw 0xcb40, 0xc01e, 0xcb7f, 0xc01e, 0x21, 0 - .dw 0xcbc0, 0xc01e, 0xcbff, 0xc01e, 0x21, 0 - .dw 0xcc40, 0xc01e, 0xcc7f, 0xc01e, 0x21, 0 - .dw 0xccc0, 0xc01e, 0xccff, 0xc01e, 0x21, 0 - .dw 0xcd40, 0xc01e, 0xcd7f, 0xc01e, 0x21, 0 - .dw 0xcdc0, 0xc01e, 0xcdff, 0xc01e, 0x21, 0 - .dw 0xce40, 0xc01e, 0xce7f, 0xc01e, 0x21, 0 - .dw 0xcec0, 0xc01e, 0xceff, 0xc01e, 0x21, 0 - .dw 0xcf40, 0xc01e, 0xcf7f, 0xc01e, 0x21, 0 - .dw 0xcfc0, 0xc01e, 0xcfff, 0xc01e, 0x21, 0 - .dw 0xd040, 0xc01e, 0xd07f, 0xc01e, 0x21, 0 - .dw 0xd0c0, 0xc01e, 0xd0ff, 0xc01e, 0x21, 0 - .dw 0xd140, 0xc01e, 0xd17f, 0xc01e, 0x21, 0 - .dw 0xd1c0, 0xc01e, 0xd1ff, 0xc01e, 0x21, 0 - .dw 0xd240, 0xc01e, 0xd27f, 0xc01e, 0x21, 0 - .dw 0xd2c0, 0xc01e, 0xd2ff, 0xc01e, 0x21, 0 - .dw 0xd340, 0xc01e, 0xd37f, 0xc01e, 0x21, 0 - .dw 0xd3c0, 0xc01e, 0xd3ff, 0xc01e, 0x21, 0 - .dw 0xd440, 0xc01e, 0xd47f, 0xc01e, 0x21, 0 - .dw 0xd4c0, 0xc01e, 0xd4ff, 0xc01e, 0x21, 0 - .dw 0xd540, 0xc01e, 0xd57f, 0xc01e, 0x21, 0 - .dw 0xd5c0, 0xc01e, 0xd5ff, 0xc01e, 0x21, 0 - .dw 0xd640, 0xc01e, 0xd67f, 0xc01e, 0x21, 0 - .dw 0xd6c0, 0xc01e, 0xd6ff, 0xc01e, 0x21, 0 - .dw 0xd740, 0xc01e, 0xd77f, 0xc01e, 0x21, 0 - .dw 0xd7c0, 0xc01e, 0xd7ff, 0xc01e, 0x21, 0 - .dw 0xd840, 0xc01e, 0xd87f, 0xc01e, 0x21, 0 - .dw 0xd8c0, 0xc01e, 0xd8ff, 0xc01e, 0x21, 0 - .dw 0xd940, 0xc01e, 0xd97f, 0xc01e, 0x21, 0 - .dw 0xd9c0, 0xc01e, 0xdfff, 0xc01e, 0x21, 0 - .dw 0xe040, 0xc01e, 0xe07f, 0xc01e, 0x21, 0 - .dw 0xe0c0, 0xc01e, 0xe0ff, 0xc01e, 0x21, 0 - .dw 0xe140, 0xc01e, 0xe17f, 0xc01e, 0x21, 0 - .dw 0xe1c0, 0xc01e, 0xe1ff, 0xc01e, 0x21, 0 - .dw 0xe240, 0xc01e, 0xe27f, 0xc01e, 0x21, 0 - .dw 0xe2c0, 0xc01e, 0xe2ff, 0xc01e, 0x21, 0 - .dw 0xe340, 0xc01e, 0xe37f, 0xc01e, 0x21, 0 - .dw 0xe3c0, 0xc01e, 0xe3ff, 0xc01e, 0x21, 0 - .dw 0xe440, 0xc01e, 0xe47f, 0xc01e, 0x21, 0 - .dw 0xe4c0, 0xc01e, 0xe4ff, 0xc01e, 0x21, 0 - .dw 0xe540, 0xc01e, 0xe57f, 0xc01e, 0x21, 0 - .dw 0xe5c0, 0xc01e, 0xe5ff, 0xc01e, 0x21, 0 - .dw 0xe640, 0xc01e, 0xe67f, 0xc01e, 0x21, 0 - .dw 0xe6c0, 0xc01e, 0xe6ff, 0xc01e, 0x21, 0 - .dw 0xe740, 0xc01e, 0xe77f, 0xc01e, 0x21, 0 - .dw 0xe7c0, 0xc01e, 0xe7ff, 0xc01e, 0x21, 0 - .dw 0xe840, 0xc01e, 0xe87f, 0xc01e, 0x21, 0 - .dw 0xe8c0, 0xc01e, 0xe8ff, 0xc01e, 0x21, 0 - .dw 0xe940, 0xc01e, 0xe97f, 0xc01e, 0x21, 0 - .dw 0xe9c0, 0xc01e, 0xe9ff, 0xc01e, 0x21, 0 - .dw 0xea40, 0xc01e, 0xea7f, 0xc01e, 0x21, 0 - .dw 0xeac0, 0xc01e, 0xeaff, 0xc01e, 0x21, 0 - .dw 0xeb40, 0xc01e, 0xeb7f, 0xc01e, 0x21, 0 - .dw 0xebc0, 0xc01e, 0xebff, 0xc01e, 0x21, 0 - .dw 0xec40, 0xc01e, 0xec7f, 0xc01e, 0x21, 0 - .dw 0xecc0, 0xc01e, 0xecff, 0xc01e, 0x21, 0 - .dw 0xed40, 0xc01e, 0xed7f, 0xc01e, 0x21, 0 - .dw 0xedc0, 0xc01e, 0xedff, 0xc01e, 0x21, 0 - .dw 0xee40, 0xc01e, 0xee7f, 0xc01e, 0x21, 0 - .dw 0xeec0, 0xc01e, 0xeeff, 0xc01e, 0x21, 0 - .dw 0xef40, 0xc01e, 0xef7f, 0xc01e, 0x21, 0 - .dw 0xefc0, 0xc01e, 0xefff, 0xc01e, 0x21, 0 - .dw 0xf040, 0xc01e, 0xf07f, 0xc01e, 0x21, 0 - .dw 0xf0c0, 0xc01e, 0xf0ff, 0xc01e, 0x21, 0 - .dw 0xf140, 0xc01e, 0xf17f, 0xc01e, 0x21, 0 - .dw 0xf1c0, 0xc01e, 0xf1ff, 0xc01e, 0x21, 0 - .dw 0xf240, 0xc01e, 0xf27f, 0xc01e, 0x21, 0 - .dw 0xf2c0, 0xc01e, 0xf2ff, 0xc01e, 0x21, 0 - .dw 0xf340, 0xc01e, 0xf37f, 0xc01e, 0x21, 0 - .dw 0xf3c0, 0xc01e, 0xf3ff, 0xc01e, 0x21, 0 - .dw 0xf440, 0xc01e, 0xf47f, 0xc01e, 0x21, 0 - .dw 0xf4c0, 0xc01e, 0xf4ff, 0xc01e, 0x21, 0 - .dw 0xf540, 0xc01e, 0xf57f, 0xc01e, 0x21, 0 - .dw 0xf5c0, 0xc01e, 0xf5ff, 0xc01e, 0x21, 0 - .dw 0xf640, 0xc01e, 0xf67f, 0xc01e, 0x21, 0 - .dw 0xf6c0, 0xc01e, 0xf6ff, 0xc01e, 0x21, 0 - .dw 0xf740, 0xc01e, 0xf77f, 0xc01e, 0x21, 0 - .dw 0xf7c0, 0xc01e, 0xf7ff, 0xc01e, 0x21, 0 - .dw 0xf840, 0xc01e, 0xf87f, 0xc01e, 0x21, 0 - .dw 0xf8c0, 0xc01e, 0xf8ff, 0xc01e, 0x21, 0 - .dw 0xf940, 0xc01e, 0xf97f, 0xc01e, 0x21, 0 - .dw 0xf9c0, 0xc01e, 0xffff, 0xc01e, 0x21, 0 - .dw 0x0040, 0xc01f, 0x007f, 0xc01f, 0x21, 0 - .dw 0x00c0, 0xc01f, 0x00ff, 0xc01f, 0x21, 0 - .dw 0x0140, 0xc01f, 0x017f, 0xc01f, 0x21, 0 - .dw 0x01c0, 0xc01f, 0x01ff, 0xc01f, 0x21, 0 - .dw 0x0240, 0xc01f, 0x027f, 0xc01f, 0x21, 0 - .dw 0x02c0, 0xc01f, 0x02ff, 0xc01f, 0x21, 0 - .dw 0x0340, 0xc01f, 0x037f, 0xc01f, 0x21, 0 - .dw 0x03c0, 0xc01f, 0x03ff, 0xc01f, 0x21, 0 - .dw 0x0440, 0xc01f, 0x047f, 0xc01f, 0x21, 0 - .dw 0x04c0, 0xc01f, 0x04ff, 0xc01f, 0x21, 0 - .dw 0x0540, 0xc01f, 0x057f, 0xc01f, 0x21, 0 - .dw 0x05c0, 0xc01f, 0x05ff, 0xc01f, 0x21, 0 - .dw 0x0640, 0xc01f, 0x067f, 0xc01f, 0x21, 0 - .dw 0x06c0, 0xc01f, 0x06ff, 0xc01f, 0x21, 0 - .dw 0x0740, 0xc01f, 0x077f, 0xc01f, 0x21, 0 - .dw 0x07c0, 0xc01f, 0x07ff, 0xc01f, 0x21, 0 - .dw 0x0840, 0xc01f, 0x087f, 0xc01f, 0x21, 0 - .dw 0x08c0, 0xc01f, 0x08ff, 0xc01f, 0x21, 0 - .dw 0x0940, 0xc01f, 0x097f, 0xc01f, 0x21, 0 - .dw 0x09c0, 0xc01f, 0x09ff, 0xc01f, 0x21, 0 - .dw 0x0a40, 0xc01f, 0x0a7f, 0xc01f, 0x21, 0 - .dw 0x0ac0, 0xc01f, 0x0aff, 0xc01f, 0x21, 0 - .dw 0x0b40, 0xc01f, 0x0b7f, 0xc01f, 0x21, 0 - .dw 0x0bc0, 0xc01f, 0x0bff, 0xc01f, 0x21, 0 - .dw 0x0c40, 0xc01f, 0x0c7f, 0xc01f, 0x21, 0 - .dw 0x0cc0, 0xc01f, 0x0cff, 0xc01f, 0x21, 0 - .dw 0x0d40, 0xc01f, 0x0d7f, 0xc01f, 0x21, 0 - .dw 0x0dc0, 0xc01f, 0x0dff, 0xc01f, 0x21, 0 - .dw 0x0e40, 0xc01f, 0x0e7f, 0xc01f, 0x21, 0 - .dw 0x0ec0, 0xc01f, 0x0eff, 0xc01f, 0x21, 0 - .dw 0x0f40, 0xc01f, 0x0f7f, 0xc01f, 0x21, 0 - .dw 0x0fc0, 0xc01f, 0x0fff, 0xc01f, 0x21, 0 - .dw 0x1040, 0xc01f, 0x107f, 0xc01f, 0x21, 0 - .dw 0x10c0, 0xc01f, 0x10ff, 0xc01f, 0x21, 0 - .dw 0x1140, 0xc01f, 0x117f, 0xc01f, 0x21, 0 - .dw 0x11c0, 0xc01f, 0x11ff, 0xc01f, 0x21, 0 - .dw 0x1240, 0xc01f, 0x127f, 0xc01f, 0x21, 0 - .dw 0x12c0, 0xc01f, 0x12ff, 0xc01f, 0x21, 0 - .dw 0x1340, 0xc01f, 0x137f, 0xc01f, 0x21, 0 - .dw 0x13c0, 0xc01f, 0x13ff, 0xc01f, 0x21, 0 - .dw 0x1440, 0xc01f, 0x147f, 0xc01f, 0x21, 0 - .dw 0x14c0, 0xc01f, 0x14ff, 0xc01f, 0x21, 0 - .dw 0x1540, 0xc01f, 0x157f, 0xc01f, 0x21, 0 - .dw 0x15c0, 0xc01f, 0x15ff, 0xc01f, 0x21, 0 - .dw 0x1640, 0xc01f, 0x167f, 0xc01f, 0x21, 0 - .dw 0x16c0, 0xc01f, 0x16ff, 0xc01f, 0x21, 0 - .dw 0x1740, 0xc01f, 0x177f, 0xc01f, 0x21, 0 - .dw 0x17c0, 0xc01f, 0x17ff, 0xc01f, 0x21, 0 - .dw 0x1840, 0xc01f, 0x187f, 0xc01f, 0x21, 0 - .dw 0x18c0, 0xc01f, 0x18ff, 0xc01f, 0x21, 0 - .dw 0x1940, 0xc01f, 0x197f, 0xc01f, 0x21, 0 - .dw 0x19c0, 0xc01f, 0x1fff, 0xc01f, 0x21, 0 - .dw 0x2040, 0xc01f, 0x207f, 0xc01f, 0x21, 0 - .dw 0x20c0, 0xc01f, 0x20ff, 0xc01f, 0x21, 0 - .dw 0x2140, 0xc01f, 0x217f, 0xc01f, 0x21, 0 - .dw 0x21c0, 0xc01f, 0x21ff, 0xc01f, 0x21, 0 - .dw 0x2240, 0xc01f, 0x227f, 0xc01f, 0x21, 0 - .dw 0x22c0, 0xc01f, 0x22ff, 0xc01f, 0x21, 0 - .dw 0x2340, 0xc01f, 0x237f, 0xc01f, 0x21, 0 - .dw 0x23c0, 0xc01f, 0x23ff, 0xc01f, 0x21, 0 - .dw 0x2440, 0xc01f, 0x247f, 0xc01f, 0x21, 0 - .dw 0x24c0, 0xc01f, 0x24ff, 0xc01f, 0x21, 0 - .dw 0x2540, 0xc01f, 0x257f, 0xc01f, 0x21, 0 - .dw 0x25c0, 0xc01f, 0x25ff, 0xc01f, 0x21, 0 - .dw 0x2640, 0xc01f, 0x267f, 0xc01f, 0x21, 0 - .dw 0x26c0, 0xc01f, 0x26ff, 0xc01f, 0x21, 0 - .dw 0x2740, 0xc01f, 0x277f, 0xc01f, 0x21, 0 - .dw 0x27c0, 0xc01f, 0x27ff, 0xc01f, 0x21, 0 - .dw 0x2840, 0xc01f, 0x287f, 0xc01f, 0x21, 0 - .dw 0x28c0, 0xc01f, 0x28ff, 0xc01f, 0x21, 0 - .dw 0x2940, 0xc01f, 0x297f, 0xc01f, 0x21, 0 - .dw 0x29c0, 0xc01f, 0x29ff, 0xc01f, 0x21, 0 - .dw 0x2a40, 0xc01f, 0x2a7f, 0xc01f, 0x21, 0 - .dw 0x2ac0, 0xc01f, 0x2aff, 0xc01f, 0x21, 0 - .dw 0x2b40, 0xc01f, 0x2b7f, 0xc01f, 0x21, 0 - .dw 0x2bc0, 0xc01f, 0x2bff, 0xc01f, 0x21, 0 - .dw 0x2c40, 0xc01f, 0x2c7f, 0xc01f, 0x21, 0 - .dw 0x2cc0, 0xc01f, 0x2cff, 0xc01f, 0x21, 0 - .dw 0x2d40, 0xc01f, 0x2d7f, 0xc01f, 0x21, 0 - .dw 0x2dc0, 0xc01f, 0x2dff, 0xc01f, 0x21, 0 - .dw 0x2e40, 0xc01f, 0x2e7f, 0xc01f, 0x21, 0 - .dw 0x2ec0, 0xc01f, 0x2eff, 0xc01f, 0x21, 0 - .dw 0x2f40, 0xc01f, 0x2f7f, 0xc01f, 0x21, 0 - .dw 0x2fc0, 0xc01f, 0x2fff, 0xc01f, 0x21, 0 - .dw 0x3040, 0xc01f, 0x307f, 0xc01f, 0x21, 0 - .dw 0x30c0, 0xc01f, 0x30ff, 0xc01f, 0x21, 0 - .dw 0x3140, 0xc01f, 0x317f, 0xc01f, 0x21, 0 - .dw 0x31c0, 0xc01f, 0x31ff, 0xc01f, 0x21, 0 - .dw 0x3240, 0xc01f, 0x327f, 0xc01f, 0x21, 0 - .dw 0x32c0, 0xc01f, 0x32ff, 0xc01f, 0x21, 0 - .dw 0x3340, 0xc01f, 0x337f, 0xc01f, 0x21, 0 - .dw 0x33c0, 0xc01f, 0x33ff, 0xc01f, 0x21, 0 - .dw 0x3440, 0xc01f, 0x347f, 0xc01f, 0x21, 0 - .dw 0x34c0, 0xc01f, 0x34ff, 0xc01f, 0x21, 0 - .dw 0x3540, 0xc01f, 0x357f, 0xc01f, 0x21, 0 - .dw 0x35c0, 0xc01f, 0x35ff, 0xc01f, 0x21, 0 - .dw 0x3640, 0xc01f, 0x367f, 0xc01f, 0x21, 0 - .dw 0x36c0, 0xc01f, 0x36ff, 0xc01f, 0x21, 0 - .dw 0x3740, 0xc01f, 0x377f, 0xc01f, 0x21, 0 - .dw 0x37c0, 0xc01f, 0x37ff, 0xc01f, 0x21, 0 - .dw 0x3840, 0xc01f, 0x387f, 0xc01f, 0x21, 0 - .dw 0x38c0, 0xc01f, 0x38ff, 0xc01f, 0x21, 0 - .dw 0x3940, 0xc01f, 0x397f, 0xc01f, 0x21, 0 - .dw 0x39c0, 0xc01f, 0x1fff, 0xc020, 0x21, 0 - .dw 0x3a00, 0xc020, 0x5fff, 0xc020, 0x21, 0 - .dw 0x7a00, 0xc020, 0x9fff, 0xc020, 0x21, 0 - .dw 0xba00, 0xc020, 0xdfff, 0xc020, 0x21, 0 - .dw 0xfa00, 0xc020, 0x1fff, 0xc021, 0x21, 0 - .dw 0x3a00, 0xc021, 0x5fff, 0xc021, 0x21, 0 - .dw 0x7a00, 0xc021, 0x9fff, 0xc021, 0x21, 0 - .dw 0xba00, 0xc021, 0xdfff, 0xc021, 0x21, 0 - .dw 0xfa00, 0xc021, 0x1fff, 0xc022, 0x21, 0 - .dw 0x3a00, 0xc022, 0x5fff, 0xc022, 0x21, 0 - .dw 0x7a00, 0xc022, 0x9fff, 0xc022, 0x21, 0 - .dw 0xba00, 0xc022, 0xdfff, 0xc022, 0x21, 0 - .dw 0xfa00, 0xc022, 0x1fff, 0xc023, 0x21, 0 - .dw 0x3a00, 0xc023, 0xffff, 0xc023, 0x21, 0 - .dw 0x1a00, 0xc024, 0x1fff, 0xc024, 0x21, 0 - .dw 0x3a00, 0xc024, 0x3fff, 0xc024, 0x21, 0 - .dw 0x5a00, 0xc024, 0x5fff, 0xc024, 0x21, 0 - .dw 0x7a00, 0xc024, 0x7fff, 0xc024, 0x21, 0 - .dw 0x9a00, 0xc024, 0x9fff, 0xc024, 0x21, 0 - .dw 0xba00, 0xc024, 0xbfff, 0xc024, 0x21, 0 - .dw 0xda00, 0xc024, 0xdfff, 0xc024, 0x21, 0 - .dw 0xfa00, 0xc024, 0xffff, 0xc024, 0x21, 0 - .dw 0x1a00, 0xc025, 0x1fff, 0xc025, 0x21, 0 - .dw 0x3a00, 0xc025, 0x3fff, 0xc025, 0x21, 0 - .dw 0x5a00, 0xc025, 0x5fff, 0xc025, 0x21, 0 - .dw 0x7a00, 0xc025, 0x7fff, 0xc025, 0x21, 0 - .dw 0x9a00, 0xc025, 0x9fff, 0xc025, 0x21, 0 - .dw 0xba00, 0xc025, 0xbfff, 0xc025, 0x21, 0 - .dw 0xda00, 0xc025, 0xdfff, 0xc025, 0x21, 0 - .dw 0xfa00, 0xc025, 0xffff, 0xc025, 0x21, 0 - .dw 0x1a00, 0xc026, 0x1fff, 0xc026, 0x21, 0 - .dw 0x3a00, 0xc026, 0x3fff, 0xc026, 0x21, 0 - .dw 0x5a00, 0xc026, 0x5fff, 0xc026, 0x21, 0 - .dw 0x7a00, 0xc026, 0x7fff, 0xc026, 0x21, 0 - .dw 0x9a00, 0xc026, 0x9fff, 0xc026, 0x21, 0 - .dw 0xba00, 0xc026, 0xbfff, 0xc026, 0x21, 0 - .dw 0xda00, 0xc026, 0xdfff, 0xc026, 0x21, 0 - .dw 0xfa00, 0xc026, 0xffff, 0xc026, 0x21, 0 - .dw 0x1a00, 0xc027, 0x1fff, 0xc027, 0x21, 0 - .dw 0x3a00, 0xc027, 0x1fff, 0xc028, 0x21, 0 - .dw 0x2040, 0xc028, 0x207f, 0xc028, 0x21, 0 - .dw 0x20c0, 0xc028, 0x20ff, 0xc028, 0x21, 0 - .dw 0x2140, 0xc028, 0x217f, 0xc028, 0x21, 0 - .dw 0x21c0, 0xc028, 0x21ff, 0xc028, 0x21, 0 - .dw 0x2240, 0xc028, 0x227f, 0xc028, 0x21, 0 - .dw 0x22c0, 0xc028, 0x22ff, 0xc028, 0x21, 0 - .dw 0x2340, 0xc028, 0x237f, 0xc028, 0x21, 0 - .dw 0x23c0, 0xc028, 0x23ff, 0xc028, 0x21, 0 - .dw 0x2440, 0xc028, 0x247f, 0xc028, 0x21, 0 - .dw 0x24c0, 0xc028, 0x24ff, 0xc028, 0x21, 0 - .dw 0x2540, 0xc028, 0x257f, 0xc028, 0x21, 0 - .dw 0x25c0, 0xc028, 0x25ff, 0xc028, 0x21, 0 - .dw 0x2640, 0xc028, 0x267f, 0xc028, 0x21, 0 - .dw 0x26c0, 0xc028, 0x26ff, 0xc028, 0x21, 0 - .dw 0x2740, 0xc028, 0x277f, 0xc028, 0x21, 0 - .dw 0x27c0, 0xc028, 0x27ff, 0xc028, 0x21, 0 - .dw 0x2840, 0xc028, 0x287f, 0xc028, 0x21, 0 - .dw 0x28c0, 0xc028, 0x28ff, 0xc028, 0x21, 0 - .dw 0x2940, 0xc028, 0x297f, 0xc028, 0x21, 0 - .dw 0x29c0, 0xc028, 0x29ff, 0xc028, 0x21, 0 - .dw 0x2a40, 0xc028, 0x2a7f, 0xc028, 0x21, 0 - .dw 0x2ac0, 0xc028, 0x2aff, 0xc028, 0x21, 0 - .dw 0x2b40, 0xc028, 0x2b7f, 0xc028, 0x21, 0 - .dw 0x2bc0, 0xc028, 0x2bff, 0xc028, 0x21, 0 - .dw 0x2c40, 0xc028, 0x2c7f, 0xc028, 0x21, 0 - .dw 0x2cc0, 0xc028, 0x2cff, 0xc028, 0x21, 0 - .dw 0x2d40, 0xc028, 0x2d7f, 0xc028, 0x21, 0 - .dw 0x2dc0, 0xc028, 0x2dff, 0xc028, 0x21, 0 - .dw 0x2e40, 0xc028, 0x2e7f, 0xc028, 0x21, 0 - .dw 0x2ec0, 0xc028, 0x2eff, 0xc028, 0x21, 0 - .dw 0x2f40, 0xc028, 0x2f7f, 0xc028, 0x21, 0 - .dw 0x2fc0, 0xc028, 0x2fff, 0xc028, 0x21, 0 - .dw 0x3040, 0xc028, 0x307f, 0xc028, 0x21, 0 - .dw 0x30c0, 0xc028, 0x30ff, 0xc028, 0x21, 0 - .dw 0x3140, 0xc028, 0x317f, 0xc028, 0x21, 0 - .dw 0x31c0, 0xc028, 0x31ff, 0xc028, 0x21, 0 - .dw 0x3240, 0xc028, 0x327f, 0xc028, 0x21, 0 - .dw 0x32c0, 0xc028, 0x32ff, 0xc028, 0x21, 0 - .dw 0x3340, 0xc028, 0x337f, 0xc028, 0x21, 0 - .dw 0x33c0, 0xc028, 0x33ff, 0xc028, 0x21, 0 - .dw 0x3440, 0xc028, 0x347f, 0xc028, 0x21, 0 - .dw 0x34c0, 0xc028, 0x34ff, 0xc028, 0x21, 0 - .dw 0x3540, 0xc028, 0x357f, 0xc028, 0x21, 0 - .dw 0x35c0, 0xc028, 0x35ff, 0xc028, 0x21, 0 - .dw 0x3640, 0xc028, 0x367f, 0xc028, 0x21, 0 - .dw 0x36c0, 0xc028, 0x36ff, 0xc028, 0x21, 0 - .dw 0x3740, 0xc028, 0x377f, 0xc028, 0x21, 0 - .dw 0x37c0, 0xc028, 0x37ff, 0xc028, 0x21, 0 - .dw 0x3840, 0xc028, 0x387f, 0xc028, 0x21, 0 - .dw 0x38c0, 0xc028, 0x38ff, 0xc028, 0x21, 0 - .dw 0x3940, 0xc028, 0x397f, 0xc028, 0x21, 0 - .dw 0x39c0, 0xc028, 0x5fff, 0xc028, 0x21, 0 - .dw 0x6040, 0xc028, 0x607f, 0xc028, 0x21, 0 - .dw 0x60c0, 0xc028, 0x60ff, 0xc028, 0x21, 0 - .dw 0x6140, 0xc028, 0x617f, 0xc028, 0x21, 0 - .dw 0x61c0, 0xc028, 0x61ff, 0xc028, 0x21, 0 - .dw 0x6240, 0xc028, 0x627f, 0xc028, 0x21, 0 - .dw 0x62c0, 0xc028, 0x62ff, 0xc028, 0x21, 0 - .dw 0x6340, 0xc028, 0x637f, 0xc028, 0x21, 0 - .dw 0x63c0, 0xc028, 0x63ff, 0xc028, 0x21, 0 - .dw 0x6440, 0xc028, 0x647f, 0xc028, 0x21, 0 - .dw 0x64c0, 0xc028, 0x64ff, 0xc028, 0x21, 0 - .dw 0x6540, 0xc028, 0x657f, 0xc028, 0x21, 0 - .dw 0x65c0, 0xc028, 0x65ff, 0xc028, 0x21, 0 - .dw 0x6640, 0xc028, 0x667f, 0xc028, 0x21, 0 - .dw 0x66c0, 0xc028, 0x66ff, 0xc028, 0x21, 0 - .dw 0x6740, 0xc028, 0x677f, 0xc028, 0x21, 0 - .dw 0x67c0, 0xc028, 0x67ff, 0xc028, 0x21, 0 - .dw 0x6840, 0xc028, 0x687f, 0xc028, 0x21, 0 - .dw 0x68c0, 0xc028, 0x68ff, 0xc028, 0x21, 0 - .dw 0x6940, 0xc028, 0x697f, 0xc028, 0x21, 0 - .dw 0x69c0, 0xc028, 0x69ff, 0xc028, 0x21, 0 - .dw 0x6a40, 0xc028, 0x6a7f, 0xc028, 0x21, 0 - .dw 0x6ac0, 0xc028, 0x6aff, 0xc028, 0x21, 0 - .dw 0x6b40, 0xc028, 0x6b7f, 0xc028, 0x21, 0 - .dw 0x6bc0, 0xc028, 0x6bff, 0xc028, 0x21, 0 - .dw 0x6c40, 0xc028, 0x6c7f, 0xc028, 0x21, 0 - .dw 0x6cc0, 0xc028, 0x6cff, 0xc028, 0x21, 0 - .dw 0x6d40, 0xc028, 0x6d7f, 0xc028, 0x21, 0 - .dw 0x6dc0, 0xc028, 0x6dff, 0xc028, 0x21, 0 - .dw 0x6e40, 0xc028, 0x6e7f, 0xc028, 0x21, 0 - .dw 0x6ec0, 0xc028, 0x6eff, 0xc028, 0x21, 0 - .dw 0x6f40, 0xc028, 0x6f7f, 0xc028, 0x21, 0 - .dw 0x6fc0, 0xc028, 0x6fff, 0xc028, 0x21, 0 - .dw 0x7040, 0xc028, 0x707f, 0xc028, 0x21, 0 - .dw 0x70c0, 0xc028, 0x70ff, 0xc028, 0x21, 0 - .dw 0x7140, 0xc028, 0x717f, 0xc028, 0x21, 0 - .dw 0x71c0, 0xc028, 0x71ff, 0xc028, 0x21, 0 - .dw 0x7240, 0xc028, 0x727f, 0xc028, 0x21, 0 - .dw 0x72c0, 0xc028, 0x72ff, 0xc028, 0x21, 0 - .dw 0x7340, 0xc028, 0x737f, 0xc028, 0x21, 0 - .dw 0x73c0, 0xc028, 0x73ff, 0xc028, 0x21, 0 - .dw 0x7440, 0xc028, 0x747f, 0xc028, 0x21, 0 - .dw 0x74c0, 0xc028, 0x74ff, 0xc028, 0x21, 0 - .dw 0x7540, 0xc028, 0x757f, 0xc028, 0x21, 0 - .dw 0x75c0, 0xc028, 0x75ff, 0xc028, 0x21, 0 - .dw 0x7640, 0xc028, 0x767f, 0xc028, 0x21, 0 - .dw 0x76c0, 0xc028, 0x76ff, 0xc028, 0x21, 0 - .dw 0x7740, 0xc028, 0x777f, 0xc028, 0x21, 0 - .dw 0x77c0, 0xc028, 0x77ff, 0xc028, 0x21, 0 - .dw 0x7840, 0xc028, 0x787f, 0xc028, 0x21, 0 - .dw 0x78c0, 0xc028, 0x78ff, 0xc028, 0x21, 0 - .dw 0x7940, 0xc028, 0x797f, 0xc028, 0x21, 0 - .dw 0x79c0, 0xc028, 0x9fff, 0xc028, 0x21, 0 - .dw 0xa040, 0xc028, 0xa07f, 0xc028, 0x21, 0 - .dw 0xa0c0, 0xc028, 0xa0ff, 0xc028, 0x21, 0 - .dw 0xa140, 0xc028, 0xa17f, 0xc028, 0x21, 0 - .dw 0xa1c0, 0xc028, 0xa1ff, 0xc028, 0x21, 0 - .dw 0xa240, 0xc028, 0xa27f, 0xc028, 0x21, 0 - .dw 0xa2c0, 0xc028, 0xa2ff, 0xc028, 0x21, 0 - .dw 0xa340, 0xc028, 0xa37f, 0xc028, 0x21, 0 - .dw 0xa3c0, 0xc028, 0xa3ff, 0xc028, 0x21, 0 - .dw 0xa440, 0xc028, 0xa47f, 0xc028, 0x21, 0 - .dw 0xa4c0, 0xc028, 0xa4ff, 0xc028, 0x21, 0 - .dw 0xa540, 0xc028, 0xa57f, 0xc028, 0x21, 0 - .dw 0xa5c0, 0xc028, 0xa5ff, 0xc028, 0x21, 0 - .dw 0xa640, 0xc028, 0xa67f, 0xc028, 0x21, 0 - .dw 0xa6c0, 0xc028, 0xa6ff, 0xc028, 0x21, 0 - .dw 0xa740, 0xc028, 0xa77f, 0xc028, 0x21, 0 - .dw 0xa7c0, 0xc028, 0xa7ff, 0xc028, 0x21, 0 - .dw 0xa840, 0xc028, 0xa87f, 0xc028, 0x21, 0 - .dw 0xa8c0, 0xc028, 0xa8ff, 0xc028, 0x21, 0 - .dw 0xa940, 0xc028, 0xa97f, 0xc028, 0x21, 0 - .dw 0xa9c0, 0xc028, 0xa9ff, 0xc028, 0x21, 0 - .dw 0xaa40, 0xc028, 0xaa7f, 0xc028, 0x21, 0 - .dw 0xaac0, 0xc028, 0xaaff, 0xc028, 0x21, 0 - .dw 0xab40, 0xc028, 0xab7f, 0xc028, 0x21, 0 - .dw 0xabc0, 0xc028, 0xabff, 0xc028, 0x21, 0 - .dw 0xac40, 0xc028, 0xac7f, 0xc028, 0x21, 0 - .dw 0xacc0, 0xc028, 0xacff, 0xc028, 0x21, 0 - .dw 0xad40, 0xc028, 0xad7f, 0xc028, 0x21, 0 - .dw 0xadc0, 0xc028, 0xadff, 0xc028, 0x21, 0 - .dw 0xae40, 0xc028, 0xae7f, 0xc028, 0x21, 0 - .dw 0xaec0, 0xc028, 0xaeff, 0xc028, 0x21, 0 - .dw 0xaf40, 0xc028, 0xaf7f, 0xc028, 0x21, 0 - .dw 0xafc0, 0xc028, 0xafff, 0xc028, 0x21, 0 - .dw 0xb040, 0xc028, 0xb07f, 0xc028, 0x21, 0 - .dw 0xb0c0, 0xc028, 0xb0ff, 0xc028, 0x21, 0 - .dw 0xb140, 0xc028, 0xb17f, 0xc028, 0x21, 0 - .dw 0xb1c0, 0xc028, 0xb1ff, 0xc028, 0x21, 0 - .dw 0xb240, 0xc028, 0xb27f, 0xc028, 0x21, 0 - .dw 0xb2c0, 0xc028, 0xb2ff, 0xc028, 0x21, 0 - .dw 0xb340, 0xc028, 0xb37f, 0xc028, 0x21, 0 - .dw 0xb3c0, 0xc028, 0xb3ff, 0xc028, 0x21, 0 - .dw 0xb440, 0xc028, 0xb47f, 0xc028, 0x21, 0 - .dw 0xb4c0, 0xc028, 0xb4ff, 0xc028, 0x21, 0 - .dw 0xb540, 0xc028, 0xb57f, 0xc028, 0x21, 0 - .dw 0xb5c0, 0xc028, 0xb5ff, 0xc028, 0x21, 0 - .dw 0xb640, 0xc028, 0xb67f, 0xc028, 0x21, 0 - .dw 0xb6c0, 0xc028, 0xb6ff, 0xc028, 0x21, 0 - .dw 0xb740, 0xc028, 0xb77f, 0xc028, 0x21, 0 - .dw 0xb7c0, 0xc028, 0xb7ff, 0xc028, 0x21, 0 - .dw 0xb840, 0xc028, 0xb87f, 0xc028, 0x21, 0 - .dw 0xb8c0, 0xc028, 0xb8ff, 0xc028, 0x21, 0 - .dw 0xb940, 0xc028, 0xb97f, 0xc028, 0x21, 0 - .dw 0xb9c0, 0xc028, 0xdfff, 0xc028, 0x21, 0 - .dw 0xe040, 0xc028, 0xe07f, 0xc028, 0x21, 0 - .dw 0xe0c0, 0xc028, 0xe0ff, 0xc028, 0x21, 0 - .dw 0xe140, 0xc028, 0xe17f, 0xc028, 0x21, 0 - .dw 0xe1c0, 0xc028, 0xe1ff, 0xc028, 0x21, 0 - .dw 0xe240, 0xc028, 0xe27f, 0xc028, 0x21, 0 - .dw 0xe2c0, 0xc028, 0xe2ff, 0xc028, 0x21, 0 - .dw 0xe340, 0xc028, 0xe37f, 0xc028, 0x21, 0 - .dw 0xe3c0, 0xc028, 0xe3ff, 0xc028, 0x21, 0 - .dw 0xe440, 0xc028, 0xe47f, 0xc028, 0x21, 0 - .dw 0xe4c0, 0xc028, 0xe4ff, 0xc028, 0x21, 0 - .dw 0xe540, 0xc028, 0xe57f, 0xc028, 0x21, 0 - .dw 0xe5c0, 0xc028, 0xe5ff, 0xc028, 0x21, 0 - .dw 0xe640, 0xc028, 0xe67f, 0xc028, 0x21, 0 - .dw 0xe6c0, 0xc028, 0xe6ff, 0xc028, 0x21, 0 - .dw 0xe740, 0xc028, 0xe77f, 0xc028, 0x21, 0 - .dw 0xe7c0, 0xc028, 0xe7ff, 0xc028, 0x21, 0 - .dw 0xe840, 0xc028, 0xe87f, 0xc028, 0x21, 0 - .dw 0xe8c0, 0xc028, 0xe8ff, 0xc028, 0x21, 0 - .dw 0xe940, 0xc028, 0xe97f, 0xc028, 0x21, 0 - .dw 0xe9c0, 0xc028, 0xe9ff, 0xc028, 0x21, 0 - .dw 0xea40, 0xc028, 0xea7f, 0xc028, 0x21, 0 - .dw 0xeac0, 0xc028, 0xeaff, 0xc028, 0x21, 0 - .dw 0xeb40, 0xc028, 0xeb7f, 0xc028, 0x21, 0 - .dw 0xebc0, 0xc028, 0xebff, 0xc028, 0x21, 0 - .dw 0xec40, 0xc028, 0xec7f, 0xc028, 0x21, 0 - .dw 0xecc0, 0xc028, 0xecff, 0xc028, 0x21, 0 - .dw 0xed40, 0xc028, 0xed7f, 0xc028, 0x21, 0 - .dw 0xedc0, 0xc028, 0xedff, 0xc028, 0x21, 0 - .dw 0xee40, 0xc028, 0xee7f, 0xc028, 0x21, 0 - .dw 0xeec0, 0xc028, 0xeeff, 0xc028, 0x21, 0 - .dw 0xef40, 0xc028, 0xef7f, 0xc028, 0x21, 0 - .dw 0xefc0, 0xc028, 0xefff, 0xc028, 0x21, 0 - .dw 0xf040, 0xc028, 0xf07f, 0xc028, 0x21, 0 - .dw 0xf0c0, 0xc028, 0xf0ff, 0xc028, 0x21, 0 - .dw 0xf140, 0xc028, 0xf17f, 0xc028, 0x21, 0 - .dw 0xf1c0, 0xc028, 0xf1ff, 0xc028, 0x21, 0 - .dw 0xf240, 0xc028, 0xf27f, 0xc028, 0x21, 0 - .dw 0xf2c0, 0xc028, 0xf2ff, 0xc028, 0x21, 0 - .dw 0xf340, 0xc028, 0xf37f, 0xc028, 0x21, 0 - .dw 0xf3c0, 0xc028, 0xf3ff, 0xc028, 0x21, 0 - .dw 0xf440, 0xc028, 0xf47f, 0xc028, 0x21, 0 - .dw 0xf4c0, 0xc028, 0xf4ff, 0xc028, 0x21, 0 - .dw 0xf540, 0xc028, 0xf57f, 0xc028, 0x21, 0 - .dw 0xf5c0, 0xc028, 0xf5ff, 0xc028, 0x21, 0 - .dw 0xf640, 0xc028, 0xf67f, 0xc028, 0x21, 0 - .dw 0xf6c0, 0xc028, 0xf6ff, 0xc028, 0x21, 0 - .dw 0xf740, 0xc028, 0xf77f, 0xc028, 0x21, 0 - .dw 0xf7c0, 0xc028, 0xf7ff, 0xc028, 0x21, 0 - .dw 0xf840, 0xc028, 0xf87f, 0xc028, 0x21, 0 - .dw 0xf8c0, 0xc028, 0xf8ff, 0xc028, 0x21, 0 - .dw 0xf940, 0xc028, 0xf97f, 0xc028, 0x21, 0 - .dw 0xf9c0, 0xc028, 0x1fff, 0xc029, 0x21, 0 - .dw 0x2040, 0xc029, 0x207f, 0xc029, 0x21, 0 - .dw 0x20c0, 0xc029, 0x20ff, 0xc029, 0x21, 0 - .dw 0x2140, 0xc029, 0x217f, 0xc029, 0x21, 0 - .dw 0x21c0, 0xc029, 0x21ff, 0xc029, 0x21, 0 - .dw 0x2240, 0xc029, 0x227f, 0xc029, 0x21, 0 - .dw 0x22c0, 0xc029, 0x22ff, 0xc029, 0x21, 0 - .dw 0x2340, 0xc029, 0x237f, 0xc029, 0x21, 0 - .dw 0x23c0, 0xc029, 0x23ff, 0xc029, 0x21, 0 - .dw 0x2440, 0xc029, 0x247f, 0xc029, 0x21, 0 - .dw 0x24c0, 0xc029, 0x24ff, 0xc029, 0x21, 0 - .dw 0x2540, 0xc029, 0x257f, 0xc029, 0x21, 0 - .dw 0x25c0, 0xc029, 0x25ff, 0xc029, 0x21, 0 - .dw 0x2640, 0xc029, 0x267f, 0xc029, 0x21, 0 - .dw 0x26c0, 0xc029, 0x26ff, 0xc029, 0x21, 0 - .dw 0x2740, 0xc029, 0x277f, 0xc029, 0x21, 0 - .dw 0x27c0, 0xc029, 0x27ff, 0xc029, 0x21, 0 - .dw 0x2840, 0xc029, 0x287f, 0xc029, 0x21, 0 - .dw 0x28c0, 0xc029, 0x28ff, 0xc029, 0x21, 0 - .dw 0x2940, 0xc029, 0x297f, 0xc029, 0x21, 0 - .dw 0x29c0, 0xc029, 0x29ff, 0xc029, 0x21, 0 - .dw 0x2a40, 0xc029, 0x2a7f, 0xc029, 0x21, 0 - .dw 0x2ac0, 0xc029, 0x2aff, 0xc029, 0x21, 0 - .dw 0x2b40, 0xc029, 0x2b7f, 0xc029, 0x21, 0 - .dw 0x2bc0, 0xc029, 0x2bff, 0xc029, 0x21, 0 - .dw 0x2c40, 0xc029, 0x2c7f, 0xc029, 0x21, 0 - .dw 0x2cc0, 0xc029, 0x2cff, 0xc029, 0x21, 0 - .dw 0x2d40, 0xc029, 0x2d7f, 0xc029, 0x21, 0 - .dw 0x2dc0, 0xc029, 0x2dff, 0xc029, 0x21, 0 - .dw 0x2e40, 0xc029, 0x2e7f, 0xc029, 0x21, 0 - .dw 0x2ec0, 0xc029, 0x2eff, 0xc029, 0x21, 0 - .dw 0x2f40, 0xc029, 0x2f7f, 0xc029, 0x21, 0 - .dw 0x2fc0, 0xc029, 0x2fff, 0xc029, 0x21, 0 - .dw 0x3040, 0xc029, 0x307f, 0xc029, 0x21, 0 - .dw 0x30c0, 0xc029, 0x30ff, 0xc029, 0x21, 0 - .dw 0x3140, 0xc029, 0x317f, 0xc029, 0x21, 0 - .dw 0x31c0, 0xc029, 0x31ff, 0xc029, 0x21, 0 - .dw 0x3240, 0xc029, 0x327f, 0xc029, 0x21, 0 - .dw 0x32c0, 0xc029, 0x32ff, 0xc029, 0x21, 0 - .dw 0x3340, 0xc029, 0x337f, 0xc029, 0x21, 0 - .dw 0x33c0, 0xc029, 0x33ff, 0xc029, 0x21, 0 - .dw 0x3440, 0xc029, 0x347f, 0xc029, 0x21, 0 - .dw 0x34c0, 0xc029, 0x34ff, 0xc029, 0x21, 0 - .dw 0x3540, 0xc029, 0x357f, 0xc029, 0x21, 0 - .dw 0x35c0, 0xc029, 0x35ff, 0xc029, 0x21, 0 - .dw 0x3640, 0xc029, 0x367f, 0xc029, 0x21, 0 - .dw 0x36c0, 0xc029, 0x36ff, 0xc029, 0x21, 0 - .dw 0x3740, 0xc029, 0x377f, 0xc029, 0x21, 0 - .dw 0x37c0, 0xc029, 0x37ff, 0xc029, 0x21, 0 - .dw 0x3840, 0xc029, 0x387f, 0xc029, 0x21, 0 - .dw 0x38c0, 0xc029, 0x38ff, 0xc029, 0x21, 0 - .dw 0x3940, 0xc029, 0x397f, 0xc029, 0x21, 0 - .dw 0x39c0, 0xc029, 0x5fff, 0xc029, 0x21, 0 - .dw 0x6040, 0xc029, 0x607f, 0xc029, 0x21, 0 - .dw 0x60c0, 0xc029, 0x60ff, 0xc029, 0x21, 0 - .dw 0x6140, 0xc029, 0x617f, 0xc029, 0x21, 0 - .dw 0x61c0, 0xc029, 0x61ff, 0xc029, 0x21, 0 - .dw 0x6240, 0xc029, 0x627f, 0xc029, 0x21, 0 - .dw 0x62c0, 0xc029, 0x62ff, 0xc029, 0x21, 0 - .dw 0x6340, 0xc029, 0x637f, 0xc029, 0x21, 0 - .dw 0x63c0, 0xc029, 0x63ff, 0xc029, 0x21, 0 - .dw 0x6440, 0xc029, 0x647f, 0xc029, 0x21, 0 - .dw 0x64c0, 0xc029, 0x64ff, 0xc029, 0x21, 0 - .dw 0x6540, 0xc029, 0x657f, 0xc029, 0x21, 0 - .dw 0x65c0, 0xc029, 0x65ff, 0xc029, 0x21, 0 - .dw 0x6640, 0xc029, 0x667f, 0xc029, 0x21, 0 - .dw 0x66c0, 0xc029, 0x66ff, 0xc029, 0x21, 0 - .dw 0x6740, 0xc029, 0x677f, 0xc029, 0x21, 0 - .dw 0x67c0, 0xc029, 0x67ff, 0xc029, 0x21, 0 - .dw 0x6840, 0xc029, 0x687f, 0xc029, 0x21, 0 - .dw 0x68c0, 0xc029, 0x68ff, 0xc029, 0x21, 0 - .dw 0x6940, 0xc029, 0x697f, 0xc029, 0x21, 0 - .dw 0x69c0, 0xc029, 0x69ff, 0xc029, 0x21, 0 - .dw 0x6a40, 0xc029, 0x6a7f, 0xc029, 0x21, 0 - .dw 0x6ac0, 0xc029, 0x6aff, 0xc029, 0x21, 0 - .dw 0x6b40, 0xc029, 0x6b7f, 0xc029, 0x21, 0 - .dw 0x6bc0, 0xc029, 0x6bff, 0xc029, 0x21, 0 - .dw 0x6c40, 0xc029, 0x6c7f, 0xc029, 0x21, 0 - .dw 0x6cc0, 0xc029, 0x6cff, 0xc029, 0x21, 0 - .dw 0x6d40, 0xc029, 0x6d7f, 0xc029, 0x21, 0 - .dw 0x6dc0, 0xc029, 0x6dff, 0xc029, 0x21, 0 - .dw 0x6e40, 0xc029, 0x6e7f, 0xc029, 0x21, 0 - .dw 0x6ec0, 0xc029, 0x6eff, 0xc029, 0x21, 0 - .dw 0x6f40, 0xc029, 0x6f7f, 0xc029, 0x21, 0 - .dw 0x6fc0, 0xc029, 0x6fff, 0xc029, 0x21, 0 - .dw 0x7040, 0xc029, 0x707f, 0xc029, 0x21, 0 - .dw 0x70c0, 0xc029, 0x70ff, 0xc029, 0x21, 0 - .dw 0x7140, 0xc029, 0x717f, 0xc029, 0x21, 0 - .dw 0x71c0, 0xc029, 0x71ff, 0xc029, 0x21, 0 - .dw 0x7240, 0xc029, 0x727f, 0xc029, 0x21, 0 - .dw 0x72c0, 0xc029, 0x72ff, 0xc029, 0x21, 0 - .dw 0x7340, 0xc029, 0x737f, 0xc029, 0x21, 0 - .dw 0x73c0, 0xc029, 0x73ff, 0xc029, 0x21, 0 - .dw 0x7440, 0xc029, 0x747f, 0xc029, 0x21, 0 - .dw 0x74c0, 0xc029, 0x74ff, 0xc029, 0x21, 0 - .dw 0x7540, 0xc029, 0x757f, 0xc029, 0x21, 0 - .dw 0x75c0, 0xc029, 0x75ff, 0xc029, 0x21, 0 - .dw 0x7640, 0xc029, 0x767f, 0xc029, 0x21, 0 - .dw 0x76c0, 0xc029, 0x76ff, 0xc029, 0x21, 0 - .dw 0x7740, 0xc029, 0x777f, 0xc029, 0x21, 0 - .dw 0x77c0, 0xc029, 0x77ff, 0xc029, 0x21, 0 - .dw 0x7840, 0xc029, 0x787f, 0xc029, 0x21, 0 - .dw 0x78c0, 0xc029, 0x78ff, 0xc029, 0x21, 0 - .dw 0x7940, 0xc029, 0x797f, 0xc029, 0x21, 0 - .dw 0x79c0, 0xc029, 0x9fff, 0xc029, 0x21, 0 - .dw 0xa040, 0xc029, 0xa07f, 0xc029, 0x21, 0 - .dw 0xa0c0, 0xc029, 0xa0ff, 0xc029, 0x21, 0 - .dw 0xa140, 0xc029, 0xa17f, 0xc029, 0x21, 0 - .dw 0xa1c0, 0xc029, 0xa1ff, 0xc029, 0x21, 0 - .dw 0xa240, 0xc029, 0xa27f, 0xc029, 0x21, 0 - .dw 0xa2c0, 0xc029, 0xa2ff, 0xc029, 0x21, 0 - .dw 0xa340, 0xc029, 0xa37f, 0xc029, 0x21, 0 - .dw 0xa3c0, 0xc029, 0xa3ff, 0xc029, 0x21, 0 - .dw 0xa440, 0xc029, 0xa47f, 0xc029, 0x21, 0 - .dw 0xa4c0, 0xc029, 0xa4ff, 0xc029, 0x21, 0 - .dw 0xa540, 0xc029, 0xa57f, 0xc029, 0x21, 0 - .dw 0xa5c0, 0xc029, 0xa5ff, 0xc029, 0x21, 0 - .dw 0xa640, 0xc029, 0xa67f, 0xc029, 0x21, 0 - .dw 0xa6c0, 0xc029, 0xa6ff, 0xc029, 0x21, 0 - .dw 0xa740, 0xc029, 0xa77f, 0xc029, 0x21, 0 - .dw 0xa7c0, 0xc029, 0xa7ff, 0xc029, 0x21, 0 - .dw 0xa840, 0xc029, 0xa87f, 0xc029, 0x21, 0 - .dw 0xa8c0, 0xc029, 0xa8ff, 0xc029, 0x21, 0 - .dw 0xa940, 0xc029, 0xa97f, 0xc029, 0x21, 0 - .dw 0xa9c0, 0xc029, 0xa9ff, 0xc029, 0x21, 0 - .dw 0xaa40, 0xc029, 0xaa7f, 0xc029, 0x21, 0 - .dw 0xaac0, 0xc029, 0xaaff, 0xc029, 0x21, 0 - .dw 0xab40, 0xc029, 0xab7f, 0xc029, 0x21, 0 - .dw 0xabc0, 0xc029, 0xabff, 0xc029, 0x21, 0 - .dw 0xac40, 0xc029, 0xac7f, 0xc029, 0x21, 0 - .dw 0xacc0, 0xc029, 0xacff, 0xc029, 0x21, 0 - .dw 0xad40, 0xc029, 0xad7f, 0xc029, 0x21, 0 - .dw 0xadc0, 0xc029, 0xadff, 0xc029, 0x21, 0 - .dw 0xae40, 0xc029, 0xae7f, 0xc029, 0x21, 0 - .dw 0xaec0, 0xc029, 0xaeff, 0xc029, 0x21, 0 - .dw 0xaf40, 0xc029, 0xaf7f, 0xc029, 0x21, 0 - .dw 0xafc0, 0xc029, 0xafff, 0xc029, 0x21, 0 - .dw 0xb040, 0xc029, 0xb07f, 0xc029, 0x21, 0 - .dw 0xb0c0, 0xc029, 0xb0ff, 0xc029, 0x21, 0 - .dw 0xb140, 0xc029, 0xb17f, 0xc029, 0x21, 0 - .dw 0xb1c0, 0xc029, 0xb1ff, 0xc029, 0x21, 0 - .dw 0xb240, 0xc029, 0xb27f, 0xc029, 0x21, 0 - .dw 0xb2c0, 0xc029, 0xb2ff, 0xc029, 0x21, 0 - .dw 0xb340, 0xc029, 0xb37f, 0xc029, 0x21, 0 - .dw 0xb3c0, 0xc029, 0xb3ff, 0xc029, 0x21, 0 - .dw 0xb440, 0xc029, 0xb47f, 0xc029, 0x21, 0 - .dw 0xb4c0, 0xc029, 0xb4ff, 0xc029, 0x21, 0 - .dw 0xb540, 0xc029, 0xb57f, 0xc029, 0x21, 0 - .dw 0xb5c0, 0xc029, 0xb5ff, 0xc029, 0x21, 0 - .dw 0xb640, 0xc029, 0xb67f, 0xc029, 0x21, 0 - .dw 0xb6c0, 0xc029, 0xb6ff, 0xc029, 0x21, 0 - .dw 0xb740, 0xc029, 0xb77f, 0xc029, 0x21, 0 - .dw 0xb7c0, 0xc029, 0xb7ff, 0xc029, 0x21, 0 - .dw 0xb840, 0xc029, 0xb87f, 0xc029, 0x21, 0 - .dw 0xb8c0, 0xc029, 0xb8ff, 0xc029, 0x21, 0 - .dw 0xb940, 0xc029, 0xb97f, 0xc029, 0x21, 0 - .dw 0xb9c0, 0xc029, 0xdfff, 0xc029, 0x21, 0 - .dw 0xe040, 0xc029, 0xe07f, 0xc029, 0x21, 0 - .dw 0xe0c0, 0xc029, 0xe0ff, 0xc029, 0x21, 0 - .dw 0xe140, 0xc029, 0xe17f, 0xc029, 0x21, 0 - .dw 0xe1c0, 0xc029, 0xe1ff, 0xc029, 0x21, 0 - .dw 0xe240, 0xc029, 0xe27f, 0xc029, 0x21, 0 - .dw 0xe2c0, 0xc029, 0xe2ff, 0xc029, 0x21, 0 - .dw 0xe340, 0xc029, 0xe37f, 0xc029, 0x21, 0 - .dw 0xe3c0, 0xc029, 0xe3ff, 0xc029, 0x21, 0 - .dw 0xe440, 0xc029, 0xe47f, 0xc029, 0x21, 0 - .dw 0xe4c0, 0xc029, 0xe4ff, 0xc029, 0x21, 0 - .dw 0xe540, 0xc029, 0xe57f, 0xc029, 0x21, 0 - .dw 0xe5c0, 0xc029, 0xe5ff, 0xc029, 0x21, 0 - .dw 0xe640, 0xc029, 0xe67f, 0xc029, 0x21, 0 - .dw 0xe6c0, 0xc029, 0xe6ff, 0xc029, 0x21, 0 - .dw 0xe740, 0xc029, 0xe77f, 0xc029, 0x21, 0 - .dw 0xe7c0, 0xc029, 0xe7ff, 0xc029, 0x21, 0 - .dw 0xe840, 0xc029, 0xe87f, 0xc029, 0x21, 0 - .dw 0xe8c0, 0xc029, 0xe8ff, 0xc029, 0x21, 0 - .dw 0xe940, 0xc029, 0xe97f, 0xc029, 0x21, 0 - .dw 0xe9c0, 0xc029, 0xe9ff, 0xc029, 0x21, 0 - .dw 0xea40, 0xc029, 0xea7f, 0xc029, 0x21, 0 - .dw 0xeac0, 0xc029, 0xeaff, 0xc029, 0x21, 0 - .dw 0xeb40, 0xc029, 0xeb7f, 0xc029, 0x21, 0 - .dw 0xebc0, 0xc029, 0xebff, 0xc029, 0x21, 0 - .dw 0xec40, 0xc029, 0xec7f, 0xc029, 0x21, 0 - .dw 0xecc0, 0xc029, 0xecff, 0xc029, 0x21, 0 - .dw 0xed40, 0xc029, 0xed7f, 0xc029, 0x21, 0 - .dw 0xedc0, 0xc029, 0xedff, 0xc029, 0x21, 0 - .dw 0xee40, 0xc029, 0xee7f, 0xc029, 0x21, 0 - .dw 0xeec0, 0xc029, 0xeeff, 0xc029, 0x21, 0 - .dw 0xef40, 0xc029, 0xef7f, 0xc029, 0x21, 0 - .dw 0xefc0, 0xc029, 0xefff, 0xc029, 0x21, 0 - .dw 0xf040, 0xc029, 0xf07f, 0xc029, 0x21, 0 - .dw 0xf0c0, 0xc029, 0xf0ff, 0xc029, 0x21, 0 - .dw 0xf140, 0xc029, 0xf17f, 0xc029, 0x21, 0 - .dw 0xf1c0, 0xc029, 0xf1ff, 0xc029, 0x21, 0 - .dw 0xf240, 0xc029, 0xf27f, 0xc029, 0x21, 0 - .dw 0xf2c0, 0xc029, 0xf2ff, 0xc029, 0x21, 0 - .dw 0xf340, 0xc029, 0xf37f, 0xc029, 0x21, 0 - .dw 0xf3c0, 0xc029, 0xf3ff, 0xc029, 0x21, 0 - .dw 0xf440, 0xc029, 0xf47f, 0xc029, 0x21, 0 - .dw 0xf4c0, 0xc029, 0xf4ff, 0xc029, 0x21, 0 - .dw 0xf540, 0xc029, 0xf57f, 0xc029, 0x21, 0 - .dw 0xf5c0, 0xc029, 0xf5ff, 0xc029, 0x21, 0 - .dw 0xf640, 0xc029, 0xf67f, 0xc029, 0x21, 0 - .dw 0xf6c0, 0xc029, 0xf6ff, 0xc029, 0x21, 0 - .dw 0xf740, 0xc029, 0xf77f, 0xc029, 0x21, 0 - .dw 0xf7c0, 0xc029, 0xf7ff, 0xc029, 0x21, 0 - .dw 0xf840, 0xc029, 0xf87f, 0xc029, 0x21, 0 - .dw 0xf8c0, 0xc029, 0xf8ff, 0xc029, 0x21, 0 - .dw 0xf940, 0xc029, 0xf97f, 0xc029, 0x21, 0 - .dw 0xf9c0, 0xc029, 0x1fff, 0xc02a, 0x21, 0 - .dw 0x2040, 0xc02a, 0x207f, 0xc02a, 0x21, 0 - .dw 0x20c0, 0xc02a, 0x20ff, 0xc02a, 0x21, 0 - .dw 0x2140, 0xc02a, 0x217f, 0xc02a, 0x21, 0 - .dw 0x21c0, 0xc02a, 0x21ff, 0xc02a, 0x21, 0 - .dw 0x2240, 0xc02a, 0x227f, 0xc02a, 0x21, 0 - .dw 0x22c0, 0xc02a, 0x22ff, 0xc02a, 0x21, 0 - .dw 0x2340, 0xc02a, 0x237f, 0xc02a, 0x21, 0 - .dw 0x23c0, 0xc02a, 0x23ff, 0xc02a, 0x21, 0 - .dw 0x2440, 0xc02a, 0x247f, 0xc02a, 0x21, 0 - .dw 0x24c0, 0xc02a, 0x24ff, 0xc02a, 0x21, 0 - .dw 0x2540, 0xc02a, 0x257f, 0xc02a, 0x21, 0 - .dw 0x25c0, 0xc02a, 0x25ff, 0xc02a, 0x21, 0 - .dw 0x2640, 0xc02a, 0x267f, 0xc02a, 0x21, 0 - .dw 0x26c0, 0xc02a, 0x26ff, 0xc02a, 0x21, 0 - .dw 0x2740, 0xc02a, 0x277f, 0xc02a, 0x21, 0 - .dw 0x27c0, 0xc02a, 0x27ff, 0xc02a, 0x21, 0 - .dw 0x2840, 0xc02a, 0x287f, 0xc02a, 0x21, 0 - .dw 0x28c0, 0xc02a, 0x28ff, 0xc02a, 0x21, 0 - .dw 0x2940, 0xc02a, 0x297f, 0xc02a, 0x21, 0 - .dw 0x29c0, 0xc02a, 0x29ff, 0xc02a, 0x21, 0 - .dw 0x2a40, 0xc02a, 0x2a7f, 0xc02a, 0x21, 0 - .dw 0x2ac0, 0xc02a, 0x2aff, 0xc02a, 0x21, 0 - .dw 0x2b40, 0xc02a, 0x2b7f, 0xc02a, 0x21, 0 - .dw 0x2bc0, 0xc02a, 0x2bff, 0xc02a, 0x21, 0 - .dw 0x2c40, 0xc02a, 0x2c7f, 0xc02a, 0x21, 0 - .dw 0x2cc0, 0xc02a, 0x2cff, 0xc02a, 0x21, 0 - .dw 0x2d40, 0xc02a, 0x2d7f, 0xc02a, 0x21, 0 - .dw 0x2dc0, 0xc02a, 0x2dff, 0xc02a, 0x21, 0 - .dw 0x2e40, 0xc02a, 0x2e7f, 0xc02a, 0x21, 0 - .dw 0x2ec0, 0xc02a, 0x2eff, 0xc02a, 0x21, 0 - .dw 0x2f40, 0xc02a, 0x2f7f, 0xc02a, 0x21, 0 - .dw 0x2fc0, 0xc02a, 0x2fff, 0xc02a, 0x21, 0 - .dw 0x3040, 0xc02a, 0x307f, 0xc02a, 0x21, 0 - .dw 0x30c0, 0xc02a, 0x30ff, 0xc02a, 0x21, 0 - .dw 0x3140, 0xc02a, 0x317f, 0xc02a, 0x21, 0 - .dw 0x31c0, 0xc02a, 0x31ff, 0xc02a, 0x21, 0 - .dw 0x3240, 0xc02a, 0x327f, 0xc02a, 0x21, 0 - .dw 0x32c0, 0xc02a, 0x32ff, 0xc02a, 0x21, 0 - .dw 0x3340, 0xc02a, 0x337f, 0xc02a, 0x21, 0 - .dw 0x33c0, 0xc02a, 0x33ff, 0xc02a, 0x21, 0 - .dw 0x3440, 0xc02a, 0x347f, 0xc02a, 0x21, 0 - .dw 0x34c0, 0xc02a, 0x34ff, 0xc02a, 0x21, 0 - .dw 0x3540, 0xc02a, 0x357f, 0xc02a, 0x21, 0 - .dw 0x35c0, 0xc02a, 0x35ff, 0xc02a, 0x21, 0 - .dw 0x3640, 0xc02a, 0x367f, 0xc02a, 0x21, 0 - .dw 0x36c0, 0xc02a, 0x36ff, 0xc02a, 0x21, 0 - .dw 0x3740, 0xc02a, 0x377f, 0xc02a, 0x21, 0 - .dw 0x37c0, 0xc02a, 0x37ff, 0xc02a, 0x21, 0 - .dw 0x3840, 0xc02a, 0x387f, 0xc02a, 0x21, 0 - .dw 0x38c0, 0xc02a, 0x38ff, 0xc02a, 0x21, 0 - .dw 0x3940, 0xc02a, 0x397f, 0xc02a, 0x21, 0 - .dw 0x39c0, 0xc02a, 0x5fff, 0xc02a, 0x21, 0 - .dw 0x6040, 0xc02a, 0x607f, 0xc02a, 0x21, 0 - .dw 0x60c0, 0xc02a, 0x60ff, 0xc02a, 0x21, 0 - .dw 0x6140, 0xc02a, 0x617f, 0xc02a, 0x21, 0 - .dw 0x61c0, 0xc02a, 0x61ff, 0xc02a, 0x21, 0 - .dw 0x6240, 0xc02a, 0x627f, 0xc02a, 0x21, 0 - .dw 0x62c0, 0xc02a, 0x62ff, 0xc02a, 0x21, 0 - .dw 0x6340, 0xc02a, 0x637f, 0xc02a, 0x21, 0 - .dw 0x63c0, 0xc02a, 0x63ff, 0xc02a, 0x21, 0 - .dw 0x6440, 0xc02a, 0x647f, 0xc02a, 0x21, 0 - .dw 0x64c0, 0xc02a, 0x64ff, 0xc02a, 0x21, 0 - .dw 0x6540, 0xc02a, 0x657f, 0xc02a, 0x21, 0 - .dw 0x65c0, 0xc02a, 0x65ff, 0xc02a, 0x21, 0 - .dw 0x6640, 0xc02a, 0x667f, 0xc02a, 0x21, 0 - .dw 0x66c0, 0xc02a, 0x66ff, 0xc02a, 0x21, 0 - .dw 0x6740, 0xc02a, 0x677f, 0xc02a, 0x21, 0 - .dw 0x67c0, 0xc02a, 0x67ff, 0xc02a, 0x21, 0 - .dw 0x6840, 0xc02a, 0x687f, 0xc02a, 0x21, 0 - .dw 0x68c0, 0xc02a, 0x68ff, 0xc02a, 0x21, 0 - .dw 0x6940, 0xc02a, 0x697f, 0xc02a, 0x21, 0 - .dw 0x69c0, 0xc02a, 0x69ff, 0xc02a, 0x21, 0 - .dw 0x6a40, 0xc02a, 0x6a7f, 0xc02a, 0x21, 0 - .dw 0x6ac0, 0xc02a, 0x6aff, 0xc02a, 0x21, 0 - .dw 0x6b40, 0xc02a, 0x6b7f, 0xc02a, 0x21, 0 - .dw 0x6bc0, 0xc02a, 0x6bff, 0xc02a, 0x21, 0 - .dw 0x6c40, 0xc02a, 0x6c7f, 0xc02a, 0x21, 0 - .dw 0x6cc0, 0xc02a, 0x6cff, 0xc02a, 0x21, 0 - .dw 0x6d40, 0xc02a, 0x6d7f, 0xc02a, 0x21, 0 - .dw 0x6dc0, 0xc02a, 0x6dff, 0xc02a, 0x21, 0 - .dw 0x6e40, 0xc02a, 0x6e7f, 0xc02a, 0x21, 0 - .dw 0x6ec0, 0xc02a, 0x6eff, 0xc02a, 0x21, 0 - .dw 0x6f40, 0xc02a, 0x6f7f, 0xc02a, 0x21, 0 - .dw 0x6fc0, 0xc02a, 0x6fff, 0xc02a, 0x21, 0 - .dw 0x7040, 0xc02a, 0x707f, 0xc02a, 0x21, 0 - .dw 0x70c0, 0xc02a, 0x70ff, 0xc02a, 0x21, 0 - .dw 0x7140, 0xc02a, 0x717f, 0xc02a, 0x21, 0 - .dw 0x71c0, 0xc02a, 0x71ff, 0xc02a, 0x21, 0 - .dw 0x7240, 0xc02a, 0x727f, 0xc02a, 0x21, 0 - .dw 0x72c0, 0xc02a, 0x72ff, 0xc02a, 0x21, 0 - .dw 0x7340, 0xc02a, 0x737f, 0xc02a, 0x21, 0 - .dw 0x73c0, 0xc02a, 0x73ff, 0xc02a, 0x21, 0 - .dw 0x7440, 0xc02a, 0x747f, 0xc02a, 0x21, 0 - .dw 0x74c0, 0xc02a, 0x74ff, 0xc02a, 0x21, 0 - .dw 0x7540, 0xc02a, 0x757f, 0xc02a, 0x21, 0 - .dw 0x75c0, 0xc02a, 0x75ff, 0xc02a, 0x21, 0 - .dw 0x7640, 0xc02a, 0x767f, 0xc02a, 0x21, 0 - .dw 0x76c0, 0xc02a, 0x76ff, 0xc02a, 0x21, 0 - .dw 0x7740, 0xc02a, 0x777f, 0xc02a, 0x21, 0 - .dw 0x77c0, 0xc02a, 0x77ff, 0xc02a, 0x21, 0 - .dw 0x7840, 0xc02a, 0x787f, 0xc02a, 0x21, 0 - .dw 0x78c0, 0xc02a, 0x78ff, 0xc02a, 0x21, 0 - .dw 0x7940, 0xc02a, 0x797f, 0xc02a, 0x21, 0 - .dw 0x79c0, 0xc02a, 0x9fff, 0xc02a, 0x21, 0 - .dw 0xa040, 0xc02a, 0xa07f, 0xc02a, 0x21, 0 - .dw 0xa0c0, 0xc02a, 0xa0ff, 0xc02a, 0x21, 0 - .dw 0xa140, 0xc02a, 0xa17f, 0xc02a, 0x21, 0 - .dw 0xa1c0, 0xc02a, 0xa1ff, 0xc02a, 0x21, 0 - .dw 0xa240, 0xc02a, 0xa27f, 0xc02a, 0x21, 0 - .dw 0xa2c0, 0xc02a, 0xa2ff, 0xc02a, 0x21, 0 - .dw 0xa340, 0xc02a, 0xa37f, 0xc02a, 0x21, 0 - .dw 0xa3c0, 0xc02a, 0xa3ff, 0xc02a, 0x21, 0 - .dw 0xa440, 0xc02a, 0xa47f, 0xc02a, 0x21, 0 - .dw 0xa4c0, 0xc02a, 0xa4ff, 0xc02a, 0x21, 0 - .dw 0xa540, 0xc02a, 0xa57f, 0xc02a, 0x21, 0 - .dw 0xa5c0, 0xc02a, 0xa5ff, 0xc02a, 0x21, 0 - .dw 0xa640, 0xc02a, 0xa67f, 0xc02a, 0x21, 0 - .dw 0xa6c0, 0xc02a, 0xa6ff, 0xc02a, 0x21, 0 - .dw 0xa740, 0xc02a, 0xa77f, 0xc02a, 0x21, 0 - .dw 0xa7c0, 0xc02a, 0xa7ff, 0xc02a, 0x21, 0 - .dw 0xa840, 0xc02a, 0xa87f, 0xc02a, 0x21, 0 - .dw 0xa8c0, 0xc02a, 0xa8ff, 0xc02a, 0x21, 0 - .dw 0xa940, 0xc02a, 0xa97f, 0xc02a, 0x21, 0 - .dw 0xa9c0, 0xc02a, 0xa9ff, 0xc02a, 0x21, 0 - .dw 0xaa40, 0xc02a, 0xaa7f, 0xc02a, 0x21, 0 - .dw 0xaac0, 0xc02a, 0xaaff, 0xc02a, 0x21, 0 - .dw 0xab40, 0xc02a, 0xab7f, 0xc02a, 0x21, 0 - .dw 0xabc0, 0xc02a, 0xabff, 0xc02a, 0x21, 0 - .dw 0xac40, 0xc02a, 0xac7f, 0xc02a, 0x21, 0 - .dw 0xacc0, 0xc02a, 0xacff, 0xc02a, 0x21, 0 - .dw 0xad40, 0xc02a, 0xad7f, 0xc02a, 0x21, 0 - .dw 0xadc0, 0xc02a, 0xadff, 0xc02a, 0x21, 0 - .dw 0xae40, 0xc02a, 0xae7f, 0xc02a, 0x21, 0 - .dw 0xaec0, 0xc02a, 0xaeff, 0xc02a, 0x21, 0 - .dw 0xaf40, 0xc02a, 0xaf7f, 0xc02a, 0x21, 0 - .dw 0xafc0, 0xc02a, 0xafff, 0xc02a, 0x21, 0 - .dw 0xb040, 0xc02a, 0xb07f, 0xc02a, 0x21, 0 - .dw 0xb0c0, 0xc02a, 0xb0ff, 0xc02a, 0x21, 0 - .dw 0xb140, 0xc02a, 0xb17f, 0xc02a, 0x21, 0 - .dw 0xb1c0, 0xc02a, 0xb1ff, 0xc02a, 0x21, 0 - .dw 0xb240, 0xc02a, 0xb27f, 0xc02a, 0x21, 0 - .dw 0xb2c0, 0xc02a, 0xb2ff, 0xc02a, 0x21, 0 - .dw 0xb340, 0xc02a, 0xb37f, 0xc02a, 0x21, 0 - .dw 0xb3c0, 0xc02a, 0xb3ff, 0xc02a, 0x21, 0 - .dw 0xb440, 0xc02a, 0xb47f, 0xc02a, 0x21, 0 - .dw 0xb4c0, 0xc02a, 0xb4ff, 0xc02a, 0x21, 0 - .dw 0xb540, 0xc02a, 0xb57f, 0xc02a, 0x21, 0 - .dw 0xb5c0, 0xc02a, 0xb5ff, 0xc02a, 0x21, 0 - .dw 0xb640, 0xc02a, 0xb67f, 0xc02a, 0x21, 0 - .dw 0xb6c0, 0xc02a, 0xb6ff, 0xc02a, 0x21, 0 - .dw 0xb740, 0xc02a, 0xb77f, 0xc02a, 0x21, 0 - .dw 0xb7c0, 0xc02a, 0xb7ff, 0xc02a, 0x21, 0 - .dw 0xb840, 0xc02a, 0xb87f, 0xc02a, 0x21, 0 - .dw 0xb8c0, 0xc02a, 0xb8ff, 0xc02a, 0x21, 0 - .dw 0xb940, 0xc02a, 0xb97f, 0xc02a, 0x21, 0 - .dw 0xb9c0, 0xc02a, 0xdfff, 0xc02a, 0x21, 0 - .dw 0xe040, 0xc02a, 0xe07f, 0xc02a, 0x21, 0 - .dw 0xe0c0, 0xc02a, 0xe0ff, 0xc02a, 0x21, 0 - .dw 0xe140, 0xc02a, 0xe17f, 0xc02a, 0x21, 0 - .dw 0xe1c0, 0xc02a, 0xe1ff, 0xc02a, 0x21, 0 - .dw 0xe240, 0xc02a, 0xe27f, 0xc02a, 0x21, 0 - .dw 0xe2c0, 0xc02a, 0xe2ff, 0xc02a, 0x21, 0 - .dw 0xe340, 0xc02a, 0xe37f, 0xc02a, 0x21, 0 - .dw 0xe3c0, 0xc02a, 0xe3ff, 0xc02a, 0x21, 0 - .dw 0xe440, 0xc02a, 0xe47f, 0xc02a, 0x21, 0 - .dw 0xe4c0, 0xc02a, 0xe4ff, 0xc02a, 0x21, 0 - .dw 0xe540, 0xc02a, 0xe57f, 0xc02a, 0x21, 0 - .dw 0xe5c0, 0xc02a, 0xe5ff, 0xc02a, 0x21, 0 - .dw 0xe640, 0xc02a, 0xe67f, 0xc02a, 0x21, 0 - .dw 0xe6c0, 0xc02a, 0xe6ff, 0xc02a, 0x21, 0 - .dw 0xe740, 0xc02a, 0xe77f, 0xc02a, 0x21, 0 - .dw 0xe7c0, 0xc02a, 0xe7ff, 0xc02a, 0x21, 0 - .dw 0xe840, 0xc02a, 0xe87f, 0xc02a, 0x21, 0 - .dw 0xe8c0, 0xc02a, 0xe8ff, 0xc02a, 0x21, 0 - .dw 0xe940, 0xc02a, 0xe97f, 0xc02a, 0x21, 0 - .dw 0xe9c0, 0xc02a, 0xe9ff, 0xc02a, 0x21, 0 - .dw 0xea40, 0xc02a, 0xea7f, 0xc02a, 0x21, 0 - .dw 0xeac0, 0xc02a, 0xeaff, 0xc02a, 0x21, 0 - .dw 0xeb40, 0xc02a, 0xeb7f, 0xc02a, 0x21, 0 - .dw 0xebc0, 0xc02a, 0xebff, 0xc02a, 0x21, 0 - .dw 0xec40, 0xc02a, 0xec7f, 0xc02a, 0x21, 0 - .dw 0xecc0, 0xc02a, 0xecff, 0xc02a, 0x21, 0 - .dw 0xed40, 0xc02a, 0xed7f, 0xc02a, 0x21, 0 - .dw 0xedc0, 0xc02a, 0xedff, 0xc02a, 0x21, 0 - .dw 0xee40, 0xc02a, 0xee7f, 0xc02a, 0x21, 0 - .dw 0xeec0, 0xc02a, 0xeeff, 0xc02a, 0x21, 0 - .dw 0xef40, 0xc02a, 0xef7f, 0xc02a, 0x21, 0 - .dw 0xefc0, 0xc02a, 0xefff, 0xc02a, 0x21, 0 - .dw 0xf040, 0xc02a, 0xf07f, 0xc02a, 0x21, 0 - .dw 0xf0c0, 0xc02a, 0xf0ff, 0xc02a, 0x21, 0 - .dw 0xf140, 0xc02a, 0xf17f, 0xc02a, 0x21, 0 - .dw 0xf1c0, 0xc02a, 0xf1ff, 0xc02a, 0x21, 0 - .dw 0xf240, 0xc02a, 0xf27f, 0xc02a, 0x21, 0 - .dw 0xf2c0, 0xc02a, 0xf2ff, 0xc02a, 0x21, 0 - .dw 0xf340, 0xc02a, 0xf37f, 0xc02a, 0x21, 0 - .dw 0xf3c0, 0xc02a, 0xf3ff, 0xc02a, 0x21, 0 - .dw 0xf440, 0xc02a, 0xf47f, 0xc02a, 0x21, 0 - .dw 0xf4c0, 0xc02a, 0xf4ff, 0xc02a, 0x21, 0 - .dw 0xf540, 0xc02a, 0xf57f, 0xc02a, 0x21, 0 - .dw 0xf5c0, 0xc02a, 0xf5ff, 0xc02a, 0x21, 0 - .dw 0xf640, 0xc02a, 0xf67f, 0xc02a, 0x21, 0 - .dw 0xf6c0, 0xc02a, 0xf6ff, 0xc02a, 0x21, 0 - .dw 0xf740, 0xc02a, 0xf77f, 0xc02a, 0x21, 0 - .dw 0xf7c0, 0xc02a, 0xf7ff, 0xc02a, 0x21, 0 - .dw 0xf840, 0xc02a, 0xf87f, 0xc02a, 0x21, 0 - .dw 0xf8c0, 0xc02a, 0xf8ff, 0xc02a, 0x21, 0 - .dw 0xf940, 0xc02a, 0xf97f, 0xc02a, 0x21, 0 - .dw 0xf9c0, 0xc02a, 0x1fff, 0xc02b, 0x21, 0 - .dw 0x2040, 0xc02b, 0x207f, 0xc02b, 0x21, 0 - .dw 0x20c0, 0xc02b, 0x20ff, 0xc02b, 0x21, 0 - .dw 0x2140, 0xc02b, 0x217f, 0xc02b, 0x21, 0 - .dw 0x21c0, 0xc02b, 0x21ff, 0xc02b, 0x21, 0 - .dw 0x2240, 0xc02b, 0x227f, 0xc02b, 0x21, 0 - .dw 0x22c0, 0xc02b, 0x22ff, 0xc02b, 0x21, 0 - .dw 0x2340, 0xc02b, 0x237f, 0xc02b, 0x21, 0 - .dw 0x23c0, 0xc02b, 0x23ff, 0xc02b, 0x21, 0 - .dw 0x2440, 0xc02b, 0x247f, 0xc02b, 0x21, 0 - .dw 0x24c0, 0xc02b, 0x24ff, 0xc02b, 0x21, 0 - .dw 0x2540, 0xc02b, 0x257f, 0xc02b, 0x21, 0 - .dw 0x25c0, 0xc02b, 0x25ff, 0xc02b, 0x21, 0 - .dw 0x2640, 0xc02b, 0x267f, 0xc02b, 0x21, 0 - .dw 0x26c0, 0xc02b, 0x26ff, 0xc02b, 0x21, 0 - .dw 0x2740, 0xc02b, 0x277f, 0xc02b, 0x21, 0 - .dw 0x27c0, 0xc02b, 0x27ff, 0xc02b, 0x21, 0 - .dw 0x2840, 0xc02b, 0x287f, 0xc02b, 0x21, 0 - .dw 0x28c0, 0xc02b, 0x28ff, 0xc02b, 0x21, 0 - .dw 0x2940, 0xc02b, 0x297f, 0xc02b, 0x21, 0 - .dw 0x29c0, 0xc02b, 0x29ff, 0xc02b, 0x21, 0 - .dw 0x2a40, 0xc02b, 0x2a7f, 0xc02b, 0x21, 0 - .dw 0x2ac0, 0xc02b, 0x2aff, 0xc02b, 0x21, 0 - .dw 0x2b40, 0xc02b, 0x2b7f, 0xc02b, 0x21, 0 - .dw 0x2bc0, 0xc02b, 0x2bff, 0xc02b, 0x21, 0 - .dw 0x2c40, 0xc02b, 0x2c7f, 0xc02b, 0x21, 0 - .dw 0x2cc0, 0xc02b, 0x2cff, 0xc02b, 0x21, 0 - .dw 0x2d40, 0xc02b, 0x2d7f, 0xc02b, 0x21, 0 - .dw 0x2dc0, 0xc02b, 0x2dff, 0xc02b, 0x21, 0 - .dw 0x2e40, 0xc02b, 0x2e7f, 0xc02b, 0x21, 0 - .dw 0x2ec0, 0xc02b, 0x2eff, 0xc02b, 0x21, 0 - .dw 0x2f40, 0xc02b, 0x2f7f, 0xc02b, 0x21, 0 - .dw 0x2fc0, 0xc02b, 0x2fff, 0xc02b, 0x21, 0 - .dw 0x3040, 0xc02b, 0x307f, 0xc02b, 0x21, 0 - .dw 0x30c0, 0xc02b, 0x30ff, 0xc02b, 0x21, 0 - .dw 0x3140, 0xc02b, 0x317f, 0xc02b, 0x21, 0 - .dw 0x31c0, 0xc02b, 0x31ff, 0xc02b, 0x21, 0 - .dw 0x3240, 0xc02b, 0x327f, 0xc02b, 0x21, 0 - .dw 0x32c0, 0xc02b, 0x32ff, 0xc02b, 0x21, 0 - .dw 0x3340, 0xc02b, 0x337f, 0xc02b, 0x21, 0 - .dw 0x33c0, 0xc02b, 0x33ff, 0xc02b, 0x21, 0 - .dw 0x3440, 0xc02b, 0x347f, 0xc02b, 0x21, 0 - .dw 0x34c0, 0xc02b, 0x34ff, 0xc02b, 0x21, 0 - .dw 0x3540, 0xc02b, 0x357f, 0xc02b, 0x21, 0 - .dw 0x35c0, 0xc02b, 0x35ff, 0xc02b, 0x21, 0 - .dw 0x3640, 0xc02b, 0x367f, 0xc02b, 0x21, 0 - .dw 0x36c0, 0xc02b, 0x36ff, 0xc02b, 0x21, 0 - .dw 0x3740, 0xc02b, 0x377f, 0xc02b, 0x21, 0 - .dw 0x37c0, 0xc02b, 0x37ff, 0xc02b, 0x21, 0 - .dw 0x3840, 0xc02b, 0x387f, 0xc02b, 0x21, 0 - .dw 0x38c0, 0xc02b, 0x38ff, 0xc02b, 0x21, 0 - .dw 0x3940, 0xc02b, 0x397f, 0xc02b, 0x21, 0 - .dw 0x39c0, 0xc02b, 0xffff, 0xc02b, 0x21, 0 - .dw 0x0040, 0xc02c, 0x007f, 0xc02c, 0x21, 0 - .dw 0x00c0, 0xc02c, 0x00ff, 0xc02c, 0x21, 0 - .dw 0x0140, 0xc02c, 0x017f, 0xc02c, 0x21, 0 - .dw 0x01c0, 0xc02c, 0x01ff, 0xc02c, 0x21, 0 - .dw 0x0240, 0xc02c, 0x027f, 0xc02c, 0x21, 0 - .dw 0x02c0, 0xc02c, 0x02ff, 0xc02c, 0x21, 0 - .dw 0x0340, 0xc02c, 0x037f, 0xc02c, 0x21, 0 - .dw 0x03c0, 0xc02c, 0x03ff, 0xc02c, 0x21, 0 - .dw 0x0440, 0xc02c, 0x047f, 0xc02c, 0x21, 0 - .dw 0x04c0, 0xc02c, 0x04ff, 0xc02c, 0x21, 0 - .dw 0x0540, 0xc02c, 0x057f, 0xc02c, 0x21, 0 - .dw 0x05c0, 0xc02c, 0x05ff, 0xc02c, 0x21, 0 - .dw 0x0640, 0xc02c, 0x067f, 0xc02c, 0x21, 0 - .dw 0x06c0, 0xc02c, 0x06ff, 0xc02c, 0x21, 0 - .dw 0x0740, 0xc02c, 0x077f, 0xc02c, 0x21, 0 - .dw 0x07c0, 0xc02c, 0x07ff, 0xc02c, 0x21, 0 - .dw 0x0840, 0xc02c, 0x087f, 0xc02c, 0x21, 0 - .dw 0x08c0, 0xc02c, 0x08ff, 0xc02c, 0x21, 0 - .dw 0x0940, 0xc02c, 0x097f, 0xc02c, 0x21, 0 - .dw 0x09c0, 0xc02c, 0x09ff, 0xc02c, 0x21, 0 - .dw 0x0a40, 0xc02c, 0x0a7f, 0xc02c, 0x21, 0 - .dw 0x0ac0, 0xc02c, 0x0aff, 0xc02c, 0x21, 0 - .dw 0x0b40, 0xc02c, 0x0b7f, 0xc02c, 0x21, 0 - .dw 0x0bc0, 0xc02c, 0x0bff, 0xc02c, 0x21, 0 - .dw 0x0c40, 0xc02c, 0x0c7f, 0xc02c, 0x21, 0 - .dw 0x0cc0, 0xc02c, 0x0cff, 0xc02c, 0x21, 0 - .dw 0x0d40, 0xc02c, 0x0d7f, 0xc02c, 0x21, 0 - .dw 0x0dc0, 0xc02c, 0x0dff, 0xc02c, 0x21, 0 - .dw 0x0e40, 0xc02c, 0x0e7f, 0xc02c, 0x21, 0 - .dw 0x0ec0, 0xc02c, 0x0eff, 0xc02c, 0x21, 0 - .dw 0x0f40, 0xc02c, 0x0f7f, 0xc02c, 0x21, 0 - .dw 0x0fc0, 0xc02c, 0x0fff, 0xc02c, 0x21, 0 - .dw 0x1040, 0xc02c, 0x107f, 0xc02c, 0x21, 0 - .dw 0x10c0, 0xc02c, 0x10ff, 0xc02c, 0x21, 0 - .dw 0x1140, 0xc02c, 0x117f, 0xc02c, 0x21, 0 - .dw 0x11c0, 0xc02c, 0x11ff, 0xc02c, 0x21, 0 - .dw 0x1240, 0xc02c, 0x127f, 0xc02c, 0x21, 0 - .dw 0x12c0, 0xc02c, 0x12ff, 0xc02c, 0x21, 0 - .dw 0x1340, 0xc02c, 0x137f, 0xc02c, 0x21, 0 - .dw 0x13c0, 0xc02c, 0x13ff, 0xc02c, 0x21, 0 - .dw 0x1440, 0xc02c, 0x147f, 0xc02c, 0x21, 0 - .dw 0x14c0, 0xc02c, 0x14ff, 0xc02c, 0x21, 0 - .dw 0x1540, 0xc02c, 0x157f, 0xc02c, 0x21, 0 - .dw 0x15c0, 0xc02c, 0x15ff, 0xc02c, 0x21, 0 - .dw 0x1640, 0xc02c, 0x167f, 0xc02c, 0x21, 0 - .dw 0x16c0, 0xc02c, 0x16ff, 0xc02c, 0x21, 0 - .dw 0x1740, 0xc02c, 0x177f, 0xc02c, 0x21, 0 - .dw 0x17c0, 0xc02c, 0x17ff, 0xc02c, 0x21, 0 - .dw 0x1840, 0xc02c, 0x187f, 0xc02c, 0x21, 0 - .dw 0x18c0, 0xc02c, 0x18ff, 0xc02c, 0x21, 0 - .dw 0x1940, 0xc02c, 0x197f, 0xc02c, 0x21, 0 - .dw 0x19c0, 0xc02c, 0x1fff, 0xc02c, 0x21, 0 - .dw 0x2040, 0xc02c, 0x207f, 0xc02c, 0x21, 0 - .dw 0x20c0, 0xc02c, 0x20ff, 0xc02c, 0x21, 0 - .dw 0x2140, 0xc02c, 0x217f, 0xc02c, 0x21, 0 - .dw 0x21c0, 0xc02c, 0x21ff, 0xc02c, 0x21, 0 - .dw 0x2240, 0xc02c, 0x227f, 0xc02c, 0x21, 0 - .dw 0x22c0, 0xc02c, 0x22ff, 0xc02c, 0x21, 0 - .dw 0x2340, 0xc02c, 0x237f, 0xc02c, 0x21, 0 - .dw 0x23c0, 0xc02c, 0x23ff, 0xc02c, 0x21, 0 - .dw 0x2440, 0xc02c, 0x247f, 0xc02c, 0x21, 0 - .dw 0x24c0, 0xc02c, 0x24ff, 0xc02c, 0x21, 0 - .dw 0x2540, 0xc02c, 0x257f, 0xc02c, 0x21, 0 - .dw 0x25c0, 0xc02c, 0x25ff, 0xc02c, 0x21, 0 - .dw 0x2640, 0xc02c, 0x267f, 0xc02c, 0x21, 0 - .dw 0x26c0, 0xc02c, 0x26ff, 0xc02c, 0x21, 0 - .dw 0x2740, 0xc02c, 0x277f, 0xc02c, 0x21, 0 - .dw 0x27c0, 0xc02c, 0x27ff, 0xc02c, 0x21, 0 - .dw 0x2840, 0xc02c, 0x287f, 0xc02c, 0x21, 0 - .dw 0x28c0, 0xc02c, 0x28ff, 0xc02c, 0x21, 0 - .dw 0x2940, 0xc02c, 0x297f, 0xc02c, 0x21, 0 - .dw 0x29c0, 0xc02c, 0x29ff, 0xc02c, 0x21, 0 - .dw 0x2a40, 0xc02c, 0x2a7f, 0xc02c, 0x21, 0 - .dw 0x2ac0, 0xc02c, 0x2aff, 0xc02c, 0x21, 0 - .dw 0x2b40, 0xc02c, 0x2b7f, 0xc02c, 0x21, 0 - .dw 0x2bc0, 0xc02c, 0x2bff, 0xc02c, 0x21, 0 - .dw 0x2c40, 0xc02c, 0x2c7f, 0xc02c, 0x21, 0 - .dw 0x2cc0, 0xc02c, 0x2cff, 0xc02c, 0x21, 0 - .dw 0x2d40, 0xc02c, 0x2d7f, 0xc02c, 0x21, 0 - .dw 0x2dc0, 0xc02c, 0x2dff, 0xc02c, 0x21, 0 - .dw 0x2e40, 0xc02c, 0x2e7f, 0xc02c, 0x21, 0 - .dw 0x2ec0, 0xc02c, 0x2eff, 0xc02c, 0x21, 0 - .dw 0x2f40, 0xc02c, 0x2f7f, 0xc02c, 0x21, 0 - .dw 0x2fc0, 0xc02c, 0x2fff, 0xc02c, 0x21, 0 - .dw 0x3040, 0xc02c, 0x307f, 0xc02c, 0x21, 0 - .dw 0x30c0, 0xc02c, 0x30ff, 0xc02c, 0x21, 0 - .dw 0x3140, 0xc02c, 0x317f, 0xc02c, 0x21, 0 - .dw 0x31c0, 0xc02c, 0x31ff, 0xc02c, 0x21, 0 - .dw 0x3240, 0xc02c, 0x327f, 0xc02c, 0x21, 0 - .dw 0x32c0, 0xc02c, 0x32ff, 0xc02c, 0x21, 0 - .dw 0x3340, 0xc02c, 0x337f, 0xc02c, 0x21, 0 - .dw 0x33c0, 0xc02c, 0x33ff, 0xc02c, 0x21, 0 - .dw 0x3440, 0xc02c, 0x347f, 0xc02c, 0x21, 0 - .dw 0x34c0, 0xc02c, 0x34ff, 0xc02c, 0x21, 0 - .dw 0x3540, 0xc02c, 0x357f, 0xc02c, 0x21, 0 - .dw 0x35c0, 0xc02c, 0x35ff, 0xc02c, 0x21, 0 - .dw 0x3640, 0xc02c, 0x367f, 0xc02c, 0x21, 0 - .dw 0x36c0, 0xc02c, 0x36ff, 0xc02c, 0x21, 0 - .dw 0x3740, 0xc02c, 0x377f, 0xc02c, 0x21, 0 - .dw 0x37c0, 0xc02c, 0x37ff, 0xc02c, 0x21, 0 - .dw 0x3840, 0xc02c, 0x387f, 0xc02c, 0x21, 0 - .dw 0x38c0, 0xc02c, 0x38ff, 0xc02c, 0x21, 0 - .dw 0x3940, 0xc02c, 0x397f, 0xc02c, 0x21, 0 - .dw 0x39c0, 0xc02c, 0x3fff, 0xc02c, 0x21, 0 - .dw 0x4040, 0xc02c, 0x407f, 0xc02c, 0x21, 0 - .dw 0x40c0, 0xc02c, 0x40ff, 0xc02c, 0x21, 0 - .dw 0x4140, 0xc02c, 0x417f, 0xc02c, 0x21, 0 - .dw 0x41c0, 0xc02c, 0x41ff, 0xc02c, 0x21, 0 - .dw 0x4240, 0xc02c, 0x427f, 0xc02c, 0x21, 0 - .dw 0x42c0, 0xc02c, 0x42ff, 0xc02c, 0x21, 0 - .dw 0x4340, 0xc02c, 0x437f, 0xc02c, 0x21, 0 - .dw 0x43c0, 0xc02c, 0x43ff, 0xc02c, 0x21, 0 - .dw 0x4440, 0xc02c, 0x447f, 0xc02c, 0x21, 0 - .dw 0x44c0, 0xc02c, 0x44ff, 0xc02c, 0x21, 0 - .dw 0x4540, 0xc02c, 0x457f, 0xc02c, 0x21, 0 - .dw 0x45c0, 0xc02c, 0x45ff, 0xc02c, 0x21, 0 - .dw 0x4640, 0xc02c, 0x467f, 0xc02c, 0x21, 0 - .dw 0x46c0, 0xc02c, 0x46ff, 0xc02c, 0x21, 0 - .dw 0x4740, 0xc02c, 0x477f, 0xc02c, 0x21, 0 - .dw 0x47c0, 0xc02c, 0x47ff, 0xc02c, 0x21, 0 - .dw 0x4840, 0xc02c, 0x487f, 0xc02c, 0x21, 0 - .dw 0x48c0, 0xc02c, 0x48ff, 0xc02c, 0x21, 0 - .dw 0x4940, 0xc02c, 0x497f, 0xc02c, 0x21, 0 - .dw 0x49c0, 0xc02c, 0x49ff, 0xc02c, 0x21, 0 - .dw 0x4a40, 0xc02c, 0x4a7f, 0xc02c, 0x21, 0 - .dw 0x4ac0, 0xc02c, 0x4aff, 0xc02c, 0x21, 0 - .dw 0x4b40, 0xc02c, 0x4b7f, 0xc02c, 0x21, 0 - .dw 0x4bc0, 0xc02c, 0x4bff, 0xc02c, 0x21, 0 - .dw 0x4c40, 0xc02c, 0x4c7f, 0xc02c, 0x21, 0 - .dw 0x4cc0, 0xc02c, 0x4cff, 0xc02c, 0x21, 0 - .dw 0x4d40, 0xc02c, 0x4d7f, 0xc02c, 0x21, 0 - .dw 0x4dc0, 0xc02c, 0x4dff, 0xc02c, 0x21, 0 - .dw 0x4e40, 0xc02c, 0x4e7f, 0xc02c, 0x21, 0 - .dw 0x4ec0, 0xc02c, 0x4eff, 0xc02c, 0x21, 0 - .dw 0x4f40, 0xc02c, 0x4f7f, 0xc02c, 0x21, 0 - .dw 0x4fc0, 0xc02c, 0x4fff, 0xc02c, 0x21, 0 - .dw 0x5040, 0xc02c, 0x507f, 0xc02c, 0x21, 0 - .dw 0x50c0, 0xc02c, 0x50ff, 0xc02c, 0x21, 0 - .dw 0x5140, 0xc02c, 0x517f, 0xc02c, 0x21, 0 - .dw 0x51c0, 0xc02c, 0x51ff, 0xc02c, 0x21, 0 - .dw 0x5240, 0xc02c, 0x527f, 0xc02c, 0x21, 0 - .dw 0x52c0, 0xc02c, 0x52ff, 0xc02c, 0x21, 0 - .dw 0x5340, 0xc02c, 0x537f, 0xc02c, 0x21, 0 - .dw 0x53c0, 0xc02c, 0x53ff, 0xc02c, 0x21, 0 - .dw 0x5440, 0xc02c, 0x547f, 0xc02c, 0x21, 0 - .dw 0x54c0, 0xc02c, 0x54ff, 0xc02c, 0x21, 0 - .dw 0x5540, 0xc02c, 0x557f, 0xc02c, 0x21, 0 - .dw 0x55c0, 0xc02c, 0x55ff, 0xc02c, 0x21, 0 - .dw 0x5640, 0xc02c, 0x567f, 0xc02c, 0x21, 0 - .dw 0x56c0, 0xc02c, 0x56ff, 0xc02c, 0x21, 0 - .dw 0x5740, 0xc02c, 0x577f, 0xc02c, 0x21, 0 - .dw 0x57c0, 0xc02c, 0x57ff, 0xc02c, 0x21, 0 - .dw 0x5840, 0xc02c, 0x587f, 0xc02c, 0x21, 0 - .dw 0x58c0, 0xc02c, 0x58ff, 0xc02c, 0x21, 0 - .dw 0x5940, 0xc02c, 0x597f, 0xc02c, 0x21, 0 - .dw 0x59c0, 0xc02c, 0x5fff, 0xc02c, 0x21, 0 - .dw 0x6040, 0xc02c, 0x607f, 0xc02c, 0x21, 0 - .dw 0x60c0, 0xc02c, 0x60ff, 0xc02c, 0x21, 0 - .dw 0x6140, 0xc02c, 0x617f, 0xc02c, 0x21, 0 - .dw 0x61c0, 0xc02c, 0x61ff, 0xc02c, 0x21, 0 - .dw 0x6240, 0xc02c, 0x627f, 0xc02c, 0x21, 0 - .dw 0x62c0, 0xc02c, 0x62ff, 0xc02c, 0x21, 0 - .dw 0x6340, 0xc02c, 0x637f, 0xc02c, 0x21, 0 - .dw 0x63c0, 0xc02c, 0x63ff, 0xc02c, 0x21, 0 - .dw 0x6440, 0xc02c, 0x647f, 0xc02c, 0x21, 0 - .dw 0x64c0, 0xc02c, 0x64ff, 0xc02c, 0x21, 0 - .dw 0x6540, 0xc02c, 0x657f, 0xc02c, 0x21, 0 - .dw 0x65c0, 0xc02c, 0x65ff, 0xc02c, 0x21, 0 - .dw 0x6640, 0xc02c, 0x667f, 0xc02c, 0x21, 0 - .dw 0x66c0, 0xc02c, 0x66ff, 0xc02c, 0x21, 0 - .dw 0x6740, 0xc02c, 0x677f, 0xc02c, 0x21, 0 - .dw 0x67c0, 0xc02c, 0x67ff, 0xc02c, 0x21, 0 - .dw 0x6840, 0xc02c, 0x687f, 0xc02c, 0x21, 0 - .dw 0x68c0, 0xc02c, 0x68ff, 0xc02c, 0x21, 0 - .dw 0x6940, 0xc02c, 0x697f, 0xc02c, 0x21, 0 - .dw 0x69c0, 0xc02c, 0x69ff, 0xc02c, 0x21, 0 - .dw 0x6a40, 0xc02c, 0x6a7f, 0xc02c, 0x21, 0 - .dw 0x6ac0, 0xc02c, 0x6aff, 0xc02c, 0x21, 0 - .dw 0x6b40, 0xc02c, 0x6b7f, 0xc02c, 0x21, 0 - .dw 0x6bc0, 0xc02c, 0x6bff, 0xc02c, 0x21, 0 - .dw 0x6c40, 0xc02c, 0x6c7f, 0xc02c, 0x21, 0 - .dw 0x6cc0, 0xc02c, 0x6cff, 0xc02c, 0x21, 0 - .dw 0x6d40, 0xc02c, 0x6d7f, 0xc02c, 0x21, 0 - .dw 0x6dc0, 0xc02c, 0x6dff, 0xc02c, 0x21, 0 - .dw 0x6e40, 0xc02c, 0x6e7f, 0xc02c, 0x21, 0 - .dw 0x6ec0, 0xc02c, 0x6eff, 0xc02c, 0x21, 0 - .dw 0x6f40, 0xc02c, 0x6f7f, 0xc02c, 0x21, 0 - .dw 0x6fc0, 0xc02c, 0x6fff, 0xc02c, 0x21, 0 - .dw 0x7040, 0xc02c, 0x707f, 0xc02c, 0x21, 0 - .dw 0x70c0, 0xc02c, 0x70ff, 0xc02c, 0x21, 0 - .dw 0x7140, 0xc02c, 0x717f, 0xc02c, 0x21, 0 - .dw 0x71c0, 0xc02c, 0x71ff, 0xc02c, 0x21, 0 - .dw 0x7240, 0xc02c, 0x727f, 0xc02c, 0x21, 0 - .dw 0x72c0, 0xc02c, 0x72ff, 0xc02c, 0x21, 0 - .dw 0x7340, 0xc02c, 0x737f, 0xc02c, 0x21, 0 - .dw 0x73c0, 0xc02c, 0x73ff, 0xc02c, 0x21, 0 - .dw 0x7440, 0xc02c, 0x747f, 0xc02c, 0x21, 0 - .dw 0x74c0, 0xc02c, 0x74ff, 0xc02c, 0x21, 0 - .dw 0x7540, 0xc02c, 0x757f, 0xc02c, 0x21, 0 - .dw 0x75c0, 0xc02c, 0x75ff, 0xc02c, 0x21, 0 - .dw 0x7640, 0xc02c, 0x767f, 0xc02c, 0x21, 0 - .dw 0x76c0, 0xc02c, 0x76ff, 0xc02c, 0x21, 0 - .dw 0x7740, 0xc02c, 0x777f, 0xc02c, 0x21, 0 - .dw 0x77c0, 0xc02c, 0x77ff, 0xc02c, 0x21, 0 - .dw 0x7840, 0xc02c, 0x787f, 0xc02c, 0x21, 0 - .dw 0x78c0, 0xc02c, 0x78ff, 0xc02c, 0x21, 0 - .dw 0x7940, 0xc02c, 0x797f, 0xc02c, 0x21, 0 - .dw 0x79c0, 0xc02c, 0x7fff, 0xc02c, 0x21, 0 - .dw 0x8040, 0xc02c, 0x807f, 0xc02c, 0x21, 0 - .dw 0x80c0, 0xc02c, 0x80ff, 0xc02c, 0x21, 0 - .dw 0x8140, 0xc02c, 0x817f, 0xc02c, 0x21, 0 - .dw 0x81c0, 0xc02c, 0x81ff, 0xc02c, 0x21, 0 - .dw 0x8240, 0xc02c, 0x827f, 0xc02c, 0x21, 0 - .dw 0x82c0, 0xc02c, 0x82ff, 0xc02c, 0x21, 0 - .dw 0x8340, 0xc02c, 0x837f, 0xc02c, 0x21, 0 - .dw 0x83c0, 0xc02c, 0x83ff, 0xc02c, 0x21, 0 - .dw 0x8440, 0xc02c, 0x847f, 0xc02c, 0x21, 0 - .dw 0x84c0, 0xc02c, 0x84ff, 0xc02c, 0x21, 0 - .dw 0x8540, 0xc02c, 0x857f, 0xc02c, 0x21, 0 - .dw 0x85c0, 0xc02c, 0x85ff, 0xc02c, 0x21, 0 - .dw 0x8640, 0xc02c, 0x867f, 0xc02c, 0x21, 0 - .dw 0x86c0, 0xc02c, 0x86ff, 0xc02c, 0x21, 0 - .dw 0x8740, 0xc02c, 0x877f, 0xc02c, 0x21, 0 - .dw 0x87c0, 0xc02c, 0x87ff, 0xc02c, 0x21, 0 - .dw 0x8840, 0xc02c, 0x887f, 0xc02c, 0x21, 0 - .dw 0x88c0, 0xc02c, 0x88ff, 0xc02c, 0x21, 0 - .dw 0x8940, 0xc02c, 0x897f, 0xc02c, 0x21, 0 - .dw 0x89c0, 0xc02c, 0x89ff, 0xc02c, 0x21, 0 - .dw 0x8a40, 0xc02c, 0x8a7f, 0xc02c, 0x21, 0 - .dw 0x8ac0, 0xc02c, 0x8aff, 0xc02c, 0x21, 0 - .dw 0x8b40, 0xc02c, 0x8b7f, 0xc02c, 0x21, 0 - .dw 0x8bc0, 0xc02c, 0x8bff, 0xc02c, 0x21, 0 - .dw 0x8c40, 0xc02c, 0x8c7f, 0xc02c, 0x21, 0 - .dw 0x8cc0, 0xc02c, 0x8cff, 0xc02c, 0x21, 0 - .dw 0x8d40, 0xc02c, 0x8d7f, 0xc02c, 0x21, 0 - .dw 0x8dc0, 0xc02c, 0x8dff, 0xc02c, 0x21, 0 - .dw 0x8e40, 0xc02c, 0x8e7f, 0xc02c, 0x21, 0 - .dw 0x8ec0, 0xc02c, 0x8eff, 0xc02c, 0x21, 0 - .dw 0x8f40, 0xc02c, 0x8f7f, 0xc02c, 0x21, 0 - .dw 0x8fc0, 0xc02c, 0x8fff, 0xc02c, 0x21, 0 - .dw 0x9040, 0xc02c, 0x907f, 0xc02c, 0x21, 0 - .dw 0x90c0, 0xc02c, 0x90ff, 0xc02c, 0x21, 0 - .dw 0x9140, 0xc02c, 0x917f, 0xc02c, 0x21, 0 - .dw 0x91c0, 0xc02c, 0x91ff, 0xc02c, 0x21, 0 - .dw 0x9240, 0xc02c, 0x927f, 0xc02c, 0x21, 0 - .dw 0x92c0, 0xc02c, 0x92ff, 0xc02c, 0x21, 0 - .dw 0x9340, 0xc02c, 0x937f, 0xc02c, 0x21, 0 - .dw 0x93c0, 0xc02c, 0x93ff, 0xc02c, 0x21, 0 - .dw 0x9440, 0xc02c, 0x947f, 0xc02c, 0x21, 0 - .dw 0x94c0, 0xc02c, 0x94ff, 0xc02c, 0x21, 0 - .dw 0x9540, 0xc02c, 0x957f, 0xc02c, 0x21, 0 - .dw 0x95c0, 0xc02c, 0x95ff, 0xc02c, 0x21, 0 - .dw 0x9640, 0xc02c, 0x967f, 0xc02c, 0x21, 0 - .dw 0x96c0, 0xc02c, 0x96ff, 0xc02c, 0x21, 0 - .dw 0x9740, 0xc02c, 0x977f, 0xc02c, 0x21, 0 - .dw 0x97c0, 0xc02c, 0x97ff, 0xc02c, 0x21, 0 - .dw 0x9840, 0xc02c, 0x987f, 0xc02c, 0x21, 0 - .dw 0x98c0, 0xc02c, 0x98ff, 0xc02c, 0x21, 0 - .dw 0x9940, 0xc02c, 0x997f, 0xc02c, 0x21, 0 - .dw 0x99c0, 0xc02c, 0x9fff, 0xc02c, 0x21, 0 - .dw 0xa040, 0xc02c, 0xa07f, 0xc02c, 0x21, 0 - .dw 0xa0c0, 0xc02c, 0xa0ff, 0xc02c, 0x21, 0 - .dw 0xa140, 0xc02c, 0xa17f, 0xc02c, 0x21, 0 - .dw 0xa1c0, 0xc02c, 0xa1ff, 0xc02c, 0x21, 0 - .dw 0xa240, 0xc02c, 0xa27f, 0xc02c, 0x21, 0 - .dw 0xa2c0, 0xc02c, 0xa2ff, 0xc02c, 0x21, 0 - .dw 0xa340, 0xc02c, 0xa37f, 0xc02c, 0x21, 0 - .dw 0xa3c0, 0xc02c, 0xa3ff, 0xc02c, 0x21, 0 - .dw 0xa440, 0xc02c, 0xa47f, 0xc02c, 0x21, 0 - .dw 0xa4c0, 0xc02c, 0xa4ff, 0xc02c, 0x21, 0 - .dw 0xa540, 0xc02c, 0xa57f, 0xc02c, 0x21, 0 - .dw 0xa5c0, 0xc02c, 0xa5ff, 0xc02c, 0x21, 0 - .dw 0xa640, 0xc02c, 0xa67f, 0xc02c, 0x21, 0 - .dw 0xa6c0, 0xc02c, 0xa6ff, 0xc02c, 0x21, 0 - .dw 0xa740, 0xc02c, 0xa77f, 0xc02c, 0x21, 0 - .dw 0xa7c0, 0xc02c, 0xa7ff, 0xc02c, 0x21, 0 - .dw 0xa840, 0xc02c, 0xa87f, 0xc02c, 0x21, 0 - .dw 0xa8c0, 0xc02c, 0xa8ff, 0xc02c, 0x21, 0 - .dw 0xa940, 0xc02c, 0xa97f, 0xc02c, 0x21, 0 - .dw 0xa9c0, 0xc02c, 0xa9ff, 0xc02c, 0x21, 0 - .dw 0xaa40, 0xc02c, 0xaa7f, 0xc02c, 0x21, 0 - .dw 0xaac0, 0xc02c, 0xaaff, 0xc02c, 0x21, 0 - .dw 0xab40, 0xc02c, 0xab7f, 0xc02c, 0x21, 0 - .dw 0xabc0, 0xc02c, 0xabff, 0xc02c, 0x21, 0 - .dw 0xac40, 0xc02c, 0xac7f, 0xc02c, 0x21, 0 - .dw 0xacc0, 0xc02c, 0xacff, 0xc02c, 0x21, 0 - .dw 0xad40, 0xc02c, 0xad7f, 0xc02c, 0x21, 0 - .dw 0xadc0, 0xc02c, 0xadff, 0xc02c, 0x21, 0 - .dw 0xae40, 0xc02c, 0xae7f, 0xc02c, 0x21, 0 - .dw 0xaec0, 0xc02c, 0xaeff, 0xc02c, 0x21, 0 - .dw 0xaf40, 0xc02c, 0xaf7f, 0xc02c, 0x21, 0 - .dw 0xafc0, 0xc02c, 0xafff, 0xc02c, 0x21, 0 - .dw 0xb040, 0xc02c, 0xb07f, 0xc02c, 0x21, 0 - .dw 0xb0c0, 0xc02c, 0xb0ff, 0xc02c, 0x21, 0 - .dw 0xb140, 0xc02c, 0xb17f, 0xc02c, 0x21, 0 - .dw 0xb1c0, 0xc02c, 0xb1ff, 0xc02c, 0x21, 0 - .dw 0xb240, 0xc02c, 0xb27f, 0xc02c, 0x21, 0 - .dw 0xb2c0, 0xc02c, 0xb2ff, 0xc02c, 0x21, 0 - .dw 0xb340, 0xc02c, 0xb37f, 0xc02c, 0x21, 0 - .dw 0xb3c0, 0xc02c, 0xb3ff, 0xc02c, 0x21, 0 - .dw 0xb440, 0xc02c, 0xb47f, 0xc02c, 0x21, 0 - .dw 0xb4c0, 0xc02c, 0xb4ff, 0xc02c, 0x21, 0 - .dw 0xb540, 0xc02c, 0xb57f, 0xc02c, 0x21, 0 - .dw 0xb5c0, 0xc02c, 0xb5ff, 0xc02c, 0x21, 0 - .dw 0xb640, 0xc02c, 0xb67f, 0xc02c, 0x21, 0 - .dw 0xb6c0, 0xc02c, 0xb6ff, 0xc02c, 0x21, 0 - .dw 0xb740, 0xc02c, 0xb77f, 0xc02c, 0x21, 0 - .dw 0xb7c0, 0xc02c, 0xb7ff, 0xc02c, 0x21, 0 - .dw 0xb840, 0xc02c, 0xb87f, 0xc02c, 0x21, 0 - .dw 0xb8c0, 0xc02c, 0xb8ff, 0xc02c, 0x21, 0 - .dw 0xb940, 0xc02c, 0xb97f, 0xc02c, 0x21, 0 - .dw 0xb9c0, 0xc02c, 0xbfff, 0xc02c, 0x21, 0 - .dw 0xc040, 0xc02c, 0xc07f, 0xc02c, 0x21, 0 - .dw 0xc0c0, 0xc02c, 0xc0ff, 0xc02c, 0x21, 0 - .dw 0xc140, 0xc02c, 0xc17f, 0xc02c, 0x21, 0 - .dw 0xc1c0, 0xc02c, 0xc1ff, 0xc02c, 0x21, 0 - .dw 0xc240, 0xc02c, 0xc27f, 0xc02c, 0x21, 0 - .dw 0xc2c0, 0xc02c, 0xc2ff, 0xc02c, 0x21, 0 - .dw 0xc340, 0xc02c, 0xc37f, 0xc02c, 0x21, 0 - .dw 0xc3c0, 0xc02c, 0xc3ff, 0xc02c, 0x21, 0 - .dw 0xc440, 0xc02c, 0xc47f, 0xc02c, 0x21, 0 - .dw 0xc4c0, 0xc02c, 0xc4ff, 0xc02c, 0x21, 0 - .dw 0xc540, 0xc02c, 0xc57f, 0xc02c, 0x21, 0 - .dw 0xc5c0, 0xc02c, 0xc5ff, 0xc02c, 0x21, 0 - .dw 0xc640, 0xc02c, 0xc67f, 0xc02c, 0x21, 0 - .dw 0xc6c0, 0xc02c, 0xc6ff, 0xc02c, 0x21, 0 - .dw 0xc740, 0xc02c, 0xc77f, 0xc02c, 0x21, 0 - .dw 0xc7c0, 0xc02c, 0xc7ff, 0xc02c, 0x21, 0 - .dw 0xc840, 0xc02c, 0xc87f, 0xc02c, 0x21, 0 - .dw 0xc8c0, 0xc02c, 0xc8ff, 0xc02c, 0x21, 0 - .dw 0xc940, 0xc02c, 0xc97f, 0xc02c, 0x21, 0 - .dw 0xc9c0, 0xc02c, 0xc9ff, 0xc02c, 0x21, 0 - .dw 0xca40, 0xc02c, 0xca7f, 0xc02c, 0x21, 0 - .dw 0xcac0, 0xc02c, 0xcaff, 0xc02c, 0x21, 0 - .dw 0xcb40, 0xc02c, 0xcb7f, 0xc02c, 0x21, 0 - .dw 0xcbc0, 0xc02c, 0xcbff, 0xc02c, 0x21, 0 - .dw 0xcc40, 0xc02c, 0xcc7f, 0xc02c, 0x21, 0 - .dw 0xccc0, 0xc02c, 0xccff, 0xc02c, 0x21, 0 - .dw 0xcd40, 0xc02c, 0xcd7f, 0xc02c, 0x21, 0 - .dw 0xcdc0, 0xc02c, 0xcdff, 0xc02c, 0x21, 0 - .dw 0xce40, 0xc02c, 0xce7f, 0xc02c, 0x21, 0 - .dw 0xcec0, 0xc02c, 0xceff, 0xc02c, 0x21, 0 - .dw 0xcf40, 0xc02c, 0xcf7f, 0xc02c, 0x21, 0 - .dw 0xcfc0, 0xc02c, 0xcfff, 0xc02c, 0x21, 0 - .dw 0xd040, 0xc02c, 0xd07f, 0xc02c, 0x21, 0 - .dw 0xd0c0, 0xc02c, 0xd0ff, 0xc02c, 0x21, 0 - .dw 0xd140, 0xc02c, 0xd17f, 0xc02c, 0x21, 0 - .dw 0xd1c0, 0xc02c, 0xd1ff, 0xc02c, 0x21, 0 - .dw 0xd240, 0xc02c, 0xd27f, 0xc02c, 0x21, 0 - .dw 0xd2c0, 0xc02c, 0xd2ff, 0xc02c, 0x21, 0 - .dw 0xd340, 0xc02c, 0xd37f, 0xc02c, 0x21, 0 - .dw 0xd3c0, 0xc02c, 0xd3ff, 0xc02c, 0x21, 0 - .dw 0xd440, 0xc02c, 0xd47f, 0xc02c, 0x21, 0 - .dw 0xd4c0, 0xc02c, 0xd4ff, 0xc02c, 0x21, 0 - .dw 0xd540, 0xc02c, 0xd57f, 0xc02c, 0x21, 0 - .dw 0xd5c0, 0xc02c, 0xd5ff, 0xc02c, 0x21, 0 - .dw 0xd640, 0xc02c, 0xd67f, 0xc02c, 0x21, 0 - .dw 0xd6c0, 0xc02c, 0xd6ff, 0xc02c, 0x21, 0 - .dw 0xd740, 0xc02c, 0xd77f, 0xc02c, 0x21, 0 - .dw 0xd7c0, 0xc02c, 0xd7ff, 0xc02c, 0x21, 0 - .dw 0xd840, 0xc02c, 0xd87f, 0xc02c, 0x21, 0 - .dw 0xd8c0, 0xc02c, 0xd8ff, 0xc02c, 0x21, 0 - .dw 0xd940, 0xc02c, 0xd97f, 0xc02c, 0x21, 0 - .dw 0xd9c0, 0xc02c, 0xdfff, 0xc02c, 0x21, 0 - .dw 0xe040, 0xc02c, 0xe07f, 0xc02c, 0x21, 0 - .dw 0xe0c0, 0xc02c, 0xe0ff, 0xc02c, 0x21, 0 - .dw 0xe140, 0xc02c, 0xe17f, 0xc02c, 0x21, 0 - .dw 0xe1c0, 0xc02c, 0xe1ff, 0xc02c, 0x21, 0 - .dw 0xe240, 0xc02c, 0xe27f, 0xc02c, 0x21, 0 - .dw 0xe2c0, 0xc02c, 0xe2ff, 0xc02c, 0x21, 0 - .dw 0xe340, 0xc02c, 0xe37f, 0xc02c, 0x21, 0 - .dw 0xe3c0, 0xc02c, 0xe3ff, 0xc02c, 0x21, 0 - .dw 0xe440, 0xc02c, 0xe47f, 0xc02c, 0x21, 0 - .dw 0xe4c0, 0xc02c, 0xe4ff, 0xc02c, 0x21, 0 - .dw 0xe540, 0xc02c, 0xe57f, 0xc02c, 0x21, 0 - .dw 0xe5c0, 0xc02c, 0xe5ff, 0xc02c, 0x21, 0 - .dw 0xe640, 0xc02c, 0xe67f, 0xc02c, 0x21, 0 - .dw 0xe6c0, 0xc02c, 0xe6ff, 0xc02c, 0x21, 0 - .dw 0xe740, 0xc02c, 0xe77f, 0xc02c, 0x21, 0 - .dw 0xe7c0, 0xc02c, 0xe7ff, 0xc02c, 0x21, 0 - .dw 0xe840, 0xc02c, 0xe87f, 0xc02c, 0x21, 0 - .dw 0xe8c0, 0xc02c, 0xe8ff, 0xc02c, 0x21, 0 - .dw 0xe940, 0xc02c, 0xe97f, 0xc02c, 0x21, 0 - .dw 0xe9c0, 0xc02c, 0xe9ff, 0xc02c, 0x21, 0 - .dw 0xea40, 0xc02c, 0xea7f, 0xc02c, 0x21, 0 - .dw 0xeac0, 0xc02c, 0xeaff, 0xc02c, 0x21, 0 - .dw 0xeb40, 0xc02c, 0xeb7f, 0xc02c, 0x21, 0 - .dw 0xebc0, 0xc02c, 0xebff, 0xc02c, 0x21, 0 - .dw 0xec40, 0xc02c, 0xec7f, 0xc02c, 0x21, 0 - .dw 0xecc0, 0xc02c, 0xecff, 0xc02c, 0x21, 0 - .dw 0xed40, 0xc02c, 0xed7f, 0xc02c, 0x21, 0 - .dw 0xedc0, 0xc02c, 0xedff, 0xc02c, 0x21, 0 - .dw 0xee40, 0xc02c, 0xee7f, 0xc02c, 0x21, 0 - .dw 0xeec0, 0xc02c, 0xeeff, 0xc02c, 0x21, 0 - .dw 0xef40, 0xc02c, 0xef7f, 0xc02c, 0x21, 0 - .dw 0xefc0, 0xc02c, 0xefff, 0xc02c, 0x21, 0 - .dw 0xf040, 0xc02c, 0xf07f, 0xc02c, 0x21, 0 - .dw 0xf0c0, 0xc02c, 0xf0ff, 0xc02c, 0x21, 0 - .dw 0xf140, 0xc02c, 0xf17f, 0xc02c, 0x21, 0 - .dw 0xf1c0, 0xc02c, 0xf1ff, 0xc02c, 0x21, 0 - .dw 0xf240, 0xc02c, 0xf27f, 0xc02c, 0x21, 0 - .dw 0xf2c0, 0xc02c, 0xf2ff, 0xc02c, 0x21, 0 - .dw 0xf340, 0xc02c, 0xf37f, 0xc02c, 0x21, 0 - .dw 0xf3c0, 0xc02c, 0xf3ff, 0xc02c, 0x21, 0 - .dw 0xf440, 0xc02c, 0xf47f, 0xc02c, 0x21, 0 - .dw 0xf4c0, 0xc02c, 0xf4ff, 0xc02c, 0x21, 0 - .dw 0xf540, 0xc02c, 0xf57f, 0xc02c, 0x21, 0 - .dw 0xf5c0, 0xc02c, 0xf5ff, 0xc02c, 0x21, 0 - .dw 0xf640, 0xc02c, 0xf67f, 0xc02c, 0x21, 0 - .dw 0xf6c0, 0xc02c, 0xf6ff, 0xc02c, 0x21, 0 - .dw 0xf740, 0xc02c, 0xf77f, 0xc02c, 0x21, 0 - .dw 0xf7c0, 0xc02c, 0xf7ff, 0xc02c, 0x21, 0 - .dw 0xf840, 0xc02c, 0xf87f, 0xc02c, 0x21, 0 - .dw 0xf8c0, 0xc02c, 0xf8ff, 0xc02c, 0x21, 0 - .dw 0xf940, 0xc02c, 0xf97f, 0xc02c, 0x21, 0 - .dw 0xf9c0, 0xc02c, 0xffff, 0xc02c, 0x21, 0 - .dw 0x0040, 0xc02d, 0x007f, 0xc02d, 0x21, 0 - .dw 0x00c0, 0xc02d, 0x00ff, 0xc02d, 0x21, 0 - .dw 0x0140, 0xc02d, 0x017f, 0xc02d, 0x21, 0 - .dw 0x01c0, 0xc02d, 0x01ff, 0xc02d, 0x21, 0 - .dw 0x0240, 0xc02d, 0x027f, 0xc02d, 0x21, 0 - .dw 0x02c0, 0xc02d, 0x02ff, 0xc02d, 0x21, 0 - .dw 0x0340, 0xc02d, 0x037f, 0xc02d, 0x21, 0 - .dw 0x03c0, 0xc02d, 0x03ff, 0xc02d, 0x21, 0 - .dw 0x0440, 0xc02d, 0x047f, 0xc02d, 0x21, 0 - .dw 0x04c0, 0xc02d, 0x04ff, 0xc02d, 0x21, 0 - .dw 0x0540, 0xc02d, 0x057f, 0xc02d, 0x21, 0 - .dw 0x05c0, 0xc02d, 0x05ff, 0xc02d, 0x21, 0 - .dw 0x0640, 0xc02d, 0x067f, 0xc02d, 0x21, 0 - .dw 0x06c0, 0xc02d, 0x06ff, 0xc02d, 0x21, 0 - .dw 0x0740, 0xc02d, 0x077f, 0xc02d, 0x21, 0 - .dw 0x07c0, 0xc02d, 0x07ff, 0xc02d, 0x21, 0 - .dw 0x0840, 0xc02d, 0x087f, 0xc02d, 0x21, 0 - .dw 0x08c0, 0xc02d, 0x08ff, 0xc02d, 0x21, 0 - .dw 0x0940, 0xc02d, 0x097f, 0xc02d, 0x21, 0 - .dw 0x09c0, 0xc02d, 0x09ff, 0xc02d, 0x21, 0 - .dw 0x0a40, 0xc02d, 0x0a7f, 0xc02d, 0x21, 0 - .dw 0x0ac0, 0xc02d, 0x0aff, 0xc02d, 0x21, 0 - .dw 0x0b40, 0xc02d, 0x0b7f, 0xc02d, 0x21, 0 - .dw 0x0bc0, 0xc02d, 0x0bff, 0xc02d, 0x21, 0 - .dw 0x0c40, 0xc02d, 0x0c7f, 0xc02d, 0x21, 0 - .dw 0x0cc0, 0xc02d, 0x0cff, 0xc02d, 0x21, 0 - .dw 0x0d40, 0xc02d, 0x0d7f, 0xc02d, 0x21, 0 - .dw 0x0dc0, 0xc02d, 0x0dff, 0xc02d, 0x21, 0 - .dw 0x0e40, 0xc02d, 0x0e7f, 0xc02d, 0x21, 0 - .dw 0x0ec0, 0xc02d, 0x0eff, 0xc02d, 0x21, 0 - .dw 0x0f40, 0xc02d, 0x0f7f, 0xc02d, 0x21, 0 - .dw 0x0fc0, 0xc02d, 0x0fff, 0xc02d, 0x21, 0 - .dw 0x1040, 0xc02d, 0x107f, 0xc02d, 0x21, 0 - .dw 0x10c0, 0xc02d, 0x10ff, 0xc02d, 0x21, 0 - .dw 0x1140, 0xc02d, 0x117f, 0xc02d, 0x21, 0 - .dw 0x11c0, 0xc02d, 0x11ff, 0xc02d, 0x21, 0 - .dw 0x1240, 0xc02d, 0x127f, 0xc02d, 0x21, 0 - .dw 0x12c0, 0xc02d, 0x12ff, 0xc02d, 0x21, 0 - .dw 0x1340, 0xc02d, 0x137f, 0xc02d, 0x21, 0 - .dw 0x13c0, 0xc02d, 0x13ff, 0xc02d, 0x21, 0 - .dw 0x1440, 0xc02d, 0x147f, 0xc02d, 0x21, 0 - .dw 0x14c0, 0xc02d, 0x14ff, 0xc02d, 0x21, 0 - .dw 0x1540, 0xc02d, 0x157f, 0xc02d, 0x21, 0 - .dw 0x15c0, 0xc02d, 0x15ff, 0xc02d, 0x21, 0 - .dw 0x1640, 0xc02d, 0x167f, 0xc02d, 0x21, 0 - .dw 0x16c0, 0xc02d, 0x16ff, 0xc02d, 0x21, 0 - .dw 0x1740, 0xc02d, 0x177f, 0xc02d, 0x21, 0 - .dw 0x17c0, 0xc02d, 0x17ff, 0xc02d, 0x21, 0 - .dw 0x1840, 0xc02d, 0x187f, 0xc02d, 0x21, 0 - .dw 0x18c0, 0xc02d, 0x18ff, 0xc02d, 0x21, 0 - .dw 0x1940, 0xc02d, 0x197f, 0xc02d, 0x21, 0 - .dw 0x19c0, 0xc02d, 0x1fff, 0xc02d, 0x21, 0 - .dw 0x2040, 0xc02d, 0x207f, 0xc02d, 0x21, 0 - .dw 0x20c0, 0xc02d, 0x20ff, 0xc02d, 0x21, 0 - .dw 0x2140, 0xc02d, 0x217f, 0xc02d, 0x21, 0 - .dw 0x21c0, 0xc02d, 0x21ff, 0xc02d, 0x21, 0 - .dw 0x2240, 0xc02d, 0x227f, 0xc02d, 0x21, 0 - .dw 0x22c0, 0xc02d, 0x22ff, 0xc02d, 0x21, 0 - .dw 0x2340, 0xc02d, 0x237f, 0xc02d, 0x21, 0 - .dw 0x23c0, 0xc02d, 0x23ff, 0xc02d, 0x21, 0 - .dw 0x2440, 0xc02d, 0x247f, 0xc02d, 0x21, 0 - .dw 0x24c0, 0xc02d, 0x24ff, 0xc02d, 0x21, 0 - .dw 0x2540, 0xc02d, 0x257f, 0xc02d, 0x21, 0 - .dw 0x25c0, 0xc02d, 0x25ff, 0xc02d, 0x21, 0 - .dw 0x2640, 0xc02d, 0x267f, 0xc02d, 0x21, 0 - .dw 0x26c0, 0xc02d, 0x26ff, 0xc02d, 0x21, 0 - .dw 0x2740, 0xc02d, 0x277f, 0xc02d, 0x21, 0 - .dw 0x27c0, 0xc02d, 0x27ff, 0xc02d, 0x21, 0 - .dw 0x2840, 0xc02d, 0x287f, 0xc02d, 0x21, 0 - .dw 0x28c0, 0xc02d, 0x28ff, 0xc02d, 0x21, 0 - .dw 0x2940, 0xc02d, 0x297f, 0xc02d, 0x21, 0 - .dw 0x29c0, 0xc02d, 0x29ff, 0xc02d, 0x21, 0 - .dw 0x2a40, 0xc02d, 0x2a7f, 0xc02d, 0x21, 0 - .dw 0x2ac0, 0xc02d, 0x2aff, 0xc02d, 0x21, 0 - .dw 0x2b40, 0xc02d, 0x2b7f, 0xc02d, 0x21, 0 - .dw 0x2bc0, 0xc02d, 0x2bff, 0xc02d, 0x21, 0 - .dw 0x2c40, 0xc02d, 0x2c7f, 0xc02d, 0x21, 0 - .dw 0x2cc0, 0xc02d, 0x2cff, 0xc02d, 0x21, 0 - .dw 0x2d40, 0xc02d, 0x2d7f, 0xc02d, 0x21, 0 - .dw 0x2dc0, 0xc02d, 0x2dff, 0xc02d, 0x21, 0 - .dw 0x2e40, 0xc02d, 0x2e7f, 0xc02d, 0x21, 0 - .dw 0x2ec0, 0xc02d, 0x2eff, 0xc02d, 0x21, 0 - .dw 0x2f40, 0xc02d, 0x2f7f, 0xc02d, 0x21, 0 - .dw 0x2fc0, 0xc02d, 0x2fff, 0xc02d, 0x21, 0 - .dw 0x3040, 0xc02d, 0x307f, 0xc02d, 0x21, 0 - .dw 0x30c0, 0xc02d, 0x30ff, 0xc02d, 0x21, 0 - .dw 0x3140, 0xc02d, 0x317f, 0xc02d, 0x21, 0 - .dw 0x31c0, 0xc02d, 0x31ff, 0xc02d, 0x21, 0 - .dw 0x3240, 0xc02d, 0x327f, 0xc02d, 0x21, 0 - .dw 0x32c0, 0xc02d, 0x32ff, 0xc02d, 0x21, 0 - .dw 0x3340, 0xc02d, 0x337f, 0xc02d, 0x21, 0 - .dw 0x33c0, 0xc02d, 0x33ff, 0xc02d, 0x21, 0 - .dw 0x3440, 0xc02d, 0x347f, 0xc02d, 0x21, 0 - .dw 0x34c0, 0xc02d, 0x34ff, 0xc02d, 0x21, 0 - .dw 0x3540, 0xc02d, 0x357f, 0xc02d, 0x21, 0 - .dw 0x35c0, 0xc02d, 0x35ff, 0xc02d, 0x21, 0 - .dw 0x3640, 0xc02d, 0x367f, 0xc02d, 0x21, 0 - .dw 0x36c0, 0xc02d, 0x36ff, 0xc02d, 0x21, 0 - .dw 0x3740, 0xc02d, 0x377f, 0xc02d, 0x21, 0 - .dw 0x37c0, 0xc02d, 0x37ff, 0xc02d, 0x21, 0 - .dw 0x3840, 0xc02d, 0x387f, 0xc02d, 0x21, 0 - .dw 0x38c0, 0xc02d, 0x38ff, 0xc02d, 0x21, 0 - .dw 0x3940, 0xc02d, 0x397f, 0xc02d, 0x21, 0 - .dw 0x39c0, 0xc02d, 0x3fff, 0xc02d, 0x21, 0 - .dw 0x4040, 0xc02d, 0x407f, 0xc02d, 0x21, 0 - .dw 0x40c0, 0xc02d, 0x40ff, 0xc02d, 0x21, 0 - .dw 0x4140, 0xc02d, 0x417f, 0xc02d, 0x21, 0 - .dw 0x41c0, 0xc02d, 0x41ff, 0xc02d, 0x21, 0 - .dw 0x4240, 0xc02d, 0x427f, 0xc02d, 0x21, 0 - .dw 0x42c0, 0xc02d, 0x42ff, 0xc02d, 0x21, 0 - .dw 0x4340, 0xc02d, 0x437f, 0xc02d, 0x21, 0 - .dw 0x43c0, 0xc02d, 0x43ff, 0xc02d, 0x21, 0 - .dw 0x4440, 0xc02d, 0x447f, 0xc02d, 0x21, 0 - .dw 0x44c0, 0xc02d, 0x44ff, 0xc02d, 0x21, 0 - .dw 0x4540, 0xc02d, 0x457f, 0xc02d, 0x21, 0 - .dw 0x45c0, 0xc02d, 0x45ff, 0xc02d, 0x21, 0 - .dw 0x4640, 0xc02d, 0x467f, 0xc02d, 0x21, 0 - .dw 0x46c0, 0xc02d, 0x46ff, 0xc02d, 0x21, 0 - .dw 0x4740, 0xc02d, 0x477f, 0xc02d, 0x21, 0 - .dw 0x47c0, 0xc02d, 0x47ff, 0xc02d, 0x21, 0 - .dw 0x4840, 0xc02d, 0x487f, 0xc02d, 0x21, 0 - .dw 0x48c0, 0xc02d, 0x48ff, 0xc02d, 0x21, 0 - .dw 0x4940, 0xc02d, 0x497f, 0xc02d, 0x21, 0 - .dw 0x49c0, 0xc02d, 0x49ff, 0xc02d, 0x21, 0 - .dw 0x4a40, 0xc02d, 0x4a7f, 0xc02d, 0x21, 0 - .dw 0x4ac0, 0xc02d, 0x4aff, 0xc02d, 0x21, 0 - .dw 0x4b40, 0xc02d, 0x4b7f, 0xc02d, 0x21, 0 - .dw 0x4bc0, 0xc02d, 0x4bff, 0xc02d, 0x21, 0 - .dw 0x4c40, 0xc02d, 0x4c7f, 0xc02d, 0x21, 0 - .dw 0x4cc0, 0xc02d, 0x4cff, 0xc02d, 0x21, 0 - .dw 0x4d40, 0xc02d, 0x4d7f, 0xc02d, 0x21, 0 - .dw 0x4dc0, 0xc02d, 0x4dff, 0xc02d, 0x21, 0 - .dw 0x4e40, 0xc02d, 0x4e7f, 0xc02d, 0x21, 0 - .dw 0x4ec0, 0xc02d, 0x4eff, 0xc02d, 0x21, 0 - .dw 0x4f40, 0xc02d, 0x4f7f, 0xc02d, 0x21, 0 - .dw 0x4fc0, 0xc02d, 0x4fff, 0xc02d, 0x21, 0 - .dw 0x5040, 0xc02d, 0x507f, 0xc02d, 0x21, 0 - .dw 0x50c0, 0xc02d, 0x50ff, 0xc02d, 0x21, 0 - .dw 0x5140, 0xc02d, 0x517f, 0xc02d, 0x21, 0 - .dw 0x51c0, 0xc02d, 0x51ff, 0xc02d, 0x21, 0 - .dw 0x5240, 0xc02d, 0x527f, 0xc02d, 0x21, 0 - .dw 0x52c0, 0xc02d, 0x52ff, 0xc02d, 0x21, 0 - .dw 0x5340, 0xc02d, 0x537f, 0xc02d, 0x21, 0 - .dw 0x53c0, 0xc02d, 0x53ff, 0xc02d, 0x21, 0 - .dw 0x5440, 0xc02d, 0x547f, 0xc02d, 0x21, 0 - .dw 0x54c0, 0xc02d, 0x54ff, 0xc02d, 0x21, 0 - .dw 0x5540, 0xc02d, 0x557f, 0xc02d, 0x21, 0 - .dw 0x55c0, 0xc02d, 0x55ff, 0xc02d, 0x21, 0 - .dw 0x5640, 0xc02d, 0x567f, 0xc02d, 0x21, 0 - .dw 0x56c0, 0xc02d, 0x56ff, 0xc02d, 0x21, 0 - .dw 0x5740, 0xc02d, 0x577f, 0xc02d, 0x21, 0 - .dw 0x57c0, 0xc02d, 0x57ff, 0xc02d, 0x21, 0 - .dw 0x5840, 0xc02d, 0x587f, 0xc02d, 0x21, 0 - .dw 0x58c0, 0xc02d, 0x58ff, 0xc02d, 0x21, 0 - .dw 0x5940, 0xc02d, 0x597f, 0xc02d, 0x21, 0 - .dw 0x59c0, 0xc02d, 0x5fff, 0xc02d, 0x21, 0 - .dw 0x6040, 0xc02d, 0x607f, 0xc02d, 0x21, 0 - .dw 0x60c0, 0xc02d, 0x60ff, 0xc02d, 0x21, 0 - .dw 0x6140, 0xc02d, 0x617f, 0xc02d, 0x21, 0 - .dw 0x61c0, 0xc02d, 0x61ff, 0xc02d, 0x21, 0 - .dw 0x6240, 0xc02d, 0x627f, 0xc02d, 0x21, 0 - .dw 0x62c0, 0xc02d, 0x62ff, 0xc02d, 0x21, 0 - .dw 0x6340, 0xc02d, 0x637f, 0xc02d, 0x21, 0 - .dw 0x63c0, 0xc02d, 0x63ff, 0xc02d, 0x21, 0 - .dw 0x6440, 0xc02d, 0x647f, 0xc02d, 0x21, 0 - .dw 0x64c0, 0xc02d, 0x64ff, 0xc02d, 0x21, 0 - .dw 0x6540, 0xc02d, 0x657f, 0xc02d, 0x21, 0 - .dw 0x65c0, 0xc02d, 0x65ff, 0xc02d, 0x21, 0 - .dw 0x6640, 0xc02d, 0x667f, 0xc02d, 0x21, 0 - .dw 0x66c0, 0xc02d, 0x66ff, 0xc02d, 0x21, 0 - .dw 0x6740, 0xc02d, 0x677f, 0xc02d, 0x21, 0 - .dw 0x67c0, 0xc02d, 0x67ff, 0xc02d, 0x21, 0 - .dw 0x6840, 0xc02d, 0x687f, 0xc02d, 0x21, 0 - .dw 0x68c0, 0xc02d, 0x68ff, 0xc02d, 0x21, 0 - .dw 0x6940, 0xc02d, 0x697f, 0xc02d, 0x21, 0 - .dw 0x69c0, 0xc02d, 0x69ff, 0xc02d, 0x21, 0 - .dw 0x6a40, 0xc02d, 0x6a7f, 0xc02d, 0x21, 0 - .dw 0x6ac0, 0xc02d, 0x6aff, 0xc02d, 0x21, 0 - .dw 0x6b40, 0xc02d, 0x6b7f, 0xc02d, 0x21, 0 - .dw 0x6bc0, 0xc02d, 0x6bff, 0xc02d, 0x21, 0 - .dw 0x6c40, 0xc02d, 0x6c7f, 0xc02d, 0x21, 0 - .dw 0x6cc0, 0xc02d, 0x6cff, 0xc02d, 0x21, 0 - .dw 0x6d40, 0xc02d, 0x6d7f, 0xc02d, 0x21, 0 - .dw 0x6dc0, 0xc02d, 0x6dff, 0xc02d, 0x21, 0 - .dw 0x6e40, 0xc02d, 0x6e7f, 0xc02d, 0x21, 0 - .dw 0x6ec0, 0xc02d, 0x6eff, 0xc02d, 0x21, 0 - .dw 0x6f40, 0xc02d, 0x6f7f, 0xc02d, 0x21, 0 - .dw 0x6fc0, 0xc02d, 0x6fff, 0xc02d, 0x21, 0 - .dw 0x7040, 0xc02d, 0x707f, 0xc02d, 0x21, 0 - .dw 0x70c0, 0xc02d, 0x70ff, 0xc02d, 0x21, 0 - .dw 0x7140, 0xc02d, 0x717f, 0xc02d, 0x21, 0 - .dw 0x71c0, 0xc02d, 0x71ff, 0xc02d, 0x21, 0 - .dw 0x7240, 0xc02d, 0x727f, 0xc02d, 0x21, 0 - .dw 0x72c0, 0xc02d, 0x72ff, 0xc02d, 0x21, 0 - .dw 0x7340, 0xc02d, 0x737f, 0xc02d, 0x21, 0 - .dw 0x73c0, 0xc02d, 0x73ff, 0xc02d, 0x21, 0 - .dw 0x7440, 0xc02d, 0x747f, 0xc02d, 0x21, 0 - .dw 0x74c0, 0xc02d, 0x74ff, 0xc02d, 0x21, 0 - .dw 0x7540, 0xc02d, 0x757f, 0xc02d, 0x21, 0 - .dw 0x75c0, 0xc02d, 0x75ff, 0xc02d, 0x21, 0 - .dw 0x7640, 0xc02d, 0x767f, 0xc02d, 0x21, 0 - .dw 0x76c0, 0xc02d, 0x76ff, 0xc02d, 0x21, 0 - .dw 0x7740, 0xc02d, 0x777f, 0xc02d, 0x21, 0 - .dw 0x77c0, 0xc02d, 0x77ff, 0xc02d, 0x21, 0 - .dw 0x7840, 0xc02d, 0x787f, 0xc02d, 0x21, 0 - .dw 0x78c0, 0xc02d, 0x78ff, 0xc02d, 0x21, 0 - .dw 0x7940, 0xc02d, 0x797f, 0xc02d, 0x21, 0 - .dw 0x79c0, 0xc02d, 0x7fff, 0xc02d, 0x21, 0 - .dw 0x8040, 0xc02d, 0x807f, 0xc02d, 0x21, 0 - .dw 0x80c0, 0xc02d, 0x80ff, 0xc02d, 0x21, 0 - .dw 0x8140, 0xc02d, 0x817f, 0xc02d, 0x21, 0 - .dw 0x81c0, 0xc02d, 0x81ff, 0xc02d, 0x21, 0 - .dw 0x8240, 0xc02d, 0x827f, 0xc02d, 0x21, 0 - .dw 0x82c0, 0xc02d, 0x82ff, 0xc02d, 0x21, 0 - .dw 0x8340, 0xc02d, 0x837f, 0xc02d, 0x21, 0 - .dw 0x83c0, 0xc02d, 0x83ff, 0xc02d, 0x21, 0 - .dw 0x8440, 0xc02d, 0x847f, 0xc02d, 0x21, 0 - .dw 0x84c0, 0xc02d, 0x84ff, 0xc02d, 0x21, 0 - .dw 0x8540, 0xc02d, 0x857f, 0xc02d, 0x21, 0 - .dw 0x85c0, 0xc02d, 0x85ff, 0xc02d, 0x21, 0 - .dw 0x8640, 0xc02d, 0x867f, 0xc02d, 0x21, 0 - .dw 0x86c0, 0xc02d, 0x86ff, 0xc02d, 0x21, 0 - .dw 0x8740, 0xc02d, 0x877f, 0xc02d, 0x21, 0 - .dw 0x87c0, 0xc02d, 0x87ff, 0xc02d, 0x21, 0 - .dw 0x8840, 0xc02d, 0x887f, 0xc02d, 0x21, 0 - .dw 0x88c0, 0xc02d, 0x88ff, 0xc02d, 0x21, 0 - .dw 0x8940, 0xc02d, 0x897f, 0xc02d, 0x21, 0 - .dw 0x89c0, 0xc02d, 0x89ff, 0xc02d, 0x21, 0 - .dw 0x8a40, 0xc02d, 0x8a7f, 0xc02d, 0x21, 0 - .dw 0x8ac0, 0xc02d, 0x8aff, 0xc02d, 0x21, 0 - .dw 0x8b40, 0xc02d, 0x8b7f, 0xc02d, 0x21, 0 - .dw 0x8bc0, 0xc02d, 0x8bff, 0xc02d, 0x21, 0 - .dw 0x8c40, 0xc02d, 0x8c7f, 0xc02d, 0x21, 0 - .dw 0x8cc0, 0xc02d, 0x8cff, 0xc02d, 0x21, 0 - .dw 0x8d40, 0xc02d, 0x8d7f, 0xc02d, 0x21, 0 - .dw 0x8dc0, 0xc02d, 0x8dff, 0xc02d, 0x21, 0 - .dw 0x8e40, 0xc02d, 0x8e7f, 0xc02d, 0x21, 0 - .dw 0x8ec0, 0xc02d, 0x8eff, 0xc02d, 0x21, 0 - .dw 0x8f40, 0xc02d, 0x8f7f, 0xc02d, 0x21, 0 - .dw 0x8fc0, 0xc02d, 0x8fff, 0xc02d, 0x21, 0 - .dw 0x9040, 0xc02d, 0x907f, 0xc02d, 0x21, 0 - .dw 0x90c0, 0xc02d, 0x90ff, 0xc02d, 0x21, 0 - .dw 0x9140, 0xc02d, 0x917f, 0xc02d, 0x21, 0 - .dw 0x91c0, 0xc02d, 0x91ff, 0xc02d, 0x21, 0 - .dw 0x9240, 0xc02d, 0x927f, 0xc02d, 0x21, 0 - .dw 0x92c0, 0xc02d, 0x92ff, 0xc02d, 0x21, 0 - .dw 0x9340, 0xc02d, 0x937f, 0xc02d, 0x21, 0 - .dw 0x93c0, 0xc02d, 0x93ff, 0xc02d, 0x21, 0 - .dw 0x9440, 0xc02d, 0x947f, 0xc02d, 0x21, 0 - .dw 0x94c0, 0xc02d, 0x94ff, 0xc02d, 0x21, 0 - .dw 0x9540, 0xc02d, 0x957f, 0xc02d, 0x21, 0 - .dw 0x95c0, 0xc02d, 0x95ff, 0xc02d, 0x21, 0 - .dw 0x9640, 0xc02d, 0x967f, 0xc02d, 0x21, 0 - .dw 0x96c0, 0xc02d, 0x96ff, 0xc02d, 0x21, 0 - .dw 0x9740, 0xc02d, 0x977f, 0xc02d, 0x21, 0 - .dw 0x97c0, 0xc02d, 0x97ff, 0xc02d, 0x21, 0 - .dw 0x9840, 0xc02d, 0x987f, 0xc02d, 0x21, 0 - .dw 0x98c0, 0xc02d, 0x98ff, 0xc02d, 0x21, 0 - .dw 0x9940, 0xc02d, 0x997f, 0xc02d, 0x21, 0 - .dw 0x99c0, 0xc02d, 0x9fff, 0xc02d, 0x21, 0 - .dw 0xa040, 0xc02d, 0xa07f, 0xc02d, 0x21, 0 - .dw 0xa0c0, 0xc02d, 0xa0ff, 0xc02d, 0x21, 0 - .dw 0xa140, 0xc02d, 0xa17f, 0xc02d, 0x21, 0 - .dw 0xa1c0, 0xc02d, 0xa1ff, 0xc02d, 0x21, 0 - .dw 0xa240, 0xc02d, 0xa27f, 0xc02d, 0x21, 0 - .dw 0xa2c0, 0xc02d, 0xa2ff, 0xc02d, 0x21, 0 - .dw 0xa340, 0xc02d, 0xa37f, 0xc02d, 0x21, 0 - .dw 0xa3c0, 0xc02d, 0xa3ff, 0xc02d, 0x21, 0 - .dw 0xa440, 0xc02d, 0xa47f, 0xc02d, 0x21, 0 - .dw 0xa4c0, 0xc02d, 0xa4ff, 0xc02d, 0x21, 0 - .dw 0xa540, 0xc02d, 0xa57f, 0xc02d, 0x21, 0 - .dw 0xa5c0, 0xc02d, 0xa5ff, 0xc02d, 0x21, 0 - .dw 0xa640, 0xc02d, 0xa67f, 0xc02d, 0x21, 0 - .dw 0xa6c0, 0xc02d, 0xa6ff, 0xc02d, 0x21, 0 - .dw 0xa740, 0xc02d, 0xa77f, 0xc02d, 0x21, 0 - .dw 0xa7c0, 0xc02d, 0xa7ff, 0xc02d, 0x21, 0 - .dw 0xa840, 0xc02d, 0xa87f, 0xc02d, 0x21, 0 - .dw 0xa8c0, 0xc02d, 0xa8ff, 0xc02d, 0x21, 0 - .dw 0xa940, 0xc02d, 0xa97f, 0xc02d, 0x21, 0 - .dw 0xa9c0, 0xc02d, 0xa9ff, 0xc02d, 0x21, 0 - .dw 0xaa40, 0xc02d, 0xaa7f, 0xc02d, 0x21, 0 - .dw 0xaac0, 0xc02d, 0xaaff, 0xc02d, 0x21, 0 - .dw 0xab40, 0xc02d, 0xab7f, 0xc02d, 0x21, 0 - .dw 0xabc0, 0xc02d, 0xabff, 0xc02d, 0x21, 0 - .dw 0xac40, 0xc02d, 0xac7f, 0xc02d, 0x21, 0 - .dw 0xacc0, 0xc02d, 0xacff, 0xc02d, 0x21, 0 - .dw 0xad40, 0xc02d, 0xad7f, 0xc02d, 0x21, 0 - .dw 0xadc0, 0xc02d, 0xadff, 0xc02d, 0x21, 0 - .dw 0xae40, 0xc02d, 0xae7f, 0xc02d, 0x21, 0 - .dw 0xaec0, 0xc02d, 0xaeff, 0xc02d, 0x21, 0 - .dw 0xaf40, 0xc02d, 0xaf7f, 0xc02d, 0x21, 0 - .dw 0xafc0, 0xc02d, 0xafff, 0xc02d, 0x21, 0 - .dw 0xb040, 0xc02d, 0xb07f, 0xc02d, 0x21, 0 - .dw 0xb0c0, 0xc02d, 0xb0ff, 0xc02d, 0x21, 0 - .dw 0xb140, 0xc02d, 0xb17f, 0xc02d, 0x21, 0 - .dw 0xb1c0, 0xc02d, 0xb1ff, 0xc02d, 0x21, 0 - .dw 0xb240, 0xc02d, 0xb27f, 0xc02d, 0x21, 0 - .dw 0xb2c0, 0xc02d, 0xb2ff, 0xc02d, 0x21, 0 - .dw 0xb340, 0xc02d, 0xb37f, 0xc02d, 0x21, 0 - .dw 0xb3c0, 0xc02d, 0xb3ff, 0xc02d, 0x21, 0 - .dw 0xb440, 0xc02d, 0xb47f, 0xc02d, 0x21, 0 - .dw 0xb4c0, 0xc02d, 0xb4ff, 0xc02d, 0x21, 0 - .dw 0xb540, 0xc02d, 0xb57f, 0xc02d, 0x21, 0 - .dw 0xb5c0, 0xc02d, 0xb5ff, 0xc02d, 0x21, 0 - .dw 0xb640, 0xc02d, 0xb67f, 0xc02d, 0x21, 0 - .dw 0xb6c0, 0xc02d, 0xb6ff, 0xc02d, 0x21, 0 - .dw 0xb740, 0xc02d, 0xb77f, 0xc02d, 0x21, 0 - .dw 0xb7c0, 0xc02d, 0xb7ff, 0xc02d, 0x21, 0 - .dw 0xb840, 0xc02d, 0xb87f, 0xc02d, 0x21, 0 - .dw 0xb8c0, 0xc02d, 0xb8ff, 0xc02d, 0x21, 0 - .dw 0xb940, 0xc02d, 0xb97f, 0xc02d, 0x21, 0 - .dw 0xb9c0, 0xc02d, 0xbfff, 0xc02d, 0x21, 0 - .dw 0xc040, 0xc02d, 0xc07f, 0xc02d, 0x21, 0 - .dw 0xc0c0, 0xc02d, 0xc0ff, 0xc02d, 0x21, 0 - .dw 0xc140, 0xc02d, 0xc17f, 0xc02d, 0x21, 0 - .dw 0xc1c0, 0xc02d, 0xc1ff, 0xc02d, 0x21, 0 - .dw 0xc240, 0xc02d, 0xc27f, 0xc02d, 0x21, 0 - .dw 0xc2c0, 0xc02d, 0xc2ff, 0xc02d, 0x21, 0 - .dw 0xc340, 0xc02d, 0xc37f, 0xc02d, 0x21, 0 - .dw 0xc3c0, 0xc02d, 0xc3ff, 0xc02d, 0x21, 0 - .dw 0xc440, 0xc02d, 0xc47f, 0xc02d, 0x21, 0 - .dw 0xc4c0, 0xc02d, 0xc4ff, 0xc02d, 0x21, 0 - .dw 0xc540, 0xc02d, 0xc57f, 0xc02d, 0x21, 0 - .dw 0xc5c0, 0xc02d, 0xc5ff, 0xc02d, 0x21, 0 - .dw 0xc640, 0xc02d, 0xc67f, 0xc02d, 0x21, 0 - .dw 0xc6c0, 0xc02d, 0xc6ff, 0xc02d, 0x21, 0 - .dw 0xc740, 0xc02d, 0xc77f, 0xc02d, 0x21, 0 - .dw 0xc7c0, 0xc02d, 0xc7ff, 0xc02d, 0x21, 0 - .dw 0xc840, 0xc02d, 0xc87f, 0xc02d, 0x21, 0 - .dw 0xc8c0, 0xc02d, 0xc8ff, 0xc02d, 0x21, 0 - .dw 0xc940, 0xc02d, 0xc97f, 0xc02d, 0x21, 0 - .dw 0xc9c0, 0xc02d, 0xc9ff, 0xc02d, 0x21, 0 - .dw 0xca40, 0xc02d, 0xca7f, 0xc02d, 0x21, 0 - .dw 0xcac0, 0xc02d, 0xcaff, 0xc02d, 0x21, 0 - .dw 0xcb40, 0xc02d, 0xcb7f, 0xc02d, 0x21, 0 - .dw 0xcbc0, 0xc02d, 0xcbff, 0xc02d, 0x21, 0 - .dw 0xcc40, 0xc02d, 0xcc7f, 0xc02d, 0x21, 0 - .dw 0xccc0, 0xc02d, 0xccff, 0xc02d, 0x21, 0 - .dw 0xcd40, 0xc02d, 0xcd7f, 0xc02d, 0x21, 0 - .dw 0xcdc0, 0xc02d, 0xcdff, 0xc02d, 0x21, 0 - .dw 0xce40, 0xc02d, 0xce7f, 0xc02d, 0x21, 0 - .dw 0xcec0, 0xc02d, 0xceff, 0xc02d, 0x21, 0 - .dw 0xcf40, 0xc02d, 0xcf7f, 0xc02d, 0x21, 0 - .dw 0xcfc0, 0xc02d, 0xcfff, 0xc02d, 0x21, 0 - .dw 0xd040, 0xc02d, 0xd07f, 0xc02d, 0x21, 0 - .dw 0xd0c0, 0xc02d, 0xd0ff, 0xc02d, 0x21, 0 - .dw 0xd140, 0xc02d, 0xd17f, 0xc02d, 0x21, 0 - .dw 0xd1c0, 0xc02d, 0xd1ff, 0xc02d, 0x21, 0 - .dw 0xd240, 0xc02d, 0xd27f, 0xc02d, 0x21, 0 - .dw 0xd2c0, 0xc02d, 0xd2ff, 0xc02d, 0x21, 0 - .dw 0xd340, 0xc02d, 0xd37f, 0xc02d, 0x21, 0 - .dw 0xd3c0, 0xc02d, 0xd3ff, 0xc02d, 0x21, 0 - .dw 0xd440, 0xc02d, 0xd47f, 0xc02d, 0x21, 0 - .dw 0xd4c0, 0xc02d, 0xd4ff, 0xc02d, 0x21, 0 - .dw 0xd540, 0xc02d, 0xd57f, 0xc02d, 0x21, 0 - .dw 0xd5c0, 0xc02d, 0xd5ff, 0xc02d, 0x21, 0 - .dw 0xd640, 0xc02d, 0xd67f, 0xc02d, 0x21, 0 - .dw 0xd6c0, 0xc02d, 0xd6ff, 0xc02d, 0x21, 0 - .dw 0xd740, 0xc02d, 0xd77f, 0xc02d, 0x21, 0 - .dw 0xd7c0, 0xc02d, 0xd7ff, 0xc02d, 0x21, 0 - .dw 0xd840, 0xc02d, 0xd87f, 0xc02d, 0x21, 0 - .dw 0xd8c0, 0xc02d, 0xd8ff, 0xc02d, 0x21, 0 - .dw 0xd940, 0xc02d, 0xd97f, 0xc02d, 0x21, 0 - .dw 0xd9c0, 0xc02d, 0xdfff, 0xc02d, 0x21, 0 - .dw 0xe040, 0xc02d, 0xe07f, 0xc02d, 0x21, 0 - .dw 0xe0c0, 0xc02d, 0xe0ff, 0xc02d, 0x21, 0 - .dw 0xe140, 0xc02d, 0xe17f, 0xc02d, 0x21, 0 - .dw 0xe1c0, 0xc02d, 0xe1ff, 0xc02d, 0x21, 0 - .dw 0xe240, 0xc02d, 0xe27f, 0xc02d, 0x21, 0 - .dw 0xe2c0, 0xc02d, 0xe2ff, 0xc02d, 0x21, 0 - .dw 0xe340, 0xc02d, 0xe37f, 0xc02d, 0x21, 0 - .dw 0xe3c0, 0xc02d, 0xe3ff, 0xc02d, 0x21, 0 - .dw 0xe440, 0xc02d, 0xe47f, 0xc02d, 0x21, 0 - .dw 0xe4c0, 0xc02d, 0xe4ff, 0xc02d, 0x21, 0 - .dw 0xe540, 0xc02d, 0xe57f, 0xc02d, 0x21, 0 - .dw 0xe5c0, 0xc02d, 0xe5ff, 0xc02d, 0x21, 0 - .dw 0xe640, 0xc02d, 0xe67f, 0xc02d, 0x21, 0 - .dw 0xe6c0, 0xc02d, 0xe6ff, 0xc02d, 0x21, 0 - .dw 0xe740, 0xc02d, 0xe77f, 0xc02d, 0x21, 0 - .dw 0xe7c0, 0xc02d, 0xe7ff, 0xc02d, 0x21, 0 - .dw 0xe840, 0xc02d, 0xe87f, 0xc02d, 0x21, 0 - .dw 0xe8c0, 0xc02d, 0xe8ff, 0xc02d, 0x21, 0 - .dw 0xe940, 0xc02d, 0xe97f, 0xc02d, 0x21, 0 - .dw 0xe9c0, 0xc02d, 0xe9ff, 0xc02d, 0x21, 0 - .dw 0xea40, 0xc02d, 0xea7f, 0xc02d, 0x21, 0 - .dw 0xeac0, 0xc02d, 0xeaff, 0xc02d, 0x21, 0 - .dw 0xeb40, 0xc02d, 0xeb7f, 0xc02d, 0x21, 0 - .dw 0xebc0, 0xc02d, 0xebff, 0xc02d, 0x21, 0 - .dw 0xec40, 0xc02d, 0xec7f, 0xc02d, 0x21, 0 - .dw 0xecc0, 0xc02d, 0xecff, 0xc02d, 0x21, 0 - .dw 0xed40, 0xc02d, 0xed7f, 0xc02d, 0x21, 0 - .dw 0xedc0, 0xc02d, 0xedff, 0xc02d, 0x21, 0 - .dw 0xee40, 0xc02d, 0xee7f, 0xc02d, 0x21, 0 - .dw 0xeec0, 0xc02d, 0xeeff, 0xc02d, 0x21, 0 - .dw 0xef40, 0xc02d, 0xef7f, 0xc02d, 0x21, 0 - .dw 0xefc0, 0xc02d, 0xefff, 0xc02d, 0x21, 0 - .dw 0xf040, 0xc02d, 0xf07f, 0xc02d, 0x21, 0 - .dw 0xf0c0, 0xc02d, 0xf0ff, 0xc02d, 0x21, 0 - .dw 0xf140, 0xc02d, 0xf17f, 0xc02d, 0x21, 0 - .dw 0xf1c0, 0xc02d, 0xf1ff, 0xc02d, 0x21, 0 - .dw 0xf240, 0xc02d, 0xf27f, 0xc02d, 0x21, 0 - .dw 0xf2c0, 0xc02d, 0xf2ff, 0xc02d, 0x21, 0 - .dw 0xf340, 0xc02d, 0xf37f, 0xc02d, 0x21, 0 - .dw 0xf3c0, 0xc02d, 0xf3ff, 0xc02d, 0x21, 0 - .dw 0xf440, 0xc02d, 0xf47f, 0xc02d, 0x21, 0 - .dw 0xf4c0, 0xc02d, 0xf4ff, 0xc02d, 0x21, 0 - .dw 0xf540, 0xc02d, 0xf57f, 0xc02d, 0x21, 0 - .dw 0xf5c0, 0xc02d, 0xf5ff, 0xc02d, 0x21, 0 - .dw 0xf640, 0xc02d, 0xf67f, 0xc02d, 0x21, 0 - .dw 0xf6c0, 0xc02d, 0xf6ff, 0xc02d, 0x21, 0 - .dw 0xf740, 0xc02d, 0xf77f, 0xc02d, 0x21, 0 - .dw 0xf7c0, 0xc02d, 0xf7ff, 0xc02d, 0x21, 0 - .dw 0xf840, 0xc02d, 0xf87f, 0xc02d, 0x21, 0 - .dw 0xf8c0, 0xc02d, 0xf8ff, 0xc02d, 0x21, 0 - .dw 0xf940, 0xc02d, 0xf97f, 0xc02d, 0x21, 0 - .dw 0xf9c0, 0xc02d, 0xffff, 0xc02d, 0x21, 0 - .dw 0x0040, 0xc02e, 0x007f, 0xc02e, 0x21, 0 - .dw 0x00c0, 0xc02e, 0x00ff, 0xc02e, 0x21, 0 - .dw 0x0140, 0xc02e, 0x017f, 0xc02e, 0x21, 0 - .dw 0x01c0, 0xc02e, 0x01ff, 0xc02e, 0x21, 0 - .dw 0x0240, 0xc02e, 0x027f, 0xc02e, 0x21, 0 - .dw 0x02c0, 0xc02e, 0x02ff, 0xc02e, 0x21, 0 - .dw 0x0340, 0xc02e, 0x037f, 0xc02e, 0x21, 0 - .dw 0x03c0, 0xc02e, 0x03ff, 0xc02e, 0x21, 0 - .dw 0x0440, 0xc02e, 0x047f, 0xc02e, 0x21, 0 - .dw 0x04c0, 0xc02e, 0x04ff, 0xc02e, 0x21, 0 - .dw 0x0540, 0xc02e, 0x057f, 0xc02e, 0x21, 0 - .dw 0x05c0, 0xc02e, 0x05ff, 0xc02e, 0x21, 0 - .dw 0x0640, 0xc02e, 0x067f, 0xc02e, 0x21, 0 - .dw 0x06c0, 0xc02e, 0x06ff, 0xc02e, 0x21, 0 - .dw 0x0740, 0xc02e, 0x077f, 0xc02e, 0x21, 0 - .dw 0x07c0, 0xc02e, 0x07ff, 0xc02e, 0x21, 0 - .dw 0x0840, 0xc02e, 0x087f, 0xc02e, 0x21, 0 - .dw 0x08c0, 0xc02e, 0x08ff, 0xc02e, 0x21, 0 - .dw 0x0940, 0xc02e, 0x097f, 0xc02e, 0x21, 0 - .dw 0x09c0, 0xc02e, 0x09ff, 0xc02e, 0x21, 0 - .dw 0x0a40, 0xc02e, 0x0a7f, 0xc02e, 0x21, 0 - .dw 0x0ac0, 0xc02e, 0x0aff, 0xc02e, 0x21, 0 - .dw 0x0b40, 0xc02e, 0x0b7f, 0xc02e, 0x21, 0 - .dw 0x0bc0, 0xc02e, 0x0bff, 0xc02e, 0x21, 0 - .dw 0x0c40, 0xc02e, 0x0c7f, 0xc02e, 0x21, 0 - .dw 0x0cc0, 0xc02e, 0x0cff, 0xc02e, 0x21, 0 - .dw 0x0d40, 0xc02e, 0x0d7f, 0xc02e, 0x21, 0 - .dw 0x0dc0, 0xc02e, 0x0dff, 0xc02e, 0x21, 0 - .dw 0x0e40, 0xc02e, 0x0e7f, 0xc02e, 0x21, 0 - .dw 0x0ec0, 0xc02e, 0x0eff, 0xc02e, 0x21, 0 - .dw 0x0f40, 0xc02e, 0x0f7f, 0xc02e, 0x21, 0 - .dw 0x0fc0, 0xc02e, 0x0fff, 0xc02e, 0x21, 0 - .dw 0x1040, 0xc02e, 0x107f, 0xc02e, 0x21, 0 - .dw 0x10c0, 0xc02e, 0x10ff, 0xc02e, 0x21, 0 - .dw 0x1140, 0xc02e, 0x117f, 0xc02e, 0x21, 0 - .dw 0x11c0, 0xc02e, 0x11ff, 0xc02e, 0x21, 0 - .dw 0x1240, 0xc02e, 0x127f, 0xc02e, 0x21, 0 - .dw 0x12c0, 0xc02e, 0x12ff, 0xc02e, 0x21, 0 - .dw 0x1340, 0xc02e, 0x137f, 0xc02e, 0x21, 0 - .dw 0x13c0, 0xc02e, 0x13ff, 0xc02e, 0x21, 0 - .dw 0x1440, 0xc02e, 0x147f, 0xc02e, 0x21, 0 - .dw 0x14c0, 0xc02e, 0x14ff, 0xc02e, 0x21, 0 - .dw 0x1540, 0xc02e, 0x157f, 0xc02e, 0x21, 0 - .dw 0x15c0, 0xc02e, 0x15ff, 0xc02e, 0x21, 0 - .dw 0x1640, 0xc02e, 0x167f, 0xc02e, 0x21, 0 - .dw 0x16c0, 0xc02e, 0x16ff, 0xc02e, 0x21, 0 - .dw 0x1740, 0xc02e, 0x177f, 0xc02e, 0x21, 0 - .dw 0x17c0, 0xc02e, 0x17ff, 0xc02e, 0x21, 0 - .dw 0x1840, 0xc02e, 0x187f, 0xc02e, 0x21, 0 - .dw 0x18c0, 0xc02e, 0x18ff, 0xc02e, 0x21, 0 - .dw 0x1940, 0xc02e, 0x197f, 0xc02e, 0x21, 0 - .dw 0x19c0, 0xc02e, 0x1fff, 0xc02e, 0x21, 0 - .dw 0x2040, 0xc02e, 0x207f, 0xc02e, 0x21, 0 - .dw 0x20c0, 0xc02e, 0x20ff, 0xc02e, 0x21, 0 - .dw 0x2140, 0xc02e, 0x217f, 0xc02e, 0x21, 0 - .dw 0x21c0, 0xc02e, 0x21ff, 0xc02e, 0x21, 0 - .dw 0x2240, 0xc02e, 0x227f, 0xc02e, 0x21, 0 - .dw 0x22c0, 0xc02e, 0x22ff, 0xc02e, 0x21, 0 - .dw 0x2340, 0xc02e, 0x237f, 0xc02e, 0x21, 0 - .dw 0x23c0, 0xc02e, 0x23ff, 0xc02e, 0x21, 0 - .dw 0x2440, 0xc02e, 0x247f, 0xc02e, 0x21, 0 - .dw 0x24c0, 0xc02e, 0x24ff, 0xc02e, 0x21, 0 - .dw 0x2540, 0xc02e, 0x257f, 0xc02e, 0x21, 0 - .dw 0x25c0, 0xc02e, 0x25ff, 0xc02e, 0x21, 0 - .dw 0x2640, 0xc02e, 0x267f, 0xc02e, 0x21, 0 - .dw 0x26c0, 0xc02e, 0x26ff, 0xc02e, 0x21, 0 - .dw 0x2740, 0xc02e, 0x277f, 0xc02e, 0x21, 0 - .dw 0x27c0, 0xc02e, 0x27ff, 0xc02e, 0x21, 0 - .dw 0x2840, 0xc02e, 0x287f, 0xc02e, 0x21, 0 - .dw 0x28c0, 0xc02e, 0x28ff, 0xc02e, 0x21, 0 - .dw 0x2940, 0xc02e, 0x297f, 0xc02e, 0x21, 0 - .dw 0x29c0, 0xc02e, 0x29ff, 0xc02e, 0x21, 0 - .dw 0x2a40, 0xc02e, 0x2a7f, 0xc02e, 0x21, 0 - .dw 0x2ac0, 0xc02e, 0x2aff, 0xc02e, 0x21, 0 - .dw 0x2b40, 0xc02e, 0x2b7f, 0xc02e, 0x21, 0 - .dw 0x2bc0, 0xc02e, 0x2bff, 0xc02e, 0x21, 0 - .dw 0x2c40, 0xc02e, 0x2c7f, 0xc02e, 0x21, 0 - .dw 0x2cc0, 0xc02e, 0x2cff, 0xc02e, 0x21, 0 - .dw 0x2d40, 0xc02e, 0x2d7f, 0xc02e, 0x21, 0 - .dw 0x2dc0, 0xc02e, 0x2dff, 0xc02e, 0x21, 0 - .dw 0x2e40, 0xc02e, 0x2e7f, 0xc02e, 0x21, 0 - .dw 0x2ec0, 0xc02e, 0x2eff, 0xc02e, 0x21, 0 - .dw 0x2f40, 0xc02e, 0x2f7f, 0xc02e, 0x21, 0 - .dw 0x2fc0, 0xc02e, 0x2fff, 0xc02e, 0x21, 0 - .dw 0x3040, 0xc02e, 0x307f, 0xc02e, 0x21, 0 - .dw 0x30c0, 0xc02e, 0x30ff, 0xc02e, 0x21, 0 - .dw 0x3140, 0xc02e, 0x317f, 0xc02e, 0x21, 0 - .dw 0x31c0, 0xc02e, 0x31ff, 0xc02e, 0x21, 0 - .dw 0x3240, 0xc02e, 0x327f, 0xc02e, 0x21, 0 - .dw 0x32c0, 0xc02e, 0x32ff, 0xc02e, 0x21, 0 - .dw 0x3340, 0xc02e, 0x337f, 0xc02e, 0x21, 0 - .dw 0x33c0, 0xc02e, 0x33ff, 0xc02e, 0x21, 0 - .dw 0x3440, 0xc02e, 0x347f, 0xc02e, 0x21, 0 - .dw 0x34c0, 0xc02e, 0x34ff, 0xc02e, 0x21, 0 - .dw 0x3540, 0xc02e, 0x357f, 0xc02e, 0x21, 0 - .dw 0x35c0, 0xc02e, 0x35ff, 0xc02e, 0x21, 0 - .dw 0x3640, 0xc02e, 0x367f, 0xc02e, 0x21, 0 - .dw 0x36c0, 0xc02e, 0x36ff, 0xc02e, 0x21, 0 - .dw 0x3740, 0xc02e, 0x377f, 0xc02e, 0x21, 0 - .dw 0x37c0, 0xc02e, 0x37ff, 0xc02e, 0x21, 0 - .dw 0x3840, 0xc02e, 0x387f, 0xc02e, 0x21, 0 - .dw 0x38c0, 0xc02e, 0x38ff, 0xc02e, 0x21, 0 - .dw 0x3940, 0xc02e, 0x397f, 0xc02e, 0x21, 0 - .dw 0x39c0, 0xc02e, 0x3fff, 0xc02e, 0x21, 0 - .dw 0x4040, 0xc02e, 0x407f, 0xc02e, 0x21, 0 - .dw 0x40c0, 0xc02e, 0x40ff, 0xc02e, 0x21, 0 - .dw 0x4140, 0xc02e, 0x417f, 0xc02e, 0x21, 0 - .dw 0x41c0, 0xc02e, 0x41ff, 0xc02e, 0x21, 0 - .dw 0x4240, 0xc02e, 0x427f, 0xc02e, 0x21, 0 - .dw 0x42c0, 0xc02e, 0x42ff, 0xc02e, 0x21, 0 - .dw 0x4340, 0xc02e, 0x437f, 0xc02e, 0x21, 0 - .dw 0x43c0, 0xc02e, 0x43ff, 0xc02e, 0x21, 0 - .dw 0x4440, 0xc02e, 0x447f, 0xc02e, 0x21, 0 - .dw 0x44c0, 0xc02e, 0x44ff, 0xc02e, 0x21, 0 - .dw 0x4540, 0xc02e, 0x457f, 0xc02e, 0x21, 0 - .dw 0x45c0, 0xc02e, 0x45ff, 0xc02e, 0x21, 0 - .dw 0x4640, 0xc02e, 0x467f, 0xc02e, 0x21, 0 - .dw 0x46c0, 0xc02e, 0x46ff, 0xc02e, 0x21, 0 - .dw 0x4740, 0xc02e, 0x477f, 0xc02e, 0x21, 0 - .dw 0x47c0, 0xc02e, 0x47ff, 0xc02e, 0x21, 0 - .dw 0x4840, 0xc02e, 0x487f, 0xc02e, 0x21, 0 - .dw 0x48c0, 0xc02e, 0x48ff, 0xc02e, 0x21, 0 - .dw 0x4940, 0xc02e, 0x497f, 0xc02e, 0x21, 0 - .dw 0x49c0, 0xc02e, 0x49ff, 0xc02e, 0x21, 0 - .dw 0x4a40, 0xc02e, 0x4a7f, 0xc02e, 0x21, 0 - .dw 0x4ac0, 0xc02e, 0x4aff, 0xc02e, 0x21, 0 - .dw 0x4b40, 0xc02e, 0x4b7f, 0xc02e, 0x21, 0 - .dw 0x4bc0, 0xc02e, 0x4bff, 0xc02e, 0x21, 0 - .dw 0x4c40, 0xc02e, 0x4c7f, 0xc02e, 0x21, 0 - .dw 0x4cc0, 0xc02e, 0x4cff, 0xc02e, 0x21, 0 - .dw 0x4d40, 0xc02e, 0x4d7f, 0xc02e, 0x21, 0 - .dw 0x4dc0, 0xc02e, 0x4dff, 0xc02e, 0x21, 0 - .dw 0x4e40, 0xc02e, 0x4e7f, 0xc02e, 0x21, 0 - .dw 0x4ec0, 0xc02e, 0x4eff, 0xc02e, 0x21, 0 - .dw 0x4f40, 0xc02e, 0x4f7f, 0xc02e, 0x21, 0 - .dw 0x4fc0, 0xc02e, 0x4fff, 0xc02e, 0x21, 0 - .dw 0x5040, 0xc02e, 0x507f, 0xc02e, 0x21, 0 - .dw 0x50c0, 0xc02e, 0x50ff, 0xc02e, 0x21, 0 - .dw 0x5140, 0xc02e, 0x517f, 0xc02e, 0x21, 0 - .dw 0x51c0, 0xc02e, 0x51ff, 0xc02e, 0x21, 0 - .dw 0x5240, 0xc02e, 0x527f, 0xc02e, 0x21, 0 - .dw 0x52c0, 0xc02e, 0x52ff, 0xc02e, 0x21, 0 - .dw 0x5340, 0xc02e, 0x537f, 0xc02e, 0x21, 0 - .dw 0x53c0, 0xc02e, 0x53ff, 0xc02e, 0x21, 0 - .dw 0x5440, 0xc02e, 0x547f, 0xc02e, 0x21, 0 - .dw 0x54c0, 0xc02e, 0x54ff, 0xc02e, 0x21, 0 - .dw 0x5540, 0xc02e, 0x557f, 0xc02e, 0x21, 0 - .dw 0x55c0, 0xc02e, 0x55ff, 0xc02e, 0x21, 0 - .dw 0x5640, 0xc02e, 0x567f, 0xc02e, 0x21, 0 - .dw 0x56c0, 0xc02e, 0x56ff, 0xc02e, 0x21, 0 - .dw 0x5740, 0xc02e, 0x577f, 0xc02e, 0x21, 0 - .dw 0x57c0, 0xc02e, 0x57ff, 0xc02e, 0x21, 0 - .dw 0x5840, 0xc02e, 0x587f, 0xc02e, 0x21, 0 - .dw 0x58c0, 0xc02e, 0x58ff, 0xc02e, 0x21, 0 - .dw 0x5940, 0xc02e, 0x597f, 0xc02e, 0x21, 0 - .dw 0x59c0, 0xc02e, 0x5fff, 0xc02e, 0x21, 0 - .dw 0x6040, 0xc02e, 0x607f, 0xc02e, 0x21, 0 - .dw 0x60c0, 0xc02e, 0x60ff, 0xc02e, 0x21, 0 - .dw 0x6140, 0xc02e, 0x617f, 0xc02e, 0x21, 0 - .dw 0x61c0, 0xc02e, 0x61ff, 0xc02e, 0x21, 0 - .dw 0x6240, 0xc02e, 0x627f, 0xc02e, 0x21, 0 - .dw 0x62c0, 0xc02e, 0x62ff, 0xc02e, 0x21, 0 - .dw 0x6340, 0xc02e, 0x637f, 0xc02e, 0x21, 0 - .dw 0x63c0, 0xc02e, 0x63ff, 0xc02e, 0x21, 0 - .dw 0x6440, 0xc02e, 0x647f, 0xc02e, 0x21, 0 - .dw 0x64c0, 0xc02e, 0x64ff, 0xc02e, 0x21, 0 - .dw 0x6540, 0xc02e, 0x657f, 0xc02e, 0x21, 0 - .dw 0x65c0, 0xc02e, 0x65ff, 0xc02e, 0x21, 0 - .dw 0x6640, 0xc02e, 0x667f, 0xc02e, 0x21, 0 - .dw 0x66c0, 0xc02e, 0x66ff, 0xc02e, 0x21, 0 - .dw 0x6740, 0xc02e, 0x677f, 0xc02e, 0x21, 0 - .dw 0x67c0, 0xc02e, 0x67ff, 0xc02e, 0x21, 0 - .dw 0x6840, 0xc02e, 0x687f, 0xc02e, 0x21, 0 - .dw 0x68c0, 0xc02e, 0x68ff, 0xc02e, 0x21, 0 - .dw 0x6940, 0xc02e, 0x697f, 0xc02e, 0x21, 0 - .dw 0x69c0, 0xc02e, 0x69ff, 0xc02e, 0x21, 0 - .dw 0x6a40, 0xc02e, 0x6a7f, 0xc02e, 0x21, 0 - .dw 0x6ac0, 0xc02e, 0x6aff, 0xc02e, 0x21, 0 - .dw 0x6b40, 0xc02e, 0x6b7f, 0xc02e, 0x21, 0 - .dw 0x6bc0, 0xc02e, 0x6bff, 0xc02e, 0x21, 0 - .dw 0x6c40, 0xc02e, 0x6c7f, 0xc02e, 0x21, 0 - .dw 0x6cc0, 0xc02e, 0x6cff, 0xc02e, 0x21, 0 - .dw 0x6d40, 0xc02e, 0x6d7f, 0xc02e, 0x21, 0 - .dw 0x6dc0, 0xc02e, 0x6dff, 0xc02e, 0x21, 0 - .dw 0x6e40, 0xc02e, 0x6e7f, 0xc02e, 0x21, 0 - .dw 0x6ec0, 0xc02e, 0x6eff, 0xc02e, 0x21, 0 - .dw 0x6f40, 0xc02e, 0x6f7f, 0xc02e, 0x21, 0 - .dw 0x6fc0, 0xc02e, 0x6fff, 0xc02e, 0x21, 0 - .dw 0x7040, 0xc02e, 0x707f, 0xc02e, 0x21, 0 - .dw 0x70c0, 0xc02e, 0x70ff, 0xc02e, 0x21, 0 - .dw 0x7140, 0xc02e, 0x717f, 0xc02e, 0x21, 0 - .dw 0x71c0, 0xc02e, 0x71ff, 0xc02e, 0x21, 0 - .dw 0x7240, 0xc02e, 0x727f, 0xc02e, 0x21, 0 - .dw 0x72c0, 0xc02e, 0x72ff, 0xc02e, 0x21, 0 - .dw 0x7340, 0xc02e, 0x737f, 0xc02e, 0x21, 0 - .dw 0x73c0, 0xc02e, 0x73ff, 0xc02e, 0x21, 0 - .dw 0x7440, 0xc02e, 0x747f, 0xc02e, 0x21, 0 - .dw 0x74c0, 0xc02e, 0x74ff, 0xc02e, 0x21, 0 - .dw 0x7540, 0xc02e, 0x757f, 0xc02e, 0x21, 0 - .dw 0x75c0, 0xc02e, 0x75ff, 0xc02e, 0x21, 0 - .dw 0x7640, 0xc02e, 0x767f, 0xc02e, 0x21, 0 - .dw 0x76c0, 0xc02e, 0x76ff, 0xc02e, 0x21, 0 - .dw 0x7740, 0xc02e, 0x777f, 0xc02e, 0x21, 0 - .dw 0x77c0, 0xc02e, 0x77ff, 0xc02e, 0x21, 0 - .dw 0x7840, 0xc02e, 0x787f, 0xc02e, 0x21, 0 - .dw 0x78c0, 0xc02e, 0x78ff, 0xc02e, 0x21, 0 - .dw 0x7940, 0xc02e, 0x797f, 0xc02e, 0x21, 0 - .dw 0x79c0, 0xc02e, 0x7fff, 0xc02e, 0x21, 0 - .dw 0x8040, 0xc02e, 0x807f, 0xc02e, 0x21, 0 - .dw 0x80c0, 0xc02e, 0x80ff, 0xc02e, 0x21, 0 - .dw 0x8140, 0xc02e, 0x817f, 0xc02e, 0x21, 0 - .dw 0x81c0, 0xc02e, 0x81ff, 0xc02e, 0x21, 0 - .dw 0x8240, 0xc02e, 0x827f, 0xc02e, 0x21, 0 - .dw 0x82c0, 0xc02e, 0x82ff, 0xc02e, 0x21, 0 - .dw 0x8340, 0xc02e, 0x837f, 0xc02e, 0x21, 0 - .dw 0x83c0, 0xc02e, 0x83ff, 0xc02e, 0x21, 0 - .dw 0x8440, 0xc02e, 0x847f, 0xc02e, 0x21, 0 - .dw 0x84c0, 0xc02e, 0x84ff, 0xc02e, 0x21, 0 - .dw 0x8540, 0xc02e, 0x857f, 0xc02e, 0x21, 0 - .dw 0x85c0, 0xc02e, 0x85ff, 0xc02e, 0x21, 0 - .dw 0x8640, 0xc02e, 0x867f, 0xc02e, 0x21, 0 - .dw 0x86c0, 0xc02e, 0x86ff, 0xc02e, 0x21, 0 - .dw 0x8740, 0xc02e, 0x877f, 0xc02e, 0x21, 0 - .dw 0x87c0, 0xc02e, 0x87ff, 0xc02e, 0x21, 0 - .dw 0x8840, 0xc02e, 0x887f, 0xc02e, 0x21, 0 - .dw 0x88c0, 0xc02e, 0x88ff, 0xc02e, 0x21, 0 - .dw 0x8940, 0xc02e, 0x897f, 0xc02e, 0x21, 0 - .dw 0x89c0, 0xc02e, 0x89ff, 0xc02e, 0x21, 0 - .dw 0x8a40, 0xc02e, 0x8a7f, 0xc02e, 0x21, 0 - .dw 0x8ac0, 0xc02e, 0x8aff, 0xc02e, 0x21, 0 - .dw 0x8b40, 0xc02e, 0x8b7f, 0xc02e, 0x21, 0 - .dw 0x8bc0, 0xc02e, 0x8bff, 0xc02e, 0x21, 0 - .dw 0x8c40, 0xc02e, 0x8c7f, 0xc02e, 0x21, 0 - .dw 0x8cc0, 0xc02e, 0x8cff, 0xc02e, 0x21, 0 - .dw 0x8d40, 0xc02e, 0x8d7f, 0xc02e, 0x21, 0 - .dw 0x8dc0, 0xc02e, 0x8dff, 0xc02e, 0x21, 0 - .dw 0x8e40, 0xc02e, 0x8e7f, 0xc02e, 0x21, 0 - .dw 0x8ec0, 0xc02e, 0x8eff, 0xc02e, 0x21, 0 - .dw 0x8f40, 0xc02e, 0x8f7f, 0xc02e, 0x21, 0 - .dw 0x8fc0, 0xc02e, 0x8fff, 0xc02e, 0x21, 0 - .dw 0x9040, 0xc02e, 0x907f, 0xc02e, 0x21, 0 - .dw 0x90c0, 0xc02e, 0x90ff, 0xc02e, 0x21, 0 - .dw 0x9140, 0xc02e, 0x917f, 0xc02e, 0x21, 0 - .dw 0x91c0, 0xc02e, 0x91ff, 0xc02e, 0x21, 0 - .dw 0x9240, 0xc02e, 0x927f, 0xc02e, 0x21, 0 - .dw 0x92c0, 0xc02e, 0x92ff, 0xc02e, 0x21, 0 - .dw 0x9340, 0xc02e, 0x937f, 0xc02e, 0x21, 0 - .dw 0x93c0, 0xc02e, 0x93ff, 0xc02e, 0x21, 0 - .dw 0x9440, 0xc02e, 0x947f, 0xc02e, 0x21, 0 - .dw 0x94c0, 0xc02e, 0x94ff, 0xc02e, 0x21, 0 - .dw 0x9540, 0xc02e, 0x957f, 0xc02e, 0x21, 0 - .dw 0x95c0, 0xc02e, 0x95ff, 0xc02e, 0x21, 0 - .dw 0x9640, 0xc02e, 0x967f, 0xc02e, 0x21, 0 - .dw 0x96c0, 0xc02e, 0x96ff, 0xc02e, 0x21, 0 - .dw 0x9740, 0xc02e, 0x977f, 0xc02e, 0x21, 0 - .dw 0x97c0, 0xc02e, 0x97ff, 0xc02e, 0x21, 0 - .dw 0x9840, 0xc02e, 0x987f, 0xc02e, 0x21, 0 - .dw 0x98c0, 0xc02e, 0x98ff, 0xc02e, 0x21, 0 - .dw 0x9940, 0xc02e, 0x997f, 0xc02e, 0x21, 0 - .dw 0x99c0, 0xc02e, 0x9fff, 0xc02e, 0x21, 0 - .dw 0xa040, 0xc02e, 0xa07f, 0xc02e, 0x21, 0 - .dw 0xa0c0, 0xc02e, 0xa0ff, 0xc02e, 0x21, 0 - .dw 0xa140, 0xc02e, 0xa17f, 0xc02e, 0x21, 0 - .dw 0xa1c0, 0xc02e, 0xa1ff, 0xc02e, 0x21, 0 - .dw 0xa240, 0xc02e, 0xa27f, 0xc02e, 0x21, 0 - .dw 0xa2c0, 0xc02e, 0xa2ff, 0xc02e, 0x21, 0 - .dw 0xa340, 0xc02e, 0xa37f, 0xc02e, 0x21, 0 - .dw 0xa3c0, 0xc02e, 0xa3ff, 0xc02e, 0x21, 0 - .dw 0xa440, 0xc02e, 0xa47f, 0xc02e, 0x21, 0 - .dw 0xa4c0, 0xc02e, 0xa4ff, 0xc02e, 0x21, 0 - .dw 0xa540, 0xc02e, 0xa57f, 0xc02e, 0x21, 0 - .dw 0xa5c0, 0xc02e, 0xa5ff, 0xc02e, 0x21, 0 - .dw 0xa640, 0xc02e, 0xa67f, 0xc02e, 0x21, 0 - .dw 0xa6c0, 0xc02e, 0xa6ff, 0xc02e, 0x21, 0 - .dw 0xa740, 0xc02e, 0xa77f, 0xc02e, 0x21, 0 - .dw 0xa7c0, 0xc02e, 0xa7ff, 0xc02e, 0x21, 0 - .dw 0xa840, 0xc02e, 0xa87f, 0xc02e, 0x21, 0 - .dw 0xa8c0, 0xc02e, 0xa8ff, 0xc02e, 0x21, 0 - .dw 0xa940, 0xc02e, 0xa97f, 0xc02e, 0x21, 0 - .dw 0xa9c0, 0xc02e, 0xa9ff, 0xc02e, 0x21, 0 - .dw 0xaa40, 0xc02e, 0xaa7f, 0xc02e, 0x21, 0 - .dw 0xaac0, 0xc02e, 0xaaff, 0xc02e, 0x21, 0 - .dw 0xab40, 0xc02e, 0xab7f, 0xc02e, 0x21, 0 - .dw 0xabc0, 0xc02e, 0xabff, 0xc02e, 0x21, 0 - .dw 0xac40, 0xc02e, 0xac7f, 0xc02e, 0x21, 0 - .dw 0xacc0, 0xc02e, 0xacff, 0xc02e, 0x21, 0 - .dw 0xad40, 0xc02e, 0xad7f, 0xc02e, 0x21, 0 - .dw 0xadc0, 0xc02e, 0xadff, 0xc02e, 0x21, 0 - .dw 0xae40, 0xc02e, 0xae7f, 0xc02e, 0x21, 0 - .dw 0xaec0, 0xc02e, 0xaeff, 0xc02e, 0x21, 0 - .dw 0xaf40, 0xc02e, 0xaf7f, 0xc02e, 0x21, 0 - .dw 0xafc0, 0xc02e, 0xafff, 0xc02e, 0x21, 0 - .dw 0xb040, 0xc02e, 0xb07f, 0xc02e, 0x21, 0 - .dw 0xb0c0, 0xc02e, 0xb0ff, 0xc02e, 0x21, 0 - .dw 0xb140, 0xc02e, 0xb17f, 0xc02e, 0x21, 0 - .dw 0xb1c0, 0xc02e, 0xb1ff, 0xc02e, 0x21, 0 - .dw 0xb240, 0xc02e, 0xb27f, 0xc02e, 0x21, 0 - .dw 0xb2c0, 0xc02e, 0xb2ff, 0xc02e, 0x21, 0 - .dw 0xb340, 0xc02e, 0xb37f, 0xc02e, 0x21, 0 - .dw 0xb3c0, 0xc02e, 0xb3ff, 0xc02e, 0x21, 0 - .dw 0xb440, 0xc02e, 0xb47f, 0xc02e, 0x21, 0 - .dw 0xb4c0, 0xc02e, 0xb4ff, 0xc02e, 0x21, 0 - .dw 0xb540, 0xc02e, 0xb57f, 0xc02e, 0x21, 0 - .dw 0xb5c0, 0xc02e, 0xb5ff, 0xc02e, 0x21, 0 - .dw 0xb640, 0xc02e, 0xb67f, 0xc02e, 0x21, 0 - .dw 0xb6c0, 0xc02e, 0xb6ff, 0xc02e, 0x21, 0 - .dw 0xb740, 0xc02e, 0xb77f, 0xc02e, 0x21, 0 - .dw 0xb7c0, 0xc02e, 0xb7ff, 0xc02e, 0x21, 0 - .dw 0xb840, 0xc02e, 0xb87f, 0xc02e, 0x21, 0 - .dw 0xb8c0, 0xc02e, 0xb8ff, 0xc02e, 0x21, 0 - .dw 0xb940, 0xc02e, 0xb97f, 0xc02e, 0x21, 0 - .dw 0xb9c0, 0xc02e, 0xbfff, 0xc02e, 0x21, 0 - .dw 0xc040, 0xc02e, 0xc07f, 0xc02e, 0x21, 0 - .dw 0xc0c0, 0xc02e, 0xc0ff, 0xc02e, 0x21, 0 - .dw 0xc140, 0xc02e, 0xc17f, 0xc02e, 0x21, 0 - .dw 0xc1c0, 0xc02e, 0xc1ff, 0xc02e, 0x21, 0 - .dw 0xc240, 0xc02e, 0xc27f, 0xc02e, 0x21, 0 - .dw 0xc2c0, 0xc02e, 0xc2ff, 0xc02e, 0x21, 0 - .dw 0xc340, 0xc02e, 0xc37f, 0xc02e, 0x21, 0 - .dw 0xc3c0, 0xc02e, 0xc3ff, 0xc02e, 0x21, 0 - .dw 0xc440, 0xc02e, 0xc47f, 0xc02e, 0x21, 0 - .dw 0xc4c0, 0xc02e, 0xc4ff, 0xc02e, 0x21, 0 - .dw 0xc540, 0xc02e, 0xc57f, 0xc02e, 0x21, 0 - .dw 0xc5c0, 0xc02e, 0xc5ff, 0xc02e, 0x21, 0 - .dw 0xc640, 0xc02e, 0xc67f, 0xc02e, 0x21, 0 - .dw 0xc6c0, 0xc02e, 0xc6ff, 0xc02e, 0x21, 0 - .dw 0xc740, 0xc02e, 0xc77f, 0xc02e, 0x21, 0 - .dw 0xc7c0, 0xc02e, 0xc7ff, 0xc02e, 0x21, 0 - .dw 0xc840, 0xc02e, 0xc87f, 0xc02e, 0x21, 0 - .dw 0xc8c0, 0xc02e, 0xc8ff, 0xc02e, 0x21, 0 - .dw 0xc940, 0xc02e, 0xc97f, 0xc02e, 0x21, 0 - .dw 0xc9c0, 0xc02e, 0xc9ff, 0xc02e, 0x21, 0 - .dw 0xca40, 0xc02e, 0xca7f, 0xc02e, 0x21, 0 - .dw 0xcac0, 0xc02e, 0xcaff, 0xc02e, 0x21, 0 - .dw 0xcb40, 0xc02e, 0xcb7f, 0xc02e, 0x21, 0 - .dw 0xcbc0, 0xc02e, 0xcbff, 0xc02e, 0x21, 0 - .dw 0xcc40, 0xc02e, 0xcc7f, 0xc02e, 0x21, 0 - .dw 0xccc0, 0xc02e, 0xccff, 0xc02e, 0x21, 0 - .dw 0xcd40, 0xc02e, 0xcd7f, 0xc02e, 0x21, 0 - .dw 0xcdc0, 0xc02e, 0xcdff, 0xc02e, 0x21, 0 - .dw 0xce40, 0xc02e, 0xce7f, 0xc02e, 0x21, 0 - .dw 0xcec0, 0xc02e, 0xceff, 0xc02e, 0x21, 0 - .dw 0xcf40, 0xc02e, 0xcf7f, 0xc02e, 0x21, 0 - .dw 0xcfc0, 0xc02e, 0xcfff, 0xc02e, 0x21, 0 - .dw 0xd040, 0xc02e, 0xd07f, 0xc02e, 0x21, 0 - .dw 0xd0c0, 0xc02e, 0xd0ff, 0xc02e, 0x21, 0 - .dw 0xd140, 0xc02e, 0xd17f, 0xc02e, 0x21, 0 - .dw 0xd1c0, 0xc02e, 0xd1ff, 0xc02e, 0x21, 0 - .dw 0xd240, 0xc02e, 0xd27f, 0xc02e, 0x21, 0 - .dw 0xd2c0, 0xc02e, 0xd2ff, 0xc02e, 0x21, 0 - .dw 0xd340, 0xc02e, 0xd37f, 0xc02e, 0x21, 0 - .dw 0xd3c0, 0xc02e, 0xd3ff, 0xc02e, 0x21, 0 - .dw 0xd440, 0xc02e, 0xd47f, 0xc02e, 0x21, 0 - .dw 0xd4c0, 0xc02e, 0xd4ff, 0xc02e, 0x21, 0 - .dw 0xd540, 0xc02e, 0xd57f, 0xc02e, 0x21, 0 - .dw 0xd5c0, 0xc02e, 0xd5ff, 0xc02e, 0x21, 0 - .dw 0xd640, 0xc02e, 0xd67f, 0xc02e, 0x21, 0 - .dw 0xd6c0, 0xc02e, 0xd6ff, 0xc02e, 0x21, 0 - .dw 0xd740, 0xc02e, 0xd77f, 0xc02e, 0x21, 0 - .dw 0xd7c0, 0xc02e, 0xd7ff, 0xc02e, 0x21, 0 - .dw 0xd840, 0xc02e, 0xd87f, 0xc02e, 0x21, 0 - .dw 0xd8c0, 0xc02e, 0xd8ff, 0xc02e, 0x21, 0 - .dw 0xd940, 0xc02e, 0xd97f, 0xc02e, 0x21, 0 - .dw 0xd9c0, 0xc02e, 0xdfff, 0xc02e, 0x21, 0 - .dw 0xe040, 0xc02e, 0xe07f, 0xc02e, 0x21, 0 - .dw 0xe0c0, 0xc02e, 0xe0ff, 0xc02e, 0x21, 0 - .dw 0xe140, 0xc02e, 0xe17f, 0xc02e, 0x21, 0 - .dw 0xe1c0, 0xc02e, 0xe1ff, 0xc02e, 0x21, 0 - .dw 0xe240, 0xc02e, 0xe27f, 0xc02e, 0x21, 0 - .dw 0xe2c0, 0xc02e, 0xe2ff, 0xc02e, 0x21, 0 - .dw 0xe340, 0xc02e, 0xe37f, 0xc02e, 0x21, 0 - .dw 0xe3c0, 0xc02e, 0xe3ff, 0xc02e, 0x21, 0 - .dw 0xe440, 0xc02e, 0xe47f, 0xc02e, 0x21, 0 - .dw 0xe4c0, 0xc02e, 0xe4ff, 0xc02e, 0x21, 0 - .dw 0xe540, 0xc02e, 0xe57f, 0xc02e, 0x21, 0 - .dw 0xe5c0, 0xc02e, 0xe5ff, 0xc02e, 0x21, 0 - .dw 0xe640, 0xc02e, 0xe67f, 0xc02e, 0x21, 0 - .dw 0xe6c0, 0xc02e, 0xe6ff, 0xc02e, 0x21, 0 - .dw 0xe740, 0xc02e, 0xe77f, 0xc02e, 0x21, 0 - .dw 0xe7c0, 0xc02e, 0xe7ff, 0xc02e, 0x21, 0 - .dw 0xe840, 0xc02e, 0xe87f, 0xc02e, 0x21, 0 - .dw 0xe8c0, 0xc02e, 0xe8ff, 0xc02e, 0x21, 0 - .dw 0xe940, 0xc02e, 0xe97f, 0xc02e, 0x21, 0 - .dw 0xe9c0, 0xc02e, 0xe9ff, 0xc02e, 0x21, 0 - .dw 0xea40, 0xc02e, 0xea7f, 0xc02e, 0x21, 0 - .dw 0xeac0, 0xc02e, 0xeaff, 0xc02e, 0x21, 0 - .dw 0xeb40, 0xc02e, 0xeb7f, 0xc02e, 0x21, 0 - .dw 0xebc0, 0xc02e, 0xebff, 0xc02e, 0x21, 0 - .dw 0xec40, 0xc02e, 0xec7f, 0xc02e, 0x21, 0 - .dw 0xecc0, 0xc02e, 0xecff, 0xc02e, 0x21, 0 - .dw 0xed40, 0xc02e, 0xed7f, 0xc02e, 0x21, 0 - .dw 0xedc0, 0xc02e, 0xedff, 0xc02e, 0x21, 0 - .dw 0xee40, 0xc02e, 0xee7f, 0xc02e, 0x21, 0 - .dw 0xeec0, 0xc02e, 0xeeff, 0xc02e, 0x21, 0 - .dw 0xef40, 0xc02e, 0xef7f, 0xc02e, 0x21, 0 - .dw 0xefc0, 0xc02e, 0xefff, 0xc02e, 0x21, 0 - .dw 0xf040, 0xc02e, 0xf07f, 0xc02e, 0x21, 0 - .dw 0xf0c0, 0xc02e, 0xf0ff, 0xc02e, 0x21, 0 - .dw 0xf140, 0xc02e, 0xf17f, 0xc02e, 0x21, 0 - .dw 0xf1c0, 0xc02e, 0xf1ff, 0xc02e, 0x21, 0 - .dw 0xf240, 0xc02e, 0xf27f, 0xc02e, 0x21, 0 - .dw 0xf2c0, 0xc02e, 0xf2ff, 0xc02e, 0x21, 0 - .dw 0xf340, 0xc02e, 0xf37f, 0xc02e, 0x21, 0 - .dw 0xf3c0, 0xc02e, 0xf3ff, 0xc02e, 0x21, 0 - .dw 0xf440, 0xc02e, 0xf47f, 0xc02e, 0x21, 0 - .dw 0xf4c0, 0xc02e, 0xf4ff, 0xc02e, 0x21, 0 - .dw 0xf540, 0xc02e, 0xf57f, 0xc02e, 0x21, 0 - .dw 0xf5c0, 0xc02e, 0xf5ff, 0xc02e, 0x21, 0 - .dw 0xf640, 0xc02e, 0xf67f, 0xc02e, 0x21, 0 - .dw 0xf6c0, 0xc02e, 0xf6ff, 0xc02e, 0x21, 0 - .dw 0xf740, 0xc02e, 0xf77f, 0xc02e, 0x21, 0 - .dw 0xf7c0, 0xc02e, 0xf7ff, 0xc02e, 0x21, 0 - .dw 0xf840, 0xc02e, 0xf87f, 0xc02e, 0x21, 0 - .dw 0xf8c0, 0xc02e, 0xf8ff, 0xc02e, 0x21, 0 - .dw 0xf940, 0xc02e, 0xf97f, 0xc02e, 0x21, 0 - .dw 0xf9c0, 0xc02e, 0xffff, 0xc02e, 0x21, 0 - .dw 0x0040, 0xc02f, 0x007f, 0xc02f, 0x21, 0 - .dw 0x00c0, 0xc02f, 0x00ff, 0xc02f, 0x21, 0 - .dw 0x0140, 0xc02f, 0x017f, 0xc02f, 0x21, 0 - .dw 0x01c0, 0xc02f, 0x01ff, 0xc02f, 0x21, 0 - .dw 0x0240, 0xc02f, 0x027f, 0xc02f, 0x21, 0 - .dw 0x02c0, 0xc02f, 0x02ff, 0xc02f, 0x21, 0 - .dw 0x0340, 0xc02f, 0x037f, 0xc02f, 0x21, 0 - .dw 0x03c0, 0xc02f, 0x03ff, 0xc02f, 0x21, 0 - .dw 0x0440, 0xc02f, 0x047f, 0xc02f, 0x21, 0 - .dw 0x04c0, 0xc02f, 0x04ff, 0xc02f, 0x21, 0 - .dw 0x0540, 0xc02f, 0x057f, 0xc02f, 0x21, 0 - .dw 0x05c0, 0xc02f, 0x05ff, 0xc02f, 0x21, 0 - .dw 0x0640, 0xc02f, 0x067f, 0xc02f, 0x21, 0 - .dw 0x06c0, 0xc02f, 0x06ff, 0xc02f, 0x21, 0 - .dw 0x0740, 0xc02f, 0x077f, 0xc02f, 0x21, 0 - .dw 0x07c0, 0xc02f, 0x07ff, 0xc02f, 0x21, 0 - .dw 0x0840, 0xc02f, 0x087f, 0xc02f, 0x21, 0 - .dw 0x08c0, 0xc02f, 0x08ff, 0xc02f, 0x21, 0 - .dw 0x0940, 0xc02f, 0x097f, 0xc02f, 0x21, 0 - .dw 0x09c0, 0xc02f, 0x09ff, 0xc02f, 0x21, 0 - .dw 0x0a40, 0xc02f, 0x0a7f, 0xc02f, 0x21, 0 - .dw 0x0ac0, 0xc02f, 0x0aff, 0xc02f, 0x21, 0 - .dw 0x0b40, 0xc02f, 0x0b7f, 0xc02f, 0x21, 0 - .dw 0x0bc0, 0xc02f, 0x0bff, 0xc02f, 0x21, 0 - .dw 0x0c40, 0xc02f, 0x0c7f, 0xc02f, 0x21, 0 - .dw 0x0cc0, 0xc02f, 0x0cff, 0xc02f, 0x21, 0 - .dw 0x0d40, 0xc02f, 0x0d7f, 0xc02f, 0x21, 0 - .dw 0x0dc0, 0xc02f, 0x0dff, 0xc02f, 0x21, 0 - .dw 0x0e40, 0xc02f, 0x0e7f, 0xc02f, 0x21, 0 - .dw 0x0ec0, 0xc02f, 0x0eff, 0xc02f, 0x21, 0 - .dw 0x0f40, 0xc02f, 0x0f7f, 0xc02f, 0x21, 0 - .dw 0x0fc0, 0xc02f, 0x0fff, 0xc02f, 0x21, 0 - .dw 0x1040, 0xc02f, 0x107f, 0xc02f, 0x21, 0 - .dw 0x10c0, 0xc02f, 0x10ff, 0xc02f, 0x21, 0 - .dw 0x1140, 0xc02f, 0x117f, 0xc02f, 0x21, 0 - .dw 0x11c0, 0xc02f, 0x11ff, 0xc02f, 0x21, 0 - .dw 0x1240, 0xc02f, 0x127f, 0xc02f, 0x21, 0 - .dw 0x12c0, 0xc02f, 0x12ff, 0xc02f, 0x21, 0 - .dw 0x1340, 0xc02f, 0x137f, 0xc02f, 0x21, 0 - .dw 0x13c0, 0xc02f, 0x13ff, 0xc02f, 0x21, 0 - .dw 0x1440, 0xc02f, 0x147f, 0xc02f, 0x21, 0 - .dw 0x14c0, 0xc02f, 0x14ff, 0xc02f, 0x21, 0 - .dw 0x1540, 0xc02f, 0x157f, 0xc02f, 0x21, 0 - .dw 0x15c0, 0xc02f, 0x15ff, 0xc02f, 0x21, 0 - .dw 0x1640, 0xc02f, 0x167f, 0xc02f, 0x21, 0 - .dw 0x16c0, 0xc02f, 0x16ff, 0xc02f, 0x21, 0 - .dw 0x1740, 0xc02f, 0x177f, 0xc02f, 0x21, 0 - .dw 0x17c0, 0xc02f, 0x17ff, 0xc02f, 0x21, 0 - .dw 0x1840, 0xc02f, 0x187f, 0xc02f, 0x21, 0 - .dw 0x18c0, 0xc02f, 0x18ff, 0xc02f, 0x21, 0 - .dw 0x1940, 0xc02f, 0x197f, 0xc02f, 0x21, 0 - .dw 0x19c0, 0xc02f, 0x1fff, 0xc02f, 0x21, 0 - .dw 0x2040, 0xc02f, 0x207f, 0xc02f, 0x21, 0 - .dw 0x20c0, 0xc02f, 0x20ff, 0xc02f, 0x21, 0 - .dw 0x2140, 0xc02f, 0x217f, 0xc02f, 0x21, 0 - .dw 0x21c0, 0xc02f, 0x21ff, 0xc02f, 0x21, 0 - .dw 0x2240, 0xc02f, 0x227f, 0xc02f, 0x21, 0 - .dw 0x22c0, 0xc02f, 0x22ff, 0xc02f, 0x21, 0 - .dw 0x2340, 0xc02f, 0x237f, 0xc02f, 0x21, 0 - .dw 0x23c0, 0xc02f, 0x23ff, 0xc02f, 0x21, 0 - .dw 0x2440, 0xc02f, 0x247f, 0xc02f, 0x21, 0 - .dw 0x24c0, 0xc02f, 0x24ff, 0xc02f, 0x21, 0 - .dw 0x2540, 0xc02f, 0x257f, 0xc02f, 0x21, 0 - .dw 0x25c0, 0xc02f, 0x25ff, 0xc02f, 0x21, 0 - .dw 0x2640, 0xc02f, 0x267f, 0xc02f, 0x21, 0 - .dw 0x26c0, 0xc02f, 0x26ff, 0xc02f, 0x21, 0 - .dw 0x2740, 0xc02f, 0x277f, 0xc02f, 0x21, 0 - .dw 0x27c0, 0xc02f, 0x27ff, 0xc02f, 0x21, 0 - .dw 0x2840, 0xc02f, 0x287f, 0xc02f, 0x21, 0 - .dw 0x28c0, 0xc02f, 0x28ff, 0xc02f, 0x21, 0 - .dw 0x2940, 0xc02f, 0x297f, 0xc02f, 0x21, 0 - .dw 0x29c0, 0xc02f, 0x29ff, 0xc02f, 0x21, 0 - .dw 0x2a40, 0xc02f, 0x2a7f, 0xc02f, 0x21, 0 - .dw 0x2ac0, 0xc02f, 0x2aff, 0xc02f, 0x21, 0 - .dw 0x2b40, 0xc02f, 0x2b7f, 0xc02f, 0x21, 0 - .dw 0x2bc0, 0xc02f, 0x2bff, 0xc02f, 0x21, 0 - .dw 0x2c40, 0xc02f, 0x2c7f, 0xc02f, 0x21, 0 - .dw 0x2cc0, 0xc02f, 0x2cff, 0xc02f, 0x21, 0 - .dw 0x2d40, 0xc02f, 0x2d7f, 0xc02f, 0x21, 0 - .dw 0x2dc0, 0xc02f, 0x2dff, 0xc02f, 0x21, 0 - .dw 0x2e40, 0xc02f, 0x2e7f, 0xc02f, 0x21, 0 - .dw 0x2ec0, 0xc02f, 0x2eff, 0xc02f, 0x21, 0 - .dw 0x2f40, 0xc02f, 0x2f7f, 0xc02f, 0x21, 0 - .dw 0x2fc0, 0xc02f, 0x2fff, 0xc02f, 0x21, 0 - .dw 0x3040, 0xc02f, 0x307f, 0xc02f, 0x21, 0 - .dw 0x30c0, 0xc02f, 0x30ff, 0xc02f, 0x21, 0 - .dw 0x3140, 0xc02f, 0x317f, 0xc02f, 0x21, 0 - .dw 0x31c0, 0xc02f, 0x31ff, 0xc02f, 0x21, 0 - .dw 0x3240, 0xc02f, 0x327f, 0xc02f, 0x21, 0 - .dw 0x32c0, 0xc02f, 0x32ff, 0xc02f, 0x21, 0 - .dw 0x3340, 0xc02f, 0x337f, 0xc02f, 0x21, 0 - .dw 0x33c0, 0xc02f, 0x33ff, 0xc02f, 0x21, 0 - .dw 0x3440, 0xc02f, 0x347f, 0xc02f, 0x21, 0 - .dw 0x34c0, 0xc02f, 0x34ff, 0xc02f, 0x21, 0 - .dw 0x3540, 0xc02f, 0x357f, 0xc02f, 0x21, 0 - .dw 0x35c0, 0xc02f, 0x35ff, 0xc02f, 0x21, 0 - .dw 0x3640, 0xc02f, 0x367f, 0xc02f, 0x21, 0 - .dw 0x36c0, 0xc02f, 0x36ff, 0xc02f, 0x21, 0 - .dw 0x3740, 0xc02f, 0x377f, 0xc02f, 0x21, 0 - .dw 0x37c0, 0xc02f, 0x37ff, 0xc02f, 0x21, 0 - .dw 0x3840, 0xc02f, 0x387f, 0xc02f, 0x21, 0 - .dw 0x38c0, 0xc02f, 0x38ff, 0xc02f, 0x21, 0 - .dw 0x3940, 0xc02f, 0x397f, 0xc02f, 0x21, 0 - .dw 0x39c0, 0xc02f, 0x1fff, 0xc030, 0x21, 0 - .dw 0x3a00, 0xc030, 0x5fff, 0xc030, 0x21, 0 - .dw 0x7a00, 0xc030, 0x9fff, 0xc030, 0x21, 0 - .dw 0xba00, 0xc030, 0xdfff, 0xc030, 0x21, 0 - .dw 0xfa00, 0xc030, 0x1fff, 0xc031, 0x21, 0 - .dw 0x3a00, 0xc031, 0x5fff, 0xc031, 0x21, 0 - .dw 0x7a00, 0xc031, 0x9fff, 0xc031, 0x21, 0 - .dw 0xba00, 0xc031, 0xdfff, 0xc031, 0x21, 0 - .dw 0xfa00, 0xc031, 0x1fff, 0xc032, 0x21, 0 - .dw 0x3a00, 0xc032, 0x5fff, 0xc032, 0x21, 0 - .dw 0x7a00, 0xc032, 0x9fff, 0xc032, 0x21, 0 - .dw 0xba00, 0xc032, 0xdfff, 0xc032, 0x21, 0 - .dw 0xfa00, 0xc032, 0xffff, 0xc033, 0x21, 0 - .dw 0x1a00, 0xc034, 0x1fff, 0xc034, 0x21, 0 - .dw 0x3a00, 0xc034, 0x3fff, 0xc034, 0x21, 0 - .dw 0x5a00, 0xc034, 0x5fff, 0xc034, 0x21, 0 - .dw 0x7a00, 0xc034, 0x7fff, 0xc034, 0x21, 0 - .dw 0x9a00, 0xc034, 0x9fff, 0xc034, 0x21, 0 - .dw 0xba00, 0xc034, 0xbfff, 0xc034, 0x21, 0 - .dw 0xda00, 0xc034, 0xdfff, 0xc034, 0x21, 0 - .dw 0xfa00, 0xc034, 0xffff, 0xc034, 0x21, 0 - .dw 0x1a00, 0xc035, 0x1fff, 0xc035, 0x21, 0 - .dw 0x3a00, 0xc035, 0x3fff, 0xc035, 0x21, 0 - .dw 0x5a00, 0xc035, 0x5fff, 0xc035, 0x21, 0 - .dw 0x7a00, 0xc035, 0x7fff, 0xc035, 0x21, 0 - .dw 0x9a00, 0xc035, 0x9fff, 0xc035, 0x21, 0 - .dw 0xba00, 0xc035, 0xbfff, 0xc035, 0x21, 0 - .dw 0xda00, 0xc035, 0xdfff, 0xc035, 0x21, 0 - .dw 0xfa00, 0xc035, 0xffff, 0xc035, 0x21, 0 - .dw 0x1a00, 0xc036, 0x1fff, 0xc036, 0x21, 0 - .dw 0x3a00, 0xc036, 0x3fff, 0xc036, 0x21, 0 - .dw 0x5a00, 0xc036, 0x5fff, 0xc036, 0x21, 0 - .dw 0x7a00, 0xc036, 0x7fff, 0xc036, 0x21, 0 - .dw 0x9a00, 0xc036, 0x9fff, 0xc036, 0x21, 0 - .dw 0xba00, 0xc036, 0xbfff, 0xc036, 0x21, 0 - .dw 0xda00, 0xc036, 0xdfff, 0xc036, 0x21, 0 - .dw 0xfa00, 0xc036, 0xffff, 0xc036, 0x21, 0 - .dw 0x1a00, 0xc037, 0x1fff, 0xc037, 0x21, 0 - .dw 0x3a00, 0xc037, 0x1fff, 0xc038, 0x21, 0 - .dw 0x2040, 0xc038, 0x207f, 0xc038, 0x21, 0 - .dw 0x20c0, 0xc038, 0x20ff, 0xc038, 0x21, 0 - .dw 0x2140, 0xc038, 0x217f, 0xc038, 0x21, 0 - .dw 0x21c0, 0xc038, 0x21ff, 0xc038, 0x21, 0 - .dw 0x2240, 0xc038, 0x227f, 0xc038, 0x21, 0 - .dw 0x22c0, 0xc038, 0x22ff, 0xc038, 0x21, 0 - .dw 0x2340, 0xc038, 0x237f, 0xc038, 0x21, 0 - .dw 0x23c0, 0xc038, 0x23ff, 0xc038, 0x21, 0 - .dw 0x2440, 0xc038, 0x247f, 0xc038, 0x21, 0 - .dw 0x24c0, 0xc038, 0x24ff, 0xc038, 0x21, 0 - .dw 0x2540, 0xc038, 0x257f, 0xc038, 0x21, 0 - .dw 0x25c0, 0xc038, 0x25ff, 0xc038, 0x21, 0 - .dw 0x2640, 0xc038, 0x267f, 0xc038, 0x21, 0 - .dw 0x26c0, 0xc038, 0x26ff, 0xc038, 0x21, 0 - .dw 0x2740, 0xc038, 0x277f, 0xc038, 0x21, 0 - .dw 0x27c0, 0xc038, 0x27ff, 0xc038, 0x21, 0 - .dw 0x2840, 0xc038, 0x287f, 0xc038, 0x21, 0 - .dw 0x28c0, 0xc038, 0x28ff, 0xc038, 0x21, 0 - .dw 0x2940, 0xc038, 0x297f, 0xc038, 0x21, 0 - .dw 0x29c0, 0xc038, 0x29ff, 0xc038, 0x21, 0 - .dw 0x2a40, 0xc038, 0x2a7f, 0xc038, 0x21, 0 - .dw 0x2ac0, 0xc038, 0x2aff, 0xc038, 0x21, 0 - .dw 0x2b40, 0xc038, 0x2b7f, 0xc038, 0x21, 0 - .dw 0x2bc0, 0xc038, 0x2bff, 0xc038, 0x21, 0 - .dw 0x2c40, 0xc038, 0x2c7f, 0xc038, 0x21, 0 - .dw 0x2cc0, 0xc038, 0x2cff, 0xc038, 0x21, 0 - .dw 0x2d40, 0xc038, 0x2d7f, 0xc038, 0x21, 0 - .dw 0x2dc0, 0xc038, 0x2dff, 0xc038, 0x21, 0 - .dw 0x2e40, 0xc038, 0x2e7f, 0xc038, 0x21, 0 - .dw 0x2ec0, 0xc038, 0x2eff, 0xc038, 0x21, 0 - .dw 0x2f40, 0xc038, 0x2f7f, 0xc038, 0x21, 0 - .dw 0x2fc0, 0xc038, 0x2fff, 0xc038, 0x21, 0 - .dw 0x3040, 0xc038, 0x307f, 0xc038, 0x21, 0 - .dw 0x30c0, 0xc038, 0x30ff, 0xc038, 0x21, 0 - .dw 0x3140, 0xc038, 0x317f, 0xc038, 0x21, 0 - .dw 0x31c0, 0xc038, 0x31ff, 0xc038, 0x21, 0 - .dw 0x3240, 0xc038, 0x327f, 0xc038, 0x21, 0 - .dw 0x32c0, 0xc038, 0x32ff, 0xc038, 0x21, 0 - .dw 0x3340, 0xc038, 0x337f, 0xc038, 0x21, 0 - .dw 0x33c0, 0xc038, 0x33ff, 0xc038, 0x21, 0 - .dw 0x3440, 0xc038, 0x347f, 0xc038, 0x21, 0 - .dw 0x34c0, 0xc038, 0x34ff, 0xc038, 0x21, 0 - .dw 0x3540, 0xc038, 0x357f, 0xc038, 0x21, 0 - .dw 0x35c0, 0xc038, 0x35ff, 0xc038, 0x21, 0 - .dw 0x3640, 0xc038, 0x367f, 0xc038, 0x21, 0 - .dw 0x36c0, 0xc038, 0x36ff, 0xc038, 0x21, 0 - .dw 0x3740, 0xc038, 0x377f, 0xc038, 0x21, 0 - .dw 0x37c0, 0xc038, 0x37ff, 0xc038, 0x21, 0 - .dw 0x3840, 0xc038, 0x387f, 0xc038, 0x21, 0 - .dw 0x38c0, 0xc038, 0x38ff, 0xc038, 0x21, 0 - .dw 0x3940, 0xc038, 0x397f, 0xc038, 0x21, 0 - .dw 0x39c0, 0xc038, 0x5fff, 0xc038, 0x21, 0 - .dw 0x6040, 0xc038, 0x607f, 0xc038, 0x21, 0 - .dw 0x60c0, 0xc038, 0x60ff, 0xc038, 0x21, 0 - .dw 0x6140, 0xc038, 0x617f, 0xc038, 0x21, 0 - .dw 0x61c0, 0xc038, 0x61ff, 0xc038, 0x21, 0 - .dw 0x6240, 0xc038, 0x627f, 0xc038, 0x21, 0 - .dw 0x62c0, 0xc038, 0x62ff, 0xc038, 0x21, 0 - .dw 0x6340, 0xc038, 0x637f, 0xc038, 0x21, 0 - .dw 0x63c0, 0xc038, 0x63ff, 0xc038, 0x21, 0 - .dw 0x6440, 0xc038, 0x647f, 0xc038, 0x21, 0 - .dw 0x64c0, 0xc038, 0x64ff, 0xc038, 0x21, 0 - .dw 0x6540, 0xc038, 0x657f, 0xc038, 0x21, 0 - .dw 0x65c0, 0xc038, 0x65ff, 0xc038, 0x21, 0 - .dw 0x6640, 0xc038, 0x667f, 0xc038, 0x21, 0 - .dw 0x66c0, 0xc038, 0x66ff, 0xc038, 0x21, 0 - .dw 0x6740, 0xc038, 0x677f, 0xc038, 0x21, 0 - .dw 0x67c0, 0xc038, 0x67ff, 0xc038, 0x21, 0 - .dw 0x6840, 0xc038, 0x687f, 0xc038, 0x21, 0 - .dw 0x68c0, 0xc038, 0x68ff, 0xc038, 0x21, 0 - .dw 0x6940, 0xc038, 0x697f, 0xc038, 0x21, 0 - .dw 0x69c0, 0xc038, 0x69ff, 0xc038, 0x21, 0 - .dw 0x6a40, 0xc038, 0x6a7f, 0xc038, 0x21, 0 - .dw 0x6ac0, 0xc038, 0x6aff, 0xc038, 0x21, 0 - .dw 0x6b40, 0xc038, 0x6b7f, 0xc038, 0x21, 0 - .dw 0x6bc0, 0xc038, 0x6bff, 0xc038, 0x21, 0 - .dw 0x6c40, 0xc038, 0x6c7f, 0xc038, 0x21, 0 - .dw 0x6cc0, 0xc038, 0x6cff, 0xc038, 0x21, 0 - .dw 0x6d40, 0xc038, 0x6d7f, 0xc038, 0x21, 0 - .dw 0x6dc0, 0xc038, 0x6dff, 0xc038, 0x21, 0 - .dw 0x6e40, 0xc038, 0x6e7f, 0xc038, 0x21, 0 - .dw 0x6ec0, 0xc038, 0x6eff, 0xc038, 0x21, 0 - .dw 0x6f40, 0xc038, 0x6f7f, 0xc038, 0x21, 0 - .dw 0x6fc0, 0xc038, 0x6fff, 0xc038, 0x21, 0 - .dw 0x7040, 0xc038, 0x707f, 0xc038, 0x21, 0 - .dw 0x70c0, 0xc038, 0x70ff, 0xc038, 0x21, 0 - .dw 0x7140, 0xc038, 0x717f, 0xc038, 0x21, 0 - .dw 0x71c0, 0xc038, 0x71ff, 0xc038, 0x21, 0 - .dw 0x7240, 0xc038, 0x727f, 0xc038, 0x21, 0 - .dw 0x72c0, 0xc038, 0x72ff, 0xc038, 0x21, 0 - .dw 0x7340, 0xc038, 0x737f, 0xc038, 0x21, 0 - .dw 0x73c0, 0xc038, 0x73ff, 0xc038, 0x21, 0 - .dw 0x7440, 0xc038, 0x747f, 0xc038, 0x21, 0 - .dw 0x74c0, 0xc038, 0x74ff, 0xc038, 0x21, 0 - .dw 0x7540, 0xc038, 0x757f, 0xc038, 0x21, 0 - .dw 0x75c0, 0xc038, 0x75ff, 0xc038, 0x21, 0 - .dw 0x7640, 0xc038, 0x767f, 0xc038, 0x21, 0 - .dw 0x76c0, 0xc038, 0x76ff, 0xc038, 0x21, 0 - .dw 0x7740, 0xc038, 0x777f, 0xc038, 0x21, 0 - .dw 0x77c0, 0xc038, 0x77ff, 0xc038, 0x21, 0 - .dw 0x7840, 0xc038, 0x787f, 0xc038, 0x21, 0 - .dw 0x78c0, 0xc038, 0x78ff, 0xc038, 0x21, 0 - .dw 0x7940, 0xc038, 0x797f, 0xc038, 0x21, 0 - .dw 0x79c0, 0xc038, 0x9fff, 0xc038, 0x21, 0 - .dw 0xa040, 0xc038, 0xa07f, 0xc038, 0x21, 0 - .dw 0xa0c0, 0xc038, 0xa0ff, 0xc038, 0x21, 0 - .dw 0xa140, 0xc038, 0xa17f, 0xc038, 0x21, 0 - .dw 0xa1c0, 0xc038, 0xa1ff, 0xc038, 0x21, 0 - .dw 0xa240, 0xc038, 0xa27f, 0xc038, 0x21, 0 - .dw 0xa2c0, 0xc038, 0xa2ff, 0xc038, 0x21, 0 - .dw 0xa340, 0xc038, 0xa37f, 0xc038, 0x21, 0 - .dw 0xa3c0, 0xc038, 0xa3ff, 0xc038, 0x21, 0 - .dw 0xa440, 0xc038, 0xa47f, 0xc038, 0x21, 0 - .dw 0xa4c0, 0xc038, 0xa4ff, 0xc038, 0x21, 0 - .dw 0xa540, 0xc038, 0xa57f, 0xc038, 0x21, 0 - .dw 0xa5c0, 0xc038, 0xa5ff, 0xc038, 0x21, 0 - .dw 0xa640, 0xc038, 0xa67f, 0xc038, 0x21, 0 - .dw 0xa6c0, 0xc038, 0xa6ff, 0xc038, 0x21, 0 - .dw 0xa740, 0xc038, 0xa77f, 0xc038, 0x21, 0 - .dw 0xa7c0, 0xc038, 0xa7ff, 0xc038, 0x21, 0 - .dw 0xa840, 0xc038, 0xa87f, 0xc038, 0x21, 0 - .dw 0xa8c0, 0xc038, 0xa8ff, 0xc038, 0x21, 0 - .dw 0xa940, 0xc038, 0xa97f, 0xc038, 0x21, 0 - .dw 0xa9c0, 0xc038, 0xa9ff, 0xc038, 0x21, 0 - .dw 0xaa40, 0xc038, 0xaa7f, 0xc038, 0x21, 0 - .dw 0xaac0, 0xc038, 0xaaff, 0xc038, 0x21, 0 - .dw 0xab40, 0xc038, 0xab7f, 0xc038, 0x21, 0 - .dw 0xabc0, 0xc038, 0xabff, 0xc038, 0x21, 0 - .dw 0xac40, 0xc038, 0xac7f, 0xc038, 0x21, 0 - .dw 0xacc0, 0xc038, 0xacff, 0xc038, 0x21, 0 - .dw 0xad40, 0xc038, 0xad7f, 0xc038, 0x21, 0 - .dw 0xadc0, 0xc038, 0xadff, 0xc038, 0x21, 0 - .dw 0xae40, 0xc038, 0xae7f, 0xc038, 0x21, 0 - .dw 0xaec0, 0xc038, 0xaeff, 0xc038, 0x21, 0 - .dw 0xaf40, 0xc038, 0xaf7f, 0xc038, 0x21, 0 - .dw 0xafc0, 0xc038, 0xafff, 0xc038, 0x21, 0 - .dw 0xb040, 0xc038, 0xb07f, 0xc038, 0x21, 0 - .dw 0xb0c0, 0xc038, 0xb0ff, 0xc038, 0x21, 0 - .dw 0xb140, 0xc038, 0xb17f, 0xc038, 0x21, 0 - .dw 0xb1c0, 0xc038, 0xb1ff, 0xc038, 0x21, 0 - .dw 0xb240, 0xc038, 0xb27f, 0xc038, 0x21, 0 - .dw 0xb2c0, 0xc038, 0xb2ff, 0xc038, 0x21, 0 - .dw 0xb340, 0xc038, 0xb37f, 0xc038, 0x21, 0 - .dw 0xb3c0, 0xc038, 0xb3ff, 0xc038, 0x21, 0 - .dw 0xb440, 0xc038, 0xb47f, 0xc038, 0x21, 0 - .dw 0xb4c0, 0xc038, 0xb4ff, 0xc038, 0x21, 0 - .dw 0xb540, 0xc038, 0xb57f, 0xc038, 0x21, 0 - .dw 0xb5c0, 0xc038, 0xb5ff, 0xc038, 0x21, 0 - .dw 0xb640, 0xc038, 0xb67f, 0xc038, 0x21, 0 - .dw 0xb6c0, 0xc038, 0xb6ff, 0xc038, 0x21, 0 - .dw 0xb740, 0xc038, 0xb77f, 0xc038, 0x21, 0 - .dw 0xb7c0, 0xc038, 0xb7ff, 0xc038, 0x21, 0 - .dw 0xb840, 0xc038, 0xb87f, 0xc038, 0x21, 0 - .dw 0xb8c0, 0xc038, 0xb8ff, 0xc038, 0x21, 0 - .dw 0xb940, 0xc038, 0xb97f, 0xc038, 0x21, 0 - .dw 0xb9c0, 0xc038, 0xdfff, 0xc038, 0x21, 0 - .dw 0xe040, 0xc038, 0xe07f, 0xc038, 0x21, 0 - .dw 0xe0c0, 0xc038, 0xe0ff, 0xc038, 0x21, 0 - .dw 0xe140, 0xc038, 0xe17f, 0xc038, 0x21, 0 - .dw 0xe1c0, 0xc038, 0xe1ff, 0xc038, 0x21, 0 - .dw 0xe240, 0xc038, 0xe27f, 0xc038, 0x21, 0 - .dw 0xe2c0, 0xc038, 0xe2ff, 0xc038, 0x21, 0 - .dw 0xe340, 0xc038, 0xe37f, 0xc038, 0x21, 0 - .dw 0xe3c0, 0xc038, 0xe3ff, 0xc038, 0x21, 0 - .dw 0xe440, 0xc038, 0xe47f, 0xc038, 0x21, 0 - .dw 0xe4c0, 0xc038, 0xe4ff, 0xc038, 0x21, 0 - .dw 0xe540, 0xc038, 0xe57f, 0xc038, 0x21, 0 - .dw 0xe5c0, 0xc038, 0xe5ff, 0xc038, 0x21, 0 - .dw 0xe640, 0xc038, 0xe67f, 0xc038, 0x21, 0 - .dw 0xe6c0, 0xc038, 0xe6ff, 0xc038, 0x21, 0 - .dw 0xe740, 0xc038, 0xe77f, 0xc038, 0x21, 0 - .dw 0xe7c0, 0xc038, 0xe7ff, 0xc038, 0x21, 0 - .dw 0xe840, 0xc038, 0xe87f, 0xc038, 0x21, 0 - .dw 0xe8c0, 0xc038, 0xe8ff, 0xc038, 0x21, 0 - .dw 0xe940, 0xc038, 0xe97f, 0xc038, 0x21, 0 - .dw 0xe9c0, 0xc038, 0xe9ff, 0xc038, 0x21, 0 - .dw 0xea40, 0xc038, 0xea7f, 0xc038, 0x21, 0 - .dw 0xeac0, 0xc038, 0xeaff, 0xc038, 0x21, 0 - .dw 0xeb40, 0xc038, 0xeb7f, 0xc038, 0x21, 0 - .dw 0xebc0, 0xc038, 0xebff, 0xc038, 0x21, 0 - .dw 0xec40, 0xc038, 0xec7f, 0xc038, 0x21, 0 - .dw 0xecc0, 0xc038, 0xecff, 0xc038, 0x21, 0 - .dw 0xed40, 0xc038, 0xed7f, 0xc038, 0x21, 0 - .dw 0xedc0, 0xc038, 0xedff, 0xc038, 0x21, 0 - .dw 0xee40, 0xc038, 0xee7f, 0xc038, 0x21, 0 - .dw 0xeec0, 0xc038, 0xeeff, 0xc038, 0x21, 0 - .dw 0xef40, 0xc038, 0xef7f, 0xc038, 0x21, 0 - .dw 0xefc0, 0xc038, 0xefff, 0xc038, 0x21, 0 - .dw 0xf040, 0xc038, 0xf07f, 0xc038, 0x21, 0 - .dw 0xf0c0, 0xc038, 0xf0ff, 0xc038, 0x21, 0 - .dw 0xf140, 0xc038, 0xf17f, 0xc038, 0x21, 0 - .dw 0xf1c0, 0xc038, 0xf1ff, 0xc038, 0x21, 0 - .dw 0xf240, 0xc038, 0xf27f, 0xc038, 0x21, 0 - .dw 0xf2c0, 0xc038, 0xf2ff, 0xc038, 0x21, 0 - .dw 0xf340, 0xc038, 0xf37f, 0xc038, 0x21, 0 - .dw 0xf3c0, 0xc038, 0xf3ff, 0xc038, 0x21, 0 - .dw 0xf440, 0xc038, 0xf47f, 0xc038, 0x21, 0 - .dw 0xf4c0, 0xc038, 0xf4ff, 0xc038, 0x21, 0 - .dw 0xf540, 0xc038, 0xf57f, 0xc038, 0x21, 0 - .dw 0xf5c0, 0xc038, 0xf5ff, 0xc038, 0x21, 0 - .dw 0xf640, 0xc038, 0xf67f, 0xc038, 0x21, 0 - .dw 0xf6c0, 0xc038, 0xf6ff, 0xc038, 0x21, 0 - .dw 0xf740, 0xc038, 0xf77f, 0xc038, 0x21, 0 - .dw 0xf7c0, 0xc038, 0xf7ff, 0xc038, 0x21, 0 - .dw 0xf840, 0xc038, 0xf87f, 0xc038, 0x21, 0 - .dw 0xf8c0, 0xc038, 0xf8ff, 0xc038, 0x21, 0 - .dw 0xf940, 0xc038, 0xf97f, 0xc038, 0x21, 0 - .dw 0xf9c0, 0xc038, 0x1fff, 0xc039, 0x21, 0 - .dw 0x2040, 0xc039, 0x207f, 0xc039, 0x21, 0 - .dw 0x20c0, 0xc039, 0x20ff, 0xc039, 0x21, 0 - .dw 0x2140, 0xc039, 0x217f, 0xc039, 0x21, 0 - .dw 0x21c0, 0xc039, 0x21ff, 0xc039, 0x21, 0 - .dw 0x2240, 0xc039, 0x227f, 0xc039, 0x21, 0 - .dw 0x22c0, 0xc039, 0x22ff, 0xc039, 0x21, 0 - .dw 0x2340, 0xc039, 0x237f, 0xc039, 0x21, 0 - .dw 0x23c0, 0xc039, 0x23ff, 0xc039, 0x21, 0 - .dw 0x2440, 0xc039, 0x247f, 0xc039, 0x21, 0 - .dw 0x24c0, 0xc039, 0x24ff, 0xc039, 0x21, 0 - .dw 0x2540, 0xc039, 0x257f, 0xc039, 0x21, 0 - .dw 0x25c0, 0xc039, 0x25ff, 0xc039, 0x21, 0 - .dw 0x2640, 0xc039, 0x267f, 0xc039, 0x21, 0 - .dw 0x26c0, 0xc039, 0x26ff, 0xc039, 0x21, 0 - .dw 0x2740, 0xc039, 0x277f, 0xc039, 0x21, 0 - .dw 0x27c0, 0xc039, 0x27ff, 0xc039, 0x21, 0 - .dw 0x2840, 0xc039, 0x287f, 0xc039, 0x21, 0 - .dw 0x28c0, 0xc039, 0x28ff, 0xc039, 0x21, 0 - .dw 0x2940, 0xc039, 0x297f, 0xc039, 0x21, 0 - .dw 0x29c0, 0xc039, 0x29ff, 0xc039, 0x21, 0 - .dw 0x2a40, 0xc039, 0x2a7f, 0xc039, 0x21, 0 - .dw 0x2ac0, 0xc039, 0x2aff, 0xc039, 0x21, 0 - .dw 0x2b40, 0xc039, 0x2b7f, 0xc039, 0x21, 0 - .dw 0x2bc0, 0xc039, 0x2bff, 0xc039, 0x21, 0 - .dw 0x2c40, 0xc039, 0x2c7f, 0xc039, 0x21, 0 - .dw 0x2cc0, 0xc039, 0x2cff, 0xc039, 0x21, 0 - .dw 0x2d40, 0xc039, 0x2d7f, 0xc039, 0x21, 0 - .dw 0x2dc0, 0xc039, 0x2dff, 0xc039, 0x21, 0 - .dw 0x2e40, 0xc039, 0x2e7f, 0xc039, 0x21, 0 - .dw 0x2ec0, 0xc039, 0x2eff, 0xc039, 0x21, 0 - .dw 0x2f40, 0xc039, 0x2f7f, 0xc039, 0x21, 0 - .dw 0x2fc0, 0xc039, 0x2fff, 0xc039, 0x21, 0 - .dw 0x3040, 0xc039, 0x307f, 0xc039, 0x21, 0 - .dw 0x30c0, 0xc039, 0x30ff, 0xc039, 0x21, 0 - .dw 0x3140, 0xc039, 0x317f, 0xc039, 0x21, 0 - .dw 0x31c0, 0xc039, 0x31ff, 0xc039, 0x21, 0 - .dw 0x3240, 0xc039, 0x327f, 0xc039, 0x21, 0 - .dw 0x32c0, 0xc039, 0x32ff, 0xc039, 0x21, 0 - .dw 0x3340, 0xc039, 0x337f, 0xc039, 0x21, 0 - .dw 0x33c0, 0xc039, 0x33ff, 0xc039, 0x21, 0 - .dw 0x3440, 0xc039, 0x347f, 0xc039, 0x21, 0 - .dw 0x34c0, 0xc039, 0x34ff, 0xc039, 0x21, 0 - .dw 0x3540, 0xc039, 0x357f, 0xc039, 0x21, 0 - .dw 0x35c0, 0xc039, 0x35ff, 0xc039, 0x21, 0 - .dw 0x3640, 0xc039, 0x367f, 0xc039, 0x21, 0 - .dw 0x36c0, 0xc039, 0x36ff, 0xc039, 0x21, 0 - .dw 0x3740, 0xc039, 0x377f, 0xc039, 0x21, 0 - .dw 0x37c0, 0xc039, 0x37ff, 0xc039, 0x21, 0 - .dw 0x3840, 0xc039, 0x387f, 0xc039, 0x21, 0 - .dw 0x38c0, 0xc039, 0x38ff, 0xc039, 0x21, 0 - .dw 0x3940, 0xc039, 0x397f, 0xc039, 0x21, 0 - .dw 0x39c0, 0xc039, 0x5fff, 0xc039, 0x21, 0 - .dw 0x6040, 0xc039, 0x607f, 0xc039, 0x21, 0 - .dw 0x60c0, 0xc039, 0x60ff, 0xc039, 0x21, 0 - .dw 0x6140, 0xc039, 0x617f, 0xc039, 0x21, 0 - .dw 0x61c0, 0xc039, 0x61ff, 0xc039, 0x21, 0 - .dw 0x6240, 0xc039, 0x627f, 0xc039, 0x21, 0 - .dw 0x62c0, 0xc039, 0x62ff, 0xc039, 0x21, 0 - .dw 0x6340, 0xc039, 0x637f, 0xc039, 0x21, 0 - .dw 0x63c0, 0xc039, 0x63ff, 0xc039, 0x21, 0 - .dw 0x6440, 0xc039, 0x647f, 0xc039, 0x21, 0 - .dw 0x64c0, 0xc039, 0x64ff, 0xc039, 0x21, 0 - .dw 0x6540, 0xc039, 0x657f, 0xc039, 0x21, 0 - .dw 0x65c0, 0xc039, 0x65ff, 0xc039, 0x21, 0 - .dw 0x6640, 0xc039, 0x667f, 0xc039, 0x21, 0 - .dw 0x66c0, 0xc039, 0x66ff, 0xc039, 0x21, 0 - .dw 0x6740, 0xc039, 0x677f, 0xc039, 0x21, 0 - .dw 0x67c0, 0xc039, 0x67ff, 0xc039, 0x21, 0 - .dw 0x6840, 0xc039, 0x687f, 0xc039, 0x21, 0 - .dw 0x68c0, 0xc039, 0x68ff, 0xc039, 0x21, 0 - .dw 0x6940, 0xc039, 0x697f, 0xc039, 0x21, 0 - .dw 0x69c0, 0xc039, 0x69ff, 0xc039, 0x21, 0 - .dw 0x6a40, 0xc039, 0x6a7f, 0xc039, 0x21, 0 - .dw 0x6ac0, 0xc039, 0x6aff, 0xc039, 0x21, 0 - .dw 0x6b40, 0xc039, 0x6b7f, 0xc039, 0x21, 0 - .dw 0x6bc0, 0xc039, 0x6bff, 0xc039, 0x21, 0 - .dw 0x6c40, 0xc039, 0x6c7f, 0xc039, 0x21, 0 - .dw 0x6cc0, 0xc039, 0x6cff, 0xc039, 0x21, 0 - .dw 0x6d40, 0xc039, 0x6d7f, 0xc039, 0x21, 0 - .dw 0x6dc0, 0xc039, 0x6dff, 0xc039, 0x21, 0 - .dw 0x6e40, 0xc039, 0x6e7f, 0xc039, 0x21, 0 - .dw 0x6ec0, 0xc039, 0x6eff, 0xc039, 0x21, 0 - .dw 0x6f40, 0xc039, 0x6f7f, 0xc039, 0x21, 0 - .dw 0x6fc0, 0xc039, 0x6fff, 0xc039, 0x21, 0 - .dw 0x7040, 0xc039, 0x707f, 0xc039, 0x21, 0 - .dw 0x70c0, 0xc039, 0x70ff, 0xc039, 0x21, 0 - .dw 0x7140, 0xc039, 0x717f, 0xc039, 0x21, 0 - .dw 0x71c0, 0xc039, 0x71ff, 0xc039, 0x21, 0 - .dw 0x7240, 0xc039, 0x727f, 0xc039, 0x21, 0 - .dw 0x72c0, 0xc039, 0x72ff, 0xc039, 0x21, 0 - .dw 0x7340, 0xc039, 0x737f, 0xc039, 0x21, 0 - .dw 0x73c0, 0xc039, 0x73ff, 0xc039, 0x21, 0 - .dw 0x7440, 0xc039, 0x747f, 0xc039, 0x21, 0 - .dw 0x74c0, 0xc039, 0x74ff, 0xc039, 0x21, 0 - .dw 0x7540, 0xc039, 0x757f, 0xc039, 0x21, 0 - .dw 0x75c0, 0xc039, 0x75ff, 0xc039, 0x21, 0 - .dw 0x7640, 0xc039, 0x767f, 0xc039, 0x21, 0 - .dw 0x76c0, 0xc039, 0x76ff, 0xc039, 0x21, 0 - .dw 0x7740, 0xc039, 0x777f, 0xc039, 0x21, 0 - .dw 0x77c0, 0xc039, 0x77ff, 0xc039, 0x21, 0 - .dw 0x7840, 0xc039, 0x787f, 0xc039, 0x21, 0 - .dw 0x78c0, 0xc039, 0x78ff, 0xc039, 0x21, 0 - .dw 0x7940, 0xc039, 0x797f, 0xc039, 0x21, 0 - .dw 0x79c0, 0xc039, 0x9fff, 0xc039, 0x21, 0 - .dw 0xa040, 0xc039, 0xa07f, 0xc039, 0x21, 0 - .dw 0xa0c0, 0xc039, 0xa0ff, 0xc039, 0x21, 0 - .dw 0xa140, 0xc039, 0xa17f, 0xc039, 0x21, 0 - .dw 0xa1c0, 0xc039, 0xa1ff, 0xc039, 0x21, 0 - .dw 0xa240, 0xc039, 0xa27f, 0xc039, 0x21, 0 - .dw 0xa2c0, 0xc039, 0xa2ff, 0xc039, 0x21, 0 - .dw 0xa340, 0xc039, 0xa37f, 0xc039, 0x21, 0 - .dw 0xa3c0, 0xc039, 0xa3ff, 0xc039, 0x21, 0 - .dw 0xa440, 0xc039, 0xa47f, 0xc039, 0x21, 0 - .dw 0xa4c0, 0xc039, 0xa4ff, 0xc039, 0x21, 0 - .dw 0xa540, 0xc039, 0xa57f, 0xc039, 0x21, 0 - .dw 0xa5c0, 0xc039, 0xa5ff, 0xc039, 0x21, 0 - .dw 0xa640, 0xc039, 0xa67f, 0xc039, 0x21, 0 - .dw 0xa6c0, 0xc039, 0xa6ff, 0xc039, 0x21, 0 - .dw 0xa740, 0xc039, 0xa77f, 0xc039, 0x21, 0 - .dw 0xa7c0, 0xc039, 0xa7ff, 0xc039, 0x21, 0 - .dw 0xa840, 0xc039, 0xa87f, 0xc039, 0x21, 0 - .dw 0xa8c0, 0xc039, 0xa8ff, 0xc039, 0x21, 0 - .dw 0xa940, 0xc039, 0xa97f, 0xc039, 0x21, 0 - .dw 0xa9c0, 0xc039, 0xa9ff, 0xc039, 0x21, 0 - .dw 0xaa40, 0xc039, 0xaa7f, 0xc039, 0x21, 0 - .dw 0xaac0, 0xc039, 0xaaff, 0xc039, 0x21, 0 - .dw 0xab40, 0xc039, 0xab7f, 0xc039, 0x21, 0 - .dw 0xabc0, 0xc039, 0xabff, 0xc039, 0x21, 0 - .dw 0xac40, 0xc039, 0xac7f, 0xc039, 0x21, 0 - .dw 0xacc0, 0xc039, 0xacff, 0xc039, 0x21, 0 - .dw 0xad40, 0xc039, 0xad7f, 0xc039, 0x21, 0 - .dw 0xadc0, 0xc039, 0xadff, 0xc039, 0x21, 0 - .dw 0xae40, 0xc039, 0xae7f, 0xc039, 0x21, 0 - .dw 0xaec0, 0xc039, 0xaeff, 0xc039, 0x21, 0 - .dw 0xaf40, 0xc039, 0xaf7f, 0xc039, 0x21, 0 - .dw 0xafc0, 0xc039, 0xafff, 0xc039, 0x21, 0 - .dw 0xb040, 0xc039, 0xb07f, 0xc039, 0x21, 0 - .dw 0xb0c0, 0xc039, 0xb0ff, 0xc039, 0x21, 0 - .dw 0xb140, 0xc039, 0xb17f, 0xc039, 0x21, 0 - .dw 0xb1c0, 0xc039, 0xb1ff, 0xc039, 0x21, 0 - .dw 0xb240, 0xc039, 0xb27f, 0xc039, 0x21, 0 - .dw 0xb2c0, 0xc039, 0xb2ff, 0xc039, 0x21, 0 - .dw 0xb340, 0xc039, 0xb37f, 0xc039, 0x21, 0 - .dw 0xb3c0, 0xc039, 0xb3ff, 0xc039, 0x21, 0 - .dw 0xb440, 0xc039, 0xb47f, 0xc039, 0x21, 0 - .dw 0xb4c0, 0xc039, 0xb4ff, 0xc039, 0x21, 0 - .dw 0xb540, 0xc039, 0xb57f, 0xc039, 0x21, 0 - .dw 0xb5c0, 0xc039, 0xb5ff, 0xc039, 0x21, 0 - .dw 0xb640, 0xc039, 0xb67f, 0xc039, 0x21, 0 - .dw 0xb6c0, 0xc039, 0xb6ff, 0xc039, 0x21, 0 - .dw 0xb740, 0xc039, 0xb77f, 0xc039, 0x21, 0 - .dw 0xb7c0, 0xc039, 0xb7ff, 0xc039, 0x21, 0 - .dw 0xb840, 0xc039, 0xb87f, 0xc039, 0x21, 0 - .dw 0xb8c0, 0xc039, 0xb8ff, 0xc039, 0x21, 0 - .dw 0xb940, 0xc039, 0xb97f, 0xc039, 0x21, 0 - .dw 0xb9c0, 0xc039, 0xdfff, 0xc039, 0x21, 0 - .dw 0xe040, 0xc039, 0xe07f, 0xc039, 0x21, 0 - .dw 0xe0c0, 0xc039, 0xe0ff, 0xc039, 0x21, 0 - .dw 0xe140, 0xc039, 0xe17f, 0xc039, 0x21, 0 - .dw 0xe1c0, 0xc039, 0xe1ff, 0xc039, 0x21, 0 - .dw 0xe240, 0xc039, 0xe27f, 0xc039, 0x21, 0 - .dw 0xe2c0, 0xc039, 0xe2ff, 0xc039, 0x21, 0 - .dw 0xe340, 0xc039, 0xe37f, 0xc039, 0x21, 0 - .dw 0xe3c0, 0xc039, 0xe3ff, 0xc039, 0x21, 0 - .dw 0xe440, 0xc039, 0xe47f, 0xc039, 0x21, 0 - .dw 0xe4c0, 0xc039, 0xe4ff, 0xc039, 0x21, 0 - .dw 0xe540, 0xc039, 0xe57f, 0xc039, 0x21, 0 - .dw 0xe5c0, 0xc039, 0xe5ff, 0xc039, 0x21, 0 - .dw 0xe640, 0xc039, 0xe67f, 0xc039, 0x21, 0 - .dw 0xe6c0, 0xc039, 0xe6ff, 0xc039, 0x21, 0 - .dw 0xe740, 0xc039, 0xe77f, 0xc039, 0x21, 0 - .dw 0xe7c0, 0xc039, 0xe7ff, 0xc039, 0x21, 0 - .dw 0xe840, 0xc039, 0xe87f, 0xc039, 0x21, 0 - .dw 0xe8c0, 0xc039, 0xe8ff, 0xc039, 0x21, 0 - .dw 0xe940, 0xc039, 0xe97f, 0xc039, 0x21, 0 - .dw 0xe9c0, 0xc039, 0xe9ff, 0xc039, 0x21, 0 - .dw 0xea40, 0xc039, 0xea7f, 0xc039, 0x21, 0 - .dw 0xeac0, 0xc039, 0xeaff, 0xc039, 0x21, 0 - .dw 0xeb40, 0xc039, 0xeb7f, 0xc039, 0x21, 0 - .dw 0xebc0, 0xc039, 0xebff, 0xc039, 0x21, 0 - .dw 0xec40, 0xc039, 0xec7f, 0xc039, 0x21, 0 - .dw 0xecc0, 0xc039, 0xecff, 0xc039, 0x21, 0 - .dw 0xed40, 0xc039, 0xed7f, 0xc039, 0x21, 0 - .dw 0xedc0, 0xc039, 0xedff, 0xc039, 0x21, 0 - .dw 0xee40, 0xc039, 0xee7f, 0xc039, 0x21, 0 - .dw 0xeec0, 0xc039, 0xeeff, 0xc039, 0x21, 0 - .dw 0xef40, 0xc039, 0xef7f, 0xc039, 0x21, 0 - .dw 0xefc0, 0xc039, 0xefff, 0xc039, 0x21, 0 - .dw 0xf040, 0xc039, 0xf07f, 0xc039, 0x21, 0 - .dw 0xf0c0, 0xc039, 0xf0ff, 0xc039, 0x21, 0 - .dw 0xf140, 0xc039, 0xf17f, 0xc039, 0x21, 0 - .dw 0xf1c0, 0xc039, 0xf1ff, 0xc039, 0x21, 0 - .dw 0xf240, 0xc039, 0xf27f, 0xc039, 0x21, 0 - .dw 0xf2c0, 0xc039, 0xf2ff, 0xc039, 0x21, 0 - .dw 0xf340, 0xc039, 0xf37f, 0xc039, 0x21, 0 - .dw 0xf3c0, 0xc039, 0xf3ff, 0xc039, 0x21, 0 - .dw 0xf440, 0xc039, 0xf47f, 0xc039, 0x21, 0 - .dw 0xf4c0, 0xc039, 0xf4ff, 0xc039, 0x21, 0 - .dw 0xf540, 0xc039, 0xf57f, 0xc039, 0x21, 0 - .dw 0xf5c0, 0xc039, 0xf5ff, 0xc039, 0x21, 0 - .dw 0xf640, 0xc039, 0xf67f, 0xc039, 0x21, 0 - .dw 0xf6c0, 0xc039, 0xf6ff, 0xc039, 0x21, 0 - .dw 0xf740, 0xc039, 0xf77f, 0xc039, 0x21, 0 - .dw 0xf7c0, 0xc039, 0xf7ff, 0xc039, 0x21, 0 - .dw 0xf840, 0xc039, 0xf87f, 0xc039, 0x21, 0 - .dw 0xf8c0, 0xc039, 0xf8ff, 0xc039, 0x21, 0 - .dw 0xf940, 0xc039, 0xf97f, 0xc039, 0x21, 0 - .dw 0xf9c0, 0xc039, 0x1fff, 0xc03a, 0x21, 0 - .dw 0x2040, 0xc03a, 0x207f, 0xc03a, 0x21, 0 - .dw 0x20c0, 0xc03a, 0x20ff, 0xc03a, 0x21, 0 - .dw 0x2140, 0xc03a, 0x217f, 0xc03a, 0x21, 0 - .dw 0x21c0, 0xc03a, 0x21ff, 0xc03a, 0x21, 0 - .dw 0x2240, 0xc03a, 0x227f, 0xc03a, 0x21, 0 - .dw 0x22c0, 0xc03a, 0x22ff, 0xc03a, 0x21, 0 - .dw 0x2340, 0xc03a, 0x237f, 0xc03a, 0x21, 0 - .dw 0x23c0, 0xc03a, 0x23ff, 0xc03a, 0x21, 0 - .dw 0x2440, 0xc03a, 0x247f, 0xc03a, 0x21, 0 - .dw 0x24c0, 0xc03a, 0x24ff, 0xc03a, 0x21, 0 - .dw 0x2540, 0xc03a, 0x257f, 0xc03a, 0x21, 0 - .dw 0x25c0, 0xc03a, 0x25ff, 0xc03a, 0x21, 0 - .dw 0x2640, 0xc03a, 0x267f, 0xc03a, 0x21, 0 - .dw 0x26c0, 0xc03a, 0x26ff, 0xc03a, 0x21, 0 - .dw 0x2740, 0xc03a, 0x277f, 0xc03a, 0x21, 0 - .dw 0x27c0, 0xc03a, 0x27ff, 0xc03a, 0x21, 0 - .dw 0x2840, 0xc03a, 0x287f, 0xc03a, 0x21, 0 - .dw 0x28c0, 0xc03a, 0x28ff, 0xc03a, 0x21, 0 - .dw 0x2940, 0xc03a, 0x297f, 0xc03a, 0x21, 0 - .dw 0x29c0, 0xc03a, 0x29ff, 0xc03a, 0x21, 0 - .dw 0x2a40, 0xc03a, 0x2a7f, 0xc03a, 0x21, 0 - .dw 0x2ac0, 0xc03a, 0x2aff, 0xc03a, 0x21, 0 - .dw 0x2b40, 0xc03a, 0x2b7f, 0xc03a, 0x21, 0 - .dw 0x2bc0, 0xc03a, 0x2bff, 0xc03a, 0x21, 0 - .dw 0x2c40, 0xc03a, 0x2c7f, 0xc03a, 0x21, 0 - .dw 0x2cc0, 0xc03a, 0x2cff, 0xc03a, 0x21, 0 - .dw 0x2d40, 0xc03a, 0x2d7f, 0xc03a, 0x21, 0 - .dw 0x2dc0, 0xc03a, 0x2dff, 0xc03a, 0x21, 0 - .dw 0x2e40, 0xc03a, 0x2e7f, 0xc03a, 0x21, 0 - .dw 0x2ec0, 0xc03a, 0x2eff, 0xc03a, 0x21, 0 - .dw 0x2f40, 0xc03a, 0x2f7f, 0xc03a, 0x21, 0 - .dw 0x2fc0, 0xc03a, 0x2fff, 0xc03a, 0x21, 0 - .dw 0x3040, 0xc03a, 0x307f, 0xc03a, 0x21, 0 - .dw 0x30c0, 0xc03a, 0x30ff, 0xc03a, 0x21, 0 - .dw 0x3140, 0xc03a, 0x317f, 0xc03a, 0x21, 0 - .dw 0x31c0, 0xc03a, 0x31ff, 0xc03a, 0x21, 0 - .dw 0x3240, 0xc03a, 0x327f, 0xc03a, 0x21, 0 - .dw 0x32c0, 0xc03a, 0x32ff, 0xc03a, 0x21, 0 - .dw 0x3340, 0xc03a, 0x337f, 0xc03a, 0x21, 0 - .dw 0x33c0, 0xc03a, 0x33ff, 0xc03a, 0x21, 0 - .dw 0x3440, 0xc03a, 0x347f, 0xc03a, 0x21, 0 - .dw 0x34c0, 0xc03a, 0x34ff, 0xc03a, 0x21, 0 - .dw 0x3540, 0xc03a, 0x357f, 0xc03a, 0x21, 0 - .dw 0x35c0, 0xc03a, 0x35ff, 0xc03a, 0x21, 0 - .dw 0x3640, 0xc03a, 0x367f, 0xc03a, 0x21, 0 - .dw 0x36c0, 0xc03a, 0x36ff, 0xc03a, 0x21, 0 - .dw 0x3740, 0xc03a, 0x377f, 0xc03a, 0x21, 0 - .dw 0x37c0, 0xc03a, 0x37ff, 0xc03a, 0x21, 0 - .dw 0x3840, 0xc03a, 0x387f, 0xc03a, 0x21, 0 - .dw 0x38c0, 0xc03a, 0x38ff, 0xc03a, 0x21, 0 - .dw 0x3940, 0xc03a, 0x397f, 0xc03a, 0x21, 0 - .dw 0x39c0, 0xc03a, 0x5fff, 0xc03a, 0x21, 0 - .dw 0x6040, 0xc03a, 0x607f, 0xc03a, 0x21, 0 - .dw 0x60c0, 0xc03a, 0x60ff, 0xc03a, 0x21, 0 - .dw 0x6140, 0xc03a, 0x617f, 0xc03a, 0x21, 0 - .dw 0x61c0, 0xc03a, 0x61ff, 0xc03a, 0x21, 0 - .dw 0x6240, 0xc03a, 0x627f, 0xc03a, 0x21, 0 - .dw 0x62c0, 0xc03a, 0x62ff, 0xc03a, 0x21, 0 - .dw 0x6340, 0xc03a, 0x637f, 0xc03a, 0x21, 0 - .dw 0x63c0, 0xc03a, 0x63ff, 0xc03a, 0x21, 0 - .dw 0x6440, 0xc03a, 0x647f, 0xc03a, 0x21, 0 - .dw 0x64c0, 0xc03a, 0x64ff, 0xc03a, 0x21, 0 - .dw 0x6540, 0xc03a, 0x657f, 0xc03a, 0x21, 0 - .dw 0x65c0, 0xc03a, 0x65ff, 0xc03a, 0x21, 0 - .dw 0x6640, 0xc03a, 0x667f, 0xc03a, 0x21, 0 - .dw 0x66c0, 0xc03a, 0x66ff, 0xc03a, 0x21, 0 - .dw 0x6740, 0xc03a, 0x677f, 0xc03a, 0x21, 0 - .dw 0x67c0, 0xc03a, 0x67ff, 0xc03a, 0x21, 0 - .dw 0x6840, 0xc03a, 0x687f, 0xc03a, 0x21, 0 - .dw 0x68c0, 0xc03a, 0x68ff, 0xc03a, 0x21, 0 - .dw 0x6940, 0xc03a, 0x697f, 0xc03a, 0x21, 0 - .dw 0x69c0, 0xc03a, 0x69ff, 0xc03a, 0x21, 0 - .dw 0x6a40, 0xc03a, 0x6a7f, 0xc03a, 0x21, 0 - .dw 0x6ac0, 0xc03a, 0x6aff, 0xc03a, 0x21, 0 - .dw 0x6b40, 0xc03a, 0x6b7f, 0xc03a, 0x21, 0 - .dw 0x6bc0, 0xc03a, 0x6bff, 0xc03a, 0x21, 0 - .dw 0x6c40, 0xc03a, 0x6c7f, 0xc03a, 0x21, 0 - .dw 0x6cc0, 0xc03a, 0x6cff, 0xc03a, 0x21, 0 - .dw 0x6d40, 0xc03a, 0x6d7f, 0xc03a, 0x21, 0 - .dw 0x6dc0, 0xc03a, 0x6dff, 0xc03a, 0x21, 0 - .dw 0x6e40, 0xc03a, 0x6e7f, 0xc03a, 0x21, 0 - .dw 0x6ec0, 0xc03a, 0x6eff, 0xc03a, 0x21, 0 - .dw 0x6f40, 0xc03a, 0x6f7f, 0xc03a, 0x21, 0 - .dw 0x6fc0, 0xc03a, 0x6fff, 0xc03a, 0x21, 0 - .dw 0x7040, 0xc03a, 0x707f, 0xc03a, 0x21, 0 - .dw 0x70c0, 0xc03a, 0x70ff, 0xc03a, 0x21, 0 - .dw 0x7140, 0xc03a, 0x717f, 0xc03a, 0x21, 0 - .dw 0x71c0, 0xc03a, 0x71ff, 0xc03a, 0x21, 0 - .dw 0x7240, 0xc03a, 0x727f, 0xc03a, 0x21, 0 - .dw 0x72c0, 0xc03a, 0x72ff, 0xc03a, 0x21, 0 - .dw 0x7340, 0xc03a, 0x737f, 0xc03a, 0x21, 0 - .dw 0x73c0, 0xc03a, 0x73ff, 0xc03a, 0x21, 0 - .dw 0x7440, 0xc03a, 0x747f, 0xc03a, 0x21, 0 - .dw 0x74c0, 0xc03a, 0x74ff, 0xc03a, 0x21, 0 - .dw 0x7540, 0xc03a, 0x757f, 0xc03a, 0x21, 0 - .dw 0x75c0, 0xc03a, 0x75ff, 0xc03a, 0x21, 0 - .dw 0x7640, 0xc03a, 0x767f, 0xc03a, 0x21, 0 - .dw 0x76c0, 0xc03a, 0x76ff, 0xc03a, 0x21, 0 - .dw 0x7740, 0xc03a, 0x777f, 0xc03a, 0x21, 0 - .dw 0x77c0, 0xc03a, 0x77ff, 0xc03a, 0x21, 0 - .dw 0x7840, 0xc03a, 0x787f, 0xc03a, 0x21, 0 - .dw 0x78c0, 0xc03a, 0x78ff, 0xc03a, 0x21, 0 - .dw 0x7940, 0xc03a, 0x797f, 0xc03a, 0x21, 0 - .dw 0x79c0, 0xc03a, 0x9fff, 0xc03a, 0x21, 0 - .dw 0xa040, 0xc03a, 0xa07f, 0xc03a, 0x21, 0 - .dw 0xa0c0, 0xc03a, 0xa0ff, 0xc03a, 0x21, 0 - .dw 0xa140, 0xc03a, 0xa17f, 0xc03a, 0x21, 0 - .dw 0xa1c0, 0xc03a, 0xa1ff, 0xc03a, 0x21, 0 - .dw 0xa240, 0xc03a, 0xa27f, 0xc03a, 0x21, 0 - .dw 0xa2c0, 0xc03a, 0xa2ff, 0xc03a, 0x21, 0 - .dw 0xa340, 0xc03a, 0xa37f, 0xc03a, 0x21, 0 - .dw 0xa3c0, 0xc03a, 0xa3ff, 0xc03a, 0x21, 0 - .dw 0xa440, 0xc03a, 0xa47f, 0xc03a, 0x21, 0 - .dw 0xa4c0, 0xc03a, 0xa4ff, 0xc03a, 0x21, 0 - .dw 0xa540, 0xc03a, 0xa57f, 0xc03a, 0x21, 0 - .dw 0xa5c0, 0xc03a, 0xa5ff, 0xc03a, 0x21, 0 - .dw 0xa640, 0xc03a, 0xa67f, 0xc03a, 0x21, 0 - .dw 0xa6c0, 0xc03a, 0xa6ff, 0xc03a, 0x21, 0 - .dw 0xa740, 0xc03a, 0xa77f, 0xc03a, 0x21, 0 - .dw 0xa7c0, 0xc03a, 0xa7ff, 0xc03a, 0x21, 0 - .dw 0xa840, 0xc03a, 0xa87f, 0xc03a, 0x21, 0 - .dw 0xa8c0, 0xc03a, 0xa8ff, 0xc03a, 0x21, 0 - .dw 0xa940, 0xc03a, 0xa97f, 0xc03a, 0x21, 0 - .dw 0xa9c0, 0xc03a, 0xa9ff, 0xc03a, 0x21, 0 - .dw 0xaa40, 0xc03a, 0xaa7f, 0xc03a, 0x21, 0 - .dw 0xaac0, 0xc03a, 0xaaff, 0xc03a, 0x21, 0 - .dw 0xab40, 0xc03a, 0xab7f, 0xc03a, 0x21, 0 - .dw 0xabc0, 0xc03a, 0xabff, 0xc03a, 0x21, 0 - .dw 0xac40, 0xc03a, 0xac7f, 0xc03a, 0x21, 0 - .dw 0xacc0, 0xc03a, 0xacff, 0xc03a, 0x21, 0 - .dw 0xad40, 0xc03a, 0xad7f, 0xc03a, 0x21, 0 - .dw 0xadc0, 0xc03a, 0xadff, 0xc03a, 0x21, 0 - .dw 0xae40, 0xc03a, 0xae7f, 0xc03a, 0x21, 0 - .dw 0xaec0, 0xc03a, 0xaeff, 0xc03a, 0x21, 0 - .dw 0xaf40, 0xc03a, 0xaf7f, 0xc03a, 0x21, 0 - .dw 0xafc0, 0xc03a, 0xafff, 0xc03a, 0x21, 0 - .dw 0xb040, 0xc03a, 0xb07f, 0xc03a, 0x21, 0 - .dw 0xb0c0, 0xc03a, 0xb0ff, 0xc03a, 0x21, 0 - .dw 0xb140, 0xc03a, 0xb17f, 0xc03a, 0x21, 0 - .dw 0xb1c0, 0xc03a, 0xb1ff, 0xc03a, 0x21, 0 - .dw 0xb240, 0xc03a, 0xb27f, 0xc03a, 0x21, 0 - .dw 0xb2c0, 0xc03a, 0xb2ff, 0xc03a, 0x21, 0 - .dw 0xb340, 0xc03a, 0xb37f, 0xc03a, 0x21, 0 - .dw 0xb3c0, 0xc03a, 0xb3ff, 0xc03a, 0x21, 0 - .dw 0xb440, 0xc03a, 0xb47f, 0xc03a, 0x21, 0 - .dw 0xb4c0, 0xc03a, 0xb4ff, 0xc03a, 0x21, 0 - .dw 0xb540, 0xc03a, 0xb57f, 0xc03a, 0x21, 0 - .dw 0xb5c0, 0xc03a, 0xb5ff, 0xc03a, 0x21, 0 - .dw 0xb640, 0xc03a, 0xb67f, 0xc03a, 0x21, 0 - .dw 0xb6c0, 0xc03a, 0xb6ff, 0xc03a, 0x21, 0 - .dw 0xb740, 0xc03a, 0xb77f, 0xc03a, 0x21, 0 - .dw 0xb7c0, 0xc03a, 0xb7ff, 0xc03a, 0x21, 0 - .dw 0xb840, 0xc03a, 0xb87f, 0xc03a, 0x21, 0 - .dw 0xb8c0, 0xc03a, 0xb8ff, 0xc03a, 0x21, 0 - .dw 0xb940, 0xc03a, 0xb97f, 0xc03a, 0x21, 0 - .dw 0xb9c0, 0xc03a, 0xdfff, 0xc03a, 0x21, 0 - .dw 0xe040, 0xc03a, 0xe07f, 0xc03a, 0x21, 0 - .dw 0xe0c0, 0xc03a, 0xe0ff, 0xc03a, 0x21, 0 - .dw 0xe140, 0xc03a, 0xe17f, 0xc03a, 0x21, 0 - .dw 0xe1c0, 0xc03a, 0xe1ff, 0xc03a, 0x21, 0 - .dw 0xe240, 0xc03a, 0xe27f, 0xc03a, 0x21, 0 - .dw 0xe2c0, 0xc03a, 0xe2ff, 0xc03a, 0x21, 0 - .dw 0xe340, 0xc03a, 0xe37f, 0xc03a, 0x21, 0 - .dw 0xe3c0, 0xc03a, 0xe3ff, 0xc03a, 0x21, 0 - .dw 0xe440, 0xc03a, 0xe47f, 0xc03a, 0x21, 0 - .dw 0xe4c0, 0xc03a, 0xe4ff, 0xc03a, 0x21, 0 - .dw 0xe540, 0xc03a, 0xe57f, 0xc03a, 0x21, 0 - .dw 0xe5c0, 0xc03a, 0xe5ff, 0xc03a, 0x21, 0 - .dw 0xe640, 0xc03a, 0xe67f, 0xc03a, 0x21, 0 - .dw 0xe6c0, 0xc03a, 0xe6ff, 0xc03a, 0x21, 0 - .dw 0xe740, 0xc03a, 0xe77f, 0xc03a, 0x21, 0 - .dw 0xe7c0, 0xc03a, 0xe7ff, 0xc03a, 0x21, 0 - .dw 0xe840, 0xc03a, 0xe87f, 0xc03a, 0x21, 0 - .dw 0xe8c0, 0xc03a, 0xe8ff, 0xc03a, 0x21, 0 - .dw 0xe940, 0xc03a, 0xe97f, 0xc03a, 0x21, 0 - .dw 0xe9c0, 0xc03a, 0xe9ff, 0xc03a, 0x21, 0 - .dw 0xea40, 0xc03a, 0xea7f, 0xc03a, 0x21, 0 - .dw 0xeac0, 0xc03a, 0xeaff, 0xc03a, 0x21, 0 - .dw 0xeb40, 0xc03a, 0xeb7f, 0xc03a, 0x21, 0 - .dw 0xebc0, 0xc03a, 0xebff, 0xc03a, 0x21, 0 - .dw 0xec40, 0xc03a, 0xec7f, 0xc03a, 0x21, 0 - .dw 0xecc0, 0xc03a, 0xecff, 0xc03a, 0x21, 0 - .dw 0xed40, 0xc03a, 0xed7f, 0xc03a, 0x21, 0 - .dw 0xedc0, 0xc03a, 0xedff, 0xc03a, 0x21, 0 - .dw 0xee40, 0xc03a, 0xee7f, 0xc03a, 0x21, 0 - .dw 0xeec0, 0xc03a, 0xeeff, 0xc03a, 0x21, 0 - .dw 0xef40, 0xc03a, 0xef7f, 0xc03a, 0x21, 0 - .dw 0xefc0, 0xc03a, 0xefff, 0xc03a, 0x21, 0 - .dw 0xf040, 0xc03a, 0xf07f, 0xc03a, 0x21, 0 - .dw 0xf0c0, 0xc03a, 0xf0ff, 0xc03a, 0x21, 0 - .dw 0xf140, 0xc03a, 0xf17f, 0xc03a, 0x21, 0 - .dw 0xf1c0, 0xc03a, 0xf1ff, 0xc03a, 0x21, 0 - .dw 0xf240, 0xc03a, 0xf27f, 0xc03a, 0x21, 0 - .dw 0xf2c0, 0xc03a, 0xf2ff, 0xc03a, 0x21, 0 - .dw 0xf340, 0xc03a, 0xf37f, 0xc03a, 0x21, 0 - .dw 0xf3c0, 0xc03a, 0xf3ff, 0xc03a, 0x21, 0 - .dw 0xf440, 0xc03a, 0xf47f, 0xc03a, 0x21, 0 - .dw 0xf4c0, 0xc03a, 0xf4ff, 0xc03a, 0x21, 0 - .dw 0xf540, 0xc03a, 0xf57f, 0xc03a, 0x21, 0 - .dw 0xf5c0, 0xc03a, 0xf5ff, 0xc03a, 0x21, 0 - .dw 0xf640, 0xc03a, 0xf67f, 0xc03a, 0x21, 0 - .dw 0xf6c0, 0xc03a, 0xf6ff, 0xc03a, 0x21, 0 - .dw 0xf740, 0xc03a, 0xf77f, 0xc03a, 0x21, 0 - .dw 0xf7c0, 0xc03a, 0xf7ff, 0xc03a, 0x21, 0 - .dw 0xf840, 0xc03a, 0xf87f, 0xc03a, 0x21, 0 - .dw 0xf8c0, 0xc03a, 0xf8ff, 0xc03a, 0x21, 0 - .dw 0xf940, 0xc03a, 0xf97f, 0xc03a, 0x21, 0 - .dw 0xf9c0, 0xc03a, 0xffff, 0xc03b, 0x21, 0 - .dw 0x0040, 0xc03c, 0x007f, 0xc03c, 0x21, 0 - .dw 0x00c0, 0xc03c, 0x00ff, 0xc03c, 0x21, 0 - .dw 0x0140, 0xc03c, 0x017f, 0xc03c, 0x21, 0 - .dw 0x01c0, 0xc03c, 0x01ff, 0xc03c, 0x21, 0 - .dw 0x0240, 0xc03c, 0x027f, 0xc03c, 0x21, 0 - .dw 0x02c0, 0xc03c, 0x02ff, 0xc03c, 0x21, 0 - .dw 0x0340, 0xc03c, 0x037f, 0xc03c, 0x21, 0 - .dw 0x03c0, 0xc03c, 0x03ff, 0xc03c, 0x21, 0 - .dw 0x0440, 0xc03c, 0x047f, 0xc03c, 0x21, 0 - .dw 0x04c0, 0xc03c, 0x04ff, 0xc03c, 0x21, 0 - .dw 0x0540, 0xc03c, 0x057f, 0xc03c, 0x21, 0 - .dw 0x05c0, 0xc03c, 0x05ff, 0xc03c, 0x21, 0 - .dw 0x0640, 0xc03c, 0x067f, 0xc03c, 0x21, 0 - .dw 0x06c0, 0xc03c, 0x06ff, 0xc03c, 0x21, 0 - .dw 0x0740, 0xc03c, 0x077f, 0xc03c, 0x21, 0 - .dw 0x07c0, 0xc03c, 0x07ff, 0xc03c, 0x21, 0 - .dw 0x0840, 0xc03c, 0x087f, 0xc03c, 0x21, 0 - .dw 0x08c0, 0xc03c, 0x08ff, 0xc03c, 0x21, 0 - .dw 0x0940, 0xc03c, 0x097f, 0xc03c, 0x21, 0 - .dw 0x09c0, 0xc03c, 0x09ff, 0xc03c, 0x21, 0 - .dw 0x0a40, 0xc03c, 0x0a7f, 0xc03c, 0x21, 0 - .dw 0x0ac0, 0xc03c, 0x0aff, 0xc03c, 0x21, 0 - .dw 0x0b40, 0xc03c, 0x0b7f, 0xc03c, 0x21, 0 - .dw 0x0bc0, 0xc03c, 0x0bff, 0xc03c, 0x21, 0 - .dw 0x0c40, 0xc03c, 0x0c7f, 0xc03c, 0x21, 0 - .dw 0x0cc0, 0xc03c, 0x0cff, 0xc03c, 0x21, 0 - .dw 0x0d40, 0xc03c, 0x0d7f, 0xc03c, 0x21, 0 - .dw 0x0dc0, 0xc03c, 0x0dff, 0xc03c, 0x21, 0 - .dw 0x0e40, 0xc03c, 0x0e7f, 0xc03c, 0x21, 0 - .dw 0x0ec0, 0xc03c, 0x0eff, 0xc03c, 0x21, 0 - .dw 0x0f40, 0xc03c, 0x0f7f, 0xc03c, 0x21, 0 - .dw 0x0fc0, 0xc03c, 0x0fff, 0xc03c, 0x21, 0 - .dw 0x1040, 0xc03c, 0x107f, 0xc03c, 0x21, 0 - .dw 0x10c0, 0xc03c, 0x10ff, 0xc03c, 0x21, 0 - .dw 0x1140, 0xc03c, 0x117f, 0xc03c, 0x21, 0 - .dw 0x11c0, 0xc03c, 0x11ff, 0xc03c, 0x21, 0 - .dw 0x1240, 0xc03c, 0x127f, 0xc03c, 0x21, 0 - .dw 0x12c0, 0xc03c, 0x12ff, 0xc03c, 0x21, 0 - .dw 0x1340, 0xc03c, 0x137f, 0xc03c, 0x21, 0 - .dw 0x13c0, 0xc03c, 0x13ff, 0xc03c, 0x21, 0 - .dw 0x1440, 0xc03c, 0x147f, 0xc03c, 0x21, 0 - .dw 0x14c0, 0xc03c, 0x14ff, 0xc03c, 0x21, 0 - .dw 0x1540, 0xc03c, 0x157f, 0xc03c, 0x21, 0 - .dw 0x15c0, 0xc03c, 0x15ff, 0xc03c, 0x21, 0 - .dw 0x1640, 0xc03c, 0x167f, 0xc03c, 0x21, 0 - .dw 0x16c0, 0xc03c, 0x16ff, 0xc03c, 0x21, 0 - .dw 0x1740, 0xc03c, 0x177f, 0xc03c, 0x21, 0 - .dw 0x17c0, 0xc03c, 0x17ff, 0xc03c, 0x21, 0 - .dw 0x1840, 0xc03c, 0x187f, 0xc03c, 0x21, 0 - .dw 0x18c0, 0xc03c, 0x18ff, 0xc03c, 0x21, 0 - .dw 0x1940, 0xc03c, 0x197f, 0xc03c, 0x21, 0 - .dw 0x19c0, 0xc03c, 0x1fff, 0xc03c, 0x21, 0 - .dw 0x2040, 0xc03c, 0x207f, 0xc03c, 0x21, 0 - .dw 0x20c0, 0xc03c, 0x20ff, 0xc03c, 0x21, 0 - .dw 0x2140, 0xc03c, 0x217f, 0xc03c, 0x21, 0 - .dw 0x21c0, 0xc03c, 0x21ff, 0xc03c, 0x21, 0 - .dw 0x2240, 0xc03c, 0x227f, 0xc03c, 0x21, 0 - .dw 0x22c0, 0xc03c, 0x22ff, 0xc03c, 0x21, 0 - .dw 0x2340, 0xc03c, 0x237f, 0xc03c, 0x21, 0 - .dw 0x23c0, 0xc03c, 0x23ff, 0xc03c, 0x21, 0 - .dw 0x2440, 0xc03c, 0x247f, 0xc03c, 0x21, 0 - .dw 0x24c0, 0xc03c, 0x24ff, 0xc03c, 0x21, 0 - .dw 0x2540, 0xc03c, 0x257f, 0xc03c, 0x21, 0 - .dw 0x25c0, 0xc03c, 0x25ff, 0xc03c, 0x21, 0 - .dw 0x2640, 0xc03c, 0x267f, 0xc03c, 0x21, 0 - .dw 0x26c0, 0xc03c, 0x26ff, 0xc03c, 0x21, 0 - .dw 0x2740, 0xc03c, 0x277f, 0xc03c, 0x21, 0 - .dw 0x27c0, 0xc03c, 0x27ff, 0xc03c, 0x21, 0 - .dw 0x2840, 0xc03c, 0x287f, 0xc03c, 0x21, 0 - .dw 0x28c0, 0xc03c, 0x28ff, 0xc03c, 0x21, 0 - .dw 0x2940, 0xc03c, 0x297f, 0xc03c, 0x21, 0 - .dw 0x29c0, 0xc03c, 0x29ff, 0xc03c, 0x21, 0 - .dw 0x2a40, 0xc03c, 0x2a7f, 0xc03c, 0x21, 0 - .dw 0x2ac0, 0xc03c, 0x2aff, 0xc03c, 0x21, 0 - .dw 0x2b40, 0xc03c, 0x2b7f, 0xc03c, 0x21, 0 - .dw 0x2bc0, 0xc03c, 0x2bff, 0xc03c, 0x21, 0 - .dw 0x2c40, 0xc03c, 0x2c7f, 0xc03c, 0x21, 0 - .dw 0x2cc0, 0xc03c, 0x2cff, 0xc03c, 0x21, 0 - .dw 0x2d40, 0xc03c, 0x2d7f, 0xc03c, 0x21, 0 - .dw 0x2dc0, 0xc03c, 0x2dff, 0xc03c, 0x21, 0 - .dw 0x2e40, 0xc03c, 0x2e7f, 0xc03c, 0x21, 0 - .dw 0x2ec0, 0xc03c, 0x2eff, 0xc03c, 0x21, 0 - .dw 0x2f40, 0xc03c, 0x2f7f, 0xc03c, 0x21, 0 - .dw 0x2fc0, 0xc03c, 0x2fff, 0xc03c, 0x21, 0 - .dw 0x3040, 0xc03c, 0x307f, 0xc03c, 0x21, 0 - .dw 0x30c0, 0xc03c, 0x30ff, 0xc03c, 0x21, 0 - .dw 0x3140, 0xc03c, 0x317f, 0xc03c, 0x21, 0 - .dw 0x31c0, 0xc03c, 0x31ff, 0xc03c, 0x21, 0 - .dw 0x3240, 0xc03c, 0x327f, 0xc03c, 0x21, 0 - .dw 0x32c0, 0xc03c, 0x32ff, 0xc03c, 0x21, 0 - .dw 0x3340, 0xc03c, 0x337f, 0xc03c, 0x21, 0 - .dw 0x33c0, 0xc03c, 0x33ff, 0xc03c, 0x21, 0 - .dw 0x3440, 0xc03c, 0x347f, 0xc03c, 0x21, 0 - .dw 0x34c0, 0xc03c, 0x34ff, 0xc03c, 0x21, 0 - .dw 0x3540, 0xc03c, 0x357f, 0xc03c, 0x21, 0 - .dw 0x35c0, 0xc03c, 0x35ff, 0xc03c, 0x21, 0 - .dw 0x3640, 0xc03c, 0x367f, 0xc03c, 0x21, 0 - .dw 0x36c0, 0xc03c, 0x36ff, 0xc03c, 0x21, 0 - .dw 0x3740, 0xc03c, 0x377f, 0xc03c, 0x21, 0 - .dw 0x37c0, 0xc03c, 0x37ff, 0xc03c, 0x21, 0 - .dw 0x3840, 0xc03c, 0x387f, 0xc03c, 0x21, 0 - .dw 0x38c0, 0xc03c, 0x38ff, 0xc03c, 0x21, 0 - .dw 0x3940, 0xc03c, 0x397f, 0xc03c, 0x21, 0 - .dw 0x39c0, 0xc03c, 0x3fff, 0xc03c, 0x21, 0 - .dw 0x4040, 0xc03c, 0x407f, 0xc03c, 0x21, 0 - .dw 0x40c0, 0xc03c, 0x40ff, 0xc03c, 0x21, 0 - .dw 0x4140, 0xc03c, 0x417f, 0xc03c, 0x21, 0 - .dw 0x41c0, 0xc03c, 0x41ff, 0xc03c, 0x21, 0 - .dw 0x4240, 0xc03c, 0x427f, 0xc03c, 0x21, 0 - .dw 0x42c0, 0xc03c, 0x42ff, 0xc03c, 0x21, 0 - .dw 0x4340, 0xc03c, 0x437f, 0xc03c, 0x21, 0 - .dw 0x43c0, 0xc03c, 0x43ff, 0xc03c, 0x21, 0 - .dw 0x4440, 0xc03c, 0x447f, 0xc03c, 0x21, 0 - .dw 0x44c0, 0xc03c, 0x44ff, 0xc03c, 0x21, 0 - .dw 0x4540, 0xc03c, 0x457f, 0xc03c, 0x21, 0 - .dw 0x45c0, 0xc03c, 0x45ff, 0xc03c, 0x21, 0 - .dw 0x4640, 0xc03c, 0x467f, 0xc03c, 0x21, 0 - .dw 0x46c0, 0xc03c, 0x46ff, 0xc03c, 0x21, 0 - .dw 0x4740, 0xc03c, 0x477f, 0xc03c, 0x21, 0 - .dw 0x47c0, 0xc03c, 0x47ff, 0xc03c, 0x21, 0 - .dw 0x4840, 0xc03c, 0x487f, 0xc03c, 0x21, 0 - .dw 0x48c0, 0xc03c, 0x48ff, 0xc03c, 0x21, 0 - .dw 0x4940, 0xc03c, 0x497f, 0xc03c, 0x21, 0 - .dw 0x49c0, 0xc03c, 0x49ff, 0xc03c, 0x21, 0 - .dw 0x4a40, 0xc03c, 0x4a7f, 0xc03c, 0x21, 0 - .dw 0x4ac0, 0xc03c, 0x4aff, 0xc03c, 0x21, 0 - .dw 0x4b40, 0xc03c, 0x4b7f, 0xc03c, 0x21, 0 - .dw 0x4bc0, 0xc03c, 0x4bff, 0xc03c, 0x21, 0 - .dw 0x4c40, 0xc03c, 0x4c7f, 0xc03c, 0x21, 0 - .dw 0x4cc0, 0xc03c, 0x4cff, 0xc03c, 0x21, 0 - .dw 0x4d40, 0xc03c, 0x4d7f, 0xc03c, 0x21, 0 - .dw 0x4dc0, 0xc03c, 0x4dff, 0xc03c, 0x21, 0 - .dw 0x4e40, 0xc03c, 0x4e7f, 0xc03c, 0x21, 0 - .dw 0x4ec0, 0xc03c, 0x4eff, 0xc03c, 0x21, 0 - .dw 0x4f40, 0xc03c, 0x4f7f, 0xc03c, 0x21, 0 - .dw 0x4fc0, 0xc03c, 0x4fff, 0xc03c, 0x21, 0 - .dw 0x5040, 0xc03c, 0x507f, 0xc03c, 0x21, 0 - .dw 0x50c0, 0xc03c, 0x50ff, 0xc03c, 0x21, 0 - .dw 0x5140, 0xc03c, 0x517f, 0xc03c, 0x21, 0 - .dw 0x51c0, 0xc03c, 0x51ff, 0xc03c, 0x21, 0 - .dw 0x5240, 0xc03c, 0x527f, 0xc03c, 0x21, 0 - .dw 0x52c0, 0xc03c, 0x52ff, 0xc03c, 0x21, 0 - .dw 0x5340, 0xc03c, 0x537f, 0xc03c, 0x21, 0 - .dw 0x53c0, 0xc03c, 0x53ff, 0xc03c, 0x21, 0 - .dw 0x5440, 0xc03c, 0x547f, 0xc03c, 0x21, 0 - .dw 0x54c0, 0xc03c, 0x54ff, 0xc03c, 0x21, 0 - .dw 0x5540, 0xc03c, 0x557f, 0xc03c, 0x21, 0 - .dw 0x55c0, 0xc03c, 0x55ff, 0xc03c, 0x21, 0 - .dw 0x5640, 0xc03c, 0x567f, 0xc03c, 0x21, 0 - .dw 0x56c0, 0xc03c, 0x56ff, 0xc03c, 0x21, 0 - .dw 0x5740, 0xc03c, 0x577f, 0xc03c, 0x21, 0 - .dw 0x57c0, 0xc03c, 0x57ff, 0xc03c, 0x21, 0 - .dw 0x5840, 0xc03c, 0x587f, 0xc03c, 0x21, 0 - .dw 0x58c0, 0xc03c, 0x58ff, 0xc03c, 0x21, 0 - .dw 0x5940, 0xc03c, 0x597f, 0xc03c, 0x21, 0 - .dw 0x59c0, 0xc03c, 0x5fff, 0xc03c, 0x21, 0 - .dw 0x6040, 0xc03c, 0x607f, 0xc03c, 0x21, 0 - .dw 0x60c0, 0xc03c, 0x60ff, 0xc03c, 0x21, 0 - .dw 0x6140, 0xc03c, 0x617f, 0xc03c, 0x21, 0 - .dw 0x61c0, 0xc03c, 0x61ff, 0xc03c, 0x21, 0 - .dw 0x6240, 0xc03c, 0x627f, 0xc03c, 0x21, 0 - .dw 0x62c0, 0xc03c, 0x62ff, 0xc03c, 0x21, 0 - .dw 0x6340, 0xc03c, 0x637f, 0xc03c, 0x21, 0 - .dw 0x63c0, 0xc03c, 0x63ff, 0xc03c, 0x21, 0 - .dw 0x6440, 0xc03c, 0x647f, 0xc03c, 0x21, 0 - .dw 0x64c0, 0xc03c, 0x64ff, 0xc03c, 0x21, 0 - .dw 0x6540, 0xc03c, 0x657f, 0xc03c, 0x21, 0 - .dw 0x65c0, 0xc03c, 0x65ff, 0xc03c, 0x21, 0 - .dw 0x6640, 0xc03c, 0x667f, 0xc03c, 0x21, 0 - .dw 0x66c0, 0xc03c, 0x66ff, 0xc03c, 0x21, 0 - .dw 0x6740, 0xc03c, 0x677f, 0xc03c, 0x21, 0 - .dw 0x67c0, 0xc03c, 0x67ff, 0xc03c, 0x21, 0 - .dw 0x6840, 0xc03c, 0x687f, 0xc03c, 0x21, 0 - .dw 0x68c0, 0xc03c, 0x68ff, 0xc03c, 0x21, 0 - .dw 0x6940, 0xc03c, 0x697f, 0xc03c, 0x21, 0 - .dw 0x69c0, 0xc03c, 0x69ff, 0xc03c, 0x21, 0 - .dw 0x6a40, 0xc03c, 0x6a7f, 0xc03c, 0x21, 0 - .dw 0x6ac0, 0xc03c, 0x6aff, 0xc03c, 0x21, 0 - .dw 0x6b40, 0xc03c, 0x6b7f, 0xc03c, 0x21, 0 - .dw 0x6bc0, 0xc03c, 0x6bff, 0xc03c, 0x21, 0 - .dw 0x6c40, 0xc03c, 0x6c7f, 0xc03c, 0x21, 0 - .dw 0x6cc0, 0xc03c, 0x6cff, 0xc03c, 0x21, 0 - .dw 0x6d40, 0xc03c, 0x6d7f, 0xc03c, 0x21, 0 - .dw 0x6dc0, 0xc03c, 0x6dff, 0xc03c, 0x21, 0 - .dw 0x6e40, 0xc03c, 0x6e7f, 0xc03c, 0x21, 0 - .dw 0x6ec0, 0xc03c, 0x6eff, 0xc03c, 0x21, 0 - .dw 0x6f40, 0xc03c, 0x6f7f, 0xc03c, 0x21, 0 - .dw 0x6fc0, 0xc03c, 0x6fff, 0xc03c, 0x21, 0 - .dw 0x7040, 0xc03c, 0x707f, 0xc03c, 0x21, 0 - .dw 0x70c0, 0xc03c, 0x70ff, 0xc03c, 0x21, 0 - .dw 0x7140, 0xc03c, 0x717f, 0xc03c, 0x21, 0 - .dw 0x71c0, 0xc03c, 0x71ff, 0xc03c, 0x21, 0 - .dw 0x7240, 0xc03c, 0x727f, 0xc03c, 0x21, 0 - .dw 0x72c0, 0xc03c, 0x72ff, 0xc03c, 0x21, 0 - .dw 0x7340, 0xc03c, 0x737f, 0xc03c, 0x21, 0 - .dw 0x73c0, 0xc03c, 0x73ff, 0xc03c, 0x21, 0 - .dw 0x7440, 0xc03c, 0x747f, 0xc03c, 0x21, 0 - .dw 0x74c0, 0xc03c, 0x74ff, 0xc03c, 0x21, 0 - .dw 0x7540, 0xc03c, 0x757f, 0xc03c, 0x21, 0 - .dw 0x75c0, 0xc03c, 0x75ff, 0xc03c, 0x21, 0 - .dw 0x7640, 0xc03c, 0x767f, 0xc03c, 0x21, 0 - .dw 0x76c0, 0xc03c, 0x76ff, 0xc03c, 0x21, 0 - .dw 0x7740, 0xc03c, 0x777f, 0xc03c, 0x21, 0 - .dw 0x77c0, 0xc03c, 0x77ff, 0xc03c, 0x21, 0 - .dw 0x7840, 0xc03c, 0x787f, 0xc03c, 0x21, 0 - .dw 0x78c0, 0xc03c, 0x78ff, 0xc03c, 0x21, 0 - .dw 0x7940, 0xc03c, 0x797f, 0xc03c, 0x21, 0 - .dw 0x79c0, 0xc03c, 0x7fff, 0xc03c, 0x21, 0 - .dw 0x8040, 0xc03c, 0x807f, 0xc03c, 0x21, 0 - .dw 0x80c0, 0xc03c, 0x80ff, 0xc03c, 0x21, 0 - .dw 0x8140, 0xc03c, 0x817f, 0xc03c, 0x21, 0 - .dw 0x81c0, 0xc03c, 0x81ff, 0xc03c, 0x21, 0 - .dw 0x8240, 0xc03c, 0x827f, 0xc03c, 0x21, 0 - .dw 0x82c0, 0xc03c, 0x82ff, 0xc03c, 0x21, 0 - .dw 0x8340, 0xc03c, 0x837f, 0xc03c, 0x21, 0 - .dw 0x83c0, 0xc03c, 0x83ff, 0xc03c, 0x21, 0 - .dw 0x8440, 0xc03c, 0x847f, 0xc03c, 0x21, 0 - .dw 0x84c0, 0xc03c, 0x84ff, 0xc03c, 0x21, 0 - .dw 0x8540, 0xc03c, 0x857f, 0xc03c, 0x21, 0 - .dw 0x85c0, 0xc03c, 0x85ff, 0xc03c, 0x21, 0 - .dw 0x8640, 0xc03c, 0x867f, 0xc03c, 0x21, 0 - .dw 0x86c0, 0xc03c, 0x86ff, 0xc03c, 0x21, 0 - .dw 0x8740, 0xc03c, 0x877f, 0xc03c, 0x21, 0 - .dw 0x87c0, 0xc03c, 0x87ff, 0xc03c, 0x21, 0 - .dw 0x8840, 0xc03c, 0x887f, 0xc03c, 0x21, 0 - .dw 0x88c0, 0xc03c, 0x88ff, 0xc03c, 0x21, 0 - .dw 0x8940, 0xc03c, 0x897f, 0xc03c, 0x21, 0 - .dw 0x89c0, 0xc03c, 0x89ff, 0xc03c, 0x21, 0 - .dw 0x8a40, 0xc03c, 0x8a7f, 0xc03c, 0x21, 0 - .dw 0x8ac0, 0xc03c, 0x8aff, 0xc03c, 0x21, 0 - .dw 0x8b40, 0xc03c, 0x8b7f, 0xc03c, 0x21, 0 - .dw 0x8bc0, 0xc03c, 0x8bff, 0xc03c, 0x21, 0 - .dw 0x8c40, 0xc03c, 0x8c7f, 0xc03c, 0x21, 0 - .dw 0x8cc0, 0xc03c, 0x8cff, 0xc03c, 0x21, 0 - .dw 0x8d40, 0xc03c, 0x8d7f, 0xc03c, 0x21, 0 - .dw 0x8dc0, 0xc03c, 0x8dff, 0xc03c, 0x21, 0 - .dw 0x8e40, 0xc03c, 0x8e7f, 0xc03c, 0x21, 0 - .dw 0x8ec0, 0xc03c, 0x8eff, 0xc03c, 0x21, 0 - .dw 0x8f40, 0xc03c, 0x8f7f, 0xc03c, 0x21, 0 - .dw 0x8fc0, 0xc03c, 0x8fff, 0xc03c, 0x21, 0 - .dw 0x9040, 0xc03c, 0x907f, 0xc03c, 0x21, 0 - .dw 0x90c0, 0xc03c, 0x90ff, 0xc03c, 0x21, 0 - .dw 0x9140, 0xc03c, 0x917f, 0xc03c, 0x21, 0 - .dw 0x91c0, 0xc03c, 0x91ff, 0xc03c, 0x21, 0 - .dw 0x9240, 0xc03c, 0x927f, 0xc03c, 0x21, 0 - .dw 0x92c0, 0xc03c, 0x92ff, 0xc03c, 0x21, 0 - .dw 0x9340, 0xc03c, 0x937f, 0xc03c, 0x21, 0 - .dw 0x93c0, 0xc03c, 0x93ff, 0xc03c, 0x21, 0 - .dw 0x9440, 0xc03c, 0x947f, 0xc03c, 0x21, 0 - .dw 0x94c0, 0xc03c, 0x94ff, 0xc03c, 0x21, 0 - .dw 0x9540, 0xc03c, 0x957f, 0xc03c, 0x21, 0 - .dw 0x95c0, 0xc03c, 0x95ff, 0xc03c, 0x21, 0 - .dw 0x9640, 0xc03c, 0x967f, 0xc03c, 0x21, 0 - .dw 0x96c0, 0xc03c, 0x96ff, 0xc03c, 0x21, 0 - .dw 0x9740, 0xc03c, 0x977f, 0xc03c, 0x21, 0 - .dw 0x97c0, 0xc03c, 0x97ff, 0xc03c, 0x21, 0 - .dw 0x9840, 0xc03c, 0x987f, 0xc03c, 0x21, 0 - .dw 0x98c0, 0xc03c, 0x98ff, 0xc03c, 0x21, 0 - .dw 0x9940, 0xc03c, 0x997f, 0xc03c, 0x21, 0 - .dw 0x99c0, 0xc03c, 0x9fff, 0xc03c, 0x21, 0 - .dw 0xa040, 0xc03c, 0xa07f, 0xc03c, 0x21, 0 - .dw 0xa0c0, 0xc03c, 0xa0ff, 0xc03c, 0x21, 0 - .dw 0xa140, 0xc03c, 0xa17f, 0xc03c, 0x21, 0 - .dw 0xa1c0, 0xc03c, 0xa1ff, 0xc03c, 0x21, 0 - .dw 0xa240, 0xc03c, 0xa27f, 0xc03c, 0x21, 0 - .dw 0xa2c0, 0xc03c, 0xa2ff, 0xc03c, 0x21, 0 - .dw 0xa340, 0xc03c, 0xa37f, 0xc03c, 0x21, 0 - .dw 0xa3c0, 0xc03c, 0xa3ff, 0xc03c, 0x21, 0 - .dw 0xa440, 0xc03c, 0xa47f, 0xc03c, 0x21, 0 - .dw 0xa4c0, 0xc03c, 0xa4ff, 0xc03c, 0x21, 0 - .dw 0xa540, 0xc03c, 0xa57f, 0xc03c, 0x21, 0 - .dw 0xa5c0, 0xc03c, 0xa5ff, 0xc03c, 0x21, 0 - .dw 0xa640, 0xc03c, 0xa67f, 0xc03c, 0x21, 0 - .dw 0xa6c0, 0xc03c, 0xa6ff, 0xc03c, 0x21, 0 - .dw 0xa740, 0xc03c, 0xa77f, 0xc03c, 0x21, 0 - .dw 0xa7c0, 0xc03c, 0xa7ff, 0xc03c, 0x21, 0 - .dw 0xa840, 0xc03c, 0xa87f, 0xc03c, 0x21, 0 - .dw 0xa8c0, 0xc03c, 0xa8ff, 0xc03c, 0x21, 0 - .dw 0xa940, 0xc03c, 0xa97f, 0xc03c, 0x21, 0 - .dw 0xa9c0, 0xc03c, 0xa9ff, 0xc03c, 0x21, 0 - .dw 0xaa40, 0xc03c, 0xaa7f, 0xc03c, 0x21, 0 - .dw 0xaac0, 0xc03c, 0xaaff, 0xc03c, 0x21, 0 - .dw 0xab40, 0xc03c, 0xab7f, 0xc03c, 0x21, 0 - .dw 0xabc0, 0xc03c, 0xabff, 0xc03c, 0x21, 0 - .dw 0xac40, 0xc03c, 0xac7f, 0xc03c, 0x21, 0 - .dw 0xacc0, 0xc03c, 0xacff, 0xc03c, 0x21, 0 - .dw 0xad40, 0xc03c, 0xad7f, 0xc03c, 0x21, 0 - .dw 0xadc0, 0xc03c, 0xadff, 0xc03c, 0x21, 0 - .dw 0xae40, 0xc03c, 0xae7f, 0xc03c, 0x21, 0 - .dw 0xaec0, 0xc03c, 0xaeff, 0xc03c, 0x21, 0 - .dw 0xaf40, 0xc03c, 0xaf7f, 0xc03c, 0x21, 0 - .dw 0xafc0, 0xc03c, 0xafff, 0xc03c, 0x21, 0 - .dw 0xb040, 0xc03c, 0xb07f, 0xc03c, 0x21, 0 - .dw 0xb0c0, 0xc03c, 0xb0ff, 0xc03c, 0x21, 0 - .dw 0xb140, 0xc03c, 0xb17f, 0xc03c, 0x21, 0 - .dw 0xb1c0, 0xc03c, 0xb1ff, 0xc03c, 0x21, 0 - .dw 0xb240, 0xc03c, 0xb27f, 0xc03c, 0x21, 0 - .dw 0xb2c0, 0xc03c, 0xb2ff, 0xc03c, 0x21, 0 - .dw 0xb340, 0xc03c, 0xb37f, 0xc03c, 0x21, 0 - .dw 0xb3c0, 0xc03c, 0xb3ff, 0xc03c, 0x21, 0 - .dw 0xb440, 0xc03c, 0xb47f, 0xc03c, 0x21, 0 - .dw 0xb4c0, 0xc03c, 0xb4ff, 0xc03c, 0x21, 0 - .dw 0xb540, 0xc03c, 0xb57f, 0xc03c, 0x21, 0 - .dw 0xb5c0, 0xc03c, 0xb5ff, 0xc03c, 0x21, 0 - .dw 0xb640, 0xc03c, 0xb67f, 0xc03c, 0x21, 0 - .dw 0xb6c0, 0xc03c, 0xb6ff, 0xc03c, 0x21, 0 - .dw 0xb740, 0xc03c, 0xb77f, 0xc03c, 0x21, 0 - .dw 0xb7c0, 0xc03c, 0xb7ff, 0xc03c, 0x21, 0 - .dw 0xb840, 0xc03c, 0xb87f, 0xc03c, 0x21, 0 - .dw 0xb8c0, 0xc03c, 0xb8ff, 0xc03c, 0x21, 0 - .dw 0xb940, 0xc03c, 0xb97f, 0xc03c, 0x21, 0 - .dw 0xb9c0, 0xc03c, 0xbfff, 0xc03c, 0x21, 0 - .dw 0xc040, 0xc03c, 0xc07f, 0xc03c, 0x21, 0 - .dw 0xc0c0, 0xc03c, 0xc0ff, 0xc03c, 0x21, 0 - .dw 0xc140, 0xc03c, 0xc17f, 0xc03c, 0x21, 0 - .dw 0xc1c0, 0xc03c, 0xc1ff, 0xc03c, 0x21, 0 - .dw 0xc240, 0xc03c, 0xc27f, 0xc03c, 0x21, 0 - .dw 0xc2c0, 0xc03c, 0xc2ff, 0xc03c, 0x21, 0 - .dw 0xc340, 0xc03c, 0xc37f, 0xc03c, 0x21, 0 - .dw 0xc3c0, 0xc03c, 0xc3ff, 0xc03c, 0x21, 0 - .dw 0xc440, 0xc03c, 0xc47f, 0xc03c, 0x21, 0 - .dw 0xc4c0, 0xc03c, 0xc4ff, 0xc03c, 0x21, 0 - .dw 0xc540, 0xc03c, 0xc57f, 0xc03c, 0x21, 0 - .dw 0xc5c0, 0xc03c, 0xc5ff, 0xc03c, 0x21, 0 - .dw 0xc640, 0xc03c, 0xc67f, 0xc03c, 0x21, 0 - .dw 0xc6c0, 0xc03c, 0xc6ff, 0xc03c, 0x21, 0 - .dw 0xc740, 0xc03c, 0xc77f, 0xc03c, 0x21, 0 - .dw 0xc7c0, 0xc03c, 0xc7ff, 0xc03c, 0x21, 0 - .dw 0xc840, 0xc03c, 0xc87f, 0xc03c, 0x21, 0 - .dw 0xc8c0, 0xc03c, 0xc8ff, 0xc03c, 0x21, 0 - .dw 0xc940, 0xc03c, 0xc97f, 0xc03c, 0x21, 0 - .dw 0xc9c0, 0xc03c, 0xc9ff, 0xc03c, 0x21, 0 - .dw 0xca40, 0xc03c, 0xca7f, 0xc03c, 0x21, 0 - .dw 0xcac0, 0xc03c, 0xcaff, 0xc03c, 0x21, 0 - .dw 0xcb40, 0xc03c, 0xcb7f, 0xc03c, 0x21, 0 - .dw 0xcbc0, 0xc03c, 0xcbff, 0xc03c, 0x21, 0 - .dw 0xcc40, 0xc03c, 0xcc7f, 0xc03c, 0x21, 0 - .dw 0xccc0, 0xc03c, 0xccff, 0xc03c, 0x21, 0 - .dw 0xcd40, 0xc03c, 0xcd7f, 0xc03c, 0x21, 0 - .dw 0xcdc0, 0xc03c, 0xcdff, 0xc03c, 0x21, 0 - .dw 0xce40, 0xc03c, 0xce7f, 0xc03c, 0x21, 0 - .dw 0xcec0, 0xc03c, 0xceff, 0xc03c, 0x21, 0 - .dw 0xcf40, 0xc03c, 0xcf7f, 0xc03c, 0x21, 0 - .dw 0xcfc0, 0xc03c, 0xcfff, 0xc03c, 0x21, 0 - .dw 0xd040, 0xc03c, 0xd07f, 0xc03c, 0x21, 0 - .dw 0xd0c0, 0xc03c, 0xd0ff, 0xc03c, 0x21, 0 - .dw 0xd140, 0xc03c, 0xd17f, 0xc03c, 0x21, 0 - .dw 0xd1c0, 0xc03c, 0xd1ff, 0xc03c, 0x21, 0 - .dw 0xd240, 0xc03c, 0xd27f, 0xc03c, 0x21, 0 - .dw 0xd2c0, 0xc03c, 0xd2ff, 0xc03c, 0x21, 0 - .dw 0xd340, 0xc03c, 0xd37f, 0xc03c, 0x21, 0 - .dw 0xd3c0, 0xc03c, 0xd3ff, 0xc03c, 0x21, 0 - .dw 0xd440, 0xc03c, 0xd47f, 0xc03c, 0x21, 0 - .dw 0xd4c0, 0xc03c, 0xd4ff, 0xc03c, 0x21, 0 - .dw 0xd540, 0xc03c, 0xd57f, 0xc03c, 0x21, 0 - .dw 0xd5c0, 0xc03c, 0xd5ff, 0xc03c, 0x21, 0 - .dw 0xd640, 0xc03c, 0xd67f, 0xc03c, 0x21, 0 - .dw 0xd6c0, 0xc03c, 0xd6ff, 0xc03c, 0x21, 0 - .dw 0xd740, 0xc03c, 0xd77f, 0xc03c, 0x21, 0 - .dw 0xd7c0, 0xc03c, 0xd7ff, 0xc03c, 0x21, 0 - .dw 0xd840, 0xc03c, 0xd87f, 0xc03c, 0x21, 0 - .dw 0xd8c0, 0xc03c, 0xd8ff, 0xc03c, 0x21, 0 - .dw 0xd940, 0xc03c, 0xd97f, 0xc03c, 0x21, 0 - .dw 0xd9c0, 0xc03c, 0xdfff, 0xc03c, 0x21, 0 - .dw 0xe040, 0xc03c, 0xe07f, 0xc03c, 0x21, 0 - .dw 0xe0c0, 0xc03c, 0xe0ff, 0xc03c, 0x21, 0 - .dw 0xe140, 0xc03c, 0xe17f, 0xc03c, 0x21, 0 - .dw 0xe1c0, 0xc03c, 0xe1ff, 0xc03c, 0x21, 0 - .dw 0xe240, 0xc03c, 0xe27f, 0xc03c, 0x21, 0 - .dw 0xe2c0, 0xc03c, 0xe2ff, 0xc03c, 0x21, 0 - .dw 0xe340, 0xc03c, 0xe37f, 0xc03c, 0x21, 0 - .dw 0xe3c0, 0xc03c, 0xe3ff, 0xc03c, 0x21, 0 - .dw 0xe440, 0xc03c, 0xe47f, 0xc03c, 0x21, 0 - .dw 0xe4c0, 0xc03c, 0xe4ff, 0xc03c, 0x21, 0 - .dw 0xe540, 0xc03c, 0xe57f, 0xc03c, 0x21, 0 - .dw 0xe5c0, 0xc03c, 0xe5ff, 0xc03c, 0x21, 0 - .dw 0xe640, 0xc03c, 0xe67f, 0xc03c, 0x21, 0 - .dw 0xe6c0, 0xc03c, 0xe6ff, 0xc03c, 0x21, 0 - .dw 0xe740, 0xc03c, 0xe77f, 0xc03c, 0x21, 0 - .dw 0xe7c0, 0xc03c, 0xe7ff, 0xc03c, 0x21, 0 - .dw 0xe840, 0xc03c, 0xe87f, 0xc03c, 0x21, 0 - .dw 0xe8c0, 0xc03c, 0xe8ff, 0xc03c, 0x21, 0 - .dw 0xe940, 0xc03c, 0xe97f, 0xc03c, 0x21, 0 - .dw 0xe9c0, 0xc03c, 0xe9ff, 0xc03c, 0x21, 0 - .dw 0xea40, 0xc03c, 0xea7f, 0xc03c, 0x21, 0 - .dw 0xeac0, 0xc03c, 0xeaff, 0xc03c, 0x21, 0 - .dw 0xeb40, 0xc03c, 0xeb7f, 0xc03c, 0x21, 0 - .dw 0xebc0, 0xc03c, 0xebff, 0xc03c, 0x21, 0 - .dw 0xec40, 0xc03c, 0xec7f, 0xc03c, 0x21, 0 - .dw 0xecc0, 0xc03c, 0xecff, 0xc03c, 0x21, 0 - .dw 0xed40, 0xc03c, 0xed7f, 0xc03c, 0x21, 0 - .dw 0xedc0, 0xc03c, 0xedff, 0xc03c, 0x21, 0 - .dw 0xee40, 0xc03c, 0xee7f, 0xc03c, 0x21, 0 - .dw 0xeec0, 0xc03c, 0xeeff, 0xc03c, 0x21, 0 - .dw 0xef40, 0xc03c, 0xef7f, 0xc03c, 0x21, 0 - .dw 0xefc0, 0xc03c, 0xefff, 0xc03c, 0x21, 0 - .dw 0xf040, 0xc03c, 0xf07f, 0xc03c, 0x21, 0 - .dw 0xf0c0, 0xc03c, 0xf0ff, 0xc03c, 0x21, 0 - .dw 0xf140, 0xc03c, 0xf17f, 0xc03c, 0x21, 0 - .dw 0xf1c0, 0xc03c, 0xf1ff, 0xc03c, 0x21, 0 - .dw 0xf240, 0xc03c, 0xf27f, 0xc03c, 0x21, 0 - .dw 0xf2c0, 0xc03c, 0xf2ff, 0xc03c, 0x21, 0 - .dw 0xf340, 0xc03c, 0xf37f, 0xc03c, 0x21, 0 - .dw 0xf3c0, 0xc03c, 0xf3ff, 0xc03c, 0x21, 0 - .dw 0xf440, 0xc03c, 0xf47f, 0xc03c, 0x21, 0 - .dw 0xf4c0, 0xc03c, 0xf4ff, 0xc03c, 0x21, 0 - .dw 0xf540, 0xc03c, 0xf57f, 0xc03c, 0x21, 0 - .dw 0xf5c0, 0xc03c, 0xf5ff, 0xc03c, 0x21, 0 - .dw 0xf640, 0xc03c, 0xf67f, 0xc03c, 0x21, 0 - .dw 0xf6c0, 0xc03c, 0xf6ff, 0xc03c, 0x21, 0 - .dw 0xf740, 0xc03c, 0xf77f, 0xc03c, 0x21, 0 - .dw 0xf7c0, 0xc03c, 0xf7ff, 0xc03c, 0x21, 0 - .dw 0xf840, 0xc03c, 0xf87f, 0xc03c, 0x21, 0 - .dw 0xf8c0, 0xc03c, 0xf8ff, 0xc03c, 0x21, 0 - .dw 0xf940, 0xc03c, 0xf97f, 0xc03c, 0x21, 0 - .dw 0xf9c0, 0xc03c, 0xffff, 0xc03c, 0x21, 0 - .dw 0x0040, 0xc03d, 0x007f, 0xc03d, 0x21, 0 - .dw 0x00c0, 0xc03d, 0x00ff, 0xc03d, 0x21, 0 - .dw 0x0140, 0xc03d, 0x017f, 0xc03d, 0x21, 0 - .dw 0x01c0, 0xc03d, 0x01ff, 0xc03d, 0x21, 0 - .dw 0x0240, 0xc03d, 0x027f, 0xc03d, 0x21, 0 - .dw 0x02c0, 0xc03d, 0x02ff, 0xc03d, 0x21, 0 - .dw 0x0340, 0xc03d, 0x037f, 0xc03d, 0x21, 0 - .dw 0x03c0, 0xc03d, 0x03ff, 0xc03d, 0x21, 0 - .dw 0x0440, 0xc03d, 0x047f, 0xc03d, 0x21, 0 - .dw 0x04c0, 0xc03d, 0x04ff, 0xc03d, 0x21, 0 - .dw 0x0540, 0xc03d, 0x057f, 0xc03d, 0x21, 0 - .dw 0x05c0, 0xc03d, 0x05ff, 0xc03d, 0x21, 0 - .dw 0x0640, 0xc03d, 0x067f, 0xc03d, 0x21, 0 - .dw 0x06c0, 0xc03d, 0x06ff, 0xc03d, 0x21, 0 - .dw 0x0740, 0xc03d, 0x077f, 0xc03d, 0x21, 0 - .dw 0x07c0, 0xc03d, 0x07ff, 0xc03d, 0x21, 0 - .dw 0x0840, 0xc03d, 0x087f, 0xc03d, 0x21, 0 - .dw 0x08c0, 0xc03d, 0x08ff, 0xc03d, 0x21, 0 - .dw 0x0940, 0xc03d, 0x097f, 0xc03d, 0x21, 0 - .dw 0x09c0, 0xc03d, 0x09ff, 0xc03d, 0x21, 0 - .dw 0x0a40, 0xc03d, 0x0a7f, 0xc03d, 0x21, 0 - .dw 0x0ac0, 0xc03d, 0x0aff, 0xc03d, 0x21, 0 - .dw 0x0b40, 0xc03d, 0x0b7f, 0xc03d, 0x21, 0 - .dw 0x0bc0, 0xc03d, 0x0bff, 0xc03d, 0x21, 0 - .dw 0x0c40, 0xc03d, 0x0c7f, 0xc03d, 0x21, 0 - .dw 0x0cc0, 0xc03d, 0x0cff, 0xc03d, 0x21, 0 - .dw 0x0d40, 0xc03d, 0x0d7f, 0xc03d, 0x21, 0 - .dw 0x0dc0, 0xc03d, 0x0dff, 0xc03d, 0x21, 0 - .dw 0x0e40, 0xc03d, 0x0e7f, 0xc03d, 0x21, 0 - .dw 0x0ec0, 0xc03d, 0x0eff, 0xc03d, 0x21, 0 - .dw 0x0f40, 0xc03d, 0x0f7f, 0xc03d, 0x21, 0 - .dw 0x0fc0, 0xc03d, 0x0fff, 0xc03d, 0x21, 0 - .dw 0x1040, 0xc03d, 0x107f, 0xc03d, 0x21, 0 - .dw 0x10c0, 0xc03d, 0x10ff, 0xc03d, 0x21, 0 - .dw 0x1140, 0xc03d, 0x117f, 0xc03d, 0x21, 0 - .dw 0x11c0, 0xc03d, 0x11ff, 0xc03d, 0x21, 0 - .dw 0x1240, 0xc03d, 0x127f, 0xc03d, 0x21, 0 - .dw 0x12c0, 0xc03d, 0x12ff, 0xc03d, 0x21, 0 - .dw 0x1340, 0xc03d, 0x137f, 0xc03d, 0x21, 0 - .dw 0x13c0, 0xc03d, 0x13ff, 0xc03d, 0x21, 0 - .dw 0x1440, 0xc03d, 0x147f, 0xc03d, 0x21, 0 - .dw 0x14c0, 0xc03d, 0x14ff, 0xc03d, 0x21, 0 - .dw 0x1540, 0xc03d, 0x157f, 0xc03d, 0x21, 0 - .dw 0x15c0, 0xc03d, 0x15ff, 0xc03d, 0x21, 0 - .dw 0x1640, 0xc03d, 0x167f, 0xc03d, 0x21, 0 - .dw 0x16c0, 0xc03d, 0x16ff, 0xc03d, 0x21, 0 - .dw 0x1740, 0xc03d, 0x177f, 0xc03d, 0x21, 0 - .dw 0x17c0, 0xc03d, 0x17ff, 0xc03d, 0x21, 0 - .dw 0x1840, 0xc03d, 0x187f, 0xc03d, 0x21, 0 - .dw 0x18c0, 0xc03d, 0x18ff, 0xc03d, 0x21, 0 - .dw 0x1940, 0xc03d, 0x197f, 0xc03d, 0x21, 0 - .dw 0x19c0, 0xc03d, 0x1fff, 0xc03d, 0x21, 0 - .dw 0x2040, 0xc03d, 0x207f, 0xc03d, 0x21, 0 - .dw 0x20c0, 0xc03d, 0x20ff, 0xc03d, 0x21, 0 - .dw 0x2140, 0xc03d, 0x217f, 0xc03d, 0x21, 0 - .dw 0x21c0, 0xc03d, 0x21ff, 0xc03d, 0x21, 0 - .dw 0x2240, 0xc03d, 0x227f, 0xc03d, 0x21, 0 - .dw 0x22c0, 0xc03d, 0x22ff, 0xc03d, 0x21, 0 - .dw 0x2340, 0xc03d, 0x237f, 0xc03d, 0x21, 0 - .dw 0x23c0, 0xc03d, 0x23ff, 0xc03d, 0x21, 0 - .dw 0x2440, 0xc03d, 0x247f, 0xc03d, 0x21, 0 - .dw 0x24c0, 0xc03d, 0x24ff, 0xc03d, 0x21, 0 - .dw 0x2540, 0xc03d, 0x257f, 0xc03d, 0x21, 0 - .dw 0x25c0, 0xc03d, 0x25ff, 0xc03d, 0x21, 0 - .dw 0x2640, 0xc03d, 0x267f, 0xc03d, 0x21, 0 - .dw 0x26c0, 0xc03d, 0x26ff, 0xc03d, 0x21, 0 - .dw 0x2740, 0xc03d, 0x277f, 0xc03d, 0x21, 0 - .dw 0x27c0, 0xc03d, 0x27ff, 0xc03d, 0x21, 0 - .dw 0x2840, 0xc03d, 0x287f, 0xc03d, 0x21, 0 - .dw 0x28c0, 0xc03d, 0x28ff, 0xc03d, 0x21, 0 - .dw 0x2940, 0xc03d, 0x297f, 0xc03d, 0x21, 0 - .dw 0x29c0, 0xc03d, 0x29ff, 0xc03d, 0x21, 0 - .dw 0x2a40, 0xc03d, 0x2a7f, 0xc03d, 0x21, 0 - .dw 0x2ac0, 0xc03d, 0x2aff, 0xc03d, 0x21, 0 - .dw 0x2b40, 0xc03d, 0x2b7f, 0xc03d, 0x21, 0 - .dw 0x2bc0, 0xc03d, 0x2bff, 0xc03d, 0x21, 0 - .dw 0x2c40, 0xc03d, 0x2c7f, 0xc03d, 0x21, 0 - .dw 0x2cc0, 0xc03d, 0x2cff, 0xc03d, 0x21, 0 - .dw 0x2d40, 0xc03d, 0x2d7f, 0xc03d, 0x21, 0 - .dw 0x2dc0, 0xc03d, 0x2dff, 0xc03d, 0x21, 0 - .dw 0x2e40, 0xc03d, 0x2e7f, 0xc03d, 0x21, 0 - .dw 0x2ec0, 0xc03d, 0x2eff, 0xc03d, 0x21, 0 - .dw 0x2f40, 0xc03d, 0x2f7f, 0xc03d, 0x21, 0 - .dw 0x2fc0, 0xc03d, 0x2fff, 0xc03d, 0x21, 0 - .dw 0x3040, 0xc03d, 0x307f, 0xc03d, 0x21, 0 - .dw 0x30c0, 0xc03d, 0x30ff, 0xc03d, 0x21, 0 - .dw 0x3140, 0xc03d, 0x317f, 0xc03d, 0x21, 0 - .dw 0x31c0, 0xc03d, 0x31ff, 0xc03d, 0x21, 0 - .dw 0x3240, 0xc03d, 0x327f, 0xc03d, 0x21, 0 - .dw 0x32c0, 0xc03d, 0x32ff, 0xc03d, 0x21, 0 - .dw 0x3340, 0xc03d, 0x337f, 0xc03d, 0x21, 0 - .dw 0x33c0, 0xc03d, 0x33ff, 0xc03d, 0x21, 0 - .dw 0x3440, 0xc03d, 0x347f, 0xc03d, 0x21, 0 - .dw 0x34c0, 0xc03d, 0x34ff, 0xc03d, 0x21, 0 - .dw 0x3540, 0xc03d, 0x357f, 0xc03d, 0x21, 0 - .dw 0x35c0, 0xc03d, 0x35ff, 0xc03d, 0x21, 0 - .dw 0x3640, 0xc03d, 0x367f, 0xc03d, 0x21, 0 - .dw 0x36c0, 0xc03d, 0x36ff, 0xc03d, 0x21, 0 - .dw 0x3740, 0xc03d, 0x377f, 0xc03d, 0x21, 0 - .dw 0x37c0, 0xc03d, 0x37ff, 0xc03d, 0x21, 0 - .dw 0x3840, 0xc03d, 0x387f, 0xc03d, 0x21, 0 - .dw 0x38c0, 0xc03d, 0x38ff, 0xc03d, 0x21, 0 - .dw 0x3940, 0xc03d, 0x397f, 0xc03d, 0x21, 0 - .dw 0x39c0, 0xc03d, 0x3fff, 0xc03d, 0x21, 0 - .dw 0x4040, 0xc03d, 0x407f, 0xc03d, 0x21, 0 - .dw 0x40c0, 0xc03d, 0x40ff, 0xc03d, 0x21, 0 - .dw 0x4140, 0xc03d, 0x417f, 0xc03d, 0x21, 0 - .dw 0x41c0, 0xc03d, 0x41ff, 0xc03d, 0x21, 0 - .dw 0x4240, 0xc03d, 0x427f, 0xc03d, 0x21, 0 - .dw 0x42c0, 0xc03d, 0x42ff, 0xc03d, 0x21, 0 - .dw 0x4340, 0xc03d, 0x437f, 0xc03d, 0x21, 0 - .dw 0x43c0, 0xc03d, 0x43ff, 0xc03d, 0x21, 0 - .dw 0x4440, 0xc03d, 0x447f, 0xc03d, 0x21, 0 - .dw 0x44c0, 0xc03d, 0x44ff, 0xc03d, 0x21, 0 - .dw 0x4540, 0xc03d, 0x457f, 0xc03d, 0x21, 0 - .dw 0x45c0, 0xc03d, 0x45ff, 0xc03d, 0x21, 0 - .dw 0x4640, 0xc03d, 0x467f, 0xc03d, 0x21, 0 - .dw 0x46c0, 0xc03d, 0x46ff, 0xc03d, 0x21, 0 - .dw 0x4740, 0xc03d, 0x477f, 0xc03d, 0x21, 0 - .dw 0x47c0, 0xc03d, 0x47ff, 0xc03d, 0x21, 0 - .dw 0x4840, 0xc03d, 0x487f, 0xc03d, 0x21, 0 - .dw 0x48c0, 0xc03d, 0x48ff, 0xc03d, 0x21, 0 - .dw 0x4940, 0xc03d, 0x497f, 0xc03d, 0x21, 0 - .dw 0x49c0, 0xc03d, 0x49ff, 0xc03d, 0x21, 0 - .dw 0x4a40, 0xc03d, 0x4a7f, 0xc03d, 0x21, 0 - .dw 0x4ac0, 0xc03d, 0x4aff, 0xc03d, 0x21, 0 - .dw 0x4b40, 0xc03d, 0x4b7f, 0xc03d, 0x21, 0 - .dw 0x4bc0, 0xc03d, 0x4bff, 0xc03d, 0x21, 0 - .dw 0x4c40, 0xc03d, 0x4c7f, 0xc03d, 0x21, 0 - .dw 0x4cc0, 0xc03d, 0x4cff, 0xc03d, 0x21, 0 - .dw 0x4d40, 0xc03d, 0x4d7f, 0xc03d, 0x21, 0 - .dw 0x4dc0, 0xc03d, 0x4dff, 0xc03d, 0x21, 0 - .dw 0x4e40, 0xc03d, 0x4e7f, 0xc03d, 0x21, 0 - .dw 0x4ec0, 0xc03d, 0x4eff, 0xc03d, 0x21, 0 - .dw 0x4f40, 0xc03d, 0x4f7f, 0xc03d, 0x21, 0 - .dw 0x4fc0, 0xc03d, 0x4fff, 0xc03d, 0x21, 0 - .dw 0x5040, 0xc03d, 0x507f, 0xc03d, 0x21, 0 - .dw 0x50c0, 0xc03d, 0x50ff, 0xc03d, 0x21, 0 - .dw 0x5140, 0xc03d, 0x517f, 0xc03d, 0x21, 0 - .dw 0x51c0, 0xc03d, 0x51ff, 0xc03d, 0x21, 0 - .dw 0x5240, 0xc03d, 0x527f, 0xc03d, 0x21, 0 - .dw 0x52c0, 0xc03d, 0x52ff, 0xc03d, 0x21, 0 - .dw 0x5340, 0xc03d, 0x537f, 0xc03d, 0x21, 0 - .dw 0x53c0, 0xc03d, 0x53ff, 0xc03d, 0x21, 0 - .dw 0x5440, 0xc03d, 0x547f, 0xc03d, 0x21, 0 - .dw 0x54c0, 0xc03d, 0x54ff, 0xc03d, 0x21, 0 - .dw 0x5540, 0xc03d, 0x557f, 0xc03d, 0x21, 0 - .dw 0x55c0, 0xc03d, 0x55ff, 0xc03d, 0x21, 0 - .dw 0x5640, 0xc03d, 0x567f, 0xc03d, 0x21, 0 - .dw 0x56c0, 0xc03d, 0x56ff, 0xc03d, 0x21, 0 - .dw 0x5740, 0xc03d, 0x577f, 0xc03d, 0x21, 0 - .dw 0x57c0, 0xc03d, 0x57ff, 0xc03d, 0x21, 0 - .dw 0x5840, 0xc03d, 0x587f, 0xc03d, 0x21, 0 - .dw 0x58c0, 0xc03d, 0x58ff, 0xc03d, 0x21, 0 - .dw 0x5940, 0xc03d, 0x597f, 0xc03d, 0x21, 0 - .dw 0x59c0, 0xc03d, 0x5fff, 0xc03d, 0x21, 0 - .dw 0x6040, 0xc03d, 0x607f, 0xc03d, 0x21, 0 - .dw 0x60c0, 0xc03d, 0x60ff, 0xc03d, 0x21, 0 - .dw 0x6140, 0xc03d, 0x617f, 0xc03d, 0x21, 0 - .dw 0x61c0, 0xc03d, 0x61ff, 0xc03d, 0x21, 0 - .dw 0x6240, 0xc03d, 0x627f, 0xc03d, 0x21, 0 - .dw 0x62c0, 0xc03d, 0x62ff, 0xc03d, 0x21, 0 - .dw 0x6340, 0xc03d, 0x637f, 0xc03d, 0x21, 0 - .dw 0x63c0, 0xc03d, 0x63ff, 0xc03d, 0x21, 0 - .dw 0x6440, 0xc03d, 0x647f, 0xc03d, 0x21, 0 - .dw 0x64c0, 0xc03d, 0x64ff, 0xc03d, 0x21, 0 - .dw 0x6540, 0xc03d, 0x657f, 0xc03d, 0x21, 0 - .dw 0x65c0, 0xc03d, 0x65ff, 0xc03d, 0x21, 0 - .dw 0x6640, 0xc03d, 0x667f, 0xc03d, 0x21, 0 - .dw 0x66c0, 0xc03d, 0x66ff, 0xc03d, 0x21, 0 - .dw 0x6740, 0xc03d, 0x677f, 0xc03d, 0x21, 0 - .dw 0x67c0, 0xc03d, 0x67ff, 0xc03d, 0x21, 0 - .dw 0x6840, 0xc03d, 0x687f, 0xc03d, 0x21, 0 - .dw 0x68c0, 0xc03d, 0x68ff, 0xc03d, 0x21, 0 - .dw 0x6940, 0xc03d, 0x697f, 0xc03d, 0x21, 0 - .dw 0x69c0, 0xc03d, 0x69ff, 0xc03d, 0x21, 0 - .dw 0x6a40, 0xc03d, 0x6a7f, 0xc03d, 0x21, 0 - .dw 0x6ac0, 0xc03d, 0x6aff, 0xc03d, 0x21, 0 - .dw 0x6b40, 0xc03d, 0x6b7f, 0xc03d, 0x21, 0 - .dw 0x6bc0, 0xc03d, 0x6bff, 0xc03d, 0x21, 0 - .dw 0x6c40, 0xc03d, 0x6c7f, 0xc03d, 0x21, 0 - .dw 0x6cc0, 0xc03d, 0x6cff, 0xc03d, 0x21, 0 - .dw 0x6d40, 0xc03d, 0x6d7f, 0xc03d, 0x21, 0 - .dw 0x6dc0, 0xc03d, 0x6dff, 0xc03d, 0x21, 0 - .dw 0x6e40, 0xc03d, 0x6e7f, 0xc03d, 0x21, 0 - .dw 0x6ec0, 0xc03d, 0x6eff, 0xc03d, 0x21, 0 - .dw 0x6f40, 0xc03d, 0x6f7f, 0xc03d, 0x21, 0 - .dw 0x6fc0, 0xc03d, 0x6fff, 0xc03d, 0x21, 0 - .dw 0x7040, 0xc03d, 0x707f, 0xc03d, 0x21, 0 - .dw 0x70c0, 0xc03d, 0x70ff, 0xc03d, 0x21, 0 - .dw 0x7140, 0xc03d, 0x717f, 0xc03d, 0x21, 0 - .dw 0x71c0, 0xc03d, 0x71ff, 0xc03d, 0x21, 0 - .dw 0x7240, 0xc03d, 0x727f, 0xc03d, 0x21, 0 - .dw 0x72c0, 0xc03d, 0x72ff, 0xc03d, 0x21, 0 - .dw 0x7340, 0xc03d, 0x737f, 0xc03d, 0x21, 0 - .dw 0x73c0, 0xc03d, 0x73ff, 0xc03d, 0x21, 0 - .dw 0x7440, 0xc03d, 0x747f, 0xc03d, 0x21, 0 - .dw 0x74c0, 0xc03d, 0x74ff, 0xc03d, 0x21, 0 - .dw 0x7540, 0xc03d, 0x757f, 0xc03d, 0x21, 0 - .dw 0x75c0, 0xc03d, 0x75ff, 0xc03d, 0x21, 0 - .dw 0x7640, 0xc03d, 0x767f, 0xc03d, 0x21, 0 - .dw 0x76c0, 0xc03d, 0x76ff, 0xc03d, 0x21, 0 - .dw 0x7740, 0xc03d, 0x777f, 0xc03d, 0x21, 0 - .dw 0x77c0, 0xc03d, 0x77ff, 0xc03d, 0x21, 0 - .dw 0x7840, 0xc03d, 0x787f, 0xc03d, 0x21, 0 - .dw 0x78c0, 0xc03d, 0x78ff, 0xc03d, 0x21, 0 - .dw 0x7940, 0xc03d, 0x797f, 0xc03d, 0x21, 0 - .dw 0x79c0, 0xc03d, 0x7fff, 0xc03d, 0x21, 0 - .dw 0x8040, 0xc03d, 0x807f, 0xc03d, 0x21, 0 - .dw 0x80c0, 0xc03d, 0x80ff, 0xc03d, 0x21, 0 - .dw 0x8140, 0xc03d, 0x817f, 0xc03d, 0x21, 0 - .dw 0x81c0, 0xc03d, 0x81ff, 0xc03d, 0x21, 0 - .dw 0x8240, 0xc03d, 0x827f, 0xc03d, 0x21, 0 - .dw 0x82c0, 0xc03d, 0x82ff, 0xc03d, 0x21, 0 - .dw 0x8340, 0xc03d, 0x837f, 0xc03d, 0x21, 0 - .dw 0x83c0, 0xc03d, 0x83ff, 0xc03d, 0x21, 0 - .dw 0x8440, 0xc03d, 0x847f, 0xc03d, 0x21, 0 - .dw 0x84c0, 0xc03d, 0x84ff, 0xc03d, 0x21, 0 - .dw 0x8540, 0xc03d, 0x857f, 0xc03d, 0x21, 0 - .dw 0x85c0, 0xc03d, 0x85ff, 0xc03d, 0x21, 0 - .dw 0x8640, 0xc03d, 0x867f, 0xc03d, 0x21, 0 - .dw 0x86c0, 0xc03d, 0x86ff, 0xc03d, 0x21, 0 - .dw 0x8740, 0xc03d, 0x877f, 0xc03d, 0x21, 0 - .dw 0x87c0, 0xc03d, 0x87ff, 0xc03d, 0x21, 0 - .dw 0x8840, 0xc03d, 0x887f, 0xc03d, 0x21, 0 - .dw 0x88c0, 0xc03d, 0x88ff, 0xc03d, 0x21, 0 - .dw 0x8940, 0xc03d, 0x897f, 0xc03d, 0x21, 0 - .dw 0x89c0, 0xc03d, 0x89ff, 0xc03d, 0x21, 0 - .dw 0x8a40, 0xc03d, 0x8a7f, 0xc03d, 0x21, 0 - .dw 0x8ac0, 0xc03d, 0x8aff, 0xc03d, 0x21, 0 - .dw 0x8b40, 0xc03d, 0x8b7f, 0xc03d, 0x21, 0 - .dw 0x8bc0, 0xc03d, 0x8bff, 0xc03d, 0x21, 0 - .dw 0x8c40, 0xc03d, 0x8c7f, 0xc03d, 0x21, 0 - .dw 0x8cc0, 0xc03d, 0x8cff, 0xc03d, 0x21, 0 - .dw 0x8d40, 0xc03d, 0x8d7f, 0xc03d, 0x21, 0 - .dw 0x8dc0, 0xc03d, 0x8dff, 0xc03d, 0x21, 0 - .dw 0x8e40, 0xc03d, 0x8e7f, 0xc03d, 0x21, 0 - .dw 0x8ec0, 0xc03d, 0x8eff, 0xc03d, 0x21, 0 - .dw 0x8f40, 0xc03d, 0x8f7f, 0xc03d, 0x21, 0 - .dw 0x8fc0, 0xc03d, 0x8fff, 0xc03d, 0x21, 0 - .dw 0x9040, 0xc03d, 0x907f, 0xc03d, 0x21, 0 - .dw 0x90c0, 0xc03d, 0x90ff, 0xc03d, 0x21, 0 - .dw 0x9140, 0xc03d, 0x917f, 0xc03d, 0x21, 0 - .dw 0x91c0, 0xc03d, 0x91ff, 0xc03d, 0x21, 0 - .dw 0x9240, 0xc03d, 0x927f, 0xc03d, 0x21, 0 - .dw 0x92c0, 0xc03d, 0x92ff, 0xc03d, 0x21, 0 - .dw 0x9340, 0xc03d, 0x937f, 0xc03d, 0x21, 0 - .dw 0x93c0, 0xc03d, 0x93ff, 0xc03d, 0x21, 0 - .dw 0x9440, 0xc03d, 0x947f, 0xc03d, 0x21, 0 - .dw 0x94c0, 0xc03d, 0x94ff, 0xc03d, 0x21, 0 - .dw 0x9540, 0xc03d, 0x957f, 0xc03d, 0x21, 0 - .dw 0x95c0, 0xc03d, 0x95ff, 0xc03d, 0x21, 0 - .dw 0x9640, 0xc03d, 0x967f, 0xc03d, 0x21, 0 - .dw 0x96c0, 0xc03d, 0x96ff, 0xc03d, 0x21, 0 - .dw 0x9740, 0xc03d, 0x977f, 0xc03d, 0x21, 0 - .dw 0x97c0, 0xc03d, 0x97ff, 0xc03d, 0x21, 0 - .dw 0x9840, 0xc03d, 0x987f, 0xc03d, 0x21, 0 - .dw 0x98c0, 0xc03d, 0x98ff, 0xc03d, 0x21, 0 - .dw 0x9940, 0xc03d, 0x997f, 0xc03d, 0x21, 0 - .dw 0x99c0, 0xc03d, 0x9fff, 0xc03d, 0x21, 0 - .dw 0xa040, 0xc03d, 0xa07f, 0xc03d, 0x21, 0 - .dw 0xa0c0, 0xc03d, 0xa0ff, 0xc03d, 0x21, 0 - .dw 0xa140, 0xc03d, 0xa17f, 0xc03d, 0x21, 0 - .dw 0xa1c0, 0xc03d, 0xa1ff, 0xc03d, 0x21, 0 - .dw 0xa240, 0xc03d, 0xa27f, 0xc03d, 0x21, 0 - .dw 0xa2c0, 0xc03d, 0xa2ff, 0xc03d, 0x21, 0 - .dw 0xa340, 0xc03d, 0xa37f, 0xc03d, 0x21, 0 - .dw 0xa3c0, 0xc03d, 0xa3ff, 0xc03d, 0x21, 0 - .dw 0xa440, 0xc03d, 0xa47f, 0xc03d, 0x21, 0 - .dw 0xa4c0, 0xc03d, 0xa4ff, 0xc03d, 0x21, 0 - .dw 0xa540, 0xc03d, 0xa57f, 0xc03d, 0x21, 0 - .dw 0xa5c0, 0xc03d, 0xa5ff, 0xc03d, 0x21, 0 - .dw 0xa640, 0xc03d, 0xa67f, 0xc03d, 0x21, 0 - .dw 0xa6c0, 0xc03d, 0xa6ff, 0xc03d, 0x21, 0 - .dw 0xa740, 0xc03d, 0xa77f, 0xc03d, 0x21, 0 - .dw 0xa7c0, 0xc03d, 0xa7ff, 0xc03d, 0x21, 0 - .dw 0xa840, 0xc03d, 0xa87f, 0xc03d, 0x21, 0 - .dw 0xa8c0, 0xc03d, 0xa8ff, 0xc03d, 0x21, 0 - .dw 0xa940, 0xc03d, 0xa97f, 0xc03d, 0x21, 0 - .dw 0xa9c0, 0xc03d, 0xa9ff, 0xc03d, 0x21, 0 - .dw 0xaa40, 0xc03d, 0xaa7f, 0xc03d, 0x21, 0 - .dw 0xaac0, 0xc03d, 0xaaff, 0xc03d, 0x21, 0 - .dw 0xab40, 0xc03d, 0xab7f, 0xc03d, 0x21, 0 - .dw 0xabc0, 0xc03d, 0xabff, 0xc03d, 0x21, 0 - .dw 0xac40, 0xc03d, 0xac7f, 0xc03d, 0x21, 0 - .dw 0xacc0, 0xc03d, 0xacff, 0xc03d, 0x21, 0 - .dw 0xad40, 0xc03d, 0xad7f, 0xc03d, 0x21, 0 - .dw 0xadc0, 0xc03d, 0xadff, 0xc03d, 0x21, 0 - .dw 0xae40, 0xc03d, 0xae7f, 0xc03d, 0x21, 0 - .dw 0xaec0, 0xc03d, 0xaeff, 0xc03d, 0x21, 0 - .dw 0xaf40, 0xc03d, 0xaf7f, 0xc03d, 0x21, 0 - .dw 0xafc0, 0xc03d, 0xafff, 0xc03d, 0x21, 0 - .dw 0xb040, 0xc03d, 0xb07f, 0xc03d, 0x21, 0 - .dw 0xb0c0, 0xc03d, 0xb0ff, 0xc03d, 0x21, 0 - .dw 0xb140, 0xc03d, 0xb17f, 0xc03d, 0x21, 0 - .dw 0xb1c0, 0xc03d, 0xb1ff, 0xc03d, 0x21, 0 - .dw 0xb240, 0xc03d, 0xb27f, 0xc03d, 0x21, 0 - .dw 0xb2c0, 0xc03d, 0xb2ff, 0xc03d, 0x21, 0 - .dw 0xb340, 0xc03d, 0xb37f, 0xc03d, 0x21, 0 - .dw 0xb3c0, 0xc03d, 0xb3ff, 0xc03d, 0x21, 0 - .dw 0xb440, 0xc03d, 0xb47f, 0xc03d, 0x21, 0 - .dw 0xb4c0, 0xc03d, 0xb4ff, 0xc03d, 0x21, 0 - .dw 0xb540, 0xc03d, 0xb57f, 0xc03d, 0x21, 0 - .dw 0xb5c0, 0xc03d, 0xb5ff, 0xc03d, 0x21, 0 - .dw 0xb640, 0xc03d, 0xb67f, 0xc03d, 0x21, 0 - .dw 0xb6c0, 0xc03d, 0xb6ff, 0xc03d, 0x21, 0 - .dw 0xb740, 0xc03d, 0xb77f, 0xc03d, 0x21, 0 - .dw 0xb7c0, 0xc03d, 0xb7ff, 0xc03d, 0x21, 0 - .dw 0xb840, 0xc03d, 0xb87f, 0xc03d, 0x21, 0 - .dw 0xb8c0, 0xc03d, 0xb8ff, 0xc03d, 0x21, 0 - .dw 0xb940, 0xc03d, 0xb97f, 0xc03d, 0x21, 0 - .dw 0xb9c0, 0xc03d, 0xbfff, 0xc03d, 0x21, 0 - .dw 0xc040, 0xc03d, 0xc07f, 0xc03d, 0x21, 0 - .dw 0xc0c0, 0xc03d, 0xc0ff, 0xc03d, 0x21, 0 - .dw 0xc140, 0xc03d, 0xc17f, 0xc03d, 0x21, 0 - .dw 0xc1c0, 0xc03d, 0xc1ff, 0xc03d, 0x21, 0 - .dw 0xc240, 0xc03d, 0xc27f, 0xc03d, 0x21, 0 - .dw 0xc2c0, 0xc03d, 0xc2ff, 0xc03d, 0x21, 0 - .dw 0xc340, 0xc03d, 0xc37f, 0xc03d, 0x21, 0 - .dw 0xc3c0, 0xc03d, 0xc3ff, 0xc03d, 0x21, 0 - .dw 0xc440, 0xc03d, 0xc47f, 0xc03d, 0x21, 0 - .dw 0xc4c0, 0xc03d, 0xc4ff, 0xc03d, 0x21, 0 - .dw 0xc540, 0xc03d, 0xc57f, 0xc03d, 0x21, 0 - .dw 0xc5c0, 0xc03d, 0xc5ff, 0xc03d, 0x21, 0 - .dw 0xc640, 0xc03d, 0xc67f, 0xc03d, 0x21, 0 - .dw 0xc6c0, 0xc03d, 0xc6ff, 0xc03d, 0x21, 0 - .dw 0xc740, 0xc03d, 0xc77f, 0xc03d, 0x21, 0 - .dw 0xc7c0, 0xc03d, 0xc7ff, 0xc03d, 0x21, 0 - .dw 0xc840, 0xc03d, 0xc87f, 0xc03d, 0x21, 0 - .dw 0xc8c0, 0xc03d, 0xc8ff, 0xc03d, 0x21, 0 - .dw 0xc940, 0xc03d, 0xc97f, 0xc03d, 0x21, 0 - .dw 0xc9c0, 0xc03d, 0xc9ff, 0xc03d, 0x21, 0 - .dw 0xca40, 0xc03d, 0xca7f, 0xc03d, 0x21, 0 - .dw 0xcac0, 0xc03d, 0xcaff, 0xc03d, 0x21, 0 - .dw 0xcb40, 0xc03d, 0xcb7f, 0xc03d, 0x21, 0 - .dw 0xcbc0, 0xc03d, 0xcbff, 0xc03d, 0x21, 0 - .dw 0xcc40, 0xc03d, 0xcc7f, 0xc03d, 0x21, 0 - .dw 0xccc0, 0xc03d, 0xccff, 0xc03d, 0x21, 0 - .dw 0xcd40, 0xc03d, 0xcd7f, 0xc03d, 0x21, 0 - .dw 0xcdc0, 0xc03d, 0xcdff, 0xc03d, 0x21, 0 - .dw 0xce40, 0xc03d, 0xce7f, 0xc03d, 0x21, 0 - .dw 0xcec0, 0xc03d, 0xceff, 0xc03d, 0x21, 0 - .dw 0xcf40, 0xc03d, 0xcf7f, 0xc03d, 0x21, 0 - .dw 0xcfc0, 0xc03d, 0xcfff, 0xc03d, 0x21, 0 - .dw 0xd040, 0xc03d, 0xd07f, 0xc03d, 0x21, 0 - .dw 0xd0c0, 0xc03d, 0xd0ff, 0xc03d, 0x21, 0 - .dw 0xd140, 0xc03d, 0xd17f, 0xc03d, 0x21, 0 - .dw 0xd1c0, 0xc03d, 0xd1ff, 0xc03d, 0x21, 0 - .dw 0xd240, 0xc03d, 0xd27f, 0xc03d, 0x21, 0 - .dw 0xd2c0, 0xc03d, 0xd2ff, 0xc03d, 0x21, 0 - .dw 0xd340, 0xc03d, 0xd37f, 0xc03d, 0x21, 0 - .dw 0xd3c0, 0xc03d, 0xd3ff, 0xc03d, 0x21, 0 - .dw 0xd440, 0xc03d, 0xd47f, 0xc03d, 0x21, 0 - .dw 0xd4c0, 0xc03d, 0xd4ff, 0xc03d, 0x21, 0 - .dw 0xd540, 0xc03d, 0xd57f, 0xc03d, 0x21, 0 - .dw 0xd5c0, 0xc03d, 0xd5ff, 0xc03d, 0x21, 0 - .dw 0xd640, 0xc03d, 0xd67f, 0xc03d, 0x21, 0 - .dw 0xd6c0, 0xc03d, 0xd6ff, 0xc03d, 0x21, 0 - .dw 0xd740, 0xc03d, 0xd77f, 0xc03d, 0x21, 0 - .dw 0xd7c0, 0xc03d, 0xd7ff, 0xc03d, 0x21, 0 - .dw 0xd840, 0xc03d, 0xd87f, 0xc03d, 0x21, 0 - .dw 0xd8c0, 0xc03d, 0xd8ff, 0xc03d, 0x21, 0 - .dw 0xd940, 0xc03d, 0xd97f, 0xc03d, 0x21, 0 - .dw 0xd9c0, 0xc03d, 0xdfff, 0xc03d, 0x21, 0 - .dw 0xe040, 0xc03d, 0xe07f, 0xc03d, 0x21, 0 - .dw 0xe0c0, 0xc03d, 0xe0ff, 0xc03d, 0x21, 0 - .dw 0xe140, 0xc03d, 0xe17f, 0xc03d, 0x21, 0 - .dw 0xe1c0, 0xc03d, 0xe1ff, 0xc03d, 0x21, 0 - .dw 0xe240, 0xc03d, 0xe27f, 0xc03d, 0x21, 0 - .dw 0xe2c0, 0xc03d, 0xe2ff, 0xc03d, 0x21, 0 - .dw 0xe340, 0xc03d, 0xe37f, 0xc03d, 0x21, 0 - .dw 0xe3c0, 0xc03d, 0xe3ff, 0xc03d, 0x21, 0 - .dw 0xe440, 0xc03d, 0xe47f, 0xc03d, 0x21, 0 - .dw 0xe4c0, 0xc03d, 0xe4ff, 0xc03d, 0x21, 0 - .dw 0xe540, 0xc03d, 0xe57f, 0xc03d, 0x21, 0 - .dw 0xe5c0, 0xc03d, 0xe5ff, 0xc03d, 0x21, 0 - .dw 0xe640, 0xc03d, 0xe67f, 0xc03d, 0x21, 0 - .dw 0xe6c0, 0xc03d, 0xe6ff, 0xc03d, 0x21, 0 - .dw 0xe740, 0xc03d, 0xe77f, 0xc03d, 0x21, 0 - .dw 0xe7c0, 0xc03d, 0xe7ff, 0xc03d, 0x21, 0 - .dw 0xe840, 0xc03d, 0xe87f, 0xc03d, 0x21, 0 - .dw 0xe8c0, 0xc03d, 0xe8ff, 0xc03d, 0x21, 0 - .dw 0xe940, 0xc03d, 0xe97f, 0xc03d, 0x21, 0 - .dw 0xe9c0, 0xc03d, 0xe9ff, 0xc03d, 0x21, 0 - .dw 0xea40, 0xc03d, 0xea7f, 0xc03d, 0x21, 0 - .dw 0xeac0, 0xc03d, 0xeaff, 0xc03d, 0x21, 0 - .dw 0xeb40, 0xc03d, 0xeb7f, 0xc03d, 0x21, 0 - .dw 0xebc0, 0xc03d, 0xebff, 0xc03d, 0x21, 0 - .dw 0xec40, 0xc03d, 0xec7f, 0xc03d, 0x21, 0 - .dw 0xecc0, 0xc03d, 0xecff, 0xc03d, 0x21, 0 - .dw 0xed40, 0xc03d, 0xed7f, 0xc03d, 0x21, 0 - .dw 0xedc0, 0xc03d, 0xedff, 0xc03d, 0x21, 0 - .dw 0xee40, 0xc03d, 0xee7f, 0xc03d, 0x21, 0 - .dw 0xeec0, 0xc03d, 0xeeff, 0xc03d, 0x21, 0 - .dw 0xef40, 0xc03d, 0xef7f, 0xc03d, 0x21, 0 - .dw 0xefc0, 0xc03d, 0xefff, 0xc03d, 0x21, 0 - .dw 0xf040, 0xc03d, 0xf07f, 0xc03d, 0x21, 0 - .dw 0xf0c0, 0xc03d, 0xf0ff, 0xc03d, 0x21, 0 - .dw 0xf140, 0xc03d, 0xf17f, 0xc03d, 0x21, 0 - .dw 0xf1c0, 0xc03d, 0xf1ff, 0xc03d, 0x21, 0 - .dw 0xf240, 0xc03d, 0xf27f, 0xc03d, 0x21, 0 - .dw 0xf2c0, 0xc03d, 0xf2ff, 0xc03d, 0x21, 0 - .dw 0xf340, 0xc03d, 0xf37f, 0xc03d, 0x21, 0 - .dw 0xf3c0, 0xc03d, 0xf3ff, 0xc03d, 0x21, 0 - .dw 0xf440, 0xc03d, 0xf47f, 0xc03d, 0x21, 0 - .dw 0xf4c0, 0xc03d, 0xf4ff, 0xc03d, 0x21, 0 - .dw 0xf540, 0xc03d, 0xf57f, 0xc03d, 0x21, 0 - .dw 0xf5c0, 0xc03d, 0xf5ff, 0xc03d, 0x21, 0 - .dw 0xf640, 0xc03d, 0xf67f, 0xc03d, 0x21, 0 - .dw 0xf6c0, 0xc03d, 0xf6ff, 0xc03d, 0x21, 0 - .dw 0xf740, 0xc03d, 0xf77f, 0xc03d, 0x21, 0 - .dw 0xf7c0, 0xc03d, 0xf7ff, 0xc03d, 0x21, 0 - .dw 0xf840, 0xc03d, 0xf87f, 0xc03d, 0x21, 0 - .dw 0xf8c0, 0xc03d, 0xf8ff, 0xc03d, 0x21, 0 - .dw 0xf940, 0xc03d, 0xf97f, 0xc03d, 0x21, 0 - .dw 0xf9c0, 0xc03d, 0xffff, 0xc03d, 0x21, 0 - .dw 0x0040, 0xc03e, 0x007f, 0xc03e, 0x21, 0 - .dw 0x00c0, 0xc03e, 0x00ff, 0xc03e, 0x21, 0 - .dw 0x0140, 0xc03e, 0x017f, 0xc03e, 0x21, 0 - .dw 0x01c0, 0xc03e, 0x01ff, 0xc03e, 0x21, 0 - .dw 0x0240, 0xc03e, 0x027f, 0xc03e, 0x21, 0 - .dw 0x02c0, 0xc03e, 0x02ff, 0xc03e, 0x21, 0 - .dw 0x0340, 0xc03e, 0x037f, 0xc03e, 0x21, 0 - .dw 0x03c0, 0xc03e, 0x03ff, 0xc03e, 0x21, 0 - .dw 0x0440, 0xc03e, 0x047f, 0xc03e, 0x21, 0 - .dw 0x04c0, 0xc03e, 0x04ff, 0xc03e, 0x21, 0 - .dw 0x0540, 0xc03e, 0x057f, 0xc03e, 0x21, 0 - .dw 0x05c0, 0xc03e, 0x05ff, 0xc03e, 0x21, 0 - .dw 0x0640, 0xc03e, 0x067f, 0xc03e, 0x21, 0 - .dw 0x06c0, 0xc03e, 0x06ff, 0xc03e, 0x21, 0 - .dw 0x0740, 0xc03e, 0x077f, 0xc03e, 0x21, 0 - .dw 0x07c0, 0xc03e, 0x07ff, 0xc03e, 0x21, 0 - .dw 0x0840, 0xc03e, 0x087f, 0xc03e, 0x21, 0 - .dw 0x08c0, 0xc03e, 0x08ff, 0xc03e, 0x21, 0 - .dw 0x0940, 0xc03e, 0x097f, 0xc03e, 0x21, 0 - .dw 0x09c0, 0xc03e, 0x09ff, 0xc03e, 0x21, 0 - .dw 0x0a40, 0xc03e, 0x0a7f, 0xc03e, 0x21, 0 - .dw 0x0ac0, 0xc03e, 0x0aff, 0xc03e, 0x21, 0 - .dw 0x0b40, 0xc03e, 0x0b7f, 0xc03e, 0x21, 0 - .dw 0x0bc0, 0xc03e, 0x0bff, 0xc03e, 0x21, 0 - .dw 0x0c40, 0xc03e, 0x0c7f, 0xc03e, 0x21, 0 - .dw 0x0cc0, 0xc03e, 0x0cff, 0xc03e, 0x21, 0 - .dw 0x0d40, 0xc03e, 0x0d7f, 0xc03e, 0x21, 0 - .dw 0x0dc0, 0xc03e, 0x0dff, 0xc03e, 0x21, 0 - .dw 0x0e40, 0xc03e, 0x0e7f, 0xc03e, 0x21, 0 - .dw 0x0ec0, 0xc03e, 0x0eff, 0xc03e, 0x21, 0 - .dw 0x0f40, 0xc03e, 0x0f7f, 0xc03e, 0x21, 0 - .dw 0x0fc0, 0xc03e, 0x0fff, 0xc03e, 0x21, 0 - .dw 0x1040, 0xc03e, 0x107f, 0xc03e, 0x21, 0 - .dw 0x10c0, 0xc03e, 0x10ff, 0xc03e, 0x21, 0 - .dw 0x1140, 0xc03e, 0x117f, 0xc03e, 0x21, 0 - .dw 0x11c0, 0xc03e, 0x11ff, 0xc03e, 0x21, 0 - .dw 0x1240, 0xc03e, 0x127f, 0xc03e, 0x21, 0 - .dw 0x12c0, 0xc03e, 0x12ff, 0xc03e, 0x21, 0 - .dw 0x1340, 0xc03e, 0x137f, 0xc03e, 0x21, 0 - .dw 0x13c0, 0xc03e, 0x13ff, 0xc03e, 0x21, 0 - .dw 0x1440, 0xc03e, 0x147f, 0xc03e, 0x21, 0 - .dw 0x14c0, 0xc03e, 0x14ff, 0xc03e, 0x21, 0 - .dw 0x1540, 0xc03e, 0x157f, 0xc03e, 0x21, 0 - .dw 0x15c0, 0xc03e, 0x15ff, 0xc03e, 0x21, 0 - .dw 0x1640, 0xc03e, 0x167f, 0xc03e, 0x21, 0 - .dw 0x16c0, 0xc03e, 0x16ff, 0xc03e, 0x21, 0 - .dw 0x1740, 0xc03e, 0x177f, 0xc03e, 0x21, 0 - .dw 0x17c0, 0xc03e, 0x17ff, 0xc03e, 0x21, 0 - .dw 0x1840, 0xc03e, 0x187f, 0xc03e, 0x21, 0 - .dw 0x18c0, 0xc03e, 0x18ff, 0xc03e, 0x21, 0 - .dw 0x1940, 0xc03e, 0x197f, 0xc03e, 0x21, 0 - .dw 0x19c0, 0xc03e, 0x1fff, 0xc03e, 0x21, 0 - .dw 0x2040, 0xc03e, 0x207f, 0xc03e, 0x21, 0 - .dw 0x20c0, 0xc03e, 0x20ff, 0xc03e, 0x21, 0 - .dw 0x2140, 0xc03e, 0x217f, 0xc03e, 0x21, 0 - .dw 0x21c0, 0xc03e, 0x21ff, 0xc03e, 0x21, 0 - .dw 0x2240, 0xc03e, 0x227f, 0xc03e, 0x21, 0 - .dw 0x22c0, 0xc03e, 0x22ff, 0xc03e, 0x21, 0 - .dw 0x2340, 0xc03e, 0x237f, 0xc03e, 0x21, 0 - .dw 0x23c0, 0xc03e, 0x23ff, 0xc03e, 0x21, 0 - .dw 0x2440, 0xc03e, 0x247f, 0xc03e, 0x21, 0 - .dw 0x24c0, 0xc03e, 0x24ff, 0xc03e, 0x21, 0 - .dw 0x2540, 0xc03e, 0x257f, 0xc03e, 0x21, 0 - .dw 0x25c0, 0xc03e, 0x25ff, 0xc03e, 0x21, 0 - .dw 0x2640, 0xc03e, 0x267f, 0xc03e, 0x21, 0 - .dw 0x26c0, 0xc03e, 0x26ff, 0xc03e, 0x21, 0 - .dw 0x2740, 0xc03e, 0x277f, 0xc03e, 0x21, 0 - .dw 0x27c0, 0xc03e, 0x27ff, 0xc03e, 0x21, 0 - .dw 0x2840, 0xc03e, 0x287f, 0xc03e, 0x21, 0 - .dw 0x28c0, 0xc03e, 0x28ff, 0xc03e, 0x21, 0 - .dw 0x2940, 0xc03e, 0x297f, 0xc03e, 0x21, 0 - .dw 0x29c0, 0xc03e, 0x29ff, 0xc03e, 0x21, 0 - .dw 0x2a40, 0xc03e, 0x2a7f, 0xc03e, 0x21, 0 - .dw 0x2ac0, 0xc03e, 0x2aff, 0xc03e, 0x21, 0 - .dw 0x2b40, 0xc03e, 0x2b7f, 0xc03e, 0x21, 0 - .dw 0x2bc0, 0xc03e, 0x2bff, 0xc03e, 0x21, 0 - .dw 0x2c40, 0xc03e, 0x2c7f, 0xc03e, 0x21, 0 - .dw 0x2cc0, 0xc03e, 0x2cff, 0xc03e, 0x21, 0 - .dw 0x2d40, 0xc03e, 0x2d7f, 0xc03e, 0x21, 0 - .dw 0x2dc0, 0xc03e, 0x2dff, 0xc03e, 0x21, 0 - .dw 0x2e40, 0xc03e, 0x2e7f, 0xc03e, 0x21, 0 - .dw 0x2ec0, 0xc03e, 0x2eff, 0xc03e, 0x21, 0 - .dw 0x2f40, 0xc03e, 0x2f7f, 0xc03e, 0x21, 0 - .dw 0x2fc0, 0xc03e, 0x2fff, 0xc03e, 0x21, 0 - .dw 0x3040, 0xc03e, 0x307f, 0xc03e, 0x21, 0 - .dw 0x30c0, 0xc03e, 0x30ff, 0xc03e, 0x21, 0 - .dw 0x3140, 0xc03e, 0x317f, 0xc03e, 0x21, 0 - .dw 0x31c0, 0xc03e, 0x31ff, 0xc03e, 0x21, 0 - .dw 0x3240, 0xc03e, 0x327f, 0xc03e, 0x21, 0 - .dw 0x32c0, 0xc03e, 0x32ff, 0xc03e, 0x21, 0 - .dw 0x3340, 0xc03e, 0x337f, 0xc03e, 0x21, 0 - .dw 0x33c0, 0xc03e, 0x33ff, 0xc03e, 0x21, 0 - .dw 0x3440, 0xc03e, 0x347f, 0xc03e, 0x21, 0 - .dw 0x34c0, 0xc03e, 0x34ff, 0xc03e, 0x21, 0 - .dw 0x3540, 0xc03e, 0x357f, 0xc03e, 0x21, 0 - .dw 0x35c0, 0xc03e, 0x35ff, 0xc03e, 0x21, 0 - .dw 0x3640, 0xc03e, 0x367f, 0xc03e, 0x21, 0 - .dw 0x36c0, 0xc03e, 0x36ff, 0xc03e, 0x21, 0 - .dw 0x3740, 0xc03e, 0x377f, 0xc03e, 0x21, 0 - .dw 0x37c0, 0xc03e, 0x37ff, 0xc03e, 0x21, 0 - .dw 0x3840, 0xc03e, 0x387f, 0xc03e, 0x21, 0 - .dw 0x38c0, 0xc03e, 0x38ff, 0xc03e, 0x21, 0 - .dw 0x3940, 0xc03e, 0x397f, 0xc03e, 0x21, 0 - .dw 0x39c0, 0xc03e, 0x3fff, 0xc03e, 0x21, 0 - .dw 0x4040, 0xc03e, 0x407f, 0xc03e, 0x21, 0 - .dw 0x40c0, 0xc03e, 0x40ff, 0xc03e, 0x21, 0 - .dw 0x4140, 0xc03e, 0x417f, 0xc03e, 0x21, 0 - .dw 0x41c0, 0xc03e, 0x41ff, 0xc03e, 0x21, 0 - .dw 0x4240, 0xc03e, 0x427f, 0xc03e, 0x21, 0 - .dw 0x42c0, 0xc03e, 0x42ff, 0xc03e, 0x21, 0 - .dw 0x4340, 0xc03e, 0x437f, 0xc03e, 0x21, 0 - .dw 0x43c0, 0xc03e, 0x43ff, 0xc03e, 0x21, 0 - .dw 0x4440, 0xc03e, 0x447f, 0xc03e, 0x21, 0 - .dw 0x44c0, 0xc03e, 0x44ff, 0xc03e, 0x21, 0 - .dw 0x4540, 0xc03e, 0x457f, 0xc03e, 0x21, 0 - .dw 0x45c0, 0xc03e, 0x45ff, 0xc03e, 0x21, 0 - .dw 0x4640, 0xc03e, 0x467f, 0xc03e, 0x21, 0 - .dw 0x46c0, 0xc03e, 0x46ff, 0xc03e, 0x21, 0 - .dw 0x4740, 0xc03e, 0x477f, 0xc03e, 0x21, 0 - .dw 0x47c0, 0xc03e, 0x47ff, 0xc03e, 0x21, 0 - .dw 0x4840, 0xc03e, 0x487f, 0xc03e, 0x21, 0 - .dw 0x48c0, 0xc03e, 0x48ff, 0xc03e, 0x21, 0 - .dw 0x4940, 0xc03e, 0x497f, 0xc03e, 0x21, 0 - .dw 0x49c0, 0xc03e, 0x49ff, 0xc03e, 0x21, 0 - .dw 0x4a40, 0xc03e, 0x4a7f, 0xc03e, 0x21, 0 - .dw 0x4ac0, 0xc03e, 0x4aff, 0xc03e, 0x21, 0 - .dw 0x4b40, 0xc03e, 0x4b7f, 0xc03e, 0x21, 0 - .dw 0x4bc0, 0xc03e, 0x4bff, 0xc03e, 0x21, 0 - .dw 0x4c40, 0xc03e, 0x4c7f, 0xc03e, 0x21, 0 - .dw 0x4cc0, 0xc03e, 0x4cff, 0xc03e, 0x21, 0 - .dw 0x4d40, 0xc03e, 0x4d7f, 0xc03e, 0x21, 0 - .dw 0x4dc0, 0xc03e, 0x4dff, 0xc03e, 0x21, 0 - .dw 0x4e40, 0xc03e, 0x4e7f, 0xc03e, 0x21, 0 - .dw 0x4ec0, 0xc03e, 0x4eff, 0xc03e, 0x21, 0 - .dw 0x4f40, 0xc03e, 0x4f7f, 0xc03e, 0x21, 0 - .dw 0x4fc0, 0xc03e, 0x4fff, 0xc03e, 0x21, 0 - .dw 0x5040, 0xc03e, 0x507f, 0xc03e, 0x21, 0 - .dw 0x50c0, 0xc03e, 0x50ff, 0xc03e, 0x21, 0 - .dw 0x5140, 0xc03e, 0x517f, 0xc03e, 0x21, 0 - .dw 0x51c0, 0xc03e, 0x51ff, 0xc03e, 0x21, 0 - .dw 0x5240, 0xc03e, 0x527f, 0xc03e, 0x21, 0 - .dw 0x52c0, 0xc03e, 0x52ff, 0xc03e, 0x21, 0 - .dw 0x5340, 0xc03e, 0x537f, 0xc03e, 0x21, 0 - .dw 0x53c0, 0xc03e, 0x53ff, 0xc03e, 0x21, 0 - .dw 0x5440, 0xc03e, 0x547f, 0xc03e, 0x21, 0 - .dw 0x54c0, 0xc03e, 0x54ff, 0xc03e, 0x21, 0 - .dw 0x5540, 0xc03e, 0x557f, 0xc03e, 0x21, 0 - .dw 0x55c0, 0xc03e, 0x55ff, 0xc03e, 0x21, 0 - .dw 0x5640, 0xc03e, 0x567f, 0xc03e, 0x21, 0 - .dw 0x56c0, 0xc03e, 0x56ff, 0xc03e, 0x21, 0 - .dw 0x5740, 0xc03e, 0x577f, 0xc03e, 0x21, 0 - .dw 0x57c0, 0xc03e, 0x57ff, 0xc03e, 0x21, 0 - .dw 0x5840, 0xc03e, 0x587f, 0xc03e, 0x21, 0 - .dw 0x58c0, 0xc03e, 0x58ff, 0xc03e, 0x21, 0 - .dw 0x5940, 0xc03e, 0x597f, 0xc03e, 0x21, 0 - .dw 0x59c0, 0xc03e, 0x5fff, 0xc03e, 0x21, 0 - .dw 0x6040, 0xc03e, 0x607f, 0xc03e, 0x21, 0 - .dw 0x60c0, 0xc03e, 0x60ff, 0xc03e, 0x21, 0 - .dw 0x6140, 0xc03e, 0x617f, 0xc03e, 0x21, 0 - .dw 0x61c0, 0xc03e, 0x61ff, 0xc03e, 0x21, 0 - .dw 0x6240, 0xc03e, 0x627f, 0xc03e, 0x21, 0 - .dw 0x62c0, 0xc03e, 0x62ff, 0xc03e, 0x21, 0 - .dw 0x6340, 0xc03e, 0x637f, 0xc03e, 0x21, 0 - .dw 0x63c0, 0xc03e, 0x63ff, 0xc03e, 0x21, 0 - .dw 0x6440, 0xc03e, 0x647f, 0xc03e, 0x21, 0 - .dw 0x64c0, 0xc03e, 0x64ff, 0xc03e, 0x21, 0 - .dw 0x6540, 0xc03e, 0x657f, 0xc03e, 0x21, 0 - .dw 0x65c0, 0xc03e, 0x65ff, 0xc03e, 0x21, 0 - .dw 0x6640, 0xc03e, 0x667f, 0xc03e, 0x21, 0 - .dw 0x66c0, 0xc03e, 0x66ff, 0xc03e, 0x21, 0 - .dw 0x6740, 0xc03e, 0x677f, 0xc03e, 0x21, 0 - .dw 0x67c0, 0xc03e, 0x67ff, 0xc03e, 0x21, 0 - .dw 0x6840, 0xc03e, 0x687f, 0xc03e, 0x21, 0 - .dw 0x68c0, 0xc03e, 0x68ff, 0xc03e, 0x21, 0 - .dw 0x6940, 0xc03e, 0x697f, 0xc03e, 0x21, 0 - .dw 0x69c0, 0xc03e, 0x69ff, 0xc03e, 0x21, 0 - .dw 0x6a40, 0xc03e, 0x6a7f, 0xc03e, 0x21, 0 - .dw 0x6ac0, 0xc03e, 0x6aff, 0xc03e, 0x21, 0 - .dw 0x6b40, 0xc03e, 0x6b7f, 0xc03e, 0x21, 0 - .dw 0x6bc0, 0xc03e, 0x6bff, 0xc03e, 0x21, 0 - .dw 0x6c40, 0xc03e, 0x6c7f, 0xc03e, 0x21, 0 - .dw 0x6cc0, 0xc03e, 0x6cff, 0xc03e, 0x21, 0 - .dw 0x6d40, 0xc03e, 0x6d7f, 0xc03e, 0x21, 0 - .dw 0x6dc0, 0xc03e, 0x6dff, 0xc03e, 0x21, 0 - .dw 0x6e40, 0xc03e, 0x6e7f, 0xc03e, 0x21, 0 - .dw 0x6ec0, 0xc03e, 0x6eff, 0xc03e, 0x21, 0 - .dw 0x6f40, 0xc03e, 0x6f7f, 0xc03e, 0x21, 0 - .dw 0x6fc0, 0xc03e, 0x6fff, 0xc03e, 0x21, 0 - .dw 0x7040, 0xc03e, 0x707f, 0xc03e, 0x21, 0 - .dw 0x70c0, 0xc03e, 0x70ff, 0xc03e, 0x21, 0 - .dw 0x7140, 0xc03e, 0x717f, 0xc03e, 0x21, 0 - .dw 0x71c0, 0xc03e, 0x71ff, 0xc03e, 0x21, 0 - .dw 0x7240, 0xc03e, 0x727f, 0xc03e, 0x21, 0 - .dw 0x72c0, 0xc03e, 0x72ff, 0xc03e, 0x21, 0 - .dw 0x7340, 0xc03e, 0x737f, 0xc03e, 0x21, 0 - .dw 0x73c0, 0xc03e, 0x73ff, 0xc03e, 0x21, 0 - .dw 0x7440, 0xc03e, 0x747f, 0xc03e, 0x21, 0 - .dw 0x74c0, 0xc03e, 0x74ff, 0xc03e, 0x21, 0 - .dw 0x7540, 0xc03e, 0x757f, 0xc03e, 0x21, 0 - .dw 0x75c0, 0xc03e, 0x75ff, 0xc03e, 0x21, 0 - .dw 0x7640, 0xc03e, 0x767f, 0xc03e, 0x21, 0 - .dw 0x76c0, 0xc03e, 0x76ff, 0xc03e, 0x21, 0 - .dw 0x7740, 0xc03e, 0x777f, 0xc03e, 0x21, 0 - .dw 0x77c0, 0xc03e, 0x77ff, 0xc03e, 0x21, 0 - .dw 0x7840, 0xc03e, 0x787f, 0xc03e, 0x21, 0 - .dw 0x78c0, 0xc03e, 0x78ff, 0xc03e, 0x21, 0 - .dw 0x7940, 0xc03e, 0x797f, 0xc03e, 0x21, 0 - .dw 0x79c0, 0xc03e, 0x7fff, 0xc03e, 0x21, 0 - .dw 0x8040, 0xc03e, 0x807f, 0xc03e, 0x21, 0 - .dw 0x80c0, 0xc03e, 0x80ff, 0xc03e, 0x21, 0 - .dw 0x8140, 0xc03e, 0x817f, 0xc03e, 0x21, 0 - .dw 0x81c0, 0xc03e, 0x81ff, 0xc03e, 0x21, 0 - .dw 0x8240, 0xc03e, 0x827f, 0xc03e, 0x21, 0 - .dw 0x82c0, 0xc03e, 0x82ff, 0xc03e, 0x21, 0 - .dw 0x8340, 0xc03e, 0x837f, 0xc03e, 0x21, 0 - .dw 0x83c0, 0xc03e, 0x83ff, 0xc03e, 0x21, 0 - .dw 0x8440, 0xc03e, 0x847f, 0xc03e, 0x21, 0 - .dw 0x84c0, 0xc03e, 0x84ff, 0xc03e, 0x21, 0 - .dw 0x8540, 0xc03e, 0x857f, 0xc03e, 0x21, 0 - .dw 0x85c0, 0xc03e, 0x85ff, 0xc03e, 0x21, 0 - .dw 0x8640, 0xc03e, 0x867f, 0xc03e, 0x21, 0 - .dw 0x86c0, 0xc03e, 0x86ff, 0xc03e, 0x21, 0 - .dw 0x8740, 0xc03e, 0x877f, 0xc03e, 0x21, 0 - .dw 0x87c0, 0xc03e, 0x87ff, 0xc03e, 0x21, 0 - .dw 0x8840, 0xc03e, 0x887f, 0xc03e, 0x21, 0 - .dw 0x88c0, 0xc03e, 0x88ff, 0xc03e, 0x21, 0 - .dw 0x8940, 0xc03e, 0x897f, 0xc03e, 0x21, 0 - .dw 0x89c0, 0xc03e, 0x89ff, 0xc03e, 0x21, 0 - .dw 0x8a40, 0xc03e, 0x8a7f, 0xc03e, 0x21, 0 - .dw 0x8ac0, 0xc03e, 0x8aff, 0xc03e, 0x21, 0 - .dw 0x8b40, 0xc03e, 0x8b7f, 0xc03e, 0x21, 0 - .dw 0x8bc0, 0xc03e, 0x8bff, 0xc03e, 0x21, 0 - .dw 0x8c40, 0xc03e, 0x8c7f, 0xc03e, 0x21, 0 - .dw 0x8cc0, 0xc03e, 0x8cff, 0xc03e, 0x21, 0 - .dw 0x8d40, 0xc03e, 0x8d7f, 0xc03e, 0x21, 0 - .dw 0x8dc0, 0xc03e, 0x8dff, 0xc03e, 0x21, 0 - .dw 0x8e40, 0xc03e, 0x8e7f, 0xc03e, 0x21, 0 - .dw 0x8ec0, 0xc03e, 0x8eff, 0xc03e, 0x21, 0 - .dw 0x8f40, 0xc03e, 0x8f7f, 0xc03e, 0x21, 0 - .dw 0x8fc0, 0xc03e, 0x8fff, 0xc03e, 0x21, 0 - .dw 0x9040, 0xc03e, 0x907f, 0xc03e, 0x21, 0 - .dw 0x90c0, 0xc03e, 0x90ff, 0xc03e, 0x21, 0 - .dw 0x9140, 0xc03e, 0x917f, 0xc03e, 0x21, 0 - .dw 0x91c0, 0xc03e, 0x91ff, 0xc03e, 0x21, 0 - .dw 0x9240, 0xc03e, 0x927f, 0xc03e, 0x21, 0 - .dw 0x92c0, 0xc03e, 0x92ff, 0xc03e, 0x21, 0 - .dw 0x9340, 0xc03e, 0x937f, 0xc03e, 0x21, 0 - .dw 0x93c0, 0xc03e, 0x93ff, 0xc03e, 0x21, 0 - .dw 0x9440, 0xc03e, 0x947f, 0xc03e, 0x21, 0 - .dw 0x94c0, 0xc03e, 0x94ff, 0xc03e, 0x21, 0 - .dw 0x9540, 0xc03e, 0x957f, 0xc03e, 0x21, 0 - .dw 0x95c0, 0xc03e, 0x95ff, 0xc03e, 0x21, 0 - .dw 0x9640, 0xc03e, 0x967f, 0xc03e, 0x21, 0 - .dw 0x96c0, 0xc03e, 0x96ff, 0xc03e, 0x21, 0 - .dw 0x9740, 0xc03e, 0x977f, 0xc03e, 0x21, 0 - .dw 0x97c0, 0xc03e, 0x97ff, 0xc03e, 0x21, 0 - .dw 0x9840, 0xc03e, 0x987f, 0xc03e, 0x21, 0 - .dw 0x98c0, 0xc03e, 0x98ff, 0xc03e, 0x21, 0 - .dw 0x9940, 0xc03e, 0x997f, 0xc03e, 0x21, 0 - .dw 0x99c0, 0xc03e, 0x9fff, 0xc03e, 0x21, 0 - .dw 0xa040, 0xc03e, 0xa07f, 0xc03e, 0x21, 0 - .dw 0xa0c0, 0xc03e, 0xa0ff, 0xc03e, 0x21, 0 - .dw 0xa140, 0xc03e, 0xa17f, 0xc03e, 0x21, 0 - .dw 0xa1c0, 0xc03e, 0xa1ff, 0xc03e, 0x21, 0 - .dw 0xa240, 0xc03e, 0xa27f, 0xc03e, 0x21, 0 - .dw 0xa2c0, 0xc03e, 0xa2ff, 0xc03e, 0x21, 0 - .dw 0xa340, 0xc03e, 0xa37f, 0xc03e, 0x21, 0 - .dw 0xa3c0, 0xc03e, 0xa3ff, 0xc03e, 0x21, 0 - .dw 0xa440, 0xc03e, 0xa47f, 0xc03e, 0x21, 0 - .dw 0xa4c0, 0xc03e, 0xa4ff, 0xc03e, 0x21, 0 - .dw 0xa540, 0xc03e, 0xa57f, 0xc03e, 0x21, 0 - .dw 0xa5c0, 0xc03e, 0xa5ff, 0xc03e, 0x21, 0 - .dw 0xa640, 0xc03e, 0xa67f, 0xc03e, 0x21, 0 - .dw 0xa6c0, 0xc03e, 0xa6ff, 0xc03e, 0x21, 0 - .dw 0xa740, 0xc03e, 0xa77f, 0xc03e, 0x21, 0 - .dw 0xa7c0, 0xc03e, 0xa7ff, 0xc03e, 0x21, 0 - .dw 0xa840, 0xc03e, 0xa87f, 0xc03e, 0x21, 0 - .dw 0xa8c0, 0xc03e, 0xa8ff, 0xc03e, 0x21, 0 - .dw 0xa940, 0xc03e, 0xa97f, 0xc03e, 0x21, 0 - .dw 0xa9c0, 0xc03e, 0xa9ff, 0xc03e, 0x21, 0 - .dw 0xaa40, 0xc03e, 0xaa7f, 0xc03e, 0x21, 0 - .dw 0xaac0, 0xc03e, 0xaaff, 0xc03e, 0x21, 0 - .dw 0xab40, 0xc03e, 0xab7f, 0xc03e, 0x21, 0 - .dw 0xabc0, 0xc03e, 0xabff, 0xc03e, 0x21, 0 - .dw 0xac40, 0xc03e, 0xac7f, 0xc03e, 0x21, 0 - .dw 0xacc0, 0xc03e, 0xacff, 0xc03e, 0x21, 0 - .dw 0xad40, 0xc03e, 0xad7f, 0xc03e, 0x21, 0 - .dw 0xadc0, 0xc03e, 0xadff, 0xc03e, 0x21, 0 - .dw 0xae40, 0xc03e, 0xae7f, 0xc03e, 0x21, 0 - .dw 0xaec0, 0xc03e, 0xaeff, 0xc03e, 0x21, 0 - .dw 0xaf40, 0xc03e, 0xaf7f, 0xc03e, 0x21, 0 - .dw 0xafc0, 0xc03e, 0xafff, 0xc03e, 0x21, 0 - .dw 0xb040, 0xc03e, 0xb07f, 0xc03e, 0x21, 0 - .dw 0xb0c0, 0xc03e, 0xb0ff, 0xc03e, 0x21, 0 - .dw 0xb140, 0xc03e, 0xb17f, 0xc03e, 0x21, 0 - .dw 0xb1c0, 0xc03e, 0xb1ff, 0xc03e, 0x21, 0 - .dw 0xb240, 0xc03e, 0xb27f, 0xc03e, 0x21, 0 - .dw 0xb2c0, 0xc03e, 0xb2ff, 0xc03e, 0x21, 0 - .dw 0xb340, 0xc03e, 0xb37f, 0xc03e, 0x21, 0 - .dw 0xb3c0, 0xc03e, 0xb3ff, 0xc03e, 0x21, 0 - .dw 0xb440, 0xc03e, 0xb47f, 0xc03e, 0x21, 0 - .dw 0xb4c0, 0xc03e, 0xb4ff, 0xc03e, 0x21, 0 - .dw 0xb540, 0xc03e, 0xb57f, 0xc03e, 0x21, 0 - .dw 0xb5c0, 0xc03e, 0xb5ff, 0xc03e, 0x21, 0 - .dw 0xb640, 0xc03e, 0xb67f, 0xc03e, 0x21, 0 - .dw 0xb6c0, 0xc03e, 0xb6ff, 0xc03e, 0x21, 0 - .dw 0xb740, 0xc03e, 0xb77f, 0xc03e, 0x21, 0 - .dw 0xb7c0, 0xc03e, 0xb7ff, 0xc03e, 0x21, 0 - .dw 0xb840, 0xc03e, 0xb87f, 0xc03e, 0x21, 0 - .dw 0xb8c0, 0xc03e, 0xb8ff, 0xc03e, 0x21, 0 - .dw 0xb940, 0xc03e, 0xb97f, 0xc03e, 0x21, 0 - .dw 0xb9c0, 0xc03e, 0xbfff, 0xc03e, 0x21, 0 - .dw 0xc040, 0xc03e, 0xc07f, 0xc03e, 0x21, 0 - .dw 0xc0c0, 0xc03e, 0xc0ff, 0xc03e, 0x21, 0 - .dw 0xc140, 0xc03e, 0xc17f, 0xc03e, 0x21, 0 - .dw 0xc1c0, 0xc03e, 0xc1ff, 0xc03e, 0x21, 0 - .dw 0xc240, 0xc03e, 0xc27f, 0xc03e, 0x21, 0 - .dw 0xc2c0, 0xc03e, 0xc2ff, 0xc03e, 0x21, 0 - .dw 0xc340, 0xc03e, 0xc37f, 0xc03e, 0x21, 0 - .dw 0xc3c0, 0xc03e, 0xc3ff, 0xc03e, 0x21, 0 - .dw 0xc440, 0xc03e, 0xc47f, 0xc03e, 0x21, 0 - .dw 0xc4c0, 0xc03e, 0xc4ff, 0xc03e, 0x21, 0 - .dw 0xc540, 0xc03e, 0xc57f, 0xc03e, 0x21, 0 - .dw 0xc5c0, 0xc03e, 0xc5ff, 0xc03e, 0x21, 0 - .dw 0xc640, 0xc03e, 0xc67f, 0xc03e, 0x21, 0 - .dw 0xc6c0, 0xc03e, 0xc6ff, 0xc03e, 0x21, 0 - .dw 0xc740, 0xc03e, 0xc77f, 0xc03e, 0x21, 0 - .dw 0xc7c0, 0xc03e, 0xc7ff, 0xc03e, 0x21, 0 - .dw 0xc840, 0xc03e, 0xc87f, 0xc03e, 0x21, 0 - .dw 0xc8c0, 0xc03e, 0xc8ff, 0xc03e, 0x21, 0 - .dw 0xc940, 0xc03e, 0xc97f, 0xc03e, 0x21, 0 - .dw 0xc9c0, 0xc03e, 0xc9ff, 0xc03e, 0x21, 0 - .dw 0xca40, 0xc03e, 0xca7f, 0xc03e, 0x21, 0 - .dw 0xcac0, 0xc03e, 0xcaff, 0xc03e, 0x21, 0 - .dw 0xcb40, 0xc03e, 0xcb7f, 0xc03e, 0x21, 0 - .dw 0xcbc0, 0xc03e, 0xcbff, 0xc03e, 0x21, 0 - .dw 0xcc40, 0xc03e, 0xcc7f, 0xc03e, 0x21, 0 - .dw 0xccc0, 0xc03e, 0xccff, 0xc03e, 0x21, 0 - .dw 0xcd40, 0xc03e, 0xcd7f, 0xc03e, 0x21, 0 - .dw 0xcdc0, 0xc03e, 0xcdff, 0xc03e, 0x21, 0 - .dw 0xce40, 0xc03e, 0xce7f, 0xc03e, 0x21, 0 - .dw 0xcec0, 0xc03e, 0xceff, 0xc03e, 0x21, 0 - .dw 0xcf40, 0xc03e, 0xcf7f, 0xc03e, 0x21, 0 - .dw 0xcfc0, 0xc03e, 0xcfff, 0xc03e, 0x21, 0 - .dw 0xd040, 0xc03e, 0xd07f, 0xc03e, 0x21, 0 - .dw 0xd0c0, 0xc03e, 0xd0ff, 0xc03e, 0x21, 0 - .dw 0xd140, 0xc03e, 0xd17f, 0xc03e, 0x21, 0 - .dw 0xd1c0, 0xc03e, 0xd1ff, 0xc03e, 0x21, 0 - .dw 0xd240, 0xc03e, 0xd27f, 0xc03e, 0x21, 0 - .dw 0xd2c0, 0xc03e, 0xd2ff, 0xc03e, 0x21, 0 - .dw 0xd340, 0xc03e, 0xd37f, 0xc03e, 0x21, 0 - .dw 0xd3c0, 0xc03e, 0xd3ff, 0xc03e, 0x21, 0 - .dw 0xd440, 0xc03e, 0xd47f, 0xc03e, 0x21, 0 - .dw 0xd4c0, 0xc03e, 0xd4ff, 0xc03e, 0x21, 0 - .dw 0xd540, 0xc03e, 0xd57f, 0xc03e, 0x21, 0 - .dw 0xd5c0, 0xc03e, 0xd5ff, 0xc03e, 0x21, 0 - .dw 0xd640, 0xc03e, 0xd67f, 0xc03e, 0x21, 0 - .dw 0xd6c0, 0xc03e, 0xd6ff, 0xc03e, 0x21, 0 - .dw 0xd740, 0xc03e, 0xd77f, 0xc03e, 0x21, 0 - .dw 0xd7c0, 0xc03e, 0xd7ff, 0xc03e, 0x21, 0 - .dw 0xd840, 0xc03e, 0xd87f, 0xc03e, 0x21, 0 - .dw 0xd8c0, 0xc03e, 0xd8ff, 0xc03e, 0x21, 0 - .dw 0xd940, 0xc03e, 0xd97f, 0xc03e, 0x21, 0 - .dw 0xd9c0, 0xc03e, 0xdfff, 0xc03e, 0x21, 0 - .dw 0xe040, 0xc03e, 0xe07f, 0xc03e, 0x21, 0 - .dw 0xe0c0, 0xc03e, 0xe0ff, 0xc03e, 0x21, 0 - .dw 0xe140, 0xc03e, 0xe17f, 0xc03e, 0x21, 0 - .dw 0xe1c0, 0xc03e, 0xe1ff, 0xc03e, 0x21, 0 - .dw 0xe240, 0xc03e, 0xe27f, 0xc03e, 0x21, 0 - .dw 0xe2c0, 0xc03e, 0xe2ff, 0xc03e, 0x21, 0 - .dw 0xe340, 0xc03e, 0xe37f, 0xc03e, 0x21, 0 - .dw 0xe3c0, 0xc03e, 0xe3ff, 0xc03e, 0x21, 0 - .dw 0xe440, 0xc03e, 0xe47f, 0xc03e, 0x21, 0 - .dw 0xe4c0, 0xc03e, 0xe4ff, 0xc03e, 0x21, 0 - .dw 0xe540, 0xc03e, 0xe57f, 0xc03e, 0x21, 0 - .dw 0xe5c0, 0xc03e, 0xe5ff, 0xc03e, 0x21, 0 - .dw 0xe640, 0xc03e, 0xe67f, 0xc03e, 0x21, 0 - .dw 0xe6c0, 0xc03e, 0xe6ff, 0xc03e, 0x21, 0 - .dw 0xe740, 0xc03e, 0xe77f, 0xc03e, 0x21, 0 - .dw 0xe7c0, 0xc03e, 0xe7ff, 0xc03e, 0x21, 0 - .dw 0xe840, 0xc03e, 0xe87f, 0xc03e, 0x21, 0 - .dw 0xe8c0, 0xc03e, 0xe8ff, 0xc03e, 0x21, 0 - .dw 0xe940, 0xc03e, 0xe97f, 0xc03e, 0x21, 0 - .dw 0xe9c0, 0xc03e, 0xe9ff, 0xc03e, 0x21, 0 - .dw 0xea40, 0xc03e, 0xea7f, 0xc03e, 0x21, 0 - .dw 0xeac0, 0xc03e, 0xeaff, 0xc03e, 0x21, 0 - .dw 0xeb40, 0xc03e, 0xeb7f, 0xc03e, 0x21, 0 - .dw 0xebc0, 0xc03e, 0xebff, 0xc03e, 0x21, 0 - .dw 0xec40, 0xc03e, 0xec7f, 0xc03e, 0x21, 0 - .dw 0xecc0, 0xc03e, 0xecff, 0xc03e, 0x21, 0 - .dw 0xed40, 0xc03e, 0xed7f, 0xc03e, 0x21, 0 - .dw 0xedc0, 0xc03e, 0xedff, 0xc03e, 0x21, 0 - .dw 0xee40, 0xc03e, 0xee7f, 0xc03e, 0x21, 0 - .dw 0xeec0, 0xc03e, 0xeeff, 0xc03e, 0x21, 0 - .dw 0xef40, 0xc03e, 0xef7f, 0xc03e, 0x21, 0 - .dw 0xefc0, 0xc03e, 0xefff, 0xc03e, 0x21, 0 - .dw 0xf040, 0xc03e, 0xf07f, 0xc03e, 0x21, 0 - .dw 0xf0c0, 0xc03e, 0xf0ff, 0xc03e, 0x21, 0 - .dw 0xf140, 0xc03e, 0xf17f, 0xc03e, 0x21, 0 - .dw 0xf1c0, 0xc03e, 0xf1ff, 0xc03e, 0x21, 0 - .dw 0xf240, 0xc03e, 0xf27f, 0xc03e, 0x21, 0 - .dw 0xf2c0, 0xc03e, 0xf2ff, 0xc03e, 0x21, 0 - .dw 0xf340, 0xc03e, 0xf37f, 0xc03e, 0x21, 0 - .dw 0xf3c0, 0xc03e, 0xf3ff, 0xc03e, 0x21, 0 - .dw 0xf440, 0xc03e, 0xf47f, 0xc03e, 0x21, 0 - .dw 0xf4c0, 0xc03e, 0xf4ff, 0xc03e, 0x21, 0 - .dw 0xf540, 0xc03e, 0xf57f, 0xc03e, 0x21, 0 - .dw 0xf5c0, 0xc03e, 0xf5ff, 0xc03e, 0x21, 0 - .dw 0xf640, 0xc03e, 0xf67f, 0xc03e, 0x21, 0 - .dw 0xf6c0, 0xc03e, 0xf6ff, 0xc03e, 0x21, 0 - .dw 0xf740, 0xc03e, 0xf77f, 0xc03e, 0x21, 0 - .dw 0xf7c0, 0xc03e, 0xf7ff, 0xc03e, 0x21, 0 - .dw 0xf840, 0xc03e, 0xf87f, 0xc03e, 0x21, 0 - .dw 0xf8c0, 0xc03e, 0xf8ff, 0xc03e, 0x21, 0 - .dw 0xf940, 0xc03e, 0xf97f, 0xc03e, 0x21, 0 - .dw 0xf9c0, 0xc03e, 0xffff, 0xc03e, 0x21, 0 - .dw 0x0040, 0xc03f, 0x007f, 0xc03f, 0x21, 0 - .dw 0x00c0, 0xc03f, 0x00ff, 0xc03f, 0x21, 0 - .dw 0x0140, 0xc03f, 0x017f, 0xc03f, 0x21, 0 - .dw 0x01c0, 0xc03f, 0x01ff, 0xc03f, 0x21, 0 - .dw 0x0240, 0xc03f, 0x027f, 0xc03f, 0x21, 0 - .dw 0x02c0, 0xc03f, 0x02ff, 0xc03f, 0x21, 0 - .dw 0x0340, 0xc03f, 0x037f, 0xc03f, 0x21, 0 - .dw 0x03c0, 0xc03f, 0x03ff, 0xc03f, 0x21, 0 - .dw 0x0440, 0xc03f, 0x047f, 0xc03f, 0x21, 0 - .dw 0x04c0, 0xc03f, 0x04ff, 0xc03f, 0x21, 0 - .dw 0x0540, 0xc03f, 0x057f, 0xc03f, 0x21, 0 - .dw 0x05c0, 0xc03f, 0x05ff, 0xc03f, 0x21, 0 - .dw 0x0640, 0xc03f, 0x067f, 0xc03f, 0x21, 0 - .dw 0x06c0, 0xc03f, 0x06ff, 0xc03f, 0x21, 0 - .dw 0x0740, 0xc03f, 0x077f, 0xc03f, 0x21, 0 - .dw 0x07c0, 0xc03f, 0x07ff, 0xc03f, 0x21, 0 - .dw 0x0840, 0xc03f, 0x087f, 0xc03f, 0x21, 0 - .dw 0x08c0, 0xc03f, 0x08ff, 0xc03f, 0x21, 0 - .dw 0x0940, 0xc03f, 0x097f, 0xc03f, 0x21, 0 - .dw 0x09c0, 0xc03f, 0x09ff, 0xc03f, 0x21, 0 - .dw 0x0a40, 0xc03f, 0x0a7f, 0xc03f, 0x21, 0 - .dw 0x0ac0, 0xc03f, 0x0aff, 0xc03f, 0x21, 0 - .dw 0x0b40, 0xc03f, 0x0b7f, 0xc03f, 0x21, 0 - .dw 0x0bc0, 0xc03f, 0x0bff, 0xc03f, 0x21, 0 - .dw 0x0c40, 0xc03f, 0x0c7f, 0xc03f, 0x21, 0 - .dw 0x0cc0, 0xc03f, 0x0cff, 0xc03f, 0x21, 0 - .dw 0x0d40, 0xc03f, 0x0d7f, 0xc03f, 0x21, 0 - .dw 0x0dc0, 0xc03f, 0x0dff, 0xc03f, 0x21, 0 - .dw 0x0e40, 0xc03f, 0x0e7f, 0xc03f, 0x21, 0 - .dw 0x0ec0, 0xc03f, 0x0eff, 0xc03f, 0x21, 0 - .dw 0x0f40, 0xc03f, 0x0f7f, 0xc03f, 0x21, 0 - .dw 0x0fc0, 0xc03f, 0x0fff, 0xc03f, 0x21, 0 - .dw 0x1040, 0xc03f, 0x107f, 0xc03f, 0x21, 0 - .dw 0x10c0, 0xc03f, 0x10ff, 0xc03f, 0x21, 0 - .dw 0x1140, 0xc03f, 0x117f, 0xc03f, 0x21, 0 - .dw 0x11c0, 0xc03f, 0x11ff, 0xc03f, 0x21, 0 - .dw 0x1240, 0xc03f, 0x127f, 0xc03f, 0x21, 0 - .dw 0x12c0, 0xc03f, 0x12ff, 0xc03f, 0x21, 0 - .dw 0x1340, 0xc03f, 0x137f, 0xc03f, 0x21, 0 - .dw 0x13c0, 0xc03f, 0x13ff, 0xc03f, 0x21, 0 - .dw 0x1440, 0xc03f, 0x147f, 0xc03f, 0x21, 0 - .dw 0x14c0, 0xc03f, 0x14ff, 0xc03f, 0x21, 0 - .dw 0x1540, 0xc03f, 0x157f, 0xc03f, 0x21, 0 - .dw 0x15c0, 0xc03f, 0x15ff, 0xc03f, 0x21, 0 - .dw 0x1640, 0xc03f, 0x167f, 0xc03f, 0x21, 0 - .dw 0x16c0, 0xc03f, 0x16ff, 0xc03f, 0x21, 0 - .dw 0x1740, 0xc03f, 0x177f, 0xc03f, 0x21, 0 - .dw 0x17c0, 0xc03f, 0x17ff, 0xc03f, 0x21, 0 - .dw 0x1840, 0xc03f, 0x187f, 0xc03f, 0x21, 0 - .dw 0x18c0, 0xc03f, 0x18ff, 0xc03f, 0x21, 0 - .dw 0x1940, 0xc03f, 0x197f, 0xc03f, 0x21, 0 - .dw 0x19c0, 0xc03f, 0x1fff, 0xc03f, 0x21, 0 - .dw 0x2040, 0xc03f, 0x207f, 0xc03f, 0x21, 0 - .dw 0x20c0, 0xc03f, 0x20ff, 0xc03f, 0x21, 0 - .dw 0x2140, 0xc03f, 0x217f, 0xc03f, 0x21, 0 - .dw 0x21c0, 0xc03f, 0x21ff, 0xc03f, 0x21, 0 - .dw 0x2240, 0xc03f, 0x227f, 0xc03f, 0x21, 0 - .dw 0x22c0, 0xc03f, 0x22ff, 0xc03f, 0x21, 0 - .dw 0x2340, 0xc03f, 0x237f, 0xc03f, 0x21, 0 - .dw 0x23c0, 0xc03f, 0x23ff, 0xc03f, 0x21, 0 - .dw 0x2440, 0xc03f, 0x247f, 0xc03f, 0x21, 0 - .dw 0x24c0, 0xc03f, 0x24ff, 0xc03f, 0x21, 0 - .dw 0x2540, 0xc03f, 0x257f, 0xc03f, 0x21, 0 - .dw 0x25c0, 0xc03f, 0x25ff, 0xc03f, 0x21, 0 - .dw 0x2640, 0xc03f, 0x267f, 0xc03f, 0x21, 0 - .dw 0x26c0, 0xc03f, 0x26ff, 0xc03f, 0x21, 0 - .dw 0x2740, 0xc03f, 0x277f, 0xc03f, 0x21, 0 - .dw 0x27c0, 0xc03f, 0x27ff, 0xc03f, 0x21, 0 - .dw 0x2840, 0xc03f, 0x287f, 0xc03f, 0x21, 0 - .dw 0x28c0, 0xc03f, 0x28ff, 0xc03f, 0x21, 0 - .dw 0x2940, 0xc03f, 0x297f, 0xc03f, 0x21, 0 - .dw 0x29c0, 0xc03f, 0x29ff, 0xc03f, 0x21, 0 - .dw 0x2a40, 0xc03f, 0x2a7f, 0xc03f, 0x21, 0 - .dw 0x2ac0, 0xc03f, 0x2aff, 0xc03f, 0x21, 0 - .dw 0x2b40, 0xc03f, 0x2b7f, 0xc03f, 0x21, 0 - .dw 0x2bc0, 0xc03f, 0x2bff, 0xc03f, 0x21, 0 - .dw 0x2c40, 0xc03f, 0x2c7f, 0xc03f, 0x21, 0 - .dw 0x2cc0, 0xc03f, 0x2cff, 0xc03f, 0x21, 0 - .dw 0x2d40, 0xc03f, 0x2d7f, 0xc03f, 0x21, 0 - .dw 0x2dc0, 0xc03f, 0x2dff, 0xc03f, 0x21, 0 - .dw 0x2e40, 0xc03f, 0x2e7f, 0xc03f, 0x21, 0 - .dw 0x2ec0, 0xc03f, 0x2eff, 0xc03f, 0x21, 0 - .dw 0x2f40, 0xc03f, 0x2f7f, 0xc03f, 0x21, 0 - .dw 0x2fc0, 0xc03f, 0x2fff, 0xc03f, 0x21, 0 - .dw 0x3040, 0xc03f, 0x307f, 0xc03f, 0x21, 0 - .dw 0x30c0, 0xc03f, 0x30ff, 0xc03f, 0x21, 0 - .dw 0x3140, 0xc03f, 0x317f, 0xc03f, 0x21, 0 - .dw 0x31c0, 0xc03f, 0x31ff, 0xc03f, 0x21, 0 - .dw 0x3240, 0xc03f, 0x327f, 0xc03f, 0x21, 0 - .dw 0x32c0, 0xc03f, 0x32ff, 0xc03f, 0x21, 0 - .dw 0x3340, 0xc03f, 0x337f, 0xc03f, 0x21, 0 - .dw 0x33c0, 0xc03f, 0x33ff, 0xc03f, 0x21, 0 - .dw 0x3440, 0xc03f, 0x347f, 0xc03f, 0x21, 0 - .dw 0x34c0, 0xc03f, 0x34ff, 0xc03f, 0x21, 0 - .dw 0x3540, 0xc03f, 0x357f, 0xc03f, 0x21, 0 - .dw 0x35c0, 0xc03f, 0x35ff, 0xc03f, 0x21, 0 - .dw 0x3640, 0xc03f, 0x367f, 0xc03f, 0x21, 0 - .dw 0x36c0, 0xc03f, 0x36ff, 0xc03f, 0x21, 0 - .dw 0x3740, 0xc03f, 0x377f, 0xc03f, 0x21, 0 - .dw 0x37c0, 0xc03f, 0x37ff, 0xc03f, 0x21, 0 - .dw 0x3840, 0xc03f, 0x387f, 0xc03f, 0x21, 0 - .dw 0x38c0, 0xc03f, 0x38ff, 0xc03f, 0x21, 0 - .dw 0x3940, 0xc03f, 0x397f, 0xc03f, 0x21, 0 - .dw 0x39c0, 0xc03f, 0x1fff, 0xc040, 0x21, 0 - .dw 0x3a00, 0xc040, 0x5fff, 0xc040, 0x21, 0 - .dw 0x7a00, 0xc040, 0x9fff, 0xc040, 0x21, 0 - .dw 0xba00, 0xc040, 0xdfff, 0xc040, 0x21, 0 - .dw 0xfa00, 0xc040, 0x1fff, 0xc041, 0x21, 0 - .dw 0x3a00, 0xc041, 0x5fff, 0xc041, 0x21, 0 - .dw 0x7a00, 0xc041, 0x9fff, 0xc041, 0x21, 0 - .dw 0xba00, 0xc041, 0xdfff, 0xc041, 0x21, 0 - .dw 0xfa00, 0xc041, 0x1fff, 0xc042, 0x21, 0 - .dw 0x3a00, 0xc042, 0x5fff, 0xc042, 0x21, 0 - .dw 0x7a00, 0xc042, 0x9fff, 0xc042, 0x21, 0 - .dw 0xba00, 0xc042, 0xdfff, 0xc042, 0x21, 0 - .dw 0xfa00, 0xc042, 0x1fff, 0xc043, 0x21, 0 - .dw 0x3a00, 0xc043, 0xffff, 0xc043, 0x21, 0 - .dw 0x1a00, 0xc044, 0x1fff, 0xc044, 0x21, 0 - .dw 0x3a00, 0xc044, 0x3fff, 0xc044, 0x21, 0 - .dw 0x5a00, 0xc044, 0x5fff, 0xc044, 0x21, 0 - .dw 0x7a00, 0xc044, 0x7fff, 0xc044, 0x21, 0 - .dw 0x9a00, 0xc044, 0x9fff, 0xc044, 0x21, 0 - .dw 0xba00, 0xc044, 0xbfff, 0xc044, 0x21, 0 - .dw 0xda00, 0xc044, 0xdfff, 0xc044, 0x21, 0 - .dw 0xfa00, 0xc044, 0xffff, 0xc044, 0x21, 0 - .dw 0x1a00, 0xc045, 0x1fff, 0xc045, 0x21, 0 - .dw 0x3a00, 0xc045, 0x3fff, 0xc045, 0x21, 0 - .dw 0x5a00, 0xc045, 0x5fff, 0xc045, 0x21, 0 - .dw 0x7a00, 0xc045, 0x7fff, 0xc045, 0x21, 0 - .dw 0x9a00, 0xc045, 0x9fff, 0xc045, 0x21, 0 - .dw 0xba00, 0xc045, 0xbfff, 0xc045, 0x21, 0 - .dw 0xda00, 0xc045, 0xdfff, 0xc045, 0x21, 0 - .dw 0xfa00, 0xc045, 0xffff, 0xc045, 0x21, 0 - .dw 0x1a00, 0xc046, 0x1fff, 0xc046, 0x21, 0 - .dw 0x3a00, 0xc046, 0x3fff, 0xc046, 0x21, 0 - .dw 0x5a00, 0xc046, 0x5fff, 0xc046, 0x21, 0 - .dw 0x7a00, 0xc046, 0x7fff, 0xc046, 0x21, 0 - .dw 0x9a00, 0xc046, 0x9fff, 0xc046, 0x21, 0 - .dw 0xba00, 0xc046, 0xbfff, 0xc046, 0x21, 0 - .dw 0xda00, 0xc046, 0xdfff, 0xc046, 0x21, 0 - .dw 0xfa00, 0xc046, 0xffff, 0xc046, 0x21, 0 - .dw 0x1a00, 0xc047, 0x1fff, 0xc047, 0x21, 0 - .dw 0x3a00, 0xc047, 0x1fff, 0xc050, 0x21, 0 - .dw 0x3a00, 0xc050, 0x5fff, 0xc050, 0x21, 0 - .dw 0x7a00, 0xc050, 0x9fff, 0xc050, 0x21, 0 - .dw 0xba00, 0xc050, 0xdfff, 0xc050, 0x21, 0 - .dw 0xfa00, 0xc050, 0x1fff, 0xc051, 0x21, 0 - .dw 0x3a00, 0xc051, 0x5fff, 0xc051, 0x21, 0 - .dw 0x7a00, 0xc051, 0x9fff, 0xc051, 0x21, 0 - .dw 0xba00, 0xc051, 0xdfff, 0xc051, 0x21, 0 - .dw 0xfa00, 0xc051, 0x1fff, 0xc052, 0x21, 0 - .dw 0x3a00, 0xc052, 0x5fff, 0xc052, 0x21, 0 - .dw 0x7a00, 0xc052, 0x9fff, 0xc052, 0x21, 0 - .dw 0xba00, 0xc052, 0xdfff, 0xc052, 0x21, 0 - .dw 0xfa00, 0xc052, 0xffff, 0xc053, 0x21, 0 - .dw 0x1a00, 0xc054, 0x1fff, 0xc054, 0x21, 0 - .dw 0x3a00, 0xc054, 0x3fff, 0xc054, 0x21, 0 - .dw 0x5a00, 0xc054, 0x5fff, 0xc054, 0x21, 0 - .dw 0x7a00, 0xc054, 0x7fff, 0xc054, 0x21, 0 - .dw 0x9a00, 0xc054, 0x9fff, 0xc054, 0x21, 0 - .dw 0xba00, 0xc054, 0xbfff, 0xc054, 0x21, 0 - .dw 0xda00, 0xc054, 0xdfff, 0xc054, 0x21, 0 - .dw 0xfa00, 0xc054, 0xffff, 0xc054, 0x21, 0 - .dw 0x1a00, 0xc055, 0x1fff, 0xc055, 0x21, 0 - .dw 0x3a00, 0xc055, 0x3fff, 0xc055, 0x21, 0 - .dw 0x5a00, 0xc055, 0x5fff, 0xc055, 0x21, 0 - .dw 0x7a00, 0xc055, 0x7fff, 0xc055, 0x21, 0 - .dw 0x9a00, 0xc055, 0x9fff, 0xc055, 0x21, 0 - .dw 0xba00, 0xc055, 0xbfff, 0xc055, 0x21, 0 - .dw 0xda00, 0xc055, 0xdfff, 0xc055, 0x21, 0 - .dw 0xfa00, 0xc055, 0xffff, 0xc055, 0x21, 0 - .dw 0x1a00, 0xc056, 0x1fff, 0xc056, 0x21, 0 - .dw 0x3a00, 0xc056, 0x3fff, 0xc056, 0x21, 0 - .dw 0x5a00, 0xc056, 0x5fff, 0xc056, 0x21, 0 - .dw 0x7a00, 0xc056, 0x7fff, 0xc056, 0x21, 0 - .dw 0x9a00, 0xc056, 0x9fff, 0xc056, 0x21, 0 - .dw 0xba00, 0xc056, 0xbfff, 0xc056, 0x21, 0 - .dw 0xda00, 0xc056, 0xdfff, 0xc056, 0x21, 0 - .dw 0xfa00, 0xc056, 0xffff, 0xc056, 0x21, 0 - .dw 0x1a00, 0xc057, 0x1fff, 0xc057, 0x21, 0 - .dw 0x3a00, 0xc057, 0xffff, 0xc05f, 0x21, 0 - .dw 0x1a00, 0xc060, 0x3fff, 0xc060, 0x21, 0 - .dw 0x5a00, 0xc060, 0x7fff, 0xc060, 0x21, 0 - .dw 0x9a00, 0xc060, 0xbfff, 0xc060, 0x21, 0 - .dw 0xda00, 0xc060, 0xffff, 0xc060, 0x21, 0 - .dw 0x1a00, 0xc061, 0x3fff, 0xc061, 0x21, 0 - .dw 0x5a00, 0xc061, 0x7fff, 0xc061, 0x21, 0 - .dw 0x9a00, 0xc061, 0xbfff, 0xc061, 0x21, 0 - .dw 0xda00, 0xc061, 0xffff, 0xc061, 0x21, 0 - .dw 0x1a00, 0xc062, 0x3fff, 0xc062, 0x21, 0 - .dw 0x5a00, 0xc062, 0x7fff, 0xc062, 0x21, 0 - .dw 0x9a00, 0xc062, 0xbfff, 0xc062, 0x21, 0 - .dw 0xda00, 0xc062, 0xffff, 0xc062, 0x21, 0 - .dw 0x1a00, 0xc063, 0xffff, 0xc06f, 0x21, 0 - .dw 0x1a00, 0xc070, 0x3fff, 0xc070, 0x21, 0 - .dw 0x5a00, 0xc070, 0x7fff, 0xc070, 0x21, 0 - .dw 0x9a00, 0xc070, 0xbfff, 0xc070, 0x21, 0 - .dw 0xda00, 0xc070, 0xffff, 0xc070, 0x21, 0 - .dw 0x1a00, 0xc071, 0x3fff, 0xc071, 0x21, 0 - .dw 0x5a00, 0xc071, 0x7fff, 0xc071, 0x21, 0 - .dw 0x9a00, 0xc071, 0xbfff, 0xc071, 0x21, 0 - .dw 0xda00, 0xc071, 0xffff, 0xc071, 0x21, 0 - .dw 0x1a00, 0xc072, 0x3fff, 0xc072, 0x21, 0 - .dw 0x5a00, 0xc072, 0x7fff, 0xc072, 0x21, 0 - .dw 0x9a00, 0xc072, 0xbfff, 0xc072, 0x21, 0 - .dw 0xda00, 0xc072, 0xffff, 0xc07f, 0x21, 0 - .dw 0x1a00, 0xc080, 0x1fff, 0xc080, 0x21, 0 - .dw 0x3a00, 0xc080, 0x3fff, 0xc080, 0x21, 0 - .dw 0x5a00, 0xc080, 0x5fff, 0xc080, 0x21, 0 - .dw 0x7a00, 0xc080, 0x7fff, 0xc080, 0x21, 0 - .dw 0x9a00, 0xc080, 0x9fff, 0xc080, 0x21, 0 - .dw 0xba00, 0xc080, 0xbfff, 0xc080, 0x21, 0 - .dw 0xda00, 0xc080, 0xdfff, 0xc080, 0x21, 0 - .dw 0xfa00, 0xc080, 0xffff, 0xc080, 0x21, 0 - .dw 0x1a00, 0xc081, 0x1fff, 0xc081, 0x21, 0 - .dw 0x3a00, 0xc081, 0x3fff, 0xc081, 0x21, 0 - .dw 0x5a00, 0xc081, 0x5fff, 0xc081, 0x21, 0 - .dw 0x7a00, 0xc081, 0x7fff, 0xc081, 0x21, 0 - .dw 0x9a00, 0xc081, 0x9fff, 0xc081, 0x21, 0 - .dw 0xba00, 0xc081, 0xbfff, 0xc081, 0x21, 0 - .dw 0xda00, 0xc081, 0xdfff, 0xc081, 0x21, 0 - .dw 0xfa00, 0xc081, 0xffff, 0xc081, 0x21, 0 - .dw 0x1a00, 0xc082, 0x1fff, 0xc082, 0x21, 0 - .dw 0x3a00, 0xc082, 0x3fff, 0xc082, 0x21, 0 - .dw 0x5a00, 0xc082, 0x5fff, 0xc082, 0x21, 0 - .dw 0x7a00, 0xc082, 0x7fff, 0xc082, 0x21, 0 - .dw 0x9a00, 0xc082, 0x9fff, 0xc082, 0x21, 0 - .dw 0xba00, 0xc082, 0xbfff, 0xc082, 0x21, 0 - .dw 0xda00, 0xc082, 0xdfff, 0xc082, 0x21, 0 - .dw 0xfa00, 0xc082, 0xffff, 0xc082, 0x21, 0 - .dw 0x1a00, 0xc083, 0x1fff, 0xc083, 0x21, 0 - .dw 0x3a00, 0xc083, 0xffff, 0xc083, 0x21, 0 - .dw 0x1a00, 0xc084, 0x1fff, 0xc084, 0x21, 0 - .dw 0x3a00, 0xc084, 0x3fff, 0xc084, 0x21, 0 - .dw 0x5a00, 0xc084, 0x5fff, 0xc084, 0x21, 0 - .dw 0x7a00, 0xc084, 0x7fff, 0xc084, 0x21, 0 - .dw 0x9a00, 0xc084, 0x9fff, 0xc084, 0x21, 0 - .dw 0xba00, 0xc084, 0xbfff, 0xc084, 0x21, 0 - .dw 0xda00, 0xc084, 0xdfff, 0xc084, 0x21, 0 - .dw 0xfa00, 0xc084, 0xffff, 0xc084, 0x21, 0 - .dw 0x1a00, 0xc085, 0x1fff, 0xc085, 0x21, 0 - .dw 0x3a00, 0xc085, 0x3fff, 0xc085, 0x21, 0 - .dw 0x5a00, 0xc085, 0x5fff, 0xc085, 0x21, 0 - .dw 0x7a00, 0xc085, 0x7fff, 0xc085, 0x21, 0 - .dw 0x9a00, 0xc085, 0x9fff, 0xc085, 0x21, 0 - .dw 0xba00, 0xc085, 0xbfff, 0xc085, 0x21, 0 - .dw 0xda00, 0xc085, 0xdfff, 0xc085, 0x21, 0 - .dw 0xfa00, 0xc085, 0xffff, 0xc085, 0x21, 0 - .dw 0x1a00, 0xc086, 0x1fff, 0xc086, 0x21, 0 - .dw 0x3a00, 0xc086, 0x3fff, 0xc086, 0x21, 0 - .dw 0x5a00, 0xc086, 0x5fff, 0xc086, 0x21, 0 - .dw 0x7a00, 0xc086, 0x7fff, 0xc086, 0x21, 0 - .dw 0x9a00, 0xc086, 0x9fff, 0xc086, 0x21, 0 - .dw 0xba00, 0xc086, 0xbfff, 0xc086, 0x21, 0 - .dw 0xda00, 0xc086, 0xdfff, 0xc086, 0x21, 0 - .dw 0xfa00, 0xc086, 0xffff, 0xc086, 0x21, 0 - .dw 0x1a00, 0xc087, 0x1fff, 0xc087, 0x21, 0 - .dw 0x3a00, 0xc087, 0x1fff, 0xc088, 0x21, 0 - .dw 0x2040, 0xc088, 0x207f, 0xc088, 0x21, 0 - .dw 0x20c0, 0xc088, 0x20ff, 0xc088, 0x21, 0 - .dw 0x2140, 0xc088, 0x217f, 0xc088, 0x21, 0 - .dw 0x21c0, 0xc088, 0x21ff, 0xc088, 0x21, 0 - .dw 0x2240, 0xc088, 0x227f, 0xc088, 0x21, 0 - .dw 0x22c0, 0xc088, 0x22ff, 0xc088, 0x21, 0 - .dw 0x2340, 0xc088, 0x237f, 0xc088, 0x21, 0 - .dw 0x23c0, 0xc088, 0x23ff, 0xc088, 0x21, 0 - .dw 0x2440, 0xc088, 0x247f, 0xc088, 0x21, 0 - .dw 0x24c0, 0xc088, 0x24ff, 0xc088, 0x21, 0 - .dw 0x2540, 0xc088, 0x257f, 0xc088, 0x21, 0 - .dw 0x25c0, 0xc088, 0x25ff, 0xc088, 0x21, 0 - .dw 0x2640, 0xc088, 0x267f, 0xc088, 0x21, 0 - .dw 0x26c0, 0xc088, 0x26ff, 0xc088, 0x21, 0 - .dw 0x2740, 0xc088, 0x277f, 0xc088, 0x21, 0 - .dw 0x27c0, 0xc088, 0x27ff, 0xc088, 0x21, 0 - .dw 0x2840, 0xc088, 0x287f, 0xc088, 0x21, 0 - .dw 0x28c0, 0xc088, 0x28ff, 0xc088, 0x21, 0 - .dw 0x2940, 0xc088, 0x297f, 0xc088, 0x21, 0 - .dw 0x29c0, 0xc088, 0x29ff, 0xc088, 0x21, 0 - .dw 0x2a40, 0xc088, 0x2a7f, 0xc088, 0x21, 0 - .dw 0x2ac0, 0xc088, 0x2aff, 0xc088, 0x21, 0 - .dw 0x2b40, 0xc088, 0x2b7f, 0xc088, 0x21, 0 - .dw 0x2bc0, 0xc088, 0x2bff, 0xc088, 0x21, 0 - .dw 0x2c40, 0xc088, 0x2c7f, 0xc088, 0x21, 0 - .dw 0x2cc0, 0xc088, 0x2cff, 0xc088, 0x21, 0 - .dw 0x2d40, 0xc088, 0x2d7f, 0xc088, 0x21, 0 - .dw 0x2dc0, 0xc088, 0x2dff, 0xc088, 0x21, 0 - .dw 0x2e40, 0xc088, 0x2e7f, 0xc088, 0x21, 0 - .dw 0x2ec0, 0xc088, 0x2eff, 0xc088, 0x21, 0 - .dw 0x2f40, 0xc088, 0x2f7f, 0xc088, 0x21, 0 - .dw 0x2fc0, 0xc088, 0x2fff, 0xc088, 0x21, 0 - .dw 0x3040, 0xc088, 0x307f, 0xc088, 0x21, 0 - .dw 0x30c0, 0xc088, 0x30ff, 0xc088, 0x21, 0 - .dw 0x3140, 0xc088, 0x317f, 0xc088, 0x21, 0 - .dw 0x31c0, 0xc088, 0x31ff, 0xc088, 0x21, 0 - .dw 0x3240, 0xc088, 0x327f, 0xc088, 0x21, 0 - .dw 0x32c0, 0xc088, 0x32ff, 0xc088, 0x21, 0 - .dw 0x3340, 0xc088, 0x337f, 0xc088, 0x21, 0 - .dw 0x33c0, 0xc088, 0x33ff, 0xc088, 0x21, 0 - .dw 0x3440, 0xc088, 0x347f, 0xc088, 0x21, 0 - .dw 0x34c0, 0xc088, 0x34ff, 0xc088, 0x21, 0 - .dw 0x3540, 0xc088, 0x357f, 0xc088, 0x21, 0 - .dw 0x35c0, 0xc088, 0x35ff, 0xc088, 0x21, 0 - .dw 0x3640, 0xc088, 0x367f, 0xc088, 0x21, 0 - .dw 0x36c0, 0xc088, 0x36ff, 0xc088, 0x21, 0 - .dw 0x3740, 0xc088, 0x377f, 0xc088, 0x21, 0 - .dw 0x37c0, 0xc088, 0x37ff, 0xc088, 0x21, 0 - .dw 0x3840, 0xc088, 0x387f, 0xc088, 0x21, 0 - .dw 0x38c0, 0xc088, 0x38ff, 0xc088, 0x21, 0 - .dw 0x3940, 0xc088, 0x397f, 0xc088, 0x21, 0 - .dw 0x39c0, 0xc088, 0x5fff, 0xc088, 0x21, 0 - .dw 0x6040, 0xc088, 0x607f, 0xc088, 0x21, 0 - .dw 0x60c0, 0xc088, 0x60ff, 0xc088, 0x21, 0 - .dw 0x6140, 0xc088, 0x617f, 0xc088, 0x21, 0 - .dw 0x61c0, 0xc088, 0x61ff, 0xc088, 0x21, 0 - .dw 0x6240, 0xc088, 0x627f, 0xc088, 0x21, 0 - .dw 0x62c0, 0xc088, 0x62ff, 0xc088, 0x21, 0 - .dw 0x6340, 0xc088, 0x637f, 0xc088, 0x21, 0 - .dw 0x63c0, 0xc088, 0x63ff, 0xc088, 0x21, 0 - .dw 0x6440, 0xc088, 0x647f, 0xc088, 0x21, 0 - .dw 0x64c0, 0xc088, 0x64ff, 0xc088, 0x21, 0 - .dw 0x6540, 0xc088, 0x657f, 0xc088, 0x21, 0 - .dw 0x65c0, 0xc088, 0x65ff, 0xc088, 0x21, 0 - .dw 0x6640, 0xc088, 0x667f, 0xc088, 0x21, 0 - .dw 0x66c0, 0xc088, 0x66ff, 0xc088, 0x21, 0 - .dw 0x6740, 0xc088, 0x677f, 0xc088, 0x21, 0 - .dw 0x67c0, 0xc088, 0x67ff, 0xc088, 0x21, 0 - .dw 0x6840, 0xc088, 0x687f, 0xc088, 0x21, 0 - .dw 0x68c0, 0xc088, 0x68ff, 0xc088, 0x21, 0 - .dw 0x6940, 0xc088, 0x697f, 0xc088, 0x21, 0 - .dw 0x69c0, 0xc088, 0x69ff, 0xc088, 0x21, 0 - .dw 0x6a40, 0xc088, 0x6a7f, 0xc088, 0x21, 0 - .dw 0x6ac0, 0xc088, 0x6aff, 0xc088, 0x21, 0 - .dw 0x6b40, 0xc088, 0x6b7f, 0xc088, 0x21, 0 - .dw 0x6bc0, 0xc088, 0x6bff, 0xc088, 0x21, 0 - .dw 0x6c40, 0xc088, 0x6c7f, 0xc088, 0x21, 0 - .dw 0x6cc0, 0xc088, 0x6cff, 0xc088, 0x21, 0 - .dw 0x6d40, 0xc088, 0x6d7f, 0xc088, 0x21, 0 - .dw 0x6dc0, 0xc088, 0x6dff, 0xc088, 0x21, 0 - .dw 0x6e40, 0xc088, 0x6e7f, 0xc088, 0x21, 0 - .dw 0x6ec0, 0xc088, 0x6eff, 0xc088, 0x21, 0 - .dw 0x6f40, 0xc088, 0x6f7f, 0xc088, 0x21, 0 - .dw 0x6fc0, 0xc088, 0x6fff, 0xc088, 0x21, 0 - .dw 0x7040, 0xc088, 0x707f, 0xc088, 0x21, 0 - .dw 0x70c0, 0xc088, 0x70ff, 0xc088, 0x21, 0 - .dw 0x7140, 0xc088, 0x717f, 0xc088, 0x21, 0 - .dw 0x71c0, 0xc088, 0x71ff, 0xc088, 0x21, 0 - .dw 0x7240, 0xc088, 0x727f, 0xc088, 0x21, 0 - .dw 0x72c0, 0xc088, 0x72ff, 0xc088, 0x21, 0 - .dw 0x7340, 0xc088, 0x737f, 0xc088, 0x21, 0 - .dw 0x73c0, 0xc088, 0x73ff, 0xc088, 0x21, 0 - .dw 0x7440, 0xc088, 0x747f, 0xc088, 0x21, 0 - .dw 0x74c0, 0xc088, 0x74ff, 0xc088, 0x21, 0 - .dw 0x7540, 0xc088, 0x757f, 0xc088, 0x21, 0 - .dw 0x75c0, 0xc088, 0x75ff, 0xc088, 0x21, 0 - .dw 0x7640, 0xc088, 0x767f, 0xc088, 0x21, 0 - .dw 0x76c0, 0xc088, 0x76ff, 0xc088, 0x21, 0 - .dw 0x7740, 0xc088, 0x777f, 0xc088, 0x21, 0 - .dw 0x77c0, 0xc088, 0x77ff, 0xc088, 0x21, 0 - .dw 0x7840, 0xc088, 0x787f, 0xc088, 0x21, 0 - .dw 0x78c0, 0xc088, 0x78ff, 0xc088, 0x21, 0 - .dw 0x7940, 0xc088, 0x797f, 0xc088, 0x21, 0 - .dw 0x79c0, 0xc088, 0x9fff, 0xc088, 0x21, 0 - .dw 0xa040, 0xc088, 0xa07f, 0xc088, 0x21, 0 - .dw 0xa0c0, 0xc088, 0xa0ff, 0xc088, 0x21, 0 - .dw 0xa140, 0xc088, 0xa17f, 0xc088, 0x21, 0 - .dw 0xa1c0, 0xc088, 0xa1ff, 0xc088, 0x21, 0 - .dw 0xa240, 0xc088, 0xa27f, 0xc088, 0x21, 0 - .dw 0xa2c0, 0xc088, 0xa2ff, 0xc088, 0x21, 0 - .dw 0xa340, 0xc088, 0xa37f, 0xc088, 0x21, 0 - .dw 0xa3c0, 0xc088, 0xa3ff, 0xc088, 0x21, 0 - .dw 0xa440, 0xc088, 0xa47f, 0xc088, 0x21, 0 - .dw 0xa4c0, 0xc088, 0xa4ff, 0xc088, 0x21, 0 - .dw 0xa540, 0xc088, 0xa57f, 0xc088, 0x21, 0 - .dw 0xa5c0, 0xc088, 0xa5ff, 0xc088, 0x21, 0 - .dw 0xa640, 0xc088, 0xa67f, 0xc088, 0x21, 0 - .dw 0xa6c0, 0xc088, 0xa6ff, 0xc088, 0x21, 0 - .dw 0xa740, 0xc088, 0xa77f, 0xc088, 0x21, 0 - .dw 0xa7c0, 0xc088, 0xa7ff, 0xc088, 0x21, 0 - .dw 0xa840, 0xc088, 0xa87f, 0xc088, 0x21, 0 - .dw 0xa8c0, 0xc088, 0xa8ff, 0xc088, 0x21, 0 - .dw 0xa940, 0xc088, 0xa97f, 0xc088, 0x21, 0 - .dw 0xa9c0, 0xc088, 0xa9ff, 0xc088, 0x21, 0 - .dw 0xaa40, 0xc088, 0xaa7f, 0xc088, 0x21, 0 - .dw 0xaac0, 0xc088, 0xaaff, 0xc088, 0x21, 0 - .dw 0xab40, 0xc088, 0xab7f, 0xc088, 0x21, 0 - .dw 0xabc0, 0xc088, 0xabff, 0xc088, 0x21, 0 - .dw 0xac40, 0xc088, 0xac7f, 0xc088, 0x21, 0 - .dw 0xacc0, 0xc088, 0xacff, 0xc088, 0x21, 0 - .dw 0xad40, 0xc088, 0xad7f, 0xc088, 0x21, 0 - .dw 0xadc0, 0xc088, 0xadff, 0xc088, 0x21, 0 - .dw 0xae40, 0xc088, 0xae7f, 0xc088, 0x21, 0 - .dw 0xaec0, 0xc088, 0xaeff, 0xc088, 0x21, 0 - .dw 0xaf40, 0xc088, 0xaf7f, 0xc088, 0x21, 0 - .dw 0xafc0, 0xc088, 0xafff, 0xc088, 0x21, 0 - .dw 0xb040, 0xc088, 0xb07f, 0xc088, 0x21, 0 - .dw 0xb0c0, 0xc088, 0xb0ff, 0xc088, 0x21, 0 - .dw 0xb140, 0xc088, 0xb17f, 0xc088, 0x21, 0 - .dw 0xb1c0, 0xc088, 0xb1ff, 0xc088, 0x21, 0 - .dw 0xb240, 0xc088, 0xb27f, 0xc088, 0x21, 0 - .dw 0xb2c0, 0xc088, 0xb2ff, 0xc088, 0x21, 0 - .dw 0xb340, 0xc088, 0xb37f, 0xc088, 0x21, 0 - .dw 0xb3c0, 0xc088, 0xb3ff, 0xc088, 0x21, 0 - .dw 0xb440, 0xc088, 0xb47f, 0xc088, 0x21, 0 - .dw 0xb4c0, 0xc088, 0xb4ff, 0xc088, 0x21, 0 - .dw 0xb540, 0xc088, 0xb57f, 0xc088, 0x21, 0 - .dw 0xb5c0, 0xc088, 0xb5ff, 0xc088, 0x21, 0 - .dw 0xb640, 0xc088, 0xb67f, 0xc088, 0x21, 0 - .dw 0xb6c0, 0xc088, 0xb6ff, 0xc088, 0x21, 0 - .dw 0xb740, 0xc088, 0xb77f, 0xc088, 0x21, 0 - .dw 0xb7c0, 0xc088, 0xb7ff, 0xc088, 0x21, 0 - .dw 0xb840, 0xc088, 0xb87f, 0xc088, 0x21, 0 - .dw 0xb8c0, 0xc088, 0xb8ff, 0xc088, 0x21, 0 - .dw 0xb940, 0xc088, 0xb97f, 0xc088, 0x21, 0 - .dw 0xb9c0, 0xc088, 0xdfff, 0xc088, 0x21, 0 - .dw 0xe040, 0xc088, 0xe07f, 0xc088, 0x21, 0 - .dw 0xe0c0, 0xc088, 0xe0ff, 0xc088, 0x21, 0 - .dw 0xe140, 0xc088, 0xe17f, 0xc088, 0x21, 0 - .dw 0xe1c0, 0xc088, 0xe1ff, 0xc088, 0x21, 0 - .dw 0xe240, 0xc088, 0xe27f, 0xc088, 0x21, 0 - .dw 0xe2c0, 0xc088, 0xe2ff, 0xc088, 0x21, 0 - .dw 0xe340, 0xc088, 0xe37f, 0xc088, 0x21, 0 - .dw 0xe3c0, 0xc088, 0xe3ff, 0xc088, 0x21, 0 - .dw 0xe440, 0xc088, 0xe47f, 0xc088, 0x21, 0 - .dw 0xe4c0, 0xc088, 0xe4ff, 0xc088, 0x21, 0 - .dw 0xe540, 0xc088, 0xe57f, 0xc088, 0x21, 0 - .dw 0xe5c0, 0xc088, 0xe5ff, 0xc088, 0x21, 0 - .dw 0xe640, 0xc088, 0xe67f, 0xc088, 0x21, 0 - .dw 0xe6c0, 0xc088, 0xe6ff, 0xc088, 0x21, 0 - .dw 0xe740, 0xc088, 0xe77f, 0xc088, 0x21, 0 - .dw 0xe7c0, 0xc088, 0xe7ff, 0xc088, 0x21, 0 - .dw 0xe840, 0xc088, 0xe87f, 0xc088, 0x21, 0 - .dw 0xe8c0, 0xc088, 0xe8ff, 0xc088, 0x21, 0 - .dw 0xe940, 0xc088, 0xe97f, 0xc088, 0x21, 0 - .dw 0xe9c0, 0xc088, 0xe9ff, 0xc088, 0x21, 0 - .dw 0xea40, 0xc088, 0xea7f, 0xc088, 0x21, 0 - .dw 0xeac0, 0xc088, 0xeaff, 0xc088, 0x21, 0 - .dw 0xeb40, 0xc088, 0xeb7f, 0xc088, 0x21, 0 - .dw 0xebc0, 0xc088, 0xebff, 0xc088, 0x21, 0 - .dw 0xec40, 0xc088, 0xec7f, 0xc088, 0x21, 0 - .dw 0xecc0, 0xc088, 0xecff, 0xc088, 0x21, 0 - .dw 0xed40, 0xc088, 0xed7f, 0xc088, 0x21, 0 - .dw 0xedc0, 0xc088, 0xedff, 0xc088, 0x21, 0 - .dw 0xee40, 0xc088, 0xee7f, 0xc088, 0x21, 0 - .dw 0xeec0, 0xc088, 0xeeff, 0xc088, 0x21, 0 - .dw 0xef40, 0xc088, 0xef7f, 0xc088, 0x21, 0 - .dw 0xefc0, 0xc088, 0xefff, 0xc088, 0x21, 0 - .dw 0xf040, 0xc088, 0xf07f, 0xc088, 0x21, 0 - .dw 0xf0c0, 0xc088, 0xf0ff, 0xc088, 0x21, 0 - .dw 0xf140, 0xc088, 0xf17f, 0xc088, 0x21, 0 - .dw 0xf1c0, 0xc088, 0xf1ff, 0xc088, 0x21, 0 - .dw 0xf240, 0xc088, 0xf27f, 0xc088, 0x21, 0 - .dw 0xf2c0, 0xc088, 0xf2ff, 0xc088, 0x21, 0 - .dw 0xf340, 0xc088, 0xf37f, 0xc088, 0x21, 0 - .dw 0xf3c0, 0xc088, 0xf3ff, 0xc088, 0x21, 0 - .dw 0xf440, 0xc088, 0xf47f, 0xc088, 0x21, 0 - .dw 0xf4c0, 0xc088, 0xf4ff, 0xc088, 0x21, 0 - .dw 0xf540, 0xc088, 0xf57f, 0xc088, 0x21, 0 - .dw 0xf5c0, 0xc088, 0xf5ff, 0xc088, 0x21, 0 - .dw 0xf640, 0xc088, 0xf67f, 0xc088, 0x21, 0 - .dw 0xf6c0, 0xc088, 0xf6ff, 0xc088, 0x21, 0 - .dw 0xf740, 0xc088, 0xf77f, 0xc088, 0x21, 0 - .dw 0xf7c0, 0xc088, 0xf7ff, 0xc088, 0x21, 0 - .dw 0xf840, 0xc088, 0xf87f, 0xc088, 0x21, 0 - .dw 0xf8c0, 0xc088, 0xf8ff, 0xc088, 0x21, 0 - .dw 0xf940, 0xc088, 0xf97f, 0xc088, 0x21, 0 - .dw 0xf9c0, 0xc088, 0x1fff, 0xc089, 0x21, 0 - .dw 0x2040, 0xc089, 0x207f, 0xc089, 0x21, 0 - .dw 0x20c0, 0xc089, 0x20ff, 0xc089, 0x21, 0 - .dw 0x2140, 0xc089, 0x217f, 0xc089, 0x21, 0 - .dw 0x21c0, 0xc089, 0x21ff, 0xc089, 0x21, 0 - .dw 0x2240, 0xc089, 0x227f, 0xc089, 0x21, 0 - .dw 0x22c0, 0xc089, 0x22ff, 0xc089, 0x21, 0 - .dw 0x2340, 0xc089, 0x237f, 0xc089, 0x21, 0 - .dw 0x23c0, 0xc089, 0x23ff, 0xc089, 0x21, 0 - .dw 0x2440, 0xc089, 0x247f, 0xc089, 0x21, 0 - .dw 0x24c0, 0xc089, 0x24ff, 0xc089, 0x21, 0 - .dw 0x2540, 0xc089, 0x257f, 0xc089, 0x21, 0 - .dw 0x25c0, 0xc089, 0x25ff, 0xc089, 0x21, 0 - .dw 0x2640, 0xc089, 0x267f, 0xc089, 0x21, 0 - .dw 0x26c0, 0xc089, 0x26ff, 0xc089, 0x21, 0 - .dw 0x2740, 0xc089, 0x277f, 0xc089, 0x21, 0 - .dw 0x27c0, 0xc089, 0x27ff, 0xc089, 0x21, 0 - .dw 0x2840, 0xc089, 0x287f, 0xc089, 0x21, 0 - .dw 0x28c0, 0xc089, 0x28ff, 0xc089, 0x21, 0 - .dw 0x2940, 0xc089, 0x297f, 0xc089, 0x21, 0 - .dw 0x29c0, 0xc089, 0x29ff, 0xc089, 0x21, 0 - .dw 0x2a40, 0xc089, 0x2a7f, 0xc089, 0x21, 0 - .dw 0x2ac0, 0xc089, 0x2aff, 0xc089, 0x21, 0 - .dw 0x2b40, 0xc089, 0x2b7f, 0xc089, 0x21, 0 - .dw 0x2bc0, 0xc089, 0x2bff, 0xc089, 0x21, 0 - .dw 0x2c40, 0xc089, 0x2c7f, 0xc089, 0x21, 0 - .dw 0x2cc0, 0xc089, 0x2cff, 0xc089, 0x21, 0 - .dw 0x2d40, 0xc089, 0x2d7f, 0xc089, 0x21, 0 - .dw 0x2dc0, 0xc089, 0x2dff, 0xc089, 0x21, 0 - .dw 0x2e40, 0xc089, 0x2e7f, 0xc089, 0x21, 0 - .dw 0x2ec0, 0xc089, 0x2eff, 0xc089, 0x21, 0 - .dw 0x2f40, 0xc089, 0x2f7f, 0xc089, 0x21, 0 - .dw 0x2fc0, 0xc089, 0x2fff, 0xc089, 0x21, 0 - .dw 0x3040, 0xc089, 0x307f, 0xc089, 0x21, 0 - .dw 0x30c0, 0xc089, 0x30ff, 0xc089, 0x21, 0 - .dw 0x3140, 0xc089, 0x317f, 0xc089, 0x21, 0 - .dw 0x31c0, 0xc089, 0x31ff, 0xc089, 0x21, 0 - .dw 0x3240, 0xc089, 0x327f, 0xc089, 0x21, 0 - .dw 0x32c0, 0xc089, 0x32ff, 0xc089, 0x21, 0 - .dw 0x3340, 0xc089, 0x337f, 0xc089, 0x21, 0 - .dw 0x33c0, 0xc089, 0x33ff, 0xc089, 0x21, 0 - .dw 0x3440, 0xc089, 0x347f, 0xc089, 0x21, 0 - .dw 0x34c0, 0xc089, 0x34ff, 0xc089, 0x21, 0 - .dw 0x3540, 0xc089, 0x357f, 0xc089, 0x21, 0 - .dw 0x35c0, 0xc089, 0x35ff, 0xc089, 0x21, 0 - .dw 0x3640, 0xc089, 0x367f, 0xc089, 0x21, 0 - .dw 0x36c0, 0xc089, 0x36ff, 0xc089, 0x21, 0 - .dw 0x3740, 0xc089, 0x377f, 0xc089, 0x21, 0 - .dw 0x37c0, 0xc089, 0x37ff, 0xc089, 0x21, 0 - .dw 0x3840, 0xc089, 0x387f, 0xc089, 0x21, 0 - .dw 0x38c0, 0xc089, 0x38ff, 0xc089, 0x21, 0 - .dw 0x3940, 0xc089, 0x397f, 0xc089, 0x21, 0 - .dw 0x39c0, 0xc089, 0x5fff, 0xc089, 0x21, 0 - .dw 0x6040, 0xc089, 0x607f, 0xc089, 0x21, 0 - .dw 0x60c0, 0xc089, 0x60ff, 0xc089, 0x21, 0 - .dw 0x6140, 0xc089, 0x617f, 0xc089, 0x21, 0 - .dw 0x61c0, 0xc089, 0x61ff, 0xc089, 0x21, 0 - .dw 0x6240, 0xc089, 0x627f, 0xc089, 0x21, 0 - .dw 0x62c0, 0xc089, 0x62ff, 0xc089, 0x21, 0 - .dw 0x6340, 0xc089, 0x637f, 0xc089, 0x21, 0 - .dw 0x63c0, 0xc089, 0x63ff, 0xc089, 0x21, 0 - .dw 0x6440, 0xc089, 0x647f, 0xc089, 0x21, 0 - .dw 0x64c0, 0xc089, 0x64ff, 0xc089, 0x21, 0 - .dw 0x6540, 0xc089, 0x657f, 0xc089, 0x21, 0 - .dw 0x65c0, 0xc089, 0x65ff, 0xc089, 0x21, 0 - .dw 0x6640, 0xc089, 0x667f, 0xc089, 0x21, 0 - .dw 0x66c0, 0xc089, 0x66ff, 0xc089, 0x21, 0 - .dw 0x6740, 0xc089, 0x677f, 0xc089, 0x21, 0 - .dw 0x67c0, 0xc089, 0x67ff, 0xc089, 0x21, 0 - .dw 0x6840, 0xc089, 0x687f, 0xc089, 0x21, 0 - .dw 0x68c0, 0xc089, 0x68ff, 0xc089, 0x21, 0 - .dw 0x6940, 0xc089, 0x697f, 0xc089, 0x21, 0 - .dw 0x69c0, 0xc089, 0x69ff, 0xc089, 0x21, 0 - .dw 0x6a40, 0xc089, 0x6a7f, 0xc089, 0x21, 0 - .dw 0x6ac0, 0xc089, 0x6aff, 0xc089, 0x21, 0 - .dw 0x6b40, 0xc089, 0x6b7f, 0xc089, 0x21, 0 - .dw 0x6bc0, 0xc089, 0x6bff, 0xc089, 0x21, 0 - .dw 0x6c40, 0xc089, 0x6c7f, 0xc089, 0x21, 0 - .dw 0x6cc0, 0xc089, 0x6cff, 0xc089, 0x21, 0 - .dw 0x6d40, 0xc089, 0x6d7f, 0xc089, 0x21, 0 - .dw 0x6dc0, 0xc089, 0x6dff, 0xc089, 0x21, 0 - .dw 0x6e40, 0xc089, 0x6e7f, 0xc089, 0x21, 0 - .dw 0x6ec0, 0xc089, 0x6eff, 0xc089, 0x21, 0 - .dw 0x6f40, 0xc089, 0x6f7f, 0xc089, 0x21, 0 - .dw 0x6fc0, 0xc089, 0x6fff, 0xc089, 0x21, 0 - .dw 0x7040, 0xc089, 0x707f, 0xc089, 0x21, 0 - .dw 0x70c0, 0xc089, 0x70ff, 0xc089, 0x21, 0 - .dw 0x7140, 0xc089, 0x717f, 0xc089, 0x21, 0 - .dw 0x71c0, 0xc089, 0x71ff, 0xc089, 0x21, 0 - .dw 0x7240, 0xc089, 0x727f, 0xc089, 0x21, 0 - .dw 0x72c0, 0xc089, 0x72ff, 0xc089, 0x21, 0 - .dw 0x7340, 0xc089, 0x737f, 0xc089, 0x21, 0 - .dw 0x73c0, 0xc089, 0x73ff, 0xc089, 0x21, 0 - .dw 0x7440, 0xc089, 0x747f, 0xc089, 0x21, 0 - .dw 0x74c0, 0xc089, 0x74ff, 0xc089, 0x21, 0 - .dw 0x7540, 0xc089, 0x757f, 0xc089, 0x21, 0 - .dw 0x75c0, 0xc089, 0x75ff, 0xc089, 0x21, 0 - .dw 0x7640, 0xc089, 0x767f, 0xc089, 0x21, 0 - .dw 0x76c0, 0xc089, 0x76ff, 0xc089, 0x21, 0 - .dw 0x7740, 0xc089, 0x777f, 0xc089, 0x21, 0 - .dw 0x77c0, 0xc089, 0x77ff, 0xc089, 0x21, 0 - .dw 0x7840, 0xc089, 0x787f, 0xc089, 0x21, 0 - .dw 0x78c0, 0xc089, 0x78ff, 0xc089, 0x21, 0 - .dw 0x7940, 0xc089, 0x797f, 0xc089, 0x21, 0 - .dw 0x79c0, 0xc089, 0x9fff, 0xc089, 0x21, 0 - .dw 0xa040, 0xc089, 0xa07f, 0xc089, 0x21, 0 - .dw 0xa0c0, 0xc089, 0xa0ff, 0xc089, 0x21, 0 - .dw 0xa140, 0xc089, 0xa17f, 0xc089, 0x21, 0 - .dw 0xa1c0, 0xc089, 0xa1ff, 0xc089, 0x21, 0 - .dw 0xa240, 0xc089, 0xa27f, 0xc089, 0x21, 0 - .dw 0xa2c0, 0xc089, 0xa2ff, 0xc089, 0x21, 0 - .dw 0xa340, 0xc089, 0xa37f, 0xc089, 0x21, 0 - .dw 0xa3c0, 0xc089, 0xa3ff, 0xc089, 0x21, 0 - .dw 0xa440, 0xc089, 0xa47f, 0xc089, 0x21, 0 - .dw 0xa4c0, 0xc089, 0xa4ff, 0xc089, 0x21, 0 - .dw 0xa540, 0xc089, 0xa57f, 0xc089, 0x21, 0 - .dw 0xa5c0, 0xc089, 0xa5ff, 0xc089, 0x21, 0 - .dw 0xa640, 0xc089, 0xa67f, 0xc089, 0x21, 0 - .dw 0xa6c0, 0xc089, 0xa6ff, 0xc089, 0x21, 0 - .dw 0xa740, 0xc089, 0xa77f, 0xc089, 0x21, 0 - .dw 0xa7c0, 0xc089, 0xa7ff, 0xc089, 0x21, 0 - .dw 0xa840, 0xc089, 0xa87f, 0xc089, 0x21, 0 - .dw 0xa8c0, 0xc089, 0xa8ff, 0xc089, 0x21, 0 - .dw 0xa940, 0xc089, 0xa97f, 0xc089, 0x21, 0 - .dw 0xa9c0, 0xc089, 0xa9ff, 0xc089, 0x21, 0 - .dw 0xaa40, 0xc089, 0xaa7f, 0xc089, 0x21, 0 - .dw 0xaac0, 0xc089, 0xaaff, 0xc089, 0x21, 0 - .dw 0xab40, 0xc089, 0xab7f, 0xc089, 0x21, 0 - .dw 0xabc0, 0xc089, 0xabff, 0xc089, 0x21, 0 - .dw 0xac40, 0xc089, 0xac7f, 0xc089, 0x21, 0 - .dw 0xacc0, 0xc089, 0xacff, 0xc089, 0x21, 0 - .dw 0xad40, 0xc089, 0xad7f, 0xc089, 0x21, 0 - .dw 0xadc0, 0xc089, 0xadff, 0xc089, 0x21, 0 - .dw 0xae40, 0xc089, 0xae7f, 0xc089, 0x21, 0 - .dw 0xaec0, 0xc089, 0xaeff, 0xc089, 0x21, 0 - .dw 0xaf40, 0xc089, 0xaf7f, 0xc089, 0x21, 0 - .dw 0xafc0, 0xc089, 0xafff, 0xc089, 0x21, 0 - .dw 0xb040, 0xc089, 0xb07f, 0xc089, 0x21, 0 - .dw 0xb0c0, 0xc089, 0xb0ff, 0xc089, 0x21, 0 - .dw 0xb140, 0xc089, 0xb17f, 0xc089, 0x21, 0 - .dw 0xb1c0, 0xc089, 0xb1ff, 0xc089, 0x21, 0 - .dw 0xb240, 0xc089, 0xb27f, 0xc089, 0x21, 0 - .dw 0xb2c0, 0xc089, 0xb2ff, 0xc089, 0x21, 0 - .dw 0xb340, 0xc089, 0xb37f, 0xc089, 0x21, 0 - .dw 0xb3c0, 0xc089, 0xb3ff, 0xc089, 0x21, 0 - .dw 0xb440, 0xc089, 0xb47f, 0xc089, 0x21, 0 - .dw 0xb4c0, 0xc089, 0xb4ff, 0xc089, 0x21, 0 - .dw 0xb540, 0xc089, 0xb57f, 0xc089, 0x21, 0 - .dw 0xb5c0, 0xc089, 0xb5ff, 0xc089, 0x21, 0 - .dw 0xb640, 0xc089, 0xb67f, 0xc089, 0x21, 0 - .dw 0xb6c0, 0xc089, 0xb6ff, 0xc089, 0x21, 0 - .dw 0xb740, 0xc089, 0xb77f, 0xc089, 0x21, 0 - .dw 0xb7c0, 0xc089, 0xb7ff, 0xc089, 0x21, 0 - .dw 0xb840, 0xc089, 0xb87f, 0xc089, 0x21, 0 - .dw 0xb8c0, 0xc089, 0xb8ff, 0xc089, 0x21, 0 - .dw 0xb940, 0xc089, 0xb97f, 0xc089, 0x21, 0 - .dw 0xb9c0, 0xc089, 0xdfff, 0xc089, 0x21, 0 - .dw 0xe040, 0xc089, 0xe07f, 0xc089, 0x21, 0 - .dw 0xe0c0, 0xc089, 0xe0ff, 0xc089, 0x21, 0 - .dw 0xe140, 0xc089, 0xe17f, 0xc089, 0x21, 0 - .dw 0xe1c0, 0xc089, 0xe1ff, 0xc089, 0x21, 0 - .dw 0xe240, 0xc089, 0xe27f, 0xc089, 0x21, 0 - .dw 0xe2c0, 0xc089, 0xe2ff, 0xc089, 0x21, 0 - .dw 0xe340, 0xc089, 0xe37f, 0xc089, 0x21, 0 - .dw 0xe3c0, 0xc089, 0xe3ff, 0xc089, 0x21, 0 - .dw 0xe440, 0xc089, 0xe47f, 0xc089, 0x21, 0 - .dw 0xe4c0, 0xc089, 0xe4ff, 0xc089, 0x21, 0 - .dw 0xe540, 0xc089, 0xe57f, 0xc089, 0x21, 0 - .dw 0xe5c0, 0xc089, 0xe5ff, 0xc089, 0x21, 0 - .dw 0xe640, 0xc089, 0xe67f, 0xc089, 0x21, 0 - .dw 0xe6c0, 0xc089, 0xe6ff, 0xc089, 0x21, 0 - .dw 0xe740, 0xc089, 0xe77f, 0xc089, 0x21, 0 - .dw 0xe7c0, 0xc089, 0xe7ff, 0xc089, 0x21, 0 - .dw 0xe840, 0xc089, 0xe87f, 0xc089, 0x21, 0 - .dw 0xe8c0, 0xc089, 0xe8ff, 0xc089, 0x21, 0 - .dw 0xe940, 0xc089, 0xe97f, 0xc089, 0x21, 0 - .dw 0xe9c0, 0xc089, 0xe9ff, 0xc089, 0x21, 0 - .dw 0xea40, 0xc089, 0xea7f, 0xc089, 0x21, 0 - .dw 0xeac0, 0xc089, 0xeaff, 0xc089, 0x21, 0 - .dw 0xeb40, 0xc089, 0xeb7f, 0xc089, 0x21, 0 - .dw 0xebc0, 0xc089, 0xebff, 0xc089, 0x21, 0 - .dw 0xec40, 0xc089, 0xec7f, 0xc089, 0x21, 0 - .dw 0xecc0, 0xc089, 0xecff, 0xc089, 0x21, 0 - .dw 0xed40, 0xc089, 0xed7f, 0xc089, 0x21, 0 - .dw 0xedc0, 0xc089, 0xedff, 0xc089, 0x21, 0 - .dw 0xee40, 0xc089, 0xee7f, 0xc089, 0x21, 0 - .dw 0xeec0, 0xc089, 0xeeff, 0xc089, 0x21, 0 - .dw 0xef40, 0xc089, 0xef7f, 0xc089, 0x21, 0 - .dw 0xefc0, 0xc089, 0xefff, 0xc089, 0x21, 0 - .dw 0xf040, 0xc089, 0xf07f, 0xc089, 0x21, 0 - .dw 0xf0c0, 0xc089, 0xf0ff, 0xc089, 0x21, 0 - .dw 0xf140, 0xc089, 0xf17f, 0xc089, 0x21, 0 - .dw 0xf1c0, 0xc089, 0xf1ff, 0xc089, 0x21, 0 - .dw 0xf240, 0xc089, 0xf27f, 0xc089, 0x21, 0 - .dw 0xf2c0, 0xc089, 0xf2ff, 0xc089, 0x21, 0 - .dw 0xf340, 0xc089, 0xf37f, 0xc089, 0x21, 0 - .dw 0xf3c0, 0xc089, 0xf3ff, 0xc089, 0x21, 0 - .dw 0xf440, 0xc089, 0xf47f, 0xc089, 0x21, 0 - .dw 0xf4c0, 0xc089, 0xf4ff, 0xc089, 0x21, 0 - .dw 0xf540, 0xc089, 0xf57f, 0xc089, 0x21, 0 - .dw 0xf5c0, 0xc089, 0xf5ff, 0xc089, 0x21, 0 - .dw 0xf640, 0xc089, 0xf67f, 0xc089, 0x21, 0 - .dw 0xf6c0, 0xc089, 0xf6ff, 0xc089, 0x21, 0 - .dw 0xf740, 0xc089, 0xf77f, 0xc089, 0x21, 0 - .dw 0xf7c0, 0xc089, 0xf7ff, 0xc089, 0x21, 0 - .dw 0xf840, 0xc089, 0xf87f, 0xc089, 0x21, 0 - .dw 0xf8c0, 0xc089, 0xf8ff, 0xc089, 0x21, 0 - .dw 0xf940, 0xc089, 0xf97f, 0xc089, 0x21, 0 - .dw 0xf9c0, 0xc089, 0x1fff, 0xc08a, 0x21, 0 - .dw 0x2040, 0xc08a, 0x207f, 0xc08a, 0x21, 0 - .dw 0x20c0, 0xc08a, 0x20ff, 0xc08a, 0x21, 0 - .dw 0x2140, 0xc08a, 0x217f, 0xc08a, 0x21, 0 - .dw 0x21c0, 0xc08a, 0x21ff, 0xc08a, 0x21, 0 - .dw 0x2240, 0xc08a, 0x227f, 0xc08a, 0x21, 0 - .dw 0x22c0, 0xc08a, 0x22ff, 0xc08a, 0x21, 0 - .dw 0x2340, 0xc08a, 0x237f, 0xc08a, 0x21, 0 - .dw 0x23c0, 0xc08a, 0x23ff, 0xc08a, 0x21, 0 - .dw 0x2440, 0xc08a, 0x247f, 0xc08a, 0x21, 0 - .dw 0x24c0, 0xc08a, 0x24ff, 0xc08a, 0x21, 0 - .dw 0x2540, 0xc08a, 0x257f, 0xc08a, 0x21, 0 - .dw 0x25c0, 0xc08a, 0x25ff, 0xc08a, 0x21, 0 - .dw 0x2640, 0xc08a, 0x267f, 0xc08a, 0x21, 0 - .dw 0x26c0, 0xc08a, 0x26ff, 0xc08a, 0x21, 0 - .dw 0x2740, 0xc08a, 0x277f, 0xc08a, 0x21, 0 - .dw 0x27c0, 0xc08a, 0x27ff, 0xc08a, 0x21, 0 - .dw 0x2840, 0xc08a, 0x287f, 0xc08a, 0x21, 0 - .dw 0x28c0, 0xc08a, 0x28ff, 0xc08a, 0x21, 0 - .dw 0x2940, 0xc08a, 0x297f, 0xc08a, 0x21, 0 - .dw 0x29c0, 0xc08a, 0x29ff, 0xc08a, 0x21, 0 - .dw 0x2a40, 0xc08a, 0x2a7f, 0xc08a, 0x21, 0 - .dw 0x2ac0, 0xc08a, 0x2aff, 0xc08a, 0x21, 0 - .dw 0x2b40, 0xc08a, 0x2b7f, 0xc08a, 0x21, 0 - .dw 0x2bc0, 0xc08a, 0x2bff, 0xc08a, 0x21, 0 - .dw 0x2c40, 0xc08a, 0x2c7f, 0xc08a, 0x21, 0 - .dw 0x2cc0, 0xc08a, 0x2cff, 0xc08a, 0x21, 0 - .dw 0x2d40, 0xc08a, 0x2d7f, 0xc08a, 0x21, 0 - .dw 0x2dc0, 0xc08a, 0x2dff, 0xc08a, 0x21, 0 - .dw 0x2e40, 0xc08a, 0x2e7f, 0xc08a, 0x21, 0 - .dw 0x2ec0, 0xc08a, 0x2eff, 0xc08a, 0x21, 0 - .dw 0x2f40, 0xc08a, 0x2f7f, 0xc08a, 0x21, 0 - .dw 0x2fc0, 0xc08a, 0x2fff, 0xc08a, 0x21, 0 - .dw 0x3040, 0xc08a, 0x307f, 0xc08a, 0x21, 0 - .dw 0x30c0, 0xc08a, 0x30ff, 0xc08a, 0x21, 0 - .dw 0x3140, 0xc08a, 0x317f, 0xc08a, 0x21, 0 - .dw 0x31c0, 0xc08a, 0x31ff, 0xc08a, 0x21, 0 - .dw 0x3240, 0xc08a, 0x327f, 0xc08a, 0x21, 0 - .dw 0x32c0, 0xc08a, 0x32ff, 0xc08a, 0x21, 0 - .dw 0x3340, 0xc08a, 0x337f, 0xc08a, 0x21, 0 - .dw 0x33c0, 0xc08a, 0x33ff, 0xc08a, 0x21, 0 - .dw 0x3440, 0xc08a, 0x347f, 0xc08a, 0x21, 0 - .dw 0x34c0, 0xc08a, 0x34ff, 0xc08a, 0x21, 0 - .dw 0x3540, 0xc08a, 0x357f, 0xc08a, 0x21, 0 - .dw 0x35c0, 0xc08a, 0x35ff, 0xc08a, 0x21, 0 - .dw 0x3640, 0xc08a, 0x367f, 0xc08a, 0x21, 0 - .dw 0x36c0, 0xc08a, 0x36ff, 0xc08a, 0x21, 0 - .dw 0x3740, 0xc08a, 0x377f, 0xc08a, 0x21, 0 - .dw 0x37c0, 0xc08a, 0x37ff, 0xc08a, 0x21, 0 - .dw 0x3840, 0xc08a, 0x387f, 0xc08a, 0x21, 0 - .dw 0x38c0, 0xc08a, 0x38ff, 0xc08a, 0x21, 0 - .dw 0x3940, 0xc08a, 0x397f, 0xc08a, 0x21, 0 - .dw 0x39c0, 0xc08a, 0x5fff, 0xc08a, 0x21, 0 - .dw 0x6040, 0xc08a, 0x607f, 0xc08a, 0x21, 0 - .dw 0x60c0, 0xc08a, 0x60ff, 0xc08a, 0x21, 0 - .dw 0x6140, 0xc08a, 0x617f, 0xc08a, 0x21, 0 - .dw 0x61c0, 0xc08a, 0x61ff, 0xc08a, 0x21, 0 - .dw 0x6240, 0xc08a, 0x627f, 0xc08a, 0x21, 0 - .dw 0x62c0, 0xc08a, 0x62ff, 0xc08a, 0x21, 0 - .dw 0x6340, 0xc08a, 0x637f, 0xc08a, 0x21, 0 - .dw 0x63c0, 0xc08a, 0x63ff, 0xc08a, 0x21, 0 - .dw 0x6440, 0xc08a, 0x647f, 0xc08a, 0x21, 0 - .dw 0x64c0, 0xc08a, 0x64ff, 0xc08a, 0x21, 0 - .dw 0x6540, 0xc08a, 0x657f, 0xc08a, 0x21, 0 - .dw 0x65c0, 0xc08a, 0x65ff, 0xc08a, 0x21, 0 - .dw 0x6640, 0xc08a, 0x667f, 0xc08a, 0x21, 0 - .dw 0x66c0, 0xc08a, 0x66ff, 0xc08a, 0x21, 0 - .dw 0x6740, 0xc08a, 0x677f, 0xc08a, 0x21, 0 - .dw 0x67c0, 0xc08a, 0x67ff, 0xc08a, 0x21, 0 - .dw 0x6840, 0xc08a, 0x687f, 0xc08a, 0x21, 0 - .dw 0x68c0, 0xc08a, 0x68ff, 0xc08a, 0x21, 0 - .dw 0x6940, 0xc08a, 0x697f, 0xc08a, 0x21, 0 - .dw 0x69c0, 0xc08a, 0x69ff, 0xc08a, 0x21, 0 - .dw 0x6a40, 0xc08a, 0x6a7f, 0xc08a, 0x21, 0 - .dw 0x6ac0, 0xc08a, 0x6aff, 0xc08a, 0x21, 0 - .dw 0x6b40, 0xc08a, 0x6b7f, 0xc08a, 0x21, 0 - .dw 0x6bc0, 0xc08a, 0x6bff, 0xc08a, 0x21, 0 - .dw 0x6c40, 0xc08a, 0x6c7f, 0xc08a, 0x21, 0 - .dw 0x6cc0, 0xc08a, 0x6cff, 0xc08a, 0x21, 0 - .dw 0x6d40, 0xc08a, 0x6d7f, 0xc08a, 0x21, 0 - .dw 0x6dc0, 0xc08a, 0x6dff, 0xc08a, 0x21, 0 - .dw 0x6e40, 0xc08a, 0x6e7f, 0xc08a, 0x21, 0 - .dw 0x6ec0, 0xc08a, 0x6eff, 0xc08a, 0x21, 0 - .dw 0x6f40, 0xc08a, 0x6f7f, 0xc08a, 0x21, 0 - .dw 0x6fc0, 0xc08a, 0x6fff, 0xc08a, 0x21, 0 - .dw 0x7040, 0xc08a, 0x707f, 0xc08a, 0x21, 0 - .dw 0x70c0, 0xc08a, 0x70ff, 0xc08a, 0x21, 0 - .dw 0x7140, 0xc08a, 0x717f, 0xc08a, 0x21, 0 - .dw 0x71c0, 0xc08a, 0x71ff, 0xc08a, 0x21, 0 - .dw 0x7240, 0xc08a, 0x727f, 0xc08a, 0x21, 0 - .dw 0x72c0, 0xc08a, 0x72ff, 0xc08a, 0x21, 0 - .dw 0x7340, 0xc08a, 0x737f, 0xc08a, 0x21, 0 - .dw 0x73c0, 0xc08a, 0x73ff, 0xc08a, 0x21, 0 - .dw 0x7440, 0xc08a, 0x747f, 0xc08a, 0x21, 0 - .dw 0x74c0, 0xc08a, 0x74ff, 0xc08a, 0x21, 0 - .dw 0x7540, 0xc08a, 0x757f, 0xc08a, 0x21, 0 - .dw 0x75c0, 0xc08a, 0x75ff, 0xc08a, 0x21, 0 - .dw 0x7640, 0xc08a, 0x767f, 0xc08a, 0x21, 0 - .dw 0x76c0, 0xc08a, 0x76ff, 0xc08a, 0x21, 0 - .dw 0x7740, 0xc08a, 0x777f, 0xc08a, 0x21, 0 - .dw 0x77c0, 0xc08a, 0x77ff, 0xc08a, 0x21, 0 - .dw 0x7840, 0xc08a, 0x787f, 0xc08a, 0x21, 0 - .dw 0x78c0, 0xc08a, 0x78ff, 0xc08a, 0x21, 0 - .dw 0x7940, 0xc08a, 0x797f, 0xc08a, 0x21, 0 - .dw 0x79c0, 0xc08a, 0x9fff, 0xc08a, 0x21, 0 - .dw 0xa040, 0xc08a, 0xa07f, 0xc08a, 0x21, 0 - .dw 0xa0c0, 0xc08a, 0xa0ff, 0xc08a, 0x21, 0 - .dw 0xa140, 0xc08a, 0xa17f, 0xc08a, 0x21, 0 - .dw 0xa1c0, 0xc08a, 0xa1ff, 0xc08a, 0x21, 0 - .dw 0xa240, 0xc08a, 0xa27f, 0xc08a, 0x21, 0 - .dw 0xa2c0, 0xc08a, 0xa2ff, 0xc08a, 0x21, 0 - .dw 0xa340, 0xc08a, 0xa37f, 0xc08a, 0x21, 0 - .dw 0xa3c0, 0xc08a, 0xa3ff, 0xc08a, 0x21, 0 - .dw 0xa440, 0xc08a, 0xa47f, 0xc08a, 0x21, 0 - .dw 0xa4c0, 0xc08a, 0xa4ff, 0xc08a, 0x21, 0 - .dw 0xa540, 0xc08a, 0xa57f, 0xc08a, 0x21, 0 - .dw 0xa5c0, 0xc08a, 0xa5ff, 0xc08a, 0x21, 0 - .dw 0xa640, 0xc08a, 0xa67f, 0xc08a, 0x21, 0 - .dw 0xa6c0, 0xc08a, 0xa6ff, 0xc08a, 0x21, 0 - .dw 0xa740, 0xc08a, 0xa77f, 0xc08a, 0x21, 0 - .dw 0xa7c0, 0xc08a, 0xa7ff, 0xc08a, 0x21, 0 - .dw 0xa840, 0xc08a, 0xa87f, 0xc08a, 0x21, 0 - .dw 0xa8c0, 0xc08a, 0xa8ff, 0xc08a, 0x21, 0 - .dw 0xa940, 0xc08a, 0xa97f, 0xc08a, 0x21, 0 - .dw 0xa9c0, 0xc08a, 0xa9ff, 0xc08a, 0x21, 0 - .dw 0xaa40, 0xc08a, 0xaa7f, 0xc08a, 0x21, 0 - .dw 0xaac0, 0xc08a, 0xaaff, 0xc08a, 0x21, 0 - .dw 0xab40, 0xc08a, 0xab7f, 0xc08a, 0x21, 0 - .dw 0xabc0, 0xc08a, 0xabff, 0xc08a, 0x21, 0 - .dw 0xac40, 0xc08a, 0xac7f, 0xc08a, 0x21, 0 - .dw 0xacc0, 0xc08a, 0xacff, 0xc08a, 0x21, 0 - .dw 0xad40, 0xc08a, 0xad7f, 0xc08a, 0x21, 0 - .dw 0xadc0, 0xc08a, 0xadff, 0xc08a, 0x21, 0 - .dw 0xae40, 0xc08a, 0xae7f, 0xc08a, 0x21, 0 - .dw 0xaec0, 0xc08a, 0xaeff, 0xc08a, 0x21, 0 - .dw 0xaf40, 0xc08a, 0xaf7f, 0xc08a, 0x21, 0 - .dw 0xafc0, 0xc08a, 0xafff, 0xc08a, 0x21, 0 - .dw 0xb040, 0xc08a, 0xb07f, 0xc08a, 0x21, 0 - .dw 0xb0c0, 0xc08a, 0xb0ff, 0xc08a, 0x21, 0 - .dw 0xb140, 0xc08a, 0xb17f, 0xc08a, 0x21, 0 - .dw 0xb1c0, 0xc08a, 0xb1ff, 0xc08a, 0x21, 0 - .dw 0xb240, 0xc08a, 0xb27f, 0xc08a, 0x21, 0 - .dw 0xb2c0, 0xc08a, 0xb2ff, 0xc08a, 0x21, 0 - .dw 0xb340, 0xc08a, 0xb37f, 0xc08a, 0x21, 0 - .dw 0xb3c0, 0xc08a, 0xb3ff, 0xc08a, 0x21, 0 - .dw 0xb440, 0xc08a, 0xb47f, 0xc08a, 0x21, 0 - .dw 0xb4c0, 0xc08a, 0xb4ff, 0xc08a, 0x21, 0 - .dw 0xb540, 0xc08a, 0xb57f, 0xc08a, 0x21, 0 - .dw 0xb5c0, 0xc08a, 0xb5ff, 0xc08a, 0x21, 0 - .dw 0xb640, 0xc08a, 0xb67f, 0xc08a, 0x21, 0 - .dw 0xb6c0, 0xc08a, 0xb6ff, 0xc08a, 0x21, 0 - .dw 0xb740, 0xc08a, 0xb77f, 0xc08a, 0x21, 0 - .dw 0xb7c0, 0xc08a, 0xb7ff, 0xc08a, 0x21, 0 - .dw 0xb840, 0xc08a, 0xb87f, 0xc08a, 0x21, 0 - .dw 0xb8c0, 0xc08a, 0xb8ff, 0xc08a, 0x21, 0 - .dw 0xb940, 0xc08a, 0xb97f, 0xc08a, 0x21, 0 - .dw 0xb9c0, 0xc08a, 0xdfff, 0xc08a, 0x21, 0 - .dw 0xe040, 0xc08a, 0xe07f, 0xc08a, 0x21, 0 - .dw 0xe0c0, 0xc08a, 0xe0ff, 0xc08a, 0x21, 0 - .dw 0xe140, 0xc08a, 0xe17f, 0xc08a, 0x21, 0 - .dw 0xe1c0, 0xc08a, 0xe1ff, 0xc08a, 0x21, 0 - .dw 0xe240, 0xc08a, 0xe27f, 0xc08a, 0x21, 0 - .dw 0xe2c0, 0xc08a, 0xe2ff, 0xc08a, 0x21, 0 - .dw 0xe340, 0xc08a, 0xe37f, 0xc08a, 0x21, 0 - .dw 0xe3c0, 0xc08a, 0xe3ff, 0xc08a, 0x21, 0 - .dw 0xe440, 0xc08a, 0xe47f, 0xc08a, 0x21, 0 - .dw 0xe4c0, 0xc08a, 0xe4ff, 0xc08a, 0x21, 0 - .dw 0xe540, 0xc08a, 0xe57f, 0xc08a, 0x21, 0 - .dw 0xe5c0, 0xc08a, 0xe5ff, 0xc08a, 0x21, 0 - .dw 0xe640, 0xc08a, 0xe67f, 0xc08a, 0x21, 0 - .dw 0xe6c0, 0xc08a, 0xe6ff, 0xc08a, 0x21, 0 - .dw 0xe740, 0xc08a, 0xe77f, 0xc08a, 0x21, 0 - .dw 0xe7c0, 0xc08a, 0xe7ff, 0xc08a, 0x21, 0 - .dw 0xe840, 0xc08a, 0xe87f, 0xc08a, 0x21, 0 - .dw 0xe8c0, 0xc08a, 0xe8ff, 0xc08a, 0x21, 0 - .dw 0xe940, 0xc08a, 0xe97f, 0xc08a, 0x21, 0 - .dw 0xe9c0, 0xc08a, 0xe9ff, 0xc08a, 0x21, 0 - .dw 0xea40, 0xc08a, 0xea7f, 0xc08a, 0x21, 0 - .dw 0xeac0, 0xc08a, 0xeaff, 0xc08a, 0x21, 0 - .dw 0xeb40, 0xc08a, 0xeb7f, 0xc08a, 0x21, 0 - .dw 0xebc0, 0xc08a, 0xebff, 0xc08a, 0x21, 0 - .dw 0xec40, 0xc08a, 0xec7f, 0xc08a, 0x21, 0 - .dw 0xecc0, 0xc08a, 0xecff, 0xc08a, 0x21, 0 - .dw 0xed40, 0xc08a, 0xed7f, 0xc08a, 0x21, 0 - .dw 0xedc0, 0xc08a, 0xedff, 0xc08a, 0x21, 0 - .dw 0xee40, 0xc08a, 0xee7f, 0xc08a, 0x21, 0 - .dw 0xeec0, 0xc08a, 0xeeff, 0xc08a, 0x21, 0 - .dw 0xef40, 0xc08a, 0xef7f, 0xc08a, 0x21, 0 - .dw 0xefc0, 0xc08a, 0xefff, 0xc08a, 0x21, 0 - .dw 0xf040, 0xc08a, 0xf07f, 0xc08a, 0x21, 0 - .dw 0xf0c0, 0xc08a, 0xf0ff, 0xc08a, 0x21, 0 - .dw 0xf140, 0xc08a, 0xf17f, 0xc08a, 0x21, 0 - .dw 0xf1c0, 0xc08a, 0xf1ff, 0xc08a, 0x21, 0 - .dw 0xf240, 0xc08a, 0xf27f, 0xc08a, 0x21, 0 - .dw 0xf2c0, 0xc08a, 0xf2ff, 0xc08a, 0x21, 0 - .dw 0xf340, 0xc08a, 0xf37f, 0xc08a, 0x21, 0 - .dw 0xf3c0, 0xc08a, 0xf3ff, 0xc08a, 0x21, 0 - .dw 0xf440, 0xc08a, 0xf47f, 0xc08a, 0x21, 0 - .dw 0xf4c0, 0xc08a, 0xf4ff, 0xc08a, 0x21, 0 - .dw 0xf540, 0xc08a, 0xf57f, 0xc08a, 0x21, 0 - .dw 0xf5c0, 0xc08a, 0xf5ff, 0xc08a, 0x21, 0 - .dw 0xf640, 0xc08a, 0xf67f, 0xc08a, 0x21, 0 - .dw 0xf6c0, 0xc08a, 0xf6ff, 0xc08a, 0x21, 0 - .dw 0xf740, 0xc08a, 0xf77f, 0xc08a, 0x21, 0 - .dw 0xf7c0, 0xc08a, 0xf7ff, 0xc08a, 0x21, 0 - .dw 0xf840, 0xc08a, 0xf87f, 0xc08a, 0x21, 0 - .dw 0xf8c0, 0xc08a, 0xf8ff, 0xc08a, 0x21, 0 - .dw 0xf940, 0xc08a, 0xf97f, 0xc08a, 0x21, 0 - .dw 0xf9c0, 0xc08a, 0x1fff, 0xc08b, 0x21, 0 - .dw 0x2040, 0xc08b, 0x207f, 0xc08b, 0x21, 0 - .dw 0x20c0, 0xc08b, 0x20ff, 0xc08b, 0x21, 0 - .dw 0x2140, 0xc08b, 0x217f, 0xc08b, 0x21, 0 - .dw 0x21c0, 0xc08b, 0x21ff, 0xc08b, 0x21, 0 - .dw 0x2240, 0xc08b, 0x227f, 0xc08b, 0x21, 0 - .dw 0x22c0, 0xc08b, 0x22ff, 0xc08b, 0x21, 0 - .dw 0x2340, 0xc08b, 0x237f, 0xc08b, 0x21, 0 - .dw 0x23c0, 0xc08b, 0x23ff, 0xc08b, 0x21, 0 - .dw 0x2440, 0xc08b, 0x247f, 0xc08b, 0x21, 0 - .dw 0x24c0, 0xc08b, 0x24ff, 0xc08b, 0x21, 0 - .dw 0x2540, 0xc08b, 0x257f, 0xc08b, 0x21, 0 - .dw 0x25c0, 0xc08b, 0x25ff, 0xc08b, 0x21, 0 - .dw 0x2640, 0xc08b, 0x267f, 0xc08b, 0x21, 0 - .dw 0x26c0, 0xc08b, 0x26ff, 0xc08b, 0x21, 0 - .dw 0x2740, 0xc08b, 0x277f, 0xc08b, 0x21, 0 - .dw 0x27c0, 0xc08b, 0x27ff, 0xc08b, 0x21, 0 - .dw 0x2840, 0xc08b, 0x287f, 0xc08b, 0x21, 0 - .dw 0x28c0, 0xc08b, 0x28ff, 0xc08b, 0x21, 0 - .dw 0x2940, 0xc08b, 0x297f, 0xc08b, 0x21, 0 - .dw 0x29c0, 0xc08b, 0x29ff, 0xc08b, 0x21, 0 - .dw 0x2a40, 0xc08b, 0x2a7f, 0xc08b, 0x21, 0 - .dw 0x2ac0, 0xc08b, 0x2aff, 0xc08b, 0x21, 0 - .dw 0x2b40, 0xc08b, 0x2b7f, 0xc08b, 0x21, 0 - .dw 0x2bc0, 0xc08b, 0x2bff, 0xc08b, 0x21, 0 - .dw 0x2c40, 0xc08b, 0x2c7f, 0xc08b, 0x21, 0 - .dw 0x2cc0, 0xc08b, 0x2cff, 0xc08b, 0x21, 0 - .dw 0x2d40, 0xc08b, 0x2d7f, 0xc08b, 0x21, 0 - .dw 0x2dc0, 0xc08b, 0x2dff, 0xc08b, 0x21, 0 - .dw 0x2e40, 0xc08b, 0x2e7f, 0xc08b, 0x21, 0 - .dw 0x2ec0, 0xc08b, 0x2eff, 0xc08b, 0x21, 0 - .dw 0x2f40, 0xc08b, 0x2f7f, 0xc08b, 0x21, 0 - .dw 0x2fc0, 0xc08b, 0x2fff, 0xc08b, 0x21, 0 - .dw 0x3040, 0xc08b, 0x307f, 0xc08b, 0x21, 0 - .dw 0x30c0, 0xc08b, 0x30ff, 0xc08b, 0x21, 0 - .dw 0x3140, 0xc08b, 0x317f, 0xc08b, 0x21, 0 - .dw 0x31c0, 0xc08b, 0x31ff, 0xc08b, 0x21, 0 - .dw 0x3240, 0xc08b, 0x327f, 0xc08b, 0x21, 0 - .dw 0x32c0, 0xc08b, 0x32ff, 0xc08b, 0x21, 0 - .dw 0x3340, 0xc08b, 0x337f, 0xc08b, 0x21, 0 - .dw 0x33c0, 0xc08b, 0x33ff, 0xc08b, 0x21, 0 - .dw 0x3440, 0xc08b, 0x347f, 0xc08b, 0x21, 0 - .dw 0x34c0, 0xc08b, 0x34ff, 0xc08b, 0x21, 0 - .dw 0x3540, 0xc08b, 0x357f, 0xc08b, 0x21, 0 - .dw 0x35c0, 0xc08b, 0x35ff, 0xc08b, 0x21, 0 - .dw 0x3640, 0xc08b, 0x367f, 0xc08b, 0x21, 0 - .dw 0x36c0, 0xc08b, 0x36ff, 0xc08b, 0x21, 0 - .dw 0x3740, 0xc08b, 0x377f, 0xc08b, 0x21, 0 - .dw 0x37c0, 0xc08b, 0x37ff, 0xc08b, 0x21, 0 - .dw 0x3840, 0xc08b, 0x387f, 0xc08b, 0x21, 0 - .dw 0x38c0, 0xc08b, 0x38ff, 0xc08b, 0x21, 0 - .dw 0x3940, 0xc08b, 0x397f, 0xc08b, 0x21, 0 - .dw 0x39c0, 0xc08b, 0xffff, 0xc08b, 0x21, 0 - .dw 0x0040, 0xc08c, 0x007f, 0xc08c, 0x21, 0 - .dw 0x00c0, 0xc08c, 0x00ff, 0xc08c, 0x21, 0 - .dw 0x0140, 0xc08c, 0x017f, 0xc08c, 0x21, 0 - .dw 0x01c0, 0xc08c, 0x01ff, 0xc08c, 0x21, 0 - .dw 0x0240, 0xc08c, 0x027f, 0xc08c, 0x21, 0 - .dw 0x02c0, 0xc08c, 0x02ff, 0xc08c, 0x21, 0 - .dw 0x0340, 0xc08c, 0x037f, 0xc08c, 0x21, 0 - .dw 0x03c0, 0xc08c, 0x03ff, 0xc08c, 0x21, 0 - .dw 0x0440, 0xc08c, 0x047f, 0xc08c, 0x21, 0 - .dw 0x04c0, 0xc08c, 0x04ff, 0xc08c, 0x21, 0 - .dw 0x0540, 0xc08c, 0x057f, 0xc08c, 0x21, 0 - .dw 0x05c0, 0xc08c, 0x05ff, 0xc08c, 0x21, 0 - .dw 0x0640, 0xc08c, 0x067f, 0xc08c, 0x21, 0 - .dw 0x06c0, 0xc08c, 0x06ff, 0xc08c, 0x21, 0 - .dw 0x0740, 0xc08c, 0x077f, 0xc08c, 0x21, 0 - .dw 0x07c0, 0xc08c, 0x07ff, 0xc08c, 0x21, 0 - .dw 0x0840, 0xc08c, 0x087f, 0xc08c, 0x21, 0 - .dw 0x08c0, 0xc08c, 0x08ff, 0xc08c, 0x21, 0 - .dw 0x0940, 0xc08c, 0x097f, 0xc08c, 0x21, 0 - .dw 0x09c0, 0xc08c, 0x09ff, 0xc08c, 0x21, 0 - .dw 0x0a40, 0xc08c, 0x0a7f, 0xc08c, 0x21, 0 - .dw 0x0ac0, 0xc08c, 0x0aff, 0xc08c, 0x21, 0 - .dw 0x0b40, 0xc08c, 0x0b7f, 0xc08c, 0x21, 0 - .dw 0x0bc0, 0xc08c, 0x0bff, 0xc08c, 0x21, 0 - .dw 0x0c40, 0xc08c, 0x0c7f, 0xc08c, 0x21, 0 - .dw 0x0cc0, 0xc08c, 0x0cff, 0xc08c, 0x21, 0 - .dw 0x0d40, 0xc08c, 0x0d7f, 0xc08c, 0x21, 0 - .dw 0x0dc0, 0xc08c, 0x0dff, 0xc08c, 0x21, 0 - .dw 0x0e40, 0xc08c, 0x0e7f, 0xc08c, 0x21, 0 - .dw 0x0ec0, 0xc08c, 0x0eff, 0xc08c, 0x21, 0 - .dw 0x0f40, 0xc08c, 0x0f7f, 0xc08c, 0x21, 0 - .dw 0x0fc0, 0xc08c, 0x0fff, 0xc08c, 0x21, 0 - .dw 0x1040, 0xc08c, 0x107f, 0xc08c, 0x21, 0 - .dw 0x10c0, 0xc08c, 0x10ff, 0xc08c, 0x21, 0 - .dw 0x1140, 0xc08c, 0x117f, 0xc08c, 0x21, 0 - .dw 0x11c0, 0xc08c, 0x11ff, 0xc08c, 0x21, 0 - .dw 0x1240, 0xc08c, 0x127f, 0xc08c, 0x21, 0 - .dw 0x12c0, 0xc08c, 0x12ff, 0xc08c, 0x21, 0 - .dw 0x1340, 0xc08c, 0x137f, 0xc08c, 0x21, 0 - .dw 0x13c0, 0xc08c, 0x13ff, 0xc08c, 0x21, 0 - .dw 0x1440, 0xc08c, 0x147f, 0xc08c, 0x21, 0 - .dw 0x14c0, 0xc08c, 0x14ff, 0xc08c, 0x21, 0 - .dw 0x1540, 0xc08c, 0x157f, 0xc08c, 0x21, 0 - .dw 0x15c0, 0xc08c, 0x15ff, 0xc08c, 0x21, 0 - .dw 0x1640, 0xc08c, 0x167f, 0xc08c, 0x21, 0 - .dw 0x16c0, 0xc08c, 0x16ff, 0xc08c, 0x21, 0 - .dw 0x1740, 0xc08c, 0x177f, 0xc08c, 0x21, 0 - .dw 0x17c0, 0xc08c, 0x17ff, 0xc08c, 0x21, 0 - .dw 0x1840, 0xc08c, 0x187f, 0xc08c, 0x21, 0 - .dw 0x18c0, 0xc08c, 0x18ff, 0xc08c, 0x21, 0 - .dw 0x1940, 0xc08c, 0x197f, 0xc08c, 0x21, 0 - .dw 0x19c0, 0xc08c, 0x1fff, 0xc08c, 0x21, 0 - .dw 0x2040, 0xc08c, 0x207f, 0xc08c, 0x21, 0 - .dw 0x20c0, 0xc08c, 0x20ff, 0xc08c, 0x21, 0 - .dw 0x2140, 0xc08c, 0x217f, 0xc08c, 0x21, 0 - .dw 0x21c0, 0xc08c, 0x21ff, 0xc08c, 0x21, 0 - .dw 0x2240, 0xc08c, 0x227f, 0xc08c, 0x21, 0 - .dw 0x22c0, 0xc08c, 0x22ff, 0xc08c, 0x21, 0 - .dw 0x2340, 0xc08c, 0x237f, 0xc08c, 0x21, 0 - .dw 0x23c0, 0xc08c, 0x23ff, 0xc08c, 0x21, 0 - .dw 0x2440, 0xc08c, 0x247f, 0xc08c, 0x21, 0 - .dw 0x24c0, 0xc08c, 0x24ff, 0xc08c, 0x21, 0 - .dw 0x2540, 0xc08c, 0x257f, 0xc08c, 0x21, 0 - .dw 0x25c0, 0xc08c, 0x25ff, 0xc08c, 0x21, 0 - .dw 0x2640, 0xc08c, 0x267f, 0xc08c, 0x21, 0 - .dw 0x26c0, 0xc08c, 0x26ff, 0xc08c, 0x21, 0 - .dw 0x2740, 0xc08c, 0x277f, 0xc08c, 0x21, 0 - .dw 0x27c0, 0xc08c, 0x27ff, 0xc08c, 0x21, 0 - .dw 0x2840, 0xc08c, 0x287f, 0xc08c, 0x21, 0 - .dw 0x28c0, 0xc08c, 0x28ff, 0xc08c, 0x21, 0 - .dw 0x2940, 0xc08c, 0x297f, 0xc08c, 0x21, 0 - .dw 0x29c0, 0xc08c, 0x29ff, 0xc08c, 0x21, 0 - .dw 0x2a40, 0xc08c, 0x2a7f, 0xc08c, 0x21, 0 - .dw 0x2ac0, 0xc08c, 0x2aff, 0xc08c, 0x21, 0 - .dw 0x2b40, 0xc08c, 0x2b7f, 0xc08c, 0x21, 0 - .dw 0x2bc0, 0xc08c, 0x2bff, 0xc08c, 0x21, 0 - .dw 0x2c40, 0xc08c, 0x2c7f, 0xc08c, 0x21, 0 - .dw 0x2cc0, 0xc08c, 0x2cff, 0xc08c, 0x21, 0 - .dw 0x2d40, 0xc08c, 0x2d7f, 0xc08c, 0x21, 0 - .dw 0x2dc0, 0xc08c, 0x2dff, 0xc08c, 0x21, 0 - .dw 0x2e40, 0xc08c, 0x2e7f, 0xc08c, 0x21, 0 - .dw 0x2ec0, 0xc08c, 0x2eff, 0xc08c, 0x21, 0 - .dw 0x2f40, 0xc08c, 0x2f7f, 0xc08c, 0x21, 0 - .dw 0x2fc0, 0xc08c, 0x2fff, 0xc08c, 0x21, 0 - .dw 0x3040, 0xc08c, 0x307f, 0xc08c, 0x21, 0 - .dw 0x30c0, 0xc08c, 0x30ff, 0xc08c, 0x21, 0 - .dw 0x3140, 0xc08c, 0x317f, 0xc08c, 0x21, 0 - .dw 0x31c0, 0xc08c, 0x31ff, 0xc08c, 0x21, 0 - .dw 0x3240, 0xc08c, 0x327f, 0xc08c, 0x21, 0 - .dw 0x32c0, 0xc08c, 0x32ff, 0xc08c, 0x21, 0 - .dw 0x3340, 0xc08c, 0x337f, 0xc08c, 0x21, 0 - .dw 0x33c0, 0xc08c, 0x33ff, 0xc08c, 0x21, 0 - .dw 0x3440, 0xc08c, 0x347f, 0xc08c, 0x21, 0 - .dw 0x34c0, 0xc08c, 0x34ff, 0xc08c, 0x21, 0 - .dw 0x3540, 0xc08c, 0x357f, 0xc08c, 0x21, 0 - .dw 0x35c0, 0xc08c, 0x35ff, 0xc08c, 0x21, 0 - .dw 0x3640, 0xc08c, 0x367f, 0xc08c, 0x21, 0 - .dw 0x36c0, 0xc08c, 0x36ff, 0xc08c, 0x21, 0 - .dw 0x3740, 0xc08c, 0x377f, 0xc08c, 0x21, 0 - .dw 0x37c0, 0xc08c, 0x37ff, 0xc08c, 0x21, 0 - .dw 0x3840, 0xc08c, 0x387f, 0xc08c, 0x21, 0 - .dw 0x38c0, 0xc08c, 0x38ff, 0xc08c, 0x21, 0 - .dw 0x3940, 0xc08c, 0x397f, 0xc08c, 0x21, 0 - .dw 0x39c0, 0xc08c, 0x3fff, 0xc08c, 0x21, 0 - .dw 0x4040, 0xc08c, 0x407f, 0xc08c, 0x21, 0 - .dw 0x40c0, 0xc08c, 0x40ff, 0xc08c, 0x21, 0 - .dw 0x4140, 0xc08c, 0x417f, 0xc08c, 0x21, 0 - .dw 0x41c0, 0xc08c, 0x41ff, 0xc08c, 0x21, 0 - .dw 0x4240, 0xc08c, 0x427f, 0xc08c, 0x21, 0 - .dw 0x42c0, 0xc08c, 0x42ff, 0xc08c, 0x21, 0 - .dw 0x4340, 0xc08c, 0x437f, 0xc08c, 0x21, 0 - .dw 0x43c0, 0xc08c, 0x43ff, 0xc08c, 0x21, 0 - .dw 0x4440, 0xc08c, 0x447f, 0xc08c, 0x21, 0 - .dw 0x44c0, 0xc08c, 0x44ff, 0xc08c, 0x21, 0 - .dw 0x4540, 0xc08c, 0x457f, 0xc08c, 0x21, 0 - .dw 0x45c0, 0xc08c, 0x45ff, 0xc08c, 0x21, 0 - .dw 0x4640, 0xc08c, 0x467f, 0xc08c, 0x21, 0 - .dw 0x46c0, 0xc08c, 0x46ff, 0xc08c, 0x21, 0 - .dw 0x4740, 0xc08c, 0x477f, 0xc08c, 0x21, 0 - .dw 0x47c0, 0xc08c, 0x47ff, 0xc08c, 0x21, 0 - .dw 0x4840, 0xc08c, 0x487f, 0xc08c, 0x21, 0 - .dw 0x48c0, 0xc08c, 0x48ff, 0xc08c, 0x21, 0 - .dw 0x4940, 0xc08c, 0x497f, 0xc08c, 0x21, 0 - .dw 0x49c0, 0xc08c, 0x49ff, 0xc08c, 0x21, 0 - .dw 0x4a40, 0xc08c, 0x4a7f, 0xc08c, 0x21, 0 - .dw 0x4ac0, 0xc08c, 0x4aff, 0xc08c, 0x21, 0 - .dw 0x4b40, 0xc08c, 0x4b7f, 0xc08c, 0x21, 0 - .dw 0x4bc0, 0xc08c, 0x4bff, 0xc08c, 0x21, 0 - .dw 0x4c40, 0xc08c, 0x4c7f, 0xc08c, 0x21, 0 - .dw 0x4cc0, 0xc08c, 0x4cff, 0xc08c, 0x21, 0 - .dw 0x4d40, 0xc08c, 0x4d7f, 0xc08c, 0x21, 0 - .dw 0x4dc0, 0xc08c, 0x4dff, 0xc08c, 0x21, 0 - .dw 0x4e40, 0xc08c, 0x4e7f, 0xc08c, 0x21, 0 - .dw 0x4ec0, 0xc08c, 0x4eff, 0xc08c, 0x21, 0 - .dw 0x4f40, 0xc08c, 0x4f7f, 0xc08c, 0x21, 0 - .dw 0x4fc0, 0xc08c, 0x4fff, 0xc08c, 0x21, 0 - .dw 0x5040, 0xc08c, 0x507f, 0xc08c, 0x21, 0 - .dw 0x50c0, 0xc08c, 0x50ff, 0xc08c, 0x21, 0 - .dw 0x5140, 0xc08c, 0x517f, 0xc08c, 0x21, 0 - .dw 0x51c0, 0xc08c, 0x51ff, 0xc08c, 0x21, 0 - .dw 0x5240, 0xc08c, 0x527f, 0xc08c, 0x21, 0 - .dw 0x52c0, 0xc08c, 0x52ff, 0xc08c, 0x21, 0 - .dw 0x5340, 0xc08c, 0x537f, 0xc08c, 0x21, 0 - .dw 0x53c0, 0xc08c, 0x53ff, 0xc08c, 0x21, 0 - .dw 0x5440, 0xc08c, 0x547f, 0xc08c, 0x21, 0 - .dw 0x54c0, 0xc08c, 0x54ff, 0xc08c, 0x21, 0 - .dw 0x5540, 0xc08c, 0x557f, 0xc08c, 0x21, 0 - .dw 0x55c0, 0xc08c, 0x55ff, 0xc08c, 0x21, 0 - .dw 0x5640, 0xc08c, 0x567f, 0xc08c, 0x21, 0 - .dw 0x56c0, 0xc08c, 0x56ff, 0xc08c, 0x21, 0 - .dw 0x5740, 0xc08c, 0x577f, 0xc08c, 0x21, 0 - .dw 0x57c0, 0xc08c, 0x57ff, 0xc08c, 0x21, 0 - .dw 0x5840, 0xc08c, 0x587f, 0xc08c, 0x21, 0 - .dw 0x58c0, 0xc08c, 0x58ff, 0xc08c, 0x21, 0 - .dw 0x5940, 0xc08c, 0x597f, 0xc08c, 0x21, 0 - .dw 0x59c0, 0xc08c, 0x5fff, 0xc08c, 0x21, 0 - .dw 0x6040, 0xc08c, 0x607f, 0xc08c, 0x21, 0 - .dw 0x60c0, 0xc08c, 0x60ff, 0xc08c, 0x21, 0 - .dw 0x6140, 0xc08c, 0x617f, 0xc08c, 0x21, 0 - .dw 0x61c0, 0xc08c, 0x61ff, 0xc08c, 0x21, 0 - .dw 0x6240, 0xc08c, 0x627f, 0xc08c, 0x21, 0 - .dw 0x62c0, 0xc08c, 0x62ff, 0xc08c, 0x21, 0 - .dw 0x6340, 0xc08c, 0x637f, 0xc08c, 0x21, 0 - .dw 0x63c0, 0xc08c, 0x63ff, 0xc08c, 0x21, 0 - .dw 0x6440, 0xc08c, 0x647f, 0xc08c, 0x21, 0 - .dw 0x64c0, 0xc08c, 0x64ff, 0xc08c, 0x21, 0 - .dw 0x6540, 0xc08c, 0x657f, 0xc08c, 0x21, 0 - .dw 0x65c0, 0xc08c, 0x65ff, 0xc08c, 0x21, 0 - .dw 0x6640, 0xc08c, 0x667f, 0xc08c, 0x21, 0 - .dw 0x66c0, 0xc08c, 0x66ff, 0xc08c, 0x21, 0 - .dw 0x6740, 0xc08c, 0x677f, 0xc08c, 0x21, 0 - .dw 0x67c0, 0xc08c, 0x67ff, 0xc08c, 0x21, 0 - .dw 0x6840, 0xc08c, 0x687f, 0xc08c, 0x21, 0 - .dw 0x68c0, 0xc08c, 0x68ff, 0xc08c, 0x21, 0 - .dw 0x6940, 0xc08c, 0x697f, 0xc08c, 0x21, 0 - .dw 0x69c0, 0xc08c, 0x69ff, 0xc08c, 0x21, 0 - .dw 0x6a40, 0xc08c, 0x6a7f, 0xc08c, 0x21, 0 - .dw 0x6ac0, 0xc08c, 0x6aff, 0xc08c, 0x21, 0 - .dw 0x6b40, 0xc08c, 0x6b7f, 0xc08c, 0x21, 0 - .dw 0x6bc0, 0xc08c, 0x6bff, 0xc08c, 0x21, 0 - .dw 0x6c40, 0xc08c, 0x6c7f, 0xc08c, 0x21, 0 - .dw 0x6cc0, 0xc08c, 0x6cff, 0xc08c, 0x21, 0 - .dw 0x6d40, 0xc08c, 0x6d7f, 0xc08c, 0x21, 0 - .dw 0x6dc0, 0xc08c, 0x6dff, 0xc08c, 0x21, 0 - .dw 0x6e40, 0xc08c, 0x6e7f, 0xc08c, 0x21, 0 - .dw 0x6ec0, 0xc08c, 0x6eff, 0xc08c, 0x21, 0 - .dw 0x6f40, 0xc08c, 0x6f7f, 0xc08c, 0x21, 0 - .dw 0x6fc0, 0xc08c, 0x6fff, 0xc08c, 0x21, 0 - .dw 0x7040, 0xc08c, 0x707f, 0xc08c, 0x21, 0 - .dw 0x70c0, 0xc08c, 0x70ff, 0xc08c, 0x21, 0 - .dw 0x7140, 0xc08c, 0x717f, 0xc08c, 0x21, 0 - .dw 0x71c0, 0xc08c, 0x71ff, 0xc08c, 0x21, 0 - .dw 0x7240, 0xc08c, 0x727f, 0xc08c, 0x21, 0 - .dw 0x72c0, 0xc08c, 0x72ff, 0xc08c, 0x21, 0 - .dw 0x7340, 0xc08c, 0x737f, 0xc08c, 0x21, 0 - .dw 0x73c0, 0xc08c, 0x73ff, 0xc08c, 0x21, 0 - .dw 0x7440, 0xc08c, 0x747f, 0xc08c, 0x21, 0 - .dw 0x74c0, 0xc08c, 0x74ff, 0xc08c, 0x21, 0 - .dw 0x7540, 0xc08c, 0x757f, 0xc08c, 0x21, 0 - .dw 0x75c0, 0xc08c, 0x75ff, 0xc08c, 0x21, 0 - .dw 0x7640, 0xc08c, 0x767f, 0xc08c, 0x21, 0 - .dw 0x76c0, 0xc08c, 0x76ff, 0xc08c, 0x21, 0 - .dw 0x7740, 0xc08c, 0x777f, 0xc08c, 0x21, 0 - .dw 0x77c0, 0xc08c, 0x77ff, 0xc08c, 0x21, 0 - .dw 0x7840, 0xc08c, 0x787f, 0xc08c, 0x21, 0 - .dw 0x78c0, 0xc08c, 0x78ff, 0xc08c, 0x21, 0 - .dw 0x7940, 0xc08c, 0x797f, 0xc08c, 0x21, 0 - .dw 0x79c0, 0xc08c, 0x7fff, 0xc08c, 0x21, 0 - .dw 0x8040, 0xc08c, 0x807f, 0xc08c, 0x21, 0 - .dw 0x80c0, 0xc08c, 0x80ff, 0xc08c, 0x21, 0 - .dw 0x8140, 0xc08c, 0x817f, 0xc08c, 0x21, 0 - .dw 0x81c0, 0xc08c, 0x81ff, 0xc08c, 0x21, 0 - .dw 0x8240, 0xc08c, 0x827f, 0xc08c, 0x21, 0 - .dw 0x82c0, 0xc08c, 0x82ff, 0xc08c, 0x21, 0 - .dw 0x8340, 0xc08c, 0x837f, 0xc08c, 0x21, 0 - .dw 0x83c0, 0xc08c, 0x83ff, 0xc08c, 0x21, 0 - .dw 0x8440, 0xc08c, 0x847f, 0xc08c, 0x21, 0 - .dw 0x84c0, 0xc08c, 0x84ff, 0xc08c, 0x21, 0 - .dw 0x8540, 0xc08c, 0x857f, 0xc08c, 0x21, 0 - .dw 0x85c0, 0xc08c, 0x85ff, 0xc08c, 0x21, 0 - .dw 0x8640, 0xc08c, 0x867f, 0xc08c, 0x21, 0 - .dw 0x86c0, 0xc08c, 0x86ff, 0xc08c, 0x21, 0 - .dw 0x8740, 0xc08c, 0x877f, 0xc08c, 0x21, 0 - .dw 0x87c0, 0xc08c, 0x87ff, 0xc08c, 0x21, 0 - .dw 0x8840, 0xc08c, 0x887f, 0xc08c, 0x21, 0 - .dw 0x88c0, 0xc08c, 0x88ff, 0xc08c, 0x21, 0 - .dw 0x8940, 0xc08c, 0x897f, 0xc08c, 0x21, 0 - .dw 0x89c0, 0xc08c, 0x89ff, 0xc08c, 0x21, 0 - .dw 0x8a40, 0xc08c, 0x8a7f, 0xc08c, 0x21, 0 - .dw 0x8ac0, 0xc08c, 0x8aff, 0xc08c, 0x21, 0 - .dw 0x8b40, 0xc08c, 0x8b7f, 0xc08c, 0x21, 0 - .dw 0x8bc0, 0xc08c, 0x8bff, 0xc08c, 0x21, 0 - .dw 0x8c40, 0xc08c, 0x8c7f, 0xc08c, 0x21, 0 - .dw 0x8cc0, 0xc08c, 0x8cff, 0xc08c, 0x21, 0 - .dw 0x8d40, 0xc08c, 0x8d7f, 0xc08c, 0x21, 0 - .dw 0x8dc0, 0xc08c, 0x8dff, 0xc08c, 0x21, 0 - .dw 0x8e40, 0xc08c, 0x8e7f, 0xc08c, 0x21, 0 - .dw 0x8ec0, 0xc08c, 0x8eff, 0xc08c, 0x21, 0 - .dw 0x8f40, 0xc08c, 0x8f7f, 0xc08c, 0x21, 0 - .dw 0x8fc0, 0xc08c, 0x8fff, 0xc08c, 0x21, 0 - .dw 0x9040, 0xc08c, 0x907f, 0xc08c, 0x21, 0 - .dw 0x90c0, 0xc08c, 0x90ff, 0xc08c, 0x21, 0 - .dw 0x9140, 0xc08c, 0x917f, 0xc08c, 0x21, 0 - .dw 0x91c0, 0xc08c, 0x91ff, 0xc08c, 0x21, 0 - .dw 0x9240, 0xc08c, 0x927f, 0xc08c, 0x21, 0 - .dw 0x92c0, 0xc08c, 0x92ff, 0xc08c, 0x21, 0 - .dw 0x9340, 0xc08c, 0x937f, 0xc08c, 0x21, 0 - .dw 0x93c0, 0xc08c, 0x93ff, 0xc08c, 0x21, 0 - .dw 0x9440, 0xc08c, 0x947f, 0xc08c, 0x21, 0 - .dw 0x94c0, 0xc08c, 0x94ff, 0xc08c, 0x21, 0 - .dw 0x9540, 0xc08c, 0x957f, 0xc08c, 0x21, 0 - .dw 0x95c0, 0xc08c, 0x95ff, 0xc08c, 0x21, 0 - .dw 0x9640, 0xc08c, 0x967f, 0xc08c, 0x21, 0 - .dw 0x96c0, 0xc08c, 0x96ff, 0xc08c, 0x21, 0 - .dw 0x9740, 0xc08c, 0x977f, 0xc08c, 0x21, 0 - .dw 0x97c0, 0xc08c, 0x97ff, 0xc08c, 0x21, 0 - .dw 0x9840, 0xc08c, 0x987f, 0xc08c, 0x21, 0 - .dw 0x98c0, 0xc08c, 0x98ff, 0xc08c, 0x21, 0 - .dw 0x9940, 0xc08c, 0x997f, 0xc08c, 0x21, 0 - .dw 0x99c0, 0xc08c, 0x9fff, 0xc08c, 0x21, 0 - .dw 0xa040, 0xc08c, 0xa07f, 0xc08c, 0x21, 0 - .dw 0xa0c0, 0xc08c, 0xa0ff, 0xc08c, 0x21, 0 - .dw 0xa140, 0xc08c, 0xa17f, 0xc08c, 0x21, 0 - .dw 0xa1c0, 0xc08c, 0xa1ff, 0xc08c, 0x21, 0 - .dw 0xa240, 0xc08c, 0xa27f, 0xc08c, 0x21, 0 - .dw 0xa2c0, 0xc08c, 0xa2ff, 0xc08c, 0x21, 0 - .dw 0xa340, 0xc08c, 0xa37f, 0xc08c, 0x21, 0 - .dw 0xa3c0, 0xc08c, 0xa3ff, 0xc08c, 0x21, 0 - .dw 0xa440, 0xc08c, 0xa47f, 0xc08c, 0x21, 0 - .dw 0xa4c0, 0xc08c, 0xa4ff, 0xc08c, 0x21, 0 - .dw 0xa540, 0xc08c, 0xa57f, 0xc08c, 0x21, 0 - .dw 0xa5c0, 0xc08c, 0xa5ff, 0xc08c, 0x21, 0 - .dw 0xa640, 0xc08c, 0xa67f, 0xc08c, 0x21, 0 - .dw 0xa6c0, 0xc08c, 0xa6ff, 0xc08c, 0x21, 0 - .dw 0xa740, 0xc08c, 0xa77f, 0xc08c, 0x21, 0 - .dw 0xa7c0, 0xc08c, 0xa7ff, 0xc08c, 0x21, 0 - .dw 0xa840, 0xc08c, 0xa87f, 0xc08c, 0x21, 0 - .dw 0xa8c0, 0xc08c, 0xa8ff, 0xc08c, 0x21, 0 - .dw 0xa940, 0xc08c, 0xa97f, 0xc08c, 0x21, 0 - .dw 0xa9c0, 0xc08c, 0xa9ff, 0xc08c, 0x21, 0 - .dw 0xaa40, 0xc08c, 0xaa7f, 0xc08c, 0x21, 0 - .dw 0xaac0, 0xc08c, 0xaaff, 0xc08c, 0x21, 0 - .dw 0xab40, 0xc08c, 0xab7f, 0xc08c, 0x21, 0 - .dw 0xabc0, 0xc08c, 0xabff, 0xc08c, 0x21, 0 - .dw 0xac40, 0xc08c, 0xac7f, 0xc08c, 0x21, 0 - .dw 0xacc0, 0xc08c, 0xacff, 0xc08c, 0x21, 0 - .dw 0xad40, 0xc08c, 0xad7f, 0xc08c, 0x21, 0 - .dw 0xadc0, 0xc08c, 0xadff, 0xc08c, 0x21, 0 - .dw 0xae40, 0xc08c, 0xae7f, 0xc08c, 0x21, 0 - .dw 0xaec0, 0xc08c, 0xaeff, 0xc08c, 0x21, 0 - .dw 0xaf40, 0xc08c, 0xaf7f, 0xc08c, 0x21, 0 - .dw 0xafc0, 0xc08c, 0xafff, 0xc08c, 0x21, 0 - .dw 0xb040, 0xc08c, 0xb07f, 0xc08c, 0x21, 0 - .dw 0xb0c0, 0xc08c, 0xb0ff, 0xc08c, 0x21, 0 - .dw 0xb140, 0xc08c, 0xb17f, 0xc08c, 0x21, 0 - .dw 0xb1c0, 0xc08c, 0xb1ff, 0xc08c, 0x21, 0 - .dw 0xb240, 0xc08c, 0xb27f, 0xc08c, 0x21, 0 - .dw 0xb2c0, 0xc08c, 0xb2ff, 0xc08c, 0x21, 0 - .dw 0xb340, 0xc08c, 0xb37f, 0xc08c, 0x21, 0 - .dw 0xb3c0, 0xc08c, 0xb3ff, 0xc08c, 0x21, 0 - .dw 0xb440, 0xc08c, 0xb47f, 0xc08c, 0x21, 0 - .dw 0xb4c0, 0xc08c, 0xb4ff, 0xc08c, 0x21, 0 - .dw 0xb540, 0xc08c, 0xb57f, 0xc08c, 0x21, 0 - .dw 0xb5c0, 0xc08c, 0xb5ff, 0xc08c, 0x21, 0 - .dw 0xb640, 0xc08c, 0xb67f, 0xc08c, 0x21, 0 - .dw 0xb6c0, 0xc08c, 0xb6ff, 0xc08c, 0x21, 0 - .dw 0xb740, 0xc08c, 0xb77f, 0xc08c, 0x21, 0 - .dw 0xb7c0, 0xc08c, 0xb7ff, 0xc08c, 0x21, 0 - .dw 0xb840, 0xc08c, 0xb87f, 0xc08c, 0x21, 0 - .dw 0xb8c0, 0xc08c, 0xb8ff, 0xc08c, 0x21, 0 - .dw 0xb940, 0xc08c, 0xb97f, 0xc08c, 0x21, 0 - .dw 0xb9c0, 0xc08c, 0xbfff, 0xc08c, 0x21, 0 - .dw 0xc040, 0xc08c, 0xc07f, 0xc08c, 0x21, 0 - .dw 0xc0c0, 0xc08c, 0xc0ff, 0xc08c, 0x21, 0 - .dw 0xc140, 0xc08c, 0xc17f, 0xc08c, 0x21, 0 - .dw 0xc1c0, 0xc08c, 0xc1ff, 0xc08c, 0x21, 0 - .dw 0xc240, 0xc08c, 0xc27f, 0xc08c, 0x21, 0 - .dw 0xc2c0, 0xc08c, 0xc2ff, 0xc08c, 0x21, 0 - .dw 0xc340, 0xc08c, 0xc37f, 0xc08c, 0x21, 0 - .dw 0xc3c0, 0xc08c, 0xc3ff, 0xc08c, 0x21, 0 - .dw 0xc440, 0xc08c, 0xc47f, 0xc08c, 0x21, 0 - .dw 0xc4c0, 0xc08c, 0xc4ff, 0xc08c, 0x21, 0 - .dw 0xc540, 0xc08c, 0xc57f, 0xc08c, 0x21, 0 - .dw 0xc5c0, 0xc08c, 0xc5ff, 0xc08c, 0x21, 0 - .dw 0xc640, 0xc08c, 0xc67f, 0xc08c, 0x21, 0 - .dw 0xc6c0, 0xc08c, 0xc6ff, 0xc08c, 0x21, 0 - .dw 0xc740, 0xc08c, 0xc77f, 0xc08c, 0x21, 0 - .dw 0xc7c0, 0xc08c, 0xc7ff, 0xc08c, 0x21, 0 - .dw 0xc840, 0xc08c, 0xc87f, 0xc08c, 0x21, 0 - .dw 0xc8c0, 0xc08c, 0xc8ff, 0xc08c, 0x21, 0 - .dw 0xc940, 0xc08c, 0xc97f, 0xc08c, 0x21, 0 - .dw 0xc9c0, 0xc08c, 0xc9ff, 0xc08c, 0x21, 0 - .dw 0xca40, 0xc08c, 0xca7f, 0xc08c, 0x21, 0 - .dw 0xcac0, 0xc08c, 0xcaff, 0xc08c, 0x21, 0 - .dw 0xcb40, 0xc08c, 0xcb7f, 0xc08c, 0x21, 0 - .dw 0xcbc0, 0xc08c, 0xcbff, 0xc08c, 0x21, 0 - .dw 0xcc40, 0xc08c, 0xcc7f, 0xc08c, 0x21, 0 - .dw 0xccc0, 0xc08c, 0xccff, 0xc08c, 0x21, 0 - .dw 0xcd40, 0xc08c, 0xcd7f, 0xc08c, 0x21, 0 - .dw 0xcdc0, 0xc08c, 0xcdff, 0xc08c, 0x21, 0 - .dw 0xce40, 0xc08c, 0xce7f, 0xc08c, 0x21, 0 - .dw 0xcec0, 0xc08c, 0xceff, 0xc08c, 0x21, 0 - .dw 0xcf40, 0xc08c, 0xcf7f, 0xc08c, 0x21, 0 - .dw 0xcfc0, 0xc08c, 0xcfff, 0xc08c, 0x21, 0 - .dw 0xd040, 0xc08c, 0xd07f, 0xc08c, 0x21, 0 - .dw 0xd0c0, 0xc08c, 0xd0ff, 0xc08c, 0x21, 0 - .dw 0xd140, 0xc08c, 0xd17f, 0xc08c, 0x21, 0 - .dw 0xd1c0, 0xc08c, 0xd1ff, 0xc08c, 0x21, 0 - .dw 0xd240, 0xc08c, 0xd27f, 0xc08c, 0x21, 0 - .dw 0xd2c0, 0xc08c, 0xd2ff, 0xc08c, 0x21, 0 - .dw 0xd340, 0xc08c, 0xd37f, 0xc08c, 0x21, 0 - .dw 0xd3c0, 0xc08c, 0xd3ff, 0xc08c, 0x21, 0 - .dw 0xd440, 0xc08c, 0xd47f, 0xc08c, 0x21, 0 - .dw 0xd4c0, 0xc08c, 0xd4ff, 0xc08c, 0x21, 0 - .dw 0xd540, 0xc08c, 0xd57f, 0xc08c, 0x21, 0 - .dw 0xd5c0, 0xc08c, 0xd5ff, 0xc08c, 0x21, 0 - .dw 0xd640, 0xc08c, 0xd67f, 0xc08c, 0x21, 0 - .dw 0xd6c0, 0xc08c, 0xd6ff, 0xc08c, 0x21, 0 - .dw 0xd740, 0xc08c, 0xd77f, 0xc08c, 0x21, 0 - .dw 0xd7c0, 0xc08c, 0xd7ff, 0xc08c, 0x21, 0 - .dw 0xd840, 0xc08c, 0xd87f, 0xc08c, 0x21, 0 - .dw 0xd8c0, 0xc08c, 0xd8ff, 0xc08c, 0x21, 0 - .dw 0xd940, 0xc08c, 0xd97f, 0xc08c, 0x21, 0 - .dw 0xd9c0, 0xc08c, 0xdfff, 0xc08c, 0x21, 0 - .dw 0xe040, 0xc08c, 0xe07f, 0xc08c, 0x21, 0 - .dw 0xe0c0, 0xc08c, 0xe0ff, 0xc08c, 0x21, 0 - .dw 0xe140, 0xc08c, 0xe17f, 0xc08c, 0x21, 0 - .dw 0xe1c0, 0xc08c, 0xe1ff, 0xc08c, 0x21, 0 - .dw 0xe240, 0xc08c, 0xe27f, 0xc08c, 0x21, 0 - .dw 0xe2c0, 0xc08c, 0xe2ff, 0xc08c, 0x21, 0 - .dw 0xe340, 0xc08c, 0xe37f, 0xc08c, 0x21, 0 - .dw 0xe3c0, 0xc08c, 0xe3ff, 0xc08c, 0x21, 0 - .dw 0xe440, 0xc08c, 0xe47f, 0xc08c, 0x21, 0 - .dw 0xe4c0, 0xc08c, 0xe4ff, 0xc08c, 0x21, 0 - .dw 0xe540, 0xc08c, 0xe57f, 0xc08c, 0x21, 0 - .dw 0xe5c0, 0xc08c, 0xe5ff, 0xc08c, 0x21, 0 - .dw 0xe640, 0xc08c, 0xe67f, 0xc08c, 0x21, 0 - .dw 0xe6c0, 0xc08c, 0xe6ff, 0xc08c, 0x21, 0 - .dw 0xe740, 0xc08c, 0xe77f, 0xc08c, 0x21, 0 - .dw 0xe7c0, 0xc08c, 0xe7ff, 0xc08c, 0x21, 0 - .dw 0xe840, 0xc08c, 0xe87f, 0xc08c, 0x21, 0 - .dw 0xe8c0, 0xc08c, 0xe8ff, 0xc08c, 0x21, 0 - .dw 0xe940, 0xc08c, 0xe97f, 0xc08c, 0x21, 0 - .dw 0xe9c0, 0xc08c, 0xe9ff, 0xc08c, 0x21, 0 - .dw 0xea40, 0xc08c, 0xea7f, 0xc08c, 0x21, 0 - .dw 0xeac0, 0xc08c, 0xeaff, 0xc08c, 0x21, 0 - .dw 0xeb40, 0xc08c, 0xeb7f, 0xc08c, 0x21, 0 - .dw 0xebc0, 0xc08c, 0xebff, 0xc08c, 0x21, 0 - .dw 0xec40, 0xc08c, 0xec7f, 0xc08c, 0x21, 0 - .dw 0xecc0, 0xc08c, 0xecff, 0xc08c, 0x21, 0 - .dw 0xed40, 0xc08c, 0xed7f, 0xc08c, 0x21, 0 - .dw 0xedc0, 0xc08c, 0xedff, 0xc08c, 0x21, 0 - .dw 0xee40, 0xc08c, 0xee7f, 0xc08c, 0x21, 0 - .dw 0xeec0, 0xc08c, 0xeeff, 0xc08c, 0x21, 0 - .dw 0xef40, 0xc08c, 0xef7f, 0xc08c, 0x21, 0 - .dw 0xefc0, 0xc08c, 0xefff, 0xc08c, 0x21, 0 - .dw 0xf040, 0xc08c, 0xf07f, 0xc08c, 0x21, 0 - .dw 0xf0c0, 0xc08c, 0xf0ff, 0xc08c, 0x21, 0 - .dw 0xf140, 0xc08c, 0xf17f, 0xc08c, 0x21, 0 - .dw 0xf1c0, 0xc08c, 0xf1ff, 0xc08c, 0x21, 0 - .dw 0xf240, 0xc08c, 0xf27f, 0xc08c, 0x21, 0 - .dw 0xf2c0, 0xc08c, 0xf2ff, 0xc08c, 0x21, 0 - .dw 0xf340, 0xc08c, 0xf37f, 0xc08c, 0x21, 0 - .dw 0xf3c0, 0xc08c, 0xf3ff, 0xc08c, 0x21, 0 - .dw 0xf440, 0xc08c, 0xf47f, 0xc08c, 0x21, 0 - .dw 0xf4c0, 0xc08c, 0xf4ff, 0xc08c, 0x21, 0 - .dw 0xf540, 0xc08c, 0xf57f, 0xc08c, 0x21, 0 - .dw 0xf5c0, 0xc08c, 0xf5ff, 0xc08c, 0x21, 0 - .dw 0xf640, 0xc08c, 0xf67f, 0xc08c, 0x21, 0 - .dw 0xf6c0, 0xc08c, 0xf6ff, 0xc08c, 0x21, 0 - .dw 0xf740, 0xc08c, 0xf77f, 0xc08c, 0x21, 0 - .dw 0xf7c0, 0xc08c, 0xf7ff, 0xc08c, 0x21, 0 - .dw 0xf840, 0xc08c, 0xf87f, 0xc08c, 0x21, 0 - .dw 0xf8c0, 0xc08c, 0xf8ff, 0xc08c, 0x21, 0 - .dw 0xf940, 0xc08c, 0xf97f, 0xc08c, 0x21, 0 - .dw 0xf9c0, 0xc08c, 0xffff, 0xc08c, 0x21, 0 - .dw 0x0040, 0xc08d, 0x007f, 0xc08d, 0x21, 0 - .dw 0x00c0, 0xc08d, 0x00ff, 0xc08d, 0x21, 0 - .dw 0x0140, 0xc08d, 0x017f, 0xc08d, 0x21, 0 - .dw 0x01c0, 0xc08d, 0x01ff, 0xc08d, 0x21, 0 - .dw 0x0240, 0xc08d, 0x027f, 0xc08d, 0x21, 0 - .dw 0x02c0, 0xc08d, 0x02ff, 0xc08d, 0x21, 0 - .dw 0x0340, 0xc08d, 0x037f, 0xc08d, 0x21, 0 - .dw 0x03c0, 0xc08d, 0x03ff, 0xc08d, 0x21, 0 - .dw 0x0440, 0xc08d, 0x047f, 0xc08d, 0x21, 0 - .dw 0x04c0, 0xc08d, 0x04ff, 0xc08d, 0x21, 0 - .dw 0x0540, 0xc08d, 0x057f, 0xc08d, 0x21, 0 - .dw 0x05c0, 0xc08d, 0x05ff, 0xc08d, 0x21, 0 - .dw 0x0640, 0xc08d, 0x067f, 0xc08d, 0x21, 0 - .dw 0x06c0, 0xc08d, 0x06ff, 0xc08d, 0x21, 0 - .dw 0x0740, 0xc08d, 0x077f, 0xc08d, 0x21, 0 - .dw 0x07c0, 0xc08d, 0x07ff, 0xc08d, 0x21, 0 - .dw 0x0840, 0xc08d, 0x087f, 0xc08d, 0x21, 0 - .dw 0x08c0, 0xc08d, 0x08ff, 0xc08d, 0x21, 0 - .dw 0x0940, 0xc08d, 0x097f, 0xc08d, 0x21, 0 - .dw 0x09c0, 0xc08d, 0x09ff, 0xc08d, 0x21, 0 - .dw 0x0a40, 0xc08d, 0x0a7f, 0xc08d, 0x21, 0 - .dw 0x0ac0, 0xc08d, 0x0aff, 0xc08d, 0x21, 0 - .dw 0x0b40, 0xc08d, 0x0b7f, 0xc08d, 0x21, 0 - .dw 0x0bc0, 0xc08d, 0x0bff, 0xc08d, 0x21, 0 - .dw 0x0c40, 0xc08d, 0x0c7f, 0xc08d, 0x21, 0 - .dw 0x0cc0, 0xc08d, 0x0cff, 0xc08d, 0x21, 0 - .dw 0x0d40, 0xc08d, 0x0d7f, 0xc08d, 0x21, 0 - .dw 0x0dc0, 0xc08d, 0x0dff, 0xc08d, 0x21, 0 - .dw 0x0e40, 0xc08d, 0x0e7f, 0xc08d, 0x21, 0 - .dw 0x0ec0, 0xc08d, 0x0eff, 0xc08d, 0x21, 0 - .dw 0x0f40, 0xc08d, 0x0f7f, 0xc08d, 0x21, 0 - .dw 0x0fc0, 0xc08d, 0x0fff, 0xc08d, 0x21, 0 - .dw 0x1040, 0xc08d, 0x107f, 0xc08d, 0x21, 0 - .dw 0x10c0, 0xc08d, 0x10ff, 0xc08d, 0x21, 0 - .dw 0x1140, 0xc08d, 0x117f, 0xc08d, 0x21, 0 - .dw 0x11c0, 0xc08d, 0x11ff, 0xc08d, 0x21, 0 - .dw 0x1240, 0xc08d, 0x127f, 0xc08d, 0x21, 0 - .dw 0x12c0, 0xc08d, 0x12ff, 0xc08d, 0x21, 0 - .dw 0x1340, 0xc08d, 0x137f, 0xc08d, 0x21, 0 - .dw 0x13c0, 0xc08d, 0x13ff, 0xc08d, 0x21, 0 - .dw 0x1440, 0xc08d, 0x147f, 0xc08d, 0x21, 0 - .dw 0x14c0, 0xc08d, 0x14ff, 0xc08d, 0x21, 0 - .dw 0x1540, 0xc08d, 0x157f, 0xc08d, 0x21, 0 - .dw 0x15c0, 0xc08d, 0x15ff, 0xc08d, 0x21, 0 - .dw 0x1640, 0xc08d, 0x167f, 0xc08d, 0x21, 0 - .dw 0x16c0, 0xc08d, 0x16ff, 0xc08d, 0x21, 0 - .dw 0x1740, 0xc08d, 0x177f, 0xc08d, 0x21, 0 - .dw 0x17c0, 0xc08d, 0x17ff, 0xc08d, 0x21, 0 - .dw 0x1840, 0xc08d, 0x187f, 0xc08d, 0x21, 0 - .dw 0x18c0, 0xc08d, 0x18ff, 0xc08d, 0x21, 0 - .dw 0x1940, 0xc08d, 0x197f, 0xc08d, 0x21, 0 - .dw 0x19c0, 0xc08d, 0x1fff, 0xc08d, 0x21, 0 - .dw 0x2040, 0xc08d, 0x207f, 0xc08d, 0x21, 0 - .dw 0x20c0, 0xc08d, 0x20ff, 0xc08d, 0x21, 0 - .dw 0x2140, 0xc08d, 0x217f, 0xc08d, 0x21, 0 - .dw 0x21c0, 0xc08d, 0x21ff, 0xc08d, 0x21, 0 - .dw 0x2240, 0xc08d, 0x227f, 0xc08d, 0x21, 0 - .dw 0x22c0, 0xc08d, 0x22ff, 0xc08d, 0x21, 0 - .dw 0x2340, 0xc08d, 0x237f, 0xc08d, 0x21, 0 - .dw 0x23c0, 0xc08d, 0x23ff, 0xc08d, 0x21, 0 - .dw 0x2440, 0xc08d, 0x247f, 0xc08d, 0x21, 0 - .dw 0x24c0, 0xc08d, 0x24ff, 0xc08d, 0x21, 0 - .dw 0x2540, 0xc08d, 0x257f, 0xc08d, 0x21, 0 - .dw 0x25c0, 0xc08d, 0x25ff, 0xc08d, 0x21, 0 - .dw 0x2640, 0xc08d, 0x267f, 0xc08d, 0x21, 0 - .dw 0x26c0, 0xc08d, 0x26ff, 0xc08d, 0x21, 0 - .dw 0x2740, 0xc08d, 0x277f, 0xc08d, 0x21, 0 - .dw 0x27c0, 0xc08d, 0x27ff, 0xc08d, 0x21, 0 - .dw 0x2840, 0xc08d, 0x287f, 0xc08d, 0x21, 0 - .dw 0x28c0, 0xc08d, 0x28ff, 0xc08d, 0x21, 0 - .dw 0x2940, 0xc08d, 0x297f, 0xc08d, 0x21, 0 - .dw 0x29c0, 0xc08d, 0x29ff, 0xc08d, 0x21, 0 - .dw 0x2a40, 0xc08d, 0x2a7f, 0xc08d, 0x21, 0 - .dw 0x2ac0, 0xc08d, 0x2aff, 0xc08d, 0x21, 0 - .dw 0x2b40, 0xc08d, 0x2b7f, 0xc08d, 0x21, 0 - .dw 0x2bc0, 0xc08d, 0x2bff, 0xc08d, 0x21, 0 - .dw 0x2c40, 0xc08d, 0x2c7f, 0xc08d, 0x21, 0 - .dw 0x2cc0, 0xc08d, 0x2cff, 0xc08d, 0x21, 0 - .dw 0x2d40, 0xc08d, 0x2d7f, 0xc08d, 0x21, 0 - .dw 0x2dc0, 0xc08d, 0x2dff, 0xc08d, 0x21, 0 - .dw 0x2e40, 0xc08d, 0x2e7f, 0xc08d, 0x21, 0 - .dw 0x2ec0, 0xc08d, 0x2eff, 0xc08d, 0x21, 0 - .dw 0x2f40, 0xc08d, 0x2f7f, 0xc08d, 0x21, 0 - .dw 0x2fc0, 0xc08d, 0x2fff, 0xc08d, 0x21, 0 - .dw 0x3040, 0xc08d, 0x307f, 0xc08d, 0x21, 0 - .dw 0x30c0, 0xc08d, 0x30ff, 0xc08d, 0x21, 0 - .dw 0x3140, 0xc08d, 0x317f, 0xc08d, 0x21, 0 - .dw 0x31c0, 0xc08d, 0x31ff, 0xc08d, 0x21, 0 - .dw 0x3240, 0xc08d, 0x327f, 0xc08d, 0x21, 0 - .dw 0x32c0, 0xc08d, 0x32ff, 0xc08d, 0x21, 0 - .dw 0x3340, 0xc08d, 0x337f, 0xc08d, 0x21, 0 - .dw 0x33c0, 0xc08d, 0x33ff, 0xc08d, 0x21, 0 - .dw 0x3440, 0xc08d, 0x347f, 0xc08d, 0x21, 0 - .dw 0x34c0, 0xc08d, 0x34ff, 0xc08d, 0x21, 0 - .dw 0x3540, 0xc08d, 0x357f, 0xc08d, 0x21, 0 - .dw 0x35c0, 0xc08d, 0x35ff, 0xc08d, 0x21, 0 - .dw 0x3640, 0xc08d, 0x367f, 0xc08d, 0x21, 0 - .dw 0x36c0, 0xc08d, 0x36ff, 0xc08d, 0x21, 0 - .dw 0x3740, 0xc08d, 0x377f, 0xc08d, 0x21, 0 - .dw 0x37c0, 0xc08d, 0x37ff, 0xc08d, 0x21, 0 - .dw 0x3840, 0xc08d, 0x387f, 0xc08d, 0x21, 0 - .dw 0x38c0, 0xc08d, 0x38ff, 0xc08d, 0x21, 0 - .dw 0x3940, 0xc08d, 0x397f, 0xc08d, 0x21, 0 - .dw 0x39c0, 0xc08d, 0x3fff, 0xc08d, 0x21, 0 - .dw 0x4040, 0xc08d, 0x407f, 0xc08d, 0x21, 0 - .dw 0x40c0, 0xc08d, 0x40ff, 0xc08d, 0x21, 0 - .dw 0x4140, 0xc08d, 0x417f, 0xc08d, 0x21, 0 - .dw 0x41c0, 0xc08d, 0x41ff, 0xc08d, 0x21, 0 - .dw 0x4240, 0xc08d, 0x427f, 0xc08d, 0x21, 0 - .dw 0x42c0, 0xc08d, 0x42ff, 0xc08d, 0x21, 0 - .dw 0x4340, 0xc08d, 0x437f, 0xc08d, 0x21, 0 - .dw 0x43c0, 0xc08d, 0x43ff, 0xc08d, 0x21, 0 - .dw 0x4440, 0xc08d, 0x447f, 0xc08d, 0x21, 0 - .dw 0x44c0, 0xc08d, 0x44ff, 0xc08d, 0x21, 0 - .dw 0x4540, 0xc08d, 0x457f, 0xc08d, 0x21, 0 - .dw 0x45c0, 0xc08d, 0x45ff, 0xc08d, 0x21, 0 - .dw 0x4640, 0xc08d, 0x467f, 0xc08d, 0x21, 0 - .dw 0x46c0, 0xc08d, 0x46ff, 0xc08d, 0x21, 0 - .dw 0x4740, 0xc08d, 0x477f, 0xc08d, 0x21, 0 - .dw 0x47c0, 0xc08d, 0x47ff, 0xc08d, 0x21, 0 - .dw 0x4840, 0xc08d, 0x487f, 0xc08d, 0x21, 0 - .dw 0x48c0, 0xc08d, 0x48ff, 0xc08d, 0x21, 0 - .dw 0x4940, 0xc08d, 0x497f, 0xc08d, 0x21, 0 - .dw 0x49c0, 0xc08d, 0x49ff, 0xc08d, 0x21, 0 - .dw 0x4a40, 0xc08d, 0x4a7f, 0xc08d, 0x21, 0 - .dw 0x4ac0, 0xc08d, 0x4aff, 0xc08d, 0x21, 0 - .dw 0x4b40, 0xc08d, 0x4b7f, 0xc08d, 0x21, 0 - .dw 0x4bc0, 0xc08d, 0x4bff, 0xc08d, 0x21, 0 - .dw 0x4c40, 0xc08d, 0x4c7f, 0xc08d, 0x21, 0 - .dw 0x4cc0, 0xc08d, 0x4cff, 0xc08d, 0x21, 0 - .dw 0x4d40, 0xc08d, 0x4d7f, 0xc08d, 0x21, 0 - .dw 0x4dc0, 0xc08d, 0x4dff, 0xc08d, 0x21, 0 - .dw 0x4e40, 0xc08d, 0x4e7f, 0xc08d, 0x21, 0 - .dw 0x4ec0, 0xc08d, 0x4eff, 0xc08d, 0x21, 0 - .dw 0x4f40, 0xc08d, 0x4f7f, 0xc08d, 0x21, 0 - .dw 0x4fc0, 0xc08d, 0x4fff, 0xc08d, 0x21, 0 - .dw 0x5040, 0xc08d, 0x507f, 0xc08d, 0x21, 0 - .dw 0x50c0, 0xc08d, 0x50ff, 0xc08d, 0x21, 0 - .dw 0x5140, 0xc08d, 0x517f, 0xc08d, 0x21, 0 - .dw 0x51c0, 0xc08d, 0x51ff, 0xc08d, 0x21, 0 - .dw 0x5240, 0xc08d, 0x527f, 0xc08d, 0x21, 0 - .dw 0x52c0, 0xc08d, 0x52ff, 0xc08d, 0x21, 0 - .dw 0x5340, 0xc08d, 0x537f, 0xc08d, 0x21, 0 - .dw 0x53c0, 0xc08d, 0x53ff, 0xc08d, 0x21, 0 - .dw 0x5440, 0xc08d, 0x547f, 0xc08d, 0x21, 0 - .dw 0x54c0, 0xc08d, 0x54ff, 0xc08d, 0x21, 0 - .dw 0x5540, 0xc08d, 0x557f, 0xc08d, 0x21, 0 - .dw 0x55c0, 0xc08d, 0x55ff, 0xc08d, 0x21, 0 - .dw 0x5640, 0xc08d, 0x567f, 0xc08d, 0x21, 0 - .dw 0x56c0, 0xc08d, 0x56ff, 0xc08d, 0x21, 0 - .dw 0x5740, 0xc08d, 0x577f, 0xc08d, 0x21, 0 - .dw 0x57c0, 0xc08d, 0x57ff, 0xc08d, 0x21, 0 - .dw 0x5840, 0xc08d, 0x587f, 0xc08d, 0x21, 0 - .dw 0x58c0, 0xc08d, 0x58ff, 0xc08d, 0x21, 0 - .dw 0x5940, 0xc08d, 0x597f, 0xc08d, 0x21, 0 - .dw 0x59c0, 0xc08d, 0x5fff, 0xc08d, 0x21, 0 - .dw 0x6040, 0xc08d, 0x607f, 0xc08d, 0x21, 0 - .dw 0x60c0, 0xc08d, 0x60ff, 0xc08d, 0x21, 0 - .dw 0x6140, 0xc08d, 0x617f, 0xc08d, 0x21, 0 - .dw 0x61c0, 0xc08d, 0x61ff, 0xc08d, 0x21, 0 - .dw 0x6240, 0xc08d, 0x627f, 0xc08d, 0x21, 0 - .dw 0x62c0, 0xc08d, 0x62ff, 0xc08d, 0x21, 0 - .dw 0x6340, 0xc08d, 0x637f, 0xc08d, 0x21, 0 - .dw 0x63c0, 0xc08d, 0x63ff, 0xc08d, 0x21, 0 - .dw 0x6440, 0xc08d, 0x647f, 0xc08d, 0x21, 0 - .dw 0x64c0, 0xc08d, 0x64ff, 0xc08d, 0x21, 0 - .dw 0x6540, 0xc08d, 0x657f, 0xc08d, 0x21, 0 - .dw 0x65c0, 0xc08d, 0x65ff, 0xc08d, 0x21, 0 - .dw 0x6640, 0xc08d, 0x667f, 0xc08d, 0x21, 0 - .dw 0x66c0, 0xc08d, 0x66ff, 0xc08d, 0x21, 0 - .dw 0x6740, 0xc08d, 0x677f, 0xc08d, 0x21, 0 - .dw 0x67c0, 0xc08d, 0x67ff, 0xc08d, 0x21, 0 - .dw 0x6840, 0xc08d, 0x687f, 0xc08d, 0x21, 0 - .dw 0x68c0, 0xc08d, 0x68ff, 0xc08d, 0x21, 0 - .dw 0x6940, 0xc08d, 0x697f, 0xc08d, 0x21, 0 - .dw 0x69c0, 0xc08d, 0x69ff, 0xc08d, 0x21, 0 - .dw 0x6a40, 0xc08d, 0x6a7f, 0xc08d, 0x21, 0 - .dw 0x6ac0, 0xc08d, 0x6aff, 0xc08d, 0x21, 0 - .dw 0x6b40, 0xc08d, 0x6b7f, 0xc08d, 0x21, 0 - .dw 0x6bc0, 0xc08d, 0x6bff, 0xc08d, 0x21, 0 - .dw 0x6c40, 0xc08d, 0x6c7f, 0xc08d, 0x21, 0 - .dw 0x6cc0, 0xc08d, 0x6cff, 0xc08d, 0x21, 0 - .dw 0x6d40, 0xc08d, 0x6d7f, 0xc08d, 0x21, 0 - .dw 0x6dc0, 0xc08d, 0x6dff, 0xc08d, 0x21, 0 - .dw 0x6e40, 0xc08d, 0x6e7f, 0xc08d, 0x21, 0 - .dw 0x6ec0, 0xc08d, 0x6eff, 0xc08d, 0x21, 0 - .dw 0x6f40, 0xc08d, 0x6f7f, 0xc08d, 0x21, 0 - .dw 0x6fc0, 0xc08d, 0x6fff, 0xc08d, 0x21, 0 - .dw 0x7040, 0xc08d, 0x707f, 0xc08d, 0x21, 0 - .dw 0x70c0, 0xc08d, 0x70ff, 0xc08d, 0x21, 0 - .dw 0x7140, 0xc08d, 0x717f, 0xc08d, 0x21, 0 - .dw 0x71c0, 0xc08d, 0x71ff, 0xc08d, 0x21, 0 - .dw 0x7240, 0xc08d, 0x727f, 0xc08d, 0x21, 0 - .dw 0x72c0, 0xc08d, 0x72ff, 0xc08d, 0x21, 0 - .dw 0x7340, 0xc08d, 0x737f, 0xc08d, 0x21, 0 - .dw 0x73c0, 0xc08d, 0x73ff, 0xc08d, 0x21, 0 - .dw 0x7440, 0xc08d, 0x747f, 0xc08d, 0x21, 0 - .dw 0x74c0, 0xc08d, 0x74ff, 0xc08d, 0x21, 0 - .dw 0x7540, 0xc08d, 0x757f, 0xc08d, 0x21, 0 - .dw 0x75c0, 0xc08d, 0x75ff, 0xc08d, 0x21, 0 - .dw 0x7640, 0xc08d, 0x767f, 0xc08d, 0x21, 0 - .dw 0x76c0, 0xc08d, 0x76ff, 0xc08d, 0x21, 0 - .dw 0x7740, 0xc08d, 0x777f, 0xc08d, 0x21, 0 - .dw 0x77c0, 0xc08d, 0x77ff, 0xc08d, 0x21, 0 - .dw 0x7840, 0xc08d, 0x787f, 0xc08d, 0x21, 0 - .dw 0x78c0, 0xc08d, 0x78ff, 0xc08d, 0x21, 0 - .dw 0x7940, 0xc08d, 0x797f, 0xc08d, 0x21, 0 - .dw 0x79c0, 0xc08d, 0x7fff, 0xc08d, 0x21, 0 - .dw 0x8040, 0xc08d, 0x807f, 0xc08d, 0x21, 0 - .dw 0x80c0, 0xc08d, 0x80ff, 0xc08d, 0x21, 0 - .dw 0x8140, 0xc08d, 0x817f, 0xc08d, 0x21, 0 - .dw 0x81c0, 0xc08d, 0x81ff, 0xc08d, 0x21, 0 - .dw 0x8240, 0xc08d, 0x827f, 0xc08d, 0x21, 0 - .dw 0x82c0, 0xc08d, 0x82ff, 0xc08d, 0x21, 0 - .dw 0x8340, 0xc08d, 0x837f, 0xc08d, 0x21, 0 - .dw 0x83c0, 0xc08d, 0x83ff, 0xc08d, 0x21, 0 - .dw 0x8440, 0xc08d, 0x847f, 0xc08d, 0x21, 0 - .dw 0x84c0, 0xc08d, 0x84ff, 0xc08d, 0x21, 0 - .dw 0x8540, 0xc08d, 0x857f, 0xc08d, 0x21, 0 - .dw 0x85c0, 0xc08d, 0x85ff, 0xc08d, 0x21, 0 - .dw 0x8640, 0xc08d, 0x867f, 0xc08d, 0x21, 0 - .dw 0x86c0, 0xc08d, 0x86ff, 0xc08d, 0x21, 0 - .dw 0x8740, 0xc08d, 0x877f, 0xc08d, 0x21, 0 - .dw 0x87c0, 0xc08d, 0x87ff, 0xc08d, 0x21, 0 - .dw 0x8840, 0xc08d, 0x887f, 0xc08d, 0x21, 0 - .dw 0x88c0, 0xc08d, 0x88ff, 0xc08d, 0x21, 0 - .dw 0x8940, 0xc08d, 0x897f, 0xc08d, 0x21, 0 - .dw 0x89c0, 0xc08d, 0x89ff, 0xc08d, 0x21, 0 - .dw 0x8a40, 0xc08d, 0x8a7f, 0xc08d, 0x21, 0 - .dw 0x8ac0, 0xc08d, 0x8aff, 0xc08d, 0x21, 0 - .dw 0x8b40, 0xc08d, 0x8b7f, 0xc08d, 0x21, 0 - .dw 0x8bc0, 0xc08d, 0x8bff, 0xc08d, 0x21, 0 - .dw 0x8c40, 0xc08d, 0x8c7f, 0xc08d, 0x21, 0 - .dw 0x8cc0, 0xc08d, 0x8cff, 0xc08d, 0x21, 0 - .dw 0x8d40, 0xc08d, 0x8d7f, 0xc08d, 0x21, 0 - .dw 0x8dc0, 0xc08d, 0x8dff, 0xc08d, 0x21, 0 - .dw 0x8e40, 0xc08d, 0x8e7f, 0xc08d, 0x21, 0 - .dw 0x8ec0, 0xc08d, 0x8eff, 0xc08d, 0x21, 0 - .dw 0x8f40, 0xc08d, 0x8f7f, 0xc08d, 0x21, 0 - .dw 0x8fc0, 0xc08d, 0x8fff, 0xc08d, 0x21, 0 - .dw 0x9040, 0xc08d, 0x907f, 0xc08d, 0x21, 0 - .dw 0x90c0, 0xc08d, 0x90ff, 0xc08d, 0x21, 0 - .dw 0x9140, 0xc08d, 0x917f, 0xc08d, 0x21, 0 - .dw 0x91c0, 0xc08d, 0x91ff, 0xc08d, 0x21, 0 - .dw 0x9240, 0xc08d, 0x927f, 0xc08d, 0x21, 0 - .dw 0x92c0, 0xc08d, 0x92ff, 0xc08d, 0x21, 0 - .dw 0x9340, 0xc08d, 0x937f, 0xc08d, 0x21, 0 - .dw 0x93c0, 0xc08d, 0x93ff, 0xc08d, 0x21, 0 - .dw 0x9440, 0xc08d, 0x947f, 0xc08d, 0x21, 0 - .dw 0x94c0, 0xc08d, 0x94ff, 0xc08d, 0x21, 0 - .dw 0x9540, 0xc08d, 0x957f, 0xc08d, 0x21, 0 - .dw 0x95c0, 0xc08d, 0x95ff, 0xc08d, 0x21, 0 - .dw 0x9640, 0xc08d, 0x967f, 0xc08d, 0x21, 0 - .dw 0x96c0, 0xc08d, 0x96ff, 0xc08d, 0x21, 0 - .dw 0x9740, 0xc08d, 0x977f, 0xc08d, 0x21, 0 - .dw 0x97c0, 0xc08d, 0x97ff, 0xc08d, 0x21, 0 - .dw 0x9840, 0xc08d, 0x987f, 0xc08d, 0x21, 0 - .dw 0x98c0, 0xc08d, 0x98ff, 0xc08d, 0x21, 0 - .dw 0x9940, 0xc08d, 0x997f, 0xc08d, 0x21, 0 - .dw 0x99c0, 0xc08d, 0x9fff, 0xc08d, 0x21, 0 - .dw 0xa040, 0xc08d, 0xa07f, 0xc08d, 0x21, 0 - .dw 0xa0c0, 0xc08d, 0xa0ff, 0xc08d, 0x21, 0 - .dw 0xa140, 0xc08d, 0xa17f, 0xc08d, 0x21, 0 - .dw 0xa1c0, 0xc08d, 0xa1ff, 0xc08d, 0x21, 0 - .dw 0xa240, 0xc08d, 0xa27f, 0xc08d, 0x21, 0 - .dw 0xa2c0, 0xc08d, 0xa2ff, 0xc08d, 0x21, 0 - .dw 0xa340, 0xc08d, 0xa37f, 0xc08d, 0x21, 0 - .dw 0xa3c0, 0xc08d, 0xa3ff, 0xc08d, 0x21, 0 - .dw 0xa440, 0xc08d, 0xa47f, 0xc08d, 0x21, 0 - .dw 0xa4c0, 0xc08d, 0xa4ff, 0xc08d, 0x21, 0 - .dw 0xa540, 0xc08d, 0xa57f, 0xc08d, 0x21, 0 - .dw 0xa5c0, 0xc08d, 0xa5ff, 0xc08d, 0x21, 0 - .dw 0xa640, 0xc08d, 0xa67f, 0xc08d, 0x21, 0 - .dw 0xa6c0, 0xc08d, 0xa6ff, 0xc08d, 0x21, 0 - .dw 0xa740, 0xc08d, 0xa77f, 0xc08d, 0x21, 0 - .dw 0xa7c0, 0xc08d, 0xa7ff, 0xc08d, 0x21, 0 - .dw 0xa840, 0xc08d, 0xa87f, 0xc08d, 0x21, 0 - .dw 0xa8c0, 0xc08d, 0xa8ff, 0xc08d, 0x21, 0 - .dw 0xa940, 0xc08d, 0xa97f, 0xc08d, 0x21, 0 - .dw 0xa9c0, 0xc08d, 0xa9ff, 0xc08d, 0x21, 0 - .dw 0xaa40, 0xc08d, 0xaa7f, 0xc08d, 0x21, 0 - .dw 0xaac0, 0xc08d, 0xaaff, 0xc08d, 0x21, 0 - .dw 0xab40, 0xc08d, 0xab7f, 0xc08d, 0x21, 0 - .dw 0xabc0, 0xc08d, 0xabff, 0xc08d, 0x21, 0 - .dw 0xac40, 0xc08d, 0xac7f, 0xc08d, 0x21, 0 - .dw 0xacc0, 0xc08d, 0xacff, 0xc08d, 0x21, 0 - .dw 0xad40, 0xc08d, 0xad7f, 0xc08d, 0x21, 0 - .dw 0xadc0, 0xc08d, 0xadff, 0xc08d, 0x21, 0 - .dw 0xae40, 0xc08d, 0xae7f, 0xc08d, 0x21, 0 - .dw 0xaec0, 0xc08d, 0xaeff, 0xc08d, 0x21, 0 - .dw 0xaf40, 0xc08d, 0xaf7f, 0xc08d, 0x21, 0 - .dw 0xafc0, 0xc08d, 0xafff, 0xc08d, 0x21, 0 - .dw 0xb040, 0xc08d, 0xb07f, 0xc08d, 0x21, 0 - .dw 0xb0c0, 0xc08d, 0xb0ff, 0xc08d, 0x21, 0 - .dw 0xb140, 0xc08d, 0xb17f, 0xc08d, 0x21, 0 - .dw 0xb1c0, 0xc08d, 0xb1ff, 0xc08d, 0x21, 0 - .dw 0xb240, 0xc08d, 0xb27f, 0xc08d, 0x21, 0 - .dw 0xb2c0, 0xc08d, 0xb2ff, 0xc08d, 0x21, 0 - .dw 0xb340, 0xc08d, 0xb37f, 0xc08d, 0x21, 0 - .dw 0xb3c0, 0xc08d, 0xb3ff, 0xc08d, 0x21, 0 - .dw 0xb440, 0xc08d, 0xb47f, 0xc08d, 0x21, 0 - .dw 0xb4c0, 0xc08d, 0xb4ff, 0xc08d, 0x21, 0 - .dw 0xb540, 0xc08d, 0xb57f, 0xc08d, 0x21, 0 - .dw 0xb5c0, 0xc08d, 0xb5ff, 0xc08d, 0x21, 0 - .dw 0xb640, 0xc08d, 0xb67f, 0xc08d, 0x21, 0 - .dw 0xb6c0, 0xc08d, 0xb6ff, 0xc08d, 0x21, 0 - .dw 0xb740, 0xc08d, 0xb77f, 0xc08d, 0x21, 0 - .dw 0xb7c0, 0xc08d, 0xb7ff, 0xc08d, 0x21, 0 - .dw 0xb840, 0xc08d, 0xb87f, 0xc08d, 0x21, 0 - .dw 0xb8c0, 0xc08d, 0xb8ff, 0xc08d, 0x21, 0 - .dw 0xb940, 0xc08d, 0xb97f, 0xc08d, 0x21, 0 - .dw 0xb9c0, 0xc08d, 0xbfff, 0xc08d, 0x21, 0 - .dw 0xc040, 0xc08d, 0xc07f, 0xc08d, 0x21, 0 - .dw 0xc0c0, 0xc08d, 0xc0ff, 0xc08d, 0x21, 0 - .dw 0xc140, 0xc08d, 0xc17f, 0xc08d, 0x21, 0 - .dw 0xc1c0, 0xc08d, 0xc1ff, 0xc08d, 0x21, 0 - .dw 0xc240, 0xc08d, 0xc27f, 0xc08d, 0x21, 0 - .dw 0xc2c0, 0xc08d, 0xc2ff, 0xc08d, 0x21, 0 - .dw 0xc340, 0xc08d, 0xc37f, 0xc08d, 0x21, 0 - .dw 0xc3c0, 0xc08d, 0xc3ff, 0xc08d, 0x21, 0 - .dw 0xc440, 0xc08d, 0xc47f, 0xc08d, 0x21, 0 - .dw 0xc4c0, 0xc08d, 0xc4ff, 0xc08d, 0x21, 0 - .dw 0xc540, 0xc08d, 0xc57f, 0xc08d, 0x21, 0 - .dw 0xc5c0, 0xc08d, 0xc5ff, 0xc08d, 0x21, 0 - .dw 0xc640, 0xc08d, 0xc67f, 0xc08d, 0x21, 0 - .dw 0xc6c0, 0xc08d, 0xc6ff, 0xc08d, 0x21, 0 - .dw 0xc740, 0xc08d, 0xc77f, 0xc08d, 0x21, 0 - .dw 0xc7c0, 0xc08d, 0xc7ff, 0xc08d, 0x21, 0 - .dw 0xc840, 0xc08d, 0xc87f, 0xc08d, 0x21, 0 - .dw 0xc8c0, 0xc08d, 0xc8ff, 0xc08d, 0x21, 0 - .dw 0xc940, 0xc08d, 0xc97f, 0xc08d, 0x21, 0 - .dw 0xc9c0, 0xc08d, 0xc9ff, 0xc08d, 0x21, 0 - .dw 0xca40, 0xc08d, 0xca7f, 0xc08d, 0x21, 0 - .dw 0xcac0, 0xc08d, 0xcaff, 0xc08d, 0x21, 0 - .dw 0xcb40, 0xc08d, 0xcb7f, 0xc08d, 0x21, 0 - .dw 0xcbc0, 0xc08d, 0xcbff, 0xc08d, 0x21, 0 - .dw 0xcc40, 0xc08d, 0xcc7f, 0xc08d, 0x21, 0 - .dw 0xccc0, 0xc08d, 0xccff, 0xc08d, 0x21, 0 - .dw 0xcd40, 0xc08d, 0xcd7f, 0xc08d, 0x21, 0 - .dw 0xcdc0, 0xc08d, 0xcdff, 0xc08d, 0x21, 0 - .dw 0xce40, 0xc08d, 0xce7f, 0xc08d, 0x21, 0 - .dw 0xcec0, 0xc08d, 0xceff, 0xc08d, 0x21, 0 - .dw 0xcf40, 0xc08d, 0xcf7f, 0xc08d, 0x21, 0 - .dw 0xcfc0, 0xc08d, 0xcfff, 0xc08d, 0x21, 0 - .dw 0xd040, 0xc08d, 0xd07f, 0xc08d, 0x21, 0 - .dw 0xd0c0, 0xc08d, 0xd0ff, 0xc08d, 0x21, 0 - .dw 0xd140, 0xc08d, 0xd17f, 0xc08d, 0x21, 0 - .dw 0xd1c0, 0xc08d, 0xd1ff, 0xc08d, 0x21, 0 - .dw 0xd240, 0xc08d, 0xd27f, 0xc08d, 0x21, 0 - .dw 0xd2c0, 0xc08d, 0xd2ff, 0xc08d, 0x21, 0 - .dw 0xd340, 0xc08d, 0xd37f, 0xc08d, 0x21, 0 - .dw 0xd3c0, 0xc08d, 0xd3ff, 0xc08d, 0x21, 0 - .dw 0xd440, 0xc08d, 0xd47f, 0xc08d, 0x21, 0 - .dw 0xd4c0, 0xc08d, 0xd4ff, 0xc08d, 0x21, 0 - .dw 0xd540, 0xc08d, 0xd57f, 0xc08d, 0x21, 0 - .dw 0xd5c0, 0xc08d, 0xd5ff, 0xc08d, 0x21, 0 - .dw 0xd640, 0xc08d, 0xd67f, 0xc08d, 0x21, 0 - .dw 0xd6c0, 0xc08d, 0xd6ff, 0xc08d, 0x21, 0 - .dw 0xd740, 0xc08d, 0xd77f, 0xc08d, 0x21, 0 - .dw 0xd7c0, 0xc08d, 0xd7ff, 0xc08d, 0x21, 0 - .dw 0xd840, 0xc08d, 0xd87f, 0xc08d, 0x21, 0 - .dw 0xd8c0, 0xc08d, 0xd8ff, 0xc08d, 0x21, 0 - .dw 0xd940, 0xc08d, 0xd97f, 0xc08d, 0x21, 0 - .dw 0xd9c0, 0xc08d, 0xdfff, 0xc08d, 0x21, 0 - .dw 0xe040, 0xc08d, 0xe07f, 0xc08d, 0x21, 0 - .dw 0xe0c0, 0xc08d, 0xe0ff, 0xc08d, 0x21, 0 - .dw 0xe140, 0xc08d, 0xe17f, 0xc08d, 0x21, 0 - .dw 0xe1c0, 0xc08d, 0xe1ff, 0xc08d, 0x21, 0 - .dw 0xe240, 0xc08d, 0xe27f, 0xc08d, 0x21, 0 - .dw 0xe2c0, 0xc08d, 0xe2ff, 0xc08d, 0x21, 0 - .dw 0xe340, 0xc08d, 0xe37f, 0xc08d, 0x21, 0 - .dw 0xe3c0, 0xc08d, 0xe3ff, 0xc08d, 0x21, 0 - .dw 0xe440, 0xc08d, 0xe47f, 0xc08d, 0x21, 0 - .dw 0xe4c0, 0xc08d, 0xe4ff, 0xc08d, 0x21, 0 - .dw 0xe540, 0xc08d, 0xe57f, 0xc08d, 0x21, 0 - .dw 0xe5c0, 0xc08d, 0xe5ff, 0xc08d, 0x21, 0 - .dw 0xe640, 0xc08d, 0xe67f, 0xc08d, 0x21, 0 - .dw 0xe6c0, 0xc08d, 0xe6ff, 0xc08d, 0x21, 0 - .dw 0xe740, 0xc08d, 0xe77f, 0xc08d, 0x21, 0 - .dw 0xe7c0, 0xc08d, 0xe7ff, 0xc08d, 0x21, 0 - .dw 0xe840, 0xc08d, 0xe87f, 0xc08d, 0x21, 0 - .dw 0xe8c0, 0xc08d, 0xe8ff, 0xc08d, 0x21, 0 - .dw 0xe940, 0xc08d, 0xe97f, 0xc08d, 0x21, 0 - .dw 0xe9c0, 0xc08d, 0xe9ff, 0xc08d, 0x21, 0 - .dw 0xea40, 0xc08d, 0xea7f, 0xc08d, 0x21, 0 - .dw 0xeac0, 0xc08d, 0xeaff, 0xc08d, 0x21, 0 - .dw 0xeb40, 0xc08d, 0xeb7f, 0xc08d, 0x21, 0 - .dw 0xebc0, 0xc08d, 0xebff, 0xc08d, 0x21, 0 - .dw 0xec40, 0xc08d, 0xec7f, 0xc08d, 0x21, 0 - .dw 0xecc0, 0xc08d, 0xecff, 0xc08d, 0x21, 0 - .dw 0xed40, 0xc08d, 0xed7f, 0xc08d, 0x21, 0 - .dw 0xedc0, 0xc08d, 0xedff, 0xc08d, 0x21, 0 - .dw 0xee40, 0xc08d, 0xee7f, 0xc08d, 0x21, 0 - .dw 0xeec0, 0xc08d, 0xeeff, 0xc08d, 0x21, 0 - .dw 0xef40, 0xc08d, 0xef7f, 0xc08d, 0x21, 0 - .dw 0xefc0, 0xc08d, 0xefff, 0xc08d, 0x21, 0 - .dw 0xf040, 0xc08d, 0xf07f, 0xc08d, 0x21, 0 - .dw 0xf0c0, 0xc08d, 0xf0ff, 0xc08d, 0x21, 0 - .dw 0xf140, 0xc08d, 0xf17f, 0xc08d, 0x21, 0 - .dw 0xf1c0, 0xc08d, 0xf1ff, 0xc08d, 0x21, 0 - .dw 0xf240, 0xc08d, 0xf27f, 0xc08d, 0x21, 0 - .dw 0xf2c0, 0xc08d, 0xf2ff, 0xc08d, 0x21, 0 - .dw 0xf340, 0xc08d, 0xf37f, 0xc08d, 0x21, 0 - .dw 0xf3c0, 0xc08d, 0xf3ff, 0xc08d, 0x21, 0 - .dw 0xf440, 0xc08d, 0xf47f, 0xc08d, 0x21, 0 - .dw 0xf4c0, 0xc08d, 0xf4ff, 0xc08d, 0x21, 0 - .dw 0xf540, 0xc08d, 0xf57f, 0xc08d, 0x21, 0 - .dw 0xf5c0, 0xc08d, 0xf5ff, 0xc08d, 0x21, 0 - .dw 0xf640, 0xc08d, 0xf67f, 0xc08d, 0x21, 0 - .dw 0xf6c0, 0xc08d, 0xf6ff, 0xc08d, 0x21, 0 - .dw 0xf740, 0xc08d, 0xf77f, 0xc08d, 0x21, 0 - .dw 0xf7c0, 0xc08d, 0xf7ff, 0xc08d, 0x21, 0 - .dw 0xf840, 0xc08d, 0xf87f, 0xc08d, 0x21, 0 - .dw 0xf8c0, 0xc08d, 0xf8ff, 0xc08d, 0x21, 0 - .dw 0xf940, 0xc08d, 0xf97f, 0xc08d, 0x21, 0 - .dw 0xf9c0, 0xc08d, 0xffff, 0xc08d, 0x21, 0 - .dw 0x0040, 0xc08e, 0x007f, 0xc08e, 0x21, 0 - .dw 0x00c0, 0xc08e, 0x00ff, 0xc08e, 0x21, 0 - .dw 0x0140, 0xc08e, 0x017f, 0xc08e, 0x21, 0 - .dw 0x01c0, 0xc08e, 0x01ff, 0xc08e, 0x21, 0 - .dw 0x0240, 0xc08e, 0x027f, 0xc08e, 0x21, 0 - .dw 0x02c0, 0xc08e, 0x02ff, 0xc08e, 0x21, 0 - .dw 0x0340, 0xc08e, 0x037f, 0xc08e, 0x21, 0 - .dw 0x03c0, 0xc08e, 0x03ff, 0xc08e, 0x21, 0 - .dw 0x0440, 0xc08e, 0x047f, 0xc08e, 0x21, 0 - .dw 0x04c0, 0xc08e, 0x04ff, 0xc08e, 0x21, 0 - .dw 0x0540, 0xc08e, 0x057f, 0xc08e, 0x21, 0 - .dw 0x05c0, 0xc08e, 0x05ff, 0xc08e, 0x21, 0 - .dw 0x0640, 0xc08e, 0x067f, 0xc08e, 0x21, 0 - .dw 0x06c0, 0xc08e, 0x06ff, 0xc08e, 0x21, 0 - .dw 0x0740, 0xc08e, 0x077f, 0xc08e, 0x21, 0 - .dw 0x07c0, 0xc08e, 0x07ff, 0xc08e, 0x21, 0 - .dw 0x0840, 0xc08e, 0x087f, 0xc08e, 0x21, 0 - .dw 0x08c0, 0xc08e, 0x08ff, 0xc08e, 0x21, 0 - .dw 0x0940, 0xc08e, 0x097f, 0xc08e, 0x21, 0 - .dw 0x09c0, 0xc08e, 0x09ff, 0xc08e, 0x21, 0 - .dw 0x0a40, 0xc08e, 0x0a7f, 0xc08e, 0x21, 0 - .dw 0x0ac0, 0xc08e, 0x0aff, 0xc08e, 0x21, 0 - .dw 0x0b40, 0xc08e, 0x0b7f, 0xc08e, 0x21, 0 - .dw 0x0bc0, 0xc08e, 0x0bff, 0xc08e, 0x21, 0 - .dw 0x0c40, 0xc08e, 0x0c7f, 0xc08e, 0x21, 0 - .dw 0x0cc0, 0xc08e, 0x0cff, 0xc08e, 0x21, 0 - .dw 0x0d40, 0xc08e, 0x0d7f, 0xc08e, 0x21, 0 - .dw 0x0dc0, 0xc08e, 0x0dff, 0xc08e, 0x21, 0 - .dw 0x0e40, 0xc08e, 0x0e7f, 0xc08e, 0x21, 0 - .dw 0x0ec0, 0xc08e, 0x0eff, 0xc08e, 0x21, 0 - .dw 0x0f40, 0xc08e, 0x0f7f, 0xc08e, 0x21, 0 - .dw 0x0fc0, 0xc08e, 0x0fff, 0xc08e, 0x21, 0 - .dw 0x1040, 0xc08e, 0x107f, 0xc08e, 0x21, 0 - .dw 0x10c0, 0xc08e, 0x10ff, 0xc08e, 0x21, 0 - .dw 0x1140, 0xc08e, 0x117f, 0xc08e, 0x21, 0 - .dw 0x11c0, 0xc08e, 0x11ff, 0xc08e, 0x21, 0 - .dw 0x1240, 0xc08e, 0x127f, 0xc08e, 0x21, 0 - .dw 0x12c0, 0xc08e, 0x12ff, 0xc08e, 0x21, 0 - .dw 0x1340, 0xc08e, 0x137f, 0xc08e, 0x21, 0 - .dw 0x13c0, 0xc08e, 0x13ff, 0xc08e, 0x21, 0 - .dw 0x1440, 0xc08e, 0x147f, 0xc08e, 0x21, 0 - .dw 0x14c0, 0xc08e, 0x14ff, 0xc08e, 0x21, 0 - .dw 0x1540, 0xc08e, 0x157f, 0xc08e, 0x21, 0 - .dw 0x15c0, 0xc08e, 0x15ff, 0xc08e, 0x21, 0 - .dw 0x1640, 0xc08e, 0x167f, 0xc08e, 0x21, 0 - .dw 0x16c0, 0xc08e, 0x16ff, 0xc08e, 0x21, 0 - .dw 0x1740, 0xc08e, 0x177f, 0xc08e, 0x21, 0 - .dw 0x17c0, 0xc08e, 0x17ff, 0xc08e, 0x21, 0 - .dw 0x1840, 0xc08e, 0x187f, 0xc08e, 0x21, 0 - .dw 0x18c0, 0xc08e, 0x18ff, 0xc08e, 0x21, 0 - .dw 0x1940, 0xc08e, 0x197f, 0xc08e, 0x21, 0 - .dw 0x19c0, 0xc08e, 0x1fff, 0xc08e, 0x21, 0 - .dw 0x2040, 0xc08e, 0x207f, 0xc08e, 0x21, 0 - .dw 0x20c0, 0xc08e, 0x20ff, 0xc08e, 0x21, 0 - .dw 0x2140, 0xc08e, 0x217f, 0xc08e, 0x21, 0 - .dw 0x21c0, 0xc08e, 0x21ff, 0xc08e, 0x21, 0 - .dw 0x2240, 0xc08e, 0x227f, 0xc08e, 0x21, 0 - .dw 0x22c0, 0xc08e, 0x22ff, 0xc08e, 0x21, 0 - .dw 0x2340, 0xc08e, 0x237f, 0xc08e, 0x21, 0 - .dw 0x23c0, 0xc08e, 0x23ff, 0xc08e, 0x21, 0 - .dw 0x2440, 0xc08e, 0x247f, 0xc08e, 0x21, 0 - .dw 0x24c0, 0xc08e, 0x24ff, 0xc08e, 0x21, 0 - .dw 0x2540, 0xc08e, 0x257f, 0xc08e, 0x21, 0 - .dw 0x25c0, 0xc08e, 0x25ff, 0xc08e, 0x21, 0 - .dw 0x2640, 0xc08e, 0x267f, 0xc08e, 0x21, 0 - .dw 0x26c0, 0xc08e, 0x26ff, 0xc08e, 0x21, 0 - .dw 0x2740, 0xc08e, 0x277f, 0xc08e, 0x21, 0 - .dw 0x27c0, 0xc08e, 0x27ff, 0xc08e, 0x21, 0 - .dw 0x2840, 0xc08e, 0x287f, 0xc08e, 0x21, 0 - .dw 0x28c0, 0xc08e, 0x28ff, 0xc08e, 0x21, 0 - .dw 0x2940, 0xc08e, 0x297f, 0xc08e, 0x21, 0 - .dw 0x29c0, 0xc08e, 0x29ff, 0xc08e, 0x21, 0 - .dw 0x2a40, 0xc08e, 0x2a7f, 0xc08e, 0x21, 0 - .dw 0x2ac0, 0xc08e, 0x2aff, 0xc08e, 0x21, 0 - .dw 0x2b40, 0xc08e, 0x2b7f, 0xc08e, 0x21, 0 - .dw 0x2bc0, 0xc08e, 0x2bff, 0xc08e, 0x21, 0 - .dw 0x2c40, 0xc08e, 0x2c7f, 0xc08e, 0x21, 0 - .dw 0x2cc0, 0xc08e, 0x2cff, 0xc08e, 0x21, 0 - .dw 0x2d40, 0xc08e, 0x2d7f, 0xc08e, 0x21, 0 - .dw 0x2dc0, 0xc08e, 0x2dff, 0xc08e, 0x21, 0 - .dw 0x2e40, 0xc08e, 0x2e7f, 0xc08e, 0x21, 0 - .dw 0x2ec0, 0xc08e, 0x2eff, 0xc08e, 0x21, 0 - .dw 0x2f40, 0xc08e, 0x2f7f, 0xc08e, 0x21, 0 - .dw 0x2fc0, 0xc08e, 0x2fff, 0xc08e, 0x21, 0 - .dw 0x3040, 0xc08e, 0x307f, 0xc08e, 0x21, 0 - .dw 0x30c0, 0xc08e, 0x30ff, 0xc08e, 0x21, 0 - .dw 0x3140, 0xc08e, 0x317f, 0xc08e, 0x21, 0 - .dw 0x31c0, 0xc08e, 0x31ff, 0xc08e, 0x21, 0 - .dw 0x3240, 0xc08e, 0x327f, 0xc08e, 0x21, 0 - .dw 0x32c0, 0xc08e, 0x32ff, 0xc08e, 0x21, 0 - .dw 0x3340, 0xc08e, 0x337f, 0xc08e, 0x21, 0 - .dw 0x33c0, 0xc08e, 0x33ff, 0xc08e, 0x21, 0 - .dw 0x3440, 0xc08e, 0x347f, 0xc08e, 0x21, 0 - .dw 0x34c0, 0xc08e, 0x34ff, 0xc08e, 0x21, 0 - .dw 0x3540, 0xc08e, 0x357f, 0xc08e, 0x21, 0 - .dw 0x35c0, 0xc08e, 0x35ff, 0xc08e, 0x21, 0 - .dw 0x3640, 0xc08e, 0x367f, 0xc08e, 0x21, 0 - .dw 0x36c0, 0xc08e, 0x36ff, 0xc08e, 0x21, 0 - .dw 0x3740, 0xc08e, 0x377f, 0xc08e, 0x21, 0 - .dw 0x37c0, 0xc08e, 0x37ff, 0xc08e, 0x21, 0 - .dw 0x3840, 0xc08e, 0x387f, 0xc08e, 0x21, 0 - .dw 0x38c0, 0xc08e, 0x38ff, 0xc08e, 0x21, 0 - .dw 0x3940, 0xc08e, 0x397f, 0xc08e, 0x21, 0 - .dw 0x39c0, 0xc08e, 0x3fff, 0xc08e, 0x21, 0 - .dw 0x4040, 0xc08e, 0x407f, 0xc08e, 0x21, 0 - .dw 0x40c0, 0xc08e, 0x40ff, 0xc08e, 0x21, 0 - .dw 0x4140, 0xc08e, 0x417f, 0xc08e, 0x21, 0 - .dw 0x41c0, 0xc08e, 0x41ff, 0xc08e, 0x21, 0 - .dw 0x4240, 0xc08e, 0x427f, 0xc08e, 0x21, 0 - .dw 0x42c0, 0xc08e, 0x42ff, 0xc08e, 0x21, 0 - .dw 0x4340, 0xc08e, 0x437f, 0xc08e, 0x21, 0 - .dw 0x43c0, 0xc08e, 0x43ff, 0xc08e, 0x21, 0 - .dw 0x4440, 0xc08e, 0x447f, 0xc08e, 0x21, 0 - .dw 0x44c0, 0xc08e, 0x44ff, 0xc08e, 0x21, 0 - .dw 0x4540, 0xc08e, 0x457f, 0xc08e, 0x21, 0 - .dw 0x45c0, 0xc08e, 0x45ff, 0xc08e, 0x21, 0 - .dw 0x4640, 0xc08e, 0x467f, 0xc08e, 0x21, 0 - .dw 0x46c0, 0xc08e, 0x46ff, 0xc08e, 0x21, 0 - .dw 0x4740, 0xc08e, 0x477f, 0xc08e, 0x21, 0 - .dw 0x47c0, 0xc08e, 0x47ff, 0xc08e, 0x21, 0 - .dw 0x4840, 0xc08e, 0x487f, 0xc08e, 0x21, 0 - .dw 0x48c0, 0xc08e, 0x48ff, 0xc08e, 0x21, 0 - .dw 0x4940, 0xc08e, 0x497f, 0xc08e, 0x21, 0 - .dw 0x49c0, 0xc08e, 0x49ff, 0xc08e, 0x21, 0 - .dw 0x4a40, 0xc08e, 0x4a7f, 0xc08e, 0x21, 0 - .dw 0x4ac0, 0xc08e, 0x4aff, 0xc08e, 0x21, 0 - .dw 0x4b40, 0xc08e, 0x4b7f, 0xc08e, 0x21, 0 - .dw 0x4bc0, 0xc08e, 0x4bff, 0xc08e, 0x21, 0 - .dw 0x4c40, 0xc08e, 0x4c7f, 0xc08e, 0x21, 0 - .dw 0x4cc0, 0xc08e, 0x4cff, 0xc08e, 0x21, 0 - .dw 0x4d40, 0xc08e, 0x4d7f, 0xc08e, 0x21, 0 - .dw 0x4dc0, 0xc08e, 0x4dff, 0xc08e, 0x21, 0 - .dw 0x4e40, 0xc08e, 0x4e7f, 0xc08e, 0x21, 0 - .dw 0x4ec0, 0xc08e, 0x4eff, 0xc08e, 0x21, 0 - .dw 0x4f40, 0xc08e, 0x4f7f, 0xc08e, 0x21, 0 - .dw 0x4fc0, 0xc08e, 0x4fff, 0xc08e, 0x21, 0 - .dw 0x5040, 0xc08e, 0x507f, 0xc08e, 0x21, 0 - .dw 0x50c0, 0xc08e, 0x50ff, 0xc08e, 0x21, 0 - .dw 0x5140, 0xc08e, 0x517f, 0xc08e, 0x21, 0 - .dw 0x51c0, 0xc08e, 0x51ff, 0xc08e, 0x21, 0 - .dw 0x5240, 0xc08e, 0x527f, 0xc08e, 0x21, 0 - .dw 0x52c0, 0xc08e, 0x52ff, 0xc08e, 0x21, 0 - .dw 0x5340, 0xc08e, 0x537f, 0xc08e, 0x21, 0 - .dw 0x53c0, 0xc08e, 0x53ff, 0xc08e, 0x21, 0 - .dw 0x5440, 0xc08e, 0x547f, 0xc08e, 0x21, 0 - .dw 0x54c0, 0xc08e, 0x54ff, 0xc08e, 0x21, 0 - .dw 0x5540, 0xc08e, 0x557f, 0xc08e, 0x21, 0 - .dw 0x55c0, 0xc08e, 0x55ff, 0xc08e, 0x21, 0 - .dw 0x5640, 0xc08e, 0x567f, 0xc08e, 0x21, 0 - .dw 0x56c0, 0xc08e, 0x56ff, 0xc08e, 0x21, 0 - .dw 0x5740, 0xc08e, 0x577f, 0xc08e, 0x21, 0 - .dw 0x57c0, 0xc08e, 0x57ff, 0xc08e, 0x21, 0 - .dw 0x5840, 0xc08e, 0x587f, 0xc08e, 0x21, 0 - .dw 0x58c0, 0xc08e, 0x58ff, 0xc08e, 0x21, 0 - .dw 0x5940, 0xc08e, 0x597f, 0xc08e, 0x21, 0 - .dw 0x59c0, 0xc08e, 0x5fff, 0xc08e, 0x21, 0 - .dw 0x6040, 0xc08e, 0x607f, 0xc08e, 0x21, 0 - .dw 0x60c0, 0xc08e, 0x60ff, 0xc08e, 0x21, 0 - .dw 0x6140, 0xc08e, 0x617f, 0xc08e, 0x21, 0 - .dw 0x61c0, 0xc08e, 0x61ff, 0xc08e, 0x21, 0 - .dw 0x6240, 0xc08e, 0x627f, 0xc08e, 0x21, 0 - .dw 0x62c0, 0xc08e, 0x62ff, 0xc08e, 0x21, 0 - .dw 0x6340, 0xc08e, 0x637f, 0xc08e, 0x21, 0 - .dw 0x63c0, 0xc08e, 0x63ff, 0xc08e, 0x21, 0 - .dw 0x6440, 0xc08e, 0x647f, 0xc08e, 0x21, 0 - .dw 0x64c0, 0xc08e, 0x64ff, 0xc08e, 0x21, 0 - .dw 0x6540, 0xc08e, 0x657f, 0xc08e, 0x21, 0 - .dw 0x65c0, 0xc08e, 0x65ff, 0xc08e, 0x21, 0 - .dw 0x6640, 0xc08e, 0x667f, 0xc08e, 0x21, 0 - .dw 0x66c0, 0xc08e, 0x66ff, 0xc08e, 0x21, 0 - .dw 0x6740, 0xc08e, 0x677f, 0xc08e, 0x21, 0 - .dw 0x67c0, 0xc08e, 0x67ff, 0xc08e, 0x21, 0 - .dw 0x6840, 0xc08e, 0x687f, 0xc08e, 0x21, 0 - .dw 0x68c0, 0xc08e, 0x68ff, 0xc08e, 0x21, 0 - .dw 0x6940, 0xc08e, 0x697f, 0xc08e, 0x21, 0 - .dw 0x69c0, 0xc08e, 0x69ff, 0xc08e, 0x21, 0 - .dw 0x6a40, 0xc08e, 0x6a7f, 0xc08e, 0x21, 0 - .dw 0x6ac0, 0xc08e, 0x6aff, 0xc08e, 0x21, 0 - .dw 0x6b40, 0xc08e, 0x6b7f, 0xc08e, 0x21, 0 - .dw 0x6bc0, 0xc08e, 0x6bff, 0xc08e, 0x21, 0 - .dw 0x6c40, 0xc08e, 0x6c7f, 0xc08e, 0x21, 0 - .dw 0x6cc0, 0xc08e, 0x6cff, 0xc08e, 0x21, 0 - .dw 0x6d40, 0xc08e, 0x6d7f, 0xc08e, 0x21, 0 - .dw 0x6dc0, 0xc08e, 0x6dff, 0xc08e, 0x21, 0 - .dw 0x6e40, 0xc08e, 0x6e7f, 0xc08e, 0x21, 0 - .dw 0x6ec0, 0xc08e, 0x6eff, 0xc08e, 0x21, 0 - .dw 0x6f40, 0xc08e, 0x6f7f, 0xc08e, 0x21, 0 - .dw 0x6fc0, 0xc08e, 0x6fff, 0xc08e, 0x21, 0 - .dw 0x7040, 0xc08e, 0x707f, 0xc08e, 0x21, 0 - .dw 0x70c0, 0xc08e, 0x70ff, 0xc08e, 0x21, 0 - .dw 0x7140, 0xc08e, 0x717f, 0xc08e, 0x21, 0 - .dw 0x71c0, 0xc08e, 0x71ff, 0xc08e, 0x21, 0 - .dw 0x7240, 0xc08e, 0x727f, 0xc08e, 0x21, 0 - .dw 0x72c0, 0xc08e, 0x72ff, 0xc08e, 0x21, 0 - .dw 0x7340, 0xc08e, 0x737f, 0xc08e, 0x21, 0 - .dw 0x73c0, 0xc08e, 0x73ff, 0xc08e, 0x21, 0 - .dw 0x7440, 0xc08e, 0x747f, 0xc08e, 0x21, 0 - .dw 0x74c0, 0xc08e, 0x74ff, 0xc08e, 0x21, 0 - .dw 0x7540, 0xc08e, 0x757f, 0xc08e, 0x21, 0 - .dw 0x75c0, 0xc08e, 0x75ff, 0xc08e, 0x21, 0 - .dw 0x7640, 0xc08e, 0x767f, 0xc08e, 0x21, 0 - .dw 0x76c0, 0xc08e, 0x76ff, 0xc08e, 0x21, 0 - .dw 0x7740, 0xc08e, 0x777f, 0xc08e, 0x21, 0 - .dw 0x77c0, 0xc08e, 0x77ff, 0xc08e, 0x21, 0 - .dw 0x7840, 0xc08e, 0x787f, 0xc08e, 0x21, 0 - .dw 0x78c0, 0xc08e, 0x78ff, 0xc08e, 0x21, 0 - .dw 0x7940, 0xc08e, 0x797f, 0xc08e, 0x21, 0 - .dw 0x79c0, 0xc08e, 0x7fff, 0xc08e, 0x21, 0 - .dw 0x8040, 0xc08e, 0x807f, 0xc08e, 0x21, 0 - .dw 0x80c0, 0xc08e, 0x80ff, 0xc08e, 0x21, 0 - .dw 0x8140, 0xc08e, 0x817f, 0xc08e, 0x21, 0 - .dw 0x81c0, 0xc08e, 0x81ff, 0xc08e, 0x21, 0 - .dw 0x8240, 0xc08e, 0x827f, 0xc08e, 0x21, 0 - .dw 0x82c0, 0xc08e, 0x82ff, 0xc08e, 0x21, 0 - .dw 0x8340, 0xc08e, 0x837f, 0xc08e, 0x21, 0 - .dw 0x83c0, 0xc08e, 0x83ff, 0xc08e, 0x21, 0 - .dw 0x8440, 0xc08e, 0x847f, 0xc08e, 0x21, 0 - .dw 0x84c0, 0xc08e, 0x84ff, 0xc08e, 0x21, 0 - .dw 0x8540, 0xc08e, 0x857f, 0xc08e, 0x21, 0 - .dw 0x85c0, 0xc08e, 0x85ff, 0xc08e, 0x21, 0 - .dw 0x8640, 0xc08e, 0x867f, 0xc08e, 0x21, 0 - .dw 0x86c0, 0xc08e, 0x86ff, 0xc08e, 0x21, 0 - .dw 0x8740, 0xc08e, 0x877f, 0xc08e, 0x21, 0 - .dw 0x87c0, 0xc08e, 0x87ff, 0xc08e, 0x21, 0 - .dw 0x8840, 0xc08e, 0x887f, 0xc08e, 0x21, 0 - .dw 0x88c0, 0xc08e, 0x88ff, 0xc08e, 0x21, 0 - .dw 0x8940, 0xc08e, 0x897f, 0xc08e, 0x21, 0 - .dw 0x89c0, 0xc08e, 0x89ff, 0xc08e, 0x21, 0 - .dw 0x8a40, 0xc08e, 0x8a7f, 0xc08e, 0x21, 0 - .dw 0x8ac0, 0xc08e, 0x8aff, 0xc08e, 0x21, 0 - .dw 0x8b40, 0xc08e, 0x8b7f, 0xc08e, 0x21, 0 - .dw 0x8bc0, 0xc08e, 0x8bff, 0xc08e, 0x21, 0 - .dw 0x8c40, 0xc08e, 0x8c7f, 0xc08e, 0x21, 0 - .dw 0x8cc0, 0xc08e, 0x8cff, 0xc08e, 0x21, 0 - .dw 0x8d40, 0xc08e, 0x8d7f, 0xc08e, 0x21, 0 - .dw 0x8dc0, 0xc08e, 0x8dff, 0xc08e, 0x21, 0 - .dw 0x8e40, 0xc08e, 0x8e7f, 0xc08e, 0x21, 0 - .dw 0x8ec0, 0xc08e, 0x8eff, 0xc08e, 0x21, 0 - .dw 0x8f40, 0xc08e, 0x8f7f, 0xc08e, 0x21, 0 - .dw 0x8fc0, 0xc08e, 0x8fff, 0xc08e, 0x21, 0 - .dw 0x9040, 0xc08e, 0x907f, 0xc08e, 0x21, 0 - .dw 0x90c0, 0xc08e, 0x90ff, 0xc08e, 0x21, 0 - .dw 0x9140, 0xc08e, 0x917f, 0xc08e, 0x21, 0 - .dw 0x91c0, 0xc08e, 0x91ff, 0xc08e, 0x21, 0 - .dw 0x9240, 0xc08e, 0x927f, 0xc08e, 0x21, 0 - .dw 0x92c0, 0xc08e, 0x92ff, 0xc08e, 0x21, 0 - .dw 0x9340, 0xc08e, 0x937f, 0xc08e, 0x21, 0 - .dw 0x93c0, 0xc08e, 0x93ff, 0xc08e, 0x21, 0 - .dw 0x9440, 0xc08e, 0x947f, 0xc08e, 0x21, 0 - .dw 0x94c0, 0xc08e, 0x94ff, 0xc08e, 0x21, 0 - .dw 0x9540, 0xc08e, 0x957f, 0xc08e, 0x21, 0 - .dw 0x95c0, 0xc08e, 0x95ff, 0xc08e, 0x21, 0 - .dw 0x9640, 0xc08e, 0x967f, 0xc08e, 0x21, 0 - .dw 0x96c0, 0xc08e, 0x96ff, 0xc08e, 0x21, 0 - .dw 0x9740, 0xc08e, 0x977f, 0xc08e, 0x21, 0 - .dw 0x97c0, 0xc08e, 0x97ff, 0xc08e, 0x21, 0 - .dw 0x9840, 0xc08e, 0x987f, 0xc08e, 0x21, 0 - .dw 0x98c0, 0xc08e, 0x98ff, 0xc08e, 0x21, 0 - .dw 0x9940, 0xc08e, 0x997f, 0xc08e, 0x21, 0 - .dw 0x99c0, 0xc08e, 0x9fff, 0xc08e, 0x21, 0 - .dw 0xa040, 0xc08e, 0xa07f, 0xc08e, 0x21, 0 - .dw 0xa0c0, 0xc08e, 0xa0ff, 0xc08e, 0x21, 0 - .dw 0xa140, 0xc08e, 0xa17f, 0xc08e, 0x21, 0 - .dw 0xa1c0, 0xc08e, 0xa1ff, 0xc08e, 0x21, 0 - .dw 0xa240, 0xc08e, 0xa27f, 0xc08e, 0x21, 0 - .dw 0xa2c0, 0xc08e, 0xa2ff, 0xc08e, 0x21, 0 - .dw 0xa340, 0xc08e, 0xa37f, 0xc08e, 0x21, 0 - .dw 0xa3c0, 0xc08e, 0xa3ff, 0xc08e, 0x21, 0 - .dw 0xa440, 0xc08e, 0xa47f, 0xc08e, 0x21, 0 - .dw 0xa4c0, 0xc08e, 0xa4ff, 0xc08e, 0x21, 0 - .dw 0xa540, 0xc08e, 0xa57f, 0xc08e, 0x21, 0 - .dw 0xa5c0, 0xc08e, 0xa5ff, 0xc08e, 0x21, 0 - .dw 0xa640, 0xc08e, 0xa67f, 0xc08e, 0x21, 0 - .dw 0xa6c0, 0xc08e, 0xa6ff, 0xc08e, 0x21, 0 - .dw 0xa740, 0xc08e, 0xa77f, 0xc08e, 0x21, 0 - .dw 0xa7c0, 0xc08e, 0xa7ff, 0xc08e, 0x21, 0 - .dw 0xa840, 0xc08e, 0xa87f, 0xc08e, 0x21, 0 - .dw 0xa8c0, 0xc08e, 0xa8ff, 0xc08e, 0x21, 0 - .dw 0xa940, 0xc08e, 0xa97f, 0xc08e, 0x21, 0 - .dw 0xa9c0, 0xc08e, 0xa9ff, 0xc08e, 0x21, 0 - .dw 0xaa40, 0xc08e, 0xaa7f, 0xc08e, 0x21, 0 - .dw 0xaac0, 0xc08e, 0xaaff, 0xc08e, 0x21, 0 - .dw 0xab40, 0xc08e, 0xab7f, 0xc08e, 0x21, 0 - .dw 0xabc0, 0xc08e, 0xabff, 0xc08e, 0x21, 0 - .dw 0xac40, 0xc08e, 0xac7f, 0xc08e, 0x21, 0 - .dw 0xacc0, 0xc08e, 0xacff, 0xc08e, 0x21, 0 - .dw 0xad40, 0xc08e, 0xad7f, 0xc08e, 0x21, 0 - .dw 0xadc0, 0xc08e, 0xadff, 0xc08e, 0x21, 0 - .dw 0xae40, 0xc08e, 0xae7f, 0xc08e, 0x21, 0 - .dw 0xaec0, 0xc08e, 0xaeff, 0xc08e, 0x21, 0 - .dw 0xaf40, 0xc08e, 0xaf7f, 0xc08e, 0x21, 0 - .dw 0xafc0, 0xc08e, 0xafff, 0xc08e, 0x21, 0 - .dw 0xb040, 0xc08e, 0xb07f, 0xc08e, 0x21, 0 - .dw 0xb0c0, 0xc08e, 0xb0ff, 0xc08e, 0x21, 0 - .dw 0xb140, 0xc08e, 0xb17f, 0xc08e, 0x21, 0 - .dw 0xb1c0, 0xc08e, 0xb1ff, 0xc08e, 0x21, 0 - .dw 0xb240, 0xc08e, 0xb27f, 0xc08e, 0x21, 0 - .dw 0xb2c0, 0xc08e, 0xb2ff, 0xc08e, 0x21, 0 - .dw 0xb340, 0xc08e, 0xb37f, 0xc08e, 0x21, 0 - .dw 0xb3c0, 0xc08e, 0xb3ff, 0xc08e, 0x21, 0 - .dw 0xb440, 0xc08e, 0xb47f, 0xc08e, 0x21, 0 - .dw 0xb4c0, 0xc08e, 0xb4ff, 0xc08e, 0x21, 0 - .dw 0xb540, 0xc08e, 0xb57f, 0xc08e, 0x21, 0 - .dw 0xb5c0, 0xc08e, 0xb5ff, 0xc08e, 0x21, 0 - .dw 0xb640, 0xc08e, 0xb67f, 0xc08e, 0x21, 0 - .dw 0xb6c0, 0xc08e, 0xb6ff, 0xc08e, 0x21, 0 - .dw 0xb740, 0xc08e, 0xb77f, 0xc08e, 0x21, 0 - .dw 0xb7c0, 0xc08e, 0xb7ff, 0xc08e, 0x21, 0 - .dw 0xb840, 0xc08e, 0xb87f, 0xc08e, 0x21, 0 - .dw 0xb8c0, 0xc08e, 0xb8ff, 0xc08e, 0x21, 0 - .dw 0xb940, 0xc08e, 0xb97f, 0xc08e, 0x21, 0 - .dw 0xb9c0, 0xc08e, 0xbfff, 0xc08e, 0x21, 0 - .dw 0xc040, 0xc08e, 0xc07f, 0xc08e, 0x21, 0 - .dw 0xc0c0, 0xc08e, 0xc0ff, 0xc08e, 0x21, 0 - .dw 0xc140, 0xc08e, 0xc17f, 0xc08e, 0x21, 0 - .dw 0xc1c0, 0xc08e, 0xc1ff, 0xc08e, 0x21, 0 - .dw 0xc240, 0xc08e, 0xc27f, 0xc08e, 0x21, 0 - .dw 0xc2c0, 0xc08e, 0xc2ff, 0xc08e, 0x21, 0 - .dw 0xc340, 0xc08e, 0xc37f, 0xc08e, 0x21, 0 - .dw 0xc3c0, 0xc08e, 0xc3ff, 0xc08e, 0x21, 0 - .dw 0xc440, 0xc08e, 0xc47f, 0xc08e, 0x21, 0 - .dw 0xc4c0, 0xc08e, 0xc4ff, 0xc08e, 0x21, 0 - .dw 0xc540, 0xc08e, 0xc57f, 0xc08e, 0x21, 0 - .dw 0xc5c0, 0xc08e, 0xc5ff, 0xc08e, 0x21, 0 - .dw 0xc640, 0xc08e, 0xc67f, 0xc08e, 0x21, 0 - .dw 0xc6c0, 0xc08e, 0xc6ff, 0xc08e, 0x21, 0 - .dw 0xc740, 0xc08e, 0xc77f, 0xc08e, 0x21, 0 - .dw 0xc7c0, 0xc08e, 0xc7ff, 0xc08e, 0x21, 0 - .dw 0xc840, 0xc08e, 0xc87f, 0xc08e, 0x21, 0 - .dw 0xc8c0, 0xc08e, 0xc8ff, 0xc08e, 0x21, 0 - .dw 0xc940, 0xc08e, 0xc97f, 0xc08e, 0x21, 0 - .dw 0xc9c0, 0xc08e, 0xc9ff, 0xc08e, 0x21, 0 - .dw 0xca40, 0xc08e, 0xca7f, 0xc08e, 0x21, 0 - .dw 0xcac0, 0xc08e, 0xcaff, 0xc08e, 0x21, 0 - .dw 0xcb40, 0xc08e, 0xcb7f, 0xc08e, 0x21, 0 - .dw 0xcbc0, 0xc08e, 0xcbff, 0xc08e, 0x21, 0 - .dw 0xcc40, 0xc08e, 0xcc7f, 0xc08e, 0x21, 0 - .dw 0xccc0, 0xc08e, 0xccff, 0xc08e, 0x21, 0 - .dw 0xcd40, 0xc08e, 0xcd7f, 0xc08e, 0x21, 0 - .dw 0xcdc0, 0xc08e, 0xcdff, 0xc08e, 0x21, 0 - .dw 0xce40, 0xc08e, 0xce7f, 0xc08e, 0x21, 0 - .dw 0xcec0, 0xc08e, 0xceff, 0xc08e, 0x21, 0 - .dw 0xcf40, 0xc08e, 0xcf7f, 0xc08e, 0x21, 0 - .dw 0xcfc0, 0xc08e, 0xcfff, 0xc08e, 0x21, 0 - .dw 0xd040, 0xc08e, 0xd07f, 0xc08e, 0x21, 0 - .dw 0xd0c0, 0xc08e, 0xd0ff, 0xc08e, 0x21, 0 - .dw 0xd140, 0xc08e, 0xd17f, 0xc08e, 0x21, 0 - .dw 0xd1c0, 0xc08e, 0xd1ff, 0xc08e, 0x21, 0 - .dw 0xd240, 0xc08e, 0xd27f, 0xc08e, 0x21, 0 - .dw 0xd2c0, 0xc08e, 0xd2ff, 0xc08e, 0x21, 0 - .dw 0xd340, 0xc08e, 0xd37f, 0xc08e, 0x21, 0 - .dw 0xd3c0, 0xc08e, 0xd3ff, 0xc08e, 0x21, 0 - .dw 0xd440, 0xc08e, 0xd47f, 0xc08e, 0x21, 0 - .dw 0xd4c0, 0xc08e, 0xd4ff, 0xc08e, 0x21, 0 - .dw 0xd540, 0xc08e, 0xd57f, 0xc08e, 0x21, 0 - .dw 0xd5c0, 0xc08e, 0xd5ff, 0xc08e, 0x21, 0 - .dw 0xd640, 0xc08e, 0xd67f, 0xc08e, 0x21, 0 - .dw 0xd6c0, 0xc08e, 0xd6ff, 0xc08e, 0x21, 0 - .dw 0xd740, 0xc08e, 0xd77f, 0xc08e, 0x21, 0 - .dw 0xd7c0, 0xc08e, 0xd7ff, 0xc08e, 0x21, 0 - .dw 0xd840, 0xc08e, 0xd87f, 0xc08e, 0x21, 0 - .dw 0xd8c0, 0xc08e, 0xd8ff, 0xc08e, 0x21, 0 - .dw 0xd940, 0xc08e, 0xd97f, 0xc08e, 0x21, 0 - .dw 0xd9c0, 0xc08e, 0xdfff, 0xc08e, 0x21, 0 - .dw 0xe040, 0xc08e, 0xe07f, 0xc08e, 0x21, 0 - .dw 0xe0c0, 0xc08e, 0xe0ff, 0xc08e, 0x21, 0 - .dw 0xe140, 0xc08e, 0xe17f, 0xc08e, 0x21, 0 - .dw 0xe1c0, 0xc08e, 0xe1ff, 0xc08e, 0x21, 0 - .dw 0xe240, 0xc08e, 0xe27f, 0xc08e, 0x21, 0 - .dw 0xe2c0, 0xc08e, 0xe2ff, 0xc08e, 0x21, 0 - .dw 0xe340, 0xc08e, 0xe37f, 0xc08e, 0x21, 0 - .dw 0xe3c0, 0xc08e, 0xe3ff, 0xc08e, 0x21, 0 - .dw 0xe440, 0xc08e, 0xe47f, 0xc08e, 0x21, 0 - .dw 0xe4c0, 0xc08e, 0xe4ff, 0xc08e, 0x21, 0 - .dw 0xe540, 0xc08e, 0xe57f, 0xc08e, 0x21, 0 - .dw 0xe5c0, 0xc08e, 0xe5ff, 0xc08e, 0x21, 0 - .dw 0xe640, 0xc08e, 0xe67f, 0xc08e, 0x21, 0 - .dw 0xe6c0, 0xc08e, 0xe6ff, 0xc08e, 0x21, 0 - .dw 0xe740, 0xc08e, 0xe77f, 0xc08e, 0x21, 0 - .dw 0xe7c0, 0xc08e, 0xe7ff, 0xc08e, 0x21, 0 - .dw 0xe840, 0xc08e, 0xe87f, 0xc08e, 0x21, 0 - .dw 0xe8c0, 0xc08e, 0xe8ff, 0xc08e, 0x21, 0 - .dw 0xe940, 0xc08e, 0xe97f, 0xc08e, 0x21, 0 - .dw 0xe9c0, 0xc08e, 0xe9ff, 0xc08e, 0x21, 0 - .dw 0xea40, 0xc08e, 0xea7f, 0xc08e, 0x21, 0 - .dw 0xeac0, 0xc08e, 0xeaff, 0xc08e, 0x21, 0 - .dw 0xeb40, 0xc08e, 0xeb7f, 0xc08e, 0x21, 0 - .dw 0xebc0, 0xc08e, 0xebff, 0xc08e, 0x21, 0 - .dw 0xec40, 0xc08e, 0xec7f, 0xc08e, 0x21, 0 - .dw 0xecc0, 0xc08e, 0xecff, 0xc08e, 0x21, 0 - .dw 0xed40, 0xc08e, 0xed7f, 0xc08e, 0x21, 0 - .dw 0xedc0, 0xc08e, 0xedff, 0xc08e, 0x21, 0 - .dw 0xee40, 0xc08e, 0xee7f, 0xc08e, 0x21, 0 - .dw 0xeec0, 0xc08e, 0xeeff, 0xc08e, 0x21, 0 - .dw 0xef40, 0xc08e, 0xef7f, 0xc08e, 0x21, 0 - .dw 0xefc0, 0xc08e, 0xefff, 0xc08e, 0x21, 0 - .dw 0xf040, 0xc08e, 0xf07f, 0xc08e, 0x21, 0 - .dw 0xf0c0, 0xc08e, 0xf0ff, 0xc08e, 0x21, 0 - .dw 0xf140, 0xc08e, 0xf17f, 0xc08e, 0x21, 0 - .dw 0xf1c0, 0xc08e, 0xf1ff, 0xc08e, 0x21, 0 - .dw 0xf240, 0xc08e, 0xf27f, 0xc08e, 0x21, 0 - .dw 0xf2c0, 0xc08e, 0xf2ff, 0xc08e, 0x21, 0 - .dw 0xf340, 0xc08e, 0xf37f, 0xc08e, 0x21, 0 - .dw 0xf3c0, 0xc08e, 0xf3ff, 0xc08e, 0x21, 0 - .dw 0xf440, 0xc08e, 0xf47f, 0xc08e, 0x21, 0 - .dw 0xf4c0, 0xc08e, 0xf4ff, 0xc08e, 0x21, 0 - .dw 0xf540, 0xc08e, 0xf57f, 0xc08e, 0x21, 0 - .dw 0xf5c0, 0xc08e, 0xf5ff, 0xc08e, 0x21, 0 - .dw 0xf640, 0xc08e, 0xf67f, 0xc08e, 0x21, 0 - .dw 0xf6c0, 0xc08e, 0xf6ff, 0xc08e, 0x21, 0 - .dw 0xf740, 0xc08e, 0xf77f, 0xc08e, 0x21, 0 - .dw 0xf7c0, 0xc08e, 0xf7ff, 0xc08e, 0x21, 0 - .dw 0xf840, 0xc08e, 0xf87f, 0xc08e, 0x21, 0 - .dw 0xf8c0, 0xc08e, 0xf8ff, 0xc08e, 0x21, 0 - .dw 0xf940, 0xc08e, 0xf97f, 0xc08e, 0x21, 0 - .dw 0xf9c0, 0xc08e, 0xffff, 0xc08e, 0x21, 0 - .dw 0x0040, 0xc08f, 0x007f, 0xc08f, 0x21, 0 - .dw 0x00c0, 0xc08f, 0x00ff, 0xc08f, 0x21, 0 - .dw 0x0140, 0xc08f, 0x017f, 0xc08f, 0x21, 0 - .dw 0x01c0, 0xc08f, 0x01ff, 0xc08f, 0x21, 0 - .dw 0x0240, 0xc08f, 0x027f, 0xc08f, 0x21, 0 - .dw 0x02c0, 0xc08f, 0x02ff, 0xc08f, 0x21, 0 - .dw 0x0340, 0xc08f, 0x037f, 0xc08f, 0x21, 0 - .dw 0x03c0, 0xc08f, 0x03ff, 0xc08f, 0x21, 0 - .dw 0x0440, 0xc08f, 0x047f, 0xc08f, 0x21, 0 - .dw 0x04c0, 0xc08f, 0x04ff, 0xc08f, 0x21, 0 - .dw 0x0540, 0xc08f, 0x057f, 0xc08f, 0x21, 0 - .dw 0x05c0, 0xc08f, 0x05ff, 0xc08f, 0x21, 0 - .dw 0x0640, 0xc08f, 0x067f, 0xc08f, 0x21, 0 - .dw 0x06c0, 0xc08f, 0x06ff, 0xc08f, 0x21, 0 - .dw 0x0740, 0xc08f, 0x077f, 0xc08f, 0x21, 0 - .dw 0x07c0, 0xc08f, 0x07ff, 0xc08f, 0x21, 0 - .dw 0x0840, 0xc08f, 0x087f, 0xc08f, 0x21, 0 - .dw 0x08c0, 0xc08f, 0x08ff, 0xc08f, 0x21, 0 - .dw 0x0940, 0xc08f, 0x097f, 0xc08f, 0x21, 0 - .dw 0x09c0, 0xc08f, 0x09ff, 0xc08f, 0x21, 0 - .dw 0x0a40, 0xc08f, 0x0a7f, 0xc08f, 0x21, 0 - .dw 0x0ac0, 0xc08f, 0x0aff, 0xc08f, 0x21, 0 - .dw 0x0b40, 0xc08f, 0x0b7f, 0xc08f, 0x21, 0 - .dw 0x0bc0, 0xc08f, 0x0bff, 0xc08f, 0x21, 0 - .dw 0x0c40, 0xc08f, 0x0c7f, 0xc08f, 0x21, 0 - .dw 0x0cc0, 0xc08f, 0x0cff, 0xc08f, 0x21, 0 - .dw 0x0d40, 0xc08f, 0x0d7f, 0xc08f, 0x21, 0 - .dw 0x0dc0, 0xc08f, 0x0dff, 0xc08f, 0x21, 0 - .dw 0x0e40, 0xc08f, 0x0e7f, 0xc08f, 0x21, 0 - .dw 0x0ec0, 0xc08f, 0x0eff, 0xc08f, 0x21, 0 - .dw 0x0f40, 0xc08f, 0x0f7f, 0xc08f, 0x21, 0 - .dw 0x0fc0, 0xc08f, 0x0fff, 0xc08f, 0x21, 0 - .dw 0x1040, 0xc08f, 0x107f, 0xc08f, 0x21, 0 - .dw 0x10c0, 0xc08f, 0x10ff, 0xc08f, 0x21, 0 - .dw 0x1140, 0xc08f, 0x117f, 0xc08f, 0x21, 0 - .dw 0x11c0, 0xc08f, 0x11ff, 0xc08f, 0x21, 0 - .dw 0x1240, 0xc08f, 0x127f, 0xc08f, 0x21, 0 - .dw 0x12c0, 0xc08f, 0x12ff, 0xc08f, 0x21, 0 - .dw 0x1340, 0xc08f, 0x137f, 0xc08f, 0x21, 0 - .dw 0x13c0, 0xc08f, 0x13ff, 0xc08f, 0x21, 0 - .dw 0x1440, 0xc08f, 0x147f, 0xc08f, 0x21, 0 - .dw 0x14c0, 0xc08f, 0x14ff, 0xc08f, 0x21, 0 - .dw 0x1540, 0xc08f, 0x157f, 0xc08f, 0x21, 0 - .dw 0x15c0, 0xc08f, 0x15ff, 0xc08f, 0x21, 0 - .dw 0x1640, 0xc08f, 0x167f, 0xc08f, 0x21, 0 - .dw 0x16c0, 0xc08f, 0x16ff, 0xc08f, 0x21, 0 - .dw 0x1740, 0xc08f, 0x177f, 0xc08f, 0x21, 0 - .dw 0x17c0, 0xc08f, 0x17ff, 0xc08f, 0x21, 0 - .dw 0x1840, 0xc08f, 0x187f, 0xc08f, 0x21, 0 - .dw 0x18c0, 0xc08f, 0x18ff, 0xc08f, 0x21, 0 - .dw 0x1940, 0xc08f, 0x197f, 0xc08f, 0x21, 0 - .dw 0x19c0, 0xc08f, 0x1fff, 0xc08f, 0x21, 0 - .dw 0x2040, 0xc08f, 0x207f, 0xc08f, 0x21, 0 - .dw 0x20c0, 0xc08f, 0x20ff, 0xc08f, 0x21, 0 - .dw 0x2140, 0xc08f, 0x217f, 0xc08f, 0x21, 0 - .dw 0x21c0, 0xc08f, 0x21ff, 0xc08f, 0x21, 0 - .dw 0x2240, 0xc08f, 0x227f, 0xc08f, 0x21, 0 - .dw 0x22c0, 0xc08f, 0x22ff, 0xc08f, 0x21, 0 - .dw 0x2340, 0xc08f, 0x237f, 0xc08f, 0x21, 0 - .dw 0x23c0, 0xc08f, 0x23ff, 0xc08f, 0x21, 0 - .dw 0x2440, 0xc08f, 0x247f, 0xc08f, 0x21, 0 - .dw 0x24c0, 0xc08f, 0x24ff, 0xc08f, 0x21, 0 - .dw 0x2540, 0xc08f, 0x257f, 0xc08f, 0x21, 0 - .dw 0x25c0, 0xc08f, 0x25ff, 0xc08f, 0x21, 0 - .dw 0x2640, 0xc08f, 0x267f, 0xc08f, 0x21, 0 - .dw 0x26c0, 0xc08f, 0x26ff, 0xc08f, 0x21, 0 - .dw 0x2740, 0xc08f, 0x277f, 0xc08f, 0x21, 0 - .dw 0x27c0, 0xc08f, 0x27ff, 0xc08f, 0x21, 0 - .dw 0x2840, 0xc08f, 0x287f, 0xc08f, 0x21, 0 - .dw 0x28c0, 0xc08f, 0x28ff, 0xc08f, 0x21, 0 - .dw 0x2940, 0xc08f, 0x297f, 0xc08f, 0x21, 0 - .dw 0x29c0, 0xc08f, 0x29ff, 0xc08f, 0x21, 0 - .dw 0x2a40, 0xc08f, 0x2a7f, 0xc08f, 0x21, 0 - .dw 0x2ac0, 0xc08f, 0x2aff, 0xc08f, 0x21, 0 - .dw 0x2b40, 0xc08f, 0x2b7f, 0xc08f, 0x21, 0 - .dw 0x2bc0, 0xc08f, 0x2bff, 0xc08f, 0x21, 0 - .dw 0x2c40, 0xc08f, 0x2c7f, 0xc08f, 0x21, 0 - .dw 0x2cc0, 0xc08f, 0x2cff, 0xc08f, 0x21, 0 - .dw 0x2d40, 0xc08f, 0x2d7f, 0xc08f, 0x21, 0 - .dw 0x2dc0, 0xc08f, 0x2dff, 0xc08f, 0x21, 0 - .dw 0x2e40, 0xc08f, 0x2e7f, 0xc08f, 0x21, 0 - .dw 0x2ec0, 0xc08f, 0x2eff, 0xc08f, 0x21, 0 - .dw 0x2f40, 0xc08f, 0x2f7f, 0xc08f, 0x21, 0 - .dw 0x2fc0, 0xc08f, 0x2fff, 0xc08f, 0x21, 0 - .dw 0x3040, 0xc08f, 0x307f, 0xc08f, 0x21, 0 - .dw 0x30c0, 0xc08f, 0x30ff, 0xc08f, 0x21, 0 - .dw 0x3140, 0xc08f, 0x317f, 0xc08f, 0x21, 0 - .dw 0x31c0, 0xc08f, 0x31ff, 0xc08f, 0x21, 0 - .dw 0x3240, 0xc08f, 0x327f, 0xc08f, 0x21, 0 - .dw 0x32c0, 0xc08f, 0x32ff, 0xc08f, 0x21, 0 - .dw 0x3340, 0xc08f, 0x337f, 0xc08f, 0x21, 0 - .dw 0x33c0, 0xc08f, 0x33ff, 0xc08f, 0x21, 0 - .dw 0x3440, 0xc08f, 0x347f, 0xc08f, 0x21, 0 - .dw 0x34c0, 0xc08f, 0x34ff, 0xc08f, 0x21, 0 - .dw 0x3540, 0xc08f, 0x357f, 0xc08f, 0x21, 0 - .dw 0x35c0, 0xc08f, 0x35ff, 0xc08f, 0x21, 0 - .dw 0x3640, 0xc08f, 0x367f, 0xc08f, 0x21, 0 - .dw 0x36c0, 0xc08f, 0x36ff, 0xc08f, 0x21, 0 - .dw 0x3740, 0xc08f, 0x377f, 0xc08f, 0x21, 0 - .dw 0x37c0, 0xc08f, 0x37ff, 0xc08f, 0x21, 0 - .dw 0x3840, 0xc08f, 0x387f, 0xc08f, 0x21, 0 - .dw 0x38c0, 0xc08f, 0x38ff, 0xc08f, 0x21, 0 - .dw 0x3940, 0xc08f, 0x397f, 0xc08f, 0x21, 0 - .dw 0x39c0, 0xc08f, 0xffff, 0xc08f, 0x21, 0 - .dw 0x1a00, 0xc090, 0x1fff, 0xc090, 0x21, 0 - .dw 0x3a00, 0xc090, 0x3fff, 0xc090, 0x21, 0 - .dw 0x5a00, 0xc090, 0x5fff, 0xc090, 0x21, 0 - .dw 0x7a00, 0xc090, 0x7fff, 0xc090, 0x21, 0 - .dw 0x9a00, 0xc090, 0x9fff, 0xc090, 0x21, 0 - .dw 0xba00, 0xc090, 0xbfff, 0xc090, 0x21, 0 - .dw 0xda00, 0xc090, 0xdfff, 0xc090, 0x21, 0 - .dw 0xfa00, 0xc090, 0xffff, 0xc090, 0x21, 0 - .dw 0x1a00, 0xc091, 0x1fff, 0xc091, 0x21, 0 - .dw 0x3a00, 0xc091, 0x3fff, 0xc091, 0x21, 0 - .dw 0x5a00, 0xc091, 0x5fff, 0xc091, 0x21, 0 - .dw 0x7a00, 0xc091, 0x7fff, 0xc091, 0x21, 0 - .dw 0x9a00, 0xc091, 0x9fff, 0xc091, 0x21, 0 - .dw 0xba00, 0xc091, 0xbfff, 0xc091, 0x21, 0 - .dw 0xda00, 0xc091, 0xdfff, 0xc091, 0x21, 0 - .dw 0xfa00, 0xc091, 0xffff, 0xc091, 0x21, 0 - .dw 0x1a00, 0xc092, 0x1fff, 0xc092, 0x21, 0 - .dw 0x3a00, 0xc092, 0x3fff, 0xc092, 0x21, 0 - .dw 0x5a00, 0xc092, 0x5fff, 0xc092, 0x21, 0 - .dw 0x7a00, 0xc092, 0x7fff, 0xc092, 0x21, 0 - .dw 0x9a00, 0xc092, 0x9fff, 0xc092, 0x21, 0 - .dw 0xba00, 0xc092, 0xbfff, 0xc092, 0x21, 0 - .dw 0xda00, 0xc092, 0xdfff, 0xc092, 0x21, 0 - .dw 0xfa00, 0xc092, 0xffff, 0xc093, 0x21, 0 - .dw 0x1a00, 0xc094, 0x1fff, 0xc094, 0x21, 0 - .dw 0x3a00, 0xc094, 0x3fff, 0xc094, 0x21, 0 - .dw 0x5a00, 0xc094, 0x5fff, 0xc094, 0x21, 0 - .dw 0x7a00, 0xc094, 0x7fff, 0xc094, 0x21, 0 - .dw 0x9a00, 0xc094, 0x9fff, 0xc094, 0x21, 0 - .dw 0xba00, 0xc094, 0xbfff, 0xc094, 0x21, 0 - .dw 0xda00, 0xc094, 0xdfff, 0xc094, 0x21, 0 - .dw 0xfa00, 0xc094, 0xffff, 0xc094, 0x21, 0 - .dw 0x1a00, 0xc095, 0x1fff, 0xc095, 0x21, 0 - .dw 0x3a00, 0xc095, 0x3fff, 0xc095, 0x21, 0 - .dw 0x5a00, 0xc095, 0x5fff, 0xc095, 0x21, 0 - .dw 0x7a00, 0xc095, 0x7fff, 0xc095, 0x21, 0 - .dw 0x9a00, 0xc095, 0x9fff, 0xc095, 0x21, 0 - .dw 0xba00, 0xc095, 0xbfff, 0xc095, 0x21, 0 - .dw 0xda00, 0xc095, 0xdfff, 0xc095, 0x21, 0 - .dw 0xfa00, 0xc095, 0xffff, 0xc095, 0x21, 0 - .dw 0x1a00, 0xc096, 0x1fff, 0xc096, 0x21, 0 - .dw 0x3a00, 0xc096, 0x3fff, 0xc096, 0x21, 0 - .dw 0x5a00, 0xc096, 0x5fff, 0xc096, 0x21, 0 - .dw 0x7a00, 0xc096, 0x7fff, 0xc096, 0x21, 0 - .dw 0x9a00, 0xc096, 0x9fff, 0xc096, 0x21, 0 - .dw 0xba00, 0xc096, 0xbfff, 0xc096, 0x21, 0 - .dw 0xda00, 0xc096, 0xdfff, 0xc096, 0x21, 0 - .dw 0xfa00, 0xc096, 0xffff, 0xc096, 0x21, 0 - .dw 0x1a00, 0xc097, 0x1fff, 0xc097, 0x21, 0 - .dw 0x3a00, 0xc097, 0x1fff, 0xc098, 0x21, 0 - .dw 0x2040, 0xc098, 0x207f, 0xc098, 0x21, 0 - .dw 0x20c0, 0xc098, 0x20ff, 0xc098, 0x21, 0 - .dw 0x2140, 0xc098, 0x217f, 0xc098, 0x21, 0 - .dw 0x21c0, 0xc098, 0x21ff, 0xc098, 0x21, 0 - .dw 0x2240, 0xc098, 0x227f, 0xc098, 0x21, 0 - .dw 0x22c0, 0xc098, 0x22ff, 0xc098, 0x21, 0 - .dw 0x2340, 0xc098, 0x237f, 0xc098, 0x21, 0 - .dw 0x23c0, 0xc098, 0x23ff, 0xc098, 0x21, 0 - .dw 0x2440, 0xc098, 0x247f, 0xc098, 0x21, 0 - .dw 0x24c0, 0xc098, 0x24ff, 0xc098, 0x21, 0 - .dw 0x2540, 0xc098, 0x257f, 0xc098, 0x21, 0 - .dw 0x25c0, 0xc098, 0x25ff, 0xc098, 0x21, 0 - .dw 0x2640, 0xc098, 0x267f, 0xc098, 0x21, 0 - .dw 0x26c0, 0xc098, 0x26ff, 0xc098, 0x21, 0 - .dw 0x2740, 0xc098, 0x277f, 0xc098, 0x21, 0 - .dw 0x27c0, 0xc098, 0x27ff, 0xc098, 0x21, 0 - .dw 0x2840, 0xc098, 0x287f, 0xc098, 0x21, 0 - .dw 0x28c0, 0xc098, 0x28ff, 0xc098, 0x21, 0 - .dw 0x2940, 0xc098, 0x297f, 0xc098, 0x21, 0 - .dw 0x29c0, 0xc098, 0x29ff, 0xc098, 0x21, 0 - .dw 0x2a40, 0xc098, 0x2a7f, 0xc098, 0x21, 0 - .dw 0x2ac0, 0xc098, 0x2aff, 0xc098, 0x21, 0 - .dw 0x2b40, 0xc098, 0x2b7f, 0xc098, 0x21, 0 - .dw 0x2bc0, 0xc098, 0x2bff, 0xc098, 0x21, 0 - .dw 0x2c40, 0xc098, 0x2c7f, 0xc098, 0x21, 0 - .dw 0x2cc0, 0xc098, 0x2cff, 0xc098, 0x21, 0 - .dw 0x2d40, 0xc098, 0x2d7f, 0xc098, 0x21, 0 - .dw 0x2dc0, 0xc098, 0x2dff, 0xc098, 0x21, 0 - .dw 0x2e40, 0xc098, 0x2e7f, 0xc098, 0x21, 0 - .dw 0x2ec0, 0xc098, 0x2eff, 0xc098, 0x21, 0 - .dw 0x2f40, 0xc098, 0x2f7f, 0xc098, 0x21, 0 - .dw 0x2fc0, 0xc098, 0x2fff, 0xc098, 0x21, 0 - .dw 0x3040, 0xc098, 0x307f, 0xc098, 0x21, 0 - .dw 0x30c0, 0xc098, 0x30ff, 0xc098, 0x21, 0 - .dw 0x3140, 0xc098, 0x317f, 0xc098, 0x21, 0 - .dw 0x31c0, 0xc098, 0x31ff, 0xc098, 0x21, 0 - .dw 0x3240, 0xc098, 0x327f, 0xc098, 0x21, 0 - .dw 0x32c0, 0xc098, 0x32ff, 0xc098, 0x21, 0 - .dw 0x3340, 0xc098, 0x337f, 0xc098, 0x21, 0 - .dw 0x33c0, 0xc098, 0x33ff, 0xc098, 0x21, 0 - .dw 0x3440, 0xc098, 0x347f, 0xc098, 0x21, 0 - .dw 0x34c0, 0xc098, 0x34ff, 0xc098, 0x21, 0 - .dw 0x3540, 0xc098, 0x357f, 0xc098, 0x21, 0 - .dw 0x35c0, 0xc098, 0x35ff, 0xc098, 0x21, 0 - .dw 0x3640, 0xc098, 0x367f, 0xc098, 0x21, 0 - .dw 0x36c0, 0xc098, 0x36ff, 0xc098, 0x21, 0 - .dw 0x3740, 0xc098, 0x377f, 0xc098, 0x21, 0 - .dw 0x37c0, 0xc098, 0x37ff, 0xc098, 0x21, 0 - .dw 0x3840, 0xc098, 0x387f, 0xc098, 0x21, 0 - .dw 0x38c0, 0xc098, 0x38ff, 0xc098, 0x21, 0 - .dw 0x3940, 0xc098, 0x397f, 0xc098, 0x21, 0 - .dw 0x39c0, 0xc098, 0x5fff, 0xc098, 0x21, 0 - .dw 0x6040, 0xc098, 0x607f, 0xc098, 0x21, 0 - .dw 0x60c0, 0xc098, 0x60ff, 0xc098, 0x21, 0 - .dw 0x6140, 0xc098, 0x617f, 0xc098, 0x21, 0 - .dw 0x61c0, 0xc098, 0x61ff, 0xc098, 0x21, 0 - .dw 0x6240, 0xc098, 0x627f, 0xc098, 0x21, 0 - .dw 0x62c0, 0xc098, 0x62ff, 0xc098, 0x21, 0 - .dw 0x6340, 0xc098, 0x637f, 0xc098, 0x21, 0 - .dw 0x63c0, 0xc098, 0x63ff, 0xc098, 0x21, 0 - .dw 0x6440, 0xc098, 0x647f, 0xc098, 0x21, 0 - .dw 0x64c0, 0xc098, 0x64ff, 0xc098, 0x21, 0 - .dw 0x6540, 0xc098, 0x657f, 0xc098, 0x21, 0 - .dw 0x65c0, 0xc098, 0x65ff, 0xc098, 0x21, 0 - .dw 0x6640, 0xc098, 0x667f, 0xc098, 0x21, 0 - .dw 0x66c0, 0xc098, 0x66ff, 0xc098, 0x21, 0 - .dw 0x6740, 0xc098, 0x677f, 0xc098, 0x21, 0 - .dw 0x67c0, 0xc098, 0x67ff, 0xc098, 0x21, 0 - .dw 0x6840, 0xc098, 0x687f, 0xc098, 0x21, 0 - .dw 0x68c0, 0xc098, 0x68ff, 0xc098, 0x21, 0 - .dw 0x6940, 0xc098, 0x697f, 0xc098, 0x21, 0 - .dw 0x69c0, 0xc098, 0x69ff, 0xc098, 0x21, 0 - .dw 0x6a40, 0xc098, 0x6a7f, 0xc098, 0x21, 0 - .dw 0x6ac0, 0xc098, 0x6aff, 0xc098, 0x21, 0 - .dw 0x6b40, 0xc098, 0x6b7f, 0xc098, 0x21, 0 - .dw 0x6bc0, 0xc098, 0x6bff, 0xc098, 0x21, 0 - .dw 0x6c40, 0xc098, 0x6c7f, 0xc098, 0x21, 0 - .dw 0x6cc0, 0xc098, 0x6cff, 0xc098, 0x21, 0 - .dw 0x6d40, 0xc098, 0x6d7f, 0xc098, 0x21, 0 - .dw 0x6dc0, 0xc098, 0x6dff, 0xc098, 0x21, 0 - .dw 0x6e40, 0xc098, 0x6e7f, 0xc098, 0x21, 0 - .dw 0x6ec0, 0xc098, 0x6eff, 0xc098, 0x21, 0 - .dw 0x6f40, 0xc098, 0x6f7f, 0xc098, 0x21, 0 - .dw 0x6fc0, 0xc098, 0x6fff, 0xc098, 0x21, 0 - .dw 0x7040, 0xc098, 0x707f, 0xc098, 0x21, 0 - .dw 0x70c0, 0xc098, 0x70ff, 0xc098, 0x21, 0 - .dw 0x7140, 0xc098, 0x717f, 0xc098, 0x21, 0 - .dw 0x71c0, 0xc098, 0x71ff, 0xc098, 0x21, 0 - .dw 0x7240, 0xc098, 0x727f, 0xc098, 0x21, 0 - .dw 0x72c0, 0xc098, 0x72ff, 0xc098, 0x21, 0 - .dw 0x7340, 0xc098, 0x737f, 0xc098, 0x21, 0 - .dw 0x73c0, 0xc098, 0x73ff, 0xc098, 0x21, 0 - .dw 0x7440, 0xc098, 0x747f, 0xc098, 0x21, 0 - .dw 0x74c0, 0xc098, 0x74ff, 0xc098, 0x21, 0 - .dw 0x7540, 0xc098, 0x757f, 0xc098, 0x21, 0 - .dw 0x75c0, 0xc098, 0x75ff, 0xc098, 0x21, 0 - .dw 0x7640, 0xc098, 0x767f, 0xc098, 0x21, 0 - .dw 0x76c0, 0xc098, 0x76ff, 0xc098, 0x21, 0 - .dw 0x7740, 0xc098, 0x777f, 0xc098, 0x21, 0 - .dw 0x77c0, 0xc098, 0x77ff, 0xc098, 0x21, 0 - .dw 0x7840, 0xc098, 0x787f, 0xc098, 0x21, 0 - .dw 0x78c0, 0xc098, 0x78ff, 0xc098, 0x21, 0 - .dw 0x7940, 0xc098, 0x797f, 0xc098, 0x21, 0 - .dw 0x79c0, 0xc098, 0x9fff, 0xc098, 0x21, 0 - .dw 0xa040, 0xc098, 0xa07f, 0xc098, 0x21, 0 - .dw 0xa0c0, 0xc098, 0xa0ff, 0xc098, 0x21, 0 - .dw 0xa140, 0xc098, 0xa17f, 0xc098, 0x21, 0 - .dw 0xa1c0, 0xc098, 0xa1ff, 0xc098, 0x21, 0 - .dw 0xa240, 0xc098, 0xa27f, 0xc098, 0x21, 0 - .dw 0xa2c0, 0xc098, 0xa2ff, 0xc098, 0x21, 0 - .dw 0xa340, 0xc098, 0xa37f, 0xc098, 0x21, 0 - .dw 0xa3c0, 0xc098, 0xa3ff, 0xc098, 0x21, 0 - .dw 0xa440, 0xc098, 0xa47f, 0xc098, 0x21, 0 - .dw 0xa4c0, 0xc098, 0xa4ff, 0xc098, 0x21, 0 - .dw 0xa540, 0xc098, 0xa57f, 0xc098, 0x21, 0 - .dw 0xa5c0, 0xc098, 0xa5ff, 0xc098, 0x21, 0 - .dw 0xa640, 0xc098, 0xa67f, 0xc098, 0x21, 0 - .dw 0xa6c0, 0xc098, 0xa6ff, 0xc098, 0x21, 0 - .dw 0xa740, 0xc098, 0xa77f, 0xc098, 0x21, 0 - .dw 0xa7c0, 0xc098, 0xa7ff, 0xc098, 0x21, 0 - .dw 0xa840, 0xc098, 0xa87f, 0xc098, 0x21, 0 - .dw 0xa8c0, 0xc098, 0xa8ff, 0xc098, 0x21, 0 - .dw 0xa940, 0xc098, 0xa97f, 0xc098, 0x21, 0 - .dw 0xa9c0, 0xc098, 0xa9ff, 0xc098, 0x21, 0 - .dw 0xaa40, 0xc098, 0xaa7f, 0xc098, 0x21, 0 - .dw 0xaac0, 0xc098, 0xaaff, 0xc098, 0x21, 0 - .dw 0xab40, 0xc098, 0xab7f, 0xc098, 0x21, 0 - .dw 0xabc0, 0xc098, 0xabff, 0xc098, 0x21, 0 - .dw 0xac40, 0xc098, 0xac7f, 0xc098, 0x21, 0 - .dw 0xacc0, 0xc098, 0xacff, 0xc098, 0x21, 0 - .dw 0xad40, 0xc098, 0xad7f, 0xc098, 0x21, 0 - .dw 0xadc0, 0xc098, 0xadff, 0xc098, 0x21, 0 - .dw 0xae40, 0xc098, 0xae7f, 0xc098, 0x21, 0 - .dw 0xaec0, 0xc098, 0xaeff, 0xc098, 0x21, 0 - .dw 0xaf40, 0xc098, 0xaf7f, 0xc098, 0x21, 0 - .dw 0xafc0, 0xc098, 0xafff, 0xc098, 0x21, 0 - .dw 0xb040, 0xc098, 0xb07f, 0xc098, 0x21, 0 - .dw 0xb0c0, 0xc098, 0xb0ff, 0xc098, 0x21, 0 - .dw 0xb140, 0xc098, 0xb17f, 0xc098, 0x21, 0 - .dw 0xb1c0, 0xc098, 0xb1ff, 0xc098, 0x21, 0 - .dw 0xb240, 0xc098, 0xb27f, 0xc098, 0x21, 0 - .dw 0xb2c0, 0xc098, 0xb2ff, 0xc098, 0x21, 0 - .dw 0xb340, 0xc098, 0xb37f, 0xc098, 0x21, 0 - .dw 0xb3c0, 0xc098, 0xb3ff, 0xc098, 0x21, 0 - .dw 0xb440, 0xc098, 0xb47f, 0xc098, 0x21, 0 - .dw 0xb4c0, 0xc098, 0xb4ff, 0xc098, 0x21, 0 - .dw 0xb540, 0xc098, 0xb57f, 0xc098, 0x21, 0 - .dw 0xb5c0, 0xc098, 0xb5ff, 0xc098, 0x21, 0 - .dw 0xb640, 0xc098, 0xb67f, 0xc098, 0x21, 0 - .dw 0xb6c0, 0xc098, 0xb6ff, 0xc098, 0x21, 0 - .dw 0xb740, 0xc098, 0xb77f, 0xc098, 0x21, 0 - .dw 0xb7c0, 0xc098, 0xb7ff, 0xc098, 0x21, 0 - .dw 0xb840, 0xc098, 0xb87f, 0xc098, 0x21, 0 - .dw 0xb8c0, 0xc098, 0xb8ff, 0xc098, 0x21, 0 - .dw 0xb940, 0xc098, 0xb97f, 0xc098, 0x21, 0 - .dw 0xb9c0, 0xc098, 0xdfff, 0xc098, 0x21, 0 - .dw 0xe040, 0xc098, 0xe07f, 0xc098, 0x21, 0 - .dw 0xe0c0, 0xc098, 0xe0ff, 0xc098, 0x21, 0 - .dw 0xe140, 0xc098, 0xe17f, 0xc098, 0x21, 0 - .dw 0xe1c0, 0xc098, 0xe1ff, 0xc098, 0x21, 0 - .dw 0xe240, 0xc098, 0xe27f, 0xc098, 0x21, 0 - .dw 0xe2c0, 0xc098, 0xe2ff, 0xc098, 0x21, 0 - .dw 0xe340, 0xc098, 0xe37f, 0xc098, 0x21, 0 - .dw 0xe3c0, 0xc098, 0xe3ff, 0xc098, 0x21, 0 - .dw 0xe440, 0xc098, 0xe47f, 0xc098, 0x21, 0 - .dw 0xe4c0, 0xc098, 0xe4ff, 0xc098, 0x21, 0 - .dw 0xe540, 0xc098, 0xe57f, 0xc098, 0x21, 0 - .dw 0xe5c0, 0xc098, 0xe5ff, 0xc098, 0x21, 0 - .dw 0xe640, 0xc098, 0xe67f, 0xc098, 0x21, 0 - .dw 0xe6c0, 0xc098, 0xe6ff, 0xc098, 0x21, 0 - .dw 0xe740, 0xc098, 0xe77f, 0xc098, 0x21, 0 - .dw 0xe7c0, 0xc098, 0xe7ff, 0xc098, 0x21, 0 - .dw 0xe840, 0xc098, 0xe87f, 0xc098, 0x21, 0 - .dw 0xe8c0, 0xc098, 0xe8ff, 0xc098, 0x21, 0 - .dw 0xe940, 0xc098, 0xe97f, 0xc098, 0x21, 0 - .dw 0xe9c0, 0xc098, 0xe9ff, 0xc098, 0x21, 0 - .dw 0xea40, 0xc098, 0xea7f, 0xc098, 0x21, 0 - .dw 0xeac0, 0xc098, 0xeaff, 0xc098, 0x21, 0 - .dw 0xeb40, 0xc098, 0xeb7f, 0xc098, 0x21, 0 - .dw 0xebc0, 0xc098, 0xebff, 0xc098, 0x21, 0 - .dw 0xec40, 0xc098, 0xec7f, 0xc098, 0x21, 0 - .dw 0xecc0, 0xc098, 0xecff, 0xc098, 0x21, 0 - .dw 0xed40, 0xc098, 0xed7f, 0xc098, 0x21, 0 - .dw 0xedc0, 0xc098, 0xedff, 0xc098, 0x21, 0 - .dw 0xee40, 0xc098, 0xee7f, 0xc098, 0x21, 0 - .dw 0xeec0, 0xc098, 0xeeff, 0xc098, 0x21, 0 - .dw 0xef40, 0xc098, 0xef7f, 0xc098, 0x21, 0 - .dw 0xefc0, 0xc098, 0xefff, 0xc098, 0x21, 0 - .dw 0xf040, 0xc098, 0xf07f, 0xc098, 0x21, 0 - .dw 0xf0c0, 0xc098, 0xf0ff, 0xc098, 0x21, 0 - .dw 0xf140, 0xc098, 0xf17f, 0xc098, 0x21, 0 - .dw 0xf1c0, 0xc098, 0xf1ff, 0xc098, 0x21, 0 - .dw 0xf240, 0xc098, 0xf27f, 0xc098, 0x21, 0 - .dw 0xf2c0, 0xc098, 0xf2ff, 0xc098, 0x21, 0 - .dw 0xf340, 0xc098, 0xf37f, 0xc098, 0x21, 0 - .dw 0xf3c0, 0xc098, 0xf3ff, 0xc098, 0x21, 0 - .dw 0xf440, 0xc098, 0xf47f, 0xc098, 0x21, 0 - .dw 0xf4c0, 0xc098, 0xf4ff, 0xc098, 0x21, 0 - .dw 0xf540, 0xc098, 0xf57f, 0xc098, 0x21, 0 - .dw 0xf5c0, 0xc098, 0xf5ff, 0xc098, 0x21, 0 - .dw 0xf640, 0xc098, 0xf67f, 0xc098, 0x21, 0 - .dw 0xf6c0, 0xc098, 0xf6ff, 0xc098, 0x21, 0 - .dw 0xf740, 0xc098, 0xf77f, 0xc098, 0x21, 0 - .dw 0xf7c0, 0xc098, 0xf7ff, 0xc098, 0x21, 0 - .dw 0xf840, 0xc098, 0xf87f, 0xc098, 0x21, 0 - .dw 0xf8c0, 0xc098, 0xf8ff, 0xc098, 0x21, 0 - .dw 0xf940, 0xc098, 0xf97f, 0xc098, 0x21, 0 - .dw 0xf9c0, 0xc098, 0x1fff, 0xc099, 0x21, 0 - .dw 0x2040, 0xc099, 0x207f, 0xc099, 0x21, 0 - .dw 0x20c0, 0xc099, 0x20ff, 0xc099, 0x21, 0 - .dw 0x2140, 0xc099, 0x217f, 0xc099, 0x21, 0 - .dw 0x21c0, 0xc099, 0x21ff, 0xc099, 0x21, 0 - .dw 0x2240, 0xc099, 0x227f, 0xc099, 0x21, 0 - .dw 0x22c0, 0xc099, 0x22ff, 0xc099, 0x21, 0 - .dw 0x2340, 0xc099, 0x237f, 0xc099, 0x21, 0 - .dw 0x23c0, 0xc099, 0x23ff, 0xc099, 0x21, 0 - .dw 0x2440, 0xc099, 0x247f, 0xc099, 0x21, 0 - .dw 0x24c0, 0xc099, 0x24ff, 0xc099, 0x21, 0 - .dw 0x2540, 0xc099, 0x257f, 0xc099, 0x21, 0 - .dw 0x25c0, 0xc099, 0x25ff, 0xc099, 0x21, 0 - .dw 0x2640, 0xc099, 0x267f, 0xc099, 0x21, 0 - .dw 0x26c0, 0xc099, 0x26ff, 0xc099, 0x21, 0 - .dw 0x2740, 0xc099, 0x277f, 0xc099, 0x21, 0 - .dw 0x27c0, 0xc099, 0x27ff, 0xc099, 0x21, 0 - .dw 0x2840, 0xc099, 0x287f, 0xc099, 0x21, 0 - .dw 0x28c0, 0xc099, 0x28ff, 0xc099, 0x21, 0 - .dw 0x2940, 0xc099, 0x297f, 0xc099, 0x21, 0 - .dw 0x29c0, 0xc099, 0x29ff, 0xc099, 0x21, 0 - .dw 0x2a40, 0xc099, 0x2a7f, 0xc099, 0x21, 0 - .dw 0x2ac0, 0xc099, 0x2aff, 0xc099, 0x21, 0 - .dw 0x2b40, 0xc099, 0x2b7f, 0xc099, 0x21, 0 - .dw 0x2bc0, 0xc099, 0x2bff, 0xc099, 0x21, 0 - .dw 0x2c40, 0xc099, 0x2c7f, 0xc099, 0x21, 0 - .dw 0x2cc0, 0xc099, 0x2cff, 0xc099, 0x21, 0 - .dw 0x2d40, 0xc099, 0x2d7f, 0xc099, 0x21, 0 - .dw 0x2dc0, 0xc099, 0x2dff, 0xc099, 0x21, 0 - .dw 0x2e40, 0xc099, 0x2e7f, 0xc099, 0x21, 0 - .dw 0x2ec0, 0xc099, 0x2eff, 0xc099, 0x21, 0 - .dw 0x2f40, 0xc099, 0x2f7f, 0xc099, 0x21, 0 - .dw 0x2fc0, 0xc099, 0x2fff, 0xc099, 0x21, 0 - .dw 0x3040, 0xc099, 0x307f, 0xc099, 0x21, 0 - .dw 0x30c0, 0xc099, 0x30ff, 0xc099, 0x21, 0 - .dw 0x3140, 0xc099, 0x317f, 0xc099, 0x21, 0 - .dw 0x31c0, 0xc099, 0x31ff, 0xc099, 0x21, 0 - .dw 0x3240, 0xc099, 0x327f, 0xc099, 0x21, 0 - .dw 0x32c0, 0xc099, 0x32ff, 0xc099, 0x21, 0 - .dw 0x3340, 0xc099, 0x337f, 0xc099, 0x21, 0 - .dw 0x33c0, 0xc099, 0x33ff, 0xc099, 0x21, 0 - .dw 0x3440, 0xc099, 0x347f, 0xc099, 0x21, 0 - .dw 0x34c0, 0xc099, 0x34ff, 0xc099, 0x21, 0 - .dw 0x3540, 0xc099, 0x357f, 0xc099, 0x21, 0 - .dw 0x35c0, 0xc099, 0x35ff, 0xc099, 0x21, 0 - .dw 0x3640, 0xc099, 0x367f, 0xc099, 0x21, 0 - .dw 0x36c0, 0xc099, 0x36ff, 0xc099, 0x21, 0 - .dw 0x3740, 0xc099, 0x377f, 0xc099, 0x21, 0 - .dw 0x37c0, 0xc099, 0x37ff, 0xc099, 0x21, 0 - .dw 0x3840, 0xc099, 0x387f, 0xc099, 0x21, 0 - .dw 0x38c0, 0xc099, 0x38ff, 0xc099, 0x21, 0 - .dw 0x3940, 0xc099, 0x397f, 0xc099, 0x21, 0 - .dw 0x39c0, 0xc099, 0x5fff, 0xc099, 0x21, 0 - .dw 0x6040, 0xc099, 0x607f, 0xc099, 0x21, 0 - .dw 0x60c0, 0xc099, 0x60ff, 0xc099, 0x21, 0 - .dw 0x6140, 0xc099, 0x617f, 0xc099, 0x21, 0 - .dw 0x61c0, 0xc099, 0x61ff, 0xc099, 0x21, 0 - .dw 0x6240, 0xc099, 0x627f, 0xc099, 0x21, 0 - .dw 0x62c0, 0xc099, 0x62ff, 0xc099, 0x21, 0 - .dw 0x6340, 0xc099, 0x637f, 0xc099, 0x21, 0 - .dw 0x63c0, 0xc099, 0x63ff, 0xc099, 0x21, 0 - .dw 0x6440, 0xc099, 0x647f, 0xc099, 0x21, 0 - .dw 0x64c0, 0xc099, 0x64ff, 0xc099, 0x21, 0 - .dw 0x6540, 0xc099, 0x657f, 0xc099, 0x21, 0 - .dw 0x65c0, 0xc099, 0x65ff, 0xc099, 0x21, 0 - .dw 0x6640, 0xc099, 0x667f, 0xc099, 0x21, 0 - .dw 0x66c0, 0xc099, 0x66ff, 0xc099, 0x21, 0 - .dw 0x6740, 0xc099, 0x677f, 0xc099, 0x21, 0 - .dw 0x67c0, 0xc099, 0x67ff, 0xc099, 0x21, 0 - .dw 0x6840, 0xc099, 0x687f, 0xc099, 0x21, 0 - .dw 0x68c0, 0xc099, 0x68ff, 0xc099, 0x21, 0 - .dw 0x6940, 0xc099, 0x697f, 0xc099, 0x21, 0 - .dw 0x69c0, 0xc099, 0x69ff, 0xc099, 0x21, 0 - .dw 0x6a40, 0xc099, 0x6a7f, 0xc099, 0x21, 0 - .dw 0x6ac0, 0xc099, 0x6aff, 0xc099, 0x21, 0 - .dw 0x6b40, 0xc099, 0x6b7f, 0xc099, 0x21, 0 - .dw 0x6bc0, 0xc099, 0x6bff, 0xc099, 0x21, 0 - .dw 0x6c40, 0xc099, 0x6c7f, 0xc099, 0x21, 0 - .dw 0x6cc0, 0xc099, 0x6cff, 0xc099, 0x21, 0 - .dw 0x6d40, 0xc099, 0x6d7f, 0xc099, 0x21, 0 - .dw 0x6dc0, 0xc099, 0x6dff, 0xc099, 0x21, 0 - .dw 0x6e40, 0xc099, 0x6e7f, 0xc099, 0x21, 0 - .dw 0x6ec0, 0xc099, 0x6eff, 0xc099, 0x21, 0 - .dw 0x6f40, 0xc099, 0x6f7f, 0xc099, 0x21, 0 - .dw 0x6fc0, 0xc099, 0x6fff, 0xc099, 0x21, 0 - .dw 0x7040, 0xc099, 0x707f, 0xc099, 0x21, 0 - .dw 0x70c0, 0xc099, 0x70ff, 0xc099, 0x21, 0 - .dw 0x7140, 0xc099, 0x717f, 0xc099, 0x21, 0 - .dw 0x71c0, 0xc099, 0x71ff, 0xc099, 0x21, 0 - .dw 0x7240, 0xc099, 0x727f, 0xc099, 0x21, 0 - .dw 0x72c0, 0xc099, 0x72ff, 0xc099, 0x21, 0 - .dw 0x7340, 0xc099, 0x737f, 0xc099, 0x21, 0 - .dw 0x73c0, 0xc099, 0x73ff, 0xc099, 0x21, 0 - .dw 0x7440, 0xc099, 0x747f, 0xc099, 0x21, 0 - .dw 0x74c0, 0xc099, 0x74ff, 0xc099, 0x21, 0 - .dw 0x7540, 0xc099, 0x757f, 0xc099, 0x21, 0 - .dw 0x75c0, 0xc099, 0x75ff, 0xc099, 0x21, 0 - .dw 0x7640, 0xc099, 0x767f, 0xc099, 0x21, 0 - .dw 0x76c0, 0xc099, 0x76ff, 0xc099, 0x21, 0 - .dw 0x7740, 0xc099, 0x777f, 0xc099, 0x21, 0 - .dw 0x77c0, 0xc099, 0x77ff, 0xc099, 0x21, 0 - .dw 0x7840, 0xc099, 0x787f, 0xc099, 0x21, 0 - .dw 0x78c0, 0xc099, 0x78ff, 0xc099, 0x21, 0 - .dw 0x7940, 0xc099, 0x797f, 0xc099, 0x21, 0 - .dw 0x79c0, 0xc099, 0x9fff, 0xc099, 0x21, 0 - .dw 0xa040, 0xc099, 0xa07f, 0xc099, 0x21, 0 - .dw 0xa0c0, 0xc099, 0xa0ff, 0xc099, 0x21, 0 - .dw 0xa140, 0xc099, 0xa17f, 0xc099, 0x21, 0 - .dw 0xa1c0, 0xc099, 0xa1ff, 0xc099, 0x21, 0 - .dw 0xa240, 0xc099, 0xa27f, 0xc099, 0x21, 0 - .dw 0xa2c0, 0xc099, 0xa2ff, 0xc099, 0x21, 0 - .dw 0xa340, 0xc099, 0xa37f, 0xc099, 0x21, 0 - .dw 0xa3c0, 0xc099, 0xa3ff, 0xc099, 0x21, 0 - .dw 0xa440, 0xc099, 0xa47f, 0xc099, 0x21, 0 - .dw 0xa4c0, 0xc099, 0xa4ff, 0xc099, 0x21, 0 - .dw 0xa540, 0xc099, 0xa57f, 0xc099, 0x21, 0 - .dw 0xa5c0, 0xc099, 0xa5ff, 0xc099, 0x21, 0 - .dw 0xa640, 0xc099, 0xa67f, 0xc099, 0x21, 0 - .dw 0xa6c0, 0xc099, 0xa6ff, 0xc099, 0x21, 0 - .dw 0xa740, 0xc099, 0xa77f, 0xc099, 0x21, 0 - .dw 0xa7c0, 0xc099, 0xa7ff, 0xc099, 0x21, 0 - .dw 0xa840, 0xc099, 0xa87f, 0xc099, 0x21, 0 - .dw 0xa8c0, 0xc099, 0xa8ff, 0xc099, 0x21, 0 - .dw 0xa940, 0xc099, 0xa97f, 0xc099, 0x21, 0 - .dw 0xa9c0, 0xc099, 0xa9ff, 0xc099, 0x21, 0 - .dw 0xaa40, 0xc099, 0xaa7f, 0xc099, 0x21, 0 - .dw 0xaac0, 0xc099, 0xaaff, 0xc099, 0x21, 0 - .dw 0xab40, 0xc099, 0xab7f, 0xc099, 0x21, 0 - .dw 0xabc0, 0xc099, 0xabff, 0xc099, 0x21, 0 - .dw 0xac40, 0xc099, 0xac7f, 0xc099, 0x21, 0 - .dw 0xacc0, 0xc099, 0xacff, 0xc099, 0x21, 0 - .dw 0xad40, 0xc099, 0xad7f, 0xc099, 0x21, 0 - .dw 0xadc0, 0xc099, 0xadff, 0xc099, 0x21, 0 - .dw 0xae40, 0xc099, 0xae7f, 0xc099, 0x21, 0 - .dw 0xaec0, 0xc099, 0xaeff, 0xc099, 0x21, 0 - .dw 0xaf40, 0xc099, 0xaf7f, 0xc099, 0x21, 0 - .dw 0xafc0, 0xc099, 0xafff, 0xc099, 0x21, 0 - .dw 0xb040, 0xc099, 0xb07f, 0xc099, 0x21, 0 - .dw 0xb0c0, 0xc099, 0xb0ff, 0xc099, 0x21, 0 - .dw 0xb140, 0xc099, 0xb17f, 0xc099, 0x21, 0 - .dw 0xb1c0, 0xc099, 0xb1ff, 0xc099, 0x21, 0 - .dw 0xb240, 0xc099, 0xb27f, 0xc099, 0x21, 0 - .dw 0xb2c0, 0xc099, 0xb2ff, 0xc099, 0x21, 0 - .dw 0xb340, 0xc099, 0xb37f, 0xc099, 0x21, 0 - .dw 0xb3c0, 0xc099, 0xb3ff, 0xc099, 0x21, 0 - .dw 0xb440, 0xc099, 0xb47f, 0xc099, 0x21, 0 - .dw 0xb4c0, 0xc099, 0xb4ff, 0xc099, 0x21, 0 - .dw 0xb540, 0xc099, 0xb57f, 0xc099, 0x21, 0 - .dw 0xb5c0, 0xc099, 0xb5ff, 0xc099, 0x21, 0 - .dw 0xb640, 0xc099, 0xb67f, 0xc099, 0x21, 0 - .dw 0xb6c0, 0xc099, 0xb6ff, 0xc099, 0x21, 0 - .dw 0xb740, 0xc099, 0xb77f, 0xc099, 0x21, 0 - .dw 0xb7c0, 0xc099, 0xb7ff, 0xc099, 0x21, 0 - .dw 0xb840, 0xc099, 0xb87f, 0xc099, 0x21, 0 - .dw 0xb8c0, 0xc099, 0xb8ff, 0xc099, 0x21, 0 - .dw 0xb940, 0xc099, 0xb97f, 0xc099, 0x21, 0 - .dw 0xb9c0, 0xc099, 0xdfff, 0xc099, 0x21, 0 - .dw 0xe040, 0xc099, 0xe07f, 0xc099, 0x21, 0 - .dw 0xe0c0, 0xc099, 0xe0ff, 0xc099, 0x21, 0 - .dw 0xe140, 0xc099, 0xe17f, 0xc099, 0x21, 0 - .dw 0xe1c0, 0xc099, 0xe1ff, 0xc099, 0x21, 0 - .dw 0xe240, 0xc099, 0xe27f, 0xc099, 0x21, 0 - .dw 0xe2c0, 0xc099, 0xe2ff, 0xc099, 0x21, 0 - .dw 0xe340, 0xc099, 0xe37f, 0xc099, 0x21, 0 - .dw 0xe3c0, 0xc099, 0xe3ff, 0xc099, 0x21, 0 - .dw 0xe440, 0xc099, 0xe47f, 0xc099, 0x21, 0 - .dw 0xe4c0, 0xc099, 0xe4ff, 0xc099, 0x21, 0 - .dw 0xe540, 0xc099, 0xe57f, 0xc099, 0x21, 0 - .dw 0xe5c0, 0xc099, 0xe5ff, 0xc099, 0x21, 0 - .dw 0xe640, 0xc099, 0xe67f, 0xc099, 0x21, 0 - .dw 0xe6c0, 0xc099, 0xe6ff, 0xc099, 0x21, 0 - .dw 0xe740, 0xc099, 0xe77f, 0xc099, 0x21, 0 - .dw 0xe7c0, 0xc099, 0xe7ff, 0xc099, 0x21, 0 - .dw 0xe840, 0xc099, 0xe87f, 0xc099, 0x21, 0 - .dw 0xe8c0, 0xc099, 0xe8ff, 0xc099, 0x21, 0 - .dw 0xe940, 0xc099, 0xe97f, 0xc099, 0x21, 0 - .dw 0xe9c0, 0xc099, 0xe9ff, 0xc099, 0x21, 0 - .dw 0xea40, 0xc099, 0xea7f, 0xc099, 0x21, 0 - .dw 0xeac0, 0xc099, 0xeaff, 0xc099, 0x21, 0 - .dw 0xeb40, 0xc099, 0xeb7f, 0xc099, 0x21, 0 - .dw 0xebc0, 0xc099, 0xebff, 0xc099, 0x21, 0 - .dw 0xec40, 0xc099, 0xec7f, 0xc099, 0x21, 0 - .dw 0xecc0, 0xc099, 0xecff, 0xc099, 0x21, 0 - .dw 0xed40, 0xc099, 0xed7f, 0xc099, 0x21, 0 - .dw 0xedc0, 0xc099, 0xedff, 0xc099, 0x21, 0 - .dw 0xee40, 0xc099, 0xee7f, 0xc099, 0x21, 0 - .dw 0xeec0, 0xc099, 0xeeff, 0xc099, 0x21, 0 - .dw 0xef40, 0xc099, 0xef7f, 0xc099, 0x21, 0 - .dw 0xefc0, 0xc099, 0xefff, 0xc099, 0x21, 0 - .dw 0xf040, 0xc099, 0xf07f, 0xc099, 0x21, 0 - .dw 0xf0c0, 0xc099, 0xf0ff, 0xc099, 0x21, 0 - .dw 0xf140, 0xc099, 0xf17f, 0xc099, 0x21, 0 - .dw 0xf1c0, 0xc099, 0xf1ff, 0xc099, 0x21, 0 - .dw 0xf240, 0xc099, 0xf27f, 0xc099, 0x21, 0 - .dw 0xf2c0, 0xc099, 0xf2ff, 0xc099, 0x21, 0 - .dw 0xf340, 0xc099, 0xf37f, 0xc099, 0x21, 0 - .dw 0xf3c0, 0xc099, 0xf3ff, 0xc099, 0x21, 0 - .dw 0xf440, 0xc099, 0xf47f, 0xc099, 0x21, 0 - .dw 0xf4c0, 0xc099, 0xf4ff, 0xc099, 0x21, 0 - .dw 0xf540, 0xc099, 0xf57f, 0xc099, 0x21, 0 - .dw 0xf5c0, 0xc099, 0xf5ff, 0xc099, 0x21, 0 - .dw 0xf640, 0xc099, 0xf67f, 0xc099, 0x21, 0 - .dw 0xf6c0, 0xc099, 0xf6ff, 0xc099, 0x21, 0 - .dw 0xf740, 0xc099, 0xf77f, 0xc099, 0x21, 0 - .dw 0xf7c0, 0xc099, 0xf7ff, 0xc099, 0x21, 0 - .dw 0xf840, 0xc099, 0xf87f, 0xc099, 0x21, 0 - .dw 0xf8c0, 0xc099, 0xf8ff, 0xc099, 0x21, 0 - .dw 0xf940, 0xc099, 0xf97f, 0xc099, 0x21, 0 - .dw 0xf9c0, 0xc099, 0x1fff, 0xc09a, 0x21, 0 - .dw 0x2040, 0xc09a, 0x207f, 0xc09a, 0x21, 0 - .dw 0x20c0, 0xc09a, 0x20ff, 0xc09a, 0x21, 0 - .dw 0x2140, 0xc09a, 0x217f, 0xc09a, 0x21, 0 - .dw 0x21c0, 0xc09a, 0x21ff, 0xc09a, 0x21, 0 - .dw 0x2240, 0xc09a, 0x227f, 0xc09a, 0x21, 0 - .dw 0x22c0, 0xc09a, 0x22ff, 0xc09a, 0x21, 0 - .dw 0x2340, 0xc09a, 0x237f, 0xc09a, 0x21, 0 - .dw 0x23c0, 0xc09a, 0x23ff, 0xc09a, 0x21, 0 - .dw 0x2440, 0xc09a, 0x247f, 0xc09a, 0x21, 0 - .dw 0x24c0, 0xc09a, 0x24ff, 0xc09a, 0x21, 0 - .dw 0x2540, 0xc09a, 0x257f, 0xc09a, 0x21, 0 - .dw 0x25c0, 0xc09a, 0x25ff, 0xc09a, 0x21, 0 - .dw 0x2640, 0xc09a, 0x267f, 0xc09a, 0x21, 0 - .dw 0x26c0, 0xc09a, 0x26ff, 0xc09a, 0x21, 0 - .dw 0x2740, 0xc09a, 0x277f, 0xc09a, 0x21, 0 - .dw 0x27c0, 0xc09a, 0x27ff, 0xc09a, 0x21, 0 - .dw 0x2840, 0xc09a, 0x287f, 0xc09a, 0x21, 0 - .dw 0x28c0, 0xc09a, 0x28ff, 0xc09a, 0x21, 0 - .dw 0x2940, 0xc09a, 0x297f, 0xc09a, 0x21, 0 - .dw 0x29c0, 0xc09a, 0x29ff, 0xc09a, 0x21, 0 - .dw 0x2a40, 0xc09a, 0x2a7f, 0xc09a, 0x21, 0 - .dw 0x2ac0, 0xc09a, 0x2aff, 0xc09a, 0x21, 0 - .dw 0x2b40, 0xc09a, 0x2b7f, 0xc09a, 0x21, 0 - .dw 0x2bc0, 0xc09a, 0x2bff, 0xc09a, 0x21, 0 - .dw 0x2c40, 0xc09a, 0x2c7f, 0xc09a, 0x21, 0 - .dw 0x2cc0, 0xc09a, 0x2cff, 0xc09a, 0x21, 0 - .dw 0x2d40, 0xc09a, 0x2d7f, 0xc09a, 0x21, 0 - .dw 0x2dc0, 0xc09a, 0x2dff, 0xc09a, 0x21, 0 - .dw 0x2e40, 0xc09a, 0x2e7f, 0xc09a, 0x21, 0 - .dw 0x2ec0, 0xc09a, 0x2eff, 0xc09a, 0x21, 0 - .dw 0x2f40, 0xc09a, 0x2f7f, 0xc09a, 0x21, 0 - .dw 0x2fc0, 0xc09a, 0x2fff, 0xc09a, 0x21, 0 - .dw 0x3040, 0xc09a, 0x307f, 0xc09a, 0x21, 0 - .dw 0x30c0, 0xc09a, 0x30ff, 0xc09a, 0x21, 0 - .dw 0x3140, 0xc09a, 0x317f, 0xc09a, 0x21, 0 - .dw 0x31c0, 0xc09a, 0x31ff, 0xc09a, 0x21, 0 - .dw 0x3240, 0xc09a, 0x327f, 0xc09a, 0x21, 0 - .dw 0x32c0, 0xc09a, 0x32ff, 0xc09a, 0x21, 0 - .dw 0x3340, 0xc09a, 0x337f, 0xc09a, 0x21, 0 - .dw 0x33c0, 0xc09a, 0x33ff, 0xc09a, 0x21, 0 - .dw 0x3440, 0xc09a, 0x347f, 0xc09a, 0x21, 0 - .dw 0x34c0, 0xc09a, 0x34ff, 0xc09a, 0x21, 0 - .dw 0x3540, 0xc09a, 0x357f, 0xc09a, 0x21, 0 - .dw 0x35c0, 0xc09a, 0x35ff, 0xc09a, 0x21, 0 - .dw 0x3640, 0xc09a, 0x367f, 0xc09a, 0x21, 0 - .dw 0x36c0, 0xc09a, 0x36ff, 0xc09a, 0x21, 0 - .dw 0x3740, 0xc09a, 0x377f, 0xc09a, 0x21, 0 - .dw 0x37c0, 0xc09a, 0x37ff, 0xc09a, 0x21, 0 - .dw 0x3840, 0xc09a, 0x387f, 0xc09a, 0x21, 0 - .dw 0x38c0, 0xc09a, 0x38ff, 0xc09a, 0x21, 0 - .dw 0x3940, 0xc09a, 0x397f, 0xc09a, 0x21, 0 - .dw 0x39c0, 0xc09a, 0x5fff, 0xc09a, 0x21, 0 - .dw 0x6040, 0xc09a, 0x607f, 0xc09a, 0x21, 0 - .dw 0x60c0, 0xc09a, 0x60ff, 0xc09a, 0x21, 0 - .dw 0x6140, 0xc09a, 0x617f, 0xc09a, 0x21, 0 - .dw 0x61c0, 0xc09a, 0x61ff, 0xc09a, 0x21, 0 - .dw 0x6240, 0xc09a, 0x627f, 0xc09a, 0x21, 0 - .dw 0x62c0, 0xc09a, 0x62ff, 0xc09a, 0x21, 0 - .dw 0x6340, 0xc09a, 0x637f, 0xc09a, 0x21, 0 - .dw 0x63c0, 0xc09a, 0x63ff, 0xc09a, 0x21, 0 - .dw 0x6440, 0xc09a, 0x647f, 0xc09a, 0x21, 0 - .dw 0x64c0, 0xc09a, 0x64ff, 0xc09a, 0x21, 0 - .dw 0x6540, 0xc09a, 0x657f, 0xc09a, 0x21, 0 - .dw 0x65c0, 0xc09a, 0x65ff, 0xc09a, 0x21, 0 - .dw 0x6640, 0xc09a, 0x667f, 0xc09a, 0x21, 0 - .dw 0x66c0, 0xc09a, 0x66ff, 0xc09a, 0x21, 0 - .dw 0x6740, 0xc09a, 0x677f, 0xc09a, 0x21, 0 - .dw 0x67c0, 0xc09a, 0x67ff, 0xc09a, 0x21, 0 - .dw 0x6840, 0xc09a, 0x687f, 0xc09a, 0x21, 0 - .dw 0x68c0, 0xc09a, 0x68ff, 0xc09a, 0x21, 0 - .dw 0x6940, 0xc09a, 0x697f, 0xc09a, 0x21, 0 - .dw 0x69c0, 0xc09a, 0x69ff, 0xc09a, 0x21, 0 - .dw 0x6a40, 0xc09a, 0x6a7f, 0xc09a, 0x21, 0 - .dw 0x6ac0, 0xc09a, 0x6aff, 0xc09a, 0x21, 0 - .dw 0x6b40, 0xc09a, 0x6b7f, 0xc09a, 0x21, 0 - .dw 0x6bc0, 0xc09a, 0x6bff, 0xc09a, 0x21, 0 - .dw 0x6c40, 0xc09a, 0x6c7f, 0xc09a, 0x21, 0 - .dw 0x6cc0, 0xc09a, 0x6cff, 0xc09a, 0x21, 0 - .dw 0x6d40, 0xc09a, 0x6d7f, 0xc09a, 0x21, 0 - .dw 0x6dc0, 0xc09a, 0x6dff, 0xc09a, 0x21, 0 - .dw 0x6e40, 0xc09a, 0x6e7f, 0xc09a, 0x21, 0 - .dw 0x6ec0, 0xc09a, 0x6eff, 0xc09a, 0x21, 0 - .dw 0x6f40, 0xc09a, 0x6f7f, 0xc09a, 0x21, 0 - .dw 0x6fc0, 0xc09a, 0x6fff, 0xc09a, 0x21, 0 - .dw 0x7040, 0xc09a, 0x707f, 0xc09a, 0x21, 0 - .dw 0x70c0, 0xc09a, 0x70ff, 0xc09a, 0x21, 0 - .dw 0x7140, 0xc09a, 0x717f, 0xc09a, 0x21, 0 - .dw 0x71c0, 0xc09a, 0x71ff, 0xc09a, 0x21, 0 - .dw 0x7240, 0xc09a, 0x727f, 0xc09a, 0x21, 0 - .dw 0x72c0, 0xc09a, 0x72ff, 0xc09a, 0x21, 0 - .dw 0x7340, 0xc09a, 0x737f, 0xc09a, 0x21, 0 - .dw 0x73c0, 0xc09a, 0x73ff, 0xc09a, 0x21, 0 - .dw 0x7440, 0xc09a, 0x747f, 0xc09a, 0x21, 0 - .dw 0x74c0, 0xc09a, 0x74ff, 0xc09a, 0x21, 0 - .dw 0x7540, 0xc09a, 0x757f, 0xc09a, 0x21, 0 - .dw 0x75c0, 0xc09a, 0x75ff, 0xc09a, 0x21, 0 - .dw 0x7640, 0xc09a, 0x767f, 0xc09a, 0x21, 0 - .dw 0x76c0, 0xc09a, 0x76ff, 0xc09a, 0x21, 0 - .dw 0x7740, 0xc09a, 0x777f, 0xc09a, 0x21, 0 - .dw 0x77c0, 0xc09a, 0x77ff, 0xc09a, 0x21, 0 - .dw 0x7840, 0xc09a, 0x787f, 0xc09a, 0x21, 0 - .dw 0x78c0, 0xc09a, 0x78ff, 0xc09a, 0x21, 0 - .dw 0x7940, 0xc09a, 0x797f, 0xc09a, 0x21, 0 - .dw 0x79c0, 0xc09a, 0x9fff, 0xc09a, 0x21, 0 - .dw 0xa040, 0xc09a, 0xa07f, 0xc09a, 0x21, 0 - .dw 0xa0c0, 0xc09a, 0xa0ff, 0xc09a, 0x21, 0 - .dw 0xa140, 0xc09a, 0xa17f, 0xc09a, 0x21, 0 - .dw 0xa1c0, 0xc09a, 0xa1ff, 0xc09a, 0x21, 0 - .dw 0xa240, 0xc09a, 0xa27f, 0xc09a, 0x21, 0 - .dw 0xa2c0, 0xc09a, 0xa2ff, 0xc09a, 0x21, 0 - .dw 0xa340, 0xc09a, 0xa37f, 0xc09a, 0x21, 0 - .dw 0xa3c0, 0xc09a, 0xa3ff, 0xc09a, 0x21, 0 - .dw 0xa440, 0xc09a, 0xa47f, 0xc09a, 0x21, 0 - .dw 0xa4c0, 0xc09a, 0xa4ff, 0xc09a, 0x21, 0 - .dw 0xa540, 0xc09a, 0xa57f, 0xc09a, 0x21, 0 - .dw 0xa5c0, 0xc09a, 0xa5ff, 0xc09a, 0x21, 0 - .dw 0xa640, 0xc09a, 0xa67f, 0xc09a, 0x21, 0 - .dw 0xa6c0, 0xc09a, 0xa6ff, 0xc09a, 0x21, 0 - .dw 0xa740, 0xc09a, 0xa77f, 0xc09a, 0x21, 0 - .dw 0xa7c0, 0xc09a, 0xa7ff, 0xc09a, 0x21, 0 - .dw 0xa840, 0xc09a, 0xa87f, 0xc09a, 0x21, 0 - .dw 0xa8c0, 0xc09a, 0xa8ff, 0xc09a, 0x21, 0 - .dw 0xa940, 0xc09a, 0xa97f, 0xc09a, 0x21, 0 - .dw 0xa9c0, 0xc09a, 0xa9ff, 0xc09a, 0x21, 0 - .dw 0xaa40, 0xc09a, 0xaa7f, 0xc09a, 0x21, 0 - .dw 0xaac0, 0xc09a, 0xaaff, 0xc09a, 0x21, 0 - .dw 0xab40, 0xc09a, 0xab7f, 0xc09a, 0x21, 0 - .dw 0xabc0, 0xc09a, 0xabff, 0xc09a, 0x21, 0 - .dw 0xac40, 0xc09a, 0xac7f, 0xc09a, 0x21, 0 - .dw 0xacc0, 0xc09a, 0xacff, 0xc09a, 0x21, 0 - .dw 0xad40, 0xc09a, 0xad7f, 0xc09a, 0x21, 0 - .dw 0xadc0, 0xc09a, 0xadff, 0xc09a, 0x21, 0 - .dw 0xae40, 0xc09a, 0xae7f, 0xc09a, 0x21, 0 - .dw 0xaec0, 0xc09a, 0xaeff, 0xc09a, 0x21, 0 - .dw 0xaf40, 0xc09a, 0xaf7f, 0xc09a, 0x21, 0 - .dw 0xafc0, 0xc09a, 0xafff, 0xc09a, 0x21, 0 - .dw 0xb040, 0xc09a, 0xb07f, 0xc09a, 0x21, 0 - .dw 0xb0c0, 0xc09a, 0xb0ff, 0xc09a, 0x21, 0 - .dw 0xb140, 0xc09a, 0xb17f, 0xc09a, 0x21, 0 - .dw 0xb1c0, 0xc09a, 0xb1ff, 0xc09a, 0x21, 0 - .dw 0xb240, 0xc09a, 0xb27f, 0xc09a, 0x21, 0 - .dw 0xb2c0, 0xc09a, 0xb2ff, 0xc09a, 0x21, 0 - .dw 0xb340, 0xc09a, 0xb37f, 0xc09a, 0x21, 0 - .dw 0xb3c0, 0xc09a, 0xb3ff, 0xc09a, 0x21, 0 - .dw 0xb440, 0xc09a, 0xb47f, 0xc09a, 0x21, 0 - .dw 0xb4c0, 0xc09a, 0xb4ff, 0xc09a, 0x21, 0 - .dw 0xb540, 0xc09a, 0xb57f, 0xc09a, 0x21, 0 - .dw 0xb5c0, 0xc09a, 0xb5ff, 0xc09a, 0x21, 0 - .dw 0xb640, 0xc09a, 0xb67f, 0xc09a, 0x21, 0 - .dw 0xb6c0, 0xc09a, 0xb6ff, 0xc09a, 0x21, 0 - .dw 0xb740, 0xc09a, 0xb77f, 0xc09a, 0x21, 0 - .dw 0xb7c0, 0xc09a, 0xb7ff, 0xc09a, 0x21, 0 - .dw 0xb840, 0xc09a, 0xb87f, 0xc09a, 0x21, 0 - .dw 0xb8c0, 0xc09a, 0xb8ff, 0xc09a, 0x21, 0 - .dw 0xb940, 0xc09a, 0xb97f, 0xc09a, 0x21, 0 - .dw 0xb9c0, 0xc09a, 0xdfff, 0xc09a, 0x21, 0 - .dw 0xe040, 0xc09a, 0xe07f, 0xc09a, 0x21, 0 - .dw 0xe0c0, 0xc09a, 0xe0ff, 0xc09a, 0x21, 0 - .dw 0xe140, 0xc09a, 0xe17f, 0xc09a, 0x21, 0 - .dw 0xe1c0, 0xc09a, 0xe1ff, 0xc09a, 0x21, 0 - .dw 0xe240, 0xc09a, 0xe27f, 0xc09a, 0x21, 0 - .dw 0xe2c0, 0xc09a, 0xe2ff, 0xc09a, 0x21, 0 - .dw 0xe340, 0xc09a, 0xe37f, 0xc09a, 0x21, 0 - .dw 0xe3c0, 0xc09a, 0xe3ff, 0xc09a, 0x21, 0 - .dw 0xe440, 0xc09a, 0xe47f, 0xc09a, 0x21, 0 - .dw 0xe4c0, 0xc09a, 0xe4ff, 0xc09a, 0x21, 0 - .dw 0xe540, 0xc09a, 0xe57f, 0xc09a, 0x21, 0 - .dw 0xe5c0, 0xc09a, 0xe5ff, 0xc09a, 0x21, 0 - .dw 0xe640, 0xc09a, 0xe67f, 0xc09a, 0x21, 0 - .dw 0xe6c0, 0xc09a, 0xe6ff, 0xc09a, 0x21, 0 - .dw 0xe740, 0xc09a, 0xe77f, 0xc09a, 0x21, 0 - .dw 0xe7c0, 0xc09a, 0xe7ff, 0xc09a, 0x21, 0 - .dw 0xe840, 0xc09a, 0xe87f, 0xc09a, 0x21, 0 - .dw 0xe8c0, 0xc09a, 0xe8ff, 0xc09a, 0x21, 0 - .dw 0xe940, 0xc09a, 0xe97f, 0xc09a, 0x21, 0 - .dw 0xe9c0, 0xc09a, 0xe9ff, 0xc09a, 0x21, 0 - .dw 0xea40, 0xc09a, 0xea7f, 0xc09a, 0x21, 0 - .dw 0xeac0, 0xc09a, 0xeaff, 0xc09a, 0x21, 0 - .dw 0xeb40, 0xc09a, 0xeb7f, 0xc09a, 0x21, 0 - .dw 0xebc0, 0xc09a, 0xebff, 0xc09a, 0x21, 0 - .dw 0xec40, 0xc09a, 0xec7f, 0xc09a, 0x21, 0 - .dw 0xecc0, 0xc09a, 0xecff, 0xc09a, 0x21, 0 - .dw 0xed40, 0xc09a, 0xed7f, 0xc09a, 0x21, 0 - .dw 0xedc0, 0xc09a, 0xedff, 0xc09a, 0x21, 0 - .dw 0xee40, 0xc09a, 0xee7f, 0xc09a, 0x21, 0 - .dw 0xeec0, 0xc09a, 0xeeff, 0xc09a, 0x21, 0 - .dw 0xef40, 0xc09a, 0xef7f, 0xc09a, 0x21, 0 - .dw 0xefc0, 0xc09a, 0xefff, 0xc09a, 0x21, 0 - .dw 0xf040, 0xc09a, 0xf07f, 0xc09a, 0x21, 0 - .dw 0xf0c0, 0xc09a, 0xf0ff, 0xc09a, 0x21, 0 - .dw 0xf140, 0xc09a, 0xf17f, 0xc09a, 0x21, 0 - .dw 0xf1c0, 0xc09a, 0xf1ff, 0xc09a, 0x21, 0 - .dw 0xf240, 0xc09a, 0xf27f, 0xc09a, 0x21, 0 - .dw 0xf2c0, 0xc09a, 0xf2ff, 0xc09a, 0x21, 0 - .dw 0xf340, 0xc09a, 0xf37f, 0xc09a, 0x21, 0 - .dw 0xf3c0, 0xc09a, 0xf3ff, 0xc09a, 0x21, 0 - .dw 0xf440, 0xc09a, 0xf47f, 0xc09a, 0x21, 0 - .dw 0xf4c0, 0xc09a, 0xf4ff, 0xc09a, 0x21, 0 - .dw 0xf540, 0xc09a, 0xf57f, 0xc09a, 0x21, 0 - .dw 0xf5c0, 0xc09a, 0xf5ff, 0xc09a, 0x21, 0 - .dw 0xf640, 0xc09a, 0xf67f, 0xc09a, 0x21, 0 - .dw 0xf6c0, 0xc09a, 0xf6ff, 0xc09a, 0x21, 0 - .dw 0xf740, 0xc09a, 0xf77f, 0xc09a, 0x21, 0 - .dw 0xf7c0, 0xc09a, 0xf7ff, 0xc09a, 0x21, 0 - .dw 0xf840, 0xc09a, 0xf87f, 0xc09a, 0x21, 0 - .dw 0xf8c0, 0xc09a, 0xf8ff, 0xc09a, 0x21, 0 - .dw 0xf940, 0xc09a, 0xf97f, 0xc09a, 0x21, 0 - .dw 0xf9c0, 0xc09a, 0xffff, 0xc09b, 0x21, 0 - .dw 0x0040, 0xc09c, 0x007f, 0xc09c, 0x21, 0 - .dw 0x00c0, 0xc09c, 0x00ff, 0xc09c, 0x21, 0 - .dw 0x0140, 0xc09c, 0x017f, 0xc09c, 0x21, 0 - .dw 0x01c0, 0xc09c, 0x01ff, 0xc09c, 0x21, 0 - .dw 0x0240, 0xc09c, 0x027f, 0xc09c, 0x21, 0 - .dw 0x02c0, 0xc09c, 0x02ff, 0xc09c, 0x21, 0 - .dw 0x0340, 0xc09c, 0x037f, 0xc09c, 0x21, 0 - .dw 0x03c0, 0xc09c, 0x03ff, 0xc09c, 0x21, 0 - .dw 0x0440, 0xc09c, 0x047f, 0xc09c, 0x21, 0 - .dw 0x04c0, 0xc09c, 0x04ff, 0xc09c, 0x21, 0 - .dw 0x0540, 0xc09c, 0x057f, 0xc09c, 0x21, 0 - .dw 0x05c0, 0xc09c, 0x05ff, 0xc09c, 0x21, 0 - .dw 0x0640, 0xc09c, 0x067f, 0xc09c, 0x21, 0 - .dw 0x06c0, 0xc09c, 0x06ff, 0xc09c, 0x21, 0 - .dw 0x0740, 0xc09c, 0x077f, 0xc09c, 0x21, 0 - .dw 0x07c0, 0xc09c, 0x07ff, 0xc09c, 0x21, 0 - .dw 0x0840, 0xc09c, 0x087f, 0xc09c, 0x21, 0 - .dw 0x08c0, 0xc09c, 0x08ff, 0xc09c, 0x21, 0 - .dw 0x0940, 0xc09c, 0x097f, 0xc09c, 0x21, 0 - .dw 0x09c0, 0xc09c, 0x09ff, 0xc09c, 0x21, 0 - .dw 0x0a40, 0xc09c, 0x0a7f, 0xc09c, 0x21, 0 - .dw 0x0ac0, 0xc09c, 0x0aff, 0xc09c, 0x21, 0 - .dw 0x0b40, 0xc09c, 0x0b7f, 0xc09c, 0x21, 0 - .dw 0x0bc0, 0xc09c, 0x0bff, 0xc09c, 0x21, 0 - .dw 0x0c40, 0xc09c, 0x0c7f, 0xc09c, 0x21, 0 - .dw 0x0cc0, 0xc09c, 0x0cff, 0xc09c, 0x21, 0 - .dw 0x0d40, 0xc09c, 0x0d7f, 0xc09c, 0x21, 0 - .dw 0x0dc0, 0xc09c, 0x0dff, 0xc09c, 0x21, 0 - .dw 0x0e40, 0xc09c, 0x0e7f, 0xc09c, 0x21, 0 - .dw 0x0ec0, 0xc09c, 0x0eff, 0xc09c, 0x21, 0 - .dw 0x0f40, 0xc09c, 0x0f7f, 0xc09c, 0x21, 0 - .dw 0x0fc0, 0xc09c, 0x0fff, 0xc09c, 0x21, 0 - .dw 0x1040, 0xc09c, 0x107f, 0xc09c, 0x21, 0 - .dw 0x10c0, 0xc09c, 0x10ff, 0xc09c, 0x21, 0 - .dw 0x1140, 0xc09c, 0x117f, 0xc09c, 0x21, 0 - .dw 0x11c0, 0xc09c, 0x11ff, 0xc09c, 0x21, 0 - .dw 0x1240, 0xc09c, 0x127f, 0xc09c, 0x21, 0 - .dw 0x12c0, 0xc09c, 0x12ff, 0xc09c, 0x21, 0 - .dw 0x1340, 0xc09c, 0x137f, 0xc09c, 0x21, 0 - .dw 0x13c0, 0xc09c, 0x13ff, 0xc09c, 0x21, 0 - .dw 0x1440, 0xc09c, 0x147f, 0xc09c, 0x21, 0 - .dw 0x14c0, 0xc09c, 0x14ff, 0xc09c, 0x21, 0 - .dw 0x1540, 0xc09c, 0x157f, 0xc09c, 0x21, 0 - .dw 0x15c0, 0xc09c, 0x15ff, 0xc09c, 0x21, 0 - .dw 0x1640, 0xc09c, 0x167f, 0xc09c, 0x21, 0 - .dw 0x16c0, 0xc09c, 0x16ff, 0xc09c, 0x21, 0 - .dw 0x1740, 0xc09c, 0x177f, 0xc09c, 0x21, 0 - .dw 0x17c0, 0xc09c, 0x17ff, 0xc09c, 0x21, 0 - .dw 0x1840, 0xc09c, 0x187f, 0xc09c, 0x21, 0 - .dw 0x18c0, 0xc09c, 0x18ff, 0xc09c, 0x21, 0 - .dw 0x1940, 0xc09c, 0x197f, 0xc09c, 0x21, 0 - .dw 0x19c0, 0xc09c, 0x1fff, 0xc09c, 0x21, 0 - .dw 0x2040, 0xc09c, 0x207f, 0xc09c, 0x21, 0 - .dw 0x20c0, 0xc09c, 0x20ff, 0xc09c, 0x21, 0 - .dw 0x2140, 0xc09c, 0x217f, 0xc09c, 0x21, 0 - .dw 0x21c0, 0xc09c, 0x21ff, 0xc09c, 0x21, 0 - .dw 0x2240, 0xc09c, 0x227f, 0xc09c, 0x21, 0 - .dw 0x22c0, 0xc09c, 0x22ff, 0xc09c, 0x21, 0 - .dw 0x2340, 0xc09c, 0x237f, 0xc09c, 0x21, 0 - .dw 0x23c0, 0xc09c, 0x23ff, 0xc09c, 0x21, 0 - .dw 0x2440, 0xc09c, 0x247f, 0xc09c, 0x21, 0 - .dw 0x24c0, 0xc09c, 0x24ff, 0xc09c, 0x21, 0 - .dw 0x2540, 0xc09c, 0x257f, 0xc09c, 0x21, 0 - .dw 0x25c0, 0xc09c, 0x25ff, 0xc09c, 0x21, 0 - .dw 0x2640, 0xc09c, 0x267f, 0xc09c, 0x21, 0 - .dw 0x26c0, 0xc09c, 0x26ff, 0xc09c, 0x21, 0 - .dw 0x2740, 0xc09c, 0x277f, 0xc09c, 0x21, 0 - .dw 0x27c0, 0xc09c, 0x27ff, 0xc09c, 0x21, 0 - .dw 0x2840, 0xc09c, 0x287f, 0xc09c, 0x21, 0 - .dw 0x28c0, 0xc09c, 0x28ff, 0xc09c, 0x21, 0 - .dw 0x2940, 0xc09c, 0x297f, 0xc09c, 0x21, 0 - .dw 0x29c0, 0xc09c, 0x29ff, 0xc09c, 0x21, 0 - .dw 0x2a40, 0xc09c, 0x2a7f, 0xc09c, 0x21, 0 - .dw 0x2ac0, 0xc09c, 0x2aff, 0xc09c, 0x21, 0 - .dw 0x2b40, 0xc09c, 0x2b7f, 0xc09c, 0x21, 0 - .dw 0x2bc0, 0xc09c, 0x2bff, 0xc09c, 0x21, 0 - .dw 0x2c40, 0xc09c, 0x2c7f, 0xc09c, 0x21, 0 - .dw 0x2cc0, 0xc09c, 0x2cff, 0xc09c, 0x21, 0 - .dw 0x2d40, 0xc09c, 0x2d7f, 0xc09c, 0x21, 0 - .dw 0x2dc0, 0xc09c, 0x2dff, 0xc09c, 0x21, 0 - .dw 0x2e40, 0xc09c, 0x2e7f, 0xc09c, 0x21, 0 - .dw 0x2ec0, 0xc09c, 0x2eff, 0xc09c, 0x21, 0 - .dw 0x2f40, 0xc09c, 0x2f7f, 0xc09c, 0x21, 0 - .dw 0x2fc0, 0xc09c, 0x2fff, 0xc09c, 0x21, 0 - .dw 0x3040, 0xc09c, 0x307f, 0xc09c, 0x21, 0 - .dw 0x30c0, 0xc09c, 0x30ff, 0xc09c, 0x21, 0 - .dw 0x3140, 0xc09c, 0x317f, 0xc09c, 0x21, 0 - .dw 0x31c0, 0xc09c, 0x31ff, 0xc09c, 0x21, 0 - .dw 0x3240, 0xc09c, 0x327f, 0xc09c, 0x21, 0 - .dw 0x32c0, 0xc09c, 0x32ff, 0xc09c, 0x21, 0 - .dw 0x3340, 0xc09c, 0x337f, 0xc09c, 0x21, 0 - .dw 0x33c0, 0xc09c, 0x33ff, 0xc09c, 0x21, 0 - .dw 0x3440, 0xc09c, 0x347f, 0xc09c, 0x21, 0 - .dw 0x34c0, 0xc09c, 0x34ff, 0xc09c, 0x21, 0 - .dw 0x3540, 0xc09c, 0x357f, 0xc09c, 0x21, 0 - .dw 0x35c0, 0xc09c, 0x35ff, 0xc09c, 0x21, 0 - .dw 0x3640, 0xc09c, 0x367f, 0xc09c, 0x21, 0 - .dw 0x36c0, 0xc09c, 0x36ff, 0xc09c, 0x21, 0 - .dw 0x3740, 0xc09c, 0x377f, 0xc09c, 0x21, 0 - .dw 0x37c0, 0xc09c, 0x37ff, 0xc09c, 0x21, 0 - .dw 0x3840, 0xc09c, 0x387f, 0xc09c, 0x21, 0 - .dw 0x38c0, 0xc09c, 0x38ff, 0xc09c, 0x21, 0 - .dw 0x3940, 0xc09c, 0x397f, 0xc09c, 0x21, 0 - .dw 0x39c0, 0xc09c, 0x3fff, 0xc09c, 0x21, 0 - .dw 0x4040, 0xc09c, 0x407f, 0xc09c, 0x21, 0 - .dw 0x40c0, 0xc09c, 0x40ff, 0xc09c, 0x21, 0 - .dw 0x4140, 0xc09c, 0x417f, 0xc09c, 0x21, 0 - .dw 0x41c0, 0xc09c, 0x41ff, 0xc09c, 0x21, 0 - .dw 0x4240, 0xc09c, 0x427f, 0xc09c, 0x21, 0 - .dw 0x42c0, 0xc09c, 0x42ff, 0xc09c, 0x21, 0 - .dw 0x4340, 0xc09c, 0x437f, 0xc09c, 0x21, 0 - .dw 0x43c0, 0xc09c, 0x43ff, 0xc09c, 0x21, 0 - .dw 0x4440, 0xc09c, 0x447f, 0xc09c, 0x21, 0 - .dw 0x44c0, 0xc09c, 0x44ff, 0xc09c, 0x21, 0 - .dw 0x4540, 0xc09c, 0x457f, 0xc09c, 0x21, 0 - .dw 0x45c0, 0xc09c, 0x45ff, 0xc09c, 0x21, 0 - .dw 0x4640, 0xc09c, 0x467f, 0xc09c, 0x21, 0 - .dw 0x46c0, 0xc09c, 0x46ff, 0xc09c, 0x21, 0 - .dw 0x4740, 0xc09c, 0x477f, 0xc09c, 0x21, 0 - .dw 0x47c0, 0xc09c, 0x47ff, 0xc09c, 0x21, 0 - .dw 0x4840, 0xc09c, 0x487f, 0xc09c, 0x21, 0 - .dw 0x48c0, 0xc09c, 0x48ff, 0xc09c, 0x21, 0 - .dw 0x4940, 0xc09c, 0x497f, 0xc09c, 0x21, 0 - .dw 0x49c0, 0xc09c, 0x49ff, 0xc09c, 0x21, 0 - .dw 0x4a40, 0xc09c, 0x4a7f, 0xc09c, 0x21, 0 - .dw 0x4ac0, 0xc09c, 0x4aff, 0xc09c, 0x21, 0 - .dw 0x4b40, 0xc09c, 0x4b7f, 0xc09c, 0x21, 0 - .dw 0x4bc0, 0xc09c, 0x4bff, 0xc09c, 0x21, 0 - .dw 0x4c40, 0xc09c, 0x4c7f, 0xc09c, 0x21, 0 - .dw 0x4cc0, 0xc09c, 0x4cff, 0xc09c, 0x21, 0 - .dw 0x4d40, 0xc09c, 0x4d7f, 0xc09c, 0x21, 0 - .dw 0x4dc0, 0xc09c, 0x4dff, 0xc09c, 0x21, 0 - .dw 0x4e40, 0xc09c, 0x4e7f, 0xc09c, 0x21, 0 - .dw 0x4ec0, 0xc09c, 0x4eff, 0xc09c, 0x21, 0 - .dw 0x4f40, 0xc09c, 0x4f7f, 0xc09c, 0x21, 0 - .dw 0x4fc0, 0xc09c, 0x4fff, 0xc09c, 0x21, 0 - .dw 0x5040, 0xc09c, 0x507f, 0xc09c, 0x21, 0 - .dw 0x50c0, 0xc09c, 0x50ff, 0xc09c, 0x21, 0 - .dw 0x5140, 0xc09c, 0x517f, 0xc09c, 0x21, 0 - .dw 0x51c0, 0xc09c, 0x51ff, 0xc09c, 0x21, 0 - .dw 0x5240, 0xc09c, 0x527f, 0xc09c, 0x21, 0 - .dw 0x52c0, 0xc09c, 0x52ff, 0xc09c, 0x21, 0 - .dw 0x5340, 0xc09c, 0x537f, 0xc09c, 0x21, 0 - .dw 0x53c0, 0xc09c, 0x53ff, 0xc09c, 0x21, 0 - .dw 0x5440, 0xc09c, 0x547f, 0xc09c, 0x21, 0 - .dw 0x54c0, 0xc09c, 0x54ff, 0xc09c, 0x21, 0 - .dw 0x5540, 0xc09c, 0x557f, 0xc09c, 0x21, 0 - .dw 0x55c0, 0xc09c, 0x55ff, 0xc09c, 0x21, 0 - .dw 0x5640, 0xc09c, 0x567f, 0xc09c, 0x21, 0 - .dw 0x56c0, 0xc09c, 0x56ff, 0xc09c, 0x21, 0 - .dw 0x5740, 0xc09c, 0x577f, 0xc09c, 0x21, 0 - .dw 0x57c0, 0xc09c, 0x57ff, 0xc09c, 0x21, 0 - .dw 0x5840, 0xc09c, 0x587f, 0xc09c, 0x21, 0 - .dw 0x58c0, 0xc09c, 0x58ff, 0xc09c, 0x21, 0 - .dw 0x5940, 0xc09c, 0x597f, 0xc09c, 0x21, 0 - .dw 0x59c0, 0xc09c, 0x5fff, 0xc09c, 0x21, 0 - .dw 0x6040, 0xc09c, 0x607f, 0xc09c, 0x21, 0 - .dw 0x60c0, 0xc09c, 0x60ff, 0xc09c, 0x21, 0 - .dw 0x6140, 0xc09c, 0x617f, 0xc09c, 0x21, 0 - .dw 0x61c0, 0xc09c, 0x61ff, 0xc09c, 0x21, 0 - .dw 0x6240, 0xc09c, 0x627f, 0xc09c, 0x21, 0 - .dw 0x62c0, 0xc09c, 0x62ff, 0xc09c, 0x21, 0 - .dw 0x6340, 0xc09c, 0x637f, 0xc09c, 0x21, 0 - .dw 0x63c0, 0xc09c, 0x63ff, 0xc09c, 0x21, 0 - .dw 0x6440, 0xc09c, 0x647f, 0xc09c, 0x21, 0 - .dw 0x64c0, 0xc09c, 0x64ff, 0xc09c, 0x21, 0 - .dw 0x6540, 0xc09c, 0x657f, 0xc09c, 0x21, 0 - .dw 0x65c0, 0xc09c, 0x65ff, 0xc09c, 0x21, 0 - .dw 0x6640, 0xc09c, 0x667f, 0xc09c, 0x21, 0 - .dw 0x66c0, 0xc09c, 0x66ff, 0xc09c, 0x21, 0 - .dw 0x6740, 0xc09c, 0x677f, 0xc09c, 0x21, 0 - .dw 0x67c0, 0xc09c, 0x67ff, 0xc09c, 0x21, 0 - .dw 0x6840, 0xc09c, 0x687f, 0xc09c, 0x21, 0 - .dw 0x68c0, 0xc09c, 0x68ff, 0xc09c, 0x21, 0 - .dw 0x6940, 0xc09c, 0x697f, 0xc09c, 0x21, 0 - .dw 0x69c0, 0xc09c, 0x69ff, 0xc09c, 0x21, 0 - .dw 0x6a40, 0xc09c, 0x6a7f, 0xc09c, 0x21, 0 - .dw 0x6ac0, 0xc09c, 0x6aff, 0xc09c, 0x21, 0 - .dw 0x6b40, 0xc09c, 0x6b7f, 0xc09c, 0x21, 0 - .dw 0x6bc0, 0xc09c, 0x6bff, 0xc09c, 0x21, 0 - .dw 0x6c40, 0xc09c, 0x6c7f, 0xc09c, 0x21, 0 - .dw 0x6cc0, 0xc09c, 0x6cff, 0xc09c, 0x21, 0 - .dw 0x6d40, 0xc09c, 0x6d7f, 0xc09c, 0x21, 0 - .dw 0x6dc0, 0xc09c, 0x6dff, 0xc09c, 0x21, 0 - .dw 0x6e40, 0xc09c, 0x6e7f, 0xc09c, 0x21, 0 - .dw 0x6ec0, 0xc09c, 0x6eff, 0xc09c, 0x21, 0 - .dw 0x6f40, 0xc09c, 0x6f7f, 0xc09c, 0x21, 0 - .dw 0x6fc0, 0xc09c, 0x6fff, 0xc09c, 0x21, 0 - .dw 0x7040, 0xc09c, 0x707f, 0xc09c, 0x21, 0 - .dw 0x70c0, 0xc09c, 0x70ff, 0xc09c, 0x21, 0 - .dw 0x7140, 0xc09c, 0x717f, 0xc09c, 0x21, 0 - .dw 0x71c0, 0xc09c, 0x71ff, 0xc09c, 0x21, 0 - .dw 0x7240, 0xc09c, 0x727f, 0xc09c, 0x21, 0 - .dw 0x72c0, 0xc09c, 0x72ff, 0xc09c, 0x21, 0 - .dw 0x7340, 0xc09c, 0x737f, 0xc09c, 0x21, 0 - .dw 0x73c0, 0xc09c, 0x73ff, 0xc09c, 0x21, 0 - .dw 0x7440, 0xc09c, 0x747f, 0xc09c, 0x21, 0 - .dw 0x74c0, 0xc09c, 0x74ff, 0xc09c, 0x21, 0 - .dw 0x7540, 0xc09c, 0x757f, 0xc09c, 0x21, 0 - .dw 0x75c0, 0xc09c, 0x75ff, 0xc09c, 0x21, 0 - .dw 0x7640, 0xc09c, 0x767f, 0xc09c, 0x21, 0 - .dw 0x76c0, 0xc09c, 0x76ff, 0xc09c, 0x21, 0 - .dw 0x7740, 0xc09c, 0x777f, 0xc09c, 0x21, 0 - .dw 0x77c0, 0xc09c, 0x77ff, 0xc09c, 0x21, 0 - .dw 0x7840, 0xc09c, 0x787f, 0xc09c, 0x21, 0 - .dw 0x78c0, 0xc09c, 0x78ff, 0xc09c, 0x21, 0 - .dw 0x7940, 0xc09c, 0x797f, 0xc09c, 0x21, 0 - .dw 0x79c0, 0xc09c, 0x7fff, 0xc09c, 0x21, 0 - .dw 0x8040, 0xc09c, 0x807f, 0xc09c, 0x21, 0 - .dw 0x80c0, 0xc09c, 0x80ff, 0xc09c, 0x21, 0 - .dw 0x8140, 0xc09c, 0x817f, 0xc09c, 0x21, 0 - .dw 0x81c0, 0xc09c, 0x81ff, 0xc09c, 0x21, 0 - .dw 0x8240, 0xc09c, 0x827f, 0xc09c, 0x21, 0 - .dw 0x82c0, 0xc09c, 0x82ff, 0xc09c, 0x21, 0 - .dw 0x8340, 0xc09c, 0x837f, 0xc09c, 0x21, 0 - .dw 0x83c0, 0xc09c, 0x83ff, 0xc09c, 0x21, 0 - .dw 0x8440, 0xc09c, 0x847f, 0xc09c, 0x21, 0 - .dw 0x84c0, 0xc09c, 0x84ff, 0xc09c, 0x21, 0 - .dw 0x8540, 0xc09c, 0x857f, 0xc09c, 0x21, 0 - .dw 0x85c0, 0xc09c, 0x85ff, 0xc09c, 0x21, 0 - .dw 0x8640, 0xc09c, 0x867f, 0xc09c, 0x21, 0 - .dw 0x86c0, 0xc09c, 0x86ff, 0xc09c, 0x21, 0 - .dw 0x8740, 0xc09c, 0x877f, 0xc09c, 0x21, 0 - .dw 0x87c0, 0xc09c, 0x87ff, 0xc09c, 0x21, 0 - .dw 0x8840, 0xc09c, 0x887f, 0xc09c, 0x21, 0 - .dw 0x88c0, 0xc09c, 0x88ff, 0xc09c, 0x21, 0 - .dw 0x8940, 0xc09c, 0x897f, 0xc09c, 0x21, 0 - .dw 0x89c0, 0xc09c, 0x89ff, 0xc09c, 0x21, 0 - .dw 0x8a40, 0xc09c, 0x8a7f, 0xc09c, 0x21, 0 - .dw 0x8ac0, 0xc09c, 0x8aff, 0xc09c, 0x21, 0 - .dw 0x8b40, 0xc09c, 0x8b7f, 0xc09c, 0x21, 0 - .dw 0x8bc0, 0xc09c, 0x8bff, 0xc09c, 0x21, 0 - .dw 0x8c40, 0xc09c, 0x8c7f, 0xc09c, 0x21, 0 - .dw 0x8cc0, 0xc09c, 0x8cff, 0xc09c, 0x21, 0 - .dw 0x8d40, 0xc09c, 0x8d7f, 0xc09c, 0x21, 0 - .dw 0x8dc0, 0xc09c, 0x8dff, 0xc09c, 0x21, 0 - .dw 0x8e40, 0xc09c, 0x8e7f, 0xc09c, 0x21, 0 - .dw 0x8ec0, 0xc09c, 0x8eff, 0xc09c, 0x21, 0 - .dw 0x8f40, 0xc09c, 0x8f7f, 0xc09c, 0x21, 0 - .dw 0x8fc0, 0xc09c, 0x8fff, 0xc09c, 0x21, 0 - .dw 0x9040, 0xc09c, 0x907f, 0xc09c, 0x21, 0 - .dw 0x90c0, 0xc09c, 0x90ff, 0xc09c, 0x21, 0 - .dw 0x9140, 0xc09c, 0x917f, 0xc09c, 0x21, 0 - .dw 0x91c0, 0xc09c, 0x91ff, 0xc09c, 0x21, 0 - .dw 0x9240, 0xc09c, 0x927f, 0xc09c, 0x21, 0 - .dw 0x92c0, 0xc09c, 0x92ff, 0xc09c, 0x21, 0 - .dw 0x9340, 0xc09c, 0x937f, 0xc09c, 0x21, 0 - .dw 0x93c0, 0xc09c, 0x93ff, 0xc09c, 0x21, 0 - .dw 0x9440, 0xc09c, 0x947f, 0xc09c, 0x21, 0 - .dw 0x94c0, 0xc09c, 0x94ff, 0xc09c, 0x21, 0 - .dw 0x9540, 0xc09c, 0x957f, 0xc09c, 0x21, 0 - .dw 0x95c0, 0xc09c, 0x95ff, 0xc09c, 0x21, 0 - .dw 0x9640, 0xc09c, 0x967f, 0xc09c, 0x21, 0 - .dw 0x96c0, 0xc09c, 0x96ff, 0xc09c, 0x21, 0 - .dw 0x9740, 0xc09c, 0x977f, 0xc09c, 0x21, 0 - .dw 0x97c0, 0xc09c, 0x97ff, 0xc09c, 0x21, 0 - .dw 0x9840, 0xc09c, 0x987f, 0xc09c, 0x21, 0 - .dw 0x98c0, 0xc09c, 0x98ff, 0xc09c, 0x21, 0 - .dw 0x9940, 0xc09c, 0x997f, 0xc09c, 0x21, 0 - .dw 0x99c0, 0xc09c, 0x9fff, 0xc09c, 0x21, 0 - .dw 0xa040, 0xc09c, 0xa07f, 0xc09c, 0x21, 0 - .dw 0xa0c0, 0xc09c, 0xa0ff, 0xc09c, 0x21, 0 - .dw 0xa140, 0xc09c, 0xa17f, 0xc09c, 0x21, 0 - .dw 0xa1c0, 0xc09c, 0xa1ff, 0xc09c, 0x21, 0 - .dw 0xa240, 0xc09c, 0xa27f, 0xc09c, 0x21, 0 - .dw 0xa2c0, 0xc09c, 0xa2ff, 0xc09c, 0x21, 0 - .dw 0xa340, 0xc09c, 0xa37f, 0xc09c, 0x21, 0 - .dw 0xa3c0, 0xc09c, 0xa3ff, 0xc09c, 0x21, 0 - .dw 0xa440, 0xc09c, 0xa47f, 0xc09c, 0x21, 0 - .dw 0xa4c0, 0xc09c, 0xa4ff, 0xc09c, 0x21, 0 - .dw 0xa540, 0xc09c, 0xa57f, 0xc09c, 0x21, 0 - .dw 0xa5c0, 0xc09c, 0xa5ff, 0xc09c, 0x21, 0 - .dw 0xa640, 0xc09c, 0xa67f, 0xc09c, 0x21, 0 - .dw 0xa6c0, 0xc09c, 0xa6ff, 0xc09c, 0x21, 0 - .dw 0xa740, 0xc09c, 0xa77f, 0xc09c, 0x21, 0 - .dw 0xa7c0, 0xc09c, 0xa7ff, 0xc09c, 0x21, 0 - .dw 0xa840, 0xc09c, 0xa87f, 0xc09c, 0x21, 0 - .dw 0xa8c0, 0xc09c, 0xa8ff, 0xc09c, 0x21, 0 - .dw 0xa940, 0xc09c, 0xa97f, 0xc09c, 0x21, 0 - .dw 0xa9c0, 0xc09c, 0xa9ff, 0xc09c, 0x21, 0 - .dw 0xaa40, 0xc09c, 0xaa7f, 0xc09c, 0x21, 0 - .dw 0xaac0, 0xc09c, 0xaaff, 0xc09c, 0x21, 0 - .dw 0xab40, 0xc09c, 0xab7f, 0xc09c, 0x21, 0 - .dw 0xabc0, 0xc09c, 0xabff, 0xc09c, 0x21, 0 - .dw 0xac40, 0xc09c, 0xac7f, 0xc09c, 0x21, 0 - .dw 0xacc0, 0xc09c, 0xacff, 0xc09c, 0x21, 0 - .dw 0xad40, 0xc09c, 0xad7f, 0xc09c, 0x21, 0 - .dw 0xadc0, 0xc09c, 0xadff, 0xc09c, 0x21, 0 - .dw 0xae40, 0xc09c, 0xae7f, 0xc09c, 0x21, 0 - .dw 0xaec0, 0xc09c, 0xaeff, 0xc09c, 0x21, 0 - .dw 0xaf40, 0xc09c, 0xaf7f, 0xc09c, 0x21, 0 - .dw 0xafc0, 0xc09c, 0xafff, 0xc09c, 0x21, 0 - .dw 0xb040, 0xc09c, 0xb07f, 0xc09c, 0x21, 0 - .dw 0xb0c0, 0xc09c, 0xb0ff, 0xc09c, 0x21, 0 - .dw 0xb140, 0xc09c, 0xb17f, 0xc09c, 0x21, 0 - .dw 0xb1c0, 0xc09c, 0xb1ff, 0xc09c, 0x21, 0 - .dw 0xb240, 0xc09c, 0xb27f, 0xc09c, 0x21, 0 - .dw 0xb2c0, 0xc09c, 0xb2ff, 0xc09c, 0x21, 0 - .dw 0xb340, 0xc09c, 0xb37f, 0xc09c, 0x21, 0 - .dw 0xb3c0, 0xc09c, 0xb3ff, 0xc09c, 0x21, 0 - .dw 0xb440, 0xc09c, 0xb47f, 0xc09c, 0x21, 0 - .dw 0xb4c0, 0xc09c, 0xb4ff, 0xc09c, 0x21, 0 - .dw 0xb540, 0xc09c, 0xb57f, 0xc09c, 0x21, 0 - .dw 0xb5c0, 0xc09c, 0xb5ff, 0xc09c, 0x21, 0 - .dw 0xb640, 0xc09c, 0xb67f, 0xc09c, 0x21, 0 - .dw 0xb6c0, 0xc09c, 0xb6ff, 0xc09c, 0x21, 0 - .dw 0xb740, 0xc09c, 0xb77f, 0xc09c, 0x21, 0 - .dw 0xb7c0, 0xc09c, 0xb7ff, 0xc09c, 0x21, 0 - .dw 0xb840, 0xc09c, 0xb87f, 0xc09c, 0x21, 0 - .dw 0xb8c0, 0xc09c, 0xb8ff, 0xc09c, 0x21, 0 - .dw 0xb940, 0xc09c, 0xb97f, 0xc09c, 0x21, 0 - .dw 0xb9c0, 0xc09c, 0xbfff, 0xc09c, 0x21, 0 - .dw 0xc040, 0xc09c, 0xc07f, 0xc09c, 0x21, 0 - .dw 0xc0c0, 0xc09c, 0xc0ff, 0xc09c, 0x21, 0 - .dw 0xc140, 0xc09c, 0xc17f, 0xc09c, 0x21, 0 - .dw 0xc1c0, 0xc09c, 0xc1ff, 0xc09c, 0x21, 0 - .dw 0xc240, 0xc09c, 0xc27f, 0xc09c, 0x21, 0 - .dw 0xc2c0, 0xc09c, 0xc2ff, 0xc09c, 0x21, 0 - .dw 0xc340, 0xc09c, 0xc37f, 0xc09c, 0x21, 0 - .dw 0xc3c0, 0xc09c, 0xc3ff, 0xc09c, 0x21, 0 - .dw 0xc440, 0xc09c, 0xc47f, 0xc09c, 0x21, 0 - .dw 0xc4c0, 0xc09c, 0xc4ff, 0xc09c, 0x21, 0 - .dw 0xc540, 0xc09c, 0xc57f, 0xc09c, 0x21, 0 - .dw 0xc5c0, 0xc09c, 0xc5ff, 0xc09c, 0x21, 0 - .dw 0xc640, 0xc09c, 0xc67f, 0xc09c, 0x21, 0 - .dw 0xc6c0, 0xc09c, 0xc6ff, 0xc09c, 0x21, 0 - .dw 0xc740, 0xc09c, 0xc77f, 0xc09c, 0x21, 0 - .dw 0xc7c0, 0xc09c, 0xc7ff, 0xc09c, 0x21, 0 - .dw 0xc840, 0xc09c, 0xc87f, 0xc09c, 0x21, 0 - .dw 0xc8c0, 0xc09c, 0xc8ff, 0xc09c, 0x21, 0 - .dw 0xc940, 0xc09c, 0xc97f, 0xc09c, 0x21, 0 - .dw 0xc9c0, 0xc09c, 0xc9ff, 0xc09c, 0x21, 0 - .dw 0xca40, 0xc09c, 0xca7f, 0xc09c, 0x21, 0 - .dw 0xcac0, 0xc09c, 0xcaff, 0xc09c, 0x21, 0 - .dw 0xcb40, 0xc09c, 0xcb7f, 0xc09c, 0x21, 0 - .dw 0xcbc0, 0xc09c, 0xcbff, 0xc09c, 0x21, 0 - .dw 0xcc40, 0xc09c, 0xcc7f, 0xc09c, 0x21, 0 - .dw 0xccc0, 0xc09c, 0xccff, 0xc09c, 0x21, 0 - .dw 0xcd40, 0xc09c, 0xcd7f, 0xc09c, 0x21, 0 - .dw 0xcdc0, 0xc09c, 0xcdff, 0xc09c, 0x21, 0 - .dw 0xce40, 0xc09c, 0xce7f, 0xc09c, 0x21, 0 - .dw 0xcec0, 0xc09c, 0xceff, 0xc09c, 0x21, 0 - .dw 0xcf40, 0xc09c, 0xcf7f, 0xc09c, 0x21, 0 - .dw 0xcfc0, 0xc09c, 0xcfff, 0xc09c, 0x21, 0 - .dw 0xd040, 0xc09c, 0xd07f, 0xc09c, 0x21, 0 - .dw 0xd0c0, 0xc09c, 0xd0ff, 0xc09c, 0x21, 0 - .dw 0xd140, 0xc09c, 0xd17f, 0xc09c, 0x21, 0 - .dw 0xd1c0, 0xc09c, 0xd1ff, 0xc09c, 0x21, 0 - .dw 0xd240, 0xc09c, 0xd27f, 0xc09c, 0x21, 0 - .dw 0xd2c0, 0xc09c, 0xd2ff, 0xc09c, 0x21, 0 - .dw 0xd340, 0xc09c, 0xd37f, 0xc09c, 0x21, 0 - .dw 0xd3c0, 0xc09c, 0xd3ff, 0xc09c, 0x21, 0 - .dw 0xd440, 0xc09c, 0xd47f, 0xc09c, 0x21, 0 - .dw 0xd4c0, 0xc09c, 0xd4ff, 0xc09c, 0x21, 0 - .dw 0xd540, 0xc09c, 0xd57f, 0xc09c, 0x21, 0 - .dw 0xd5c0, 0xc09c, 0xd5ff, 0xc09c, 0x21, 0 - .dw 0xd640, 0xc09c, 0xd67f, 0xc09c, 0x21, 0 - .dw 0xd6c0, 0xc09c, 0xd6ff, 0xc09c, 0x21, 0 - .dw 0xd740, 0xc09c, 0xd77f, 0xc09c, 0x21, 0 - .dw 0xd7c0, 0xc09c, 0xd7ff, 0xc09c, 0x21, 0 - .dw 0xd840, 0xc09c, 0xd87f, 0xc09c, 0x21, 0 - .dw 0xd8c0, 0xc09c, 0xd8ff, 0xc09c, 0x21, 0 - .dw 0xd940, 0xc09c, 0xd97f, 0xc09c, 0x21, 0 - .dw 0xd9c0, 0xc09c, 0xdfff, 0xc09c, 0x21, 0 - .dw 0xe040, 0xc09c, 0xe07f, 0xc09c, 0x21, 0 - .dw 0xe0c0, 0xc09c, 0xe0ff, 0xc09c, 0x21, 0 - .dw 0xe140, 0xc09c, 0xe17f, 0xc09c, 0x21, 0 - .dw 0xe1c0, 0xc09c, 0xe1ff, 0xc09c, 0x21, 0 - .dw 0xe240, 0xc09c, 0xe27f, 0xc09c, 0x21, 0 - .dw 0xe2c0, 0xc09c, 0xe2ff, 0xc09c, 0x21, 0 - .dw 0xe340, 0xc09c, 0xe37f, 0xc09c, 0x21, 0 - .dw 0xe3c0, 0xc09c, 0xe3ff, 0xc09c, 0x21, 0 - .dw 0xe440, 0xc09c, 0xe47f, 0xc09c, 0x21, 0 - .dw 0xe4c0, 0xc09c, 0xe4ff, 0xc09c, 0x21, 0 - .dw 0xe540, 0xc09c, 0xe57f, 0xc09c, 0x21, 0 - .dw 0xe5c0, 0xc09c, 0xe5ff, 0xc09c, 0x21, 0 - .dw 0xe640, 0xc09c, 0xe67f, 0xc09c, 0x21, 0 - .dw 0xe6c0, 0xc09c, 0xe6ff, 0xc09c, 0x21, 0 - .dw 0xe740, 0xc09c, 0xe77f, 0xc09c, 0x21, 0 - .dw 0xe7c0, 0xc09c, 0xe7ff, 0xc09c, 0x21, 0 - .dw 0xe840, 0xc09c, 0xe87f, 0xc09c, 0x21, 0 - .dw 0xe8c0, 0xc09c, 0xe8ff, 0xc09c, 0x21, 0 - .dw 0xe940, 0xc09c, 0xe97f, 0xc09c, 0x21, 0 - .dw 0xe9c0, 0xc09c, 0xe9ff, 0xc09c, 0x21, 0 - .dw 0xea40, 0xc09c, 0xea7f, 0xc09c, 0x21, 0 - .dw 0xeac0, 0xc09c, 0xeaff, 0xc09c, 0x21, 0 - .dw 0xeb40, 0xc09c, 0xeb7f, 0xc09c, 0x21, 0 - .dw 0xebc0, 0xc09c, 0xebff, 0xc09c, 0x21, 0 - .dw 0xec40, 0xc09c, 0xec7f, 0xc09c, 0x21, 0 - .dw 0xecc0, 0xc09c, 0xecff, 0xc09c, 0x21, 0 - .dw 0xed40, 0xc09c, 0xed7f, 0xc09c, 0x21, 0 - .dw 0xedc0, 0xc09c, 0xedff, 0xc09c, 0x21, 0 - .dw 0xee40, 0xc09c, 0xee7f, 0xc09c, 0x21, 0 - .dw 0xeec0, 0xc09c, 0xeeff, 0xc09c, 0x21, 0 - .dw 0xef40, 0xc09c, 0xef7f, 0xc09c, 0x21, 0 - .dw 0xefc0, 0xc09c, 0xefff, 0xc09c, 0x21, 0 - .dw 0xf040, 0xc09c, 0xf07f, 0xc09c, 0x21, 0 - .dw 0xf0c0, 0xc09c, 0xf0ff, 0xc09c, 0x21, 0 - .dw 0xf140, 0xc09c, 0xf17f, 0xc09c, 0x21, 0 - .dw 0xf1c0, 0xc09c, 0xf1ff, 0xc09c, 0x21, 0 - .dw 0xf240, 0xc09c, 0xf27f, 0xc09c, 0x21, 0 - .dw 0xf2c0, 0xc09c, 0xf2ff, 0xc09c, 0x21, 0 - .dw 0xf340, 0xc09c, 0xf37f, 0xc09c, 0x21, 0 - .dw 0xf3c0, 0xc09c, 0xf3ff, 0xc09c, 0x21, 0 - .dw 0xf440, 0xc09c, 0xf47f, 0xc09c, 0x21, 0 - .dw 0xf4c0, 0xc09c, 0xf4ff, 0xc09c, 0x21, 0 - .dw 0xf540, 0xc09c, 0xf57f, 0xc09c, 0x21, 0 - .dw 0xf5c0, 0xc09c, 0xf5ff, 0xc09c, 0x21, 0 - .dw 0xf640, 0xc09c, 0xf67f, 0xc09c, 0x21, 0 - .dw 0xf6c0, 0xc09c, 0xf6ff, 0xc09c, 0x21, 0 - .dw 0xf740, 0xc09c, 0xf77f, 0xc09c, 0x21, 0 - .dw 0xf7c0, 0xc09c, 0xf7ff, 0xc09c, 0x21, 0 - .dw 0xf840, 0xc09c, 0xf87f, 0xc09c, 0x21, 0 - .dw 0xf8c0, 0xc09c, 0xf8ff, 0xc09c, 0x21, 0 - .dw 0xf940, 0xc09c, 0xf97f, 0xc09c, 0x21, 0 - .dw 0xf9c0, 0xc09c, 0xffff, 0xc09c, 0x21, 0 - .dw 0x0040, 0xc09d, 0x007f, 0xc09d, 0x21, 0 - .dw 0x00c0, 0xc09d, 0x00ff, 0xc09d, 0x21, 0 - .dw 0x0140, 0xc09d, 0x017f, 0xc09d, 0x21, 0 - .dw 0x01c0, 0xc09d, 0x01ff, 0xc09d, 0x21, 0 - .dw 0x0240, 0xc09d, 0x027f, 0xc09d, 0x21, 0 - .dw 0x02c0, 0xc09d, 0x02ff, 0xc09d, 0x21, 0 - .dw 0x0340, 0xc09d, 0x037f, 0xc09d, 0x21, 0 - .dw 0x03c0, 0xc09d, 0x03ff, 0xc09d, 0x21, 0 - .dw 0x0440, 0xc09d, 0x047f, 0xc09d, 0x21, 0 - .dw 0x04c0, 0xc09d, 0x04ff, 0xc09d, 0x21, 0 - .dw 0x0540, 0xc09d, 0x057f, 0xc09d, 0x21, 0 - .dw 0x05c0, 0xc09d, 0x05ff, 0xc09d, 0x21, 0 - .dw 0x0640, 0xc09d, 0x067f, 0xc09d, 0x21, 0 - .dw 0x06c0, 0xc09d, 0x06ff, 0xc09d, 0x21, 0 - .dw 0x0740, 0xc09d, 0x077f, 0xc09d, 0x21, 0 - .dw 0x07c0, 0xc09d, 0x07ff, 0xc09d, 0x21, 0 - .dw 0x0840, 0xc09d, 0x087f, 0xc09d, 0x21, 0 - .dw 0x08c0, 0xc09d, 0x08ff, 0xc09d, 0x21, 0 - .dw 0x0940, 0xc09d, 0x097f, 0xc09d, 0x21, 0 - .dw 0x09c0, 0xc09d, 0x09ff, 0xc09d, 0x21, 0 - .dw 0x0a40, 0xc09d, 0x0a7f, 0xc09d, 0x21, 0 - .dw 0x0ac0, 0xc09d, 0x0aff, 0xc09d, 0x21, 0 - .dw 0x0b40, 0xc09d, 0x0b7f, 0xc09d, 0x21, 0 - .dw 0x0bc0, 0xc09d, 0x0bff, 0xc09d, 0x21, 0 - .dw 0x0c40, 0xc09d, 0x0c7f, 0xc09d, 0x21, 0 - .dw 0x0cc0, 0xc09d, 0x0cff, 0xc09d, 0x21, 0 - .dw 0x0d40, 0xc09d, 0x0d7f, 0xc09d, 0x21, 0 - .dw 0x0dc0, 0xc09d, 0x0dff, 0xc09d, 0x21, 0 - .dw 0x0e40, 0xc09d, 0x0e7f, 0xc09d, 0x21, 0 - .dw 0x0ec0, 0xc09d, 0x0eff, 0xc09d, 0x21, 0 - .dw 0x0f40, 0xc09d, 0x0f7f, 0xc09d, 0x21, 0 - .dw 0x0fc0, 0xc09d, 0x0fff, 0xc09d, 0x21, 0 - .dw 0x1040, 0xc09d, 0x107f, 0xc09d, 0x21, 0 - .dw 0x10c0, 0xc09d, 0x10ff, 0xc09d, 0x21, 0 - .dw 0x1140, 0xc09d, 0x117f, 0xc09d, 0x21, 0 - .dw 0x11c0, 0xc09d, 0x11ff, 0xc09d, 0x21, 0 - .dw 0x1240, 0xc09d, 0x127f, 0xc09d, 0x21, 0 - .dw 0x12c0, 0xc09d, 0x12ff, 0xc09d, 0x21, 0 - .dw 0x1340, 0xc09d, 0x137f, 0xc09d, 0x21, 0 - .dw 0x13c0, 0xc09d, 0x13ff, 0xc09d, 0x21, 0 - .dw 0x1440, 0xc09d, 0x147f, 0xc09d, 0x21, 0 - .dw 0x14c0, 0xc09d, 0x14ff, 0xc09d, 0x21, 0 - .dw 0x1540, 0xc09d, 0x157f, 0xc09d, 0x21, 0 - .dw 0x15c0, 0xc09d, 0x15ff, 0xc09d, 0x21, 0 - .dw 0x1640, 0xc09d, 0x167f, 0xc09d, 0x21, 0 - .dw 0x16c0, 0xc09d, 0x16ff, 0xc09d, 0x21, 0 - .dw 0x1740, 0xc09d, 0x177f, 0xc09d, 0x21, 0 - .dw 0x17c0, 0xc09d, 0x17ff, 0xc09d, 0x21, 0 - .dw 0x1840, 0xc09d, 0x187f, 0xc09d, 0x21, 0 - .dw 0x18c0, 0xc09d, 0x18ff, 0xc09d, 0x21, 0 - .dw 0x1940, 0xc09d, 0x197f, 0xc09d, 0x21, 0 - .dw 0x19c0, 0xc09d, 0x1fff, 0xc09d, 0x21, 0 - .dw 0x2040, 0xc09d, 0x207f, 0xc09d, 0x21, 0 - .dw 0x20c0, 0xc09d, 0x20ff, 0xc09d, 0x21, 0 - .dw 0x2140, 0xc09d, 0x217f, 0xc09d, 0x21, 0 - .dw 0x21c0, 0xc09d, 0x21ff, 0xc09d, 0x21, 0 - .dw 0x2240, 0xc09d, 0x227f, 0xc09d, 0x21, 0 - .dw 0x22c0, 0xc09d, 0x22ff, 0xc09d, 0x21, 0 - .dw 0x2340, 0xc09d, 0x237f, 0xc09d, 0x21, 0 - .dw 0x23c0, 0xc09d, 0x23ff, 0xc09d, 0x21, 0 - .dw 0x2440, 0xc09d, 0x247f, 0xc09d, 0x21, 0 - .dw 0x24c0, 0xc09d, 0x24ff, 0xc09d, 0x21, 0 - .dw 0x2540, 0xc09d, 0x257f, 0xc09d, 0x21, 0 - .dw 0x25c0, 0xc09d, 0x25ff, 0xc09d, 0x21, 0 - .dw 0x2640, 0xc09d, 0x267f, 0xc09d, 0x21, 0 - .dw 0x26c0, 0xc09d, 0x26ff, 0xc09d, 0x21, 0 - .dw 0x2740, 0xc09d, 0x277f, 0xc09d, 0x21, 0 - .dw 0x27c0, 0xc09d, 0x27ff, 0xc09d, 0x21, 0 - .dw 0x2840, 0xc09d, 0x287f, 0xc09d, 0x21, 0 - .dw 0x28c0, 0xc09d, 0x28ff, 0xc09d, 0x21, 0 - .dw 0x2940, 0xc09d, 0x297f, 0xc09d, 0x21, 0 - .dw 0x29c0, 0xc09d, 0x29ff, 0xc09d, 0x21, 0 - .dw 0x2a40, 0xc09d, 0x2a7f, 0xc09d, 0x21, 0 - .dw 0x2ac0, 0xc09d, 0x2aff, 0xc09d, 0x21, 0 - .dw 0x2b40, 0xc09d, 0x2b7f, 0xc09d, 0x21, 0 - .dw 0x2bc0, 0xc09d, 0x2bff, 0xc09d, 0x21, 0 - .dw 0x2c40, 0xc09d, 0x2c7f, 0xc09d, 0x21, 0 - .dw 0x2cc0, 0xc09d, 0x2cff, 0xc09d, 0x21, 0 - .dw 0x2d40, 0xc09d, 0x2d7f, 0xc09d, 0x21, 0 - .dw 0x2dc0, 0xc09d, 0x2dff, 0xc09d, 0x21, 0 - .dw 0x2e40, 0xc09d, 0x2e7f, 0xc09d, 0x21, 0 - .dw 0x2ec0, 0xc09d, 0x2eff, 0xc09d, 0x21, 0 - .dw 0x2f40, 0xc09d, 0x2f7f, 0xc09d, 0x21, 0 - .dw 0x2fc0, 0xc09d, 0x2fff, 0xc09d, 0x21, 0 - .dw 0x3040, 0xc09d, 0x307f, 0xc09d, 0x21, 0 - .dw 0x30c0, 0xc09d, 0x30ff, 0xc09d, 0x21, 0 - .dw 0x3140, 0xc09d, 0x317f, 0xc09d, 0x21, 0 - .dw 0x31c0, 0xc09d, 0x31ff, 0xc09d, 0x21, 0 - .dw 0x3240, 0xc09d, 0x327f, 0xc09d, 0x21, 0 - .dw 0x32c0, 0xc09d, 0x32ff, 0xc09d, 0x21, 0 - .dw 0x3340, 0xc09d, 0x337f, 0xc09d, 0x21, 0 - .dw 0x33c0, 0xc09d, 0x33ff, 0xc09d, 0x21, 0 - .dw 0x3440, 0xc09d, 0x347f, 0xc09d, 0x21, 0 - .dw 0x34c0, 0xc09d, 0x34ff, 0xc09d, 0x21, 0 - .dw 0x3540, 0xc09d, 0x357f, 0xc09d, 0x21, 0 - .dw 0x35c0, 0xc09d, 0x35ff, 0xc09d, 0x21, 0 - .dw 0x3640, 0xc09d, 0x367f, 0xc09d, 0x21, 0 - .dw 0x36c0, 0xc09d, 0x36ff, 0xc09d, 0x21, 0 - .dw 0x3740, 0xc09d, 0x377f, 0xc09d, 0x21, 0 - .dw 0x37c0, 0xc09d, 0x37ff, 0xc09d, 0x21, 0 - .dw 0x3840, 0xc09d, 0x387f, 0xc09d, 0x21, 0 - .dw 0x38c0, 0xc09d, 0x38ff, 0xc09d, 0x21, 0 - .dw 0x3940, 0xc09d, 0x397f, 0xc09d, 0x21, 0 - .dw 0x39c0, 0xc09d, 0x3fff, 0xc09d, 0x21, 0 - .dw 0x4040, 0xc09d, 0x407f, 0xc09d, 0x21, 0 - .dw 0x40c0, 0xc09d, 0x40ff, 0xc09d, 0x21, 0 - .dw 0x4140, 0xc09d, 0x417f, 0xc09d, 0x21, 0 - .dw 0x41c0, 0xc09d, 0x41ff, 0xc09d, 0x21, 0 - .dw 0x4240, 0xc09d, 0x427f, 0xc09d, 0x21, 0 - .dw 0x42c0, 0xc09d, 0x42ff, 0xc09d, 0x21, 0 - .dw 0x4340, 0xc09d, 0x437f, 0xc09d, 0x21, 0 - .dw 0x43c0, 0xc09d, 0x43ff, 0xc09d, 0x21, 0 - .dw 0x4440, 0xc09d, 0x447f, 0xc09d, 0x21, 0 - .dw 0x44c0, 0xc09d, 0x44ff, 0xc09d, 0x21, 0 - .dw 0x4540, 0xc09d, 0x457f, 0xc09d, 0x21, 0 - .dw 0x45c0, 0xc09d, 0x45ff, 0xc09d, 0x21, 0 - .dw 0x4640, 0xc09d, 0x467f, 0xc09d, 0x21, 0 - .dw 0x46c0, 0xc09d, 0x46ff, 0xc09d, 0x21, 0 - .dw 0x4740, 0xc09d, 0x477f, 0xc09d, 0x21, 0 - .dw 0x47c0, 0xc09d, 0x47ff, 0xc09d, 0x21, 0 - .dw 0x4840, 0xc09d, 0x487f, 0xc09d, 0x21, 0 - .dw 0x48c0, 0xc09d, 0x48ff, 0xc09d, 0x21, 0 - .dw 0x4940, 0xc09d, 0x497f, 0xc09d, 0x21, 0 - .dw 0x49c0, 0xc09d, 0x49ff, 0xc09d, 0x21, 0 - .dw 0x4a40, 0xc09d, 0x4a7f, 0xc09d, 0x21, 0 - .dw 0x4ac0, 0xc09d, 0x4aff, 0xc09d, 0x21, 0 - .dw 0x4b40, 0xc09d, 0x4b7f, 0xc09d, 0x21, 0 - .dw 0x4bc0, 0xc09d, 0x4bff, 0xc09d, 0x21, 0 - .dw 0x4c40, 0xc09d, 0x4c7f, 0xc09d, 0x21, 0 - .dw 0x4cc0, 0xc09d, 0x4cff, 0xc09d, 0x21, 0 - .dw 0x4d40, 0xc09d, 0x4d7f, 0xc09d, 0x21, 0 - .dw 0x4dc0, 0xc09d, 0x4dff, 0xc09d, 0x21, 0 - .dw 0x4e40, 0xc09d, 0x4e7f, 0xc09d, 0x21, 0 - .dw 0x4ec0, 0xc09d, 0x4eff, 0xc09d, 0x21, 0 - .dw 0x4f40, 0xc09d, 0x4f7f, 0xc09d, 0x21, 0 - .dw 0x4fc0, 0xc09d, 0x4fff, 0xc09d, 0x21, 0 - .dw 0x5040, 0xc09d, 0x507f, 0xc09d, 0x21, 0 - .dw 0x50c0, 0xc09d, 0x50ff, 0xc09d, 0x21, 0 - .dw 0x5140, 0xc09d, 0x517f, 0xc09d, 0x21, 0 - .dw 0x51c0, 0xc09d, 0x51ff, 0xc09d, 0x21, 0 - .dw 0x5240, 0xc09d, 0x527f, 0xc09d, 0x21, 0 - .dw 0x52c0, 0xc09d, 0x52ff, 0xc09d, 0x21, 0 - .dw 0x5340, 0xc09d, 0x537f, 0xc09d, 0x21, 0 - .dw 0x53c0, 0xc09d, 0x53ff, 0xc09d, 0x21, 0 - .dw 0x5440, 0xc09d, 0x547f, 0xc09d, 0x21, 0 - .dw 0x54c0, 0xc09d, 0x54ff, 0xc09d, 0x21, 0 - .dw 0x5540, 0xc09d, 0x557f, 0xc09d, 0x21, 0 - .dw 0x55c0, 0xc09d, 0x55ff, 0xc09d, 0x21, 0 - .dw 0x5640, 0xc09d, 0x567f, 0xc09d, 0x21, 0 - .dw 0x56c0, 0xc09d, 0x56ff, 0xc09d, 0x21, 0 - .dw 0x5740, 0xc09d, 0x577f, 0xc09d, 0x21, 0 - .dw 0x57c0, 0xc09d, 0x57ff, 0xc09d, 0x21, 0 - .dw 0x5840, 0xc09d, 0x587f, 0xc09d, 0x21, 0 - .dw 0x58c0, 0xc09d, 0x58ff, 0xc09d, 0x21, 0 - .dw 0x5940, 0xc09d, 0x597f, 0xc09d, 0x21, 0 - .dw 0x59c0, 0xc09d, 0x5fff, 0xc09d, 0x21, 0 - .dw 0x6040, 0xc09d, 0x607f, 0xc09d, 0x21, 0 - .dw 0x60c0, 0xc09d, 0x60ff, 0xc09d, 0x21, 0 - .dw 0x6140, 0xc09d, 0x617f, 0xc09d, 0x21, 0 - .dw 0x61c0, 0xc09d, 0x61ff, 0xc09d, 0x21, 0 - .dw 0x6240, 0xc09d, 0x627f, 0xc09d, 0x21, 0 - .dw 0x62c0, 0xc09d, 0x62ff, 0xc09d, 0x21, 0 - .dw 0x6340, 0xc09d, 0x637f, 0xc09d, 0x21, 0 - .dw 0x63c0, 0xc09d, 0x63ff, 0xc09d, 0x21, 0 - .dw 0x6440, 0xc09d, 0x647f, 0xc09d, 0x21, 0 - .dw 0x64c0, 0xc09d, 0x64ff, 0xc09d, 0x21, 0 - .dw 0x6540, 0xc09d, 0x657f, 0xc09d, 0x21, 0 - .dw 0x65c0, 0xc09d, 0x65ff, 0xc09d, 0x21, 0 - .dw 0x6640, 0xc09d, 0x667f, 0xc09d, 0x21, 0 - .dw 0x66c0, 0xc09d, 0x66ff, 0xc09d, 0x21, 0 - .dw 0x6740, 0xc09d, 0x677f, 0xc09d, 0x21, 0 - .dw 0x67c0, 0xc09d, 0x67ff, 0xc09d, 0x21, 0 - .dw 0x6840, 0xc09d, 0x687f, 0xc09d, 0x21, 0 - .dw 0x68c0, 0xc09d, 0x68ff, 0xc09d, 0x21, 0 - .dw 0x6940, 0xc09d, 0x697f, 0xc09d, 0x21, 0 - .dw 0x69c0, 0xc09d, 0x69ff, 0xc09d, 0x21, 0 - .dw 0x6a40, 0xc09d, 0x6a7f, 0xc09d, 0x21, 0 - .dw 0x6ac0, 0xc09d, 0x6aff, 0xc09d, 0x21, 0 - .dw 0x6b40, 0xc09d, 0x6b7f, 0xc09d, 0x21, 0 - .dw 0x6bc0, 0xc09d, 0x6bff, 0xc09d, 0x21, 0 - .dw 0x6c40, 0xc09d, 0x6c7f, 0xc09d, 0x21, 0 - .dw 0x6cc0, 0xc09d, 0x6cff, 0xc09d, 0x21, 0 - .dw 0x6d40, 0xc09d, 0x6d7f, 0xc09d, 0x21, 0 - .dw 0x6dc0, 0xc09d, 0x6dff, 0xc09d, 0x21, 0 - .dw 0x6e40, 0xc09d, 0x6e7f, 0xc09d, 0x21, 0 - .dw 0x6ec0, 0xc09d, 0x6eff, 0xc09d, 0x21, 0 - .dw 0x6f40, 0xc09d, 0x6f7f, 0xc09d, 0x21, 0 - .dw 0x6fc0, 0xc09d, 0x6fff, 0xc09d, 0x21, 0 - .dw 0x7040, 0xc09d, 0x707f, 0xc09d, 0x21, 0 - .dw 0x70c0, 0xc09d, 0x70ff, 0xc09d, 0x21, 0 - .dw 0x7140, 0xc09d, 0x717f, 0xc09d, 0x21, 0 - .dw 0x71c0, 0xc09d, 0x71ff, 0xc09d, 0x21, 0 - .dw 0x7240, 0xc09d, 0x727f, 0xc09d, 0x21, 0 - .dw 0x72c0, 0xc09d, 0x72ff, 0xc09d, 0x21, 0 - .dw 0x7340, 0xc09d, 0x737f, 0xc09d, 0x21, 0 - .dw 0x73c0, 0xc09d, 0x73ff, 0xc09d, 0x21, 0 - .dw 0x7440, 0xc09d, 0x747f, 0xc09d, 0x21, 0 - .dw 0x74c0, 0xc09d, 0x74ff, 0xc09d, 0x21, 0 - .dw 0x7540, 0xc09d, 0x757f, 0xc09d, 0x21, 0 - .dw 0x75c0, 0xc09d, 0x75ff, 0xc09d, 0x21, 0 - .dw 0x7640, 0xc09d, 0x767f, 0xc09d, 0x21, 0 - .dw 0x76c0, 0xc09d, 0x76ff, 0xc09d, 0x21, 0 - .dw 0x7740, 0xc09d, 0x777f, 0xc09d, 0x21, 0 - .dw 0x77c0, 0xc09d, 0x77ff, 0xc09d, 0x21, 0 - .dw 0x7840, 0xc09d, 0x787f, 0xc09d, 0x21, 0 - .dw 0x78c0, 0xc09d, 0x78ff, 0xc09d, 0x21, 0 - .dw 0x7940, 0xc09d, 0x797f, 0xc09d, 0x21, 0 - .dw 0x79c0, 0xc09d, 0x7fff, 0xc09d, 0x21, 0 - .dw 0x8040, 0xc09d, 0x807f, 0xc09d, 0x21, 0 - .dw 0x80c0, 0xc09d, 0x80ff, 0xc09d, 0x21, 0 - .dw 0x8140, 0xc09d, 0x817f, 0xc09d, 0x21, 0 - .dw 0x81c0, 0xc09d, 0x81ff, 0xc09d, 0x21, 0 - .dw 0x8240, 0xc09d, 0x827f, 0xc09d, 0x21, 0 - .dw 0x82c0, 0xc09d, 0x82ff, 0xc09d, 0x21, 0 - .dw 0x8340, 0xc09d, 0x837f, 0xc09d, 0x21, 0 - .dw 0x83c0, 0xc09d, 0x83ff, 0xc09d, 0x21, 0 - .dw 0x8440, 0xc09d, 0x847f, 0xc09d, 0x21, 0 - .dw 0x84c0, 0xc09d, 0x84ff, 0xc09d, 0x21, 0 - .dw 0x8540, 0xc09d, 0x857f, 0xc09d, 0x21, 0 - .dw 0x85c0, 0xc09d, 0x85ff, 0xc09d, 0x21, 0 - .dw 0x8640, 0xc09d, 0x867f, 0xc09d, 0x21, 0 - .dw 0x86c0, 0xc09d, 0x86ff, 0xc09d, 0x21, 0 - .dw 0x8740, 0xc09d, 0x877f, 0xc09d, 0x21, 0 - .dw 0x87c0, 0xc09d, 0x87ff, 0xc09d, 0x21, 0 - .dw 0x8840, 0xc09d, 0x887f, 0xc09d, 0x21, 0 - .dw 0x88c0, 0xc09d, 0x88ff, 0xc09d, 0x21, 0 - .dw 0x8940, 0xc09d, 0x897f, 0xc09d, 0x21, 0 - .dw 0x89c0, 0xc09d, 0x89ff, 0xc09d, 0x21, 0 - .dw 0x8a40, 0xc09d, 0x8a7f, 0xc09d, 0x21, 0 - .dw 0x8ac0, 0xc09d, 0x8aff, 0xc09d, 0x21, 0 - .dw 0x8b40, 0xc09d, 0x8b7f, 0xc09d, 0x21, 0 - .dw 0x8bc0, 0xc09d, 0x8bff, 0xc09d, 0x21, 0 - .dw 0x8c40, 0xc09d, 0x8c7f, 0xc09d, 0x21, 0 - .dw 0x8cc0, 0xc09d, 0x8cff, 0xc09d, 0x21, 0 - .dw 0x8d40, 0xc09d, 0x8d7f, 0xc09d, 0x21, 0 - .dw 0x8dc0, 0xc09d, 0x8dff, 0xc09d, 0x21, 0 - .dw 0x8e40, 0xc09d, 0x8e7f, 0xc09d, 0x21, 0 - .dw 0x8ec0, 0xc09d, 0x8eff, 0xc09d, 0x21, 0 - .dw 0x8f40, 0xc09d, 0x8f7f, 0xc09d, 0x21, 0 - .dw 0x8fc0, 0xc09d, 0x8fff, 0xc09d, 0x21, 0 - .dw 0x9040, 0xc09d, 0x907f, 0xc09d, 0x21, 0 - .dw 0x90c0, 0xc09d, 0x90ff, 0xc09d, 0x21, 0 - .dw 0x9140, 0xc09d, 0x917f, 0xc09d, 0x21, 0 - .dw 0x91c0, 0xc09d, 0x91ff, 0xc09d, 0x21, 0 - .dw 0x9240, 0xc09d, 0x927f, 0xc09d, 0x21, 0 - .dw 0x92c0, 0xc09d, 0x92ff, 0xc09d, 0x21, 0 - .dw 0x9340, 0xc09d, 0x937f, 0xc09d, 0x21, 0 - .dw 0x93c0, 0xc09d, 0x93ff, 0xc09d, 0x21, 0 - .dw 0x9440, 0xc09d, 0x947f, 0xc09d, 0x21, 0 - .dw 0x94c0, 0xc09d, 0x94ff, 0xc09d, 0x21, 0 - .dw 0x9540, 0xc09d, 0x957f, 0xc09d, 0x21, 0 - .dw 0x95c0, 0xc09d, 0x95ff, 0xc09d, 0x21, 0 - .dw 0x9640, 0xc09d, 0x967f, 0xc09d, 0x21, 0 - .dw 0x96c0, 0xc09d, 0x96ff, 0xc09d, 0x21, 0 - .dw 0x9740, 0xc09d, 0x977f, 0xc09d, 0x21, 0 - .dw 0x97c0, 0xc09d, 0x97ff, 0xc09d, 0x21, 0 - .dw 0x9840, 0xc09d, 0x987f, 0xc09d, 0x21, 0 - .dw 0x98c0, 0xc09d, 0x98ff, 0xc09d, 0x21, 0 - .dw 0x9940, 0xc09d, 0x997f, 0xc09d, 0x21, 0 - .dw 0x99c0, 0xc09d, 0x9fff, 0xc09d, 0x21, 0 - .dw 0xa040, 0xc09d, 0xa07f, 0xc09d, 0x21, 0 - .dw 0xa0c0, 0xc09d, 0xa0ff, 0xc09d, 0x21, 0 - .dw 0xa140, 0xc09d, 0xa17f, 0xc09d, 0x21, 0 - .dw 0xa1c0, 0xc09d, 0xa1ff, 0xc09d, 0x21, 0 - .dw 0xa240, 0xc09d, 0xa27f, 0xc09d, 0x21, 0 - .dw 0xa2c0, 0xc09d, 0xa2ff, 0xc09d, 0x21, 0 - .dw 0xa340, 0xc09d, 0xa37f, 0xc09d, 0x21, 0 - .dw 0xa3c0, 0xc09d, 0xa3ff, 0xc09d, 0x21, 0 - .dw 0xa440, 0xc09d, 0xa47f, 0xc09d, 0x21, 0 - .dw 0xa4c0, 0xc09d, 0xa4ff, 0xc09d, 0x21, 0 - .dw 0xa540, 0xc09d, 0xa57f, 0xc09d, 0x21, 0 - .dw 0xa5c0, 0xc09d, 0xa5ff, 0xc09d, 0x21, 0 - .dw 0xa640, 0xc09d, 0xa67f, 0xc09d, 0x21, 0 - .dw 0xa6c0, 0xc09d, 0xa6ff, 0xc09d, 0x21, 0 - .dw 0xa740, 0xc09d, 0xa77f, 0xc09d, 0x21, 0 - .dw 0xa7c0, 0xc09d, 0xa7ff, 0xc09d, 0x21, 0 - .dw 0xa840, 0xc09d, 0xa87f, 0xc09d, 0x21, 0 - .dw 0xa8c0, 0xc09d, 0xa8ff, 0xc09d, 0x21, 0 - .dw 0xa940, 0xc09d, 0xa97f, 0xc09d, 0x21, 0 - .dw 0xa9c0, 0xc09d, 0xa9ff, 0xc09d, 0x21, 0 - .dw 0xaa40, 0xc09d, 0xaa7f, 0xc09d, 0x21, 0 - .dw 0xaac0, 0xc09d, 0xaaff, 0xc09d, 0x21, 0 - .dw 0xab40, 0xc09d, 0xab7f, 0xc09d, 0x21, 0 - .dw 0xabc0, 0xc09d, 0xabff, 0xc09d, 0x21, 0 - .dw 0xac40, 0xc09d, 0xac7f, 0xc09d, 0x21, 0 - .dw 0xacc0, 0xc09d, 0xacff, 0xc09d, 0x21, 0 - .dw 0xad40, 0xc09d, 0xad7f, 0xc09d, 0x21, 0 - .dw 0xadc0, 0xc09d, 0xadff, 0xc09d, 0x21, 0 - .dw 0xae40, 0xc09d, 0xae7f, 0xc09d, 0x21, 0 - .dw 0xaec0, 0xc09d, 0xaeff, 0xc09d, 0x21, 0 - .dw 0xaf40, 0xc09d, 0xaf7f, 0xc09d, 0x21, 0 - .dw 0xafc0, 0xc09d, 0xafff, 0xc09d, 0x21, 0 - .dw 0xb040, 0xc09d, 0xb07f, 0xc09d, 0x21, 0 - .dw 0xb0c0, 0xc09d, 0xb0ff, 0xc09d, 0x21, 0 - .dw 0xb140, 0xc09d, 0xb17f, 0xc09d, 0x21, 0 - .dw 0xb1c0, 0xc09d, 0xb1ff, 0xc09d, 0x21, 0 - .dw 0xb240, 0xc09d, 0xb27f, 0xc09d, 0x21, 0 - .dw 0xb2c0, 0xc09d, 0xb2ff, 0xc09d, 0x21, 0 - .dw 0xb340, 0xc09d, 0xb37f, 0xc09d, 0x21, 0 - .dw 0xb3c0, 0xc09d, 0xb3ff, 0xc09d, 0x21, 0 - .dw 0xb440, 0xc09d, 0xb47f, 0xc09d, 0x21, 0 - .dw 0xb4c0, 0xc09d, 0xb4ff, 0xc09d, 0x21, 0 - .dw 0xb540, 0xc09d, 0xb57f, 0xc09d, 0x21, 0 - .dw 0xb5c0, 0xc09d, 0xb5ff, 0xc09d, 0x21, 0 - .dw 0xb640, 0xc09d, 0xb67f, 0xc09d, 0x21, 0 - .dw 0xb6c0, 0xc09d, 0xb6ff, 0xc09d, 0x21, 0 - .dw 0xb740, 0xc09d, 0xb77f, 0xc09d, 0x21, 0 - .dw 0xb7c0, 0xc09d, 0xb7ff, 0xc09d, 0x21, 0 - .dw 0xb840, 0xc09d, 0xb87f, 0xc09d, 0x21, 0 - .dw 0xb8c0, 0xc09d, 0xb8ff, 0xc09d, 0x21, 0 - .dw 0xb940, 0xc09d, 0xb97f, 0xc09d, 0x21, 0 - .dw 0xb9c0, 0xc09d, 0xbfff, 0xc09d, 0x21, 0 - .dw 0xc040, 0xc09d, 0xc07f, 0xc09d, 0x21, 0 - .dw 0xc0c0, 0xc09d, 0xc0ff, 0xc09d, 0x21, 0 - .dw 0xc140, 0xc09d, 0xc17f, 0xc09d, 0x21, 0 - .dw 0xc1c0, 0xc09d, 0xc1ff, 0xc09d, 0x21, 0 - .dw 0xc240, 0xc09d, 0xc27f, 0xc09d, 0x21, 0 - .dw 0xc2c0, 0xc09d, 0xc2ff, 0xc09d, 0x21, 0 - .dw 0xc340, 0xc09d, 0xc37f, 0xc09d, 0x21, 0 - .dw 0xc3c0, 0xc09d, 0xc3ff, 0xc09d, 0x21, 0 - .dw 0xc440, 0xc09d, 0xc47f, 0xc09d, 0x21, 0 - .dw 0xc4c0, 0xc09d, 0xc4ff, 0xc09d, 0x21, 0 - .dw 0xc540, 0xc09d, 0xc57f, 0xc09d, 0x21, 0 - .dw 0xc5c0, 0xc09d, 0xc5ff, 0xc09d, 0x21, 0 - .dw 0xc640, 0xc09d, 0xc67f, 0xc09d, 0x21, 0 - .dw 0xc6c0, 0xc09d, 0xc6ff, 0xc09d, 0x21, 0 - .dw 0xc740, 0xc09d, 0xc77f, 0xc09d, 0x21, 0 - .dw 0xc7c0, 0xc09d, 0xc7ff, 0xc09d, 0x21, 0 - .dw 0xc840, 0xc09d, 0xc87f, 0xc09d, 0x21, 0 - .dw 0xc8c0, 0xc09d, 0xc8ff, 0xc09d, 0x21, 0 - .dw 0xc940, 0xc09d, 0xc97f, 0xc09d, 0x21, 0 - .dw 0xc9c0, 0xc09d, 0xc9ff, 0xc09d, 0x21, 0 - .dw 0xca40, 0xc09d, 0xca7f, 0xc09d, 0x21, 0 - .dw 0xcac0, 0xc09d, 0xcaff, 0xc09d, 0x21, 0 - .dw 0xcb40, 0xc09d, 0xcb7f, 0xc09d, 0x21, 0 - .dw 0xcbc0, 0xc09d, 0xcbff, 0xc09d, 0x21, 0 - .dw 0xcc40, 0xc09d, 0xcc7f, 0xc09d, 0x21, 0 - .dw 0xccc0, 0xc09d, 0xccff, 0xc09d, 0x21, 0 - .dw 0xcd40, 0xc09d, 0xcd7f, 0xc09d, 0x21, 0 - .dw 0xcdc0, 0xc09d, 0xcdff, 0xc09d, 0x21, 0 - .dw 0xce40, 0xc09d, 0xce7f, 0xc09d, 0x21, 0 - .dw 0xcec0, 0xc09d, 0xceff, 0xc09d, 0x21, 0 - .dw 0xcf40, 0xc09d, 0xcf7f, 0xc09d, 0x21, 0 - .dw 0xcfc0, 0xc09d, 0xcfff, 0xc09d, 0x21, 0 - .dw 0xd040, 0xc09d, 0xd07f, 0xc09d, 0x21, 0 - .dw 0xd0c0, 0xc09d, 0xd0ff, 0xc09d, 0x21, 0 - .dw 0xd140, 0xc09d, 0xd17f, 0xc09d, 0x21, 0 - .dw 0xd1c0, 0xc09d, 0xd1ff, 0xc09d, 0x21, 0 - .dw 0xd240, 0xc09d, 0xd27f, 0xc09d, 0x21, 0 - .dw 0xd2c0, 0xc09d, 0xd2ff, 0xc09d, 0x21, 0 - .dw 0xd340, 0xc09d, 0xd37f, 0xc09d, 0x21, 0 - .dw 0xd3c0, 0xc09d, 0xd3ff, 0xc09d, 0x21, 0 - .dw 0xd440, 0xc09d, 0xd47f, 0xc09d, 0x21, 0 - .dw 0xd4c0, 0xc09d, 0xd4ff, 0xc09d, 0x21, 0 - .dw 0xd540, 0xc09d, 0xd57f, 0xc09d, 0x21, 0 - .dw 0xd5c0, 0xc09d, 0xd5ff, 0xc09d, 0x21, 0 - .dw 0xd640, 0xc09d, 0xd67f, 0xc09d, 0x21, 0 - .dw 0xd6c0, 0xc09d, 0xd6ff, 0xc09d, 0x21, 0 - .dw 0xd740, 0xc09d, 0xd77f, 0xc09d, 0x21, 0 - .dw 0xd7c0, 0xc09d, 0xd7ff, 0xc09d, 0x21, 0 - .dw 0xd840, 0xc09d, 0xd87f, 0xc09d, 0x21, 0 - .dw 0xd8c0, 0xc09d, 0xd8ff, 0xc09d, 0x21, 0 - .dw 0xd940, 0xc09d, 0xd97f, 0xc09d, 0x21, 0 - .dw 0xd9c0, 0xc09d, 0xdfff, 0xc09d, 0x21, 0 - .dw 0xe040, 0xc09d, 0xe07f, 0xc09d, 0x21, 0 - .dw 0xe0c0, 0xc09d, 0xe0ff, 0xc09d, 0x21, 0 - .dw 0xe140, 0xc09d, 0xe17f, 0xc09d, 0x21, 0 - .dw 0xe1c0, 0xc09d, 0xe1ff, 0xc09d, 0x21, 0 - .dw 0xe240, 0xc09d, 0xe27f, 0xc09d, 0x21, 0 - .dw 0xe2c0, 0xc09d, 0xe2ff, 0xc09d, 0x21, 0 - .dw 0xe340, 0xc09d, 0xe37f, 0xc09d, 0x21, 0 - .dw 0xe3c0, 0xc09d, 0xe3ff, 0xc09d, 0x21, 0 - .dw 0xe440, 0xc09d, 0xe47f, 0xc09d, 0x21, 0 - .dw 0xe4c0, 0xc09d, 0xe4ff, 0xc09d, 0x21, 0 - .dw 0xe540, 0xc09d, 0xe57f, 0xc09d, 0x21, 0 - .dw 0xe5c0, 0xc09d, 0xe5ff, 0xc09d, 0x21, 0 - .dw 0xe640, 0xc09d, 0xe67f, 0xc09d, 0x21, 0 - .dw 0xe6c0, 0xc09d, 0xe6ff, 0xc09d, 0x21, 0 - .dw 0xe740, 0xc09d, 0xe77f, 0xc09d, 0x21, 0 - .dw 0xe7c0, 0xc09d, 0xe7ff, 0xc09d, 0x21, 0 - .dw 0xe840, 0xc09d, 0xe87f, 0xc09d, 0x21, 0 - .dw 0xe8c0, 0xc09d, 0xe8ff, 0xc09d, 0x21, 0 - .dw 0xe940, 0xc09d, 0xe97f, 0xc09d, 0x21, 0 - .dw 0xe9c0, 0xc09d, 0xe9ff, 0xc09d, 0x21, 0 - .dw 0xea40, 0xc09d, 0xea7f, 0xc09d, 0x21, 0 - .dw 0xeac0, 0xc09d, 0xeaff, 0xc09d, 0x21, 0 - .dw 0xeb40, 0xc09d, 0xeb7f, 0xc09d, 0x21, 0 - .dw 0xebc0, 0xc09d, 0xebff, 0xc09d, 0x21, 0 - .dw 0xec40, 0xc09d, 0xec7f, 0xc09d, 0x21, 0 - .dw 0xecc0, 0xc09d, 0xecff, 0xc09d, 0x21, 0 - .dw 0xed40, 0xc09d, 0xed7f, 0xc09d, 0x21, 0 - .dw 0xedc0, 0xc09d, 0xedff, 0xc09d, 0x21, 0 - .dw 0xee40, 0xc09d, 0xee7f, 0xc09d, 0x21, 0 - .dw 0xeec0, 0xc09d, 0xeeff, 0xc09d, 0x21, 0 - .dw 0xef40, 0xc09d, 0xef7f, 0xc09d, 0x21, 0 - .dw 0xefc0, 0xc09d, 0xefff, 0xc09d, 0x21, 0 - .dw 0xf040, 0xc09d, 0xf07f, 0xc09d, 0x21, 0 - .dw 0xf0c0, 0xc09d, 0xf0ff, 0xc09d, 0x21, 0 - .dw 0xf140, 0xc09d, 0xf17f, 0xc09d, 0x21, 0 - .dw 0xf1c0, 0xc09d, 0xf1ff, 0xc09d, 0x21, 0 - .dw 0xf240, 0xc09d, 0xf27f, 0xc09d, 0x21, 0 - .dw 0xf2c0, 0xc09d, 0xf2ff, 0xc09d, 0x21, 0 - .dw 0xf340, 0xc09d, 0xf37f, 0xc09d, 0x21, 0 - .dw 0xf3c0, 0xc09d, 0xf3ff, 0xc09d, 0x21, 0 - .dw 0xf440, 0xc09d, 0xf47f, 0xc09d, 0x21, 0 - .dw 0xf4c0, 0xc09d, 0xf4ff, 0xc09d, 0x21, 0 - .dw 0xf540, 0xc09d, 0xf57f, 0xc09d, 0x21, 0 - .dw 0xf5c0, 0xc09d, 0xf5ff, 0xc09d, 0x21, 0 - .dw 0xf640, 0xc09d, 0xf67f, 0xc09d, 0x21, 0 - .dw 0xf6c0, 0xc09d, 0xf6ff, 0xc09d, 0x21, 0 - .dw 0xf740, 0xc09d, 0xf77f, 0xc09d, 0x21, 0 - .dw 0xf7c0, 0xc09d, 0xf7ff, 0xc09d, 0x21, 0 - .dw 0xf840, 0xc09d, 0xf87f, 0xc09d, 0x21, 0 - .dw 0xf8c0, 0xc09d, 0xf8ff, 0xc09d, 0x21, 0 - .dw 0xf940, 0xc09d, 0xf97f, 0xc09d, 0x21, 0 - .dw 0xf9c0, 0xc09d, 0xffff, 0xc09d, 0x21, 0 - .dw 0x0040, 0xc09e, 0x007f, 0xc09e, 0x21, 0 - .dw 0x00c0, 0xc09e, 0x00ff, 0xc09e, 0x21, 0 - .dw 0x0140, 0xc09e, 0x017f, 0xc09e, 0x21, 0 - .dw 0x01c0, 0xc09e, 0x01ff, 0xc09e, 0x21, 0 - .dw 0x0240, 0xc09e, 0x027f, 0xc09e, 0x21, 0 - .dw 0x02c0, 0xc09e, 0x02ff, 0xc09e, 0x21, 0 - .dw 0x0340, 0xc09e, 0x037f, 0xc09e, 0x21, 0 - .dw 0x03c0, 0xc09e, 0x03ff, 0xc09e, 0x21, 0 - .dw 0x0440, 0xc09e, 0x047f, 0xc09e, 0x21, 0 - .dw 0x04c0, 0xc09e, 0x04ff, 0xc09e, 0x21, 0 - .dw 0x0540, 0xc09e, 0x057f, 0xc09e, 0x21, 0 - .dw 0x05c0, 0xc09e, 0x05ff, 0xc09e, 0x21, 0 - .dw 0x0640, 0xc09e, 0x067f, 0xc09e, 0x21, 0 - .dw 0x06c0, 0xc09e, 0x06ff, 0xc09e, 0x21, 0 - .dw 0x0740, 0xc09e, 0x077f, 0xc09e, 0x21, 0 - .dw 0x07c0, 0xc09e, 0x07ff, 0xc09e, 0x21, 0 - .dw 0x0840, 0xc09e, 0x087f, 0xc09e, 0x21, 0 - .dw 0x08c0, 0xc09e, 0x08ff, 0xc09e, 0x21, 0 - .dw 0x0940, 0xc09e, 0x097f, 0xc09e, 0x21, 0 - .dw 0x09c0, 0xc09e, 0x09ff, 0xc09e, 0x21, 0 - .dw 0x0a40, 0xc09e, 0x0a7f, 0xc09e, 0x21, 0 - .dw 0x0ac0, 0xc09e, 0x0aff, 0xc09e, 0x21, 0 - .dw 0x0b40, 0xc09e, 0x0b7f, 0xc09e, 0x21, 0 - .dw 0x0bc0, 0xc09e, 0x0bff, 0xc09e, 0x21, 0 - .dw 0x0c40, 0xc09e, 0x0c7f, 0xc09e, 0x21, 0 - .dw 0x0cc0, 0xc09e, 0x0cff, 0xc09e, 0x21, 0 - .dw 0x0d40, 0xc09e, 0x0d7f, 0xc09e, 0x21, 0 - .dw 0x0dc0, 0xc09e, 0x0dff, 0xc09e, 0x21, 0 - .dw 0x0e40, 0xc09e, 0x0e7f, 0xc09e, 0x21, 0 - .dw 0x0ec0, 0xc09e, 0x0eff, 0xc09e, 0x21, 0 - .dw 0x0f40, 0xc09e, 0x0f7f, 0xc09e, 0x21, 0 - .dw 0x0fc0, 0xc09e, 0x0fff, 0xc09e, 0x21, 0 - .dw 0x1040, 0xc09e, 0x107f, 0xc09e, 0x21, 0 - .dw 0x10c0, 0xc09e, 0x10ff, 0xc09e, 0x21, 0 - .dw 0x1140, 0xc09e, 0x117f, 0xc09e, 0x21, 0 - .dw 0x11c0, 0xc09e, 0x11ff, 0xc09e, 0x21, 0 - .dw 0x1240, 0xc09e, 0x127f, 0xc09e, 0x21, 0 - .dw 0x12c0, 0xc09e, 0x12ff, 0xc09e, 0x21, 0 - .dw 0x1340, 0xc09e, 0x137f, 0xc09e, 0x21, 0 - .dw 0x13c0, 0xc09e, 0x13ff, 0xc09e, 0x21, 0 - .dw 0x1440, 0xc09e, 0x147f, 0xc09e, 0x21, 0 - .dw 0x14c0, 0xc09e, 0x14ff, 0xc09e, 0x21, 0 - .dw 0x1540, 0xc09e, 0x157f, 0xc09e, 0x21, 0 - .dw 0x15c0, 0xc09e, 0x15ff, 0xc09e, 0x21, 0 - .dw 0x1640, 0xc09e, 0x167f, 0xc09e, 0x21, 0 - .dw 0x16c0, 0xc09e, 0x16ff, 0xc09e, 0x21, 0 - .dw 0x1740, 0xc09e, 0x177f, 0xc09e, 0x21, 0 - .dw 0x17c0, 0xc09e, 0x17ff, 0xc09e, 0x21, 0 - .dw 0x1840, 0xc09e, 0x187f, 0xc09e, 0x21, 0 - .dw 0x18c0, 0xc09e, 0x18ff, 0xc09e, 0x21, 0 - .dw 0x1940, 0xc09e, 0x197f, 0xc09e, 0x21, 0 - .dw 0x19c0, 0xc09e, 0x1fff, 0xc09e, 0x21, 0 - .dw 0x2040, 0xc09e, 0x207f, 0xc09e, 0x21, 0 - .dw 0x20c0, 0xc09e, 0x20ff, 0xc09e, 0x21, 0 - .dw 0x2140, 0xc09e, 0x217f, 0xc09e, 0x21, 0 - .dw 0x21c0, 0xc09e, 0x21ff, 0xc09e, 0x21, 0 - .dw 0x2240, 0xc09e, 0x227f, 0xc09e, 0x21, 0 - .dw 0x22c0, 0xc09e, 0x22ff, 0xc09e, 0x21, 0 - .dw 0x2340, 0xc09e, 0x237f, 0xc09e, 0x21, 0 - .dw 0x23c0, 0xc09e, 0x23ff, 0xc09e, 0x21, 0 - .dw 0x2440, 0xc09e, 0x247f, 0xc09e, 0x21, 0 - .dw 0x24c0, 0xc09e, 0x24ff, 0xc09e, 0x21, 0 - .dw 0x2540, 0xc09e, 0x257f, 0xc09e, 0x21, 0 - .dw 0x25c0, 0xc09e, 0x25ff, 0xc09e, 0x21, 0 - .dw 0x2640, 0xc09e, 0x267f, 0xc09e, 0x21, 0 - .dw 0x26c0, 0xc09e, 0x26ff, 0xc09e, 0x21, 0 - .dw 0x2740, 0xc09e, 0x277f, 0xc09e, 0x21, 0 - .dw 0x27c0, 0xc09e, 0x27ff, 0xc09e, 0x21, 0 - .dw 0x2840, 0xc09e, 0x287f, 0xc09e, 0x21, 0 - .dw 0x28c0, 0xc09e, 0x28ff, 0xc09e, 0x21, 0 - .dw 0x2940, 0xc09e, 0x297f, 0xc09e, 0x21, 0 - .dw 0x29c0, 0xc09e, 0x29ff, 0xc09e, 0x21, 0 - .dw 0x2a40, 0xc09e, 0x2a7f, 0xc09e, 0x21, 0 - .dw 0x2ac0, 0xc09e, 0x2aff, 0xc09e, 0x21, 0 - .dw 0x2b40, 0xc09e, 0x2b7f, 0xc09e, 0x21, 0 - .dw 0x2bc0, 0xc09e, 0x2bff, 0xc09e, 0x21, 0 - .dw 0x2c40, 0xc09e, 0x2c7f, 0xc09e, 0x21, 0 - .dw 0x2cc0, 0xc09e, 0x2cff, 0xc09e, 0x21, 0 - .dw 0x2d40, 0xc09e, 0x2d7f, 0xc09e, 0x21, 0 - .dw 0x2dc0, 0xc09e, 0x2dff, 0xc09e, 0x21, 0 - .dw 0x2e40, 0xc09e, 0x2e7f, 0xc09e, 0x21, 0 - .dw 0x2ec0, 0xc09e, 0x2eff, 0xc09e, 0x21, 0 - .dw 0x2f40, 0xc09e, 0x2f7f, 0xc09e, 0x21, 0 - .dw 0x2fc0, 0xc09e, 0x2fff, 0xc09e, 0x21, 0 - .dw 0x3040, 0xc09e, 0x307f, 0xc09e, 0x21, 0 - .dw 0x30c0, 0xc09e, 0x30ff, 0xc09e, 0x21, 0 - .dw 0x3140, 0xc09e, 0x317f, 0xc09e, 0x21, 0 - .dw 0x31c0, 0xc09e, 0x31ff, 0xc09e, 0x21, 0 - .dw 0x3240, 0xc09e, 0x327f, 0xc09e, 0x21, 0 - .dw 0x32c0, 0xc09e, 0x32ff, 0xc09e, 0x21, 0 - .dw 0x3340, 0xc09e, 0x337f, 0xc09e, 0x21, 0 - .dw 0x33c0, 0xc09e, 0x33ff, 0xc09e, 0x21, 0 - .dw 0x3440, 0xc09e, 0x347f, 0xc09e, 0x21, 0 - .dw 0x34c0, 0xc09e, 0x34ff, 0xc09e, 0x21, 0 - .dw 0x3540, 0xc09e, 0x357f, 0xc09e, 0x21, 0 - .dw 0x35c0, 0xc09e, 0x35ff, 0xc09e, 0x21, 0 - .dw 0x3640, 0xc09e, 0x367f, 0xc09e, 0x21, 0 - .dw 0x36c0, 0xc09e, 0x36ff, 0xc09e, 0x21, 0 - .dw 0x3740, 0xc09e, 0x377f, 0xc09e, 0x21, 0 - .dw 0x37c0, 0xc09e, 0x37ff, 0xc09e, 0x21, 0 - .dw 0x3840, 0xc09e, 0x387f, 0xc09e, 0x21, 0 - .dw 0x38c0, 0xc09e, 0x38ff, 0xc09e, 0x21, 0 - .dw 0x3940, 0xc09e, 0x397f, 0xc09e, 0x21, 0 - .dw 0x39c0, 0xc09e, 0x3fff, 0xc09e, 0x21, 0 - .dw 0x4040, 0xc09e, 0x407f, 0xc09e, 0x21, 0 - .dw 0x40c0, 0xc09e, 0x40ff, 0xc09e, 0x21, 0 - .dw 0x4140, 0xc09e, 0x417f, 0xc09e, 0x21, 0 - .dw 0x41c0, 0xc09e, 0x41ff, 0xc09e, 0x21, 0 - .dw 0x4240, 0xc09e, 0x427f, 0xc09e, 0x21, 0 - .dw 0x42c0, 0xc09e, 0x42ff, 0xc09e, 0x21, 0 - .dw 0x4340, 0xc09e, 0x437f, 0xc09e, 0x21, 0 - .dw 0x43c0, 0xc09e, 0x43ff, 0xc09e, 0x21, 0 - .dw 0x4440, 0xc09e, 0x447f, 0xc09e, 0x21, 0 - .dw 0x44c0, 0xc09e, 0x44ff, 0xc09e, 0x21, 0 - .dw 0x4540, 0xc09e, 0x457f, 0xc09e, 0x21, 0 - .dw 0x45c0, 0xc09e, 0x45ff, 0xc09e, 0x21, 0 - .dw 0x4640, 0xc09e, 0x467f, 0xc09e, 0x21, 0 - .dw 0x46c0, 0xc09e, 0x46ff, 0xc09e, 0x21, 0 - .dw 0x4740, 0xc09e, 0x477f, 0xc09e, 0x21, 0 - .dw 0x47c0, 0xc09e, 0x47ff, 0xc09e, 0x21, 0 - .dw 0x4840, 0xc09e, 0x487f, 0xc09e, 0x21, 0 - .dw 0x48c0, 0xc09e, 0x48ff, 0xc09e, 0x21, 0 - .dw 0x4940, 0xc09e, 0x497f, 0xc09e, 0x21, 0 - .dw 0x49c0, 0xc09e, 0x49ff, 0xc09e, 0x21, 0 - .dw 0x4a40, 0xc09e, 0x4a7f, 0xc09e, 0x21, 0 - .dw 0x4ac0, 0xc09e, 0x4aff, 0xc09e, 0x21, 0 - .dw 0x4b40, 0xc09e, 0x4b7f, 0xc09e, 0x21, 0 - .dw 0x4bc0, 0xc09e, 0x4bff, 0xc09e, 0x21, 0 - .dw 0x4c40, 0xc09e, 0x4c7f, 0xc09e, 0x21, 0 - .dw 0x4cc0, 0xc09e, 0x4cff, 0xc09e, 0x21, 0 - .dw 0x4d40, 0xc09e, 0x4d7f, 0xc09e, 0x21, 0 - .dw 0x4dc0, 0xc09e, 0x4dff, 0xc09e, 0x21, 0 - .dw 0x4e40, 0xc09e, 0x4e7f, 0xc09e, 0x21, 0 - .dw 0x4ec0, 0xc09e, 0x4eff, 0xc09e, 0x21, 0 - .dw 0x4f40, 0xc09e, 0x4f7f, 0xc09e, 0x21, 0 - .dw 0x4fc0, 0xc09e, 0x4fff, 0xc09e, 0x21, 0 - .dw 0x5040, 0xc09e, 0x507f, 0xc09e, 0x21, 0 - .dw 0x50c0, 0xc09e, 0x50ff, 0xc09e, 0x21, 0 - .dw 0x5140, 0xc09e, 0x517f, 0xc09e, 0x21, 0 - .dw 0x51c0, 0xc09e, 0x51ff, 0xc09e, 0x21, 0 - .dw 0x5240, 0xc09e, 0x527f, 0xc09e, 0x21, 0 - .dw 0x52c0, 0xc09e, 0x52ff, 0xc09e, 0x21, 0 - .dw 0x5340, 0xc09e, 0x537f, 0xc09e, 0x21, 0 - .dw 0x53c0, 0xc09e, 0x53ff, 0xc09e, 0x21, 0 - .dw 0x5440, 0xc09e, 0x547f, 0xc09e, 0x21, 0 - .dw 0x54c0, 0xc09e, 0x54ff, 0xc09e, 0x21, 0 - .dw 0x5540, 0xc09e, 0x557f, 0xc09e, 0x21, 0 - .dw 0x55c0, 0xc09e, 0x55ff, 0xc09e, 0x21, 0 - .dw 0x5640, 0xc09e, 0x567f, 0xc09e, 0x21, 0 - .dw 0x56c0, 0xc09e, 0x56ff, 0xc09e, 0x21, 0 - .dw 0x5740, 0xc09e, 0x577f, 0xc09e, 0x21, 0 - .dw 0x57c0, 0xc09e, 0x57ff, 0xc09e, 0x21, 0 - .dw 0x5840, 0xc09e, 0x587f, 0xc09e, 0x21, 0 - .dw 0x58c0, 0xc09e, 0x58ff, 0xc09e, 0x21, 0 - .dw 0x5940, 0xc09e, 0x597f, 0xc09e, 0x21, 0 - .dw 0x59c0, 0xc09e, 0x5fff, 0xc09e, 0x21, 0 - .dw 0x6040, 0xc09e, 0x607f, 0xc09e, 0x21, 0 - .dw 0x60c0, 0xc09e, 0x60ff, 0xc09e, 0x21, 0 - .dw 0x6140, 0xc09e, 0x617f, 0xc09e, 0x21, 0 - .dw 0x61c0, 0xc09e, 0x61ff, 0xc09e, 0x21, 0 - .dw 0x6240, 0xc09e, 0x627f, 0xc09e, 0x21, 0 - .dw 0x62c0, 0xc09e, 0x62ff, 0xc09e, 0x21, 0 - .dw 0x6340, 0xc09e, 0x637f, 0xc09e, 0x21, 0 - .dw 0x63c0, 0xc09e, 0x63ff, 0xc09e, 0x21, 0 - .dw 0x6440, 0xc09e, 0x647f, 0xc09e, 0x21, 0 - .dw 0x64c0, 0xc09e, 0x64ff, 0xc09e, 0x21, 0 - .dw 0x6540, 0xc09e, 0x657f, 0xc09e, 0x21, 0 - .dw 0x65c0, 0xc09e, 0x65ff, 0xc09e, 0x21, 0 - .dw 0x6640, 0xc09e, 0x667f, 0xc09e, 0x21, 0 - .dw 0x66c0, 0xc09e, 0x66ff, 0xc09e, 0x21, 0 - .dw 0x6740, 0xc09e, 0x677f, 0xc09e, 0x21, 0 - .dw 0x67c0, 0xc09e, 0x67ff, 0xc09e, 0x21, 0 - .dw 0x6840, 0xc09e, 0x687f, 0xc09e, 0x21, 0 - .dw 0x68c0, 0xc09e, 0x68ff, 0xc09e, 0x21, 0 - .dw 0x6940, 0xc09e, 0x697f, 0xc09e, 0x21, 0 - .dw 0x69c0, 0xc09e, 0x69ff, 0xc09e, 0x21, 0 - .dw 0x6a40, 0xc09e, 0x6a7f, 0xc09e, 0x21, 0 - .dw 0x6ac0, 0xc09e, 0x6aff, 0xc09e, 0x21, 0 - .dw 0x6b40, 0xc09e, 0x6b7f, 0xc09e, 0x21, 0 - .dw 0x6bc0, 0xc09e, 0x6bff, 0xc09e, 0x21, 0 - .dw 0x6c40, 0xc09e, 0x6c7f, 0xc09e, 0x21, 0 - .dw 0x6cc0, 0xc09e, 0x6cff, 0xc09e, 0x21, 0 - .dw 0x6d40, 0xc09e, 0x6d7f, 0xc09e, 0x21, 0 - .dw 0x6dc0, 0xc09e, 0x6dff, 0xc09e, 0x21, 0 - .dw 0x6e40, 0xc09e, 0x6e7f, 0xc09e, 0x21, 0 - .dw 0x6ec0, 0xc09e, 0x6eff, 0xc09e, 0x21, 0 - .dw 0x6f40, 0xc09e, 0x6f7f, 0xc09e, 0x21, 0 - .dw 0x6fc0, 0xc09e, 0x6fff, 0xc09e, 0x21, 0 - .dw 0x7040, 0xc09e, 0x707f, 0xc09e, 0x21, 0 - .dw 0x70c0, 0xc09e, 0x70ff, 0xc09e, 0x21, 0 - .dw 0x7140, 0xc09e, 0x717f, 0xc09e, 0x21, 0 - .dw 0x71c0, 0xc09e, 0x71ff, 0xc09e, 0x21, 0 - .dw 0x7240, 0xc09e, 0x727f, 0xc09e, 0x21, 0 - .dw 0x72c0, 0xc09e, 0x72ff, 0xc09e, 0x21, 0 - .dw 0x7340, 0xc09e, 0x737f, 0xc09e, 0x21, 0 - .dw 0x73c0, 0xc09e, 0x73ff, 0xc09e, 0x21, 0 - .dw 0x7440, 0xc09e, 0x747f, 0xc09e, 0x21, 0 - .dw 0x74c0, 0xc09e, 0x74ff, 0xc09e, 0x21, 0 - .dw 0x7540, 0xc09e, 0x757f, 0xc09e, 0x21, 0 - .dw 0x75c0, 0xc09e, 0x75ff, 0xc09e, 0x21, 0 - .dw 0x7640, 0xc09e, 0x767f, 0xc09e, 0x21, 0 - .dw 0x76c0, 0xc09e, 0x76ff, 0xc09e, 0x21, 0 - .dw 0x7740, 0xc09e, 0x777f, 0xc09e, 0x21, 0 - .dw 0x77c0, 0xc09e, 0x77ff, 0xc09e, 0x21, 0 - .dw 0x7840, 0xc09e, 0x787f, 0xc09e, 0x21, 0 - .dw 0x78c0, 0xc09e, 0x78ff, 0xc09e, 0x21, 0 - .dw 0x7940, 0xc09e, 0x797f, 0xc09e, 0x21, 0 - .dw 0x79c0, 0xc09e, 0x7fff, 0xc09e, 0x21, 0 - .dw 0x8040, 0xc09e, 0x807f, 0xc09e, 0x21, 0 - .dw 0x80c0, 0xc09e, 0x80ff, 0xc09e, 0x21, 0 - .dw 0x8140, 0xc09e, 0x817f, 0xc09e, 0x21, 0 - .dw 0x81c0, 0xc09e, 0x81ff, 0xc09e, 0x21, 0 - .dw 0x8240, 0xc09e, 0x827f, 0xc09e, 0x21, 0 - .dw 0x82c0, 0xc09e, 0x82ff, 0xc09e, 0x21, 0 - .dw 0x8340, 0xc09e, 0x837f, 0xc09e, 0x21, 0 - .dw 0x83c0, 0xc09e, 0x83ff, 0xc09e, 0x21, 0 - .dw 0x8440, 0xc09e, 0x847f, 0xc09e, 0x21, 0 - .dw 0x84c0, 0xc09e, 0x84ff, 0xc09e, 0x21, 0 - .dw 0x8540, 0xc09e, 0x857f, 0xc09e, 0x21, 0 - .dw 0x85c0, 0xc09e, 0x85ff, 0xc09e, 0x21, 0 - .dw 0x8640, 0xc09e, 0x867f, 0xc09e, 0x21, 0 - .dw 0x86c0, 0xc09e, 0x86ff, 0xc09e, 0x21, 0 - .dw 0x8740, 0xc09e, 0x877f, 0xc09e, 0x21, 0 - .dw 0x87c0, 0xc09e, 0x87ff, 0xc09e, 0x21, 0 - .dw 0x8840, 0xc09e, 0x887f, 0xc09e, 0x21, 0 - .dw 0x88c0, 0xc09e, 0x88ff, 0xc09e, 0x21, 0 - .dw 0x8940, 0xc09e, 0x897f, 0xc09e, 0x21, 0 - .dw 0x89c0, 0xc09e, 0x89ff, 0xc09e, 0x21, 0 - .dw 0x8a40, 0xc09e, 0x8a7f, 0xc09e, 0x21, 0 - .dw 0x8ac0, 0xc09e, 0x8aff, 0xc09e, 0x21, 0 - .dw 0x8b40, 0xc09e, 0x8b7f, 0xc09e, 0x21, 0 - .dw 0x8bc0, 0xc09e, 0x8bff, 0xc09e, 0x21, 0 - .dw 0x8c40, 0xc09e, 0x8c7f, 0xc09e, 0x21, 0 - .dw 0x8cc0, 0xc09e, 0x8cff, 0xc09e, 0x21, 0 - .dw 0x8d40, 0xc09e, 0x8d7f, 0xc09e, 0x21, 0 - .dw 0x8dc0, 0xc09e, 0x8dff, 0xc09e, 0x21, 0 - .dw 0x8e40, 0xc09e, 0x8e7f, 0xc09e, 0x21, 0 - .dw 0x8ec0, 0xc09e, 0x8eff, 0xc09e, 0x21, 0 - .dw 0x8f40, 0xc09e, 0x8f7f, 0xc09e, 0x21, 0 - .dw 0x8fc0, 0xc09e, 0x8fff, 0xc09e, 0x21, 0 - .dw 0x9040, 0xc09e, 0x907f, 0xc09e, 0x21, 0 - .dw 0x90c0, 0xc09e, 0x90ff, 0xc09e, 0x21, 0 - .dw 0x9140, 0xc09e, 0x917f, 0xc09e, 0x21, 0 - .dw 0x91c0, 0xc09e, 0x91ff, 0xc09e, 0x21, 0 - .dw 0x9240, 0xc09e, 0x927f, 0xc09e, 0x21, 0 - .dw 0x92c0, 0xc09e, 0x92ff, 0xc09e, 0x21, 0 - .dw 0x9340, 0xc09e, 0x937f, 0xc09e, 0x21, 0 - .dw 0x93c0, 0xc09e, 0x93ff, 0xc09e, 0x21, 0 - .dw 0x9440, 0xc09e, 0x947f, 0xc09e, 0x21, 0 - .dw 0x94c0, 0xc09e, 0x94ff, 0xc09e, 0x21, 0 - .dw 0x9540, 0xc09e, 0x957f, 0xc09e, 0x21, 0 - .dw 0x95c0, 0xc09e, 0x95ff, 0xc09e, 0x21, 0 - .dw 0x9640, 0xc09e, 0x967f, 0xc09e, 0x21, 0 - .dw 0x96c0, 0xc09e, 0x96ff, 0xc09e, 0x21, 0 - .dw 0x9740, 0xc09e, 0x977f, 0xc09e, 0x21, 0 - .dw 0x97c0, 0xc09e, 0x97ff, 0xc09e, 0x21, 0 - .dw 0x9840, 0xc09e, 0x987f, 0xc09e, 0x21, 0 - .dw 0x98c0, 0xc09e, 0x98ff, 0xc09e, 0x21, 0 - .dw 0x9940, 0xc09e, 0x997f, 0xc09e, 0x21, 0 - .dw 0x99c0, 0xc09e, 0x9fff, 0xc09e, 0x21, 0 - .dw 0xa040, 0xc09e, 0xa07f, 0xc09e, 0x21, 0 - .dw 0xa0c0, 0xc09e, 0xa0ff, 0xc09e, 0x21, 0 - .dw 0xa140, 0xc09e, 0xa17f, 0xc09e, 0x21, 0 - .dw 0xa1c0, 0xc09e, 0xa1ff, 0xc09e, 0x21, 0 - .dw 0xa240, 0xc09e, 0xa27f, 0xc09e, 0x21, 0 - .dw 0xa2c0, 0xc09e, 0xa2ff, 0xc09e, 0x21, 0 - .dw 0xa340, 0xc09e, 0xa37f, 0xc09e, 0x21, 0 - .dw 0xa3c0, 0xc09e, 0xa3ff, 0xc09e, 0x21, 0 - .dw 0xa440, 0xc09e, 0xa47f, 0xc09e, 0x21, 0 - .dw 0xa4c0, 0xc09e, 0xa4ff, 0xc09e, 0x21, 0 - .dw 0xa540, 0xc09e, 0xa57f, 0xc09e, 0x21, 0 - .dw 0xa5c0, 0xc09e, 0xa5ff, 0xc09e, 0x21, 0 - .dw 0xa640, 0xc09e, 0xa67f, 0xc09e, 0x21, 0 - .dw 0xa6c0, 0xc09e, 0xa6ff, 0xc09e, 0x21, 0 - .dw 0xa740, 0xc09e, 0xa77f, 0xc09e, 0x21, 0 - .dw 0xa7c0, 0xc09e, 0xa7ff, 0xc09e, 0x21, 0 - .dw 0xa840, 0xc09e, 0xa87f, 0xc09e, 0x21, 0 - .dw 0xa8c0, 0xc09e, 0xa8ff, 0xc09e, 0x21, 0 - .dw 0xa940, 0xc09e, 0xa97f, 0xc09e, 0x21, 0 - .dw 0xa9c0, 0xc09e, 0xa9ff, 0xc09e, 0x21, 0 - .dw 0xaa40, 0xc09e, 0xaa7f, 0xc09e, 0x21, 0 - .dw 0xaac0, 0xc09e, 0xaaff, 0xc09e, 0x21, 0 - .dw 0xab40, 0xc09e, 0xab7f, 0xc09e, 0x21, 0 - .dw 0xabc0, 0xc09e, 0xabff, 0xc09e, 0x21, 0 - .dw 0xac40, 0xc09e, 0xac7f, 0xc09e, 0x21, 0 - .dw 0xacc0, 0xc09e, 0xacff, 0xc09e, 0x21, 0 - .dw 0xad40, 0xc09e, 0xad7f, 0xc09e, 0x21, 0 - .dw 0xadc0, 0xc09e, 0xadff, 0xc09e, 0x21, 0 - .dw 0xae40, 0xc09e, 0xae7f, 0xc09e, 0x21, 0 - .dw 0xaec0, 0xc09e, 0xaeff, 0xc09e, 0x21, 0 - .dw 0xaf40, 0xc09e, 0xaf7f, 0xc09e, 0x21, 0 - .dw 0xafc0, 0xc09e, 0xafff, 0xc09e, 0x21, 0 - .dw 0xb040, 0xc09e, 0xb07f, 0xc09e, 0x21, 0 - .dw 0xb0c0, 0xc09e, 0xb0ff, 0xc09e, 0x21, 0 - .dw 0xb140, 0xc09e, 0xb17f, 0xc09e, 0x21, 0 - .dw 0xb1c0, 0xc09e, 0xb1ff, 0xc09e, 0x21, 0 - .dw 0xb240, 0xc09e, 0xb27f, 0xc09e, 0x21, 0 - .dw 0xb2c0, 0xc09e, 0xb2ff, 0xc09e, 0x21, 0 - .dw 0xb340, 0xc09e, 0xb37f, 0xc09e, 0x21, 0 - .dw 0xb3c0, 0xc09e, 0xb3ff, 0xc09e, 0x21, 0 - .dw 0xb440, 0xc09e, 0xb47f, 0xc09e, 0x21, 0 - .dw 0xb4c0, 0xc09e, 0xb4ff, 0xc09e, 0x21, 0 - .dw 0xb540, 0xc09e, 0xb57f, 0xc09e, 0x21, 0 - .dw 0xb5c0, 0xc09e, 0xb5ff, 0xc09e, 0x21, 0 - .dw 0xb640, 0xc09e, 0xb67f, 0xc09e, 0x21, 0 - .dw 0xb6c0, 0xc09e, 0xb6ff, 0xc09e, 0x21, 0 - .dw 0xb740, 0xc09e, 0xb77f, 0xc09e, 0x21, 0 - .dw 0xb7c0, 0xc09e, 0xb7ff, 0xc09e, 0x21, 0 - .dw 0xb840, 0xc09e, 0xb87f, 0xc09e, 0x21, 0 - .dw 0xb8c0, 0xc09e, 0xb8ff, 0xc09e, 0x21, 0 - .dw 0xb940, 0xc09e, 0xb97f, 0xc09e, 0x21, 0 - .dw 0xb9c0, 0xc09e, 0xbfff, 0xc09e, 0x21, 0 - .dw 0xc040, 0xc09e, 0xc07f, 0xc09e, 0x21, 0 - .dw 0xc0c0, 0xc09e, 0xc0ff, 0xc09e, 0x21, 0 - .dw 0xc140, 0xc09e, 0xc17f, 0xc09e, 0x21, 0 - .dw 0xc1c0, 0xc09e, 0xc1ff, 0xc09e, 0x21, 0 - .dw 0xc240, 0xc09e, 0xc27f, 0xc09e, 0x21, 0 - .dw 0xc2c0, 0xc09e, 0xc2ff, 0xc09e, 0x21, 0 - .dw 0xc340, 0xc09e, 0xc37f, 0xc09e, 0x21, 0 - .dw 0xc3c0, 0xc09e, 0xc3ff, 0xc09e, 0x21, 0 - .dw 0xc440, 0xc09e, 0xc47f, 0xc09e, 0x21, 0 - .dw 0xc4c0, 0xc09e, 0xc4ff, 0xc09e, 0x21, 0 - .dw 0xc540, 0xc09e, 0xc57f, 0xc09e, 0x21, 0 - .dw 0xc5c0, 0xc09e, 0xc5ff, 0xc09e, 0x21, 0 - .dw 0xc640, 0xc09e, 0xc67f, 0xc09e, 0x21, 0 - .dw 0xc6c0, 0xc09e, 0xc6ff, 0xc09e, 0x21, 0 - .dw 0xc740, 0xc09e, 0xc77f, 0xc09e, 0x21, 0 - .dw 0xc7c0, 0xc09e, 0xc7ff, 0xc09e, 0x21, 0 - .dw 0xc840, 0xc09e, 0xc87f, 0xc09e, 0x21, 0 - .dw 0xc8c0, 0xc09e, 0xc8ff, 0xc09e, 0x21, 0 - .dw 0xc940, 0xc09e, 0xc97f, 0xc09e, 0x21, 0 - .dw 0xc9c0, 0xc09e, 0xc9ff, 0xc09e, 0x21, 0 - .dw 0xca40, 0xc09e, 0xca7f, 0xc09e, 0x21, 0 - .dw 0xcac0, 0xc09e, 0xcaff, 0xc09e, 0x21, 0 - .dw 0xcb40, 0xc09e, 0xcb7f, 0xc09e, 0x21, 0 - .dw 0xcbc0, 0xc09e, 0xcbff, 0xc09e, 0x21, 0 - .dw 0xcc40, 0xc09e, 0xcc7f, 0xc09e, 0x21, 0 - .dw 0xccc0, 0xc09e, 0xccff, 0xc09e, 0x21, 0 - .dw 0xcd40, 0xc09e, 0xcd7f, 0xc09e, 0x21, 0 - .dw 0xcdc0, 0xc09e, 0xcdff, 0xc09e, 0x21, 0 - .dw 0xce40, 0xc09e, 0xce7f, 0xc09e, 0x21, 0 - .dw 0xcec0, 0xc09e, 0xceff, 0xc09e, 0x21, 0 - .dw 0xcf40, 0xc09e, 0xcf7f, 0xc09e, 0x21, 0 - .dw 0xcfc0, 0xc09e, 0xcfff, 0xc09e, 0x21, 0 - .dw 0xd040, 0xc09e, 0xd07f, 0xc09e, 0x21, 0 - .dw 0xd0c0, 0xc09e, 0xd0ff, 0xc09e, 0x21, 0 - .dw 0xd140, 0xc09e, 0xd17f, 0xc09e, 0x21, 0 - .dw 0xd1c0, 0xc09e, 0xd1ff, 0xc09e, 0x21, 0 - .dw 0xd240, 0xc09e, 0xd27f, 0xc09e, 0x21, 0 - .dw 0xd2c0, 0xc09e, 0xd2ff, 0xc09e, 0x21, 0 - .dw 0xd340, 0xc09e, 0xd37f, 0xc09e, 0x21, 0 - .dw 0xd3c0, 0xc09e, 0xd3ff, 0xc09e, 0x21, 0 - .dw 0xd440, 0xc09e, 0xd47f, 0xc09e, 0x21, 0 - .dw 0xd4c0, 0xc09e, 0xd4ff, 0xc09e, 0x21, 0 - .dw 0xd540, 0xc09e, 0xd57f, 0xc09e, 0x21, 0 - .dw 0xd5c0, 0xc09e, 0xd5ff, 0xc09e, 0x21, 0 - .dw 0xd640, 0xc09e, 0xd67f, 0xc09e, 0x21, 0 - .dw 0xd6c0, 0xc09e, 0xd6ff, 0xc09e, 0x21, 0 - .dw 0xd740, 0xc09e, 0xd77f, 0xc09e, 0x21, 0 - .dw 0xd7c0, 0xc09e, 0xd7ff, 0xc09e, 0x21, 0 - .dw 0xd840, 0xc09e, 0xd87f, 0xc09e, 0x21, 0 - .dw 0xd8c0, 0xc09e, 0xd8ff, 0xc09e, 0x21, 0 - .dw 0xd940, 0xc09e, 0xd97f, 0xc09e, 0x21, 0 - .dw 0xd9c0, 0xc09e, 0xdfff, 0xc09e, 0x21, 0 - .dw 0xe040, 0xc09e, 0xe07f, 0xc09e, 0x21, 0 - .dw 0xe0c0, 0xc09e, 0xe0ff, 0xc09e, 0x21, 0 - .dw 0xe140, 0xc09e, 0xe17f, 0xc09e, 0x21, 0 - .dw 0xe1c0, 0xc09e, 0xe1ff, 0xc09e, 0x21, 0 - .dw 0xe240, 0xc09e, 0xe27f, 0xc09e, 0x21, 0 - .dw 0xe2c0, 0xc09e, 0xe2ff, 0xc09e, 0x21, 0 - .dw 0xe340, 0xc09e, 0xe37f, 0xc09e, 0x21, 0 - .dw 0xe3c0, 0xc09e, 0xe3ff, 0xc09e, 0x21, 0 - .dw 0xe440, 0xc09e, 0xe47f, 0xc09e, 0x21, 0 - .dw 0xe4c0, 0xc09e, 0xe4ff, 0xc09e, 0x21, 0 - .dw 0xe540, 0xc09e, 0xe57f, 0xc09e, 0x21, 0 - .dw 0xe5c0, 0xc09e, 0xe5ff, 0xc09e, 0x21, 0 - .dw 0xe640, 0xc09e, 0xe67f, 0xc09e, 0x21, 0 - .dw 0xe6c0, 0xc09e, 0xe6ff, 0xc09e, 0x21, 0 - .dw 0xe740, 0xc09e, 0xe77f, 0xc09e, 0x21, 0 - .dw 0xe7c0, 0xc09e, 0xe7ff, 0xc09e, 0x21, 0 - .dw 0xe840, 0xc09e, 0xe87f, 0xc09e, 0x21, 0 - .dw 0xe8c0, 0xc09e, 0xe8ff, 0xc09e, 0x21, 0 - .dw 0xe940, 0xc09e, 0xe97f, 0xc09e, 0x21, 0 - .dw 0xe9c0, 0xc09e, 0xe9ff, 0xc09e, 0x21, 0 - .dw 0xea40, 0xc09e, 0xea7f, 0xc09e, 0x21, 0 - .dw 0xeac0, 0xc09e, 0xeaff, 0xc09e, 0x21, 0 - .dw 0xeb40, 0xc09e, 0xeb7f, 0xc09e, 0x21, 0 - .dw 0xebc0, 0xc09e, 0xebff, 0xc09e, 0x21, 0 - .dw 0xec40, 0xc09e, 0xec7f, 0xc09e, 0x21, 0 - .dw 0xecc0, 0xc09e, 0xecff, 0xc09e, 0x21, 0 - .dw 0xed40, 0xc09e, 0xed7f, 0xc09e, 0x21, 0 - .dw 0xedc0, 0xc09e, 0xedff, 0xc09e, 0x21, 0 - .dw 0xee40, 0xc09e, 0xee7f, 0xc09e, 0x21, 0 - .dw 0xeec0, 0xc09e, 0xeeff, 0xc09e, 0x21, 0 - .dw 0xef40, 0xc09e, 0xef7f, 0xc09e, 0x21, 0 - .dw 0xefc0, 0xc09e, 0xefff, 0xc09e, 0x21, 0 - .dw 0xf040, 0xc09e, 0xf07f, 0xc09e, 0x21, 0 - .dw 0xf0c0, 0xc09e, 0xf0ff, 0xc09e, 0x21, 0 - .dw 0xf140, 0xc09e, 0xf17f, 0xc09e, 0x21, 0 - .dw 0xf1c0, 0xc09e, 0xf1ff, 0xc09e, 0x21, 0 - .dw 0xf240, 0xc09e, 0xf27f, 0xc09e, 0x21, 0 - .dw 0xf2c0, 0xc09e, 0xf2ff, 0xc09e, 0x21, 0 - .dw 0xf340, 0xc09e, 0xf37f, 0xc09e, 0x21, 0 - .dw 0xf3c0, 0xc09e, 0xf3ff, 0xc09e, 0x21, 0 - .dw 0xf440, 0xc09e, 0xf47f, 0xc09e, 0x21, 0 - .dw 0xf4c0, 0xc09e, 0xf4ff, 0xc09e, 0x21, 0 - .dw 0xf540, 0xc09e, 0xf57f, 0xc09e, 0x21, 0 - .dw 0xf5c0, 0xc09e, 0xf5ff, 0xc09e, 0x21, 0 - .dw 0xf640, 0xc09e, 0xf67f, 0xc09e, 0x21, 0 - .dw 0xf6c0, 0xc09e, 0xf6ff, 0xc09e, 0x21, 0 - .dw 0xf740, 0xc09e, 0xf77f, 0xc09e, 0x21, 0 - .dw 0xf7c0, 0xc09e, 0xf7ff, 0xc09e, 0x21, 0 - .dw 0xf840, 0xc09e, 0xf87f, 0xc09e, 0x21, 0 - .dw 0xf8c0, 0xc09e, 0xf8ff, 0xc09e, 0x21, 0 - .dw 0xf940, 0xc09e, 0xf97f, 0xc09e, 0x21, 0 - .dw 0xf9c0, 0xc09e, 0xffff, 0xc09e, 0x21, 0 - .dw 0x0040, 0xc09f, 0x007f, 0xc09f, 0x21, 0 - .dw 0x00c0, 0xc09f, 0x00ff, 0xc09f, 0x21, 0 - .dw 0x0140, 0xc09f, 0x017f, 0xc09f, 0x21, 0 - .dw 0x01c0, 0xc09f, 0x01ff, 0xc09f, 0x21, 0 - .dw 0x0240, 0xc09f, 0x027f, 0xc09f, 0x21, 0 - .dw 0x02c0, 0xc09f, 0x02ff, 0xc09f, 0x21, 0 - .dw 0x0340, 0xc09f, 0x037f, 0xc09f, 0x21, 0 - .dw 0x03c0, 0xc09f, 0x03ff, 0xc09f, 0x21, 0 - .dw 0x0440, 0xc09f, 0x047f, 0xc09f, 0x21, 0 - .dw 0x04c0, 0xc09f, 0x04ff, 0xc09f, 0x21, 0 - .dw 0x0540, 0xc09f, 0x057f, 0xc09f, 0x21, 0 - .dw 0x05c0, 0xc09f, 0x05ff, 0xc09f, 0x21, 0 - .dw 0x0640, 0xc09f, 0x067f, 0xc09f, 0x21, 0 - .dw 0x06c0, 0xc09f, 0x06ff, 0xc09f, 0x21, 0 - .dw 0x0740, 0xc09f, 0x077f, 0xc09f, 0x21, 0 - .dw 0x07c0, 0xc09f, 0x07ff, 0xc09f, 0x21, 0 - .dw 0x0840, 0xc09f, 0x087f, 0xc09f, 0x21, 0 - .dw 0x08c0, 0xc09f, 0x08ff, 0xc09f, 0x21, 0 - .dw 0x0940, 0xc09f, 0x097f, 0xc09f, 0x21, 0 - .dw 0x09c0, 0xc09f, 0x09ff, 0xc09f, 0x21, 0 - .dw 0x0a40, 0xc09f, 0x0a7f, 0xc09f, 0x21, 0 - .dw 0x0ac0, 0xc09f, 0x0aff, 0xc09f, 0x21, 0 - .dw 0x0b40, 0xc09f, 0x0b7f, 0xc09f, 0x21, 0 - .dw 0x0bc0, 0xc09f, 0x0bff, 0xc09f, 0x21, 0 - .dw 0x0c40, 0xc09f, 0x0c7f, 0xc09f, 0x21, 0 - .dw 0x0cc0, 0xc09f, 0x0cff, 0xc09f, 0x21, 0 - .dw 0x0d40, 0xc09f, 0x0d7f, 0xc09f, 0x21, 0 - .dw 0x0dc0, 0xc09f, 0x0dff, 0xc09f, 0x21, 0 - .dw 0x0e40, 0xc09f, 0x0e7f, 0xc09f, 0x21, 0 - .dw 0x0ec0, 0xc09f, 0x0eff, 0xc09f, 0x21, 0 - .dw 0x0f40, 0xc09f, 0x0f7f, 0xc09f, 0x21, 0 - .dw 0x0fc0, 0xc09f, 0x0fff, 0xc09f, 0x21, 0 - .dw 0x1040, 0xc09f, 0x107f, 0xc09f, 0x21, 0 - .dw 0x10c0, 0xc09f, 0x10ff, 0xc09f, 0x21, 0 - .dw 0x1140, 0xc09f, 0x117f, 0xc09f, 0x21, 0 - .dw 0x11c0, 0xc09f, 0x11ff, 0xc09f, 0x21, 0 - .dw 0x1240, 0xc09f, 0x127f, 0xc09f, 0x21, 0 - .dw 0x12c0, 0xc09f, 0x12ff, 0xc09f, 0x21, 0 - .dw 0x1340, 0xc09f, 0x137f, 0xc09f, 0x21, 0 - .dw 0x13c0, 0xc09f, 0x13ff, 0xc09f, 0x21, 0 - .dw 0x1440, 0xc09f, 0x147f, 0xc09f, 0x21, 0 - .dw 0x14c0, 0xc09f, 0x14ff, 0xc09f, 0x21, 0 - .dw 0x1540, 0xc09f, 0x157f, 0xc09f, 0x21, 0 - .dw 0x15c0, 0xc09f, 0x15ff, 0xc09f, 0x21, 0 - .dw 0x1640, 0xc09f, 0x167f, 0xc09f, 0x21, 0 - .dw 0x16c0, 0xc09f, 0x16ff, 0xc09f, 0x21, 0 - .dw 0x1740, 0xc09f, 0x177f, 0xc09f, 0x21, 0 - .dw 0x17c0, 0xc09f, 0x17ff, 0xc09f, 0x21, 0 - .dw 0x1840, 0xc09f, 0x187f, 0xc09f, 0x21, 0 - .dw 0x18c0, 0xc09f, 0x18ff, 0xc09f, 0x21, 0 - .dw 0x1940, 0xc09f, 0x197f, 0xc09f, 0x21, 0 - .dw 0x19c0, 0xc09f, 0x1fff, 0xc09f, 0x21, 0 - .dw 0x2040, 0xc09f, 0x207f, 0xc09f, 0x21, 0 - .dw 0x20c0, 0xc09f, 0x20ff, 0xc09f, 0x21, 0 - .dw 0x2140, 0xc09f, 0x217f, 0xc09f, 0x21, 0 - .dw 0x21c0, 0xc09f, 0x21ff, 0xc09f, 0x21, 0 - .dw 0x2240, 0xc09f, 0x227f, 0xc09f, 0x21, 0 - .dw 0x22c0, 0xc09f, 0x22ff, 0xc09f, 0x21, 0 - .dw 0x2340, 0xc09f, 0x237f, 0xc09f, 0x21, 0 - .dw 0x23c0, 0xc09f, 0x23ff, 0xc09f, 0x21, 0 - .dw 0x2440, 0xc09f, 0x247f, 0xc09f, 0x21, 0 - .dw 0x24c0, 0xc09f, 0x24ff, 0xc09f, 0x21, 0 - .dw 0x2540, 0xc09f, 0x257f, 0xc09f, 0x21, 0 - .dw 0x25c0, 0xc09f, 0x25ff, 0xc09f, 0x21, 0 - .dw 0x2640, 0xc09f, 0x267f, 0xc09f, 0x21, 0 - .dw 0x26c0, 0xc09f, 0x26ff, 0xc09f, 0x21, 0 - .dw 0x2740, 0xc09f, 0x277f, 0xc09f, 0x21, 0 - .dw 0x27c0, 0xc09f, 0x27ff, 0xc09f, 0x21, 0 - .dw 0x2840, 0xc09f, 0x287f, 0xc09f, 0x21, 0 - .dw 0x28c0, 0xc09f, 0x28ff, 0xc09f, 0x21, 0 - .dw 0x2940, 0xc09f, 0x297f, 0xc09f, 0x21, 0 - .dw 0x29c0, 0xc09f, 0x29ff, 0xc09f, 0x21, 0 - .dw 0x2a40, 0xc09f, 0x2a7f, 0xc09f, 0x21, 0 - .dw 0x2ac0, 0xc09f, 0x2aff, 0xc09f, 0x21, 0 - .dw 0x2b40, 0xc09f, 0x2b7f, 0xc09f, 0x21, 0 - .dw 0x2bc0, 0xc09f, 0x2bff, 0xc09f, 0x21, 0 - .dw 0x2c40, 0xc09f, 0x2c7f, 0xc09f, 0x21, 0 - .dw 0x2cc0, 0xc09f, 0x2cff, 0xc09f, 0x21, 0 - .dw 0x2d40, 0xc09f, 0x2d7f, 0xc09f, 0x21, 0 - .dw 0x2dc0, 0xc09f, 0x2dff, 0xc09f, 0x21, 0 - .dw 0x2e40, 0xc09f, 0x2e7f, 0xc09f, 0x21, 0 - .dw 0x2ec0, 0xc09f, 0x2eff, 0xc09f, 0x21, 0 - .dw 0x2f40, 0xc09f, 0x2f7f, 0xc09f, 0x21, 0 - .dw 0x2fc0, 0xc09f, 0x2fff, 0xc09f, 0x21, 0 - .dw 0x3040, 0xc09f, 0x307f, 0xc09f, 0x21, 0 - .dw 0x30c0, 0xc09f, 0x30ff, 0xc09f, 0x21, 0 - .dw 0x3140, 0xc09f, 0x317f, 0xc09f, 0x21, 0 - .dw 0x31c0, 0xc09f, 0x31ff, 0xc09f, 0x21, 0 - .dw 0x3240, 0xc09f, 0x327f, 0xc09f, 0x21, 0 - .dw 0x32c0, 0xc09f, 0x32ff, 0xc09f, 0x21, 0 - .dw 0x3340, 0xc09f, 0x337f, 0xc09f, 0x21, 0 - .dw 0x33c0, 0xc09f, 0x33ff, 0xc09f, 0x21, 0 - .dw 0x3440, 0xc09f, 0x347f, 0xc09f, 0x21, 0 - .dw 0x34c0, 0xc09f, 0x34ff, 0xc09f, 0x21, 0 - .dw 0x3540, 0xc09f, 0x357f, 0xc09f, 0x21, 0 - .dw 0x35c0, 0xc09f, 0x35ff, 0xc09f, 0x21, 0 - .dw 0x3640, 0xc09f, 0x367f, 0xc09f, 0x21, 0 - .dw 0x36c0, 0xc09f, 0x36ff, 0xc09f, 0x21, 0 - .dw 0x3740, 0xc09f, 0x377f, 0xc09f, 0x21, 0 - .dw 0x37c0, 0xc09f, 0x37ff, 0xc09f, 0x21, 0 - .dw 0x3840, 0xc09f, 0x387f, 0xc09f, 0x21, 0 - .dw 0x38c0, 0xc09f, 0x38ff, 0xc09f, 0x21, 0 - .dw 0x3940, 0xc09f, 0x397f, 0xc09f, 0x21, 0 - .dw 0x39c0, 0xc09f, 0x1fff, 0xc0c0, 0x21, 0 - .dw 0x3a00, 0xc0c0, 0x5fff, 0xc0c0, 0x21, 0 - .dw 0x7a00, 0xc0c0, 0x9fff, 0xc0c0, 0x21, 0 - .dw 0xba00, 0xc0c0, 0xdfff, 0xc0c0, 0x21, 0 - .dw 0xfa00, 0xc0c0, 0x1fff, 0xc0c1, 0x21, 0 - .dw 0x3a00, 0xc0c1, 0x5fff, 0xc0c1, 0x21, 0 - .dw 0x7a00, 0xc0c1, 0x9fff, 0xc0c1, 0x21, 0 - .dw 0xba00, 0xc0c1, 0xdfff, 0xc0c1, 0x21, 0 - .dw 0xfa00, 0xc0c1, 0x1fff, 0xc0c2, 0x21, 0 - .dw 0x3a00, 0xc0c2, 0x5fff, 0xc0c2, 0x21, 0 - .dw 0x7a00, 0xc0c2, 0x9fff, 0xc0c2, 0x21, 0 - .dw 0xba00, 0xc0c2, 0xdfff, 0xc0c2, 0x21, 0 - .dw 0xfa00, 0xc0c2, 0x1fff, 0xc0c3, 0x21, 0 - .dw 0x3a00, 0xc0c3, 0xffff, 0xc0c3, 0x21, 0 - .dw 0x1a00, 0xc0c4, 0x1fff, 0xc0c4, 0x21, 0 - .dw 0x3a00, 0xc0c4, 0x3fff, 0xc0c4, 0x21, 0 - .dw 0x5a00, 0xc0c4, 0x5fff, 0xc0c4, 0x21, 0 - .dw 0x7a00, 0xc0c4, 0x7fff, 0xc0c4, 0x21, 0 - .dw 0x9a00, 0xc0c4, 0x9fff, 0xc0c4, 0x21, 0 - .dw 0xba00, 0xc0c4, 0xbfff, 0xc0c4, 0x21, 0 - .dw 0xda00, 0xc0c4, 0xdfff, 0xc0c4, 0x21, 0 - .dw 0xfa00, 0xc0c4, 0xffff, 0xc0c4, 0x21, 0 - .dw 0x1a00, 0xc0c5, 0x1fff, 0xc0c5, 0x21, 0 - .dw 0x3a00, 0xc0c5, 0x3fff, 0xc0c5, 0x21, 0 - .dw 0x5a00, 0xc0c5, 0x5fff, 0xc0c5, 0x21, 0 - .dw 0x7a00, 0xc0c5, 0x7fff, 0xc0c5, 0x21, 0 - .dw 0x9a00, 0xc0c5, 0x9fff, 0xc0c5, 0x21, 0 - .dw 0xba00, 0xc0c5, 0xbfff, 0xc0c5, 0x21, 0 - .dw 0xda00, 0xc0c5, 0xdfff, 0xc0c5, 0x21, 0 - .dw 0xfa00, 0xc0c5, 0xffff, 0xc0c5, 0x21, 0 - .dw 0x1a00, 0xc0c6, 0x1fff, 0xc0c6, 0x21, 0 - .dw 0x3a00, 0xc0c6, 0x3fff, 0xc0c6, 0x21, 0 - .dw 0x5a00, 0xc0c6, 0x5fff, 0xc0c6, 0x21, 0 - .dw 0x7a00, 0xc0c6, 0x7fff, 0xc0c6, 0x21, 0 - .dw 0x9a00, 0xc0c6, 0x9fff, 0xc0c6, 0x21, 0 - .dw 0xba00, 0xc0c6, 0xbfff, 0xc0c6, 0x21, 0 - .dw 0xda00, 0xc0c6, 0xdfff, 0xc0c6, 0x21, 0 - .dw 0xfa00, 0xc0c6, 0xffff, 0xc0c6, 0x21, 0 - .dw 0x1a00, 0xc0c7, 0x1fff, 0xc0c7, 0x21, 0 - .dw 0x3a00, 0xc0c7, 0x1fff, 0xc0d0, 0x21, 0 - .dw 0x3a00, 0xc0d0, 0x5fff, 0xc0d0, 0x21, 0 - .dw 0x7a00, 0xc0d0, 0x9fff, 0xc0d0, 0x21, 0 - .dw 0xba00, 0xc0d0, 0xdfff, 0xc0d0, 0x21, 0 - .dw 0xfa00, 0xc0d0, 0x1fff, 0xc0d1, 0x21, 0 - .dw 0x3a00, 0xc0d1, 0x5fff, 0xc0d1, 0x21, 0 - .dw 0x7a00, 0xc0d1, 0x9fff, 0xc0d1, 0x21, 0 - .dw 0xba00, 0xc0d1, 0xdfff, 0xc0d1, 0x21, 0 - .dw 0xfa00, 0xc0d1, 0x1fff, 0xc0d2, 0x21, 0 - .dw 0x3a00, 0xc0d2, 0x5fff, 0xc0d2, 0x21, 0 - .dw 0x7a00, 0xc0d2, 0x9fff, 0xc0d2, 0x21, 0 - .dw 0xba00, 0xc0d2, 0xdfff, 0xc0d2, 0x21, 0 - .dw 0xfa00, 0xc0d2, 0xffff, 0xc0d3, 0x21, 0 - .dw 0x1a00, 0xc0d4, 0x1fff, 0xc0d4, 0x21, 0 - .dw 0x3a00, 0xc0d4, 0x3fff, 0xc0d4, 0x21, 0 - .dw 0x5a00, 0xc0d4, 0x5fff, 0xc0d4, 0x21, 0 - .dw 0x7a00, 0xc0d4, 0x7fff, 0xc0d4, 0x21, 0 - .dw 0x9a00, 0xc0d4, 0x9fff, 0xc0d4, 0x21, 0 - .dw 0xba00, 0xc0d4, 0xbfff, 0xc0d4, 0x21, 0 - .dw 0xda00, 0xc0d4, 0xdfff, 0xc0d4, 0x21, 0 - .dw 0xfa00, 0xc0d4, 0xffff, 0xc0d4, 0x21, 0 - .dw 0x1a00, 0xc0d5, 0x1fff, 0xc0d5, 0x21, 0 - .dw 0x3a00, 0xc0d5, 0x3fff, 0xc0d5, 0x21, 0 - .dw 0x5a00, 0xc0d5, 0x5fff, 0xc0d5, 0x21, 0 - .dw 0x7a00, 0xc0d5, 0x7fff, 0xc0d5, 0x21, 0 - .dw 0x9a00, 0xc0d5, 0x9fff, 0xc0d5, 0x21, 0 - .dw 0xba00, 0xc0d5, 0xbfff, 0xc0d5, 0x21, 0 - .dw 0xda00, 0xc0d5, 0xdfff, 0xc0d5, 0x21, 0 - .dw 0xfa00, 0xc0d5, 0xffff, 0xc0d5, 0x21, 0 - .dw 0x1a00, 0xc0d6, 0x1fff, 0xc0d6, 0x21, 0 - .dw 0x3a00, 0xc0d6, 0x3fff, 0xc0d6, 0x21, 0 - .dw 0x5a00, 0xc0d6, 0x5fff, 0xc0d6, 0x21, 0 - .dw 0x7a00, 0xc0d6, 0x7fff, 0xc0d6, 0x21, 0 - .dw 0x9a00, 0xc0d6, 0x9fff, 0xc0d6, 0x21, 0 - .dw 0xba00, 0xc0d6, 0xbfff, 0xc0d6, 0x21, 0 - .dw 0xda00, 0xc0d6, 0xdfff, 0xc0d6, 0x21, 0 - .dw 0xfa00, 0xc0d6, 0xffff, 0xc0d6, 0x21, 0 - .dw 0x1a00, 0xc0d7, 0x1fff, 0xc0d7, 0x21, 0 - .dw 0x3a00, 0xc0d7, 0xffff, 0xc0ff, 0x21, 0 - .dw 0x1a00, 0xc100, 0x1fff, 0xc100, 0x21, 0 - .dw 0x3a00, 0xc100, 0x3fff, 0xc100, 0x21, 0 - .dw 0x5a00, 0xc100, 0x5fff, 0xc100, 0x21, 0 - .dw 0x7a00, 0xc100, 0x7fff, 0xc100, 0x21, 0 - .dw 0x9a00, 0xc100, 0x9fff, 0xc100, 0x21, 0 - .dw 0xba00, 0xc100, 0xbfff, 0xc100, 0x21, 0 - .dw 0xda00, 0xc100, 0xdfff, 0xc100, 0x21, 0 - .dw 0xfa00, 0xc100, 0xffff, 0xc100, 0x21, 0 - .dw 0x1a00, 0xc101, 0x1fff, 0xc101, 0x21, 0 - .dw 0x3a00, 0xc101, 0x3fff, 0xc101, 0x21, 0 - .dw 0x5a00, 0xc101, 0x5fff, 0xc101, 0x21, 0 - .dw 0x7a00, 0xc101, 0x7fff, 0xc101, 0x21, 0 - .dw 0x9a00, 0xc101, 0x9fff, 0xc101, 0x21, 0 - .dw 0xba00, 0xc101, 0xbfff, 0xc101, 0x21, 0 - .dw 0xda00, 0xc101, 0xdfff, 0xc101, 0x21, 0 - .dw 0xfa00, 0xc101, 0xffff, 0xc101, 0x21, 0 - .dw 0x1a00, 0xc102, 0x1fff, 0xc102, 0x21, 0 - .dw 0x3a00, 0xc102, 0x3fff, 0xc102, 0x21, 0 - .dw 0x5a00, 0xc102, 0x5fff, 0xc102, 0x21, 0 - .dw 0x7a00, 0xc102, 0x7fff, 0xc102, 0x21, 0 - .dw 0x9a00, 0xc102, 0x9fff, 0xc102, 0x21, 0 - .dw 0xba00, 0xc102, 0xbfff, 0xc102, 0x21, 0 - .dw 0xda00, 0xc102, 0xdfff, 0xc102, 0x21, 0 - .dw 0xfa00, 0xc102, 0xffff, 0xc102, 0x21, 0 - .dw 0x1a00, 0xc103, 0x1fff, 0xc103, 0x21, 0 - .dw 0x3a00, 0xc103, 0xffff, 0xc103, 0x21, 0 - .dw 0x1a00, 0xc104, 0x1fff, 0xc104, 0x21, 0 - .dw 0x3a00, 0xc104, 0x3fff, 0xc104, 0x21, 0 - .dw 0x5a00, 0xc104, 0x5fff, 0xc104, 0x21, 0 - .dw 0x7a00, 0xc104, 0x7fff, 0xc104, 0x21, 0 - .dw 0x9a00, 0xc104, 0x9fff, 0xc104, 0x21, 0 - .dw 0xba00, 0xc104, 0xbfff, 0xc104, 0x21, 0 - .dw 0xda00, 0xc104, 0xdfff, 0xc104, 0x21, 0 - .dw 0xfa00, 0xc104, 0xffff, 0xc104, 0x21, 0 - .dw 0x1a00, 0xc105, 0x1fff, 0xc105, 0x21, 0 - .dw 0x3a00, 0xc105, 0x3fff, 0xc105, 0x21, 0 - .dw 0x5a00, 0xc105, 0x5fff, 0xc105, 0x21, 0 - .dw 0x7a00, 0xc105, 0x7fff, 0xc105, 0x21, 0 - .dw 0x9a00, 0xc105, 0x9fff, 0xc105, 0x21, 0 - .dw 0xba00, 0xc105, 0xbfff, 0xc105, 0x21, 0 - .dw 0xda00, 0xc105, 0xdfff, 0xc105, 0x21, 0 - .dw 0xfa00, 0xc105, 0xffff, 0xc105, 0x21, 0 - .dw 0x1a00, 0xc106, 0x1fff, 0xc106, 0x21, 0 - .dw 0x3a00, 0xc106, 0x3fff, 0xc106, 0x21, 0 - .dw 0x5a00, 0xc106, 0x5fff, 0xc106, 0x21, 0 - .dw 0x7a00, 0xc106, 0x7fff, 0xc106, 0x21, 0 - .dw 0x9a00, 0xc106, 0x9fff, 0xc106, 0x21, 0 - .dw 0xba00, 0xc106, 0xbfff, 0xc106, 0x21, 0 - .dw 0xda00, 0xc106, 0xdfff, 0xc106, 0x21, 0 - .dw 0xfa00, 0xc106, 0xffff, 0xc106, 0x21, 0 - .dw 0x1a00, 0xc107, 0x1fff, 0xc107, 0x21, 0 - .dw 0x3a00, 0xc107, 0x1fff, 0xc108, 0x21, 0 - .dw 0x2040, 0xc108, 0x207f, 0xc108, 0x21, 0 - .dw 0x20c0, 0xc108, 0x20ff, 0xc108, 0x21, 0 - .dw 0x2140, 0xc108, 0x217f, 0xc108, 0x21, 0 - .dw 0x21c0, 0xc108, 0x21ff, 0xc108, 0x21, 0 - .dw 0x2240, 0xc108, 0x227f, 0xc108, 0x21, 0 - .dw 0x22c0, 0xc108, 0x22ff, 0xc108, 0x21, 0 - .dw 0x2340, 0xc108, 0x237f, 0xc108, 0x21, 0 - .dw 0x23c0, 0xc108, 0x23ff, 0xc108, 0x21, 0 - .dw 0x2440, 0xc108, 0x247f, 0xc108, 0x21, 0 - .dw 0x24c0, 0xc108, 0x24ff, 0xc108, 0x21, 0 - .dw 0x2540, 0xc108, 0x257f, 0xc108, 0x21, 0 - .dw 0x25c0, 0xc108, 0x25ff, 0xc108, 0x21, 0 - .dw 0x2640, 0xc108, 0x267f, 0xc108, 0x21, 0 - .dw 0x26c0, 0xc108, 0x26ff, 0xc108, 0x21, 0 - .dw 0x2740, 0xc108, 0x277f, 0xc108, 0x21, 0 - .dw 0x27c0, 0xc108, 0x27ff, 0xc108, 0x21, 0 - .dw 0x2840, 0xc108, 0x287f, 0xc108, 0x21, 0 - .dw 0x28c0, 0xc108, 0x28ff, 0xc108, 0x21, 0 - .dw 0x2940, 0xc108, 0x297f, 0xc108, 0x21, 0 - .dw 0x29c0, 0xc108, 0x29ff, 0xc108, 0x21, 0 - .dw 0x2a40, 0xc108, 0x2a7f, 0xc108, 0x21, 0 - .dw 0x2ac0, 0xc108, 0x2aff, 0xc108, 0x21, 0 - .dw 0x2b40, 0xc108, 0x2b7f, 0xc108, 0x21, 0 - .dw 0x2bc0, 0xc108, 0x2bff, 0xc108, 0x21, 0 - .dw 0x2c40, 0xc108, 0x2c7f, 0xc108, 0x21, 0 - .dw 0x2cc0, 0xc108, 0x2cff, 0xc108, 0x21, 0 - .dw 0x2d40, 0xc108, 0x2d7f, 0xc108, 0x21, 0 - .dw 0x2dc0, 0xc108, 0x2dff, 0xc108, 0x21, 0 - .dw 0x2e40, 0xc108, 0x2e7f, 0xc108, 0x21, 0 - .dw 0x2ec0, 0xc108, 0x2eff, 0xc108, 0x21, 0 - .dw 0x2f40, 0xc108, 0x2f7f, 0xc108, 0x21, 0 - .dw 0x2fc0, 0xc108, 0x2fff, 0xc108, 0x21, 0 - .dw 0x3040, 0xc108, 0x307f, 0xc108, 0x21, 0 - .dw 0x30c0, 0xc108, 0x30ff, 0xc108, 0x21, 0 - .dw 0x3140, 0xc108, 0x317f, 0xc108, 0x21, 0 - .dw 0x31c0, 0xc108, 0x31ff, 0xc108, 0x21, 0 - .dw 0x3240, 0xc108, 0x327f, 0xc108, 0x21, 0 - .dw 0x32c0, 0xc108, 0x32ff, 0xc108, 0x21, 0 - .dw 0x3340, 0xc108, 0x337f, 0xc108, 0x21, 0 - .dw 0x33c0, 0xc108, 0x33ff, 0xc108, 0x21, 0 - .dw 0x3440, 0xc108, 0x347f, 0xc108, 0x21, 0 - .dw 0x34c0, 0xc108, 0x34ff, 0xc108, 0x21, 0 - .dw 0x3540, 0xc108, 0x357f, 0xc108, 0x21, 0 - .dw 0x35c0, 0xc108, 0x35ff, 0xc108, 0x21, 0 - .dw 0x3640, 0xc108, 0x367f, 0xc108, 0x21, 0 - .dw 0x36c0, 0xc108, 0x36ff, 0xc108, 0x21, 0 - .dw 0x3740, 0xc108, 0x377f, 0xc108, 0x21, 0 - .dw 0x37c0, 0xc108, 0x37ff, 0xc108, 0x21, 0 - .dw 0x3840, 0xc108, 0x387f, 0xc108, 0x21, 0 - .dw 0x38c0, 0xc108, 0x38ff, 0xc108, 0x21, 0 - .dw 0x3940, 0xc108, 0x397f, 0xc108, 0x21, 0 - .dw 0x39c0, 0xc108, 0x5fff, 0xc108, 0x21, 0 - .dw 0x6040, 0xc108, 0x607f, 0xc108, 0x21, 0 - .dw 0x60c0, 0xc108, 0x60ff, 0xc108, 0x21, 0 - .dw 0x6140, 0xc108, 0x617f, 0xc108, 0x21, 0 - .dw 0x61c0, 0xc108, 0x61ff, 0xc108, 0x21, 0 - .dw 0x6240, 0xc108, 0x627f, 0xc108, 0x21, 0 - .dw 0x62c0, 0xc108, 0x62ff, 0xc108, 0x21, 0 - .dw 0x6340, 0xc108, 0x637f, 0xc108, 0x21, 0 - .dw 0x63c0, 0xc108, 0x63ff, 0xc108, 0x21, 0 - .dw 0x6440, 0xc108, 0x647f, 0xc108, 0x21, 0 - .dw 0x64c0, 0xc108, 0x64ff, 0xc108, 0x21, 0 - .dw 0x6540, 0xc108, 0x657f, 0xc108, 0x21, 0 - .dw 0x65c0, 0xc108, 0x65ff, 0xc108, 0x21, 0 - .dw 0x6640, 0xc108, 0x667f, 0xc108, 0x21, 0 - .dw 0x66c0, 0xc108, 0x66ff, 0xc108, 0x21, 0 - .dw 0x6740, 0xc108, 0x677f, 0xc108, 0x21, 0 - .dw 0x67c0, 0xc108, 0x67ff, 0xc108, 0x21, 0 - .dw 0x6840, 0xc108, 0x687f, 0xc108, 0x21, 0 - .dw 0x68c0, 0xc108, 0x68ff, 0xc108, 0x21, 0 - .dw 0x6940, 0xc108, 0x697f, 0xc108, 0x21, 0 - .dw 0x69c0, 0xc108, 0x69ff, 0xc108, 0x21, 0 - .dw 0x6a40, 0xc108, 0x6a7f, 0xc108, 0x21, 0 - .dw 0x6ac0, 0xc108, 0x6aff, 0xc108, 0x21, 0 - .dw 0x6b40, 0xc108, 0x6b7f, 0xc108, 0x21, 0 - .dw 0x6bc0, 0xc108, 0x6bff, 0xc108, 0x21, 0 - .dw 0x6c40, 0xc108, 0x6c7f, 0xc108, 0x21, 0 - .dw 0x6cc0, 0xc108, 0x6cff, 0xc108, 0x21, 0 - .dw 0x6d40, 0xc108, 0x6d7f, 0xc108, 0x21, 0 - .dw 0x6dc0, 0xc108, 0x6dff, 0xc108, 0x21, 0 - .dw 0x6e40, 0xc108, 0x6e7f, 0xc108, 0x21, 0 - .dw 0x6ec0, 0xc108, 0x6eff, 0xc108, 0x21, 0 - .dw 0x6f40, 0xc108, 0x6f7f, 0xc108, 0x21, 0 - .dw 0x6fc0, 0xc108, 0x6fff, 0xc108, 0x21, 0 - .dw 0x7040, 0xc108, 0x707f, 0xc108, 0x21, 0 - .dw 0x70c0, 0xc108, 0x70ff, 0xc108, 0x21, 0 - .dw 0x7140, 0xc108, 0x717f, 0xc108, 0x21, 0 - .dw 0x71c0, 0xc108, 0x71ff, 0xc108, 0x21, 0 - .dw 0x7240, 0xc108, 0x727f, 0xc108, 0x21, 0 - .dw 0x72c0, 0xc108, 0x72ff, 0xc108, 0x21, 0 - .dw 0x7340, 0xc108, 0x737f, 0xc108, 0x21, 0 - .dw 0x73c0, 0xc108, 0x73ff, 0xc108, 0x21, 0 - .dw 0x7440, 0xc108, 0x747f, 0xc108, 0x21, 0 - .dw 0x74c0, 0xc108, 0x74ff, 0xc108, 0x21, 0 - .dw 0x7540, 0xc108, 0x757f, 0xc108, 0x21, 0 - .dw 0x75c0, 0xc108, 0x75ff, 0xc108, 0x21, 0 - .dw 0x7640, 0xc108, 0x767f, 0xc108, 0x21, 0 - .dw 0x76c0, 0xc108, 0x76ff, 0xc108, 0x21, 0 - .dw 0x7740, 0xc108, 0x777f, 0xc108, 0x21, 0 - .dw 0x77c0, 0xc108, 0x77ff, 0xc108, 0x21, 0 - .dw 0x7840, 0xc108, 0x787f, 0xc108, 0x21, 0 - .dw 0x78c0, 0xc108, 0x78ff, 0xc108, 0x21, 0 - .dw 0x7940, 0xc108, 0x797f, 0xc108, 0x21, 0 - .dw 0x79c0, 0xc108, 0x9fff, 0xc108, 0x21, 0 - .dw 0xa040, 0xc108, 0xa07f, 0xc108, 0x21, 0 - .dw 0xa0c0, 0xc108, 0xa0ff, 0xc108, 0x21, 0 - .dw 0xa140, 0xc108, 0xa17f, 0xc108, 0x21, 0 - .dw 0xa1c0, 0xc108, 0xa1ff, 0xc108, 0x21, 0 - .dw 0xa240, 0xc108, 0xa27f, 0xc108, 0x21, 0 - .dw 0xa2c0, 0xc108, 0xa2ff, 0xc108, 0x21, 0 - .dw 0xa340, 0xc108, 0xa37f, 0xc108, 0x21, 0 - .dw 0xa3c0, 0xc108, 0xa3ff, 0xc108, 0x21, 0 - .dw 0xa440, 0xc108, 0xa47f, 0xc108, 0x21, 0 - .dw 0xa4c0, 0xc108, 0xa4ff, 0xc108, 0x21, 0 - .dw 0xa540, 0xc108, 0xa57f, 0xc108, 0x21, 0 - .dw 0xa5c0, 0xc108, 0xa5ff, 0xc108, 0x21, 0 - .dw 0xa640, 0xc108, 0xa67f, 0xc108, 0x21, 0 - .dw 0xa6c0, 0xc108, 0xa6ff, 0xc108, 0x21, 0 - .dw 0xa740, 0xc108, 0xa77f, 0xc108, 0x21, 0 - .dw 0xa7c0, 0xc108, 0xa7ff, 0xc108, 0x21, 0 - .dw 0xa840, 0xc108, 0xa87f, 0xc108, 0x21, 0 - .dw 0xa8c0, 0xc108, 0xa8ff, 0xc108, 0x21, 0 - .dw 0xa940, 0xc108, 0xa97f, 0xc108, 0x21, 0 - .dw 0xa9c0, 0xc108, 0xa9ff, 0xc108, 0x21, 0 - .dw 0xaa40, 0xc108, 0xaa7f, 0xc108, 0x21, 0 - .dw 0xaac0, 0xc108, 0xaaff, 0xc108, 0x21, 0 - .dw 0xab40, 0xc108, 0xab7f, 0xc108, 0x21, 0 - .dw 0xabc0, 0xc108, 0xabff, 0xc108, 0x21, 0 - .dw 0xac40, 0xc108, 0xac7f, 0xc108, 0x21, 0 - .dw 0xacc0, 0xc108, 0xacff, 0xc108, 0x21, 0 - .dw 0xad40, 0xc108, 0xad7f, 0xc108, 0x21, 0 - .dw 0xadc0, 0xc108, 0xadff, 0xc108, 0x21, 0 - .dw 0xae40, 0xc108, 0xae7f, 0xc108, 0x21, 0 - .dw 0xaec0, 0xc108, 0xaeff, 0xc108, 0x21, 0 - .dw 0xaf40, 0xc108, 0xaf7f, 0xc108, 0x21, 0 - .dw 0xafc0, 0xc108, 0xafff, 0xc108, 0x21, 0 - .dw 0xb040, 0xc108, 0xb07f, 0xc108, 0x21, 0 - .dw 0xb0c0, 0xc108, 0xb0ff, 0xc108, 0x21, 0 - .dw 0xb140, 0xc108, 0xb17f, 0xc108, 0x21, 0 - .dw 0xb1c0, 0xc108, 0xb1ff, 0xc108, 0x21, 0 - .dw 0xb240, 0xc108, 0xb27f, 0xc108, 0x21, 0 - .dw 0xb2c0, 0xc108, 0xb2ff, 0xc108, 0x21, 0 - .dw 0xb340, 0xc108, 0xb37f, 0xc108, 0x21, 0 - .dw 0xb3c0, 0xc108, 0xb3ff, 0xc108, 0x21, 0 - .dw 0xb440, 0xc108, 0xb47f, 0xc108, 0x21, 0 - .dw 0xb4c0, 0xc108, 0xb4ff, 0xc108, 0x21, 0 - .dw 0xb540, 0xc108, 0xb57f, 0xc108, 0x21, 0 - .dw 0xb5c0, 0xc108, 0xb5ff, 0xc108, 0x21, 0 - .dw 0xb640, 0xc108, 0xb67f, 0xc108, 0x21, 0 - .dw 0xb6c0, 0xc108, 0xb6ff, 0xc108, 0x21, 0 - .dw 0xb740, 0xc108, 0xb77f, 0xc108, 0x21, 0 - .dw 0xb7c0, 0xc108, 0xb7ff, 0xc108, 0x21, 0 - .dw 0xb840, 0xc108, 0xb87f, 0xc108, 0x21, 0 - .dw 0xb8c0, 0xc108, 0xb8ff, 0xc108, 0x21, 0 - .dw 0xb940, 0xc108, 0xb97f, 0xc108, 0x21, 0 - .dw 0xb9c0, 0xc108, 0xdfff, 0xc108, 0x21, 0 - .dw 0xe040, 0xc108, 0xe07f, 0xc108, 0x21, 0 - .dw 0xe0c0, 0xc108, 0xe0ff, 0xc108, 0x21, 0 - .dw 0xe140, 0xc108, 0xe17f, 0xc108, 0x21, 0 - .dw 0xe1c0, 0xc108, 0xe1ff, 0xc108, 0x21, 0 - .dw 0xe240, 0xc108, 0xe27f, 0xc108, 0x21, 0 - .dw 0xe2c0, 0xc108, 0xe2ff, 0xc108, 0x21, 0 - .dw 0xe340, 0xc108, 0xe37f, 0xc108, 0x21, 0 - .dw 0xe3c0, 0xc108, 0xe3ff, 0xc108, 0x21, 0 - .dw 0xe440, 0xc108, 0xe47f, 0xc108, 0x21, 0 - .dw 0xe4c0, 0xc108, 0xe4ff, 0xc108, 0x21, 0 - .dw 0xe540, 0xc108, 0xe57f, 0xc108, 0x21, 0 - .dw 0xe5c0, 0xc108, 0xe5ff, 0xc108, 0x21, 0 - .dw 0xe640, 0xc108, 0xe67f, 0xc108, 0x21, 0 - .dw 0xe6c0, 0xc108, 0xe6ff, 0xc108, 0x21, 0 - .dw 0xe740, 0xc108, 0xe77f, 0xc108, 0x21, 0 - .dw 0xe7c0, 0xc108, 0xe7ff, 0xc108, 0x21, 0 - .dw 0xe840, 0xc108, 0xe87f, 0xc108, 0x21, 0 - .dw 0xe8c0, 0xc108, 0xe8ff, 0xc108, 0x21, 0 - .dw 0xe940, 0xc108, 0xe97f, 0xc108, 0x21, 0 - .dw 0xe9c0, 0xc108, 0xe9ff, 0xc108, 0x21, 0 - .dw 0xea40, 0xc108, 0xea7f, 0xc108, 0x21, 0 - .dw 0xeac0, 0xc108, 0xeaff, 0xc108, 0x21, 0 - .dw 0xeb40, 0xc108, 0xeb7f, 0xc108, 0x21, 0 - .dw 0xebc0, 0xc108, 0xebff, 0xc108, 0x21, 0 - .dw 0xec40, 0xc108, 0xec7f, 0xc108, 0x21, 0 - .dw 0xecc0, 0xc108, 0xecff, 0xc108, 0x21, 0 - .dw 0xed40, 0xc108, 0xed7f, 0xc108, 0x21, 0 - .dw 0xedc0, 0xc108, 0xedff, 0xc108, 0x21, 0 - .dw 0xee40, 0xc108, 0xee7f, 0xc108, 0x21, 0 - .dw 0xeec0, 0xc108, 0xeeff, 0xc108, 0x21, 0 - .dw 0xef40, 0xc108, 0xef7f, 0xc108, 0x21, 0 - .dw 0xefc0, 0xc108, 0xefff, 0xc108, 0x21, 0 - .dw 0xf040, 0xc108, 0xf07f, 0xc108, 0x21, 0 - .dw 0xf0c0, 0xc108, 0xf0ff, 0xc108, 0x21, 0 - .dw 0xf140, 0xc108, 0xf17f, 0xc108, 0x21, 0 - .dw 0xf1c0, 0xc108, 0xf1ff, 0xc108, 0x21, 0 - .dw 0xf240, 0xc108, 0xf27f, 0xc108, 0x21, 0 - .dw 0xf2c0, 0xc108, 0xf2ff, 0xc108, 0x21, 0 - .dw 0xf340, 0xc108, 0xf37f, 0xc108, 0x21, 0 - .dw 0xf3c0, 0xc108, 0xf3ff, 0xc108, 0x21, 0 - .dw 0xf440, 0xc108, 0xf47f, 0xc108, 0x21, 0 - .dw 0xf4c0, 0xc108, 0xf4ff, 0xc108, 0x21, 0 - .dw 0xf540, 0xc108, 0xf57f, 0xc108, 0x21, 0 - .dw 0xf5c0, 0xc108, 0xf5ff, 0xc108, 0x21, 0 - .dw 0xf640, 0xc108, 0xf67f, 0xc108, 0x21, 0 - .dw 0xf6c0, 0xc108, 0xf6ff, 0xc108, 0x21, 0 - .dw 0xf740, 0xc108, 0xf77f, 0xc108, 0x21, 0 - .dw 0xf7c0, 0xc108, 0xf7ff, 0xc108, 0x21, 0 - .dw 0xf840, 0xc108, 0xf87f, 0xc108, 0x21, 0 - .dw 0xf8c0, 0xc108, 0xf8ff, 0xc108, 0x21, 0 - .dw 0xf940, 0xc108, 0xf97f, 0xc108, 0x21, 0 - .dw 0xf9c0, 0xc108, 0x1fff, 0xc109, 0x21, 0 - .dw 0x2040, 0xc109, 0x207f, 0xc109, 0x21, 0 - .dw 0x20c0, 0xc109, 0x20ff, 0xc109, 0x21, 0 - .dw 0x2140, 0xc109, 0x217f, 0xc109, 0x21, 0 - .dw 0x21c0, 0xc109, 0x21ff, 0xc109, 0x21, 0 - .dw 0x2240, 0xc109, 0x227f, 0xc109, 0x21, 0 - .dw 0x22c0, 0xc109, 0x22ff, 0xc109, 0x21, 0 - .dw 0x2340, 0xc109, 0x237f, 0xc109, 0x21, 0 - .dw 0x23c0, 0xc109, 0x23ff, 0xc109, 0x21, 0 - .dw 0x2440, 0xc109, 0x247f, 0xc109, 0x21, 0 - .dw 0x24c0, 0xc109, 0x24ff, 0xc109, 0x21, 0 - .dw 0x2540, 0xc109, 0x257f, 0xc109, 0x21, 0 - .dw 0x25c0, 0xc109, 0x25ff, 0xc109, 0x21, 0 - .dw 0x2640, 0xc109, 0x267f, 0xc109, 0x21, 0 - .dw 0x26c0, 0xc109, 0x26ff, 0xc109, 0x21, 0 - .dw 0x2740, 0xc109, 0x277f, 0xc109, 0x21, 0 - .dw 0x27c0, 0xc109, 0x27ff, 0xc109, 0x21, 0 - .dw 0x2840, 0xc109, 0x287f, 0xc109, 0x21, 0 - .dw 0x28c0, 0xc109, 0x28ff, 0xc109, 0x21, 0 - .dw 0x2940, 0xc109, 0x297f, 0xc109, 0x21, 0 - .dw 0x29c0, 0xc109, 0x29ff, 0xc109, 0x21, 0 - .dw 0x2a40, 0xc109, 0x2a7f, 0xc109, 0x21, 0 - .dw 0x2ac0, 0xc109, 0x2aff, 0xc109, 0x21, 0 - .dw 0x2b40, 0xc109, 0x2b7f, 0xc109, 0x21, 0 - .dw 0x2bc0, 0xc109, 0x2bff, 0xc109, 0x21, 0 - .dw 0x2c40, 0xc109, 0x2c7f, 0xc109, 0x21, 0 - .dw 0x2cc0, 0xc109, 0x2cff, 0xc109, 0x21, 0 - .dw 0x2d40, 0xc109, 0x2d7f, 0xc109, 0x21, 0 - .dw 0x2dc0, 0xc109, 0x2dff, 0xc109, 0x21, 0 - .dw 0x2e40, 0xc109, 0x2e7f, 0xc109, 0x21, 0 - .dw 0x2ec0, 0xc109, 0x2eff, 0xc109, 0x21, 0 - .dw 0x2f40, 0xc109, 0x2f7f, 0xc109, 0x21, 0 - .dw 0x2fc0, 0xc109, 0x2fff, 0xc109, 0x21, 0 - .dw 0x3040, 0xc109, 0x307f, 0xc109, 0x21, 0 - .dw 0x30c0, 0xc109, 0x30ff, 0xc109, 0x21, 0 - .dw 0x3140, 0xc109, 0x317f, 0xc109, 0x21, 0 - .dw 0x31c0, 0xc109, 0x31ff, 0xc109, 0x21, 0 - .dw 0x3240, 0xc109, 0x327f, 0xc109, 0x21, 0 - .dw 0x32c0, 0xc109, 0x32ff, 0xc109, 0x21, 0 - .dw 0x3340, 0xc109, 0x337f, 0xc109, 0x21, 0 - .dw 0x33c0, 0xc109, 0x33ff, 0xc109, 0x21, 0 - .dw 0x3440, 0xc109, 0x347f, 0xc109, 0x21, 0 - .dw 0x34c0, 0xc109, 0x34ff, 0xc109, 0x21, 0 - .dw 0x3540, 0xc109, 0x357f, 0xc109, 0x21, 0 - .dw 0x35c0, 0xc109, 0x35ff, 0xc109, 0x21, 0 - .dw 0x3640, 0xc109, 0x367f, 0xc109, 0x21, 0 - .dw 0x36c0, 0xc109, 0x36ff, 0xc109, 0x21, 0 - .dw 0x3740, 0xc109, 0x377f, 0xc109, 0x21, 0 - .dw 0x37c0, 0xc109, 0x37ff, 0xc109, 0x21, 0 - .dw 0x3840, 0xc109, 0x387f, 0xc109, 0x21, 0 - .dw 0x38c0, 0xc109, 0x38ff, 0xc109, 0x21, 0 - .dw 0x3940, 0xc109, 0x397f, 0xc109, 0x21, 0 - .dw 0x39c0, 0xc109, 0x5fff, 0xc109, 0x21, 0 - .dw 0x6040, 0xc109, 0x607f, 0xc109, 0x21, 0 - .dw 0x60c0, 0xc109, 0x60ff, 0xc109, 0x21, 0 - .dw 0x6140, 0xc109, 0x617f, 0xc109, 0x21, 0 - .dw 0x61c0, 0xc109, 0x61ff, 0xc109, 0x21, 0 - .dw 0x6240, 0xc109, 0x627f, 0xc109, 0x21, 0 - .dw 0x62c0, 0xc109, 0x62ff, 0xc109, 0x21, 0 - .dw 0x6340, 0xc109, 0x637f, 0xc109, 0x21, 0 - .dw 0x63c0, 0xc109, 0x63ff, 0xc109, 0x21, 0 - .dw 0x6440, 0xc109, 0x647f, 0xc109, 0x21, 0 - .dw 0x64c0, 0xc109, 0x64ff, 0xc109, 0x21, 0 - .dw 0x6540, 0xc109, 0x657f, 0xc109, 0x21, 0 - .dw 0x65c0, 0xc109, 0x65ff, 0xc109, 0x21, 0 - .dw 0x6640, 0xc109, 0x667f, 0xc109, 0x21, 0 - .dw 0x66c0, 0xc109, 0x66ff, 0xc109, 0x21, 0 - .dw 0x6740, 0xc109, 0x677f, 0xc109, 0x21, 0 - .dw 0x67c0, 0xc109, 0x67ff, 0xc109, 0x21, 0 - .dw 0x6840, 0xc109, 0x687f, 0xc109, 0x21, 0 - .dw 0x68c0, 0xc109, 0x68ff, 0xc109, 0x21, 0 - .dw 0x6940, 0xc109, 0x697f, 0xc109, 0x21, 0 - .dw 0x69c0, 0xc109, 0x69ff, 0xc109, 0x21, 0 - .dw 0x6a40, 0xc109, 0x6a7f, 0xc109, 0x21, 0 - .dw 0x6ac0, 0xc109, 0x6aff, 0xc109, 0x21, 0 - .dw 0x6b40, 0xc109, 0x6b7f, 0xc109, 0x21, 0 - .dw 0x6bc0, 0xc109, 0x6bff, 0xc109, 0x21, 0 - .dw 0x6c40, 0xc109, 0x6c7f, 0xc109, 0x21, 0 - .dw 0x6cc0, 0xc109, 0x6cff, 0xc109, 0x21, 0 - .dw 0x6d40, 0xc109, 0x6d7f, 0xc109, 0x21, 0 - .dw 0x6dc0, 0xc109, 0x6dff, 0xc109, 0x21, 0 - .dw 0x6e40, 0xc109, 0x6e7f, 0xc109, 0x21, 0 - .dw 0x6ec0, 0xc109, 0x6eff, 0xc109, 0x21, 0 - .dw 0x6f40, 0xc109, 0x6f7f, 0xc109, 0x21, 0 - .dw 0x6fc0, 0xc109, 0x6fff, 0xc109, 0x21, 0 - .dw 0x7040, 0xc109, 0x707f, 0xc109, 0x21, 0 - .dw 0x70c0, 0xc109, 0x70ff, 0xc109, 0x21, 0 - .dw 0x7140, 0xc109, 0x717f, 0xc109, 0x21, 0 - .dw 0x71c0, 0xc109, 0x71ff, 0xc109, 0x21, 0 - .dw 0x7240, 0xc109, 0x727f, 0xc109, 0x21, 0 - .dw 0x72c0, 0xc109, 0x72ff, 0xc109, 0x21, 0 - .dw 0x7340, 0xc109, 0x737f, 0xc109, 0x21, 0 - .dw 0x73c0, 0xc109, 0x73ff, 0xc109, 0x21, 0 - .dw 0x7440, 0xc109, 0x747f, 0xc109, 0x21, 0 - .dw 0x74c0, 0xc109, 0x74ff, 0xc109, 0x21, 0 - .dw 0x7540, 0xc109, 0x757f, 0xc109, 0x21, 0 - .dw 0x75c0, 0xc109, 0x75ff, 0xc109, 0x21, 0 - .dw 0x7640, 0xc109, 0x767f, 0xc109, 0x21, 0 - .dw 0x76c0, 0xc109, 0x76ff, 0xc109, 0x21, 0 - .dw 0x7740, 0xc109, 0x777f, 0xc109, 0x21, 0 - .dw 0x77c0, 0xc109, 0x77ff, 0xc109, 0x21, 0 - .dw 0x7840, 0xc109, 0x787f, 0xc109, 0x21, 0 - .dw 0x78c0, 0xc109, 0x78ff, 0xc109, 0x21, 0 - .dw 0x7940, 0xc109, 0x797f, 0xc109, 0x21, 0 - .dw 0x79c0, 0xc109, 0x9fff, 0xc109, 0x21, 0 - .dw 0xa040, 0xc109, 0xa07f, 0xc109, 0x21, 0 - .dw 0xa0c0, 0xc109, 0xa0ff, 0xc109, 0x21, 0 - .dw 0xa140, 0xc109, 0xa17f, 0xc109, 0x21, 0 - .dw 0xa1c0, 0xc109, 0xa1ff, 0xc109, 0x21, 0 - .dw 0xa240, 0xc109, 0xa27f, 0xc109, 0x21, 0 - .dw 0xa2c0, 0xc109, 0xa2ff, 0xc109, 0x21, 0 - .dw 0xa340, 0xc109, 0xa37f, 0xc109, 0x21, 0 - .dw 0xa3c0, 0xc109, 0xa3ff, 0xc109, 0x21, 0 - .dw 0xa440, 0xc109, 0xa47f, 0xc109, 0x21, 0 - .dw 0xa4c0, 0xc109, 0xa4ff, 0xc109, 0x21, 0 - .dw 0xa540, 0xc109, 0xa57f, 0xc109, 0x21, 0 - .dw 0xa5c0, 0xc109, 0xa5ff, 0xc109, 0x21, 0 - .dw 0xa640, 0xc109, 0xa67f, 0xc109, 0x21, 0 - .dw 0xa6c0, 0xc109, 0xa6ff, 0xc109, 0x21, 0 - .dw 0xa740, 0xc109, 0xa77f, 0xc109, 0x21, 0 - .dw 0xa7c0, 0xc109, 0xa7ff, 0xc109, 0x21, 0 - .dw 0xa840, 0xc109, 0xa87f, 0xc109, 0x21, 0 - .dw 0xa8c0, 0xc109, 0xa8ff, 0xc109, 0x21, 0 - .dw 0xa940, 0xc109, 0xa97f, 0xc109, 0x21, 0 - .dw 0xa9c0, 0xc109, 0xa9ff, 0xc109, 0x21, 0 - .dw 0xaa40, 0xc109, 0xaa7f, 0xc109, 0x21, 0 - .dw 0xaac0, 0xc109, 0xaaff, 0xc109, 0x21, 0 - .dw 0xab40, 0xc109, 0xab7f, 0xc109, 0x21, 0 - .dw 0xabc0, 0xc109, 0xabff, 0xc109, 0x21, 0 - .dw 0xac40, 0xc109, 0xac7f, 0xc109, 0x21, 0 - .dw 0xacc0, 0xc109, 0xacff, 0xc109, 0x21, 0 - .dw 0xad40, 0xc109, 0xad7f, 0xc109, 0x21, 0 - .dw 0xadc0, 0xc109, 0xadff, 0xc109, 0x21, 0 - .dw 0xae40, 0xc109, 0xae7f, 0xc109, 0x21, 0 - .dw 0xaec0, 0xc109, 0xaeff, 0xc109, 0x21, 0 - .dw 0xaf40, 0xc109, 0xaf7f, 0xc109, 0x21, 0 - .dw 0xafc0, 0xc109, 0xafff, 0xc109, 0x21, 0 - .dw 0xb040, 0xc109, 0xb07f, 0xc109, 0x21, 0 - .dw 0xb0c0, 0xc109, 0xb0ff, 0xc109, 0x21, 0 - .dw 0xb140, 0xc109, 0xb17f, 0xc109, 0x21, 0 - .dw 0xb1c0, 0xc109, 0xb1ff, 0xc109, 0x21, 0 - .dw 0xb240, 0xc109, 0xb27f, 0xc109, 0x21, 0 - .dw 0xb2c0, 0xc109, 0xb2ff, 0xc109, 0x21, 0 - .dw 0xb340, 0xc109, 0xb37f, 0xc109, 0x21, 0 - .dw 0xb3c0, 0xc109, 0xb3ff, 0xc109, 0x21, 0 - .dw 0xb440, 0xc109, 0xb47f, 0xc109, 0x21, 0 - .dw 0xb4c0, 0xc109, 0xb4ff, 0xc109, 0x21, 0 - .dw 0xb540, 0xc109, 0xb57f, 0xc109, 0x21, 0 - .dw 0xb5c0, 0xc109, 0xb5ff, 0xc109, 0x21, 0 - .dw 0xb640, 0xc109, 0xb67f, 0xc109, 0x21, 0 - .dw 0xb6c0, 0xc109, 0xb6ff, 0xc109, 0x21, 0 - .dw 0xb740, 0xc109, 0xb77f, 0xc109, 0x21, 0 - .dw 0xb7c0, 0xc109, 0xb7ff, 0xc109, 0x21, 0 - .dw 0xb840, 0xc109, 0xb87f, 0xc109, 0x21, 0 - .dw 0xb8c0, 0xc109, 0xb8ff, 0xc109, 0x21, 0 - .dw 0xb940, 0xc109, 0xb97f, 0xc109, 0x21, 0 - .dw 0xb9c0, 0xc109, 0xdfff, 0xc109, 0x21, 0 - .dw 0xe040, 0xc109, 0xe07f, 0xc109, 0x21, 0 - .dw 0xe0c0, 0xc109, 0xe0ff, 0xc109, 0x21, 0 - .dw 0xe140, 0xc109, 0xe17f, 0xc109, 0x21, 0 - .dw 0xe1c0, 0xc109, 0xe1ff, 0xc109, 0x21, 0 - .dw 0xe240, 0xc109, 0xe27f, 0xc109, 0x21, 0 - .dw 0xe2c0, 0xc109, 0xe2ff, 0xc109, 0x21, 0 - .dw 0xe340, 0xc109, 0xe37f, 0xc109, 0x21, 0 - .dw 0xe3c0, 0xc109, 0xe3ff, 0xc109, 0x21, 0 - .dw 0xe440, 0xc109, 0xe47f, 0xc109, 0x21, 0 - .dw 0xe4c0, 0xc109, 0xe4ff, 0xc109, 0x21, 0 - .dw 0xe540, 0xc109, 0xe57f, 0xc109, 0x21, 0 - .dw 0xe5c0, 0xc109, 0xe5ff, 0xc109, 0x21, 0 - .dw 0xe640, 0xc109, 0xe67f, 0xc109, 0x21, 0 - .dw 0xe6c0, 0xc109, 0xe6ff, 0xc109, 0x21, 0 - .dw 0xe740, 0xc109, 0xe77f, 0xc109, 0x21, 0 - .dw 0xe7c0, 0xc109, 0xe7ff, 0xc109, 0x21, 0 - .dw 0xe840, 0xc109, 0xe87f, 0xc109, 0x21, 0 - .dw 0xe8c0, 0xc109, 0xe8ff, 0xc109, 0x21, 0 - .dw 0xe940, 0xc109, 0xe97f, 0xc109, 0x21, 0 - .dw 0xe9c0, 0xc109, 0xe9ff, 0xc109, 0x21, 0 - .dw 0xea40, 0xc109, 0xea7f, 0xc109, 0x21, 0 - .dw 0xeac0, 0xc109, 0xeaff, 0xc109, 0x21, 0 - .dw 0xeb40, 0xc109, 0xeb7f, 0xc109, 0x21, 0 - .dw 0xebc0, 0xc109, 0xebff, 0xc109, 0x21, 0 - .dw 0xec40, 0xc109, 0xec7f, 0xc109, 0x21, 0 - .dw 0xecc0, 0xc109, 0xecff, 0xc109, 0x21, 0 - .dw 0xed40, 0xc109, 0xed7f, 0xc109, 0x21, 0 - .dw 0xedc0, 0xc109, 0xedff, 0xc109, 0x21, 0 - .dw 0xee40, 0xc109, 0xee7f, 0xc109, 0x21, 0 - .dw 0xeec0, 0xc109, 0xeeff, 0xc109, 0x21, 0 - .dw 0xef40, 0xc109, 0xef7f, 0xc109, 0x21, 0 - .dw 0xefc0, 0xc109, 0xefff, 0xc109, 0x21, 0 - .dw 0xf040, 0xc109, 0xf07f, 0xc109, 0x21, 0 - .dw 0xf0c0, 0xc109, 0xf0ff, 0xc109, 0x21, 0 - .dw 0xf140, 0xc109, 0xf17f, 0xc109, 0x21, 0 - .dw 0xf1c0, 0xc109, 0xf1ff, 0xc109, 0x21, 0 - .dw 0xf240, 0xc109, 0xf27f, 0xc109, 0x21, 0 - .dw 0xf2c0, 0xc109, 0xf2ff, 0xc109, 0x21, 0 - .dw 0xf340, 0xc109, 0xf37f, 0xc109, 0x21, 0 - .dw 0xf3c0, 0xc109, 0xf3ff, 0xc109, 0x21, 0 - .dw 0xf440, 0xc109, 0xf47f, 0xc109, 0x21, 0 - .dw 0xf4c0, 0xc109, 0xf4ff, 0xc109, 0x21, 0 - .dw 0xf540, 0xc109, 0xf57f, 0xc109, 0x21, 0 - .dw 0xf5c0, 0xc109, 0xf5ff, 0xc109, 0x21, 0 - .dw 0xf640, 0xc109, 0xf67f, 0xc109, 0x21, 0 - .dw 0xf6c0, 0xc109, 0xf6ff, 0xc109, 0x21, 0 - .dw 0xf740, 0xc109, 0xf77f, 0xc109, 0x21, 0 - .dw 0xf7c0, 0xc109, 0xf7ff, 0xc109, 0x21, 0 - .dw 0xf840, 0xc109, 0xf87f, 0xc109, 0x21, 0 - .dw 0xf8c0, 0xc109, 0xf8ff, 0xc109, 0x21, 0 - .dw 0xf940, 0xc109, 0xf97f, 0xc109, 0x21, 0 - .dw 0xf9c0, 0xc109, 0x1fff, 0xc10a, 0x21, 0 - .dw 0x2040, 0xc10a, 0x207f, 0xc10a, 0x21, 0 - .dw 0x20c0, 0xc10a, 0x20ff, 0xc10a, 0x21, 0 - .dw 0x2140, 0xc10a, 0x217f, 0xc10a, 0x21, 0 - .dw 0x21c0, 0xc10a, 0x21ff, 0xc10a, 0x21, 0 - .dw 0x2240, 0xc10a, 0x227f, 0xc10a, 0x21, 0 - .dw 0x22c0, 0xc10a, 0x22ff, 0xc10a, 0x21, 0 - .dw 0x2340, 0xc10a, 0x237f, 0xc10a, 0x21, 0 - .dw 0x23c0, 0xc10a, 0x23ff, 0xc10a, 0x21, 0 - .dw 0x2440, 0xc10a, 0x247f, 0xc10a, 0x21, 0 - .dw 0x24c0, 0xc10a, 0x24ff, 0xc10a, 0x21, 0 - .dw 0x2540, 0xc10a, 0x257f, 0xc10a, 0x21, 0 - .dw 0x25c0, 0xc10a, 0x25ff, 0xc10a, 0x21, 0 - .dw 0x2640, 0xc10a, 0x267f, 0xc10a, 0x21, 0 - .dw 0x26c0, 0xc10a, 0x26ff, 0xc10a, 0x21, 0 - .dw 0x2740, 0xc10a, 0x277f, 0xc10a, 0x21, 0 - .dw 0x27c0, 0xc10a, 0x27ff, 0xc10a, 0x21, 0 - .dw 0x2840, 0xc10a, 0x287f, 0xc10a, 0x21, 0 - .dw 0x28c0, 0xc10a, 0x28ff, 0xc10a, 0x21, 0 - .dw 0x2940, 0xc10a, 0x297f, 0xc10a, 0x21, 0 - .dw 0x29c0, 0xc10a, 0x29ff, 0xc10a, 0x21, 0 - .dw 0x2a40, 0xc10a, 0x2a7f, 0xc10a, 0x21, 0 - .dw 0x2ac0, 0xc10a, 0x2aff, 0xc10a, 0x21, 0 - .dw 0x2b40, 0xc10a, 0x2b7f, 0xc10a, 0x21, 0 - .dw 0x2bc0, 0xc10a, 0x2bff, 0xc10a, 0x21, 0 - .dw 0x2c40, 0xc10a, 0x2c7f, 0xc10a, 0x21, 0 - .dw 0x2cc0, 0xc10a, 0x2cff, 0xc10a, 0x21, 0 - .dw 0x2d40, 0xc10a, 0x2d7f, 0xc10a, 0x21, 0 - .dw 0x2dc0, 0xc10a, 0x2dff, 0xc10a, 0x21, 0 - .dw 0x2e40, 0xc10a, 0x2e7f, 0xc10a, 0x21, 0 - .dw 0x2ec0, 0xc10a, 0x2eff, 0xc10a, 0x21, 0 - .dw 0x2f40, 0xc10a, 0x2f7f, 0xc10a, 0x21, 0 - .dw 0x2fc0, 0xc10a, 0x2fff, 0xc10a, 0x21, 0 - .dw 0x3040, 0xc10a, 0x307f, 0xc10a, 0x21, 0 - .dw 0x30c0, 0xc10a, 0x30ff, 0xc10a, 0x21, 0 - .dw 0x3140, 0xc10a, 0x317f, 0xc10a, 0x21, 0 - .dw 0x31c0, 0xc10a, 0x31ff, 0xc10a, 0x21, 0 - .dw 0x3240, 0xc10a, 0x327f, 0xc10a, 0x21, 0 - .dw 0x32c0, 0xc10a, 0x32ff, 0xc10a, 0x21, 0 - .dw 0x3340, 0xc10a, 0x337f, 0xc10a, 0x21, 0 - .dw 0x33c0, 0xc10a, 0x33ff, 0xc10a, 0x21, 0 - .dw 0x3440, 0xc10a, 0x347f, 0xc10a, 0x21, 0 - .dw 0x34c0, 0xc10a, 0x34ff, 0xc10a, 0x21, 0 - .dw 0x3540, 0xc10a, 0x357f, 0xc10a, 0x21, 0 - .dw 0x35c0, 0xc10a, 0x35ff, 0xc10a, 0x21, 0 - .dw 0x3640, 0xc10a, 0x367f, 0xc10a, 0x21, 0 - .dw 0x36c0, 0xc10a, 0x36ff, 0xc10a, 0x21, 0 - .dw 0x3740, 0xc10a, 0x377f, 0xc10a, 0x21, 0 - .dw 0x37c0, 0xc10a, 0x37ff, 0xc10a, 0x21, 0 - .dw 0x3840, 0xc10a, 0x387f, 0xc10a, 0x21, 0 - .dw 0x38c0, 0xc10a, 0x38ff, 0xc10a, 0x21, 0 - .dw 0x3940, 0xc10a, 0x397f, 0xc10a, 0x21, 0 - .dw 0x39c0, 0xc10a, 0x5fff, 0xc10a, 0x21, 0 - .dw 0x6040, 0xc10a, 0x607f, 0xc10a, 0x21, 0 - .dw 0x60c0, 0xc10a, 0x60ff, 0xc10a, 0x21, 0 - .dw 0x6140, 0xc10a, 0x617f, 0xc10a, 0x21, 0 - .dw 0x61c0, 0xc10a, 0x61ff, 0xc10a, 0x21, 0 - .dw 0x6240, 0xc10a, 0x627f, 0xc10a, 0x21, 0 - .dw 0x62c0, 0xc10a, 0x62ff, 0xc10a, 0x21, 0 - .dw 0x6340, 0xc10a, 0x637f, 0xc10a, 0x21, 0 - .dw 0x63c0, 0xc10a, 0x63ff, 0xc10a, 0x21, 0 - .dw 0x6440, 0xc10a, 0x647f, 0xc10a, 0x21, 0 - .dw 0x64c0, 0xc10a, 0x64ff, 0xc10a, 0x21, 0 - .dw 0x6540, 0xc10a, 0x657f, 0xc10a, 0x21, 0 - .dw 0x65c0, 0xc10a, 0x65ff, 0xc10a, 0x21, 0 - .dw 0x6640, 0xc10a, 0x667f, 0xc10a, 0x21, 0 - .dw 0x66c0, 0xc10a, 0x66ff, 0xc10a, 0x21, 0 - .dw 0x6740, 0xc10a, 0x677f, 0xc10a, 0x21, 0 - .dw 0x67c0, 0xc10a, 0x67ff, 0xc10a, 0x21, 0 - .dw 0x6840, 0xc10a, 0x687f, 0xc10a, 0x21, 0 - .dw 0x68c0, 0xc10a, 0x68ff, 0xc10a, 0x21, 0 - .dw 0x6940, 0xc10a, 0x697f, 0xc10a, 0x21, 0 - .dw 0x69c0, 0xc10a, 0x69ff, 0xc10a, 0x21, 0 - .dw 0x6a40, 0xc10a, 0x6a7f, 0xc10a, 0x21, 0 - .dw 0x6ac0, 0xc10a, 0x6aff, 0xc10a, 0x21, 0 - .dw 0x6b40, 0xc10a, 0x6b7f, 0xc10a, 0x21, 0 - .dw 0x6bc0, 0xc10a, 0x6bff, 0xc10a, 0x21, 0 - .dw 0x6c40, 0xc10a, 0x6c7f, 0xc10a, 0x21, 0 - .dw 0x6cc0, 0xc10a, 0x6cff, 0xc10a, 0x21, 0 - .dw 0x6d40, 0xc10a, 0x6d7f, 0xc10a, 0x21, 0 - .dw 0x6dc0, 0xc10a, 0x6dff, 0xc10a, 0x21, 0 - .dw 0x6e40, 0xc10a, 0x6e7f, 0xc10a, 0x21, 0 - .dw 0x6ec0, 0xc10a, 0x6eff, 0xc10a, 0x21, 0 - .dw 0x6f40, 0xc10a, 0x6f7f, 0xc10a, 0x21, 0 - .dw 0x6fc0, 0xc10a, 0x6fff, 0xc10a, 0x21, 0 - .dw 0x7040, 0xc10a, 0x707f, 0xc10a, 0x21, 0 - .dw 0x70c0, 0xc10a, 0x70ff, 0xc10a, 0x21, 0 - .dw 0x7140, 0xc10a, 0x717f, 0xc10a, 0x21, 0 - .dw 0x71c0, 0xc10a, 0x71ff, 0xc10a, 0x21, 0 - .dw 0x7240, 0xc10a, 0x727f, 0xc10a, 0x21, 0 - .dw 0x72c0, 0xc10a, 0x72ff, 0xc10a, 0x21, 0 - .dw 0x7340, 0xc10a, 0x737f, 0xc10a, 0x21, 0 - .dw 0x73c0, 0xc10a, 0x73ff, 0xc10a, 0x21, 0 - .dw 0x7440, 0xc10a, 0x747f, 0xc10a, 0x21, 0 - .dw 0x74c0, 0xc10a, 0x74ff, 0xc10a, 0x21, 0 - .dw 0x7540, 0xc10a, 0x757f, 0xc10a, 0x21, 0 - .dw 0x75c0, 0xc10a, 0x75ff, 0xc10a, 0x21, 0 - .dw 0x7640, 0xc10a, 0x767f, 0xc10a, 0x21, 0 - .dw 0x76c0, 0xc10a, 0x76ff, 0xc10a, 0x21, 0 - .dw 0x7740, 0xc10a, 0x777f, 0xc10a, 0x21, 0 - .dw 0x77c0, 0xc10a, 0x77ff, 0xc10a, 0x21, 0 - .dw 0x7840, 0xc10a, 0x787f, 0xc10a, 0x21, 0 - .dw 0x78c0, 0xc10a, 0x78ff, 0xc10a, 0x21, 0 - .dw 0x7940, 0xc10a, 0x797f, 0xc10a, 0x21, 0 - .dw 0x79c0, 0xc10a, 0x9fff, 0xc10a, 0x21, 0 - .dw 0xa040, 0xc10a, 0xa07f, 0xc10a, 0x21, 0 - .dw 0xa0c0, 0xc10a, 0xa0ff, 0xc10a, 0x21, 0 - .dw 0xa140, 0xc10a, 0xa17f, 0xc10a, 0x21, 0 - .dw 0xa1c0, 0xc10a, 0xa1ff, 0xc10a, 0x21, 0 - .dw 0xa240, 0xc10a, 0xa27f, 0xc10a, 0x21, 0 - .dw 0xa2c0, 0xc10a, 0xa2ff, 0xc10a, 0x21, 0 - .dw 0xa340, 0xc10a, 0xa37f, 0xc10a, 0x21, 0 - .dw 0xa3c0, 0xc10a, 0xa3ff, 0xc10a, 0x21, 0 - .dw 0xa440, 0xc10a, 0xa47f, 0xc10a, 0x21, 0 - .dw 0xa4c0, 0xc10a, 0xa4ff, 0xc10a, 0x21, 0 - .dw 0xa540, 0xc10a, 0xa57f, 0xc10a, 0x21, 0 - .dw 0xa5c0, 0xc10a, 0xa5ff, 0xc10a, 0x21, 0 - .dw 0xa640, 0xc10a, 0xa67f, 0xc10a, 0x21, 0 - .dw 0xa6c0, 0xc10a, 0xa6ff, 0xc10a, 0x21, 0 - .dw 0xa740, 0xc10a, 0xa77f, 0xc10a, 0x21, 0 - .dw 0xa7c0, 0xc10a, 0xa7ff, 0xc10a, 0x21, 0 - .dw 0xa840, 0xc10a, 0xa87f, 0xc10a, 0x21, 0 - .dw 0xa8c0, 0xc10a, 0xa8ff, 0xc10a, 0x21, 0 - .dw 0xa940, 0xc10a, 0xa97f, 0xc10a, 0x21, 0 - .dw 0xa9c0, 0xc10a, 0xa9ff, 0xc10a, 0x21, 0 - .dw 0xaa40, 0xc10a, 0xaa7f, 0xc10a, 0x21, 0 - .dw 0xaac0, 0xc10a, 0xaaff, 0xc10a, 0x21, 0 - .dw 0xab40, 0xc10a, 0xab7f, 0xc10a, 0x21, 0 - .dw 0xabc0, 0xc10a, 0xabff, 0xc10a, 0x21, 0 - .dw 0xac40, 0xc10a, 0xac7f, 0xc10a, 0x21, 0 - .dw 0xacc0, 0xc10a, 0xacff, 0xc10a, 0x21, 0 - .dw 0xad40, 0xc10a, 0xad7f, 0xc10a, 0x21, 0 - .dw 0xadc0, 0xc10a, 0xadff, 0xc10a, 0x21, 0 - .dw 0xae40, 0xc10a, 0xae7f, 0xc10a, 0x21, 0 - .dw 0xaec0, 0xc10a, 0xaeff, 0xc10a, 0x21, 0 - .dw 0xaf40, 0xc10a, 0xaf7f, 0xc10a, 0x21, 0 - .dw 0xafc0, 0xc10a, 0xafff, 0xc10a, 0x21, 0 - .dw 0xb040, 0xc10a, 0xb07f, 0xc10a, 0x21, 0 - .dw 0xb0c0, 0xc10a, 0xb0ff, 0xc10a, 0x21, 0 - .dw 0xb140, 0xc10a, 0xb17f, 0xc10a, 0x21, 0 - .dw 0xb1c0, 0xc10a, 0xb1ff, 0xc10a, 0x21, 0 - .dw 0xb240, 0xc10a, 0xb27f, 0xc10a, 0x21, 0 - .dw 0xb2c0, 0xc10a, 0xb2ff, 0xc10a, 0x21, 0 - .dw 0xb340, 0xc10a, 0xb37f, 0xc10a, 0x21, 0 - .dw 0xb3c0, 0xc10a, 0xb3ff, 0xc10a, 0x21, 0 - .dw 0xb440, 0xc10a, 0xb47f, 0xc10a, 0x21, 0 - .dw 0xb4c0, 0xc10a, 0xb4ff, 0xc10a, 0x21, 0 - .dw 0xb540, 0xc10a, 0xb57f, 0xc10a, 0x21, 0 - .dw 0xb5c0, 0xc10a, 0xb5ff, 0xc10a, 0x21, 0 - .dw 0xb640, 0xc10a, 0xb67f, 0xc10a, 0x21, 0 - .dw 0xb6c0, 0xc10a, 0xb6ff, 0xc10a, 0x21, 0 - .dw 0xb740, 0xc10a, 0xb77f, 0xc10a, 0x21, 0 - .dw 0xb7c0, 0xc10a, 0xb7ff, 0xc10a, 0x21, 0 - .dw 0xb840, 0xc10a, 0xb87f, 0xc10a, 0x21, 0 - .dw 0xb8c0, 0xc10a, 0xb8ff, 0xc10a, 0x21, 0 - .dw 0xb940, 0xc10a, 0xb97f, 0xc10a, 0x21, 0 - .dw 0xb9c0, 0xc10a, 0xdfff, 0xc10a, 0x21, 0 - .dw 0xe040, 0xc10a, 0xe07f, 0xc10a, 0x21, 0 - .dw 0xe0c0, 0xc10a, 0xe0ff, 0xc10a, 0x21, 0 - .dw 0xe140, 0xc10a, 0xe17f, 0xc10a, 0x21, 0 - .dw 0xe1c0, 0xc10a, 0xe1ff, 0xc10a, 0x21, 0 - .dw 0xe240, 0xc10a, 0xe27f, 0xc10a, 0x21, 0 - .dw 0xe2c0, 0xc10a, 0xe2ff, 0xc10a, 0x21, 0 - .dw 0xe340, 0xc10a, 0xe37f, 0xc10a, 0x21, 0 - .dw 0xe3c0, 0xc10a, 0xe3ff, 0xc10a, 0x21, 0 - .dw 0xe440, 0xc10a, 0xe47f, 0xc10a, 0x21, 0 - .dw 0xe4c0, 0xc10a, 0xe4ff, 0xc10a, 0x21, 0 - .dw 0xe540, 0xc10a, 0xe57f, 0xc10a, 0x21, 0 - .dw 0xe5c0, 0xc10a, 0xe5ff, 0xc10a, 0x21, 0 - .dw 0xe640, 0xc10a, 0xe67f, 0xc10a, 0x21, 0 - .dw 0xe6c0, 0xc10a, 0xe6ff, 0xc10a, 0x21, 0 - .dw 0xe740, 0xc10a, 0xe77f, 0xc10a, 0x21, 0 - .dw 0xe7c0, 0xc10a, 0xe7ff, 0xc10a, 0x21, 0 - .dw 0xe840, 0xc10a, 0xe87f, 0xc10a, 0x21, 0 - .dw 0xe8c0, 0xc10a, 0xe8ff, 0xc10a, 0x21, 0 - .dw 0xe940, 0xc10a, 0xe97f, 0xc10a, 0x21, 0 - .dw 0xe9c0, 0xc10a, 0xe9ff, 0xc10a, 0x21, 0 - .dw 0xea40, 0xc10a, 0xea7f, 0xc10a, 0x21, 0 - .dw 0xeac0, 0xc10a, 0xeaff, 0xc10a, 0x21, 0 - .dw 0xeb40, 0xc10a, 0xeb7f, 0xc10a, 0x21, 0 - .dw 0xebc0, 0xc10a, 0xebff, 0xc10a, 0x21, 0 - .dw 0xec40, 0xc10a, 0xec7f, 0xc10a, 0x21, 0 - .dw 0xecc0, 0xc10a, 0xecff, 0xc10a, 0x21, 0 - .dw 0xed40, 0xc10a, 0xed7f, 0xc10a, 0x21, 0 - .dw 0xedc0, 0xc10a, 0xedff, 0xc10a, 0x21, 0 - .dw 0xee40, 0xc10a, 0xee7f, 0xc10a, 0x21, 0 - .dw 0xeec0, 0xc10a, 0xeeff, 0xc10a, 0x21, 0 - .dw 0xef40, 0xc10a, 0xef7f, 0xc10a, 0x21, 0 - .dw 0xefc0, 0xc10a, 0xefff, 0xc10a, 0x21, 0 - .dw 0xf040, 0xc10a, 0xf07f, 0xc10a, 0x21, 0 - .dw 0xf0c0, 0xc10a, 0xf0ff, 0xc10a, 0x21, 0 - .dw 0xf140, 0xc10a, 0xf17f, 0xc10a, 0x21, 0 - .dw 0xf1c0, 0xc10a, 0xf1ff, 0xc10a, 0x21, 0 - .dw 0xf240, 0xc10a, 0xf27f, 0xc10a, 0x21, 0 - .dw 0xf2c0, 0xc10a, 0xf2ff, 0xc10a, 0x21, 0 - .dw 0xf340, 0xc10a, 0xf37f, 0xc10a, 0x21, 0 - .dw 0xf3c0, 0xc10a, 0xf3ff, 0xc10a, 0x21, 0 - .dw 0xf440, 0xc10a, 0xf47f, 0xc10a, 0x21, 0 - .dw 0xf4c0, 0xc10a, 0xf4ff, 0xc10a, 0x21, 0 - .dw 0xf540, 0xc10a, 0xf57f, 0xc10a, 0x21, 0 - .dw 0xf5c0, 0xc10a, 0xf5ff, 0xc10a, 0x21, 0 - .dw 0xf640, 0xc10a, 0xf67f, 0xc10a, 0x21, 0 - .dw 0xf6c0, 0xc10a, 0xf6ff, 0xc10a, 0x21, 0 - .dw 0xf740, 0xc10a, 0xf77f, 0xc10a, 0x21, 0 - .dw 0xf7c0, 0xc10a, 0xf7ff, 0xc10a, 0x21, 0 - .dw 0xf840, 0xc10a, 0xf87f, 0xc10a, 0x21, 0 - .dw 0xf8c0, 0xc10a, 0xf8ff, 0xc10a, 0x21, 0 - .dw 0xf940, 0xc10a, 0xf97f, 0xc10a, 0x21, 0 - .dw 0xf9c0, 0xc10a, 0x1fff, 0xc10b, 0x21, 0 - .dw 0x2040, 0xc10b, 0x207f, 0xc10b, 0x21, 0 - .dw 0x20c0, 0xc10b, 0x20ff, 0xc10b, 0x21, 0 - .dw 0x2140, 0xc10b, 0x217f, 0xc10b, 0x21, 0 - .dw 0x21c0, 0xc10b, 0x21ff, 0xc10b, 0x21, 0 - .dw 0x2240, 0xc10b, 0x227f, 0xc10b, 0x21, 0 - .dw 0x22c0, 0xc10b, 0x22ff, 0xc10b, 0x21, 0 - .dw 0x2340, 0xc10b, 0x237f, 0xc10b, 0x21, 0 - .dw 0x23c0, 0xc10b, 0x23ff, 0xc10b, 0x21, 0 - .dw 0x2440, 0xc10b, 0x247f, 0xc10b, 0x21, 0 - .dw 0x24c0, 0xc10b, 0x24ff, 0xc10b, 0x21, 0 - .dw 0x2540, 0xc10b, 0x257f, 0xc10b, 0x21, 0 - .dw 0x25c0, 0xc10b, 0x25ff, 0xc10b, 0x21, 0 - .dw 0x2640, 0xc10b, 0x267f, 0xc10b, 0x21, 0 - .dw 0x26c0, 0xc10b, 0x26ff, 0xc10b, 0x21, 0 - .dw 0x2740, 0xc10b, 0x277f, 0xc10b, 0x21, 0 - .dw 0x27c0, 0xc10b, 0x27ff, 0xc10b, 0x21, 0 - .dw 0x2840, 0xc10b, 0x287f, 0xc10b, 0x21, 0 - .dw 0x28c0, 0xc10b, 0x28ff, 0xc10b, 0x21, 0 - .dw 0x2940, 0xc10b, 0x297f, 0xc10b, 0x21, 0 - .dw 0x29c0, 0xc10b, 0x29ff, 0xc10b, 0x21, 0 - .dw 0x2a40, 0xc10b, 0x2a7f, 0xc10b, 0x21, 0 - .dw 0x2ac0, 0xc10b, 0x2aff, 0xc10b, 0x21, 0 - .dw 0x2b40, 0xc10b, 0x2b7f, 0xc10b, 0x21, 0 - .dw 0x2bc0, 0xc10b, 0x2bff, 0xc10b, 0x21, 0 - .dw 0x2c40, 0xc10b, 0x2c7f, 0xc10b, 0x21, 0 - .dw 0x2cc0, 0xc10b, 0x2cff, 0xc10b, 0x21, 0 - .dw 0x2d40, 0xc10b, 0x2d7f, 0xc10b, 0x21, 0 - .dw 0x2dc0, 0xc10b, 0x2dff, 0xc10b, 0x21, 0 - .dw 0x2e40, 0xc10b, 0x2e7f, 0xc10b, 0x21, 0 - .dw 0x2ec0, 0xc10b, 0x2eff, 0xc10b, 0x21, 0 - .dw 0x2f40, 0xc10b, 0x2f7f, 0xc10b, 0x21, 0 - .dw 0x2fc0, 0xc10b, 0x2fff, 0xc10b, 0x21, 0 - .dw 0x3040, 0xc10b, 0x307f, 0xc10b, 0x21, 0 - .dw 0x30c0, 0xc10b, 0x30ff, 0xc10b, 0x21, 0 - .dw 0x3140, 0xc10b, 0x317f, 0xc10b, 0x21, 0 - .dw 0x31c0, 0xc10b, 0x31ff, 0xc10b, 0x21, 0 - .dw 0x3240, 0xc10b, 0x327f, 0xc10b, 0x21, 0 - .dw 0x32c0, 0xc10b, 0x32ff, 0xc10b, 0x21, 0 - .dw 0x3340, 0xc10b, 0x337f, 0xc10b, 0x21, 0 - .dw 0x33c0, 0xc10b, 0x33ff, 0xc10b, 0x21, 0 - .dw 0x3440, 0xc10b, 0x347f, 0xc10b, 0x21, 0 - .dw 0x34c0, 0xc10b, 0x34ff, 0xc10b, 0x21, 0 - .dw 0x3540, 0xc10b, 0x357f, 0xc10b, 0x21, 0 - .dw 0x35c0, 0xc10b, 0x35ff, 0xc10b, 0x21, 0 - .dw 0x3640, 0xc10b, 0x367f, 0xc10b, 0x21, 0 - .dw 0x36c0, 0xc10b, 0x36ff, 0xc10b, 0x21, 0 - .dw 0x3740, 0xc10b, 0x377f, 0xc10b, 0x21, 0 - .dw 0x37c0, 0xc10b, 0x37ff, 0xc10b, 0x21, 0 - .dw 0x3840, 0xc10b, 0x387f, 0xc10b, 0x21, 0 - .dw 0x38c0, 0xc10b, 0x38ff, 0xc10b, 0x21, 0 - .dw 0x3940, 0xc10b, 0x397f, 0xc10b, 0x21, 0 - .dw 0x39c0, 0xc10b, 0xffff, 0xc10b, 0x21, 0 - .dw 0x0040, 0xc10c, 0x007f, 0xc10c, 0x21, 0 - .dw 0x00c0, 0xc10c, 0x00ff, 0xc10c, 0x21, 0 - .dw 0x0140, 0xc10c, 0x017f, 0xc10c, 0x21, 0 - .dw 0x01c0, 0xc10c, 0x01ff, 0xc10c, 0x21, 0 - .dw 0x0240, 0xc10c, 0x027f, 0xc10c, 0x21, 0 - .dw 0x02c0, 0xc10c, 0x02ff, 0xc10c, 0x21, 0 - .dw 0x0340, 0xc10c, 0x037f, 0xc10c, 0x21, 0 - .dw 0x03c0, 0xc10c, 0x03ff, 0xc10c, 0x21, 0 - .dw 0x0440, 0xc10c, 0x047f, 0xc10c, 0x21, 0 - .dw 0x04c0, 0xc10c, 0x04ff, 0xc10c, 0x21, 0 - .dw 0x0540, 0xc10c, 0x057f, 0xc10c, 0x21, 0 - .dw 0x05c0, 0xc10c, 0x05ff, 0xc10c, 0x21, 0 - .dw 0x0640, 0xc10c, 0x067f, 0xc10c, 0x21, 0 - .dw 0x06c0, 0xc10c, 0x06ff, 0xc10c, 0x21, 0 - .dw 0x0740, 0xc10c, 0x077f, 0xc10c, 0x21, 0 - .dw 0x07c0, 0xc10c, 0x07ff, 0xc10c, 0x21, 0 - .dw 0x0840, 0xc10c, 0x087f, 0xc10c, 0x21, 0 - .dw 0x08c0, 0xc10c, 0x08ff, 0xc10c, 0x21, 0 - .dw 0x0940, 0xc10c, 0x097f, 0xc10c, 0x21, 0 - .dw 0x09c0, 0xc10c, 0x09ff, 0xc10c, 0x21, 0 - .dw 0x0a40, 0xc10c, 0x0a7f, 0xc10c, 0x21, 0 - .dw 0x0ac0, 0xc10c, 0x0aff, 0xc10c, 0x21, 0 - .dw 0x0b40, 0xc10c, 0x0b7f, 0xc10c, 0x21, 0 - .dw 0x0bc0, 0xc10c, 0x0bff, 0xc10c, 0x21, 0 - .dw 0x0c40, 0xc10c, 0x0c7f, 0xc10c, 0x21, 0 - .dw 0x0cc0, 0xc10c, 0x0cff, 0xc10c, 0x21, 0 - .dw 0x0d40, 0xc10c, 0x0d7f, 0xc10c, 0x21, 0 - .dw 0x0dc0, 0xc10c, 0x0dff, 0xc10c, 0x21, 0 - .dw 0x0e40, 0xc10c, 0x0e7f, 0xc10c, 0x21, 0 - .dw 0x0ec0, 0xc10c, 0x0eff, 0xc10c, 0x21, 0 - .dw 0x0f40, 0xc10c, 0x0f7f, 0xc10c, 0x21, 0 - .dw 0x0fc0, 0xc10c, 0x0fff, 0xc10c, 0x21, 0 - .dw 0x1040, 0xc10c, 0x107f, 0xc10c, 0x21, 0 - .dw 0x10c0, 0xc10c, 0x10ff, 0xc10c, 0x21, 0 - .dw 0x1140, 0xc10c, 0x117f, 0xc10c, 0x21, 0 - .dw 0x11c0, 0xc10c, 0x11ff, 0xc10c, 0x21, 0 - .dw 0x1240, 0xc10c, 0x127f, 0xc10c, 0x21, 0 - .dw 0x12c0, 0xc10c, 0x12ff, 0xc10c, 0x21, 0 - .dw 0x1340, 0xc10c, 0x137f, 0xc10c, 0x21, 0 - .dw 0x13c0, 0xc10c, 0x13ff, 0xc10c, 0x21, 0 - .dw 0x1440, 0xc10c, 0x147f, 0xc10c, 0x21, 0 - .dw 0x14c0, 0xc10c, 0x14ff, 0xc10c, 0x21, 0 - .dw 0x1540, 0xc10c, 0x157f, 0xc10c, 0x21, 0 - .dw 0x15c0, 0xc10c, 0x15ff, 0xc10c, 0x21, 0 - .dw 0x1640, 0xc10c, 0x167f, 0xc10c, 0x21, 0 - .dw 0x16c0, 0xc10c, 0x16ff, 0xc10c, 0x21, 0 - .dw 0x1740, 0xc10c, 0x177f, 0xc10c, 0x21, 0 - .dw 0x17c0, 0xc10c, 0x17ff, 0xc10c, 0x21, 0 - .dw 0x1840, 0xc10c, 0x187f, 0xc10c, 0x21, 0 - .dw 0x18c0, 0xc10c, 0x18ff, 0xc10c, 0x21, 0 - .dw 0x1940, 0xc10c, 0x197f, 0xc10c, 0x21, 0 - .dw 0x19c0, 0xc10c, 0x1fff, 0xc10c, 0x21, 0 - .dw 0x2040, 0xc10c, 0x207f, 0xc10c, 0x21, 0 - .dw 0x20c0, 0xc10c, 0x20ff, 0xc10c, 0x21, 0 - .dw 0x2140, 0xc10c, 0x217f, 0xc10c, 0x21, 0 - .dw 0x21c0, 0xc10c, 0x21ff, 0xc10c, 0x21, 0 - .dw 0x2240, 0xc10c, 0x227f, 0xc10c, 0x21, 0 - .dw 0x22c0, 0xc10c, 0x22ff, 0xc10c, 0x21, 0 - .dw 0x2340, 0xc10c, 0x237f, 0xc10c, 0x21, 0 - .dw 0x23c0, 0xc10c, 0x23ff, 0xc10c, 0x21, 0 - .dw 0x2440, 0xc10c, 0x247f, 0xc10c, 0x21, 0 - .dw 0x24c0, 0xc10c, 0x24ff, 0xc10c, 0x21, 0 - .dw 0x2540, 0xc10c, 0x257f, 0xc10c, 0x21, 0 - .dw 0x25c0, 0xc10c, 0x25ff, 0xc10c, 0x21, 0 - .dw 0x2640, 0xc10c, 0x267f, 0xc10c, 0x21, 0 - .dw 0x26c0, 0xc10c, 0x26ff, 0xc10c, 0x21, 0 - .dw 0x2740, 0xc10c, 0x277f, 0xc10c, 0x21, 0 - .dw 0x27c0, 0xc10c, 0x27ff, 0xc10c, 0x21, 0 - .dw 0x2840, 0xc10c, 0x287f, 0xc10c, 0x21, 0 - .dw 0x28c0, 0xc10c, 0x28ff, 0xc10c, 0x21, 0 - .dw 0x2940, 0xc10c, 0x297f, 0xc10c, 0x21, 0 - .dw 0x29c0, 0xc10c, 0x29ff, 0xc10c, 0x21, 0 - .dw 0x2a40, 0xc10c, 0x2a7f, 0xc10c, 0x21, 0 - .dw 0x2ac0, 0xc10c, 0x2aff, 0xc10c, 0x21, 0 - .dw 0x2b40, 0xc10c, 0x2b7f, 0xc10c, 0x21, 0 - .dw 0x2bc0, 0xc10c, 0x2bff, 0xc10c, 0x21, 0 - .dw 0x2c40, 0xc10c, 0x2c7f, 0xc10c, 0x21, 0 - .dw 0x2cc0, 0xc10c, 0x2cff, 0xc10c, 0x21, 0 - .dw 0x2d40, 0xc10c, 0x2d7f, 0xc10c, 0x21, 0 - .dw 0x2dc0, 0xc10c, 0x2dff, 0xc10c, 0x21, 0 - .dw 0x2e40, 0xc10c, 0x2e7f, 0xc10c, 0x21, 0 - .dw 0x2ec0, 0xc10c, 0x2eff, 0xc10c, 0x21, 0 - .dw 0x2f40, 0xc10c, 0x2f7f, 0xc10c, 0x21, 0 - .dw 0x2fc0, 0xc10c, 0x2fff, 0xc10c, 0x21, 0 - .dw 0x3040, 0xc10c, 0x307f, 0xc10c, 0x21, 0 - .dw 0x30c0, 0xc10c, 0x30ff, 0xc10c, 0x21, 0 - .dw 0x3140, 0xc10c, 0x317f, 0xc10c, 0x21, 0 - .dw 0x31c0, 0xc10c, 0x31ff, 0xc10c, 0x21, 0 - .dw 0x3240, 0xc10c, 0x327f, 0xc10c, 0x21, 0 - .dw 0x32c0, 0xc10c, 0x32ff, 0xc10c, 0x21, 0 - .dw 0x3340, 0xc10c, 0x337f, 0xc10c, 0x21, 0 - .dw 0x33c0, 0xc10c, 0x33ff, 0xc10c, 0x21, 0 - .dw 0x3440, 0xc10c, 0x347f, 0xc10c, 0x21, 0 - .dw 0x34c0, 0xc10c, 0x34ff, 0xc10c, 0x21, 0 - .dw 0x3540, 0xc10c, 0x357f, 0xc10c, 0x21, 0 - .dw 0x35c0, 0xc10c, 0x35ff, 0xc10c, 0x21, 0 - .dw 0x3640, 0xc10c, 0x367f, 0xc10c, 0x21, 0 - .dw 0x36c0, 0xc10c, 0x36ff, 0xc10c, 0x21, 0 - .dw 0x3740, 0xc10c, 0x377f, 0xc10c, 0x21, 0 - .dw 0x37c0, 0xc10c, 0x37ff, 0xc10c, 0x21, 0 - .dw 0x3840, 0xc10c, 0x387f, 0xc10c, 0x21, 0 - .dw 0x38c0, 0xc10c, 0x38ff, 0xc10c, 0x21, 0 - .dw 0x3940, 0xc10c, 0x397f, 0xc10c, 0x21, 0 - .dw 0x39c0, 0xc10c, 0x3fff, 0xc10c, 0x21, 0 - .dw 0x4040, 0xc10c, 0x407f, 0xc10c, 0x21, 0 - .dw 0x40c0, 0xc10c, 0x40ff, 0xc10c, 0x21, 0 - .dw 0x4140, 0xc10c, 0x417f, 0xc10c, 0x21, 0 - .dw 0x41c0, 0xc10c, 0x41ff, 0xc10c, 0x21, 0 - .dw 0x4240, 0xc10c, 0x427f, 0xc10c, 0x21, 0 - .dw 0x42c0, 0xc10c, 0x42ff, 0xc10c, 0x21, 0 - .dw 0x4340, 0xc10c, 0x437f, 0xc10c, 0x21, 0 - .dw 0x43c0, 0xc10c, 0x43ff, 0xc10c, 0x21, 0 - .dw 0x4440, 0xc10c, 0x447f, 0xc10c, 0x21, 0 - .dw 0x44c0, 0xc10c, 0x44ff, 0xc10c, 0x21, 0 - .dw 0x4540, 0xc10c, 0x457f, 0xc10c, 0x21, 0 - .dw 0x45c0, 0xc10c, 0x45ff, 0xc10c, 0x21, 0 - .dw 0x4640, 0xc10c, 0x467f, 0xc10c, 0x21, 0 - .dw 0x46c0, 0xc10c, 0x46ff, 0xc10c, 0x21, 0 - .dw 0x4740, 0xc10c, 0x477f, 0xc10c, 0x21, 0 - .dw 0x47c0, 0xc10c, 0x47ff, 0xc10c, 0x21, 0 - .dw 0x4840, 0xc10c, 0x487f, 0xc10c, 0x21, 0 - .dw 0x48c0, 0xc10c, 0x48ff, 0xc10c, 0x21, 0 - .dw 0x4940, 0xc10c, 0x497f, 0xc10c, 0x21, 0 - .dw 0x49c0, 0xc10c, 0x49ff, 0xc10c, 0x21, 0 - .dw 0x4a40, 0xc10c, 0x4a7f, 0xc10c, 0x21, 0 - .dw 0x4ac0, 0xc10c, 0x4aff, 0xc10c, 0x21, 0 - .dw 0x4b40, 0xc10c, 0x4b7f, 0xc10c, 0x21, 0 - .dw 0x4bc0, 0xc10c, 0x4bff, 0xc10c, 0x21, 0 - .dw 0x4c40, 0xc10c, 0x4c7f, 0xc10c, 0x21, 0 - .dw 0x4cc0, 0xc10c, 0x4cff, 0xc10c, 0x21, 0 - .dw 0x4d40, 0xc10c, 0x4d7f, 0xc10c, 0x21, 0 - .dw 0x4dc0, 0xc10c, 0x4dff, 0xc10c, 0x21, 0 - .dw 0x4e40, 0xc10c, 0x4e7f, 0xc10c, 0x21, 0 - .dw 0x4ec0, 0xc10c, 0x4eff, 0xc10c, 0x21, 0 - .dw 0x4f40, 0xc10c, 0x4f7f, 0xc10c, 0x21, 0 - .dw 0x4fc0, 0xc10c, 0x4fff, 0xc10c, 0x21, 0 - .dw 0x5040, 0xc10c, 0x507f, 0xc10c, 0x21, 0 - .dw 0x50c0, 0xc10c, 0x50ff, 0xc10c, 0x21, 0 - .dw 0x5140, 0xc10c, 0x517f, 0xc10c, 0x21, 0 - .dw 0x51c0, 0xc10c, 0x51ff, 0xc10c, 0x21, 0 - .dw 0x5240, 0xc10c, 0x527f, 0xc10c, 0x21, 0 - .dw 0x52c0, 0xc10c, 0x52ff, 0xc10c, 0x21, 0 - .dw 0x5340, 0xc10c, 0x537f, 0xc10c, 0x21, 0 - .dw 0x53c0, 0xc10c, 0x53ff, 0xc10c, 0x21, 0 - .dw 0x5440, 0xc10c, 0x547f, 0xc10c, 0x21, 0 - .dw 0x54c0, 0xc10c, 0x54ff, 0xc10c, 0x21, 0 - .dw 0x5540, 0xc10c, 0x557f, 0xc10c, 0x21, 0 - .dw 0x55c0, 0xc10c, 0x55ff, 0xc10c, 0x21, 0 - .dw 0x5640, 0xc10c, 0x567f, 0xc10c, 0x21, 0 - .dw 0x56c0, 0xc10c, 0x56ff, 0xc10c, 0x21, 0 - .dw 0x5740, 0xc10c, 0x577f, 0xc10c, 0x21, 0 - .dw 0x57c0, 0xc10c, 0x57ff, 0xc10c, 0x21, 0 - .dw 0x5840, 0xc10c, 0x587f, 0xc10c, 0x21, 0 - .dw 0x58c0, 0xc10c, 0x58ff, 0xc10c, 0x21, 0 - .dw 0x5940, 0xc10c, 0x597f, 0xc10c, 0x21, 0 - .dw 0x59c0, 0xc10c, 0x5fff, 0xc10c, 0x21, 0 - .dw 0x6040, 0xc10c, 0x607f, 0xc10c, 0x21, 0 - .dw 0x60c0, 0xc10c, 0x60ff, 0xc10c, 0x21, 0 - .dw 0x6140, 0xc10c, 0x617f, 0xc10c, 0x21, 0 - .dw 0x61c0, 0xc10c, 0x61ff, 0xc10c, 0x21, 0 - .dw 0x6240, 0xc10c, 0x627f, 0xc10c, 0x21, 0 - .dw 0x62c0, 0xc10c, 0x62ff, 0xc10c, 0x21, 0 - .dw 0x6340, 0xc10c, 0x637f, 0xc10c, 0x21, 0 - .dw 0x63c0, 0xc10c, 0x63ff, 0xc10c, 0x21, 0 - .dw 0x6440, 0xc10c, 0x647f, 0xc10c, 0x21, 0 - .dw 0x64c0, 0xc10c, 0x64ff, 0xc10c, 0x21, 0 - .dw 0x6540, 0xc10c, 0x657f, 0xc10c, 0x21, 0 - .dw 0x65c0, 0xc10c, 0x65ff, 0xc10c, 0x21, 0 - .dw 0x6640, 0xc10c, 0x667f, 0xc10c, 0x21, 0 - .dw 0x66c0, 0xc10c, 0x66ff, 0xc10c, 0x21, 0 - .dw 0x6740, 0xc10c, 0x677f, 0xc10c, 0x21, 0 - .dw 0x67c0, 0xc10c, 0x67ff, 0xc10c, 0x21, 0 - .dw 0x6840, 0xc10c, 0x687f, 0xc10c, 0x21, 0 - .dw 0x68c0, 0xc10c, 0x68ff, 0xc10c, 0x21, 0 - .dw 0x6940, 0xc10c, 0x697f, 0xc10c, 0x21, 0 - .dw 0x69c0, 0xc10c, 0x69ff, 0xc10c, 0x21, 0 - .dw 0x6a40, 0xc10c, 0x6a7f, 0xc10c, 0x21, 0 - .dw 0x6ac0, 0xc10c, 0x6aff, 0xc10c, 0x21, 0 - .dw 0x6b40, 0xc10c, 0x6b7f, 0xc10c, 0x21, 0 - .dw 0x6bc0, 0xc10c, 0x6bff, 0xc10c, 0x21, 0 - .dw 0x6c40, 0xc10c, 0x6c7f, 0xc10c, 0x21, 0 - .dw 0x6cc0, 0xc10c, 0x6cff, 0xc10c, 0x21, 0 - .dw 0x6d40, 0xc10c, 0x6d7f, 0xc10c, 0x21, 0 - .dw 0x6dc0, 0xc10c, 0x6dff, 0xc10c, 0x21, 0 - .dw 0x6e40, 0xc10c, 0x6e7f, 0xc10c, 0x21, 0 - .dw 0x6ec0, 0xc10c, 0x6eff, 0xc10c, 0x21, 0 - .dw 0x6f40, 0xc10c, 0x6f7f, 0xc10c, 0x21, 0 - .dw 0x6fc0, 0xc10c, 0x6fff, 0xc10c, 0x21, 0 - .dw 0x7040, 0xc10c, 0x707f, 0xc10c, 0x21, 0 - .dw 0x70c0, 0xc10c, 0x70ff, 0xc10c, 0x21, 0 - .dw 0x7140, 0xc10c, 0x717f, 0xc10c, 0x21, 0 - .dw 0x71c0, 0xc10c, 0x71ff, 0xc10c, 0x21, 0 - .dw 0x7240, 0xc10c, 0x727f, 0xc10c, 0x21, 0 - .dw 0x72c0, 0xc10c, 0x72ff, 0xc10c, 0x21, 0 - .dw 0x7340, 0xc10c, 0x737f, 0xc10c, 0x21, 0 - .dw 0x73c0, 0xc10c, 0x73ff, 0xc10c, 0x21, 0 - .dw 0x7440, 0xc10c, 0x747f, 0xc10c, 0x21, 0 - .dw 0x74c0, 0xc10c, 0x74ff, 0xc10c, 0x21, 0 - .dw 0x7540, 0xc10c, 0x757f, 0xc10c, 0x21, 0 - .dw 0x75c0, 0xc10c, 0x75ff, 0xc10c, 0x21, 0 - .dw 0x7640, 0xc10c, 0x767f, 0xc10c, 0x21, 0 - .dw 0x76c0, 0xc10c, 0x76ff, 0xc10c, 0x21, 0 - .dw 0x7740, 0xc10c, 0x777f, 0xc10c, 0x21, 0 - .dw 0x77c0, 0xc10c, 0x77ff, 0xc10c, 0x21, 0 - .dw 0x7840, 0xc10c, 0x787f, 0xc10c, 0x21, 0 - .dw 0x78c0, 0xc10c, 0x78ff, 0xc10c, 0x21, 0 - .dw 0x7940, 0xc10c, 0x797f, 0xc10c, 0x21, 0 - .dw 0x79c0, 0xc10c, 0x7fff, 0xc10c, 0x21, 0 - .dw 0x8040, 0xc10c, 0x807f, 0xc10c, 0x21, 0 - .dw 0x80c0, 0xc10c, 0x80ff, 0xc10c, 0x21, 0 - .dw 0x8140, 0xc10c, 0x817f, 0xc10c, 0x21, 0 - .dw 0x81c0, 0xc10c, 0x81ff, 0xc10c, 0x21, 0 - .dw 0x8240, 0xc10c, 0x827f, 0xc10c, 0x21, 0 - .dw 0x82c0, 0xc10c, 0x82ff, 0xc10c, 0x21, 0 - .dw 0x8340, 0xc10c, 0x837f, 0xc10c, 0x21, 0 - .dw 0x83c0, 0xc10c, 0x83ff, 0xc10c, 0x21, 0 - .dw 0x8440, 0xc10c, 0x847f, 0xc10c, 0x21, 0 - .dw 0x84c0, 0xc10c, 0x84ff, 0xc10c, 0x21, 0 - .dw 0x8540, 0xc10c, 0x857f, 0xc10c, 0x21, 0 - .dw 0x85c0, 0xc10c, 0x85ff, 0xc10c, 0x21, 0 - .dw 0x8640, 0xc10c, 0x867f, 0xc10c, 0x21, 0 - .dw 0x86c0, 0xc10c, 0x86ff, 0xc10c, 0x21, 0 - .dw 0x8740, 0xc10c, 0x877f, 0xc10c, 0x21, 0 - .dw 0x87c0, 0xc10c, 0x87ff, 0xc10c, 0x21, 0 - .dw 0x8840, 0xc10c, 0x887f, 0xc10c, 0x21, 0 - .dw 0x88c0, 0xc10c, 0x88ff, 0xc10c, 0x21, 0 - .dw 0x8940, 0xc10c, 0x897f, 0xc10c, 0x21, 0 - .dw 0x89c0, 0xc10c, 0x89ff, 0xc10c, 0x21, 0 - .dw 0x8a40, 0xc10c, 0x8a7f, 0xc10c, 0x21, 0 - .dw 0x8ac0, 0xc10c, 0x8aff, 0xc10c, 0x21, 0 - .dw 0x8b40, 0xc10c, 0x8b7f, 0xc10c, 0x21, 0 - .dw 0x8bc0, 0xc10c, 0x8bff, 0xc10c, 0x21, 0 - .dw 0x8c40, 0xc10c, 0x8c7f, 0xc10c, 0x21, 0 - .dw 0x8cc0, 0xc10c, 0x8cff, 0xc10c, 0x21, 0 - .dw 0x8d40, 0xc10c, 0x8d7f, 0xc10c, 0x21, 0 - .dw 0x8dc0, 0xc10c, 0x8dff, 0xc10c, 0x21, 0 - .dw 0x8e40, 0xc10c, 0x8e7f, 0xc10c, 0x21, 0 - .dw 0x8ec0, 0xc10c, 0x8eff, 0xc10c, 0x21, 0 - .dw 0x8f40, 0xc10c, 0x8f7f, 0xc10c, 0x21, 0 - .dw 0x8fc0, 0xc10c, 0x8fff, 0xc10c, 0x21, 0 - .dw 0x9040, 0xc10c, 0x907f, 0xc10c, 0x21, 0 - .dw 0x90c0, 0xc10c, 0x90ff, 0xc10c, 0x21, 0 - .dw 0x9140, 0xc10c, 0x917f, 0xc10c, 0x21, 0 - .dw 0x91c0, 0xc10c, 0x91ff, 0xc10c, 0x21, 0 - .dw 0x9240, 0xc10c, 0x927f, 0xc10c, 0x21, 0 - .dw 0x92c0, 0xc10c, 0x92ff, 0xc10c, 0x21, 0 - .dw 0x9340, 0xc10c, 0x937f, 0xc10c, 0x21, 0 - .dw 0x93c0, 0xc10c, 0x93ff, 0xc10c, 0x21, 0 - .dw 0x9440, 0xc10c, 0x947f, 0xc10c, 0x21, 0 - .dw 0x94c0, 0xc10c, 0x94ff, 0xc10c, 0x21, 0 - .dw 0x9540, 0xc10c, 0x957f, 0xc10c, 0x21, 0 - .dw 0x95c0, 0xc10c, 0x95ff, 0xc10c, 0x21, 0 - .dw 0x9640, 0xc10c, 0x967f, 0xc10c, 0x21, 0 - .dw 0x96c0, 0xc10c, 0x96ff, 0xc10c, 0x21, 0 - .dw 0x9740, 0xc10c, 0x977f, 0xc10c, 0x21, 0 - .dw 0x97c0, 0xc10c, 0x97ff, 0xc10c, 0x21, 0 - .dw 0x9840, 0xc10c, 0x987f, 0xc10c, 0x21, 0 - .dw 0x98c0, 0xc10c, 0x98ff, 0xc10c, 0x21, 0 - .dw 0x9940, 0xc10c, 0x997f, 0xc10c, 0x21, 0 - .dw 0x99c0, 0xc10c, 0x9fff, 0xc10c, 0x21, 0 - .dw 0xa040, 0xc10c, 0xa07f, 0xc10c, 0x21, 0 - .dw 0xa0c0, 0xc10c, 0xa0ff, 0xc10c, 0x21, 0 - .dw 0xa140, 0xc10c, 0xa17f, 0xc10c, 0x21, 0 - .dw 0xa1c0, 0xc10c, 0xa1ff, 0xc10c, 0x21, 0 - .dw 0xa240, 0xc10c, 0xa27f, 0xc10c, 0x21, 0 - .dw 0xa2c0, 0xc10c, 0xa2ff, 0xc10c, 0x21, 0 - .dw 0xa340, 0xc10c, 0xa37f, 0xc10c, 0x21, 0 - .dw 0xa3c0, 0xc10c, 0xa3ff, 0xc10c, 0x21, 0 - .dw 0xa440, 0xc10c, 0xa47f, 0xc10c, 0x21, 0 - .dw 0xa4c0, 0xc10c, 0xa4ff, 0xc10c, 0x21, 0 - .dw 0xa540, 0xc10c, 0xa57f, 0xc10c, 0x21, 0 - .dw 0xa5c0, 0xc10c, 0xa5ff, 0xc10c, 0x21, 0 - .dw 0xa640, 0xc10c, 0xa67f, 0xc10c, 0x21, 0 - .dw 0xa6c0, 0xc10c, 0xa6ff, 0xc10c, 0x21, 0 - .dw 0xa740, 0xc10c, 0xa77f, 0xc10c, 0x21, 0 - .dw 0xa7c0, 0xc10c, 0xa7ff, 0xc10c, 0x21, 0 - .dw 0xa840, 0xc10c, 0xa87f, 0xc10c, 0x21, 0 - .dw 0xa8c0, 0xc10c, 0xa8ff, 0xc10c, 0x21, 0 - .dw 0xa940, 0xc10c, 0xa97f, 0xc10c, 0x21, 0 - .dw 0xa9c0, 0xc10c, 0xa9ff, 0xc10c, 0x21, 0 - .dw 0xaa40, 0xc10c, 0xaa7f, 0xc10c, 0x21, 0 - .dw 0xaac0, 0xc10c, 0xaaff, 0xc10c, 0x21, 0 - .dw 0xab40, 0xc10c, 0xab7f, 0xc10c, 0x21, 0 - .dw 0xabc0, 0xc10c, 0xabff, 0xc10c, 0x21, 0 - .dw 0xac40, 0xc10c, 0xac7f, 0xc10c, 0x21, 0 - .dw 0xacc0, 0xc10c, 0xacff, 0xc10c, 0x21, 0 - .dw 0xad40, 0xc10c, 0xad7f, 0xc10c, 0x21, 0 - .dw 0xadc0, 0xc10c, 0xadff, 0xc10c, 0x21, 0 - .dw 0xae40, 0xc10c, 0xae7f, 0xc10c, 0x21, 0 - .dw 0xaec0, 0xc10c, 0xaeff, 0xc10c, 0x21, 0 - .dw 0xaf40, 0xc10c, 0xaf7f, 0xc10c, 0x21, 0 - .dw 0xafc0, 0xc10c, 0xafff, 0xc10c, 0x21, 0 - .dw 0xb040, 0xc10c, 0xb07f, 0xc10c, 0x21, 0 - .dw 0xb0c0, 0xc10c, 0xb0ff, 0xc10c, 0x21, 0 - .dw 0xb140, 0xc10c, 0xb17f, 0xc10c, 0x21, 0 - .dw 0xb1c0, 0xc10c, 0xb1ff, 0xc10c, 0x21, 0 - .dw 0xb240, 0xc10c, 0xb27f, 0xc10c, 0x21, 0 - .dw 0xb2c0, 0xc10c, 0xb2ff, 0xc10c, 0x21, 0 - .dw 0xb340, 0xc10c, 0xb37f, 0xc10c, 0x21, 0 - .dw 0xb3c0, 0xc10c, 0xb3ff, 0xc10c, 0x21, 0 - .dw 0xb440, 0xc10c, 0xb47f, 0xc10c, 0x21, 0 - .dw 0xb4c0, 0xc10c, 0xb4ff, 0xc10c, 0x21, 0 - .dw 0xb540, 0xc10c, 0xb57f, 0xc10c, 0x21, 0 - .dw 0xb5c0, 0xc10c, 0xb5ff, 0xc10c, 0x21, 0 - .dw 0xb640, 0xc10c, 0xb67f, 0xc10c, 0x21, 0 - .dw 0xb6c0, 0xc10c, 0xb6ff, 0xc10c, 0x21, 0 - .dw 0xb740, 0xc10c, 0xb77f, 0xc10c, 0x21, 0 - .dw 0xb7c0, 0xc10c, 0xb7ff, 0xc10c, 0x21, 0 - .dw 0xb840, 0xc10c, 0xb87f, 0xc10c, 0x21, 0 - .dw 0xb8c0, 0xc10c, 0xb8ff, 0xc10c, 0x21, 0 - .dw 0xb940, 0xc10c, 0xb97f, 0xc10c, 0x21, 0 - .dw 0xb9c0, 0xc10c, 0xbfff, 0xc10c, 0x21, 0 - .dw 0xc040, 0xc10c, 0xc07f, 0xc10c, 0x21, 0 - .dw 0xc0c0, 0xc10c, 0xc0ff, 0xc10c, 0x21, 0 - .dw 0xc140, 0xc10c, 0xc17f, 0xc10c, 0x21, 0 - .dw 0xc1c0, 0xc10c, 0xc1ff, 0xc10c, 0x21, 0 - .dw 0xc240, 0xc10c, 0xc27f, 0xc10c, 0x21, 0 - .dw 0xc2c0, 0xc10c, 0xc2ff, 0xc10c, 0x21, 0 - .dw 0xc340, 0xc10c, 0xc37f, 0xc10c, 0x21, 0 - .dw 0xc3c0, 0xc10c, 0xc3ff, 0xc10c, 0x21, 0 - .dw 0xc440, 0xc10c, 0xc47f, 0xc10c, 0x21, 0 - .dw 0xc4c0, 0xc10c, 0xc4ff, 0xc10c, 0x21, 0 - .dw 0xc540, 0xc10c, 0xc57f, 0xc10c, 0x21, 0 - .dw 0xc5c0, 0xc10c, 0xc5ff, 0xc10c, 0x21, 0 - .dw 0xc640, 0xc10c, 0xc67f, 0xc10c, 0x21, 0 - .dw 0xc6c0, 0xc10c, 0xc6ff, 0xc10c, 0x21, 0 - .dw 0xc740, 0xc10c, 0xc77f, 0xc10c, 0x21, 0 - .dw 0xc7c0, 0xc10c, 0xc7ff, 0xc10c, 0x21, 0 - .dw 0xc840, 0xc10c, 0xc87f, 0xc10c, 0x21, 0 - .dw 0xc8c0, 0xc10c, 0xc8ff, 0xc10c, 0x21, 0 - .dw 0xc940, 0xc10c, 0xc97f, 0xc10c, 0x21, 0 - .dw 0xc9c0, 0xc10c, 0xc9ff, 0xc10c, 0x21, 0 - .dw 0xca40, 0xc10c, 0xca7f, 0xc10c, 0x21, 0 - .dw 0xcac0, 0xc10c, 0xcaff, 0xc10c, 0x21, 0 - .dw 0xcb40, 0xc10c, 0xcb7f, 0xc10c, 0x21, 0 - .dw 0xcbc0, 0xc10c, 0xcbff, 0xc10c, 0x21, 0 - .dw 0xcc40, 0xc10c, 0xcc7f, 0xc10c, 0x21, 0 - .dw 0xccc0, 0xc10c, 0xccff, 0xc10c, 0x21, 0 - .dw 0xcd40, 0xc10c, 0xcd7f, 0xc10c, 0x21, 0 - .dw 0xcdc0, 0xc10c, 0xcdff, 0xc10c, 0x21, 0 - .dw 0xce40, 0xc10c, 0xce7f, 0xc10c, 0x21, 0 - .dw 0xcec0, 0xc10c, 0xceff, 0xc10c, 0x21, 0 - .dw 0xcf40, 0xc10c, 0xcf7f, 0xc10c, 0x21, 0 - .dw 0xcfc0, 0xc10c, 0xcfff, 0xc10c, 0x21, 0 - .dw 0xd040, 0xc10c, 0xd07f, 0xc10c, 0x21, 0 - .dw 0xd0c0, 0xc10c, 0xd0ff, 0xc10c, 0x21, 0 - .dw 0xd140, 0xc10c, 0xd17f, 0xc10c, 0x21, 0 - .dw 0xd1c0, 0xc10c, 0xd1ff, 0xc10c, 0x21, 0 - .dw 0xd240, 0xc10c, 0xd27f, 0xc10c, 0x21, 0 - .dw 0xd2c0, 0xc10c, 0xd2ff, 0xc10c, 0x21, 0 - .dw 0xd340, 0xc10c, 0xd37f, 0xc10c, 0x21, 0 - .dw 0xd3c0, 0xc10c, 0xd3ff, 0xc10c, 0x21, 0 - .dw 0xd440, 0xc10c, 0xd47f, 0xc10c, 0x21, 0 - .dw 0xd4c0, 0xc10c, 0xd4ff, 0xc10c, 0x21, 0 - .dw 0xd540, 0xc10c, 0xd57f, 0xc10c, 0x21, 0 - .dw 0xd5c0, 0xc10c, 0xd5ff, 0xc10c, 0x21, 0 - .dw 0xd640, 0xc10c, 0xd67f, 0xc10c, 0x21, 0 - .dw 0xd6c0, 0xc10c, 0xd6ff, 0xc10c, 0x21, 0 - .dw 0xd740, 0xc10c, 0xd77f, 0xc10c, 0x21, 0 - .dw 0xd7c0, 0xc10c, 0xd7ff, 0xc10c, 0x21, 0 - .dw 0xd840, 0xc10c, 0xd87f, 0xc10c, 0x21, 0 - .dw 0xd8c0, 0xc10c, 0xd8ff, 0xc10c, 0x21, 0 - .dw 0xd940, 0xc10c, 0xd97f, 0xc10c, 0x21, 0 - .dw 0xd9c0, 0xc10c, 0xdfff, 0xc10c, 0x21, 0 - .dw 0xe040, 0xc10c, 0xe07f, 0xc10c, 0x21, 0 - .dw 0xe0c0, 0xc10c, 0xe0ff, 0xc10c, 0x21, 0 - .dw 0xe140, 0xc10c, 0xe17f, 0xc10c, 0x21, 0 - .dw 0xe1c0, 0xc10c, 0xe1ff, 0xc10c, 0x21, 0 - .dw 0xe240, 0xc10c, 0xe27f, 0xc10c, 0x21, 0 - .dw 0xe2c0, 0xc10c, 0xe2ff, 0xc10c, 0x21, 0 - .dw 0xe340, 0xc10c, 0xe37f, 0xc10c, 0x21, 0 - .dw 0xe3c0, 0xc10c, 0xe3ff, 0xc10c, 0x21, 0 - .dw 0xe440, 0xc10c, 0xe47f, 0xc10c, 0x21, 0 - .dw 0xe4c0, 0xc10c, 0xe4ff, 0xc10c, 0x21, 0 - .dw 0xe540, 0xc10c, 0xe57f, 0xc10c, 0x21, 0 - .dw 0xe5c0, 0xc10c, 0xe5ff, 0xc10c, 0x21, 0 - .dw 0xe640, 0xc10c, 0xe67f, 0xc10c, 0x21, 0 - .dw 0xe6c0, 0xc10c, 0xe6ff, 0xc10c, 0x21, 0 - .dw 0xe740, 0xc10c, 0xe77f, 0xc10c, 0x21, 0 - .dw 0xe7c0, 0xc10c, 0xe7ff, 0xc10c, 0x21, 0 - .dw 0xe840, 0xc10c, 0xe87f, 0xc10c, 0x21, 0 - .dw 0xe8c0, 0xc10c, 0xe8ff, 0xc10c, 0x21, 0 - .dw 0xe940, 0xc10c, 0xe97f, 0xc10c, 0x21, 0 - .dw 0xe9c0, 0xc10c, 0xe9ff, 0xc10c, 0x21, 0 - .dw 0xea40, 0xc10c, 0xea7f, 0xc10c, 0x21, 0 - .dw 0xeac0, 0xc10c, 0xeaff, 0xc10c, 0x21, 0 - .dw 0xeb40, 0xc10c, 0xeb7f, 0xc10c, 0x21, 0 - .dw 0xebc0, 0xc10c, 0xebff, 0xc10c, 0x21, 0 - .dw 0xec40, 0xc10c, 0xec7f, 0xc10c, 0x21, 0 - .dw 0xecc0, 0xc10c, 0xecff, 0xc10c, 0x21, 0 - .dw 0xed40, 0xc10c, 0xed7f, 0xc10c, 0x21, 0 - .dw 0xedc0, 0xc10c, 0xedff, 0xc10c, 0x21, 0 - .dw 0xee40, 0xc10c, 0xee7f, 0xc10c, 0x21, 0 - .dw 0xeec0, 0xc10c, 0xeeff, 0xc10c, 0x21, 0 - .dw 0xef40, 0xc10c, 0xef7f, 0xc10c, 0x21, 0 - .dw 0xefc0, 0xc10c, 0xefff, 0xc10c, 0x21, 0 - .dw 0xf040, 0xc10c, 0xf07f, 0xc10c, 0x21, 0 - .dw 0xf0c0, 0xc10c, 0xf0ff, 0xc10c, 0x21, 0 - .dw 0xf140, 0xc10c, 0xf17f, 0xc10c, 0x21, 0 - .dw 0xf1c0, 0xc10c, 0xf1ff, 0xc10c, 0x21, 0 - .dw 0xf240, 0xc10c, 0xf27f, 0xc10c, 0x21, 0 - .dw 0xf2c0, 0xc10c, 0xf2ff, 0xc10c, 0x21, 0 - .dw 0xf340, 0xc10c, 0xf37f, 0xc10c, 0x21, 0 - .dw 0xf3c0, 0xc10c, 0xf3ff, 0xc10c, 0x21, 0 - .dw 0xf440, 0xc10c, 0xf47f, 0xc10c, 0x21, 0 - .dw 0xf4c0, 0xc10c, 0xf4ff, 0xc10c, 0x21, 0 - .dw 0xf540, 0xc10c, 0xf57f, 0xc10c, 0x21, 0 - .dw 0xf5c0, 0xc10c, 0xf5ff, 0xc10c, 0x21, 0 - .dw 0xf640, 0xc10c, 0xf67f, 0xc10c, 0x21, 0 - .dw 0xf6c0, 0xc10c, 0xf6ff, 0xc10c, 0x21, 0 - .dw 0xf740, 0xc10c, 0xf77f, 0xc10c, 0x21, 0 - .dw 0xf7c0, 0xc10c, 0xf7ff, 0xc10c, 0x21, 0 - .dw 0xf840, 0xc10c, 0xf87f, 0xc10c, 0x21, 0 - .dw 0xf8c0, 0xc10c, 0xf8ff, 0xc10c, 0x21, 0 - .dw 0xf940, 0xc10c, 0xf97f, 0xc10c, 0x21, 0 - .dw 0xf9c0, 0xc10c, 0xffff, 0xc10c, 0x21, 0 - .dw 0x0040, 0xc10d, 0x007f, 0xc10d, 0x21, 0 - .dw 0x00c0, 0xc10d, 0x00ff, 0xc10d, 0x21, 0 - .dw 0x0140, 0xc10d, 0x017f, 0xc10d, 0x21, 0 - .dw 0x01c0, 0xc10d, 0x01ff, 0xc10d, 0x21, 0 - .dw 0x0240, 0xc10d, 0x027f, 0xc10d, 0x21, 0 - .dw 0x02c0, 0xc10d, 0x02ff, 0xc10d, 0x21, 0 - .dw 0x0340, 0xc10d, 0x037f, 0xc10d, 0x21, 0 - .dw 0x03c0, 0xc10d, 0x03ff, 0xc10d, 0x21, 0 - .dw 0x0440, 0xc10d, 0x047f, 0xc10d, 0x21, 0 - .dw 0x04c0, 0xc10d, 0x04ff, 0xc10d, 0x21, 0 - .dw 0x0540, 0xc10d, 0x057f, 0xc10d, 0x21, 0 - .dw 0x05c0, 0xc10d, 0x05ff, 0xc10d, 0x21, 0 - .dw 0x0640, 0xc10d, 0x067f, 0xc10d, 0x21, 0 - .dw 0x06c0, 0xc10d, 0x06ff, 0xc10d, 0x21, 0 - .dw 0x0740, 0xc10d, 0x077f, 0xc10d, 0x21, 0 - .dw 0x07c0, 0xc10d, 0x07ff, 0xc10d, 0x21, 0 - .dw 0x0840, 0xc10d, 0x087f, 0xc10d, 0x21, 0 - .dw 0x08c0, 0xc10d, 0x08ff, 0xc10d, 0x21, 0 - .dw 0x0940, 0xc10d, 0x097f, 0xc10d, 0x21, 0 - .dw 0x09c0, 0xc10d, 0x09ff, 0xc10d, 0x21, 0 - .dw 0x0a40, 0xc10d, 0x0a7f, 0xc10d, 0x21, 0 - .dw 0x0ac0, 0xc10d, 0x0aff, 0xc10d, 0x21, 0 - .dw 0x0b40, 0xc10d, 0x0b7f, 0xc10d, 0x21, 0 - .dw 0x0bc0, 0xc10d, 0x0bff, 0xc10d, 0x21, 0 - .dw 0x0c40, 0xc10d, 0x0c7f, 0xc10d, 0x21, 0 - .dw 0x0cc0, 0xc10d, 0x0cff, 0xc10d, 0x21, 0 - .dw 0x0d40, 0xc10d, 0x0d7f, 0xc10d, 0x21, 0 - .dw 0x0dc0, 0xc10d, 0x0dff, 0xc10d, 0x21, 0 - .dw 0x0e40, 0xc10d, 0x0e7f, 0xc10d, 0x21, 0 - .dw 0x0ec0, 0xc10d, 0x0eff, 0xc10d, 0x21, 0 - .dw 0x0f40, 0xc10d, 0x0f7f, 0xc10d, 0x21, 0 - .dw 0x0fc0, 0xc10d, 0x0fff, 0xc10d, 0x21, 0 - .dw 0x1040, 0xc10d, 0x107f, 0xc10d, 0x21, 0 - .dw 0x10c0, 0xc10d, 0x10ff, 0xc10d, 0x21, 0 - .dw 0x1140, 0xc10d, 0x117f, 0xc10d, 0x21, 0 - .dw 0x11c0, 0xc10d, 0x11ff, 0xc10d, 0x21, 0 - .dw 0x1240, 0xc10d, 0x127f, 0xc10d, 0x21, 0 - .dw 0x12c0, 0xc10d, 0x12ff, 0xc10d, 0x21, 0 - .dw 0x1340, 0xc10d, 0x137f, 0xc10d, 0x21, 0 - .dw 0x13c0, 0xc10d, 0x13ff, 0xc10d, 0x21, 0 - .dw 0x1440, 0xc10d, 0x147f, 0xc10d, 0x21, 0 - .dw 0x14c0, 0xc10d, 0x14ff, 0xc10d, 0x21, 0 - .dw 0x1540, 0xc10d, 0x157f, 0xc10d, 0x21, 0 - .dw 0x15c0, 0xc10d, 0x15ff, 0xc10d, 0x21, 0 - .dw 0x1640, 0xc10d, 0x167f, 0xc10d, 0x21, 0 - .dw 0x16c0, 0xc10d, 0x16ff, 0xc10d, 0x21, 0 - .dw 0x1740, 0xc10d, 0x177f, 0xc10d, 0x21, 0 - .dw 0x17c0, 0xc10d, 0x17ff, 0xc10d, 0x21, 0 - .dw 0x1840, 0xc10d, 0x187f, 0xc10d, 0x21, 0 - .dw 0x18c0, 0xc10d, 0x18ff, 0xc10d, 0x21, 0 - .dw 0x1940, 0xc10d, 0x197f, 0xc10d, 0x21, 0 - .dw 0x19c0, 0xc10d, 0x1fff, 0xc10d, 0x21, 0 - .dw 0x2040, 0xc10d, 0x207f, 0xc10d, 0x21, 0 - .dw 0x20c0, 0xc10d, 0x20ff, 0xc10d, 0x21, 0 - .dw 0x2140, 0xc10d, 0x217f, 0xc10d, 0x21, 0 - .dw 0x21c0, 0xc10d, 0x21ff, 0xc10d, 0x21, 0 - .dw 0x2240, 0xc10d, 0x227f, 0xc10d, 0x21, 0 - .dw 0x22c0, 0xc10d, 0x22ff, 0xc10d, 0x21, 0 - .dw 0x2340, 0xc10d, 0x237f, 0xc10d, 0x21, 0 - .dw 0x23c0, 0xc10d, 0x23ff, 0xc10d, 0x21, 0 - .dw 0x2440, 0xc10d, 0x247f, 0xc10d, 0x21, 0 - .dw 0x24c0, 0xc10d, 0x24ff, 0xc10d, 0x21, 0 - .dw 0x2540, 0xc10d, 0x257f, 0xc10d, 0x21, 0 - .dw 0x25c0, 0xc10d, 0x25ff, 0xc10d, 0x21, 0 - .dw 0x2640, 0xc10d, 0x267f, 0xc10d, 0x21, 0 - .dw 0x26c0, 0xc10d, 0x26ff, 0xc10d, 0x21, 0 - .dw 0x2740, 0xc10d, 0x277f, 0xc10d, 0x21, 0 - .dw 0x27c0, 0xc10d, 0x27ff, 0xc10d, 0x21, 0 - .dw 0x2840, 0xc10d, 0x287f, 0xc10d, 0x21, 0 - .dw 0x28c0, 0xc10d, 0x28ff, 0xc10d, 0x21, 0 - .dw 0x2940, 0xc10d, 0x297f, 0xc10d, 0x21, 0 - .dw 0x29c0, 0xc10d, 0x29ff, 0xc10d, 0x21, 0 - .dw 0x2a40, 0xc10d, 0x2a7f, 0xc10d, 0x21, 0 - .dw 0x2ac0, 0xc10d, 0x2aff, 0xc10d, 0x21, 0 - .dw 0x2b40, 0xc10d, 0x2b7f, 0xc10d, 0x21, 0 - .dw 0x2bc0, 0xc10d, 0x2bff, 0xc10d, 0x21, 0 - .dw 0x2c40, 0xc10d, 0x2c7f, 0xc10d, 0x21, 0 - .dw 0x2cc0, 0xc10d, 0x2cff, 0xc10d, 0x21, 0 - .dw 0x2d40, 0xc10d, 0x2d7f, 0xc10d, 0x21, 0 - .dw 0x2dc0, 0xc10d, 0x2dff, 0xc10d, 0x21, 0 - .dw 0x2e40, 0xc10d, 0x2e7f, 0xc10d, 0x21, 0 - .dw 0x2ec0, 0xc10d, 0x2eff, 0xc10d, 0x21, 0 - .dw 0x2f40, 0xc10d, 0x2f7f, 0xc10d, 0x21, 0 - .dw 0x2fc0, 0xc10d, 0x2fff, 0xc10d, 0x21, 0 - .dw 0x3040, 0xc10d, 0x307f, 0xc10d, 0x21, 0 - .dw 0x30c0, 0xc10d, 0x30ff, 0xc10d, 0x21, 0 - .dw 0x3140, 0xc10d, 0x317f, 0xc10d, 0x21, 0 - .dw 0x31c0, 0xc10d, 0x31ff, 0xc10d, 0x21, 0 - .dw 0x3240, 0xc10d, 0x327f, 0xc10d, 0x21, 0 - .dw 0x32c0, 0xc10d, 0x32ff, 0xc10d, 0x21, 0 - .dw 0x3340, 0xc10d, 0x337f, 0xc10d, 0x21, 0 - .dw 0x33c0, 0xc10d, 0x33ff, 0xc10d, 0x21, 0 - .dw 0x3440, 0xc10d, 0x347f, 0xc10d, 0x21, 0 - .dw 0x34c0, 0xc10d, 0x34ff, 0xc10d, 0x21, 0 - .dw 0x3540, 0xc10d, 0x357f, 0xc10d, 0x21, 0 - .dw 0x35c0, 0xc10d, 0x35ff, 0xc10d, 0x21, 0 - .dw 0x3640, 0xc10d, 0x367f, 0xc10d, 0x21, 0 - .dw 0x36c0, 0xc10d, 0x36ff, 0xc10d, 0x21, 0 - .dw 0x3740, 0xc10d, 0x377f, 0xc10d, 0x21, 0 - .dw 0x37c0, 0xc10d, 0x37ff, 0xc10d, 0x21, 0 - .dw 0x3840, 0xc10d, 0x387f, 0xc10d, 0x21, 0 - .dw 0x38c0, 0xc10d, 0x38ff, 0xc10d, 0x21, 0 - .dw 0x3940, 0xc10d, 0x397f, 0xc10d, 0x21, 0 - .dw 0x39c0, 0xc10d, 0x3fff, 0xc10d, 0x21, 0 - .dw 0x4040, 0xc10d, 0x407f, 0xc10d, 0x21, 0 - .dw 0x40c0, 0xc10d, 0x40ff, 0xc10d, 0x21, 0 - .dw 0x4140, 0xc10d, 0x417f, 0xc10d, 0x21, 0 - .dw 0x41c0, 0xc10d, 0x41ff, 0xc10d, 0x21, 0 - .dw 0x4240, 0xc10d, 0x427f, 0xc10d, 0x21, 0 - .dw 0x42c0, 0xc10d, 0x42ff, 0xc10d, 0x21, 0 - .dw 0x4340, 0xc10d, 0x437f, 0xc10d, 0x21, 0 - .dw 0x43c0, 0xc10d, 0x43ff, 0xc10d, 0x21, 0 - .dw 0x4440, 0xc10d, 0x447f, 0xc10d, 0x21, 0 - .dw 0x44c0, 0xc10d, 0x44ff, 0xc10d, 0x21, 0 - .dw 0x4540, 0xc10d, 0x457f, 0xc10d, 0x21, 0 - .dw 0x45c0, 0xc10d, 0x45ff, 0xc10d, 0x21, 0 - .dw 0x4640, 0xc10d, 0x467f, 0xc10d, 0x21, 0 - .dw 0x46c0, 0xc10d, 0x46ff, 0xc10d, 0x21, 0 - .dw 0x4740, 0xc10d, 0x477f, 0xc10d, 0x21, 0 - .dw 0x47c0, 0xc10d, 0x47ff, 0xc10d, 0x21, 0 - .dw 0x4840, 0xc10d, 0x487f, 0xc10d, 0x21, 0 - .dw 0x48c0, 0xc10d, 0x48ff, 0xc10d, 0x21, 0 - .dw 0x4940, 0xc10d, 0x497f, 0xc10d, 0x21, 0 - .dw 0x49c0, 0xc10d, 0x49ff, 0xc10d, 0x21, 0 - .dw 0x4a40, 0xc10d, 0x4a7f, 0xc10d, 0x21, 0 - .dw 0x4ac0, 0xc10d, 0x4aff, 0xc10d, 0x21, 0 - .dw 0x4b40, 0xc10d, 0x4b7f, 0xc10d, 0x21, 0 - .dw 0x4bc0, 0xc10d, 0x4bff, 0xc10d, 0x21, 0 - .dw 0x4c40, 0xc10d, 0x4c7f, 0xc10d, 0x21, 0 - .dw 0x4cc0, 0xc10d, 0x4cff, 0xc10d, 0x21, 0 - .dw 0x4d40, 0xc10d, 0x4d7f, 0xc10d, 0x21, 0 - .dw 0x4dc0, 0xc10d, 0x4dff, 0xc10d, 0x21, 0 - .dw 0x4e40, 0xc10d, 0x4e7f, 0xc10d, 0x21, 0 - .dw 0x4ec0, 0xc10d, 0x4eff, 0xc10d, 0x21, 0 - .dw 0x4f40, 0xc10d, 0x4f7f, 0xc10d, 0x21, 0 - .dw 0x4fc0, 0xc10d, 0x4fff, 0xc10d, 0x21, 0 - .dw 0x5040, 0xc10d, 0x507f, 0xc10d, 0x21, 0 - .dw 0x50c0, 0xc10d, 0x50ff, 0xc10d, 0x21, 0 - .dw 0x5140, 0xc10d, 0x517f, 0xc10d, 0x21, 0 - .dw 0x51c0, 0xc10d, 0x51ff, 0xc10d, 0x21, 0 - .dw 0x5240, 0xc10d, 0x527f, 0xc10d, 0x21, 0 - .dw 0x52c0, 0xc10d, 0x52ff, 0xc10d, 0x21, 0 - .dw 0x5340, 0xc10d, 0x537f, 0xc10d, 0x21, 0 - .dw 0x53c0, 0xc10d, 0x53ff, 0xc10d, 0x21, 0 - .dw 0x5440, 0xc10d, 0x547f, 0xc10d, 0x21, 0 - .dw 0x54c0, 0xc10d, 0x54ff, 0xc10d, 0x21, 0 - .dw 0x5540, 0xc10d, 0x557f, 0xc10d, 0x21, 0 - .dw 0x55c0, 0xc10d, 0x55ff, 0xc10d, 0x21, 0 - .dw 0x5640, 0xc10d, 0x567f, 0xc10d, 0x21, 0 - .dw 0x56c0, 0xc10d, 0x56ff, 0xc10d, 0x21, 0 - .dw 0x5740, 0xc10d, 0x577f, 0xc10d, 0x21, 0 - .dw 0x57c0, 0xc10d, 0x57ff, 0xc10d, 0x21, 0 - .dw 0x5840, 0xc10d, 0x587f, 0xc10d, 0x21, 0 - .dw 0x58c0, 0xc10d, 0x58ff, 0xc10d, 0x21, 0 - .dw 0x5940, 0xc10d, 0x597f, 0xc10d, 0x21, 0 - .dw 0x59c0, 0xc10d, 0x5fff, 0xc10d, 0x21, 0 - .dw 0x6040, 0xc10d, 0x607f, 0xc10d, 0x21, 0 - .dw 0x60c0, 0xc10d, 0x60ff, 0xc10d, 0x21, 0 - .dw 0x6140, 0xc10d, 0x617f, 0xc10d, 0x21, 0 - .dw 0x61c0, 0xc10d, 0x61ff, 0xc10d, 0x21, 0 - .dw 0x6240, 0xc10d, 0x627f, 0xc10d, 0x21, 0 - .dw 0x62c0, 0xc10d, 0x62ff, 0xc10d, 0x21, 0 - .dw 0x6340, 0xc10d, 0x637f, 0xc10d, 0x21, 0 - .dw 0x63c0, 0xc10d, 0x63ff, 0xc10d, 0x21, 0 - .dw 0x6440, 0xc10d, 0x647f, 0xc10d, 0x21, 0 - .dw 0x64c0, 0xc10d, 0x64ff, 0xc10d, 0x21, 0 - .dw 0x6540, 0xc10d, 0x657f, 0xc10d, 0x21, 0 - .dw 0x65c0, 0xc10d, 0x65ff, 0xc10d, 0x21, 0 - .dw 0x6640, 0xc10d, 0x667f, 0xc10d, 0x21, 0 - .dw 0x66c0, 0xc10d, 0x66ff, 0xc10d, 0x21, 0 - .dw 0x6740, 0xc10d, 0x677f, 0xc10d, 0x21, 0 - .dw 0x67c0, 0xc10d, 0x67ff, 0xc10d, 0x21, 0 - .dw 0x6840, 0xc10d, 0x687f, 0xc10d, 0x21, 0 - .dw 0x68c0, 0xc10d, 0x68ff, 0xc10d, 0x21, 0 - .dw 0x6940, 0xc10d, 0x697f, 0xc10d, 0x21, 0 - .dw 0x69c0, 0xc10d, 0x69ff, 0xc10d, 0x21, 0 - .dw 0x6a40, 0xc10d, 0x6a7f, 0xc10d, 0x21, 0 - .dw 0x6ac0, 0xc10d, 0x6aff, 0xc10d, 0x21, 0 - .dw 0x6b40, 0xc10d, 0x6b7f, 0xc10d, 0x21, 0 - .dw 0x6bc0, 0xc10d, 0x6bff, 0xc10d, 0x21, 0 - .dw 0x6c40, 0xc10d, 0x6c7f, 0xc10d, 0x21, 0 - .dw 0x6cc0, 0xc10d, 0x6cff, 0xc10d, 0x21, 0 - .dw 0x6d40, 0xc10d, 0x6d7f, 0xc10d, 0x21, 0 - .dw 0x6dc0, 0xc10d, 0x6dff, 0xc10d, 0x21, 0 - .dw 0x6e40, 0xc10d, 0x6e7f, 0xc10d, 0x21, 0 - .dw 0x6ec0, 0xc10d, 0x6eff, 0xc10d, 0x21, 0 - .dw 0x6f40, 0xc10d, 0x6f7f, 0xc10d, 0x21, 0 - .dw 0x6fc0, 0xc10d, 0x6fff, 0xc10d, 0x21, 0 - .dw 0x7040, 0xc10d, 0x707f, 0xc10d, 0x21, 0 - .dw 0x70c0, 0xc10d, 0x70ff, 0xc10d, 0x21, 0 - .dw 0x7140, 0xc10d, 0x717f, 0xc10d, 0x21, 0 - .dw 0x71c0, 0xc10d, 0x71ff, 0xc10d, 0x21, 0 - .dw 0x7240, 0xc10d, 0x727f, 0xc10d, 0x21, 0 - .dw 0x72c0, 0xc10d, 0x72ff, 0xc10d, 0x21, 0 - .dw 0x7340, 0xc10d, 0x737f, 0xc10d, 0x21, 0 - .dw 0x73c0, 0xc10d, 0x73ff, 0xc10d, 0x21, 0 - .dw 0x7440, 0xc10d, 0x747f, 0xc10d, 0x21, 0 - .dw 0x74c0, 0xc10d, 0x74ff, 0xc10d, 0x21, 0 - .dw 0x7540, 0xc10d, 0x757f, 0xc10d, 0x21, 0 - .dw 0x75c0, 0xc10d, 0x75ff, 0xc10d, 0x21, 0 - .dw 0x7640, 0xc10d, 0x767f, 0xc10d, 0x21, 0 - .dw 0x76c0, 0xc10d, 0x76ff, 0xc10d, 0x21, 0 - .dw 0x7740, 0xc10d, 0x777f, 0xc10d, 0x21, 0 - .dw 0x77c0, 0xc10d, 0x77ff, 0xc10d, 0x21, 0 - .dw 0x7840, 0xc10d, 0x787f, 0xc10d, 0x21, 0 - .dw 0x78c0, 0xc10d, 0x78ff, 0xc10d, 0x21, 0 - .dw 0x7940, 0xc10d, 0x797f, 0xc10d, 0x21, 0 - .dw 0x79c0, 0xc10d, 0x7fff, 0xc10d, 0x21, 0 - .dw 0x8040, 0xc10d, 0x807f, 0xc10d, 0x21, 0 - .dw 0x80c0, 0xc10d, 0x80ff, 0xc10d, 0x21, 0 - .dw 0x8140, 0xc10d, 0x817f, 0xc10d, 0x21, 0 - .dw 0x81c0, 0xc10d, 0x81ff, 0xc10d, 0x21, 0 - .dw 0x8240, 0xc10d, 0x827f, 0xc10d, 0x21, 0 - .dw 0x82c0, 0xc10d, 0x82ff, 0xc10d, 0x21, 0 - .dw 0x8340, 0xc10d, 0x837f, 0xc10d, 0x21, 0 - .dw 0x83c0, 0xc10d, 0x83ff, 0xc10d, 0x21, 0 - .dw 0x8440, 0xc10d, 0x847f, 0xc10d, 0x21, 0 - .dw 0x84c0, 0xc10d, 0x84ff, 0xc10d, 0x21, 0 - .dw 0x8540, 0xc10d, 0x857f, 0xc10d, 0x21, 0 - .dw 0x85c0, 0xc10d, 0x85ff, 0xc10d, 0x21, 0 - .dw 0x8640, 0xc10d, 0x867f, 0xc10d, 0x21, 0 - .dw 0x86c0, 0xc10d, 0x86ff, 0xc10d, 0x21, 0 - .dw 0x8740, 0xc10d, 0x877f, 0xc10d, 0x21, 0 - .dw 0x87c0, 0xc10d, 0x87ff, 0xc10d, 0x21, 0 - .dw 0x8840, 0xc10d, 0x887f, 0xc10d, 0x21, 0 - .dw 0x88c0, 0xc10d, 0x88ff, 0xc10d, 0x21, 0 - .dw 0x8940, 0xc10d, 0x897f, 0xc10d, 0x21, 0 - .dw 0x89c0, 0xc10d, 0x89ff, 0xc10d, 0x21, 0 - .dw 0x8a40, 0xc10d, 0x8a7f, 0xc10d, 0x21, 0 - .dw 0x8ac0, 0xc10d, 0x8aff, 0xc10d, 0x21, 0 - .dw 0x8b40, 0xc10d, 0x8b7f, 0xc10d, 0x21, 0 - .dw 0x8bc0, 0xc10d, 0x8bff, 0xc10d, 0x21, 0 - .dw 0x8c40, 0xc10d, 0x8c7f, 0xc10d, 0x21, 0 - .dw 0x8cc0, 0xc10d, 0x8cff, 0xc10d, 0x21, 0 - .dw 0x8d40, 0xc10d, 0x8d7f, 0xc10d, 0x21, 0 - .dw 0x8dc0, 0xc10d, 0x8dff, 0xc10d, 0x21, 0 - .dw 0x8e40, 0xc10d, 0x8e7f, 0xc10d, 0x21, 0 - .dw 0x8ec0, 0xc10d, 0x8eff, 0xc10d, 0x21, 0 - .dw 0x8f40, 0xc10d, 0x8f7f, 0xc10d, 0x21, 0 - .dw 0x8fc0, 0xc10d, 0x8fff, 0xc10d, 0x21, 0 - .dw 0x9040, 0xc10d, 0x907f, 0xc10d, 0x21, 0 - .dw 0x90c0, 0xc10d, 0x90ff, 0xc10d, 0x21, 0 - .dw 0x9140, 0xc10d, 0x917f, 0xc10d, 0x21, 0 - .dw 0x91c0, 0xc10d, 0x91ff, 0xc10d, 0x21, 0 - .dw 0x9240, 0xc10d, 0x927f, 0xc10d, 0x21, 0 - .dw 0x92c0, 0xc10d, 0x92ff, 0xc10d, 0x21, 0 - .dw 0x9340, 0xc10d, 0x937f, 0xc10d, 0x21, 0 - .dw 0x93c0, 0xc10d, 0x93ff, 0xc10d, 0x21, 0 - .dw 0x9440, 0xc10d, 0x947f, 0xc10d, 0x21, 0 - .dw 0x94c0, 0xc10d, 0x94ff, 0xc10d, 0x21, 0 - .dw 0x9540, 0xc10d, 0x957f, 0xc10d, 0x21, 0 - .dw 0x95c0, 0xc10d, 0x95ff, 0xc10d, 0x21, 0 - .dw 0x9640, 0xc10d, 0x967f, 0xc10d, 0x21, 0 - .dw 0x96c0, 0xc10d, 0x96ff, 0xc10d, 0x21, 0 - .dw 0x9740, 0xc10d, 0x977f, 0xc10d, 0x21, 0 - .dw 0x97c0, 0xc10d, 0x97ff, 0xc10d, 0x21, 0 - .dw 0x9840, 0xc10d, 0x987f, 0xc10d, 0x21, 0 - .dw 0x98c0, 0xc10d, 0x98ff, 0xc10d, 0x21, 0 - .dw 0x9940, 0xc10d, 0x997f, 0xc10d, 0x21, 0 - .dw 0x99c0, 0xc10d, 0x9fff, 0xc10d, 0x21, 0 - .dw 0xa040, 0xc10d, 0xa07f, 0xc10d, 0x21, 0 - .dw 0xa0c0, 0xc10d, 0xa0ff, 0xc10d, 0x21, 0 - .dw 0xa140, 0xc10d, 0xa17f, 0xc10d, 0x21, 0 - .dw 0xa1c0, 0xc10d, 0xa1ff, 0xc10d, 0x21, 0 - .dw 0xa240, 0xc10d, 0xa27f, 0xc10d, 0x21, 0 - .dw 0xa2c0, 0xc10d, 0xa2ff, 0xc10d, 0x21, 0 - .dw 0xa340, 0xc10d, 0xa37f, 0xc10d, 0x21, 0 - .dw 0xa3c0, 0xc10d, 0xa3ff, 0xc10d, 0x21, 0 - .dw 0xa440, 0xc10d, 0xa47f, 0xc10d, 0x21, 0 - .dw 0xa4c0, 0xc10d, 0xa4ff, 0xc10d, 0x21, 0 - .dw 0xa540, 0xc10d, 0xa57f, 0xc10d, 0x21, 0 - .dw 0xa5c0, 0xc10d, 0xa5ff, 0xc10d, 0x21, 0 - .dw 0xa640, 0xc10d, 0xa67f, 0xc10d, 0x21, 0 - .dw 0xa6c0, 0xc10d, 0xa6ff, 0xc10d, 0x21, 0 - .dw 0xa740, 0xc10d, 0xa77f, 0xc10d, 0x21, 0 - .dw 0xa7c0, 0xc10d, 0xa7ff, 0xc10d, 0x21, 0 - .dw 0xa840, 0xc10d, 0xa87f, 0xc10d, 0x21, 0 - .dw 0xa8c0, 0xc10d, 0xa8ff, 0xc10d, 0x21, 0 - .dw 0xa940, 0xc10d, 0xa97f, 0xc10d, 0x21, 0 - .dw 0xa9c0, 0xc10d, 0xa9ff, 0xc10d, 0x21, 0 - .dw 0xaa40, 0xc10d, 0xaa7f, 0xc10d, 0x21, 0 - .dw 0xaac0, 0xc10d, 0xaaff, 0xc10d, 0x21, 0 - .dw 0xab40, 0xc10d, 0xab7f, 0xc10d, 0x21, 0 - .dw 0xabc0, 0xc10d, 0xabff, 0xc10d, 0x21, 0 - .dw 0xac40, 0xc10d, 0xac7f, 0xc10d, 0x21, 0 - .dw 0xacc0, 0xc10d, 0xacff, 0xc10d, 0x21, 0 - .dw 0xad40, 0xc10d, 0xad7f, 0xc10d, 0x21, 0 - .dw 0xadc0, 0xc10d, 0xadff, 0xc10d, 0x21, 0 - .dw 0xae40, 0xc10d, 0xae7f, 0xc10d, 0x21, 0 - .dw 0xaec0, 0xc10d, 0xaeff, 0xc10d, 0x21, 0 - .dw 0xaf40, 0xc10d, 0xaf7f, 0xc10d, 0x21, 0 - .dw 0xafc0, 0xc10d, 0xafff, 0xc10d, 0x21, 0 - .dw 0xb040, 0xc10d, 0xb07f, 0xc10d, 0x21, 0 - .dw 0xb0c0, 0xc10d, 0xb0ff, 0xc10d, 0x21, 0 - .dw 0xb140, 0xc10d, 0xb17f, 0xc10d, 0x21, 0 - .dw 0xb1c0, 0xc10d, 0xb1ff, 0xc10d, 0x21, 0 - .dw 0xb240, 0xc10d, 0xb27f, 0xc10d, 0x21, 0 - .dw 0xb2c0, 0xc10d, 0xb2ff, 0xc10d, 0x21, 0 - .dw 0xb340, 0xc10d, 0xb37f, 0xc10d, 0x21, 0 - .dw 0xb3c0, 0xc10d, 0xb3ff, 0xc10d, 0x21, 0 - .dw 0xb440, 0xc10d, 0xb47f, 0xc10d, 0x21, 0 - .dw 0xb4c0, 0xc10d, 0xb4ff, 0xc10d, 0x21, 0 - .dw 0xb540, 0xc10d, 0xb57f, 0xc10d, 0x21, 0 - .dw 0xb5c0, 0xc10d, 0xb5ff, 0xc10d, 0x21, 0 - .dw 0xb640, 0xc10d, 0xb67f, 0xc10d, 0x21, 0 - .dw 0xb6c0, 0xc10d, 0xb6ff, 0xc10d, 0x21, 0 - .dw 0xb740, 0xc10d, 0xb77f, 0xc10d, 0x21, 0 - .dw 0xb7c0, 0xc10d, 0xb7ff, 0xc10d, 0x21, 0 - .dw 0xb840, 0xc10d, 0xb87f, 0xc10d, 0x21, 0 - .dw 0xb8c0, 0xc10d, 0xb8ff, 0xc10d, 0x21, 0 - .dw 0xb940, 0xc10d, 0xb97f, 0xc10d, 0x21, 0 - .dw 0xb9c0, 0xc10d, 0xbfff, 0xc10d, 0x21, 0 - .dw 0xc040, 0xc10d, 0xc07f, 0xc10d, 0x21, 0 - .dw 0xc0c0, 0xc10d, 0xc0ff, 0xc10d, 0x21, 0 - .dw 0xc140, 0xc10d, 0xc17f, 0xc10d, 0x21, 0 - .dw 0xc1c0, 0xc10d, 0xc1ff, 0xc10d, 0x21, 0 - .dw 0xc240, 0xc10d, 0xc27f, 0xc10d, 0x21, 0 - .dw 0xc2c0, 0xc10d, 0xc2ff, 0xc10d, 0x21, 0 - .dw 0xc340, 0xc10d, 0xc37f, 0xc10d, 0x21, 0 - .dw 0xc3c0, 0xc10d, 0xc3ff, 0xc10d, 0x21, 0 - .dw 0xc440, 0xc10d, 0xc47f, 0xc10d, 0x21, 0 - .dw 0xc4c0, 0xc10d, 0xc4ff, 0xc10d, 0x21, 0 - .dw 0xc540, 0xc10d, 0xc57f, 0xc10d, 0x21, 0 - .dw 0xc5c0, 0xc10d, 0xc5ff, 0xc10d, 0x21, 0 - .dw 0xc640, 0xc10d, 0xc67f, 0xc10d, 0x21, 0 - .dw 0xc6c0, 0xc10d, 0xc6ff, 0xc10d, 0x21, 0 - .dw 0xc740, 0xc10d, 0xc77f, 0xc10d, 0x21, 0 - .dw 0xc7c0, 0xc10d, 0xc7ff, 0xc10d, 0x21, 0 - .dw 0xc840, 0xc10d, 0xc87f, 0xc10d, 0x21, 0 - .dw 0xc8c0, 0xc10d, 0xc8ff, 0xc10d, 0x21, 0 - .dw 0xc940, 0xc10d, 0xc97f, 0xc10d, 0x21, 0 - .dw 0xc9c0, 0xc10d, 0xc9ff, 0xc10d, 0x21, 0 - .dw 0xca40, 0xc10d, 0xca7f, 0xc10d, 0x21, 0 - .dw 0xcac0, 0xc10d, 0xcaff, 0xc10d, 0x21, 0 - .dw 0xcb40, 0xc10d, 0xcb7f, 0xc10d, 0x21, 0 - .dw 0xcbc0, 0xc10d, 0xcbff, 0xc10d, 0x21, 0 - .dw 0xcc40, 0xc10d, 0xcc7f, 0xc10d, 0x21, 0 - .dw 0xccc0, 0xc10d, 0xccff, 0xc10d, 0x21, 0 - .dw 0xcd40, 0xc10d, 0xcd7f, 0xc10d, 0x21, 0 - .dw 0xcdc0, 0xc10d, 0xcdff, 0xc10d, 0x21, 0 - .dw 0xce40, 0xc10d, 0xce7f, 0xc10d, 0x21, 0 - .dw 0xcec0, 0xc10d, 0xceff, 0xc10d, 0x21, 0 - .dw 0xcf40, 0xc10d, 0xcf7f, 0xc10d, 0x21, 0 - .dw 0xcfc0, 0xc10d, 0xcfff, 0xc10d, 0x21, 0 - .dw 0xd040, 0xc10d, 0xd07f, 0xc10d, 0x21, 0 - .dw 0xd0c0, 0xc10d, 0xd0ff, 0xc10d, 0x21, 0 - .dw 0xd140, 0xc10d, 0xd17f, 0xc10d, 0x21, 0 - .dw 0xd1c0, 0xc10d, 0xd1ff, 0xc10d, 0x21, 0 - .dw 0xd240, 0xc10d, 0xd27f, 0xc10d, 0x21, 0 - .dw 0xd2c0, 0xc10d, 0xd2ff, 0xc10d, 0x21, 0 - .dw 0xd340, 0xc10d, 0xd37f, 0xc10d, 0x21, 0 - .dw 0xd3c0, 0xc10d, 0xd3ff, 0xc10d, 0x21, 0 - .dw 0xd440, 0xc10d, 0xd47f, 0xc10d, 0x21, 0 - .dw 0xd4c0, 0xc10d, 0xd4ff, 0xc10d, 0x21, 0 - .dw 0xd540, 0xc10d, 0xd57f, 0xc10d, 0x21, 0 - .dw 0xd5c0, 0xc10d, 0xd5ff, 0xc10d, 0x21, 0 - .dw 0xd640, 0xc10d, 0xd67f, 0xc10d, 0x21, 0 - .dw 0xd6c0, 0xc10d, 0xd6ff, 0xc10d, 0x21, 0 - .dw 0xd740, 0xc10d, 0xd77f, 0xc10d, 0x21, 0 - .dw 0xd7c0, 0xc10d, 0xd7ff, 0xc10d, 0x21, 0 - .dw 0xd840, 0xc10d, 0xd87f, 0xc10d, 0x21, 0 - .dw 0xd8c0, 0xc10d, 0xd8ff, 0xc10d, 0x21, 0 - .dw 0xd940, 0xc10d, 0xd97f, 0xc10d, 0x21, 0 - .dw 0xd9c0, 0xc10d, 0xdfff, 0xc10d, 0x21, 0 - .dw 0xe040, 0xc10d, 0xe07f, 0xc10d, 0x21, 0 - .dw 0xe0c0, 0xc10d, 0xe0ff, 0xc10d, 0x21, 0 - .dw 0xe140, 0xc10d, 0xe17f, 0xc10d, 0x21, 0 - .dw 0xe1c0, 0xc10d, 0xe1ff, 0xc10d, 0x21, 0 - .dw 0xe240, 0xc10d, 0xe27f, 0xc10d, 0x21, 0 - .dw 0xe2c0, 0xc10d, 0xe2ff, 0xc10d, 0x21, 0 - .dw 0xe340, 0xc10d, 0xe37f, 0xc10d, 0x21, 0 - .dw 0xe3c0, 0xc10d, 0xe3ff, 0xc10d, 0x21, 0 - .dw 0xe440, 0xc10d, 0xe47f, 0xc10d, 0x21, 0 - .dw 0xe4c0, 0xc10d, 0xe4ff, 0xc10d, 0x21, 0 - .dw 0xe540, 0xc10d, 0xe57f, 0xc10d, 0x21, 0 - .dw 0xe5c0, 0xc10d, 0xe5ff, 0xc10d, 0x21, 0 - .dw 0xe640, 0xc10d, 0xe67f, 0xc10d, 0x21, 0 - .dw 0xe6c0, 0xc10d, 0xe6ff, 0xc10d, 0x21, 0 - .dw 0xe740, 0xc10d, 0xe77f, 0xc10d, 0x21, 0 - .dw 0xe7c0, 0xc10d, 0xe7ff, 0xc10d, 0x21, 0 - .dw 0xe840, 0xc10d, 0xe87f, 0xc10d, 0x21, 0 - .dw 0xe8c0, 0xc10d, 0xe8ff, 0xc10d, 0x21, 0 - .dw 0xe940, 0xc10d, 0xe97f, 0xc10d, 0x21, 0 - .dw 0xe9c0, 0xc10d, 0xe9ff, 0xc10d, 0x21, 0 - .dw 0xea40, 0xc10d, 0xea7f, 0xc10d, 0x21, 0 - .dw 0xeac0, 0xc10d, 0xeaff, 0xc10d, 0x21, 0 - .dw 0xeb40, 0xc10d, 0xeb7f, 0xc10d, 0x21, 0 - .dw 0xebc0, 0xc10d, 0xebff, 0xc10d, 0x21, 0 - .dw 0xec40, 0xc10d, 0xec7f, 0xc10d, 0x21, 0 - .dw 0xecc0, 0xc10d, 0xecff, 0xc10d, 0x21, 0 - .dw 0xed40, 0xc10d, 0xed7f, 0xc10d, 0x21, 0 - .dw 0xedc0, 0xc10d, 0xedff, 0xc10d, 0x21, 0 - .dw 0xee40, 0xc10d, 0xee7f, 0xc10d, 0x21, 0 - .dw 0xeec0, 0xc10d, 0xeeff, 0xc10d, 0x21, 0 - .dw 0xef40, 0xc10d, 0xef7f, 0xc10d, 0x21, 0 - .dw 0xefc0, 0xc10d, 0xefff, 0xc10d, 0x21, 0 - .dw 0xf040, 0xc10d, 0xf07f, 0xc10d, 0x21, 0 - .dw 0xf0c0, 0xc10d, 0xf0ff, 0xc10d, 0x21, 0 - .dw 0xf140, 0xc10d, 0xf17f, 0xc10d, 0x21, 0 - .dw 0xf1c0, 0xc10d, 0xf1ff, 0xc10d, 0x21, 0 - .dw 0xf240, 0xc10d, 0xf27f, 0xc10d, 0x21, 0 - .dw 0xf2c0, 0xc10d, 0xf2ff, 0xc10d, 0x21, 0 - .dw 0xf340, 0xc10d, 0xf37f, 0xc10d, 0x21, 0 - .dw 0xf3c0, 0xc10d, 0xf3ff, 0xc10d, 0x21, 0 - .dw 0xf440, 0xc10d, 0xf47f, 0xc10d, 0x21, 0 - .dw 0xf4c0, 0xc10d, 0xf4ff, 0xc10d, 0x21, 0 - .dw 0xf540, 0xc10d, 0xf57f, 0xc10d, 0x21, 0 - .dw 0xf5c0, 0xc10d, 0xf5ff, 0xc10d, 0x21, 0 - .dw 0xf640, 0xc10d, 0xf67f, 0xc10d, 0x21, 0 - .dw 0xf6c0, 0xc10d, 0xf6ff, 0xc10d, 0x21, 0 - .dw 0xf740, 0xc10d, 0xf77f, 0xc10d, 0x21, 0 - .dw 0xf7c0, 0xc10d, 0xf7ff, 0xc10d, 0x21, 0 - .dw 0xf840, 0xc10d, 0xf87f, 0xc10d, 0x21, 0 - .dw 0xf8c0, 0xc10d, 0xf8ff, 0xc10d, 0x21, 0 - .dw 0xf940, 0xc10d, 0xf97f, 0xc10d, 0x21, 0 - .dw 0xf9c0, 0xc10d, 0xffff, 0xc10d, 0x21, 0 - .dw 0x0040, 0xc10e, 0x007f, 0xc10e, 0x21, 0 - .dw 0x00c0, 0xc10e, 0x00ff, 0xc10e, 0x21, 0 - .dw 0x0140, 0xc10e, 0x017f, 0xc10e, 0x21, 0 - .dw 0x01c0, 0xc10e, 0x01ff, 0xc10e, 0x21, 0 - .dw 0x0240, 0xc10e, 0x027f, 0xc10e, 0x21, 0 - .dw 0x02c0, 0xc10e, 0x02ff, 0xc10e, 0x21, 0 - .dw 0x0340, 0xc10e, 0x037f, 0xc10e, 0x21, 0 - .dw 0x03c0, 0xc10e, 0x03ff, 0xc10e, 0x21, 0 - .dw 0x0440, 0xc10e, 0x047f, 0xc10e, 0x21, 0 - .dw 0x04c0, 0xc10e, 0x04ff, 0xc10e, 0x21, 0 - .dw 0x0540, 0xc10e, 0x057f, 0xc10e, 0x21, 0 - .dw 0x05c0, 0xc10e, 0x05ff, 0xc10e, 0x21, 0 - .dw 0x0640, 0xc10e, 0x067f, 0xc10e, 0x21, 0 - .dw 0x06c0, 0xc10e, 0x06ff, 0xc10e, 0x21, 0 - .dw 0x0740, 0xc10e, 0x077f, 0xc10e, 0x21, 0 - .dw 0x07c0, 0xc10e, 0x07ff, 0xc10e, 0x21, 0 - .dw 0x0840, 0xc10e, 0x087f, 0xc10e, 0x21, 0 - .dw 0x08c0, 0xc10e, 0x08ff, 0xc10e, 0x21, 0 - .dw 0x0940, 0xc10e, 0x097f, 0xc10e, 0x21, 0 - .dw 0x09c0, 0xc10e, 0x09ff, 0xc10e, 0x21, 0 - .dw 0x0a40, 0xc10e, 0x0a7f, 0xc10e, 0x21, 0 - .dw 0x0ac0, 0xc10e, 0x0aff, 0xc10e, 0x21, 0 - .dw 0x0b40, 0xc10e, 0x0b7f, 0xc10e, 0x21, 0 - .dw 0x0bc0, 0xc10e, 0x0bff, 0xc10e, 0x21, 0 - .dw 0x0c40, 0xc10e, 0x0c7f, 0xc10e, 0x21, 0 - .dw 0x0cc0, 0xc10e, 0x0cff, 0xc10e, 0x21, 0 - .dw 0x0d40, 0xc10e, 0x0d7f, 0xc10e, 0x21, 0 - .dw 0x0dc0, 0xc10e, 0x0dff, 0xc10e, 0x21, 0 - .dw 0x0e40, 0xc10e, 0x0e7f, 0xc10e, 0x21, 0 - .dw 0x0ec0, 0xc10e, 0x0eff, 0xc10e, 0x21, 0 - .dw 0x0f40, 0xc10e, 0x0f7f, 0xc10e, 0x21, 0 - .dw 0x0fc0, 0xc10e, 0x0fff, 0xc10e, 0x21, 0 - .dw 0x1040, 0xc10e, 0x107f, 0xc10e, 0x21, 0 - .dw 0x10c0, 0xc10e, 0x10ff, 0xc10e, 0x21, 0 - .dw 0x1140, 0xc10e, 0x117f, 0xc10e, 0x21, 0 - .dw 0x11c0, 0xc10e, 0x11ff, 0xc10e, 0x21, 0 - .dw 0x1240, 0xc10e, 0x127f, 0xc10e, 0x21, 0 - .dw 0x12c0, 0xc10e, 0x12ff, 0xc10e, 0x21, 0 - .dw 0x1340, 0xc10e, 0x137f, 0xc10e, 0x21, 0 - .dw 0x13c0, 0xc10e, 0x13ff, 0xc10e, 0x21, 0 - .dw 0x1440, 0xc10e, 0x147f, 0xc10e, 0x21, 0 - .dw 0x14c0, 0xc10e, 0x14ff, 0xc10e, 0x21, 0 - .dw 0x1540, 0xc10e, 0x157f, 0xc10e, 0x21, 0 - .dw 0x15c0, 0xc10e, 0x15ff, 0xc10e, 0x21, 0 - .dw 0x1640, 0xc10e, 0x167f, 0xc10e, 0x21, 0 - .dw 0x16c0, 0xc10e, 0x16ff, 0xc10e, 0x21, 0 - .dw 0x1740, 0xc10e, 0x177f, 0xc10e, 0x21, 0 - .dw 0x17c0, 0xc10e, 0x17ff, 0xc10e, 0x21, 0 - .dw 0x1840, 0xc10e, 0x187f, 0xc10e, 0x21, 0 - .dw 0x18c0, 0xc10e, 0x18ff, 0xc10e, 0x21, 0 - .dw 0x1940, 0xc10e, 0x197f, 0xc10e, 0x21, 0 - .dw 0x19c0, 0xc10e, 0x1fff, 0xc10e, 0x21, 0 - .dw 0x2040, 0xc10e, 0x207f, 0xc10e, 0x21, 0 - .dw 0x20c0, 0xc10e, 0x20ff, 0xc10e, 0x21, 0 - .dw 0x2140, 0xc10e, 0x217f, 0xc10e, 0x21, 0 - .dw 0x21c0, 0xc10e, 0x21ff, 0xc10e, 0x21, 0 - .dw 0x2240, 0xc10e, 0x227f, 0xc10e, 0x21, 0 - .dw 0x22c0, 0xc10e, 0x22ff, 0xc10e, 0x21, 0 - .dw 0x2340, 0xc10e, 0x237f, 0xc10e, 0x21, 0 - .dw 0x23c0, 0xc10e, 0x23ff, 0xc10e, 0x21, 0 - .dw 0x2440, 0xc10e, 0x247f, 0xc10e, 0x21, 0 - .dw 0x24c0, 0xc10e, 0x24ff, 0xc10e, 0x21, 0 - .dw 0x2540, 0xc10e, 0x257f, 0xc10e, 0x21, 0 - .dw 0x25c0, 0xc10e, 0x25ff, 0xc10e, 0x21, 0 - .dw 0x2640, 0xc10e, 0x267f, 0xc10e, 0x21, 0 - .dw 0x26c0, 0xc10e, 0x26ff, 0xc10e, 0x21, 0 - .dw 0x2740, 0xc10e, 0x277f, 0xc10e, 0x21, 0 - .dw 0x27c0, 0xc10e, 0x27ff, 0xc10e, 0x21, 0 - .dw 0x2840, 0xc10e, 0x287f, 0xc10e, 0x21, 0 - .dw 0x28c0, 0xc10e, 0x28ff, 0xc10e, 0x21, 0 - .dw 0x2940, 0xc10e, 0x297f, 0xc10e, 0x21, 0 - .dw 0x29c0, 0xc10e, 0x29ff, 0xc10e, 0x21, 0 - .dw 0x2a40, 0xc10e, 0x2a7f, 0xc10e, 0x21, 0 - .dw 0x2ac0, 0xc10e, 0x2aff, 0xc10e, 0x21, 0 - .dw 0x2b40, 0xc10e, 0x2b7f, 0xc10e, 0x21, 0 - .dw 0x2bc0, 0xc10e, 0x2bff, 0xc10e, 0x21, 0 - .dw 0x2c40, 0xc10e, 0x2c7f, 0xc10e, 0x21, 0 - .dw 0x2cc0, 0xc10e, 0x2cff, 0xc10e, 0x21, 0 - .dw 0x2d40, 0xc10e, 0x2d7f, 0xc10e, 0x21, 0 - .dw 0x2dc0, 0xc10e, 0x2dff, 0xc10e, 0x21, 0 - .dw 0x2e40, 0xc10e, 0x2e7f, 0xc10e, 0x21, 0 - .dw 0x2ec0, 0xc10e, 0x2eff, 0xc10e, 0x21, 0 - .dw 0x2f40, 0xc10e, 0x2f7f, 0xc10e, 0x21, 0 - .dw 0x2fc0, 0xc10e, 0x2fff, 0xc10e, 0x21, 0 - .dw 0x3040, 0xc10e, 0x307f, 0xc10e, 0x21, 0 - .dw 0x30c0, 0xc10e, 0x30ff, 0xc10e, 0x21, 0 - .dw 0x3140, 0xc10e, 0x317f, 0xc10e, 0x21, 0 - .dw 0x31c0, 0xc10e, 0x31ff, 0xc10e, 0x21, 0 - .dw 0x3240, 0xc10e, 0x327f, 0xc10e, 0x21, 0 - .dw 0x32c0, 0xc10e, 0x32ff, 0xc10e, 0x21, 0 - .dw 0x3340, 0xc10e, 0x337f, 0xc10e, 0x21, 0 - .dw 0x33c0, 0xc10e, 0x33ff, 0xc10e, 0x21, 0 - .dw 0x3440, 0xc10e, 0x347f, 0xc10e, 0x21, 0 - .dw 0x34c0, 0xc10e, 0x34ff, 0xc10e, 0x21, 0 - .dw 0x3540, 0xc10e, 0x357f, 0xc10e, 0x21, 0 - .dw 0x35c0, 0xc10e, 0x35ff, 0xc10e, 0x21, 0 - .dw 0x3640, 0xc10e, 0x367f, 0xc10e, 0x21, 0 - .dw 0x36c0, 0xc10e, 0x36ff, 0xc10e, 0x21, 0 - .dw 0x3740, 0xc10e, 0x377f, 0xc10e, 0x21, 0 - .dw 0x37c0, 0xc10e, 0x37ff, 0xc10e, 0x21, 0 - .dw 0x3840, 0xc10e, 0x387f, 0xc10e, 0x21, 0 - .dw 0x38c0, 0xc10e, 0x38ff, 0xc10e, 0x21, 0 - .dw 0x3940, 0xc10e, 0x397f, 0xc10e, 0x21, 0 - .dw 0x39c0, 0xc10e, 0x3fff, 0xc10e, 0x21, 0 - .dw 0x4040, 0xc10e, 0x407f, 0xc10e, 0x21, 0 - .dw 0x40c0, 0xc10e, 0x40ff, 0xc10e, 0x21, 0 - .dw 0x4140, 0xc10e, 0x417f, 0xc10e, 0x21, 0 - .dw 0x41c0, 0xc10e, 0x41ff, 0xc10e, 0x21, 0 - .dw 0x4240, 0xc10e, 0x427f, 0xc10e, 0x21, 0 - .dw 0x42c0, 0xc10e, 0x42ff, 0xc10e, 0x21, 0 - .dw 0x4340, 0xc10e, 0x437f, 0xc10e, 0x21, 0 - .dw 0x43c0, 0xc10e, 0x43ff, 0xc10e, 0x21, 0 - .dw 0x4440, 0xc10e, 0x447f, 0xc10e, 0x21, 0 - .dw 0x44c0, 0xc10e, 0x44ff, 0xc10e, 0x21, 0 - .dw 0x4540, 0xc10e, 0x457f, 0xc10e, 0x21, 0 - .dw 0x45c0, 0xc10e, 0x45ff, 0xc10e, 0x21, 0 - .dw 0x4640, 0xc10e, 0x467f, 0xc10e, 0x21, 0 - .dw 0x46c0, 0xc10e, 0x46ff, 0xc10e, 0x21, 0 - .dw 0x4740, 0xc10e, 0x477f, 0xc10e, 0x21, 0 - .dw 0x47c0, 0xc10e, 0x47ff, 0xc10e, 0x21, 0 - .dw 0x4840, 0xc10e, 0x487f, 0xc10e, 0x21, 0 - .dw 0x48c0, 0xc10e, 0x48ff, 0xc10e, 0x21, 0 - .dw 0x4940, 0xc10e, 0x497f, 0xc10e, 0x21, 0 - .dw 0x49c0, 0xc10e, 0x49ff, 0xc10e, 0x21, 0 - .dw 0x4a40, 0xc10e, 0x4a7f, 0xc10e, 0x21, 0 - .dw 0x4ac0, 0xc10e, 0x4aff, 0xc10e, 0x21, 0 - .dw 0x4b40, 0xc10e, 0x4b7f, 0xc10e, 0x21, 0 - .dw 0x4bc0, 0xc10e, 0x4bff, 0xc10e, 0x21, 0 - .dw 0x4c40, 0xc10e, 0x4c7f, 0xc10e, 0x21, 0 - .dw 0x4cc0, 0xc10e, 0x4cff, 0xc10e, 0x21, 0 - .dw 0x4d40, 0xc10e, 0x4d7f, 0xc10e, 0x21, 0 - .dw 0x4dc0, 0xc10e, 0x4dff, 0xc10e, 0x21, 0 - .dw 0x4e40, 0xc10e, 0x4e7f, 0xc10e, 0x21, 0 - .dw 0x4ec0, 0xc10e, 0x4eff, 0xc10e, 0x21, 0 - .dw 0x4f40, 0xc10e, 0x4f7f, 0xc10e, 0x21, 0 - .dw 0x4fc0, 0xc10e, 0x4fff, 0xc10e, 0x21, 0 - .dw 0x5040, 0xc10e, 0x507f, 0xc10e, 0x21, 0 - .dw 0x50c0, 0xc10e, 0x50ff, 0xc10e, 0x21, 0 - .dw 0x5140, 0xc10e, 0x517f, 0xc10e, 0x21, 0 - .dw 0x51c0, 0xc10e, 0x51ff, 0xc10e, 0x21, 0 - .dw 0x5240, 0xc10e, 0x527f, 0xc10e, 0x21, 0 - .dw 0x52c0, 0xc10e, 0x52ff, 0xc10e, 0x21, 0 - .dw 0x5340, 0xc10e, 0x537f, 0xc10e, 0x21, 0 - .dw 0x53c0, 0xc10e, 0x53ff, 0xc10e, 0x21, 0 - .dw 0x5440, 0xc10e, 0x547f, 0xc10e, 0x21, 0 - .dw 0x54c0, 0xc10e, 0x54ff, 0xc10e, 0x21, 0 - .dw 0x5540, 0xc10e, 0x557f, 0xc10e, 0x21, 0 - .dw 0x55c0, 0xc10e, 0x55ff, 0xc10e, 0x21, 0 - .dw 0x5640, 0xc10e, 0x567f, 0xc10e, 0x21, 0 - .dw 0x56c0, 0xc10e, 0x56ff, 0xc10e, 0x21, 0 - .dw 0x5740, 0xc10e, 0x577f, 0xc10e, 0x21, 0 - .dw 0x57c0, 0xc10e, 0x57ff, 0xc10e, 0x21, 0 - .dw 0x5840, 0xc10e, 0x587f, 0xc10e, 0x21, 0 - .dw 0x58c0, 0xc10e, 0x58ff, 0xc10e, 0x21, 0 - .dw 0x5940, 0xc10e, 0x597f, 0xc10e, 0x21, 0 - .dw 0x59c0, 0xc10e, 0x5fff, 0xc10e, 0x21, 0 - .dw 0x6040, 0xc10e, 0x607f, 0xc10e, 0x21, 0 - .dw 0x60c0, 0xc10e, 0x60ff, 0xc10e, 0x21, 0 - .dw 0x6140, 0xc10e, 0x617f, 0xc10e, 0x21, 0 - .dw 0x61c0, 0xc10e, 0x61ff, 0xc10e, 0x21, 0 - .dw 0x6240, 0xc10e, 0x627f, 0xc10e, 0x21, 0 - .dw 0x62c0, 0xc10e, 0x62ff, 0xc10e, 0x21, 0 - .dw 0x6340, 0xc10e, 0x637f, 0xc10e, 0x21, 0 - .dw 0x63c0, 0xc10e, 0x63ff, 0xc10e, 0x21, 0 - .dw 0x6440, 0xc10e, 0x647f, 0xc10e, 0x21, 0 - .dw 0x64c0, 0xc10e, 0x64ff, 0xc10e, 0x21, 0 - .dw 0x6540, 0xc10e, 0x657f, 0xc10e, 0x21, 0 - .dw 0x65c0, 0xc10e, 0x65ff, 0xc10e, 0x21, 0 - .dw 0x6640, 0xc10e, 0x667f, 0xc10e, 0x21, 0 - .dw 0x66c0, 0xc10e, 0x66ff, 0xc10e, 0x21, 0 - .dw 0x6740, 0xc10e, 0x677f, 0xc10e, 0x21, 0 - .dw 0x67c0, 0xc10e, 0x67ff, 0xc10e, 0x21, 0 - .dw 0x6840, 0xc10e, 0x687f, 0xc10e, 0x21, 0 - .dw 0x68c0, 0xc10e, 0x68ff, 0xc10e, 0x21, 0 - .dw 0x6940, 0xc10e, 0x697f, 0xc10e, 0x21, 0 - .dw 0x69c0, 0xc10e, 0x69ff, 0xc10e, 0x21, 0 - .dw 0x6a40, 0xc10e, 0x6a7f, 0xc10e, 0x21, 0 - .dw 0x6ac0, 0xc10e, 0x6aff, 0xc10e, 0x21, 0 - .dw 0x6b40, 0xc10e, 0x6b7f, 0xc10e, 0x21, 0 - .dw 0x6bc0, 0xc10e, 0x6bff, 0xc10e, 0x21, 0 - .dw 0x6c40, 0xc10e, 0x6c7f, 0xc10e, 0x21, 0 - .dw 0x6cc0, 0xc10e, 0x6cff, 0xc10e, 0x21, 0 - .dw 0x6d40, 0xc10e, 0x6d7f, 0xc10e, 0x21, 0 - .dw 0x6dc0, 0xc10e, 0x6dff, 0xc10e, 0x21, 0 - .dw 0x6e40, 0xc10e, 0x6e7f, 0xc10e, 0x21, 0 - .dw 0x6ec0, 0xc10e, 0x6eff, 0xc10e, 0x21, 0 - .dw 0x6f40, 0xc10e, 0x6f7f, 0xc10e, 0x21, 0 - .dw 0x6fc0, 0xc10e, 0x6fff, 0xc10e, 0x21, 0 - .dw 0x7040, 0xc10e, 0x707f, 0xc10e, 0x21, 0 - .dw 0x70c0, 0xc10e, 0x70ff, 0xc10e, 0x21, 0 - .dw 0x7140, 0xc10e, 0x717f, 0xc10e, 0x21, 0 - .dw 0x71c0, 0xc10e, 0x71ff, 0xc10e, 0x21, 0 - .dw 0x7240, 0xc10e, 0x727f, 0xc10e, 0x21, 0 - .dw 0x72c0, 0xc10e, 0x72ff, 0xc10e, 0x21, 0 - .dw 0x7340, 0xc10e, 0x737f, 0xc10e, 0x21, 0 - .dw 0x73c0, 0xc10e, 0x73ff, 0xc10e, 0x21, 0 - .dw 0x7440, 0xc10e, 0x747f, 0xc10e, 0x21, 0 - .dw 0x74c0, 0xc10e, 0x74ff, 0xc10e, 0x21, 0 - .dw 0x7540, 0xc10e, 0x757f, 0xc10e, 0x21, 0 - .dw 0x75c0, 0xc10e, 0x75ff, 0xc10e, 0x21, 0 - .dw 0x7640, 0xc10e, 0x767f, 0xc10e, 0x21, 0 - .dw 0x76c0, 0xc10e, 0x76ff, 0xc10e, 0x21, 0 - .dw 0x7740, 0xc10e, 0x777f, 0xc10e, 0x21, 0 - .dw 0x77c0, 0xc10e, 0x77ff, 0xc10e, 0x21, 0 - .dw 0x7840, 0xc10e, 0x787f, 0xc10e, 0x21, 0 - .dw 0x78c0, 0xc10e, 0x78ff, 0xc10e, 0x21, 0 - .dw 0x7940, 0xc10e, 0x797f, 0xc10e, 0x21, 0 - .dw 0x79c0, 0xc10e, 0x7fff, 0xc10e, 0x21, 0 - .dw 0x8040, 0xc10e, 0x807f, 0xc10e, 0x21, 0 - .dw 0x80c0, 0xc10e, 0x80ff, 0xc10e, 0x21, 0 - .dw 0x8140, 0xc10e, 0x817f, 0xc10e, 0x21, 0 - .dw 0x81c0, 0xc10e, 0x81ff, 0xc10e, 0x21, 0 - .dw 0x8240, 0xc10e, 0x827f, 0xc10e, 0x21, 0 - .dw 0x82c0, 0xc10e, 0x82ff, 0xc10e, 0x21, 0 - .dw 0x8340, 0xc10e, 0x837f, 0xc10e, 0x21, 0 - .dw 0x83c0, 0xc10e, 0x83ff, 0xc10e, 0x21, 0 - .dw 0x8440, 0xc10e, 0x847f, 0xc10e, 0x21, 0 - .dw 0x84c0, 0xc10e, 0x84ff, 0xc10e, 0x21, 0 - .dw 0x8540, 0xc10e, 0x857f, 0xc10e, 0x21, 0 - .dw 0x85c0, 0xc10e, 0x85ff, 0xc10e, 0x21, 0 - .dw 0x8640, 0xc10e, 0x867f, 0xc10e, 0x21, 0 - .dw 0x86c0, 0xc10e, 0x86ff, 0xc10e, 0x21, 0 - .dw 0x8740, 0xc10e, 0x877f, 0xc10e, 0x21, 0 - .dw 0x87c0, 0xc10e, 0x87ff, 0xc10e, 0x21, 0 - .dw 0x8840, 0xc10e, 0x887f, 0xc10e, 0x21, 0 - .dw 0x88c0, 0xc10e, 0x88ff, 0xc10e, 0x21, 0 - .dw 0x8940, 0xc10e, 0x897f, 0xc10e, 0x21, 0 - .dw 0x89c0, 0xc10e, 0x89ff, 0xc10e, 0x21, 0 - .dw 0x8a40, 0xc10e, 0x8a7f, 0xc10e, 0x21, 0 - .dw 0x8ac0, 0xc10e, 0x8aff, 0xc10e, 0x21, 0 - .dw 0x8b40, 0xc10e, 0x8b7f, 0xc10e, 0x21, 0 - .dw 0x8bc0, 0xc10e, 0x8bff, 0xc10e, 0x21, 0 - .dw 0x8c40, 0xc10e, 0x8c7f, 0xc10e, 0x21, 0 - .dw 0x8cc0, 0xc10e, 0x8cff, 0xc10e, 0x21, 0 - .dw 0x8d40, 0xc10e, 0x8d7f, 0xc10e, 0x21, 0 - .dw 0x8dc0, 0xc10e, 0x8dff, 0xc10e, 0x21, 0 - .dw 0x8e40, 0xc10e, 0x8e7f, 0xc10e, 0x21, 0 - .dw 0x8ec0, 0xc10e, 0x8eff, 0xc10e, 0x21, 0 - .dw 0x8f40, 0xc10e, 0x8f7f, 0xc10e, 0x21, 0 - .dw 0x8fc0, 0xc10e, 0x8fff, 0xc10e, 0x21, 0 - .dw 0x9040, 0xc10e, 0x907f, 0xc10e, 0x21, 0 - .dw 0x90c0, 0xc10e, 0x90ff, 0xc10e, 0x21, 0 - .dw 0x9140, 0xc10e, 0x917f, 0xc10e, 0x21, 0 - .dw 0x91c0, 0xc10e, 0x91ff, 0xc10e, 0x21, 0 - .dw 0x9240, 0xc10e, 0x927f, 0xc10e, 0x21, 0 - .dw 0x92c0, 0xc10e, 0x92ff, 0xc10e, 0x21, 0 - .dw 0x9340, 0xc10e, 0x937f, 0xc10e, 0x21, 0 - .dw 0x93c0, 0xc10e, 0x93ff, 0xc10e, 0x21, 0 - .dw 0x9440, 0xc10e, 0x947f, 0xc10e, 0x21, 0 - .dw 0x94c0, 0xc10e, 0x94ff, 0xc10e, 0x21, 0 - .dw 0x9540, 0xc10e, 0x957f, 0xc10e, 0x21, 0 - .dw 0x95c0, 0xc10e, 0x95ff, 0xc10e, 0x21, 0 - .dw 0x9640, 0xc10e, 0x967f, 0xc10e, 0x21, 0 - .dw 0x96c0, 0xc10e, 0x96ff, 0xc10e, 0x21, 0 - .dw 0x9740, 0xc10e, 0x977f, 0xc10e, 0x21, 0 - .dw 0x97c0, 0xc10e, 0x97ff, 0xc10e, 0x21, 0 - .dw 0x9840, 0xc10e, 0x987f, 0xc10e, 0x21, 0 - .dw 0x98c0, 0xc10e, 0x98ff, 0xc10e, 0x21, 0 - .dw 0x9940, 0xc10e, 0x997f, 0xc10e, 0x21, 0 - .dw 0x99c0, 0xc10e, 0x9fff, 0xc10e, 0x21, 0 - .dw 0xa040, 0xc10e, 0xa07f, 0xc10e, 0x21, 0 - .dw 0xa0c0, 0xc10e, 0xa0ff, 0xc10e, 0x21, 0 - .dw 0xa140, 0xc10e, 0xa17f, 0xc10e, 0x21, 0 - .dw 0xa1c0, 0xc10e, 0xa1ff, 0xc10e, 0x21, 0 - .dw 0xa240, 0xc10e, 0xa27f, 0xc10e, 0x21, 0 - .dw 0xa2c0, 0xc10e, 0xa2ff, 0xc10e, 0x21, 0 - .dw 0xa340, 0xc10e, 0xa37f, 0xc10e, 0x21, 0 - .dw 0xa3c0, 0xc10e, 0xa3ff, 0xc10e, 0x21, 0 - .dw 0xa440, 0xc10e, 0xa47f, 0xc10e, 0x21, 0 - .dw 0xa4c0, 0xc10e, 0xa4ff, 0xc10e, 0x21, 0 - .dw 0xa540, 0xc10e, 0xa57f, 0xc10e, 0x21, 0 - .dw 0xa5c0, 0xc10e, 0xa5ff, 0xc10e, 0x21, 0 - .dw 0xa640, 0xc10e, 0xa67f, 0xc10e, 0x21, 0 - .dw 0xa6c0, 0xc10e, 0xa6ff, 0xc10e, 0x21, 0 - .dw 0xa740, 0xc10e, 0xa77f, 0xc10e, 0x21, 0 - .dw 0xa7c0, 0xc10e, 0xa7ff, 0xc10e, 0x21, 0 - .dw 0xa840, 0xc10e, 0xa87f, 0xc10e, 0x21, 0 - .dw 0xa8c0, 0xc10e, 0xa8ff, 0xc10e, 0x21, 0 - .dw 0xa940, 0xc10e, 0xa97f, 0xc10e, 0x21, 0 - .dw 0xa9c0, 0xc10e, 0xa9ff, 0xc10e, 0x21, 0 - .dw 0xaa40, 0xc10e, 0xaa7f, 0xc10e, 0x21, 0 - .dw 0xaac0, 0xc10e, 0xaaff, 0xc10e, 0x21, 0 - .dw 0xab40, 0xc10e, 0xab7f, 0xc10e, 0x21, 0 - .dw 0xabc0, 0xc10e, 0xabff, 0xc10e, 0x21, 0 - .dw 0xac40, 0xc10e, 0xac7f, 0xc10e, 0x21, 0 - .dw 0xacc0, 0xc10e, 0xacff, 0xc10e, 0x21, 0 - .dw 0xad40, 0xc10e, 0xad7f, 0xc10e, 0x21, 0 - .dw 0xadc0, 0xc10e, 0xadff, 0xc10e, 0x21, 0 - .dw 0xae40, 0xc10e, 0xae7f, 0xc10e, 0x21, 0 - .dw 0xaec0, 0xc10e, 0xaeff, 0xc10e, 0x21, 0 - .dw 0xaf40, 0xc10e, 0xaf7f, 0xc10e, 0x21, 0 - .dw 0xafc0, 0xc10e, 0xafff, 0xc10e, 0x21, 0 - .dw 0xb040, 0xc10e, 0xb07f, 0xc10e, 0x21, 0 - .dw 0xb0c0, 0xc10e, 0xb0ff, 0xc10e, 0x21, 0 - .dw 0xb140, 0xc10e, 0xb17f, 0xc10e, 0x21, 0 - .dw 0xb1c0, 0xc10e, 0xb1ff, 0xc10e, 0x21, 0 - .dw 0xb240, 0xc10e, 0xb27f, 0xc10e, 0x21, 0 - .dw 0xb2c0, 0xc10e, 0xb2ff, 0xc10e, 0x21, 0 - .dw 0xb340, 0xc10e, 0xb37f, 0xc10e, 0x21, 0 - .dw 0xb3c0, 0xc10e, 0xb3ff, 0xc10e, 0x21, 0 - .dw 0xb440, 0xc10e, 0xb47f, 0xc10e, 0x21, 0 - .dw 0xb4c0, 0xc10e, 0xb4ff, 0xc10e, 0x21, 0 - .dw 0xb540, 0xc10e, 0xb57f, 0xc10e, 0x21, 0 - .dw 0xb5c0, 0xc10e, 0xb5ff, 0xc10e, 0x21, 0 - .dw 0xb640, 0xc10e, 0xb67f, 0xc10e, 0x21, 0 - .dw 0xb6c0, 0xc10e, 0xb6ff, 0xc10e, 0x21, 0 - .dw 0xb740, 0xc10e, 0xb77f, 0xc10e, 0x21, 0 - .dw 0xb7c0, 0xc10e, 0xb7ff, 0xc10e, 0x21, 0 - .dw 0xb840, 0xc10e, 0xb87f, 0xc10e, 0x21, 0 - .dw 0xb8c0, 0xc10e, 0xb8ff, 0xc10e, 0x21, 0 - .dw 0xb940, 0xc10e, 0xb97f, 0xc10e, 0x21, 0 - .dw 0xb9c0, 0xc10e, 0xbfff, 0xc10e, 0x21, 0 - .dw 0xc040, 0xc10e, 0xc07f, 0xc10e, 0x21, 0 - .dw 0xc0c0, 0xc10e, 0xc0ff, 0xc10e, 0x21, 0 - .dw 0xc140, 0xc10e, 0xc17f, 0xc10e, 0x21, 0 - .dw 0xc1c0, 0xc10e, 0xc1ff, 0xc10e, 0x21, 0 - .dw 0xc240, 0xc10e, 0xc27f, 0xc10e, 0x21, 0 - .dw 0xc2c0, 0xc10e, 0xc2ff, 0xc10e, 0x21, 0 - .dw 0xc340, 0xc10e, 0xc37f, 0xc10e, 0x21, 0 - .dw 0xc3c0, 0xc10e, 0xc3ff, 0xc10e, 0x21, 0 - .dw 0xc440, 0xc10e, 0xc47f, 0xc10e, 0x21, 0 - .dw 0xc4c0, 0xc10e, 0xc4ff, 0xc10e, 0x21, 0 - .dw 0xc540, 0xc10e, 0xc57f, 0xc10e, 0x21, 0 - .dw 0xc5c0, 0xc10e, 0xc5ff, 0xc10e, 0x21, 0 - .dw 0xc640, 0xc10e, 0xc67f, 0xc10e, 0x21, 0 - .dw 0xc6c0, 0xc10e, 0xc6ff, 0xc10e, 0x21, 0 - .dw 0xc740, 0xc10e, 0xc77f, 0xc10e, 0x21, 0 - .dw 0xc7c0, 0xc10e, 0xc7ff, 0xc10e, 0x21, 0 - .dw 0xc840, 0xc10e, 0xc87f, 0xc10e, 0x21, 0 - .dw 0xc8c0, 0xc10e, 0xc8ff, 0xc10e, 0x21, 0 - .dw 0xc940, 0xc10e, 0xc97f, 0xc10e, 0x21, 0 - .dw 0xc9c0, 0xc10e, 0xc9ff, 0xc10e, 0x21, 0 - .dw 0xca40, 0xc10e, 0xca7f, 0xc10e, 0x21, 0 - .dw 0xcac0, 0xc10e, 0xcaff, 0xc10e, 0x21, 0 - .dw 0xcb40, 0xc10e, 0xcb7f, 0xc10e, 0x21, 0 - .dw 0xcbc0, 0xc10e, 0xcbff, 0xc10e, 0x21, 0 - .dw 0xcc40, 0xc10e, 0xcc7f, 0xc10e, 0x21, 0 - .dw 0xccc0, 0xc10e, 0xccff, 0xc10e, 0x21, 0 - .dw 0xcd40, 0xc10e, 0xcd7f, 0xc10e, 0x21, 0 - .dw 0xcdc0, 0xc10e, 0xcdff, 0xc10e, 0x21, 0 - .dw 0xce40, 0xc10e, 0xce7f, 0xc10e, 0x21, 0 - .dw 0xcec0, 0xc10e, 0xceff, 0xc10e, 0x21, 0 - .dw 0xcf40, 0xc10e, 0xcf7f, 0xc10e, 0x21, 0 - .dw 0xcfc0, 0xc10e, 0xcfff, 0xc10e, 0x21, 0 - .dw 0xd040, 0xc10e, 0xd07f, 0xc10e, 0x21, 0 - .dw 0xd0c0, 0xc10e, 0xd0ff, 0xc10e, 0x21, 0 - .dw 0xd140, 0xc10e, 0xd17f, 0xc10e, 0x21, 0 - .dw 0xd1c0, 0xc10e, 0xd1ff, 0xc10e, 0x21, 0 - .dw 0xd240, 0xc10e, 0xd27f, 0xc10e, 0x21, 0 - .dw 0xd2c0, 0xc10e, 0xd2ff, 0xc10e, 0x21, 0 - .dw 0xd340, 0xc10e, 0xd37f, 0xc10e, 0x21, 0 - .dw 0xd3c0, 0xc10e, 0xd3ff, 0xc10e, 0x21, 0 - .dw 0xd440, 0xc10e, 0xd47f, 0xc10e, 0x21, 0 - .dw 0xd4c0, 0xc10e, 0xd4ff, 0xc10e, 0x21, 0 - .dw 0xd540, 0xc10e, 0xd57f, 0xc10e, 0x21, 0 - .dw 0xd5c0, 0xc10e, 0xd5ff, 0xc10e, 0x21, 0 - .dw 0xd640, 0xc10e, 0xd67f, 0xc10e, 0x21, 0 - .dw 0xd6c0, 0xc10e, 0xd6ff, 0xc10e, 0x21, 0 - .dw 0xd740, 0xc10e, 0xd77f, 0xc10e, 0x21, 0 - .dw 0xd7c0, 0xc10e, 0xd7ff, 0xc10e, 0x21, 0 - .dw 0xd840, 0xc10e, 0xd87f, 0xc10e, 0x21, 0 - .dw 0xd8c0, 0xc10e, 0xd8ff, 0xc10e, 0x21, 0 - .dw 0xd940, 0xc10e, 0xd97f, 0xc10e, 0x21, 0 - .dw 0xd9c0, 0xc10e, 0xdfff, 0xc10e, 0x21, 0 - .dw 0xe040, 0xc10e, 0xe07f, 0xc10e, 0x21, 0 - .dw 0xe0c0, 0xc10e, 0xe0ff, 0xc10e, 0x21, 0 - .dw 0xe140, 0xc10e, 0xe17f, 0xc10e, 0x21, 0 - .dw 0xe1c0, 0xc10e, 0xe1ff, 0xc10e, 0x21, 0 - .dw 0xe240, 0xc10e, 0xe27f, 0xc10e, 0x21, 0 - .dw 0xe2c0, 0xc10e, 0xe2ff, 0xc10e, 0x21, 0 - .dw 0xe340, 0xc10e, 0xe37f, 0xc10e, 0x21, 0 - .dw 0xe3c0, 0xc10e, 0xe3ff, 0xc10e, 0x21, 0 - .dw 0xe440, 0xc10e, 0xe47f, 0xc10e, 0x21, 0 - .dw 0xe4c0, 0xc10e, 0xe4ff, 0xc10e, 0x21, 0 - .dw 0xe540, 0xc10e, 0xe57f, 0xc10e, 0x21, 0 - .dw 0xe5c0, 0xc10e, 0xe5ff, 0xc10e, 0x21, 0 - .dw 0xe640, 0xc10e, 0xe67f, 0xc10e, 0x21, 0 - .dw 0xe6c0, 0xc10e, 0xe6ff, 0xc10e, 0x21, 0 - .dw 0xe740, 0xc10e, 0xe77f, 0xc10e, 0x21, 0 - .dw 0xe7c0, 0xc10e, 0xe7ff, 0xc10e, 0x21, 0 - .dw 0xe840, 0xc10e, 0xe87f, 0xc10e, 0x21, 0 - .dw 0xe8c0, 0xc10e, 0xe8ff, 0xc10e, 0x21, 0 - .dw 0xe940, 0xc10e, 0xe97f, 0xc10e, 0x21, 0 - .dw 0xe9c0, 0xc10e, 0xe9ff, 0xc10e, 0x21, 0 - .dw 0xea40, 0xc10e, 0xea7f, 0xc10e, 0x21, 0 - .dw 0xeac0, 0xc10e, 0xeaff, 0xc10e, 0x21, 0 - .dw 0xeb40, 0xc10e, 0xeb7f, 0xc10e, 0x21, 0 - .dw 0xebc0, 0xc10e, 0xebff, 0xc10e, 0x21, 0 - .dw 0xec40, 0xc10e, 0xec7f, 0xc10e, 0x21, 0 - .dw 0xecc0, 0xc10e, 0xecff, 0xc10e, 0x21, 0 - .dw 0xed40, 0xc10e, 0xed7f, 0xc10e, 0x21, 0 - .dw 0xedc0, 0xc10e, 0xedff, 0xc10e, 0x21, 0 - .dw 0xee40, 0xc10e, 0xee7f, 0xc10e, 0x21, 0 - .dw 0xeec0, 0xc10e, 0xeeff, 0xc10e, 0x21, 0 - .dw 0xef40, 0xc10e, 0xef7f, 0xc10e, 0x21, 0 - .dw 0xefc0, 0xc10e, 0xefff, 0xc10e, 0x21, 0 - .dw 0xf040, 0xc10e, 0xf07f, 0xc10e, 0x21, 0 - .dw 0xf0c0, 0xc10e, 0xf0ff, 0xc10e, 0x21, 0 - .dw 0xf140, 0xc10e, 0xf17f, 0xc10e, 0x21, 0 - .dw 0xf1c0, 0xc10e, 0xf1ff, 0xc10e, 0x21, 0 - .dw 0xf240, 0xc10e, 0xf27f, 0xc10e, 0x21, 0 - .dw 0xf2c0, 0xc10e, 0xf2ff, 0xc10e, 0x21, 0 - .dw 0xf340, 0xc10e, 0xf37f, 0xc10e, 0x21, 0 - .dw 0xf3c0, 0xc10e, 0xf3ff, 0xc10e, 0x21, 0 - .dw 0xf440, 0xc10e, 0xf47f, 0xc10e, 0x21, 0 - .dw 0xf4c0, 0xc10e, 0xf4ff, 0xc10e, 0x21, 0 - .dw 0xf540, 0xc10e, 0xf57f, 0xc10e, 0x21, 0 - .dw 0xf5c0, 0xc10e, 0xf5ff, 0xc10e, 0x21, 0 - .dw 0xf640, 0xc10e, 0xf67f, 0xc10e, 0x21, 0 - .dw 0xf6c0, 0xc10e, 0xf6ff, 0xc10e, 0x21, 0 - .dw 0xf740, 0xc10e, 0xf77f, 0xc10e, 0x21, 0 - .dw 0xf7c0, 0xc10e, 0xf7ff, 0xc10e, 0x21, 0 - .dw 0xf840, 0xc10e, 0xf87f, 0xc10e, 0x21, 0 - .dw 0xf8c0, 0xc10e, 0xf8ff, 0xc10e, 0x21, 0 - .dw 0xf940, 0xc10e, 0xf97f, 0xc10e, 0x21, 0 - .dw 0xf9c0, 0xc10e, 0xffff, 0xc10e, 0x21, 0 - .dw 0x0040, 0xc10f, 0x007f, 0xc10f, 0x21, 0 - .dw 0x00c0, 0xc10f, 0x00ff, 0xc10f, 0x21, 0 - .dw 0x0140, 0xc10f, 0x017f, 0xc10f, 0x21, 0 - .dw 0x01c0, 0xc10f, 0x01ff, 0xc10f, 0x21, 0 - .dw 0x0240, 0xc10f, 0x027f, 0xc10f, 0x21, 0 - .dw 0x02c0, 0xc10f, 0x02ff, 0xc10f, 0x21, 0 - .dw 0x0340, 0xc10f, 0x037f, 0xc10f, 0x21, 0 - .dw 0x03c0, 0xc10f, 0x03ff, 0xc10f, 0x21, 0 - .dw 0x0440, 0xc10f, 0x047f, 0xc10f, 0x21, 0 - .dw 0x04c0, 0xc10f, 0x04ff, 0xc10f, 0x21, 0 - .dw 0x0540, 0xc10f, 0x057f, 0xc10f, 0x21, 0 - .dw 0x05c0, 0xc10f, 0x05ff, 0xc10f, 0x21, 0 - .dw 0x0640, 0xc10f, 0x067f, 0xc10f, 0x21, 0 - .dw 0x06c0, 0xc10f, 0x06ff, 0xc10f, 0x21, 0 - .dw 0x0740, 0xc10f, 0x077f, 0xc10f, 0x21, 0 - .dw 0x07c0, 0xc10f, 0x07ff, 0xc10f, 0x21, 0 - .dw 0x0840, 0xc10f, 0x087f, 0xc10f, 0x21, 0 - .dw 0x08c0, 0xc10f, 0x08ff, 0xc10f, 0x21, 0 - .dw 0x0940, 0xc10f, 0x097f, 0xc10f, 0x21, 0 - .dw 0x09c0, 0xc10f, 0x09ff, 0xc10f, 0x21, 0 - .dw 0x0a40, 0xc10f, 0x0a7f, 0xc10f, 0x21, 0 - .dw 0x0ac0, 0xc10f, 0x0aff, 0xc10f, 0x21, 0 - .dw 0x0b40, 0xc10f, 0x0b7f, 0xc10f, 0x21, 0 - .dw 0x0bc0, 0xc10f, 0x0bff, 0xc10f, 0x21, 0 - .dw 0x0c40, 0xc10f, 0x0c7f, 0xc10f, 0x21, 0 - .dw 0x0cc0, 0xc10f, 0x0cff, 0xc10f, 0x21, 0 - .dw 0x0d40, 0xc10f, 0x0d7f, 0xc10f, 0x21, 0 - .dw 0x0dc0, 0xc10f, 0x0dff, 0xc10f, 0x21, 0 - .dw 0x0e40, 0xc10f, 0x0e7f, 0xc10f, 0x21, 0 - .dw 0x0ec0, 0xc10f, 0x0eff, 0xc10f, 0x21, 0 - .dw 0x0f40, 0xc10f, 0x0f7f, 0xc10f, 0x21, 0 - .dw 0x0fc0, 0xc10f, 0x0fff, 0xc10f, 0x21, 0 - .dw 0x1040, 0xc10f, 0x107f, 0xc10f, 0x21, 0 - .dw 0x10c0, 0xc10f, 0x10ff, 0xc10f, 0x21, 0 - .dw 0x1140, 0xc10f, 0x117f, 0xc10f, 0x21, 0 - .dw 0x11c0, 0xc10f, 0x11ff, 0xc10f, 0x21, 0 - .dw 0x1240, 0xc10f, 0x127f, 0xc10f, 0x21, 0 - .dw 0x12c0, 0xc10f, 0x12ff, 0xc10f, 0x21, 0 - .dw 0x1340, 0xc10f, 0x137f, 0xc10f, 0x21, 0 - .dw 0x13c0, 0xc10f, 0x13ff, 0xc10f, 0x21, 0 - .dw 0x1440, 0xc10f, 0x147f, 0xc10f, 0x21, 0 - .dw 0x14c0, 0xc10f, 0x14ff, 0xc10f, 0x21, 0 - .dw 0x1540, 0xc10f, 0x157f, 0xc10f, 0x21, 0 - .dw 0x15c0, 0xc10f, 0x15ff, 0xc10f, 0x21, 0 - .dw 0x1640, 0xc10f, 0x167f, 0xc10f, 0x21, 0 - .dw 0x16c0, 0xc10f, 0x16ff, 0xc10f, 0x21, 0 - .dw 0x1740, 0xc10f, 0x177f, 0xc10f, 0x21, 0 - .dw 0x17c0, 0xc10f, 0x17ff, 0xc10f, 0x21, 0 - .dw 0x1840, 0xc10f, 0x187f, 0xc10f, 0x21, 0 - .dw 0x18c0, 0xc10f, 0x18ff, 0xc10f, 0x21, 0 - .dw 0x1940, 0xc10f, 0x197f, 0xc10f, 0x21, 0 - .dw 0x19c0, 0xc10f, 0x1fff, 0xc10f, 0x21, 0 - .dw 0x2040, 0xc10f, 0x207f, 0xc10f, 0x21, 0 - .dw 0x20c0, 0xc10f, 0x20ff, 0xc10f, 0x21, 0 - .dw 0x2140, 0xc10f, 0x217f, 0xc10f, 0x21, 0 - .dw 0x21c0, 0xc10f, 0x21ff, 0xc10f, 0x21, 0 - .dw 0x2240, 0xc10f, 0x227f, 0xc10f, 0x21, 0 - .dw 0x22c0, 0xc10f, 0x22ff, 0xc10f, 0x21, 0 - .dw 0x2340, 0xc10f, 0x237f, 0xc10f, 0x21, 0 - .dw 0x23c0, 0xc10f, 0x23ff, 0xc10f, 0x21, 0 - .dw 0x2440, 0xc10f, 0x247f, 0xc10f, 0x21, 0 - .dw 0x24c0, 0xc10f, 0x24ff, 0xc10f, 0x21, 0 - .dw 0x2540, 0xc10f, 0x257f, 0xc10f, 0x21, 0 - .dw 0x25c0, 0xc10f, 0x25ff, 0xc10f, 0x21, 0 - .dw 0x2640, 0xc10f, 0x267f, 0xc10f, 0x21, 0 - .dw 0x26c0, 0xc10f, 0x26ff, 0xc10f, 0x21, 0 - .dw 0x2740, 0xc10f, 0x277f, 0xc10f, 0x21, 0 - .dw 0x27c0, 0xc10f, 0x27ff, 0xc10f, 0x21, 0 - .dw 0x2840, 0xc10f, 0x287f, 0xc10f, 0x21, 0 - .dw 0x28c0, 0xc10f, 0x28ff, 0xc10f, 0x21, 0 - .dw 0x2940, 0xc10f, 0x297f, 0xc10f, 0x21, 0 - .dw 0x29c0, 0xc10f, 0x29ff, 0xc10f, 0x21, 0 - .dw 0x2a40, 0xc10f, 0x2a7f, 0xc10f, 0x21, 0 - .dw 0x2ac0, 0xc10f, 0x2aff, 0xc10f, 0x21, 0 - .dw 0x2b40, 0xc10f, 0x2b7f, 0xc10f, 0x21, 0 - .dw 0x2bc0, 0xc10f, 0x2bff, 0xc10f, 0x21, 0 - .dw 0x2c40, 0xc10f, 0x2c7f, 0xc10f, 0x21, 0 - .dw 0x2cc0, 0xc10f, 0x2cff, 0xc10f, 0x21, 0 - .dw 0x2d40, 0xc10f, 0x2d7f, 0xc10f, 0x21, 0 - .dw 0x2dc0, 0xc10f, 0x2dff, 0xc10f, 0x21, 0 - .dw 0x2e40, 0xc10f, 0x2e7f, 0xc10f, 0x21, 0 - .dw 0x2ec0, 0xc10f, 0x2eff, 0xc10f, 0x21, 0 - .dw 0x2f40, 0xc10f, 0x2f7f, 0xc10f, 0x21, 0 - .dw 0x2fc0, 0xc10f, 0x2fff, 0xc10f, 0x21, 0 - .dw 0x3040, 0xc10f, 0x307f, 0xc10f, 0x21, 0 - .dw 0x30c0, 0xc10f, 0x30ff, 0xc10f, 0x21, 0 - .dw 0x3140, 0xc10f, 0x317f, 0xc10f, 0x21, 0 - .dw 0x31c0, 0xc10f, 0x31ff, 0xc10f, 0x21, 0 - .dw 0x3240, 0xc10f, 0x327f, 0xc10f, 0x21, 0 - .dw 0x32c0, 0xc10f, 0x32ff, 0xc10f, 0x21, 0 - .dw 0x3340, 0xc10f, 0x337f, 0xc10f, 0x21, 0 - .dw 0x33c0, 0xc10f, 0x33ff, 0xc10f, 0x21, 0 - .dw 0x3440, 0xc10f, 0x347f, 0xc10f, 0x21, 0 - .dw 0x34c0, 0xc10f, 0x34ff, 0xc10f, 0x21, 0 - .dw 0x3540, 0xc10f, 0x357f, 0xc10f, 0x21, 0 - .dw 0x35c0, 0xc10f, 0x35ff, 0xc10f, 0x21, 0 - .dw 0x3640, 0xc10f, 0x367f, 0xc10f, 0x21, 0 - .dw 0x36c0, 0xc10f, 0x36ff, 0xc10f, 0x21, 0 - .dw 0x3740, 0xc10f, 0x377f, 0xc10f, 0x21, 0 - .dw 0x37c0, 0xc10f, 0x37ff, 0xc10f, 0x21, 0 - .dw 0x3840, 0xc10f, 0x387f, 0xc10f, 0x21, 0 - .dw 0x38c0, 0xc10f, 0x38ff, 0xc10f, 0x21, 0 - .dw 0x3940, 0xc10f, 0x397f, 0xc10f, 0x21, 0 - .dw 0x39c0, 0xc10f, 0xffff, 0xc10f, 0x21, 0 - .dw 0x1a00, 0xc110, 0x1fff, 0xc110, 0x21, 0 - .dw 0x3a00, 0xc110, 0x3fff, 0xc110, 0x21, 0 - .dw 0x5a00, 0xc110, 0x5fff, 0xc110, 0x21, 0 - .dw 0x7a00, 0xc110, 0x7fff, 0xc110, 0x21, 0 - .dw 0x9a00, 0xc110, 0x9fff, 0xc110, 0x21, 0 - .dw 0xba00, 0xc110, 0xbfff, 0xc110, 0x21, 0 - .dw 0xda00, 0xc110, 0xdfff, 0xc110, 0x21, 0 - .dw 0xfa00, 0xc110, 0xffff, 0xc110, 0x21, 0 - .dw 0x1a00, 0xc111, 0x1fff, 0xc111, 0x21, 0 - .dw 0x3a00, 0xc111, 0x3fff, 0xc111, 0x21, 0 - .dw 0x5a00, 0xc111, 0x5fff, 0xc111, 0x21, 0 - .dw 0x7a00, 0xc111, 0x7fff, 0xc111, 0x21, 0 - .dw 0x9a00, 0xc111, 0x9fff, 0xc111, 0x21, 0 - .dw 0xba00, 0xc111, 0xbfff, 0xc111, 0x21, 0 - .dw 0xda00, 0xc111, 0xdfff, 0xc111, 0x21, 0 - .dw 0xfa00, 0xc111, 0xffff, 0xc111, 0x21, 0 - .dw 0x1a00, 0xc112, 0x1fff, 0xc112, 0x21, 0 - .dw 0x3a00, 0xc112, 0x3fff, 0xc112, 0x21, 0 - .dw 0x5a00, 0xc112, 0x5fff, 0xc112, 0x21, 0 - .dw 0x7a00, 0xc112, 0x7fff, 0xc112, 0x21, 0 - .dw 0x9a00, 0xc112, 0x9fff, 0xc112, 0x21, 0 - .dw 0xba00, 0xc112, 0xbfff, 0xc112, 0x21, 0 - .dw 0xda00, 0xc112, 0xdfff, 0xc112, 0x21, 0 - .dw 0xfa00, 0xc112, 0xffff, 0xc113, 0x21, 0 - .dw 0x1a00, 0xc114, 0x1fff, 0xc114, 0x21, 0 - .dw 0x3a00, 0xc114, 0x3fff, 0xc114, 0x21, 0 - .dw 0x5a00, 0xc114, 0x5fff, 0xc114, 0x21, 0 - .dw 0x7a00, 0xc114, 0x7fff, 0xc114, 0x21, 0 - .dw 0x9a00, 0xc114, 0x9fff, 0xc114, 0x21, 0 - .dw 0xba00, 0xc114, 0xbfff, 0xc114, 0x21, 0 - .dw 0xda00, 0xc114, 0xdfff, 0xc114, 0x21, 0 - .dw 0xfa00, 0xc114, 0xffff, 0xc114, 0x21, 0 - .dw 0x1a00, 0xc115, 0x1fff, 0xc115, 0x21, 0 - .dw 0x3a00, 0xc115, 0x3fff, 0xc115, 0x21, 0 - .dw 0x5a00, 0xc115, 0x5fff, 0xc115, 0x21, 0 - .dw 0x7a00, 0xc115, 0x7fff, 0xc115, 0x21, 0 - .dw 0x9a00, 0xc115, 0x9fff, 0xc115, 0x21, 0 - .dw 0xba00, 0xc115, 0xbfff, 0xc115, 0x21, 0 - .dw 0xda00, 0xc115, 0xdfff, 0xc115, 0x21, 0 - .dw 0xfa00, 0xc115, 0xffff, 0xc115, 0x21, 0 - .dw 0x1a00, 0xc116, 0x1fff, 0xc116, 0x21, 0 - .dw 0x3a00, 0xc116, 0x3fff, 0xc116, 0x21, 0 - .dw 0x5a00, 0xc116, 0x5fff, 0xc116, 0x21, 0 - .dw 0x7a00, 0xc116, 0x7fff, 0xc116, 0x21, 0 - .dw 0x9a00, 0xc116, 0x9fff, 0xc116, 0x21, 0 - .dw 0xba00, 0xc116, 0xbfff, 0xc116, 0x21, 0 - .dw 0xda00, 0xc116, 0xdfff, 0xc116, 0x21, 0 - .dw 0xfa00, 0xc116, 0xffff, 0xc116, 0x21, 0 - .dw 0x1a00, 0xc117, 0x1fff, 0xc117, 0x21, 0 - .dw 0x3a00, 0xc117, 0x1fff, 0xc118, 0x21, 0 - .dw 0x2040, 0xc118, 0x207f, 0xc118, 0x21, 0 - .dw 0x20c0, 0xc118, 0x20ff, 0xc118, 0x21, 0 - .dw 0x2140, 0xc118, 0x217f, 0xc118, 0x21, 0 - .dw 0x21c0, 0xc118, 0x21ff, 0xc118, 0x21, 0 - .dw 0x2240, 0xc118, 0x227f, 0xc118, 0x21, 0 - .dw 0x22c0, 0xc118, 0x22ff, 0xc118, 0x21, 0 - .dw 0x2340, 0xc118, 0x237f, 0xc118, 0x21, 0 - .dw 0x23c0, 0xc118, 0x23ff, 0xc118, 0x21, 0 - .dw 0x2440, 0xc118, 0x247f, 0xc118, 0x21, 0 - .dw 0x24c0, 0xc118, 0x24ff, 0xc118, 0x21, 0 - .dw 0x2540, 0xc118, 0x257f, 0xc118, 0x21, 0 - .dw 0x25c0, 0xc118, 0x25ff, 0xc118, 0x21, 0 - .dw 0x2640, 0xc118, 0x267f, 0xc118, 0x21, 0 - .dw 0x26c0, 0xc118, 0x26ff, 0xc118, 0x21, 0 - .dw 0x2740, 0xc118, 0x277f, 0xc118, 0x21, 0 - .dw 0x27c0, 0xc118, 0x27ff, 0xc118, 0x21, 0 - .dw 0x2840, 0xc118, 0x287f, 0xc118, 0x21, 0 - .dw 0x28c0, 0xc118, 0x28ff, 0xc118, 0x21, 0 - .dw 0x2940, 0xc118, 0x297f, 0xc118, 0x21, 0 - .dw 0x29c0, 0xc118, 0x29ff, 0xc118, 0x21, 0 - .dw 0x2a40, 0xc118, 0x2a7f, 0xc118, 0x21, 0 - .dw 0x2ac0, 0xc118, 0x2aff, 0xc118, 0x21, 0 - .dw 0x2b40, 0xc118, 0x2b7f, 0xc118, 0x21, 0 - .dw 0x2bc0, 0xc118, 0x2bff, 0xc118, 0x21, 0 - .dw 0x2c40, 0xc118, 0x2c7f, 0xc118, 0x21, 0 - .dw 0x2cc0, 0xc118, 0x2cff, 0xc118, 0x21, 0 - .dw 0x2d40, 0xc118, 0x2d7f, 0xc118, 0x21, 0 - .dw 0x2dc0, 0xc118, 0x2dff, 0xc118, 0x21, 0 - .dw 0x2e40, 0xc118, 0x2e7f, 0xc118, 0x21, 0 - .dw 0x2ec0, 0xc118, 0x2eff, 0xc118, 0x21, 0 - .dw 0x2f40, 0xc118, 0x2f7f, 0xc118, 0x21, 0 - .dw 0x2fc0, 0xc118, 0x2fff, 0xc118, 0x21, 0 - .dw 0x3040, 0xc118, 0x307f, 0xc118, 0x21, 0 - .dw 0x30c0, 0xc118, 0x30ff, 0xc118, 0x21, 0 - .dw 0x3140, 0xc118, 0x317f, 0xc118, 0x21, 0 - .dw 0x31c0, 0xc118, 0x31ff, 0xc118, 0x21, 0 - .dw 0x3240, 0xc118, 0x327f, 0xc118, 0x21, 0 - .dw 0x32c0, 0xc118, 0x32ff, 0xc118, 0x21, 0 - .dw 0x3340, 0xc118, 0x337f, 0xc118, 0x21, 0 - .dw 0x33c0, 0xc118, 0x33ff, 0xc118, 0x21, 0 - .dw 0x3440, 0xc118, 0x347f, 0xc118, 0x21, 0 - .dw 0x34c0, 0xc118, 0x34ff, 0xc118, 0x21, 0 - .dw 0x3540, 0xc118, 0x357f, 0xc118, 0x21, 0 - .dw 0x35c0, 0xc118, 0x35ff, 0xc118, 0x21, 0 - .dw 0x3640, 0xc118, 0x367f, 0xc118, 0x21, 0 - .dw 0x36c0, 0xc118, 0x36ff, 0xc118, 0x21, 0 - .dw 0x3740, 0xc118, 0x377f, 0xc118, 0x21, 0 - .dw 0x37c0, 0xc118, 0x37ff, 0xc118, 0x21, 0 - .dw 0x3840, 0xc118, 0x387f, 0xc118, 0x21, 0 - .dw 0x38c0, 0xc118, 0x38ff, 0xc118, 0x21, 0 - .dw 0x3940, 0xc118, 0x397f, 0xc118, 0x21, 0 - .dw 0x39c0, 0xc118, 0x5fff, 0xc118, 0x21, 0 - .dw 0x6040, 0xc118, 0x607f, 0xc118, 0x21, 0 - .dw 0x60c0, 0xc118, 0x60ff, 0xc118, 0x21, 0 - .dw 0x6140, 0xc118, 0x617f, 0xc118, 0x21, 0 - .dw 0x61c0, 0xc118, 0x61ff, 0xc118, 0x21, 0 - .dw 0x6240, 0xc118, 0x627f, 0xc118, 0x21, 0 - .dw 0x62c0, 0xc118, 0x62ff, 0xc118, 0x21, 0 - .dw 0x6340, 0xc118, 0x637f, 0xc118, 0x21, 0 - .dw 0x63c0, 0xc118, 0x63ff, 0xc118, 0x21, 0 - .dw 0x6440, 0xc118, 0x647f, 0xc118, 0x21, 0 - .dw 0x64c0, 0xc118, 0x64ff, 0xc118, 0x21, 0 - .dw 0x6540, 0xc118, 0x657f, 0xc118, 0x21, 0 - .dw 0x65c0, 0xc118, 0x65ff, 0xc118, 0x21, 0 - .dw 0x6640, 0xc118, 0x667f, 0xc118, 0x21, 0 - .dw 0x66c0, 0xc118, 0x66ff, 0xc118, 0x21, 0 - .dw 0x6740, 0xc118, 0x677f, 0xc118, 0x21, 0 - .dw 0x67c0, 0xc118, 0x67ff, 0xc118, 0x21, 0 - .dw 0x6840, 0xc118, 0x687f, 0xc118, 0x21, 0 - .dw 0x68c0, 0xc118, 0x68ff, 0xc118, 0x21, 0 - .dw 0x6940, 0xc118, 0x697f, 0xc118, 0x21, 0 - .dw 0x69c0, 0xc118, 0x69ff, 0xc118, 0x21, 0 - .dw 0x6a40, 0xc118, 0x6a7f, 0xc118, 0x21, 0 - .dw 0x6ac0, 0xc118, 0x6aff, 0xc118, 0x21, 0 - .dw 0x6b40, 0xc118, 0x6b7f, 0xc118, 0x21, 0 - .dw 0x6bc0, 0xc118, 0x6bff, 0xc118, 0x21, 0 - .dw 0x6c40, 0xc118, 0x6c7f, 0xc118, 0x21, 0 - .dw 0x6cc0, 0xc118, 0x6cff, 0xc118, 0x21, 0 - .dw 0x6d40, 0xc118, 0x6d7f, 0xc118, 0x21, 0 - .dw 0x6dc0, 0xc118, 0x6dff, 0xc118, 0x21, 0 - .dw 0x6e40, 0xc118, 0x6e7f, 0xc118, 0x21, 0 - .dw 0x6ec0, 0xc118, 0x6eff, 0xc118, 0x21, 0 - .dw 0x6f40, 0xc118, 0x6f7f, 0xc118, 0x21, 0 - .dw 0x6fc0, 0xc118, 0x6fff, 0xc118, 0x21, 0 - .dw 0x7040, 0xc118, 0x707f, 0xc118, 0x21, 0 - .dw 0x70c0, 0xc118, 0x70ff, 0xc118, 0x21, 0 - .dw 0x7140, 0xc118, 0x717f, 0xc118, 0x21, 0 - .dw 0x71c0, 0xc118, 0x71ff, 0xc118, 0x21, 0 - .dw 0x7240, 0xc118, 0x727f, 0xc118, 0x21, 0 - .dw 0x72c0, 0xc118, 0x72ff, 0xc118, 0x21, 0 - .dw 0x7340, 0xc118, 0x737f, 0xc118, 0x21, 0 - .dw 0x73c0, 0xc118, 0x73ff, 0xc118, 0x21, 0 - .dw 0x7440, 0xc118, 0x747f, 0xc118, 0x21, 0 - .dw 0x74c0, 0xc118, 0x74ff, 0xc118, 0x21, 0 - .dw 0x7540, 0xc118, 0x757f, 0xc118, 0x21, 0 - .dw 0x75c0, 0xc118, 0x75ff, 0xc118, 0x21, 0 - .dw 0x7640, 0xc118, 0x767f, 0xc118, 0x21, 0 - .dw 0x76c0, 0xc118, 0x76ff, 0xc118, 0x21, 0 - .dw 0x7740, 0xc118, 0x777f, 0xc118, 0x21, 0 - .dw 0x77c0, 0xc118, 0x77ff, 0xc118, 0x21, 0 - .dw 0x7840, 0xc118, 0x787f, 0xc118, 0x21, 0 - .dw 0x78c0, 0xc118, 0x78ff, 0xc118, 0x21, 0 - .dw 0x7940, 0xc118, 0x797f, 0xc118, 0x21, 0 - .dw 0x79c0, 0xc118, 0x9fff, 0xc118, 0x21, 0 - .dw 0xa040, 0xc118, 0xa07f, 0xc118, 0x21, 0 - .dw 0xa0c0, 0xc118, 0xa0ff, 0xc118, 0x21, 0 - .dw 0xa140, 0xc118, 0xa17f, 0xc118, 0x21, 0 - .dw 0xa1c0, 0xc118, 0xa1ff, 0xc118, 0x21, 0 - .dw 0xa240, 0xc118, 0xa27f, 0xc118, 0x21, 0 - .dw 0xa2c0, 0xc118, 0xa2ff, 0xc118, 0x21, 0 - .dw 0xa340, 0xc118, 0xa37f, 0xc118, 0x21, 0 - .dw 0xa3c0, 0xc118, 0xa3ff, 0xc118, 0x21, 0 - .dw 0xa440, 0xc118, 0xa47f, 0xc118, 0x21, 0 - .dw 0xa4c0, 0xc118, 0xa4ff, 0xc118, 0x21, 0 - .dw 0xa540, 0xc118, 0xa57f, 0xc118, 0x21, 0 - .dw 0xa5c0, 0xc118, 0xa5ff, 0xc118, 0x21, 0 - .dw 0xa640, 0xc118, 0xa67f, 0xc118, 0x21, 0 - .dw 0xa6c0, 0xc118, 0xa6ff, 0xc118, 0x21, 0 - .dw 0xa740, 0xc118, 0xa77f, 0xc118, 0x21, 0 - .dw 0xa7c0, 0xc118, 0xa7ff, 0xc118, 0x21, 0 - .dw 0xa840, 0xc118, 0xa87f, 0xc118, 0x21, 0 - .dw 0xa8c0, 0xc118, 0xa8ff, 0xc118, 0x21, 0 - .dw 0xa940, 0xc118, 0xa97f, 0xc118, 0x21, 0 - .dw 0xa9c0, 0xc118, 0xa9ff, 0xc118, 0x21, 0 - .dw 0xaa40, 0xc118, 0xaa7f, 0xc118, 0x21, 0 - .dw 0xaac0, 0xc118, 0xaaff, 0xc118, 0x21, 0 - .dw 0xab40, 0xc118, 0xab7f, 0xc118, 0x21, 0 - .dw 0xabc0, 0xc118, 0xabff, 0xc118, 0x21, 0 - .dw 0xac40, 0xc118, 0xac7f, 0xc118, 0x21, 0 - .dw 0xacc0, 0xc118, 0xacff, 0xc118, 0x21, 0 - .dw 0xad40, 0xc118, 0xad7f, 0xc118, 0x21, 0 - .dw 0xadc0, 0xc118, 0xadff, 0xc118, 0x21, 0 - .dw 0xae40, 0xc118, 0xae7f, 0xc118, 0x21, 0 - .dw 0xaec0, 0xc118, 0xaeff, 0xc118, 0x21, 0 - .dw 0xaf40, 0xc118, 0xaf7f, 0xc118, 0x21, 0 - .dw 0xafc0, 0xc118, 0xafff, 0xc118, 0x21, 0 - .dw 0xb040, 0xc118, 0xb07f, 0xc118, 0x21, 0 - .dw 0xb0c0, 0xc118, 0xb0ff, 0xc118, 0x21, 0 - .dw 0xb140, 0xc118, 0xb17f, 0xc118, 0x21, 0 - .dw 0xb1c0, 0xc118, 0xb1ff, 0xc118, 0x21, 0 - .dw 0xb240, 0xc118, 0xb27f, 0xc118, 0x21, 0 - .dw 0xb2c0, 0xc118, 0xb2ff, 0xc118, 0x21, 0 - .dw 0xb340, 0xc118, 0xb37f, 0xc118, 0x21, 0 - .dw 0xb3c0, 0xc118, 0xb3ff, 0xc118, 0x21, 0 - .dw 0xb440, 0xc118, 0xb47f, 0xc118, 0x21, 0 - .dw 0xb4c0, 0xc118, 0xb4ff, 0xc118, 0x21, 0 - .dw 0xb540, 0xc118, 0xb57f, 0xc118, 0x21, 0 - .dw 0xb5c0, 0xc118, 0xb5ff, 0xc118, 0x21, 0 - .dw 0xb640, 0xc118, 0xb67f, 0xc118, 0x21, 0 - .dw 0xb6c0, 0xc118, 0xb6ff, 0xc118, 0x21, 0 - .dw 0xb740, 0xc118, 0xb77f, 0xc118, 0x21, 0 - .dw 0xb7c0, 0xc118, 0xb7ff, 0xc118, 0x21, 0 - .dw 0xb840, 0xc118, 0xb87f, 0xc118, 0x21, 0 - .dw 0xb8c0, 0xc118, 0xb8ff, 0xc118, 0x21, 0 - .dw 0xb940, 0xc118, 0xb97f, 0xc118, 0x21, 0 - .dw 0xb9c0, 0xc118, 0xdfff, 0xc118, 0x21, 0 - .dw 0xe040, 0xc118, 0xe07f, 0xc118, 0x21, 0 - .dw 0xe0c0, 0xc118, 0xe0ff, 0xc118, 0x21, 0 - .dw 0xe140, 0xc118, 0xe17f, 0xc118, 0x21, 0 - .dw 0xe1c0, 0xc118, 0xe1ff, 0xc118, 0x21, 0 - .dw 0xe240, 0xc118, 0xe27f, 0xc118, 0x21, 0 - .dw 0xe2c0, 0xc118, 0xe2ff, 0xc118, 0x21, 0 - .dw 0xe340, 0xc118, 0xe37f, 0xc118, 0x21, 0 - .dw 0xe3c0, 0xc118, 0xe3ff, 0xc118, 0x21, 0 - .dw 0xe440, 0xc118, 0xe47f, 0xc118, 0x21, 0 - .dw 0xe4c0, 0xc118, 0xe4ff, 0xc118, 0x21, 0 - .dw 0xe540, 0xc118, 0xe57f, 0xc118, 0x21, 0 - .dw 0xe5c0, 0xc118, 0xe5ff, 0xc118, 0x21, 0 - .dw 0xe640, 0xc118, 0xe67f, 0xc118, 0x21, 0 - .dw 0xe6c0, 0xc118, 0xe6ff, 0xc118, 0x21, 0 - .dw 0xe740, 0xc118, 0xe77f, 0xc118, 0x21, 0 - .dw 0xe7c0, 0xc118, 0xe7ff, 0xc118, 0x21, 0 - .dw 0xe840, 0xc118, 0xe87f, 0xc118, 0x21, 0 - .dw 0xe8c0, 0xc118, 0xe8ff, 0xc118, 0x21, 0 - .dw 0xe940, 0xc118, 0xe97f, 0xc118, 0x21, 0 - .dw 0xe9c0, 0xc118, 0xe9ff, 0xc118, 0x21, 0 - .dw 0xea40, 0xc118, 0xea7f, 0xc118, 0x21, 0 - .dw 0xeac0, 0xc118, 0xeaff, 0xc118, 0x21, 0 - .dw 0xeb40, 0xc118, 0xeb7f, 0xc118, 0x21, 0 - .dw 0xebc0, 0xc118, 0xebff, 0xc118, 0x21, 0 - .dw 0xec40, 0xc118, 0xec7f, 0xc118, 0x21, 0 - .dw 0xecc0, 0xc118, 0xecff, 0xc118, 0x21, 0 - .dw 0xed40, 0xc118, 0xed7f, 0xc118, 0x21, 0 - .dw 0xedc0, 0xc118, 0xedff, 0xc118, 0x21, 0 - .dw 0xee40, 0xc118, 0xee7f, 0xc118, 0x21, 0 - .dw 0xeec0, 0xc118, 0xeeff, 0xc118, 0x21, 0 - .dw 0xef40, 0xc118, 0xef7f, 0xc118, 0x21, 0 - .dw 0xefc0, 0xc118, 0xefff, 0xc118, 0x21, 0 - .dw 0xf040, 0xc118, 0xf07f, 0xc118, 0x21, 0 - .dw 0xf0c0, 0xc118, 0xf0ff, 0xc118, 0x21, 0 - .dw 0xf140, 0xc118, 0xf17f, 0xc118, 0x21, 0 - .dw 0xf1c0, 0xc118, 0xf1ff, 0xc118, 0x21, 0 - .dw 0xf240, 0xc118, 0xf27f, 0xc118, 0x21, 0 - .dw 0xf2c0, 0xc118, 0xf2ff, 0xc118, 0x21, 0 - .dw 0xf340, 0xc118, 0xf37f, 0xc118, 0x21, 0 - .dw 0xf3c0, 0xc118, 0xf3ff, 0xc118, 0x21, 0 - .dw 0xf440, 0xc118, 0xf47f, 0xc118, 0x21, 0 - .dw 0xf4c0, 0xc118, 0xf4ff, 0xc118, 0x21, 0 - .dw 0xf540, 0xc118, 0xf57f, 0xc118, 0x21, 0 - .dw 0xf5c0, 0xc118, 0xf5ff, 0xc118, 0x21, 0 - .dw 0xf640, 0xc118, 0xf67f, 0xc118, 0x21, 0 - .dw 0xf6c0, 0xc118, 0xf6ff, 0xc118, 0x21, 0 - .dw 0xf740, 0xc118, 0xf77f, 0xc118, 0x21, 0 - .dw 0xf7c0, 0xc118, 0xf7ff, 0xc118, 0x21, 0 - .dw 0xf840, 0xc118, 0xf87f, 0xc118, 0x21, 0 - .dw 0xf8c0, 0xc118, 0xf8ff, 0xc118, 0x21, 0 - .dw 0xf940, 0xc118, 0xf97f, 0xc118, 0x21, 0 - .dw 0xf9c0, 0xc118, 0x1fff, 0xc119, 0x21, 0 - .dw 0x2040, 0xc119, 0x207f, 0xc119, 0x21, 0 - .dw 0x20c0, 0xc119, 0x20ff, 0xc119, 0x21, 0 - .dw 0x2140, 0xc119, 0x217f, 0xc119, 0x21, 0 - .dw 0x21c0, 0xc119, 0x21ff, 0xc119, 0x21, 0 - .dw 0x2240, 0xc119, 0x227f, 0xc119, 0x21, 0 - .dw 0x22c0, 0xc119, 0x22ff, 0xc119, 0x21, 0 - .dw 0x2340, 0xc119, 0x237f, 0xc119, 0x21, 0 - .dw 0x23c0, 0xc119, 0x23ff, 0xc119, 0x21, 0 - .dw 0x2440, 0xc119, 0x247f, 0xc119, 0x21, 0 - .dw 0x24c0, 0xc119, 0x24ff, 0xc119, 0x21, 0 - .dw 0x2540, 0xc119, 0x257f, 0xc119, 0x21, 0 - .dw 0x25c0, 0xc119, 0x25ff, 0xc119, 0x21, 0 - .dw 0x2640, 0xc119, 0x267f, 0xc119, 0x21, 0 - .dw 0x26c0, 0xc119, 0x26ff, 0xc119, 0x21, 0 - .dw 0x2740, 0xc119, 0x277f, 0xc119, 0x21, 0 - .dw 0x27c0, 0xc119, 0x27ff, 0xc119, 0x21, 0 - .dw 0x2840, 0xc119, 0x287f, 0xc119, 0x21, 0 - .dw 0x28c0, 0xc119, 0x28ff, 0xc119, 0x21, 0 - .dw 0x2940, 0xc119, 0x297f, 0xc119, 0x21, 0 - .dw 0x29c0, 0xc119, 0x29ff, 0xc119, 0x21, 0 - .dw 0x2a40, 0xc119, 0x2a7f, 0xc119, 0x21, 0 - .dw 0x2ac0, 0xc119, 0x2aff, 0xc119, 0x21, 0 - .dw 0x2b40, 0xc119, 0x2b7f, 0xc119, 0x21, 0 - .dw 0x2bc0, 0xc119, 0x2bff, 0xc119, 0x21, 0 - .dw 0x2c40, 0xc119, 0x2c7f, 0xc119, 0x21, 0 - .dw 0x2cc0, 0xc119, 0x2cff, 0xc119, 0x21, 0 - .dw 0x2d40, 0xc119, 0x2d7f, 0xc119, 0x21, 0 - .dw 0x2dc0, 0xc119, 0x2dff, 0xc119, 0x21, 0 - .dw 0x2e40, 0xc119, 0x2e7f, 0xc119, 0x21, 0 - .dw 0x2ec0, 0xc119, 0x2eff, 0xc119, 0x21, 0 - .dw 0x2f40, 0xc119, 0x2f7f, 0xc119, 0x21, 0 - .dw 0x2fc0, 0xc119, 0x2fff, 0xc119, 0x21, 0 - .dw 0x3040, 0xc119, 0x307f, 0xc119, 0x21, 0 - .dw 0x30c0, 0xc119, 0x30ff, 0xc119, 0x21, 0 - .dw 0x3140, 0xc119, 0x317f, 0xc119, 0x21, 0 - .dw 0x31c0, 0xc119, 0x31ff, 0xc119, 0x21, 0 - .dw 0x3240, 0xc119, 0x327f, 0xc119, 0x21, 0 - .dw 0x32c0, 0xc119, 0x32ff, 0xc119, 0x21, 0 - .dw 0x3340, 0xc119, 0x337f, 0xc119, 0x21, 0 - .dw 0x33c0, 0xc119, 0x33ff, 0xc119, 0x21, 0 - .dw 0x3440, 0xc119, 0x347f, 0xc119, 0x21, 0 - .dw 0x34c0, 0xc119, 0x34ff, 0xc119, 0x21, 0 - .dw 0x3540, 0xc119, 0x357f, 0xc119, 0x21, 0 - .dw 0x35c0, 0xc119, 0x35ff, 0xc119, 0x21, 0 - .dw 0x3640, 0xc119, 0x367f, 0xc119, 0x21, 0 - .dw 0x36c0, 0xc119, 0x36ff, 0xc119, 0x21, 0 - .dw 0x3740, 0xc119, 0x377f, 0xc119, 0x21, 0 - .dw 0x37c0, 0xc119, 0x37ff, 0xc119, 0x21, 0 - .dw 0x3840, 0xc119, 0x387f, 0xc119, 0x21, 0 - .dw 0x38c0, 0xc119, 0x38ff, 0xc119, 0x21, 0 - .dw 0x3940, 0xc119, 0x397f, 0xc119, 0x21, 0 - .dw 0x39c0, 0xc119, 0x5fff, 0xc119, 0x21, 0 - .dw 0x6040, 0xc119, 0x607f, 0xc119, 0x21, 0 - .dw 0x60c0, 0xc119, 0x60ff, 0xc119, 0x21, 0 - .dw 0x6140, 0xc119, 0x617f, 0xc119, 0x21, 0 - .dw 0x61c0, 0xc119, 0x61ff, 0xc119, 0x21, 0 - .dw 0x6240, 0xc119, 0x627f, 0xc119, 0x21, 0 - .dw 0x62c0, 0xc119, 0x62ff, 0xc119, 0x21, 0 - .dw 0x6340, 0xc119, 0x637f, 0xc119, 0x21, 0 - .dw 0x63c0, 0xc119, 0x63ff, 0xc119, 0x21, 0 - .dw 0x6440, 0xc119, 0x647f, 0xc119, 0x21, 0 - .dw 0x64c0, 0xc119, 0x64ff, 0xc119, 0x21, 0 - .dw 0x6540, 0xc119, 0x657f, 0xc119, 0x21, 0 - .dw 0x65c0, 0xc119, 0x65ff, 0xc119, 0x21, 0 - .dw 0x6640, 0xc119, 0x667f, 0xc119, 0x21, 0 - .dw 0x66c0, 0xc119, 0x66ff, 0xc119, 0x21, 0 - .dw 0x6740, 0xc119, 0x677f, 0xc119, 0x21, 0 - .dw 0x67c0, 0xc119, 0x67ff, 0xc119, 0x21, 0 - .dw 0x6840, 0xc119, 0x687f, 0xc119, 0x21, 0 - .dw 0x68c0, 0xc119, 0x68ff, 0xc119, 0x21, 0 - .dw 0x6940, 0xc119, 0x697f, 0xc119, 0x21, 0 - .dw 0x69c0, 0xc119, 0x69ff, 0xc119, 0x21, 0 - .dw 0x6a40, 0xc119, 0x6a7f, 0xc119, 0x21, 0 - .dw 0x6ac0, 0xc119, 0x6aff, 0xc119, 0x21, 0 - .dw 0x6b40, 0xc119, 0x6b7f, 0xc119, 0x21, 0 - .dw 0x6bc0, 0xc119, 0x6bff, 0xc119, 0x21, 0 - .dw 0x6c40, 0xc119, 0x6c7f, 0xc119, 0x21, 0 - .dw 0x6cc0, 0xc119, 0x6cff, 0xc119, 0x21, 0 - .dw 0x6d40, 0xc119, 0x6d7f, 0xc119, 0x21, 0 - .dw 0x6dc0, 0xc119, 0x6dff, 0xc119, 0x21, 0 - .dw 0x6e40, 0xc119, 0x6e7f, 0xc119, 0x21, 0 - .dw 0x6ec0, 0xc119, 0x6eff, 0xc119, 0x21, 0 - .dw 0x6f40, 0xc119, 0x6f7f, 0xc119, 0x21, 0 - .dw 0x6fc0, 0xc119, 0x6fff, 0xc119, 0x21, 0 - .dw 0x7040, 0xc119, 0x707f, 0xc119, 0x21, 0 - .dw 0x70c0, 0xc119, 0x70ff, 0xc119, 0x21, 0 - .dw 0x7140, 0xc119, 0x717f, 0xc119, 0x21, 0 - .dw 0x71c0, 0xc119, 0x71ff, 0xc119, 0x21, 0 - .dw 0x7240, 0xc119, 0x727f, 0xc119, 0x21, 0 - .dw 0x72c0, 0xc119, 0x72ff, 0xc119, 0x21, 0 - .dw 0x7340, 0xc119, 0x737f, 0xc119, 0x21, 0 - .dw 0x73c0, 0xc119, 0x73ff, 0xc119, 0x21, 0 - .dw 0x7440, 0xc119, 0x747f, 0xc119, 0x21, 0 - .dw 0x74c0, 0xc119, 0x74ff, 0xc119, 0x21, 0 - .dw 0x7540, 0xc119, 0x757f, 0xc119, 0x21, 0 - .dw 0x75c0, 0xc119, 0x75ff, 0xc119, 0x21, 0 - .dw 0x7640, 0xc119, 0x767f, 0xc119, 0x21, 0 - .dw 0x76c0, 0xc119, 0x76ff, 0xc119, 0x21, 0 - .dw 0x7740, 0xc119, 0x777f, 0xc119, 0x21, 0 - .dw 0x77c0, 0xc119, 0x77ff, 0xc119, 0x21, 0 - .dw 0x7840, 0xc119, 0x787f, 0xc119, 0x21, 0 - .dw 0x78c0, 0xc119, 0x78ff, 0xc119, 0x21, 0 - .dw 0x7940, 0xc119, 0x797f, 0xc119, 0x21, 0 - .dw 0x79c0, 0xc119, 0x9fff, 0xc119, 0x21, 0 - .dw 0xa040, 0xc119, 0xa07f, 0xc119, 0x21, 0 - .dw 0xa0c0, 0xc119, 0xa0ff, 0xc119, 0x21, 0 - .dw 0xa140, 0xc119, 0xa17f, 0xc119, 0x21, 0 - .dw 0xa1c0, 0xc119, 0xa1ff, 0xc119, 0x21, 0 - .dw 0xa240, 0xc119, 0xa27f, 0xc119, 0x21, 0 - .dw 0xa2c0, 0xc119, 0xa2ff, 0xc119, 0x21, 0 - .dw 0xa340, 0xc119, 0xa37f, 0xc119, 0x21, 0 - .dw 0xa3c0, 0xc119, 0xa3ff, 0xc119, 0x21, 0 - .dw 0xa440, 0xc119, 0xa47f, 0xc119, 0x21, 0 - .dw 0xa4c0, 0xc119, 0xa4ff, 0xc119, 0x21, 0 - .dw 0xa540, 0xc119, 0xa57f, 0xc119, 0x21, 0 - .dw 0xa5c0, 0xc119, 0xa5ff, 0xc119, 0x21, 0 - .dw 0xa640, 0xc119, 0xa67f, 0xc119, 0x21, 0 - .dw 0xa6c0, 0xc119, 0xa6ff, 0xc119, 0x21, 0 - .dw 0xa740, 0xc119, 0xa77f, 0xc119, 0x21, 0 - .dw 0xa7c0, 0xc119, 0xa7ff, 0xc119, 0x21, 0 - .dw 0xa840, 0xc119, 0xa87f, 0xc119, 0x21, 0 - .dw 0xa8c0, 0xc119, 0xa8ff, 0xc119, 0x21, 0 - .dw 0xa940, 0xc119, 0xa97f, 0xc119, 0x21, 0 - .dw 0xa9c0, 0xc119, 0xa9ff, 0xc119, 0x21, 0 - .dw 0xaa40, 0xc119, 0xaa7f, 0xc119, 0x21, 0 - .dw 0xaac0, 0xc119, 0xaaff, 0xc119, 0x21, 0 - .dw 0xab40, 0xc119, 0xab7f, 0xc119, 0x21, 0 - .dw 0xabc0, 0xc119, 0xabff, 0xc119, 0x21, 0 - .dw 0xac40, 0xc119, 0xac7f, 0xc119, 0x21, 0 - .dw 0xacc0, 0xc119, 0xacff, 0xc119, 0x21, 0 - .dw 0xad40, 0xc119, 0xad7f, 0xc119, 0x21, 0 - .dw 0xadc0, 0xc119, 0xadff, 0xc119, 0x21, 0 - .dw 0xae40, 0xc119, 0xae7f, 0xc119, 0x21, 0 - .dw 0xaec0, 0xc119, 0xaeff, 0xc119, 0x21, 0 - .dw 0xaf40, 0xc119, 0xaf7f, 0xc119, 0x21, 0 - .dw 0xafc0, 0xc119, 0xafff, 0xc119, 0x21, 0 - .dw 0xb040, 0xc119, 0xb07f, 0xc119, 0x21, 0 - .dw 0xb0c0, 0xc119, 0xb0ff, 0xc119, 0x21, 0 - .dw 0xb140, 0xc119, 0xb17f, 0xc119, 0x21, 0 - .dw 0xb1c0, 0xc119, 0xb1ff, 0xc119, 0x21, 0 - .dw 0xb240, 0xc119, 0xb27f, 0xc119, 0x21, 0 - .dw 0xb2c0, 0xc119, 0xb2ff, 0xc119, 0x21, 0 - .dw 0xb340, 0xc119, 0xb37f, 0xc119, 0x21, 0 - .dw 0xb3c0, 0xc119, 0xb3ff, 0xc119, 0x21, 0 - .dw 0xb440, 0xc119, 0xb47f, 0xc119, 0x21, 0 - .dw 0xb4c0, 0xc119, 0xb4ff, 0xc119, 0x21, 0 - .dw 0xb540, 0xc119, 0xb57f, 0xc119, 0x21, 0 - .dw 0xb5c0, 0xc119, 0xb5ff, 0xc119, 0x21, 0 - .dw 0xb640, 0xc119, 0xb67f, 0xc119, 0x21, 0 - .dw 0xb6c0, 0xc119, 0xb6ff, 0xc119, 0x21, 0 - .dw 0xb740, 0xc119, 0xb77f, 0xc119, 0x21, 0 - .dw 0xb7c0, 0xc119, 0xb7ff, 0xc119, 0x21, 0 - .dw 0xb840, 0xc119, 0xb87f, 0xc119, 0x21, 0 - .dw 0xb8c0, 0xc119, 0xb8ff, 0xc119, 0x21, 0 - .dw 0xb940, 0xc119, 0xb97f, 0xc119, 0x21, 0 - .dw 0xb9c0, 0xc119, 0xdfff, 0xc119, 0x21, 0 - .dw 0xe040, 0xc119, 0xe07f, 0xc119, 0x21, 0 - .dw 0xe0c0, 0xc119, 0xe0ff, 0xc119, 0x21, 0 - .dw 0xe140, 0xc119, 0xe17f, 0xc119, 0x21, 0 - .dw 0xe1c0, 0xc119, 0xe1ff, 0xc119, 0x21, 0 - .dw 0xe240, 0xc119, 0xe27f, 0xc119, 0x21, 0 - .dw 0xe2c0, 0xc119, 0xe2ff, 0xc119, 0x21, 0 - .dw 0xe340, 0xc119, 0xe37f, 0xc119, 0x21, 0 - .dw 0xe3c0, 0xc119, 0xe3ff, 0xc119, 0x21, 0 - .dw 0xe440, 0xc119, 0xe47f, 0xc119, 0x21, 0 - .dw 0xe4c0, 0xc119, 0xe4ff, 0xc119, 0x21, 0 - .dw 0xe540, 0xc119, 0xe57f, 0xc119, 0x21, 0 - .dw 0xe5c0, 0xc119, 0xe5ff, 0xc119, 0x21, 0 - .dw 0xe640, 0xc119, 0xe67f, 0xc119, 0x21, 0 - .dw 0xe6c0, 0xc119, 0xe6ff, 0xc119, 0x21, 0 - .dw 0xe740, 0xc119, 0xe77f, 0xc119, 0x21, 0 - .dw 0xe7c0, 0xc119, 0xe7ff, 0xc119, 0x21, 0 - .dw 0xe840, 0xc119, 0xe87f, 0xc119, 0x21, 0 - .dw 0xe8c0, 0xc119, 0xe8ff, 0xc119, 0x21, 0 - .dw 0xe940, 0xc119, 0xe97f, 0xc119, 0x21, 0 - .dw 0xe9c0, 0xc119, 0xe9ff, 0xc119, 0x21, 0 - .dw 0xea40, 0xc119, 0xea7f, 0xc119, 0x21, 0 - .dw 0xeac0, 0xc119, 0xeaff, 0xc119, 0x21, 0 - .dw 0xeb40, 0xc119, 0xeb7f, 0xc119, 0x21, 0 - .dw 0xebc0, 0xc119, 0xebff, 0xc119, 0x21, 0 - .dw 0xec40, 0xc119, 0xec7f, 0xc119, 0x21, 0 - .dw 0xecc0, 0xc119, 0xecff, 0xc119, 0x21, 0 - .dw 0xed40, 0xc119, 0xed7f, 0xc119, 0x21, 0 - .dw 0xedc0, 0xc119, 0xedff, 0xc119, 0x21, 0 - .dw 0xee40, 0xc119, 0xee7f, 0xc119, 0x21, 0 - .dw 0xeec0, 0xc119, 0xeeff, 0xc119, 0x21, 0 - .dw 0xef40, 0xc119, 0xef7f, 0xc119, 0x21, 0 - .dw 0xefc0, 0xc119, 0xefff, 0xc119, 0x21, 0 - .dw 0xf040, 0xc119, 0xf07f, 0xc119, 0x21, 0 - .dw 0xf0c0, 0xc119, 0xf0ff, 0xc119, 0x21, 0 - .dw 0xf140, 0xc119, 0xf17f, 0xc119, 0x21, 0 - .dw 0xf1c0, 0xc119, 0xf1ff, 0xc119, 0x21, 0 - .dw 0xf240, 0xc119, 0xf27f, 0xc119, 0x21, 0 - .dw 0xf2c0, 0xc119, 0xf2ff, 0xc119, 0x21, 0 - .dw 0xf340, 0xc119, 0xf37f, 0xc119, 0x21, 0 - .dw 0xf3c0, 0xc119, 0xf3ff, 0xc119, 0x21, 0 - .dw 0xf440, 0xc119, 0xf47f, 0xc119, 0x21, 0 - .dw 0xf4c0, 0xc119, 0xf4ff, 0xc119, 0x21, 0 - .dw 0xf540, 0xc119, 0xf57f, 0xc119, 0x21, 0 - .dw 0xf5c0, 0xc119, 0xf5ff, 0xc119, 0x21, 0 - .dw 0xf640, 0xc119, 0xf67f, 0xc119, 0x21, 0 - .dw 0xf6c0, 0xc119, 0xf6ff, 0xc119, 0x21, 0 - .dw 0xf740, 0xc119, 0xf77f, 0xc119, 0x21, 0 - .dw 0xf7c0, 0xc119, 0xf7ff, 0xc119, 0x21, 0 - .dw 0xf840, 0xc119, 0xf87f, 0xc119, 0x21, 0 - .dw 0xf8c0, 0xc119, 0xf8ff, 0xc119, 0x21, 0 - .dw 0xf940, 0xc119, 0xf97f, 0xc119, 0x21, 0 - .dw 0xf9c0, 0xc119, 0x1fff, 0xc11a, 0x21, 0 - .dw 0x2040, 0xc11a, 0x207f, 0xc11a, 0x21, 0 - .dw 0x20c0, 0xc11a, 0x20ff, 0xc11a, 0x21, 0 - .dw 0x2140, 0xc11a, 0x217f, 0xc11a, 0x21, 0 - .dw 0x21c0, 0xc11a, 0x21ff, 0xc11a, 0x21, 0 - .dw 0x2240, 0xc11a, 0x227f, 0xc11a, 0x21, 0 - .dw 0x22c0, 0xc11a, 0x22ff, 0xc11a, 0x21, 0 - .dw 0x2340, 0xc11a, 0x237f, 0xc11a, 0x21, 0 - .dw 0x23c0, 0xc11a, 0x23ff, 0xc11a, 0x21, 0 - .dw 0x2440, 0xc11a, 0x247f, 0xc11a, 0x21, 0 - .dw 0x24c0, 0xc11a, 0x24ff, 0xc11a, 0x21, 0 - .dw 0x2540, 0xc11a, 0x257f, 0xc11a, 0x21, 0 - .dw 0x25c0, 0xc11a, 0x25ff, 0xc11a, 0x21, 0 - .dw 0x2640, 0xc11a, 0x267f, 0xc11a, 0x21, 0 - .dw 0x26c0, 0xc11a, 0x26ff, 0xc11a, 0x21, 0 - .dw 0x2740, 0xc11a, 0x277f, 0xc11a, 0x21, 0 - .dw 0x27c0, 0xc11a, 0x27ff, 0xc11a, 0x21, 0 - .dw 0x2840, 0xc11a, 0x287f, 0xc11a, 0x21, 0 - .dw 0x28c0, 0xc11a, 0x28ff, 0xc11a, 0x21, 0 - .dw 0x2940, 0xc11a, 0x297f, 0xc11a, 0x21, 0 - .dw 0x29c0, 0xc11a, 0x29ff, 0xc11a, 0x21, 0 - .dw 0x2a40, 0xc11a, 0x2a7f, 0xc11a, 0x21, 0 - .dw 0x2ac0, 0xc11a, 0x2aff, 0xc11a, 0x21, 0 - .dw 0x2b40, 0xc11a, 0x2b7f, 0xc11a, 0x21, 0 - .dw 0x2bc0, 0xc11a, 0x2bff, 0xc11a, 0x21, 0 - .dw 0x2c40, 0xc11a, 0x2c7f, 0xc11a, 0x21, 0 - .dw 0x2cc0, 0xc11a, 0x2cff, 0xc11a, 0x21, 0 - .dw 0x2d40, 0xc11a, 0x2d7f, 0xc11a, 0x21, 0 - .dw 0x2dc0, 0xc11a, 0x2dff, 0xc11a, 0x21, 0 - .dw 0x2e40, 0xc11a, 0x2e7f, 0xc11a, 0x21, 0 - .dw 0x2ec0, 0xc11a, 0x2eff, 0xc11a, 0x21, 0 - .dw 0x2f40, 0xc11a, 0x2f7f, 0xc11a, 0x21, 0 - .dw 0x2fc0, 0xc11a, 0x2fff, 0xc11a, 0x21, 0 - .dw 0x3040, 0xc11a, 0x307f, 0xc11a, 0x21, 0 - .dw 0x30c0, 0xc11a, 0x30ff, 0xc11a, 0x21, 0 - .dw 0x3140, 0xc11a, 0x317f, 0xc11a, 0x21, 0 - .dw 0x31c0, 0xc11a, 0x31ff, 0xc11a, 0x21, 0 - .dw 0x3240, 0xc11a, 0x327f, 0xc11a, 0x21, 0 - .dw 0x32c0, 0xc11a, 0x32ff, 0xc11a, 0x21, 0 - .dw 0x3340, 0xc11a, 0x337f, 0xc11a, 0x21, 0 - .dw 0x33c0, 0xc11a, 0x33ff, 0xc11a, 0x21, 0 - .dw 0x3440, 0xc11a, 0x347f, 0xc11a, 0x21, 0 - .dw 0x34c0, 0xc11a, 0x34ff, 0xc11a, 0x21, 0 - .dw 0x3540, 0xc11a, 0x357f, 0xc11a, 0x21, 0 - .dw 0x35c0, 0xc11a, 0x35ff, 0xc11a, 0x21, 0 - .dw 0x3640, 0xc11a, 0x367f, 0xc11a, 0x21, 0 - .dw 0x36c0, 0xc11a, 0x36ff, 0xc11a, 0x21, 0 - .dw 0x3740, 0xc11a, 0x377f, 0xc11a, 0x21, 0 - .dw 0x37c0, 0xc11a, 0x37ff, 0xc11a, 0x21, 0 - .dw 0x3840, 0xc11a, 0x387f, 0xc11a, 0x21, 0 - .dw 0x38c0, 0xc11a, 0x38ff, 0xc11a, 0x21, 0 - .dw 0x3940, 0xc11a, 0x397f, 0xc11a, 0x21, 0 - .dw 0x39c0, 0xc11a, 0x5fff, 0xc11a, 0x21, 0 - .dw 0x6040, 0xc11a, 0x607f, 0xc11a, 0x21, 0 - .dw 0x60c0, 0xc11a, 0x60ff, 0xc11a, 0x21, 0 - .dw 0x6140, 0xc11a, 0x617f, 0xc11a, 0x21, 0 - .dw 0x61c0, 0xc11a, 0x61ff, 0xc11a, 0x21, 0 - .dw 0x6240, 0xc11a, 0x627f, 0xc11a, 0x21, 0 - .dw 0x62c0, 0xc11a, 0x62ff, 0xc11a, 0x21, 0 - .dw 0x6340, 0xc11a, 0x637f, 0xc11a, 0x21, 0 - .dw 0x63c0, 0xc11a, 0x63ff, 0xc11a, 0x21, 0 - .dw 0x6440, 0xc11a, 0x647f, 0xc11a, 0x21, 0 - .dw 0x64c0, 0xc11a, 0x64ff, 0xc11a, 0x21, 0 - .dw 0x6540, 0xc11a, 0x657f, 0xc11a, 0x21, 0 - .dw 0x65c0, 0xc11a, 0x65ff, 0xc11a, 0x21, 0 - .dw 0x6640, 0xc11a, 0x667f, 0xc11a, 0x21, 0 - .dw 0x66c0, 0xc11a, 0x66ff, 0xc11a, 0x21, 0 - .dw 0x6740, 0xc11a, 0x677f, 0xc11a, 0x21, 0 - .dw 0x67c0, 0xc11a, 0x67ff, 0xc11a, 0x21, 0 - .dw 0x6840, 0xc11a, 0x687f, 0xc11a, 0x21, 0 - .dw 0x68c0, 0xc11a, 0x68ff, 0xc11a, 0x21, 0 - .dw 0x6940, 0xc11a, 0x697f, 0xc11a, 0x21, 0 - .dw 0x69c0, 0xc11a, 0x69ff, 0xc11a, 0x21, 0 - .dw 0x6a40, 0xc11a, 0x6a7f, 0xc11a, 0x21, 0 - .dw 0x6ac0, 0xc11a, 0x6aff, 0xc11a, 0x21, 0 - .dw 0x6b40, 0xc11a, 0x6b7f, 0xc11a, 0x21, 0 - .dw 0x6bc0, 0xc11a, 0x6bff, 0xc11a, 0x21, 0 - .dw 0x6c40, 0xc11a, 0x6c7f, 0xc11a, 0x21, 0 - .dw 0x6cc0, 0xc11a, 0x6cff, 0xc11a, 0x21, 0 - .dw 0x6d40, 0xc11a, 0x6d7f, 0xc11a, 0x21, 0 - .dw 0x6dc0, 0xc11a, 0x6dff, 0xc11a, 0x21, 0 - .dw 0x6e40, 0xc11a, 0x6e7f, 0xc11a, 0x21, 0 - .dw 0x6ec0, 0xc11a, 0x6eff, 0xc11a, 0x21, 0 - .dw 0x6f40, 0xc11a, 0x6f7f, 0xc11a, 0x21, 0 - .dw 0x6fc0, 0xc11a, 0x6fff, 0xc11a, 0x21, 0 - .dw 0x7040, 0xc11a, 0x707f, 0xc11a, 0x21, 0 - .dw 0x70c0, 0xc11a, 0x70ff, 0xc11a, 0x21, 0 - .dw 0x7140, 0xc11a, 0x717f, 0xc11a, 0x21, 0 - .dw 0x71c0, 0xc11a, 0x71ff, 0xc11a, 0x21, 0 - .dw 0x7240, 0xc11a, 0x727f, 0xc11a, 0x21, 0 - .dw 0x72c0, 0xc11a, 0x72ff, 0xc11a, 0x21, 0 - .dw 0x7340, 0xc11a, 0x737f, 0xc11a, 0x21, 0 - .dw 0x73c0, 0xc11a, 0x73ff, 0xc11a, 0x21, 0 - .dw 0x7440, 0xc11a, 0x747f, 0xc11a, 0x21, 0 - .dw 0x74c0, 0xc11a, 0x74ff, 0xc11a, 0x21, 0 - .dw 0x7540, 0xc11a, 0x757f, 0xc11a, 0x21, 0 - .dw 0x75c0, 0xc11a, 0x75ff, 0xc11a, 0x21, 0 - .dw 0x7640, 0xc11a, 0x767f, 0xc11a, 0x21, 0 - .dw 0x76c0, 0xc11a, 0x76ff, 0xc11a, 0x21, 0 - .dw 0x7740, 0xc11a, 0x777f, 0xc11a, 0x21, 0 - .dw 0x77c0, 0xc11a, 0x77ff, 0xc11a, 0x21, 0 - .dw 0x7840, 0xc11a, 0x787f, 0xc11a, 0x21, 0 - .dw 0x78c0, 0xc11a, 0x78ff, 0xc11a, 0x21, 0 - .dw 0x7940, 0xc11a, 0x797f, 0xc11a, 0x21, 0 - .dw 0x79c0, 0xc11a, 0x9fff, 0xc11a, 0x21, 0 - .dw 0xa040, 0xc11a, 0xa07f, 0xc11a, 0x21, 0 - .dw 0xa0c0, 0xc11a, 0xa0ff, 0xc11a, 0x21, 0 - .dw 0xa140, 0xc11a, 0xa17f, 0xc11a, 0x21, 0 - .dw 0xa1c0, 0xc11a, 0xa1ff, 0xc11a, 0x21, 0 - .dw 0xa240, 0xc11a, 0xa27f, 0xc11a, 0x21, 0 - .dw 0xa2c0, 0xc11a, 0xa2ff, 0xc11a, 0x21, 0 - .dw 0xa340, 0xc11a, 0xa37f, 0xc11a, 0x21, 0 - .dw 0xa3c0, 0xc11a, 0xa3ff, 0xc11a, 0x21, 0 - .dw 0xa440, 0xc11a, 0xa47f, 0xc11a, 0x21, 0 - .dw 0xa4c0, 0xc11a, 0xa4ff, 0xc11a, 0x21, 0 - .dw 0xa540, 0xc11a, 0xa57f, 0xc11a, 0x21, 0 - .dw 0xa5c0, 0xc11a, 0xa5ff, 0xc11a, 0x21, 0 - .dw 0xa640, 0xc11a, 0xa67f, 0xc11a, 0x21, 0 - .dw 0xa6c0, 0xc11a, 0xa6ff, 0xc11a, 0x21, 0 - .dw 0xa740, 0xc11a, 0xa77f, 0xc11a, 0x21, 0 - .dw 0xa7c0, 0xc11a, 0xa7ff, 0xc11a, 0x21, 0 - .dw 0xa840, 0xc11a, 0xa87f, 0xc11a, 0x21, 0 - .dw 0xa8c0, 0xc11a, 0xa8ff, 0xc11a, 0x21, 0 - .dw 0xa940, 0xc11a, 0xa97f, 0xc11a, 0x21, 0 - .dw 0xa9c0, 0xc11a, 0xa9ff, 0xc11a, 0x21, 0 - .dw 0xaa40, 0xc11a, 0xaa7f, 0xc11a, 0x21, 0 - .dw 0xaac0, 0xc11a, 0xaaff, 0xc11a, 0x21, 0 - .dw 0xab40, 0xc11a, 0xab7f, 0xc11a, 0x21, 0 - .dw 0xabc0, 0xc11a, 0xabff, 0xc11a, 0x21, 0 - .dw 0xac40, 0xc11a, 0xac7f, 0xc11a, 0x21, 0 - .dw 0xacc0, 0xc11a, 0xacff, 0xc11a, 0x21, 0 - .dw 0xad40, 0xc11a, 0xad7f, 0xc11a, 0x21, 0 - .dw 0xadc0, 0xc11a, 0xadff, 0xc11a, 0x21, 0 - .dw 0xae40, 0xc11a, 0xae7f, 0xc11a, 0x21, 0 - .dw 0xaec0, 0xc11a, 0xaeff, 0xc11a, 0x21, 0 - .dw 0xaf40, 0xc11a, 0xaf7f, 0xc11a, 0x21, 0 - .dw 0xafc0, 0xc11a, 0xafff, 0xc11a, 0x21, 0 - .dw 0xb040, 0xc11a, 0xb07f, 0xc11a, 0x21, 0 - .dw 0xb0c0, 0xc11a, 0xb0ff, 0xc11a, 0x21, 0 - .dw 0xb140, 0xc11a, 0xb17f, 0xc11a, 0x21, 0 - .dw 0xb1c0, 0xc11a, 0xb1ff, 0xc11a, 0x21, 0 - .dw 0xb240, 0xc11a, 0xb27f, 0xc11a, 0x21, 0 - .dw 0xb2c0, 0xc11a, 0xb2ff, 0xc11a, 0x21, 0 - .dw 0xb340, 0xc11a, 0xb37f, 0xc11a, 0x21, 0 - .dw 0xb3c0, 0xc11a, 0xb3ff, 0xc11a, 0x21, 0 - .dw 0xb440, 0xc11a, 0xb47f, 0xc11a, 0x21, 0 - .dw 0xb4c0, 0xc11a, 0xb4ff, 0xc11a, 0x21, 0 - .dw 0xb540, 0xc11a, 0xb57f, 0xc11a, 0x21, 0 - .dw 0xb5c0, 0xc11a, 0xb5ff, 0xc11a, 0x21, 0 - .dw 0xb640, 0xc11a, 0xb67f, 0xc11a, 0x21, 0 - .dw 0xb6c0, 0xc11a, 0xb6ff, 0xc11a, 0x21, 0 - .dw 0xb740, 0xc11a, 0xb77f, 0xc11a, 0x21, 0 - .dw 0xb7c0, 0xc11a, 0xb7ff, 0xc11a, 0x21, 0 - .dw 0xb840, 0xc11a, 0xb87f, 0xc11a, 0x21, 0 - .dw 0xb8c0, 0xc11a, 0xb8ff, 0xc11a, 0x21, 0 - .dw 0xb940, 0xc11a, 0xb97f, 0xc11a, 0x21, 0 - .dw 0xb9c0, 0xc11a, 0xdfff, 0xc11a, 0x21, 0 - .dw 0xe040, 0xc11a, 0xe07f, 0xc11a, 0x21, 0 - .dw 0xe0c0, 0xc11a, 0xe0ff, 0xc11a, 0x21, 0 - .dw 0xe140, 0xc11a, 0xe17f, 0xc11a, 0x21, 0 - .dw 0xe1c0, 0xc11a, 0xe1ff, 0xc11a, 0x21, 0 - .dw 0xe240, 0xc11a, 0xe27f, 0xc11a, 0x21, 0 - .dw 0xe2c0, 0xc11a, 0xe2ff, 0xc11a, 0x21, 0 - .dw 0xe340, 0xc11a, 0xe37f, 0xc11a, 0x21, 0 - .dw 0xe3c0, 0xc11a, 0xe3ff, 0xc11a, 0x21, 0 - .dw 0xe440, 0xc11a, 0xe47f, 0xc11a, 0x21, 0 - .dw 0xe4c0, 0xc11a, 0xe4ff, 0xc11a, 0x21, 0 - .dw 0xe540, 0xc11a, 0xe57f, 0xc11a, 0x21, 0 - .dw 0xe5c0, 0xc11a, 0xe5ff, 0xc11a, 0x21, 0 - .dw 0xe640, 0xc11a, 0xe67f, 0xc11a, 0x21, 0 - .dw 0xe6c0, 0xc11a, 0xe6ff, 0xc11a, 0x21, 0 - .dw 0xe740, 0xc11a, 0xe77f, 0xc11a, 0x21, 0 - .dw 0xe7c0, 0xc11a, 0xe7ff, 0xc11a, 0x21, 0 - .dw 0xe840, 0xc11a, 0xe87f, 0xc11a, 0x21, 0 - .dw 0xe8c0, 0xc11a, 0xe8ff, 0xc11a, 0x21, 0 - .dw 0xe940, 0xc11a, 0xe97f, 0xc11a, 0x21, 0 - .dw 0xe9c0, 0xc11a, 0xe9ff, 0xc11a, 0x21, 0 - .dw 0xea40, 0xc11a, 0xea7f, 0xc11a, 0x21, 0 - .dw 0xeac0, 0xc11a, 0xeaff, 0xc11a, 0x21, 0 - .dw 0xeb40, 0xc11a, 0xeb7f, 0xc11a, 0x21, 0 - .dw 0xebc0, 0xc11a, 0xebff, 0xc11a, 0x21, 0 - .dw 0xec40, 0xc11a, 0xec7f, 0xc11a, 0x21, 0 - .dw 0xecc0, 0xc11a, 0xecff, 0xc11a, 0x21, 0 - .dw 0xed40, 0xc11a, 0xed7f, 0xc11a, 0x21, 0 - .dw 0xedc0, 0xc11a, 0xedff, 0xc11a, 0x21, 0 - .dw 0xee40, 0xc11a, 0xee7f, 0xc11a, 0x21, 0 - .dw 0xeec0, 0xc11a, 0xeeff, 0xc11a, 0x21, 0 - .dw 0xef40, 0xc11a, 0xef7f, 0xc11a, 0x21, 0 - .dw 0xefc0, 0xc11a, 0xefff, 0xc11a, 0x21, 0 - .dw 0xf040, 0xc11a, 0xf07f, 0xc11a, 0x21, 0 - .dw 0xf0c0, 0xc11a, 0xf0ff, 0xc11a, 0x21, 0 - .dw 0xf140, 0xc11a, 0xf17f, 0xc11a, 0x21, 0 - .dw 0xf1c0, 0xc11a, 0xf1ff, 0xc11a, 0x21, 0 - .dw 0xf240, 0xc11a, 0xf27f, 0xc11a, 0x21, 0 - .dw 0xf2c0, 0xc11a, 0xf2ff, 0xc11a, 0x21, 0 - .dw 0xf340, 0xc11a, 0xf37f, 0xc11a, 0x21, 0 - .dw 0xf3c0, 0xc11a, 0xf3ff, 0xc11a, 0x21, 0 - .dw 0xf440, 0xc11a, 0xf47f, 0xc11a, 0x21, 0 - .dw 0xf4c0, 0xc11a, 0xf4ff, 0xc11a, 0x21, 0 - .dw 0xf540, 0xc11a, 0xf57f, 0xc11a, 0x21, 0 - .dw 0xf5c0, 0xc11a, 0xf5ff, 0xc11a, 0x21, 0 - .dw 0xf640, 0xc11a, 0xf67f, 0xc11a, 0x21, 0 - .dw 0xf6c0, 0xc11a, 0xf6ff, 0xc11a, 0x21, 0 - .dw 0xf740, 0xc11a, 0xf77f, 0xc11a, 0x21, 0 - .dw 0xf7c0, 0xc11a, 0xf7ff, 0xc11a, 0x21, 0 - .dw 0xf840, 0xc11a, 0xf87f, 0xc11a, 0x21, 0 - .dw 0xf8c0, 0xc11a, 0xf8ff, 0xc11a, 0x21, 0 - .dw 0xf940, 0xc11a, 0xf97f, 0xc11a, 0x21, 0 - .dw 0xf9c0, 0xc11a, 0xffff, 0xc11b, 0x21, 0 - .dw 0x0040, 0xc11c, 0x007f, 0xc11c, 0x21, 0 - .dw 0x00c0, 0xc11c, 0x00ff, 0xc11c, 0x21, 0 - .dw 0x0140, 0xc11c, 0x017f, 0xc11c, 0x21, 0 - .dw 0x01c0, 0xc11c, 0x01ff, 0xc11c, 0x21, 0 - .dw 0x0240, 0xc11c, 0x027f, 0xc11c, 0x21, 0 - .dw 0x02c0, 0xc11c, 0x02ff, 0xc11c, 0x21, 0 - .dw 0x0340, 0xc11c, 0x037f, 0xc11c, 0x21, 0 - .dw 0x03c0, 0xc11c, 0x03ff, 0xc11c, 0x21, 0 - .dw 0x0440, 0xc11c, 0x047f, 0xc11c, 0x21, 0 - .dw 0x04c0, 0xc11c, 0x04ff, 0xc11c, 0x21, 0 - .dw 0x0540, 0xc11c, 0x057f, 0xc11c, 0x21, 0 - .dw 0x05c0, 0xc11c, 0x05ff, 0xc11c, 0x21, 0 - .dw 0x0640, 0xc11c, 0x067f, 0xc11c, 0x21, 0 - .dw 0x06c0, 0xc11c, 0x06ff, 0xc11c, 0x21, 0 - .dw 0x0740, 0xc11c, 0x077f, 0xc11c, 0x21, 0 - .dw 0x07c0, 0xc11c, 0x07ff, 0xc11c, 0x21, 0 - .dw 0x0840, 0xc11c, 0x087f, 0xc11c, 0x21, 0 - .dw 0x08c0, 0xc11c, 0x08ff, 0xc11c, 0x21, 0 - .dw 0x0940, 0xc11c, 0x097f, 0xc11c, 0x21, 0 - .dw 0x09c0, 0xc11c, 0x09ff, 0xc11c, 0x21, 0 - .dw 0x0a40, 0xc11c, 0x0a7f, 0xc11c, 0x21, 0 - .dw 0x0ac0, 0xc11c, 0x0aff, 0xc11c, 0x21, 0 - .dw 0x0b40, 0xc11c, 0x0b7f, 0xc11c, 0x21, 0 - .dw 0x0bc0, 0xc11c, 0x0bff, 0xc11c, 0x21, 0 - .dw 0x0c40, 0xc11c, 0x0c7f, 0xc11c, 0x21, 0 - .dw 0x0cc0, 0xc11c, 0x0cff, 0xc11c, 0x21, 0 - .dw 0x0d40, 0xc11c, 0x0d7f, 0xc11c, 0x21, 0 - .dw 0x0dc0, 0xc11c, 0x0dff, 0xc11c, 0x21, 0 - .dw 0x0e40, 0xc11c, 0x0e7f, 0xc11c, 0x21, 0 - .dw 0x0ec0, 0xc11c, 0x0eff, 0xc11c, 0x21, 0 - .dw 0x0f40, 0xc11c, 0x0f7f, 0xc11c, 0x21, 0 - .dw 0x0fc0, 0xc11c, 0x0fff, 0xc11c, 0x21, 0 - .dw 0x1040, 0xc11c, 0x107f, 0xc11c, 0x21, 0 - .dw 0x10c0, 0xc11c, 0x10ff, 0xc11c, 0x21, 0 - .dw 0x1140, 0xc11c, 0x117f, 0xc11c, 0x21, 0 - .dw 0x11c0, 0xc11c, 0x11ff, 0xc11c, 0x21, 0 - .dw 0x1240, 0xc11c, 0x127f, 0xc11c, 0x21, 0 - .dw 0x12c0, 0xc11c, 0x12ff, 0xc11c, 0x21, 0 - .dw 0x1340, 0xc11c, 0x137f, 0xc11c, 0x21, 0 - .dw 0x13c0, 0xc11c, 0x13ff, 0xc11c, 0x21, 0 - .dw 0x1440, 0xc11c, 0x147f, 0xc11c, 0x21, 0 - .dw 0x14c0, 0xc11c, 0x14ff, 0xc11c, 0x21, 0 - .dw 0x1540, 0xc11c, 0x157f, 0xc11c, 0x21, 0 - .dw 0x15c0, 0xc11c, 0x15ff, 0xc11c, 0x21, 0 - .dw 0x1640, 0xc11c, 0x167f, 0xc11c, 0x21, 0 - .dw 0x16c0, 0xc11c, 0x16ff, 0xc11c, 0x21, 0 - .dw 0x1740, 0xc11c, 0x177f, 0xc11c, 0x21, 0 - .dw 0x17c0, 0xc11c, 0x17ff, 0xc11c, 0x21, 0 - .dw 0x1840, 0xc11c, 0x187f, 0xc11c, 0x21, 0 - .dw 0x18c0, 0xc11c, 0x18ff, 0xc11c, 0x21, 0 - .dw 0x1940, 0xc11c, 0x197f, 0xc11c, 0x21, 0 - .dw 0x19c0, 0xc11c, 0x1fff, 0xc11c, 0x21, 0 - .dw 0x2040, 0xc11c, 0x207f, 0xc11c, 0x21, 0 - .dw 0x20c0, 0xc11c, 0x20ff, 0xc11c, 0x21, 0 - .dw 0x2140, 0xc11c, 0x217f, 0xc11c, 0x21, 0 - .dw 0x21c0, 0xc11c, 0x21ff, 0xc11c, 0x21, 0 - .dw 0x2240, 0xc11c, 0x227f, 0xc11c, 0x21, 0 - .dw 0x22c0, 0xc11c, 0x22ff, 0xc11c, 0x21, 0 - .dw 0x2340, 0xc11c, 0x237f, 0xc11c, 0x21, 0 - .dw 0x23c0, 0xc11c, 0x23ff, 0xc11c, 0x21, 0 - .dw 0x2440, 0xc11c, 0x247f, 0xc11c, 0x21, 0 - .dw 0x24c0, 0xc11c, 0x24ff, 0xc11c, 0x21, 0 - .dw 0x2540, 0xc11c, 0x257f, 0xc11c, 0x21, 0 - .dw 0x25c0, 0xc11c, 0x25ff, 0xc11c, 0x21, 0 - .dw 0x2640, 0xc11c, 0x267f, 0xc11c, 0x21, 0 - .dw 0x26c0, 0xc11c, 0x26ff, 0xc11c, 0x21, 0 - .dw 0x2740, 0xc11c, 0x277f, 0xc11c, 0x21, 0 - .dw 0x27c0, 0xc11c, 0x27ff, 0xc11c, 0x21, 0 - .dw 0x2840, 0xc11c, 0x287f, 0xc11c, 0x21, 0 - .dw 0x28c0, 0xc11c, 0x28ff, 0xc11c, 0x21, 0 - .dw 0x2940, 0xc11c, 0x297f, 0xc11c, 0x21, 0 - .dw 0x29c0, 0xc11c, 0x29ff, 0xc11c, 0x21, 0 - .dw 0x2a40, 0xc11c, 0x2a7f, 0xc11c, 0x21, 0 - .dw 0x2ac0, 0xc11c, 0x2aff, 0xc11c, 0x21, 0 - .dw 0x2b40, 0xc11c, 0x2b7f, 0xc11c, 0x21, 0 - .dw 0x2bc0, 0xc11c, 0x2bff, 0xc11c, 0x21, 0 - .dw 0x2c40, 0xc11c, 0x2c7f, 0xc11c, 0x21, 0 - .dw 0x2cc0, 0xc11c, 0x2cff, 0xc11c, 0x21, 0 - .dw 0x2d40, 0xc11c, 0x2d7f, 0xc11c, 0x21, 0 - .dw 0x2dc0, 0xc11c, 0x2dff, 0xc11c, 0x21, 0 - .dw 0x2e40, 0xc11c, 0x2e7f, 0xc11c, 0x21, 0 - .dw 0x2ec0, 0xc11c, 0x2eff, 0xc11c, 0x21, 0 - .dw 0x2f40, 0xc11c, 0x2f7f, 0xc11c, 0x21, 0 - .dw 0x2fc0, 0xc11c, 0x2fff, 0xc11c, 0x21, 0 - .dw 0x3040, 0xc11c, 0x307f, 0xc11c, 0x21, 0 - .dw 0x30c0, 0xc11c, 0x30ff, 0xc11c, 0x21, 0 - .dw 0x3140, 0xc11c, 0x317f, 0xc11c, 0x21, 0 - .dw 0x31c0, 0xc11c, 0x31ff, 0xc11c, 0x21, 0 - .dw 0x3240, 0xc11c, 0x327f, 0xc11c, 0x21, 0 - .dw 0x32c0, 0xc11c, 0x32ff, 0xc11c, 0x21, 0 - .dw 0x3340, 0xc11c, 0x337f, 0xc11c, 0x21, 0 - .dw 0x33c0, 0xc11c, 0x33ff, 0xc11c, 0x21, 0 - .dw 0x3440, 0xc11c, 0x347f, 0xc11c, 0x21, 0 - .dw 0x34c0, 0xc11c, 0x34ff, 0xc11c, 0x21, 0 - .dw 0x3540, 0xc11c, 0x357f, 0xc11c, 0x21, 0 - .dw 0x35c0, 0xc11c, 0x35ff, 0xc11c, 0x21, 0 - .dw 0x3640, 0xc11c, 0x367f, 0xc11c, 0x21, 0 - .dw 0x36c0, 0xc11c, 0x36ff, 0xc11c, 0x21, 0 - .dw 0x3740, 0xc11c, 0x377f, 0xc11c, 0x21, 0 - .dw 0x37c0, 0xc11c, 0x37ff, 0xc11c, 0x21, 0 - .dw 0x3840, 0xc11c, 0x387f, 0xc11c, 0x21, 0 - .dw 0x38c0, 0xc11c, 0x38ff, 0xc11c, 0x21, 0 - .dw 0x3940, 0xc11c, 0x397f, 0xc11c, 0x21, 0 - .dw 0x39c0, 0xc11c, 0x3fff, 0xc11c, 0x21, 0 - .dw 0x4040, 0xc11c, 0x407f, 0xc11c, 0x21, 0 - .dw 0x40c0, 0xc11c, 0x40ff, 0xc11c, 0x21, 0 - .dw 0x4140, 0xc11c, 0x417f, 0xc11c, 0x21, 0 - .dw 0x41c0, 0xc11c, 0x41ff, 0xc11c, 0x21, 0 - .dw 0x4240, 0xc11c, 0x427f, 0xc11c, 0x21, 0 - .dw 0x42c0, 0xc11c, 0x42ff, 0xc11c, 0x21, 0 - .dw 0x4340, 0xc11c, 0x437f, 0xc11c, 0x21, 0 - .dw 0x43c0, 0xc11c, 0x43ff, 0xc11c, 0x21, 0 - .dw 0x4440, 0xc11c, 0x447f, 0xc11c, 0x21, 0 - .dw 0x44c0, 0xc11c, 0x44ff, 0xc11c, 0x21, 0 - .dw 0x4540, 0xc11c, 0x457f, 0xc11c, 0x21, 0 - .dw 0x45c0, 0xc11c, 0x45ff, 0xc11c, 0x21, 0 - .dw 0x4640, 0xc11c, 0x467f, 0xc11c, 0x21, 0 - .dw 0x46c0, 0xc11c, 0x46ff, 0xc11c, 0x21, 0 - .dw 0x4740, 0xc11c, 0x477f, 0xc11c, 0x21, 0 - .dw 0x47c0, 0xc11c, 0x47ff, 0xc11c, 0x21, 0 - .dw 0x4840, 0xc11c, 0x487f, 0xc11c, 0x21, 0 - .dw 0x48c0, 0xc11c, 0x48ff, 0xc11c, 0x21, 0 - .dw 0x4940, 0xc11c, 0x497f, 0xc11c, 0x21, 0 - .dw 0x49c0, 0xc11c, 0x49ff, 0xc11c, 0x21, 0 - .dw 0x4a40, 0xc11c, 0x4a7f, 0xc11c, 0x21, 0 - .dw 0x4ac0, 0xc11c, 0x4aff, 0xc11c, 0x21, 0 - .dw 0x4b40, 0xc11c, 0x4b7f, 0xc11c, 0x21, 0 - .dw 0x4bc0, 0xc11c, 0x4bff, 0xc11c, 0x21, 0 - .dw 0x4c40, 0xc11c, 0x4c7f, 0xc11c, 0x21, 0 - .dw 0x4cc0, 0xc11c, 0x4cff, 0xc11c, 0x21, 0 - .dw 0x4d40, 0xc11c, 0x4d7f, 0xc11c, 0x21, 0 - .dw 0x4dc0, 0xc11c, 0x4dff, 0xc11c, 0x21, 0 - .dw 0x4e40, 0xc11c, 0x4e7f, 0xc11c, 0x21, 0 - .dw 0x4ec0, 0xc11c, 0x4eff, 0xc11c, 0x21, 0 - .dw 0x4f40, 0xc11c, 0x4f7f, 0xc11c, 0x21, 0 - .dw 0x4fc0, 0xc11c, 0x4fff, 0xc11c, 0x21, 0 - .dw 0x5040, 0xc11c, 0x507f, 0xc11c, 0x21, 0 - .dw 0x50c0, 0xc11c, 0x50ff, 0xc11c, 0x21, 0 - .dw 0x5140, 0xc11c, 0x517f, 0xc11c, 0x21, 0 - .dw 0x51c0, 0xc11c, 0x51ff, 0xc11c, 0x21, 0 - .dw 0x5240, 0xc11c, 0x527f, 0xc11c, 0x21, 0 - .dw 0x52c0, 0xc11c, 0x52ff, 0xc11c, 0x21, 0 - .dw 0x5340, 0xc11c, 0x537f, 0xc11c, 0x21, 0 - .dw 0x53c0, 0xc11c, 0x53ff, 0xc11c, 0x21, 0 - .dw 0x5440, 0xc11c, 0x547f, 0xc11c, 0x21, 0 - .dw 0x54c0, 0xc11c, 0x54ff, 0xc11c, 0x21, 0 - .dw 0x5540, 0xc11c, 0x557f, 0xc11c, 0x21, 0 - .dw 0x55c0, 0xc11c, 0x55ff, 0xc11c, 0x21, 0 - .dw 0x5640, 0xc11c, 0x567f, 0xc11c, 0x21, 0 - .dw 0x56c0, 0xc11c, 0x56ff, 0xc11c, 0x21, 0 - .dw 0x5740, 0xc11c, 0x577f, 0xc11c, 0x21, 0 - .dw 0x57c0, 0xc11c, 0x57ff, 0xc11c, 0x21, 0 - .dw 0x5840, 0xc11c, 0x587f, 0xc11c, 0x21, 0 - .dw 0x58c0, 0xc11c, 0x58ff, 0xc11c, 0x21, 0 - .dw 0x5940, 0xc11c, 0x597f, 0xc11c, 0x21, 0 - .dw 0x59c0, 0xc11c, 0x5fff, 0xc11c, 0x21, 0 - .dw 0x6040, 0xc11c, 0x607f, 0xc11c, 0x21, 0 - .dw 0x60c0, 0xc11c, 0x60ff, 0xc11c, 0x21, 0 - .dw 0x6140, 0xc11c, 0x617f, 0xc11c, 0x21, 0 - .dw 0x61c0, 0xc11c, 0x61ff, 0xc11c, 0x21, 0 - .dw 0x6240, 0xc11c, 0x627f, 0xc11c, 0x21, 0 - .dw 0x62c0, 0xc11c, 0x62ff, 0xc11c, 0x21, 0 - .dw 0x6340, 0xc11c, 0x637f, 0xc11c, 0x21, 0 - .dw 0x63c0, 0xc11c, 0x63ff, 0xc11c, 0x21, 0 - .dw 0x6440, 0xc11c, 0x647f, 0xc11c, 0x21, 0 - .dw 0x64c0, 0xc11c, 0x64ff, 0xc11c, 0x21, 0 - .dw 0x6540, 0xc11c, 0x657f, 0xc11c, 0x21, 0 - .dw 0x65c0, 0xc11c, 0x65ff, 0xc11c, 0x21, 0 - .dw 0x6640, 0xc11c, 0x667f, 0xc11c, 0x21, 0 - .dw 0x66c0, 0xc11c, 0x66ff, 0xc11c, 0x21, 0 - .dw 0x6740, 0xc11c, 0x677f, 0xc11c, 0x21, 0 - .dw 0x67c0, 0xc11c, 0x67ff, 0xc11c, 0x21, 0 - .dw 0x6840, 0xc11c, 0x687f, 0xc11c, 0x21, 0 - .dw 0x68c0, 0xc11c, 0x68ff, 0xc11c, 0x21, 0 - .dw 0x6940, 0xc11c, 0x697f, 0xc11c, 0x21, 0 - .dw 0x69c0, 0xc11c, 0x69ff, 0xc11c, 0x21, 0 - .dw 0x6a40, 0xc11c, 0x6a7f, 0xc11c, 0x21, 0 - .dw 0x6ac0, 0xc11c, 0x6aff, 0xc11c, 0x21, 0 - .dw 0x6b40, 0xc11c, 0x6b7f, 0xc11c, 0x21, 0 - .dw 0x6bc0, 0xc11c, 0x6bff, 0xc11c, 0x21, 0 - .dw 0x6c40, 0xc11c, 0x6c7f, 0xc11c, 0x21, 0 - .dw 0x6cc0, 0xc11c, 0x6cff, 0xc11c, 0x21, 0 - .dw 0x6d40, 0xc11c, 0x6d7f, 0xc11c, 0x21, 0 - .dw 0x6dc0, 0xc11c, 0x6dff, 0xc11c, 0x21, 0 - .dw 0x6e40, 0xc11c, 0x6e7f, 0xc11c, 0x21, 0 - .dw 0x6ec0, 0xc11c, 0x6eff, 0xc11c, 0x21, 0 - .dw 0x6f40, 0xc11c, 0x6f7f, 0xc11c, 0x21, 0 - .dw 0x6fc0, 0xc11c, 0x6fff, 0xc11c, 0x21, 0 - .dw 0x7040, 0xc11c, 0x707f, 0xc11c, 0x21, 0 - .dw 0x70c0, 0xc11c, 0x70ff, 0xc11c, 0x21, 0 - .dw 0x7140, 0xc11c, 0x717f, 0xc11c, 0x21, 0 - .dw 0x71c0, 0xc11c, 0x71ff, 0xc11c, 0x21, 0 - .dw 0x7240, 0xc11c, 0x727f, 0xc11c, 0x21, 0 - .dw 0x72c0, 0xc11c, 0x72ff, 0xc11c, 0x21, 0 - .dw 0x7340, 0xc11c, 0x737f, 0xc11c, 0x21, 0 - .dw 0x73c0, 0xc11c, 0x73ff, 0xc11c, 0x21, 0 - .dw 0x7440, 0xc11c, 0x747f, 0xc11c, 0x21, 0 - .dw 0x74c0, 0xc11c, 0x74ff, 0xc11c, 0x21, 0 - .dw 0x7540, 0xc11c, 0x757f, 0xc11c, 0x21, 0 - .dw 0x75c0, 0xc11c, 0x75ff, 0xc11c, 0x21, 0 - .dw 0x7640, 0xc11c, 0x767f, 0xc11c, 0x21, 0 - .dw 0x76c0, 0xc11c, 0x76ff, 0xc11c, 0x21, 0 - .dw 0x7740, 0xc11c, 0x777f, 0xc11c, 0x21, 0 - .dw 0x77c0, 0xc11c, 0x77ff, 0xc11c, 0x21, 0 - .dw 0x7840, 0xc11c, 0x787f, 0xc11c, 0x21, 0 - .dw 0x78c0, 0xc11c, 0x78ff, 0xc11c, 0x21, 0 - .dw 0x7940, 0xc11c, 0x797f, 0xc11c, 0x21, 0 - .dw 0x79c0, 0xc11c, 0x7fff, 0xc11c, 0x21, 0 - .dw 0x8040, 0xc11c, 0x807f, 0xc11c, 0x21, 0 - .dw 0x80c0, 0xc11c, 0x80ff, 0xc11c, 0x21, 0 - .dw 0x8140, 0xc11c, 0x817f, 0xc11c, 0x21, 0 - .dw 0x81c0, 0xc11c, 0x81ff, 0xc11c, 0x21, 0 - .dw 0x8240, 0xc11c, 0x827f, 0xc11c, 0x21, 0 - .dw 0x82c0, 0xc11c, 0x82ff, 0xc11c, 0x21, 0 - .dw 0x8340, 0xc11c, 0x837f, 0xc11c, 0x21, 0 - .dw 0x83c0, 0xc11c, 0x83ff, 0xc11c, 0x21, 0 - .dw 0x8440, 0xc11c, 0x847f, 0xc11c, 0x21, 0 - .dw 0x84c0, 0xc11c, 0x84ff, 0xc11c, 0x21, 0 - .dw 0x8540, 0xc11c, 0x857f, 0xc11c, 0x21, 0 - .dw 0x85c0, 0xc11c, 0x85ff, 0xc11c, 0x21, 0 - .dw 0x8640, 0xc11c, 0x867f, 0xc11c, 0x21, 0 - .dw 0x86c0, 0xc11c, 0x86ff, 0xc11c, 0x21, 0 - .dw 0x8740, 0xc11c, 0x877f, 0xc11c, 0x21, 0 - .dw 0x87c0, 0xc11c, 0x87ff, 0xc11c, 0x21, 0 - .dw 0x8840, 0xc11c, 0x887f, 0xc11c, 0x21, 0 - .dw 0x88c0, 0xc11c, 0x88ff, 0xc11c, 0x21, 0 - .dw 0x8940, 0xc11c, 0x897f, 0xc11c, 0x21, 0 - .dw 0x89c0, 0xc11c, 0x89ff, 0xc11c, 0x21, 0 - .dw 0x8a40, 0xc11c, 0x8a7f, 0xc11c, 0x21, 0 - .dw 0x8ac0, 0xc11c, 0x8aff, 0xc11c, 0x21, 0 - .dw 0x8b40, 0xc11c, 0x8b7f, 0xc11c, 0x21, 0 - .dw 0x8bc0, 0xc11c, 0x8bff, 0xc11c, 0x21, 0 - .dw 0x8c40, 0xc11c, 0x8c7f, 0xc11c, 0x21, 0 - .dw 0x8cc0, 0xc11c, 0x8cff, 0xc11c, 0x21, 0 - .dw 0x8d40, 0xc11c, 0x8d7f, 0xc11c, 0x21, 0 - .dw 0x8dc0, 0xc11c, 0x8dff, 0xc11c, 0x21, 0 - .dw 0x8e40, 0xc11c, 0x8e7f, 0xc11c, 0x21, 0 - .dw 0x8ec0, 0xc11c, 0x8eff, 0xc11c, 0x21, 0 - .dw 0x8f40, 0xc11c, 0x8f7f, 0xc11c, 0x21, 0 - .dw 0x8fc0, 0xc11c, 0x8fff, 0xc11c, 0x21, 0 - .dw 0x9040, 0xc11c, 0x907f, 0xc11c, 0x21, 0 - .dw 0x90c0, 0xc11c, 0x90ff, 0xc11c, 0x21, 0 - .dw 0x9140, 0xc11c, 0x917f, 0xc11c, 0x21, 0 - .dw 0x91c0, 0xc11c, 0x91ff, 0xc11c, 0x21, 0 - .dw 0x9240, 0xc11c, 0x927f, 0xc11c, 0x21, 0 - .dw 0x92c0, 0xc11c, 0x92ff, 0xc11c, 0x21, 0 - .dw 0x9340, 0xc11c, 0x937f, 0xc11c, 0x21, 0 - .dw 0x93c0, 0xc11c, 0x93ff, 0xc11c, 0x21, 0 - .dw 0x9440, 0xc11c, 0x947f, 0xc11c, 0x21, 0 - .dw 0x94c0, 0xc11c, 0x94ff, 0xc11c, 0x21, 0 - .dw 0x9540, 0xc11c, 0x957f, 0xc11c, 0x21, 0 - .dw 0x95c0, 0xc11c, 0x95ff, 0xc11c, 0x21, 0 - .dw 0x9640, 0xc11c, 0x967f, 0xc11c, 0x21, 0 - .dw 0x96c0, 0xc11c, 0x96ff, 0xc11c, 0x21, 0 - .dw 0x9740, 0xc11c, 0x977f, 0xc11c, 0x21, 0 - .dw 0x97c0, 0xc11c, 0x97ff, 0xc11c, 0x21, 0 - .dw 0x9840, 0xc11c, 0x987f, 0xc11c, 0x21, 0 - .dw 0x98c0, 0xc11c, 0x98ff, 0xc11c, 0x21, 0 - .dw 0x9940, 0xc11c, 0x997f, 0xc11c, 0x21, 0 - .dw 0x99c0, 0xc11c, 0x9fff, 0xc11c, 0x21, 0 - .dw 0xa040, 0xc11c, 0xa07f, 0xc11c, 0x21, 0 - .dw 0xa0c0, 0xc11c, 0xa0ff, 0xc11c, 0x21, 0 - .dw 0xa140, 0xc11c, 0xa17f, 0xc11c, 0x21, 0 - .dw 0xa1c0, 0xc11c, 0xa1ff, 0xc11c, 0x21, 0 - .dw 0xa240, 0xc11c, 0xa27f, 0xc11c, 0x21, 0 - .dw 0xa2c0, 0xc11c, 0xa2ff, 0xc11c, 0x21, 0 - .dw 0xa340, 0xc11c, 0xa37f, 0xc11c, 0x21, 0 - .dw 0xa3c0, 0xc11c, 0xa3ff, 0xc11c, 0x21, 0 - .dw 0xa440, 0xc11c, 0xa47f, 0xc11c, 0x21, 0 - .dw 0xa4c0, 0xc11c, 0xa4ff, 0xc11c, 0x21, 0 - .dw 0xa540, 0xc11c, 0xa57f, 0xc11c, 0x21, 0 - .dw 0xa5c0, 0xc11c, 0xa5ff, 0xc11c, 0x21, 0 - .dw 0xa640, 0xc11c, 0xa67f, 0xc11c, 0x21, 0 - .dw 0xa6c0, 0xc11c, 0xa6ff, 0xc11c, 0x21, 0 - .dw 0xa740, 0xc11c, 0xa77f, 0xc11c, 0x21, 0 - .dw 0xa7c0, 0xc11c, 0xa7ff, 0xc11c, 0x21, 0 - .dw 0xa840, 0xc11c, 0xa87f, 0xc11c, 0x21, 0 - .dw 0xa8c0, 0xc11c, 0xa8ff, 0xc11c, 0x21, 0 - .dw 0xa940, 0xc11c, 0xa97f, 0xc11c, 0x21, 0 - .dw 0xa9c0, 0xc11c, 0xa9ff, 0xc11c, 0x21, 0 - .dw 0xaa40, 0xc11c, 0xaa7f, 0xc11c, 0x21, 0 - .dw 0xaac0, 0xc11c, 0xaaff, 0xc11c, 0x21, 0 - .dw 0xab40, 0xc11c, 0xab7f, 0xc11c, 0x21, 0 - .dw 0xabc0, 0xc11c, 0xabff, 0xc11c, 0x21, 0 - .dw 0xac40, 0xc11c, 0xac7f, 0xc11c, 0x21, 0 - .dw 0xacc0, 0xc11c, 0xacff, 0xc11c, 0x21, 0 - .dw 0xad40, 0xc11c, 0xad7f, 0xc11c, 0x21, 0 - .dw 0xadc0, 0xc11c, 0xadff, 0xc11c, 0x21, 0 - .dw 0xae40, 0xc11c, 0xae7f, 0xc11c, 0x21, 0 - .dw 0xaec0, 0xc11c, 0xaeff, 0xc11c, 0x21, 0 - .dw 0xaf40, 0xc11c, 0xaf7f, 0xc11c, 0x21, 0 - .dw 0xafc0, 0xc11c, 0xafff, 0xc11c, 0x21, 0 - .dw 0xb040, 0xc11c, 0xb07f, 0xc11c, 0x21, 0 - .dw 0xb0c0, 0xc11c, 0xb0ff, 0xc11c, 0x21, 0 - .dw 0xb140, 0xc11c, 0xb17f, 0xc11c, 0x21, 0 - .dw 0xb1c0, 0xc11c, 0xb1ff, 0xc11c, 0x21, 0 - .dw 0xb240, 0xc11c, 0xb27f, 0xc11c, 0x21, 0 - .dw 0xb2c0, 0xc11c, 0xb2ff, 0xc11c, 0x21, 0 - .dw 0xb340, 0xc11c, 0xb37f, 0xc11c, 0x21, 0 - .dw 0xb3c0, 0xc11c, 0xb3ff, 0xc11c, 0x21, 0 - .dw 0xb440, 0xc11c, 0xb47f, 0xc11c, 0x21, 0 - .dw 0xb4c0, 0xc11c, 0xb4ff, 0xc11c, 0x21, 0 - .dw 0xb540, 0xc11c, 0xb57f, 0xc11c, 0x21, 0 - .dw 0xb5c0, 0xc11c, 0xb5ff, 0xc11c, 0x21, 0 - .dw 0xb640, 0xc11c, 0xb67f, 0xc11c, 0x21, 0 - .dw 0xb6c0, 0xc11c, 0xb6ff, 0xc11c, 0x21, 0 - .dw 0xb740, 0xc11c, 0xb77f, 0xc11c, 0x21, 0 - .dw 0xb7c0, 0xc11c, 0xb7ff, 0xc11c, 0x21, 0 - .dw 0xb840, 0xc11c, 0xb87f, 0xc11c, 0x21, 0 - .dw 0xb8c0, 0xc11c, 0xb8ff, 0xc11c, 0x21, 0 - .dw 0xb940, 0xc11c, 0xb97f, 0xc11c, 0x21, 0 - .dw 0xb9c0, 0xc11c, 0xbfff, 0xc11c, 0x21, 0 - .dw 0xc040, 0xc11c, 0xc07f, 0xc11c, 0x21, 0 - .dw 0xc0c0, 0xc11c, 0xc0ff, 0xc11c, 0x21, 0 - .dw 0xc140, 0xc11c, 0xc17f, 0xc11c, 0x21, 0 - .dw 0xc1c0, 0xc11c, 0xc1ff, 0xc11c, 0x21, 0 - .dw 0xc240, 0xc11c, 0xc27f, 0xc11c, 0x21, 0 - .dw 0xc2c0, 0xc11c, 0xc2ff, 0xc11c, 0x21, 0 - .dw 0xc340, 0xc11c, 0xc37f, 0xc11c, 0x21, 0 - .dw 0xc3c0, 0xc11c, 0xc3ff, 0xc11c, 0x21, 0 - .dw 0xc440, 0xc11c, 0xc47f, 0xc11c, 0x21, 0 - .dw 0xc4c0, 0xc11c, 0xc4ff, 0xc11c, 0x21, 0 - .dw 0xc540, 0xc11c, 0xc57f, 0xc11c, 0x21, 0 - .dw 0xc5c0, 0xc11c, 0xc5ff, 0xc11c, 0x21, 0 - .dw 0xc640, 0xc11c, 0xc67f, 0xc11c, 0x21, 0 - .dw 0xc6c0, 0xc11c, 0xc6ff, 0xc11c, 0x21, 0 - .dw 0xc740, 0xc11c, 0xc77f, 0xc11c, 0x21, 0 - .dw 0xc7c0, 0xc11c, 0xc7ff, 0xc11c, 0x21, 0 - .dw 0xc840, 0xc11c, 0xc87f, 0xc11c, 0x21, 0 - .dw 0xc8c0, 0xc11c, 0xc8ff, 0xc11c, 0x21, 0 - .dw 0xc940, 0xc11c, 0xc97f, 0xc11c, 0x21, 0 - .dw 0xc9c0, 0xc11c, 0xc9ff, 0xc11c, 0x21, 0 - .dw 0xca40, 0xc11c, 0xca7f, 0xc11c, 0x21, 0 - .dw 0xcac0, 0xc11c, 0xcaff, 0xc11c, 0x21, 0 - .dw 0xcb40, 0xc11c, 0xcb7f, 0xc11c, 0x21, 0 - .dw 0xcbc0, 0xc11c, 0xcbff, 0xc11c, 0x21, 0 - .dw 0xcc40, 0xc11c, 0xcc7f, 0xc11c, 0x21, 0 - .dw 0xccc0, 0xc11c, 0xccff, 0xc11c, 0x21, 0 - .dw 0xcd40, 0xc11c, 0xcd7f, 0xc11c, 0x21, 0 - .dw 0xcdc0, 0xc11c, 0xcdff, 0xc11c, 0x21, 0 - .dw 0xce40, 0xc11c, 0xce7f, 0xc11c, 0x21, 0 - .dw 0xcec0, 0xc11c, 0xceff, 0xc11c, 0x21, 0 - .dw 0xcf40, 0xc11c, 0xcf7f, 0xc11c, 0x21, 0 - .dw 0xcfc0, 0xc11c, 0xcfff, 0xc11c, 0x21, 0 - .dw 0xd040, 0xc11c, 0xd07f, 0xc11c, 0x21, 0 - .dw 0xd0c0, 0xc11c, 0xd0ff, 0xc11c, 0x21, 0 - .dw 0xd140, 0xc11c, 0xd17f, 0xc11c, 0x21, 0 - .dw 0xd1c0, 0xc11c, 0xd1ff, 0xc11c, 0x21, 0 - .dw 0xd240, 0xc11c, 0xd27f, 0xc11c, 0x21, 0 - .dw 0xd2c0, 0xc11c, 0xd2ff, 0xc11c, 0x21, 0 - .dw 0xd340, 0xc11c, 0xd37f, 0xc11c, 0x21, 0 - .dw 0xd3c0, 0xc11c, 0xd3ff, 0xc11c, 0x21, 0 - .dw 0xd440, 0xc11c, 0xd47f, 0xc11c, 0x21, 0 - .dw 0xd4c0, 0xc11c, 0xd4ff, 0xc11c, 0x21, 0 - .dw 0xd540, 0xc11c, 0xd57f, 0xc11c, 0x21, 0 - .dw 0xd5c0, 0xc11c, 0xd5ff, 0xc11c, 0x21, 0 - .dw 0xd640, 0xc11c, 0xd67f, 0xc11c, 0x21, 0 - .dw 0xd6c0, 0xc11c, 0xd6ff, 0xc11c, 0x21, 0 - .dw 0xd740, 0xc11c, 0xd77f, 0xc11c, 0x21, 0 - .dw 0xd7c0, 0xc11c, 0xd7ff, 0xc11c, 0x21, 0 - .dw 0xd840, 0xc11c, 0xd87f, 0xc11c, 0x21, 0 - .dw 0xd8c0, 0xc11c, 0xd8ff, 0xc11c, 0x21, 0 - .dw 0xd940, 0xc11c, 0xd97f, 0xc11c, 0x21, 0 - .dw 0xd9c0, 0xc11c, 0xdfff, 0xc11c, 0x21, 0 - .dw 0xe040, 0xc11c, 0xe07f, 0xc11c, 0x21, 0 - .dw 0xe0c0, 0xc11c, 0xe0ff, 0xc11c, 0x21, 0 - .dw 0xe140, 0xc11c, 0xe17f, 0xc11c, 0x21, 0 - .dw 0xe1c0, 0xc11c, 0xe1ff, 0xc11c, 0x21, 0 - .dw 0xe240, 0xc11c, 0xe27f, 0xc11c, 0x21, 0 - .dw 0xe2c0, 0xc11c, 0xe2ff, 0xc11c, 0x21, 0 - .dw 0xe340, 0xc11c, 0xe37f, 0xc11c, 0x21, 0 - .dw 0xe3c0, 0xc11c, 0xe3ff, 0xc11c, 0x21, 0 - .dw 0xe440, 0xc11c, 0xe47f, 0xc11c, 0x21, 0 - .dw 0xe4c0, 0xc11c, 0xe4ff, 0xc11c, 0x21, 0 - .dw 0xe540, 0xc11c, 0xe57f, 0xc11c, 0x21, 0 - .dw 0xe5c0, 0xc11c, 0xe5ff, 0xc11c, 0x21, 0 - .dw 0xe640, 0xc11c, 0xe67f, 0xc11c, 0x21, 0 - .dw 0xe6c0, 0xc11c, 0xe6ff, 0xc11c, 0x21, 0 - .dw 0xe740, 0xc11c, 0xe77f, 0xc11c, 0x21, 0 - .dw 0xe7c0, 0xc11c, 0xe7ff, 0xc11c, 0x21, 0 - .dw 0xe840, 0xc11c, 0xe87f, 0xc11c, 0x21, 0 - .dw 0xe8c0, 0xc11c, 0xe8ff, 0xc11c, 0x21, 0 - .dw 0xe940, 0xc11c, 0xe97f, 0xc11c, 0x21, 0 - .dw 0xe9c0, 0xc11c, 0xe9ff, 0xc11c, 0x21, 0 - .dw 0xea40, 0xc11c, 0xea7f, 0xc11c, 0x21, 0 - .dw 0xeac0, 0xc11c, 0xeaff, 0xc11c, 0x21, 0 - .dw 0xeb40, 0xc11c, 0xeb7f, 0xc11c, 0x21, 0 - .dw 0xebc0, 0xc11c, 0xebff, 0xc11c, 0x21, 0 - .dw 0xec40, 0xc11c, 0xec7f, 0xc11c, 0x21, 0 - .dw 0xecc0, 0xc11c, 0xecff, 0xc11c, 0x21, 0 - .dw 0xed40, 0xc11c, 0xed7f, 0xc11c, 0x21, 0 - .dw 0xedc0, 0xc11c, 0xedff, 0xc11c, 0x21, 0 - .dw 0xee40, 0xc11c, 0xee7f, 0xc11c, 0x21, 0 - .dw 0xeec0, 0xc11c, 0xeeff, 0xc11c, 0x21, 0 - .dw 0xef40, 0xc11c, 0xef7f, 0xc11c, 0x21, 0 - .dw 0xefc0, 0xc11c, 0xefff, 0xc11c, 0x21, 0 - .dw 0xf040, 0xc11c, 0xf07f, 0xc11c, 0x21, 0 - .dw 0xf0c0, 0xc11c, 0xf0ff, 0xc11c, 0x21, 0 - .dw 0xf140, 0xc11c, 0xf17f, 0xc11c, 0x21, 0 - .dw 0xf1c0, 0xc11c, 0xf1ff, 0xc11c, 0x21, 0 - .dw 0xf240, 0xc11c, 0xf27f, 0xc11c, 0x21, 0 - .dw 0xf2c0, 0xc11c, 0xf2ff, 0xc11c, 0x21, 0 - .dw 0xf340, 0xc11c, 0xf37f, 0xc11c, 0x21, 0 - .dw 0xf3c0, 0xc11c, 0xf3ff, 0xc11c, 0x21, 0 - .dw 0xf440, 0xc11c, 0xf47f, 0xc11c, 0x21, 0 - .dw 0xf4c0, 0xc11c, 0xf4ff, 0xc11c, 0x21, 0 - .dw 0xf540, 0xc11c, 0xf57f, 0xc11c, 0x21, 0 - .dw 0xf5c0, 0xc11c, 0xf5ff, 0xc11c, 0x21, 0 - .dw 0xf640, 0xc11c, 0xf67f, 0xc11c, 0x21, 0 - .dw 0xf6c0, 0xc11c, 0xf6ff, 0xc11c, 0x21, 0 - .dw 0xf740, 0xc11c, 0xf77f, 0xc11c, 0x21, 0 - .dw 0xf7c0, 0xc11c, 0xf7ff, 0xc11c, 0x21, 0 - .dw 0xf840, 0xc11c, 0xf87f, 0xc11c, 0x21, 0 - .dw 0xf8c0, 0xc11c, 0xf8ff, 0xc11c, 0x21, 0 - .dw 0xf940, 0xc11c, 0xf97f, 0xc11c, 0x21, 0 - .dw 0xf9c0, 0xc11c, 0xffff, 0xc11c, 0x21, 0 - .dw 0x0040, 0xc11d, 0x007f, 0xc11d, 0x21, 0 - .dw 0x00c0, 0xc11d, 0x00ff, 0xc11d, 0x21, 0 - .dw 0x0140, 0xc11d, 0x017f, 0xc11d, 0x21, 0 - .dw 0x01c0, 0xc11d, 0x01ff, 0xc11d, 0x21, 0 - .dw 0x0240, 0xc11d, 0x027f, 0xc11d, 0x21, 0 - .dw 0x02c0, 0xc11d, 0x02ff, 0xc11d, 0x21, 0 - .dw 0x0340, 0xc11d, 0x037f, 0xc11d, 0x21, 0 - .dw 0x03c0, 0xc11d, 0x03ff, 0xc11d, 0x21, 0 - .dw 0x0440, 0xc11d, 0x047f, 0xc11d, 0x21, 0 - .dw 0x04c0, 0xc11d, 0x04ff, 0xc11d, 0x21, 0 - .dw 0x0540, 0xc11d, 0x057f, 0xc11d, 0x21, 0 - .dw 0x05c0, 0xc11d, 0x05ff, 0xc11d, 0x21, 0 - .dw 0x0640, 0xc11d, 0x067f, 0xc11d, 0x21, 0 - .dw 0x06c0, 0xc11d, 0x06ff, 0xc11d, 0x21, 0 - .dw 0x0740, 0xc11d, 0x077f, 0xc11d, 0x21, 0 - .dw 0x07c0, 0xc11d, 0x07ff, 0xc11d, 0x21, 0 - .dw 0x0840, 0xc11d, 0x087f, 0xc11d, 0x21, 0 - .dw 0x08c0, 0xc11d, 0x08ff, 0xc11d, 0x21, 0 - .dw 0x0940, 0xc11d, 0x097f, 0xc11d, 0x21, 0 - .dw 0x09c0, 0xc11d, 0x09ff, 0xc11d, 0x21, 0 - .dw 0x0a40, 0xc11d, 0x0a7f, 0xc11d, 0x21, 0 - .dw 0x0ac0, 0xc11d, 0x0aff, 0xc11d, 0x21, 0 - .dw 0x0b40, 0xc11d, 0x0b7f, 0xc11d, 0x21, 0 - .dw 0x0bc0, 0xc11d, 0x0bff, 0xc11d, 0x21, 0 - .dw 0x0c40, 0xc11d, 0x0c7f, 0xc11d, 0x21, 0 - .dw 0x0cc0, 0xc11d, 0x0cff, 0xc11d, 0x21, 0 - .dw 0x0d40, 0xc11d, 0x0d7f, 0xc11d, 0x21, 0 - .dw 0x0dc0, 0xc11d, 0x0dff, 0xc11d, 0x21, 0 - .dw 0x0e40, 0xc11d, 0x0e7f, 0xc11d, 0x21, 0 - .dw 0x0ec0, 0xc11d, 0x0eff, 0xc11d, 0x21, 0 - .dw 0x0f40, 0xc11d, 0x0f7f, 0xc11d, 0x21, 0 - .dw 0x0fc0, 0xc11d, 0x0fff, 0xc11d, 0x21, 0 - .dw 0x1040, 0xc11d, 0x107f, 0xc11d, 0x21, 0 - .dw 0x10c0, 0xc11d, 0x10ff, 0xc11d, 0x21, 0 - .dw 0x1140, 0xc11d, 0x117f, 0xc11d, 0x21, 0 - .dw 0x11c0, 0xc11d, 0x11ff, 0xc11d, 0x21, 0 - .dw 0x1240, 0xc11d, 0x127f, 0xc11d, 0x21, 0 - .dw 0x12c0, 0xc11d, 0x12ff, 0xc11d, 0x21, 0 - .dw 0x1340, 0xc11d, 0x137f, 0xc11d, 0x21, 0 - .dw 0x13c0, 0xc11d, 0x13ff, 0xc11d, 0x21, 0 - .dw 0x1440, 0xc11d, 0x147f, 0xc11d, 0x21, 0 - .dw 0x14c0, 0xc11d, 0x14ff, 0xc11d, 0x21, 0 - .dw 0x1540, 0xc11d, 0x157f, 0xc11d, 0x21, 0 - .dw 0x15c0, 0xc11d, 0x15ff, 0xc11d, 0x21, 0 - .dw 0x1640, 0xc11d, 0x167f, 0xc11d, 0x21, 0 - .dw 0x16c0, 0xc11d, 0x16ff, 0xc11d, 0x21, 0 - .dw 0x1740, 0xc11d, 0x177f, 0xc11d, 0x21, 0 - .dw 0x17c0, 0xc11d, 0x17ff, 0xc11d, 0x21, 0 - .dw 0x1840, 0xc11d, 0x187f, 0xc11d, 0x21, 0 - .dw 0x18c0, 0xc11d, 0x18ff, 0xc11d, 0x21, 0 - .dw 0x1940, 0xc11d, 0x197f, 0xc11d, 0x21, 0 - .dw 0x19c0, 0xc11d, 0x1fff, 0xc11d, 0x21, 0 - .dw 0x2040, 0xc11d, 0x207f, 0xc11d, 0x21, 0 - .dw 0x20c0, 0xc11d, 0x20ff, 0xc11d, 0x21, 0 - .dw 0x2140, 0xc11d, 0x217f, 0xc11d, 0x21, 0 - .dw 0x21c0, 0xc11d, 0x21ff, 0xc11d, 0x21, 0 - .dw 0x2240, 0xc11d, 0x227f, 0xc11d, 0x21, 0 - .dw 0x22c0, 0xc11d, 0x22ff, 0xc11d, 0x21, 0 - .dw 0x2340, 0xc11d, 0x237f, 0xc11d, 0x21, 0 - .dw 0x23c0, 0xc11d, 0x23ff, 0xc11d, 0x21, 0 - .dw 0x2440, 0xc11d, 0x247f, 0xc11d, 0x21, 0 - .dw 0x24c0, 0xc11d, 0x24ff, 0xc11d, 0x21, 0 - .dw 0x2540, 0xc11d, 0x257f, 0xc11d, 0x21, 0 - .dw 0x25c0, 0xc11d, 0x25ff, 0xc11d, 0x21, 0 - .dw 0x2640, 0xc11d, 0x267f, 0xc11d, 0x21, 0 - .dw 0x26c0, 0xc11d, 0x26ff, 0xc11d, 0x21, 0 - .dw 0x2740, 0xc11d, 0x277f, 0xc11d, 0x21, 0 - .dw 0x27c0, 0xc11d, 0x27ff, 0xc11d, 0x21, 0 - .dw 0x2840, 0xc11d, 0x287f, 0xc11d, 0x21, 0 - .dw 0x28c0, 0xc11d, 0x28ff, 0xc11d, 0x21, 0 - .dw 0x2940, 0xc11d, 0x297f, 0xc11d, 0x21, 0 - .dw 0x29c0, 0xc11d, 0x29ff, 0xc11d, 0x21, 0 - .dw 0x2a40, 0xc11d, 0x2a7f, 0xc11d, 0x21, 0 - .dw 0x2ac0, 0xc11d, 0x2aff, 0xc11d, 0x21, 0 - .dw 0x2b40, 0xc11d, 0x2b7f, 0xc11d, 0x21, 0 - .dw 0x2bc0, 0xc11d, 0x2bff, 0xc11d, 0x21, 0 - .dw 0x2c40, 0xc11d, 0x2c7f, 0xc11d, 0x21, 0 - .dw 0x2cc0, 0xc11d, 0x2cff, 0xc11d, 0x21, 0 - .dw 0x2d40, 0xc11d, 0x2d7f, 0xc11d, 0x21, 0 - .dw 0x2dc0, 0xc11d, 0x2dff, 0xc11d, 0x21, 0 - .dw 0x2e40, 0xc11d, 0x2e7f, 0xc11d, 0x21, 0 - .dw 0x2ec0, 0xc11d, 0x2eff, 0xc11d, 0x21, 0 - .dw 0x2f40, 0xc11d, 0x2f7f, 0xc11d, 0x21, 0 - .dw 0x2fc0, 0xc11d, 0x2fff, 0xc11d, 0x21, 0 - .dw 0x3040, 0xc11d, 0x307f, 0xc11d, 0x21, 0 - .dw 0x30c0, 0xc11d, 0x30ff, 0xc11d, 0x21, 0 - .dw 0x3140, 0xc11d, 0x317f, 0xc11d, 0x21, 0 - .dw 0x31c0, 0xc11d, 0x31ff, 0xc11d, 0x21, 0 - .dw 0x3240, 0xc11d, 0x327f, 0xc11d, 0x21, 0 - .dw 0x32c0, 0xc11d, 0x32ff, 0xc11d, 0x21, 0 - .dw 0x3340, 0xc11d, 0x337f, 0xc11d, 0x21, 0 - .dw 0x33c0, 0xc11d, 0x33ff, 0xc11d, 0x21, 0 - .dw 0x3440, 0xc11d, 0x347f, 0xc11d, 0x21, 0 - .dw 0x34c0, 0xc11d, 0x34ff, 0xc11d, 0x21, 0 - .dw 0x3540, 0xc11d, 0x357f, 0xc11d, 0x21, 0 - .dw 0x35c0, 0xc11d, 0x35ff, 0xc11d, 0x21, 0 - .dw 0x3640, 0xc11d, 0x367f, 0xc11d, 0x21, 0 - .dw 0x36c0, 0xc11d, 0x36ff, 0xc11d, 0x21, 0 - .dw 0x3740, 0xc11d, 0x377f, 0xc11d, 0x21, 0 - .dw 0x37c0, 0xc11d, 0x37ff, 0xc11d, 0x21, 0 - .dw 0x3840, 0xc11d, 0x387f, 0xc11d, 0x21, 0 - .dw 0x38c0, 0xc11d, 0x38ff, 0xc11d, 0x21, 0 - .dw 0x3940, 0xc11d, 0x397f, 0xc11d, 0x21, 0 - .dw 0x39c0, 0xc11d, 0x3fff, 0xc11d, 0x21, 0 - .dw 0x4040, 0xc11d, 0x407f, 0xc11d, 0x21, 0 - .dw 0x40c0, 0xc11d, 0x40ff, 0xc11d, 0x21, 0 - .dw 0x4140, 0xc11d, 0x417f, 0xc11d, 0x21, 0 - .dw 0x41c0, 0xc11d, 0x41ff, 0xc11d, 0x21, 0 - .dw 0x4240, 0xc11d, 0x427f, 0xc11d, 0x21, 0 - .dw 0x42c0, 0xc11d, 0x42ff, 0xc11d, 0x21, 0 - .dw 0x4340, 0xc11d, 0x437f, 0xc11d, 0x21, 0 - .dw 0x43c0, 0xc11d, 0x43ff, 0xc11d, 0x21, 0 - .dw 0x4440, 0xc11d, 0x447f, 0xc11d, 0x21, 0 - .dw 0x44c0, 0xc11d, 0x44ff, 0xc11d, 0x21, 0 - .dw 0x4540, 0xc11d, 0x457f, 0xc11d, 0x21, 0 - .dw 0x45c0, 0xc11d, 0x45ff, 0xc11d, 0x21, 0 - .dw 0x4640, 0xc11d, 0x467f, 0xc11d, 0x21, 0 - .dw 0x46c0, 0xc11d, 0x46ff, 0xc11d, 0x21, 0 - .dw 0x4740, 0xc11d, 0x477f, 0xc11d, 0x21, 0 - .dw 0x47c0, 0xc11d, 0x47ff, 0xc11d, 0x21, 0 - .dw 0x4840, 0xc11d, 0x487f, 0xc11d, 0x21, 0 - .dw 0x48c0, 0xc11d, 0x48ff, 0xc11d, 0x21, 0 - .dw 0x4940, 0xc11d, 0x497f, 0xc11d, 0x21, 0 - .dw 0x49c0, 0xc11d, 0x49ff, 0xc11d, 0x21, 0 - .dw 0x4a40, 0xc11d, 0x4a7f, 0xc11d, 0x21, 0 - .dw 0x4ac0, 0xc11d, 0x4aff, 0xc11d, 0x21, 0 - .dw 0x4b40, 0xc11d, 0x4b7f, 0xc11d, 0x21, 0 - .dw 0x4bc0, 0xc11d, 0x4bff, 0xc11d, 0x21, 0 - .dw 0x4c40, 0xc11d, 0x4c7f, 0xc11d, 0x21, 0 - .dw 0x4cc0, 0xc11d, 0x4cff, 0xc11d, 0x21, 0 - .dw 0x4d40, 0xc11d, 0x4d7f, 0xc11d, 0x21, 0 - .dw 0x4dc0, 0xc11d, 0x4dff, 0xc11d, 0x21, 0 - .dw 0x4e40, 0xc11d, 0x4e7f, 0xc11d, 0x21, 0 - .dw 0x4ec0, 0xc11d, 0x4eff, 0xc11d, 0x21, 0 - .dw 0x4f40, 0xc11d, 0x4f7f, 0xc11d, 0x21, 0 - .dw 0x4fc0, 0xc11d, 0x4fff, 0xc11d, 0x21, 0 - .dw 0x5040, 0xc11d, 0x507f, 0xc11d, 0x21, 0 - .dw 0x50c0, 0xc11d, 0x50ff, 0xc11d, 0x21, 0 - .dw 0x5140, 0xc11d, 0x517f, 0xc11d, 0x21, 0 - .dw 0x51c0, 0xc11d, 0x51ff, 0xc11d, 0x21, 0 - .dw 0x5240, 0xc11d, 0x527f, 0xc11d, 0x21, 0 - .dw 0x52c0, 0xc11d, 0x52ff, 0xc11d, 0x21, 0 - .dw 0x5340, 0xc11d, 0x537f, 0xc11d, 0x21, 0 - .dw 0x53c0, 0xc11d, 0x53ff, 0xc11d, 0x21, 0 - .dw 0x5440, 0xc11d, 0x547f, 0xc11d, 0x21, 0 - .dw 0x54c0, 0xc11d, 0x54ff, 0xc11d, 0x21, 0 - .dw 0x5540, 0xc11d, 0x557f, 0xc11d, 0x21, 0 - .dw 0x55c0, 0xc11d, 0x55ff, 0xc11d, 0x21, 0 - .dw 0x5640, 0xc11d, 0x567f, 0xc11d, 0x21, 0 - .dw 0x56c0, 0xc11d, 0x56ff, 0xc11d, 0x21, 0 - .dw 0x5740, 0xc11d, 0x577f, 0xc11d, 0x21, 0 - .dw 0x57c0, 0xc11d, 0x57ff, 0xc11d, 0x21, 0 - .dw 0x5840, 0xc11d, 0x587f, 0xc11d, 0x21, 0 - .dw 0x58c0, 0xc11d, 0x58ff, 0xc11d, 0x21, 0 - .dw 0x5940, 0xc11d, 0x597f, 0xc11d, 0x21, 0 - .dw 0x59c0, 0xc11d, 0x5fff, 0xc11d, 0x21, 0 - .dw 0x6040, 0xc11d, 0x607f, 0xc11d, 0x21, 0 - .dw 0x60c0, 0xc11d, 0x60ff, 0xc11d, 0x21, 0 - .dw 0x6140, 0xc11d, 0x617f, 0xc11d, 0x21, 0 - .dw 0x61c0, 0xc11d, 0x61ff, 0xc11d, 0x21, 0 - .dw 0x6240, 0xc11d, 0x627f, 0xc11d, 0x21, 0 - .dw 0x62c0, 0xc11d, 0x62ff, 0xc11d, 0x21, 0 - .dw 0x6340, 0xc11d, 0x637f, 0xc11d, 0x21, 0 - .dw 0x63c0, 0xc11d, 0x63ff, 0xc11d, 0x21, 0 - .dw 0x6440, 0xc11d, 0x647f, 0xc11d, 0x21, 0 - .dw 0x64c0, 0xc11d, 0x64ff, 0xc11d, 0x21, 0 - .dw 0x6540, 0xc11d, 0x657f, 0xc11d, 0x21, 0 - .dw 0x65c0, 0xc11d, 0x65ff, 0xc11d, 0x21, 0 - .dw 0x6640, 0xc11d, 0x667f, 0xc11d, 0x21, 0 - .dw 0x66c0, 0xc11d, 0x66ff, 0xc11d, 0x21, 0 - .dw 0x6740, 0xc11d, 0x677f, 0xc11d, 0x21, 0 - .dw 0x67c0, 0xc11d, 0x67ff, 0xc11d, 0x21, 0 - .dw 0x6840, 0xc11d, 0x687f, 0xc11d, 0x21, 0 - .dw 0x68c0, 0xc11d, 0x68ff, 0xc11d, 0x21, 0 - .dw 0x6940, 0xc11d, 0x697f, 0xc11d, 0x21, 0 - .dw 0x69c0, 0xc11d, 0x69ff, 0xc11d, 0x21, 0 - .dw 0x6a40, 0xc11d, 0x6a7f, 0xc11d, 0x21, 0 - .dw 0x6ac0, 0xc11d, 0x6aff, 0xc11d, 0x21, 0 - .dw 0x6b40, 0xc11d, 0x6b7f, 0xc11d, 0x21, 0 - .dw 0x6bc0, 0xc11d, 0x6bff, 0xc11d, 0x21, 0 - .dw 0x6c40, 0xc11d, 0x6c7f, 0xc11d, 0x21, 0 - .dw 0x6cc0, 0xc11d, 0x6cff, 0xc11d, 0x21, 0 - .dw 0x6d40, 0xc11d, 0x6d7f, 0xc11d, 0x21, 0 - .dw 0x6dc0, 0xc11d, 0x6dff, 0xc11d, 0x21, 0 - .dw 0x6e40, 0xc11d, 0x6e7f, 0xc11d, 0x21, 0 - .dw 0x6ec0, 0xc11d, 0x6eff, 0xc11d, 0x21, 0 - .dw 0x6f40, 0xc11d, 0x6f7f, 0xc11d, 0x21, 0 - .dw 0x6fc0, 0xc11d, 0x6fff, 0xc11d, 0x21, 0 - .dw 0x7040, 0xc11d, 0x707f, 0xc11d, 0x21, 0 - .dw 0x70c0, 0xc11d, 0x70ff, 0xc11d, 0x21, 0 - .dw 0x7140, 0xc11d, 0x717f, 0xc11d, 0x21, 0 - .dw 0x71c0, 0xc11d, 0x71ff, 0xc11d, 0x21, 0 - .dw 0x7240, 0xc11d, 0x727f, 0xc11d, 0x21, 0 - .dw 0x72c0, 0xc11d, 0x72ff, 0xc11d, 0x21, 0 - .dw 0x7340, 0xc11d, 0x737f, 0xc11d, 0x21, 0 - .dw 0x73c0, 0xc11d, 0x73ff, 0xc11d, 0x21, 0 - .dw 0x7440, 0xc11d, 0x747f, 0xc11d, 0x21, 0 - .dw 0x74c0, 0xc11d, 0x74ff, 0xc11d, 0x21, 0 - .dw 0x7540, 0xc11d, 0x757f, 0xc11d, 0x21, 0 - .dw 0x75c0, 0xc11d, 0x75ff, 0xc11d, 0x21, 0 - .dw 0x7640, 0xc11d, 0x767f, 0xc11d, 0x21, 0 - .dw 0x76c0, 0xc11d, 0x76ff, 0xc11d, 0x21, 0 - .dw 0x7740, 0xc11d, 0x777f, 0xc11d, 0x21, 0 - .dw 0x77c0, 0xc11d, 0x77ff, 0xc11d, 0x21, 0 - .dw 0x7840, 0xc11d, 0x787f, 0xc11d, 0x21, 0 - .dw 0x78c0, 0xc11d, 0x78ff, 0xc11d, 0x21, 0 - .dw 0x7940, 0xc11d, 0x797f, 0xc11d, 0x21, 0 - .dw 0x79c0, 0xc11d, 0x7fff, 0xc11d, 0x21, 0 - .dw 0x8040, 0xc11d, 0x807f, 0xc11d, 0x21, 0 - .dw 0x80c0, 0xc11d, 0x80ff, 0xc11d, 0x21, 0 - .dw 0x8140, 0xc11d, 0x817f, 0xc11d, 0x21, 0 - .dw 0x81c0, 0xc11d, 0x81ff, 0xc11d, 0x21, 0 - .dw 0x8240, 0xc11d, 0x827f, 0xc11d, 0x21, 0 - .dw 0x82c0, 0xc11d, 0x82ff, 0xc11d, 0x21, 0 - .dw 0x8340, 0xc11d, 0x837f, 0xc11d, 0x21, 0 - .dw 0x83c0, 0xc11d, 0x83ff, 0xc11d, 0x21, 0 - .dw 0x8440, 0xc11d, 0x847f, 0xc11d, 0x21, 0 - .dw 0x84c0, 0xc11d, 0x84ff, 0xc11d, 0x21, 0 - .dw 0x8540, 0xc11d, 0x857f, 0xc11d, 0x21, 0 - .dw 0x85c0, 0xc11d, 0x85ff, 0xc11d, 0x21, 0 - .dw 0x8640, 0xc11d, 0x867f, 0xc11d, 0x21, 0 - .dw 0x86c0, 0xc11d, 0x86ff, 0xc11d, 0x21, 0 - .dw 0x8740, 0xc11d, 0x877f, 0xc11d, 0x21, 0 - .dw 0x87c0, 0xc11d, 0x87ff, 0xc11d, 0x21, 0 - .dw 0x8840, 0xc11d, 0x887f, 0xc11d, 0x21, 0 - .dw 0x88c0, 0xc11d, 0x88ff, 0xc11d, 0x21, 0 - .dw 0x8940, 0xc11d, 0x897f, 0xc11d, 0x21, 0 - .dw 0x89c0, 0xc11d, 0x89ff, 0xc11d, 0x21, 0 - .dw 0x8a40, 0xc11d, 0x8a7f, 0xc11d, 0x21, 0 - .dw 0x8ac0, 0xc11d, 0x8aff, 0xc11d, 0x21, 0 - .dw 0x8b40, 0xc11d, 0x8b7f, 0xc11d, 0x21, 0 - .dw 0x8bc0, 0xc11d, 0x8bff, 0xc11d, 0x21, 0 - .dw 0x8c40, 0xc11d, 0x8c7f, 0xc11d, 0x21, 0 - .dw 0x8cc0, 0xc11d, 0x8cff, 0xc11d, 0x21, 0 - .dw 0x8d40, 0xc11d, 0x8d7f, 0xc11d, 0x21, 0 - .dw 0x8dc0, 0xc11d, 0x8dff, 0xc11d, 0x21, 0 - .dw 0x8e40, 0xc11d, 0x8e7f, 0xc11d, 0x21, 0 - .dw 0x8ec0, 0xc11d, 0x8eff, 0xc11d, 0x21, 0 - .dw 0x8f40, 0xc11d, 0x8f7f, 0xc11d, 0x21, 0 - .dw 0x8fc0, 0xc11d, 0x8fff, 0xc11d, 0x21, 0 - .dw 0x9040, 0xc11d, 0x907f, 0xc11d, 0x21, 0 - .dw 0x90c0, 0xc11d, 0x90ff, 0xc11d, 0x21, 0 - .dw 0x9140, 0xc11d, 0x917f, 0xc11d, 0x21, 0 - .dw 0x91c0, 0xc11d, 0x91ff, 0xc11d, 0x21, 0 - .dw 0x9240, 0xc11d, 0x927f, 0xc11d, 0x21, 0 - .dw 0x92c0, 0xc11d, 0x92ff, 0xc11d, 0x21, 0 - .dw 0x9340, 0xc11d, 0x937f, 0xc11d, 0x21, 0 - .dw 0x93c0, 0xc11d, 0x93ff, 0xc11d, 0x21, 0 - .dw 0x9440, 0xc11d, 0x947f, 0xc11d, 0x21, 0 - .dw 0x94c0, 0xc11d, 0x94ff, 0xc11d, 0x21, 0 - .dw 0x9540, 0xc11d, 0x957f, 0xc11d, 0x21, 0 - .dw 0x95c0, 0xc11d, 0x95ff, 0xc11d, 0x21, 0 - .dw 0x9640, 0xc11d, 0x967f, 0xc11d, 0x21, 0 - .dw 0x96c0, 0xc11d, 0x96ff, 0xc11d, 0x21, 0 - .dw 0x9740, 0xc11d, 0x977f, 0xc11d, 0x21, 0 - .dw 0x97c0, 0xc11d, 0x97ff, 0xc11d, 0x21, 0 - .dw 0x9840, 0xc11d, 0x987f, 0xc11d, 0x21, 0 - .dw 0x98c0, 0xc11d, 0x98ff, 0xc11d, 0x21, 0 - .dw 0x9940, 0xc11d, 0x997f, 0xc11d, 0x21, 0 - .dw 0x99c0, 0xc11d, 0x9fff, 0xc11d, 0x21, 0 - .dw 0xa040, 0xc11d, 0xa07f, 0xc11d, 0x21, 0 - .dw 0xa0c0, 0xc11d, 0xa0ff, 0xc11d, 0x21, 0 - .dw 0xa140, 0xc11d, 0xa17f, 0xc11d, 0x21, 0 - .dw 0xa1c0, 0xc11d, 0xa1ff, 0xc11d, 0x21, 0 - .dw 0xa240, 0xc11d, 0xa27f, 0xc11d, 0x21, 0 - .dw 0xa2c0, 0xc11d, 0xa2ff, 0xc11d, 0x21, 0 - .dw 0xa340, 0xc11d, 0xa37f, 0xc11d, 0x21, 0 - .dw 0xa3c0, 0xc11d, 0xa3ff, 0xc11d, 0x21, 0 - .dw 0xa440, 0xc11d, 0xa47f, 0xc11d, 0x21, 0 - .dw 0xa4c0, 0xc11d, 0xa4ff, 0xc11d, 0x21, 0 - .dw 0xa540, 0xc11d, 0xa57f, 0xc11d, 0x21, 0 - .dw 0xa5c0, 0xc11d, 0xa5ff, 0xc11d, 0x21, 0 - .dw 0xa640, 0xc11d, 0xa67f, 0xc11d, 0x21, 0 - .dw 0xa6c0, 0xc11d, 0xa6ff, 0xc11d, 0x21, 0 - .dw 0xa740, 0xc11d, 0xa77f, 0xc11d, 0x21, 0 - .dw 0xa7c0, 0xc11d, 0xa7ff, 0xc11d, 0x21, 0 - .dw 0xa840, 0xc11d, 0xa87f, 0xc11d, 0x21, 0 - .dw 0xa8c0, 0xc11d, 0xa8ff, 0xc11d, 0x21, 0 - .dw 0xa940, 0xc11d, 0xa97f, 0xc11d, 0x21, 0 - .dw 0xa9c0, 0xc11d, 0xa9ff, 0xc11d, 0x21, 0 - .dw 0xaa40, 0xc11d, 0xaa7f, 0xc11d, 0x21, 0 - .dw 0xaac0, 0xc11d, 0xaaff, 0xc11d, 0x21, 0 - .dw 0xab40, 0xc11d, 0xab7f, 0xc11d, 0x21, 0 - .dw 0xabc0, 0xc11d, 0xabff, 0xc11d, 0x21, 0 - .dw 0xac40, 0xc11d, 0xac7f, 0xc11d, 0x21, 0 - .dw 0xacc0, 0xc11d, 0xacff, 0xc11d, 0x21, 0 - .dw 0xad40, 0xc11d, 0xad7f, 0xc11d, 0x21, 0 - .dw 0xadc0, 0xc11d, 0xadff, 0xc11d, 0x21, 0 - .dw 0xae40, 0xc11d, 0xae7f, 0xc11d, 0x21, 0 - .dw 0xaec0, 0xc11d, 0xaeff, 0xc11d, 0x21, 0 - .dw 0xaf40, 0xc11d, 0xaf7f, 0xc11d, 0x21, 0 - .dw 0xafc0, 0xc11d, 0xafff, 0xc11d, 0x21, 0 - .dw 0xb040, 0xc11d, 0xb07f, 0xc11d, 0x21, 0 - .dw 0xb0c0, 0xc11d, 0xb0ff, 0xc11d, 0x21, 0 - .dw 0xb140, 0xc11d, 0xb17f, 0xc11d, 0x21, 0 - .dw 0xb1c0, 0xc11d, 0xb1ff, 0xc11d, 0x21, 0 - .dw 0xb240, 0xc11d, 0xb27f, 0xc11d, 0x21, 0 - .dw 0xb2c0, 0xc11d, 0xb2ff, 0xc11d, 0x21, 0 - .dw 0xb340, 0xc11d, 0xb37f, 0xc11d, 0x21, 0 - .dw 0xb3c0, 0xc11d, 0xb3ff, 0xc11d, 0x21, 0 - .dw 0xb440, 0xc11d, 0xb47f, 0xc11d, 0x21, 0 - .dw 0xb4c0, 0xc11d, 0xb4ff, 0xc11d, 0x21, 0 - .dw 0xb540, 0xc11d, 0xb57f, 0xc11d, 0x21, 0 - .dw 0xb5c0, 0xc11d, 0xb5ff, 0xc11d, 0x21, 0 - .dw 0xb640, 0xc11d, 0xb67f, 0xc11d, 0x21, 0 - .dw 0xb6c0, 0xc11d, 0xb6ff, 0xc11d, 0x21, 0 - .dw 0xb740, 0xc11d, 0xb77f, 0xc11d, 0x21, 0 - .dw 0xb7c0, 0xc11d, 0xb7ff, 0xc11d, 0x21, 0 - .dw 0xb840, 0xc11d, 0xb87f, 0xc11d, 0x21, 0 - .dw 0xb8c0, 0xc11d, 0xb8ff, 0xc11d, 0x21, 0 - .dw 0xb940, 0xc11d, 0xb97f, 0xc11d, 0x21, 0 - .dw 0xb9c0, 0xc11d, 0xbfff, 0xc11d, 0x21, 0 - .dw 0xc040, 0xc11d, 0xc07f, 0xc11d, 0x21, 0 - .dw 0xc0c0, 0xc11d, 0xc0ff, 0xc11d, 0x21, 0 - .dw 0xc140, 0xc11d, 0xc17f, 0xc11d, 0x21, 0 - .dw 0xc1c0, 0xc11d, 0xc1ff, 0xc11d, 0x21, 0 - .dw 0xc240, 0xc11d, 0xc27f, 0xc11d, 0x21, 0 - .dw 0xc2c0, 0xc11d, 0xc2ff, 0xc11d, 0x21, 0 - .dw 0xc340, 0xc11d, 0xc37f, 0xc11d, 0x21, 0 - .dw 0xc3c0, 0xc11d, 0xc3ff, 0xc11d, 0x21, 0 - .dw 0xc440, 0xc11d, 0xc47f, 0xc11d, 0x21, 0 - .dw 0xc4c0, 0xc11d, 0xc4ff, 0xc11d, 0x21, 0 - .dw 0xc540, 0xc11d, 0xc57f, 0xc11d, 0x21, 0 - .dw 0xc5c0, 0xc11d, 0xc5ff, 0xc11d, 0x21, 0 - .dw 0xc640, 0xc11d, 0xc67f, 0xc11d, 0x21, 0 - .dw 0xc6c0, 0xc11d, 0xc6ff, 0xc11d, 0x21, 0 - .dw 0xc740, 0xc11d, 0xc77f, 0xc11d, 0x21, 0 - .dw 0xc7c0, 0xc11d, 0xc7ff, 0xc11d, 0x21, 0 - .dw 0xc840, 0xc11d, 0xc87f, 0xc11d, 0x21, 0 - .dw 0xc8c0, 0xc11d, 0xc8ff, 0xc11d, 0x21, 0 - .dw 0xc940, 0xc11d, 0xc97f, 0xc11d, 0x21, 0 - .dw 0xc9c0, 0xc11d, 0xc9ff, 0xc11d, 0x21, 0 - .dw 0xca40, 0xc11d, 0xca7f, 0xc11d, 0x21, 0 - .dw 0xcac0, 0xc11d, 0xcaff, 0xc11d, 0x21, 0 - .dw 0xcb40, 0xc11d, 0xcb7f, 0xc11d, 0x21, 0 - .dw 0xcbc0, 0xc11d, 0xcbff, 0xc11d, 0x21, 0 - .dw 0xcc40, 0xc11d, 0xcc7f, 0xc11d, 0x21, 0 - .dw 0xccc0, 0xc11d, 0xccff, 0xc11d, 0x21, 0 - .dw 0xcd40, 0xc11d, 0xcd7f, 0xc11d, 0x21, 0 - .dw 0xcdc0, 0xc11d, 0xcdff, 0xc11d, 0x21, 0 - .dw 0xce40, 0xc11d, 0xce7f, 0xc11d, 0x21, 0 - .dw 0xcec0, 0xc11d, 0xceff, 0xc11d, 0x21, 0 - .dw 0xcf40, 0xc11d, 0xcf7f, 0xc11d, 0x21, 0 - .dw 0xcfc0, 0xc11d, 0xcfff, 0xc11d, 0x21, 0 - .dw 0xd040, 0xc11d, 0xd07f, 0xc11d, 0x21, 0 - .dw 0xd0c0, 0xc11d, 0xd0ff, 0xc11d, 0x21, 0 - .dw 0xd140, 0xc11d, 0xd17f, 0xc11d, 0x21, 0 - .dw 0xd1c0, 0xc11d, 0xd1ff, 0xc11d, 0x21, 0 - .dw 0xd240, 0xc11d, 0xd27f, 0xc11d, 0x21, 0 - .dw 0xd2c0, 0xc11d, 0xd2ff, 0xc11d, 0x21, 0 - .dw 0xd340, 0xc11d, 0xd37f, 0xc11d, 0x21, 0 - .dw 0xd3c0, 0xc11d, 0xd3ff, 0xc11d, 0x21, 0 - .dw 0xd440, 0xc11d, 0xd47f, 0xc11d, 0x21, 0 - .dw 0xd4c0, 0xc11d, 0xd4ff, 0xc11d, 0x21, 0 - .dw 0xd540, 0xc11d, 0xd57f, 0xc11d, 0x21, 0 - .dw 0xd5c0, 0xc11d, 0xd5ff, 0xc11d, 0x21, 0 - .dw 0xd640, 0xc11d, 0xd67f, 0xc11d, 0x21, 0 - .dw 0xd6c0, 0xc11d, 0xd6ff, 0xc11d, 0x21, 0 - .dw 0xd740, 0xc11d, 0xd77f, 0xc11d, 0x21, 0 - .dw 0xd7c0, 0xc11d, 0xd7ff, 0xc11d, 0x21, 0 - .dw 0xd840, 0xc11d, 0xd87f, 0xc11d, 0x21, 0 - .dw 0xd8c0, 0xc11d, 0xd8ff, 0xc11d, 0x21, 0 - .dw 0xd940, 0xc11d, 0xd97f, 0xc11d, 0x21, 0 - .dw 0xd9c0, 0xc11d, 0xdfff, 0xc11d, 0x21, 0 - .dw 0xe040, 0xc11d, 0xe07f, 0xc11d, 0x21, 0 - .dw 0xe0c0, 0xc11d, 0xe0ff, 0xc11d, 0x21, 0 - .dw 0xe140, 0xc11d, 0xe17f, 0xc11d, 0x21, 0 - .dw 0xe1c0, 0xc11d, 0xe1ff, 0xc11d, 0x21, 0 - .dw 0xe240, 0xc11d, 0xe27f, 0xc11d, 0x21, 0 - .dw 0xe2c0, 0xc11d, 0xe2ff, 0xc11d, 0x21, 0 - .dw 0xe340, 0xc11d, 0xe37f, 0xc11d, 0x21, 0 - .dw 0xe3c0, 0xc11d, 0xe3ff, 0xc11d, 0x21, 0 - .dw 0xe440, 0xc11d, 0xe47f, 0xc11d, 0x21, 0 - .dw 0xe4c0, 0xc11d, 0xe4ff, 0xc11d, 0x21, 0 - .dw 0xe540, 0xc11d, 0xe57f, 0xc11d, 0x21, 0 - .dw 0xe5c0, 0xc11d, 0xe5ff, 0xc11d, 0x21, 0 - .dw 0xe640, 0xc11d, 0xe67f, 0xc11d, 0x21, 0 - .dw 0xe6c0, 0xc11d, 0xe6ff, 0xc11d, 0x21, 0 - .dw 0xe740, 0xc11d, 0xe77f, 0xc11d, 0x21, 0 - .dw 0xe7c0, 0xc11d, 0xe7ff, 0xc11d, 0x21, 0 - .dw 0xe840, 0xc11d, 0xe87f, 0xc11d, 0x21, 0 - .dw 0xe8c0, 0xc11d, 0xe8ff, 0xc11d, 0x21, 0 - .dw 0xe940, 0xc11d, 0xe97f, 0xc11d, 0x21, 0 - .dw 0xe9c0, 0xc11d, 0xe9ff, 0xc11d, 0x21, 0 - .dw 0xea40, 0xc11d, 0xea7f, 0xc11d, 0x21, 0 - .dw 0xeac0, 0xc11d, 0xeaff, 0xc11d, 0x21, 0 - .dw 0xeb40, 0xc11d, 0xeb7f, 0xc11d, 0x21, 0 - .dw 0xebc0, 0xc11d, 0xebff, 0xc11d, 0x21, 0 - .dw 0xec40, 0xc11d, 0xec7f, 0xc11d, 0x21, 0 - .dw 0xecc0, 0xc11d, 0xecff, 0xc11d, 0x21, 0 - .dw 0xed40, 0xc11d, 0xed7f, 0xc11d, 0x21, 0 - .dw 0xedc0, 0xc11d, 0xedff, 0xc11d, 0x21, 0 - .dw 0xee40, 0xc11d, 0xee7f, 0xc11d, 0x21, 0 - .dw 0xeec0, 0xc11d, 0xeeff, 0xc11d, 0x21, 0 - .dw 0xef40, 0xc11d, 0xef7f, 0xc11d, 0x21, 0 - .dw 0xefc0, 0xc11d, 0xefff, 0xc11d, 0x21, 0 - .dw 0xf040, 0xc11d, 0xf07f, 0xc11d, 0x21, 0 - .dw 0xf0c0, 0xc11d, 0xf0ff, 0xc11d, 0x21, 0 - .dw 0xf140, 0xc11d, 0xf17f, 0xc11d, 0x21, 0 - .dw 0xf1c0, 0xc11d, 0xf1ff, 0xc11d, 0x21, 0 - .dw 0xf240, 0xc11d, 0xf27f, 0xc11d, 0x21, 0 - .dw 0xf2c0, 0xc11d, 0xf2ff, 0xc11d, 0x21, 0 - .dw 0xf340, 0xc11d, 0xf37f, 0xc11d, 0x21, 0 - .dw 0xf3c0, 0xc11d, 0xf3ff, 0xc11d, 0x21, 0 - .dw 0xf440, 0xc11d, 0xf47f, 0xc11d, 0x21, 0 - .dw 0xf4c0, 0xc11d, 0xf4ff, 0xc11d, 0x21, 0 - .dw 0xf540, 0xc11d, 0xf57f, 0xc11d, 0x21, 0 - .dw 0xf5c0, 0xc11d, 0xf5ff, 0xc11d, 0x21, 0 - .dw 0xf640, 0xc11d, 0xf67f, 0xc11d, 0x21, 0 - .dw 0xf6c0, 0xc11d, 0xf6ff, 0xc11d, 0x21, 0 - .dw 0xf740, 0xc11d, 0xf77f, 0xc11d, 0x21, 0 - .dw 0xf7c0, 0xc11d, 0xf7ff, 0xc11d, 0x21, 0 - .dw 0xf840, 0xc11d, 0xf87f, 0xc11d, 0x21, 0 - .dw 0xf8c0, 0xc11d, 0xf8ff, 0xc11d, 0x21, 0 - .dw 0xf940, 0xc11d, 0xf97f, 0xc11d, 0x21, 0 - .dw 0xf9c0, 0xc11d, 0xffff, 0xc11d, 0x21, 0 - .dw 0x0040, 0xc11e, 0x007f, 0xc11e, 0x21, 0 - .dw 0x00c0, 0xc11e, 0x00ff, 0xc11e, 0x21, 0 - .dw 0x0140, 0xc11e, 0x017f, 0xc11e, 0x21, 0 - .dw 0x01c0, 0xc11e, 0x01ff, 0xc11e, 0x21, 0 - .dw 0x0240, 0xc11e, 0x027f, 0xc11e, 0x21, 0 - .dw 0x02c0, 0xc11e, 0x02ff, 0xc11e, 0x21, 0 - .dw 0x0340, 0xc11e, 0x037f, 0xc11e, 0x21, 0 - .dw 0x03c0, 0xc11e, 0x03ff, 0xc11e, 0x21, 0 - .dw 0x0440, 0xc11e, 0x047f, 0xc11e, 0x21, 0 - .dw 0x04c0, 0xc11e, 0x04ff, 0xc11e, 0x21, 0 - .dw 0x0540, 0xc11e, 0x057f, 0xc11e, 0x21, 0 - .dw 0x05c0, 0xc11e, 0x05ff, 0xc11e, 0x21, 0 - .dw 0x0640, 0xc11e, 0x067f, 0xc11e, 0x21, 0 - .dw 0x06c0, 0xc11e, 0x06ff, 0xc11e, 0x21, 0 - .dw 0x0740, 0xc11e, 0x077f, 0xc11e, 0x21, 0 - .dw 0x07c0, 0xc11e, 0x07ff, 0xc11e, 0x21, 0 - .dw 0x0840, 0xc11e, 0x087f, 0xc11e, 0x21, 0 - .dw 0x08c0, 0xc11e, 0x08ff, 0xc11e, 0x21, 0 - .dw 0x0940, 0xc11e, 0x097f, 0xc11e, 0x21, 0 - .dw 0x09c0, 0xc11e, 0x09ff, 0xc11e, 0x21, 0 - .dw 0x0a40, 0xc11e, 0x0a7f, 0xc11e, 0x21, 0 - .dw 0x0ac0, 0xc11e, 0x0aff, 0xc11e, 0x21, 0 - .dw 0x0b40, 0xc11e, 0x0b7f, 0xc11e, 0x21, 0 - .dw 0x0bc0, 0xc11e, 0x0bff, 0xc11e, 0x21, 0 - .dw 0x0c40, 0xc11e, 0x0c7f, 0xc11e, 0x21, 0 - .dw 0x0cc0, 0xc11e, 0x0cff, 0xc11e, 0x21, 0 - .dw 0x0d40, 0xc11e, 0x0d7f, 0xc11e, 0x21, 0 - .dw 0x0dc0, 0xc11e, 0x0dff, 0xc11e, 0x21, 0 - .dw 0x0e40, 0xc11e, 0x0e7f, 0xc11e, 0x21, 0 - .dw 0x0ec0, 0xc11e, 0x0eff, 0xc11e, 0x21, 0 - .dw 0x0f40, 0xc11e, 0x0f7f, 0xc11e, 0x21, 0 - .dw 0x0fc0, 0xc11e, 0x0fff, 0xc11e, 0x21, 0 - .dw 0x1040, 0xc11e, 0x107f, 0xc11e, 0x21, 0 - .dw 0x10c0, 0xc11e, 0x10ff, 0xc11e, 0x21, 0 - .dw 0x1140, 0xc11e, 0x117f, 0xc11e, 0x21, 0 - .dw 0x11c0, 0xc11e, 0x11ff, 0xc11e, 0x21, 0 - .dw 0x1240, 0xc11e, 0x127f, 0xc11e, 0x21, 0 - .dw 0x12c0, 0xc11e, 0x12ff, 0xc11e, 0x21, 0 - .dw 0x1340, 0xc11e, 0x137f, 0xc11e, 0x21, 0 - .dw 0x13c0, 0xc11e, 0x13ff, 0xc11e, 0x21, 0 - .dw 0x1440, 0xc11e, 0x147f, 0xc11e, 0x21, 0 - .dw 0x14c0, 0xc11e, 0x14ff, 0xc11e, 0x21, 0 - .dw 0x1540, 0xc11e, 0x157f, 0xc11e, 0x21, 0 - .dw 0x15c0, 0xc11e, 0x15ff, 0xc11e, 0x21, 0 - .dw 0x1640, 0xc11e, 0x167f, 0xc11e, 0x21, 0 - .dw 0x16c0, 0xc11e, 0x16ff, 0xc11e, 0x21, 0 - .dw 0x1740, 0xc11e, 0x177f, 0xc11e, 0x21, 0 - .dw 0x17c0, 0xc11e, 0x17ff, 0xc11e, 0x21, 0 - .dw 0x1840, 0xc11e, 0x187f, 0xc11e, 0x21, 0 - .dw 0x18c0, 0xc11e, 0x18ff, 0xc11e, 0x21, 0 - .dw 0x1940, 0xc11e, 0x197f, 0xc11e, 0x21, 0 - .dw 0x19c0, 0xc11e, 0x1fff, 0xc11e, 0x21, 0 - .dw 0x2040, 0xc11e, 0x207f, 0xc11e, 0x21, 0 - .dw 0x20c0, 0xc11e, 0x20ff, 0xc11e, 0x21, 0 - .dw 0x2140, 0xc11e, 0x217f, 0xc11e, 0x21, 0 - .dw 0x21c0, 0xc11e, 0x21ff, 0xc11e, 0x21, 0 - .dw 0x2240, 0xc11e, 0x227f, 0xc11e, 0x21, 0 - .dw 0x22c0, 0xc11e, 0x22ff, 0xc11e, 0x21, 0 - .dw 0x2340, 0xc11e, 0x237f, 0xc11e, 0x21, 0 - .dw 0x23c0, 0xc11e, 0x23ff, 0xc11e, 0x21, 0 - .dw 0x2440, 0xc11e, 0x247f, 0xc11e, 0x21, 0 - .dw 0x24c0, 0xc11e, 0x24ff, 0xc11e, 0x21, 0 - .dw 0x2540, 0xc11e, 0x257f, 0xc11e, 0x21, 0 - .dw 0x25c0, 0xc11e, 0x25ff, 0xc11e, 0x21, 0 - .dw 0x2640, 0xc11e, 0x267f, 0xc11e, 0x21, 0 - .dw 0x26c0, 0xc11e, 0x26ff, 0xc11e, 0x21, 0 - .dw 0x2740, 0xc11e, 0x277f, 0xc11e, 0x21, 0 - .dw 0x27c0, 0xc11e, 0x27ff, 0xc11e, 0x21, 0 - .dw 0x2840, 0xc11e, 0x287f, 0xc11e, 0x21, 0 - .dw 0x28c0, 0xc11e, 0x28ff, 0xc11e, 0x21, 0 - .dw 0x2940, 0xc11e, 0x297f, 0xc11e, 0x21, 0 - .dw 0x29c0, 0xc11e, 0x29ff, 0xc11e, 0x21, 0 - .dw 0x2a40, 0xc11e, 0x2a7f, 0xc11e, 0x21, 0 - .dw 0x2ac0, 0xc11e, 0x2aff, 0xc11e, 0x21, 0 - .dw 0x2b40, 0xc11e, 0x2b7f, 0xc11e, 0x21, 0 - .dw 0x2bc0, 0xc11e, 0x2bff, 0xc11e, 0x21, 0 - .dw 0x2c40, 0xc11e, 0x2c7f, 0xc11e, 0x21, 0 - .dw 0x2cc0, 0xc11e, 0x2cff, 0xc11e, 0x21, 0 - .dw 0x2d40, 0xc11e, 0x2d7f, 0xc11e, 0x21, 0 - .dw 0x2dc0, 0xc11e, 0x2dff, 0xc11e, 0x21, 0 - .dw 0x2e40, 0xc11e, 0x2e7f, 0xc11e, 0x21, 0 - .dw 0x2ec0, 0xc11e, 0x2eff, 0xc11e, 0x21, 0 - .dw 0x2f40, 0xc11e, 0x2f7f, 0xc11e, 0x21, 0 - .dw 0x2fc0, 0xc11e, 0x2fff, 0xc11e, 0x21, 0 - .dw 0x3040, 0xc11e, 0x307f, 0xc11e, 0x21, 0 - .dw 0x30c0, 0xc11e, 0x30ff, 0xc11e, 0x21, 0 - .dw 0x3140, 0xc11e, 0x317f, 0xc11e, 0x21, 0 - .dw 0x31c0, 0xc11e, 0x31ff, 0xc11e, 0x21, 0 - .dw 0x3240, 0xc11e, 0x327f, 0xc11e, 0x21, 0 - .dw 0x32c0, 0xc11e, 0x32ff, 0xc11e, 0x21, 0 - .dw 0x3340, 0xc11e, 0x337f, 0xc11e, 0x21, 0 - .dw 0x33c0, 0xc11e, 0x33ff, 0xc11e, 0x21, 0 - .dw 0x3440, 0xc11e, 0x347f, 0xc11e, 0x21, 0 - .dw 0x34c0, 0xc11e, 0x34ff, 0xc11e, 0x21, 0 - .dw 0x3540, 0xc11e, 0x357f, 0xc11e, 0x21, 0 - .dw 0x35c0, 0xc11e, 0x35ff, 0xc11e, 0x21, 0 - .dw 0x3640, 0xc11e, 0x367f, 0xc11e, 0x21, 0 - .dw 0x36c0, 0xc11e, 0x36ff, 0xc11e, 0x21, 0 - .dw 0x3740, 0xc11e, 0x377f, 0xc11e, 0x21, 0 - .dw 0x37c0, 0xc11e, 0x37ff, 0xc11e, 0x21, 0 - .dw 0x3840, 0xc11e, 0x387f, 0xc11e, 0x21, 0 - .dw 0x38c0, 0xc11e, 0x38ff, 0xc11e, 0x21, 0 - .dw 0x3940, 0xc11e, 0x397f, 0xc11e, 0x21, 0 - .dw 0x39c0, 0xc11e, 0x3fff, 0xc11e, 0x21, 0 - .dw 0x4040, 0xc11e, 0x407f, 0xc11e, 0x21, 0 - .dw 0x40c0, 0xc11e, 0x40ff, 0xc11e, 0x21, 0 - .dw 0x4140, 0xc11e, 0x417f, 0xc11e, 0x21, 0 - .dw 0x41c0, 0xc11e, 0x41ff, 0xc11e, 0x21, 0 - .dw 0x4240, 0xc11e, 0x427f, 0xc11e, 0x21, 0 - .dw 0x42c0, 0xc11e, 0x42ff, 0xc11e, 0x21, 0 - .dw 0x4340, 0xc11e, 0x437f, 0xc11e, 0x21, 0 - .dw 0x43c0, 0xc11e, 0x43ff, 0xc11e, 0x21, 0 - .dw 0x4440, 0xc11e, 0x447f, 0xc11e, 0x21, 0 - .dw 0x44c0, 0xc11e, 0x44ff, 0xc11e, 0x21, 0 - .dw 0x4540, 0xc11e, 0x457f, 0xc11e, 0x21, 0 - .dw 0x45c0, 0xc11e, 0x45ff, 0xc11e, 0x21, 0 - .dw 0x4640, 0xc11e, 0x467f, 0xc11e, 0x21, 0 - .dw 0x46c0, 0xc11e, 0x46ff, 0xc11e, 0x21, 0 - .dw 0x4740, 0xc11e, 0x477f, 0xc11e, 0x21, 0 - .dw 0x47c0, 0xc11e, 0x47ff, 0xc11e, 0x21, 0 - .dw 0x4840, 0xc11e, 0x487f, 0xc11e, 0x21, 0 - .dw 0x48c0, 0xc11e, 0x48ff, 0xc11e, 0x21, 0 - .dw 0x4940, 0xc11e, 0x497f, 0xc11e, 0x21, 0 - .dw 0x49c0, 0xc11e, 0x49ff, 0xc11e, 0x21, 0 - .dw 0x4a40, 0xc11e, 0x4a7f, 0xc11e, 0x21, 0 - .dw 0x4ac0, 0xc11e, 0x4aff, 0xc11e, 0x21, 0 - .dw 0x4b40, 0xc11e, 0x4b7f, 0xc11e, 0x21, 0 - .dw 0x4bc0, 0xc11e, 0x4bff, 0xc11e, 0x21, 0 - .dw 0x4c40, 0xc11e, 0x4c7f, 0xc11e, 0x21, 0 - .dw 0x4cc0, 0xc11e, 0x4cff, 0xc11e, 0x21, 0 - .dw 0x4d40, 0xc11e, 0x4d7f, 0xc11e, 0x21, 0 - .dw 0x4dc0, 0xc11e, 0x4dff, 0xc11e, 0x21, 0 - .dw 0x4e40, 0xc11e, 0x4e7f, 0xc11e, 0x21, 0 - .dw 0x4ec0, 0xc11e, 0x4eff, 0xc11e, 0x21, 0 - .dw 0x4f40, 0xc11e, 0x4f7f, 0xc11e, 0x21, 0 - .dw 0x4fc0, 0xc11e, 0x4fff, 0xc11e, 0x21, 0 - .dw 0x5040, 0xc11e, 0x507f, 0xc11e, 0x21, 0 - .dw 0x50c0, 0xc11e, 0x50ff, 0xc11e, 0x21, 0 - .dw 0x5140, 0xc11e, 0x517f, 0xc11e, 0x21, 0 - .dw 0x51c0, 0xc11e, 0x51ff, 0xc11e, 0x21, 0 - .dw 0x5240, 0xc11e, 0x527f, 0xc11e, 0x21, 0 - .dw 0x52c0, 0xc11e, 0x52ff, 0xc11e, 0x21, 0 - .dw 0x5340, 0xc11e, 0x537f, 0xc11e, 0x21, 0 - .dw 0x53c0, 0xc11e, 0x53ff, 0xc11e, 0x21, 0 - .dw 0x5440, 0xc11e, 0x547f, 0xc11e, 0x21, 0 - .dw 0x54c0, 0xc11e, 0x54ff, 0xc11e, 0x21, 0 - .dw 0x5540, 0xc11e, 0x557f, 0xc11e, 0x21, 0 - .dw 0x55c0, 0xc11e, 0x55ff, 0xc11e, 0x21, 0 - .dw 0x5640, 0xc11e, 0x567f, 0xc11e, 0x21, 0 - .dw 0x56c0, 0xc11e, 0x56ff, 0xc11e, 0x21, 0 - .dw 0x5740, 0xc11e, 0x577f, 0xc11e, 0x21, 0 - .dw 0x57c0, 0xc11e, 0x57ff, 0xc11e, 0x21, 0 - .dw 0x5840, 0xc11e, 0x587f, 0xc11e, 0x21, 0 - .dw 0x58c0, 0xc11e, 0x58ff, 0xc11e, 0x21, 0 - .dw 0x5940, 0xc11e, 0x597f, 0xc11e, 0x21, 0 - .dw 0x59c0, 0xc11e, 0x5fff, 0xc11e, 0x21, 0 - .dw 0x6040, 0xc11e, 0x607f, 0xc11e, 0x21, 0 - .dw 0x60c0, 0xc11e, 0x60ff, 0xc11e, 0x21, 0 - .dw 0x6140, 0xc11e, 0x617f, 0xc11e, 0x21, 0 - .dw 0x61c0, 0xc11e, 0x61ff, 0xc11e, 0x21, 0 - .dw 0x6240, 0xc11e, 0x627f, 0xc11e, 0x21, 0 - .dw 0x62c0, 0xc11e, 0x62ff, 0xc11e, 0x21, 0 - .dw 0x6340, 0xc11e, 0x637f, 0xc11e, 0x21, 0 - .dw 0x63c0, 0xc11e, 0x63ff, 0xc11e, 0x21, 0 - .dw 0x6440, 0xc11e, 0x647f, 0xc11e, 0x21, 0 - .dw 0x64c0, 0xc11e, 0x64ff, 0xc11e, 0x21, 0 - .dw 0x6540, 0xc11e, 0x657f, 0xc11e, 0x21, 0 - .dw 0x65c0, 0xc11e, 0x65ff, 0xc11e, 0x21, 0 - .dw 0x6640, 0xc11e, 0x667f, 0xc11e, 0x21, 0 - .dw 0x66c0, 0xc11e, 0x66ff, 0xc11e, 0x21, 0 - .dw 0x6740, 0xc11e, 0x677f, 0xc11e, 0x21, 0 - .dw 0x67c0, 0xc11e, 0x67ff, 0xc11e, 0x21, 0 - .dw 0x6840, 0xc11e, 0x687f, 0xc11e, 0x21, 0 - .dw 0x68c0, 0xc11e, 0x68ff, 0xc11e, 0x21, 0 - .dw 0x6940, 0xc11e, 0x697f, 0xc11e, 0x21, 0 - .dw 0x69c0, 0xc11e, 0x69ff, 0xc11e, 0x21, 0 - .dw 0x6a40, 0xc11e, 0x6a7f, 0xc11e, 0x21, 0 - .dw 0x6ac0, 0xc11e, 0x6aff, 0xc11e, 0x21, 0 - .dw 0x6b40, 0xc11e, 0x6b7f, 0xc11e, 0x21, 0 - .dw 0x6bc0, 0xc11e, 0x6bff, 0xc11e, 0x21, 0 - .dw 0x6c40, 0xc11e, 0x6c7f, 0xc11e, 0x21, 0 - .dw 0x6cc0, 0xc11e, 0x6cff, 0xc11e, 0x21, 0 - .dw 0x6d40, 0xc11e, 0x6d7f, 0xc11e, 0x21, 0 - .dw 0x6dc0, 0xc11e, 0x6dff, 0xc11e, 0x21, 0 - .dw 0x6e40, 0xc11e, 0x6e7f, 0xc11e, 0x21, 0 - .dw 0x6ec0, 0xc11e, 0x6eff, 0xc11e, 0x21, 0 - .dw 0x6f40, 0xc11e, 0x6f7f, 0xc11e, 0x21, 0 - .dw 0x6fc0, 0xc11e, 0x6fff, 0xc11e, 0x21, 0 - .dw 0x7040, 0xc11e, 0x707f, 0xc11e, 0x21, 0 - .dw 0x70c0, 0xc11e, 0x70ff, 0xc11e, 0x21, 0 - .dw 0x7140, 0xc11e, 0x717f, 0xc11e, 0x21, 0 - .dw 0x71c0, 0xc11e, 0x71ff, 0xc11e, 0x21, 0 - .dw 0x7240, 0xc11e, 0x727f, 0xc11e, 0x21, 0 - .dw 0x72c0, 0xc11e, 0x72ff, 0xc11e, 0x21, 0 - .dw 0x7340, 0xc11e, 0x737f, 0xc11e, 0x21, 0 - .dw 0x73c0, 0xc11e, 0x73ff, 0xc11e, 0x21, 0 - .dw 0x7440, 0xc11e, 0x747f, 0xc11e, 0x21, 0 - .dw 0x74c0, 0xc11e, 0x74ff, 0xc11e, 0x21, 0 - .dw 0x7540, 0xc11e, 0x757f, 0xc11e, 0x21, 0 - .dw 0x75c0, 0xc11e, 0x75ff, 0xc11e, 0x21, 0 - .dw 0x7640, 0xc11e, 0x767f, 0xc11e, 0x21, 0 - .dw 0x76c0, 0xc11e, 0x76ff, 0xc11e, 0x21, 0 - .dw 0x7740, 0xc11e, 0x777f, 0xc11e, 0x21, 0 - .dw 0x77c0, 0xc11e, 0x77ff, 0xc11e, 0x21, 0 - .dw 0x7840, 0xc11e, 0x787f, 0xc11e, 0x21, 0 - .dw 0x78c0, 0xc11e, 0x78ff, 0xc11e, 0x21, 0 - .dw 0x7940, 0xc11e, 0x797f, 0xc11e, 0x21, 0 - .dw 0x79c0, 0xc11e, 0x7fff, 0xc11e, 0x21, 0 - .dw 0x8040, 0xc11e, 0x807f, 0xc11e, 0x21, 0 - .dw 0x80c0, 0xc11e, 0x80ff, 0xc11e, 0x21, 0 - .dw 0x8140, 0xc11e, 0x817f, 0xc11e, 0x21, 0 - .dw 0x81c0, 0xc11e, 0x81ff, 0xc11e, 0x21, 0 - .dw 0x8240, 0xc11e, 0x827f, 0xc11e, 0x21, 0 - .dw 0x82c0, 0xc11e, 0x82ff, 0xc11e, 0x21, 0 - .dw 0x8340, 0xc11e, 0x837f, 0xc11e, 0x21, 0 - .dw 0x83c0, 0xc11e, 0x83ff, 0xc11e, 0x21, 0 - .dw 0x8440, 0xc11e, 0x847f, 0xc11e, 0x21, 0 - .dw 0x84c0, 0xc11e, 0x84ff, 0xc11e, 0x21, 0 - .dw 0x8540, 0xc11e, 0x857f, 0xc11e, 0x21, 0 - .dw 0x85c0, 0xc11e, 0x85ff, 0xc11e, 0x21, 0 - .dw 0x8640, 0xc11e, 0x867f, 0xc11e, 0x21, 0 - .dw 0x86c0, 0xc11e, 0x86ff, 0xc11e, 0x21, 0 - .dw 0x8740, 0xc11e, 0x877f, 0xc11e, 0x21, 0 - .dw 0x87c0, 0xc11e, 0x87ff, 0xc11e, 0x21, 0 - .dw 0x8840, 0xc11e, 0x887f, 0xc11e, 0x21, 0 - .dw 0x88c0, 0xc11e, 0x88ff, 0xc11e, 0x21, 0 - .dw 0x8940, 0xc11e, 0x897f, 0xc11e, 0x21, 0 - .dw 0x89c0, 0xc11e, 0x89ff, 0xc11e, 0x21, 0 - .dw 0x8a40, 0xc11e, 0x8a7f, 0xc11e, 0x21, 0 - .dw 0x8ac0, 0xc11e, 0x8aff, 0xc11e, 0x21, 0 - .dw 0x8b40, 0xc11e, 0x8b7f, 0xc11e, 0x21, 0 - .dw 0x8bc0, 0xc11e, 0x8bff, 0xc11e, 0x21, 0 - .dw 0x8c40, 0xc11e, 0x8c7f, 0xc11e, 0x21, 0 - .dw 0x8cc0, 0xc11e, 0x8cff, 0xc11e, 0x21, 0 - .dw 0x8d40, 0xc11e, 0x8d7f, 0xc11e, 0x21, 0 - .dw 0x8dc0, 0xc11e, 0x8dff, 0xc11e, 0x21, 0 - .dw 0x8e40, 0xc11e, 0x8e7f, 0xc11e, 0x21, 0 - .dw 0x8ec0, 0xc11e, 0x8eff, 0xc11e, 0x21, 0 - .dw 0x8f40, 0xc11e, 0x8f7f, 0xc11e, 0x21, 0 - .dw 0x8fc0, 0xc11e, 0x8fff, 0xc11e, 0x21, 0 - .dw 0x9040, 0xc11e, 0x907f, 0xc11e, 0x21, 0 - .dw 0x90c0, 0xc11e, 0x90ff, 0xc11e, 0x21, 0 - .dw 0x9140, 0xc11e, 0x917f, 0xc11e, 0x21, 0 - .dw 0x91c0, 0xc11e, 0x91ff, 0xc11e, 0x21, 0 - .dw 0x9240, 0xc11e, 0x927f, 0xc11e, 0x21, 0 - .dw 0x92c0, 0xc11e, 0x92ff, 0xc11e, 0x21, 0 - .dw 0x9340, 0xc11e, 0x937f, 0xc11e, 0x21, 0 - .dw 0x93c0, 0xc11e, 0x93ff, 0xc11e, 0x21, 0 - .dw 0x9440, 0xc11e, 0x947f, 0xc11e, 0x21, 0 - .dw 0x94c0, 0xc11e, 0x94ff, 0xc11e, 0x21, 0 - .dw 0x9540, 0xc11e, 0x957f, 0xc11e, 0x21, 0 - .dw 0x95c0, 0xc11e, 0x95ff, 0xc11e, 0x21, 0 - .dw 0x9640, 0xc11e, 0x967f, 0xc11e, 0x21, 0 - .dw 0x96c0, 0xc11e, 0x96ff, 0xc11e, 0x21, 0 - .dw 0x9740, 0xc11e, 0x977f, 0xc11e, 0x21, 0 - .dw 0x97c0, 0xc11e, 0x97ff, 0xc11e, 0x21, 0 - .dw 0x9840, 0xc11e, 0x987f, 0xc11e, 0x21, 0 - .dw 0x98c0, 0xc11e, 0x98ff, 0xc11e, 0x21, 0 - .dw 0x9940, 0xc11e, 0x997f, 0xc11e, 0x21, 0 - .dw 0x99c0, 0xc11e, 0x9fff, 0xc11e, 0x21, 0 - .dw 0xa040, 0xc11e, 0xa07f, 0xc11e, 0x21, 0 - .dw 0xa0c0, 0xc11e, 0xa0ff, 0xc11e, 0x21, 0 - .dw 0xa140, 0xc11e, 0xa17f, 0xc11e, 0x21, 0 - .dw 0xa1c0, 0xc11e, 0xa1ff, 0xc11e, 0x21, 0 - .dw 0xa240, 0xc11e, 0xa27f, 0xc11e, 0x21, 0 - .dw 0xa2c0, 0xc11e, 0xa2ff, 0xc11e, 0x21, 0 - .dw 0xa340, 0xc11e, 0xa37f, 0xc11e, 0x21, 0 - .dw 0xa3c0, 0xc11e, 0xa3ff, 0xc11e, 0x21, 0 - .dw 0xa440, 0xc11e, 0xa47f, 0xc11e, 0x21, 0 - .dw 0xa4c0, 0xc11e, 0xa4ff, 0xc11e, 0x21, 0 - .dw 0xa540, 0xc11e, 0xa57f, 0xc11e, 0x21, 0 - .dw 0xa5c0, 0xc11e, 0xa5ff, 0xc11e, 0x21, 0 - .dw 0xa640, 0xc11e, 0xa67f, 0xc11e, 0x21, 0 - .dw 0xa6c0, 0xc11e, 0xa6ff, 0xc11e, 0x21, 0 - .dw 0xa740, 0xc11e, 0xa77f, 0xc11e, 0x21, 0 - .dw 0xa7c0, 0xc11e, 0xa7ff, 0xc11e, 0x21, 0 - .dw 0xa840, 0xc11e, 0xa87f, 0xc11e, 0x21, 0 - .dw 0xa8c0, 0xc11e, 0xa8ff, 0xc11e, 0x21, 0 - .dw 0xa940, 0xc11e, 0xa97f, 0xc11e, 0x21, 0 - .dw 0xa9c0, 0xc11e, 0xa9ff, 0xc11e, 0x21, 0 - .dw 0xaa40, 0xc11e, 0xaa7f, 0xc11e, 0x21, 0 - .dw 0xaac0, 0xc11e, 0xaaff, 0xc11e, 0x21, 0 - .dw 0xab40, 0xc11e, 0xab7f, 0xc11e, 0x21, 0 - .dw 0xabc0, 0xc11e, 0xabff, 0xc11e, 0x21, 0 - .dw 0xac40, 0xc11e, 0xac7f, 0xc11e, 0x21, 0 - .dw 0xacc0, 0xc11e, 0xacff, 0xc11e, 0x21, 0 - .dw 0xad40, 0xc11e, 0xad7f, 0xc11e, 0x21, 0 - .dw 0xadc0, 0xc11e, 0xadff, 0xc11e, 0x21, 0 - .dw 0xae40, 0xc11e, 0xae7f, 0xc11e, 0x21, 0 - .dw 0xaec0, 0xc11e, 0xaeff, 0xc11e, 0x21, 0 - .dw 0xaf40, 0xc11e, 0xaf7f, 0xc11e, 0x21, 0 - .dw 0xafc0, 0xc11e, 0xafff, 0xc11e, 0x21, 0 - .dw 0xb040, 0xc11e, 0xb07f, 0xc11e, 0x21, 0 - .dw 0xb0c0, 0xc11e, 0xb0ff, 0xc11e, 0x21, 0 - .dw 0xb140, 0xc11e, 0xb17f, 0xc11e, 0x21, 0 - .dw 0xb1c0, 0xc11e, 0xb1ff, 0xc11e, 0x21, 0 - .dw 0xb240, 0xc11e, 0xb27f, 0xc11e, 0x21, 0 - .dw 0xb2c0, 0xc11e, 0xb2ff, 0xc11e, 0x21, 0 - .dw 0xb340, 0xc11e, 0xb37f, 0xc11e, 0x21, 0 - .dw 0xb3c0, 0xc11e, 0xb3ff, 0xc11e, 0x21, 0 - .dw 0xb440, 0xc11e, 0xb47f, 0xc11e, 0x21, 0 - .dw 0xb4c0, 0xc11e, 0xb4ff, 0xc11e, 0x21, 0 - .dw 0xb540, 0xc11e, 0xb57f, 0xc11e, 0x21, 0 - .dw 0xb5c0, 0xc11e, 0xb5ff, 0xc11e, 0x21, 0 - .dw 0xb640, 0xc11e, 0xb67f, 0xc11e, 0x21, 0 - .dw 0xb6c0, 0xc11e, 0xb6ff, 0xc11e, 0x21, 0 - .dw 0xb740, 0xc11e, 0xb77f, 0xc11e, 0x21, 0 - .dw 0xb7c0, 0xc11e, 0xb7ff, 0xc11e, 0x21, 0 - .dw 0xb840, 0xc11e, 0xb87f, 0xc11e, 0x21, 0 - .dw 0xb8c0, 0xc11e, 0xb8ff, 0xc11e, 0x21, 0 - .dw 0xb940, 0xc11e, 0xb97f, 0xc11e, 0x21, 0 - .dw 0xb9c0, 0xc11e, 0xbfff, 0xc11e, 0x21, 0 - .dw 0xc040, 0xc11e, 0xc07f, 0xc11e, 0x21, 0 - .dw 0xc0c0, 0xc11e, 0xc0ff, 0xc11e, 0x21, 0 - .dw 0xc140, 0xc11e, 0xc17f, 0xc11e, 0x21, 0 - .dw 0xc1c0, 0xc11e, 0xc1ff, 0xc11e, 0x21, 0 - .dw 0xc240, 0xc11e, 0xc27f, 0xc11e, 0x21, 0 - .dw 0xc2c0, 0xc11e, 0xc2ff, 0xc11e, 0x21, 0 - .dw 0xc340, 0xc11e, 0xc37f, 0xc11e, 0x21, 0 - .dw 0xc3c0, 0xc11e, 0xc3ff, 0xc11e, 0x21, 0 - .dw 0xc440, 0xc11e, 0xc47f, 0xc11e, 0x21, 0 - .dw 0xc4c0, 0xc11e, 0xc4ff, 0xc11e, 0x21, 0 - .dw 0xc540, 0xc11e, 0xc57f, 0xc11e, 0x21, 0 - .dw 0xc5c0, 0xc11e, 0xc5ff, 0xc11e, 0x21, 0 - .dw 0xc640, 0xc11e, 0xc67f, 0xc11e, 0x21, 0 - .dw 0xc6c0, 0xc11e, 0xc6ff, 0xc11e, 0x21, 0 - .dw 0xc740, 0xc11e, 0xc77f, 0xc11e, 0x21, 0 - .dw 0xc7c0, 0xc11e, 0xc7ff, 0xc11e, 0x21, 0 - .dw 0xc840, 0xc11e, 0xc87f, 0xc11e, 0x21, 0 - .dw 0xc8c0, 0xc11e, 0xc8ff, 0xc11e, 0x21, 0 - .dw 0xc940, 0xc11e, 0xc97f, 0xc11e, 0x21, 0 - .dw 0xc9c0, 0xc11e, 0xc9ff, 0xc11e, 0x21, 0 - .dw 0xca40, 0xc11e, 0xca7f, 0xc11e, 0x21, 0 - .dw 0xcac0, 0xc11e, 0xcaff, 0xc11e, 0x21, 0 - .dw 0xcb40, 0xc11e, 0xcb7f, 0xc11e, 0x21, 0 - .dw 0xcbc0, 0xc11e, 0xcbff, 0xc11e, 0x21, 0 - .dw 0xcc40, 0xc11e, 0xcc7f, 0xc11e, 0x21, 0 - .dw 0xccc0, 0xc11e, 0xccff, 0xc11e, 0x21, 0 - .dw 0xcd40, 0xc11e, 0xcd7f, 0xc11e, 0x21, 0 - .dw 0xcdc0, 0xc11e, 0xcdff, 0xc11e, 0x21, 0 - .dw 0xce40, 0xc11e, 0xce7f, 0xc11e, 0x21, 0 - .dw 0xcec0, 0xc11e, 0xceff, 0xc11e, 0x21, 0 - .dw 0xcf40, 0xc11e, 0xcf7f, 0xc11e, 0x21, 0 - .dw 0xcfc0, 0xc11e, 0xcfff, 0xc11e, 0x21, 0 - .dw 0xd040, 0xc11e, 0xd07f, 0xc11e, 0x21, 0 - .dw 0xd0c0, 0xc11e, 0xd0ff, 0xc11e, 0x21, 0 - .dw 0xd140, 0xc11e, 0xd17f, 0xc11e, 0x21, 0 - .dw 0xd1c0, 0xc11e, 0xd1ff, 0xc11e, 0x21, 0 - .dw 0xd240, 0xc11e, 0xd27f, 0xc11e, 0x21, 0 - .dw 0xd2c0, 0xc11e, 0xd2ff, 0xc11e, 0x21, 0 - .dw 0xd340, 0xc11e, 0xd37f, 0xc11e, 0x21, 0 - .dw 0xd3c0, 0xc11e, 0xd3ff, 0xc11e, 0x21, 0 - .dw 0xd440, 0xc11e, 0xd47f, 0xc11e, 0x21, 0 - .dw 0xd4c0, 0xc11e, 0xd4ff, 0xc11e, 0x21, 0 - .dw 0xd540, 0xc11e, 0xd57f, 0xc11e, 0x21, 0 - .dw 0xd5c0, 0xc11e, 0xd5ff, 0xc11e, 0x21, 0 - .dw 0xd640, 0xc11e, 0xd67f, 0xc11e, 0x21, 0 - .dw 0xd6c0, 0xc11e, 0xd6ff, 0xc11e, 0x21, 0 - .dw 0xd740, 0xc11e, 0xd77f, 0xc11e, 0x21, 0 - .dw 0xd7c0, 0xc11e, 0xd7ff, 0xc11e, 0x21, 0 - .dw 0xd840, 0xc11e, 0xd87f, 0xc11e, 0x21, 0 - .dw 0xd8c0, 0xc11e, 0xd8ff, 0xc11e, 0x21, 0 - .dw 0xd940, 0xc11e, 0xd97f, 0xc11e, 0x21, 0 - .dw 0xd9c0, 0xc11e, 0xdfff, 0xc11e, 0x21, 0 - .dw 0xe040, 0xc11e, 0xe07f, 0xc11e, 0x21, 0 - .dw 0xe0c0, 0xc11e, 0xe0ff, 0xc11e, 0x21, 0 - .dw 0xe140, 0xc11e, 0xe17f, 0xc11e, 0x21, 0 - .dw 0xe1c0, 0xc11e, 0xe1ff, 0xc11e, 0x21, 0 - .dw 0xe240, 0xc11e, 0xe27f, 0xc11e, 0x21, 0 - .dw 0xe2c0, 0xc11e, 0xe2ff, 0xc11e, 0x21, 0 - .dw 0xe340, 0xc11e, 0xe37f, 0xc11e, 0x21, 0 - .dw 0xe3c0, 0xc11e, 0xe3ff, 0xc11e, 0x21, 0 - .dw 0xe440, 0xc11e, 0xe47f, 0xc11e, 0x21, 0 - .dw 0xe4c0, 0xc11e, 0xe4ff, 0xc11e, 0x21, 0 - .dw 0xe540, 0xc11e, 0xe57f, 0xc11e, 0x21, 0 - .dw 0xe5c0, 0xc11e, 0xe5ff, 0xc11e, 0x21, 0 - .dw 0xe640, 0xc11e, 0xe67f, 0xc11e, 0x21, 0 - .dw 0xe6c0, 0xc11e, 0xe6ff, 0xc11e, 0x21, 0 - .dw 0xe740, 0xc11e, 0xe77f, 0xc11e, 0x21, 0 - .dw 0xe7c0, 0xc11e, 0xe7ff, 0xc11e, 0x21, 0 - .dw 0xe840, 0xc11e, 0xe87f, 0xc11e, 0x21, 0 - .dw 0xe8c0, 0xc11e, 0xe8ff, 0xc11e, 0x21, 0 - .dw 0xe940, 0xc11e, 0xe97f, 0xc11e, 0x21, 0 - .dw 0xe9c0, 0xc11e, 0xe9ff, 0xc11e, 0x21, 0 - .dw 0xea40, 0xc11e, 0xea7f, 0xc11e, 0x21, 0 - .dw 0xeac0, 0xc11e, 0xeaff, 0xc11e, 0x21, 0 - .dw 0xeb40, 0xc11e, 0xeb7f, 0xc11e, 0x21, 0 - .dw 0xebc0, 0xc11e, 0xebff, 0xc11e, 0x21, 0 - .dw 0xec40, 0xc11e, 0xec7f, 0xc11e, 0x21, 0 - .dw 0xecc0, 0xc11e, 0xecff, 0xc11e, 0x21, 0 - .dw 0xed40, 0xc11e, 0xed7f, 0xc11e, 0x21, 0 - .dw 0xedc0, 0xc11e, 0xedff, 0xc11e, 0x21, 0 - .dw 0xee40, 0xc11e, 0xee7f, 0xc11e, 0x21, 0 - .dw 0xeec0, 0xc11e, 0xeeff, 0xc11e, 0x21, 0 - .dw 0xef40, 0xc11e, 0xef7f, 0xc11e, 0x21, 0 - .dw 0xefc0, 0xc11e, 0xefff, 0xc11e, 0x21, 0 - .dw 0xf040, 0xc11e, 0xf07f, 0xc11e, 0x21, 0 - .dw 0xf0c0, 0xc11e, 0xf0ff, 0xc11e, 0x21, 0 - .dw 0xf140, 0xc11e, 0xf17f, 0xc11e, 0x21, 0 - .dw 0xf1c0, 0xc11e, 0xf1ff, 0xc11e, 0x21, 0 - .dw 0xf240, 0xc11e, 0xf27f, 0xc11e, 0x21, 0 - .dw 0xf2c0, 0xc11e, 0xf2ff, 0xc11e, 0x21, 0 - .dw 0xf340, 0xc11e, 0xf37f, 0xc11e, 0x21, 0 - .dw 0xf3c0, 0xc11e, 0xf3ff, 0xc11e, 0x21, 0 - .dw 0xf440, 0xc11e, 0xf47f, 0xc11e, 0x21, 0 - .dw 0xf4c0, 0xc11e, 0xf4ff, 0xc11e, 0x21, 0 - .dw 0xf540, 0xc11e, 0xf57f, 0xc11e, 0x21, 0 - .dw 0xf5c0, 0xc11e, 0xf5ff, 0xc11e, 0x21, 0 - .dw 0xf640, 0xc11e, 0xf67f, 0xc11e, 0x21, 0 - .dw 0xf6c0, 0xc11e, 0xf6ff, 0xc11e, 0x21, 0 - .dw 0xf740, 0xc11e, 0xf77f, 0xc11e, 0x21, 0 - .dw 0xf7c0, 0xc11e, 0xf7ff, 0xc11e, 0x21, 0 - .dw 0xf840, 0xc11e, 0xf87f, 0xc11e, 0x21, 0 - .dw 0xf8c0, 0xc11e, 0xf8ff, 0xc11e, 0x21, 0 - .dw 0xf940, 0xc11e, 0xf97f, 0xc11e, 0x21, 0 - .dw 0xf9c0, 0xc11e, 0xffff, 0xc11e, 0x21, 0 - .dw 0x0040, 0xc11f, 0x007f, 0xc11f, 0x21, 0 - .dw 0x00c0, 0xc11f, 0x00ff, 0xc11f, 0x21, 0 - .dw 0x0140, 0xc11f, 0x017f, 0xc11f, 0x21, 0 - .dw 0x01c0, 0xc11f, 0x01ff, 0xc11f, 0x21, 0 - .dw 0x0240, 0xc11f, 0x027f, 0xc11f, 0x21, 0 - .dw 0x02c0, 0xc11f, 0x02ff, 0xc11f, 0x21, 0 - .dw 0x0340, 0xc11f, 0x037f, 0xc11f, 0x21, 0 - .dw 0x03c0, 0xc11f, 0x03ff, 0xc11f, 0x21, 0 - .dw 0x0440, 0xc11f, 0x047f, 0xc11f, 0x21, 0 - .dw 0x04c0, 0xc11f, 0x04ff, 0xc11f, 0x21, 0 - .dw 0x0540, 0xc11f, 0x057f, 0xc11f, 0x21, 0 - .dw 0x05c0, 0xc11f, 0x05ff, 0xc11f, 0x21, 0 - .dw 0x0640, 0xc11f, 0x067f, 0xc11f, 0x21, 0 - .dw 0x06c0, 0xc11f, 0x06ff, 0xc11f, 0x21, 0 - .dw 0x0740, 0xc11f, 0x077f, 0xc11f, 0x21, 0 - .dw 0x07c0, 0xc11f, 0x07ff, 0xc11f, 0x21, 0 - .dw 0x0840, 0xc11f, 0x087f, 0xc11f, 0x21, 0 - .dw 0x08c0, 0xc11f, 0x08ff, 0xc11f, 0x21, 0 - .dw 0x0940, 0xc11f, 0x097f, 0xc11f, 0x21, 0 - .dw 0x09c0, 0xc11f, 0x09ff, 0xc11f, 0x21, 0 - .dw 0x0a40, 0xc11f, 0x0a7f, 0xc11f, 0x21, 0 - .dw 0x0ac0, 0xc11f, 0x0aff, 0xc11f, 0x21, 0 - .dw 0x0b40, 0xc11f, 0x0b7f, 0xc11f, 0x21, 0 - .dw 0x0bc0, 0xc11f, 0x0bff, 0xc11f, 0x21, 0 - .dw 0x0c40, 0xc11f, 0x0c7f, 0xc11f, 0x21, 0 - .dw 0x0cc0, 0xc11f, 0x0cff, 0xc11f, 0x21, 0 - .dw 0x0d40, 0xc11f, 0x0d7f, 0xc11f, 0x21, 0 - .dw 0x0dc0, 0xc11f, 0x0dff, 0xc11f, 0x21, 0 - .dw 0x0e40, 0xc11f, 0x0e7f, 0xc11f, 0x21, 0 - .dw 0x0ec0, 0xc11f, 0x0eff, 0xc11f, 0x21, 0 - .dw 0x0f40, 0xc11f, 0x0f7f, 0xc11f, 0x21, 0 - .dw 0x0fc0, 0xc11f, 0x0fff, 0xc11f, 0x21, 0 - .dw 0x1040, 0xc11f, 0x107f, 0xc11f, 0x21, 0 - .dw 0x10c0, 0xc11f, 0x10ff, 0xc11f, 0x21, 0 - .dw 0x1140, 0xc11f, 0x117f, 0xc11f, 0x21, 0 - .dw 0x11c0, 0xc11f, 0x11ff, 0xc11f, 0x21, 0 - .dw 0x1240, 0xc11f, 0x127f, 0xc11f, 0x21, 0 - .dw 0x12c0, 0xc11f, 0x12ff, 0xc11f, 0x21, 0 - .dw 0x1340, 0xc11f, 0x137f, 0xc11f, 0x21, 0 - .dw 0x13c0, 0xc11f, 0x13ff, 0xc11f, 0x21, 0 - .dw 0x1440, 0xc11f, 0x147f, 0xc11f, 0x21, 0 - .dw 0x14c0, 0xc11f, 0x14ff, 0xc11f, 0x21, 0 - .dw 0x1540, 0xc11f, 0x157f, 0xc11f, 0x21, 0 - .dw 0x15c0, 0xc11f, 0x15ff, 0xc11f, 0x21, 0 - .dw 0x1640, 0xc11f, 0x167f, 0xc11f, 0x21, 0 - .dw 0x16c0, 0xc11f, 0x16ff, 0xc11f, 0x21, 0 - .dw 0x1740, 0xc11f, 0x177f, 0xc11f, 0x21, 0 - .dw 0x17c0, 0xc11f, 0x17ff, 0xc11f, 0x21, 0 - .dw 0x1840, 0xc11f, 0x187f, 0xc11f, 0x21, 0 - .dw 0x18c0, 0xc11f, 0x18ff, 0xc11f, 0x21, 0 - .dw 0x1940, 0xc11f, 0x197f, 0xc11f, 0x21, 0 - .dw 0x19c0, 0xc11f, 0x1fff, 0xc11f, 0x21, 0 - .dw 0x2040, 0xc11f, 0x207f, 0xc11f, 0x21, 0 - .dw 0x20c0, 0xc11f, 0x20ff, 0xc11f, 0x21, 0 - .dw 0x2140, 0xc11f, 0x217f, 0xc11f, 0x21, 0 - .dw 0x21c0, 0xc11f, 0x21ff, 0xc11f, 0x21, 0 - .dw 0x2240, 0xc11f, 0x227f, 0xc11f, 0x21, 0 - .dw 0x22c0, 0xc11f, 0x22ff, 0xc11f, 0x21, 0 - .dw 0x2340, 0xc11f, 0x237f, 0xc11f, 0x21, 0 - .dw 0x23c0, 0xc11f, 0x23ff, 0xc11f, 0x21, 0 - .dw 0x2440, 0xc11f, 0x247f, 0xc11f, 0x21, 0 - .dw 0x24c0, 0xc11f, 0x24ff, 0xc11f, 0x21, 0 - .dw 0x2540, 0xc11f, 0x257f, 0xc11f, 0x21, 0 - .dw 0x25c0, 0xc11f, 0x25ff, 0xc11f, 0x21, 0 - .dw 0x2640, 0xc11f, 0x267f, 0xc11f, 0x21, 0 - .dw 0x26c0, 0xc11f, 0x26ff, 0xc11f, 0x21, 0 - .dw 0x2740, 0xc11f, 0x277f, 0xc11f, 0x21, 0 - .dw 0x27c0, 0xc11f, 0x27ff, 0xc11f, 0x21, 0 - .dw 0x2840, 0xc11f, 0x287f, 0xc11f, 0x21, 0 - .dw 0x28c0, 0xc11f, 0x28ff, 0xc11f, 0x21, 0 - .dw 0x2940, 0xc11f, 0x297f, 0xc11f, 0x21, 0 - .dw 0x29c0, 0xc11f, 0x29ff, 0xc11f, 0x21, 0 - .dw 0x2a40, 0xc11f, 0x2a7f, 0xc11f, 0x21, 0 - .dw 0x2ac0, 0xc11f, 0x2aff, 0xc11f, 0x21, 0 - .dw 0x2b40, 0xc11f, 0x2b7f, 0xc11f, 0x21, 0 - .dw 0x2bc0, 0xc11f, 0x2bff, 0xc11f, 0x21, 0 - .dw 0x2c40, 0xc11f, 0x2c7f, 0xc11f, 0x21, 0 - .dw 0x2cc0, 0xc11f, 0x2cff, 0xc11f, 0x21, 0 - .dw 0x2d40, 0xc11f, 0x2d7f, 0xc11f, 0x21, 0 - .dw 0x2dc0, 0xc11f, 0x2dff, 0xc11f, 0x21, 0 - .dw 0x2e40, 0xc11f, 0x2e7f, 0xc11f, 0x21, 0 - .dw 0x2ec0, 0xc11f, 0x2eff, 0xc11f, 0x21, 0 - .dw 0x2f40, 0xc11f, 0x2f7f, 0xc11f, 0x21, 0 - .dw 0x2fc0, 0xc11f, 0x2fff, 0xc11f, 0x21, 0 - .dw 0x3040, 0xc11f, 0x307f, 0xc11f, 0x21, 0 - .dw 0x30c0, 0xc11f, 0x30ff, 0xc11f, 0x21, 0 - .dw 0x3140, 0xc11f, 0x317f, 0xc11f, 0x21, 0 - .dw 0x31c0, 0xc11f, 0x31ff, 0xc11f, 0x21, 0 - .dw 0x3240, 0xc11f, 0x327f, 0xc11f, 0x21, 0 - .dw 0x32c0, 0xc11f, 0x32ff, 0xc11f, 0x21, 0 - .dw 0x3340, 0xc11f, 0x337f, 0xc11f, 0x21, 0 - .dw 0x33c0, 0xc11f, 0x33ff, 0xc11f, 0x21, 0 - .dw 0x3440, 0xc11f, 0x347f, 0xc11f, 0x21, 0 - .dw 0x34c0, 0xc11f, 0x34ff, 0xc11f, 0x21, 0 - .dw 0x3540, 0xc11f, 0x357f, 0xc11f, 0x21, 0 - .dw 0x35c0, 0xc11f, 0x35ff, 0xc11f, 0x21, 0 - .dw 0x3640, 0xc11f, 0x367f, 0xc11f, 0x21, 0 - .dw 0x36c0, 0xc11f, 0x36ff, 0xc11f, 0x21, 0 - .dw 0x3740, 0xc11f, 0x377f, 0xc11f, 0x21, 0 - .dw 0x37c0, 0xc11f, 0x37ff, 0xc11f, 0x21, 0 - .dw 0x3840, 0xc11f, 0x387f, 0xc11f, 0x21, 0 - .dw 0x38c0, 0xc11f, 0x38ff, 0xc11f, 0x21, 0 - .dw 0x3940, 0xc11f, 0x397f, 0xc11f, 0x21, 0 - .dw 0x39c0, 0xc11f, 0x1fff, 0xc120, 0x21, 0 - .dw 0x3a00, 0xc120, 0x5fff, 0xc120, 0x21, 0 - .dw 0x7a00, 0xc120, 0x9fff, 0xc120, 0x21, 0 - .dw 0xba00, 0xc120, 0xdfff, 0xc120, 0x21, 0 - .dw 0xfa00, 0xc120, 0x1fff, 0xc121, 0x21, 0 - .dw 0x3a00, 0xc121, 0x5fff, 0xc121, 0x21, 0 - .dw 0x7a00, 0xc121, 0x9fff, 0xc121, 0x21, 0 - .dw 0xba00, 0xc121, 0xdfff, 0xc121, 0x21, 0 - .dw 0xfa00, 0xc121, 0x1fff, 0xc122, 0x21, 0 - .dw 0x3a00, 0xc122, 0x5fff, 0xc122, 0x21, 0 - .dw 0x7a00, 0xc122, 0x9fff, 0xc122, 0x21, 0 - .dw 0xba00, 0xc122, 0xdfff, 0xc122, 0x21, 0 - .dw 0xfa00, 0xc122, 0x1fff, 0xc123, 0x21, 0 - .dw 0x3a00, 0xc123, 0xffff, 0xc123, 0x21, 0 - .dw 0x1a00, 0xc124, 0x1fff, 0xc124, 0x21, 0 - .dw 0x3a00, 0xc124, 0x3fff, 0xc124, 0x21, 0 - .dw 0x5a00, 0xc124, 0x5fff, 0xc124, 0x21, 0 - .dw 0x7a00, 0xc124, 0x7fff, 0xc124, 0x21, 0 - .dw 0x9a00, 0xc124, 0x9fff, 0xc124, 0x21, 0 - .dw 0xba00, 0xc124, 0xbfff, 0xc124, 0x21, 0 - .dw 0xda00, 0xc124, 0xdfff, 0xc124, 0x21, 0 - .dw 0xfa00, 0xc124, 0xffff, 0xc124, 0x21, 0 - .dw 0x1a00, 0xc125, 0x1fff, 0xc125, 0x21, 0 - .dw 0x3a00, 0xc125, 0x3fff, 0xc125, 0x21, 0 - .dw 0x5a00, 0xc125, 0x5fff, 0xc125, 0x21, 0 - .dw 0x7a00, 0xc125, 0x7fff, 0xc125, 0x21, 0 - .dw 0x9a00, 0xc125, 0x9fff, 0xc125, 0x21, 0 - .dw 0xba00, 0xc125, 0xbfff, 0xc125, 0x21, 0 - .dw 0xda00, 0xc125, 0xdfff, 0xc125, 0x21, 0 - .dw 0xfa00, 0xc125, 0xffff, 0xc125, 0x21, 0 - .dw 0x1a00, 0xc126, 0x1fff, 0xc126, 0x21, 0 - .dw 0x3a00, 0xc126, 0x3fff, 0xc126, 0x21, 0 - .dw 0x5a00, 0xc126, 0x5fff, 0xc126, 0x21, 0 - .dw 0x7a00, 0xc126, 0x7fff, 0xc126, 0x21, 0 - .dw 0x9a00, 0xc126, 0x9fff, 0xc126, 0x21, 0 - .dw 0xba00, 0xc126, 0xbfff, 0xc126, 0x21, 0 - .dw 0xda00, 0xc126, 0xdfff, 0xc126, 0x21, 0 - .dw 0xfa00, 0xc126, 0xffff, 0xc126, 0x21, 0 - .dw 0x1a00, 0xc127, 0x1fff, 0xc127, 0x21, 0 - .dw 0x3a00, 0xc127, 0x1fff, 0xc128, 0x21, 0 - .dw 0x2040, 0xc128, 0x207f, 0xc128, 0x21, 0 - .dw 0x20c0, 0xc128, 0x20ff, 0xc128, 0x21, 0 - .dw 0x2140, 0xc128, 0x217f, 0xc128, 0x21, 0 - .dw 0x21c0, 0xc128, 0x21ff, 0xc128, 0x21, 0 - .dw 0x2240, 0xc128, 0x227f, 0xc128, 0x21, 0 - .dw 0x22c0, 0xc128, 0x22ff, 0xc128, 0x21, 0 - .dw 0x2340, 0xc128, 0x237f, 0xc128, 0x21, 0 - .dw 0x23c0, 0xc128, 0x23ff, 0xc128, 0x21, 0 - .dw 0x2440, 0xc128, 0x247f, 0xc128, 0x21, 0 - .dw 0x24c0, 0xc128, 0x24ff, 0xc128, 0x21, 0 - .dw 0x2540, 0xc128, 0x257f, 0xc128, 0x21, 0 - .dw 0x25c0, 0xc128, 0x25ff, 0xc128, 0x21, 0 - .dw 0x2640, 0xc128, 0x267f, 0xc128, 0x21, 0 - .dw 0x26c0, 0xc128, 0x26ff, 0xc128, 0x21, 0 - .dw 0x2740, 0xc128, 0x277f, 0xc128, 0x21, 0 - .dw 0x27c0, 0xc128, 0x27ff, 0xc128, 0x21, 0 - .dw 0x2840, 0xc128, 0x287f, 0xc128, 0x21, 0 - .dw 0x28c0, 0xc128, 0x28ff, 0xc128, 0x21, 0 - .dw 0x2940, 0xc128, 0x297f, 0xc128, 0x21, 0 - .dw 0x29c0, 0xc128, 0x29ff, 0xc128, 0x21, 0 - .dw 0x2a40, 0xc128, 0x2a7f, 0xc128, 0x21, 0 - .dw 0x2ac0, 0xc128, 0x2aff, 0xc128, 0x21, 0 - .dw 0x2b40, 0xc128, 0x2b7f, 0xc128, 0x21, 0 - .dw 0x2bc0, 0xc128, 0x2bff, 0xc128, 0x21, 0 - .dw 0x2c40, 0xc128, 0x2c7f, 0xc128, 0x21, 0 - .dw 0x2cc0, 0xc128, 0x2cff, 0xc128, 0x21, 0 - .dw 0x2d40, 0xc128, 0x2d7f, 0xc128, 0x21, 0 - .dw 0x2dc0, 0xc128, 0x2dff, 0xc128, 0x21, 0 - .dw 0x2e40, 0xc128, 0x2e7f, 0xc128, 0x21, 0 - .dw 0x2ec0, 0xc128, 0x2eff, 0xc128, 0x21, 0 - .dw 0x2f40, 0xc128, 0x2f7f, 0xc128, 0x21, 0 - .dw 0x2fc0, 0xc128, 0x2fff, 0xc128, 0x21, 0 - .dw 0x3040, 0xc128, 0x307f, 0xc128, 0x21, 0 - .dw 0x30c0, 0xc128, 0x30ff, 0xc128, 0x21, 0 - .dw 0x3140, 0xc128, 0x317f, 0xc128, 0x21, 0 - .dw 0x31c0, 0xc128, 0x31ff, 0xc128, 0x21, 0 - .dw 0x3240, 0xc128, 0x327f, 0xc128, 0x21, 0 - .dw 0x32c0, 0xc128, 0x32ff, 0xc128, 0x21, 0 - .dw 0x3340, 0xc128, 0x337f, 0xc128, 0x21, 0 - .dw 0x33c0, 0xc128, 0x33ff, 0xc128, 0x21, 0 - .dw 0x3440, 0xc128, 0x347f, 0xc128, 0x21, 0 - .dw 0x34c0, 0xc128, 0x34ff, 0xc128, 0x21, 0 - .dw 0x3540, 0xc128, 0x357f, 0xc128, 0x21, 0 - .dw 0x35c0, 0xc128, 0x35ff, 0xc128, 0x21, 0 - .dw 0x3640, 0xc128, 0x367f, 0xc128, 0x21, 0 - .dw 0x36c0, 0xc128, 0x36ff, 0xc128, 0x21, 0 - .dw 0x3740, 0xc128, 0x377f, 0xc128, 0x21, 0 - .dw 0x37c0, 0xc128, 0x37ff, 0xc128, 0x21, 0 - .dw 0x3840, 0xc128, 0x387f, 0xc128, 0x21, 0 - .dw 0x38c0, 0xc128, 0x38ff, 0xc128, 0x21, 0 - .dw 0x3940, 0xc128, 0x397f, 0xc128, 0x21, 0 - .dw 0x39c0, 0xc128, 0x5fff, 0xc128, 0x21, 0 - .dw 0x6040, 0xc128, 0x607f, 0xc128, 0x21, 0 - .dw 0x60c0, 0xc128, 0x60ff, 0xc128, 0x21, 0 - .dw 0x6140, 0xc128, 0x617f, 0xc128, 0x21, 0 - .dw 0x61c0, 0xc128, 0x61ff, 0xc128, 0x21, 0 - .dw 0x6240, 0xc128, 0x627f, 0xc128, 0x21, 0 - .dw 0x62c0, 0xc128, 0x62ff, 0xc128, 0x21, 0 - .dw 0x6340, 0xc128, 0x637f, 0xc128, 0x21, 0 - .dw 0x63c0, 0xc128, 0x63ff, 0xc128, 0x21, 0 - .dw 0x6440, 0xc128, 0x647f, 0xc128, 0x21, 0 - .dw 0x64c0, 0xc128, 0x64ff, 0xc128, 0x21, 0 - .dw 0x6540, 0xc128, 0x657f, 0xc128, 0x21, 0 - .dw 0x65c0, 0xc128, 0x65ff, 0xc128, 0x21, 0 - .dw 0x6640, 0xc128, 0x667f, 0xc128, 0x21, 0 - .dw 0x66c0, 0xc128, 0x66ff, 0xc128, 0x21, 0 - .dw 0x6740, 0xc128, 0x677f, 0xc128, 0x21, 0 - .dw 0x67c0, 0xc128, 0x67ff, 0xc128, 0x21, 0 - .dw 0x6840, 0xc128, 0x687f, 0xc128, 0x21, 0 - .dw 0x68c0, 0xc128, 0x68ff, 0xc128, 0x21, 0 - .dw 0x6940, 0xc128, 0x697f, 0xc128, 0x21, 0 - .dw 0x69c0, 0xc128, 0x69ff, 0xc128, 0x21, 0 - .dw 0x6a40, 0xc128, 0x6a7f, 0xc128, 0x21, 0 - .dw 0x6ac0, 0xc128, 0x6aff, 0xc128, 0x21, 0 - .dw 0x6b40, 0xc128, 0x6b7f, 0xc128, 0x21, 0 - .dw 0x6bc0, 0xc128, 0x6bff, 0xc128, 0x21, 0 - .dw 0x6c40, 0xc128, 0x6c7f, 0xc128, 0x21, 0 - .dw 0x6cc0, 0xc128, 0x6cff, 0xc128, 0x21, 0 - .dw 0x6d40, 0xc128, 0x6d7f, 0xc128, 0x21, 0 - .dw 0x6dc0, 0xc128, 0x6dff, 0xc128, 0x21, 0 - .dw 0x6e40, 0xc128, 0x6e7f, 0xc128, 0x21, 0 - .dw 0x6ec0, 0xc128, 0x6eff, 0xc128, 0x21, 0 - .dw 0x6f40, 0xc128, 0x6f7f, 0xc128, 0x21, 0 - .dw 0x6fc0, 0xc128, 0x6fff, 0xc128, 0x21, 0 - .dw 0x7040, 0xc128, 0x707f, 0xc128, 0x21, 0 - .dw 0x70c0, 0xc128, 0x70ff, 0xc128, 0x21, 0 - .dw 0x7140, 0xc128, 0x717f, 0xc128, 0x21, 0 - .dw 0x71c0, 0xc128, 0x71ff, 0xc128, 0x21, 0 - .dw 0x7240, 0xc128, 0x727f, 0xc128, 0x21, 0 - .dw 0x72c0, 0xc128, 0x72ff, 0xc128, 0x21, 0 - .dw 0x7340, 0xc128, 0x737f, 0xc128, 0x21, 0 - .dw 0x73c0, 0xc128, 0x73ff, 0xc128, 0x21, 0 - .dw 0x7440, 0xc128, 0x747f, 0xc128, 0x21, 0 - .dw 0x74c0, 0xc128, 0x74ff, 0xc128, 0x21, 0 - .dw 0x7540, 0xc128, 0x757f, 0xc128, 0x21, 0 - .dw 0x75c0, 0xc128, 0x75ff, 0xc128, 0x21, 0 - .dw 0x7640, 0xc128, 0x767f, 0xc128, 0x21, 0 - .dw 0x76c0, 0xc128, 0x76ff, 0xc128, 0x21, 0 - .dw 0x7740, 0xc128, 0x777f, 0xc128, 0x21, 0 - .dw 0x77c0, 0xc128, 0x77ff, 0xc128, 0x21, 0 - .dw 0x7840, 0xc128, 0x787f, 0xc128, 0x21, 0 - .dw 0x78c0, 0xc128, 0x78ff, 0xc128, 0x21, 0 - .dw 0x7940, 0xc128, 0x797f, 0xc128, 0x21, 0 - .dw 0x79c0, 0xc128, 0x9fff, 0xc128, 0x21, 0 - .dw 0xa040, 0xc128, 0xa07f, 0xc128, 0x21, 0 - .dw 0xa0c0, 0xc128, 0xa0ff, 0xc128, 0x21, 0 - .dw 0xa140, 0xc128, 0xa17f, 0xc128, 0x21, 0 - .dw 0xa1c0, 0xc128, 0xa1ff, 0xc128, 0x21, 0 - .dw 0xa240, 0xc128, 0xa27f, 0xc128, 0x21, 0 - .dw 0xa2c0, 0xc128, 0xa2ff, 0xc128, 0x21, 0 - .dw 0xa340, 0xc128, 0xa37f, 0xc128, 0x21, 0 - .dw 0xa3c0, 0xc128, 0xa3ff, 0xc128, 0x21, 0 - .dw 0xa440, 0xc128, 0xa47f, 0xc128, 0x21, 0 - .dw 0xa4c0, 0xc128, 0xa4ff, 0xc128, 0x21, 0 - .dw 0xa540, 0xc128, 0xa57f, 0xc128, 0x21, 0 - .dw 0xa5c0, 0xc128, 0xa5ff, 0xc128, 0x21, 0 - .dw 0xa640, 0xc128, 0xa67f, 0xc128, 0x21, 0 - .dw 0xa6c0, 0xc128, 0xa6ff, 0xc128, 0x21, 0 - .dw 0xa740, 0xc128, 0xa77f, 0xc128, 0x21, 0 - .dw 0xa7c0, 0xc128, 0xa7ff, 0xc128, 0x21, 0 - .dw 0xa840, 0xc128, 0xa87f, 0xc128, 0x21, 0 - .dw 0xa8c0, 0xc128, 0xa8ff, 0xc128, 0x21, 0 - .dw 0xa940, 0xc128, 0xa97f, 0xc128, 0x21, 0 - .dw 0xa9c0, 0xc128, 0xa9ff, 0xc128, 0x21, 0 - .dw 0xaa40, 0xc128, 0xaa7f, 0xc128, 0x21, 0 - .dw 0xaac0, 0xc128, 0xaaff, 0xc128, 0x21, 0 - .dw 0xab40, 0xc128, 0xab7f, 0xc128, 0x21, 0 - .dw 0xabc0, 0xc128, 0xabff, 0xc128, 0x21, 0 - .dw 0xac40, 0xc128, 0xac7f, 0xc128, 0x21, 0 - .dw 0xacc0, 0xc128, 0xacff, 0xc128, 0x21, 0 - .dw 0xad40, 0xc128, 0xad7f, 0xc128, 0x21, 0 - .dw 0xadc0, 0xc128, 0xadff, 0xc128, 0x21, 0 - .dw 0xae40, 0xc128, 0xae7f, 0xc128, 0x21, 0 - .dw 0xaec0, 0xc128, 0xaeff, 0xc128, 0x21, 0 - .dw 0xaf40, 0xc128, 0xaf7f, 0xc128, 0x21, 0 - .dw 0xafc0, 0xc128, 0xafff, 0xc128, 0x21, 0 - .dw 0xb040, 0xc128, 0xb07f, 0xc128, 0x21, 0 - .dw 0xb0c0, 0xc128, 0xb0ff, 0xc128, 0x21, 0 - .dw 0xb140, 0xc128, 0xb17f, 0xc128, 0x21, 0 - .dw 0xb1c0, 0xc128, 0xb1ff, 0xc128, 0x21, 0 - .dw 0xb240, 0xc128, 0xb27f, 0xc128, 0x21, 0 - .dw 0xb2c0, 0xc128, 0xb2ff, 0xc128, 0x21, 0 - .dw 0xb340, 0xc128, 0xb37f, 0xc128, 0x21, 0 - .dw 0xb3c0, 0xc128, 0xb3ff, 0xc128, 0x21, 0 - .dw 0xb440, 0xc128, 0xb47f, 0xc128, 0x21, 0 - .dw 0xb4c0, 0xc128, 0xb4ff, 0xc128, 0x21, 0 - .dw 0xb540, 0xc128, 0xb57f, 0xc128, 0x21, 0 - .dw 0xb5c0, 0xc128, 0xb5ff, 0xc128, 0x21, 0 - .dw 0xb640, 0xc128, 0xb67f, 0xc128, 0x21, 0 - .dw 0xb6c0, 0xc128, 0xb6ff, 0xc128, 0x21, 0 - .dw 0xb740, 0xc128, 0xb77f, 0xc128, 0x21, 0 - .dw 0xb7c0, 0xc128, 0xb7ff, 0xc128, 0x21, 0 - .dw 0xb840, 0xc128, 0xb87f, 0xc128, 0x21, 0 - .dw 0xb8c0, 0xc128, 0xb8ff, 0xc128, 0x21, 0 - .dw 0xb940, 0xc128, 0xb97f, 0xc128, 0x21, 0 - .dw 0xb9c0, 0xc128, 0xdfff, 0xc128, 0x21, 0 - .dw 0xe040, 0xc128, 0xe07f, 0xc128, 0x21, 0 - .dw 0xe0c0, 0xc128, 0xe0ff, 0xc128, 0x21, 0 - .dw 0xe140, 0xc128, 0xe17f, 0xc128, 0x21, 0 - .dw 0xe1c0, 0xc128, 0xe1ff, 0xc128, 0x21, 0 - .dw 0xe240, 0xc128, 0xe27f, 0xc128, 0x21, 0 - .dw 0xe2c0, 0xc128, 0xe2ff, 0xc128, 0x21, 0 - .dw 0xe340, 0xc128, 0xe37f, 0xc128, 0x21, 0 - .dw 0xe3c0, 0xc128, 0xe3ff, 0xc128, 0x21, 0 - .dw 0xe440, 0xc128, 0xe47f, 0xc128, 0x21, 0 - .dw 0xe4c0, 0xc128, 0xe4ff, 0xc128, 0x21, 0 - .dw 0xe540, 0xc128, 0xe57f, 0xc128, 0x21, 0 - .dw 0xe5c0, 0xc128, 0xe5ff, 0xc128, 0x21, 0 - .dw 0xe640, 0xc128, 0xe67f, 0xc128, 0x21, 0 - .dw 0xe6c0, 0xc128, 0xe6ff, 0xc128, 0x21, 0 - .dw 0xe740, 0xc128, 0xe77f, 0xc128, 0x21, 0 - .dw 0xe7c0, 0xc128, 0xe7ff, 0xc128, 0x21, 0 - .dw 0xe840, 0xc128, 0xe87f, 0xc128, 0x21, 0 - .dw 0xe8c0, 0xc128, 0xe8ff, 0xc128, 0x21, 0 - .dw 0xe940, 0xc128, 0xe97f, 0xc128, 0x21, 0 - .dw 0xe9c0, 0xc128, 0xe9ff, 0xc128, 0x21, 0 - .dw 0xea40, 0xc128, 0xea7f, 0xc128, 0x21, 0 - .dw 0xeac0, 0xc128, 0xeaff, 0xc128, 0x21, 0 - .dw 0xeb40, 0xc128, 0xeb7f, 0xc128, 0x21, 0 - .dw 0xebc0, 0xc128, 0xebff, 0xc128, 0x21, 0 - .dw 0xec40, 0xc128, 0xec7f, 0xc128, 0x21, 0 - .dw 0xecc0, 0xc128, 0xecff, 0xc128, 0x21, 0 - .dw 0xed40, 0xc128, 0xed7f, 0xc128, 0x21, 0 - .dw 0xedc0, 0xc128, 0xedff, 0xc128, 0x21, 0 - .dw 0xee40, 0xc128, 0xee7f, 0xc128, 0x21, 0 - .dw 0xeec0, 0xc128, 0xeeff, 0xc128, 0x21, 0 - .dw 0xef40, 0xc128, 0xef7f, 0xc128, 0x21, 0 - .dw 0xefc0, 0xc128, 0xefff, 0xc128, 0x21, 0 - .dw 0xf040, 0xc128, 0xf07f, 0xc128, 0x21, 0 - .dw 0xf0c0, 0xc128, 0xf0ff, 0xc128, 0x21, 0 - .dw 0xf140, 0xc128, 0xf17f, 0xc128, 0x21, 0 - .dw 0xf1c0, 0xc128, 0xf1ff, 0xc128, 0x21, 0 - .dw 0xf240, 0xc128, 0xf27f, 0xc128, 0x21, 0 - .dw 0xf2c0, 0xc128, 0xf2ff, 0xc128, 0x21, 0 - .dw 0xf340, 0xc128, 0xf37f, 0xc128, 0x21, 0 - .dw 0xf3c0, 0xc128, 0xf3ff, 0xc128, 0x21, 0 - .dw 0xf440, 0xc128, 0xf47f, 0xc128, 0x21, 0 - .dw 0xf4c0, 0xc128, 0xf4ff, 0xc128, 0x21, 0 - .dw 0xf540, 0xc128, 0xf57f, 0xc128, 0x21, 0 - .dw 0xf5c0, 0xc128, 0xf5ff, 0xc128, 0x21, 0 - .dw 0xf640, 0xc128, 0xf67f, 0xc128, 0x21, 0 - .dw 0xf6c0, 0xc128, 0xf6ff, 0xc128, 0x21, 0 - .dw 0xf740, 0xc128, 0xf77f, 0xc128, 0x21, 0 - .dw 0xf7c0, 0xc128, 0xf7ff, 0xc128, 0x21, 0 - .dw 0xf840, 0xc128, 0xf87f, 0xc128, 0x21, 0 - .dw 0xf8c0, 0xc128, 0xf8ff, 0xc128, 0x21, 0 - .dw 0xf940, 0xc128, 0xf97f, 0xc128, 0x21, 0 - .dw 0xf9c0, 0xc128, 0x1fff, 0xc129, 0x21, 0 - .dw 0x2040, 0xc129, 0x207f, 0xc129, 0x21, 0 - .dw 0x20c0, 0xc129, 0x20ff, 0xc129, 0x21, 0 - .dw 0x2140, 0xc129, 0x217f, 0xc129, 0x21, 0 - .dw 0x21c0, 0xc129, 0x21ff, 0xc129, 0x21, 0 - .dw 0x2240, 0xc129, 0x227f, 0xc129, 0x21, 0 - .dw 0x22c0, 0xc129, 0x22ff, 0xc129, 0x21, 0 - .dw 0x2340, 0xc129, 0x237f, 0xc129, 0x21, 0 - .dw 0x23c0, 0xc129, 0x23ff, 0xc129, 0x21, 0 - .dw 0x2440, 0xc129, 0x247f, 0xc129, 0x21, 0 - .dw 0x24c0, 0xc129, 0x24ff, 0xc129, 0x21, 0 - .dw 0x2540, 0xc129, 0x257f, 0xc129, 0x21, 0 - .dw 0x25c0, 0xc129, 0x25ff, 0xc129, 0x21, 0 - .dw 0x2640, 0xc129, 0x267f, 0xc129, 0x21, 0 - .dw 0x26c0, 0xc129, 0x26ff, 0xc129, 0x21, 0 - .dw 0x2740, 0xc129, 0x277f, 0xc129, 0x21, 0 - .dw 0x27c0, 0xc129, 0x27ff, 0xc129, 0x21, 0 - .dw 0x2840, 0xc129, 0x287f, 0xc129, 0x21, 0 - .dw 0x28c0, 0xc129, 0x28ff, 0xc129, 0x21, 0 - .dw 0x2940, 0xc129, 0x297f, 0xc129, 0x21, 0 - .dw 0x29c0, 0xc129, 0x29ff, 0xc129, 0x21, 0 - .dw 0x2a40, 0xc129, 0x2a7f, 0xc129, 0x21, 0 - .dw 0x2ac0, 0xc129, 0x2aff, 0xc129, 0x21, 0 - .dw 0x2b40, 0xc129, 0x2b7f, 0xc129, 0x21, 0 - .dw 0x2bc0, 0xc129, 0x2bff, 0xc129, 0x21, 0 - .dw 0x2c40, 0xc129, 0x2c7f, 0xc129, 0x21, 0 - .dw 0x2cc0, 0xc129, 0x2cff, 0xc129, 0x21, 0 - .dw 0x2d40, 0xc129, 0x2d7f, 0xc129, 0x21, 0 - .dw 0x2dc0, 0xc129, 0x2dff, 0xc129, 0x21, 0 - .dw 0x2e40, 0xc129, 0x2e7f, 0xc129, 0x21, 0 - .dw 0x2ec0, 0xc129, 0x2eff, 0xc129, 0x21, 0 - .dw 0x2f40, 0xc129, 0x2f7f, 0xc129, 0x21, 0 - .dw 0x2fc0, 0xc129, 0x2fff, 0xc129, 0x21, 0 - .dw 0x3040, 0xc129, 0x307f, 0xc129, 0x21, 0 - .dw 0x30c0, 0xc129, 0x30ff, 0xc129, 0x21, 0 - .dw 0x3140, 0xc129, 0x317f, 0xc129, 0x21, 0 - .dw 0x31c0, 0xc129, 0x31ff, 0xc129, 0x21, 0 - .dw 0x3240, 0xc129, 0x327f, 0xc129, 0x21, 0 - .dw 0x32c0, 0xc129, 0x32ff, 0xc129, 0x21, 0 - .dw 0x3340, 0xc129, 0x337f, 0xc129, 0x21, 0 - .dw 0x33c0, 0xc129, 0x33ff, 0xc129, 0x21, 0 - .dw 0x3440, 0xc129, 0x347f, 0xc129, 0x21, 0 - .dw 0x34c0, 0xc129, 0x34ff, 0xc129, 0x21, 0 - .dw 0x3540, 0xc129, 0x357f, 0xc129, 0x21, 0 - .dw 0x35c0, 0xc129, 0x35ff, 0xc129, 0x21, 0 - .dw 0x3640, 0xc129, 0x367f, 0xc129, 0x21, 0 - .dw 0x36c0, 0xc129, 0x36ff, 0xc129, 0x21, 0 - .dw 0x3740, 0xc129, 0x377f, 0xc129, 0x21, 0 - .dw 0x37c0, 0xc129, 0x37ff, 0xc129, 0x21, 0 - .dw 0x3840, 0xc129, 0x387f, 0xc129, 0x21, 0 - .dw 0x38c0, 0xc129, 0x38ff, 0xc129, 0x21, 0 - .dw 0x3940, 0xc129, 0x397f, 0xc129, 0x21, 0 - .dw 0x39c0, 0xc129, 0x5fff, 0xc129, 0x21, 0 - .dw 0x6040, 0xc129, 0x607f, 0xc129, 0x21, 0 - .dw 0x60c0, 0xc129, 0x60ff, 0xc129, 0x21, 0 - .dw 0x6140, 0xc129, 0x617f, 0xc129, 0x21, 0 - .dw 0x61c0, 0xc129, 0x61ff, 0xc129, 0x21, 0 - .dw 0x6240, 0xc129, 0x627f, 0xc129, 0x21, 0 - .dw 0x62c0, 0xc129, 0x62ff, 0xc129, 0x21, 0 - .dw 0x6340, 0xc129, 0x637f, 0xc129, 0x21, 0 - .dw 0x63c0, 0xc129, 0x63ff, 0xc129, 0x21, 0 - .dw 0x6440, 0xc129, 0x647f, 0xc129, 0x21, 0 - .dw 0x64c0, 0xc129, 0x64ff, 0xc129, 0x21, 0 - .dw 0x6540, 0xc129, 0x657f, 0xc129, 0x21, 0 - .dw 0x65c0, 0xc129, 0x65ff, 0xc129, 0x21, 0 - .dw 0x6640, 0xc129, 0x667f, 0xc129, 0x21, 0 - .dw 0x66c0, 0xc129, 0x66ff, 0xc129, 0x21, 0 - .dw 0x6740, 0xc129, 0x677f, 0xc129, 0x21, 0 - .dw 0x67c0, 0xc129, 0x67ff, 0xc129, 0x21, 0 - .dw 0x6840, 0xc129, 0x687f, 0xc129, 0x21, 0 - .dw 0x68c0, 0xc129, 0x68ff, 0xc129, 0x21, 0 - .dw 0x6940, 0xc129, 0x697f, 0xc129, 0x21, 0 - .dw 0x69c0, 0xc129, 0x69ff, 0xc129, 0x21, 0 - .dw 0x6a40, 0xc129, 0x6a7f, 0xc129, 0x21, 0 - .dw 0x6ac0, 0xc129, 0x6aff, 0xc129, 0x21, 0 - .dw 0x6b40, 0xc129, 0x6b7f, 0xc129, 0x21, 0 - .dw 0x6bc0, 0xc129, 0x6bff, 0xc129, 0x21, 0 - .dw 0x6c40, 0xc129, 0x6c7f, 0xc129, 0x21, 0 - .dw 0x6cc0, 0xc129, 0x6cff, 0xc129, 0x21, 0 - .dw 0x6d40, 0xc129, 0x6d7f, 0xc129, 0x21, 0 - .dw 0x6dc0, 0xc129, 0x6dff, 0xc129, 0x21, 0 - .dw 0x6e40, 0xc129, 0x6e7f, 0xc129, 0x21, 0 - .dw 0x6ec0, 0xc129, 0x6eff, 0xc129, 0x21, 0 - .dw 0x6f40, 0xc129, 0x6f7f, 0xc129, 0x21, 0 - .dw 0x6fc0, 0xc129, 0x6fff, 0xc129, 0x21, 0 - .dw 0x7040, 0xc129, 0x707f, 0xc129, 0x21, 0 - .dw 0x70c0, 0xc129, 0x70ff, 0xc129, 0x21, 0 - .dw 0x7140, 0xc129, 0x717f, 0xc129, 0x21, 0 - .dw 0x71c0, 0xc129, 0x71ff, 0xc129, 0x21, 0 - .dw 0x7240, 0xc129, 0x727f, 0xc129, 0x21, 0 - .dw 0x72c0, 0xc129, 0x72ff, 0xc129, 0x21, 0 - .dw 0x7340, 0xc129, 0x737f, 0xc129, 0x21, 0 - .dw 0x73c0, 0xc129, 0x73ff, 0xc129, 0x21, 0 - .dw 0x7440, 0xc129, 0x747f, 0xc129, 0x21, 0 - .dw 0x74c0, 0xc129, 0x74ff, 0xc129, 0x21, 0 - .dw 0x7540, 0xc129, 0x757f, 0xc129, 0x21, 0 - .dw 0x75c0, 0xc129, 0x75ff, 0xc129, 0x21, 0 - .dw 0x7640, 0xc129, 0x767f, 0xc129, 0x21, 0 - .dw 0x76c0, 0xc129, 0x76ff, 0xc129, 0x21, 0 - .dw 0x7740, 0xc129, 0x777f, 0xc129, 0x21, 0 - .dw 0x77c0, 0xc129, 0x77ff, 0xc129, 0x21, 0 - .dw 0x7840, 0xc129, 0x787f, 0xc129, 0x21, 0 - .dw 0x78c0, 0xc129, 0x78ff, 0xc129, 0x21, 0 - .dw 0x7940, 0xc129, 0x797f, 0xc129, 0x21, 0 - .dw 0x79c0, 0xc129, 0x9fff, 0xc129, 0x21, 0 - .dw 0xa040, 0xc129, 0xa07f, 0xc129, 0x21, 0 - .dw 0xa0c0, 0xc129, 0xa0ff, 0xc129, 0x21, 0 - .dw 0xa140, 0xc129, 0xa17f, 0xc129, 0x21, 0 - .dw 0xa1c0, 0xc129, 0xa1ff, 0xc129, 0x21, 0 - .dw 0xa240, 0xc129, 0xa27f, 0xc129, 0x21, 0 - .dw 0xa2c0, 0xc129, 0xa2ff, 0xc129, 0x21, 0 - .dw 0xa340, 0xc129, 0xa37f, 0xc129, 0x21, 0 - .dw 0xa3c0, 0xc129, 0xa3ff, 0xc129, 0x21, 0 - .dw 0xa440, 0xc129, 0xa47f, 0xc129, 0x21, 0 - .dw 0xa4c0, 0xc129, 0xa4ff, 0xc129, 0x21, 0 - .dw 0xa540, 0xc129, 0xa57f, 0xc129, 0x21, 0 - .dw 0xa5c0, 0xc129, 0xa5ff, 0xc129, 0x21, 0 - .dw 0xa640, 0xc129, 0xa67f, 0xc129, 0x21, 0 - .dw 0xa6c0, 0xc129, 0xa6ff, 0xc129, 0x21, 0 - .dw 0xa740, 0xc129, 0xa77f, 0xc129, 0x21, 0 - .dw 0xa7c0, 0xc129, 0xa7ff, 0xc129, 0x21, 0 - .dw 0xa840, 0xc129, 0xa87f, 0xc129, 0x21, 0 - .dw 0xa8c0, 0xc129, 0xa8ff, 0xc129, 0x21, 0 - .dw 0xa940, 0xc129, 0xa97f, 0xc129, 0x21, 0 - .dw 0xa9c0, 0xc129, 0xa9ff, 0xc129, 0x21, 0 - .dw 0xaa40, 0xc129, 0xaa7f, 0xc129, 0x21, 0 - .dw 0xaac0, 0xc129, 0xaaff, 0xc129, 0x21, 0 - .dw 0xab40, 0xc129, 0xab7f, 0xc129, 0x21, 0 - .dw 0xabc0, 0xc129, 0xabff, 0xc129, 0x21, 0 - .dw 0xac40, 0xc129, 0xac7f, 0xc129, 0x21, 0 - .dw 0xacc0, 0xc129, 0xacff, 0xc129, 0x21, 0 - .dw 0xad40, 0xc129, 0xad7f, 0xc129, 0x21, 0 - .dw 0xadc0, 0xc129, 0xadff, 0xc129, 0x21, 0 - .dw 0xae40, 0xc129, 0xae7f, 0xc129, 0x21, 0 - .dw 0xaec0, 0xc129, 0xaeff, 0xc129, 0x21, 0 - .dw 0xaf40, 0xc129, 0xaf7f, 0xc129, 0x21, 0 - .dw 0xafc0, 0xc129, 0xafff, 0xc129, 0x21, 0 - .dw 0xb040, 0xc129, 0xb07f, 0xc129, 0x21, 0 - .dw 0xb0c0, 0xc129, 0xb0ff, 0xc129, 0x21, 0 - .dw 0xb140, 0xc129, 0xb17f, 0xc129, 0x21, 0 - .dw 0xb1c0, 0xc129, 0xb1ff, 0xc129, 0x21, 0 - .dw 0xb240, 0xc129, 0xb27f, 0xc129, 0x21, 0 - .dw 0xb2c0, 0xc129, 0xb2ff, 0xc129, 0x21, 0 - .dw 0xb340, 0xc129, 0xb37f, 0xc129, 0x21, 0 - .dw 0xb3c0, 0xc129, 0xb3ff, 0xc129, 0x21, 0 - .dw 0xb440, 0xc129, 0xb47f, 0xc129, 0x21, 0 - .dw 0xb4c0, 0xc129, 0xb4ff, 0xc129, 0x21, 0 - .dw 0xb540, 0xc129, 0xb57f, 0xc129, 0x21, 0 - .dw 0xb5c0, 0xc129, 0xb5ff, 0xc129, 0x21, 0 - .dw 0xb640, 0xc129, 0xb67f, 0xc129, 0x21, 0 - .dw 0xb6c0, 0xc129, 0xb6ff, 0xc129, 0x21, 0 - .dw 0xb740, 0xc129, 0xb77f, 0xc129, 0x21, 0 - .dw 0xb7c0, 0xc129, 0xb7ff, 0xc129, 0x21, 0 - .dw 0xb840, 0xc129, 0xb87f, 0xc129, 0x21, 0 - .dw 0xb8c0, 0xc129, 0xb8ff, 0xc129, 0x21, 0 - .dw 0xb940, 0xc129, 0xb97f, 0xc129, 0x21, 0 - .dw 0xb9c0, 0xc129, 0xdfff, 0xc129, 0x21, 0 - .dw 0xe040, 0xc129, 0xe07f, 0xc129, 0x21, 0 - .dw 0xe0c0, 0xc129, 0xe0ff, 0xc129, 0x21, 0 - .dw 0xe140, 0xc129, 0xe17f, 0xc129, 0x21, 0 - .dw 0xe1c0, 0xc129, 0xe1ff, 0xc129, 0x21, 0 - .dw 0xe240, 0xc129, 0xe27f, 0xc129, 0x21, 0 - .dw 0xe2c0, 0xc129, 0xe2ff, 0xc129, 0x21, 0 - .dw 0xe340, 0xc129, 0xe37f, 0xc129, 0x21, 0 - .dw 0xe3c0, 0xc129, 0xe3ff, 0xc129, 0x21, 0 - .dw 0xe440, 0xc129, 0xe47f, 0xc129, 0x21, 0 - .dw 0xe4c0, 0xc129, 0xe4ff, 0xc129, 0x21, 0 - .dw 0xe540, 0xc129, 0xe57f, 0xc129, 0x21, 0 - .dw 0xe5c0, 0xc129, 0xe5ff, 0xc129, 0x21, 0 - .dw 0xe640, 0xc129, 0xe67f, 0xc129, 0x21, 0 - .dw 0xe6c0, 0xc129, 0xe6ff, 0xc129, 0x21, 0 - .dw 0xe740, 0xc129, 0xe77f, 0xc129, 0x21, 0 - .dw 0xe7c0, 0xc129, 0xe7ff, 0xc129, 0x21, 0 - .dw 0xe840, 0xc129, 0xe87f, 0xc129, 0x21, 0 - .dw 0xe8c0, 0xc129, 0xe8ff, 0xc129, 0x21, 0 - .dw 0xe940, 0xc129, 0xe97f, 0xc129, 0x21, 0 - .dw 0xe9c0, 0xc129, 0xe9ff, 0xc129, 0x21, 0 - .dw 0xea40, 0xc129, 0xea7f, 0xc129, 0x21, 0 - .dw 0xeac0, 0xc129, 0xeaff, 0xc129, 0x21, 0 - .dw 0xeb40, 0xc129, 0xeb7f, 0xc129, 0x21, 0 - .dw 0xebc0, 0xc129, 0xebff, 0xc129, 0x21, 0 - .dw 0xec40, 0xc129, 0xec7f, 0xc129, 0x21, 0 - .dw 0xecc0, 0xc129, 0xecff, 0xc129, 0x21, 0 - .dw 0xed40, 0xc129, 0xed7f, 0xc129, 0x21, 0 - .dw 0xedc0, 0xc129, 0xedff, 0xc129, 0x21, 0 - .dw 0xee40, 0xc129, 0xee7f, 0xc129, 0x21, 0 - .dw 0xeec0, 0xc129, 0xeeff, 0xc129, 0x21, 0 - .dw 0xef40, 0xc129, 0xef7f, 0xc129, 0x21, 0 - .dw 0xefc0, 0xc129, 0xefff, 0xc129, 0x21, 0 - .dw 0xf040, 0xc129, 0xf07f, 0xc129, 0x21, 0 - .dw 0xf0c0, 0xc129, 0xf0ff, 0xc129, 0x21, 0 - .dw 0xf140, 0xc129, 0xf17f, 0xc129, 0x21, 0 - .dw 0xf1c0, 0xc129, 0xf1ff, 0xc129, 0x21, 0 - .dw 0xf240, 0xc129, 0xf27f, 0xc129, 0x21, 0 - .dw 0xf2c0, 0xc129, 0xf2ff, 0xc129, 0x21, 0 - .dw 0xf340, 0xc129, 0xf37f, 0xc129, 0x21, 0 - .dw 0xf3c0, 0xc129, 0xf3ff, 0xc129, 0x21, 0 - .dw 0xf440, 0xc129, 0xf47f, 0xc129, 0x21, 0 - .dw 0xf4c0, 0xc129, 0xf4ff, 0xc129, 0x21, 0 - .dw 0xf540, 0xc129, 0xf57f, 0xc129, 0x21, 0 - .dw 0xf5c0, 0xc129, 0xf5ff, 0xc129, 0x21, 0 - .dw 0xf640, 0xc129, 0xf67f, 0xc129, 0x21, 0 - .dw 0xf6c0, 0xc129, 0xf6ff, 0xc129, 0x21, 0 - .dw 0xf740, 0xc129, 0xf77f, 0xc129, 0x21, 0 - .dw 0xf7c0, 0xc129, 0xf7ff, 0xc129, 0x21, 0 - .dw 0xf840, 0xc129, 0xf87f, 0xc129, 0x21, 0 - .dw 0xf8c0, 0xc129, 0xf8ff, 0xc129, 0x21, 0 - .dw 0xf940, 0xc129, 0xf97f, 0xc129, 0x21, 0 - .dw 0xf9c0, 0xc129, 0x1fff, 0xc12a, 0x21, 0 - .dw 0x2040, 0xc12a, 0x207f, 0xc12a, 0x21, 0 - .dw 0x20c0, 0xc12a, 0x20ff, 0xc12a, 0x21, 0 - .dw 0x2140, 0xc12a, 0x217f, 0xc12a, 0x21, 0 - .dw 0x21c0, 0xc12a, 0x21ff, 0xc12a, 0x21, 0 - .dw 0x2240, 0xc12a, 0x227f, 0xc12a, 0x21, 0 - .dw 0x22c0, 0xc12a, 0x22ff, 0xc12a, 0x21, 0 - .dw 0x2340, 0xc12a, 0x237f, 0xc12a, 0x21, 0 - .dw 0x23c0, 0xc12a, 0x23ff, 0xc12a, 0x21, 0 - .dw 0x2440, 0xc12a, 0x247f, 0xc12a, 0x21, 0 - .dw 0x24c0, 0xc12a, 0x24ff, 0xc12a, 0x21, 0 - .dw 0x2540, 0xc12a, 0x257f, 0xc12a, 0x21, 0 - .dw 0x25c0, 0xc12a, 0x25ff, 0xc12a, 0x21, 0 - .dw 0x2640, 0xc12a, 0x267f, 0xc12a, 0x21, 0 - .dw 0x26c0, 0xc12a, 0x26ff, 0xc12a, 0x21, 0 - .dw 0x2740, 0xc12a, 0x277f, 0xc12a, 0x21, 0 - .dw 0x27c0, 0xc12a, 0x27ff, 0xc12a, 0x21, 0 - .dw 0x2840, 0xc12a, 0x287f, 0xc12a, 0x21, 0 - .dw 0x28c0, 0xc12a, 0x28ff, 0xc12a, 0x21, 0 - .dw 0x2940, 0xc12a, 0x297f, 0xc12a, 0x21, 0 - .dw 0x29c0, 0xc12a, 0x29ff, 0xc12a, 0x21, 0 - .dw 0x2a40, 0xc12a, 0x2a7f, 0xc12a, 0x21, 0 - .dw 0x2ac0, 0xc12a, 0x2aff, 0xc12a, 0x21, 0 - .dw 0x2b40, 0xc12a, 0x2b7f, 0xc12a, 0x21, 0 - .dw 0x2bc0, 0xc12a, 0x2bff, 0xc12a, 0x21, 0 - .dw 0x2c40, 0xc12a, 0x2c7f, 0xc12a, 0x21, 0 - .dw 0x2cc0, 0xc12a, 0x2cff, 0xc12a, 0x21, 0 - .dw 0x2d40, 0xc12a, 0x2d7f, 0xc12a, 0x21, 0 - .dw 0x2dc0, 0xc12a, 0x2dff, 0xc12a, 0x21, 0 - .dw 0x2e40, 0xc12a, 0x2e7f, 0xc12a, 0x21, 0 - .dw 0x2ec0, 0xc12a, 0x2eff, 0xc12a, 0x21, 0 - .dw 0x2f40, 0xc12a, 0x2f7f, 0xc12a, 0x21, 0 - .dw 0x2fc0, 0xc12a, 0x2fff, 0xc12a, 0x21, 0 - .dw 0x3040, 0xc12a, 0x307f, 0xc12a, 0x21, 0 - .dw 0x30c0, 0xc12a, 0x30ff, 0xc12a, 0x21, 0 - .dw 0x3140, 0xc12a, 0x317f, 0xc12a, 0x21, 0 - .dw 0x31c0, 0xc12a, 0x31ff, 0xc12a, 0x21, 0 - .dw 0x3240, 0xc12a, 0x327f, 0xc12a, 0x21, 0 - .dw 0x32c0, 0xc12a, 0x32ff, 0xc12a, 0x21, 0 - .dw 0x3340, 0xc12a, 0x337f, 0xc12a, 0x21, 0 - .dw 0x33c0, 0xc12a, 0x33ff, 0xc12a, 0x21, 0 - .dw 0x3440, 0xc12a, 0x347f, 0xc12a, 0x21, 0 - .dw 0x34c0, 0xc12a, 0x34ff, 0xc12a, 0x21, 0 - .dw 0x3540, 0xc12a, 0x357f, 0xc12a, 0x21, 0 - .dw 0x35c0, 0xc12a, 0x35ff, 0xc12a, 0x21, 0 - .dw 0x3640, 0xc12a, 0x367f, 0xc12a, 0x21, 0 - .dw 0x36c0, 0xc12a, 0x36ff, 0xc12a, 0x21, 0 - .dw 0x3740, 0xc12a, 0x377f, 0xc12a, 0x21, 0 - .dw 0x37c0, 0xc12a, 0x37ff, 0xc12a, 0x21, 0 - .dw 0x3840, 0xc12a, 0x387f, 0xc12a, 0x21, 0 - .dw 0x38c0, 0xc12a, 0x38ff, 0xc12a, 0x21, 0 - .dw 0x3940, 0xc12a, 0x397f, 0xc12a, 0x21, 0 - .dw 0x39c0, 0xc12a, 0x5fff, 0xc12a, 0x21, 0 - .dw 0x6040, 0xc12a, 0x607f, 0xc12a, 0x21, 0 - .dw 0x60c0, 0xc12a, 0x60ff, 0xc12a, 0x21, 0 - .dw 0x6140, 0xc12a, 0x617f, 0xc12a, 0x21, 0 - .dw 0x61c0, 0xc12a, 0x61ff, 0xc12a, 0x21, 0 - .dw 0x6240, 0xc12a, 0x627f, 0xc12a, 0x21, 0 - .dw 0x62c0, 0xc12a, 0x62ff, 0xc12a, 0x21, 0 - .dw 0x6340, 0xc12a, 0x637f, 0xc12a, 0x21, 0 - .dw 0x63c0, 0xc12a, 0x63ff, 0xc12a, 0x21, 0 - .dw 0x6440, 0xc12a, 0x647f, 0xc12a, 0x21, 0 - .dw 0x64c0, 0xc12a, 0x64ff, 0xc12a, 0x21, 0 - .dw 0x6540, 0xc12a, 0x657f, 0xc12a, 0x21, 0 - .dw 0x65c0, 0xc12a, 0x65ff, 0xc12a, 0x21, 0 - .dw 0x6640, 0xc12a, 0x667f, 0xc12a, 0x21, 0 - .dw 0x66c0, 0xc12a, 0x66ff, 0xc12a, 0x21, 0 - .dw 0x6740, 0xc12a, 0x677f, 0xc12a, 0x21, 0 - .dw 0x67c0, 0xc12a, 0x67ff, 0xc12a, 0x21, 0 - .dw 0x6840, 0xc12a, 0x687f, 0xc12a, 0x21, 0 - .dw 0x68c0, 0xc12a, 0x68ff, 0xc12a, 0x21, 0 - .dw 0x6940, 0xc12a, 0x697f, 0xc12a, 0x21, 0 - .dw 0x69c0, 0xc12a, 0x69ff, 0xc12a, 0x21, 0 - .dw 0x6a40, 0xc12a, 0x6a7f, 0xc12a, 0x21, 0 - .dw 0x6ac0, 0xc12a, 0x6aff, 0xc12a, 0x21, 0 - .dw 0x6b40, 0xc12a, 0x6b7f, 0xc12a, 0x21, 0 - .dw 0x6bc0, 0xc12a, 0x6bff, 0xc12a, 0x21, 0 - .dw 0x6c40, 0xc12a, 0x6c7f, 0xc12a, 0x21, 0 - .dw 0x6cc0, 0xc12a, 0x6cff, 0xc12a, 0x21, 0 - .dw 0x6d40, 0xc12a, 0x6d7f, 0xc12a, 0x21, 0 - .dw 0x6dc0, 0xc12a, 0x6dff, 0xc12a, 0x21, 0 - .dw 0x6e40, 0xc12a, 0x6e7f, 0xc12a, 0x21, 0 - .dw 0x6ec0, 0xc12a, 0x6eff, 0xc12a, 0x21, 0 - .dw 0x6f40, 0xc12a, 0x6f7f, 0xc12a, 0x21, 0 - .dw 0x6fc0, 0xc12a, 0x6fff, 0xc12a, 0x21, 0 - .dw 0x7040, 0xc12a, 0x707f, 0xc12a, 0x21, 0 - .dw 0x70c0, 0xc12a, 0x70ff, 0xc12a, 0x21, 0 - .dw 0x7140, 0xc12a, 0x717f, 0xc12a, 0x21, 0 - .dw 0x71c0, 0xc12a, 0x71ff, 0xc12a, 0x21, 0 - .dw 0x7240, 0xc12a, 0x727f, 0xc12a, 0x21, 0 - .dw 0x72c0, 0xc12a, 0x72ff, 0xc12a, 0x21, 0 - .dw 0x7340, 0xc12a, 0x737f, 0xc12a, 0x21, 0 - .dw 0x73c0, 0xc12a, 0x73ff, 0xc12a, 0x21, 0 - .dw 0x7440, 0xc12a, 0x747f, 0xc12a, 0x21, 0 - .dw 0x74c0, 0xc12a, 0x74ff, 0xc12a, 0x21, 0 - .dw 0x7540, 0xc12a, 0x757f, 0xc12a, 0x21, 0 - .dw 0x75c0, 0xc12a, 0x75ff, 0xc12a, 0x21, 0 - .dw 0x7640, 0xc12a, 0x767f, 0xc12a, 0x21, 0 - .dw 0x76c0, 0xc12a, 0x76ff, 0xc12a, 0x21, 0 - .dw 0x7740, 0xc12a, 0x777f, 0xc12a, 0x21, 0 - .dw 0x77c0, 0xc12a, 0x77ff, 0xc12a, 0x21, 0 - .dw 0x7840, 0xc12a, 0x787f, 0xc12a, 0x21, 0 - .dw 0x78c0, 0xc12a, 0x78ff, 0xc12a, 0x21, 0 - .dw 0x7940, 0xc12a, 0x797f, 0xc12a, 0x21, 0 - .dw 0x79c0, 0xc12a, 0x9fff, 0xc12a, 0x21, 0 - .dw 0xa040, 0xc12a, 0xa07f, 0xc12a, 0x21, 0 - .dw 0xa0c0, 0xc12a, 0xa0ff, 0xc12a, 0x21, 0 - .dw 0xa140, 0xc12a, 0xa17f, 0xc12a, 0x21, 0 - .dw 0xa1c0, 0xc12a, 0xa1ff, 0xc12a, 0x21, 0 - .dw 0xa240, 0xc12a, 0xa27f, 0xc12a, 0x21, 0 - .dw 0xa2c0, 0xc12a, 0xa2ff, 0xc12a, 0x21, 0 - .dw 0xa340, 0xc12a, 0xa37f, 0xc12a, 0x21, 0 - .dw 0xa3c0, 0xc12a, 0xa3ff, 0xc12a, 0x21, 0 - .dw 0xa440, 0xc12a, 0xa47f, 0xc12a, 0x21, 0 - .dw 0xa4c0, 0xc12a, 0xa4ff, 0xc12a, 0x21, 0 - .dw 0xa540, 0xc12a, 0xa57f, 0xc12a, 0x21, 0 - .dw 0xa5c0, 0xc12a, 0xa5ff, 0xc12a, 0x21, 0 - .dw 0xa640, 0xc12a, 0xa67f, 0xc12a, 0x21, 0 - .dw 0xa6c0, 0xc12a, 0xa6ff, 0xc12a, 0x21, 0 - .dw 0xa740, 0xc12a, 0xa77f, 0xc12a, 0x21, 0 - .dw 0xa7c0, 0xc12a, 0xa7ff, 0xc12a, 0x21, 0 - .dw 0xa840, 0xc12a, 0xa87f, 0xc12a, 0x21, 0 - .dw 0xa8c0, 0xc12a, 0xa8ff, 0xc12a, 0x21, 0 - .dw 0xa940, 0xc12a, 0xa97f, 0xc12a, 0x21, 0 - .dw 0xa9c0, 0xc12a, 0xa9ff, 0xc12a, 0x21, 0 - .dw 0xaa40, 0xc12a, 0xaa7f, 0xc12a, 0x21, 0 - .dw 0xaac0, 0xc12a, 0xaaff, 0xc12a, 0x21, 0 - .dw 0xab40, 0xc12a, 0xab7f, 0xc12a, 0x21, 0 - .dw 0xabc0, 0xc12a, 0xabff, 0xc12a, 0x21, 0 - .dw 0xac40, 0xc12a, 0xac7f, 0xc12a, 0x21, 0 - .dw 0xacc0, 0xc12a, 0xacff, 0xc12a, 0x21, 0 - .dw 0xad40, 0xc12a, 0xad7f, 0xc12a, 0x21, 0 - .dw 0xadc0, 0xc12a, 0xadff, 0xc12a, 0x21, 0 - .dw 0xae40, 0xc12a, 0xae7f, 0xc12a, 0x21, 0 - .dw 0xaec0, 0xc12a, 0xaeff, 0xc12a, 0x21, 0 - .dw 0xaf40, 0xc12a, 0xaf7f, 0xc12a, 0x21, 0 - .dw 0xafc0, 0xc12a, 0xafff, 0xc12a, 0x21, 0 - .dw 0xb040, 0xc12a, 0xb07f, 0xc12a, 0x21, 0 - .dw 0xb0c0, 0xc12a, 0xb0ff, 0xc12a, 0x21, 0 - .dw 0xb140, 0xc12a, 0xb17f, 0xc12a, 0x21, 0 - .dw 0xb1c0, 0xc12a, 0xb1ff, 0xc12a, 0x21, 0 - .dw 0xb240, 0xc12a, 0xb27f, 0xc12a, 0x21, 0 - .dw 0xb2c0, 0xc12a, 0xb2ff, 0xc12a, 0x21, 0 - .dw 0xb340, 0xc12a, 0xb37f, 0xc12a, 0x21, 0 - .dw 0xb3c0, 0xc12a, 0xb3ff, 0xc12a, 0x21, 0 - .dw 0xb440, 0xc12a, 0xb47f, 0xc12a, 0x21, 0 - .dw 0xb4c0, 0xc12a, 0xb4ff, 0xc12a, 0x21, 0 - .dw 0xb540, 0xc12a, 0xb57f, 0xc12a, 0x21, 0 - .dw 0xb5c0, 0xc12a, 0xb5ff, 0xc12a, 0x21, 0 - .dw 0xb640, 0xc12a, 0xb67f, 0xc12a, 0x21, 0 - .dw 0xb6c0, 0xc12a, 0xb6ff, 0xc12a, 0x21, 0 - .dw 0xb740, 0xc12a, 0xb77f, 0xc12a, 0x21, 0 - .dw 0xb7c0, 0xc12a, 0xb7ff, 0xc12a, 0x21, 0 - .dw 0xb840, 0xc12a, 0xb87f, 0xc12a, 0x21, 0 - .dw 0xb8c0, 0xc12a, 0xb8ff, 0xc12a, 0x21, 0 - .dw 0xb940, 0xc12a, 0xb97f, 0xc12a, 0x21, 0 - .dw 0xb9c0, 0xc12a, 0xdfff, 0xc12a, 0x21, 0 - .dw 0xe040, 0xc12a, 0xe07f, 0xc12a, 0x21, 0 - .dw 0xe0c0, 0xc12a, 0xe0ff, 0xc12a, 0x21, 0 - .dw 0xe140, 0xc12a, 0xe17f, 0xc12a, 0x21, 0 - .dw 0xe1c0, 0xc12a, 0xe1ff, 0xc12a, 0x21, 0 - .dw 0xe240, 0xc12a, 0xe27f, 0xc12a, 0x21, 0 - .dw 0xe2c0, 0xc12a, 0xe2ff, 0xc12a, 0x21, 0 - .dw 0xe340, 0xc12a, 0xe37f, 0xc12a, 0x21, 0 - .dw 0xe3c0, 0xc12a, 0xe3ff, 0xc12a, 0x21, 0 - .dw 0xe440, 0xc12a, 0xe47f, 0xc12a, 0x21, 0 - .dw 0xe4c0, 0xc12a, 0xe4ff, 0xc12a, 0x21, 0 - .dw 0xe540, 0xc12a, 0xe57f, 0xc12a, 0x21, 0 - .dw 0xe5c0, 0xc12a, 0xe5ff, 0xc12a, 0x21, 0 - .dw 0xe640, 0xc12a, 0xe67f, 0xc12a, 0x21, 0 - .dw 0xe6c0, 0xc12a, 0xe6ff, 0xc12a, 0x21, 0 - .dw 0xe740, 0xc12a, 0xe77f, 0xc12a, 0x21, 0 - .dw 0xe7c0, 0xc12a, 0xe7ff, 0xc12a, 0x21, 0 - .dw 0xe840, 0xc12a, 0xe87f, 0xc12a, 0x21, 0 - .dw 0xe8c0, 0xc12a, 0xe8ff, 0xc12a, 0x21, 0 - .dw 0xe940, 0xc12a, 0xe97f, 0xc12a, 0x21, 0 - .dw 0xe9c0, 0xc12a, 0xe9ff, 0xc12a, 0x21, 0 - .dw 0xea40, 0xc12a, 0xea7f, 0xc12a, 0x21, 0 - .dw 0xeac0, 0xc12a, 0xeaff, 0xc12a, 0x21, 0 - .dw 0xeb40, 0xc12a, 0xeb7f, 0xc12a, 0x21, 0 - .dw 0xebc0, 0xc12a, 0xebff, 0xc12a, 0x21, 0 - .dw 0xec40, 0xc12a, 0xec7f, 0xc12a, 0x21, 0 - .dw 0xecc0, 0xc12a, 0xecff, 0xc12a, 0x21, 0 - .dw 0xed40, 0xc12a, 0xed7f, 0xc12a, 0x21, 0 - .dw 0xedc0, 0xc12a, 0xedff, 0xc12a, 0x21, 0 - .dw 0xee40, 0xc12a, 0xee7f, 0xc12a, 0x21, 0 - .dw 0xeec0, 0xc12a, 0xeeff, 0xc12a, 0x21, 0 - .dw 0xef40, 0xc12a, 0xef7f, 0xc12a, 0x21, 0 - .dw 0xefc0, 0xc12a, 0xefff, 0xc12a, 0x21, 0 - .dw 0xf040, 0xc12a, 0xf07f, 0xc12a, 0x21, 0 - .dw 0xf0c0, 0xc12a, 0xf0ff, 0xc12a, 0x21, 0 - .dw 0xf140, 0xc12a, 0xf17f, 0xc12a, 0x21, 0 - .dw 0xf1c0, 0xc12a, 0xf1ff, 0xc12a, 0x21, 0 - .dw 0xf240, 0xc12a, 0xf27f, 0xc12a, 0x21, 0 - .dw 0xf2c0, 0xc12a, 0xf2ff, 0xc12a, 0x21, 0 - .dw 0xf340, 0xc12a, 0xf37f, 0xc12a, 0x21, 0 - .dw 0xf3c0, 0xc12a, 0xf3ff, 0xc12a, 0x21, 0 - .dw 0xf440, 0xc12a, 0xf47f, 0xc12a, 0x21, 0 - .dw 0xf4c0, 0xc12a, 0xf4ff, 0xc12a, 0x21, 0 - .dw 0xf540, 0xc12a, 0xf57f, 0xc12a, 0x21, 0 - .dw 0xf5c0, 0xc12a, 0xf5ff, 0xc12a, 0x21, 0 - .dw 0xf640, 0xc12a, 0xf67f, 0xc12a, 0x21, 0 - .dw 0xf6c0, 0xc12a, 0xf6ff, 0xc12a, 0x21, 0 - .dw 0xf740, 0xc12a, 0xf77f, 0xc12a, 0x21, 0 - .dw 0xf7c0, 0xc12a, 0xf7ff, 0xc12a, 0x21, 0 - .dw 0xf840, 0xc12a, 0xf87f, 0xc12a, 0x21, 0 - .dw 0xf8c0, 0xc12a, 0xf8ff, 0xc12a, 0x21, 0 - .dw 0xf940, 0xc12a, 0xf97f, 0xc12a, 0x21, 0 - .dw 0xf9c0, 0xc12a, 0x1fff, 0xc12b, 0x21, 0 - .dw 0x2040, 0xc12b, 0x207f, 0xc12b, 0x21, 0 - .dw 0x20c0, 0xc12b, 0x20ff, 0xc12b, 0x21, 0 - .dw 0x2140, 0xc12b, 0x217f, 0xc12b, 0x21, 0 - .dw 0x21c0, 0xc12b, 0x21ff, 0xc12b, 0x21, 0 - .dw 0x2240, 0xc12b, 0x227f, 0xc12b, 0x21, 0 - .dw 0x22c0, 0xc12b, 0x22ff, 0xc12b, 0x21, 0 - .dw 0x2340, 0xc12b, 0x237f, 0xc12b, 0x21, 0 - .dw 0x23c0, 0xc12b, 0x23ff, 0xc12b, 0x21, 0 - .dw 0x2440, 0xc12b, 0x247f, 0xc12b, 0x21, 0 - .dw 0x24c0, 0xc12b, 0x24ff, 0xc12b, 0x21, 0 - .dw 0x2540, 0xc12b, 0x257f, 0xc12b, 0x21, 0 - .dw 0x25c0, 0xc12b, 0x25ff, 0xc12b, 0x21, 0 - .dw 0x2640, 0xc12b, 0x267f, 0xc12b, 0x21, 0 - .dw 0x26c0, 0xc12b, 0x26ff, 0xc12b, 0x21, 0 - .dw 0x2740, 0xc12b, 0x277f, 0xc12b, 0x21, 0 - .dw 0x27c0, 0xc12b, 0x27ff, 0xc12b, 0x21, 0 - .dw 0x2840, 0xc12b, 0x287f, 0xc12b, 0x21, 0 - .dw 0x28c0, 0xc12b, 0x28ff, 0xc12b, 0x21, 0 - .dw 0x2940, 0xc12b, 0x297f, 0xc12b, 0x21, 0 - .dw 0x29c0, 0xc12b, 0x29ff, 0xc12b, 0x21, 0 - .dw 0x2a40, 0xc12b, 0x2a7f, 0xc12b, 0x21, 0 - .dw 0x2ac0, 0xc12b, 0x2aff, 0xc12b, 0x21, 0 - .dw 0x2b40, 0xc12b, 0x2b7f, 0xc12b, 0x21, 0 - .dw 0x2bc0, 0xc12b, 0x2bff, 0xc12b, 0x21, 0 - .dw 0x2c40, 0xc12b, 0x2c7f, 0xc12b, 0x21, 0 - .dw 0x2cc0, 0xc12b, 0x2cff, 0xc12b, 0x21, 0 - .dw 0x2d40, 0xc12b, 0x2d7f, 0xc12b, 0x21, 0 - .dw 0x2dc0, 0xc12b, 0x2dff, 0xc12b, 0x21, 0 - .dw 0x2e40, 0xc12b, 0x2e7f, 0xc12b, 0x21, 0 - .dw 0x2ec0, 0xc12b, 0x2eff, 0xc12b, 0x21, 0 - .dw 0x2f40, 0xc12b, 0x2f7f, 0xc12b, 0x21, 0 - .dw 0x2fc0, 0xc12b, 0x2fff, 0xc12b, 0x21, 0 - .dw 0x3040, 0xc12b, 0x307f, 0xc12b, 0x21, 0 - .dw 0x30c0, 0xc12b, 0x30ff, 0xc12b, 0x21, 0 - .dw 0x3140, 0xc12b, 0x317f, 0xc12b, 0x21, 0 - .dw 0x31c0, 0xc12b, 0x31ff, 0xc12b, 0x21, 0 - .dw 0x3240, 0xc12b, 0x327f, 0xc12b, 0x21, 0 - .dw 0x32c0, 0xc12b, 0x32ff, 0xc12b, 0x21, 0 - .dw 0x3340, 0xc12b, 0x337f, 0xc12b, 0x21, 0 - .dw 0x33c0, 0xc12b, 0x33ff, 0xc12b, 0x21, 0 - .dw 0x3440, 0xc12b, 0x347f, 0xc12b, 0x21, 0 - .dw 0x34c0, 0xc12b, 0x34ff, 0xc12b, 0x21, 0 - .dw 0x3540, 0xc12b, 0x357f, 0xc12b, 0x21, 0 - .dw 0x35c0, 0xc12b, 0x35ff, 0xc12b, 0x21, 0 - .dw 0x3640, 0xc12b, 0x367f, 0xc12b, 0x21, 0 - .dw 0x36c0, 0xc12b, 0x36ff, 0xc12b, 0x21, 0 - .dw 0x3740, 0xc12b, 0x377f, 0xc12b, 0x21, 0 - .dw 0x37c0, 0xc12b, 0x37ff, 0xc12b, 0x21, 0 - .dw 0x3840, 0xc12b, 0x387f, 0xc12b, 0x21, 0 - .dw 0x38c0, 0xc12b, 0x38ff, 0xc12b, 0x21, 0 - .dw 0x3940, 0xc12b, 0x397f, 0xc12b, 0x21, 0 - .dw 0x39c0, 0xc12b, 0xffff, 0xc12b, 0x21, 0 - .dw 0x0040, 0xc12c, 0x007f, 0xc12c, 0x21, 0 - .dw 0x00c0, 0xc12c, 0x00ff, 0xc12c, 0x21, 0 - .dw 0x0140, 0xc12c, 0x017f, 0xc12c, 0x21, 0 - .dw 0x01c0, 0xc12c, 0x01ff, 0xc12c, 0x21, 0 - .dw 0x0240, 0xc12c, 0x027f, 0xc12c, 0x21, 0 - .dw 0x02c0, 0xc12c, 0x02ff, 0xc12c, 0x21, 0 - .dw 0x0340, 0xc12c, 0x037f, 0xc12c, 0x21, 0 - .dw 0x03c0, 0xc12c, 0x03ff, 0xc12c, 0x21, 0 - .dw 0x0440, 0xc12c, 0x047f, 0xc12c, 0x21, 0 - .dw 0x04c0, 0xc12c, 0x04ff, 0xc12c, 0x21, 0 - .dw 0x0540, 0xc12c, 0x057f, 0xc12c, 0x21, 0 - .dw 0x05c0, 0xc12c, 0x05ff, 0xc12c, 0x21, 0 - .dw 0x0640, 0xc12c, 0x067f, 0xc12c, 0x21, 0 - .dw 0x06c0, 0xc12c, 0x06ff, 0xc12c, 0x21, 0 - .dw 0x0740, 0xc12c, 0x077f, 0xc12c, 0x21, 0 - .dw 0x07c0, 0xc12c, 0x07ff, 0xc12c, 0x21, 0 - .dw 0x0840, 0xc12c, 0x087f, 0xc12c, 0x21, 0 - .dw 0x08c0, 0xc12c, 0x08ff, 0xc12c, 0x21, 0 - .dw 0x0940, 0xc12c, 0x097f, 0xc12c, 0x21, 0 - .dw 0x09c0, 0xc12c, 0x09ff, 0xc12c, 0x21, 0 - .dw 0x0a40, 0xc12c, 0x0a7f, 0xc12c, 0x21, 0 - .dw 0x0ac0, 0xc12c, 0x0aff, 0xc12c, 0x21, 0 - .dw 0x0b40, 0xc12c, 0x0b7f, 0xc12c, 0x21, 0 - .dw 0x0bc0, 0xc12c, 0x0bff, 0xc12c, 0x21, 0 - .dw 0x0c40, 0xc12c, 0x0c7f, 0xc12c, 0x21, 0 - .dw 0x0cc0, 0xc12c, 0x0cff, 0xc12c, 0x21, 0 - .dw 0x0d40, 0xc12c, 0x0d7f, 0xc12c, 0x21, 0 - .dw 0x0dc0, 0xc12c, 0x0dff, 0xc12c, 0x21, 0 - .dw 0x0e40, 0xc12c, 0x0e7f, 0xc12c, 0x21, 0 - .dw 0x0ec0, 0xc12c, 0x0eff, 0xc12c, 0x21, 0 - .dw 0x0f40, 0xc12c, 0x0f7f, 0xc12c, 0x21, 0 - .dw 0x0fc0, 0xc12c, 0x0fff, 0xc12c, 0x21, 0 - .dw 0x1040, 0xc12c, 0x107f, 0xc12c, 0x21, 0 - .dw 0x10c0, 0xc12c, 0x10ff, 0xc12c, 0x21, 0 - .dw 0x1140, 0xc12c, 0x117f, 0xc12c, 0x21, 0 - .dw 0x11c0, 0xc12c, 0x11ff, 0xc12c, 0x21, 0 - .dw 0x1240, 0xc12c, 0x127f, 0xc12c, 0x21, 0 - .dw 0x12c0, 0xc12c, 0x12ff, 0xc12c, 0x21, 0 - .dw 0x1340, 0xc12c, 0x137f, 0xc12c, 0x21, 0 - .dw 0x13c0, 0xc12c, 0x13ff, 0xc12c, 0x21, 0 - .dw 0x1440, 0xc12c, 0x147f, 0xc12c, 0x21, 0 - .dw 0x14c0, 0xc12c, 0x14ff, 0xc12c, 0x21, 0 - .dw 0x1540, 0xc12c, 0x157f, 0xc12c, 0x21, 0 - .dw 0x15c0, 0xc12c, 0x15ff, 0xc12c, 0x21, 0 - .dw 0x1640, 0xc12c, 0x167f, 0xc12c, 0x21, 0 - .dw 0x16c0, 0xc12c, 0x16ff, 0xc12c, 0x21, 0 - .dw 0x1740, 0xc12c, 0x177f, 0xc12c, 0x21, 0 - .dw 0x17c0, 0xc12c, 0x17ff, 0xc12c, 0x21, 0 - .dw 0x1840, 0xc12c, 0x187f, 0xc12c, 0x21, 0 - .dw 0x18c0, 0xc12c, 0x18ff, 0xc12c, 0x21, 0 - .dw 0x1940, 0xc12c, 0x197f, 0xc12c, 0x21, 0 - .dw 0x19c0, 0xc12c, 0x1fff, 0xc12c, 0x21, 0 - .dw 0x2040, 0xc12c, 0x207f, 0xc12c, 0x21, 0 - .dw 0x20c0, 0xc12c, 0x20ff, 0xc12c, 0x21, 0 - .dw 0x2140, 0xc12c, 0x217f, 0xc12c, 0x21, 0 - .dw 0x21c0, 0xc12c, 0x21ff, 0xc12c, 0x21, 0 - .dw 0x2240, 0xc12c, 0x227f, 0xc12c, 0x21, 0 - .dw 0x22c0, 0xc12c, 0x22ff, 0xc12c, 0x21, 0 - .dw 0x2340, 0xc12c, 0x237f, 0xc12c, 0x21, 0 - .dw 0x23c0, 0xc12c, 0x23ff, 0xc12c, 0x21, 0 - .dw 0x2440, 0xc12c, 0x247f, 0xc12c, 0x21, 0 - .dw 0x24c0, 0xc12c, 0x24ff, 0xc12c, 0x21, 0 - .dw 0x2540, 0xc12c, 0x257f, 0xc12c, 0x21, 0 - .dw 0x25c0, 0xc12c, 0x25ff, 0xc12c, 0x21, 0 - .dw 0x2640, 0xc12c, 0x267f, 0xc12c, 0x21, 0 - .dw 0x26c0, 0xc12c, 0x26ff, 0xc12c, 0x21, 0 - .dw 0x2740, 0xc12c, 0x277f, 0xc12c, 0x21, 0 - .dw 0x27c0, 0xc12c, 0x27ff, 0xc12c, 0x21, 0 - .dw 0x2840, 0xc12c, 0x287f, 0xc12c, 0x21, 0 - .dw 0x28c0, 0xc12c, 0x28ff, 0xc12c, 0x21, 0 - .dw 0x2940, 0xc12c, 0x297f, 0xc12c, 0x21, 0 - .dw 0x29c0, 0xc12c, 0x29ff, 0xc12c, 0x21, 0 - .dw 0x2a40, 0xc12c, 0x2a7f, 0xc12c, 0x21, 0 - .dw 0x2ac0, 0xc12c, 0x2aff, 0xc12c, 0x21, 0 - .dw 0x2b40, 0xc12c, 0x2b7f, 0xc12c, 0x21, 0 - .dw 0x2bc0, 0xc12c, 0x2bff, 0xc12c, 0x21, 0 - .dw 0x2c40, 0xc12c, 0x2c7f, 0xc12c, 0x21, 0 - .dw 0x2cc0, 0xc12c, 0x2cff, 0xc12c, 0x21, 0 - .dw 0x2d40, 0xc12c, 0x2d7f, 0xc12c, 0x21, 0 - .dw 0x2dc0, 0xc12c, 0x2dff, 0xc12c, 0x21, 0 - .dw 0x2e40, 0xc12c, 0x2e7f, 0xc12c, 0x21, 0 - .dw 0x2ec0, 0xc12c, 0x2eff, 0xc12c, 0x21, 0 - .dw 0x2f40, 0xc12c, 0x2f7f, 0xc12c, 0x21, 0 - .dw 0x2fc0, 0xc12c, 0x2fff, 0xc12c, 0x21, 0 - .dw 0x3040, 0xc12c, 0x307f, 0xc12c, 0x21, 0 - .dw 0x30c0, 0xc12c, 0x30ff, 0xc12c, 0x21, 0 - .dw 0x3140, 0xc12c, 0x317f, 0xc12c, 0x21, 0 - .dw 0x31c0, 0xc12c, 0x31ff, 0xc12c, 0x21, 0 - .dw 0x3240, 0xc12c, 0x327f, 0xc12c, 0x21, 0 - .dw 0x32c0, 0xc12c, 0x32ff, 0xc12c, 0x21, 0 - .dw 0x3340, 0xc12c, 0x337f, 0xc12c, 0x21, 0 - .dw 0x33c0, 0xc12c, 0x33ff, 0xc12c, 0x21, 0 - .dw 0x3440, 0xc12c, 0x347f, 0xc12c, 0x21, 0 - .dw 0x34c0, 0xc12c, 0x34ff, 0xc12c, 0x21, 0 - .dw 0x3540, 0xc12c, 0x357f, 0xc12c, 0x21, 0 - .dw 0x35c0, 0xc12c, 0x35ff, 0xc12c, 0x21, 0 - .dw 0x3640, 0xc12c, 0x367f, 0xc12c, 0x21, 0 - .dw 0x36c0, 0xc12c, 0x36ff, 0xc12c, 0x21, 0 - .dw 0x3740, 0xc12c, 0x377f, 0xc12c, 0x21, 0 - .dw 0x37c0, 0xc12c, 0x37ff, 0xc12c, 0x21, 0 - .dw 0x3840, 0xc12c, 0x387f, 0xc12c, 0x21, 0 - .dw 0x38c0, 0xc12c, 0x38ff, 0xc12c, 0x21, 0 - .dw 0x3940, 0xc12c, 0x397f, 0xc12c, 0x21, 0 - .dw 0x39c0, 0xc12c, 0x3fff, 0xc12c, 0x21, 0 - .dw 0x4040, 0xc12c, 0x407f, 0xc12c, 0x21, 0 - .dw 0x40c0, 0xc12c, 0x40ff, 0xc12c, 0x21, 0 - .dw 0x4140, 0xc12c, 0x417f, 0xc12c, 0x21, 0 - .dw 0x41c0, 0xc12c, 0x41ff, 0xc12c, 0x21, 0 - .dw 0x4240, 0xc12c, 0x427f, 0xc12c, 0x21, 0 - .dw 0x42c0, 0xc12c, 0x42ff, 0xc12c, 0x21, 0 - .dw 0x4340, 0xc12c, 0x437f, 0xc12c, 0x21, 0 - .dw 0x43c0, 0xc12c, 0x43ff, 0xc12c, 0x21, 0 - .dw 0x4440, 0xc12c, 0x447f, 0xc12c, 0x21, 0 - .dw 0x44c0, 0xc12c, 0x44ff, 0xc12c, 0x21, 0 - .dw 0x4540, 0xc12c, 0x457f, 0xc12c, 0x21, 0 - .dw 0x45c0, 0xc12c, 0x45ff, 0xc12c, 0x21, 0 - .dw 0x4640, 0xc12c, 0x467f, 0xc12c, 0x21, 0 - .dw 0x46c0, 0xc12c, 0x46ff, 0xc12c, 0x21, 0 - .dw 0x4740, 0xc12c, 0x477f, 0xc12c, 0x21, 0 - .dw 0x47c0, 0xc12c, 0x47ff, 0xc12c, 0x21, 0 - .dw 0x4840, 0xc12c, 0x487f, 0xc12c, 0x21, 0 - .dw 0x48c0, 0xc12c, 0x48ff, 0xc12c, 0x21, 0 - .dw 0x4940, 0xc12c, 0x497f, 0xc12c, 0x21, 0 - .dw 0x49c0, 0xc12c, 0x49ff, 0xc12c, 0x21, 0 - .dw 0x4a40, 0xc12c, 0x4a7f, 0xc12c, 0x21, 0 - .dw 0x4ac0, 0xc12c, 0x4aff, 0xc12c, 0x21, 0 - .dw 0x4b40, 0xc12c, 0x4b7f, 0xc12c, 0x21, 0 - .dw 0x4bc0, 0xc12c, 0x4bff, 0xc12c, 0x21, 0 - .dw 0x4c40, 0xc12c, 0x4c7f, 0xc12c, 0x21, 0 - .dw 0x4cc0, 0xc12c, 0x4cff, 0xc12c, 0x21, 0 - .dw 0x4d40, 0xc12c, 0x4d7f, 0xc12c, 0x21, 0 - .dw 0x4dc0, 0xc12c, 0x4dff, 0xc12c, 0x21, 0 - .dw 0x4e40, 0xc12c, 0x4e7f, 0xc12c, 0x21, 0 - .dw 0x4ec0, 0xc12c, 0x4eff, 0xc12c, 0x21, 0 - .dw 0x4f40, 0xc12c, 0x4f7f, 0xc12c, 0x21, 0 - .dw 0x4fc0, 0xc12c, 0x4fff, 0xc12c, 0x21, 0 - .dw 0x5040, 0xc12c, 0x507f, 0xc12c, 0x21, 0 - .dw 0x50c0, 0xc12c, 0x50ff, 0xc12c, 0x21, 0 - .dw 0x5140, 0xc12c, 0x517f, 0xc12c, 0x21, 0 - .dw 0x51c0, 0xc12c, 0x51ff, 0xc12c, 0x21, 0 - .dw 0x5240, 0xc12c, 0x527f, 0xc12c, 0x21, 0 - .dw 0x52c0, 0xc12c, 0x52ff, 0xc12c, 0x21, 0 - .dw 0x5340, 0xc12c, 0x537f, 0xc12c, 0x21, 0 - .dw 0x53c0, 0xc12c, 0x53ff, 0xc12c, 0x21, 0 - .dw 0x5440, 0xc12c, 0x547f, 0xc12c, 0x21, 0 - .dw 0x54c0, 0xc12c, 0x54ff, 0xc12c, 0x21, 0 - .dw 0x5540, 0xc12c, 0x557f, 0xc12c, 0x21, 0 - .dw 0x55c0, 0xc12c, 0x55ff, 0xc12c, 0x21, 0 - .dw 0x5640, 0xc12c, 0x567f, 0xc12c, 0x21, 0 - .dw 0x56c0, 0xc12c, 0x56ff, 0xc12c, 0x21, 0 - .dw 0x5740, 0xc12c, 0x577f, 0xc12c, 0x21, 0 - .dw 0x57c0, 0xc12c, 0x57ff, 0xc12c, 0x21, 0 - .dw 0x5840, 0xc12c, 0x587f, 0xc12c, 0x21, 0 - .dw 0x58c0, 0xc12c, 0x58ff, 0xc12c, 0x21, 0 - .dw 0x5940, 0xc12c, 0x597f, 0xc12c, 0x21, 0 - .dw 0x59c0, 0xc12c, 0x5fff, 0xc12c, 0x21, 0 - .dw 0x6040, 0xc12c, 0x607f, 0xc12c, 0x21, 0 - .dw 0x60c0, 0xc12c, 0x60ff, 0xc12c, 0x21, 0 - .dw 0x6140, 0xc12c, 0x617f, 0xc12c, 0x21, 0 - .dw 0x61c0, 0xc12c, 0x61ff, 0xc12c, 0x21, 0 - .dw 0x6240, 0xc12c, 0x627f, 0xc12c, 0x21, 0 - .dw 0x62c0, 0xc12c, 0x62ff, 0xc12c, 0x21, 0 - .dw 0x6340, 0xc12c, 0x637f, 0xc12c, 0x21, 0 - .dw 0x63c0, 0xc12c, 0x63ff, 0xc12c, 0x21, 0 - .dw 0x6440, 0xc12c, 0x647f, 0xc12c, 0x21, 0 - .dw 0x64c0, 0xc12c, 0x64ff, 0xc12c, 0x21, 0 - .dw 0x6540, 0xc12c, 0x657f, 0xc12c, 0x21, 0 - .dw 0x65c0, 0xc12c, 0x65ff, 0xc12c, 0x21, 0 - .dw 0x6640, 0xc12c, 0x667f, 0xc12c, 0x21, 0 - .dw 0x66c0, 0xc12c, 0x66ff, 0xc12c, 0x21, 0 - .dw 0x6740, 0xc12c, 0x677f, 0xc12c, 0x21, 0 - .dw 0x67c0, 0xc12c, 0x67ff, 0xc12c, 0x21, 0 - .dw 0x6840, 0xc12c, 0x687f, 0xc12c, 0x21, 0 - .dw 0x68c0, 0xc12c, 0x68ff, 0xc12c, 0x21, 0 - .dw 0x6940, 0xc12c, 0x697f, 0xc12c, 0x21, 0 - .dw 0x69c0, 0xc12c, 0x69ff, 0xc12c, 0x21, 0 - .dw 0x6a40, 0xc12c, 0x6a7f, 0xc12c, 0x21, 0 - .dw 0x6ac0, 0xc12c, 0x6aff, 0xc12c, 0x21, 0 - .dw 0x6b40, 0xc12c, 0x6b7f, 0xc12c, 0x21, 0 - .dw 0x6bc0, 0xc12c, 0x6bff, 0xc12c, 0x21, 0 - .dw 0x6c40, 0xc12c, 0x6c7f, 0xc12c, 0x21, 0 - .dw 0x6cc0, 0xc12c, 0x6cff, 0xc12c, 0x21, 0 - .dw 0x6d40, 0xc12c, 0x6d7f, 0xc12c, 0x21, 0 - .dw 0x6dc0, 0xc12c, 0x6dff, 0xc12c, 0x21, 0 - .dw 0x6e40, 0xc12c, 0x6e7f, 0xc12c, 0x21, 0 - .dw 0x6ec0, 0xc12c, 0x6eff, 0xc12c, 0x21, 0 - .dw 0x6f40, 0xc12c, 0x6f7f, 0xc12c, 0x21, 0 - .dw 0x6fc0, 0xc12c, 0x6fff, 0xc12c, 0x21, 0 - .dw 0x7040, 0xc12c, 0x707f, 0xc12c, 0x21, 0 - .dw 0x70c0, 0xc12c, 0x70ff, 0xc12c, 0x21, 0 - .dw 0x7140, 0xc12c, 0x717f, 0xc12c, 0x21, 0 - .dw 0x71c0, 0xc12c, 0x71ff, 0xc12c, 0x21, 0 - .dw 0x7240, 0xc12c, 0x727f, 0xc12c, 0x21, 0 - .dw 0x72c0, 0xc12c, 0x72ff, 0xc12c, 0x21, 0 - .dw 0x7340, 0xc12c, 0x737f, 0xc12c, 0x21, 0 - .dw 0x73c0, 0xc12c, 0x73ff, 0xc12c, 0x21, 0 - .dw 0x7440, 0xc12c, 0x747f, 0xc12c, 0x21, 0 - .dw 0x74c0, 0xc12c, 0x74ff, 0xc12c, 0x21, 0 - .dw 0x7540, 0xc12c, 0x757f, 0xc12c, 0x21, 0 - .dw 0x75c0, 0xc12c, 0x75ff, 0xc12c, 0x21, 0 - .dw 0x7640, 0xc12c, 0x767f, 0xc12c, 0x21, 0 - .dw 0x76c0, 0xc12c, 0x76ff, 0xc12c, 0x21, 0 - .dw 0x7740, 0xc12c, 0x777f, 0xc12c, 0x21, 0 - .dw 0x77c0, 0xc12c, 0x77ff, 0xc12c, 0x21, 0 - .dw 0x7840, 0xc12c, 0x787f, 0xc12c, 0x21, 0 - .dw 0x78c0, 0xc12c, 0x78ff, 0xc12c, 0x21, 0 - .dw 0x7940, 0xc12c, 0x797f, 0xc12c, 0x21, 0 - .dw 0x79c0, 0xc12c, 0x7fff, 0xc12c, 0x21, 0 - .dw 0x8040, 0xc12c, 0x807f, 0xc12c, 0x21, 0 - .dw 0x80c0, 0xc12c, 0x80ff, 0xc12c, 0x21, 0 - .dw 0x8140, 0xc12c, 0x817f, 0xc12c, 0x21, 0 - .dw 0x81c0, 0xc12c, 0x81ff, 0xc12c, 0x21, 0 - .dw 0x8240, 0xc12c, 0x827f, 0xc12c, 0x21, 0 - .dw 0x82c0, 0xc12c, 0x82ff, 0xc12c, 0x21, 0 - .dw 0x8340, 0xc12c, 0x837f, 0xc12c, 0x21, 0 - .dw 0x83c0, 0xc12c, 0x83ff, 0xc12c, 0x21, 0 - .dw 0x8440, 0xc12c, 0x847f, 0xc12c, 0x21, 0 - .dw 0x84c0, 0xc12c, 0x84ff, 0xc12c, 0x21, 0 - .dw 0x8540, 0xc12c, 0x857f, 0xc12c, 0x21, 0 - .dw 0x85c0, 0xc12c, 0x85ff, 0xc12c, 0x21, 0 - .dw 0x8640, 0xc12c, 0x867f, 0xc12c, 0x21, 0 - .dw 0x86c0, 0xc12c, 0x86ff, 0xc12c, 0x21, 0 - .dw 0x8740, 0xc12c, 0x877f, 0xc12c, 0x21, 0 - .dw 0x87c0, 0xc12c, 0x87ff, 0xc12c, 0x21, 0 - .dw 0x8840, 0xc12c, 0x887f, 0xc12c, 0x21, 0 - .dw 0x88c0, 0xc12c, 0x88ff, 0xc12c, 0x21, 0 - .dw 0x8940, 0xc12c, 0x897f, 0xc12c, 0x21, 0 - .dw 0x89c0, 0xc12c, 0x89ff, 0xc12c, 0x21, 0 - .dw 0x8a40, 0xc12c, 0x8a7f, 0xc12c, 0x21, 0 - .dw 0x8ac0, 0xc12c, 0x8aff, 0xc12c, 0x21, 0 - .dw 0x8b40, 0xc12c, 0x8b7f, 0xc12c, 0x21, 0 - .dw 0x8bc0, 0xc12c, 0x8bff, 0xc12c, 0x21, 0 - .dw 0x8c40, 0xc12c, 0x8c7f, 0xc12c, 0x21, 0 - .dw 0x8cc0, 0xc12c, 0x8cff, 0xc12c, 0x21, 0 - .dw 0x8d40, 0xc12c, 0x8d7f, 0xc12c, 0x21, 0 - .dw 0x8dc0, 0xc12c, 0x8dff, 0xc12c, 0x21, 0 - .dw 0x8e40, 0xc12c, 0x8e7f, 0xc12c, 0x21, 0 - .dw 0x8ec0, 0xc12c, 0x8eff, 0xc12c, 0x21, 0 - .dw 0x8f40, 0xc12c, 0x8f7f, 0xc12c, 0x21, 0 - .dw 0x8fc0, 0xc12c, 0x8fff, 0xc12c, 0x21, 0 - .dw 0x9040, 0xc12c, 0x907f, 0xc12c, 0x21, 0 - .dw 0x90c0, 0xc12c, 0x90ff, 0xc12c, 0x21, 0 - .dw 0x9140, 0xc12c, 0x917f, 0xc12c, 0x21, 0 - .dw 0x91c0, 0xc12c, 0x91ff, 0xc12c, 0x21, 0 - .dw 0x9240, 0xc12c, 0x927f, 0xc12c, 0x21, 0 - .dw 0x92c0, 0xc12c, 0x92ff, 0xc12c, 0x21, 0 - .dw 0x9340, 0xc12c, 0x937f, 0xc12c, 0x21, 0 - .dw 0x93c0, 0xc12c, 0x93ff, 0xc12c, 0x21, 0 - .dw 0x9440, 0xc12c, 0x947f, 0xc12c, 0x21, 0 - .dw 0x94c0, 0xc12c, 0x94ff, 0xc12c, 0x21, 0 - .dw 0x9540, 0xc12c, 0x957f, 0xc12c, 0x21, 0 - .dw 0x95c0, 0xc12c, 0x95ff, 0xc12c, 0x21, 0 - .dw 0x9640, 0xc12c, 0x967f, 0xc12c, 0x21, 0 - .dw 0x96c0, 0xc12c, 0x96ff, 0xc12c, 0x21, 0 - .dw 0x9740, 0xc12c, 0x977f, 0xc12c, 0x21, 0 - .dw 0x97c0, 0xc12c, 0x97ff, 0xc12c, 0x21, 0 - .dw 0x9840, 0xc12c, 0x987f, 0xc12c, 0x21, 0 - .dw 0x98c0, 0xc12c, 0x98ff, 0xc12c, 0x21, 0 - .dw 0x9940, 0xc12c, 0x997f, 0xc12c, 0x21, 0 - .dw 0x99c0, 0xc12c, 0x9fff, 0xc12c, 0x21, 0 - .dw 0xa040, 0xc12c, 0xa07f, 0xc12c, 0x21, 0 - .dw 0xa0c0, 0xc12c, 0xa0ff, 0xc12c, 0x21, 0 - .dw 0xa140, 0xc12c, 0xa17f, 0xc12c, 0x21, 0 - .dw 0xa1c0, 0xc12c, 0xa1ff, 0xc12c, 0x21, 0 - .dw 0xa240, 0xc12c, 0xa27f, 0xc12c, 0x21, 0 - .dw 0xa2c0, 0xc12c, 0xa2ff, 0xc12c, 0x21, 0 - .dw 0xa340, 0xc12c, 0xa37f, 0xc12c, 0x21, 0 - .dw 0xa3c0, 0xc12c, 0xa3ff, 0xc12c, 0x21, 0 - .dw 0xa440, 0xc12c, 0xa47f, 0xc12c, 0x21, 0 - .dw 0xa4c0, 0xc12c, 0xa4ff, 0xc12c, 0x21, 0 - .dw 0xa540, 0xc12c, 0xa57f, 0xc12c, 0x21, 0 - .dw 0xa5c0, 0xc12c, 0xa5ff, 0xc12c, 0x21, 0 - .dw 0xa640, 0xc12c, 0xa67f, 0xc12c, 0x21, 0 - .dw 0xa6c0, 0xc12c, 0xa6ff, 0xc12c, 0x21, 0 - .dw 0xa740, 0xc12c, 0xa77f, 0xc12c, 0x21, 0 - .dw 0xa7c0, 0xc12c, 0xa7ff, 0xc12c, 0x21, 0 - .dw 0xa840, 0xc12c, 0xa87f, 0xc12c, 0x21, 0 - .dw 0xa8c0, 0xc12c, 0xa8ff, 0xc12c, 0x21, 0 - .dw 0xa940, 0xc12c, 0xa97f, 0xc12c, 0x21, 0 - .dw 0xa9c0, 0xc12c, 0xa9ff, 0xc12c, 0x21, 0 - .dw 0xaa40, 0xc12c, 0xaa7f, 0xc12c, 0x21, 0 - .dw 0xaac0, 0xc12c, 0xaaff, 0xc12c, 0x21, 0 - .dw 0xab40, 0xc12c, 0xab7f, 0xc12c, 0x21, 0 - .dw 0xabc0, 0xc12c, 0xabff, 0xc12c, 0x21, 0 - .dw 0xac40, 0xc12c, 0xac7f, 0xc12c, 0x21, 0 - .dw 0xacc0, 0xc12c, 0xacff, 0xc12c, 0x21, 0 - .dw 0xad40, 0xc12c, 0xad7f, 0xc12c, 0x21, 0 - .dw 0xadc0, 0xc12c, 0xadff, 0xc12c, 0x21, 0 - .dw 0xae40, 0xc12c, 0xae7f, 0xc12c, 0x21, 0 - .dw 0xaec0, 0xc12c, 0xaeff, 0xc12c, 0x21, 0 - .dw 0xaf40, 0xc12c, 0xaf7f, 0xc12c, 0x21, 0 - .dw 0xafc0, 0xc12c, 0xafff, 0xc12c, 0x21, 0 - .dw 0xb040, 0xc12c, 0xb07f, 0xc12c, 0x21, 0 - .dw 0xb0c0, 0xc12c, 0xb0ff, 0xc12c, 0x21, 0 - .dw 0xb140, 0xc12c, 0xb17f, 0xc12c, 0x21, 0 - .dw 0xb1c0, 0xc12c, 0xb1ff, 0xc12c, 0x21, 0 - .dw 0xb240, 0xc12c, 0xb27f, 0xc12c, 0x21, 0 - .dw 0xb2c0, 0xc12c, 0xb2ff, 0xc12c, 0x21, 0 - .dw 0xb340, 0xc12c, 0xb37f, 0xc12c, 0x21, 0 - .dw 0xb3c0, 0xc12c, 0xb3ff, 0xc12c, 0x21, 0 - .dw 0xb440, 0xc12c, 0xb47f, 0xc12c, 0x21, 0 - .dw 0xb4c0, 0xc12c, 0xb4ff, 0xc12c, 0x21, 0 - .dw 0xb540, 0xc12c, 0xb57f, 0xc12c, 0x21, 0 - .dw 0xb5c0, 0xc12c, 0xb5ff, 0xc12c, 0x21, 0 - .dw 0xb640, 0xc12c, 0xb67f, 0xc12c, 0x21, 0 - .dw 0xb6c0, 0xc12c, 0xb6ff, 0xc12c, 0x21, 0 - .dw 0xb740, 0xc12c, 0xb77f, 0xc12c, 0x21, 0 - .dw 0xb7c0, 0xc12c, 0xb7ff, 0xc12c, 0x21, 0 - .dw 0xb840, 0xc12c, 0xb87f, 0xc12c, 0x21, 0 - .dw 0xb8c0, 0xc12c, 0xb8ff, 0xc12c, 0x21, 0 - .dw 0xb940, 0xc12c, 0xb97f, 0xc12c, 0x21, 0 - .dw 0xb9c0, 0xc12c, 0xbfff, 0xc12c, 0x21, 0 - .dw 0xc040, 0xc12c, 0xc07f, 0xc12c, 0x21, 0 - .dw 0xc0c0, 0xc12c, 0xc0ff, 0xc12c, 0x21, 0 - .dw 0xc140, 0xc12c, 0xc17f, 0xc12c, 0x21, 0 - .dw 0xc1c0, 0xc12c, 0xc1ff, 0xc12c, 0x21, 0 - .dw 0xc240, 0xc12c, 0xc27f, 0xc12c, 0x21, 0 - .dw 0xc2c0, 0xc12c, 0xc2ff, 0xc12c, 0x21, 0 - .dw 0xc340, 0xc12c, 0xc37f, 0xc12c, 0x21, 0 - .dw 0xc3c0, 0xc12c, 0xc3ff, 0xc12c, 0x21, 0 - .dw 0xc440, 0xc12c, 0xc47f, 0xc12c, 0x21, 0 - .dw 0xc4c0, 0xc12c, 0xc4ff, 0xc12c, 0x21, 0 - .dw 0xc540, 0xc12c, 0xc57f, 0xc12c, 0x21, 0 - .dw 0xc5c0, 0xc12c, 0xc5ff, 0xc12c, 0x21, 0 - .dw 0xc640, 0xc12c, 0xc67f, 0xc12c, 0x21, 0 - .dw 0xc6c0, 0xc12c, 0xc6ff, 0xc12c, 0x21, 0 - .dw 0xc740, 0xc12c, 0xc77f, 0xc12c, 0x21, 0 - .dw 0xc7c0, 0xc12c, 0xc7ff, 0xc12c, 0x21, 0 - .dw 0xc840, 0xc12c, 0xc87f, 0xc12c, 0x21, 0 - .dw 0xc8c0, 0xc12c, 0xc8ff, 0xc12c, 0x21, 0 - .dw 0xc940, 0xc12c, 0xc97f, 0xc12c, 0x21, 0 - .dw 0xc9c0, 0xc12c, 0xc9ff, 0xc12c, 0x21, 0 - .dw 0xca40, 0xc12c, 0xca7f, 0xc12c, 0x21, 0 - .dw 0xcac0, 0xc12c, 0xcaff, 0xc12c, 0x21, 0 - .dw 0xcb40, 0xc12c, 0xcb7f, 0xc12c, 0x21, 0 - .dw 0xcbc0, 0xc12c, 0xcbff, 0xc12c, 0x21, 0 - .dw 0xcc40, 0xc12c, 0xcc7f, 0xc12c, 0x21, 0 - .dw 0xccc0, 0xc12c, 0xccff, 0xc12c, 0x21, 0 - .dw 0xcd40, 0xc12c, 0xcd7f, 0xc12c, 0x21, 0 - .dw 0xcdc0, 0xc12c, 0xcdff, 0xc12c, 0x21, 0 - .dw 0xce40, 0xc12c, 0xce7f, 0xc12c, 0x21, 0 - .dw 0xcec0, 0xc12c, 0xceff, 0xc12c, 0x21, 0 - .dw 0xcf40, 0xc12c, 0xcf7f, 0xc12c, 0x21, 0 - .dw 0xcfc0, 0xc12c, 0xcfff, 0xc12c, 0x21, 0 - .dw 0xd040, 0xc12c, 0xd07f, 0xc12c, 0x21, 0 - .dw 0xd0c0, 0xc12c, 0xd0ff, 0xc12c, 0x21, 0 - .dw 0xd140, 0xc12c, 0xd17f, 0xc12c, 0x21, 0 - .dw 0xd1c0, 0xc12c, 0xd1ff, 0xc12c, 0x21, 0 - .dw 0xd240, 0xc12c, 0xd27f, 0xc12c, 0x21, 0 - .dw 0xd2c0, 0xc12c, 0xd2ff, 0xc12c, 0x21, 0 - .dw 0xd340, 0xc12c, 0xd37f, 0xc12c, 0x21, 0 - .dw 0xd3c0, 0xc12c, 0xd3ff, 0xc12c, 0x21, 0 - .dw 0xd440, 0xc12c, 0xd47f, 0xc12c, 0x21, 0 - .dw 0xd4c0, 0xc12c, 0xd4ff, 0xc12c, 0x21, 0 - .dw 0xd540, 0xc12c, 0xd57f, 0xc12c, 0x21, 0 - .dw 0xd5c0, 0xc12c, 0xd5ff, 0xc12c, 0x21, 0 - .dw 0xd640, 0xc12c, 0xd67f, 0xc12c, 0x21, 0 - .dw 0xd6c0, 0xc12c, 0xd6ff, 0xc12c, 0x21, 0 - .dw 0xd740, 0xc12c, 0xd77f, 0xc12c, 0x21, 0 - .dw 0xd7c0, 0xc12c, 0xd7ff, 0xc12c, 0x21, 0 - .dw 0xd840, 0xc12c, 0xd87f, 0xc12c, 0x21, 0 - .dw 0xd8c0, 0xc12c, 0xd8ff, 0xc12c, 0x21, 0 - .dw 0xd940, 0xc12c, 0xd97f, 0xc12c, 0x21, 0 - .dw 0xd9c0, 0xc12c, 0xdfff, 0xc12c, 0x21, 0 - .dw 0xe040, 0xc12c, 0xe07f, 0xc12c, 0x21, 0 - .dw 0xe0c0, 0xc12c, 0xe0ff, 0xc12c, 0x21, 0 - .dw 0xe140, 0xc12c, 0xe17f, 0xc12c, 0x21, 0 - .dw 0xe1c0, 0xc12c, 0xe1ff, 0xc12c, 0x21, 0 - .dw 0xe240, 0xc12c, 0xe27f, 0xc12c, 0x21, 0 - .dw 0xe2c0, 0xc12c, 0xe2ff, 0xc12c, 0x21, 0 - .dw 0xe340, 0xc12c, 0xe37f, 0xc12c, 0x21, 0 - .dw 0xe3c0, 0xc12c, 0xe3ff, 0xc12c, 0x21, 0 - .dw 0xe440, 0xc12c, 0xe47f, 0xc12c, 0x21, 0 - .dw 0xe4c0, 0xc12c, 0xe4ff, 0xc12c, 0x21, 0 - .dw 0xe540, 0xc12c, 0xe57f, 0xc12c, 0x21, 0 - .dw 0xe5c0, 0xc12c, 0xe5ff, 0xc12c, 0x21, 0 - .dw 0xe640, 0xc12c, 0xe67f, 0xc12c, 0x21, 0 - .dw 0xe6c0, 0xc12c, 0xe6ff, 0xc12c, 0x21, 0 - .dw 0xe740, 0xc12c, 0xe77f, 0xc12c, 0x21, 0 - .dw 0xe7c0, 0xc12c, 0xe7ff, 0xc12c, 0x21, 0 - .dw 0xe840, 0xc12c, 0xe87f, 0xc12c, 0x21, 0 - .dw 0xe8c0, 0xc12c, 0xe8ff, 0xc12c, 0x21, 0 - .dw 0xe940, 0xc12c, 0xe97f, 0xc12c, 0x21, 0 - .dw 0xe9c0, 0xc12c, 0xe9ff, 0xc12c, 0x21, 0 - .dw 0xea40, 0xc12c, 0xea7f, 0xc12c, 0x21, 0 - .dw 0xeac0, 0xc12c, 0xeaff, 0xc12c, 0x21, 0 - .dw 0xeb40, 0xc12c, 0xeb7f, 0xc12c, 0x21, 0 - .dw 0xebc0, 0xc12c, 0xebff, 0xc12c, 0x21, 0 - .dw 0xec40, 0xc12c, 0xec7f, 0xc12c, 0x21, 0 - .dw 0xecc0, 0xc12c, 0xecff, 0xc12c, 0x21, 0 - .dw 0xed40, 0xc12c, 0xed7f, 0xc12c, 0x21, 0 - .dw 0xedc0, 0xc12c, 0xedff, 0xc12c, 0x21, 0 - .dw 0xee40, 0xc12c, 0xee7f, 0xc12c, 0x21, 0 - .dw 0xeec0, 0xc12c, 0xeeff, 0xc12c, 0x21, 0 - .dw 0xef40, 0xc12c, 0xef7f, 0xc12c, 0x21, 0 - .dw 0xefc0, 0xc12c, 0xefff, 0xc12c, 0x21, 0 - .dw 0xf040, 0xc12c, 0xf07f, 0xc12c, 0x21, 0 - .dw 0xf0c0, 0xc12c, 0xf0ff, 0xc12c, 0x21, 0 - .dw 0xf140, 0xc12c, 0xf17f, 0xc12c, 0x21, 0 - .dw 0xf1c0, 0xc12c, 0xf1ff, 0xc12c, 0x21, 0 - .dw 0xf240, 0xc12c, 0xf27f, 0xc12c, 0x21, 0 - .dw 0xf2c0, 0xc12c, 0xf2ff, 0xc12c, 0x21, 0 - .dw 0xf340, 0xc12c, 0xf37f, 0xc12c, 0x21, 0 - .dw 0xf3c0, 0xc12c, 0xf3ff, 0xc12c, 0x21, 0 - .dw 0xf440, 0xc12c, 0xf47f, 0xc12c, 0x21, 0 - .dw 0xf4c0, 0xc12c, 0xf4ff, 0xc12c, 0x21, 0 - .dw 0xf540, 0xc12c, 0xf57f, 0xc12c, 0x21, 0 - .dw 0xf5c0, 0xc12c, 0xf5ff, 0xc12c, 0x21, 0 - .dw 0xf640, 0xc12c, 0xf67f, 0xc12c, 0x21, 0 - .dw 0xf6c0, 0xc12c, 0xf6ff, 0xc12c, 0x21, 0 - .dw 0xf740, 0xc12c, 0xf77f, 0xc12c, 0x21, 0 - .dw 0xf7c0, 0xc12c, 0xf7ff, 0xc12c, 0x21, 0 - .dw 0xf840, 0xc12c, 0xf87f, 0xc12c, 0x21, 0 - .dw 0xf8c0, 0xc12c, 0xf8ff, 0xc12c, 0x21, 0 - .dw 0xf940, 0xc12c, 0xf97f, 0xc12c, 0x21, 0 - .dw 0xf9c0, 0xc12c, 0xffff, 0xc12c, 0x21, 0 - .dw 0x0040, 0xc12d, 0x007f, 0xc12d, 0x21, 0 - .dw 0x00c0, 0xc12d, 0x00ff, 0xc12d, 0x21, 0 - .dw 0x0140, 0xc12d, 0x017f, 0xc12d, 0x21, 0 - .dw 0x01c0, 0xc12d, 0x01ff, 0xc12d, 0x21, 0 - .dw 0x0240, 0xc12d, 0x027f, 0xc12d, 0x21, 0 - .dw 0x02c0, 0xc12d, 0x02ff, 0xc12d, 0x21, 0 - .dw 0x0340, 0xc12d, 0x037f, 0xc12d, 0x21, 0 - .dw 0x03c0, 0xc12d, 0x03ff, 0xc12d, 0x21, 0 - .dw 0x0440, 0xc12d, 0x047f, 0xc12d, 0x21, 0 - .dw 0x04c0, 0xc12d, 0x04ff, 0xc12d, 0x21, 0 - .dw 0x0540, 0xc12d, 0x057f, 0xc12d, 0x21, 0 - .dw 0x05c0, 0xc12d, 0x05ff, 0xc12d, 0x21, 0 - .dw 0x0640, 0xc12d, 0x067f, 0xc12d, 0x21, 0 - .dw 0x06c0, 0xc12d, 0x06ff, 0xc12d, 0x21, 0 - .dw 0x0740, 0xc12d, 0x077f, 0xc12d, 0x21, 0 - .dw 0x07c0, 0xc12d, 0x07ff, 0xc12d, 0x21, 0 - .dw 0x0840, 0xc12d, 0x087f, 0xc12d, 0x21, 0 - .dw 0x08c0, 0xc12d, 0x08ff, 0xc12d, 0x21, 0 - .dw 0x0940, 0xc12d, 0x097f, 0xc12d, 0x21, 0 - .dw 0x09c0, 0xc12d, 0x09ff, 0xc12d, 0x21, 0 - .dw 0x0a40, 0xc12d, 0x0a7f, 0xc12d, 0x21, 0 - .dw 0x0ac0, 0xc12d, 0x0aff, 0xc12d, 0x21, 0 - .dw 0x0b40, 0xc12d, 0x0b7f, 0xc12d, 0x21, 0 - .dw 0x0bc0, 0xc12d, 0x0bff, 0xc12d, 0x21, 0 - .dw 0x0c40, 0xc12d, 0x0c7f, 0xc12d, 0x21, 0 - .dw 0x0cc0, 0xc12d, 0x0cff, 0xc12d, 0x21, 0 - .dw 0x0d40, 0xc12d, 0x0d7f, 0xc12d, 0x21, 0 - .dw 0x0dc0, 0xc12d, 0x0dff, 0xc12d, 0x21, 0 - .dw 0x0e40, 0xc12d, 0x0e7f, 0xc12d, 0x21, 0 - .dw 0x0ec0, 0xc12d, 0x0eff, 0xc12d, 0x21, 0 - .dw 0x0f40, 0xc12d, 0x0f7f, 0xc12d, 0x21, 0 - .dw 0x0fc0, 0xc12d, 0x0fff, 0xc12d, 0x21, 0 - .dw 0x1040, 0xc12d, 0x107f, 0xc12d, 0x21, 0 - .dw 0x10c0, 0xc12d, 0x10ff, 0xc12d, 0x21, 0 - .dw 0x1140, 0xc12d, 0x117f, 0xc12d, 0x21, 0 - .dw 0x11c0, 0xc12d, 0x11ff, 0xc12d, 0x21, 0 - .dw 0x1240, 0xc12d, 0x127f, 0xc12d, 0x21, 0 - .dw 0x12c0, 0xc12d, 0x12ff, 0xc12d, 0x21, 0 - .dw 0x1340, 0xc12d, 0x137f, 0xc12d, 0x21, 0 - .dw 0x13c0, 0xc12d, 0x13ff, 0xc12d, 0x21, 0 - .dw 0x1440, 0xc12d, 0x147f, 0xc12d, 0x21, 0 - .dw 0x14c0, 0xc12d, 0x14ff, 0xc12d, 0x21, 0 - .dw 0x1540, 0xc12d, 0x157f, 0xc12d, 0x21, 0 - .dw 0x15c0, 0xc12d, 0x15ff, 0xc12d, 0x21, 0 - .dw 0x1640, 0xc12d, 0x167f, 0xc12d, 0x21, 0 - .dw 0x16c0, 0xc12d, 0x16ff, 0xc12d, 0x21, 0 - .dw 0x1740, 0xc12d, 0x177f, 0xc12d, 0x21, 0 - .dw 0x17c0, 0xc12d, 0x17ff, 0xc12d, 0x21, 0 - .dw 0x1840, 0xc12d, 0x187f, 0xc12d, 0x21, 0 - .dw 0x18c0, 0xc12d, 0x18ff, 0xc12d, 0x21, 0 - .dw 0x1940, 0xc12d, 0x197f, 0xc12d, 0x21, 0 - .dw 0x19c0, 0xc12d, 0x1fff, 0xc12d, 0x21, 0 - .dw 0x2040, 0xc12d, 0x207f, 0xc12d, 0x21, 0 - .dw 0x20c0, 0xc12d, 0x20ff, 0xc12d, 0x21, 0 - .dw 0x2140, 0xc12d, 0x217f, 0xc12d, 0x21, 0 - .dw 0x21c0, 0xc12d, 0x21ff, 0xc12d, 0x21, 0 - .dw 0x2240, 0xc12d, 0x227f, 0xc12d, 0x21, 0 - .dw 0x22c0, 0xc12d, 0x22ff, 0xc12d, 0x21, 0 - .dw 0x2340, 0xc12d, 0x237f, 0xc12d, 0x21, 0 - .dw 0x23c0, 0xc12d, 0x23ff, 0xc12d, 0x21, 0 - .dw 0x2440, 0xc12d, 0x247f, 0xc12d, 0x21, 0 - .dw 0x24c0, 0xc12d, 0x24ff, 0xc12d, 0x21, 0 - .dw 0x2540, 0xc12d, 0x257f, 0xc12d, 0x21, 0 - .dw 0x25c0, 0xc12d, 0x25ff, 0xc12d, 0x21, 0 - .dw 0x2640, 0xc12d, 0x267f, 0xc12d, 0x21, 0 - .dw 0x26c0, 0xc12d, 0x26ff, 0xc12d, 0x21, 0 - .dw 0x2740, 0xc12d, 0x277f, 0xc12d, 0x21, 0 - .dw 0x27c0, 0xc12d, 0x27ff, 0xc12d, 0x21, 0 - .dw 0x2840, 0xc12d, 0x287f, 0xc12d, 0x21, 0 - .dw 0x28c0, 0xc12d, 0x28ff, 0xc12d, 0x21, 0 - .dw 0x2940, 0xc12d, 0x297f, 0xc12d, 0x21, 0 - .dw 0x29c0, 0xc12d, 0x29ff, 0xc12d, 0x21, 0 - .dw 0x2a40, 0xc12d, 0x2a7f, 0xc12d, 0x21, 0 - .dw 0x2ac0, 0xc12d, 0x2aff, 0xc12d, 0x21, 0 - .dw 0x2b40, 0xc12d, 0x2b7f, 0xc12d, 0x21, 0 - .dw 0x2bc0, 0xc12d, 0x2bff, 0xc12d, 0x21, 0 - .dw 0x2c40, 0xc12d, 0x2c7f, 0xc12d, 0x21, 0 - .dw 0x2cc0, 0xc12d, 0x2cff, 0xc12d, 0x21, 0 - .dw 0x2d40, 0xc12d, 0x2d7f, 0xc12d, 0x21, 0 - .dw 0x2dc0, 0xc12d, 0x2dff, 0xc12d, 0x21, 0 - .dw 0x2e40, 0xc12d, 0x2e7f, 0xc12d, 0x21, 0 - .dw 0x2ec0, 0xc12d, 0x2eff, 0xc12d, 0x21, 0 - .dw 0x2f40, 0xc12d, 0x2f7f, 0xc12d, 0x21, 0 - .dw 0x2fc0, 0xc12d, 0x2fff, 0xc12d, 0x21, 0 - .dw 0x3040, 0xc12d, 0x307f, 0xc12d, 0x21, 0 - .dw 0x30c0, 0xc12d, 0x30ff, 0xc12d, 0x21, 0 - .dw 0x3140, 0xc12d, 0x317f, 0xc12d, 0x21, 0 - .dw 0x31c0, 0xc12d, 0x31ff, 0xc12d, 0x21, 0 - .dw 0x3240, 0xc12d, 0x327f, 0xc12d, 0x21, 0 - .dw 0x32c0, 0xc12d, 0x32ff, 0xc12d, 0x21, 0 - .dw 0x3340, 0xc12d, 0x337f, 0xc12d, 0x21, 0 - .dw 0x33c0, 0xc12d, 0x33ff, 0xc12d, 0x21, 0 - .dw 0x3440, 0xc12d, 0x347f, 0xc12d, 0x21, 0 - .dw 0x34c0, 0xc12d, 0x34ff, 0xc12d, 0x21, 0 - .dw 0x3540, 0xc12d, 0x357f, 0xc12d, 0x21, 0 - .dw 0x35c0, 0xc12d, 0x35ff, 0xc12d, 0x21, 0 - .dw 0x3640, 0xc12d, 0x367f, 0xc12d, 0x21, 0 - .dw 0x36c0, 0xc12d, 0x36ff, 0xc12d, 0x21, 0 - .dw 0x3740, 0xc12d, 0x377f, 0xc12d, 0x21, 0 - .dw 0x37c0, 0xc12d, 0x37ff, 0xc12d, 0x21, 0 - .dw 0x3840, 0xc12d, 0x387f, 0xc12d, 0x21, 0 - .dw 0x38c0, 0xc12d, 0x38ff, 0xc12d, 0x21, 0 - .dw 0x3940, 0xc12d, 0x397f, 0xc12d, 0x21, 0 - .dw 0x39c0, 0xc12d, 0x3fff, 0xc12d, 0x21, 0 - .dw 0x4040, 0xc12d, 0x407f, 0xc12d, 0x21, 0 - .dw 0x40c0, 0xc12d, 0x40ff, 0xc12d, 0x21, 0 - .dw 0x4140, 0xc12d, 0x417f, 0xc12d, 0x21, 0 - .dw 0x41c0, 0xc12d, 0x41ff, 0xc12d, 0x21, 0 - .dw 0x4240, 0xc12d, 0x427f, 0xc12d, 0x21, 0 - .dw 0x42c0, 0xc12d, 0x42ff, 0xc12d, 0x21, 0 - .dw 0x4340, 0xc12d, 0x437f, 0xc12d, 0x21, 0 - .dw 0x43c0, 0xc12d, 0x43ff, 0xc12d, 0x21, 0 - .dw 0x4440, 0xc12d, 0x447f, 0xc12d, 0x21, 0 - .dw 0x44c0, 0xc12d, 0x44ff, 0xc12d, 0x21, 0 - .dw 0x4540, 0xc12d, 0x457f, 0xc12d, 0x21, 0 - .dw 0x45c0, 0xc12d, 0x45ff, 0xc12d, 0x21, 0 - .dw 0x4640, 0xc12d, 0x467f, 0xc12d, 0x21, 0 - .dw 0x46c0, 0xc12d, 0x46ff, 0xc12d, 0x21, 0 - .dw 0x4740, 0xc12d, 0x477f, 0xc12d, 0x21, 0 - .dw 0x47c0, 0xc12d, 0x47ff, 0xc12d, 0x21, 0 - .dw 0x4840, 0xc12d, 0x487f, 0xc12d, 0x21, 0 - .dw 0x48c0, 0xc12d, 0x48ff, 0xc12d, 0x21, 0 - .dw 0x4940, 0xc12d, 0x497f, 0xc12d, 0x21, 0 - .dw 0x49c0, 0xc12d, 0x49ff, 0xc12d, 0x21, 0 - .dw 0x4a40, 0xc12d, 0x4a7f, 0xc12d, 0x21, 0 - .dw 0x4ac0, 0xc12d, 0x4aff, 0xc12d, 0x21, 0 - .dw 0x4b40, 0xc12d, 0x4b7f, 0xc12d, 0x21, 0 - .dw 0x4bc0, 0xc12d, 0x4bff, 0xc12d, 0x21, 0 - .dw 0x4c40, 0xc12d, 0x4c7f, 0xc12d, 0x21, 0 - .dw 0x4cc0, 0xc12d, 0x4cff, 0xc12d, 0x21, 0 - .dw 0x4d40, 0xc12d, 0x4d7f, 0xc12d, 0x21, 0 - .dw 0x4dc0, 0xc12d, 0x4dff, 0xc12d, 0x21, 0 - .dw 0x4e40, 0xc12d, 0x4e7f, 0xc12d, 0x21, 0 - .dw 0x4ec0, 0xc12d, 0x4eff, 0xc12d, 0x21, 0 - .dw 0x4f40, 0xc12d, 0x4f7f, 0xc12d, 0x21, 0 - .dw 0x4fc0, 0xc12d, 0x4fff, 0xc12d, 0x21, 0 - .dw 0x5040, 0xc12d, 0x507f, 0xc12d, 0x21, 0 - .dw 0x50c0, 0xc12d, 0x50ff, 0xc12d, 0x21, 0 - .dw 0x5140, 0xc12d, 0x517f, 0xc12d, 0x21, 0 - .dw 0x51c0, 0xc12d, 0x51ff, 0xc12d, 0x21, 0 - .dw 0x5240, 0xc12d, 0x527f, 0xc12d, 0x21, 0 - .dw 0x52c0, 0xc12d, 0x52ff, 0xc12d, 0x21, 0 - .dw 0x5340, 0xc12d, 0x537f, 0xc12d, 0x21, 0 - .dw 0x53c0, 0xc12d, 0x53ff, 0xc12d, 0x21, 0 - .dw 0x5440, 0xc12d, 0x547f, 0xc12d, 0x21, 0 - .dw 0x54c0, 0xc12d, 0x54ff, 0xc12d, 0x21, 0 - .dw 0x5540, 0xc12d, 0x557f, 0xc12d, 0x21, 0 - .dw 0x55c0, 0xc12d, 0x55ff, 0xc12d, 0x21, 0 - .dw 0x5640, 0xc12d, 0x567f, 0xc12d, 0x21, 0 - .dw 0x56c0, 0xc12d, 0x56ff, 0xc12d, 0x21, 0 - .dw 0x5740, 0xc12d, 0x577f, 0xc12d, 0x21, 0 - .dw 0x57c0, 0xc12d, 0x57ff, 0xc12d, 0x21, 0 - .dw 0x5840, 0xc12d, 0x587f, 0xc12d, 0x21, 0 - .dw 0x58c0, 0xc12d, 0x58ff, 0xc12d, 0x21, 0 - .dw 0x5940, 0xc12d, 0x597f, 0xc12d, 0x21, 0 - .dw 0x59c0, 0xc12d, 0x5fff, 0xc12d, 0x21, 0 - .dw 0x6040, 0xc12d, 0x607f, 0xc12d, 0x21, 0 - .dw 0x60c0, 0xc12d, 0x60ff, 0xc12d, 0x21, 0 - .dw 0x6140, 0xc12d, 0x617f, 0xc12d, 0x21, 0 - .dw 0x61c0, 0xc12d, 0x61ff, 0xc12d, 0x21, 0 - .dw 0x6240, 0xc12d, 0x627f, 0xc12d, 0x21, 0 - .dw 0x62c0, 0xc12d, 0x62ff, 0xc12d, 0x21, 0 - .dw 0x6340, 0xc12d, 0x637f, 0xc12d, 0x21, 0 - .dw 0x63c0, 0xc12d, 0x63ff, 0xc12d, 0x21, 0 - .dw 0x6440, 0xc12d, 0x647f, 0xc12d, 0x21, 0 - .dw 0x64c0, 0xc12d, 0x64ff, 0xc12d, 0x21, 0 - .dw 0x6540, 0xc12d, 0x657f, 0xc12d, 0x21, 0 - .dw 0x65c0, 0xc12d, 0x65ff, 0xc12d, 0x21, 0 - .dw 0x6640, 0xc12d, 0x667f, 0xc12d, 0x21, 0 - .dw 0x66c0, 0xc12d, 0x66ff, 0xc12d, 0x21, 0 - .dw 0x6740, 0xc12d, 0x677f, 0xc12d, 0x21, 0 - .dw 0x67c0, 0xc12d, 0x67ff, 0xc12d, 0x21, 0 - .dw 0x6840, 0xc12d, 0x687f, 0xc12d, 0x21, 0 - .dw 0x68c0, 0xc12d, 0x68ff, 0xc12d, 0x21, 0 - .dw 0x6940, 0xc12d, 0x697f, 0xc12d, 0x21, 0 - .dw 0x69c0, 0xc12d, 0x69ff, 0xc12d, 0x21, 0 - .dw 0x6a40, 0xc12d, 0x6a7f, 0xc12d, 0x21, 0 - .dw 0x6ac0, 0xc12d, 0x6aff, 0xc12d, 0x21, 0 - .dw 0x6b40, 0xc12d, 0x6b7f, 0xc12d, 0x21, 0 - .dw 0x6bc0, 0xc12d, 0x6bff, 0xc12d, 0x21, 0 - .dw 0x6c40, 0xc12d, 0x6c7f, 0xc12d, 0x21, 0 - .dw 0x6cc0, 0xc12d, 0x6cff, 0xc12d, 0x21, 0 - .dw 0x6d40, 0xc12d, 0x6d7f, 0xc12d, 0x21, 0 - .dw 0x6dc0, 0xc12d, 0x6dff, 0xc12d, 0x21, 0 - .dw 0x6e40, 0xc12d, 0x6e7f, 0xc12d, 0x21, 0 - .dw 0x6ec0, 0xc12d, 0x6eff, 0xc12d, 0x21, 0 - .dw 0x6f40, 0xc12d, 0x6f7f, 0xc12d, 0x21, 0 - .dw 0x6fc0, 0xc12d, 0x6fff, 0xc12d, 0x21, 0 - .dw 0x7040, 0xc12d, 0x707f, 0xc12d, 0x21, 0 - .dw 0x70c0, 0xc12d, 0x70ff, 0xc12d, 0x21, 0 - .dw 0x7140, 0xc12d, 0x717f, 0xc12d, 0x21, 0 - .dw 0x71c0, 0xc12d, 0x71ff, 0xc12d, 0x21, 0 - .dw 0x7240, 0xc12d, 0x727f, 0xc12d, 0x21, 0 - .dw 0x72c0, 0xc12d, 0x72ff, 0xc12d, 0x21, 0 - .dw 0x7340, 0xc12d, 0x737f, 0xc12d, 0x21, 0 - .dw 0x73c0, 0xc12d, 0x73ff, 0xc12d, 0x21, 0 - .dw 0x7440, 0xc12d, 0x747f, 0xc12d, 0x21, 0 - .dw 0x74c0, 0xc12d, 0x74ff, 0xc12d, 0x21, 0 - .dw 0x7540, 0xc12d, 0x757f, 0xc12d, 0x21, 0 - .dw 0x75c0, 0xc12d, 0x75ff, 0xc12d, 0x21, 0 - .dw 0x7640, 0xc12d, 0x767f, 0xc12d, 0x21, 0 - .dw 0x76c0, 0xc12d, 0x76ff, 0xc12d, 0x21, 0 - .dw 0x7740, 0xc12d, 0x777f, 0xc12d, 0x21, 0 - .dw 0x77c0, 0xc12d, 0x77ff, 0xc12d, 0x21, 0 - .dw 0x7840, 0xc12d, 0x787f, 0xc12d, 0x21, 0 - .dw 0x78c0, 0xc12d, 0x78ff, 0xc12d, 0x21, 0 - .dw 0x7940, 0xc12d, 0x797f, 0xc12d, 0x21, 0 - .dw 0x79c0, 0xc12d, 0x7fff, 0xc12d, 0x21, 0 - .dw 0x8040, 0xc12d, 0x807f, 0xc12d, 0x21, 0 - .dw 0x80c0, 0xc12d, 0x80ff, 0xc12d, 0x21, 0 - .dw 0x8140, 0xc12d, 0x817f, 0xc12d, 0x21, 0 - .dw 0x81c0, 0xc12d, 0x81ff, 0xc12d, 0x21, 0 - .dw 0x8240, 0xc12d, 0x827f, 0xc12d, 0x21, 0 - .dw 0x82c0, 0xc12d, 0x82ff, 0xc12d, 0x21, 0 - .dw 0x8340, 0xc12d, 0x837f, 0xc12d, 0x21, 0 - .dw 0x83c0, 0xc12d, 0x83ff, 0xc12d, 0x21, 0 - .dw 0x8440, 0xc12d, 0x847f, 0xc12d, 0x21, 0 - .dw 0x84c0, 0xc12d, 0x84ff, 0xc12d, 0x21, 0 - .dw 0x8540, 0xc12d, 0x857f, 0xc12d, 0x21, 0 - .dw 0x85c0, 0xc12d, 0x85ff, 0xc12d, 0x21, 0 - .dw 0x8640, 0xc12d, 0x867f, 0xc12d, 0x21, 0 - .dw 0x86c0, 0xc12d, 0x86ff, 0xc12d, 0x21, 0 - .dw 0x8740, 0xc12d, 0x877f, 0xc12d, 0x21, 0 - .dw 0x87c0, 0xc12d, 0x87ff, 0xc12d, 0x21, 0 - .dw 0x8840, 0xc12d, 0x887f, 0xc12d, 0x21, 0 - .dw 0x88c0, 0xc12d, 0x88ff, 0xc12d, 0x21, 0 - .dw 0x8940, 0xc12d, 0x897f, 0xc12d, 0x21, 0 - .dw 0x89c0, 0xc12d, 0x89ff, 0xc12d, 0x21, 0 - .dw 0x8a40, 0xc12d, 0x8a7f, 0xc12d, 0x21, 0 - .dw 0x8ac0, 0xc12d, 0x8aff, 0xc12d, 0x21, 0 - .dw 0x8b40, 0xc12d, 0x8b7f, 0xc12d, 0x21, 0 - .dw 0x8bc0, 0xc12d, 0x8bff, 0xc12d, 0x21, 0 - .dw 0x8c40, 0xc12d, 0x8c7f, 0xc12d, 0x21, 0 - .dw 0x8cc0, 0xc12d, 0x8cff, 0xc12d, 0x21, 0 - .dw 0x8d40, 0xc12d, 0x8d7f, 0xc12d, 0x21, 0 - .dw 0x8dc0, 0xc12d, 0x8dff, 0xc12d, 0x21, 0 - .dw 0x8e40, 0xc12d, 0x8e7f, 0xc12d, 0x21, 0 - .dw 0x8ec0, 0xc12d, 0x8eff, 0xc12d, 0x21, 0 - .dw 0x8f40, 0xc12d, 0x8f7f, 0xc12d, 0x21, 0 - .dw 0x8fc0, 0xc12d, 0x8fff, 0xc12d, 0x21, 0 - .dw 0x9040, 0xc12d, 0x907f, 0xc12d, 0x21, 0 - .dw 0x90c0, 0xc12d, 0x90ff, 0xc12d, 0x21, 0 - .dw 0x9140, 0xc12d, 0x917f, 0xc12d, 0x21, 0 - .dw 0x91c0, 0xc12d, 0x91ff, 0xc12d, 0x21, 0 - .dw 0x9240, 0xc12d, 0x927f, 0xc12d, 0x21, 0 - .dw 0x92c0, 0xc12d, 0x92ff, 0xc12d, 0x21, 0 - .dw 0x9340, 0xc12d, 0x937f, 0xc12d, 0x21, 0 - .dw 0x93c0, 0xc12d, 0x93ff, 0xc12d, 0x21, 0 - .dw 0x9440, 0xc12d, 0x947f, 0xc12d, 0x21, 0 - .dw 0x94c0, 0xc12d, 0x94ff, 0xc12d, 0x21, 0 - .dw 0x9540, 0xc12d, 0x957f, 0xc12d, 0x21, 0 - .dw 0x95c0, 0xc12d, 0x95ff, 0xc12d, 0x21, 0 - .dw 0x9640, 0xc12d, 0x967f, 0xc12d, 0x21, 0 - .dw 0x96c0, 0xc12d, 0x96ff, 0xc12d, 0x21, 0 - .dw 0x9740, 0xc12d, 0x977f, 0xc12d, 0x21, 0 - .dw 0x97c0, 0xc12d, 0x97ff, 0xc12d, 0x21, 0 - .dw 0x9840, 0xc12d, 0x987f, 0xc12d, 0x21, 0 - .dw 0x98c0, 0xc12d, 0x98ff, 0xc12d, 0x21, 0 - .dw 0x9940, 0xc12d, 0x997f, 0xc12d, 0x21, 0 - .dw 0x99c0, 0xc12d, 0x9fff, 0xc12d, 0x21, 0 - .dw 0xa040, 0xc12d, 0xa07f, 0xc12d, 0x21, 0 - .dw 0xa0c0, 0xc12d, 0xa0ff, 0xc12d, 0x21, 0 - .dw 0xa140, 0xc12d, 0xa17f, 0xc12d, 0x21, 0 - .dw 0xa1c0, 0xc12d, 0xa1ff, 0xc12d, 0x21, 0 - .dw 0xa240, 0xc12d, 0xa27f, 0xc12d, 0x21, 0 - .dw 0xa2c0, 0xc12d, 0xa2ff, 0xc12d, 0x21, 0 - .dw 0xa340, 0xc12d, 0xa37f, 0xc12d, 0x21, 0 - .dw 0xa3c0, 0xc12d, 0xa3ff, 0xc12d, 0x21, 0 - .dw 0xa440, 0xc12d, 0xa47f, 0xc12d, 0x21, 0 - .dw 0xa4c0, 0xc12d, 0xa4ff, 0xc12d, 0x21, 0 - .dw 0xa540, 0xc12d, 0xa57f, 0xc12d, 0x21, 0 - .dw 0xa5c0, 0xc12d, 0xa5ff, 0xc12d, 0x21, 0 - .dw 0xa640, 0xc12d, 0xa67f, 0xc12d, 0x21, 0 - .dw 0xa6c0, 0xc12d, 0xa6ff, 0xc12d, 0x21, 0 - .dw 0xa740, 0xc12d, 0xa77f, 0xc12d, 0x21, 0 - .dw 0xa7c0, 0xc12d, 0xa7ff, 0xc12d, 0x21, 0 - .dw 0xa840, 0xc12d, 0xa87f, 0xc12d, 0x21, 0 - .dw 0xa8c0, 0xc12d, 0xa8ff, 0xc12d, 0x21, 0 - .dw 0xa940, 0xc12d, 0xa97f, 0xc12d, 0x21, 0 - .dw 0xa9c0, 0xc12d, 0xa9ff, 0xc12d, 0x21, 0 - .dw 0xaa40, 0xc12d, 0xaa7f, 0xc12d, 0x21, 0 - .dw 0xaac0, 0xc12d, 0xaaff, 0xc12d, 0x21, 0 - .dw 0xab40, 0xc12d, 0xab7f, 0xc12d, 0x21, 0 - .dw 0xabc0, 0xc12d, 0xabff, 0xc12d, 0x21, 0 - .dw 0xac40, 0xc12d, 0xac7f, 0xc12d, 0x21, 0 - .dw 0xacc0, 0xc12d, 0xacff, 0xc12d, 0x21, 0 - .dw 0xad40, 0xc12d, 0xad7f, 0xc12d, 0x21, 0 - .dw 0xadc0, 0xc12d, 0xadff, 0xc12d, 0x21, 0 - .dw 0xae40, 0xc12d, 0xae7f, 0xc12d, 0x21, 0 - .dw 0xaec0, 0xc12d, 0xaeff, 0xc12d, 0x21, 0 - .dw 0xaf40, 0xc12d, 0xaf7f, 0xc12d, 0x21, 0 - .dw 0xafc0, 0xc12d, 0xafff, 0xc12d, 0x21, 0 - .dw 0xb040, 0xc12d, 0xb07f, 0xc12d, 0x21, 0 - .dw 0xb0c0, 0xc12d, 0xb0ff, 0xc12d, 0x21, 0 - .dw 0xb140, 0xc12d, 0xb17f, 0xc12d, 0x21, 0 - .dw 0xb1c0, 0xc12d, 0xb1ff, 0xc12d, 0x21, 0 - .dw 0xb240, 0xc12d, 0xb27f, 0xc12d, 0x21, 0 - .dw 0xb2c0, 0xc12d, 0xb2ff, 0xc12d, 0x21, 0 - .dw 0xb340, 0xc12d, 0xb37f, 0xc12d, 0x21, 0 - .dw 0xb3c0, 0xc12d, 0xb3ff, 0xc12d, 0x21, 0 - .dw 0xb440, 0xc12d, 0xb47f, 0xc12d, 0x21, 0 - .dw 0xb4c0, 0xc12d, 0xb4ff, 0xc12d, 0x21, 0 - .dw 0xb540, 0xc12d, 0xb57f, 0xc12d, 0x21, 0 - .dw 0xb5c0, 0xc12d, 0xb5ff, 0xc12d, 0x21, 0 - .dw 0xb640, 0xc12d, 0xb67f, 0xc12d, 0x21, 0 - .dw 0xb6c0, 0xc12d, 0xb6ff, 0xc12d, 0x21, 0 - .dw 0xb740, 0xc12d, 0xb77f, 0xc12d, 0x21, 0 - .dw 0xb7c0, 0xc12d, 0xb7ff, 0xc12d, 0x21, 0 - .dw 0xb840, 0xc12d, 0xb87f, 0xc12d, 0x21, 0 - .dw 0xb8c0, 0xc12d, 0xb8ff, 0xc12d, 0x21, 0 - .dw 0xb940, 0xc12d, 0xb97f, 0xc12d, 0x21, 0 - .dw 0xb9c0, 0xc12d, 0xbfff, 0xc12d, 0x21, 0 - .dw 0xc040, 0xc12d, 0xc07f, 0xc12d, 0x21, 0 - .dw 0xc0c0, 0xc12d, 0xc0ff, 0xc12d, 0x21, 0 - .dw 0xc140, 0xc12d, 0xc17f, 0xc12d, 0x21, 0 - .dw 0xc1c0, 0xc12d, 0xc1ff, 0xc12d, 0x21, 0 - .dw 0xc240, 0xc12d, 0xc27f, 0xc12d, 0x21, 0 - .dw 0xc2c0, 0xc12d, 0xc2ff, 0xc12d, 0x21, 0 - .dw 0xc340, 0xc12d, 0xc37f, 0xc12d, 0x21, 0 - .dw 0xc3c0, 0xc12d, 0xc3ff, 0xc12d, 0x21, 0 - .dw 0xc440, 0xc12d, 0xc47f, 0xc12d, 0x21, 0 - .dw 0xc4c0, 0xc12d, 0xc4ff, 0xc12d, 0x21, 0 - .dw 0xc540, 0xc12d, 0xc57f, 0xc12d, 0x21, 0 - .dw 0xc5c0, 0xc12d, 0xc5ff, 0xc12d, 0x21, 0 - .dw 0xc640, 0xc12d, 0xc67f, 0xc12d, 0x21, 0 - .dw 0xc6c0, 0xc12d, 0xc6ff, 0xc12d, 0x21, 0 - .dw 0xc740, 0xc12d, 0xc77f, 0xc12d, 0x21, 0 - .dw 0xc7c0, 0xc12d, 0xc7ff, 0xc12d, 0x21, 0 - .dw 0xc840, 0xc12d, 0xc87f, 0xc12d, 0x21, 0 - .dw 0xc8c0, 0xc12d, 0xc8ff, 0xc12d, 0x21, 0 - .dw 0xc940, 0xc12d, 0xc97f, 0xc12d, 0x21, 0 - .dw 0xc9c0, 0xc12d, 0xc9ff, 0xc12d, 0x21, 0 - .dw 0xca40, 0xc12d, 0xca7f, 0xc12d, 0x21, 0 - .dw 0xcac0, 0xc12d, 0xcaff, 0xc12d, 0x21, 0 - .dw 0xcb40, 0xc12d, 0xcb7f, 0xc12d, 0x21, 0 - .dw 0xcbc0, 0xc12d, 0xcbff, 0xc12d, 0x21, 0 - .dw 0xcc40, 0xc12d, 0xcc7f, 0xc12d, 0x21, 0 - .dw 0xccc0, 0xc12d, 0xccff, 0xc12d, 0x21, 0 - .dw 0xcd40, 0xc12d, 0xcd7f, 0xc12d, 0x21, 0 - .dw 0xcdc0, 0xc12d, 0xcdff, 0xc12d, 0x21, 0 - .dw 0xce40, 0xc12d, 0xce7f, 0xc12d, 0x21, 0 - .dw 0xcec0, 0xc12d, 0xceff, 0xc12d, 0x21, 0 - .dw 0xcf40, 0xc12d, 0xcf7f, 0xc12d, 0x21, 0 - .dw 0xcfc0, 0xc12d, 0xcfff, 0xc12d, 0x21, 0 - .dw 0xd040, 0xc12d, 0xd07f, 0xc12d, 0x21, 0 - .dw 0xd0c0, 0xc12d, 0xd0ff, 0xc12d, 0x21, 0 - .dw 0xd140, 0xc12d, 0xd17f, 0xc12d, 0x21, 0 - .dw 0xd1c0, 0xc12d, 0xd1ff, 0xc12d, 0x21, 0 - .dw 0xd240, 0xc12d, 0xd27f, 0xc12d, 0x21, 0 - .dw 0xd2c0, 0xc12d, 0xd2ff, 0xc12d, 0x21, 0 - .dw 0xd340, 0xc12d, 0xd37f, 0xc12d, 0x21, 0 - .dw 0xd3c0, 0xc12d, 0xd3ff, 0xc12d, 0x21, 0 - .dw 0xd440, 0xc12d, 0xd47f, 0xc12d, 0x21, 0 - .dw 0xd4c0, 0xc12d, 0xd4ff, 0xc12d, 0x21, 0 - .dw 0xd540, 0xc12d, 0xd57f, 0xc12d, 0x21, 0 - .dw 0xd5c0, 0xc12d, 0xd5ff, 0xc12d, 0x21, 0 - .dw 0xd640, 0xc12d, 0xd67f, 0xc12d, 0x21, 0 - .dw 0xd6c0, 0xc12d, 0xd6ff, 0xc12d, 0x21, 0 - .dw 0xd740, 0xc12d, 0xd77f, 0xc12d, 0x21, 0 - .dw 0xd7c0, 0xc12d, 0xd7ff, 0xc12d, 0x21, 0 - .dw 0xd840, 0xc12d, 0xd87f, 0xc12d, 0x21, 0 - .dw 0xd8c0, 0xc12d, 0xd8ff, 0xc12d, 0x21, 0 - .dw 0xd940, 0xc12d, 0xd97f, 0xc12d, 0x21, 0 - .dw 0xd9c0, 0xc12d, 0xdfff, 0xc12d, 0x21, 0 - .dw 0xe040, 0xc12d, 0xe07f, 0xc12d, 0x21, 0 - .dw 0xe0c0, 0xc12d, 0xe0ff, 0xc12d, 0x21, 0 - .dw 0xe140, 0xc12d, 0xe17f, 0xc12d, 0x21, 0 - .dw 0xe1c0, 0xc12d, 0xe1ff, 0xc12d, 0x21, 0 - .dw 0xe240, 0xc12d, 0xe27f, 0xc12d, 0x21, 0 - .dw 0xe2c0, 0xc12d, 0xe2ff, 0xc12d, 0x21, 0 - .dw 0xe340, 0xc12d, 0xe37f, 0xc12d, 0x21, 0 - .dw 0xe3c0, 0xc12d, 0xe3ff, 0xc12d, 0x21, 0 - .dw 0xe440, 0xc12d, 0xe47f, 0xc12d, 0x21, 0 - .dw 0xe4c0, 0xc12d, 0xe4ff, 0xc12d, 0x21, 0 - .dw 0xe540, 0xc12d, 0xe57f, 0xc12d, 0x21, 0 - .dw 0xe5c0, 0xc12d, 0xe5ff, 0xc12d, 0x21, 0 - .dw 0xe640, 0xc12d, 0xe67f, 0xc12d, 0x21, 0 - .dw 0xe6c0, 0xc12d, 0xe6ff, 0xc12d, 0x21, 0 - .dw 0xe740, 0xc12d, 0xe77f, 0xc12d, 0x21, 0 - .dw 0xe7c0, 0xc12d, 0xe7ff, 0xc12d, 0x21, 0 - .dw 0xe840, 0xc12d, 0xe87f, 0xc12d, 0x21, 0 - .dw 0xe8c0, 0xc12d, 0xe8ff, 0xc12d, 0x21, 0 - .dw 0xe940, 0xc12d, 0xe97f, 0xc12d, 0x21, 0 - .dw 0xe9c0, 0xc12d, 0xe9ff, 0xc12d, 0x21, 0 - .dw 0xea40, 0xc12d, 0xea7f, 0xc12d, 0x21, 0 - .dw 0xeac0, 0xc12d, 0xeaff, 0xc12d, 0x21, 0 - .dw 0xeb40, 0xc12d, 0xeb7f, 0xc12d, 0x21, 0 - .dw 0xebc0, 0xc12d, 0xebff, 0xc12d, 0x21, 0 - .dw 0xec40, 0xc12d, 0xec7f, 0xc12d, 0x21, 0 - .dw 0xecc0, 0xc12d, 0xecff, 0xc12d, 0x21, 0 - .dw 0xed40, 0xc12d, 0xed7f, 0xc12d, 0x21, 0 - .dw 0xedc0, 0xc12d, 0xedff, 0xc12d, 0x21, 0 - .dw 0xee40, 0xc12d, 0xee7f, 0xc12d, 0x21, 0 - .dw 0xeec0, 0xc12d, 0xeeff, 0xc12d, 0x21, 0 - .dw 0xef40, 0xc12d, 0xef7f, 0xc12d, 0x21, 0 - .dw 0xefc0, 0xc12d, 0xefff, 0xc12d, 0x21, 0 - .dw 0xf040, 0xc12d, 0xf07f, 0xc12d, 0x21, 0 - .dw 0xf0c0, 0xc12d, 0xf0ff, 0xc12d, 0x21, 0 - .dw 0xf140, 0xc12d, 0xf17f, 0xc12d, 0x21, 0 - .dw 0xf1c0, 0xc12d, 0xf1ff, 0xc12d, 0x21, 0 - .dw 0xf240, 0xc12d, 0xf27f, 0xc12d, 0x21, 0 - .dw 0xf2c0, 0xc12d, 0xf2ff, 0xc12d, 0x21, 0 - .dw 0xf340, 0xc12d, 0xf37f, 0xc12d, 0x21, 0 - .dw 0xf3c0, 0xc12d, 0xf3ff, 0xc12d, 0x21, 0 - .dw 0xf440, 0xc12d, 0xf47f, 0xc12d, 0x21, 0 - .dw 0xf4c0, 0xc12d, 0xf4ff, 0xc12d, 0x21, 0 - .dw 0xf540, 0xc12d, 0xf57f, 0xc12d, 0x21, 0 - .dw 0xf5c0, 0xc12d, 0xf5ff, 0xc12d, 0x21, 0 - .dw 0xf640, 0xc12d, 0xf67f, 0xc12d, 0x21, 0 - .dw 0xf6c0, 0xc12d, 0xf6ff, 0xc12d, 0x21, 0 - .dw 0xf740, 0xc12d, 0xf77f, 0xc12d, 0x21, 0 - .dw 0xf7c0, 0xc12d, 0xf7ff, 0xc12d, 0x21, 0 - .dw 0xf840, 0xc12d, 0xf87f, 0xc12d, 0x21, 0 - .dw 0xf8c0, 0xc12d, 0xf8ff, 0xc12d, 0x21, 0 - .dw 0xf940, 0xc12d, 0xf97f, 0xc12d, 0x21, 0 - .dw 0xf9c0, 0xc12d, 0xffff, 0xc12d, 0x21, 0 - .dw 0x0040, 0xc12e, 0x007f, 0xc12e, 0x21, 0 - .dw 0x00c0, 0xc12e, 0x00ff, 0xc12e, 0x21, 0 - .dw 0x0140, 0xc12e, 0x017f, 0xc12e, 0x21, 0 - .dw 0x01c0, 0xc12e, 0x01ff, 0xc12e, 0x21, 0 - .dw 0x0240, 0xc12e, 0x027f, 0xc12e, 0x21, 0 - .dw 0x02c0, 0xc12e, 0x02ff, 0xc12e, 0x21, 0 - .dw 0x0340, 0xc12e, 0x037f, 0xc12e, 0x21, 0 - .dw 0x03c0, 0xc12e, 0x03ff, 0xc12e, 0x21, 0 - .dw 0x0440, 0xc12e, 0x047f, 0xc12e, 0x21, 0 - .dw 0x04c0, 0xc12e, 0x04ff, 0xc12e, 0x21, 0 - .dw 0x0540, 0xc12e, 0x057f, 0xc12e, 0x21, 0 - .dw 0x05c0, 0xc12e, 0x05ff, 0xc12e, 0x21, 0 - .dw 0x0640, 0xc12e, 0x067f, 0xc12e, 0x21, 0 - .dw 0x06c0, 0xc12e, 0x06ff, 0xc12e, 0x21, 0 - .dw 0x0740, 0xc12e, 0x077f, 0xc12e, 0x21, 0 - .dw 0x07c0, 0xc12e, 0x07ff, 0xc12e, 0x21, 0 - .dw 0x0840, 0xc12e, 0x087f, 0xc12e, 0x21, 0 - .dw 0x08c0, 0xc12e, 0x08ff, 0xc12e, 0x21, 0 - .dw 0x0940, 0xc12e, 0x097f, 0xc12e, 0x21, 0 - .dw 0x09c0, 0xc12e, 0x09ff, 0xc12e, 0x21, 0 - .dw 0x0a40, 0xc12e, 0x0a7f, 0xc12e, 0x21, 0 - .dw 0x0ac0, 0xc12e, 0x0aff, 0xc12e, 0x21, 0 - .dw 0x0b40, 0xc12e, 0x0b7f, 0xc12e, 0x21, 0 - .dw 0x0bc0, 0xc12e, 0x0bff, 0xc12e, 0x21, 0 - .dw 0x0c40, 0xc12e, 0x0c7f, 0xc12e, 0x21, 0 - .dw 0x0cc0, 0xc12e, 0x0cff, 0xc12e, 0x21, 0 - .dw 0x0d40, 0xc12e, 0x0d7f, 0xc12e, 0x21, 0 - .dw 0x0dc0, 0xc12e, 0x0dff, 0xc12e, 0x21, 0 - .dw 0x0e40, 0xc12e, 0x0e7f, 0xc12e, 0x21, 0 - .dw 0x0ec0, 0xc12e, 0x0eff, 0xc12e, 0x21, 0 - .dw 0x0f40, 0xc12e, 0x0f7f, 0xc12e, 0x21, 0 - .dw 0x0fc0, 0xc12e, 0x0fff, 0xc12e, 0x21, 0 - .dw 0x1040, 0xc12e, 0x107f, 0xc12e, 0x21, 0 - .dw 0x10c0, 0xc12e, 0x10ff, 0xc12e, 0x21, 0 - .dw 0x1140, 0xc12e, 0x117f, 0xc12e, 0x21, 0 - .dw 0x11c0, 0xc12e, 0x11ff, 0xc12e, 0x21, 0 - .dw 0x1240, 0xc12e, 0x127f, 0xc12e, 0x21, 0 - .dw 0x12c0, 0xc12e, 0x12ff, 0xc12e, 0x21, 0 - .dw 0x1340, 0xc12e, 0x137f, 0xc12e, 0x21, 0 - .dw 0x13c0, 0xc12e, 0x13ff, 0xc12e, 0x21, 0 - .dw 0x1440, 0xc12e, 0x147f, 0xc12e, 0x21, 0 - .dw 0x14c0, 0xc12e, 0x14ff, 0xc12e, 0x21, 0 - .dw 0x1540, 0xc12e, 0x157f, 0xc12e, 0x21, 0 - .dw 0x15c0, 0xc12e, 0x15ff, 0xc12e, 0x21, 0 - .dw 0x1640, 0xc12e, 0x167f, 0xc12e, 0x21, 0 - .dw 0x16c0, 0xc12e, 0x16ff, 0xc12e, 0x21, 0 - .dw 0x1740, 0xc12e, 0x177f, 0xc12e, 0x21, 0 - .dw 0x17c0, 0xc12e, 0x17ff, 0xc12e, 0x21, 0 - .dw 0x1840, 0xc12e, 0x187f, 0xc12e, 0x21, 0 - .dw 0x18c0, 0xc12e, 0x18ff, 0xc12e, 0x21, 0 - .dw 0x1940, 0xc12e, 0x197f, 0xc12e, 0x21, 0 - .dw 0x19c0, 0xc12e, 0x1fff, 0xc12e, 0x21, 0 - .dw 0x2040, 0xc12e, 0x207f, 0xc12e, 0x21, 0 - .dw 0x20c0, 0xc12e, 0x20ff, 0xc12e, 0x21, 0 - .dw 0x2140, 0xc12e, 0x217f, 0xc12e, 0x21, 0 - .dw 0x21c0, 0xc12e, 0x21ff, 0xc12e, 0x21, 0 - .dw 0x2240, 0xc12e, 0x227f, 0xc12e, 0x21, 0 - .dw 0x22c0, 0xc12e, 0x22ff, 0xc12e, 0x21, 0 - .dw 0x2340, 0xc12e, 0x237f, 0xc12e, 0x21, 0 - .dw 0x23c0, 0xc12e, 0x23ff, 0xc12e, 0x21, 0 - .dw 0x2440, 0xc12e, 0x247f, 0xc12e, 0x21, 0 - .dw 0x24c0, 0xc12e, 0x24ff, 0xc12e, 0x21, 0 - .dw 0x2540, 0xc12e, 0x257f, 0xc12e, 0x21, 0 - .dw 0x25c0, 0xc12e, 0x25ff, 0xc12e, 0x21, 0 - .dw 0x2640, 0xc12e, 0x267f, 0xc12e, 0x21, 0 - .dw 0x26c0, 0xc12e, 0x26ff, 0xc12e, 0x21, 0 - .dw 0x2740, 0xc12e, 0x277f, 0xc12e, 0x21, 0 - .dw 0x27c0, 0xc12e, 0x27ff, 0xc12e, 0x21, 0 - .dw 0x2840, 0xc12e, 0x287f, 0xc12e, 0x21, 0 - .dw 0x28c0, 0xc12e, 0x28ff, 0xc12e, 0x21, 0 - .dw 0x2940, 0xc12e, 0x297f, 0xc12e, 0x21, 0 - .dw 0x29c0, 0xc12e, 0x29ff, 0xc12e, 0x21, 0 - .dw 0x2a40, 0xc12e, 0x2a7f, 0xc12e, 0x21, 0 - .dw 0x2ac0, 0xc12e, 0x2aff, 0xc12e, 0x21, 0 - .dw 0x2b40, 0xc12e, 0x2b7f, 0xc12e, 0x21, 0 - .dw 0x2bc0, 0xc12e, 0x2bff, 0xc12e, 0x21, 0 - .dw 0x2c40, 0xc12e, 0x2c7f, 0xc12e, 0x21, 0 - .dw 0x2cc0, 0xc12e, 0x2cff, 0xc12e, 0x21, 0 - .dw 0x2d40, 0xc12e, 0x2d7f, 0xc12e, 0x21, 0 - .dw 0x2dc0, 0xc12e, 0x2dff, 0xc12e, 0x21, 0 - .dw 0x2e40, 0xc12e, 0x2e7f, 0xc12e, 0x21, 0 - .dw 0x2ec0, 0xc12e, 0x2eff, 0xc12e, 0x21, 0 - .dw 0x2f40, 0xc12e, 0x2f7f, 0xc12e, 0x21, 0 - .dw 0x2fc0, 0xc12e, 0x2fff, 0xc12e, 0x21, 0 - .dw 0x3040, 0xc12e, 0x307f, 0xc12e, 0x21, 0 - .dw 0x30c0, 0xc12e, 0x30ff, 0xc12e, 0x21, 0 - .dw 0x3140, 0xc12e, 0x317f, 0xc12e, 0x21, 0 - .dw 0x31c0, 0xc12e, 0x31ff, 0xc12e, 0x21, 0 - .dw 0x3240, 0xc12e, 0x327f, 0xc12e, 0x21, 0 - .dw 0x32c0, 0xc12e, 0x32ff, 0xc12e, 0x21, 0 - .dw 0x3340, 0xc12e, 0x337f, 0xc12e, 0x21, 0 - .dw 0x33c0, 0xc12e, 0x33ff, 0xc12e, 0x21, 0 - .dw 0x3440, 0xc12e, 0x347f, 0xc12e, 0x21, 0 - .dw 0x34c0, 0xc12e, 0x34ff, 0xc12e, 0x21, 0 - .dw 0x3540, 0xc12e, 0x357f, 0xc12e, 0x21, 0 - .dw 0x35c0, 0xc12e, 0x35ff, 0xc12e, 0x21, 0 - .dw 0x3640, 0xc12e, 0x367f, 0xc12e, 0x21, 0 - .dw 0x36c0, 0xc12e, 0x36ff, 0xc12e, 0x21, 0 - .dw 0x3740, 0xc12e, 0x377f, 0xc12e, 0x21, 0 - .dw 0x37c0, 0xc12e, 0x37ff, 0xc12e, 0x21, 0 - .dw 0x3840, 0xc12e, 0x387f, 0xc12e, 0x21, 0 - .dw 0x38c0, 0xc12e, 0x38ff, 0xc12e, 0x21, 0 - .dw 0x3940, 0xc12e, 0x397f, 0xc12e, 0x21, 0 - .dw 0x39c0, 0xc12e, 0x3fff, 0xc12e, 0x21, 0 - .dw 0x4040, 0xc12e, 0x407f, 0xc12e, 0x21, 0 - .dw 0x40c0, 0xc12e, 0x40ff, 0xc12e, 0x21, 0 - .dw 0x4140, 0xc12e, 0x417f, 0xc12e, 0x21, 0 - .dw 0x41c0, 0xc12e, 0x41ff, 0xc12e, 0x21, 0 - .dw 0x4240, 0xc12e, 0x427f, 0xc12e, 0x21, 0 - .dw 0x42c0, 0xc12e, 0x42ff, 0xc12e, 0x21, 0 - .dw 0x4340, 0xc12e, 0x437f, 0xc12e, 0x21, 0 - .dw 0x43c0, 0xc12e, 0x43ff, 0xc12e, 0x21, 0 - .dw 0x4440, 0xc12e, 0x447f, 0xc12e, 0x21, 0 - .dw 0x44c0, 0xc12e, 0x44ff, 0xc12e, 0x21, 0 - .dw 0x4540, 0xc12e, 0x457f, 0xc12e, 0x21, 0 - .dw 0x45c0, 0xc12e, 0x45ff, 0xc12e, 0x21, 0 - .dw 0x4640, 0xc12e, 0x467f, 0xc12e, 0x21, 0 - .dw 0x46c0, 0xc12e, 0x46ff, 0xc12e, 0x21, 0 - .dw 0x4740, 0xc12e, 0x477f, 0xc12e, 0x21, 0 - .dw 0x47c0, 0xc12e, 0x47ff, 0xc12e, 0x21, 0 - .dw 0x4840, 0xc12e, 0x487f, 0xc12e, 0x21, 0 - .dw 0x48c0, 0xc12e, 0x48ff, 0xc12e, 0x21, 0 - .dw 0x4940, 0xc12e, 0x497f, 0xc12e, 0x21, 0 - .dw 0x49c0, 0xc12e, 0x49ff, 0xc12e, 0x21, 0 - .dw 0x4a40, 0xc12e, 0x4a7f, 0xc12e, 0x21, 0 - .dw 0x4ac0, 0xc12e, 0x4aff, 0xc12e, 0x21, 0 - .dw 0x4b40, 0xc12e, 0x4b7f, 0xc12e, 0x21, 0 - .dw 0x4bc0, 0xc12e, 0x4bff, 0xc12e, 0x21, 0 - .dw 0x4c40, 0xc12e, 0x4c7f, 0xc12e, 0x21, 0 - .dw 0x4cc0, 0xc12e, 0x4cff, 0xc12e, 0x21, 0 - .dw 0x4d40, 0xc12e, 0x4d7f, 0xc12e, 0x21, 0 - .dw 0x4dc0, 0xc12e, 0x4dff, 0xc12e, 0x21, 0 - .dw 0x4e40, 0xc12e, 0x4e7f, 0xc12e, 0x21, 0 - .dw 0x4ec0, 0xc12e, 0x4eff, 0xc12e, 0x21, 0 - .dw 0x4f40, 0xc12e, 0x4f7f, 0xc12e, 0x21, 0 - .dw 0x4fc0, 0xc12e, 0x4fff, 0xc12e, 0x21, 0 - .dw 0x5040, 0xc12e, 0x507f, 0xc12e, 0x21, 0 - .dw 0x50c0, 0xc12e, 0x50ff, 0xc12e, 0x21, 0 - .dw 0x5140, 0xc12e, 0x517f, 0xc12e, 0x21, 0 - .dw 0x51c0, 0xc12e, 0x51ff, 0xc12e, 0x21, 0 - .dw 0x5240, 0xc12e, 0x527f, 0xc12e, 0x21, 0 - .dw 0x52c0, 0xc12e, 0x52ff, 0xc12e, 0x21, 0 - .dw 0x5340, 0xc12e, 0x537f, 0xc12e, 0x21, 0 - .dw 0x53c0, 0xc12e, 0x53ff, 0xc12e, 0x21, 0 - .dw 0x5440, 0xc12e, 0x547f, 0xc12e, 0x21, 0 - .dw 0x54c0, 0xc12e, 0x54ff, 0xc12e, 0x21, 0 - .dw 0x5540, 0xc12e, 0x557f, 0xc12e, 0x21, 0 - .dw 0x55c0, 0xc12e, 0x55ff, 0xc12e, 0x21, 0 - .dw 0x5640, 0xc12e, 0x567f, 0xc12e, 0x21, 0 - .dw 0x56c0, 0xc12e, 0x56ff, 0xc12e, 0x21, 0 - .dw 0x5740, 0xc12e, 0x577f, 0xc12e, 0x21, 0 - .dw 0x57c0, 0xc12e, 0x57ff, 0xc12e, 0x21, 0 - .dw 0x5840, 0xc12e, 0x587f, 0xc12e, 0x21, 0 - .dw 0x58c0, 0xc12e, 0x58ff, 0xc12e, 0x21, 0 - .dw 0x5940, 0xc12e, 0x597f, 0xc12e, 0x21, 0 - .dw 0x59c0, 0xc12e, 0x5fff, 0xc12e, 0x21, 0 - .dw 0x6040, 0xc12e, 0x607f, 0xc12e, 0x21, 0 - .dw 0x60c0, 0xc12e, 0x60ff, 0xc12e, 0x21, 0 - .dw 0x6140, 0xc12e, 0x617f, 0xc12e, 0x21, 0 - .dw 0x61c0, 0xc12e, 0x61ff, 0xc12e, 0x21, 0 - .dw 0x6240, 0xc12e, 0x627f, 0xc12e, 0x21, 0 - .dw 0x62c0, 0xc12e, 0x62ff, 0xc12e, 0x21, 0 - .dw 0x6340, 0xc12e, 0x637f, 0xc12e, 0x21, 0 - .dw 0x63c0, 0xc12e, 0x63ff, 0xc12e, 0x21, 0 - .dw 0x6440, 0xc12e, 0x647f, 0xc12e, 0x21, 0 - .dw 0x64c0, 0xc12e, 0x64ff, 0xc12e, 0x21, 0 - .dw 0x6540, 0xc12e, 0x657f, 0xc12e, 0x21, 0 - .dw 0x65c0, 0xc12e, 0x65ff, 0xc12e, 0x21, 0 - .dw 0x6640, 0xc12e, 0x667f, 0xc12e, 0x21, 0 - .dw 0x66c0, 0xc12e, 0x66ff, 0xc12e, 0x21, 0 - .dw 0x6740, 0xc12e, 0x677f, 0xc12e, 0x21, 0 - .dw 0x67c0, 0xc12e, 0x67ff, 0xc12e, 0x21, 0 - .dw 0x6840, 0xc12e, 0x687f, 0xc12e, 0x21, 0 - .dw 0x68c0, 0xc12e, 0x68ff, 0xc12e, 0x21, 0 - .dw 0x6940, 0xc12e, 0x697f, 0xc12e, 0x21, 0 - .dw 0x69c0, 0xc12e, 0x69ff, 0xc12e, 0x21, 0 - .dw 0x6a40, 0xc12e, 0x6a7f, 0xc12e, 0x21, 0 - .dw 0x6ac0, 0xc12e, 0x6aff, 0xc12e, 0x21, 0 - .dw 0x6b40, 0xc12e, 0x6b7f, 0xc12e, 0x21, 0 - .dw 0x6bc0, 0xc12e, 0x6bff, 0xc12e, 0x21, 0 - .dw 0x6c40, 0xc12e, 0x6c7f, 0xc12e, 0x21, 0 - .dw 0x6cc0, 0xc12e, 0x6cff, 0xc12e, 0x21, 0 - .dw 0x6d40, 0xc12e, 0x6d7f, 0xc12e, 0x21, 0 - .dw 0x6dc0, 0xc12e, 0x6dff, 0xc12e, 0x21, 0 - .dw 0x6e40, 0xc12e, 0x6e7f, 0xc12e, 0x21, 0 - .dw 0x6ec0, 0xc12e, 0x6eff, 0xc12e, 0x21, 0 - .dw 0x6f40, 0xc12e, 0x6f7f, 0xc12e, 0x21, 0 - .dw 0x6fc0, 0xc12e, 0x6fff, 0xc12e, 0x21, 0 - .dw 0x7040, 0xc12e, 0x707f, 0xc12e, 0x21, 0 - .dw 0x70c0, 0xc12e, 0x70ff, 0xc12e, 0x21, 0 - .dw 0x7140, 0xc12e, 0x717f, 0xc12e, 0x21, 0 - .dw 0x71c0, 0xc12e, 0x71ff, 0xc12e, 0x21, 0 - .dw 0x7240, 0xc12e, 0x727f, 0xc12e, 0x21, 0 - .dw 0x72c0, 0xc12e, 0x72ff, 0xc12e, 0x21, 0 - .dw 0x7340, 0xc12e, 0x737f, 0xc12e, 0x21, 0 - .dw 0x73c0, 0xc12e, 0x73ff, 0xc12e, 0x21, 0 - .dw 0x7440, 0xc12e, 0x747f, 0xc12e, 0x21, 0 - .dw 0x74c0, 0xc12e, 0x74ff, 0xc12e, 0x21, 0 - .dw 0x7540, 0xc12e, 0x757f, 0xc12e, 0x21, 0 - .dw 0x75c0, 0xc12e, 0x75ff, 0xc12e, 0x21, 0 - .dw 0x7640, 0xc12e, 0x767f, 0xc12e, 0x21, 0 - .dw 0x76c0, 0xc12e, 0x76ff, 0xc12e, 0x21, 0 - .dw 0x7740, 0xc12e, 0x777f, 0xc12e, 0x21, 0 - .dw 0x77c0, 0xc12e, 0x77ff, 0xc12e, 0x21, 0 - .dw 0x7840, 0xc12e, 0x787f, 0xc12e, 0x21, 0 - .dw 0x78c0, 0xc12e, 0x78ff, 0xc12e, 0x21, 0 - .dw 0x7940, 0xc12e, 0x797f, 0xc12e, 0x21, 0 - .dw 0x79c0, 0xc12e, 0x7fff, 0xc12e, 0x21, 0 - .dw 0x8040, 0xc12e, 0x807f, 0xc12e, 0x21, 0 - .dw 0x80c0, 0xc12e, 0x80ff, 0xc12e, 0x21, 0 - .dw 0x8140, 0xc12e, 0x817f, 0xc12e, 0x21, 0 - .dw 0x81c0, 0xc12e, 0x81ff, 0xc12e, 0x21, 0 - .dw 0x8240, 0xc12e, 0x827f, 0xc12e, 0x21, 0 - .dw 0x82c0, 0xc12e, 0x82ff, 0xc12e, 0x21, 0 - .dw 0x8340, 0xc12e, 0x837f, 0xc12e, 0x21, 0 - .dw 0x83c0, 0xc12e, 0x83ff, 0xc12e, 0x21, 0 - .dw 0x8440, 0xc12e, 0x847f, 0xc12e, 0x21, 0 - .dw 0x84c0, 0xc12e, 0x84ff, 0xc12e, 0x21, 0 - .dw 0x8540, 0xc12e, 0x857f, 0xc12e, 0x21, 0 - .dw 0x85c0, 0xc12e, 0x85ff, 0xc12e, 0x21, 0 - .dw 0x8640, 0xc12e, 0x867f, 0xc12e, 0x21, 0 - .dw 0x86c0, 0xc12e, 0x86ff, 0xc12e, 0x21, 0 - .dw 0x8740, 0xc12e, 0x877f, 0xc12e, 0x21, 0 - .dw 0x87c0, 0xc12e, 0x87ff, 0xc12e, 0x21, 0 - .dw 0x8840, 0xc12e, 0x887f, 0xc12e, 0x21, 0 - .dw 0x88c0, 0xc12e, 0x88ff, 0xc12e, 0x21, 0 - .dw 0x8940, 0xc12e, 0x897f, 0xc12e, 0x21, 0 - .dw 0x89c0, 0xc12e, 0x89ff, 0xc12e, 0x21, 0 - .dw 0x8a40, 0xc12e, 0x8a7f, 0xc12e, 0x21, 0 - .dw 0x8ac0, 0xc12e, 0x8aff, 0xc12e, 0x21, 0 - .dw 0x8b40, 0xc12e, 0x8b7f, 0xc12e, 0x21, 0 - .dw 0x8bc0, 0xc12e, 0x8bff, 0xc12e, 0x21, 0 - .dw 0x8c40, 0xc12e, 0x8c7f, 0xc12e, 0x21, 0 - .dw 0x8cc0, 0xc12e, 0x8cff, 0xc12e, 0x21, 0 - .dw 0x8d40, 0xc12e, 0x8d7f, 0xc12e, 0x21, 0 - .dw 0x8dc0, 0xc12e, 0x8dff, 0xc12e, 0x21, 0 - .dw 0x8e40, 0xc12e, 0x8e7f, 0xc12e, 0x21, 0 - .dw 0x8ec0, 0xc12e, 0x8eff, 0xc12e, 0x21, 0 - .dw 0x8f40, 0xc12e, 0x8f7f, 0xc12e, 0x21, 0 - .dw 0x8fc0, 0xc12e, 0x8fff, 0xc12e, 0x21, 0 - .dw 0x9040, 0xc12e, 0x907f, 0xc12e, 0x21, 0 - .dw 0x90c0, 0xc12e, 0x90ff, 0xc12e, 0x21, 0 - .dw 0x9140, 0xc12e, 0x917f, 0xc12e, 0x21, 0 - .dw 0x91c0, 0xc12e, 0x91ff, 0xc12e, 0x21, 0 - .dw 0x9240, 0xc12e, 0x927f, 0xc12e, 0x21, 0 - .dw 0x92c0, 0xc12e, 0x92ff, 0xc12e, 0x21, 0 - .dw 0x9340, 0xc12e, 0x937f, 0xc12e, 0x21, 0 - .dw 0x93c0, 0xc12e, 0x93ff, 0xc12e, 0x21, 0 - .dw 0x9440, 0xc12e, 0x947f, 0xc12e, 0x21, 0 - .dw 0x94c0, 0xc12e, 0x94ff, 0xc12e, 0x21, 0 - .dw 0x9540, 0xc12e, 0x957f, 0xc12e, 0x21, 0 - .dw 0x95c0, 0xc12e, 0x95ff, 0xc12e, 0x21, 0 - .dw 0x9640, 0xc12e, 0x967f, 0xc12e, 0x21, 0 - .dw 0x96c0, 0xc12e, 0x96ff, 0xc12e, 0x21, 0 - .dw 0x9740, 0xc12e, 0x977f, 0xc12e, 0x21, 0 - .dw 0x97c0, 0xc12e, 0x97ff, 0xc12e, 0x21, 0 - .dw 0x9840, 0xc12e, 0x987f, 0xc12e, 0x21, 0 - .dw 0x98c0, 0xc12e, 0x98ff, 0xc12e, 0x21, 0 - .dw 0x9940, 0xc12e, 0x997f, 0xc12e, 0x21, 0 - .dw 0x99c0, 0xc12e, 0x9fff, 0xc12e, 0x21, 0 - .dw 0xa040, 0xc12e, 0xa07f, 0xc12e, 0x21, 0 - .dw 0xa0c0, 0xc12e, 0xa0ff, 0xc12e, 0x21, 0 - .dw 0xa140, 0xc12e, 0xa17f, 0xc12e, 0x21, 0 - .dw 0xa1c0, 0xc12e, 0xa1ff, 0xc12e, 0x21, 0 - .dw 0xa240, 0xc12e, 0xa27f, 0xc12e, 0x21, 0 - .dw 0xa2c0, 0xc12e, 0xa2ff, 0xc12e, 0x21, 0 - .dw 0xa340, 0xc12e, 0xa37f, 0xc12e, 0x21, 0 - .dw 0xa3c0, 0xc12e, 0xa3ff, 0xc12e, 0x21, 0 - .dw 0xa440, 0xc12e, 0xa47f, 0xc12e, 0x21, 0 - .dw 0xa4c0, 0xc12e, 0xa4ff, 0xc12e, 0x21, 0 - .dw 0xa540, 0xc12e, 0xa57f, 0xc12e, 0x21, 0 - .dw 0xa5c0, 0xc12e, 0xa5ff, 0xc12e, 0x21, 0 - .dw 0xa640, 0xc12e, 0xa67f, 0xc12e, 0x21, 0 - .dw 0xa6c0, 0xc12e, 0xa6ff, 0xc12e, 0x21, 0 - .dw 0xa740, 0xc12e, 0xa77f, 0xc12e, 0x21, 0 - .dw 0xa7c0, 0xc12e, 0xa7ff, 0xc12e, 0x21, 0 - .dw 0xa840, 0xc12e, 0xa87f, 0xc12e, 0x21, 0 - .dw 0xa8c0, 0xc12e, 0xa8ff, 0xc12e, 0x21, 0 - .dw 0xa940, 0xc12e, 0xa97f, 0xc12e, 0x21, 0 - .dw 0xa9c0, 0xc12e, 0xa9ff, 0xc12e, 0x21, 0 - .dw 0xaa40, 0xc12e, 0xaa7f, 0xc12e, 0x21, 0 - .dw 0xaac0, 0xc12e, 0xaaff, 0xc12e, 0x21, 0 - .dw 0xab40, 0xc12e, 0xab7f, 0xc12e, 0x21, 0 - .dw 0xabc0, 0xc12e, 0xabff, 0xc12e, 0x21, 0 - .dw 0xac40, 0xc12e, 0xac7f, 0xc12e, 0x21, 0 - .dw 0xacc0, 0xc12e, 0xacff, 0xc12e, 0x21, 0 - .dw 0xad40, 0xc12e, 0xad7f, 0xc12e, 0x21, 0 - .dw 0xadc0, 0xc12e, 0xadff, 0xc12e, 0x21, 0 - .dw 0xae40, 0xc12e, 0xae7f, 0xc12e, 0x21, 0 - .dw 0xaec0, 0xc12e, 0xaeff, 0xc12e, 0x21, 0 - .dw 0xaf40, 0xc12e, 0xaf7f, 0xc12e, 0x21, 0 - .dw 0xafc0, 0xc12e, 0xafff, 0xc12e, 0x21, 0 - .dw 0xb040, 0xc12e, 0xb07f, 0xc12e, 0x21, 0 - .dw 0xb0c0, 0xc12e, 0xb0ff, 0xc12e, 0x21, 0 - .dw 0xb140, 0xc12e, 0xb17f, 0xc12e, 0x21, 0 - .dw 0xb1c0, 0xc12e, 0xb1ff, 0xc12e, 0x21, 0 - .dw 0xb240, 0xc12e, 0xb27f, 0xc12e, 0x21, 0 - .dw 0xb2c0, 0xc12e, 0xb2ff, 0xc12e, 0x21, 0 - .dw 0xb340, 0xc12e, 0xb37f, 0xc12e, 0x21, 0 - .dw 0xb3c0, 0xc12e, 0xb3ff, 0xc12e, 0x21, 0 - .dw 0xb440, 0xc12e, 0xb47f, 0xc12e, 0x21, 0 - .dw 0xb4c0, 0xc12e, 0xb4ff, 0xc12e, 0x21, 0 - .dw 0xb540, 0xc12e, 0xb57f, 0xc12e, 0x21, 0 - .dw 0xb5c0, 0xc12e, 0xb5ff, 0xc12e, 0x21, 0 - .dw 0xb640, 0xc12e, 0xb67f, 0xc12e, 0x21, 0 - .dw 0xb6c0, 0xc12e, 0xb6ff, 0xc12e, 0x21, 0 - .dw 0xb740, 0xc12e, 0xb77f, 0xc12e, 0x21, 0 - .dw 0xb7c0, 0xc12e, 0xb7ff, 0xc12e, 0x21, 0 - .dw 0xb840, 0xc12e, 0xb87f, 0xc12e, 0x21, 0 - .dw 0xb8c0, 0xc12e, 0xb8ff, 0xc12e, 0x21, 0 - .dw 0xb940, 0xc12e, 0xb97f, 0xc12e, 0x21, 0 - .dw 0xb9c0, 0xc12e, 0xbfff, 0xc12e, 0x21, 0 - .dw 0xc040, 0xc12e, 0xc07f, 0xc12e, 0x21, 0 - .dw 0xc0c0, 0xc12e, 0xc0ff, 0xc12e, 0x21, 0 - .dw 0xc140, 0xc12e, 0xc17f, 0xc12e, 0x21, 0 - .dw 0xc1c0, 0xc12e, 0xc1ff, 0xc12e, 0x21, 0 - .dw 0xc240, 0xc12e, 0xc27f, 0xc12e, 0x21, 0 - .dw 0xc2c0, 0xc12e, 0xc2ff, 0xc12e, 0x21, 0 - .dw 0xc340, 0xc12e, 0xc37f, 0xc12e, 0x21, 0 - .dw 0xc3c0, 0xc12e, 0xc3ff, 0xc12e, 0x21, 0 - .dw 0xc440, 0xc12e, 0xc47f, 0xc12e, 0x21, 0 - .dw 0xc4c0, 0xc12e, 0xc4ff, 0xc12e, 0x21, 0 - .dw 0xc540, 0xc12e, 0xc57f, 0xc12e, 0x21, 0 - .dw 0xc5c0, 0xc12e, 0xc5ff, 0xc12e, 0x21, 0 - .dw 0xc640, 0xc12e, 0xc67f, 0xc12e, 0x21, 0 - .dw 0xc6c0, 0xc12e, 0xc6ff, 0xc12e, 0x21, 0 - .dw 0xc740, 0xc12e, 0xc77f, 0xc12e, 0x21, 0 - .dw 0xc7c0, 0xc12e, 0xc7ff, 0xc12e, 0x21, 0 - .dw 0xc840, 0xc12e, 0xc87f, 0xc12e, 0x21, 0 - .dw 0xc8c0, 0xc12e, 0xc8ff, 0xc12e, 0x21, 0 - .dw 0xc940, 0xc12e, 0xc97f, 0xc12e, 0x21, 0 - .dw 0xc9c0, 0xc12e, 0xc9ff, 0xc12e, 0x21, 0 - .dw 0xca40, 0xc12e, 0xca7f, 0xc12e, 0x21, 0 - .dw 0xcac0, 0xc12e, 0xcaff, 0xc12e, 0x21, 0 - .dw 0xcb40, 0xc12e, 0xcb7f, 0xc12e, 0x21, 0 - .dw 0xcbc0, 0xc12e, 0xcbff, 0xc12e, 0x21, 0 - .dw 0xcc40, 0xc12e, 0xcc7f, 0xc12e, 0x21, 0 - .dw 0xccc0, 0xc12e, 0xccff, 0xc12e, 0x21, 0 - .dw 0xcd40, 0xc12e, 0xcd7f, 0xc12e, 0x21, 0 - .dw 0xcdc0, 0xc12e, 0xcdff, 0xc12e, 0x21, 0 - .dw 0xce40, 0xc12e, 0xce7f, 0xc12e, 0x21, 0 - .dw 0xcec0, 0xc12e, 0xceff, 0xc12e, 0x21, 0 - .dw 0xcf40, 0xc12e, 0xcf7f, 0xc12e, 0x21, 0 - .dw 0xcfc0, 0xc12e, 0xcfff, 0xc12e, 0x21, 0 - .dw 0xd040, 0xc12e, 0xd07f, 0xc12e, 0x21, 0 - .dw 0xd0c0, 0xc12e, 0xd0ff, 0xc12e, 0x21, 0 - .dw 0xd140, 0xc12e, 0xd17f, 0xc12e, 0x21, 0 - .dw 0xd1c0, 0xc12e, 0xd1ff, 0xc12e, 0x21, 0 - .dw 0xd240, 0xc12e, 0xd27f, 0xc12e, 0x21, 0 - .dw 0xd2c0, 0xc12e, 0xd2ff, 0xc12e, 0x21, 0 - .dw 0xd340, 0xc12e, 0xd37f, 0xc12e, 0x21, 0 - .dw 0xd3c0, 0xc12e, 0xd3ff, 0xc12e, 0x21, 0 - .dw 0xd440, 0xc12e, 0xd47f, 0xc12e, 0x21, 0 - .dw 0xd4c0, 0xc12e, 0xd4ff, 0xc12e, 0x21, 0 - .dw 0xd540, 0xc12e, 0xd57f, 0xc12e, 0x21, 0 - .dw 0xd5c0, 0xc12e, 0xd5ff, 0xc12e, 0x21, 0 - .dw 0xd640, 0xc12e, 0xd67f, 0xc12e, 0x21, 0 - .dw 0xd6c0, 0xc12e, 0xd6ff, 0xc12e, 0x21, 0 - .dw 0xd740, 0xc12e, 0xd77f, 0xc12e, 0x21, 0 - .dw 0xd7c0, 0xc12e, 0xd7ff, 0xc12e, 0x21, 0 - .dw 0xd840, 0xc12e, 0xd87f, 0xc12e, 0x21, 0 - .dw 0xd8c0, 0xc12e, 0xd8ff, 0xc12e, 0x21, 0 - .dw 0xd940, 0xc12e, 0xd97f, 0xc12e, 0x21, 0 - .dw 0xd9c0, 0xc12e, 0xdfff, 0xc12e, 0x21, 0 - .dw 0xe040, 0xc12e, 0xe07f, 0xc12e, 0x21, 0 - .dw 0xe0c0, 0xc12e, 0xe0ff, 0xc12e, 0x21, 0 - .dw 0xe140, 0xc12e, 0xe17f, 0xc12e, 0x21, 0 - .dw 0xe1c0, 0xc12e, 0xe1ff, 0xc12e, 0x21, 0 - .dw 0xe240, 0xc12e, 0xe27f, 0xc12e, 0x21, 0 - .dw 0xe2c0, 0xc12e, 0xe2ff, 0xc12e, 0x21, 0 - .dw 0xe340, 0xc12e, 0xe37f, 0xc12e, 0x21, 0 - .dw 0xe3c0, 0xc12e, 0xe3ff, 0xc12e, 0x21, 0 - .dw 0xe440, 0xc12e, 0xe47f, 0xc12e, 0x21, 0 - .dw 0xe4c0, 0xc12e, 0xe4ff, 0xc12e, 0x21, 0 - .dw 0xe540, 0xc12e, 0xe57f, 0xc12e, 0x21, 0 - .dw 0xe5c0, 0xc12e, 0xe5ff, 0xc12e, 0x21, 0 - .dw 0xe640, 0xc12e, 0xe67f, 0xc12e, 0x21, 0 - .dw 0xe6c0, 0xc12e, 0xe6ff, 0xc12e, 0x21, 0 - .dw 0xe740, 0xc12e, 0xe77f, 0xc12e, 0x21, 0 - .dw 0xe7c0, 0xc12e, 0xe7ff, 0xc12e, 0x21, 0 - .dw 0xe840, 0xc12e, 0xe87f, 0xc12e, 0x21, 0 - .dw 0xe8c0, 0xc12e, 0xe8ff, 0xc12e, 0x21, 0 - .dw 0xe940, 0xc12e, 0xe97f, 0xc12e, 0x21, 0 - .dw 0xe9c0, 0xc12e, 0xe9ff, 0xc12e, 0x21, 0 - .dw 0xea40, 0xc12e, 0xea7f, 0xc12e, 0x21, 0 - .dw 0xeac0, 0xc12e, 0xeaff, 0xc12e, 0x21, 0 - .dw 0xeb40, 0xc12e, 0xeb7f, 0xc12e, 0x21, 0 - .dw 0xebc0, 0xc12e, 0xebff, 0xc12e, 0x21, 0 - .dw 0xec40, 0xc12e, 0xec7f, 0xc12e, 0x21, 0 - .dw 0xecc0, 0xc12e, 0xecff, 0xc12e, 0x21, 0 - .dw 0xed40, 0xc12e, 0xed7f, 0xc12e, 0x21, 0 - .dw 0xedc0, 0xc12e, 0xedff, 0xc12e, 0x21, 0 - .dw 0xee40, 0xc12e, 0xee7f, 0xc12e, 0x21, 0 - .dw 0xeec0, 0xc12e, 0xeeff, 0xc12e, 0x21, 0 - .dw 0xef40, 0xc12e, 0xef7f, 0xc12e, 0x21, 0 - .dw 0xefc0, 0xc12e, 0xefff, 0xc12e, 0x21, 0 - .dw 0xf040, 0xc12e, 0xf07f, 0xc12e, 0x21, 0 - .dw 0xf0c0, 0xc12e, 0xf0ff, 0xc12e, 0x21, 0 - .dw 0xf140, 0xc12e, 0xf17f, 0xc12e, 0x21, 0 - .dw 0xf1c0, 0xc12e, 0xf1ff, 0xc12e, 0x21, 0 - .dw 0xf240, 0xc12e, 0xf27f, 0xc12e, 0x21, 0 - .dw 0xf2c0, 0xc12e, 0xf2ff, 0xc12e, 0x21, 0 - .dw 0xf340, 0xc12e, 0xf37f, 0xc12e, 0x21, 0 - .dw 0xf3c0, 0xc12e, 0xf3ff, 0xc12e, 0x21, 0 - .dw 0xf440, 0xc12e, 0xf47f, 0xc12e, 0x21, 0 - .dw 0xf4c0, 0xc12e, 0xf4ff, 0xc12e, 0x21, 0 - .dw 0xf540, 0xc12e, 0xf57f, 0xc12e, 0x21, 0 - .dw 0xf5c0, 0xc12e, 0xf5ff, 0xc12e, 0x21, 0 - .dw 0xf640, 0xc12e, 0xf67f, 0xc12e, 0x21, 0 - .dw 0xf6c0, 0xc12e, 0xf6ff, 0xc12e, 0x21, 0 - .dw 0xf740, 0xc12e, 0xf77f, 0xc12e, 0x21, 0 - .dw 0xf7c0, 0xc12e, 0xf7ff, 0xc12e, 0x21, 0 - .dw 0xf840, 0xc12e, 0xf87f, 0xc12e, 0x21, 0 - .dw 0xf8c0, 0xc12e, 0xf8ff, 0xc12e, 0x21, 0 - .dw 0xf940, 0xc12e, 0xf97f, 0xc12e, 0x21, 0 - .dw 0xf9c0, 0xc12e, 0xffff, 0xc12e, 0x21, 0 - .dw 0x0040, 0xc12f, 0x007f, 0xc12f, 0x21, 0 - .dw 0x00c0, 0xc12f, 0x00ff, 0xc12f, 0x21, 0 - .dw 0x0140, 0xc12f, 0x017f, 0xc12f, 0x21, 0 - .dw 0x01c0, 0xc12f, 0x01ff, 0xc12f, 0x21, 0 - .dw 0x0240, 0xc12f, 0x027f, 0xc12f, 0x21, 0 - .dw 0x02c0, 0xc12f, 0x02ff, 0xc12f, 0x21, 0 - .dw 0x0340, 0xc12f, 0x037f, 0xc12f, 0x21, 0 - .dw 0x03c0, 0xc12f, 0x03ff, 0xc12f, 0x21, 0 - .dw 0x0440, 0xc12f, 0x047f, 0xc12f, 0x21, 0 - .dw 0x04c0, 0xc12f, 0x04ff, 0xc12f, 0x21, 0 - .dw 0x0540, 0xc12f, 0x057f, 0xc12f, 0x21, 0 - .dw 0x05c0, 0xc12f, 0x05ff, 0xc12f, 0x21, 0 - .dw 0x0640, 0xc12f, 0x067f, 0xc12f, 0x21, 0 - .dw 0x06c0, 0xc12f, 0x06ff, 0xc12f, 0x21, 0 - .dw 0x0740, 0xc12f, 0x077f, 0xc12f, 0x21, 0 - .dw 0x07c0, 0xc12f, 0x07ff, 0xc12f, 0x21, 0 - .dw 0x0840, 0xc12f, 0x087f, 0xc12f, 0x21, 0 - .dw 0x08c0, 0xc12f, 0x08ff, 0xc12f, 0x21, 0 - .dw 0x0940, 0xc12f, 0x097f, 0xc12f, 0x21, 0 - .dw 0x09c0, 0xc12f, 0x09ff, 0xc12f, 0x21, 0 - .dw 0x0a40, 0xc12f, 0x0a7f, 0xc12f, 0x21, 0 - .dw 0x0ac0, 0xc12f, 0x0aff, 0xc12f, 0x21, 0 - .dw 0x0b40, 0xc12f, 0x0b7f, 0xc12f, 0x21, 0 - .dw 0x0bc0, 0xc12f, 0x0bff, 0xc12f, 0x21, 0 - .dw 0x0c40, 0xc12f, 0x0c7f, 0xc12f, 0x21, 0 - .dw 0x0cc0, 0xc12f, 0x0cff, 0xc12f, 0x21, 0 - .dw 0x0d40, 0xc12f, 0x0d7f, 0xc12f, 0x21, 0 - .dw 0x0dc0, 0xc12f, 0x0dff, 0xc12f, 0x21, 0 - .dw 0x0e40, 0xc12f, 0x0e7f, 0xc12f, 0x21, 0 - .dw 0x0ec0, 0xc12f, 0x0eff, 0xc12f, 0x21, 0 - .dw 0x0f40, 0xc12f, 0x0f7f, 0xc12f, 0x21, 0 - .dw 0x0fc0, 0xc12f, 0x0fff, 0xc12f, 0x21, 0 - .dw 0x1040, 0xc12f, 0x107f, 0xc12f, 0x21, 0 - .dw 0x10c0, 0xc12f, 0x10ff, 0xc12f, 0x21, 0 - .dw 0x1140, 0xc12f, 0x117f, 0xc12f, 0x21, 0 - .dw 0x11c0, 0xc12f, 0x11ff, 0xc12f, 0x21, 0 - .dw 0x1240, 0xc12f, 0x127f, 0xc12f, 0x21, 0 - .dw 0x12c0, 0xc12f, 0x12ff, 0xc12f, 0x21, 0 - .dw 0x1340, 0xc12f, 0x137f, 0xc12f, 0x21, 0 - .dw 0x13c0, 0xc12f, 0x13ff, 0xc12f, 0x21, 0 - .dw 0x1440, 0xc12f, 0x147f, 0xc12f, 0x21, 0 - .dw 0x14c0, 0xc12f, 0x14ff, 0xc12f, 0x21, 0 - .dw 0x1540, 0xc12f, 0x157f, 0xc12f, 0x21, 0 - .dw 0x15c0, 0xc12f, 0x15ff, 0xc12f, 0x21, 0 - .dw 0x1640, 0xc12f, 0x167f, 0xc12f, 0x21, 0 - .dw 0x16c0, 0xc12f, 0x16ff, 0xc12f, 0x21, 0 - .dw 0x1740, 0xc12f, 0x177f, 0xc12f, 0x21, 0 - .dw 0x17c0, 0xc12f, 0x17ff, 0xc12f, 0x21, 0 - .dw 0x1840, 0xc12f, 0x187f, 0xc12f, 0x21, 0 - .dw 0x18c0, 0xc12f, 0x18ff, 0xc12f, 0x21, 0 - .dw 0x1940, 0xc12f, 0x197f, 0xc12f, 0x21, 0 - .dw 0x19c0, 0xc12f, 0x1fff, 0xc12f, 0x21, 0 - .dw 0x2040, 0xc12f, 0x207f, 0xc12f, 0x21, 0 - .dw 0x20c0, 0xc12f, 0x20ff, 0xc12f, 0x21, 0 - .dw 0x2140, 0xc12f, 0x217f, 0xc12f, 0x21, 0 - .dw 0x21c0, 0xc12f, 0x21ff, 0xc12f, 0x21, 0 - .dw 0x2240, 0xc12f, 0x227f, 0xc12f, 0x21, 0 - .dw 0x22c0, 0xc12f, 0x22ff, 0xc12f, 0x21, 0 - .dw 0x2340, 0xc12f, 0x237f, 0xc12f, 0x21, 0 - .dw 0x23c0, 0xc12f, 0x23ff, 0xc12f, 0x21, 0 - .dw 0x2440, 0xc12f, 0x247f, 0xc12f, 0x21, 0 - .dw 0x24c0, 0xc12f, 0x24ff, 0xc12f, 0x21, 0 - .dw 0x2540, 0xc12f, 0x257f, 0xc12f, 0x21, 0 - .dw 0x25c0, 0xc12f, 0x25ff, 0xc12f, 0x21, 0 - .dw 0x2640, 0xc12f, 0x267f, 0xc12f, 0x21, 0 - .dw 0x26c0, 0xc12f, 0x26ff, 0xc12f, 0x21, 0 - .dw 0x2740, 0xc12f, 0x277f, 0xc12f, 0x21, 0 - .dw 0x27c0, 0xc12f, 0x27ff, 0xc12f, 0x21, 0 - .dw 0x2840, 0xc12f, 0x287f, 0xc12f, 0x21, 0 - .dw 0x28c0, 0xc12f, 0x28ff, 0xc12f, 0x21, 0 - .dw 0x2940, 0xc12f, 0x297f, 0xc12f, 0x21, 0 - .dw 0x29c0, 0xc12f, 0x29ff, 0xc12f, 0x21, 0 - .dw 0x2a40, 0xc12f, 0x2a7f, 0xc12f, 0x21, 0 - .dw 0x2ac0, 0xc12f, 0x2aff, 0xc12f, 0x21, 0 - .dw 0x2b40, 0xc12f, 0x2b7f, 0xc12f, 0x21, 0 - .dw 0x2bc0, 0xc12f, 0x2bff, 0xc12f, 0x21, 0 - .dw 0x2c40, 0xc12f, 0x2c7f, 0xc12f, 0x21, 0 - .dw 0x2cc0, 0xc12f, 0x2cff, 0xc12f, 0x21, 0 - .dw 0x2d40, 0xc12f, 0x2d7f, 0xc12f, 0x21, 0 - .dw 0x2dc0, 0xc12f, 0x2dff, 0xc12f, 0x21, 0 - .dw 0x2e40, 0xc12f, 0x2e7f, 0xc12f, 0x21, 0 - .dw 0x2ec0, 0xc12f, 0x2eff, 0xc12f, 0x21, 0 - .dw 0x2f40, 0xc12f, 0x2f7f, 0xc12f, 0x21, 0 - .dw 0x2fc0, 0xc12f, 0x2fff, 0xc12f, 0x21, 0 - .dw 0x3040, 0xc12f, 0x307f, 0xc12f, 0x21, 0 - .dw 0x30c0, 0xc12f, 0x30ff, 0xc12f, 0x21, 0 - .dw 0x3140, 0xc12f, 0x317f, 0xc12f, 0x21, 0 - .dw 0x31c0, 0xc12f, 0x31ff, 0xc12f, 0x21, 0 - .dw 0x3240, 0xc12f, 0x327f, 0xc12f, 0x21, 0 - .dw 0x32c0, 0xc12f, 0x32ff, 0xc12f, 0x21, 0 - .dw 0x3340, 0xc12f, 0x337f, 0xc12f, 0x21, 0 - .dw 0x33c0, 0xc12f, 0x33ff, 0xc12f, 0x21, 0 - .dw 0x3440, 0xc12f, 0x347f, 0xc12f, 0x21, 0 - .dw 0x34c0, 0xc12f, 0x34ff, 0xc12f, 0x21, 0 - .dw 0x3540, 0xc12f, 0x357f, 0xc12f, 0x21, 0 - .dw 0x35c0, 0xc12f, 0x35ff, 0xc12f, 0x21, 0 - .dw 0x3640, 0xc12f, 0x367f, 0xc12f, 0x21, 0 - .dw 0x36c0, 0xc12f, 0x36ff, 0xc12f, 0x21, 0 - .dw 0x3740, 0xc12f, 0x377f, 0xc12f, 0x21, 0 - .dw 0x37c0, 0xc12f, 0x37ff, 0xc12f, 0x21, 0 - .dw 0x3840, 0xc12f, 0x387f, 0xc12f, 0x21, 0 - .dw 0x38c0, 0xc12f, 0x38ff, 0xc12f, 0x21, 0 - .dw 0x3940, 0xc12f, 0x397f, 0xc12f, 0x21, 0 - .dw 0x39c0, 0xc12f, 0x1fff, 0xc130, 0x21, 0 - .dw 0x3a00, 0xc130, 0x5fff, 0xc130, 0x21, 0 - .dw 0x7a00, 0xc130, 0x9fff, 0xc130, 0x21, 0 - .dw 0xba00, 0xc130, 0xdfff, 0xc130, 0x21, 0 - .dw 0xfa00, 0xc130, 0x1fff, 0xc131, 0x21, 0 - .dw 0x3a00, 0xc131, 0x5fff, 0xc131, 0x21, 0 - .dw 0x7a00, 0xc131, 0x9fff, 0xc131, 0x21, 0 - .dw 0xba00, 0xc131, 0xdfff, 0xc131, 0x21, 0 - .dw 0xfa00, 0xc131, 0x1fff, 0xc132, 0x21, 0 - .dw 0x3a00, 0xc132, 0x5fff, 0xc132, 0x21, 0 - .dw 0x7a00, 0xc132, 0x9fff, 0xc132, 0x21, 0 - .dw 0xba00, 0xc132, 0xdfff, 0xc132, 0x21, 0 - .dw 0xfa00, 0xc132, 0xffff, 0xc133, 0x21, 0 - .dw 0x1a00, 0xc134, 0x1fff, 0xc134, 0x21, 0 - .dw 0x3a00, 0xc134, 0x3fff, 0xc134, 0x21, 0 - .dw 0x5a00, 0xc134, 0x5fff, 0xc134, 0x21, 0 - .dw 0x7a00, 0xc134, 0x7fff, 0xc134, 0x21, 0 - .dw 0x9a00, 0xc134, 0x9fff, 0xc134, 0x21, 0 - .dw 0xba00, 0xc134, 0xbfff, 0xc134, 0x21, 0 - .dw 0xda00, 0xc134, 0xdfff, 0xc134, 0x21, 0 - .dw 0xfa00, 0xc134, 0xffff, 0xc134, 0x21, 0 - .dw 0x1a00, 0xc135, 0x1fff, 0xc135, 0x21, 0 - .dw 0x3a00, 0xc135, 0x3fff, 0xc135, 0x21, 0 - .dw 0x5a00, 0xc135, 0x5fff, 0xc135, 0x21, 0 - .dw 0x7a00, 0xc135, 0x7fff, 0xc135, 0x21, 0 - .dw 0x9a00, 0xc135, 0x9fff, 0xc135, 0x21, 0 - .dw 0xba00, 0xc135, 0xbfff, 0xc135, 0x21, 0 - .dw 0xda00, 0xc135, 0xdfff, 0xc135, 0x21, 0 - .dw 0xfa00, 0xc135, 0xffff, 0xc135, 0x21, 0 - .dw 0x1a00, 0xc136, 0x1fff, 0xc136, 0x21, 0 - .dw 0x3a00, 0xc136, 0x3fff, 0xc136, 0x21, 0 - .dw 0x5a00, 0xc136, 0x5fff, 0xc136, 0x21, 0 - .dw 0x7a00, 0xc136, 0x7fff, 0xc136, 0x21, 0 - .dw 0x9a00, 0xc136, 0x9fff, 0xc136, 0x21, 0 - .dw 0xba00, 0xc136, 0xbfff, 0xc136, 0x21, 0 - .dw 0xda00, 0xc136, 0xdfff, 0xc136, 0x21, 0 - .dw 0xfa00, 0xc136, 0xffff, 0xc136, 0x21, 0 - .dw 0x1a00, 0xc137, 0x1fff, 0xc137, 0x21, 0 - .dw 0x3a00, 0xc137, 0x1fff, 0xc138, 0x21, 0 - .dw 0x2040, 0xc138, 0x207f, 0xc138, 0x21, 0 - .dw 0x20c0, 0xc138, 0x20ff, 0xc138, 0x21, 0 - .dw 0x2140, 0xc138, 0x217f, 0xc138, 0x21, 0 - .dw 0x21c0, 0xc138, 0x21ff, 0xc138, 0x21, 0 - .dw 0x2240, 0xc138, 0x227f, 0xc138, 0x21, 0 - .dw 0x22c0, 0xc138, 0x22ff, 0xc138, 0x21, 0 - .dw 0x2340, 0xc138, 0x237f, 0xc138, 0x21, 0 - .dw 0x23c0, 0xc138, 0x23ff, 0xc138, 0x21, 0 - .dw 0x2440, 0xc138, 0x247f, 0xc138, 0x21, 0 - .dw 0x24c0, 0xc138, 0x24ff, 0xc138, 0x21, 0 - .dw 0x2540, 0xc138, 0x257f, 0xc138, 0x21, 0 - .dw 0x25c0, 0xc138, 0x25ff, 0xc138, 0x21, 0 - .dw 0x2640, 0xc138, 0x267f, 0xc138, 0x21, 0 - .dw 0x26c0, 0xc138, 0x26ff, 0xc138, 0x21, 0 - .dw 0x2740, 0xc138, 0x277f, 0xc138, 0x21, 0 - .dw 0x27c0, 0xc138, 0x27ff, 0xc138, 0x21, 0 - .dw 0x2840, 0xc138, 0x287f, 0xc138, 0x21, 0 - .dw 0x28c0, 0xc138, 0x28ff, 0xc138, 0x21, 0 - .dw 0x2940, 0xc138, 0x297f, 0xc138, 0x21, 0 - .dw 0x29c0, 0xc138, 0x29ff, 0xc138, 0x21, 0 - .dw 0x2a40, 0xc138, 0x2a7f, 0xc138, 0x21, 0 - .dw 0x2ac0, 0xc138, 0x2aff, 0xc138, 0x21, 0 - .dw 0x2b40, 0xc138, 0x2b7f, 0xc138, 0x21, 0 - .dw 0x2bc0, 0xc138, 0x2bff, 0xc138, 0x21, 0 - .dw 0x2c40, 0xc138, 0x2c7f, 0xc138, 0x21, 0 - .dw 0x2cc0, 0xc138, 0x2cff, 0xc138, 0x21, 0 - .dw 0x2d40, 0xc138, 0x2d7f, 0xc138, 0x21, 0 - .dw 0x2dc0, 0xc138, 0x2dff, 0xc138, 0x21, 0 - .dw 0x2e40, 0xc138, 0x2e7f, 0xc138, 0x21, 0 - .dw 0x2ec0, 0xc138, 0x2eff, 0xc138, 0x21, 0 - .dw 0x2f40, 0xc138, 0x2f7f, 0xc138, 0x21, 0 - .dw 0x2fc0, 0xc138, 0x2fff, 0xc138, 0x21, 0 - .dw 0x3040, 0xc138, 0x307f, 0xc138, 0x21, 0 - .dw 0x30c0, 0xc138, 0x30ff, 0xc138, 0x21, 0 - .dw 0x3140, 0xc138, 0x317f, 0xc138, 0x21, 0 - .dw 0x31c0, 0xc138, 0x31ff, 0xc138, 0x21, 0 - .dw 0x3240, 0xc138, 0x327f, 0xc138, 0x21, 0 - .dw 0x32c0, 0xc138, 0x32ff, 0xc138, 0x21, 0 - .dw 0x3340, 0xc138, 0x337f, 0xc138, 0x21, 0 - .dw 0x33c0, 0xc138, 0x33ff, 0xc138, 0x21, 0 - .dw 0x3440, 0xc138, 0x347f, 0xc138, 0x21, 0 - .dw 0x34c0, 0xc138, 0x34ff, 0xc138, 0x21, 0 - .dw 0x3540, 0xc138, 0x357f, 0xc138, 0x21, 0 - .dw 0x35c0, 0xc138, 0x35ff, 0xc138, 0x21, 0 - .dw 0x3640, 0xc138, 0x367f, 0xc138, 0x21, 0 - .dw 0x36c0, 0xc138, 0x36ff, 0xc138, 0x21, 0 - .dw 0x3740, 0xc138, 0x377f, 0xc138, 0x21, 0 - .dw 0x37c0, 0xc138, 0x37ff, 0xc138, 0x21, 0 - .dw 0x3840, 0xc138, 0x387f, 0xc138, 0x21, 0 - .dw 0x38c0, 0xc138, 0x38ff, 0xc138, 0x21, 0 - .dw 0x3940, 0xc138, 0x397f, 0xc138, 0x21, 0 - .dw 0x39c0, 0xc138, 0x5fff, 0xc138, 0x21, 0 - .dw 0x6040, 0xc138, 0x607f, 0xc138, 0x21, 0 - .dw 0x60c0, 0xc138, 0x60ff, 0xc138, 0x21, 0 - .dw 0x6140, 0xc138, 0x617f, 0xc138, 0x21, 0 - .dw 0x61c0, 0xc138, 0x61ff, 0xc138, 0x21, 0 - .dw 0x6240, 0xc138, 0x627f, 0xc138, 0x21, 0 - .dw 0x62c0, 0xc138, 0x62ff, 0xc138, 0x21, 0 - .dw 0x6340, 0xc138, 0x637f, 0xc138, 0x21, 0 - .dw 0x63c0, 0xc138, 0x63ff, 0xc138, 0x21, 0 - .dw 0x6440, 0xc138, 0x647f, 0xc138, 0x21, 0 - .dw 0x64c0, 0xc138, 0x64ff, 0xc138, 0x21, 0 - .dw 0x6540, 0xc138, 0x657f, 0xc138, 0x21, 0 - .dw 0x65c0, 0xc138, 0x65ff, 0xc138, 0x21, 0 - .dw 0x6640, 0xc138, 0x667f, 0xc138, 0x21, 0 - .dw 0x66c0, 0xc138, 0x66ff, 0xc138, 0x21, 0 - .dw 0x6740, 0xc138, 0x677f, 0xc138, 0x21, 0 - .dw 0x67c0, 0xc138, 0x67ff, 0xc138, 0x21, 0 - .dw 0x6840, 0xc138, 0x687f, 0xc138, 0x21, 0 - .dw 0x68c0, 0xc138, 0x68ff, 0xc138, 0x21, 0 - .dw 0x6940, 0xc138, 0x697f, 0xc138, 0x21, 0 - .dw 0x69c0, 0xc138, 0x69ff, 0xc138, 0x21, 0 - .dw 0x6a40, 0xc138, 0x6a7f, 0xc138, 0x21, 0 - .dw 0x6ac0, 0xc138, 0x6aff, 0xc138, 0x21, 0 - .dw 0x6b40, 0xc138, 0x6b7f, 0xc138, 0x21, 0 - .dw 0x6bc0, 0xc138, 0x6bff, 0xc138, 0x21, 0 - .dw 0x6c40, 0xc138, 0x6c7f, 0xc138, 0x21, 0 - .dw 0x6cc0, 0xc138, 0x6cff, 0xc138, 0x21, 0 - .dw 0x6d40, 0xc138, 0x6d7f, 0xc138, 0x21, 0 - .dw 0x6dc0, 0xc138, 0x6dff, 0xc138, 0x21, 0 - .dw 0x6e40, 0xc138, 0x6e7f, 0xc138, 0x21, 0 - .dw 0x6ec0, 0xc138, 0x6eff, 0xc138, 0x21, 0 - .dw 0x6f40, 0xc138, 0x6f7f, 0xc138, 0x21, 0 - .dw 0x6fc0, 0xc138, 0x6fff, 0xc138, 0x21, 0 - .dw 0x7040, 0xc138, 0x707f, 0xc138, 0x21, 0 - .dw 0x70c0, 0xc138, 0x70ff, 0xc138, 0x21, 0 - .dw 0x7140, 0xc138, 0x717f, 0xc138, 0x21, 0 - .dw 0x71c0, 0xc138, 0x71ff, 0xc138, 0x21, 0 - .dw 0x7240, 0xc138, 0x727f, 0xc138, 0x21, 0 - .dw 0x72c0, 0xc138, 0x72ff, 0xc138, 0x21, 0 - .dw 0x7340, 0xc138, 0x737f, 0xc138, 0x21, 0 - .dw 0x73c0, 0xc138, 0x73ff, 0xc138, 0x21, 0 - .dw 0x7440, 0xc138, 0x747f, 0xc138, 0x21, 0 - .dw 0x74c0, 0xc138, 0x74ff, 0xc138, 0x21, 0 - .dw 0x7540, 0xc138, 0x757f, 0xc138, 0x21, 0 - .dw 0x75c0, 0xc138, 0x75ff, 0xc138, 0x21, 0 - .dw 0x7640, 0xc138, 0x767f, 0xc138, 0x21, 0 - .dw 0x76c0, 0xc138, 0x76ff, 0xc138, 0x21, 0 - .dw 0x7740, 0xc138, 0x777f, 0xc138, 0x21, 0 - .dw 0x77c0, 0xc138, 0x77ff, 0xc138, 0x21, 0 - .dw 0x7840, 0xc138, 0x787f, 0xc138, 0x21, 0 - .dw 0x78c0, 0xc138, 0x78ff, 0xc138, 0x21, 0 - .dw 0x7940, 0xc138, 0x797f, 0xc138, 0x21, 0 - .dw 0x79c0, 0xc138, 0x9fff, 0xc138, 0x21, 0 - .dw 0xa040, 0xc138, 0xa07f, 0xc138, 0x21, 0 - .dw 0xa0c0, 0xc138, 0xa0ff, 0xc138, 0x21, 0 - .dw 0xa140, 0xc138, 0xa17f, 0xc138, 0x21, 0 - .dw 0xa1c0, 0xc138, 0xa1ff, 0xc138, 0x21, 0 - .dw 0xa240, 0xc138, 0xa27f, 0xc138, 0x21, 0 - .dw 0xa2c0, 0xc138, 0xa2ff, 0xc138, 0x21, 0 - .dw 0xa340, 0xc138, 0xa37f, 0xc138, 0x21, 0 - .dw 0xa3c0, 0xc138, 0xa3ff, 0xc138, 0x21, 0 - .dw 0xa440, 0xc138, 0xa47f, 0xc138, 0x21, 0 - .dw 0xa4c0, 0xc138, 0xa4ff, 0xc138, 0x21, 0 - .dw 0xa540, 0xc138, 0xa57f, 0xc138, 0x21, 0 - .dw 0xa5c0, 0xc138, 0xa5ff, 0xc138, 0x21, 0 - .dw 0xa640, 0xc138, 0xa67f, 0xc138, 0x21, 0 - .dw 0xa6c0, 0xc138, 0xa6ff, 0xc138, 0x21, 0 - .dw 0xa740, 0xc138, 0xa77f, 0xc138, 0x21, 0 - .dw 0xa7c0, 0xc138, 0xa7ff, 0xc138, 0x21, 0 - .dw 0xa840, 0xc138, 0xa87f, 0xc138, 0x21, 0 - .dw 0xa8c0, 0xc138, 0xa8ff, 0xc138, 0x21, 0 - .dw 0xa940, 0xc138, 0xa97f, 0xc138, 0x21, 0 - .dw 0xa9c0, 0xc138, 0xa9ff, 0xc138, 0x21, 0 - .dw 0xaa40, 0xc138, 0xaa7f, 0xc138, 0x21, 0 - .dw 0xaac0, 0xc138, 0xaaff, 0xc138, 0x21, 0 - .dw 0xab40, 0xc138, 0xab7f, 0xc138, 0x21, 0 - .dw 0xabc0, 0xc138, 0xabff, 0xc138, 0x21, 0 - .dw 0xac40, 0xc138, 0xac7f, 0xc138, 0x21, 0 - .dw 0xacc0, 0xc138, 0xacff, 0xc138, 0x21, 0 - .dw 0xad40, 0xc138, 0xad7f, 0xc138, 0x21, 0 - .dw 0xadc0, 0xc138, 0xadff, 0xc138, 0x21, 0 - .dw 0xae40, 0xc138, 0xae7f, 0xc138, 0x21, 0 - .dw 0xaec0, 0xc138, 0xaeff, 0xc138, 0x21, 0 - .dw 0xaf40, 0xc138, 0xaf7f, 0xc138, 0x21, 0 - .dw 0xafc0, 0xc138, 0xafff, 0xc138, 0x21, 0 - .dw 0xb040, 0xc138, 0xb07f, 0xc138, 0x21, 0 - .dw 0xb0c0, 0xc138, 0xb0ff, 0xc138, 0x21, 0 - .dw 0xb140, 0xc138, 0xb17f, 0xc138, 0x21, 0 - .dw 0xb1c0, 0xc138, 0xb1ff, 0xc138, 0x21, 0 - .dw 0xb240, 0xc138, 0xb27f, 0xc138, 0x21, 0 - .dw 0xb2c0, 0xc138, 0xb2ff, 0xc138, 0x21, 0 - .dw 0xb340, 0xc138, 0xb37f, 0xc138, 0x21, 0 - .dw 0xb3c0, 0xc138, 0xb3ff, 0xc138, 0x21, 0 - .dw 0xb440, 0xc138, 0xb47f, 0xc138, 0x21, 0 - .dw 0xb4c0, 0xc138, 0xb4ff, 0xc138, 0x21, 0 - .dw 0xb540, 0xc138, 0xb57f, 0xc138, 0x21, 0 - .dw 0xb5c0, 0xc138, 0xb5ff, 0xc138, 0x21, 0 - .dw 0xb640, 0xc138, 0xb67f, 0xc138, 0x21, 0 - .dw 0xb6c0, 0xc138, 0xb6ff, 0xc138, 0x21, 0 - .dw 0xb740, 0xc138, 0xb77f, 0xc138, 0x21, 0 - .dw 0xb7c0, 0xc138, 0xb7ff, 0xc138, 0x21, 0 - .dw 0xb840, 0xc138, 0xb87f, 0xc138, 0x21, 0 - .dw 0xb8c0, 0xc138, 0xb8ff, 0xc138, 0x21, 0 - .dw 0xb940, 0xc138, 0xb97f, 0xc138, 0x21, 0 - .dw 0xb9c0, 0xc138, 0xdfff, 0xc138, 0x21, 0 - .dw 0xe040, 0xc138, 0xe07f, 0xc138, 0x21, 0 - .dw 0xe0c0, 0xc138, 0xe0ff, 0xc138, 0x21, 0 - .dw 0xe140, 0xc138, 0xe17f, 0xc138, 0x21, 0 - .dw 0xe1c0, 0xc138, 0xe1ff, 0xc138, 0x21, 0 - .dw 0xe240, 0xc138, 0xe27f, 0xc138, 0x21, 0 - .dw 0xe2c0, 0xc138, 0xe2ff, 0xc138, 0x21, 0 - .dw 0xe340, 0xc138, 0xe37f, 0xc138, 0x21, 0 - .dw 0xe3c0, 0xc138, 0xe3ff, 0xc138, 0x21, 0 - .dw 0xe440, 0xc138, 0xe47f, 0xc138, 0x21, 0 - .dw 0xe4c0, 0xc138, 0xe4ff, 0xc138, 0x21, 0 - .dw 0xe540, 0xc138, 0xe57f, 0xc138, 0x21, 0 - .dw 0xe5c0, 0xc138, 0xe5ff, 0xc138, 0x21, 0 - .dw 0xe640, 0xc138, 0xe67f, 0xc138, 0x21, 0 - .dw 0xe6c0, 0xc138, 0xe6ff, 0xc138, 0x21, 0 - .dw 0xe740, 0xc138, 0xe77f, 0xc138, 0x21, 0 - .dw 0xe7c0, 0xc138, 0xe7ff, 0xc138, 0x21, 0 - .dw 0xe840, 0xc138, 0xe87f, 0xc138, 0x21, 0 - .dw 0xe8c0, 0xc138, 0xe8ff, 0xc138, 0x21, 0 - .dw 0xe940, 0xc138, 0xe97f, 0xc138, 0x21, 0 - .dw 0xe9c0, 0xc138, 0xe9ff, 0xc138, 0x21, 0 - .dw 0xea40, 0xc138, 0xea7f, 0xc138, 0x21, 0 - .dw 0xeac0, 0xc138, 0xeaff, 0xc138, 0x21, 0 - .dw 0xeb40, 0xc138, 0xeb7f, 0xc138, 0x21, 0 - .dw 0xebc0, 0xc138, 0xebff, 0xc138, 0x21, 0 - .dw 0xec40, 0xc138, 0xec7f, 0xc138, 0x21, 0 - .dw 0xecc0, 0xc138, 0xecff, 0xc138, 0x21, 0 - .dw 0xed40, 0xc138, 0xed7f, 0xc138, 0x21, 0 - .dw 0xedc0, 0xc138, 0xedff, 0xc138, 0x21, 0 - .dw 0xee40, 0xc138, 0xee7f, 0xc138, 0x21, 0 - .dw 0xeec0, 0xc138, 0xeeff, 0xc138, 0x21, 0 - .dw 0xef40, 0xc138, 0xef7f, 0xc138, 0x21, 0 - .dw 0xefc0, 0xc138, 0xefff, 0xc138, 0x21, 0 - .dw 0xf040, 0xc138, 0xf07f, 0xc138, 0x21, 0 - .dw 0xf0c0, 0xc138, 0xf0ff, 0xc138, 0x21, 0 - .dw 0xf140, 0xc138, 0xf17f, 0xc138, 0x21, 0 - .dw 0xf1c0, 0xc138, 0xf1ff, 0xc138, 0x21, 0 - .dw 0xf240, 0xc138, 0xf27f, 0xc138, 0x21, 0 - .dw 0xf2c0, 0xc138, 0xf2ff, 0xc138, 0x21, 0 - .dw 0xf340, 0xc138, 0xf37f, 0xc138, 0x21, 0 - .dw 0xf3c0, 0xc138, 0xf3ff, 0xc138, 0x21, 0 - .dw 0xf440, 0xc138, 0xf47f, 0xc138, 0x21, 0 - .dw 0xf4c0, 0xc138, 0xf4ff, 0xc138, 0x21, 0 - .dw 0xf540, 0xc138, 0xf57f, 0xc138, 0x21, 0 - .dw 0xf5c0, 0xc138, 0xf5ff, 0xc138, 0x21, 0 - .dw 0xf640, 0xc138, 0xf67f, 0xc138, 0x21, 0 - .dw 0xf6c0, 0xc138, 0xf6ff, 0xc138, 0x21, 0 - .dw 0xf740, 0xc138, 0xf77f, 0xc138, 0x21, 0 - .dw 0xf7c0, 0xc138, 0xf7ff, 0xc138, 0x21, 0 - .dw 0xf840, 0xc138, 0xf87f, 0xc138, 0x21, 0 - .dw 0xf8c0, 0xc138, 0xf8ff, 0xc138, 0x21, 0 - .dw 0xf940, 0xc138, 0xf97f, 0xc138, 0x21, 0 - .dw 0xf9c0, 0xc138, 0x1fff, 0xc139, 0x21, 0 - .dw 0x2040, 0xc139, 0x207f, 0xc139, 0x21, 0 - .dw 0x20c0, 0xc139, 0x20ff, 0xc139, 0x21, 0 - .dw 0x2140, 0xc139, 0x217f, 0xc139, 0x21, 0 - .dw 0x21c0, 0xc139, 0x21ff, 0xc139, 0x21, 0 - .dw 0x2240, 0xc139, 0x227f, 0xc139, 0x21, 0 - .dw 0x22c0, 0xc139, 0x22ff, 0xc139, 0x21, 0 - .dw 0x2340, 0xc139, 0x237f, 0xc139, 0x21, 0 - .dw 0x23c0, 0xc139, 0x23ff, 0xc139, 0x21, 0 - .dw 0x2440, 0xc139, 0x247f, 0xc139, 0x21, 0 - .dw 0x24c0, 0xc139, 0x24ff, 0xc139, 0x21, 0 - .dw 0x2540, 0xc139, 0x257f, 0xc139, 0x21, 0 - .dw 0x25c0, 0xc139, 0x25ff, 0xc139, 0x21, 0 - .dw 0x2640, 0xc139, 0x267f, 0xc139, 0x21, 0 - .dw 0x26c0, 0xc139, 0x26ff, 0xc139, 0x21, 0 - .dw 0x2740, 0xc139, 0x277f, 0xc139, 0x21, 0 - .dw 0x27c0, 0xc139, 0x27ff, 0xc139, 0x21, 0 - .dw 0x2840, 0xc139, 0x287f, 0xc139, 0x21, 0 - .dw 0x28c0, 0xc139, 0x28ff, 0xc139, 0x21, 0 - .dw 0x2940, 0xc139, 0x297f, 0xc139, 0x21, 0 - .dw 0x29c0, 0xc139, 0x29ff, 0xc139, 0x21, 0 - .dw 0x2a40, 0xc139, 0x2a7f, 0xc139, 0x21, 0 - .dw 0x2ac0, 0xc139, 0x2aff, 0xc139, 0x21, 0 - .dw 0x2b40, 0xc139, 0x2b7f, 0xc139, 0x21, 0 - .dw 0x2bc0, 0xc139, 0x2bff, 0xc139, 0x21, 0 - .dw 0x2c40, 0xc139, 0x2c7f, 0xc139, 0x21, 0 - .dw 0x2cc0, 0xc139, 0x2cff, 0xc139, 0x21, 0 - .dw 0x2d40, 0xc139, 0x2d7f, 0xc139, 0x21, 0 - .dw 0x2dc0, 0xc139, 0x2dff, 0xc139, 0x21, 0 - .dw 0x2e40, 0xc139, 0x2e7f, 0xc139, 0x21, 0 - .dw 0x2ec0, 0xc139, 0x2eff, 0xc139, 0x21, 0 - .dw 0x2f40, 0xc139, 0x2f7f, 0xc139, 0x21, 0 - .dw 0x2fc0, 0xc139, 0x2fff, 0xc139, 0x21, 0 - .dw 0x3040, 0xc139, 0x307f, 0xc139, 0x21, 0 - .dw 0x30c0, 0xc139, 0x30ff, 0xc139, 0x21, 0 - .dw 0x3140, 0xc139, 0x317f, 0xc139, 0x21, 0 - .dw 0x31c0, 0xc139, 0x31ff, 0xc139, 0x21, 0 - .dw 0x3240, 0xc139, 0x327f, 0xc139, 0x21, 0 - .dw 0x32c0, 0xc139, 0x32ff, 0xc139, 0x21, 0 - .dw 0x3340, 0xc139, 0x337f, 0xc139, 0x21, 0 - .dw 0x33c0, 0xc139, 0x33ff, 0xc139, 0x21, 0 - .dw 0x3440, 0xc139, 0x347f, 0xc139, 0x21, 0 - .dw 0x34c0, 0xc139, 0x34ff, 0xc139, 0x21, 0 - .dw 0x3540, 0xc139, 0x357f, 0xc139, 0x21, 0 - .dw 0x35c0, 0xc139, 0x35ff, 0xc139, 0x21, 0 - .dw 0x3640, 0xc139, 0x367f, 0xc139, 0x21, 0 - .dw 0x36c0, 0xc139, 0x36ff, 0xc139, 0x21, 0 - .dw 0x3740, 0xc139, 0x377f, 0xc139, 0x21, 0 - .dw 0x37c0, 0xc139, 0x37ff, 0xc139, 0x21, 0 - .dw 0x3840, 0xc139, 0x387f, 0xc139, 0x21, 0 - .dw 0x38c0, 0xc139, 0x38ff, 0xc139, 0x21, 0 - .dw 0x3940, 0xc139, 0x397f, 0xc139, 0x21, 0 - .dw 0x39c0, 0xc139, 0x5fff, 0xc139, 0x21, 0 - .dw 0x6040, 0xc139, 0x607f, 0xc139, 0x21, 0 - .dw 0x60c0, 0xc139, 0x60ff, 0xc139, 0x21, 0 - .dw 0x6140, 0xc139, 0x617f, 0xc139, 0x21, 0 - .dw 0x61c0, 0xc139, 0x61ff, 0xc139, 0x21, 0 - .dw 0x6240, 0xc139, 0x627f, 0xc139, 0x21, 0 - .dw 0x62c0, 0xc139, 0x62ff, 0xc139, 0x21, 0 - .dw 0x6340, 0xc139, 0x637f, 0xc139, 0x21, 0 - .dw 0x63c0, 0xc139, 0x63ff, 0xc139, 0x21, 0 - .dw 0x6440, 0xc139, 0x647f, 0xc139, 0x21, 0 - .dw 0x64c0, 0xc139, 0x64ff, 0xc139, 0x21, 0 - .dw 0x6540, 0xc139, 0x657f, 0xc139, 0x21, 0 - .dw 0x65c0, 0xc139, 0x65ff, 0xc139, 0x21, 0 - .dw 0x6640, 0xc139, 0x667f, 0xc139, 0x21, 0 - .dw 0x66c0, 0xc139, 0x66ff, 0xc139, 0x21, 0 - .dw 0x6740, 0xc139, 0x677f, 0xc139, 0x21, 0 - .dw 0x67c0, 0xc139, 0x67ff, 0xc139, 0x21, 0 - .dw 0x6840, 0xc139, 0x687f, 0xc139, 0x21, 0 - .dw 0x68c0, 0xc139, 0x68ff, 0xc139, 0x21, 0 - .dw 0x6940, 0xc139, 0x697f, 0xc139, 0x21, 0 - .dw 0x69c0, 0xc139, 0x69ff, 0xc139, 0x21, 0 - .dw 0x6a40, 0xc139, 0x6a7f, 0xc139, 0x21, 0 - .dw 0x6ac0, 0xc139, 0x6aff, 0xc139, 0x21, 0 - .dw 0x6b40, 0xc139, 0x6b7f, 0xc139, 0x21, 0 - .dw 0x6bc0, 0xc139, 0x6bff, 0xc139, 0x21, 0 - .dw 0x6c40, 0xc139, 0x6c7f, 0xc139, 0x21, 0 - .dw 0x6cc0, 0xc139, 0x6cff, 0xc139, 0x21, 0 - .dw 0x6d40, 0xc139, 0x6d7f, 0xc139, 0x21, 0 - .dw 0x6dc0, 0xc139, 0x6dff, 0xc139, 0x21, 0 - .dw 0x6e40, 0xc139, 0x6e7f, 0xc139, 0x21, 0 - .dw 0x6ec0, 0xc139, 0x6eff, 0xc139, 0x21, 0 - .dw 0x6f40, 0xc139, 0x6f7f, 0xc139, 0x21, 0 - .dw 0x6fc0, 0xc139, 0x6fff, 0xc139, 0x21, 0 - .dw 0x7040, 0xc139, 0x707f, 0xc139, 0x21, 0 - .dw 0x70c0, 0xc139, 0x70ff, 0xc139, 0x21, 0 - .dw 0x7140, 0xc139, 0x717f, 0xc139, 0x21, 0 - .dw 0x71c0, 0xc139, 0x71ff, 0xc139, 0x21, 0 - .dw 0x7240, 0xc139, 0x727f, 0xc139, 0x21, 0 - .dw 0x72c0, 0xc139, 0x72ff, 0xc139, 0x21, 0 - .dw 0x7340, 0xc139, 0x737f, 0xc139, 0x21, 0 - .dw 0x73c0, 0xc139, 0x73ff, 0xc139, 0x21, 0 - .dw 0x7440, 0xc139, 0x747f, 0xc139, 0x21, 0 - .dw 0x74c0, 0xc139, 0x74ff, 0xc139, 0x21, 0 - .dw 0x7540, 0xc139, 0x757f, 0xc139, 0x21, 0 - .dw 0x75c0, 0xc139, 0x75ff, 0xc139, 0x21, 0 - .dw 0x7640, 0xc139, 0x767f, 0xc139, 0x21, 0 - .dw 0x76c0, 0xc139, 0x76ff, 0xc139, 0x21, 0 - .dw 0x7740, 0xc139, 0x777f, 0xc139, 0x21, 0 - .dw 0x77c0, 0xc139, 0x77ff, 0xc139, 0x21, 0 - .dw 0x7840, 0xc139, 0x787f, 0xc139, 0x21, 0 - .dw 0x78c0, 0xc139, 0x78ff, 0xc139, 0x21, 0 - .dw 0x7940, 0xc139, 0x797f, 0xc139, 0x21, 0 - .dw 0x79c0, 0xc139, 0x9fff, 0xc139, 0x21, 0 - .dw 0xa040, 0xc139, 0xa07f, 0xc139, 0x21, 0 - .dw 0xa0c0, 0xc139, 0xa0ff, 0xc139, 0x21, 0 - .dw 0xa140, 0xc139, 0xa17f, 0xc139, 0x21, 0 - .dw 0xa1c0, 0xc139, 0xa1ff, 0xc139, 0x21, 0 - .dw 0xa240, 0xc139, 0xa27f, 0xc139, 0x21, 0 - .dw 0xa2c0, 0xc139, 0xa2ff, 0xc139, 0x21, 0 - .dw 0xa340, 0xc139, 0xa37f, 0xc139, 0x21, 0 - .dw 0xa3c0, 0xc139, 0xa3ff, 0xc139, 0x21, 0 - .dw 0xa440, 0xc139, 0xa47f, 0xc139, 0x21, 0 - .dw 0xa4c0, 0xc139, 0xa4ff, 0xc139, 0x21, 0 - .dw 0xa540, 0xc139, 0xa57f, 0xc139, 0x21, 0 - .dw 0xa5c0, 0xc139, 0xa5ff, 0xc139, 0x21, 0 - .dw 0xa640, 0xc139, 0xa67f, 0xc139, 0x21, 0 - .dw 0xa6c0, 0xc139, 0xa6ff, 0xc139, 0x21, 0 - .dw 0xa740, 0xc139, 0xa77f, 0xc139, 0x21, 0 - .dw 0xa7c0, 0xc139, 0xa7ff, 0xc139, 0x21, 0 - .dw 0xa840, 0xc139, 0xa87f, 0xc139, 0x21, 0 - .dw 0xa8c0, 0xc139, 0xa8ff, 0xc139, 0x21, 0 - .dw 0xa940, 0xc139, 0xa97f, 0xc139, 0x21, 0 - .dw 0xa9c0, 0xc139, 0xa9ff, 0xc139, 0x21, 0 - .dw 0xaa40, 0xc139, 0xaa7f, 0xc139, 0x21, 0 - .dw 0xaac0, 0xc139, 0xaaff, 0xc139, 0x21, 0 - .dw 0xab40, 0xc139, 0xab7f, 0xc139, 0x21, 0 - .dw 0xabc0, 0xc139, 0xabff, 0xc139, 0x21, 0 - .dw 0xac40, 0xc139, 0xac7f, 0xc139, 0x21, 0 - .dw 0xacc0, 0xc139, 0xacff, 0xc139, 0x21, 0 - .dw 0xad40, 0xc139, 0xad7f, 0xc139, 0x21, 0 - .dw 0xadc0, 0xc139, 0xadff, 0xc139, 0x21, 0 - .dw 0xae40, 0xc139, 0xae7f, 0xc139, 0x21, 0 - .dw 0xaec0, 0xc139, 0xaeff, 0xc139, 0x21, 0 - .dw 0xaf40, 0xc139, 0xaf7f, 0xc139, 0x21, 0 - .dw 0xafc0, 0xc139, 0xafff, 0xc139, 0x21, 0 - .dw 0xb040, 0xc139, 0xb07f, 0xc139, 0x21, 0 - .dw 0xb0c0, 0xc139, 0xb0ff, 0xc139, 0x21, 0 - .dw 0xb140, 0xc139, 0xb17f, 0xc139, 0x21, 0 - .dw 0xb1c0, 0xc139, 0xb1ff, 0xc139, 0x21, 0 - .dw 0xb240, 0xc139, 0xb27f, 0xc139, 0x21, 0 - .dw 0xb2c0, 0xc139, 0xb2ff, 0xc139, 0x21, 0 - .dw 0xb340, 0xc139, 0xb37f, 0xc139, 0x21, 0 - .dw 0xb3c0, 0xc139, 0xb3ff, 0xc139, 0x21, 0 - .dw 0xb440, 0xc139, 0xb47f, 0xc139, 0x21, 0 - .dw 0xb4c0, 0xc139, 0xb4ff, 0xc139, 0x21, 0 - .dw 0xb540, 0xc139, 0xb57f, 0xc139, 0x21, 0 - .dw 0xb5c0, 0xc139, 0xb5ff, 0xc139, 0x21, 0 - .dw 0xb640, 0xc139, 0xb67f, 0xc139, 0x21, 0 - .dw 0xb6c0, 0xc139, 0xb6ff, 0xc139, 0x21, 0 - .dw 0xb740, 0xc139, 0xb77f, 0xc139, 0x21, 0 - .dw 0xb7c0, 0xc139, 0xb7ff, 0xc139, 0x21, 0 - .dw 0xb840, 0xc139, 0xb87f, 0xc139, 0x21, 0 - .dw 0xb8c0, 0xc139, 0xb8ff, 0xc139, 0x21, 0 - .dw 0xb940, 0xc139, 0xb97f, 0xc139, 0x21, 0 - .dw 0xb9c0, 0xc139, 0xdfff, 0xc139, 0x21, 0 - .dw 0xe040, 0xc139, 0xe07f, 0xc139, 0x21, 0 - .dw 0xe0c0, 0xc139, 0xe0ff, 0xc139, 0x21, 0 - .dw 0xe140, 0xc139, 0xe17f, 0xc139, 0x21, 0 - .dw 0xe1c0, 0xc139, 0xe1ff, 0xc139, 0x21, 0 - .dw 0xe240, 0xc139, 0xe27f, 0xc139, 0x21, 0 - .dw 0xe2c0, 0xc139, 0xe2ff, 0xc139, 0x21, 0 - .dw 0xe340, 0xc139, 0xe37f, 0xc139, 0x21, 0 - .dw 0xe3c0, 0xc139, 0xe3ff, 0xc139, 0x21, 0 - .dw 0xe440, 0xc139, 0xe47f, 0xc139, 0x21, 0 - .dw 0xe4c0, 0xc139, 0xe4ff, 0xc139, 0x21, 0 - .dw 0xe540, 0xc139, 0xe57f, 0xc139, 0x21, 0 - .dw 0xe5c0, 0xc139, 0xe5ff, 0xc139, 0x21, 0 - .dw 0xe640, 0xc139, 0xe67f, 0xc139, 0x21, 0 - .dw 0xe6c0, 0xc139, 0xe6ff, 0xc139, 0x21, 0 - .dw 0xe740, 0xc139, 0xe77f, 0xc139, 0x21, 0 - .dw 0xe7c0, 0xc139, 0xe7ff, 0xc139, 0x21, 0 - .dw 0xe840, 0xc139, 0xe87f, 0xc139, 0x21, 0 - .dw 0xe8c0, 0xc139, 0xe8ff, 0xc139, 0x21, 0 - .dw 0xe940, 0xc139, 0xe97f, 0xc139, 0x21, 0 - .dw 0xe9c0, 0xc139, 0xe9ff, 0xc139, 0x21, 0 - .dw 0xea40, 0xc139, 0xea7f, 0xc139, 0x21, 0 - .dw 0xeac0, 0xc139, 0xeaff, 0xc139, 0x21, 0 - .dw 0xeb40, 0xc139, 0xeb7f, 0xc139, 0x21, 0 - .dw 0xebc0, 0xc139, 0xebff, 0xc139, 0x21, 0 - .dw 0xec40, 0xc139, 0xec7f, 0xc139, 0x21, 0 - .dw 0xecc0, 0xc139, 0xecff, 0xc139, 0x21, 0 - .dw 0xed40, 0xc139, 0xed7f, 0xc139, 0x21, 0 - .dw 0xedc0, 0xc139, 0xedff, 0xc139, 0x21, 0 - .dw 0xee40, 0xc139, 0xee7f, 0xc139, 0x21, 0 - .dw 0xeec0, 0xc139, 0xeeff, 0xc139, 0x21, 0 - .dw 0xef40, 0xc139, 0xef7f, 0xc139, 0x21, 0 - .dw 0xefc0, 0xc139, 0xefff, 0xc139, 0x21, 0 - .dw 0xf040, 0xc139, 0xf07f, 0xc139, 0x21, 0 - .dw 0xf0c0, 0xc139, 0xf0ff, 0xc139, 0x21, 0 - .dw 0xf140, 0xc139, 0xf17f, 0xc139, 0x21, 0 - .dw 0xf1c0, 0xc139, 0xf1ff, 0xc139, 0x21, 0 - .dw 0xf240, 0xc139, 0xf27f, 0xc139, 0x21, 0 - .dw 0xf2c0, 0xc139, 0xf2ff, 0xc139, 0x21, 0 - .dw 0xf340, 0xc139, 0xf37f, 0xc139, 0x21, 0 - .dw 0xf3c0, 0xc139, 0xf3ff, 0xc139, 0x21, 0 - .dw 0xf440, 0xc139, 0xf47f, 0xc139, 0x21, 0 - .dw 0xf4c0, 0xc139, 0xf4ff, 0xc139, 0x21, 0 - .dw 0xf540, 0xc139, 0xf57f, 0xc139, 0x21, 0 - .dw 0xf5c0, 0xc139, 0xf5ff, 0xc139, 0x21, 0 - .dw 0xf640, 0xc139, 0xf67f, 0xc139, 0x21, 0 - .dw 0xf6c0, 0xc139, 0xf6ff, 0xc139, 0x21, 0 - .dw 0xf740, 0xc139, 0xf77f, 0xc139, 0x21, 0 - .dw 0xf7c0, 0xc139, 0xf7ff, 0xc139, 0x21, 0 - .dw 0xf840, 0xc139, 0xf87f, 0xc139, 0x21, 0 - .dw 0xf8c0, 0xc139, 0xf8ff, 0xc139, 0x21, 0 - .dw 0xf940, 0xc139, 0xf97f, 0xc139, 0x21, 0 - .dw 0xf9c0, 0xc139, 0x1fff, 0xc13a, 0x21, 0 - .dw 0x2040, 0xc13a, 0x207f, 0xc13a, 0x21, 0 - .dw 0x20c0, 0xc13a, 0x20ff, 0xc13a, 0x21, 0 - .dw 0x2140, 0xc13a, 0x217f, 0xc13a, 0x21, 0 - .dw 0x21c0, 0xc13a, 0x21ff, 0xc13a, 0x21, 0 - .dw 0x2240, 0xc13a, 0x227f, 0xc13a, 0x21, 0 - .dw 0x22c0, 0xc13a, 0x22ff, 0xc13a, 0x21, 0 - .dw 0x2340, 0xc13a, 0x237f, 0xc13a, 0x21, 0 - .dw 0x23c0, 0xc13a, 0x23ff, 0xc13a, 0x21, 0 - .dw 0x2440, 0xc13a, 0x247f, 0xc13a, 0x21, 0 - .dw 0x24c0, 0xc13a, 0x24ff, 0xc13a, 0x21, 0 - .dw 0x2540, 0xc13a, 0x257f, 0xc13a, 0x21, 0 - .dw 0x25c0, 0xc13a, 0x25ff, 0xc13a, 0x21, 0 - .dw 0x2640, 0xc13a, 0x267f, 0xc13a, 0x21, 0 - .dw 0x26c0, 0xc13a, 0x26ff, 0xc13a, 0x21, 0 - .dw 0x2740, 0xc13a, 0x277f, 0xc13a, 0x21, 0 - .dw 0x27c0, 0xc13a, 0x27ff, 0xc13a, 0x21, 0 - .dw 0x2840, 0xc13a, 0x287f, 0xc13a, 0x21, 0 - .dw 0x28c0, 0xc13a, 0x28ff, 0xc13a, 0x21, 0 - .dw 0x2940, 0xc13a, 0x297f, 0xc13a, 0x21, 0 - .dw 0x29c0, 0xc13a, 0x29ff, 0xc13a, 0x21, 0 - .dw 0x2a40, 0xc13a, 0x2a7f, 0xc13a, 0x21, 0 - .dw 0x2ac0, 0xc13a, 0x2aff, 0xc13a, 0x21, 0 - .dw 0x2b40, 0xc13a, 0x2b7f, 0xc13a, 0x21, 0 - .dw 0x2bc0, 0xc13a, 0x2bff, 0xc13a, 0x21, 0 - .dw 0x2c40, 0xc13a, 0x2c7f, 0xc13a, 0x21, 0 - .dw 0x2cc0, 0xc13a, 0x2cff, 0xc13a, 0x21, 0 - .dw 0x2d40, 0xc13a, 0x2d7f, 0xc13a, 0x21, 0 - .dw 0x2dc0, 0xc13a, 0x2dff, 0xc13a, 0x21, 0 - .dw 0x2e40, 0xc13a, 0x2e7f, 0xc13a, 0x21, 0 - .dw 0x2ec0, 0xc13a, 0x2eff, 0xc13a, 0x21, 0 - .dw 0x2f40, 0xc13a, 0x2f7f, 0xc13a, 0x21, 0 - .dw 0x2fc0, 0xc13a, 0x2fff, 0xc13a, 0x21, 0 - .dw 0x3040, 0xc13a, 0x307f, 0xc13a, 0x21, 0 - .dw 0x30c0, 0xc13a, 0x30ff, 0xc13a, 0x21, 0 - .dw 0x3140, 0xc13a, 0x317f, 0xc13a, 0x21, 0 - .dw 0x31c0, 0xc13a, 0x31ff, 0xc13a, 0x21, 0 - .dw 0x3240, 0xc13a, 0x327f, 0xc13a, 0x21, 0 - .dw 0x32c0, 0xc13a, 0x32ff, 0xc13a, 0x21, 0 - .dw 0x3340, 0xc13a, 0x337f, 0xc13a, 0x21, 0 - .dw 0x33c0, 0xc13a, 0x33ff, 0xc13a, 0x21, 0 - .dw 0x3440, 0xc13a, 0x347f, 0xc13a, 0x21, 0 - .dw 0x34c0, 0xc13a, 0x34ff, 0xc13a, 0x21, 0 - .dw 0x3540, 0xc13a, 0x357f, 0xc13a, 0x21, 0 - .dw 0x35c0, 0xc13a, 0x35ff, 0xc13a, 0x21, 0 - .dw 0x3640, 0xc13a, 0x367f, 0xc13a, 0x21, 0 - .dw 0x36c0, 0xc13a, 0x36ff, 0xc13a, 0x21, 0 - .dw 0x3740, 0xc13a, 0x377f, 0xc13a, 0x21, 0 - .dw 0x37c0, 0xc13a, 0x37ff, 0xc13a, 0x21, 0 - .dw 0x3840, 0xc13a, 0x387f, 0xc13a, 0x21, 0 - .dw 0x38c0, 0xc13a, 0x38ff, 0xc13a, 0x21, 0 - .dw 0x3940, 0xc13a, 0x397f, 0xc13a, 0x21, 0 - .dw 0x39c0, 0xc13a, 0x5fff, 0xc13a, 0x21, 0 - .dw 0x6040, 0xc13a, 0x607f, 0xc13a, 0x21, 0 - .dw 0x60c0, 0xc13a, 0x60ff, 0xc13a, 0x21, 0 - .dw 0x6140, 0xc13a, 0x617f, 0xc13a, 0x21, 0 - .dw 0x61c0, 0xc13a, 0x61ff, 0xc13a, 0x21, 0 - .dw 0x6240, 0xc13a, 0x627f, 0xc13a, 0x21, 0 - .dw 0x62c0, 0xc13a, 0x62ff, 0xc13a, 0x21, 0 - .dw 0x6340, 0xc13a, 0x637f, 0xc13a, 0x21, 0 - .dw 0x63c0, 0xc13a, 0x63ff, 0xc13a, 0x21, 0 - .dw 0x6440, 0xc13a, 0x647f, 0xc13a, 0x21, 0 - .dw 0x64c0, 0xc13a, 0x64ff, 0xc13a, 0x21, 0 - .dw 0x6540, 0xc13a, 0x657f, 0xc13a, 0x21, 0 - .dw 0x65c0, 0xc13a, 0x65ff, 0xc13a, 0x21, 0 - .dw 0x6640, 0xc13a, 0x667f, 0xc13a, 0x21, 0 - .dw 0x66c0, 0xc13a, 0x66ff, 0xc13a, 0x21, 0 - .dw 0x6740, 0xc13a, 0x677f, 0xc13a, 0x21, 0 - .dw 0x67c0, 0xc13a, 0x67ff, 0xc13a, 0x21, 0 - .dw 0x6840, 0xc13a, 0x687f, 0xc13a, 0x21, 0 - .dw 0x68c0, 0xc13a, 0x68ff, 0xc13a, 0x21, 0 - .dw 0x6940, 0xc13a, 0x697f, 0xc13a, 0x21, 0 - .dw 0x69c0, 0xc13a, 0x69ff, 0xc13a, 0x21, 0 - .dw 0x6a40, 0xc13a, 0x6a7f, 0xc13a, 0x21, 0 - .dw 0x6ac0, 0xc13a, 0x6aff, 0xc13a, 0x21, 0 - .dw 0x6b40, 0xc13a, 0x6b7f, 0xc13a, 0x21, 0 - .dw 0x6bc0, 0xc13a, 0x6bff, 0xc13a, 0x21, 0 - .dw 0x6c40, 0xc13a, 0x6c7f, 0xc13a, 0x21, 0 - .dw 0x6cc0, 0xc13a, 0x6cff, 0xc13a, 0x21, 0 - .dw 0x6d40, 0xc13a, 0x6d7f, 0xc13a, 0x21, 0 - .dw 0x6dc0, 0xc13a, 0x6dff, 0xc13a, 0x21, 0 - .dw 0x6e40, 0xc13a, 0x6e7f, 0xc13a, 0x21, 0 - .dw 0x6ec0, 0xc13a, 0x6eff, 0xc13a, 0x21, 0 - .dw 0x6f40, 0xc13a, 0x6f7f, 0xc13a, 0x21, 0 - .dw 0x6fc0, 0xc13a, 0x6fff, 0xc13a, 0x21, 0 - .dw 0x7040, 0xc13a, 0x707f, 0xc13a, 0x21, 0 - .dw 0x70c0, 0xc13a, 0x70ff, 0xc13a, 0x21, 0 - .dw 0x7140, 0xc13a, 0x717f, 0xc13a, 0x21, 0 - .dw 0x71c0, 0xc13a, 0x71ff, 0xc13a, 0x21, 0 - .dw 0x7240, 0xc13a, 0x727f, 0xc13a, 0x21, 0 - .dw 0x72c0, 0xc13a, 0x72ff, 0xc13a, 0x21, 0 - .dw 0x7340, 0xc13a, 0x737f, 0xc13a, 0x21, 0 - .dw 0x73c0, 0xc13a, 0x73ff, 0xc13a, 0x21, 0 - .dw 0x7440, 0xc13a, 0x747f, 0xc13a, 0x21, 0 - .dw 0x74c0, 0xc13a, 0x74ff, 0xc13a, 0x21, 0 - .dw 0x7540, 0xc13a, 0x757f, 0xc13a, 0x21, 0 - .dw 0x75c0, 0xc13a, 0x75ff, 0xc13a, 0x21, 0 - .dw 0x7640, 0xc13a, 0x767f, 0xc13a, 0x21, 0 - .dw 0x76c0, 0xc13a, 0x76ff, 0xc13a, 0x21, 0 - .dw 0x7740, 0xc13a, 0x777f, 0xc13a, 0x21, 0 - .dw 0x77c0, 0xc13a, 0x77ff, 0xc13a, 0x21, 0 - .dw 0x7840, 0xc13a, 0x787f, 0xc13a, 0x21, 0 - .dw 0x78c0, 0xc13a, 0x78ff, 0xc13a, 0x21, 0 - .dw 0x7940, 0xc13a, 0x797f, 0xc13a, 0x21, 0 - .dw 0x79c0, 0xc13a, 0x9fff, 0xc13a, 0x21, 0 - .dw 0xa040, 0xc13a, 0xa07f, 0xc13a, 0x21, 0 - .dw 0xa0c0, 0xc13a, 0xa0ff, 0xc13a, 0x21, 0 - .dw 0xa140, 0xc13a, 0xa17f, 0xc13a, 0x21, 0 - .dw 0xa1c0, 0xc13a, 0xa1ff, 0xc13a, 0x21, 0 - .dw 0xa240, 0xc13a, 0xa27f, 0xc13a, 0x21, 0 - .dw 0xa2c0, 0xc13a, 0xa2ff, 0xc13a, 0x21, 0 - .dw 0xa340, 0xc13a, 0xa37f, 0xc13a, 0x21, 0 - .dw 0xa3c0, 0xc13a, 0xa3ff, 0xc13a, 0x21, 0 - .dw 0xa440, 0xc13a, 0xa47f, 0xc13a, 0x21, 0 - .dw 0xa4c0, 0xc13a, 0xa4ff, 0xc13a, 0x21, 0 - .dw 0xa540, 0xc13a, 0xa57f, 0xc13a, 0x21, 0 - .dw 0xa5c0, 0xc13a, 0xa5ff, 0xc13a, 0x21, 0 - .dw 0xa640, 0xc13a, 0xa67f, 0xc13a, 0x21, 0 - .dw 0xa6c0, 0xc13a, 0xa6ff, 0xc13a, 0x21, 0 - .dw 0xa740, 0xc13a, 0xa77f, 0xc13a, 0x21, 0 - .dw 0xa7c0, 0xc13a, 0xa7ff, 0xc13a, 0x21, 0 - .dw 0xa840, 0xc13a, 0xa87f, 0xc13a, 0x21, 0 - .dw 0xa8c0, 0xc13a, 0xa8ff, 0xc13a, 0x21, 0 - .dw 0xa940, 0xc13a, 0xa97f, 0xc13a, 0x21, 0 - .dw 0xa9c0, 0xc13a, 0xa9ff, 0xc13a, 0x21, 0 - .dw 0xaa40, 0xc13a, 0xaa7f, 0xc13a, 0x21, 0 - .dw 0xaac0, 0xc13a, 0xaaff, 0xc13a, 0x21, 0 - .dw 0xab40, 0xc13a, 0xab7f, 0xc13a, 0x21, 0 - .dw 0xabc0, 0xc13a, 0xabff, 0xc13a, 0x21, 0 - .dw 0xac40, 0xc13a, 0xac7f, 0xc13a, 0x21, 0 - .dw 0xacc0, 0xc13a, 0xacff, 0xc13a, 0x21, 0 - .dw 0xad40, 0xc13a, 0xad7f, 0xc13a, 0x21, 0 - .dw 0xadc0, 0xc13a, 0xadff, 0xc13a, 0x21, 0 - .dw 0xae40, 0xc13a, 0xae7f, 0xc13a, 0x21, 0 - .dw 0xaec0, 0xc13a, 0xaeff, 0xc13a, 0x21, 0 - .dw 0xaf40, 0xc13a, 0xaf7f, 0xc13a, 0x21, 0 - .dw 0xafc0, 0xc13a, 0xafff, 0xc13a, 0x21, 0 - .dw 0xb040, 0xc13a, 0xb07f, 0xc13a, 0x21, 0 - .dw 0xb0c0, 0xc13a, 0xb0ff, 0xc13a, 0x21, 0 - .dw 0xb140, 0xc13a, 0xb17f, 0xc13a, 0x21, 0 - .dw 0xb1c0, 0xc13a, 0xb1ff, 0xc13a, 0x21, 0 - .dw 0xb240, 0xc13a, 0xb27f, 0xc13a, 0x21, 0 - .dw 0xb2c0, 0xc13a, 0xb2ff, 0xc13a, 0x21, 0 - .dw 0xb340, 0xc13a, 0xb37f, 0xc13a, 0x21, 0 - .dw 0xb3c0, 0xc13a, 0xb3ff, 0xc13a, 0x21, 0 - .dw 0xb440, 0xc13a, 0xb47f, 0xc13a, 0x21, 0 - .dw 0xb4c0, 0xc13a, 0xb4ff, 0xc13a, 0x21, 0 - .dw 0xb540, 0xc13a, 0xb57f, 0xc13a, 0x21, 0 - .dw 0xb5c0, 0xc13a, 0xb5ff, 0xc13a, 0x21, 0 - .dw 0xb640, 0xc13a, 0xb67f, 0xc13a, 0x21, 0 - .dw 0xb6c0, 0xc13a, 0xb6ff, 0xc13a, 0x21, 0 - .dw 0xb740, 0xc13a, 0xb77f, 0xc13a, 0x21, 0 - .dw 0xb7c0, 0xc13a, 0xb7ff, 0xc13a, 0x21, 0 - .dw 0xb840, 0xc13a, 0xb87f, 0xc13a, 0x21, 0 - .dw 0xb8c0, 0xc13a, 0xb8ff, 0xc13a, 0x21, 0 - .dw 0xb940, 0xc13a, 0xb97f, 0xc13a, 0x21, 0 - .dw 0xb9c0, 0xc13a, 0xdfff, 0xc13a, 0x21, 0 - .dw 0xe040, 0xc13a, 0xe07f, 0xc13a, 0x21, 0 - .dw 0xe0c0, 0xc13a, 0xe0ff, 0xc13a, 0x21, 0 - .dw 0xe140, 0xc13a, 0xe17f, 0xc13a, 0x21, 0 - .dw 0xe1c0, 0xc13a, 0xe1ff, 0xc13a, 0x21, 0 - .dw 0xe240, 0xc13a, 0xe27f, 0xc13a, 0x21, 0 - .dw 0xe2c0, 0xc13a, 0xe2ff, 0xc13a, 0x21, 0 - .dw 0xe340, 0xc13a, 0xe37f, 0xc13a, 0x21, 0 - .dw 0xe3c0, 0xc13a, 0xe3ff, 0xc13a, 0x21, 0 - .dw 0xe440, 0xc13a, 0xe47f, 0xc13a, 0x21, 0 - .dw 0xe4c0, 0xc13a, 0xe4ff, 0xc13a, 0x21, 0 - .dw 0xe540, 0xc13a, 0xe57f, 0xc13a, 0x21, 0 - .dw 0xe5c0, 0xc13a, 0xe5ff, 0xc13a, 0x21, 0 - .dw 0xe640, 0xc13a, 0xe67f, 0xc13a, 0x21, 0 - .dw 0xe6c0, 0xc13a, 0xe6ff, 0xc13a, 0x21, 0 - .dw 0xe740, 0xc13a, 0xe77f, 0xc13a, 0x21, 0 - .dw 0xe7c0, 0xc13a, 0xe7ff, 0xc13a, 0x21, 0 - .dw 0xe840, 0xc13a, 0xe87f, 0xc13a, 0x21, 0 - .dw 0xe8c0, 0xc13a, 0xe8ff, 0xc13a, 0x21, 0 - .dw 0xe940, 0xc13a, 0xe97f, 0xc13a, 0x21, 0 - .dw 0xe9c0, 0xc13a, 0xe9ff, 0xc13a, 0x21, 0 - .dw 0xea40, 0xc13a, 0xea7f, 0xc13a, 0x21, 0 - .dw 0xeac0, 0xc13a, 0xeaff, 0xc13a, 0x21, 0 - .dw 0xeb40, 0xc13a, 0xeb7f, 0xc13a, 0x21, 0 - .dw 0xebc0, 0xc13a, 0xebff, 0xc13a, 0x21, 0 - .dw 0xec40, 0xc13a, 0xec7f, 0xc13a, 0x21, 0 - .dw 0xecc0, 0xc13a, 0xecff, 0xc13a, 0x21, 0 - .dw 0xed40, 0xc13a, 0xed7f, 0xc13a, 0x21, 0 - .dw 0xedc0, 0xc13a, 0xedff, 0xc13a, 0x21, 0 - .dw 0xee40, 0xc13a, 0xee7f, 0xc13a, 0x21, 0 - .dw 0xeec0, 0xc13a, 0xeeff, 0xc13a, 0x21, 0 - .dw 0xef40, 0xc13a, 0xef7f, 0xc13a, 0x21, 0 - .dw 0xefc0, 0xc13a, 0xefff, 0xc13a, 0x21, 0 - .dw 0xf040, 0xc13a, 0xf07f, 0xc13a, 0x21, 0 - .dw 0xf0c0, 0xc13a, 0xf0ff, 0xc13a, 0x21, 0 - .dw 0xf140, 0xc13a, 0xf17f, 0xc13a, 0x21, 0 - .dw 0xf1c0, 0xc13a, 0xf1ff, 0xc13a, 0x21, 0 - .dw 0xf240, 0xc13a, 0xf27f, 0xc13a, 0x21, 0 - .dw 0xf2c0, 0xc13a, 0xf2ff, 0xc13a, 0x21, 0 - .dw 0xf340, 0xc13a, 0xf37f, 0xc13a, 0x21, 0 - .dw 0xf3c0, 0xc13a, 0xf3ff, 0xc13a, 0x21, 0 - .dw 0xf440, 0xc13a, 0xf47f, 0xc13a, 0x21, 0 - .dw 0xf4c0, 0xc13a, 0xf4ff, 0xc13a, 0x21, 0 - .dw 0xf540, 0xc13a, 0xf57f, 0xc13a, 0x21, 0 - .dw 0xf5c0, 0xc13a, 0xf5ff, 0xc13a, 0x21, 0 - .dw 0xf640, 0xc13a, 0xf67f, 0xc13a, 0x21, 0 - .dw 0xf6c0, 0xc13a, 0xf6ff, 0xc13a, 0x21, 0 - .dw 0xf740, 0xc13a, 0xf77f, 0xc13a, 0x21, 0 - .dw 0xf7c0, 0xc13a, 0xf7ff, 0xc13a, 0x21, 0 - .dw 0xf840, 0xc13a, 0xf87f, 0xc13a, 0x21, 0 - .dw 0xf8c0, 0xc13a, 0xf8ff, 0xc13a, 0x21, 0 - .dw 0xf940, 0xc13a, 0xf97f, 0xc13a, 0x21, 0 - .dw 0xf9c0, 0xc13a, 0xffff, 0xc13b, 0x21, 0 - .dw 0x0040, 0xc13c, 0x007f, 0xc13c, 0x21, 0 - .dw 0x00c0, 0xc13c, 0x00ff, 0xc13c, 0x21, 0 - .dw 0x0140, 0xc13c, 0x017f, 0xc13c, 0x21, 0 - .dw 0x01c0, 0xc13c, 0x01ff, 0xc13c, 0x21, 0 - .dw 0x0240, 0xc13c, 0x027f, 0xc13c, 0x21, 0 - .dw 0x02c0, 0xc13c, 0x02ff, 0xc13c, 0x21, 0 - .dw 0x0340, 0xc13c, 0x037f, 0xc13c, 0x21, 0 - .dw 0x03c0, 0xc13c, 0x03ff, 0xc13c, 0x21, 0 - .dw 0x0440, 0xc13c, 0x047f, 0xc13c, 0x21, 0 - .dw 0x04c0, 0xc13c, 0x04ff, 0xc13c, 0x21, 0 - .dw 0x0540, 0xc13c, 0x057f, 0xc13c, 0x21, 0 - .dw 0x05c0, 0xc13c, 0x05ff, 0xc13c, 0x21, 0 - .dw 0x0640, 0xc13c, 0x067f, 0xc13c, 0x21, 0 - .dw 0x06c0, 0xc13c, 0x06ff, 0xc13c, 0x21, 0 - .dw 0x0740, 0xc13c, 0x077f, 0xc13c, 0x21, 0 - .dw 0x07c0, 0xc13c, 0x07ff, 0xc13c, 0x21, 0 - .dw 0x0840, 0xc13c, 0x087f, 0xc13c, 0x21, 0 - .dw 0x08c0, 0xc13c, 0x08ff, 0xc13c, 0x21, 0 - .dw 0x0940, 0xc13c, 0x097f, 0xc13c, 0x21, 0 - .dw 0x09c0, 0xc13c, 0x09ff, 0xc13c, 0x21, 0 - .dw 0x0a40, 0xc13c, 0x0a7f, 0xc13c, 0x21, 0 - .dw 0x0ac0, 0xc13c, 0x0aff, 0xc13c, 0x21, 0 - .dw 0x0b40, 0xc13c, 0x0b7f, 0xc13c, 0x21, 0 - .dw 0x0bc0, 0xc13c, 0x0bff, 0xc13c, 0x21, 0 - .dw 0x0c40, 0xc13c, 0x0c7f, 0xc13c, 0x21, 0 - .dw 0x0cc0, 0xc13c, 0x0cff, 0xc13c, 0x21, 0 - .dw 0x0d40, 0xc13c, 0x0d7f, 0xc13c, 0x21, 0 - .dw 0x0dc0, 0xc13c, 0x0dff, 0xc13c, 0x21, 0 - .dw 0x0e40, 0xc13c, 0x0e7f, 0xc13c, 0x21, 0 - .dw 0x0ec0, 0xc13c, 0x0eff, 0xc13c, 0x21, 0 - .dw 0x0f40, 0xc13c, 0x0f7f, 0xc13c, 0x21, 0 - .dw 0x0fc0, 0xc13c, 0x0fff, 0xc13c, 0x21, 0 - .dw 0x1040, 0xc13c, 0x107f, 0xc13c, 0x21, 0 - .dw 0x10c0, 0xc13c, 0x10ff, 0xc13c, 0x21, 0 - .dw 0x1140, 0xc13c, 0x117f, 0xc13c, 0x21, 0 - .dw 0x11c0, 0xc13c, 0x11ff, 0xc13c, 0x21, 0 - .dw 0x1240, 0xc13c, 0x127f, 0xc13c, 0x21, 0 - .dw 0x12c0, 0xc13c, 0x12ff, 0xc13c, 0x21, 0 - .dw 0x1340, 0xc13c, 0x137f, 0xc13c, 0x21, 0 - .dw 0x13c0, 0xc13c, 0x13ff, 0xc13c, 0x21, 0 - .dw 0x1440, 0xc13c, 0x147f, 0xc13c, 0x21, 0 - .dw 0x14c0, 0xc13c, 0x14ff, 0xc13c, 0x21, 0 - .dw 0x1540, 0xc13c, 0x157f, 0xc13c, 0x21, 0 - .dw 0x15c0, 0xc13c, 0x15ff, 0xc13c, 0x21, 0 - .dw 0x1640, 0xc13c, 0x167f, 0xc13c, 0x21, 0 - .dw 0x16c0, 0xc13c, 0x16ff, 0xc13c, 0x21, 0 - .dw 0x1740, 0xc13c, 0x177f, 0xc13c, 0x21, 0 - .dw 0x17c0, 0xc13c, 0x17ff, 0xc13c, 0x21, 0 - .dw 0x1840, 0xc13c, 0x187f, 0xc13c, 0x21, 0 - .dw 0x18c0, 0xc13c, 0x18ff, 0xc13c, 0x21, 0 - .dw 0x1940, 0xc13c, 0x197f, 0xc13c, 0x21, 0 - .dw 0x19c0, 0xc13c, 0x1fff, 0xc13c, 0x21, 0 - .dw 0x2040, 0xc13c, 0x207f, 0xc13c, 0x21, 0 - .dw 0x20c0, 0xc13c, 0x20ff, 0xc13c, 0x21, 0 - .dw 0x2140, 0xc13c, 0x217f, 0xc13c, 0x21, 0 - .dw 0x21c0, 0xc13c, 0x21ff, 0xc13c, 0x21, 0 - .dw 0x2240, 0xc13c, 0x227f, 0xc13c, 0x21, 0 - .dw 0x22c0, 0xc13c, 0x22ff, 0xc13c, 0x21, 0 - .dw 0x2340, 0xc13c, 0x237f, 0xc13c, 0x21, 0 - .dw 0x23c0, 0xc13c, 0x23ff, 0xc13c, 0x21, 0 - .dw 0x2440, 0xc13c, 0x247f, 0xc13c, 0x21, 0 - .dw 0x24c0, 0xc13c, 0x24ff, 0xc13c, 0x21, 0 - .dw 0x2540, 0xc13c, 0x257f, 0xc13c, 0x21, 0 - .dw 0x25c0, 0xc13c, 0x25ff, 0xc13c, 0x21, 0 - .dw 0x2640, 0xc13c, 0x267f, 0xc13c, 0x21, 0 - .dw 0x26c0, 0xc13c, 0x26ff, 0xc13c, 0x21, 0 - .dw 0x2740, 0xc13c, 0x277f, 0xc13c, 0x21, 0 - .dw 0x27c0, 0xc13c, 0x27ff, 0xc13c, 0x21, 0 - .dw 0x2840, 0xc13c, 0x287f, 0xc13c, 0x21, 0 - .dw 0x28c0, 0xc13c, 0x28ff, 0xc13c, 0x21, 0 - .dw 0x2940, 0xc13c, 0x297f, 0xc13c, 0x21, 0 - .dw 0x29c0, 0xc13c, 0x29ff, 0xc13c, 0x21, 0 - .dw 0x2a40, 0xc13c, 0x2a7f, 0xc13c, 0x21, 0 - .dw 0x2ac0, 0xc13c, 0x2aff, 0xc13c, 0x21, 0 - .dw 0x2b40, 0xc13c, 0x2b7f, 0xc13c, 0x21, 0 - .dw 0x2bc0, 0xc13c, 0x2bff, 0xc13c, 0x21, 0 - .dw 0x2c40, 0xc13c, 0x2c7f, 0xc13c, 0x21, 0 - .dw 0x2cc0, 0xc13c, 0x2cff, 0xc13c, 0x21, 0 - .dw 0x2d40, 0xc13c, 0x2d7f, 0xc13c, 0x21, 0 - .dw 0x2dc0, 0xc13c, 0x2dff, 0xc13c, 0x21, 0 - .dw 0x2e40, 0xc13c, 0x2e7f, 0xc13c, 0x21, 0 - .dw 0x2ec0, 0xc13c, 0x2eff, 0xc13c, 0x21, 0 - .dw 0x2f40, 0xc13c, 0x2f7f, 0xc13c, 0x21, 0 - .dw 0x2fc0, 0xc13c, 0x2fff, 0xc13c, 0x21, 0 - .dw 0x3040, 0xc13c, 0x307f, 0xc13c, 0x21, 0 - .dw 0x30c0, 0xc13c, 0x30ff, 0xc13c, 0x21, 0 - .dw 0x3140, 0xc13c, 0x317f, 0xc13c, 0x21, 0 - .dw 0x31c0, 0xc13c, 0x31ff, 0xc13c, 0x21, 0 - .dw 0x3240, 0xc13c, 0x327f, 0xc13c, 0x21, 0 - .dw 0x32c0, 0xc13c, 0x32ff, 0xc13c, 0x21, 0 - .dw 0x3340, 0xc13c, 0x337f, 0xc13c, 0x21, 0 - .dw 0x33c0, 0xc13c, 0x33ff, 0xc13c, 0x21, 0 - .dw 0x3440, 0xc13c, 0x347f, 0xc13c, 0x21, 0 - .dw 0x34c0, 0xc13c, 0x34ff, 0xc13c, 0x21, 0 - .dw 0x3540, 0xc13c, 0x357f, 0xc13c, 0x21, 0 - .dw 0x35c0, 0xc13c, 0x35ff, 0xc13c, 0x21, 0 - .dw 0x3640, 0xc13c, 0x367f, 0xc13c, 0x21, 0 - .dw 0x36c0, 0xc13c, 0x36ff, 0xc13c, 0x21, 0 - .dw 0x3740, 0xc13c, 0x377f, 0xc13c, 0x21, 0 - .dw 0x37c0, 0xc13c, 0x37ff, 0xc13c, 0x21, 0 - .dw 0x3840, 0xc13c, 0x387f, 0xc13c, 0x21, 0 - .dw 0x38c0, 0xc13c, 0x38ff, 0xc13c, 0x21, 0 - .dw 0x3940, 0xc13c, 0x397f, 0xc13c, 0x21, 0 - .dw 0x39c0, 0xc13c, 0x3fff, 0xc13c, 0x21, 0 - .dw 0x4040, 0xc13c, 0x407f, 0xc13c, 0x21, 0 - .dw 0x40c0, 0xc13c, 0x40ff, 0xc13c, 0x21, 0 - .dw 0x4140, 0xc13c, 0x417f, 0xc13c, 0x21, 0 - .dw 0x41c0, 0xc13c, 0x41ff, 0xc13c, 0x21, 0 - .dw 0x4240, 0xc13c, 0x427f, 0xc13c, 0x21, 0 - .dw 0x42c0, 0xc13c, 0x42ff, 0xc13c, 0x21, 0 - .dw 0x4340, 0xc13c, 0x437f, 0xc13c, 0x21, 0 - .dw 0x43c0, 0xc13c, 0x43ff, 0xc13c, 0x21, 0 - .dw 0x4440, 0xc13c, 0x447f, 0xc13c, 0x21, 0 - .dw 0x44c0, 0xc13c, 0x44ff, 0xc13c, 0x21, 0 - .dw 0x4540, 0xc13c, 0x457f, 0xc13c, 0x21, 0 - .dw 0x45c0, 0xc13c, 0x45ff, 0xc13c, 0x21, 0 - .dw 0x4640, 0xc13c, 0x467f, 0xc13c, 0x21, 0 - .dw 0x46c0, 0xc13c, 0x46ff, 0xc13c, 0x21, 0 - .dw 0x4740, 0xc13c, 0x477f, 0xc13c, 0x21, 0 - .dw 0x47c0, 0xc13c, 0x47ff, 0xc13c, 0x21, 0 - .dw 0x4840, 0xc13c, 0x487f, 0xc13c, 0x21, 0 - .dw 0x48c0, 0xc13c, 0x48ff, 0xc13c, 0x21, 0 - .dw 0x4940, 0xc13c, 0x497f, 0xc13c, 0x21, 0 - .dw 0x49c0, 0xc13c, 0x49ff, 0xc13c, 0x21, 0 - .dw 0x4a40, 0xc13c, 0x4a7f, 0xc13c, 0x21, 0 - .dw 0x4ac0, 0xc13c, 0x4aff, 0xc13c, 0x21, 0 - .dw 0x4b40, 0xc13c, 0x4b7f, 0xc13c, 0x21, 0 - .dw 0x4bc0, 0xc13c, 0x4bff, 0xc13c, 0x21, 0 - .dw 0x4c40, 0xc13c, 0x4c7f, 0xc13c, 0x21, 0 - .dw 0x4cc0, 0xc13c, 0x4cff, 0xc13c, 0x21, 0 - .dw 0x4d40, 0xc13c, 0x4d7f, 0xc13c, 0x21, 0 - .dw 0x4dc0, 0xc13c, 0x4dff, 0xc13c, 0x21, 0 - .dw 0x4e40, 0xc13c, 0x4e7f, 0xc13c, 0x21, 0 - .dw 0x4ec0, 0xc13c, 0x4eff, 0xc13c, 0x21, 0 - .dw 0x4f40, 0xc13c, 0x4f7f, 0xc13c, 0x21, 0 - .dw 0x4fc0, 0xc13c, 0x4fff, 0xc13c, 0x21, 0 - .dw 0x5040, 0xc13c, 0x507f, 0xc13c, 0x21, 0 - .dw 0x50c0, 0xc13c, 0x50ff, 0xc13c, 0x21, 0 - .dw 0x5140, 0xc13c, 0x517f, 0xc13c, 0x21, 0 - .dw 0x51c0, 0xc13c, 0x51ff, 0xc13c, 0x21, 0 - .dw 0x5240, 0xc13c, 0x527f, 0xc13c, 0x21, 0 - .dw 0x52c0, 0xc13c, 0x52ff, 0xc13c, 0x21, 0 - .dw 0x5340, 0xc13c, 0x537f, 0xc13c, 0x21, 0 - .dw 0x53c0, 0xc13c, 0x53ff, 0xc13c, 0x21, 0 - .dw 0x5440, 0xc13c, 0x547f, 0xc13c, 0x21, 0 - .dw 0x54c0, 0xc13c, 0x54ff, 0xc13c, 0x21, 0 - .dw 0x5540, 0xc13c, 0x557f, 0xc13c, 0x21, 0 - .dw 0x55c0, 0xc13c, 0x55ff, 0xc13c, 0x21, 0 - .dw 0x5640, 0xc13c, 0x567f, 0xc13c, 0x21, 0 - .dw 0x56c0, 0xc13c, 0x56ff, 0xc13c, 0x21, 0 - .dw 0x5740, 0xc13c, 0x577f, 0xc13c, 0x21, 0 - .dw 0x57c0, 0xc13c, 0x57ff, 0xc13c, 0x21, 0 - .dw 0x5840, 0xc13c, 0x587f, 0xc13c, 0x21, 0 - .dw 0x58c0, 0xc13c, 0x58ff, 0xc13c, 0x21, 0 - .dw 0x5940, 0xc13c, 0x597f, 0xc13c, 0x21, 0 - .dw 0x59c0, 0xc13c, 0x5fff, 0xc13c, 0x21, 0 - .dw 0x6040, 0xc13c, 0x607f, 0xc13c, 0x21, 0 - .dw 0x60c0, 0xc13c, 0x60ff, 0xc13c, 0x21, 0 - .dw 0x6140, 0xc13c, 0x617f, 0xc13c, 0x21, 0 - .dw 0x61c0, 0xc13c, 0x61ff, 0xc13c, 0x21, 0 - .dw 0x6240, 0xc13c, 0x627f, 0xc13c, 0x21, 0 - .dw 0x62c0, 0xc13c, 0x62ff, 0xc13c, 0x21, 0 - .dw 0x6340, 0xc13c, 0x637f, 0xc13c, 0x21, 0 - .dw 0x63c0, 0xc13c, 0x63ff, 0xc13c, 0x21, 0 - .dw 0x6440, 0xc13c, 0x647f, 0xc13c, 0x21, 0 - .dw 0x64c0, 0xc13c, 0x64ff, 0xc13c, 0x21, 0 - .dw 0x6540, 0xc13c, 0x657f, 0xc13c, 0x21, 0 - .dw 0x65c0, 0xc13c, 0x65ff, 0xc13c, 0x21, 0 - .dw 0x6640, 0xc13c, 0x667f, 0xc13c, 0x21, 0 - .dw 0x66c0, 0xc13c, 0x66ff, 0xc13c, 0x21, 0 - .dw 0x6740, 0xc13c, 0x677f, 0xc13c, 0x21, 0 - .dw 0x67c0, 0xc13c, 0x67ff, 0xc13c, 0x21, 0 - .dw 0x6840, 0xc13c, 0x687f, 0xc13c, 0x21, 0 - .dw 0x68c0, 0xc13c, 0x68ff, 0xc13c, 0x21, 0 - .dw 0x6940, 0xc13c, 0x697f, 0xc13c, 0x21, 0 - .dw 0x69c0, 0xc13c, 0x69ff, 0xc13c, 0x21, 0 - .dw 0x6a40, 0xc13c, 0x6a7f, 0xc13c, 0x21, 0 - .dw 0x6ac0, 0xc13c, 0x6aff, 0xc13c, 0x21, 0 - .dw 0x6b40, 0xc13c, 0x6b7f, 0xc13c, 0x21, 0 - .dw 0x6bc0, 0xc13c, 0x6bff, 0xc13c, 0x21, 0 - .dw 0x6c40, 0xc13c, 0x6c7f, 0xc13c, 0x21, 0 - .dw 0x6cc0, 0xc13c, 0x6cff, 0xc13c, 0x21, 0 - .dw 0x6d40, 0xc13c, 0x6d7f, 0xc13c, 0x21, 0 - .dw 0x6dc0, 0xc13c, 0x6dff, 0xc13c, 0x21, 0 - .dw 0x6e40, 0xc13c, 0x6e7f, 0xc13c, 0x21, 0 - .dw 0x6ec0, 0xc13c, 0x6eff, 0xc13c, 0x21, 0 - .dw 0x6f40, 0xc13c, 0x6f7f, 0xc13c, 0x21, 0 - .dw 0x6fc0, 0xc13c, 0x6fff, 0xc13c, 0x21, 0 - .dw 0x7040, 0xc13c, 0x707f, 0xc13c, 0x21, 0 - .dw 0x70c0, 0xc13c, 0x70ff, 0xc13c, 0x21, 0 - .dw 0x7140, 0xc13c, 0x717f, 0xc13c, 0x21, 0 - .dw 0x71c0, 0xc13c, 0x71ff, 0xc13c, 0x21, 0 - .dw 0x7240, 0xc13c, 0x727f, 0xc13c, 0x21, 0 - .dw 0x72c0, 0xc13c, 0x72ff, 0xc13c, 0x21, 0 - .dw 0x7340, 0xc13c, 0x737f, 0xc13c, 0x21, 0 - .dw 0x73c0, 0xc13c, 0x73ff, 0xc13c, 0x21, 0 - .dw 0x7440, 0xc13c, 0x747f, 0xc13c, 0x21, 0 - .dw 0x74c0, 0xc13c, 0x74ff, 0xc13c, 0x21, 0 - .dw 0x7540, 0xc13c, 0x757f, 0xc13c, 0x21, 0 - .dw 0x75c0, 0xc13c, 0x75ff, 0xc13c, 0x21, 0 - .dw 0x7640, 0xc13c, 0x767f, 0xc13c, 0x21, 0 - .dw 0x76c0, 0xc13c, 0x76ff, 0xc13c, 0x21, 0 - .dw 0x7740, 0xc13c, 0x777f, 0xc13c, 0x21, 0 - .dw 0x77c0, 0xc13c, 0x77ff, 0xc13c, 0x21, 0 - .dw 0x7840, 0xc13c, 0x787f, 0xc13c, 0x21, 0 - .dw 0x78c0, 0xc13c, 0x78ff, 0xc13c, 0x21, 0 - .dw 0x7940, 0xc13c, 0x797f, 0xc13c, 0x21, 0 - .dw 0x79c0, 0xc13c, 0x7fff, 0xc13c, 0x21, 0 - .dw 0x8040, 0xc13c, 0x807f, 0xc13c, 0x21, 0 - .dw 0x80c0, 0xc13c, 0x80ff, 0xc13c, 0x21, 0 - .dw 0x8140, 0xc13c, 0x817f, 0xc13c, 0x21, 0 - .dw 0x81c0, 0xc13c, 0x81ff, 0xc13c, 0x21, 0 - .dw 0x8240, 0xc13c, 0x827f, 0xc13c, 0x21, 0 - .dw 0x82c0, 0xc13c, 0x82ff, 0xc13c, 0x21, 0 - .dw 0x8340, 0xc13c, 0x837f, 0xc13c, 0x21, 0 - .dw 0x83c0, 0xc13c, 0x83ff, 0xc13c, 0x21, 0 - .dw 0x8440, 0xc13c, 0x847f, 0xc13c, 0x21, 0 - .dw 0x84c0, 0xc13c, 0x84ff, 0xc13c, 0x21, 0 - .dw 0x8540, 0xc13c, 0x857f, 0xc13c, 0x21, 0 - .dw 0x85c0, 0xc13c, 0x85ff, 0xc13c, 0x21, 0 - .dw 0x8640, 0xc13c, 0x867f, 0xc13c, 0x21, 0 - .dw 0x86c0, 0xc13c, 0x86ff, 0xc13c, 0x21, 0 - .dw 0x8740, 0xc13c, 0x877f, 0xc13c, 0x21, 0 - .dw 0x87c0, 0xc13c, 0x87ff, 0xc13c, 0x21, 0 - .dw 0x8840, 0xc13c, 0x887f, 0xc13c, 0x21, 0 - .dw 0x88c0, 0xc13c, 0x88ff, 0xc13c, 0x21, 0 - .dw 0x8940, 0xc13c, 0x897f, 0xc13c, 0x21, 0 - .dw 0x89c0, 0xc13c, 0x89ff, 0xc13c, 0x21, 0 - .dw 0x8a40, 0xc13c, 0x8a7f, 0xc13c, 0x21, 0 - .dw 0x8ac0, 0xc13c, 0x8aff, 0xc13c, 0x21, 0 - .dw 0x8b40, 0xc13c, 0x8b7f, 0xc13c, 0x21, 0 - .dw 0x8bc0, 0xc13c, 0x8bff, 0xc13c, 0x21, 0 - .dw 0x8c40, 0xc13c, 0x8c7f, 0xc13c, 0x21, 0 - .dw 0x8cc0, 0xc13c, 0x8cff, 0xc13c, 0x21, 0 - .dw 0x8d40, 0xc13c, 0x8d7f, 0xc13c, 0x21, 0 - .dw 0x8dc0, 0xc13c, 0x8dff, 0xc13c, 0x21, 0 - .dw 0x8e40, 0xc13c, 0x8e7f, 0xc13c, 0x21, 0 - .dw 0x8ec0, 0xc13c, 0x8eff, 0xc13c, 0x21, 0 - .dw 0x8f40, 0xc13c, 0x8f7f, 0xc13c, 0x21, 0 - .dw 0x8fc0, 0xc13c, 0x8fff, 0xc13c, 0x21, 0 - .dw 0x9040, 0xc13c, 0x907f, 0xc13c, 0x21, 0 - .dw 0x90c0, 0xc13c, 0x90ff, 0xc13c, 0x21, 0 - .dw 0x9140, 0xc13c, 0x917f, 0xc13c, 0x21, 0 - .dw 0x91c0, 0xc13c, 0x91ff, 0xc13c, 0x21, 0 - .dw 0x9240, 0xc13c, 0x927f, 0xc13c, 0x21, 0 - .dw 0x92c0, 0xc13c, 0x92ff, 0xc13c, 0x21, 0 - .dw 0x9340, 0xc13c, 0x937f, 0xc13c, 0x21, 0 - .dw 0x93c0, 0xc13c, 0x93ff, 0xc13c, 0x21, 0 - .dw 0x9440, 0xc13c, 0x947f, 0xc13c, 0x21, 0 - .dw 0x94c0, 0xc13c, 0x94ff, 0xc13c, 0x21, 0 - .dw 0x9540, 0xc13c, 0x957f, 0xc13c, 0x21, 0 - .dw 0x95c0, 0xc13c, 0x95ff, 0xc13c, 0x21, 0 - .dw 0x9640, 0xc13c, 0x967f, 0xc13c, 0x21, 0 - .dw 0x96c0, 0xc13c, 0x96ff, 0xc13c, 0x21, 0 - .dw 0x9740, 0xc13c, 0x977f, 0xc13c, 0x21, 0 - .dw 0x97c0, 0xc13c, 0x97ff, 0xc13c, 0x21, 0 - .dw 0x9840, 0xc13c, 0x987f, 0xc13c, 0x21, 0 - .dw 0x98c0, 0xc13c, 0x98ff, 0xc13c, 0x21, 0 - .dw 0x9940, 0xc13c, 0x997f, 0xc13c, 0x21, 0 - .dw 0x99c0, 0xc13c, 0x9fff, 0xc13c, 0x21, 0 - .dw 0xa040, 0xc13c, 0xa07f, 0xc13c, 0x21, 0 - .dw 0xa0c0, 0xc13c, 0xa0ff, 0xc13c, 0x21, 0 - .dw 0xa140, 0xc13c, 0xa17f, 0xc13c, 0x21, 0 - .dw 0xa1c0, 0xc13c, 0xa1ff, 0xc13c, 0x21, 0 - .dw 0xa240, 0xc13c, 0xa27f, 0xc13c, 0x21, 0 - .dw 0xa2c0, 0xc13c, 0xa2ff, 0xc13c, 0x21, 0 - .dw 0xa340, 0xc13c, 0xa37f, 0xc13c, 0x21, 0 - .dw 0xa3c0, 0xc13c, 0xa3ff, 0xc13c, 0x21, 0 - .dw 0xa440, 0xc13c, 0xa47f, 0xc13c, 0x21, 0 - .dw 0xa4c0, 0xc13c, 0xa4ff, 0xc13c, 0x21, 0 - .dw 0xa540, 0xc13c, 0xa57f, 0xc13c, 0x21, 0 - .dw 0xa5c0, 0xc13c, 0xa5ff, 0xc13c, 0x21, 0 - .dw 0xa640, 0xc13c, 0xa67f, 0xc13c, 0x21, 0 - .dw 0xa6c0, 0xc13c, 0xa6ff, 0xc13c, 0x21, 0 - .dw 0xa740, 0xc13c, 0xa77f, 0xc13c, 0x21, 0 - .dw 0xa7c0, 0xc13c, 0xa7ff, 0xc13c, 0x21, 0 - .dw 0xa840, 0xc13c, 0xa87f, 0xc13c, 0x21, 0 - .dw 0xa8c0, 0xc13c, 0xa8ff, 0xc13c, 0x21, 0 - .dw 0xa940, 0xc13c, 0xa97f, 0xc13c, 0x21, 0 - .dw 0xa9c0, 0xc13c, 0xa9ff, 0xc13c, 0x21, 0 - .dw 0xaa40, 0xc13c, 0xaa7f, 0xc13c, 0x21, 0 - .dw 0xaac0, 0xc13c, 0xaaff, 0xc13c, 0x21, 0 - .dw 0xab40, 0xc13c, 0xab7f, 0xc13c, 0x21, 0 - .dw 0xabc0, 0xc13c, 0xabff, 0xc13c, 0x21, 0 - .dw 0xac40, 0xc13c, 0xac7f, 0xc13c, 0x21, 0 - .dw 0xacc0, 0xc13c, 0xacff, 0xc13c, 0x21, 0 - .dw 0xad40, 0xc13c, 0xad7f, 0xc13c, 0x21, 0 - .dw 0xadc0, 0xc13c, 0xadff, 0xc13c, 0x21, 0 - .dw 0xae40, 0xc13c, 0xae7f, 0xc13c, 0x21, 0 - .dw 0xaec0, 0xc13c, 0xaeff, 0xc13c, 0x21, 0 - .dw 0xaf40, 0xc13c, 0xaf7f, 0xc13c, 0x21, 0 - .dw 0xafc0, 0xc13c, 0xafff, 0xc13c, 0x21, 0 - .dw 0xb040, 0xc13c, 0xb07f, 0xc13c, 0x21, 0 - .dw 0xb0c0, 0xc13c, 0xb0ff, 0xc13c, 0x21, 0 - .dw 0xb140, 0xc13c, 0xb17f, 0xc13c, 0x21, 0 - .dw 0xb1c0, 0xc13c, 0xb1ff, 0xc13c, 0x21, 0 - .dw 0xb240, 0xc13c, 0xb27f, 0xc13c, 0x21, 0 - .dw 0xb2c0, 0xc13c, 0xb2ff, 0xc13c, 0x21, 0 - .dw 0xb340, 0xc13c, 0xb37f, 0xc13c, 0x21, 0 - .dw 0xb3c0, 0xc13c, 0xb3ff, 0xc13c, 0x21, 0 - .dw 0xb440, 0xc13c, 0xb47f, 0xc13c, 0x21, 0 - .dw 0xb4c0, 0xc13c, 0xb4ff, 0xc13c, 0x21, 0 - .dw 0xb540, 0xc13c, 0xb57f, 0xc13c, 0x21, 0 - .dw 0xb5c0, 0xc13c, 0xb5ff, 0xc13c, 0x21, 0 - .dw 0xb640, 0xc13c, 0xb67f, 0xc13c, 0x21, 0 - .dw 0xb6c0, 0xc13c, 0xb6ff, 0xc13c, 0x21, 0 - .dw 0xb740, 0xc13c, 0xb77f, 0xc13c, 0x21, 0 - .dw 0xb7c0, 0xc13c, 0xb7ff, 0xc13c, 0x21, 0 - .dw 0xb840, 0xc13c, 0xb87f, 0xc13c, 0x21, 0 - .dw 0xb8c0, 0xc13c, 0xb8ff, 0xc13c, 0x21, 0 - .dw 0xb940, 0xc13c, 0xb97f, 0xc13c, 0x21, 0 - .dw 0xb9c0, 0xc13c, 0xbfff, 0xc13c, 0x21, 0 - .dw 0xc040, 0xc13c, 0xc07f, 0xc13c, 0x21, 0 - .dw 0xc0c0, 0xc13c, 0xc0ff, 0xc13c, 0x21, 0 - .dw 0xc140, 0xc13c, 0xc17f, 0xc13c, 0x21, 0 - .dw 0xc1c0, 0xc13c, 0xc1ff, 0xc13c, 0x21, 0 - .dw 0xc240, 0xc13c, 0xc27f, 0xc13c, 0x21, 0 - .dw 0xc2c0, 0xc13c, 0xc2ff, 0xc13c, 0x21, 0 - .dw 0xc340, 0xc13c, 0xc37f, 0xc13c, 0x21, 0 - .dw 0xc3c0, 0xc13c, 0xc3ff, 0xc13c, 0x21, 0 - .dw 0xc440, 0xc13c, 0xc47f, 0xc13c, 0x21, 0 - .dw 0xc4c0, 0xc13c, 0xc4ff, 0xc13c, 0x21, 0 - .dw 0xc540, 0xc13c, 0xc57f, 0xc13c, 0x21, 0 - .dw 0xc5c0, 0xc13c, 0xc5ff, 0xc13c, 0x21, 0 - .dw 0xc640, 0xc13c, 0xc67f, 0xc13c, 0x21, 0 - .dw 0xc6c0, 0xc13c, 0xc6ff, 0xc13c, 0x21, 0 - .dw 0xc740, 0xc13c, 0xc77f, 0xc13c, 0x21, 0 - .dw 0xc7c0, 0xc13c, 0xc7ff, 0xc13c, 0x21, 0 - .dw 0xc840, 0xc13c, 0xc87f, 0xc13c, 0x21, 0 - .dw 0xc8c0, 0xc13c, 0xc8ff, 0xc13c, 0x21, 0 - .dw 0xc940, 0xc13c, 0xc97f, 0xc13c, 0x21, 0 - .dw 0xc9c0, 0xc13c, 0xc9ff, 0xc13c, 0x21, 0 - .dw 0xca40, 0xc13c, 0xca7f, 0xc13c, 0x21, 0 - .dw 0xcac0, 0xc13c, 0xcaff, 0xc13c, 0x21, 0 - .dw 0xcb40, 0xc13c, 0xcb7f, 0xc13c, 0x21, 0 - .dw 0xcbc0, 0xc13c, 0xcbff, 0xc13c, 0x21, 0 - .dw 0xcc40, 0xc13c, 0xcc7f, 0xc13c, 0x21, 0 - .dw 0xccc0, 0xc13c, 0xccff, 0xc13c, 0x21, 0 - .dw 0xcd40, 0xc13c, 0xcd7f, 0xc13c, 0x21, 0 - .dw 0xcdc0, 0xc13c, 0xcdff, 0xc13c, 0x21, 0 - .dw 0xce40, 0xc13c, 0xce7f, 0xc13c, 0x21, 0 - .dw 0xcec0, 0xc13c, 0xceff, 0xc13c, 0x21, 0 - .dw 0xcf40, 0xc13c, 0xcf7f, 0xc13c, 0x21, 0 - .dw 0xcfc0, 0xc13c, 0xcfff, 0xc13c, 0x21, 0 - .dw 0xd040, 0xc13c, 0xd07f, 0xc13c, 0x21, 0 - .dw 0xd0c0, 0xc13c, 0xd0ff, 0xc13c, 0x21, 0 - .dw 0xd140, 0xc13c, 0xd17f, 0xc13c, 0x21, 0 - .dw 0xd1c0, 0xc13c, 0xd1ff, 0xc13c, 0x21, 0 - .dw 0xd240, 0xc13c, 0xd27f, 0xc13c, 0x21, 0 - .dw 0xd2c0, 0xc13c, 0xd2ff, 0xc13c, 0x21, 0 - .dw 0xd340, 0xc13c, 0xd37f, 0xc13c, 0x21, 0 - .dw 0xd3c0, 0xc13c, 0xd3ff, 0xc13c, 0x21, 0 - .dw 0xd440, 0xc13c, 0xd47f, 0xc13c, 0x21, 0 - .dw 0xd4c0, 0xc13c, 0xd4ff, 0xc13c, 0x21, 0 - .dw 0xd540, 0xc13c, 0xd57f, 0xc13c, 0x21, 0 - .dw 0xd5c0, 0xc13c, 0xd5ff, 0xc13c, 0x21, 0 - .dw 0xd640, 0xc13c, 0xd67f, 0xc13c, 0x21, 0 - .dw 0xd6c0, 0xc13c, 0xd6ff, 0xc13c, 0x21, 0 - .dw 0xd740, 0xc13c, 0xd77f, 0xc13c, 0x21, 0 - .dw 0xd7c0, 0xc13c, 0xd7ff, 0xc13c, 0x21, 0 - .dw 0xd840, 0xc13c, 0xd87f, 0xc13c, 0x21, 0 - .dw 0xd8c0, 0xc13c, 0xd8ff, 0xc13c, 0x21, 0 - .dw 0xd940, 0xc13c, 0xd97f, 0xc13c, 0x21, 0 - .dw 0xd9c0, 0xc13c, 0xdfff, 0xc13c, 0x21, 0 - .dw 0xe040, 0xc13c, 0xe07f, 0xc13c, 0x21, 0 - .dw 0xe0c0, 0xc13c, 0xe0ff, 0xc13c, 0x21, 0 - .dw 0xe140, 0xc13c, 0xe17f, 0xc13c, 0x21, 0 - .dw 0xe1c0, 0xc13c, 0xe1ff, 0xc13c, 0x21, 0 - .dw 0xe240, 0xc13c, 0xe27f, 0xc13c, 0x21, 0 - .dw 0xe2c0, 0xc13c, 0xe2ff, 0xc13c, 0x21, 0 - .dw 0xe340, 0xc13c, 0xe37f, 0xc13c, 0x21, 0 - .dw 0xe3c0, 0xc13c, 0xe3ff, 0xc13c, 0x21, 0 - .dw 0xe440, 0xc13c, 0xe47f, 0xc13c, 0x21, 0 - .dw 0xe4c0, 0xc13c, 0xe4ff, 0xc13c, 0x21, 0 - .dw 0xe540, 0xc13c, 0xe57f, 0xc13c, 0x21, 0 - .dw 0xe5c0, 0xc13c, 0xe5ff, 0xc13c, 0x21, 0 - .dw 0xe640, 0xc13c, 0xe67f, 0xc13c, 0x21, 0 - .dw 0xe6c0, 0xc13c, 0xe6ff, 0xc13c, 0x21, 0 - .dw 0xe740, 0xc13c, 0xe77f, 0xc13c, 0x21, 0 - .dw 0xe7c0, 0xc13c, 0xe7ff, 0xc13c, 0x21, 0 - .dw 0xe840, 0xc13c, 0xe87f, 0xc13c, 0x21, 0 - .dw 0xe8c0, 0xc13c, 0xe8ff, 0xc13c, 0x21, 0 - .dw 0xe940, 0xc13c, 0xe97f, 0xc13c, 0x21, 0 - .dw 0xe9c0, 0xc13c, 0xe9ff, 0xc13c, 0x21, 0 - .dw 0xea40, 0xc13c, 0xea7f, 0xc13c, 0x21, 0 - .dw 0xeac0, 0xc13c, 0xeaff, 0xc13c, 0x21, 0 - .dw 0xeb40, 0xc13c, 0xeb7f, 0xc13c, 0x21, 0 - .dw 0xebc0, 0xc13c, 0xebff, 0xc13c, 0x21, 0 - .dw 0xec40, 0xc13c, 0xec7f, 0xc13c, 0x21, 0 - .dw 0xecc0, 0xc13c, 0xecff, 0xc13c, 0x21, 0 - .dw 0xed40, 0xc13c, 0xed7f, 0xc13c, 0x21, 0 - .dw 0xedc0, 0xc13c, 0xedff, 0xc13c, 0x21, 0 - .dw 0xee40, 0xc13c, 0xee7f, 0xc13c, 0x21, 0 - .dw 0xeec0, 0xc13c, 0xeeff, 0xc13c, 0x21, 0 - .dw 0xef40, 0xc13c, 0xef7f, 0xc13c, 0x21, 0 - .dw 0xefc0, 0xc13c, 0xefff, 0xc13c, 0x21, 0 - .dw 0xf040, 0xc13c, 0xf07f, 0xc13c, 0x21, 0 - .dw 0xf0c0, 0xc13c, 0xf0ff, 0xc13c, 0x21, 0 - .dw 0xf140, 0xc13c, 0xf17f, 0xc13c, 0x21, 0 - .dw 0xf1c0, 0xc13c, 0xf1ff, 0xc13c, 0x21, 0 - .dw 0xf240, 0xc13c, 0xf27f, 0xc13c, 0x21, 0 - .dw 0xf2c0, 0xc13c, 0xf2ff, 0xc13c, 0x21, 0 - .dw 0xf340, 0xc13c, 0xf37f, 0xc13c, 0x21, 0 - .dw 0xf3c0, 0xc13c, 0xf3ff, 0xc13c, 0x21, 0 - .dw 0xf440, 0xc13c, 0xf47f, 0xc13c, 0x21, 0 - .dw 0xf4c0, 0xc13c, 0xf4ff, 0xc13c, 0x21, 0 - .dw 0xf540, 0xc13c, 0xf57f, 0xc13c, 0x21, 0 - .dw 0xf5c0, 0xc13c, 0xf5ff, 0xc13c, 0x21, 0 - .dw 0xf640, 0xc13c, 0xf67f, 0xc13c, 0x21, 0 - .dw 0xf6c0, 0xc13c, 0xf6ff, 0xc13c, 0x21, 0 - .dw 0xf740, 0xc13c, 0xf77f, 0xc13c, 0x21, 0 - .dw 0xf7c0, 0xc13c, 0xf7ff, 0xc13c, 0x21, 0 - .dw 0xf840, 0xc13c, 0xf87f, 0xc13c, 0x21, 0 - .dw 0xf8c0, 0xc13c, 0xf8ff, 0xc13c, 0x21, 0 - .dw 0xf940, 0xc13c, 0xf97f, 0xc13c, 0x21, 0 - .dw 0xf9c0, 0xc13c, 0xffff, 0xc13c, 0x21, 0 - .dw 0x0040, 0xc13d, 0x007f, 0xc13d, 0x21, 0 - .dw 0x00c0, 0xc13d, 0x00ff, 0xc13d, 0x21, 0 - .dw 0x0140, 0xc13d, 0x017f, 0xc13d, 0x21, 0 - .dw 0x01c0, 0xc13d, 0x01ff, 0xc13d, 0x21, 0 - .dw 0x0240, 0xc13d, 0x027f, 0xc13d, 0x21, 0 - .dw 0x02c0, 0xc13d, 0x02ff, 0xc13d, 0x21, 0 - .dw 0x0340, 0xc13d, 0x037f, 0xc13d, 0x21, 0 - .dw 0x03c0, 0xc13d, 0x03ff, 0xc13d, 0x21, 0 - .dw 0x0440, 0xc13d, 0x047f, 0xc13d, 0x21, 0 - .dw 0x04c0, 0xc13d, 0x04ff, 0xc13d, 0x21, 0 - .dw 0x0540, 0xc13d, 0x057f, 0xc13d, 0x21, 0 - .dw 0x05c0, 0xc13d, 0x05ff, 0xc13d, 0x21, 0 - .dw 0x0640, 0xc13d, 0x067f, 0xc13d, 0x21, 0 - .dw 0x06c0, 0xc13d, 0x06ff, 0xc13d, 0x21, 0 - .dw 0x0740, 0xc13d, 0x077f, 0xc13d, 0x21, 0 - .dw 0x07c0, 0xc13d, 0x07ff, 0xc13d, 0x21, 0 - .dw 0x0840, 0xc13d, 0x087f, 0xc13d, 0x21, 0 - .dw 0x08c0, 0xc13d, 0x08ff, 0xc13d, 0x21, 0 - .dw 0x0940, 0xc13d, 0x097f, 0xc13d, 0x21, 0 - .dw 0x09c0, 0xc13d, 0x09ff, 0xc13d, 0x21, 0 - .dw 0x0a40, 0xc13d, 0x0a7f, 0xc13d, 0x21, 0 - .dw 0x0ac0, 0xc13d, 0x0aff, 0xc13d, 0x21, 0 - .dw 0x0b40, 0xc13d, 0x0b7f, 0xc13d, 0x21, 0 - .dw 0x0bc0, 0xc13d, 0x0bff, 0xc13d, 0x21, 0 - .dw 0x0c40, 0xc13d, 0x0c7f, 0xc13d, 0x21, 0 - .dw 0x0cc0, 0xc13d, 0x0cff, 0xc13d, 0x21, 0 - .dw 0x0d40, 0xc13d, 0x0d7f, 0xc13d, 0x21, 0 - .dw 0x0dc0, 0xc13d, 0x0dff, 0xc13d, 0x21, 0 - .dw 0x0e40, 0xc13d, 0x0e7f, 0xc13d, 0x21, 0 - .dw 0x0ec0, 0xc13d, 0x0eff, 0xc13d, 0x21, 0 - .dw 0x0f40, 0xc13d, 0x0f7f, 0xc13d, 0x21, 0 - .dw 0x0fc0, 0xc13d, 0x0fff, 0xc13d, 0x21, 0 - .dw 0x1040, 0xc13d, 0x107f, 0xc13d, 0x21, 0 - .dw 0x10c0, 0xc13d, 0x10ff, 0xc13d, 0x21, 0 - .dw 0x1140, 0xc13d, 0x117f, 0xc13d, 0x21, 0 - .dw 0x11c0, 0xc13d, 0x11ff, 0xc13d, 0x21, 0 - .dw 0x1240, 0xc13d, 0x127f, 0xc13d, 0x21, 0 - .dw 0x12c0, 0xc13d, 0x12ff, 0xc13d, 0x21, 0 - .dw 0x1340, 0xc13d, 0x137f, 0xc13d, 0x21, 0 - .dw 0x13c0, 0xc13d, 0x13ff, 0xc13d, 0x21, 0 - .dw 0x1440, 0xc13d, 0x147f, 0xc13d, 0x21, 0 - .dw 0x14c0, 0xc13d, 0x14ff, 0xc13d, 0x21, 0 - .dw 0x1540, 0xc13d, 0x157f, 0xc13d, 0x21, 0 - .dw 0x15c0, 0xc13d, 0x15ff, 0xc13d, 0x21, 0 - .dw 0x1640, 0xc13d, 0x167f, 0xc13d, 0x21, 0 - .dw 0x16c0, 0xc13d, 0x16ff, 0xc13d, 0x21, 0 - .dw 0x1740, 0xc13d, 0x177f, 0xc13d, 0x21, 0 - .dw 0x17c0, 0xc13d, 0x17ff, 0xc13d, 0x21, 0 - .dw 0x1840, 0xc13d, 0x187f, 0xc13d, 0x21, 0 - .dw 0x18c0, 0xc13d, 0x18ff, 0xc13d, 0x21, 0 - .dw 0x1940, 0xc13d, 0x197f, 0xc13d, 0x21, 0 - .dw 0x19c0, 0xc13d, 0x1fff, 0xc13d, 0x21, 0 - .dw 0x2040, 0xc13d, 0x207f, 0xc13d, 0x21, 0 - .dw 0x20c0, 0xc13d, 0x20ff, 0xc13d, 0x21, 0 - .dw 0x2140, 0xc13d, 0x217f, 0xc13d, 0x21, 0 - .dw 0x21c0, 0xc13d, 0x21ff, 0xc13d, 0x21, 0 - .dw 0x2240, 0xc13d, 0x227f, 0xc13d, 0x21, 0 - .dw 0x22c0, 0xc13d, 0x22ff, 0xc13d, 0x21, 0 - .dw 0x2340, 0xc13d, 0x237f, 0xc13d, 0x21, 0 - .dw 0x23c0, 0xc13d, 0x23ff, 0xc13d, 0x21, 0 - .dw 0x2440, 0xc13d, 0x247f, 0xc13d, 0x21, 0 - .dw 0x24c0, 0xc13d, 0x24ff, 0xc13d, 0x21, 0 - .dw 0x2540, 0xc13d, 0x257f, 0xc13d, 0x21, 0 - .dw 0x25c0, 0xc13d, 0x25ff, 0xc13d, 0x21, 0 - .dw 0x2640, 0xc13d, 0x267f, 0xc13d, 0x21, 0 - .dw 0x26c0, 0xc13d, 0x26ff, 0xc13d, 0x21, 0 - .dw 0x2740, 0xc13d, 0x277f, 0xc13d, 0x21, 0 - .dw 0x27c0, 0xc13d, 0x27ff, 0xc13d, 0x21, 0 - .dw 0x2840, 0xc13d, 0x287f, 0xc13d, 0x21, 0 - .dw 0x28c0, 0xc13d, 0x28ff, 0xc13d, 0x21, 0 - .dw 0x2940, 0xc13d, 0x297f, 0xc13d, 0x21, 0 - .dw 0x29c0, 0xc13d, 0x29ff, 0xc13d, 0x21, 0 - .dw 0x2a40, 0xc13d, 0x2a7f, 0xc13d, 0x21, 0 - .dw 0x2ac0, 0xc13d, 0x2aff, 0xc13d, 0x21, 0 - .dw 0x2b40, 0xc13d, 0x2b7f, 0xc13d, 0x21, 0 - .dw 0x2bc0, 0xc13d, 0x2bff, 0xc13d, 0x21, 0 - .dw 0x2c40, 0xc13d, 0x2c7f, 0xc13d, 0x21, 0 - .dw 0x2cc0, 0xc13d, 0x2cff, 0xc13d, 0x21, 0 - .dw 0x2d40, 0xc13d, 0x2d7f, 0xc13d, 0x21, 0 - .dw 0x2dc0, 0xc13d, 0x2dff, 0xc13d, 0x21, 0 - .dw 0x2e40, 0xc13d, 0x2e7f, 0xc13d, 0x21, 0 - .dw 0x2ec0, 0xc13d, 0x2eff, 0xc13d, 0x21, 0 - .dw 0x2f40, 0xc13d, 0x2f7f, 0xc13d, 0x21, 0 - .dw 0x2fc0, 0xc13d, 0x2fff, 0xc13d, 0x21, 0 - .dw 0x3040, 0xc13d, 0x307f, 0xc13d, 0x21, 0 - .dw 0x30c0, 0xc13d, 0x30ff, 0xc13d, 0x21, 0 - .dw 0x3140, 0xc13d, 0x317f, 0xc13d, 0x21, 0 - .dw 0x31c0, 0xc13d, 0x31ff, 0xc13d, 0x21, 0 - .dw 0x3240, 0xc13d, 0x327f, 0xc13d, 0x21, 0 - .dw 0x32c0, 0xc13d, 0x32ff, 0xc13d, 0x21, 0 - .dw 0x3340, 0xc13d, 0x337f, 0xc13d, 0x21, 0 - .dw 0x33c0, 0xc13d, 0x33ff, 0xc13d, 0x21, 0 - .dw 0x3440, 0xc13d, 0x347f, 0xc13d, 0x21, 0 - .dw 0x34c0, 0xc13d, 0x34ff, 0xc13d, 0x21, 0 - .dw 0x3540, 0xc13d, 0x357f, 0xc13d, 0x21, 0 - .dw 0x35c0, 0xc13d, 0x35ff, 0xc13d, 0x21, 0 - .dw 0x3640, 0xc13d, 0x367f, 0xc13d, 0x21, 0 - .dw 0x36c0, 0xc13d, 0x36ff, 0xc13d, 0x21, 0 - .dw 0x3740, 0xc13d, 0x377f, 0xc13d, 0x21, 0 - .dw 0x37c0, 0xc13d, 0x37ff, 0xc13d, 0x21, 0 - .dw 0x3840, 0xc13d, 0x387f, 0xc13d, 0x21, 0 - .dw 0x38c0, 0xc13d, 0x38ff, 0xc13d, 0x21, 0 - .dw 0x3940, 0xc13d, 0x397f, 0xc13d, 0x21, 0 - .dw 0x39c0, 0xc13d, 0x3fff, 0xc13d, 0x21, 0 - .dw 0x4040, 0xc13d, 0x407f, 0xc13d, 0x21, 0 - .dw 0x40c0, 0xc13d, 0x40ff, 0xc13d, 0x21, 0 - .dw 0x4140, 0xc13d, 0x417f, 0xc13d, 0x21, 0 - .dw 0x41c0, 0xc13d, 0x41ff, 0xc13d, 0x21, 0 - .dw 0x4240, 0xc13d, 0x427f, 0xc13d, 0x21, 0 - .dw 0x42c0, 0xc13d, 0x42ff, 0xc13d, 0x21, 0 - .dw 0x4340, 0xc13d, 0x437f, 0xc13d, 0x21, 0 - .dw 0x43c0, 0xc13d, 0x43ff, 0xc13d, 0x21, 0 - .dw 0x4440, 0xc13d, 0x447f, 0xc13d, 0x21, 0 - .dw 0x44c0, 0xc13d, 0x44ff, 0xc13d, 0x21, 0 - .dw 0x4540, 0xc13d, 0x457f, 0xc13d, 0x21, 0 - .dw 0x45c0, 0xc13d, 0x45ff, 0xc13d, 0x21, 0 - .dw 0x4640, 0xc13d, 0x467f, 0xc13d, 0x21, 0 - .dw 0x46c0, 0xc13d, 0x46ff, 0xc13d, 0x21, 0 - .dw 0x4740, 0xc13d, 0x477f, 0xc13d, 0x21, 0 - .dw 0x47c0, 0xc13d, 0x47ff, 0xc13d, 0x21, 0 - .dw 0x4840, 0xc13d, 0x487f, 0xc13d, 0x21, 0 - .dw 0x48c0, 0xc13d, 0x48ff, 0xc13d, 0x21, 0 - .dw 0x4940, 0xc13d, 0x497f, 0xc13d, 0x21, 0 - .dw 0x49c0, 0xc13d, 0x49ff, 0xc13d, 0x21, 0 - .dw 0x4a40, 0xc13d, 0x4a7f, 0xc13d, 0x21, 0 - .dw 0x4ac0, 0xc13d, 0x4aff, 0xc13d, 0x21, 0 - .dw 0x4b40, 0xc13d, 0x4b7f, 0xc13d, 0x21, 0 - .dw 0x4bc0, 0xc13d, 0x4bff, 0xc13d, 0x21, 0 - .dw 0x4c40, 0xc13d, 0x4c7f, 0xc13d, 0x21, 0 - .dw 0x4cc0, 0xc13d, 0x4cff, 0xc13d, 0x21, 0 - .dw 0x4d40, 0xc13d, 0x4d7f, 0xc13d, 0x21, 0 - .dw 0x4dc0, 0xc13d, 0x4dff, 0xc13d, 0x21, 0 - .dw 0x4e40, 0xc13d, 0x4e7f, 0xc13d, 0x21, 0 - .dw 0x4ec0, 0xc13d, 0x4eff, 0xc13d, 0x21, 0 - .dw 0x4f40, 0xc13d, 0x4f7f, 0xc13d, 0x21, 0 - .dw 0x4fc0, 0xc13d, 0x4fff, 0xc13d, 0x21, 0 - .dw 0x5040, 0xc13d, 0x507f, 0xc13d, 0x21, 0 - .dw 0x50c0, 0xc13d, 0x50ff, 0xc13d, 0x21, 0 - .dw 0x5140, 0xc13d, 0x517f, 0xc13d, 0x21, 0 - .dw 0x51c0, 0xc13d, 0x51ff, 0xc13d, 0x21, 0 - .dw 0x5240, 0xc13d, 0x527f, 0xc13d, 0x21, 0 - .dw 0x52c0, 0xc13d, 0x52ff, 0xc13d, 0x21, 0 - .dw 0x5340, 0xc13d, 0x537f, 0xc13d, 0x21, 0 - .dw 0x53c0, 0xc13d, 0x53ff, 0xc13d, 0x21, 0 - .dw 0x5440, 0xc13d, 0x547f, 0xc13d, 0x21, 0 - .dw 0x54c0, 0xc13d, 0x54ff, 0xc13d, 0x21, 0 - .dw 0x5540, 0xc13d, 0x557f, 0xc13d, 0x21, 0 - .dw 0x55c0, 0xc13d, 0x55ff, 0xc13d, 0x21, 0 - .dw 0x5640, 0xc13d, 0x567f, 0xc13d, 0x21, 0 - .dw 0x56c0, 0xc13d, 0x56ff, 0xc13d, 0x21, 0 - .dw 0x5740, 0xc13d, 0x577f, 0xc13d, 0x21, 0 - .dw 0x57c0, 0xc13d, 0x57ff, 0xc13d, 0x21, 0 - .dw 0x5840, 0xc13d, 0x587f, 0xc13d, 0x21, 0 - .dw 0x58c0, 0xc13d, 0x58ff, 0xc13d, 0x21, 0 - .dw 0x5940, 0xc13d, 0x597f, 0xc13d, 0x21, 0 - .dw 0x59c0, 0xc13d, 0x5fff, 0xc13d, 0x21, 0 - .dw 0x6040, 0xc13d, 0x607f, 0xc13d, 0x21, 0 - .dw 0x60c0, 0xc13d, 0x60ff, 0xc13d, 0x21, 0 - .dw 0x6140, 0xc13d, 0x617f, 0xc13d, 0x21, 0 - .dw 0x61c0, 0xc13d, 0x61ff, 0xc13d, 0x21, 0 - .dw 0x6240, 0xc13d, 0x627f, 0xc13d, 0x21, 0 - .dw 0x62c0, 0xc13d, 0x62ff, 0xc13d, 0x21, 0 - .dw 0x6340, 0xc13d, 0x637f, 0xc13d, 0x21, 0 - .dw 0x63c0, 0xc13d, 0x63ff, 0xc13d, 0x21, 0 - .dw 0x6440, 0xc13d, 0x647f, 0xc13d, 0x21, 0 - .dw 0x64c0, 0xc13d, 0x64ff, 0xc13d, 0x21, 0 - .dw 0x6540, 0xc13d, 0x657f, 0xc13d, 0x21, 0 - .dw 0x65c0, 0xc13d, 0x65ff, 0xc13d, 0x21, 0 - .dw 0x6640, 0xc13d, 0x667f, 0xc13d, 0x21, 0 - .dw 0x66c0, 0xc13d, 0x66ff, 0xc13d, 0x21, 0 - .dw 0x6740, 0xc13d, 0x677f, 0xc13d, 0x21, 0 - .dw 0x67c0, 0xc13d, 0x67ff, 0xc13d, 0x21, 0 - .dw 0x6840, 0xc13d, 0x687f, 0xc13d, 0x21, 0 - .dw 0x68c0, 0xc13d, 0x68ff, 0xc13d, 0x21, 0 - .dw 0x6940, 0xc13d, 0x697f, 0xc13d, 0x21, 0 - .dw 0x69c0, 0xc13d, 0x69ff, 0xc13d, 0x21, 0 - .dw 0x6a40, 0xc13d, 0x6a7f, 0xc13d, 0x21, 0 - .dw 0x6ac0, 0xc13d, 0x6aff, 0xc13d, 0x21, 0 - .dw 0x6b40, 0xc13d, 0x6b7f, 0xc13d, 0x21, 0 - .dw 0x6bc0, 0xc13d, 0x6bff, 0xc13d, 0x21, 0 - .dw 0x6c40, 0xc13d, 0x6c7f, 0xc13d, 0x21, 0 - .dw 0x6cc0, 0xc13d, 0x6cff, 0xc13d, 0x21, 0 - .dw 0x6d40, 0xc13d, 0x6d7f, 0xc13d, 0x21, 0 - .dw 0x6dc0, 0xc13d, 0x6dff, 0xc13d, 0x21, 0 - .dw 0x6e40, 0xc13d, 0x6e7f, 0xc13d, 0x21, 0 - .dw 0x6ec0, 0xc13d, 0x6eff, 0xc13d, 0x21, 0 - .dw 0x6f40, 0xc13d, 0x6f7f, 0xc13d, 0x21, 0 - .dw 0x6fc0, 0xc13d, 0x6fff, 0xc13d, 0x21, 0 - .dw 0x7040, 0xc13d, 0x707f, 0xc13d, 0x21, 0 - .dw 0x70c0, 0xc13d, 0x70ff, 0xc13d, 0x21, 0 - .dw 0x7140, 0xc13d, 0x717f, 0xc13d, 0x21, 0 - .dw 0x71c0, 0xc13d, 0x71ff, 0xc13d, 0x21, 0 - .dw 0x7240, 0xc13d, 0x727f, 0xc13d, 0x21, 0 - .dw 0x72c0, 0xc13d, 0x72ff, 0xc13d, 0x21, 0 - .dw 0x7340, 0xc13d, 0x737f, 0xc13d, 0x21, 0 - .dw 0x73c0, 0xc13d, 0x73ff, 0xc13d, 0x21, 0 - .dw 0x7440, 0xc13d, 0x747f, 0xc13d, 0x21, 0 - .dw 0x74c0, 0xc13d, 0x74ff, 0xc13d, 0x21, 0 - .dw 0x7540, 0xc13d, 0x757f, 0xc13d, 0x21, 0 - .dw 0x75c0, 0xc13d, 0x75ff, 0xc13d, 0x21, 0 - .dw 0x7640, 0xc13d, 0x767f, 0xc13d, 0x21, 0 - .dw 0x76c0, 0xc13d, 0x76ff, 0xc13d, 0x21, 0 - .dw 0x7740, 0xc13d, 0x777f, 0xc13d, 0x21, 0 - .dw 0x77c0, 0xc13d, 0x77ff, 0xc13d, 0x21, 0 - .dw 0x7840, 0xc13d, 0x787f, 0xc13d, 0x21, 0 - .dw 0x78c0, 0xc13d, 0x78ff, 0xc13d, 0x21, 0 - .dw 0x7940, 0xc13d, 0x797f, 0xc13d, 0x21, 0 - .dw 0x79c0, 0xc13d, 0x7fff, 0xc13d, 0x21, 0 - .dw 0x8040, 0xc13d, 0x807f, 0xc13d, 0x21, 0 - .dw 0x80c0, 0xc13d, 0x80ff, 0xc13d, 0x21, 0 - .dw 0x8140, 0xc13d, 0x817f, 0xc13d, 0x21, 0 - .dw 0x81c0, 0xc13d, 0x81ff, 0xc13d, 0x21, 0 - .dw 0x8240, 0xc13d, 0x827f, 0xc13d, 0x21, 0 - .dw 0x82c0, 0xc13d, 0x82ff, 0xc13d, 0x21, 0 - .dw 0x8340, 0xc13d, 0x837f, 0xc13d, 0x21, 0 - .dw 0x83c0, 0xc13d, 0x83ff, 0xc13d, 0x21, 0 - .dw 0x8440, 0xc13d, 0x847f, 0xc13d, 0x21, 0 - .dw 0x84c0, 0xc13d, 0x84ff, 0xc13d, 0x21, 0 - .dw 0x8540, 0xc13d, 0x857f, 0xc13d, 0x21, 0 - .dw 0x85c0, 0xc13d, 0x85ff, 0xc13d, 0x21, 0 - .dw 0x8640, 0xc13d, 0x867f, 0xc13d, 0x21, 0 - .dw 0x86c0, 0xc13d, 0x86ff, 0xc13d, 0x21, 0 - .dw 0x8740, 0xc13d, 0x877f, 0xc13d, 0x21, 0 - .dw 0x87c0, 0xc13d, 0x87ff, 0xc13d, 0x21, 0 - .dw 0x8840, 0xc13d, 0x887f, 0xc13d, 0x21, 0 - .dw 0x88c0, 0xc13d, 0x88ff, 0xc13d, 0x21, 0 - .dw 0x8940, 0xc13d, 0x897f, 0xc13d, 0x21, 0 - .dw 0x89c0, 0xc13d, 0x89ff, 0xc13d, 0x21, 0 - .dw 0x8a40, 0xc13d, 0x8a7f, 0xc13d, 0x21, 0 - .dw 0x8ac0, 0xc13d, 0x8aff, 0xc13d, 0x21, 0 - .dw 0x8b40, 0xc13d, 0x8b7f, 0xc13d, 0x21, 0 - .dw 0x8bc0, 0xc13d, 0x8bff, 0xc13d, 0x21, 0 - .dw 0x8c40, 0xc13d, 0x8c7f, 0xc13d, 0x21, 0 - .dw 0x8cc0, 0xc13d, 0x8cff, 0xc13d, 0x21, 0 - .dw 0x8d40, 0xc13d, 0x8d7f, 0xc13d, 0x21, 0 - .dw 0x8dc0, 0xc13d, 0x8dff, 0xc13d, 0x21, 0 - .dw 0x8e40, 0xc13d, 0x8e7f, 0xc13d, 0x21, 0 - .dw 0x8ec0, 0xc13d, 0x8eff, 0xc13d, 0x21, 0 - .dw 0x8f40, 0xc13d, 0x8f7f, 0xc13d, 0x21, 0 - .dw 0x8fc0, 0xc13d, 0x8fff, 0xc13d, 0x21, 0 - .dw 0x9040, 0xc13d, 0x907f, 0xc13d, 0x21, 0 - .dw 0x90c0, 0xc13d, 0x90ff, 0xc13d, 0x21, 0 - .dw 0x9140, 0xc13d, 0x917f, 0xc13d, 0x21, 0 - .dw 0x91c0, 0xc13d, 0x91ff, 0xc13d, 0x21, 0 - .dw 0x9240, 0xc13d, 0x927f, 0xc13d, 0x21, 0 - .dw 0x92c0, 0xc13d, 0x92ff, 0xc13d, 0x21, 0 - .dw 0x9340, 0xc13d, 0x937f, 0xc13d, 0x21, 0 - .dw 0x93c0, 0xc13d, 0x93ff, 0xc13d, 0x21, 0 - .dw 0x9440, 0xc13d, 0x947f, 0xc13d, 0x21, 0 - .dw 0x94c0, 0xc13d, 0x94ff, 0xc13d, 0x21, 0 - .dw 0x9540, 0xc13d, 0x957f, 0xc13d, 0x21, 0 - .dw 0x95c0, 0xc13d, 0x95ff, 0xc13d, 0x21, 0 - .dw 0x9640, 0xc13d, 0x967f, 0xc13d, 0x21, 0 - .dw 0x96c0, 0xc13d, 0x96ff, 0xc13d, 0x21, 0 - .dw 0x9740, 0xc13d, 0x977f, 0xc13d, 0x21, 0 - .dw 0x97c0, 0xc13d, 0x97ff, 0xc13d, 0x21, 0 - .dw 0x9840, 0xc13d, 0x987f, 0xc13d, 0x21, 0 - .dw 0x98c0, 0xc13d, 0x98ff, 0xc13d, 0x21, 0 - .dw 0x9940, 0xc13d, 0x997f, 0xc13d, 0x21, 0 - .dw 0x99c0, 0xc13d, 0x9fff, 0xc13d, 0x21, 0 - .dw 0xa040, 0xc13d, 0xa07f, 0xc13d, 0x21, 0 - .dw 0xa0c0, 0xc13d, 0xa0ff, 0xc13d, 0x21, 0 - .dw 0xa140, 0xc13d, 0xa17f, 0xc13d, 0x21, 0 - .dw 0xa1c0, 0xc13d, 0xa1ff, 0xc13d, 0x21, 0 - .dw 0xa240, 0xc13d, 0xa27f, 0xc13d, 0x21, 0 - .dw 0xa2c0, 0xc13d, 0xa2ff, 0xc13d, 0x21, 0 - .dw 0xa340, 0xc13d, 0xa37f, 0xc13d, 0x21, 0 - .dw 0xa3c0, 0xc13d, 0xa3ff, 0xc13d, 0x21, 0 - .dw 0xa440, 0xc13d, 0xa47f, 0xc13d, 0x21, 0 - .dw 0xa4c0, 0xc13d, 0xa4ff, 0xc13d, 0x21, 0 - .dw 0xa540, 0xc13d, 0xa57f, 0xc13d, 0x21, 0 - .dw 0xa5c0, 0xc13d, 0xa5ff, 0xc13d, 0x21, 0 - .dw 0xa640, 0xc13d, 0xa67f, 0xc13d, 0x21, 0 - .dw 0xa6c0, 0xc13d, 0xa6ff, 0xc13d, 0x21, 0 - .dw 0xa740, 0xc13d, 0xa77f, 0xc13d, 0x21, 0 - .dw 0xa7c0, 0xc13d, 0xa7ff, 0xc13d, 0x21, 0 - .dw 0xa840, 0xc13d, 0xa87f, 0xc13d, 0x21, 0 - .dw 0xa8c0, 0xc13d, 0xa8ff, 0xc13d, 0x21, 0 - .dw 0xa940, 0xc13d, 0xa97f, 0xc13d, 0x21, 0 - .dw 0xa9c0, 0xc13d, 0xa9ff, 0xc13d, 0x21, 0 - .dw 0xaa40, 0xc13d, 0xaa7f, 0xc13d, 0x21, 0 - .dw 0xaac0, 0xc13d, 0xaaff, 0xc13d, 0x21, 0 - .dw 0xab40, 0xc13d, 0xab7f, 0xc13d, 0x21, 0 - .dw 0xabc0, 0xc13d, 0xabff, 0xc13d, 0x21, 0 - .dw 0xac40, 0xc13d, 0xac7f, 0xc13d, 0x21, 0 - .dw 0xacc0, 0xc13d, 0xacff, 0xc13d, 0x21, 0 - .dw 0xad40, 0xc13d, 0xad7f, 0xc13d, 0x21, 0 - .dw 0xadc0, 0xc13d, 0xadff, 0xc13d, 0x21, 0 - .dw 0xae40, 0xc13d, 0xae7f, 0xc13d, 0x21, 0 - .dw 0xaec0, 0xc13d, 0xaeff, 0xc13d, 0x21, 0 - .dw 0xaf40, 0xc13d, 0xaf7f, 0xc13d, 0x21, 0 - .dw 0xafc0, 0xc13d, 0xafff, 0xc13d, 0x21, 0 - .dw 0xb040, 0xc13d, 0xb07f, 0xc13d, 0x21, 0 - .dw 0xb0c0, 0xc13d, 0xb0ff, 0xc13d, 0x21, 0 - .dw 0xb140, 0xc13d, 0xb17f, 0xc13d, 0x21, 0 - .dw 0xb1c0, 0xc13d, 0xb1ff, 0xc13d, 0x21, 0 - .dw 0xb240, 0xc13d, 0xb27f, 0xc13d, 0x21, 0 - .dw 0xb2c0, 0xc13d, 0xb2ff, 0xc13d, 0x21, 0 - .dw 0xb340, 0xc13d, 0xb37f, 0xc13d, 0x21, 0 - .dw 0xb3c0, 0xc13d, 0xb3ff, 0xc13d, 0x21, 0 - .dw 0xb440, 0xc13d, 0xb47f, 0xc13d, 0x21, 0 - .dw 0xb4c0, 0xc13d, 0xb4ff, 0xc13d, 0x21, 0 - .dw 0xb540, 0xc13d, 0xb57f, 0xc13d, 0x21, 0 - .dw 0xb5c0, 0xc13d, 0xb5ff, 0xc13d, 0x21, 0 - .dw 0xb640, 0xc13d, 0xb67f, 0xc13d, 0x21, 0 - .dw 0xb6c0, 0xc13d, 0xb6ff, 0xc13d, 0x21, 0 - .dw 0xb740, 0xc13d, 0xb77f, 0xc13d, 0x21, 0 - .dw 0xb7c0, 0xc13d, 0xb7ff, 0xc13d, 0x21, 0 - .dw 0xb840, 0xc13d, 0xb87f, 0xc13d, 0x21, 0 - .dw 0xb8c0, 0xc13d, 0xb8ff, 0xc13d, 0x21, 0 - .dw 0xb940, 0xc13d, 0xb97f, 0xc13d, 0x21, 0 - .dw 0xb9c0, 0xc13d, 0xbfff, 0xc13d, 0x21, 0 - .dw 0xc040, 0xc13d, 0xc07f, 0xc13d, 0x21, 0 - .dw 0xc0c0, 0xc13d, 0xc0ff, 0xc13d, 0x21, 0 - .dw 0xc140, 0xc13d, 0xc17f, 0xc13d, 0x21, 0 - .dw 0xc1c0, 0xc13d, 0xc1ff, 0xc13d, 0x21, 0 - .dw 0xc240, 0xc13d, 0xc27f, 0xc13d, 0x21, 0 - .dw 0xc2c0, 0xc13d, 0xc2ff, 0xc13d, 0x21, 0 - .dw 0xc340, 0xc13d, 0xc37f, 0xc13d, 0x21, 0 - .dw 0xc3c0, 0xc13d, 0xc3ff, 0xc13d, 0x21, 0 - .dw 0xc440, 0xc13d, 0xc47f, 0xc13d, 0x21, 0 - .dw 0xc4c0, 0xc13d, 0xc4ff, 0xc13d, 0x21, 0 - .dw 0xc540, 0xc13d, 0xc57f, 0xc13d, 0x21, 0 - .dw 0xc5c0, 0xc13d, 0xc5ff, 0xc13d, 0x21, 0 - .dw 0xc640, 0xc13d, 0xc67f, 0xc13d, 0x21, 0 - .dw 0xc6c0, 0xc13d, 0xc6ff, 0xc13d, 0x21, 0 - .dw 0xc740, 0xc13d, 0xc77f, 0xc13d, 0x21, 0 - .dw 0xc7c0, 0xc13d, 0xc7ff, 0xc13d, 0x21, 0 - .dw 0xc840, 0xc13d, 0xc87f, 0xc13d, 0x21, 0 - .dw 0xc8c0, 0xc13d, 0xc8ff, 0xc13d, 0x21, 0 - .dw 0xc940, 0xc13d, 0xc97f, 0xc13d, 0x21, 0 - .dw 0xc9c0, 0xc13d, 0xc9ff, 0xc13d, 0x21, 0 - .dw 0xca40, 0xc13d, 0xca7f, 0xc13d, 0x21, 0 - .dw 0xcac0, 0xc13d, 0xcaff, 0xc13d, 0x21, 0 - .dw 0xcb40, 0xc13d, 0xcb7f, 0xc13d, 0x21, 0 - .dw 0xcbc0, 0xc13d, 0xcbff, 0xc13d, 0x21, 0 - .dw 0xcc40, 0xc13d, 0xcc7f, 0xc13d, 0x21, 0 - .dw 0xccc0, 0xc13d, 0xccff, 0xc13d, 0x21, 0 - .dw 0xcd40, 0xc13d, 0xcd7f, 0xc13d, 0x21, 0 - .dw 0xcdc0, 0xc13d, 0xcdff, 0xc13d, 0x21, 0 - .dw 0xce40, 0xc13d, 0xce7f, 0xc13d, 0x21, 0 - .dw 0xcec0, 0xc13d, 0xceff, 0xc13d, 0x21, 0 - .dw 0xcf40, 0xc13d, 0xcf7f, 0xc13d, 0x21, 0 - .dw 0xcfc0, 0xc13d, 0xcfff, 0xc13d, 0x21, 0 - .dw 0xd040, 0xc13d, 0xd07f, 0xc13d, 0x21, 0 - .dw 0xd0c0, 0xc13d, 0xd0ff, 0xc13d, 0x21, 0 - .dw 0xd140, 0xc13d, 0xd17f, 0xc13d, 0x21, 0 - .dw 0xd1c0, 0xc13d, 0xd1ff, 0xc13d, 0x21, 0 - .dw 0xd240, 0xc13d, 0xd27f, 0xc13d, 0x21, 0 - .dw 0xd2c0, 0xc13d, 0xd2ff, 0xc13d, 0x21, 0 - .dw 0xd340, 0xc13d, 0xd37f, 0xc13d, 0x21, 0 - .dw 0xd3c0, 0xc13d, 0xd3ff, 0xc13d, 0x21, 0 - .dw 0xd440, 0xc13d, 0xd47f, 0xc13d, 0x21, 0 - .dw 0xd4c0, 0xc13d, 0xd4ff, 0xc13d, 0x21, 0 - .dw 0xd540, 0xc13d, 0xd57f, 0xc13d, 0x21, 0 - .dw 0xd5c0, 0xc13d, 0xd5ff, 0xc13d, 0x21, 0 - .dw 0xd640, 0xc13d, 0xd67f, 0xc13d, 0x21, 0 - .dw 0xd6c0, 0xc13d, 0xd6ff, 0xc13d, 0x21, 0 - .dw 0xd740, 0xc13d, 0xd77f, 0xc13d, 0x21, 0 - .dw 0xd7c0, 0xc13d, 0xd7ff, 0xc13d, 0x21, 0 - .dw 0xd840, 0xc13d, 0xd87f, 0xc13d, 0x21, 0 - .dw 0xd8c0, 0xc13d, 0xd8ff, 0xc13d, 0x21, 0 - .dw 0xd940, 0xc13d, 0xd97f, 0xc13d, 0x21, 0 - .dw 0xd9c0, 0xc13d, 0xdfff, 0xc13d, 0x21, 0 - .dw 0xe040, 0xc13d, 0xe07f, 0xc13d, 0x21, 0 - .dw 0xe0c0, 0xc13d, 0xe0ff, 0xc13d, 0x21, 0 - .dw 0xe140, 0xc13d, 0xe17f, 0xc13d, 0x21, 0 - .dw 0xe1c0, 0xc13d, 0xe1ff, 0xc13d, 0x21, 0 - .dw 0xe240, 0xc13d, 0xe27f, 0xc13d, 0x21, 0 - .dw 0xe2c0, 0xc13d, 0xe2ff, 0xc13d, 0x21, 0 - .dw 0xe340, 0xc13d, 0xe37f, 0xc13d, 0x21, 0 - .dw 0xe3c0, 0xc13d, 0xe3ff, 0xc13d, 0x21, 0 - .dw 0xe440, 0xc13d, 0xe47f, 0xc13d, 0x21, 0 - .dw 0xe4c0, 0xc13d, 0xe4ff, 0xc13d, 0x21, 0 - .dw 0xe540, 0xc13d, 0xe57f, 0xc13d, 0x21, 0 - .dw 0xe5c0, 0xc13d, 0xe5ff, 0xc13d, 0x21, 0 - .dw 0xe640, 0xc13d, 0xe67f, 0xc13d, 0x21, 0 - .dw 0xe6c0, 0xc13d, 0xe6ff, 0xc13d, 0x21, 0 - .dw 0xe740, 0xc13d, 0xe77f, 0xc13d, 0x21, 0 - .dw 0xe7c0, 0xc13d, 0xe7ff, 0xc13d, 0x21, 0 - .dw 0xe840, 0xc13d, 0xe87f, 0xc13d, 0x21, 0 - .dw 0xe8c0, 0xc13d, 0xe8ff, 0xc13d, 0x21, 0 - .dw 0xe940, 0xc13d, 0xe97f, 0xc13d, 0x21, 0 - .dw 0xe9c0, 0xc13d, 0xe9ff, 0xc13d, 0x21, 0 - .dw 0xea40, 0xc13d, 0xea7f, 0xc13d, 0x21, 0 - .dw 0xeac0, 0xc13d, 0xeaff, 0xc13d, 0x21, 0 - .dw 0xeb40, 0xc13d, 0xeb7f, 0xc13d, 0x21, 0 - .dw 0xebc0, 0xc13d, 0xebff, 0xc13d, 0x21, 0 - .dw 0xec40, 0xc13d, 0xec7f, 0xc13d, 0x21, 0 - .dw 0xecc0, 0xc13d, 0xecff, 0xc13d, 0x21, 0 - .dw 0xed40, 0xc13d, 0xed7f, 0xc13d, 0x21, 0 - .dw 0xedc0, 0xc13d, 0xedff, 0xc13d, 0x21, 0 - .dw 0xee40, 0xc13d, 0xee7f, 0xc13d, 0x21, 0 - .dw 0xeec0, 0xc13d, 0xeeff, 0xc13d, 0x21, 0 - .dw 0xef40, 0xc13d, 0xef7f, 0xc13d, 0x21, 0 - .dw 0xefc0, 0xc13d, 0xefff, 0xc13d, 0x21, 0 - .dw 0xf040, 0xc13d, 0xf07f, 0xc13d, 0x21, 0 - .dw 0xf0c0, 0xc13d, 0xf0ff, 0xc13d, 0x21, 0 - .dw 0xf140, 0xc13d, 0xf17f, 0xc13d, 0x21, 0 - .dw 0xf1c0, 0xc13d, 0xf1ff, 0xc13d, 0x21, 0 - .dw 0xf240, 0xc13d, 0xf27f, 0xc13d, 0x21, 0 - .dw 0xf2c0, 0xc13d, 0xf2ff, 0xc13d, 0x21, 0 - .dw 0xf340, 0xc13d, 0xf37f, 0xc13d, 0x21, 0 - .dw 0xf3c0, 0xc13d, 0xf3ff, 0xc13d, 0x21, 0 - .dw 0xf440, 0xc13d, 0xf47f, 0xc13d, 0x21, 0 - .dw 0xf4c0, 0xc13d, 0xf4ff, 0xc13d, 0x21, 0 - .dw 0xf540, 0xc13d, 0xf57f, 0xc13d, 0x21, 0 - .dw 0xf5c0, 0xc13d, 0xf5ff, 0xc13d, 0x21, 0 - .dw 0xf640, 0xc13d, 0xf67f, 0xc13d, 0x21, 0 - .dw 0xf6c0, 0xc13d, 0xf6ff, 0xc13d, 0x21, 0 - .dw 0xf740, 0xc13d, 0xf77f, 0xc13d, 0x21, 0 - .dw 0xf7c0, 0xc13d, 0xf7ff, 0xc13d, 0x21, 0 - .dw 0xf840, 0xc13d, 0xf87f, 0xc13d, 0x21, 0 - .dw 0xf8c0, 0xc13d, 0xf8ff, 0xc13d, 0x21, 0 - .dw 0xf940, 0xc13d, 0xf97f, 0xc13d, 0x21, 0 - .dw 0xf9c0, 0xc13d, 0xffff, 0xc13d, 0x21, 0 - .dw 0x0040, 0xc13e, 0x007f, 0xc13e, 0x21, 0 - .dw 0x00c0, 0xc13e, 0x00ff, 0xc13e, 0x21, 0 - .dw 0x0140, 0xc13e, 0x017f, 0xc13e, 0x21, 0 - .dw 0x01c0, 0xc13e, 0x01ff, 0xc13e, 0x21, 0 - .dw 0x0240, 0xc13e, 0x027f, 0xc13e, 0x21, 0 - .dw 0x02c0, 0xc13e, 0x02ff, 0xc13e, 0x21, 0 - .dw 0x0340, 0xc13e, 0x037f, 0xc13e, 0x21, 0 - .dw 0x03c0, 0xc13e, 0x03ff, 0xc13e, 0x21, 0 - .dw 0x0440, 0xc13e, 0x047f, 0xc13e, 0x21, 0 - .dw 0x04c0, 0xc13e, 0x04ff, 0xc13e, 0x21, 0 - .dw 0x0540, 0xc13e, 0x057f, 0xc13e, 0x21, 0 - .dw 0x05c0, 0xc13e, 0x05ff, 0xc13e, 0x21, 0 - .dw 0x0640, 0xc13e, 0x067f, 0xc13e, 0x21, 0 - .dw 0x06c0, 0xc13e, 0x06ff, 0xc13e, 0x21, 0 - .dw 0x0740, 0xc13e, 0x077f, 0xc13e, 0x21, 0 - .dw 0x07c0, 0xc13e, 0x07ff, 0xc13e, 0x21, 0 - .dw 0x0840, 0xc13e, 0x087f, 0xc13e, 0x21, 0 - .dw 0x08c0, 0xc13e, 0x08ff, 0xc13e, 0x21, 0 - .dw 0x0940, 0xc13e, 0x097f, 0xc13e, 0x21, 0 - .dw 0x09c0, 0xc13e, 0x09ff, 0xc13e, 0x21, 0 - .dw 0x0a40, 0xc13e, 0x0a7f, 0xc13e, 0x21, 0 - .dw 0x0ac0, 0xc13e, 0x0aff, 0xc13e, 0x21, 0 - .dw 0x0b40, 0xc13e, 0x0b7f, 0xc13e, 0x21, 0 - .dw 0x0bc0, 0xc13e, 0x0bff, 0xc13e, 0x21, 0 - .dw 0x0c40, 0xc13e, 0x0c7f, 0xc13e, 0x21, 0 - .dw 0x0cc0, 0xc13e, 0x0cff, 0xc13e, 0x21, 0 - .dw 0x0d40, 0xc13e, 0x0d7f, 0xc13e, 0x21, 0 - .dw 0x0dc0, 0xc13e, 0x0dff, 0xc13e, 0x21, 0 - .dw 0x0e40, 0xc13e, 0x0e7f, 0xc13e, 0x21, 0 - .dw 0x0ec0, 0xc13e, 0x0eff, 0xc13e, 0x21, 0 - .dw 0x0f40, 0xc13e, 0x0f7f, 0xc13e, 0x21, 0 - .dw 0x0fc0, 0xc13e, 0x0fff, 0xc13e, 0x21, 0 - .dw 0x1040, 0xc13e, 0x107f, 0xc13e, 0x21, 0 - .dw 0x10c0, 0xc13e, 0x10ff, 0xc13e, 0x21, 0 - .dw 0x1140, 0xc13e, 0x117f, 0xc13e, 0x21, 0 - .dw 0x11c0, 0xc13e, 0x11ff, 0xc13e, 0x21, 0 - .dw 0x1240, 0xc13e, 0x127f, 0xc13e, 0x21, 0 - .dw 0x12c0, 0xc13e, 0x12ff, 0xc13e, 0x21, 0 - .dw 0x1340, 0xc13e, 0x137f, 0xc13e, 0x21, 0 - .dw 0x13c0, 0xc13e, 0x13ff, 0xc13e, 0x21, 0 - .dw 0x1440, 0xc13e, 0x147f, 0xc13e, 0x21, 0 - .dw 0x14c0, 0xc13e, 0x14ff, 0xc13e, 0x21, 0 - .dw 0x1540, 0xc13e, 0x157f, 0xc13e, 0x21, 0 - .dw 0x15c0, 0xc13e, 0x15ff, 0xc13e, 0x21, 0 - .dw 0x1640, 0xc13e, 0x167f, 0xc13e, 0x21, 0 - .dw 0x16c0, 0xc13e, 0x16ff, 0xc13e, 0x21, 0 - .dw 0x1740, 0xc13e, 0x177f, 0xc13e, 0x21, 0 - .dw 0x17c0, 0xc13e, 0x17ff, 0xc13e, 0x21, 0 - .dw 0x1840, 0xc13e, 0x187f, 0xc13e, 0x21, 0 - .dw 0x18c0, 0xc13e, 0x18ff, 0xc13e, 0x21, 0 - .dw 0x1940, 0xc13e, 0x197f, 0xc13e, 0x21, 0 - .dw 0x19c0, 0xc13e, 0x1fff, 0xc13e, 0x21, 0 - .dw 0x2040, 0xc13e, 0x207f, 0xc13e, 0x21, 0 - .dw 0x20c0, 0xc13e, 0x20ff, 0xc13e, 0x21, 0 - .dw 0x2140, 0xc13e, 0x217f, 0xc13e, 0x21, 0 - .dw 0x21c0, 0xc13e, 0x21ff, 0xc13e, 0x21, 0 - .dw 0x2240, 0xc13e, 0x227f, 0xc13e, 0x21, 0 - .dw 0x22c0, 0xc13e, 0x22ff, 0xc13e, 0x21, 0 - .dw 0x2340, 0xc13e, 0x237f, 0xc13e, 0x21, 0 - .dw 0x23c0, 0xc13e, 0x23ff, 0xc13e, 0x21, 0 - .dw 0x2440, 0xc13e, 0x247f, 0xc13e, 0x21, 0 - .dw 0x24c0, 0xc13e, 0x24ff, 0xc13e, 0x21, 0 - .dw 0x2540, 0xc13e, 0x257f, 0xc13e, 0x21, 0 - .dw 0x25c0, 0xc13e, 0x25ff, 0xc13e, 0x21, 0 - .dw 0x2640, 0xc13e, 0x267f, 0xc13e, 0x21, 0 - .dw 0x26c0, 0xc13e, 0x26ff, 0xc13e, 0x21, 0 - .dw 0x2740, 0xc13e, 0x277f, 0xc13e, 0x21, 0 - .dw 0x27c0, 0xc13e, 0x27ff, 0xc13e, 0x21, 0 - .dw 0x2840, 0xc13e, 0x287f, 0xc13e, 0x21, 0 - .dw 0x28c0, 0xc13e, 0x28ff, 0xc13e, 0x21, 0 - .dw 0x2940, 0xc13e, 0x297f, 0xc13e, 0x21, 0 - .dw 0x29c0, 0xc13e, 0x29ff, 0xc13e, 0x21, 0 - .dw 0x2a40, 0xc13e, 0x2a7f, 0xc13e, 0x21, 0 - .dw 0x2ac0, 0xc13e, 0x2aff, 0xc13e, 0x21, 0 - .dw 0x2b40, 0xc13e, 0x2b7f, 0xc13e, 0x21, 0 - .dw 0x2bc0, 0xc13e, 0x2bff, 0xc13e, 0x21, 0 - .dw 0x2c40, 0xc13e, 0x2c7f, 0xc13e, 0x21, 0 - .dw 0x2cc0, 0xc13e, 0x2cff, 0xc13e, 0x21, 0 - .dw 0x2d40, 0xc13e, 0x2d7f, 0xc13e, 0x21, 0 - .dw 0x2dc0, 0xc13e, 0x2dff, 0xc13e, 0x21, 0 - .dw 0x2e40, 0xc13e, 0x2e7f, 0xc13e, 0x21, 0 - .dw 0x2ec0, 0xc13e, 0x2eff, 0xc13e, 0x21, 0 - .dw 0x2f40, 0xc13e, 0x2f7f, 0xc13e, 0x21, 0 - .dw 0x2fc0, 0xc13e, 0x2fff, 0xc13e, 0x21, 0 - .dw 0x3040, 0xc13e, 0x307f, 0xc13e, 0x21, 0 - .dw 0x30c0, 0xc13e, 0x30ff, 0xc13e, 0x21, 0 - .dw 0x3140, 0xc13e, 0x317f, 0xc13e, 0x21, 0 - .dw 0x31c0, 0xc13e, 0x31ff, 0xc13e, 0x21, 0 - .dw 0x3240, 0xc13e, 0x327f, 0xc13e, 0x21, 0 - .dw 0x32c0, 0xc13e, 0x32ff, 0xc13e, 0x21, 0 - .dw 0x3340, 0xc13e, 0x337f, 0xc13e, 0x21, 0 - .dw 0x33c0, 0xc13e, 0x33ff, 0xc13e, 0x21, 0 - .dw 0x3440, 0xc13e, 0x347f, 0xc13e, 0x21, 0 - .dw 0x34c0, 0xc13e, 0x34ff, 0xc13e, 0x21, 0 - .dw 0x3540, 0xc13e, 0x357f, 0xc13e, 0x21, 0 - .dw 0x35c0, 0xc13e, 0x35ff, 0xc13e, 0x21, 0 - .dw 0x3640, 0xc13e, 0x367f, 0xc13e, 0x21, 0 - .dw 0x36c0, 0xc13e, 0x36ff, 0xc13e, 0x21, 0 - .dw 0x3740, 0xc13e, 0x377f, 0xc13e, 0x21, 0 - .dw 0x37c0, 0xc13e, 0x37ff, 0xc13e, 0x21, 0 - .dw 0x3840, 0xc13e, 0x387f, 0xc13e, 0x21, 0 - .dw 0x38c0, 0xc13e, 0x38ff, 0xc13e, 0x21, 0 - .dw 0x3940, 0xc13e, 0x397f, 0xc13e, 0x21, 0 - .dw 0x39c0, 0xc13e, 0x3fff, 0xc13e, 0x21, 0 - .dw 0x4040, 0xc13e, 0x407f, 0xc13e, 0x21, 0 - .dw 0x40c0, 0xc13e, 0x40ff, 0xc13e, 0x21, 0 - .dw 0x4140, 0xc13e, 0x417f, 0xc13e, 0x21, 0 - .dw 0x41c0, 0xc13e, 0x41ff, 0xc13e, 0x21, 0 - .dw 0x4240, 0xc13e, 0x427f, 0xc13e, 0x21, 0 - .dw 0x42c0, 0xc13e, 0x42ff, 0xc13e, 0x21, 0 - .dw 0x4340, 0xc13e, 0x437f, 0xc13e, 0x21, 0 - .dw 0x43c0, 0xc13e, 0x43ff, 0xc13e, 0x21, 0 - .dw 0x4440, 0xc13e, 0x447f, 0xc13e, 0x21, 0 - .dw 0x44c0, 0xc13e, 0x44ff, 0xc13e, 0x21, 0 - .dw 0x4540, 0xc13e, 0x457f, 0xc13e, 0x21, 0 - .dw 0x45c0, 0xc13e, 0x45ff, 0xc13e, 0x21, 0 - .dw 0x4640, 0xc13e, 0x467f, 0xc13e, 0x21, 0 - .dw 0x46c0, 0xc13e, 0x46ff, 0xc13e, 0x21, 0 - .dw 0x4740, 0xc13e, 0x477f, 0xc13e, 0x21, 0 - .dw 0x47c0, 0xc13e, 0x47ff, 0xc13e, 0x21, 0 - .dw 0x4840, 0xc13e, 0x487f, 0xc13e, 0x21, 0 - .dw 0x48c0, 0xc13e, 0x48ff, 0xc13e, 0x21, 0 - .dw 0x4940, 0xc13e, 0x497f, 0xc13e, 0x21, 0 - .dw 0x49c0, 0xc13e, 0x49ff, 0xc13e, 0x21, 0 - .dw 0x4a40, 0xc13e, 0x4a7f, 0xc13e, 0x21, 0 - .dw 0x4ac0, 0xc13e, 0x4aff, 0xc13e, 0x21, 0 - .dw 0x4b40, 0xc13e, 0x4b7f, 0xc13e, 0x21, 0 - .dw 0x4bc0, 0xc13e, 0x4bff, 0xc13e, 0x21, 0 - .dw 0x4c40, 0xc13e, 0x4c7f, 0xc13e, 0x21, 0 - .dw 0x4cc0, 0xc13e, 0x4cff, 0xc13e, 0x21, 0 - .dw 0x4d40, 0xc13e, 0x4d7f, 0xc13e, 0x21, 0 - .dw 0x4dc0, 0xc13e, 0x4dff, 0xc13e, 0x21, 0 - .dw 0x4e40, 0xc13e, 0x4e7f, 0xc13e, 0x21, 0 - .dw 0x4ec0, 0xc13e, 0x4eff, 0xc13e, 0x21, 0 - .dw 0x4f40, 0xc13e, 0x4f7f, 0xc13e, 0x21, 0 - .dw 0x4fc0, 0xc13e, 0x4fff, 0xc13e, 0x21, 0 - .dw 0x5040, 0xc13e, 0x507f, 0xc13e, 0x21, 0 - .dw 0x50c0, 0xc13e, 0x50ff, 0xc13e, 0x21, 0 - .dw 0x5140, 0xc13e, 0x517f, 0xc13e, 0x21, 0 - .dw 0x51c0, 0xc13e, 0x51ff, 0xc13e, 0x21, 0 - .dw 0x5240, 0xc13e, 0x527f, 0xc13e, 0x21, 0 - .dw 0x52c0, 0xc13e, 0x52ff, 0xc13e, 0x21, 0 - .dw 0x5340, 0xc13e, 0x537f, 0xc13e, 0x21, 0 - .dw 0x53c0, 0xc13e, 0x53ff, 0xc13e, 0x21, 0 - .dw 0x5440, 0xc13e, 0x547f, 0xc13e, 0x21, 0 - .dw 0x54c0, 0xc13e, 0x54ff, 0xc13e, 0x21, 0 - .dw 0x5540, 0xc13e, 0x557f, 0xc13e, 0x21, 0 - .dw 0x55c0, 0xc13e, 0x55ff, 0xc13e, 0x21, 0 - .dw 0x5640, 0xc13e, 0x567f, 0xc13e, 0x21, 0 - .dw 0x56c0, 0xc13e, 0x56ff, 0xc13e, 0x21, 0 - .dw 0x5740, 0xc13e, 0x577f, 0xc13e, 0x21, 0 - .dw 0x57c0, 0xc13e, 0x57ff, 0xc13e, 0x21, 0 - .dw 0x5840, 0xc13e, 0x587f, 0xc13e, 0x21, 0 - .dw 0x58c0, 0xc13e, 0x58ff, 0xc13e, 0x21, 0 - .dw 0x5940, 0xc13e, 0x597f, 0xc13e, 0x21, 0 - .dw 0x59c0, 0xc13e, 0x5fff, 0xc13e, 0x21, 0 - .dw 0x6040, 0xc13e, 0x607f, 0xc13e, 0x21, 0 - .dw 0x60c0, 0xc13e, 0x60ff, 0xc13e, 0x21, 0 - .dw 0x6140, 0xc13e, 0x617f, 0xc13e, 0x21, 0 - .dw 0x61c0, 0xc13e, 0x61ff, 0xc13e, 0x21, 0 - .dw 0x6240, 0xc13e, 0x627f, 0xc13e, 0x21, 0 - .dw 0x62c0, 0xc13e, 0x62ff, 0xc13e, 0x21, 0 - .dw 0x6340, 0xc13e, 0x637f, 0xc13e, 0x21, 0 - .dw 0x63c0, 0xc13e, 0x63ff, 0xc13e, 0x21, 0 - .dw 0x6440, 0xc13e, 0x647f, 0xc13e, 0x21, 0 - .dw 0x64c0, 0xc13e, 0x64ff, 0xc13e, 0x21, 0 - .dw 0x6540, 0xc13e, 0x657f, 0xc13e, 0x21, 0 - .dw 0x65c0, 0xc13e, 0x65ff, 0xc13e, 0x21, 0 - .dw 0x6640, 0xc13e, 0x667f, 0xc13e, 0x21, 0 - .dw 0x66c0, 0xc13e, 0x66ff, 0xc13e, 0x21, 0 - .dw 0x6740, 0xc13e, 0x677f, 0xc13e, 0x21, 0 - .dw 0x67c0, 0xc13e, 0x67ff, 0xc13e, 0x21, 0 - .dw 0x6840, 0xc13e, 0x687f, 0xc13e, 0x21, 0 - .dw 0x68c0, 0xc13e, 0x68ff, 0xc13e, 0x21, 0 - .dw 0x6940, 0xc13e, 0x697f, 0xc13e, 0x21, 0 - .dw 0x69c0, 0xc13e, 0x69ff, 0xc13e, 0x21, 0 - .dw 0x6a40, 0xc13e, 0x6a7f, 0xc13e, 0x21, 0 - .dw 0x6ac0, 0xc13e, 0x6aff, 0xc13e, 0x21, 0 - .dw 0x6b40, 0xc13e, 0x6b7f, 0xc13e, 0x21, 0 - .dw 0x6bc0, 0xc13e, 0x6bff, 0xc13e, 0x21, 0 - .dw 0x6c40, 0xc13e, 0x6c7f, 0xc13e, 0x21, 0 - .dw 0x6cc0, 0xc13e, 0x6cff, 0xc13e, 0x21, 0 - .dw 0x6d40, 0xc13e, 0x6d7f, 0xc13e, 0x21, 0 - .dw 0x6dc0, 0xc13e, 0x6dff, 0xc13e, 0x21, 0 - .dw 0x6e40, 0xc13e, 0x6e7f, 0xc13e, 0x21, 0 - .dw 0x6ec0, 0xc13e, 0x6eff, 0xc13e, 0x21, 0 - .dw 0x6f40, 0xc13e, 0x6f7f, 0xc13e, 0x21, 0 - .dw 0x6fc0, 0xc13e, 0x6fff, 0xc13e, 0x21, 0 - .dw 0x7040, 0xc13e, 0x707f, 0xc13e, 0x21, 0 - .dw 0x70c0, 0xc13e, 0x70ff, 0xc13e, 0x21, 0 - .dw 0x7140, 0xc13e, 0x717f, 0xc13e, 0x21, 0 - .dw 0x71c0, 0xc13e, 0x71ff, 0xc13e, 0x21, 0 - .dw 0x7240, 0xc13e, 0x727f, 0xc13e, 0x21, 0 - .dw 0x72c0, 0xc13e, 0x72ff, 0xc13e, 0x21, 0 - .dw 0x7340, 0xc13e, 0x737f, 0xc13e, 0x21, 0 - .dw 0x73c0, 0xc13e, 0x73ff, 0xc13e, 0x21, 0 - .dw 0x7440, 0xc13e, 0x747f, 0xc13e, 0x21, 0 - .dw 0x74c0, 0xc13e, 0x74ff, 0xc13e, 0x21, 0 - .dw 0x7540, 0xc13e, 0x757f, 0xc13e, 0x21, 0 - .dw 0x75c0, 0xc13e, 0x75ff, 0xc13e, 0x21, 0 - .dw 0x7640, 0xc13e, 0x767f, 0xc13e, 0x21, 0 - .dw 0x76c0, 0xc13e, 0x76ff, 0xc13e, 0x21, 0 - .dw 0x7740, 0xc13e, 0x777f, 0xc13e, 0x21, 0 - .dw 0x77c0, 0xc13e, 0x77ff, 0xc13e, 0x21, 0 - .dw 0x7840, 0xc13e, 0x787f, 0xc13e, 0x21, 0 - .dw 0x78c0, 0xc13e, 0x78ff, 0xc13e, 0x21, 0 - .dw 0x7940, 0xc13e, 0x797f, 0xc13e, 0x21, 0 - .dw 0x79c0, 0xc13e, 0x7fff, 0xc13e, 0x21, 0 - .dw 0x8040, 0xc13e, 0x807f, 0xc13e, 0x21, 0 - .dw 0x80c0, 0xc13e, 0x80ff, 0xc13e, 0x21, 0 - .dw 0x8140, 0xc13e, 0x817f, 0xc13e, 0x21, 0 - .dw 0x81c0, 0xc13e, 0x81ff, 0xc13e, 0x21, 0 - .dw 0x8240, 0xc13e, 0x827f, 0xc13e, 0x21, 0 - .dw 0x82c0, 0xc13e, 0x82ff, 0xc13e, 0x21, 0 - .dw 0x8340, 0xc13e, 0x837f, 0xc13e, 0x21, 0 - .dw 0x83c0, 0xc13e, 0x83ff, 0xc13e, 0x21, 0 - .dw 0x8440, 0xc13e, 0x847f, 0xc13e, 0x21, 0 - .dw 0x84c0, 0xc13e, 0x84ff, 0xc13e, 0x21, 0 - .dw 0x8540, 0xc13e, 0x857f, 0xc13e, 0x21, 0 - .dw 0x85c0, 0xc13e, 0x85ff, 0xc13e, 0x21, 0 - .dw 0x8640, 0xc13e, 0x867f, 0xc13e, 0x21, 0 - .dw 0x86c0, 0xc13e, 0x86ff, 0xc13e, 0x21, 0 - .dw 0x8740, 0xc13e, 0x877f, 0xc13e, 0x21, 0 - .dw 0x87c0, 0xc13e, 0x87ff, 0xc13e, 0x21, 0 - .dw 0x8840, 0xc13e, 0x887f, 0xc13e, 0x21, 0 - .dw 0x88c0, 0xc13e, 0x88ff, 0xc13e, 0x21, 0 - .dw 0x8940, 0xc13e, 0x897f, 0xc13e, 0x21, 0 - .dw 0x89c0, 0xc13e, 0x89ff, 0xc13e, 0x21, 0 - .dw 0x8a40, 0xc13e, 0x8a7f, 0xc13e, 0x21, 0 - .dw 0x8ac0, 0xc13e, 0x8aff, 0xc13e, 0x21, 0 - .dw 0x8b40, 0xc13e, 0x8b7f, 0xc13e, 0x21, 0 - .dw 0x8bc0, 0xc13e, 0x8bff, 0xc13e, 0x21, 0 - .dw 0x8c40, 0xc13e, 0x8c7f, 0xc13e, 0x21, 0 - .dw 0x8cc0, 0xc13e, 0x8cff, 0xc13e, 0x21, 0 - .dw 0x8d40, 0xc13e, 0x8d7f, 0xc13e, 0x21, 0 - .dw 0x8dc0, 0xc13e, 0x8dff, 0xc13e, 0x21, 0 - .dw 0x8e40, 0xc13e, 0x8e7f, 0xc13e, 0x21, 0 - .dw 0x8ec0, 0xc13e, 0x8eff, 0xc13e, 0x21, 0 - .dw 0x8f40, 0xc13e, 0x8f7f, 0xc13e, 0x21, 0 - .dw 0x8fc0, 0xc13e, 0x8fff, 0xc13e, 0x21, 0 - .dw 0x9040, 0xc13e, 0x907f, 0xc13e, 0x21, 0 - .dw 0x90c0, 0xc13e, 0x90ff, 0xc13e, 0x21, 0 - .dw 0x9140, 0xc13e, 0x917f, 0xc13e, 0x21, 0 - .dw 0x91c0, 0xc13e, 0x91ff, 0xc13e, 0x21, 0 - .dw 0x9240, 0xc13e, 0x927f, 0xc13e, 0x21, 0 - .dw 0x92c0, 0xc13e, 0x92ff, 0xc13e, 0x21, 0 - .dw 0x9340, 0xc13e, 0x937f, 0xc13e, 0x21, 0 - .dw 0x93c0, 0xc13e, 0x93ff, 0xc13e, 0x21, 0 - .dw 0x9440, 0xc13e, 0x947f, 0xc13e, 0x21, 0 - .dw 0x94c0, 0xc13e, 0x94ff, 0xc13e, 0x21, 0 - .dw 0x9540, 0xc13e, 0x957f, 0xc13e, 0x21, 0 - .dw 0x95c0, 0xc13e, 0x95ff, 0xc13e, 0x21, 0 - .dw 0x9640, 0xc13e, 0x967f, 0xc13e, 0x21, 0 - .dw 0x96c0, 0xc13e, 0x96ff, 0xc13e, 0x21, 0 - .dw 0x9740, 0xc13e, 0x977f, 0xc13e, 0x21, 0 - .dw 0x97c0, 0xc13e, 0x97ff, 0xc13e, 0x21, 0 - .dw 0x9840, 0xc13e, 0x987f, 0xc13e, 0x21, 0 - .dw 0x98c0, 0xc13e, 0x98ff, 0xc13e, 0x21, 0 - .dw 0x9940, 0xc13e, 0x997f, 0xc13e, 0x21, 0 - .dw 0x99c0, 0xc13e, 0x9fff, 0xc13e, 0x21, 0 - .dw 0xa040, 0xc13e, 0xa07f, 0xc13e, 0x21, 0 - .dw 0xa0c0, 0xc13e, 0xa0ff, 0xc13e, 0x21, 0 - .dw 0xa140, 0xc13e, 0xa17f, 0xc13e, 0x21, 0 - .dw 0xa1c0, 0xc13e, 0xa1ff, 0xc13e, 0x21, 0 - .dw 0xa240, 0xc13e, 0xa27f, 0xc13e, 0x21, 0 - .dw 0xa2c0, 0xc13e, 0xa2ff, 0xc13e, 0x21, 0 - .dw 0xa340, 0xc13e, 0xa37f, 0xc13e, 0x21, 0 - .dw 0xa3c0, 0xc13e, 0xa3ff, 0xc13e, 0x21, 0 - .dw 0xa440, 0xc13e, 0xa47f, 0xc13e, 0x21, 0 - .dw 0xa4c0, 0xc13e, 0xa4ff, 0xc13e, 0x21, 0 - .dw 0xa540, 0xc13e, 0xa57f, 0xc13e, 0x21, 0 - .dw 0xa5c0, 0xc13e, 0xa5ff, 0xc13e, 0x21, 0 - .dw 0xa640, 0xc13e, 0xa67f, 0xc13e, 0x21, 0 - .dw 0xa6c0, 0xc13e, 0xa6ff, 0xc13e, 0x21, 0 - .dw 0xa740, 0xc13e, 0xa77f, 0xc13e, 0x21, 0 - .dw 0xa7c0, 0xc13e, 0xa7ff, 0xc13e, 0x21, 0 - .dw 0xa840, 0xc13e, 0xa87f, 0xc13e, 0x21, 0 - .dw 0xa8c0, 0xc13e, 0xa8ff, 0xc13e, 0x21, 0 - .dw 0xa940, 0xc13e, 0xa97f, 0xc13e, 0x21, 0 - .dw 0xa9c0, 0xc13e, 0xa9ff, 0xc13e, 0x21, 0 - .dw 0xaa40, 0xc13e, 0xaa7f, 0xc13e, 0x21, 0 - .dw 0xaac0, 0xc13e, 0xaaff, 0xc13e, 0x21, 0 - .dw 0xab40, 0xc13e, 0xab7f, 0xc13e, 0x21, 0 - .dw 0xabc0, 0xc13e, 0xabff, 0xc13e, 0x21, 0 - .dw 0xac40, 0xc13e, 0xac7f, 0xc13e, 0x21, 0 - .dw 0xacc0, 0xc13e, 0xacff, 0xc13e, 0x21, 0 - .dw 0xad40, 0xc13e, 0xad7f, 0xc13e, 0x21, 0 - .dw 0xadc0, 0xc13e, 0xadff, 0xc13e, 0x21, 0 - .dw 0xae40, 0xc13e, 0xae7f, 0xc13e, 0x21, 0 - .dw 0xaec0, 0xc13e, 0xaeff, 0xc13e, 0x21, 0 - .dw 0xaf40, 0xc13e, 0xaf7f, 0xc13e, 0x21, 0 - .dw 0xafc0, 0xc13e, 0xafff, 0xc13e, 0x21, 0 - .dw 0xb040, 0xc13e, 0xb07f, 0xc13e, 0x21, 0 - .dw 0xb0c0, 0xc13e, 0xb0ff, 0xc13e, 0x21, 0 - .dw 0xb140, 0xc13e, 0xb17f, 0xc13e, 0x21, 0 - .dw 0xb1c0, 0xc13e, 0xb1ff, 0xc13e, 0x21, 0 - .dw 0xb240, 0xc13e, 0xb27f, 0xc13e, 0x21, 0 - .dw 0xb2c0, 0xc13e, 0xb2ff, 0xc13e, 0x21, 0 - .dw 0xb340, 0xc13e, 0xb37f, 0xc13e, 0x21, 0 - .dw 0xb3c0, 0xc13e, 0xb3ff, 0xc13e, 0x21, 0 - .dw 0xb440, 0xc13e, 0xb47f, 0xc13e, 0x21, 0 - .dw 0xb4c0, 0xc13e, 0xb4ff, 0xc13e, 0x21, 0 - .dw 0xb540, 0xc13e, 0xb57f, 0xc13e, 0x21, 0 - .dw 0xb5c0, 0xc13e, 0xb5ff, 0xc13e, 0x21, 0 - .dw 0xb640, 0xc13e, 0xb67f, 0xc13e, 0x21, 0 - .dw 0xb6c0, 0xc13e, 0xb6ff, 0xc13e, 0x21, 0 - .dw 0xb740, 0xc13e, 0xb77f, 0xc13e, 0x21, 0 - .dw 0xb7c0, 0xc13e, 0xb7ff, 0xc13e, 0x21, 0 - .dw 0xb840, 0xc13e, 0xb87f, 0xc13e, 0x21, 0 - .dw 0xb8c0, 0xc13e, 0xb8ff, 0xc13e, 0x21, 0 - .dw 0xb940, 0xc13e, 0xb97f, 0xc13e, 0x21, 0 - .dw 0xb9c0, 0xc13e, 0xbfff, 0xc13e, 0x21, 0 - .dw 0xc040, 0xc13e, 0xc07f, 0xc13e, 0x21, 0 - .dw 0xc0c0, 0xc13e, 0xc0ff, 0xc13e, 0x21, 0 - .dw 0xc140, 0xc13e, 0xc17f, 0xc13e, 0x21, 0 - .dw 0xc1c0, 0xc13e, 0xc1ff, 0xc13e, 0x21, 0 - .dw 0xc240, 0xc13e, 0xc27f, 0xc13e, 0x21, 0 - .dw 0xc2c0, 0xc13e, 0xc2ff, 0xc13e, 0x21, 0 - .dw 0xc340, 0xc13e, 0xc37f, 0xc13e, 0x21, 0 - .dw 0xc3c0, 0xc13e, 0xc3ff, 0xc13e, 0x21, 0 - .dw 0xc440, 0xc13e, 0xc47f, 0xc13e, 0x21, 0 - .dw 0xc4c0, 0xc13e, 0xc4ff, 0xc13e, 0x21, 0 - .dw 0xc540, 0xc13e, 0xc57f, 0xc13e, 0x21, 0 - .dw 0xc5c0, 0xc13e, 0xc5ff, 0xc13e, 0x21, 0 - .dw 0xc640, 0xc13e, 0xc67f, 0xc13e, 0x21, 0 - .dw 0xc6c0, 0xc13e, 0xc6ff, 0xc13e, 0x21, 0 - .dw 0xc740, 0xc13e, 0xc77f, 0xc13e, 0x21, 0 - .dw 0xc7c0, 0xc13e, 0xc7ff, 0xc13e, 0x21, 0 - .dw 0xc840, 0xc13e, 0xc87f, 0xc13e, 0x21, 0 - .dw 0xc8c0, 0xc13e, 0xc8ff, 0xc13e, 0x21, 0 - .dw 0xc940, 0xc13e, 0xc97f, 0xc13e, 0x21, 0 - .dw 0xc9c0, 0xc13e, 0xc9ff, 0xc13e, 0x21, 0 - .dw 0xca40, 0xc13e, 0xca7f, 0xc13e, 0x21, 0 - .dw 0xcac0, 0xc13e, 0xcaff, 0xc13e, 0x21, 0 - .dw 0xcb40, 0xc13e, 0xcb7f, 0xc13e, 0x21, 0 - .dw 0xcbc0, 0xc13e, 0xcbff, 0xc13e, 0x21, 0 - .dw 0xcc40, 0xc13e, 0xcc7f, 0xc13e, 0x21, 0 - .dw 0xccc0, 0xc13e, 0xccff, 0xc13e, 0x21, 0 - .dw 0xcd40, 0xc13e, 0xcd7f, 0xc13e, 0x21, 0 - .dw 0xcdc0, 0xc13e, 0xcdff, 0xc13e, 0x21, 0 - .dw 0xce40, 0xc13e, 0xce7f, 0xc13e, 0x21, 0 - .dw 0xcec0, 0xc13e, 0xceff, 0xc13e, 0x21, 0 - .dw 0xcf40, 0xc13e, 0xcf7f, 0xc13e, 0x21, 0 - .dw 0xcfc0, 0xc13e, 0xcfff, 0xc13e, 0x21, 0 - .dw 0xd040, 0xc13e, 0xd07f, 0xc13e, 0x21, 0 - .dw 0xd0c0, 0xc13e, 0xd0ff, 0xc13e, 0x21, 0 - .dw 0xd140, 0xc13e, 0xd17f, 0xc13e, 0x21, 0 - .dw 0xd1c0, 0xc13e, 0xd1ff, 0xc13e, 0x21, 0 - .dw 0xd240, 0xc13e, 0xd27f, 0xc13e, 0x21, 0 - .dw 0xd2c0, 0xc13e, 0xd2ff, 0xc13e, 0x21, 0 - .dw 0xd340, 0xc13e, 0xd37f, 0xc13e, 0x21, 0 - .dw 0xd3c0, 0xc13e, 0xd3ff, 0xc13e, 0x21, 0 - .dw 0xd440, 0xc13e, 0xd47f, 0xc13e, 0x21, 0 - .dw 0xd4c0, 0xc13e, 0xd4ff, 0xc13e, 0x21, 0 - .dw 0xd540, 0xc13e, 0xd57f, 0xc13e, 0x21, 0 - .dw 0xd5c0, 0xc13e, 0xd5ff, 0xc13e, 0x21, 0 - .dw 0xd640, 0xc13e, 0xd67f, 0xc13e, 0x21, 0 - .dw 0xd6c0, 0xc13e, 0xd6ff, 0xc13e, 0x21, 0 - .dw 0xd740, 0xc13e, 0xd77f, 0xc13e, 0x21, 0 - .dw 0xd7c0, 0xc13e, 0xd7ff, 0xc13e, 0x21, 0 - .dw 0xd840, 0xc13e, 0xd87f, 0xc13e, 0x21, 0 - .dw 0xd8c0, 0xc13e, 0xd8ff, 0xc13e, 0x21, 0 - .dw 0xd940, 0xc13e, 0xd97f, 0xc13e, 0x21, 0 - .dw 0xd9c0, 0xc13e, 0xdfff, 0xc13e, 0x21, 0 - .dw 0xe040, 0xc13e, 0xe07f, 0xc13e, 0x21, 0 - .dw 0xe0c0, 0xc13e, 0xe0ff, 0xc13e, 0x21, 0 - .dw 0xe140, 0xc13e, 0xe17f, 0xc13e, 0x21, 0 - .dw 0xe1c0, 0xc13e, 0xe1ff, 0xc13e, 0x21, 0 - .dw 0xe240, 0xc13e, 0xe27f, 0xc13e, 0x21, 0 - .dw 0xe2c0, 0xc13e, 0xe2ff, 0xc13e, 0x21, 0 - .dw 0xe340, 0xc13e, 0xe37f, 0xc13e, 0x21, 0 - .dw 0xe3c0, 0xc13e, 0xe3ff, 0xc13e, 0x21, 0 - .dw 0xe440, 0xc13e, 0xe47f, 0xc13e, 0x21, 0 - .dw 0xe4c0, 0xc13e, 0xe4ff, 0xc13e, 0x21, 0 - .dw 0xe540, 0xc13e, 0xe57f, 0xc13e, 0x21, 0 - .dw 0xe5c0, 0xc13e, 0xe5ff, 0xc13e, 0x21, 0 - .dw 0xe640, 0xc13e, 0xe67f, 0xc13e, 0x21, 0 - .dw 0xe6c0, 0xc13e, 0xe6ff, 0xc13e, 0x21, 0 - .dw 0xe740, 0xc13e, 0xe77f, 0xc13e, 0x21, 0 - .dw 0xe7c0, 0xc13e, 0xe7ff, 0xc13e, 0x21, 0 - .dw 0xe840, 0xc13e, 0xe87f, 0xc13e, 0x21, 0 - .dw 0xe8c0, 0xc13e, 0xe8ff, 0xc13e, 0x21, 0 - .dw 0xe940, 0xc13e, 0xe97f, 0xc13e, 0x21, 0 - .dw 0xe9c0, 0xc13e, 0xe9ff, 0xc13e, 0x21, 0 - .dw 0xea40, 0xc13e, 0xea7f, 0xc13e, 0x21, 0 - .dw 0xeac0, 0xc13e, 0xeaff, 0xc13e, 0x21, 0 - .dw 0xeb40, 0xc13e, 0xeb7f, 0xc13e, 0x21, 0 - .dw 0xebc0, 0xc13e, 0xebff, 0xc13e, 0x21, 0 - .dw 0xec40, 0xc13e, 0xec7f, 0xc13e, 0x21, 0 - .dw 0xecc0, 0xc13e, 0xecff, 0xc13e, 0x21, 0 - .dw 0xed40, 0xc13e, 0xed7f, 0xc13e, 0x21, 0 - .dw 0xedc0, 0xc13e, 0xedff, 0xc13e, 0x21, 0 - .dw 0xee40, 0xc13e, 0xee7f, 0xc13e, 0x21, 0 - .dw 0xeec0, 0xc13e, 0xeeff, 0xc13e, 0x21, 0 - .dw 0xef40, 0xc13e, 0xef7f, 0xc13e, 0x21, 0 - .dw 0xefc0, 0xc13e, 0xefff, 0xc13e, 0x21, 0 - .dw 0xf040, 0xc13e, 0xf07f, 0xc13e, 0x21, 0 - .dw 0xf0c0, 0xc13e, 0xf0ff, 0xc13e, 0x21, 0 - .dw 0xf140, 0xc13e, 0xf17f, 0xc13e, 0x21, 0 - .dw 0xf1c0, 0xc13e, 0xf1ff, 0xc13e, 0x21, 0 - .dw 0xf240, 0xc13e, 0xf27f, 0xc13e, 0x21, 0 - .dw 0xf2c0, 0xc13e, 0xf2ff, 0xc13e, 0x21, 0 - .dw 0xf340, 0xc13e, 0xf37f, 0xc13e, 0x21, 0 - .dw 0xf3c0, 0xc13e, 0xf3ff, 0xc13e, 0x21, 0 - .dw 0xf440, 0xc13e, 0xf47f, 0xc13e, 0x21, 0 - .dw 0xf4c0, 0xc13e, 0xf4ff, 0xc13e, 0x21, 0 - .dw 0xf540, 0xc13e, 0xf57f, 0xc13e, 0x21, 0 - .dw 0xf5c0, 0xc13e, 0xf5ff, 0xc13e, 0x21, 0 - .dw 0xf640, 0xc13e, 0xf67f, 0xc13e, 0x21, 0 - .dw 0xf6c0, 0xc13e, 0xf6ff, 0xc13e, 0x21, 0 - .dw 0xf740, 0xc13e, 0xf77f, 0xc13e, 0x21, 0 - .dw 0xf7c0, 0xc13e, 0xf7ff, 0xc13e, 0x21, 0 - .dw 0xf840, 0xc13e, 0xf87f, 0xc13e, 0x21, 0 - .dw 0xf8c0, 0xc13e, 0xf8ff, 0xc13e, 0x21, 0 - .dw 0xf940, 0xc13e, 0xf97f, 0xc13e, 0x21, 0 - .dw 0xf9c0, 0xc13e, 0xffff, 0xc13e, 0x21, 0 - .dw 0x0040, 0xc13f, 0x007f, 0xc13f, 0x21, 0 - .dw 0x00c0, 0xc13f, 0x00ff, 0xc13f, 0x21, 0 - .dw 0x0140, 0xc13f, 0x017f, 0xc13f, 0x21, 0 - .dw 0x01c0, 0xc13f, 0x01ff, 0xc13f, 0x21, 0 - .dw 0x0240, 0xc13f, 0x027f, 0xc13f, 0x21, 0 - .dw 0x02c0, 0xc13f, 0x02ff, 0xc13f, 0x21, 0 - .dw 0x0340, 0xc13f, 0x037f, 0xc13f, 0x21, 0 - .dw 0x03c0, 0xc13f, 0x03ff, 0xc13f, 0x21, 0 - .dw 0x0440, 0xc13f, 0x047f, 0xc13f, 0x21, 0 - .dw 0x04c0, 0xc13f, 0x04ff, 0xc13f, 0x21, 0 - .dw 0x0540, 0xc13f, 0x057f, 0xc13f, 0x21, 0 - .dw 0x05c0, 0xc13f, 0x05ff, 0xc13f, 0x21, 0 - .dw 0x0640, 0xc13f, 0x067f, 0xc13f, 0x21, 0 - .dw 0x06c0, 0xc13f, 0x06ff, 0xc13f, 0x21, 0 - .dw 0x0740, 0xc13f, 0x077f, 0xc13f, 0x21, 0 - .dw 0x07c0, 0xc13f, 0x07ff, 0xc13f, 0x21, 0 - .dw 0x0840, 0xc13f, 0x087f, 0xc13f, 0x21, 0 - .dw 0x08c0, 0xc13f, 0x08ff, 0xc13f, 0x21, 0 - .dw 0x0940, 0xc13f, 0x097f, 0xc13f, 0x21, 0 - .dw 0x09c0, 0xc13f, 0x09ff, 0xc13f, 0x21, 0 - .dw 0x0a40, 0xc13f, 0x0a7f, 0xc13f, 0x21, 0 - .dw 0x0ac0, 0xc13f, 0x0aff, 0xc13f, 0x21, 0 - .dw 0x0b40, 0xc13f, 0x0b7f, 0xc13f, 0x21, 0 - .dw 0x0bc0, 0xc13f, 0x0bff, 0xc13f, 0x21, 0 - .dw 0x0c40, 0xc13f, 0x0c7f, 0xc13f, 0x21, 0 - .dw 0x0cc0, 0xc13f, 0x0cff, 0xc13f, 0x21, 0 - .dw 0x0d40, 0xc13f, 0x0d7f, 0xc13f, 0x21, 0 - .dw 0x0dc0, 0xc13f, 0x0dff, 0xc13f, 0x21, 0 - .dw 0x0e40, 0xc13f, 0x0e7f, 0xc13f, 0x21, 0 - .dw 0x0ec0, 0xc13f, 0x0eff, 0xc13f, 0x21, 0 - .dw 0x0f40, 0xc13f, 0x0f7f, 0xc13f, 0x21, 0 - .dw 0x0fc0, 0xc13f, 0x0fff, 0xc13f, 0x21, 0 - .dw 0x1040, 0xc13f, 0x107f, 0xc13f, 0x21, 0 - .dw 0x10c0, 0xc13f, 0x10ff, 0xc13f, 0x21, 0 - .dw 0x1140, 0xc13f, 0x117f, 0xc13f, 0x21, 0 - .dw 0x11c0, 0xc13f, 0x11ff, 0xc13f, 0x21, 0 - .dw 0x1240, 0xc13f, 0x127f, 0xc13f, 0x21, 0 - .dw 0x12c0, 0xc13f, 0x12ff, 0xc13f, 0x21, 0 - .dw 0x1340, 0xc13f, 0x137f, 0xc13f, 0x21, 0 - .dw 0x13c0, 0xc13f, 0x13ff, 0xc13f, 0x21, 0 - .dw 0x1440, 0xc13f, 0x147f, 0xc13f, 0x21, 0 - .dw 0x14c0, 0xc13f, 0x14ff, 0xc13f, 0x21, 0 - .dw 0x1540, 0xc13f, 0x157f, 0xc13f, 0x21, 0 - .dw 0x15c0, 0xc13f, 0x15ff, 0xc13f, 0x21, 0 - .dw 0x1640, 0xc13f, 0x167f, 0xc13f, 0x21, 0 - .dw 0x16c0, 0xc13f, 0x16ff, 0xc13f, 0x21, 0 - .dw 0x1740, 0xc13f, 0x177f, 0xc13f, 0x21, 0 - .dw 0x17c0, 0xc13f, 0x17ff, 0xc13f, 0x21, 0 - .dw 0x1840, 0xc13f, 0x187f, 0xc13f, 0x21, 0 - .dw 0x18c0, 0xc13f, 0x18ff, 0xc13f, 0x21, 0 - .dw 0x1940, 0xc13f, 0x197f, 0xc13f, 0x21, 0 - .dw 0x19c0, 0xc13f, 0x1fff, 0xc13f, 0x21, 0 - .dw 0x2040, 0xc13f, 0x207f, 0xc13f, 0x21, 0 - .dw 0x20c0, 0xc13f, 0x20ff, 0xc13f, 0x21, 0 - .dw 0x2140, 0xc13f, 0x217f, 0xc13f, 0x21, 0 - .dw 0x21c0, 0xc13f, 0x21ff, 0xc13f, 0x21, 0 - .dw 0x2240, 0xc13f, 0x227f, 0xc13f, 0x21, 0 - .dw 0x22c0, 0xc13f, 0x22ff, 0xc13f, 0x21, 0 - .dw 0x2340, 0xc13f, 0x237f, 0xc13f, 0x21, 0 - .dw 0x23c0, 0xc13f, 0x23ff, 0xc13f, 0x21, 0 - .dw 0x2440, 0xc13f, 0x247f, 0xc13f, 0x21, 0 - .dw 0x24c0, 0xc13f, 0x24ff, 0xc13f, 0x21, 0 - .dw 0x2540, 0xc13f, 0x257f, 0xc13f, 0x21, 0 - .dw 0x25c0, 0xc13f, 0x25ff, 0xc13f, 0x21, 0 - .dw 0x2640, 0xc13f, 0x267f, 0xc13f, 0x21, 0 - .dw 0x26c0, 0xc13f, 0x26ff, 0xc13f, 0x21, 0 - .dw 0x2740, 0xc13f, 0x277f, 0xc13f, 0x21, 0 - .dw 0x27c0, 0xc13f, 0x27ff, 0xc13f, 0x21, 0 - .dw 0x2840, 0xc13f, 0x287f, 0xc13f, 0x21, 0 - .dw 0x28c0, 0xc13f, 0x28ff, 0xc13f, 0x21, 0 - .dw 0x2940, 0xc13f, 0x297f, 0xc13f, 0x21, 0 - .dw 0x29c0, 0xc13f, 0x29ff, 0xc13f, 0x21, 0 - .dw 0x2a40, 0xc13f, 0x2a7f, 0xc13f, 0x21, 0 - .dw 0x2ac0, 0xc13f, 0x2aff, 0xc13f, 0x21, 0 - .dw 0x2b40, 0xc13f, 0x2b7f, 0xc13f, 0x21, 0 - .dw 0x2bc0, 0xc13f, 0x2bff, 0xc13f, 0x21, 0 - .dw 0x2c40, 0xc13f, 0x2c7f, 0xc13f, 0x21, 0 - .dw 0x2cc0, 0xc13f, 0x2cff, 0xc13f, 0x21, 0 - .dw 0x2d40, 0xc13f, 0x2d7f, 0xc13f, 0x21, 0 - .dw 0x2dc0, 0xc13f, 0x2dff, 0xc13f, 0x21, 0 - .dw 0x2e40, 0xc13f, 0x2e7f, 0xc13f, 0x21, 0 - .dw 0x2ec0, 0xc13f, 0x2eff, 0xc13f, 0x21, 0 - .dw 0x2f40, 0xc13f, 0x2f7f, 0xc13f, 0x21, 0 - .dw 0x2fc0, 0xc13f, 0x2fff, 0xc13f, 0x21, 0 - .dw 0x3040, 0xc13f, 0x307f, 0xc13f, 0x21, 0 - .dw 0x30c0, 0xc13f, 0x30ff, 0xc13f, 0x21, 0 - .dw 0x3140, 0xc13f, 0x317f, 0xc13f, 0x21, 0 - .dw 0x31c0, 0xc13f, 0x31ff, 0xc13f, 0x21, 0 - .dw 0x3240, 0xc13f, 0x327f, 0xc13f, 0x21, 0 - .dw 0x32c0, 0xc13f, 0x32ff, 0xc13f, 0x21, 0 - .dw 0x3340, 0xc13f, 0x337f, 0xc13f, 0x21, 0 - .dw 0x33c0, 0xc13f, 0x33ff, 0xc13f, 0x21, 0 - .dw 0x3440, 0xc13f, 0x347f, 0xc13f, 0x21, 0 - .dw 0x34c0, 0xc13f, 0x34ff, 0xc13f, 0x21, 0 - .dw 0x3540, 0xc13f, 0x357f, 0xc13f, 0x21, 0 - .dw 0x35c0, 0xc13f, 0x35ff, 0xc13f, 0x21, 0 - .dw 0x3640, 0xc13f, 0x367f, 0xc13f, 0x21, 0 - .dw 0x36c0, 0xc13f, 0x36ff, 0xc13f, 0x21, 0 - .dw 0x3740, 0xc13f, 0x377f, 0xc13f, 0x21, 0 - .dw 0x37c0, 0xc13f, 0x37ff, 0xc13f, 0x21, 0 - .dw 0x3840, 0xc13f, 0x387f, 0xc13f, 0x21, 0 - .dw 0x38c0, 0xc13f, 0x38ff, 0xc13f, 0x21, 0 - .dw 0x3940, 0xc13f, 0x397f, 0xc13f, 0x21, 0 - .dw 0x39c0, 0xc13f, 0x1fff, 0xc160, 0x21, 0 - .dw 0x3a00, 0xc160, 0x5fff, 0xc160, 0x21, 0 - .dw 0x7a00, 0xc160, 0x9fff, 0xc160, 0x21, 0 - .dw 0xba00, 0xc160, 0xdfff, 0xc160, 0x21, 0 - .dw 0xfa00, 0xc160, 0x1fff, 0xc161, 0x21, 0 - .dw 0x3a00, 0xc161, 0x5fff, 0xc161, 0x21, 0 - .dw 0x7a00, 0xc161, 0x9fff, 0xc161, 0x21, 0 - .dw 0xba00, 0xc161, 0xdfff, 0xc161, 0x21, 0 - .dw 0xfa00, 0xc161, 0x1fff, 0xc162, 0x21, 0 - .dw 0x3a00, 0xc162, 0x5fff, 0xc162, 0x21, 0 - .dw 0x7a00, 0xc162, 0x9fff, 0xc162, 0x21, 0 - .dw 0xba00, 0xc162, 0xdfff, 0xc162, 0x21, 0 - .dw 0xfa00, 0xc162, 0x1fff, 0xc163, 0x21, 0 - .dw 0x3a00, 0xc163, 0xffff, 0xc163, 0x21, 0 - .dw 0x1a00, 0xc164, 0x1fff, 0xc164, 0x21, 0 - .dw 0x3a00, 0xc164, 0x3fff, 0xc164, 0x21, 0 - .dw 0x5a00, 0xc164, 0x5fff, 0xc164, 0x21, 0 - .dw 0x7a00, 0xc164, 0x7fff, 0xc164, 0x21, 0 - .dw 0x9a00, 0xc164, 0x9fff, 0xc164, 0x21, 0 - .dw 0xba00, 0xc164, 0xbfff, 0xc164, 0x21, 0 - .dw 0xda00, 0xc164, 0xdfff, 0xc164, 0x21, 0 - .dw 0xfa00, 0xc164, 0xffff, 0xc164, 0x21, 0 - .dw 0x1a00, 0xc165, 0x1fff, 0xc165, 0x21, 0 - .dw 0x3a00, 0xc165, 0x3fff, 0xc165, 0x21, 0 - .dw 0x5a00, 0xc165, 0x5fff, 0xc165, 0x21, 0 - .dw 0x7a00, 0xc165, 0x7fff, 0xc165, 0x21, 0 - .dw 0x9a00, 0xc165, 0x9fff, 0xc165, 0x21, 0 - .dw 0xba00, 0xc165, 0xbfff, 0xc165, 0x21, 0 - .dw 0xda00, 0xc165, 0xdfff, 0xc165, 0x21, 0 - .dw 0xfa00, 0xc165, 0xffff, 0xc165, 0x21, 0 - .dw 0x1a00, 0xc166, 0x1fff, 0xc166, 0x21, 0 - .dw 0x3a00, 0xc166, 0x3fff, 0xc166, 0x21, 0 - .dw 0x5a00, 0xc166, 0x5fff, 0xc166, 0x21, 0 - .dw 0x7a00, 0xc166, 0x7fff, 0xc166, 0x21, 0 - .dw 0x9a00, 0xc166, 0x9fff, 0xc166, 0x21, 0 - .dw 0xba00, 0xc166, 0xbfff, 0xc166, 0x21, 0 - .dw 0xda00, 0xc166, 0xdfff, 0xc166, 0x21, 0 - .dw 0xfa00, 0xc166, 0xffff, 0xc166, 0x21, 0 - .dw 0x1a00, 0xc167, 0x1fff, 0xc167, 0x21, 0 - .dw 0x3a00, 0xc167, 0x1fff, 0xc170, 0x21, 0 - .dw 0x3a00, 0xc170, 0x5fff, 0xc170, 0x21, 0 - .dw 0x7a00, 0xc170, 0x9fff, 0xc170, 0x21, 0 - .dw 0xba00, 0xc170, 0xdfff, 0xc170, 0x21, 0 - .dw 0xfa00, 0xc170, 0x1fff, 0xc171, 0x21, 0 - .dw 0x3a00, 0xc171, 0x5fff, 0xc171, 0x21, 0 - .dw 0x7a00, 0xc171, 0x9fff, 0xc171, 0x21, 0 - .dw 0xba00, 0xc171, 0xdfff, 0xc171, 0x21, 0 - .dw 0xfa00, 0xc171, 0x1fff, 0xc172, 0x21, 0 - .dw 0x3a00, 0xc172, 0x5fff, 0xc172, 0x21, 0 - .dw 0x7a00, 0xc172, 0x9fff, 0xc172, 0x21, 0 - .dw 0xba00, 0xc172, 0xdfff, 0xc172, 0x21, 0 - .dw 0xfa00, 0xc172, 0xffff, 0xc173, 0x21, 0 - .dw 0x1a00, 0xc174, 0x1fff, 0xc174, 0x21, 0 - .dw 0x3a00, 0xc174, 0x3fff, 0xc174, 0x21, 0 - .dw 0x5a00, 0xc174, 0x5fff, 0xc174, 0x21, 0 - .dw 0x7a00, 0xc174, 0x7fff, 0xc174, 0x21, 0 - .dw 0x9a00, 0xc174, 0x9fff, 0xc174, 0x21, 0 - .dw 0xba00, 0xc174, 0xbfff, 0xc174, 0x21, 0 - .dw 0xda00, 0xc174, 0xdfff, 0xc174, 0x21, 0 - .dw 0xfa00, 0xc174, 0xffff, 0xc174, 0x21, 0 - .dw 0x1a00, 0xc175, 0x1fff, 0xc175, 0x21, 0 - .dw 0x3a00, 0xc175, 0x3fff, 0xc175, 0x21, 0 - .dw 0x5a00, 0xc175, 0x5fff, 0xc175, 0x21, 0 - .dw 0x7a00, 0xc175, 0x7fff, 0xc175, 0x21, 0 - .dw 0x9a00, 0xc175, 0x9fff, 0xc175, 0x21, 0 - .dw 0xba00, 0xc175, 0xbfff, 0xc175, 0x21, 0 - .dw 0xda00, 0xc175, 0xdfff, 0xc175, 0x21, 0 - .dw 0xfa00, 0xc175, 0xffff, 0xc175, 0x21, 0 - .dw 0x1a00, 0xc176, 0x1fff, 0xc176, 0x21, 0 - .dw 0x3a00, 0xc176, 0x3fff, 0xc176, 0x21, 0 - .dw 0x5a00, 0xc176, 0x5fff, 0xc176, 0x21, 0 - .dw 0x7a00, 0xc176, 0x7fff, 0xc176, 0x21, 0 - .dw 0x9a00, 0xc176, 0x9fff, 0xc176, 0x21, 0 - .dw 0xba00, 0xc176, 0xbfff, 0xc176, 0x21, 0 - .dw 0xda00, 0xc176, 0xdfff, 0xc176, 0x21, 0 - .dw 0xfa00, 0xc176, 0xffff, 0xc176, 0x21, 0 - .dw 0x1a00, 0xc177, 0x1fff, 0xc177, 0x21, 0 - .dw 0x3a00, 0xc177, 0x1fff, 0xc180, 0x21, 0 - .dw 0x3a00, 0xc180, 0x5fff, 0xc180, 0x21, 0 - .dw 0x7a00, 0xc180, 0x9fff, 0xc180, 0x21, 0 - .dw 0xba00, 0xc180, 0xdfff, 0xc180, 0x21, 0 - .dw 0xfa00, 0xc180, 0x1fff, 0xc181, 0x21, 0 - .dw 0x3a00, 0xc181, 0x5fff, 0xc181, 0x21, 0 - .dw 0x7a00, 0xc181, 0x9fff, 0xc181, 0x21, 0 - .dw 0xba00, 0xc181, 0xdfff, 0xc181, 0x21, 0 - .dw 0xfa00, 0xc181, 0x1fff, 0xc182, 0x21, 0 - .dw 0x3a00, 0xc182, 0x5fff, 0xc182, 0x21, 0 - .dw 0x7a00, 0xc182, 0x9fff, 0xc182, 0x21, 0 - .dw 0xba00, 0xc182, 0xdfff, 0xc182, 0x21, 0 - .dw 0xfa00, 0xc182, 0x1fff, 0xc183, 0x21, 0 - .dw 0x3a00, 0xc183, 0xffff, 0xc183, 0x21, 0 - .dw 0x1a00, 0xc184, 0x1fff, 0xc184, 0x21, 0 - .dw 0x3a00, 0xc184, 0x3fff, 0xc184, 0x21, 0 - .dw 0x5a00, 0xc184, 0x5fff, 0xc184, 0x21, 0 - .dw 0x7a00, 0xc184, 0x7fff, 0xc184, 0x21, 0 - .dw 0x9a00, 0xc184, 0x9fff, 0xc184, 0x21, 0 - .dw 0xba00, 0xc184, 0xbfff, 0xc184, 0x21, 0 - .dw 0xda00, 0xc184, 0xdfff, 0xc184, 0x21, 0 - .dw 0xfa00, 0xc184, 0xffff, 0xc184, 0x21, 0 - .dw 0x1a00, 0xc185, 0x1fff, 0xc185, 0x21, 0 - .dw 0x3a00, 0xc185, 0x3fff, 0xc185, 0x21, 0 - .dw 0x5a00, 0xc185, 0x5fff, 0xc185, 0x21, 0 - .dw 0x7a00, 0xc185, 0x7fff, 0xc185, 0x21, 0 - .dw 0x9a00, 0xc185, 0x9fff, 0xc185, 0x21, 0 - .dw 0xba00, 0xc185, 0xbfff, 0xc185, 0x21, 0 - .dw 0xda00, 0xc185, 0xdfff, 0xc185, 0x21, 0 - .dw 0xfa00, 0xc185, 0xffff, 0xc185, 0x21, 0 - .dw 0x1a00, 0xc186, 0x1fff, 0xc186, 0x21, 0 - .dw 0x3a00, 0xc186, 0x3fff, 0xc186, 0x21, 0 - .dw 0x5a00, 0xc186, 0x5fff, 0xc186, 0x21, 0 - .dw 0x7a00, 0xc186, 0x7fff, 0xc186, 0x21, 0 - .dw 0x9a00, 0xc186, 0x9fff, 0xc186, 0x21, 0 - .dw 0xba00, 0xc186, 0xbfff, 0xc186, 0x21, 0 - .dw 0xda00, 0xc186, 0xdfff, 0xc186, 0x21, 0 - .dw 0xfa00, 0xc186, 0xffff, 0xc186, 0x21, 0 - .dw 0x1a00, 0xc187, 0x1fff, 0xc187, 0x21, 0 - .dw 0x3a00, 0xc187, 0x1fff, 0xc188, 0x21, 0 - .dw 0x2040, 0xc188, 0x207f, 0xc188, 0x21, 0 - .dw 0x20c0, 0xc188, 0x20ff, 0xc188, 0x21, 0 - .dw 0x2140, 0xc188, 0x217f, 0xc188, 0x21, 0 - .dw 0x21c0, 0xc188, 0x21ff, 0xc188, 0x21, 0 - .dw 0x2240, 0xc188, 0x227f, 0xc188, 0x21, 0 - .dw 0x22c0, 0xc188, 0x22ff, 0xc188, 0x21, 0 - .dw 0x2340, 0xc188, 0x237f, 0xc188, 0x21, 0 - .dw 0x23c0, 0xc188, 0x23ff, 0xc188, 0x21, 0 - .dw 0x2440, 0xc188, 0x247f, 0xc188, 0x21, 0 - .dw 0x24c0, 0xc188, 0x24ff, 0xc188, 0x21, 0 - .dw 0x2540, 0xc188, 0x257f, 0xc188, 0x21, 0 - .dw 0x25c0, 0xc188, 0x25ff, 0xc188, 0x21, 0 - .dw 0x2640, 0xc188, 0x267f, 0xc188, 0x21, 0 - .dw 0x26c0, 0xc188, 0x26ff, 0xc188, 0x21, 0 - .dw 0x2740, 0xc188, 0x277f, 0xc188, 0x21, 0 - .dw 0x27c0, 0xc188, 0x27ff, 0xc188, 0x21, 0 - .dw 0x2840, 0xc188, 0x287f, 0xc188, 0x21, 0 - .dw 0x28c0, 0xc188, 0x28ff, 0xc188, 0x21, 0 - .dw 0x2940, 0xc188, 0x297f, 0xc188, 0x21, 0 - .dw 0x29c0, 0xc188, 0x29ff, 0xc188, 0x21, 0 - .dw 0x2a40, 0xc188, 0x2a7f, 0xc188, 0x21, 0 - .dw 0x2ac0, 0xc188, 0x2aff, 0xc188, 0x21, 0 - .dw 0x2b40, 0xc188, 0x2b7f, 0xc188, 0x21, 0 - .dw 0x2bc0, 0xc188, 0x2bff, 0xc188, 0x21, 0 - .dw 0x2c40, 0xc188, 0x2c7f, 0xc188, 0x21, 0 - .dw 0x2cc0, 0xc188, 0x2cff, 0xc188, 0x21, 0 - .dw 0x2d40, 0xc188, 0x2d7f, 0xc188, 0x21, 0 - .dw 0x2dc0, 0xc188, 0x2dff, 0xc188, 0x21, 0 - .dw 0x2e40, 0xc188, 0x2e7f, 0xc188, 0x21, 0 - .dw 0x2ec0, 0xc188, 0x2eff, 0xc188, 0x21, 0 - .dw 0x2f40, 0xc188, 0x2f7f, 0xc188, 0x21, 0 - .dw 0x2fc0, 0xc188, 0x2fff, 0xc188, 0x21, 0 - .dw 0x3040, 0xc188, 0x307f, 0xc188, 0x21, 0 - .dw 0x30c0, 0xc188, 0x30ff, 0xc188, 0x21, 0 - .dw 0x3140, 0xc188, 0x317f, 0xc188, 0x21, 0 - .dw 0x31c0, 0xc188, 0x31ff, 0xc188, 0x21, 0 - .dw 0x3240, 0xc188, 0x327f, 0xc188, 0x21, 0 - .dw 0x32c0, 0xc188, 0x32ff, 0xc188, 0x21, 0 - .dw 0x3340, 0xc188, 0x337f, 0xc188, 0x21, 0 - .dw 0x33c0, 0xc188, 0x33ff, 0xc188, 0x21, 0 - .dw 0x3440, 0xc188, 0x347f, 0xc188, 0x21, 0 - .dw 0x34c0, 0xc188, 0x34ff, 0xc188, 0x21, 0 - .dw 0x3540, 0xc188, 0x357f, 0xc188, 0x21, 0 - .dw 0x35c0, 0xc188, 0x35ff, 0xc188, 0x21, 0 - .dw 0x3640, 0xc188, 0x367f, 0xc188, 0x21, 0 - .dw 0x36c0, 0xc188, 0x36ff, 0xc188, 0x21, 0 - .dw 0x3740, 0xc188, 0x377f, 0xc188, 0x21, 0 - .dw 0x37c0, 0xc188, 0x37ff, 0xc188, 0x21, 0 - .dw 0x3840, 0xc188, 0x387f, 0xc188, 0x21, 0 - .dw 0x38c0, 0xc188, 0x38ff, 0xc188, 0x21, 0 - .dw 0x3940, 0xc188, 0x397f, 0xc188, 0x21, 0 - .dw 0x39c0, 0xc188, 0x5fff, 0xc188, 0x21, 0 - .dw 0x6040, 0xc188, 0x607f, 0xc188, 0x21, 0 - .dw 0x60c0, 0xc188, 0x60ff, 0xc188, 0x21, 0 - .dw 0x6140, 0xc188, 0x617f, 0xc188, 0x21, 0 - .dw 0x61c0, 0xc188, 0x61ff, 0xc188, 0x21, 0 - .dw 0x6240, 0xc188, 0x627f, 0xc188, 0x21, 0 - .dw 0x62c0, 0xc188, 0x62ff, 0xc188, 0x21, 0 - .dw 0x6340, 0xc188, 0x637f, 0xc188, 0x21, 0 - .dw 0x63c0, 0xc188, 0x63ff, 0xc188, 0x21, 0 - .dw 0x6440, 0xc188, 0x647f, 0xc188, 0x21, 0 - .dw 0x64c0, 0xc188, 0x64ff, 0xc188, 0x21, 0 - .dw 0x6540, 0xc188, 0x657f, 0xc188, 0x21, 0 - .dw 0x65c0, 0xc188, 0x65ff, 0xc188, 0x21, 0 - .dw 0x6640, 0xc188, 0x667f, 0xc188, 0x21, 0 - .dw 0x66c0, 0xc188, 0x66ff, 0xc188, 0x21, 0 - .dw 0x6740, 0xc188, 0x677f, 0xc188, 0x21, 0 - .dw 0x67c0, 0xc188, 0x67ff, 0xc188, 0x21, 0 - .dw 0x6840, 0xc188, 0x687f, 0xc188, 0x21, 0 - .dw 0x68c0, 0xc188, 0x68ff, 0xc188, 0x21, 0 - .dw 0x6940, 0xc188, 0x697f, 0xc188, 0x21, 0 - .dw 0x69c0, 0xc188, 0x69ff, 0xc188, 0x21, 0 - .dw 0x6a40, 0xc188, 0x6a7f, 0xc188, 0x21, 0 - .dw 0x6ac0, 0xc188, 0x6aff, 0xc188, 0x21, 0 - .dw 0x6b40, 0xc188, 0x6b7f, 0xc188, 0x21, 0 - .dw 0x6bc0, 0xc188, 0x6bff, 0xc188, 0x21, 0 - .dw 0x6c40, 0xc188, 0x6c7f, 0xc188, 0x21, 0 - .dw 0x6cc0, 0xc188, 0x6cff, 0xc188, 0x21, 0 - .dw 0x6d40, 0xc188, 0x6d7f, 0xc188, 0x21, 0 - .dw 0x6dc0, 0xc188, 0x6dff, 0xc188, 0x21, 0 - .dw 0x6e40, 0xc188, 0x6e7f, 0xc188, 0x21, 0 - .dw 0x6ec0, 0xc188, 0x6eff, 0xc188, 0x21, 0 - .dw 0x6f40, 0xc188, 0x6f7f, 0xc188, 0x21, 0 - .dw 0x6fc0, 0xc188, 0x6fff, 0xc188, 0x21, 0 - .dw 0x7040, 0xc188, 0x707f, 0xc188, 0x21, 0 - .dw 0x70c0, 0xc188, 0x70ff, 0xc188, 0x21, 0 - .dw 0x7140, 0xc188, 0x717f, 0xc188, 0x21, 0 - .dw 0x71c0, 0xc188, 0x71ff, 0xc188, 0x21, 0 - .dw 0x7240, 0xc188, 0x727f, 0xc188, 0x21, 0 - .dw 0x72c0, 0xc188, 0x72ff, 0xc188, 0x21, 0 - .dw 0x7340, 0xc188, 0x737f, 0xc188, 0x21, 0 - .dw 0x73c0, 0xc188, 0x73ff, 0xc188, 0x21, 0 - .dw 0x7440, 0xc188, 0x747f, 0xc188, 0x21, 0 - .dw 0x74c0, 0xc188, 0x74ff, 0xc188, 0x21, 0 - .dw 0x7540, 0xc188, 0x757f, 0xc188, 0x21, 0 - .dw 0x75c0, 0xc188, 0x75ff, 0xc188, 0x21, 0 - .dw 0x7640, 0xc188, 0x767f, 0xc188, 0x21, 0 - .dw 0x76c0, 0xc188, 0x76ff, 0xc188, 0x21, 0 - .dw 0x7740, 0xc188, 0x777f, 0xc188, 0x21, 0 - .dw 0x77c0, 0xc188, 0x77ff, 0xc188, 0x21, 0 - .dw 0x7840, 0xc188, 0x787f, 0xc188, 0x21, 0 - .dw 0x78c0, 0xc188, 0x78ff, 0xc188, 0x21, 0 - .dw 0x7940, 0xc188, 0x797f, 0xc188, 0x21, 0 - .dw 0x79c0, 0xc188, 0x9fff, 0xc188, 0x21, 0 - .dw 0xa040, 0xc188, 0xa07f, 0xc188, 0x21, 0 - .dw 0xa0c0, 0xc188, 0xa0ff, 0xc188, 0x21, 0 - .dw 0xa140, 0xc188, 0xa17f, 0xc188, 0x21, 0 - .dw 0xa1c0, 0xc188, 0xa1ff, 0xc188, 0x21, 0 - .dw 0xa240, 0xc188, 0xa27f, 0xc188, 0x21, 0 - .dw 0xa2c0, 0xc188, 0xa2ff, 0xc188, 0x21, 0 - .dw 0xa340, 0xc188, 0xa37f, 0xc188, 0x21, 0 - .dw 0xa3c0, 0xc188, 0xa3ff, 0xc188, 0x21, 0 - .dw 0xa440, 0xc188, 0xa47f, 0xc188, 0x21, 0 - .dw 0xa4c0, 0xc188, 0xa4ff, 0xc188, 0x21, 0 - .dw 0xa540, 0xc188, 0xa57f, 0xc188, 0x21, 0 - .dw 0xa5c0, 0xc188, 0xa5ff, 0xc188, 0x21, 0 - .dw 0xa640, 0xc188, 0xa67f, 0xc188, 0x21, 0 - .dw 0xa6c0, 0xc188, 0xa6ff, 0xc188, 0x21, 0 - .dw 0xa740, 0xc188, 0xa77f, 0xc188, 0x21, 0 - .dw 0xa7c0, 0xc188, 0xa7ff, 0xc188, 0x21, 0 - .dw 0xa840, 0xc188, 0xa87f, 0xc188, 0x21, 0 - .dw 0xa8c0, 0xc188, 0xa8ff, 0xc188, 0x21, 0 - .dw 0xa940, 0xc188, 0xa97f, 0xc188, 0x21, 0 - .dw 0xa9c0, 0xc188, 0xa9ff, 0xc188, 0x21, 0 - .dw 0xaa40, 0xc188, 0xaa7f, 0xc188, 0x21, 0 - .dw 0xaac0, 0xc188, 0xaaff, 0xc188, 0x21, 0 - .dw 0xab40, 0xc188, 0xab7f, 0xc188, 0x21, 0 - .dw 0xabc0, 0xc188, 0xabff, 0xc188, 0x21, 0 - .dw 0xac40, 0xc188, 0xac7f, 0xc188, 0x21, 0 - .dw 0xacc0, 0xc188, 0xacff, 0xc188, 0x21, 0 - .dw 0xad40, 0xc188, 0xad7f, 0xc188, 0x21, 0 - .dw 0xadc0, 0xc188, 0xadff, 0xc188, 0x21, 0 - .dw 0xae40, 0xc188, 0xae7f, 0xc188, 0x21, 0 - .dw 0xaec0, 0xc188, 0xaeff, 0xc188, 0x21, 0 - .dw 0xaf40, 0xc188, 0xaf7f, 0xc188, 0x21, 0 - .dw 0xafc0, 0xc188, 0xafff, 0xc188, 0x21, 0 - .dw 0xb040, 0xc188, 0xb07f, 0xc188, 0x21, 0 - .dw 0xb0c0, 0xc188, 0xb0ff, 0xc188, 0x21, 0 - .dw 0xb140, 0xc188, 0xb17f, 0xc188, 0x21, 0 - .dw 0xb1c0, 0xc188, 0xb1ff, 0xc188, 0x21, 0 - .dw 0xb240, 0xc188, 0xb27f, 0xc188, 0x21, 0 - .dw 0xb2c0, 0xc188, 0xb2ff, 0xc188, 0x21, 0 - .dw 0xb340, 0xc188, 0xb37f, 0xc188, 0x21, 0 - .dw 0xb3c0, 0xc188, 0xb3ff, 0xc188, 0x21, 0 - .dw 0xb440, 0xc188, 0xb47f, 0xc188, 0x21, 0 - .dw 0xb4c0, 0xc188, 0xb4ff, 0xc188, 0x21, 0 - .dw 0xb540, 0xc188, 0xb57f, 0xc188, 0x21, 0 - .dw 0xb5c0, 0xc188, 0xb5ff, 0xc188, 0x21, 0 - .dw 0xb640, 0xc188, 0xb67f, 0xc188, 0x21, 0 - .dw 0xb6c0, 0xc188, 0xb6ff, 0xc188, 0x21, 0 - .dw 0xb740, 0xc188, 0xb77f, 0xc188, 0x21, 0 - .dw 0xb7c0, 0xc188, 0xb7ff, 0xc188, 0x21, 0 - .dw 0xb840, 0xc188, 0xb87f, 0xc188, 0x21, 0 - .dw 0xb8c0, 0xc188, 0xb8ff, 0xc188, 0x21, 0 - .dw 0xb940, 0xc188, 0xb97f, 0xc188, 0x21, 0 - .dw 0xb9c0, 0xc188, 0xdfff, 0xc188, 0x21, 0 - .dw 0xe040, 0xc188, 0xe07f, 0xc188, 0x21, 0 - .dw 0xe0c0, 0xc188, 0xe0ff, 0xc188, 0x21, 0 - .dw 0xe140, 0xc188, 0xe17f, 0xc188, 0x21, 0 - .dw 0xe1c0, 0xc188, 0xe1ff, 0xc188, 0x21, 0 - .dw 0xe240, 0xc188, 0xe27f, 0xc188, 0x21, 0 - .dw 0xe2c0, 0xc188, 0xe2ff, 0xc188, 0x21, 0 - .dw 0xe340, 0xc188, 0xe37f, 0xc188, 0x21, 0 - .dw 0xe3c0, 0xc188, 0xe3ff, 0xc188, 0x21, 0 - .dw 0xe440, 0xc188, 0xe47f, 0xc188, 0x21, 0 - .dw 0xe4c0, 0xc188, 0xe4ff, 0xc188, 0x21, 0 - .dw 0xe540, 0xc188, 0xe57f, 0xc188, 0x21, 0 - .dw 0xe5c0, 0xc188, 0xe5ff, 0xc188, 0x21, 0 - .dw 0xe640, 0xc188, 0xe67f, 0xc188, 0x21, 0 - .dw 0xe6c0, 0xc188, 0xe6ff, 0xc188, 0x21, 0 - .dw 0xe740, 0xc188, 0xe77f, 0xc188, 0x21, 0 - .dw 0xe7c0, 0xc188, 0xe7ff, 0xc188, 0x21, 0 - .dw 0xe840, 0xc188, 0xe87f, 0xc188, 0x21, 0 - .dw 0xe8c0, 0xc188, 0xe8ff, 0xc188, 0x21, 0 - .dw 0xe940, 0xc188, 0xe97f, 0xc188, 0x21, 0 - .dw 0xe9c0, 0xc188, 0xe9ff, 0xc188, 0x21, 0 - .dw 0xea40, 0xc188, 0xea7f, 0xc188, 0x21, 0 - .dw 0xeac0, 0xc188, 0xeaff, 0xc188, 0x21, 0 - .dw 0xeb40, 0xc188, 0xeb7f, 0xc188, 0x21, 0 - .dw 0xebc0, 0xc188, 0xebff, 0xc188, 0x21, 0 - .dw 0xec40, 0xc188, 0xec7f, 0xc188, 0x21, 0 - .dw 0xecc0, 0xc188, 0xecff, 0xc188, 0x21, 0 - .dw 0xed40, 0xc188, 0xed7f, 0xc188, 0x21, 0 - .dw 0xedc0, 0xc188, 0xedff, 0xc188, 0x21, 0 - .dw 0xee40, 0xc188, 0xee7f, 0xc188, 0x21, 0 - .dw 0xeec0, 0xc188, 0xeeff, 0xc188, 0x21, 0 - .dw 0xef40, 0xc188, 0xef7f, 0xc188, 0x21, 0 - .dw 0xefc0, 0xc188, 0xefff, 0xc188, 0x21, 0 - .dw 0xf040, 0xc188, 0xf07f, 0xc188, 0x21, 0 - .dw 0xf0c0, 0xc188, 0xf0ff, 0xc188, 0x21, 0 - .dw 0xf140, 0xc188, 0xf17f, 0xc188, 0x21, 0 - .dw 0xf1c0, 0xc188, 0xf1ff, 0xc188, 0x21, 0 - .dw 0xf240, 0xc188, 0xf27f, 0xc188, 0x21, 0 - .dw 0xf2c0, 0xc188, 0xf2ff, 0xc188, 0x21, 0 - .dw 0xf340, 0xc188, 0xf37f, 0xc188, 0x21, 0 - .dw 0xf3c0, 0xc188, 0xf3ff, 0xc188, 0x21, 0 - .dw 0xf440, 0xc188, 0xf47f, 0xc188, 0x21, 0 - .dw 0xf4c0, 0xc188, 0xf4ff, 0xc188, 0x21, 0 - .dw 0xf540, 0xc188, 0xf57f, 0xc188, 0x21, 0 - .dw 0xf5c0, 0xc188, 0xf5ff, 0xc188, 0x21, 0 - .dw 0xf640, 0xc188, 0xf67f, 0xc188, 0x21, 0 - .dw 0xf6c0, 0xc188, 0xf6ff, 0xc188, 0x21, 0 - .dw 0xf740, 0xc188, 0xf77f, 0xc188, 0x21, 0 - .dw 0xf7c0, 0xc188, 0xf7ff, 0xc188, 0x21, 0 - .dw 0xf840, 0xc188, 0xf87f, 0xc188, 0x21, 0 - .dw 0xf8c0, 0xc188, 0xf8ff, 0xc188, 0x21, 0 - .dw 0xf940, 0xc188, 0xf97f, 0xc188, 0x21, 0 - .dw 0xf9c0, 0xc188, 0x1fff, 0xc189, 0x21, 0 - .dw 0x2040, 0xc189, 0x207f, 0xc189, 0x21, 0 - .dw 0x20c0, 0xc189, 0x20ff, 0xc189, 0x21, 0 - .dw 0x2140, 0xc189, 0x217f, 0xc189, 0x21, 0 - .dw 0x21c0, 0xc189, 0x21ff, 0xc189, 0x21, 0 - .dw 0x2240, 0xc189, 0x227f, 0xc189, 0x21, 0 - .dw 0x22c0, 0xc189, 0x22ff, 0xc189, 0x21, 0 - .dw 0x2340, 0xc189, 0x237f, 0xc189, 0x21, 0 - .dw 0x23c0, 0xc189, 0x23ff, 0xc189, 0x21, 0 - .dw 0x2440, 0xc189, 0x247f, 0xc189, 0x21, 0 - .dw 0x24c0, 0xc189, 0x24ff, 0xc189, 0x21, 0 - .dw 0x2540, 0xc189, 0x257f, 0xc189, 0x21, 0 - .dw 0x25c0, 0xc189, 0x25ff, 0xc189, 0x21, 0 - .dw 0x2640, 0xc189, 0x267f, 0xc189, 0x21, 0 - .dw 0x26c0, 0xc189, 0x26ff, 0xc189, 0x21, 0 - .dw 0x2740, 0xc189, 0x277f, 0xc189, 0x21, 0 - .dw 0x27c0, 0xc189, 0x27ff, 0xc189, 0x21, 0 - .dw 0x2840, 0xc189, 0x287f, 0xc189, 0x21, 0 - .dw 0x28c0, 0xc189, 0x28ff, 0xc189, 0x21, 0 - .dw 0x2940, 0xc189, 0x297f, 0xc189, 0x21, 0 - .dw 0x29c0, 0xc189, 0x29ff, 0xc189, 0x21, 0 - .dw 0x2a40, 0xc189, 0x2a7f, 0xc189, 0x21, 0 - .dw 0x2ac0, 0xc189, 0x2aff, 0xc189, 0x21, 0 - .dw 0x2b40, 0xc189, 0x2b7f, 0xc189, 0x21, 0 - .dw 0x2bc0, 0xc189, 0x2bff, 0xc189, 0x21, 0 - .dw 0x2c40, 0xc189, 0x2c7f, 0xc189, 0x21, 0 - .dw 0x2cc0, 0xc189, 0x2cff, 0xc189, 0x21, 0 - .dw 0x2d40, 0xc189, 0x2d7f, 0xc189, 0x21, 0 - .dw 0x2dc0, 0xc189, 0x2dff, 0xc189, 0x21, 0 - .dw 0x2e40, 0xc189, 0x2e7f, 0xc189, 0x21, 0 - .dw 0x2ec0, 0xc189, 0x2eff, 0xc189, 0x21, 0 - .dw 0x2f40, 0xc189, 0x2f7f, 0xc189, 0x21, 0 - .dw 0x2fc0, 0xc189, 0x2fff, 0xc189, 0x21, 0 - .dw 0x3040, 0xc189, 0x307f, 0xc189, 0x21, 0 - .dw 0x30c0, 0xc189, 0x30ff, 0xc189, 0x21, 0 - .dw 0x3140, 0xc189, 0x317f, 0xc189, 0x21, 0 - .dw 0x31c0, 0xc189, 0x31ff, 0xc189, 0x21, 0 - .dw 0x3240, 0xc189, 0x327f, 0xc189, 0x21, 0 - .dw 0x32c0, 0xc189, 0x32ff, 0xc189, 0x21, 0 - .dw 0x3340, 0xc189, 0x337f, 0xc189, 0x21, 0 - .dw 0x33c0, 0xc189, 0x33ff, 0xc189, 0x21, 0 - .dw 0x3440, 0xc189, 0x347f, 0xc189, 0x21, 0 - .dw 0x34c0, 0xc189, 0x34ff, 0xc189, 0x21, 0 - .dw 0x3540, 0xc189, 0x357f, 0xc189, 0x21, 0 - .dw 0x35c0, 0xc189, 0x35ff, 0xc189, 0x21, 0 - .dw 0x3640, 0xc189, 0x367f, 0xc189, 0x21, 0 - .dw 0x36c0, 0xc189, 0x36ff, 0xc189, 0x21, 0 - .dw 0x3740, 0xc189, 0x377f, 0xc189, 0x21, 0 - .dw 0x37c0, 0xc189, 0x37ff, 0xc189, 0x21, 0 - .dw 0x3840, 0xc189, 0x387f, 0xc189, 0x21, 0 - .dw 0x38c0, 0xc189, 0x38ff, 0xc189, 0x21, 0 - .dw 0x3940, 0xc189, 0x397f, 0xc189, 0x21, 0 - .dw 0x39c0, 0xc189, 0x5fff, 0xc189, 0x21, 0 - .dw 0x6040, 0xc189, 0x607f, 0xc189, 0x21, 0 - .dw 0x60c0, 0xc189, 0x60ff, 0xc189, 0x21, 0 - .dw 0x6140, 0xc189, 0x617f, 0xc189, 0x21, 0 - .dw 0x61c0, 0xc189, 0x61ff, 0xc189, 0x21, 0 - .dw 0x6240, 0xc189, 0x627f, 0xc189, 0x21, 0 - .dw 0x62c0, 0xc189, 0x62ff, 0xc189, 0x21, 0 - .dw 0x6340, 0xc189, 0x637f, 0xc189, 0x21, 0 - .dw 0x63c0, 0xc189, 0x63ff, 0xc189, 0x21, 0 - .dw 0x6440, 0xc189, 0x647f, 0xc189, 0x21, 0 - .dw 0x64c0, 0xc189, 0x64ff, 0xc189, 0x21, 0 - .dw 0x6540, 0xc189, 0x657f, 0xc189, 0x21, 0 - .dw 0x65c0, 0xc189, 0x65ff, 0xc189, 0x21, 0 - .dw 0x6640, 0xc189, 0x667f, 0xc189, 0x21, 0 - .dw 0x66c0, 0xc189, 0x66ff, 0xc189, 0x21, 0 - .dw 0x6740, 0xc189, 0x677f, 0xc189, 0x21, 0 - .dw 0x67c0, 0xc189, 0x67ff, 0xc189, 0x21, 0 - .dw 0x6840, 0xc189, 0x687f, 0xc189, 0x21, 0 - .dw 0x68c0, 0xc189, 0x68ff, 0xc189, 0x21, 0 - .dw 0x6940, 0xc189, 0x697f, 0xc189, 0x21, 0 - .dw 0x69c0, 0xc189, 0x69ff, 0xc189, 0x21, 0 - .dw 0x6a40, 0xc189, 0x6a7f, 0xc189, 0x21, 0 - .dw 0x6ac0, 0xc189, 0x6aff, 0xc189, 0x21, 0 - .dw 0x6b40, 0xc189, 0x6b7f, 0xc189, 0x21, 0 - .dw 0x6bc0, 0xc189, 0x6bff, 0xc189, 0x21, 0 - .dw 0x6c40, 0xc189, 0x6c7f, 0xc189, 0x21, 0 - .dw 0x6cc0, 0xc189, 0x6cff, 0xc189, 0x21, 0 - .dw 0x6d40, 0xc189, 0x6d7f, 0xc189, 0x21, 0 - .dw 0x6dc0, 0xc189, 0x6dff, 0xc189, 0x21, 0 - .dw 0x6e40, 0xc189, 0x6e7f, 0xc189, 0x21, 0 - .dw 0x6ec0, 0xc189, 0x6eff, 0xc189, 0x21, 0 - .dw 0x6f40, 0xc189, 0x6f7f, 0xc189, 0x21, 0 - .dw 0x6fc0, 0xc189, 0x6fff, 0xc189, 0x21, 0 - .dw 0x7040, 0xc189, 0x707f, 0xc189, 0x21, 0 - .dw 0x70c0, 0xc189, 0x70ff, 0xc189, 0x21, 0 - .dw 0x7140, 0xc189, 0x717f, 0xc189, 0x21, 0 - .dw 0x71c0, 0xc189, 0x71ff, 0xc189, 0x21, 0 - .dw 0x7240, 0xc189, 0x727f, 0xc189, 0x21, 0 - .dw 0x72c0, 0xc189, 0x72ff, 0xc189, 0x21, 0 - .dw 0x7340, 0xc189, 0x737f, 0xc189, 0x21, 0 - .dw 0x73c0, 0xc189, 0x73ff, 0xc189, 0x21, 0 - .dw 0x7440, 0xc189, 0x747f, 0xc189, 0x21, 0 - .dw 0x74c0, 0xc189, 0x74ff, 0xc189, 0x21, 0 - .dw 0x7540, 0xc189, 0x757f, 0xc189, 0x21, 0 - .dw 0x75c0, 0xc189, 0x75ff, 0xc189, 0x21, 0 - .dw 0x7640, 0xc189, 0x767f, 0xc189, 0x21, 0 - .dw 0x76c0, 0xc189, 0x76ff, 0xc189, 0x21, 0 - .dw 0x7740, 0xc189, 0x777f, 0xc189, 0x21, 0 - .dw 0x77c0, 0xc189, 0x77ff, 0xc189, 0x21, 0 - .dw 0x7840, 0xc189, 0x787f, 0xc189, 0x21, 0 - .dw 0x78c0, 0xc189, 0x78ff, 0xc189, 0x21, 0 - .dw 0x7940, 0xc189, 0x797f, 0xc189, 0x21, 0 - .dw 0x79c0, 0xc189, 0x9fff, 0xc189, 0x21, 0 - .dw 0xa040, 0xc189, 0xa07f, 0xc189, 0x21, 0 - .dw 0xa0c0, 0xc189, 0xa0ff, 0xc189, 0x21, 0 - .dw 0xa140, 0xc189, 0xa17f, 0xc189, 0x21, 0 - .dw 0xa1c0, 0xc189, 0xa1ff, 0xc189, 0x21, 0 - .dw 0xa240, 0xc189, 0xa27f, 0xc189, 0x21, 0 - .dw 0xa2c0, 0xc189, 0xa2ff, 0xc189, 0x21, 0 - .dw 0xa340, 0xc189, 0xa37f, 0xc189, 0x21, 0 - .dw 0xa3c0, 0xc189, 0xa3ff, 0xc189, 0x21, 0 - .dw 0xa440, 0xc189, 0xa47f, 0xc189, 0x21, 0 - .dw 0xa4c0, 0xc189, 0xa4ff, 0xc189, 0x21, 0 - .dw 0xa540, 0xc189, 0xa57f, 0xc189, 0x21, 0 - .dw 0xa5c0, 0xc189, 0xa5ff, 0xc189, 0x21, 0 - .dw 0xa640, 0xc189, 0xa67f, 0xc189, 0x21, 0 - .dw 0xa6c0, 0xc189, 0xa6ff, 0xc189, 0x21, 0 - .dw 0xa740, 0xc189, 0xa77f, 0xc189, 0x21, 0 - .dw 0xa7c0, 0xc189, 0xa7ff, 0xc189, 0x21, 0 - .dw 0xa840, 0xc189, 0xa87f, 0xc189, 0x21, 0 - .dw 0xa8c0, 0xc189, 0xa8ff, 0xc189, 0x21, 0 - .dw 0xa940, 0xc189, 0xa97f, 0xc189, 0x21, 0 - .dw 0xa9c0, 0xc189, 0xa9ff, 0xc189, 0x21, 0 - .dw 0xaa40, 0xc189, 0xaa7f, 0xc189, 0x21, 0 - .dw 0xaac0, 0xc189, 0xaaff, 0xc189, 0x21, 0 - .dw 0xab40, 0xc189, 0xab7f, 0xc189, 0x21, 0 - .dw 0xabc0, 0xc189, 0xabff, 0xc189, 0x21, 0 - .dw 0xac40, 0xc189, 0xac7f, 0xc189, 0x21, 0 - .dw 0xacc0, 0xc189, 0xacff, 0xc189, 0x21, 0 - .dw 0xad40, 0xc189, 0xad7f, 0xc189, 0x21, 0 - .dw 0xadc0, 0xc189, 0xadff, 0xc189, 0x21, 0 - .dw 0xae40, 0xc189, 0xae7f, 0xc189, 0x21, 0 - .dw 0xaec0, 0xc189, 0xaeff, 0xc189, 0x21, 0 - .dw 0xaf40, 0xc189, 0xaf7f, 0xc189, 0x21, 0 - .dw 0xafc0, 0xc189, 0xafff, 0xc189, 0x21, 0 - .dw 0xb040, 0xc189, 0xb07f, 0xc189, 0x21, 0 - .dw 0xb0c0, 0xc189, 0xb0ff, 0xc189, 0x21, 0 - .dw 0xb140, 0xc189, 0xb17f, 0xc189, 0x21, 0 - .dw 0xb1c0, 0xc189, 0xb1ff, 0xc189, 0x21, 0 - .dw 0xb240, 0xc189, 0xb27f, 0xc189, 0x21, 0 - .dw 0xb2c0, 0xc189, 0xb2ff, 0xc189, 0x21, 0 - .dw 0xb340, 0xc189, 0xb37f, 0xc189, 0x21, 0 - .dw 0xb3c0, 0xc189, 0xb3ff, 0xc189, 0x21, 0 - .dw 0xb440, 0xc189, 0xb47f, 0xc189, 0x21, 0 - .dw 0xb4c0, 0xc189, 0xb4ff, 0xc189, 0x21, 0 - .dw 0xb540, 0xc189, 0xb57f, 0xc189, 0x21, 0 - .dw 0xb5c0, 0xc189, 0xb5ff, 0xc189, 0x21, 0 - .dw 0xb640, 0xc189, 0xb67f, 0xc189, 0x21, 0 - .dw 0xb6c0, 0xc189, 0xb6ff, 0xc189, 0x21, 0 - .dw 0xb740, 0xc189, 0xb77f, 0xc189, 0x21, 0 - .dw 0xb7c0, 0xc189, 0xb7ff, 0xc189, 0x21, 0 - .dw 0xb840, 0xc189, 0xb87f, 0xc189, 0x21, 0 - .dw 0xb8c0, 0xc189, 0xb8ff, 0xc189, 0x21, 0 - .dw 0xb940, 0xc189, 0xb97f, 0xc189, 0x21, 0 - .dw 0xb9c0, 0xc189, 0xdfff, 0xc189, 0x21, 0 - .dw 0xe040, 0xc189, 0xe07f, 0xc189, 0x21, 0 - .dw 0xe0c0, 0xc189, 0xe0ff, 0xc189, 0x21, 0 - .dw 0xe140, 0xc189, 0xe17f, 0xc189, 0x21, 0 - .dw 0xe1c0, 0xc189, 0xe1ff, 0xc189, 0x21, 0 - .dw 0xe240, 0xc189, 0xe27f, 0xc189, 0x21, 0 - .dw 0xe2c0, 0xc189, 0xe2ff, 0xc189, 0x21, 0 - .dw 0xe340, 0xc189, 0xe37f, 0xc189, 0x21, 0 - .dw 0xe3c0, 0xc189, 0xe3ff, 0xc189, 0x21, 0 - .dw 0xe440, 0xc189, 0xe47f, 0xc189, 0x21, 0 - .dw 0xe4c0, 0xc189, 0xe4ff, 0xc189, 0x21, 0 - .dw 0xe540, 0xc189, 0xe57f, 0xc189, 0x21, 0 - .dw 0xe5c0, 0xc189, 0xe5ff, 0xc189, 0x21, 0 - .dw 0xe640, 0xc189, 0xe67f, 0xc189, 0x21, 0 - .dw 0xe6c0, 0xc189, 0xe6ff, 0xc189, 0x21, 0 - .dw 0xe740, 0xc189, 0xe77f, 0xc189, 0x21, 0 - .dw 0xe7c0, 0xc189, 0xe7ff, 0xc189, 0x21, 0 - .dw 0xe840, 0xc189, 0xe87f, 0xc189, 0x21, 0 - .dw 0xe8c0, 0xc189, 0xe8ff, 0xc189, 0x21, 0 - .dw 0xe940, 0xc189, 0xe97f, 0xc189, 0x21, 0 - .dw 0xe9c0, 0xc189, 0xe9ff, 0xc189, 0x21, 0 - .dw 0xea40, 0xc189, 0xea7f, 0xc189, 0x21, 0 - .dw 0xeac0, 0xc189, 0xeaff, 0xc189, 0x21, 0 - .dw 0xeb40, 0xc189, 0xeb7f, 0xc189, 0x21, 0 - .dw 0xebc0, 0xc189, 0xebff, 0xc189, 0x21, 0 - .dw 0xec40, 0xc189, 0xec7f, 0xc189, 0x21, 0 - .dw 0xecc0, 0xc189, 0xecff, 0xc189, 0x21, 0 - .dw 0xed40, 0xc189, 0xed7f, 0xc189, 0x21, 0 - .dw 0xedc0, 0xc189, 0xedff, 0xc189, 0x21, 0 - .dw 0xee40, 0xc189, 0xee7f, 0xc189, 0x21, 0 - .dw 0xeec0, 0xc189, 0xeeff, 0xc189, 0x21, 0 - .dw 0xef40, 0xc189, 0xef7f, 0xc189, 0x21, 0 - .dw 0xefc0, 0xc189, 0xefff, 0xc189, 0x21, 0 - .dw 0xf040, 0xc189, 0xf07f, 0xc189, 0x21, 0 - .dw 0xf0c0, 0xc189, 0xf0ff, 0xc189, 0x21, 0 - .dw 0xf140, 0xc189, 0xf17f, 0xc189, 0x21, 0 - .dw 0xf1c0, 0xc189, 0xf1ff, 0xc189, 0x21, 0 - .dw 0xf240, 0xc189, 0xf27f, 0xc189, 0x21, 0 - .dw 0xf2c0, 0xc189, 0xf2ff, 0xc189, 0x21, 0 - .dw 0xf340, 0xc189, 0xf37f, 0xc189, 0x21, 0 - .dw 0xf3c0, 0xc189, 0xf3ff, 0xc189, 0x21, 0 - .dw 0xf440, 0xc189, 0xf47f, 0xc189, 0x21, 0 - .dw 0xf4c0, 0xc189, 0xf4ff, 0xc189, 0x21, 0 - .dw 0xf540, 0xc189, 0xf57f, 0xc189, 0x21, 0 - .dw 0xf5c0, 0xc189, 0xf5ff, 0xc189, 0x21, 0 - .dw 0xf640, 0xc189, 0xf67f, 0xc189, 0x21, 0 - .dw 0xf6c0, 0xc189, 0xf6ff, 0xc189, 0x21, 0 - .dw 0xf740, 0xc189, 0xf77f, 0xc189, 0x21, 0 - .dw 0xf7c0, 0xc189, 0xf7ff, 0xc189, 0x21, 0 - .dw 0xf840, 0xc189, 0xf87f, 0xc189, 0x21, 0 - .dw 0xf8c0, 0xc189, 0xf8ff, 0xc189, 0x21, 0 - .dw 0xf940, 0xc189, 0xf97f, 0xc189, 0x21, 0 - .dw 0xf9c0, 0xc189, 0x1fff, 0xc18a, 0x21, 0 - .dw 0x2040, 0xc18a, 0x207f, 0xc18a, 0x21, 0 - .dw 0x20c0, 0xc18a, 0x20ff, 0xc18a, 0x21, 0 - .dw 0x2140, 0xc18a, 0x217f, 0xc18a, 0x21, 0 - .dw 0x21c0, 0xc18a, 0x21ff, 0xc18a, 0x21, 0 - .dw 0x2240, 0xc18a, 0x227f, 0xc18a, 0x21, 0 - .dw 0x22c0, 0xc18a, 0x22ff, 0xc18a, 0x21, 0 - .dw 0x2340, 0xc18a, 0x237f, 0xc18a, 0x21, 0 - .dw 0x23c0, 0xc18a, 0x23ff, 0xc18a, 0x21, 0 - .dw 0x2440, 0xc18a, 0x247f, 0xc18a, 0x21, 0 - .dw 0x24c0, 0xc18a, 0x24ff, 0xc18a, 0x21, 0 - .dw 0x2540, 0xc18a, 0x257f, 0xc18a, 0x21, 0 - .dw 0x25c0, 0xc18a, 0x25ff, 0xc18a, 0x21, 0 - .dw 0x2640, 0xc18a, 0x267f, 0xc18a, 0x21, 0 - .dw 0x26c0, 0xc18a, 0x26ff, 0xc18a, 0x21, 0 - .dw 0x2740, 0xc18a, 0x277f, 0xc18a, 0x21, 0 - .dw 0x27c0, 0xc18a, 0x27ff, 0xc18a, 0x21, 0 - .dw 0x2840, 0xc18a, 0x287f, 0xc18a, 0x21, 0 - .dw 0x28c0, 0xc18a, 0x28ff, 0xc18a, 0x21, 0 - .dw 0x2940, 0xc18a, 0x297f, 0xc18a, 0x21, 0 - .dw 0x29c0, 0xc18a, 0x29ff, 0xc18a, 0x21, 0 - .dw 0x2a40, 0xc18a, 0x2a7f, 0xc18a, 0x21, 0 - .dw 0x2ac0, 0xc18a, 0x2aff, 0xc18a, 0x21, 0 - .dw 0x2b40, 0xc18a, 0x2b7f, 0xc18a, 0x21, 0 - .dw 0x2bc0, 0xc18a, 0x2bff, 0xc18a, 0x21, 0 - .dw 0x2c40, 0xc18a, 0x2c7f, 0xc18a, 0x21, 0 - .dw 0x2cc0, 0xc18a, 0x2cff, 0xc18a, 0x21, 0 - .dw 0x2d40, 0xc18a, 0x2d7f, 0xc18a, 0x21, 0 - .dw 0x2dc0, 0xc18a, 0x2dff, 0xc18a, 0x21, 0 - .dw 0x2e40, 0xc18a, 0x2e7f, 0xc18a, 0x21, 0 - .dw 0x2ec0, 0xc18a, 0x2eff, 0xc18a, 0x21, 0 - .dw 0x2f40, 0xc18a, 0x2f7f, 0xc18a, 0x21, 0 - .dw 0x2fc0, 0xc18a, 0x2fff, 0xc18a, 0x21, 0 - .dw 0x3040, 0xc18a, 0x307f, 0xc18a, 0x21, 0 - .dw 0x30c0, 0xc18a, 0x30ff, 0xc18a, 0x21, 0 - .dw 0x3140, 0xc18a, 0x317f, 0xc18a, 0x21, 0 - .dw 0x31c0, 0xc18a, 0x31ff, 0xc18a, 0x21, 0 - .dw 0x3240, 0xc18a, 0x327f, 0xc18a, 0x21, 0 - .dw 0x32c0, 0xc18a, 0x32ff, 0xc18a, 0x21, 0 - .dw 0x3340, 0xc18a, 0x337f, 0xc18a, 0x21, 0 - .dw 0x33c0, 0xc18a, 0x33ff, 0xc18a, 0x21, 0 - .dw 0x3440, 0xc18a, 0x347f, 0xc18a, 0x21, 0 - .dw 0x34c0, 0xc18a, 0x34ff, 0xc18a, 0x21, 0 - .dw 0x3540, 0xc18a, 0x357f, 0xc18a, 0x21, 0 - .dw 0x35c0, 0xc18a, 0x35ff, 0xc18a, 0x21, 0 - .dw 0x3640, 0xc18a, 0x367f, 0xc18a, 0x21, 0 - .dw 0x36c0, 0xc18a, 0x36ff, 0xc18a, 0x21, 0 - .dw 0x3740, 0xc18a, 0x377f, 0xc18a, 0x21, 0 - .dw 0x37c0, 0xc18a, 0x37ff, 0xc18a, 0x21, 0 - .dw 0x3840, 0xc18a, 0x387f, 0xc18a, 0x21, 0 - .dw 0x38c0, 0xc18a, 0x38ff, 0xc18a, 0x21, 0 - .dw 0x3940, 0xc18a, 0x397f, 0xc18a, 0x21, 0 - .dw 0x39c0, 0xc18a, 0x5fff, 0xc18a, 0x21, 0 - .dw 0x6040, 0xc18a, 0x607f, 0xc18a, 0x21, 0 - .dw 0x60c0, 0xc18a, 0x60ff, 0xc18a, 0x21, 0 - .dw 0x6140, 0xc18a, 0x617f, 0xc18a, 0x21, 0 - .dw 0x61c0, 0xc18a, 0x61ff, 0xc18a, 0x21, 0 - .dw 0x6240, 0xc18a, 0x627f, 0xc18a, 0x21, 0 - .dw 0x62c0, 0xc18a, 0x62ff, 0xc18a, 0x21, 0 - .dw 0x6340, 0xc18a, 0x637f, 0xc18a, 0x21, 0 - .dw 0x63c0, 0xc18a, 0x63ff, 0xc18a, 0x21, 0 - .dw 0x6440, 0xc18a, 0x647f, 0xc18a, 0x21, 0 - .dw 0x64c0, 0xc18a, 0x64ff, 0xc18a, 0x21, 0 - .dw 0x6540, 0xc18a, 0x657f, 0xc18a, 0x21, 0 - .dw 0x65c0, 0xc18a, 0x65ff, 0xc18a, 0x21, 0 - .dw 0x6640, 0xc18a, 0x667f, 0xc18a, 0x21, 0 - .dw 0x66c0, 0xc18a, 0x66ff, 0xc18a, 0x21, 0 - .dw 0x6740, 0xc18a, 0x677f, 0xc18a, 0x21, 0 - .dw 0x67c0, 0xc18a, 0x67ff, 0xc18a, 0x21, 0 - .dw 0x6840, 0xc18a, 0x687f, 0xc18a, 0x21, 0 - .dw 0x68c0, 0xc18a, 0x68ff, 0xc18a, 0x21, 0 - .dw 0x6940, 0xc18a, 0x697f, 0xc18a, 0x21, 0 - .dw 0x69c0, 0xc18a, 0x69ff, 0xc18a, 0x21, 0 - .dw 0x6a40, 0xc18a, 0x6a7f, 0xc18a, 0x21, 0 - .dw 0x6ac0, 0xc18a, 0x6aff, 0xc18a, 0x21, 0 - .dw 0x6b40, 0xc18a, 0x6b7f, 0xc18a, 0x21, 0 - .dw 0x6bc0, 0xc18a, 0x6bff, 0xc18a, 0x21, 0 - .dw 0x6c40, 0xc18a, 0x6c7f, 0xc18a, 0x21, 0 - .dw 0x6cc0, 0xc18a, 0x6cff, 0xc18a, 0x21, 0 - .dw 0x6d40, 0xc18a, 0x6d7f, 0xc18a, 0x21, 0 - .dw 0x6dc0, 0xc18a, 0x6dff, 0xc18a, 0x21, 0 - .dw 0x6e40, 0xc18a, 0x6e7f, 0xc18a, 0x21, 0 - .dw 0x6ec0, 0xc18a, 0x6eff, 0xc18a, 0x21, 0 - .dw 0x6f40, 0xc18a, 0x6f7f, 0xc18a, 0x21, 0 - .dw 0x6fc0, 0xc18a, 0x6fff, 0xc18a, 0x21, 0 - .dw 0x7040, 0xc18a, 0x707f, 0xc18a, 0x21, 0 - .dw 0x70c0, 0xc18a, 0x70ff, 0xc18a, 0x21, 0 - .dw 0x7140, 0xc18a, 0x717f, 0xc18a, 0x21, 0 - .dw 0x71c0, 0xc18a, 0x71ff, 0xc18a, 0x21, 0 - .dw 0x7240, 0xc18a, 0x727f, 0xc18a, 0x21, 0 - .dw 0x72c0, 0xc18a, 0x72ff, 0xc18a, 0x21, 0 - .dw 0x7340, 0xc18a, 0x737f, 0xc18a, 0x21, 0 - .dw 0x73c0, 0xc18a, 0x73ff, 0xc18a, 0x21, 0 - .dw 0x7440, 0xc18a, 0x747f, 0xc18a, 0x21, 0 - .dw 0x74c0, 0xc18a, 0x74ff, 0xc18a, 0x21, 0 - .dw 0x7540, 0xc18a, 0x757f, 0xc18a, 0x21, 0 - .dw 0x75c0, 0xc18a, 0x75ff, 0xc18a, 0x21, 0 - .dw 0x7640, 0xc18a, 0x767f, 0xc18a, 0x21, 0 - .dw 0x76c0, 0xc18a, 0x76ff, 0xc18a, 0x21, 0 - .dw 0x7740, 0xc18a, 0x777f, 0xc18a, 0x21, 0 - .dw 0x77c0, 0xc18a, 0x77ff, 0xc18a, 0x21, 0 - .dw 0x7840, 0xc18a, 0x787f, 0xc18a, 0x21, 0 - .dw 0x78c0, 0xc18a, 0x78ff, 0xc18a, 0x21, 0 - .dw 0x7940, 0xc18a, 0x797f, 0xc18a, 0x21, 0 - .dw 0x79c0, 0xc18a, 0x9fff, 0xc18a, 0x21, 0 - .dw 0xa040, 0xc18a, 0xa07f, 0xc18a, 0x21, 0 - .dw 0xa0c0, 0xc18a, 0xa0ff, 0xc18a, 0x21, 0 - .dw 0xa140, 0xc18a, 0xa17f, 0xc18a, 0x21, 0 - .dw 0xa1c0, 0xc18a, 0xa1ff, 0xc18a, 0x21, 0 - .dw 0xa240, 0xc18a, 0xa27f, 0xc18a, 0x21, 0 - .dw 0xa2c0, 0xc18a, 0xa2ff, 0xc18a, 0x21, 0 - .dw 0xa340, 0xc18a, 0xa37f, 0xc18a, 0x21, 0 - .dw 0xa3c0, 0xc18a, 0xa3ff, 0xc18a, 0x21, 0 - .dw 0xa440, 0xc18a, 0xa47f, 0xc18a, 0x21, 0 - .dw 0xa4c0, 0xc18a, 0xa4ff, 0xc18a, 0x21, 0 - .dw 0xa540, 0xc18a, 0xa57f, 0xc18a, 0x21, 0 - .dw 0xa5c0, 0xc18a, 0xa5ff, 0xc18a, 0x21, 0 - .dw 0xa640, 0xc18a, 0xa67f, 0xc18a, 0x21, 0 - .dw 0xa6c0, 0xc18a, 0xa6ff, 0xc18a, 0x21, 0 - .dw 0xa740, 0xc18a, 0xa77f, 0xc18a, 0x21, 0 - .dw 0xa7c0, 0xc18a, 0xa7ff, 0xc18a, 0x21, 0 - .dw 0xa840, 0xc18a, 0xa87f, 0xc18a, 0x21, 0 - .dw 0xa8c0, 0xc18a, 0xa8ff, 0xc18a, 0x21, 0 - .dw 0xa940, 0xc18a, 0xa97f, 0xc18a, 0x21, 0 - .dw 0xa9c0, 0xc18a, 0xa9ff, 0xc18a, 0x21, 0 - .dw 0xaa40, 0xc18a, 0xaa7f, 0xc18a, 0x21, 0 - .dw 0xaac0, 0xc18a, 0xaaff, 0xc18a, 0x21, 0 - .dw 0xab40, 0xc18a, 0xab7f, 0xc18a, 0x21, 0 - .dw 0xabc0, 0xc18a, 0xabff, 0xc18a, 0x21, 0 - .dw 0xac40, 0xc18a, 0xac7f, 0xc18a, 0x21, 0 - .dw 0xacc0, 0xc18a, 0xacff, 0xc18a, 0x21, 0 - .dw 0xad40, 0xc18a, 0xad7f, 0xc18a, 0x21, 0 - .dw 0xadc0, 0xc18a, 0xadff, 0xc18a, 0x21, 0 - .dw 0xae40, 0xc18a, 0xae7f, 0xc18a, 0x21, 0 - .dw 0xaec0, 0xc18a, 0xaeff, 0xc18a, 0x21, 0 - .dw 0xaf40, 0xc18a, 0xaf7f, 0xc18a, 0x21, 0 - .dw 0xafc0, 0xc18a, 0xafff, 0xc18a, 0x21, 0 - .dw 0xb040, 0xc18a, 0xb07f, 0xc18a, 0x21, 0 - .dw 0xb0c0, 0xc18a, 0xb0ff, 0xc18a, 0x21, 0 - .dw 0xb140, 0xc18a, 0xb17f, 0xc18a, 0x21, 0 - .dw 0xb1c0, 0xc18a, 0xb1ff, 0xc18a, 0x21, 0 - .dw 0xb240, 0xc18a, 0xb27f, 0xc18a, 0x21, 0 - .dw 0xb2c0, 0xc18a, 0xb2ff, 0xc18a, 0x21, 0 - .dw 0xb340, 0xc18a, 0xb37f, 0xc18a, 0x21, 0 - .dw 0xb3c0, 0xc18a, 0xb3ff, 0xc18a, 0x21, 0 - .dw 0xb440, 0xc18a, 0xb47f, 0xc18a, 0x21, 0 - .dw 0xb4c0, 0xc18a, 0xb4ff, 0xc18a, 0x21, 0 - .dw 0xb540, 0xc18a, 0xb57f, 0xc18a, 0x21, 0 - .dw 0xb5c0, 0xc18a, 0xb5ff, 0xc18a, 0x21, 0 - .dw 0xb640, 0xc18a, 0xb67f, 0xc18a, 0x21, 0 - .dw 0xb6c0, 0xc18a, 0xb6ff, 0xc18a, 0x21, 0 - .dw 0xb740, 0xc18a, 0xb77f, 0xc18a, 0x21, 0 - .dw 0xb7c0, 0xc18a, 0xb7ff, 0xc18a, 0x21, 0 - .dw 0xb840, 0xc18a, 0xb87f, 0xc18a, 0x21, 0 - .dw 0xb8c0, 0xc18a, 0xb8ff, 0xc18a, 0x21, 0 - .dw 0xb940, 0xc18a, 0xb97f, 0xc18a, 0x21, 0 - .dw 0xb9c0, 0xc18a, 0xdfff, 0xc18a, 0x21, 0 - .dw 0xe040, 0xc18a, 0xe07f, 0xc18a, 0x21, 0 - .dw 0xe0c0, 0xc18a, 0xe0ff, 0xc18a, 0x21, 0 - .dw 0xe140, 0xc18a, 0xe17f, 0xc18a, 0x21, 0 - .dw 0xe1c0, 0xc18a, 0xe1ff, 0xc18a, 0x21, 0 - .dw 0xe240, 0xc18a, 0xe27f, 0xc18a, 0x21, 0 - .dw 0xe2c0, 0xc18a, 0xe2ff, 0xc18a, 0x21, 0 - .dw 0xe340, 0xc18a, 0xe37f, 0xc18a, 0x21, 0 - .dw 0xe3c0, 0xc18a, 0xe3ff, 0xc18a, 0x21, 0 - .dw 0xe440, 0xc18a, 0xe47f, 0xc18a, 0x21, 0 - .dw 0xe4c0, 0xc18a, 0xe4ff, 0xc18a, 0x21, 0 - .dw 0xe540, 0xc18a, 0xe57f, 0xc18a, 0x21, 0 - .dw 0xe5c0, 0xc18a, 0xe5ff, 0xc18a, 0x21, 0 - .dw 0xe640, 0xc18a, 0xe67f, 0xc18a, 0x21, 0 - .dw 0xe6c0, 0xc18a, 0xe6ff, 0xc18a, 0x21, 0 - .dw 0xe740, 0xc18a, 0xe77f, 0xc18a, 0x21, 0 - .dw 0xe7c0, 0xc18a, 0xe7ff, 0xc18a, 0x21, 0 - .dw 0xe840, 0xc18a, 0xe87f, 0xc18a, 0x21, 0 - .dw 0xe8c0, 0xc18a, 0xe8ff, 0xc18a, 0x21, 0 - .dw 0xe940, 0xc18a, 0xe97f, 0xc18a, 0x21, 0 - .dw 0xe9c0, 0xc18a, 0xe9ff, 0xc18a, 0x21, 0 - .dw 0xea40, 0xc18a, 0xea7f, 0xc18a, 0x21, 0 - .dw 0xeac0, 0xc18a, 0xeaff, 0xc18a, 0x21, 0 - .dw 0xeb40, 0xc18a, 0xeb7f, 0xc18a, 0x21, 0 - .dw 0xebc0, 0xc18a, 0xebff, 0xc18a, 0x21, 0 - .dw 0xec40, 0xc18a, 0xec7f, 0xc18a, 0x21, 0 - .dw 0xecc0, 0xc18a, 0xecff, 0xc18a, 0x21, 0 - .dw 0xed40, 0xc18a, 0xed7f, 0xc18a, 0x21, 0 - .dw 0xedc0, 0xc18a, 0xedff, 0xc18a, 0x21, 0 - .dw 0xee40, 0xc18a, 0xee7f, 0xc18a, 0x21, 0 - .dw 0xeec0, 0xc18a, 0xeeff, 0xc18a, 0x21, 0 - .dw 0xef40, 0xc18a, 0xef7f, 0xc18a, 0x21, 0 - .dw 0xefc0, 0xc18a, 0xefff, 0xc18a, 0x21, 0 - .dw 0xf040, 0xc18a, 0xf07f, 0xc18a, 0x21, 0 - .dw 0xf0c0, 0xc18a, 0xf0ff, 0xc18a, 0x21, 0 - .dw 0xf140, 0xc18a, 0xf17f, 0xc18a, 0x21, 0 - .dw 0xf1c0, 0xc18a, 0xf1ff, 0xc18a, 0x21, 0 - .dw 0xf240, 0xc18a, 0xf27f, 0xc18a, 0x21, 0 - .dw 0xf2c0, 0xc18a, 0xf2ff, 0xc18a, 0x21, 0 - .dw 0xf340, 0xc18a, 0xf37f, 0xc18a, 0x21, 0 - .dw 0xf3c0, 0xc18a, 0xf3ff, 0xc18a, 0x21, 0 - .dw 0xf440, 0xc18a, 0xf47f, 0xc18a, 0x21, 0 - .dw 0xf4c0, 0xc18a, 0xf4ff, 0xc18a, 0x21, 0 - .dw 0xf540, 0xc18a, 0xf57f, 0xc18a, 0x21, 0 - .dw 0xf5c0, 0xc18a, 0xf5ff, 0xc18a, 0x21, 0 - .dw 0xf640, 0xc18a, 0xf67f, 0xc18a, 0x21, 0 - .dw 0xf6c0, 0xc18a, 0xf6ff, 0xc18a, 0x21, 0 - .dw 0xf740, 0xc18a, 0xf77f, 0xc18a, 0x21, 0 - .dw 0xf7c0, 0xc18a, 0xf7ff, 0xc18a, 0x21, 0 - .dw 0xf840, 0xc18a, 0xf87f, 0xc18a, 0x21, 0 - .dw 0xf8c0, 0xc18a, 0xf8ff, 0xc18a, 0x21, 0 - .dw 0xf940, 0xc18a, 0xf97f, 0xc18a, 0x21, 0 - .dw 0xf9c0, 0xc18a, 0x1fff, 0xc18b, 0x21, 0 - .dw 0x2040, 0xc18b, 0x207f, 0xc18b, 0x21, 0 - .dw 0x20c0, 0xc18b, 0x20ff, 0xc18b, 0x21, 0 - .dw 0x2140, 0xc18b, 0x217f, 0xc18b, 0x21, 0 - .dw 0x21c0, 0xc18b, 0x21ff, 0xc18b, 0x21, 0 - .dw 0x2240, 0xc18b, 0x227f, 0xc18b, 0x21, 0 - .dw 0x22c0, 0xc18b, 0x22ff, 0xc18b, 0x21, 0 - .dw 0x2340, 0xc18b, 0x237f, 0xc18b, 0x21, 0 - .dw 0x23c0, 0xc18b, 0x23ff, 0xc18b, 0x21, 0 - .dw 0x2440, 0xc18b, 0x247f, 0xc18b, 0x21, 0 - .dw 0x24c0, 0xc18b, 0x24ff, 0xc18b, 0x21, 0 - .dw 0x2540, 0xc18b, 0x257f, 0xc18b, 0x21, 0 - .dw 0x25c0, 0xc18b, 0x25ff, 0xc18b, 0x21, 0 - .dw 0x2640, 0xc18b, 0x267f, 0xc18b, 0x21, 0 - .dw 0x26c0, 0xc18b, 0x26ff, 0xc18b, 0x21, 0 - .dw 0x2740, 0xc18b, 0x277f, 0xc18b, 0x21, 0 - .dw 0x27c0, 0xc18b, 0x27ff, 0xc18b, 0x21, 0 - .dw 0x2840, 0xc18b, 0x287f, 0xc18b, 0x21, 0 - .dw 0x28c0, 0xc18b, 0x28ff, 0xc18b, 0x21, 0 - .dw 0x2940, 0xc18b, 0x297f, 0xc18b, 0x21, 0 - .dw 0x29c0, 0xc18b, 0x29ff, 0xc18b, 0x21, 0 - .dw 0x2a40, 0xc18b, 0x2a7f, 0xc18b, 0x21, 0 - .dw 0x2ac0, 0xc18b, 0x2aff, 0xc18b, 0x21, 0 - .dw 0x2b40, 0xc18b, 0x2b7f, 0xc18b, 0x21, 0 - .dw 0x2bc0, 0xc18b, 0x2bff, 0xc18b, 0x21, 0 - .dw 0x2c40, 0xc18b, 0x2c7f, 0xc18b, 0x21, 0 - .dw 0x2cc0, 0xc18b, 0x2cff, 0xc18b, 0x21, 0 - .dw 0x2d40, 0xc18b, 0x2d7f, 0xc18b, 0x21, 0 - .dw 0x2dc0, 0xc18b, 0x2dff, 0xc18b, 0x21, 0 - .dw 0x2e40, 0xc18b, 0x2e7f, 0xc18b, 0x21, 0 - .dw 0x2ec0, 0xc18b, 0x2eff, 0xc18b, 0x21, 0 - .dw 0x2f40, 0xc18b, 0x2f7f, 0xc18b, 0x21, 0 - .dw 0x2fc0, 0xc18b, 0x2fff, 0xc18b, 0x21, 0 - .dw 0x3040, 0xc18b, 0x307f, 0xc18b, 0x21, 0 - .dw 0x30c0, 0xc18b, 0x30ff, 0xc18b, 0x21, 0 - .dw 0x3140, 0xc18b, 0x317f, 0xc18b, 0x21, 0 - .dw 0x31c0, 0xc18b, 0x31ff, 0xc18b, 0x21, 0 - .dw 0x3240, 0xc18b, 0x327f, 0xc18b, 0x21, 0 - .dw 0x32c0, 0xc18b, 0x32ff, 0xc18b, 0x21, 0 - .dw 0x3340, 0xc18b, 0x337f, 0xc18b, 0x21, 0 - .dw 0x33c0, 0xc18b, 0x33ff, 0xc18b, 0x21, 0 - .dw 0x3440, 0xc18b, 0x347f, 0xc18b, 0x21, 0 - .dw 0x34c0, 0xc18b, 0x34ff, 0xc18b, 0x21, 0 - .dw 0x3540, 0xc18b, 0x357f, 0xc18b, 0x21, 0 - .dw 0x35c0, 0xc18b, 0x35ff, 0xc18b, 0x21, 0 - .dw 0x3640, 0xc18b, 0x367f, 0xc18b, 0x21, 0 - .dw 0x36c0, 0xc18b, 0x36ff, 0xc18b, 0x21, 0 - .dw 0x3740, 0xc18b, 0x377f, 0xc18b, 0x21, 0 - .dw 0x37c0, 0xc18b, 0x37ff, 0xc18b, 0x21, 0 - .dw 0x3840, 0xc18b, 0x387f, 0xc18b, 0x21, 0 - .dw 0x38c0, 0xc18b, 0x38ff, 0xc18b, 0x21, 0 - .dw 0x3940, 0xc18b, 0x397f, 0xc18b, 0x21, 0 - .dw 0x39c0, 0xc18b, 0xffff, 0xc18b, 0x21, 0 - .dw 0x0040, 0xc18c, 0x007f, 0xc18c, 0x21, 0 - .dw 0x00c0, 0xc18c, 0x00ff, 0xc18c, 0x21, 0 - .dw 0x0140, 0xc18c, 0x017f, 0xc18c, 0x21, 0 - .dw 0x01c0, 0xc18c, 0x01ff, 0xc18c, 0x21, 0 - .dw 0x0240, 0xc18c, 0x027f, 0xc18c, 0x21, 0 - .dw 0x02c0, 0xc18c, 0x02ff, 0xc18c, 0x21, 0 - .dw 0x0340, 0xc18c, 0x037f, 0xc18c, 0x21, 0 - .dw 0x03c0, 0xc18c, 0x03ff, 0xc18c, 0x21, 0 - .dw 0x0440, 0xc18c, 0x047f, 0xc18c, 0x21, 0 - .dw 0x04c0, 0xc18c, 0x04ff, 0xc18c, 0x21, 0 - .dw 0x0540, 0xc18c, 0x057f, 0xc18c, 0x21, 0 - .dw 0x05c0, 0xc18c, 0x05ff, 0xc18c, 0x21, 0 - .dw 0x0640, 0xc18c, 0x067f, 0xc18c, 0x21, 0 - .dw 0x06c0, 0xc18c, 0x06ff, 0xc18c, 0x21, 0 - .dw 0x0740, 0xc18c, 0x077f, 0xc18c, 0x21, 0 - .dw 0x07c0, 0xc18c, 0x07ff, 0xc18c, 0x21, 0 - .dw 0x0840, 0xc18c, 0x087f, 0xc18c, 0x21, 0 - .dw 0x08c0, 0xc18c, 0x08ff, 0xc18c, 0x21, 0 - .dw 0x0940, 0xc18c, 0x097f, 0xc18c, 0x21, 0 - .dw 0x09c0, 0xc18c, 0x09ff, 0xc18c, 0x21, 0 - .dw 0x0a40, 0xc18c, 0x0a7f, 0xc18c, 0x21, 0 - .dw 0x0ac0, 0xc18c, 0x0aff, 0xc18c, 0x21, 0 - .dw 0x0b40, 0xc18c, 0x0b7f, 0xc18c, 0x21, 0 - .dw 0x0bc0, 0xc18c, 0x0bff, 0xc18c, 0x21, 0 - .dw 0x0c40, 0xc18c, 0x0c7f, 0xc18c, 0x21, 0 - .dw 0x0cc0, 0xc18c, 0x0cff, 0xc18c, 0x21, 0 - .dw 0x0d40, 0xc18c, 0x0d7f, 0xc18c, 0x21, 0 - .dw 0x0dc0, 0xc18c, 0x0dff, 0xc18c, 0x21, 0 - .dw 0x0e40, 0xc18c, 0x0e7f, 0xc18c, 0x21, 0 - .dw 0x0ec0, 0xc18c, 0x0eff, 0xc18c, 0x21, 0 - .dw 0x0f40, 0xc18c, 0x0f7f, 0xc18c, 0x21, 0 - .dw 0x0fc0, 0xc18c, 0x0fff, 0xc18c, 0x21, 0 - .dw 0x1040, 0xc18c, 0x107f, 0xc18c, 0x21, 0 - .dw 0x10c0, 0xc18c, 0x10ff, 0xc18c, 0x21, 0 - .dw 0x1140, 0xc18c, 0x117f, 0xc18c, 0x21, 0 - .dw 0x11c0, 0xc18c, 0x11ff, 0xc18c, 0x21, 0 - .dw 0x1240, 0xc18c, 0x127f, 0xc18c, 0x21, 0 - .dw 0x12c0, 0xc18c, 0x12ff, 0xc18c, 0x21, 0 - .dw 0x1340, 0xc18c, 0x137f, 0xc18c, 0x21, 0 - .dw 0x13c0, 0xc18c, 0x13ff, 0xc18c, 0x21, 0 - .dw 0x1440, 0xc18c, 0x147f, 0xc18c, 0x21, 0 - .dw 0x14c0, 0xc18c, 0x14ff, 0xc18c, 0x21, 0 - .dw 0x1540, 0xc18c, 0x157f, 0xc18c, 0x21, 0 - .dw 0x15c0, 0xc18c, 0x15ff, 0xc18c, 0x21, 0 - .dw 0x1640, 0xc18c, 0x167f, 0xc18c, 0x21, 0 - .dw 0x16c0, 0xc18c, 0x16ff, 0xc18c, 0x21, 0 - .dw 0x1740, 0xc18c, 0x177f, 0xc18c, 0x21, 0 - .dw 0x17c0, 0xc18c, 0x17ff, 0xc18c, 0x21, 0 - .dw 0x1840, 0xc18c, 0x187f, 0xc18c, 0x21, 0 - .dw 0x18c0, 0xc18c, 0x18ff, 0xc18c, 0x21, 0 - .dw 0x1940, 0xc18c, 0x197f, 0xc18c, 0x21, 0 - .dw 0x19c0, 0xc18c, 0x1fff, 0xc18c, 0x21, 0 - .dw 0x2040, 0xc18c, 0x207f, 0xc18c, 0x21, 0 - .dw 0x20c0, 0xc18c, 0x20ff, 0xc18c, 0x21, 0 - .dw 0x2140, 0xc18c, 0x217f, 0xc18c, 0x21, 0 - .dw 0x21c0, 0xc18c, 0x21ff, 0xc18c, 0x21, 0 - .dw 0x2240, 0xc18c, 0x227f, 0xc18c, 0x21, 0 - .dw 0x22c0, 0xc18c, 0x22ff, 0xc18c, 0x21, 0 - .dw 0x2340, 0xc18c, 0x237f, 0xc18c, 0x21, 0 - .dw 0x23c0, 0xc18c, 0x23ff, 0xc18c, 0x21, 0 - .dw 0x2440, 0xc18c, 0x247f, 0xc18c, 0x21, 0 - .dw 0x24c0, 0xc18c, 0x24ff, 0xc18c, 0x21, 0 - .dw 0x2540, 0xc18c, 0x257f, 0xc18c, 0x21, 0 - .dw 0x25c0, 0xc18c, 0x25ff, 0xc18c, 0x21, 0 - .dw 0x2640, 0xc18c, 0x267f, 0xc18c, 0x21, 0 - .dw 0x26c0, 0xc18c, 0x26ff, 0xc18c, 0x21, 0 - .dw 0x2740, 0xc18c, 0x277f, 0xc18c, 0x21, 0 - .dw 0x27c0, 0xc18c, 0x27ff, 0xc18c, 0x21, 0 - .dw 0x2840, 0xc18c, 0x287f, 0xc18c, 0x21, 0 - .dw 0x28c0, 0xc18c, 0x28ff, 0xc18c, 0x21, 0 - .dw 0x2940, 0xc18c, 0x297f, 0xc18c, 0x21, 0 - .dw 0x29c0, 0xc18c, 0x29ff, 0xc18c, 0x21, 0 - .dw 0x2a40, 0xc18c, 0x2a7f, 0xc18c, 0x21, 0 - .dw 0x2ac0, 0xc18c, 0x2aff, 0xc18c, 0x21, 0 - .dw 0x2b40, 0xc18c, 0x2b7f, 0xc18c, 0x21, 0 - .dw 0x2bc0, 0xc18c, 0x2bff, 0xc18c, 0x21, 0 - .dw 0x2c40, 0xc18c, 0x2c7f, 0xc18c, 0x21, 0 - .dw 0x2cc0, 0xc18c, 0x2cff, 0xc18c, 0x21, 0 - .dw 0x2d40, 0xc18c, 0x2d7f, 0xc18c, 0x21, 0 - .dw 0x2dc0, 0xc18c, 0x2dff, 0xc18c, 0x21, 0 - .dw 0x2e40, 0xc18c, 0x2e7f, 0xc18c, 0x21, 0 - .dw 0x2ec0, 0xc18c, 0x2eff, 0xc18c, 0x21, 0 - .dw 0x2f40, 0xc18c, 0x2f7f, 0xc18c, 0x21, 0 - .dw 0x2fc0, 0xc18c, 0x2fff, 0xc18c, 0x21, 0 - .dw 0x3040, 0xc18c, 0x307f, 0xc18c, 0x21, 0 - .dw 0x30c0, 0xc18c, 0x30ff, 0xc18c, 0x21, 0 - .dw 0x3140, 0xc18c, 0x317f, 0xc18c, 0x21, 0 - .dw 0x31c0, 0xc18c, 0x31ff, 0xc18c, 0x21, 0 - .dw 0x3240, 0xc18c, 0x327f, 0xc18c, 0x21, 0 - .dw 0x32c0, 0xc18c, 0x32ff, 0xc18c, 0x21, 0 - .dw 0x3340, 0xc18c, 0x337f, 0xc18c, 0x21, 0 - .dw 0x33c0, 0xc18c, 0x33ff, 0xc18c, 0x21, 0 - .dw 0x3440, 0xc18c, 0x347f, 0xc18c, 0x21, 0 - .dw 0x34c0, 0xc18c, 0x34ff, 0xc18c, 0x21, 0 - .dw 0x3540, 0xc18c, 0x357f, 0xc18c, 0x21, 0 - .dw 0x35c0, 0xc18c, 0x35ff, 0xc18c, 0x21, 0 - .dw 0x3640, 0xc18c, 0x367f, 0xc18c, 0x21, 0 - .dw 0x36c0, 0xc18c, 0x36ff, 0xc18c, 0x21, 0 - .dw 0x3740, 0xc18c, 0x377f, 0xc18c, 0x21, 0 - .dw 0x37c0, 0xc18c, 0x37ff, 0xc18c, 0x21, 0 - .dw 0x3840, 0xc18c, 0x387f, 0xc18c, 0x21, 0 - .dw 0x38c0, 0xc18c, 0x38ff, 0xc18c, 0x21, 0 - .dw 0x3940, 0xc18c, 0x397f, 0xc18c, 0x21, 0 - .dw 0x39c0, 0xc18c, 0x3fff, 0xc18c, 0x21, 0 - .dw 0x4040, 0xc18c, 0x407f, 0xc18c, 0x21, 0 - .dw 0x40c0, 0xc18c, 0x40ff, 0xc18c, 0x21, 0 - .dw 0x4140, 0xc18c, 0x417f, 0xc18c, 0x21, 0 - .dw 0x41c0, 0xc18c, 0x41ff, 0xc18c, 0x21, 0 - .dw 0x4240, 0xc18c, 0x427f, 0xc18c, 0x21, 0 - .dw 0x42c0, 0xc18c, 0x42ff, 0xc18c, 0x21, 0 - .dw 0x4340, 0xc18c, 0x437f, 0xc18c, 0x21, 0 - .dw 0x43c0, 0xc18c, 0x43ff, 0xc18c, 0x21, 0 - .dw 0x4440, 0xc18c, 0x447f, 0xc18c, 0x21, 0 - .dw 0x44c0, 0xc18c, 0x44ff, 0xc18c, 0x21, 0 - .dw 0x4540, 0xc18c, 0x457f, 0xc18c, 0x21, 0 - .dw 0x45c0, 0xc18c, 0x45ff, 0xc18c, 0x21, 0 - .dw 0x4640, 0xc18c, 0x467f, 0xc18c, 0x21, 0 - .dw 0x46c0, 0xc18c, 0x46ff, 0xc18c, 0x21, 0 - .dw 0x4740, 0xc18c, 0x477f, 0xc18c, 0x21, 0 - .dw 0x47c0, 0xc18c, 0x47ff, 0xc18c, 0x21, 0 - .dw 0x4840, 0xc18c, 0x487f, 0xc18c, 0x21, 0 - .dw 0x48c0, 0xc18c, 0x48ff, 0xc18c, 0x21, 0 - .dw 0x4940, 0xc18c, 0x497f, 0xc18c, 0x21, 0 - .dw 0x49c0, 0xc18c, 0x49ff, 0xc18c, 0x21, 0 - .dw 0x4a40, 0xc18c, 0x4a7f, 0xc18c, 0x21, 0 - .dw 0x4ac0, 0xc18c, 0x4aff, 0xc18c, 0x21, 0 - .dw 0x4b40, 0xc18c, 0x4b7f, 0xc18c, 0x21, 0 - .dw 0x4bc0, 0xc18c, 0x4bff, 0xc18c, 0x21, 0 - .dw 0x4c40, 0xc18c, 0x4c7f, 0xc18c, 0x21, 0 - .dw 0x4cc0, 0xc18c, 0x4cff, 0xc18c, 0x21, 0 - .dw 0x4d40, 0xc18c, 0x4d7f, 0xc18c, 0x21, 0 - .dw 0x4dc0, 0xc18c, 0x4dff, 0xc18c, 0x21, 0 - .dw 0x4e40, 0xc18c, 0x4e7f, 0xc18c, 0x21, 0 - .dw 0x4ec0, 0xc18c, 0x4eff, 0xc18c, 0x21, 0 - .dw 0x4f40, 0xc18c, 0x4f7f, 0xc18c, 0x21, 0 - .dw 0x4fc0, 0xc18c, 0x4fff, 0xc18c, 0x21, 0 - .dw 0x5040, 0xc18c, 0x507f, 0xc18c, 0x21, 0 - .dw 0x50c0, 0xc18c, 0x50ff, 0xc18c, 0x21, 0 - .dw 0x5140, 0xc18c, 0x517f, 0xc18c, 0x21, 0 - .dw 0x51c0, 0xc18c, 0x51ff, 0xc18c, 0x21, 0 - .dw 0x5240, 0xc18c, 0x527f, 0xc18c, 0x21, 0 - .dw 0x52c0, 0xc18c, 0x52ff, 0xc18c, 0x21, 0 - .dw 0x5340, 0xc18c, 0x537f, 0xc18c, 0x21, 0 - .dw 0x53c0, 0xc18c, 0x53ff, 0xc18c, 0x21, 0 - .dw 0x5440, 0xc18c, 0x547f, 0xc18c, 0x21, 0 - .dw 0x54c0, 0xc18c, 0x54ff, 0xc18c, 0x21, 0 - .dw 0x5540, 0xc18c, 0x557f, 0xc18c, 0x21, 0 - .dw 0x55c0, 0xc18c, 0x55ff, 0xc18c, 0x21, 0 - .dw 0x5640, 0xc18c, 0x567f, 0xc18c, 0x21, 0 - .dw 0x56c0, 0xc18c, 0x56ff, 0xc18c, 0x21, 0 - .dw 0x5740, 0xc18c, 0x577f, 0xc18c, 0x21, 0 - .dw 0x57c0, 0xc18c, 0x57ff, 0xc18c, 0x21, 0 - .dw 0x5840, 0xc18c, 0x587f, 0xc18c, 0x21, 0 - .dw 0x58c0, 0xc18c, 0x58ff, 0xc18c, 0x21, 0 - .dw 0x5940, 0xc18c, 0x597f, 0xc18c, 0x21, 0 - .dw 0x59c0, 0xc18c, 0x5fff, 0xc18c, 0x21, 0 - .dw 0x6040, 0xc18c, 0x607f, 0xc18c, 0x21, 0 - .dw 0x60c0, 0xc18c, 0x60ff, 0xc18c, 0x21, 0 - .dw 0x6140, 0xc18c, 0x617f, 0xc18c, 0x21, 0 - .dw 0x61c0, 0xc18c, 0x61ff, 0xc18c, 0x21, 0 - .dw 0x6240, 0xc18c, 0x627f, 0xc18c, 0x21, 0 - .dw 0x62c0, 0xc18c, 0x62ff, 0xc18c, 0x21, 0 - .dw 0x6340, 0xc18c, 0x637f, 0xc18c, 0x21, 0 - .dw 0x63c0, 0xc18c, 0x63ff, 0xc18c, 0x21, 0 - .dw 0x6440, 0xc18c, 0x647f, 0xc18c, 0x21, 0 - .dw 0x64c0, 0xc18c, 0x64ff, 0xc18c, 0x21, 0 - .dw 0x6540, 0xc18c, 0x657f, 0xc18c, 0x21, 0 - .dw 0x65c0, 0xc18c, 0x65ff, 0xc18c, 0x21, 0 - .dw 0x6640, 0xc18c, 0x667f, 0xc18c, 0x21, 0 - .dw 0x66c0, 0xc18c, 0x66ff, 0xc18c, 0x21, 0 - .dw 0x6740, 0xc18c, 0x677f, 0xc18c, 0x21, 0 - .dw 0x67c0, 0xc18c, 0x67ff, 0xc18c, 0x21, 0 - .dw 0x6840, 0xc18c, 0x687f, 0xc18c, 0x21, 0 - .dw 0x68c0, 0xc18c, 0x68ff, 0xc18c, 0x21, 0 - .dw 0x6940, 0xc18c, 0x697f, 0xc18c, 0x21, 0 - .dw 0x69c0, 0xc18c, 0x69ff, 0xc18c, 0x21, 0 - .dw 0x6a40, 0xc18c, 0x6a7f, 0xc18c, 0x21, 0 - .dw 0x6ac0, 0xc18c, 0x6aff, 0xc18c, 0x21, 0 - .dw 0x6b40, 0xc18c, 0x6b7f, 0xc18c, 0x21, 0 - .dw 0x6bc0, 0xc18c, 0x6bff, 0xc18c, 0x21, 0 - .dw 0x6c40, 0xc18c, 0x6c7f, 0xc18c, 0x21, 0 - .dw 0x6cc0, 0xc18c, 0x6cff, 0xc18c, 0x21, 0 - .dw 0x6d40, 0xc18c, 0x6d7f, 0xc18c, 0x21, 0 - .dw 0x6dc0, 0xc18c, 0x6dff, 0xc18c, 0x21, 0 - .dw 0x6e40, 0xc18c, 0x6e7f, 0xc18c, 0x21, 0 - .dw 0x6ec0, 0xc18c, 0x6eff, 0xc18c, 0x21, 0 - .dw 0x6f40, 0xc18c, 0x6f7f, 0xc18c, 0x21, 0 - .dw 0x6fc0, 0xc18c, 0x6fff, 0xc18c, 0x21, 0 - .dw 0x7040, 0xc18c, 0x707f, 0xc18c, 0x21, 0 - .dw 0x70c0, 0xc18c, 0x70ff, 0xc18c, 0x21, 0 - .dw 0x7140, 0xc18c, 0x717f, 0xc18c, 0x21, 0 - .dw 0x71c0, 0xc18c, 0x71ff, 0xc18c, 0x21, 0 - .dw 0x7240, 0xc18c, 0x727f, 0xc18c, 0x21, 0 - .dw 0x72c0, 0xc18c, 0x72ff, 0xc18c, 0x21, 0 - .dw 0x7340, 0xc18c, 0x737f, 0xc18c, 0x21, 0 - .dw 0x73c0, 0xc18c, 0x73ff, 0xc18c, 0x21, 0 - .dw 0x7440, 0xc18c, 0x747f, 0xc18c, 0x21, 0 - .dw 0x74c0, 0xc18c, 0x74ff, 0xc18c, 0x21, 0 - .dw 0x7540, 0xc18c, 0x757f, 0xc18c, 0x21, 0 - .dw 0x75c0, 0xc18c, 0x75ff, 0xc18c, 0x21, 0 - .dw 0x7640, 0xc18c, 0x767f, 0xc18c, 0x21, 0 - .dw 0x76c0, 0xc18c, 0x76ff, 0xc18c, 0x21, 0 - .dw 0x7740, 0xc18c, 0x777f, 0xc18c, 0x21, 0 - .dw 0x77c0, 0xc18c, 0x77ff, 0xc18c, 0x21, 0 - .dw 0x7840, 0xc18c, 0x787f, 0xc18c, 0x21, 0 - .dw 0x78c0, 0xc18c, 0x78ff, 0xc18c, 0x21, 0 - .dw 0x7940, 0xc18c, 0x797f, 0xc18c, 0x21, 0 - .dw 0x79c0, 0xc18c, 0x7fff, 0xc18c, 0x21, 0 - .dw 0x8040, 0xc18c, 0x807f, 0xc18c, 0x21, 0 - .dw 0x80c0, 0xc18c, 0x80ff, 0xc18c, 0x21, 0 - .dw 0x8140, 0xc18c, 0x817f, 0xc18c, 0x21, 0 - .dw 0x81c0, 0xc18c, 0x81ff, 0xc18c, 0x21, 0 - .dw 0x8240, 0xc18c, 0x827f, 0xc18c, 0x21, 0 - .dw 0x82c0, 0xc18c, 0x82ff, 0xc18c, 0x21, 0 - .dw 0x8340, 0xc18c, 0x837f, 0xc18c, 0x21, 0 - .dw 0x83c0, 0xc18c, 0x83ff, 0xc18c, 0x21, 0 - .dw 0x8440, 0xc18c, 0x847f, 0xc18c, 0x21, 0 - .dw 0x84c0, 0xc18c, 0x84ff, 0xc18c, 0x21, 0 - .dw 0x8540, 0xc18c, 0x857f, 0xc18c, 0x21, 0 - .dw 0x85c0, 0xc18c, 0x85ff, 0xc18c, 0x21, 0 - .dw 0x8640, 0xc18c, 0x867f, 0xc18c, 0x21, 0 - .dw 0x86c0, 0xc18c, 0x86ff, 0xc18c, 0x21, 0 - .dw 0x8740, 0xc18c, 0x877f, 0xc18c, 0x21, 0 - .dw 0x87c0, 0xc18c, 0x87ff, 0xc18c, 0x21, 0 - .dw 0x8840, 0xc18c, 0x887f, 0xc18c, 0x21, 0 - .dw 0x88c0, 0xc18c, 0x88ff, 0xc18c, 0x21, 0 - .dw 0x8940, 0xc18c, 0x897f, 0xc18c, 0x21, 0 - .dw 0x89c0, 0xc18c, 0x89ff, 0xc18c, 0x21, 0 - .dw 0x8a40, 0xc18c, 0x8a7f, 0xc18c, 0x21, 0 - .dw 0x8ac0, 0xc18c, 0x8aff, 0xc18c, 0x21, 0 - .dw 0x8b40, 0xc18c, 0x8b7f, 0xc18c, 0x21, 0 - .dw 0x8bc0, 0xc18c, 0x8bff, 0xc18c, 0x21, 0 - .dw 0x8c40, 0xc18c, 0x8c7f, 0xc18c, 0x21, 0 - .dw 0x8cc0, 0xc18c, 0x8cff, 0xc18c, 0x21, 0 - .dw 0x8d40, 0xc18c, 0x8d7f, 0xc18c, 0x21, 0 - .dw 0x8dc0, 0xc18c, 0x8dff, 0xc18c, 0x21, 0 - .dw 0x8e40, 0xc18c, 0x8e7f, 0xc18c, 0x21, 0 - .dw 0x8ec0, 0xc18c, 0x8eff, 0xc18c, 0x21, 0 - .dw 0x8f40, 0xc18c, 0x8f7f, 0xc18c, 0x21, 0 - .dw 0x8fc0, 0xc18c, 0x8fff, 0xc18c, 0x21, 0 - .dw 0x9040, 0xc18c, 0x907f, 0xc18c, 0x21, 0 - .dw 0x90c0, 0xc18c, 0x90ff, 0xc18c, 0x21, 0 - .dw 0x9140, 0xc18c, 0x917f, 0xc18c, 0x21, 0 - .dw 0x91c0, 0xc18c, 0x91ff, 0xc18c, 0x21, 0 - .dw 0x9240, 0xc18c, 0x927f, 0xc18c, 0x21, 0 - .dw 0x92c0, 0xc18c, 0x92ff, 0xc18c, 0x21, 0 - .dw 0x9340, 0xc18c, 0x937f, 0xc18c, 0x21, 0 - .dw 0x93c0, 0xc18c, 0x93ff, 0xc18c, 0x21, 0 - .dw 0x9440, 0xc18c, 0x947f, 0xc18c, 0x21, 0 - .dw 0x94c0, 0xc18c, 0x94ff, 0xc18c, 0x21, 0 - .dw 0x9540, 0xc18c, 0x957f, 0xc18c, 0x21, 0 - .dw 0x95c0, 0xc18c, 0x95ff, 0xc18c, 0x21, 0 - .dw 0x9640, 0xc18c, 0x967f, 0xc18c, 0x21, 0 - .dw 0x96c0, 0xc18c, 0x96ff, 0xc18c, 0x21, 0 - .dw 0x9740, 0xc18c, 0x977f, 0xc18c, 0x21, 0 - .dw 0x97c0, 0xc18c, 0x97ff, 0xc18c, 0x21, 0 - .dw 0x9840, 0xc18c, 0x987f, 0xc18c, 0x21, 0 - .dw 0x98c0, 0xc18c, 0x98ff, 0xc18c, 0x21, 0 - .dw 0x9940, 0xc18c, 0x997f, 0xc18c, 0x21, 0 - .dw 0x99c0, 0xc18c, 0x9fff, 0xc18c, 0x21, 0 - .dw 0xa040, 0xc18c, 0xa07f, 0xc18c, 0x21, 0 - .dw 0xa0c0, 0xc18c, 0xa0ff, 0xc18c, 0x21, 0 - .dw 0xa140, 0xc18c, 0xa17f, 0xc18c, 0x21, 0 - .dw 0xa1c0, 0xc18c, 0xa1ff, 0xc18c, 0x21, 0 - .dw 0xa240, 0xc18c, 0xa27f, 0xc18c, 0x21, 0 - .dw 0xa2c0, 0xc18c, 0xa2ff, 0xc18c, 0x21, 0 - .dw 0xa340, 0xc18c, 0xa37f, 0xc18c, 0x21, 0 - .dw 0xa3c0, 0xc18c, 0xa3ff, 0xc18c, 0x21, 0 - .dw 0xa440, 0xc18c, 0xa47f, 0xc18c, 0x21, 0 - .dw 0xa4c0, 0xc18c, 0xa4ff, 0xc18c, 0x21, 0 - .dw 0xa540, 0xc18c, 0xa57f, 0xc18c, 0x21, 0 - .dw 0xa5c0, 0xc18c, 0xa5ff, 0xc18c, 0x21, 0 - .dw 0xa640, 0xc18c, 0xa67f, 0xc18c, 0x21, 0 - .dw 0xa6c0, 0xc18c, 0xa6ff, 0xc18c, 0x21, 0 - .dw 0xa740, 0xc18c, 0xa77f, 0xc18c, 0x21, 0 - .dw 0xa7c0, 0xc18c, 0xa7ff, 0xc18c, 0x21, 0 - .dw 0xa840, 0xc18c, 0xa87f, 0xc18c, 0x21, 0 - .dw 0xa8c0, 0xc18c, 0xa8ff, 0xc18c, 0x21, 0 - .dw 0xa940, 0xc18c, 0xa97f, 0xc18c, 0x21, 0 - .dw 0xa9c0, 0xc18c, 0xa9ff, 0xc18c, 0x21, 0 - .dw 0xaa40, 0xc18c, 0xaa7f, 0xc18c, 0x21, 0 - .dw 0xaac0, 0xc18c, 0xaaff, 0xc18c, 0x21, 0 - .dw 0xab40, 0xc18c, 0xab7f, 0xc18c, 0x21, 0 - .dw 0xabc0, 0xc18c, 0xabff, 0xc18c, 0x21, 0 - .dw 0xac40, 0xc18c, 0xac7f, 0xc18c, 0x21, 0 - .dw 0xacc0, 0xc18c, 0xacff, 0xc18c, 0x21, 0 - .dw 0xad40, 0xc18c, 0xad7f, 0xc18c, 0x21, 0 - .dw 0xadc0, 0xc18c, 0xadff, 0xc18c, 0x21, 0 - .dw 0xae40, 0xc18c, 0xae7f, 0xc18c, 0x21, 0 - .dw 0xaec0, 0xc18c, 0xaeff, 0xc18c, 0x21, 0 - .dw 0xaf40, 0xc18c, 0xaf7f, 0xc18c, 0x21, 0 - .dw 0xafc0, 0xc18c, 0xafff, 0xc18c, 0x21, 0 - .dw 0xb040, 0xc18c, 0xb07f, 0xc18c, 0x21, 0 - .dw 0xb0c0, 0xc18c, 0xb0ff, 0xc18c, 0x21, 0 - .dw 0xb140, 0xc18c, 0xb17f, 0xc18c, 0x21, 0 - .dw 0xb1c0, 0xc18c, 0xb1ff, 0xc18c, 0x21, 0 - .dw 0xb240, 0xc18c, 0xb27f, 0xc18c, 0x21, 0 - .dw 0xb2c0, 0xc18c, 0xb2ff, 0xc18c, 0x21, 0 - .dw 0xb340, 0xc18c, 0xb37f, 0xc18c, 0x21, 0 - .dw 0xb3c0, 0xc18c, 0xb3ff, 0xc18c, 0x21, 0 - .dw 0xb440, 0xc18c, 0xb47f, 0xc18c, 0x21, 0 - .dw 0xb4c0, 0xc18c, 0xb4ff, 0xc18c, 0x21, 0 - .dw 0xb540, 0xc18c, 0xb57f, 0xc18c, 0x21, 0 - .dw 0xb5c0, 0xc18c, 0xb5ff, 0xc18c, 0x21, 0 - .dw 0xb640, 0xc18c, 0xb67f, 0xc18c, 0x21, 0 - .dw 0xb6c0, 0xc18c, 0xb6ff, 0xc18c, 0x21, 0 - .dw 0xb740, 0xc18c, 0xb77f, 0xc18c, 0x21, 0 - .dw 0xb7c0, 0xc18c, 0xb7ff, 0xc18c, 0x21, 0 - .dw 0xb840, 0xc18c, 0xb87f, 0xc18c, 0x21, 0 - .dw 0xb8c0, 0xc18c, 0xb8ff, 0xc18c, 0x21, 0 - .dw 0xb940, 0xc18c, 0xb97f, 0xc18c, 0x21, 0 - .dw 0xb9c0, 0xc18c, 0xbfff, 0xc18c, 0x21, 0 - .dw 0xc040, 0xc18c, 0xc07f, 0xc18c, 0x21, 0 - .dw 0xc0c0, 0xc18c, 0xc0ff, 0xc18c, 0x21, 0 - .dw 0xc140, 0xc18c, 0xc17f, 0xc18c, 0x21, 0 - .dw 0xc1c0, 0xc18c, 0xc1ff, 0xc18c, 0x21, 0 - .dw 0xc240, 0xc18c, 0xc27f, 0xc18c, 0x21, 0 - .dw 0xc2c0, 0xc18c, 0xc2ff, 0xc18c, 0x21, 0 - .dw 0xc340, 0xc18c, 0xc37f, 0xc18c, 0x21, 0 - .dw 0xc3c0, 0xc18c, 0xc3ff, 0xc18c, 0x21, 0 - .dw 0xc440, 0xc18c, 0xc47f, 0xc18c, 0x21, 0 - .dw 0xc4c0, 0xc18c, 0xc4ff, 0xc18c, 0x21, 0 - .dw 0xc540, 0xc18c, 0xc57f, 0xc18c, 0x21, 0 - .dw 0xc5c0, 0xc18c, 0xc5ff, 0xc18c, 0x21, 0 - .dw 0xc640, 0xc18c, 0xc67f, 0xc18c, 0x21, 0 - .dw 0xc6c0, 0xc18c, 0xc6ff, 0xc18c, 0x21, 0 - .dw 0xc740, 0xc18c, 0xc77f, 0xc18c, 0x21, 0 - .dw 0xc7c0, 0xc18c, 0xc7ff, 0xc18c, 0x21, 0 - .dw 0xc840, 0xc18c, 0xc87f, 0xc18c, 0x21, 0 - .dw 0xc8c0, 0xc18c, 0xc8ff, 0xc18c, 0x21, 0 - .dw 0xc940, 0xc18c, 0xc97f, 0xc18c, 0x21, 0 - .dw 0xc9c0, 0xc18c, 0xc9ff, 0xc18c, 0x21, 0 - .dw 0xca40, 0xc18c, 0xca7f, 0xc18c, 0x21, 0 - .dw 0xcac0, 0xc18c, 0xcaff, 0xc18c, 0x21, 0 - .dw 0xcb40, 0xc18c, 0xcb7f, 0xc18c, 0x21, 0 - .dw 0xcbc0, 0xc18c, 0xcbff, 0xc18c, 0x21, 0 - .dw 0xcc40, 0xc18c, 0xcc7f, 0xc18c, 0x21, 0 - .dw 0xccc0, 0xc18c, 0xccff, 0xc18c, 0x21, 0 - .dw 0xcd40, 0xc18c, 0xcd7f, 0xc18c, 0x21, 0 - .dw 0xcdc0, 0xc18c, 0xcdff, 0xc18c, 0x21, 0 - .dw 0xce40, 0xc18c, 0xce7f, 0xc18c, 0x21, 0 - .dw 0xcec0, 0xc18c, 0xceff, 0xc18c, 0x21, 0 - .dw 0xcf40, 0xc18c, 0xcf7f, 0xc18c, 0x21, 0 - .dw 0xcfc0, 0xc18c, 0xcfff, 0xc18c, 0x21, 0 - .dw 0xd040, 0xc18c, 0xd07f, 0xc18c, 0x21, 0 - .dw 0xd0c0, 0xc18c, 0xd0ff, 0xc18c, 0x21, 0 - .dw 0xd140, 0xc18c, 0xd17f, 0xc18c, 0x21, 0 - .dw 0xd1c0, 0xc18c, 0xd1ff, 0xc18c, 0x21, 0 - .dw 0xd240, 0xc18c, 0xd27f, 0xc18c, 0x21, 0 - .dw 0xd2c0, 0xc18c, 0xd2ff, 0xc18c, 0x21, 0 - .dw 0xd340, 0xc18c, 0xd37f, 0xc18c, 0x21, 0 - .dw 0xd3c0, 0xc18c, 0xd3ff, 0xc18c, 0x21, 0 - .dw 0xd440, 0xc18c, 0xd47f, 0xc18c, 0x21, 0 - .dw 0xd4c0, 0xc18c, 0xd4ff, 0xc18c, 0x21, 0 - .dw 0xd540, 0xc18c, 0xd57f, 0xc18c, 0x21, 0 - .dw 0xd5c0, 0xc18c, 0xd5ff, 0xc18c, 0x21, 0 - .dw 0xd640, 0xc18c, 0xd67f, 0xc18c, 0x21, 0 - .dw 0xd6c0, 0xc18c, 0xd6ff, 0xc18c, 0x21, 0 - .dw 0xd740, 0xc18c, 0xd77f, 0xc18c, 0x21, 0 - .dw 0xd7c0, 0xc18c, 0xd7ff, 0xc18c, 0x21, 0 - .dw 0xd840, 0xc18c, 0xd87f, 0xc18c, 0x21, 0 - .dw 0xd8c0, 0xc18c, 0xd8ff, 0xc18c, 0x21, 0 - .dw 0xd940, 0xc18c, 0xd97f, 0xc18c, 0x21, 0 - .dw 0xd9c0, 0xc18c, 0xdfff, 0xc18c, 0x21, 0 - .dw 0xe040, 0xc18c, 0xe07f, 0xc18c, 0x21, 0 - .dw 0xe0c0, 0xc18c, 0xe0ff, 0xc18c, 0x21, 0 - .dw 0xe140, 0xc18c, 0xe17f, 0xc18c, 0x21, 0 - .dw 0xe1c0, 0xc18c, 0xe1ff, 0xc18c, 0x21, 0 - .dw 0xe240, 0xc18c, 0xe27f, 0xc18c, 0x21, 0 - .dw 0xe2c0, 0xc18c, 0xe2ff, 0xc18c, 0x21, 0 - .dw 0xe340, 0xc18c, 0xe37f, 0xc18c, 0x21, 0 - .dw 0xe3c0, 0xc18c, 0xe3ff, 0xc18c, 0x21, 0 - .dw 0xe440, 0xc18c, 0xe47f, 0xc18c, 0x21, 0 - .dw 0xe4c0, 0xc18c, 0xe4ff, 0xc18c, 0x21, 0 - .dw 0xe540, 0xc18c, 0xe57f, 0xc18c, 0x21, 0 - .dw 0xe5c0, 0xc18c, 0xe5ff, 0xc18c, 0x21, 0 - .dw 0xe640, 0xc18c, 0xe67f, 0xc18c, 0x21, 0 - .dw 0xe6c0, 0xc18c, 0xe6ff, 0xc18c, 0x21, 0 - .dw 0xe740, 0xc18c, 0xe77f, 0xc18c, 0x21, 0 - .dw 0xe7c0, 0xc18c, 0xe7ff, 0xc18c, 0x21, 0 - .dw 0xe840, 0xc18c, 0xe87f, 0xc18c, 0x21, 0 - .dw 0xe8c0, 0xc18c, 0xe8ff, 0xc18c, 0x21, 0 - .dw 0xe940, 0xc18c, 0xe97f, 0xc18c, 0x21, 0 - .dw 0xe9c0, 0xc18c, 0xe9ff, 0xc18c, 0x21, 0 - .dw 0xea40, 0xc18c, 0xea7f, 0xc18c, 0x21, 0 - .dw 0xeac0, 0xc18c, 0xeaff, 0xc18c, 0x21, 0 - .dw 0xeb40, 0xc18c, 0xeb7f, 0xc18c, 0x21, 0 - .dw 0xebc0, 0xc18c, 0xebff, 0xc18c, 0x21, 0 - .dw 0xec40, 0xc18c, 0xec7f, 0xc18c, 0x21, 0 - .dw 0xecc0, 0xc18c, 0xecff, 0xc18c, 0x21, 0 - .dw 0xed40, 0xc18c, 0xed7f, 0xc18c, 0x21, 0 - .dw 0xedc0, 0xc18c, 0xedff, 0xc18c, 0x21, 0 - .dw 0xee40, 0xc18c, 0xee7f, 0xc18c, 0x21, 0 - .dw 0xeec0, 0xc18c, 0xeeff, 0xc18c, 0x21, 0 - .dw 0xef40, 0xc18c, 0xef7f, 0xc18c, 0x21, 0 - .dw 0xefc0, 0xc18c, 0xefff, 0xc18c, 0x21, 0 - .dw 0xf040, 0xc18c, 0xf07f, 0xc18c, 0x21, 0 - .dw 0xf0c0, 0xc18c, 0xf0ff, 0xc18c, 0x21, 0 - .dw 0xf140, 0xc18c, 0xf17f, 0xc18c, 0x21, 0 - .dw 0xf1c0, 0xc18c, 0xf1ff, 0xc18c, 0x21, 0 - .dw 0xf240, 0xc18c, 0xf27f, 0xc18c, 0x21, 0 - .dw 0xf2c0, 0xc18c, 0xf2ff, 0xc18c, 0x21, 0 - .dw 0xf340, 0xc18c, 0xf37f, 0xc18c, 0x21, 0 - .dw 0xf3c0, 0xc18c, 0xf3ff, 0xc18c, 0x21, 0 - .dw 0xf440, 0xc18c, 0xf47f, 0xc18c, 0x21, 0 - .dw 0xf4c0, 0xc18c, 0xf4ff, 0xc18c, 0x21, 0 - .dw 0xf540, 0xc18c, 0xf57f, 0xc18c, 0x21, 0 - .dw 0xf5c0, 0xc18c, 0xf5ff, 0xc18c, 0x21, 0 - .dw 0xf640, 0xc18c, 0xf67f, 0xc18c, 0x21, 0 - .dw 0xf6c0, 0xc18c, 0xf6ff, 0xc18c, 0x21, 0 - .dw 0xf740, 0xc18c, 0xf77f, 0xc18c, 0x21, 0 - .dw 0xf7c0, 0xc18c, 0xf7ff, 0xc18c, 0x21, 0 - .dw 0xf840, 0xc18c, 0xf87f, 0xc18c, 0x21, 0 - .dw 0xf8c0, 0xc18c, 0xf8ff, 0xc18c, 0x21, 0 - .dw 0xf940, 0xc18c, 0xf97f, 0xc18c, 0x21, 0 - .dw 0xf9c0, 0xc18c, 0xffff, 0xc18c, 0x21, 0 - .dw 0x0040, 0xc18d, 0x007f, 0xc18d, 0x21, 0 - .dw 0x00c0, 0xc18d, 0x00ff, 0xc18d, 0x21, 0 - .dw 0x0140, 0xc18d, 0x017f, 0xc18d, 0x21, 0 - .dw 0x01c0, 0xc18d, 0x01ff, 0xc18d, 0x21, 0 - .dw 0x0240, 0xc18d, 0x027f, 0xc18d, 0x21, 0 - .dw 0x02c0, 0xc18d, 0x02ff, 0xc18d, 0x21, 0 - .dw 0x0340, 0xc18d, 0x037f, 0xc18d, 0x21, 0 - .dw 0x03c0, 0xc18d, 0x03ff, 0xc18d, 0x21, 0 - .dw 0x0440, 0xc18d, 0x047f, 0xc18d, 0x21, 0 - .dw 0x04c0, 0xc18d, 0x04ff, 0xc18d, 0x21, 0 - .dw 0x0540, 0xc18d, 0x057f, 0xc18d, 0x21, 0 - .dw 0x05c0, 0xc18d, 0x05ff, 0xc18d, 0x21, 0 - .dw 0x0640, 0xc18d, 0x067f, 0xc18d, 0x21, 0 - .dw 0x06c0, 0xc18d, 0x06ff, 0xc18d, 0x21, 0 - .dw 0x0740, 0xc18d, 0x077f, 0xc18d, 0x21, 0 - .dw 0x07c0, 0xc18d, 0x07ff, 0xc18d, 0x21, 0 - .dw 0x0840, 0xc18d, 0x087f, 0xc18d, 0x21, 0 - .dw 0x08c0, 0xc18d, 0x08ff, 0xc18d, 0x21, 0 - .dw 0x0940, 0xc18d, 0x097f, 0xc18d, 0x21, 0 - .dw 0x09c0, 0xc18d, 0x09ff, 0xc18d, 0x21, 0 - .dw 0x0a40, 0xc18d, 0x0a7f, 0xc18d, 0x21, 0 - .dw 0x0ac0, 0xc18d, 0x0aff, 0xc18d, 0x21, 0 - .dw 0x0b40, 0xc18d, 0x0b7f, 0xc18d, 0x21, 0 - .dw 0x0bc0, 0xc18d, 0x0bff, 0xc18d, 0x21, 0 - .dw 0x0c40, 0xc18d, 0x0c7f, 0xc18d, 0x21, 0 - .dw 0x0cc0, 0xc18d, 0x0cff, 0xc18d, 0x21, 0 - .dw 0x0d40, 0xc18d, 0x0d7f, 0xc18d, 0x21, 0 - .dw 0x0dc0, 0xc18d, 0x0dff, 0xc18d, 0x21, 0 - .dw 0x0e40, 0xc18d, 0x0e7f, 0xc18d, 0x21, 0 - .dw 0x0ec0, 0xc18d, 0x0eff, 0xc18d, 0x21, 0 - .dw 0x0f40, 0xc18d, 0x0f7f, 0xc18d, 0x21, 0 - .dw 0x0fc0, 0xc18d, 0x0fff, 0xc18d, 0x21, 0 - .dw 0x1040, 0xc18d, 0x107f, 0xc18d, 0x21, 0 - .dw 0x10c0, 0xc18d, 0x10ff, 0xc18d, 0x21, 0 - .dw 0x1140, 0xc18d, 0x117f, 0xc18d, 0x21, 0 - .dw 0x11c0, 0xc18d, 0x11ff, 0xc18d, 0x21, 0 - .dw 0x1240, 0xc18d, 0x127f, 0xc18d, 0x21, 0 - .dw 0x12c0, 0xc18d, 0x12ff, 0xc18d, 0x21, 0 - .dw 0x1340, 0xc18d, 0x137f, 0xc18d, 0x21, 0 - .dw 0x13c0, 0xc18d, 0x13ff, 0xc18d, 0x21, 0 - .dw 0x1440, 0xc18d, 0x147f, 0xc18d, 0x21, 0 - .dw 0x14c0, 0xc18d, 0x14ff, 0xc18d, 0x21, 0 - .dw 0x1540, 0xc18d, 0x157f, 0xc18d, 0x21, 0 - .dw 0x15c0, 0xc18d, 0x15ff, 0xc18d, 0x21, 0 - .dw 0x1640, 0xc18d, 0x167f, 0xc18d, 0x21, 0 - .dw 0x16c0, 0xc18d, 0x16ff, 0xc18d, 0x21, 0 - .dw 0x1740, 0xc18d, 0x177f, 0xc18d, 0x21, 0 - .dw 0x17c0, 0xc18d, 0x17ff, 0xc18d, 0x21, 0 - .dw 0x1840, 0xc18d, 0x187f, 0xc18d, 0x21, 0 - .dw 0x18c0, 0xc18d, 0x18ff, 0xc18d, 0x21, 0 - .dw 0x1940, 0xc18d, 0x197f, 0xc18d, 0x21, 0 - .dw 0x19c0, 0xc18d, 0x1fff, 0xc18d, 0x21, 0 - .dw 0x2040, 0xc18d, 0x207f, 0xc18d, 0x21, 0 - .dw 0x20c0, 0xc18d, 0x20ff, 0xc18d, 0x21, 0 - .dw 0x2140, 0xc18d, 0x217f, 0xc18d, 0x21, 0 - .dw 0x21c0, 0xc18d, 0x21ff, 0xc18d, 0x21, 0 - .dw 0x2240, 0xc18d, 0x227f, 0xc18d, 0x21, 0 - .dw 0x22c0, 0xc18d, 0x22ff, 0xc18d, 0x21, 0 - .dw 0x2340, 0xc18d, 0x237f, 0xc18d, 0x21, 0 - .dw 0x23c0, 0xc18d, 0x23ff, 0xc18d, 0x21, 0 - .dw 0x2440, 0xc18d, 0x247f, 0xc18d, 0x21, 0 - .dw 0x24c0, 0xc18d, 0x24ff, 0xc18d, 0x21, 0 - .dw 0x2540, 0xc18d, 0x257f, 0xc18d, 0x21, 0 - .dw 0x25c0, 0xc18d, 0x25ff, 0xc18d, 0x21, 0 - .dw 0x2640, 0xc18d, 0x267f, 0xc18d, 0x21, 0 - .dw 0x26c0, 0xc18d, 0x26ff, 0xc18d, 0x21, 0 - .dw 0x2740, 0xc18d, 0x277f, 0xc18d, 0x21, 0 - .dw 0x27c0, 0xc18d, 0x27ff, 0xc18d, 0x21, 0 - .dw 0x2840, 0xc18d, 0x287f, 0xc18d, 0x21, 0 - .dw 0x28c0, 0xc18d, 0x28ff, 0xc18d, 0x21, 0 - .dw 0x2940, 0xc18d, 0x297f, 0xc18d, 0x21, 0 - .dw 0x29c0, 0xc18d, 0x29ff, 0xc18d, 0x21, 0 - .dw 0x2a40, 0xc18d, 0x2a7f, 0xc18d, 0x21, 0 - .dw 0x2ac0, 0xc18d, 0x2aff, 0xc18d, 0x21, 0 - .dw 0x2b40, 0xc18d, 0x2b7f, 0xc18d, 0x21, 0 - .dw 0x2bc0, 0xc18d, 0x2bff, 0xc18d, 0x21, 0 - .dw 0x2c40, 0xc18d, 0x2c7f, 0xc18d, 0x21, 0 - .dw 0x2cc0, 0xc18d, 0x2cff, 0xc18d, 0x21, 0 - .dw 0x2d40, 0xc18d, 0x2d7f, 0xc18d, 0x21, 0 - .dw 0x2dc0, 0xc18d, 0x2dff, 0xc18d, 0x21, 0 - .dw 0x2e40, 0xc18d, 0x2e7f, 0xc18d, 0x21, 0 - .dw 0x2ec0, 0xc18d, 0x2eff, 0xc18d, 0x21, 0 - .dw 0x2f40, 0xc18d, 0x2f7f, 0xc18d, 0x21, 0 - .dw 0x2fc0, 0xc18d, 0x2fff, 0xc18d, 0x21, 0 - .dw 0x3040, 0xc18d, 0x307f, 0xc18d, 0x21, 0 - .dw 0x30c0, 0xc18d, 0x30ff, 0xc18d, 0x21, 0 - .dw 0x3140, 0xc18d, 0x317f, 0xc18d, 0x21, 0 - .dw 0x31c0, 0xc18d, 0x31ff, 0xc18d, 0x21, 0 - .dw 0x3240, 0xc18d, 0x327f, 0xc18d, 0x21, 0 - .dw 0x32c0, 0xc18d, 0x32ff, 0xc18d, 0x21, 0 - .dw 0x3340, 0xc18d, 0x337f, 0xc18d, 0x21, 0 - .dw 0x33c0, 0xc18d, 0x33ff, 0xc18d, 0x21, 0 - .dw 0x3440, 0xc18d, 0x347f, 0xc18d, 0x21, 0 - .dw 0x34c0, 0xc18d, 0x34ff, 0xc18d, 0x21, 0 - .dw 0x3540, 0xc18d, 0x357f, 0xc18d, 0x21, 0 - .dw 0x35c0, 0xc18d, 0x35ff, 0xc18d, 0x21, 0 - .dw 0x3640, 0xc18d, 0x367f, 0xc18d, 0x21, 0 - .dw 0x36c0, 0xc18d, 0x36ff, 0xc18d, 0x21, 0 - .dw 0x3740, 0xc18d, 0x377f, 0xc18d, 0x21, 0 - .dw 0x37c0, 0xc18d, 0x37ff, 0xc18d, 0x21, 0 - .dw 0x3840, 0xc18d, 0x387f, 0xc18d, 0x21, 0 - .dw 0x38c0, 0xc18d, 0x38ff, 0xc18d, 0x21, 0 - .dw 0x3940, 0xc18d, 0x397f, 0xc18d, 0x21, 0 - .dw 0x39c0, 0xc18d, 0x3fff, 0xc18d, 0x21, 0 - .dw 0x4040, 0xc18d, 0x407f, 0xc18d, 0x21, 0 - .dw 0x40c0, 0xc18d, 0x40ff, 0xc18d, 0x21, 0 - .dw 0x4140, 0xc18d, 0x417f, 0xc18d, 0x21, 0 - .dw 0x41c0, 0xc18d, 0x41ff, 0xc18d, 0x21, 0 - .dw 0x4240, 0xc18d, 0x427f, 0xc18d, 0x21, 0 - .dw 0x42c0, 0xc18d, 0x42ff, 0xc18d, 0x21, 0 - .dw 0x4340, 0xc18d, 0x437f, 0xc18d, 0x21, 0 - .dw 0x43c0, 0xc18d, 0x43ff, 0xc18d, 0x21, 0 - .dw 0x4440, 0xc18d, 0x447f, 0xc18d, 0x21, 0 - .dw 0x44c0, 0xc18d, 0x44ff, 0xc18d, 0x21, 0 - .dw 0x4540, 0xc18d, 0x457f, 0xc18d, 0x21, 0 - .dw 0x45c0, 0xc18d, 0x45ff, 0xc18d, 0x21, 0 - .dw 0x4640, 0xc18d, 0x467f, 0xc18d, 0x21, 0 - .dw 0x46c0, 0xc18d, 0x46ff, 0xc18d, 0x21, 0 - .dw 0x4740, 0xc18d, 0x477f, 0xc18d, 0x21, 0 - .dw 0x47c0, 0xc18d, 0x47ff, 0xc18d, 0x21, 0 - .dw 0x4840, 0xc18d, 0x487f, 0xc18d, 0x21, 0 - .dw 0x48c0, 0xc18d, 0x48ff, 0xc18d, 0x21, 0 - .dw 0x4940, 0xc18d, 0x497f, 0xc18d, 0x21, 0 - .dw 0x49c0, 0xc18d, 0x49ff, 0xc18d, 0x21, 0 - .dw 0x4a40, 0xc18d, 0x4a7f, 0xc18d, 0x21, 0 - .dw 0x4ac0, 0xc18d, 0x4aff, 0xc18d, 0x21, 0 - .dw 0x4b40, 0xc18d, 0x4b7f, 0xc18d, 0x21, 0 - .dw 0x4bc0, 0xc18d, 0x4bff, 0xc18d, 0x21, 0 - .dw 0x4c40, 0xc18d, 0x4c7f, 0xc18d, 0x21, 0 - .dw 0x4cc0, 0xc18d, 0x4cff, 0xc18d, 0x21, 0 - .dw 0x4d40, 0xc18d, 0x4d7f, 0xc18d, 0x21, 0 - .dw 0x4dc0, 0xc18d, 0x4dff, 0xc18d, 0x21, 0 - .dw 0x4e40, 0xc18d, 0x4e7f, 0xc18d, 0x21, 0 - .dw 0x4ec0, 0xc18d, 0x4eff, 0xc18d, 0x21, 0 - .dw 0x4f40, 0xc18d, 0x4f7f, 0xc18d, 0x21, 0 - .dw 0x4fc0, 0xc18d, 0x4fff, 0xc18d, 0x21, 0 - .dw 0x5040, 0xc18d, 0x507f, 0xc18d, 0x21, 0 - .dw 0x50c0, 0xc18d, 0x50ff, 0xc18d, 0x21, 0 - .dw 0x5140, 0xc18d, 0x517f, 0xc18d, 0x21, 0 - .dw 0x51c0, 0xc18d, 0x51ff, 0xc18d, 0x21, 0 - .dw 0x5240, 0xc18d, 0x527f, 0xc18d, 0x21, 0 - .dw 0x52c0, 0xc18d, 0x52ff, 0xc18d, 0x21, 0 - .dw 0x5340, 0xc18d, 0x537f, 0xc18d, 0x21, 0 - .dw 0x53c0, 0xc18d, 0x53ff, 0xc18d, 0x21, 0 - .dw 0x5440, 0xc18d, 0x547f, 0xc18d, 0x21, 0 - .dw 0x54c0, 0xc18d, 0x54ff, 0xc18d, 0x21, 0 - .dw 0x5540, 0xc18d, 0x557f, 0xc18d, 0x21, 0 - .dw 0x55c0, 0xc18d, 0x55ff, 0xc18d, 0x21, 0 - .dw 0x5640, 0xc18d, 0x567f, 0xc18d, 0x21, 0 - .dw 0x56c0, 0xc18d, 0x56ff, 0xc18d, 0x21, 0 - .dw 0x5740, 0xc18d, 0x577f, 0xc18d, 0x21, 0 - .dw 0x57c0, 0xc18d, 0x57ff, 0xc18d, 0x21, 0 - .dw 0x5840, 0xc18d, 0x587f, 0xc18d, 0x21, 0 - .dw 0x58c0, 0xc18d, 0x58ff, 0xc18d, 0x21, 0 - .dw 0x5940, 0xc18d, 0x597f, 0xc18d, 0x21, 0 - .dw 0x59c0, 0xc18d, 0x5fff, 0xc18d, 0x21, 0 - .dw 0x6040, 0xc18d, 0x607f, 0xc18d, 0x21, 0 - .dw 0x60c0, 0xc18d, 0x60ff, 0xc18d, 0x21, 0 - .dw 0x6140, 0xc18d, 0x617f, 0xc18d, 0x21, 0 - .dw 0x61c0, 0xc18d, 0x61ff, 0xc18d, 0x21, 0 - .dw 0x6240, 0xc18d, 0x627f, 0xc18d, 0x21, 0 - .dw 0x62c0, 0xc18d, 0x62ff, 0xc18d, 0x21, 0 - .dw 0x6340, 0xc18d, 0x637f, 0xc18d, 0x21, 0 - .dw 0x63c0, 0xc18d, 0x63ff, 0xc18d, 0x21, 0 - .dw 0x6440, 0xc18d, 0x647f, 0xc18d, 0x21, 0 - .dw 0x64c0, 0xc18d, 0x64ff, 0xc18d, 0x21, 0 - .dw 0x6540, 0xc18d, 0x657f, 0xc18d, 0x21, 0 - .dw 0x65c0, 0xc18d, 0x65ff, 0xc18d, 0x21, 0 - .dw 0x6640, 0xc18d, 0x667f, 0xc18d, 0x21, 0 - .dw 0x66c0, 0xc18d, 0x66ff, 0xc18d, 0x21, 0 - .dw 0x6740, 0xc18d, 0x677f, 0xc18d, 0x21, 0 - .dw 0x67c0, 0xc18d, 0x67ff, 0xc18d, 0x21, 0 - .dw 0x6840, 0xc18d, 0x687f, 0xc18d, 0x21, 0 - .dw 0x68c0, 0xc18d, 0x68ff, 0xc18d, 0x21, 0 - .dw 0x6940, 0xc18d, 0x697f, 0xc18d, 0x21, 0 - .dw 0x69c0, 0xc18d, 0x69ff, 0xc18d, 0x21, 0 - .dw 0x6a40, 0xc18d, 0x6a7f, 0xc18d, 0x21, 0 - .dw 0x6ac0, 0xc18d, 0x6aff, 0xc18d, 0x21, 0 - .dw 0x6b40, 0xc18d, 0x6b7f, 0xc18d, 0x21, 0 - .dw 0x6bc0, 0xc18d, 0x6bff, 0xc18d, 0x21, 0 - .dw 0x6c40, 0xc18d, 0x6c7f, 0xc18d, 0x21, 0 - .dw 0x6cc0, 0xc18d, 0x6cff, 0xc18d, 0x21, 0 - .dw 0x6d40, 0xc18d, 0x6d7f, 0xc18d, 0x21, 0 - .dw 0x6dc0, 0xc18d, 0x6dff, 0xc18d, 0x21, 0 - .dw 0x6e40, 0xc18d, 0x6e7f, 0xc18d, 0x21, 0 - .dw 0x6ec0, 0xc18d, 0x6eff, 0xc18d, 0x21, 0 - .dw 0x6f40, 0xc18d, 0x6f7f, 0xc18d, 0x21, 0 - .dw 0x6fc0, 0xc18d, 0x6fff, 0xc18d, 0x21, 0 - .dw 0x7040, 0xc18d, 0x707f, 0xc18d, 0x21, 0 - .dw 0x70c0, 0xc18d, 0x70ff, 0xc18d, 0x21, 0 - .dw 0x7140, 0xc18d, 0x717f, 0xc18d, 0x21, 0 - .dw 0x71c0, 0xc18d, 0x71ff, 0xc18d, 0x21, 0 - .dw 0x7240, 0xc18d, 0x727f, 0xc18d, 0x21, 0 - .dw 0x72c0, 0xc18d, 0x72ff, 0xc18d, 0x21, 0 - .dw 0x7340, 0xc18d, 0x737f, 0xc18d, 0x21, 0 - .dw 0x73c0, 0xc18d, 0x73ff, 0xc18d, 0x21, 0 - .dw 0x7440, 0xc18d, 0x747f, 0xc18d, 0x21, 0 - .dw 0x74c0, 0xc18d, 0x74ff, 0xc18d, 0x21, 0 - .dw 0x7540, 0xc18d, 0x757f, 0xc18d, 0x21, 0 - .dw 0x75c0, 0xc18d, 0x75ff, 0xc18d, 0x21, 0 - .dw 0x7640, 0xc18d, 0x767f, 0xc18d, 0x21, 0 - .dw 0x76c0, 0xc18d, 0x76ff, 0xc18d, 0x21, 0 - .dw 0x7740, 0xc18d, 0x777f, 0xc18d, 0x21, 0 - .dw 0x77c0, 0xc18d, 0x77ff, 0xc18d, 0x21, 0 - .dw 0x7840, 0xc18d, 0x787f, 0xc18d, 0x21, 0 - .dw 0x78c0, 0xc18d, 0x78ff, 0xc18d, 0x21, 0 - .dw 0x7940, 0xc18d, 0x797f, 0xc18d, 0x21, 0 - .dw 0x79c0, 0xc18d, 0x7fff, 0xc18d, 0x21, 0 - .dw 0x8040, 0xc18d, 0x807f, 0xc18d, 0x21, 0 - .dw 0x80c0, 0xc18d, 0x80ff, 0xc18d, 0x21, 0 - .dw 0x8140, 0xc18d, 0x817f, 0xc18d, 0x21, 0 - .dw 0x81c0, 0xc18d, 0x81ff, 0xc18d, 0x21, 0 - .dw 0x8240, 0xc18d, 0x827f, 0xc18d, 0x21, 0 - .dw 0x82c0, 0xc18d, 0x82ff, 0xc18d, 0x21, 0 - .dw 0x8340, 0xc18d, 0x837f, 0xc18d, 0x21, 0 - .dw 0x83c0, 0xc18d, 0x83ff, 0xc18d, 0x21, 0 - .dw 0x8440, 0xc18d, 0x847f, 0xc18d, 0x21, 0 - .dw 0x84c0, 0xc18d, 0x84ff, 0xc18d, 0x21, 0 - .dw 0x8540, 0xc18d, 0x857f, 0xc18d, 0x21, 0 - .dw 0x85c0, 0xc18d, 0x85ff, 0xc18d, 0x21, 0 - .dw 0x8640, 0xc18d, 0x867f, 0xc18d, 0x21, 0 - .dw 0x86c0, 0xc18d, 0x86ff, 0xc18d, 0x21, 0 - .dw 0x8740, 0xc18d, 0x877f, 0xc18d, 0x21, 0 - .dw 0x87c0, 0xc18d, 0x87ff, 0xc18d, 0x21, 0 - .dw 0x8840, 0xc18d, 0x887f, 0xc18d, 0x21, 0 - .dw 0x88c0, 0xc18d, 0x88ff, 0xc18d, 0x21, 0 - .dw 0x8940, 0xc18d, 0x897f, 0xc18d, 0x21, 0 - .dw 0x89c0, 0xc18d, 0x89ff, 0xc18d, 0x21, 0 - .dw 0x8a40, 0xc18d, 0x8a7f, 0xc18d, 0x21, 0 - .dw 0x8ac0, 0xc18d, 0x8aff, 0xc18d, 0x21, 0 - .dw 0x8b40, 0xc18d, 0x8b7f, 0xc18d, 0x21, 0 - .dw 0x8bc0, 0xc18d, 0x8bff, 0xc18d, 0x21, 0 - .dw 0x8c40, 0xc18d, 0x8c7f, 0xc18d, 0x21, 0 - .dw 0x8cc0, 0xc18d, 0x8cff, 0xc18d, 0x21, 0 - .dw 0x8d40, 0xc18d, 0x8d7f, 0xc18d, 0x21, 0 - .dw 0x8dc0, 0xc18d, 0x8dff, 0xc18d, 0x21, 0 - .dw 0x8e40, 0xc18d, 0x8e7f, 0xc18d, 0x21, 0 - .dw 0x8ec0, 0xc18d, 0x8eff, 0xc18d, 0x21, 0 - .dw 0x8f40, 0xc18d, 0x8f7f, 0xc18d, 0x21, 0 - .dw 0x8fc0, 0xc18d, 0x8fff, 0xc18d, 0x21, 0 - .dw 0x9040, 0xc18d, 0x907f, 0xc18d, 0x21, 0 - .dw 0x90c0, 0xc18d, 0x90ff, 0xc18d, 0x21, 0 - .dw 0x9140, 0xc18d, 0x917f, 0xc18d, 0x21, 0 - .dw 0x91c0, 0xc18d, 0x91ff, 0xc18d, 0x21, 0 - .dw 0x9240, 0xc18d, 0x927f, 0xc18d, 0x21, 0 - .dw 0x92c0, 0xc18d, 0x92ff, 0xc18d, 0x21, 0 - .dw 0x9340, 0xc18d, 0x937f, 0xc18d, 0x21, 0 - .dw 0x93c0, 0xc18d, 0x93ff, 0xc18d, 0x21, 0 - .dw 0x9440, 0xc18d, 0x947f, 0xc18d, 0x21, 0 - .dw 0x94c0, 0xc18d, 0x94ff, 0xc18d, 0x21, 0 - .dw 0x9540, 0xc18d, 0x957f, 0xc18d, 0x21, 0 - .dw 0x95c0, 0xc18d, 0x95ff, 0xc18d, 0x21, 0 - .dw 0x9640, 0xc18d, 0x967f, 0xc18d, 0x21, 0 - .dw 0x96c0, 0xc18d, 0x96ff, 0xc18d, 0x21, 0 - .dw 0x9740, 0xc18d, 0x977f, 0xc18d, 0x21, 0 - .dw 0x97c0, 0xc18d, 0x97ff, 0xc18d, 0x21, 0 - .dw 0x9840, 0xc18d, 0x987f, 0xc18d, 0x21, 0 - .dw 0x98c0, 0xc18d, 0x98ff, 0xc18d, 0x21, 0 - .dw 0x9940, 0xc18d, 0x997f, 0xc18d, 0x21, 0 - .dw 0x99c0, 0xc18d, 0x9fff, 0xc18d, 0x21, 0 - .dw 0xa040, 0xc18d, 0xa07f, 0xc18d, 0x21, 0 - .dw 0xa0c0, 0xc18d, 0xa0ff, 0xc18d, 0x21, 0 - .dw 0xa140, 0xc18d, 0xa17f, 0xc18d, 0x21, 0 - .dw 0xa1c0, 0xc18d, 0xa1ff, 0xc18d, 0x21, 0 - .dw 0xa240, 0xc18d, 0xa27f, 0xc18d, 0x21, 0 - .dw 0xa2c0, 0xc18d, 0xa2ff, 0xc18d, 0x21, 0 - .dw 0xa340, 0xc18d, 0xa37f, 0xc18d, 0x21, 0 - .dw 0xa3c0, 0xc18d, 0xa3ff, 0xc18d, 0x21, 0 - .dw 0xa440, 0xc18d, 0xa47f, 0xc18d, 0x21, 0 - .dw 0xa4c0, 0xc18d, 0xa4ff, 0xc18d, 0x21, 0 - .dw 0xa540, 0xc18d, 0xa57f, 0xc18d, 0x21, 0 - .dw 0xa5c0, 0xc18d, 0xa5ff, 0xc18d, 0x21, 0 - .dw 0xa640, 0xc18d, 0xa67f, 0xc18d, 0x21, 0 - .dw 0xa6c0, 0xc18d, 0xa6ff, 0xc18d, 0x21, 0 - .dw 0xa740, 0xc18d, 0xa77f, 0xc18d, 0x21, 0 - .dw 0xa7c0, 0xc18d, 0xa7ff, 0xc18d, 0x21, 0 - .dw 0xa840, 0xc18d, 0xa87f, 0xc18d, 0x21, 0 - .dw 0xa8c0, 0xc18d, 0xa8ff, 0xc18d, 0x21, 0 - .dw 0xa940, 0xc18d, 0xa97f, 0xc18d, 0x21, 0 - .dw 0xa9c0, 0xc18d, 0xa9ff, 0xc18d, 0x21, 0 - .dw 0xaa40, 0xc18d, 0xaa7f, 0xc18d, 0x21, 0 - .dw 0xaac0, 0xc18d, 0xaaff, 0xc18d, 0x21, 0 - .dw 0xab40, 0xc18d, 0xab7f, 0xc18d, 0x21, 0 - .dw 0xabc0, 0xc18d, 0xabff, 0xc18d, 0x21, 0 - .dw 0xac40, 0xc18d, 0xac7f, 0xc18d, 0x21, 0 - .dw 0xacc0, 0xc18d, 0xacff, 0xc18d, 0x21, 0 - .dw 0xad40, 0xc18d, 0xad7f, 0xc18d, 0x21, 0 - .dw 0xadc0, 0xc18d, 0xadff, 0xc18d, 0x21, 0 - .dw 0xae40, 0xc18d, 0xae7f, 0xc18d, 0x21, 0 - .dw 0xaec0, 0xc18d, 0xaeff, 0xc18d, 0x21, 0 - .dw 0xaf40, 0xc18d, 0xaf7f, 0xc18d, 0x21, 0 - .dw 0xafc0, 0xc18d, 0xafff, 0xc18d, 0x21, 0 - .dw 0xb040, 0xc18d, 0xb07f, 0xc18d, 0x21, 0 - .dw 0xb0c0, 0xc18d, 0xb0ff, 0xc18d, 0x21, 0 - .dw 0xb140, 0xc18d, 0xb17f, 0xc18d, 0x21, 0 - .dw 0xb1c0, 0xc18d, 0xb1ff, 0xc18d, 0x21, 0 - .dw 0xb240, 0xc18d, 0xb27f, 0xc18d, 0x21, 0 - .dw 0xb2c0, 0xc18d, 0xb2ff, 0xc18d, 0x21, 0 - .dw 0xb340, 0xc18d, 0xb37f, 0xc18d, 0x21, 0 - .dw 0xb3c0, 0xc18d, 0xb3ff, 0xc18d, 0x21, 0 - .dw 0xb440, 0xc18d, 0xb47f, 0xc18d, 0x21, 0 - .dw 0xb4c0, 0xc18d, 0xb4ff, 0xc18d, 0x21, 0 - .dw 0xb540, 0xc18d, 0xb57f, 0xc18d, 0x21, 0 - .dw 0xb5c0, 0xc18d, 0xb5ff, 0xc18d, 0x21, 0 - .dw 0xb640, 0xc18d, 0xb67f, 0xc18d, 0x21, 0 - .dw 0xb6c0, 0xc18d, 0xb6ff, 0xc18d, 0x21, 0 - .dw 0xb740, 0xc18d, 0xb77f, 0xc18d, 0x21, 0 - .dw 0xb7c0, 0xc18d, 0xb7ff, 0xc18d, 0x21, 0 - .dw 0xb840, 0xc18d, 0xb87f, 0xc18d, 0x21, 0 - .dw 0xb8c0, 0xc18d, 0xb8ff, 0xc18d, 0x21, 0 - .dw 0xb940, 0xc18d, 0xb97f, 0xc18d, 0x21, 0 - .dw 0xb9c0, 0xc18d, 0xbfff, 0xc18d, 0x21, 0 - .dw 0xc040, 0xc18d, 0xc07f, 0xc18d, 0x21, 0 - .dw 0xc0c0, 0xc18d, 0xc0ff, 0xc18d, 0x21, 0 - .dw 0xc140, 0xc18d, 0xc17f, 0xc18d, 0x21, 0 - .dw 0xc1c0, 0xc18d, 0xc1ff, 0xc18d, 0x21, 0 - .dw 0xc240, 0xc18d, 0xc27f, 0xc18d, 0x21, 0 - .dw 0xc2c0, 0xc18d, 0xc2ff, 0xc18d, 0x21, 0 - .dw 0xc340, 0xc18d, 0xc37f, 0xc18d, 0x21, 0 - .dw 0xc3c0, 0xc18d, 0xc3ff, 0xc18d, 0x21, 0 - .dw 0xc440, 0xc18d, 0xc47f, 0xc18d, 0x21, 0 - .dw 0xc4c0, 0xc18d, 0xc4ff, 0xc18d, 0x21, 0 - .dw 0xc540, 0xc18d, 0xc57f, 0xc18d, 0x21, 0 - .dw 0xc5c0, 0xc18d, 0xc5ff, 0xc18d, 0x21, 0 - .dw 0xc640, 0xc18d, 0xc67f, 0xc18d, 0x21, 0 - .dw 0xc6c0, 0xc18d, 0xc6ff, 0xc18d, 0x21, 0 - .dw 0xc740, 0xc18d, 0xc77f, 0xc18d, 0x21, 0 - .dw 0xc7c0, 0xc18d, 0xc7ff, 0xc18d, 0x21, 0 - .dw 0xc840, 0xc18d, 0xc87f, 0xc18d, 0x21, 0 - .dw 0xc8c0, 0xc18d, 0xc8ff, 0xc18d, 0x21, 0 - .dw 0xc940, 0xc18d, 0xc97f, 0xc18d, 0x21, 0 - .dw 0xc9c0, 0xc18d, 0xc9ff, 0xc18d, 0x21, 0 - .dw 0xca40, 0xc18d, 0xca7f, 0xc18d, 0x21, 0 - .dw 0xcac0, 0xc18d, 0xcaff, 0xc18d, 0x21, 0 - .dw 0xcb40, 0xc18d, 0xcb7f, 0xc18d, 0x21, 0 - .dw 0xcbc0, 0xc18d, 0xcbff, 0xc18d, 0x21, 0 - .dw 0xcc40, 0xc18d, 0xcc7f, 0xc18d, 0x21, 0 - .dw 0xccc0, 0xc18d, 0xccff, 0xc18d, 0x21, 0 - .dw 0xcd40, 0xc18d, 0xcd7f, 0xc18d, 0x21, 0 - .dw 0xcdc0, 0xc18d, 0xcdff, 0xc18d, 0x21, 0 - .dw 0xce40, 0xc18d, 0xce7f, 0xc18d, 0x21, 0 - .dw 0xcec0, 0xc18d, 0xceff, 0xc18d, 0x21, 0 - .dw 0xcf40, 0xc18d, 0xcf7f, 0xc18d, 0x21, 0 - .dw 0xcfc0, 0xc18d, 0xcfff, 0xc18d, 0x21, 0 - .dw 0xd040, 0xc18d, 0xd07f, 0xc18d, 0x21, 0 - .dw 0xd0c0, 0xc18d, 0xd0ff, 0xc18d, 0x21, 0 - .dw 0xd140, 0xc18d, 0xd17f, 0xc18d, 0x21, 0 - .dw 0xd1c0, 0xc18d, 0xd1ff, 0xc18d, 0x21, 0 - .dw 0xd240, 0xc18d, 0xd27f, 0xc18d, 0x21, 0 - .dw 0xd2c0, 0xc18d, 0xd2ff, 0xc18d, 0x21, 0 - .dw 0xd340, 0xc18d, 0xd37f, 0xc18d, 0x21, 0 - .dw 0xd3c0, 0xc18d, 0xd3ff, 0xc18d, 0x21, 0 - .dw 0xd440, 0xc18d, 0xd47f, 0xc18d, 0x21, 0 - .dw 0xd4c0, 0xc18d, 0xd4ff, 0xc18d, 0x21, 0 - .dw 0xd540, 0xc18d, 0xd57f, 0xc18d, 0x21, 0 - .dw 0xd5c0, 0xc18d, 0xd5ff, 0xc18d, 0x21, 0 - .dw 0xd640, 0xc18d, 0xd67f, 0xc18d, 0x21, 0 - .dw 0xd6c0, 0xc18d, 0xd6ff, 0xc18d, 0x21, 0 - .dw 0xd740, 0xc18d, 0xd77f, 0xc18d, 0x21, 0 - .dw 0xd7c0, 0xc18d, 0xd7ff, 0xc18d, 0x21, 0 - .dw 0xd840, 0xc18d, 0xd87f, 0xc18d, 0x21, 0 - .dw 0xd8c0, 0xc18d, 0xd8ff, 0xc18d, 0x21, 0 - .dw 0xd940, 0xc18d, 0xd97f, 0xc18d, 0x21, 0 - .dw 0xd9c0, 0xc18d, 0xdfff, 0xc18d, 0x21, 0 - .dw 0xe040, 0xc18d, 0xe07f, 0xc18d, 0x21, 0 - .dw 0xe0c0, 0xc18d, 0xe0ff, 0xc18d, 0x21, 0 - .dw 0xe140, 0xc18d, 0xe17f, 0xc18d, 0x21, 0 - .dw 0xe1c0, 0xc18d, 0xe1ff, 0xc18d, 0x21, 0 - .dw 0xe240, 0xc18d, 0xe27f, 0xc18d, 0x21, 0 - .dw 0xe2c0, 0xc18d, 0xe2ff, 0xc18d, 0x21, 0 - .dw 0xe340, 0xc18d, 0xe37f, 0xc18d, 0x21, 0 - .dw 0xe3c0, 0xc18d, 0xe3ff, 0xc18d, 0x21, 0 - .dw 0xe440, 0xc18d, 0xe47f, 0xc18d, 0x21, 0 - .dw 0xe4c0, 0xc18d, 0xe4ff, 0xc18d, 0x21, 0 - .dw 0xe540, 0xc18d, 0xe57f, 0xc18d, 0x21, 0 - .dw 0xe5c0, 0xc18d, 0xe5ff, 0xc18d, 0x21, 0 - .dw 0xe640, 0xc18d, 0xe67f, 0xc18d, 0x21, 0 - .dw 0xe6c0, 0xc18d, 0xe6ff, 0xc18d, 0x21, 0 - .dw 0xe740, 0xc18d, 0xe77f, 0xc18d, 0x21, 0 - .dw 0xe7c0, 0xc18d, 0xe7ff, 0xc18d, 0x21, 0 - .dw 0xe840, 0xc18d, 0xe87f, 0xc18d, 0x21, 0 - .dw 0xe8c0, 0xc18d, 0xe8ff, 0xc18d, 0x21, 0 - .dw 0xe940, 0xc18d, 0xe97f, 0xc18d, 0x21, 0 - .dw 0xe9c0, 0xc18d, 0xe9ff, 0xc18d, 0x21, 0 - .dw 0xea40, 0xc18d, 0xea7f, 0xc18d, 0x21, 0 - .dw 0xeac0, 0xc18d, 0xeaff, 0xc18d, 0x21, 0 - .dw 0xeb40, 0xc18d, 0xeb7f, 0xc18d, 0x21, 0 - .dw 0xebc0, 0xc18d, 0xebff, 0xc18d, 0x21, 0 - .dw 0xec40, 0xc18d, 0xec7f, 0xc18d, 0x21, 0 - .dw 0xecc0, 0xc18d, 0xecff, 0xc18d, 0x21, 0 - .dw 0xed40, 0xc18d, 0xed7f, 0xc18d, 0x21, 0 - .dw 0xedc0, 0xc18d, 0xedff, 0xc18d, 0x21, 0 - .dw 0xee40, 0xc18d, 0xee7f, 0xc18d, 0x21, 0 - .dw 0xeec0, 0xc18d, 0xeeff, 0xc18d, 0x21, 0 - .dw 0xef40, 0xc18d, 0xef7f, 0xc18d, 0x21, 0 - .dw 0xefc0, 0xc18d, 0xefff, 0xc18d, 0x21, 0 - .dw 0xf040, 0xc18d, 0xf07f, 0xc18d, 0x21, 0 - .dw 0xf0c0, 0xc18d, 0xf0ff, 0xc18d, 0x21, 0 - .dw 0xf140, 0xc18d, 0xf17f, 0xc18d, 0x21, 0 - .dw 0xf1c0, 0xc18d, 0xf1ff, 0xc18d, 0x21, 0 - .dw 0xf240, 0xc18d, 0xf27f, 0xc18d, 0x21, 0 - .dw 0xf2c0, 0xc18d, 0xf2ff, 0xc18d, 0x21, 0 - .dw 0xf340, 0xc18d, 0xf37f, 0xc18d, 0x21, 0 - .dw 0xf3c0, 0xc18d, 0xf3ff, 0xc18d, 0x21, 0 - .dw 0xf440, 0xc18d, 0xf47f, 0xc18d, 0x21, 0 - .dw 0xf4c0, 0xc18d, 0xf4ff, 0xc18d, 0x21, 0 - .dw 0xf540, 0xc18d, 0xf57f, 0xc18d, 0x21, 0 - .dw 0xf5c0, 0xc18d, 0xf5ff, 0xc18d, 0x21, 0 - .dw 0xf640, 0xc18d, 0xf67f, 0xc18d, 0x21, 0 - .dw 0xf6c0, 0xc18d, 0xf6ff, 0xc18d, 0x21, 0 - .dw 0xf740, 0xc18d, 0xf77f, 0xc18d, 0x21, 0 - .dw 0xf7c0, 0xc18d, 0xf7ff, 0xc18d, 0x21, 0 - .dw 0xf840, 0xc18d, 0xf87f, 0xc18d, 0x21, 0 - .dw 0xf8c0, 0xc18d, 0xf8ff, 0xc18d, 0x21, 0 - .dw 0xf940, 0xc18d, 0xf97f, 0xc18d, 0x21, 0 - .dw 0xf9c0, 0xc18d, 0xffff, 0xc18d, 0x21, 0 - .dw 0x0040, 0xc18e, 0x007f, 0xc18e, 0x21, 0 - .dw 0x00c0, 0xc18e, 0x00ff, 0xc18e, 0x21, 0 - .dw 0x0140, 0xc18e, 0x017f, 0xc18e, 0x21, 0 - .dw 0x01c0, 0xc18e, 0x01ff, 0xc18e, 0x21, 0 - .dw 0x0240, 0xc18e, 0x027f, 0xc18e, 0x21, 0 - .dw 0x02c0, 0xc18e, 0x02ff, 0xc18e, 0x21, 0 - .dw 0x0340, 0xc18e, 0x037f, 0xc18e, 0x21, 0 - .dw 0x03c0, 0xc18e, 0x03ff, 0xc18e, 0x21, 0 - .dw 0x0440, 0xc18e, 0x047f, 0xc18e, 0x21, 0 - .dw 0x04c0, 0xc18e, 0x04ff, 0xc18e, 0x21, 0 - .dw 0x0540, 0xc18e, 0x057f, 0xc18e, 0x21, 0 - .dw 0x05c0, 0xc18e, 0x05ff, 0xc18e, 0x21, 0 - .dw 0x0640, 0xc18e, 0x067f, 0xc18e, 0x21, 0 - .dw 0x06c0, 0xc18e, 0x06ff, 0xc18e, 0x21, 0 - .dw 0x0740, 0xc18e, 0x077f, 0xc18e, 0x21, 0 - .dw 0x07c0, 0xc18e, 0x07ff, 0xc18e, 0x21, 0 - .dw 0x0840, 0xc18e, 0x087f, 0xc18e, 0x21, 0 - .dw 0x08c0, 0xc18e, 0x08ff, 0xc18e, 0x21, 0 - .dw 0x0940, 0xc18e, 0x097f, 0xc18e, 0x21, 0 - .dw 0x09c0, 0xc18e, 0x09ff, 0xc18e, 0x21, 0 - .dw 0x0a40, 0xc18e, 0x0a7f, 0xc18e, 0x21, 0 - .dw 0x0ac0, 0xc18e, 0x0aff, 0xc18e, 0x21, 0 - .dw 0x0b40, 0xc18e, 0x0b7f, 0xc18e, 0x21, 0 - .dw 0x0bc0, 0xc18e, 0x0bff, 0xc18e, 0x21, 0 - .dw 0x0c40, 0xc18e, 0x0c7f, 0xc18e, 0x21, 0 - .dw 0x0cc0, 0xc18e, 0x0cff, 0xc18e, 0x21, 0 - .dw 0x0d40, 0xc18e, 0x0d7f, 0xc18e, 0x21, 0 - .dw 0x0dc0, 0xc18e, 0x0dff, 0xc18e, 0x21, 0 - .dw 0x0e40, 0xc18e, 0x0e7f, 0xc18e, 0x21, 0 - .dw 0x0ec0, 0xc18e, 0x0eff, 0xc18e, 0x21, 0 - .dw 0x0f40, 0xc18e, 0x0f7f, 0xc18e, 0x21, 0 - .dw 0x0fc0, 0xc18e, 0x0fff, 0xc18e, 0x21, 0 - .dw 0x1040, 0xc18e, 0x107f, 0xc18e, 0x21, 0 - .dw 0x10c0, 0xc18e, 0x10ff, 0xc18e, 0x21, 0 - .dw 0x1140, 0xc18e, 0x117f, 0xc18e, 0x21, 0 - .dw 0x11c0, 0xc18e, 0x11ff, 0xc18e, 0x21, 0 - .dw 0x1240, 0xc18e, 0x127f, 0xc18e, 0x21, 0 - .dw 0x12c0, 0xc18e, 0x12ff, 0xc18e, 0x21, 0 - .dw 0x1340, 0xc18e, 0x137f, 0xc18e, 0x21, 0 - .dw 0x13c0, 0xc18e, 0x13ff, 0xc18e, 0x21, 0 - .dw 0x1440, 0xc18e, 0x147f, 0xc18e, 0x21, 0 - .dw 0x14c0, 0xc18e, 0x14ff, 0xc18e, 0x21, 0 - .dw 0x1540, 0xc18e, 0x157f, 0xc18e, 0x21, 0 - .dw 0x15c0, 0xc18e, 0x15ff, 0xc18e, 0x21, 0 - .dw 0x1640, 0xc18e, 0x167f, 0xc18e, 0x21, 0 - .dw 0x16c0, 0xc18e, 0x16ff, 0xc18e, 0x21, 0 - .dw 0x1740, 0xc18e, 0x177f, 0xc18e, 0x21, 0 - .dw 0x17c0, 0xc18e, 0x17ff, 0xc18e, 0x21, 0 - .dw 0x1840, 0xc18e, 0x187f, 0xc18e, 0x21, 0 - .dw 0x18c0, 0xc18e, 0x18ff, 0xc18e, 0x21, 0 - .dw 0x1940, 0xc18e, 0x197f, 0xc18e, 0x21, 0 - .dw 0x19c0, 0xc18e, 0x1fff, 0xc18e, 0x21, 0 - .dw 0x2040, 0xc18e, 0x207f, 0xc18e, 0x21, 0 - .dw 0x20c0, 0xc18e, 0x20ff, 0xc18e, 0x21, 0 - .dw 0x2140, 0xc18e, 0x217f, 0xc18e, 0x21, 0 - .dw 0x21c0, 0xc18e, 0x21ff, 0xc18e, 0x21, 0 - .dw 0x2240, 0xc18e, 0x227f, 0xc18e, 0x21, 0 - .dw 0x22c0, 0xc18e, 0x22ff, 0xc18e, 0x21, 0 - .dw 0x2340, 0xc18e, 0x237f, 0xc18e, 0x21, 0 - .dw 0x23c0, 0xc18e, 0x23ff, 0xc18e, 0x21, 0 - .dw 0x2440, 0xc18e, 0x247f, 0xc18e, 0x21, 0 - .dw 0x24c0, 0xc18e, 0x24ff, 0xc18e, 0x21, 0 - .dw 0x2540, 0xc18e, 0x257f, 0xc18e, 0x21, 0 - .dw 0x25c0, 0xc18e, 0x25ff, 0xc18e, 0x21, 0 - .dw 0x2640, 0xc18e, 0x267f, 0xc18e, 0x21, 0 - .dw 0x26c0, 0xc18e, 0x26ff, 0xc18e, 0x21, 0 - .dw 0x2740, 0xc18e, 0x277f, 0xc18e, 0x21, 0 - .dw 0x27c0, 0xc18e, 0x27ff, 0xc18e, 0x21, 0 - .dw 0x2840, 0xc18e, 0x287f, 0xc18e, 0x21, 0 - .dw 0x28c0, 0xc18e, 0x28ff, 0xc18e, 0x21, 0 - .dw 0x2940, 0xc18e, 0x297f, 0xc18e, 0x21, 0 - .dw 0x29c0, 0xc18e, 0x29ff, 0xc18e, 0x21, 0 - .dw 0x2a40, 0xc18e, 0x2a7f, 0xc18e, 0x21, 0 - .dw 0x2ac0, 0xc18e, 0x2aff, 0xc18e, 0x21, 0 - .dw 0x2b40, 0xc18e, 0x2b7f, 0xc18e, 0x21, 0 - .dw 0x2bc0, 0xc18e, 0x2bff, 0xc18e, 0x21, 0 - .dw 0x2c40, 0xc18e, 0x2c7f, 0xc18e, 0x21, 0 - .dw 0x2cc0, 0xc18e, 0x2cff, 0xc18e, 0x21, 0 - .dw 0x2d40, 0xc18e, 0x2d7f, 0xc18e, 0x21, 0 - .dw 0x2dc0, 0xc18e, 0x2dff, 0xc18e, 0x21, 0 - .dw 0x2e40, 0xc18e, 0x2e7f, 0xc18e, 0x21, 0 - .dw 0x2ec0, 0xc18e, 0x2eff, 0xc18e, 0x21, 0 - .dw 0x2f40, 0xc18e, 0x2f7f, 0xc18e, 0x21, 0 - .dw 0x2fc0, 0xc18e, 0x2fff, 0xc18e, 0x21, 0 - .dw 0x3040, 0xc18e, 0x307f, 0xc18e, 0x21, 0 - .dw 0x30c0, 0xc18e, 0x30ff, 0xc18e, 0x21, 0 - .dw 0x3140, 0xc18e, 0x317f, 0xc18e, 0x21, 0 - .dw 0x31c0, 0xc18e, 0x31ff, 0xc18e, 0x21, 0 - .dw 0x3240, 0xc18e, 0x327f, 0xc18e, 0x21, 0 - .dw 0x32c0, 0xc18e, 0x32ff, 0xc18e, 0x21, 0 - .dw 0x3340, 0xc18e, 0x337f, 0xc18e, 0x21, 0 - .dw 0x33c0, 0xc18e, 0x33ff, 0xc18e, 0x21, 0 - .dw 0x3440, 0xc18e, 0x347f, 0xc18e, 0x21, 0 - .dw 0x34c0, 0xc18e, 0x34ff, 0xc18e, 0x21, 0 - .dw 0x3540, 0xc18e, 0x357f, 0xc18e, 0x21, 0 - .dw 0x35c0, 0xc18e, 0x35ff, 0xc18e, 0x21, 0 - .dw 0x3640, 0xc18e, 0x367f, 0xc18e, 0x21, 0 - .dw 0x36c0, 0xc18e, 0x36ff, 0xc18e, 0x21, 0 - .dw 0x3740, 0xc18e, 0x377f, 0xc18e, 0x21, 0 - .dw 0x37c0, 0xc18e, 0x37ff, 0xc18e, 0x21, 0 - .dw 0x3840, 0xc18e, 0x387f, 0xc18e, 0x21, 0 - .dw 0x38c0, 0xc18e, 0x38ff, 0xc18e, 0x21, 0 - .dw 0x3940, 0xc18e, 0x397f, 0xc18e, 0x21, 0 - .dw 0x39c0, 0xc18e, 0x3fff, 0xc18e, 0x21, 0 - .dw 0x4040, 0xc18e, 0x407f, 0xc18e, 0x21, 0 - .dw 0x40c0, 0xc18e, 0x40ff, 0xc18e, 0x21, 0 - .dw 0x4140, 0xc18e, 0x417f, 0xc18e, 0x21, 0 - .dw 0x41c0, 0xc18e, 0x41ff, 0xc18e, 0x21, 0 - .dw 0x4240, 0xc18e, 0x427f, 0xc18e, 0x21, 0 - .dw 0x42c0, 0xc18e, 0x42ff, 0xc18e, 0x21, 0 - .dw 0x4340, 0xc18e, 0x437f, 0xc18e, 0x21, 0 - .dw 0x43c0, 0xc18e, 0x43ff, 0xc18e, 0x21, 0 - .dw 0x4440, 0xc18e, 0x447f, 0xc18e, 0x21, 0 - .dw 0x44c0, 0xc18e, 0x44ff, 0xc18e, 0x21, 0 - .dw 0x4540, 0xc18e, 0x457f, 0xc18e, 0x21, 0 - .dw 0x45c0, 0xc18e, 0x45ff, 0xc18e, 0x21, 0 - .dw 0x4640, 0xc18e, 0x467f, 0xc18e, 0x21, 0 - .dw 0x46c0, 0xc18e, 0x46ff, 0xc18e, 0x21, 0 - .dw 0x4740, 0xc18e, 0x477f, 0xc18e, 0x21, 0 - .dw 0x47c0, 0xc18e, 0x47ff, 0xc18e, 0x21, 0 - .dw 0x4840, 0xc18e, 0x487f, 0xc18e, 0x21, 0 - .dw 0x48c0, 0xc18e, 0x48ff, 0xc18e, 0x21, 0 - .dw 0x4940, 0xc18e, 0x497f, 0xc18e, 0x21, 0 - .dw 0x49c0, 0xc18e, 0x49ff, 0xc18e, 0x21, 0 - .dw 0x4a40, 0xc18e, 0x4a7f, 0xc18e, 0x21, 0 - .dw 0x4ac0, 0xc18e, 0x4aff, 0xc18e, 0x21, 0 - .dw 0x4b40, 0xc18e, 0x4b7f, 0xc18e, 0x21, 0 - .dw 0x4bc0, 0xc18e, 0x4bff, 0xc18e, 0x21, 0 - .dw 0x4c40, 0xc18e, 0x4c7f, 0xc18e, 0x21, 0 - .dw 0x4cc0, 0xc18e, 0x4cff, 0xc18e, 0x21, 0 - .dw 0x4d40, 0xc18e, 0x4d7f, 0xc18e, 0x21, 0 - .dw 0x4dc0, 0xc18e, 0x4dff, 0xc18e, 0x21, 0 - .dw 0x4e40, 0xc18e, 0x4e7f, 0xc18e, 0x21, 0 - .dw 0x4ec0, 0xc18e, 0x4eff, 0xc18e, 0x21, 0 - .dw 0x4f40, 0xc18e, 0x4f7f, 0xc18e, 0x21, 0 - .dw 0x4fc0, 0xc18e, 0x4fff, 0xc18e, 0x21, 0 - .dw 0x5040, 0xc18e, 0x507f, 0xc18e, 0x21, 0 - .dw 0x50c0, 0xc18e, 0x50ff, 0xc18e, 0x21, 0 - .dw 0x5140, 0xc18e, 0x517f, 0xc18e, 0x21, 0 - .dw 0x51c0, 0xc18e, 0x51ff, 0xc18e, 0x21, 0 - .dw 0x5240, 0xc18e, 0x527f, 0xc18e, 0x21, 0 - .dw 0x52c0, 0xc18e, 0x52ff, 0xc18e, 0x21, 0 - .dw 0x5340, 0xc18e, 0x537f, 0xc18e, 0x21, 0 - .dw 0x53c0, 0xc18e, 0x53ff, 0xc18e, 0x21, 0 - .dw 0x5440, 0xc18e, 0x547f, 0xc18e, 0x21, 0 - .dw 0x54c0, 0xc18e, 0x54ff, 0xc18e, 0x21, 0 - .dw 0x5540, 0xc18e, 0x557f, 0xc18e, 0x21, 0 - .dw 0x55c0, 0xc18e, 0x55ff, 0xc18e, 0x21, 0 - .dw 0x5640, 0xc18e, 0x567f, 0xc18e, 0x21, 0 - .dw 0x56c0, 0xc18e, 0x56ff, 0xc18e, 0x21, 0 - .dw 0x5740, 0xc18e, 0x577f, 0xc18e, 0x21, 0 - .dw 0x57c0, 0xc18e, 0x57ff, 0xc18e, 0x21, 0 - .dw 0x5840, 0xc18e, 0x587f, 0xc18e, 0x21, 0 - .dw 0x58c0, 0xc18e, 0x58ff, 0xc18e, 0x21, 0 - .dw 0x5940, 0xc18e, 0x597f, 0xc18e, 0x21, 0 - .dw 0x59c0, 0xc18e, 0x5fff, 0xc18e, 0x21, 0 - .dw 0x6040, 0xc18e, 0x607f, 0xc18e, 0x21, 0 - .dw 0x60c0, 0xc18e, 0x60ff, 0xc18e, 0x21, 0 - .dw 0x6140, 0xc18e, 0x617f, 0xc18e, 0x21, 0 - .dw 0x61c0, 0xc18e, 0x61ff, 0xc18e, 0x21, 0 - .dw 0x6240, 0xc18e, 0x627f, 0xc18e, 0x21, 0 - .dw 0x62c0, 0xc18e, 0x62ff, 0xc18e, 0x21, 0 - .dw 0x6340, 0xc18e, 0x637f, 0xc18e, 0x21, 0 - .dw 0x63c0, 0xc18e, 0x63ff, 0xc18e, 0x21, 0 - .dw 0x6440, 0xc18e, 0x647f, 0xc18e, 0x21, 0 - .dw 0x64c0, 0xc18e, 0x64ff, 0xc18e, 0x21, 0 - .dw 0x6540, 0xc18e, 0x657f, 0xc18e, 0x21, 0 - .dw 0x65c0, 0xc18e, 0x65ff, 0xc18e, 0x21, 0 - .dw 0x6640, 0xc18e, 0x667f, 0xc18e, 0x21, 0 - .dw 0x66c0, 0xc18e, 0x66ff, 0xc18e, 0x21, 0 - .dw 0x6740, 0xc18e, 0x677f, 0xc18e, 0x21, 0 - .dw 0x67c0, 0xc18e, 0x67ff, 0xc18e, 0x21, 0 - .dw 0x6840, 0xc18e, 0x687f, 0xc18e, 0x21, 0 - .dw 0x68c0, 0xc18e, 0x68ff, 0xc18e, 0x21, 0 - .dw 0x6940, 0xc18e, 0x697f, 0xc18e, 0x21, 0 - .dw 0x69c0, 0xc18e, 0x69ff, 0xc18e, 0x21, 0 - .dw 0x6a40, 0xc18e, 0x6a7f, 0xc18e, 0x21, 0 - .dw 0x6ac0, 0xc18e, 0x6aff, 0xc18e, 0x21, 0 - .dw 0x6b40, 0xc18e, 0x6b7f, 0xc18e, 0x21, 0 - .dw 0x6bc0, 0xc18e, 0x6bff, 0xc18e, 0x21, 0 - .dw 0x6c40, 0xc18e, 0x6c7f, 0xc18e, 0x21, 0 - .dw 0x6cc0, 0xc18e, 0x6cff, 0xc18e, 0x21, 0 - .dw 0x6d40, 0xc18e, 0x6d7f, 0xc18e, 0x21, 0 - .dw 0x6dc0, 0xc18e, 0x6dff, 0xc18e, 0x21, 0 - .dw 0x6e40, 0xc18e, 0x6e7f, 0xc18e, 0x21, 0 - .dw 0x6ec0, 0xc18e, 0x6eff, 0xc18e, 0x21, 0 - .dw 0x6f40, 0xc18e, 0x6f7f, 0xc18e, 0x21, 0 - .dw 0x6fc0, 0xc18e, 0x6fff, 0xc18e, 0x21, 0 - .dw 0x7040, 0xc18e, 0x707f, 0xc18e, 0x21, 0 - .dw 0x70c0, 0xc18e, 0x70ff, 0xc18e, 0x21, 0 - .dw 0x7140, 0xc18e, 0x717f, 0xc18e, 0x21, 0 - .dw 0x71c0, 0xc18e, 0x71ff, 0xc18e, 0x21, 0 - .dw 0x7240, 0xc18e, 0x727f, 0xc18e, 0x21, 0 - .dw 0x72c0, 0xc18e, 0x72ff, 0xc18e, 0x21, 0 - .dw 0x7340, 0xc18e, 0x737f, 0xc18e, 0x21, 0 - .dw 0x73c0, 0xc18e, 0x73ff, 0xc18e, 0x21, 0 - .dw 0x7440, 0xc18e, 0x747f, 0xc18e, 0x21, 0 - .dw 0x74c0, 0xc18e, 0x74ff, 0xc18e, 0x21, 0 - .dw 0x7540, 0xc18e, 0x757f, 0xc18e, 0x21, 0 - .dw 0x75c0, 0xc18e, 0x75ff, 0xc18e, 0x21, 0 - .dw 0x7640, 0xc18e, 0x767f, 0xc18e, 0x21, 0 - .dw 0x76c0, 0xc18e, 0x76ff, 0xc18e, 0x21, 0 - .dw 0x7740, 0xc18e, 0x777f, 0xc18e, 0x21, 0 - .dw 0x77c0, 0xc18e, 0x77ff, 0xc18e, 0x21, 0 - .dw 0x7840, 0xc18e, 0x787f, 0xc18e, 0x21, 0 - .dw 0x78c0, 0xc18e, 0x78ff, 0xc18e, 0x21, 0 - .dw 0x7940, 0xc18e, 0x797f, 0xc18e, 0x21, 0 - .dw 0x79c0, 0xc18e, 0x7fff, 0xc18e, 0x21, 0 - .dw 0x8040, 0xc18e, 0x807f, 0xc18e, 0x21, 0 - .dw 0x80c0, 0xc18e, 0x80ff, 0xc18e, 0x21, 0 - .dw 0x8140, 0xc18e, 0x817f, 0xc18e, 0x21, 0 - .dw 0x81c0, 0xc18e, 0x81ff, 0xc18e, 0x21, 0 - .dw 0x8240, 0xc18e, 0x827f, 0xc18e, 0x21, 0 - .dw 0x82c0, 0xc18e, 0x82ff, 0xc18e, 0x21, 0 - .dw 0x8340, 0xc18e, 0x837f, 0xc18e, 0x21, 0 - .dw 0x83c0, 0xc18e, 0x83ff, 0xc18e, 0x21, 0 - .dw 0x8440, 0xc18e, 0x847f, 0xc18e, 0x21, 0 - .dw 0x84c0, 0xc18e, 0x84ff, 0xc18e, 0x21, 0 - .dw 0x8540, 0xc18e, 0x857f, 0xc18e, 0x21, 0 - .dw 0x85c0, 0xc18e, 0x85ff, 0xc18e, 0x21, 0 - .dw 0x8640, 0xc18e, 0x867f, 0xc18e, 0x21, 0 - .dw 0x86c0, 0xc18e, 0x86ff, 0xc18e, 0x21, 0 - .dw 0x8740, 0xc18e, 0x877f, 0xc18e, 0x21, 0 - .dw 0x87c0, 0xc18e, 0x87ff, 0xc18e, 0x21, 0 - .dw 0x8840, 0xc18e, 0x887f, 0xc18e, 0x21, 0 - .dw 0x88c0, 0xc18e, 0x88ff, 0xc18e, 0x21, 0 - .dw 0x8940, 0xc18e, 0x897f, 0xc18e, 0x21, 0 - .dw 0x89c0, 0xc18e, 0x89ff, 0xc18e, 0x21, 0 - .dw 0x8a40, 0xc18e, 0x8a7f, 0xc18e, 0x21, 0 - .dw 0x8ac0, 0xc18e, 0x8aff, 0xc18e, 0x21, 0 - .dw 0x8b40, 0xc18e, 0x8b7f, 0xc18e, 0x21, 0 - .dw 0x8bc0, 0xc18e, 0x8bff, 0xc18e, 0x21, 0 - .dw 0x8c40, 0xc18e, 0x8c7f, 0xc18e, 0x21, 0 - .dw 0x8cc0, 0xc18e, 0x8cff, 0xc18e, 0x21, 0 - .dw 0x8d40, 0xc18e, 0x8d7f, 0xc18e, 0x21, 0 - .dw 0x8dc0, 0xc18e, 0x8dff, 0xc18e, 0x21, 0 - .dw 0x8e40, 0xc18e, 0x8e7f, 0xc18e, 0x21, 0 - .dw 0x8ec0, 0xc18e, 0x8eff, 0xc18e, 0x21, 0 - .dw 0x8f40, 0xc18e, 0x8f7f, 0xc18e, 0x21, 0 - .dw 0x8fc0, 0xc18e, 0x8fff, 0xc18e, 0x21, 0 - .dw 0x9040, 0xc18e, 0x907f, 0xc18e, 0x21, 0 - .dw 0x90c0, 0xc18e, 0x90ff, 0xc18e, 0x21, 0 - .dw 0x9140, 0xc18e, 0x917f, 0xc18e, 0x21, 0 - .dw 0x91c0, 0xc18e, 0x91ff, 0xc18e, 0x21, 0 - .dw 0x9240, 0xc18e, 0x927f, 0xc18e, 0x21, 0 - .dw 0x92c0, 0xc18e, 0x92ff, 0xc18e, 0x21, 0 - .dw 0x9340, 0xc18e, 0x937f, 0xc18e, 0x21, 0 - .dw 0x93c0, 0xc18e, 0x93ff, 0xc18e, 0x21, 0 - .dw 0x9440, 0xc18e, 0x947f, 0xc18e, 0x21, 0 - .dw 0x94c0, 0xc18e, 0x94ff, 0xc18e, 0x21, 0 - .dw 0x9540, 0xc18e, 0x957f, 0xc18e, 0x21, 0 - .dw 0x95c0, 0xc18e, 0x95ff, 0xc18e, 0x21, 0 - .dw 0x9640, 0xc18e, 0x967f, 0xc18e, 0x21, 0 - .dw 0x96c0, 0xc18e, 0x96ff, 0xc18e, 0x21, 0 - .dw 0x9740, 0xc18e, 0x977f, 0xc18e, 0x21, 0 - .dw 0x97c0, 0xc18e, 0x97ff, 0xc18e, 0x21, 0 - .dw 0x9840, 0xc18e, 0x987f, 0xc18e, 0x21, 0 - .dw 0x98c0, 0xc18e, 0x98ff, 0xc18e, 0x21, 0 - .dw 0x9940, 0xc18e, 0x997f, 0xc18e, 0x21, 0 - .dw 0x99c0, 0xc18e, 0x9fff, 0xc18e, 0x21, 0 - .dw 0xa040, 0xc18e, 0xa07f, 0xc18e, 0x21, 0 - .dw 0xa0c0, 0xc18e, 0xa0ff, 0xc18e, 0x21, 0 - .dw 0xa140, 0xc18e, 0xa17f, 0xc18e, 0x21, 0 - .dw 0xa1c0, 0xc18e, 0xa1ff, 0xc18e, 0x21, 0 - .dw 0xa240, 0xc18e, 0xa27f, 0xc18e, 0x21, 0 - .dw 0xa2c0, 0xc18e, 0xa2ff, 0xc18e, 0x21, 0 - .dw 0xa340, 0xc18e, 0xa37f, 0xc18e, 0x21, 0 - .dw 0xa3c0, 0xc18e, 0xa3ff, 0xc18e, 0x21, 0 - .dw 0xa440, 0xc18e, 0xa47f, 0xc18e, 0x21, 0 - .dw 0xa4c0, 0xc18e, 0xa4ff, 0xc18e, 0x21, 0 - .dw 0xa540, 0xc18e, 0xa57f, 0xc18e, 0x21, 0 - .dw 0xa5c0, 0xc18e, 0xa5ff, 0xc18e, 0x21, 0 - .dw 0xa640, 0xc18e, 0xa67f, 0xc18e, 0x21, 0 - .dw 0xa6c0, 0xc18e, 0xa6ff, 0xc18e, 0x21, 0 - .dw 0xa740, 0xc18e, 0xa77f, 0xc18e, 0x21, 0 - .dw 0xa7c0, 0xc18e, 0xa7ff, 0xc18e, 0x21, 0 - .dw 0xa840, 0xc18e, 0xa87f, 0xc18e, 0x21, 0 - .dw 0xa8c0, 0xc18e, 0xa8ff, 0xc18e, 0x21, 0 - .dw 0xa940, 0xc18e, 0xa97f, 0xc18e, 0x21, 0 - .dw 0xa9c0, 0xc18e, 0xa9ff, 0xc18e, 0x21, 0 - .dw 0xaa40, 0xc18e, 0xaa7f, 0xc18e, 0x21, 0 - .dw 0xaac0, 0xc18e, 0xaaff, 0xc18e, 0x21, 0 - .dw 0xab40, 0xc18e, 0xab7f, 0xc18e, 0x21, 0 - .dw 0xabc0, 0xc18e, 0xabff, 0xc18e, 0x21, 0 - .dw 0xac40, 0xc18e, 0xac7f, 0xc18e, 0x21, 0 - .dw 0xacc0, 0xc18e, 0xacff, 0xc18e, 0x21, 0 - .dw 0xad40, 0xc18e, 0xad7f, 0xc18e, 0x21, 0 - .dw 0xadc0, 0xc18e, 0xadff, 0xc18e, 0x21, 0 - .dw 0xae40, 0xc18e, 0xae7f, 0xc18e, 0x21, 0 - .dw 0xaec0, 0xc18e, 0xaeff, 0xc18e, 0x21, 0 - .dw 0xaf40, 0xc18e, 0xaf7f, 0xc18e, 0x21, 0 - .dw 0xafc0, 0xc18e, 0xafff, 0xc18e, 0x21, 0 - .dw 0xb040, 0xc18e, 0xb07f, 0xc18e, 0x21, 0 - .dw 0xb0c0, 0xc18e, 0xb0ff, 0xc18e, 0x21, 0 - .dw 0xb140, 0xc18e, 0xb17f, 0xc18e, 0x21, 0 - .dw 0xb1c0, 0xc18e, 0xb1ff, 0xc18e, 0x21, 0 - .dw 0xb240, 0xc18e, 0xb27f, 0xc18e, 0x21, 0 - .dw 0xb2c0, 0xc18e, 0xb2ff, 0xc18e, 0x21, 0 - .dw 0xb340, 0xc18e, 0xb37f, 0xc18e, 0x21, 0 - .dw 0xb3c0, 0xc18e, 0xb3ff, 0xc18e, 0x21, 0 - .dw 0xb440, 0xc18e, 0xb47f, 0xc18e, 0x21, 0 - .dw 0xb4c0, 0xc18e, 0xb4ff, 0xc18e, 0x21, 0 - .dw 0xb540, 0xc18e, 0xb57f, 0xc18e, 0x21, 0 - .dw 0xb5c0, 0xc18e, 0xb5ff, 0xc18e, 0x21, 0 - .dw 0xb640, 0xc18e, 0xb67f, 0xc18e, 0x21, 0 - .dw 0xb6c0, 0xc18e, 0xb6ff, 0xc18e, 0x21, 0 - .dw 0xb740, 0xc18e, 0xb77f, 0xc18e, 0x21, 0 - .dw 0xb7c0, 0xc18e, 0xb7ff, 0xc18e, 0x21, 0 - .dw 0xb840, 0xc18e, 0xb87f, 0xc18e, 0x21, 0 - .dw 0xb8c0, 0xc18e, 0xb8ff, 0xc18e, 0x21, 0 - .dw 0xb940, 0xc18e, 0xb97f, 0xc18e, 0x21, 0 - .dw 0xb9c0, 0xc18e, 0xbfff, 0xc18e, 0x21, 0 - .dw 0xc040, 0xc18e, 0xc07f, 0xc18e, 0x21, 0 - .dw 0xc0c0, 0xc18e, 0xc0ff, 0xc18e, 0x21, 0 - .dw 0xc140, 0xc18e, 0xc17f, 0xc18e, 0x21, 0 - .dw 0xc1c0, 0xc18e, 0xc1ff, 0xc18e, 0x21, 0 - .dw 0xc240, 0xc18e, 0xc27f, 0xc18e, 0x21, 0 - .dw 0xc2c0, 0xc18e, 0xc2ff, 0xc18e, 0x21, 0 - .dw 0xc340, 0xc18e, 0xc37f, 0xc18e, 0x21, 0 - .dw 0xc3c0, 0xc18e, 0xc3ff, 0xc18e, 0x21, 0 - .dw 0xc440, 0xc18e, 0xc47f, 0xc18e, 0x21, 0 - .dw 0xc4c0, 0xc18e, 0xc4ff, 0xc18e, 0x21, 0 - .dw 0xc540, 0xc18e, 0xc57f, 0xc18e, 0x21, 0 - .dw 0xc5c0, 0xc18e, 0xc5ff, 0xc18e, 0x21, 0 - .dw 0xc640, 0xc18e, 0xc67f, 0xc18e, 0x21, 0 - .dw 0xc6c0, 0xc18e, 0xc6ff, 0xc18e, 0x21, 0 - .dw 0xc740, 0xc18e, 0xc77f, 0xc18e, 0x21, 0 - .dw 0xc7c0, 0xc18e, 0xc7ff, 0xc18e, 0x21, 0 - .dw 0xc840, 0xc18e, 0xc87f, 0xc18e, 0x21, 0 - .dw 0xc8c0, 0xc18e, 0xc8ff, 0xc18e, 0x21, 0 - .dw 0xc940, 0xc18e, 0xc97f, 0xc18e, 0x21, 0 - .dw 0xc9c0, 0xc18e, 0xc9ff, 0xc18e, 0x21, 0 - .dw 0xca40, 0xc18e, 0xca7f, 0xc18e, 0x21, 0 - .dw 0xcac0, 0xc18e, 0xcaff, 0xc18e, 0x21, 0 - .dw 0xcb40, 0xc18e, 0xcb7f, 0xc18e, 0x21, 0 - .dw 0xcbc0, 0xc18e, 0xcbff, 0xc18e, 0x21, 0 - .dw 0xcc40, 0xc18e, 0xcc7f, 0xc18e, 0x21, 0 - .dw 0xccc0, 0xc18e, 0xccff, 0xc18e, 0x21, 0 - .dw 0xcd40, 0xc18e, 0xcd7f, 0xc18e, 0x21, 0 - .dw 0xcdc0, 0xc18e, 0xcdff, 0xc18e, 0x21, 0 - .dw 0xce40, 0xc18e, 0xce7f, 0xc18e, 0x21, 0 - .dw 0xcec0, 0xc18e, 0xceff, 0xc18e, 0x21, 0 - .dw 0xcf40, 0xc18e, 0xcf7f, 0xc18e, 0x21, 0 - .dw 0xcfc0, 0xc18e, 0xcfff, 0xc18e, 0x21, 0 - .dw 0xd040, 0xc18e, 0xd07f, 0xc18e, 0x21, 0 - .dw 0xd0c0, 0xc18e, 0xd0ff, 0xc18e, 0x21, 0 - .dw 0xd140, 0xc18e, 0xd17f, 0xc18e, 0x21, 0 - .dw 0xd1c0, 0xc18e, 0xd1ff, 0xc18e, 0x21, 0 - .dw 0xd240, 0xc18e, 0xd27f, 0xc18e, 0x21, 0 - .dw 0xd2c0, 0xc18e, 0xd2ff, 0xc18e, 0x21, 0 - .dw 0xd340, 0xc18e, 0xd37f, 0xc18e, 0x21, 0 - .dw 0xd3c0, 0xc18e, 0xd3ff, 0xc18e, 0x21, 0 - .dw 0xd440, 0xc18e, 0xd47f, 0xc18e, 0x21, 0 - .dw 0xd4c0, 0xc18e, 0xd4ff, 0xc18e, 0x21, 0 - .dw 0xd540, 0xc18e, 0xd57f, 0xc18e, 0x21, 0 - .dw 0xd5c0, 0xc18e, 0xd5ff, 0xc18e, 0x21, 0 - .dw 0xd640, 0xc18e, 0xd67f, 0xc18e, 0x21, 0 - .dw 0xd6c0, 0xc18e, 0xd6ff, 0xc18e, 0x21, 0 - .dw 0xd740, 0xc18e, 0xd77f, 0xc18e, 0x21, 0 - .dw 0xd7c0, 0xc18e, 0xd7ff, 0xc18e, 0x21, 0 - .dw 0xd840, 0xc18e, 0xd87f, 0xc18e, 0x21, 0 - .dw 0xd8c0, 0xc18e, 0xd8ff, 0xc18e, 0x21, 0 - .dw 0xd940, 0xc18e, 0xd97f, 0xc18e, 0x21, 0 - .dw 0xd9c0, 0xc18e, 0xdfff, 0xc18e, 0x21, 0 - .dw 0xe040, 0xc18e, 0xe07f, 0xc18e, 0x21, 0 - .dw 0xe0c0, 0xc18e, 0xe0ff, 0xc18e, 0x21, 0 - .dw 0xe140, 0xc18e, 0xe17f, 0xc18e, 0x21, 0 - .dw 0xe1c0, 0xc18e, 0xe1ff, 0xc18e, 0x21, 0 - .dw 0xe240, 0xc18e, 0xe27f, 0xc18e, 0x21, 0 - .dw 0xe2c0, 0xc18e, 0xe2ff, 0xc18e, 0x21, 0 - .dw 0xe340, 0xc18e, 0xe37f, 0xc18e, 0x21, 0 - .dw 0xe3c0, 0xc18e, 0xe3ff, 0xc18e, 0x21, 0 - .dw 0xe440, 0xc18e, 0xe47f, 0xc18e, 0x21, 0 - .dw 0xe4c0, 0xc18e, 0xe4ff, 0xc18e, 0x21, 0 - .dw 0xe540, 0xc18e, 0xe57f, 0xc18e, 0x21, 0 - .dw 0xe5c0, 0xc18e, 0xe5ff, 0xc18e, 0x21, 0 - .dw 0xe640, 0xc18e, 0xe67f, 0xc18e, 0x21, 0 - .dw 0xe6c0, 0xc18e, 0xe6ff, 0xc18e, 0x21, 0 - .dw 0xe740, 0xc18e, 0xe77f, 0xc18e, 0x21, 0 - .dw 0xe7c0, 0xc18e, 0xe7ff, 0xc18e, 0x21, 0 - .dw 0xe840, 0xc18e, 0xe87f, 0xc18e, 0x21, 0 - .dw 0xe8c0, 0xc18e, 0xe8ff, 0xc18e, 0x21, 0 - .dw 0xe940, 0xc18e, 0xe97f, 0xc18e, 0x21, 0 - .dw 0xe9c0, 0xc18e, 0xe9ff, 0xc18e, 0x21, 0 - .dw 0xea40, 0xc18e, 0xea7f, 0xc18e, 0x21, 0 - .dw 0xeac0, 0xc18e, 0xeaff, 0xc18e, 0x21, 0 - .dw 0xeb40, 0xc18e, 0xeb7f, 0xc18e, 0x21, 0 - .dw 0xebc0, 0xc18e, 0xebff, 0xc18e, 0x21, 0 - .dw 0xec40, 0xc18e, 0xec7f, 0xc18e, 0x21, 0 - .dw 0xecc0, 0xc18e, 0xecff, 0xc18e, 0x21, 0 - .dw 0xed40, 0xc18e, 0xed7f, 0xc18e, 0x21, 0 - .dw 0xedc0, 0xc18e, 0xedff, 0xc18e, 0x21, 0 - .dw 0xee40, 0xc18e, 0xee7f, 0xc18e, 0x21, 0 - .dw 0xeec0, 0xc18e, 0xeeff, 0xc18e, 0x21, 0 - .dw 0xef40, 0xc18e, 0xef7f, 0xc18e, 0x21, 0 - .dw 0xefc0, 0xc18e, 0xefff, 0xc18e, 0x21, 0 - .dw 0xf040, 0xc18e, 0xf07f, 0xc18e, 0x21, 0 - .dw 0xf0c0, 0xc18e, 0xf0ff, 0xc18e, 0x21, 0 - .dw 0xf140, 0xc18e, 0xf17f, 0xc18e, 0x21, 0 - .dw 0xf1c0, 0xc18e, 0xf1ff, 0xc18e, 0x21, 0 - .dw 0xf240, 0xc18e, 0xf27f, 0xc18e, 0x21, 0 - .dw 0xf2c0, 0xc18e, 0xf2ff, 0xc18e, 0x21, 0 - .dw 0xf340, 0xc18e, 0xf37f, 0xc18e, 0x21, 0 - .dw 0xf3c0, 0xc18e, 0xf3ff, 0xc18e, 0x21, 0 - .dw 0xf440, 0xc18e, 0xf47f, 0xc18e, 0x21, 0 - .dw 0xf4c0, 0xc18e, 0xf4ff, 0xc18e, 0x21, 0 - .dw 0xf540, 0xc18e, 0xf57f, 0xc18e, 0x21, 0 - .dw 0xf5c0, 0xc18e, 0xf5ff, 0xc18e, 0x21, 0 - .dw 0xf640, 0xc18e, 0xf67f, 0xc18e, 0x21, 0 - .dw 0xf6c0, 0xc18e, 0xf6ff, 0xc18e, 0x21, 0 - .dw 0xf740, 0xc18e, 0xf77f, 0xc18e, 0x21, 0 - .dw 0xf7c0, 0xc18e, 0xf7ff, 0xc18e, 0x21, 0 - .dw 0xf840, 0xc18e, 0xf87f, 0xc18e, 0x21, 0 - .dw 0xf8c0, 0xc18e, 0xf8ff, 0xc18e, 0x21, 0 - .dw 0xf940, 0xc18e, 0xf97f, 0xc18e, 0x21, 0 - .dw 0xf9c0, 0xc18e, 0xffff, 0xc18e, 0x21, 0 - .dw 0x0040, 0xc18f, 0x007f, 0xc18f, 0x21, 0 - .dw 0x00c0, 0xc18f, 0x00ff, 0xc18f, 0x21, 0 - .dw 0x0140, 0xc18f, 0x017f, 0xc18f, 0x21, 0 - .dw 0x01c0, 0xc18f, 0x01ff, 0xc18f, 0x21, 0 - .dw 0x0240, 0xc18f, 0x027f, 0xc18f, 0x21, 0 - .dw 0x02c0, 0xc18f, 0x02ff, 0xc18f, 0x21, 0 - .dw 0x0340, 0xc18f, 0x037f, 0xc18f, 0x21, 0 - .dw 0x03c0, 0xc18f, 0x03ff, 0xc18f, 0x21, 0 - .dw 0x0440, 0xc18f, 0x047f, 0xc18f, 0x21, 0 - .dw 0x04c0, 0xc18f, 0x04ff, 0xc18f, 0x21, 0 - .dw 0x0540, 0xc18f, 0x057f, 0xc18f, 0x21, 0 - .dw 0x05c0, 0xc18f, 0x05ff, 0xc18f, 0x21, 0 - .dw 0x0640, 0xc18f, 0x067f, 0xc18f, 0x21, 0 - .dw 0x06c0, 0xc18f, 0x06ff, 0xc18f, 0x21, 0 - .dw 0x0740, 0xc18f, 0x077f, 0xc18f, 0x21, 0 - .dw 0x07c0, 0xc18f, 0x07ff, 0xc18f, 0x21, 0 - .dw 0x0840, 0xc18f, 0x087f, 0xc18f, 0x21, 0 - .dw 0x08c0, 0xc18f, 0x08ff, 0xc18f, 0x21, 0 - .dw 0x0940, 0xc18f, 0x097f, 0xc18f, 0x21, 0 - .dw 0x09c0, 0xc18f, 0x09ff, 0xc18f, 0x21, 0 - .dw 0x0a40, 0xc18f, 0x0a7f, 0xc18f, 0x21, 0 - .dw 0x0ac0, 0xc18f, 0x0aff, 0xc18f, 0x21, 0 - .dw 0x0b40, 0xc18f, 0x0b7f, 0xc18f, 0x21, 0 - .dw 0x0bc0, 0xc18f, 0x0bff, 0xc18f, 0x21, 0 - .dw 0x0c40, 0xc18f, 0x0c7f, 0xc18f, 0x21, 0 - .dw 0x0cc0, 0xc18f, 0x0cff, 0xc18f, 0x21, 0 - .dw 0x0d40, 0xc18f, 0x0d7f, 0xc18f, 0x21, 0 - .dw 0x0dc0, 0xc18f, 0x0dff, 0xc18f, 0x21, 0 - .dw 0x0e40, 0xc18f, 0x0e7f, 0xc18f, 0x21, 0 - .dw 0x0ec0, 0xc18f, 0x0eff, 0xc18f, 0x21, 0 - .dw 0x0f40, 0xc18f, 0x0f7f, 0xc18f, 0x21, 0 - .dw 0x0fc0, 0xc18f, 0x0fff, 0xc18f, 0x21, 0 - .dw 0x1040, 0xc18f, 0x107f, 0xc18f, 0x21, 0 - .dw 0x10c0, 0xc18f, 0x10ff, 0xc18f, 0x21, 0 - .dw 0x1140, 0xc18f, 0x117f, 0xc18f, 0x21, 0 - .dw 0x11c0, 0xc18f, 0x11ff, 0xc18f, 0x21, 0 - .dw 0x1240, 0xc18f, 0x127f, 0xc18f, 0x21, 0 - .dw 0x12c0, 0xc18f, 0x12ff, 0xc18f, 0x21, 0 - .dw 0x1340, 0xc18f, 0x137f, 0xc18f, 0x21, 0 - .dw 0x13c0, 0xc18f, 0x13ff, 0xc18f, 0x21, 0 - .dw 0x1440, 0xc18f, 0x147f, 0xc18f, 0x21, 0 - .dw 0x14c0, 0xc18f, 0x14ff, 0xc18f, 0x21, 0 - .dw 0x1540, 0xc18f, 0x157f, 0xc18f, 0x21, 0 - .dw 0x15c0, 0xc18f, 0x15ff, 0xc18f, 0x21, 0 - .dw 0x1640, 0xc18f, 0x167f, 0xc18f, 0x21, 0 - .dw 0x16c0, 0xc18f, 0x16ff, 0xc18f, 0x21, 0 - .dw 0x1740, 0xc18f, 0x177f, 0xc18f, 0x21, 0 - .dw 0x17c0, 0xc18f, 0x17ff, 0xc18f, 0x21, 0 - .dw 0x1840, 0xc18f, 0x187f, 0xc18f, 0x21, 0 - .dw 0x18c0, 0xc18f, 0x18ff, 0xc18f, 0x21, 0 - .dw 0x1940, 0xc18f, 0x197f, 0xc18f, 0x21, 0 - .dw 0x19c0, 0xc18f, 0x1fff, 0xc18f, 0x21, 0 - .dw 0x2040, 0xc18f, 0x207f, 0xc18f, 0x21, 0 - .dw 0x20c0, 0xc18f, 0x20ff, 0xc18f, 0x21, 0 - .dw 0x2140, 0xc18f, 0x217f, 0xc18f, 0x21, 0 - .dw 0x21c0, 0xc18f, 0x21ff, 0xc18f, 0x21, 0 - .dw 0x2240, 0xc18f, 0x227f, 0xc18f, 0x21, 0 - .dw 0x22c0, 0xc18f, 0x22ff, 0xc18f, 0x21, 0 - .dw 0x2340, 0xc18f, 0x237f, 0xc18f, 0x21, 0 - .dw 0x23c0, 0xc18f, 0x23ff, 0xc18f, 0x21, 0 - .dw 0x2440, 0xc18f, 0x247f, 0xc18f, 0x21, 0 - .dw 0x24c0, 0xc18f, 0x24ff, 0xc18f, 0x21, 0 - .dw 0x2540, 0xc18f, 0x257f, 0xc18f, 0x21, 0 - .dw 0x25c0, 0xc18f, 0x25ff, 0xc18f, 0x21, 0 - .dw 0x2640, 0xc18f, 0x267f, 0xc18f, 0x21, 0 - .dw 0x26c0, 0xc18f, 0x26ff, 0xc18f, 0x21, 0 - .dw 0x2740, 0xc18f, 0x277f, 0xc18f, 0x21, 0 - .dw 0x27c0, 0xc18f, 0x27ff, 0xc18f, 0x21, 0 - .dw 0x2840, 0xc18f, 0x287f, 0xc18f, 0x21, 0 - .dw 0x28c0, 0xc18f, 0x28ff, 0xc18f, 0x21, 0 - .dw 0x2940, 0xc18f, 0x297f, 0xc18f, 0x21, 0 - .dw 0x29c0, 0xc18f, 0x29ff, 0xc18f, 0x21, 0 - .dw 0x2a40, 0xc18f, 0x2a7f, 0xc18f, 0x21, 0 - .dw 0x2ac0, 0xc18f, 0x2aff, 0xc18f, 0x21, 0 - .dw 0x2b40, 0xc18f, 0x2b7f, 0xc18f, 0x21, 0 - .dw 0x2bc0, 0xc18f, 0x2bff, 0xc18f, 0x21, 0 - .dw 0x2c40, 0xc18f, 0x2c7f, 0xc18f, 0x21, 0 - .dw 0x2cc0, 0xc18f, 0x2cff, 0xc18f, 0x21, 0 - .dw 0x2d40, 0xc18f, 0x2d7f, 0xc18f, 0x21, 0 - .dw 0x2dc0, 0xc18f, 0x2dff, 0xc18f, 0x21, 0 - .dw 0x2e40, 0xc18f, 0x2e7f, 0xc18f, 0x21, 0 - .dw 0x2ec0, 0xc18f, 0x2eff, 0xc18f, 0x21, 0 - .dw 0x2f40, 0xc18f, 0x2f7f, 0xc18f, 0x21, 0 - .dw 0x2fc0, 0xc18f, 0x2fff, 0xc18f, 0x21, 0 - .dw 0x3040, 0xc18f, 0x307f, 0xc18f, 0x21, 0 - .dw 0x30c0, 0xc18f, 0x30ff, 0xc18f, 0x21, 0 - .dw 0x3140, 0xc18f, 0x317f, 0xc18f, 0x21, 0 - .dw 0x31c0, 0xc18f, 0x31ff, 0xc18f, 0x21, 0 - .dw 0x3240, 0xc18f, 0x327f, 0xc18f, 0x21, 0 - .dw 0x32c0, 0xc18f, 0x32ff, 0xc18f, 0x21, 0 - .dw 0x3340, 0xc18f, 0x337f, 0xc18f, 0x21, 0 - .dw 0x33c0, 0xc18f, 0x33ff, 0xc18f, 0x21, 0 - .dw 0x3440, 0xc18f, 0x347f, 0xc18f, 0x21, 0 - .dw 0x34c0, 0xc18f, 0x34ff, 0xc18f, 0x21, 0 - .dw 0x3540, 0xc18f, 0x357f, 0xc18f, 0x21, 0 - .dw 0x35c0, 0xc18f, 0x35ff, 0xc18f, 0x21, 0 - .dw 0x3640, 0xc18f, 0x367f, 0xc18f, 0x21, 0 - .dw 0x36c0, 0xc18f, 0x36ff, 0xc18f, 0x21, 0 - .dw 0x3740, 0xc18f, 0x377f, 0xc18f, 0x21, 0 - .dw 0x37c0, 0xc18f, 0x37ff, 0xc18f, 0x21, 0 - .dw 0x3840, 0xc18f, 0x387f, 0xc18f, 0x21, 0 - .dw 0x38c0, 0xc18f, 0x38ff, 0xc18f, 0x21, 0 - .dw 0x3940, 0xc18f, 0x397f, 0xc18f, 0x21, 0 - .dw 0x39c0, 0xc18f, 0x1fff, 0xc190, 0x21, 0 - .dw 0x3a00, 0xc190, 0x5fff, 0xc190, 0x21, 0 - .dw 0x7a00, 0xc190, 0x9fff, 0xc190, 0x21, 0 - .dw 0xba00, 0xc190, 0xdfff, 0xc190, 0x21, 0 - .dw 0xfa00, 0xc190, 0x1fff, 0xc191, 0x21, 0 - .dw 0x3a00, 0xc191, 0x5fff, 0xc191, 0x21, 0 - .dw 0x7a00, 0xc191, 0x9fff, 0xc191, 0x21, 0 - .dw 0xba00, 0xc191, 0xdfff, 0xc191, 0x21, 0 - .dw 0xfa00, 0xc191, 0x1fff, 0xc192, 0x21, 0 - .dw 0x3a00, 0xc192, 0x5fff, 0xc192, 0x21, 0 - .dw 0x7a00, 0xc192, 0x9fff, 0xc192, 0x21, 0 - .dw 0xba00, 0xc192, 0xdfff, 0xc192, 0x21, 0 - .dw 0xfa00, 0xc192, 0xffff, 0xc193, 0x21, 0 - .dw 0x1a00, 0xc194, 0x1fff, 0xc194, 0x21, 0 - .dw 0x3a00, 0xc194, 0x3fff, 0xc194, 0x21, 0 - .dw 0x5a00, 0xc194, 0x5fff, 0xc194, 0x21, 0 - .dw 0x7a00, 0xc194, 0x7fff, 0xc194, 0x21, 0 - .dw 0x9a00, 0xc194, 0x9fff, 0xc194, 0x21, 0 - .dw 0xba00, 0xc194, 0xbfff, 0xc194, 0x21, 0 - .dw 0xda00, 0xc194, 0xdfff, 0xc194, 0x21, 0 - .dw 0xfa00, 0xc194, 0xffff, 0xc194, 0x21, 0 - .dw 0x1a00, 0xc195, 0x1fff, 0xc195, 0x21, 0 - .dw 0x3a00, 0xc195, 0x3fff, 0xc195, 0x21, 0 - .dw 0x5a00, 0xc195, 0x5fff, 0xc195, 0x21, 0 - .dw 0x7a00, 0xc195, 0x7fff, 0xc195, 0x21, 0 - .dw 0x9a00, 0xc195, 0x9fff, 0xc195, 0x21, 0 - .dw 0xba00, 0xc195, 0xbfff, 0xc195, 0x21, 0 - .dw 0xda00, 0xc195, 0xdfff, 0xc195, 0x21, 0 - .dw 0xfa00, 0xc195, 0xffff, 0xc195, 0x21, 0 - .dw 0x1a00, 0xc196, 0x1fff, 0xc196, 0x21, 0 - .dw 0x3a00, 0xc196, 0x3fff, 0xc196, 0x21, 0 - .dw 0x5a00, 0xc196, 0x5fff, 0xc196, 0x21, 0 - .dw 0x7a00, 0xc196, 0x7fff, 0xc196, 0x21, 0 - .dw 0x9a00, 0xc196, 0x9fff, 0xc196, 0x21, 0 - .dw 0xba00, 0xc196, 0xbfff, 0xc196, 0x21, 0 - .dw 0xda00, 0xc196, 0xdfff, 0xc196, 0x21, 0 - .dw 0xfa00, 0xc196, 0xffff, 0xc196, 0x21, 0 - .dw 0x1a00, 0xc197, 0x1fff, 0xc197, 0x21, 0 - .dw 0x3a00, 0xc197, 0x1fff, 0xc198, 0x21, 0 - .dw 0x2040, 0xc198, 0x207f, 0xc198, 0x21, 0 - .dw 0x20c0, 0xc198, 0x20ff, 0xc198, 0x21, 0 - .dw 0x2140, 0xc198, 0x217f, 0xc198, 0x21, 0 - .dw 0x21c0, 0xc198, 0x21ff, 0xc198, 0x21, 0 - .dw 0x2240, 0xc198, 0x227f, 0xc198, 0x21, 0 - .dw 0x22c0, 0xc198, 0x22ff, 0xc198, 0x21, 0 - .dw 0x2340, 0xc198, 0x237f, 0xc198, 0x21, 0 - .dw 0x23c0, 0xc198, 0x23ff, 0xc198, 0x21, 0 - .dw 0x2440, 0xc198, 0x247f, 0xc198, 0x21, 0 - .dw 0x24c0, 0xc198, 0x24ff, 0xc198, 0x21, 0 - .dw 0x2540, 0xc198, 0x257f, 0xc198, 0x21, 0 - .dw 0x25c0, 0xc198, 0x25ff, 0xc198, 0x21, 0 - .dw 0x2640, 0xc198, 0x267f, 0xc198, 0x21, 0 - .dw 0x26c0, 0xc198, 0x26ff, 0xc198, 0x21, 0 - .dw 0x2740, 0xc198, 0x277f, 0xc198, 0x21, 0 - .dw 0x27c0, 0xc198, 0x27ff, 0xc198, 0x21, 0 - .dw 0x2840, 0xc198, 0x287f, 0xc198, 0x21, 0 - .dw 0x28c0, 0xc198, 0x28ff, 0xc198, 0x21, 0 - .dw 0x2940, 0xc198, 0x297f, 0xc198, 0x21, 0 - .dw 0x29c0, 0xc198, 0x29ff, 0xc198, 0x21, 0 - .dw 0x2a40, 0xc198, 0x2a7f, 0xc198, 0x21, 0 - .dw 0x2ac0, 0xc198, 0x2aff, 0xc198, 0x21, 0 - .dw 0x2b40, 0xc198, 0x2b7f, 0xc198, 0x21, 0 - .dw 0x2bc0, 0xc198, 0x2bff, 0xc198, 0x21, 0 - .dw 0x2c40, 0xc198, 0x2c7f, 0xc198, 0x21, 0 - .dw 0x2cc0, 0xc198, 0x2cff, 0xc198, 0x21, 0 - .dw 0x2d40, 0xc198, 0x2d7f, 0xc198, 0x21, 0 - .dw 0x2dc0, 0xc198, 0x2dff, 0xc198, 0x21, 0 - .dw 0x2e40, 0xc198, 0x2e7f, 0xc198, 0x21, 0 - .dw 0x2ec0, 0xc198, 0x2eff, 0xc198, 0x21, 0 - .dw 0x2f40, 0xc198, 0x2f7f, 0xc198, 0x21, 0 - .dw 0x2fc0, 0xc198, 0x2fff, 0xc198, 0x21, 0 - .dw 0x3040, 0xc198, 0x307f, 0xc198, 0x21, 0 - .dw 0x30c0, 0xc198, 0x30ff, 0xc198, 0x21, 0 - .dw 0x3140, 0xc198, 0x317f, 0xc198, 0x21, 0 - .dw 0x31c0, 0xc198, 0x31ff, 0xc198, 0x21, 0 - .dw 0x3240, 0xc198, 0x327f, 0xc198, 0x21, 0 - .dw 0x32c0, 0xc198, 0x32ff, 0xc198, 0x21, 0 - .dw 0x3340, 0xc198, 0x337f, 0xc198, 0x21, 0 - .dw 0x33c0, 0xc198, 0x33ff, 0xc198, 0x21, 0 - .dw 0x3440, 0xc198, 0x347f, 0xc198, 0x21, 0 - .dw 0x34c0, 0xc198, 0x34ff, 0xc198, 0x21, 0 - .dw 0x3540, 0xc198, 0x357f, 0xc198, 0x21, 0 - .dw 0x35c0, 0xc198, 0x35ff, 0xc198, 0x21, 0 - .dw 0x3640, 0xc198, 0x367f, 0xc198, 0x21, 0 - .dw 0x36c0, 0xc198, 0x36ff, 0xc198, 0x21, 0 - .dw 0x3740, 0xc198, 0x377f, 0xc198, 0x21, 0 - .dw 0x37c0, 0xc198, 0x37ff, 0xc198, 0x21, 0 - .dw 0x3840, 0xc198, 0x387f, 0xc198, 0x21, 0 - .dw 0x38c0, 0xc198, 0x38ff, 0xc198, 0x21, 0 - .dw 0x3940, 0xc198, 0x397f, 0xc198, 0x21, 0 - .dw 0x39c0, 0xc198, 0x5fff, 0xc198, 0x21, 0 - .dw 0x6040, 0xc198, 0x607f, 0xc198, 0x21, 0 - .dw 0x60c0, 0xc198, 0x60ff, 0xc198, 0x21, 0 - .dw 0x6140, 0xc198, 0x617f, 0xc198, 0x21, 0 - .dw 0x61c0, 0xc198, 0x61ff, 0xc198, 0x21, 0 - .dw 0x6240, 0xc198, 0x627f, 0xc198, 0x21, 0 - .dw 0x62c0, 0xc198, 0x62ff, 0xc198, 0x21, 0 - .dw 0x6340, 0xc198, 0x637f, 0xc198, 0x21, 0 - .dw 0x63c0, 0xc198, 0x63ff, 0xc198, 0x21, 0 - .dw 0x6440, 0xc198, 0x647f, 0xc198, 0x21, 0 - .dw 0x64c0, 0xc198, 0x64ff, 0xc198, 0x21, 0 - .dw 0x6540, 0xc198, 0x657f, 0xc198, 0x21, 0 - .dw 0x65c0, 0xc198, 0x65ff, 0xc198, 0x21, 0 - .dw 0x6640, 0xc198, 0x667f, 0xc198, 0x21, 0 - .dw 0x66c0, 0xc198, 0x66ff, 0xc198, 0x21, 0 - .dw 0x6740, 0xc198, 0x677f, 0xc198, 0x21, 0 - .dw 0x67c0, 0xc198, 0x67ff, 0xc198, 0x21, 0 - .dw 0x6840, 0xc198, 0x687f, 0xc198, 0x21, 0 - .dw 0x68c0, 0xc198, 0x68ff, 0xc198, 0x21, 0 - .dw 0x6940, 0xc198, 0x697f, 0xc198, 0x21, 0 - .dw 0x69c0, 0xc198, 0x69ff, 0xc198, 0x21, 0 - .dw 0x6a40, 0xc198, 0x6a7f, 0xc198, 0x21, 0 - .dw 0x6ac0, 0xc198, 0x6aff, 0xc198, 0x21, 0 - .dw 0x6b40, 0xc198, 0x6b7f, 0xc198, 0x21, 0 - .dw 0x6bc0, 0xc198, 0x6bff, 0xc198, 0x21, 0 - .dw 0x6c40, 0xc198, 0x6c7f, 0xc198, 0x21, 0 - .dw 0x6cc0, 0xc198, 0x6cff, 0xc198, 0x21, 0 - .dw 0x6d40, 0xc198, 0x6d7f, 0xc198, 0x21, 0 - .dw 0x6dc0, 0xc198, 0x6dff, 0xc198, 0x21, 0 - .dw 0x6e40, 0xc198, 0x6e7f, 0xc198, 0x21, 0 - .dw 0x6ec0, 0xc198, 0x6eff, 0xc198, 0x21, 0 - .dw 0x6f40, 0xc198, 0x6f7f, 0xc198, 0x21, 0 - .dw 0x6fc0, 0xc198, 0x6fff, 0xc198, 0x21, 0 - .dw 0x7040, 0xc198, 0x707f, 0xc198, 0x21, 0 - .dw 0x70c0, 0xc198, 0x70ff, 0xc198, 0x21, 0 - .dw 0x7140, 0xc198, 0x717f, 0xc198, 0x21, 0 - .dw 0x71c0, 0xc198, 0x71ff, 0xc198, 0x21, 0 - .dw 0x7240, 0xc198, 0x727f, 0xc198, 0x21, 0 - .dw 0x72c0, 0xc198, 0x72ff, 0xc198, 0x21, 0 - .dw 0x7340, 0xc198, 0x737f, 0xc198, 0x21, 0 - .dw 0x73c0, 0xc198, 0x73ff, 0xc198, 0x21, 0 - .dw 0x7440, 0xc198, 0x747f, 0xc198, 0x21, 0 - .dw 0x74c0, 0xc198, 0x74ff, 0xc198, 0x21, 0 - .dw 0x7540, 0xc198, 0x757f, 0xc198, 0x21, 0 - .dw 0x75c0, 0xc198, 0x75ff, 0xc198, 0x21, 0 - .dw 0x7640, 0xc198, 0x767f, 0xc198, 0x21, 0 - .dw 0x76c0, 0xc198, 0x76ff, 0xc198, 0x21, 0 - .dw 0x7740, 0xc198, 0x777f, 0xc198, 0x21, 0 - .dw 0x77c0, 0xc198, 0x77ff, 0xc198, 0x21, 0 - .dw 0x7840, 0xc198, 0x787f, 0xc198, 0x21, 0 - .dw 0x78c0, 0xc198, 0x78ff, 0xc198, 0x21, 0 - .dw 0x7940, 0xc198, 0x797f, 0xc198, 0x21, 0 - .dw 0x79c0, 0xc198, 0x9fff, 0xc198, 0x21, 0 - .dw 0xa040, 0xc198, 0xa07f, 0xc198, 0x21, 0 - .dw 0xa0c0, 0xc198, 0xa0ff, 0xc198, 0x21, 0 - .dw 0xa140, 0xc198, 0xa17f, 0xc198, 0x21, 0 - .dw 0xa1c0, 0xc198, 0xa1ff, 0xc198, 0x21, 0 - .dw 0xa240, 0xc198, 0xa27f, 0xc198, 0x21, 0 - .dw 0xa2c0, 0xc198, 0xa2ff, 0xc198, 0x21, 0 - .dw 0xa340, 0xc198, 0xa37f, 0xc198, 0x21, 0 - .dw 0xa3c0, 0xc198, 0xa3ff, 0xc198, 0x21, 0 - .dw 0xa440, 0xc198, 0xa47f, 0xc198, 0x21, 0 - .dw 0xa4c0, 0xc198, 0xa4ff, 0xc198, 0x21, 0 - .dw 0xa540, 0xc198, 0xa57f, 0xc198, 0x21, 0 - .dw 0xa5c0, 0xc198, 0xa5ff, 0xc198, 0x21, 0 - .dw 0xa640, 0xc198, 0xa67f, 0xc198, 0x21, 0 - .dw 0xa6c0, 0xc198, 0xa6ff, 0xc198, 0x21, 0 - .dw 0xa740, 0xc198, 0xa77f, 0xc198, 0x21, 0 - .dw 0xa7c0, 0xc198, 0xa7ff, 0xc198, 0x21, 0 - .dw 0xa840, 0xc198, 0xa87f, 0xc198, 0x21, 0 - .dw 0xa8c0, 0xc198, 0xa8ff, 0xc198, 0x21, 0 - .dw 0xa940, 0xc198, 0xa97f, 0xc198, 0x21, 0 - .dw 0xa9c0, 0xc198, 0xa9ff, 0xc198, 0x21, 0 - .dw 0xaa40, 0xc198, 0xaa7f, 0xc198, 0x21, 0 - .dw 0xaac0, 0xc198, 0xaaff, 0xc198, 0x21, 0 - .dw 0xab40, 0xc198, 0xab7f, 0xc198, 0x21, 0 - .dw 0xabc0, 0xc198, 0xabff, 0xc198, 0x21, 0 - .dw 0xac40, 0xc198, 0xac7f, 0xc198, 0x21, 0 - .dw 0xacc0, 0xc198, 0xacff, 0xc198, 0x21, 0 - .dw 0xad40, 0xc198, 0xad7f, 0xc198, 0x21, 0 - .dw 0xadc0, 0xc198, 0xadff, 0xc198, 0x21, 0 - .dw 0xae40, 0xc198, 0xae7f, 0xc198, 0x21, 0 - .dw 0xaec0, 0xc198, 0xaeff, 0xc198, 0x21, 0 - .dw 0xaf40, 0xc198, 0xaf7f, 0xc198, 0x21, 0 - .dw 0xafc0, 0xc198, 0xafff, 0xc198, 0x21, 0 - .dw 0xb040, 0xc198, 0xb07f, 0xc198, 0x21, 0 - .dw 0xb0c0, 0xc198, 0xb0ff, 0xc198, 0x21, 0 - .dw 0xb140, 0xc198, 0xb17f, 0xc198, 0x21, 0 - .dw 0xb1c0, 0xc198, 0xb1ff, 0xc198, 0x21, 0 - .dw 0xb240, 0xc198, 0xb27f, 0xc198, 0x21, 0 - .dw 0xb2c0, 0xc198, 0xb2ff, 0xc198, 0x21, 0 - .dw 0xb340, 0xc198, 0xb37f, 0xc198, 0x21, 0 - .dw 0xb3c0, 0xc198, 0xb3ff, 0xc198, 0x21, 0 - .dw 0xb440, 0xc198, 0xb47f, 0xc198, 0x21, 0 - .dw 0xb4c0, 0xc198, 0xb4ff, 0xc198, 0x21, 0 - .dw 0xb540, 0xc198, 0xb57f, 0xc198, 0x21, 0 - .dw 0xb5c0, 0xc198, 0xb5ff, 0xc198, 0x21, 0 - .dw 0xb640, 0xc198, 0xb67f, 0xc198, 0x21, 0 - .dw 0xb6c0, 0xc198, 0xb6ff, 0xc198, 0x21, 0 - .dw 0xb740, 0xc198, 0xb77f, 0xc198, 0x21, 0 - .dw 0xb7c0, 0xc198, 0xb7ff, 0xc198, 0x21, 0 - .dw 0xb840, 0xc198, 0xb87f, 0xc198, 0x21, 0 - .dw 0xb8c0, 0xc198, 0xb8ff, 0xc198, 0x21, 0 - .dw 0xb940, 0xc198, 0xb97f, 0xc198, 0x21, 0 - .dw 0xb9c0, 0xc198, 0xdfff, 0xc198, 0x21, 0 - .dw 0xe040, 0xc198, 0xe07f, 0xc198, 0x21, 0 - .dw 0xe0c0, 0xc198, 0xe0ff, 0xc198, 0x21, 0 - .dw 0xe140, 0xc198, 0xe17f, 0xc198, 0x21, 0 - .dw 0xe1c0, 0xc198, 0xe1ff, 0xc198, 0x21, 0 - .dw 0xe240, 0xc198, 0xe27f, 0xc198, 0x21, 0 - .dw 0xe2c0, 0xc198, 0xe2ff, 0xc198, 0x21, 0 - .dw 0xe340, 0xc198, 0xe37f, 0xc198, 0x21, 0 - .dw 0xe3c0, 0xc198, 0xe3ff, 0xc198, 0x21, 0 - .dw 0xe440, 0xc198, 0xe47f, 0xc198, 0x21, 0 - .dw 0xe4c0, 0xc198, 0xe4ff, 0xc198, 0x21, 0 - .dw 0xe540, 0xc198, 0xe57f, 0xc198, 0x21, 0 - .dw 0xe5c0, 0xc198, 0xe5ff, 0xc198, 0x21, 0 - .dw 0xe640, 0xc198, 0xe67f, 0xc198, 0x21, 0 - .dw 0xe6c0, 0xc198, 0xe6ff, 0xc198, 0x21, 0 - .dw 0xe740, 0xc198, 0xe77f, 0xc198, 0x21, 0 - .dw 0xe7c0, 0xc198, 0xe7ff, 0xc198, 0x21, 0 - .dw 0xe840, 0xc198, 0xe87f, 0xc198, 0x21, 0 - .dw 0xe8c0, 0xc198, 0xe8ff, 0xc198, 0x21, 0 - .dw 0xe940, 0xc198, 0xe97f, 0xc198, 0x21, 0 - .dw 0xe9c0, 0xc198, 0xe9ff, 0xc198, 0x21, 0 - .dw 0xea40, 0xc198, 0xea7f, 0xc198, 0x21, 0 - .dw 0xeac0, 0xc198, 0xeaff, 0xc198, 0x21, 0 - .dw 0xeb40, 0xc198, 0xeb7f, 0xc198, 0x21, 0 - .dw 0xebc0, 0xc198, 0xebff, 0xc198, 0x21, 0 - .dw 0xec40, 0xc198, 0xec7f, 0xc198, 0x21, 0 - .dw 0xecc0, 0xc198, 0xecff, 0xc198, 0x21, 0 - .dw 0xed40, 0xc198, 0xed7f, 0xc198, 0x21, 0 - .dw 0xedc0, 0xc198, 0xedff, 0xc198, 0x21, 0 - .dw 0xee40, 0xc198, 0xee7f, 0xc198, 0x21, 0 - .dw 0xeec0, 0xc198, 0xeeff, 0xc198, 0x21, 0 - .dw 0xef40, 0xc198, 0xef7f, 0xc198, 0x21, 0 - .dw 0xefc0, 0xc198, 0xefff, 0xc198, 0x21, 0 - .dw 0xf040, 0xc198, 0xf07f, 0xc198, 0x21, 0 - .dw 0xf0c0, 0xc198, 0xf0ff, 0xc198, 0x21, 0 - .dw 0xf140, 0xc198, 0xf17f, 0xc198, 0x21, 0 - .dw 0xf1c0, 0xc198, 0xf1ff, 0xc198, 0x21, 0 - .dw 0xf240, 0xc198, 0xf27f, 0xc198, 0x21, 0 - .dw 0xf2c0, 0xc198, 0xf2ff, 0xc198, 0x21, 0 - .dw 0xf340, 0xc198, 0xf37f, 0xc198, 0x21, 0 - .dw 0xf3c0, 0xc198, 0xf3ff, 0xc198, 0x21, 0 - .dw 0xf440, 0xc198, 0xf47f, 0xc198, 0x21, 0 - .dw 0xf4c0, 0xc198, 0xf4ff, 0xc198, 0x21, 0 - .dw 0xf540, 0xc198, 0xf57f, 0xc198, 0x21, 0 - .dw 0xf5c0, 0xc198, 0xf5ff, 0xc198, 0x21, 0 - .dw 0xf640, 0xc198, 0xf67f, 0xc198, 0x21, 0 - .dw 0xf6c0, 0xc198, 0xf6ff, 0xc198, 0x21, 0 - .dw 0xf740, 0xc198, 0xf77f, 0xc198, 0x21, 0 - .dw 0xf7c0, 0xc198, 0xf7ff, 0xc198, 0x21, 0 - .dw 0xf840, 0xc198, 0xf87f, 0xc198, 0x21, 0 - .dw 0xf8c0, 0xc198, 0xf8ff, 0xc198, 0x21, 0 - .dw 0xf940, 0xc198, 0xf97f, 0xc198, 0x21, 0 - .dw 0xf9c0, 0xc198, 0x1fff, 0xc199, 0x21, 0 - .dw 0x2040, 0xc199, 0x207f, 0xc199, 0x21, 0 - .dw 0x20c0, 0xc199, 0x20ff, 0xc199, 0x21, 0 - .dw 0x2140, 0xc199, 0x217f, 0xc199, 0x21, 0 - .dw 0x21c0, 0xc199, 0x21ff, 0xc199, 0x21, 0 - .dw 0x2240, 0xc199, 0x227f, 0xc199, 0x21, 0 - .dw 0x22c0, 0xc199, 0x22ff, 0xc199, 0x21, 0 - .dw 0x2340, 0xc199, 0x237f, 0xc199, 0x21, 0 - .dw 0x23c0, 0xc199, 0x23ff, 0xc199, 0x21, 0 - .dw 0x2440, 0xc199, 0x247f, 0xc199, 0x21, 0 - .dw 0x24c0, 0xc199, 0x24ff, 0xc199, 0x21, 0 - .dw 0x2540, 0xc199, 0x257f, 0xc199, 0x21, 0 - .dw 0x25c0, 0xc199, 0x25ff, 0xc199, 0x21, 0 - .dw 0x2640, 0xc199, 0x267f, 0xc199, 0x21, 0 - .dw 0x26c0, 0xc199, 0x26ff, 0xc199, 0x21, 0 - .dw 0x2740, 0xc199, 0x277f, 0xc199, 0x21, 0 - .dw 0x27c0, 0xc199, 0x27ff, 0xc199, 0x21, 0 - .dw 0x2840, 0xc199, 0x287f, 0xc199, 0x21, 0 - .dw 0x28c0, 0xc199, 0x28ff, 0xc199, 0x21, 0 - .dw 0x2940, 0xc199, 0x297f, 0xc199, 0x21, 0 - .dw 0x29c0, 0xc199, 0x29ff, 0xc199, 0x21, 0 - .dw 0x2a40, 0xc199, 0x2a7f, 0xc199, 0x21, 0 - .dw 0x2ac0, 0xc199, 0x2aff, 0xc199, 0x21, 0 - .dw 0x2b40, 0xc199, 0x2b7f, 0xc199, 0x21, 0 - .dw 0x2bc0, 0xc199, 0x2bff, 0xc199, 0x21, 0 - .dw 0x2c40, 0xc199, 0x2c7f, 0xc199, 0x21, 0 - .dw 0x2cc0, 0xc199, 0x2cff, 0xc199, 0x21, 0 - .dw 0x2d40, 0xc199, 0x2d7f, 0xc199, 0x21, 0 - .dw 0x2dc0, 0xc199, 0x2dff, 0xc199, 0x21, 0 - .dw 0x2e40, 0xc199, 0x2e7f, 0xc199, 0x21, 0 - .dw 0x2ec0, 0xc199, 0x2eff, 0xc199, 0x21, 0 - .dw 0x2f40, 0xc199, 0x2f7f, 0xc199, 0x21, 0 - .dw 0x2fc0, 0xc199, 0x2fff, 0xc199, 0x21, 0 - .dw 0x3040, 0xc199, 0x307f, 0xc199, 0x21, 0 - .dw 0x30c0, 0xc199, 0x30ff, 0xc199, 0x21, 0 - .dw 0x3140, 0xc199, 0x317f, 0xc199, 0x21, 0 - .dw 0x31c0, 0xc199, 0x31ff, 0xc199, 0x21, 0 - .dw 0x3240, 0xc199, 0x327f, 0xc199, 0x21, 0 - .dw 0x32c0, 0xc199, 0x32ff, 0xc199, 0x21, 0 - .dw 0x3340, 0xc199, 0x337f, 0xc199, 0x21, 0 - .dw 0x33c0, 0xc199, 0x33ff, 0xc199, 0x21, 0 - .dw 0x3440, 0xc199, 0x347f, 0xc199, 0x21, 0 - .dw 0x34c0, 0xc199, 0x34ff, 0xc199, 0x21, 0 - .dw 0x3540, 0xc199, 0x357f, 0xc199, 0x21, 0 - .dw 0x35c0, 0xc199, 0x35ff, 0xc199, 0x21, 0 - .dw 0x3640, 0xc199, 0x367f, 0xc199, 0x21, 0 - .dw 0x36c0, 0xc199, 0x36ff, 0xc199, 0x21, 0 - .dw 0x3740, 0xc199, 0x377f, 0xc199, 0x21, 0 - .dw 0x37c0, 0xc199, 0x37ff, 0xc199, 0x21, 0 - .dw 0x3840, 0xc199, 0x387f, 0xc199, 0x21, 0 - .dw 0x38c0, 0xc199, 0x38ff, 0xc199, 0x21, 0 - .dw 0x3940, 0xc199, 0x397f, 0xc199, 0x21, 0 - .dw 0x39c0, 0xc199, 0x5fff, 0xc199, 0x21, 0 - .dw 0x6040, 0xc199, 0x607f, 0xc199, 0x21, 0 - .dw 0x60c0, 0xc199, 0x60ff, 0xc199, 0x21, 0 - .dw 0x6140, 0xc199, 0x617f, 0xc199, 0x21, 0 - .dw 0x61c0, 0xc199, 0x61ff, 0xc199, 0x21, 0 - .dw 0x6240, 0xc199, 0x627f, 0xc199, 0x21, 0 - .dw 0x62c0, 0xc199, 0x62ff, 0xc199, 0x21, 0 - .dw 0x6340, 0xc199, 0x637f, 0xc199, 0x21, 0 - .dw 0x63c0, 0xc199, 0x63ff, 0xc199, 0x21, 0 - .dw 0x6440, 0xc199, 0x647f, 0xc199, 0x21, 0 - .dw 0x64c0, 0xc199, 0x64ff, 0xc199, 0x21, 0 - .dw 0x6540, 0xc199, 0x657f, 0xc199, 0x21, 0 - .dw 0x65c0, 0xc199, 0x65ff, 0xc199, 0x21, 0 - .dw 0x6640, 0xc199, 0x667f, 0xc199, 0x21, 0 - .dw 0x66c0, 0xc199, 0x66ff, 0xc199, 0x21, 0 - .dw 0x6740, 0xc199, 0x677f, 0xc199, 0x21, 0 - .dw 0x67c0, 0xc199, 0x67ff, 0xc199, 0x21, 0 - .dw 0x6840, 0xc199, 0x687f, 0xc199, 0x21, 0 - .dw 0x68c0, 0xc199, 0x68ff, 0xc199, 0x21, 0 - .dw 0x6940, 0xc199, 0x697f, 0xc199, 0x21, 0 - .dw 0x69c0, 0xc199, 0x69ff, 0xc199, 0x21, 0 - .dw 0x6a40, 0xc199, 0x6a7f, 0xc199, 0x21, 0 - .dw 0x6ac0, 0xc199, 0x6aff, 0xc199, 0x21, 0 - .dw 0x6b40, 0xc199, 0x6b7f, 0xc199, 0x21, 0 - .dw 0x6bc0, 0xc199, 0x6bff, 0xc199, 0x21, 0 - .dw 0x6c40, 0xc199, 0x6c7f, 0xc199, 0x21, 0 - .dw 0x6cc0, 0xc199, 0x6cff, 0xc199, 0x21, 0 - .dw 0x6d40, 0xc199, 0x6d7f, 0xc199, 0x21, 0 - .dw 0x6dc0, 0xc199, 0x6dff, 0xc199, 0x21, 0 - .dw 0x6e40, 0xc199, 0x6e7f, 0xc199, 0x21, 0 - .dw 0x6ec0, 0xc199, 0x6eff, 0xc199, 0x21, 0 - .dw 0x6f40, 0xc199, 0x6f7f, 0xc199, 0x21, 0 - .dw 0x6fc0, 0xc199, 0x6fff, 0xc199, 0x21, 0 - .dw 0x7040, 0xc199, 0x707f, 0xc199, 0x21, 0 - .dw 0x70c0, 0xc199, 0x70ff, 0xc199, 0x21, 0 - .dw 0x7140, 0xc199, 0x717f, 0xc199, 0x21, 0 - .dw 0x71c0, 0xc199, 0x71ff, 0xc199, 0x21, 0 - .dw 0x7240, 0xc199, 0x727f, 0xc199, 0x21, 0 - .dw 0x72c0, 0xc199, 0x72ff, 0xc199, 0x21, 0 - .dw 0x7340, 0xc199, 0x737f, 0xc199, 0x21, 0 - .dw 0x73c0, 0xc199, 0x73ff, 0xc199, 0x21, 0 - .dw 0x7440, 0xc199, 0x747f, 0xc199, 0x21, 0 - .dw 0x74c0, 0xc199, 0x74ff, 0xc199, 0x21, 0 - .dw 0x7540, 0xc199, 0x757f, 0xc199, 0x21, 0 - .dw 0x75c0, 0xc199, 0x75ff, 0xc199, 0x21, 0 - .dw 0x7640, 0xc199, 0x767f, 0xc199, 0x21, 0 - .dw 0x76c0, 0xc199, 0x76ff, 0xc199, 0x21, 0 - .dw 0x7740, 0xc199, 0x777f, 0xc199, 0x21, 0 - .dw 0x77c0, 0xc199, 0x77ff, 0xc199, 0x21, 0 - .dw 0x7840, 0xc199, 0x787f, 0xc199, 0x21, 0 - .dw 0x78c0, 0xc199, 0x78ff, 0xc199, 0x21, 0 - .dw 0x7940, 0xc199, 0x797f, 0xc199, 0x21, 0 - .dw 0x79c0, 0xc199, 0x9fff, 0xc199, 0x21, 0 - .dw 0xa040, 0xc199, 0xa07f, 0xc199, 0x21, 0 - .dw 0xa0c0, 0xc199, 0xa0ff, 0xc199, 0x21, 0 - .dw 0xa140, 0xc199, 0xa17f, 0xc199, 0x21, 0 - .dw 0xa1c0, 0xc199, 0xa1ff, 0xc199, 0x21, 0 - .dw 0xa240, 0xc199, 0xa27f, 0xc199, 0x21, 0 - .dw 0xa2c0, 0xc199, 0xa2ff, 0xc199, 0x21, 0 - .dw 0xa340, 0xc199, 0xa37f, 0xc199, 0x21, 0 - .dw 0xa3c0, 0xc199, 0xa3ff, 0xc199, 0x21, 0 - .dw 0xa440, 0xc199, 0xa47f, 0xc199, 0x21, 0 - .dw 0xa4c0, 0xc199, 0xa4ff, 0xc199, 0x21, 0 - .dw 0xa540, 0xc199, 0xa57f, 0xc199, 0x21, 0 - .dw 0xa5c0, 0xc199, 0xa5ff, 0xc199, 0x21, 0 - .dw 0xa640, 0xc199, 0xa67f, 0xc199, 0x21, 0 - .dw 0xa6c0, 0xc199, 0xa6ff, 0xc199, 0x21, 0 - .dw 0xa740, 0xc199, 0xa77f, 0xc199, 0x21, 0 - .dw 0xa7c0, 0xc199, 0xa7ff, 0xc199, 0x21, 0 - .dw 0xa840, 0xc199, 0xa87f, 0xc199, 0x21, 0 - .dw 0xa8c0, 0xc199, 0xa8ff, 0xc199, 0x21, 0 - .dw 0xa940, 0xc199, 0xa97f, 0xc199, 0x21, 0 - .dw 0xa9c0, 0xc199, 0xa9ff, 0xc199, 0x21, 0 - .dw 0xaa40, 0xc199, 0xaa7f, 0xc199, 0x21, 0 - .dw 0xaac0, 0xc199, 0xaaff, 0xc199, 0x21, 0 - .dw 0xab40, 0xc199, 0xab7f, 0xc199, 0x21, 0 - .dw 0xabc0, 0xc199, 0xabff, 0xc199, 0x21, 0 - .dw 0xac40, 0xc199, 0xac7f, 0xc199, 0x21, 0 - .dw 0xacc0, 0xc199, 0xacff, 0xc199, 0x21, 0 - .dw 0xad40, 0xc199, 0xad7f, 0xc199, 0x21, 0 - .dw 0xadc0, 0xc199, 0xadff, 0xc199, 0x21, 0 - .dw 0xae40, 0xc199, 0xae7f, 0xc199, 0x21, 0 - .dw 0xaec0, 0xc199, 0xaeff, 0xc199, 0x21, 0 - .dw 0xaf40, 0xc199, 0xaf7f, 0xc199, 0x21, 0 - .dw 0xafc0, 0xc199, 0xafff, 0xc199, 0x21, 0 - .dw 0xb040, 0xc199, 0xb07f, 0xc199, 0x21, 0 - .dw 0xb0c0, 0xc199, 0xb0ff, 0xc199, 0x21, 0 - .dw 0xb140, 0xc199, 0xb17f, 0xc199, 0x21, 0 - .dw 0xb1c0, 0xc199, 0xb1ff, 0xc199, 0x21, 0 - .dw 0xb240, 0xc199, 0xb27f, 0xc199, 0x21, 0 - .dw 0xb2c0, 0xc199, 0xb2ff, 0xc199, 0x21, 0 - .dw 0xb340, 0xc199, 0xb37f, 0xc199, 0x21, 0 - .dw 0xb3c0, 0xc199, 0xb3ff, 0xc199, 0x21, 0 - .dw 0xb440, 0xc199, 0xb47f, 0xc199, 0x21, 0 - .dw 0xb4c0, 0xc199, 0xb4ff, 0xc199, 0x21, 0 - .dw 0xb540, 0xc199, 0xb57f, 0xc199, 0x21, 0 - .dw 0xb5c0, 0xc199, 0xb5ff, 0xc199, 0x21, 0 - .dw 0xb640, 0xc199, 0xb67f, 0xc199, 0x21, 0 - .dw 0xb6c0, 0xc199, 0xb6ff, 0xc199, 0x21, 0 - .dw 0xb740, 0xc199, 0xb77f, 0xc199, 0x21, 0 - .dw 0xb7c0, 0xc199, 0xb7ff, 0xc199, 0x21, 0 - .dw 0xb840, 0xc199, 0xb87f, 0xc199, 0x21, 0 - .dw 0xb8c0, 0xc199, 0xb8ff, 0xc199, 0x21, 0 - .dw 0xb940, 0xc199, 0xb97f, 0xc199, 0x21, 0 - .dw 0xb9c0, 0xc199, 0xdfff, 0xc199, 0x21, 0 - .dw 0xe040, 0xc199, 0xe07f, 0xc199, 0x21, 0 - .dw 0xe0c0, 0xc199, 0xe0ff, 0xc199, 0x21, 0 - .dw 0xe140, 0xc199, 0xe17f, 0xc199, 0x21, 0 - .dw 0xe1c0, 0xc199, 0xe1ff, 0xc199, 0x21, 0 - .dw 0xe240, 0xc199, 0xe27f, 0xc199, 0x21, 0 - .dw 0xe2c0, 0xc199, 0xe2ff, 0xc199, 0x21, 0 - .dw 0xe340, 0xc199, 0xe37f, 0xc199, 0x21, 0 - .dw 0xe3c0, 0xc199, 0xe3ff, 0xc199, 0x21, 0 - .dw 0xe440, 0xc199, 0xe47f, 0xc199, 0x21, 0 - .dw 0xe4c0, 0xc199, 0xe4ff, 0xc199, 0x21, 0 - .dw 0xe540, 0xc199, 0xe57f, 0xc199, 0x21, 0 - .dw 0xe5c0, 0xc199, 0xe5ff, 0xc199, 0x21, 0 - .dw 0xe640, 0xc199, 0xe67f, 0xc199, 0x21, 0 - .dw 0xe6c0, 0xc199, 0xe6ff, 0xc199, 0x21, 0 - .dw 0xe740, 0xc199, 0xe77f, 0xc199, 0x21, 0 - .dw 0xe7c0, 0xc199, 0xe7ff, 0xc199, 0x21, 0 - .dw 0xe840, 0xc199, 0xe87f, 0xc199, 0x21, 0 - .dw 0xe8c0, 0xc199, 0xe8ff, 0xc199, 0x21, 0 - .dw 0xe940, 0xc199, 0xe97f, 0xc199, 0x21, 0 - .dw 0xe9c0, 0xc199, 0xe9ff, 0xc199, 0x21, 0 - .dw 0xea40, 0xc199, 0xea7f, 0xc199, 0x21, 0 - .dw 0xeac0, 0xc199, 0xeaff, 0xc199, 0x21, 0 - .dw 0xeb40, 0xc199, 0xeb7f, 0xc199, 0x21, 0 - .dw 0xebc0, 0xc199, 0xebff, 0xc199, 0x21, 0 - .dw 0xec40, 0xc199, 0xec7f, 0xc199, 0x21, 0 - .dw 0xecc0, 0xc199, 0xecff, 0xc199, 0x21, 0 - .dw 0xed40, 0xc199, 0xed7f, 0xc199, 0x21, 0 - .dw 0xedc0, 0xc199, 0xedff, 0xc199, 0x21, 0 - .dw 0xee40, 0xc199, 0xee7f, 0xc199, 0x21, 0 - .dw 0xeec0, 0xc199, 0xeeff, 0xc199, 0x21, 0 - .dw 0xef40, 0xc199, 0xef7f, 0xc199, 0x21, 0 - .dw 0xefc0, 0xc199, 0xefff, 0xc199, 0x21, 0 - .dw 0xf040, 0xc199, 0xf07f, 0xc199, 0x21, 0 - .dw 0xf0c0, 0xc199, 0xf0ff, 0xc199, 0x21, 0 - .dw 0xf140, 0xc199, 0xf17f, 0xc199, 0x21, 0 - .dw 0xf1c0, 0xc199, 0xf1ff, 0xc199, 0x21, 0 - .dw 0xf240, 0xc199, 0xf27f, 0xc199, 0x21, 0 - .dw 0xf2c0, 0xc199, 0xf2ff, 0xc199, 0x21, 0 - .dw 0xf340, 0xc199, 0xf37f, 0xc199, 0x21, 0 - .dw 0xf3c0, 0xc199, 0xf3ff, 0xc199, 0x21, 0 - .dw 0xf440, 0xc199, 0xf47f, 0xc199, 0x21, 0 - .dw 0xf4c0, 0xc199, 0xf4ff, 0xc199, 0x21, 0 - .dw 0xf540, 0xc199, 0xf57f, 0xc199, 0x21, 0 - .dw 0xf5c0, 0xc199, 0xf5ff, 0xc199, 0x21, 0 - .dw 0xf640, 0xc199, 0xf67f, 0xc199, 0x21, 0 - .dw 0xf6c0, 0xc199, 0xf6ff, 0xc199, 0x21, 0 - .dw 0xf740, 0xc199, 0xf77f, 0xc199, 0x21, 0 - .dw 0xf7c0, 0xc199, 0xf7ff, 0xc199, 0x21, 0 - .dw 0xf840, 0xc199, 0xf87f, 0xc199, 0x21, 0 - .dw 0xf8c0, 0xc199, 0xf8ff, 0xc199, 0x21, 0 - .dw 0xf940, 0xc199, 0xf97f, 0xc199, 0x21, 0 - .dw 0xf9c0, 0xc199, 0x1fff, 0xc19a, 0x21, 0 - .dw 0x2040, 0xc19a, 0x207f, 0xc19a, 0x21, 0 - .dw 0x20c0, 0xc19a, 0x20ff, 0xc19a, 0x21, 0 - .dw 0x2140, 0xc19a, 0x217f, 0xc19a, 0x21, 0 - .dw 0x21c0, 0xc19a, 0x21ff, 0xc19a, 0x21, 0 - .dw 0x2240, 0xc19a, 0x227f, 0xc19a, 0x21, 0 - .dw 0x22c0, 0xc19a, 0x22ff, 0xc19a, 0x21, 0 - .dw 0x2340, 0xc19a, 0x237f, 0xc19a, 0x21, 0 - .dw 0x23c0, 0xc19a, 0x23ff, 0xc19a, 0x21, 0 - .dw 0x2440, 0xc19a, 0x247f, 0xc19a, 0x21, 0 - .dw 0x24c0, 0xc19a, 0x24ff, 0xc19a, 0x21, 0 - .dw 0x2540, 0xc19a, 0x257f, 0xc19a, 0x21, 0 - .dw 0x25c0, 0xc19a, 0x25ff, 0xc19a, 0x21, 0 - .dw 0x2640, 0xc19a, 0x267f, 0xc19a, 0x21, 0 - .dw 0x26c0, 0xc19a, 0x26ff, 0xc19a, 0x21, 0 - .dw 0x2740, 0xc19a, 0x277f, 0xc19a, 0x21, 0 - .dw 0x27c0, 0xc19a, 0x27ff, 0xc19a, 0x21, 0 - .dw 0x2840, 0xc19a, 0x287f, 0xc19a, 0x21, 0 - .dw 0x28c0, 0xc19a, 0x28ff, 0xc19a, 0x21, 0 - .dw 0x2940, 0xc19a, 0x297f, 0xc19a, 0x21, 0 - .dw 0x29c0, 0xc19a, 0x29ff, 0xc19a, 0x21, 0 - .dw 0x2a40, 0xc19a, 0x2a7f, 0xc19a, 0x21, 0 - .dw 0x2ac0, 0xc19a, 0x2aff, 0xc19a, 0x21, 0 - .dw 0x2b40, 0xc19a, 0x2b7f, 0xc19a, 0x21, 0 - .dw 0x2bc0, 0xc19a, 0x2bff, 0xc19a, 0x21, 0 - .dw 0x2c40, 0xc19a, 0x2c7f, 0xc19a, 0x21, 0 - .dw 0x2cc0, 0xc19a, 0x2cff, 0xc19a, 0x21, 0 - .dw 0x2d40, 0xc19a, 0x2d7f, 0xc19a, 0x21, 0 - .dw 0x2dc0, 0xc19a, 0x2dff, 0xc19a, 0x21, 0 - .dw 0x2e40, 0xc19a, 0x2e7f, 0xc19a, 0x21, 0 - .dw 0x2ec0, 0xc19a, 0x2eff, 0xc19a, 0x21, 0 - .dw 0x2f40, 0xc19a, 0x2f7f, 0xc19a, 0x21, 0 - .dw 0x2fc0, 0xc19a, 0x2fff, 0xc19a, 0x21, 0 - .dw 0x3040, 0xc19a, 0x307f, 0xc19a, 0x21, 0 - .dw 0x30c0, 0xc19a, 0x30ff, 0xc19a, 0x21, 0 - .dw 0x3140, 0xc19a, 0x317f, 0xc19a, 0x21, 0 - .dw 0x31c0, 0xc19a, 0x31ff, 0xc19a, 0x21, 0 - .dw 0x3240, 0xc19a, 0x327f, 0xc19a, 0x21, 0 - .dw 0x32c0, 0xc19a, 0x32ff, 0xc19a, 0x21, 0 - .dw 0x3340, 0xc19a, 0x337f, 0xc19a, 0x21, 0 - .dw 0x33c0, 0xc19a, 0x33ff, 0xc19a, 0x21, 0 - .dw 0x3440, 0xc19a, 0x347f, 0xc19a, 0x21, 0 - .dw 0x34c0, 0xc19a, 0x34ff, 0xc19a, 0x21, 0 - .dw 0x3540, 0xc19a, 0x357f, 0xc19a, 0x21, 0 - .dw 0x35c0, 0xc19a, 0x35ff, 0xc19a, 0x21, 0 - .dw 0x3640, 0xc19a, 0x367f, 0xc19a, 0x21, 0 - .dw 0x36c0, 0xc19a, 0x36ff, 0xc19a, 0x21, 0 - .dw 0x3740, 0xc19a, 0x377f, 0xc19a, 0x21, 0 - .dw 0x37c0, 0xc19a, 0x37ff, 0xc19a, 0x21, 0 - .dw 0x3840, 0xc19a, 0x387f, 0xc19a, 0x21, 0 - .dw 0x38c0, 0xc19a, 0x38ff, 0xc19a, 0x21, 0 - .dw 0x3940, 0xc19a, 0x397f, 0xc19a, 0x21, 0 - .dw 0x39c0, 0xc19a, 0x5fff, 0xc19a, 0x21, 0 - .dw 0x6040, 0xc19a, 0x607f, 0xc19a, 0x21, 0 - .dw 0x60c0, 0xc19a, 0x60ff, 0xc19a, 0x21, 0 - .dw 0x6140, 0xc19a, 0x617f, 0xc19a, 0x21, 0 - .dw 0x61c0, 0xc19a, 0x61ff, 0xc19a, 0x21, 0 - .dw 0x6240, 0xc19a, 0x627f, 0xc19a, 0x21, 0 - .dw 0x62c0, 0xc19a, 0x62ff, 0xc19a, 0x21, 0 - .dw 0x6340, 0xc19a, 0x637f, 0xc19a, 0x21, 0 - .dw 0x63c0, 0xc19a, 0x63ff, 0xc19a, 0x21, 0 - .dw 0x6440, 0xc19a, 0x647f, 0xc19a, 0x21, 0 - .dw 0x64c0, 0xc19a, 0x64ff, 0xc19a, 0x21, 0 - .dw 0x6540, 0xc19a, 0x657f, 0xc19a, 0x21, 0 - .dw 0x65c0, 0xc19a, 0x65ff, 0xc19a, 0x21, 0 - .dw 0x6640, 0xc19a, 0x667f, 0xc19a, 0x21, 0 - .dw 0x66c0, 0xc19a, 0x66ff, 0xc19a, 0x21, 0 - .dw 0x6740, 0xc19a, 0x677f, 0xc19a, 0x21, 0 - .dw 0x67c0, 0xc19a, 0x67ff, 0xc19a, 0x21, 0 - .dw 0x6840, 0xc19a, 0x687f, 0xc19a, 0x21, 0 - .dw 0x68c0, 0xc19a, 0x68ff, 0xc19a, 0x21, 0 - .dw 0x6940, 0xc19a, 0x697f, 0xc19a, 0x21, 0 - .dw 0x69c0, 0xc19a, 0x69ff, 0xc19a, 0x21, 0 - .dw 0x6a40, 0xc19a, 0x6a7f, 0xc19a, 0x21, 0 - .dw 0x6ac0, 0xc19a, 0x6aff, 0xc19a, 0x21, 0 - .dw 0x6b40, 0xc19a, 0x6b7f, 0xc19a, 0x21, 0 - .dw 0x6bc0, 0xc19a, 0x6bff, 0xc19a, 0x21, 0 - .dw 0x6c40, 0xc19a, 0x6c7f, 0xc19a, 0x21, 0 - .dw 0x6cc0, 0xc19a, 0x6cff, 0xc19a, 0x21, 0 - .dw 0x6d40, 0xc19a, 0x6d7f, 0xc19a, 0x21, 0 - .dw 0x6dc0, 0xc19a, 0x6dff, 0xc19a, 0x21, 0 - .dw 0x6e40, 0xc19a, 0x6e7f, 0xc19a, 0x21, 0 - .dw 0x6ec0, 0xc19a, 0x6eff, 0xc19a, 0x21, 0 - .dw 0x6f40, 0xc19a, 0x6f7f, 0xc19a, 0x21, 0 - .dw 0x6fc0, 0xc19a, 0x6fff, 0xc19a, 0x21, 0 - .dw 0x7040, 0xc19a, 0x707f, 0xc19a, 0x21, 0 - .dw 0x70c0, 0xc19a, 0x70ff, 0xc19a, 0x21, 0 - .dw 0x7140, 0xc19a, 0x717f, 0xc19a, 0x21, 0 - .dw 0x71c0, 0xc19a, 0x71ff, 0xc19a, 0x21, 0 - .dw 0x7240, 0xc19a, 0x727f, 0xc19a, 0x21, 0 - .dw 0x72c0, 0xc19a, 0x72ff, 0xc19a, 0x21, 0 - .dw 0x7340, 0xc19a, 0x737f, 0xc19a, 0x21, 0 - .dw 0x73c0, 0xc19a, 0x73ff, 0xc19a, 0x21, 0 - .dw 0x7440, 0xc19a, 0x747f, 0xc19a, 0x21, 0 - .dw 0x74c0, 0xc19a, 0x74ff, 0xc19a, 0x21, 0 - .dw 0x7540, 0xc19a, 0x757f, 0xc19a, 0x21, 0 - .dw 0x75c0, 0xc19a, 0x75ff, 0xc19a, 0x21, 0 - .dw 0x7640, 0xc19a, 0x767f, 0xc19a, 0x21, 0 - .dw 0x76c0, 0xc19a, 0x76ff, 0xc19a, 0x21, 0 - .dw 0x7740, 0xc19a, 0x777f, 0xc19a, 0x21, 0 - .dw 0x77c0, 0xc19a, 0x77ff, 0xc19a, 0x21, 0 - .dw 0x7840, 0xc19a, 0x787f, 0xc19a, 0x21, 0 - .dw 0x78c0, 0xc19a, 0x78ff, 0xc19a, 0x21, 0 - .dw 0x7940, 0xc19a, 0x797f, 0xc19a, 0x21, 0 - .dw 0x79c0, 0xc19a, 0x9fff, 0xc19a, 0x21, 0 - .dw 0xa040, 0xc19a, 0xa07f, 0xc19a, 0x21, 0 - .dw 0xa0c0, 0xc19a, 0xa0ff, 0xc19a, 0x21, 0 - .dw 0xa140, 0xc19a, 0xa17f, 0xc19a, 0x21, 0 - .dw 0xa1c0, 0xc19a, 0xa1ff, 0xc19a, 0x21, 0 - .dw 0xa240, 0xc19a, 0xa27f, 0xc19a, 0x21, 0 - .dw 0xa2c0, 0xc19a, 0xa2ff, 0xc19a, 0x21, 0 - .dw 0xa340, 0xc19a, 0xa37f, 0xc19a, 0x21, 0 - .dw 0xa3c0, 0xc19a, 0xa3ff, 0xc19a, 0x21, 0 - .dw 0xa440, 0xc19a, 0xa47f, 0xc19a, 0x21, 0 - .dw 0xa4c0, 0xc19a, 0xa4ff, 0xc19a, 0x21, 0 - .dw 0xa540, 0xc19a, 0xa57f, 0xc19a, 0x21, 0 - .dw 0xa5c0, 0xc19a, 0xa5ff, 0xc19a, 0x21, 0 - .dw 0xa640, 0xc19a, 0xa67f, 0xc19a, 0x21, 0 - .dw 0xa6c0, 0xc19a, 0xa6ff, 0xc19a, 0x21, 0 - .dw 0xa740, 0xc19a, 0xa77f, 0xc19a, 0x21, 0 - .dw 0xa7c0, 0xc19a, 0xa7ff, 0xc19a, 0x21, 0 - .dw 0xa840, 0xc19a, 0xa87f, 0xc19a, 0x21, 0 - .dw 0xa8c0, 0xc19a, 0xa8ff, 0xc19a, 0x21, 0 - .dw 0xa940, 0xc19a, 0xa97f, 0xc19a, 0x21, 0 - .dw 0xa9c0, 0xc19a, 0xa9ff, 0xc19a, 0x21, 0 - .dw 0xaa40, 0xc19a, 0xaa7f, 0xc19a, 0x21, 0 - .dw 0xaac0, 0xc19a, 0xaaff, 0xc19a, 0x21, 0 - .dw 0xab40, 0xc19a, 0xab7f, 0xc19a, 0x21, 0 - .dw 0xabc0, 0xc19a, 0xabff, 0xc19a, 0x21, 0 - .dw 0xac40, 0xc19a, 0xac7f, 0xc19a, 0x21, 0 - .dw 0xacc0, 0xc19a, 0xacff, 0xc19a, 0x21, 0 - .dw 0xad40, 0xc19a, 0xad7f, 0xc19a, 0x21, 0 - .dw 0xadc0, 0xc19a, 0xadff, 0xc19a, 0x21, 0 - .dw 0xae40, 0xc19a, 0xae7f, 0xc19a, 0x21, 0 - .dw 0xaec0, 0xc19a, 0xaeff, 0xc19a, 0x21, 0 - .dw 0xaf40, 0xc19a, 0xaf7f, 0xc19a, 0x21, 0 - .dw 0xafc0, 0xc19a, 0xafff, 0xc19a, 0x21, 0 - .dw 0xb040, 0xc19a, 0xb07f, 0xc19a, 0x21, 0 - .dw 0xb0c0, 0xc19a, 0xb0ff, 0xc19a, 0x21, 0 - .dw 0xb140, 0xc19a, 0xb17f, 0xc19a, 0x21, 0 - .dw 0xb1c0, 0xc19a, 0xb1ff, 0xc19a, 0x21, 0 - .dw 0xb240, 0xc19a, 0xb27f, 0xc19a, 0x21, 0 - .dw 0xb2c0, 0xc19a, 0xb2ff, 0xc19a, 0x21, 0 - .dw 0xb340, 0xc19a, 0xb37f, 0xc19a, 0x21, 0 - .dw 0xb3c0, 0xc19a, 0xb3ff, 0xc19a, 0x21, 0 - .dw 0xb440, 0xc19a, 0xb47f, 0xc19a, 0x21, 0 - .dw 0xb4c0, 0xc19a, 0xb4ff, 0xc19a, 0x21, 0 - .dw 0xb540, 0xc19a, 0xb57f, 0xc19a, 0x21, 0 - .dw 0xb5c0, 0xc19a, 0xb5ff, 0xc19a, 0x21, 0 - .dw 0xb640, 0xc19a, 0xb67f, 0xc19a, 0x21, 0 - .dw 0xb6c0, 0xc19a, 0xb6ff, 0xc19a, 0x21, 0 - .dw 0xb740, 0xc19a, 0xb77f, 0xc19a, 0x21, 0 - .dw 0xb7c0, 0xc19a, 0xb7ff, 0xc19a, 0x21, 0 - .dw 0xb840, 0xc19a, 0xb87f, 0xc19a, 0x21, 0 - .dw 0xb8c0, 0xc19a, 0xb8ff, 0xc19a, 0x21, 0 - .dw 0xb940, 0xc19a, 0xb97f, 0xc19a, 0x21, 0 - .dw 0xb9c0, 0xc19a, 0xdfff, 0xc19a, 0x21, 0 - .dw 0xe040, 0xc19a, 0xe07f, 0xc19a, 0x21, 0 - .dw 0xe0c0, 0xc19a, 0xe0ff, 0xc19a, 0x21, 0 - .dw 0xe140, 0xc19a, 0xe17f, 0xc19a, 0x21, 0 - .dw 0xe1c0, 0xc19a, 0xe1ff, 0xc19a, 0x21, 0 - .dw 0xe240, 0xc19a, 0xe27f, 0xc19a, 0x21, 0 - .dw 0xe2c0, 0xc19a, 0xe2ff, 0xc19a, 0x21, 0 - .dw 0xe340, 0xc19a, 0xe37f, 0xc19a, 0x21, 0 - .dw 0xe3c0, 0xc19a, 0xe3ff, 0xc19a, 0x21, 0 - .dw 0xe440, 0xc19a, 0xe47f, 0xc19a, 0x21, 0 - .dw 0xe4c0, 0xc19a, 0xe4ff, 0xc19a, 0x21, 0 - .dw 0xe540, 0xc19a, 0xe57f, 0xc19a, 0x21, 0 - .dw 0xe5c0, 0xc19a, 0xe5ff, 0xc19a, 0x21, 0 - .dw 0xe640, 0xc19a, 0xe67f, 0xc19a, 0x21, 0 - .dw 0xe6c0, 0xc19a, 0xe6ff, 0xc19a, 0x21, 0 - .dw 0xe740, 0xc19a, 0xe77f, 0xc19a, 0x21, 0 - .dw 0xe7c0, 0xc19a, 0xe7ff, 0xc19a, 0x21, 0 - .dw 0xe840, 0xc19a, 0xe87f, 0xc19a, 0x21, 0 - .dw 0xe8c0, 0xc19a, 0xe8ff, 0xc19a, 0x21, 0 - .dw 0xe940, 0xc19a, 0xe97f, 0xc19a, 0x21, 0 - .dw 0xe9c0, 0xc19a, 0xe9ff, 0xc19a, 0x21, 0 - .dw 0xea40, 0xc19a, 0xea7f, 0xc19a, 0x21, 0 - .dw 0xeac0, 0xc19a, 0xeaff, 0xc19a, 0x21, 0 - .dw 0xeb40, 0xc19a, 0xeb7f, 0xc19a, 0x21, 0 - .dw 0xebc0, 0xc19a, 0xebff, 0xc19a, 0x21, 0 - .dw 0xec40, 0xc19a, 0xec7f, 0xc19a, 0x21, 0 - .dw 0xecc0, 0xc19a, 0xecff, 0xc19a, 0x21, 0 - .dw 0xed40, 0xc19a, 0xed7f, 0xc19a, 0x21, 0 - .dw 0xedc0, 0xc19a, 0xedff, 0xc19a, 0x21, 0 - .dw 0xee40, 0xc19a, 0xee7f, 0xc19a, 0x21, 0 - .dw 0xeec0, 0xc19a, 0xeeff, 0xc19a, 0x21, 0 - .dw 0xef40, 0xc19a, 0xef7f, 0xc19a, 0x21, 0 - .dw 0xefc0, 0xc19a, 0xefff, 0xc19a, 0x21, 0 - .dw 0xf040, 0xc19a, 0xf07f, 0xc19a, 0x21, 0 - .dw 0xf0c0, 0xc19a, 0xf0ff, 0xc19a, 0x21, 0 - .dw 0xf140, 0xc19a, 0xf17f, 0xc19a, 0x21, 0 - .dw 0xf1c0, 0xc19a, 0xf1ff, 0xc19a, 0x21, 0 - .dw 0xf240, 0xc19a, 0xf27f, 0xc19a, 0x21, 0 - .dw 0xf2c0, 0xc19a, 0xf2ff, 0xc19a, 0x21, 0 - .dw 0xf340, 0xc19a, 0xf37f, 0xc19a, 0x21, 0 - .dw 0xf3c0, 0xc19a, 0xf3ff, 0xc19a, 0x21, 0 - .dw 0xf440, 0xc19a, 0xf47f, 0xc19a, 0x21, 0 - .dw 0xf4c0, 0xc19a, 0xf4ff, 0xc19a, 0x21, 0 - .dw 0xf540, 0xc19a, 0xf57f, 0xc19a, 0x21, 0 - .dw 0xf5c0, 0xc19a, 0xf5ff, 0xc19a, 0x21, 0 - .dw 0xf640, 0xc19a, 0xf67f, 0xc19a, 0x21, 0 - .dw 0xf6c0, 0xc19a, 0xf6ff, 0xc19a, 0x21, 0 - .dw 0xf740, 0xc19a, 0xf77f, 0xc19a, 0x21, 0 - .dw 0xf7c0, 0xc19a, 0xf7ff, 0xc19a, 0x21, 0 - .dw 0xf840, 0xc19a, 0xf87f, 0xc19a, 0x21, 0 - .dw 0xf8c0, 0xc19a, 0xf8ff, 0xc19a, 0x21, 0 - .dw 0xf940, 0xc19a, 0xf97f, 0xc19a, 0x21, 0 - .dw 0xf9c0, 0xc19a, 0xffff, 0xc19b, 0x21, 0 - .dw 0x0040, 0xc19c, 0x007f, 0xc19c, 0x21, 0 - .dw 0x00c0, 0xc19c, 0x00ff, 0xc19c, 0x21, 0 - .dw 0x0140, 0xc19c, 0x017f, 0xc19c, 0x21, 0 - .dw 0x01c0, 0xc19c, 0x01ff, 0xc19c, 0x21, 0 - .dw 0x0240, 0xc19c, 0x027f, 0xc19c, 0x21, 0 - .dw 0x02c0, 0xc19c, 0x02ff, 0xc19c, 0x21, 0 - .dw 0x0340, 0xc19c, 0x037f, 0xc19c, 0x21, 0 - .dw 0x03c0, 0xc19c, 0x03ff, 0xc19c, 0x21, 0 - .dw 0x0440, 0xc19c, 0x047f, 0xc19c, 0x21, 0 - .dw 0x04c0, 0xc19c, 0x04ff, 0xc19c, 0x21, 0 - .dw 0x0540, 0xc19c, 0x057f, 0xc19c, 0x21, 0 - .dw 0x05c0, 0xc19c, 0x05ff, 0xc19c, 0x21, 0 - .dw 0x0640, 0xc19c, 0x067f, 0xc19c, 0x21, 0 - .dw 0x06c0, 0xc19c, 0x06ff, 0xc19c, 0x21, 0 - .dw 0x0740, 0xc19c, 0x077f, 0xc19c, 0x21, 0 - .dw 0x07c0, 0xc19c, 0x07ff, 0xc19c, 0x21, 0 - .dw 0x0840, 0xc19c, 0x087f, 0xc19c, 0x21, 0 - .dw 0x08c0, 0xc19c, 0x08ff, 0xc19c, 0x21, 0 - .dw 0x0940, 0xc19c, 0x097f, 0xc19c, 0x21, 0 - .dw 0x09c0, 0xc19c, 0x09ff, 0xc19c, 0x21, 0 - .dw 0x0a40, 0xc19c, 0x0a7f, 0xc19c, 0x21, 0 - .dw 0x0ac0, 0xc19c, 0x0aff, 0xc19c, 0x21, 0 - .dw 0x0b40, 0xc19c, 0x0b7f, 0xc19c, 0x21, 0 - .dw 0x0bc0, 0xc19c, 0x0bff, 0xc19c, 0x21, 0 - .dw 0x0c40, 0xc19c, 0x0c7f, 0xc19c, 0x21, 0 - .dw 0x0cc0, 0xc19c, 0x0cff, 0xc19c, 0x21, 0 - .dw 0x0d40, 0xc19c, 0x0d7f, 0xc19c, 0x21, 0 - .dw 0x0dc0, 0xc19c, 0x0dff, 0xc19c, 0x21, 0 - .dw 0x0e40, 0xc19c, 0x0e7f, 0xc19c, 0x21, 0 - .dw 0x0ec0, 0xc19c, 0x0eff, 0xc19c, 0x21, 0 - .dw 0x0f40, 0xc19c, 0x0f7f, 0xc19c, 0x21, 0 - .dw 0x0fc0, 0xc19c, 0x0fff, 0xc19c, 0x21, 0 - .dw 0x1040, 0xc19c, 0x107f, 0xc19c, 0x21, 0 - .dw 0x10c0, 0xc19c, 0x10ff, 0xc19c, 0x21, 0 - .dw 0x1140, 0xc19c, 0x117f, 0xc19c, 0x21, 0 - .dw 0x11c0, 0xc19c, 0x11ff, 0xc19c, 0x21, 0 - .dw 0x1240, 0xc19c, 0x127f, 0xc19c, 0x21, 0 - .dw 0x12c0, 0xc19c, 0x12ff, 0xc19c, 0x21, 0 - .dw 0x1340, 0xc19c, 0x137f, 0xc19c, 0x21, 0 - .dw 0x13c0, 0xc19c, 0x13ff, 0xc19c, 0x21, 0 - .dw 0x1440, 0xc19c, 0x147f, 0xc19c, 0x21, 0 - .dw 0x14c0, 0xc19c, 0x14ff, 0xc19c, 0x21, 0 - .dw 0x1540, 0xc19c, 0x157f, 0xc19c, 0x21, 0 - .dw 0x15c0, 0xc19c, 0x15ff, 0xc19c, 0x21, 0 - .dw 0x1640, 0xc19c, 0x167f, 0xc19c, 0x21, 0 - .dw 0x16c0, 0xc19c, 0x16ff, 0xc19c, 0x21, 0 - .dw 0x1740, 0xc19c, 0x177f, 0xc19c, 0x21, 0 - .dw 0x17c0, 0xc19c, 0x17ff, 0xc19c, 0x21, 0 - .dw 0x1840, 0xc19c, 0x187f, 0xc19c, 0x21, 0 - .dw 0x18c0, 0xc19c, 0x18ff, 0xc19c, 0x21, 0 - .dw 0x1940, 0xc19c, 0x197f, 0xc19c, 0x21, 0 - .dw 0x19c0, 0xc19c, 0x1fff, 0xc19c, 0x21, 0 - .dw 0x2040, 0xc19c, 0x207f, 0xc19c, 0x21, 0 - .dw 0x20c0, 0xc19c, 0x20ff, 0xc19c, 0x21, 0 - .dw 0x2140, 0xc19c, 0x217f, 0xc19c, 0x21, 0 - .dw 0x21c0, 0xc19c, 0x21ff, 0xc19c, 0x21, 0 - .dw 0x2240, 0xc19c, 0x227f, 0xc19c, 0x21, 0 - .dw 0x22c0, 0xc19c, 0x22ff, 0xc19c, 0x21, 0 - .dw 0x2340, 0xc19c, 0x237f, 0xc19c, 0x21, 0 - .dw 0x23c0, 0xc19c, 0x23ff, 0xc19c, 0x21, 0 - .dw 0x2440, 0xc19c, 0x247f, 0xc19c, 0x21, 0 - .dw 0x24c0, 0xc19c, 0x24ff, 0xc19c, 0x21, 0 - .dw 0x2540, 0xc19c, 0x257f, 0xc19c, 0x21, 0 - .dw 0x25c0, 0xc19c, 0x25ff, 0xc19c, 0x21, 0 - .dw 0x2640, 0xc19c, 0x267f, 0xc19c, 0x21, 0 - .dw 0x26c0, 0xc19c, 0x26ff, 0xc19c, 0x21, 0 - .dw 0x2740, 0xc19c, 0x277f, 0xc19c, 0x21, 0 - .dw 0x27c0, 0xc19c, 0x27ff, 0xc19c, 0x21, 0 - .dw 0x2840, 0xc19c, 0x287f, 0xc19c, 0x21, 0 - .dw 0x28c0, 0xc19c, 0x28ff, 0xc19c, 0x21, 0 - .dw 0x2940, 0xc19c, 0x297f, 0xc19c, 0x21, 0 - .dw 0x29c0, 0xc19c, 0x29ff, 0xc19c, 0x21, 0 - .dw 0x2a40, 0xc19c, 0x2a7f, 0xc19c, 0x21, 0 - .dw 0x2ac0, 0xc19c, 0x2aff, 0xc19c, 0x21, 0 - .dw 0x2b40, 0xc19c, 0x2b7f, 0xc19c, 0x21, 0 - .dw 0x2bc0, 0xc19c, 0x2bff, 0xc19c, 0x21, 0 - .dw 0x2c40, 0xc19c, 0x2c7f, 0xc19c, 0x21, 0 - .dw 0x2cc0, 0xc19c, 0x2cff, 0xc19c, 0x21, 0 - .dw 0x2d40, 0xc19c, 0x2d7f, 0xc19c, 0x21, 0 - .dw 0x2dc0, 0xc19c, 0x2dff, 0xc19c, 0x21, 0 - .dw 0x2e40, 0xc19c, 0x2e7f, 0xc19c, 0x21, 0 - .dw 0x2ec0, 0xc19c, 0x2eff, 0xc19c, 0x21, 0 - .dw 0x2f40, 0xc19c, 0x2f7f, 0xc19c, 0x21, 0 - .dw 0x2fc0, 0xc19c, 0x2fff, 0xc19c, 0x21, 0 - .dw 0x3040, 0xc19c, 0x307f, 0xc19c, 0x21, 0 - .dw 0x30c0, 0xc19c, 0x30ff, 0xc19c, 0x21, 0 - .dw 0x3140, 0xc19c, 0x317f, 0xc19c, 0x21, 0 - .dw 0x31c0, 0xc19c, 0x31ff, 0xc19c, 0x21, 0 - .dw 0x3240, 0xc19c, 0x327f, 0xc19c, 0x21, 0 - .dw 0x32c0, 0xc19c, 0x32ff, 0xc19c, 0x21, 0 - .dw 0x3340, 0xc19c, 0x337f, 0xc19c, 0x21, 0 - .dw 0x33c0, 0xc19c, 0x33ff, 0xc19c, 0x21, 0 - .dw 0x3440, 0xc19c, 0x347f, 0xc19c, 0x21, 0 - .dw 0x34c0, 0xc19c, 0x34ff, 0xc19c, 0x21, 0 - .dw 0x3540, 0xc19c, 0x357f, 0xc19c, 0x21, 0 - .dw 0x35c0, 0xc19c, 0x35ff, 0xc19c, 0x21, 0 - .dw 0x3640, 0xc19c, 0x367f, 0xc19c, 0x21, 0 - .dw 0x36c0, 0xc19c, 0x36ff, 0xc19c, 0x21, 0 - .dw 0x3740, 0xc19c, 0x377f, 0xc19c, 0x21, 0 - .dw 0x37c0, 0xc19c, 0x37ff, 0xc19c, 0x21, 0 - .dw 0x3840, 0xc19c, 0x387f, 0xc19c, 0x21, 0 - .dw 0x38c0, 0xc19c, 0x38ff, 0xc19c, 0x21, 0 - .dw 0x3940, 0xc19c, 0x397f, 0xc19c, 0x21, 0 - .dw 0x39c0, 0xc19c, 0x3fff, 0xc19c, 0x21, 0 - .dw 0x4040, 0xc19c, 0x407f, 0xc19c, 0x21, 0 - .dw 0x40c0, 0xc19c, 0x40ff, 0xc19c, 0x21, 0 - .dw 0x4140, 0xc19c, 0x417f, 0xc19c, 0x21, 0 - .dw 0x41c0, 0xc19c, 0x41ff, 0xc19c, 0x21, 0 - .dw 0x4240, 0xc19c, 0x427f, 0xc19c, 0x21, 0 - .dw 0x42c0, 0xc19c, 0x42ff, 0xc19c, 0x21, 0 - .dw 0x4340, 0xc19c, 0x437f, 0xc19c, 0x21, 0 - .dw 0x43c0, 0xc19c, 0x43ff, 0xc19c, 0x21, 0 - .dw 0x4440, 0xc19c, 0x447f, 0xc19c, 0x21, 0 - .dw 0x44c0, 0xc19c, 0x44ff, 0xc19c, 0x21, 0 - .dw 0x4540, 0xc19c, 0x457f, 0xc19c, 0x21, 0 - .dw 0x45c0, 0xc19c, 0x45ff, 0xc19c, 0x21, 0 - .dw 0x4640, 0xc19c, 0x467f, 0xc19c, 0x21, 0 - .dw 0x46c0, 0xc19c, 0x46ff, 0xc19c, 0x21, 0 - .dw 0x4740, 0xc19c, 0x477f, 0xc19c, 0x21, 0 - .dw 0x47c0, 0xc19c, 0x47ff, 0xc19c, 0x21, 0 - .dw 0x4840, 0xc19c, 0x487f, 0xc19c, 0x21, 0 - .dw 0x48c0, 0xc19c, 0x48ff, 0xc19c, 0x21, 0 - .dw 0x4940, 0xc19c, 0x497f, 0xc19c, 0x21, 0 - .dw 0x49c0, 0xc19c, 0x49ff, 0xc19c, 0x21, 0 - .dw 0x4a40, 0xc19c, 0x4a7f, 0xc19c, 0x21, 0 - .dw 0x4ac0, 0xc19c, 0x4aff, 0xc19c, 0x21, 0 - .dw 0x4b40, 0xc19c, 0x4b7f, 0xc19c, 0x21, 0 - .dw 0x4bc0, 0xc19c, 0x4bff, 0xc19c, 0x21, 0 - .dw 0x4c40, 0xc19c, 0x4c7f, 0xc19c, 0x21, 0 - .dw 0x4cc0, 0xc19c, 0x4cff, 0xc19c, 0x21, 0 - .dw 0x4d40, 0xc19c, 0x4d7f, 0xc19c, 0x21, 0 - .dw 0x4dc0, 0xc19c, 0x4dff, 0xc19c, 0x21, 0 - .dw 0x4e40, 0xc19c, 0x4e7f, 0xc19c, 0x21, 0 - .dw 0x4ec0, 0xc19c, 0x4eff, 0xc19c, 0x21, 0 - .dw 0x4f40, 0xc19c, 0x4f7f, 0xc19c, 0x21, 0 - .dw 0x4fc0, 0xc19c, 0x4fff, 0xc19c, 0x21, 0 - .dw 0x5040, 0xc19c, 0x507f, 0xc19c, 0x21, 0 - .dw 0x50c0, 0xc19c, 0x50ff, 0xc19c, 0x21, 0 - .dw 0x5140, 0xc19c, 0x517f, 0xc19c, 0x21, 0 - .dw 0x51c0, 0xc19c, 0x51ff, 0xc19c, 0x21, 0 - .dw 0x5240, 0xc19c, 0x527f, 0xc19c, 0x21, 0 - .dw 0x52c0, 0xc19c, 0x52ff, 0xc19c, 0x21, 0 - .dw 0x5340, 0xc19c, 0x537f, 0xc19c, 0x21, 0 - .dw 0x53c0, 0xc19c, 0x53ff, 0xc19c, 0x21, 0 - .dw 0x5440, 0xc19c, 0x547f, 0xc19c, 0x21, 0 - .dw 0x54c0, 0xc19c, 0x54ff, 0xc19c, 0x21, 0 - .dw 0x5540, 0xc19c, 0x557f, 0xc19c, 0x21, 0 - .dw 0x55c0, 0xc19c, 0x55ff, 0xc19c, 0x21, 0 - .dw 0x5640, 0xc19c, 0x567f, 0xc19c, 0x21, 0 - .dw 0x56c0, 0xc19c, 0x56ff, 0xc19c, 0x21, 0 - .dw 0x5740, 0xc19c, 0x577f, 0xc19c, 0x21, 0 - .dw 0x57c0, 0xc19c, 0x57ff, 0xc19c, 0x21, 0 - .dw 0x5840, 0xc19c, 0x587f, 0xc19c, 0x21, 0 - .dw 0x58c0, 0xc19c, 0x58ff, 0xc19c, 0x21, 0 - .dw 0x5940, 0xc19c, 0x597f, 0xc19c, 0x21, 0 - .dw 0x59c0, 0xc19c, 0x5fff, 0xc19c, 0x21, 0 - .dw 0x6040, 0xc19c, 0x607f, 0xc19c, 0x21, 0 - .dw 0x60c0, 0xc19c, 0x60ff, 0xc19c, 0x21, 0 - .dw 0x6140, 0xc19c, 0x617f, 0xc19c, 0x21, 0 - .dw 0x61c0, 0xc19c, 0x61ff, 0xc19c, 0x21, 0 - .dw 0x6240, 0xc19c, 0x627f, 0xc19c, 0x21, 0 - .dw 0x62c0, 0xc19c, 0x62ff, 0xc19c, 0x21, 0 - .dw 0x6340, 0xc19c, 0x637f, 0xc19c, 0x21, 0 - .dw 0x63c0, 0xc19c, 0x63ff, 0xc19c, 0x21, 0 - .dw 0x6440, 0xc19c, 0x647f, 0xc19c, 0x21, 0 - .dw 0x64c0, 0xc19c, 0x64ff, 0xc19c, 0x21, 0 - .dw 0x6540, 0xc19c, 0x657f, 0xc19c, 0x21, 0 - .dw 0x65c0, 0xc19c, 0x65ff, 0xc19c, 0x21, 0 - .dw 0x6640, 0xc19c, 0x667f, 0xc19c, 0x21, 0 - .dw 0x66c0, 0xc19c, 0x66ff, 0xc19c, 0x21, 0 - .dw 0x6740, 0xc19c, 0x677f, 0xc19c, 0x21, 0 - .dw 0x67c0, 0xc19c, 0x67ff, 0xc19c, 0x21, 0 - .dw 0x6840, 0xc19c, 0x687f, 0xc19c, 0x21, 0 - .dw 0x68c0, 0xc19c, 0x68ff, 0xc19c, 0x21, 0 - .dw 0x6940, 0xc19c, 0x697f, 0xc19c, 0x21, 0 - .dw 0x69c0, 0xc19c, 0x69ff, 0xc19c, 0x21, 0 - .dw 0x6a40, 0xc19c, 0x6a7f, 0xc19c, 0x21, 0 - .dw 0x6ac0, 0xc19c, 0x6aff, 0xc19c, 0x21, 0 - .dw 0x6b40, 0xc19c, 0x6b7f, 0xc19c, 0x21, 0 - .dw 0x6bc0, 0xc19c, 0x6bff, 0xc19c, 0x21, 0 - .dw 0x6c40, 0xc19c, 0x6c7f, 0xc19c, 0x21, 0 - .dw 0x6cc0, 0xc19c, 0x6cff, 0xc19c, 0x21, 0 - .dw 0x6d40, 0xc19c, 0x6d7f, 0xc19c, 0x21, 0 - .dw 0x6dc0, 0xc19c, 0x6dff, 0xc19c, 0x21, 0 - .dw 0x6e40, 0xc19c, 0x6e7f, 0xc19c, 0x21, 0 - .dw 0x6ec0, 0xc19c, 0x6eff, 0xc19c, 0x21, 0 - .dw 0x6f40, 0xc19c, 0x6f7f, 0xc19c, 0x21, 0 - .dw 0x6fc0, 0xc19c, 0x6fff, 0xc19c, 0x21, 0 - .dw 0x7040, 0xc19c, 0x707f, 0xc19c, 0x21, 0 - .dw 0x70c0, 0xc19c, 0x70ff, 0xc19c, 0x21, 0 - .dw 0x7140, 0xc19c, 0x717f, 0xc19c, 0x21, 0 - .dw 0x71c0, 0xc19c, 0x71ff, 0xc19c, 0x21, 0 - .dw 0x7240, 0xc19c, 0x727f, 0xc19c, 0x21, 0 - .dw 0x72c0, 0xc19c, 0x72ff, 0xc19c, 0x21, 0 - .dw 0x7340, 0xc19c, 0x737f, 0xc19c, 0x21, 0 - .dw 0x73c0, 0xc19c, 0x73ff, 0xc19c, 0x21, 0 - .dw 0x7440, 0xc19c, 0x747f, 0xc19c, 0x21, 0 - .dw 0x74c0, 0xc19c, 0x74ff, 0xc19c, 0x21, 0 - .dw 0x7540, 0xc19c, 0x757f, 0xc19c, 0x21, 0 - .dw 0x75c0, 0xc19c, 0x75ff, 0xc19c, 0x21, 0 - .dw 0x7640, 0xc19c, 0x767f, 0xc19c, 0x21, 0 - .dw 0x76c0, 0xc19c, 0x76ff, 0xc19c, 0x21, 0 - .dw 0x7740, 0xc19c, 0x777f, 0xc19c, 0x21, 0 - .dw 0x77c0, 0xc19c, 0x77ff, 0xc19c, 0x21, 0 - .dw 0x7840, 0xc19c, 0x787f, 0xc19c, 0x21, 0 - .dw 0x78c0, 0xc19c, 0x78ff, 0xc19c, 0x21, 0 - .dw 0x7940, 0xc19c, 0x797f, 0xc19c, 0x21, 0 - .dw 0x79c0, 0xc19c, 0x7fff, 0xc19c, 0x21, 0 - .dw 0x8040, 0xc19c, 0x807f, 0xc19c, 0x21, 0 - .dw 0x80c0, 0xc19c, 0x80ff, 0xc19c, 0x21, 0 - .dw 0x8140, 0xc19c, 0x817f, 0xc19c, 0x21, 0 - .dw 0x81c0, 0xc19c, 0x81ff, 0xc19c, 0x21, 0 - .dw 0x8240, 0xc19c, 0x827f, 0xc19c, 0x21, 0 - .dw 0x82c0, 0xc19c, 0x82ff, 0xc19c, 0x21, 0 - .dw 0x8340, 0xc19c, 0x837f, 0xc19c, 0x21, 0 - .dw 0x83c0, 0xc19c, 0x83ff, 0xc19c, 0x21, 0 - .dw 0x8440, 0xc19c, 0x847f, 0xc19c, 0x21, 0 - .dw 0x84c0, 0xc19c, 0x84ff, 0xc19c, 0x21, 0 - .dw 0x8540, 0xc19c, 0x857f, 0xc19c, 0x21, 0 - .dw 0x85c0, 0xc19c, 0x85ff, 0xc19c, 0x21, 0 - .dw 0x8640, 0xc19c, 0x867f, 0xc19c, 0x21, 0 - .dw 0x86c0, 0xc19c, 0x86ff, 0xc19c, 0x21, 0 - .dw 0x8740, 0xc19c, 0x877f, 0xc19c, 0x21, 0 - .dw 0x87c0, 0xc19c, 0x87ff, 0xc19c, 0x21, 0 - .dw 0x8840, 0xc19c, 0x887f, 0xc19c, 0x21, 0 - .dw 0x88c0, 0xc19c, 0x88ff, 0xc19c, 0x21, 0 - .dw 0x8940, 0xc19c, 0x897f, 0xc19c, 0x21, 0 - .dw 0x89c0, 0xc19c, 0x89ff, 0xc19c, 0x21, 0 - .dw 0x8a40, 0xc19c, 0x8a7f, 0xc19c, 0x21, 0 - .dw 0x8ac0, 0xc19c, 0x8aff, 0xc19c, 0x21, 0 - .dw 0x8b40, 0xc19c, 0x8b7f, 0xc19c, 0x21, 0 - .dw 0x8bc0, 0xc19c, 0x8bff, 0xc19c, 0x21, 0 - .dw 0x8c40, 0xc19c, 0x8c7f, 0xc19c, 0x21, 0 - .dw 0x8cc0, 0xc19c, 0x8cff, 0xc19c, 0x21, 0 - .dw 0x8d40, 0xc19c, 0x8d7f, 0xc19c, 0x21, 0 - .dw 0x8dc0, 0xc19c, 0x8dff, 0xc19c, 0x21, 0 - .dw 0x8e40, 0xc19c, 0x8e7f, 0xc19c, 0x21, 0 - .dw 0x8ec0, 0xc19c, 0x8eff, 0xc19c, 0x21, 0 - .dw 0x8f40, 0xc19c, 0x8f7f, 0xc19c, 0x21, 0 - .dw 0x8fc0, 0xc19c, 0x8fff, 0xc19c, 0x21, 0 - .dw 0x9040, 0xc19c, 0x907f, 0xc19c, 0x21, 0 - .dw 0x90c0, 0xc19c, 0x90ff, 0xc19c, 0x21, 0 - .dw 0x9140, 0xc19c, 0x917f, 0xc19c, 0x21, 0 - .dw 0x91c0, 0xc19c, 0x91ff, 0xc19c, 0x21, 0 - .dw 0x9240, 0xc19c, 0x927f, 0xc19c, 0x21, 0 - .dw 0x92c0, 0xc19c, 0x92ff, 0xc19c, 0x21, 0 - .dw 0x9340, 0xc19c, 0x937f, 0xc19c, 0x21, 0 - .dw 0x93c0, 0xc19c, 0x93ff, 0xc19c, 0x21, 0 - .dw 0x9440, 0xc19c, 0x947f, 0xc19c, 0x21, 0 - .dw 0x94c0, 0xc19c, 0x94ff, 0xc19c, 0x21, 0 - .dw 0x9540, 0xc19c, 0x957f, 0xc19c, 0x21, 0 - .dw 0x95c0, 0xc19c, 0x95ff, 0xc19c, 0x21, 0 - .dw 0x9640, 0xc19c, 0x967f, 0xc19c, 0x21, 0 - .dw 0x96c0, 0xc19c, 0x96ff, 0xc19c, 0x21, 0 - .dw 0x9740, 0xc19c, 0x977f, 0xc19c, 0x21, 0 - .dw 0x97c0, 0xc19c, 0x97ff, 0xc19c, 0x21, 0 - .dw 0x9840, 0xc19c, 0x987f, 0xc19c, 0x21, 0 - .dw 0x98c0, 0xc19c, 0x98ff, 0xc19c, 0x21, 0 - .dw 0x9940, 0xc19c, 0x997f, 0xc19c, 0x21, 0 - .dw 0x99c0, 0xc19c, 0x9fff, 0xc19c, 0x21, 0 - .dw 0xa040, 0xc19c, 0xa07f, 0xc19c, 0x21, 0 - .dw 0xa0c0, 0xc19c, 0xa0ff, 0xc19c, 0x21, 0 - .dw 0xa140, 0xc19c, 0xa17f, 0xc19c, 0x21, 0 - .dw 0xa1c0, 0xc19c, 0xa1ff, 0xc19c, 0x21, 0 - .dw 0xa240, 0xc19c, 0xa27f, 0xc19c, 0x21, 0 - .dw 0xa2c0, 0xc19c, 0xa2ff, 0xc19c, 0x21, 0 - .dw 0xa340, 0xc19c, 0xa37f, 0xc19c, 0x21, 0 - .dw 0xa3c0, 0xc19c, 0xa3ff, 0xc19c, 0x21, 0 - .dw 0xa440, 0xc19c, 0xa47f, 0xc19c, 0x21, 0 - .dw 0xa4c0, 0xc19c, 0xa4ff, 0xc19c, 0x21, 0 - .dw 0xa540, 0xc19c, 0xa57f, 0xc19c, 0x21, 0 - .dw 0xa5c0, 0xc19c, 0xa5ff, 0xc19c, 0x21, 0 - .dw 0xa640, 0xc19c, 0xa67f, 0xc19c, 0x21, 0 - .dw 0xa6c0, 0xc19c, 0xa6ff, 0xc19c, 0x21, 0 - .dw 0xa740, 0xc19c, 0xa77f, 0xc19c, 0x21, 0 - .dw 0xa7c0, 0xc19c, 0xa7ff, 0xc19c, 0x21, 0 - .dw 0xa840, 0xc19c, 0xa87f, 0xc19c, 0x21, 0 - .dw 0xa8c0, 0xc19c, 0xa8ff, 0xc19c, 0x21, 0 - .dw 0xa940, 0xc19c, 0xa97f, 0xc19c, 0x21, 0 - .dw 0xa9c0, 0xc19c, 0xa9ff, 0xc19c, 0x21, 0 - .dw 0xaa40, 0xc19c, 0xaa7f, 0xc19c, 0x21, 0 - .dw 0xaac0, 0xc19c, 0xaaff, 0xc19c, 0x21, 0 - .dw 0xab40, 0xc19c, 0xab7f, 0xc19c, 0x21, 0 - .dw 0xabc0, 0xc19c, 0xabff, 0xc19c, 0x21, 0 - .dw 0xac40, 0xc19c, 0xac7f, 0xc19c, 0x21, 0 - .dw 0xacc0, 0xc19c, 0xacff, 0xc19c, 0x21, 0 - .dw 0xad40, 0xc19c, 0xad7f, 0xc19c, 0x21, 0 - .dw 0xadc0, 0xc19c, 0xadff, 0xc19c, 0x21, 0 - .dw 0xae40, 0xc19c, 0xae7f, 0xc19c, 0x21, 0 - .dw 0xaec0, 0xc19c, 0xaeff, 0xc19c, 0x21, 0 - .dw 0xaf40, 0xc19c, 0xaf7f, 0xc19c, 0x21, 0 - .dw 0xafc0, 0xc19c, 0xafff, 0xc19c, 0x21, 0 - .dw 0xb040, 0xc19c, 0xb07f, 0xc19c, 0x21, 0 - .dw 0xb0c0, 0xc19c, 0xb0ff, 0xc19c, 0x21, 0 - .dw 0xb140, 0xc19c, 0xb17f, 0xc19c, 0x21, 0 - .dw 0xb1c0, 0xc19c, 0xb1ff, 0xc19c, 0x21, 0 - .dw 0xb240, 0xc19c, 0xb27f, 0xc19c, 0x21, 0 - .dw 0xb2c0, 0xc19c, 0xb2ff, 0xc19c, 0x21, 0 - .dw 0xb340, 0xc19c, 0xb37f, 0xc19c, 0x21, 0 - .dw 0xb3c0, 0xc19c, 0xb3ff, 0xc19c, 0x21, 0 - .dw 0xb440, 0xc19c, 0xb47f, 0xc19c, 0x21, 0 - .dw 0xb4c0, 0xc19c, 0xb4ff, 0xc19c, 0x21, 0 - .dw 0xb540, 0xc19c, 0xb57f, 0xc19c, 0x21, 0 - .dw 0xb5c0, 0xc19c, 0xb5ff, 0xc19c, 0x21, 0 - .dw 0xb640, 0xc19c, 0xb67f, 0xc19c, 0x21, 0 - .dw 0xb6c0, 0xc19c, 0xb6ff, 0xc19c, 0x21, 0 - .dw 0xb740, 0xc19c, 0xb77f, 0xc19c, 0x21, 0 - .dw 0xb7c0, 0xc19c, 0xb7ff, 0xc19c, 0x21, 0 - .dw 0xb840, 0xc19c, 0xb87f, 0xc19c, 0x21, 0 - .dw 0xb8c0, 0xc19c, 0xb8ff, 0xc19c, 0x21, 0 - .dw 0xb940, 0xc19c, 0xb97f, 0xc19c, 0x21, 0 - .dw 0xb9c0, 0xc19c, 0xbfff, 0xc19c, 0x21, 0 - .dw 0xc040, 0xc19c, 0xc07f, 0xc19c, 0x21, 0 - .dw 0xc0c0, 0xc19c, 0xc0ff, 0xc19c, 0x21, 0 - .dw 0xc140, 0xc19c, 0xc17f, 0xc19c, 0x21, 0 - .dw 0xc1c0, 0xc19c, 0xc1ff, 0xc19c, 0x21, 0 - .dw 0xc240, 0xc19c, 0xc27f, 0xc19c, 0x21, 0 - .dw 0xc2c0, 0xc19c, 0xc2ff, 0xc19c, 0x21, 0 - .dw 0xc340, 0xc19c, 0xc37f, 0xc19c, 0x21, 0 - .dw 0xc3c0, 0xc19c, 0xc3ff, 0xc19c, 0x21, 0 - .dw 0xc440, 0xc19c, 0xc47f, 0xc19c, 0x21, 0 - .dw 0xc4c0, 0xc19c, 0xc4ff, 0xc19c, 0x21, 0 - .dw 0xc540, 0xc19c, 0xc57f, 0xc19c, 0x21, 0 - .dw 0xc5c0, 0xc19c, 0xc5ff, 0xc19c, 0x21, 0 - .dw 0xc640, 0xc19c, 0xc67f, 0xc19c, 0x21, 0 - .dw 0xc6c0, 0xc19c, 0xc6ff, 0xc19c, 0x21, 0 - .dw 0xc740, 0xc19c, 0xc77f, 0xc19c, 0x21, 0 - .dw 0xc7c0, 0xc19c, 0xc7ff, 0xc19c, 0x21, 0 - .dw 0xc840, 0xc19c, 0xc87f, 0xc19c, 0x21, 0 - .dw 0xc8c0, 0xc19c, 0xc8ff, 0xc19c, 0x21, 0 - .dw 0xc940, 0xc19c, 0xc97f, 0xc19c, 0x21, 0 - .dw 0xc9c0, 0xc19c, 0xc9ff, 0xc19c, 0x21, 0 - .dw 0xca40, 0xc19c, 0xca7f, 0xc19c, 0x21, 0 - .dw 0xcac0, 0xc19c, 0xcaff, 0xc19c, 0x21, 0 - .dw 0xcb40, 0xc19c, 0xcb7f, 0xc19c, 0x21, 0 - .dw 0xcbc0, 0xc19c, 0xcbff, 0xc19c, 0x21, 0 - .dw 0xcc40, 0xc19c, 0xcc7f, 0xc19c, 0x21, 0 - .dw 0xccc0, 0xc19c, 0xccff, 0xc19c, 0x21, 0 - .dw 0xcd40, 0xc19c, 0xcd7f, 0xc19c, 0x21, 0 - .dw 0xcdc0, 0xc19c, 0xcdff, 0xc19c, 0x21, 0 - .dw 0xce40, 0xc19c, 0xce7f, 0xc19c, 0x21, 0 - .dw 0xcec0, 0xc19c, 0xceff, 0xc19c, 0x21, 0 - .dw 0xcf40, 0xc19c, 0xcf7f, 0xc19c, 0x21, 0 - .dw 0xcfc0, 0xc19c, 0xcfff, 0xc19c, 0x21, 0 - .dw 0xd040, 0xc19c, 0xd07f, 0xc19c, 0x21, 0 - .dw 0xd0c0, 0xc19c, 0xd0ff, 0xc19c, 0x21, 0 - .dw 0xd140, 0xc19c, 0xd17f, 0xc19c, 0x21, 0 - .dw 0xd1c0, 0xc19c, 0xd1ff, 0xc19c, 0x21, 0 - .dw 0xd240, 0xc19c, 0xd27f, 0xc19c, 0x21, 0 - .dw 0xd2c0, 0xc19c, 0xd2ff, 0xc19c, 0x21, 0 - .dw 0xd340, 0xc19c, 0xd37f, 0xc19c, 0x21, 0 - .dw 0xd3c0, 0xc19c, 0xd3ff, 0xc19c, 0x21, 0 - .dw 0xd440, 0xc19c, 0xd47f, 0xc19c, 0x21, 0 - .dw 0xd4c0, 0xc19c, 0xd4ff, 0xc19c, 0x21, 0 - .dw 0xd540, 0xc19c, 0xd57f, 0xc19c, 0x21, 0 - .dw 0xd5c0, 0xc19c, 0xd5ff, 0xc19c, 0x21, 0 - .dw 0xd640, 0xc19c, 0xd67f, 0xc19c, 0x21, 0 - .dw 0xd6c0, 0xc19c, 0xd6ff, 0xc19c, 0x21, 0 - .dw 0xd740, 0xc19c, 0xd77f, 0xc19c, 0x21, 0 - .dw 0xd7c0, 0xc19c, 0xd7ff, 0xc19c, 0x21, 0 - .dw 0xd840, 0xc19c, 0xd87f, 0xc19c, 0x21, 0 - .dw 0xd8c0, 0xc19c, 0xd8ff, 0xc19c, 0x21, 0 - .dw 0xd940, 0xc19c, 0xd97f, 0xc19c, 0x21, 0 - .dw 0xd9c0, 0xc19c, 0xdfff, 0xc19c, 0x21, 0 - .dw 0xe040, 0xc19c, 0xe07f, 0xc19c, 0x21, 0 - .dw 0xe0c0, 0xc19c, 0xe0ff, 0xc19c, 0x21, 0 - .dw 0xe140, 0xc19c, 0xe17f, 0xc19c, 0x21, 0 - .dw 0xe1c0, 0xc19c, 0xe1ff, 0xc19c, 0x21, 0 - .dw 0xe240, 0xc19c, 0xe27f, 0xc19c, 0x21, 0 - .dw 0xe2c0, 0xc19c, 0xe2ff, 0xc19c, 0x21, 0 - .dw 0xe340, 0xc19c, 0xe37f, 0xc19c, 0x21, 0 - .dw 0xe3c0, 0xc19c, 0xe3ff, 0xc19c, 0x21, 0 - .dw 0xe440, 0xc19c, 0xe47f, 0xc19c, 0x21, 0 - .dw 0xe4c0, 0xc19c, 0xe4ff, 0xc19c, 0x21, 0 - .dw 0xe540, 0xc19c, 0xe57f, 0xc19c, 0x21, 0 - .dw 0xe5c0, 0xc19c, 0xe5ff, 0xc19c, 0x21, 0 - .dw 0xe640, 0xc19c, 0xe67f, 0xc19c, 0x21, 0 - .dw 0xe6c0, 0xc19c, 0xe6ff, 0xc19c, 0x21, 0 - .dw 0xe740, 0xc19c, 0xe77f, 0xc19c, 0x21, 0 - .dw 0xe7c0, 0xc19c, 0xe7ff, 0xc19c, 0x21, 0 - .dw 0xe840, 0xc19c, 0xe87f, 0xc19c, 0x21, 0 - .dw 0xe8c0, 0xc19c, 0xe8ff, 0xc19c, 0x21, 0 - .dw 0xe940, 0xc19c, 0xe97f, 0xc19c, 0x21, 0 - .dw 0xe9c0, 0xc19c, 0xe9ff, 0xc19c, 0x21, 0 - .dw 0xea40, 0xc19c, 0xea7f, 0xc19c, 0x21, 0 - .dw 0xeac0, 0xc19c, 0xeaff, 0xc19c, 0x21, 0 - .dw 0xeb40, 0xc19c, 0xeb7f, 0xc19c, 0x21, 0 - .dw 0xebc0, 0xc19c, 0xebff, 0xc19c, 0x21, 0 - .dw 0xec40, 0xc19c, 0xec7f, 0xc19c, 0x21, 0 - .dw 0xecc0, 0xc19c, 0xecff, 0xc19c, 0x21, 0 - .dw 0xed40, 0xc19c, 0xed7f, 0xc19c, 0x21, 0 - .dw 0xedc0, 0xc19c, 0xedff, 0xc19c, 0x21, 0 - .dw 0xee40, 0xc19c, 0xee7f, 0xc19c, 0x21, 0 - .dw 0xeec0, 0xc19c, 0xeeff, 0xc19c, 0x21, 0 - .dw 0xef40, 0xc19c, 0xef7f, 0xc19c, 0x21, 0 - .dw 0xefc0, 0xc19c, 0xefff, 0xc19c, 0x21, 0 - .dw 0xf040, 0xc19c, 0xf07f, 0xc19c, 0x21, 0 - .dw 0xf0c0, 0xc19c, 0xf0ff, 0xc19c, 0x21, 0 - .dw 0xf140, 0xc19c, 0xf17f, 0xc19c, 0x21, 0 - .dw 0xf1c0, 0xc19c, 0xf1ff, 0xc19c, 0x21, 0 - .dw 0xf240, 0xc19c, 0xf27f, 0xc19c, 0x21, 0 - .dw 0xf2c0, 0xc19c, 0xf2ff, 0xc19c, 0x21, 0 - .dw 0xf340, 0xc19c, 0xf37f, 0xc19c, 0x21, 0 - .dw 0xf3c0, 0xc19c, 0xf3ff, 0xc19c, 0x21, 0 - .dw 0xf440, 0xc19c, 0xf47f, 0xc19c, 0x21, 0 - .dw 0xf4c0, 0xc19c, 0xf4ff, 0xc19c, 0x21, 0 - .dw 0xf540, 0xc19c, 0xf57f, 0xc19c, 0x21, 0 - .dw 0xf5c0, 0xc19c, 0xf5ff, 0xc19c, 0x21, 0 - .dw 0xf640, 0xc19c, 0xf67f, 0xc19c, 0x21, 0 - .dw 0xf6c0, 0xc19c, 0xf6ff, 0xc19c, 0x21, 0 - .dw 0xf740, 0xc19c, 0xf77f, 0xc19c, 0x21, 0 - .dw 0xf7c0, 0xc19c, 0xf7ff, 0xc19c, 0x21, 0 - .dw 0xf840, 0xc19c, 0xf87f, 0xc19c, 0x21, 0 - .dw 0xf8c0, 0xc19c, 0xf8ff, 0xc19c, 0x21, 0 - .dw 0xf940, 0xc19c, 0xf97f, 0xc19c, 0x21, 0 - .dw 0xf9c0, 0xc19c, 0xffff, 0xc19c, 0x21, 0 - .dw 0x0040, 0xc19d, 0x007f, 0xc19d, 0x21, 0 - .dw 0x00c0, 0xc19d, 0x00ff, 0xc19d, 0x21, 0 - .dw 0x0140, 0xc19d, 0x017f, 0xc19d, 0x21, 0 - .dw 0x01c0, 0xc19d, 0x01ff, 0xc19d, 0x21, 0 - .dw 0x0240, 0xc19d, 0x027f, 0xc19d, 0x21, 0 - .dw 0x02c0, 0xc19d, 0x02ff, 0xc19d, 0x21, 0 - .dw 0x0340, 0xc19d, 0x037f, 0xc19d, 0x21, 0 - .dw 0x03c0, 0xc19d, 0x03ff, 0xc19d, 0x21, 0 - .dw 0x0440, 0xc19d, 0x047f, 0xc19d, 0x21, 0 - .dw 0x04c0, 0xc19d, 0x04ff, 0xc19d, 0x21, 0 - .dw 0x0540, 0xc19d, 0x057f, 0xc19d, 0x21, 0 - .dw 0x05c0, 0xc19d, 0x05ff, 0xc19d, 0x21, 0 - .dw 0x0640, 0xc19d, 0x067f, 0xc19d, 0x21, 0 - .dw 0x06c0, 0xc19d, 0x06ff, 0xc19d, 0x21, 0 - .dw 0x0740, 0xc19d, 0x077f, 0xc19d, 0x21, 0 - .dw 0x07c0, 0xc19d, 0x07ff, 0xc19d, 0x21, 0 - .dw 0x0840, 0xc19d, 0x087f, 0xc19d, 0x21, 0 - .dw 0x08c0, 0xc19d, 0x08ff, 0xc19d, 0x21, 0 - .dw 0x0940, 0xc19d, 0x097f, 0xc19d, 0x21, 0 - .dw 0x09c0, 0xc19d, 0x09ff, 0xc19d, 0x21, 0 - .dw 0x0a40, 0xc19d, 0x0a7f, 0xc19d, 0x21, 0 - .dw 0x0ac0, 0xc19d, 0x0aff, 0xc19d, 0x21, 0 - .dw 0x0b40, 0xc19d, 0x0b7f, 0xc19d, 0x21, 0 - .dw 0x0bc0, 0xc19d, 0x0bff, 0xc19d, 0x21, 0 - .dw 0x0c40, 0xc19d, 0x0c7f, 0xc19d, 0x21, 0 - .dw 0x0cc0, 0xc19d, 0x0cff, 0xc19d, 0x21, 0 - .dw 0x0d40, 0xc19d, 0x0d7f, 0xc19d, 0x21, 0 - .dw 0x0dc0, 0xc19d, 0x0dff, 0xc19d, 0x21, 0 - .dw 0x0e40, 0xc19d, 0x0e7f, 0xc19d, 0x21, 0 - .dw 0x0ec0, 0xc19d, 0x0eff, 0xc19d, 0x21, 0 - .dw 0x0f40, 0xc19d, 0x0f7f, 0xc19d, 0x21, 0 - .dw 0x0fc0, 0xc19d, 0x0fff, 0xc19d, 0x21, 0 - .dw 0x1040, 0xc19d, 0x107f, 0xc19d, 0x21, 0 - .dw 0x10c0, 0xc19d, 0x10ff, 0xc19d, 0x21, 0 - .dw 0x1140, 0xc19d, 0x117f, 0xc19d, 0x21, 0 - .dw 0x11c0, 0xc19d, 0x11ff, 0xc19d, 0x21, 0 - .dw 0x1240, 0xc19d, 0x127f, 0xc19d, 0x21, 0 - .dw 0x12c0, 0xc19d, 0x12ff, 0xc19d, 0x21, 0 - .dw 0x1340, 0xc19d, 0x137f, 0xc19d, 0x21, 0 - .dw 0x13c0, 0xc19d, 0x13ff, 0xc19d, 0x21, 0 - .dw 0x1440, 0xc19d, 0x147f, 0xc19d, 0x21, 0 - .dw 0x14c0, 0xc19d, 0x14ff, 0xc19d, 0x21, 0 - .dw 0x1540, 0xc19d, 0x157f, 0xc19d, 0x21, 0 - .dw 0x15c0, 0xc19d, 0x15ff, 0xc19d, 0x21, 0 - .dw 0x1640, 0xc19d, 0x167f, 0xc19d, 0x21, 0 - .dw 0x16c0, 0xc19d, 0x16ff, 0xc19d, 0x21, 0 - .dw 0x1740, 0xc19d, 0x177f, 0xc19d, 0x21, 0 - .dw 0x17c0, 0xc19d, 0x17ff, 0xc19d, 0x21, 0 - .dw 0x1840, 0xc19d, 0x187f, 0xc19d, 0x21, 0 - .dw 0x18c0, 0xc19d, 0x18ff, 0xc19d, 0x21, 0 - .dw 0x1940, 0xc19d, 0x197f, 0xc19d, 0x21, 0 - .dw 0x19c0, 0xc19d, 0x1fff, 0xc19d, 0x21, 0 - .dw 0x2040, 0xc19d, 0x207f, 0xc19d, 0x21, 0 - .dw 0x20c0, 0xc19d, 0x20ff, 0xc19d, 0x21, 0 - .dw 0x2140, 0xc19d, 0x217f, 0xc19d, 0x21, 0 - .dw 0x21c0, 0xc19d, 0x21ff, 0xc19d, 0x21, 0 - .dw 0x2240, 0xc19d, 0x227f, 0xc19d, 0x21, 0 - .dw 0x22c0, 0xc19d, 0x22ff, 0xc19d, 0x21, 0 - .dw 0x2340, 0xc19d, 0x237f, 0xc19d, 0x21, 0 - .dw 0x23c0, 0xc19d, 0x23ff, 0xc19d, 0x21, 0 - .dw 0x2440, 0xc19d, 0x247f, 0xc19d, 0x21, 0 - .dw 0x24c0, 0xc19d, 0x24ff, 0xc19d, 0x21, 0 - .dw 0x2540, 0xc19d, 0x257f, 0xc19d, 0x21, 0 - .dw 0x25c0, 0xc19d, 0x25ff, 0xc19d, 0x21, 0 - .dw 0x2640, 0xc19d, 0x267f, 0xc19d, 0x21, 0 - .dw 0x26c0, 0xc19d, 0x26ff, 0xc19d, 0x21, 0 - .dw 0x2740, 0xc19d, 0x277f, 0xc19d, 0x21, 0 - .dw 0x27c0, 0xc19d, 0x27ff, 0xc19d, 0x21, 0 - .dw 0x2840, 0xc19d, 0x287f, 0xc19d, 0x21, 0 - .dw 0x28c0, 0xc19d, 0x28ff, 0xc19d, 0x21, 0 - .dw 0x2940, 0xc19d, 0x297f, 0xc19d, 0x21, 0 - .dw 0x29c0, 0xc19d, 0x29ff, 0xc19d, 0x21, 0 - .dw 0x2a40, 0xc19d, 0x2a7f, 0xc19d, 0x21, 0 - .dw 0x2ac0, 0xc19d, 0x2aff, 0xc19d, 0x21, 0 - .dw 0x2b40, 0xc19d, 0x2b7f, 0xc19d, 0x21, 0 - .dw 0x2bc0, 0xc19d, 0x2bff, 0xc19d, 0x21, 0 - .dw 0x2c40, 0xc19d, 0x2c7f, 0xc19d, 0x21, 0 - .dw 0x2cc0, 0xc19d, 0x2cff, 0xc19d, 0x21, 0 - .dw 0x2d40, 0xc19d, 0x2d7f, 0xc19d, 0x21, 0 - .dw 0x2dc0, 0xc19d, 0x2dff, 0xc19d, 0x21, 0 - .dw 0x2e40, 0xc19d, 0x2e7f, 0xc19d, 0x21, 0 - .dw 0x2ec0, 0xc19d, 0x2eff, 0xc19d, 0x21, 0 - .dw 0x2f40, 0xc19d, 0x2f7f, 0xc19d, 0x21, 0 - .dw 0x2fc0, 0xc19d, 0x2fff, 0xc19d, 0x21, 0 - .dw 0x3040, 0xc19d, 0x307f, 0xc19d, 0x21, 0 - .dw 0x30c0, 0xc19d, 0x30ff, 0xc19d, 0x21, 0 - .dw 0x3140, 0xc19d, 0x317f, 0xc19d, 0x21, 0 - .dw 0x31c0, 0xc19d, 0x31ff, 0xc19d, 0x21, 0 - .dw 0x3240, 0xc19d, 0x327f, 0xc19d, 0x21, 0 - .dw 0x32c0, 0xc19d, 0x32ff, 0xc19d, 0x21, 0 - .dw 0x3340, 0xc19d, 0x337f, 0xc19d, 0x21, 0 - .dw 0x33c0, 0xc19d, 0x33ff, 0xc19d, 0x21, 0 - .dw 0x3440, 0xc19d, 0x347f, 0xc19d, 0x21, 0 - .dw 0x34c0, 0xc19d, 0x34ff, 0xc19d, 0x21, 0 - .dw 0x3540, 0xc19d, 0x357f, 0xc19d, 0x21, 0 - .dw 0x35c0, 0xc19d, 0x35ff, 0xc19d, 0x21, 0 - .dw 0x3640, 0xc19d, 0x367f, 0xc19d, 0x21, 0 - .dw 0x36c0, 0xc19d, 0x36ff, 0xc19d, 0x21, 0 - .dw 0x3740, 0xc19d, 0x377f, 0xc19d, 0x21, 0 - .dw 0x37c0, 0xc19d, 0x37ff, 0xc19d, 0x21, 0 - .dw 0x3840, 0xc19d, 0x387f, 0xc19d, 0x21, 0 - .dw 0x38c0, 0xc19d, 0x38ff, 0xc19d, 0x21, 0 - .dw 0x3940, 0xc19d, 0x397f, 0xc19d, 0x21, 0 - .dw 0x39c0, 0xc19d, 0x3fff, 0xc19d, 0x21, 0 - .dw 0x4040, 0xc19d, 0x407f, 0xc19d, 0x21, 0 - .dw 0x40c0, 0xc19d, 0x40ff, 0xc19d, 0x21, 0 - .dw 0x4140, 0xc19d, 0x417f, 0xc19d, 0x21, 0 - .dw 0x41c0, 0xc19d, 0x41ff, 0xc19d, 0x21, 0 - .dw 0x4240, 0xc19d, 0x427f, 0xc19d, 0x21, 0 - .dw 0x42c0, 0xc19d, 0x42ff, 0xc19d, 0x21, 0 - .dw 0x4340, 0xc19d, 0x437f, 0xc19d, 0x21, 0 - .dw 0x43c0, 0xc19d, 0x43ff, 0xc19d, 0x21, 0 - .dw 0x4440, 0xc19d, 0x447f, 0xc19d, 0x21, 0 - .dw 0x44c0, 0xc19d, 0x44ff, 0xc19d, 0x21, 0 - .dw 0x4540, 0xc19d, 0x457f, 0xc19d, 0x21, 0 - .dw 0x45c0, 0xc19d, 0x45ff, 0xc19d, 0x21, 0 - .dw 0x4640, 0xc19d, 0x467f, 0xc19d, 0x21, 0 - .dw 0x46c0, 0xc19d, 0x46ff, 0xc19d, 0x21, 0 - .dw 0x4740, 0xc19d, 0x477f, 0xc19d, 0x21, 0 - .dw 0x47c0, 0xc19d, 0x47ff, 0xc19d, 0x21, 0 - .dw 0x4840, 0xc19d, 0x487f, 0xc19d, 0x21, 0 - .dw 0x48c0, 0xc19d, 0x48ff, 0xc19d, 0x21, 0 - .dw 0x4940, 0xc19d, 0x497f, 0xc19d, 0x21, 0 - .dw 0x49c0, 0xc19d, 0x49ff, 0xc19d, 0x21, 0 - .dw 0x4a40, 0xc19d, 0x4a7f, 0xc19d, 0x21, 0 - .dw 0x4ac0, 0xc19d, 0x4aff, 0xc19d, 0x21, 0 - .dw 0x4b40, 0xc19d, 0x4b7f, 0xc19d, 0x21, 0 - .dw 0x4bc0, 0xc19d, 0x4bff, 0xc19d, 0x21, 0 - .dw 0x4c40, 0xc19d, 0x4c7f, 0xc19d, 0x21, 0 - .dw 0x4cc0, 0xc19d, 0x4cff, 0xc19d, 0x21, 0 - .dw 0x4d40, 0xc19d, 0x4d7f, 0xc19d, 0x21, 0 - .dw 0x4dc0, 0xc19d, 0x4dff, 0xc19d, 0x21, 0 - .dw 0x4e40, 0xc19d, 0x4e7f, 0xc19d, 0x21, 0 - .dw 0x4ec0, 0xc19d, 0x4eff, 0xc19d, 0x21, 0 - .dw 0x4f40, 0xc19d, 0x4f7f, 0xc19d, 0x21, 0 - .dw 0x4fc0, 0xc19d, 0x4fff, 0xc19d, 0x21, 0 - .dw 0x5040, 0xc19d, 0x507f, 0xc19d, 0x21, 0 - .dw 0x50c0, 0xc19d, 0x50ff, 0xc19d, 0x21, 0 - .dw 0x5140, 0xc19d, 0x517f, 0xc19d, 0x21, 0 - .dw 0x51c0, 0xc19d, 0x51ff, 0xc19d, 0x21, 0 - .dw 0x5240, 0xc19d, 0x527f, 0xc19d, 0x21, 0 - .dw 0x52c0, 0xc19d, 0x52ff, 0xc19d, 0x21, 0 - .dw 0x5340, 0xc19d, 0x537f, 0xc19d, 0x21, 0 - .dw 0x53c0, 0xc19d, 0x53ff, 0xc19d, 0x21, 0 - .dw 0x5440, 0xc19d, 0x547f, 0xc19d, 0x21, 0 - .dw 0x54c0, 0xc19d, 0x54ff, 0xc19d, 0x21, 0 - .dw 0x5540, 0xc19d, 0x557f, 0xc19d, 0x21, 0 - .dw 0x55c0, 0xc19d, 0x55ff, 0xc19d, 0x21, 0 - .dw 0x5640, 0xc19d, 0x567f, 0xc19d, 0x21, 0 - .dw 0x56c0, 0xc19d, 0x56ff, 0xc19d, 0x21, 0 - .dw 0x5740, 0xc19d, 0x577f, 0xc19d, 0x21, 0 - .dw 0x57c0, 0xc19d, 0x57ff, 0xc19d, 0x21, 0 - .dw 0x5840, 0xc19d, 0x587f, 0xc19d, 0x21, 0 - .dw 0x58c0, 0xc19d, 0x58ff, 0xc19d, 0x21, 0 - .dw 0x5940, 0xc19d, 0x597f, 0xc19d, 0x21, 0 - .dw 0x59c0, 0xc19d, 0x5fff, 0xc19d, 0x21, 0 - .dw 0x6040, 0xc19d, 0x607f, 0xc19d, 0x21, 0 - .dw 0x60c0, 0xc19d, 0x60ff, 0xc19d, 0x21, 0 - .dw 0x6140, 0xc19d, 0x617f, 0xc19d, 0x21, 0 - .dw 0x61c0, 0xc19d, 0x61ff, 0xc19d, 0x21, 0 - .dw 0x6240, 0xc19d, 0x627f, 0xc19d, 0x21, 0 - .dw 0x62c0, 0xc19d, 0x62ff, 0xc19d, 0x21, 0 - .dw 0x6340, 0xc19d, 0x637f, 0xc19d, 0x21, 0 - .dw 0x63c0, 0xc19d, 0x63ff, 0xc19d, 0x21, 0 - .dw 0x6440, 0xc19d, 0x647f, 0xc19d, 0x21, 0 - .dw 0x64c0, 0xc19d, 0x64ff, 0xc19d, 0x21, 0 - .dw 0x6540, 0xc19d, 0x657f, 0xc19d, 0x21, 0 - .dw 0x65c0, 0xc19d, 0x65ff, 0xc19d, 0x21, 0 - .dw 0x6640, 0xc19d, 0x667f, 0xc19d, 0x21, 0 - .dw 0x66c0, 0xc19d, 0x66ff, 0xc19d, 0x21, 0 - .dw 0x6740, 0xc19d, 0x677f, 0xc19d, 0x21, 0 - .dw 0x67c0, 0xc19d, 0x67ff, 0xc19d, 0x21, 0 - .dw 0x6840, 0xc19d, 0x687f, 0xc19d, 0x21, 0 - .dw 0x68c0, 0xc19d, 0x68ff, 0xc19d, 0x21, 0 - .dw 0x6940, 0xc19d, 0x697f, 0xc19d, 0x21, 0 - .dw 0x69c0, 0xc19d, 0x69ff, 0xc19d, 0x21, 0 - .dw 0x6a40, 0xc19d, 0x6a7f, 0xc19d, 0x21, 0 - .dw 0x6ac0, 0xc19d, 0x6aff, 0xc19d, 0x21, 0 - .dw 0x6b40, 0xc19d, 0x6b7f, 0xc19d, 0x21, 0 - .dw 0x6bc0, 0xc19d, 0x6bff, 0xc19d, 0x21, 0 - .dw 0x6c40, 0xc19d, 0x6c7f, 0xc19d, 0x21, 0 - .dw 0x6cc0, 0xc19d, 0x6cff, 0xc19d, 0x21, 0 - .dw 0x6d40, 0xc19d, 0x6d7f, 0xc19d, 0x21, 0 - .dw 0x6dc0, 0xc19d, 0x6dff, 0xc19d, 0x21, 0 - .dw 0x6e40, 0xc19d, 0x6e7f, 0xc19d, 0x21, 0 - .dw 0x6ec0, 0xc19d, 0x6eff, 0xc19d, 0x21, 0 - .dw 0x6f40, 0xc19d, 0x6f7f, 0xc19d, 0x21, 0 - .dw 0x6fc0, 0xc19d, 0x6fff, 0xc19d, 0x21, 0 - .dw 0x7040, 0xc19d, 0x707f, 0xc19d, 0x21, 0 - .dw 0x70c0, 0xc19d, 0x70ff, 0xc19d, 0x21, 0 - .dw 0x7140, 0xc19d, 0x717f, 0xc19d, 0x21, 0 - .dw 0x71c0, 0xc19d, 0x71ff, 0xc19d, 0x21, 0 - .dw 0x7240, 0xc19d, 0x727f, 0xc19d, 0x21, 0 - .dw 0x72c0, 0xc19d, 0x72ff, 0xc19d, 0x21, 0 - .dw 0x7340, 0xc19d, 0x737f, 0xc19d, 0x21, 0 - .dw 0x73c0, 0xc19d, 0x73ff, 0xc19d, 0x21, 0 - .dw 0x7440, 0xc19d, 0x747f, 0xc19d, 0x21, 0 - .dw 0x74c0, 0xc19d, 0x74ff, 0xc19d, 0x21, 0 - .dw 0x7540, 0xc19d, 0x757f, 0xc19d, 0x21, 0 - .dw 0x75c0, 0xc19d, 0x75ff, 0xc19d, 0x21, 0 - .dw 0x7640, 0xc19d, 0x767f, 0xc19d, 0x21, 0 - .dw 0x76c0, 0xc19d, 0x76ff, 0xc19d, 0x21, 0 - .dw 0x7740, 0xc19d, 0x777f, 0xc19d, 0x21, 0 - .dw 0x77c0, 0xc19d, 0x77ff, 0xc19d, 0x21, 0 - .dw 0x7840, 0xc19d, 0x787f, 0xc19d, 0x21, 0 - .dw 0x78c0, 0xc19d, 0x78ff, 0xc19d, 0x21, 0 - .dw 0x7940, 0xc19d, 0x797f, 0xc19d, 0x21, 0 - .dw 0x79c0, 0xc19d, 0x7fff, 0xc19d, 0x21, 0 - .dw 0x8040, 0xc19d, 0x807f, 0xc19d, 0x21, 0 - .dw 0x80c0, 0xc19d, 0x80ff, 0xc19d, 0x21, 0 - .dw 0x8140, 0xc19d, 0x817f, 0xc19d, 0x21, 0 - .dw 0x81c0, 0xc19d, 0x81ff, 0xc19d, 0x21, 0 - .dw 0x8240, 0xc19d, 0x827f, 0xc19d, 0x21, 0 - .dw 0x82c0, 0xc19d, 0x82ff, 0xc19d, 0x21, 0 - .dw 0x8340, 0xc19d, 0x837f, 0xc19d, 0x21, 0 - .dw 0x83c0, 0xc19d, 0x83ff, 0xc19d, 0x21, 0 - .dw 0x8440, 0xc19d, 0x847f, 0xc19d, 0x21, 0 - .dw 0x84c0, 0xc19d, 0x84ff, 0xc19d, 0x21, 0 - .dw 0x8540, 0xc19d, 0x857f, 0xc19d, 0x21, 0 - .dw 0x85c0, 0xc19d, 0x85ff, 0xc19d, 0x21, 0 - .dw 0x8640, 0xc19d, 0x867f, 0xc19d, 0x21, 0 - .dw 0x86c0, 0xc19d, 0x86ff, 0xc19d, 0x21, 0 - .dw 0x8740, 0xc19d, 0x877f, 0xc19d, 0x21, 0 - .dw 0x87c0, 0xc19d, 0x87ff, 0xc19d, 0x21, 0 - .dw 0x8840, 0xc19d, 0x887f, 0xc19d, 0x21, 0 - .dw 0x88c0, 0xc19d, 0x88ff, 0xc19d, 0x21, 0 - .dw 0x8940, 0xc19d, 0x897f, 0xc19d, 0x21, 0 - .dw 0x89c0, 0xc19d, 0x89ff, 0xc19d, 0x21, 0 - .dw 0x8a40, 0xc19d, 0x8a7f, 0xc19d, 0x21, 0 - .dw 0x8ac0, 0xc19d, 0x8aff, 0xc19d, 0x21, 0 - .dw 0x8b40, 0xc19d, 0x8b7f, 0xc19d, 0x21, 0 - .dw 0x8bc0, 0xc19d, 0x8bff, 0xc19d, 0x21, 0 - .dw 0x8c40, 0xc19d, 0x8c7f, 0xc19d, 0x21, 0 - .dw 0x8cc0, 0xc19d, 0x8cff, 0xc19d, 0x21, 0 - .dw 0x8d40, 0xc19d, 0x8d7f, 0xc19d, 0x21, 0 - .dw 0x8dc0, 0xc19d, 0x8dff, 0xc19d, 0x21, 0 - .dw 0x8e40, 0xc19d, 0x8e7f, 0xc19d, 0x21, 0 - .dw 0x8ec0, 0xc19d, 0x8eff, 0xc19d, 0x21, 0 - .dw 0x8f40, 0xc19d, 0x8f7f, 0xc19d, 0x21, 0 - .dw 0x8fc0, 0xc19d, 0x8fff, 0xc19d, 0x21, 0 - .dw 0x9040, 0xc19d, 0x907f, 0xc19d, 0x21, 0 - .dw 0x90c0, 0xc19d, 0x90ff, 0xc19d, 0x21, 0 - .dw 0x9140, 0xc19d, 0x917f, 0xc19d, 0x21, 0 - .dw 0x91c0, 0xc19d, 0x91ff, 0xc19d, 0x21, 0 - .dw 0x9240, 0xc19d, 0x927f, 0xc19d, 0x21, 0 - .dw 0x92c0, 0xc19d, 0x92ff, 0xc19d, 0x21, 0 - .dw 0x9340, 0xc19d, 0x937f, 0xc19d, 0x21, 0 - .dw 0x93c0, 0xc19d, 0x93ff, 0xc19d, 0x21, 0 - .dw 0x9440, 0xc19d, 0x947f, 0xc19d, 0x21, 0 - .dw 0x94c0, 0xc19d, 0x94ff, 0xc19d, 0x21, 0 - .dw 0x9540, 0xc19d, 0x957f, 0xc19d, 0x21, 0 - .dw 0x95c0, 0xc19d, 0x95ff, 0xc19d, 0x21, 0 - .dw 0x9640, 0xc19d, 0x967f, 0xc19d, 0x21, 0 - .dw 0x96c0, 0xc19d, 0x96ff, 0xc19d, 0x21, 0 - .dw 0x9740, 0xc19d, 0x977f, 0xc19d, 0x21, 0 - .dw 0x97c0, 0xc19d, 0x97ff, 0xc19d, 0x21, 0 - .dw 0x9840, 0xc19d, 0x987f, 0xc19d, 0x21, 0 - .dw 0x98c0, 0xc19d, 0x98ff, 0xc19d, 0x21, 0 - .dw 0x9940, 0xc19d, 0x997f, 0xc19d, 0x21, 0 - .dw 0x99c0, 0xc19d, 0x9fff, 0xc19d, 0x21, 0 - .dw 0xa040, 0xc19d, 0xa07f, 0xc19d, 0x21, 0 - .dw 0xa0c0, 0xc19d, 0xa0ff, 0xc19d, 0x21, 0 - .dw 0xa140, 0xc19d, 0xa17f, 0xc19d, 0x21, 0 - .dw 0xa1c0, 0xc19d, 0xa1ff, 0xc19d, 0x21, 0 - .dw 0xa240, 0xc19d, 0xa27f, 0xc19d, 0x21, 0 - .dw 0xa2c0, 0xc19d, 0xa2ff, 0xc19d, 0x21, 0 - .dw 0xa340, 0xc19d, 0xa37f, 0xc19d, 0x21, 0 - .dw 0xa3c0, 0xc19d, 0xa3ff, 0xc19d, 0x21, 0 - .dw 0xa440, 0xc19d, 0xa47f, 0xc19d, 0x21, 0 - .dw 0xa4c0, 0xc19d, 0xa4ff, 0xc19d, 0x21, 0 - .dw 0xa540, 0xc19d, 0xa57f, 0xc19d, 0x21, 0 - .dw 0xa5c0, 0xc19d, 0xa5ff, 0xc19d, 0x21, 0 - .dw 0xa640, 0xc19d, 0xa67f, 0xc19d, 0x21, 0 - .dw 0xa6c0, 0xc19d, 0xa6ff, 0xc19d, 0x21, 0 - .dw 0xa740, 0xc19d, 0xa77f, 0xc19d, 0x21, 0 - .dw 0xa7c0, 0xc19d, 0xa7ff, 0xc19d, 0x21, 0 - .dw 0xa840, 0xc19d, 0xa87f, 0xc19d, 0x21, 0 - .dw 0xa8c0, 0xc19d, 0xa8ff, 0xc19d, 0x21, 0 - .dw 0xa940, 0xc19d, 0xa97f, 0xc19d, 0x21, 0 - .dw 0xa9c0, 0xc19d, 0xa9ff, 0xc19d, 0x21, 0 - .dw 0xaa40, 0xc19d, 0xaa7f, 0xc19d, 0x21, 0 - .dw 0xaac0, 0xc19d, 0xaaff, 0xc19d, 0x21, 0 - .dw 0xab40, 0xc19d, 0xab7f, 0xc19d, 0x21, 0 - .dw 0xabc0, 0xc19d, 0xabff, 0xc19d, 0x21, 0 - .dw 0xac40, 0xc19d, 0xac7f, 0xc19d, 0x21, 0 - .dw 0xacc0, 0xc19d, 0xacff, 0xc19d, 0x21, 0 - .dw 0xad40, 0xc19d, 0xad7f, 0xc19d, 0x21, 0 - .dw 0xadc0, 0xc19d, 0xadff, 0xc19d, 0x21, 0 - .dw 0xae40, 0xc19d, 0xae7f, 0xc19d, 0x21, 0 - .dw 0xaec0, 0xc19d, 0xaeff, 0xc19d, 0x21, 0 - .dw 0xaf40, 0xc19d, 0xaf7f, 0xc19d, 0x21, 0 - .dw 0xafc0, 0xc19d, 0xafff, 0xc19d, 0x21, 0 - .dw 0xb040, 0xc19d, 0xb07f, 0xc19d, 0x21, 0 - .dw 0xb0c0, 0xc19d, 0xb0ff, 0xc19d, 0x21, 0 - .dw 0xb140, 0xc19d, 0xb17f, 0xc19d, 0x21, 0 - .dw 0xb1c0, 0xc19d, 0xb1ff, 0xc19d, 0x21, 0 - .dw 0xb240, 0xc19d, 0xb27f, 0xc19d, 0x21, 0 - .dw 0xb2c0, 0xc19d, 0xb2ff, 0xc19d, 0x21, 0 - .dw 0xb340, 0xc19d, 0xb37f, 0xc19d, 0x21, 0 - .dw 0xb3c0, 0xc19d, 0xb3ff, 0xc19d, 0x21, 0 - .dw 0xb440, 0xc19d, 0xb47f, 0xc19d, 0x21, 0 - .dw 0xb4c0, 0xc19d, 0xb4ff, 0xc19d, 0x21, 0 - .dw 0xb540, 0xc19d, 0xb57f, 0xc19d, 0x21, 0 - .dw 0xb5c0, 0xc19d, 0xb5ff, 0xc19d, 0x21, 0 - .dw 0xb640, 0xc19d, 0xb67f, 0xc19d, 0x21, 0 - .dw 0xb6c0, 0xc19d, 0xb6ff, 0xc19d, 0x21, 0 - .dw 0xb740, 0xc19d, 0xb77f, 0xc19d, 0x21, 0 - .dw 0xb7c0, 0xc19d, 0xb7ff, 0xc19d, 0x21, 0 - .dw 0xb840, 0xc19d, 0xb87f, 0xc19d, 0x21, 0 - .dw 0xb8c0, 0xc19d, 0xb8ff, 0xc19d, 0x21, 0 - .dw 0xb940, 0xc19d, 0xb97f, 0xc19d, 0x21, 0 - .dw 0xb9c0, 0xc19d, 0xbfff, 0xc19d, 0x21, 0 - .dw 0xc040, 0xc19d, 0xc07f, 0xc19d, 0x21, 0 - .dw 0xc0c0, 0xc19d, 0xc0ff, 0xc19d, 0x21, 0 - .dw 0xc140, 0xc19d, 0xc17f, 0xc19d, 0x21, 0 - .dw 0xc1c0, 0xc19d, 0xc1ff, 0xc19d, 0x21, 0 - .dw 0xc240, 0xc19d, 0xc27f, 0xc19d, 0x21, 0 - .dw 0xc2c0, 0xc19d, 0xc2ff, 0xc19d, 0x21, 0 - .dw 0xc340, 0xc19d, 0xc37f, 0xc19d, 0x21, 0 - .dw 0xc3c0, 0xc19d, 0xc3ff, 0xc19d, 0x21, 0 - .dw 0xc440, 0xc19d, 0xc47f, 0xc19d, 0x21, 0 - .dw 0xc4c0, 0xc19d, 0xc4ff, 0xc19d, 0x21, 0 - .dw 0xc540, 0xc19d, 0xc57f, 0xc19d, 0x21, 0 - .dw 0xc5c0, 0xc19d, 0xc5ff, 0xc19d, 0x21, 0 - .dw 0xc640, 0xc19d, 0xc67f, 0xc19d, 0x21, 0 - .dw 0xc6c0, 0xc19d, 0xc6ff, 0xc19d, 0x21, 0 - .dw 0xc740, 0xc19d, 0xc77f, 0xc19d, 0x21, 0 - .dw 0xc7c0, 0xc19d, 0xc7ff, 0xc19d, 0x21, 0 - .dw 0xc840, 0xc19d, 0xc87f, 0xc19d, 0x21, 0 - .dw 0xc8c0, 0xc19d, 0xc8ff, 0xc19d, 0x21, 0 - .dw 0xc940, 0xc19d, 0xc97f, 0xc19d, 0x21, 0 - .dw 0xc9c0, 0xc19d, 0xc9ff, 0xc19d, 0x21, 0 - .dw 0xca40, 0xc19d, 0xca7f, 0xc19d, 0x21, 0 - .dw 0xcac0, 0xc19d, 0xcaff, 0xc19d, 0x21, 0 - .dw 0xcb40, 0xc19d, 0xcb7f, 0xc19d, 0x21, 0 - .dw 0xcbc0, 0xc19d, 0xcbff, 0xc19d, 0x21, 0 - .dw 0xcc40, 0xc19d, 0xcc7f, 0xc19d, 0x21, 0 - .dw 0xccc0, 0xc19d, 0xccff, 0xc19d, 0x21, 0 - .dw 0xcd40, 0xc19d, 0xcd7f, 0xc19d, 0x21, 0 - .dw 0xcdc0, 0xc19d, 0xcdff, 0xc19d, 0x21, 0 - .dw 0xce40, 0xc19d, 0xce7f, 0xc19d, 0x21, 0 - .dw 0xcec0, 0xc19d, 0xceff, 0xc19d, 0x21, 0 - .dw 0xcf40, 0xc19d, 0xcf7f, 0xc19d, 0x21, 0 - .dw 0xcfc0, 0xc19d, 0xcfff, 0xc19d, 0x21, 0 - .dw 0xd040, 0xc19d, 0xd07f, 0xc19d, 0x21, 0 - .dw 0xd0c0, 0xc19d, 0xd0ff, 0xc19d, 0x21, 0 - .dw 0xd140, 0xc19d, 0xd17f, 0xc19d, 0x21, 0 - .dw 0xd1c0, 0xc19d, 0xd1ff, 0xc19d, 0x21, 0 - .dw 0xd240, 0xc19d, 0xd27f, 0xc19d, 0x21, 0 - .dw 0xd2c0, 0xc19d, 0xd2ff, 0xc19d, 0x21, 0 - .dw 0xd340, 0xc19d, 0xd37f, 0xc19d, 0x21, 0 - .dw 0xd3c0, 0xc19d, 0xd3ff, 0xc19d, 0x21, 0 - .dw 0xd440, 0xc19d, 0xd47f, 0xc19d, 0x21, 0 - .dw 0xd4c0, 0xc19d, 0xd4ff, 0xc19d, 0x21, 0 - .dw 0xd540, 0xc19d, 0xd57f, 0xc19d, 0x21, 0 - .dw 0xd5c0, 0xc19d, 0xd5ff, 0xc19d, 0x21, 0 - .dw 0xd640, 0xc19d, 0xd67f, 0xc19d, 0x21, 0 - .dw 0xd6c0, 0xc19d, 0xd6ff, 0xc19d, 0x21, 0 - .dw 0xd740, 0xc19d, 0xd77f, 0xc19d, 0x21, 0 - .dw 0xd7c0, 0xc19d, 0xd7ff, 0xc19d, 0x21, 0 - .dw 0xd840, 0xc19d, 0xd87f, 0xc19d, 0x21, 0 - .dw 0xd8c0, 0xc19d, 0xd8ff, 0xc19d, 0x21, 0 - .dw 0xd940, 0xc19d, 0xd97f, 0xc19d, 0x21, 0 - .dw 0xd9c0, 0xc19d, 0xdfff, 0xc19d, 0x21, 0 - .dw 0xe040, 0xc19d, 0xe07f, 0xc19d, 0x21, 0 - .dw 0xe0c0, 0xc19d, 0xe0ff, 0xc19d, 0x21, 0 - .dw 0xe140, 0xc19d, 0xe17f, 0xc19d, 0x21, 0 - .dw 0xe1c0, 0xc19d, 0xe1ff, 0xc19d, 0x21, 0 - .dw 0xe240, 0xc19d, 0xe27f, 0xc19d, 0x21, 0 - .dw 0xe2c0, 0xc19d, 0xe2ff, 0xc19d, 0x21, 0 - .dw 0xe340, 0xc19d, 0xe37f, 0xc19d, 0x21, 0 - .dw 0xe3c0, 0xc19d, 0xe3ff, 0xc19d, 0x21, 0 - .dw 0xe440, 0xc19d, 0xe47f, 0xc19d, 0x21, 0 - .dw 0xe4c0, 0xc19d, 0xe4ff, 0xc19d, 0x21, 0 - .dw 0xe540, 0xc19d, 0xe57f, 0xc19d, 0x21, 0 - .dw 0xe5c0, 0xc19d, 0xe5ff, 0xc19d, 0x21, 0 - .dw 0xe640, 0xc19d, 0xe67f, 0xc19d, 0x21, 0 - .dw 0xe6c0, 0xc19d, 0xe6ff, 0xc19d, 0x21, 0 - .dw 0xe740, 0xc19d, 0xe77f, 0xc19d, 0x21, 0 - .dw 0xe7c0, 0xc19d, 0xe7ff, 0xc19d, 0x21, 0 - .dw 0xe840, 0xc19d, 0xe87f, 0xc19d, 0x21, 0 - .dw 0xe8c0, 0xc19d, 0xe8ff, 0xc19d, 0x21, 0 - .dw 0xe940, 0xc19d, 0xe97f, 0xc19d, 0x21, 0 - .dw 0xe9c0, 0xc19d, 0xe9ff, 0xc19d, 0x21, 0 - .dw 0xea40, 0xc19d, 0xea7f, 0xc19d, 0x21, 0 - .dw 0xeac0, 0xc19d, 0xeaff, 0xc19d, 0x21, 0 - .dw 0xeb40, 0xc19d, 0xeb7f, 0xc19d, 0x21, 0 - .dw 0xebc0, 0xc19d, 0xebff, 0xc19d, 0x21, 0 - .dw 0xec40, 0xc19d, 0xec7f, 0xc19d, 0x21, 0 - .dw 0xecc0, 0xc19d, 0xecff, 0xc19d, 0x21, 0 - .dw 0xed40, 0xc19d, 0xed7f, 0xc19d, 0x21, 0 - .dw 0xedc0, 0xc19d, 0xedff, 0xc19d, 0x21, 0 - .dw 0xee40, 0xc19d, 0xee7f, 0xc19d, 0x21, 0 - .dw 0xeec0, 0xc19d, 0xeeff, 0xc19d, 0x21, 0 - .dw 0xef40, 0xc19d, 0xef7f, 0xc19d, 0x21, 0 - .dw 0xefc0, 0xc19d, 0xefff, 0xc19d, 0x21, 0 - .dw 0xf040, 0xc19d, 0xf07f, 0xc19d, 0x21, 0 - .dw 0xf0c0, 0xc19d, 0xf0ff, 0xc19d, 0x21, 0 - .dw 0xf140, 0xc19d, 0xf17f, 0xc19d, 0x21, 0 - .dw 0xf1c0, 0xc19d, 0xf1ff, 0xc19d, 0x21, 0 - .dw 0xf240, 0xc19d, 0xf27f, 0xc19d, 0x21, 0 - .dw 0xf2c0, 0xc19d, 0xf2ff, 0xc19d, 0x21, 0 - .dw 0xf340, 0xc19d, 0xf37f, 0xc19d, 0x21, 0 - .dw 0xf3c0, 0xc19d, 0xf3ff, 0xc19d, 0x21, 0 - .dw 0xf440, 0xc19d, 0xf47f, 0xc19d, 0x21, 0 - .dw 0xf4c0, 0xc19d, 0xf4ff, 0xc19d, 0x21, 0 - .dw 0xf540, 0xc19d, 0xf57f, 0xc19d, 0x21, 0 - .dw 0xf5c0, 0xc19d, 0xf5ff, 0xc19d, 0x21, 0 - .dw 0xf640, 0xc19d, 0xf67f, 0xc19d, 0x21, 0 - .dw 0xf6c0, 0xc19d, 0xf6ff, 0xc19d, 0x21, 0 - .dw 0xf740, 0xc19d, 0xf77f, 0xc19d, 0x21, 0 - .dw 0xf7c0, 0xc19d, 0xf7ff, 0xc19d, 0x21, 0 - .dw 0xf840, 0xc19d, 0xf87f, 0xc19d, 0x21, 0 - .dw 0xf8c0, 0xc19d, 0xf8ff, 0xc19d, 0x21, 0 - .dw 0xf940, 0xc19d, 0xf97f, 0xc19d, 0x21, 0 - .dw 0xf9c0, 0xc19d, 0xffff, 0xc19d, 0x21, 0 - .dw 0x0040, 0xc19e, 0x007f, 0xc19e, 0x21, 0 - .dw 0x00c0, 0xc19e, 0x00ff, 0xc19e, 0x21, 0 - .dw 0x0140, 0xc19e, 0x017f, 0xc19e, 0x21, 0 - .dw 0x01c0, 0xc19e, 0x01ff, 0xc19e, 0x21, 0 - .dw 0x0240, 0xc19e, 0x027f, 0xc19e, 0x21, 0 - .dw 0x02c0, 0xc19e, 0x02ff, 0xc19e, 0x21, 0 - .dw 0x0340, 0xc19e, 0x037f, 0xc19e, 0x21, 0 - .dw 0x03c0, 0xc19e, 0x03ff, 0xc19e, 0x21, 0 - .dw 0x0440, 0xc19e, 0x047f, 0xc19e, 0x21, 0 - .dw 0x04c0, 0xc19e, 0x04ff, 0xc19e, 0x21, 0 - .dw 0x0540, 0xc19e, 0x057f, 0xc19e, 0x21, 0 - .dw 0x05c0, 0xc19e, 0x05ff, 0xc19e, 0x21, 0 - .dw 0x0640, 0xc19e, 0x067f, 0xc19e, 0x21, 0 - .dw 0x06c0, 0xc19e, 0x06ff, 0xc19e, 0x21, 0 - .dw 0x0740, 0xc19e, 0x077f, 0xc19e, 0x21, 0 - .dw 0x07c0, 0xc19e, 0x07ff, 0xc19e, 0x21, 0 - .dw 0x0840, 0xc19e, 0x087f, 0xc19e, 0x21, 0 - .dw 0x08c0, 0xc19e, 0x08ff, 0xc19e, 0x21, 0 - .dw 0x0940, 0xc19e, 0x097f, 0xc19e, 0x21, 0 - .dw 0x09c0, 0xc19e, 0x09ff, 0xc19e, 0x21, 0 - .dw 0x0a40, 0xc19e, 0x0a7f, 0xc19e, 0x21, 0 - .dw 0x0ac0, 0xc19e, 0x0aff, 0xc19e, 0x21, 0 - .dw 0x0b40, 0xc19e, 0x0b7f, 0xc19e, 0x21, 0 - .dw 0x0bc0, 0xc19e, 0x0bff, 0xc19e, 0x21, 0 - .dw 0x0c40, 0xc19e, 0x0c7f, 0xc19e, 0x21, 0 - .dw 0x0cc0, 0xc19e, 0x0cff, 0xc19e, 0x21, 0 - .dw 0x0d40, 0xc19e, 0x0d7f, 0xc19e, 0x21, 0 - .dw 0x0dc0, 0xc19e, 0x0dff, 0xc19e, 0x21, 0 - .dw 0x0e40, 0xc19e, 0x0e7f, 0xc19e, 0x21, 0 - .dw 0x0ec0, 0xc19e, 0x0eff, 0xc19e, 0x21, 0 - .dw 0x0f40, 0xc19e, 0x0f7f, 0xc19e, 0x21, 0 - .dw 0x0fc0, 0xc19e, 0x0fff, 0xc19e, 0x21, 0 - .dw 0x1040, 0xc19e, 0x107f, 0xc19e, 0x21, 0 - .dw 0x10c0, 0xc19e, 0x10ff, 0xc19e, 0x21, 0 - .dw 0x1140, 0xc19e, 0x117f, 0xc19e, 0x21, 0 - .dw 0x11c0, 0xc19e, 0x11ff, 0xc19e, 0x21, 0 - .dw 0x1240, 0xc19e, 0x127f, 0xc19e, 0x21, 0 - .dw 0x12c0, 0xc19e, 0x12ff, 0xc19e, 0x21, 0 - .dw 0x1340, 0xc19e, 0x137f, 0xc19e, 0x21, 0 - .dw 0x13c0, 0xc19e, 0x13ff, 0xc19e, 0x21, 0 - .dw 0x1440, 0xc19e, 0x147f, 0xc19e, 0x21, 0 - .dw 0x14c0, 0xc19e, 0x14ff, 0xc19e, 0x21, 0 - .dw 0x1540, 0xc19e, 0x157f, 0xc19e, 0x21, 0 - .dw 0x15c0, 0xc19e, 0x15ff, 0xc19e, 0x21, 0 - .dw 0x1640, 0xc19e, 0x167f, 0xc19e, 0x21, 0 - .dw 0x16c0, 0xc19e, 0x16ff, 0xc19e, 0x21, 0 - .dw 0x1740, 0xc19e, 0x177f, 0xc19e, 0x21, 0 - .dw 0x17c0, 0xc19e, 0x17ff, 0xc19e, 0x21, 0 - .dw 0x1840, 0xc19e, 0x187f, 0xc19e, 0x21, 0 - .dw 0x18c0, 0xc19e, 0x18ff, 0xc19e, 0x21, 0 - .dw 0x1940, 0xc19e, 0x197f, 0xc19e, 0x21, 0 - .dw 0x19c0, 0xc19e, 0x1fff, 0xc19e, 0x21, 0 - .dw 0x2040, 0xc19e, 0x207f, 0xc19e, 0x21, 0 - .dw 0x20c0, 0xc19e, 0x20ff, 0xc19e, 0x21, 0 - .dw 0x2140, 0xc19e, 0x217f, 0xc19e, 0x21, 0 - .dw 0x21c0, 0xc19e, 0x21ff, 0xc19e, 0x21, 0 - .dw 0x2240, 0xc19e, 0x227f, 0xc19e, 0x21, 0 - .dw 0x22c0, 0xc19e, 0x22ff, 0xc19e, 0x21, 0 - .dw 0x2340, 0xc19e, 0x237f, 0xc19e, 0x21, 0 - .dw 0x23c0, 0xc19e, 0x23ff, 0xc19e, 0x21, 0 - .dw 0x2440, 0xc19e, 0x247f, 0xc19e, 0x21, 0 - .dw 0x24c0, 0xc19e, 0x24ff, 0xc19e, 0x21, 0 - .dw 0x2540, 0xc19e, 0x257f, 0xc19e, 0x21, 0 - .dw 0x25c0, 0xc19e, 0x25ff, 0xc19e, 0x21, 0 - .dw 0x2640, 0xc19e, 0x267f, 0xc19e, 0x21, 0 - .dw 0x26c0, 0xc19e, 0x26ff, 0xc19e, 0x21, 0 - .dw 0x2740, 0xc19e, 0x277f, 0xc19e, 0x21, 0 - .dw 0x27c0, 0xc19e, 0x27ff, 0xc19e, 0x21, 0 - .dw 0x2840, 0xc19e, 0x287f, 0xc19e, 0x21, 0 - .dw 0x28c0, 0xc19e, 0x28ff, 0xc19e, 0x21, 0 - .dw 0x2940, 0xc19e, 0x297f, 0xc19e, 0x21, 0 - .dw 0x29c0, 0xc19e, 0x29ff, 0xc19e, 0x21, 0 - .dw 0x2a40, 0xc19e, 0x2a7f, 0xc19e, 0x21, 0 - .dw 0x2ac0, 0xc19e, 0x2aff, 0xc19e, 0x21, 0 - .dw 0x2b40, 0xc19e, 0x2b7f, 0xc19e, 0x21, 0 - .dw 0x2bc0, 0xc19e, 0x2bff, 0xc19e, 0x21, 0 - .dw 0x2c40, 0xc19e, 0x2c7f, 0xc19e, 0x21, 0 - .dw 0x2cc0, 0xc19e, 0x2cff, 0xc19e, 0x21, 0 - .dw 0x2d40, 0xc19e, 0x2d7f, 0xc19e, 0x21, 0 - .dw 0x2dc0, 0xc19e, 0x2dff, 0xc19e, 0x21, 0 - .dw 0x2e40, 0xc19e, 0x2e7f, 0xc19e, 0x21, 0 - .dw 0x2ec0, 0xc19e, 0x2eff, 0xc19e, 0x21, 0 - .dw 0x2f40, 0xc19e, 0x2f7f, 0xc19e, 0x21, 0 - .dw 0x2fc0, 0xc19e, 0x2fff, 0xc19e, 0x21, 0 - .dw 0x3040, 0xc19e, 0x307f, 0xc19e, 0x21, 0 - .dw 0x30c0, 0xc19e, 0x30ff, 0xc19e, 0x21, 0 - .dw 0x3140, 0xc19e, 0x317f, 0xc19e, 0x21, 0 - .dw 0x31c0, 0xc19e, 0x31ff, 0xc19e, 0x21, 0 - .dw 0x3240, 0xc19e, 0x327f, 0xc19e, 0x21, 0 - .dw 0x32c0, 0xc19e, 0x32ff, 0xc19e, 0x21, 0 - .dw 0x3340, 0xc19e, 0x337f, 0xc19e, 0x21, 0 - .dw 0x33c0, 0xc19e, 0x33ff, 0xc19e, 0x21, 0 - .dw 0x3440, 0xc19e, 0x347f, 0xc19e, 0x21, 0 - .dw 0x34c0, 0xc19e, 0x34ff, 0xc19e, 0x21, 0 - .dw 0x3540, 0xc19e, 0x357f, 0xc19e, 0x21, 0 - .dw 0x35c0, 0xc19e, 0x35ff, 0xc19e, 0x21, 0 - .dw 0x3640, 0xc19e, 0x367f, 0xc19e, 0x21, 0 - .dw 0x36c0, 0xc19e, 0x36ff, 0xc19e, 0x21, 0 - .dw 0x3740, 0xc19e, 0x377f, 0xc19e, 0x21, 0 - .dw 0x37c0, 0xc19e, 0x37ff, 0xc19e, 0x21, 0 - .dw 0x3840, 0xc19e, 0x387f, 0xc19e, 0x21, 0 - .dw 0x38c0, 0xc19e, 0x38ff, 0xc19e, 0x21, 0 - .dw 0x3940, 0xc19e, 0x397f, 0xc19e, 0x21, 0 - .dw 0x39c0, 0xc19e, 0x3fff, 0xc19e, 0x21, 0 - .dw 0x4040, 0xc19e, 0x407f, 0xc19e, 0x21, 0 - .dw 0x40c0, 0xc19e, 0x40ff, 0xc19e, 0x21, 0 - .dw 0x4140, 0xc19e, 0x417f, 0xc19e, 0x21, 0 - .dw 0x41c0, 0xc19e, 0x41ff, 0xc19e, 0x21, 0 - .dw 0x4240, 0xc19e, 0x427f, 0xc19e, 0x21, 0 - .dw 0x42c0, 0xc19e, 0x42ff, 0xc19e, 0x21, 0 - .dw 0x4340, 0xc19e, 0x437f, 0xc19e, 0x21, 0 - .dw 0x43c0, 0xc19e, 0x43ff, 0xc19e, 0x21, 0 - .dw 0x4440, 0xc19e, 0x447f, 0xc19e, 0x21, 0 - .dw 0x44c0, 0xc19e, 0x44ff, 0xc19e, 0x21, 0 - .dw 0x4540, 0xc19e, 0x457f, 0xc19e, 0x21, 0 - .dw 0x45c0, 0xc19e, 0x45ff, 0xc19e, 0x21, 0 - .dw 0x4640, 0xc19e, 0x467f, 0xc19e, 0x21, 0 - .dw 0x46c0, 0xc19e, 0x46ff, 0xc19e, 0x21, 0 - .dw 0x4740, 0xc19e, 0x477f, 0xc19e, 0x21, 0 - .dw 0x47c0, 0xc19e, 0x47ff, 0xc19e, 0x21, 0 - .dw 0x4840, 0xc19e, 0x487f, 0xc19e, 0x21, 0 - .dw 0x48c0, 0xc19e, 0x48ff, 0xc19e, 0x21, 0 - .dw 0x4940, 0xc19e, 0x497f, 0xc19e, 0x21, 0 - .dw 0x49c0, 0xc19e, 0x49ff, 0xc19e, 0x21, 0 - .dw 0x4a40, 0xc19e, 0x4a7f, 0xc19e, 0x21, 0 - .dw 0x4ac0, 0xc19e, 0x4aff, 0xc19e, 0x21, 0 - .dw 0x4b40, 0xc19e, 0x4b7f, 0xc19e, 0x21, 0 - .dw 0x4bc0, 0xc19e, 0x4bff, 0xc19e, 0x21, 0 - .dw 0x4c40, 0xc19e, 0x4c7f, 0xc19e, 0x21, 0 - .dw 0x4cc0, 0xc19e, 0x4cff, 0xc19e, 0x21, 0 - .dw 0x4d40, 0xc19e, 0x4d7f, 0xc19e, 0x21, 0 - .dw 0x4dc0, 0xc19e, 0x4dff, 0xc19e, 0x21, 0 - .dw 0x4e40, 0xc19e, 0x4e7f, 0xc19e, 0x21, 0 - .dw 0x4ec0, 0xc19e, 0x4eff, 0xc19e, 0x21, 0 - .dw 0x4f40, 0xc19e, 0x4f7f, 0xc19e, 0x21, 0 - .dw 0x4fc0, 0xc19e, 0x4fff, 0xc19e, 0x21, 0 - .dw 0x5040, 0xc19e, 0x507f, 0xc19e, 0x21, 0 - .dw 0x50c0, 0xc19e, 0x50ff, 0xc19e, 0x21, 0 - .dw 0x5140, 0xc19e, 0x517f, 0xc19e, 0x21, 0 - .dw 0x51c0, 0xc19e, 0x51ff, 0xc19e, 0x21, 0 - .dw 0x5240, 0xc19e, 0x527f, 0xc19e, 0x21, 0 - .dw 0x52c0, 0xc19e, 0x52ff, 0xc19e, 0x21, 0 - .dw 0x5340, 0xc19e, 0x537f, 0xc19e, 0x21, 0 - .dw 0x53c0, 0xc19e, 0x53ff, 0xc19e, 0x21, 0 - .dw 0x5440, 0xc19e, 0x547f, 0xc19e, 0x21, 0 - .dw 0x54c0, 0xc19e, 0x54ff, 0xc19e, 0x21, 0 - .dw 0x5540, 0xc19e, 0x557f, 0xc19e, 0x21, 0 - .dw 0x55c0, 0xc19e, 0x55ff, 0xc19e, 0x21, 0 - .dw 0x5640, 0xc19e, 0x567f, 0xc19e, 0x21, 0 - .dw 0x56c0, 0xc19e, 0x56ff, 0xc19e, 0x21, 0 - .dw 0x5740, 0xc19e, 0x577f, 0xc19e, 0x21, 0 - .dw 0x57c0, 0xc19e, 0x57ff, 0xc19e, 0x21, 0 - .dw 0x5840, 0xc19e, 0x587f, 0xc19e, 0x21, 0 - .dw 0x58c0, 0xc19e, 0x58ff, 0xc19e, 0x21, 0 - .dw 0x5940, 0xc19e, 0x597f, 0xc19e, 0x21, 0 - .dw 0x59c0, 0xc19e, 0x5fff, 0xc19e, 0x21, 0 - .dw 0x6040, 0xc19e, 0x607f, 0xc19e, 0x21, 0 - .dw 0x60c0, 0xc19e, 0x60ff, 0xc19e, 0x21, 0 - .dw 0x6140, 0xc19e, 0x617f, 0xc19e, 0x21, 0 - .dw 0x61c0, 0xc19e, 0x61ff, 0xc19e, 0x21, 0 - .dw 0x6240, 0xc19e, 0x627f, 0xc19e, 0x21, 0 - .dw 0x62c0, 0xc19e, 0x62ff, 0xc19e, 0x21, 0 - .dw 0x6340, 0xc19e, 0x637f, 0xc19e, 0x21, 0 - .dw 0x63c0, 0xc19e, 0x63ff, 0xc19e, 0x21, 0 - .dw 0x6440, 0xc19e, 0x647f, 0xc19e, 0x21, 0 - .dw 0x64c0, 0xc19e, 0x64ff, 0xc19e, 0x21, 0 - .dw 0x6540, 0xc19e, 0x657f, 0xc19e, 0x21, 0 - .dw 0x65c0, 0xc19e, 0x65ff, 0xc19e, 0x21, 0 - .dw 0x6640, 0xc19e, 0x667f, 0xc19e, 0x21, 0 - .dw 0x66c0, 0xc19e, 0x66ff, 0xc19e, 0x21, 0 - .dw 0x6740, 0xc19e, 0x677f, 0xc19e, 0x21, 0 - .dw 0x67c0, 0xc19e, 0x67ff, 0xc19e, 0x21, 0 - .dw 0x6840, 0xc19e, 0x687f, 0xc19e, 0x21, 0 - .dw 0x68c0, 0xc19e, 0x68ff, 0xc19e, 0x21, 0 - .dw 0x6940, 0xc19e, 0x697f, 0xc19e, 0x21, 0 - .dw 0x69c0, 0xc19e, 0x69ff, 0xc19e, 0x21, 0 - .dw 0x6a40, 0xc19e, 0x6a7f, 0xc19e, 0x21, 0 - .dw 0x6ac0, 0xc19e, 0x6aff, 0xc19e, 0x21, 0 - .dw 0x6b40, 0xc19e, 0x6b7f, 0xc19e, 0x21, 0 - .dw 0x6bc0, 0xc19e, 0x6bff, 0xc19e, 0x21, 0 - .dw 0x6c40, 0xc19e, 0x6c7f, 0xc19e, 0x21, 0 - .dw 0x6cc0, 0xc19e, 0x6cff, 0xc19e, 0x21, 0 - .dw 0x6d40, 0xc19e, 0x6d7f, 0xc19e, 0x21, 0 - .dw 0x6dc0, 0xc19e, 0x6dff, 0xc19e, 0x21, 0 - .dw 0x6e40, 0xc19e, 0x6e7f, 0xc19e, 0x21, 0 - .dw 0x6ec0, 0xc19e, 0x6eff, 0xc19e, 0x21, 0 - .dw 0x6f40, 0xc19e, 0x6f7f, 0xc19e, 0x21, 0 - .dw 0x6fc0, 0xc19e, 0x6fff, 0xc19e, 0x21, 0 - .dw 0x7040, 0xc19e, 0x707f, 0xc19e, 0x21, 0 - .dw 0x70c0, 0xc19e, 0x70ff, 0xc19e, 0x21, 0 - .dw 0x7140, 0xc19e, 0x717f, 0xc19e, 0x21, 0 - .dw 0x71c0, 0xc19e, 0x71ff, 0xc19e, 0x21, 0 - .dw 0x7240, 0xc19e, 0x727f, 0xc19e, 0x21, 0 - .dw 0x72c0, 0xc19e, 0x72ff, 0xc19e, 0x21, 0 - .dw 0x7340, 0xc19e, 0x737f, 0xc19e, 0x21, 0 - .dw 0x73c0, 0xc19e, 0x73ff, 0xc19e, 0x21, 0 - .dw 0x7440, 0xc19e, 0x747f, 0xc19e, 0x21, 0 - .dw 0x74c0, 0xc19e, 0x74ff, 0xc19e, 0x21, 0 - .dw 0x7540, 0xc19e, 0x757f, 0xc19e, 0x21, 0 - .dw 0x75c0, 0xc19e, 0x75ff, 0xc19e, 0x21, 0 - .dw 0x7640, 0xc19e, 0x767f, 0xc19e, 0x21, 0 - .dw 0x76c0, 0xc19e, 0x76ff, 0xc19e, 0x21, 0 - .dw 0x7740, 0xc19e, 0x777f, 0xc19e, 0x21, 0 - .dw 0x77c0, 0xc19e, 0x77ff, 0xc19e, 0x21, 0 - .dw 0x7840, 0xc19e, 0x787f, 0xc19e, 0x21, 0 - .dw 0x78c0, 0xc19e, 0x78ff, 0xc19e, 0x21, 0 - .dw 0x7940, 0xc19e, 0x797f, 0xc19e, 0x21, 0 - .dw 0x79c0, 0xc19e, 0x7fff, 0xc19e, 0x21, 0 - .dw 0x8040, 0xc19e, 0x807f, 0xc19e, 0x21, 0 - .dw 0x80c0, 0xc19e, 0x80ff, 0xc19e, 0x21, 0 - .dw 0x8140, 0xc19e, 0x817f, 0xc19e, 0x21, 0 - .dw 0x81c0, 0xc19e, 0x81ff, 0xc19e, 0x21, 0 - .dw 0x8240, 0xc19e, 0x827f, 0xc19e, 0x21, 0 - .dw 0x82c0, 0xc19e, 0x82ff, 0xc19e, 0x21, 0 - .dw 0x8340, 0xc19e, 0x837f, 0xc19e, 0x21, 0 - .dw 0x83c0, 0xc19e, 0x83ff, 0xc19e, 0x21, 0 - .dw 0x8440, 0xc19e, 0x847f, 0xc19e, 0x21, 0 - .dw 0x84c0, 0xc19e, 0x84ff, 0xc19e, 0x21, 0 - .dw 0x8540, 0xc19e, 0x857f, 0xc19e, 0x21, 0 - .dw 0x85c0, 0xc19e, 0x85ff, 0xc19e, 0x21, 0 - .dw 0x8640, 0xc19e, 0x867f, 0xc19e, 0x21, 0 - .dw 0x86c0, 0xc19e, 0x86ff, 0xc19e, 0x21, 0 - .dw 0x8740, 0xc19e, 0x877f, 0xc19e, 0x21, 0 - .dw 0x87c0, 0xc19e, 0x87ff, 0xc19e, 0x21, 0 - .dw 0x8840, 0xc19e, 0x887f, 0xc19e, 0x21, 0 - .dw 0x88c0, 0xc19e, 0x88ff, 0xc19e, 0x21, 0 - .dw 0x8940, 0xc19e, 0x897f, 0xc19e, 0x21, 0 - .dw 0x89c0, 0xc19e, 0x89ff, 0xc19e, 0x21, 0 - .dw 0x8a40, 0xc19e, 0x8a7f, 0xc19e, 0x21, 0 - .dw 0x8ac0, 0xc19e, 0x8aff, 0xc19e, 0x21, 0 - .dw 0x8b40, 0xc19e, 0x8b7f, 0xc19e, 0x21, 0 - .dw 0x8bc0, 0xc19e, 0x8bff, 0xc19e, 0x21, 0 - .dw 0x8c40, 0xc19e, 0x8c7f, 0xc19e, 0x21, 0 - .dw 0x8cc0, 0xc19e, 0x8cff, 0xc19e, 0x21, 0 - .dw 0x8d40, 0xc19e, 0x8d7f, 0xc19e, 0x21, 0 - .dw 0x8dc0, 0xc19e, 0x8dff, 0xc19e, 0x21, 0 - .dw 0x8e40, 0xc19e, 0x8e7f, 0xc19e, 0x21, 0 - .dw 0x8ec0, 0xc19e, 0x8eff, 0xc19e, 0x21, 0 - .dw 0x8f40, 0xc19e, 0x8f7f, 0xc19e, 0x21, 0 - .dw 0x8fc0, 0xc19e, 0x8fff, 0xc19e, 0x21, 0 - .dw 0x9040, 0xc19e, 0x907f, 0xc19e, 0x21, 0 - .dw 0x90c0, 0xc19e, 0x90ff, 0xc19e, 0x21, 0 - .dw 0x9140, 0xc19e, 0x917f, 0xc19e, 0x21, 0 - .dw 0x91c0, 0xc19e, 0x91ff, 0xc19e, 0x21, 0 - .dw 0x9240, 0xc19e, 0x927f, 0xc19e, 0x21, 0 - .dw 0x92c0, 0xc19e, 0x92ff, 0xc19e, 0x21, 0 - .dw 0x9340, 0xc19e, 0x937f, 0xc19e, 0x21, 0 - .dw 0x93c0, 0xc19e, 0x93ff, 0xc19e, 0x21, 0 - .dw 0x9440, 0xc19e, 0x947f, 0xc19e, 0x21, 0 - .dw 0x94c0, 0xc19e, 0x94ff, 0xc19e, 0x21, 0 - .dw 0x9540, 0xc19e, 0x957f, 0xc19e, 0x21, 0 - .dw 0x95c0, 0xc19e, 0x95ff, 0xc19e, 0x21, 0 - .dw 0x9640, 0xc19e, 0x967f, 0xc19e, 0x21, 0 - .dw 0x96c0, 0xc19e, 0x96ff, 0xc19e, 0x21, 0 - .dw 0x9740, 0xc19e, 0x977f, 0xc19e, 0x21, 0 - .dw 0x97c0, 0xc19e, 0x97ff, 0xc19e, 0x21, 0 - .dw 0x9840, 0xc19e, 0x987f, 0xc19e, 0x21, 0 - .dw 0x98c0, 0xc19e, 0x98ff, 0xc19e, 0x21, 0 - .dw 0x9940, 0xc19e, 0x997f, 0xc19e, 0x21, 0 - .dw 0x99c0, 0xc19e, 0x9fff, 0xc19e, 0x21, 0 - .dw 0xa040, 0xc19e, 0xa07f, 0xc19e, 0x21, 0 - .dw 0xa0c0, 0xc19e, 0xa0ff, 0xc19e, 0x21, 0 - .dw 0xa140, 0xc19e, 0xa17f, 0xc19e, 0x21, 0 - .dw 0xa1c0, 0xc19e, 0xa1ff, 0xc19e, 0x21, 0 - .dw 0xa240, 0xc19e, 0xa27f, 0xc19e, 0x21, 0 - .dw 0xa2c0, 0xc19e, 0xa2ff, 0xc19e, 0x21, 0 - .dw 0xa340, 0xc19e, 0xa37f, 0xc19e, 0x21, 0 - .dw 0xa3c0, 0xc19e, 0xa3ff, 0xc19e, 0x21, 0 - .dw 0xa440, 0xc19e, 0xa47f, 0xc19e, 0x21, 0 - .dw 0xa4c0, 0xc19e, 0xa4ff, 0xc19e, 0x21, 0 - .dw 0xa540, 0xc19e, 0xa57f, 0xc19e, 0x21, 0 - .dw 0xa5c0, 0xc19e, 0xa5ff, 0xc19e, 0x21, 0 - .dw 0xa640, 0xc19e, 0xa67f, 0xc19e, 0x21, 0 - .dw 0xa6c0, 0xc19e, 0xa6ff, 0xc19e, 0x21, 0 - .dw 0xa740, 0xc19e, 0xa77f, 0xc19e, 0x21, 0 - .dw 0xa7c0, 0xc19e, 0xa7ff, 0xc19e, 0x21, 0 - .dw 0xa840, 0xc19e, 0xa87f, 0xc19e, 0x21, 0 - .dw 0xa8c0, 0xc19e, 0xa8ff, 0xc19e, 0x21, 0 - .dw 0xa940, 0xc19e, 0xa97f, 0xc19e, 0x21, 0 - .dw 0xa9c0, 0xc19e, 0xa9ff, 0xc19e, 0x21, 0 - .dw 0xaa40, 0xc19e, 0xaa7f, 0xc19e, 0x21, 0 - .dw 0xaac0, 0xc19e, 0xaaff, 0xc19e, 0x21, 0 - .dw 0xab40, 0xc19e, 0xab7f, 0xc19e, 0x21, 0 - .dw 0xabc0, 0xc19e, 0xabff, 0xc19e, 0x21, 0 - .dw 0xac40, 0xc19e, 0xac7f, 0xc19e, 0x21, 0 - .dw 0xacc0, 0xc19e, 0xacff, 0xc19e, 0x21, 0 - .dw 0xad40, 0xc19e, 0xad7f, 0xc19e, 0x21, 0 - .dw 0xadc0, 0xc19e, 0xadff, 0xc19e, 0x21, 0 - .dw 0xae40, 0xc19e, 0xae7f, 0xc19e, 0x21, 0 - .dw 0xaec0, 0xc19e, 0xaeff, 0xc19e, 0x21, 0 - .dw 0xaf40, 0xc19e, 0xaf7f, 0xc19e, 0x21, 0 - .dw 0xafc0, 0xc19e, 0xafff, 0xc19e, 0x21, 0 - .dw 0xb040, 0xc19e, 0xb07f, 0xc19e, 0x21, 0 - .dw 0xb0c0, 0xc19e, 0xb0ff, 0xc19e, 0x21, 0 - .dw 0xb140, 0xc19e, 0xb17f, 0xc19e, 0x21, 0 - .dw 0xb1c0, 0xc19e, 0xb1ff, 0xc19e, 0x21, 0 - .dw 0xb240, 0xc19e, 0xb27f, 0xc19e, 0x21, 0 - .dw 0xb2c0, 0xc19e, 0xb2ff, 0xc19e, 0x21, 0 - .dw 0xb340, 0xc19e, 0xb37f, 0xc19e, 0x21, 0 - .dw 0xb3c0, 0xc19e, 0xb3ff, 0xc19e, 0x21, 0 - .dw 0xb440, 0xc19e, 0xb47f, 0xc19e, 0x21, 0 - .dw 0xb4c0, 0xc19e, 0xb4ff, 0xc19e, 0x21, 0 - .dw 0xb540, 0xc19e, 0xb57f, 0xc19e, 0x21, 0 - .dw 0xb5c0, 0xc19e, 0xb5ff, 0xc19e, 0x21, 0 - .dw 0xb640, 0xc19e, 0xb67f, 0xc19e, 0x21, 0 - .dw 0xb6c0, 0xc19e, 0xb6ff, 0xc19e, 0x21, 0 - .dw 0xb740, 0xc19e, 0xb77f, 0xc19e, 0x21, 0 - .dw 0xb7c0, 0xc19e, 0xb7ff, 0xc19e, 0x21, 0 - .dw 0xb840, 0xc19e, 0xb87f, 0xc19e, 0x21, 0 - .dw 0xb8c0, 0xc19e, 0xb8ff, 0xc19e, 0x21, 0 - .dw 0xb940, 0xc19e, 0xb97f, 0xc19e, 0x21, 0 - .dw 0xb9c0, 0xc19e, 0xbfff, 0xc19e, 0x21, 0 - .dw 0xc040, 0xc19e, 0xc07f, 0xc19e, 0x21, 0 - .dw 0xc0c0, 0xc19e, 0xc0ff, 0xc19e, 0x21, 0 - .dw 0xc140, 0xc19e, 0xc17f, 0xc19e, 0x21, 0 - .dw 0xc1c0, 0xc19e, 0xc1ff, 0xc19e, 0x21, 0 - .dw 0xc240, 0xc19e, 0xc27f, 0xc19e, 0x21, 0 - .dw 0xc2c0, 0xc19e, 0xc2ff, 0xc19e, 0x21, 0 - .dw 0xc340, 0xc19e, 0xc37f, 0xc19e, 0x21, 0 - .dw 0xc3c0, 0xc19e, 0xc3ff, 0xc19e, 0x21, 0 - .dw 0xc440, 0xc19e, 0xc47f, 0xc19e, 0x21, 0 - .dw 0xc4c0, 0xc19e, 0xc4ff, 0xc19e, 0x21, 0 - .dw 0xc540, 0xc19e, 0xc57f, 0xc19e, 0x21, 0 - .dw 0xc5c0, 0xc19e, 0xc5ff, 0xc19e, 0x21, 0 - .dw 0xc640, 0xc19e, 0xc67f, 0xc19e, 0x21, 0 - .dw 0xc6c0, 0xc19e, 0xc6ff, 0xc19e, 0x21, 0 - .dw 0xc740, 0xc19e, 0xc77f, 0xc19e, 0x21, 0 - .dw 0xc7c0, 0xc19e, 0xc7ff, 0xc19e, 0x21, 0 - .dw 0xc840, 0xc19e, 0xc87f, 0xc19e, 0x21, 0 - .dw 0xc8c0, 0xc19e, 0xc8ff, 0xc19e, 0x21, 0 - .dw 0xc940, 0xc19e, 0xc97f, 0xc19e, 0x21, 0 - .dw 0xc9c0, 0xc19e, 0xc9ff, 0xc19e, 0x21, 0 - .dw 0xca40, 0xc19e, 0xca7f, 0xc19e, 0x21, 0 - .dw 0xcac0, 0xc19e, 0xcaff, 0xc19e, 0x21, 0 - .dw 0xcb40, 0xc19e, 0xcb7f, 0xc19e, 0x21, 0 - .dw 0xcbc0, 0xc19e, 0xcbff, 0xc19e, 0x21, 0 - .dw 0xcc40, 0xc19e, 0xcc7f, 0xc19e, 0x21, 0 - .dw 0xccc0, 0xc19e, 0xccff, 0xc19e, 0x21, 0 - .dw 0xcd40, 0xc19e, 0xcd7f, 0xc19e, 0x21, 0 - .dw 0xcdc0, 0xc19e, 0xcdff, 0xc19e, 0x21, 0 - .dw 0xce40, 0xc19e, 0xce7f, 0xc19e, 0x21, 0 - .dw 0xcec0, 0xc19e, 0xceff, 0xc19e, 0x21, 0 - .dw 0xcf40, 0xc19e, 0xcf7f, 0xc19e, 0x21, 0 - .dw 0xcfc0, 0xc19e, 0xcfff, 0xc19e, 0x21, 0 - .dw 0xd040, 0xc19e, 0xd07f, 0xc19e, 0x21, 0 - .dw 0xd0c0, 0xc19e, 0xd0ff, 0xc19e, 0x21, 0 - .dw 0xd140, 0xc19e, 0xd17f, 0xc19e, 0x21, 0 - .dw 0xd1c0, 0xc19e, 0xd1ff, 0xc19e, 0x21, 0 - .dw 0xd240, 0xc19e, 0xd27f, 0xc19e, 0x21, 0 - .dw 0xd2c0, 0xc19e, 0xd2ff, 0xc19e, 0x21, 0 - .dw 0xd340, 0xc19e, 0xd37f, 0xc19e, 0x21, 0 - .dw 0xd3c0, 0xc19e, 0xd3ff, 0xc19e, 0x21, 0 - .dw 0xd440, 0xc19e, 0xd47f, 0xc19e, 0x21, 0 - .dw 0xd4c0, 0xc19e, 0xd4ff, 0xc19e, 0x21, 0 - .dw 0xd540, 0xc19e, 0xd57f, 0xc19e, 0x21, 0 - .dw 0xd5c0, 0xc19e, 0xd5ff, 0xc19e, 0x21, 0 - .dw 0xd640, 0xc19e, 0xd67f, 0xc19e, 0x21, 0 - .dw 0xd6c0, 0xc19e, 0xd6ff, 0xc19e, 0x21, 0 - .dw 0xd740, 0xc19e, 0xd77f, 0xc19e, 0x21, 0 - .dw 0xd7c0, 0xc19e, 0xd7ff, 0xc19e, 0x21, 0 - .dw 0xd840, 0xc19e, 0xd87f, 0xc19e, 0x21, 0 - .dw 0xd8c0, 0xc19e, 0xd8ff, 0xc19e, 0x21, 0 - .dw 0xd940, 0xc19e, 0xd97f, 0xc19e, 0x21, 0 - .dw 0xd9c0, 0xc19e, 0xdfff, 0xc19e, 0x21, 0 - .dw 0xe040, 0xc19e, 0xe07f, 0xc19e, 0x21, 0 - .dw 0xe0c0, 0xc19e, 0xe0ff, 0xc19e, 0x21, 0 - .dw 0xe140, 0xc19e, 0xe17f, 0xc19e, 0x21, 0 - .dw 0xe1c0, 0xc19e, 0xe1ff, 0xc19e, 0x21, 0 - .dw 0xe240, 0xc19e, 0xe27f, 0xc19e, 0x21, 0 - .dw 0xe2c0, 0xc19e, 0xe2ff, 0xc19e, 0x21, 0 - .dw 0xe340, 0xc19e, 0xe37f, 0xc19e, 0x21, 0 - .dw 0xe3c0, 0xc19e, 0xe3ff, 0xc19e, 0x21, 0 - .dw 0xe440, 0xc19e, 0xe47f, 0xc19e, 0x21, 0 - .dw 0xe4c0, 0xc19e, 0xe4ff, 0xc19e, 0x21, 0 - .dw 0xe540, 0xc19e, 0xe57f, 0xc19e, 0x21, 0 - .dw 0xe5c0, 0xc19e, 0xe5ff, 0xc19e, 0x21, 0 - .dw 0xe640, 0xc19e, 0xe67f, 0xc19e, 0x21, 0 - .dw 0xe6c0, 0xc19e, 0xe6ff, 0xc19e, 0x21, 0 - .dw 0xe740, 0xc19e, 0xe77f, 0xc19e, 0x21, 0 - .dw 0xe7c0, 0xc19e, 0xe7ff, 0xc19e, 0x21, 0 - .dw 0xe840, 0xc19e, 0xe87f, 0xc19e, 0x21, 0 - .dw 0xe8c0, 0xc19e, 0xe8ff, 0xc19e, 0x21, 0 - .dw 0xe940, 0xc19e, 0xe97f, 0xc19e, 0x21, 0 - .dw 0xe9c0, 0xc19e, 0xe9ff, 0xc19e, 0x21, 0 - .dw 0xea40, 0xc19e, 0xea7f, 0xc19e, 0x21, 0 - .dw 0xeac0, 0xc19e, 0xeaff, 0xc19e, 0x21, 0 - .dw 0xeb40, 0xc19e, 0xeb7f, 0xc19e, 0x21, 0 - .dw 0xebc0, 0xc19e, 0xebff, 0xc19e, 0x21, 0 - .dw 0xec40, 0xc19e, 0xec7f, 0xc19e, 0x21, 0 - .dw 0xecc0, 0xc19e, 0xecff, 0xc19e, 0x21, 0 - .dw 0xed40, 0xc19e, 0xed7f, 0xc19e, 0x21, 0 - .dw 0xedc0, 0xc19e, 0xedff, 0xc19e, 0x21, 0 - .dw 0xee40, 0xc19e, 0xee7f, 0xc19e, 0x21, 0 - .dw 0xeec0, 0xc19e, 0xeeff, 0xc19e, 0x21, 0 - .dw 0xef40, 0xc19e, 0xef7f, 0xc19e, 0x21, 0 - .dw 0xefc0, 0xc19e, 0xefff, 0xc19e, 0x21, 0 - .dw 0xf040, 0xc19e, 0xf07f, 0xc19e, 0x21, 0 - .dw 0xf0c0, 0xc19e, 0xf0ff, 0xc19e, 0x21, 0 - .dw 0xf140, 0xc19e, 0xf17f, 0xc19e, 0x21, 0 - .dw 0xf1c0, 0xc19e, 0xf1ff, 0xc19e, 0x21, 0 - .dw 0xf240, 0xc19e, 0xf27f, 0xc19e, 0x21, 0 - .dw 0xf2c0, 0xc19e, 0xf2ff, 0xc19e, 0x21, 0 - .dw 0xf340, 0xc19e, 0xf37f, 0xc19e, 0x21, 0 - .dw 0xf3c0, 0xc19e, 0xf3ff, 0xc19e, 0x21, 0 - .dw 0xf440, 0xc19e, 0xf47f, 0xc19e, 0x21, 0 - .dw 0xf4c0, 0xc19e, 0xf4ff, 0xc19e, 0x21, 0 - .dw 0xf540, 0xc19e, 0xf57f, 0xc19e, 0x21, 0 - .dw 0xf5c0, 0xc19e, 0xf5ff, 0xc19e, 0x21, 0 - .dw 0xf640, 0xc19e, 0xf67f, 0xc19e, 0x21, 0 - .dw 0xf6c0, 0xc19e, 0xf6ff, 0xc19e, 0x21, 0 - .dw 0xf740, 0xc19e, 0xf77f, 0xc19e, 0x21, 0 - .dw 0xf7c0, 0xc19e, 0xf7ff, 0xc19e, 0x21, 0 - .dw 0xf840, 0xc19e, 0xf87f, 0xc19e, 0x21, 0 - .dw 0xf8c0, 0xc19e, 0xf8ff, 0xc19e, 0x21, 0 - .dw 0xf940, 0xc19e, 0xf97f, 0xc19e, 0x21, 0 - .dw 0xf9c0, 0xc19e, 0xffff, 0xc19e, 0x21, 0 - .dw 0x0040, 0xc19f, 0x007f, 0xc19f, 0x21, 0 - .dw 0x00c0, 0xc19f, 0x00ff, 0xc19f, 0x21, 0 - .dw 0x0140, 0xc19f, 0x017f, 0xc19f, 0x21, 0 - .dw 0x01c0, 0xc19f, 0x01ff, 0xc19f, 0x21, 0 - .dw 0x0240, 0xc19f, 0x027f, 0xc19f, 0x21, 0 - .dw 0x02c0, 0xc19f, 0x02ff, 0xc19f, 0x21, 0 - .dw 0x0340, 0xc19f, 0x037f, 0xc19f, 0x21, 0 - .dw 0x03c0, 0xc19f, 0x03ff, 0xc19f, 0x21, 0 - .dw 0x0440, 0xc19f, 0x047f, 0xc19f, 0x21, 0 - .dw 0x04c0, 0xc19f, 0x04ff, 0xc19f, 0x21, 0 - .dw 0x0540, 0xc19f, 0x057f, 0xc19f, 0x21, 0 - .dw 0x05c0, 0xc19f, 0x05ff, 0xc19f, 0x21, 0 - .dw 0x0640, 0xc19f, 0x067f, 0xc19f, 0x21, 0 - .dw 0x06c0, 0xc19f, 0x06ff, 0xc19f, 0x21, 0 - .dw 0x0740, 0xc19f, 0x077f, 0xc19f, 0x21, 0 - .dw 0x07c0, 0xc19f, 0x07ff, 0xc19f, 0x21, 0 - .dw 0x0840, 0xc19f, 0x087f, 0xc19f, 0x21, 0 - .dw 0x08c0, 0xc19f, 0x08ff, 0xc19f, 0x21, 0 - .dw 0x0940, 0xc19f, 0x097f, 0xc19f, 0x21, 0 - .dw 0x09c0, 0xc19f, 0x09ff, 0xc19f, 0x21, 0 - .dw 0x0a40, 0xc19f, 0x0a7f, 0xc19f, 0x21, 0 - .dw 0x0ac0, 0xc19f, 0x0aff, 0xc19f, 0x21, 0 - .dw 0x0b40, 0xc19f, 0x0b7f, 0xc19f, 0x21, 0 - .dw 0x0bc0, 0xc19f, 0x0bff, 0xc19f, 0x21, 0 - .dw 0x0c40, 0xc19f, 0x0c7f, 0xc19f, 0x21, 0 - .dw 0x0cc0, 0xc19f, 0x0cff, 0xc19f, 0x21, 0 - .dw 0x0d40, 0xc19f, 0x0d7f, 0xc19f, 0x21, 0 - .dw 0x0dc0, 0xc19f, 0x0dff, 0xc19f, 0x21, 0 - .dw 0x0e40, 0xc19f, 0x0e7f, 0xc19f, 0x21, 0 - .dw 0x0ec0, 0xc19f, 0x0eff, 0xc19f, 0x21, 0 - .dw 0x0f40, 0xc19f, 0x0f7f, 0xc19f, 0x21, 0 - .dw 0x0fc0, 0xc19f, 0x0fff, 0xc19f, 0x21, 0 - .dw 0x1040, 0xc19f, 0x107f, 0xc19f, 0x21, 0 - .dw 0x10c0, 0xc19f, 0x10ff, 0xc19f, 0x21, 0 - .dw 0x1140, 0xc19f, 0x117f, 0xc19f, 0x21, 0 - .dw 0x11c0, 0xc19f, 0x11ff, 0xc19f, 0x21, 0 - .dw 0x1240, 0xc19f, 0x127f, 0xc19f, 0x21, 0 - .dw 0x12c0, 0xc19f, 0x12ff, 0xc19f, 0x21, 0 - .dw 0x1340, 0xc19f, 0x137f, 0xc19f, 0x21, 0 - .dw 0x13c0, 0xc19f, 0x13ff, 0xc19f, 0x21, 0 - .dw 0x1440, 0xc19f, 0x147f, 0xc19f, 0x21, 0 - .dw 0x14c0, 0xc19f, 0x14ff, 0xc19f, 0x21, 0 - .dw 0x1540, 0xc19f, 0x157f, 0xc19f, 0x21, 0 - .dw 0x15c0, 0xc19f, 0x15ff, 0xc19f, 0x21, 0 - .dw 0x1640, 0xc19f, 0x167f, 0xc19f, 0x21, 0 - .dw 0x16c0, 0xc19f, 0x16ff, 0xc19f, 0x21, 0 - .dw 0x1740, 0xc19f, 0x177f, 0xc19f, 0x21, 0 - .dw 0x17c0, 0xc19f, 0x17ff, 0xc19f, 0x21, 0 - .dw 0x1840, 0xc19f, 0x187f, 0xc19f, 0x21, 0 - .dw 0x18c0, 0xc19f, 0x18ff, 0xc19f, 0x21, 0 - .dw 0x1940, 0xc19f, 0x197f, 0xc19f, 0x21, 0 - .dw 0x19c0, 0xc19f, 0x1fff, 0xc19f, 0x21, 0 - .dw 0x2040, 0xc19f, 0x207f, 0xc19f, 0x21, 0 - .dw 0x20c0, 0xc19f, 0x20ff, 0xc19f, 0x21, 0 - .dw 0x2140, 0xc19f, 0x217f, 0xc19f, 0x21, 0 - .dw 0x21c0, 0xc19f, 0x21ff, 0xc19f, 0x21, 0 - .dw 0x2240, 0xc19f, 0x227f, 0xc19f, 0x21, 0 - .dw 0x22c0, 0xc19f, 0x22ff, 0xc19f, 0x21, 0 - .dw 0x2340, 0xc19f, 0x237f, 0xc19f, 0x21, 0 - .dw 0x23c0, 0xc19f, 0x23ff, 0xc19f, 0x21, 0 - .dw 0x2440, 0xc19f, 0x247f, 0xc19f, 0x21, 0 - .dw 0x24c0, 0xc19f, 0x24ff, 0xc19f, 0x21, 0 - .dw 0x2540, 0xc19f, 0x257f, 0xc19f, 0x21, 0 - .dw 0x25c0, 0xc19f, 0x25ff, 0xc19f, 0x21, 0 - .dw 0x2640, 0xc19f, 0x267f, 0xc19f, 0x21, 0 - .dw 0x26c0, 0xc19f, 0x26ff, 0xc19f, 0x21, 0 - .dw 0x2740, 0xc19f, 0x277f, 0xc19f, 0x21, 0 - .dw 0x27c0, 0xc19f, 0x27ff, 0xc19f, 0x21, 0 - .dw 0x2840, 0xc19f, 0x287f, 0xc19f, 0x21, 0 - .dw 0x28c0, 0xc19f, 0x28ff, 0xc19f, 0x21, 0 - .dw 0x2940, 0xc19f, 0x297f, 0xc19f, 0x21, 0 - .dw 0x29c0, 0xc19f, 0x29ff, 0xc19f, 0x21, 0 - .dw 0x2a40, 0xc19f, 0x2a7f, 0xc19f, 0x21, 0 - .dw 0x2ac0, 0xc19f, 0x2aff, 0xc19f, 0x21, 0 - .dw 0x2b40, 0xc19f, 0x2b7f, 0xc19f, 0x21, 0 - .dw 0x2bc0, 0xc19f, 0x2bff, 0xc19f, 0x21, 0 - .dw 0x2c40, 0xc19f, 0x2c7f, 0xc19f, 0x21, 0 - .dw 0x2cc0, 0xc19f, 0x2cff, 0xc19f, 0x21, 0 - .dw 0x2d40, 0xc19f, 0x2d7f, 0xc19f, 0x21, 0 - .dw 0x2dc0, 0xc19f, 0x2dff, 0xc19f, 0x21, 0 - .dw 0x2e40, 0xc19f, 0x2e7f, 0xc19f, 0x21, 0 - .dw 0x2ec0, 0xc19f, 0x2eff, 0xc19f, 0x21, 0 - .dw 0x2f40, 0xc19f, 0x2f7f, 0xc19f, 0x21, 0 - .dw 0x2fc0, 0xc19f, 0x2fff, 0xc19f, 0x21, 0 - .dw 0x3040, 0xc19f, 0x307f, 0xc19f, 0x21, 0 - .dw 0x30c0, 0xc19f, 0x30ff, 0xc19f, 0x21, 0 - .dw 0x3140, 0xc19f, 0x317f, 0xc19f, 0x21, 0 - .dw 0x31c0, 0xc19f, 0x31ff, 0xc19f, 0x21, 0 - .dw 0x3240, 0xc19f, 0x327f, 0xc19f, 0x21, 0 - .dw 0x32c0, 0xc19f, 0x32ff, 0xc19f, 0x21, 0 - .dw 0x3340, 0xc19f, 0x337f, 0xc19f, 0x21, 0 - .dw 0x33c0, 0xc19f, 0x33ff, 0xc19f, 0x21, 0 - .dw 0x3440, 0xc19f, 0x347f, 0xc19f, 0x21, 0 - .dw 0x34c0, 0xc19f, 0x34ff, 0xc19f, 0x21, 0 - .dw 0x3540, 0xc19f, 0x357f, 0xc19f, 0x21, 0 - .dw 0x35c0, 0xc19f, 0x35ff, 0xc19f, 0x21, 0 - .dw 0x3640, 0xc19f, 0x367f, 0xc19f, 0x21, 0 - .dw 0x36c0, 0xc19f, 0x36ff, 0xc19f, 0x21, 0 - .dw 0x3740, 0xc19f, 0x377f, 0xc19f, 0x21, 0 - .dw 0x37c0, 0xc19f, 0x37ff, 0xc19f, 0x21, 0 - .dw 0x3840, 0xc19f, 0x387f, 0xc19f, 0x21, 0 - .dw 0x38c0, 0xc19f, 0x38ff, 0xc19f, 0x21, 0 - .dw 0x3940, 0xc19f, 0x397f, 0xc19f, 0x21, 0 - .dw 0x39c0, 0xc19f, 0x1fff, 0xc200, 0x21, 0 - .dw 0x2800, 0xc200, 0xffff, 0xc203, 0x21, 0 - .dw 0x0200, 0xc204, 0x1fff, 0xc204, 0x21, 0 - .dw 0x2800, 0xc204, 0x3fff, 0xc204, 0x21, 0 - .dw 0x4200, 0xc204, 0x5fff, 0xc204, 0x21, 0 - .dw 0x6800, 0xc204, 0x7fff, 0xc204, 0x21, 0 - .dw 0x8200, 0xc204, 0x9fff, 0xc204, 0x21, 0 - .dw 0xa800, 0xc204, 0xbfff, 0xc204, 0x21, 0 - .dw 0xc200, 0xc204, 0xdfff, 0xc204, 0x21, 0 - .dw 0xe800, 0xc204, 0x1fff, 0xc208, 0x21, 0 - .dw 0x2040, 0xc208, 0x207f, 0xc208, 0x21, 0 - .dw 0x20c0, 0xc208, 0x20ff, 0xc208, 0x21, 0 - .dw 0x2140, 0xc208, 0x217f, 0xc208, 0x21, 0 - .dw 0x21c0, 0xc208, 0x21ff, 0xc208, 0x21, 0 - .dw 0x2240, 0xc208, 0x227f, 0xc208, 0x21, 0 - .dw 0x22c0, 0xc208, 0x22ff, 0xc208, 0x21, 0 - .dw 0x2340, 0xc208, 0x237f, 0xc208, 0x21, 0 - .dw 0x23c0, 0xc208, 0x23ff, 0xc208, 0x21, 0 - .dw 0x2440, 0xc208, 0x247f, 0xc208, 0x21, 0 - .dw 0x24c0, 0xc208, 0x24ff, 0xc208, 0x21, 0 - .dw 0x2540, 0xc208, 0x257f, 0xc208, 0x21, 0 - .dw 0x25c0, 0xc208, 0x25ff, 0xc208, 0x21, 0 - .dw 0x2640, 0xc208, 0x267f, 0xc208, 0x21, 0 - .dw 0x26c0, 0xc208, 0x26ff, 0xc208, 0x21, 0 - .dw 0x2740, 0xc208, 0x277f, 0xc208, 0x21, 0 - .dw 0x27c0, 0xc208, 0xffff, 0xc20b, 0x21, 0 - .dw 0x0040, 0xc20c, 0x007f, 0xc20c, 0x21, 0 - .dw 0x00c0, 0xc20c, 0x00ff, 0xc20c, 0x21, 0 - .dw 0x0140, 0xc20c, 0x017f, 0xc20c, 0x21, 0 - .dw 0x01c0, 0xc20c, 0x1fff, 0xc20c, 0x21, 0 - .dw 0x2040, 0xc20c, 0x207f, 0xc20c, 0x21, 0 - .dw 0x20c0, 0xc20c, 0x20ff, 0xc20c, 0x21, 0 - .dw 0x2140, 0xc20c, 0x217f, 0xc20c, 0x21, 0 - .dw 0x21c0, 0xc20c, 0x21ff, 0xc20c, 0x21, 0 - .dw 0x2240, 0xc20c, 0x227f, 0xc20c, 0x21, 0 - .dw 0x22c0, 0xc20c, 0x22ff, 0xc20c, 0x21, 0 - .dw 0x2340, 0xc20c, 0x237f, 0xc20c, 0x21, 0 - .dw 0x23c0, 0xc20c, 0x23ff, 0xc20c, 0x21, 0 - .dw 0x2440, 0xc20c, 0x247f, 0xc20c, 0x21, 0 - .dw 0x24c0, 0xc20c, 0x24ff, 0xc20c, 0x21, 0 - .dw 0x2540, 0xc20c, 0x257f, 0xc20c, 0x21, 0 - .dw 0x25c0, 0xc20c, 0x25ff, 0xc20c, 0x21, 0 - .dw 0x2640, 0xc20c, 0x267f, 0xc20c, 0x21, 0 - .dw 0x26c0, 0xc20c, 0x26ff, 0xc20c, 0x21, 0 - .dw 0x2740, 0xc20c, 0x277f, 0xc20c, 0x21, 0 - .dw 0x27c0, 0xc20c, 0x3fff, 0xc20c, 0x21, 0 - .dw 0x4040, 0xc20c, 0x407f, 0xc20c, 0x21, 0 - .dw 0x40c0, 0xc20c, 0x40ff, 0xc20c, 0x21, 0 - .dw 0x4140, 0xc20c, 0x417f, 0xc20c, 0x21, 0 - .dw 0x41c0, 0xc20c, 0x5fff, 0xc20c, 0x21, 0 - .dw 0x6040, 0xc20c, 0x607f, 0xc20c, 0x21, 0 - .dw 0x60c0, 0xc20c, 0x60ff, 0xc20c, 0x21, 0 - .dw 0x6140, 0xc20c, 0x617f, 0xc20c, 0x21, 0 - .dw 0x61c0, 0xc20c, 0x61ff, 0xc20c, 0x21, 0 - .dw 0x6240, 0xc20c, 0x627f, 0xc20c, 0x21, 0 - .dw 0x62c0, 0xc20c, 0x62ff, 0xc20c, 0x21, 0 - .dw 0x6340, 0xc20c, 0x637f, 0xc20c, 0x21, 0 - .dw 0x63c0, 0xc20c, 0x63ff, 0xc20c, 0x21, 0 - .dw 0x6440, 0xc20c, 0x647f, 0xc20c, 0x21, 0 - .dw 0x64c0, 0xc20c, 0x64ff, 0xc20c, 0x21, 0 - .dw 0x6540, 0xc20c, 0x657f, 0xc20c, 0x21, 0 - .dw 0x65c0, 0xc20c, 0x65ff, 0xc20c, 0x21, 0 - .dw 0x6640, 0xc20c, 0x667f, 0xc20c, 0x21, 0 - .dw 0x66c0, 0xc20c, 0x66ff, 0xc20c, 0x21, 0 - .dw 0x6740, 0xc20c, 0x677f, 0xc20c, 0x21, 0 - .dw 0x67c0, 0xc20c, 0x7fff, 0xc20c, 0x21, 0 - .dw 0x8040, 0xc20c, 0x807f, 0xc20c, 0x21, 0 - .dw 0x80c0, 0xc20c, 0x80ff, 0xc20c, 0x21, 0 - .dw 0x8140, 0xc20c, 0x817f, 0xc20c, 0x21, 0 - .dw 0x81c0, 0xc20c, 0x9fff, 0xc20c, 0x21, 0 - .dw 0xa040, 0xc20c, 0xa07f, 0xc20c, 0x21, 0 - .dw 0xa0c0, 0xc20c, 0xa0ff, 0xc20c, 0x21, 0 - .dw 0xa140, 0xc20c, 0xa17f, 0xc20c, 0x21, 0 - .dw 0xa1c0, 0xc20c, 0xa1ff, 0xc20c, 0x21, 0 - .dw 0xa240, 0xc20c, 0xa27f, 0xc20c, 0x21, 0 - .dw 0xa2c0, 0xc20c, 0xa2ff, 0xc20c, 0x21, 0 - .dw 0xa340, 0xc20c, 0xa37f, 0xc20c, 0x21, 0 - .dw 0xa3c0, 0xc20c, 0xa3ff, 0xc20c, 0x21, 0 - .dw 0xa440, 0xc20c, 0xa47f, 0xc20c, 0x21, 0 - .dw 0xa4c0, 0xc20c, 0xa4ff, 0xc20c, 0x21, 0 - .dw 0xa540, 0xc20c, 0xa57f, 0xc20c, 0x21, 0 - .dw 0xa5c0, 0xc20c, 0xa5ff, 0xc20c, 0x21, 0 - .dw 0xa640, 0xc20c, 0xa67f, 0xc20c, 0x21, 0 - .dw 0xa6c0, 0xc20c, 0xa6ff, 0xc20c, 0x21, 0 - .dw 0xa740, 0xc20c, 0xa77f, 0xc20c, 0x21, 0 - .dw 0xa7c0, 0xc20c, 0xbfff, 0xc20c, 0x21, 0 - .dw 0xc040, 0xc20c, 0xc07f, 0xc20c, 0x21, 0 - .dw 0xc0c0, 0xc20c, 0xc0ff, 0xc20c, 0x21, 0 - .dw 0xc140, 0xc20c, 0xc17f, 0xc20c, 0x21, 0 - .dw 0xc1c0, 0xc20c, 0xdfff, 0xc20c, 0x21, 0 - .dw 0xe040, 0xc20c, 0xe07f, 0xc20c, 0x21, 0 - .dw 0xe0c0, 0xc20c, 0xe0ff, 0xc20c, 0x21, 0 - .dw 0xe140, 0xc20c, 0xe17f, 0xc20c, 0x21, 0 - .dw 0xe1c0, 0xc20c, 0xe1ff, 0xc20c, 0x21, 0 - .dw 0xe240, 0xc20c, 0xe27f, 0xc20c, 0x21, 0 - .dw 0xe2c0, 0xc20c, 0xe2ff, 0xc20c, 0x21, 0 - .dw 0xe340, 0xc20c, 0xe37f, 0xc20c, 0x21, 0 - .dw 0xe3c0, 0xc20c, 0xe3ff, 0xc20c, 0x21, 0 - .dw 0xe440, 0xc20c, 0xe47f, 0xc20c, 0x21, 0 - .dw 0xe4c0, 0xc20c, 0xe4ff, 0xc20c, 0x21, 0 - .dw 0xe540, 0xc20c, 0xe57f, 0xc20c, 0x21, 0 - .dw 0xe5c0, 0xc20c, 0xe5ff, 0xc20c, 0x21, 0 - .dw 0xe640, 0xc20c, 0xe67f, 0xc20c, 0x21, 0 - .dw 0xe6c0, 0xc20c, 0xe6ff, 0xc20c, 0x21, 0 - .dw 0xe740, 0xc20c, 0xe77f, 0xc20c, 0x21, 0 - .dw 0xe7c0, 0xc20c, 0xffff, 0xc213, 0x21, 0 - .dw 0x0200, 0xc214, 0x1fff, 0xc214, 0x21, 0 - .dw 0x2800, 0xc214, 0x3fff, 0xc214, 0x21, 0 - .dw 0x4200, 0xc214, 0x5fff, 0xc214, 0x21, 0 - .dw 0x6800, 0xc214, 0x7fff, 0xc214, 0x21, 0 - .dw 0x8200, 0xc214, 0x9fff, 0xc214, 0x21, 0 - .dw 0xa800, 0xc214, 0xbfff, 0xc214, 0x21, 0 - .dw 0xc200, 0xc214, 0xdfff, 0xc214, 0x21, 0 - .dw 0xe800, 0xc214, 0xffff, 0xc21b, 0x21, 0 - .dw 0x0040, 0xc21c, 0x007f, 0xc21c, 0x21, 0 - .dw 0x00c0, 0xc21c, 0x00ff, 0xc21c, 0x21, 0 - .dw 0x0140, 0xc21c, 0x017f, 0xc21c, 0x21, 0 - .dw 0x01c0, 0xc21c, 0x1fff, 0xc21c, 0x21, 0 - .dw 0x2040, 0xc21c, 0x207f, 0xc21c, 0x21, 0 - .dw 0x20c0, 0xc21c, 0x20ff, 0xc21c, 0x21, 0 - .dw 0x2140, 0xc21c, 0x217f, 0xc21c, 0x21, 0 - .dw 0x21c0, 0xc21c, 0x21ff, 0xc21c, 0x21, 0 - .dw 0x2240, 0xc21c, 0x227f, 0xc21c, 0x21, 0 - .dw 0x22c0, 0xc21c, 0x22ff, 0xc21c, 0x21, 0 - .dw 0x2340, 0xc21c, 0x237f, 0xc21c, 0x21, 0 - .dw 0x23c0, 0xc21c, 0x23ff, 0xc21c, 0x21, 0 - .dw 0x2440, 0xc21c, 0x247f, 0xc21c, 0x21, 0 - .dw 0x24c0, 0xc21c, 0x24ff, 0xc21c, 0x21, 0 - .dw 0x2540, 0xc21c, 0x257f, 0xc21c, 0x21, 0 - .dw 0x25c0, 0xc21c, 0x25ff, 0xc21c, 0x21, 0 - .dw 0x2640, 0xc21c, 0x267f, 0xc21c, 0x21, 0 - .dw 0x26c0, 0xc21c, 0x26ff, 0xc21c, 0x21, 0 - .dw 0x2740, 0xc21c, 0x277f, 0xc21c, 0x21, 0 - .dw 0x27c0, 0xc21c, 0x3fff, 0xc21c, 0x21, 0 - .dw 0x4040, 0xc21c, 0x407f, 0xc21c, 0x21, 0 - .dw 0x40c0, 0xc21c, 0x40ff, 0xc21c, 0x21, 0 - .dw 0x4140, 0xc21c, 0x417f, 0xc21c, 0x21, 0 - .dw 0x41c0, 0xc21c, 0x5fff, 0xc21c, 0x21, 0 - .dw 0x6040, 0xc21c, 0x607f, 0xc21c, 0x21, 0 - .dw 0x60c0, 0xc21c, 0x60ff, 0xc21c, 0x21, 0 - .dw 0x6140, 0xc21c, 0x617f, 0xc21c, 0x21, 0 - .dw 0x61c0, 0xc21c, 0x61ff, 0xc21c, 0x21, 0 - .dw 0x6240, 0xc21c, 0x627f, 0xc21c, 0x21, 0 - .dw 0x62c0, 0xc21c, 0x62ff, 0xc21c, 0x21, 0 - .dw 0x6340, 0xc21c, 0x637f, 0xc21c, 0x21, 0 - .dw 0x63c0, 0xc21c, 0x63ff, 0xc21c, 0x21, 0 - .dw 0x6440, 0xc21c, 0x647f, 0xc21c, 0x21, 0 - .dw 0x64c0, 0xc21c, 0x64ff, 0xc21c, 0x21, 0 - .dw 0x6540, 0xc21c, 0x657f, 0xc21c, 0x21, 0 - .dw 0x65c0, 0xc21c, 0x65ff, 0xc21c, 0x21, 0 - .dw 0x6640, 0xc21c, 0x667f, 0xc21c, 0x21, 0 - .dw 0x66c0, 0xc21c, 0x66ff, 0xc21c, 0x21, 0 - .dw 0x6740, 0xc21c, 0x677f, 0xc21c, 0x21, 0 - .dw 0x67c0, 0xc21c, 0x7fff, 0xc21c, 0x21, 0 - .dw 0x8040, 0xc21c, 0x807f, 0xc21c, 0x21, 0 - .dw 0x80c0, 0xc21c, 0x80ff, 0xc21c, 0x21, 0 - .dw 0x8140, 0xc21c, 0x817f, 0xc21c, 0x21, 0 - .dw 0x81c0, 0xc21c, 0x9fff, 0xc21c, 0x21, 0 - .dw 0xa040, 0xc21c, 0xa07f, 0xc21c, 0x21, 0 - .dw 0xa0c0, 0xc21c, 0xa0ff, 0xc21c, 0x21, 0 - .dw 0xa140, 0xc21c, 0xa17f, 0xc21c, 0x21, 0 - .dw 0xa1c0, 0xc21c, 0xa1ff, 0xc21c, 0x21, 0 - .dw 0xa240, 0xc21c, 0xa27f, 0xc21c, 0x21, 0 - .dw 0xa2c0, 0xc21c, 0xa2ff, 0xc21c, 0x21, 0 - .dw 0xa340, 0xc21c, 0xa37f, 0xc21c, 0x21, 0 - .dw 0xa3c0, 0xc21c, 0xa3ff, 0xc21c, 0x21, 0 - .dw 0xa440, 0xc21c, 0xa47f, 0xc21c, 0x21, 0 - .dw 0xa4c0, 0xc21c, 0xa4ff, 0xc21c, 0x21, 0 - .dw 0xa540, 0xc21c, 0xa57f, 0xc21c, 0x21, 0 - .dw 0xa5c0, 0xc21c, 0xa5ff, 0xc21c, 0x21, 0 - .dw 0xa640, 0xc21c, 0xa67f, 0xc21c, 0x21, 0 - .dw 0xa6c0, 0xc21c, 0xa6ff, 0xc21c, 0x21, 0 - .dw 0xa740, 0xc21c, 0xa77f, 0xc21c, 0x21, 0 - .dw 0xa7c0, 0xc21c, 0xbfff, 0xc21c, 0x21, 0 - .dw 0xc040, 0xc21c, 0xc07f, 0xc21c, 0x21, 0 - .dw 0xc0c0, 0xc21c, 0xc0ff, 0xc21c, 0x21, 0 - .dw 0xc140, 0xc21c, 0xc17f, 0xc21c, 0x21, 0 - .dw 0xc1c0, 0xc21c, 0xdfff, 0xc21c, 0x21, 0 - .dw 0xe040, 0xc21c, 0xe07f, 0xc21c, 0x21, 0 - .dw 0xe0c0, 0xc21c, 0xe0ff, 0xc21c, 0x21, 0 - .dw 0xe140, 0xc21c, 0xe17f, 0xc21c, 0x21, 0 - .dw 0xe1c0, 0xc21c, 0xe1ff, 0xc21c, 0x21, 0 - .dw 0xe240, 0xc21c, 0xe27f, 0xc21c, 0x21, 0 - .dw 0xe2c0, 0xc21c, 0xe2ff, 0xc21c, 0x21, 0 - .dw 0xe340, 0xc21c, 0xe37f, 0xc21c, 0x21, 0 - .dw 0xe3c0, 0xc21c, 0xe3ff, 0xc21c, 0x21, 0 - .dw 0xe440, 0xc21c, 0xe47f, 0xc21c, 0x21, 0 - .dw 0xe4c0, 0xc21c, 0xe4ff, 0xc21c, 0x21, 0 - .dw 0xe540, 0xc21c, 0xe57f, 0xc21c, 0x21, 0 - .dw 0xe5c0, 0xc21c, 0xe5ff, 0xc21c, 0x21, 0 - .dw 0xe640, 0xc21c, 0xe67f, 0xc21c, 0x21, 0 - .dw 0xe6c0, 0xc21c, 0xe6ff, 0xc21c, 0x21, 0 - .dw 0xe740, 0xc21c, 0xe77f, 0xc21c, 0x21, 0 - .dw 0xe7c0, 0xc21c, 0x1fff, 0xc220, 0x21, 0 - .dw 0x2800, 0xc220, 0xffff, 0xc223, 0x21, 0 - .dw 0x0200, 0xc224, 0x1fff, 0xc224, 0x21, 0 - .dw 0x2800, 0xc224, 0x3fff, 0xc224, 0x21, 0 - .dw 0x4200, 0xc224, 0x5fff, 0xc224, 0x21, 0 - .dw 0x6800, 0xc224, 0x7fff, 0xc224, 0x21, 0 - .dw 0x8200, 0xc224, 0x9fff, 0xc224, 0x21, 0 - .dw 0xa800, 0xc224, 0xbfff, 0xc224, 0x21, 0 - .dw 0xc200, 0xc224, 0xdfff, 0xc224, 0x21, 0 - .dw 0xe800, 0xc224, 0x1fff, 0xc228, 0x21, 0 - .dw 0x2040, 0xc228, 0x207f, 0xc228, 0x21, 0 - .dw 0x20c0, 0xc228, 0x20ff, 0xc228, 0x21, 0 - .dw 0x2140, 0xc228, 0x217f, 0xc228, 0x21, 0 - .dw 0x21c0, 0xc228, 0x21ff, 0xc228, 0x21, 0 - .dw 0x2240, 0xc228, 0x227f, 0xc228, 0x21, 0 - .dw 0x22c0, 0xc228, 0x22ff, 0xc228, 0x21, 0 - .dw 0x2340, 0xc228, 0x237f, 0xc228, 0x21, 0 - .dw 0x23c0, 0xc228, 0x23ff, 0xc228, 0x21, 0 - .dw 0x2440, 0xc228, 0x247f, 0xc228, 0x21, 0 - .dw 0x24c0, 0xc228, 0x24ff, 0xc228, 0x21, 0 - .dw 0x2540, 0xc228, 0x257f, 0xc228, 0x21, 0 - .dw 0x25c0, 0xc228, 0x25ff, 0xc228, 0x21, 0 - .dw 0x2640, 0xc228, 0x267f, 0xc228, 0x21, 0 - .dw 0x26c0, 0xc228, 0x26ff, 0xc228, 0x21, 0 - .dw 0x2740, 0xc228, 0x277f, 0xc228, 0x21, 0 - .dw 0x27c0, 0xc228, 0xffff, 0xc22b, 0x21, 0 - .dw 0x0040, 0xc22c, 0x007f, 0xc22c, 0x21, 0 - .dw 0x00c0, 0xc22c, 0x00ff, 0xc22c, 0x21, 0 - .dw 0x0140, 0xc22c, 0x017f, 0xc22c, 0x21, 0 - .dw 0x01c0, 0xc22c, 0x1fff, 0xc22c, 0x21, 0 - .dw 0x2040, 0xc22c, 0x207f, 0xc22c, 0x21, 0 - .dw 0x20c0, 0xc22c, 0x20ff, 0xc22c, 0x21, 0 - .dw 0x2140, 0xc22c, 0x217f, 0xc22c, 0x21, 0 - .dw 0x21c0, 0xc22c, 0x21ff, 0xc22c, 0x21, 0 - .dw 0x2240, 0xc22c, 0x227f, 0xc22c, 0x21, 0 - .dw 0x22c0, 0xc22c, 0x22ff, 0xc22c, 0x21, 0 - .dw 0x2340, 0xc22c, 0x237f, 0xc22c, 0x21, 0 - .dw 0x23c0, 0xc22c, 0x23ff, 0xc22c, 0x21, 0 - .dw 0x2440, 0xc22c, 0x247f, 0xc22c, 0x21, 0 - .dw 0x24c0, 0xc22c, 0x24ff, 0xc22c, 0x21, 0 - .dw 0x2540, 0xc22c, 0x257f, 0xc22c, 0x21, 0 - .dw 0x25c0, 0xc22c, 0x25ff, 0xc22c, 0x21, 0 - .dw 0x2640, 0xc22c, 0x267f, 0xc22c, 0x21, 0 - .dw 0x26c0, 0xc22c, 0x26ff, 0xc22c, 0x21, 0 - .dw 0x2740, 0xc22c, 0x277f, 0xc22c, 0x21, 0 - .dw 0x27c0, 0xc22c, 0x3fff, 0xc22c, 0x21, 0 - .dw 0x4040, 0xc22c, 0x407f, 0xc22c, 0x21, 0 - .dw 0x40c0, 0xc22c, 0x40ff, 0xc22c, 0x21, 0 - .dw 0x4140, 0xc22c, 0x417f, 0xc22c, 0x21, 0 - .dw 0x41c0, 0xc22c, 0x5fff, 0xc22c, 0x21, 0 - .dw 0x6040, 0xc22c, 0x607f, 0xc22c, 0x21, 0 - .dw 0x60c0, 0xc22c, 0x60ff, 0xc22c, 0x21, 0 - .dw 0x6140, 0xc22c, 0x617f, 0xc22c, 0x21, 0 - .dw 0x61c0, 0xc22c, 0x61ff, 0xc22c, 0x21, 0 - .dw 0x6240, 0xc22c, 0x627f, 0xc22c, 0x21, 0 - .dw 0x62c0, 0xc22c, 0x62ff, 0xc22c, 0x21, 0 - .dw 0x6340, 0xc22c, 0x637f, 0xc22c, 0x21, 0 - .dw 0x63c0, 0xc22c, 0x63ff, 0xc22c, 0x21, 0 - .dw 0x6440, 0xc22c, 0x647f, 0xc22c, 0x21, 0 - .dw 0x64c0, 0xc22c, 0x64ff, 0xc22c, 0x21, 0 - .dw 0x6540, 0xc22c, 0x657f, 0xc22c, 0x21, 0 - .dw 0x65c0, 0xc22c, 0x65ff, 0xc22c, 0x21, 0 - .dw 0x6640, 0xc22c, 0x667f, 0xc22c, 0x21, 0 - .dw 0x66c0, 0xc22c, 0x66ff, 0xc22c, 0x21, 0 - .dw 0x6740, 0xc22c, 0x677f, 0xc22c, 0x21, 0 - .dw 0x67c0, 0xc22c, 0x7fff, 0xc22c, 0x21, 0 - .dw 0x8040, 0xc22c, 0x807f, 0xc22c, 0x21, 0 - .dw 0x80c0, 0xc22c, 0x80ff, 0xc22c, 0x21, 0 - .dw 0x8140, 0xc22c, 0x817f, 0xc22c, 0x21, 0 - .dw 0x81c0, 0xc22c, 0x9fff, 0xc22c, 0x21, 0 - .dw 0xa040, 0xc22c, 0xa07f, 0xc22c, 0x21, 0 - .dw 0xa0c0, 0xc22c, 0xa0ff, 0xc22c, 0x21, 0 - .dw 0xa140, 0xc22c, 0xa17f, 0xc22c, 0x21, 0 - .dw 0xa1c0, 0xc22c, 0xa1ff, 0xc22c, 0x21, 0 - .dw 0xa240, 0xc22c, 0xa27f, 0xc22c, 0x21, 0 - .dw 0xa2c0, 0xc22c, 0xa2ff, 0xc22c, 0x21, 0 - .dw 0xa340, 0xc22c, 0xa37f, 0xc22c, 0x21, 0 - .dw 0xa3c0, 0xc22c, 0xa3ff, 0xc22c, 0x21, 0 - .dw 0xa440, 0xc22c, 0xa47f, 0xc22c, 0x21, 0 - .dw 0xa4c0, 0xc22c, 0xa4ff, 0xc22c, 0x21, 0 - .dw 0xa540, 0xc22c, 0xa57f, 0xc22c, 0x21, 0 - .dw 0xa5c0, 0xc22c, 0xa5ff, 0xc22c, 0x21, 0 - .dw 0xa640, 0xc22c, 0xa67f, 0xc22c, 0x21, 0 - .dw 0xa6c0, 0xc22c, 0xa6ff, 0xc22c, 0x21, 0 - .dw 0xa740, 0xc22c, 0xa77f, 0xc22c, 0x21, 0 - .dw 0xa7c0, 0xc22c, 0xbfff, 0xc22c, 0x21, 0 - .dw 0xc040, 0xc22c, 0xc07f, 0xc22c, 0x21, 0 - .dw 0xc0c0, 0xc22c, 0xc0ff, 0xc22c, 0x21, 0 - .dw 0xc140, 0xc22c, 0xc17f, 0xc22c, 0x21, 0 - .dw 0xc1c0, 0xc22c, 0xdfff, 0xc22c, 0x21, 0 - .dw 0xe040, 0xc22c, 0xe07f, 0xc22c, 0x21, 0 - .dw 0xe0c0, 0xc22c, 0xe0ff, 0xc22c, 0x21, 0 - .dw 0xe140, 0xc22c, 0xe17f, 0xc22c, 0x21, 0 - .dw 0xe1c0, 0xc22c, 0xe1ff, 0xc22c, 0x21, 0 - .dw 0xe240, 0xc22c, 0xe27f, 0xc22c, 0x21, 0 - .dw 0xe2c0, 0xc22c, 0xe2ff, 0xc22c, 0x21, 0 - .dw 0xe340, 0xc22c, 0xe37f, 0xc22c, 0x21, 0 - .dw 0xe3c0, 0xc22c, 0xe3ff, 0xc22c, 0x21, 0 - .dw 0xe440, 0xc22c, 0xe47f, 0xc22c, 0x21, 0 - .dw 0xe4c0, 0xc22c, 0xe4ff, 0xc22c, 0x21, 0 - .dw 0xe540, 0xc22c, 0xe57f, 0xc22c, 0x21, 0 - .dw 0xe5c0, 0xc22c, 0xe5ff, 0xc22c, 0x21, 0 - .dw 0xe640, 0xc22c, 0xe67f, 0xc22c, 0x21, 0 - .dw 0xe6c0, 0xc22c, 0xe6ff, 0xc22c, 0x21, 0 - .dw 0xe740, 0xc22c, 0xe77f, 0xc22c, 0x21, 0 - .dw 0xe7c0, 0xc22c, 0xffff, 0xc233, 0x21, 0 - .dw 0x0200, 0xc234, 0x1fff, 0xc234, 0x21, 0 - .dw 0x2800, 0xc234, 0x3fff, 0xc234, 0x21, 0 - .dw 0x4200, 0xc234, 0x5fff, 0xc234, 0x21, 0 - .dw 0x6800, 0xc234, 0x7fff, 0xc234, 0x21, 0 - .dw 0x8200, 0xc234, 0x9fff, 0xc234, 0x21, 0 - .dw 0xa800, 0xc234, 0xbfff, 0xc234, 0x21, 0 - .dw 0xc200, 0xc234, 0xdfff, 0xc234, 0x21, 0 - .dw 0xe800, 0xc234, 0xffff, 0xc23b, 0x21, 0 - .dw 0x0040, 0xc23c, 0x007f, 0xc23c, 0x21, 0 - .dw 0x00c0, 0xc23c, 0x00ff, 0xc23c, 0x21, 0 - .dw 0x0140, 0xc23c, 0x017f, 0xc23c, 0x21, 0 - .dw 0x01c0, 0xc23c, 0x1fff, 0xc23c, 0x21, 0 - .dw 0x2040, 0xc23c, 0x207f, 0xc23c, 0x21, 0 - .dw 0x20c0, 0xc23c, 0x20ff, 0xc23c, 0x21, 0 - .dw 0x2140, 0xc23c, 0x217f, 0xc23c, 0x21, 0 - .dw 0x21c0, 0xc23c, 0x21ff, 0xc23c, 0x21, 0 - .dw 0x2240, 0xc23c, 0x227f, 0xc23c, 0x21, 0 - .dw 0x22c0, 0xc23c, 0x22ff, 0xc23c, 0x21, 0 - .dw 0x2340, 0xc23c, 0x237f, 0xc23c, 0x21, 0 - .dw 0x23c0, 0xc23c, 0x23ff, 0xc23c, 0x21, 0 - .dw 0x2440, 0xc23c, 0x247f, 0xc23c, 0x21, 0 - .dw 0x24c0, 0xc23c, 0x24ff, 0xc23c, 0x21, 0 - .dw 0x2540, 0xc23c, 0x257f, 0xc23c, 0x21, 0 - .dw 0x25c0, 0xc23c, 0x25ff, 0xc23c, 0x21, 0 - .dw 0x2640, 0xc23c, 0x267f, 0xc23c, 0x21, 0 - .dw 0x26c0, 0xc23c, 0x26ff, 0xc23c, 0x21, 0 - .dw 0x2740, 0xc23c, 0x277f, 0xc23c, 0x21, 0 - .dw 0x27c0, 0xc23c, 0x3fff, 0xc23c, 0x21, 0 - .dw 0x4040, 0xc23c, 0x407f, 0xc23c, 0x21, 0 - .dw 0x40c0, 0xc23c, 0x40ff, 0xc23c, 0x21, 0 - .dw 0x4140, 0xc23c, 0x417f, 0xc23c, 0x21, 0 - .dw 0x41c0, 0xc23c, 0x5fff, 0xc23c, 0x21, 0 - .dw 0x6040, 0xc23c, 0x607f, 0xc23c, 0x21, 0 - .dw 0x60c0, 0xc23c, 0x60ff, 0xc23c, 0x21, 0 - .dw 0x6140, 0xc23c, 0x617f, 0xc23c, 0x21, 0 - .dw 0x61c0, 0xc23c, 0x61ff, 0xc23c, 0x21, 0 - .dw 0x6240, 0xc23c, 0x627f, 0xc23c, 0x21, 0 - .dw 0x62c0, 0xc23c, 0x62ff, 0xc23c, 0x21, 0 - .dw 0x6340, 0xc23c, 0x637f, 0xc23c, 0x21, 0 - .dw 0x63c0, 0xc23c, 0x63ff, 0xc23c, 0x21, 0 - .dw 0x6440, 0xc23c, 0x647f, 0xc23c, 0x21, 0 - .dw 0x64c0, 0xc23c, 0x64ff, 0xc23c, 0x21, 0 - .dw 0x6540, 0xc23c, 0x657f, 0xc23c, 0x21, 0 - .dw 0x65c0, 0xc23c, 0x65ff, 0xc23c, 0x21, 0 - .dw 0x6640, 0xc23c, 0x667f, 0xc23c, 0x21, 0 - .dw 0x66c0, 0xc23c, 0x66ff, 0xc23c, 0x21, 0 - .dw 0x6740, 0xc23c, 0x677f, 0xc23c, 0x21, 0 - .dw 0x67c0, 0xc23c, 0x7fff, 0xc23c, 0x21, 0 - .dw 0x8040, 0xc23c, 0x807f, 0xc23c, 0x21, 0 - .dw 0x80c0, 0xc23c, 0x80ff, 0xc23c, 0x21, 0 - .dw 0x8140, 0xc23c, 0x817f, 0xc23c, 0x21, 0 - .dw 0x81c0, 0xc23c, 0x9fff, 0xc23c, 0x21, 0 - .dw 0xa040, 0xc23c, 0xa07f, 0xc23c, 0x21, 0 - .dw 0xa0c0, 0xc23c, 0xa0ff, 0xc23c, 0x21, 0 - .dw 0xa140, 0xc23c, 0xa17f, 0xc23c, 0x21, 0 - .dw 0xa1c0, 0xc23c, 0xa1ff, 0xc23c, 0x21, 0 - .dw 0xa240, 0xc23c, 0xa27f, 0xc23c, 0x21, 0 - .dw 0xa2c0, 0xc23c, 0xa2ff, 0xc23c, 0x21, 0 - .dw 0xa340, 0xc23c, 0xa37f, 0xc23c, 0x21, 0 - .dw 0xa3c0, 0xc23c, 0xa3ff, 0xc23c, 0x21, 0 - .dw 0xa440, 0xc23c, 0xa47f, 0xc23c, 0x21, 0 - .dw 0xa4c0, 0xc23c, 0xa4ff, 0xc23c, 0x21, 0 - .dw 0xa540, 0xc23c, 0xa57f, 0xc23c, 0x21, 0 - .dw 0xa5c0, 0xc23c, 0xa5ff, 0xc23c, 0x21, 0 - .dw 0xa640, 0xc23c, 0xa67f, 0xc23c, 0x21, 0 - .dw 0xa6c0, 0xc23c, 0xa6ff, 0xc23c, 0x21, 0 - .dw 0xa740, 0xc23c, 0xa77f, 0xc23c, 0x21, 0 - .dw 0xa7c0, 0xc23c, 0xbfff, 0xc23c, 0x21, 0 - .dw 0xc040, 0xc23c, 0xc07f, 0xc23c, 0x21, 0 - .dw 0xc0c0, 0xc23c, 0xc0ff, 0xc23c, 0x21, 0 - .dw 0xc140, 0xc23c, 0xc17f, 0xc23c, 0x21, 0 - .dw 0xc1c0, 0xc23c, 0xdfff, 0xc23c, 0x21, 0 - .dw 0xe040, 0xc23c, 0xe07f, 0xc23c, 0x21, 0 - .dw 0xe0c0, 0xc23c, 0xe0ff, 0xc23c, 0x21, 0 - .dw 0xe140, 0xc23c, 0xe17f, 0xc23c, 0x21, 0 - .dw 0xe1c0, 0xc23c, 0xe1ff, 0xc23c, 0x21, 0 - .dw 0xe240, 0xc23c, 0xe27f, 0xc23c, 0x21, 0 - .dw 0xe2c0, 0xc23c, 0xe2ff, 0xc23c, 0x21, 0 - .dw 0xe340, 0xc23c, 0xe37f, 0xc23c, 0x21, 0 - .dw 0xe3c0, 0xc23c, 0xe3ff, 0xc23c, 0x21, 0 - .dw 0xe440, 0xc23c, 0xe47f, 0xc23c, 0x21, 0 - .dw 0xe4c0, 0xc23c, 0xe4ff, 0xc23c, 0x21, 0 - .dw 0xe540, 0xc23c, 0xe57f, 0xc23c, 0x21, 0 - .dw 0xe5c0, 0xc23c, 0xe5ff, 0xc23c, 0x21, 0 - .dw 0xe640, 0xc23c, 0xe67f, 0xc23c, 0x21, 0 - .dw 0xe6c0, 0xc23c, 0xe6ff, 0xc23c, 0x21, 0 - .dw 0xe740, 0xc23c, 0xe77f, 0xc23c, 0x21, 0 - .dw 0xe7c0, 0xc23c, 0x1fff, 0xc240, 0x21, 0 - .dw 0x2800, 0xc240, 0xffff, 0xc243, 0x21, 0 - .dw 0x0200, 0xc244, 0x1fff, 0xc244, 0x21, 0 - .dw 0x2800, 0xc244, 0x3fff, 0xc244, 0x21, 0 - .dw 0x4200, 0xc244, 0x5fff, 0xc244, 0x21, 0 - .dw 0x6800, 0xc244, 0x7fff, 0xc244, 0x21, 0 - .dw 0x8200, 0xc244, 0x9fff, 0xc244, 0x21, 0 - .dw 0xa800, 0xc244, 0xbfff, 0xc244, 0x21, 0 - .dw 0xc200, 0xc244, 0xdfff, 0xc244, 0x21, 0 - .dw 0xe800, 0xc244, 0xffff, 0xc253, 0x21, 0 - .dw 0x0200, 0xc254, 0x1fff, 0xc254, 0x21, 0 - .dw 0x2800, 0xc254, 0x3fff, 0xc254, 0x21, 0 - .dw 0x4200, 0xc254, 0x5fff, 0xc254, 0x21, 0 - .dw 0x6800, 0xc254, 0x7fff, 0xc254, 0x21, 0 - .dw 0x8200, 0xc254, 0x9fff, 0xc254, 0x21, 0 - .dw 0xa800, 0xc254, 0xbfff, 0xc254, 0x21, 0 - .dw 0xc200, 0xc254, 0xdfff, 0xc254, 0x21, 0 - .dw 0xe800, 0xc254, 0x1fff, 0xc280, 0x21, 0 - .dw 0x2800, 0xc280, 0xffff, 0xc283, 0x21, 0 - .dw 0x0200, 0xc284, 0x1fff, 0xc284, 0x21, 0 - .dw 0x2800, 0xc284, 0x3fff, 0xc284, 0x21, 0 - .dw 0x4200, 0xc284, 0x5fff, 0xc284, 0x21, 0 - .dw 0x6800, 0xc284, 0x7fff, 0xc284, 0x21, 0 - .dw 0x8200, 0xc284, 0x9fff, 0xc284, 0x21, 0 - .dw 0xa800, 0xc284, 0xbfff, 0xc284, 0x21, 0 - .dw 0xc200, 0xc284, 0xdfff, 0xc284, 0x21, 0 - .dw 0xe800, 0xc284, 0x1fff, 0xc288, 0x21, 0 - .dw 0x2040, 0xc288, 0x207f, 0xc288, 0x21, 0 - .dw 0x20c0, 0xc288, 0x20ff, 0xc288, 0x21, 0 - .dw 0x2140, 0xc288, 0x217f, 0xc288, 0x21, 0 - .dw 0x21c0, 0xc288, 0x21ff, 0xc288, 0x21, 0 - .dw 0x2240, 0xc288, 0x227f, 0xc288, 0x21, 0 - .dw 0x22c0, 0xc288, 0x22ff, 0xc288, 0x21, 0 - .dw 0x2340, 0xc288, 0x237f, 0xc288, 0x21, 0 - .dw 0x23c0, 0xc288, 0x23ff, 0xc288, 0x21, 0 - .dw 0x2440, 0xc288, 0x247f, 0xc288, 0x21, 0 - .dw 0x24c0, 0xc288, 0x24ff, 0xc288, 0x21, 0 - .dw 0x2540, 0xc288, 0x257f, 0xc288, 0x21, 0 - .dw 0x25c0, 0xc288, 0x25ff, 0xc288, 0x21, 0 - .dw 0x2640, 0xc288, 0x267f, 0xc288, 0x21, 0 - .dw 0x26c0, 0xc288, 0x26ff, 0xc288, 0x21, 0 - .dw 0x2740, 0xc288, 0x277f, 0xc288, 0x21, 0 - .dw 0x27c0, 0xc288, 0xffff, 0xc28b, 0x21, 0 - .dw 0x0040, 0xc28c, 0x007f, 0xc28c, 0x21, 0 - .dw 0x00c0, 0xc28c, 0x00ff, 0xc28c, 0x21, 0 - .dw 0x0140, 0xc28c, 0x017f, 0xc28c, 0x21, 0 - .dw 0x01c0, 0xc28c, 0x1fff, 0xc28c, 0x21, 0 - .dw 0x2040, 0xc28c, 0x207f, 0xc28c, 0x21, 0 - .dw 0x20c0, 0xc28c, 0x20ff, 0xc28c, 0x21, 0 - .dw 0x2140, 0xc28c, 0x217f, 0xc28c, 0x21, 0 - .dw 0x21c0, 0xc28c, 0x21ff, 0xc28c, 0x21, 0 - .dw 0x2240, 0xc28c, 0x227f, 0xc28c, 0x21, 0 - .dw 0x22c0, 0xc28c, 0x22ff, 0xc28c, 0x21, 0 - .dw 0x2340, 0xc28c, 0x237f, 0xc28c, 0x21, 0 - .dw 0x23c0, 0xc28c, 0x23ff, 0xc28c, 0x21, 0 - .dw 0x2440, 0xc28c, 0x247f, 0xc28c, 0x21, 0 - .dw 0x24c0, 0xc28c, 0x24ff, 0xc28c, 0x21, 0 - .dw 0x2540, 0xc28c, 0x257f, 0xc28c, 0x21, 0 - .dw 0x25c0, 0xc28c, 0x25ff, 0xc28c, 0x21, 0 - .dw 0x2640, 0xc28c, 0x267f, 0xc28c, 0x21, 0 - .dw 0x26c0, 0xc28c, 0x26ff, 0xc28c, 0x21, 0 - .dw 0x2740, 0xc28c, 0x277f, 0xc28c, 0x21, 0 - .dw 0x27c0, 0xc28c, 0x3fff, 0xc28c, 0x21, 0 - .dw 0x4040, 0xc28c, 0x407f, 0xc28c, 0x21, 0 - .dw 0x40c0, 0xc28c, 0x40ff, 0xc28c, 0x21, 0 - .dw 0x4140, 0xc28c, 0x417f, 0xc28c, 0x21, 0 - .dw 0x41c0, 0xc28c, 0x5fff, 0xc28c, 0x21, 0 - .dw 0x6040, 0xc28c, 0x607f, 0xc28c, 0x21, 0 - .dw 0x60c0, 0xc28c, 0x60ff, 0xc28c, 0x21, 0 - .dw 0x6140, 0xc28c, 0x617f, 0xc28c, 0x21, 0 - .dw 0x61c0, 0xc28c, 0x61ff, 0xc28c, 0x21, 0 - .dw 0x6240, 0xc28c, 0x627f, 0xc28c, 0x21, 0 - .dw 0x62c0, 0xc28c, 0x62ff, 0xc28c, 0x21, 0 - .dw 0x6340, 0xc28c, 0x637f, 0xc28c, 0x21, 0 - .dw 0x63c0, 0xc28c, 0x63ff, 0xc28c, 0x21, 0 - .dw 0x6440, 0xc28c, 0x647f, 0xc28c, 0x21, 0 - .dw 0x64c0, 0xc28c, 0x64ff, 0xc28c, 0x21, 0 - .dw 0x6540, 0xc28c, 0x657f, 0xc28c, 0x21, 0 - .dw 0x65c0, 0xc28c, 0x65ff, 0xc28c, 0x21, 0 - .dw 0x6640, 0xc28c, 0x667f, 0xc28c, 0x21, 0 - .dw 0x66c0, 0xc28c, 0x66ff, 0xc28c, 0x21, 0 - .dw 0x6740, 0xc28c, 0x677f, 0xc28c, 0x21, 0 - .dw 0x67c0, 0xc28c, 0x7fff, 0xc28c, 0x21, 0 - .dw 0x8040, 0xc28c, 0x807f, 0xc28c, 0x21, 0 - .dw 0x80c0, 0xc28c, 0x80ff, 0xc28c, 0x21, 0 - .dw 0x8140, 0xc28c, 0x817f, 0xc28c, 0x21, 0 - .dw 0x81c0, 0xc28c, 0x9fff, 0xc28c, 0x21, 0 - .dw 0xa040, 0xc28c, 0xa07f, 0xc28c, 0x21, 0 - .dw 0xa0c0, 0xc28c, 0xa0ff, 0xc28c, 0x21, 0 - .dw 0xa140, 0xc28c, 0xa17f, 0xc28c, 0x21, 0 - .dw 0xa1c0, 0xc28c, 0xa1ff, 0xc28c, 0x21, 0 - .dw 0xa240, 0xc28c, 0xa27f, 0xc28c, 0x21, 0 - .dw 0xa2c0, 0xc28c, 0xa2ff, 0xc28c, 0x21, 0 - .dw 0xa340, 0xc28c, 0xa37f, 0xc28c, 0x21, 0 - .dw 0xa3c0, 0xc28c, 0xa3ff, 0xc28c, 0x21, 0 - .dw 0xa440, 0xc28c, 0xa47f, 0xc28c, 0x21, 0 - .dw 0xa4c0, 0xc28c, 0xa4ff, 0xc28c, 0x21, 0 - .dw 0xa540, 0xc28c, 0xa57f, 0xc28c, 0x21, 0 - .dw 0xa5c0, 0xc28c, 0xa5ff, 0xc28c, 0x21, 0 - .dw 0xa640, 0xc28c, 0xa67f, 0xc28c, 0x21, 0 - .dw 0xa6c0, 0xc28c, 0xa6ff, 0xc28c, 0x21, 0 - .dw 0xa740, 0xc28c, 0xa77f, 0xc28c, 0x21, 0 - .dw 0xa7c0, 0xc28c, 0xbfff, 0xc28c, 0x21, 0 - .dw 0xc040, 0xc28c, 0xc07f, 0xc28c, 0x21, 0 - .dw 0xc0c0, 0xc28c, 0xc0ff, 0xc28c, 0x21, 0 - .dw 0xc140, 0xc28c, 0xc17f, 0xc28c, 0x21, 0 - .dw 0xc1c0, 0xc28c, 0xdfff, 0xc28c, 0x21, 0 - .dw 0xe040, 0xc28c, 0xe07f, 0xc28c, 0x21, 0 - .dw 0xe0c0, 0xc28c, 0xe0ff, 0xc28c, 0x21, 0 - .dw 0xe140, 0xc28c, 0xe17f, 0xc28c, 0x21, 0 - .dw 0xe1c0, 0xc28c, 0xe1ff, 0xc28c, 0x21, 0 - .dw 0xe240, 0xc28c, 0xe27f, 0xc28c, 0x21, 0 - .dw 0xe2c0, 0xc28c, 0xe2ff, 0xc28c, 0x21, 0 - .dw 0xe340, 0xc28c, 0xe37f, 0xc28c, 0x21, 0 - .dw 0xe3c0, 0xc28c, 0xe3ff, 0xc28c, 0x21, 0 - .dw 0xe440, 0xc28c, 0xe47f, 0xc28c, 0x21, 0 - .dw 0xe4c0, 0xc28c, 0xe4ff, 0xc28c, 0x21, 0 - .dw 0xe540, 0xc28c, 0xe57f, 0xc28c, 0x21, 0 - .dw 0xe5c0, 0xc28c, 0xe5ff, 0xc28c, 0x21, 0 - .dw 0xe640, 0xc28c, 0xe67f, 0xc28c, 0x21, 0 - .dw 0xe6c0, 0xc28c, 0xe6ff, 0xc28c, 0x21, 0 - .dw 0xe740, 0xc28c, 0xe77f, 0xc28c, 0x21, 0 - .dw 0xe7c0, 0xc28c, 0xffff, 0xc293, 0x21, 0 - .dw 0x0200, 0xc294, 0x1fff, 0xc294, 0x21, 0 - .dw 0x2800, 0xc294, 0x3fff, 0xc294, 0x21, 0 - .dw 0x4200, 0xc294, 0x5fff, 0xc294, 0x21, 0 - .dw 0x6800, 0xc294, 0x7fff, 0xc294, 0x21, 0 - .dw 0x8200, 0xc294, 0x9fff, 0xc294, 0x21, 0 - .dw 0xa800, 0xc294, 0xbfff, 0xc294, 0x21, 0 - .dw 0xc200, 0xc294, 0xdfff, 0xc294, 0x21, 0 - .dw 0xe800, 0xc294, 0xffff, 0xc29b, 0x21, 0 - .dw 0x0040, 0xc29c, 0x007f, 0xc29c, 0x21, 0 - .dw 0x00c0, 0xc29c, 0x00ff, 0xc29c, 0x21, 0 - .dw 0x0140, 0xc29c, 0x017f, 0xc29c, 0x21, 0 - .dw 0x01c0, 0xc29c, 0x1fff, 0xc29c, 0x21, 0 - .dw 0x2040, 0xc29c, 0x207f, 0xc29c, 0x21, 0 - .dw 0x20c0, 0xc29c, 0x20ff, 0xc29c, 0x21, 0 - .dw 0x2140, 0xc29c, 0x217f, 0xc29c, 0x21, 0 - .dw 0x21c0, 0xc29c, 0x21ff, 0xc29c, 0x21, 0 - .dw 0x2240, 0xc29c, 0x227f, 0xc29c, 0x21, 0 - .dw 0x22c0, 0xc29c, 0x22ff, 0xc29c, 0x21, 0 - .dw 0x2340, 0xc29c, 0x237f, 0xc29c, 0x21, 0 - .dw 0x23c0, 0xc29c, 0x23ff, 0xc29c, 0x21, 0 - .dw 0x2440, 0xc29c, 0x247f, 0xc29c, 0x21, 0 - .dw 0x24c0, 0xc29c, 0x24ff, 0xc29c, 0x21, 0 - .dw 0x2540, 0xc29c, 0x257f, 0xc29c, 0x21, 0 - .dw 0x25c0, 0xc29c, 0x25ff, 0xc29c, 0x21, 0 - .dw 0x2640, 0xc29c, 0x267f, 0xc29c, 0x21, 0 - .dw 0x26c0, 0xc29c, 0x26ff, 0xc29c, 0x21, 0 - .dw 0x2740, 0xc29c, 0x277f, 0xc29c, 0x21, 0 - .dw 0x27c0, 0xc29c, 0x3fff, 0xc29c, 0x21, 0 - .dw 0x4040, 0xc29c, 0x407f, 0xc29c, 0x21, 0 - .dw 0x40c0, 0xc29c, 0x40ff, 0xc29c, 0x21, 0 - .dw 0x4140, 0xc29c, 0x417f, 0xc29c, 0x21, 0 - .dw 0x41c0, 0xc29c, 0x5fff, 0xc29c, 0x21, 0 - .dw 0x6040, 0xc29c, 0x607f, 0xc29c, 0x21, 0 - .dw 0x60c0, 0xc29c, 0x60ff, 0xc29c, 0x21, 0 - .dw 0x6140, 0xc29c, 0x617f, 0xc29c, 0x21, 0 - .dw 0x61c0, 0xc29c, 0x61ff, 0xc29c, 0x21, 0 - .dw 0x6240, 0xc29c, 0x627f, 0xc29c, 0x21, 0 - .dw 0x62c0, 0xc29c, 0x62ff, 0xc29c, 0x21, 0 - .dw 0x6340, 0xc29c, 0x637f, 0xc29c, 0x21, 0 - .dw 0x63c0, 0xc29c, 0x63ff, 0xc29c, 0x21, 0 - .dw 0x6440, 0xc29c, 0x647f, 0xc29c, 0x21, 0 - .dw 0x64c0, 0xc29c, 0x64ff, 0xc29c, 0x21, 0 - .dw 0x6540, 0xc29c, 0x657f, 0xc29c, 0x21, 0 - .dw 0x65c0, 0xc29c, 0x65ff, 0xc29c, 0x21, 0 - .dw 0x6640, 0xc29c, 0x667f, 0xc29c, 0x21, 0 - .dw 0x66c0, 0xc29c, 0x66ff, 0xc29c, 0x21, 0 - .dw 0x6740, 0xc29c, 0x677f, 0xc29c, 0x21, 0 - .dw 0x67c0, 0xc29c, 0x7fff, 0xc29c, 0x21, 0 - .dw 0x8040, 0xc29c, 0x807f, 0xc29c, 0x21, 0 - .dw 0x80c0, 0xc29c, 0x80ff, 0xc29c, 0x21, 0 - .dw 0x8140, 0xc29c, 0x817f, 0xc29c, 0x21, 0 - .dw 0x81c0, 0xc29c, 0x9fff, 0xc29c, 0x21, 0 - .dw 0xa040, 0xc29c, 0xa07f, 0xc29c, 0x21, 0 - .dw 0xa0c0, 0xc29c, 0xa0ff, 0xc29c, 0x21, 0 - .dw 0xa140, 0xc29c, 0xa17f, 0xc29c, 0x21, 0 - .dw 0xa1c0, 0xc29c, 0xa1ff, 0xc29c, 0x21, 0 - .dw 0xa240, 0xc29c, 0xa27f, 0xc29c, 0x21, 0 - .dw 0xa2c0, 0xc29c, 0xa2ff, 0xc29c, 0x21, 0 - .dw 0xa340, 0xc29c, 0xa37f, 0xc29c, 0x21, 0 - .dw 0xa3c0, 0xc29c, 0xa3ff, 0xc29c, 0x21, 0 - .dw 0xa440, 0xc29c, 0xa47f, 0xc29c, 0x21, 0 - .dw 0xa4c0, 0xc29c, 0xa4ff, 0xc29c, 0x21, 0 - .dw 0xa540, 0xc29c, 0xa57f, 0xc29c, 0x21, 0 - .dw 0xa5c0, 0xc29c, 0xa5ff, 0xc29c, 0x21, 0 - .dw 0xa640, 0xc29c, 0xa67f, 0xc29c, 0x21, 0 - .dw 0xa6c0, 0xc29c, 0xa6ff, 0xc29c, 0x21, 0 - .dw 0xa740, 0xc29c, 0xa77f, 0xc29c, 0x21, 0 - .dw 0xa7c0, 0xc29c, 0xbfff, 0xc29c, 0x21, 0 - .dw 0xc040, 0xc29c, 0xc07f, 0xc29c, 0x21, 0 - .dw 0xc0c0, 0xc29c, 0xc0ff, 0xc29c, 0x21, 0 - .dw 0xc140, 0xc29c, 0xc17f, 0xc29c, 0x21, 0 - .dw 0xc1c0, 0xc29c, 0xdfff, 0xc29c, 0x21, 0 - .dw 0xe040, 0xc29c, 0xe07f, 0xc29c, 0x21, 0 - .dw 0xe0c0, 0xc29c, 0xe0ff, 0xc29c, 0x21, 0 - .dw 0xe140, 0xc29c, 0xe17f, 0xc29c, 0x21, 0 - .dw 0xe1c0, 0xc29c, 0xe1ff, 0xc29c, 0x21, 0 - .dw 0xe240, 0xc29c, 0xe27f, 0xc29c, 0x21, 0 - .dw 0xe2c0, 0xc29c, 0xe2ff, 0xc29c, 0x21, 0 - .dw 0xe340, 0xc29c, 0xe37f, 0xc29c, 0x21, 0 - .dw 0xe3c0, 0xc29c, 0xe3ff, 0xc29c, 0x21, 0 - .dw 0xe440, 0xc29c, 0xe47f, 0xc29c, 0x21, 0 - .dw 0xe4c0, 0xc29c, 0xe4ff, 0xc29c, 0x21, 0 - .dw 0xe540, 0xc29c, 0xe57f, 0xc29c, 0x21, 0 - .dw 0xe5c0, 0xc29c, 0xe5ff, 0xc29c, 0x21, 0 - .dw 0xe640, 0xc29c, 0xe67f, 0xc29c, 0x21, 0 - .dw 0xe6c0, 0xc29c, 0xe6ff, 0xc29c, 0x21, 0 - .dw 0xe740, 0xc29c, 0xe77f, 0xc29c, 0x21, 0 - .dw 0xe7c0, 0xc29c, 0x1fff, 0xc2c0, 0x21, 0 - .dw 0x2800, 0xc2c0, 0xffff, 0xc2c3, 0x21, 0 - .dw 0x0200, 0xc2c4, 0x1fff, 0xc2c4, 0x21, 0 - .dw 0x2800, 0xc2c4, 0x3fff, 0xc2c4, 0x21, 0 - .dw 0x4200, 0xc2c4, 0x5fff, 0xc2c4, 0x21, 0 - .dw 0x6800, 0xc2c4, 0x7fff, 0xc2c4, 0x21, 0 - .dw 0x8200, 0xc2c4, 0x9fff, 0xc2c4, 0x21, 0 - .dw 0xa800, 0xc2c4, 0xbfff, 0xc2c4, 0x21, 0 - .dw 0xc200, 0xc2c4, 0xdfff, 0xc2c4, 0x21, 0 - .dw 0xe800, 0xc2c4, 0xffff, 0xc2d3, 0x21, 0 - .dw 0x0200, 0xc2d4, 0x1fff, 0xc2d4, 0x21, 0 - .dw 0x2800, 0xc2d4, 0x3fff, 0xc2d4, 0x21, 0 - .dw 0x4200, 0xc2d4, 0x5fff, 0xc2d4, 0x21, 0 - .dw 0x6800, 0xc2d4, 0x7fff, 0xc2d4, 0x21, 0 - .dw 0x8200, 0xc2d4, 0x9fff, 0xc2d4, 0x21, 0 - .dw 0xa800, 0xc2d4, 0xbfff, 0xc2d4, 0x21, 0 - .dw 0xc200, 0xc2d4, 0xdfff, 0xc2d4, 0x21, 0 - .dw 0xe800, 0xc2d4, 0x1fff, 0xc300, 0x21, 0 - .dw 0x2800, 0xc300, 0xffff, 0xc303, 0x21, 0 - .dw 0x0200, 0xc304, 0x1fff, 0xc304, 0x21, 0 - .dw 0x2800, 0xc304, 0x3fff, 0xc304, 0x21, 0 - .dw 0x4200, 0xc304, 0x5fff, 0xc304, 0x21, 0 - .dw 0x6800, 0xc304, 0x7fff, 0xc304, 0x21, 0 - .dw 0x8200, 0xc304, 0x9fff, 0xc304, 0x21, 0 - .dw 0xa800, 0xc304, 0xbfff, 0xc304, 0x21, 0 - .dw 0xc200, 0xc304, 0xdfff, 0xc304, 0x21, 0 - .dw 0xe800, 0xc304, 0x1fff, 0xc308, 0x21, 0 - .dw 0x2040, 0xc308, 0x207f, 0xc308, 0x21, 0 - .dw 0x20c0, 0xc308, 0x20ff, 0xc308, 0x21, 0 - .dw 0x2140, 0xc308, 0x217f, 0xc308, 0x21, 0 - .dw 0x21c0, 0xc308, 0x21ff, 0xc308, 0x21, 0 - .dw 0x2240, 0xc308, 0x227f, 0xc308, 0x21, 0 - .dw 0x22c0, 0xc308, 0x22ff, 0xc308, 0x21, 0 - .dw 0x2340, 0xc308, 0x237f, 0xc308, 0x21, 0 - .dw 0x23c0, 0xc308, 0x23ff, 0xc308, 0x21, 0 - .dw 0x2440, 0xc308, 0x247f, 0xc308, 0x21, 0 - .dw 0x24c0, 0xc308, 0x24ff, 0xc308, 0x21, 0 - .dw 0x2540, 0xc308, 0x257f, 0xc308, 0x21, 0 - .dw 0x25c0, 0xc308, 0x25ff, 0xc308, 0x21, 0 - .dw 0x2640, 0xc308, 0x267f, 0xc308, 0x21, 0 - .dw 0x26c0, 0xc308, 0x26ff, 0xc308, 0x21, 0 - .dw 0x2740, 0xc308, 0x277f, 0xc308, 0x21, 0 - .dw 0x27c0, 0xc308, 0xffff, 0xc30b, 0x21, 0 - .dw 0x0040, 0xc30c, 0x007f, 0xc30c, 0x21, 0 - .dw 0x00c0, 0xc30c, 0x00ff, 0xc30c, 0x21, 0 - .dw 0x0140, 0xc30c, 0x017f, 0xc30c, 0x21, 0 - .dw 0x01c0, 0xc30c, 0x1fff, 0xc30c, 0x21, 0 - .dw 0x2040, 0xc30c, 0x207f, 0xc30c, 0x21, 0 - .dw 0x20c0, 0xc30c, 0x20ff, 0xc30c, 0x21, 0 - .dw 0x2140, 0xc30c, 0x217f, 0xc30c, 0x21, 0 - .dw 0x21c0, 0xc30c, 0x21ff, 0xc30c, 0x21, 0 - .dw 0x2240, 0xc30c, 0x227f, 0xc30c, 0x21, 0 - .dw 0x22c0, 0xc30c, 0x22ff, 0xc30c, 0x21, 0 - .dw 0x2340, 0xc30c, 0x237f, 0xc30c, 0x21, 0 - .dw 0x23c0, 0xc30c, 0x23ff, 0xc30c, 0x21, 0 - .dw 0x2440, 0xc30c, 0x247f, 0xc30c, 0x21, 0 - .dw 0x24c0, 0xc30c, 0x24ff, 0xc30c, 0x21, 0 - .dw 0x2540, 0xc30c, 0x257f, 0xc30c, 0x21, 0 - .dw 0x25c0, 0xc30c, 0x25ff, 0xc30c, 0x21, 0 - .dw 0x2640, 0xc30c, 0x267f, 0xc30c, 0x21, 0 - .dw 0x26c0, 0xc30c, 0x26ff, 0xc30c, 0x21, 0 - .dw 0x2740, 0xc30c, 0x277f, 0xc30c, 0x21, 0 - .dw 0x27c0, 0xc30c, 0x3fff, 0xc30c, 0x21, 0 - .dw 0x4040, 0xc30c, 0x407f, 0xc30c, 0x21, 0 - .dw 0x40c0, 0xc30c, 0x40ff, 0xc30c, 0x21, 0 - .dw 0x4140, 0xc30c, 0x417f, 0xc30c, 0x21, 0 - .dw 0x41c0, 0xc30c, 0x5fff, 0xc30c, 0x21, 0 - .dw 0x6040, 0xc30c, 0x607f, 0xc30c, 0x21, 0 - .dw 0x60c0, 0xc30c, 0x60ff, 0xc30c, 0x21, 0 - .dw 0x6140, 0xc30c, 0x617f, 0xc30c, 0x21, 0 - .dw 0x61c0, 0xc30c, 0x61ff, 0xc30c, 0x21, 0 - .dw 0x6240, 0xc30c, 0x627f, 0xc30c, 0x21, 0 - .dw 0x62c0, 0xc30c, 0x62ff, 0xc30c, 0x21, 0 - .dw 0x6340, 0xc30c, 0x637f, 0xc30c, 0x21, 0 - .dw 0x63c0, 0xc30c, 0x63ff, 0xc30c, 0x21, 0 - .dw 0x6440, 0xc30c, 0x647f, 0xc30c, 0x21, 0 - .dw 0x64c0, 0xc30c, 0x64ff, 0xc30c, 0x21, 0 - .dw 0x6540, 0xc30c, 0x657f, 0xc30c, 0x21, 0 - .dw 0x65c0, 0xc30c, 0x65ff, 0xc30c, 0x21, 0 - .dw 0x6640, 0xc30c, 0x667f, 0xc30c, 0x21, 0 - .dw 0x66c0, 0xc30c, 0x66ff, 0xc30c, 0x21, 0 - .dw 0x6740, 0xc30c, 0x677f, 0xc30c, 0x21, 0 - .dw 0x67c0, 0xc30c, 0x7fff, 0xc30c, 0x21, 0 - .dw 0x8040, 0xc30c, 0x807f, 0xc30c, 0x21, 0 - .dw 0x80c0, 0xc30c, 0x80ff, 0xc30c, 0x21, 0 - .dw 0x8140, 0xc30c, 0x817f, 0xc30c, 0x21, 0 - .dw 0x81c0, 0xc30c, 0x9fff, 0xc30c, 0x21, 0 - .dw 0xa040, 0xc30c, 0xa07f, 0xc30c, 0x21, 0 - .dw 0xa0c0, 0xc30c, 0xa0ff, 0xc30c, 0x21, 0 - .dw 0xa140, 0xc30c, 0xa17f, 0xc30c, 0x21, 0 - .dw 0xa1c0, 0xc30c, 0xa1ff, 0xc30c, 0x21, 0 - .dw 0xa240, 0xc30c, 0xa27f, 0xc30c, 0x21, 0 - .dw 0xa2c0, 0xc30c, 0xa2ff, 0xc30c, 0x21, 0 - .dw 0xa340, 0xc30c, 0xa37f, 0xc30c, 0x21, 0 - .dw 0xa3c0, 0xc30c, 0xa3ff, 0xc30c, 0x21, 0 - .dw 0xa440, 0xc30c, 0xa47f, 0xc30c, 0x21, 0 - .dw 0xa4c0, 0xc30c, 0xa4ff, 0xc30c, 0x21, 0 - .dw 0xa540, 0xc30c, 0xa57f, 0xc30c, 0x21, 0 - .dw 0xa5c0, 0xc30c, 0xa5ff, 0xc30c, 0x21, 0 - .dw 0xa640, 0xc30c, 0xa67f, 0xc30c, 0x21, 0 - .dw 0xa6c0, 0xc30c, 0xa6ff, 0xc30c, 0x21, 0 - .dw 0xa740, 0xc30c, 0xa77f, 0xc30c, 0x21, 0 - .dw 0xa7c0, 0xc30c, 0xbfff, 0xc30c, 0x21, 0 - .dw 0xc040, 0xc30c, 0xc07f, 0xc30c, 0x21, 0 - .dw 0xc0c0, 0xc30c, 0xc0ff, 0xc30c, 0x21, 0 - .dw 0xc140, 0xc30c, 0xc17f, 0xc30c, 0x21, 0 - .dw 0xc1c0, 0xc30c, 0xdfff, 0xc30c, 0x21, 0 - .dw 0xe040, 0xc30c, 0xe07f, 0xc30c, 0x21, 0 - .dw 0xe0c0, 0xc30c, 0xe0ff, 0xc30c, 0x21, 0 - .dw 0xe140, 0xc30c, 0xe17f, 0xc30c, 0x21, 0 - .dw 0xe1c0, 0xc30c, 0xe1ff, 0xc30c, 0x21, 0 - .dw 0xe240, 0xc30c, 0xe27f, 0xc30c, 0x21, 0 - .dw 0xe2c0, 0xc30c, 0xe2ff, 0xc30c, 0x21, 0 - .dw 0xe340, 0xc30c, 0xe37f, 0xc30c, 0x21, 0 - .dw 0xe3c0, 0xc30c, 0xe3ff, 0xc30c, 0x21, 0 - .dw 0xe440, 0xc30c, 0xe47f, 0xc30c, 0x21, 0 - .dw 0xe4c0, 0xc30c, 0xe4ff, 0xc30c, 0x21, 0 - .dw 0xe540, 0xc30c, 0xe57f, 0xc30c, 0x21, 0 - .dw 0xe5c0, 0xc30c, 0xe5ff, 0xc30c, 0x21, 0 - .dw 0xe640, 0xc30c, 0xe67f, 0xc30c, 0x21, 0 - .dw 0xe6c0, 0xc30c, 0xe6ff, 0xc30c, 0x21, 0 - .dw 0xe740, 0xc30c, 0xe77f, 0xc30c, 0x21, 0 - .dw 0xe7c0, 0xc30c, 0xffff, 0xc313, 0x21, 0 - .dw 0x0200, 0xc314, 0x1fff, 0xc314, 0x21, 0 - .dw 0x2800, 0xc314, 0x3fff, 0xc314, 0x21, 0 - .dw 0x4200, 0xc314, 0x5fff, 0xc314, 0x21, 0 - .dw 0x6800, 0xc314, 0x7fff, 0xc314, 0x21, 0 - .dw 0x8200, 0xc314, 0x9fff, 0xc314, 0x21, 0 - .dw 0xa800, 0xc314, 0xbfff, 0xc314, 0x21, 0 - .dw 0xc200, 0xc314, 0xdfff, 0xc314, 0x21, 0 - .dw 0xe800, 0xc314, 0xffff, 0xc31b, 0x21, 0 - .dw 0x0040, 0xc31c, 0x007f, 0xc31c, 0x21, 0 - .dw 0x00c0, 0xc31c, 0x00ff, 0xc31c, 0x21, 0 - .dw 0x0140, 0xc31c, 0x017f, 0xc31c, 0x21, 0 - .dw 0x01c0, 0xc31c, 0x1fff, 0xc31c, 0x21, 0 - .dw 0x2040, 0xc31c, 0x207f, 0xc31c, 0x21, 0 - .dw 0x20c0, 0xc31c, 0x20ff, 0xc31c, 0x21, 0 - .dw 0x2140, 0xc31c, 0x217f, 0xc31c, 0x21, 0 - .dw 0x21c0, 0xc31c, 0x21ff, 0xc31c, 0x21, 0 - .dw 0x2240, 0xc31c, 0x227f, 0xc31c, 0x21, 0 - .dw 0x22c0, 0xc31c, 0x22ff, 0xc31c, 0x21, 0 - .dw 0x2340, 0xc31c, 0x237f, 0xc31c, 0x21, 0 - .dw 0x23c0, 0xc31c, 0x23ff, 0xc31c, 0x21, 0 - .dw 0x2440, 0xc31c, 0x247f, 0xc31c, 0x21, 0 - .dw 0x24c0, 0xc31c, 0x24ff, 0xc31c, 0x21, 0 - .dw 0x2540, 0xc31c, 0x257f, 0xc31c, 0x21, 0 - .dw 0x25c0, 0xc31c, 0x25ff, 0xc31c, 0x21, 0 - .dw 0x2640, 0xc31c, 0x267f, 0xc31c, 0x21, 0 - .dw 0x26c0, 0xc31c, 0x26ff, 0xc31c, 0x21, 0 - .dw 0x2740, 0xc31c, 0x277f, 0xc31c, 0x21, 0 - .dw 0x27c0, 0xc31c, 0x3fff, 0xc31c, 0x21, 0 - .dw 0x4040, 0xc31c, 0x407f, 0xc31c, 0x21, 0 - .dw 0x40c0, 0xc31c, 0x40ff, 0xc31c, 0x21, 0 - .dw 0x4140, 0xc31c, 0x417f, 0xc31c, 0x21, 0 - .dw 0x41c0, 0xc31c, 0x5fff, 0xc31c, 0x21, 0 - .dw 0x6040, 0xc31c, 0x607f, 0xc31c, 0x21, 0 - .dw 0x60c0, 0xc31c, 0x60ff, 0xc31c, 0x21, 0 - .dw 0x6140, 0xc31c, 0x617f, 0xc31c, 0x21, 0 - .dw 0x61c0, 0xc31c, 0x61ff, 0xc31c, 0x21, 0 - .dw 0x6240, 0xc31c, 0x627f, 0xc31c, 0x21, 0 - .dw 0x62c0, 0xc31c, 0x62ff, 0xc31c, 0x21, 0 - .dw 0x6340, 0xc31c, 0x637f, 0xc31c, 0x21, 0 - .dw 0x63c0, 0xc31c, 0x63ff, 0xc31c, 0x21, 0 - .dw 0x6440, 0xc31c, 0x647f, 0xc31c, 0x21, 0 - .dw 0x64c0, 0xc31c, 0x64ff, 0xc31c, 0x21, 0 - .dw 0x6540, 0xc31c, 0x657f, 0xc31c, 0x21, 0 - .dw 0x65c0, 0xc31c, 0x65ff, 0xc31c, 0x21, 0 - .dw 0x6640, 0xc31c, 0x667f, 0xc31c, 0x21, 0 - .dw 0x66c0, 0xc31c, 0x66ff, 0xc31c, 0x21, 0 - .dw 0x6740, 0xc31c, 0x677f, 0xc31c, 0x21, 0 - .dw 0x67c0, 0xc31c, 0x7fff, 0xc31c, 0x21, 0 - .dw 0x8040, 0xc31c, 0x807f, 0xc31c, 0x21, 0 - .dw 0x80c0, 0xc31c, 0x80ff, 0xc31c, 0x21, 0 - .dw 0x8140, 0xc31c, 0x817f, 0xc31c, 0x21, 0 - .dw 0x81c0, 0xc31c, 0x9fff, 0xc31c, 0x21, 0 - .dw 0xa040, 0xc31c, 0xa07f, 0xc31c, 0x21, 0 - .dw 0xa0c0, 0xc31c, 0xa0ff, 0xc31c, 0x21, 0 - .dw 0xa140, 0xc31c, 0xa17f, 0xc31c, 0x21, 0 - .dw 0xa1c0, 0xc31c, 0xa1ff, 0xc31c, 0x21, 0 - .dw 0xa240, 0xc31c, 0xa27f, 0xc31c, 0x21, 0 - .dw 0xa2c0, 0xc31c, 0xa2ff, 0xc31c, 0x21, 0 - .dw 0xa340, 0xc31c, 0xa37f, 0xc31c, 0x21, 0 - .dw 0xa3c0, 0xc31c, 0xa3ff, 0xc31c, 0x21, 0 - .dw 0xa440, 0xc31c, 0xa47f, 0xc31c, 0x21, 0 - .dw 0xa4c0, 0xc31c, 0xa4ff, 0xc31c, 0x21, 0 - .dw 0xa540, 0xc31c, 0xa57f, 0xc31c, 0x21, 0 - .dw 0xa5c0, 0xc31c, 0xa5ff, 0xc31c, 0x21, 0 - .dw 0xa640, 0xc31c, 0xa67f, 0xc31c, 0x21, 0 - .dw 0xa6c0, 0xc31c, 0xa6ff, 0xc31c, 0x21, 0 - .dw 0xa740, 0xc31c, 0xa77f, 0xc31c, 0x21, 0 - .dw 0xa7c0, 0xc31c, 0xbfff, 0xc31c, 0x21, 0 - .dw 0xc040, 0xc31c, 0xc07f, 0xc31c, 0x21, 0 - .dw 0xc0c0, 0xc31c, 0xc0ff, 0xc31c, 0x21, 0 - .dw 0xc140, 0xc31c, 0xc17f, 0xc31c, 0x21, 0 - .dw 0xc1c0, 0xc31c, 0xdfff, 0xc31c, 0x21, 0 - .dw 0xe040, 0xc31c, 0xe07f, 0xc31c, 0x21, 0 - .dw 0xe0c0, 0xc31c, 0xe0ff, 0xc31c, 0x21, 0 - .dw 0xe140, 0xc31c, 0xe17f, 0xc31c, 0x21, 0 - .dw 0xe1c0, 0xc31c, 0xe1ff, 0xc31c, 0x21, 0 - .dw 0xe240, 0xc31c, 0xe27f, 0xc31c, 0x21, 0 - .dw 0xe2c0, 0xc31c, 0xe2ff, 0xc31c, 0x21, 0 - .dw 0xe340, 0xc31c, 0xe37f, 0xc31c, 0x21, 0 - .dw 0xe3c0, 0xc31c, 0xe3ff, 0xc31c, 0x21, 0 - .dw 0xe440, 0xc31c, 0xe47f, 0xc31c, 0x21, 0 - .dw 0xe4c0, 0xc31c, 0xe4ff, 0xc31c, 0x21, 0 - .dw 0xe540, 0xc31c, 0xe57f, 0xc31c, 0x21, 0 - .dw 0xe5c0, 0xc31c, 0xe5ff, 0xc31c, 0x21, 0 - .dw 0xe640, 0xc31c, 0xe67f, 0xc31c, 0x21, 0 - .dw 0xe6c0, 0xc31c, 0xe6ff, 0xc31c, 0x21, 0 - .dw 0xe740, 0xc31c, 0xe77f, 0xc31c, 0x21, 0 - .dw 0xe7c0, 0xc31c, 0x1fff, 0xc320, 0x21, 0 - .dw 0x2800, 0xc320, 0xffff, 0xc323, 0x21, 0 - .dw 0x0200, 0xc324, 0x1fff, 0xc324, 0x21, 0 - .dw 0x2800, 0xc324, 0x3fff, 0xc324, 0x21, 0 - .dw 0x4200, 0xc324, 0x5fff, 0xc324, 0x21, 0 - .dw 0x6800, 0xc324, 0x7fff, 0xc324, 0x21, 0 - .dw 0x8200, 0xc324, 0x9fff, 0xc324, 0x21, 0 - .dw 0xa800, 0xc324, 0xbfff, 0xc324, 0x21, 0 - .dw 0xc200, 0xc324, 0xdfff, 0xc324, 0x21, 0 - .dw 0xe800, 0xc324, 0x1fff, 0xc328, 0x21, 0 - .dw 0x2040, 0xc328, 0x207f, 0xc328, 0x21, 0 - .dw 0x20c0, 0xc328, 0x20ff, 0xc328, 0x21, 0 - .dw 0x2140, 0xc328, 0x217f, 0xc328, 0x21, 0 - .dw 0x21c0, 0xc328, 0x21ff, 0xc328, 0x21, 0 - .dw 0x2240, 0xc328, 0x227f, 0xc328, 0x21, 0 - .dw 0x22c0, 0xc328, 0x22ff, 0xc328, 0x21, 0 - .dw 0x2340, 0xc328, 0x237f, 0xc328, 0x21, 0 - .dw 0x23c0, 0xc328, 0x23ff, 0xc328, 0x21, 0 - .dw 0x2440, 0xc328, 0x247f, 0xc328, 0x21, 0 - .dw 0x24c0, 0xc328, 0x24ff, 0xc328, 0x21, 0 - .dw 0x2540, 0xc328, 0x257f, 0xc328, 0x21, 0 - .dw 0x25c0, 0xc328, 0x25ff, 0xc328, 0x21, 0 - .dw 0x2640, 0xc328, 0x267f, 0xc328, 0x21, 0 - .dw 0x26c0, 0xc328, 0x26ff, 0xc328, 0x21, 0 - .dw 0x2740, 0xc328, 0x277f, 0xc328, 0x21, 0 - .dw 0x27c0, 0xc328, 0xffff, 0xc32b, 0x21, 0 - .dw 0x0040, 0xc32c, 0x007f, 0xc32c, 0x21, 0 - .dw 0x00c0, 0xc32c, 0x00ff, 0xc32c, 0x21, 0 - .dw 0x0140, 0xc32c, 0x017f, 0xc32c, 0x21, 0 - .dw 0x01c0, 0xc32c, 0x1fff, 0xc32c, 0x21, 0 - .dw 0x2040, 0xc32c, 0x207f, 0xc32c, 0x21, 0 - .dw 0x20c0, 0xc32c, 0x20ff, 0xc32c, 0x21, 0 - .dw 0x2140, 0xc32c, 0x217f, 0xc32c, 0x21, 0 - .dw 0x21c0, 0xc32c, 0x21ff, 0xc32c, 0x21, 0 - .dw 0x2240, 0xc32c, 0x227f, 0xc32c, 0x21, 0 - .dw 0x22c0, 0xc32c, 0x22ff, 0xc32c, 0x21, 0 - .dw 0x2340, 0xc32c, 0x237f, 0xc32c, 0x21, 0 - .dw 0x23c0, 0xc32c, 0x23ff, 0xc32c, 0x21, 0 - .dw 0x2440, 0xc32c, 0x247f, 0xc32c, 0x21, 0 - .dw 0x24c0, 0xc32c, 0x24ff, 0xc32c, 0x21, 0 - .dw 0x2540, 0xc32c, 0x257f, 0xc32c, 0x21, 0 - .dw 0x25c0, 0xc32c, 0x25ff, 0xc32c, 0x21, 0 - .dw 0x2640, 0xc32c, 0x267f, 0xc32c, 0x21, 0 - .dw 0x26c0, 0xc32c, 0x26ff, 0xc32c, 0x21, 0 - .dw 0x2740, 0xc32c, 0x277f, 0xc32c, 0x21, 0 - .dw 0x27c0, 0xc32c, 0x3fff, 0xc32c, 0x21, 0 - .dw 0x4040, 0xc32c, 0x407f, 0xc32c, 0x21, 0 - .dw 0x40c0, 0xc32c, 0x40ff, 0xc32c, 0x21, 0 - .dw 0x4140, 0xc32c, 0x417f, 0xc32c, 0x21, 0 - .dw 0x41c0, 0xc32c, 0x5fff, 0xc32c, 0x21, 0 - .dw 0x6040, 0xc32c, 0x607f, 0xc32c, 0x21, 0 - .dw 0x60c0, 0xc32c, 0x60ff, 0xc32c, 0x21, 0 - .dw 0x6140, 0xc32c, 0x617f, 0xc32c, 0x21, 0 - .dw 0x61c0, 0xc32c, 0x61ff, 0xc32c, 0x21, 0 - .dw 0x6240, 0xc32c, 0x627f, 0xc32c, 0x21, 0 - .dw 0x62c0, 0xc32c, 0x62ff, 0xc32c, 0x21, 0 - .dw 0x6340, 0xc32c, 0x637f, 0xc32c, 0x21, 0 - .dw 0x63c0, 0xc32c, 0x63ff, 0xc32c, 0x21, 0 - .dw 0x6440, 0xc32c, 0x647f, 0xc32c, 0x21, 0 - .dw 0x64c0, 0xc32c, 0x64ff, 0xc32c, 0x21, 0 - .dw 0x6540, 0xc32c, 0x657f, 0xc32c, 0x21, 0 - .dw 0x65c0, 0xc32c, 0x65ff, 0xc32c, 0x21, 0 - .dw 0x6640, 0xc32c, 0x667f, 0xc32c, 0x21, 0 - .dw 0x66c0, 0xc32c, 0x66ff, 0xc32c, 0x21, 0 - .dw 0x6740, 0xc32c, 0x677f, 0xc32c, 0x21, 0 - .dw 0x67c0, 0xc32c, 0x7fff, 0xc32c, 0x21, 0 - .dw 0x8040, 0xc32c, 0x807f, 0xc32c, 0x21, 0 - .dw 0x80c0, 0xc32c, 0x80ff, 0xc32c, 0x21, 0 - .dw 0x8140, 0xc32c, 0x817f, 0xc32c, 0x21, 0 - .dw 0x81c0, 0xc32c, 0x9fff, 0xc32c, 0x21, 0 - .dw 0xa040, 0xc32c, 0xa07f, 0xc32c, 0x21, 0 - .dw 0xa0c0, 0xc32c, 0xa0ff, 0xc32c, 0x21, 0 - .dw 0xa140, 0xc32c, 0xa17f, 0xc32c, 0x21, 0 - .dw 0xa1c0, 0xc32c, 0xa1ff, 0xc32c, 0x21, 0 - .dw 0xa240, 0xc32c, 0xa27f, 0xc32c, 0x21, 0 - .dw 0xa2c0, 0xc32c, 0xa2ff, 0xc32c, 0x21, 0 - .dw 0xa340, 0xc32c, 0xa37f, 0xc32c, 0x21, 0 - .dw 0xa3c0, 0xc32c, 0xa3ff, 0xc32c, 0x21, 0 - .dw 0xa440, 0xc32c, 0xa47f, 0xc32c, 0x21, 0 - .dw 0xa4c0, 0xc32c, 0xa4ff, 0xc32c, 0x21, 0 - .dw 0xa540, 0xc32c, 0xa57f, 0xc32c, 0x21, 0 - .dw 0xa5c0, 0xc32c, 0xa5ff, 0xc32c, 0x21, 0 - .dw 0xa640, 0xc32c, 0xa67f, 0xc32c, 0x21, 0 - .dw 0xa6c0, 0xc32c, 0xa6ff, 0xc32c, 0x21, 0 - .dw 0xa740, 0xc32c, 0xa77f, 0xc32c, 0x21, 0 - .dw 0xa7c0, 0xc32c, 0xbfff, 0xc32c, 0x21, 0 - .dw 0xc040, 0xc32c, 0xc07f, 0xc32c, 0x21, 0 - .dw 0xc0c0, 0xc32c, 0xc0ff, 0xc32c, 0x21, 0 - .dw 0xc140, 0xc32c, 0xc17f, 0xc32c, 0x21, 0 - .dw 0xc1c0, 0xc32c, 0xdfff, 0xc32c, 0x21, 0 - .dw 0xe040, 0xc32c, 0xe07f, 0xc32c, 0x21, 0 - .dw 0xe0c0, 0xc32c, 0xe0ff, 0xc32c, 0x21, 0 - .dw 0xe140, 0xc32c, 0xe17f, 0xc32c, 0x21, 0 - .dw 0xe1c0, 0xc32c, 0xe1ff, 0xc32c, 0x21, 0 - .dw 0xe240, 0xc32c, 0xe27f, 0xc32c, 0x21, 0 - .dw 0xe2c0, 0xc32c, 0xe2ff, 0xc32c, 0x21, 0 - .dw 0xe340, 0xc32c, 0xe37f, 0xc32c, 0x21, 0 - .dw 0xe3c0, 0xc32c, 0xe3ff, 0xc32c, 0x21, 0 - .dw 0xe440, 0xc32c, 0xe47f, 0xc32c, 0x21, 0 - .dw 0xe4c0, 0xc32c, 0xe4ff, 0xc32c, 0x21, 0 - .dw 0xe540, 0xc32c, 0xe57f, 0xc32c, 0x21, 0 - .dw 0xe5c0, 0xc32c, 0xe5ff, 0xc32c, 0x21, 0 - .dw 0xe640, 0xc32c, 0xe67f, 0xc32c, 0x21, 0 - .dw 0xe6c0, 0xc32c, 0xe6ff, 0xc32c, 0x21, 0 - .dw 0xe740, 0xc32c, 0xe77f, 0xc32c, 0x21, 0 - .dw 0xe7c0, 0xc32c, 0xffff, 0xc333, 0x21, 0 - .dw 0x0200, 0xc334, 0x1fff, 0xc334, 0x21, 0 - .dw 0x2800, 0xc334, 0x3fff, 0xc334, 0x21, 0 - .dw 0x4200, 0xc334, 0x5fff, 0xc334, 0x21, 0 - .dw 0x6800, 0xc334, 0x7fff, 0xc334, 0x21, 0 - .dw 0x8200, 0xc334, 0x9fff, 0xc334, 0x21, 0 - .dw 0xa800, 0xc334, 0xbfff, 0xc334, 0x21, 0 - .dw 0xc200, 0xc334, 0xdfff, 0xc334, 0x21, 0 - .dw 0xe800, 0xc334, 0xffff, 0xc33b, 0x21, 0 - .dw 0x0040, 0xc33c, 0x007f, 0xc33c, 0x21, 0 - .dw 0x00c0, 0xc33c, 0x00ff, 0xc33c, 0x21, 0 - .dw 0x0140, 0xc33c, 0x017f, 0xc33c, 0x21, 0 - .dw 0x01c0, 0xc33c, 0x1fff, 0xc33c, 0x21, 0 - .dw 0x2040, 0xc33c, 0x207f, 0xc33c, 0x21, 0 - .dw 0x20c0, 0xc33c, 0x20ff, 0xc33c, 0x21, 0 - .dw 0x2140, 0xc33c, 0x217f, 0xc33c, 0x21, 0 - .dw 0x21c0, 0xc33c, 0x21ff, 0xc33c, 0x21, 0 - .dw 0x2240, 0xc33c, 0x227f, 0xc33c, 0x21, 0 - .dw 0x22c0, 0xc33c, 0x22ff, 0xc33c, 0x21, 0 - .dw 0x2340, 0xc33c, 0x237f, 0xc33c, 0x21, 0 - .dw 0x23c0, 0xc33c, 0x23ff, 0xc33c, 0x21, 0 - .dw 0x2440, 0xc33c, 0x247f, 0xc33c, 0x21, 0 - .dw 0x24c0, 0xc33c, 0x24ff, 0xc33c, 0x21, 0 - .dw 0x2540, 0xc33c, 0x257f, 0xc33c, 0x21, 0 - .dw 0x25c0, 0xc33c, 0x25ff, 0xc33c, 0x21, 0 - .dw 0x2640, 0xc33c, 0x267f, 0xc33c, 0x21, 0 - .dw 0x26c0, 0xc33c, 0x26ff, 0xc33c, 0x21, 0 - .dw 0x2740, 0xc33c, 0x277f, 0xc33c, 0x21, 0 - .dw 0x27c0, 0xc33c, 0x3fff, 0xc33c, 0x21, 0 - .dw 0x4040, 0xc33c, 0x407f, 0xc33c, 0x21, 0 - .dw 0x40c0, 0xc33c, 0x40ff, 0xc33c, 0x21, 0 - .dw 0x4140, 0xc33c, 0x417f, 0xc33c, 0x21, 0 - .dw 0x41c0, 0xc33c, 0x5fff, 0xc33c, 0x21, 0 - .dw 0x6040, 0xc33c, 0x607f, 0xc33c, 0x21, 0 - .dw 0x60c0, 0xc33c, 0x60ff, 0xc33c, 0x21, 0 - .dw 0x6140, 0xc33c, 0x617f, 0xc33c, 0x21, 0 - .dw 0x61c0, 0xc33c, 0x61ff, 0xc33c, 0x21, 0 - .dw 0x6240, 0xc33c, 0x627f, 0xc33c, 0x21, 0 - .dw 0x62c0, 0xc33c, 0x62ff, 0xc33c, 0x21, 0 - .dw 0x6340, 0xc33c, 0x637f, 0xc33c, 0x21, 0 - .dw 0x63c0, 0xc33c, 0x63ff, 0xc33c, 0x21, 0 - .dw 0x6440, 0xc33c, 0x647f, 0xc33c, 0x21, 0 - .dw 0x64c0, 0xc33c, 0x64ff, 0xc33c, 0x21, 0 - .dw 0x6540, 0xc33c, 0x657f, 0xc33c, 0x21, 0 - .dw 0x65c0, 0xc33c, 0x65ff, 0xc33c, 0x21, 0 - .dw 0x6640, 0xc33c, 0x667f, 0xc33c, 0x21, 0 - .dw 0x66c0, 0xc33c, 0x66ff, 0xc33c, 0x21, 0 - .dw 0x6740, 0xc33c, 0x677f, 0xc33c, 0x21, 0 - .dw 0x67c0, 0xc33c, 0x7fff, 0xc33c, 0x21, 0 - .dw 0x8040, 0xc33c, 0x807f, 0xc33c, 0x21, 0 - .dw 0x80c0, 0xc33c, 0x80ff, 0xc33c, 0x21, 0 - .dw 0x8140, 0xc33c, 0x817f, 0xc33c, 0x21, 0 - .dw 0x81c0, 0xc33c, 0x9fff, 0xc33c, 0x21, 0 - .dw 0xa040, 0xc33c, 0xa07f, 0xc33c, 0x21, 0 - .dw 0xa0c0, 0xc33c, 0xa0ff, 0xc33c, 0x21, 0 - .dw 0xa140, 0xc33c, 0xa17f, 0xc33c, 0x21, 0 - .dw 0xa1c0, 0xc33c, 0xa1ff, 0xc33c, 0x21, 0 - .dw 0xa240, 0xc33c, 0xa27f, 0xc33c, 0x21, 0 - .dw 0xa2c0, 0xc33c, 0xa2ff, 0xc33c, 0x21, 0 - .dw 0xa340, 0xc33c, 0xa37f, 0xc33c, 0x21, 0 - .dw 0xa3c0, 0xc33c, 0xa3ff, 0xc33c, 0x21, 0 - .dw 0xa440, 0xc33c, 0xa47f, 0xc33c, 0x21, 0 - .dw 0xa4c0, 0xc33c, 0xa4ff, 0xc33c, 0x21, 0 - .dw 0xa540, 0xc33c, 0xa57f, 0xc33c, 0x21, 0 - .dw 0xa5c0, 0xc33c, 0xa5ff, 0xc33c, 0x21, 0 - .dw 0xa640, 0xc33c, 0xa67f, 0xc33c, 0x21, 0 - .dw 0xa6c0, 0xc33c, 0xa6ff, 0xc33c, 0x21, 0 - .dw 0xa740, 0xc33c, 0xa77f, 0xc33c, 0x21, 0 - .dw 0xa7c0, 0xc33c, 0xbfff, 0xc33c, 0x21, 0 - .dw 0xc040, 0xc33c, 0xc07f, 0xc33c, 0x21, 0 - .dw 0xc0c0, 0xc33c, 0xc0ff, 0xc33c, 0x21, 0 - .dw 0xc140, 0xc33c, 0xc17f, 0xc33c, 0x21, 0 - .dw 0xc1c0, 0xc33c, 0xdfff, 0xc33c, 0x21, 0 - .dw 0xe040, 0xc33c, 0xe07f, 0xc33c, 0x21, 0 - .dw 0xe0c0, 0xc33c, 0xe0ff, 0xc33c, 0x21, 0 - .dw 0xe140, 0xc33c, 0xe17f, 0xc33c, 0x21, 0 - .dw 0xe1c0, 0xc33c, 0xe1ff, 0xc33c, 0x21, 0 - .dw 0xe240, 0xc33c, 0xe27f, 0xc33c, 0x21, 0 - .dw 0xe2c0, 0xc33c, 0xe2ff, 0xc33c, 0x21, 0 - .dw 0xe340, 0xc33c, 0xe37f, 0xc33c, 0x21, 0 - .dw 0xe3c0, 0xc33c, 0xe3ff, 0xc33c, 0x21, 0 - .dw 0xe440, 0xc33c, 0xe47f, 0xc33c, 0x21, 0 - .dw 0xe4c0, 0xc33c, 0xe4ff, 0xc33c, 0x21, 0 - .dw 0xe540, 0xc33c, 0xe57f, 0xc33c, 0x21, 0 - .dw 0xe5c0, 0xc33c, 0xe5ff, 0xc33c, 0x21, 0 - .dw 0xe640, 0xc33c, 0xe67f, 0xc33c, 0x21, 0 - .dw 0xe6c0, 0xc33c, 0xe6ff, 0xc33c, 0x21, 0 - .dw 0xe740, 0xc33c, 0xe77f, 0xc33c, 0x21, 0 - .dw 0xe7c0, 0xc33c, 0x1fff, 0xc360, 0x21, 0 - .dw 0x2800, 0xc360, 0xffff, 0xc363, 0x21, 0 - .dw 0x0200, 0xc364, 0x1fff, 0xc364, 0x21, 0 - .dw 0x2800, 0xc364, 0x3fff, 0xc364, 0x21, 0 - .dw 0x4200, 0xc364, 0x5fff, 0xc364, 0x21, 0 - .dw 0x6800, 0xc364, 0x7fff, 0xc364, 0x21, 0 - .dw 0x8200, 0xc364, 0x9fff, 0xc364, 0x21, 0 - .dw 0xa800, 0xc364, 0xbfff, 0xc364, 0x21, 0 - .dw 0xc200, 0xc364, 0xdfff, 0xc364, 0x21, 0 - .dw 0xe800, 0xc364, 0xffff, 0xc373, 0x21, 0 - .dw 0x0200, 0xc374, 0x1fff, 0xc374, 0x21, 0 - .dw 0x2800, 0xc374, 0x3fff, 0xc374, 0x21, 0 - .dw 0x4200, 0xc374, 0x5fff, 0xc374, 0x21, 0 - .dw 0x6800, 0xc374, 0x7fff, 0xc374, 0x21, 0 - .dw 0x8200, 0xc374, 0x9fff, 0xc374, 0x21, 0 - .dw 0xa800, 0xc374, 0xbfff, 0xc374, 0x21, 0 - .dw 0xc200, 0xc374, 0xdfff, 0xc374, 0x21, 0 - .dw 0xe800, 0xc374, 0x1fff, 0xc380, 0x21, 0 - .dw 0x2800, 0xc380, 0xffff, 0xc383, 0x21, 0 - .dw 0x0200, 0xc384, 0x1fff, 0xc384, 0x21, 0 - .dw 0x2800, 0xc384, 0x3fff, 0xc384, 0x21, 0 - .dw 0x4200, 0xc384, 0x5fff, 0xc384, 0x21, 0 - .dw 0x6800, 0xc384, 0x7fff, 0xc384, 0x21, 0 - .dw 0x8200, 0xc384, 0x9fff, 0xc384, 0x21, 0 - .dw 0xa800, 0xc384, 0xbfff, 0xc384, 0x21, 0 - .dw 0xc200, 0xc384, 0xdfff, 0xc384, 0x21, 0 - .dw 0xe800, 0xc384, 0x1fff, 0xc388, 0x21, 0 - .dw 0x2040, 0xc388, 0x207f, 0xc388, 0x21, 0 - .dw 0x20c0, 0xc388, 0x20ff, 0xc388, 0x21, 0 - .dw 0x2140, 0xc388, 0x217f, 0xc388, 0x21, 0 - .dw 0x21c0, 0xc388, 0x21ff, 0xc388, 0x21, 0 - .dw 0x2240, 0xc388, 0x227f, 0xc388, 0x21, 0 - .dw 0x22c0, 0xc388, 0x22ff, 0xc388, 0x21, 0 - .dw 0x2340, 0xc388, 0x237f, 0xc388, 0x21, 0 - .dw 0x23c0, 0xc388, 0x23ff, 0xc388, 0x21, 0 - .dw 0x2440, 0xc388, 0x247f, 0xc388, 0x21, 0 - .dw 0x24c0, 0xc388, 0x24ff, 0xc388, 0x21, 0 - .dw 0x2540, 0xc388, 0x257f, 0xc388, 0x21, 0 - .dw 0x25c0, 0xc388, 0x25ff, 0xc388, 0x21, 0 - .dw 0x2640, 0xc388, 0x267f, 0xc388, 0x21, 0 - .dw 0x26c0, 0xc388, 0x26ff, 0xc388, 0x21, 0 - .dw 0x2740, 0xc388, 0x277f, 0xc388, 0x21, 0 - .dw 0x27c0, 0xc388, 0xffff, 0xc38b, 0x21, 0 - .dw 0x0040, 0xc38c, 0x007f, 0xc38c, 0x21, 0 - .dw 0x00c0, 0xc38c, 0x00ff, 0xc38c, 0x21, 0 - .dw 0x0140, 0xc38c, 0x017f, 0xc38c, 0x21, 0 - .dw 0x01c0, 0xc38c, 0x1fff, 0xc38c, 0x21, 0 - .dw 0x2040, 0xc38c, 0x207f, 0xc38c, 0x21, 0 - .dw 0x20c0, 0xc38c, 0x20ff, 0xc38c, 0x21, 0 - .dw 0x2140, 0xc38c, 0x217f, 0xc38c, 0x21, 0 - .dw 0x21c0, 0xc38c, 0x21ff, 0xc38c, 0x21, 0 - .dw 0x2240, 0xc38c, 0x227f, 0xc38c, 0x21, 0 - .dw 0x22c0, 0xc38c, 0x22ff, 0xc38c, 0x21, 0 - .dw 0x2340, 0xc38c, 0x237f, 0xc38c, 0x21, 0 - .dw 0x23c0, 0xc38c, 0x23ff, 0xc38c, 0x21, 0 - .dw 0x2440, 0xc38c, 0x247f, 0xc38c, 0x21, 0 - .dw 0x24c0, 0xc38c, 0x24ff, 0xc38c, 0x21, 0 - .dw 0x2540, 0xc38c, 0x257f, 0xc38c, 0x21, 0 - .dw 0x25c0, 0xc38c, 0x25ff, 0xc38c, 0x21, 0 - .dw 0x2640, 0xc38c, 0x267f, 0xc38c, 0x21, 0 - .dw 0x26c0, 0xc38c, 0x26ff, 0xc38c, 0x21, 0 - .dw 0x2740, 0xc38c, 0x277f, 0xc38c, 0x21, 0 - .dw 0x27c0, 0xc38c, 0x3fff, 0xc38c, 0x21, 0 - .dw 0x4040, 0xc38c, 0x407f, 0xc38c, 0x21, 0 - .dw 0x40c0, 0xc38c, 0x40ff, 0xc38c, 0x21, 0 - .dw 0x4140, 0xc38c, 0x417f, 0xc38c, 0x21, 0 - .dw 0x41c0, 0xc38c, 0x5fff, 0xc38c, 0x21, 0 - .dw 0x6040, 0xc38c, 0x607f, 0xc38c, 0x21, 0 - .dw 0x60c0, 0xc38c, 0x60ff, 0xc38c, 0x21, 0 - .dw 0x6140, 0xc38c, 0x617f, 0xc38c, 0x21, 0 - .dw 0x61c0, 0xc38c, 0x61ff, 0xc38c, 0x21, 0 - .dw 0x6240, 0xc38c, 0x627f, 0xc38c, 0x21, 0 - .dw 0x62c0, 0xc38c, 0x62ff, 0xc38c, 0x21, 0 - .dw 0x6340, 0xc38c, 0x637f, 0xc38c, 0x21, 0 - .dw 0x63c0, 0xc38c, 0x63ff, 0xc38c, 0x21, 0 - .dw 0x6440, 0xc38c, 0x647f, 0xc38c, 0x21, 0 - .dw 0x64c0, 0xc38c, 0x64ff, 0xc38c, 0x21, 0 - .dw 0x6540, 0xc38c, 0x657f, 0xc38c, 0x21, 0 - .dw 0x65c0, 0xc38c, 0x65ff, 0xc38c, 0x21, 0 - .dw 0x6640, 0xc38c, 0x667f, 0xc38c, 0x21, 0 - .dw 0x66c0, 0xc38c, 0x66ff, 0xc38c, 0x21, 0 - .dw 0x6740, 0xc38c, 0x677f, 0xc38c, 0x21, 0 - .dw 0x67c0, 0xc38c, 0x7fff, 0xc38c, 0x21, 0 - .dw 0x8040, 0xc38c, 0x807f, 0xc38c, 0x21, 0 - .dw 0x80c0, 0xc38c, 0x80ff, 0xc38c, 0x21, 0 - .dw 0x8140, 0xc38c, 0x817f, 0xc38c, 0x21, 0 - .dw 0x81c0, 0xc38c, 0x9fff, 0xc38c, 0x21, 0 - .dw 0xa040, 0xc38c, 0xa07f, 0xc38c, 0x21, 0 - .dw 0xa0c0, 0xc38c, 0xa0ff, 0xc38c, 0x21, 0 - .dw 0xa140, 0xc38c, 0xa17f, 0xc38c, 0x21, 0 - .dw 0xa1c0, 0xc38c, 0xa1ff, 0xc38c, 0x21, 0 - .dw 0xa240, 0xc38c, 0xa27f, 0xc38c, 0x21, 0 - .dw 0xa2c0, 0xc38c, 0xa2ff, 0xc38c, 0x21, 0 - .dw 0xa340, 0xc38c, 0xa37f, 0xc38c, 0x21, 0 - .dw 0xa3c0, 0xc38c, 0xa3ff, 0xc38c, 0x21, 0 - .dw 0xa440, 0xc38c, 0xa47f, 0xc38c, 0x21, 0 - .dw 0xa4c0, 0xc38c, 0xa4ff, 0xc38c, 0x21, 0 - .dw 0xa540, 0xc38c, 0xa57f, 0xc38c, 0x21, 0 - .dw 0xa5c0, 0xc38c, 0xa5ff, 0xc38c, 0x21, 0 - .dw 0xa640, 0xc38c, 0xa67f, 0xc38c, 0x21, 0 - .dw 0xa6c0, 0xc38c, 0xa6ff, 0xc38c, 0x21, 0 - .dw 0xa740, 0xc38c, 0xa77f, 0xc38c, 0x21, 0 - .dw 0xa7c0, 0xc38c, 0xbfff, 0xc38c, 0x21, 0 - .dw 0xc040, 0xc38c, 0xc07f, 0xc38c, 0x21, 0 - .dw 0xc0c0, 0xc38c, 0xc0ff, 0xc38c, 0x21, 0 - .dw 0xc140, 0xc38c, 0xc17f, 0xc38c, 0x21, 0 - .dw 0xc1c0, 0xc38c, 0xdfff, 0xc38c, 0x21, 0 - .dw 0xe040, 0xc38c, 0xe07f, 0xc38c, 0x21, 0 - .dw 0xe0c0, 0xc38c, 0xe0ff, 0xc38c, 0x21, 0 - .dw 0xe140, 0xc38c, 0xe17f, 0xc38c, 0x21, 0 - .dw 0xe1c0, 0xc38c, 0xe1ff, 0xc38c, 0x21, 0 - .dw 0xe240, 0xc38c, 0xe27f, 0xc38c, 0x21, 0 - .dw 0xe2c0, 0xc38c, 0xe2ff, 0xc38c, 0x21, 0 - .dw 0xe340, 0xc38c, 0xe37f, 0xc38c, 0x21, 0 - .dw 0xe3c0, 0xc38c, 0xe3ff, 0xc38c, 0x21, 0 - .dw 0xe440, 0xc38c, 0xe47f, 0xc38c, 0x21, 0 - .dw 0xe4c0, 0xc38c, 0xe4ff, 0xc38c, 0x21, 0 - .dw 0xe540, 0xc38c, 0xe57f, 0xc38c, 0x21, 0 - .dw 0xe5c0, 0xc38c, 0xe5ff, 0xc38c, 0x21, 0 - .dw 0xe640, 0xc38c, 0xe67f, 0xc38c, 0x21, 0 - .dw 0xe6c0, 0xc38c, 0xe6ff, 0xc38c, 0x21, 0 - .dw 0xe740, 0xc38c, 0xe77f, 0xc38c, 0x21, 0 - .dw 0xe7c0, 0xc38c, 0xffff, 0xc393, 0x21, 0 - .dw 0x0200, 0xc394, 0x1fff, 0xc394, 0x21, 0 - .dw 0x2800, 0xc394, 0x3fff, 0xc394, 0x21, 0 - .dw 0x4200, 0xc394, 0x5fff, 0xc394, 0x21, 0 - .dw 0x6800, 0xc394, 0x7fff, 0xc394, 0x21, 0 - .dw 0x8200, 0xc394, 0x9fff, 0xc394, 0x21, 0 - .dw 0xa800, 0xc394, 0xbfff, 0xc394, 0x21, 0 - .dw 0xc200, 0xc394, 0xdfff, 0xc394, 0x21, 0 - .dw 0xe800, 0xc394, 0xffff, 0xc39b, 0x21, 0 - .dw 0x0040, 0xc39c, 0x007f, 0xc39c, 0x21, 0 - .dw 0x00c0, 0xc39c, 0x00ff, 0xc39c, 0x21, 0 - .dw 0x0140, 0xc39c, 0x017f, 0xc39c, 0x21, 0 - .dw 0x01c0, 0xc39c, 0x1fff, 0xc39c, 0x21, 0 - .dw 0x2040, 0xc39c, 0x207f, 0xc39c, 0x21, 0 - .dw 0x20c0, 0xc39c, 0x20ff, 0xc39c, 0x21, 0 - .dw 0x2140, 0xc39c, 0x217f, 0xc39c, 0x21, 0 - .dw 0x21c0, 0xc39c, 0x21ff, 0xc39c, 0x21, 0 - .dw 0x2240, 0xc39c, 0x227f, 0xc39c, 0x21, 0 - .dw 0x22c0, 0xc39c, 0x22ff, 0xc39c, 0x21, 0 - .dw 0x2340, 0xc39c, 0x237f, 0xc39c, 0x21, 0 - .dw 0x23c0, 0xc39c, 0x23ff, 0xc39c, 0x21, 0 - .dw 0x2440, 0xc39c, 0x247f, 0xc39c, 0x21, 0 - .dw 0x24c0, 0xc39c, 0x24ff, 0xc39c, 0x21, 0 - .dw 0x2540, 0xc39c, 0x257f, 0xc39c, 0x21, 0 - .dw 0x25c0, 0xc39c, 0x25ff, 0xc39c, 0x21, 0 - .dw 0x2640, 0xc39c, 0x267f, 0xc39c, 0x21, 0 - .dw 0x26c0, 0xc39c, 0x26ff, 0xc39c, 0x21, 0 - .dw 0x2740, 0xc39c, 0x277f, 0xc39c, 0x21, 0 - .dw 0x27c0, 0xc39c, 0x3fff, 0xc39c, 0x21, 0 - .dw 0x4040, 0xc39c, 0x407f, 0xc39c, 0x21, 0 - .dw 0x40c0, 0xc39c, 0x40ff, 0xc39c, 0x21, 0 - .dw 0x4140, 0xc39c, 0x417f, 0xc39c, 0x21, 0 - .dw 0x41c0, 0xc39c, 0x5fff, 0xc39c, 0x21, 0 - .dw 0x6040, 0xc39c, 0x607f, 0xc39c, 0x21, 0 - .dw 0x60c0, 0xc39c, 0x60ff, 0xc39c, 0x21, 0 - .dw 0x6140, 0xc39c, 0x617f, 0xc39c, 0x21, 0 - .dw 0x61c0, 0xc39c, 0x61ff, 0xc39c, 0x21, 0 - .dw 0x6240, 0xc39c, 0x627f, 0xc39c, 0x21, 0 - .dw 0x62c0, 0xc39c, 0x62ff, 0xc39c, 0x21, 0 - .dw 0x6340, 0xc39c, 0x637f, 0xc39c, 0x21, 0 - .dw 0x63c0, 0xc39c, 0x63ff, 0xc39c, 0x21, 0 - .dw 0x6440, 0xc39c, 0x647f, 0xc39c, 0x21, 0 - .dw 0x64c0, 0xc39c, 0x64ff, 0xc39c, 0x21, 0 - .dw 0x6540, 0xc39c, 0x657f, 0xc39c, 0x21, 0 - .dw 0x65c0, 0xc39c, 0x65ff, 0xc39c, 0x21, 0 - .dw 0x6640, 0xc39c, 0x667f, 0xc39c, 0x21, 0 - .dw 0x66c0, 0xc39c, 0x66ff, 0xc39c, 0x21, 0 - .dw 0x6740, 0xc39c, 0x677f, 0xc39c, 0x21, 0 - .dw 0x67c0, 0xc39c, 0x7fff, 0xc39c, 0x21, 0 - .dw 0x8040, 0xc39c, 0x807f, 0xc39c, 0x21, 0 - .dw 0x80c0, 0xc39c, 0x80ff, 0xc39c, 0x21, 0 - .dw 0x8140, 0xc39c, 0x817f, 0xc39c, 0x21, 0 - .dw 0x81c0, 0xc39c, 0x9fff, 0xc39c, 0x21, 0 - .dw 0xa040, 0xc39c, 0xa07f, 0xc39c, 0x21, 0 - .dw 0xa0c0, 0xc39c, 0xa0ff, 0xc39c, 0x21, 0 - .dw 0xa140, 0xc39c, 0xa17f, 0xc39c, 0x21, 0 - .dw 0xa1c0, 0xc39c, 0xa1ff, 0xc39c, 0x21, 0 - .dw 0xa240, 0xc39c, 0xa27f, 0xc39c, 0x21, 0 - .dw 0xa2c0, 0xc39c, 0xa2ff, 0xc39c, 0x21, 0 - .dw 0xa340, 0xc39c, 0xa37f, 0xc39c, 0x21, 0 - .dw 0xa3c0, 0xc39c, 0xa3ff, 0xc39c, 0x21, 0 - .dw 0xa440, 0xc39c, 0xa47f, 0xc39c, 0x21, 0 - .dw 0xa4c0, 0xc39c, 0xa4ff, 0xc39c, 0x21, 0 - .dw 0xa540, 0xc39c, 0xa57f, 0xc39c, 0x21, 0 - .dw 0xa5c0, 0xc39c, 0xa5ff, 0xc39c, 0x21, 0 - .dw 0xa640, 0xc39c, 0xa67f, 0xc39c, 0x21, 0 - .dw 0xa6c0, 0xc39c, 0xa6ff, 0xc39c, 0x21, 0 - .dw 0xa740, 0xc39c, 0xa77f, 0xc39c, 0x21, 0 - .dw 0xa7c0, 0xc39c, 0xbfff, 0xc39c, 0x21, 0 - .dw 0xc040, 0xc39c, 0xc07f, 0xc39c, 0x21, 0 - .dw 0xc0c0, 0xc39c, 0xc0ff, 0xc39c, 0x21, 0 - .dw 0xc140, 0xc39c, 0xc17f, 0xc39c, 0x21, 0 - .dw 0xc1c0, 0xc39c, 0xdfff, 0xc39c, 0x21, 0 - .dw 0xe040, 0xc39c, 0xe07f, 0xc39c, 0x21, 0 - .dw 0xe0c0, 0xc39c, 0xe0ff, 0xc39c, 0x21, 0 - .dw 0xe140, 0xc39c, 0xe17f, 0xc39c, 0x21, 0 - .dw 0xe1c0, 0xc39c, 0xe1ff, 0xc39c, 0x21, 0 - .dw 0xe240, 0xc39c, 0xe27f, 0xc39c, 0x21, 0 - .dw 0xe2c0, 0xc39c, 0xe2ff, 0xc39c, 0x21, 0 - .dw 0xe340, 0xc39c, 0xe37f, 0xc39c, 0x21, 0 - .dw 0xe3c0, 0xc39c, 0xe3ff, 0xc39c, 0x21, 0 - .dw 0xe440, 0xc39c, 0xe47f, 0xc39c, 0x21, 0 - .dw 0xe4c0, 0xc39c, 0xe4ff, 0xc39c, 0x21, 0 - .dw 0xe540, 0xc39c, 0xe57f, 0xc39c, 0x21, 0 - .dw 0xe5c0, 0xc39c, 0xe5ff, 0xc39c, 0x21, 0 - .dw 0xe640, 0xc39c, 0xe67f, 0xc39c, 0x21, 0 - .dw 0xe6c0, 0xc39c, 0xe6ff, 0xc39c, 0x21, 0 - .dw 0xe740, 0xc39c, 0xe77f, 0xc39c, 0x21, 0 - .dw 0xe7c0, 0xc39c, 0xffff, 0xc3ff, 0x21, 0 - .dw 0x0000, 0xc401, 0x003f, 0xc401, 0x22, 0 - .dw 0x0240, 0xc401, 0x027f, 0xc401, 0x22, 0 - .dw 0x0480, 0xc401, 0x04bf, 0xc401, 0x22, 0 - .dw 0x06c0, 0xc401, 0x06ff, 0xc401, 0x22, 0 - .dw 0x0900, 0xc401, 0x093f, 0xc401, 0x22, 0 - .dw 0x0b40, 0xc401, 0x0b7f, 0xc401, 0x22, 0 - .dw 0x0d80, 0xc401, 0x0dbf, 0xc401, 0x22, 0 - .dw 0x0fc0, 0xc401, 0x103f, 0xc401, 0x22, 0 - .dw 0x1240, 0xc401, 0x127f, 0xc401, 0x22, 0 - .dw 0x1480, 0xc401, 0x14bf, 0xc401, 0x22, 0 - .dw 0x16c0, 0xc401, 0x16ff, 0xc401, 0x22, 0 - .dw 0x1900, 0xc401, 0x193f, 0xc401, 0x22, 0 - .dw 0x1b40, 0xc401, 0x1b7f, 0xc401, 0x22, 0 - .dw 0x1d80, 0xc401, 0x1dbf, 0xc401, 0x22, 0 - .dw 0x1fc0, 0xc401, 0x203f, 0xc401, 0x22, 0 - .dw 0x2240, 0xc401, 0x227f, 0xc401, 0x22, 0 - .dw 0x2480, 0xc401, 0x24bf, 0xc401, 0x22, 0 - .dw 0x26c0, 0xc401, 0x26ff, 0xc401, 0x22, 0 - .dw 0x2900, 0xc401, 0x293f, 0xc401, 0x22, 0 - .dw 0x2b40, 0xc401, 0x2b7f, 0xc401, 0x22, 0 - .dw 0x2d80, 0xc401, 0x2dbf, 0xc401, 0x22, 0 - .dw 0x2fc0, 0xc401, 0x303f, 0xc401, 0x22, 0 - .dw 0x3240, 0xc401, 0x327f, 0xc401, 0x22, 0 - .dw 0x3480, 0xc401, 0x34bf, 0xc401, 0x22, 0 - .dw 0x36c0, 0xc401, 0x36ff, 0xc401, 0x22, 0 - .dw 0x3900, 0xc401, 0x393f, 0xc401, 0x22, 0 - .dw 0x3b40, 0xc401, 0x3b7f, 0xc401, 0x22, 0 - .dw 0x3d80, 0xc401, 0x3dbf, 0xc401, 0x22, 0 - .dw 0x3fc0, 0xc401, 0x3fff, 0xc401, 0x22, 0 - .dw 0x4000, 0xc401, 0x7fff, 0xc401, 0x21, 0 - .dw 0x8000, 0xc401, 0x803f, 0xc401, 0x22, 0 - .dw 0x8240, 0xc401, 0x827f, 0xc401, 0x22, 0 - .dw 0x8480, 0xc401, 0x84bf, 0xc401, 0x22, 0 - .dw 0x86c0, 0xc401, 0x86ff, 0xc401, 0x22, 0 - .dw 0x8900, 0xc401, 0x893f, 0xc401, 0x22, 0 - .dw 0x8b40, 0xc401, 0x8b7f, 0xc401, 0x22, 0 - .dw 0x8d80, 0xc401, 0x8dbf, 0xc401, 0x22, 0 - .dw 0x8fc0, 0xc401, 0x903f, 0xc401, 0x22, 0 - .dw 0x9240, 0xc401, 0x927f, 0xc401, 0x22, 0 - .dw 0x9480, 0xc401, 0x94bf, 0xc401, 0x22, 0 - .dw 0x96c0, 0xc401, 0x96ff, 0xc401, 0x22, 0 - .dw 0x9900, 0xc401, 0x993f, 0xc401, 0x22, 0 - .dw 0x9b40, 0xc401, 0x9b7f, 0xc401, 0x22, 0 - .dw 0x9d80, 0xc401, 0x9dbf, 0xc401, 0x22, 0 - .dw 0x9fc0, 0xc401, 0xa03f, 0xc401, 0x22, 0 - .dw 0xa240, 0xc401, 0xa27f, 0xc401, 0x22, 0 - .dw 0xa480, 0xc401, 0xa4bf, 0xc401, 0x22, 0 - .dw 0xa6c0, 0xc401, 0xa6ff, 0xc401, 0x22, 0 - .dw 0xa900, 0xc401, 0xa93f, 0xc401, 0x22, 0 - .dw 0xab40, 0xc401, 0xab7f, 0xc401, 0x22, 0 - .dw 0xad80, 0xc401, 0xadbf, 0xc401, 0x22, 0 - .dw 0xafc0, 0xc401, 0xb03f, 0xc401, 0x22, 0 - .dw 0xb240, 0xc401, 0xb27f, 0xc401, 0x22, 0 - .dw 0xb480, 0xc401, 0xb4bf, 0xc401, 0x22, 0 - .dw 0xb6c0, 0xc401, 0xb6ff, 0xc401, 0x22, 0 - .dw 0xb900, 0xc401, 0xb93f, 0xc401, 0x22, 0 - .dw 0xbb40, 0xc401, 0xbb7f, 0xc401, 0x22, 0 - .dw 0xbd80, 0xc401, 0xbdbf, 0xc401, 0x22, 0 - .dw 0xbfc0, 0xc401, 0xc03f, 0xc401, 0x22, 0 - .dw 0xc240, 0xc401, 0xc27f, 0xc401, 0x22, 0 - .dw 0xc480, 0xc401, 0xc4bf, 0xc401, 0x22, 0 - .dw 0xc6c0, 0xc401, 0xc6ff, 0xc401, 0x22, 0 - .dw 0xc900, 0xc401, 0xc93f, 0xc401, 0x22, 0 - .dw 0xcb40, 0xc401, 0xcb7f, 0xc401, 0x22, 0 - .dw 0xcd80, 0xc401, 0xcdbf, 0xc401, 0x22, 0 - .dw 0xcfc0, 0xc401, 0xd03f, 0xc401, 0x22, 0 - .dw 0xd240, 0xc401, 0xd27f, 0xc401, 0x22, 0 - .dw 0xd480, 0xc401, 0xd4bf, 0xc401, 0x22, 0 - .dw 0xd6c0, 0xc401, 0xd6ff, 0xc401, 0x22, 0 - .dw 0xd900, 0xc401, 0xd93f, 0xc401, 0x22, 0 - .dw 0xdb40, 0xc401, 0xdb7f, 0xc401, 0x22, 0 - .dw 0xdd80, 0xc401, 0xddbf, 0xc401, 0x22, 0 - .dw 0xdfc0, 0xc401, 0xe03f, 0xc401, 0x22, 0 - .dw 0xe240, 0xc401, 0xe27f, 0xc401, 0x22, 0 - .dw 0xe480, 0xc401, 0xe4bf, 0xc401, 0x22, 0 - .dw 0xe6c0, 0xc401, 0xe6ff, 0xc401, 0x22, 0 - .dw 0xe900, 0xc401, 0xe93f, 0xc401, 0x22, 0 - .dw 0xeb40, 0xc401, 0xeb7f, 0xc401, 0x22, 0 - .dw 0xed80, 0xc401, 0xedbf, 0xc401, 0x22, 0 - .dw 0xefc0, 0xc401, 0xf03f, 0xc401, 0x22, 0 - .dw 0xf240, 0xc401, 0xf27f, 0xc401, 0x22, 0 - .dw 0xf480, 0xc401, 0xf4bf, 0xc401, 0x22, 0 - .dw 0xf6c0, 0xc401, 0xf6ff, 0xc401, 0x22, 0 - .dw 0xf900, 0xc401, 0xf93f, 0xc401, 0x22, 0 - .dw 0xfb40, 0xc401, 0xfb7f, 0xc401, 0x22, 0 - .dw 0xfd80, 0xc401, 0xfdbf, 0xc401, 0x22, 0 - .dw 0xffc0, 0xc401, 0xffff, 0xc401, 0x22, 0 - .dw 0x1000, 0xc402, 0x1fff, 0xc402, 0x21, 0 - .dw 0x3000, 0xc402, 0x3fff, 0xc402, 0x21, 0 - .dw 0x5000, 0xc402, 0x5fff, 0xc402, 0x21, 0 - .dw 0x7000, 0xc402, 0x7fff, 0xc402, 0x21, 0 - .dw 0x9000, 0xc402, 0x9fff, 0xc402, 0x21, 0 - .dw 0xb000, 0xc402, 0xbfff, 0xc402, 0x21, 0 - .dw 0xd000, 0xc402, 0xdfff, 0xc402, 0x21, 0 - .dw 0xf000, 0xc402, 0xffff, 0xc402, 0x21, 0 - .dw 0x1000, 0xc403, 0x1fff, 0xc403, 0x21, 0 - .dw 0x3000, 0xc403, 0x3fff, 0xc403, 0x21, 0 - .dw 0x5000, 0xc403, 0x5fff, 0xc403, 0x21, 0 - .dw 0x7000, 0xc403, 0x7fff, 0xc403, 0x21, 0 - .dw 0x9000, 0xc403, 0x9fff, 0xc403, 0x21, 0 - .dw 0xb000, 0xc403, 0xbfff, 0xc403, 0x21, 0 - .dw 0xd000, 0xc403, 0xdfff, 0xc403, 0x21, 0 - .dw 0xf000, 0xc403, 0xffff, 0xc403, 0x21, 0 - .dw 0x1000, 0xc404, 0x1fff, 0xc404, 0x21, 0 - .dw 0x3000, 0xc404, 0x3fff, 0xc404, 0x21, 0 - .dw 0x5000, 0xc404, 0x5fff, 0xc404, 0x21, 0 - .dw 0x7000, 0xc404, 0x7fff, 0xc404, 0x21, 0 - .dw 0x8000, 0xc404, 0x803f, 0xc404, 0x22, 0 - .dw 0x8240, 0xc404, 0x827f, 0xc404, 0x22, 0 - .dw 0x8480, 0xc404, 0x84bf, 0xc404, 0x22, 0 - .dw 0x86c0, 0xc404, 0x86ff, 0xc404, 0x22, 0 - .dw 0x8900, 0xc404, 0x893f, 0xc404, 0x22, 0 - .dw 0x8b40, 0xc404, 0x8b7f, 0xc404, 0x22, 0 - .dw 0x8d80, 0xc404, 0x8dbf, 0xc404, 0x22, 0 - .dw 0x8fc0, 0xc404, 0x8fff, 0xc404, 0x22, 0 - .dw 0x9000, 0xc404, 0x9fff, 0xc404, 0x21, 0 - .dw 0xa000, 0xc404, 0xa03f, 0xc404, 0x22, 0 - .dw 0xa240, 0xc404, 0xa27f, 0xc404, 0x22, 0 - .dw 0xa480, 0xc404, 0xa4bf, 0xc404, 0x22, 0 - .dw 0xa6c0, 0xc404, 0xa6ff, 0xc404, 0x22, 0 - .dw 0xa900, 0xc404, 0xa93f, 0xc404, 0x22, 0 - .dw 0xab40, 0xc404, 0xab7f, 0xc404, 0x22, 0 - .dw 0xad80, 0xc404, 0xadbf, 0xc404, 0x22, 0 - .dw 0xafc0, 0xc404, 0xafff, 0xc404, 0x22, 0 - .dw 0xb000, 0xc404, 0xffff, 0xc404, 0x21, 0 - .dw 0x1000, 0xc405, 0x3fff, 0xc405, 0x21, 0 - .dw 0x5000, 0xc405, 0x8fff, 0xc405, 0x21, 0 - .dw 0xa000, 0xc405, 0xcfff, 0xc405, 0x21, 0 - .dw 0xe000, 0xc405, 0xffff, 0xc405, 0x21, 0 - .dw 0x1000, 0xc406, 0x3fff, 0xc406, 0x21, 0 - .dw 0x5000, 0xc406, 0x7fff, 0xc406, 0x21, 0 - .dw 0x9000, 0xc406, 0xffff, 0xc406, 0x21, 0 - .dw 0x1000, 0xc407, 0x3fff, 0xc407, 0x21, 0 - .dw 0x5000, 0xc407, 0x7fff, 0xc407, 0x21, 0 - .dw 0x9000, 0xc407, 0xbfff, 0xc407, 0x21, 0 - .dw 0xd000, 0xc407, 0xdfff, 0xc407, 0x21, 0 - .dw 0xf000, 0xc407, 0xffff, 0xc407, 0x21, 0 - .dw 0x1000, 0xc408, 0x1fff, 0xc408, 0x21, 0 - .dw 0x3000, 0xc408, 0x3fff, 0xc408, 0x21, 0 - .dw 0x5000, 0xc408, 0x5fff, 0xc408, 0x21, 0 - .dw 0x7000, 0xc408, 0x7fff, 0xc408, 0x21, 0 - .dw 0x9000, 0xc408, 0x9fff, 0xc408, 0x21, 0 - .dw 0xb000, 0xc408, 0xbfff, 0xc408, 0x21, 0 - .dw 0xd000, 0xc408, 0xdfff, 0xc408, 0x21, 0 - .dw 0xf000, 0xc408, 0xffff, 0xc408, 0x21, 0 - .dw 0x1000, 0xc409, 0x1fff, 0xc409, 0x21, 0 - .dw 0x3000, 0xc409, 0x3fff, 0xc409, 0x21, 0 - .dw 0x5000, 0xc409, 0x7fff, 0xc409, 0x21, 0 - .dw 0x9000, 0xc409, 0x9fff, 0xc409, 0x21, 0 - .dw 0xb000, 0xc409, 0xbfff, 0xc409, 0x21, 0 - .dw 0xd000, 0xc409, 0xffff, 0xc409, 0x21, 0 - .dw 0x1000, 0xc40a, 0x3fff, 0xc40a, 0x21, 0 - .dw 0x5000, 0xc40a, 0xffff, 0xc40a, 0x21, 0 - .dw 0x1000, 0xc40b, 0x3fff, 0xc40b, 0x21, 0 - .dw 0x5000, 0xc40b, 0x7fff, 0xc40b, 0x21, 0 - .dw 0x9000, 0xc40b, 0x9fff, 0xc40b, 0x21, 0 - .dw 0xb000, 0xc40b, 0xbfff, 0xc40b, 0x21, 0 - .dw 0xd000, 0xc40b, 0xdfff, 0xc40b, 0x21, 0 - .dw 0xf000, 0xc40b, 0xffff, 0xc40b, 0x21, 0 - .dw 0x1000, 0xc40c, 0x3fff, 0xc40c, 0x21, 0 - .dw 0x4000, 0xc40c, 0x403f, 0xc40c, 0x22, 0 - .dw 0x4240, 0xc40c, 0x427f, 0xc40c, 0x22, 0 - .dw 0x4480, 0xc40c, 0x44bf, 0xc40c, 0x22, 0 - .dw 0x46c0, 0xc40c, 0x46ff, 0xc40c, 0x22, 0 - .dw 0x4900, 0xc40c, 0x493f, 0xc40c, 0x22, 0 - .dw 0x4b40, 0xc40c, 0x4b7f, 0xc40c, 0x22, 0 - .dw 0x4d80, 0xc40c, 0x4dbf, 0xc40c, 0x22, 0 - .dw 0x4fc0, 0xc40c, 0x4fff, 0xc40c, 0x22, 0 - .dw 0x5000, 0xc40c, 0xbfff, 0xc40c, 0x21, 0 - .dw 0xd000, 0xc40c, 0xffff, 0xc40c, 0x21, 0 - .dw 0x0000, 0xc40d, 0x003f, 0xc40d, 0x22, 0 - .dw 0x0240, 0xc40d, 0x027f, 0xc40d, 0x22, 0 - .dw 0x0480, 0xc40d, 0x04bf, 0xc40d, 0x22, 0 - .dw 0x06c0, 0xc40d, 0x06ff, 0xc40d, 0x22, 0 - .dw 0x0900, 0xc40d, 0x093f, 0xc40d, 0x22, 0 - .dw 0x0b40, 0xc40d, 0x0b7f, 0xc40d, 0x22, 0 - .dw 0x0d80, 0xc40d, 0x0dbf, 0xc40d, 0x22, 0 - .dw 0x0fc0, 0xc40d, 0x0fff, 0xc40d, 0x22, 0 - .dw 0x1000, 0xc40d, 0x3fff, 0xc40d, 0x21, 0 - .dw 0x4000, 0xc40d, 0x403f, 0xc40d, 0x22, 0 - .dw 0x4240, 0xc40d, 0x427f, 0xc40d, 0x22, 0 - .dw 0x4480, 0xc40d, 0x44bf, 0xc40d, 0x22, 0 - .dw 0x46c0, 0xc40d, 0x46ff, 0xc40d, 0x22, 0 - .dw 0x4900, 0xc40d, 0x493f, 0xc40d, 0x22, 0 - .dw 0x4b40, 0xc40d, 0x4b7f, 0xc40d, 0x22, 0 - .dw 0x4d80, 0xc40d, 0x4dbf, 0xc40d, 0x22, 0 - .dw 0x4fc0, 0xc40d, 0x4fff, 0xc40d, 0x22, 0 - .dw 0x5000, 0xc40d, 0x7fff, 0xc40d, 0x21, 0 - .dw 0x8000, 0xc40d, 0x803f, 0xc40d, 0x22, 0 - .dw 0x8240, 0xc40d, 0x827f, 0xc40d, 0x22, 0 - .dw 0x8480, 0xc40d, 0x84bf, 0xc40d, 0x22, 0 - .dw 0x86c0, 0xc40d, 0x86ff, 0xc40d, 0x22, 0 - .dw 0x8900, 0xc40d, 0x893f, 0xc40d, 0x22, 0 - .dw 0x8b40, 0xc40d, 0x8b7f, 0xc40d, 0x22, 0 - .dw 0x8d80, 0xc40d, 0x8dbf, 0xc40d, 0x22, 0 - .dw 0x8fc0, 0xc40d, 0x8fff, 0xc40d, 0x22, 0 - .dw 0x9000, 0xc40d, 0xbfff, 0xc40d, 0x21, 0 - .dw 0xc000, 0xc40d, 0xc03f, 0xc40d, 0x22, 0 - .dw 0xc240, 0xc40d, 0xc27f, 0xc40d, 0x22, 0 - .dw 0xc480, 0xc40d, 0xc4bf, 0xc40d, 0x22, 0 - .dw 0xc6c0, 0xc40d, 0xc6ff, 0xc40d, 0x22, 0 - .dw 0xc900, 0xc40d, 0xc93f, 0xc40d, 0x22, 0 - .dw 0xcb40, 0xc40d, 0xcb7f, 0xc40d, 0x22, 0 - .dw 0xcd80, 0xc40d, 0xcdbf, 0xc40d, 0x22, 0 - .dw 0xcfc0, 0xc40d, 0xcfff, 0xc40d, 0x22, 0 - .dw 0xd000, 0xc40d, 0xffff, 0xc40d, 0x21, 0 - .dw 0x1000, 0xc40e, 0x3fff, 0xc40e, 0x21, 0 - .dw 0x5000, 0xc40e, 0xbfff, 0xc40e, 0x21, 0 - .dw 0xd000, 0xc40e, 0xbfff, 0xc40f, 0x21, 0 - .dw 0xd000, 0xc40f, 0xffff, 0xc40f, 0x21, 0 - .dw 0x1000, 0xc410, 0x3fff, 0xc410, 0x21, 0 - .dw 0x5000, 0xc410, 0xbfff, 0xc410, 0x21, 0 - .dw 0xd000, 0xc410, 0xffff, 0xc410, 0x21, 0 - .dw 0x0000, 0xc411, 0x003f, 0xc411, 0x22, 0 - .dw 0x0240, 0xc411, 0x027f, 0xc411, 0x22, 0 - .dw 0x0480, 0xc411, 0x04bf, 0xc411, 0x22, 0 - .dw 0x06c0, 0xc411, 0x06ff, 0xc411, 0x22, 0 - .dw 0x0900, 0xc411, 0x093f, 0xc411, 0x22, 0 - .dw 0x0b40, 0xc411, 0x0b7f, 0xc411, 0x22, 0 - .dw 0x0d80, 0xc411, 0x0dbf, 0xc411, 0x22, 0 - .dw 0x0fc0, 0xc411, 0x0fff, 0xc411, 0x22, 0 - .dw 0x1000, 0xc411, 0x1fff, 0xc411, 0x21, 0 - .dw 0x2000, 0xc411, 0x203f, 0xc411, 0x22, 0 - .dw 0x2240, 0xc411, 0x227f, 0xc411, 0x22, 0 - .dw 0x2480, 0xc411, 0x24bf, 0xc411, 0x22, 0 - .dw 0x26c0, 0xc411, 0x26ff, 0xc411, 0x22, 0 - .dw 0x2900, 0xc411, 0x293f, 0xc411, 0x22, 0 - .dw 0x2b40, 0xc411, 0x2b7f, 0xc411, 0x22, 0 - .dw 0x2d80, 0xc411, 0x2dbf, 0xc411, 0x22, 0 - .dw 0x2fc0, 0xc411, 0x2fff, 0xc411, 0x22, 0 - .dw 0x3000, 0xc411, 0x3fff, 0xc411, 0x21, 0 - .dw 0x4000, 0xc411, 0x403f, 0xc411, 0x22, 0 - .dw 0x4240, 0xc411, 0x427f, 0xc411, 0x22, 0 - .dw 0x4480, 0xc411, 0x44bf, 0xc411, 0x22, 0 - .dw 0x46c0, 0xc411, 0x46ff, 0xc411, 0x22, 0 - .dw 0x4900, 0xc411, 0x493f, 0xc411, 0x22, 0 - .dw 0x4b40, 0xc411, 0x4b7f, 0xc411, 0x22, 0 - .dw 0x4d80, 0xc411, 0x4dbf, 0xc411, 0x22, 0 - .dw 0x4fc0, 0xc411, 0x4fff, 0xc411, 0x22, 0 - .dw 0x5000, 0xc411, 0x5fff, 0xc411, 0x21, 0 - .dw 0x6000, 0xc411, 0x603f, 0xc411, 0x22, 0 - .dw 0x6240, 0xc411, 0x627f, 0xc411, 0x22, 0 - .dw 0x6480, 0xc411, 0x64bf, 0xc411, 0x22, 0 - .dw 0x66c0, 0xc411, 0x66ff, 0xc411, 0x22, 0 - .dw 0x6900, 0xc411, 0x693f, 0xc411, 0x22, 0 - .dw 0x6b40, 0xc411, 0x6b7f, 0xc411, 0x22, 0 - .dw 0x6d80, 0xc411, 0x6dbf, 0xc411, 0x22, 0 - .dw 0x6fc0, 0xc411, 0x6fff, 0xc411, 0x22, 0 - .dw 0x7000, 0xc411, 0xffff, 0xc411, 0x21, 0 - .dw 0x0001, 0xc412, 0x0001, 0xc412, 0x21, 0 - .dw 0x0003, 0xc412, 0x000f, 0xc412, 0x21, 0 - .dw 0x0011, 0xc412, 0x0011, 0xc412, 0x21, 0 - .dw 0x0013, 0xc412, 0x003f, 0xc412, 0x21, 0 - .dw 0x0041, 0xc412, 0x0041, 0xc412, 0x21, 0 - .dw 0x0043, 0xc412, 0x004f, 0xc412, 0x21, 0 - .dw 0x0051, 0xc412, 0x0051, 0xc412, 0x21, 0 - .dw 0x0053, 0xc412, 0x007f, 0xc412, 0x21, 0 - .dw 0x0081, 0xc412, 0x0081, 0xc412, 0x21, 0 - .dw 0x0083, 0xc412, 0x008f, 0xc412, 0x21, 0 - .dw 0x0091, 0xc412, 0x0091, 0xc412, 0x21, 0 - .dw 0x0093, 0xc412, 0x00bf, 0xc412, 0x21, 0 - .dw 0x00c1, 0xc412, 0x00c1, 0xc412, 0x21, 0 - .dw 0x00c3, 0xc412, 0x00cf, 0xc412, 0x21, 0 - .dw 0x00d1, 0xc412, 0x00d1, 0xc412, 0x21, 0 - .dw 0x00d3, 0xc412, 0x00ff, 0xc412, 0x21, 0 - .dw 0x0101, 0xc412, 0x0101, 0xc412, 0x21, 0 - .dw 0x0103, 0xc412, 0x010f, 0xc412, 0x21, 0 - .dw 0x0111, 0xc412, 0x0111, 0xc412, 0x21, 0 - .dw 0x0113, 0xc412, 0x013f, 0xc412, 0x21, 0 - .dw 0x0141, 0xc412, 0x0141, 0xc412, 0x21, 0 - .dw 0x0143, 0xc412, 0x014f, 0xc412, 0x21, 0 - .dw 0x0151, 0xc412, 0x0151, 0xc412, 0x21, 0 - .dw 0x0153, 0xc412, 0x017f, 0xc412, 0x21, 0 - .dw 0x0181, 0xc412, 0x0181, 0xc412, 0x21, 0 - .dw 0x0183, 0xc412, 0x018f, 0xc412, 0x21, 0 - .dw 0x0191, 0xc412, 0x0191, 0xc412, 0x21, 0 - .dw 0x0193, 0xc412, 0x01bf, 0xc412, 0x21, 0 - .dw 0x01c1, 0xc412, 0x01c1, 0xc412, 0x21, 0 - .dw 0x01c3, 0xc412, 0x01cf, 0xc412, 0x21, 0 - .dw 0x01d1, 0xc412, 0x01d1, 0xc412, 0x21, 0 - .dw 0x01d3, 0xc412, 0x01ff, 0xc412, 0x21, 0 - .dw 0x0201, 0xc412, 0x0201, 0xc412, 0x21, 0 - .dw 0x0203, 0xc412, 0x020f, 0xc412, 0x21, 0 - .dw 0x0211, 0xc412, 0x0211, 0xc412, 0x21, 0 - .dw 0x0213, 0xc412, 0x023f, 0xc412, 0x21, 0 - .dw 0x0241, 0xc412, 0x0241, 0xc412, 0x21, 0 - .dw 0x0243, 0xc412, 0x024f, 0xc412, 0x21, 0 - .dw 0x0251, 0xc412, 0x0251, 0xc412, 0x21, 0 - .dw 0x0253, 0xc412, 0x027f, 0xc412, 0x21, 0 - .dw 0x0281, 0xc412, 0x0281, 0xc412, 0x21, 0 - .dw 0x0283, 0xc412, 0x028f, 0xc412, 0x21, 0 - .dw 0x0291, 0xc412, 0x0291, 0xc412, 0x21, 0 - .dw 0x0293, 0xc412, 0x02bf, 0xc412, 0x21, 0 - .dw 0x02c1, 0xc412, 0x02c1, 0xc412, 0x21, 0 - .dw 0x02c3, 0xc412, 0x02cf, 0xc412, 0x21, 0 - .dw 0x02d1, 0xc412, 0x02d1, 0xc412, 0x21, 0 - .dw 0x02d3, 0xc412, 0x02ff, 0xc412, 0x21, 0 - .dw 0x0301, 0xc412, 0x0301, 0xc412, 0x21, 0 - .dw 0x0303, 0xc412, 0x030f, 0xc412, 0x21, 0 - .dw 0x0311, 0xc412, 0x0311, 0xc412, 0x21, 0 - .dw 0x0313, 0xc412, 0x033f, 0xc412, 0x21, 0 - .dw 0x0341, 0xc412, 0x0341, 0xc412, 0x21, 0 - .dw 0x0343, 0xc412, 0x034f, 0xc412, 0x21, 0 - .dw 0x0351, 0xc412, 0x0351, 0xc412, 0x21, 0 - .dw 0x0353, 0xc412, 0x037f, 0xc412, 0x21, 0 - .dw 0x0381, 0xc412, 0x0381, 0xc412, 0x21, 0 - .dw 0x0383, 0xc412, 0x038f, 0xc412, 0x21, 0 - .dw 0x0391, 0xc412, 0x0391, 0xc412, 0x21, 0 - .dw 0x0393, 0xc412, 0x03bf, 0xc412, 0x21, 0 - .dw 0x03c1, 0xc412, 0x03c1, 0xc412, 0x21, 0 - .dw 0x03c3, 0xc412, 0x03cf, 0xc412, 0x21, 0 - .dw 0x03d1, 0xc412, 0x03d1, 0xc412, 0x21, 0 - .dw 0x03d3, 0xc412, 0x03ff, 0xc412, 0x21, 0 - .dw 0x0401, 0xc412, 0x0401, 0xc412, 0x21, 0 - .dw 0x0403, 0xc412, 0x040f, 0xc412, 0x21, 0 - .dw 0x0411, 0xc412, 0x0411, 0xc412, 0x21, 0 - .dw 0x0413, 0xc412, 0x043f, 0xc412, 0x21, 0 - .dw 0x0441, 0xc412, 0x0441, 0xc412, 0x21, 0 - .dw 0x0443, 0xc412, 0x044f, 0xc412, 0x21, 0 - .dw 0x0451, 0xc412, 0x0451, 0xc412, 0x21, 0 - .dw 0x0453, 0xc412, 0x047f, 0xc412, 0x21, 0 - .dw 0x0481, 0xc412, 0x0481, 0xc412, 0x21, 0 - .dw 0x0483, 0xc412, 0x048f, 0xc412, 0x21, 0 - .dw 0x0491, 0xc412, 0x0491, 0xc412, 0x21, 0 - .dw 0x0493, 0xc412, 0x04bf, 0xc412, 0x21, 0 - .dw 0x04c1, 0xc412, 0x04c1, 0xc412, 0x21, 0 - .dw 0x04c3, 0xc412, 0x04cf, 0xc412, 0x21, 0 - .dw 0x04d1, 0xc412, 0x04d1, 0xc412, 0x21, 0 - .dw 0x04d3, 0xc412, 0x04ff, 0xc412, 0x21, 0 - .dw 0x0501, 0xc412, 0x0501, 0xc412, 0x21, 0 - .dw 0x0503, 0xc412, 0x050f, 0xc412, 0x21, 0 - .dw 0x0511, 0xc412, 0x0511, 0xc412, 0x21, 0 - .dw 0x0513, 0xc412, 0x053f, 0xc412, 0x21, 0 - .dw 0x0541, 0xc412, 0x0541, 0xc412, 0x21, 0 - .dw 0x0543, 0xc412, 0x054f, 0xc412, 0x21, 0 - .dw 0x0551, 0xc412, 0x0551, 0xc412, 0x21, 0 - .dw 0x0553, 0xc412, 0x057f, 0xc412, 0x21, 0 - .dw 0x0581, 0xc412, 0x0581, 0xc412, 0x21, 0 - .dw 0x0583, 0xc412, 0x058f, 0xc412, 0x21, 0 - .dw 0x0591, 0xc412, 0x0591, 0xc412, 0x21, 0 - .dw 0x0593, 0xc412, 0x05bf, 0xc412, 0x21, 0 - .dw 0x05c1, 0xc412, 0x05c1, 0xc412, 0x21, 0 - .dw 0x05c3, 0xc412, 0x05cf, 0xc412, 0x21, 0 - .dw 0x05d1, 0xc412, 0x05d1, 0xc412, 0x21, 0 - .dw 0x05d3, 0xc412, 0x05ff, 0xc412, 0x21, 0 - .dw 0x0601, 0xc412, 0x0601, 0xc412, 0x21, 0 - .dw 0x0603, 0xc412, 0x060f, 0xc412, 0x21, 0 - .dw 0x0611, 0xc412, 0x0611, 0xc412, 0x21, 0 - .dw 0x0613, 0xc412, 0x063f, 0xc412, 0x21, 0 - .dw 0x0641, 0xc412, 0x0641, 0xc412, 0x21, 0 - .dw 0x0643, 0xc412, 0x064f, 0xc412, 0x21, 0 - .dw 0x0651, 0xc412, 0x0651, 0xc412, 0x21, 0 - .dw 0x0653, 0xc412, 0x067f, 0xc412, 0x21, 0 - .dw 0x0681, 0xc412, 0x0681, 0xc412, 0x21, 0 - .dw 0x0683, 0xc412, 0x068f, 0xc412, 0x21, 0 - .dw 0x0691, 0xc412, 0x0691, 0xc412, 0x21, 0 - .dw 0x0693, 0xc412, 0x06bf, 0xc412, 0x21, 0 - .dw 0x06c1, 0xc412, 0x06c1, 0xc412, 0x21, 0 - .dw 0x06c3, 0xc412, 0x06cf, 0xc412, 0x21, 0 - .dw 0x06d1, 0xc412, 0x06d1, 0xc412, 0x21, 0 - .dw 0x06d3, 0xc412, 0x06ff, 0xc412, 0x21, 0 - .dw 0x0701, 0xc412, 0x0701, 0xc412, 0x21, 0 - .dw 0x0703, 0xc412, 0x070f, 0xc412, 0x21, 0 - .dw 0x0711, 0xc412, 0x0711, 0xc412, 0x21, 0 - .dw 0x0713, 0xc412, 0x073f, 0xc412, 0x21, 0 - .dw 0x0741, 0xc412, 0x0741, 0xc412, 0x21, 0 - .dw 0x0743, 0xc412, 0x074f, 0xc412, 0x21, 0 - .dw 0x0751, 0xc412, 0x0751, 0xc412, 0x21, 0 - .dw 0x0753, 0xc412, 0x077f, 0xc412, 0x21, 0 - .dw 0x0781, 0xc412, 0x0781, 0xc412, 0x21, 0 - .dw 0x0783, 0xc412, 0x078f, 0xc412, 0x21, 0 - .dw 0x0791, 0xc412, 0x0791, 0xc412, 0x21, 0 - .dw 0x0793, 0xc412, 0x07bf, 0xc412, 0x21, 0 - .dw 0x07c1, 0xc412, 0x07c1, 0xc412, 0x21, 0 - .dw 0x07c3, 0xc412, 0x07cf, 0xc412, 0x21, 0 - .dw 0x07d1, 0xc412, 0x07d1, 0xc412, 0x21, 0 - .dw 0x07d3, 0xc412, 0x07ff, 0xc412, 0x21, 0 - .dw 0x0801, 0xc412, 0x0801, 0xc412, 0x21, 0 - .dw 0x0803, 0xc412, 0x080f, 0xc412, 0x21, 0 - .dw 0x0811, 0xc412, 0x0811, 0xc412, 0x21, 0 - .dw 0x0813, 0xc412, 0x083f, 0xc412, 0x21, 0 - .dw 0x0841, 0xc412, 0x0841, 0xc412, 0x21, 0 - .dw 0x0843, 0xc412, 0x084f, 0xc412, 0x21, 0 - .dw 0x0851, 0xc412, 0x0851, 0xc412, 0x21, 0 - .dw 0x0853, 0xc412, 0x087f, 0xc412, 0x21, 0 - .dw 0x0881, 0xc412, 0x0881, 0xc412, 0x21, 0 - .dw 0x0883, 0xc412, 0x088f, 0xc412, 0x21, 0 - .dw 0x0891, 0xc412, 0x0891, 0xc412, 0x21, 0 - .dw 0x0893, 0xc412, 0x08bf, 0xc412, 0x21, 0 - .dw 0x08c1, 0xc412, 0x08c1, 0xc412, 0x21, 0 - .dw 0x08c3, 0xc412, 0x08cf, 0xc412, 0x21, 0 - .dw 0x08d1, 0xc412, 0x08d1, 0xc412, 0x21, 0 - .dw 0x08d3, 0xc412, 0x08ff, 0xc412, 0x21, 0 - .dw 0x0901, 0xc412, 0x0901, 0xc412, 0x21, 0 - .dw 0x0903, 0xc412, 0x090f, 0xc412, 0x21, 0 - .dw 0x0911, 0xc412, 0x0911, 0xc412, 0x21, 0 - .dw 0x0913, 0xc412, 0x093f, 0xc412, 0x21, 0 - .dw 0x0941, 0xc412, 0x0941, 0xc412, 0x21, 0 - .dw 0x0943, 0xc412, 0x094f, 0xc412, 0x21, 0 - .dw 0x0951, 0xc412, 0x0951, 0xc412, 0x21, 0 - .dw 0x0953, 0xc412, 0x097f, 0xc412, 0x21, 0 - .dw 0x0981, 0xc412, 0x0981, 0xc412, 0x21, 0 - .dw 0x0983, 0xc412, 0x098f, 0xc412, 0x21, 0 - .dw 0x0991, 0xc412, 0x0991, 0xc412, 0x21, 0 - .dw 0x0993, 0xc412, 0x09bf, 0xc412, 0x21, 0 - .dw 0x09c1, 0xc412, 0x09c1, 0xc412, 0x21, 0 - .dw 0x09c3, 0xc412, 0x09cf, 0xc412, 0x21, 0 - .dw 0x09d1, 0xc412, 0x09d1, 0xc412, 0x21, 0 - .dw 0x09d3, 0xc412, 0x09ff, 0xc412, 0x21, 0 - .dw 0x0a01, 0xc412, 0x0a01, 0xc412, 0x21, 0 - .dw 0x0a03, 0xc412, 0x0a0f, 0xc412, 0x21, 0 - .dw 0x0a11, 0xc412, 0x0a11, 0xc412, 0x21, 0 - .dw 0x0a13, 0xc412, 0x0a3f, 0xc412, 0x21, 0 - .dw 0x0a41, 0xc412, 0x0a41, 0xc412, 0x21, 0 - .dw 0x0a43, 0xc412, 0x0a4f, 0xc412, 0x21, 0 - .dw 0x0a51, 0xc412, 0x0a51, 0xc412, 0x21, 0 - .dw 0x0a53, 0xc412, 0x0a7f, 0xc412, 0x21, 0 - .dw 0x0a81, 0xc412, 0x0a81, 0xc412, 0x21, 0 - .dw 0x0a83, 0xc412, 0x0a8f, 0xc412, 0x21, 0 - .dw 0x0a91, 0xc412, 0x0a91, 0xc412, 0x21, 0 - .dw 0x0a93, 0xc412, 0x0abf, 0xc412, 0x21, 0 - .dw 0x0ac1, 0xc412, 0x0ac1, 0xc412, 0x21, 0 - .dw 0x0ac3, 0xc412, 0x0acf, 0xc412, 0x21, 0 - .dw 0x0ad1, 0xc412, 0x0ad1, 0xc412, 0x21, 0 - .dw 0x0ad3, 0xc412, 0x0aff, 0xc412, 0x21, 0 - .dw 0x0b01, 0xc412, 0x0b01, 0xc412, 0x21, 0 - .dw 0x0b03, 0xc412, 0x0b0f, 0xc412, 0x21, 0 - .dw 0x0b11, 0xc412, 0x0b11, 0xc412, 0x21, 0 - .dw 0x0b13, 0xc412, 0x0b3f, 0xc412, 0x21, 0 - .dw 0x0b41, 0xc412, 0x0b41, 0xc412, 0x21, 0 - .dw 0x0b43, 0xc412, 0x0b4f, 0xc412, 0x21, 0 - .dw 0x0b51, 0xc412, 0x0b51, 0xc412, 0x21, 0 - .dw 0x0b53, 0xc412, 0x0b7f, 0xc412, 0x21, 0 - .dw 0x0b81, 0xc412, 0x0b81, 0xc412, 0x21, 0 - .dw 0x0b83, 0xc412, 0x0b8f, 0xc412, 0x21, 0 - .dw 0x0b91, 0xc412, 0x0b91, 0xc412, 0x21, 0 - .dw 0x0b93, 0xc412, 0x0bbf, 0xc412, 0x21, 0 - .dw 0x0bc1, 0xc412, 0x0bc1, 0xc412, 0x21, 0 - .dw 0x0bc3, 0xc412, 0x0bcf, 0xc412, 0x21, 0 - .dw 0x0bd1, 0xc412, 0x0bd1, 0xc412, 0x21, 0 - .dw 0x0bd3, 0xc412, 0x0bff, 0xc412, 0x21, 0 - .dw 0x0c01, 0xc412, 0x0c01, 0xc412, 0x21, 0 - .dw 0x0c03, 0xc412, 0x0c0f, 0xc412, 0x21, 0 - .dw 0x0c11, 0xc412, 0x0c11, 0xc412, 0x21, 0 - .dw 0x0c13, 0xc412, 0x0c3f, 0xc412, 0x21, 0 - .dw 0x0c41, 0xc412, 0x0c41, 0xc412, 0x21, 0 - .dw 0x0c43, 0xc412, 0x0c4f, 0xc412, 0x21, 0 - .dw 0x0c51, 0xc412, 0x0c51, 0xc412, 0x21, 0 - .dw 0x0c53, 0xc412, 0x0c7f, 0xc412, 0x21, 0 - .dw 0x0c81, 0xc412, 0x0c81, 0xc412, 0x21, 0 - .dw 0x0c83, 0xc412, 0x0c8f, 0xc412, 0x21, 0 - .dw 0x0c91, 0xc412, 0x0c91, 0xc412, 0x21, 0 - .dw 0x0c93, 0xc412, 0x0cbf, 0xc412, 0x21, 0 - .dw 0x0cc1, 0xc412, 0x0cc1, 0xc412, 0x21, 0 - .dw 0x0cc3, 0xc412, 0x0ccf, 0xc412, 0x21, 0 - .dw 0x0cd1, 0xc412, 0x0cd1, 0xc412, 0x21, 0 - .dw 0x0cd3, 0xc412, 0x0cff, 0xc412, 0x21, 0 - .dw 0x0d01, 0xc412, 0x0d01, 0xc412, 0x21, 0 - .dw 0x0d03, 0xc412, 0x0d0f, 0xc412, 0x21, 0 - .dw 0x0d11, 0xc412, 0x0d11, 0xc412, 0x21, 0 - .dw 0x0d13, 0xc412, 0x0d3f, 0xc412, 0x21, 0 - .dw 0x0d41, 0xc412, 0x0d41, 0xc412, 0x21, 0 - .dw 0x0d43, 0xc412, 0x0d4f, 0xc412, 0x21, 0 - .dw 0x0d51, 0xc412, 0x0d51, 0xc412, 0x21, 0 - .dw 0x0d53, 0xc412, 0x0d7f, 0xc412, 0x21, 0 - .dw 0x0d81, 0xc412, 0x0d81, 0xc412, 0x21, 0 - .dw 0x0d83, 0xc412, 0x0d8f, 0xc412, 0x21, 0 - .dw 0x0d91, 0xc412, 0x0d91, 0xc412, 0x21, 0 - .dw 0x0d93, 0xc412, 0x0dbf, 0xc412, 0x21, 0 - .dw 0x0dc1, 0xc412, 0x0dc1, 0xc412, 0x21, 0 - .dw 0x0dc3, 0xc412, 0x0dcf, 0xc412, 0x21, 0 - .dw 0x0dd1, 0xc412, 0x0dd1, 0xc412, 0x21, 0 - .dw 0x0dd3, 0xc412, 0x0dff, 0xc412, 0x21, 0 - .dw 0x0e01, 0xc412, 0x0e01, 0xc412, 0x21, 0 - .dw 0x0e03, 0xc412, 0x0e0f, 0xc412, 0x21, 0 - .dw 0x0e11, 0xc412, 0x0e11, 0xc412, 0x21, 0 - .dw 0x0e13, 0xc412, 0x0e3f, 0xc412, 0x21, 0 - .dw 0x0e41, 0xc412, 0x0e41, 0xc412, 0x21, 0 - .dw 0x0e43, 0xc412, 0x0e4f, 0xc412, 0x21, 0 - .dw 0x0e51, 0xc412, 0x0e51, 0xc412, 0x21, 0 - .dw 0x0e53, 0xc412, 0x0e7f, 0xc412, 0x21, 0 - .dw 0x0e81, 0xc412, 0x0e81, 0xc412, 0x21, 0 - .dw 0x0e83, 0xc412, 0x0e8f, 0xc412, 0x21, 0 - .dw 0x0e91, 0xc412, 0x0e91, 0xc412, 0x21, 0 - .dw 0x0e93, 0xc412, 0x0ebf, 0xc412, 0x21, 0 - .dw 0x0ec1, 0xc412, 0x0ec1, 0xc412, 0x21, 0 - .dw 0x0ec3, 0xc412, 0x0ecf, 0xc412, 0x21, 0 - .dw 0x0ed1, 0xc412, 0x0ed1, 0xc412, 0x21, 0 - .dw 0x0ed3, 0xc412, 0x0eff, 0xc412, 0x21, 0 - .dw 0x0f01, 0xc412, 0x0f01, 0xc412, 0x21, 0 - .dw 0x0f03, 0xc412, 0x0f0f, 0xc412, 0x21, 0 - .dw 0x0f11, 0xc412, 0x0f11, 0xc412, 0x21, 0 - .dw 0x0f13, 0xc412, 0x0f3f, 0xc412, 0x21, 0 - .dw 0x0f41, 0xc412, 0x0f41, 0xc412, 0x21, 0 - .dw 0x0f43, 0xc412, 0x0f4f, 0xc412, 0x21, 0 - .dw 0x0f51, 0xc412, 0x0f51, 0xc412, 0x21, 0 - .dw 0x0f53, 0xc412, 0x0f7f, 0xc412, 0x21, 0 - .dw 0x0f81, 0xc412, 0x0f81, 0xc412, 0x21, 0 - .dw 0x0f83, 0xc412, 0x0f8f, 0xc412, 0x21, 0 - .dw 0x0f91, 0xc412, 0x0f91, 0xc412, 0x21, 0 - .dw 0x0f93, 0xc412, 0x0fbf, 0xc412, 0x21, 0 - .dw 0x0fc1, 0xc412, 0x0fc1, 0xc412, 0x21, 0 - .dw 0x0fc3, 0xc412, 0x0fcf, 0xc412, 0x21, 0 - .dw 0x0fd1, 0xc412, 0x0fd1, 0xc412, 0x21, 0 - .dw 0x0fd3, 0xc412, 0x1fff, 0xc412, 0x21, 0 - .dw 0x2001, 0xc412, 0x2001, 0xc412, 0x21, 0 - .dw 0x2003, 0xc412, 0x200f, 0xc412, 0x21, 0 - .dw 0x2011, 0xc412, 0x2011, 0xc412, 0x21, 0 - .dw 0x2013, 0xc412, 0x203f, 0xc412, 0x21, 0 - .dw 0x2041, 0xc412, 0x2041, 0xc412, 0x21, 0 - .dw 0x2043, 0xc412, 0x204f, 0xc412, 0x21, 0 - .dw 0x2051, 0xc412, 0x2051, 0xc412, 0x21, 0 - .dw 0x2053, 0xc412, 0x207f, 0xc412, 0x21, 0 - .dw 0x2081, 0xc412, 0x2081, 0xc412, 0x21, 0 - .dw 0x2083, 0xc412, 0x208f, 0xc412, 0x21, 0 - .dw 0x2091, 0xc412, 0x2091, 0xc412, 0x21, 0 - .dw 0x2093, 0xc412, 0x20bf, 0xc412, 0x21, 0 - .dw 0x20c1, 0xc412, 0x20c1, 0xc412, 0x21, 0 - .dw 0x20c3, 0xc412, 0x20cf, 0xc412, 0x21, 0 - .dw 0x20d1, 0xc412, 0x20d1, 0xc412, 0x21, 0 - .dw 0x20d3, 0xc412, 0x20ff, 0xc412, 0x21, 0 - .dw 0x2101, 0xc412, 0x2101, 0xc412, 0x21, 0 - .dw 0x2103, 0xc412, 0x210f, 0xc412, 0x21, 0 - .dw 0x2111, 0xc412, 0x2111, 0xc412, 0x21, 0 - .dw 0x2113, 0xc412, 0x213f, 0xc412, 0x21, 0 - .dw 0x2141, 0xc412, 0x2141, 0xc412, 0x21, 0 - .dw 0x2143, 0xc412, 0x214f, 0xc412, 0x21, 0 - .dw 0x2151, 0xc412, 0x2151, 0xc412, 0x21, 0 - .dw 0x2153, 0xc412, 0x217f, 0xc412, 0x21, 0 - .dw 0x2181, 0xc412, 0x2181, 0xc412, 0x21, 0 - .dw 0x2183, 0xc412, 0x218f, 0xc412, 0x21, 0 - .dw 0x2191, 0xc412, 0x2191, 0xc412, 0x21, 0 - .dw 0x2193, 0xc412, 0x21bf, 0xc412, 0x21, 0 - .dw 0x21c1, 0xc412, 0x21c1, 0xc412, 0x21, 0 - .dw 0x21c3, 0xc412, 0x21cf, 0xc412, 0x21, 0 - .dw 0x21d1, 0xc412, 0x21d1, 0xc412, 0x21, 0 - .dw 0x21d3, 0xc412, 0x21ff, 0xc412, 0x21, 0 - .dw 0x2201, 0xc412, 0x2201, 0xc412, 0x21, 0 - .dw 0x2203, 0xc412, 0x220f, 0xc412, 0x21, 0 - .dw 0x2211, 0xc412, 0x2211, 0xc412, 0x21, 0 - .dw 0x2213, 0xc412, 0x223f, 0xc412, 0x21, 0 - .dw 0x2241, 0xc412, 0x2241, 0xc412, 0x21, 0 - .dw 0x2243, 0xc412, 0x224f, 0xc412, 0x21, 0 - .dw 0x2251, 0xc412, 0x2251, 0xc412, 0x21, 0 - .dw 0x2253, 0xc412, 0x227f, 0xc412, 0x21, 0 - .dw 0x2281, 0xc412, 0x2281, 0xc412, 0x21, 0 - .dw 0x2283, 0xc412, 0x228f, 0xc412, 0x21, 0 - .dw 0x2291, 0xc412, 0x2291, 0xc412, 0x21, 0 - .dw 0x2293, 0xc412, 0x22bf, 0xc412, 0x21, 0 - .dw 0x22c1, 0xc412, 0x22c1, 0xc412, 0x21, 0 - .dw 0x22c3, 0xc412, 0x22cf, 0xc412, 0x21, 0 - .dw 0x22d1, 0xc412, 0x22d1, 0xc412, 0x21, 0 - .dw 0x22d3, 0xc412, 0x22ff, 0xc412, 0x21, 0 - .dw 0x2301, 0xc412, 0x2301, 0xc412, 0x21, 0 - .dw 0x2303, 0xc412, 0x230f, 0xc412, 0x21, 0 - .dw 0x2311, 0xc412, 0x2311, 0xc412, 0x21, 0 - .dw 0x2313, 0xc412, 0x233f, 0xc412, 0x21, 0 - .dw 0x2341, 0xc412, 0x2341, 0xc412, 0x21, 0 - .dw 0x2343, 0xc412, 0x234f, 0xc412, 0x21, 0 - .dw 0x2351, 0xc412, 0x2351, 0xc412, 0x21, 0 - .dw 0x2353, 0xc412, 0x237f, 0xc412, 0x21, 0 - .dw 0x2381, 0xc412, 0x2381, 0xc412, 0x21, 0 - .dw 0x2383, 0xc412, 0x238f, 0xc412, 0x21, 0 - .dw 0x2391, 0xc412, 0x2391, 0xc412, 0x21, 0 - .dw 0x2393, 0xc412, 0x23bf, 0xc412, 0x21, 0 - .dw 0x23c1, 0xc412, 0x23c1, 0xc412, 0x21, 0 - .dw 0x23c3, 0xc412, 0x23cf, 0xc412, 0x21, 0 - .dw 0x23d1, 0xc412, 0x23d1, 0xc412, 0x21, 0 - .dw 0x23d3, 0xc412, 0x23ff, 0xc412, 0x21, 0 - .dw 0x2401, 0xc412, 0x2401, 0xc412, 0x21, 0 - .dw 0x2403, 0xc412, 0x240f, 0xc412, 0x21, 0 - .dw 0x2411, 0xc412, 0x2411, 0xc412, 0x21, 0 - .dw 0x2413, 0xc412, 0x243f, 0xc412, 0x21, 0 - .dw 0x2441, 0xc412, 0x2441, 0xc412, 0x21, 0 - .dw 0x2443, 0xc412, 0x244f, 0xc412, 0x21, 0 - .dw 0x2451, 0xc412, 0x2451, 0xc412, 0x21, 0 - .dw 0x2453, 0xc412, 0x247f, 0xc412, 0x21, 0 - .dw 0x2481, 0xc412, 0x2481, 0xc412, 0x21, 0 - .dw 0x2483, 0xc412, 0x248f, 0xc412, 0x21, 0 - .dw 0x2491, 0xc412, 0x2491, 0xc412, 0x21, 0 - .dw 0x2493, 0xc412, 0x24bf, 0xc412, 0x21, 0 - .dw 0x24c1, 0xc412, 0x24c1, 0xc412, 0x21, 0 - .dw 0x24c3, 0xc412, 0x24cf, 0xc412, 0x21, 0 - .dw 0x24d1, 0xc412, 0x24d1, 0xc412, 0x21, 0 - .dw 0x24d3, 0xc412, 0x24ff, 0xc412, 0x21, 0 - .dw 0x2501, 0xc412, 0x2501, 0xc412, 0x21, 0 - .dw 0x2503, 0xc412, 0x250f, 0xc412, 0x21, 0 - .dw 0x2511, 0xc412, 0x2511, 0xc412, 0x21, 0 - .dw 0x2513, 0xc412, 0x253f, 0xc412, 0x21, 0 - .dw 0x2541, 0xc412, 0x2541, 0xc412, 0x21, 0 - .dw 0x2543, 0xc412, 0x254f, 0xc412, 0x21, 0 - .dw 0x2551, 0xc412, 0x2551, 0xc412, 0x21, 0 - .dw 0x2553, 0xc412, 0x257f, 0xc412, 0x21, 0 - .dw 0x2581, 0xc412, 0x2581, 0xc412, 0x21, 0 - .dw 0x2583, 0xc412, 0x258f, 0xc412, 0x21, 0 - .dw 0x2591, 0xc412, 0x2591, 0xc412, 0x21, 0 - .dw 0x2593, 0xc412, 0x25bf, 0xc412, 0x21, 0 - .dw 0x25c1, 0xc412, 0x25c1, 0xc412, 0x21, 0 - .dw 0x25c3, 0xc412, 0x25cf, 0xc412, 0x21, 0 - .dw 0x25d1, 0xc412, 0x25d1, 0xc412, 0x21, 0 - .dw 0x25d3, 0xc412, 0x25ff, 0xc412, 0x21, 0 - .dw 0x2601, 0xc412, 0x2601, 0xc412, 0x21, 0 - .dw 0x2603, 0xc412, 0x260f, 0xc412, 0x21, 0 - .dw 0x2611, 0xc412, 0x2611, 0xc412, 0x21, 0 - .dw 0x2613, 0xc412, 0x263f, 0xc412, 0x21, 0 - .dw 0x2641, 0xc412, 0x2641, 0xc412, 0x21, 0 - .dw 0x2643, 0xc412, 0x264f, 0xc412, 0x21, 0 - .dw 0x2651, 0xc412, 0x2651, 0xc412, 0x21, 0 - .dw 0x2653, 0xc412, 0x267f, 0xc412, 0x21, 0 - .dw 0x2681, 0xc412, 0x2681, 0xc412, 0x21, 0 - .dw 0x2683, 0xc412, 0x268f, 0xc412, 0x21, 0 - .dw 0x2691, 0xc412, 0x2691, 0xc412, 0x21, 0 - .dw 0x2693, 0xc412, 0x26bf, 0xc412, 0x21, 0 - .dw 0x26c1, 0xc412, 0x26c1, 0xc412, 0x21, 0 - .dw 0x26c3, 0xc412, 0x26cf, 0xc412, 0x21, 0 - .dw 0x26d1, 0xc412, 0x26d1, 0xc412, 0x21, 0 - .dw 0x26d3, 0xc412, 0x26ff, 0xc412, 0x21, 0 - .dw 0x2701, 0xc412, 0x2701, 0xc412, 0x21, 0 - .dw 0x2703, 0xc412, 0x270f, 0xc412, 0x21, 0 - .dw 0x2711, 0xc412, 0x2711, 0xc412, 0x21, 0 - .dw 0x2713, 0xc412, 0x273f, 0xc412, 0x21, 0 - .dw 0x2741, 0xc412, 0x2741, 0xc412, 0x21, 0 - .dw 0x2743, 0xc412, 0x274f, 0xc412, 0x21, 0 - .dw 0x2751, 0xc412, 0x2751, 0xc412, 0x21, 0 - .dw 0x2753, 0xc412, 0x277f, 0xc412, 0x21, 0 - .dw 0x2781, 0xc412, 0x2781, 0xc412, 0x21, 0 - .dw 0x2783, 0xc412, 0x278f, 0xc412, 0x21, 0 - .dw 0x2791, 0xc412, 0x2791, 0xc412, 0x21, 0 - .dw 0x2793, 0xc412, 0x27bf, 0xc412, 0x21, 0 - .dw 0x27c1, 0xc412, 0x27c1, 0xc412, 0x21, 0 - .dw 0x27c3, 0xc412, 0x27cf, 0xc412, 0x21, 0 - .dw 0x27d1, 0xc412, 0x27d1, 0xc412, 0x21, 0 - .dw 0x27d3, 0xc412, 0x27ff, 0xc412, 0x21, 0 - .dw 0x2801, 0xc412, 0x2801, 0xc412, 0x21, 0 - .dw 0x2803, 0xc412, 0x280f, 0xc412, 0x21, 0 - .dw 0x2811, 0xc412, 0x2811, 0xc412, 0x21, 0 - .dw 0x2813, 0xc412, 0x283f, 0xc412, 0x21, 0 - .dw 0x2841, 0xc412, 0x2841, 0xc412, 0x21, 0 - .dw 0x2843, 0xc412, 0x284f, 0xc412, 0x21, 0 - .dw 0x2851, 0xc412, 0x2851, 0xc412, 0x21, 0 - .dw 0x2853, 0xc412, 0x287f, 0xc412, 0x21, 0 - .dw 0x2881, 0xc412, 0x2881, 0xc412, 0x21, 0 - .dw 0x2883, 0xc412, 0x288f, 0xc412, 0x21, 0 - .dw 0x2891, 0xc412, 0x2891, 0xc412, 0x21, 0 - .dw 0x2893, 0xc412, 0x28bf, 0xc412, 0x21, 0 - .dw 0x28c1, 0xc412, 0x28c1, 0xc412, 0x21, 0 - .dw 0x28c3, 0xc412, 0x28cf, 0xc412, 0x21, 0 - .dw 0x28d1, 0xc412, 0x28d1, 0xc412, 0x21, 0 - .dw 0x28d3, 0xc412, 0x28ff, 0xc412, 0x21, 0 - .dw 0x2901, 0xc412, 0x2901, 0xc412, 0x21, 0 - .dw 0x2903, 0xc412, 0x290f, 0xc412, 0x21, 0 - .dw 0x2911, 0xc412, 0x2911, 0xc412, 0x21, 0 - .dw 0x2913, 0xc412, 0x293f, 0xc412, 0x21, 0 - .dw 0x2941, 0xc412, 0x2941, 0xc412, 0x21, 0 - .dw 0x2943, 0xc412, 0x294f, 0xc412, 0x21, 0 - .dw 0x2951, 0xc412, 0x2951, 0xc412, 0x21, 0 - .dw 0x2953, 0xc412, 0x297f, 0xc412, 0x21, 0 - .dw 0x2981, 0xc412, 0x2981, 0xc412, 0x21, 0 - .dw 0x2983, 0xc412, 0x298f, 0xc412, 0x21, 0 - .dw 0x2991, 0xc412, 0x2991, 0xc412, 0x21, 0 - .dw 0x2993, 0xc412, 0x29bf, 0xc412, 0x21, 0 - .dw 0x29c1, 0xc412, 0x29c1, 0xc412, 0x21, 0 - .dw 0x29c3, 0xc412, 0x29cf, 0xc412, 0x21, 0 - .dw 0x29d1, 0xc412, 0x29d1, 0xc412, 0x21, 0 - .dw 0x29d3, 0xc412, 0x29ff, 0xc412, 0x21, 0 - .dw 0x2a01, 0xc412, 0x2a01, 0xc412, 0x21, 0 - .dw 0x2a03, 0xc412, 0x2a0f, 0xc412, 0x21, 0 - .dw 0x2a11, 0xc412, 0x2a11, 0xc412, 0x21, 0 - .dw 0x2a13, 0xc412, 0x2a3f, 0xc412, 0x21, 0 - .dw 0x2a41, 0xc412, 0x2a41, 0xc412, 0x21, 0 - .dw 0x2a43, 0xc412, 0x2a4f, 0xc412, 0x21, 0 - .dw 0x2a51, 0xc412, 0x2a51, 0xc412, 0x21, 0 - .dw 0x2a53, 0xc412, 0x2a7f, 0xc412, 0x21, 0 - .dw 0x2a81, 0xc412, 0x2a81, 0xc412, 0x21, 0 - .dw 0x2a83, 0xc412, 0x2a8f, 0xc412, 0x21, 0 - .dw 0x2a91, 0xc412, 0x2a91, 0xc412, 0x21, 0 - .dw 0x2a93, 0xc412, 0x2abf, 0xc412, 0x21, 0 - .dw 0x2ac1, 0xc412, 0x2ac1, 0xc412, 0x21, 0 - .dw 0x2ac3, 0xc412, 0x2acf, 0xc412, 0x21, 0 - .dw 0x2ad1, 0xc412, 0x2ad1, 0xc412, 0x21, 0 - .dw 0x2ad3, 0xc412, 0x2aff, 0xc412, 0x21, 0 - .dw 0x2b01, 0xc412, 0x2b01, 0xc412, 0x21, 0 - .dw 0x2b03, 0xc412, 0x2b0f, 0xc412, 0x21, 0 - .dw 0x2b11, 0xc412, 0x2b11, 0xc412, 0x21, 0 - .dw 0x2b13, 0xc412, 0x2b3f, 0xc412, 0x21, 0 - .dw 0x2b41, 0xc412, 0x2b41, 0xc412, 0x21, 0 - .dw 0x2b43, 0xc412, 0x2b4f, 0xc412, 0x21, 0 - .dw 0x2b51, 0xc412, 0x2b51, 0xc412, 0x21, 0 - .dw 0x2b53, 0xc412, 0x2b7f, 0xc412, 0x21, 0 - .dw 0x2b81, 0xc412, 0x2b81, 0xc412, 0x21, 0 - .dw 0x2b83, 0xc412, 0x2b8f, 0xc412, 0x21, 0 - .dw 0x2b91, 0xc412, 0x2b91, 0xc412, 0x21, 0 - .dw 0x2b93, 0xc412, 0x2bbf, 0xc412, 0x21, 0 - .dw 0x2bc1, 0xc412, 0x2bc1, 0xc412, 0x21, 0 - .dw 0x2bc3, 0xc412, 0x2bcf, 0xc412, 0x21, 0 - .dw 0x2bd1, 0xc412, 0x2bd1, 0xc412, 0x21, 0 - .dw 0x2bd3, 0xc412, 0x2bff, 0xc412, 0x21, 0 - .dw 0x2c01, 0xc412, 0x2c01, 0xc412, 0x21, 0 - .dw 0x2c03, 0xc412, 0x2c0f, 0xc412, 0x21, 0 - .dw 0x2c11, 0xc412, 0x2c11, 0xc412, 0x21, 0 - .dw 0x2c13, 0xc412, 0x2c3f, 0xc412, 0x21, 0 - .dw 0x2c41, 0xc412, 0x2c41, 0xc412, 0x21, 0 - .dw 0x2c43, 0xc412, 0x2c4f, 0xc412, 0x21, 0 - .dw 0x2c51, 0xc412, 0x2c51, 0xc412, 0x21, 0 - .dw 0x2c53, 0xc412, 0x2c7f, 0xc412, 0x21, 0 - .dw 0x2c81, 0xc412, 0x2c81, 0xc412, 0x21, 0 - .dw 0x2c83, 0xc412, 0x2c8f, 0xc412, 0x21, 0 - .dw 0x2c91, 0xc412, 0x2c91, 0xc412, 0x21, 0 - .dw 0x2c93, 0xc412, 0x2cbf, 0xc412, 0x21, 0 - .dw 0x2cc1, 0xc412, 0x2cc1, 0xc412, 0x21, 0 - .dw 0x2cc3, 0xc412, 0x2ccf, 0xc412, 0x21, 0 - .dw 0x2cd1, 0xc412, 0x2cd1, 0xc412, 0x21, 0 - .dw 0x2cd3, 0xc412, 0x2cff, 0xc412, 0x21, 0 - .dw 0x2d01, 0xc412, 0x2d01, 0xc412, 0x21, 0 - .dw 0x2d03, 0xc412, 0x2d0f, 0xc412, 0x21, 0 - .dw 0x2d11, 0xc412, 0x2d11, 0xc412, 0x21, 0 - .dw 0x2d13, 0xc412, 0x2d3f, 0xc412, 0x21, 0 - .dw 0x2d41, 0xc412, 0x2d41, 0xc412, 0x21, 0 - .dw 0x2d43, 0xc412, 0x2d4f, 0xc412, 0x21, 0 - .dw 0x2d51, 0xc412, 0x2d51, 0xc412, 0x21, 0 - .dw 0x2d53, 0xc412, 0x2d7f, 0xc412, 0x21, 0 - .dw 0x2d81, 0xc412, 0x2d81, 0xc412, 0x21, 0 - .dw 0x2d83, 0xc412, 0x2d8f, 0xc412, 0x21, 0 - .dw 0x2d91, 0xc412, 0x2d91, 0xc412, 0x21, 0 - .dw 0x2d93, 0xc412, 0x2dbf, 0xc412, 0x21, 0 - .dw 0x2dc1, 0xc412, 0x2dc1, 0xc412, 0x21, 0 - .dw 0x2dc3, 0xc412, 0x2dcf, 0xc412, 0x21, 0 - .dw 0x2dd1, 0xc412, 0x2dd1, 0xc412, 0x21, 0 - .dw 0x2dd3, 0xc412, 0x2dff, 0xc412, 0x21, 0 - .dw 0x2e01, 0xc412, 0x2e01, 0xc412, 0x21, 0 - .dw 0x2e03, 0xc412, 0x2e0f, 0xc412, 0x21, 0 - .dw 0x2e11, 0xc412, 0x2e11, 0xc412, 0x21, 0 - .dw 0x2e13, 0xc412, 0x2e3f, 0xc412, 0x21, 0 - .dw 0x2e41, 0xc412, 0x2e41, 0xc412, 0x21, 0 - .dw 0x2e43, 0xc412, 0x2e4f, 0xc412, 0x21, 0 - .dw 0x2e51, 0xc412, 0x2e51, 0xc412, 0x21, 0 - .dw 0x2e53, 0xc412, 0x2e7f, 0xc412, 0x21, 0 - .dw 0x2e81, 0xc412, 0x2e81, 0xc412, 0x21, 0 - .dw 0x2e83, 0xc412, 0x2e8f, 0xc412, 0x21, 0 - .dw 0x2e91, 0xc412, 0x2e91, 0xc412, 0x21, 0 - .dw 0x2e93, 0xc412, 0x2ebf, 0xc412, 0x21, 0 - .dw 0x2ec1, 0xc412, 0x2ec1, 0xc412, 0x21, 0 - .dw 0x2ec3, 0xc412, 0x2ecf, 0xc412, 0x21, 0 - .dw 0x2ed1, 0xc412, 0x2ed1, 0xc412, 0x21, 0 - .dw 0x2ed3, 0xc412, 0x2eff, 0xc412, 0x21, 0 - .dw 0x2f01, 0xc412, 0x2f01, 0xc412, 0x21, 0 - .dw 0x2f03, 0xc412, 0x2f0f, 0xc412, 0x21, 0 - .dw 0x2f11, 0xc412, 0x2f11, 0xc412, 0x21, 0 - .dw 0x2f13, 0xc412, 0x2f3f, 0xc412, 0x21, 0 - .dw 0x2f41, 0xc412, 0x2f41, 0xc412, 0x21, 0 - .dw 0x2f43, 0xc412, 0x2f4f, 0xc412, 0x21, 0 - .dw 0x2f51, 0xc412, 0x2f51, 0xc412, 0x21, 0 - .dw 0x2f53, 0xc412, 0x2f7f, 0xc412, 0x21, 0 - .dw 0x2f81, 0xc412, 0x2f81, 0xc412, 0x21, 0 - .dw 0x2f83, 0xc412, 0x2f8f, 0xc412, 0x21, 0 - .dw 0x2f91, 0xc412, 0x2f91, 0xc412, 0x21, 0 - .dw 0x2f93, 0xc412, 0x2fbf, 0xc412, 0x21, 0 - .dw 0x2fc1, 0xc412, 0x2fc1, 0xc412, 0x21, 0 - .dw 0x2fc3, 0xc412, 0x2fcf, 0xc412, 0x21, 0 - .dw 0x2fd1, 0xc412, 0x2fd1, 0xc412, 0x21, 0 - .dw 0x2fd3, 0xc412, 0xbfff, 0xc412, 0x21, 0 - .dw 0xd000, 0xc412, 0xffff, 0xc413, 0x21, 0 - .dw 0x0001, 0xc414, 0x0001, 0xc414, 0x21, 0 - .dw 0x0003, 0xc414, 0x000f, 0xc414, 0x21, 0 - .dw 0x0011, 0xc414, 0x0011, 0xc414, 0x21, 0 - .dw 0x0013, 0xc414, 0x003f, 0xc414, 0x21, 0 - .dw 0x0041, 0xc414, 0x0041, 0xc414, 0x21, 0 - .dw 0x0043, 0xc414, 0x004f, 0xc414, 0x21, 0 - .dw 0x0051, 0xc414, 0x0051, 0xc414, 0x21, 0 - .dw 0x0053, 0xc414, 0x007f, 0xc414, 0x21, 0 - .dw 0x0081, 0xc414, 0x0081, 0xc414, 0x21, 0 - .dw 0x0083, 0xc414, 0x008f, 0xc414, 0x21, 0 - .dw 0x0091, 0xc414, 0x0091, 0xc414, 0x21, 0 - .dw 0x0093, 0xc414, 0x00bf, 0xc414, 0x21, 0 - .dw 0x00c1, 0xc414, 0x00c1, 0xc414, 0x21, 0 - .dw 0x00c3, 0xc414, 0x00cf, 0xc414, 0x21, 0 - .dw 0x00d1, 0xc414, 0x00d1, 0xc414, 0x21, 0 - .dw 0x00d3, 0xc414, 0x00ff, 0xc414, 0x21, 0 - .dw 0x0101, 0xc414, 0x0101, 0xc414, 0x21, 0 - .dw 0x0103, 0xc414, 0x010f, 0xc414, 0x21, 0 - .dw 0x0111, 0xc414, 0x0111, 0xc414, 0x21, 0 - .dw 0x0113, 0xc414, 0x013f, 0xc414, 0x21, 0 - .dw 0x0141, 0xc414, 0x0141, 0xc414, 0x21, 0 - .dw 0x0143, 0xc414, 0x014f, 0xc414, 0x21, 0 - .dw 0x0151, 0xc414, 0x0151, 0xc414, 0x21, 0 - .dw 0x0153, 0xc414, 0x017f, 0xc414, 0x21, 0 - .dw 0x0181, 0xc414, 0x0181, 0xc414, 0x21, 0 - .dw 0x0183, 0xc414, 0x018f, 0xc414, 0x21, 0 - .dw 0x0191, 0xc414, 0x0191, 0xc414, 0x21, 0 - .dw 0x0193, 0xc414, 0x01bf, 0xc414, 0x21, 0 - .dw 0x01c1, 0xc414, 0x01c1, 0xc414, 0x21, 0 - .dw 0x01c3, 0xc414, 0x01cf, 0xc414, 0x21, 0 - .dw 0x01d1, 0xc414, 0x01d1, 0xc414, 0x21, 0 - .dw 0x01d3, 0xc414, 0x01ff, 0xc414, 0x21, 0 - .dw 0x0201, 0xc414, 0x0201, 0xc414, 0x21, 0 - .dw 0x0203, 0xc414, 0x020f, 0xc414, 0x21, 0 - .dw 0x0211, 0xc414, 0x0211, 0xc414, 0x21, 0 - .dw 0x0213, 0xc414, 0x023f, 0xc414, 0x21, 0 - .dw 0x0241, 0xc414, 0x0241, 0xc414, 0x21, 0 - .dw 0x0243, 0xc414, 0x024f, 0xc414, 0x21, 0 - .dw 0x0251, 0xc414, 0x0251, 0xc414, 0x21, 0 - .dw 0x0253, 0xc414, 0x027f, 0xc414, 0x21, 0 - .dw 0x0281, 0xc414, 0x0281, 0xc414, 0x21, 0 - .dw 0x0283, 0xc414, 0x028f, 0xc414, 0x21, 0 - .dw 0x0291, 0xc414, 0x0291, 0xc414, 0x21, 0 - .dw 0x0293, 0xc414, 0x02bf, 0xc414, 0x21, 0 - .dw 0x02c1, 0xc414, 0x02c1, 0xc414, 0x21, 0 - .dw 0x02c3, 0xc414, 0x02cf, 0xc414, 0x21, 0 - .dw 0x02d1, 0xc414, 0x02d1, 0xc414, 0x21, 0 - .dw 0x02d3, 0xc414, 0x02ff, 0xc414, 0x21, 0 - .dw 0x0301, 0xc414, 0x0301, 0xc414, 0x21, 0 - .dw 0x0303, 0xc414, 0x030f, 0xc414, 0x21, 0 - .dw 0x0311, 0xc414, 0x0311, 0xc414, 0x21, 0 - .dw 0x0313, 0xc414, 0x033f, 0xc414, 0x21, 0 - .dw 0x0341, 0xc414, 0x0341, 0xc414, 0x21, 0 - .dw 0x0343, 0xc414, 0x034f, 0xc414, 0x21, 0 - .dw 0x0351, 0xc414, 0x0351, 0xc414, 0x21, 0 - .dw 0x0353, 0xc414, 0x037f, 0xc414, 0x21, 0 - .dw 0x0381, 0xc414, 0x0381, 0xc414, 0x21, 0 - .dw 0x0383, 0xc414, 0x038f, 0xc414, 0x21, 0 - .dw 0x0391, 0xc414, 0x0391, 0xc414, 0x21, 0 - .dw 0x0393, 0xc414, 0x03bf, 0xc414, 0x21, 0 - .dw 0x03c1, 0xc414, 0x03c1, 0xc414, 0x21, 0 - .dw 0x03c3, 0xc414, 0x03cf, 0xc414, 0x21, 0 - .dw 0x03d1, 0xc414, 0x03d1, 0xc414, 0x21, 0 - .dw 0x03d3, 0xc414, 0x03ff, 0xc414, 0x21, 0 - .dw 0x0401, 0xc414, 0x0401, 0xc414, 0x21, 0 - .dw 0x0403, 0xc414, 0x040f, 0xc414, 0x21, 0 - .dw 0x0411, 0xc414, 0x0411, 0xc414, 0x21, 0 - .dw 0x0413, 0xc414, 0x043f, 0xc414, 0x21, 0 - .dw 0x0441, 0xc414, 0x0441, 0xc414, 0x21, 0 - .dw 0x0443, 0xc414, 0x044f, 0xc414, 0x21, 0 - .dw 0x0451, 0xc414, 0x0451, 0xc414, 0x21, 0 - .dw 0x0453, 0xc414, 0x047f, 0xc414, 0x21, 0 - .dw 0x0481, 0xc414, 0x0481, 0xc414, 0x21, 0 - .dw 0x0483, 0xc414, 0x048f, 0xc414, 0x21, 0 - .dw 0x0491, 0xc414, 0x0491, 0xc414, 0x21, 0 - .dw 0x0493, 0xc414, 0x04bf, 0xc414, 0x21, 0 - .dw 0x04c1, 0xc414, 0x04c1, 0xc414, 0x21, 0 - .dw 0x04c3, 0xc414, 0x04cf, 0xc414, 0x21, 0 - .dw 0x04d1, 0xc414, 0x04d1, 0xc414, 0x21, 0 - .dw 0x04d3, 0xc414, 0x04ff, 0xc414, 0x21, 0 - .dw 0x0501, 0xc414, 0x0501, 0xc414, 0x21, 0 - .dw 0x0503, 0xc414, 0x050f, 0xc414, 0x21, 0 - .dw 0x0511, 0xc414, 0x0511, 0xc414, 0x21, 0 - .dw 0x0513, 0xc414, 0x053f, 0xc414, 0x21, 0 - .dw 0x0541, 0xc414, 0x0541, 0xc414, 0x21, 0 - .dw 0x0543, 0xc414, 0x054f, 0xc414, 0x21, 0 - .dw 0x0551, 0xc414, 0x0551, 0xc414, 0x21, 0 - .dw 0x0553, 0xc414, 0x057f, 0xc414, 0x21, 0 - .dw 0x0581, 0xc414, 0x0581, 0xc414, 0x21, 0 - .dw 0x0583, 0xc414, 0x058f, 0xc414, 0x21, 0 - .dw 0x0591, 0xc414, 0x0591, 0xc414, 0x21, 0 - .dw 0x0593, 0xc414, 0x05bf, 0xc414, 0x21, 0 - .dw 0x05c1, 0xc414, 0x05c1, 0xc414, 0x21, 0 - .dw 0x05c3, 0xc414, 0x05cf, 0xc414, 0x21, 0 - .dw 0x05d1, 0xc414, 0x05d1, 0xc414, 0x21, 0 - .dw 0x05d3, 0xc414, 0x05ff, 0xc414, 0x21, 0 - .dw 0x0601, 0xc414, 0x0601, 0xc414, 0x21, 0 - .dw 0x0603, 0xc414, 0x060f, 0xc414, 0x21, 0 - .dw 0x0611, 0xc414, 0x0611, 0xc414, 0x21, 0 - .dw 0x0613, 0xc414, 0x063f, 0xc414, 0x21, 0 - .dw 0x0641, 0xc414, 0x0641, 0xc414, 0x21, 0 - .dw 0x0643, 0xc414, 0x064f, 0xc414, 0x21, 0 - .dw 0x0651, 0xc414, 0x0651, 0xc414, 0x21, 0 - .dw 0x0653, 0xc414, 0x067f, 0xc414, 0x21, 0 - .dw 0x0681, 0xc414, 0x0681, 0xc414, 0x21, 0 - .dw 0x0683, 0xc414, 0x068f, 0xc414, 0x21, 0 - .dw 0x0691, 0xc414, 0x0691, 0xc414, 0x21, 0 - .dw 0x0693, 0xc414, 0x06bf, 0xc414, 0x21, 0 - .dw 0x06c1, 0xc414, 0x06c1, 0xc414, 0x21, 0 - .dw 0x06c3, 0xc414, 0x06cf, 0xc414, 0x21, 0 - .dw 0x06d1, 0xc414, 0x06d1, 0xc414, 0x21, 0 - .dw 0x06d3, 0xc414, 0x06ff, 0xc414, 0x21, 0 - .dw 0x0701, 0xc414, 0x0701, 0xc414, 0x21, 0 - .dw 0x0703, 0xc414, 0x070f, 0xc414, 0x21, 0 - .dw 0x0711, 0xc414, 0x0711, 0xc414, 0x21, 0 - .dw 0x0713, 0xc414, 0x073f, 0xc414, 0x21, 0 - .dw 0x0741, 0xc414, 0x0741, 0xc414, 0x21, 0 - .dw 0x0743, 0xc414, 0x074f, 0xc414, 0x21, 0 - .dw 0x0751, 0xc414, 0x0751, 0xc414, 0x21, 0 - .dw 0x0753, 0xc414, 0x077f, 0xc414, 0x21, 0 - .dw 0x0781, 0xc414, 0x0781, 0xc414, 0x21, 0 - .dw 0x0783, 0xc414, 0x078f, 0xc414, 0x21, 0 - .dw 0x0791, 0xc414, 0x0791, 0xc414, 0x21, 0 - .dw 0x0793, 0xc414, 0x07bf, 0xc414, 0x21, 0 - .dw 0x07c1, 0xc414, 0x07c1, 0xc414, 0x21, 0 - .dw 0x07c3, 0xc414, 0x07cf, 0xc414, 0x21, 0 - .dw 0x07d1, 0xc414, 0x07d1, 0xc414, 0x21, 0 - .dw 0x07d3, 0xc414, 0x07ff, 0xc414, 0x21, 0 - .dw 0x0801, 0xc414, 0x0801, 0xc414, 0x21, 0 - .dw 0x0803, 0xc414, 0x080f, 0xc414, 0x21, 0 - .dw 0x0811, 0xc414, 0x0811, 0xc414, 0x21, 0 - .dw 0x0813, 0xc414, 0x083f, 0xc414, 0x21, 0 - .dw 0x0841, 0xc414, 0x0841, 0xc414, 0x21, 0 - .dw 0x0843, 0xc414, 0x084f, 0xc414, 0x21, 0 - .dw 0x0851, 0xc414, 0x0851, 0xc414, 0x21, 0 - .dw 0x0853, 0xc414, 0x087f, 0xc414, 0x21, 0 - .dw 0x0881, 0xc414, 0x0881, 0xc414, 0x21, 0 - .dw 0x0883, 0xc414, 0x088f, 0xc414, 0x21, 0 - .dw 0x0891, 0xc414, 0x0891, 0xc414, 0x21, 0 - .dw 0x0893, 0xc414, 0x08bf, 0xc414, 0x21, 0 - .dw 0x08c1, 0xc414, 0x08c1, 0xc414, 0x21, 0 - .dw 0x08c3, 0xc414, 0x08cf, 0xc414, 0x21, 0 - .dw 0x08d1, 0xc414, 0x08d1, 0xc414, 0x21, 0 - .dw 0x08d3, 0xc414, 0x08ff, 0xc414, 0x21, 0 - .dw 0x0901, 0xc414, 0x0901, 0xc414, 0x21, 0 - .dw 0x0903, 0xc414, 0x090f, 0xc414, 0x21, 0 - .dw 0x0911, 0xc414, 0x0911, 0xc414, 0x21, 0 - .dw 0x0913, 0xc414, 0x093f, 0xc414, 0x21, 0 - .dw 0x0941, 0xc414, 0x0941, 0xc414, 0x21, 0 - .dw 0x0943, 0xc414, 0x094f, 0xc414, 0x21, 0 - .dw 0x0951, 0xc414, 0x0951, 0xc414, 0x21, 0 - .dw 0x0953, 0xc414, 0x097f, 0xc414, 0x21, 0 - .dw 0x0981, 0xc414, 0x0981, 0xc414, 0x21, 0 - .dw 0x0983, 0xc414, 0x098f, 0xc414, 0x21, 0 - .dw 0x0991, 0xc414, 0x0991, 0xc414, 0x21, 0 - .dw 0x0993, 0xc414, 0x09bf, 0xc414, 0x21, 0 - .dw 0x09c1, 0xc414, 0x09c1, 0xc414, 0x21, 0 - .dw 0x09c3, 0xc414, 0x09cf, 0xc414, 0x21, 0 - .dw 0x09d1, 0xc414, 0x09d1, 0xc414, 0x21, 0 - .dw 0x09d3, 0xc414, 0x09ff, 0xc414, 0x21, 0 - .dw 0x0a01, 0xc414, 0x0a01, 0xc414, 0x21, 0 - .dw 0x0a03, 0xc414, 0x0a0f, 0xc414, 0x21, 0 - .dw 0x0a11, 0xc414, 0x0a11, 0xc414, 0x21, 0 - .dw 0x0a13, 0xc414, 0x0a3f, 0xc414, 0x21, 0 - .dw 0x0a41, 0xc414, 0x0a41, 0xc414, 0x21, 0 - .dw 0x0a43, 0xc414, 0x0a4f, 0xc414, 0x21, 0 - .dw 0x0a51, 0xc414, 0x0a51, 0xc414, 0x21, 0 - .dw 0x0a53, 0xc414, 0x0a7f, 0xc414, 0x21, 0 - .dw 0x0a81, 0xc414, 0x0a81, 0xc414, 0x21, 0 - .dw 0x0a83, 0xc414, 0x0a8f, 0xc414, 0x21, 0 - .dw 0x0a91, 0xc414, 0x0a91, 0xc414, 0x21, 0 - .dw 0x0a93, 0xc414, 0x0abf, 0xc414, 0x21, 0 - .dw 0x0ac1, 0xc414, 0x0ac1, 0xc414, 0x21, 0 - .dw 0x0ac3, 0xc414, 0x0acf, 0xc414, 0x21, 0 - .dw 0x0ad1, 0xc414, 0x0ad1, 0xc414, 0x21, 0 - .dw 0x0ad3, 0xc414, 0x0aff, 0xc414, 0x21, 0 - .dw 0x0b01, 0xc414, 0x0b01, 0xc414, 0x21, 0 - .dw 0x0b03, 0xc414, 0x0b0f, 0xc414, 0x21, 0 - .dw 0x0b11, 0xc414, 0x0b11, 0xc414, 0x21, 0 - .dw 0x0b13, 0xc414, 0x0b3f, 0xc414, 0x21, 0 - .dw 0x0b41, 0xc414, 0x0b41, 0xc414, 0x21, 0 - .dw 0x0b43, 0xc414, 0x0b4f, 0xc414, 0x21, 0 - .dw 0x0b51, 0xc414, 0x0b51, 0xc414, 0x21, 0 - .dw 0x0b53, 0xc414, 0x0b7f, 0xc414, 0x21, 0 - .dw 0x0b81, 0xc414, 0x0b81, 0xc414, 0x21, 0 - .dw 0x0b83, 0xc414, 0x0b8f, 0xc414, 0x21, 0 - .dw 0x0b91, 0xc414, 0x0b91, 0xc414, 0x21, 0 - .dw 0x0b93, 0xc414, 0x0bbf, 0xc414, 0x21, 0 - .dw 0x0bc1, 0xc414, 0x0bc1, 0xc414, 0x21, 0 - .dw 0x0bc3, 0xc414, 0x0bcf, 0xc414, 0x21, 0 - .dw 0x0bd1, 0xc414, 0x0bd1, 0xc414, 0x21, 0 - .dw 0x0bd3, 0xc414, 0x0bff, 0xc414, 0x21, 0 - .dw 0x0c01, 0xc414, 0x0c01, 0xc414, 0x21, 0 - .dw 0x0c03, 0xc414, 0x0c0f, 0xc414, 0x21, 0 - .dw 0x0c11, 0xc414, 0x0c11, 0xc414, 0x21, 0 - .dw 0x0c13, 0xc414, 0x0c3f, 0xc414, 0x21, 0 - .dw 0x0c41, 0xc414, 0x0c41, 0xc414, 0x21, 0 - .dw 0x0c43, 0xc414, 0x0c4f, 0xc414, 0x21, 0 - .dw 0x0c51, 0xc414, 0x0c51, 0xc414, 0x21, 0 - .dw 0x0c53, 0xc414, 0x0c7f, 0xc414, 0x21, 0 - .dw 0x0c81, 0xc414, 0x0c81, 0xc414, 0x21, 0 - .dw 0x0c83, 0xc414, 0x0c8f, 0xc414, 0x21, 0 - .dw 0x0c91, 0xc414, 0x0c91, 0xc414, 0x21, 0 - .dw 0x0c93, 0xc414, 0x0cbf, 0xc414, 0x21, 0 - .dw 0x0cc1, 0xc414, 0x0cc1, 0xc414, 0x21, 0 - .dw 0x0cc3, 0xc414, 0x0ccf, 0xc414, 0x21, 0 - .dw 0x0cd1, 0xc414, 0x0cd1, 0xc414, 0x21, 0 - .dw 0x0cd3, 0xc414, 0x0cff, 0xc414, 0x21, 0 - .dw 0x0d01, 0xc414, 0x0d01, 0xc414, 0x21, 0 - .dw 0x0d03, 0xc414, 0x0d0f, 0xc414, 0x21, 0 - .dw 0x0d11, 0xc414, 0x0d11, 0xc414, 0x21, 0 - .dw 0x0d13, 0xc414, 0x0d3f, 0xc414, 0x21, 0 - .dw 0x0d41, 0xc414, 0x0d41, 0xc414, 0x21, 0 - .dw 0x0d43, 0xc414, 0x0d4f, 0xc414, 0x21, 0 - .dw 0x0d51, 0xc414, 0x0d51, 0xc414, 0x21, 0 - .dw 0x0d53, 0xc414, 0x0d7f, 0xc414, 0x21, 0 - .dw 0x0d81, 0xc414, 0x0d81, 0xc414, 0x21, 0 - .dw 0x0d83, 0xc414, 0x0d8f, 0xc414, 0x21, 0 - .dw 0x0d91, 0xc414, 0x0d91, 0xc414, 0x21, 0 - .dw 0x0d93, 0xc414, 0x0dbf, 0xc414, 0x21, 0 - .dw 0x0dc1, 0xc414, 0x0dc1, 0xc414, 0x21, 0 - .dw 0x0dc3, 0xc414, 0x0dcf, 0xc414, 0x21, 0 - .dw 0x0dd1, 0xc414, 0x0dd1, 0xc414, 0x21, 0 - .dw 0x0dd3, 0xc414, 0x0dff, 0xc414, 0x21, 0 - .dw 0x0e01, 0xc414, 0x0e01, 0xc414, 0x21, 0 - .dw 0x0e03, 0xc414, 0x0e0f, 0xc414, 0x21, 0 - .dw 0x0e11, 0xc414, 0x0e11, 0xc414, 0x21, 0 - .dw 0x0e13, 0xc414, 0x0e3f, 0xc414, 0x21, 0 - .dw 0x0e41, 0xc414, 0x0e41, 0xc414, 0x21, 0 - .dw 0x0e43, 0xc414, 0x0e4f, 0xc414, 0x21, 0 - .dw 0x0e51, 0xc414, 0x0e51, 0xc414, 0x21, 0 - .dw 0x0e53, 0xc414, 0x0e7f, 0xc414, 0x21, 0 - .dw 0x0e81, 0xc414, 0x0e81, 0xc414, 0x21, 0 - .dw 0x0e83, 0xc414, 0x0e8f, 0xc414, 0x21, 0 - .dw 0x0e91, 0xc414, 0x0e91, 0xc414, 0x21, 0 - .dw 0x0e93, 0xc414, 0x0ebf, 0xc414, 0x21, 0 - .dw 0x0ec1, 0xc414, 0x0ec1, 0xc414, 0x21, 0 - .dw 0x0ec3, 0xc414, 0x0ecf, 0xc414, 0x21, 0 - .dw 0x0ed1, 0xc414, 0x0ed1, 0xc414, 0x21, 0 - .dw 0x0ed3, 0xc414, 0x0eff, 0xc414, 0x21, 0 - .dw 0x0f01, 0xc414, 0x0f01, 0xc414, 0x21, 0 - .dw 0x0f03, 0xc414, 0x0f0f, 0xc414, 0x21, 0 - .dw 0x0f11, 0xc414, 0x0f11, 0xc414, 0x21, 0 - .dw 0x0f13, 0xc414, 0x0f3f, 0xc414, 0x21, 0 - .dw 0x0f41, 0xc414, 0x0f41, 0xc414, 0x21, 0 - .dw 0x0f43, 0xc414, 0x0f4f, 0xc414, 0x21, 0 - .dw 0x0f51, 0xc414, 0x0f51, 0xc414, 0x21, 0 - .dw 0x0f53, 0xc414, 0x0f7f, 0xc414, 0x21, 0 - .dw 0x0f81, 0xc414, 0x0f81, 0xc414, 0x21, 0 - .dw 0x0f83, 0xc414, 0x0f8f, 0xc414, 0x21, 0 - .dw 0x0f91, 0xc414, 0x0f91, 0xc414, 0x21, 0 - .dw 0x0f93, 0xc414, 0x0fbf, 0xc414, 0x21, 0 - .dw 0x0fc1, 0xc414, 0x0fc1, 0xc414, 0x21, 0 - .dw 0x0fc3, 0xc414, 0x0fcf, 0xc414, 0x21, 0 - .dw 0x0fd1, 0xc414, 0x0fd1, 0xc414, 0x21, 0 - .dw 0x0fd3, 0xc414, 0x1fff, 0xc414, 0x21, 0 - .dw 0x2001, 0xc414, 0x2001, 0xc414, 0x21, 0 - .dw 0x2003, 0xc414, 0x200f, 0xc414, 0x21, 0 - .dw 0x2011, 0xc414, 0x2011, 0xc414, 0x21, 0 - .dw 0x2013, 0xc414, 0x203f, 0xc414, 0x21, 0 - .dw 0x2041, 0xc414, 0x2041, 0xc414, 0x21, 0 - .dw 0x2043, 0xc414, 0x204f, 0xc414, 0x21, 0 - .dw 0x2051, 0xc414, 0x2051, 0xc414, 0x21, 0 - .dw 0x2053, 0xc414, 0x207f, 0xc414, 0x21, 0 - .dw 0x2081, 0xc414, 0x2081, 0xc414, 0x21, 0 - .dw 0x2083, 0xc414, 0x208f, 0xc414, 0x21, 0 - .dw 0x2091, 0xc414, 0x2091, 0xc414, 0x21, 0 - .dw 0x2093, 0xc414, 0x20bf, 0xc414, 0x21, 0 - .dw 0x20c1, 0xc414, 0x20c1, 0xc414, 0x21, 0 - .dw 0x20c3, 0xc414, 0x20cf, 0xc414, 0x21, 0 - .dw 0x20d1, 0xc414, 0x20d1, 0xc414, 0x21, 0 - .dw 0x20d3, 0xc414, 0x20ff, 0xc414, 0x21, 0 - .dw 0x2101, 0xc414, 0x2101, 0xc414, 0x21, 0 - .dw 0x2103, 0xc414, 0x210f, 0xc414, 0x21, 0 - .dw 0x2111, 0xc414, 0x2111, 0xc414, 0x21, 0 - .dw 0x2113, 0xc414, 0x213f, 0xc414, 0x21, 0 - .dw 0x2141, 0xc414, 0x2141, 0xc414, 0x21, 0 - .dw 0x2143, 0xc414, 0x214f, 0xc414, 0x21, 0 - .dw 0x2151, 0xc414, 0x2151, 0xc414, 0x21, 0 - .dw 0x2153, 0xc414, 0x217f, 0xc414, 0x21, 0 - .dw 0x2181, 0xc414, 0x2181, 0xc414, 0x21, 0 - .dw 0x2183, 0xc414, 0x218f, 0xc414, 0x21, 0 - .dw 0x2191, 0xc414, 0x2191, 0xc414, 0x21, 0 - .dw 0x2193, 0xc414, 0x21bf, 0xc414, 0x21, 0 - .dw 0x21c1, 0xc414, 0x21c1, 0xc414, 0x21, 0 - .dw 0x21c3, 0xc414, 0x21cf, 0xc414, 0x21, 0 - .dw 0x21d1, 0xc414, 0x21d1, 0xc414, 0x21, 0 - .dw 0x21d3, 0xc414, 0x21ff, 0xc414, 0x21, 0 - .dw 0x2201, 0xc414, 0x2201, 0xc414, 0x21, 0 - .dw 0x2203, 0xc414, 0x220f, 0xc414, 0x21, 0 - .dw 0x2211, 0xc414, 0x2211, 0xc414, 0x21, 0 - .dw 0x2213, 0xc414, 0x223f, 0xc414, 0x21, 0 - .dw 0x2241, 0xc414, 0x2241, 0xc414, 0x21, 0 - .dw 0x2243, 0xc414, 0x224f, 0xc414, 0x21, 0 - .dw 0x2251, 0xc414, 0x2251, 0xc414, 0x21, 0 - .dw 0x2253, 0xc414, 0x227f, 0xc414, 0x21, 0 - .dw 0x2281, 0xc414, 0x2281, 0xc414, 0x21, 0 - .dw 0x2283, 0xc414, 0x228f, 0xc414, 0x21, 0 - .dw 0x2291, 0xc414, 0x2291, 0xc414, 0x21, 0 - .dw 0x2293, 0xc414, 0x22bf, 0xc414, 0x21, 0 - .dw 0x22c1, 0xc414, 0x22c1, 0xc414, 0x21, 0 - .dw 0x22c3, 0xc414, 0x22cf, 0xc414, 0x21, 0 - .dw 0x22d1, 0xc414, 0x22d1, 0xc414, 0x21, 0 - .dw 0x22d3, 0xc414, 0x22ff, 0xc414, 0x21, 0 - .dw 0x2301, 0xc414, 0x2301, 0xc414, 0x21, 0 - .dw 0x2303, 0xc414, 0x230f, 0xc414, 0x21, 0 - .dw 0x2311, 0xc414, 0x2311, 0xc414, 0x21, 0 - .dw 0x2313, 0xc414, 0x233f, 0xc414, 0x21, 0 - .dw 0x2341, 0xc414, 0x2341, 0xc414, 0x21, 0 - .dw 0x2343, 0xc414, 0x234f, 0xc414, 0x21, 0 - .dw 0x2351, 0xc414, 0x2351, 0xc414, 0x21, 0 - .dw 0x2353, 0xc414, 0x237f, 0xc414, 0x21, 0 - .dw 0x2381, 0xc414, 0x2381, 0xc414, 0x21, 0 - .dw 0x2383, 0xc414, 0x238f, 0xc414, 0x21, 0 - .dw 0x2391, 0xc414, 0x2391, 0xc414, 0x21, 0 - .dw 0x2393, 0xc414, 0x23bf, 0xc414, 0x21, 0 - .dw 0x23c1, 0xc414, 0x23c1, 0xc414, 0x21, 0 - .dw 0x23c3, 0xc414, 0x23cf, 0xc414, 0x21, 0 - .dw 0x23d1, 0xc414, 0x23d1, 0xc414, 0x21, 0 - .dw 0x23d3, 0xc414, 0x23ff, 0xc414, 0x21, 0 - .dw 0x2401, 0xc414, 0x2401, 0xc414, 0x21, 0 - .dw 0x2403, 0xc414, 0x240f, 0xc414, 0x21, 0 - .dw 0x2411, 0xc414, 0x2411, 0xc414, 0x21, 0 - .dw 0x2413, 0xc414, 0x243f, 0xc414, 0x21, 0 - .dw 0x2441, 0xc414, 0x2441, 0xc414, 0x21, 0 - .dw 0x2443, 0xc414, 0x244f, 0xc414, 0x21, 0 - .dw 0x2451, 0xc414, 0x2451, 0xc414, 0x21, 0 - .dw 0x2453, 0xc414, 0x247f, 0xc414, 0x21, 0 - .dw 0x2481, 0xc414, 0x2481, 0xc414, 0x21, 0 - .dw 0x2483, 0xc414, 0x248f, 0xc414, 0x21, 0 - .dw 0x2491, 0xc414, 0x2491, 0xc414, 0x21, 0 - .dw 0x2493, 0xc414, 0x24bf, 0xc414, 0x21, 0 - .dw 0x24c1, 0xc414, 0x24c1, 0xc414, 0x21, 0 - .dw 0x24c3, 0xc414, 0x24cf, 0xc414, 0x21, 0 - .dw 0x24d1, 0xc414, 0x24d1, 0xc414, 0x21, 0 - .dw 0x24d3, 0xc414, 0x24ff, 0xc414, 0x21, 0 - .dw 0x2501, 0xc414, 0x2501, 0xc414, 0x21, 0 - .dw 0x2503, 0xc414, 0x250f, 0xc414, 0x21, 0 - .dw 0x2511, 0xc414, 0x2511, 0xc414, 0x21, 0 - .dw 0x2513, 0xc414, 0x253f, 0xc414, 0x21, 0 - .dw 0x2541, 0xc414, 0x2541, 0xc414, 0x21, 0 - .dw 0x2543, 0xc414, 0x254f, 0xc414, 0x21, 0 - .dw 0x2551, 0xc414, 0x2551, 0xc414, 0x21, 0 - .dw 0x2553, 0xc414, 0x257f, 0xc414, 0x21, 0 - .dw 0x2581, 0xc414, 0x2581, 0xc414, 0x21, 0 - .dw 0x2583, 0xc414, 0x258f, 0xc414, 0x21, 0 - .dw 0x2591, 0xc414, 0x2591, 0xc414, 0x21, 0 - .dw 0x2593, 0xc414, 0x25bf, 0xc414, 0x21, 0 - .dw 0x25c1, 0xc414, 0x25c1, 0xc414, 0x21, 0 - .dw 0x25c3, 0xc414, 0x25cf, 0xc414, 0x21, 0 - .dw 0x25d1, 0xc414, 0x25d1, 0xc414, 0x21, 0 - .dw 0x25d3, 0xc414, 0x25ff, 0xc414, 0x21, 0 - .dw 0x2601, 0xc414, 0x2601, 0xc414, 0x21, 0 - .dw 0x2603, 0xc414, 0x260f, 0xc414, 0x21, 0 - .dw 0x2611, 0xc414, 0x2611, 0xc414, 0x21, 0 - .dw 0x2613, 0xc414, 0x263f, 0xc414, 0x21, 0 - .dw 0x2641, 0xc414, 0x2641, 0xc414, 0x21, 0 - .dw 0x2643, 0xc414, 0x264f, 0xc414, 0x21, 0 - .dw 0x2651, 0xc414, 0x2651, 0xc414, 0x21, 0 - .dw 0x2653, 0xc414, 0x267f, 0xc414, 0x21, 0 - .dw 0x2681, 0xc414, 0x2681, 0xc414, 0x21, 0 - .dw 0x2683, 0xc414, 0x268f, 0xc414, 0x21, 0 - .dw 0x2691, 0xc414, 0x2691, 0xc414, 0x21, 0 - .dw 0x2693, 0xc414, 0x26bf, 0xc414, 0x21, 0 - .dw 0x26c1, 0xc414, 0x26c1, 0xc414, 0x21, 0 - .dw 0x26c3, 0xc414, 0x26cf, 0xc414, 0x21, 0 - .dw 0x26d1, 0xc414, 0x26d1, 0xc414, 0x21, 0 - .dw 0x26d3, 0xc414, 0x26ff, 0xc414, 0x21, 0 - .dw 0x2701, 0xc414, 0x2701, 0xc414, 0x21, 0 - .dw 0x2703, 0xc414, 0x270f, 0xc414, 0x21, 0 - .dw 0x2711, 0xc414, 0x2711, 0xc414, 0x21, 0 - .dw 0x2713, 0xc414, 0x273f, 0xc414, 0x21, 0 - .dw 0x2741, 0xc414, 0x2741, 0xc414, 0x21, 0 - .dw 0x2743, 0xc414, 0x274f, 0xc414, 0x21, 0 - .dw 0x2751, 0xc414, 0x2751, 0xc414, 0x21, 0 - .dw 0x2753, 0xc414, 0x277f, 0xc414, 0x21, 0 - .dw 0x2781, 0xc414, 0x2781, 0xc414, 0x21, 0 - .dw 0x2783, 0xc414, 0x278f, 0xc414, 0x21, 0 - .dw 0x2791, 0xc414, 0x2791, 0xc414, 0x21, 0 - .dw 0x2793, 0xc414, 0x27bf, 0xc414, 0x21, 0 - .dw 0x27c1, 0xc414, 0x27c1, 0xc414, 0x21, 0 - .dw 0x27c3, 0xc414, 0x27cf, 0xc414, 0x21, 0 - .dw 0x27d1, 0xc414, 0x27d1, 0xc414, 0x21, 0 - .dw 0x27d3, 0xc414, 0x27ff, 0xc414, 0x21, 0 - .dw 0x2801, 0xc414, 0x2801, 0xc414, 0x21, 0 - .dw 0x2803, 0xc414, 0x280f, 0xc414, 0x21, 0 - .dw 0x2811, 0xc414, 0x2811, 0xc414, 0x21, 0 - .dw 0x2813, 0xc414, 0x283f, 0xc414, 0x21, 0 - .dw 0x2841, 0xc414, 0x2841, 0xc414, 0x21, 0 - .dw 0x2843, 0xc414, 0x284f, 0xc414, 0x21, 0 - .dw 0x2851, 0xc414, 0x2851, 0xc414, 0x21, 0 - .dw 0x2853, 0xc414, 0x287f, 0xc414, 0x21, 0 - .dw 0x2881, 0xc414, 0x2881, 0xc414, 0x21, 0 - .dw 0x2883, 0xc414, 0x288f, 0xc414, 0x21, 0 - .dw 0x2891, 0xc414, 0x2891, 0xc414, 0x21, 0 - .dw 0x2893, 0xc414, 0x28bf, 0xc414, 0x21, 0 - .dw 0x28c1, 0xc414, 0x28c1, 0xc414, 0x21, 0 - .dw 0x28c3, 0xc414, 0x28cf, 0xc414, 0x21, 0 - .dw 0x28d1, 0xc414, 0x28d1, 0xc414, 0x21, 0 - .dw 0x28d3, 0xc414, 0x28ff, 0xc414, 0x21, 0 - .dw 0x2901, 0xc414, 0x2901, 0xc414, 0x21, 0 - .dw 0x2903, 0xc414, 0x290f, 0xc414, 0x21, 0 - .dw 0x2911, 0xc414, 0x2911, 0xc414, 0x21, 0 - .dw 0x2913, 0xc414, 0x293f, 0xc414, 0x21, 0 - .dw 0x2941, 0xc414, 0x2941, 0xc414, 0x21, 0 - .dw 0x2943, 0xc414, 0x294f, 0xc414, 0x21, 0 - .dw 0x2951, 0xc414, 0x2951, 0xc414, 0x21, 0 - .dw 0x2953, 0xc414, 0x297f, 0xc414, 0x21, 0 - .dw 0x2981, 0xc414, 0x2981, 0xc414, 0x21, 0 - .dw 0x2983, 0xc414, 0x298f, 0xc414, 0x21, 0 - .dw 0x2991, 0xc414, 0x2991, 0xc414, 0x21, 0 - .dw 0x2993, 0xc414, 0x29bf, 0xc414, 0x21, 0 - .dw 0x29c1, 0xc414, 0x29c1, 0xc414, 0x21, 0 - .dw 0x29c3, 0xc414, 0x29cf, 0xc414, 0x21, 0 - .dw 0x29d1, 0xc414, 0x29d1, 0xc414, 0x21, 0 - .dw 0x29d3, 0xc414, 0x29ff, 0xc414, 0x21, 0 - .dw 0x2a01, 0xc414, 0x2a01, 0xc414, 0x21, 0 - .dw 0x2a03, 0xc414, 0x2a0f, 0xc414, 0x21, 0 - .dw 0x2a11, 0xc414, 0x2a11, 0xc414, 0x21, 0 - .dw 0x2a13, 0xc414, 0x2a3f, 0xc414, 0x21, 0 - .dw 0x2a41, 0xc414, 0x2a41, 0xc414, 0x21, 0 - .dw 0x2a43, 0xc414, 0x2a4f, 0xc414, 0x21, 0 - .dw 0x2a51, 0xc414, 0x2a51, 0xc414, 0x21, 0 - .dw 0x2a53, 0xc414, 0x2a7f, 0xc414, 0x21, 0 - .dw 0x2a81, 0xc414, 0x2a81, 0xc414, 0x21, 0 - .dw 0x2a83, 0xc414, 0x2a8f, 0xc414, 0x21, 0 - .dw 0x2a91, 0xc414, 0x2a91, 0xc414, 0x21, 0 - .dw 0x2a93, 0xc414, 0x2abf, 0xc414, 0x21, 0 - .dw 0x2ac1, 0xc414, 0x2ac1, 0xc414, 0x21, 0 - .dw 0x2ac3, 0xc414, 0x2acf, 0xc414, 0x21, 0 - .dw 0x2ad1, 0xc414, 0x2ad1, 0xc414, 0x21, 0 - .dw 0x2ad3, 0xc414, 0x2aff, 0xc414, 0x21, 0 - .dw 0x2b01, 0xc414, 0x2b01, 0xc414, 0x21, 0 - .dw 0x2b03, 0xc414, 0x2b0f, 0xc414, 0x21, 0 - .dw 0x2b11, 0xc414, 0x2b11, 0xc414, 0x21, 0 - .dw 0x2b13, 0xc414, 0x2b3f, 0xc414, 0x21, 0 - .dw 0x2b41, 0xc414, 0x2b41, 0xc414, 0x21, 0 - .dw 0x2b43, 0xc414, 0x2b4f, 0xc414, 0x21, 0 - .dw 0x2b51, 0xc414, 0x2b51, 0xc414, 0x21, 0 - .dw 0x2b53, 0xc414, 0x2b7f, 0xc414, 0x21, 0 - .dw 0x2b81, 0xc414, 0x2b81, 0xc414, 0x21, 0 - .dw 0x2b83, 0xc414, 0x2b8f, 0xc414, 0x21, 0 - .dw 0x2b91, 0xc414, 0x2b91, 0xc414, 0x21, 0 - .dw 0x2b93, 0xc414, 0x2bbf, 0xc414, 0x21, 0 - .dw 0x2bc1, 0xc414, 0x2bc1, 0xc414, 0x21, 0 - .dw 0x2bc3, 0xc414, 0x2bcf, 0xc414, 0x21, 0 - .dw 0x2bd1, 0xc414, 0x2bd1, 0xc414, 0x21, 0 - .dw 0x2bd3, 0xc414, 0x2bff, 0xc414, 0x21, 0 - .dw 0x2c01, 0xc414, 0x2c01, 0xc414, 0x21, 0 - .dw 0x2c03, 0xc414, 0x2c0f, 0xc414, 0x21, 0 - .dw 0x2c11, 0xc414, 0x2c11, 0xc414, 0x21, 0 - .dw 0x2c13, 0xc414, 0x2c3f, 0xc414, 0x21, 0 - .dw 0x2c41, 0xc414, 0x2c41, 0xc414, 0x21, 0 - .dw 0x2c43, 0xc414, 0x2c4f, 0xc414, 0x21, 0 - .dw 0x2c51, 0xc414, 0x2c51, 0xc414, 0x21, 0 - .dw 0x2c53, 0xc414, 0x2c7f, 0xc414, 0x21, 0 - .dw 0x2c81, 0xc414, 0x2c81, 0xc414, 0x21, 0 - .dw 0x2c83, 0xc414, 0x2c8f, 0xc414, 0x21, 0 - .dw 0x2c91, 0xc414, 0x2c91, 0xc414, 0x21, 0 - .dw 0x2c93, 0xc414, 0x2cbf, 0xc414, 0x21, 0 - .dw 0x2cc1, 0xc414, 0x2cc1, 0xc414, 0x21, 0 - .dw 0x2cc3, 0xc414, 0x2ccf, 0xc414, 0x21, 0 - .dw 0x2cd1, 0xc414, 0x2cd1, 0xc414, 0x21, 0 - .dw 0x2cd3, 0xc414, 0x2cff, 0xc414, 0x21, 0 - .dw 0x2d01, 0xc414, 0x2d01, 0xc414, 0x21, 0 - .dw 0x2d03, 0xc414, 0x2d0f, 0xc414, 0x21, 0 - .dw 0x2d11, 0xc414, 0x2d11, 0xc414, 0x21, 0 - .dw 0x2d13, 0xc414, 0x2d3f, 0xc414, 0x21, 0 - .dw 0x2d41, 0xc414, 0x2d41, 0xc414, 0x21, 0 - .dw 0x2d43, 0xc414, 0x2d4f, 0xc414, 0x21, 0 - .dw 0x2d51, 0xc414, 0x2d51, 0xc414, 0x21, 0 - .dw 0x2d53, 0xc414, 0x2d7f, 0xc414, 0x21, 0 - .dw 0x2d81, 0xc414, 0x2d81, 0xc414, 0x21, 0 - .dw 0x2d83, 0xc414, 0x2d8f, 0xc414, 0x21, 0 - .dw 0x2d91, 0xc414, 0x2d91, 0xc414, 0x21, 0 - .dw 0x2d93, 0xc414, 0x2dbf, 0xc414, 0x21, 0 - .dw 0x2dc1, 0xc414, 0x2dc1, 0xc414, 0x21, 0 - .dw 0x2dc3, 0xc414, 0x2dcf, 0xc414, 0x21, 0 - .dw 0x2dd1, 0xc414, 0x2dd1, 0xc414, 0x21, 0 - .dw 0x2dd3, 0xc414, 0x2dff, 0xc414, 0x21, 0 - .dw 0x2e01, 0xc414, 0x2e01, 0xc414, 0x21, 0 - .dw 0x2e03, 0xc414, 0x2e0f, 0xc414, 0x21, 0 - .dw 0x2e11, 0xc414, 0x2e11, 0xc414, 0x21, 0 - .dw 0x2e13, 0xc414, 0x2e3f, 0xc414, 0x21, 0 - .dw 0x2e41, 0xc414, 0x2e41, 0xc414, 0x21, 0 - .dw 0x2e43, 0xc414, 0x2e4f, 0xc414, 0x21, 0 - .dw 0x2e51, 0xc414, 0x2e51, 0xc414, 0x21, 0 - .dw 0x2e53, 0xc414, 0x2e7f, 0xc414, 0x21, 0 - .dw 0x2e81, 0xc414, 0x2e81, 0xc414, 0x21, 0 - .dw 0x2e83, 0xc414, 0x2e8f, 0xc414, 0x21, 0 - .dw 0x2e91, 0xc414, 0x2e91, 0xc414, 0x21, 0 - .dw 0x2e93, 0xc414, 0x2ebf, 0xc414, 0x21, 0 - .dw 0x2ec1, 0xc414, 0x2ec1, 0xc414, 0x21, 0 - .dw 0x2ec3, 0xc414, 0x2ecf, 0xc414, 0x21, 0 - .dw 0x2ed1, 0xc414, 0x2ed1, 0xc414, 0x21, 0 - .dw 0x2ed3, 0xc414, 0x2eff, 0xc414, 0x21, 0 - .dw 0x2f01, 0xc414, 0x2f01, 0xc414, 0x21, 0 - .dw 0x2f03, 0xc414, 0x2f0f, 0xc414, 0x21, 0 - .dw 0x2f11, 0xc414, 0x2f11, 0xc414, 0x21, 0 - .dw 0x2f13, 0xc414, 0x2f3f, 0xc414, 0x21, 0 - .dw 0x2f41, 0xc414, 0x2f41, 0xc414, 0x21, 0 - .dw 0x2f43, 0xc414, 0x2f4f, 0xc414, 0x21, 0 - .dw 0x2f51, 0xc414, 0x2f51, 0xc414, 0x21, 0 - .dw 0x2f53, 0xc414, 0x2f7f, 0xc414, 0x21, 0 - .dw 0x2f81, 0xc414, 0x2f81, 0xc414, 0x21, 0 - .dw 0x2f83, 0xc414, 0x2f8f, 0xc414, 0x21, 0 - .dw 0x2f91, 0xc414, 0x2f91, 0xc414, 0x21, 0 - .dw 0x2f93, 0xc414, 0x2fbf, 0xc414, 0x21, 0 - .dw 0x2fc1, 0xc414, 0x2fc1, 0xc414, 0x21, 0 - .dw 0x2fc3, 0xc414, 0x2fcf, 0xc414, 0x21, 0 - .dw 0x2fd1, 0xc414, 0x2fd1, 0xc414, 0x21, 0 - .dw 0x2fd3, 0xc414, 0x3fff, 0xc414, 0x21, 0 - .dw 0x4001, 0xc414, 0x4001, 0xc414, 0x21, 0 - .dw 0x4003, 0xc414, 0x400f, 0xc414, 0x21, 0 - .dw 0x4011, 0xc414, 0x4011, 0xc414, 0x21, 0 - .dw 0x4013, 0xc414, 0x403f, 0xc414, 0x21, 0 - .dw 0x4041, 0xc414, 0x4041, 0xc414, 0x21, 0 - .dw 0x4043, 0xc414, 0x404f, 0xc414, 0x21, 0 - .dw 0x4051, 0xc414, 0x4051, 0xc414, 0x21, 0 - .dw 0x4053, 0xc414, 0x407f, 0xc414, 0x21, 0 - .dw 0x4081, 0xc414, 0x4081, 0xc414, 0x21, 0 - .dw 0x4083, 0xc414, 0x408f, 0xc414, 0x21, 0 - .dw 0x4091, 0xc414, 0x4091, 0xc414, 0x21, 0 - .dw 0x4093, 0xc414, 0x40bf, 0xc414, 0x21, 0 - .dw 0x40c1, 0xc414, 0x40c1, 0xc414, 0x21, 0 - .dw 0x40c3, 0xc414, 0x40cf, 0xc414, 0x21, 0 - .dw 0x40d1, 0xc414, 0x40d1, 0xc414, 0x21, 0 - .dw 0x40d3, 0xc414, 0x40ff, 0xc414, 0x21, 0 - .dw 0x4101, 0xc414, 0x4101, 0xc414, 0x21, 0 - .dw 0x4103, 0xc414, 0x410f, 0xc414, 0x21, 0 - .dw 0x4111, 0xc414, 0x4111, 0xc414, 0x21, 0 - .dw 0x4113, 0xc414, 0x413f, 0xc414, 0x21, 0 - .dw 0x4141, 0xc414, 0x4141, 0xc414, 0x21, 0 - .dw 0x4143, 0xc414, 0x414f, 0xc414, 0x21, 0 - .dw 0x4151, 0xc414, 0x4151, 0xc414, 0x21, 0 - .dw 0x4153, 0xc414, 0x417f, 0xc414, 0x21, 0 - .dw 0x4181, 0xc414, 0x4181, 0xc414, 0x21, 0 - .dw 0x4183, 0xc414, 0x418f, 0xc414, 0x21, 0 - .dw 0x4191, 0xc414, 0x4191, 0xc414, 0x21, 0 - .dw 0x4193, 0xc414, 0x41bf, 0xc414, 0x21, 0 - .dw 0x41c1, 0xc414, 0x41c1, 0xc414, 0x21, 0 - .dw 0x41c3, 0xc414, 0x41cf, 0xc414, 0x21, 0 - .dw 0x41d1, 0xc414, 0x41d1, 0xc414, 0x21, 0 - .dw 0x41d3, 0xc414, 0x41ff, 0xc414, 0x21, 0 - .dw 0x4201, 0xc414, 0x4201, 0xc414, 0x21, 0 - .dw 0x4203, 0xc414, 0x420f, 0xc414, 0x21, 0 - .dw 0x4211, 0xc414, 0x4211, 0xc414, 0x21, 0 - .dw 0x4213, 0xc414, 0x423f, 0xc414, 0x21, 0 - .dw 0x4241, 0xc414, 0x4241, 0xc414, 0x21, 0 - .dw 0x4243, 0xc414, 0x424f, 0xc414, 0x21, 0 - .dw 0x4251, 0xc414, 0x4251, 0xc414, 0x21, 0 - .dw 0x4253, 0xc414, 0x427f, 0xc414, 0x21, 0 - .dw 0x4281, 0xc414, 0x4281, 0xc414, 0x21, 0 - .dw 0x4283, 0xc414, 0x428f, 0xc414, 0x21, 0 - .dw 0x4291, 0xc414, 0x4291, 0xc414, 0x21, 0 - .dw 0x4293, 0xc414, 0x42bf, 0xc414, 0x21, 0 - .dw 0x42c1, 0xc414, 0x42c1, 0xc414, 0x21, 0 - .dw 0x42c3, 0xc414, 0x42cf, 0xc414, 0x21, 0 - .dw 0x42d1, 0xc414, 0x42d1, 0xc414, 0x21, 0 - .dw 0x42d3, 0xc414, 0x42ff, 0xc414, 0x21, 0 - .dw 0x4301, 0xc414, 0x4301, 0xc414, 0x21, 0 - .dw 0x4303, 0xc414, 0x430f, 0xc414, 0x21, 0 - .dw 0x4311, 0xc414, 0x4311, 0xc414, 0x21, 0 - .dw 0x4313, 0xc414, 0x433f, 0xc414, 0x21, 0 - .dw 0x4341, 0xc414, 0x4341, 0xc414, 0x21, 0 - .dw 0x4343, 0xc414, 0x434f, 0xc414, 0x21, 0 - .dw 0x4351, 0xc414, 0x4351, 0xc414, 0x21, 0 - .dw 0x4353, 0xc414, 0x437f, 0xc414, 0x21, 0 - .dw 0x4381, 0xc414, 0x4381, 0xc414, 0x21, 0 - .dw 0x4383, 0xc414, 0x438f, 0xc414, 0x21, 0 - .dw 0x4391, 0xc414, 0x4391, 0xc414, 0x21, 0 - .dw 0x4393, 0xc414, 0x43bf, 0xc414, 0x21, 0 - .dw 0x43c1, 0xc414, 0x43c1, 0xc414, 0x21, 0 - .dw 0x43c3, 0xc414, 0x43cf, 0xc414, 0x21, 0 - .dw 0x43d1, 0xc414, 0x43d1, 0xc414, 0x21, 0 - .dw 0x43d3, 0xc414, 0x43ff, 0xc414, 0x21, 0 - .dw 0x4401, 0xc414, 0x4401, 0xc414, 0x21, 0 - .dw 0x4403, 0xc414, 0x440f, 0xc414, 0x21, 0 - .dw 0x4411, 0xc414, 0x4411, 0xc414, 0x21, 0 - .dw 0x4413, 0xc414, 0x443f, 0xc414, 0x21, 0 - .dw 0x4441, 0xc414, 0x4441, 0xc414, 0x21, 0 - .dw 0x4443, 0xc414, 0x444f, 0xc414, 0x21, 0 - .dw 0x4451, 0xc414, 0x4451, 0xc414, 0x21, 0 - .dw 0x4453, 0xc414, 0x447f, 0xc414, 0x21, 0 - .dw 0x4481, 0xc414, 0x4481, 0xc414, 0x21, 0 - .dw 0x4483, 0xc414, 0x448f, 0xc414, 0x21, 0 - .dw 0x4491, 0xc414, 0x4491, 0xc414, 0x21, 0 - .dw 0x4493, 0xc414, 0x44bf, 0xc414, 0x21, 0 - .dw 0x44c1, 0xc414, 0x44c1, 0xc414, 0x21, 0 - .dw 0x44c3, 0xc414, 0x44cf, 0xc414, 0x21, 0 - .dw 0x44d1, 0xc414, 0x44d1, 0xc414, 0x21, 0 - .dw 0x44d3, 0xc414, 0x44ff, 0xc414, 0x21, 0 - .dw 0x4501, 0xc414, 0x4501, 0xc414, 0x21, 0 - .dw 0x4503, 0xc414, 0x450f, 0xc414, 0x21, 0 - .dw 0x4511, 0xc414, 0x4511, 0xc414, 0x21, 0 - .dw 0x4513, 0xc414, 0x453f, 0xc414, 0x21, 0 - .dw 0x4541, 0xc414, 0x4541, 0xc414, 0x21, 0 - .dw 0x4543, 0xc414, 0x454f, 0xc414, 0x21, 0 - .dw 0x4551, 0xc414, 0x4551, 0xc414, 0x21, 0 - .dw 0x4553, 0xc414, 0x457f, 0xc414, 0x21, 0 - .dw 0x4581, 0xc414, 0x4581, 0xc414, 0x21, 0 - .dw 0x4583, 0xc414, 0x458f, 0xc414, 0x21, 0 - .dw 0x4591, 0xc414, 0x4591, 0xc414, 0x21, 0 - .dw 0x4593, 0xc414, 0x45bf, 0xc414, 0x21, 0 - .dw 0x45c1, 0xc414, 0x45c1, 0xc414, 0x21, 0 - .dw 0x45c3, 0xc414, 0x45cf, 0xc414, 0x21, 0 - .dw 0x45d1, 0xc414, 0x45d1, 0xc414, 0x21, 0 - .dw 0x45d3, 0xc414, 0x45ff, 0xc414, 0x21, 0 - .dw 0x4601, 0xc414, 0x4601, 0xc414, 0x21, 0 - .dw 0x4603, 0xc414, 0x460f, 0xc414, 0x21, 0 - .dw 0x4611, 0xc414, 0x4611, 0xc414, 0x21, 0 - .dw 0x4613, 0xc414, 0x463f, 0xc414, 0x21, 0 - .dw 0x4641, 0xc414, 0x4641, 0xc414, 0x21, 0 - .dw 0x4643, 0xc414, 0x464f, 0xc414, 0x21, 0 - .dw 0x4651, 0xc414, 0x4651, 0xc414, 0x21, 0 - .dw 0x4653, 0xc414, 0x467f, 0xc414, 0x21, 0 - .dw 0x4681, 0xc414, 0x4681, 0xc414, 0x21, 0 - .dw 0x4683, 0xc414, 0x468f, 0xc414, 0x21, 0 - .dw 0x4691, 0xc414, 0x4691, 0xc414, 0x21, 0 - .dw 0x4693, 0xc414, 0x46bf, 0xc414, 0x21, 0 - .dw 0x46c1, 0xc414, 0x46c1, 0xc414, 0x21, 0 - .dw 0x46c3, 0xc414, 0x46cf, 0xc414, 0x21, 0 - .dw 0x46d1, 0xc414, 0x46d1, 0xc414, 0x21, 0 - .dw 0x46d3, 0xc414, 0x46ff, 0xc414, 0x21, 0 - .dw 0x4701, 0xc414, 0x4701, 0xc414, 0x21, 0 - .dw 0x4703, 0xc414, 0x470f, 0xc414, 0x21, 0 - .dw 0x4711, 0xc414, 0x4711, 0xc414, 0x21, 0 - .dw 0x4713, 0xc414, 0x473f, 0xc414, 0x21, 0 - .dw 0x4741, 0xc414, 0x4741, 0xc414, 0x21, 0 - .dw 0x4743, 0xc414, 0x474f, 0xc414, 0x21, 0 - .dw 0x4751, 0xc414, 0x4751, 0xc414, 0x21, 0 - .dw 0x4753, 0xc414, 0x477f, 0xc414, 0x21, 0 - .dw 0x4781, 0xc414, 0x4781, 0xc414, 0x21, 0 - .dw 0x4783, 0xc414, 0x478f, 0xc414, 0x21, 0 - .dw 0x4791, 0xc414, 0x4791, 0xc414, 0x21, 0 - .dw 0x4793, 0xc414, 0x47bf, 0xc414, 0x21, 0 - .dw 0x47c1, 0xc414, 0x47c1, 0xc414, 0x21, 0 - .dw 0x47c3, 0xc414, 0x47cf, 0xc414, 0x21, 0 - .dw 0x47d1, 0xc414, 0x47d1, 0xc414, 0x21, 0 - .dw 0x47d3, 0xc414, 0x47ff, 0xc414, 0x21, 0 - .dw 0x4801, 0xc414, 0x4801, 0xc414, 0x21, 0 - .dw 0x4803, 0xc414, 0x480f, 0xc414, 0x21, 0 - .dw 0x4811, 0xc414, 0x4811, 0xc414, 0x21, 0 - .dw 0x4813, 0xc414, 0x483f, 0xc414, 0x21, 0 - .dw 0x4841, 0xc414, 0x4841, 0xc414, 0x21, 0 - .dw 0x4843, 0xc414, 0x484f, 0xc414, 0x21, 0 - .dw 0x4851, 0xc414, 0x4851, 0xc414, 0x21, 0 - .dw 0x4853, 0xc414, 0x487f, 0xc414, 0x21, 0 - .dw 0x4881, 0xc414, 0x4881, 0xc414, 0x21, 0 - .dw 0x4883, 0xc414, 0x488f, 0xc414, 0x21, 0 - .dw 0x4891, 0xc414, 0x4891, 0xc414, 0x21, 0 - .dw 0x4893, 0xc414, 0x48bf, 0xc414, 0x21, 0 - .dw 0x48c1, 0xc414, 0x48c1, 0xc414, 0x21, 0 - .dw 0x48c3, 0xc414, 0x48cf, 0xc414, 0x21, 0 - .dw 0x48d1, 0xc414, 0x48d1, 0xc414, 0x21, 0 - .dw 0x48d3, 0xc414, 0x48ff, 0xc414, 0x21, 0 - .dw 0x4901, 0xc414, 0x4901, 0xc414, 0x21, 0 - .dw 0x4903, 0xc414, 0x490f, 0xc414, 0x21, 0 - .dw 0x4911, 0xc414, 0x4911, 0xc414, 0x21, 0 - .dw 0x4913, 0xc414, 0x493f, 0xc414, 0x21, 0 - .dw 0x4941, 0xc414, 0x4941, 0xc414, 0x21, 0 - .dw 0x4943, 0xc414, 0x494f, 0xc414, 0x21, 0 - .dw 0x4951, 0xc414, 0x4951, 0xc414, 0x21, 0 - .dw 0x4953, 0xc414, 0x497f, 0xc414, 0x21, 0 - .dw 0x4981, 0xc414, 0x4981, 0xc414, 0x21, 0 - .dw 0x4983, 0xc414, 0x498f, 0xc414, 0x21, 0 - .dw 0x4991, 0xc414, 0x4991, 0xc414, 0x21, 0 - .dw 0x4993, 0xc414, 0x49bf, 0xc414, 0x21, 0 - .dw 0x49c1, 0xc414, 0x49c1, 0xc414, 0x21, 0 - .dw 0x49c3, 0xc414, 0x49cf, 0xc414, 0x21, 0 - .dw 0x49d1, 0xc414, 0x49d1, 0xc414, 0x21, 0 - .dw 0x49d3, 0xc414, 0x49ff, 0xc414, 0x21, 0 - .dw 0x4a01, 0xc414, 0x4a01, 0xc414, 0x21, 0 - .dw 0x4a03, 0xc414, 0x4a0f, 0xc414, 0x21, 0 - .dw 0x4a11, 0xc414, 0x4a11, 0xc414, 0x21, 0 - .dw 0x4a13, 0xc414, 0x4a3f, 0xc414, 0x21, 0 - .dw 0x4a41, 0xc414, 0x4a41, 0xc414, 0x21, 0 - .dw 0x4a43, 0xc414, 0x4a4f, 0xc414, 0x21, 0 - .dw 0x4a51, 0xc414, 0x4a51, 0xc414, 0x21, 0 - .dw 0x4a53, 0xc414, 0x4a7f, 0xc414, 0x21, 0 - .dw 0x4a81, 0xc414, 0x4a81, 0xc414, 0x21, 0 - .dw 0x4a83, 0xc414, 0x4a8f, 0xc414, 0x21, 0 - .dw 0x4a91, 0xc414, 0x4a91, 0xc414, 0x21, 0 - .dw 0x4a93, 0xc414, 0x4abf, 0xc414, 0x21, 0 - .dw 0x4ac1, 0xc414, 0x4ac1, 0xc414, 0x21, 0 - .dw 0x4ac3, 0xc414, 0x4acf, 0xc414, 0x21, 0 - .dw 0x4ad1, 0xc414, 0x4ad1, 0xc414, 0x21, 0 - .dw 0x4ad3, 0xc414, 0x4aff, 0xc414, 0x21, 0 - .dw 0x4b01, 0xc414, 0x4b01, 0xc414, 0x21, 0 - .dw 0x4b03, 0xc414, 0x4b0f, 0xc414, 0x21, 0 - .dw 0x4b11, 0xc414, 0x4b11, 0xc414, 0x21, 0 - .dw 0x4b13, 0xc414, 0x4b3f, 0xc414, 0x21, 0 - .dw 0x4b41, 0xc414, 0x4b41, 0xc414, 0x21, 0 - .dw 0x4b43, 0xc414, 0x4b4f, 0xc414, 0x21, 0 - .dw 0x4b51, 0xc414, 0x4b51, 0xc414, 0x21, 0 - .dw 0x4b53, 0xc414, 0x4b7f, 0xc414, 0x21, 0 - .dw 0x4b81, 0xc414, 0x4b81, 0xc414, 0x21, 0 - .dw 0x4b83, 0xc414, 0x4b8f, 0xc414, 0x21, 0 - .dw 0x4b91, 0xc414, 0x4b91, 0xc414, 0x21, 0 - .dw 0x4b93, 0xc414, 0x4bbf, 0xc414, 0x21, 0 - .dw 0x4bc1, 0xc414, 0x4bc1, 0xc414, 0x21, 0 - .dw 0x4bc3, 0xc414, 0x4bcf, 0xc414, 0x21, 0 - .dw 0x4bd1, 0xc414, 0x4bd1, 0xc414, 0x21, 0 - .dw 0x4bd3, 0xc414, 0x4bff, 0xc414, 0x21, 0 - .dw 0x4c01, 0xc414, 0x4c01, 0xc414, 0x21, 0 - .dw 0x4c03, 0xc414, 0x4c0f, 0xc414, 0x21, 0 - .dw 0x4c11, 0xc414, 0x4c11, 0xc414, 0x21, 0 - .dw 0x4c13, 0xc414, 0x4c3f, 0xc414, 0x21, 0 - .dw 0x4c41, 0xc414, 0x4c41, 0xc414, 0x21, 0 - .dw 0x4c43, 0xc414, 0x4c4f, 0xc414, 0x21, 0 - .dw 0x4c51, 0xc414, 0x4c51, 0xc414, 0x21, 0 - .dw 0x4c53, 0xc414, 0x4c7f, 0xc414, 0x21, 0 - .dw 0x4c81, 0xc414, 0x4c81, 0xc414, 0x21, 0 - .dw 0x4c83, 0xc414, 0x4c8f, 0xc414, 0x21, 0 - .dw 0x4c91, 0xc414, 0x4c91, 0xc414, 0x21, 0 - .dw 0x4c93, 0xc414, 0x4cbf, 0xc414, 0x21, 0 - .dw 0x4cc1, 0xc414, 0x4cc1, 0xc414, 0x21, 0 - .dw 0x4cc3, 0xc414, 0x4ccf, 0xc414, 0x21, 0 - .dw 0x4cd1, 0xc414, 0x4cd1, 0xc414, 0x21, 0 - .dw 0x4cd3, 0xc414, 0x4cff, 0xc414, 0x21, 0 - .dw 0x4d01, 0xc414, 0x4d01, 0xc414, 0x21, 0 - .dw 0x4d03, 0xc414, 0x4d0f, 0xc414, 0x21, 0 - .dw 0x4d11, 0xc414, 0x4d11, 0xc414, 0x21, 0 - .dw 0x4d13, 0xc414, 0x4d3f, 0xc414, 0x21, 0 - .dw 0x4d41, 0xc414, 0x4d41, 0xc414, 0x21, 0 - .dw 0x4d43, 0xc414, 0x4d4f, 0xc414, 0x21, 0 - .dw 0x4d51, 0xc414, 0x4d51, 0xc414, 0x21, 0 - .dw 0x4d53, 0xc414, 0x4d7f, 0xc414, 0x21, 0 - .dw 0x4d81, 0xc414, 0x4d81, 0xc414, 0x21, 0 - .dw 0x4d83, 0xc414, 0x4d8f, 0xc414, 0x21, 0 - .dw 0x4d91, 0xc414, 0x4d91, 0xc414, 0x21, 0 - .dw 0x4d93, 0xc414, 0x4dbf, 0xc414, 0x21, 0 - .dw 0x4dc1, 0xc414, 0x4dc1, 0xc414, 0x21, 0 - .dw 0x4dc3, 0xc414, 0x4dcf, 0xc414, 0x21, 0 - .dw 0x4dd1, 0xc414, 0x4dd1, 0xc414, 0x21, 0 - .dw 0x4dd3, 0xc414, 0x4dff, 0xc414, 0x21, 0 - .dw 0x4e01, 0xc414, 0x4e01, 0xc414, 0x21, 0 - .dw 0x4e03, 0xc414, 0x4e0f, 0xc414, 0x21, 0 - .dw 0x4e11, 0xc414, 0x4e11, 0xc414, 0x21, 0 - .dw 0x4e13, 0xc414, 0x4e3f, 0xc414, 0x21, 0 - .dw 0x4e41, 0xc414, 0x4e41, 0xc414, 0x21, 0 - .dw 0x4e43, 0xc414, 0x4e4f, 0xc414, 0x21, 0 - .dw 0x4e51, 0xc414, 0x4e51, 0xc414, 0x21, 0 - .dw 0x4e53, 0xc414, 0x4e7f, 0xc414, 0x21, 0 - .dw 0x4e81, 0xc414, 0x4e81, 0xc414, 0x21, 0 - .dw 0x4e83, 0xc414, 0x4e8f, 0xc414, 0x21, 0 - .dw 0x4e91, 0xc414, 0x4e91, 0xc414, 0x21, 0 - .dw 0x4e93, 0xc414, 0x4ebf, 0xc414, 0x21, 0 - .dw 0x4ec1, 0xc414, 0x4ec1, 0xc414, 0x21, 0 - .dw 0x4ec3, 0xc414, 0x4ecf, 0xc414, 0x21, 0 - .dw 0x4ed1, 0xc414, 0x4ed1, 0xc414, 0x21, 0 - .dw 0x4ed3, 0xc414, 0x4eff, 0xc414, 0x21, 0 - .dw 0x4f01, 0xc414, 0x4f01, 0xc414, 0x21, 0 - .dw 0x4f03, 0xc414, 0x4f0f, 0xc414, 0x21, 0 - .dw 0x4f11, 0xc414, 0x4f11, 0xc414, 0x21, 0 - .dw 0x4f13, 0xc414, 0x4f3f, 0xc414, 0x21, 0 - .dw 0x4f41, 0xc414, 0x4f41, 0xc414, 0x21, 0 - .dw 0x4f43, 0xc414, 0x4f4f, 0xc414, 0x21, 0 - .dw 0x4f51, 0xc414, 0x4f51, 0xc414, 0x21, 0 - .dw 0x4f53, 0xc414, 0x4f7f, 0xc414, 0x21, 0 - .dw 0x4f81, 0xc414, 0x4f81, 0xc414, 0x21, 0 - .dw 0x4f83, 0xc414, 0x4f8f, 0xc414, 0x21, 0 - .dw 0x4f91, 0xc414, 0x4f91, 0xc414, 0x21, 0 - .dw 0x4f93, 0xc414, 0x4fbf, 0xc414, 0x21, 0 - .dw 0x4fc1, 0xc414, 0x4fc1, 0xc414, 0x21, 0 - .dw 0x4fc3, 0xc414, 0x4fcf, 0xc414, 0x21, 0 - .dw 0x4fd1, 0xc414, 0x4fd1, 0xc414, 0x21, 0 - .dw 0x4fd3, 0xc414, 0x5fff, 0xc414, 0x21, 0 - .dw 0x6001, 0xc414, 0x6001, 0xc414, 0x21, 0 - .dw 0x6003, 0xc414, 0x600f, 0xc414, 0x21, 0 - .dw 0x6011, 0xc414, 0x6011, 0xc414, 0x21, 0 - .dw 0x6013, 0xc414, 0x603f, 0xc414, 0x21, 0 - .dw 0x6041, 0xc414, 0x6041, 0xc414, 0x21, 0 - .dw 0x6043, 0xc414, 0x604f, 0xc414, 0x21, 0 - .dw 0x6051, 0xc414, 0x6051, 0xc414, 0x21, 0 - .dw 0x6053, 0xc414, 0x607f, 0xc414, 0x21, 0 - .dw 0x6081, 0xc414, 0x6081, 0xc414, 0x21, 0 - .dw 0x6083, 0xc414, 0x608f, 0xc414, 0x21, 0 - .dw 0x6091, 0xc414, 0x6091, 0xc414, 0x21, 0 - .dw 0x6093, 0xc414, 0x60bf, 0xc414, 0x21, 0 - .dw 0x60c1, 0xc414, 0x60c1, 0xc414, 0x21, 0 - .dw 0x60c3, 0xc414, 0x60cf, 0xc414, 0x21, 0 - .dw 0x60d1, 0xc414, 0x60d1, 0xc414, 0x21, 0 - .dw 0x60d3, 0xc414, 0x60ff, 0xc414, 0x21, 0 - .dw 0x6101, 0xc414, 0x6101, 0xc414, 0x21, 0 - .dw 0x6103, 0xc414, 0x610f, 0xc414, 0x21, 0 - .dw 0x6111, 0xc414, 0x6111, 0xc414, 0x21, 0 - .dw 0x6113, 0xc414, 0x613f, 0xc414, 0x21, 0 - .dw 0x6141, 0xc414, 0x6141, 0xc414, 0x21, 0 - .dw 0x6143, 0xc414, 0x614f, 0xc414, 0x21, 0 - .dw 0x6151, 0xc414, 0x6151, 0xc414, 0x21, 0 - .dw 0x6153, 0xc414, 0x617f, 0xc414, 0x21, 0 - .dw 0x6181, 0xc414, 0x6181, 0xc414, 0x21, 0 - .dw 0x6183, 0xc414, 0x618f, 0xc414, 0x21, 0 - .dw 0x6191, 0xc414, 0x6191, 0xc414, 0x21, 0 - .dw 0x6193, 0xc414, 0x61bf, 0xc414, 0x21, 0 - .dw 0x61c1, 0xc414, 0x61c1, 0xc414, 0x21, 0 - .dw 0x61c3, 0xc414, 0x61cf, 0xc414, 0x21, 0 - .dw 0x61d1, 0xc414, 0x61d1, 0xc414, 0x21, 0 - .dw 0x61d3, 0xc414, 0x61ff, 0xc414, 0x21, 0 - .dw 0x6201, 0xc414, 0x6201, 0xc414, 0x21, 0 - .dw 0x6203, 0xc414, 0x620f, 0xc414, 0x21, 0 - .dw 0x6211, 0xc414, 0x6211, 0xc414, 0x21, 0 - .dw 0x6213, 0xc414, 0x623f, 0xc414, 0x21, 0 - .dw 0x6241, 0xc414, 0x6241, 0xc414, 0x21, 0 - .dw 0x6243, 0xc414, 0x624f, 0xc414, 0x21, 0 - .dw 0x6251, 0xc414, 0x6251, 0xc414, 0x21, 0 - .dw 0x6253, 0xc414, 0x627f, 0xc414, 0x21, 0 - .dw 0x6281, 0xc414, 0x6281, 0xc414, 0x21, 0 - .dw 0x6283, 0xc414, 0x628f, 0xc414, 0x21, 0 - .dw 0x6291, 0xc414, 0x6291, 0xc414, 0x21, 0 - .dw 0x6293, 0xc414, 0x62bf, 0xc414, 0x21, 0 - .dw 0x62c1, 0xc414, 0x62c1, 0xc414, 0x21, 0 - .dw 0x62c3, 0xc414, 0x62cf, 0xc414, 0x21, 0 - .dw 0x62d1, 0xc414, 0x62d1, 0xc414, 0x21, 0 - .dw 0x62d3, 0xc414, 0x62ff, 0xc414, 0x21, 0 - .dw 0x6301, 0xc414, 0x6301, 0xc414, 0x21, 0 - .dw 0x6303, 0xc414, 0x630f, 0xc414, 0x21, 0 - .dw 0x6311, 0xc414, 0x6311, 0xc414, 0x21, 0 - .dw 0x6313, 0xc414, 0x633f, 0xc414, 0x21, 0 - .dw 0x6341, 0xc414, 0x6341, 0xc414, 0x21, 0 - .dw 0x6343, 0xc414, 0x634f, 0xc414, 0x21, 0 - .dw 0x6351, 0xc414, 0x6351, 0xc414, 0x21, 0 - .dw 0x6353, 0xc414, 0x637f, 0xc414, 0x21, 0 - .dw 0x6381, 0xc414, 0x6381, 0xc414, 0x21, 0 - .dw 0x6383, 0xc414, 0x638f, 0xc414, 0x21, 0 - .dw 0x6391, 0xc414, 0x6391, 0xc414, 0x21, 0 - .dw 0x6393, 0xc414, 0x63bf, 0xc414, 0x21, 0 - .dw 0x63c1, 0xc414, 0x63c1, 0xc414, 0x21, 0 - .dw 0x63c3, 0xc414, 0x63cf, 0xc414, 0x21, 0 - .dw 0x63d1, 0xc414, 0x63d1, 0xc414, 0x21, 0 - .dw 0x63d3, 0xc414, 0x63ff, 0xc414, 0x21, 0 - .dw 0x6401, 0xc414, 0x6401, 0xc414, 0x21, 0 - .dw 0x6403, 0xc414, 0x640f, 0xc414, 0x21, 0 - .dw 0x6411, 0xc414, 0x6411, 0xc414, 0x21, 0 - .dw 0x6413, 0xc414, 0x643f, 0xc414, 0x21, 0 - .dw 0x6441, 0xc414, 0x6441, 0xc414, 0x21, 0 - .dw 0x6443, 0xc414, 0x644f, 0xc414, 0x21, 0 - .dw 0x6451, 0xc414, 0x6451, 0xc414, 0x21, 0 - .dw 0x6453, 0xc414, 0x647f, 0xc414, 0x21, 0 - .dw 0x6481, 0xc414, 0x6481, 0xc414, 0x21, 0 - .dw 0x6483, 0xc414, 0x648f, 0xc414, 0x21, 0 - .dw 0x6491, 0xc414, 0x6491, 0xc414, 0x21, 0 - .dw 0x6493, 0xc414, 0x64bf, 0xc414, 0x21, 0 - .dw 0x64c1, 0xc414, 0x64c1, 0xc414, 0x21, 0 - .dw 0x64c3, 0xc414, 0x64cf, 0xc414, 0x21, 0 - .dw 0x64d1, 0xc414, 0x64d1, 0xc414, 0x21, 0 - .dw 0x64d3, 0xc414, 0x64ff, 0xc414, 0x21, 0 - .dw 0x6501, 0xc414, 0x6501, 0xc414, 0x21, 0 - .dw 0x6503, 0xc414, 0x650f, 0xc414, 0x21, 0 - .dw 0x6511, 0xc414, 0x6511, 0xc414, 0x21, 0 - .dw 0x6513, 0xc414, 0x653f, 0xc414, 0x21, 0 - .dw 0x6541, 0xc414, 0x6541, 0xc414, 0x21, 0 - .dw 0x6543, 0xc414, 0x654f, 0xc414, 0x21, 0 - .dw 0x6551, 0xc414, 0x6551, 0xc414, 0x21, 0 - .dw 0x6553, 0xc414, 0x657f, 0xc414, 0x21, 0 - .dw 0x6581, 0xc414, 0x6581, 0xc414, 0x21, 0 - .dw 0x6583, 0xc414, 0x658f, 0xc414, 0x21, 0 - .dw 0x6591, 0xc414, 0x6591, 0xc414, 0x21, 0 - .dw 0x6593, 0xc414, 0x65bf, 0xc414, 0x21, 0 - .dw 0x65c1, 0xc414, 0x65c1, 0xc414, 0x21, 0 - .dw 0x65c3, 0xc414, 0x65cf, 0xc414, 0x21, 0 - .dw 0x65d1, 0xc414, 0x65d1, 0xc414, 0x21, 0 - .dw 0x65d3, 0xc414, 0x65ff, 0xc414, 0x21, 0 - .dw 0x6601, 0xc414, 0x6601, 0xc414, 0x21, 0 - .dw 0x6603, 0xc414, 0x660f, 0xc414, 0x21, 0 - .dw 0x6611, 0xc414, 0x6611, 0xc414, 0x21, 0 - .dw 0x6613, 0xc414, 0x663f, 0xc414, 0x21, 0 - .dw 0x6641, 0xc414, 0x6641, 0xc414, 0x21, 0 - .dw 0x6643, 0xc414, 0x664f, 0xc414, 0x21, 0 - .dw 0x6651, 0xc414, 0x6651, 0xc414, 0x21, 0 - .dw 0x6653, 0xc414, 0x667f, 0xc414, 0x21, 0 - .dw 0x6681, 0xc414, 0x6681, 0xc414, 0x21, 0 - .dw 0x6683, 0xc414, 0x668f, 0xc414, 0x21, 0 - .dw 0x6691, 0xc414, 0x6691, 0xc414, 0x21, 0 - .dw 0x6693, 0xc414, 0x66bf, 0xc414, 0x21, 0 - .dw 0x66c1, 0xc414, 0x66c1, 0xc414, 0x21, 0 - .dw 0x66c3, 0xc414, 0x66cf, 0xc414, 0x21, 0 - .dw 0x66d1, 0xc414, 0x66d1, 0xc414, 0x21, 0 - .dw 0x66d3, 0xc414, 0x66ff, 0xc414, 0x21, 0 - .dw 0x6701, 0xc414, 0x6701, 0xc414, 0x21, 0 - .dw 0x6703, 0xc414, 0x670f, 0xc414, 0x21, 0 - .dw 0x6711, 0xc414, 0x6711, 0xc414, 0x21, 0 - .dw 0x6713, 0xc414, 0x673f, 0xc414, 0x21, 0 - .dw 0x6741, 0xc414, 0x6741, 0xc414, 0x21, 0 - .dw 0x6743, 0xc414, 0x674f, 0xc414, 0x21, 0 - .dw 0x6751, 0xc414, 0x6751, 0xc414, 0x21, 0 - .dw 0x6753, 0xc414, 0x677f, 0xc414, 0x21, 0 - .dw 0x6781, 0xc414, 0x6781, 0xc414, 0x21, 0 - .dw 0x6783, 0xc414, 0x678f, 0xc414, 0x21, 0 - .dw 0x6791, 0xc414, 0x6791, 0xc414, 0x21, 0 - .dw 0x6793, 0xc414, 0x67bf, 0xc414, 0x21, 0 - .dw 0x67c1, 0xc414, 0x67c1, 0xc414, 0x21, 0 - .dw 0x67c3, 0xc414, 0x67cf, 0xc414, 0x21, 0 - .dw 0x67d1, 0xc414, 0x67d1, 0xc414, 0x21, 0 - .dw 0x67d3, 0xc414, 0x67ff, 0xc414, 0x21, 0 - .dw 0x6801, 0xc414, 0x6801, 0xc414, 0x21, 0 - .dw 0x6803, 0xc414, 0x680f, 0xc414, 0x21, 0 - .dw 0x6811, 0xc414, 0x6811, 0xc414, 0x21, 0 - .dw 0x6813, 0xc414, 0x683f, 0xc414, 0x21, 0 - .dw 0x6841, 0xc414, 0x6841, 0xc414, 0x21, 0 - .dw 0x6843, 0xc414, 0x684f, 0xc414, 0x21, 0 - .dw 0x6851, 0xc414, 0x6851, 0xc414, 0x21, 0 - .dw 0x6853, 0xc414, 0x687f, 0xc414, 0x21, 0 - .dw 0x6881, 0xc414, 0x6881, 0xc414, 0x21, 0 - .dw 0x6883, 0xc414, 0x688f, 0xc414, 0x21, 0 - .dw 0x6891, 0xc414, 0x6891, 0xc414, 0x21, 0 - .dw 0x6893, 0xc414, 0x68bf, 0xc414, 0x21, 0 - .dw 0x68c1, 0xc414, 0x68c1, 0xc414, 0x21, 0 - .dw 0x68c3, 0xc414, 0x68cf, 0xc414, 0x21, 0 - .dw 0x68d1, 0xc414, 0x68d1, 0xc414, 0x21, 0 - .dw 0x68d3, 0xc414, 0x68ff, 0xc414, 0x21, 0 - .dw 0x6901, 0xc414, 0x6901, 0xc414, 0x21, 0 - .dw 0x6903, 0xc414, 0x690f, 0xc414, 0x21, 0 - .dw 0x6911, 0xc414, 0x6911, 0xc414, 0x21, 0 - .dw 0x6913, 0xc414, 0x693f, 0xc414, 0x21, 0 - .dw 0x6941, 0xc414, 0x6941, 0xc414, 0x21, 0 - .dw 0x6943, 0xc414, 0x694f, 0xc414, 0x21, 0 - .dw 0x6951, 0xc414, 0x6951, 0xc414, 0x21, 0 - .dw 0x6953, 0xc414, 0x697f, 0xc414, 0x21, 0 - .dw 0x6981, 0xc414, 0x6981, 0xc414, 0x21, 0 - .dw 0x6983, 0xc414, 0x698f, 0xc414, 0x21, 0 - .dw 0x6991, 0xc414, 0x6991, 0xc414, 0x21, 0 - .dw 0x6993, 0xc414, 0x69bf, 0xc414, 0x21, 0 - .dw 0x69c1, 0xc414, 0x69c1, 0xc414, 0x21, 0 - .dw 0x69c3, 0xc414, 0x69cf, 0xc414, 0x21, 0 - .dw 0x69d1, 0xc414, 0x69d1, 0xc414, 0x21, 0 - .dw 0x69d3, 0xc414, 0x69ff, 0xc414, 0x21, 0 - .dw 0x6a01, 0xc414, 0x6a01, 0xc414, 0x21, 0 - .dw 0x6a03, 0xc414, 0x6a0f, 0xc414, 0x21, 0 - .dw 0x6a11, 0xc414, 0x6a11, 0xc414, 0x21, 0 - .dw 0x6a13, 0xc414, 0x6a3f, 0xc414, 0x21, 0 - .dw 0x6a41, 0xc414, 0x6a41, 0xc414, 0x21, 0 - .dw 0x6a43, 0xc414, 0x6a4f, 0xc414, 0x21, 0 - .dw 0x6a51, 0xc414, 0x6a51, 0xc414, 0x21, 0 - .dw 0x6a53, 0xc414, 0x6a7f, 0xc414, 0x21, 0 - .dw 0x6a81, 0xc414, 0x6a81, 0xc414, 0x21, 0 - .dw 0x6a83, 0xc414, 0x6a8f, 0xc414, 0x21, 0 - .dw 0x6a91, 0xc414, 0x6a91, 0xc414, 0x21, 0 - .dw 0x6a93, 0xc414, 0x6abf, 0xc414, 0x21, 0 - .dw 0x6ac1, 0xc414, 0x6ac1, 0xc414, 0x21, 0 - .dw 0x6ac3, 0xc414, 0x6acf, 0xc414, 0x21, 0 - .dw 0x6ad1, 0xc414, 0x6ad1, 0xc414, 0x21, 0 - .dw 0x6ad3, 0xc414, 0x6aff, 0xc414, 0x21, 0 - .dw 0x6b01, 0xc414, 0x6b01, 0xc414, 0x21, 0 - .dw 0x6b03, 0xc414, 0x6b0f, 0xc414, 0x21, 0 - .dw 0x6b11, 0xc414, 0x6b11, 0xc414, 0x21, 0 - .dw 0x6b13, 0xc414, 0x6b3f, 0xc414, 0x21, 0 - .dw 0x6b41, 0xc414, 0x6b41, 0xc414, 0x21, 0 - .dw 0x6b43, 0xc414, 0x6b4f, 0xc414, 0x21, 0 - .dw 0x6b51, 0xc414, 0x6b51, 0xc414, 0x21, 0 - .dw 0x6b53, 0xc414, 0x6b7f, 0xc414, 0x21, 0 - .dw 0x6b81, 0xc414, 0x6b81, 0xc414, 0x21, 0 - .dw 0x6b83, 0xc414, 0x6b8f, 0xc414, 0x21, 0 - .dw 0x6b91, 0xc414, 0x6b91, 0xc414, 0x21, 0 - .dw 0x6b93, 0xc414, 0x6bbf, 0xc414, 0x21, 0 - .dw 0x6bc1, 0xc414, 0x6bc1, 0xc414, 0x21, 0 - .dw 0x6bc3, 0xc414, 0x6bcf, 0xc414, 0x21, 0 - .dw 0x6bd1, 0xc414, 0x6bd1, 0xc414, 0x21, 0 - .dw 0x6bd3, 0xc414, 0x6bff, 0xc414, 0x21, 0 - .dw 0x6c01, 0xc414, 0x6c01, 0xc414, 0x21, 0 - .dw 0x6c03, 0xc414, 0x6c0f, 0xc414, 0x21, 0 - .dw 0x6c11, 0xc414, 0x6c11, 0xc414, 0x21, 0 - .dw 0x6c13, 0xc414, 0x6c3f, 0xc414, 0x21, 0 - .dw 0x6c41, 0xc414, 0x6c41, 0xc414, 0x21, 0 - .dw 0x6c43, 0xc414, 0x6c4f, 0xc414, 0x21, 0 - .dw 0x6c51, 0xc414, 0x6c51, 0xc414, 0x21, 0 - .dw 0x6c53, 0xc414, 0x6c7f, 0xc414, 0x21, 0 - .dw 0x6c81, 0xc414, 0x6c81, 0xc414, 0x21, 0 - .dw 0x6c83, 0xc414, 0x6c8f, 0xc414, 0x21, 0 - .dw 0x6c91, 0xc414, 0x6c91, 0xc414, 0x21, 0 - .dw 0x6c93, 0xc414, 0x6cbf, 0xc414, 0x21, 0 - .dw 0x6cc1, 0xc414, 0x6cc1, 0xc414, 0x21, 0 - .dw 0x6cc3, 0xc414, 0x6ccf, 0xc414, 0x21, 0 - .dw 0x6cd1, 0xc414, 0x6cd1, 0xc414, 0x21, 0 - .dw 0x6cd3, 0xc414, 0x6cff, 0xc414, 0x21, 0 - .dw 0x6d01, 0xc414, 0x6d01, 0xc414, 0x21, 0 - .dw 0x6d03, 0xc414, 0x6d0f, 0xc414, 0x21, 0 - .dw 0x6d11, 0xc414, 0x6d11, 0xc414, 0x21, 0 - .dw 0x6d13, 0xc414, 0x6d3f, 0xc414, 0x21, 0 - .dw 0x6d41, 0xc414, 0x6d41, 0xc414, 0x21, 0 - .dw 0x6d43, 0xc414, 0x6d4f, 0xc414, 0x21, 0 - .dw 0x6d51, 0xc414, 0x6d51, 0xc414, 0x21, 0 - .dw 0x6d53, 0xc414, 0x6d7f, 0xc414, 0x21, 0 - .dw 0x6d81, 0xc414, 0x6d81, 0xc414, 0x21, 0 - .dw 0x6d83, 0xc414, 0x6d8f, 0xc414, 0x21, 0 - .dw 0x6d91, 0xc414, 0x6d91, 0xc414, 0x21, 0 - .dw 0x6d93, 0xc414, 0x6dbf, 0xc414, 0x21, 0 - .dw 0x6dc1, 0xc414, 0x6dc1, 0xc414, 0x21, 0 - .dw 0x6dc3, 0xc414, 0x6dcf, 0xc414, 0x21, 0 - .dw 0x6dd1, 0xc414, 0x6dd1, 0xc414, 0x21, 0 - .dw 0x6dd3, 0xc414, 0x6dff, 0xc414, 0x21, 0 - .dw 0x6e01, 0xc414, 0x6e01, 0xc414, 0x21, 0 - .dw 0x6e03, 0xc414, 0x6e0f, 0xc414, 0x21, 0 - .dw 0x6e11, 0xc414, 0x6e11, 0xc414, 0x21, 0 - .dw 0x6e13, 0xc414, 0x6e3f, 0xc414, 0x21, 0 - .dw 0x6e41, 0xc414, 0x6e41, 0xc414, 0x21, 0 - .dw 0x6e43, 0xc414, 0x6e4f, 0xc414, 0x21, 0 - .dw 0x6e51, 0xc414, 0x6e51, 0xc414, 0x21, 0 - .dw 0x6e53, 0xc414, 0x6e7f, 0xc414, 0x21, 0 - .dw 0x6e81, 0xc414, 0x6e81, 0xc414, 0x21, 0 - .dw 0x6e83, 0xc414, 0x6e8f, 0xc414, 0x21, 0 - .dw 0x6e91, 0xc414, 0x6e91, 0xc414, 0x21, 0 - .dw 0x6e93, 0xc414, 0x6ebf, 0xc414, 0x21, 0 - .dw 0x6ec1, 0xc414, 0x6ec1, 0xc414, 0x21, 0 - .dw 0x6ec3, 0xc414, 0x6ecf, 0xc414, 0x21, 0 - .dw 0x6ed1, 0xc414, 0x6ed1, 0xc414, 0x21, 0 - .dw 0x6ed3, 0xc414, 0x6eff, 0xc414, 0x21, 0 - .dw 0x6f01, 0xc414, 0x6f01, 0xc414, 0x21, 0 - .dw 0x6f03, 0xc414, 0x6f0f, 0xc414, 0x21, 0 - .dw 0x6f11, 0xc414, 0x6f11, 0xc414, 0x21, 0 - .dw 0x6f13, 0xc414, 0x6f3f, 0xc414, 0x21, 0 - .dw 0x6f41, 0xc414, 0x6f41, 0xc414, 0x21, 0 - .dw 0x6f43, 0xc414, 0x6f4f, 0xc414, 0x21, 0 - .dw 0x6f51, 0xc414, 0x6f51, 0xc414, 0x21, 0 - .dw 0x6f53, 0xc414, 0x6f7f, 0xc414, 0x21, 0 - .dw 0x6f81, 0xc414, 0x6f81, 0xc414, 0x21, 0 - .dw 0x6f83, 0xc414, 0x6f8f, 0xc414, 0x21, 0 - .dw 0x6f91, 0xc414, 0x6f91, 0xc414, 0x21, 0 - .dw 0x6f93, 0xc414, 0x6fbf, 0xc414, 0x21, 0 - .dw 0x6fc1, 0xc414, 0x6fc1, 0xc414, 0x21, 0 - .dw 0x6fc3, 0xc414, 0x6fcf, 0xc414, 0x21, 0 - .dw 0x6fd1, 0xc414, 0x6fd1, 0xc414, 0x21, 0 - .dw 0x6fd3, 0xc414, 0xffff, 0xc414, 0x21, 0 - .dw 0x0000, 0xc415, 0x0000, 0xc415, 0x22, 0 - .dw 0x0001, 0xc415, 0x0001, 0xc415, 0x21, 0 - .dw 0x0002, 0xc415, 0x0002, 0xc415, 0x22, 0 - .dw 0x0003, 0xc415, 0x000f, 0xc415, 0x21, 0 - .dw 0x0010, 0xc415, 0x0010, 0xc415, 0x22, 0 - .dw 0x0011, 0xc415, 0x0011, 0xc415, 0x21, 0 - .dw 0x0012, 0xc415, 0x0012, 0xc415, 0x22, 0 - .dw 0x0013, 0xc415, 0x003f, 0xc415, 0x21, 0 - .dw 0x0041, 0xc415, 0x0041, 0xc415, 0x21, 0 - .dw 0x0043, 0xc415, 0x004f, 0xc415, 0x21, 0 - .dw 0x0051, 0xc415, 0x0051, 0xc415, 0x21, 0 - .dw 0x0053, 0xc415, 0x007f, 0xc415, 0x21, 0 - .dw 0x0081, 0xc415, 0x0081, 0xc415, 0x21, 0 - .dw 0x0083, 0xc415, 0x008f, 0xc415, 0x21, 0 - .dw 0x0091, 0xc415, 0x0091, 0xc415, 0x21, 0 - .dw 0x0093, 0xc415, 0x00bf, 0xc415, 0x21, 0 - .dw 0x00c1, 0xc415, 0x00c1, 0xc415, 0x21, 0 - .dw 0x00c3, 0xc415, 0x00cf, 0xc415, 0x21, 0 - .dw 0x00d1, 0xc415, 0x00d1, 0xc415, 0x21, 0 - .dw 0x00d3, 0xc415, 0x00ff, 0xc415, 0x21, 0 - .dw 0x0101, 0xc415, 0x0101, 0xc415, 0x21, 0 - .dw 0x0103, 0xc415, 0x010f, 0xc415, 0x21, 0 - .dw 0x0111, 0xc415, 0x0111, 0xc415, 0x21, 0 - .dw 0x0113, 0xc415, 0x013f, 0xc415, 0x21, 0 - .dw 0x0141, 0xc415, 0x0141, 0xc415, 0x21, 0 - .dw 0x0143, 0xc415, 0x014f, 0xc415, 0x21, 0 - .dw 0x0151, 0xc415, 0x0151, 0xc415, 0x21, 0 - .dw 0x0153, 0xc415, 0x017f, 0xc415, 0x21, 0 - .dw 0x0181, 0xc415, 0x0181, 0xc415, 0x21, 0 - .dw 0x0183, 0xc415, 0x018f, 0xc415, 0x21, 0 - .dw 0x0191, 0xc415, 0x0191, 0xc415, 0x21, 0 - .dw 0x0193, 0xc415, 0x01bf, 0xc415, 0x21, 0 - .dw 0x01c1, 0xc415, 0x01c1, 0xc415, 0x21, 0 - .dw 0x01c3, 0xc415, 0x01cf, 0xc415, 0x21, 0 - .dw 0x01d1, 0xc415, 0x01d1, 0xc415, 0x21, 0 - .dw 0x01d3, 0xc415, 0x01ff, 0xc415, 0x21, 0 - .dw 0x0201, 0xc415, 0x0201, 0xc415, 0x21, 0 - .dw 0x0203, 0xc415, 0x020f, 0xc415, 0x21, 0 - .dw 0x0211, 0xc415, 0x0211, 0xc415, 0x21, 0 - .dw 0x0213, 0xc415, 0x023f, 0xc415, 0x21, 0 - .dw 0x0240, 0xc415, 0x0240, 0xc415, 0x22, 0 - .dw 0x0241, 0xc415, 0x0241, 0xc415, 0x21, 0 - .dw 0x0242, 0xc415, 0x0242, 0xc415, 0x22, 0 - .dw 0x0243, 0xc415, 0x024f, 0xc415, 0x21, 0 - .dw 0x0250, 0xc415, 0x0250, 0xc415, 0x22, 0 - .dw 0x0251, 0xc415, 0x0251, 0xc415, 0x21, 0 - .dw 0x0252, 0xc415, 0x0252, 0xc415, 0x22, 0 - .dw 0x0253, 0xc415, 0x027f, 0xc415, 0x21, 0 - .dw 0x0281, 0xc415, 0x0281, 0xc415, 0x21, 0 - .dw 0x0283, 0xc415, 0x028f, 0xc415, 0x21, 0 - .dw 0x0291, 0xc415, 0x0291, 0xc415, 0x21, 0 - .dw 0x0293, 0xc415, 0x02bf, 0xc415, 0x21, 0 - .dw 0x02c1, 0xc415, 0x02c1, 0xc415, 0x21, 0 - .dw 0x02c3, 0xc415, 0x02cf, 0xc415, 0x21, 0 - .dw 0x02d1, 0xc415, 0x02d1, 0xc415, 0x21, 0 - .dw 0x02d3, 0xc415, 0x02ff, 0xc415, 0x21, 0 - .dw 0x0301, 0xc415, 0x0301, 0xc415, 0x21, 0 - .dw 0x0303, 0xc415, 0x030f, 0xc415, 0x21, 0 - .dw 0x0311, 0xc415, 0x0311, 0xc415, 0x21, 0 - .dw 0x0313, 0xc415, 0x033f, 0xc415, 0x21, 0 - .dw 0x0341, 0xc415, 0x0341, 0xc415, 0x21, 0 - .dw 0x0343, 0xc415, 0x034f, 0xc415, 0x21, 0 - .dw 0x0351, 0xc415, 0x0351, 0xc415, 0x21, 0 - .dw 0x0353, 0xc415, 0x037f, 0xc415, 0x21, 0 - .dw 0x0381, 0xc415, 0x0381, 0xc415, 0x21, 0 - .dw 0x0383, 0xc415, 0x038f, 0xc415, 0x21, 0 - .dw 0x0391, 0xc415, 0x0391, 0xc415, 0x21, 0 - .dw 0x0393, 0xc415, 0x03bf, 0xc415, 0x21, 0 - .dw 0x03c1, 0xc415, 0x03c1, 0xc415, 0x21, 0 - .dw 0x03c3, 0xc415, 0x03cf, 0xc415, 0x21, 0 - .dw 0x03d1, 0xc415, 0x03d1, 0xc415, 0x21, 0 - .dw 0x03d3, 0xc415, 0x03ff, 0xc415, 0x21, 0 - .dw 0x0401, 0xc415, 0x0401, 0xc415, 0x21, 0 - .dw 0x0403, 0xc415, 0x040f, 0xc415, 0x21, 0 - .dw 0x0411, 0xc415, 0x0411, 0xc415, 0x21, 0 - .dw 0x0413, 0xc415, 0x043f, 0xc415, 0x21, 0 - .dw 0x0441, 0xc415, 0x0441, 0xc415, 0x21, 0 - .dw 0x0443, 0xc415, 0x044f, 0xc415, 0x21, 0 - .dw 0x0451, 0xc415, 0x0451, 0xc415, 0x21, 0 - .dw 0x0453, 0xc415, 0x047f, 0xc415, 0x21, 0 - .dw 0x0480, 0xc415, 0x0480, 0xc415, 0x22, 0 - .dw 0x0481, 0xc415, 0x0481, 0xc415, 0x21, 0 - .dw 0x0482, 0xc415, 0x0482, 0xc415, 0x22, 0 - .dw 0x0483, 0xc415, 0x048f, 0xc415, 0x21, 0 - .dw 0x0490, 0xc415, 0x0490, 0xc415, 0x22, 0 - .dw 0x0491, 0xc415, 0x0491, 0xc415, 0x21, 0 - .dw 0x0492, 0xc415, 0x0492, 0xc415, 0x22, 0 - .dw 0x0493, 0xc415, 0x04bf, 0xc415, 0x21, 0 - .dw 0x04c1, 0xc415, 0x04c1, 0xc415, 0x21, 0 - .dw 0x04c3, 0xc415, 0x04cf, 0xc415, 0x21, 0 - .dw 0x04d1, 0xc415, 0x04d1, 0xc415, 0x21, 0 - .dw 0x04d3, 0xc415, 0x04ff, 0xc415, 0x21, 0 - .dw 0x0501, 0xc415, 0x0501, 0xc415, 0x21, 0 - .dw 0x0503, 0xc415, 0x050f, 0xc415, 0x21, 0 - .dw 0x0511, 0xc415, 0x0511, 0xc415, 0x21, 0 - .dw 0x0513, 0xc415, 0x053f, 0xc415, 0x21, 0 - .dw 0x0541, 0xc415, 0x0541, 0xc415, 0x21, 0 - .dw 0x0543, 0xc415, 0x054f, 0xc415, 0x21, 0 - .dw 0x0551, 0xc415, 0x0551, 0xc415, 0x21, 0 - .dw 0x0553, 0xc415, 0x057f, 0xc415, 0x21, 0 - .dw 0x0581, 0xc415, 0x0581, 0xc415, 0x21, 0 - .dw 0x0583, 0xc415, 0x058f, 0xc415, 0x21, 0 - .dw 0x0591, 0xc415, 0x0591, 0xc415, 0x21, 0 - .dw 0x0593, 0xc415, 0x05bf, 0xc415, 0x21, 0 - .dw 0x05c1, 0xc415, 0x05c1, 0xc415, 0x21, 0 - .dw 0x05c3, 0xc415, 0x05cf, 0xc415, 0x21, 0 - .dw 0x05d1, 0xc415, 0x05d1, 0xc415, 0x21, 0 - .dw 0x05d3, 0xc415, 0x05ff, 0xc415, 0x21, 0 - .dw 0x0601, 0xc415, 0x0601, 0xc415, 0x21, 0 - .dw 0x0603, 0xc415, 0x060f, 0xc415, 0x21, 0 - .dw 0x0611, 0xc415, 0x0611, 0xc415, 0x21, 0 - .dw 0x0613, 0xc415, 0x063f, 0xc415, 0x21, 0 - .dw 0x0641, 0xc415, 0x0641, 0xc415, 0x21, 0 - .dw 0x0643, 0xc415, 0x064f, 0xc415, 0x21, 0 - .dw 0x0651, 0xc415, 0x0651, 0xc415, 0x21, 0 - .dw 0x0653, 0xc415, 0x067f, 0xc415, 0x21, 0 - .dw 0x0681, 0xc415, 0x0681, 0xc415, 0x21, 0 - .dw 0x0683, 0xc415, 0x068f, 0xc415, 0x21, 0 - .dw 0x0691, 0xc415, 0x0691, 0xc415, 0x21, 0 - .dw 0x0693, 0xc415, 0x06bf, 0xc415, 0x21, 0 - .dw 0x06c0, 0xc415, 0x06c0, 0xc415, 0x22, 0 - .dw 0x06c1, 0xc415, 0x06c1, 0xc415, 0x21, 0 - .dw 0x06c2, 0xc415, 0x06c2, 0xc415, 0x22, 0 - .dw 0x06c3, 0xc415, 0x06cf, 0xc415, 0x21, 0 - .dw 0x06d0, 0xc415, 0x06d0, 0xc415, 0x22, 0 - .dw 0x06d1, 0xc415, 0x06d1, 0xc415, 0x21, 0 - .dw 0x06d2, 0xc415, 0x06d2, 0xc415, 0x22, 0 - .dw 0x06d3, 0xc415, 0x06ff, 0xc415, 0x21, 0 - .dw 0x0701, 0xc415, 0x0701, 0xc415, 0x21, 0 - .dw 0x0703, 0xc415, 0x070f, 0xc415, 0x21, 0 - .dw 0x0711, 0xc415, 0x0711, 0xc415, 0x21, 0 - .dw 0x0713, 0xc415, 0x073f, 0xc415, 0x21, 0 - .dw 0x0741, 0xc415, 0x0741, 0xc415, 0x21, 0 - .dw 0x0743, 0xc415, 0x074f, 0xc415, 0x21, 0 - .dw 0x0751, 0xc415, 0x0751, 0xc415, 0x21, 0 - .dw 0x0753, 0xc415, 0x077f, 0xc415, 0x21, 0 - .dw 0x0781, 0xc415, 0x0781, 0xc415, 0x21, 0 - .dw 0x0783, 0xc415, 0x078f, 0xc415, 0x21, 0 - .dw 0x0791, 0xc415, 0x0791, 0xc415, 0x21, 0 - .dw 0x0793, 0xc415, 0x07bf, 0xc415, 0x21, 0 - .dw 0x07c1, 0xc415, 0x07c1, 0xc415, 0x21, 0 - .dw 0x07c3, 0xc415, 0x07cf, 0xc415, 0x21, 0 - .dw 0x07d1, 0xc415, 0x07d1, 0xc415, 0x21, 0 - .dw 0x07d3, 0xc415, 0x07ff, 0xc415, 0x21, 0 - .dw 0x0801, 0xc415, 0x0801, 0xc415, 0x21, 0 - .dw 0x0803, 0xc415, 0x080f, 0xc415, 0x21, 0 - .dw 0x0811, 0xc415, 0x0811, 0xc415, 0x21, 0 - .dw 0x0813, 0xc415, 0x083f, 0xc415, 0x21, 0 - .dw 0x0841, 0xc415, 0x0841, 0xc415, 0x21, 0 - .dw 0x0843, 0xc415, 0x084f, 0xc415, 0x21, 0 - .dw 0x0851, 0xc415, 0x0851, 0xc415, 0x21, 0 - .dw 0x0853, 0xc415, 0x087f, 0xc415, 0x21, 0 - .dw 0x0881, 0xc415, 0x0881, 0xc415, 0x21, 0 - .dw 0x0883, 0xc415, 0x088f, 0xc415, 0x21, 0 - .dw 0x0891, 0xc415, 0x0891, 0xc415, 0x21, 0 - .dw 0x0893, 0xc415, 0x08bf, 0xc415, 0x21, 0 - .dw 0x08c1, 0xc415, 0x08c1, 0xc415, 0x21, 0 - .dw 0x08c3, 0xc415, 0x08cf, 0xc415, 0x21, 0 - .dw 0x08d1, 0xc415, 0x08d1, 0xc415, 0x21, 0 - .dw 0x08d3, 0xc415, 0x08ff, 0xc415, 0x21, 0 - .dw 0x0900, 0xc415, 0x0900, 0xc415, 0x22, 0 - .dw 0x0901, 0xc415, 0x0901, 0xc415, 0x21, 0 - .dw 0x0902, 0xc415, 0x0902, 0xc415, 0x22, 0 - .dw 0x0903, 0xc415, 0x090f, 0xc415, 0x21, 0 - .dw 0x0910, 0xc415, 0x0910, 0xc415, 0x22, 0 - .dw 0x0911, 0xc415, 0x0911, 0xc415, 0x21, 0 - .dw 0x0912, 0xc415, 0x0912, 0xc415, 0x22, 0 - .dw 0x0913, 0xc415, 0x093f, 0xc415, 0x21, 0 - .dw 0x0941, 0xc415, 0x0941, 0xc415, 0x21, 0 - .dw 0x0943, 0xc415, 0x094f, 0xc415, 0x21, 0 - .dw 0x0951, 0xc415, 0x0951, 0xc415, 0x21, 0 - .dw 0x0953, 0xc415, 0x097f, 0xc415, 0x21, 0 - .dw 0x0981, 0xc415, 0x0981, 0xc415, 0x21, 0 - .dw 0x0983, 0xc415, 0x098f, 0xc415, 0x21, 0 - .dw 0x0991, 0xc415, 0x0991, 0xc415, 0x21, 0 - .dw 0x0993, 0xc415, 0x09bf, 0xc415, 0x21, 0 - .dw 0x09c1, 0xc415, 0x09c1, 0xc415, 0x21, 0 - .dw 0x09c3, 0xc415, 0x09cf, 0xc415, 0x21, 0 - .dw 0x09d1, 0xc415, 0x09d1, 0xc415, 0x21, 0 - .dw 0x09d3, 0xc415, 0x09ff, 0xc415, 0x21, 0 - .dw 0x0a01, 0xc415, 0x0a01, 0xc415, 0x21, 0 - .dw 0x0a03, 0xc415, 0x0a0f, 0xc415, 0x21, 0 - .dw 0x0a11, 0xc415, 0x0a11, 0xc415, 0x21, 0 - .dw 0x0a13, 0xc415, 0x0a3f, 0xc415, 0x21, 0 - .dw 0x0a41, 0xc415, 0x0a41, 0xc415, 0x21, 0 - .dw 0x0a43, 0xc415, 0x0a4f, 0xc415, 0x21, 0 - .dw 0x0a51, 0xc415, 0x0a51, 0xc415, 0x21, 0 - .dw 0x0a53, 0xc415, 0x0a7f, 0xc415, 0x21, 0 - .dw 0x0a81, 0xc415, 0x0a81, 0xc415, 0x21, 0 - .dw 0x0a83, 0xc415, 0x0a8f, 0xc415, 0x21, 0 - .dw 0x0a91, 0xc415, 0x0a91, 0xc415, 0x21, 0 - .dw 0x0a93, 0xc415, 0x0abf, 0xc415, 0x21, 0 - .dw 0x0ac1, 0xc415, 0x0ac1, 0xc415, 0x21, 0 - .dw 0x0ac3, 0xc415, 0x0acf, 0xc415, 0x21, 0 - .dw 0x0ad1, 0xc415, 0x0ad1, 0xc415, 0x21, 0 - .dw 0x0ad3, 0xc415, 0x0aff, 0xc415, 0x21, 0 - .dw 0x0b01, 0xc415, 0x0b01, 0xc415, 0x21, 0 - .dw 0x0b03, 0xc415, 0x0b0f, 0xc415, 0x21, 0 - .dw 0x0b11, 0xc415, 0x0b11, 0xc415, 0x21, 0 - .dw 0x0b13, 0xc415, 0x0b3f, 0xc415, 0x21, 0 - .dw 0x0b40, 0xc415, 0x0b40, 0xc415, 0x22, 0 - .dw 0x0b41, 0xc415, 0x0b41, 0xc415, 0x21, 0 - .dw 0x0b42, 0xc415, 0x0b42, 0xc415, 0x22, 0 - .dw 0x0b43, 0xc415, 0x0b4f, 0xc415, 0x21, 0 - .dw 0x0b50, 0xc415, 0x0b50, 0xc415, 0x22, 0 - .dw 0x0b51, 0xc415, 0x0b51, 0xc415, 0x21, 0 - .dw 0x0b52, 0xc415, 0x0b52, 0xc415, 0x22, 0 - .dw 0x0b53, 0xc415, 0x0b7f, 0xc415, 0x21, 0 - .dw 0x0b81, 0xc415, 0x0b81, 0xc415, 0x21, 0 - .dw 0x0b83, 0xc415, 0x0b8f, 0xc415, 0x21, 0 - .dw 0x0b91, 0xc415, 0x0b91, 0xc415, 0x21, 0 - .dw 0x0b93, 0xc415, 0x0bbf, 0xc415, 0x21, 0 - .dw 0x0bc1, 0xc415, 0x0bc1, 0xc415, 0x21, 0 - .dw 0x0bc3, 0xc415, 0x0bcf, 0xc415, 0x21, 0 - .dw 0x0bd1, 0xc415, 0x0bd1, 0xc415, 0x21, 0 - .dw 0x0bd3, 0xc415, 0x0bff, 0xc415, 0x21, 0 - .dw 0x0c01, 0xc415, 0x0c01, 0xc415, 0x21, 0 - .dw 0x0c03, 0xc415, 0x0c0f, 0xc415, 0x21, 0 - .dw 0x0c11, 0xc415, 0x0c11, 0xc415, 0x21, 0 - .dw 0x0c13, 0xc415, 0x0c3f, 0xc415, 0x21, 0 - .dw 0x0c41, 0xc415, 0x0c41, 0xc415, 0x21, 0 - .dw 0x0c43, 0xc415, 0x0c4f, 0xc415, 0x21, 0 - .dw 0x0c51, 0xc415, 0x0c51, 0xc415, 0x21, 0 - .dw 0x0c53, 0xc415, 0x0c7f, 0xc415, 0x21, 0 - .dw 0x0c81, 0xc415, 0x0c81, 0xc415, 0x21, 0 - .dw 0x0c83, 0xc415, 0x0c8f, 0xc415, 0x21, 0 - .dw 0x0c91, 0xc415, 0x0c91, 0xc415, 0x21, 0 - .dw 0x0c93, 0xc415, 0x0cbf, 0xc415, 0x21, 0 - .dw 0x0cc1, 0xc415, 0x0cc1, 0xc415, 0x21, 0 - .dw 0x0cc3, 0xc415, 0x0ccf, 0xc415, 0x21, 0 - .dw 0x0cd1, 0xc415, 0x0cd1, 0xc415, 0x21, 0 - .dw 0x0cd3, 0xc415, 0x0cff, 0xc415, 0x21, 0 - .dw 0x0d01, 0xc415, 0x0d01, 0xc415, 0x21, 0 - .dw 0x0d03, 0xc415, 0x0d0f, 0xc415, 0x21, 0 - .dw 0x0d11, 0xc415, 0x0d11, 0xc415, 0x21, 0 - .dw 0x0d13, 0xc415, 0x0d3f, 0xc415, 0x21, 0 - .dw 0x0d41, 0xc415, 0x0d41, 0xc415, 0x21, 0 - .dw 0x0d43, 0xc415, 0x0d4f, 0xc415, 0x21, 0 - .dw 0x0d51, 0xc415, 0x0d51, 0xc415, 0x21, 0 - .dw 0x0d53, 0xc415, 0x0d7f, 0xc415, 0x21, 0 - .dw 0x0d80, 0xc415, 0x0d80, 0xc415, 0x22, 0 - .dw 0x0d81, 0xc415, 0x0d81, 0xc415, 0x21, 0 - .dw 0x0d82, 0xc415, 0x0d82, 0xc415, 0x22, 0 - .dw 0x0d83, 0xc415, 0x0d8f, 0xc415, 0x21, 0 - .dw 0x0d90, 0xc415, 0x0d90, 0xc415, 0x22, 0 - .dw 0x0d91, 0xc415, 0x0d91, 0xc415, 0x21, 0 - .dw 0x0d92, 0xc415, 0x0d92, 0xc415, 0x22, 0 - .dw 0x0d93, 0xc415, 0x0dbf, 0xc415, 0x21, 0 - .dw 0x0dc1, 0xc415, 0x0dc1, 0xc415, 0x21, 0 - .dw 0x0dc3, 0xc415, 0x0dcf, 0xc415, 0x21, 0 - .dw 0x0dd1, 0xc415, 0x0dd1, 0xc415, 0x21, 0 - .dw 0x0dd3, 0xc415, 0x0dff, 0xc415, 0x21, 0 - .dw 0x0e01, 0xc415, 0x0e01, 0xc415, 0x21, 0 - .dw 0x0e03, 0xc415, 0x0e0f, 0xc415, 0x21, 0 - .dw 0x0e11, 0xc415, 0x0e11, 0xc415, 0x21, 0 - .dw 0x0e13, 0xc415, 0x0e3f, 0xc415, 0x21, 0 - .dw 0x0e41, 0xc415, 0x0e41, 0xc415, 0x21, 0 - .dw 0x0e43, 0xc415, 0x0e4f, 0xc415, 0x21, 0 - .dw 0x0e51, 0xc415, 0x0e51, 0xc415, 0x21, 0 - .dw 0x0e53, 0xc415, 0x0e7f, 0xc415, 0x21, 0 - .dw 0x0e81, 0xc415, 0x0e81, 0xc415, 0x21, 0 - .dw 0x0e83, 0xc415, 0x0e8f, 0xc415, 0x21, 0 - .dw 0x0e91, 0xc415, 0x0e91, 0xc415, 0x21, 0 - .dw 0x0e93, 0xc415, 0x0ebf, 0xc415, 0x21, 0 - .dw 0x0ec1, 0xc415, 0x0ec1, 0xc415, 0x21, 0 - .dw 0x0ec3, 0xc415, 0x0ecf, 0xc415, 0x21, 0 - .dw 0x0ed1, 0xc415, 0x0ed1, 0xc415, 0x21, 0 - .dw 0x0ed3, 0xc415, 0x0eff, 0xc415, 0x21, 0 - .dw 0x0f01, 0xc415, 0x0f01, 0xc415, 0x21, 0 - .dw 0x0f03, 0xc415, 0x0f0f, 0xc415, 0x21, 0 - .dw 0x0f11, 0xc415, 0x0f11, 0xc415, 0x21, 0 - .dw 0x0f13, 0xc415, 0x0f3f, 0xc415, 0x21, 0 - .dw 0x0f41, 0xc415, 0x0f41, 0xc415, 0x21, 0 - .dw 0x0f43, 0xc415, 0x0f4f, 0xc415, 0x21, 0 - .dw 0x0f51, 0xc415, 0x0f51, 0xc415, 0x21, 0 - .dw 0x0f53, 0xc415, 0x0f7f, 0xc415, 0x21, 0 - .dw 0x0f81, 0xc415, 0x0f81, 0xc415, 0x21, 0 - .dw 0x0f83, 0xc415, 0x0f8f, 0xc415, 0x21, 0 - .dw 0x0f91, 0xc415, 0x0f91, 0xc415, 0x21, 0 - .dw 0x0f93, 0xc415, 0x0fbf, 0xc415, 0x21, 0 - .dw 0x0fc0, 0xc415, 0x0fc0, 0xc415, 0x22, 0 - .dw 0x0fc1, 0xc415, 0x0fc1, 0xc415, 0x21, 0 - .dw 0x0fc2, 0xc415, 0x0fc2, 0xc415, 0x22, 0 - .dw 0x0fc3, 0xc415, 0x0fcf, 0xc415, 0x21, 0 - .dw 0x0fd0, 0xc415, 0x0fd0, 0xc415, 0x22, 0 - .dw 0x0fd1, 0xc415, 0x0fd1, 0xc415, 0x21, 0 - .dw 0x0fd2, 0xc415, 0x0fd2, 0xc415, 0x22, 0 - .dw 0x0fd3, 0xc415, 0x1fff, 0xc415, 0x21, 0 - .dw 0x2000, 0xc415, 0x2000, 0xc415, 0x22, 0 - .dw 0x2001, 0xc415, 0x2001, 0xc415, 0x21, 0 - .dw 0x2002, 0xc415, 0x2002, 0xc415, 0x22, 0 - .dw 0x2003, 0xc415, 0x200f, 0xc415, 0x21, 0 - .dw 0x2010, 0xc415, 0x2010, 0xc415, 0x22, 0 - .dw 0x2011, 0xc415, 0x2011, 0xc415, 0x21, 0 - .dw 0x2012, 0xc415, 0x2012, 0xc415, 0x22, 0 - .dw 0x2013, 0xc415, 0x203f, 0xc415, 0x21, 0 - .dw 0x2041, 0xc415, 0x2041, 0xc415, 0x21, 0 - .dw 0x2043, 0xc415, 0x204f, 0xc415, 0x21, 0 - .dw 0x2051, 0xc415, 0x2051, 0xc415, 0x21, 0 - .dw 0x2053, 0xc415, 0x207f, 0xc415, 0x21, 0 - .dw 0x2081, 0xc415, 0x2081, 0xc415, 0x21, 0 - .dw 0x2083, 0xc415, 0x208f, 0xc415, 0x21, 0 - .dw 0x2091, 0xc415, 0x2091, 0xc415, 0x21, 0 - .dw 0x2093, 0xc415, 0x20bf, 0xc415, 0x21, 0 - .dw 0x20c1, 0xc415, 0x20c1, 0xc415, 0x21, 0 - .dw 0x20c3, 0xc415, 0x20cf, 0xc415, 0x21, 0 - .dw 0x20d1, 0xc415, 0x20d1, 0xc415, 0x21, 0 - .dw 0x20d3, 0xc415, 0x20ff, 0xc415, 0x21, 0 - .dw 0x2101, 0xc415, 0x2101, 0xc415, 0x21, 0 - .dw 0x2103, 0xc415, 0x210f, 0xc415, 0x21, 0 - .dw 0x2111, 0xc415, 0x2111, 0xc415, 0x21, 0 - .dw 0x2113, 0xc415, 0x213f, 0xc415, 0x21, 0 - .dw 0x2141, 0xc415, 0x2141, 0xc415, 0x21, 0 - .dw 0x2143, 0xc415, 0x214f, 0xc415, 0x21, 0 - .dw 0x2151, 0xc415, 0x2151, 0xc415, 0x21, 0 - .dw 0x2153, 0xc415, 0x217f, 0xc415, 0x21, 0 - .dw 0x2181, 0xc415, 0x2181, 0xc415, 0x21, 0 - .dw 0x2183, 0xc415, 0x218f, 0xc415, 0x21, 0 - .dw 0x2191, 0xc415, 0x2191, 0xc415, 0x21, 0 - .dw 0x2193, 0xc415, 0x21bf, 0xc415, 0x21, 0 - .dw 0x21c1, 0xc415, 0x21c1, 0xc415, 0x21, 0 - .dw 0x21c3, 0xc415, 0x21cf, 0xc415, 0x21, 0 - .dw 0x21d1, 0xc415, 0x21d1, 0xc415, 0x21, 0 - .dw 0x21d3, 0xc415, 0x21ff, 0xc415, 0x21, 0 - .dw 0x2201, 0xc415, 0x2201, 0xc415, 0x21, 0 - .dw 0x2203, 0xc415, 0x220f, 0xc415, 0x21, 0 - .dw 0x2211, 0xc415, 0x2211, 0xc415, 0x21, 0 - .dw 0x2213, 0xc415, 0x223f, 0xc415, 0x21, 0 - .dw 0x2240, 0xc415, 0x2240, 0xc415, 0x22, 0 - .dw 0x2241, 0xc415, 0x2241, 0xc415, 0x21, 0 - .dw 0x2242, 0xc415, 0x2242, 0xc415, 0x22, 0 - .dw 0x2243, 0xc415, 0x224f, 0xc415, 0x21, 0 - .dw 0x2250, 0xc415, 0x2250, 0xc415, 0x22, 0 - .dw 0x2251, 0xc415, 0x2251, 0xc415, 0x21, 0 - .dw 0x2252, 0xc415, 0x2252, 0xc415, 0x22, 0 - .dw 0x2253, 0xc415, 0x227f, 0xc415, 0x21, 0 - .dw 0x2281, 0xc415, 0x2281, 0xc415, 0x21, 0 - .dw 0x2283, 0xc415, 0x228f, 0xc415, 0x21, 0 - .dw 0x2291, 0xc415, 0x2291, 0xc415, 0x21, 0 - .dw 0x2293, 0xc415, 0x22bf, 0xc415, 0x21, 0 - .dw 0x22c1, 0xc415, 0x22c1, 0xc415, 0x21, 0 - .dw 0x22c3, 0xc415, 0x22cf, 0xc415, 0x21, 0 - .dw 0x22d1, 0xc415, 0x22d1, 0xc415, 0x21, 0 - .dw 0x22d3, 0xc415, 0x22ff, 0xc415, 0x21, 0 - .dw 0x2301, 0xc415, 0x2301, 0xc415, 0x21, 0 - .dw 0x2303, 0xc415, 0x230f, 0xc415, 0x21, 0 - .dw 0x2311, 0xc415, 0x2311, 0xc415, 0x21, 0 - .dw 0x2313, 0xc415, 0x233f, 0xc415, 0x21, 0 - .dw 0x2341, 0xc415, 0x2341, 0xc415, 0x21, 0 - .dw 0x2343, 0xc415, 0x234f, 0xc415, 0x21, 0 - .dw 0x2351, 0xc415, 0x2351, 0xc415, 0x21, 0 - .dw 0x2353, 0xc415, 0x237f, 0xc415, 0x21, 0 - .dw 0x2381, 0xc415, 0x2381, 0xc415, 0x21, 0 - .dw 0x2383, 0xc415, 0x238f, 0xc415, 0x21, 0 - .dw 0x2391, 0xc415, 0x2391, 0xc415, 0x21, 0 - .dw 0x2393, 0xc415, 0x23bf, 0xc415, 0x21, 0 - .dw 0x23c1, 0xc415, 0x23c1, 0xc415, 0x21, 0 - .dw 0x23c3, 0xc415, 0x23cf, 0xc415, 0x21, 0 - .dw 0x23d1, 0xc415, 0x23d1, 0xc415, 0x21, 0 - .dw 0x23d3, 0xc415, 0x23ff, 0xc415, 0x21, 0 - .dw 0x2401, 0xc415, 0x2401, 0xc415, 0x21, 0 - .dw 0x2403, 0xc415, 0x240f, 0xc415, 0x21, 0 - .dw 0x2411, 0xc415, 0x2411, 0xc415, 0x21, 0 - .dw 0x2413, 0xc415, 0x243f, 0xc415, 0x21, 0 - .dw 0x2441, 0xc415, 0x2441, 0xc415, 0x21, 0 - .dw 0x2443, 0xc415, 0x244f, 0xc415, 0x21, 0 - .dw 0x2451, 0xc415, 0x2451, 0xc415, 0x21, 0 - .dw 0x2453, 0xc415, 0x247f, 0xc415, 0x21, 0 - .dw 0x2480, 0xc415, 0x2480, 0xc415, 0x22, 0 - .dw 0x2481, 0xc415, 0x2481, 0xc415, 0x21, 0 - .dw 0x2482, 0xc415, 0x2482, 0xc415, 0x22, 0 - .dw 0x2483, 0xc415, 0x248f, 0xc415, 0x21, 0 - .dw 0x2490, 0xc415, 0x2490, 0xc415, 0x22, 0 - .dw 0x2491, 0xc415, 0x2491, 0xc415, 0x21, 0 - .dw 0x2492, 0xc415, 0x2492, 0xc415, 0x22, 0 - .dw 0x2493, 0xc415, 0x24bf, 0xc415, 0x21, 0 - .dw 0x24c1, 0xc415, 0x24c1, 0xc415, 0x21, 0 - .dw 0x24c3, 0xc415, 0x24cf, 0xc415, 0x21, 0 - .dw 0x24d1, 0xc415, 0x24d1, 0xc415, 0x21, 0 - .dw 0x24d3, 0xc415, 0x24ff, 0xc415, 0x21, 0 - .dw 0x2501, 0xc415, 0x2501, 0xc415, 0x21, 0 - .dw 0x2503, 0xc415, 0x250f, 0xc415, 0x21, 0 - .dw 0x2511, 0xc415, 0x2511, 0xc415, 0x21, 0 - .dw 0x2513, 0xc415, 0x253f, 0xc415, 0x21, 0 - .dw 0x2541, 0xc415, 0x2541, 0xc415, 0x21, 0 - .dw 0x2543, 0xc415, 0x254f, 0xc415, 0x21, 0 - .dw 0x2551, 0xc415, 0x2551, 0xc415, 0x21, 0 - .dw 0x2553, 0xc415, 0x257f, 0xc415, 0x21, 0 - .dw 0x2581, 0xc415, 0x2581, 0xc415, 0x21, 0 - .dw 0x2583, 0xc415, 0x258f, 0xc415, 0x21, 0 - .dw 0x2591, 0xc415, 0x2591, 0xc415, 0x21, 0 - .dw 0x2593, 0xc415, 0x25bf, 0xc415, 0x21, 0 - .dw 0x25c1, 0xc415, 0x25c1, 0xc415, 0x21, 0 - .dw 0x25c3, 0xc415, 0x25cf, 0xc415, 0x21, 0 - .dw 0x25d1, 0xc415, 0x25d1, 0xc415, 0x21, 0 - .dw 0x25d3, 0xc415, 0x25ff, 0xc415, 0x21, 0 - .dw 0x2601, 0xc415, 0x2601, 0xc415, 0x21, 0 - .dw 0x2603, 0xc415, 0x260f, 0xc415, 0x21, 0 - .dw 0x2611, 0xc415, 0x2611, 0xc415, 0x21, 0 - .dw 0x2613, 0xc415, 0x263f, 0xc415, 0x21, 0 - .dw 0x2641, 0xc415, 0x2641, 0xc415, 0x21, 0 - .dw 0x2643, 0xc415, 0x264f, 0xc415, 0x21, 0 - .dw 0x2651, 0xc415, 0x2651, 0xc415, 0x21, 0 - .dw 0x2653, 0xc415, 0x267f, 0xc415, 0x21, 0 - .dw 0x2681, 0xc415, 0x2681, 0xc415, 0x21, 0 - .dw 0x2683, 0xc415, 0x268f, 0xc415, 0x21, 0 - .dw 0x2691, 0xc415, 0x2691, 0xc415, 0x21, 0 - .dw 0x2693, 0xc415, 0x26bf, 0xc415, 0x21, 0 - .dw 0x26c0, 0xc415, 0x26c0, 0xc415, 0x22, 0 - .dw 0x26c1, 0xc415, 0x26c1, 0xc415, 0x21, 0 - .dw 0x26c2, 0xc415, 0x26c2, 0xc415, 0x22, 0 - .dw 0x26c3, 0xc415, 0x26cf, 0xc415, 0x21, 0 - .dw 0x26d0, 0xc415, 0x26d0, 0xc415, 0x22, 0 - .dw 0x26d1, 0xc415, 0x26d1, 0xc415, 0x21, 0 - .dw 0x26d2, 0xc415, 0x26d2, 0xc415, 0x22, 0 - .dw 0x26d3, 0xc415, 0x26ff, 0xc415, 0x21, 0 - .dw 0x2701, 0xc415, 0x2701, 0xc415, 0x21, 0 - .dw 0x2703, 0xc415, 0x270f, 0xc415, 0x21, 0 - .dw 0x2711, 0xc415, 0x2711, 0xc415, 0x21, 0 - .dw 0x2713, 0xc415, 0x273f, 0xc415, 0x21, 0 - .dw 0x2741, 0xc415, 0x2741, 0xc415, 0x21, 0 - .dw 0x2743, 0xc415, 0x274f, 0xc415, 0x21, 0 - .dw 0x2751, 0xc415, 0x2751, 0xc415, 0x21, 0 - .dw 0x2753, 0xc415, 0x277f, 0xc415, 0x21, 0 - .dw 0x2781, 0xc415, 0x2781, 0xc415, 0x21, 0 - .dw 0x2783, 0xc415, 0x278f, 0xc415, 0x21, 0 - .dw 0x2791, 0xc415, 0x2791, 0xc415, 0x21, 0 - .dw 0x2793, 0xc415, 0x27bf, 0xc415, 0x21, 0 - .dw 0x27c1, 0xc415, 0x27c1, 0xc415, 0x21, 0 - .dw 0x27c3, 0xc415, 0x27cf, 0xc415, 0x21, 0 - .dw 0x27d1, 0xc415, 0x27d1, 0xc415, 0x21, 0 - .dw 0x27d3, 0xc415, 0x27ff, 0xc415, 0x21, 0 - .dw 0x2801, 0xc415, 0x2801, 0xc415, 0x21, 0 - .dw 0x2803, 0xc415, 0x280f, 0xc415, 0x21, 0 - .dw 0x2811, 0xc415, 0x2811, 0xc415, 0x21, 0 - .dw 0x2813, 0xc415, 0x283f, 0xc415, 0x21, 0 - .dw 0x2841, 0xc415, 0x2841, 0xc415, 0x21, 0 - .dw 0x2843, 0xc415, 0x284f, 0xc415, 0x21, 0 - .dw 0x2851, 0xc415, 0x2851, 0xc415, 0x21, 0 - .dw 0x2853, 0xc415, 0x287f, 0xc415, 0x21, 0 - .dw 0x2881, 0xc415, 0x2881, 0xc415, 0x21, 0 - .dw 0x2883, 0xc415, 0x288f, 0xc415, 0x21, 0 - .dw 0x2891, 0xc415, 0x2891, 0xc415, 0x21, 0 - .dw 0x2893, 0xc415, 0x28bf, 0xc415, 0x21, 0 - .dw 0x28c1, 0xc415, 0x28c1, 0xc415, 0x21, 0 - .dw 0x28c3, 0xc415, 0x28cf, 0xc415, 0x21, 0 - .dw 0x28d1, 0xc415, 0x28d1, 0xc415, 0x21, 0 - .dw 0x28d3, 0xc415, 0x28ff, 0xc415, 0x21, 0 - .dw 0x2900, 0xc415, 0x2900, 0xc415, 0x22, 0 - .dw 0x2901, 0xc415, 0x2901, 0xc415, 0x21, 0 - .dw 0x2902, 0xc415, 0x2902, 0xc415, 0x22, 0 - .dw 0x2903, 0xc415, 0x290f, 0xc415, 0x21, 0 - .dw 0x2910, 0xc415, 0x2910, 0xc415, 0x22, 0 - .dw 0x2911, 0xc415, 0x2911, 0xc415, 0x21, 0 - .dw 0x2912, 0xc415, 0x2912, 0xc415, 0x22, 0 - .dw 0x2913, 0xc415, 0x293f, 0xc415, 0x21, 0 - .dw 0x2941, 0xc415, 0x2941, 0xc415, 0x21, 0 - .dw 0x2943, 0xc415, 0x294f, 0xc415, 0x21, 0 - .dw 0x2951, 0xc415, 0x2951, 0xc415, 0x21, 0 - .dw 0x2953, 0xc415, 0x297f, 0xc415, 0x21, 0 - .dw 0x2981, 0xc415, 0x2981, 0xc415, 0x21, 0 - .dw 0x2983, 0xc415, 0x298f, 0xc415, 0x21, 0 - .dw 0x2991, 0xc415, 0x2991, 0xc415, 0x21, 0 - .dw 0x2993, 0xc415, 0x29bf, 0xc415, 0x21, 0 - .dw 0x29c1, 0xc415, 0x29c1, 0xc415, 0x21, 0 - .dw 0x29c3, 0xc415, 0x29cf, 0xc415, 0x21, 0 - .dw 0x29d1, 0xc415, 0x29d1, 0xc415, 0x21, 0 - .dw 0x29d3, 0xc415, 0x29ff, 0xc415, 0x21, 0 - .dw 0x2a01, 0xc415, 0x2a01, 0xc415, 0x21, 0 - .dw 0x2a03, 0xc415, 0x2a0f, 0xc415, 0x21, 0 - .dw 0x2a11, 0xc415, 0x2a11, 0xc415, 0x21, 0 - .dw 0x2a13, 0xc415, 0x2a3f, 0xc415, 0x21, 0 - .dw 0x2a41, 0xc415, 0x2a41, 0xc415, 0x21, 0 - .dw 0x2a43, 0xc415, 0x2a4f, 0xc415, 0x21, 0 - .dw 0x2a51, 0xc415, 0x2a51, 0xc415, 0x21, 0 - .dw 0x2a53, 0xc415, 0x2a7f, 0xc415, 0x21, 0 - .dw 0x2a81, 0xc415, 0x2a81, 0xc415, 0x21, 0 - .dw 0x2a83, 0xc415, 0x2a8f, 0xc415, 0x21, 0 - .dw 0x2a91, 0xc415, 0x2a91, 0xc415, 0x21, 0 - .dw 0x2a93, 0xc415, 0x2abf, 0xc415, 0x21, 0 - .dw 0x2ac1, 0xc415, 0x2ac1, 0xc415, 0x21, 0 - .dw 0x2ac3, 0xc415, 0x2acf, 0xc415, 0x21, 0 - .dw 0x2ad1, 0xc415, 0x2ad1, 0xc415, 0x21, 0 - .dw 0x2ad3, 0xc415, 0x2aff, 0xc415, 0x21, 0 - .dw 0x2b01, 0xc415, 0x2b01, 0xc415, 0x21, 0 - .dw 0x2b03, 0xc415, 0x2b0f, 0xc415, 0x21, 0 - .dw 0x2b11, 0xc415, 0x2b11, 0xc415, 0x21, 0 - .dw 0x2b13, 0xc415, 0x2b3f, 0xc415, 0x21, 0 - .dw 0x2b40, 0xc415, 0x2b40, 0xc415, 0x22, 0 - .dw 0x2b41, 0xc415, 0x2b41, 0xc415, 0x21, 0 - .dw 0x2b42, 0xc415, 0x2b42, 0xc415, 0x22, 0 - .dw 0x2b43, 0xc415, 0x2b4f, 0xc415, 0x21, 0 - .dw 0x2b50, 0xc415, 0x2b50, 0xc415, 0x22, 0 - .dw 0x2b51, 0xc415, 0x2b51, 0xc415, 0x21, 0 - .dw 0x2b52, 0xc415, 0x2b52, 0xc415, 0x22, 0 - .dw 0x2b53, 0xc415, 0x2b7f, 0xc415, 0x21, 0 - .dw 0x2b81, 0xc415, 0x2b81, 0xc415, 0x21, 0 - .dw 0x2b83, 0xc415, 0x2b8f, 0xc415, 0x21, 0 - .dw 0x2b91, 0xc415, 0x2b91, 0xc415, 0x21, 0 - .dw 0x2b93, 0xc415, 0x2bbf, 0xc415, 0x21, 0 - .dw 0x2bc1, 0xc415, 0x2bc1, 0xc415, 0x21, 0 - .dw 0x2bc3, 0xc415, 0x2bcf, 0xc415, 0x21, 0 - .dw 0x2bd1, 0xc415, 0x2bd1, 0xc415, 0x21, 0 - .dw 0x2bd3, 0xc415, 0x2bff, 0xc415, 0x21, 0 - .dw 0x2c01, 0xc415, 0x2c01, 0xc415, 0x21, 0 - .dw 0x2c03, 0xc415, 0x2c0f, 0xc415, 0x21, 0 - .dw 0x2c11, 0xc415, 0x2c11, 0xc415, 0x21, 0 - .dw 0x2c13, 0xc415, 0x2c3f, 0xc415, 0x21, 0 - .dw 0x2c41, 0xc415, 0x2c41, 0xc415, 0x21, 0 - .dw 0x2c43, 0xc415, 0x2c4f, 0xc415, 0x21, 0 - .dw 0x2c51, 0xc415, 0x2c51, 0xc415, 0x21, 0 - .dw 0x2c53, 0xc415, 0x2c7f, 0xc415, 0x21, 0 - .dw 0x2c81, 0xc415, 0x2c81, 0xc415, 0x21, 0 - .dw 0x2c83, 0xc415, 0x2c8f, 0xc415, 0x21, 0 - .dw 0x2c91, 0xc415, 0x2c91, 0xc415, 0x21, 0 - .dw 0x2c93, 0xc415, 0x2cbf, 0xc415, 0x21, 0 - .dw 0x2cc1, 0xc415, 0x2cc1, 0xc415, 0x21, 0 - .dw 0x2cc3, 0xc415, 0x2ccf, 0xc415, 0x21, 0 - .dw 0x2cd1, 0xc415, 0x2cd1, 0xc415, 0x21, 0 - .dw 0x2cd3, 0xc415, 0x2cff, 0xc415, 0x21, 0 - .dw 0x2d01, 0xc415, 0x2d01, 0xc415, 0x21, 0 - .dw 0x2d03, 0xc415, 0x2d0f, 0xc415, 0x21, 0 - .dw 0x2d11, 0xc415, 0x2d11, 0xc415, 0x21, 0 - .dw 0x2d13, 0xc415, 0x2d3f, 0xc415, 0x21, 0 - .dw 0x2d41, 0xc415, 0x2d41, 0xc415, 0x21, 0 - .dw 0x2d43, 0xc415, 0x2d4f, 0xc415, 0x21, 0 - .dw 0x2d51, 0xc415, 0x2d51, 0xc415, 0x21, 0 - .dw 0x2d53, 0xc415, 0x2d7f, 0xc415, 0x21, 0 - .dw 0x2d80, 0xc415, 0x2d80, 0xc415, 0x22, 0 - .dw 0x2d81, 0xc415, 0x2d81, 0xc415, 0x21, 0 - .dw 0x2d82, 0xc415, 0x2d82, 0xc415, 0x22, 0 - .dw 0x2d83, 0xc415, 0x2d8f, 0xc415, 0x21, 0 - .dw 0x2d90, 0xc415, 0x2d90, 0xc415, 0x22, 0 - .dw 0x2d91, 0xc415, 0x2d91, 0xc415, 0x21, 0 - .dw 0x2d92, 0xc415, 0x2d92, 0xc415, 0x22, 0 - .dw 0x2d93, 0xc415, 0x2dbf, 0xc415, 0x21, 0 - .dw 0x2dc1, 0xc415, 0x2dc1, 0xc415, 0x21, 0 - .dw 0x2dc3, 0xc415, 0x2dcf, 0xc415, 0x21, 0 - .dw 0x2dd1, 0xc415, 0x2dd1, 0xc415, 0x21, 0 - .dw 0x2dd3, 0xc415, 0x2dff, 0xc415, 0x21, 0 - .dw 0x2e01, 0xc415, 0x2e01, 0xc415, 0x21, 0 - .dw 0x2e03, 0xc415, 0x2e0f, 0xc415, 0x21, 0 - .dw 0x2e11, 0xc415, 0x2e11, 0xc415, 0x21, 0 - .dw 0x2e13, 0xc415, 0x2e3f, 0xc415, 0x21, 0 - .dw 0x2e41, 0xc415, 0x2e41, 0xc415, 0x21, 0 - .dw 0x2e43, 0xc415, 0x2e4f, 0xc415, 0x21, 0 - .dw 0x2e51, 0xc415, 0x2e51, 0xc415, 0x21, 0 - .dw 0x2e53, 0xc415, 0x2e7f, 0xc415, 0x21, 0 - .dw 0x2e81, 0xc415, 0x2e81, 0xc415, 0x21, 0 - .dw 0x2e83, 0xc415, 0x2e8f, 0xc415, 0x21, 0 - .dw 0x2e91, 0xc415, 0x2e91, 0xc415, 0x21, 0 - .dw 0x2e93, 0xc415, 0x2ebf, 0xc415, 0x21, 0 - .dw 0x2ec1, 0xc415, 0x2ec1, 0xc415, 0x21, 0 - .dw 0x2ec3, 0xc415, 0x2ecf, 0xc415, 0x21, 0 - .dw 0x2ed1, 0xc415, 0x2ed1, 0xc415, 0x21, 0 - .dw 0x2ed3, 0xc415, 0x2eff, 0xc415, 0x21, 0 - .dw 0x2f01, 0xc415, 0x2f01, 0xc415, 0x21, 0 - .dw 0x2f03, 0xc415, 0x2f0f, 0xc415, 0x21, 0 - .dw 0x2f11, 0xc415, 0x2f11, 0xc415, 0x21, 0 - .dw 0x2f13, 0xc415, 0x2f3f, 0xc415, 0x21, 0 - .dw 0x2f41, 0xc415, 0x2f41, 0xc415, 0x21, 0 - .dw 0x2f43, 0xc415, 0x2f4f, 0xc415, 0x21, 0 - .dw 0x2f51, 0xc415, 0x2f51, 0xc415, 0x21, 0 - .dw 0x2f53, 0xc415, 0x2f7f, 0xc415, 0x21, 0 - .dw 0x2f81, 0xc415, 0x2f81, 0xc415, 0x21, 0 - .dw 0x2f83, 0xc415, 0x2f8f, 0xc415, 0x21, 0 - .dw 0x2f91, 0xc415, 0x2f91, 0xc415, 0x21, 0 - .dw 0x2f93, 0xc415, 0x2fbf, 0xc415, 0x21, 0 - .dw 0x2fc0, 0xc415, 0x2fc0, 0xc415, 0x22, 0 - .dw 0x2fc1, 0xc415, 0x2fc1, 0xc415, 0x21, 0 - .dw 0x2fc2, 0xc415, 0x2fc2, 0xc415, 0x22, 0 - .dw 0x2fc3, 0xc415, 0x2fcf, 0xc415, 0x21, 0 - .dw 0x2fd0, 0xc415, 0x2fd0, 0xc415, 0x22, 0 - .dw 0x2fd1, 0xc415, 0x2fd1, 0xc415, 0x21, 0 - .dw 0x2fd2, 0xc415, 0x2fd2, 0xc415, 0x22, 0 - .dw 0x2fd3, 0xc415, 0x3fff, 0xc415, 0x21, 0 - .dw 0x4000, 0xc415, 0x4000, 0xc415, 0x22, 0 - .dw 0x4001, 0xc415, 0x4001, 0xc415, 0x21, 0 - .dw 0x4002, 0xc415, 0x4002, 0xc415, 0x22, 0 - .dw 0x4003, 0xc415, 0x400f, 0xc415, 0x21, 0 - .dw 0x4010, 0xc415, 0x4010, 0xc415, 0x22, 0 - .dw 0x4011, 0xc415, 0x4011, 0xc415, 0x21, 0 - .dw 0x4012, 0xc415, 0x4012, 0xc415, 0x22, 0 - .dw 0x4013, 0xc415, 0x403f, 0xc415, 0x21, 0 - .dw 0x4041, 0xc415, 0x4041, 0xc415, 0x21, 0 - .dw 0x4043, 0xc415, 0x404f, 0xc415, 0x21, 0 - .dw 0x4051, 0xc415, 0x4051, 0xc415, 0x21, 0 - .dw 0x4053, 0xc415, 0x407f, 0xc415, 0x21, 0 - .dw 0x4081, 0xc415, 0x4081, 0xc415, 0x21, 0 - .dw 0x4083, 0xc415, 0x408f, 0xc415, 0x21, 0 - .dw 0x4091, 0xc415, 0x4091, 0xc415, 0x21, 0 - .dw 0x4093, 0xc415, 0x40bf, 0xc415, 0x21, 0 - .dw 0x40c1, 0xc415, 0x40c1, 0xc415, 0x21, 0 - .dw 0x40c3, 0xc415, 0x40cf, 0xc415, 0x21, 0 - .dw 0x40d1, 0xc415, 0x40d1, 0xc415, 0x21, 0 - .dw 0x40d3, 0xc415, 0x40ff, 0xc415, 0x21, 0 - .dw 0x4101, 0xc415, 0x4101, 0xc415, 0x21, 0 - .dw 0x4103, 0xc415, 0x410f, 0xc415, 0x21, 0 - .dw 0x4111, 0xc415, 0x4111, 0xc415, 0x21, 0 - .dw 0x4113, 0xc415, 0x413f, 0xc415, 0x21, 0 - .dw 0x4141, 0xc415, 0x4141, 0xc415, 0x21, 0 - .dw 0x4143, 0xc415, 0x414f, 0xc415, 0x21, 0 - .dw 0x4151, 0xc415, 0x4151, 0xc415, 0x21, 0 - .dw 0x4153, 0xc415, 0x417f, 0xc415, 0x21, 0 - .dw 0x4181, 0xc415, 0x4181, 0xc415, 0x21, 0 - .dw 0x4183, 0xc415, 0x418f, 0xc415, 0x21, 0 - .dw 0x4191, 0xc415, 0x4191, 0xc415, 0x21, 0 - .dw 0x4193, 0xc415, 0x41bf, 0xc415, 0x21, 0 - .dw 0x41c1, 0xc415, 0x41c1, 0xc415, 0x21, 0 - .dw 0x41c3, 0xc415, 0x41cf, 0xc415, 0x21, 0 - .dw 0x41d1, 0xc415, 0x41d1, 0xc415, 0x21, 0 - .dw 0x41d3, 0xc415, 0x41ff, 0xc415, 0x21, 0 - .dw 0x4201, 0xc415, 0x4201, 0xc415, 0x21, 0 - .dw 0x4203, 0xc415, 0x420f, 0xc415, 0x21, 0 - .dw 0x4211, 0xc415, 0x4211, 0xc415, 0x21, 0 - .dw 0x4213, 0xc415, 0x423f, 0xc415, 0x21, 0 - .dw 0x4240, 0xc415, 0x4240, 0xc415, 0x22, 0 - .dw 0x4241, 0xc415, 0x4241, 0xc415, 0x21, 0 - .dw 0x4242, 0xc415, 0x4242, 0xc415, 0x22, 0 - .dw 0x4243, 0xc415, 0x424f, 0xc415, 0x21, 0 - .dw 0x4250, 0xc415, 0x4250, 0xc415, 0x22, 0 - .dw 0x4251, 0xc415, 0x4251, 0xc415, 0x21, 0 - .dw 0x4252, 0xc415, 0x4252, 0xc415, 0x22, 0 - .dw 0x4253, 0xc415, 0x427f, 0xc415, 0x21, 0 - .dw 0x4281, 0xc415, 0x4281, 0xc415, 0x21, 0 - .dw 0x4283, 0xc415, 0x428f, 0xc415, 0x21, 0 - .dw 0x4291, 0xc415, 0x4291, 0xc415, 0x21, 0 - .dw 0x4293, 0xc415, 0x42bf, 0xc415, 0x21, 0 - .dw 0x42c1, 0xc415, 0x42c1, 0xc415, 0x21, 0 - .dw 0x42c3, 0xc415, 0x42cf, 0xc415, 0x21, 0 - .dw 0x42d1, 0xc415, 0x42d1, 0xc415, 0x21, 0 - .dw 0x42d3, 0xc415, 0x42ff, 0xc415, 0x21, 0 - .dw 0x4301, 0xc415, 0x4301, 0xc415, 0x21, 0 - .dw 0x4303, 0xc415, 0x430f, 0xc415, 0x21, 0 - .dw 0x4311, 0xc415, 0x4311, 0xc415, 0x21, 0 - .dw 0x4313, 0xc415, 0x433f, 0xc415, 0x21, 0 - .dw 0x4341, 0xc415, 0x4341, 0xc415, 0x21, 0 - .dw 0x4343, 0xc415, 0x434f, 0xc415, 0x21, 0 - .dw 0x4351, 0xc415, 0x4351, 0xc415, 0x21, 0 - .dw 0x4353, 0xc415, 0x437f, 0xc415, 0x21, 0 - .dw 0x4381, 0xc415, 0x4381, 0xc415, 0x21, 0 - .dw 0x4383, 0xc415, 0x438f, 0xc415, 0x21, 0 - .dw 0x4391, 0xc415, 0x4391, 0xc415, 0x21, 0 - .dw 0x4393, 0xc415, 0x43bf, 0xc415, 0x21, 0 - .dw 0x43c1, 0xc415, 0x43c1, 0xc415, 0x21, 0 - .dw 0x43c3, 0xc415, 0x43cf, 0xc415, 0x21, 0 - .dw 0x43d1, 0xc415, 0x43d1, 0xc415, 0x21, 0 - .dw 0x43d3, 0xc415, 0x43ff, 0xc415, 0x21, 0 - .dw 0x4401, 0xc415, 0x4401, 0xc415, 0x21, 0 - .dw 0x4403, 0xc415, 0x440f, 0xc415, 0x21, 0 - .dw 0x4411, 0xc415, 0x4411, 0xc415, 0x21, 0 - .dw 0x4413, 0xc415, 0x443f, 0xc415, 0x21, 0 - .dw 0x4441, 0xc415, 0x4441, 0xc415, 0x21, 0 - .dw 0x4443, 0xc415, 0x444f, 0xc415, 0x21, 0 - .dw 0x4451, 0xc415, 0x4451, 0xc415, 0x21, 0 - .dw 0x4453, 0xc415, 0x447f, 0xc415, 0x21, 0 - .dw 0x4480, 0xc415, 0x4480, 0xc415, 0x22, 0 - .dw 0x4481, 0xc415, 0x4481, 0xc415, 0x21, 0 - .dw 0x4482, 0xc415, 0x4482, 0xc415, 0x22, 0 - .dw 0x4483, 0xc415, 0x448f, 0xc415, 0x21, 0 - .dw 0x4490, 0xc415, 0x4490, 0xc415, 0x22, 0 - .dw 0x4491, 0xc415, 0x4491, 0xc415, 0x21, 0 - .dw 0x4492, 0xc415, 0x4492, 0xc415, 0x22, 0 - .dw 0x4493, 0xc415, 0x44bf, 0xc415, 0x21, 0 - .dw 0x44c1, 0xc415, 0x44c1, 0xc415, 0x21, 0 - .dw 0x44c3, 0xc415, 0x44cf, 0xc415, 0x21, 0 - .dw 0x44d1, 0xc415, 0x44d1, 0xc415, 0x21, 0 - .dw 0x44d3, 0xc415, 0x44ff, 0xc415, 0x21, 0 - .dw 0x4501, 0xc415, 0x4501, 0xc415, 0x21, 0 - .dw 0x4503, 0xc415, 0x450f, 0xc415, 0x21, 0 - .dw 0x4511, 0xc415, 0x4511, 0xc415, 0x21, 0 - .dw 0x4513, 0xc415, 0x453f, 0xc415, 0x21, 0 - .dw 0x4541, 0xc415, 0x4541, 0xc415, 0x21, 0 - .dw 0x4543, 0xc415, 0x454f, 0xc415, 0x21, 0 - .dw 0x4551, 0xc415, 0x4551, 0xc415, 0x21, 0 - .dw 0x4553, 0xc415, 0x457f, 0xc415, 0x21, 0 - .dw 0x4581, 0xc415, 0x4581, 0xc415, 0x21, 0 - .dw 0x4583, 0xc415, 0x458f, 0xc415, 0x21, 0 - .dw 0x4591, 0xc415, 0x4591, 0xc415, 0x21, 0 - .dw 0x4593, 0xc415, 0x45bf, 0xc415, 0x21, 0 - .dw 0x45c1, 0xc415, 0x45c1, 0xc415, 0x21, 0 - .dw 0x45c3, 0xc415, 0x45cf, 0xc415, 0x21, 0 - .dw 0x45d1, 0xc415, 0x45d1, 0xc415, 0x21, 0 - .dw 0x45d3, 0xc415, 0x45ff, 0xc415, 0x21, 0 - .dw 0x4601, 0xc415, 0x4601, 0xc415, 0x21, 0 - .dw 0x4603, 0xc415, 0x460f, 0xc415, 0x21, 0 - .dw 0x4611, 0xc415, 0x4611, 0xc415, 0x21, 0 - .dw 0x4613, 0xc415, 0x463f, 0xc415, 0x21, 0 - .dw 0x4641, 0xc415, 0x4641, 0xc415, 0x21, 0 - .dw 0x4643, 0xc415, 0x464f, 0xc415, 0x21, 0 - .dw 0x4651, 0xc415, 0x4651, 0xc415, 0x21, 0 - .dw 0x4653, 0xc415, 0x467f, 0xc415, 0x21, 0 - .dw 0x4681, 0xc415, 0x4681, 0xc415, 0x21, 0 - .dw 0x4683, 0xc415, 0x468f, 0xc415, 0x21, 0 - .dw 0x4691, 0xc415, 0x4691, 0xc415, 0x21, 0 - .dw 0x4693, 0xc415, 0x46bf, 0xc415, 0x21, 0 - .dw 0x46c0, 0xc415, 0x46c0, 0xc415, 0x22, 0 - .dw 0x46c1, 0xc415, 0x46c1, 0xc415, 0x21, 0 - .dw 0x46c2, 0xc415, 0x46c2, 0xc415, 0x22, 0 - .dw 0x46c3, 0xc415, 0x46cf, 0xc415, 0x21, 0 - .dw 0x46d0, 0xc415, 0x46d0, 0xc415, 0x22, 0 - .dw 0x46d1, 0xc415, 0x46d1, 0xc415, 0x21, 0 - .dw 0x46d2, 0xc415, 0x46d2, 0xc415, 0x22, 0 - .dw 0x46d3, 0xc415, 0x46ff, 0xc415, 0x21, 0 - .dw 0x4701, 0xc415, 0x4701, 0xc415, 0x21, 0 - .dw 0x4703, 0xc415, 0x470f, 0xc415, 0x21, 0 - .dw 0x4711, 0xc415, 0x4711, 0xc415, 0x21, 0 - .dw 0x4713, 0xc415, 0x473f, 0xc415, 0x21, 0 - .dw 0x4741, 0xc415, 0x4741, 0xc415, 0x21, 0 - .dw 0x4743, 0xc415, 0x474f, 0xc415, 0x21, 0 - .dw 0x4751, 0xc415, 0x4751, 0xc415, 0x21, 0 - .dw 0x4753, 0xc415, 0x477f, 0xc415, 0x21, 0 - .dw 0x4781, 0xc415, 0x4781, 0xc415, 0x21, 0 - .dw 0x4783, 0xc415, 0x478f, 0xc415, 0x21, 0 - .dw 0x4791, 0xc415, 0x4791, 0xc415, 0x21, 0 - .dw 0x4793, 0xc415, 0x47bf, 0xc415, 0x21, 0 - .dw 0x47c1, 0xc415, 0x47c1, 0xc415, 0x21, 0 - .dw 0x47c3, 0xc415, 0x47cf, 0xc415, 0x21, 0 - .dw 0x47d1, 0xc415, 0x47d1, 0xc415, 0x21, 0 - .dw 0x47d3, 0xc415, 0x47ff, 0xc415, 0x21, 0 - .dw 0x4801, 0xc415, 0x4801, 0xc415, 0x21, 0 - .dw 0x4803, 0xc415, 0x480f, 0xc415, 0x21, 0 - .dw 0x4811, 0xc415, 0x4811, 0xc415, 0x21, 0 - .dw 0x4813, 0xc415, 0x483f, 0xc415, 0x21, 0 - .dw 0x4841, 0xc415, 0x4841, 0xc415, 0x21, 0 - .dw 0x4843, 0xc415, 0x484f, 0xc415, 0x21, 0 - .dw 0x4851, 0xc415, 0x4851, 0xc415, 0x21, 0 - .dw 0x4853, 0xc415, 0x487f, 0xc415, 0x21, 0 - .dw 0x4881, 0xc415, 0x4881, 0xc415, 0x21, 0 - .dw 0x4883, 0xc415, 0x488f, 0xc415, 0x21, 0 - .dw 0x4891, 0xc415, 0x4891, 0xc415, 0x21, 0 - .dw 0x4893, 0xc415, 0x48bf, 0xc415, 0x21, 0 - .dw 0x48c1, 0xc415, 0x48c1, 0xc415, 0x21, 0 - .dw 0x48c3, 0xc415, 0x48cf, 0xc415, 0x21, 0 - .dw 0x48d1, 0xc415, 0x48d1, 0xc415, 0x21, 0 - .dw 0x48d3, 0xc415, 0x48ff, 0xc415, 0x21, 0 - .dw 0x4900, 0xc415, 0x4900, 0xc415, 0x22, 0 - .dw 0x4901, 0xc415, 0x4901, 0xc415, 0x21, 0 - .dw 0x4902, 0xc415, 0x4902, 0xc415, 0x22, 0 - .dw 0x4903, 0xc415, 0x490f, 0xc415, 0x21, 0 - .dw 0x4910, 0xc415, 0x4910, 0xc415, 0x22, 0 - .dw 0x4911, 0xc415, 0x4911, 0xc415, 0x21, 0 - .dw 0x4912, 0xc415, 0x4912, 0xc415, 0x22, 0 - .dw 0x4913, 0xc415, 0x493f, 0xc415, 0x21, 0 - .dw 0x4941, 0xc415, 0x4941, 0xc415, 0x21, 0 - .dw 0x4943, 0xc415, 0x494f, 0xc415, 0x21, 0 - .dw 0x4951, 0xc415, 0x4951, 0xc415, 0x21, 0 - .dw 0x4953, 0xc415, 0x497f, 0xc415, 0x21, 0 - .dw 0x4981, 0xc415, 0x4981, 0xc415, 0x21, 0 - .dw 0x4983, 0xc415, 0x498f, 0xc415, 0x21, 0 - .dw 0x4991, 0xc415, 0x4991, 0xc415, 0x21, 0 - .dw 0x4993, 0xc415, 0x49bf, 0xc415, 0x21, 0 - .dw 0x49c1, 0xc415, 0x49c1, 0xc415, 0x21, 0 - .dw 0x49c3, 0xc415, 0x49cf, 0xc415, 0x21, 0 - .dw 0x49d1, 0xc415, 0x49d1, 0xc415, 0x21, 0 - .dw 0x49d3, 0xc415, 0x49ff, 0xc415, 0x21, 0 - .dw 0x4a01, 0xc415, 0x4a01, 0xc415, 0x21, 0 - .dw 0x4a03, 0xc415, 0x4a0f, 0xc415, 0x21, 0 - .dw 0x4a11, 0xc415, 0x4a11, 0xc415, 0x21, 0 - .dw 0x4a13, 0xc415, 0x4a3f, 0xc415, 0x21, 0 - .dw 0x4a41, 0xc415, 0x4a41, 0xc415, 0x21, 0 - .dw 0x4a43, 0xc415, 0x4a4f, 0xc415, 0x21, 0 - .dw 0x4a51, 0xc415, 0x4a51, 0xc415, 0x21, 0 - .dw 0x4a53, 0xc415, 0x4a7f, 0xc415, 0x21, 0 - .dw 0x4a81, 0xc415, 0x4a81, 0xc415, 0x21, 0 - .dw 0x4a83, 0xc415, 0x4a8f, 0xc415, 0x21, 0 - .dw 0x4a91, 0xc415, 0x4a91, 0xc415, 0x21, 0 - .dw 0x4a93, 0xc415, 0x4abf, 0xc415, 0x21, 0 - .dw 0x4ac1, 0xc415, 0x4ac1, 0xc415, 0x21, 0 - .dw 0x4ac3, 0xc415, 0x4acf, 0xc415, 0x21, 0 - .dw 0x4ad1, 0xc415, 0x4ad1, 0xc415, 0x21, 0 - .dw 0x4ad3, 0xc415, 0x4aff, 0xc415, 0x21, 0 - .dw 0x4b01, 0xc415, 0x4b01, 0xc415, 0x21, 0 - .dw 0x4b03, 0xc415, 0x4b0f, 0xc415, 0x21, 0 - .dw 0x4b11, 0xc415, 0x4b11, 0xc415, 0x21, 0 - .dw 0x4b13, 0xc415, 0x4b3f, 0xc415, 0x21, 0 - .dw 0x4b40, 0xc415, 0x4b40, 0xc415, 0x22, 0 - .dw 0x4b41, 0xc415, 0x4b41, 0xc415, 0x21, 0 - .dw 0x4b42, 0xc415, 0x4b42, 0xc415, 0x22, 0 - .dw 0x4b43, 0xc415, 0x4b4f, 0xc415, 0x21, 0 - .dw 0x4b50, 0xc415, 0x4b50, 0xc415, 0x22, 0 - .dw 0x4b51, 0xc415, 0x4b51, 0xc415, 0x21, 0 - .dw 0x4b52, 0xc415, 0x4b52, 0xc415, 0x22, 0 - .dw 0x4b53, 0xc415, 0x4b7f, 0xc415, 0x21, 0 - .dw 0x4b81, 0xc415, 0x4b81, 0xc415, 0x21, 0 - .dw 0x4b83, 0xc415, 0x4b8f, 0xc415, 0x21, 0 - .dw 0x4b91, 0xc415, 0x4b91, 0xc415, 0x21, 0 - .dw 0x4b93, 0xc415, 0x4bbf, 0xc415, 0x21, 0 - .dw 0x4bc1, 0xc415, 0x4bc1, 0xc415, 0x21, 0 - .dw 0x4bc3, 0xc415, 0x4bcf, 0xc415, 0x21, 0 - .dw 0x4bd1, 0xc415, 0x4bd1, 0xc415, 0x21, 0 - .dw 0x4bd3, 0xc415, 0x4bff, 0xc415, 0x21, 0 - .dw 0x4c01, 0xc415, 0x4c01, 0xc415, 0x21, 0 - .dw 0x4c03, 0xc415, 0x4c0f, 0xc415, 0x21, 0 - .dw 0x4c11, 0xc415, 0x4c11, 0xc415, 0x21, 0 - .dw 0x4c13, 0xc415, 0x4c3f, 0xc415, 0x21, 0 - .dw 0x4c41, 0xc415, 0x4c41, 0xc415, 0x21, 0 - .dw 0x4c43, 0xc415, 0x4c4f, 0xc415, 0x21, 0 - .dw 0x4c51, 0xc415, 0x4c51, 0xc415, 0x21, 0 - .dw 0x4c53, 0xc415, 0x4c7f, 0xc415, 0x21, 0 - .dw 0x4c81, 0xc415, 0x4c81, 0xc415, 0x21, 0 - .dw 0x4c83, 0xc415, 0x4c8f, 0xc415, 0x21, 0 - .dw 0x4c91, 0xc415, 0x4c91, 0xc415, 0x21, 0 - .dw 0x4c93, 0xc415, 0x4cbf, 0xc415, 0x21, 0 - .dw 0x4cc1, 0xc415, 0x4cc1, 0xc415, 0x21, 0 - .dw 0x4cc3, 0xc415, 0x4ccf, 0xc415, 0x21, 0 - .dw 0x4cd1, 0xc415, 0x4cd1, 0xc415, 0x21, 0 - .dw 0x4cd3, 0xc415, 0x4cff, 0xc415, 0x21, 0 - .dw 0x4d01, 0xc415, 0x4d01, 0xc415, 0x21, 0 - .dw 0x4d03, 0xc415, 0x4d0f, 0xc415, 0x21, 0 - .dw 0x4d11, 0xc415, 0x4d11, 0xc415, 0x21, 0 - .dw 0x4d13, 0xc415, 0x4d3f, 0xc415, 0x21, 0 - .dw 0x4d41, 0xc415, 0x4d41, 0xc415, 0x21, 0 - .dw 0x4d43, 0xc415, 0x4d4f, 0xc415, 0x21, 0 - .dw 0x4d51, 0xc415, 0x4d51, 0xc415, 0x21, 0 - .dw 0x4d53, 0xc415, 0x4d7f, 0xc415, 0x21, 0 - .dw 0x4d80, 0xc415, 0x4d80, 0xc415, 0x22, 0 - .dw 0x4d81, 0xc415, 0x4d81, 0xc415, 0x21, 0 - .dw 0x4d82, 0xc415, 0x4d82, 0xc415, 0x22, 0 - .dw 0x4d83, 0xc415, 0x4d8f, 0xc415, 0x21, 0 - .dw 0x4d90, 0xc415, 0x4d90, 0xc415, 0x22, 0 - .dw 0x4d91, 0xc415, 0x4d91, 0xc415, 0x21, 0 - .dw 0x4d92, 0xc415, 0x4d92, 0xc415, 0x22, 0 - .dw 0x4d93, 0xc415, 0x4dbf, 0xc415, 0x21, 0 - .dw 0x4dc1, 0xc415, 0x4dc1, 0xc415, 0x21, 0 - .dw 0x4dc3, 0xc415, 0x4dcf, 0xc415, 0x21, 0 - .dw 0x4dd1, 0xc415, 0x4dd1, 0xc415, 0x21, 0 - .dw 0x4dd3, 0xc415, 0x4dff, 0xc415, 0x21, 0 - .dw 0x4e01, 0xc415, 0x4e01, 0xc415, 0x21, 0 - .dw 0x4e03, 0xc415, 0x4e0f, 0xc415, 0x21, 0 - .dw 0x4e11, 0xc415, 0x4e11, 0xc415, 0x21, 0 - .dw 0x4e13, 0xc415, 0x4e3f, 0xc415, 0x21, 0 - .dw 0x4e41, 0xc415, 0x4e41, 0xc415, 0x21, 0 - .dw 0x4e43, 0xc415, 0x4e4f, 0xc415, 0x21, 0 - .dw 0x4e51, 0xc415, 0x4e51, 0xc415, 0x21, 0 - .dw 0x4e53, 0xc415, 0x4e7f, 0xc415, 0x21, 0 - .dw 0x4e81, 0xc415, 0x4e81, 0xc415, 0x21, 0 - .dw 0x4e83, 0xc415, 0x4e8f, 0xc415, 0x21, 0 - .dw 0x4e91, 0xc415, 0x4e91, 0xc415, 0x21, 0 - .dw 0x4e93, 0xc415, 0x4ebf, 0xc415, 0x21, 0 - .dw 0x4ec1, 0xc415, 0x4ec1, 0xc415, 0x21, 0 - .dw 0x4ec3, 0xc415, 0x4ecf, 0xc415, 0x21, 0 - .dw 0x4ed1, 0xc415, 0x4ed1, 0xc415, 0x21, 0 - .dw 0x4ed3, 0xc415, 0x4eff, 0xc415, 0x21, 0 - .dw 0x4f01, 0xc415, 0x4f01, 0xc415, 0x21, 0 - .dw 0x4f03, 0xc415, 0x4f0f, 0xc415, 0x21, 0 - .dw 0x4f11, 0xc415, 0x4f11, 0xc415, 0x21, 0 - .dw 0x4f13, 0xc415, 0x4f3f, 0xc415, 0x21, 0 - .dw 0x4f41, 0xc415, 0x4f41, 0xc415, 0x21, 0 - .dw 0x4f43, 0xc415, 0x4f4f, 0xc415, 0x21, 0 - .dw 0x4f51, 0xc415, 0x4f51, 0xc415, 0x21, 0 - .dw 0x4f53, 0xc415, 0x4f7f, 0xc415, 0x21, 0 - .dw 0x4f81, 0xc415, 0x4f81, 0xc415, 0x21, 0 - .dw 0x4f83, 0xc415, 0x4f8f, 0xc415, 0x21, 0 - .dw 0x4f91, 0xc415, 0x4f91, 0xc415, 0x21, 0 - .dw 0x4f93, 0xc415, 0x4fbf, 0xc415, 0x21, 0 - .dw 0x4fc0, 0xc415, 0x4fc0, 0xc415, 0x22, 0 - .dw 0x4fc1, 0xc415, 0x4fc1, 0xc415, 0x21, 0 - .dw 0x4fc2, 0xc415, 0x4fc2, 0xc415, 0x22, 0 - .dw 0x4fc3, 0xc415, 0x4fcf, 0xc415, 0x21, 0 - .dw 0x4fd0, 0xc415, 0x4fd0, 0xc415, 0x22, 0 - .dw 0x4fd1, 0xc415, 0x4fd1, 0xc415, 0x21, 0 - .dw 0x4fd2, 0xc415, 0x4fd2, 0xc415, 0x22, 0 - .dw 0x4fd3, 0xc415, 0x5fff, 0xc415, 0x21, 0 - .dw 0x6000, 0xc415, 0x6000, 0xc415, 0x22, 0 - .dw 0x6001, 0xc415, 0x6001, 0xc415, 0x21, 0 - .dw 0x6002, 0xc415, 0x6002, 0xc415, 0x22, 0 - .dw 0x6003, 0xc415, 0x600f, 0xc415, 0x21, 0 - .dw 0x6010, 0xc415, 0x6010, 0xc415, 0x22, 0 - .dw 0x6011, 0xc415, 0x6011, 0xc415, 0x21, 0 - .dw 0x6012, 0xc415, 0x6012, 0xc415, 0x22, 0 - .dw 0x6013, 0xc415, 0x603f, 0xc415, 0x21, 0 - .dw 0x6041, 0xc415, 0x6041, 0xc415, 0x21, 0 - .dw 0x6043, 0xc415, 0x604f, 0xc415, 0x21, 0 - .dw 0x6051, 0xc415, 0x6051, 0xc415, 0x21, 0 - .dw 0x6053, 0xc415, 0x607f, 0xc415, 0x21, 0 - .dw 0x6081, 0xc415, 0x6081, 0xc415, 0x21, 0 - .dw 0x6083, 0xc415, 0x608f, 0xc415, 0x21, 0 - .dw 0x6091, 0xc415, 0x6091, 0xc415, 0x21, 0 - .dw 0x6093, 0xc415, 0x60bf, 0xc415, 0x21, 0 - .dw 0x60c1, 0xc415, 0x60c1, 0xc415, 0x21, 0 - .dw 0x60c3, 0xc415, 0x60cf, 0xc415, 0x21, 0 - .dw 0x60d1, 0xc415, 0x60d1, 0xc415, 0x21, 0 - .dw 0x60d3, 0xc415, 0x60ff, 0xc415, 0x21, 0 - .dw 0x6101, 0xc415, 0x6101, 0xc415, 0x21, 0 - .dw 0x6103, 0xc415, 0x610f, 0xc415, 0x21, 0 - .dw 0x6111, 0xc415, 0x6111, 0xc415, 0x21, 0 - .dw 0x6113, 0xc415, 0x613f, 0xc415, 0x21, 0 - .dw 0x6141, 0xc415, 0x6141, 0xc415, 0x21, 0 - .dw 0x6143, 0xc415, 0x614f, 0xc415, 0x21, 0 - .dw 0x6151, 0xc415, 0x6151, 0xc415, 0x21, 0 - .dw 0x6153, 0xc415, 0x617f, 0xc415, 0x21, 0 - .dw 0x6181, 0xc415, 0x6181, 0xc415, 0x21, 0 - .dw 0x6183, 0xc415, 0x618f, 0xc415, 0x21, 0 - .dw 0x6191, 0xc415, 0x6191, 0xc415, 0x21, 0 - .dw 0x6193, 0xc415, 0x61bf, 0xc415, 0x21, 0 - .dw 0x61c1, 0xc415, 0x61c1, 0xc415, 0x21, 0 - .dw 0x61c3, 0xc415, 0x61cf, 0xc415, 0x21, 0 - .dw 0x61d1, 0xc415, 0x61d1, 0xc415, 0x21, 0 - .dw 0x61d3, 0xc415, 0x61ff, 0xc415, 0x21, 0 - .dw 0x6201, 0xc415, 0x6201, 0xc415, 0x21, 0 - .dw 0x6203, 0xc415, 0x620f, 0xc415, 0x21, 0 - .dw 0x6211, 0xc415, 0x6211, 0xc415, 0x21, 0 - .dw 0x6213, 0xc415, 0x623f, 0xc415, 0x21, 0 - .dw 0x6240, 0xc415, 0x6240, 0xc415, 0x22, 0 - .dw 0x6241, 0xc415, 0x6241, 0xc415, 0x21, 0 - .dw 0x6242, 0xc415, 0x6242, 0xc415, 0x22, 0 - .dw 0x6243, 0xc415, 0x624f, 0xc415, 0x21, 0 - .dw 0x6250, 0xc415, 0x6250, 0xc415, 0x22, 0 - .dw 0x6251, 0xc415, 0x6251, 0xc415, 0x21, 0 - .dw 0x6252, 0xc415, 0x6252, 0xc415, 0x22, 0 - .dw 0x6253, 0xc415, 0x627f, 0xc415, 0x21, 0 - .dw 0x6281, 0xc415, 0x6281, 0xc415, 0x21, 0 - .dw 0x6283, 0xc415, 0x628f, 0xc415, 0x21, 0 - .dw 0x6291, 0xc415, 0x6291, 0xc415, 0x21, 0 - .dw 0x6293, 0xc415, 0x62bf, 0xc415, 0x21, 0 - .dw 0x62c1, 0xc415, 0x62c1, 0xc415, 0x21, 0 - .dw 0x62c3, 0xc415, 0x62cf, 0xc415, 0x21, 0 - .dw 0x62d1, 0xc415, 0x62d1, 0xc415, 0x21, 0 - .dw 0x62d3, 0xc415, 0x62ff, 0xc415, 0x21, 0 - .dw 0x6301, 0xc415, 0x6301, 0xc415, 0x21, 0 - .dw 0x6303, 0xc415, 0x630f, 0xc415, 0x21, 0 - .dw 0x6311, 0xc415, 0x6311, 0xc415, 0x21, 0 - .dw 0x6313, 0xc415, 0x633f, 0xc415, 0x21, 0 - .dw 0x6341, 0xc415, 0x6341, 0xc415, 0x21, 0 - .dw 0x6343, 0xc415, 0x634f, 0xc415, 0x21, 0 - .dw 0x6351, 0xc415, 0x6351, 0xc415, 0x21, 0 - .dw 0x6353, 0xc415, 0x637f, 0xc415, 0x21, 0 - .dw 0x6381, 0xc415, 0x6381, 0xc415, 0x21, 0 - .dw 0x6383, 0xc415, 0x638f, 0xc415, 0x21, 0 - .dw 0x6391, 0xc415, 0x6391, 0xc415, 0x21, 0 - .dw 0x6393, 0xc415, 0x63bf, 0xc415, 0x21, 0 - .dw 0x63c1, 0xc415, 0x63c1, 0xc415, 0x21, 0 - .dw 0x63c3, 0xc415, 0x63cf, 0xc415, 0x21, 0 - .dw 0x63d1, 0xc415, 0x63d1, 0xc415, 0x21, 0 - .dw 0x63d3, 0xc415, 0x63ff, 0xc415, 0x21, 0 - .dw 0x6401, 0xc415, 0x6401, 0xc415, 0x21, 0 - .dw 0x6403, 0xc415, 0x640f, 0xc415, 0x21, 0 - .dw 0x6411, 0xc415, 0x6411, 0xc415, 0x21, 0 - .dw 0x6413, 0xc415, 0x643f, 0xc415, 0x21, 0 - .dw 0x6441, 0xc415, 0x6441, 0xc415, 0x21, 0 - .dw 0x6443, 0xc415, 0x644f, 0xc415, 0x21, 0 - .dw 0x6451, 0xc415, 0x6451, 0xc415, 0x21, 0 - .dw 0x6453, 0xc415, 0x647f, 0xc415, 0x21, 0 - .dw 0x6480, 0xc415, 0x6480, 0xc415, 0x22, 0 - .dw 0x6481, 0xc415, 0x6481, 0xc415, 0x21, 0 - .dw 0x6482, 0xc415, 0x6482, 0xc415, 0x22, 0 - .dw 0x6483, 0xc415, 0x648f, 0xc415, 0x21, 0 - .dw 0x6490, 0xc415, 0x6490, 0xc415, 0x22, 0 - .dw 0x6491, 0xc415, 0x6491, 0xc415, 0x21, 0 - .dw 0x6492, 0xc415, 0x6492, 0xc415, 0x22, 0 - .dw 0x6493, 0xc415, 0x64bf, 0xc415, 0x21, 0 - .dw 0x64c1, 0xc415, 0x64c1, 0xc415, 0x21, 0 - .dw 0x64c3, 0xc415, 0x64cf, 0xc415, 0x21, 0 - .dw 0x64d1, 0xc415, 0x64d1, 0xc415, 0x21, 0 - .dw 0x64d3, 0xc415, 0x64ff, 0xc415, 0x21, 0 - .dw 0x6501, 0xc415, 0x6501, 0xc415, 0x21, 0 - .dw 0x6503, 0xc415, 0x650f, 0xc415, 0x21, 0 - .dw 0x6511, 0xc415, 0x6511, 0xc415, 0x21, 0 - .dw 0x6513, 0xc415, 0x653f, 0xc415, 0x21, 0 - .dw 0x6541, 0xc415, 0x6541, 0xc415, 0x21, 0 - .dw 0x6543, 0xc415, 0x654f, 0xc415, 0x21, 0 - .dw 0x6551, 0xc415, 0x6551, 0xc415, 0x21, 0 - .dw 0x6553, 0xc415, 0x657f, 0xc415, 0x21, 0 - .dw 0x6581, 0xc415, 0x6581, 0xc415, 0x21, 0 - .dw 0x6583, 0xc415, 0x658f, 0xc415, 0x21, 0 - .dw 0x6591, 0xc415, 0x6591, 0xc415, 0x21, 0 - .dw 0x6593, 0xc415, 0x65bf, 0xc415, 0x21, 0 - .dw 0x65c1, 0xc415, 0x65c1, 0xc415, 0x21, 0 - .dw 0x65c3, 0xc415, 0x65cf, 0xc415, 0x21, 0 - .dw 0x65d1, 0xc415, 0x65d1, 0xc415, 0x21, 0 - .dw 0x65d3, 0xc415, 0x65ff, 0xc415, 0x21, 0 - .dw 0x6601, 0xc415, 0x6601, 0xc415, 0x21, 0 - .dw 0x6603, 0xc415, 0x660f, 0xc415, 0x21, 0 - .dw 0x6611, 0xc415, 0x6611, 0xc415, 0x21, 0 - .dw 0x6613, 0xc415, 0x663f, 0xc415, 0x21, 0 - .dw 0x6641, 0xc415, 0x6641, 0xc415, 0x21, 0 - .dw 0x6643, 0xc415, 0x664f, 0xc415, 0x21, 0 - .dw 0x6651, 0xc415, 0x6651, 0xc415, 0x21, 0 - .dw 0x6653, 0xc415, 0x667f, 0xc415, 0x21, 0 - .dw 0x6681, 0xc415, 0x6681, 0xc415, 0x21, 0 - .dw 0x6683, 0xc415, 0x668f, 0xc415, 0x21, 0 - .dw 0x6691, 0xc415, 0x6691, 0xc415, 0x21, 0 - .dw 0x6693, 0xc415, 0x66bf, 0xc415, 0x21, 0 - .dw 0x66c0, 0xc415, 0x66c0, 0xc415, 0x22, 0 - .dw 0x66c1, 0xc415, 0x66c1, 0xc415, 0x21, 0 - .dw 0x66c2, 0xc415, 0x66c2, 0xc415, 0x22, 0 - .dw 0x66c3, 0xc415, 0x66cf, 0xc415, 0x21, 0 - .dw 0x66d0, 0xc415, 0x66d0, 0xc415, 0x22, 0 - .dw 0x66d1, 0xc415, 0x66d1, 0xc415, 0x21, 0 - .dw 0x66d2, 0xc415, 0x66d2, 0xc415, 0x22, 0 - .dw 0x66d3, 0xc415, 0x66ff, 0xc415, 0x21, 0 - .dw 0x6701, 0xc415, 0x6701, 0xc415, 0x21, 0 - .dw 0x6703, 0xc415, 0x670f, 0xc415, 0x21, 0 - .dw 0x6711, 0xc415, 0x6711, 0xc415, 0x21, 0 - .dw 0x6713, 0xc415, 0x673f, 0xc415, 0x21, 0 - .dw 0x6741, 0xc415, 0x6741, 0xc415, 0x21, 0 - .dw 0x6743, 0xc415, 0x674f, 0xc415, 0x21, 0 - .dw 0x6751, 0xc415, 0x6751, 0xc415, 0x21, 0 - .dw 0x6753, 0xc415, 0x677f, 0xc415, 0x21, 0 - .dw 0x6781, 0xc415, 0x6781, 0xc415, 0x21, 0 - .dw 0x6783, 0xc415, 0x678f, 0xc415, 0x21, 0 - .dw 0x6791, 0xc415, 0x6791, 0xc415, 0x21, 0 - .dw 0x6793, 0xc415, 0x67bf, 0xc415, 0x21, 0 - .dw 0x67c1, 0xc415, 0x67c1, 0xc415, 0x21, 0 - .dw 0x67c3, 0xc415, 0x67cf, 0xc415, 0x21, 0 - .dw 0x67d1, 0xc415, 0x67d1, 0xc415, 0x21, 0 - .dw 0x67d3, 0xc415, 0x67ff, 0xc415, 0x21, 0 - .dw 0x6801, 0xc415, 0x6801, 0xc415, 0x21, 0 - .dw 0x6803, 0xc415, 0x680f, 0xc415, 0x21, 0 - .dw 0x6811, 0xc415, 0x6811, 0xc415, 0x21, 0 - .dw 0x6813, 0xc415, 0x683f, 0xc415, 0x21, 0 - .dw 0x6841, 0xc415, 0x6841, 0xc415, 0x21, 0 - .dw 0x6843, 0xc415, 0x684f, 0xc415, 0x21, 0 - .dw 0x6851, 0xc415, 0x6851, 0xc415, 0x21, 0 - .dw 0x6853, 0xc415, 0x687f, 0xc415, 0x21, 0 - .dw 0x6881, 0xc415, 0x6881, 0xc415, 0x21, 0 - .dw 0x6883, 0xc415, 0x688f, 0xc415, 0x21, 0 - .dw 0x6891, 0xc415, 0x6891, 0xc415, 0x21, 0 - .dw 0x6893, 0xc415, 0x68bf, 0xc415, 0x21, 0 - .dw 0x68c1, 0xc415, 0x68c1, 0xc415, 0x21, 0 - .dw 0x68c3, 0xc415, 0x68cf, 0xc415, 0x21, 0 - .dw 0x68d1, 0xc415, 0x68d1, 0xc415, 0x21, 0 - .dw 0x68d3, 0xc415, 0x68ff, 0xc415, 0x21, 0 - .dw 0x6900, 0xc415, 0x6900, 0xc415, 0x22, 0 - .dw 0x6901, 0xc415, 0x6901, 0xc415, 0x21, 0 - .dw 0x6902, 0xc415, 0x6902, 0xc415, 0x22, 0 - .dw 0x6903, 0xc415, 0x690f, 0xc415, 0x21, 0 - .dw 0x6910, 0xc415, 0x6910, 0xc415, 0x22, 0 - .dw 0x6911, 0xc415, 0x6911, 0xc415, 0x21, 0 - .dw 0x6912, 0xc415, 0x6912, 0xc415, 0x22, 0 - .dw 0x6913, 0xc415, 0x693f, 0xc415, 0x21, 0 - .dw 0x6941, 0xc415, 0x6941, 0xc415, 0x21, 0 - .dw 0x6943, 0xc415, 0x694f, 0xc415, 0x21, 0 - .dw 0x6951, 0xc415, 0x6951, 0xc415, 0x21, 0 - .dw 0x6953, 0xc415, 0x697f, 0xc415, 0x21, 0 - .dw 0x6981, 0xc415, 0x6981, 0xc415, 0x21, 0 - .dw 0x6983, 0xc415, 0x698f, 0xc415, 0x21, 0 - .dw 0x6991, 0xc415, 0x6991, 0xc415, 0x21, 0 - .dw 0x6993, 0xc415, 0x69bf, 0xc415, 0x21, 0 - .dw 0x69c1, 0xc415, 0x69c1, 0xc415, 0x21, 0 - .dw 0x69c3, 0xc415, 0x69cf, 0xc415, 0x21, 0 - .dw 0x69d1, 0xc415, 0x69d1, 0xc415, 0x21, 0 - .dw 0x69d3, 0xc415, 0x69ff, 0xc415, 0x21, 0 - .dw 0x6a01, 0xc415, 0x6a01, 0xc415, 0x21, 0 - .dw 0x6a03, 0xc415, 0x6a0f, 0xc415, 0x21, 0 - .dw 0x6a11, 0xc415, 0x6a11, 0xc415, 0x21, 0 - .dw 0x6a13, 0xc415, 0x6a3f, 0xc415, 0x21, 0 - .dw 0x6a41, 0xc415, 0x6a41, 0xc415, 0x21, 0 - .dw 0x6a43, 0xc415, 0x6a4f, 0xc415, 0x21, 0 - .dw 0x6a51, 0xc415, 0x6a51, 0xc415, 0x21, 0 - .dw 0x6a53, 0xc415, 0x6a7f, 0xc415, 0x21, 0 - .dw 0x6a81, 0xc415, 0x6a81, 0xc415, 0x21, 0 - .dw 0x6a83, 0xc415, 0x6a8f, 0xc415, 0x21, 0 - .dw 0x6a91, 0xc415, 0x6a91, 0xc415, 0x21, 0 - .dw 0x6a93, 0xc415, 0x6abf, 0xc415, 0x21, 0 - .dw 0x6ac1, 0xc415, 0x6ac1, 0xc415, 0x21, 0 - .dw 0x6ac3, 0xc415, 0x6acf, 0xc415, 0x21, 0 - .dw 0x6ad1, 0xc415, 0x6ad1, 0xc415, 0x21, 0 - .dw 0x6ad3, 0xc415, 0x6aff, 0xc415, 0x21, 0 - .dw 0x6b01, 0xc415, 0x6b01, 0xc415, 0x21, 0 - .dw 0x6b03, 0xc415, 0x6b0f, 0xc415, 0x21, 0 - .dw 0x6b11, 0xc415, 0x6b11, 0xc415, 0x21, 0 - .dw 0x6b13, 0xc415, 0x6b3f, 0xc415, 0x21, 0 - .dw 0x6b40, 0xc415, 0x6b40, 0xc415, 0x22, 0 - .dw 0x6b41, 0xc415, 0x6b41, 0xc415, 0x21, 0 - .dw 0x6b42, 0xc415, 0x6b42, 0xc415, 0x22, 0 - .dw 0x6b43, 0xc415, 0x6b4f, 0xc415, 0x21, 0 - .dw 0x6b50, 0xc415, 0x6b50, 0xc415, 0x22, 0 - .dw 0x6b51, 0xc415, 0x6b51, 0xc415, 0x21, 0 - .dw 0x6b52, 0xc415, 0x6b52, 0xc415, 0x22, 0 - .dw 0x6b53, 0xc415, 0x6b7f, 0xc415, 0x21, 0 - .dw 0x6b81, 0xc415, 0x6b81, 0xc415, 0x21, 0 - .dw 0x6b83, 0xc415, 0x6b8f, 0xc415, 0x21, 0 - .dw 0x6b91, 0xc415, 0x6b91, 0xc415, 0x21, 0 - .dw 0x6b93, 0xc415, 0x6bbf, 0xc415, 0x21, 0 - .dw 0x6bc1, 0xc415, 0x6bc1, 0xc415, 0x21, 0 - .dw 0x6bc3, 0xc415, 0x6bcf, 0xc415, 0x21, 0 - .dw 0x6bd1, 0xc415, 0x6bd1, 0xc415, 0x21, 0 - .dw 0x6bd3, 0xc415, 0x6bff, 0xc415, 0x21, 0 - .dw 0x6c01, 0xc415, 0x6c01, 0xc415, 0x21, 0 - .dw 0x6c03, 0xc415, 0x6c0f, 0xc415, 0x21, 0 - .dw 0x6c11, 0xc415, 0x6c11, 0xc415, 0x21, 0 - .dw 0x6c13, 0xc415, 0x6c3f, 0xc415, 0x21, 0 - .dw 0x6c41, 0xc415, 0x6c41, 0xc415, 0x21, 0 - .dw 0x6c43, 0xc415, 0x6c4f, 0xc415, 0x21, 0 - .dw 0x6c51, 0xc415, 0x6c51, 0xc415, 0x21, 0 - .dw 0x6c53, 0xc415, 0x6c7f, 0xc415, 0x21, 0 - .dw 0x6c81, 0xc415, 0x6c81, 0xc415, 0x21, 0 - .dw 0x6c83, 0xc415, 0x6c8f, 0xc415, 0x21, 0 - .dw 0x6c91, 0xc415, 0x6c91, 0xc415, 0x21, 0 - .dw 0x6c93, 0xc415, 0x6cbf, 0xc415, 0x21, 0 - .dw 0x6cc1, 0xc415, 0x6cc1, 0xc415, 0x21, 0 - .dw 0x6cc3, 0xc415, 0x6ccf, 0xc415, 0x21, 0 - .dw 0x6cd1, 0xc415, 0x6cd1, 0xc415, 0x21, 0 - .dw 0x6cd3, 0xc415, 0x6cff, 0xc415, 0x21, 0 - .dw 0x6d01, 0xc415, 0x6d01, 0xc415, 0x21, 0 - .dw 0x6d03, 0xc415, 0x6d0f, 0xc415, 0x21, 0 - .dw 0x6d11, 0xc415, 0x6d11, 0xc415, 0x21, 0 - .dw 0x6d13, 0xc415, 0x6d3f, 0xc415, 0x21, 0 - .dw 0x6d41, 0xc415, 0x6d41, 0xc415, 0x21, 0 - .dw 0x6d43, 0xc415, 0x6d4f, 0xc415, 0x21, 0 - .dw 0x6d51, 0xc415, 0x6d51, 0xc415, 0x21, 0 - .dw 0x6d53, 0xc415, 0x6d7f, 0xc415, 0x21, 0 - .dw 0x6d80, 0xc415, 0x6d80, 0xc415, 0x22, 0 - .dw 0x6d81, 0xc415, 0x6d81, 0xc415, 0x21, 0 - .dw 0x6d82, 0xc415, 0x6d82, 0xc415, 0x22, 0 - .dw 0x6d83, 0xc415, 0x6d8f, 0xc415, 0x21, 0 - .dw 0x6d90, 0xc415, 0x6d90, 0xc415, 0x22, 0 - .dw 0x6d91, 0xc415, 0x6d91, 0xc415, 0x21, 0 - .dw 0x6d92, 0xc415, 0x6d92, 0xc415, 0x22, 0 - .dw 0x6d93, 0xc415, 0x6dbf, 0xc415, 0x21, 0 - .dw 0x6dc1, 0xc415, 0x6dc1, 0xc415, 0x21, 0 - .dw 0x6dc3, 0xc415, 0x6dcf, 0xc415, 0x21, 0 - .dw 0x6dd1, 0xc415, 0x6dd1, 0xc415, 0x21, 0 - .dw 0x6dd3, 0xc415, 0x6dff, 0xc415, 0x21, 0 - .dw 0x6e01, 0xc415, 0x6e01, 0xc415, 0x21, 0 - .dw 0x6e03, 0xc415, 0x6e0f, 0xc415, 0x21, 0 - .dw 0x6e11, 0xc415, 0x6e11, 0xc415, 0x21, 0 - .dw 0x6e13, 0xc415, 0x6e3f, 0xc415, 0x21, 0 - .dw 0x6e41, 0xc415, 0x6e41, 0xc415, 0x21, 0 - .dw 0x6e43, 0xc415, 0x6e4f, 0xc415, 0x21, 0 - .dw 0x6e51, 0xc415, 0x6e51, 0xc415, 0x21, 0 - .dw 0x6e53, 0xc415, 0x6e7f, 0xc415, 0x21, 0 - .dw 0x6e81, 0xc415, 0x6e81, 0xc415, 0x21, 0 - .dw 0x6e83, 0xc415, 0x6e8f, 0xc415, 0x21, 0 - .dw 0x6e91, 0xc415, 0x6e91, 0xc415, 0x21, 0 - .dw 0x6e93, 0xc415, 0x6ebf, 0xc415, 0x21, 0 - .dw 0x6ec1, 0xc415, 0x6ec1, 0xc415, 0x21, 0 - .dw 0x6ec3, 0xc415, 0x6ecf, 0xc415, 0x21, 0 - .dw 0x6ed1, 0xc415, 0x6ed1, 0xc415, 0x21, 0 - .dw 0x6ed3, 0xc415, 0x6eff, 0xc415, 0x21, 0 - .dw 0x6f01, 0xc415, 0x6f01, 0xc415, 0x21, 0 - .dw 0x6f03, 0xc415, 0x6f0f, 0xc415, 0x21, 0 - .dw 0x6f11, 0xc415, 0x6f11, 0xc415, 0x21, 0 - .dw 0x6f13, 0xc415, 0x6f3f, 0xc415, 0x21, 0 - .dw 0x6f41, 0xc415, 0x6f41, 0xc415, 0x21, 0 - .dw 0x6f43, 0xc415, 0x6f4f, 0xc415, 0x21, 0 - .dw 0x6f51, 0xc415, 0x6f51, 0xc415, 0x21, 0 - .dw 0x6f53, 0xc415, 0x6f7f, 0xc415, 0x21, 0 - .dw 0x6f81, 0xc415, 0x6f81, 0xc415, 0x21, 0 - .dw 0x6f83, 0xc415, 0x6f8f, 0xc415, 0x21, 0 - .dw 0x6f91, 0xc415, 0x6f91, 0xc415, 0x21, 0 - .dw 0x6f93, 0xc415, 0x6fbf, 0xc415, 0x21, 0 - .dw 0x6fc0, 0xc415, 0x6fc0, 0xc415, 0x22, 0 - .dw 0x6fc1, 0xc415, 0x6fc1, 0xc415, 0x21, 0 - .dw 0x6fc2, 0xc415, 0x6fc2, 0xc415, 0x22, 0 - .dw 0x6fc3, 0xc415, 0x6fcf, 0xc415, 0x21, 0 - .dw 0x6fd0, 0xc415, 0x6fd0, 0xc415, 0x22, 0 - .dw 0x6fd1, 0xc415, 0x6fd1, 0xc415, 0x21, 0 - .dw 0x6fd2, 0xc415, 0x6fd2, 0xc415, 0x22, 0 - .dw 0x6fd3, 0xc415, 0xffff, 0xc415, 0x21, 0 - .dw 0x0001, 0xc416, 0x0001, 0xc416, 0x21, 0 - .dw 0x0003, 0xc416, 0x000f, 0xc416, 0x21, 0 - .dw 0x0011, 0xc416, 0x0011, 0xc416, 0x21, 0 - .dw 0x0013, 0xc416, 0x003f, 0xc416, 0x21, 0 - .dw 0x0041, 0xc416, 0x0041, 0xc416, 0x21, 0 - .dw 0x0043, 0xc416, 0x004f, 0xc416, 0x21, 0 - .dw 0x0051, 0xc416, 0x0051, 0xc416, 0x21, 0 - .dw 0x0053, 0xc416, 0x007f, 0xc416, 0x21, 0 - .dw 0x0081, 0xc416, 0x0081, 0xc416, 0x21, 0 - .dw 0x0083, 0xc416, 0x008f, 0xc416, 0x21, 0 - .dw 0x0091, 0xc416, 0x0091, 0xc416, 0x21, 0 - .dw 0x0093, 0xc416, 0x00bf, 0xc416, 0x21, 0 - .dw 0x00c1, 0xc416, 0x00c1, 0xc416, 0x21, 0 - .dw 0x00c3, 0xc416, 0x00cf, 0xc416, 0x21, 0 - .dw 0x00d1, 0xc416, 0x00d1, 0xc416, 0x21, 0 - .dw 0x00d3, 0xc416, 0x00ff, 0xc416, 0x21, 0 - .dw 0x0101, 0xc416, 0x0101, 0xc416, 0x21, 0 - .dw 0x0103, 0xc416, 0x010f, 0xc416, 0x21, 0 - .dw 0x0111, 0xc416, 0x0111, 0xc416, 0x21, 0 - .dw 0x0113, 0xc416, 0x013f, 0xc416, 0x21, 0 - .dw 0x0141, 0xc416, 0x0141, 0xc416, 0x21, 0 - .dw 0x0143, 0xc416, 0x014f, 0xc416, 0x21, 0 - .dw 0x0151, 0xc416, 0x0151, 0xc416, 0x21, 0 - .dw 0x0153, 0xc416, 0x017f, 0xc416, 0x21, 0 - .dw 0x0181, 0xc416, 0x0181, 0xc416, 0x21, 0 - .dw 0x0183, 0xc416, 0x018f, 0xc416, 0x21, 0 - .dw 0x0191, 0xc416, 0x0191, 0xc416, 0x21, 0 - .dw 0x0193, 0xc416, 0x01bf, 0xc416, 0x21, 0 - .dw 0x01c1, 0xc416, 0x01c1, 0xc416, 0x21, 0 - .dw 0x01c3, 0xc416, 0x01cf, 0xc416, 0x21, 0 - .dw 0x01d1, 0xc416, 0x01d1, 0xc416, 0x21, 0 - .dw 0x01d3, 0xc416, 0x01ff, 0xc416, 0x21, 0 - .dw 0x0201, 0xc416, 0x0201, 0xc416, 0x21, 0 - .dw 0x0203, 0xc416, 0x020f, 0xc416, 0x21, 0 - .dw 0x0211, 0xc416, 0x0211, 0xc416, 0x21, 0 - .dw 0x0213, 0xc416, 0x023f, 0xc416, 0x21, 0 - .dw 0x0241, 0xc416, 0x0241, 0xc416, 0x21, 0 - .dw 0x0243, 0xc416, 0x024f, 0xc416, 0x21, 0 - .dw 0x0251, 0xc416, 0x0251, 0xc416, 0x21, 0 - .dw 0x0253, 0xc416, 0x027f, 0xc416, 0x21, 0 - .dw 0x0281, 0xc416, 0x0281, 0xc416, 0x21, 0 - .dw 0x0283, 0xc416, 0x028f, 0xc416, 0x21, 0 - .dw 0x0291, 0xc416, 0x0291, 0xc416, 0x21, 0 - .dw 0x0293, 0xc416, 0x02bf, 0xc416, 0x21, 0 - .dw 0x02c1, 0xc416, 0x02c1, 0xc416, 0x21, 0 - .dw 0x02c3, 0xc416, 0x02cf, 0xc416, 0x21, 0 - .dw 0x02d1, 0xc416, 0x02d1, 0xc416, 0x21, 0 - .dw 0x02d3, 0xc416, 0x02ff, 0xc416, 0x21, 0 - .dw 0x0301, 0xc416, 0x0301, 0xc416, 0x21, 0 - .dw 0x0303, 0xc416, 0x030f, 0xc416, 0x21, 0 - .dw 0x0311, 0xc416, 0x0311, 0xc416, 0x21, 0 - .dw 0x0313, 0xc416, 0x033f, 0xc416, 0x21, 0 - .dw 0x0341, 0xc416, 0x0341, 0xc416, 0x21, 0 - .dw 0x0343, 0xc416, 0x034f, 0xc416, 0x21, 0 - .dw 0x0351, 0xc416, 0x0351, 0xc416, 0x21, 0 - .dw 0x0353, 0xc416, 0x037f, 0xc416, 0x21, 0 - .dw 0x0381, 0xc416, 0x0381, 0xc416, 0x21, 0 - .dw 0x0383, 0xc416, 0x038f, 0xc416, 0x21, 0 - .dw 0x0391, 0xc416, 0x0391, 0xc416, 0x21, 0 - .dw 0x0393, 0xc416, 0x03bf, 0xc416, 0x21, 0 - .dw 0x03c1, 0xc416, 0x03c1, 0xc416, 0x21, 0 - .dw 0x03c3, 0xc416, 0x03cf, 0xc416, 0x21, 0 - .dw 0x03d1, 0xc416, 0x03d1, 0xc416, 0x21, 0 - .dw 0x03d3, 0xc416, 0x03ff, 0xc416, 0x21, 0 - .dw 0x0401, 0xc416, 0x0401, 0xc416, 0x21, 0 - .dw 0x0403, 0xc416, 0x040f, 0xc416, 0x21, 0 - .dw 0x0411, 0xc416, 0x0411, 0xc416, 0x21, 0 - .dw 0x0413, 0xc416, 0x043f, 0xc416, 0x21, 0 - .dw 0x0441, 0xc416, 0x0441, 0xc416, 0x21, 0 - .dw 0x0443, 0xc416, 0x044f, 0xc416, 0x21, 0 - .dw 0x0451, 0xc416, 0x0451, 0xc416, 0x21, 0 - .dw 0x0453, 0xc416, 0x047f, 0xc416, 0x21, 0 - .dw 0x0481, 0xc416, 0x0481, 0xc416, 0x21, 0 - .dw 0x0483, 0xc416, 0x048f, 0xc416, 0x21, 0 - .dw 0x0491, 0xc416, 0x0491, 0xc416, 0x21, 0 - .dw 0x0493, 0xc416, 0x04bf, 0xc416, 0x21, 0 - .dw 0x04c1, 0xc416, 0x04c1, 0xc416, 0x21, 0 - .dw 0x04c3, 0xc416, 0x04cf, 0xc416, 0x21, 0 - .dw 0x04d1, 0xc416, 0x04d1, 0xc416, 0x21, 0 - .dw 0x04d3, 0xc416, 0x04ff, 0xc416, 0x21, 0 - .dw 0x0501, 0xc416, 0x0501, 0xc416, 0x21, 0 - .dw 0x0503, 0xc416, 0x050f, 0xc416, 0x21, 0 - .dw 0x0511, 0xc416, 0x0511, 0xc416, 0x21, 0 - .dw 0x0513, 0xc416, 0x053f, 0xc416, 0x21, 0 - .dw 0x0541, 0xc416, 0x0541, 0xc416, 0x21, 0 - .dw 0x0543, 0xc416, 0x054f, 0xc416, 0x21, 0 - .dw 0x0551, 0xc416, 0x0551, 0xc416, 0x21, 0 - .dw 0x0553, 0xc416, 0x057f, 0xc416, 0x21, 0 - .dw 0x0581, 0xc416, 0x0581, 0xc416, 0x21, 0 - .dw 0x0583, 0xc416, 0x058f, 0xc416, 0x21, 0 - .dw 0x0591, 0xc416, 0x0591, 0xc416, 0x21, 0 - .dw 0x0593, 0xc416, 0x05bf, 0xc416, 0x21, 0 - .dw 0x05c1, 0xc416, 0x05c1, 0xc416, 0x21, 0 - .dw 0x05c3, 0xc416, 0x05cf, 0xc416, 0x21, 0 - .dw 0x05d1, 0xc416, 0x05d1, 0xc416, 0x21, 0 - .dw 0x05d3, 0xc416, 0x05ff, 0xc416, 0x21, 0 - .dw 0x0601, 0xc416, 0x0601, 0xc416, 0x21, 0 - .dw 0x0603, 0xc416, 0x060f, 0xc416, 0x21, 0 - .dw 0x0611, 0xc416, 0x0611, 0xc416, 0x21, 0 - .dw 0x0613, 0xc416, 0x063f, 0xc416, 0x21, 0 - .dw 0x0641, 0xc416, 0x0641, 0xc416, 0x21, 0 - .dw 0x0643, 0xc416, 0x064f, 0xc416, 0x21, 0 - .dw 0x0651, 0xc416, 0x0651, 0xc416, 0x21, 0 - .dw 0x0653, 0xc416, 0x067f, 0xc416, 0x21, 0 - .dw 0x0681, 0xc416, 0x0681, 0xc416, 0x21, 0 - .dw 0x0683, 0xc416, 0x068f, 0xc416, 0x21, 0 - .dw 0x0691, 0xc416, 0x0691, 0xc416, 0x21, 0 - .dw 0x0693, 0xc416, 0x06bf, 0xc416, 0x21, 0 - .dw 0x06c1, 0xc416, 0x06c1, 0xc416, 0x21, 0 - .dw 0x06c3, 0xc416, 0x06cf, 0xc416, 0x21, 0 - .dw 0x06d1, 0xc416, 0x06d1, 0xc416, 0x21, 0 - .dw 0x06d3, 0xc416, 0x06ff, 0xc416, 0x21, 0 - .dw 0x0701, 0xc416, 0x0701, 0xc416, 0x21, 0 - .dw 0x0703, 0xc416, 0x070f, 0xc416, 0x21, 0 - .dw 0x0711, 0xc416, 0x0711, 0xc416, 0x21, 0 - .dw 0x0713, 0xc416, 0x073f, 0xc416, 0x21, 0 - .dw 0x0741, 0xc416, 0x0741, 0xc416, 0x21, 0 - .dw 0x0743, 0xc416, 0x074f, 0xc416, 0x21, 0 - .dw 0x0751, 0xc416, 0x0751, 0xc416, 0x21, 0 - .dw 0x0753, 0xc416, 0x077f, 0xc416, 0x21, 0 - .dw 0x0781, 0xc416, 0x0781, 0xc416, 0x21, 0 - .dw 0x0783, 0xc416, 0x078f, 0xc416, 0x21, 0 - .dw 0x0791, 0xc416, 0x0791, 0xc416, 0x21, 0 - .dw 0x0793, 0xc416, 0x07bf, 0xc416, 0x21, 0 - .dw 0x07c1, 0xc416, 0x07c1, 0xc416, 0x21, 0 - .dw 0x07c3, 0xc416, 0x07cf, 0xc416, 0x21, 0 - .dw 0x07d1, 0xc416, 0x07d1, 0xc416, 0x21, 0 - .dw 0x07d3, 0xc416, 0x07ff, 0xc416, 0x21, 0 - .dw 0x0801, 0xc416, 0x0801, 0xc416, 0x21, 0 - .dw 0x0803, 0xc416, 0x080f, 0xc416, 0x21, 0 - .dw 0x0811, 0xc416, 0x0811, 0xc416, 0x21, 0 - .dw 0x0813, 0xc416, 0x083f, 0xc416, 0x21, 0 - .dw 0x0841, 0xc416, 0x0841, 0xc416, 0x21, 0 - .dw 0x0843, 0xc416, 0x084f, 0xc416, 0x21, 0 - .dw 0x0851, 0xc416, 0x0851, 0xc416, 0x21, 0 - .dw 0x0853, 0xc416, 0x087f, 0xc416, 0x21, 0 - .dw 0x0881, 0xc416, 0x0881, 0xc416, 0x21, 0 - .dw 0x0883, 0xc416, 0x088f, 0xc416, 0x21, 0 - .dw 0x0891, 0xc416, 0x0891, 0xc416, 0x21, 0 - .dw 0x0893, 0xc416, 0x08bf, 0xc416, 0x21, 0 - .dw 0x08c1, 0xc416, 0x08c1, 0xc416, 0x21, 0 - .dw 0x08c3, 0xc416, 0x08cf, 0xc416, 0x21, 0 - .dw 0x08d1, 0xc416, 0x08d1, 0xc416, 0x21, 0 - .dw 0x08d3, 0xc416, 0x08ff, 0xc416, 0x21, 0 - .dw 0x0901, 0xc416, 0x0901, 0xc416, 0x21, 0 - .dw 0x0903, 0xc416, 0x090f, 0xc416, 0x21, 0 - .dw 0x0911, 0xc416, 0x0911, 0xc416, 0x21, 0 - .dw 0x0913, 0xc416, 0x093f, 0xc416, 0x21, 0 - .dw 0x0941, 0xc416, 0x0941, 0xc416, 0x21, 0 - .dw 0x0943, 0xc416, 0x094f, 0xc416, 0x21, 0 - .dw 0x0951, 0xc416, 0x0951, 0xc416, 0x21, 0 - .dw 0x0953, 0xc416, 0x097f, 0xc416, 0x21, 0 - .dw 0x0981, 0xc416, 0x0981, 0xc416, 0x21, 0 - .dw 0x0983, 0xc416, 0x098f, 0xc416, 0x21, 0 - .dw 0x0991, 0xc416, 0x0991, 0xc416, 0x21, 0 - .dw 0x0993, 0xc416, 0x09bf, 0xc416, 0x21, 0 - .dw 0x09c1, 0xc416, 0x09c1, 0xc416, 0x21, 0 - .dw 0x09c3, 0xc416, 0x09cf, 0xc416, 0x21, 0 - .dw 0x09d1, 0xc416, 0x09d1, 0xc416, 0x21, 0 - .dw 0x09d3, 0xc416, 0x09ff, 0xc416, 0x21, 0 - .dw 0x0a01, 0xc416, 0x0a01, 0xc416, 0x21, 0 - .dw 0x0a03, 0xc416, 0x0a0f, 0xc416, 0x21, 0 - .dw 0x0a11, 0xc416, 0x0a11, 0xc416, 0x21, 0 - .dw 0x0a13, 0xc416, 0x0a3f, 0xc416, 0x21, 0 - .dw 0x0a41, 0xc416, 0x0a41, 0xc416, 0x21, 0 - .dw 0x0a43, 0xc416, 0x0a4f, 0xc416, 0x21, 0 - .dw 0x0a51, 0xc416, 0x0a51, 0xc416, 0x21, 0 - .dw 0x0a53, 0xc416, 0x0a7f, 0xc416, 0x21, 0 - .dw 0x0a81, 0xc416, 0x0a81, 0xc416, 0x21, 0 - .dw 0x0a83, 0xc416, 0x0a8f, 0xc416, 0x21, 0 - .dw 0x0a91, 0xc416, 0x0a91, 0xc416, 0x21, 0 - .dw 0x0a93, 0xc416, 0x0abf, 0xc416, 0x21, 0 - .dw 0x0ac1, 0xc416, 0x0ac1, 0xc416, 0x21, 0 - .dw 0x0ac3, 0xc416, 0x0acf, 0xc416, 0x21, 0 - .dw 0x0ad1, 0xc416, 0x0ad1, 0xc416, 0x21, 0 - .dw 0x0ad3, 0xc416, 0x0aff, 0xc416, 0x21, 0 - .dw 0x0b01, 0xc416, 0x0b01, 0xc416, 0x21, 0 - .dw 0x0b03, 0xc416, 0x0b0f, 0xc416, 0x21, 0 - .dw 0x0b11, 0xc416, 0x0b11, 0xc416, 0x21, 0 - .dw 0x0b13, 0xc416, 0x0b3f, 0xc416, 0x21, 0 - .dw 0x0b41, 0xc416, 0x0b41, 0xc416, 0x21, 0 - .dw 0x0b43, 0xc416, 0x0b4f, 0xc416, 0x21, 0 - .dw 0x0b51, 0xc416, 0x0b51, 0xc416, 0x21, 0 - .dw 0x0b53, 0xc416, 0x0b7f, 0xc416, 0x21, 0 - .dw 0x0b81, 0xc416, 0x0b81, 0xc416, 0x21, 0 - .dw 0x0b83, 0xc416, 0x0b8f, 0xc416, 0x21, 0 - .dw 0x0b91, 0xc416, 0x0b91, 0xc416, 0x21, 0 - .dw 0x0b93, 0xc416, 0x0bbf, 0xc416, 0x21, 0 - .dw 0x0bc1, 0xc416, 0x0bc1, 0xc416, 0x21, 0 - .dw 0x0bc3, 0xc416, 0x0bcf, 0xc416, 0x21, 0 - .dw 0x0bd1, 0xc416, 0x0bd1, 0xc416, 0x21, 0 - .dw 0x0bd3, 0xc416, 0x0bff, 0xc416, 0x21, 0 - .dw 0x0c01, 0xc416, 0x0c01, 0xc416, 0x21, 0 - .dw 0x0c03, 0xc416, 0x0c0f, 0xc416, 0x21, 0 - .dw 0x0c11, 0xc416, 0x0c11, 0xc416, 0x21, 0 - .dw 0x0c13, 0xc416, 0x0c3f, 0xc416, 0x21, 0 - .dw 0x0c41, 0xc416, 0x0c41, 0xc416, 0x21, 0 - .dw 0x0c43, 0xc416, 0x0c4f, 0xc416, 0x21, 0 - .dw 0x0c51, 0xc416, 0x0c51, 0xc416, 0x21, 0 - .dw 0x0c53, 0xc416, 0x0c7f, 0xc416, 0x21, 0 - .dw 0x0c81, 0xc416, 0x0c81, 0xc416, 0x21, 0 - .dw 0x0c83, 0xc416, 0x0c8f, 0xc416, 0x21, 0 - .dw 0x0c91, 0xc416, 0x0c91, 0xc416, 0x21, 0 - .dw 0x0c93, 0xc416, 0x0cbf, 0xc416, 0x21, 0 - .dw 0x0cc1, 0xc416, 0x0cc1, 0xc416, 0x21, 0 - .dw 0x0cc3, 0xc416, 0x0ccf, 0xc416, 0x21, 0 - .dw 0x0cd1, 0xc416, 0x0cd1, 0xc416, 0x21, 0 - .dw 0x0cd3, 0xc416, 0x0cff, 0xc416, 0x21, 0 - .dw 0x0d01, 0xc416, 0x0d01, 0xc416, 0x21, 0 - .dw 0x0d03, 0xc416, 0x0d0f, 0xc416, 0x21, 0 - .dw 0x0d11, 0xc416, 0x0d11, 0xc416, 0x21, 0 - .dw 0x0d13, 0xc416, 0x0d3f, 0xc416, 0x21, 0 - .dw 0x0d41, 0xc416, 0x0d41, 0xc416, 0x21, 0 - .dw 0x0d43, 0xc416, 0x0d4f, 0xc416, 0x21, 0 - .dw 0x0d51, 0xc416, 0x0d51, 0xc416, 0x21, 0 - .dw 0x0d53, 0xc416, 0x0d7f, 0xc416, 0x21, 0 - .dw 0x0d81, 0xc416, 0x0d81, 0xc416, 0x21, 0 - .dw 0x0d83, 0xc416, 0x0d8f, 0xc416, 0x21, 0 - .dw 0x0d91, 0xc416, 0x0d91, 0xc416, 0x21, 0 - .dw 0x0d93, 0xc416, 0x0dbf, 0xc416, 0x21, 0 - .dw 0x0dc1, 0xc416, 0x0dc1, 0xc416, 0x21, 0 - .dw 0x0dc3, 0xc416, 0x0dcf, 0xc416, 0x21, 0 - .dw 0x0dd1, 0xc416, 0x0dd1, 0xc416, 0x21, 0 - .dw 0x0dd3, 0xc416, 0x0dff, 0xc416, 0x21, 0 - .dw 0x0e01, 0xc416, 0x0e01, 0xc416, 0x21, 0 - .dw 0x0e03, 0xc416, 0x0e0f, 0xc416, 0x21, 0 - .dw 0x0e11, 0xc416, 0x0e11, 0xc416, 0x21, 0 - .dw 0x0e13, 0xc416, 0x0e3f, 0xc416, 0x21, 0 - .dw 0x0e41, 0xc416, 0x0e41, 0xc416, 0x21, 0 - .dw 0x0e43, 0xc416, 0x0e4f, 0xc416, 0x21, 0 - .dw 0x0e51, 0xc416, 0x0e51, 0xc416, 0x21, 0 - .dw 0x0e53, 0xc416, 0x0e7f, 0xc416, 0x21, 0 - .dw 0x0e81, 0xc416, 0x0e81, 0xc416, 0x21, 0 - .dw 0x0e83, 0xc416, 0x0e8f, 0xc416, 0x21, 0 - .dw 0x0e91, 0xc416, 0x0e91, 0xc416, 0x21, 0 - .dw 0x0e93, 0xc416, 0x0ebf, 0xc416, 0x21, 0 - .dw 0x0ec1, 0xc416, 0x0ec1, 0xc416, 0x21, 0 - .dw 0x0ec3, 0xc416, 0x0ecf, 0xc416, 0x21, 0 - .dw 0x0ed1, 0xc416, 0x0ed1, 0xc416, 0x21, 0 - .dw 0x0ed3, 0xc416, 0x0eff, 0xc416, 0x21, 0 - .dw 0x0f01, 0xc416, 0x0f01, 0xc416, 0x21, 0 - .dw 0x0f03, 0xc416, 0x0f0f, 0xc416, 0x21, 0 - .dw 0x0f11, 0xc416, 0x0f11, 0xc416, 0x21, 0 - .dw 0x0f13, 0xc416, 0x0f3f, 0xc416, 0x21, 0 - .dw 0x0f41, 0xc416, 0x0f41, 0xc416, 0x21, 0 - .dw 0x0f43, 0xc416, 0x0f4f, 0xc416, 0x21, 0 - .dw 0x0f51, 0xc416, 0x0f51, 0xc416, 0x21, 0 - .dw 0x0f53, 0xc416, 0x0f7f, 0xc416, 0x21, 0 - .dw 0x0f81, 0xc416, 0x0f81, 0xc416, 0x21, 0 - .dw 0x0f83, 0xc416, 0x0f8f, 0xc416, 0x21, 0 - .dw 0x0f91, 0xc416, 0x0f91, 0xc416, 0x21, 0 - .dw 0x0f93, 0xc416, 0x0fbf, 0xc416, 0x21, 0 - .dw 0x0fc1, 0xc416, 0x0fc1, 0xc416, 0x21, 0 - .dw 0x0fc3, 0xc416, 0x0fcf, 0xc416, 0x21, 0 - .dw 0x0fd1, 0xc416, 0x0fd1, 0xc416, 0x21, 0 - .dw 0x0fd3, 0xc416, 0x1fff, 0xc416, 0x21, 0 - .dw 0x2001, 0xc416, 0x2001, 0xc416, 0x21, 0 - .dw 0x2003, 0xc416, 0x200f, 0xc416, 0x21, 0 - .dw 0x2011, 0xc416, 0x2011, 0xc416, 0x21, 0 - .dw 0x2013, 0xc416, 0x203f, 0xc416, 0x21, 0 - .dw 0x2041, 0xc416, 0x2041, 0xc416, 0x21, 0 - .dw 0x2043, 0xc416, 0x204f, 0xc416, 0x21, 0 - .dw 0x2051, 0xc416, 0x2051, 0xc416, 0x21, 0 - .dw 0x2053, 0xc416, 0x207f, 0xc416, 0x21, 0 - .dw 0x2081, 0xc416, 0x2081, 0xc416, 0x21, 0 - .dw 0x2083, 0xc416, 0x208f, 0xc416, 0x21, 0 - .dw 0x2091, 0xc416, 0x2091, 0xc416, 0x21, 0 - .dw 0x2093, 0xc416, 0x20bf, 0xc416, 0x21, 0 - .dw 0x20c1, 0xc416, 0x20c1, 0xc416, 0x21, 0 - .dw 0x20c3, 0xc416, 0x20cf, 0xc416, 0x21, 0 - .dw 0x20d1, 0xc416, 0x20d1, 0xc416, 0x21, 0 - .dw 0x20d3, 0xc416, 0x20ff, 0xc416, 0x21, 0 - .dw 0x2101, 0xc416, 0x2101, 0xc416, 0x21, 0 - .dw 0x2103, 0xc416, 0x210f, 0xc416, 0x21, 0 - .dw 0x2111, 0xc416, 0x2111, 0xc416, 0x21, 0 - .dw 0x2113, 0xc416, 0x213f, 0xc416, 0x21, 0 - .dw 0x2141, 0xc416, 0x2141, 0xc416, 0x21, 0 - .dw 0x2143, 0xc416, 0x214f, 0xc416, 0x21, 0 - .dw 0x2151, 0xc416, 0x2151, 0xc416, 0x21, 0 - .dw 0x2153, 0xc416, 0x217f, 0xc416, 0x21, 0 - .dw 0x2181, 0xc416, 0x2181, 0xc416, 0x21, 0 - .dw 0x2183, 0xc416, 0x218f, 0xc416, 0x21, 0 - .dw 0x2191, 0xc416, 0x2191, 0xc416, 0x21, 0 - .dw 0x2193, 0xc416, 0x21bf, 0xc416, 0x21, 0 - .dw 0x21c1, 0xc416, 0x21c1, 0xc416, 0x21, 0 - .dw 0x21c3, 0xc416, 0x21cf, 0xc416, 0x21, 0 - .dw 0x21d1, 0xc416, 0x21d1, 0xc416, 0x21, 0 - .dw 0x21d3, 0xc416, 0x21ff, 0xc416, 0x21, 0 - .dw 0x2201, 0xc416, 0x2201, 0xc416, 0x21, 0 - .dw 0x2203, 0xc416, 0x220f, 0xc416, 0x21, 0 - .dw 0x2211, 0xc416, 0x2211, 0xc416, 0x21, 0 - .dw 0x2213, 0xc416, 0x223f, 0xc416, 0x21, 0 - .dw 0x2241, 0xc416, 0x2241, 0xc416, 0x21, 0 - .dw 0x2243, 0xc416, 0x224f, 0xc416, 0x21, 0 - .dw 0x2251, 0xc416, 0x2251, 0xc416, 0x21, 0 - .dw 0x2253, 0xc416, 0x227f, 0xc416, 0x21, 0 - .dw 0x2281, 0xc416, 0x2281, 0xc416, 0x21, 0 - .dw 0x2283, 0xc416, 0x228f, 0xc416, 0x21, 0 - .dw 0x2291, 0xc416, 0x2291, 0xc416, 0x21, 0 - .dw 0x2293, 0xc416, 0x22bf, 0xc416, 0x21, 0 - .dw 0x22c1, 0xc416, 0x22c1, 0xc416, 0x21, 0 - .dw 0x22c3, 0xc416, 0x22cf, 0xc416, 0x21, 0 - .dw 0x22d1, 0xc416, 0x22d1, 0xc416, 0x21, 0 - .dw 0x22d3, 0xc416, 0x22ff, 0xc416, 0x21, 0 - .dw 0x2301, 0xc416, 0x2301, 0xc416, 0x21, 0 - .dw 0x2303, 0xc416, 0x230f, 0xc416, 0x21, 0 - .dw 0x2311, 0xc416, 0x2311, 0xc416, 0x21, 0 - .dw 0x2313, 0xc416, 0x233f, 0xc416, 0x21, 0 - .dw 0x2341, 0xc416, 0x2341, 0xc416, 0x21, 0 - .dw 0x2343, 0xc416, 0x234f, 0xc416, 0x21, 0 - .dw 0x2351, 0xc416, 0x2351, 0xc416, 0x21, 0 - .dw 0x2353, 0xc416, 0x237f, 0xc416, 0x21, 0 - .dw 0x2381, 0xc416, 0x2381, 0xc416, 0x21, 0 - .dw 0x2383, 0xc416, 0x238f, 0xc416, 0x21, 0 - .dw 0x2391, 0xc416, 0x2391, 0xc416, 0x21, 0 - .dw 0x2393, 0xc416, 0x23bf, 0xc416, 0x21, 0 - .dw 0x23c1, 0xc416, 0x23c1, 0xc416, 0x21, 0 - .dw 0x23c3, 0xc416, 0x23cf, 0xc416, 0x21, 0 - .dw 0x23d1, 0xc416, 0x23d1, 0xc416, 0x21, 0 - .dw 0x23d3, 0xc416, 0x23ff, 0xc416, 0x21, 0 - .dw 0x2401, 0xc416, 0x2401, 0xc416, 0x21, 0 - .dw 0x2403, 0xc416, 0x240f, 0xc416, 0x21, 0 - .dw 0x2411, 0xc416, 0x2411, 0xc416, 0x21, 0 - .dw 0x2413, 0xc416, 0x243f, 0xc416, 0x21, 0 - .dw 0x2441, 0xc416, 0x2441, 0xc416, 0x21, 0 - .dw 0x2443, 0xc416, 0x244f, 0xc416, 0x21, 0 - .dw 0x2451, 0xc416, 0x2451, 0xc416, 0x21, 0 - .dw 0x2453, 0xc416, 0x247f, 0xc416, 0x21, 0 - .dw 0x2481, 0xc416, 0x2481, 0xc416, 0x21, 0 - .dw 0x2483, 0xc416, 0x248f, 0xc416, 0x21, 0 - .dw 0x2491, 0xc416, 0x2491, 0xc416, 0x21, 0 - .dw 0x2493, 0xc416, 0x24bf, 0xc416, 0x21, 0 - .dw 0x24c1, 0xc416, 0x24c1, 0xc416, 0x21, 0 - .dw 0x24c3, 0xc416, 0x24cf, 0xc416, 0x21, 0 - .dw 0x24d1, 0xc416, 0x24d1, 0xc416, 0x21, 0 - .dw 0x24d3, 0xc416, 0x24ff, 0xc416, 0x21, 0 - .dw 0x2501, 0xc416, 0x2501, 0xc416, 0x21, 0 - .dw 0x2503, 0xc416, 0x250f, 0xc416, 0x21, 0 - .dw 0x2511, 0xc416, 0x2511, 0xc416, 0x21, 0 - .dw 0x2513, 0xc416, 0x253f, 0xc416, 0x21, 0 - .dw 0x2541, 0xc416, 0x2541, 0xc416, 0x21, 0 - .dw 0x2543, 0xc416, 0x254f, 0xc416, 0x21, 0 - .dw 0x2551, 0xc416, 0x2551, 0xc416, 0x21, 0 - .dw 0x2553, 0xc416, 0x257f, 0xc416, 0x21, 0 - .dw 0x2581, 0xc416, 0x2581, 0xc416, 0x21, 0 - .dw 0x2583, 0xc416, 0x258f, 0xc416, 0x21, 0 - .dw 0x2591, 0xc416, 0x2591, 0xc416, 0x21, 0 - .dw 0x2593, 0xc416, 0x25bf, 0xc416, 0x21, 0 - .dw 0x25c1, 0xc416, 0x25c1, 0xc416, 0x21, 0 - .dw 0x25c3, 0xc416, 0x25cf, 0xc416, 0x21, 0 - .dw 0x25d1, 0xc416, 0x25d1, 0xc416, 0x21, 0 - .dw 0x25d3, 0xc416, 0x25ff, 0xc416, 0x21, 0 - .dw 0x2601, 0xc416, 0x2601, 0xc416, 0x21, 0 - .dw 0x2603, 0xc416, 0x260f, 0xc416, 0x21, 0 - .dw 0x2611, 0xc416, 0x2611, 0xc416, 0x21, 0 - .dw 0x2613, 0xc416, 0x263f, 0xc416, 0x21, 0 - .dw 0x2641, 0xc416, 0x2641, 0xc416, 0x21, 0 - .dw 0x2643, 0xc416, 0x264f, 0xc416, 0x21, 0 - .dw 0x2651, 0xc416, 0x2651, 0xc416, 0x21, 0 - .dw 0x2653, 0xc416, 0x267f, 0xc416, 0x21, 0 - .dw 0x2681, 0xc416, 0x2681, 0xc416, 0x21, 0 - .dw 0x2683, 0xc416, 0x268f, 0xc416, 0x21, 0 - .dw 0x2691, 0xc416, 0x2691, 0xc416, 0x21, 0 - .dw 0x2693, 0xc416, 0x26bf, 0xc416, 0x21, 0 - .dw 0x26c1, 0xc416, 0x26c1, 0xc416, 0x21, 0 - .dw 0x26c3, 0xc416, 0x26cf, 0xc416, 0x21, 0 - .dw 0x26d1, 0xc416, 0x26d1, 0xc416, 0x21, 0 - .dw 0x26d3, 0xc416, 0x26ff, 0xc416, 0x21, 0 - .dw 0x2701, 0xc416, 0x2701, 0xc416, 0x21, 0 - .dw 0x2703, 0xc416, 0x270f, 0xc416, 0x21, 0 - .dw 0x2711, 0xc416, 0x2711, 0xc416, 0x21, 0 - .dw 0x2713, 0xc416, 0x273f, 0xc416, 0x21, 0 - .dw 0x2741, 0xc416, 0x2741, 0xc416, 0x21, 0 - .dw 0x2743, 0xc416, 0x274f, 0xc416, 0x21, 0 - .dw 0x2751, 0xc416, 0x2751, 0xc416, 0x21, 0 - .dw 0x2753, 0xc416, 0x277f, 0xc416, 0x21, 0 - .dw 0x2781, 0xc416, 0x2781, 0xc416, 0x21, 0 - .dw 0x2783, 0xc416, 0x278f, 0xc416, 0x21, 0 - .dw 0x2791, 0xc416, 0x2791, 0xc416, 0x21, 0 - .dw 0x2793, 0xc416, 0x27bf, 0xc416, 0x21, 0 - .dw 0x27c1, 0xc416, 0x27c1, 0xc416, 0x21, 0 - .dw 0x27c3, 0xc416, 0x27cf, 0xc416, 0x21, 0 - .dw 0x27d1, 0xc416, 0x27d1, 0xc416, 0x21, 0 - .dw 0x27d3, 0xc416, 0x27ff, 0xc416, 0x21, 0 - .dw 0x2801, 0xc416, 0x2801, 0xc416, 0x21, 0 - .dw 0x2803, 0xc416, 0x280f, 0xc416, 0x21, 0 - .dw 0x2811, 0xc416, 0x2811, 0xc416, 0x21, 0 - .dw 0x2813, 0xc416, 0x283f, 0xc416, 0x21, 0 - .dw 0x2841, 0xc416, 0x2841, 0xc416, 0x21, 0 - .dw 0x2843, 0xc416, 0x284f, 0xc416, 0x21, 0 - .dw 0x2851, 0xc416, 0x2851, 0xc416, 0x21, 0 - .dw 0x2853, 0xc416, 0x287f, 0xc416, 0x21, 0 - .dw 0x2881, 0xc416, 0x2881, 0xc416, 0x21, 0 - .dw 0x2883, 0xc416, 0x288f, 0xc416, 0x21, 0 - .dw 0x2891, 0xc416, 0x2891, 0xc416, 0x21, 0 - .dw 0x2893, 0xc416, 0x28bf, 0xc416, 0x21, 0 - .dw 0x28c1, 0xc416, 0x28c1, 0xc416, 0x21, 0 - .dw 0x28c3, 0xc416, 0x28cf, 0xc416, 0x21, 0 - .dw 0x28d1, 0xc416, 0x28d1, 0xc416, 0x21, 0 - .dw 0x28d3, 0xc416, 0x28ff, 0xc416, 0x21, 0 - .dw 0x2901, 0xc416, 0x2901, 0xc416, 0x21, 0 - .dw 0x2903, 0xc416, 0x290f, 0xc416, 0x21, 0 - .dw 0x2911, 0xc416, 0x2911, 0xc416, 0x21, 0 - .dw 0x2913, 0xc416, 0x293f, 0xc416, 0x21, 0 - .dw 0x2941, 0xc416, 0x2941, 0xc416, 0x21, 0 - .dw 0x2943, 0xc416, 0x294f, 0xc416, 0x21, 0 - .dw 0x2951, 0xc416, 0x2951, 0xc416, 0x21, 0 - .dw 0x2953, 0xc416, 0x297f, 0xc416, 0x21, 0 - .dw 0x2981, 0xc416, 0x2981, 0xc416, 0x21, 0 - .dw 0x2983, 0xc416, 0x298f, 0xc416, 0x21, 0 - .dw 0x2991, 0xc416, 0x2991, 0xc416, 0x21, 0 - .dw 0x2993, 0xc416, 0x29bf, 0xc416, 0x21, 0 - .dw 0x29c1, 0xc416, 0x29c1, 0xc416, 0x21, 0 - .dw 0x29c3, 0xc416, 0x29cf, 0xc416, 0x21, 0 - .dw 0x29d1, 0xc416, 0x29d1, 0xc416, 0x21, 0 - .dw 0x29d3, 0xc416, 0x29ff, 0xc416, 0x21, 0 - .dw 0x2a01, 0xc416, 0x2a01, 0xc416, 0x21, 0 - .dw 0x2a03, 0xc416, 0x2a0f, 0xc416, 0x21, 0 - .dw 0x2a11, 0xc416, 0x2a11, 0xc416, 0x21, 0 - .dw 0x2a13, 0xc416, 0x2a3f, 0xc416, 0x21, 0 - .dw 0x2a41, 0xc416, 0x2a41, 0xc416, 0x21, 0 - .dw 0x2a43, 0xc416, 0x2a4f, 0xc416, 0x21, 0 - .dw 0x2a51, 0xc416, 0x2a51, 0xc416, 0x21, 0 - .dw 0x2a53, 0xc416, 0x2a7f, 0xc416, 0x21, 0 - .dw 0x2a81, 0xc416, 0x2a81, 0xc416, 0x21, 0 - .dw 0x2a83, 0xc416, 0x2a8f, 0xc416, 0x21, 0 - .dw 0x2a91, 0xc416, 0x2a91, 0xc416, 0x21, 0 - .dw 0x2a93, 0xc416, 0x2abf, 0xc416, 0x21, 0 - .dw 0x2ac1, 0xc416, 0x2ac1, 0xc416, 0x21, 0 - .dw 0x2ac3, 0xc416, 0x2acf, 0xc416, 0x21, 0 - .dw 0x2ad1, 0xc416, 0x2ad1, 0xc416, 0x21, 0 - .dw 0x2ad3, 0xc416, 0x2aff, 0xc416, 0x21, 0 - .dw 0x2b01, 0xc416, 0x2b01, 0xc416, 0x21, 0 - .dw 0x2b03, 0xc416, 0x2b0f, 0xc416, 0x21, 0 - .dw 0x2b11, 0xc416, 0x2b11, 0xc416, 0x21, 0 - .dw 0x2b13, 0xc416, 0x2b3f, 0xc416, 0x21, 0 - .dw 0x2b41, 0xc416, 0x2b41, 0xc416, 0x21, 0 - .dw 0x2b43, 0xc416, 0x2b4f, 0xc416, 0x21, 0 - .dw 0x2b51, 0xc416, 0x2b51, 0xc416, 0x21, 0 - .dw 0x2b53, 0xc416, 0x2b7f, 0xc416, 0x21, 0 - .dw 0x2b81, 0xc416, 0x2b81, 0xc416, 0x21, 0 - .dw 0x2b83, 0xc416, 0x2b8f, 0xc416, 0x21, 0 - .dw 0x2b91, 0xc416, 0x2b91, 0xc416, 0x21, 0 - .dw 0x2b93, 0xc416, 0x2bbf, 0xc416, 0x21, 0 - .dw 0x2bc1, 0xc416, 0x2bc1, 0xc416, 0x21, 0 - .dw 0x2bc3, 0xc416, 0x2bcf, 0xc416, 0x21, 0 - .dw 0x2bd1, 0xc416, 0x2bd1, 0xc416, 0x21, 0 - .dw 0x2bd3, 0xc416, 0x2bff, 0xc416, 0x21, 0 - .dw 0x2c01, 0xc416, 0x2c01, 0xc416, 0x21, 0 - .dw 0x2c03, 0xc416, 0x2c0f, 0xc416, 0x21, 0 - .dw 0x2c11, 0xc416, 0x2c11, 0xc416, 0x21, 0 - .dw 0x2c13, 0xc416, 0x2c3f, 0xc416, 0x21, 0 - .dw 0x2c41, 0xc416, 0x2c41, 0xc416, 0x21, 0 - .dw 0x2c43, 0xc416, 0x2c4f, 0xc416, 0x21, 0 - .dw 0x2c51, 0xc416, 0x2c51, 0xc416, 0x21, 0 - .dw 0x2c53, 0xc416, 0x2c7f, 0xc416, 0x21, 0 - .dw 0x2c81, 0xc416, 0x2c81, 0xc416, 0x21, 0 - .dw 0x2c83, 0xc416, 0x2c8f, 0xc416, 0x21, 0 - .dw 0x2c91, 0xc416, 0x2c91, 0xc416, 0x21, 0 - .dw 0x2c93, 0xc416, 0x2cbf, 0xc416, 0x21, 0 - .dw 0x2cc1, 0xc416, 0x2cc1, 0xc416, 0x21, 0 - .dw 0x2cc3, 0xc416, 0x2ccf, 0xc416, 0x21, 0 - .dw 0x2cd1, 0xc416, 0x2cd1, 0xc416, 0x21, 0 - .dw 0x2cd3, 0xc416, 0x2cff, 0xc416, 0x21, 0 - .dw 0x2d01, 0xc416, 0x2d01, 0xc416, 0x21, 0 - .dw 0x2d03, 0xc416, 0x2d0f, 0xc416, 0x21, 0 - .dw 0x2d11, 0xc416, 0x2d11, 0xc416, 0x21, 0 - .dw 0x2d13, 0xc416, 0x2d3f, 0xc416, 0x21, 0 - .dw 0x2d41, 0xc416, 0x2d41, 0xc416, 0x21, 0 - .dw 0x2d43, 0xc416, 0x2d4f, 0xc416, 0x21, 0 - .dw 0x2d51, 0xc416, 0x2d51, 0xc416, 0x21, 0 - .dw 0x2d53, 0xc416, 0x2d7f, 0xc416, 0x21, 0 - .dw 0x2d81, 0xc416, 0x2d81, 0xc416, 0x21, 0 - .dw 0x2d83, 0xc416, 0x2d8f, 0xc416, 0x21, 0 - .dw 0x2d91, 0xc416, 0x2d91, 0xc416, 0x21, 0 - .dw 0x2d93, 0xc416, 0x2dbf, 0xc416, 0x21, 0 - .dw 0x2dc1, 0xc416, 0x2dc1, 0xc416, 0x21, 0 - .dw 0x2dc3, 0xc416, 0x2dcf, 0xc416, 0x21, 0 - .dw 0x2dd1, 0xc416, 0x2dd1, 0xc416, 0x21, 0 - .dw 0x2dd3, 0xc416, 0x2dff, 0xc416, 0x21, 0 - .dw 0x2e01, 0xc416, 0x2e01, 0xc416, 0x21, 0 - .dw 0x2e03, 0xc416, 0x2e0f, 0xc416, 0x21, 0 - .dw 0x2e11, 0xc416, 0x2e11, 0xc416, 0x21, 0 - .dw 0x2e13, 0xc416, 0x2e3f, 0xc416, 0x21, 0 - .dw 0x2e41, 0xc416, 0x2e41, 0xc416, 0x21, 0 - .dw 0x2e43, 0xc416, 0x2e4f, 0xc416, 0x21, 0 - .dw 0x2e51, 0xc416, 0x2e51, 0xc416, 0x21, 0 - .dw 0x2e53, 0xc416, 0x2e7f, 0xc416, 0x21, 0 - .dw 0x2e81, 0xc416, 0x2e81, 0xc416, 0x21, 0 - .dw 0x2e83, 0xc416, 0x2e8f, 0xc416, 0x21, 0 - .dw 0x2e91, 0xc416, 0x2e91, 0xc416, 0x21, 0 - .dw 0x2e93, 0xc416, 0x2ebf, 0xc416, 0x21, 0 - .dw 0x2ec1, 0xc416, 0x2ec1, 0xc416, 0x21, 0 - .dw 0x2ec3, 0xc416, 0x2ecf, 0xc416, 0x21, 0 - .dw 0x2ed1, 0xc416, 0x2ed1, 0xc416, 0x21, 0 - .dw 0x2ed3, 0xc416, 0x2eff, 0xc416, 0x21, 0 - .dw 0x2f01, 0xc416, 0x2f01, 0xc416, 0x21, 0 - .dw 0x2f03, 0xc416, 0x2f0f, 0xc416, 0x21, 0 - .dw 0x2f11, 0xc416, 0x2f11, 0xc416, 0x21, 0 - .dw 0x2f13, 0xc416, 0x2f3f, 0xc416, 0x21, 0 - .dw 0x2f41, 0xc416, 0x2f41, 0xc416, 0x21, 0 - .dw 0x2f43, 0xc416, 0x2f4f, 0xc416, 0x21, 0 - .dw 0x2f51, 0xc416, 0x2f51, 0xc416, 0x21, 0 - .dw 0x2f53, 0xc416, 0x2f7f, 0xc416, 0x21, 0 - .dw 0x2f81, 0xc416, 0x2f81, 0xc416, 0x21, 0 - .dw 0x2f83, 0xc416, 0x2f8f, 0xc416, 0x21, 0 - .dw 0x2f91, 0xc416, 0x2f91, 0xc416, 0x21, 0 - .dw 0x2f93, 0xc416, 0x2fbf, 0xc416, 0x21, 0 - .dw 0x2fc1, 0xc416, 0x2fc1, 0xc416, 0x21, 0 - .dw 0x2fc3, 0xc416, 0x2fcf, 0xc416, 0x21, 0 - .dw 0x2fd1, 0xc416, 0x2fd1, 0xc416, 0x21, 0 - .dw 0x2fd3, 0xc416, 0x3fff, 0xc416, 0x21, 0 - .dw 0x4001, 0xc416, 0x4001, 0xc416, 0x21, 0 - .dw 0x4003, 0xc416, 0x400f, 0xc416, 0x21, 0 - .dw 0x4011, 0xc416, 0x4011, 0xc416, 0x21, 0 - .dw 0x4013, 0xc416, 0x403f, 0xc416, 0x21, 0 - .dw 0x4041, 0xc416, 0x4041, 0xc416, 0x21, 0 - .dw 0x4043, 0xc416, 0x404f, 0xc416, 0x21, 0 - .dw 0x4051, 0xc416, 0x4051, 0xc416, 0x21, 0 - .dw 0x4053, 0xc416, 0x407f, 0xc416, 0x21, 0 - .dw 0x4081, 0xc416, 0x4081, 0xc416, 0x21, 0 - .dw 0x4083, 0xc416, 0x408f, 0xc416, 0x21, 0 - .dw 0x4091, 0xc416, 0x4091, 0xc416, 0x21, 0 - .dw 0x4093, 0xc416, 0x40bf, 0xc416, 0x21, 0 - .dw 0x40c1, 0xc416, 0x40c1, 0xc416, 0x21, 0 - .dw 0x40c3, 0xc416, 0x40cf, 0xc416, 0x21, 0 - .dw 0x40d1, 0xc416, 0x40d1, 0xc416, 0x21, 0 - .dw 0x40d3, 0xc416, 0x40ff, 0xc416, 0x21, 0 - .dw 0x4101, 0xc416, 0x4101, 0xc416, 0x21, 0 - .dw 0x4103, 0xc416, 0x410f, 0xc416, 0x21, 0 - .dw 0x4111, 0xc416, 0x4111, 0xc416, 0x21, 0 - .dw 0x4113, 0xc416, 0x413f, 0xc416, 0x21, 0 - .dw 0x4141, 0xc416, 0x4141, 0xc416, 0x21, 0 - .dw 0x4143, 0xc416, 0x414f, 0xc416, 0x21, 0 - .dw 0x4151, 0xc416, 0x4151, 0xc416, 0x21, 0 - .dw 0x4153, 0xc416, 0x417f, 0xc416, 0x21, 0 - .dw 0x4181, 0xc416, 0x4181, 0xc416, 0x21, 0 - .dw 0x4183, 0xc416, 0x418f, 0xc416, 0x21, 0 - .dw 0x4191, 0xc416, 0x4191, 0xc416, 0x21, 0 - .dw 0x4193, 0xc416, 0x41bf, 0xc416, 0x21, 0 - .dw 0x41c1, 0xc416, 0x41c1, 0xc416, 0x21, 0 - .dw 0x41c3, 0xc416, 0x41cf, 0xc416, 0x21, 0 - .dw 0x41d1, 0xc416, 0x41d1, 0xc416, 0x21, 0 - .dw 0x41d3, 0xc416, 0x41ff, 0xc416, 0x21, 0 - .dw 0x4201, 0xc416, 0x4201, 0xc416, 0x21, 0 - .dw 0x4203, 0xc416, 0x420f, 0xc416, 0x21, 0 - .dw 0x4211, 0xc416, 0x4211, 0xc416, 0x21, 0 - .dw 0x4213, 0xc416, 0x423f, 0xc416, 0x21, 0 - .dw 0x4241, 0xc416, 0x4241, 0xc416, 0x21, 0 - .dw 0x4243, 0xc416, 0x424f, 0xc416, 0x21, 0 - .dw 0x4251, 0xc416, 0x4251, 0xc416, 0x21, 0 - .dw 0x4253, 0xc416, 0x427f, 0xc416, 0x21, 0 - .dw 0x4281, 0xc416, 0x4281, 0xc416, 0x21, 0 - .dw 0x4283, 0xc416, 0x428f, 0xc416, 0x21, 0 - .dw 0x4291, 0xc416, 0x4291, 0xc416, 0x21, 0 - .dw 0x4293, 0xc416, 0x42bf, 0xc416, 0x21, 0 - .dw 0x42c1, 0xc416, 0x42c1, 0xc416, 0x21, 0 - .dw 0x42c3, 0xc416, 0x42cf, 0xc416, 0x21, 0 - .dw 0x42d1, 0xc416, 0x42d1, 0xc416, 0x21, 0 - .dw 0x42d3, 0xc416, 0x42ff, 0xc416, 0x21, 0 - .dw 0x4301, 0xc416, 0x4301, 0xc416, 0x21, 0 - .dw 0x4303, 0xc416, 0x430f, 0xc416, 0x21, 0 - .dw 0x4311, 0xc416, 0x4311, 0xc416, 0x21, 0 - .dw 0x4313, 0xc416, 0x433f, 0xc416, 0x21, 0 - .dw 0x4341, 0xc416, 0x4341, 0xc416, 0x21, 0 - .dw 0x4343, 0xc416, 0x434f, 0xc416, 0x21, 0 - .dw 0x4351, 0xc416, 0x4351, 0xc416, 0x21, 0 - .dw 0x4353, 0xc416, 0x437f, 0xc416, 0x21, 0 - .dw 0x4381, 0xc416, 0x4381, 0xc416, 0x21, 0 - .dw 0x4383, 0xc416, 0x438f, 0xc416, 0x21, 0 - .dw 0x4391, 0xc416, 0x4391, 0xc416, 0x21, 0 - .dw 0x4393, 0xc416, 0x43bf, 0xc416, 0x21, 0 - .dw 0x43c1, 0xc416, 0x43c1, 0xc416, 0x21, 0 - .dw 0x43c3, 0xc416, 0x43cf, 0xc416, 0x21, 0 - .dw 0x43d1, 0xc416, 0x43d1, 0xc416, 0x21, 0 - .dw 0x43d3, 0xc416, 0x43ff, 0xc416, 0x21, 0 - .dw 0x4401, 0xc416, 0x4401, 0xc416, 0x21, 0 - .dw 0x4403, 0xc416, 0x440f, 0xc416, 0x21, 0 - .dw 0x4411, 0xc416, 0x4411, 0xc416, 0x21, 0 - .dw 0x4413, 0xc416, 0x443f, 0xc416, 0x21, 0 - .dw 0x4441, 0xc416, 0x4441, 0xc416, 0x21, 0 - .dw 0x4443, 0xc416, 0x444f, 0xc416, 0x21, 0 - .dw 0x4451, 0xc416, 0x4451, 0xc416, 0x21, 0 - .dw 0x4453, 0xc416, 0x447f, 0xc416, 0x21, 0 - .dw 0x4481, 0xc416, 0x4481, 0xc416, 0x21, 0 - .dw 0x4483, 0xc416, 0x448f, 0xc416, 0x21, 0 - .dw 0x4491, 0xc416, 0x4491, 0xc416, 0x21, 0 - .dw 0x4493, 0xc416, 0x44bf, 0xc416, 0x21, 0 - .dw 0x44c1, 0xc416, 0x44c1, 0xc416, 0x21, 0 - .dw 0x44c3, 0xc416, 0x44cf, 0xc416, 0x21, 0 - .dw 0x44d1, 0xc416, 0x44d1, 0xc416, 0x21, 0 - .dw 0x44d3, 0xc416, 0x44ff, 0xc416, 0x21, 0 - .dw 0x4501, 0xc416, 0x4501, 0xc416, 0x21, 0 - .dw 0x4503, 0xc416, 0x450f, 0xc416, 0x21, 0 - .dw 0x4511, 0xc416, 0x4511, 0xc416, 0x21, 0 - .dw 0x4513, 0xc416, 0x453f, 0xc416, 0x21, 0 - .dw 0x4541, 0xc416, 0x4541, 0xc416, 0x21, 0 - .dw 0x4543, 0xc416, 0x454f, 0xc416, 0x21, 0 - .dw 0x4551, 0xc416, 0x4551, 0xc416, 0x21, 0 - .dw 0x4553, 0xc416, 0x457f, 0xc416, 0x21, 0 - .dw 0x4581, 0xc416, 0x4581, 0xc416, 0x21, 0 - .dw 0x4583, 0xc416, 0x458f, 0xc416, 0x21, 0 - .dw 0x4591, 0xc416, 0x4591, 0xc416, 0x21, 0 - .dw 0x4593, 0xc416, 0x45bf, 0xc416, 0x21, 0 - .dw 0x45c1, 0xc416, 0x45c1, 0xc416, 0x21, 0 - .dw 0x45c3, 0xc416, 0x45cf, 0xc416, 0x21, 0 - .dw 0x45d1, 0xc416, 0x45d1, 0xc416, 0x21, 0 - .dw 0x45d3, 0xc416, 0x45ff, 0xc416, 0x21, 0 - .dw 0x4601, 0xc416, 0x4601, 0xc416, 0x21, 0 - .dw 0x4603, 0xc416, 0x460f, 0xc416, 0x21, 0 - .dw 0x4611, 0xc416, 0x4611, 0xc416, 0x21, 0 - .dw 0x4613, 0xc416, 0x463f, 0xc416, 0x21, 0 - .dw 0x4641, 0xc416, 0x4641, 0xc416, 0x21, 0 - .dw 0x4643, 0xc416, 0x464f, 0xc416, 0x21, 0 - .dw 0x4651, 0xc416, 0x4651, 0xc416, 0x21, 0 - .dw 0x4653, 0xc416, 0x467f, 0xc416, 0x21, 0 - .dw 0x4681, 0xc416, 0x4681, 0xc416, 0x21, 0 - .dw 0x4683, 0xc416, 0x468f, 0xc416, 0x21, 0 - .dw 0x4691, 0xc416, 0x4691, 0xc416, 0x21, 0 - .dw 0x4693, 0xc416, 0x46bf, 0xc416, 0x21, 0 - .dw 0x46c1, 0xc416, 0x46c1, 0xc416, 0x21, 0 - .dw 0x46c3, 0xc416, 0x46cf, 0xc416, 0x21, 0 - .dw 0x46d1, 0xc416, 0x46d1, 0xc416, 0x21, 0 - .dw 0x46d3, 0xc416, 0x46ff, 0xc416, 0x21, 0 - .dw 0x4701, 0xc416, 0x4701, 0xc416, 0x21, 0 - .dw 0x4703, 0xc416, 0x470f, 0xc416, 0x21, 0 - .dw 0x4711, 0xc416, 0x4711, 0xc416, 0x21, 0 - .dw 0x4713, 0xc416, 0x473f, 0xc416, 0x21, 0 - .dw 0x4741, 0xc416, 0x4741, 0xc416, 0x21, 0 - .dw 0x4743, 0xc416, 0x474f, 0xc416, 0x21, 0 - .dw 0x4751, 0xc416, 0x4751, 0xc416, 0x21, 0 - .dw 0x4753, 0xc416, 0x477f, 0xc416, 0x21, 0 - .dw 0x4781, 0xc416, 0x4781, 0xc416, 0x21, 0 - .dw 0x4783, 0xc416, 0x478f, 0xc416, 0x21, 0 - .dw 0x4791, 0xc416, 0x4791, 0xc416, 0x21, 0 - .dw 0x4793, 0xc416, 0x47bf, 0xc416, 0x21, 0 - .dw 0x47c1, 0xc416, 0x47c1, 0xc416, 0x21, 0 - .dw 0x47c3, 0xc416, 0x47cf, 0xc416, 0x21, 0 - .dw 0x47d1, 0xc416, 0x47d1, 0xc416, 0x21, 0 - .dw 0x47d3, 0xc416, 0x47ff, 0xc416, 0x21, 0 - .dw 0x4801, 0xc416, 0x4801, 0xc416, 0x21, 0 - .dw 0x4803, 0xc416, 0x480f, 0xc416, 0x21, 0 - .dw 0x4811, 0xc416, 0x4811, 0xc416, 0x21, 0 - .dw 0x4813, 0xc416, 0x483f, 0xc416, 0x21, 0 - .dw 0x4841, 0xc416, 0x4841, 0xc416, 0x21, 0 - .dw 0x4843, 0xc416, 0x484f, 0xc416, 0x21, 0 - .dw 0x4851, 0xc416, 0x4851, 0xc416, 0x21, 0 - .dw 0x4853, 0xc416, 0x487f, 0xc416, 0x21, 0 - .dw 0x4881, 0xc416, 0x4881, 0xc416, 0x21, 0 - .dw 0x4883, 0xc416, 0x488f, 0xc416, 0x21, 0 - .dw 0x4891, 0xc416, 0x4891, 0xc416, 0x21, 0 - .dw 0x4893, 0xc416, 0x48bf, 0xc416, 0x21, 0 - .dw 0x48c1, 0xc416, 0x48c1, 0xc416, 0x21, 0 - .dw 0x48c3, 0xc416, 0x48cf, 0xc416, 0x21, 0 - .dw 0x48d1, 0xc416, 0x48d1, 0xc416, 0x21, 0 - .dw 0x48d3, 0xc416, 0x48ff, 0xc416, 0x21, 0 - .dw 0x4901, 0xc416, 0x4901, 0xc416, 0x21, 0 - .dw 0x4903, 0xc416, 0x490f, 0xc416, 0x21, 0 - .dw 0x4911, 0xc416, 0x4911, 0xc416, 0x21, 0 - .dw 0x4913, 0xc416, 0x493f, 0xc416, 0x21, 0 - .dw 0x4941, 0xc416, 0x4941, 0xc416, 0x21, 0 - .dw 0x4943, 0xc416, 0x494f, 0xc416, 0x21, 0 - .dw 0x4951, 0xc416, 0x4951, 0xc416, 0x21, 0 - .dw 0x4953, 0xc416, 0x497f, 0xc416, 0x21, 0 - .dw 0x4981, 0xc416, 0x4981, 0xc416, 0x21, 0 - .dw 0x4983, 0xc416, 0x498f, 0xc416, 0x21, 0 - .dw 0x4991, 0xc416, 0x4991, 0xc416, 0x21, 0 - .dw 0x4993, 0xc416, 0x49bf, 0xc416, 0x21, 0 - .dw 0x49c1, 0xc416, 0x49c1, 0xc416, 0x21, 0 - .dw 0x49c3, 0xc416, 0x49cf, 0xc416, 0x21, 0 - .dw 0x49d1, 0xc416, 0x49d1, 0xc416, 0x21, 0 - .dw 0x49d3, 0xc416, 0x49ff, 0xc416, 0x21, 0 - .dw 0x4a01, 0xc416, 0x4a01, 0xc416, 0x21, 0 - .dw 0x4a03, 0xc416, 0x4a0f, 0xc416, 0x21, 0 - .dw 0x4a11, 0xc416, 0x4a11, 0xc416, 0x21, 0 - .dw 0x4a13, 0xc416, 0x4a3f, 0xc416, 0x21, 0 - .dw 0x4a41, 0xc416, 0x4a41, 0xc416, 0x21, 0 - .dw 0x4a43, 0xc416, 0x4a4f, 0xc416, 0x21, 0 - .dw 0x4a51, 0xc416, 0x4a51, 0xc416, 0x21, 0 - .dw 0x4a53, 0xc416, 0x4a7f, 0xc416, 0x21, 0 - .dw 0x4a81, 0xc416, 0x4a81, 0xc416, 0x21, 0 - .dw 0x4a83, 0xc416, 0x4a8f, 0xc416, 0x21, 0 - .dw 0x4a91, 0xc416, 0x4a91, 0xc416, 0x21, 0 - .dw 0x4a93, 0xc416, 0x4abf, 0xc416, 0x21, 0 - .dw 0x4ac1, 0xc416, 0x4ac1, 0xc416, 0x21, 0 - .dw 0x4ac3, 0xc416, 0x4acf, 0xc416, 0x21, 0 - .dw 0x4ad1, 0xc416, 0x4ad1, 0xc416, 0x21, 0 - .dw 0x4ad3, 0xc416, 0x4aff, 0xc416, 0x21, 0 - .dw 0x4b01, 0xc416, 0x4b01, 0xc416, 0x21, 0 - .dw 0x4b03, 0xc416, 0x4b0f, 0xc416, 0x21, 0 - .dw 0x4b11, 0xc416, 0x4b11, 0xc416, 0x21, 0 - .dw 0x4b13, 0xc416, 0x4b3f, 0xc416, 0x21, 0 - .dw 0x4b41, 0xc416, 0x4b41, 0xc416, 0x21, 0 - .dw 0x4b43, 0xc416, 0x4b4f, 0xc416, 0x21, 0 - .dw 0x4b51, 0xc416, 0x4b51, 0xc416, 0x21, 0 - .dw 0x4b53, 0xc416, 0x4b7f, 0xc416, 0x21, 0 - .dw 0x4b81, 0xc416, 0x4b81, 0xc416, 0x21, 0 - .dw 0x4b83, 0xc416, 0x4b8f, 0xc416, 0x21, 0 - .dw 0x4b91, 0xc416, 0x4b91, 0xc416, 0x21, 0 - .dw 0x4b93, 0xc416, 0x4bbf, 0xc416, 0x21, 0 - .dw 0x4bc1, 0xc416, 0x4bc1, 0xc416, 0x21, 0 - .dw 0x4bc3, 0xc416, 0x4bcf, 0xc416, 0x21, 0 - .dw 0x4bd1, 0xc416, 0x4bd1, 0xc416, 0x21, 0 - .dw 0x4bd3, 0xc416, 0x4bff, 0xc416, 0x21, 0 - .dw 0x4c01, 0xc416, 0x4c01, 0xc416, 0x21, 0 - .dw 0x4c03, 0xc416, 0x4c0f, 0xc416, 0x21, 0 - .dw 0x4c11, 0xc416, 0x4c11, 0xc416, 0x21, 0 - .dw 0x4c13, 0xc416, 0x4c3f, 0xc416, 0x21, 0 - .dw 0x4c41, 0xc416, 0x4c41, 0xc416, 0x21, 0 - .dw 0x4c43, 0xc416, 0x4c4f, 0xc416, 0x21, 0 - .dw 0x4c51, 0xc416, 0x4c51, 0xc416, 0x21, 0 - .dw 0x4c53, 0xc416, 0x4c7f, 0xc416, 0x21, 0 - .dw 0x4c81, 0xc416, 0x4c81, 0xc416, 0x21, 0 - .dw 0x4c83, 0xc416, 0x4c8f, 0xc416, 0x21, 0 - .dw 0x4c91, 0xc416, 0x4c91, 0xc416, 0x21, 0 - .dw 0x4c93, 0xc416, 0x4cbf, 0xc416, 0x21, 0 - .dw 0x4cc1, 0xc416, 0x4cc1, 0xc416, 0x21, 0 - .dw 0x4cc3, 0xc416, 0x4ccf, 0xc416, 0x21, 0 - .dw 0x4cd1, 0xc416, 0x4cd1, 0xc416, 0x21, 0 - .dw 0x4cd3, 0xc416, 0x4cff, 0xc416, 0x21, 0 - .dw 0x4d01, 0xc416, 0x4d01, 0xc416, 0x21, 0 - .dw 0x4d03, 0xc416, 0x4d0f, 0xc416, 0x21, 0 - .dw 0x4d11, 0xc416, 0x4d11, 0xc416, 0x21, 0 - .dw 0x4d13, 0xc416, 0x4d3f, 0xc416, 0x21, 0 - .dw 0x4d41, 0xc416, 0x4d41, 0xc416, 0x21, 0 - .dw 0x4d43, 0xc416, 0x4d4f, 0xc416, 0x21, 0 - .dw 0x4d51, 0xc416, 0x4d51, 0xc416, 0x21, 0 - .dw 0x4d53, 0xc416, 0x4d7f, 0xc416, 0x21, 0 - .dw 0x4d81, 0xc416, 0x4d81, 0xc416, 0x21, 0 - .dw 0x4d83, 0xc416, 0x4d8f, 0xc416, 0x21, 0 - .dw 0x4d91, 0xc416, 0x4d91, 0xc416, 0x21, 0 - .dw 0x4d93, 0xc416, 0x4dbf, 0xc416, 0x21, 0 - .dw 0x4dc1, 0xc416, 0x4dc1, 0xc416, 0x21, 0 - .dw 0x4dc3, 0xc416, 0x4dcf, 0xc416, 0x21, 0 - .dw 0x4dd1, 0xc416, 0x4dd1, 0xc416, 0x21, 0 - .dw 0x4dd3, 0xc416, 0x4dff, 0xc416, 0x21, 0 - .dw 0x4e01, 0xc416, 0x4e01, 0xc416, 0x21, 0 - .dw 0x4e03, 0xc416, 0x4e0f, 0xc416, 0x21, 0 - .dw 0x4e11, 0xc416, 0x4e11, 0xc416, 0x21, 0 - .dw 0x4e13, 0xc416, 0x4e3f, 0xc416, 0x21, 0 - .dw 0x4e41, 0xc416, 0x4e41, 0xc416, 0x21, 0 - .dw 0x4e43, 0xc416, 0x4e4f, 0xc416, 0x21, 0 - .dw 0x4e51, 0xc416, 0x4e51, 0xc416, 0x21, 0 - .dw 0x4e53, 0xc416, 0x4e7f, 0xc416, 0x21, 0 - .dw 0x4e81, 0xc416, 0x4e81, 0xc416, 0x21, 0 - .dw 0x4e83, 0xc416, 0x4e8f, 0xc416, 0x21, 0 - .dw 0x4e91, 0xc416, 0x4e91, 0xc416, 0x21, 0 - .dw 0x4e93, 0xc416, 0x4ebf, 0xc416, 0x21, 0 - .dw 0x4ec1, 0xc416, 0x4ec1, 0xc416, 0x21, 0 - .dw 0x4ec3, 0xc416, 0x4ecf, 0xc416, 0x21, 0 - .dw 0x4ed1, 0xc416, 0x4ed1, 0xc416, 0x21, 0 - .dw 0x4ed3, 0xc416, 0x4eff, 0xc416, 0x21, 0 - .dw 0x4f01, 0xc416, 0x4f01, 0xc416, 0x21, 0 - .dw 0x4f03, 0xc416, 0x4f0f, 0xc416, 0x21, 0 - .dw 0x4f11, 0xc416, 0x4f11, 0xc416, 0x21, 0 - .dw 0x4f13, 0xc416, 0x4f3f, 0xc416, 0x21, 0 - .dw 0x4f41, 0xc416, 0x4f41, 0xc416, 0x21, 0 - .dw 0x4f43, 0xc416, 0x4f4f, 0xc416, 0x21, 0 - .dw 0x4f51, 0xc416, 0x4f51, 0xc416, 0x21, 0 - .dw 0x4f53, 0xc416, 0x4f7f, 0xc416, 0x21, 0 - .dw 0x4f81, 0xc416, 0x4f81, 0xc416, 0x21, 0 - .dw 0x4f83, 0xc416, 0x4f8f, 0xc416, 0x21, 0 - .dw 0x4f91, 0xc416, 0x4f91, 0xc416, 0x21, 0 - .dw 0x4f93, 0xc416, 0x4fbf, 0xc416, 0x21, 0 - .dw 0x4fc1, 0xc416, 0x4fc1, 0xc416, 0x21, 0 - .dw 0x4fc3, 0xc416, 0x4fcf, 0xc416, 0x21, 0 - .dw 0x4fd1, 0xc416, 0x4fd1, 0xc416, 0x21, 0 - .dw 0x4fd3, 0xc416, 0x5fff, 0xc416, 0x21, 0 - .dw 0x6001, 0xc416, 0x6001, 0xc416, 0x21, 0 - .dw 0x6003, 0xc416, 0x600f, 0xc416, 0x21, 0 - .dw 0x6011, 0xc416, 0x6011, 0xc416, 0x21, 0 - .dw 0x6013, 0xc416, 0x603f, 0xc416, 0x21, 0 - .dw 0x6041, 0xc416, 0x6041, 0xc416, 0x21, 0 - .dw 0x6043, 0xc416, 0x604f, 0xc416, 0x21, 0 - .dw 0x6051, 0xc416, 0x6051, 0xc416, 0x21, 0 - .dw 0x6053, 0xc416, 0x607f, 0xc416, 0x21, 0 - .dw 0x6081, 0xc416, 0x6081, 0xc416, 0x21, 0 - .dw 0x6083, 0xc416, 0x608f, 0xc416, 0x21, 0 - .dw 0x6091, 0xc416, 0x6091, 0xc416, 0x21, 0 - .dw 0x6093, 0xc416, 0x60bf, 0xc416, 0x21, 0 - .dw 0x60c1, 0xc416, 0x60c1, 0xc416, 0x21, 0 - .dw 0x60c3, 0xc416, 0x60cf, 0xc416, 0x21, 0 - .dw 0x60d1, 0xc416, 0x60d1, 0xc416, 0x21, 0 - .dw 0x60d3, 0xc416, 0x60ff, 0xc416, 0x21, 0 - .dw 0x6101, 0xc416, 0x6101, 0xc416, 0x21, 0 - .dw 0x6103, 0xc416, 0x610f, 0xc416, 0x21, 0 - .dw 0x6111, 0xc416, 0x6111, 0xc416, 0x21, 0 - .dw 0x6113, 0xc416, 0x613f, 0xc416, 0x21, 0 - .dw 0x6141, 0xc416, 0x6141, 0xc416, 0x21, 0 - .dw 0x6143, 0xc416, 0x614f, 0xc416, 0x21, 0 - .dw 0x6151, 0xc416, 0x6151, 0xc416, 0x21, 0 - .dw 0x6153, 0xc416, 0x617f, 0xc416, 0x21, 0 - .dw 0x6181, 0xc416, 0x6181, 0xc416, 0x21, 0 - .dw 0x6183, 0xc416, 0x618f, 0xc416, 0x21, 0 - .dw 0x6191, 0xc416, 0x6191, 0xc416, 0x21, 0 - .dw 0x6193, 0xc416, 0x61bf, 0xc416, 0x21, 0 - .dw 0x61c1, 0xc416, 0x61c1, 0xc416, 0x21, 0 - .dw 0x61c3, 0xc416, 0x61cf, 0xc416, 0x21, 0 - .dw 0x61d1, 0xc416, 0x61d1, 0xc416, 0x21, 0 - .dw 0x61d3, 0xc416, 0x61ff, 0xc416, 0x21, 0 - .dw 0x6201, 0xc416, 0x6201, 0xc416, 0x21, 0 - .dw 0x6203, 0xc416, 0x620f, 0xc416, 0x21, 0 - .dw 0x6211, 0xc416, 0x6211, 0xc416, 0x21, 0 - .dw 0x6213, 0xc416, 0x623f, 0xc416, 0x21, 0 - .dw 0x6241, 0xc416, 0x6241, 0xc416, 0x21, 0 - .dw 0x6243, 0xc416, 0x624f, 0xc416, 0x21, 0 - .dw 0x6251, 0xc416, 0x6251, 0xc416, 0x21, 0 - .dw 0x6253, 0xc416, 0x627f, 0xc416, 0x21, 0 - .dw 0x6281, 0xc416, 0x6281, 0xc416, 0x21, 0 - .dw 0x6283, 0xc416, 0x628f, 0xc416, 0x21, 0 - .dw 0x6291, 0xc416, 0x6291, 0xc416, 0x21, 0 - .dw 0x6293, 0xc416, 0x62bf, 0xc416, 0x21, 0 - .dw 0x62c1, 0xc416, 0x62c1, 0xc416, 0x21, 0 - .dw 0x62c3, 0xc416, 0x62cf, 0xc416, 0x21, 0 - .dw 0x62d1, 0xc416, 0x62d1, 0xc416, 0x21, 0 - .dw 0x62d3, 0xc416, 0x62ff, 0xc416, 0x21, 0 - .dw 0x6301, 0xc416, 0x6301, 0xc416, 0x21, 0 - .dw 0x6303, 0xc416, 0x630f, 0xc416, 0x21, 0 - .dw 0x6311, 0xc416, 0x6311, 0xc416, 0x21, 0 - .dw 0x6313, 0xc416, 0x633f, 0xc416, 0x21, 0 - .dw 0x6341, 0xc416, 0x6341, 0xc416, 0x21, 0 - .dw 0x6343, 0xc416, 0x634f, 0xc416, 0x21, 0 - .dw 0x6351, 0xc416, 0x6351, 0xc416, 0x21, 0 - .dw 0x6353, 0xc416, 0x637f, 0xc416, 0x21, 0 - .dw 0x6381, 0xc416, 0x6381, 0xc416, 0x21, 0 - .dw 0x6383, 0xc416, 0x638f, 0xc416, 0x21, 0 - .dw 0x6391, 0xc416, 0x6391, 0xc416, 0x21, 0 - .dw 0x6393, 0xc416, 0x63bf, 0xc416, 0x21, 0 - .dw 0x63c1, 0xc416, 0x63c1, 0xc416, 0x21, 0 - .dw 0x63c3, 0xc416, 0x63cf, 0xc416, 0x21, 0 - .dw 0x63d1, 0xc416, 0x63d1, 0xc416, 0x21, 0 - .dw 0x63d3, 0xc416, 0x63ff, 0xc416, 0x21, 0 - .dw 0x6401, 0xc416, 0x6401, 0xc416, 0x21, 0 - .dw 0x6403, 0xc416, 0x640f, 0xc416, 0x21, 0 - .dw 0x6411, 0xc416, 0x6411, 0xc416, 0x21, 0 - .dw 0x6413, 0xc416, 0x643f, 0xc416, 0x21, 0 - .dw 0x6441, 0xc416, 0x6441, 0xc416, 0x21, 0 - .dw 0x6443, 0xc416, 0x644f, 0xc416, 0x21, 0 - .dw 0x6451, 0xc416, 0x6451, 0xc416, 0x21, 0 - .dw 0x6453, 0xc416, 0x647f, 0xc416, 0x21, 0 - .dw 0x6481, 0xc416, 0x6481, 0xc416, 0x21, 0 - .dw 0x6483, 0xc416, 0x648f, 0xc416, 0x21, 0 - .dw 0x6491, 0xc416, 0x6491, 0xc416, 0x21, 0 - .dw 0x6493, 0xc416, 0x64bf, 0xc416, 0x21, 0 - .dw 0x64c1, 0xc416, 0x64c1, 0xc416, 0x21, 0 - .dw 0x64c3, 0xc416, 0x64cf, 0xc416, 0x21, 0 - .dw 0x64d1, 0xc416, 0x64d1, 0xc416, 0x21, 0 - .dw 0x64d3, 0xc416, 0x64ff, 0xc416, 0x21, 0 - .dw 0x6501, 0xc416, 0x6501, 0xc416, 0x21, 0 - .dw 0x6503, 0xc416, 0x650f, 0xc416, 0x21, 0 - .dw 0x6511, 0xc416, 0x6511, 0xc416, 0x21, 0 - .dw 0x6513, 0xc416, 0x653f, 0xc416, 0x21, 0 - .dw 0x6541, 0xc416, 0x6541, 0xc416, 0x21, 0 - .dw 0x6543, 0xc416, 0x654f, 0xc416, 0x21, 0 - .dw 0x6551, 0xc416, 0x6551, 0xc416, 0x21, 0 - .dw 0x6553, 0xc416, 0x657f, 0xc416, 0x21, 0 - .dw 0x6581, 0xc416, 0x6581, 0xc416, 0x21, 0 - .dw 0x6583, 0xc416, 0x658f, 0xc416, 0x21, 0 - .dw 0x6591, 0xc416, 0x6591, 0xc416, 0x21, 0 - .dw 0x6593, 0xc416, 0x65bf, 0xc416, 0x21, 0 - .dw 0x65c1, 0xc416, 0x65c1, 0xc416, 0x21, 0 - .dw 0x65c3, 0xc416, 0x65cf, 0xc416, 0x21, 0 - .dw 0x65d1, 0xc416, 0x65d1, 0xc416, 0x21, 0 - .dw 0x65d3, 0xc416, 0x65ff, 0xc416, 0x21, 0 - .dw 0x6601, 0xc416, 0x6601, 0xc416, 0x21, 0 - .dw 0x6603, 0xc416, 0x660f, 0xc416, 0x21, 0 - .dw 0x6611, 0xc416, 0x6611, 0xc416, 0x21, 0 - .dw 0x6613, 0xc416, 0x663f, 0xc416, 0x21, 0 - .dw 0x6641, 0xc416, 0x6641, 0xc416, 0x21, 0 - .dw 0x6643, 0xc416, 0x664f, 0xc416, 0x21, 0 - .dw 0x6651, 0xc416, 0x6651, 0xc416, 0x21, 0 - .dw 0x6653, 0xc416, 0x667f, 0xc416, 0x21, 0 - .dw 0x6681, 0xc416, 0x6681, 0xc416, 0x21, 0 - .dw 0x6683, 0xc416, 0x668f, 0xc416, 0x21, 0 - .dw 0x6691, 0xc416, 0x6691, 0xc416, 0x21, 0 - .dw 0x6693, 0xc416, 0x66bf, 0xc416, 0x21, 0 - .dw 0x66c1, 0xc416, 0x66c1, 0xc416, 0x21, 0 - .dw 0x66c3, 0xc416, 0x66cf, 0xc416, 0x21, 0 - .dw 0x66d1, 0xc416, 0x66d1, 0xc416, 0x21, 0 - .dw 0x66d3, 0xc416, 0x66ff, 0xc416, 0x21, 0 - .dw 0x6701, 0xc416, 0x6701, 0xc416, 0x21, 0 - .dw 0x6703, 0xc416, 0x670f, 0xc416, 0x21, 0 - .dw 0x6711, 0xc416, 0x6711, 0xc416, 0x21, 0 - .dw 0x6713, 0xc416, 0x673f, 0xc416, 0x21, 0 - .dw 0x6741, 0xc416, 0x6741, 0xc416, 0x21, 0 - .dw 0x6743, 0xc416, 0x674f, 0xc416, 0x21, 0 - .dw 0x6751, 0xc416, 0x6751, 0xc416, 0x21, 0 - .dw 0x6753, 0xc416, 0x677f, 0xc416, 0x21, 0 - .dw 0x6781, 0xc416, 0x6781, 0xc416, 0x21, 0 - .dw 0x6783, 0xc416, 0x678f, 0xc416, 0x21, 0 - .dw 0x6791, 0xc416, 0x6791, 0xc416, 0x21, 0 - .dw 0x6793, 0xc416, 0x67bf, 0xc416, 0x21, 0 - .dw 0x67c1, 0xc416, 0x67c1, 0xc416, 0x21, 0 - .dw 0x67c3, 0xc416, 0x67cf, 0xc416, 0x21, 0 - .dw 0x67d1, 0xc416, 0x67d1, 0xc416, 0x21, 0 - .dw 0x67d3, 0xc416, 0x67ff, 0xc416, 0x21, 0 - .dw 0x6801, 0xc416, 0x6801, 0xc416, 0x21, 0 - .dw 0x6803, 0xc416, 0x680f, 0xc416, 0x21, 0 - .dw 0x6811, 0xc416, 0x6811, 0xc416, 0x21, 0 - .dw 0x6813, 0xc416, 0x683f, 0xc416, 0x21, 0 - .dw 0x6841, 0xc416, 0x6841, 0xc416, 0x21, 0 - .dw 0x6843, 0xc416, 0x684f, 0xc416, 0x21, 0 - .dw 0x6851, 0xc416, 0x6851, 0xc416, 0x21, 0 - .dw 0x6853, 0xc416, 0x687f, 0xc416, 0x21, 0 - .dw 0x6881, 0xc416, 0x6881, 0xc416, 0x21, 0 - .dw 0x6883, 0xc416, 0x688f, 0xc416, 0x21, 0 - .dw 0x6891, 0xc416, 0x6891, 0xc416, 0x21, 0 - .dw 0x6893, 0xc416, 0x68bf, 0xc416, 0x21, 0 - .dw 0x68c1, 0xc416, 0x68c1, 0xc416, 0x21, 0 - .dw 0x68c3, 0xc416, 0x68cf, 0xc416, 0x21, 0 - .dw 0x68d1, 0xc416, 0x68d1, 0xc416, 0x21, 0 - .dw 0x68d3, 0xc416, 0x68ff, 0xc416, 0x21, 0 - .dw 0x6901, 0xc416, 0x6901, 0xc416, 0x21, 0 - .dw 0x6903, 0xc416, 0x690f, 0xc416, 0x21, 0 - .dw 0x6911, 0xc416, 0x6911, 0xc416, 0x21, 0 - .dw 0x6913, 0xc416, 0x693f, 0xc416, 0x21, 0 - .dw 0x6941, 0xc416, 0x6941, 0xc416, 0x21, 0 - .dw 0x6943, 0xc416, 0x694f, 0xc416, 0x21, 0 - .dw 0x6951, 0xc416, 0x6951, 0xc416, 0x21, 0 - .dw 0x6953, 0xc416, 0x697f, 0xc416, 0x21, 0 - .dw 0x6981, 0xc416, 0x6981, 0xc416, 0x21, 0 - .dw 0x6983, 0xc416, 0x698f, 0xc416, 0x21, 0 - .dw 0x6991, 0xc416, 0x6991, 0xc416, 0x21, 0 - .dw 0x6993, 0xc416, 0x69bf, 0xc416, 0x21, 0 - .dw 0x69c1, 0xc416, 0x69c1, 0xc416, 0x21, 0 - .dw 0x69c3, 0xc416, 0x69cf, 0xc416, 0x21, 0 - .dw 0x69d1, 0xc416, 0x69d1, 0xc416, 0x21, 0 - .dw 0x69d3, 0xc416, 0x69ff, 0xc416, 0x21, 0 - .dw 0x6a01, 0xc416, 0x6a01, 0xc416, 0x21, 0 - .dw 0x6a03, 0xc416, 0x6a0f, 0xc416, 0x21, 0 - .dw 0x6a11, 0xc416, 0x6a11, 0xc416, 0x21, 0 - .dw 0x6a13, 0xc416, 0x6a3f, 0xc416, 0x21, 0 - .dw 0x6a41, 0xc416, 0x6a41, 0xc416, 0x21, 0 - .dw 0x6a43, 0xc416, 0x6a4f, 0xc416, 0x21, 0 - .dw 0x6a51, 0xc416, 0x6a51, 0xc416, 0x21, 0 - .dw 0x6a53, 0xc416, 0x6a7f, 0xc416, 0x21, 0 - .dw 0x6a81, 0xc416, 0x6a81, 0xc416, 0x21, 0 - .dw 0x6a83, 0xc416, 0x6a8f, 0xc416, 0x21, 0 - .dw 0x6a91, 0xc416, 0x6a91, 0xc416, 0x21, 0 - .dw 0x6a93, 0xc416, 0x6abf, 0xc416, 0x21, 0 - .dw 0x6ac1, 0xc416, 0x6ac1, 0xc416, 0x21, 0 - .dw 0x6ac3, 0xc416, 0x6acf, 0xc416, 0x21, 0 - .dw 0x6ad1, 0xc416, 0x6ad1, 0xc416, 0x21, 0 - .dw 0x6ad3, 0xc416, 0x6aff, 0xc416, 0x21, 0 - .dw 0x6b01, 0xc416, 0x6b01, 0xc416, 0x21, 0 - .dw 0x6b03, 0xc416, 0x6b0f, 0xc416, 0x21, 0 - .dw 0x6b11, 0xc416, 0x6b11, 0xc416, 0x21, 0 - .dw 0x6b13, 0xc416, 0x6b3f, 0xc416, 0x21, 0 - .dw 0x6b41, 0xc416, 0x6b41, 0xc416, 0x21, 0 - .dw 0x6b43, 0xc416, 0x6b4f, 0xc416, 0x21, 0 - .dw 0x6b51, 0xc416, 0x6b51, 0xc416, 0x21, 0 - .dw 0x6b53, 0xc416, 0x6b7f, 0xc416, 0x21, 0 - .dw 0x6b81, 0xc416, 0x6b81, 0xc416, 0x21, 0 - .dw 0x6b83, 0xc416, 0x6b8f, 0xc416, 0x21, 0 - .dw 0x6b91, 0xc416, 0x6b91, 0xc416, 0x21, 0 - .dw 0x6b93, 0xc416, 0x6bbf, 0xc416, 0x21, 0 - .dw 0x6bc1, 0xc416, 0x6bc1, 0xc416, 0x21, 0 - .dw 0x6bc3, 0xc416, 0x6bcf, 0xc416, 0x21, 0 - .dw 0x6bd1, 0xc416, 0x6bd1, 0xc416, 0x21, 0 - .dw 0x6bd3, 0xc416, 0x6bff, 0xc416, 0x21, 0 - .dw 0x6c01, 0xc416, 0x6c01, 0xc416, 0x21, 0 - .dw 0x6c03, 0xc416, 0x6c0f, 0xc416, 0x21, 0 - .dw 0x6c11, 0xc416, 0x6c11, 0xc416, 0x21, 0 - .dw 0x6c13, 0xc416, 0x6c3f, 0xc416, 0x21, 0 - .dw 0x6c41, 0xc416, 0x6c41, 0xc416, 0x21, 0 - .dw 0x6c43, 0xc416, 0x6c4f, 0xc416, 0x21, 0 - .dw 0x6c51, 0xc416, 0x6c51, 0xc416, 0x21, 0 - .dw 0x6c53, 0xc416, 0x6c7f, 0xc416, 0x21, 0 - .dw 0x6c81, 0xc416, 0x6c81, 0xc416, 0x21, 0 - .dw 0x6c83, 0xc416, 0x6c8f, 0xc416, 0x21, 0 - .dw 0x6c91, 0xc416, 0x6c91, 0xc416, 0x21, 0 - .dw 0x6c93, 0xc416, 0x6cbf, 0xc416, 0x21, 0 - .dw 0x6cc1, 0xc416, 0x6cc1, 0xc416, 0x21, 0 - .dw 0x6cc3, 0xc416, 0x6ccf, 0xc416, 0x21, 0 - .dw 0x6cd1, 0xc416, 0x6cd1, 0xc416, 0x21, 0 - .dw 0x6cd3, 0xc416, 0x6cff, 0xc416, 0x21, 0 - .dw 0x6d01, 0xc416, 0x6d01, 0xc416, 0x21, 0 - .dw 0x6d03, 0xc416, 0x6d0f, 0xc416, 0x21, 0 - .dw 0x6d11, 0xc416, 0x6d11, 0xc416, 0x21, 0 - .dw 0x6d13, 0xc416, 0x6d3f, 0xc416, 0x21, 0 - .dw 0x6d41, 0xc416, 0x6d41, 0xc416, 0x21, 0 - .dw 0x6d43, 0xc416, 0x6d4f, 0xc416, 0x21, 0 - .dw 0x6d51, 0xc416, 0x6d51, 0xc416, 0x21, 0 - .dw 0x6d53, 0xc416, 0x6d7f, 0xc416, 0x21, 0 - .dw 0x6d81, 0xc416, 0x6d81, 0xc416, 0x21, 0 - .dw 0x6d83, 0xc416, 0x6d8f, 0xc416, 0x21, 0 - .dw 0x6d91, 0xc416, 0x6d91, 0xc416, 0x21, 0 - .dw 0x6d93, 0xc416, 0x6dbf, 0xc416, 0x21, 0 - .dw 0x6dc1, 0xc416, 0x6dc1, 0xc416, 0x21, 0 - .dw 0x6dc3, 0xc416, 0x6dcf, 0xc416, 0x21, 0 - .dw 0x6dd1, 0xc416, 0x6dd1, 0xc416, 0x21, 0 - .dw 0x6dd3, 0xc416, 0x6dff, 0xc416, 0x21, 0 - .dw 0x6e01, 0xc416, 0x6e01, 0xc416, 0x21, 0 - .dw 0x6e03, 0xc416, 0x6e0f, 0xc416, 0x21, 0 - .dw 0x6e11, 0xc416, 0x6e11, 0xc416, 0x21, 0 - .dw 0x6e13, 0xc416, 0x6e3f, 0xc416, 0x21, 0 - .dw 0x6e41, 0xc416, 0x6e41, 0xc416, 0x21, 0 - .dw 0x6e43, 0xc416, 0x6e4f, 0xc416, 0x21, 0 - .dw 0x6e51, 0xc416, 0x6e51, 0xc416, 0x21, 0 - .dw 0x6e53, 0xc416, 0x6e7f, 0xc416, 0x21, 0 - .dw 0x6e81, 0xc416, 0x6e81, 0xc416, 0x21, 0 - .dw 0x6e83, 0xc416, 0x6e8f, 0xc416, 0x21, 0 - .dw 0x6e91, 0xc416, 0x6e91, 0xc416, 0x21, 0 - .dw 0x6e93, 0xc416, 0x6ebf, 0xc416, 0x21, 0 - .dw 0x6ec1, 0xc416, 0x6ec1, 0xc416, 0x21, 0 - .dw 0x6ec3, 0xc416, 0x6ecf, 0xc416, 0x21, 0 - .dw 0x6ed1, 0xc416, 0x6ed1, 0xc416, 0x21, 0 - .dw 0x6ed3, 0xc416, 0x6eff, 0xc416, 0x21, 0 - .dw 0x6f01, 0xc416, 0x6f01, 0xc416, 0x21, 0 - .dw 0x6f03, 0xc416, 0x6f0f, 0xc416, 0x21, 0 - .dw 0x6f11, 0xc416, 0x6f11, 0xc416, 0x21, 0 - .dw 0x6f13, 0xc416, 0x6f3f, 0xc416, 0x21, 0 - .dw 0x6f41, 0xc416, 0x6f41, 0xc416, 0x21, 0 - .dw 0x6f43, 0xc416, 0x6f4f, 0xc416, 0x21, 0 - .dw 0x6f51, 0xc416, 0x6f51, 0xc416, 0x21, 0 - .dw 0x6f53, 0xc416, 0x6f7f, 0xc416, 0x21, 0 - .dw 0x6f81, 0xc416, 0x6f81, 0xc416, 0x21, 0 - .dw 0x6f83, 0xc416, 0x6f8f, 0xc416, 0x21, 0 - .dw 0x6f91, 0xc416, 0x6f91, 0xc416, 0x21, 0 - .dw 0x6f93, 0xc416, 0x6fbf, 0xc416, 0x21, 0 - .dw 0x6fc1, 0xc416, 0x6fc1, 0xc416, 0x21, 0 - .dw 0x6fc3, 0xc416, 0x6fcf, 0xc416, 0x21, 0 - .dw 0x6fd1, 0xc416, 0x6fd1, 0xc416, 0x21, 0 - .dw 0x6fd3, 0xc416, 0xffff, 0xc416, 0x21, 0 - .dw 0x0001, 0xc417, 0x0001, 0xc417, 0x21, 0 - .dw 0x0003, 0xc417, 0x000f, 0xc417, 0x21, 0 - .dw 0x0011, 0xc417, 0x0011, 0xc417, 0x21, 0 - .dw 0x0013, 0xc417, 0x003f, 0xc417, 0x21, 0 - .dw 0x0041, 0xc417, 0x0041, 0xc417, 0x21, 0 - .dw 0x0043, 0xc417, 0x004f, 0xc417, 0x21, 0 - .dw 0x0051, 0xc417, 0x0051, 0xc417, 0x21, 0 - .dw 0x0053, 0xc417, 0x007f, 0xc417, 0x21, 0 - .dw 0x0081, 0xc417, 0x0081, 0xc417, 0x21, 0 - .dw 0x0083, 0xc417, 0x008f, 0xc417, 0x21, 0 - .dw 0x0091, 0xc417, 0x0091, 0xc417, 0x21, 0 - .dw 0x0093, 0xc417, 0x00bf, 0xc417, 0x21, 0 - .dw 0x00c1, 0xc417, 0x00c1, 0xc417, 0x21, 0 - .dw 0x00c3, 0xc417, 0x00cf, 0xc417, 0x21, 0 - .dw 0x00d1, 0xc417, 0x00d1, 0xc417, 0x21, 0 - .dw 0x00d3, 0xc417, 0x00ff, 0xc417, 0x21, 0 - .dw 0x0101, 0xc417, 0x0101, 0xc417, 0x21, 0 - .dw 0x0103, 0xc417, 0x010f, 0xc417, 0x21, 0 - .dw 0x0111, 0xc417, 0x0111, 0xc417, 0x21, 0 - .dw 0x0113, 0xc417, 0x013f, 0xc417, 0x21, 0 - .dw 0x0141, 0xc417, 0x0141, 0xc417, 0x21, 0 - .dw 0x0143, 0xc417, 0x014f, 0xc417, 0x21, 0 - .dw 0x0151, 0xc417, 0x0151, 0xc417, 0x21, 0 - .dw 0x0153, 0xc417, 0x017f, 0xc417, 0x21, 0 - .dw 0x0181, 0xc417, 0x0181, 0xc417, 0x21, 0 - .dw 0x0183, 0xc417, 0x018f, 0xc417, 0x21, 0 - .dw 0x0191, 0xc417, 0x0191, 0xc417, 0x21, 0 - .dw 0x0193, 0xc417, 0x01bf, 0xc417, 0x21, 0 - .dw 0x01c1, 0xc417, 0x01c1, 0xc417, 0x21, 0 - .dw 0x01c3, 0xc417, 0x01cf, 0xc417, 0x21, 0 - .dw 0x01d1, 0xc417, 0x01d1, 0xc417, 0x21, 0 - .dw 0x01d3, 0xc417, 0x01ff, 0xc417, 0x21, 0 - .dw 0x0201, 0xc417, 0x0201, 0xc417, 0x21, 0 - .dw 0x0203, 0xc417, 0x020f, 0xc417, 0x21, 0 - .dw 0x0211, 0xc417, 0x0211, 0xc417, 0x21, 0 - .dw 0x0213, 0xc417, 0x023f, 0xc417, 0x21, 0 - .dw 0x0241, 0xc417, 0x0241, 0xc417, 0x21, 0 - .dw 0x0243, 0xc417, 0x024f, 0xc417, 0x21, 0 - .dw 0x0251, 0xc417, 0x0251, 0xc417, 0x21, 0 - .dw 0x0253, 0xc417, 0x027f, 0xc417, 0x21, 0 - .dw 0x0281, 0xc417, 0x0281, 0xc417, 0x21, 0 - .dw 0x0283, 0xc417, 0x028f, 0xc417, 0x21, 0 - .dw 0x0291, 0xc417, 0x0291, 0xc417, 0x21, 0 - .dw 0x0293, 0xc417, 0x02bf, 0xc417, 0x21, 0 - .dw 0x02c1, 0xc417, 0x02c1, 0xc417, 0x21, 0 - .dw 0x02c3, 0xc417, 0x02cf, 0xc417, 0x21, 0 - .dw 0x02d1, 0xc417, 0x02d1, 0xc417, 0x21, 0 - .dw 0x02d3, 0xc417, 0x02ff, 0xc417, 0x21, 0 - .dw 0x0301, 0xc417, 0x0301, 0xc417, 0x21, 0 - .dw 0x0303, 0xc417, 0x030f, 0xc417, 0x21, 0 - .dw 0x0311, 0xc417, 0x0311, 0xc417, 0x21, 0 - .dw 0x0313, 0xc417, 0x033f, 0xc417, 0x21, 0 - .dw 0x0341, 0xc417, 0x0341, 0xc417, 0x21, 0 - .dw 0x0343, 0xc417, 0x034f, 0xc417, 0x21, 0 - .dw 0x0351, 0xc417, 0x0351, 0xc417, 0x21, 0 - .dw 0x0353, 0xc417, 0x037f, 0xc417, 0x21, 0 - .dw 0x0381, 0xc417, 0x0381, 0xc417, 0x21, 0 - .dw 0x0383, 0xc417, 0x038f, 0xc417, 0x21, 0 - .dw 0x0391, 0xc417, 0x0391, 0xc417, 0x21, 0 - .dw 0x0393, 0xc417, 0x03bf, 0xc417, 0x21, 0 - .dw 0x03c1, 0xc417, 0x03c1, 0xc417, 0x21, 0 - .dw 0x03c3, 0xc417, 0x03cf, 0xc417, 0x21, 0 - .dw 0x03d1, 0xc417, 0x03d1, 0xc417, 0x21, 0 - .dw 0x03d3, 0xc417, 0x03ff, 0xc417, 0x21, 0 - .dw 0x0401, 0xc417, 0x0401, 0xc417, 0x21, 0 - .dw 0x0403, 0xc417, 0x040f, 0xc417, 0x21, 0 - .dw 0x0411, 0xc417, 0x0411, 0xc417, 0x21, 0 - .dw 0x0413, 0xc417, 0x043f, 0xc417, 0x21, 0 - .dw 0x0441, 0xc417, 0x0441, 0xc417, 0x21, 0 - .dw 0x0443, 0xc417, 0x044f, 0xc417, 0x21, 0 - .dw 0x0451, 0xc417, 0x0451, 0xc417, 0x21, 0 - .dw 0x0453, 0xc417, 0x047f, 0xc417, 0x21, 0 - .dw 0x0481, 0xc417, 0x0481, 0xc417, 0x21, 0 - .dw 0x0483, 0xc417, 0x048f, 0xc417, 0x21, 0 - .dw 0x0491, 0xc417, 0x0491, 0xc417, 0x21, 0 - .dw 0x0493, 0xc417, 0x04bf, 0xc417, 0x21, 0 - .dw 0x04c1, 0xc417, 0x04c1, 0xc417, 0x21, 0 - .dw 0x04c3, 0xc417, 0x04cf, 0xc417, 0x21, 0 - .dw 0x04d1, 0xc417, 0x04d1, 0xc417, 0x21, 0 - .dw 0x04d3, 0xc417, 0x04ff, 0xc417, 0x21, 0 - .dw 0x0501, 0xc417, 0x0501, 0xc417, 0x21, 0 - .dw 0x0503, 0xc417, 0x050f, 0xc417, 0x21, 0 - .dw 0x0511, 0xc417, 0x0511, 0xc417, 0x21, 0 - .dw 0x0513, 0xc417, 0x053f, 0xc417, 0x21, 0 - .dw 0x0541, 0xc417, 0x0541, 0xc417, 0x21, 0 - .dw 0x0543, 0xc417, 0x054f, 0xc417, 0x21, 0 - .dw 0x0551, 0xc417, 0x0551, 0xc417, 0x21, 0 - .dw 0x0553, 0xc417, 0x057f, 0xc417, 0x21, 0 - .dw 0x0581, 0xc417, 0x0581, 0xc417, 0x21, 0 - .dw 0x0583, 0xc417, 0x058f, 0xc417, 0x21, 0 - .dw 0x0591, 0xc417, 0x0591, 0xc417, 0x21, 0 - .dw 0x0593, 0xc417, 0x05bf, 0xc417, 0x21, 0 - .dw 0x05c1, 0xc417, 0x05c1, 0xc417, 0x21, 0 - .dw 0x05c3, 0xc417, 0x05cf, 0xc417, 0x21, 0 - .dw 0x05d1, 0xc417, 0x05d1, 0xc417, 0x21, 0 - .dw 0x05d3, 0xc417, 0x05ff, 0xc417, 0x21, 0 - .dw 0x0601, 0xc417, 0x0601, 0xc417, 0x21, 0 - .dw 0x0603, 0xc417, 0x060f, 0xc417, 0x21, 0 - .dw 0x0611, 0xc417, 0x0611, 0xc417, 0x21, 0 - .dw 0x0613, 0xc417, 0x063f, 0xc417, 0x21, 0 - .dw 0x0641, 0xc417, 0x0641, 0xc417, 0x21, 0 - .dw 0x0643, 0xc417, 0x064f, 0xc417, 0x21, 0 - .dw 0x0651, 0xc417, 0x0651, 0xc417, 0x21, 0 - .dw 0x0653, 0xc417, 0x067f, 0xc417, 0x21, 0 - .dw 0x0681, 0xc417, 0x0681, 0xc417, 0x21, 0 - .dw 0x0683, 0xc417, 0x068f, 0xc417, 0x21, 0 - .dw 0x0691, 0xc417, 0x0691, 0xc417, 0x21, 0 - .dw 0x0693, 0xc417, 0x06bf, 0xc417, 0x21, 0 - .dw 0x06c1, 0xc417, 0x06c1, 0xc417, 0x21, 0 - .dw 0x06c3, 0xc417, 0x06cf, 0xc417, 0x21, 0 - .dw 0x06d1, 0xc417, 0x06d1, 0xc417, 0x21, 0 - .dw 0x06d3, 0xc417, 0x06ff, 0xc417, 0x21, 0 - .dw 0x0701, 0xc417, 0x0701, 0xc417, 0x21, 0 - .dw 0x0703, 0xc417, 0x070f, 0xc417, 0x21, 0 - .dw 0x0711, 0xc417, 0x0711, 0xc417, 0x21, 0 - .dw 0x0713, 0xc417, 0x073f, 0xc417, 0x21, 0 - .dw 0x0741, 0xc417, 0x0741, 0xc417, 0x21, 0 - .dw 0x0743, 0xc417, 0x074f, 0xc417, 0x21, 0 - .dw 0x0751, 0xc417, 0x0751, 0xc417, 0x21, 0 - .dw 0x0753, 0xc417, 0x077f, 0xc417, 0x21, 0 - .dw 0x0781, 0xc417, 0x0781, 0xc417, 0x21, 0 - .dw 0x0783, 0xc417, 0x078f, 0xc417, 0x21, 0 - .dw 0x0791, 0xc417, 0x0791, 0xc417, 0x21, 0 - .dw 0x0793, 0xc417, 0x07bf, 0xc417, 0x21, 0 - .dw 0x07c1, 0xc417, 0x07c1, 0xc417, 0x21, 0 - .dw 0x07c3, 0xc417, 0x07cf, 0xc417, 0x21, 0 - .dw 0x07d1, 0xc417, 0x07d1, 0xc417, 0x21, 0 - .dw 0x07d3, 0xc417, 0x07ff, 0xc417, 0x21, 0 - .dw 0x0801, 0xc417, 0x0801, 0xc417, 0x21, 0 - .dw 0x0803, 0xc417, 0x080f, 0xc417, 0x21, 0 - .dw 0x0811, 0xc417, 0x0811, 0xc417, 0x21, 0 - .dw 0x0813, 0xc417, 0x083f, 0xc417, 0x21, 0 - .dw 0x0841, 0xc417, 0x0841, 0xc417, 0x21, 0 - .dw 0x0843, 0xc417, 0x084f, 0xc417, 0x21, 0 - .dw 0x0851, 0xc417, 0x0851, 0xc417, 0x21, 0 - .dw 0x0853, 0xc417, 0x087f, 0xc417, 0x21, 0 - .dw 0x0881, 0xc417, 0x0881, 0xc417, 0x21, 0 - .dw 0x0883, 0xc417, 0x088f, 0xc417, 0x21, 0 - .dw 0x0891, 0xc417, 0x0891, 0xc417, 0x21, 0 - .dw 0x0893, 0xc417, 0x08bf, 0xc417, 0x21, 0 - .dw 0x08c1, 0xc417, 0x08c1, 0xc417, 0x21, 0 - .dw 0x08c3, 0xc417, 0x08cf, 0xc417, 0x21, 0 - .dw 0x08d1, 0xc417, 0x08d1, 0xc417, 0x21, 0 - .dw 0x08d3, 0xc417, 0x08ff, 0xc417, 0x21, 0 - .dw 0x0901, 0xc417, 0x0901, 0xc417, 0x21, 0 - .dw 0x0903, 0xc417, 0x090f, 0xc417, 0x21, 0 - .dw 0x0911, 0xc417, 0x0911, 0xc417, 0x21, 0 - .dw 0x0913, 0xc417, 0x093f, 0xc417, 0x21, 0 - .dw 0x0941, 0xc417, 0x0941, 0xc417, 0x21, 0 - .dw 0x0943, 0xc417, 0x094f, 0xc417, 0x21, 0 - .dw 0x0951, 0xc417, 0x0951, 0xc417, 0x21, 0 - .dw 0x0953, 0xc417, 0x097f, 0xc417, 0x21, 0 - .dw 0x0981, 0xc417, 0x0981, 0xc417, 0x21, 0 - .dw 0x0983, 0xc417, 0x098f, 0xc417, 0x21, 0 - .dw 0x0991, 0xc417, 0x0991, 0xc417, 0x21, 0 - .dw 0x0993, 0xc417, 0x09bf, 0xc417, 0x21, 0 - .dw 0x09c1, 0xc417, 0x09c1, 0xc417, 0x21, 0 - .dw 0x09c3, 0xc417, 0x09cf, 0xc417, 0x21, 0 - .dw 0x09d1, 0xc417, 0x09d1, 0xc417, 0x21, 0 - .dw 0x09d3, 0xc417, 0x09ff, 0xc417, 0x21, 0 - .dw 0x0a01, 0xc417, 0x0a01, 0xc417, 0x21, 0 - .dw 0x0a03, 0xc417, 0x0a0f, 0xc417, 0x21, 0 - .dw 0x0a11, 0xc417, 0x0a11, 0xc417, 0x21, 0 - .dw 0x0a13, 0xc417, 0x0a3f, 0xc417, 0x21, 0 - .dw 0x0a41, 0xc417, 0x0a41, 0xc417, 0x21, 0 - .dw 0x0a43, 0xc417, 0x0a4f, 0xc417, 0x21, 0 - .dw 0x0a51, 0xc417, 0x0a51, 0xc417, 0x21, 0 - .dw 0x0a53, 0xc417, 0x0a7f, 0xc417, 0x21, 0 - .dw 0x0a81, 0xc417, 0x0a81, 0xc417, 0x21, 0 - .dw 0x0a83, 0xc417, 0x0a8f, 0xc417, 0x21, 0 - .dw 0x0a91, 0xc417, 0x0a91, 0xc417, 0x21, 0 - .dw 0x0a93, 0xc417, 0x0abf, 0xc417, 0x21, 0 - .dw 0x0ac1, 0xc417, 0x0ac1, 0xc417, 0x21, 0 - .dw 0x0ac3, 0xc417, 0x0acf, 0xc417, 0x21, 0 - .dw 0x0ad1, 0xc417, 0x0ad1, 0xc417, 0x21, 0 - .dw 0x0ad3, 0xc417, 0x0aff, 0xc417, 0x21, 0 - .dw 0x0b01, 0xc417, 0x0b01, 0xc417, 0x21, 0 - .dw 0x0b03, 0xc417, 0x0b0f, 0xc417, 0x21, 0 - .dw 0x0b11, 0xc417, 0x0b11, 0xc417, 0x21, 0 - .dw 0x0b13, 0xc417, 0x0b3f, 0xc417, 0x21, 0 - .dw 0x0b41, 0xc417, 0x0b41, 0xc417, 0x21, 0 - .dw 0x0b43, 0xc417, 0x0b4f, 0xc417, 0x21, 0 - .dw 0x0b51, 0xc417, 0x0b51, 0xc417, 0x21, 0 - .dw 0x0b53, 0xc417, 0x0b7f, 0xc417, 0x21, 0 - .dw 0x0b81, 0xc417, 0x0b81, 0xc417, 0x21, 0 - .dw 0x0b83, 0xc417, 0x0b8f, 0xc417, 0x21, 0 - .dw 0x0b91, 0xc417, 0x0b91, 0xc417, 0x21, 0 - .dw 0x0b93, 0xc417, 0x0bbf, 0xc417, 0x21, 0 - .dw 0x0bc1, 0xc417, 0x0bc1, 0xc417, 0x21, 0 - .dw 0x0bc3, 0xc417, 0x0bcf, 0xc417, 0x21, 0 - .dw 0x0bd1, 0xc417, 0x0bd1, 0xc417, 0x21, 0 - .dw 0x0bd3, 0xc417, 0x0bff, 0xc417, 0x21, 0 - .dw 0x0c01, 0xc417, 0x0c01, 0xc417, 0x21, 0 - .dw 0x0c03, 0xc417, 0x0c0f, 0xc417, 0x21, 0 - .dw 0x0c11, 0xc417, 0x0c11, 0xc417, 0x21, 0 - .dw 0x0c13, 0xc417, 0x0c3f, 0xc417, 0x21, 0 - .dw 0x0c41, 0xc417, 0x0c41, 0xc417, 0x21, 0 - .dw 0x0c43, 0xc417, 0x0c4f, 0xc417, 0x21, 0 - .dw 0x0c51, 0xc417, 0x0c51, 0xc417, 0x21, 0 - .dw 0x0c53, 0xc417, 0x0c7f, 0xc417, 0x21, 0 - .dw 0x0c81, 0xc417, 0x0c81, 0xc417, 0x21, 0 - .dw 0x0c83, 0xc417, 0x0c8f, 0xc417, 0x21, 0 - .dw 0x0c91, 0xc417, 0x0c91, 0xc417, 0x21, 0 - .dw 0x0c93, 0xc417, 0x0cbf, 0xc417, 0x21, 0 - .dw 0x0cc1, 0xc417, 0x0cc1, 0xc417, 0x21, 0 - .dw 0x0cc3, 0xc417, 0x0ccf, 0xc417, 0x21, 0 - .dw 0x0cd1, 0xc417, 0x0cd1, 0xc417, 0x21, 0 - .dw 0x0cd3, 0xc417, 0x0cff, 0xc417, 0x21, 0 - .dw 0x0d01, 0xc417, 0x0d01, 0xc417, 0x21, 0 - .dw 0x0d03, 0xc417, 0x0d0f, 0xc417, 0x21, 0 - .dw 0x0d11, 0xc417, 0x0d11, 0xc417, 0x21, 0 - .dw 0x0d13, 0xc417, 0x0d3f, 0xc417, 0x21, 0 - .dw 0x0d41, 0xc417, 0x0d41, 0xc417, 0x21, 0 - .dw 0x0d43, 0xc417, 0x0d4f, 0xc417, 0x21, 0 - .dw 0x0d51, 0xc417, 0x0d51, 0xc417, 0x21, 0 - .dw 0x0d53, 0xc417, 0x0d7f, 0xc417, 0x21, 0 - .dw 0x0d81, 0xc417, 0x0d81, 0xc417, 0x21, 0 - .dw 0x0d83, 0xc417, 0x0d8f, 0xc417, 0x21, 0 - .dw 0x0d91, 0xc417, 0x0d91, 0xc417, 0x21, 0 - .dw 0x0d93, 0xc417, 0x0dbf, 0xc417, 0x21, 0 - .dw 0x0dc1, 0xc417, 0x0dc1, 0xc417, 0x21, 0 - .dw 0x0dc3, 0xc417, 0x0dcf, 0xc417, 0x21, 0 - .dw 0x0dd1, 0xc417, 0x0dd1, 0xc417, 0x21, 0 - .dw 0x0dd3, 0xc417, 0x0dff, 0xc417, 0x21, 0 - .dw 0x0e01, 0xc417, 0x0e01, 0xc417, 0x21, 0 - .dw 0x0e03, 0xc417, 0x0e0f, 0xc417, 0x21, 0 - .dw 0x0e11, 0xc417, 0x0e11, 0xc417, 0x21, 0 - .dw 0x0e13, 0xc417, 0x0e3f, 0xc417, 0x21, 0 - .dw 0x0e41, 0xc417, 0x0e41, 0xc417, 0x21, 0 - .dw 0x0e43, 0xc417, 0x0e4f, 0xc417, 0x21, 0 - .dw 0x0e51, 0xc417, 0x0e51, 0xc417, 0x21, 0 - .dw 0x0e53, 0xc417, 0x0e7f, 0xc417, 0x21, 0 - .dw 0x0e81, 0xc417, 0x0e81, 0xc417, 0x21, 0 - .dw 0x0e83, 0xc417, 0x0e8f, 0xc417, 0x21, 0 - .dw 0x0e91, 0xc417, 0x0e91, 0xc417, 0x21, 0 - .dw 0x0e93, 0xc417, 0x0ebf, 0xc417, 0x21, 0 - .dw 0x0ec1, 0xc417, 0x0ec1, 0xc417, 0x21, 0 - .dw 0x0ec3, 0xc417, 0x0ecf, 0xc417, 0x21, 0 - .dw 0x0ed1, 0xc417, 0x0ed1, 0xc417, 0x21, 0 - .dw 0x0ed3, 0xc417, 0x0eff, 0xc417, 0x21, 0 - .dw 0x0f01, 0xc417, 0x0f01, 0xc417, 0x21, 0 - .dw 0x0f03, 0xc417, 0x0f0f, 0xc417, 0x21, 0 - .dw 0x0f11, 0xc417, 0x0f11, 0xc417, 0x21, 0 - .dw 0x0f13, 0xc417, 0x0f3f, 0xc417, 0x21, 0 - .dw 0x0f41, 0xc417, 0x0f41, 0xc417, 0x21, 0 - .dw 0x0f43, 0xc417, 0x0f4f, 0xc417, 0x21, 0 - .dw 0x0f51, 0xc417, 0x0f51, 0xc417, 0x21, 0 - .dw 0x0f53, 0xc417, 0x0f7f, 0xc417, 0x21, 0 - .dw 0x0f81, 0xc417, 0x0f81, 0xc417, 0x21, 0 - .dw 0x0f83, 0xc417, 0x0f8f, 0xc417, 0x21, 0 - .dw 0x0f91, 0xc417, 0x0f91, 0xc417, 0x21, 0 - .dw 0x0f93, 0xc417, 0x0fbf, 0xc417, 0x21, 0 - .dw 0x0fc1, 0xc417, 0x0fc1, 0xc417, 0x21, 0 - .dw 0x0fc3, 0xc417, 0x0fcf, 0xc417, 0x21, 0 - .dw 0x0fd1, 0xc417, 0x0fd1, 0xc417, 0x21, 0 - .dw 0x0fd3, 0xc417, 0x1fff, 0xc417, 0x21, 0 - .dw 0x2001, 0xc417, 0x2001, 0xc417, 0x21, 0 - .dw 0x2003, 0xc417, 0x200f, 0xc417, 0x21, 0 - .dw 0x2011, 0xc417, 0x2011, 0xc417, 0x21, 0 - .dw 0x2013, 0xc417, 0x203f, 0xc417, 0x21, 0 - .dw 0x2041, 0xc417, 0x2041, 0xc417, 0x21, 0 - .dw 0x2043, 0xc417, 0x204f, 0xc417, 0x21, 0 - .dw 0x2051, 0xc417, 0x2051, 0xc417, 0x21, 0 - .dw 0x2053, 0xc417, 0x207f, 0xc417, 0x21, 0 - .dw 0x2081, 0xc417, 0x2081, 0xc417, 0x21, 0 - .dw 0x2083, 0xc417, 0x208f, 0xc417, 0x21, 0 - .dw 0x2091, 0xc417, 0x2091, 0xc417, 0x21, 0 - .dw 0x2093, 0xc417, 0x20bf, 0xc417, 0x21, 0 - .dw 0x20c1, 0xc417, 0x20c1, 0xc417, 0x21, 0 - .dw 0x20c3, 0xc417, 0x20cf, 0xc417, 0x21, 0 - .dw 0x20d1, 0xc417, 0x20d1, 0xc417, 0x21, 0 - .dw 0x20d3, 0xc417, 0x20ff, 0xc417, 0x21, 0 - .dw 0x2101, 0xc417, 0x2101, 0xc417, 0x21, 0 - .dw 0x2103, 0xc417, 0x210f, 0xc417, 0x21, 0 - .dw 0x2111, 0xc417, 0x2111, 0xc417, 0x21, 0 - .dw 0x2113, 0xc417, 0x213f, 0xc417, 0x21, 0 - .dw 0x2141, 0xc417, 0x2141, 0xc417, 0x21, 0 - .dw 0x2143, 0xc417, 0x214f, 0xc417, 0x21, 0 - .dw 0x2151, 0xc417, 0x2151, 0xc417, 0x21, 0 - .dw 0x2153, 0xc417, 0x217f, 0xc417, 0x21, 0 - .dw 0x2181, 0xc417, 0x2181, 0xc417, 0x21, 0 - .dw 0x2183, 0xc417, 0x218f, 0xc417, 0x21, 0 - .dw 0x2191, 0xc417, 0x2191, 0xc417, 0x21, 0 - .dw 0x2193, 0xc417, 0x21bf, 0xc417, 0x21, 0 - .dw 0x21c1, 0xc417, 0x21c1, 0xc417, 0x21, 0 - .dw 0x21c3, 0xc417, 0x21cf, 0xc417, 0x21, 0 - .dw 0x21d1, 0xc417, 0x21d1, 0xc417, 0x21, 0 - .dw 0x21d3, 0xc417, 0x21ff, 0xc417, 0x21, 0 - .dw 0x2201, 0xc417, 0x2201, 0xc417, 0x21, 0 - .dw 0x2203, 0xc417, 0x220f, 0xc417, 0x21, 0 - .dw 0x2211, 0xc417, 0x2211, 0xc417, 0x21, 0 - .dw 0x2213, 0xc417, 0x223f, 0xc417, 0x21, 0 - .dw 0x2241, 0xc417, 0x2241, 0xc417, 0x21, 0 - .dw 0x2243, 0xc417, 0x224f, 0xc417, 0x21, 0 - .dw 0x2251, 0xc417, 0x2251, 0xc417, 0x21, 0 - .dw 0x2253, 0xc417, 0x227f, 0xc417, 0x21, 0 - .dw 0x2281, 0xc417, 0x2281, 0xc417, 0x21, 0 - .dw 0x2283, 0xc417, 0x228f, 0xc417, 0x21, 0 - .dw 0x2291, 0xc417, 0x2291, 0xc417, 0x21, 0 - .dw 0x2293, 0xc417, 0x22bf, 0xc417, 0x21, 0 - .dw 0x22c1, 0xc417, 0x22c1, 0xc417, 0x21, 0 - .dw 0x22c3, 0xc417, 0x22cf, 0xc417, 0x21, 0 - .dw 0x22d1, 0xc417, 0x22d1, 0xc417, 0x21, 0 - .dw 0x22d3, 0xc417, 0x22ff, 0xc417, 0x21, 0 - .dw 0x2301, 0xc417, 0x2301, 0xc417, 0x21, 0 - .dw 0x2303, 0xc417, 0x230f, 0xc417, 0x21, 0 - .dw 0x2311, 0xc417, 0x2311, 0xc417, 0x21, 0 - .dw 0x2313, 0xc417, 0x233f, 0xc417, 0x21, 0 - .dw 0x2341, 0xc417, 0x2341, 0xc417, 0x21, 0 - .dw 0x2343, 0xc417, 0x234f, 0xc417, 0x21, 0 - .dw 0x2351, 0xc417, 0x2351, 0xc417, 0x21, 0 - .dw 0x2353, 0xc417, 0x237f, 0xc417, 0x21, 0 - .dw 0x2381, 0xc417, 0x2381, 0xc417, 0x21, 0 - .dw 0x2383, 0xc417, 0x238f, 0xc417, 0x21, 0 - .dw 0x2391, 0xc417, 0x2391, 0xc417, 0x21, 0 - .dw 0x2393, 0xc417, 0x23bf, 0xc417, 0x21, 0 - .dw 0x23c1, 0xc417, 0x23c1, 0xc417, 0x21, 0 - .dw 0x23c3, 0xc417, 0x23cf, 0xc417, 0x21, 0 - .dw 0x23d1, 0xc417, 0x23d1, 0xc417, 0x21, 0 - .dw 0x23d3, 0xc417, 0x23ff, 0xc417, 0x21, 0 - .dw 0x2401, 0xc417, 0x2401, 0xc417, 0x21, 0 - .dw 0x2403, 0xc417, 0x240f, 0xc417, 0x21, 0 - .dw 0x2411, 0xc417, 0x2411, 0xc417, 0x21, 0 - .dw 0x2413, 0xc417, 0x243f, 0xc417, 0x21, 0 - .dw 0x2441, 0xc417, 0x2441, 0xc417, 0x21, 0 - .dw 0x2443, 0xc417, 0x244f, 0xc417, 0x21, 0 - .dw 0x2451, 0xc417, 0x2451, 0xc417, 0x21, 0 - .dw 0x2453, 0xc417, 0x247f, 0xc417, 0x21, 0 - .dw 0x2481, 0xc417, 0x2481, 0xc417, 0x21, 0 - .dw 0x2483, 0xc417, 0x248f, 0xc417, 0x21, 0 - .dw 0x2491, 0xc417, 0x2491, 0xc417, 0x21, 0 - .dw 0x2493, 0xc417, 0x24bf, 0xc417, 0x21, 0 - .dw 0x24c1, 0xc417, 0x24c1, 0xc417, 0x21, 0 - .dw 0x24c3, 0xc417, 0x24cf, 0xc417, 0x21, 0 - .dw 0x24d1, 0xc417, 0x24d1, 0xc417, 0x21, 0 - .dw 0x24d3, 0xc417, 0x24ff, 0xc417, 0x21, 0 - .dw 0x2501, 0xc417, 0x2501, 0xc417, 0x21, 0 - .dw 0x2503, 0xc417, 0x250f, 0xc417, 0x21, 0 - .dw 0x2511, 0xc417, 0x2511, 0xc417, 0x21, 0 - .dw 0x2513, 0xc417, 0x253f, 0xc417, 0x21, 0 - .dw 0x2541, 0xc417, 0x2541, 0xc417, 0x21, 0 - .dw 0x2543, 0xc417, 0x254f, 0xc417, 0x21, 0 - .dw 0x2551, 0xc417, 0x2551, 0xc417, 0x21, 0 - .dw 0x2553, 0xc417, 0x257f, 0xc417, 0x21, 0 - .dw 0x2581, 0xc417, 0x2581, 0xc417, 0x21, 0 - .dw 0x2583, 0xc417, 0x258f, 0xc417, 0x21, 0 - .dw 0x2591, 0xc417, 0x2591, 0xc417, 0x21, 0 - .dw 0x2593, 0xc417, 0x25bf, 0xc417, 0x21, 0 - .dw 0x25c1, 0xc417, 0x25c1, 0xc417, 0x21, 0 - .dw 0x25c3, 0xc417, 0x25cf, 0xc417, 0x21, 0 - .dw 0x25d1, 0xc417, 0x25d1, 0xc417, 0x21, 0 - .dw 0x25d3, 0xc417, 0x25ff, 0xc417, 0x21, 0 - .dw 0x2601, 0xc417, 0x2601, 0xc417, 0x21, 0 - .dw 0x2603, 0xc417, 0x260f, 0xc417, 0x21, 0 - .dw 0x2611, 0xc417, 0x2611, 0xc417, 0x21, 0 - .dw 0x2613, 0xc417, 0x263f, 0xc417, 0x21, 0 - .dw 0x2641, 0xc417, 0x2641, 0xc417, 0x21, 0 - .dw 0x2643, 0xc417, 0x264f, 0xc417, 0x21, 0 - .dw 0x2651, 0xc417, 0x2651, 0xc417, 0x21, 0 - .dw 0x2653, 0xc417, 0x267f, 0xc417, 0x21, 0 - .dw 0x2681, 0xc417, 0x2681, 0xc417, 0x21, 0 - .dw 0x2683, 0xc417, 0x268f, 0xc417, 0x21, 0 - .dw 0x2691, 0xc417, 0x2691, 0xc417, 0x21, 0 - .dw 0x2693, 0xc417, 0x26bf, 0xc417, 0x21, 0 - .dw 0x26c1, 0xc417, 0x26c1, 0xc417, 0x21, 0 - .dw 0x26c3, 0xc417, 0x26cf, 0xc417, 0x21, 0 - .dw 0x26d1, 0xc417, 0x26d1, 0xc417, 0x21, 0 - .dw 0x26d3, 0xc417, 0x26ff, 0xc417, 0x21, 0 - .dw 0x2701, 0xc417, 0x2701, 0xc417, 0x21, 0 - .dw 0x2703, 0xc417, 0x270f, 0xc417, 0x21, 0 - .dw 0x2711, 0xc417, 0x2711, 0xc417, 0x21, 0 - .dw 0x2713, 0xc417, 0x273f, 0xc417, 0x21, 0 - .dw 0x2741, 0xc417, 0x2741, 0xc417, 0x21, 0 - .dw 0x2743, 0xc417, 0x274f, 0xc417, 0x21, 0 - .dw 0x2751, 0xc417, 0x2751, 0xc417, 0x21, 0 - .dw 0x2753, 0xc417, 0x277f, 0xc417, 0x21, 0 - .dw 0x2781, 0xc417, 0x2781, 0xc417, 0x21, 0 - .dw 0x2783, 0xc417, 0x278f, 0xc417, 0x21, 0 - .dw 0x2791, 0xc417, 0x2791, 0xc417, 0x21, 0 - .dw 0x2793, 0xc417, 0x27bf, 0xc417, 0x21, 0 - .dw 0x27c1, 0xc417, 0x27c1, 0xc417, 0x21, 0 - .dw 0x27c3, 0xc417, 0x27cf, 0xc417, 0x21, 0 - .dw 0x27d1, 0xc417, 0x27d1, 0xc417, 0x21, 0 - .dw 0x27d3, 0xc417, 0x27ff, 0xc417, 0x21, 0 - .dw 0x2801, 0xc417, 0x2801, 0xc417, 0x21, 0 - .dw 0x2803, 0xc417, 0x280f, 0xc417, 0x21, 0 - .dw 0x2811, 0xc417, 0x2811, 0xc417, 0x21, 0 - .dw 0x2813, 0xc417, 0x283f, 0xc417, 0x21, 0 - .dw 0x2841, 0xc417, 0x2841, 0xc417, 0x21, 0 - .dw 0x2843, 0xc417, 0x284f, 0xc417, 0x21, 0 - .dw 0x2851, 0xc417, 0x2851, 0xc417, 0x21, 0 - .dw 0x2853, 0xc417, 0x287f, 0xc417, 0x21, 0 - .dw 0x2881, 0xc417, 0x2881, 0xc417, 0x21, 0 - .dw 0x2883, 0xc417, 0x288f, 0xc417, 0x21, 0 - .dw 0x2891, 0xc417, 0x2891, 0xc417, 0x21, 0 - .dw 0x2893, 0xc417, 0x28bf, 0xc417, 0x21, 0 - .dw 0x28c1, 0xc417, 0x28c1, 0xc417, 0x21, 0 - .dw 0x28c3, 0xc417, 0x28cf, 0xc417, 0x21, 0 - .dw 0x28d1, 0xc417, 0x28d1, 0xc417, 0x21, 0 - .dw 0x28d3, 0xc417, 0x28ff, 0xc417, 0x21, 0 - .dw 0x2901, 0xc417, 0x2901, 0xc417, 0x21, 0 - .dw 0x2903, 0xc417, 0x290f, 0xc417, 0x21, 0 - .dw 0x2911, 0xc417, 0x2911, 0xc417, 0x21, 0 - .dw 0x2913, 0xc417, 0x293f, 0xc417, 0x21, 0 - .dw 0x2941, 0xc417, 0x2941, 0xc417, 0x21, 0 - .dw 0x2943, 0xc417, 0x294f, 0xc417, 0x21, 0 - .dw 0x2951, 0xc417, 0x2951, 0xc417, 0x21, 0 - .dw 0x2953, 0xc417, 0x297f, 0xc417, 0x21, 0 - .dw 0x2981, 0xc417, 0x2981, 0xc417, 0x21, 0 - .dw 0x2983, 0xc417, 0x298f, 0xc417, 0x21, 0 - .dw 0x2991, 0xc417, 0x2991, 0xc417, 0x21, 0 - .dw 0x2993, 0xc417, 0x29bf, 0xc417, 0x21, 0 - .dw 0x29c1, 0xc417, 0x29c1, 0xc417, 0x21, 0 - .dw 0x29c3, 0xc417, 0x29cf, 0xc417, 0x21, 0 - .dw 0x29d1, 0xc417, 0x29d1, 0xc417, 0x21, 0 - .dw 0x29d3, 0xc417, 0x29ff, 0xc417, 0x21, 0 - .dw 0x2a01, 0xc417, 0x2a01, 0xc417, 0x21, 0 - .dw 0x2a03, 0xc417, 0x2a0f, 0xc417, 0x21, 0 - .dw 0x2a11, 0xc417, 0x2a11, 0xc417, 0x21, 0 - .dw 0x2a13, 0xc417, 0x2a3f, 0xc417, 0x21, 0 - .dw 0x2a41, 0xc417, 0x2a41, 0xc417, 0x21, 0 - .dw 0x2a43, 0xc417, 0x2a4f, 0xc417, 0x21, 0 - .dw 0x2a51, 0xc417, 0x2a51, 0xc417, 0x21, 0 - .dw 0x2a53, 0xc417, 0x2a7f, 0xc417, 0x21, 0 - .dw 0x2a81, 0xc417, 0x2a81, 0xc417, 0x21, 0 - .dw 0x2a83, 0xc417, 0x2a8f, 0xc417, 0x21, 0 - .dw 0x2a91, 0xc417, 0x2a91, 0xc417, 0x21, 0 - .dw 0x2a93, 0xc417, 0x2abf, 0xc417, 0x21, 0 - .dw 0x2ac1, 0xc417, 0x2ac1, 0xc417, 0x21, 0 - .dw 0x2ac3, 0xc417, 0x2acf, 0xc417, 0x21, 0 - .dw 0x2ad1, 0xc417, 0x2ad1, 0xc417, 0x21, 0 - .dw 0x2ad3, 0xc417, 0x2aff, 0xc417, 0x21, 0 - .dw 0x2b01, 0xc417, 0x2b01, 0xc417, 0x21, 0 - .dw 0x2b03, 0xc417, 0x2b0f, 0xc417, 0x21, 0 - .dw 0x2b11, 0xc417, 0x2b11, 0xc417, 0x21, 0 - .dw 0x2b13, 0xc417, 0x2b3f, 0xc417, 0x21, 0 - .dw 0x2b41, 0xc417, 0x2b41, 0xc417, 0x21, 0 - .dw 0x2b43, 0xc417, 0x2b4f, 0xc417, 0x21, 0 - .dw 0x2b51, 0xc417, 0x2b51, 0xc417, 0x21, 0 - .dw 0x2b53, 0xc417, 0x2b7f, 0xc417, 0x21, 0 - .dw 0x2b81, 0xc417, 0x2b81, 0xc417, 0x21, 0 - .dw 0x2b83, 0xc417, 0x2b8f, 0xc417, 0x21, 0 - .dw 0x2b91, 0xc417, 0x2b91, 0xc417, 0x21, 0 - .dw 0x2b93, 0xc417, 0x2bbf, 0xc417, 0x21, 0 - .dw 0x2bc1, 0xc417, 0x2bc1, 0xc417, 0x21, 0 - .dw 0x2bc3, 0xc417, 0x2bcf, 0xc417, 0x21, 0 - .dw 0x2bd1, 0xc417, 0x2bd1, 0xc417, 0x21, 0 - .dw 0x2bd3, 0xc417, 0x2bff, 0xc417, 0x21, 0 - .dw 0x2c01, 0xc417, 0x2c01, 0xc417, 0x21, 0 - .dw 0x2c03, 0xc417, 0x2c0f, 0xc417, 0x21, 0 - .dw 0x2c11, 0xc417, 0x2c11, 0xc417, 0x21, 0 - .dw 0x2c13, 0xc417, 0x2c3f, 0xc417, 0x21, 0 - .dw 0x2c41, 0xc417, 0x2c41, 0xc417, 0x21, 0 - .dw 0x2c43, 0xc417, 0x2c4f, 0xc417, 0x21, 0 - .dw 0x2c51, 0xc417, 0x2c51, 0xc417, 0x21, 0 - .dw 0x2c53, 0xc417, 0x2c7f, 0xc417, 0x21, 0 - .dw 0x2c81, 0xc417, 0x2c81, 0xc417, 0x21, 0 - .dw 0x2c83, 0xc417, 0x2c8f, 0xc417, 0x21, 0 - .dw 0x2c91, 0xc417, 0x2c91, 0xc417, 0x21, 0 - .dw 0x2c93, 0xc417, 0x2cbf, 0xc417, 0x21, 0 - .dw 0x2cc1, 0xc417, 0x2cc1, 0xc417, 0x21, 0 - .dw 0x2cc3, 0xc417, 0x2ccf, 0xc417, 0x21, 0 - .dw 0x2cd1, 0xc417, 0x2cd1, 0xc417, 0x21, 0 - .dw 0x2cd3, 0xc417, 0x2cff, 0xc417, 0x21, 0 - .dw 0x2d01, 0xc417, 0x2d01, 0xc417, 0x21, 0 - .dw 0x2d03, 0xc417, 0x2d0f, 0xc417, 0x21, 0 - .dw 0x2d11, 0xc417, 0x2d11, 0xc417, 0x21, 0 - .dw 0x2d13, 0xc417, 0x2d3f, 0xc417, 0x21, 0 - .dw 0x2d41, 0xc417, 0x2d41, 0xc417, 0x21, 0 - .dw 0x2d43, 0xc417, 0x2d4f, 0xc417, 0x21, 0 - .dw 0x2d51, 0xc417, 0x2d51, 0xc417, 0x21, 0 - .dw 0x2d53, 0xc417, 0x2d7f, 0xc417, 0x21, 0 - .dw 0x2d81, 0xc417, 0x2d81, 0xc417, 0x21, 0 - .dw 0x2d83, 0xc417, 0x2d8f, 0xc417, 0x21, 0 - .dw 0x2d91, 0xc417, 0x2d91, 0xc417, 0x21, 0 - .dw 0x2d93, 0xc417, 0x2dbf, 0xc417, 0x21, 0 - .dw 0x2dc1, 0xc417, 0x2dc1, 0xc417, 0x21, 0 - .dw 0x2dc3, 0xc417, 0x2dcf, 0xc417, 0x21, 0 - .dw 0x2dd1, 0xc417, 0x2dd1, 0xc417, 0x21, 0 - .dw 0x2dd3, 0xc417, 0x2dff, 0xc417, 0x21, 0 - .dw 0x2e01, 0xc417, 0x2e01, 0xc417, 0x21, 0 - .dw 0x2e03, 0xc417, 0x2e0f, 0xc417, 0x21, 0 - .dw 0x2e11, 0xc417, 0x2e11, 0xc417, 0x21, 0 - .dw 0x2e13, 0xc417, 0x2e3f, 0xc417, 0x21, 0 - .dw 0x2e41, 0xc417, 0x2e41, 0xc417, 0x21, 0 - .dw 0x2e43, 0xc417, 0x2e4f, 0xc417, 0x21, 0 - .dw 0x2e51, 0xc417, 0x2e51, 0xc417, 0x21, 0 - .dw 0x2e53, 0xc417, 0x2e7f, 0xc417, 0x21, 0 - .dw 0x2e81, 0xc417, 0x2e81, 0xc417, 0x21, 0 - .dw 0x2e83, 0xc417, 0x2e8f, 0xc417, 0x21, 0 - .dw 0x2e91, 0xc417, 0x2e91, 0xc417, 0x21, 0 - .dw 0x2e93, 0xc417, 0x2ebf, 0xc417, 0x21, 0 - .dw 0x2ec1, 0xc417, 0x2ec1, 0xc417, 0x21, 0 - .dw 0x2ec3, 0xc417, 0x2ecf, 0xc417, 0x21, 0 - .dw 0x2ed1, 0xc417, 0x2ed1, 0xc417, 0x21, 0 - .dw 0x2ed3, 0xc417, 0x2eff, 0xc417, 0x21, 0 - .dw 0x2f01, 0xc417, 0x2f01, 0xc417, 0x21, 0 - .dw 0x2f03, 0xc417, 0x2f0f, 0xc417, 0x21, 0 - .dw 0x2f11, 0xc417, 0x2f11, 0xc417, 0x21, 0 - .dw 0x2f13, 0xc417, 0x2f3f, 0xc417, 0x21, 0 - .dw 0x2f41, 0xc417, 0x2f41, 0xc417, 0x21, 0 - .dw 0x2f43, 0xc417, 0x2f4f, 0xc417, 0x21, 0 - .dw 0x2f51, 0xc417, 0x2f51, 0xc417, 0x21, 0 - .dw 0x2f53, 0xc417, 0x2f7f, 0xc417, 0x21, 0 - .dw 0x2f81, 0xc417, 0x2f81, 0xc417, 0x21, 0 - .dw 0x2f83, 0xc417, 0x2f8f, 0xc417, 0x21, 0 - .dw 0x2f91, 0xc417, 0x2f91, 0xc417, 0x21, 0 - .dw 0x2f93, 0xc417, 0x2fbf, 0xc417, 0x21, 0 - .dw 0x2fc1, 0xc417, 0x2fc1, 0xc417, 0x21, 0 - .dw 0x2fc3, 0xc417, 0x2fcf, 0xc417, 0x21, 0 - .dw 0x2fd1, 0xc417, 0x2fd1, 0xc417, 0x21, 0 - .dw 0x2fd3, 0xc417, 0xffff, 0xc417, 0x21, 0 - .dw 0x1000, 0xc418, 0x3fff, 0xc418, 0x21, 0 - .dw 0x4000, 0xc418, 0x4000, 0xc418, 0x22, 0 - .dw 0x4001, 0xc418, 0x4001, 0xc418, 0x21, 0 - .dw 0x4002, 0xc418, 0x4002, 0xc418, 0x22, 0 - .dw 0x4003, 0xc418, 0x400f, 0xc418, 0x21, 0 - .dw 0x4010, 0xc418, 0x4010, 0xc418, 0x22, 0 - .dw 0x4011, 0xc418, 0x4011, 0xc418, 0x21, 0 - .dw 0x4012, 0xc418, 0x4012, 0xc418, 0x22, 0 - .dw 0x4013, 0xc418, 0x403f, 0xc418, 0x21, 0 - .dw 0x4041, 0xc418, 0x4041, 0xc418, 0x21, 0 - .dw 0x4043, 0xc418, 0x404f, 0xc418, 0x21, 0 - .dw 0x4051, 0xc418, 0x4051, 0xc418, 0x21, 0 - .dw 0x4053, 0xc418, 0x407f, 0xc418, 0x21, 0 - .dw 0x4081, 0xc418, 0x4081, 0xc418, 0x21, 0 - .dw 0x4083, 0xc418, 0x408f, 0xc418, 0x21, 0 - .dw 0x4091, 0xc418, 0x4091, 0xc418, 0x21, 0 - .dw 0x4093, 0xc418, 0x40bf, 0xc418, 0x21, 0 - .dw 0x40c1, 0xc418, 0x40c1, 0xc418, 0x21, 0 - .dw 0x40c3, 0xc418, 0x40cf, 0xc418, 0x21, 0 - .dw 0x40d1, 0xc418, 0x40d1, 0xc418, 0x21, 0 - .dw 0x40d3, 0xc418, 0x40ff, 0xc418, 0x21, 0 - .dw 0x4101, 0xc418, 0x4101, 0xc418, 0x21, 0 - .dw 0x4103, 0xc418, 0x410f, 0xc418, 0x21, 0 - .dw 0x4111, 0xc418, 0x4111, 0xc418, 0x21, 0 - .dw 0x4113, 0xc418, 0x413f, 0xc418, 0x21, 0 - .dw 0x4141, 0xc418, 0x4141, 0xc418, 0x21, 0 - .dw 0x4143, 0xc418, 0x414f, 0xc418, 0x21, 0 - .dw 0x4151, 0xc418, 0x4151, 0xc418, 0x21, 0 - .dw 0x4153, 0xc418, 0x417f, 0xc418, 0x21, 0 - .dw 0x4181, 0xc418, 0x4181, 0xc418, 0x21, 0 - .dw 0x4183, 0xc418, 0x418f, 0xc418, 0x21, 0 - .dw 0x4191, 0xc418, 0x4191, 0xc418, 0x21, 0 - .dw 0x4193, 0xc418, 0x41bf, 0xc418, 0x21, 0 - .dw 0x41c1, 0xc418, 0x41c1, 0xc418, 0x21, 0 - .dw 0x41c3, 0xc418, 0x41cf, 0xc418, 0x21, 0 - .dw 0x41d1, 0xc418, 0x41d1, 0xc418, 0x21, 0 - .dw 0x41d3, 0xc418, 0x41ff, 0xc418, 0x21, 0 - .dw 0x4201, 0xc418, 0x4201, 0xc418, 0x21, 0 - .dw 0x4203, 0xc418, 0x420f, 0xc418, 0x21, 0 - .dw 0x4211, 0xc418, 0x4211, 0xc418, 0x21, 0 - .dw 0x4213, 0xc418, 0x423f, 0xc418, 0x21, 0 - .dw 0x4240, 0xc418, 0x4240, 0xc418, 0x22, 0 - .dw 0x4241, 0xc418, 0x4241, 0xc418, 0x21, 0 - .dw 0x4242, 0xc418, 0x4242, 0xc418, 0x22, 0 - .dw 0x4243, 0xc418, 0x424f, 0xc418, 0x21, 0 - .dw 0x4250, 0xc418, 0x4250, 0xc418, 0x22, 0 - .dw 0x4251, 0xc418, 0x4251, 0xc418, 0x21, 0 - .dw 0x4252, 0xc418, 0x4252, 0xc418, 0x22, 0 - .dw 0x4253, 0xc418, 0x427f, 0xc418, 0x21, 0 - .dw 0x4281, 0xc418, 0x4281, 0xc418, 0x21, 0 - .dw 0x4283, 0xc418, 0x428f, 0xc418, 0x21, 0 - .dw 0x4291, 0xc418, 0x4291, 0xc418, 0x21, 0 - .dw 0x4293, 0xc418, 0x42bf, 0xc418, 0x21, 0 - .dw 0x42c1, 0xc418, 0x42c1, 0xc418, 0x21, 0 - .dw 0x42c3, 0xc418, 0x42cf, 0xc418, 0x21, 0 - .dw 0x42d1, 0xc418, 0x42d1, 0xc418, 0x21, 0 - .dw 0x42d3, 0xc418, 0x42ff, 0xc418, 0x21, 0 - .dw 0x4301, 0xc418, 0x4301, 0xc418, 0x21, 0 - .dw 0x4303, 0xc418, 0x430f, 0xc418, 0x21, 0 - .dw 0x4311, 0xc418, 0x4311, 0xc418, 0x21, 0 - .dw 0x4313, 0xc418, 0x433f, 0xc418, 0x21, 0 - .dw 0x4341, 0xc418, 0x4341, 0xc418, 0x21, 0 - .dw 0x4343, 0xc418, 0x434f, 0xc418, 0x21, 0 - .dw 0x4351, 0xc418, 0x4351, 0xc418, 0x21, 0 - .dw 0x4353, 0xc418, 0x437f, 0xc418, 0x21, 0 - .dw 0x4381, 0xc418, 0x4381, 0xc418, 0x21, 0 - .dw 0x4383, 0xc418, 0x438f, 0xc418, 0x21, 0 - .dw 0x4391, 0xc418, 0x4391, 0xc418, 0x21, 0 - .dw 0x4393, 0xc418, 0x43bf, 0xc418, 0x21, 0 - .dw 0x43c1, 0xc418, 0x43c1, 0xc418, 0x21, 0 - .dw 0x43c3, 0xc418, 0x43cf, 0xc418, 0x21, 0 - .dw 0x43d1, 0xc418, 0x43d1, 0xc418, 0x21, 0 - .dw 0x43d3, 0xc418, 0x43ff, 0xc418, 0x21, 0 - .dw 0x4401, 0xc418, 0x4401, 0xc418, 0x21, 0 - .dw 0x4403, 0xc418, 0x440f, 0xc418, 0x21, 0 - .dw 0x4411, 0xc418, 0x4411, 0xc418, 0x21, 0 - .dw 0x4413, 0xc418, 0x443f, 0xc418, 0x21, 0 - .dw 0x4441, 0xc418, 0x4441, 0xc418, 0x21, 0 - .dw 0x4443, 0xc418, 0x444f, 0xc418, 0x21, 0 - .dw 0x4451, 0xc418, 0x4451, 0xc418, 0x21, 0 - .dw 0x4453, 0xc418, 0x447f, 0xc418, 0x21, 0 - .dw 0x4480, 0xc418, 0x4480, 0xc418, 0x22, 0 - .dw 0x4481, 0xc418, 0x4481, 0xc418, 0x21, 0 - .dw 0x4482, 0xc418, 0x4482, 0xc418, 0x22, 0 - .dw 0x4483, 0xc418, 0x448f, 0xc418, 0x21, 0 - .dw 0x4490, 0xc418, 0x4490, 0xc418, 0x22, 0 - .dw 0x4491, 0xc418, 0x4491, 0xc418, 0x21, 0 - .dw 0x4492, 0xc418, 0x4492, 0xc418, 0x22, 0 - .dw 0x4493, 0xc418, 0x44bf, 0xc418, 0x21, 0 - .dw 0x44c1, 0xc418, 0x44c1, 0xc418, 0x21, 0 - .dw 0x44c3, 0xc418, 0x44cf, 0xc418, 0x21, 0 - .dw 0x44d1, 0xc418, 0x44d1, 0xc418, 0x21, 0 - .dw 0x44d3, 0xc418, 0x44ff, 0xc418, 0x21, 0 - .dw 0x4501, 0xc418, 0x4501, 0xc418, 0x21, 0 - .dw 0x4503, 0xc418, 0x450f, 0xc418, 0x21, 0 - .dw 0x4511, 0xc418, 0x4511, 0xc418, 0x21, 0 - .dw 0x4513, 0xc418, 0x453f, 0xc418, 0x21, 0 - .dw 0x4541, 0xc418, 0x4541, 0xc418, 0x21, 0 - .dw 0x4543, 0xc418, 0x454f, 0xc418, 0x21, 0 - .dw 0x4551, 0xc418, 0x4551, 0xc418, 0x21, 0 - .dw 0x4553, 0xc418, 0x457f, 0xc418, 0x21, 0 - .dw 0x4581, 0xc418, 0x4581, 0xc418, 0x21, 0 - .dw 0x4583, 0xc418, 0x458f, 0xc418, 0x21, 0 - .dw 0x4591, 0xc418, 0x4591, 0xc418, 0x21, 0 - .dw 0x4593, 0xc418, 0x45bf, 0xc418, 0x21, 0 - .dw 0x45c1, 0xc418, 0x45c1, 0xc418, 0x21, 0 - .dw 0x45c3, 0xc418, 0x45cf, 0xc418, 0x21, 0 - .dw 0x45d1, 0xc418, 0x45d1, 0xc418, 0x21, 0 - .dw 0x45d3, 0xc418, 0x45ff, 0xc418, 0x21, 0 - .dw 0x4601, 0xc418, 0x4601, 0xc418, 0x21, 0 - .dw 0x4603, 0xc418, 0x460f, 0xc418, 0x21, 0 - .dw 0x4611, 0xc418, 0x4611, 0xc418, 0x21, 0 - .dw 0x4613, 0xc418, 0x463f, 0xc418, 0x21, 0 - .dw 0x4641, 0xc418, 0x4641, 0xc418, 0x21, 0 - .dw 0x4643, 0xc418, 0x464f, 0xc418, 0x21, 0 - .dw 0x4651, 0xc418, 0x4651, 0xc418, 0x21, 0 - .dw 0x4653, 0xc418, 0x467f, 0xc418, 0x21, 0 - .dw 0x4681, 0xc418, 0x4681, 0xc418, 0x21, 0 - .dw 0x4683, 0xc418, 0x468f, 0xc418, 0x21, 0 - .dw 0x4691, 0xc418, 0x4691, 0xc418, 0x21, 0 - .dw 0x4693, 0xc418, 0x46bf, 0xc418, 0x21, 0 - .dw 0x46c0, 0xc418, 0x46c0, 0xc418, 0x22, 0 - .dw 0x46c1, 0xc418, 0x46c1, 0xc418, 0x21, 0 - .dw 0x46c2, 0xc418, 0x46c2, 0xc418, 0x22, 0 - .dw 0x46c3, 0xc418, 0x46cf, 0xc418, 0x21, 0 - .dw 0x46d0, 0xc418, 0x46d0, 0xc418, 0x22, 0 - .dw 0x46d1, 0xc418, 0x46d1, 0xc418, 0x21, 0 - .dw 0x46d2, 0xc418, 0x46d2, 0xc418, 0x22, 0 - .dw 0x46d3, 0xc418, 0x46ff, 0xc418, 0x21, 0 - .dw 0x4701, 0xc418, 0x4701, 0xc418, 0x21, 0 - .dw 0x4703, 0xc418, 0x470f, 0xc418, 0x21, 0 - .dw 0x4711, 0xc418, 0x4711, 0xc418, 0x21, 0 - .dw 0x4713, 0xc418, 0x473f, 0xc418, 0x21, 0 - .dw 0x4741, 0xc418, 0x4741, 0xc418, 0x21, 0 - .dw 0x4743, 0xc418, 0x474f, 0xc418, 0x21, 0 - .dw 0x4751, 0xc418, 0x4751, 0xc418, 0x21, 0 - .dw 0x4753, 0xc418, 0x477f, 0xc418, 0x21, 0 - .dw 0x4781, 0xc418, 0x4781, 0xc418, 0x21, 0 - .dw 0x4783, 0xc418, 0x478f, 0xc418, 0x21, 0 - .dw 0x4791, 0xc418, 0x4791, 0xc418, 0x21, 0 - .dw 0x4793, 0xc418, 0x47bf, 0xc418, 0x21, 0 - .dw 0x47c1, 0xc418, 0x47c1, 0xc418, 0x21, 0 - .dw 0x47c3, 0xc418, 0x47cf, 0xc418, 0x21, 0 - .dw 0x47d1, 0xc418, 0x47d1, 0xc418, 0x21, 0 - .dw 0x47d3, 0xc418, 0x47ff, 0xc418, 0x21, 0 - .dw 0x4801, 0xc418, 0x4801, 0xc418, 0x21, 0 - .dw 0x4803, 0xc418, 0x480f, 0xc418, 0x21, 0 - .dw 0x4811, 0xc418, 0x4811, 0xc418, 0x21, 0 - .dw 0x4813, 0xc418, 0x483f, 0xc418, 0x21, 0 - .dw 0x4841, 0xc418, 0x4841, 0xc418, 0x21, 0 - .dw 0x4843, 0xc418, 0x484f, 0xc418, 0x21, 0 - .dw 0x4851, 0xc418, 0x4851, 0xc418, 0x21, 0 - .dw 0x4853, 0xc418, 0x487f, 0xc418, 0x21, 0 - .dw 0x4881, 0xc418, 0x4881, 0xc418, 0x21, 0 - .dw 0x4883, 0xc418, 0x488f, 0xc418, 0x21, 0 - .dw 0x4891, 0xc418, 0x4891, 0xc418, 0x21, 0 - .dw 0x4893, 0xc418, 0x48bf, 0xc418, 0x21, 0 - .dw 0x48c1, 0xc418, 0x48c1, 0xc418, 0x21, 0 - .dw 0x48c3, 0xc418, 0x48cf, 0xc418, 0x21, 0 - .dw 0x48d1, 0xc418, 0x48d1, 0xc418, 0x21, 0 - .dw 0x48d3, 0xc418, 0x48ff, 0xc418, 0x21, 0 - .dw 0x4900, 0xc418, 0x4900, 0xc418, 0x22, 0 - .dw 0x4901, 0xc418, 0x4901, 0xc418, 0x21, 0 - .dw 0x4902, 0xc418, 0x4902, 0xc418, 0x22, 0 - .dw 0x4903, 0xc418, 0x490f, 0xc418, 0x21, 0 - .dw 0x4910, 0xc418, 0x4910, 0xc418, 0x22, 0 - .dw 0x4911, 0xc418, 0x4911, 0xc418, 0x21, 0 - .dw 0x4912, 0xc418, 0x4912, 0xc418, 0x22, 0 - .dw 0x4913, 0xc418, 0x493f, 0xc418, 0x21, 0 - .dw 0x4941, 0xc418, 0x4941, 0xc418, 0x21, 0 - .dw 0x4943, 0xc418, 0x494f, 0xc418, 0x21, 0 - .dw 0x4951, 0xc418, 0x4951, 0xc418, 0x21, 0 - .dw 0x4953, 0xc418, 0x497f, 0xc418, 0x21, 0 - .dw 0x4981, 0xc418, 0x4981, 0xc418, 0x21, 0 - .dw 0x4983, 0xc418, 0x498f, 0xc418, 0x21, 0 - .dw 0x4991, 0xc418, 0x4991, 0xc418, 0x21, 0 - .dw 0x4993, 0xc418, 0x49bf, 0xc418, 0x21, 0 - .dw 0x49c1, 0xc418, 0x49c1, 0xc418, 0x21, 0 - .dw 0x49c3, 0xc418, 0x49cf, 0xc418, 0x21, 0 - .dw 0x49d1, 0xc418, 0x49d1, 0xc418, 0x21, 0 - .dw 0x49d3, 0xc418, 0x49ff, 0xc418, 0x21, 0 - .dw 0x4a01, 0xc418, 0x4a01, 0xc418, 0x21, 0 - .dw 0x4a03, 0xc418, 0x4a0f, 0xc418, 0x21, 0 - .dw 0x4a11, 0xc418, 0x4a11, 0xc418, 0x21, 0 - .dw 0x4a13, 0xc418, 0x4a3f, 0xc418, 0x21, 0 - .dw 0x4a41, 0xc418, 0x4a41, 0xc418, 0x21, 0 - .dw 0x4a43, 0xc418, 0x4a4f, 0xc418, 0x21, 0 - .dw 0x4a51, 0xc418, 0x4a51, 0xc418, 0x21, 0 - .dw 0x4a53, 0xc418, 0x4a7f, 0xc418, 0x21, 0 - .dw 0x4a81, 0xc418, 0x4a81, 0xc418, 0x21, 0 - .dw 0x4a83, 0xc418, 0x4a8f, 0xc418, 0x21, 0 - .dw 0x4a91, 0xc418, 0x4a91, 0xc418, 0x21, 0 - .dw 0x4a93, 0xc418, 0x4abf, 0xc418, 0x21, 0 - .dw 0x4ac1, 0xc418, 0x4ac1, 0xc418, 0x21, 0 - .dw 0x4ac3, 0xc418, 0x4acf, 0xc418, 0x21, 0 - .dw 0x4ad1, 0xc418, 0x4ad1, 0xc418, 0x21, 0 - .dw 0x4ad3, 0xc418, 0x4aff, 0xc418, 0x21, 0 - .dw 0x4b01, 0xc418, 0x4b01, 0xc418, 0x21, 0 - .dw 0x4b03, 0xc418, 0x4b0f, 0xc418, 0x21, 0 - .dw 0x4b11, 0xc418, 0x4b11, 0xc418, 0x21, 0 - .dw 0x4b13, 0xc418, 0x4b3f, 0xc418, 0x21, 0 - .dw 0x4b40, 0xc418, 0x4b40, 0xc418, 0x22, 0 - .dw 0x4b41, 0xc418, 0x4b41, 0xc418, 0x21, 0 - .dw 0x4b42, 0xc418, 0x4b42, 0xc418, 0x22, 0 - .dw 0x4b43, 0xc418, 0x4b4f, 0xc418, 0x21, 0 - .dw 0x4b50, 0xc418, 0x4b50, 0xc418, 0x22, 0 - .dw 0x4b51, 0xc418, 0x4b51, 0xc418, 0x21, 0 - .dw 0x4b52, 0xc418, 0x4b52, 0xc418, 0x22, 0 - .dw 0x4b53, 0xc418, 0x4b7f, 0xc418, 0x21, 0 - .dw 0x4b81, 0xc418, 0x4b81, 0xc418, 0x21, 0 - .dw 0x4b83, 0xc418, 0x4b8f, 0xc418, 0x21, 0 - .dw 0x4b91, 0xc418, 0x4b91, 0xc418, 0x21, 0 - .dw 0x4b93, 0xc418, 0x4bbf, 0xc418, 0x21, 0 - .dw 0x4bc1, 0xc418, 0x4bc1, 0xc418, 0x21, 0 - .dw 0x4bc3, 0xc418, 0x4bcf, 0xc418, 0x21, 0 - .dw 0x4bd1, 0xc418, 0x4bd1, 0xc418, 0x21, 0 - .dw 0x4bd3, 0xc418, 0x4bff, 0xc418, 0x21, 0 - .dw 0x4c01, 0xc418, 0x4c01, 0xc418, 0x21, 0 - .dw 0x4c03, 0xc418, 0x4c0f, 0xc418, 0x21, 0 - .dw 0x4c11, 0xc418, 0x4c11, 0xc418, 0x21, 0 - .dw 0x4c13, 0xc418, 0x4c3f, 0xc418, 0x21, 0 - .dw 0x4c41, 0xc418, 0x4c41, 0xc418, 0x21, 0 - .dw 0x4c43, 0xc418, 0x4c4f, 0xc418, 0x21, 0 - .dw 0x4c51, 0xc418, 0x4c51, 0xc418, 0x21, 0 - .dw 0x4c53, 0xc418, 0x4c7f, 0xc418, 0x21, 0 - .dw 0x4c81, 0xc418, 0x4c81, 0xc418, 0x21, 0 - .dw 0x4c83, 0xc418, 0x4c8f, 0xc418, 0x21, 0 - .dw 0x4c91, 0xc418, 0x4c91, 0xc418, 0x21, 0 - .dw 0x4c93, 0xc418, 0x4cbf, 0xc418, 0x21, 0 - .dw 0x4cc1, 0xc418, 0x4cc1, 0xc418, 0x21, 0 - .dw 0x4cc3, 0xc418, 0x4ccf, 0xc418, 0x21, 0 - .dw 0x4cd1, 0xc418, 0x4cd1, 0xc418, 0x21, 0 - .dw 0x4cd3, 0xc418, 0x4cff, 0xc418, 0x21, 0 - .dw 0x4d01, 0xc418, 0x4d01, 0xc418, 0x21, 0 - .dw 0x4d03, 0xc418, 0x4d0f, 0xc418, 0x21, 0 - .dw 0x4d11, 0xc418, 0x4d11, 0xc418, 0x21, 0 - .dw 0x4d13, 0xc418, 0x4d3f, 0xc418, 0x21, 0 - .dw 0x4d41, 0xc418, 0x4d41, 0xc418, 0x21, 0 - .dw 0x4d43, 0xc418, 0x4d4f, 0xc418, 0x21, 0 - .dw 0x4d51, 0xc418, 0x4d51, 0xc418, 0x21, 0 - .dw 0x4d53, 0xc418, 0x4d7f, 0xc418, 0x21, 0 - .dw 0x4d80, 0xc418, 0x4d80, 0xc418, 0x22, 0 - .dw 0x4d81, 0xc418, 0x4d81, 0xc418, 0x21, 0 - .dw 0x4d82, 0xc418, 0x4d82, 0xc418, 0x22, 0 - .dw 0x4d83, 0xc418, 0x4d8f, 0xc418, 0x21, 0 - .dw 0x4d90, 0xc418, 0x4d90, 0xc418, 0x22, 0 - .dw 0x4d91, 0xc418, 0x4d91, 0xc418, 0x21, 0 - .dw 0x4d92, 0xc418, 0x4d92, 0xc418, 0x22, 0 - .dw 0x4d93, 0xc418, 0x4dbf, 0xc418, 0x21, 0 - .dw 0x4dc1, 0xc418, 0x4dc1, 0xc418, 0x21, 0 - .dw 0x4dc3, 0xc418, 0x4dcf, 0xc418, 0x21, 0 - .dw 0x4dd1, 0xc418, 0x4dd1, 0xc418, 0x21, 0 - .dw 0x4dd3, 0xc418, 0x4dff, 0xc418, 0x21, 0 - .dw 0x4e01, 0xc418, 0x4e01, 0xc418, 0x21, 0 - .dw 0x4e03, 0xc418, 0x4e0f, 0xc418, 0x21, 0 - .dw 0x4e11, 0xc418, 0x4e11, 0xc418, 0x21, 0 - .dw 0x4e13, 0xc418, 0x4e3f, 0xc418, 0x21, 0 - .dw 0x4e41, 0xc418, 0x4e41, 0xc418, 0x21, 0 - .dw 0x4e43, 0xc418, 0x4e4f, 0xc418, 0x21, 0 - .dw 0x4e51, 0xc418, 0x4e51, 0xc418, 0x21, 0 - .dw 0x4e53, 0xc418, 0x4e7f, 0xc418, 0x21, 0 - .dw 0x4e81, 0xc418, 0x4e81, 0xc418, 0x21, 0 - .dw 0x4e83, 0xc418, 0x4e8f, 0xc418, 0x21, 0 - .dw 0x4e91, 0xc418, 0x4e91, 0xc418, 0x21, 0 - .dw 0x4e93, 0xc418, 0x4ebf, 0xc418, 0x21, 0 - .dw 0x4ec1, 0xc418, 0x4ec1, 0xc418, 0x21, 0 - .dw 0x4ec3, 0xc418, 0x4ecf, 0xc418, 0x21, 0 - .dw 0x4ed1, 0xc418, 0x4ed1, 0xc418, 0x21, 0 - .dw 0x4ed3, 0xc418, 0x4eff, 0xc418, 0x21, 0 - .dw 0x4f01, 0xc418, 0x4f01, 0xc418, 0x21, 0 - .dw 0x4f03, 0xc418, 0x4f0f, 0xc418, 0x21, 0 - .dw 0x4f11, 0xc418, 0x4f11, 0xc418, 0x21, 0 - .dw 0x4f13, 0xc418, 0x4f3f, 0xc418, 0x21, 0 - .dw 0x4f41, 0xc418, 0x4f41, 0xc418, 0x21, 0 - .dw 0x4f43, 0xc418, 0x4f4f, 0xc418, 0x21, 0 - .dw 0x4f51, 0xc418, 0x4f51, 0xc418, 0x21, 0 - .dw 0x4f53, 0xc418, 0x4f7f, 0xc418, 0x21, 0 - .dw 0x4f81, 0xc418, 0x4f81, 0xc418, 0x21, 0 - .dw 0x4f83, 0xc418, 0x4f8f, 0xc418, 0x21, 0 - .dw 0x4f91, 0xc418, 0x4f91, 0xc418, 0x21, 0 - .dw 0x4f93, 0xc418, 0x4fbf, 0xc418, 0x21, 0 - .dw 0x4fc0, 0xc418, 0x4fc0, 0xc418, 0x22, 0 - .dw 0x4fc1, 0xc418, 0x4fc1, 0xc418, 0x21, 0 - .dw 0x4fc2, 0xc418, 0x4fc2, 0xc418, 0x22, 0 - .dw 0x4fc3, 0xc418, 0x4fcf, 0xc418, 0x21, 0 - .dw 0x4fd0, 0xc418, 0x4fd0, 0xc418, 0x22, 0 - .dw 0x4fd1, 0xc418, 0x4fd1, 0xc418, 0x21, 0 - .dw 0x4fd2, 0xc418, 0x4fd2, 0xc418, 0x22, 0 - .dw 0x4fd3, 0xc418, 0x5fff, 0xc418, 0x21, 0 - .dw 0x6000, 0xc418, 0x6000, 0xc418, 0x22, 0 - .dw 0x6001, 0xc418, 0x6001, 0xc418, 0x21, 0 - .dw 0x6002, 0xc418, 0x6002, 0xc418, 0x22, 0 - .dw 0x6003, 0xc418, 0x600f, 0xc418, 0x21, 0 - .dw 0x6010, 0xc418, 0x6010, 0xc418, 0x22, 0 - .dw 0x6011, 0xc418, 0x6011, 0xc418, 0x21, 0 - .dw 0x6012, 0xc418, 0x6012, 0xc418, 0x22, 0 - .dw 0x6013, 0xc418, 0x603f, 0xc418, 0x21, 0 - .dw 0x6041, 0xc418, 0x6041, 0xc418, 0x21, 0 - .dw 0x6043, 0xc418, 0x604f, 0xc418, 0x21, 0 - .dw 0x6051, 0xc418, 0x6051, 0xc418, 0x21, 0 - .dw 0x6053, 0xc418, 0x607f, 0xc418, 0x21, 0 - .dw 0x6081, 0xc418, 0x6081, 0xc418, 0x21, 0 - .dw 0x6083, 0xc418, 0x608f, 0xc418, 0x21, 0 - .dw 0x6091, 0xc418, 0x6091, 0xc418, 0x21, 0 - .dw 0x6093, 0xc418, 0x60bf, 0xc418, 0x21, 0 - .dw 0x60c1, 0xc418, 0x60c1, 0xc418, 0x21, 0 - .dw 0x60c3, 0xc418, 0x60cf, 0xc418, 0x21, 0 - .dw 0x60d1, 0xc418, 0x60d1, 0xc418, 0x21, 0 - .dw 0x60d3, 0xc418, 0x60ff, 0xc418, 0x21, 0 - .dw 0x6101, 0xc418, 0x6101, 0xc418, 0x21, 0 - .dw 0x6103, 0xc418, 0x610f, 0xc418, 0x21, 0 - .dw 0x6111, 0xc418, 0x6111, 0xc418, 0x21, 0 - .dw 0x6113, 0xc418, 0x613f, 0xc418, 0x21, 0 - .dw 0x6141, 0xc418, 0x6141, 0xc418, 0x21, 0 - .dw 0x6143, 0xc418, 0x614f, 0xc418, 0x21, 0 - .dw 0x6151, 0xc418, 0x6151, 0xc418, 0x21, 0 - .dw 0x6153, 0xc418, 0x617f, 0xc418, 0x21, 0 - .dw 0x6181, 0xc418, 0x6181, 0xc418, 0x21, 0 - .dw 0x6183, 0xc418, 0x618f, 0xc418, 0x21, 0 - .dw 0x6191, 0xc418, 0x6191, 0xc418, 0x21, 0 - .dw 0x6193, 0xc418, 0x61bf, 0xc418, 0x21, 0 - .dw 0x61c1, 0xc418, 0x61c1, 0xc418, 0x21, 0 - .dw 0x61c3, 0xc418, 0x61cf, 0xc418, 0x21, 0 - .dw 0x61d1, 0xc418, 0x61d1, 0xc418, 0x21, 0 - .dw 0x61d3, 0xc418, 0x61ff, 0xc418, 0x21, 0 - .dw 0x6201, 0xc418, 0x6201, 0xc418, 0x21, 0 - .dw 0x6203, 0xc418, 0x620f, 0xc418, 0x21, 0 - .dw 0x6211, 0xc418, 0x6211, 0xc418, 0x21, 0 - .dw 0x6213, 0xc418, 0x623f, 0xc418, 0x21, 0 - .dw 0x6240, 0xc418, 0x6240, 0xc418, 0x22, 0 - .dw 0x6241, 0xc418, 0x6241, 0xc418, 0x21, 0 - .dw 0x6242, 0xc418, 0x6242, 0xc418, 0x22, 0 - .dw 0x6243, 0xc418, 0x624f, 0xc418, 0x21, 0 - .dw 0x6250, 0xc418, 0x6250, 0xc418, 0x22, 0 - .dw 0x6251, 0xc418, 0x6251, 0xc418, 0x21, 0 - .dw 0x6252, 0xc418, 0x6252, 0xc418, 0x22, 0 - .dw 0x6253, 0xc418, 0x627f, 0xc418, 0x21, 0 - .dw 0x6281, 0xc418, 0x6281, 0xc418, 0x21, 0 - .dw 0x6283, 0xc418, 0x628f, 0xc418, 0x21, 0 - .dw 0x6291, 0xc418, 0x6291, 0xc418, 0x21, 0 - .dw 0x6293, 0xc418, 0x62bf, 0xc418, 0x21, 0 - .dw 0x62c1, 0xc418, 0x62c1, 0xc418, 0x21, 0 - .dw 0x62c3, 0xc418, 0x62cf, 0xc418, 0x21, 0 - .dw 0x62d1, 0xc418, 0x62d1, 0xc418, 0x21, 0 - .dw 0x62d3, 0xc418, 0x62ff, 0xc418, 0x21, 0 - .dw 0x6301, 0xc418, 0x6301, 0xc418, 0x21, 0 - .dw 0x6303, 0xc418, 0x630f, 0xc418, 0x21, 0 - .dw 0x6311, 0xc418, 0x6311, 0xc418, 0x21, 0 - .dw 0x6313, 0xc418, 0x633f, 0xc418, 0x21, 0 - .dw 0x6341, 0xc418, 0x6341, 0xc418, 0x21, 0 - .dw 0x6343, 0xc418, 0x634f, 0xc418, 0x21, 0 - .dw 0x6351, 0xc418, 0x6351, 0xc418, 0x21, 0 - .dw 0x6353, 0xc418, 0x637f, 0xc418, 0x21, 0 - .dw 0x6381, 0xc418, 0x6381, 0xc418, 0x21, 0 - .dw 0x6383, 0xc418, 0x638f, 0xc418, 0x21, 0 - .dw 0x6391, 0xc418, 0x6391, 0xc418, 0x21, 0 - .dw 0x6393, 0xc418, 0x63bf, 0xc418, 0x21, 0 - .dw 0x63c1, 0xc418, 0x63c1, 0xc418, 0x21, 0 - .dw 0x63c3, 0xc418, 0x63cf, 0xc418, 0x21, 0 - .dw 0x63d1, 0xc418, 0x63d1, 0xc418, 0x21, 0 - .dw 0x63d3, 0xc418, 0x63ff, 0xc418, 0x21, 0 - .dw 0x6401, 0xc418, 0x6401, 0xc418, 0x21, 0 - .dw 0x6403, 0xc418, 0x640f, 0xc418, 0x21, 0 - .dw 0x6411, 0xc418, 0x6411, 0xc418, 0x21, 0 - .dw 0x6413, 0xc418, 0x643f, 0xc418, 0x21, 0 - .dw 0x6441, 0xc418, 0x6441, 0xc418, 0x21, 0 - .dw 0x6443, 0xc418, 0x644f, 0xc418, 0x21, 0 - .dw 0x6451, 0xc418, 0x6451, 0xc418, 0x21, 0 - .dw 0x6453, 0xc418, 0x647f, 0xc418, 0x21, 0 - .dw 0x6480, 0xc418, 0x6480, 0xc418, 0x22, 0 - .dw 0x6481, 0xc418, 0x6481, 0xc418, 0x21, 0 - .dw 0x6482, 0xc418, 0x6482, 0xc418, 0x22, 0 - .dw 0x6483, 0xc418, 0x648f, 0xc418, 0x21, 0 - .dw 0x6490, 0xc418, 0x6490, 0xc418, 0x22, 0 - .dw 0x6491, 0xc418, 0x6491, 0xc418, 0x21, 0 - .dw 0x6492, 0xc418, 0x6492, 0xc418, 0x22, 0 - .dw 0x6493, 0xc418, 0x64bf, 0xc418, 0x21, 0 - .dw 0x64c1, 0xc418, 0x64c1, 0xc418, 0x21, 0 - .dw 0x64c3, 0xc418, 0x64cf, 0xc418, 0x21, 0 - .dw 0x64d1, 0xc418, 0x64d1, 0xc418, 0x21, 0 - .dw 0x64d3, 0xc418, 0x64ff, 0xc418, 0x21, 0 - .dw 0x6501, 0xc418, 0x6501, 0xc418, 0x21, 0 - .dw 0x6503, 0xc418, 0x650f, 0xc418, 0x21, 0 - .dw 0x6511, 0xc418, 0x6511, 0xc418, 0x21, 0 - .dw 0x6513, 0xc418, 0x653f, 0xc418, 0x21, 0 - .dw 0x6541, 0xc418, 0x6541, 0xc418, 0x21, 0 - .dw 0x6543, 0xc418, 0x654f, 0xc418, 0x21, 0 - .dw 0x6551, 0xc418, 0x6551, 0xc418, 0x21, 0 - .dw 0x6553, 0xc418, 0x657f, 0xc418, 0x21, 0 - .dw 0x6581, 0xc418, 0x6581, 0xc418, 0x21, 0 - .dw 0x6583, 0xc418, 0x658f, 0xc418, 0x21, 0 - .dw 0x6591, 0xc418, 0x6591, 0xc418, 0x21, 0 - .dw 0x6593, 0xc418, 0x65bf, 0xc418, 0x21, 0 - .dw 0x65c1, 0xc418, 0x65c1, 0xc418, 0x21, 0 - .dw 0x65c3, 0xc418, 0x65cf, 0xc418, 0x21, 0 - .dw 0x65d1, 0xc418, 0x65d1, 0xc418, 0x21, 0 - .dw 0x65d3, 0xc418, 0x65ff, 0xc418, 0x21, 0 - .dw 0x6601, 0xc418, 0x6601, 0xc418, 0x21, 0 - .dw 0x6603, 0xc418, 0x660f, 0xc418, 0x21, 0 - .dw 0x6611, 0xc418, 0x6611, 0xc418, 0x21, 0 - .dw 0x6613, 0xc418, 0x663f, 0xc418, 0x21, 0 - .dw 0x6641, 0xc418, 0x6641, 0xc418, 0x21, 0 - .dw 0x6643, 0xc418, 0x664f, 0xc418, 0x21, 0 - .dw 0x6651, 0xc418, 0x6651, 0xc418, 0x21, 0 - .dw 0x6653, 0xc418, 0x667f, 0xc418, 0x21, 0 - .dw 0x6681, 0xc418, 0x6681, 0xc418, 0x21, 0 - .dw 0x6683, 0xc418, 0x668f, 0xc418, 0x21, 0 - .dw 0x6691, 0xc418, 0x6691, 0xc418, 0x21, 0 - .dw 0x6693, 0xc418, 0x66bf, 0xc418, 0x21, 0 - .dw 0x66c0, 0xc418, 0x66c0, 0xc418, 0x22, 0 - .dw 0x66c1, 0xc418, 0x66c1, 0xc418, 0x21, 0 - .dw 0x66c2, 0xc418, 0x66c2, 0xc418, 0x22, 0 - .dw 0x66c3, 0xc418, 0x66cf, 0xc418, 0x21, 0 - .dw 0x66d0, 0xc418, 0x66d0, 0xc418, 0x22, 0 - .dw 0x66d1, 0xc418, 0x66d1, 0xc418, 0x21, 0 - .dw 0x66d2, 0xc418, 0x66d2, 0xc418, 0x22, 0 - .dw 0x66d3, 0xc418, 0x66ff, 0xc418, 0x21, 0 - .dw 0x6701, 0xc418, 0x6701, 0xc418, 0x21, 0 - .dw 0x6703, 0xc418, 0x670f, 0xc418, 0x21, 0 - .dw 0x6711, 0xc418, 0x6711, 0xc418, 0x21, 0 - .dw 0x6713, 0xc418, 0x673f, 0xc418, 0x21, 0 - .dw 0x6741, 0xc418, 0x6741, 0xc418, 0x21, 0 - .dw 0x6743, 0xc418, 0x674f, 0xc418, 0x21, 0 - .dw 0x6751, 0xc418, 0x6751, 0xc418, 0x21, 0 - .dw 0x6753, 0xc418, 0x677f, 0xc418, 0x21, 0 - .dw 0x6781, 0xc418, 0x6781, 0xc418, 0x21, 0 - .dw 0x6783, 0xc418, 0x678f, 0xc418, 0x21, 0 - .dw 0x6791, 0xc418, 0x6791, 0xc418, 0x21, 0 - .dw 0x6793, 0xc418, 0x67bf, 0xc418, 0x21, 0 - .dw 0x67c1, 0xc418, 0x67c1, 0xc418, 0x21, 0 - .dw 0x67c3, 0xc418, 0x67cf, 0xc418, 0x21, 0 - .dw 0x67d1, 0xc418, 0x67d1, 0xc418, 0x21, 0 - .dw 0x67d3, 0xc418, 0x67ff, 0xc418, 0x21, 0 - .dw 0x6801, 0xc418, 0x6801, 0xc418, 0x21, 0 - .dw 0x6803, 0xc418, 0x680f, 0xc418, 0x21, 0 - .dw 0x6811, 0xc418, 0x6811, 0xc418, 0x21, 0 - .dw 0x6813, 0xc418, 0x683f, 0xc418, 0x21, 0 - .dw 0x6841, 0xc418, 0x6841, 0xc418, 0x21, 0 - .dw 0x6843, 0xc418, 0x684f, 0xc418, 0x21, 0 - .dw 0x6851, 0xc418, 0x6851, 0xc418, 0x21, 0 - .dw 0x6853, 0xc418, 0x687f, 0xc418, 0x21, 0 - .dw 0x6881, 0xc418, 0x6881, 0xc418, 0x21, 0 - .dw 0x6883, 0xc418, 0x688f, 0xc418, 0x21, 0 - .dw 0x6891, 0xc418, 0x6891, 0xc418, 0x21, 0 - .dw 0x6893, 0xc418, 0x68bf, 0xc418, 0x21, 0 - .dw 0x68c1, 0xc418, 0x68c1, 0xc418, 0x21, 0 - .dw 0x68c3, 0xc418, 0x68cf, 0xc418, 0x21, 0 - .dw 0x68d1, 0xc418, 0x68d1, 0xc418, 0x21, 0 - .dw 0x68d3, 0xc418, 0x68ff, 0xc418, 0x21, 0 - .dw 0x6900, 0xc418, 0x6900, 0xc418, 0x22, 0 - .dw 0x6901, 0xc418, 0x6901, 0xc418, 0x21, 0 - .dw 0x6902, 0xc418, 0x6902, 0xc418, 0x22, 0 - .dw 0x6903, 0xc418, 0x690f, 0xc418, 0x21, 0 - .dw 0x6910, 0xc418, 0x6910, 0xc418, 0x22, 0 - .dw 0x6911, 0xc418, 0x6911, 0xc418, 0x21, 0 - .dw 0x6912, 0xc418, 0x6912, 0xc418, 0x22, 0 - .dw 0x6913, 0xc418, 0x693f, 0xc418, 0x21, 0 - .dw 0x6941, 0xc418, 0x6941, 0xc418, 0x21, 0 - .dw 0x6943, 0xc418, 0x694f, 0xc418, 0x21, 0 - .dw 0x6951, 0xc418, 0x6951, 0xc418, 0x21, 0 - .dw 0x6953, 0xc418, 0x697f, 0xc418, 0x21, 0 - .dw 0x6981, 0xc418, 0x6981, 0xc418, 0x21, 0 - .dw 0x6983, 0xc418, 0x698f, 0xc418, 0x21, 0 - .dw 0x6991, 0xc418, 0x6991, 0xc418, 0x21, 0 - .dw 0x6993, 0xc418, 0x69bf, 0xc418, 0x21, 0 - .dw 0x69c1, 0xc418, 0x69c1, 0xc418, 0x21, 0 - .dw 0x69c3, 0xc418, 0x69cf, 0xc418, 0x21, 0 - .dw 0x69d1, 0xc418, 0x69d1, 0xc418, 0x21, 0 - .dw 0x69d3, 0xc418, 0x69ff, 0xc418, 0x21, 0 - .dw 0x6a01, 0xc418, 0x6a01, 0xc418, 0x21, 0 - .dw 0x6a03, 0xc418, 0x6a0f, 0xc418, 0x21, 0 - .dw 0x6a11, 0xc418, 0x6a11, 0xc418, 0x21, 0 - .dw 0x6a13, 0xc418, 0x6a3f, 0xc418, 0x21, 0 - .dw 0x6a41, 0xc418, 0x6a41, 0xc418, 0x21, 0 - .dw 0x6a43, 0xc418, 0x6a4f, 0xc418, 0x21, 0 - .dw 0x6a51, 0xc418, 0x6a51, 0xc418, 0x21, 0 - .dw 0x6a53, 0xc418, 0x6a7f, 0xc418, 0x21, 0 - .dw 0x6a81, 0xc418, 0x6a81, 0xc418, 0x21, 0 - .dw 0x6a83, 0xc418, 0x6a8f, 0xc418, 0x21, 0 - .dw 0x6a91, 0xc418, 0x6a91, 0xc418, 0x21, 0 - .dw 0x6a93, 0xc418, 0x6abf, 0xc418, 0x21, 0 - .dw 0x6ac1, 0xc418, 0x6ac1, 0xc418, 0x21, 0 - .dw 0x6ac3, 0xc418, 0x6acf, 0xc418, 0x21, 0 - .dw 0x6ad1, 0xc418, 0x6ad1, 0xc418, 0x21, 0 - .dw 0x6ad3, 0xc418, 0x6aff, 0xc418, 0x21, 0 - .dw 0x6b01, 0xc418, 0x6b01, 0xc418, 0x21, 0 - .dw 0x6b03, 0xc418, 0x6b0f, 0xc418, 0x21, 0 - .dw 0x6b11, 0xc418, 0x6b11, 0xc418, 0x21, 0 - .dw 0x6b13, 0xc418, 0x6b3f, 0xc418, 0x21, 0 - .dw 0x6b40, 0xc418, 0x6b40, 0xc418, 0x22, 0 - .dw 0x6b41, 0xc418, 0x6b41, 0xc418, 0x21, 0 - .dw 0x6b42, 0xc418, 0x6b42, 0xc418, 0x22, 0 - .dw 0x6b43, 0xc418, 0x6b4f, 0xc418, 0x21, 0 - .dw 0x6b50, 0xc418, 0x6b50, 0xc418, 0x22, 0 - .dw 0x6b51, 0xc418, 0x6b51, 0xc418, 0x21, 0 - .dw 0x6b52, 0xc418, 0x6b52, 0xc418, 0x22, 0 - .dw 0x6b53, 0xc418, 0x6b7f, 0xc418, 0x21, 0 - .dw 0x6b81, 0xc418, 0x6b81, 0xc418, 0x21, 0 - .dw 0x6b83, 0xc418, 0x6b8f, 0xc418, 0x21, 0 - .dw 0x6b91, 0xc418, 0x6b91, 0xc418, 0x21, 0 - .dw 0x6b93, 0xc418, 0x6bbf, 0xc418, 0x21, 0 - .dw 0x6bc1, 0xc418, 0x6bc1, 0xc418, 0x21, 0 - .dw 0x6bc3, 0xc418, 0x6bcf, 0xc418, 0x21, 0 - .dw 0x6bd1, 0xc418, 0x6bd1, 0xc418, 0x21, 0 - .dw 0x6bd3, 0xc418, 0x6bff, 0xc418, 0x21, 0 - .dw 0x6c01, 0xc418, 0x6c01, 0xc418, 0x21, 0 - .dw 0x6c03, 0xc418, 0x6c0f, 0xc418, 0x21, 0 - .dw 0x6c11, 0xc418, 0x6c11, 0xc418, 0x21, 0 - .dw 0x6c13, 0xc418, 0x6c3f, 0xc418, 0x21, 0 - .dw 0x6c41, 0xc418, 0x6c41, 0xc418, 0x21, 0 - .dw 0x6c43, 0xc418, 0x6c4f, 0xc418, 0x21, 0 - .dw 0x6c51, 0xc418, 0x6c51, 0xc418, 0x21, 0 - .dw 0x6c53, 0xc418, 0x6c7f, 0xc418, 0x21, 0 - .dw 0x6c81, 0xc418, 0x6c81, 0xc418, 0x21, 0 - .dw 0x6c83, 0xc418, 0x6c8f, 0xc418, 0x21, 0 - .dw 0x6c91, 0xc418, 0x6c91, 0xc418, 0x21, 0 - .dw 0x6c93, 0xc418, 0x6cbf, 0xc418, 0x21, 0 - .dw 0x6cc1, 0xc418, 0x6cc1, 0xc418, 0x21, 0 - .dw 0x6cc3, 0xc418, 0x6ccf, 0xc418, 0x21, 0 - .dw 0x6cd1, 0xc418, 0x6cd1, 0xc418, 0x21, 0 - .dw 0x6cd3, 0xc418, 0x6cff, 0xc418, 0x21, 0 - .dw 0x6d01, 0xc418, 0x6d01, 0xc418, 0x21, 0 - .dw 0x6d03, 0xc418, 0x6d0f, 0xc418, 0x21, 0 - .dw 0x6d11, 0xc418, 0x6d11, 0xc418, 0x21, 0 - .dw 0x6d13, 0xc418, 0x6d3f, 0xc418, 0x21, 0 - .dw 0x6d41, 0xc418, 0x6d41, 0xc418, 0x21, 0 - .dw 0x6d43, 0xc418, 0x6d4f, 0xc418, 0x21, 0 - .dw 0x6d51, 0xc418, 0x6d51, 0xc418, 0x21, 0 - .dw 0x6d53, 0xc418, 0x6d7f, 0xc418, 0x21, 0 - .dw 0x6d80, 0xc418, 0x6d80, 0xc418, 0x22, 0 - .dw 0x6d81, 0xc418, 0x6d81, 0xc418, 0x21, 0 - .dw 0x6d82, 0xc418, 0x6d82, 0xc418, 0x22, 0 - .dw 0x6d83, 0xc418, 0x6d8f, 0xc418, 0x21, 0 - .dw 0x6d90, 0xc418, 0x6d90, 0xc418, 0x22, 0 - .dw 0x6d91, 0xc418, 0x6d91, 0xc418, 0x21, 0 - .dw 0x6d92, 0xc418, 0x6d92, 0xc418, 0x22, 0 - .dw 0x6d93, 0xc418, 0x6dbf, 0xc418, 0x21, 0 - .dw 0x6dc1, 0xc418, 0x6dc1, 0xc418, 0x21, 0 - .dw 0x6dc3, 0xc418, 0x6dcf, 0xc418, 0x21, 0 - .dw 0x6dd1, 0xc418, 0x6dd1, 0xc418, 0x21, 0 - .dw 0x6dd3, 0xc418, 0x6dff, 0xc418, 0x21, 0 - .dw 0x6e01, 0xc418, 0x6e01, 0xc418, 0x21, 0 - .dw 0x6e03, 0xc418, 0x6e0f, 0xc418, 0x21, 0 - .dw 0x6e11, 0xc418, 0x6e11, 0xc418, 0x21, 0 - .dw 0x6e13, 0xc418, 0x6e3f, 0xc418, 0x21, 0 - .dw 0x6e41, 0xc418, 0x6e41, 0xc418, 0x21, 0 - .dw 0x6e43, 0xc418, 0x6e4f, 0xc418, 0x21, 0 - .dw 0x6e51, 0xc418, 0x6e51, 0xc418, 0x21, 0 - .dw 0x6e53, 0xc418, 0x6e7f, 0xc418, 0x21, 0 - .dw 0x6e81, 0xc418, 0x6e81, 0xc418, 0x21, 0 - .dw 0x6e83, 0xc418, 0x6e8f, 0xc418, 0x21, 0 - .dw 0x6e91, 0xc418, 0x6e91, 0xc418, 0x21, 0 - .dw 0x6e93, 0xc418, 0x6ebf, 0xc418, 0x21, 0 - .dw 0x6ec1, 0xc418, 0x6ec1, 0xc418, 0x21, 0 - .dw 0x6ec3, 0xc418, 0x6ecf, 0xc418, 0x21, 0 - .dw 0x6ed1, 0xc418, 0x6ed1, 0xc418, 0x21, 0 - .dw 0x6ed3, 0xc418, 0x6eff, 0xc418, 0x21, 0 - .dw 0x6f01, 0xc418, 0x6f01, 0xc418, 0x21, 0 - .dw 0x6f03, 0xc418, 0x6f0f, 0xc418, 0x21, 0 - .dw 0x6f11, 0xc418, 0x6f11, 0xc418, 0x21, 0 - .dw 0x6f13, 0xc418, 0x6f3f, 0xc418, 0x21, 0 - .dw 0x6f41, 0xc418, 0x6f41, 0xc418, 0x21, 0 - .dw 0x6f43, 0xc418, 0x6f4f, 0xc418, 0x21, 0 - .dw 0x6f51, 0xc418, 0x6f51, 0xc418, 0x21, 0 - .dw 0x6f53, 0xc418, 0x6f7f, 0xc418, 0x21, 0 - .dw 0x6f81, 0xc418, 0x6f81, 0xc418, 0x21, 0 - .dw 0x6f83, 0xc418, 0x6f8f, 0xc418, 0x21, 0 - .dw 0x6f91, 0xc418, 0x6f91, 0xc418, 0x21, 0 - .dw 0x6f93, 0xc418, 0x6fbf, 0xc418, 0x21, 0 - .dw 0x6fc0, 0xc418, 0x6fc0, 0xc418, 0x22, 0 - .dw 0x6fc1, 0xc418, 0x6fc1, 0xc418, 0x21, 0 - .dw 0x6fc2, 0xc418, 0x6fc2, 0xc418, 0x22, 0 - .dw 0x6fc3, 0xc418, 0x6fcf, 0xc418, 0x21, 0 - .dw 0x6fd0, 0xc418, 0x6fd0, 0xc418, 0x22, 0 - .dw 0x6fd1, 0xc418, 0x6fd1, 0xc418, 0x21, 0 - .dw 0x6fd2, 0xc418, 0x6fd2, 0xc418, 0x22, 0 - .dw 0x6fd3, 0xc418, 0xffff, 0xc420, 0x21, 0 - .dw 0x0000, 0xc421, 0x003f, 0xc421, 0x22, 0 - .dw 0x0240, 0xc421, 0x027f, 0xc421, 0x22, 0 - .dw 0x0480, 0xc421, 0x04bf, 0xc421, 0x22, 0 - .dw 0x06c0, 0xc421, 0x06ff, 0xc421, 0x22, 0 - .dw 0x0900, 0xc421, 0x093f, 0xc421, 0x22, 0 - .dw 0x0b40, 0xc421, 0x0b7f, 0xc421, 0x22, 0 - .dw 0x0d80, 0xc421, 0x0dbf, 0xc421, 0x22, 0 - .dw 0x0fc0, 0xc421, 0x103f, 0xc421, 0x22, 0 - .dw 0x1240, 0xc421, 0x127f, 0xc421, 0x22, 0 - .dw 0x1480, 0xc421, 0x14bf, 0xc421, 0x22, 0 - .dw 0x16c0, 0xc421, 0x16ff, 0xc421, 0x22, 0 - .dw 0x1900, 0xc421, 0x193f, 0xc421, 0x22, 0 - .dw 0x1b40, 0xc421, 0x1b7f, 0xc421, 0x22, 0 - .dw 0x1d80, 0xc421, 0x1dbf, 0xc421, 0x22, 0 - .dw 0x1fc0, 0xc421, 0x203f, 0xc421, 0x22, 0 - .dw 0x2240, 0xc421, 0x227f, 0xc421, 0x22, 0 - .dw 0x2480, 0xc421, 0x24bf, 0xc421, 0x22, 0 - .dw 0x26c0, 0xc421, 0x26ff, 0xc421, 0x22, 0 - .dw 0x2900, 0xc421, 0x293f, 0xc421, 0x22, 0 - .dw 0x2b40, 0xc421, 0x2b7f, 0xc421, 0x22, 0 - .dw 0x2d80, 0xc421, 0x2dbf, 0xc421, 0x22, 0 - .dw 0x2fc0, 0xc421, 0x303f, 0xc421, 0x22, 0 - .dw 0x3240, 0xc421, 0x327f, 0xc421, 0x22, 0 - .dw 0x3480, 0xc421, 0x34bf, 0xc421, 0x22, 0 - .dw 0x36c0, 0xc421, 0x36ff, 0xc421, 0x22, 0 - .dw 0x3900, 0xc421, 0x393f, 0xc421, 0x22, 0 - .dw 0x3b40, 0xc421, 0x3b7f, 0xc421, 0x22, 0 - .dw 0x3d80, 0xc421, 0x3dbf, 0xc421, 0x22, 0 - .dw 0x3fc0, 0xc421, 0x3fff, 0xc421, 0x22, 0 - .dw 0x4000, 0xc421, 0x7fff, 0xc421, 0x21, 0 - .dw 0x8000, 0xc421, 0x803f, 0xc421, 0x22, 0 - .dw 0x8240, 0xc421, 0x827f, 0xc421, 0x22, 0 - .dw 0x8480, 0xc421, 0x84bf, 0xc421, 0x22, 0 - .dw 0x86c0, 0xc421, 0x86ff, 0xc421, 0x22, 0 - .dw 0x8900, 0xc421, 0x893f, 0xc421, 0x22, 0 - .dw 0x8b40, 0xc421, 0x8b7f, 0xc421, 0x22, 0 - .dw 0x8d80, 0xc421, 0x8dbf, 0xc421, 0x22, 0 - .dw 0x8fc0, 0xc421, 0x903f, 0xc421, 0x22, 0 - .dw 0x9240, 0xc421, 0x927f, 0xc421, 0x22, 0 - .dw 0x9480, 0xc421, 0x94bf, 0xc421, 0x22, 0 - .dw 0x96c0, 0xc421, 0x96ff, 0xc421, 0x22, 0 - .dw 0x9900, 0xc421, 0x993f, 0xc421, 0x22, 0 - .dw 0x9b40, 0xc421, 0x9b7f, 0xc421, 0x22, 0 - .dw 0x9d80, 0xc421, 0x9dbf, 0xc421, 0x22, 0 - .dw 0x9fc0, 0xc421, 0xa03f, 0xc421, 0x22, 0 - .dw 0xa240, 0xc421, 0xa27f, 0xc421, 0x22, 0 - .dw 0xa480, 0xc421, 0xa4bf, 0xc421, 0x22, 0 - .dw 0xa6c0, 0xc421, 0xa6ff, 0xc421, 0x22, 0 - .dw 0xa900, 0xc421, 0xa93f, 0xc421, 0x22, 0 - .dw 0xab40, 0xc421, 0xab7f, 0xc421, 0x22, 0 - .dw 0xad80, 0xc421, 0xadbf, 0xc421, 0x22, 0 - .dw 0xafc0, 0xc421, 0xb03f, 0xc421, 0x22, 0 - .dw 0xb240, 0xc421, 0xb27f, 0xc421, 0x22, 0 - .dw 0xb480, 0xc421, 0xb4bf, 0xc421, 0x22, 0 - .dw 0xb6c0, 0xc421, 0xb6ff, 0xc421, 0x22, 0 - .dw 0xb900, 0xc421, 0xb93f, 0xc421, 0x22, 0 - .dw 0xbb40, 0xc421, 0xbb7f, 0xc421, 0x22, 0 - .dw 0xbd80, 0xc421, 0xbdbf, 0xc421, 0x22, 0 - .dw 0xbfc0, 0xc421, 0xc03f, 0xc421, 0x22, 0 - .dw 0xc240, 0xc421, 0xc27f, 0xc421, 0x22, 0 - .dw 0xc480, 0xc421, 0xc4bf, 0xc421, 0x22, 0 - .dw 0xc6c0, 0xc421, 0xc6ff, 0xc421, 0x22, 0 - .dw 0xc900, 0xc421, 0xc93f, 0xc421, 0x22, 0 - .dw 0xcb40, 0xc421, 0xcb7f, 0xc421, 0x22, 0 - .dw 0xcd80, 0xc421, 0xcdbf, 0xc421, 0x22, 0 - .dw 0xcfc0, 0xc421, 0xd03f, 0xc421, 0x22, 0 - .dw 0xd240, 0xc421, 0xd27f, 0xc421, 0x22, 0 - .dw 0xd480, 0xc421, 0xd4bf, 0xc421, 0x22, 0 - .dw 0xd6c0, 0xc421, 0xd6ff, 0xc421, 0x22, 0 - .dw 0xd900, 0xc421, 0xd93f, 0xc421, 0x22, 0 - .dw 0xdb40, 0xc421, 0xdb7f, 0xc421, 0x22, 0 - .dw 0xdd80, 0xc421, 0xddbf, 0xc421, 0x22, 0 - .dw 0xdfc0, 0xc421, 0xe03f, 0xc421, 0x22, 0 - .dw 0xe240, 0xc421, 0xe27f, 0xc421, 0x22, 0 - .dw 0xe480, 0xc421, 0xe4bf, 0xc421, 0x22, 0 - .dw 0xe6c0, 0xc421, 0xe6ff, 0xc421, 0x22, 0 - .dw 0xe900, 0xc421, 0xe93f, 0xc421, 0x22, 0 - .dw 0xeb40, 0xc421, 0xeb7f, 0xc421, 0x22, 0 - .dw 0xed80, 0xc421, 0xedbf, 0xc421, 0x22, 0 - .dw 0xefc0, 0xc421, 0xf03f, 0xc421, 0x22, 0 - .dw 0xf240, 0xc421, 0xf27f, 0xc421, 0x22, 0 - .dw 0xf480, 0xc421, 0xf4bf, 0xc421, 0x22, 0 - .dw 0xf6c0, 0xc421, 0xf6ff, 0xc421, 0x22, 0 - .dw 0xf900, 0xc421, 0xf93f, 0xc421, 0x22, 0 - .dw 0xfb40, 0xc421, 0xfb7f, 0xc421, 0x22, 0 - .dw 0xfd80, 0xc421, 0xfdbf, 0xc421, 0x22, 0 - .dw 0xffc0, 0xc421, 0xffff, 0xc421, 0x22, 0 - .dw 0x1000, 0xc422, 0x1fff, 0xc422, 0x21, 0 - .dw 0x3000, 0xc422, 0x3fff, 0xc422, 0x21, 0 - .dw 0x5000, 0xc422, 0x5fff, 0xc422, 0x21, 0 - .dw 0x7000, 0xc422, 0x7fff, 0xc422, 0x21, 0 - .dw 0x9000, 0xc422, 0x9fff, 0xc422, 0x21, 0 - .dw 0xb000, 0xc422, 0xbfff, 0xc422, 0x21, 0 - .dw 0xd000, 0xc422, 0xdfff, 0xc422, 0x21, 0 - .dw 0xf000, 0xc422, 0xffff, 0xc422, 0x21, 0 - .dw 0x1000, 0xc423, 0x1fff, 0xc423, 0x21, 0 - .dw 0x3000, 0xc423, 0x3fff, 0xc423, 0x21, 0 - .dw 0x5000, 0xc423, 0x5fff, 0xc423, 0x21, 0 - .dw 0x7000, 0xc423, 0x7fff, 0xc423, 0x21, 0 - .dw 0x9000, 0xc423, 0x9fff, 0xc423, 0x21, 0 - .dw 0xb000, 0xc423, 0xbfff, 0xc423, 0x21, 0 - .dw 0xd000, 0xc423, 0xdfff, 0xc423, 0x21, 0 - .dw 0xf000, 0xc423, 0xffff, 0xc424, 0x21, 0 - .dw 0x1000, 0xc425, 0x3fff, 0xc425, 0x21, 0 - .dw 0x5000, 0xc425, 0x8fff, 0xc425, 0x21, 0 - .dw 0xa000, 0xc425, 0xcfff, 0xc425, 0x21, 0 - .dw 0xe000, 0xc425, 0xffff, 0xc428, 0x21, 0 - .dw 0x1000, 0xc429, 0x7fff, 0xc429, 0x21, 0 - .dw 0x9000, 0xc429, 0xffff, 0xc42a, 0x21, 0 - .dw 0x1000, 0xc42b, 0x3fff, 0xc42b, 0x21, 0 - .dw 0x5000, 0xc42b, 0xbfff, 0xc42c, 0x21, 0 - .dw 0xd000, 0xc42c, 0xffff, 0xc42d, 0x21, 0 - .dw 0x1000, 0xc42e, 0x3fff, 0xc42e, 0x21, 0 - .dw 0x5000, 0xc42e, 0xffff, 0xc42f, 0x21, 0 - .dw 0x1000, 0xc430, 0x3fff, 0xc430, 0x21, 0 - .dw 0x5000, 0xc430, 0xffff, 0xc435, 0x21, 0 - .dw 0x0001, 0xc436, 0x0001, 0xc436, 0x21, 0 - .dw 0x0003, 0xc436, 0x000f, 0xc436, 0x21, 0 - .dw 0x0011, 0xc436, 0x0011, 0xc436, 0x21, 0 - .dw 0x0013, 0xc436, 0x003f, 0xc436, 0x21, 0 - .dw 0x0041, 0xc436, 0x0041, 0xc436, 0x21, 0 - .dw 0x0043, 0xc436, 0x004f, 0xc436, 0x21, 0 - .dw 0x0051, 0xc436, 0x0051, 0xc436, 0x21, 0 - .dw 0x0053, 0xc436, 0x007f, 0xc436, 0x21, 0 - .dw 0x0081, 0xc436, 0x0081, 0xc436, 0x21, 0 - .dw 0x0083, 0xc436, 0x008f, 0xc436, 0x21, 0 - .dw 0x0091, 0xc436, 0x0091, 0xc436, 0x21, 0 - .dw 0x0093, 0xc436, 0x00bf, 0xc436, 0x21, 0 - .dw 0x00c1, 0xc436, 0x00c1, 0xc436, 0x21, 0 - .dw 0x00c3, 0xc436, 0x00cf, 0xc436, 0x21, 0 - .dw 0x00d1, 0xc436, 0x00d1, 0xc436, 0x21, 0 - .dw 0x00d3, 0xc436, 0x00ff, 0xc436, 0x21, 0 - .dw 0x0101, 0xc436, 0x0101, 0xc436, 0x21, 0 - .dw 0x0103, 0xc436, 0x010f, 0xc436, 0x21, 0 - .dw 0x0111, 0xc436, 0x0111, 0xc436, 0x21, 0 - .dw 0x0113, 0xc436, 0x013f, 0xc436, 0x21, 0 - .dw 0x0141, 0xc436, 0x0141, 0xc436, 0x21, 0 - .dw 0x0143, 0xc436, 0x014f, 0xc436, 0x21, 0 - .dw 0x0151, 0xc436, 0x0151, 0xc436, 0x21, 0 - .dw 0x0153, 0xc436, 0x017f, 0xc436, 0x21, 0 - .dw 0x0181, 0xc436, 0x0181, 0xc436, 0x21, 0 - .dw 0x0183, 0xc436, 0x018f, 0xc436, 0x21, 0 - .dw 0x0191, 0xc436, 0x0191, 0xc436, 0x21, 0 - .dw 0x0193, 0xc436, 0x01bf, 0xc436, 0x21, 0 - .dw 0x01c1, 0xc436, 0x01c1, 0xc436, 0x21, 0 - .dw 0x01c3, 0xc436, 0x01cf, 0xc436, 0x21, 0 - .dw 0x01d1, 0xc436, 0x01d1, 0xc436, 0x21, 0 - .dw 0x01d3, 0xc436, 0x01ff, 0xc436, 0x21, 0 - .dw 0x0201, 0xc436, 0x0201, 0xc436, 0x21, 0 - .dw 0x0203, 0xc436, 0x020f, 0xc436, 0x21, 0 - .dw 0x0211, 0xc436, 0x0211, 0xc436, 0x21, 0 - .dw 0x0213, 0xc436, 0x023f, 0xc436, 0x21, 0 - .dw 0x0241, 0xc436, 0x0241, 0xc436, 0x21, 0 - .dw 0x0243, 0xc436, 0x024f, 0xc436, 0x21, 0 - .dw 0x0251, 0xc436, 0x0251, 0xc436, 0x21, 0 - .dw 0x0253, 0xc436, 0x027f, 0xc436, 0x21, 0 - .dw 0x0281, 0xc436, 0x0281, 0xc436, 0x21, 0 - .dw 0x0283, 0xc436, 0x028f, 0xc436, 0x21, 0 - .dw 0x0291, 0xc436, 0x0291, 0xc436, 0x21, 0 - .dw 0x0293, 0xc436, 0x02bf, 0xc436, 0x21, 0 - .dw 0x02c1, 0xc436, 0x02c1, 0xc436, 0x21, 0 - .dw 0x02c3, 0xc436, 0x02cf, 0xc436, 0x21, 0 - .dw 0x02d1, 0xc436, 0x02d1, 0xc436, 0x21, 0 - .dw 0x02d3, 0xc436, 0x02ff, 0xc436, 0x21, 0 - .dw 0x0301, 0xc436, 0x0301, 0xc436, 0x21, 0 - .dw 0x0303, 0xc436, 0x030f, 0xc436, 0x21, 0 - .dw 0x0311, 0xc436, 0x0311, 0xc436, 0x21, 0 - .dw 0x0313, 0xc436, 0x033f, 0xc436, 0x21, 0 - .dw 0x0341, 0xc436, 0x0341, 0xc436, 0x21, 0 - .dw 0x0343, 0xc436, 0x034f, 0xc436, 0x21, 0 - .dw 0x0351, 0xc436, 0x0351, 0xc436, 0x21, 0 - .dw 0x0353, 0xc436, 0x037f, 0xc436, 0x21, 0 - .dw 0x0381, 0xc436, 0x0381, 0xc436, 0x21, 0 - .dw 0x0383, 0xc436, 0x038f, 0xc436, 0x21, 0 - .dw 0x0391, 0xc436, 0x0391, 0xc436, 0x21, 0 - .dw 0x0393, 0xc436, 0x03bf, 0xc436, 0x21, 0 - .dw 0x03c1, 0xc436, 0x03c1, 0xc436, 0x21, 0 - .dw 0x03c3, 0xc436, 0x03cf, 0xc436, 0x21, 0 - .dw 0x03d1, 0xc436, 0x03d1, 0xc436, 0x21, 0 - .dw 0x03d3, 0xc436, 0x03ff, 0xc436, 0x21, 0 - .dw 0x0401, 0xc436, 0x0401, 0xc436, 0x21, 0 - .dw 0x0403, 0xc436, 0x040f, 0xc436, 0x21, 0 - .dw 0x0411, 0xc436, 0x0411, 0xc436, 0x21, 0 - .dw 0x0413, 0xc436, 0x043f, 0xc436, 0x21, 0 - .dw 0x0441, 0xc436, 0x0441, 0xc436, 0x21, 0 - .dw 0x0443, 0xc436, 0x044f, 0xc436, 0x21, 0 - .dw 0x0451, 0xc436, 0x0451, 0xc436, 0x21, 0 - .dw 0x0453, 0xc436, 0x047f, 0xc436, 0x21, 0 - .dw 0x0481, 0xc436, 0x0481, 0xc436, 0x21, 0 - .dw 0x0483, 0xc436, 0x048f, 0xc436, 0x21, 0 - .dw 0x0491, 0xc436, 0x0491, 0xc436, 0x21, 0 - .dw 0x0493, 0xc436, 0x04bf, 0xc436, 0x21, 0 - .dw 0x04c1, 0xc436, 0x04c1, 0xc436, 0x21, 0 - .dw 0x04c3, 0xc436, 0x04cf, 0xc436, 0x21, 0 - .dw 0x04d1, 0xc436, 0x04d1, 0xc436, 0x21, 0 - .dw 0x04d3, 0xc436, 0x04ff, 0xc436, 0x21, 0 - .dw 0x0501, 0xc436, 0x0501, 0xc436, 0x21, 0 - .dw 0x0503, 0xc436, 0x050f, 0xc436, 0x21, 0 - .dw 0x0511, 0xc436, 0x0511, 0xc436, 0x21, 0 - .dw 0x0513, 0xc436, 0x053f, 0xc436, 0x21, 0 - .dw 0x0541, 0xc436, 0x0541, 0xc436, 0x21, 0 - .dw 0x0543, 0xc436, 0x054f, 0xc436, 0x21, 0 - .dw 0x0551, 0xc436, 0x0551, 0xc436, 0x21, 0 - .dw 0x0553, 0xc436, 0x057f, 0xc436, 0x21, 0 - .dw 0x0581, 0xc436, 0x0581, 0xc436, 0x21, 0 - .dw 0x0583, 0xc436, 0x058f, 0xc436, 0x21, 0 - .dw 0x0591, 0xc436, 0x0591, 0xc436, 0x21, 0 - .dw 0x0593, 0xc436, 0x05bf, 0xc436, 0x21, 0 - .dw 0x05c1, 0xc436, 0x05c1, 0xc436, 0x21, 0 - .dw 0x05c3, 0xc436, 0x05cf, 0xc436, 0x21, 0 - .dw 0x05d1, 0xc436, 0x05d1, 0xc436, 0x21, 0 - .dw 0x05d3, 0xc436, 0x05ff, 0xc436, 0x21, 0 - .dw 0x0601, 0xc436, 0x0601, 0xc436, 0x21, 0 - .dw 0x0603, 0xc436, 0x060f, 0xc436, 0x21, 0 - .dw 0x0611, 0xc436, 0x0611, 0xc436, 0x21, 0 - .dw 0x0613, 0xc436, 0x063f, 0xc436, 0x21, 0 - .dw 0x0641, 0xc436, 0x0641, 0xc436, 0x21, 0 - .dw 0x0643, 0xc436, 0x064f, 0xc436, 0x21, 0 - .dw 0x0651, 0xc436, 0x0651, 0xc436, 0x21, 0 - .dw 0x0653, 0xc436, 0x067f, 0xc436, 0x21, 0 - .dw 0x0681, 0xc436, 0x0681, 0xc436, 0x21, 0 - .dw 0x0683, 0xc436, 0x068f, 0xc436, 0x21, 0 - .dw 0x0691, 0xc436, 0x0691, 0xc436, 0x21, 0 - .dw 0x0693, 0xc436, 0x06bf, 0xc436, 0x21, 0 - .dw 0x06c1, 0xc436, 0x06c1, 0xc436, 0x21, 0 - .dw 0x06c3, 0xc436, 0x06cf, 0xc436, 0x21, 0 - .dw 0x06d1, 0xc436, 0x06d1, 0xc436, 0x21, 0 - .dw 0x06d3, 0xc436, 0x06ff, 0xc436, 0x21, 0 - .dw 0x0701, 0xc436, 0x0701, 0xc436, 0x21, 0 - .dw 0x0703, 0xc436, 0x070f, 0xc436, 0x21, 0 - .dw 0x0711, 0xc436, 0x0711, 0xc436, 0x21, 0 - .dw 0x0713, 0xc436, 0x073f, 0xc436, 0x21, 0 - .dw 0x0741, 0xc436, 0x0741, 0xc436, 0x21, 0 - .dw 0x0743, 0xc436, 0x074f, 0xc436, 0x21, 0 - .dw 0x0751, 0xc436, 0x0751, 0xc436, 0x21, 0 - .dw 0x0753, 0xc436, 0x077f, 0xc436, 0x21, 0 - .dw 0x0781, 0xc436, 0x0781, 0xc436, 0x21, 0 - .dw 0x0783, 0xc436, 0x078f, 0xc436, 0x21, 0 - .dw 0x0791, 0xc436, 0x0791, 0xc436, 0x21, 0 - .dw 0x0793, 0xc436, 0x07bf, 0xc436, 0x21, 0 - .dw 0x07c1, 0xc436, 0x07c1, 0xc436, 0x21, 0 - .dw 0x07c3, 0xc436, 0x07cf, 0xc436, 0x21, 0 - .dw 0x07d1, 0xc436, 0x07d1, 0xc436, 0x21, 0 - .dw 0x07d3, 0xc436, 0x07ff, 0xc436, 0x21, 0 - .dw 0x0801, 0xc436, 0x0801, 0xc436, 0x21, 0 - .dw 0x0803, 0xc436, 0x080f, 0xc436, 0x21, 0 - .dw 0x0811, 0xc436, 0x0811, 0xc436, 0x21, 0 - .dw 0x0813, 0xc436, 0x083f, 0xc436, 0x21, 0 - .dw 0x0841, 0xc436, 0x0841, 0xc436, 0x21, 0 - .dw 0x0843, 0xc436, 0x084f, 0xc436, 0x21, 0 - .dw 0x0851, 0xc436, 0x0851, 0xc436, 0x21, 0 - .dw 0x0853, 0xc436, 0x087f, 0xc436, 0x21, 0 - .dw 0x0881, 0xc436, 0x0881, 0xc436, 0x21, 0 - .dw 0x0883, 0xc436, 0x088f, 0xc436, 0x21, 0 - .dw 0x0891, 0xc436, 0x0891, 0xc436, 0x21, 0 - .dw 0x0893, 0xc436, 0x08bf, 0xc436, 0x21, 0 - .dw 0x08c1, 0xc436, 0x08c1, 0xc436, 0x21, 0 - .dw 0x08c3, 0xc436, 0x08cf, 0xc436, 0x21, 0 - .dw 0x08d1, 0xc436, 0x08d1, 0xc436, 0x21, 0 - .dw 0x08d3, 0xc436, 0x08ff, 0xc436, 0x21, 0 - .dw 0x0901, 0xc436, 0x0901, 0xc436, 0x21, 0 - .dw 0x0903, 0xc436, 0x090f, 0xc436, 0x21, 0 - .dw 0x0911, 0xc436, 0x0911, 0xc436, 0x21, 0 - .dw 0x0913, 0xc436, 0x093f, 0xc436, 0x21, 0 - .dw 0x0941, 0xc436, 0x0941, 0xc436, 0x21, 0 - .dw 0x0943, 0xc436, 0x094f, 0xc436, 0x21, 0 - .dw 0x0951, 0xc436, 0x0951, 0xc436, 0x21, 0 - .dw 0x0953, 0xc436, 0x097f, 0xc436, 0x21, 0 - .dw 0x0981, 0xc436, 0x0981, 0xc436, 0x21, 0 - .dw 0x0983, 0xc436, 0x098f, 0xc436, 0x21, 0 - .dw 0x0991, 0xc436, 0x0991, 0xc436, 0x21, 0 - .dw 0x0993, 0xc436, 0x09bf, 0xc436, 0x21, 0 - .dw 0x09c1, 0xc436, 0x09c1, 0xc436, 0x21, 0 - .dw 0x09c3, 0xc436, 0x09cf, 0xc436, 0x21, 0 - .dw 0x09d1, 0xc436, 0x09d1, 0xc436, 0x21, 0 - .dw 0x09d3, 0xc436, 0x09ff, 0xc436, 0x21, 0 - .dw 0x0a01, 0xc436, 0x0a01, 0xc436, 0x21, 0 - .dw 0x0a03, 0xc436, 0x0a0f, 0xc436, 0x21, 0 - .dw 0x0a11, 0xc436, 0x0a11, 0xc436, 0x21, 0 - .dw 0x0a13, 0xc436, 0x0a3f, 0xc436, 0x21, 0 - .dw 0x0a41, 0xc436, 0x0a41, 0xc436, 0x21, 0 - .dw 0x0a43, 0xc436, 0x0a4f, 0xc436, 0x21, 0 - .dw 0x0a51, 0xc436, 0x0a51, 0xc436, 0x21, 0 - .dw 0x0a53, 0xc436, 0x0a7f, 0xc436, 0x21, 0 - .dw 0x0a81, 0xc436, 0x0a81, 0xc436, 0x21, 0 - .dw 0x0a83, 0xc436, 0x0a8f, 0xc436, 0x21, 0 - .dw 0x0a91, 0xc436, 0x0a91, 0xc436, 0x21, 0 - .dw 0x0a93, 0xc436, 0x0abf, 0xc436, 0x21, 0 - .dw 0x0ac1, 0xc436, 0x0ac1, 0xc436, 0x21, 0 - .dw 0x0ac3, 0xc436, 0x0acf, 0xc436, 0x21, 0 - .dw 0x0ad1, 0xc436, 0x0ad1, 0xc436, 0x21, 0 - .dw 0x0ad3, 0xc436, 0x0aff, 0xc436, 0x21, 0 - .dw 0x0b01, 0xc436, 0x0b01, 0xc436, 0x21, 0 - .dw 0x0b03, 0xc436, 0x0b0f, 0xc436, 0x21, 0 - .dw 0x0b11, 0xc436, 0x0b11, 0xc436, 0x21, 0 - .dw 0x0b13, 0xc436, 0x0b3f, 0xc436, 0x21, 0 - .dw 0x0b41, 0xc436, 0x0b41, 0xc436, 0x21, 0 - .dw 0x0b43, 0xc436, 0x0b4f, 0xc436, 0x21, 0 - .dw 0x0b51, 0xc436, 0x0b51, 0xc436, 0x21, 0 - .dw 0x0b53, 0xc436, 0x0b7f, 0xc436, 0x21, 0 - .dw 0x0b81, 0xc436, 0x0b81, 0xc436, 0x21, 0 - .dw 0x0b83, 0xc436, 0x0b8f, 0xc436, 0x21, 0 - .dw 0x0b91, 0xc436, 0x0b91, 0xc436, 0x21, 0 - .dw 0x0b93, 0xc436, 0x0bbf, 0xc436, 0x21, 0 - .dw 0x0bc1, 0xc436, 0x0bc1, 0xc436, 0x21, 0 - .dw 0x0bc3, 0xc436, 0x0bcf, 0xc436, 0x21, 0 - .dw 0x0bd1, 0xc436, 0x0bd1, 0xc436, 0x21, 0 - .dw 0x0bd3, 0xc436, 0x0bff, 0xc436, 0x21, 0 - .dw 0x0c01, 0xc436, 0x0c01, 0xc436, 0x21, 0 - .dw 0x0c03, 0xc436, 0x0c0f, 0xc436, 0x21, 0 - .dw 0x0c11, 0xc436, 0x0c11, 0xc436, 0x21, 0 - .dw 0x0c13, 0xc436, 0x0c3f, 0xc436, 0x21, 0 - .dw 0x0c41, 0xc436, 0x0c41, 0xc436, 0x21, 0 - .dw 0x0c43, 0xc436, 0x0c4f, 0xc436, 0x21, 0 - .dw 0x0c51, 0xc436, 0x0c51, 0xc436, 0x21, 0 - .dw 0x0c53, 0xc436, 0x0c7f, 0xc436, 0x21, 0 - .dw 0x0c81, 0xc436, 0x0c81, 0xc436, 0x21, 0 - .dw 0x0c83, 0xc436, 0x0c8f, 0xc436, 0x21, 0 - .dw 0x0c91, 0xc436, 0x0c91, 0xc436, 0x21, 0 - .dw 0x0c93, 0xc436, 0x0cbf, 0xc436, 0x21, 0 - .dw 0x0cc1, 0xc436, 0x0cc1, 0xc436, 0x21, 0 - .dw 0x0cc3, 0xc436, 0x0ccf, 0xc436, 0x21, 0 - .dw 0x0cd1, 0xc436, 0x0cd1, 0xc436, 0x21, 0 - .dw 0x0cd3, 0xc436, 0x0cff, 0xc436, 0x21, 0 - .dw 0x0d01, 0xc436, 0x0d01, 0xc436, 0x21, 0 - .dw 0x0d03, 0xc436, 0x0d0f, 0xc436, 0x21, 0 - .dw 0x0d11, 0xc436, 0x0d11, 0xc436, 0x21, 0 - .dw 0x0d13, 0xc436, 0x0d3f, 0xc436, 0x21, 0 - .dw 0x0d41, 0xc436, 0x0d41, 0xc436, 0x21, 0 - .dw 0x0d43, 0xc436, 0x0d4f, 0xc436, 0x21, 0 - .dw 0x0d51, 0xc436, 0x0d51, 0xc436, 0x21, 0 - .dw 0x0d53, 0xc436, 0x0d7f, 0xc436, 0x21, 0 - .dw 0x0d81, 0xc436, 0x0d81, 0xc436, 0x21, 0 - .dw 0x0d83, 0xc436, 0x0d8f, 0xc436, 0x21, 0 - .dw 0x0d91, 0xc436, 0x0d91, 0xc436, 0x21, 0 - .dw 0x0d93, 0xc436, 0x0dbf, 0xc436, 0x21, 0 - .dw 0x0dc1, 0xc436, 0x0dc1, 0xc436, 0x21, 0 - .dw 0x0dc3, 0xc436, 0x0dcf, 0xc436, 0x21, 0 - .dw 0x0dd1, 0xc436, 0x0dd1, 0xc436, 0x21, 0 - .dw 0x0dd3, 0xc436, 0x0dff, 0xc436, 0x21, 0 - .dw 0x0e01, 0xc436, 0x0e01, 0xc436, 0x21, 0 - .dw 0x0e03, 0xc436, 0x0e0f, 0xc436, 0x21, 0 - .dw 0x0e11, 0xc436, 0x0e11, 0xc436, 0x21, 0 - .dw 0x0e13, 0xc436, 0x0e3f, 0xc436, 0x21, 0 - .dw 0x0e41, 0xc436, 0x0e41, 0xc436, 0x21, 0 - .dw 0x0e43, 0xc436, 0x0e4f, 0xc436, 0x21, 0 - .dw 0x0e51, 0xc436, 0x0e51, 0xc436, 0x21, 0 - .dw 0x0e53, 0xc436, 0x0e7f, 0xc436, 0x21, 0 - .dw 0x0e81, 0xc436, 0x0e81, 0xc436, 0x21, 0 - .dw 0x0e83, 0xc436, 0x0e8f, 0xc436, 0x21, 0 - .dw 0x0e91, 0xc436, 0x0e91, 0xc436, 0x21, 0 - .dw 0x0e93, 0xc436, 0x0ebf, 0xc436, 0x21, 0 - .dw 0x0ec1, 0xc436, 0x0ec1, 0xc436, 0x21, 0 - .dw 0x0ec3, 0xc436, 0x0ecf, 0xc436, 0x21, 0 - .dw 0x0ed1, 0xc436, 0x0ed1, 0xc436, 0x21, 0 - .dw 0x0ed3, 0xc436, 0x0eff, 0xc436, 0x21, 0 - .dw 0x0f01, 0xc436, 0x0f01, 0xc436, 0x21, 0 - .dw 0x0f03, 0xc436, 0x0f0f, 0xc436, 0x21, 0 - .dw 0x0f11, 0xc436, 0x0f11, 0xc436, 0x21, 0 - .dw 0x0f13, 0xc436, 0x0f3f, 0xc436, 0x21, 0 - .dw 0x0f41, 0xc436, 0x0f41, 0xc436, 0x21, 0 - .dw 0x0f43, 0xc436, 0x0f4f, 0xc436, 0x21, 0 - .dw 0x0f51, 0xc436, 0x0f51, 0xc436, 0x21, 0 - .dw 0x0f53, 0xc436, 0x0f7f, 0xc436, 0x21, 0 - .dw 0x0f81, 0xc436, 0x0f81, 0xc436, 0x21, 0 - .dw 0x0f83, 0xc436, 0x0f8f, 0xc436, 0x21, 0 - .dw 0x0f91, 0xc436, 0x0f91, 0xc436, 0x21, 0 - .dw 0x0f93, 0xc436, 0x0fbf, 0xc436, 0x21, 0 - .dw 0x0fc1, 0xc436, 0x0fc1, 0xc436, 0x21, 0 - .dw 0x0fc3, 0xc436, 0x0fcf, 0xc436, 0x21, 0 - .dw 0x0fd1, 0xc436, 0x0fd1, 0xc436, 0x21, 0 - .dw 0x0fd3, 0xc436, 0x1fff, 0xc436, 0x21, 0 - .dw 0x2001, 0xc436, 0x2001, 0xc436, 0x21, 0 - .dw 0x2003, 0xc436, 0x200f, 0xc436, 0x21, 0 - .dw 0x2011, 0xc436, 0x2011, 0xc436, 0x21, 0 - .dw 0x2013, 0xc436, 0x203f, 0xc436, 0x21, 0 - .dw 0x2041, 0xc436, 0x2041, 0xc436, 0x21, 0 - .dw 0x2043, 0xc436, 0x204f, 0xc436, 0x21, 0 - .dw 0x2051, 0xc436, 0x2051, 0xc436, 0x21, 0 - .dw 0x2053, 0xc436, 0x207f, 0xc436, 0x21, 0 - .dw 0x2081, 0xc436, 0x2081, 0xc436, 0x21, 0 - .dw 0x2083, 0xc436, 0x208f, 0xc436, 0x21, 0 - .dw 0x2091, 0xc436, 0x2091, 0xc436, 0x21, 0 - .dw 0x2093, 0xc436, 0x20bf, 0xc436, 0x21, 0 - .dw 0x20c1, 0xc436, 0x20c1, 0xc436, 0x21, 0 - .dw 0x20c3, 0xc436, 0x20cf, 0xc436, 0x21, 0 - .dw 0x20d1, 0xc436, 0x20d1, 0xc436, 0x21, 0 - .dw 0x20d3, 0xc436, 0x20ff, 0xc436, 0x21, 0 - .dw 0x2101, 0xc436, 0x2101, 0xc436, 0x21, 0 - .dw 0x2103, 0xc436, 0x210f, 0xc436, 0x21, 0 - .dw 0x2111, 0xc436, 0x2111, 0xc436, 0x21, 0 - .dw 0x2113, 0xc436, 0x213f, 0xc436, 0x21, 0 - .dw 0x2141, 0xc436, 0x2141, 0xc436, 0x21, 0 - .dw 0x2143, 0xc436, 0x214f, 0xc436, 0x21, 0 - .dw 0x2151, 0xc436, 0x2151, 0xc436, 0x21, 0 - .dw 0x2153, 0xc436, 0x217f, 0xc436, 0x21, 0 - .dw 0x2181, 0xc436, 0x2181, 0xc436, 0x21, 0 - .dw 0x2183, 0xc436, 0x218f, 0xc436, 0x21, 0 - .dw 0x2191, 0xc436, 0x2191, 0xc436, 0x21, 0 - .dw 0x2193, 0xc436, 0x21bf, 0xc436, 0x21, 0 - .dw 0x21c1, 0xc436, 0x21c1, 0xc436, 0x21, 0 - .dw 0x21c3, 0xc436, 0x21cf, 0xc436, 0x21, 0 - .dw 0x21d1, 0xc436, 0x21d1, 0xc436, 0x21, 0 - .dw 0x21d3, 0xc436, 0x21ff, 0xc436, 0x21, 0 - .dw 0x2201, 0xc436, 0x2201, 0xc436, 0x21, 0 - .dw 0x2203, 0xc436, 0x220f, 0xc436, 0x21, 0 - .dw 0x2211, 0xc436, 0x2211, 0xc436, 0x21, 0 - .dw 0x2213, 0xc436, 0x223f, 0xc436, 0x21, 0 - .dw 0x2241, 0xc436, 0x2241, 0xc436, 0x21, 0 - .dw 0x2243, 0xc436, 0x224f, 0xc436, 0x21, 0 - .dw 0x2251, 0xc436, 0x2251, 0xc436, 0x21, 0 - .dw 0x2253, 0xc436, 0x227f, 0xc436, 0x21, 0 - .dw 0x2281, 0xc436, 0x2281, 0xc436, 0x21, 0 - .dw 0x2283, 0xc436, 0x228f, 0xc436, 0x21, 0 - .dw 0x2291, 0xc436, 0x2291, 0xc436, 0x21, 0 - .dw 0x2293, 0xc436, 0x22bf, 0xc436, 0x21, 0 - .dw 0x22c1, 0xc436, 0x22c1, 0xc436, 0x21, 0 - .dw 0x22c3, 0xc436, 0x22cf, 0xc436, 0x21, 0 - .dw 0x22d1, 0xc436, 0x22d1, 0xc436, 0x21, 0 - .dw 0x22d3, 0xc436, 0x22ff, 0xc436, 0x21, 0 - .dw 0x2301, 0xc436, 0x2301, 0xc436, 0x21, 0 - .dw 0x2303, 0xc436, 0x230f, 0xc436, 0x21, 0 - .dw 0x2311, 0xc436, 0x2311, 0xc436, 0x21, 0 - .dw 0x2313, 0xc436, 0x233f, 0xc436, 0x21, 0 - .dw 0x2341, 0xc436, 0x2341, 0xc436, 0x21, 0 - .dw 0x2343, 0xc436, 0x234f, 0xc436, 0x21, 0 - .dw 0x2351, 0xc436, 0x2351, 0xc436, 0x21, 0 - .dw 0x2353, 0xc436, 0x237f, 0xc436, 0x21, 0 - .dw 0x2381, 0xc436, 0x2381, 0xc436, 0x21, 0 - .dw 0x2383, 0xc436, 0x238f, 0xc436, 0x21, 0 - .dw 0x2391, 0xc436, 0x2391, 0xc436, 0x21, 0 - .dw 0x2393, 0xc436, 0x23bf, 0xc436, 0x21, 0 - .dw 0x23c1, 0xc436, 0x23c1, 0xc436, 0x21, 0 - .dw 0x23c3, 0xc436, 0x23cf, 0xc436, 0x21, 0 - .dw 0x23d1, 0xc436, 0x23d1, 0xc436, 0x21, 0 - .dw 0x23d3, 0xc436, 0x23ff, 0xc436, 0x21, 0 - .dw 0x2401, 0xc436, 0x2401, 0xc436, 0x21, 0 - .dw 0x2403, 0xc436, 0x240f, 0xc436, 0x21, 0 - .dw 0x2411, 0xc436, 0x2411, 0xc436, 0x21, 0 - .dw 0x2413, 0xc436, 0x243f, 0xc436, 0x21, 0 - .dw 0x2441, 0xc436, 0x2441, 0xc436, 0x21, 0 - .dw 0x2443, 0xc436, 0x244f, 0xc436, 0x21, 0 - .dw 0x2451, 0xc436, 0x2451, 0xc436, 0x21, 0 - .dw 0x2453, 0xc436, 0x247f, 0xc436, 0x21, 0 - .dw 0x2481, 0xc436, 0x2481, 0xc436, 0x21, 0 - .dw 0x2483, 0xc436, 0x248f, 0xc436, 0x21, 0 - .dw 0x2491, 0xc436, 0x2491, 0xc436, 0x21, 0 - .dw 0x2493, 0xc436, 0x24bf, 0xc436, 0x21, 0 - .dw 0x24c1, 0xc436, 0x24c1, 0xc436, 0x21, 0 - .dw 0x24c3, 0xc436, 0x24cf, 0xc436, 0x21, 0 - .dw 0x24d1, 0xc436, 0x24d1, 0xc436, 0x21, 0 - .dw 0x24d3, 0xc436, 0x24ff, 0xc436, 0x21, 0 - .dw 0x2501, 0xc436, 0x2501, 0xc436, 0x21, 0 - .dw 0x2503, 0xc436, 0x250f, 0xc436, 0x21, 0 - .dw 0x2511, 0xc436, 0x2511, 0xc436, 0x21, 0 - .dw 0x2513, 0xc436, 0x253f, 0xc436, 0x21, 0 - .dw 0x2541, 0xc436, 0x2541, 0xc436, 0x21, 0 - .dw 0x2543, 0xc436, 0x254f, 0xc436, 0x21, 0 - .dw 0x2551, 0xc436, 0x2551, 0xc436, 0x21, 0 - .dw 0x2553, 0xc436, 0x257f, 0xc436, 0x21, 0 - .dw 0x2581, 0xc436, 0x2581, 0xc436, 0x21, 0 - .dw 0x2583, 0xc436, 0x258f, 0xc436, 0x21, 0 - .dw 0x2591, 0xc436, 0x2591, 0xc436, 0x21, 0 - .dw 0x2593, 0xc436, 0x25bf, 0xc436, 0x21, 0 - .dw 0x25c1, 0xc436, 0x25c1, 0xc436, 0x21, 0 - .dw 0x25c3, 0xc436, 0x25cf, 0xc436, 0x21, 0 - .dw 0x25d1, 0xc436, 0x25d1, 0xc436, 0x21, 0 - .dw 0x25d3, 0xc436, 0x25ff, 0xc436, 0x21, 0 - .dw 0x2601, 0xc436, 0x2601, 0xc436, 0x21, 0 - .dw 0x2603, 0xc436, 0x260f, 0xc436, 0x21, 0 - .dw 0x2611, 0xc436, 0x2611, 0xc436, 0x21, 0 - .dw 0x2613, 0xc436, 0x263f, 0xc436, 0x21, 0 - .dw 0x2641, 0xc436, 0x2641, 0xc436, 0x21, 0 - .dw 0x2643, 0xc436, 0x264f, 0xc436, 0x21, 0 - .dw 0x2651, 0xc436, 0x2651, 0xc436, 0x21, 0 - .dw 0x2653, 0xc436, 0x267f, 0xc436, 0x21, 0 - .dw 0x2681, 0xc436, 0x2681, 0xc436, 0x21, 0 - .dw 0x2683, 0xc436, 0x268f, 0xc436, 0x21, 0 - .dw 0x2691, 0xc436, 0x2691, 0xc436, 0x21, 0 - .dw 0x2693, 0xc436, 0x26bf, 0xc436, 0x21, 0 - .dw 0x26c1, 0xc436, 0x26c1, 0xc436, 0x21, 0 - .dw 0x26c3, 0xc436, 0x26cf, 0xc436, 0x21, 0 - .dw 0x26d1, 0xc436, 0x26d1, 0xc436, 0x21, 0 - .dw 0x26d3, 0xc436, 0x26ff, 0xc436, 0x21, 0 - .dw 0x2701, 0xc436, 0x2701, 0xc436, 0x21, 0 - .dw 0x2703, 0xc436, 0x270f, 0xc436, 0x21, 0 - .dw 0x2711, 0xc436, 0x2711, 0xc436, 0x21, 0 - .dw 0x2713, 0xc436, 0x273f, 0xc436, 0x21, 0 - .dw 0x2741, 0xc436, 0x2741, 0xc436, 0x21, 0 - .dw 0x2743, 0xc436, 0x274f, 0xc436, 0x21, 0 - .dw 0x2751, 0xc436, 0x2751, 0xc436, 0x21, 0 - .dw 0x2753, 0xc436, 0x277f, 0xc436, 0x21, 0 - .dw 0x2781, 0xc436, 0x2781, 0xc436, 0x21, 0 - .dw 0x2783, 0xc436, 0x278f, 0xc436, 0x21, 0 - .dw 0x2791, 0xc436, 0x2791, 0xc436, 0x21, 0 - .dw 0x2793, 0xc436, 0x27bf, 0xc436, 0x21, 0 - .dw 0x27c1, 0xc436, 0x27c1, 0xc436, 0x21, 0 - .dw 0x27c3, 0xc436, 0x27cf, 0xc436, 0x21, 0 - .dw 0x27d1, 0xc436, 0x27d1, 0xc436, 0x21, 0 - .dw 0x27d3, 0xc436, 0x27ff, 0xc436, 0x21, 0 - .dw 0x2801, 0xc436, 0x2801, 0xc436, 0x21, 0 - .dw 0x2803, 0xc436, 0x280f, 0xc436, 0x21, 0 - .dw 0x2811, 0xc436, 0x2811, 0xc436, 0x21, 0 - .dw 0x2813, 0xc436, 0x283f, 0xc436, 0x21, 0 - .dw 0x2841, 0xc436, 0x2841, 0xc436, 0x21, 0 - .dw 0x2843, 0xc436, 0x284f, 0xc436, 0x21, 0 - .dw 0x2851, 0xc436, 0x2851, 0xc436, 0x21, 0 - .dw 0x2853, 0xc436, 0x287f, 0xc436, 0x21, 0 - .dw 0x2881, 0xc436, 0x2881, 0xc436, 0x21, 0 - .dw 0x2883, 0xc436, 0x288f, 0xc436, 0x21, 0 - .dw 0x2891, 0xc436, 0x2891, 0xc436, 0x21, 0 - .dw 0x2893, 0xc436, 0x28bf, 0xc436, 0x21, 0 - .dw 0x28c1, 0xc436, 0x28c1, 0xc436, 0x21, 0 - .dw 0x28c3, 0xc436, 0x28cf, 0xc436, 0x21, 0 - .dw 0x28d1, 0xc436, 0x28d1, 0xc436, 0x21, 0 - .dw 0x28d3, 0xc436, 0x28ff, 0xc436, 0x21, 0 - .dw 0x2901, 0xc436, 0x2901, 0xc436, 0x21, 0 - .dw 0x2903, 0xc436, 0x290f, 0xc436, 0x21, 0 - .dw 0x2911, 0xc436, 0x2911, 0xc436, 0x21, 0 - .dw 0x2913, 0xc436, 0x293f, 0xc436, 0x21, 0 - .dw 0x2941, 0xc436, 0x2941, 0xc436, 0x21, 0 - .dw 0x2943, 0xc436, 0x294f, 0xc436, 0x21, 0 - .dw 0x2951, 0xc436, 0x2951, 0xc436, 0x21, 0 - .dw 0x2953, 0xc436, 0x297f, 0xc436, 0x21, 0 - .dw 0x2981, 0xc436, 0x2981, 0xc436, 0x21, 0 - .dw 0x2983, 0xc436, 0x298f, 0xc436, 0x21, 0 - .dw 0x2991, 0xc436, 0x2991, 0xc436, 0x21, 0 - .dw 0x2993, 0xc436, 0x29bf, 0xc436, 0x21, 0 - .dw 0x29c1, 0xc436, 0x29c1, 0xc436, 0x21, 0 - .dw 0x29c3, 0xc436, 0x29cf, 0xc436, 0x21, 0 - .dw 0x29d1, 0xc436, 0x29d1, 0xc436, 0x21, 0 - .dw 0x29d3, 0xc436, 0x29ff, 0xc436, 0x21, 0 - .dw 0x2a01, 0xc436, 0x2a01, 0xc436, 0x21, 0 - .dw 0x2a03, 0xc436, 0x2a0f, 0xc436, 0x21, 0 - .dw 0x2a11, 0xc436, 0x2a11, 0xc436, 0x21, 0 - .dw 0x2a13, 0xc436, 0x2a3f, 0xc436, 0x21, 0 - .dw 0x2a41, 0xc436, 0x2a41, 0xc436, 0x21, 0 - .dw 0x2a43, 0xc436, 0x2a4f, 0xc436, 0x21, 0 - .dw 0x2a51, 0xc436, 0x2a51, 0xc436, 0x21, 0 - .dw 0x2a53, 0xc436, 0x2a7f, 0xc436, 0x21, 0 - .dw 0x2a81, 0xc436, 0x2a81, 0xc436, 0x21, 0 - .dw 0x2a83, 0xc436, 0x2a8f, 0xc436, 0x21, 0 - .dw 0x2a91, 0xc436, 0x2a91, 0xc436, 0x21, 0 - .dw 0x2a93, 0xc436, 0x2abf, 0xc436, 0x21, 0 - .dw 0x2ac1, 0xc436, 0x2ac1, 0xc436, 0x21, 0 - .dw 0x2ac3, 0xc436, 0x2acf, 0xc436, 0x21, 0 - .dw 0x2ad1, 0xc436, 0x2ad1, 0xc436, 0x21, 0 - .dw 0x2ad3, 0xc436, 0x2aff, 0xc436, 0x21, 0 - .dw 0x2b01, 0xc436, 0x2b01, 0xc436, 0x21, 0 - .dw 0x2b03, 0xc436, 0x2b0f, 0xc436, 0x21, 0 - .dw 0x2b11, 0xc436, 0x2b11, 0xc436, 0x21, 0 - .dw 0x2b13, 0xc436, 0x2b3f, 0xc436, 0x21, 0 - .dw 0x2b41, 0xc436, 0x2b41, 0xc436, 0x21, 0 - .dw 0x2b43, 0xc436, 0x2b4f, 0xc436, 0x21, 0 - .dw 0x2b51, 0xc436, 0x2b51, 0xc436, 0x21, 0 - .dw 0x2b53, 0xc436, 0x2b7f, 0xc436, 0x21, 0 - .dw 0x2b81, 0xc436, 0x2b81, 0xc436, 0x21, 0 - .dw 0x2b83, 0xc436, 0x2b8f, 0xc436, 0x21, 0 - .dw 0x2b91, 0xc436, 0x2b91, 0xc436, 0x21, 0 - .dw 0x2b93, 0xc436, 0x2bbf, 0xc436, 0x21, 0 - .dw 0x2bc1, 0xc436, 0x2bc1, 0xc436, 0x21, 0 - .dw 0x2bc3, 0xc436, 0x2bcf, 0xc436, 0x21, 0 - .dw 0x2bd1, 0xc436, 0x2bd1, 0xc436, 0x21, 0 - .dw 0x2bd3, 0xc436, 0x2bff, 0xc436, 0x21, 0 - .dw 0x2c01, 0xc436, 0x2c01, 0xc436, 0x21, 0 - .dw 0x2c03, 0xc436, 0x2c0f, 0xc436, 0x21, 0 - .dw 0x2c11, 0xc436, 0x2c11, 0xc436, 0x21, 0 - .dw 0x2c13, 0xc436, 0x2c3f, 0xc436, 0x21, 0 - .dw 0x2c41, 0xc436, 0x2c41, 0xc436, 0x21, 0 - .dw 0x2c43, 0xc436, 0x2c4f, 0xc436, 0x21, 0 - .dw 0x2c51, 0xc436, 0x2c51, 0xc436, 0x21, 0 - .dw 0x2c53, 0xc436, 0x2c7f, 0xc436, 0x21, 0 - .dw 0x2c81, 0xc436, 0x2c81, 0xc436, 0x21, 0 - .dw 0x2c83, 0xc436, 0x2c8f, 0xc436, 0x21, 0 - .dw 0x2c91, 0xc436, 0x2c91, 0xc436, 0x21, 0 - .dw 0x2c93, 0xc436, 0x2cbf, 0xc436, 0x21, 0 - .dw 0x2cc1, 0xc436, 0x2cc1, 0xc436, 0x21, 0 - .dw 0x2cc3, 0xc436, 0x2ccf, 0xc436, 0x21, 0 - .dw 0x2cd1, 0xc436, 0x2cd1, 0xc436, 0x21, 0 - .dw 0x2cd3, 0xc436, 0x2cff, 0xc436, 0x21, 0 - .dw 0x2d01, 0xc436, 0x2d01, 0xc436, 0x21, 0 - .dw 0x2d03, 0xc436, 0x2d0f, 0xc436, 0x21, 0 - .dw 0x2d11, 0xc436, 0x2d11, 0xc436, 0x21, 0 - .dw 0x2d13, 0xc436, 0x2d3f, 0xc436, 0x21, 0 - .dw 0x2d41, 0xc436, 0x2d41, 0xc436, 0x21, 0 - .dw 0x2d43, 0xc436, 0x2d4f, 0xc436, 0x21, 0 - .dw 0x2d51, 0xc436, 0x2d51, 0xc436, 0x21, 0 - .dw 0x2d53, 0xc436, 0x2d7f, 0xc436, 0x21, 0 - .dw 0x2d81, 0xc436, 0x2d81, 0xc436, 0x21, 0 - .dw 0x2d83, 0xc436, 0x2d8f, 0xc436, 0x21, 0 - .dw 0x2d91, 0xc436, 0x2d91, 0xc436, 0x21, 0 - .dw 0x2d93, 0xc436, 0x2dbf, 0xc436, 0x21, 0 - .dw 0x2dc1, 0xc436, 0x2dc1, 0xc436, 0x21, 0 - .dw 0x2dc3, 0xc436, 0x2dcf, 0xc436, 0x21, 0 - .dw 0x2dd1, 0xc436, 0x2dd1, 0xc436, 0x21, 0 - .dw 0x2dd3, 0xc436, 0x2dff, 0xc436, 0x21, 0 - .dw 0x2e01, 0xc436, 0x2e01, 0xc436, 0x21, 0 - .dw 0x2e03, 0xc436, 0x2e0f, 0xc436, 0x21, 0 - .dw 0x2e11, 0xc436, 0x2e11, 0xc436, 0x21, 0 - .dw 0x2e13, 0xc436, 0x2e3f, 0xc436, 0x21, 0 - .dw 0x2e41, 0xc436, 0x2e41, 0xc436, 0x21, 0 - .dw 0x2e43, 0xc436, 0x2e4f, 0xc436, 0x21, 0 - .dw 0x2e51, 0xc436, 0x2e51, 0xc436, 0x21, 0 - .dw 0x2e53, 0xc436, 0x2e7f, 0xc436, 0x21, 0 - .dw 0x2e81, 0xc436, 0x2e81, 0xc436, 0x21, 0 - .dw 0x2e83, 0xc436, 0x2e8f, 0xc436, 0x21, 0 - .dw 0x2e91, 0xc436, 0x2e91, 0xc436, 0x21, 0 - .dw 0x2e93, 0xc436, 0x2ebf, 0xc436, 0x21, 0 - .dw 0x2ec1, 0xc436, 0x2ec1, 0xc436, 0x21, 0 - .dw 0x2ec3, 0xc436, 0x2ecf, 0xc436, 0x21, 0 - .dw 0x2ed1, 0xc436, 0x2ed1, 0xc436, 0x21, 0 - .dw 0x2ed3, 0xc436, 0x2eff, 0xc436, 0x21, 0 - .dw 0x2f01, 0xc436, 0x2f01, 0xc436, 0x21, 0 - .dw 0x2f03, 0xc436, 0x2f0f, 0xc436, 0x21, 0 - .dw 0x2f11, 0xc436, 0x2f11, 0xc436, 0x21, 0 - .dw 0x2f13, 0xc436, 0x2f3f, 0xc436, 0x21, 0 - .dw 0x2f41, 0xc436, 0x2f41, 0xc436, 0x21, 0 - .dw 0x2f43, 0xc436, 0x2f4f, 0xc436, 0x21, 0 - .dw 0x2f51, 0xc436, 0x2f51, 0xc436, 0x21, 0 - .dw 0x2f53, 0xc436, 0x2f7f, 0xc436, 0x21, 0 - .dw 0x2f81, 0xc436, 0x2f81, 0xc436, 0x21, 0 - .dw 0x2f83, 0xc436, 0x2f8f, 0xc436, 0x21, 0 - .dw 0x2f91, 0xc436, 0x2f91, 0xc436, 0x21, 0 - .dw 0x2f93, 0xc436, 0x2fbf, 0xc436, 0x21, 0 - .dw 0x2fc1, 0xc436, 0x2fc1, 0xc436, 0x21, 0 - .dw 0x2fc3, 0xc436, 0x2fcf, 0xc436, 0x21, 0 - .dw 0x2fd1, 0xc436, 0x2fd1, 0xc436, 0x21, 0 - .dw 0x2fd3, 0xc436, 0x3fff, 0xc436, 0x21, 0 - .dw 0x4001, 0xc436, 0x4001, 0xc436, 0x21, 0 - .dw 0x4003, 0xc436, 0x400f, 0xc436, 0x21, 0 - .dw 0x4011, 0xc436, 0x4011, 0xc436, 0x21, 0 - .dw 0x4013, 0xc436, 0x403f, 0xc436, 0x21, 0 - .dw 0x4041, 0xc436, 0x4041, 0xc436, 0x21, 0 - .dw 0x4043, 0xc436, 0x404f, 0xc436, 0x21, 0 - .dw 0x4051, 0xc436, 0x4051, 0xc436, 0x21, 0 - .dw 0x4053, 0xc436, 0x407f, 0xc436, 0x21, 0 - .dw 0x4081, 0xc436, 0x4081, 0xc436, 0x21, 0 - .dw 0x4083, 0xc436, 0x408f, 0xc436, 0x21, 0 - .dw 0x4091, 0xc436, 0x4091, 0xc436, 0x21, 0 - .dw 0x4093, 0xc436, 0x40bf, 0xc436, 0x21, 0 - .dw 0x40c1, 0xc436, 0x40c1, 0xc436, 0x21, 0 - .dw 0x40c3, 0xc436, 0x40cf, 0xc436, 0x21, 0 - .dw 0x40d1, 0xc436, 0x40d1, 0xc436, 0x21, 0 - .dw 0x40d3, 0xc436, 0x40ff, 0xc436, 0x21, 0 - .dw 0x4101, 0xc436, 0x4101, 0xc436, 0x21, 0 - .dw 0x4103, 0xc436, 0x410f, 0xc436, 0x21, 0 - .dw 0x4111, 0xc436, 0x4111, 0xc436, 0x21, 0 - .dw 0x4113, 0xc436, 0x413f, 0xc436, 0x21, 0 - .dw 0x4141, 0xc436, 0x4141, 0xc436, 0x21, 0 - .dw 0x4143, 0xc436, 0x414f, 0xc436, 0x21, 0 - .dw 0x4151, 0xc436, 0x4151, 0xc436, 0x21, 0 - .dw 0x4153, 0xc436, 0x417f, 0xc436, 0x21, 0 - .dw 0x4181, 0xc436, 0x4181, 0xc436, 0x21, 0 - .dw 0x4183, 0xc436, 0x418f, 0xc436, 0x21, 0 - .dw 0x4191, 0xc436, 0x4191, 0xc436, 0x21, 0 - .dw 0x4193, 0xc436, 0x41bf, 0xc436, 0x21, 0 - .dw 0x41c1, 0xc436, 0x41c1, 0xc436, 0x21, 0 - .dw 0x41c3, 0xc436, 0x41cf, 0xc436, 0x21, 0 - .dw 0x41d1, 0xc436, 0x41d1, 0xc436, 0x21, 0 - .dw 0x41d3, 0xc436, 0x41ff, 0xc436, 0x21, 0 - .dw 0x4201, 0xc436, 0x4201, 0xc436, 0x21, 0 - .dw 0x4203, 0xc436, 0x420f, 0xc436, 0x21, 0 - .dw 0x4211, 0xc436, 0x4211, 0xc436, 0x21, 0 - .dw 0x4213, 0xc436, 0x423f, 0xc436, 0x21, 0 - .dw 0x4241, 0xc436, 0x4241, 0xc436, 0x21, 0 - .dw 0x4243, 0xc436, 0x424f, 0xc436, 0x21, 0 - .dw 0x4251, 0xc436, 0x4251, 0xc436, 0x21, 0 - .dw 0x4253, 0xc436, 0x427f, 0xc436, 0x21, 0 - .dw 0x4281, 0xc436, 0x4281, 0xc436, 0x21, 0 - .dw 0x4283, 0xc436, 0x428f, 0xc436, 0x21, 0 - .dw 0x4291, 0xc436, 0x4291, 0xc436, 0x21, 0 - .dw 0x4293, 0xc436, 0x42bf, 0xc436, 0x21, 0 - .dw 0x42c1, 0xc436, 0x42c1, 0xc436, 0x21, 0 - .dw 0x42c3, 0xc436, 0x42cf, 0xc436, 0x21, 0 - .dw 0x42d1, 0xc436, 0x42d1, 0xc436, 0x21, 0 - .dw 0x42d3, 0xc436, 0x42ff, 0xc436, 0x21, 0 - .dw 0x4301, 0xc436, 0x4301, 0xc436, 0x21, 0 - .dw 0x4303, 0xc436, 0x430f, 0xc436, 0x21, 0 - .dw 0x4311, 0xc436, 0x4311, 0xc436, 0x21, 0 - .dw 0x4313, 0xc436, 0x433f, 0xc436, 0x21, 0 - .dw 0x4341, 0xc436, 0x4341, 0xc436, 0x21, 0 - .dw 0x4343, 0xc436, 0x434f, 0xc436, 0x21, 0 - .dw 0x4351, 0xc436, 0x4351, 0xc436, 0x21, 0 - .dw 0x4353, 0xc436, 0x437f, 0xc436, 0x21, 0 - .dw 0x4381, 0xc436, 0x4381, 0xc436, 0x21, 0 - .dw 0x4383, 0xc436, 0x438f, 0xc436, 0x21, 0 - .dw 0x4391, 0xc436, 0x4391, 0xc436, 0x21, 0 - .dw 0x4393, 0xc436, 0x43bf, 0xc436, 0x21, 0 - .dw 0x43c1, 0xc436, 0x43c1, 0xc436, 0x21, 0 - .dw 0x43c3, 0xc436, 0x43cf, 0xc436, 0x21, 0 - .dw 0x43d1, 0xc436, 0x43d1, 0xc436, 0x21, 0 - .dw 0x43d3, 0xc436, 0x43ff, 0xc436, 0x21, 0 - .dw 0x4401, 0xc436, 0x4401, 0xc436, 0x21, 0 - .dw 0x4403, 0xc436, 0x440f, 0xc436, 0x21, 0 - .dw 0x4411, 0xc436, 0x4411, 0xc436, 0x21, 0 - .dw 0x4413, 0xc436, 0x443f, 0xc436, 0x21, 0 - .dw 0x4441, 0xc436, 0x4441, 0xc436, 0x21, 0 - .dw 0x4443, 0xc436, 0x444f, 0xc436, 0x21, 0 - .dw 0x4451, 0xc436, 0x4451, 0xc436, 0x21, 0 - .dw 0x4453, 0xc436, 0x447f, 0xc436, 0x21, 0 - .dw 0x4481, 0xc436, 0x4481, 0xc436, 0x21, 0 - .dw 0x4483, 0xc436, 0x448f, 0xc436, 0x21, 0 - .dw 0x4491, 0xc436, 0x4491, 0xc436, 0x21, 0 - .dw 0x4493, 0xc436, 0x44bf, 0xc436, 0x21, 0 - .dw 0x44c1, 0xc436, 0x44c1, 0xc436, 0x21, 0 - .dw 0x44c3, 0xc436, 0x44cf, 0xc436, 0x21, 0 - .dw 0x44d1, 0xc436, 0x44d1, 0xc436, 0x21, 0 - .dw 0x44d3, 0xc436, 0x44ff, 0xc436, 0x21, 0 - .dw 0x4501, 0xc436, 0x4501, 0xc436, 0x21, 0 - .dw 0x4503, 0xc436, 0x450f, 0xc436, 0x21, 0 - .dw 0x4511, 0xc436, 0x4511, 0xc436, 0x21, 0 - .dw 0x4513, 0xc436, 0x453f, 0xc436, 0x21, 0 - .dw 0x4541, 0xc436, 0x4541, 0xc436, 0x21, 0 - .dw 0x4543, 0xc436, 0x454f, 0xc436, 0x21, 0 - .dw 0x4551, 0xc436, 0x4551, 0xc436, 0x21, 0 - .dw 0x4553, 0xc436, 0x457f, 0xc436, 0x21, 0 - .dw 0x4581, 0xc436, 0x4581, 0xc436, 0x21, 0 - .dw 0x4583, 0xc436, 0x458f, 0xc436, 0x21, 0 - .dw 0x4591, 0xc436, 0x4591, 0xc436, 0x21, 0 - .dw 0x4593, 0xc436, 0x45bf, 0xc436, 0x21, 0 - .dw 0x45c1, 0xc436, 0x45c1, 0xc436, 0x21, 0 - .dw 0x45c3, 0xc436, 0x45cf, 0xc436, 0x21, 0 - .dw 0x45d1, 0xc436, 0x45d1, 0xc436, 0x21, 0 - .dw 0x45d3, 0xc436, 0x45ff, 0xc436, 0x21, 0 - .dw 0x4601, 0xc436, 0x4601, 0xc436, 0x21, 0 - .dw 0x4603, 0xc436, 0x460f, 0xc436, 0x21, 0 - .dw 0x4611, 0xc436, 0x4611, 0xc436, 0x21, 0 - .dw 0x4613, 0xc436, 0x463f, 0xc436, 0x21, 0 - .dw 0x4641, 0xc436, 0x4641, 0xc436, 0x21, 0 - .dw 0x4643, 0xc436, 0x464f, 0xc436, 0x21, 0 - .dw 0x4651, 0xc436, 0x4651, 0xc436, 0x21, 0 - .dw 0x4653, 0xc436, 0x467f, 0xc436, 0x21, 0 - .dw 0x4681, 0xc436, 0x4681, 0xc436, 0x21, 0 - .dw 0x4683, 0xc436, 0x468f, 0xc436, 0x21, 0 - .dw 0x4691, 0xc436, 0x4691, 0xc436, 0x21, 0 - .dw 0x4693, 0xc436, 0x46bf, 0xc436, 0x21, 0 - .dw 0x46c1, 0xc436, 0x46c1, 0xc436, 0x21, 0 - .dw 0x46c3, 0xc436, 0x46cf, 0xc436, 0x21, 0 - .dw 0x46d1, 0xc436, 0x46d1, 0xc436, 0x21, 0 - .dw 0x46d3, 0xc436, 0x46ff, 0xc436, 0x21, 0 - .dw 0x4701, 0xc436, 0x4701, 0xc436, 0x21, 0 - .dw 0x4703, 0xc436, 0x470f, 0xc436, 0x21, 0 - .dw 0x4711, 0xc436, 0x4711, 0xc436, 0x21, 0 - .dw 0x4713, 0xc436, 0x473f, 0xc436, 0x21, 0 - .dw 0x4741, 0xc436, 0x4741, 0xc436, 0x21, 0 - .dw 0x4743, 0xc436, 0x474f, 0xc436, 0x21, 0 - .dw 0x4751, 0xc436, 0x4751, 0xc436, 0x21, 0 - .dw 0x4753, 0xc436, 0x477f, 0xc436, 0x21, 0 - .dw 0x4781, 0xc436, 0x4781, 0xc436, 0x21, 0 - .dw 0x4783, 0xc436, 0x478f, 0xc436, 0x21, 0 - .dw 0x4791, 0xc436, 0x4791, 0xc436, 0x21, 0 - .dw 0x4793, 0xc436, 0x47bf, 0xc436, 0x21, 0 - .dw 0x47c1, 0xc436, 0x47c1, 0xc436, 0x21, 0 - .dw 0x47c3, 0xc436, 0x47cf, 0xc436, 0x21, 0 - .dw 0x47d1, 0xc436, 0x47d1, 0xc436, 0x21, 0 - .dw 0x47d3, 0xc436, 0x47ff, 0xc436, 0x21, 0 - .dw 0x4801, 0xc436, 0x4801, 0xc436, 0x21, 0 - .dw 0x4803, 0xc436, 0x480f, 0xc436, 0x21, 0 - .dw 0x4811, 0xc436, 0x4811, 0xc436, 0x21, 0 - .dw 0x4813, 0xc436, 0x483f, 0xc436, 0x21, 0 - .dw 0x4841, 0xc436, 0x4841, 0xc436, 0x21, 0 - .dw 0x4843, 0xc436, 0x484f, 0xc436, 0x21, 0 - .dw 0x4851, 0xc436, 0x4851, 0xc436, 0x21, 0 - .dw 0x4853, 0xc436, 0x487f, 0xc436, 0x21, 0 - .dw 0x4881, 0xc436, 0x4881, 0xc436, 0x21, 0 - .dw 0x4883, 0xc436, 0x488f, 0xc436, 0x21, 0 - .dw 0x4891, 0xc436, 0x4891, 0xc436, 0x21, 0 - .dw 0x4893, 0xc436, 0x48bf, 0xc436, 0x21, 0 - .dw 0x48c1, 0xc436, 0x48c1, 0xc436, 0x21, 0 - .dw 0x48c3, 0xc436, 0x48cf, 0xc436, 0x21, 0 - .dw 0x48d1, 0xc436, 0x48d1, 0xc436, 0x21, 0 - .dw 0x48d3, 0xc436, 0x48ff, 0xc436, 0x21, 0 - .dw 0x4901, 0xc436, 0x4901, 0xc436, 0x21, 0 - .dw 0x4903, 0xc436, 0x490f, 0xc436, 0x21, 0 - .dw 0x4911, 0xc436, 0x4911, 0xc436, 0x21, 0 - .dw 0x4913, 0xc436, 0x493f, 0xc436, 0x21, 0 - .dw 0x4941, 0xc436, 0x4941, 0xc436, 0x21, 0 - .dw 0x4943, 0xc436, 0x494f, 0xc436, 0x21, 0 - .dw 0x4951, 0xc436, 0x4951, 0xc436, 0x21, 0 - .dw 0x4953, 0xc436, 0x497f, 0xc436, 0x21, 0 - .dw 0x4981, 0xc436, 0x4981, 0xc436, 0x21, 0 - .dw 0x4983, 0xc436, 0x498f, 0xc436, 0x21, 0 - .dw 0x4991, 0xc436, 0x4991, 0xc436, 0x21, 0 - .dw 0x4993, 0xc436, 0x49bf, 0xc436, 0x21, 0 - .dw 0x49c1, 0xc436, 0x49c1, 0xc436, 0x21, 0 - .dw 0x49c3, 0xc436, 0x49cf, 0xc436, 0x21, 0 - .dw 0x49d1, 0xc436, 0x49d1, 0xc436, 0x21, 0 - .dw 0x49d3, 0xc436, 0x49ff, 0xc436, 0x21, 0 - .dw 0x4a01, 0xc436, 0x4a01, 0xc436, 0x21, 0 - .dw 0x4a03, 0xc436, 0x4a0f, 0xc436, 0x21, 0 - .dw 0x4a11, 0xc436, 0x4a11, 0xc436, 0x21, 0 - .dw 0x4a13, 0xc436, 0x4a3f, 0xc436, 0x21, 0 - .dw 0x4a41, 0xc436, 0x4a41, 0xc436, 0x21, 0 - .dw 0x4a43, 0xc436, 0x4a4f, 0xc436, 0x21, 0 - .dw 0x4a51, 0xc436, 0x4a51, 0xc436, 0x21, 0 - .dw 0x4a53, 0xc436, 0x4a7f, 0xc436, 0x21, 0 - .dw 0x4a81, 0xc436, 0x4a81, 0xc436, 0x21, 0 - .dw 0x4a83, 0xc436, 0x4a8f, 0xc436, 0x21, 0 - .dw 0x4a91, 0xc436, 0x4a91, 0xc436, 0x21, 0 - .dw 0x4a93, 0xc436, 0x4abf, 0xc436, 0x21, 0 - .dw 0x4ac1, 0xc436, 0x4ac1, 0xc436, 0x21, 0 - .dw 0x4ac3, 0xc436, 0x4acf, 0xc436, 0x21, 0 - .dw 0x4ad1, 0xc436, 0x4ad1, 0xc436, 0x21, 0 - .dw 0x4ad3, 0xc436, 0x4aff, 0xc436, 0x21, 0 - .dw 0x4b01, 0xc436, 0x4b01, 0xc436, 0x21, 0 - .dw 0x4b03, 0xc436, 0x4b0f, 0xc436, 0x21, 0 - .dw 0x4b11, 0xc436, 0x4b11, 0xc436, 0x21, 0 - .dw 0x4b13, 0xc436, 0x4b3f, 0xc436, 0x21, 0 - .dw 0x4b41, 0xc436, 0x4b41, 0xc436, 0x21, 0 - .dw 0x4b43, 0xc436, 0x4b4f, 0xc436, 0x21, 0 - .dw 0x4b51, 0xc436, 0x4b51, 0xc436, 0x21, 0 - .dw 0x4b53, 0xc436, 0x4b7f, 0xc436, 0x21, 0 - .dw 0x4b81, 0xc436, 0x4b81, 0xc436, 0x21, 0 - .dw 0x4b83, 0xc436, 0x4b8f, 0xc436, 0x21, 0 - .dw 0x4b91, 0xc436, 0x4b91, 0xc436, 0x21, 0 - .dw 0x4b93, 0xc436, 0x4bbf, 0xc436, 0x21, 0 - .dw 0x4bc1, 0xc436, 0x4bc1, 0xc436, 0x21, 0 - .dw 0x4bc3, 0xc436, 0x4bcf, 0xc436, 0x21, 0 - .dw 0x4bd1, 0xc436, 0x4bd1, 0xc436, 0x21, 0 - .dw 0x4bd3, 0xc436, 0x4bff, 0xc436, 0x21, 0 - .dw 0x4c01, 0xc436, 0x4c01, 0xc436, 0x21, 0 - .dw 0x4c03, 0xc436, 0x4c0f, 0xc436, 0x21, 0 - .dw 0x4c11, 0xc436, 0x4c11, 0xc436, 0x21, 0 - .dw 0x4c13, 0xc436, 0x4c3f, 0xc436, 0x21, 0 - .dw 0x4c41, 0xc436, 0x4c41, 0xc436, 0x21, 0 - .dw 0x4c43, 0xc436, 0x4c4f, 0xc436, 0x21, 0 - .dw 0x4c51, 0xc436, 0x4c51, 0xc436, 0x21, 0 - .dw 0x4c53, 0xc436, 0x4c7f, 0xc436, 0x21, 0 - .dw 0x4c81, 0xc436, 0x4c81, 0xc436, 0x21, 0 - .dw 0x4c83, 0xc436, 0x4c8f, 0xc436, 0x21, 0 - .dw 0x4c91, 0xc436, 0x4c91, 0xc436, 0x21, 0 - .dw 0x4c93, 0xc436, 0x4cbf, 0xc436, 0x21, 0 - .dw 0x4cc1, 0xc436, 0x4cc1, 0xc436, 0x21, 0 - .dw 0x4cc3, 0xc436, 0x4ccf, 0xc436, 0x21, 0 - .dw 0x4cd1, 0xc436, 0x4cd1, 0xc436, 0x21, 0 - .dw 0x4cd3, 0xc436, 0x4cff, 0xc436, 0x21, 0 - .dw 0x4d01, 0xc436, 0x4d01, 0xc436, 0x21, 0 - .dw 0x4d03, 0xc436, 0x4d0f, 0xc436, 0x21, 0 - .dw 0x4d11, 0xc436, 0x4d11, 0xc436, 0x21, 0 - .dw 0x4d13, 0xc436, 0x4d3f, 0xc436, 0x21, 0 - .dw 0x4d41, 0xc436, 0x4d41, 0xc436, 0x21, 0 - .dw 0x4d43, 0xc436, 0x4d4f, 0xc436, 0x21, 0 - .dw 0x4d51, 0xc436, 0x4d51, 0xc436, 0x21, 0 - .dw 0x4d53, 0xc436, 0x4d7f, 0xc436, 0x21, 0 - .dw 0x4d81, 0xc436, 0x4d81, 0xc436, 0x21, 0 - .dw 0x4d83, 0xc436, 0x4d8f, 0xc436, 0x21, 0 - .dw 0x4d91, 0xc436, 0x4d91, 0xc436, 0x21, 0 - .dw 0x4d93, 0xc436, 0x4dbf, 0xc436, 0x21, 0 - .dw 0x4dc1, 0xc436, 0x4dc1, 0xc436, 0x21, 0 - .dw 0x4dc3, 0xc436, 0x4dcf, 0xc436, 0x21, 0 - .dw 0x4dd1, 0xc436, 0x4dd1, 0xc436, 0x21, 0 - .dw 0x4dd3, 0xc436, 0x4dff, 0xc436, 0x21, 0 - .dw 0x4e01, 0xc436, 0x4e01, 0xc436, 0x21, 0 - .dw 0x4e03, 0xc436, 0x4e0f, 0xc436, 0x21, 0 - .dw 0x4e11, 0xc436, 0x4e11, 0xc436, 0x21, 0 - .dw 0x4e13, 0xc436, 0x4e3f, 0xc436, 0x21, 0 - .dw 0x4e41, 0xc436, 0x4e41, 0xc436, 0x21, 0 - .dw 0x4e43, 0xc436, 0x4e4f, 0xc436, 0x21, 0 - .dw 0x4e51, 0xc436, 0x4e51, 0xc436, 0x21, 0 - .dw 0x4e53, 0xc436, 0x4e7f, 0xc436, 0x21, 0 - .dw 0x4e81, 0xc436, 0x4e81, 0xc436, 0x21, 0 - .dw 0x4e83, 0xc436, 0x4e8f, 0xc436, 0x21, 0 - .dw 0x4e91, 0xc436, 0x4e91, 0xc436, 0x21, 0 - .dw 0x4e93, 0xc436, 0x4ebf, 0xc436, 0x21, 0 - .dw 0x4ec1, 0xc436, 0x4ec1, 0xc436, 0x21, 0 - .dw 0x4ec3, 0xc436, 0x4ecf, 0xc436, 0x21, 0 - .dw 0x4ed1, 0xc436, 0x4ed1, 0xc436, 0x21, 0 - .dw 0x4ed3, 0xc436, 0x4eff, 0xc436, 0x21, 0 - .dw 0x4f01, 0xc436, 0x4f01, 0xc436, 0x21, 0 - .dw 0x4f03, 0xc436, 0x4f0f, 0xc436, 0x21, 0 - .dw 0x4f11, 0xc436, 0x4f11, 0xc436, 0x21, 0 - .dw 0x4f13, 0xc436, 0x4f3f, 0xc436, 0x21, 0 - .dw 0x4f41, 0xc436, 0x4f41, 0xc436, 0x21, 0 - .dw 0x4f43, 0xc436, 0x4f4f, 0xc436, 0x21, 0 - .dw 0x4f51, 0xc436, 0x4f51, 0xc436, 0x21, 0 - .dw 0x4f53, 0xc436, 0x4f7f, 0xc436, 0x21, 0 - .dw 0x4f81, 0xc436, 0x4f81, 0xc436, 0x21, 0 - .dw 0x4f83, 0xc436, 0x4f8f, 0xc436, 0x21, 0 - .dw 0x4f91, 0xc436, 0x4f91, 0xc436, 0x21, 0 - .dw 0x4f93, 0xc436, 0x4fbf, 0xc436, 0x21, 0 - .dw 0x4fc1, 0xc436, 0x4fc1, 0xc436, 0x21, 0 - .dw 0x4fc3, 0xc436, 0x4fcf, 0xc436, 0x21, 0 - .dw 0x4fd1, 0xc436, 0x4fd1, 0xc436, 0x21, 0 - .dw 0x4fd3, 0xc436, 0x5fff, 0xc436, 0x21, 0 - .dw 0x6001, 0xc436, 0x6001, 0xc436, 0x21, 0 - .dw 0x6003, 0xc436, 0x600f, 0xc436, 0x21, 0 - .dw 0x6011, 0xc436, 0x6011, 0xc436, 0x21, 0 - .dw 0x6013, 0xc436, 0x603f, 0xc436, 0x21, 0 - .dw 0x6041, 0xc436, 0x6041, 0xc436, 0x21, 0 - .dw 0x6043, 0xc436, 0x604f, 0xc436, 0x21, 0 - .dw 0x6051, 0xc436, 0x6051, 0xc436, 0x21, 0 - .dw 0x6053, 0xc436, 0x607f, 0xc436, 0x21, 0 - .dw 0x6081, 0xc436, 0x6081, 0xc436, 0x21, 0 - .dw 0x6083, 0xc436, 0x608f, 0xc436, 0x21, 0 - .dw 0x6091, 0xc436, 0x6091, 0xc436, 0x21, 0 - .dw 0x6093, 0xc436, 0x60bf, 0xc436, 0x21, 0 - .dw 0x60c1, 0xc436, 0x60c1, 0xc436, 0x21, 0 - .dw 0x60c3, 0xc436, 0x60cf, 0xc436, 0x21, 0 - .dw 0x60d1, 0xc436, 0x60d1, 0xc436, 0x21, 0 - .dw 0x60d3, 0xc436, 0x60ff, 0xc436, 0x21, 0 - .dw 0x6101, 0xc436, 0x6101, 0xc436, 0x21, 0 - .dw 0x6103, 0xc436, 0x610f, 0xc436, 0x21, 0 - .dw 0x6111, 0xc436, 0x6111, 0xc436, 0x21, 0 - .dw 0x6113, 0xc436, 0x613f, 0xc436, 0x21, 0 - .dw 0x6141, 0xc436, 0x6141, 0xc436, 0x21, 0 - .dw 0x6143, 0xc436, 0x614f, 0xc436, 0x21, 0 - .dw 0x6151, 0xc436, 0x6151, 0xc436, 0x21, 0 - .dw 0x6153, 0xc436, 0x617f, 0xc436, 0x21, 0 - .dw 0x6181, 0xc436, 0x6181, 0xc436, 0x21, 0 - .dw 0x6183, 0xc436, 0x618f, 0xc436, 0x21, 0 - .dw 0x6191, 0xc436, 0x6191, 0xc436, 0x21, 0 - .dw 0x6193, 0xc436, 0x61bf, 0xc436, 0x21, 0 - .dw 0x61c1, 0xc436, 0x61c1, 0xc436, 0x21, 0 - .dw 0x61c3, 0xc436, 0x61cf, 0xc436, 0x21, 0 - .dw 0x61d1, 0xc436, 0x61d1, 0xc436, 0x21, 0 - .dw 0x61d3, 0xc436, 0x61ff, 0xc436, 0x21, 0 - .dw 0x6201, 0xc436, 0x6201, 0xc436, 0x21, 0 - .dw 0x6203, 0xc436, 0x620f, 0xc436, 0x21, 0 - .dw 0x6211, 0xc436, 0x6211, 0xc436, 0x21, 0 - .dw 0x6213, 0xc436, 0x623f, 0xc436, 0x21, 0 - .dw 0x6241, 0xc436, 0x6241, 0xc436, 0x21, 0 - .dw 0x6243, 0xc436, 0x624f, 0xc436, 0x21, 0 - .dw 0x6251, 0xc436, 0x6251, 0xc436, 0x21, 0 - .dw 0x6253, 0xc436, 0x627f, 0xc436, 0x21, 0 - .dw 0x6281, 0xc436, 0x6281, 0xc436, 0x21, 0 - .dw 0x6283, 0xc436, 0x628f, 0xc436, 0x21, 0 - .dw 0x6291, 0xc436, 0x6291, 0xc436, 0x21, 0 - .dw 0x6293, 0xc436, 0x62bf, 0xc436, 0x21, 0 - .dw 0x62c1, 0xc436, 0x62c1, 0xc436, 0x21, 0 - .dw 0x62c3, 0xc436, 0x62cf, 0xc436, 0x21, 0 - .dw 0x62d1, 0xc436, 0x62d1, 0xc436, 0x21, 0 - .dw 0x62d3, 0xc436, 0x62ff, 0xc436, 0x21, 0 - .dw 0x6301, 0xc436, 0x6301, 0xc436, 0x21, 0 - .dw 0x6303, 0xc436, 0x630f, 0xc436, 0x21, 0 - .dw 0x6311, 0xc436, 0x6311, 0xc436, 0x21, 0 - .dw 0x6313, 0xc436, 0x633f, 0xc436, 0x21, 0 - .dw 0x6341, 0xc436, 0x6341, 0xc436, 0x21, 0 - .dw 0x6343, 0xc436, 0x634f, 0xc436, 0x21, 0 - .dw 0x6351, 0xc436, 0x6351, 0xc436, 0x21, 0 - .dw 0x6353, 0xc436, 0x637f, 0xc436, 0x21, 0 - .dw 0x6381, 0xc436, 0x6381, 0xc436, 0x21, 0 - .dw 0x6383, 0xc436, 0x638f, 0xc436, 0x21, 0 - .dw 0x6391, 0xc436, 0x6391, 0xc436, 0x21, 0 - .dw 0x6393, 0xc436, 0x63bf, 0xc436, 0x21, 0 - .dw 0x63c1, 0xc436, 0x63c1, 0xc436, 0x21, 0 - .dw 0x63c3, 0xc436, 0x63cf, 0xc436, 0x21, 0 - .dw 0x63d1, 0xc436, 0x63d1, 0xc436, 0x21, 0 - .dw 0x63d3, 0xc436, 0x63ff, 0xc436, 0x21, 0 - .dw 0x6401, 0xc436, 0x6401, 0xc436, 0x21, 0 - .dw 0x6403, 0xc436, 0x640f, 0xc436, 0x21, 0 - .dw 0x6411, 0xc436, 0x6411, 0xc436, 0x21, 0 - .dw 0x6413, 0xc436, 0x643f, 0xc436, 0x21, 0 - .dw 0x6441, 0xc436, 0x6441, 0xc436, 0x21, 0 - .dw 0x6443, 0xc436, 0x644f, 0xc436, 0x21, 0 - .dw 0x6451, 0xc436, 0x6451, 0xc436, 0x21, 0 - .dw 0x6453, 0xc436, 0x647f, 0xc436, 0x21, 0 - .dw 0x6481, 0xc436, 0x6481, 0xc436, 0x21, 0 - .dw 0x6483, 0xc436, 0x648f, 0xc436, 0x21, 0 - .dw 0x6491, 0xc436, 0x6491, 0xc436, 0x21, 0 - .dw 0x6493, 0xc436, 0x64bf, 0xc436, 0x21, 0 - .dw 0x64c1, 0xc436, 0x64c1, 0xc436, 0x21, 0 - .dw 0x64c3, 0xc436, 0x64cf, 0xc436, 0x21, 0 - .dw 0x64d1, 0xc436, 0x64d1, 0xc436, 0x21, 0 - .dw 0x64d3, 0xc436, 0x64ff, 0xc436, 0x21, 0 - .dw 0x6501, 0xc436, 0x6501, 0xc436, 0x21, 0 - .dw 0x6503, 0xc436, 0x650f, 0xc436, 0x21, 0 - .dw 0x6511, 0xc436, 0x6511, 0xc436, 0x21, 0 - .dw 0x6513, 0xc436, 0x653f, 0xc436, 0x21, 0 - .dw 0x6541, 0xc436, 0x6541, 0xc436, 0x21, 0 - .dw 0x6543, 0xc436, 0x654f, 0xc436, 0x21, 0 - .dw 0x6551, 0xc436, 0x6551, 0xc436, 0x21, 0 - .dw 0x6553, 0xc436, 0x657f, 0xc436, 0x21, 0 - .dw 0x6581, 0xc436, 0x6581, 0xc436, 0x21, 0 - .dw 0x6583, 0xc436, 0x658f, 0xc436, 0x21, 0 - .dw 0x6591, 0xc436, 0x6591, 0xc436, 0x21, 0 - .dw 0x6593, 0xc436, 0x65bf, 0xc436, 0x21, 0 - .dw 0x65c1, 0xc436, 0x65c1, 0xc436, 0x21, 0 - .dw 0x65c3, 0xc436, 0x65cf, 0xc436, 0x21, 0 - .dw 0x65d1, 0xc436, 0x65d1, 0xc436, 0x21, 0 - .dw 0x65d3, 0xc436, 0x65ff, 0xc436, 0x21, 0 - .dw 0x6601, 0xc436, 0x6601, 0xc436, 0x21, 0 - .dw 0x6603, 0xc436, 0x660f, 0xc436, 0x21, 0 - .dw 0x6611, 0xc436, 0x6611, 0xc436, 0x21, 0 - .dw 0x6613, 0xc436, 0x663f, 0xc436, 0x21, 0 - .dw 0x6641, 0xc436, 0x6641, 0xc436, 0x21, 0 - .dw 0x6643, 0xc436, 0x664f, 0xc436, 0x21, 0 - .dw 0x6651, 0xc436, 0x6651, 0xc436, 0x21, 0 - .dw 0x6653, 0xc436, 0x667f, 0xc436, 0x21, 0 - .dw 0x6681, 0xc436, 0x6681, 0xc436, 0x21, 0 - .dw 0x6683, 0xc436, 0x668f, 0xc436, 0x21, 0 - .dw 0x6691, 0xc436, 0x6691, 0xc436, 0x21, 0 - .dw 0x6693, 0xc436, 0x66bf, 0xc436, 0x21, 0 - .dw 0x66c1, 0xc436, 0x66c1, 0xc436, 0x21, 0 - .dw 0x66c3, 0xc436, 0x66cf, 0xc436, 0x21, 0 - .dw 0x66d1, 0xc436, 0x66d1, 0xc436, 0x21, 0 - .dw 0x66d3, 0xc436, 0x66ff, 0xc436, 0x21, 0 - .dw 0x6701, 0xc436, 0x6701, 0xc436, 0x21, 0 - .dw 0x6703, 0xc436, 0x670f, 0xc436, 0x21, 0 - .dw 0x6711, 0xc436, 0x6711, 0xc436, 0x21, 0 - .dw 0x6713, 0xc436, 0x673f, 0xc436, 0x21, 0 - .dw 0x6741, 0xc436, 0x6741, 0xc436, 0x21, 0 - .dw 0x6743, 0xc436, 0x674f, 0xc436, 0x21, 0 - .dw 0x6751, 0xc436, 0x6751, 0xc436, 0x21, 0 - .dw 0x6753, 0xc436, 0x677f, 0xc436, 0x21, 0 - .dw 0x6781, 0xc436, 0x6781, 0xc436, 0x21, 0 - .dw 0x6783, 0xc436, 0x678f, 0xc436, 0x21, 0 - .dw 0x6791, 0xc436, 0x6791, 0xc436, 0x21, 0 - .dw 0x6793, 0xc436, 0x67bf, 0xc436, 0x21, 0 - .dw 0x67c1, 0xc436, 0x67c1, 0xc436, 0x21, 0 - .dw 0x67c3, 0xc436, 0x67cf, 0xc436, 0x21, 0 - .dw 0x67d1, 0xc436, 0x67d1, 0xc436, 0x21, 0 - .dw 0x67d3, 0xc436, 0x67ff, 0xc436, 0x21, 0 - .dw 0x6801, 0xc436, 0x6801, 0xc436, 0x21, 0 - .dw 0x6803, 0xc436, 0x680f, 0xc436, 0x21, 0 - .dw 0x6811, 0xc436, 0x6811, 0xc436, 0x21, 0 - .dw 0x6813, 0xc436, 0x683f, 0xc436, 0x21, 0 - .dw 0x6841, 0xc436, 0x6841, 0xc436, 0x21, 0 - .dw 0x6843, 0xc436, 0x684f, 0xc436, 0x21, 0 - .dw 0x6851, 0xc436, 0x6851, 0xc436, 0x21, 0 - .dw 0x6853, 0xc436, 0x687f, 0xc436, 0x21, 0 - .dw 0x6881, 0xc436, 0x6881, 0xc436, 0x21, 0 - .dw 0x6883, 0xc436, 0x688f, 0xc436, 0x21, 0 - .dw 0x6891, 0xc436, 0x6891, 0xc436, 0x21, 0 - .dw 0x6893, 0xc436, 0x68bf, 0xc436, 0x21, 0 - .dw 0x68c1, 0xc436, 0x68c1, 0xc436, 0x21, 0 - .dw 0x68c3, 0xc436, 0x68cf, 0xc436, 0x21, 0 - .dw 0x68d1, 0xc436, 0x68d1, 0xc436, 0x21, 0 - .dw 0x68d3, 0xc436, 0x68ff, 0xc436, 0x21, 0 - .dw 0x6901, 0xc436, 0x6901, 0xc436, 0x21, 0 - .dw 0x6903, 0xc436, 0x690f, 0xc436, 0x21, 0 - .dw 0x6911, 0xc436, 0x6911, 0xc436, 0x21, 0 - .dw 0x6913, 0xc436, 0x693f, 0xc436, 0x21, 0 - .dw 0x6941, 0xc436, 0x6941, 0xc436, 0x21, 0 - .dw 0x6943, 0xc436, 0x694f, 0xc436, 0x21, 0 - .dw 0x6951, 0xc436, 0x6951, 0xc436, 0x21, 0 - .dw 0x6953, 0xc436, 0x697f, 0xc436, 0x21, 0 - .dw 0x6981, 0xc436, 0x6981, 0xc436, 0x21, 0 - .dw 0x6983, 0xc436, 0x698f, 0xc436, 0x21, 0 - .dw 0x6991, 0xc436, 0x6991, 0xc436, 0x21, 0 - .dw 0x6993, 0xc436, 0x69bf, 0xc436, 0x21, 0 - .dw 0x69c1, 0xc436, 0x69c1, 0xc436, 0x21, 0 - .dw 0x69c3, 0xc436, 0x69cf, 0xc436, 0x21, 0 - .dw 0x69d1, 0xc436, 0x69d1, 0xc436, 0x21, 0 - .dw 0x69d3, 0xc436, 0x69ff, 0xc436, 0x21, 0 - .dw 0x6a01, 0xc436, 0x6a01, 0xc436, 0x21, 0 - .dw 0x6a03, 0xc436, 0x6a0f, 0xc436, 0x21, 0 - .dw 0x6a11, 0xc436, 0x6a11, 0xc436, 0x21, 0 - .dw 0x6a13, 0xc436, 0x6a3f, 0xc436, 0x21, 0 - .dw 0x6a41, 0xc436, 0x6a41, 0xc436, 0x21, 0 - .dw 0x6a43, 0xc436, 0x6a4f, 0xc436, 0x21, 0 - .dw 0x6a51, 0xc436, 0x6a51, 0xc436, 0x21, 0 - .dw 0x6a53, 0xc436, 0x6a7f, 0xc436, 0x21, 0 - .dw 0x6a81, 0xc436, 0x6a81, 0xc436, 0x21, 0 - .dw 0x6a83, 0xc436, 0x6a8f, 0xc436, 0x21, 0 - .dw 0x6a91, 0xc436, 0x6a91, 0xc436, 0x21, 0 - .dw 0x6a93, 0xc436, 0x6abf, 0xc436, 0x21, 0 - .dw 0x6ac1, 0xc436, 0x6ac1, 0xc436, 0x21, 0 - .dw 0x6ac3, 0xc436, 0x6acf, 0xc436, 0x21, 0 - .dw 0x6ad1, 0xc436, 0x6ad1, 0xc436, 0x21, 0 - .dw 0x6ad3, 0xc436, 0x6aff, 0xc436, 0x21, 0 - .dw 0x6b01, 0xc436, 0x6b01, 0xc436, 0x21, 0 - .dw 0x6b03, 0xc436, 0x6b0f, 0xc436, 0x21, 0 - .dw 0x6b11, 0xc436, 0x6b11, 0xc436, 0x21, 0 - .dw 0x6b13, 0xc436, 0x6b3f, 0xc436, 0x21, 0 - .dw 0x6b41, 0xc436, 0x6b41, 0xc436, 0x21, 0 - .dw 0x6b43, 0xc436, 0x6b4f, 0xc436, 0x21, 0 - .dw 0x6b51, 0xc436, 0x6b51, 0xc436, 0x21, 0 - .dw 0x6b53, 0xc436, 0x6b7f, 0xc436, 0x21, 0 - .dw 0x6b81, 0xc436, 0x6b81, 0xc436, 0x21, 0 - .dw 0x6b83, 0xc436, 0x6b8f, 0xc436, 0x21, 0 - .dw 0x6b91, 0xc436, 0x6b91, 0xc436, 0x21, 0 - .dw 0x6b93, 0xc436, 0x6bbf, 0xc436, 0x21, 0 - .dw 0x6bc1, 0xc436, 0x6bc1, 0xc436, 0x21, 0 - .dw 0x6bc3, 0xc436, 0x6bcf, 0xc436, 0x21, 0 - .dw 0x6bd1, 0xc436, 0x6bd1, 0xc436, 0x21, 0 - .dw 0x6bd3, 0xc436, 0x6bff, 0xc436, 0x21, 0 - .dw 0x6c01, 0xc436, 0x6c01, 0xc436, 0x21, 0 - .dw 0x6c03, 0xc436, 0x6c0f, 0xc436, 0x21, 0 - .dw 0x6c11, 0xc436, 0x6c11, 0xc436, 0x21, 0 - .dw 0x6c13, 0xc436, 0x6c3f, 0xc436, 0x21, 0 - .dw 0x6c41, 0xc436, 0x6c41, 0xc436, 0x21, 0 - .dw 0x6c43, 0xc436, 0x6c4f, 0xc436, 0x21, 0 - .dw 0x6c51, 0xc436, 0x6c51, 0xc436, 0x21, 0 - .dw 0x6c53, 0xc436, 0x6c7f, 0xc436, 0x21, 0 - .dw 0x6c81, 0xc436, 0x6c81, 0xc436, 0x21, 0 - .dw 0x6c83, 0xc436, 0x6c8f, 0xc436, 0x21, 0 - .dw 0x6c91, 0xc436, 0x6c91, 0xc436, 0x21, 0 - .dw 0x6c93, 0xc436, 0x6cbf, 0xc436, 0x21, 0 - .dw 0x6cc1, 0xc436, 0x6cc1, 0xc436, 0x21, 0 - .dw 0x6cc3, 0xc436, 0x6ccf, 0xc436, 0x21, 0 - .dw 0x6cd1, 0xc436, 0x6cd1, 0xc436, 0x21, 0 - .dw 0x6cd3, 0xc436, 0x6cff, 0xc436, 0x21, 0 - .dw 0x6d01, 0xc436, 0x6d01, 0xc436, 0x21, 0 - .dw 0x6d03, 0xc436, 0x6d0f, 0xc436, 0x21, 0 - .dw 0x6d11, 0xc436, 0x6d11, 0xc436, 0x21, 0 - .dw 0x6d13, 0xc436, 0x6d3f, 0xc436, 0x21, 0 - .dw 0x6d41, 0xc436, 0x6d41, 0xc436, 0x21, 0 - .dw 0x6d43, 0xc436, 0x6d4f, 0xc436, 0x21, 0 - .dw 0x6d51, 0xc436, 0x6d51, 0xc436, 0x21, 0 - .dw 0x6d53, 0xc436, 0x6d7f, 0xc436, 0x21, 0 - .dw 0x6d81, 0xc436, 0x6d81, 0xc436, 0x21, 0 - .dw 0x6d83, 0xc436, 0x6d8f, 0xc436, 0x21, 0 - .dw 0x6d91, 0xc436, 0x6d91, 0xc436, 0x21, 0 - .dw 0x6d93, 0xc436, 0x6dbf, 0xc436, 0x21, 0 - .dw 0x6dc1, 0xc436, 0x6dc1, 0xc436, 0x21, 0 - .dw 0x6dc3, 0xc436, 0x6dcf, 0xc436, 0x21, 0 - .dw 0x6dd1, 0xc436, 0x6dd1, 0xc436, 0x21, 0 - .dw 0x6dd3, 0xc436, 0x6dff, 0xc436, 0x21, 0 - .dw 0x6e01, 0xc436, 0x6e01, 0xc436, 0x21, 0 - .dw 0x6e03, 0xc436, 0x6e0f, 0xc436, 0x21, 0 - .dw 0x6e11, 0xc436, 0x6e11, 0xc436, 0x21, 0 - .dw 0x6e13, 0xc436, 0x6e3f, 0xc436, 0x21, 0 - .dw 0x6e41, 0xc436, 0x6e41, 0xc436, 0x21, 0 - .dw 0x6e43, 0xc436, 0x6e4f, 0xc436, 0x21, 0 - .dw 0x6e51, 0xc436, 0x6e51, 0xc436, 0x21, 0 - .dw 0x6e53, 0xc436, 0x6e7f, 0xc436, 0x21, 0 - .dw 0x6e81, 0xc436, 0x6e81, 0xc436, 0x21, 0 - .dw 0x6e83, 0xc436, 0x6e8f, 0xc436, 0x21, 0 - .dw 0x6e91, 0xc436, 0x6e91, 0xc436, 0x21, 0 - .dw 0x6e93, 0xc436, 0x6ebf, 0xc436, 0x21, 0 - .dw 0x6ec1, 0xc436, 0x6ec1, 0xc436, 0x21, 0 - .dw 0x6ec3, 0xc436, 0x6ecf, 0xc436, 0x21, 0 - .dw 0x6ed1, 0xc436, 0x6ed1, 0xc436, 0x21, 0 - .dw 0x6ed3, 0xc436, 0x6eff, 0xc436, 0x21, 0 - .dw 0x6f01, 0xc436, 0x6f01, 0xc436, 0x21, 0 - .dw 0x6f03, 0xc436, 0x6f0f, 0xc436, 0x21, 0 - .dw 0x6f11, 0xc436, 0x6f11, 0xc436, 0x21, 0 - .dw 0x6f13, 0xc436, 0x6f3f, 0xc436, 0x21, 0 - .dw 0x6f41, 0xc436, 0x6f41, 0xc436, 0x21, 0 - .dw 0x6f43, 0xc436, 0x6f4f, 0xc436, 0x21, 0 - .dw 0x6f51, 0xc436, 0x6f51, 0xc436, 0x21, 0 - .dw 0x6f53, 0xc436, 0x6f7f, 0xc436, 0x21, 0 - .dw 0x6f81, 0xc436, 0x6f81, 0xc436, 0x21, 0 - .dw 0x6f83, 0xc436, 0x6f8f, 0xc436, 0x21, 0 - .dw 0x6f91, 0xc436, 0x6f91, 0xc436, 0x21, 0 - .dw 0x6f93, 0xc436, 0x6fbf, 0xc436, 0x21, 0 - .dw 0x6fc1, 0xc436, 0x6fc1, 0xc436, 0x21, 0 - .dw 0x6fc3, 0xc436, 0x6fcf, 0xc436, 0x21, 0 - .dw 0x6fd1, 0xc436, 0x6fd1, 0xc436, 0x21, 0 - .dw 0x6fd3, 0xc436, 0xffff, 0xc436, 0x21, 0 - .dw 0x0001, 0xc437, 0x0001, 0xc437, 0x21, 0 - .dw 0x0003, 0xc437, 0x000f, 0xc437, 0x21, 0 - .dw 0x0011, 0xc437, 0x0011, 0xc437, 0x21, 0 - .dw 0x0013, 0xc437, 0x003f, 0xc437, 0x21, 0 - .dw 0x0041, 0xc437, 0x0041, 0xc437, 0x21, 0 - .dw 0x0043, 0xc437, 0x004f, 0xc437, 0x21, 0 - .dw 0x0051, 0xc437, 0x0051, 0xc437, 0x21, 0 - .dw 0x0053, 0xc437, 0x007f, 0xc437, 0x21, 0 - .dw 0x0081, 0xc437, 0x0081, 0xc437, 0x21, 0 - .dw 0x0083, 0xc437, 0x008f, 0xc437, 0x21, 0 - .dw 0x0091, 0xc437, 0x0091, 0xc437, 0x21, 0 - .dw 0x0093, 0xc437, 0x00bf, 0xc437, 0x21, 0 - .dw 0x00c1, 0xc437, 0x00c1, 0xc437, 0x21, 0 - .dw 0x00c3, 0xc437, 0x00cf, 0xc437, 0x21, 0 - .dw 0x00d1, 0xc437, 0x00d1, 0xc437, 0x21, 0 - .dw 0x00d3, 0xc437, 0x00ff, 0xc437, 0x21, 0 - .dw 0x0101, 0xc437, 0x0101, 0xc437, 0x21, 0 - .dw 0x0103, 0xc437, 0x010f, 0xc437, 0x21, 0 - .dw 0x0111, 0xc437, 0x0111, 0xc437, 0x21, 0 - .dw 0x0113, 0xc437, 0x013f, 0xc437, 0x21, 0 - .dw 0x0141, 0xc437, 0x0141, 0xc437, 0x21, 0 - .dw 0x0143, 0xc437, 0x014f, 0xc437, 0x21, 0 - .dw 0x0151, 0xc437, 0x0151, 0xc437, 0x21, 0 - .dw 0x0153, 0xc437, 0x017f, 0xc437, 0x21, 0 - .dw 0x0181, 0xc437, 0x0181, 0xc437, 0x21, 0 - .dw 0x0183, 0xc437, 0x018f, 0xc437, 0x21, 0 - .dw 0x0191, 0xc437, 0x0191, 0xc437, 0x21, 0 - .dw 0x0193, 0xc437, 0x01bf, 0xc437, 0x21, 0 - .dw 0x01c1, 0xc437, 0x01c1, 0xc437, 0x21, 0 - .dw 0x01c3, 0xc437, 0x01cf, 0xc437, 0x21, 0 - .dw 0x01d1, 0xc437, 0x01d1, 0xc437, 0x21, 0 - .dw 0x01d3, 0xc437, 0x01ff, 0xc437, 0x21, 0 - .dw 0x0201, 0xc437, 0x0201, 0xc437, 0x21, 0 - .dw 0x0203, 0xc437, 0x020f, 0xc437, 0x21, 0 - .dw 0x0211, 0xc437, 0x0211, 0xc437, 0x21, 0 - .dw 0x0213, 0xc437, 0x023f, 0xc437, 0x21, 0 - .dw 0x0241, 0xc437, 0x0241, 0xc437, 0x21, 0 - .dw 0x0243, 0xc437, 0x024f, 0xc437, 0x21, 0 - .dw 0x0251, 0xc437, 0x0251, 0xc437, 0x21, 0 - .dw 0x0253, 0xc437, 0x027f, 0xc437, 0x21, 0 - .dw 0x0281, 0xc437, 0x0281, 0xc437, 0x21, 0 - .dw 0x0283, 0xc437, 0x028f, 0xc437, 0x21, 0 - .dw 0x0291, 0xc437, 0x0291, 0xc437, 0x21, 0 - .dw 0x0293, 0xc437, 0x02bf, 0xc437, 0x21, 0 - .dw 0x02c1, 0xc437, 0x02c1, 0xc437, 0x21, 0 - .dw 0x02c3, 0xc437, 0x02cf, 0xc437, 0x21, 0 - .dw 0x02d1, 0xc437, 0x02d1, 0xc437, 0x21, 0 - .dw 0x02d3, 0xc437, 0x02ff, 0xc437, 0x21, 0 - .dw 0x0301, 0xc437, 0x0301, 0xc437, 0x21, 0 - .dw 0x0303, 0xc437, 0x030f, 0xc437, 0x21, 0 - .dw 0x0311, 0xc437, 0x0311, 0xc437, 0x21, 0 - .dw 0x0313, 0xc437, 0x033f, 0xc437, 0x21, 0 - .dw 0x0341, 0xc437, 0x0341, 0xc437, 0x21, 0 - .dw 0x0343, 0xc437, 0x034f, 0xc437, 0x21, 0 - .dw 0x0351, 0xc437, 0x0351, 0xc437, 0x21, 0 - .dw 0x0353, 0xc437, 0x037f, 0xc437, 0x21, 0 - .dw 0x0381, 0xc437, 0x0381, 0xc437, 0x21, 0 - .dw 0x0383, 0xc437, 0x038f, 0xc437, 0x21, 0 - .dw 0x0391, 0xc437, 0x0391, 0xc437, 0x21, 0 - .dw 0x0393, 0xc437, 0x03bf, 0xc437, 0x21, 0 - .dw 0x03c1, 0xc437, 0x03c1, 0xc437, 0x21, 0 - .dw 0x03c3, 0xc437, 0x03cf, 0xc437, 0x21, 0 - .dw 0x03d1, 0xc437, 0x03d1, 0xc437, 0x21, 0 - .dw 0x03d3, 0xc437, 0x03ff, 0xc437, 0x21, 0 - .dw 0x0401, 0xc437, 0x0401, 0xc437, 0x21, 0 - .dw 0x0403, 0xc437, 0x040f, 0xc437, 0x21, 0 - .dw 0x0411, 0xc437, 0x0411, 0xc437, 0x21, 0 - .dw 0x0413, 0xc437, 0x043f, 0xc437, 0x21, 0 - .dw 0x0441, 0xc437, 0x0441, 0xc437, 0x21, 0 - .dw 0x0443, 0xc437, 0x044f, 0xc437, 0x21, 0 - .dw 0x0451, 0xc437, 0x0451, 0xc437, 0x21, 0 - .dw 0x0453, 0xc437, 0x047f, 0xc437, 0x21, 0 - .dw 0x0481, 0xc437, 0x0481, 0xc437, 0x21, 0 - .dw 0x0483, 0xc437, 0x048f, 0xc437, 0x21, 0 - .dw 0x0491, 0xc437, 0x0491, 0xc437, 0x21, 0 - .dw 0x0493, 0xc437, 0x04bf, 0xc437, 0x21, 0 - .dw 0x04c1, 0xc437, 0x04c1, 0xc437, 0x21, 0 - .dw 0x04c3, 0xc437, 0x04cf, 0xc437, 0x21, 0 - .dw 0x04d1, 0xc437, 0x04d1, 0xc437, 0x21, 0 - .dw 0x04d3, 0xc437, 0x04ff, 0xc437, 0x21, 0 - .dw 0x0501, 0xc437, 0x0501, 0xc437, 0x21, 0 - .dw 0x0503, 0xc437, 0x050f, 0xc437, 0x21, 0 - .dw 0x0511, 0xc437, 0x0511, 0xc437, 0x21, 0 - .dw 0x0513, 0xc437, 0x053f, 0xc437, 0x21, 0 - .dw 0x0541, 0xc437, 0x0541, 0xc437, 0x21, 0 - .dw 0x0543, 0xc437, 0x054f, 0xc437, 0x21, 0 - .dw 0x0551, 0xc437, 0x0551, 0xc437, 0x21, 0 - .dw 0x0553, 0xc437, 0x057f, 0xc437, 0x21, 0 - .dw 0x0581, 0xc437, 0x0581, 0xc437, 0x21, 0 - .dw 0x0583, 0xc437, 0x058f, 0xc437, 0x21, 0 - .dw 0x0591, 0xc437, 0x0591, 0xc437, 0x21, 0 - .dw 0x0593, 0xc437, 0x05bf, 0xc437, 0x21, 0 - .dw 0x05c1, 0xc437, 0x05c1, 0xc437, 0x21, 0 - .dw 0x05c3, 0xc437, 0x05cf, 0xc437, 0x21, 0 - .dw 0x05d1, 0xc437, 0x05d1, 0xc437, 0x21, 0 - .dw 0x05d3, 0xc437, 0x05ff, 0xc437, 0x21, 0 - .dw 0x0601, 0xc437, 0x0601, 0xc437, 0x21, 0 - .dw 0x0603, 0xc437, 0x060f, 0xc437, 0x21, 0 - .dw 0x0611, 0xc437, 0x0611, 0xc437, 0x21, 0 - .dw 0x0613, 0xc437, 0x063f, 0xc437, 0x21, 0 - .dw 0x0641, 0xc437, 0x0641, 0xc437, 0x21, 0 - .dw 0x0643, 0xc437, 0x064f, 0xc437, 0x21, 0 - .dw 0x0651, 0xc437, 0x0651, 0xc437, 0x21, 0 - .dw 0x0653, 0xc437, 0x067f, 0xc437, 0x21, 0 - .dw 0x0681, 0xc437, 0x0681, 0xc437, 0x21, 0 - .dw 0x0683, 0xc437, 0x068f, 0xc437, 0x21, 0 - .dw 0x0691, 0xc437, 0x0691, 0xc437, 0x21, 0 - .dw 0x0693, 0xc437, 0x06bf, 0xc437, 0x21, 0 - .dw 0x06c1, 0xc437, 0x06c1, 0xc437, 0x21, 0 - .dw 0x06c3, 0xc437, 0x06cf, 0xc437, 0x21, 0 - .dw 0x06d1, 0xc437, 0x06d1, 0xc437, 0x21, 0 - .dw 0x06d3, 0xc437, 0x06ff, 0xc437, 0x21, 0 - .dw 0x0701, 0xc437, 0x0701, 0xc437, 0x21, 0 - .dw 0x0703, 0xc437, 0x070f, 0xc437, 0x21, 0 - .dw 0x0711, 0xc437, 0x0711, 0xc437, 0x21, 0 - .dw 0x0713, 0xc437, 0x073f, 0xc437, 0x21, 0 - .dw 0x0741, 0xc437, 0x0741, 0xc437, 0x21, 0 - .dw 0x0743, 0xc437, 0x074f, 0xc437, 0x21, 0 - .dw 0x0751, 0xc437, 0x0751, 0xc437, 0x21, 0 - .dw 0x0753, 0xc437, 0x077f, 0xc437, 0x21, 0 - .dw 0x0781, 0xc437, 0x0781, 0xc437, 0x21, 0 - .dw 0x0783, 0xc437, 0x078f, 0xc437, 0x21, 0 - .dw 0x0791, 0xc437, 0x0791, 0xc437, 0x21, 0 - .dw 0x0793, 0xc437, 0x07bf, 0xc437, 0x21, 0 - .dw 0x07c1, 0xc437, 0x07c1, 0xc437, 0x21, 0 - .dw 0x07c3, 0xc437, 0x07cf, 0xc437, 0x21, 0 - .dw 0x07d1, 0xc437, 0x07d1, 0xc437, 0x21, 0 - .dw 0x07d3, 0xc437, 0x07ff, 0xc437, 0x21, 0 - .dw 0x0801, 0xc437, 0x0801, 0xc437, 0x21, 0 - .dw 0x0803, 0xc437, 0x080f, 0xc437, 0x21, 0 - .dw 0x0811, 0xc437, 0x0811, 0xc437, 0x21, 0 - .dw 0x0813, 0xc437, 0x083f, 0xc437, 0x21, 0 - .dw 0x0841, 0xc437, 0x0841, 0xc437, 0x21, 0 - .dw 0x0843, 0xc437, 0x084f, 0xc437, 0x21, 0 - .dw 0x0851, 0xc437, 0x0851, 0xc437, 0x21, 0 - .dw 0x0853, 0xc437, 0x087f, 0xc437, 0x21, 0 - .dw 0x0881, 0xc437, 0x0881, 0xc437, 0x21, 0 - .dw 0x0883, 0xc437, 0x088f, 0xc437, 0x21, 0 - .dw 0x0891, 0xc437, 0x0891, 0xc437, 0x21, 0 - .dw 0x0893, 0xc437, 0x08bf, 0xc437, 0x21, 0 - .dw 0x08c1, 0xc437, 0x08c1, 0xc437, 0x21, 0 - .dw 0x08c3, 0xc437, 0x08cf, 0xc437, 0x21, 0 - .dw 0x08d1, 0xc437, 0x08d1, 0xc437, 0x21, 0 - .dw 0x08d3, 0xc437, 0x08ff, 0xc437, 0x21, 0 - .dw 0x0901, 0xc437, 0x0901, 0xc437, 0x21, 0 - .dw 0x0903, 0xc437, 0x090f, 0xc437, 0x21, 0 - .dw 0x0911, 0xc437, 0x0911, 0xc437, 0x21, 0 - .dw 0x0913, 0xc437, 0x093f, 0xc437, 0x21, 0 - .dw 0x0941, 0xc437, 0x0941, 0xc437, 0x21, 0 - .dw 0x0943, 0xc437, 0x094f, 0xc437, 0x21, 0 - .dw 0x0951, 0xc437, 0x0951, 0xc437, 0x21, 0 - .dw 0x0953, 0xc437, 0x097f, 0xc437, 0x21, 0 - .dw 0x0981, 0xc437, 0x0981, 0xc437, 0x21, 0 - .dw 0x0983, 0xc437, 0x098f, 0xc437, 0x21, 0 - .dw 0x0991, 0xc437, 0x0991, 0xc437, 0x21, 0 - .dw 0x0993, 0xc437, 0x09bf, 0xc437, 0x21, 0 - .dw 0x09c1, 0xc437, 0x09c1, 0xc437, 0x21, 0 - .dw 0x09c3, 0xc437, 0x09cf, 0xc437, 0x21, 0 - .dw 0x09d1, 0xc437, 0x09d1, 0xc437, 0x21, 0 - .dw 0x09d3, 0xc437, 0x09ff, 0xc437, 0x21, 0 - .dw 0x0a01, 0xc437, 0x0a01, 0xc437, 0x21, 0 - .dw 0x0a03, 0xc437, 0x0a0f, 0xc437, 0x21, 0 - .dw 0x0a11, 0xc437, 0x0a11, 0xc437, 0x21, 0 - .dw 0x0a13, 0xc437, 0x0a3f, 0xc437, 0x21, 0 - .dw 0x0a41, 0xc437, 0x0a41, 0xc437, 0x21, 0 - .dw 0x0a43, 0xc437, 0x0a4f, 0xc437, 0x21, 0 - .dw 0x0a51, 0xc437, 0x0a51, 0xc437, 0x21, 0 - .dw 0x0a53, 0xc437, 0x0a7f, 0xc437, 0x21, 0 - .dw 0x0a81, 0xc437, 0x0a81, 0xc437, 0x21, 0 - .dw 0x0a83, 0xc437, 0x0a8f, 0xc437, 0x21, 0 - .dw 0x0a91, 0xc437, 0x0a91, 0xc437, 0x21, 0 - .dw 0x0a93, 0xc437, 0x0abf, 0xc437, 0x21, 0 - .dw 0x0ac1, 0xc437, 0x0ac1, 0xc437, 0x21, 0 - .dw 0x0ac3, 0xc437, 0x0acf, 0xc437, 0x21, 0 - .dw 0x0ad1, 0xc437, 0x0ad1, 0xc437, 0x21, 0 - .dw 0x0ad3, 0xc437, 0x0aff, 0xc437, 0x21, 0 - .dw 0x0b01, 0xc437, 0x0b01, 0xc437, 0x21, 0 - .dw 0x0b03, 0xc437, 0x0b0f, 0xc437, 0x21, 0 - .dw 0x0b11, 0xc437, 0x0b11, 0xc437, 0x21, 0 - .dw 0x0b13, 0xc437, 0x0b3f, 0xc437, 0x21, 0 - .dw 0x0b41, 0xc437, 0x0b41, 0xc437, 0x21, 0 - .dw 0x0b43, 0xc437, 0x0b4f, 0xc437, 0x21, 0 - .dw 0x0b51, 0xc437, 0x0b51, 0xc437, 0x21, 0 - .dw 0x0b53, 0xc437, 0x0b7f, 0xc437, 0x21, 0 - .dw 0x0b81, 0xc437, 0x0b81, 0xc437, 0x21, 0 - .dw 0x0b83, 0xc437, 0x0b8f, 0xc437, 0x21, 0 - .dw 0x0b91, 0xc437, 0x0b91, 0xc437, 0x21, 0 - .dw 0x0b93, 0xc437, 0x0bbf, 0xc437, 0x21, 0 - .dw 0x0bc1, 0xc437, 0x0bc1, 0xc437, 0x21, 0 - .dw 0x0bc3, 0xc437, 0x0bcf, 0xc437, 0x21, 0 - .dw 0x0bd1, 0xc437, 0x0bd1, 0xc437, 0x21, 0 - .dw 0x0bd3, 0xc437, 0x0bff, 0xc437, 0x21, 0 - .dw 0x0c01, 0xc437, 0x0c01, 0xc437, 0x21, 0 - .dw 0x0c03, 0xc437, 0x0c0f, 0xc437, 0x21, 0 - .dw 0x0c11, 0xc437, 0x0c11, 0xc437, 0x21, 0 - .dw 0x0c13, 0xc437, 0x0c3f, 0xc437, 0x21, 0 - .dw 0x0c41, 0xc437, 0x0c41, 0xc437, 0x21, 0 - .dw 0x0c43, 0xc437, 0x0c4f, 0xc437, 0x21, 0 - .dw 0x0c51, 0xc437, 0x0c51, 0xc437, 0x21, 0 - .dw 0x0c53, 0xc437, 0x0c7f, 0xc437, 0x21, 0 - .dw 0x0c81, 0xc437, 0x0c81, 0xc437, 0x21, 0 - .dw 0x0c83, 0xc437, 0x0c8f, 0xc437, 0x21, 0 - .dw 0x0c91, 0xc437, 0x0c91, 0xc437, 0x21, 0 - .dw 0x0c93, 0xc437, 0x0cbf, 0xc437, 0x21, 0 - .dw 0x0cc1, 0xc437, 0x0cc1, 0xc437, 0x21, 0 - .dw 0x0cc3, 0xc437, 0x0ccf, 0xc437, 0x21, 0 - .dw 0x0cd1, 0xc437, 0x0cd1, 0xc437, 0x21, 0 - .dw 0x0cd3, 0xc437, 0x0cff, 0xc437, 0x21, 0 - .dw 0x0d01, 0xc437, 0x0d01, 0xc437, 0x21, 0 - .dw 0x0d03, 0xc437, 0x0d0f, 0xc437, 0x21, 0 - .dw 0x0d11, 0xc437, 0x0d11, 0xc437, 0x21, 0 - .dw 0x0d13, 0xc437, 0x0d3f, 0xc437, 0x21, 0 - .dw 0x0d41, 0xc437, 0x0d41, 0xc437, 0x21, 0 - .dw 0x0d43, 0xc437, 0x0d4f, 0xc437, 0x21, 0 - .dw 0x0d51, 0xc437, 0x0d51, 0xc437, 0x21, 0 - .dw 0x0d53, 0xc437, 0x0d7f, 0xc437, 0x21, 0 - .dw 0x0d81, 0xc437, 0x0d81, 0xc437, 0x21, 0 - .dw 0x0d83, 0xc437, 0x0d8f, 0xc437, 0x21, 0 - .dw 0x0d91, 0xc437, 0x0d91, 0xc437, 0x21, 0 - .dw 0x0d93, 0xc437, 0x0dbf, 0xc437, 0x21, 0 - .dw 0x0dc1, 0xc437, 0x0dc1, 0xc437, 0x21, 0 - .dw 0x0dc3, 0xc437, 0x0dcf, 0xc437, 0x21, 0 - .dw 0x0dd1, 0xc437, 0x0dd1, 0xc437, 0x21, 0 - .dw 0x0dd3, 0xc437, 0x0dff, 0xc437, 0x21, 0 - .dw 0x0e01, 0xc437, 0x0e01, 0xc437, 0x21, 0 - .dw 0x0e03, 0xc437, 0x0e0f, 0xc437, 0x21, 0 - .dw 0x0e11, 0xc437, 0x0e11, 0xc437, 0x21, 0 - .dw 0x0e13, 0xc437, 0x0e3f, 0xc437, 0x21, 0 - .dw 0x0e41, 0xc437, 0x0e41, 0xc437, 0x21, 0 - .dw 0x0e43, 0xc437, 0x0e4f, 0xc437, 0x21, 0 - .dw 0x0e51, 0xc437, 0x0e51, 0xc437, 0x21, 0 - .dw 0x0e53, 0xc437, 0x0e7f, 0xc437, 0x21, 0 - .dw 0x0e81, 0xc437, 0x0e81, 0xc437, 0x21, 0 - .dw 0x0e83, 0xc437, 0x0e8f, 0xc437, 0x21, 0 - .dw 0x0e91, 0xc437, 0x0e91, 0xc437, 0x21, 0 - .dw 0x0e93, 0xc437, 0x0ebf, 0xc437, 0x21, 0 - .dw 0x0ec1, 0xc437, 0x0ec1, 0xc437, 0x21, 0 - .dw 0x0ec3, 0xc437, 0x0ecf, 0xc437, 0x21, 0 - .dw 0x0ed1, 0xc437, 0x0ed1, 0xc437, 0x21, 0 - .dw 0x0ed3, 0xc437, 0x0eff, 0xc437, 0x21, 0 - .dw 0x0f01, 0xc437, 0x0f01, 0xc437, 0x21, 0 - .dw 0x0f03, 0xc437, 0x0f0f, 0xc437, 0x21, 0 - .dw 0x0f11, 0xc437, 0x0f11, 0xc437, 0x21, 0 - .dw 0x0f13, 0xc437, 0x0f3f, 0xc437, 0x21, 0 - .dw 0x0f41, 0xc437, 0x0f41, 0xc437, 0x21, 0 - .dw 0x0f43, 0xc437, 0x0f4f, 0xc437, 0x21, 0 - .dw 0x0f51, 0xc437, 0x0f51, 0xc437, 0x21, 0 - .dw 0x0f53, 0xc437, 0x0f7f, 0xc437, 0x21, 0 - .dw 0x0f81, 0xc437, 0x0f81, 0xc437, 0x21, 0 - .dw 0x0f83, 0xc437, 0x0f8f, 0xc437, 0x21, 0 - .dw 0x0f91, 0xc437, 0x0f91, 0xc437, 0x21, 0 - .dw 0x0f93, 0xc437, 0x0fbf, 0xc437, 0x21, 0 - .dw 0x0fc1, 0xc437, 0x0fc1, 0xc437, 0x21, 0 - .dw 0x0fc3, 0xc437, 0x0fcf, 0xc437, 0x21, 0 - .dw 0x0fd1, 0xc437, 0x0fd1, 0xc437, 0x21, 0 - .dw 0x0fd3, 0xc437, 0x1fff, 0xc437, 0x21, 0 - .dw 0x2001, 0xc437, 0x2001, 0xc437, 0x21, 0 - .dw 0x2003, 0xc437, 0x200f, 0xc437, 0x21, 0 - .dw 0x2011, 0xc437, 0x2011, 0xc437, 0x21, 0 - .dw 0x2013, 0xc437, 0x203f, 0xc437, 0x21, 0 - .dw 0x2041, 0xc437, 0x2041, 0xc437, 0x21, 0 - .dw 0x2043, 0xc437, 0x204f, 0xc437, 0x21, 0 - .dw 0x2051, 0xc437, 0x2051, 0xc437, 0x21, 0 - .dw 0x2053, 0xc437, 0x207f, 0xc437, 0x21, 0 - .dw 0x2081, 0xc437, 0x2081, 0xc437, 0x21, 0 - .dw 0x2083, 0xc437, 0x208f, 0xc437, 0x21, 0 - .dw 0x2091, 0xc437, 0x2091, 0xc437, 0x21, 0 - .dw 0x2093, 0xc437, 0x20bf, 0xc437, 0x21, 0 - .dw 0x20c1, 0xc437, 0x20c1, 0xc437, 0x21, 0 - .dw 0x20c3, 0xc437, 0x20cf, 0xc437, 0x21, 0 - .dw 0x20d1, 0xc437, 0x20d1, 0xc437, 0x21, 0 - .dw 0x20d3, 0xc437, 0x20ff, 0xc437, 0x21, 0 - .dw 0x2101, 0xc437, 0x2101, 0xc437, 0x21, 0 - .dw 0x2103, 0xc437, 0x210f, 0xc437, 0x21, 0 - .dw 0x2111, 0xc437, 0x2111, 0xc437, 0x21, 0 - .dw 0x2113, 0xc437, 0x213f, 0xc437, 0x21, 0 - .dw 0x2141, 0xc437, 0x2141, 0xc437, 0x21, 0 - .dw 0x2143, 0xc437, 0x214f, 0xc437, 0x21, 0 - .dw 0x2151, 0xc437, 0x2151, 0xc437, 0x21, 0 - .dw 0x2153, 0xc437, 0x217f, 0xc437, 0x21, 0 - .dw 0x2181, 0xc437, 0x2181, 0xc437, 0x21, 0 - .dw 0x2183, 0xc437, 0x218f, 0xc437, 0x21, 0 - .dw 0x2191, 0xc437, 0x2191, 0xc437, 0x21, 0 - .dw 0x2193, 0xc437, 0x21bf, 0xc437, 0x21, 0 - .dw 0x21c1, 0xc437, 0x21c1, 0xc437, 0x21, 0 - .dw 0x21c3, 0xc437, 0x21cf, 0xc437, 0x21, 0 - .dw 0x21d1, 0xc437, 0x21d1, 0xc437, 0x21, 0 - .dw 0x21d3, 0xc437, 0x21ff, 0xc437, 0x21, 0 - .dw 0x2201, 0xc437, 0x2201, 0xc437, 0x21, 0 - .dw 0x2203, 0xc437, 0x220f, 0xc437, 0x21, 0 - .dw 0x2211, 0xc437, 0x2211, 0xc437, 0x21, 0 - .dw 0x2213, 0xc437, 0x223f, 0xc437, 0x21, 0 - .dw 0x2241, 0xc437, 0x2241, 0xc437, 0x21, 0 - .dw 0x2243, 0xc437, 0x224f, 0xc437, 0x21, 0 - .dw 0x2251, 0xc437, 0x2251, 0xc437, 0x21, 0 - .dw 0x2253, 0xc437, 0x227f, 0xc437, 0x21, 0 - .dw 0x2281, 0xc437, 0x2281, 0xc437, 0x21, 0 - .dw 0x2283, 0xc437, 0x228f, 0xc437, 0x21, 0 - .dw 0x2291, 0xc437, 0x2291, 0xc437, 0x21, 0 - .dw 0x2293, 0xc437, 0x22bf, 0xc437, 0x21, 0 - .dw 0x22c1, 0xc437, 0x22c1, 0xc437, 0x21, 0 - .dw 0x22c3, 0xc437, 0x22cf, 0xc437, 0x21, 0 - .dw 0x22d1, 0xc437, 0x22d1, 0xc437, 0x21, 0 - .dw 0x22d3, 0xc437, 0x22ff, 0xc437, 0x21, 0 - .dw 0x2301, 0xc437, 0x2301, 0xc437, 0x21, 0 - .dw 0x2303, 0xc437, 0x230f, 0xc437, 0x21, 0 - .dw 0x2311, 0xc437, 0x2311, 0xc437, 0x21, 0 - .dw 0x2313, 0xc437, 0x233f, 0xc437, 0x21, 0 - .dw 0x2341, 0xc437, 0x2341, 0xc437, 0x21, 0 - .dw 0x2343, 0xc437, 0x234f, 0xc437, 0x21, 0 - .dw 0x2351, 0xc437, 0x2351, 0xc437, 0x21, 0 - .dw 0x2353, 0xc437, 0x237f, 0xc437, 0x21, 0 - .dw 0x2381, 0xc437, 0x2381, 0xc437, 0x21, 0 - .dw 0x2383, 0xc437, 0x238f, 0xc437, 0x21, 0 - .dw 0x2391, 0xc437, 0x2391, 0xc437, 0x21, 0 - .dw 0x2393, 0xc437, 0x23bf, 0xc437, 0x21, 0 - .dw 0x23c1, 0xc437, 0x23c1, 0xc437, 0x21, 0 - .dw 0x23c3, 0xc437, 0x23cf, 0xc437, 0x21, 0 - .dw 0x23d1, 0xc437, 0x23d1, 0xc437, 0x21, 0 - .dw 0x23d3, 0xc437, 0x23ff, 0xc437, 0x21, 0 - .dw 0x2401, 0xc437, 0x2401, 0xc437, 0x21, 0 - .dw 0x2403, 0xc437, 0x240f, 0xc437, 0x21, 0 - .dw 0x2411, 0xc437, 0x2411, 0xc437, 0x21, 0 - .dw 0x2413, 0xc437, 0x243f, 0xc437, 0x21, 0 - .dw 0x2441, 0xc437, 0x2441, 0xc437, 0x21, 0 - .dw 0x2443, 0xc437, 0x244f, 0xc437, 0x21, 0 - .dw 0x2451, 0xc437, 0x2451, 0xc437, 0x21, 0 - .dw 0x2453, 0xc437, 0x247f, 0xc437, 0x21, 0 - .dw 0x2481, 0xc437, 0x2481, 0xc437, 0x21, 0 - .dw 0x2483, 0xc437, 0x248f, 0xc437, 0x21, 0 - .dw 0x2491, 0xc437, 0x2491, 0xc437, 0x21, 0 - .dw 0x2493, 0xc437, 0x24bf, 0xc437, 0x21, 0 - .dw 0x24c1, 0xc437, 0x24c1, 0xc437, 0x21, 0 - .dw 0x24c3, 0xc437, 0x24cf, 0xc437, 0x21, 0 - .dw 0x24d1, 0xc437, 0x24d1, 0xc437, 0x21, 0 - .dw 0x24d3, 0xc437, 0x24ff, 0xc437, 0x21, 0 - .dw 0x2501, 0xc437, 0x2501, 0xc437, 0x21, 0 - .dw 0x2503, 0xc437, 0x250f, 0xc437, 0x21, 0 - .dw 0x2511, 0xc437, 0x2511, 0xc437, 0x21, 0 - .dw 0x2513, 0xc437, 0x253f, 0xc437, 0x21, 0 - .dw 0x2541, 0xc437, 0x2541, 0xc437, 0x21, 0 - .dw 0x2543, 0xc437, 0x254f, 0xc437, 0x21, 0 - .dw 0x2551, 0xc437, 0x2551, 0xc437, 0x21, 0 - .dw 0x2553, 0xc437, 0x257f, 0xc437, 0x21, 0 - .dw 0x2581, 0xc437, 0x2581, 0xc437, 0x21, 0 - .dw 0x2583, 0xc437, 0x258f, 0xc437, 0x21, 0 - .dw 0x2591, 0xc437, 0x2591, 0xc437, 0x21, 0 - .dw 0x2593, 0xc437, 0x25bf, 0xc437, 0x21, 0 - .dw 0x25c1, 0xc437, 0x25c1, 0xc437, 0x21, 0 - .dw 0x25c3, 0xc437, 0x25cf, 0xc437, 0x21, 0 - .dw 0x25d1, 0xc437, 0x25d1, 0xc437, 0x21, 0 - .dw 0x25d3, 0xc437, 0x25ff, 0xc437, 0x21, 0 - .dw 0x2601, 0xc437, 0x2601, 0xc437, 0x21, 0 - .dw 0x2603, 0xc437, 0x260f, 0xc437, 0x21, 0 - .dw 0x2611, 0xc437, 0x2611, 0xc437, 0x21, 0 - .dw 0x2613, 0xc437, 0x263f, 0xc437, 0x21, 0 - .dw 0x2641, 0xc437, 0x2641, 0xc437, 0x21, 0 - .dw 0x2643, 0xc437, 0x264f, 0xc437, 0x21, 0 - .dw 0x2651, 0xc437, 0x2651, 0xc437, 0x21, 0 - .dw 0x2653, 0xc437, 0x267f, 0xc437, 0x21, 0 - .dw 0x2681, 0xc437, 0x2681, 0xc437, 0x21, 0 - .dw 0x2683, 0xc437, 0x268f, 0xc437, 0x21, 0 - .dw 0x2691, 0xc437, 0x2691, 0xc437, 0x21, 0 - .dw 0x2693, 0xc437, 0x26bf, 0xc437, 0x21, 0 - .dw 0x26c1, 0xc437, 0x26c1, 0xc437, 0x21, 0 - .dw 0x26c3, 0xc437, 0x26cf, 0xc437, 0x21, 0 - .dw 0x26d1, 0xc437, 0x26d1, 0xc437, 0x21, 0 - .dw 0x26d3, 0xc437, 0x26ff, 0xc437, 0x21, 0 - .dw 0x2701, 0xc437, 0x2701, 0xc437, 0x21, 0 - .dw 0x2703, 0xc437, 0x270f, 0xc437, 0x21, 0 - .dw 0x2711, 0xc437, 0x2711, 0xc437, 0x21, 0 - .dw 0x2713, 0xc437, 0x273f, 0xc437, 0x21, 0 - .dw 0x2741, 0xc437, 0x2741, 0xc437, 0x21, 0 - .dw 0x2743, 0xc437, 0x274f, 0xc437, 0x21, 0 - .dw 0x2751, 0xc437, 0x2751, 0xc437, 0x21, 0 - .dw 0x2753, 0xc437, 0x277f, 0xc437, 0x21, 0 - .dw 0x2781, 0xc437, 0x2781, 0xc437, 0x21, 0 - .dw 0x2783, 0xc437, 0x278f, 0xc437, 0x21, 0 - .dw 0x2791, 0xc437, 0x2791, 0xc437, 0x21, 0 - .dw 0x2793, 0xc437, 0x27bf, 0xc437, 0x21, 0 - .dw 0x27c1, 0xc437, 0x27c1, 0xc437, 0x21, 0 - .dw 0x27c3, 0xc437, 0x27cf, 0xc437, 0x21, 0 - .dw 0x27d1, 0xc437, 0x27d1, 0xc437, 0x21, 0 - .dw 0x27d3, 0xc437, 0x27ff, 0xc437, 0x21, 0 - .dw 0x2801, 0xc437, 0x2801, 0xc437, 0x21, 0 - .dw 0x2803, 0xc437, 0x280f, 0xc437, 0x21, 0 - .dw 0x2811, 0xc437, 0x2811, 0xc437, 0x21, 0 - .dw 0x2813, 0xc437, 0x283f, 0xc437, 0x21, 0 - .dw 0x2841, 0xc437, 0x2841, 0xc437, 0x21, 0 - .dw 0x2843, 0xc437, 0x284f, 0xc437, 0x21, 0 - .dw 0x2851, 0xc437, 0x2851, 0xc437, 0x21, 0 - .dw 0x2853, 0xc437, 0x287f, 0xc437, 0x21, 0 - .dw 0x2881, 0xc437, 0x2881, 0xc437, 0x21, 0 - .dw 0x2883, 0xc437, 0x288f, 0xc437, 0x21, 0 - .dw 0x2891, 0xc437, 0x2891, 0xc437, 0x21, 0 - .dw 0x2893, 0xc437, 0x28bf, 0xc437, 0x21, 0 - .dw 0x28c1, 0xc437, 0x28c1, 0xc437, 0x21, 0 - .dw 0x28c3, 0xc437, 0x28cf, 0xc437, 0x21, 0 - .dw 0x28d1, 0xc437, 0x28d1, 0xc437, 0x21, 0 - .dw 0x28d3, 0xc437, 0x28ff, 0xc437, 0x21, 0 - .dw 0x2901, 0xc437, 0x2901, 0xc437, 0x21, 0 - .dw 0x2903, 0xc437, 0x290f, 0xc437, 0x21, 0 - .dw 0x2911, 0xc437, 0x2911, 0xc437, 0x21, 0 - .dw 0x2913, 0xc437, 0x293f, 0xc437, 0x21, 0 - .dw 0x2941, 0xc437, 0x2941, 0xc437, 0x21, 0 - .dw 0x2943, 0xc437, 0x294f, 0xc437, 0x21, 0 - .dw 0x2951, 0xc437, 0x2951, 0xc437, 0x21, 0 - .dw 0x2953, 0xc437, 0x297f, 0xc437, 0x21, 0 - .dw 0x2981, 0xc437, 0x2981, 0xc437, 0x21, 0 - .dw 0x2983, 0xc437, 0x298f, 0xc437, 0x21, 0 - .dw 0x2991, 0xc437, 0x2991, 0xc437, 0x21, 0 - .dw 0x2993, 0xc437, 0x29bf, 0xc437, 0x21, 0 - .dw 0x29c1, 0xc437, 0x29c1, 0xc437, 0x21, 0 - .dw 0x29c3, 0xc437, 0x29cf, 0xc437, 0x21, 0 - .dw 0x29d1, 0xc437, 0x29d1, 0xc437, 0x21, 0 - .dw 0x29d3, 0xc437, 0x29ff, 0xc437, 0x21, 0 - .dw 0x2a01, 0xc437, 0x2a01, 0xc437, 0x21, 0 - .dw 0x2a03, 0xc437, 0x2a0f, 0xc437, 0x21, 0 - .dw 0x2a11, 0xc437, 0x2a11, 0xc437, 0x21, 0 - .dw 0x2a13, 0xc437, 0x2a3f, 0xc437, 0x21, 0 - .dw 0x2a41, 0xc437, 0x2a41, 0xc437, 0x21, 0 - .dw 0x2a43, 0xc437, 0x2a4f, 0xc437, 0x21, 0 - .dw 0x2a51, 0xc437, 0x2a51, 0xc437, 0x21, 0 - .dw 0x2a53, 0xc437, 0x2a7f, 0xc437, 0x21, 0 - .dw 0x2a81, 0xc437, 0x2a81, 0xc437, 0x21, 0 - .dw 0x2a83, 0xc437, 0x2a8f, 0xc437, 0x21, 0 - .dw 0x2a91, 0xc437, 0x2a91, 0xc437, 0x21, 0 - .dw 0x2a93, 0xc437, 0x2abf, 0xc437, 0x21, 0 - .dw 0x2ac1, 0xc437, 0x2ac1, 0xc437, 0x21, 0 - .dw 0x2ac3, 0xc437, 0x2acf, 0xc437, 0x21, 0 - .dw 0x2ad1, 0xc437, 0x2ad1, 0xc437, 0x21, 0 - .dw 0x2ad3, 0xc437, 0x2aff, 0xc437, 0x21, 0 - .dw 0x2b01, 0xc437, 0x2b01, 0xc437, 0x21, 0 - .dw 0x2b03, 0xc437, 0x2b0f, 0xc437, 0x21, 0 - .dw 0x2b11, 0xc437, 0x2b11, 0xc437, 0x21, 0 - .dw 0x2b13, 0xc437, 0x2b3f, 0xc437, 0x21, 0 - .dw 0x2b41, 0xc437, 0x2b41, 0xc437, 0x21, 0 - .dw 0x2b43, 0xc437, 0x2b4f, 0xc437, 0x21, 0 - .dw 0x2b51, 0xc437, 0x2b51, 0xc437, 0x21, 0 - .dw 0x2b53, 0xc437, 0x2b7f, 0xc437, 0x21, 0 - .dw 0x2b81, 0xc437, 0x2b81, 0xc437, 0x21, 0 - .dw 0x2b83, 0xc437, 0x2b8f, 0xc437, 0x21, 0 - .dw 0x2b91, 0xc437, 0x2b91, 0xc437, 0x21, 0 - .dw 0x2b93, 0xc437, 0x2bbf, 0xc437, 0x21, 0 - .dw 0x2bc1, 0xc437, 0x2bc1, 0xc437, 0x21, 0 - .dw 0x2bc3, 0xc437, 0x2bcf, 0xc437, 0x21, 0 - .dw 0x2bd1, 0xc437, 0x2bd1, 0xc437, 0x21, 0 - .dw 0x2bd3, 0xc437, 0x2bff, 0xc437, 0x21, 0 - .dw 0x2c01, 0xc437, 0x2c01, 0xc437, 0x21, 0 - .dw 0x2c03, 0xc437, 0x2c0f, 0xc437, 0x21, 0 - .dw 0x2c11, 0xc437, 0x2c11, 0xc437, 0x21, 0 - .dw 0x2c13, 0xc437, 0x2c3f, 0xc437, 0x21, 0 - .dw 0x2c41, 0xc437, 0x2c41, 0xc437, 0x21, 0 - .dw 0x2c43, 0xc437, 0x2c4f, 0xc437, 0x21, 0 - .dw 0x2c51, 0xc437, 0x2c51, 0xc437, 0x21, 0 - .dw 0x2c53, 0xc437, 0x2c7f, 0xc437, 0x21, 0 - .dw 0x2c81, 0xc437, 0x2c81, 0xc437, 0x21, 0 - .dw 0x2c83, 0xc437, 0x2c8f, 0xc437, 0x21, 0 - .dw 0x2c91, 0xc437, 0x2c91, 0xc437, 0x21, 0 - .dw 0x2c93, 0xc437, 0x2cbf, 0xc437, 0x21, 0 - .dw 0x2cc1, 0xc437, 0x2cc1, 0xc437, 0x21, 0 - .dw 0x2cc3, 0xc437, 0x2ccf, 0xc437, 0x21, 0 - .dw 0x2cd1, 0xc437, 0x2cd1, 0xc437, 0x21, 0 - .dw 0x2cd3, 0xc437, 0x2cff, 0xc437, 0x21, 0 - .dw 0x2d01, 0xc437, 0x2d01, 0xc437, 0x21, 0 - .dw 0x2d03, 0xc437, 0x2d0f, 0xc437, 0x21, 0 - .dw 0x2d11, 0xc437, 0x2d11, 0xc437, 0x21, 0 - .dw 0x2d13, 0xc437, 0x2d3f, 0xc437, 0x21, 0 - .dw 0x2d41, 0xc437, 0x2d41, 0xc437, 0x21, 0 - .dw 0x2d43, 0xc437, 0x2d4f, 0xc437, 0x21, 0 - .dw 0x2d51, 0xc437, 0x2d51, 0xc437, 0x21, 0 - .dw 0x2d53, 0xc437, 0x2d7f, 0xc437, 0x21, 0 - .dw 0x2d81, 0xc437, 0x2d81, 0xc437, 0x21, 0 - .dw 0x2d83, 0xc437, 0x2d8f, 0xc437, 0x21, 0 - .dw 0x2d91, 0xc437, 0x2d91, 0xc437, 0x21, 0 - .dw 0x2d93, 0xc437, 0x2dbf, 0xc437, 0x21, 0 - .dw 0x2dc1, 0xc437, 0x2dc1, 0xc437, 0x21, 0 - .dw 0x2dc3, 0xc437, 0x2dcf, 0xc437, 0x21, 0 - .dw 0x2dd1, 0xc437, 0x2dd1, 0xc437, 0x21, 0 - .dw 0x2dd3, 0xc437, 0x2dff, 0xc437, 0x21, 0 - .dw 0x2e01, 0xc437, 0x2e01, 0xc437, 0x21, 0 - .dw 0x2e03, 0xc437, 0x2e0f, 0xc437, 0x21, 0 - .dw 0x2e11, 0xc437, 0x2e11, 0xc437, 0x21, 0 - .dw 0x2e13, 0xc437, 0x2e3f, 0xc437, 0x21, 0 - .dw 0x2e41, 0xc437, 0x2e41, 0xc437, 0x21, 0 - .dw 0x2e43, 0xc437, 0x2e4f, 0xc437, 0x21, 0 - .dw 0x2e51, 0xc437, 0x2e51, 0xc437, 0x21, 0 - .dw 0x2e53, 0xc437, 0x2e7f, 0xc437, 0x21, 0 - .dw 0x2e81, 0xc437, 0x2e81, 0xc437, 0x21, 0 - .dw 0x2e83, 0xc437, 0x2e8f, 0xc437, 0x21, 0 - .dw 0x2e91, 0xc437, 0x2e91, 0xc437, 0x21, 0 - .dw 0x2e93, 0xc437, 0x2ebf, 0xc437, 0x21, 0 - .dw 0x2ec1, 0xc437, 0x2ec1, 0xc437, 0x21, 0 - .dw 0x2ec3, 0xc437, 0x2ecf, 0xc437, 0x21, 0 - .dw 0x2ed1, 0xc437, 0x2ed1, 0xc437, 0x21, 0 - .dw 0x2ed3, 0xc437, 0x2eff, 0xc437, 0x21, 0 - .dw 0x2f01, 0xc437, 0x2f01, 0xc437, 0x21, 0 - .dw 0x2f03, 0xc437, 0x2f0f, 0xc437, 0x21, 0 - .dw 0x2f11, 0xc437, 0x2f11, 0xc437, 0x21, 0 - .dw 0x2f13, 0xc437, 0x2f3f, 0xc437, 0x21, 0 - .dw 0x2f41, 0xc437, 0x2f41, 0xc437, 0x21, 0 - .dw 0x2f43, 0xc437, 0x2f4f, 0xc437, 0x21, 0 - .dw 0x2f51, 0xc437, 0x2f51, 0xc437, 0x21, 0 - .dw 0x2f53, 0xc437, 0x2f7f, 0xc437, 0x21, 0 - .dw 0x2f81, 0xc437, 0x2f81, 0xc437, 0x21, 0 - .dw 0x2f83, 0xc437, 0x2f8f, 0xc437, 0x21, 0 - .dw 0x2f91, 0xc437, 0x2f91, 0xc437, 0x21, 0 - .dw 0x2f93, 0xc437, 0x2fbf, 0xc437, 0x21, 0 - .dw 0x2fc1, 0xc437, 0x2fc1, 0xc437, 0x21, 0 - .dw 0x2fc3, 0xc437, 0x2fcf, 0xc437, 0x21, 0 - .dw 0x2fd1, 0xc437, 0x2fd1, 0xc437, 0x21, 0 - .dw 0x2fd3, 0xc437, 0xffff, 0xc5ff, 0x21, 0 - .dw 0x0040, 0xc600, 0x01ff, 0xc600, 0x21, 0 - .dw 0x0240, 0xc600, 0x03ff, 0xc600, 0x21, 0 - .dw 0x0440, 0xc600, 0x05ff, 0xc600, 0x21, 0 - .dw 0x0640, 0xc600, 0x07ff, 0xc600, 0x21, 0 - .dw 0x0840, 0xc600, 0x09ff, 0xc600, 0x21, 0 - .dw 0x0a40, 0xc600, 0x0bff, 0xc600, 0x21, 0 - .dw 0x0c40, 0xc600, 0x0dff, 0xc600, 0x21, 0 - .dw 0x0e40, 0xc600, 0x0fff, 0xc600, 0x21, 0 - .dw 0x1040, 0xc600, 0x11ff, 0xc600, 0x21, 0 - .dw 0x1240, 0xc600, 0x13ff, 0xc600, 0x21, 0 - .dw 0x1440, 0xc600, 0x15ff, 0xc600, 0x21, 0 - .dw 0x1640, 0xc600, 0x17ff, 0xc600, 0x21, 0 - .dw 0x1840, 0xc600, 0x19ff, 0xc600, 0x21, 0 - .dw 0x1a40, 0xc600, 0x1bff, 0xc600, 0x21, 0 - .dw 0x1c40, 0xc600, 0x1dff, 0xc600, 0x21, 0 - .dw 0x1e40, 0xc600, 0x1fff, 0xc600, 0x21, 0 - .dw 0x2040, 0xc600, 0x21ff, 0xc600, 0x21, 0 - .dw 0x2240, 0xc600, 0x23ff, 0xc600, 0x21, 0 - .dw 0x2440, 0xc600, 0x25ff, 0xc600, 0x21, 0 - .dw 0x2640, 0xc600, 0x27ff, 0xc600, 0x21, 0 - .dw 0x2840, 0xc600, 0x29ff, 0xc600, 0x21, 0 - .dw 0x2a40, 0xc600, 0x2bff, 0xc600, 0x21, 0 - .dw 0x2c40, 0xc600, 0x2dff, 0xc600, 0x21, 0 - .dw 0x2e40, 0xc600, 0x2fff, 0xc600, 0x21, 0 - .dw 0x3040, 0xc600, 0x31ff, 0xc600, 0x21, 0 - .dw 0x3240, 0xc600, 0x33ff, 0xc600, 0x21, 0 - .dw 0x3440, 0xc600, 0x35ff, 0xc600, 0x21, 0 - .dw 0x3640, 0xc600, 0x37ff, 0xc600, 0x21, 0 - .dw 0x3840, 0xc600, 0x39ff, 0xc600, 0x21, 0 - .dw 0x3a40, 0xc600, 0x3bff, 0xc600, 0x21, 0 - .dw 0x3c40, 0xc600, 0x3dff, 0xc600, 0x21, 0 - .dw 0x3e40, 0xc600, 0x3fff, 0xc600, 0x21, 0 - .dw 0x4040, 0xc600, 0x41ff, 0xc600, 0x21, 0 - .dw 0x4240, 0xc600, 0x43ff, 0xc600, 0x21, 0 - .dw 0x4440, 0xc600, 0x45ff, 0xc600, 0x21, 0 - .dw 0x4640, 0xc600, 0x47ff, 0xc600, 0x21, 0 - .dw 0x4840, 0xc600, 0x49ff, 0xc600, 0x21, 0 - .dw 0x4a40, 0xc600, 0x4bff, 0xc600, 0x21, 0 - .dw 0x4c40, 0xc600, 0x4dff, 0xc600, 0x21, 0 - .dw 0x4e40, 0xc600, 0x4fff, 0xc600, 0x21, 0 - .dw 0x5040, 0xc600, 0x51ff, 0xc600, 0x21, 0 - .dw 0x5240, 0xc600, 0x53ff, 0xc600, 0x21, 0 - .dw 0x5440, 0xc600, 0x55ff, 0xc600, 0x21, 0 - .dw 0x5640, 0xc600, 0x57ff, 0xc600, 0x21, 0 - .dw 0x5840, 0xc600, 0x59ff, 0xc600, 0x21, 0 - .dw 0x5a40, 0xc600, 0x5bff, 0xc600, 0x21, 0 - .dw 0x5c40, 0xc600, 0x5dff, 0xc600, 0x21, 0 - .dw 0x5e40, 0xc600, 0x5fff, 0xc600, 0x21, 0 - .dw 0x6040, 0xc600, 0x61ff, 0xc600, 0x21, 0 - .dw 0x6240, 0xc600, 0x63ff, 0xc600, 0x21, 0 - .dw 0x6440, 0xc600, 0x65ff, 0xc600, 0x21, 0 - .dw 0x6640, 0xc600, 0x67ff, 0xc600, 0x21, 0 - .dw 0x6840, 0xc600, 0x69ff, 0xc600, 0x21, 0 - .dw 0x6a40, 0xc600, 0x6bff, 0xc600, 0x21, 0 - .dw 0x6c40, 0xc600, 0x6dff, 0xc600, 0x21, 0 - .dw 0x6e40, 0xc600, 0x6fff, 0xc600, 0x21, 0 - .dw 0x7040, 0xc600, 0x71ff, 0xc600, 0x21, 0 - .dw 0x7240, 0xc600, 0x73ff, 0xc600, 0x21, 0 - .dw 0x7440, 0xc600, 0x75ff, 0xc600, 0x21, 0 - .dw 0x7640, 0xc600, 0x77ff, 0xc600, 0x21, 0 - .dw 0x7840, 0xc600, 0x79ff, 0xc600, 0x21, 0 - .dw 0x7a40, 0xc600, 0x7bff, 0xc600, 0x21, 0 - .dw 0x7c40, 0xc600, 0x7dff, 0xc600, 0x21, 0 - .dw 0x7e40, 0xc600, 0x7fff, 0xc600, 0x21, 0 - .dw 0x8040, 0xc600, 0x81ff, 0xc600, 0x21, 0 - .dw 0x8240, 0xc600, 0x83ff, 0xc600, 0x21, 0 - .dw 0x8440, 0xc600, 0x85ff, 0xc600, 0x21, 0 - .dw 0x8640, 0xc600, 0x87ff, 0xc600, 0x21, 0 - .dw 0x8840, 0xc600, 0x89ff, 0xc600, 0x21, 0 - .dw 0x8a40, 0xc600, 0x8bff, 0xc600, 0x21, 0 - .dw 0x8c40, 0xc600, 0x8dff, 0xc600, 0x21, 0 - .dw 0x8e40, 0xc600, 0x8fff, 0xc600, 0x21, 0 - .dw 0x9040, 0xc600, 0x91ff, 0xc600, 0x21, 0 - .dw 0x9240, 0xc600, 0x93ff, 0xc600, 0x21, 0 - .dw 0x9440, 0xc600, 0x95ff, 0xc600, 0x21, 0 - .dw 0x9640, 0xc600, 0x97ff, 0xc600, 0x21, 0 - .dw 0x9840, 0xc600, 0x99ff, 0xc600, 0x21, 0 - .dw 0x9a40, 0xc600, 0x9bff, 0xc600, 0x21, 0 - .dw 0x9c40, 0xc600, 0x9dff, 0xc600, 0x21, 0 - .dw 0x9e40, 0xc600, 0x9fff, 0xc600, 0x21, 0 - .dw 0xa040, 0xc600, 0xa1ff, 0xc600, 0x21, 0 - .dw 0xa240, 0xc600, 0xa3ff, 0xc600, 0x21, 0 - .dw 0xa440, 0xc600, 0xa5ff, 0xc600, 0x21, 0 - .dw 0xa640, 0xc600, 0xa7ff, 0xc600, 0x21, 0 - .dw 0xa840, 0xc600, 0xa9ff, 0xc600, 0x21, 0 - .dw 0xaa40, 0xc600, 0xabff, 0xc600, 0x21, 0 - .dw 0xac40, 0xc600, 0xadff, 0xc600, 0x21, 0 - .dw 0xae40, 0xc600, 0xafff, 0xc600, 0x21, 0 - .dw 0xb040, 0xc600, 0xb1ff, 0xc600, 0x21, 0 - .dw 0xb240, 0xc600, 0xb3ff, 0xc600, 0x21, 0 - .dw 0xb440, 0xc600, 0xb5ff, 0xc600, 0x21, 0 - .dw 0xb640, 0xc600, 0xb7ff, 0xc600, 0x21, 0 - .dw 0xb840, 0xc600, 0xb9ff, 0xc600, 0x21, 0 - .dw 0xba40, 0xc600, 0xbbff, 0xc600, 0x21, 0 - .dw 0xbc40, 0xc600, 0xbdff, 0xc600, 0x21, 0 - .dw 0xbe40, 0xc600, 0xffff, 0xc600, 0x21, 0 - .dw 0x0040, 0xc601, 0x01ff, 0xc601, 0x21, 0 - .dw 0x0240, 0xc601, 0x03ff, 0xc601, 0x21, 0 - .dw 0x0440, 0xc601, 0x05ff, 0xc601, 0x21, 0 - .dw 0x0640, 0xc601, 0x07ff, 0xc601, 0x21, 0 - .dw 0x0840, 0xc601, 0x09ff, 0xc601, 0x21, 0 - .dw 0x0a40, 0xc601, 0x0bff, 0xc601, 0x21, 0 - .dw 0x0c40, 0xc601, 0x0dff, 0xc601, 0x21, 0 - .dw 0x0e40, 0xc601, 0x3fff, 0xc601, 0x21, 0 - .dw 0x4040, 0xc601, 0x41ff, 0xc601, 0x21, 0 - .dw 0x4240, 0xc601, 0x43ff, 0xc601, 0x21, 0 - .dw 0x4440, 0xc601, 0x45ff, 0xc601, 0x21, 0 - .dw 0x4640, 0xc601, 0x47ff, 0xc601, 0x21, 0 - .dw 0x4840, 0xc601, 0x49ff, 0xc601, 0x21, 0 - .dw 0x4a40, 0xc601, 0x4bff, 0xc601, 0x21, 0 - .dw 0x4c40, 0xc601, 0x4dff, 0xc601, 0x21, 0 - .dw 0x4e40, 0xc601, 0x7fff, 0xc601, 0x21, 0 - .dw 0x8040, 0xc601, 0x81ff, 0xc601, 0x21, 0 - .dw 0x8240, 0xc601, 0x83ff, 0xc601, 0x21, 0 - .dw 0x8440, 0xc601, 0x85ff, 0xc601, 0x21, 0 - .dw 0x8640, 0xc601, 0x87ff, 0xc601, 0x21, 0 - .dw 0x8840, 0xc601, 0x89ff, 0xc601, 0x21, 0 - .dw 0x8a40, 0xc601, 0x8bff, 0xc601, 0x21, 0 - .dw 0x8c40, 0xc601, 0x8dff, 0xc601, 0x21, 0 - .dw 0x8e40, 0xc601, 0xffff, 0xc601, 0x21, 0 - .dw 0x0040, 0xc602, 0x01ff, 0xc602, 0x21, 0 - .dw 0x0240, 0xc602, 0x03ff, 0xc602, 0x21, 0 - .dw 0x0440, 0xc602, 0x05ff, 0xc602, 0x21, 0 - .dw 0x0640, 0xc602, 0x07ff, 0xc602, 0x21, 0 - .dw 0x0840, 0xc602, 0x09ff, 0xc602, 0x21, 0 - .dw 0x0a40, 0xc602, 0x0bff, 0xc602, 0x21, 0 - .dw 0x0c40, 0xc602, 0x0dff, 0xc602, 0x21, 0 - .dw 0x0e40, 0xc602, 0x3fff, 0xc602, 0x21, 0 - .dw 0x4040, 0xc602, 0x41ff, 0xc602, 0x21, 0 - .dw 0x4240, 0xc602, 0x43ff, 0xc602, 0x21, 0 - .dw 0x4440, 0xc602, 0x45ff, 0xc602, 0x21, 0 - .dw 0x4640, 0xc602, 0x47ff, 0xc602, 0x21, 0 - .dw 0x4840, 0xc602, 0x49ff, 0xc602, 0x21, 0 - .dw 0x4a40, 0xc602, 0x4bff, 0xc602, 0x21, 0 - .dw 0x4c40, 0xc602, 0x4dff, 0xc602, 0x21, 0 - .dw 0x4e40, 0xc602, 0x7fff, 0xc602, 0x21, 0 - .dw 0x8040, 0xc602, 0x81ff, 0xc602, 0x21, 0 - .dw 0x8240, 0xc602, 0x83ff, 0xc602, 0x21, 0 - .dw 0x8440, 0xc602, 0x85ff, 0xc602, 0x21, 0 - .dw 0x8640, 0xc602, 0x87ff, 0xc602, 0x21, 0 - .dw 0x8840, 0xc602, 0x89ff, 0xc602, 0x21, 0 - .dw 0x8a40, 0xc602, 0x8bff, 0xc602, 0x21, 0 - .dw 0x8c40, 0xc602, 0x8dff, 0xc602, 0x21, 0 - .dw 0x8e40, 0xc602, 0xbfff, 0xc602, 0x21, 0 - .dw 0xc040, 0xc602, 0xc1ff, 0xc602, 0x21, 0 - .dw 0xc240, 0xc602, 0xc3ff, 0xc602, 0x21, 0 - .dw 0xc440, 0xc602, 0xc5ff, 0xc602, 0x21, 0 - .dw 0xc640, 0xc602, 0xc7ff, 0xc602, 0x21, 0 - .dw 0xc840, 0xc602, 0xc9ff, 0xc602, 0x21, 0 - .dw 0xca40, 0xc602, 0xcbff, 0xc602, 0x21, 0 - .dw 0xcc40, 0xc602, 0xcdff, 0xc602, 0x21, 0 - .dw 0xce40, 0xc602, 0xffff, 0xc602, 0x21, 0 - .dw 0x0040, 0xc603, 0x01ff, 0xc603, 0x21, 0 - .dw 0x0240, 0xc603, 0x03ff, 0xc603, 0x21, 0 - .dw 0x0440, 0xc603, 0x05ff, 0xc603, 0x21, 0 - .dw 0x0640, 0xc603, 0x07ff, 0xc603, 0x21, 0 - .dw 0x0840, 0xc603, 0x09ff, 0xc603, 0x21, 0 - .dw 0x0a40, 0xc603, 0x0bff, 0xc603, 0x21, 0 - .dw 0x0c40, 0xc603, 0x0dff, 0xc603, 0x21, 0 - .dw 0x0e40, 0xc603, 0x0fff, 0xc603, 0x21, 0 - .dw 0x1040, 0xc603, 0x11ff, 0xc603, 0x21, 0 - .dw 0x1240, 0xc603, 0x13ff, 0xc603, 0x21, 0 - .dw 0x1440, 0xc603, 0x15ff, 0xc603, 0x21, 0 - .dw 0x1640, 0xc603, 0x17ff, 0xc603, 0x21, 0 - .dw 0x1840, 0xc603, 0x19ff, 0xc603, 0x21, 0 - .dw 0x1a40, 0xc603, 0x1bff, 0xc603, 0x21, 0 - .dw 0x1c40, 0xc603, 0x1dff, 0xc603, 0x21, 0 - .dw 0x1e40, 0xc603, 0x3fff, 0xc603, 0x21, 0 - .dw 0x4040, 0xc603, 0x41ff, 0xc603, 0x21, 0 - .dw 0x4240, 0xc603, 0x43ff, 0xc603, 0x21, 0 - .dw 0x4440, 0xc603, 0x45ff, 0xc603, 0x21, 0 - .dw 0x4640, 0xc603, 0x47ff, 0xc603, 0x21, 0 - .dw 0x4840, 0xc603, 0x49ff, 0xc603, 0x21, 0 - .dw 0x4a40, 0xc603, 0x4bff, 0xc603, 0x21, 0 - .dw 0x4c40, 0xc603, 0x4dff, 0xc603, 0x21, 0 - .dw 0x4e40, 0xc603, 0x4fff, 0xc603, 0x21, 0 - .dw 0x5040, 0xc603, 0x51ff, 0xc603, 0x21, 0 - .dw 0x5240, 0xc603, 0x53ff, 0xc603, 0x21, 0 - .dw 0x5440, 0xc603, 0x55ff, 0xc603, 0x21, 0 - .dw 0x5640, 0xc603, 0x57ff, 0xc603, 0x21, 0 - .dw 0x5840, 0xc603, 0x59ff, 0xc603, 0x21, 0 - .dw 0x5a40, 0xc603, 0x5bff, 0xc603, 0x21, 0 - .dw 0x5c40, 0xc603, 0x5dff, 0xc603, 0x21, 0 - .dw 0x5e40, 0xc603, 0x7fff, 0xc603, 0x21, 0 - .dw 0x8040, 0xc603, 0x81ff, 0xc603, 0x21, 0 - .dw 0x8240, 0xc603, 0x83ff, 0xc603, 0x21, 0 - .dw 0x8440, 0xc603, 0x85ff, 0xc603, 0x21, 0 - .dw 0x8640, 0xc603, 0x87ff, 0xc603, 0x21, 0 - .dw 0x8840, 0xc603, 0x89ff, 0xc603, 0x21, 0 - .dw 0x8a40, 0xc603, 0x8bff, 0xc603, 0x21, 0 - .dw 0x8c40, 0xc603, 0x8dff, 0xc603, 0x21, 0 - .dw 0x8e40, 0xc603, 0x8fff, 0xc603, 0x21, 0 - .dw 0x9040, 0xc603, 0x91ff, 0xc603, 0x21, 0 - .dw 0x9240, 0xc603, 0x93ff, 0xc603, 0x21, 0 - .dw 0x9440, 0xc603, 0x95ff, 0xc603, 0x21, 0 - .dw 0x9640, 0xc603, 0x97ff, 0xc603, 0x21, 0 - .dw 0x9840, 0xc603, 0x99ff, 0xc603, 0x21, 0 - .dw 0x9a40, 0xc603, 0x9bff, 0xc603, 0x21, 0 - .dw 0x9c40, 0xc603, 0x9dff, 0xc603, 0x21, 0 - .dw 0x9e40, 0xc603, 0xffff, 0xc603, 0x21, 0 - .dw 0x0040, 0xc604, 0x01ff, 0xc604, 0x21, 0 - .dw 0x0240, 0xc604, 0x03ff, 0xc604, 0x21, 0 - .dw 0x0440, 0xc604, 0x05ff, 0xc604, 0x21, 0 - .dw 0x0640, 0xc604, 0x07ff, 0xc604, 0x21, 0 - .dw 0x0840, 0xc604, 0x09ff, 0xc604, 0x21, 0 - .dw 0x0a40, 0xc604, 0x0bff, 0xc604, 0x21, 0 - .dw 0x0c40, 0xc604, 0x0dff, 0xc604, 0x21, 0 - .dw 0x0e40, 0xc604, 0x3fff, 0xc604, 0x21, 0 - .dw 0x4040, 0xc604, 0x41ff, 0xc604, 0x21, 0 - .dw 0x4240, 0xc604, 0x43ff, 0xc604, 0x21, 0 - .dw 0x4440, 0xc604, 0x45ff, 0xc604, 0x21, 0 - .dw 0x4640, 0xc604, 0x47ff, 0xc604, 0x21, 0 - .dw 0x4840, 0xc604, 0x49ff, 0xc604, 0x21, 0 - .dw 0x4a40, 0xc604, 0x4bff, 0xc604, 0x21, 0 - .dw 0x4c40, 0xc604, 0x4dff, 0xc604, 0x21, 0 - .dw 0x4e40, 0xc604, 0x7fff, 0xc604, 0x21, 0 - .dw 0x8040, 0xc604, 0x81ff, 0xc604, 0x21, 0 - .dw 0x8240, 0xc604, 0x83ff, 0xc604, 0x21, 0 - .dw 0x8440, 0xc604, 0x85ff, 0xc604, 0x21, 0 - .dw 0x8640, 0xc604, 0x87ff, 0xc604, 0x21, 0 - .dw 0x8840, 0xc604, 0x89ff, 0xc604, 0x21, 0 - .dw 0x8a40, 0xc604, 0x8bff, 0xc604, 0x21, 0 - .dw 0x8c40, 0xc604, 0x8dff, 0xc604, 0x21, 0 - .dw 0x8e40, 0xc604, 0xbfff, 0xc604, 0x21, 0 - .dw 0xc040, 0xc604, 0xc1ff, 0xc604, 0x21, 0 - .dw 0xc240, 0xc604, 0xc3ff, 0xc604, 0x21, 0 - .dw 0xc440, 0xc604, 0xc5ff, 0xc604, 0x21, 0 - .dw 0xc640, 0xc604, 0xc7ff, 0xc604, 0x21, 0 - .dw 0xc840, 0xc604, 0xc9ff, 0xc604, 0x21, 0 - .dw 0xca40, 0xc604, 0xcbff, 0xc604, 0x21, 0 - .dw 0xcc40, 0xc604, 0xcdff, 0xc604, 0x21, 0 - .dw 0xce40, 0xc604, 0xffff, 0xc604, 0x21, 0 - .dw 0x0040, 0xc605, 0x01ff, 0xc605, 0x21, 0 - .dw 0x0240, 0xc605, 0x03ff, 0xc605, 0x21, 0 - .dw 0x0440, 0xc605, 0x05ff, 0xc605, 0x21, 0 - .dw 0x0640, 0xc605, 0x07ff, 0xc605, 0x21, 0 - .dw 0x0840, 0xc605, 0x09ff, 0xc605, 0x21, 0 - .dw 0x0a40, 0xc605, 0x0bff, 0xc605, 0x21, 0 - .dw 0x0c40, 0xc605, 0x0dff, 0xc605, 0x21, 0 - .dw 0x0e40, 0xc605, 0x3fff, 0xc605, 0x21, 0 - .dw 0x4040, 0xc605, 0x41ff, 0xc605, 0x21, 0 - .dw 0x4240, 0xc605, 0x43ff, 0xc605, 0x21, 0 - .dw 0x4440, 0xc605, 0x45ff, 0xc605, 0x21, 0 - .dw 0x4640, 0xc605, 0x47ff, 0xc605, 0x21, 0 - .dw 0x4840, 0xc605, 0x49ff, 0xc605, 0x21, 0 - .dw 0x4a40, 0xc605, 0x4bff, 0xc605, 0x21, 0 - .dw 0x4c40, 0xc605, 0x4dff, 0xc605, 0x21, 0 - .dw 0x4e40, 0xc605, 0x7fff, 0xc605, 0x21, 0 - .dw 0x8040, 0xc605, 0x81ff, 0xc605, 0x21, 0 - .dw 0x8240, 0xc605, 0x83ff, 0xc605, 0x21, 0 - .dw 0x8440, 0xc605, 0x85ff, 0xc605, 0x21, 0 - .dw 0x8640, 0xc605, 0x87ff, 0xc605, 0x21, 0 - .dw 0x8840, 0xc605, 0x89ff, 0xc605, 0x21, 0 - .dw 0x8a40, 0xc605, 0x8bff, 0xc605, 0x21, 0 - .dw 0x8c40, 0xc605, 0x8dff, 0xc605, 0x21, 0 - .dw 0x8e40, 0xc605, 0xffff, 0xc605, 0x21, 0 - .dw 0x0040, 0xc606, 0x01ff, 0xc606, 0x21, 0 - .dw 0x0240, 0xc606, 0x03ff, 0xc606, 0x21, 0 - .dw 0x0440, 0xc606, 0x05ff, 0xc606, 0x21, 0 - .dw 0x0640, 0xc606, 0x07ff, 0xc606, 0x21, 0 - .dw 0x0840, 0xc606, 0x09ff, 0xc606, 0x21, 0 - .dw 0x0a40, 0xc606, 0x0bff, 0xc606, 0x21, 0 - .dw 0x0c40, 0xc606, 0x0dff, 0xc606, 0x21, 0 - .dw 0x0e40, 0xc606, 0x3fff, 0xc606, 0x21, 0 - .dw 0x4040, 0xc606, 0x41ff, 0xc606, 0x21, 0 - .dw 0x4240, 0xc606, 0x43ff, 0xc606, 0x21, 0 - .dw 0x4440, 0xc606, 0x45ff, 0xc606, 0x21, 0 - .dw 0x4640, 0xc606, 0x47ff, 0xc606, 0x21, 0 - .dw 0x4840, 0xc606, 0x49ff, 0xc606, 0x21, 0 - .dw 0x4a40, 0xc606, 0x4bff, 0xc606, 0x21, 0 - .dw 0x4c40, 0xc606, 0x4dff, 0xc606, 0x21, 0 - .dw 0x4e40, 0xc606, 0xbfff, 0xc606, 0x21, 0 - .dw 0xc040, 0xc606, 0xc1ff, 0xc606, 0x21, 0 - .dw 0xc240, 0xc606, 0xc3ff, 0xc606, 0x21, 0 - .dw 0xc440, 0xc606, 0xc5ff, 0xc606, 0x21, 0 - .dw 0xc640, 0xc606, 0xc7ff, 0xc606, 0x21, 0 - .dw 0xc840, 0xc606, 0xc9ff, 0xc606, 0x21, 0 - .dw 0xca40, 0xc606, 0xcbff, 0xc606, 0x21, 0 - .dw 0xcc40, 0xc606, 0xcdff, 0xc606, 0x21, 0 - .dw 0xce40, 0xc606, 0xffff, 0xc606, 0x21, 0 - .dw 0x0040, 0xc607, 0x01ff, 0xc607, 0x21, 0 - .dw 0x0240, 0xc607, 0x03ff, 0xc607, 0x21, 0 - .dw 0x0440, 0xc607, 0x05ff, 0xc607, 0x21, 0 - .dw 0x0640, 0xc607, 0x07ff, 0xc607, 0x21, 0 - .dw 0x0840, 0xc607, 0x09ff, 0xc607, 0x21, 0 - .dw 0x0a40, 0xc607, 0x0bff, 0xc607, 0x21, 0 - .dw 0x0c40, 0xc607, 0x0dff, 0xc607, 0x21, 0 - .dw 0x0e40, 0xc607, 0x3fff, 0xc607, 0x21, 0 - .dw 0x4040, 0xc607, 0x41ff, 0xc607, 0x21, 0 - .dw 0x4240, 0xc607, 0x43ff, 0xc607, 0x21, 0 - .dw 0x4440, 0xc607, 0x45ff, 0xc607, 0x21, 0 - .dw 0x4640, 0xc607, 0x47ff, 0xc607, 0x21, 0 - .dw 0x4840, 0xc607, 0x49ff, 0xc607, 0x21, 0 - .dw 0x4a40, 0xc607, 0x4bff, 0xc607, 0x21, 0 - .dw 0x4c40, 0xc607, 0x4dff, 0xc607, 0x21, 0 - .dw 0x4e40, 0xc607, 0x7fff, 0xc607, 0x21, 0 - .dw 0x8040, 0xc607, 0x81ff, 0xc607, 0x21, 0 - .dw 0x8240, 0xc607, 0x83ff, 0xc607, 0x21, 0 - .dw 0x8440, 0xc607, 0x85ff, 0xc607, 0x21, 0 - .dw 0x8640, 0xc607, 0x87ff, 0xc607, 0x21, 0 - .dw 0x8840, 0xc607, 0x89ff, 0xc607, 0x21, 0 - .dw 0x8a40, 0xc607, 0x8bff, 0xc607, 0x21, 0 - .dw 0x8c40, 0xc607, 0x8dff, 0xc607, 0x21, 0 - .dw 0x8e40, 0xc607, 0xbfff, 0xc607, 0x21, 0 - .dw 0xc040, 0xc607, 0xc1ff, 0xc607, 0x21, 0 - .dw 0xc240, 0xc607, 0xc3ff, 0xc607, 0x21, 0 - .dw 0xc440, 0xc607, 0xc5ff, 0xc607, 0x21, 0 - .dw 0xc640, 0xc607, 0xc7ff, 0xc607, 0x21, 0 - .dw 0xc840, 0xc607, 0xc9ff, 0xc607, 0x21, 0 - .dw 0xca40, 0xc607, 0xcbff, 0xc607, 0x21, 0 - .dw 0xcc40, 0xc607, 0xcdff, 0xc607, 0x21, 0 - .dw 0xce40, 0xc607, 0xffff, 0xc607, 0x21, 0 - .dw 0x0000, 0xc608, 0x0000, 0xc608, 0x22, 0 - .dw 0x0009, 0xc608, 0x0009, 0xc608, 0x22, 0 - .dw 0x0012, 0xc608, 0x0012, 0xc608, 0x22, 0 - .dw 0x001b, 0xc608, 0x001b, 0xc608, 0x22, 0 - .dw 0x0024, 0xc608, 0x0024, 0xc608, 0x22, 0 - .dw 0x002d, 0xc608, 0x002d, 0xc608, 0x22, 0 - .dw 0x0036, 0xc608, 0x0036, 0xc608, 0x22, 0 - .dw 0x003f, 0xc608, 0x003f, 0xc608, 0x22, 0 - .dw 0x0040, 0xc608, 0x01ff, 0xc608, 0x21, 0 - .dw 0x0200, 0xc608, 0x0200, 0xc608, 0x22, 0 - .dw 0x0209, 0xc608, 0x0209, 0xc608, 0x22, 0 - .dw 0x0212, 0xc608, 0x0212, 0xc608, 0x22, 0 - .dw 0x021b, 0xc608, 0x021b, 0xc608, 0x22, 0 - .dw 0x0224, 0xc608, 0x0224, 0xc608, 0x22, 0 - .dw 0x022d, 0xc608, 0x022d, 0xc608, 0x22, 0 - .dw 0x0236, 0xc608, 0x0236, 0xc608, 0x22, 0 - .dw 0x023f, 0xc608, 0x023f, 0xc608, 0x22, 0 - .dw 0x0240, 0xc608, 0x03ff, 0xc608, 0x21, 0 - .dw 0x0400, 0xc608, 0x0400, 0xc608, 0x22, 0 - .dw 0x0409, 0xc608, 0x0409, 0xc608, 0x22, 0 - .dw 0x0412, 0xc608, 0x0412, 0xc608, 0x22, 0 - .dw 0x041b, 0xc608, 0x041b, 0xc608, 0x22, 0 - .dw 0x0424, 0xc608, 0x0424, 0xc608, 0x22, 0 - .dw 0x042d, 0xc608, 0x042d, 0xc608, 0x22, 0 - .dw 0x0436, 0xc608, 0x0436, 0xc608, 0x22, 0 - .dw 0x043f, 0xc608, 0x043f, 0xc608, 0x22, 0 - .dw 0x0440, 0xc608, 0x05ff, 0xc608, 0x21, 0 - .dw 0x0600, 0xc608, 0x0600, 0xc608, 0x22, 0 - .dw 0x0609, 0xc608, 0x0609, 0xc608, 0x22, 0 - .dw 0x0612, 0xc608, 0x0612, 0xc608, 0x22, 0 - .dw 0x061b, 0xc608, 0x061b, 0xc608, 0x22, 0 - .dw 0x0624, 0xc608, 0x0624, 0xc608, 0x22, 0 - .dw 0x062d, 0xc608, 0x062d, 0xc608, 0x22, 0 - .dw 0x0636, 0xc608, 0x0636, 0xc608, 0x22, 0 - .dw 0x063f, 0xc608, 0x063f, 0xc608, 0x22, 0 - .dw 0x0640, 0xc608, 0x07ff, 0xc608, 0x21, 0 - .dw 0x0800, 0xc608, 0x0800, 0xc608, 0x22, 0 - .dw 0x0809, 0xc608, 0x0809, 0xc608, 0x22, 0 - .dw 0x0812, 0xc608, 0x0812, 0xc608, 0x22, 0 - .dw 0x081b, 0xc608, 0x081b, 0xc608, 0x22, 0 - .dw 0x0824, 0xc608, 0x0824, 0xc608, 0x22, 0 - .dw 0x082d, 0xc608, 0x082d, 0xc608, 0x22, 0 - .dw 0x0836, 0xc608, 0x0836, 0xc608, 0x22, 0 - .dw 0x083f, 0xc608, 0x083f, 0xc608, 0x22, 0 - .dw 0x0840, 0xc608, 0x09ff, 0xc608, 0x21, 0 - .dw 0x0a00, 0xc608, 0x0a00, 0xc608, 0x22, 0 - .dw 0x0a09, 0xc608, 0x0a09, 0xc608, 0x22, 0 - .dw 0x0a12, 0xc608, 0x0a12, 0xc608, 0x22, 0 - .dw 0x0a1b, 0xc608, 0x0a1b, 0xc608, 0x22, 0 - .dw 0x0a24, 0xc608, 0x0a24, 0xc608, 0x22, 0 - .dw 0x0a2d, 0xc608, 0x0a2d, 0xc608, 0x22, 0 - .dw 0x0a36, 0xc608, 0x0a36, 0xc608, 0x22, 0 - .dw 0x0a3f, 0xc608, 0x0a3f, 0xc608, 0x22, 0 - .dw 0x0a40, 0xc608, 0x0bff, 0xc608, 0x21, 0 - .dw 0x0c00, 0xc608, 0x0c00, 0xc608, 0x22, 0 - .dw 0x0c09, 0xc608, 0x0c09, 0xc608, 0x22, 0 - .dw 0x0c12, 0xc608, 0x0c12, 0xc608, 0x22, 0 - .dw 0x0c1b, 0xc608, 0x0c1b, 0xc608, 0x22, 0 - .dw 0x0c24, 0xc608, 0x0c24, 0xc608, 0x22, 0 - .dw 0x0c2d, 0xc608, 0x0c2d, 0xc608, 0x22, 0 - .dw 0x0c36, 0xc608, 0x0c36, 0xc608, 0x22, 0 - .dw 0x0c3f, 0xc608, 0x0c3f, 0xc608, 0x22, 0 - .dw 0x0c40, 0xc608, 0x0dff, 0xc608, 0x21, 0 - .dw 0x0e00, 0xc608, 0x0e00, 0xc608, 0x22, 0 - .dw 0x0e09, 0xc608, 0x0e09, 0xc608, 0x22, 0 - .dw 0x0e12, 0xc608, 0x0e12, 0xc608, 0x22, 0 - .dw 0x0e1b, 0xc608, 0x0e1b, 0xc608, 0x22, 0 - .dw 0x0e24, 0xc608, 0x0e24, 0xc608, 0x22, 0 - .dw 0x0e2d, 0xc608, 0x0e2d, 0xc608, 0x22, 0 - .dw 0x0e36, 0xc608, 0x0e36, 0xc608, 0x22, 0 - .dw 0x0e3f, 0xc608, 0x0e3f, 0xc608, 0x22, 0 - .dw 0x0e40, 0xc608, 0x3fff, 0xc608, 0x21, 0 - .dw 0x4000, 0xc608, 0x4000, 0xc608, 0x22, 0 - .dw 0x4009, 0xc608, 0x4009, 0xc608, 0x22, 0 - .dw 0x4012, 0xc608, 0x4012, 0xc608, 0x22, 0 - .dw 0x401b, 0xc608, 0x401b, 0xc608, 0x22, 0 - .dw 0x4024, 0xc608, 0x4024, 0xc608, 0x22, 0 - .dw 0x402d, 0xc608, 0x402d, 0xc608, 0x22, 0 - .dw 0x4036, 0xc608, 0x4036, 0xc608, 0x22, 0 - .dw 0x403f, 0xc608, 0x403f, 0xc608, 0x22, 0 - .dw 0x4040, 0xc608, 0x41ff, 0xc608, 0x21, 0 - .dw 0x4200, 0xc608, 0x4200, 0xc608, 0x22, 0 - .dw 0x4209, 0xc608, 0x4209, 0xc608, 0x22, 0 - .dw 0x4212, 0xc608, 0x4212, 0xc608, 0x22, 0 - .dw 0x421b, 0xc608, 0x421b, 0xc608, 0x22, 0 - .dw 0x4224, 0xc608, 0x4224, 0xc608, 0x22, 0 - .dw 0x422d, 0xc608, 0x422d, 0xc608, 0x22, 0 - .dw 0x4236, 0xc608, 0x4236, 0xc608, 0x22, 0 - .dw 0x423f, 0xc608, 0x423f, 0xc608, 0x22, 0 - .dw 0x4240, 0xc608, 0x43ff, 0xc608, 0x21, 0 - .dw 0x4400, 0xc608, 0x4400, 0xc608, 0x22, 0 - .dw 0x4409, 0xc608, 0x4409, 0xc608, 0x22, 0 - .dw 0x4412, 0xc608, 0x4412, 0xc608, 0x22, 0 - .dw 0x441b, 0xc608, 0x441b, 0xc608, 0x22, 0 - .dw 0x4424, 0xc608, 0x4424, 0xc608, 0x22, 0 - .dw 0x442d, 0xc608, 0x442d, 0xc608, 0x22, 0 - .dw 0x4436, 0xc608, 0x4436, 0xc608, 0x22, 0 - .dw 0x443f, 0xc608, 0x443f, 0xc608, 0x22, 0 - .dw 0x4440, 0xc608, 0x45ff, 0xc608, 0x21, 0 - .dw 0x4600, 0xc608, 0x4600, 0xc608, 0x22, 0 - .dw 0x4609, 0xc608, 0x4609, 0xc608, 0x22, 0 - .dw 0x4612, 0xc608, 0x4612, 0xc608, 0x22, 0 - .dw 0x461b, 0xc608, 0x461b, 0xc608, 0x22, 0 - .dw 0x4624, 0xc608, 0x4624, 0xc608, 0x22, 0 - .dw 0x462d, 0xc608, 0x462d, 0xc608, 0x22, 0 - .dw 0x4636, 0xc608, 0x4636, 0xc608, 0x22, 0 - .dw 0x463f, 0xc608, 0x463f, 0xc608, 0x22, 0 - .dw 0x4640, 0xc608, 0x47ff, 0xc608, 0x21, 0 - .dw 0x4800, 0xc608, 0x4800, 0xc608, 0x22, 0 - .dw 0x4809, 0xc608, 0x4809, 0xc608, 0x22, 0 - .dw 0x4812, 0xc608, 0x4812, 0xc608, 0x22, 0 - .dw 0x481b, 0xc608, 0x481b, 0xc608, 0x22, 0 - .dw 0x4824, 0xc608, 0x4824, 0xc608, 0x22, 0 - .dw 0x482d, 0xc608, 0x482d, 0xc608, 0x22, 0 - .dw 0x4836, 0xc608, 0x4836, 0xc608, 0x22, 0 - .dw 0x483f, 0xc608, 0x483f, 0xc608, 0x22, 0 - .dw 0x4840, 0xc608, 0x49ff, 0xc608, 0x21, 0 - .dw 0x4a00, 0xc608, 0x4a00, 0xc608, 0x22, 0 - .dw 0x4a09, 0xc608, 0x4a09, 0xc608, 0x22, 0 - .dw 0x4a12, 0xc608, 0x4a12, 0xc608, 0x22, 0 - .dw 0x4a1b, 0xc608, 0x4a1b, 0xc608, 0x22, 0 - .dw 0x4a24, 0xc608, 0x4a24, 0xc608, 0x22, 0 - .dw 0x4a2d, 0xc608, 0x4a2d, 0xc608, 0x22, 0 - .dw 0x4a36, 0xc608, 0x4a36, 0xc608, 0x22, 0 - .dw 0x4a3f, 0xc608, 0x4a3f, 0xc608, 0x22, 0 - .dw 0x4a40, 0xc608, 0x4bff, 0xc608, 0x21, 0 - .dw 0x4c00, 0xc608, 0x4c00, 0xc608, 0x22, 0 - .dw 0x4c09, 0xc608, 0x4c09, 0xc608, 0x22, 0 - .dw 0x4c12, 0xc608, 0x4c12, 0xc608, 0x22, 0 - .dw 0x4c1b, 0xc608, 0x4c1b, 0xc608, 0x22, 0 - .dw 0x4c24, 0xc608, 0x4c24, 0xc608, 0x22, 0 - .dw 0x4c2d, 0xc608, 0x4c2d, 0xc608, 0x22, 0 - .dw 0x4c36, 0xc608, 0x4c36, 0xc608, 0x22, 0 - .dw 0x4c3f, 0xc608, 0x4c3f, 0xc608, 0x22, 0 - .dw 0x4c40, 0xc608, 0x4dff, 0xc608, 0x21, 0 - .dw 0x4e00, 0xc608, 0x4e00, 0xc608, 0x22, 0 - .dw 0x4e09, 0xc608, 0x4e09, 0xc608, 0x22, 0 - .dw 0x4e12, 0xc608, 0x4e12, 0xc608, 0x22, 0 - .dw 0x4e1b, 0xc608, 0x4e1b, 0xc608, 0x22, 0 - .dw 0x4e24, 0xc608, 0x4e24, 0xc608, 0x22, 0 - .dw 0x4e2d, 0xc608, 0x4e2d, 0xc608, 0x22, 0 - .dw 0x4e36, 0xc608, 0x4e36, 0xc608, 0x22, 0 - .dw 0x4e3f, 0xc608, 0x4e3f, 0xc608, 0x22, 0 - .dw 0x4e40, 0xc608, 0xffff, 0xc608, 0x21, 0 - .dw 0x0040, 0xc609, 0x01ff, 0xc609, 0x21, 0 - .dw 0x0240, 0xc609, 0x03ff, 0xc609, 0x21, 0 - .dw 0x0440, 0xc609, 0x05ff, 0xc609, 0x21, 0 - .dw 0x0640, 0xc609, 0x07ff, 0xc609, 0x21, 0 - .dw 0x0840, 0xc609, 0x09ff, 0xc609, 0x21, 0 - .dw 0x0a40, 0xc609, 0x0bff, 0xc609, 0x21, 0 - .dw 0x0c40, 0xc609, 0x0dff, 0xc609, 0x21, 0 - .dw 0x0e40, 0xc609, 0x3fff, 0xc609, 0x21, 0 - .dw 0x4040, 0xc609, 0x41ff, 0xc609, 0x21, 0 - .dw 0x4240, 0xc609, 0x43ff, 0xc609, 0x21, 0 - .dw 0x4440, 0xc609, 0x45ff, 0xc609, 0x21, 0 - .dw 0x4640, 0xc609, 0x47ff, 0xc609, 0x21, 0 - .dw 0x4840, 0xc609, 0x49ff, 0xc609, 0x21, 0 - .dw 0x4a40, 0xc609, 0x4bff, 0xc609, 0x21, 0 - .dw 0x4c40, 0xc609, 0x4dff, 0xc609, 0x21, 0 - .dw 0x4e40, 0xc609, 0x7fff, 0xc609, 0x21, 0 - .dw 0x8040, 0xc609, 0x81ff, 0xc609, 0x21, 0 - .dw 0x8240, 0xc609, 0x83ff, 0xc609, 0x21, 0 - .dw 0x8440, 0xc609, 0x85ff, 0xc609, 0x21, 0 - .dw 0x8640, 0xc609, 0x87ff, 0xc609, 0x21, 0 - .dw 0x8840, 0xc609, 0x89ff, 0xc609, 0x21, 0 - .dw 0x8a40, 0xc609, 0x8bff, 0xc609, 0x21, 0 - .dw 0x8c40, 0xc609, 0x8dff, 0xc609, 0x21, 0 - .dw 0x8e40, 0xc609, 0xbfff, 0xc609, 0x21, 0 - .dw 0xc040, 0xc609, 0xc1ff, 0xc609, 0x21, 0 - .dw 0xc240, 0xc609, 0xc3ff, 0xc609, 0x21, 0 - .dw 0xc440, 0xc609, 0xc5ff, 0xc609, 0x21, 0 - .dw 0xc640, 0xc609, 0xc7ff, 0xc609, 0x21, 0 - .dw 0xc840, 0xc609, 0xc9ff, 0xc609, 0x21, 0 - .dw 0xca40, 0xc609, 0xcbff, 0xc609, 0x21, 0 - .dw 0xcc40, 0xc609, 0xcdff, 0xc609, 0x21, 0 - .dw 0xce40, 0xc609, 0xffff, 0xc609, 0x21, 0 - .dw 0x0040, 0xc60a, 0x01ff, 0xc60a, 0x21, 0 - .dw 0x0240, 0xc60a, 0x03ff, 0xc60a, 0x21, 0 - .dw 0x0440, 0xc60a, 0x05ff, 0xc60a, 0x21, 0 - .dw 0x0640, 0xc60a, 0x07ff, 0xc60a, 0x21, 0 - .dw 0x0840, 0xc60a, 0x09ff, 0xc60a, 0x21, 0 - .dw 0x0a40, 0xc60a, 0x0bff, 0xc60a, 0x21, 0 - .dw 0x0c40, 0xc60a, 0x0dff, 0xc60a, 0x21, 0 - .dw 0x0e40, 0xc60a, 0x3fff, 0xc60a, 0x21, 0 - .dw 0x4040, 0xc60a, 0x41ff, 0xc60a, 0x21, 0 - .dw 0x4240, 0xc60a, 0x43ff, 0xc60a, 0x21, 0 - .dw 0x4440, 0xc60a, 0x45ff, 0xc60a, 0x21, 0 - .dw 0x4640, 0xc60a, 0x47ff, 0xc60a, 0x21, 0 - .dw 0x4840, 0xc60a, 0x49ff, 0xc60a, 0x21, 0 - .dw 0x4a40, 0xc60a, 0x4bff, 0xc60a, 0x21, 0 - .dw 0x4c40, 0xc60a, 0x4dff, 0xc60a, 0x21, 0 - .dw 0x4e40, 0xc60a, 0x7fff, 0xc60a, 0x21, 0 - .dw 0x8040, 0xc60a, 0x81ff, 0xc60a, 0x21, 0 - .dw 0x8240, 0xc60a, 0x83ff, 0xc60a, 0x21, 0 - .dw 0x8440, 0xc60a, 0x85ff, 0xc60a, 0x21, 0 - .dw 0x8640, 0xc60a, 0x87ff, 0xc60a, 0x21, 0 - .dw 0x8840, 0xc60a, 0x89ff, 0xc60a, 0x21, 0 - .dw 0x8a40, 0xc60a, 0x8bff, 0xc60a, 0x21, 0 - .dw 0x8c40, 0xc60a, 0x8dff, 0xc60a, 0x21, 0 - .dw 0x8e40, 0xc60a, 0xbfff, 0xc60a, 0x21, 0 - .dw 0xc040, 0xc60a, 0xc1ff, 0xc60a, 0x21, 0 - .dw 0xc240, 0xc60a, 0xc3ff, 0xc60a, 0x21, 0 - .dw 0xc440, 0xc60a, 0xc5ff, 0xc60a, 0x21, 0 - .dw 0xc640, 0xc60a, 0xc7ff, 0xc60a, 0x21, 0 - .dw 0xc840, 0xc60a, 0xc9ff, 0xc60a, 0x21, 0 - .dw 0xca40, 0xc60a, 0xcbff, 0xc60a, 0x21, 0 - .dw 0xcc40, 0xc60a, 0xcdff, 0xc60a, 0x21, 0 - .dw 0xce40, 0xc60a, 0xffff, 0xc60a, 0x21, 0 - .dw 0x0040, 0xc60b, 0x01ff, 0xc60b, 0x21, 0 - .dw 0x0240, 0xc60b, 0x03ff, 0xc60b, 0x21, 0 - .dw 0x0440, 0xc60b, 0x05ff, 0xc60b, 0x21, 0 - .dw 0x0640, 0xc60b, 0x07ff, 0xc60b, 0x21, 0 - .dw 0x0840, 0xc60b, 0x09ff, 0xc60b, 0x21, 0 - .dw 0x0a40, 0xc60b, 0x0bff, 0xc60b, 0x21, 0 - .dw 0x0c40, 0xc60b, 0x0dff, 0xc60b, 0x21, 0 - .dw 0x0e40, 0xc60b, 0x3fff, 0xc60b, 0x21, 0 - .dw 0x4040, 0xc60b, 0x41ff, 0xc60b, 0x21, 0 - .dw 0x4240, 0xc60b, 0x43ff, 0xc60b, 0x21, 0 - .dw 0x4440, 0xc60b, 0x45ff, 0xc60b, 0x21, 0 - .dw 0x4640, 0xc60b, 0x47ff, 0xc60b, 0x21, 0 - .dw 0x4840, 0xc60b, 0x49ff, 0xc60b, 0x21, 0 - .dw 0x4a40, 0xc60b, 0x4bff, 0xc60b, 0x21, 0 - .dw 0x4c40, 0xc60b, 0x4dff, 0xc60b, 0x21, 0 - .dw 0x4e40, 0xc60b, 0xffff, 0xc60b, 0x21, 0 - .dw 0x0040, 0xc60c, 0x01ff, 0xc60c, 0x21, 0 - .dw 0x0240, 0xc60c, 0x03ff, 0xc60c, 0x21, 0 - .dw 0x0440, 0xc60c, 0x05ff, 0xc60c, 0x21, 0 - .dw 0x0640, 0xc60c, 0x07ff, 0xc60c, 0x21, 0 - .dw 0x0840, 0xc60c, 0x09ff, 0xc60c, 0x21, 0 - .dw 0x0a40, 0xc60c, 0x0bff, 0xc60c, 0x21, 0 - .dw 0x0c40, 0xc60c, 0x0dff, 0xc60c, 0x21, 0 - .dw 0x0e40, 0xc60c, 0x3fff, 0xc60c, 0x21, 0 - .dw 0x4040, 0xc60c, 0x41ff, 0xc60c, 0x21, 0 - .dw 0x4240, 0xc60c, 0x43ff, 0xc60c, 0x21, 0 - .dw 0x4440, 0xc60c, 0x45ff, 0xc60c, 0x21, 0 - .dw 0x4640, 0xc60c, 0x47ff, 0xc60c, 0x21, 0 - .dw 0x4840, 0xc60c, 0x49ff, 0xc60c, 0x21, 0 - .dw 0x4a40, 0xc60c, 0x4bff, 0xc60c, 0x21, 0 - .dw 0x4c40, 0xc60c, 0x4dff, 0xc60c, 0x21, 0 - .dw 0x4e40, 0xc60c, 0xffff, 0xc60c, 0x21, 0 - .dw 0x0040, 0xc60d, 0x01ff, 0xc60d, 0x21, 0 - .dw 0x0240, 0xc60d, 0x03ff, 0xc60d, 0x21, 0 - .dw 0x0440, 0xc60d, 0x05ff, 0xc60d, 0x21, 0 - .dw 0x0640, 0xc60d, 0x07ff, 0xc60d, 0x21, 0 - .dw 0x0840, 0xc60d, 0x09ff, 0xc60d, 0x21, 0 - .dw 0x0a40, 0xc60d, 0x0bff, 0xc60d, 0x21, 0 - .dw 0x0c40, 0xc60d, 0x0dff, 0xc60d, 0x21, 0 - .dw 0x0e40, 0xc60d, 0x3fff, 0xc60d, 0x21, 0 - .dw 0x4040, 0xc60d, 0x41ff, 0xc60d, 0x21, 0 - .dw 0x4240, 0xc60d, 0x43ff, 0xc60d, 0x21, 0 - .dw 0x4440, 0xc60d, 0x45ff, 0xc60d, 0x21, 0 - .dw 0x4640, 0xc60d, 0x47ff, 0xc60d, 0x21, 0 - .dw 0x4840, 0xc60d, 0x49ff, 0xc60d, 0x21, 0 - .dw 0x4a40, 0xc60d, 0x4bff, 0xc60d, 0x21, 0 - .dw 0x4c40, 0xc60d, 0x4dff, 0xc60d, 0x21, 0 - .dw 0x4e40, 0xc60d, 0x7fff, 0xc60d, 0x21, 0 - .dw 0x8040, 0xc60d, 0x81ff, 0xc60d, 0x21, 0 - .dw 0x8240, 0xc60d, 0x83ff, 0xc60d, 0x21, 0 - .dw 0x8440, 0xc60d, 0x85ff, 0xc60d, 0x21, 0 - .dw 0x8640, 0xc60d, 0x87ff, 0xc60d, 0x21, 0 - .dw 0x8840, 0xc60d, 0x89ff, 0xc60d, 0x21, 0 - .dw 0x8a40, 0xc60d, 0x8bff, 0xc60d, 0x21, 0 - .dw 0x8c40, 0xc60d, 0x8dff, 0xc60d, 0x21, 0 - .dw 0x8e40, 0xc60d, 0xffff, 0xc67f, 0x21, 0 - .dw 0xc000, 0xc680, 0xffff, 0xc680, 0x21, 0 - .dw 0x1000, 0xc681, 0x3fff, 0xc681, 0x21, 0 - .dw 0x5000, 0xc681, 0x7fff, 0xc681, 0x21, 0 - .dw 0x9000, 0xc681, 0xffff, 0xc681, 0x21, 0 - .dw 0x1000, 0xc682, 0x3fff, 0xc682, 0x21, 0 - .dw 0x5000, 0xc682, 0x7fff, 0xc682, 0x21, 0 - .dw 0x9000, 0xc682, 0xbfff, 0xc682, 0x21, 0 - .dw 0xd000, 0xc682, 0xffff, 0xc682, 0x21, 0 - .dw 0x2000, 0xc683, 0x3fff, 0xc683, 0x21, 0 - .dw 0x6000, 0xc683, 0x7fff, 0xc683, 0x21, 0 - .dw 0xa000, 0xc683, 0xffff, 0xe07f, 0x21, 0 - .dw 0x0400, 0xe080, 0x0fff, 0xe080, 0x21, 0 - .dw 0x1400, 0xe080, 0x1fff, 0xe080, 0x21, 0 - .dw 0x2400, 0xe080, 0x2fff, 0xe080, 0x21, 0 - .dw 0x3400, 0xe080, 0x3fff, 0xe080, 0x21, 0 - .dw 0x4400, 0xe080, 0x4fff, 0xe080, 0x21, 0 - .dw 0x5400, 0xe080, 0x5fff, 0xe080, 0x21, 0 - .dw 0x6400, 0xe080, 0x6fff, 0xe080, 0x21, 0 - .dw 0x7400, 0xe080, 0xffff, 0xe080, 0x21, 0 - .dw 0x0400, 0xe081, 0x0fff, 0xe081, 0x21, 0 - .dw 0x1400, 0xe081, 0x1fff, 0xe081, 0x21, 0 - .dw 0x2400, 0xe081, 0x2fff, 0xe081, 0x21, 0 - .dw 0x3400, 0xe081, 0x3fff, 0xe081, 0x21, 0 - .dw 0x4400, 0xe081, 0x4fff, 0xe081, 0x21, 0 - .dw 0x5400, 0xe081, 0x5fff, 0xe081, 0x21, 0 - .dw 0x6400, 0xe081, 0x6fff, 0xe081, 0x21, 0 - .dw 0x7400, 0xe081, 0xffff, 0xe081, 0x21, 0 - .dw 0x0400, 0xe082, 0x0fff, 0xe082, 0x21, 0 - .dw 0x1400, 0xe082, 0x1fff, 0xe082, 0x21, 0 - .dw 0x2400, 0xe082, 0x2fff, 0xe082, 0x21, 0 - .dw 0x3400, 0xe082, 0x3fff, 0xe082, 0x21, 0 - .dw 0x4400, 0xe082, 0x4fff, 0xe082, 0x21, 0 - .dw 0x5400, 0xe082, 0x5fff, 0xe082, 0x21, 0 - .dw 0x6400, 0xe082, 0x6fff, 0xe082, 0x21, 0 - .dw 0x7400, 0xe082, 0xffff, 0xe082, 0x21, 0 - .dw 0x0400, 0xe083, 0x0fff, 0xe083, 0x21, 0 - .dw 0x1400, 0xe083, 0x1fff, 0xe083, 0x21, 0 - .dw 0x2400, 0xe083, 0x2fff, 0xe083, 0x21, 0 - .dw 0x3400, 0xe083, 0x3fff, 0xe083, 0x21, 0 - .dw 0x4400, 0xe083, 0x4fff, 0xe083, 0x21, 0 - .dw 0x5400, 0xe083, 0x5fff, 0xe083, 0x21, 0 - .dw 0x6400, 0xe083, 0x6fff, 0xe083, 0x21, 0 - .dw 0x7400, 0xe083, 0xffff, 0xe083, 0x21, 0 - .dw 0x0400, 0xe084, 0x0fff, 0xe084, 0x21, 0 - .dw 0x1400, 0xe084, 0x1fff, 0xe084, 0x21, 0 - .dw 0x2400, 0xe084, 0x2fff, 0xe084, 0x21, 0 - .dw 0x3400, 0xe084, 0x3fff, 0xe084, 0x21, 0 - .dw 0x4400, 0xe084, 0x4fff, 0xe084, 0x21, 0 - .dw 0x5400, 0xe084, 0x5fff, 0xe084, 0x21, 0 - .dw 0x6400, 0xe084, 0x6fff, 0xe084, 0x21, 0 - .dw 0x7400, 0xe084, 0xffff, 0xe084, 0x21, 0 - .dw 0x0400, 0xe085, 0x0fff, 0xe085, 0x21, 0 - .dw 0x1400, 0xe085, 0x1fff, 0xe085, 0x21, 0 - .dw 0x2400, 0xe085, 0x2fff, 0xe085, 0x21, 0 - .dw 0x3400, 0xe085, 0x3fff, 0xe085, 0x21, 0 - .dw 0x4400, 0xe085, 0x4fff, 0xe085, 0x21, 0 - .dw 0x5400, 0xe085, 0x5fff, 0xe085, 0x21, 0 - .dw 0x6400, 0xe085, 0x6fff, 0xe085, 0x21, 0 - .dw 0x7400, 0xe085, 0xffff, 0xe085, 0x21, 0 - .dw 0x0400, 0xe086, 0x0fff, 0xe086, 0x21, 0 - .dw 0x1400, 0xe086, 0x1fff, 0xe086, 0x21, 0 - .dw 0x2400, 0xe086, 0x2fff, 0xe086, 0x21, 0 - .dw 0x3400, 0xe086, 0x3fff, 0xe086, 0x21, 0 - .dw 0x4400, 0xe086, 0x4fff, 0xe086, 0x21, 0 - .dw 0x5400, 0xe086, 0x5fff, 0xe086, 0x21, 0 - .dw 0x6400, 0xe086, 0x6fff, 0xe086, 0x21, 0 - .dw 0x7400, 0xe086, 0xffff, 0xe086, 0x21, 0 - .dw 0x0400, 0xe087, 0x0fff, 0xe087, 0x21, 0 - .dw 0x1400, 0xe087, 0x1fff, 0xe087, 0x21, 0 - .dw 0x2400, 0xe087, 0x2fff, 0xe087, 0x21, 0 - .dw 0x3400, 0xe087, 0x3fff, 0xe087, 0x21, 0 - .dw 0x4400, 0xe087, 0x4fff, 0xe087, 0x21, 0 - .dw 0x5400, 0xe087, 0x5fff, 0xe087, 0x21, 0 - .dw 0x6400, 0xe087, 0x6fff, 0xe087, 0x21, 0 - .dw 0x7400, 0xe087, 0xffff, 0xe087, 0x21, 0 - .dw 0x0400, 0xe088, 0x0fff, 0xe088, 0x21, 0 - .dw 0x1400, 0xe088, 0x1fff, 0xe088, 0x21, 0 - .dw 0x2400, 0xe088, 0x2fff, 0xe088, 0x21, 0 - .dw 0x3400, 0xe088, 0x3fff, 0xe088, 0x21, 0 - .dw 0x4400, 0xe088, 0x4fff, 0xe088, 0x21, 0 - .dw 0x5400, 0xe088, 0x5fff, 0xe088, 0x21, 0 - .dw 0x6400, 0xe088, 0x6fff, 0xe088, 0x21, 0 - .dw 0x7400, 0xe088, 0xffff, 0xe088, 0x21, 0 - .dw 0x0400, 0xe089, 0x0fff, 0xe089, 0x21, 0 - .dw 0x1400, 0xe089, 0x1fff, 0xe089, 0x21, 0 - .dw 0x2400, 0xe089, 0x2fff, 0xe089, 0x21, 0 - .dw 0x3400, 0xe089, 0x3fff, 0xe089, 0x21, 0 - .dw 0x4400, 0xe089, 0x4fff, 0xe089, 0x21, 0 - .dw 0x5400, 0xe089, 0x5fff, 0xe089, 0x21, 0 - .dw 0x6400, 0xe089, 0x6fff, 0xe089, 0x21, 0 - .dw 0x7400, 0xe089, 0xffff, 0xe089, 0x21, 0 - .dw 0x0400, 0xe08a, 0x0fff, 0xe08a, 0x21, 0 - .dw 0x1400, 0xe08a, 0x1fff, 0xe08a, 0x21, 0 - .dw 0x2400, 0xe08a, 0x2fff, 0xe08a, 0x21, 0 - .dw 0x3400, 0xe08a, 0x3fff, 0xe08a, 0x21, 0 - .dw 0x4400, 0xe08a, 0x4fff, 0xe08a, 0x21, 0 - .dw 0x5400, 0xe08a, 0x5fff, 0xe08a, 0x21, 0 - .dw 0x6400, 0xe08a, 0x6fff, 0xe08a, 0x21, 0 - .dw 0x7400, 0xe08a, 0xffff, 0xe08a, 0x21, 0 - .dw 0x0400, 0xe08b, 0x0fff, 0xe08b, 0x21, 0 - .dw 0x1400, 0xe08b, 0x1fff, 0xe08b, 0x21, 0 - .dw 0x2400, 0xe08b, 0x2fff, 0xe08b, 0x21, 0 - .dw 0x3400, 0xe08b, 0x3fff, 0xe08b, 0x21, 0 - .dw 0x4400, 0xe08b, 0x4fff, 0xe08b, 0x21, 0 - .dw 0x5400, 0xe08b, 0x5fff, 0xe08b, 0x21, 0 - .dw 0x6400, 0xe08b, 0x6fff, 0xe08b, 0x21, 0 - .dw 0x7400, 0xe08b, 0xffff, 0xe08b, 0x21, 0 - .dw 0x0400, 0xe08c, 0x0fff, 0xe08c, 0x21, 0 - .dw 0x1400, 0xe08c, 0x1fff, 0xe08c, 0x21, 0 - .dw 0x2400, 0xe08c, 0x2fff, 0xe08c, 0x21, 0 - .dw 0x3400, 0xe08c, 0x3fff, 0xe08c, 0x21, 0 - .dw 0x4400, 0xe08c, 0x4fff, 0xe08c, 0x21, 0 - .dw 0x5400, 0xe08c, 0x5fff, 0xe08c, 0x21, 0 - .dw 0x6400, 0xe08c, 0x6fff, 0xe08c, 0x21, 0 - .dw 0x7400, 0xe08c, 0xffff, 0xe08c, 0x21, 0 - .dw 0x0400, 0xe08d, 0x0fff, 0xe08d, 0x21, 0 - .dw 0x1400, 0xe08d, 0x1fff, 0xe08d, 0x21, 0 - .dw 0x2400, 0xe08d, 0x2fff, 0xe08d, 0x21, 0 - .dw 0x3400, 0xe08d, 0x3fff, 0xe08d, 0x21, 0 - .dw 0x4400, 0xe08d, 0x4fff, 0xe08d, 0x21, 0 - .dw 0x5400, 0xe08d, 0x5fff, 0xe08d, 0x21, 0 - .dw 0x6400, 0xe08d, 0x6fff, 0xe08d, 0x21, 0 - .dw 0x7400, 0xe08d, 0xffff, 0xe08d, 0x21, 0 - .dw 0x0400, 0xe08e, 0x0fff, 0xe08e, 0x21, 0 - .dw 0x1400, 0xe08e, 0x1fff, 0xe08e, 0x21, 0 - .dw 0x2400, 0xe08e, 0x2fff, 0xe08e, 0x21, 0 - .dw 0x3400, 0xe08e, 0x3fff, 0xe08e, 0x21, 0 - .dw 0x4400, 0xe08e, 0x4fff, 0xe08e, 0x21, 0 - .dw 0x5400, 0xe08e, 0x5fff, 0xe08e, 0x21, 0 - .dw 0x6400, 0xe08e, 0x6fff, 0xe08e, 0x21, 0 - .dw 0x7400, 0xe08e, 0xffff, 0xe08e, 0x21, 0 - .dw 0x0400, 0xe08f, 0x0fff, 0xe08f, 0x21, 0 - .dw 0x1400, 0xe08f, 0x1fff, 0xe08f, 0x21, 0 - .dw 0x2400, 0xe08f, 0x2fff, 0xe08f, 0x21, 0 - .dw 0x3400, 0xe08f, 0x3fff, 0xe08f, 0x21, 0 - .dw 0x4400, 0xe08f, 0x4fff, 0xe08f, 0x21, 0 - .dw 0x5400, 0xe08f, 0x5fff, 0xe08f, 0x21, 0 - .dw 0x6400, 0xe08f, 0x6fff, 0xe08f, 0x21, 0 - .dw 0x7400, 0xe08f, 0xffff, 0xe08f, 0x21, 0 - .dw 0x0400, 0xe090, 0x0fff, 0xe090, 0x21, 0 - .dw 0x1400, 0xe090, 0x1fff, 0xe090, 0x21, 0 - .dw 0x2400, 0xe090, 0x2fff, 0xe090, 0x21, 0 - .dw 0x3400, 0xe090, 0x3fff, 0xe090, 0x21, 0 - .dw 0x4400, 0xe090, 0x4fff, 0xe090, 0x21, 0 - .dw 0x5400, 0xe090, 0x5fff, 0xe090, 0x21, 0 - .dw 0x6400, 0xe090, 0x6fff, 0xe090, 0x21, 0 - .dw 0x7400, 0xe090, 0xffff, 0xe090, 0x21, 0 - .dw 0x0400, 0xe091, 0x0fff, 0xe091, 0x21, 0 - .dw 0x1400, 0xe091, 0x1fff, 0xe091, 0x21, 0 - .dw 0x2400, 0xe091, 0x2fff, 0xe091, 0x21, 0 - .dw 0x3400, 0xe091, 0x3fff, 0xe091, 0x21, 0 - .dw 0x4400, 0xe091, 0x4fff, 0xe091, 0x21, 0 - .dw 0x5400, 0xe091, 0x5fff, 0xe091, 0x21, 0 - .dw 0x6400, 0xe091, 0x6fff, 0xe091, 0x21, 0 - .dw 0x7400, 0xe091, 0xffff, 0xe091, 0x21, 0 - .dw 0x0400, 0xe092, 0x0fff, 0xe092, 0x21, 0 - .dw 0x1400, 0xe092, 0x1fff, 0xe092, 0x21, 0 - .dw 0x2400, 0xe092, 0x2fff, 0xe092, 0x21, 0 - .dw 0x3400, 0xe092, 0x3fff, 0xe092, 0x21, 0 - .dw 0x4400, 0xe092, 0x4fff, 0xe092, 0x21, 0 - .dw 0x5400, 0xe092, 0x5fff, 0xe092, 0x21, 0 - .dw 0x6400, 0xe092, 0x6fff, 0xe092, 0x21, 0 - .dw 0x7400, 0xe092, 0xffff, 0xe092, 0x21, 0 - .dw 0x0400, 0xe093, 0x0fff, 0xe093, 0x21, 0 - .dw 0x1400, 0xe093, 0x1fff, 0xe093, 0x21, 0 - .dw 0x2400, 0xe093, 0x2fff, 0xe093, 0x21, 0 - .dw 0x3400, 0xe093, 0x3fff, 0xe093, 0x21, 0 - .dw 0x4400, 0xe093, 0x4fff, 0xe093, 0x21, 0 - .dw 0x5400, 0xe093, 0x5fff, 0xe093, 0x21, 0 - .dw 0x6400, 0xe093, 0x6fff, 0xe093, 0x21, 0 - .dw 0x7400, 0xe093, 0xffff, 0xe093, 0x21, 0 - .dw 0x0400, 0xe094, 0x0fff, 0xe094, 0x21, 0 - .dw 0x1400, 0xe094, 0x1fff, 0xe094, 0x21, 0 - .dw 0x2400, 0xe094, 0x2fff, 0xe094, 0x21, 0 - .dw 0x3400, 0xe094, 0x3fff, 0xe094, 0x21, 0 - .dw 0x4400, 0xe094, 0x4fff, 0xe094, 0x21, 0 - .dw 0x5400, 0xe094, 0x5fff, 0xe094, 0x21, 0 - .dw 0x6400, 0xe094, 0x6fff, 0xe094, 0x21, 0 - .dw 0x7400, 0xe094, 0xffff, 0xe094, 0x21, 0 - .dw 0x0400, 0xe095, 0x0fff, 0xe095, 0x21, 0 - .dw 0x1400, 0xe095, 0x1fff, 0xe095, 0x21, 0 - .dw 0x2400, 0xe095, 0x2fff, 0xe095, 0x21, 0 - .dw 0x3400, 0xe095, 0x3fff, 0xe095, 0x21, 0 - .dw 0x4400, 0xe095, 0x4fff, 0xe095, 0x21, 0 - .dw 0x5400, 0xe095, 0x5fff, 0xe095, 0x21, 0 - .dw 0x6400, 0xe095, 0x6fff, 0xe095, 0x21, 0 - .dw 0x7400, 0xe095, 0xffff, 0xe095, 0x21, 0 - .dw 0x0400, 0xe096, 0x0fff, 0xe096, 0x21, 0 - .dw 0x1400, 0xe096, 0x1fff, 0xe096, 0x21, 0 - .dw 0x2400, 0xe096, 0x2fff, 0xe096, 0x21, 0 - .dw 0x3400, 0xe096, 0x3fff, 0xe096, 0x21, 0 - .dw 0x4400, 0xe096, 0x4fff, 0xe096, 0x21, 0 - .dw 0x5400, 0xe096, 0x5fff, 0xe096, 0x21, 0 - .dw 0x6400, 0xe096, 0x6fff, 0xe096, 0x21, 0 - .dw 0x7400, 0xe096, 0xffff, 0xe096, 0x21, 0 - .dw 0x0400, 0xe097, 0x0fff, 0xe097, 0x21, 0 - .dw 0x1400, 0xe097, 0x1fff, 0xe097, 0x21, 0 - .dw 0x2400, 0xe097, 0x2fff, 0xe097, 0x21, 0 - .dw 0x3400, 0xe097, 0x3fff, 0xe097, 0x21, 0 - .dw 0x4400, 0xe097, 0x4fff, 0xe097, 0x21, 0 - .dw 0x5400, 0xe097, 0x5fff, 0xe097, 0x21, 0 - .dw 0x6400, 0xe097, 0x6fff, 0xe097, 0x21, 0 - .dw 0x7400, 0xe097, 0xffff, 0xe097, 0x21, 0 - .dw 0x0400, 0xe098, 0x0fff, 0xe098, 0x21, 0 - .dw 0x1400, 0xe098, 0x1fff, 0xe098, 0x21, 0 - .dw 0x2400, 0xe098, 0x2fff, 0xe098, 0x21, 0 - .dw 0x3400, 0xe098, 0x3fff, 0xe098, 0x21, 0 - .dw 0x4400, 0xe098, 0x4fff, 0xe098, 0x21, 0 - .dw 0x5400, 0xe098, 0x5fff, 0xe098, 0x21, 0 - .dw 0x6400, 0xe098, 0x6fff, 0xe098, 0x21, 0 - .dw 0x7400, 0xe098, 0xffff, 0xe098, 0x21, 0 - .dw 0x0400, 0xe099, 0x0fff, 0xe099, 0x21, 0 - .dw 0x1400, 0xe099, 0x1fff, 0xe099, 0x21, 0 - .dw 0x2400, 0xe099, 0x2fff, 0xe099, 0x21, 0 - .dw 0x3400, 0xe099, 0x3fff, 0xe099, 0x21, 0 - .dw 0x4400, 0xe099, 0x4fff, 0xe099, 0x21, 0 - .dw 0x5400, 0xe099, 0x5fff, 0xe099, 0x21, 0 - .dw 0x6400, 0xe099, 0x6fff, 0xe099, 0x21, 0 - .dw 0x7400, 0xe099, 0xffff, 0xe099, 0x21, 0 - .dw 0x0400, 0xe09a, 0x0fff, 0xe09a, 0x21, 0 - .dw 0x1400, 0xe09a, 0x1fff, 0xe09a, 0x21, 0 - .dw 0x2400, 0xe09a, 0x2fff, 0xe09a, 0x21, 0 - .dw 0x3400, 0xe09a, 0x3fff, 0xe09a, 0x21, 0 - .dw 0x4400, 0xe09a, 0x4fff, 0xe09a, 0x21, 0 - .dw 0x5400, 0xe09a, 0x5fff, 0xe09a, 0x21, 0 - .dw 0x6400, 0xe09a, 0x6fff, 0xe09a, 0x21, 0 - .dw 0x7400, 0xe09a, 0xffff, 0xe09a, 0x21, 0 - .dw 0x0400, 0xe09b, 0x0fff, 0xe09b, 0x21, 0 - .dw 0x1400, 0xe09b, 0x1fff, 0xe09b, 0x21, 0 - .dw 0x2400, 0xe09b, 0x2fff, 0xe09b, 0x21, 0 - .dw 0x3400, 0xe09b, 0x3fff, 0xe09b, 0x21, 0 - .dw 0x4400, 0xe09b, 0x4fff, 0xe09b, 0x21, 0 - .dw 0x5400, 0xe09b, 0x5fff, 0xe09b, 0x21, 0 - .dw 0x6400, 0xe09b, 0x6fff, 0xe09b, 0x21, 0 - .dw 0x7400, 0xe09b, 0xffff, 0xe09b, 0x21, 0 - .dw 0x0400, 0xe09c, 0x0fff, 0xe09c, 0x21, 0 - .dw 0x1400, 0xe09c, 0x1fff, 0xe09c, 0x21, 0 - .dw 0x2400, 0xe09c, 0x2fff, 0xe09c, 0x21, 0 - .dw 0x3400, 0xe09c, 0x3fff, 0xe09c, 0x21, 0 - .dw 0x4400, 0xe09c, 0x4fff, 0xe09c, 0x21, 0 - .dw 0x5400, 0xe09c, 0x5fff, 0xe09c, 0x21, 0 - .dw 0x6400, 0xe09c, 0x6fff, 0xe09c, 0x21, 0 - .dw 0x7400, 0xe09c, 0xffff, 0xe09c, 0x21, 0 - .dw 0x0400, 0xe09d, 0x0fff, 0xe09d, 0x21, 0 - .dw 0x1400, 0xe09d, 0x1fff, 0xe09d, 0x21, 0 - .dw 0x2400, 0xe09d, 0x2fff, 0xe09d, 0x21, 0 - .dw 0x3400, 0xe09d, 0x3fff, 0xe09d, 0x21, 0 - .dw 0x4400, 0xe09d, 0x4fff, 0xe09d, 0x21, 0 - .dw 0x5400, 0xe09d, 0x5fff, 0xe09d, 0x21, 0 - .dw 0x6400, 0xe09d, 0x6fff, 0xe09d, 0x21, 0 - .dw 0x7400, 0xe09d, 0xffff, 0xe09d, 0x21, 0 - .dw 0x0400, 0xe09e, 0x0fff, 0xe09e, 0x21, 0 - .dw 0x1400, 0xe09e, 0x1fff, 0xe09e, 0x21, 0 - .dw 0x2400, 0xe09e, 0x2fff, 0xe09e, 0x21, 0 - .dw 0x3400, 0xe09e, 0x3fff, 0xe09e, 0x21, 0 - .dw 0x4400, 0xe09e, 0x4fff, 0xe09e, 0x21, 0 - .dw 0x5400, 0xe09e, 0x5fff, 0xe09e, 0x21, 0 - .dw 0x6400, 0xe09e, 0x6fff, 0xe09e, 0x21, 0 - .dw 0x7400, 0xe09e, 0xffff, 0xe09e, 0x21, 0 - .dw 0x0400, 0xe09f, 0x0fff, 0xe09f, 0x21, 0 - .dw 0x1400, 0xe09f, 0x1fff, 0xe09f, 0x21, 0 - .dw 0x2400, 0xe09f, 0x2fff, 0xe09f, 0x21, 0 - .dw 0x3400, 0xe09f, 0x3fff, 0xe09f, 0x21, 0 - .dw 0x4400, 0xe09f, 0x4fff, 0xe09f, 0x21, 0 - .dw 0x5400, 0xe09f, 0x5fff, 0xe09f, 0x21, 0 - .dw 0x6400, 0xe09f, 0x6fff, 0xe09f, 0x21, 0 - .dw 0x7400, 0xe09f, 0xffff, 0xe09f, 0x21, 0 - .dw 0x0400, 0xe0a0, 0x0fff, 0xe0a0, 0x21, 0 - .dw 0x1400, 0xe0a0, 0x1fff, 0xe0a0, 0x21, 0 - .dw 0x2400, 0xe0a0, 0x2fff, 0xe0a0, 0x21, 0 - .dw 0x3400, 0xe0a0, 0x3fff, 0xe0a0, 0x21, 0 - .dw 0x4400, 0xe0a0, 0x4fff, 0xe0a0, 0x21, 0 - .dw 0x5400, 0xe0a0, 0x5fff, 0xe0a0, 0x21, 0 - .dw 0x6400, 0xe0a0, 0x6fff, 0xe0a0, 0x21, 0 - .dw 0x7400, 0xe0a0, 0xffff, 0xe0a0, 0x21, 0 - .dw 0x0400, 0xe0a1, 0x0fff, 0xe0a1, 0x21, 0 - .dw 0x1400, 0xe0a1, 0x1fff, 0xe0a1, 0x21, 0 - .dw 0x2400, 0xe0a1, 0x2fff, 0xe0a1, 0x21, 0 - .dw 0x3400, 0xe0a1, 0x3fff, 0xe0a1, 0x21, 0 - .dw 0x4400, 0xe0a1, 0x4fff, 0xe0a1, 0x21, 0 - .dw 0x5400, 0xe0a1, 0x5fff, 0xe0a1, 0x21, 0 - .dw 0x6400, 0xe0a1, 0x6fff, 0xe0a1, 0x21, 0 - .dw 0x7400, 0xe0a1, 0xffff, 0xe0a1, 0x21, 0 - .dw 0x0400, 0xe0a2, 0x0fff, 0xe0a2, 0x21, 0 - .dw 0x1400, 0xe0a2, 0x1fff, 0xe0a2, 0x21, 0 - .dw 0x2400, 0xe0a2, 0x2fff, 0xe0a2, 0x21, 0 - .dw 0x3400, 0xe0a2, 0x3fff, 0xe0a2, 0x21, 0 - .dw 0x4400, 0xe0a2, 0x4fff, 0xe0a2, 0x21, 0 - .dw 0x5400, 0xe0a2, 0x5fff, 0xe0a2, 0x21, 0 - .dw 0x6400, 0xe0a2, 0x6fff, 0xe0a2, 0x21, 0 - .dw 0x7400, 0xe0a2, 0xffff, 0xe0a2, 0x21, 0 - .dw 0x0400, 0xe0a3, 0x0fff, 0xe0a3, 0x21, 0 - .dw 0x1400, 0xe0a3, 0x1fff, 0xe0a3, 0x21, 0 - .dw 0x2400, 0xe0a3, 0x2fff, 0xe0a3, 0x21, 0 - .dw 0x3400, 0xe0a3, 0x3fff, 0xe0a3, 0x21, 0 - .dw 0x4400, 0xe0a3, 0x4fff, 0xe0a3, 0x21, 0 - .dw 0x5400, 0xe0a3, 0x5fff, 0xe0a3, 0x21, 0 - .dw 0x6400, 0xe0a3, 0x6fff, 0xe0a3, 0x21, 0 - .dw 0x7400, 0xe0a3, 0xffff, 0xe0a3, 0x21, 0 - .dw 0x0400, 0xe0a4, 0x0fff, 0xe0a4, 0x21, 0 - .dw 0x1400, 0xe0a4, 0x1fff, 0xe0a4, 0x21, 0 - .dw 0x2400, 0xe0a4, 0x2fff, 0xe0a4, 0x21, 0 - .dw 0x3400, 0xe0a4, 0x3fff, 0xe0a4, 0x21, 0 - .dw 0x4400, 0xe0a4, 0x4fff, 0xe0a4, 0x21, 0 - .dw 0x5400, 0xe0a4, 0x5fff, 0xe0a4, 0x21, 0 - .dw 0x6400, 0xe0a4, 0x6fff, 0xe0a4, 0x21, 0 - .dw 0x7400, 0xe0a4, 0xffff, 0xe0a4, 0x21, 0 - .dw 0x0400, 0xe0a5, 0x0fff, 0xe0a5, 0x21, 0 - .dw 0x1400, 0xe0a5, 0x1fff, 0xe0a5, 0x21, 0 - .dw 0x2400, 0xe0a5, 0x2fff, 0xe0a5, 0x21, 0 - .dw 0x3400, 0xe0a5, 0x3fff, 0xe0a5, 0x21, 0 - .dw 0x4400, 0xe0a5, 0x4fff, 0xe0a5, 0x21, 0 - .dw 0x5400, 0xe0a5, 0x5fff, 0xe0a5, 0x21, 0 - .dw 0x6400, 0xe0a5, 0x6fff, 0xe0a5, 0x21, 0 - .dw 0x7400, 0xe0a5, 0xffff, 0xe0a5, 0x21, 0 - .dw 0x0400, 0xe0a6, 0x0fff, 0xe0a6, 0x21, 0 - .dw 0x1400, 0xe0a6, 0x1fff, 0xe0a6, 0x21, 0 - .dw 0x2400, 0xe0a6, 0x2fff, 0xe0a6, 0x21, 0 - .dw 0x3400, 0xe0a6, 0x3fff, 0xe0a6, 0x21, 0 - .dw 0x4400, 0xe0a6, 0x4fff, 0xe0a6, 0x21, 0 - .dw 0x5400, 0xe0a6, 0x5fff, 0xe0a6, 0x21, 0 - .dw 0x6400, 0xe0a6, 0x6fff, 0xe0a6, 0x21, 0 - .dw 0x7400, 0xe0a6, 0xffff, 0xe0a6, 0x21, 0 - .dw 0x0400, 0xe0a7, 0x0fff, 0xe0a7, 0x21, 0 - .dw 0x1400, 0xe0a7, 0x1fff, 0xe0a7, 0x21, 0 - .dw 0x2400, 0xe0a7, 0x2fff, 0xe0a7, 0x21, 0 - .dw 0x3400, 0xe0a7, 0x3fff, 0xe0a7, 0x21, 0 - .dw 0x4400, 0xe0a7, 0x4fff, 0xe0a7, 0x21, 0 - .dw 0x5400, 0xe0a7, 0x5fff, 0xe0a7, 0x21, 0 - .dw 0x6400, 0xe0a7, 0x6fff, 0xe0a7, 0x21, 0 - .dw 0x7400, 0xe0a7, 0xffff, 0xe0a7, 0x21, 0 - .dw 0x0400, 0xe0a8, 0x0fff, 0xe0a8, 0x21, 0 - .dw 0x1400, 0xe0a8, 0x1fff, 0xe0a8, 0x21, 0 - .dw 0x2400, 0xe0a8, 0x2fff, 0xe0a8, 0x21, 0 - .dw 0x3400, 0xe0a8, 0x3fff, 0xe0a8, 0x21, 0 - .dw 0x4400, 0xe0a8, 0x4fff, 0xe0a8, 0x21, 0 - .dw 0x5400, 0xe0a8, 0x5fff, 0xe0a8, 0x21, 0 - .dw 0x6400, 0xe0a8, 0x6fff, 0xe0a8, 0x21, 0 - .dw 0x7400, 0xe0a8, 0xffff, 0xe0a8, 0x21, 0 - .dw 0x0400, 0xe0a9, 0x0fff, 0xe0a9, 0x21, 0 - .dw 0x1400, 0xe0a9, 0x1fff, 0xe0a9, 0x21, 0 - .dw 0x2400, 0xe0a9, 0x2fff, 0xe0a9, 0x21, 0 - .dw 0x3400, 0xe0a9, 0x3fff, 0xe0a9, 0x21, 0 - .dw 0x4400, 0xe0a9, 0x4fff, 0xe0a9, 0x21, 0 - .dw 0x5400, 0xe0a9, 0x5fff, 0xe0a9, 0x21, 0 - .dw 0x6400, 0xe0a9, 0x6fff, 0xe0a9, 0x21, 0 - .dw 0x7400, 0xe0a9, 0xffff, 0xe0a9, 0x21, 0 - .dw 0x0400, 0xe0aa, 0x0fff, 0xe0aa, 0x21, 0 - .dw 0x1400, 0xe0aa, 0x1fff, 0xe0aa, 0x21, 0 - .dw 0x2400, 0xe0aa, 0x2fff, 0xe0aa, 0x21, 0 - .dw 0x3400, 0xe0aa, 0x3fff, 0xe0aa, 0x21, 0 - .dw 0x4400, 0xe0aa, 0x4fff, 0xe0aa, 0x21, 0 - .dw 0x5400, 0xe0aa, 0x5fff, 0xe0aa, 0x21, 0 - .dw 0x6400, 0xe0aa, 0x6fff, 0xe0aa, 0x21, 0 - .dw 0x7400, 0xe0aa, 0xffff, 0xe0aa, 0x21, 0 - .dw 0x0400, 0xe0ab, 0x0fff, 0xe0ab, 0x21, 0 - .dw 0x1400, 0xe0ab, 0x1fff, 0xe0ab, 0x21, 0 - .dw 0x2400, 0xe0ab, 0x2fff, 0xe0ab, 0x21, 0 - .dw 0x3400, 0xe0ab, 0x3fff, 0xe0ab, 0x21, 0 - .dw 0x4400, 0xe0ab, 0x4fff, 0xe0ab, 0x21, 0 - .dw 0x5400, 0xe0ab, 0x5fff, 0xe0ab, 0x21, 0 - .dw 0x6400, 0xe0ab, 0x6fff, 0xe0ab, 0x21, 0 - .dw 0x7400, 0xe0ab, 0xffff, 0xe0ab, 0x21, 0 - .dw 0x0400, 0xe0ac, 0x0fff, 0xe0ac, 0x21, 0 - .dw 0x1400, 0xe0ac, 0x1fff, 0xe0ac, 0x21, 0 - .dw 0x2400, 0xe0ac, 0x2fff, 0xe0ac, 0x21, 0 - .dw 0x3400, 0xe0ac, 0x3fff, 0xe0ac, 0x21, 0 - .dw 0x4400, 0xe0ac, 0x4fff, 0xe0ac, 0x21, 0 - .dw 0x5400, 0xe0ac, 0x5fff, 0xe0ac, 0x21, 0 - .dw 0x6400, 0xe0ac, 0x6fff, 0xe0ac, 0x21, 0 - .dw 0x7400, 0xe0ac, 0xffff, 0xe0ac, 0x21, 0 - .dw 0x0400, 0xe0ad, 0x0fff, 0xe0ad, 0x21, 0 - .dw 0x1400, 0xe0ad, 0x1fff, 0xe0ad, 0x21, 0 - .dw 0x2400, 0xe0ad, 0x2fff, 0xe0ad, 0x21, 0 - .dw 0x3400, 0xe0ad, 0x3fff, 0xe0ad, 0x21, 0 - .dw 0x4400, 0xe0ad, 0x4fff, 0xe0ad, 0x21, 0 - .dw 0x5400, 0xe0ad, 0x5fff, 0xe0ad, 0x21, 0 - .dw 0x6400, 0xe0ad, 0x6fff, 0xe0ad, 0x21, 0 - .dw 0x7400, 0xe0ad, 0xffff, 0xe0ad, 0x21, 0 - .dw 0x0400, 0xe0ae, 0x0fff, 0xe0ae, 0x21, 0 - .dw 0x1400, 0xe0ae, 0x1fff, 0xe0ae, 0x21, 0 - .dw 0x2400, 0xe0ae, 0x2fff, 0xe0ae, 0x21, 0 - .dw 0x3400, 0xe0ae, 0x3fff, 0xe0ae, 0x21, 0 - .dw 0x4400, 0xe0ae, 0x4fff, 0xe0ae, 0x21, 0 - .dw 0x5400, 0xe0ae, 0x5fff, 0xe0ae, 0x21, 0 - .dw 0x6400, 0xe0ae, 0x6fff, 0xe0ae, 0x21, 0 - .dw 0x7400, 0xe0ae, 0xffff, 0xe0ae, 0x21, 0 - .dw 0x0400, 0xe0af, 0x0fff, 0xe0af, 0x21, 0 - .dw 0x1400, 0xe0af, 0x1fff, 0xe0af, 0x21, 0 - .dw 0x2400, 0xe0af, 0x2fff, 0xe0af, 0x21, 0 - .dw 0x3400, 0xe0af, 0x3fff, 0xe0af, 0x21, 0 - .dw 0x4400, 0xe0af, 0x4fff, 0xe0af, 0x21, 0 - .dw 0x5400, 0xe0af, 0x5fff, 0xe0af, 0x21, 0 - .dw 0x6400, 0xe0af, 0x6fff, 0xe0af, 0x21, 0 - .dw 0x7400, 0xe0af, 0xffff, 0xe0af, 0x21, 0 - .dw 0x0400, 0xe0b0, 0x0fff, 0xe0b0, 0x21, 0 - .dw 0x1400, 0xe0b0, 0x1fff, 0xe0b0, 0x21, 0 - .dw 0x2400, 0xe0b0, 0x2fff, 0xe0b0, 0x21, 0 - .dw 0x3400, 0xe0b0, 0x3fff, 0xe0b0, 0x21, 0 - .dw 0x4400, 0xe0b0, 0x4fff, 0xe0b0, 0x21, 0 - .dw 0x5400, 0xe0b0, 0x5fff, 0xe0b0, 0x21, 0 - .dw 0x6400, 0xe0b0, 0x6fff, 0xe0b0, 0x21, 0 - .dw 0x7400, 0xe0b0, 0xffff, 0xe0b0, 0x21, 0 - .dw 0x0400, 0xe0b1, 0x0fff, 0xe0b1, 0x21, 0 - .dw 0x1400, 0xe0b1, 0x1fff, 0xe0b1, 0x21, 0 - .dw 0x2400, 0xe0b1, 0x2fff, 0xe0b1, 0x21, 0 - .dw 0x3400, 0xe0b1, 0x3fff, 0xe0b1, 0x21, 0 - .dw 0x4400, 0xe0b1, 0x4fff, 0xe0b1, 0x21, 0 - .dw 0x5400, 0xe0b1, 0x5fff, 0xe0b1, 0x21, 0 - .dw 0x6400, 0xe0b1, 0x6fff, 0xe0b1, 0x21, 0 - .dw 0x7400, 0xe0b1, 0xffff, 0xe0b1, 0x21, 0 - .dw 0x0400, 0xe0b2, 0x0fff, 0xe0b2, 0x21, 0 - .dw 0x1400, 0xe0b2, 0x1fff, 0xe0b2, 0x21, 0 - .dw 0x2400, 0xe0b2, 0x2fff, 0xe0b2, 0x21, 0 - .dw 0x3400, 0xe0b2, 0x3fff, 0xe0b2, 0x21, 0 - .dw 0x4400, 0xe0b2, 0x4fff, 0xe0b2, 0x21, 0 - .dw 0x5400, 0xe0b2, 0x5fff, 0xe0b2, 0x21, 0 - .dw 0x6400, 0xe0b2, 0x6fff, 0xe0b2, 0x21, 0 - .dw 0x7400, 0xe0b2, 0xffff, 0xe0b2, 0x21, 0 - .dw 0x0400, 0xe0b3, 0x0fff, 0xe0b3, 0x21, 0 - .dw 0x1400, 0xe0b3, 0x1fff, 0xe0b3, 0x21, 0 - .dw 0x2400, 0xe0b3, 0x2fff, 0xe0b3, 0x21, 0 - .dw 0x3400, 0xe0b3, 0x3fff, 0xe0b3, 0x21, 0 - .dw 0x4400, 0xe0b3, 0x4fff, 0xe0b3, 0x21, 0 - .dw 0x5400, 0xe0b3, 0x5fff, 0xe0b3, 0x21, 0 - .dw 0x6400, 0xe0b3, 0x6fff, 0xe0b3, 0x21, 0 - .dw 0x7400, 0xe0b3, 0xffff, 0xe0b3, 0x21, 0 - .dw 0x0400, 0xe0b4, 0x0fff, 0xe0b4, 0x21, 0 - .dw 0x1400, 0xe0b4, 0x1fff, 0xe0b4, 0x21, 0 - .dw 0x2400, 0xe0b4, 0x2fff, 0xe0b4, 0x21, 0 - .dw 0x3400, 0xe0b4, 0x3fff, 0xe0b4, 0x21, 0 - .dw 0x4400, 0xe0b4, 0x4fff, 0xe0b4, 0x21, 0 - .dw 0x5400, 0xe0b4, 0x5fff, 0xe0b4, 0x21, 0 - .dw 0x6400, 0xe0b4, 0x6fff, 0xe0b4, 0x21, 0 - .dw 0x7400, 0xe0b4, 0xffff, 0xe0b4, 0x21, 0 - .dw 0x0400, 0xe0b5, 0x0fff, 0xe0b5, 0x21, 0 - .dw 0x1400, 0xe0b5, 0x1fff, 0xe0b5, 0x21, 0 - .dw 0x2400, 0xe0b5, 0x2fff, 0xe0b5, 0x21, 0 - .dw 0x3400, 0xe0b5, 0x3fff, 0xe0b5, 0x21, 0 - .dw 0x4400, 0xe0b5, 0x4fff, 0xe0b5, 0x21, 0 - .dw 0x5400, 0xe0b5, 0x5fff, 0xe0b5, 0x21, 0 - .dw 0x6400, 0xe0b5, 0x6fff, 0xe0b5, 0x21, 0 - .dw 0x7400, 0xe0b5, 0xffff, 0xe0b5, 0x21, 0 - .dw 0x0400, 0xe0b6, 0x0fff, 0xe0b6, 0x21, 0 - .dw 0x1400, 0xe0b6, 0x1fff, 0xe0b6, 0x21, 0 - .dw 0x2400, 0xe0b6, 0x2fff, 0xe0b6, 0x21, 0 - .dw 0x3400, 0xe0b6, 0x3fff, 0xe0b6, 0x21, 0 - .dw 0x4400, 0xe0b6, 0x4fff, 0xe0b6, 0x21, 0 - .dw 0x5400, 0xe0b6, 0x5fff, 0xe0b6, 0x21, 0 - .dw 0x6400, 0xe0b6, 0x6fff, 0xe0b6, 0x21, 0 - .dw 0x7400, 0xe0b6, 0xffff, 0xe0b6, 0x21, 0 - .dw 0x0400, 0xe0b7, 0x0fff, 0xe0b7, 0x21, 0 - .dw 0x1400, 0xe0b7, 0x1fff, 0xe0b7, 0x21, 0 - .dw 0x2400, 0xe0b7, 0x2fff, 0xe0b7, 0x21, 0 - .dw 0x3400, 0xe0b7, 0x3fff, 0xe0b7, 0x21, 0 - .dw 0x4400, 0xe0b7, 0x4fff, 0xe0b7, 0x21, 0 - .dw 0x5400, 0xe0b7, 0x5fff, 0xe0b7, 0x21, 0 - .dw 0x6400, 0xe0b7, 0x6fff, 0xe0b7, 0x21, 0 - .dw 0x7400, 0xe0b7, 0xffff, 0xe0b7, 0x21, 0 - .dw 0x0400, 0xe0b8, 0x0fff, 0xe0b8, 0x21, 0 - .dw 0x1400, 0xe0b8, 0x1fff, 0xe0b8, 0x21, 0 - .dw 0x2400, 0xe0b8, 0x2fff, 0xe0b8, 0x21, 0 - .dw 0x3400, 0xe0b8, 0x3fff, 0xe0b8, 0x21, 0 - .dw 0x4400, 0xe0b8, 0x4fff, 0xe0b8, 0x21, 0 - .dw 0x5400, 0xe0b8, 0x5fff, 0xe0b8, 0x21, 0 - .dw 0x6400, 0xe0b8, 0x6fff, 0xe0b8, 0x21, 0 - .dw 0x7400, 0xe0b8, 0xffff, 0xe0b8, 0x21, 0 - .dw 0x0400, 0xe0b9, 0x0fff, 0xe0b9, 0x21, 0 - .dw 0x1400, 0xe0b9, 0x1fff, 0xe0b9, 0x21, 0 - .dw 0x2400, 0xe0b9, 0x2fff, 0xe0b9, 0x21, 0 - .dw 0x3400, 0xe0b9, 0x3fff, 0xe0b9, 0x21, 0 - .dw 0x4400, 0xe0b9, 0x4fff, 0xe0b9, 0x21, 0 - .dw 0x5400, 0xe0b9, 0x5fff, 0xe0b9, 0x21, 0 - .dw 0x6400, 0xe0b9, 0x6fff, 0xe0b9, 0x21, 0 - .dw 0x7400, 0xe0b9, 0xffff, 0xe0b9, 0x21, 0 - .dw 0x0400, 0xe0ba, 0x0fff, 0xe0ba, 0x21, 0 - .dw 0x1400, 0xe0ba, 0x1fff, 0xe0ba, 0x21, 0 - .dw 0x2400, 0xe0ba, 0x2fff, 0xe0ba, 0x21, 0 - .dw 0x3400, 0xe0ba, 0x3fff, 0xe0ba, 0x21, 0 - .dw 0x4400, 0xe0ba, 0x4fff, 0xe0ba, 0x21, 0 - .dw 0x5400, 0xe0ba, 0x5fff, 0xe0ba, 0x21, 0 - .dw 0x6400, 0xe0ba, 0x6fff, 0xe0ba, 0x21, 0 - .dw 0x7400, 0xe0ba, 0xffff, 0xe0ba, 0x21, 0 - .dw 0x0400, 0xe0bb, 0x0fff, 0xe0bb, 0x21, 0 - .dw 0x1400, 0xe0bb, 0x1fff, 0xe0bb, 0x21, 0 - .dw 0x2400, 0xe0bb, 0x2fff, 0xe0bb, 0x21, 0 - .dw 0x3400, 0xe0bb, 0x3fff, 0xe0bb, 0x21, 0 - .dw 0x4400, 0xe0bb, 0x4fff, 0xe0bb, 0x21, 0 - .dw 0x5400, 0xe0bb, 0x5fff, 0xe0bb, 0x21, 0 - .dw 0x6400, 0xe0bb, 0x6fff, 0xe0bb, 0x21, 0 - .dw 0x7400, 0xe0bb, 0xffff, 0xe0bb, 0x21, 0 - .dw 0x0400, 0xe0bc, 0x0fff, 0xe0bc, 0x21, 0 - .dw 0x1400, 0xe0bc, 0x1fff, 0xe0bc, 0x21, 0 - .dw 0x2400, 0xe0bc, 0x2fff, 0xe0bc, 0x21, 0 - .dw 0x3400, 0xe0bc, 0x3fff, 0xe0bc, 0x21, 0 - .dw 0x4400, 0xe0bc, 0x4fff, 0xe0bc, 0x21, 0 - .dw 0x5400, 0xe0bc, 0x5fff, 0xe0bc, 0x21, 0 - .dw 0x6400, 0xe0bc, 0x6fff, 0xe0bc, 0x21, 0 - .dw 0x7400, 0xe0bc, 0xffff, 0xe0bc, 0x21, 0 - .dw 0x0400, 0xe0bd, 0x0fff, 0xe0bd, 0x21, 0 - .dw 0x1400, 0xe0bd, 0x1fff, 0xe0bd, 0x21, 0 - .dw 0x2400, 0xe0bd, 0x2fff, 0xe0bd, 0x21, 0 - .dw 0x3400, 0xe0bd, 0x3fff, 0xe0bd, 0x21, 0 - .dw 0x4400, 0xe0bd, 0x4fff, 0xe0bd, 0x21, 0 - .dw 0x5400, 0xe0bd, 0x5fff, 0xe0bd, 0x21, 0 - .dw 0x6400, 0xe0bd, 0x6fff, 0xe0bd, 0x21, 0 - .dw 0x7400, 0xe0bd, 0xffff, 0xe0bd, 0x21, 0 - .dw 0x0400, 0xe0be, 0x0fff, 0xe0be, 0x21, 0 - .dw 0x1400, 0xe0be, 0x1fff, 0xe0be, 0x21, 0 - .dw 0x2400, 0xe0be, 0x2fff, 0xe0be, 0x21, 0 - .dw 0x3400, 0xe0be, 0x3fff, 0xe0be, 0x21, 0 - .dw 0x4400, 0xe0be, 0x4fff, 0xe0be, 0x21, 0 - .dw 0x5400, 0xe0be, 0x5fff, 0xe0be, 0x21, 0 - .dw 0x6400, 0xe0be, 0x6fff, 0xe0be, 0x21, 0 - .dw 0x7400, 0xe0be, 0xffff, 0xe0be, 0x21, 0 - .dw 0x0400, 0xe0bf, 0x0fff, 0xe0bf, 0x21, 0 - .dw 0x1400, 0xe0bf, 0x1fff, 0xe0bf, 0x21, 0 - .dw 0x2400, 0xe0bf, 0x2fff, 0xe0bf, 0x21, 0 - .dw 0x3400, 0xe0bf, 0x3fff, 0xe0bf, 0x21, 0 - .dw 0x4400, 0xe0bf, 0x4fff, 0xe0bf, 0x21, 0 - .dw 0x5400, 0xe0bf, 0x5fff, 0xe0bf, 0x21, 0 - .dw 0x6400, 0xe0bf, 0x6fff, 0xe0bf, 0x21, 0 - .dw 0x7400, 0xe0bf, 0xffff, 0xe0df, 0x21, 0 - .dw 0x0400, 0xe0e0, 0x0fff, 0xe0e0, 0x21, 0 - .dw 0x1400, 0xe0e0, 0x1fff, 0xe0e0, 0x21, 0 - .dw 0x2400, 0xe0e0, 0x2fff, 0xe0e0, 0x21, 0 - .dw 0x3400, 0xe0e0, 0x3fff, 0xe0e0, 0x21, 0 - .dw 0x4400, 0xe0e0, 0x4fff, 0xe0e0, 0x21, 0 - .dw 0x5400, 0xe0e0, 0x5fff, 0xe0e0, 0x21, 0 - .dw 0x6400, 0xe0e0, 0x6fff, 0xe0e0, 0x21, 0 - .dw 0x7400, 0xe0e0, 0xffff, 0xe0e0, 0x21, 0 - .dw 0x0400, 0xe0e1, 0x0fff, 0xe0e1, 0x21, 0 - .dw 0x1400, 0xe0e1, 0x1fff, 0xe0e1, 0x21, 0 - .dw 0x2400, 0xe0e1, 0x2fff, 0xe0e1, 0x21, 0 - .dw 0x3400, 0xe0e1, 0x3fff, 0xe0e1, 0x21, 0 - .dw 0x4400, 0xe0e1, 0x4fff, 0xe0e1, 0x21, 0 - .dw 0x5400, 0xe0e1, 0x5fff, 0xe0e1, 0x21, 0 - .dw 0x6400, 0xe0e1, 0x6fff, 0xe0e1, 0x21, 0 - .dw 0x7400, 0xe0e1, 0xffff, 0xe0e1, 0x21, 0 - .dw 0x0400, 0xe0e2, 0x0fff, 0xe0e2, 0x21, 0 - .dw 0x1400, 0xe0e2, 0x1fff, 0xe0e2, 0x21, 0 - .dw 0x2400, 0xe0e2, 0x2fff, 0xe0e2, 0x21, 0 - .dw 0x3400, 0xe0e2, 0x3fff, 0xe0e2, 0x21, 0 - .dw 0x4400, 0xe0e2, 0x4fff, 0xe0e2, 0x21, 0 - .dw 0x5400, 0xe0e2, 0x5fff, 0xe0e2, 0x21, 0 - .dw 0x6400, 0xe0e2, 0x6fff, 0xe0e2, 0x21, 0 - .dw 0x7400, 0xe0e2, 0xffff, 0xe0e2, 0x21, 0 - .dw 0x0400, 0xe0e3, 0x0fff, 0xe0e3, 0x21, 0 - .dw 0x1400, 0xe0e3, 0x1fff, 0xe0e3, 0x21, 0 - .dw 0x2400, 0xe0e3, 0x2fff, 0xe0e3, 0x21, 0 - .dw 0x3400, 0xe0e3, 0x3fff, 0xe0e3, 0x21, 0 - .dw 0x4400, 0xe0e3, 0x4fff, 0xe0e3, 0x21, 0 - .dw 0x5400, 0xe0e3, 0x5fff, 0xe0e3, 0x21, 0 - .dw 0x6400, 0xe0e3, 0x6fff, 0xe0e3, 0x21, 0 - .dw 0x7400, 0xe0e3, 0xffff, 0xe0e3, 0x21, 0 - .dw 0x0400, 0xe0e4, 0x0fff, 0xe0e4, 0x21, 0 - .dw 0x1400, 0xe0e4, 0x1fff, 0xe0e4, 0x21, 0 - .dw 0x2400, 0xe0e4, 0x2fff, 0xe0e4, 0x21, 0 - .dw 0x3400, 0xe0e4, 0x3fff, 0xe0e4, 0x21, 0 - .dw 0x4400, 0xe0e4, 0x4fff, 0xe0e4, 0x21, 0 - .dw 0x5400, 0xe0e4, 0x5fff, 0xe0e4, 0x21, 0 - .dw 0x6400, 0xe0e4, 0x6fff, 0xe0e4, 0x21, 0 - .dw 0x7400, 0xe0e4, 0xffff, 0xe0e4, 0x21, 0 - .dw 0x0400, 0xe0e5, 0x0fff, 0xe0e5, 0x21, 0 - .dw 0x1400, 0xe0e5, 0x1fff, 0xe0e5, 0x21, 0 - .dw 0x2400, 0xe0e5, 0x2fff, 0xe0e5, 0x21, 0 - .dw 0x3400, 0xe0e5, 0x3fff, 0xe0e5, 0x21, 0 - .dw 0x4400, 0xe0e5, 0x4fff, 0xe0e5, 0x21, 0 - .dw 0x5400, 0xe0e5, 0x5fff, 0xe0e5, 0x21, 0 - .dw 0x6400, 0xe0e5, 0x6fff, 0xe0e5, 0x21, 0 - .dw 0x7400, 0xe0e5, 0xffff, 0xe0e5, 0x21, 0 - .dw 0x0400, 0xe0e6, 0x0fff, 0xe0e6, 0x21, 0 - .dw 0x1400, 0xe0e6, 0x1fff, 0xe0e6, 0x21, 0 - .dw 0x2400, 0xe0e6, 0x2fff, 0xe0e6, 0x21, 0 - .dw 0x3400, 0xe0e6, 0x3fff, 0xe0e6, 0x21, 0 - .dw 0x4400, 0xe0e6, 0x4fff, 0xe0e6, 0x21, 0 - .dw 0x5400, 0xe0e6, 0x5fff, 0xe0e6, 0x21, 0 - .dw 0x6400, 0xe0e6, 0x6fff, 0xe0e6, 0x21, 0 - .dw 0x7400, 0xe0e6, 0xffff, 0xe0e6, 0x21, 0 - .dw 0x0400, 0xe0e7, 0x0fff, 0xe0e7, 0x21, 0 - .dw 0x1400, 0xe0e7, 0x1fff, 0xe0e7, 0x21, 0 - .dw 0x2400, 0xe0e7, 0x2fff, 0xe0e7, 0x21, 0 - .dw 0x3400, 0xe0e7, 0x3fff, 0xe0e7, 0x21, 0 - .dw 0x4400, 0xe0e7, 0x4fff, 0xe0e7, 0x21, 0 - .dw 0x5400, 0xe0e7, 0x5fff, 0xe0e7, 0x21, 0 - .dw 0x6400, 0xe0e7, 0x6fff, 0xe0e7, 0x21, 0 - .dw 0x7400, 0xe0e7, 0xffff, 0xe0e7, 0x21, 0 - .dw 0x0400, 0xe0e8, 0x0fff, 0xe0e8, 0x21, 0 - .dw 0x1400, 0xe0e8, 0x1fff, 0xe0e8, 0x21, 0 - .dw 0x2400, 0xe0e8, 0x2fff, 0xe0e8, 0x21, 0 - .dw 0x3400, 0xe0e8, 0x3fff, 0xe0e8, 0x21, 0 - .dw 0x4400, 0xe0e8, 0x4fff, 0xe0e8, 0x21, 0 - .dw 0x5400, 0xe0e8, 0x5fff, 0xe0e8, 0x21, 0 - .dw 0x6400, 0xe0e8, 0x6fff, 0xe0e8, 0x21, 0 - .dw 0x7400, 0xe0e8, 0xffff, 0xe0e8, 0x21, 0 - .dw 0x0400, 0xe0e9, 0x0fff, 0xe0e9, 0x21, 0 - .dw 0x1400, 0xe0e9, 0x1fff, 0xe0e9, 0x21, 0 - .dw 0x2400, 0xe0e9, 0x2fff, 0xe0e9, 0x21, 0 - .dw 0x3400, 0xe0e9, 0x3fff, 0xe0e9, 0x21, 0 - .dw 0x4400, 0xe0e9, 0x4fff, 0xe0e9, 0x21, 0 - .dw 0x5400, 0xe0e9, 0x5fff, 0xe0e9, 0x21, 0 - .dw 0x6400, 0xe0e9, 0x6fff, 0xe0e9, 0x21, 0 - .dw 0x7400, 0xe0e9, 0xffff, 0xe0e9, 0x21, 0 - .dw 0x0400, 0xe0ea, 0x0fff, 0xe0ea, 0x21, 0 - .dw 0x1400, 0xe0ea, 0x1fff, 0xe0ea, 0x21, 0 - .dw 0x2400, 0xe0ea, 0x2fff, 0xe0ea, 0x21, 0 - .dw 0x3400, 0xe0ea, 0x3fff, 0xe0ea, 0x21, 0 - .dw 0x4400, 0xe0ea, 0x4fff, 0xe0ea, 0x21, 0 - .dw 0x5400, 0xe0ea, 0x5fff, 0xe0ea, 0x21, 0 - .dw 0x6400, 0xe0ea, 0x6fff, 0xe0ea, 0x21, 0 - .dw 0x7400, 0xe0ea, 0xffff, 0xe0ea, 0x21, 0 - .dw 0x0400, 0xe0eb, 0x0fff, 0xe0eb, 0x21, 0 - .dw 0x1400, 0xe0eb, 0x1fff, 0xe0eb, 0x21, 0 - .dw 0x2400, 0xe0eb, 0x2fff, 0xe0eb, 0x21, 0 - .dw 0x3400, 0xe0eb, 0x3fff, 0xe0eb, 0x21, 0 - .dw 0x4400, 0xe0eb, 0x4fff, 0xe0eb, 0x21, 0 - .dw 0x5400, 0xe0eb, 0x5fff, 0xe0eb, 0x21, 0 - .dw 0x6400, 0xe0eb, 0x6fff, 0xe0eb, 0x21, 0 - .dw 0x7400, 0xe0eb, 0xffff, 0xe0eb, 0x21, 0 - .dw 0x0400, 0xe0ec, 0x0fff, 0xe0ec, 0x21, 0 - .dw 0x1400, 0xe0ec, 0x1fff, 0xe0ec, 0x21, 0 - .dw 0x2400, 0xe0ec, 0x2fff, 0xe0ec, 0x21, 0 - .dw 0x3400, 0xe0ec, 0x3fff, 0xe0ec, 0x21, 0 - .dw 0x4400, 0xe0ec, 0x4fff, 0xe0ec, 0x21, 0 - .dw 0x5400, 0xe0ec, 0x5fff, 0xe0ec, 0x21, 0 - .dw 0x6400, 0xe0ec, 0x6fff, 0xe0ec, 0x21, 0 - .dw 0x7400, 0xe0ec, 0xffff, 0xe0ec, 0x21, 0 - .dw 0x0400, 0xe0ed, 0x0fff, 0xe0ed, 0x21, 0 - .dw 0x1400, 0xe0ed, 0x1fff, 0xe0ed, 0x21, 0 - .dw 0x2400, 0xe0ed, 0x2fff, 0xe0ed, 0x21, 0 - .dw 0x3400, 0xe0ed, 0x3fff, 0xe0ed, 0x21, 0 - .dw 0x4400, 0xe0ed, 0x4fff, 0xe0ed, 0x21, 0 - .dw 0x5400, 0xe0ed, 0x5fff, 0xe0ed, 0x21, 0 - .dw 0x6400, 0xe0ed, 0x6fff, 0xe0ed, 0x21, 0 - .dw 0x7400, 0xe0ed, 0xffff, 0xe0ed, 0x21, 0 - .dw 0x0400, 0xe0ee, 0x0fff, 0xe0ee, 0x21, 0 - .dw 0x1400, 0xe0ee, 0x1fff, 0xe0ee, 0x21, 0 - .dw 0x2400, 0xe0ee, 0x2fff, 0xe0ee, 0x21, 0 - .dw 0x3400, 0xe0ee, 0x3fff, 0xe0ee, 0x21, 0 - .dw 0x4400, 0xe0ee, 0x4fff, 0xe0ee, 0x21, 0 - .dw 0x5400, 0xe0ee, 0x5fff, 0xe0ee, 0x21, 0 - .dw 0x6400, 0xe0ee, 0x6fff, 0xe0ee, 0x21, 0 - .dw 0x7400, 0xe0ee, 0xffff, 0xe0ee, 0x21, 0 - .dw 0x0400, 0xe0ef, 0x0fff, 0xe0ef, 0x21, 0 - .dw 0x1400, 0xe0ef, 0x1fff, 0xe0ef, 0x21, 0 - .dw 0x2400, 0xe0ef, 0x2fff, 0xe0ef, 0x21, 0 - .dw 0x3400, 0xe0ef, 0x3fff, 0xe0ef, 0x21, 0 - .dw 0x4400, 0xe0ef, 0x4fff, 0xe0ef, 0x21, 0 - .dw 0x5400, 0xe0ef, 0x5fff, 0xe0ef, 0x21, 0 - .dw 0x6400, 0xe0ef, 0x6fff, 0xe0ef, 0x21, 0 - .dw 0x7400, 0xe0ef, 0xffff, 0xe0ef, 0x21, 0 - .dw 0x0400, 0xe0f0, 0x0fff, 0xe0f0, 0x21, 0 - .dw 0x1400, 0xe0f0, 0x1fff, 0xe0f0, 0x21, 0 - .dw 0x2400, 0xe0f0, 0x2fff, 0xe0f0, 0x21, 0 - .dw 0x3400, 0xe0f0, 0x3fff, 0xe0f0, 0x21, 0 - .dw 0x4400, 0xe0f0, 0x4fff, 0xe0f0, 0x21, 0 - .dw 0x5400, 0xe0f0, 0x5fff, 0xe0f0, 0x21, 0 - .dw 0x6400, 0xe0f0, 0x6fff, 0xe0f0, 0x21, 0 - .dw 0x7400, 0xe0f0, 0xffff, 0xe0f0, 0x21, 0 - .dw 0x0400, 0xe0f1, 0x0fff, 0xe0f1, 0x21, 0 - .dw 0x1400, 0xe0f1, 0x1fff, 0xe0f1, 0x21, 0 - .dw 0x2400, 0xe0f1, 0x2fff, 0xe0f1, 0x21, 0 - .dw 0x3400, 0xe0f1, 0x3fff, 0xe0f1, 0x21, 0 - .dw 0x4400, 0xe0f1, 0x4fff, 0xe0f1, 0x21, 0 - .dw 0x5400, 0xe0f1, 0x5fff, 0xe0f1, 0x21, 0 - .dw 0x6400, 0xe0f1, 0x6fff, 0xe0f1, 0x21, 0 - .dw 0x7400, 0xe0f1, 0xffff, 0xe0f1, 0x21, 0 - .dw 0x0400, 0xe0f2, 0x0fff, 0xe0f2, 0x21, 0 - .dw 0x1400, 0xe0f2, 0x1fff, 0xe0f2, 0x21, 0 - .dw 0x2400, 0xe0f2, 0x2fff, 0xe0f2, 0x21, 0 - .dw 0x3400, 0xe0f2, 0x3fff, 0xe0f2, 0x21, 0 - .dw 0x4400, 0xe0f2, 0x4fff, 0xe0f2, 0x21, 0 - .dw 0x5400, 0xe0f2, 0x5fff, 0xe0f2, 0x21, 0 - .dw 0x6400, 0xe0f2, 0x6fff, 0xe0f2, 0x21, 0 - .dw 0x7400, 0xe0f2, 0xffff, 0xe0f2, 0x21, 0 - .dw 0x0400, 0xe0f3, 0x0fff, 0xe0f3, 0x21, 0 - .dw 0x1400, 0xe0f3, 0x1fff, 0xe0f3, 0x21, 0 - .dw 0x2400, 0xe0f3, 0x2fff, 0xe0f3, 0x21, 0 - .dw 0x3400, 0xe0f3, 0x3fff, 0xe0f3, 0x21, 0 - .dw 0x4400, 0xe0f3, 0x4fff, 0xe0f3, 0x21, 0 - .dw 0x5400, 0xe0f3, 0x5fff, 0xe0f3, 0x21, 0 - .dw 0x6400, 0xe0f3, 0x6fff, 0xe0f3, 0x21, 0 - .dw 0x7400, 0xe0f3, 0xffff, 0xe0f3, 0x21, 0 - .dw 0x0400, 0xe0f4, 0x0fff, 0xe0f4, 0x21, 0 - .dw 0x1400, 0xe0f4, 0x1fff, 0xe0f4, 0x21, 0 - .dw 0x2400, 0xe0f4, 0x2fff, 0xe0f4, 0x21, 0 - .dw 0x3400, 0xe0f4, 0x3fff, 0xe0f4, 0x21, 0 - .dw 0x4400, 0xe0f4, 0x4fff, 0xe0f4, 0x21, 0 - .dw 0x5400, 0xe0f4, 0x5fff, 0xe0f4, 0x21, 0 - .dw 0x6400, 0xe0f4, 0x6fff, 0xe0f4, 0x21, 0 - .dw 0x7400, 0xe0f4, 0xffff, 0xe0f4, 0x21, 0 - .dw 0x0400, 0xe0f5, 0x0fff, 0xe0f5, 0x21, 0 - .dw 0x1400, 0xe0f5, 0x1fff, 0xe0f5, 0x21, 0 - .dw 0x2400, 0xe0f5, 0x2fff, 0xe0f5, 0x21, 0 - .dw 0x3400, 0xe0f5, 0x3fff, 0xe0f5, 0x21, 0 - .dw 0x4400, 0xe0f5, 0x4fff, 0xe0f5, 0x21, 0 - .dw 0x5400, 0xe0f5, 0x5fff, 0xe0f5, 0x21, 0 - .dw 0x6400, 0xe0f5, 0x6fff, 0xe0f5, 0x21, 0 - .dw 0x7400, 0xe0f5, 0xffff, 0xe0f5, 0x21, 0 - .dw 0x0400, 0xe0f6, 0x0fff, 0xe0f6, 0x21, 0 - .dw 0x1400, 0xe0f6, 0x1fff, 0xe0f6, 0x21, 0 - .dw 0x2400, 0xe0f6, 0x2fff, 0xe0f6, 0x21, 0 - .dw 0x3400, 0xe0f6, 0x3fff, 0xe0f6, 0x21, 0 - .dw 0x4400, 0xe0f6, 0x4fff, 0xe0f6, 0x21, 0 - .dw 0x5400, 0xe0f6, 0x5fff, 0xe0f6, 0x21, 0 - .dw 0x6400, 0xe0f6, 0x6fff, 0xe0f6, 0x21, 0 - .dw 0x7400, 0xe0f6, 0xffff, 0xe0f6, 0x21, 0 - .dw 0x0400, 0xe0f7, 0x0fff, 0xe0f7, 0x21, 0 - .dw 0x1400, 0xe0f7, 0x1fff, 0xe0f7, 0x21, 0 - .dw 0x2400, 0xe0f7, 0x2fff, 0xe0f7, 0x21, 0 - .dw 0x3400, 0xe0f7, 0x3fff, 0xe0f7, 0x21, 0 - .dw 0x4400, 0xe0f7, 0x4fff, 0xe0f7, 0x21, 0 - .dw 0x5400, 0xe0f7, 0x5fff, 0xe0f7, 0x21, 0 - .dw 0x6400, 0xe0f7, 0x6fff, 0xe0f7, 0x21, 0 - .dw 0x7400, 0xe0f7, 0xffff, 0xe0f7, 0x21, 0 - .dw 0x0400, 0xe0f8, 0x0fff, 0xe0f8, 0x21, 0 - .dw 0x1400, 0xe0f8, 0x1fff, 0xe0f8, 0x21, 0 - .dw 0x2400, 0xe0f8, 0x2fff, 0xe0f8, 0x21, 0 - .dw 0x3400, 0xe0f8, 0x3fff, 0xe0f8, 0x21, 0 - .dw 0x4400, 0xe0f8, 0x4fff, 0xe0f8, 0x21, 0 - .dw 0x5400, 0xe0f8, 0x5fff, 0xe0f8, 0x21, 0 - .dw 0x6400, 0xe0f8, 0x6fff, 0xe0f8, 0x21, 0 - .dw 0x7400, 0xe0f8, 0xffff, 0xe0f8, 0x21, 0 - .dw 0x0400, 0xe0f9, 0x0fff, 0xe0f9, 0x21, 0 - .dw 0x1400, 0xe0f9, 0x1fff, 0xe0f9, 0x21, 0 - .dw 0x2400, 0xe0f9, 0x2fff, 0xe0f9, 0x21, 0 - .dw 0x3400, 0xe0f9, 0x3fff, 0xe0f9, 0x21, 0 - .dw 0x4400, 0xe0f9, 0x4fff, 0xe0f9, 0x21, 0 - .dw 0x5400, 0xe0f9, 0x5fff, 0xe0f9, 0x21, 0 - .dw 0x6400, 0xe0f9, 0x6fff, 0xe0f9, 0x21, 0 - .dw 0x7400, 0xe0f9, 0xffff, 0xe0f9, 0x21, 0 - .dw 0x0400, 0xe0fa, 0x0fff, 0xe0fa, 0x21, 0 - .dw 0x1400, 0xe0fa, 0x1fff, 0xe0fa, 0x21, 0 - .dw 0x2400, 0xe0fa, 0x2fff, 0xe0fa, 0x21, 0 - .dw 0x3400, 0xe0fa, 0x3fff, 0xe0fa, 0x21, 0 - .dw 0x4400, 0xe0fa, 0x4fff, 0xe0fa, 0x21, 0 - .dw 0x5400, 0xe0fa, 0x5fff, 0xe0fa, 0x21, 0 - .dw 0x6400, 0xe0fa, 0x6fff, 0xe0fa, 0x21, 0 - .dw 0x7400, 0xe0fa, 0xffff, 0xe0fa, 0x21, 0 - .dw 0x0400, 0xe0fb, 0x0fff, 0xe0fb, 0x21, 0 - .dw 0x1400, 0xe0fb, 0x1fff, 0xe0fb, 0x21, 0 - .dw 0x2400, 0xe0fb, 0x2fff, 0xe0fb, 0x21, 0 - .dw 0x3400, 0xe0fb, 0x3fff, 0xe0fb, 0x21, 0 - .dw 0x4400, 0xe0fb, 0x4fff, 0xe0fb, 0x21, 0 - .dw 0x5400, 0xe0fb, 0x5fff, 0xe0fb, 0x21, 0 - .dw 0x6400, 0xe0fb, 0x6fff, 0xe0fb, 0x21, 0 - .dw 0x7400, 0xe0fb, 0xffff, 0xe0fb, 0x21, 0 - .dw 0x0400, 0xe0fc, 0x0fff, 0xe0fc, 0x21, 0 - .dw 0x1400, 0xe0fc, 0x1fff, 0xe0fc, 0x21, 0 - .dw 0x2400, 0xe0fc, 0x2fff, 0xe0fc, 0x21, 0 - .dw 0x3400, 0xe0fc, 0x3fff, 0xe0fc, 0x21, 0 - .dw 0x4400, 0xe0fc, 0x4fff, 0xe0fc, 0x21, 0 - .dw 0x5400, 0xe0fc, 0x5fff, 0xe0fc, 0x21, 0 - .dw 0x6400, 0xe0fc, 0x6fff, 0xe0fc, 0x21, 0 - .dw 0x7400, 0xe0fc, 0xffff, 0xe0fc, 0x21, 0 - .dw 0x0400, 0xe0fd, 0x0fff, 0xe0fd, 0x21, 0 - .dw 0x1400, 0xe0fd, 0x1fff, 0xe0fd, 0x21, 0 - .dw 0x2400, 0xe0fd, 0x2fff, 0xe0fd, 0x21, 0 - .dw 0x3400, 0xe0fd, 0x3fff, 0xe0fd, 0x21, 0 - .dw 0x4400, 0xe0fd, 0x4fff, 0xe0fd, 0x21, 0 - .dw 0x5400, 0xe0fd, 0x5fff, 0xe0fd, 0x21, 0 - .dw 0x6400, 0xe0fd, 0x6fff, 0xe0fd, 0x21, 0 - .dw 0x7400, 0xe0fd, 0xffff, 0xe0fd, 0x21, 0 - .dw 0x0400, 0xe0fe, 0x0fff, 0xe0fe, 0x21, 0 - .dw 0x1400, 0xe0fe, 0x1fff, 0xe0fe, 0x21, 0 - .dw 0x2400, 0xe0fe, 0x2fff, 0xe0fe, 0x21, 0 - .dw 0x3400, 0xe0fe, 0x3fff, 0xe0fe, 0x21, 0 - .dw 0x4400, 0xe0fe, 0x4fff, 0xe0fe, 0x21, 0 - .dw 0x5400, 0xe0fe, 0x5fff, 0xe0fe, 0x21, 0 - .dw 0x6400, 0xe0fe, 0x6fff, 0xe0fe, 0x21, 0 - .dw 0x7400, 0xe0fe, 0xffff, 0xe0fe, 0x21, 0 - .dw 0x0400, 0xe0ff, 0x0fff, 0xe0ff, 0x21, 0 - .dw 0x1400, 0xe0ff, 0x1fff, 0xe0ff, 0x21, 0 - .dw 0x2400, 0xe0ff, 0x2fff, 0xe0ff, 0x21, 0 - .dw 0x3400, 0xe0ff, 0x3fff, 0xe0ff, 0x21, 0 - .dw 0x4400, 0xe0ff, 0x4fff, 0xe0ff, 0x21, 0 - .dw 0x5400, 0xe0ff, 0x5fff, 0xe0ff, 0x21, 0 - .dw 0x6400, 0xe0ff, 0x6fff, 0xe0ff, 0x21, 0 - .dw 0x7400, 0xe0ff, 0xffff, 0xe0ff, 0x21, 0 - .dw 0x0000, 0xe160, 0xffff, 0xe17f, 0x21, 0 - .dw 0x0000, 0xe1a0, 0xffff, 0xe1ff, 0x21, 0 - .dw 0x0000, 0xe4c0, 0xffff, 0xe4ff, 0x21, 0 - .dw 0x0000, 0xe5c0, 0xffff, 0xe5ff, 0x21, 0 - .dw 0x0000, 0xe6c0, 0xffff, 0xe6ff, 0x21, 0 - .dw 0x0000, 0xe740, 0xffff, 0xe7ff, 0x21, 0 - .dw 0x0000, 0xf001, 0xffff, 0xffff, 0x21, 0 - .dw 0x0000, 0x0000, 0x0000, 0x0000, 0x00, 0 -.endm - - se_all_test diff --git a/sim/testsuite/sim/bfin/se_all32bitopcodes.lds b/sim/testsuite/sim/bfin/se_all32bitopcodes.lds deleted file mode 100644 index 6f37d65..0000000 --- a/sim/testsuite/sim/bfin/se_all32bitopcodes.lds +++ /dev/null @@ -1,16 +0,0 @@ -MEMORY -{ - L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000 - L1_DATA : ORIGIN = 0xFF800000, LENGTH = 0x8000 - SDRAM : ORIGIN = 0x4000, LENGTH = 0x4000000 -} - -OUTPUT_ARCH(bfin) -ENTRY(__start) - -SECTIONS -{ - .text : { *(.text) } >L1_CODE - .text.usr : { *(.text.usr) } >SDRAM - .data : { *(.data) } >SDRAM -} diff --git a/sim/testsuite/sim/bfin/se_all64bitg0opcodes.S b/sim/testsuite/sim/bfin/se_all64bitg0opcodes.S deleted file mode 100644 index 516583b..0000000 --- a/sim/testsuite/sim/bfin/se_all64bitg0opcodes.S +++ /dev/null @@ -1,33369 +0,0 @@ -/* - * Blackfin testcase for testing illegal/legal 64-bit opcodes (group 0) - * from userspace. we track all instructions which cause some sort of - * exception when run from userspace, this is normally EXCAUSE : - * - 0x22 : illegal instruction combination - * and walk every instruction from 0xC0000000 to 0xffffffff - * (and have 0x8000000 set) - */ - -# Don't want to enable for normal `make check` as it takes way too long in -# the sim -- executes over 3 billion insns, and even at 10 MIPS, that's 10+ -# minutes. Useful for directed testing, but that's about it. -# mach: none -# sim: --environment operating -# xfail: too many invalid insns are decoded as valid - -#include "test.h" - .include "testutils.inc" - -#define SE_ALL_BITS 32 -#include "se_allopcodes.h" - -.macro se_all_load_insn - R2 = [P5]; - R0 = R2 << 16; - R1 = R2 >> 16; - R0 = R0 | R1; -.endm - -.macro se_all_next_insn - /* increment, and go again. */ - R0 = R2; - - /* Is this the last insn we'll execute ? */ - R1 = -1 (x); - CC = R1 == R0; - IF CC JUMP pass_lvl; - - /* cut across the opcode space in an efficient manner: - * increment the high 16bits first since the low 16bits encode - * the type of insn ... */ - imm32 R1, 0x10000; - R0 = R1 + R0; - CC = R1 < R0 (IU); - IF CC jump 1f (bp); - - R0 += 1; - /* skip any 16bit insn chunks */ - R1 = R0; - R1.L = 0xC800; - CC = R0 < R1 (IU); - IF CC R0 = R1; -1: - - /* force parallel insns */ - BITSET (R0, 11); - - /* skip linkage insns */ - R1 = R0; - R2 = R0; - R1.L = 0xe800; - R2.L = 0xe802; - CC = R0 == R1; - IF CC R0 = R2; - - [P5] = R0; -.endm - -.macro se_all_insn_init - .dw 0xc800; /* 32bit */ - .dw 0x0000; /* insn */ - .dw 0x0000; /* || group1 */ - .dw 0x0000; /* || group2; */ -.endm -.macro se_all_insn_table - /* this table must be sorted, and end with zero */ - /* start end SEQSTAT */ - .dw 0x1a00, 0xc800, 0x1fff, 0xc800, 0x21, 0 - .dw 0x3a00, 0xc800, 0x3fff, 0xc800, 0x21, 0 - .dw 0x5a00, 0xc800, 0x5fff, 0xc800, 0x21, 0 - .dw 0x7a00, 0xc800, 0x7fff, 0xc800, 0x21, 0 - .dw 0x9a00, 0xc800, 0x9fff, 0xc800, 0x21, 0 - .dw 0xba00, 0xc800, 0xbfff, 0xc800, 0x21, 0 - .dw 0xda00, 0xc800, 0xdfff, 0xc800, 0x21, 0 - .dw 0xfa00, 0xc800, 0xffff, 0xc800, 0x21, 0 - .dw 0x1a00, 0xc801, 0x1fff, 0xc801, 0x21, 0 - .dw 0x3a00, 0xc801, 0x3fff, 0xc801, 0x21, 0 - .dw 0x5a00, 0xc801, 0x5fff, 0xc801, 0x21, 0 - .dw 0x7a00, 0xc801, 0x7fff, 0xc801, 0x21, 0 - .dw 0x9a00, 0xc801, 0x9fff, 0xc801, 0x21, 0 - .dw 0xba00, 0xc801, 0xbfff, 0xc801, 0x21, 0 - .dw 0xda00, 0xc801, 0xdfff, 0xc801, 0x21, 0 - .dw 0xfa00, 0xc801, 0xffff, 0xc801, 0x21, 0 - .dw 0x1a00, 0xc802, 0x1fff, 0xc802, 0x21, 0 - .dw 0x3a00, 0xc802, 0x3fff, 0xc802, 0x21, 0 - .dw 0x5a00, 0xc802, 0x5fff, 0xc802, 0x21, 0 - .dw 0x7a00, 0xc802, 0x7fff, 0xc802, 0x21, 0 - .dw 0x9a00, 0xc802, 0x9fff, 0xc802, 0x21, 0 - .dw 0xba00, 0xc802, 0xbfff, 0xc802, 0x21, 0 - .dw 0xda00, 0xc802, 0xdfff, 0xc802, 0x21, 0 - .dw 0xfa00, 0xc802, 0xffff, 0xc802, 0x21, 0 - .dw 0x1a00, 0xc803, 0x1fff, 0xc803, 0x21, 0 - .dw 0x3a00, 0xc803, 0xffff, 0xc803, 0x21, 0 - .dw 0x1a00, 0xc804, 0x1fff, 0xc804, 0x21, 0 - .dw 0x3a00, 0xc804, 0x3fff, 0xc804, 0x21, 0 - .dw 0x5a00, 0xc804, 0x5fff, 0xc804, 0x21, 0 - .dw 0x7a00, 0xc804, 0x7fff, 0xc804, 0x21, 0 - .dw 0x9a00, 0xc804, 0x9fff, 0xc804, 0x21, 0 - .dw 0xba00, 0xc804, 0xbfff, 0xc804, 0x21, 0 - .dw 0xda00, 0xc804, 0xdfff, 0xc804, 0x21, 0 - .dw 0xfa00, 0xc804, 0xffff, 0xc804, 0x21, 0 - .dw 0x1a00, 0xc805, 0x1fff, 0xc805, 0x21, 0 - .dw 0x3a00, 0xc805, 0x3fff, 0xc805, 0x21, 0 - .dw 0x5a00, 0xc805, 0x5fff, 0xc805, 0x21, 0 - .dw 0x7a00, 0xc805, 0x7fff, 0xc805, 0x21, 0 - .dw 0x9a00, 0xc805, 0x9fff, 0xc805, 0x21, 0 - .dw 0xba00, 0xc805, 0xbfff, 0xc805, 0x21, 0 - .dw 0xda00, 0xc805, 0xdfff, 0xc805, 0x21, 0 - .dw 0xfa00, 0xc805, 0xffff, 0xc805, 0x21, 0 - .dw 0x1a00, 0xc806, 0x1fff, 0xc806, 0x21, 0 - .dw 0x3a00, 0xc806, 0x3fff, 0xc806, 0x21, 0 - .dw 0x5a00, 0xc806, 0x5fff, 0xc806, 0x21, 0 - .dw 0x7a00, 0xc806, 0x7fff, 0xc806, 0x21, 0 - .dw 0x9a00, 0xc806, 0x9fff, 0xc806, 0x21, 0 - .dw 0xba00, 0xc806, 0xbfff, 0xc806, 0x21, 0 - .dw 0xda00, 0xc806, 0xdfff, 0xc806, 0x21, 0 - .dw 0xfa00, 0xc806, 0xffff, 0xc806, 0x21, 0 - .dw 0x1a00, 0xc807, 0x1fff, 0xc807, 0x21, 0 - .dw 0x3a00, 0xc807, 0x1fff, 0xc808, 0x21, 0 - .dw 0x2040, 0xc808, 0x207f, 0xc808, 0x21, 0 - .dw 0x20c0, 0xc808, 0x20ff, 0xc808, 0x21, 0 - .dw 0x2140, 0xc808, 0x217f, 0xc808, 0x21, 0 - .dw 0x21c0, 0xc808, 0x21ff, 0xc808, 0x21, 0 - .dw 0x2240, 0xc808, 0x227f, 0xc808, 0x21, 0 - .dw 0x22c0, 0xc808, 0x22ff, 0xc808, 0x21, 0 - .dw 0x2340, 0xc808, 0x237f, 0xc808, 0x21, 0 - .dw 0x23c0, 0xc808, 0x23ff, 0xc808, 0x21, 0 - .dw 0x2440, 0xc808, 0x247f, 0xc808, 0x21, 0 - .dw 0x24c0, 0xc808, 0x24ff, 0xc808, 0x21, 0 - .dw 0x2540, 0xc808, 0x257f, 0xc808, 0x21, 0 - .dw 0x25c0, 0xc808, 0x25ff, 0xc808, 0x21, 0 - .dw 0x2640, 0xc808, 0x267f, 0xc808, 0x21, 0 - .dw 0x26c0, 0xc808, 0x26ff, 0xc808, 0x21, 0 - .dw 0x2740, 0xc808, 0x277f, 0xc808, 0x21, 0 - .dw 0x27c0, 0xc808, 0x27ff, 0xc808, 0x21, 0 - .dw 0x2840, 0xc808, 0x287f, 0xc808, 0x21, 0 - .dw 0x28c0, 0xc808, 0x28ff, 0xc808, 0x21, 0 - .dw 0x2940, 0xc808, 0x297f, 0xc808, 0x21, 0 - .dw 0x29c0, 0xc808, 0x29ff, 0xc808, 0x21, 0 - .dw 0x2a40, 0xc808, 0x2a7f, 0xc808, 0x21, 0 - .dw 0x2ac0, 0xc808, 0x2aff, 0xc808, 0x21, 0 - .dw 0x2b40, 0xc808, 0x2b7f, 0xc808, 0x21, 0 - .dw 0x2bc0, 0xc808, 0x2bff, 0xc808, 0x21, 0 - .dw 0x2c40, 0xc808, 0x2c7f, 0xc808, 0x21, 0 - .dw 0x2cc0, 0xc808, 0x2cff, 0xc808, 0x21, 0 - .dw 0x2d40, 0xc808, 0x2d7f, 0xc808, 0x21, 0 - .dw 0x2dc0, 0xc808, 0x2dff, 0xc808, 0x21, 0 - .dw 0x2e40, 0xc808, 0x2e7f, 0xc808, 0x21, 0 - .dw 0x2ec0, 0xc808, 0x2eff, 0xc808, 0x21, 0 - .dw 0x2f40, 0xc808, 0x2f7f, 0xc808, 0x21, 0 - .dw 0x2fc0, 0xc808, 0x2fff, 0xc808, 0x21, 0 - .dw 0x3040, 0xc808, 0x307f, 0xc808, 0x21, 0 - .dw 0x30c0, 0xc808, 0x30ff, 0xc808, 0x21, 0 - .dw 0x3140, 0xc808, 0x317f, 0xc808, 0x21, 0 - .dw 0x31c0, 0xc808, 0x31ff, 0xc808, 0x21, 0 - .dw 0x3240, 0xc808, 0x327f, 0xc808, 0x21, 0 - .dw 0x32c0, 0xc808, 0x32ff, 0xc808, 0x21, 0 - .dw 0x3340, 0xc808, 0x337f, 0xc808, 0x21, 0 - .dw 0x33c0, 0xc808, 0x33ff, 0xc808, 0x21, 0 - .dw 0x3440, 0xc808, 0x347f, 0xc808, 0x21, 0 - .dw 0x34c0, 0xc808, 0x34ff, 0xc808, 0x21, 0 - .dw 0x3540, 0xc808, 0x357f, 0xc808, 0x21, 0 - .dw 0x35c0, 0xc808, 0x35ff, 0xc808, 0x21, 0 - .dw 0x3640, 0xc808, 0x367f, 0xc808, 0x21, 0 - .dw 0x36c0, 0xc808, 0x36ff, 0xc808, 0x21, 0 - .dw 0x3740, 0xc808, 0x377f, 0xc808, 0x21, 0 - .dw 0x37c0, 0xc808, 0x37ff, 0xc808, 0x21, 0 - .dw 0x3840, 0xc808, 0x387f, 0xc808, 0x21, 0 - .dw 0x38c0, 0xc808, 0x38ff, 0xc808, 0x21, 0 - .dw 0x3940, 0xc808, 0x397f, 0xc808, 0x21, 0 - .dw 0x39c0, 0xc808, 0x5fff, 0xc808, 0x21, 0 - .dw 0x6040, 0xc808, 0x607f, 0xc808, 0x21, 0 - .dw 0x60c0, 0xc808, 0x60ff, 0xc808, 0x21, 0 - .dw 0x6140, 0xc808, 0x617f, 0xc808, 0x21, 0 - .dw 0x61c0, 0xc808, 0x61ff, 0xc808, 0x21, 0 - .dw 0x6240, 0xc808, 0x627f, 0xc808, 0x21, 0 - .dw 0x62c0, 0xc808, 0x62ff, 0xc808, 0x21, 0 - .dw 0x6340, 0xc808, 0x637f, 0xc808, 0x21, 0 - .dw 0x63c0, 0xc808, 0x63ff, 0xc808, 0x21, 0 - .dw 0x6440, 0xc808, 0x647f, 0xc808, 0x21, 0 - .dw 0x64c0, 0xc808, 0x64ff, 0xc808, 0x21, 0 - .dw 0x6540, 0xc808, 0x657f, 0xc808, 0x21, 0 - .dw 0x65c0, 0xc808, 0x65ff, 0xc808, 0x21, 0 - .dw 0x6640, 0xc808, 0x667f, 0xc808, 0x21, 0 - .dw 0x66c0, 0xc808, 0x66ff, 0xc808, 0x21, 0 - .dw 0x6740, 0xc808, 0x677f, 0xc808, 0x21, 0 - .dw 0x67c0, 0xc808, 0x67ff, 0xc808, 0x21, 0 - .dw 0x6840, 0xc808, 0x687f, 0xc808, 0x21, 0 - .dw 0x68c0, 0xc808, 0x68ff, 0xc808, 0x21, 0 - .dw 0x6940, 0xc808, 0x697f, 0xc808, 0x21, 0 - .dw 0x69c0, 0xc808, 0x69ff, 0xc808, 0x21, 0 - .dw 0x6a40, 0xc808, 0x6a7f, 0xc808, 0x21, 0 - .dw 0x6ac0, 0xc808, 0x6aff, 0xc808, 0x21, 0 - .dw 0x6b40, 0xc808, 0x6b7f, 0xc808, 0x21, 0 - .dw 0x6bc0, 0xc808, 0x6bff, 0xc808, 0x21, 0 - .dw 0x6c40, 0xc808, 0x6c7f, 0xc808, 0x21, 0 - .dw 0x6cc0, 0xc808, 0x6cff, 0xc808, 0x21, 0 - .dw 0x6d40, 0xc808, 0x6d7f, 0xc808, 0x21, 0 - .dw 0x6dc0, 0xc808, 0x6dff, 0xc808, 0x21, 0 - .dw 0x6e40, 0xc808, 0x6e7f, 0xc808, 0x21, 0 - .dw 0x6ec0, 0xc808, 0x6eff, 0xc808, 0x21, 0 - .dw 0x6f40, 0xc808, 0x6f7f, 0xc808, 0x21, 0 - .dw 0x6fc0, 0xc808, 0x6fff, 0xc808, 0x21, 0 - .dw 0x7040, 0xc808, 0x707f, 0xc808, 0x21, 0 - .dw 0x70c0, 0xc808, 0x70ff, 0xc808, 0x21, 0 - .dw 0x7140, 0xc808, 0x717f, 0xc808, 0x21, 0 - .dw 0x71c0, 0xc808, 0x71ff, 0xc808, 0x21, 0 - .dw 0x7240, 0xc808, 0x727f, 0xc808, 0x21, 0 - .dw 0x72c0, 0xc808, 0x72ff, 0xc808, 0x21, 0 - .dw 0x7340, 0xc808, 0x737f, 0xc808, 0x21, 0 - .dw 0x73c0, 0xc808, 0x73ff, 0xc808, 0x21, 0 - .dw 0x7440, 0xc808, 0x747f, 0xc808, 0x21, 0 - .dw 0x74c0, 0xc808, 0x74ff, 0xc808, 0x21, 0 - .dw 0x7540, 0xc808, 0x757f, 0xc808, 0x21, 0 - .dw 0x75c0, 0xc808, 0x75ff, 0xc808, 0x21, 0 - .dw 0x7640, 0xc808, 0x767f, 0xc808, 0x21, 0 - .dw 0x76c0, 0xc808, 0x76ff, 0xc808, 0x21, 0 - .dw 0x7740, 0xc808, 0x777f, 0xc808, 0x21, 0 - .dw 0x77c0, 0xc808, 0x77ff, 0xc808, 0x21, 0 - .dw 0x7840, 0xc808, 0x787f, 0xc808, 0x21, 0 - .dw 0x78c0, 0xc808, 0x78ff, 0xc808, 0x21, 0 - .dw 0x7940, 0xc808, 0x797f, 0xc808, 0x21, 0 - .dw 0x79c0, 0xc808, 0x9fff, 0xc808, 0x21, 0 - .dw 0xa040, 0xc808, 0xa07f, 0xc808, 0x21, 0 - .dw 0xa0c0, 0xc808, 0xa0ff, 0xc808, 0x21, 0 - .dw 0xa140, 0xc808, 0xa17f, 0xc808, 0x21, 0 - .dw 0xa1c0, 0xc808, 0xa1ff, 0xc808, 0x21, 0 - .dw 0xa240, 0xc808, 0xa27f, 0xc808, 0x21, 0 - .dw 0xa2c0, 0xc808, 0xa2ff, 0xc808, 0x21, 0 - .dw 0xa340, 0xc808, 0xa37f, 0xc808, 0x21, 0 - .dw 0xa3c0, 0xc808, 0xa3ff, 0xc808, 0x21, 0 - .dw 0xa440, 0xc808, 0xa47f, 0xc808, 0x21, 0 - .dw 0xa4c0, 0xc808, 0xa4ff, 0xc808, 0x21, 0 - .dw 0xa540, 0xc808, 0xa57f, 0xc808, 0x21, 0 - .dw 0xa5c0, 0xc808, 0xa5ff, 0xc808, 0x21, 0 - .dw 0xa640, 0xc808, 0xa67f, 0xc808, 0x21, 0 - .dw 0xa6c0, 0xc808, 0xa6ff, 0xc808, 0x21, 0 - .dw 0xa740, 0xc808, 0xa77f, 0xc808, 0x21, 0 - .dw 0xa7c0, 0xc808, 0xa7ff, 0xc808, 0x21, 0 - .dw 0xa840, 0xc808, 0xa87f, 0xc808, 0x21, 0 - .dw 0xa8c0, 0xc808, 0xa8ff, 0xc808, 0x21, 0 - .dw 0xa940, 0xc808, 0xa97f, 0xc808, 0x21, 0 - .dw 0xa9c0, 0xc808, 0xa9ff, 0xc808, 0x21, 0 - .dw 0xaa40, 0xc808, 0xaa7f, 0xc808, 0x21, 0 - .dw 0xaac0, 0xc808, 0xaaff, 0xc808, 0x21, 0 - .dw 0xab40, 0xc808, 0xab7f, 0xc808, 0x21, 0 - .dw 0xabc0, 0xc808, 0xabff, 0xc808, 0x21, 0 - .dw 0xac40, 0xc808, 0xac7f, 0xc808, 0x21, 0 - .dw 0xacc0, 0xc808, 0xacff, 0xc808, 0x21, 0 - .dw 0xad40, 0xc808, 0xad7f, 0xc808, 0x21, 0 - .dw 0xadc0, 0xc808, 0xadff, 0xc808, 0x21, 0 - .dw 0xae40, 0xc808, 0xae7f, 0xc808, 0x21, 0 - .dw 0xaec0, 0xc808, 0xaeff, 0xc808, 0x21, 0 - .dw 0xaf40, 0xc808, 0xaf7f, 0xc808, 0x21, 0 - .dw 0xafc0, 0xc808, 0xafff, 0xc808, 0x21, 0 - .dw 0xb040, 0xc808, 0xb07f, 0xc808, 0x21, 0 - .dw 0xb0c0, 0xc808, 0xb0ff, 0xc808, 0x21, 0 - .dw 0xb140, 0xc808, 0xb17f, 0xc808, 0x21, 0 - .dw 0xb1c0, 0xc808, 0xb1ff, 0xc808, 0x21, 0 - .dw 0xb240, 0xc808, 0xb27f, 0xc808, 0x21, 0 - .dw 0xb2c0, 0xc808, 0xb2ff, 0xc808, 0x21, 0 - .dw 0xb340, 0xc808, 0xb37f, 0xc808, 0x21, 0 - .dw 0xb3c0, 0xc808, 0xb3ff, 0xc808, 0x21, 0 - .dw 0xb440, 0xc808, 0xb47f, 0xc808, 0x21, 0 - .dw 0xb4c0, 0xc808, 0xb4ff, 0xc808, 0x21, 0 - .dw 0xb540, 0xc808, 0xb57f, 0xc808, 0x21, 0 - .dw 0xb5c0, 0xc808, 0xb5ff, 0xc808, 0x21, 0 - .dw 0xb640, 0xc808, 0xb67f, 0xc808, 0x21, 0 - .dw 0xb6c0, 0xc808, 0xb6ff, 0xc808, 0x21, 0 - .dw 0xb740, 0xc808, 0xb77f, 0xc808, 0x21, 0 - .dw 0xb7c0, 0xc808, 0xb7ff, 0xc808, 0x21, 0 - .dw 0xb840, 0xc808, 0xb87f, 0xc808, 0x21, 0 - .dw 0xb8c0, 0xc808, 0xb8ff, 0xc808, 0x21, 0 - .dw 0xb940, 0xc808, 0xb97f, 0xc808, 0x21, 0 - .dw 0xb9c0, 0xc808, 0xdfff, 0xc808, 0x21, 0 - .dw 0xe040, 0xc808, 0xe07f, 0xc808, 0x21, 0 - .dw 0xe0c0, 0xc808, 0xe0ff, 0xc808, 0x21, 0 - .dw 0xe140, 0xc808, 0xe17f, 0xc808, 0x21, 0 - .dw 0xe1c0, 0xc808, 0xe1ff, 0xc808, 0x21, 0 - .dw 0xe240, 0xc808, 0xe27f, 0xc808, 0x21, 0 - .dw 0xe2c0, 0xc808, 0xe2ff, 0xc808, 0x21, 0 - .dw 0xe340, 0xc808, 0xe37f, 0xc808, 0x21, 0 - .dw 0xe3c0, 0xc808, 0xe3ff, 0xc808, 0x21, 0 - .dw 0xe440, 0xc808, 0xe47f, 0xc808, 0x21, 0 - .dw 0xe4c0, 0xc808, 0xe4ff, 0xc808, 0x21, 0 - .dw 0xe540, 0xc808, 0xe57f, 0xc808, 0x21, 0 - .dw 0xe5c0, 0xc808, 0xe5ff, 0xc808, 0x21, 0 - .dw 0xe640, 0xc808, 0xe67f, 0xc808, 0x21, 0 - .dw 0xe6c0, 0xc808, 0xe6ff, 0xc808, 0x21, 0 - .dw 0xe740, 0xc808, 0xe77f, 0xc808, 0x21, 0 - .dw 0xe7c0, 0xc808, 0xe7ff, 0xc808, 0x21, 0 - .dw 0xe840, 0xc808, 0xe87f, 0xc808, 0x21, 0 - .dw 0xe8c0, 0xc808, 0xe8ff, 0xc808, 0x21, 0 - .dw 0xe940, 0xc808, 0xe97f, 0xc808, 0x21, 0 - .dw 0xe9c0, 0xc808, 0xe9ff, 0xc808, 0x21, 0 - .dw 0xea40, 0xc808, 0xea7f, 0xc808, 0x21, 0 - .dw 0xeac0, 0xc808, 0xeaff, 0xc808, 0x21, 0 - .dw 0xeb40, 0xc808, 0xeb7f, 0xc808, 0x21, 0 - .dw 0xebc0, 0xc808, 0xebff, 0xc808, 0x21, 0 - .dw 0xec40, 0xc808, 0xec7f, 0xc808, 0x21, 0 - .dw 0xecc0, 0xc808, 0xecff, 0xc808, 0x21, 0 - .dw 0xed40, 0xc808, 0xed7f, 0xc808, 0x21, 0 - .dw 0xedc0, 0xc808, 0xedff, 0xc808, 0x21, 0 - .dw 0xee40, 0xc808, 0xee7f, 0xc808, 0x21, 0 - .dw 0xeec0, 0xc808, 0xeeff, 0xc808, 0x21, 0 - .dw 0xef40, 0xc808, 0xef7f, 0xc808, 0x21, 0 - .dw 0xefc0, 0xc808, 0xefff, 0xc808, 0x21, 0 - .dw 0xf040, 0xc808, 0xf07f, 0xc808, 0x21, 0 - .dw 0xf0c0, 0xc808, 0xf0ff, 0xc808, 0x21, 0 - .dw 0xf140, 0xc808, 0xf17f, 0xc808, 0x21, 0 - .dw 0xf1c0, 0xc808, 0xf1ff, 0xc808, 0x21, 0 - .dw 0xf240, 0xc808, 0xf27f, 0xc808, 0x21, 0 - .dw 0xf2c0, 0xc808, 0xf2ff, 0xc808, 0x21, 0 - .dw 0xf340, 0xc808, 0xf37f, 0xc808, 0x21, 0 - .dw 0xf3c0, 0xc808, 0xf3ff, 0xc808, 0x21, 0 - .dw 0xf440, 0xc808, 0xf47f, 0xc808, 0x21, 0 - .dw 0xf4c0, 0xc808, 0xf4ff, 0xc808, 0x21, 0 - .dw 0xf540, 0xc808, 0xf57f, 0xc808, 0x21, 0 - .dw 0xf5c0, 0xc808, 0xf5ff, 0xc808, 0x21, 0 - .dw 0xf640, 0xc808, 0xf67f, 0xc808, 0x21, 0 - .dw 0xf6c0, 0xc808, 0xf6ff, 0xc808, 0x21, 0 - .dw 0xf740, 0xc808, 0xf77f, 0xc808, 0x21, 0 - .dw 0xf7c0, 0xc808, 0xf7ff, 0xc808, 0x21, 0 - .dw 0xf840, 0xc808, 0xf87f, 0xc808, 0x21, 0 - .dw 0xf8c0, 0xc808, 0xf8ff, 0xc808, 0x21, 0 - .dw 0xf940, 0xc808, 0xf97f, 0xc808, 0x21, 0 - .dw 0xf9c0, 0xc808, 0x1fff, 0xc809, 0x21, 0 - .dw 0x2040, 0xc809, 0x207f, 0xc809, 0x21, 0 - .dw 0x20c0, 0xc809, 0x20ff, 0xc809, 0x21, 0 - .dw 0x2140, 0xc809, 0x217f, 0xc809, 0x21, 0 - .dw 0x21c0, 0xc809, 0x21ff, 0xc809, 0x21, 0 - .dw 0x2240, 0xc809, 0x227f, 0xc809, 0x21, 0 - .dw 0x22c0, 0xc809, 0x22ff, 0xc809, 0x21, 0 - .dw 0x2340, 0xc809, 0x237f, 0xc809, 0x21, 0 - .dw 0x23c0, 0xc809, 0x23ff, 0xc809, 0x21, 0 - .dw 0x2440, 0xc809, 0x247f, 0xc809, 0x21, 0 - .dw 0x24c0, 0xc809, 0x24ff, 0xc809, 0x21, 0 - .dw 0x2540, 0xc809, 0x257f, 0xc809, 0x21, 0 - .dw 0x25c0, 0xc809, 0x25ff, 0xc809, 0x21, 0 - .dw 0x2640, 0xc809, 0x267f, 0xc809, 0x21, 0 - .dw 0x26c0, 0xc809, 0x26ff, 0xc809, 0x21, 0 - .dw 0x2740, 0xc809, 0x277f, 0xc809, 0x21, 0 - .dw 0x27c0, 0xc809, 0x27ff, 0xc809, 0x21, 0 - .dw 0x2840, 0xc809, 0x287f, 0xc809, 0x21, 0 - .dw 0x28c0, 0xc809, 0x28ff, 0xc809, 0x21, 0 - .dw 0x2940, 0xc809, 0x297f, 0xc809, 0x21, 0 - .dw 0x29c0, 0xc809, 0x29ff, 0xc809, 0x21, 0 - .dw 0x2a40, 0xc809, 0x2a7f, 0xc809, 0x21, 0 - .dw 0x2ac0, 0xc809, 0x2aff, 0xc809, 0x21, 0 - .dw 0x2b40, 0xc809, 0x2b7f, 0xc809, 0x21, 0 - .dw 0x2bc0, 0xc809, 0x2bff, 0xc809, 0x21, 0 - .dw 0x2c40, 0xc809, 0x2c7f, 0xc809, 0x21, 0 - .dw 0x2cc0, 0xc809, 0x2cff, 0xc809, 0x21, 0 - .dw 0x2d40, 0xc809, 0x2d7f, 0xc809, 0x21, 0 - .dw 0x2dc0, 0xc809, 0x2dff, 0xc809, 0x21, 0 - .dw 0x2e40, 0xc809, 0x2e7f, 0xc809, 0x21, 0 - .dw 0x2ec0, 0xc809, 0x2eff, 0xc809, 0x21, 0 - .dw 0x2f40, 0xc809, 0x2f7f, 0xc809, 0x21, 0 - .dw 0x2fc0, 0xc809, 0x2fff, 0xc809, 0x21, 0 - .dw 0x3040, 0xc809, 0x307f, 0xc809, 0x21, 0 - .dw 0x30c0, 0xc809, 0x30ff, 0xc809, 0x21, 0 - .dw 0x3140, 0xc809, 0x317f, 0xc809, 0x21, 0 - .dw 0x31c0, 0xc809, 0x31ff, 0xc809, 0x21, 0 - .dw 0x3240, 0xc809, 0x327f, 0xc809, 0x21, 0 - .dw 0x32c0, 0xc809, 0x32ff, 0xc809, 0x21, 0 - .dw 0x3340, 0xc809, 0x337f, 0xc809, 0x21, 0 - .dw 0x33c0, 0xc809, 0x33ff, 0xc809, 0x21, 0 - .dw 0x3440, 0xc809, 0x347f, 0xc809, 0x21, 0 - .dw 0x34c0, 0xc809, 0x34ff, 0xc809, 0x21, 0 - .dw 0x3540, 0xc809, 0x357f, 0xc809, 0x21, 0 - .dw 0x35c0, 0xc809, 0x35ff, 0xc809, 0x21, 0 - .dw 0x3640, 0xc809, 0x367f, 0xc809, 0x21, 0 - .dw 0x36c0, 0xc809, 0x36ff, 0xc809, 0x21, 0 - .dw 0x3740, 0xc809, 0x377f, 0xc809, 0x21, 0 - .dw 0x37c0, 0xc809, 0x37ff, 0xc809, 0x21, 0 - .dw 0x3840, 0xc809, 0x387f, 0xc809, 0x21, 0 - .dw 0x38c0, 0xc809, 0x38ff, 0xc809, 0x21, 0 - .dw 0x3940, 0xc809, 0x397f, 0xc809, 0x21, 0 - .dw 0x39c0, 0xc809, 0x5fff, 0xc809, 0x21, 0 - .dw 0x6040, 0xc809, 0x607f, 0xc809, 0x21, 0 - .dw 0x60c0, 0xc809, 0x60ff, 0xc809, 0x21, 0 - .dw 0x6140, 0xc809, 0x617f, 0xc809, 0x21, 0 - .dw 0x61c0, 0xc809, 0x61ff, 0xc809, 0x21, 0 - .dw 0x6240, 0xc809, 0x627f, 0xc809, 0x21, 0 - .dw 0x62c0, 0xc809, 0x62ff, 0xc809, 0x21, 0 - .dw 0x6340, 0xc809, 0x637f, 0xc809, 0x21, 0 - .dw 0x63c0, 0xc809, 0x63ff, 0xc809, 0x21, 0 - .dw 0x6440, 0xc809, 0x647f, 0xc809, 0x21, 0 - .dw 0x64c0, 0xc809, 0x64ff, 0xc809, 0x21, 0 - .dw 0x6540, 0xc809, 0x657f, 0xc809, 0x21, 0 - .dw 0x65c0, 0xc809, 0x65ff, 0xc809, 0x21, 0 - .dw 0x6640, 0xc809, 0x667f, 0xc809, 0x21, 0 - .dw 0x66c0, 0xc809, 0x66ff, 0xc809, 0x21, 0 - .dw 0x6740, 0xc809, 0x677f, 0xc809, 0x21, 0 - .dw 0x67c0, 0xc809, 0x67ff, 0xc809, 0x21, 0 - .dw 0x6840, 0xc809, 0x687f, 0xc809, 0x21, 0 - .dw 0x68c0, 0xc809, 0x68ff, 0xc809, 0x21, 0 - .dw 0x6940, 0xc809, 0x697f, 0xc809, 0x21, 0 - .dw 0x69c0, 0xc809, 0x69ff, 0xc809, 0x21, 0 - .dw 0x6a40, 0xc809, 0x6a7f, 0xc809, 0x21, 0 - .dw 0x6ac0, 0xc809, 0x6aff, 0xc809, 0x21, 0 - .dw 0x6b40, 0xc809, 0x6b7f, 0xc809, 0x21, 0 - .dw 0x6bc0, 0xc809, 0x6bff, 0xc809, 0x21, 0 - .dw 0x6c40, 0xc809, 0x6c7f, 0xc809, 0x21, 0 - .dw 0x6cc0, 0xc809, 0x6cff, 0xc809, 0x21, 0 - .dw 0x6d40, 0xc809, 0x6d7f, 0xc809, 0x21, 0 - .dw 0x6dc0, 0xc809, 0x6dff, 0xc809, 0x21, 0 - .dw 0x6e40, 0xc809, 0x6e7f, 0xc809, 0x21, 0 - .dw 0x6ec0, 0xc809, 0x6eff, 0xc809, 0x21, 0 - .dw 0x6f40, 0xc809, 0x6f7f, 0xc809, 0x21, 0 - .dw 0x6fc0, 0xc809, 0x6fff, 0xc809, 0x21, 0 - .dw 0x7040, 0xc809, 0x707f, 0xc809, 0x21, 0 - .dw 0x70c0, 0xc809, 0x70ff, 0xc809, 0x21, 0 - .dw 0x7140, 0xc809, 0x717f, 0xc809, 0x21, 0 - .dw 0x71c0, 0xc809, 0x71ff, 0xc809, 0x21, 0 - .dw 0x7240, 0xc809, 0x727f, 0xc809, 0x21, 0 - .dw 0x72c0, 0xc809, 0x72ff, 0xc809, 0x21, 0 - .dw 0x7340, 0xc809, 0x737f, 0xc809, 0x21, 0 - .dw 0x73c0, 0xc809, 0x73ff, 0xc809, 0x21, 0 - .dw 0x7440, 0xc809, 0x747f, 0xc809, 0x21, 0 - .dw 0x74c0, 0xc809, 0x74ff, 0xc809, 0x21, 0 - .dw 0x7540, 0xc809, 0x757f, 0xc809, 0x21, 0 - .dw 0x75c0, 0xc809, 0x75ff, 0xc809, 0x21, 0 - .dw 0x7640, 0xc809, 0x767f, 0xc809, 0x21, 0 - .dw 0x76c0, 0xc809, 0x76ff, 0xc809, 0x21, 0 - .dw 0x7740, 0xc809, 0x777f, 0xc809, 0x21, 0 - .dw 0x77c0, 0xc809, 0x77ff, 0xc809, 0x21, 0 - .dw 0x7840, 0xc809, 0x787f, 0xc809, 0x21, 0 - .dw 0x78c0, 0xc809, 0x78ff, 0xc809, 0x21, 0 - .dw 0x7940, 0xc809, 0x797f, 0xc809, 0x21, 0 - .dw 0x79c0, 0xc809, 0x9fff, 0xc809, 0x21, 0 - .dw 0xa040, 0xc809, 0xa07f, 0xc809, 0x21, 0 - .dw 0xa0c0, 0xc809, 0xa0ff, 0xc809, 0x21, 0 - .dw 0xa140, 0xc809, 0xa17f, 0xc809, 0x21, 0 - .dw 0xa1c0, 0xc809, 0xa1ff, 0xc809, 0x21, 0 - .dw 0xa240, 0xc809, 0xa27f, 0xc809, 0x21, 0 - .dw 0xa2c0, 0xc809, 0xa2ff, 0xc809, 0x21, 0 - .dw 0xa340, 0xc809, 0xa37f, 0xc809, 0x21, 0 - .dw 0xa3c0, 0xc809, 0xa3ff, 0xc809, 0x21, 0 - .dw 0xa440, 0xc809, 0xa47f, 0xc809, 0x21, 0 - .dw 0xa4c0, 0xc809, 0xa4ff, 0xc809, 0x21, 0 - .dw 0xa540, 0xc809, 0xa57f, 0xc809, 0x21, 0 - .dw 0xa5c0, 0xc809, 0xa5ff, 0xc809, 0x21, 0 - .dw 0xa640, 0xc809, 0xa67f, 0xc809, 0x21, 0 - .dw 0xa6c0, 0xc809, 0xa6ff, 0xc809, 0x21, 0 - .dw 0xa740, 0xc809, 0xa77f, 0xc809, 0x21, 0 - .dw 0xa7c0, 0xc809, 0xa7ff, 0xc809, 0x21, 0 - .dw 0xa840, 0xc809, 0xa87f, 0xc809, 0x21, 0 - .dw 0xa8c0, 0xc809, 0xa8ff, 0xc809, 0x21, 0 - .dw 0xa940, 0xc809, 0xa97f, 0xc809, 0x21, 0 - .dw 0xa9c0, 0xc809, 0xa9ff, 0xc809, 0x21, 0 - .dw 0xaa40, 0xc809, 0xaa7f, 0xc809, 0x21, 0 - .dw 0xaac0, 0xc809, 0xaaff, 0xc809, 0x21, 0 - .dw 0xab40, 0xc809, 0xab7f, 0xc809, 0x21, 0 - .dw 0xabc0, 0xc809, 0xabff, 0xc809, 0x21, 0 - .dw 0xac40, 0xc809, 0xac7f, 0xc809, 0x21, 0 - .dw 0xacc0, 0xc809, 0xacff, 0xc809, 0x21, 0 - .dw 0xad40, 0xc809, 0xad7f, 0xc809, 0x21, 0 - .dw 0xadc0, 0xc809, 0xadff, 0xc809, 0x21, 0 - .dw 0xae40, 0xc809, 0xae7f, 0xc809, 0x21, 0 - .dw 0xaec0, 0xc809, 0xaeff, 0xc809, 0x21, 0 - .dw 0xaf40, 0xc809, 0xaf7f, 0xc809, 0x21, 0 - .dw 0xafc0, 0xc809, 0xafff, 0xc809, 0x21, 0 - .dw 0xb040, 0xc809, 0xb07f, 0xc809, 0x21, 0 - .dw 0xb0c0, 0xc809, 0xb0ff, 0xc809, 0x21, 0 - .dw 0xb140, 0xc809, 0xb17f, 0xc809, 0x21, 0 - .dw 0xb1c0, 0xc809, 0xb1ff, 0xc809, 0x21, 0 - .dw 0xb240, 0xc809, 0xb27f, 0xc809, 0x21, 0 - .dw 0xb2c0, 0xc809, 0xb2ff, 0xc809, 0x21, 0 - .dw 0xb340, 0xc809, 0xb37f, 0xc809, 0x21, 0 - .dw 0xb3c0, 0xc809, 0xb3ff, 0xc809, 0x21, 0 - .dw 0xb440, 0xc809, 0xb47f, 0xc809, 0x21, 0 - .dw 0xb4c0, 0xc809, 0xb4ff, 0xc809, 0x21, 0 - .dw 0xb540, 0xc809, 0xb57f, 0xc809, 0x21, 0 - .dw 0xb5c0, 0xc809, 0xb5ff, 0xc809, 0x21, 0 - .dw 0xb640, 0xc809, 0xb67f, 0xc809, 0x21, 0 - .dw 0xb6c0, 0xc809, 0xb6ff, 0xc809, 0x21, 0 - .dw 0xb740, 0xc809, 0xb77f, 0xc809, 0x21, 0 - .dw 0xb7c0, 0xc809, 0xb7ff, 0xc809, 0x21, 0 - .dw 0xb840, 0xc809, 0xb87f, 0xc809, 0x21, 0 - .dw 0xb8c0, 0xc809, 0xb8ff, 0xc809, 0x21, 0 - .dw 0xb940, 0xc809, 0xb97f, 0xc809, 0x21, 0 - .dw 0xb9c0, 0xc809, 0xdfff, 0xc809, 0x21, 0 - .dw 0xe040, 0xc809, 0xe07f, 0xc809, 0x21, 0 - .dw 0xe0c0, 0xc809, 0xe0ff, 0xc809, 0x21, 0 - .dw 0xe140, 0xc809, 0xe17f, 0xc809, 0x21, 0 - .dw 0xe1c0, 0xc809, 0xe1ff, 0xc809, 0x21, 0 - .dw 0xe240, 0xc809, 0xe27f, 0xc809, 0x21, 0 - .dw 0xe2c0, 0xc809, 0xe2ff, 0xc809, 0x21, 0 - .dw 0xe340, 0xc809, 0xe37f, 0xc809, 0x21, 0 - .dw 0xe3c0, 0xc809, 0xe3ff, 0xc809, 0x21, 0 - .dw 0xe440, 0xc809, 0xe47f, 0xc809, 0x21, 0 - .dw 0xe4c0, 0xc809, 0xe4ff, 0xc809, 0x21, 0 - .dw 0xe540, 0xc809, 0xe57f, 0xc809, 0x21, 0 - .dw 0xe5c0, 0xc809, 0xe5ff, 0xc809, 0x21, 0 - .dw 0xe640, 0xc809, 0xe67f, 0xc809, 0x21, 0 - .dw 0xe6c0, 0xc809, 0xe6ff, 0xc809, 0x21, 0 - .dw 0xe740, 0xc809, 0xe77f, 0xc809, 0x21, 0 - .dw 0xe7c0, 0xc809, 0xe7ff, 0xc809, 0x21, 0 - .dw 0xe840, 0xc809, 0xe87f, 0xc809, 0x21, 0 - .dw 0xe8c0, 0xc809, 0xe8ff, 0xc809, 0x21, 0 - .dw 0xe940, 0xc809, 0xe97f, 0xc809, 0x21, 0 - .dw 0xe9c0, 0xc809, 0xe9ff, 0xc809, 0x21, 0 - .dw 0xea40, 0xc809, 0xea7f, 0xc809, 0x21, 0 - .dw 0xeac0, 0xc809, 0xeaff, 0xc809, 0x21, 0 - .dw 0xeb40, 0xc809, 0xeb7f, 0xc809, 0x21, 0 - .dw 0xebc0, 0xc809, 0xebff, 0xc809, 0x21, 0 - .dw 0xec40, 0xc809, 0xec7f, 0xc809, 0x21, 0 - .dw 0xecc0, 0xc809, 0xecff, 0xc809, 0x21, 0 - .dw 0xed40, 0xc809, 0xed7f, 0xc809, 0x21, 0 - .dw 0xedc0, 0xc809, 0xedff, 0xc809, 0x21, 0 - .dw 0xee40, 0xc809, 0xee7f, 0xc809, 0x21, 0 - .dw 0xeec0, 0xc809, 0xeeff, 0xc809, 0x21, 0 - .dw 0xef40, 0xc809, 0xef7f, 0xc809, 0x21, 0 - .dw 0xefc0, 0xc809, 0xefff, 0xc809, 0x21, 0 - .dw 0xf040, 0xc809, 0xf07f, 0xc809, 0x21, 0 - .dw 0xf0c0, 0xc809, 0xf0ff, 0xc809, 0x21, 0 - .dw 0xf140, 0xc809, 0xf17f, 0xc809, 0x21, 0 - .dw 0xf1c0, 0xc809, 0xf1ff, 0xc809, 0x21, 0 - .dw 0xf240, 0xc809, 0xf27f, 0xc809, 0x21, 0 - .dw 0xf2c0, 0xc809, 0xf2ff, 0xc809, 0x21, 0 - .dw 0xf340, 0xc809, 0xf37f, 0xc809, 0x21, 0 - .dw 0xf3c0, 0xc809, 0xf3ff, 0xc809, 0x21, 0 - .dw 0xf440, 0xc809, 0xf47f, 0xc809, 0x21, 0 - .dw 0xf4c0, 0xc809, 0xf4ff, 0xc809, 0x21, 0 - .dw 0xf540, 0xc809, 0xf57f, 0xc809, 0x21, 0 - .dw 0xf5c0, 0xc809, 0xf5ff, 0xc809, 0x21, 0 - .dw 0xf640, 0xc809, 0xf67f, 0xc809, 0x21, 0 - .dw 0xf6c0, 0xc809, 0xf6ff, 0xc809, 0x21, 0 - .dw 0xf740, 0xc809, 0xf77f, 0xc809, 0x21, 0 - .dw 0xf7c0, 0xc809, 0xf7ff, 0xc809, 0x21, 0 - .dw 0xf840, 0xc809, 0xf87f, 0xc809, 0x21, 0 - .dw 0xf8c0, 0xc809, 0xf8ff, 0xc809, 0x21, 0 - .dw 0xf940, 0xc809, 0xf97f, 0xc809, 0x21, 0 - .dw 0xf9c0, 0xc809, 0x1fff, 0xc80a, 0x21, 0 - .dw 0x2040, 0xc80a, 0x207f, 0xc80a, 0x21, 0 - .dw 0x20c0, 0xc80a, 0x20ff, 0xc80a, 0x21, 0 - .dw 0x2140, 0xc80a, 0x217f, 0xc80a, 0x21, 0 - .dw 0x21c0, 0xc80a, 0x21ff, 0xc80a, 0x21, 0 - .dw 0x2240, 0xc80a, 0x227f, 0xc80a, 0x21, 0 - .dw 0x22c0, 0xc80a, 0x22ff, 0xc80a, 0x21, 0 - .dw 0x2340, 0xc80a, 0x237f, 0xc80a, 0x21, 0 - .dw 0x23c0, 0xc80a, 0x23ff, 0xc80a, 0x21, 0 - .dw 0x2440, 0xc80a, 0x247f, 0xc80a, 0x21, 0 - .dw 0x24c0, 0xc80a, 0x24ff, 0xc80a, 0x21, 0 - .dw 0x2540, 0xc80a, 0x257f, 0xc80a, 0x21, 0 - .dw 0x25c0, 0xc80a, 0x25ff, 0xc80a, 0x21, 0 - .dw 0x2640, 0xc80a, 0x267f, 0xc80a, 0x21, 0 - .dw 0x26c0, 0xc80a, 0x26ff, 0xc80a, 0x21, 0 - .dw 0x2740, 0xc80a, 0x277f, 0xc80a, 0x21, 0 - .dw 0x27c0, 0xc80a, 0x27ff, 0xc80a, 0x21, 0 - .dw 0x2840, 0xc80a, 0x287f, 0xc80a, 0x21, 0 - .dw 0x28c0, 0xc80a, 0x28ff, 0xc80a, 0x21, 0 - .dw 0x2940, 0xc80a, 0x297f, 0xc80a, 0x21, 0 - .dw 0x29c0, 0xc80a, 0x29ff, 0xc80a, 0x21, 0 - .dw 0x2a40, 0xc80a, 0x2a7f, 0xc80a, 0x21, 0 - .dw 0x2ac0, 0xc80a, 0x2aff, 0xc80a, 0x21, 0 - .dw 0x2b40, 0xc80a, 0x2b7f, 0xc80a, 0x21, 0 - .dw 0x2bc0, 0xc80a, 0x2bff, 0xc80a, 0x21, 0 - .dw 0x2c40, 0xc80a, 0x2c7f, 0xc80a, 0x21, 0 - .dw 0x2cc0, 0xc80a, 0x2cff, 0xc80a, 0x21, 0 - .dw 0x2d40, 0xc80a, 0x2d7f, 0xc80a, 0x21, 0 - .dw 0x2dc0, 0xc80a, 0x2dff, 0xc80a, 0x21, 0 - .dw 0x2e40, 0xc80a, 0x2e7f, 0xc80a, 0x21, 0 - .dw 0x2ec0, 0xc80a, 0x2eff, 0xc80a, 0x21, 0 - .dw 0x2f40, 0xc80a, 0x2f7f, 0xc80a, 0x21, 0 - .dw 0x2fc0, 0xc80a, 0x2fff, 0xc80a, 0x21, 0 - .dw 0x3040, 0xc80a, 0x307f, 0xc80a, 0x21, 0 - .dw 0x30c0, 0xc80a, 0x30ff, 0xc80a, 0x21, 0 - .dw 0x3140, 0xc80a, 0x317f, 0xc80a, 0x21, 0 - .dw 0x31c0, 0xc80a, 0x31ff, 0xc80a, 0x21, 0 - .dw 0x3240, 0xc80a, 0x327f, 0xc80a, 0x21, 0 - .dw 0x32c0, 0xc80a, 0x32ff, 0xc80a, 0x21, 0 - .dw 0x3340, 0xc80a, 0x337f, 0xc80a, 0x21, 0 - .dw 0x33c0, 0xc80a, 0x33ff, 0xc80a, 0x21, 0 - .dw 0x3440, 0xc80a, 0x347f, 0xc80a, 0x21, 0 - .dw 0x34c0, 0xc80a, 0x34ff, 0xc80a, 0x21, 0 - .dw 0x3540, 0xc80a, 0x357f, 0xc80a, 0x21, 0 - .dw 0x35c0, 0xc80a, 0x35ff, 0xc80a, 0x21, 0 - .dw 0x3640, 0xc80a, 0x367f, 0xc80a, 0x21, 0 - .dw 0x36c0, 0xc80a, 0x36ff, 0xc80a, 0x21, 0 - .dw 0x3740, 0xc80a, 0x377f, 0xc80a, 0x21, 0 - .dw 0x37c0, 0xc80a, 0x37ff, 0xc80a, 0x21, 0 - .dw 0x3840, 0xc80a, 0x387f, 0xc80a, 0x21, 0 - .dw 0x38c0, 0xc80a, 0x38ff, 0xc80a, 0x21, 0 - .dw 0x3940, 0xc80a, 0x397f, 0xc80a, 0x21, 0 - .dw 0x39c0, 0xc80a, 0x5fff, 0xc80a, 0x21, 0 - .dw 0x6040, 0xc80a, 0x607f, 0xc80a, 0x21, 0 - .dw 0x60c0, 0xc80a, 0x60ff, 0xc80a, 0x21, 0 - .dw 0x6140, 0xc80a, 0x617f, 0xc80a, 0x21, 0 - .dw 0x61c0, 0xc80a, 0x61ff, 0xc80a, 0x21, 0 - .dw 0x6240, 0xc80a, 0x627f, 0xc80a, 0x21, 0 - .dw 0x62c0, 0xc80a, 0x62ff, 0xc80a, 0x21, 0 - .dw 0x6340, 0xc80a, 0x637f, 0xc80a, 0x21, 0 - .dw 0x63c0, 0xc80a, 0x63ff, 0xc80a, 0x21, 0 - .dw 0x6440, 0xc80a, 0x647f, 0xc80a, 0x21, 0 - .dw 0x64c0, 0xc80a, 0x64ff, 0xc80a, 0x21, 0 - .dw 0x6540, 0xc80a, 0x657f, 0xc80a, 0x21, 0 - .dw 0x65c0, 0xc80a, 0x65ff, 0xc80a, 0x21, 0 - .dw 0x6640, 0xc80a, 0x667f, 0xc80a, 0x21, 0 - .dw 0x66c0, 0xc80a, 0x66ff, 0xc80a, 0x21, 0 - .dw 0x6740, 0xc80a, 0x677f, 0xc80a, 0x21, 0 - .dw 0x67c0, 0xc80a, 0x67ff, 0xc80a, 0x21, 0 - .dw 0x6840, 0xc80a, 0x687f, 0xc80a, 0x21, 0 - .dw 0x68c0, 0xc80a, 0x68ff, 0xc80a, 0x21, 0 - .dw 0x6940, 0xc80a, 0x697f, 0xc80a, 0x21, 0 - .dw 0x69c0, 0xc80a, 0x69ff, 0xc80a, 0x21, 0 - .dw 0x6a40, 0xc80a, 0x6a7f, 0xc80a, 0x21, 0 - .dw 0x6ac0, 0xc80a, 0x6aff, 0xc80a, 0x21, 0 - .dw 0x6b40, 0xc80a, 0x6b7f, 0xc80a, 0x21, 0 - .dw 0x6bc0, 0xc80a, 0x6bff, 0xc80a, 0x21, 0 - .dw 0x6c40, 0xc80a, 0x6c7f, 0xc80a, 0x21, 0 - .dw 0x6cc0, 0xc80a, 0x6cff, 0xc80a, 0x21, 0 - .dw 0x6d40, 0xc80a, 0x6d7f, 0xc80a, 0x21, 0 - .dw 0x6dc0, 0xc80a, 0x6dff, 0xc80a, 0x21, 0 - .dw 0x6e40, 0xc80a, 0x6e7f, 0xc80a, 0x21, 0 - .dw 0x6ec0, 0xc80a, 0x6eff, 0xc80a, 0x21, 0 - .dw 0x6f40, 0xc80a, 0x6f7f, 0xc80a, 0x21, 0 - .dw 0x6fc0, 0xc80a, 0x6fff, 0xc80a, 0x21, 0 - .dw 0x7040, 0xc80a, 0x707f, 0xc80a, 0x21, 0 - .dw 0x70c0, 0xc80a, 0x70ff, 0xc80a, 0x21, 0 - .dw 0x7140, 0xc80a, 0x717f, 0xc80a, 0x21, 0 - .dw 0x71c0, 0xc80a, 0x71ff, 0xc80a, 0x21, 0 - .dw 0x7240, 0xc80a, 0x727f, 0xc80a, 0x21, 0 - .dw 0x72c0, 0xc80a, 0x72ff, 0xc80a, 0x21, 0 - .dw 0x7340, 0xc80a, 0x737f, 0xc80a, 0x21, 0 - .dw 0x73c0, 0xc80a, 0x73ff, 0xc80a, 0x21, 0 - .dw 0x7440, 0xc80a, 0x747f, 0xc80a, 0x21, 0 - .dw 0x74c0, 0xc80a, 0x74ff, 0xc80a, 0x21, 0 - .dw 0x7540, 0xc80a, 0x757f, 0xc80a, 0x21, 0 - .dw 0x75c0, 0xc80a, 0x75ff, 0xc80a, 0x21, 0 - .dw 0x7640, 0xc80a, 0x767f, 0xc80a, 0x21, 0 - .dw 0x76c0, 0xc80a, 0x76ff, 0xc80a, 0x21, 0 - .dw 0x7740, 0xc80a, 0x777f, 0xc80a, 0x21, 0 - .dw 0x77c0, 0xc80a, 0x77ff, 0xc80a, 0x21, 0 - .dw 0x7840, 0xc80a, 0x787f, 0xc80a, 0x21, 0 - .dw 0x78c0, 0xc80a, 0x78ff, 0xc80a, 0x21, 0 - .dw 0x7940, 0xc80a, 0x797f, 0xc80a, 0x21, 0 - .dw 0x79c0, 0xc80a, 0x9fff, 0xc80a, 0x21, 0 - .dw 0xa040, 0xc80a, 0xa07f, 0xc80a, 0x21, 0 - .dw 0xa0c0, 0xc80a, 0xa0ff, 0xc80a, 0x21, 0 - .dw 0xa140, 0xc80a, 0xa17f, 0xc80a, 0x21, 0 - .dw 0xa1c0, 0xc80a, 0xa1ff, 0xc80a, 0x21, 0 - .dw 0xa240, 0xc80a, 0xa27f, 0xc80a, 0x21, 0 - .dw 0xa2c0, 0xc80a, 0xa2ff, 0xc80a, 0x21, 0 - .dw 0xa340, 0xc80a, 0xa37f, 0xc80a, 0x21, 0 - .dw 0xa3c0, 0xc80a, 0xa3ff, 0xc80a, 0x21, 0 - .dw 0xa440, 0xc80a, 0xa47f, 0xc80a, 0x21, 0 - .dw 0xa4c0, 0xc80a, 0xa4ff, 0xc80a, 0x21, 0 - .dw 0xa540, 0xc80a, 0xa57f, 0xc80a, 0x21, 0 - .dw 0xa5c0, 0xc80a, 0xa5ff, 0xc80a, 0x21, 0 - .dw 0xa640, 0xc80a, 0xa67f, 0xc80a, 0x21, 0 - .dw 0xa6c0, 0xc80a, 0xa6ff, 0xc80a, 0x21, 0 - .dw 0xa740, 0xc80a, 0xa77f, 0xc80a, 0x21, 0 - .dw 0xa7c0, 0xc80a, 0xa7ff, 0xc80a, 0x21, 0 - .dw 0xa840, 0xc80a, 0xa87f, 0xc80a, 0x21, 0 - .dw 0xa8c0, 0xc80a, 0xa8ff, 0xc80a, 0x21, 0 - .dw 0xa940, 0xc80a, 0xa97f, 0xc80a, 0x21, 0 - .dw 0xa9c0, 0xc80a, 0xa9ff, 0xc80a, 0x21, 0 - .dw 0xaa40, 0xc80a, 0xaa7f, 0xc80a, 0x21, 0 - .dw 0xaac0, 0xc80a, 0xaaff, 0xc80a, 0x21, 0 - .dw 0xab40, 0xc80a, 0xab7f, 0xc80a, 0x21, 0 - .dw 0xabc0, 0xc80a, 0xabff, 0xc80a, 0x21, 0 - .dw 0xac40, 0xc80a, 0xac7f, 0xc80a, 0x21, 0 - .dw 0xacc0, 0xc80a, 0xacff, 0xc80a, 0x21, 0 - .dw 0xad40, 0xc80a, 0xad7f, 0xc80a, 0x21, 0 - .dw 0xadc0, 0xc80a, 0xadff, 0xc80a, 0x21, 0 - .dw 0xae40, 0xc80a, 0xae7f, 0xc80a, 0x21, 0 - .dw 0xaec0, 0xc80a, 0xaeff, 0xc80a, 0x21, 0 - .dw 0xaf40, 0xc80a, 0xaf7f, 0xc80a, 0x21, 0 - .dw 0xafc0, 0xc80a, 0xafff, 0xc80a, 0x21, 0 - .dw 0xb040, 0xc80a, 0xb07f, 0xc80a, 0x21, 0 - .dw 0xb0c0, 0xc80a, 0xb0ff, 0xc80a, 0x21, 0 - .dw 0xb140, 0xc80a, 0xb17f, 0xc80a, 0x21, 0 - .dw 0xb1c0, 0xc80a, 0xb1ff, 0xc80a, 0x21, 0 - .dw 0xb240, 0xc80a, 0xb27f, 0xc80a, 0x21, 0 - .dw 0xb2c0, 0xc80a, 0xb2ff, 0xc80a, 0x21, 0 - .dw 0xb340, 0xc80a, 0xb37f, 0xc80a, 0x21, 0 - .dw 0xb3c0, 0xc80a, 0xb3ff, 0xc80a, 0x21, 0 - .dw 0xb440, 0xc80a, 0xb47f, 0xc80a, 0x21, 0 - .dw 0xb4c0, 0xc80a, 0xb4ff, 0xc80a, 0x21, 0 - .dw 0xb540, 0xc80a, 0xb57f, 0xc80a, 0x21, 0 - .dw 0xb5c0, 0xc80a, 0xb5ff, 0xc80a, 0x21, 0 - .dw 0xb640, 0xc80a, 0xb67f, 0xc80a, 0x21, 0 - .dw 0xb6c0, 0xc80a, 0xb6ff, 0xc80a, 0x21, 0 - .dw 0xb740, 0xc80a, 0xb77f, 0xc80a, 0x21, 0 - .dw 0xb7c0, 0xc80a, 0xb7ff, 0xc80a, 0x21, 0 - .dw 0xb840, 0xc80a, 0xb87f, 0xc80a, 0x21, 0 - .dw 0xb8c0, 0xc80a, 0xb8ff, 0xc80a, 0x21, 0 - .dw 0xb940, 0xc80a, 0xb97f, 0xc80a, 0x21, 0 - .dw 0xb9c0, 0xc80a, 0xdfff, 0xc80a, 0x21, 0 - .dw 0xe040, 0xc80a, 0xe07f, 0xc80a, 0x21, 0 - .dw 0xe0c0, 0xc80a, 0xe0ff, 0xc80a, 0x21, 0 - .dw 0xe140, 0xc80a, 0xe17f, 0xc80a, 0x21, 0 - .dw 0xe1c0, 0xc80a, 0xe1ff, 0xc80a, 0x21, 0 - .dw 0xe240, 0xc80a, 0xe27f, 0xc80a, 0x21, 0 - .dw 0xe2c0, 0xc80a, 0xe2ff, 0xc80a, 0x21, 0 - .dw 0xe340, 0xc80a, 0xe37f, 0xc80a, 0x21, 0 - .dw 0xe3c0, 0xc80a, 0xe3ff, 0xc80a, 0x21, 0 - .dw 0xe440, 0xc80a, 0xe47f, 0xc80a, 0x21, 0 - .dw 0xe4c0, 0xc80a, 0xe4ff, 0xc80a, 0x21, 0 - .dw 0xe540, 0xc80a, 0xe57f, 0xc80a, 0x21, 0 - .dw 0xe5c0, 0xc80a, 0xe5ff, 0xc80a, 0x21, 0 - .dw 0xe640, 0xc80a, 0xe67f, 0xc80a, 0x21, 0 - .dw 0xe6c0, 0xc80a, 0xe6ff, 0xc80a, 0x21, 0 - .dw 0xe740, 0xc80a, 0xe77f, 0xc80a, 0x21, 0 - .dw 0xe7c0, 0xc80a, 0xe7ff, 0xc80a, 0x21, 0 - .dw 0xe840, 0xc80a, 0xe87f, 0xc80a, 0x21, 0 - .dw 0xe8c0, 0xc80a, 0xe8ff, 0xc80a, 0x21, 0 - .dw 0xe940, 0xc80a, 0xe97f, 0xc80a, 0x21, 0 - .dw 0xe9c0, 0xc80a, 0xe9ff, 0xc80a, 0x21, 0 - .dw 0xea40, 0xc80a, 0xea7f, 0xc80a, 0x21, 0 - .dw 0xeac0, 0xc80a, 0xeaff, 0xc80a, 0x21, 0 - .dw 0xeb40, 0xc80a, 0xeb7f, 0xc80a, 0x21, 0 - .dw 0xebc0, 0xc80a, 0xebff, 0xc80a, 0x21, 0 - .dw 0xec40, 0xc80a, 0xec7f, 0xc80a, 0x21, 0 - .dw 0xecc0, 0xc80a, 0xecff, 0xc80a, 0x21, 0 - .dw 0xed40, 0xc80a, 0xed7f, 0xc80a, 0x21, 0 - .dw 0xedc0, 0xc80a, 0xedff, 0xc80a, 0x21, 0 - .dw 0xee40, 0xc80a, 0xee7f, 0xc80a, 0x21, 0 - .dw 0xeec0, 0xc80a, 0xeeff, 0xc80a, 0x21, 0 - .dw 0xef40, 0xc80a, 0xef7f, 0xc80a, 0x21, 0 - .dw 0xefc0, 0xc80a, 0xefff, 0xc80a, 0x21, 0 - .dw 0xf040, 0xc80a, 0xf07f, 0xc80a, 0x21, 0 - .dw 0xf0c0, 0xc80a, 0xf0ff, 0xc80a, 0x21, 0 - .dw 0xf140, 0xc80a, 0xf17f, 0xc80a, 0x21, 0 - .dw 0xf1c0, 0xc80a, 0xf1ff, 0xc80a, 0x21, 0 - .dw 0xf240, 0xc80a, 0xf27f, 0xc80a, 0x21, 0 - .dw 0xf2c0, 0xc80a, 0xf2ff, 0xc80a, 0x21, 0 - .dw 0xf340, 0xc80a, 0xf37f, 0xc80a, 0x21, 0 - .dw 0xf3c0, 0xc80a, 0xf3ff, 0xc80a, 0x21, 0 - .dw 0xf440, 0xc80a, 0xf47f, 0xc80a, 0x21, 0 - .dw 0xf4c0, 0xc80a, 0xf4ff, 0xc80a, 0x21, 0 - .dw 0xf540, 0xc80a, 0xf57f, 0xc80a, 0x21, 0 - .dw 0xf5c0, 0xc80a, 0xf5ff, 0xc80a, 0x21, 0 - .dw 0xf640, 0xc80a, 0xf67f, 0xc80a, 0x21, 0 - .dw 0xf6c0, 0xc80a, 0xf6ff, 0xc80a, 0x21, 0 - .dw 0xf740, 0xc80a, 0xf77f, 0xc80a, 0x21, 0 - .dw 0xf7c0, 0xc80a, 0xf7ff, 0xc80a, 0x21, 0 - .dw 0xf840, 0xc80a, 0xf87f, 0xc80a, 0x21, 0 - .dw 0xf8c0, 0xc80a, 0xf8ff, 0xc80a, 0x21, 0 - .dw 0xf940, 0xc80a, 0xf97f, 0xc80a, 0x21, 0 - .dw 0xf9c0, 0xc80a, 0x1fff, 0xc80b, 0x21, 0 - .dw 0x2040, 0xc80b, 0x207f, 0xc80b, 0x21, 0 - .dw 0x20c0, 0xc80b, 0x20ff, 0xc80b, 0x21, 0 - .dw 0x2140, 0xc80b, 0x217f, 0xc80b, 0x21, 0 - .dw 0x21c0, 0xc80b, 0x21ff, 0xc80b, 0x21, 0 - .dw 0x2240, 0xc80b, 0x227f, 0xc80b, 0x21, 0 - .dw 0x22c0, 0xc80b, 0x22ff, 0xc80b, 0x21, 0 - .dw 0x2340, 0xc80b, 0x237f, 0xc80b, 0x21, 0 - .dw 0x23c0, 0xc80b, 0x23ff, 0xc80b, 0x21, 0 - .dw 0x2440, 0xc80b, 0x247f, 0xc80b, 0x21, 0 - .dw 0x24c0, 0xc80b, 0x24ff, 0xc80b, 0x21, 0 - .dw 0x2540, 0xc80b, 0x257f, 0xc80b, 0x21, 0 - .dw 0x25c0, 0xc80b, 0x25ff, 0xc80b, 0x21, 0 - .dw 0x2640, 0xc80b, 0x267f, 0xc80b, 0x21, 0 - .dw 0x26c0, 0xc80b, 0x26ff, 0xc80b, 0x21, 0 - .dw 0x2740, 0xc80b, 0x277f, 0xc80b, 0x21, 0 - .dw 0x27c0, 0xc80b, 0x27ff, 0xc80b, 0x21, 0 - .dw 0x2840, 0xc80b, 0x287f, 0xc80b, 0x21, 0 - .dw 0x28c0, 0xc80b, 0x28ff, 0xc80b, 0x21, 0 - .dw 0x2940, 0xc80b, 0x297f, 0xc80b, 0x21, 0 - .dw 0x29c0, 0xc80b, 0x29ff, 0xc80b, 0x21, 0 - .dw 0x2a40, 0xc80b, 0x2a7f, 0xc80b, 0x21, 0 - .dw 0x2ac0, 0xc80b, 0x2aff, 0xc80b, 0x21, 0 - .dw 0x2b40, 0xc80b, 0x2b7f, 0xc80b, 0x21, 0 - .dw 0x2bc0, 0xc80b, 0x2bff, 0xc80b, 0x21, 0 - .dw 0x2c40, 0xc80b, 0x2c7f, 0xc80b, 0x21, 0 - .dw 0x2cc0, 0xc80b, 0x2cff, 0xc80b, 0x21, 0 - .dw 0x2d40, 0xc80b, 0x2d7f, 0xc80b, 0x21, 0 - .dw 0x2dc0, 0xc80b, 0x2dff, 0xc80b, 0x21, 0 - .dw 0x2e40, 0xc80b, 0x2e7f, 0xc80b, 0x21, 0 - .dw 0x2ec0, 0xc80b, 0x2eff, 0xc80b, 0x21, 0 - .dw 0x2f40, 0xc80b, 0x2f7f, 0xc80b, 0x21, 0 - .dw 0x2fc0, 0xc80b, 0x2fff, 0xc80b, 0x21, 0 - .dw 0x3040, 0xc80b, 0x307f, 0xc80b, 0x21, 0 - .dw 0x30c0, 0xc80b, 0x30ff, 0xc80b, 0x21, 0 - .dw 0x3140, 0xc80b, 0x317f, 0xc80b, 0x21, 0 - .dw 0x31c0, 0xc80b, 0x31ff, 0xc80b, 0x21, 0 - .dw 0x3240, 0xc80b, 0x327f, 0xc80b, 0x21, 0 - .dw 0x32c0, 0xc80b, 0x32ff, 0xc80b, 0x21, 0 - .dw 0x3340, 0xc80b, 0x337f, 0xc80b, 0x21, 0 - .dw 0x33c0, 0xc80b, 0x33ff, 0xc80b, 0x21, 0 - .dw 0x3440, 0xc80b, 0x347f, 0xc80b, 0x21, 0 - .dw 0x34c0, 0xc80b, 0x34ff, 0xc80b, 0x21, 0 - .dw 0x3540, 0xc80b, 0x357f, 0xc80b, 0x21, 0 - .dw 0x35c0, 0xc80b, 0x35ff, 0xc80b, 0x21, 0 - .dw 0x3640, 0xc80b, 0x367f, 0xc80b, 0x21, 0 - .dw 0x36c0, 0xc80b, 0x36ff, 0xc80b, 0x21, 0 - .dw 0x3740, 0xc80b, 0x377f, 0xc80b, 0x21, 0 - .dw 0x37c0, 0xc80b, 0x37ff, 0xc80b, 0x21, 0 - .dw 0x3840, 0xc80b, 0x387f, 0xc80b, 0x21, 0 - .dw 0x38c0, 0xc80b, 0x38ff, 0xc80b, 0x21, 0 - .dw 0x3940, 0xc80b, 0x397f, 0xc80b, 0x21, 0 - .dw 0x39c0, 0xc80b, 0xffff, 0xc80b, 0x21, 0 - .dw 0x0040, 0xc80c, 0x007f, 0xc80c, 0x21, 0 - .dw 0x00c0, 0xc80c, 0x00ff, 0xc80c, 0x21, 0 - .dw 0x0140, 0xc80c, 0x017f, 0xc80c, 0x21, 0 - .dw 0x01c0, 0xc80c, 0x01ff, 0xc80c, 0x21, 0 - .dw 0x0240, 0xc80c, 0x027f, 0xc80c, 0x21, 0 - .dw 0x02c0, 0xc80c, 0x02ff, 0xc80c, 0x21, 0 - .dw 0x0340, 0xc80c, 0x037f, 0xc80c, 0x21, 0 - .dw 0x03c0, 0xc80c, 0x03ff, 0xc80c, 0x21, 0 - .dw 0x0440, 0xc80c, 0x047f, 0xc80c, 0x21, 0 - .dw 0x04c0, 0xc80c, 0x04ff, 0xc80c, 0x21, 0 - .dw 0x0540, 0xc80c, 0x057f, 0xc80c, 0x21, 0 - .dw 0x05c0, 0xc80c, 0x05ff, 0xc80c, 0x21, 0 - .dw 0x0640, 0xc80c, 0x067f, 0xc80c, 0x21, 0 - .dw 0x06c0, 0xc80c, 0x06ff, 0xc80c, 0x21, 0 - .dw 0x0740, 0xc80c, 0x077f, 0xc80c, 0x21, 0 - .dw 0x07c0, 0xc80c, 0x07ff, 0xc80c, 0x21, 0 - .dw 0x0840, 0xc80c, 0x087f, 0xc80c, 0x21, 0 - .dw 0x08c0, 0xc80c, 0x08ff, 0xc80c, 0x21, 0 - .dw 0x0940, 0xc80c, 0x097f, 0xc80c, 0x21, 0 - .dw 0x09c0, 0xc80c, 0x09ff, 0xc80c, 0x21, 0 - .dw 0x0a40, 0xc80c, 0x0a7f, 0xc80c, 0x21, 0 - .dw 0x0ac0, 0xc80c, 0x0aff, 0xc80c, 0x21, 0 - .dw 0x0b40, 0xc80c, 0x0b7f, 0xc80c, 0x21, 0 - .dw 0x0bc0, 0xc80c, 0x0bff, 0xc80c, 0x21, 0 - .dw 0x0c40, 0xc80c, 0x0c7f, 0xc80c, 0x21, 0 - .dw 0x0cc0, 0xc80c, 0x0cff, 0xc80c, 0x21, 0 - .dw 0x0d40, 0xc80c, 0x0d7f, 0xc80c, 0x21, 0 - .dw 0x0dc0, 0xc80c, 0x0dff, 0xc80c, 0x21, 0 - .dw 0x0e40, 0xc80c, 0x0e7f, 0xc80c, 0x21, 0 - .dw 0x0ec0, 0xc80c, 0x0eff, 0xc80c, 0x21, 0 - .dw 0x0f40, 0xc80c, 0x0f7f, 0xc80c, 0x21, 0 - .dw 0x0fc0, 0xc80c, 0x0fff, 0xc80c, 0x21, 0 - .dw 0x1040, 0xc80c, 0x107f, 0xc80c, 0x21, 0 - .dw 0x10c0, 0xc80c, 0x10ff, 0xc80c, 0x21, 0 - .dw 0x1140, 0xc80c, 0x117f, 0xc80c, 0x21, 0 - .dw 0x11c0, 0xc80c, 0x11ff, 0xc80c, 0x21, 0 - .dw 0x1240, 0xc80c, 0x127f, 0xc80c, 0x21, 0 - .dw 0x12c0, 0xc80c, 0x12ff, 0xc80c, 0x21, 0 - .dw 0x1340, 0xc80c, 0x137f, 0xc80c, 0x21, 0 - .dw 0x13c0, 0xc80c, 0x13ff, 0xc80c, 0x21, 0 - .dw 0x1440, 0xc80c, 0x147f, 0xc80c, 0x21, 0 - .dw 0x14c0, 0xc80c, 0x14ff, 0xc80c, 0x21, 0 - .dw 0x1540, 0xc80c, 0x157f, 0xc80c, 0x21, 0 - .dw 0x15c0, 0xc80c, 0x15ff, 0xc80c, 0x21, 0 - .dw 0x1640, 0xc80c, 0x167f, 0xc80c, 0x21, 0 - .dw 0x16c0, 0xc80c, 0x16ff, 0xc80c, 0x21, 0 - .dw 0x1740, 0xc80c, 0x177f, 0xc80c, 0x21, 0 - .dw 0x17c0, 0xc80c, 0x17ff, 0xc80c, 0x21, 0 - .dw 0x1840, 0xc80c, 0x187f, 0xc80c, 0x21, 0 - .dw 0x18c0, 0xc80c, 0x18ff, 0xc80c, 0x21, 0 - .dw 0x1940, 0xc80c, 0x197f, 0xc80c, 0x21, 0 - .dw 0x19c0, 0xc80c, 0x1fff, 0xc80c, 0x21, 0 - .dw 0x2040, 0xc80c, 0x207f, 0xc80c, 0x21, 0 - .dw 0x20c0, 0xc80c, 0x20ff, 0xc80c, 0x21, 0 - .dw 0x2140, 0xc80c, 0x217f, 0xc80c, 0x21, 0 - .dw 0x21c0, 0xc80c, 0x21ff, 0xc80c, 0x21, 0 - .dw 0x2240, 0xc80c, 0x227f, 0xc80c, 0x21, 0 - .dw 0x22c0, 0xc80c, 0x22ff, 0xc80c, 0x21, 0 - .dw 0x2340, 0xc80c, 0x237f, 0xc80c, 0x21, 0 - .dw 0x23c0, 0xc80c, 0x23ff, 0xc80c, 0x21, 0 - .dw 0x2440, 0xc80c, 0x247f, 0xc80c, 0x21, 0 - .dw 0x24c0, 0xc80c, 0x24ff, 0xc80c, 0x21, 0 - .dw 0x2540, 0xc80c, 0x257f, 0xc80c, 0x21, 0 - .dw 0x25c0, 0xc80c, 0x25ff, 0xc80c, 0x21, 0 - .dw 0x2640, 0xc80c, 0x267f, 0xc80c, 0x21, 0 - .dw 0x26c0, 0xc80c, 0x26ff, 0xc80c, 0x21, 0 - .dw 0x2740, 0xc80c, 0x277f, 0xc80c, 0x21, 0 - .dw 0x27c0, 0xc80c, 0x27ff, 0xc80c, 0x21, 0 - .dw 0x2840, 0xc80c, 0x287f, 0xc80c, 0x21, 0 - .dw 0x28c0, 0xc80c, 0x28ff, 0xc80c, 0x21, 0 - .dw 0x2940, 0xc80c, 0x297f, 0xc80c, 0x21, 0 - .dw 0x29c0, 0xc80c, 0x29ff, 0xc80c, 0x21, 0 - .dw 0x2a40, 0xc80c, 0x2a7f, 0xc80c, 0x21, 0 - .dw 0x2ac0, 0xc80c, 0x2aff, 0xc80c, 0x21, 0 - .dw 0x2b40, 0xc80c, 0x2b7f, 0xc80c, 0x21, 0 - .dw 0x2bc0, 0xc80c, 0x2bff, 0xc80c, 0x21, 0 - .dw 0x2c40, 0xc80c, 0x2c7f, 0xc80c, 0x21, 0 - .dw 0x2cc0, 0xc80c, 0x2cff, 0xc80c, 0x21, 0 - .dw 0x2d40, 0xc80c, 0x2d7f, 0xc80c, 0x21, 0 - .dw 0x2dc0, 0xc80c, 0x2dff, 0xc80c, 0x21, 0 - .dw 0x2e40, 0xc80c, 0x2e7f, 0xc80c, 0x21, 0 - .dw 0x2ec0, 0xc80c, 0x2eff, 0xc80c, 0x21, 0 - .dw 0x2f40, 0xc80c, 0x2f7f, 0xc80c, 0x21, 0 - .dw 0x2fc0, 0xc80c, 0x2fff, 0xc80c, 0x21, 0 - .dw 0x3040, 0xc80c, 0x307f, 0xc80c, 0x21, 0 - .dw 0x30c0, 0xc80c, 0x30ff, 0xc80c, 0x21, 0 - .dw 0x3140, 0xc80c, 0x317f, 0xc80c, 0x21, 0 - .dw 0x31c0, 0xc80c, 0x31ff, 0xc80c, 0x21, 0 - .dw 0x3240, 0xc80c, 0x327f, 0xc80c, 0x21, 0 - .dw 0x32c0, 0xc80c, 0x32ff, 0xc80c, 0x21, 0 - .dw 0x3340, 0xc80c, 0x337f, 0xc80c, 0x21, 0 - .dw 0x33c0, 0xc80c, 0x33ff, 0xc80c, 0x21, 0 - .dw 0x3440, 0xc80c, 0x347f, 0xc80c, 0x21, 0 - .dw 0x34c0, 0xc80c, 0x34ff, 0xc80c, 0x21, 0 - .dw 0x3540, 0xc80c, 0x357f, 0xc80c, 0x21, 0 - .dw 0x35c0, 0xc80c, 0x35ff, 0xc80c, 0x21, 0 - .dw 0x3640, 0xc80c, 0x367f, 0xc80c, 0x21, 0 - .dw 0x36c0, 0xc80c, 0x36ff, 0xc80c, 0x21, 0 - .dw 0x3740, 0xc80c, 0x377f, 0xc80c, 0x21, 0 - .dw 0x37c0, 0xc80c, 0x37ff, 0xc80c, 0x21, 0 - .dw 0x3840, 0xc80c, 0x387f, 0xc80c, 0x21, 0 - .dw 0x38c0, 0xc80c, 0x38ff, 0xc80c, 0x21, 0 - .dw 0x3940, 0xc80c, 0x397f, 0xc80c, 0x21, 0 - .dw 0x39c0, 0xc80c, 0x3fff, 0xc80c, 0x21, 0 - .dw 0x4040, 0xc80c, 0x407f, 0xc80c, 0x21, 0 - .dw 0x40c0, 0xc80c, 0x40ff, 0xc80c, 0x21, 0 - .dw 0x4140, 0xc80c, 0x417f, 0xc80c, 0x21, 0 - .dw 0x41c0, 0xc80c, 0x41ff, 0xc80c, 0x21, 0 - .dw 0x4240, 0xc80c, 0x427f, 0xc80c, 0x21, 0 - .dw 0x42c0, 0xc80c, 0x42ff, 0xc80c, 0x21, 0 - .dw 0x4340, 0xc80c, 0x437f, 0xc80c, 0x21, 0 - .dw 0x43c0, 0xc80c, 0x43ff, 0xc80c, 0x21, 0 - .dw 0x4440, 0xc80c, 0x447f, 0xc80c, 0x21, 0 - .dw 0x44c0, 0xc80c, 0x44ff, 0xc80c, 0x21, 0 - .dw 0x4540, 0xc80c, 0x457f, 0xc80c, 0x21, 0 - .dw 0x45c0, 0xc80c, 0x45ff, 0xc80c, 0x21, 0 - .dw 0x4640, 0xc80c, 0x467f, 0xc80c, 0x21, 0 - .dw 0x46c0, 0xc80c, 0x46ff, 0xc80c, 0x21, 0 - .dw 0x4740, 0xc80c, 0x477f, 0xc80c, 0x21, 0 - .dw 0x47c0, 0xc80c, 0x47ff, 0xc80c, 0x21, 0 - .dw 0x4840, 0xc80c, 0x487f, 0xc80c, 0x21, 0 - .dw 0x48c0, 0xc80c, 0x48ff, 0xc80c, 0x21, 0 - .dw 0x4940, 0xc80c, 0x497f, 0xc80c, 0x21, 0 - .dw 0x49c0, 0xc80c, 0x49ff, 0xc80c, 0x21, 0 - .dw 0x4a40, 0xc80c, 0x4a7f, 0xc80c, 0x21, 0 - .dw 0x4ac0, 0xc80c, 0x4aff, 0xc80c, 0x21, 0 - .dw 0x4b40, 0xc80c, 0x4b7f, 0xc80c, 0x21, 0 - .dw 0x4bc0, 0xc80c, 0x4bff, 0xc80c, 0x21, 0 - .dw 0x4c40, 0xc80c, 0x4c7f, 0xc80c, 0x21, 0 - .dw 0x4cc0, 0xc80c, 0x4cff, 0xc80c, 0x21, 0 - .dw 0x4d40, 0xc80c, 0x4d7f, 0xc80c, 0x21, 0 - .dw 0x4dc0, 0xc80c, 0x4dff, 0xc80c, 0x21, 0 - .dw 0x4e40, 0xc80c, 0x4e7f, 0xc80c, 0x21, 0 - .dw 0x4ec0, 0xc80c, 0x4eff, 0xc80c, 0x21, 0 - .dw 0x4f40, 0xc80c, 0x4f7f, 0xc80c, 0x21, 0 - .dw 0x4fc0, 0xc80c, 0x4fff, 0xc80c, 0x21, 0 - .dw 0x5040, 0xc80c, 0x507f, 0xc80c, 0x21, 0 - .dw 0x50c0, 0xc80c, 0x50ff, 0xc80c, 0x21, 0 - .dw 0x5140, 0xc80c, 0x517f, 0xc80c, 0x21, 0 - .dw 0x51c0, 0xc80c, 0x51ff, 0xc80c, 0x21, 0 - .dw 0x5240, 0xc80c, 0x527f, 0xc80c, 0x21, 0 - .dw 0x52c0, 0xc80c, 0x52ff, 0xc80c, 0x21, 0 - .dw 0x5340, 0xc80c, 0x537f, 0xc80c, 0x21, 0 - .dw 0x53c0, 0xc80c, 0x53ff, 0xc80c, 0x21, 0 - .dw 0x5440, 0xc80c, 0x547f, 0xc80c, 0x21, 0 - .dw 0x54c0, 0xc80c, 0x54ff, 0xc80c, 0x21, 0 - .dw 0x5540, 0xc80c, 0x557f, 0xc80c, 0x21, 0 - .dw 0x55c0, 0xc80c, 0x55ff, 0xc80c, 0x21, 0 - .dw 0x5640, 0xc80c, 0x567f, 0xc80c, 0x21, 0 - .dw 0x56c0, 0xc80c, 0x56ff, 0xc80c, 0x21, 0 - .dw 0x5740, 0xc80c, 0x577f, 0xc80c, 0x21, 0 - .dw 0x57c0, 0xc80c, 0x57ff, 0xc80c, 0x21, 0 - .dw 0x5840, 0xc80c, 0x587f, 0xc80c, 0x21, 0 - .dw 0x58c0, 0xc80c, 0x58ff, 0xc80c, 0x21, 0 - .dw 0x5940, 0xc80c, 0x597f, 0xc80c, 0x21, 0 - .dw 0x59c0, 0xc80c, 0x5fff, 0xc80c, 0x21, 0 - .dw 0x6040, 0xc80c, 0x607f, 0xc80c, 0x21, 0 - .dw 0x60c0, 0xc80c, 0x60ff, 0xc80c, 0x21, 0 - .dw 0x6140, 0xc80c, 0x617f, 0xc80c, 0x21, 0 - .dw 0x61c0, 0xc80c, 0x61ff, 0xc80c, 0x21, 0 - .dw 0x6240, 0xc80c, 0x627f, 0xc80c, 0x21, 0 - .dw 0x62c0, 0xc80c, 0x62ff, 0xc80c, 0x21, 0 - .dw 0x6340, 0xc80c, 0x637f, 0xc80c, 0x21, 0 - .dw 0x63c0, 0xc80c, 0x63ff, 0xc80c, 0x21, 0 - .dw 0x6440, 0xc80c, 0x647f, 0xc80c, 0x21, 0 - .dw 0x64c0, 0xc80c, 0x64ff, 0xc80c, 0x21, 0 - .dw 0x6540, 0xc80c, 0x657f, 0xc80c, 0x21, 0 - .dw 0x65c0, 0xc80c, 0x65ff, 0xc80c, 0x21, 0 - .dw 0x6640, 0xc80c, 0x667f, 0xc80c, 0x21, 0 - .dw 0x66c0, 0xc80c, 0x66ff, 0xc80c, 0x21, 0 - .dw 0x6740, 0xc80c, 0x677f, 0xc80c, 0x21, 0 - .dw 0x67c0, 0xc80c, 0x67ff, 0xc80c, 0x21, 0 - .dw 0x6840, 0xc80c, 0x687f, 0xc80c, 0x21, 0 - .dw 0x68c0, 0xc80c, 0x68ff, 0xc80c, 0x21, 0 - .dw 0x6940, 0xc80c, 0x697f, 0xc80c, 0x21, 0 - .dw 0x69c0, 0xc80c, 0x69ff, 0xc80c, 0x21, 0 - .dw 0x6a40, 0xc80c, 0x6a7f, 0xc80c, 0x21, 0 - .dw 0x6ac0, 0xc80c, 0x6aff, 0xc80c, 0x21, 0 - .dw 0x6b40, 0xc80c, 0x6b7f, 0xc80c, 0x21, 0 - .dw 0x6bc0, 0xc80c, 0x6bff, 0xc80c, 0x21, 0 - .dw 0x6c40, 0xc80c, 0x6c7f, 0xc80c, 0x21, 0 - .dw 0x6cc0, 0xc80c, 0x6cff, 0xc80c, 0x21, 0 - .dw 0x6d40, 0xc80c, 0x6d7f, 0xc80c, 0x21, 0 - .dw 0x6dc0, 0xc80c, 0x6dff, 0xc80c, 0x21, 0 - .dw 0x6e40, 0xc80c, 0x6e7f, 0xc80c, 0x21, 0 - .dw 0x6ec0, 0xc80c, 0x6eff, 0xc80c, 0x21, 0 - .dw 0x6f40, 0xc80c, 0x6f7f, 0xc80c, 0x21, 0 - .dw 0x6fc0, 0xc80c, 0x6fff, 0xc80c, 0x21, 0 - .dw 0x7040, 0xc80c, 0x707f, 0xc80c, 0x21, 0 - .dw 0x70c0, 0xc80c, 0x70ff, 0xc80c, 0x21, 0 - .dw 0x7140, 0xc80c, 0x717f, 0xc80c, 0x21, 0 - .dw 0x71c0, 0xc80c, 0x71ff, 0xc80c, 0x21, 0 - .dw 0x7240, 0xc80c, 0x727f, 0xc80c, 0x21, 0 - .dw 0x72c0, 0xc80c, 0x72ff, 0xc80c, 0x21, 0 - .dw 0x7340, 0xc80c, 0x737f, 0xc80c, 0x21, 0 - .dw 0x73c0, 0xc80c, 0x73ff, 0xc80c, 0x21, 0 - .dw 0x7440, 0xc80c, 0x747f, 0xc80c, 0x21, 0 - .dw 0x74c0, 0xc80c, 0x74ff, 0xc80c, 0x21, 0 - .dw 0x7540, 0xc80c, 0x757f, 0xc80c, 0x21, 0 - .dw 0x75c0, 0xc80c, 0x75ff, 0xc80c, 0x21, 0 - .dw 0x7640, 0xc80c, 0x767f, 0xc80c, 0x21, 0 - .dw 0x76c0, 0xc80c, 0x76ff, 0xc80c, 0x21, 0 - .dw 0x7740, 0xc80c, 0x777f, 0xc80c, 0x21, 0 - .dw 0x77c0, 0xc80c, 0x77ff, 0xc80c, 0x21, 0 - .dw 0x7840, 0xc80c, 0x787f, 0xc80c, 0x21, 0 - .dw 0x78c0, 0xc80c, 0x78ff, 0xc80c, 0x21, 0 - .dw 0x7940, 0xc80c, 0x797f, 0xc80c, 0x21, 0 - .dw 0x79c0, 0xc80c, 0x7fff, 0xc80c, 0x21, 0 - .dw 0x8040, 0xc80c, 0x807f, 0xc80c, 0x21, 0 - .dw 0x80c0, 0xc80c, 0x80ff, 0xc80c, 0x21, 0 - .dw 0x8140, 0xc80c, 0x817f, 0xc80c, 0x21, 0 - .dw 0x81c0, 0xc80c, 0x81ff, 0xc80c, 0x21, 0 - .dw 0x8240, 0xc80c, 0x827f, 0xc80c, 0x21, 0 - .dw 0x82c0, 0xc80c, 0x82ff, 0xc80c, 0x21, 0 - .dw 0x8340, 0xc80c, 0x837f, 0xc80c, 0x21, 0 - .dw 0x83c0, 0xc80c, 0x83ff, 0xc80c, 0x21, 0 - .dw 0x8440, 0xc80c, 0x847f, 0xc80c, 0x21, 0 - .dw 0x84c0, 0xc80c, 0x84ff, 0xc80c, 0x21, 0 - .dw 0x8540, 0xc80c, 0x857f, 0xc80c, 0x21, 0 - .dw 0x85c0, 0xc80c, 0x85ff, 0xc80c, 0x21, 0 - .dw 0x8640, 0xc80c, 0x867f, 0xc80c, 0x21, 0 - .dw 0x86c0, 0xc80c, 0x86ff, 0xc80c, 0x21, 0 - .dw 0x8740, 0xc80c, 0x877f, 0xc80c, 0x21, 0 - .dw 0x87c0, 0xc80c, 0x87ff, 0xc80c, 0x21, 0 - .dw 0x8840, 0xc80c, 0x887f, 0xc80c, 0x21, 0 - .dw 0x88c0, 0xc80c, 0x88ff, 0xc80c, 0x21, 0 - .dw 0x8940, 0xc80c, 0x897f, 0xc80c, 0x21, 0 - .dw 0x89c0, 0xc80c, 0x89ff, 0xc80c, 0x21, 0 - .dw 0x8a40, 0xc80c, 0x8a7f, 0xc80c, 0x21, 0 - .dw 0x8ac0, 0xc80c, 0x8aff, 0xc80c, 0x21, 0 - .dw 0x8b40, 0xc80c, 0x8b7f, 0xc80c, 0x21, 0 - .dw 0x8bc0, 0xc80c, 0x8bff, 0xc80c, 0x21, 0 - .dw 0x8c40, 0xc80c, 0x8c7f, 0xc80c, 0x21, 0 - .dw 0x8cc0, 0xc80c, 0x8cff, 0xc80c, 0x21, 0 - .dw 0x8d40, 0xc80c, 0x8d7f, 0xc80c, 0x21, 0 - .dw 0x8dc0, 0xc80c, 0x8dff, 0xc80c, 0x21, 0 - .dw 0x8e40, 0xc80c, 0x8e7f, 0xc80c, 0x21, 0 - .dw 0x8ec0, 0xc80c, 0x8eff, 0xc80c, 0x21, 0 - .dw 0x8f40, 0xc80c, 0x8f7f, 0xc80c, 0x21, 0 - .dw 0x8fc0, 0xc80c, 0x8fff, 0xc80c, 0x21, 0 - .dw 0x9040, 0xc80c, 0x907f, 0xc80c, 0x21, 0 - .dw 0x90c0, 0xc80c, 0x90ff, 0xc80c, 0x21, 0 - .dw 0x9140, 0xc80c, 0x917f, 0xc80c, 0x21, 0 - .dw 0x91c0, 0xc80c, 0x91ff, 0xc80c, 0x21, 0 - .dw 0x9240, 0xc80c, 0x927f, 0xc80c, 0x21, 0 - .dw 0x92c0, 0xc80c, 0x92ff, 0xc80c, 0x21, 0 - .dw 0x9340, 0xc80c, 0x937f, 0xc80c, 0x21, 0 - .dw 0x93c0, 0xc80c, 0x93ff, 0xc80c, 0x21, 0 - .dw 0x9440, 0xc80c, 0x947f, 0xc80c, 0x21, 0 - .dw 0x94c0, 0xc80c, 0x94ff, 0xc80c, 0x21, 0 - .dw 0x9540, 0xc80c, 0x957f, 0xc80c, 0x21, 0 - .dw 0x95c0, 0xc80c, 0x95ff, 0xc80c, 0x21, 0 - .dw 0x9640, 0xc80c, 0x967f, 0xc80c, 0x21, 0 - .dw 0x96c0, 0xc80c, 0x96ff, 0xc80c, 0x21, 0 - .dw 0x9740, 0xc80c, 0x977f, 0xc80c, 0x21, 0 - .dw 0x97c0, 0xc80c, 0x97ff, 0xc80c, 0x21, 0 - .dw 0x9840, 0xc80c, 0x987f, 0xc80c, 0x21, 0 - .dw 0x98c0, 0xc80c, 0x98ff, 0xc80c, 0x21, 0 - .dw 0x9940, 0xc80c, 0x997f, 0xc80c, 0x21, 0 - .dw 0x99c0, 0xc80c, 0x9fff, 0xc80c, 0x21, 0 - .dw 0xa040, 0xc80c, 0xa07f, 0xc80c, 0x21, 0 - .dw 0xa0c0, 0xc80c, 0xa0ff, 0xc80c, 0x21, 0 - .dw 0xa140, 0xc80c, 0xa17f, 0xc80c, 0x21, 0 - .dw 0xa1c0, 0xc80c, 0xa1ff, 0xc80c, 0x21, 0 - .dw 0xa240, 0xc80c, 0xa27f, 0xc80c, 0x21, 0 - .dw 0xa2c0, 0xc80c, 0xa2ff, 0xc80c, 0x21, 0 - .dw 0xa340, 0xc80c, 0xa37f, 0xc80c, 0x21, 0 - .dw 0xa3c0, 0xc80c, 0xa3ff, 0xc80c, 0x21, 0 - .dw 0xa440, 0xc80c, 0xa47f, 0xc80c, 0x21, 0 - .dw 0xa4c0, 0xc80c, 0xa4ff, 0xc80c, 0x21, 0 - .dw 0xa540, 0xc80c, 0xa57f, 0xc80c, 0x21, 0 - .dw 0xa5c0, 0xc80c, 0xa5ff, 0xc80c, 0x21, 0 - .dw 0xa640, 0xc80c, 0xa67f, 0xc80c, 0x21, 0 - .dw 0xa6c0, 0xc80c, 0xa6ff, 0xc80c, 0x21, 0 - .dw 0xa740, 0xc80c, 0xa77f, 0xc80c, 0x21, 0 - .dw 0xa7c0, 0xc80c, 0xa7ff, 0xc80c, 0x21, 0 - .dw 0xa840, 0xc80c, 0xa87f, 0xc80c, 0x21, 0 - .dw 0xa8c0, 0xc80c, 0xa8ff, 0xc80c, 0x21, 0 - .dw 0xa940, 0xc80c, 0xa97f, 0xc80c, 0x21, 0 - .dw 0xa9c0, 0xc80c, 0xa9ff, 0xc80c, 0x21, 0 - .dw 0xaa40, 0xc80c, 0xaa7f, 0xc80c, 0x21, 0 - .dw 0xaac0, 0xc80c, 0xaaff, 0xc80c, 0x21, 0 - .dw 0xab40, 0xc80c, 0xab7f, 0xc80c, 0x21, 0 - .dw 0xabc0, 0xc80c, 0xabff, 0xc80c, 0x21, 0 - .dw 0xac40, 0xc80c, 0xac7f, 0xc80c, 0x21, 0 - .dw 0xacc0, 0xc80c, 0xacff, 0xc80c, 0x21, 0 - .dw 0xad40, 0xc80c, 0xad7f, 0xc80c, 0x21, 0 - .dw 0xadc0, 0xc80c, 0xadff, 0xc80c, 0x21, 0 - .dw 0xae40, 0xc80c, 0xae7f, 0xc80c, 0x21, 0 - .dw 0xaec0, 0xc80c, 0xaeff, 0xc80c, 0x21, 0 - .dw 0xaf40, 0xc80c, 0xaf7f, 0xc80c, 0x21, 0 - .dw 0xafc0, 0xc80c, 0xafff, 0xc80c, 0x21, 0 - .dw 0xb040, 0xc80c, 0xb07f, 0xc80c, 0x21, 0 - .dw 0xb0c0, 0xc80c, 0xb0ff, 0xc80c, 0x21, 0 - .dw 0xb140, 0xc80c, 0xb17f, 0xc80c, 0x21, 0 - .dw 0xb1c0, 0xc80c, 0xb1ff, 0xc80c, 0x21, 0 - .dw 0xb240, 0xc80c, 0xb27f, 0xc80c, 0x21, 0 - .dw 0xb2c0, 0xc80c, 0xb2ff, 0xc80c, 0x21, 0 - .dw 0xb340, 0xc80c, 0xb37f, 0xc80c, 0x21, 0 - .dw 0xb3c0, 0xc80c, 0xb3ff, 0xc80c, 0x21, 0 - .dw 0xb440, 0xc80c, 0xb47f, 0xc80c, 0x21, 0 - .dw 0xb4c0, 0xc80c, 0xb4ff, 0xc80c, 0x21, 0 - .dw 0xb540, 0xc80c, 0xb57f, 0xc80c, 0x21, 0 - .dw 0xb5c0, 0xc80c, 0xb5ff, 0xc80c, 0x21, 0 - .dw 0xb640, 0xc80c, 0xb67f, 0xc80c, 0x21, 0 - .dw 0xb6c0, 0xc80c, 0xb6ff, 0xc80c, 0x21, 0 - .dw 0xb740, 0xc80c, 0xb77f, 0xc80c, 0x21, 0 - .dw 0xb7c0, 0xc80c, 0xb7ff, 0xc80c, 0x21, 0 - .dw 0xb840, 0xc80c, 0xb87f, 0xc80c, 0x21, 0 - .dw 0xb8c0, 0xc80c, 0xb8ff, 0xc80c, 0x21, 0 - .dw 0xb940, 0xc80c, 0xb97f, 0xc80c, 0x21, 0 - .dw 0xb9c0, 0xc80c, 0xbfff, 0xc80c, 0x21, 0 - .dw 0xc040, 0xc80c, 0xc07f, 0xc80c, 0x21, 0 - .dw 0xc0c0, 0xc80c, 0xc0ff, 0xc80c, 0x21, 0 - .dw 0xc140, 0xc80c, 0xc17f, 0xc80c, 0x21, 0 - .dw 0xc1c0, 0xc80c, 0xc1ff, 0xc80c, 0x21, 0 - .dw 0xc240, 0xc80c, 0xc27f, 0xc80c, 0x21, 0 - .dw 0xc2c0, 0xc80c, 0xc2ff, 0xc80c, 0x21, 0 - .dw 0xc340, 0xc80c, 0xc37f, 0xc80c, 0x21, 0 - .dw 0xc3c0, 0xc80c, 0xc3ff, 0xc80c, 0x21, 0 - .dw 0xc440, 0xc80c, 0xc47f, 0xc80c, 0x21, 0 - .dw 0xc4c0, 0xc80c, 0xc4ff, 0xc80c, 0x21, 0 - .dw 0xc540, 0xc80c, 0xc57f, 0xc80c, 0x21, 0 - .dw 0xc5c0, 0xc80c, 0xc5ff, 0xc80c, 0x21, 0 - .dw 0xc640, 0xc80c, 0xc67f, 0xc80c, 0x21, 0 - .dw 0xc6c0, 0xc80c, 0xc6ff, 0xc80c, 0x21, 0 - .dw 0xc740, 0xc80c, 0xc77f, 0xc80c, 0x21, 0 - .dw 0xc7c0, 0xc80c, 0xc7ff, 0xc80c, 0x21, 0 - .dw 0xc840, 0xc80c, 0xc87f, 0xc80c, 0x21, 0 - .dw 0xc8c0, 0xc80c, 0xc8ff, 0xc80c, 0x21, 0 - .dw 0xc940, 0xc80c, 0xc97f, 0xc80c, 0x21, 0 - .dw 0xc9c0, 0xc80c, 0xc9ff, 0xc80c, 0x21, 0 - .dw 0xca40, 0xc80c, 0xca7f, 0xc80c, 0x21, 0 - .dw 0xcac0, 0xc80c, 0xcaff, 0xc80c, 0x21, 0 - .dw 0xcb40, 0xc80c, 0xcb7f, 0xc80c, 0x21, 0 - .dw 0xcbc0, 0xc80c, 0xcbff, 0xc80c, 0x21, 0 - .dw 0xcc40, 0xc80c, 0xcc7f, 0xc80c, 0x21, 0 - .dw 0xccc0, 0xc80c, 0xccff, 0xc80c, 0x21, 0 - .dw 0xcd40, 0xc80c, 0xcd7f, 0xc80c, 0x21, 0 - .dw 0xcdc0, 0xc80c, 0xcdff, 0xc80c, 0x21, 0 - .dw 0xce40, 0xc80c, 0xce7f, 0xc80c, 0x21, 0 - .dw 0xcec0, 0xc80c, 0xceff, 0xc80c, 0x21, 0 - .dw 0xcf40, 0xc80c, 0xcf7f, 0xc80c, 0x21, 0 - .dw 0xcfc0, 0xc80c, 0xcfff, 0xc80c, 0x21, 0 - .dw 0xd040, 0xc80c, 0xd07f, 0xc80c, 0x21, 0 - .dw 0xd0c0, 0xc80c, 0xd0ff, 0xc80c, 0x21, 0 - .dw 0xd140, 0xc80c, 0xd17f, 0xc80c, 0x21, 0 - .dw 0xd1c0, 0xc80c, 0xd1ff, 0xc80c, 0x21, 0 - .dw 0xd240, 0xc80c, 0xd27f, 0xc80c, 0x21, 0 - .dw 0xd2c0, 0xc80c, 0xd2ff, 0xc80c, 0x21, 0 - .dw 0xd340, 0xc80c, 0xd37f, 0xc80c, 0x21, 0 - .dw 0xd3c0, 0xc80c, 0xd3ff, 0xc80c, 0x21, 0 - .dw 0xd440, 0xc80c, 0xd47f, 0xc80c, 0x21, 0 - .dw 0xd4c0, 0xc80c, 0xd4ff, 0xc80c, 0x21, 0 - .dw 0xd540, 0xc80c, 0xd57f, 0xc80c, 0x21, 0 - .dw 0xd5c0, 0xc80c, 0xd5ff, 0xc80c, 0x21, 0 - .dw 0xd640, 0xc80c, 0xd67f, 0xc80c, 0x21, 0 - .dw 0xd6c0, 0xc80c, 0xd6ff, 0xc80c, 0x21, 0 - .dw 0xd740, 0xc80c, 0xd77f, 0xc80c, 0x21, 0 - .dw 0xd7c0, 0xc80c, 0xd7ff, 0xc80c, 0x21, 0 - .dw 0xd840, 0xc80c, 0xd87f, 0xc80c, 0x21, 0 - .dw 0xd8c0, 0xc80c, 0xd8ff, 0xc80c, 0x21, 0 - .dw 0xd940, 0xc80c, 0xd97f, 0xc80c, 0x21, 0 - .dw 0xd9c0, 0xc80c, 0xdfff, 0xc80c, 0x21, 0 - .dw 0xe040, 0xc80c, 0xe07f, 0xc80c, 0x21, 0 - .dw 0xe0c0, 0xc80c, 0xe0ff, 0xc80c, 0x21, 0 - .dw 0xe140, 0xc80c, 0xe17f, 0xc80c, 0x21, 0 - .dw 0xe1c0, 0xc80c, 0xe1ff, 0xc80c, 0x21, 0 - .dw 0xe240, 0xc80c, 0xe27f, 0xc80c, 0x21, 0 - .dw 0xe2c0, 0xc80c, 0xe2ff, 0xc80c, 0x21, 0 - .dw 0xe340, 0xc80c, 0xe37f, 0xc80c, 0x21, 0 - .dw 0xe3c0, 0xc80c, 0xe3ff, 0xc80c, 0x21, 0 - .dw 0xe440, 0xc80c, 0xe47f, 0xc80c, 0x21, 0 - .dw 0xe4c0, 0xc80c, 0xe4ff, 0xc80c, 0x21, 0 - .dw 0xe540, 0xc80c, 0xe57f, 0xc80c, 0x21, 0 - .dw 0xe5c0, 0xc80c, 0xe5ff, 0xc80c, 0x21, 0 - .dw 0xe640, 0xc80c, 0xe67f, 0xc80c, 0x21, 0 - .dw 0xe6c0, 0xc80c, 0xe6ff, 0xc80c, 0x21, 0 - .dw 0xe740, 0xc80c, 0xe77f, 0xc80c, 0x21, 0 - .dw 0xe7c0, 0xc80c, 0xe7ff, 0xc80c, 0x21, 0 - .dw 0xe840, 0xc80c, 0xe87f, 0xc80c, 0x21, 0 - .dw 0xe8c0, 0xc80c, 0xe8ff, 0xc80c, 0x21, 0 - .dw 0xe940, 0xc80c, 0xe97f, 0xc80c, 0x21, 0 - .dw 0xe9c0, 0xc80c, 0xe9ff, 0xc80c, 0x21, 0 - .dw 0xea40, 0xc80c, 0xea7f, 0xc80c, 0x21, 0 - .dw 0xeac0, 0xc80c, 0xeaff, 0xc80c, 0x21, 0 - .dw 0xeb40, 0xc80c, 0xeb7f, 0xc80c, 0x21, 0 - .dw 0xebc0, 0xc80c, 0xebff, 0xc80c, 0x21, 0 - .dw 0xec40, 0xc80c, 0xec7f, 0xc80c, 0x21, 0 - .dw 0xecc0, 0xc80c, 0xecff, 0xc80c, 0x21, 0 - .dw 0xed40, 0xc80c, 0xed7f, 0xc80c, 0x21, 0 - .dw 0xedc0, 0xc80c, 0xedff, 0xc80c, 0x21, 0 - .dw 0xee40, 0xc80c, 0xee7f, 0xc80c, 0x21, 0 - .dw 0xeec0, 0xc80c, 0xeeff, 0xc80c, 0x21, 0 - .dw 0xef40, 0xc80c, 0xef7f, 0xc80c, 0x21, 0 - .dw 0xefc0, 0xc80c, 0xefff, 0xc80c, 0x21, 0 - .dw 0xf040, 0xc80c, 0xf07f, 0xc80c, 0x21, 0 - .dw 0xf0c0, 0xc80c, 0xf0ff, 0xc80c, 0x21, 0 - .dw 0xf140, 0xc80c, 0xf17f, 0xc80c, 0x21, 0 - .dw 0xf1c0, 0xc80c, 0xf1ff, 0xc80c, 0x21, 0 - .dw 0xf240, 0xc80c, 0xf27f, 0xc80c, 0x21, 0 - .dw 0xf2c0, 0xc80c, 0xf2ff, 0xc80c, 0x21, 0 - .dw 0xf340, 0xc80c, 0xf37f, 0xc80c, 0x21, 0 - .dw 0xf3c0, 0xc80c, 0xf3ff, 0xc80c, 0x21, 0 - .dw 0xf440, 0xc80c, 0xf47f, 0xc80c, 0x21, 0 - .dw 0xf4c0, 0xc80c, 0xf4ff, 0xc80c, 0x21, 0 - .dw 0xf540, 0xc80c, 0xf57f, 0xc80c, 0x21, 0 - .dw 0xf5c0, 0xc80c, 0xf5ff, 0xc80c, 0x21, 0 - .dw 0xf640, 0xc80c, 0xf67f, 0xc80c, 0x21, 0 - .dw 0xf6c0, 0xc80c, 0xf6ff, 0xc80c, 0x21, 0 - .dw 0xf740, 0xc80c, 0xf77f, 0xc80c, 0x21, 0 - .dw 0xf7c0, 0xc80c, 0xf7ff, 0xc80c, 0x21, 0 - .dw 0xf840, 0xc80c, 0xf87f, 0xc80c, 0x21, 0 - .dw 0xf8c0, 0xc80c, 0xf8ff, 0xc80c, 0x21, 0 - .dw 0xf940, 0xc80c, 0xf97f, 0xc80c, 0x21, 0 - .dw 0xf9c0, 0xc80c, 0xffff, 0xc80c, 0x21, 0 - .dw 0x0040, 0xc80d, 0x007f, 0xc80d, 0x21, 0 - .dw 0x00c0, 0xc80d, 0x00ff, 0xc80d, 0x21, 0 - .dw 0x0140, 0xc80d, 0x017f, 0xc80d, 0x21, 0 - .dw 0x01c0, 0xc80d, 0x01ff, 0xc80d, 0x21, 0 - .dw 0x0240, 0xc80d, 0x027f, 0xc80d, 0x21, 0 - .dw 0x02c0, 0xc80d, 0x02ff, 0xc80d, 0x21, 0 - .dw 0x0340, 0xc80d, 0x037f, 0xc80d, 0x21, 0 - .dw 0x03c0, 0xc80d, 0x03ff, 0xc80d, 0x21, 0 - .dw 0x0440, 0xc80d, 0x047f, 0xc80d, 0x21, 0 - .dw 0x04c0, 0xc80d, 0x04ff, 0xc80d, 0x21, 0 - .dw 0x0540, 0xc80d, 0x057f, 0xc80d, 0x21, 0 - .dw 0x05c0, 0xc80d, 0x05ff, 0xc80d, 0x21, 0 - .dw 0x0640, 0xc80d, 0x067f, 0xc80d, 0x21, 0 - .dw 0x06c0, 0xc80d, 0x06ff, 0xc80d, 0x21, 0 - .dw 0x0740, 0xc80d, 0x077f, 0xc80d, 0x21, 0 - .dw 0x07c0, 0xc80d, 0x07ff, 0xc80d, 0x21, 0 - .dw 0x0840, 0xc80d, 0x087f, 0xc80d, 0x21, 0 - .dw 0x08c0, 0xc80d, 0x08ff, 0xc80d, 0x21, 0 - .dw 0x0940, 0xc80d, 0x097f, 0xc80d, 0x21, 0 - .dw 0x09c0, 0xc80d, 0x09ff, 0xc80d, 0x21, 0 - .dw 0x0a40, 0xc80d, 0x0a7f, 0xc80d, 0x21, 0 - .dw 0x0ac0, 0xc80d, 0x0aff, 0xc80d, 0x21, 0 - .dw 0x0b40, 0xc80d, 0x0b7f, 0xc80d, 0x21, 0 - .dw 0x0bc0, 0xc80d, 0x0bff, 0xc80d, 0x21, 0 - .dw 0x0c40, 0xc80d, 0x0c7f, 0xc80d, 0x21, 0 - .dw 0x0cc0, 0xc80d, 0x0cff, 0xc80d, 0x21, 0 - .dw 0x0d40, 0xc80d, 0x0d7f, 0xc80d, 0x21, 0 - .dw 0x0dc0, 0xc80d, 0x0dff, 0xc80d, 0x21, 0 - .dw 0x0e40, 0xc80d, 0x0e7f, 0xc80d, 0x21, 0 - .dw 0x0ec0, 0xc80d, 0x0eff, 0xc80d, 0x21, 0 - .dw 0x0f40, 0xc80d, 0x0f7f, 0xc80d, 0x21, 0 - .dw 0x0fc0, 0xc80d, 0x0fff, 0xc80d, 0x21, 0 - .dw 0x1040, 0xc80d, 0x107f, 0xc80d, 0x21, 0 - .dw 0x10c0, 0xc80d, 0x10ff, 0xc80d, 0x21, 0 - .dw 0x1140, 0xc80d, 0x117f, 0xc80d, 0x21, 0 - .dw 0x11c0, 0xc80d, 0x11ff, 0xc80d, 0x21, 0 - .dw 0x1240, 0xc80d, 0x127f, 0xc80d, 0x21, 0 - .dw 0x12c0, 0xc80d, 0x12ff, 0xc80d, 0x21, 0 - .dw 0x1340, 0xc80d, 0x137f, 0xc80d, 0x21, 0 - .dw 0x13c0, 0xc80d, 0x13ff, 0xc80d, 0x21, 0 - .dw 0x1440, 0xc80d, 0x147f, 0xc80d, 0x21, 0 - .dw 0x14c0, 0xc80d, 0x14ff, 0xc80d, 0x21, 0 - .dw 0x1540, 0xc80d, 0x157f, 0xc80d, 0x21, 0 - .dw 0x15c0, 0xc80d, 0x15ff, 0xc80d, 0x21, 0 - .dw 0x1640, 0xc80d, 0x167f, 0xc80d, 0x21, 0 - .dw 0x16c0, 0xc80d, 0x16ff, 0xc80d, 0x21, 0 - .dw 0x1740, 0xc80d, 0x177f, 0xc80d, 0x21, 0 - .dw 0x17c0, 0xc80d, 0x17ff, 0xc80d, 0x21, 0 - .dw 0x1840, 0xc80d, 0x187f, 0xc80d, 0x21, 0 - .dw 0x18c0, 0xc80d, 0x18ff, 0xc80d, 0x21, 0 - .dw 0x1940, 0xc80d, 0x197f, 0xc80d, 0x21, 0 - .dw 0x19c0, 0xc80d, 0x1fff, 0xc80d, 0x21, 0 - .dw 0x2040, 0xc80d, 0x207f, 0xc80d, 0x21, 0 - .dw 0x20c0, 0xc80d, 0x20ff, 0xc80d, 0x21, 0 - .dw 0x2140, 0xc80d, 0x217f, 0xc80d, 0x21, 0 - .dw 0x21c0, 0xc80d, 0x21ff, 0xc80d, 0x21, 0 - .dw 0x2240, 0xc80d, 0x227f, 0xc80d, 0x21, 0 - .dw 0x22c0, 0xc80d, 0x22ff, 0xc80d, 0x21, 0 - .dw 0x2340, 0xc80d, 0x237f, 0xc80d, 0x21, 0 - .dw 0x23c0, 0xc80d, 0x23ff, 0xc80d, 0x21, 0 - .dw 0x2440, 0xc80d, 0x247f, 0xc80d, 0x21, 0 - .dw 0x24c0, 0xc80d, 0x24ff, 0xc80d, 0x21, 0 - .dw 0x2540, 0xc80d, 0x257f, 0xc80d, 0x21, 0 - .dw 0x25c0, 0xc80d, 0x25ff, 0xc80d, 0x21, 0 - .dw 0x2640, 0xc80d, 0x267f, 0xc80d, 0x21, 0 - .dw 0x26c0, 0xc80d, 0x26ff, 0xc80d, 0x21, 0 - .dw 0x2740, 0xc80d, 0x277f, 0xc80d, 0x21, 0 - .dw 0x27c0, 0xc80d, 0x27ff, 0xc80d, 0x21, 0 - .dw 0x2840, 0xc80d, 0x287f, 0xc80d, 0x21, 0 - .dw 0x28c0, 0xc80d, 0x28ff, 0xc80d, 0x21, 0 - .dw 0x2940, 0xc80d, 0x297f, 0xc80d, 0x21, 0 - .dw 0x29c0, 0xc80d, 0x29ff, 0xc80d, 0x21, 0 - .dw 0x2a40, 0xc80d, 0x2a7f, 0xc80d, 0x21, 0 - .dw 0x2ac0, 0xc80d, 0x2aff, 0xc80d, 0x21, 0 - .dw 0x2b40, 0xc80d, 0x2b7f, 0xc80d, 0x21, 0 - .dw 0x2bc0, 0xc80d, 0x2bff, 0xc80d, 0x21, 0 - .dw 0x2c40, 0xc80d, 0x2c7f, 0xc80d, 0x21, 0 - .dw 0x2cc0, 0xc80d, 0x2cff, 0xc80d, 0x21, 0 - .dw 0x2d40, 0xc80d, 0x2d7f, 0xc80d, 0x21, 0 - .dw 0x2dc0, 0xc80d, 0x2dff, 0xc80d, 0x21, 0 - .dw 0x2e40, 0xc80d, 0x2e7f, 0xc80d, 0x21, 0 - .dw 0x2ec0, 0xc80d, 0x2eff, 0xc80d, 0x21, 0 - .dw 0x2f40, 0xc80d, 0x2f7f, 0xc80d, 0x21, 0 - .dw 0x2fc0, 0xc80d, 0x2fff, 0xc80d, 0x21, 0 - .dw 0x3040, 0xc80d, 0x307f, 0xc80d, 0x21, 0 - .dw 0x30c0, 0xc80d, 0x30ff, 0xc80d, 0x21, 0 - .dw 0x3140, 0xc80d, 0x317f, 0xc80d, 0x21, 0 - .dw 0x31c0, 0xc80d, 0x31ff, 0xc80d, 0x21, 0 - .dw 0x3240, 0xc80d, 0x327f, 0xc80d, 0x21, 0 - .dw 0x32c0, 0xc80d, 0x32ff, 0xc80d, 0x21, 0 - .dw 0x3340, 0xc80d, 0x337f, 0xc80d, 0x21, 0 - .dw 0x33c0, 0xc80d, 0x33ff, 0xc80d, 0x21, 0 - .dw 0x3440, 0xc80d, 0x347f, 0xc80d, 0x21, 0 - .dw 0x34c0, 0xc80d, 0x34ff, 0xc80d, 0x21, 0 - .dw 0x3540, 0xc80d, 0x357f, 0xc80d, 0x21, 0 - .dw 0x35c0, 0xc80d, 0x35ff, 0xc80d, 0x21, 0 - .dw 0x3640, 0xc80d, 0x367f, 0xc80d, 0x21, 0 - .dw 0x36c0, 0xc80d, 0x36ff, 0xc80d, 0x21, 0 - .dw 0x3740, 0xc80d, 0x377f, 0xc80d, 0x21, 0 - .dw 0x37c0, 0xc80d, 0x37ff, 0xc80d, 0x21, 0 - .dw 0x3840, 0xc80d, 0x387f, 0xc80d, 0x21, 0 - .dw 0x38c0, 0xc80d, 0x38ff, 0xc80d, 0x21, 0 - .dw 0x3940, 0xc80d, 0x397f, 0xc80d, 0x21, 0 - .dw 0x39c0, 0xc80d, 0x3fff, 0xc80d, 0x21, 0 - .dw 0x4040, 0xc80d, 0x407f, 0xc80d, 0x21, 0 - .dw 0x40c0, 0xc80d, 0x40ff, 0xc80d, 0x21, 0 - .dw 0x4140, 0xc80d, 0x417f, 0xc80d, 0x21, 0 - .dw 0x41c0, 0xc80d, 0x41ff, 0xc80d, 0x21, 0 - .dw 0x4240, 0xc80d, 0x427f, 0xc80d, 0x21, 0 - .dw 0x42c0, 0xc80d, 0x42ff, 0xc80d, 0x21, 0 - .dw 0x4340, 0xc80d, 0x437f, 0xc80d, 0x21, 0 - .dw 0x43c0, 0xc80d, 0x43ff, 0xc80d, 0x21, 0 - .dw 0x4440, 0xc80d, 0x447f, 0xc80d, 0x21, 0 - .dw 0x44c0, 0xc80d, 0x44ff, 0xc80d, 0x21, 0 - .dw 0x4540, 0xc80d, 0x457f, 0xc80d, 0x21, 0 - .dw 0x45c0, 0xc80d, 0x45ff, 0xc80d, 0x21, 0 - .dw 0x4640, 0xc80d, 0x467f, 0xc80d, 0x21, 0 - .dw 0x46c0, 0xc80d, 0x46ff, 0xc80d, 0x21, 0 - .dw 0x4740, 0xc80d, 0x477f, 0xc80d, 0x21, 0 - .dw 0x47c0, 0xc80d, 0x47ff, 0xc80d, 0x21, 0 - .dw 0x4840, 0xc80d, 0x487f, 0xc80d, 0x21, 0 - .dw 0x48c0, 0xc80d, 0x48ff, 0xc80d, 0x21, 0 - .dw 0x4940, 0xc80d, 0x497f, 0xc80d, 0x21, 0 - .dw 0x49c0, 0xc80d, 0x49ff, 0xc80d, 0x21, 0 - .dw 0x4a40, 0xc80d, 0x4a7f, 0xc80d, 0x21, 0 - .dw 0x4ac0, 0xc80d, 0x4aff, 0xc80d, 0x21, 0 - .dw 0x4b40, 0xc80d, 0x4b7f, 0xc80d, 0x21, 0 - .dw 0x4bc0, 0xc80d, 0x4bff, 0xc80d, 0x21, 0 - .dw 0x4c40, 0xc80d, 0x4c7f, 0xc80d, 0x21, 0 - .dw 0x4cc0, 0xc80d, 0x4cff, 0xc80d, 0x21, 0 - .dw 0x4d40, 0xc80d, 0x4d7f, 0xc80d, 0x21, 0 - .dw 0x4dc0, 0xc80d, 0x4dff, 0xc80d, 0x21, 0 - .dw 0x4e40, 0xc80d, 0x4e7f, 0xc80d, 0x21, 0 - .dw 0x4ec0, 0xc80d, 0x4eff, 0xc80d, 0x21, 0 - .dw 0x4f40, 0xc80d, 0x4f7f, 0xc80d, 0x21, 0 - .dw 0x4fc0, 0xc80d, 0x4fff, 0xc80d, 0x21, 0 - .dw 0x5040, 0xc80d, 0x507f, 0xc80d, 0x21, 0 - .dw 0x50c0, 0xc80d, 0x50ff, 0xc80d, 0x21, 0 - .dw 0x5140, 0xc80d, 0x517f, 0xc80d, 0x21, 0 - .dw 0x51c0, 0xc80d, 0x51ff, 0xc80d, 0x21, 0 - .dw 0x5240, 0xc80d, 0x527f, 0xc80d, 0x21, 0 - .dw 0x52c0, 0xc80d, 0x52ff, 0xc80d, 0x21, 0 - .dw 0x5340, 0xc80d, 0x537f, 0xc80d, 0x21, 0 - .dw 0x53c0, 0xc80d, 0x53ff, 0xc80d, 0x21, 0 - .dw 0x5440, 0xc80d, 0x547f, 0xc80d, 0x21, 0 - .dw 0x54c0, 0xc80d, 0x54ff, 0xc80d, 0x21, 0 - .dw 0x5540, 0xc80d, 0x557f, 0xc80d, 0x21, 0 - .dw 0x55c0, 0xc80d, 0x55ff, 0xc80d, 0x21, 0 - .dw 0x5640, 0xc80d, 0x567f, 0xc80d, 0x21, 0 - .dw 0x56c0, 0xc80d, 0x56ff, 0xc80d, 0x21, 0 - .dw 0x5740, 0xc80d, 0x577f, 0xc80d, 0x21, 0 - .dw 0x57c0, 0xc80d, 0x57ff, 0xc80d, 0x21, 0 - .dw 0x5840, 0xc80d, 0x587f, 0xc80d, 0x21, 0 - .dw 0x58c0, 0xc80d, 0x58ff, 0xc80d, 0x21, 0 - .dw 0x5940, 0xc80d, 0x597f, 0xc80d, 0x21, 0 - .dw 0x59c0, 0xc80d, 0x5fff, 0xc80d, 0x21, 0 - .dw 0x6040, 0xc80d, 0x607f, 0xc80d, 0x21, 0 - .dw 0x60c0, 0xc80d, 0x60ff, 0xc80d, 0x21, 0 - .dw 0x6140, 0xc80d, 0x617f, 0xc80d, 0x21, 0 - .dw 0x61c0, 0xc80d, 0x61ff, 0xc80d, 0x21, 0 - .dw 0x6240, 0xc80d, 0x627f, 0xc80d, 0x21, 0 - .dw 0x62c0, 0xc80d, 0x62ff, 0xc80d, 0x21, 0 - .dw 0x6340, 0xc80d, 0x637f, 0xc80d, 0x21, 0 - .dw 0x63c0, 0xc80d, 0x63ff, 0xc80d, 0x21, 0 - .dw 0x6440, 0xc80d, 0x647f, 0xc80d, 0x21, 0 - .dw 0x64c0, 0xc80d, 0x64ff, 0xc80d, 0x21, 0 - .dw 0x6540, 0xc80d, 0x657f, 0xc80d, 0x21, 0 - .dw 0x65c0, 0xc80d, 0x65ff, 0xc80d, 0x21, 0 - .dw 0x6640, 0xc80d, 0x667f, 0xc80d, 0x21, 0 - .dw 0x66c0, 0xc80d, 0x66ff, 0xc80d, 0x21, 0 - .dw 0x6740, 0xc80d, 0x677f, 0xc80d, 0x21, 0 - .dw 0x67c0, 0xc80d, 0x67ff, 0xc80d, 0x21, 0 - .dw 0x6840, 0xc80d, 0x687f, 0xc80d, 0x21, 0 - .dw 0x68c0, 0xc80d, 0x68ff, 0xc80d, 0x21, 0 - .dw 0x6940, 0xc80d, 0x697f, 0xc80d, 0x21, 0 - .dw 0x69c0, 0xc80d, 0x69ff, 0xc80d, 0x21, 0 - .dw 0x6a40, 0xc80d, 0x6a7f, 0xc80d, 0x21, 0 - .dw 0x6ac0, 0xc80d, 0x6aff, 0xc80d, 0x21, 0 - .dw 0x6b40, 0xc80d, 0x6b7f, 0xc80d, 0x21, 0 - .dw 0x6bc0, 0xc80d, 0x6bff, 0xc80d, 0x21, 0 - .dw 0x6c40, 0xc80d, 0x6c7f, 0xc80d, 0x21, 0 - .dw 0x6cc0, 0xc80d, 0x6cff, 0xc80d, 0x21, 0 - .dw 0x6d40, 0xc80d, 0x6d7f, 0xc80d, 0x21, 0 - .dw 0x6dc0, 0xc80d, 0x6dff, 0xc80d, 0x21, 0 - .dw 0x6e40, 0xc80d, 0x6e7f, 0xc80d, 0x21, 0 - .dw 0x6ec0, 0xc80d, 0x6eff, 0xc80d, 0x21, 0 - .dw 0x6f40, 0xc80d, 0x6f7f, 0xc80d, 0x21, 0 - .dw 0x6fc0, 0xc80d, 0x6fff, 0xc80d, 0x21, 0 - .dw 0x7040, 0xc80d, 0x707f, 0xc80d, 0x21, 0 - .dw 0x70c0, 0xc80d, 0x70ff, 0xc80d, 0x21, 0 - .dw 0x7140, 0xc80d, 0x717f, 0xc80d, 0x21, 0 - .dw 0x71c0, 0xc80d, 0x71ff, 0xc80d, 0x21, 0 - .dw 0x7240, 0xc80d, 0x727f, 0xc80d, 0x21, 0 - .dw 0x72c0, 0xc80d, 0x72ff, 0xc80d, 0x21, 0 - .dw 0x7340, 0xc80d, 0x737f, 0xc80d, 0x21, 0 - .dw 0x73c0, 0xc80d, 0x73ff, 0xc80d, 0x21, 0 - .dw 0x7440, 0xc80d, 0x747f, 0xc80d, 0x21, 0 - .dw 0x74c0, 0xc80d, 0x74ff, 0xc80d, 0x21, 0 - .dw 0x7540, 0xc80d, 0x757f, 0xc80d, 0x21, 0 - .dw 0x75c0, 0xc80d, 0x75ff, 0xc80d, 0x21, 0 - .dw 0x7640, 0xc80d, 0x767f, 0xc80d, 0x21, 0 - .dw 0x76c0, 0xc80d, 0x76ff, 0xc80d, 0x21, 0 - .dw 0x7740, 0xc80d, 0x777f, 0xc80d, 0x21, 0 - .dw 0x77c0, 0xc80d, 0x77ff, 0xc80d, 0x21, 0 - .dw 0x7840, 0xc80d, 0x787f, 0xc80d, 0x21, 0 - .dw 0x78c0, 0xc80d, 0x78ff, 0xc80d, 0x21, 0 - .dw 0x7940, 0xc80d, 0x797f, 0xc80d, 0x21, 0 - .dw 0x79c0, 0xc80d, 0x7fff, 0xc80d, 0x21, 0 - .dw 0x8040, 0xc80d, 0x807f, 0xc80d, 0x21, 0 - .dw 0x80c0, 0xc80d, 0x80ff, 0xc80d, 0x21, 0 - .dw 0x8140, 0xc80d, 0x817f, 0xc80d, 0x21, 0 - .dw 0x81c0, 0xc80d, 0x81ff, 0xc80d, 0x21, 0 - .dw 0x8240, 0xc80d, 0x827f, 0xc80d, 0x21, 0 - .dw 0x82c0, 0xc80d, 0x82ff, 0xc80d, 0x21, 0 - .dw 0x8340, 0xc80d, 0x837f, 0xc80d, 0x21, 0 - .dw 0x83c0, 0xc80d, 0x83ff, 0xc80d, 0x21, 0 - .dw 0x8440, 0xc80d, 0x847f, 0xc80d, 0x21, 0 - .dw 0x84c0, 0xc80d, 0x84ff, 0xc80d, 0x21, 0 - .dw 0x8540, 0xc80d, 0x857f, 0xc80d, 0x21, 0 - .dw 0x85c0, 0xc80d, 0x85ff, 0xc80d, 0x21, 0 - .dw 0x8640, 0xc80d, 0x867f, 0xc80d, 0x21, 0 - .dw 0x86c0, 0xc80d, 0x86ff, 0xc80d, 0x21, 0 - .dw 0x8740, 0xc80d, 0x877f, 0xc80d, 0x21, 0 - .dw 0x87c0, 0xc80d, 0x87ff, 0xc80d, 0x21, 0 - .dw 0x8840, 0xc80d, 0x887f, 0xc80d, 0x21, 0 - .dw 0x88c0, 0xc80d, 0x88ff, 0xc80d, 0x21, 0 - .dw 0x8940, 0xc80d, 0x897f, 0xc80d, 0x21, 0 - .dw 0x89c0, 0xc80d, 0x89ff, 0xc80d, 0x21, 0 - .dw 0x8a40, 0xc80d, 0x8a7f, 0xc80d, 0x21, 0 - .dw 0x8ac0, 0xc80d, 0x8aff, 0xc80d, 0x21, 0 - .dw 0x8b40, 0xc80d, 0x8b7f, 0xc80d, 0x21, 0 - .dw 0x8bc0, 0xc80d, 0x8bff, 0xc80d, 0x21, 0 - .dw 0x8c40, 0xc80d, 0x8c7f, 0xc80d, 0x21, 0 - .dw 0x8cc0, 0xc80d, 0x8cff, 0xc80d, 0x21, 0 - .dw 0x8d40, 0xc80d, 0x8d7f, 0xc80d, 0x21, 0 - .dw 0x8dc0, 0xc80d, 0x8dff, 0xc80d, 0x21, 0 - .dw 0x8e40, 0xc80d, 0x8e7f, 0xc80d, 0x21, 0 - .dw 0x8ec0, 0xc80d, 0x8eff, 0xc80d, 0x21, 0 - .dw 0x8f40, 0xc80d, 0x8f7f, 0xc80d, 0x21, 0 - .dw 0x8fc0, 0xc80d, 0x8fff, 0xc80d, 0x21, 0 - .dw 0x9040, 0xc80d, 0x907f, 0xc80d, 0x21, 0 - .dw 0x90c0, 0xc80d, 0x90ff, 0xc80d, 0x21, 0 - .dw 0x9140, 0xc80d, 0x917f, 0xc80d, 0x21, 0 - .dw 0x91c0, 0xc80d, 0x91ff, 0xc80d, 0x21, 0 - .dw 0x9240, 0xc80d, 0x927f, 0xc80d, 0x21, 0 - .dw 0x92c0, 0xc80d, 0x92ff, 0xc80d, 0x21, 0 - .dw 0x9340, 0xc80d, 0x937f, 0xc80d, 0x21, 0 - .dw 0x93c0, 0xc80d, 0x93ff, 0xc80d, 0x21, 0 - .dw 0x9440, 0xc80d, 0x947f, 0xc80d, 0x21, 0 - .dw 0x94c0, 0xc80d, 0x94ff, 0xc80d, 0x21, 0 - .dw 0x9540, 0xc80d, 0x957f, 0xc80d, 0x21, 0 - .dw 0x95c0, 0xc80d, 0x95ff, 0xc80d, 0x21, 0 - .dw 0x9640, 0xc80d, 0x967f, 0xc80d, 0x21, 0 - .dw 0x96c0, 0xc80d, 0x96ff, 0xc80d, 0x21, 0 - .dw 0x9740, 0xc80d, 0x977f, 0xc80d, 0x21, 0 - .dw 0x97c0, 0xc80d, 0x97ff, 0xc80d, 0x21, 0 - .dw 0x9840, 0xc80d, 0x987f, 0xc80d, 0x21, 0 - .dw 0x98c0, 0xc80d, 0x98ff, 0xc80d, 0x21, 0 - .dw 0x9940, 0xc80d, 0x997f, 0xc80d, 0x21, 0 - .dw 0x99c0, 0xc80d, 0x9fff, 0xc80d, 0x21, 0 - .dw 0xa040, 0xc80d, 0xa07f, 0xc80d, 0x21, 0 - .dw 0xa0c0, 0xc80d, 0xa0ff, 0xc80d, 0x21, 0 - .dw 0xa140, 0xc80d, 0xa17f, 0xc80d, 0x21, 0 - .dw 0xa1c0, 0xc80d, 0xa1ff, 0xc80d, 0x21, 0 - .dw 0xa240, 0xc80d, 0xa27f, 0xc80d, 0x21, 0 - .dw 0xa2c0, 0xc80d, 0xa2ff, 0xc80d, 0x21, 0 - .dw 0xa340, 0xc80d, 0xa37f, 0xc80d, 0x21, 0 - .dw 0xa3c0, 0xc80d, 0xa3ff, 0xc80d, 0x21, 0 - .dw 0xa440, 0xc80d, 0xa47f, 0xc80d, 0x21, 0 - .dw 0xa4c0, 0xc80d, 0xa4ff, 0xc80d, 0x21, 0 - .dw 0xa540, 0xc80d, 0xa57f, 0xc80d, 0x21, 0 - .dw 0xa5c0, 0xc80d, 0xa5ff, 0xc80d, 0x21, 0 - .dw 0xa640, 0xc80d, 0xa67f, 0xc80d, 0x21, 0 - .dw 0xa6c0, 0xc80d, 0xa6ff, 0xc80d, 0x21, 0 - .dw 0xa740, 0xc80d, 0xa77f, 0xc80d, 0x21, 0 - .dw 0xa7c0, 0xc80d, 0xa7ff, 0xc80d, 0x21, 0 - .dw 0xa840, 0xc80d, 0xa87f, 0xc80d, 0x21, 0 - .dw 0xa8c0, 0xc80d, 0xa8ff, 0xc80d, 0x21, 0 - .dw 0xa940, 0xc80d, 0xa97f, 0xc80d, 0x21, 0 - .dw 0xa9c0, 0xc80d, 0xa9ff, 0xc80d, 0x21, 0 - .dw 0xaa40, 0xc80d, 0xaa7f, 0xc80d, 0x21, 0 - .dw 0xaac0, 0xc80d, 0xaaff, 0xc80d, 0x21, 0 - .dw 0xab40, 0xc80d, 0xab7f, 0xc80d, 0x21, 0 - .dw 0xabc0, 0xc80d, 0xabff, 0xc80d, 0x21, 0 - .dw 0xac40, 0xc80d, 0xac7f, 0xc80d, 0x21, 0 - .dw 0xacc0, 0xc80d, 0xacff, 0xc80d, 0x21, 0 - .dw 0xad40, 0xc80d, 0xad7f, 0xc80d, 0x21, 0 - .dw 0xadc0, 0xc80d, 0xadff, 0xc80d, 0x21, 0 - .dw 0xae40, 0xc80d, 0xae7f, 0xc80d, 0x21, 0 - .dw 0xaec0, 0xc80d, 0xaeff, 0xc80d, 0x21, 0 - .dw 0xaf40, 0xc80d, 0xaf7f, 0xc80d, 0x21, 0 - .dw 0xafc0, 0xc80d, 0xafff, 0xc80d, 0x21, 0 - .dw 0xb040, 0xc80d, 0xb07f, 0xc80d, 0x21, 0 - .dw 0xb0c0, 0xc80d, 0xb0ff, 0xc80d, 0x21, 0 - .dw 0xb140, 0xc80d, 0xb17f, 0xc80d, 0x21, 0 - .dw 0xb1c0, 0xc80d, 0xb1ff, 0xc80d, 0x21, 0 - .dw 0xb240, 0xc80d, 0xb27f, 0xc80d, 0x21, 0 - .dw 0xb2c0, 0xc80d, 0xb2ff, 0xc80d, 0x21, 0 - .dw 0xb340, 0xc80d, 0xb37f, 0xc80d, 0x21, 0 - .dw 0xb3c0, 0xc80d, 0xb3ff, 0xc80d, 0x21, 0 - .dw 0xb440, 0xc80d, 0xb47f, 0xc80d, 0x21, 0 - .dw 0xb4c0, 0xc80d, 0xb4ff, 0xc80d, 0x21, 0 - .dw 0xb540, 0xc80d, 0xb57f, 0xc80d, 0x21, 0 - .dw 0xb5c0, 0xc80d, 0xb5ff, 0xc80d, 0x21, 0 - .dw 0xb640, 0xc80d, 0xb67f, 0xc80d, 0x21, 0 - .dw 0xb6c0, 0xc80d, 0xb6ff, 0xc80d, 0x21, 0 - .dw 0xb740, 0xc80d, 0xb77f, 0xc80d, 0x21, 0 - .dw 0xb7c0, 0xc80d, 0xb7ff, 0xc80d, 0x21, 0 - .dw 0xb840, 0xc80d, 0xb87f, 0xc80d, 0x21, 0 - .dw 0xb8c0, 0xc80d, 0xb8ff, 0xc80d, 0x21, 0 - .dw 0xb940, 0xc80d, 0xb97f, 0xc80d, 0x21, 0 - .dw 0xb9c0, 0xc80d, 0xbfff, 0xc80d, 0x21, 0 - .dw 0xc040, 0xc80d, 0xc07f, 0xc80d, 0x21, 0 - .dw 0xc0c0, 0xc80d, 0xc0ff, 0xc80d, 0x21, 0 - .dw 0xc140, 0xc80d, 0xc17f, 0xc80d, 0x21, 0 - .dw 0xc1c0, 0xc80d, 0xc1ff, 0xc80d, 0x21, 0 - .dw 0xc240, 0xc80d, 0xc27f, 0xc80d, 0x21, 0 - .dw 0xc2c0, 0xc80d, 0xc2ff, 0xc80d, 0x21, 0 - .dw 0xc340, 0xc80d, 0xc37f, 0xc80d, 0x21, 0 - .dw 0xc3c0, 0xc80d, 0xc3ff, 0xc80d, 0x21, 0 - .dw 0xc440, 0xc80d, 0xc47f, 0xc80d, 0x21, 0 - .dw 0xc4c0, 0xc80d, 0xc4ff, 0xc80d, 0x21, 0 - .dw 0xc540, 0xc80d, 0xc57f, 0xc80d, 0x21, 0 - .dw 0xc5c0, 0xc80d, 0xc5ff, 0xc80d, 0x21, 0 - .dw 0xc640, 0xc80d, 0xc67f, 0xc80d, 0x21, 0 - .dw 0xc6c0, 0xc80d, 0xc6ff, 0xc80d, 0x21, 0 - .dw 0xc740, 0xc80d, 0xc77f, 0xc80d, 0x21, 0 - .dw 0xc7c0, 0xc80d, 0xc7ff, 0xc80d, 0x21, 0 - .dw 0xc840, 0xc80d, 0xc87f, 0xc80d, 0x21, 0 - .dw 0xc8c0, 0xc80d, 0xc8ff, 0xc80d, 0x21, 0 - .dw 0xc940, 0xc80d, 0xc97f, 0xc80d, 0x21, 0 - .dw 0xc9c0, 0xc80d, 0xc9ff, 0xc80d, 0x21, 0 - .dw 0xca40, 0xc80d, 0xca7f, 0xc80d, 0x21, 0 - .dw 0xcac0, 0xc80d, 0xcaff, 0xc80d, 0x21, 0 - .dw 0xcb40, 0xc80d, 0xcb7f, 0xc80d, 0x21, 0 - .dw 0xcbc0, 0xc80d, 0xcbff, 0xc80d, 0x21, 0 - .dw 0xcc40, 0xc80d, 0xcc7f, 0xc80d, 0x21, 0 - .dw 0xccc0, 0xc80d, 0xccff, 0xc80d, 0x21, 0 - .dw 0xcd40, 0xc80d, 0xcd7f, 0xc80d, 0x21, 0 - .dw 0xcdc0, 0xc80d, 0xcdff, 0xc80d, 0x21, 0 - .dw 0xce40, 0xc80d, 0xce7f, 0xc80d, 0x21, 0 - .dw 0xcec0, 0xc80d, 0xceff, 0xc80d, 0x21, 0 - .dw 0xcf40, 0xc80d, 0xcf7f, 0xc80d, 0x21, 0 - .dw 0xcfc0, 0xc80d, 0xcfff, 0xc80d, 0x21, 0 - .dw 0xd040, 0xc80d, 0xd07f, 0xc80d, 0x21, 0 - .dw 0xd0c0, 0xc80d, 0xd0ff, 0xc80d, 0x21, 0 - .dw 0xd140, 0xc80d, 0xd17f, 0xc80d, 0x21, 0 - .dw 0xd1c0, 0xc80d, 0xd1ff, 0xc80d, 0x21, 0 - .dw 0xd240, 0xc80d, 0xd27f, 0xc80d, 0x21, 0 - .dw 0xd2c0, 0xc80d, 0xd2ff, 0xc80d, 0x21, 0 - .dw 0xd340, 0xc80d, 0xd37f, 0xc80d, 0x21, 0 - .dw 0xd3c0, 0xc80d, 0xd3ff, 0xc80d, 0x21, 0 - .dw 0xd440, 0xc80d, 0xd47f, 0xc80d, 0x21, 0 - .dw 0xd4c0, 0xc80d, 0xd4ff, 0xc80d, 0x21, 0 - .dw 0xd540, 0xc80d, 0xd57f, 0xc80d, 0x21, 0 - .dw 0xd5c0, 0xc80d, 0xd5ff, 0xc80d, 0x21, 0 - .dw 0xd640, 0xc80d, 0xd67f, 0xc80d, 0x21, 0 - .dw 0xd6c0, 0xc80d, 0xd6ff, 0xc80d, 0x21, 0 - .dw 0xd740, 0xc80d, 0xd77f, 0xc80d, 0x21, 0 - .dw 0xd7c0, 0xc80d, 0xd7ff, 0xc80d, 0x21, 0 - .dw 0xd840, 0xc80d, 0xd87f, 0xc80d, 0x21, 0 - .dw 0xd8c0, 0xc80d, 0xd8ff, 0xc80d, 0x21, 0 - .dw 0xd940, 0xc80d, 0xd97f, 0xc80d, 0x21, 0 - .dw 0xd9c0, 0xc80d, 0xdfff, 0xc80d, 0x21, 0 - .dw 0xe040, 0xc80d, 0xe07f, 0xc80d, 0x21, 0 - .dw 0xe0c0, 0xc80d, 0xe0ff, 0xc80d, 0x21, 0 - .dw 0xe140, 0xc80d, 0xe17f, 0xc80d, 0x21, 0 - .dw 0xe1c0, 0xc80d, 0xe1ff, 0xc80d, 0x21, 0 - .dw 0xe240, 0xc80d, 0xe27f, 0xc80d, 0x21, 0 - .dw 0xe2c0, 0xc80d, 0xe2ff, 0xc80d, 0x21, 0 - .dw 0xe340, 0xc80d, 0xe37f, 0xc80d, 0x21, 0 - .dw 0xe3c0, 0xc80d, 0xe3ff, 0xc80d, 0x21, 0 - .dw 0xe440, 0xc80d, 0xe47f, 0xc80d, 0x21, 0 - .dw 0xe4c0, 0xc80d, 0xe4ff, 0xc80d, 0x21, 0 - .dw 0xe540, 0xc80d, 0xe57f, 0xc80d, 0x21, 0 - .dw 0xe5c0, 0xc80d, 0xe5ff, 0xc80d, 0x21, 0 - .dw 0xe640, 0xc80d, 0xe67f, 0xc80d, 0x21, 0 - .dw 0xe6c0, 0xc80d, 0xe6ff, 0xc80d, 0x21, 0 - .dw 0xe740, 0xc80d, 0xe77f, 0xc80d, 0x21, 0 - .dw 0xe7c0, 0xc80d, 0xe7ff, 0xc80d, 0x21, 0 - .dw 0xe840, 0xc80d, 0xe87f, 0xc80d, 0x21, 0 - .dw 0xe8c0, 0xc80d, 0xe8ff, 0xc80d, 0x21, 0 - .dw 0xe940, 0xc80d, 0xe97f, 0xc80d, 0x21, 0 - .dw 0xe9c0, 0xc80d, 0xe9ff, 0xc80d, 0x21, 0 - .dw 0xea40, 0xc80d, 0xea7f, 0xc80d, 0x21, 0 - .dw 0xeac0, 0xc80d, 0xeaff, 0xc80d, 0x21, 0 - .dw 0xeb40, 0xc80d, 0xeb7f, 0xc80d, 0x21, 0 - .dw 0xebc0, 0xc80d, 0xebff, 0xc80d, 0x21, 0 - .dw 0xec40, 0xc80d, 0xec7f, 0xc80d, 0x21, 0 - .dw 0xecc0, 0xc80d, 0xecff, 0xc80d, 0x21, 0 - .dw 0xed40, 0xc80d, 0xed7f, 0xc80d, 0x21, 0 - .dw 0xedc0, 0xc80d, 0xedff, 0xc80d, 0x21, 0 - .dw 0xee40, 0xc80d, 0xee7f, 0xc80d, 0x21, 0 - .dw 0xeec0, 0xc80d, 0xeeff, 0xc80d, 0x21, 0 - .dw 0xef40, 0xc80d, 0xef7f, 0xc80d, 0x21, 0 - .dw 0xefc0, 0xc80d, 0xefff, 0xc80d, 0x21, 0 - .dw 0xf040, 0xc80d, 0xf07f, 0xc80d, 0x21, 0 - .dw 0xf0c0, 0xc80d, 0xf0ff, 0xc80d, 0x21, 0 - .dw 0xf140, 0xc80d, 0xf17f, 0xc80d, 0x21, 0 - .dw 0xf1c0, 0xc80d, 0xf1ff, 0xc80d, 0x21, 0 - .dw 0xf240, 0xc80d, 0xf27f, 0xc80d, 0x21, 0 - .dw 0xf2c0, 0xc80d, 0xf2ff, 0xc80d, 0x21, 0 - .dw 0xf340, 0xc80d, 0xf37f, 0xc80d, 0x21, 0 - .dw 0xf3c0, 0xc80d, 0xf3ff, 0xc80d, 0x21, 0 - .dw 0xf440, 0xc80d, 0xf47f, 0xc80d, 0x21, 0 - .dw 0xf4c0, 0xc80d, 0xf4ff, 0xc80d, 0x21, 0 - .dw 0xf540, 0xc80d, 0xf57f, 0xc80d, 0x21, 0 - .dw 0xf5c0, 0xc80d, 0xf5ff, 0xc80d, 0x21, 0 - .dw 0xf640, 0xc80d, 0xf67f, 0xc80d, 0x21, 0 - .dw 0xf6c0, 0xc80d, 0xf6ff, 0xc80d, 0x21, 0 - .dw 0xf740, 0xc80d, 0xf77f, 0xc80d, 0x21, 0 - .dw 0xf7c0, 0xc80d, 0xf7ff, 0xc80d, 0x21, 0 - .dw 0xf840, 0xc80d, 0xf87f, 0xc80d, 0x21, 0 - .dw 0xf8c0, 0xc80d, 0xf8ff, 0xc80d, 0x21, 0 - .dw 0xf940, 0xc80d, 0xf97f, 0xc80d, 0x21, 0 - .dw 0xf9c0, 0xc80d, 0xffff, 0xc80d, 0x21, 0 - .dw 0x0040, 0xc80e, 0x007f, 0xc80e, 0x21, 0 - .dw 0x00c0, 0xc80e, 0x00ff, 0xc80e, 0x21, 0 - .dw 0x0140, 0xc80e, 0x017f, 0xc80e, 0x21, 0 - .dw 0x01c0, 0xc80e, 0x01ff, 0xc80e, 0x21, 0 - .dw 0x0240, 0xc80e, 0x027f, 0xc80e, 0x21, 0 - .dw 0x02c0, 0xc80e, 0x02ff, 0xc80e, 0x21, 0 - .dw 0x0340, 0xc80e, 0x037f, 0xc80e, 0x21, 0 - .dw 0x03c0, 0xc80e, 0x03ff, 0xc80e, 0x21, 0 - .dw 0x0440, 0xc80e, 0x047f, 0xc80e, 0x21, 0 - .dw 0x04c0, 0xc80e, 0x04ff, 0xc80e, 0x21, 0 - .dw 0x0540, 0xc80e, 0x057f, 0xc80e, 0x21, 0 - .dw 0x05c0, 0xc80e, 0x05ff, 0xc80e, 0x21, 0 - .dw 0x0640, 0xc80e, 0x067f, 0xc80e, 0x21, 0 - .dw 0x06c0, 0xc80e, 0x06ff, 0xc80e, 0x21, 0 - .dw 0x0740, 0xc80e, 0x077f, 0xc80e, 0x21, 0 - .dw 0x07c0, 0xc80e, 0x07ff, 0xc80e, 0x21, 0 - .dw 0x0840, 0xc80e, 0x087f, 0xc80e, 0x21, 0 - .dw 0x08c0, 0xc80e, 0x08ff, 0xc80e, 0x21, 0 - .dw 0x0940, 0xc80e, 0x097f, 0xc80e, 0x21, 0 - .dw 0x09c0, 0xc80e, 0x09ff, 0xc80e, 0x21, 0 - .dw 0x0a40, 0xc80e, 0x0a7f, 0xc80e, 0x21, 0 - .dw 0x0ac0, 0xc80e, 0x0aff, 0xc80e, 0x21, 0 - .dw 0x0b40, 0xc80e, 0x0b7f, 0xc80e, 0x21, 0 - .dw 0x0bc0, 0xc80e, 0x0bff, 0xc80e, 0x21, 0 - .dw 0x0c40, 0xc80e, 0x0c7f, 0xc80e, 0x21, 0 - .dw 0x0cc0, 0xc80e, 0x0cff, 0xc80e, 0x21, 0 - .dw 0x0d40, 0xc80e, 0x0d7f, 0xc80e, 0x21, 0 - .dw 0x0dc0, 0xc80e, 0x0dff, 0xc80e, 0x21, 0 - .dw 0x0e40, 0xc80e, 0x0e7f, 0xc80e, 0x21, 0 - .dw 0x0ec0, 0xc80e, 0x0eff, 0xc80e, 0x21, 0 - .dw 0x0f40, 0xc80e, 0x0f7f, 0xc80e, 0x21, 0 - .dw 0x0fc0, 0xc80e, 0x0fff, 0xc80e, 0x21, 0 - .dw 0x1040, 0xc80e, 0x107f, 0xc80e, 0x21, 0 - .dw 0x10c0, 0xc80e, 0x10ff, 0xc80e, 0x21, 0 - .dw 0x1140, 0xc80e, 0x117f, 0xc80e, 0x21, 0 - .dw 0x11c0, 0xc80e, 0x11ff, 0xc80e, 0x21, 0 - .dw 0x1240, 0xc80e, 0x127f, 0xc80e, 0x21, 0 - .dw 0x12c0, 0xc80e, 0x12ff, 0xc80e, 0x21, 0 - .dw 0x1340, 0xc80e, 0x137f, 0xc80e, 0x21, 0 - .dw 0x13c0, 0xc80e, 0x13ff, 0xc80e, 0x21, 0 - .dw 0x1440, 0xc80e, 0x147f, 0xc80e, 0x21, 0 - .dw 0x14c0, 0xc80e, 0x14ff, 0xc80e, 0x21, 0 - .dw 0x1540, 0xc80e, 0x157f, 0xc80e, 0x21, 0 - .dw 0x15c0, 0xc80e, 0x15ff, 0xc80e, 0x21, 0 - .dw 0x1640, 0xc80e, 0x167f, 0xc80e, 0x21, 0 - .dw 0x16c0, 0xc80e, 0x16ff, 0xc80e, 0x21, 0 - .dw 0x1740, 0xc80e, 0x177f, 0xc80e, 0x21, 0 - .dw 0x17c0, 0xc80e, 0x17ff, 0xc80e, 0x21, 0 - .dw 0x1840, 0xc80e, 0x187f, 0xc80e, 0x21, 0 - .dw 0x18c0, 0xc80e, 0x18ff, 0xc80e, 0x21, 0 - .dw 0x1940, 0xc80e, 0x197f, 0xc80e, 0x21, 0 - .dw 0x19c0, 0xc80e, 0x1fff, 0xc80e, 0x21, 0 - .dw 0x2040, 0xc80e, 0x207f, 0xc80e, 0x21, 0 - .dw 0x20c0, 0xc80e, 0x20ff, 0xc80e, 0x21, 0 - .dw 0x2140, 0xc80e, 0x217f, 0xc80e, 0x21, 0 - .dw 0x21c0, 0xc80e, 0x21ff, 0xc80e, 0x21, 0 - .dw 0x2240, 0xc80e, 0x227f, 0xc80e, 0x21, 0 - .dw 0x22c0, 0xc80e, 0x22ff, 0xc80e, 0x21, 0 - .dw 0x2340, 0xc80e, 0x237f, 0xc80e, 0x21, 0 - .dw 0x23c0, 0xc80e, 0x23ff, 0xc80e, 0x21, 0 - .dw 0x2440, 0xc80e, 0x247f, 0xc80e, 0x21, 0 - .dw 0x24c0, 0xc80e, 0x24ff, 0xc80e, 0x21, 0 - .dw 0x2540, 0xc80e, 0x257f, 0xc80e, 0x21, 0 - .dw 0x25c0, 0xc80e, 0x25ff, 0xc80e, 0x21, 0 - .dw 0x2640, 0xc80e, 0x267f, 0xc80e, 0x21, 0 - .dw 0x26c0, 0xc80e, 0x26ff, 0xc80e, 0x21, 0 - .dw 0x2740, 0xc80e, 0x277f, 0xc80e, 0x21, 0 - .dw 0x27c0, 0xc80e, 0x27ff, 0xc80e, 0x21, 0 - .dw 0x2840, 0xc80e, 0x287f, 0xc80e, 0x21, 0 - .dw 0x28c0, 0xc80e, 0x28ff, 0xc80e, 0x21, 0 - .dw 0x2940, 0xc80e, 0x297f, 0xc80e, 0x21, 0 - .dw 0x29c0, 0xc80e, 0x29ff, 0xc80e, 0x21, 0 - .dw 0x2a40, 0xc80e, 0x2a7f, 0xc80e, 0x21, 0 - .dw 0x2ac0, 0xc80e, 0x2aff, 0xc80e, 0x21, 0 - .dw 0x2b40, 0xc80e, 0x2b7f, 0xc80e, 0x21, 0 - .dw 0x2bc0, 0xc80e, 0x2bff, 0xc80e, 0x21, 0 - .dw 0x2c40, 0xc80e, 0x2c7f, 0xc80e, 0x21, 0 - .dw 0x2cc0, 0xc80e, 0x2cff, 0xc80e, 0x21, 0 - .dw 0x2d40, 0xc80e, 0x2d7f, 0xc80e, 0x21, 0 - .dw 0x2dc0, 0xc80e, 0x2dff, 0xc80e, 0x21, 0 - .dw 0x2e40, 0xc80e, 0x2e7f, 0xc80e, 0x21, 0 - .dw 0x2ec0, 0xc80e, 0x2eff, 0xc80e, 0x21, 0 - .dw 0x2f40, 0xc80e, 0x2f7f, 0xc80e, 0x21, 0 - .dw 0x2fc0, 0xc80e, 0x2fff, 0xc80e, 0x21, 0 - .dw 0x3040, 0xc80e, 0x307f, 0xc80e, 0x21, 0 - .dw 0x30c0, 0xc80e, 0x30ff, 0xc80e, 0x21, 0 - .dw 0x3140, 0xc80e, 0x317f, 0xc80e, 0x21, 0 - .dw 0x31c0, 0xc80e, 0x31ff, 0xc80e, 0x21, 0 - .dw 0x3240, 0xc80e, 0x327f, 0xc80e, 0x21, 0 - .dw 0x32c0, 0xc80e, 0x32ff, 0xc80e, 0x21, 0 - .dw 0x3340, 0xc80e, 0x337f, 0xc80e, 0x21, 0 - .dw 0x33c0, 0xc80e, 0x33ff, 0xc80e, 0x21, 0 - .dw 0x3440, 0xc80e, 0x347f, 0xc80e, 0x21, 0 - .dw 0x34c0, 0xc80e, 0x34ff, 0xc80e, 0x21, 0 - .dw 0x3540, 0xc80e, 0x357f, 0xc80e, 0x21, 0 - .dw 0x35c0, 0xc80e, 0x35ff, 0xc80e, 0x21, 0 - .dw 0x3640, 0xc80e, 0x367f, 0xc80e, 0x21, 0 - .dw 0x36c0, 0xc80e, 0x36ff, 0xc80e, 0x21, 0 - .dw 0x3740, 0xc80e, 0x377f, 0xc80e, 0x21, 0 - .dw 0x37c0, 0xc80e, 0x37ff, 0xc80e, 0x21, 0 - .dw 0x3840, 0xc80e, 0x387f, 0xc80e, 0x21, 0 - .dw 0x38c0, 0xc80e, 0x38ff, 0xc80e, 0x21, 0 - .dw 0x3940, 0xc80e, 0x397f, 0xc80e, 0x21, 0 - .dw 0x39c0, 0xc80e, 0x3fff, 0xc80e, 0x21, 0 - .dw 0x4040, 0xc80e, 0x407f, 0xc80e, 0x21, 0 - .dw 0x40c0, 0xc80e, 0x40ff, 0xc80e, 0x21, 0 - .dw 0x4140, 0xc80e, 0x417f, 0xc80e, 0x21, 0 - .dw 0x41c0, 0xc80e, 0x41ff, 0xc80e, 0x21, 0 - .dw 0x4240, 0xc80e, 0x427f, 0xc80e, 0x21, 0 - .dw 0x42c0, 0xc80e, 0x42ff, 0xc80e, 0x21, 0 - .dw 0x4340, 0xc80e, 0x437f, 0xc80e, 0x21, 0 - .dw 0x43c0, 0xc80e, 0x43ff, 0xc80e, 0x21, 0 - .dw 0x4440, 0xc80e, 0x447f, 0xc80e, 0x21, 0 - .dw 0x44c0, 0xc80e, 0x44ff, 0xc80e, 0x21, 0 - .dw 0x4540, 0xc80e, 0x457f, 0xc80e, 0x21, 0 - .dw 0x45c0, 0xc80e, 0x45ff, 0xc80e, 0x21, 0 - .dw 0x4640, 0xc80e, 0x467f, 0xc80e, 0x21, 0 - .dw 0x46c0, 0xc80e, 0x46ff, 0xc80e, 0x21, 0 - .dw 0x4740, 0xc80e, 0x477f, 0xc80e, 0x21, 0 - .dw 0x47c0, 0xc80e, 0x47ff, 0xc80e, 0x21, 0 - .dw 0x4840, 0xc80e, 0x487f, 0xc80e, 0x21, 0 - .dw 0x48c0, 0xc80e, 0x48ff, 0xc80e, 0x21, 0 - .dw 0x4940, 0xc80e, 0x497f, 0xc80e, 0x21, 0 - .dw 0x49c0, 0xc80e, 0x49ff, 0xc80e, 0x21, 0 - .dw 0x4a40, 0xc80e, 0x4a7f, 0xc80e, 0x21, 0 - .dw 0x4ac0, 0xc80e, 0x4aff, 0xc80e, 0x21, 0 - .dw 0x4b40, 0xc80e, 0x4b7f, 0xc80e, 0x21, 0 - .dw 0x4bc0, 0xc80e, 0x4bff, 0xc80e, 0x21, 0 - .dw 0x4c40, 0xc80e, 0x4c7f, 0xc80e, 0x21, 0 - .dw 0x4cc0, 0xc80e, 0x4cff, 0xc80e, 0x21, 0 - .dw 0x4d40, 0xc80e, 0x4d7f, 0xc80e, 0x21, 0 - .dw 0x4dc0, 0xc80e, 0x4dff, 0xc80e, 0x21, 0 - .dw 0x4e40, 0xc80e, 0x4e7f, 0xc80e, 0x21, 0 - .dw 0x4ec0, 0xc80e, 0x4eff, 0xc80e, 0x21, 0 - .dw 0x4f40, 0xc80e, 0x4f7f, 0xc80e, 0x21, 0 - .dw 0x4fc0, 0xc80e, 0x4fff, 0xc80e, 0x21, 0 - .dw 0x5040, 0xc80e, 0x507f, 0xc80e, 0x21, 0 - .dw 0x50c0, 0xc80e, 0x50ff, 0xc80e, 0x21, 0 - .dw 0x5140, 0xc80e, 0x517f, 0xc80e, 0x21, 0 - .dw 0x51c0, 0xc80e, 0x51ff, 0xc80e, 0x21, 0 - .dw 0x5240, 0xc80e, 0x527f, 0xc80e, 0x21, 0 - .dw 0x52c0, 0xc80e, 0x52ff, 0xc80e, 0x21, 0 - .dw 0x5340, 0xc80e, 0x537f, 0xc80e, 0x21, 0 - .dw 0x53c0, 0xc80e, 0x53ff, 0xc80e, 0x21, 0 - .dw 0x5440, 0xc80e, 0x547f, 0xc80e, 0x21, 0 - .dw 0x54c0, 0xc80e, 0x54ff, 0xc80e, 0x21, 0 - .dw 0x5540, 0xc80e, 0x557f, 0xc80e, 0x21, 0 - .dw 0x55c0, 0xc80e, 0x55ff, 0xc80e, 0x21, 0 - .dw 0x5640, 0xc80e, 0x567f, 0xc80e, 0x21, 0 - .dw 0x56c0, 0xc80e, 0x56ff, 0xc80e, 0x21, 0 - .dw 0x5740, 0xc80e, 0x577f, 0xc80e, 0x21, 0 - .dw 0x57c0, 0xc80e, 0x57ff, 0xc80e, 0x21, 0 - .dw 0x5840, 0xc80e, 0x587f, 0xc80e, 0x21, 0 - .dw 0x58c0, 0xc80e, 0x58ff, 0xc80e, 0x21, 0 - .dw 0x5940, 0xc80e, 0x597f, 0xc80e, 0x21, 0 - .dw 0x59c0, 0xc80e, 0x5fff, 0xc80e, 0x21, 0 - .dw 0x6040, 0xc80e, 0x607f, 0xc80e, 0x21, 0 - .dw 0x60c0, 0xc80e, 0x60ff, 0xc80e, 0x21, 0 - .dw 0x6140, 0xc80e, 0x617f, 0xc80e, 0x21, 0 - .dw 0x61c0, 0xc80e, 0x61ff, 0xc80e, 0x21, 0 - .dw 0x6240, 0xc80e, 0x627f, 0xc80e, 0x21, 0 - .dw 0x62c0, 0xc80e, 0x62ff, 0xc80e, 0x21, 0 - .dw 0x6340, 0xc80e, 0x637f, 0xc80e, 0x21, 0 - .dw 0x63c0, 0xc80e, 0x63ff, 0xc80e, 0x21, 0 - .dw 0x6440, 0xc80e, 0x647f, 0xc80e, 0x21, 0 - .dw 0x64c0, 0xc80e, 0x64ff, 0xc80e, 0x21, 0 - .dw 0x6540, 0xc80e, 0x657f, 0xc80e, 0x21, 0 - .dw 0x65c0, 0xc80e, 0x65ff, 0xc80e, 0x21, 0 - .dw 0x6640, 0xc80e, 0x667f, 0xc80e, 0x21, 0 - .dw 0x66c0, 0xc80e, 0x66ff, 0xc80e, 0x21, 0 - .dw 0x6740, 0xc80e, 0x677f, 0xc80e, 0x21, 0 - .dw 0x67c0, 0xc80e, 0x67ff, 0xc80e, 0x21, 0 - .dw 0x6840, 0xc80e, 0x687f, 0xc80e, 0x21, 0 - .dw 0x68c0, 0xc80e, 0x68ff, 0xc80e, 0x21, 0 - .dw 0x6940, 0xc80e, 0x697f, 0xc80e, 0x21, 0 - .dw 0x69c0, 0xc80e, 0x69ff, 0xc80e, 0x21, 0 - .dw 0x6a40, 0xc80e, 0x6a7f, 0xc80e, 0x21, 0 - .dw 0x6ac0, 0xc80e, 0x6aff, 0xc80e, 0x21, 0 - .dw 0x6b40, 0xc80e, 0x6b7f, 0xc80e, 0x21, 0 - .dw 0x6bc0, 0xc80e, 0x6bff, 0xc80e, 0x21, 0 - .dw 0x6c40, 0xc80e, 0x6c7f, 0xc80e, 0x21, 0 - .dw 0x6cc0, 0xc80e, 0x6cff, 0xc80e, 0x21, 0 - .dw 0x6d40, 0xc80e, 0x6d7f, 0xc80e, 0x21, 0 - .dw 0x6dc0, 0xc80e, 0x6dff, 0xc80e, 0x21, 0 - .dw 0x6e40, 0xc80e, 0x6e7f, 0xc80e, 0x21, 0 - .dw 0x6ec0, 0xc80e, 0x6eff, 0xc80e, 0x21, 0 - .dw 0x6f40, 0xc80e, 0x6f7f, 0xc80e, 0x21, 0 - .dw 0x6fc0, 0xc80e, 0x6fff, 0xc80e, 0x21, 0 - .dw 0x7040, 0xc80e, 0x707f, 0xc80e, 0x21, 0 - .dw 0x70c0, 0xc80e, 0x70ff, 0xc80e, 0x21, 0 - .dw 0x7140, 0xc80e, 0x717f, 0xc80e, 0x21, 0 - .dw 0x71c0, 0xc80e, 0x71ff, 0xc80e, 0x21, 0 - .dw 0x7240, 0xc80e, 0x727f, 0xc80e, 0x21, 0 - .dw 0x72c0, 0xc80e, 0x72ff, 0xc80e, 0x21, 0 - .dw 0x7340, 0xc80e, 0x737f, 0xc80e, 0x21, 0 - .dw 0x73c0, 0xc80e, 0x73ff, 0xc80e, 0x21, 0 - .dw 0x7440, 0xc80e, 0x747f, 0xc80e, 0x21, 0 - .dw 0x74c0, 0xc80e, 0x74ff, 0xc80e, 0x21, 0 - .dw 0x7540, 0xc80e, 0x757f, 0xc80e, 0x21, 0 - .dw 0x75c0, 0xc80e, 0x75ff, 0xc80e, 0x21, 0 - .dw 0x7640, 0xc80e, 0x767f, 0xc80e, 0x21, 0 - .dw 0x76c0, 0xc80e, 0x76ff, 0xc80e, 0x21, 0 - .dw 0x7740, 0xc80e, 0x777f, 0xc80e, 0x21, 0 - .dw 0x77c0, 0xc80e, 0x77ff, 0xc80e, 0x21, 0 - .dw 0x7840, 0xc80e, 0x787f, 0xc80e, 0x21, 0 - .dw 0x78c0, 0xc80e, 0x78ff, 0xc80e, 0x21, 0 - .dw 0x7940, 0xc80e, 0x797f, 0xc80e, 0x21, 0 - .dw 0x79c0, 0xc80e, 0x7fff, 0xc80e, 0x21, 0 - .dw 0x8040, 0xc80e, 0x807f, 0xc80e, 0x21, 0 - .dw 0x80c0, 0xc80e, 0x80ff, 0xc80e, 0x21, 0 - .dw 0x8140, 0xc80e, 0x817f, 0xc80e, 0x21, 0 - .dw 0x81c0, 0xc80e, 0x81ff, 0xc80e, 0x21, 0 - .dw 0x8240, 0xc80e, 0x827f, 0xc80e, 0x21, 0 - .dw 0x82c0, 0xc80e, 0x82ff, 0xc80e, 0x21, 0 - .dw 0x8340, 0xc80e, 0x837f, 0xc80e, 0x21, 0 - .dw 0x83c0, 0xc80e, 0x83ff, 0xc80e, 0x21, 0 - .dw 0x8440, 0xc80e, 0x847f, 0xc80e, 0x21, 0 - .dw 0x84c0, 0xc80e, 0x84ff, 0xc80e, 0x21, 0 - .dw 0x8540, 0xc80e, 0x857f, 0xc80e, 0x21, 0 - .dw 0x85c0, 0xc80e, 0x85ff, 0xc80e, 0x21, 0 - .dw 0x8640, 0xc80e, 0x867f, 0xc80e, 0x21, 0 - .dw 0x86c0, 0xc80e, 0x86ff, 0xc80e, 0x21, 0 - .dw 0x8740, 0xc80e, 0x877f, 0xc80e, 0x21, 0 - .dw 0x87c0, 0xc80e, 0x87ff, 0xc80e, 0x21, 0 - .dw 0x8840, 0xc80e, 0x887f, 0xc80e, 0x21, 0 - .dw 0x88c0, 0xc80e, 0x88ff, 0xc80e, 0x21, 0 - .dw 0x8940, 0xc80e, 0x897f, 0xc80e, 0x21, 0 - .dw 0x89c0, 0xc80e, 0x89ff, 0xc80e, 0x21, 0 - .dw 0x8a40, 0xc80e, 0x8a7f, 0xc80e, 0x21, 0 - .dw 0x8ac0, 0xc80e, 0x8aff, 0xc80e, 0x21, 0 - .dw 0x8b40, 0xc80e, 0x8b7f, 0xc80e, 0x21, 0 - .dw 0x8bc0, 0xc80e, 0x8bff, 0xc80e, 0x21, 0 - .dw 0x8c40, 0xc80e, 0x8c7f, 0xc80e, 0x21, 0 - .dw 0x8cc0, 0xc80e, 0x8cff, 0xc80e, 0x21, 0 - .dw 0x8d40, 0xc80e, 0x8d7f, 0xc80e, 0x21, 0 - .dw 0x8dc0, 0xc80e, 0x8dff, 0xc80e, 0x21, 0 - .dw 0x8e40, 0xc80e, 0x8e7f, 0xc80e, 0x21, 0 - .dw 0x8ec0, 0xc80e, 0x8eff, 0xc80e, 0x21, 0 - .dw 0x8f40, 0xc80e, 0x8f7f, 0xc80e, 0x21, 0 - .dw 0x8fc0, 0xc80e, 0x8fff, 0xc80e, 0x21, 0 - .dw 0x9040, 0xc80e, 0x907f, 0xc80e, 0x21, 0 - .dw 0x90c0, 0xc80e, 0x90ff, 0xc80e, 0x21, 0 - .dw 0x9140, 0xc80e, 0x917f, 0xc80e, 0x21, 0 - .dw 0x91c0, 0xc80e, 0x91ff, 0xc80e, 0x21, 0 - .dw 0x9240, 0xc80e, 0x927f, 0xc80e, 0x21, 0 - .dw 0x92c0, 0xc80e, 0x92ff, 0xc80e, 0x21, 0 - .dw 0x9340, 0xc80e, 0x937f, 0xc80e, 0x21, 0 - .dw 0x93c0, 0xc80e, 0x93ff, 0xc80e, 0x21, 0 - .dw 0x9440, 0xc80e, 0x947f, 0xc80e, 0x21, 0 - .dw 0x94c0, 0xc80e, 0x94ff, 0xc80e, 0x21, 0 - .dw 0x9540, 0xc80e, 0x957f, 0xc80e, 0x21, 0 - .dw 0x95c0, 0xc80e, 0x95ff, 0xc80e, 0x21, 0 - .dw 0x9640, 0xc80e, 0x967f, 0xc80e, 0x21, 0 - .dw 0x96c0, 0xc80e, 0x96ff, 0xc80e, 0x21, 0 - .dw 0x9740, 0xc80e, 0x977f, 0xc80e, 0x21, 0 - .dw 0x97c0, 0xc80e, 0x97ff, 0xc80e, 0x21, 0 - .dw 0x9840, 0xc80e, 0x987f, 0xc80e, 0x21, 0 - .dw 0x98c0, 0xc80e, 0x98ff, 0xc80e, 0x21, 0 - .dw 0x9940, 0xc80e, 0x997f, 0xc80e, 0x21, 0 - .dw 0x99c0, 0xc80e, 0x9fff, 0xc80e, 0x21, 0 - .dw 0xa040, 0xc80e, 0xa07f, 0xc80e, 0x21, 0 - .dw 0xa0c0, 0xc80e, 0xa0ff, 0xc80e, 0x21, 0 - .dw 0xa140, 0xc80e, 0xa17f, 0xc80e, 0x21, 0 - .dw 0xa1c0, 0xc80e, 0xa1ff, 0xc80e, 0x21, 0 - .dw 0xa240, 0xc80e, 0xa27f, 0xc80e, 0x21, 0 - .dw 0xa2c0, 0xc80e, 0xa2ff, 0xc80e, 0x21, 0 - .dw 0xa340, 0xc80e, 0xa37f, 0xc80e, 0x21, 0 - .dw 0xa3c0, 0xc80e, 0xa3ff, 0xc80e, 0x21, 0 - .dw 0xa440, 0xc80e, 0xa47f, 0xc80e, 0x21, 0 - .dw 0xa4c0, 0xc80e, 0xa4ff, 0xc80e, 0x21, 0 - .dw 0xa540, 0xc80e, 0xa57f, 0xc80e, 0x21, 0 - .dw 0xa5c0, 0xc80e, 0xa5ff, 0xc80e, 0x21, 0 - .dw 0xa640, 0xc80e, 0xa67f, 0xc80e, 0x21, 0 - .dw 0xa6c0, 0xc80e, 0xa6ff, 0xc80e, 0x21, 0 - .dw 0xa740, 0xc80e, 0xa77f, 0xc80e, 0x21, 0 - .dw 0xa7c0, 0xc80e, 0xa7ff, 0xc80e, 0x21, 0 - .dw 0xa840, 0xc80e, 0xa87f, 0xc80e, 0x21, 0 - .dw 0xa8c0, 0xc80e, 0xa8ff, 0xc80e, 0x21, 0 - .dw 0xa940, 0xc80e, 0xa97f, 0xc80e, 0x21, 0 - .dw 0xa9c0, 0xc80e, 0xa9ff, 0xc80e, 0x21, 0 - .dw 0xaa40, 0xc80e, 0xaa7f, 0xc80e, 0x21, 0 - .dw 0xaac0, 0xc80e, 0xaaff, 0xc80e, 0x21, 0 - .dw 0xab40, 0xc80e, 0xab7f, 0xc80e, 0x21, 0 - .dw 0xabc0, 0xc80e, 0xabff, 0xc80e, 0x21, 0 - .dw 0xac40, 0xc80e, 0xac7f, 0xc80e, 0x21, 0 - .dw 0xacc0, 0xc80e, 0xacff, 0xc80e, 0x21, 0 - .dw 0xad40, 0xc80e, 0xad7f, 0xc80e, 0x21, 0 - .dw 0xadc0, 0xc80e, 0xadff, 0xc80e, 0x21, 0 - .dw 0xae40, 0xc80e, 0xae7f, 0xc80e, 0x21, 0 - .dw 0xaec0, 0xc80e, 0xaeff, 0xc80e, 0x21, 0 - .dw 0xaf40, 0xc80e, 0xaf7f, 0xc80e, 0x21, 0 - .dw 0xafc0, 0xc80e, 0xafff, 0xc80e, 0x21, 0 - .dw 0xb040, 0xc80e, 0xb07f, 0xc80e, 0x21, 0 - .dw 0xb0c0, 0xc80e, 0xb0ff, 0xc80e, 0x21, 0 - .dw 0xb140, 0xc80e, 0xb17f, 0xc80e, 0x21, 0 - .dw 0xb1c0, 0xc80e, 0xb1ff, 0xc80e, 0x21, 0 - .dw 0xb240, 0xc80e, 0xb27f, 0xc80e, 0x21, 0 - .dw 0xb2c0, 0xc80e, 0xb2ff, 0xc80e, 0x21, 0 - .dw 0xb340, 0xc80e, 0xb37f, 0xc80e, 0x21, 0 - .dw 0xb3c0, 0xc80e, 0xb3ff, 0xc80e, 0x21, 0 - .dw 0xb440, 0xc80e, 0xb47f, 0xc80e, 0x21, 0 - .dw 0xb4c0, 0xc80e, 0xb4ff, 0xc80e, 0x21, 0 - .dw 0xb540, 0xc80e, 0xb57f, 0xc80e, 0x21, 0 - .dw 0xb5c0, 0xc80e, 0xb5ff, 0xc80e, 0x21, 0 - .dw 0xb640, 0xc80e, 0xb67f, 0xc80e, 0x21, 0 - .dw 0xb6c0, 0xc80e, 0xb6ff, 0xc80e, 0x21, 0 - .dw 0xb740, 0xc80e, 0xb77f, 0xc80e, 0x21, 0 - .dw 0xb7c0, 0xc80e, 0xb7ff, 0xc80e, 0x21, 0 - .dw 0xb840, 0xc80e, 0xb87f, 0xc80e, 0x21, 0 - .dw 0xb8c0, 0xc80e, 0xb8ff, 0xc80e, 0x21, 0 - .dw 0xb940, 0xc80e, 0xb97f, 0xc80e, 0x21, 0 - .dw 0xb9c0, 0xc80e, 0xbfff, 0xc80e, 0x21, 0 - .dw 0xc040, 0xc80e, 0xc07f, 0xc80e, 0x21, 0 - .dw 0xc0c0, 0xc80e, 0xc0ff, 0xc80e, 0x21, 0 - .dw 0xc140, 0xc80e, 0xc17f, 0xc80e, 0x21, 0 - .dw 0xc1c0, 0xc80e, 0xc1ff, 0xc80e, 0x21, 0 - .dw 0xc240, 0xc80e, 0xc27f, 0xc80e, 0x21, 0 - .dw 0xc2c0, 0xc80e, 0xc2ff, 0xc80e, 0x21, 0 - .dw 0xc340, 0xc80e, 0xc37f, 0xc80e, 0x21, 0 - .dw 0xc3c0, 0xc80e, 0xc3ff, 0xc80e, 0x21, 0 - .dw 0xc440, 0xc80e, 0xc47f, 0xc80e, 0x21, 0 - .dw 0xc4c0, 0xc80e, 0xc4ff, 0xc80e, 0x21, 0 - .dw 0xc540, 0xc80e, 0xc57f, 0xc80e, 0x21, 0 - .dw 0xc5c0, 0xc80e, 0xc5ff, 0xc80e, 0x21, 0 - .dw 0xc640, 0xc80e, 0xc67f, 0xc80e, 0x21, 0 - .dw 0xc6c0, 0xc80e, 0xc6ff, 0xc80e, 0x21, 0 - .dw 0xc740, 0xc80e, 0xc77f, 0xc80e, 0x21, 0 - .dw 0xc7c0, 0xc80e, 0xc7ff, 0xc80e, 0x21, 0 - .dw 0xc840, 0xc80e, 0xc87f, 0xc80e, 0x21, 0 - .dw 0xc8c0, 0xc80e, 0xc8ff, 0xc80e, 0x21, 0 - .dw 0xc940, 0xc80e, 0xc97f, 0xc80e, 0x21, 0 - .dw 0xc9c0, 0xc80e, 0xc9ff, 0xc80e, 0x21, 0 - .dw 0xca40, 0xc80e, 0xca7f, 0xc80e, 0x21, 0 - .dw 0xcac0, 0xc80e, 0xcaff, 0xc80e, 0x21, 0 - .dw 0xcb40, 0xc80e, 0xcb7f, 0xc80e, 0x21, 0 - .dw 0xcbc0, 0xc80e, 0xcbff, 0xc80e, 0x21, 0 - .dw 0xcc40, 0xc80e, 0xcc7f, 0xc80e, 0x21, 0 - .dw 0xccc0, 0xc80e, 0xccff, 0xc80e, 0x21, 0 - .dw 0xcd40, 0xc80e, 0xcd7f, 0xc80e, 0x21, 0 - .dw 0xcdc0, 0xc80e, 0xcdff, 0xc80e, 0x21, 0 - .dw 0xce40, 0xc80e, 0xce7f, 0xc80e, 0x21, 0 - .dw 0xcec0, 0xc80e, 0xceff, 0xc80e, 0x21, 0 - .dw 0xcf40, 0xc80e, 0xcf7f, 0xc80e, 0x21, 0 - .dw 0xcfc0, 0xc80e, 0xcfff, 0xc80e, 0x21, 0 - .dw 0xd040, 0xc80e, 0xd07f, 0xc80e, 0x21, 0 - .dw 0xd0c0, 0xc80e, 0xd0ff, 0xc80e, 0x21, 0 - .dw 0xd140, 0xc80e, 0xd17f, 0xc80e, 0x21, 0 - .dw 0xd1c0, 0xc80e, 0xd1ff, 0xc80e, 0x21, 0 - .dw 0xd240, 0xc80e, 0xd27f, 0xc80e, 0x21, 0 - .dw 0xd2c0, 0xc80e, 0xd2ff, 0xc80e, 0x21, 0 - .dw 0xd340, 0xc80e, 0xd37f, 0xc80e, 0x21, 0 - .dw 0xd3c0, 0xc80e, 0xd3ff, 0xc80e, 0x21, 0 - .dw 0xd440, 0xc80e, 0xd47f, 0xc80e, 0x21, 0 - .dw 0xd4c0, 0xc80e, 0xd4ff, 0xc80e, 0x21, 0 - .dw 0xd540, 0xc80e, 0xd57f, 0xc80e, 0x21, 0 - .dw 0xd5c0, 0xc80e, 0xd5ff, 0xc80e, 0x21, 0 - .dw 0xd640, 0xc80e, 0xd67f, 0xc80e, 0x21, 0 - .dw 0xd6c0, 0xc80e, 0xd6ff, 0xc80e, 0x21, 0 - .dw 0xd740, 0xc80e, 0xd77f, 0xc80e, 0x21, 0 - .dw 0xd7c0, 0xc80e, 0xd7ff, 0xc80e, 0x21, 0 - .dw 0xd840, 0xc80e, 0xd87f, 0xc80e, 0x21, 0 - .dw 0xd8c0, 0xc80e, 0xd8ff, 0xc80e, 0x21, 0 - .dw 0xd940, 0xc80e, 0xd97f, 0xc80e, 0x21, 0 - .dw 0xd9c0, 0xc80e, 0xdfff, 0xc80e, 0x21, 0 - .dw 0xe040, 0xc80e, 0xe07f, 0xc80e, 0x21, 0 - .dw 0xe0c0, 0xc80e, 0xe0ff, 0xc80e, 0x21, 0 - .dw 0xe140, 0xc80e, 0xe17f, 0xc80e, 0x21, 0 - .dw 0xe1c0, 0xc80e, 0xe1ff, 0xc80e, 0x21, 0 - .dw 0xe240, 0xc80e, 0xe27f, 0xc80e, 0x21, 0 - .dw 0xe2c0, 0xc80e, 0xe2ff, 0xc80e, 0x21, 0 - .dw 0xe340, 0xc80e, 0xe37f, 0xc80e, 0x21, 0 - .dw 0xe3c0, 0xc80e, 0xe3ff, 0xc80e, 0x21, 0 - .dw 0xe440, 0xc80e, 0xe47f, 0xc80e, 0x21, 0 - .dw 0xe4c0, 0xc80e, 0xe4ff, 0xc80e, 0x21, 0 - .dw 0xe540, 0xc80e, 0xe57f, 0xc80e, 0x21, 0 - .dw 0xe5c0, 0xc80e, 0xe5ff, 0xc80e, 0x21, 0 - .dw 0xe640, 0xc80e, 0xe67f, 0xc80e, 0x21, 0 - .dw 0xe6c0, 0xc80e, 0xe6ff, 0xc80e, 0x21, 0 - .dw 0xe740, 0xc80e, 0xe77f, 0xc80e, 0x21, 0 - .dw 0xe7c0, 0xc80e, 0xe7ff, 0xc80e, 0x21, 0 - .dw 0xe840, 0xc80e, 0xe87f, 0xc80e, 0x21, 0 - .dw 0xe8c0, 0xc80e, 0xe8ff, 0xc80e, 0x21, 0 - .dw 0xe940, 0xc80e, 0xe97f, 0xc80e, 0x21, 0 - .dw 0xe9c0, 0xc80e, 0xe9ff, 0xc80e, 0x21, 0 - .dw 0xea40, 0xc80e, 0xea7f, 0xc80e, 0x21, 0 - .dw 0xeac0, 0xc80e, 0xeaff, 0xc80e, 0x21, 0 - .dw 0xeb40, 0xc80e, 0xeb7f, 0xc80e, 0x21, 0 - .dw 0xebc0, 0xc80e, 0xebff, 0xc80e, 0x21, 0 - .dw 0xec40, 0xc80e, 0xec7f, 0xc80e, 0x21, 0 - .dw 0xecc0, 0xc80e, 0xecff, 0xc80e, 0x21, 0 - .dw 0xed40, 0xc80e, 0xed7f, 0xc80e, 0x21, 0 - .dw 0xedc0, 0xc80e, 0xedff, 0xc80e, 0x21, 0 - .dw 0xee40, 0xc80e, 0xee7f, 0xc80e, 0x21, 0 - .dw 0xeec0, 0xc80e, 0xeeff, 0xc80e, 0x21, 0 - .dw 0xef40, 0xc80e, 0xef7f, 0xc80e, 0x21, 0 - .dw 0xefc0, 0xc80e, 0xefff, 0xc80e, 0x21, 0 - .dw 0xf040, 0xc80e, 0xf07f, 0xc80e, 0x21, 0 - .dw 0xf0c0, 0xc80e, 0xf0ff, 0xc80e, 0x21, 0 - .dw 0xf140, 0xc80e, 0xf17f, 0xc80e, 0x21, 0 - .dw 0xf1c0, 0xc80e, 0xf1ff, 0xc80e, 0x21, 0 - .dw 0xf240, 0xc80e, 0xf27f, 0xc80e, 0x21, 0 - .dw 0xf2c0, 0xc80e, 0xf2ff, 0xc80e, 0x21, 0 - .dw 0xf340, 0xc80e, 0xf37f, 0xc80e, 0x21, 0 - .dw 0xf3c0, 0xc80e, 0xf3ff, 0xc80e, 0x21, 0 - .dw 0xf440, 0xc80e, 0xf47f, 0xc80e, 0x21, 0 - .dw 0xf4c0, 0xc80e, 0xf4ff, 0xc80e, 0x21, 0 - .dw 0xf540, 0xc80e, 0xf57f, 0xc80e, 0x21, 0 - .dw 0xf5c0, 0xc80e, 0xf5ff, 0xc80e, 0x21, 0 - .dw 0xf640, 0xc80e, 0xf67f, 0xc80e, 0x21, 0 - .dw 0xf6c0, 0xc80e, 0xf6ff, 0xc80e, 0x21, 0 - .dw 0xf740, 0xc80e, 0xf77f, 0xc80e, 0x21, 0 - .dw 0xf7c0, 0xc80e, 0xf7ff, 0xc80e, 0x21, 0 - .dw 0xf840, 0xc80e, 0xf87f, 0xc80e, 0x21, 0 - .dw 0xf8c0, 0xc80e, 0xf8ff, 0xc80e, 0x21, 0 - .dw 0xf940, 0xc80e, 0xf97f, 0xc80e, 0x21, 0 - .dw 0xf9c0, 0xc80e, 0xffff, 0xc80e, 0x21, 0 - .dw 0x0040, 0xc80f, 0x007f, 0xc80f, 0x21, 0 - .dw 0x00c0, 0xc80f, 0x00ff, 0xc80f, 0x21, 0 - .dw 0x0140, 0xc80f, 0x017f, 0xc80f, 0x21, 0 - .dw 0x01c0, 0xc80f, 0x01ff, 0xc80f, 0x21, 0 - .dw 0x0240, 0xc80f, 0x027f, 0xc80f, 0x21, 0 - .dw 0x02c0, 0xc80f, 0x02ff, 0xc80f, 0x21, 0 - .dw 0x0340, 0xc80f, 0x037f, 0xc80f, 0x21, 0 - .dw 0x03c0, 0xc80f, 0x03ff, 0xc80f, 0x21, 0 - .dw 0x0440, 0xc80f, 0x047f, 0xc80f, 0x21, 0 - .dw 0x04c0, 0xc80f, 0x04ff, 0xc80f, 0x21, 0 - .dw 0x0540, 0xc80f, 0x057f, 0xc80f, 0x21, 0 - .dw 0x05c0, 0xc80f, 0x05ff, 0xc80f, 0x21, 0 - .dw 0x0640, 0xc80f, 0x067f, 0xc80f, 0x21, 0 - .dw 0x06c0, 0xc80f, 0x06ff, 0xc80f, 0x21, 0 - .dw 0x0740, 0xc80f, 0x077f, 0xc80f, 0x21, 0 - .dw 0x07c0, 0xc80f, 0x07ff, 0xc80f, 0x21, 0 - .dw 0x0840, 0xc80f, 0x087f, 0xc80f, 0x21, 0 - .dw 0x08c0, 0xc80f, 0x08ff, 0xc80f, 0x21, 0 - .dw 0x0940, 0xc80f, 0x097f, 0xc80f, 0x21, 0 - .dw 0x09c0, 0xc80f, 0x09ff, 0xc80f, 0x21, 0 - .dw 0x0a40, 0xc80f, 0x0a7f, 0xc80f, 0x21, 0 - .dw 0x0ac0, 0xc80f, 0x0aff, 0xc80f, 0x21, 0 - .dw 0x0b40, 0xc80f, 0x0b7f, 0xc80f, 0x21, 0 - .dw 0x0bc0, 0xc80f, 0x0bff, 0xc80f, 0x21, 0 - .dw 0x0c40, 0xc80f, 0x0c7f, 0xc80f, 0x21, 0 - .dw 0x0cc0, 0xc80f, 0x0cff, 0xc80f, 0x21, 0 - .dw 0x0d40, 0xc80f, 0x0d7f, 0xc80f, 0x21, 0 - .dw 0x0dc0, 0xc80f, 0x0dff, 0xc80f, 0x21, 0 - .dw 0x0e40, 0xc80f, 0x0e7f, 0xc80f, 0x21, 0 - .dw 0x0ec0, 0xc80f, 0x0eff, 0xc80f, 0x21, 0 - .dw 0x0f40, 0xc80f, 0x0f7f, 0xc80f, 0x21, 0 - .dw 0x0fc0, 0xc80f, 0x0fff, 0xc80f, 0x21, 0 - .dw 0x1040, 0xc80f, 0x107f, 0xc80f, 0x21, 0 - .dw 0x10c0, 0xc80f, 0x10ff, 0xc80f, 0x21, 0 - .dw 0x1140, 0xc80f, 0x117f, 0xc80f, 0x21, 0 - .dw 0x11c0, 0xc80f, 0x11ff, 0xc80f, 0x21, 0 - .dw 0x1240, 0xc80f, 0x127f, 0xc80f, 0x21, 0 - .dw 0x12c0, 0xc80f, 0x12ff, 0xc80f, 0x21, 0 - .dw 0x1340, 0xc80f, 0x137f, 0xc80f, 0x21, 0 - .dw 0x13c0, 0xc80f, 0x13ff, 0xc80f, 0x21, 0 - .dw 0x1440, 0xc80f, 0x147f, 0xc80f, 0x21, 0 - .dw 0x14c0, 0xc80f, 0x14ff, 0xc80f, 0x21, 0 - .dw 0x1540, 0xc80f, 0x157f, 0xc80f, 0x21, 0 - .dw 0x15c0, 0xc80f, 0x15ff, 0xc80f, 0x21, 0 - .dw 0x1640, 0xc80f, 0x167f, 0xc80f, 0x21, 0 - .dw 0x16c0, 0xc80f, 0x16ff, 0xc80f, 0x21, 0 - .dw 0x1740, 0xc80f, 0x177f, 0xc80f, 0x21, 0 - .dw 0x17c0, 0xc80f, 0x17ff, 0xc80f, 0x21, 0 - .dw 0x1840, 0xc80f, 0x187f, 0xc80f, 0x21, 0 - .dw 0x18c0, 0xc80f, 0x18ff, 0xc80f, 0x21, 0 - .dw 0x1940, 0xc80f, 0x197f, 0xc80f, 0x21, 0 - .dw 0x19c0, 0xc80f, 0x1fff, 0xc80f, 0x21, 0 - .dw 0x2040, 0xc80f, 0x207f, 0xc80f, 0x21, 0 - .dw 0x20c0, 0xc80f, 0x20ff, 0xc80f, 0x21, 0 - .dw 0x2140, 0xc80f, 0x217f, 0xc80f, 0x21, 0 - .dw 0x21c0, 0xc80f, 0x21ff, 0xc80f, 0x21, 0 - .dw 0x2240, 0xc80f, 0x227f, 0xc80f, 0x21, 0 - .dw 0x22c0, 0xc80f, 0x22ff, 0xc80f, 0x21, 0 - .dw 0x2340, 0xc80f, 0x237f, 0xc80f, 0x21, 0 - .dw 0x23c0, 0xc80f, 0x23ff, 0xc80f, 0x21, 0 - .dw 0x2440, 0xc80f, 0x247f, 0xc80f, 0x21, 0 - .dw 0x24c0, 0xc80f, 0x24ff, 0xc80f, 0x21, 0 - .dw 0x2540, 0xc80f, 0x257f, 0xc80f, 0x21, 0 - .dw 0x25c0, 0xc80f, 0x25ff, 0xc80f, 0x21, 0 - .dw 0x2640, 0xc80f, 0x267f, 0xc80f, 0x21, 0 - .dw 0x26c0, 0xc80f, 0x26ff, 0xc80f, 0x21, 0 - .dw 0x2740, 0xc80f, 0x277f, 0xc80f, 0x21, 0 - .dw 0x27c0, 0xc80f, 0x27ff, 0xc80f, 0x21, 0 - .dw 0x2840, 0xc80f, 0x287f, 0xc80f, 0x21, 0 - .dw 0x28c0, 0xc80f, 0x28ff, 0xc80f, 0x21, 0 - .dw 0x2940, 0xc80f, 0x297f, 0xc80f, 0x21, 0 - .dw 0x29c0, 0xc80f, 0x29ff, 0xc80f, 0x21, 0 - .dw 0x2a40, 0xc80f, 0x2a7f, 0xc80f, 0x21, 0 - .dw 0x2ac0, 0xc80f, 0x2aff, 0xc80f, 0x21, 0 - .dw 0x2b40, 0xc80f, 0x2b7f, 0xc80f, 0x21, 0 - .dw 0x2bc0, 0xc80f, 0x2bff, 0xc80f, 0x21, 0 - .dw 0x2c40, 0xc80f, 0x2c7f, 0xc80f, 0x21, 0 - .dw 0x2cc0, 0xc80f, 0x2cff, 0xc80f, 0x21, 0 - .dw 0x2d40, 0xc80f, 0x2d7f, 0xc80f, 0x21, 0 - .dw 0x2dc0, 0xc80f, 0x2dff, 0xc80f, 0x21, 0 - .dw 0x2e40, 0xc80f, 0x2e7f, 0xc80f, 0x21, 0 - .dw 0x2ec0, 0xc80f, 0x2eff, 0xc80f, 0x21, 0 - .dw 0x2f40, 0xc80f, 0x2f7f, 0xc80f, 0x21, 0 - .dw 0x2fc0, 0xc80f, 0x2fff, 0xc80f, 0x21, 0 - .dw 0x3040, 0xc80f, 0x307f, 0xc80f, 0x21, 0 - .dw 0x30c0, 0xc80f, 0x30ff, 0xc80f, 0x21, 0 - .dw 0x3140, 0xc80f, 0x317f, 0xc80f, 0x21, 0 - .dw 0x31c0, 0xc80f, 0x31ff, 0xc80f, 0x21, 0 - .dw 0x3240, 0xc80f, 0x327f, 0xc80f, 0x21, 0 - .dw 0x32c0, 0xc80f, 0x32ff, 0xc80f, 0x21, 0 - .dw 0x3340, 0xc80f, 0x337f, 0xc80f, 0x21, 0 - .dw 0x33c0, 0xc80f, 0x33ff, 0xc80f, 0x21, 0 - .dw 0x3440, 0xc80f, 0x347f, 0xc80f, 0x21, 0 - .dw 0x34c0, 0xc80f, 0x34ff, 0xc80f, 0x21, 0 - .dw 0x3540, 0xc80f, 0x357f, 0xc80f, 0x21, 0 - .dw 0x35c0, 0xc80f, 0x35ff, 0xc80f, 0x21, 0 - .dw 0x3640, 0xc80f, 0x367f, 0xc80f, 0x21, 0 - .dw 0x36c0, 0xc80f, 0x36ff, 0xc80f, 0x21, 0 - .dw 0x3740, 0xc80f, 0x377f, 0xc80f, 0x21, 0 - .dw 0x37c0, 0xc80f, 0x37ff, 0xc80f, 0x21, 0 - .dw 0x3840, 0xc80f, 0x387f, 0xc80f, 0x21, 0 - .dw 0x38c0, 0xc80f, 0x38ff, 0xc80f, 0x21, 0 - .dw 0x3940, 0xc80f, 0x397f, 0xc80f, 0x21, 0 - .dw 0x39c0, 0xc80f, 0xffff, 0xc80f, 0x21, 0 - .dw 0x1a00, 0xc810, 0x1fff, 0xc810, 0x21, 0 - .dw 0x3a00, 0xc810, 0x3fff, 0xc810, 0x21, 0 - .dw 0x5a00, 0xc810, 0x5fff, 0xc810, 0x21, 0 - .dw 0x7a00, 0xc810, 0x7fff, 0xc810, 0x21, 0 - .dw 0x9a00, 0xc810, 0x9fff, 0xc810, 0x21, 0 - .dw 0xba00, 0xc810, 0xbfff, 0xc810, 0x21, 0 - .dw 0xda00, 0xc810, 0xdfff, 0xc810, 0x21, 0 - .dw 0xfa00, 0xc810, 0xffff, 0xc810, 0x21, 0 - .dw 0x1a00, 0xc811, 0x1fff, 0xc811, 0x21, 0 - .dw 0x3a00, 0xc811, 0x3fff, 0xc811, 0x21, 0 - .dw 0x5a00, 0xc811, 0x5fff, 0xc811, 0x21, 0 - .dw 0x7a00, 0xc811, 0x7fff, 0xc811, 0x21, 0 - .dw 0x9a00, 0xc811, 0x9fff, 0xc811, 0x21, 0 - .dw 0xba00, 0xc811, 0xbfff, 0xc811, 0x21, 0 - .dw 0xda00, 0xc811, 0xdfff, 0xc811, 0x21, 0 - .dw 0xfa00, 0xc811, 0xffff, 0xc811, 0x21, 0 - .dw 0x1a00, 0xc812, 0x1fff, 0xc812, 0x21, 0 - .dw 0x3a00, 0xc812, 0x3fff, 0xc812, 0x21, 0 - .dw 0x5a00, 0xc812, 0x5fff, 0xc812, 0x21, 0 - .dw 0x7a00, 0xc812, 0x7fff, 0xc812, 0x21, 0 - .dw 0x9a00, 0xc812, 0x9fff, 0xc812, 0x21, 0 - .dw 0xba00, 0xc812, 0xbfff, 0xc812, 0x21, 0 - .dw 0xda00, 0xc812, 0xdfff, 0xc812, 0x21, 0 - .dw 0xfa00, 0xc812, 0xffff, 0xc813, 0x21, 0 - .dw 0x1a00, 0xc814, 0x1fff, 0xc814, 0x21, 0 - .dw 0x3a00, 0xc814, 0x3fff, 0xc814, 0x21, 0 - .dw 0x5a00, 0xc814, 0x5fff, 0xc814, 0x21, 0 - .dw 0x7a00, 0xc814, 0x7fff, 0xc814, 0x21, 0 - .dw 0x9a00, 0xc814, 0x9fff, 0xc814, 0x21, 0 - .dw 0xba00, 0xc814, 0xbfff, 0xc814, 0x21, 0 - .dw 0xda00, 0xc814, 0xdfff, 0xc814, 0x21, 0 - .dw 0xfa00, 0xc814, 0xffff, 0xc814, 0x21, 0 - .dw 0x1a00, 0xc815, 0x1fff, 0xc815, 0x21, 0 - .dw 0x3a00, 0xc815, 0x3fff, 0xc815, 0x21, 0 - .dw 0x5a00, 0xc815, 0x5fff, 0xc815, 0x21, 0 - .dw 0x7a00, 0xc815, 0x7fff, 0xc815, 0x21, 0 - .dw 0x9a00, 0xc815, 0x9fff, 0xc815, 0x21, 0 - .dw 0xba00, 0xc815, 0xbfff, 0xc815, 0x21, 0 - .dw 0xda00, 0xc815, 0xdfff, 0xc815, 0x21, 0 - .dw 0xfa00, 0xc815, 0xffff, 0xc815, 0x21, 0 - .dw 0x1a00, 0xc816, 0x1fff, 0xc816, 0x21, 0 - .dw 0x3a00, 0xc816, 0x3fff, 0xc816, 0x21, 0 - .dw 0x5a00, 0xc816, 0x5fff, 0xc816, 0x21, 0 - .dw 0x7a00, 0xc816, 0x7fff, 0xc816, 0x21, 0 - .dw 0x9a00, 0xc816, 0x9fff, 0xc816, 0x21, 0 - .dw 0xba00, 0xc816, 0xbfff, 0xc816, 0x21, 0 - .dw 0xda00, 0xc816, 0xdfff, 0xc816, 0x21, 0 - .dw 0xfa00, 0xc816, 0xffff, 0xc816, 0x21, 0 - .dw 0x1a00, 0xc817, 0x1fff, 0xc817, 0x21, 0 - .dw 0x3a00, 0xc817, 0x1fff, 0xc818, 0x21, 0 - .dw 0x2040, 0xc818, 0x207f, 0xc818, 0x21, 0 - .dw 0x20c0, 0xc818, 0x20ff, 0xc818, 0x21, 0 - .dw 0x2140, 0xc818, 0x217f, 0xc818, 0x21, 0 - .dw 0x21c0, 0xc818, 0x21ff, 0xc818, 0x21, 0 - .dw 0x2240, 0xc818, 0x227f, 0xc818, 0x21, 0 - .dw 0x22c0, 0xc818, 0x22ff, 0xc818, 0x21, 0 - .dw 0x2340, 0xc818, 0x237f, 0xc818, 0x21, 0 - .dw 0x23c0, 0xc818, 0x23ff, 0xc818, 0x21, 0 - .dw 0x2440, 0xc818, 0x247f, 0xc818, 0x21, 0 - .dw 0x24c0, 0xc818, 0x24ff, 0xc818, 0x21, 0 - .dw 0x2540, 0xc818, 0x257f, 0xc818, 0x21, 0 - .dw 0x25c0, 0xc818, 0x25ff, 0xc818, 0x21, 0 - .dw 0x2640, 0xc818, 0x267f, 0xc818, 0x21, 0 - .dw 0x26c0, 0xc818, 0x26ff, 0xc818, 0x21, 0 - .dw 0x2740, 0xc818, 0x277f, 0xc818, 0x21, 0 - .dw 0x27c0, 0xc818, 0x27ff, 0xc818, 0x21, 0 - .dw 0x2840, 0xc818, 0x287f, 0xc818, 0x21, 0 - .dw 0x28c0, 0xc818, 0x28ff, 0xc818, 0x21, 0 - .dw 0x2940, 0xc818, 0x297f, 0xc818, 0x21, 0 - .dw 0x29c0, 0xc818, 0x29ff, 0xc818, 0x21, 0 - .dw 0x2a40, 0xc818, 0x2a7f, 0xc818, 0x21, 0 - .dw 0x2ac0, 0xc818, 0x2aff, 0xc818, 0x21, 0 - .dw 0x2b40, 0xc818, 0x2b7f, 0xc818, 0x21, 0 - .dw 0x2bc0, 0xc818, 0x2bff, 0xc818, 0x21, 0 - .dw 0x2c40, 0xc818, 0x2c7f, 0xc818, 0x21, 0 - .dw 0x2cc0, 0xc818, 0x2cff, 0xc818, 0x21, 0 - .dw 0x2d40, 0xc818, 0x2d7f, 0xc818, 0x21, 0 - .dw 0x2dc0, 0xc818, 0x2dff, 0xc818, 0x21, 0 - .dw 0x2e40, 0xc818, 0x2e7f, 0xc818, 0x21, 0 - .dw 0x2ec0, 0xc818, 0x2eff, 0xc818, 0x21, 0 - .dw 0x2f40, 0xc818, 0x2f7f, 0xc818, 0x21, 0 - .dw 0x2fc0, 0xc818, 0x2fff, 0xc818, 0x21, 0 - .dw 0x3040, 0xc818, 0x307f, 0xc818, 0x21, 0 - .dw 0x30c0, 0xc818, 0x30ff, 0xc818, 0x21, 0 - .dw 0x3140, 0xc818, 0x317f, 0xc818, 0x21, 0 - .dw 0x31c0, 0xc818, 0x31ff, 0xc818, 0x21, 0 - .dw 0x3240, 0xc818, 0x327f, 0xc818, 0x21, 0 - .dw 0x32c0, 0xc818, 0x32ff, 0xc818, 0x21, 0 - .dw 0x3340, 0xc818, 0x337f, 0xc818, 0x21, 0 - .dw 0x33c0, 0xc818, 0x33ff, 0xc818, 0x21, 0 - .dw 0x3440, 0xc818, 0x347f, 0xc818, 0x21, 0 - .dw 0x34c0, 0xc818, 0x34ff, 0xc818, 0x21, 0 - .dw 0x3540, 0xc818, 0x357f, 0xc818, 0x21, 0 - .dw 0x35c0, 0xc818, 0x35ff, 0xc818, 0x21, 0 - .dw 0x3640, 0xc818, 0x367f, 0xc818, 0x21, 0 - .dw 0x36c0, 0xc818, 0x36ff, 0xc818, 0x21, 0 - .dw 0x3740, 0xc818, 0x377f, 0xc818, 0x21, 0 - .dw 0x37c0, 0xc818, 0x37ff, 0xc818, 0x21, 0 - .dw 0x3840, 0xc818, 0x387f, 0xc818, 0x21, 0 - .dw 0x38c0, 0xc818, 0x38ff, 0xc818, 0x21, 0 - .dw 0x3940, 0xc818, 0x397f, 0xc818, 0x21, 0 - .dw 0x39c0, 0xc818, 0x5fff, 0xc818, 0x21, 0 - .dw 0x6040, 0xc818, 0x607f, 0xc818, 0x21, 0 - .dw 0x60c0, 0xc818, 0x60ff, 0xc818, 0x21, 0 - .dw 0x6140, 0xc818, 0x617f, 0xc818, 0x21, 0 - .dw 0x61c0, 0xc818, 0x61ff, 0xc818, 0x21, 0 - .dw 0x6240, 0xc818, 0x627f, 0xc818, 0x21, 0 - .dw 0x62c0, 0xc818, 0x62ff, 0xc818, 0x21, 0 - .dw 0x6340, 0xc818, 0x637f, 0xc818, 0x21, 0 - .dw 0x63c0, 0xc818, 0x63ff, 0xc818, 0x21, 0 - .dw 0x6440, 0xc818, 0x647f, 0xc818, 0x21, 0 - .dw 0x64c0, 0xc818, 0x64ff, 0xc818, 0x21, 0 - .dw 0x6540, 0xc818, 0x657f, 0xc818, 0x21, 0 - .dw 0x65c0, 0xc818, 0x65ff, 0xc818, 0x21, 0 - .dw 0x6640, 0xc818, 0x667f, 0xc818, 0x21, 0 - .dw 0x66c0, 0xc818, 0x66ff, 0xc818, 0x21, 0 - .dw 0x6740, 0xc818, 0x677f, 0xc818, 0x21, 0 - .dw 0x67c0, 0xc818, 0x67ff, 0xc818, 0x21, 0 - .dw 0x6840, 0xc818, 0x687f, 0xc818, 0x21, 0 - .dw 0x68c0, 0xc818, 0x68ff, 0xc818, 0x21, 0 - .dw 0x6940, 0xc818, 0x697f, 0xc818, 0x21, 0 - .dw 0x69c0, 0xc818, 0x69ff, 0xc818, 0x21, 0 - .dw 0x6a40, 0xc818, 0x6a7f, 0xc818, 0x21, 0 - .dw 0x6ac0, 0xc818, 0x6aff, 0xc818, 0x21, 0 - .dw 0x6b40, 0xc818, 0x6b7f, 0xc818, 0x21, 0 - .dw 0x6bc0, 0xc818, 0x6bff, 0xc818, 0x21, 0 - .dw 0x6c40, 0xc818, 0x6c7f, 0xc818, 0x21, 0 - .dw 0x6cc0, 0xc818, 0x6cff, 0xc818, 0x21, 0 - .dw 0x6d40, 0xc818, 0x6d7f, 0xc818, 0x21, 0 - .dw 0x6dc0, 0xc818, 0x6dff, 0xc818, 0x21, 0 - .dw 0x6e40, 0xc818, 0x6e7f, 0xc818, 0x21, 0 - .dw 0x6ec0, 0xc818, 0x6eff, 0xc818, 0x21, 0 - .dw 0x6f40, 0xc818, 0x6f7f, 0xc818, 0x21, 0 - .dw 0x6fc0, 0xc818, 0x6fff, 0xc818, 0x21, 0 - .dw 0x7040, 0xc818, 0x707f, 0xc818, 0x21, 0 - .dw 0x70c0, 0xc818, 0x70ff, 0xc818, 0x21, 0 - .dw 0x7140, 0xc818, 0x717f, 0xc818, 0x21, 0 - .dw 0x71c0, 0xc818, 0x71ff, 0xc818, 0x21, 0 - .dw 0x7240, 0xc818, 0x727f, 0xc818, 0x21, 0 - .dw 0x72c0, 0xc818, 0x72ff, 0xc818, 0x21, 0 - .dw 0x7340, 0xc818, 0x737f, 0xc818, 0x21, 0 - .dw 0x73c0, 0xc818, 0x73ff, 0xc818, 0x21, 0 - .dw 0x7440, 0xc818, 0x747f, 0xc818, 0x21, 0 - .dw 0x74c0, 0xc818, 0x74ff, 0xc818, 0x21, 0 - .dw 0x7540, 0xc818, 0x757f, 0xc818, 0x21, 0 - .dw 0x75c0, 0xc818, 0x75ff, 0xc818, 0x21, 0 - .dw 0x7640, 0xc818, 0x767f, 0xc818, 0x21, 0 - .dw 0x76c0, 0xc818, 0x76ff, 0xc818, 0x21, 0 - .dw 0x7740, 0xc818, 0x777f, 0xc818, 0x21, 0 - .dw 0x77c0, 0xc818, 0x77ff, 0xc818, 0x21, 0 - .dw 0x7840, 0xc818, 0x787f, 0xc818, 0x21, 0 - .dw 0x78c0, 0xc818, 0x78ff, 0xc818, 0x21, 0 - .dw 0x7940, 0xc818, 0x797f, 0xc818, 0x21, 0 - .dw 0x79c0, 0xc818, 0x9fff, 0xc818, 0x21, 0 - .dw 0xa040, 0xc818, 0xa07f, 0xc818, 0x21, 0 - .dw 0xa0c0, 0xc818, 0xa0ff, 0xc818, 0x21, 0 - .dw 0xa140, 0xc818, 0xa17f, 0xc818, 0x21, 0 - .dw 0xa1c0, 0xc818, 0xa1ff, 0xc818, 0x21, 0 - .dw 0xa240, 0xc818, 0xa27f, 0xc818, 0x21, 0 - .dw 0xa2c0, 0xc818, 0xa2ff, 0xc818, 0x21, 0 - .dw 0xa340, 0xc818, 0xa37f, 0xc818, 0x21, 0 - .dw 0xa3c0, 0xc818, 0xa3ff, 0xc818, 0x21, 0 - .dw 0xa440, 0xc818, 0xa47f, 0xc818, 0x21, 0 - .dw 0xa4c0, 0xc818, 0xa4ff, 0xc818, 0x21, 0 - .dw 0xa540, 0xc818, 0xa57f, 0xc818, 0x21, 0 - .dw 0xa5c0, 0xc818, 0xa5ff, 0xc818, 0x21, 0 - .dw 0xa640, 0xc818, 0xa67f, 0xc818, 0x21, 0 - .dw 0xa6c0, 0xc818, 0xa6ff, 0xc818, 0x21, 0 - .dw 0xa740, 0xc818, 0xa77f, 0xc818, 0x21, 0 - .dw 0xa7c0, 0xc818, 0xa7ff, 0xc818, 0x21, 0 - .dw 0xa840, 0xc818, 0xa87f, 0xc818, 0x21, 0 - .dw 0xa8c0, 0xc818, 0xa8ff, 0xc818, 0x21, 0 - .dw 0xa940, 0xc818, 0xa97f, 0xc818, 0x21, 0 - .dw 0xa9c0, 0xc818, 0xa9ff, 0xc818, 0x21, 0 - .dw 0xaa40, 0xc818, 0xaa7f, 0xc818, 0x21, 0 - .dw 0xaac0, 0xc818, 0xaaff, 0xc818, 0x21, 0 - .dw 0xab40, 0xc818, 0xab7f, 0xc818, 0x21, 0 - .dw 0xabc0, 0xc818, 0xabff, 0xc818, 0x21, 0 - .dw 0xac40, 0xc818, 0xac7f, 0xc818, 0x21, 0 - .dw 0xacc0, 0xc818, 0xacff, 0xc818, 0x21, 0 - .dw 0xad40, 0xc818, 0xad7f, 0xc818, 0x21, 0 - .dw 0xadc0, 0xc818, 0xadff, 0xc818, 0x21, 0 - .dw 0xae40, 0xc818, 0xae7f, 0xc818, 0x21, 0 - .dw 0xaec0, 0xc818, 0xaeff, 0xc818, 0x21, 0 - .dw 0xaf40, 0xc818, 0xaf7f, 0xc818, 0x21, 0 - .dw 0xafc0, 0xc818, 0xafff, 0xc818, 0x21, 0 - .dw 0xb040, 0xc818, 0xb07f, 0xc818, 0x21, 0 - .dw 0xb0c0, 0xc818, 0xb0ff, 0xc818, 0x21, 0 - .dw 0xb140, 0xc818, 0xb17f, 0xc818, 0x21, 0 - .dw 0xb1c0, 0xc818, 0xb1ff, 0xc818, 0x21, 0 - .dw 0xb240, 0xc818, 0xb27f, 0xc818, 0x21, 0 - .dw 0xb2c0, 0xc818, 0xb2ff, 0xc818, 0x21, 0 - .dw 0xb340, 0xc818, 0xb37f, 0xc818, 0x21, 0 - .dw 0xb3c0, 0xc818, 0xb3ff, 0xc818, 0x21, 0 - .dw 0xb440, 0xc818, 0xb47f, 0xc818, 0x21, 0 - .dw 0xb4c0, 0xc818, 0xb4ff, 0xc818, 0x21, 0 - .dw 0xb540, 0xc818, 0xb57f, 0xc818, 0x21, 0 - .dw 0xb5c0, 0xc818, 0xb5ff, 0xc818, 0x21, 0 - .dw 0xb640, 0xc818, 0xb67f, 0xc818, 0x21, 0 - .dw 0xb6c0, 0xc818, 0xb6ff, 0xc818, 0x21, 0 - .dw 0xb740, 0xc818, 0xb77f, 0xc818, 0x21, 0 - .dw 0xb7c0, 0xc818, 0xb7ff, 0xc818, 0x21, 0 - .dw 0xb840, 0xc818, 0xb87f, 0xc818, 0x21, 0 - .dw 0xb8c0, 0xc818, 0xb8ff, 0xc818, 0x21, 0 - .dw 0xb940, 0xc818, 0xb97f, 0xc818, 0x21, 0 - .dw 0xb9c0, 0xc818, 0xdfff, 0xc818, 0x21, 0 - .dw 0xe040, 0xc818, 0xe07f, 0xc818, 0x21, 0 - .dw 0xe0c0, 0xc818, 0xe0ff, 0xc818, 0x21, 0 - .dw 0xe140, 0xc818, 0xe17f, 0xc818, 0x21, 0 - .dw 0xe1c0, 0xc818, 0xe1ff, 0xc818, 0x21, 0 - .dw 0xe240, 0xc818, 0xe27f, 0xc818, 0x21, 0 - .dw 0xe2c0, 0xc818, 0xe2ff, 0xc818, 0x21, 0 - .dw 0xe340, 0xc818, 0xe37f, 0xc818, 0x21, 0 - .dw 0xe3c0, 0xc818, 0xe3ff, 0xc818, 0x21, 0 - .dw 0xe440, 0xc818, 0xe47f, 0xc818, 0x21, 0 - .dw 0xe4c0, 0xc818, 0xe4ff, 0xc818, 0x21, 0 - .dw 0xe540, 0xc818, 0xe57f, 0xc818, 0x21, 0 - .dw 0xe5c0, 0xc818, 0xe5ff, 0xc818, 0x21, 0 - .dw 0xe640, 0xc818, 0xe67f, 0xc818, 0x21, 0 - .dw 0xe6c0, 0xc818, 0xe6ff, 0xc818, 0x21, 0 - .dw 0xe740, 0xc818, 0xe77f, 0xc818, 0x21, 0 - .dw 0xe7c0, 0xc818, 0xe7ff, 0xc818, 0x21, 0 - .dw 0xe840, 0xc818, 0xe87f, 0xc818, 0x21, 0 - .dw 0xe8c0, 0xc818, 0xe8ff, 0xc818, 0x21, 0 - .dw 0xe940, 0xc818, 0xe97f, 0xc818, 0x21, 0 - .dw 0xe9c0, 0xc818, 0xe9ff, 0xc818, 0x21, 0 - .dw 0xea40, 0xc818, 0xea7f, 0xc818, 0x21, 0 - .dw 0xeac0, 0xc818, 0xeaff, 0xc818, 0x21, 0 - .dw 0xeb40, 0xc818, 0xeb7f, 0xc818, 0x21, 0 - .dw 0xebc0, 0xc818, 0xebff, 0xc818, 0x21, 0 - .dw 0xec40, 0xc818, 0xec7f, 0xc818, 0x21, 0 - .dw 0xecc0, 0xc818, 0xecff, 0xc818, 0x21, 0 - .dw 0xed40, 0xc818, 0xed7f, 0xc818, 0x21, 0 - .dw 0xedc0, 0xc818, 0xedff, 0xc818, 0x21, 0 - .dw 0xee40, 0xc818, 0xee7f, 0xc818, 0x21, 0 - .dw 0xeec0, 0xc818, 0xeeff, 0xc818, 0x21, 0 - .dw 0xef40, 0xc818, 0xef7f, 0xc818, 0x21, 0 - .dw 0xefc0, 0xc818, 0xefff, 0xc818, 0x21, 0 - .dw 0xf040, 0xc818, 0xf07f, 0xc818, 0x21, 0 - .dw 0xf0c0, 0xc818, 0xf0ff, 0xc818, 0x21, 0 - .dw 0xf140, 0xc818, 0xf17f, 0xc818, 0x21, 0 - .dw 0xf1c0, 0xc818, 0xf1ff, 0xc818, 0x21, 0 - .dw 0xf240, 0xc818, 0xf27f, 0xc818, 0x21, 0 - .dw 0xf2c0, 0xc818, 0xf2ff, 0xc818, 0x21, 0 - .dw 0xf340, 0xc818, 0xf37f, 0xc818, 0x21, 0 - .dw 0xf3c0, 0xc818, 0xf3ff, 0xc818, 0x21, 0 - .dw 0xf440, 0xc818, 0xf47f, 0xc818, 0x21, 0 - .dw 0xf4c0, 0xc818, 0xf4ff, 0xc818, 0x21, 0 - .dw 0xf540, 0xc818, 0xf57f, 0xc818, 0x21, 0 - .dw 0xf5c0, 0xc818, 0xf5ff, 0xc818, 0x21, 0 - .dw 0xf640, 0xc818, 0xf67f, 0xc818, 0x21, 0 - .dw 0xf6c0, 0xc818, 0xf6ff, 0xc818, 0x21, 0 - .dw 0xf740, 0xc818, 0xf77f, 0xc818, 0x21, 0 - .dw 0xf7c0, 0xc818, 0xf7ff, 0xc818, 0x21, 0 - .dw 0xf840, 0xc818, 0xf87f, 0xc818, 0x21, 0 - .dw 0xf8c0, 0xc818, 0xf8ff, 0xc818, 0x21, 0 - .dw 0xf940, 0xc818, 0xf97f, 0xc818, 0x21, 0 - .dw 0xf9c0, 0xc818, 0x1fff, 0xc819, 0x21, 0 - .dw 0x2040, 0xc819, 0x207f, 0xc819, 0x21, 0 - .dw 0x20c0, 0xc819, 0x20ff, 0xc819, 0x21, 0 - .dw 0x2140, 0xc819, 0x217f, 0xc819, 0x21, 0 - .dw 0x21c0, 0xc819, 0x21ff, 0xc819, 0x21, 0 - .dw 0x2240, 0xc819, 0x227f, 0xc819, 0x21, 0 - .dw 0x22c0, 0xc819, 0x22ff, 0xc819, 0x21, 0 - .dw 0x2340, 0xc819, 0x237f, 0xc819, 0x21, 0 - .dw 0x23c0, 0xc819, 0x23ff, 0xc819, 0x21, 0 - .dw 0x2440, 0xc819, 0x247f, 0xc819, 0x21, 0 - .dw 0x24c0, 0xc819, 0x24ff, 0xc819, 0x21, 0 - .dw 0x2540, 0xc819, 0x257f, 0xc819, 0x21, 0 - .dw 0x25c0, 0xc819, 0x25ff, 0xc819, 0x21, 0 - .dw 0x2640, 0xc819, 0x267f, 0xc819, 0x21, 0 - .dw 0x26c0, 0xc819, 0x26ff, 0xc819, 0x21, 0 - .dw 0x2740, 0xc819, 0x277f, 0xc819, 0x21, 0 - .dw 0x27c0, 0xc819, 0x27ff, 0xc819, 0x21, 0 - .dw 0x2840, 0xc819, 0x287f, 0xc819, 0x21, 0 - .dw 0x28c0, 0xc819, 0x28ff, 0xc819, 0x21, 0 - .dw 0x2940, 0xc819, 0x297f, 0xc819, 0x21, 0 - .dw 0x29c0, 0xc819, 0x29ff, 0xc819, 0x21, 0 - .dw 0x2a40, 0xc819, 0x2a7f, 0xc819, 0x21, 0 - .dw 0x2ac0, 0xc819, 0x2aff, 0xc819, 0x21, 0 - .dw 0x2b40, 0xc819, 0x2b7f, 0xc819, 0x21, 0 - .dw 0x2bc0, 0xc819, 0x2bff, 0xc819, 0x21, 0 - .dw 0x2c40, 0xc819, 0x2c7f, 0xc819, 0x21, 0 - .dw 0x2cc0, 0xc819, 0x2cff, 0xc819, 0x21, 0 - .dw 0x2d40, 0xc819, 0x2d7f, 0xc819, 0x21, 0 - .dw 0x2dc0, 0xc819, 0x2dff, 0xc819, 0x21, 0 - .dw 0x2e40, 0xc819, 0x2e7f, 0xc819, 0x21, 0 - .dw 0x2ec0, 0xc819, 0x2eff, 0xc819, 0x21, 0 - .dw 0x2f40, 0xc819, 0x2f7f, 0xc819, 0x21, 0 - .dw 0x2fc0, 0xc819, 0x2fff, 0xc819, 0x21, 0 - .dw 0x3040, 0xc819, 0x307f, 0xc819, 0x21, 0 - .dw 0x30c0, 0xc819, 0x30ff, 0xc819, 0x21, 0 - .dw 0x3140, 0xc819, 0x317f, 0xc819, 0x21, 0 - .dw 0x31c0, 0xc819, 0x31ff, 0xc819, 0x21, 0 - .dw 0x3240, 0xc819, 0x327f, 0xc819, 0x21, 0 - .dw 0x32c0, 0xc819, 0x32ff, 0xc819, 0x21, 0 - .dw 0x3340, 0xc819, 0x337f, 0xc819, 0x21, 0 - .dw 0x33c0, 0xc819, 0x33ff, 0xc819, 0x21, 0 - .dw 0x3440, 0xc819, 0x347f, 0xc819, 0x21, 0 - .dw 0x34c0, 0xc819, 0x34ff, 0xc819, 0x21, 0 - .dw 0x3540, 0xc819, 0x357f, 0xc819, 0x21, 0 - .dw 0x35c0, 0xc819, 0x35ff, 0xc819, 0x21, 0 - .dw 0x3640, 0xc819, 0x367f, 0xc819, 0x21, 0 - .dw 0x36c0, 0xc819, 0x36ff, 0xc819, 0x21, 0 - .dw 0x3740, 0xc819, 0x377f, 0xc819, 0x21, 0 - .dw 0x37c0, 0xc819, 0x37ff, 0xc819, 0x21, 0 - .dw 0x3840, 0xc819, 0x387f, 0xc819, 0x21, 0 - .dw 0x38c0, 0xc819, 0x38ff, 0xc819, 0x21, 0 - .dw 0x3940, 0xc819, 0x397f, 0xc819, 0x21, 0 - .dw 0x39c0, 0xc819, 0x5fff, 0xc819, 0x21, 0 - .dw 0x6040, 0xc819, 0x607f, 0xc819, 0x21, 0 - .dw 0x60c0, 0xc819, 0x60ff, 0xc819, 0x21, 0 - .dw 0x6140, 0xc819, 0x617f, 0xc819, 0x21, 0 - .dw 0x61c0, 0xc819, 0x61ff, 0xc819, 0x21, 0 - .dw 0x6240, 0xc819, 0x627f, 0xc819, 0x21, 0 - .dw 0x62c0, 0xc819, 0x62ff, 0xc819, 0x21, 0 - .dw 0x6340, 0xc819, 0x637f, 0xc819, 0x21, 0 - .dw 0x63c0, 0xc819, 0x63ff, 0xc819, 0x21, 0 - .dw 0x6440, 0xc819, 0x647f, 0xc819, 0x21, 0 - .dw 0x64c0, 0xc819, 0x64ff, 0xc819, 0x21, 0 - .dw 0x6540, 0xc819, 0x657f, 0xc819, 0x21, 0 - .dw 0x65c0, 0xc819, 0x65ff, 0xc819, 0x21, 0 - .dw 0x6640, 0xc819, 0x667f, 0xc819, 0x21, 0 - .dw 0x66c0, 0xc819, 0x66ff, 0xc819, 0x21, 0 - .dw 0x6740, 0xc819, 0x677f, 0xc819, 0x21, 0 - .dw 0x67c0, 0xc819, 0x67ff, 0xc819, 0x21, 0 - .dw 0x6840, 0xc819, 0x687f, 0xc819, 0x21, 0 - .dw 0x68c0, 0xc819, 0x68ff, 0xc819, 0x21, 0 - .dw 0x6940, 0xc819, 0x697f, 0xc819, 0x21, 0 - .dw 0x69c0, 0xc819, 0x69ff, 0xc819, 0x21, 0 - .dw 0x6a40, 0xc819, 0x6a7f, 0xc819, 0x21, 0 - .dw 0x6ac0, 0xc819, 0x6aff, 0xc819, 0x21, 0 - .dw 0x6b40, 0xc819, 0x6b7f, 0xc819, 0x21, 0 - .dw 0x6bc0, 0xc819, 0x6bff, 0xc819, 0x21, 0 - .dw 0x6c40, 0xc819, 0x6c7f, 0xc819, 0x21, 0 - .dw 0x6cc0, 0xc819, 0x6cff, 0xc819, 0x21, 0 - .dw 0x6d40, 0xc819, 0x6d7f, 0xc819, 0x21, 0 - .dw 0x6dc0, 0xc819, 0x6dff, 0xc819, 0x21, 0 - .dw 0x6e40, 0xc819, 0x6e7f, 0xc819, 0x21, 0 - .dw 0x6ec0, 0xc819, 0x6eff, 0xc819, 0x21, 0 - .dw 0x6f40, 0xc819, 0x6f7f, 0xc819, 0x21, 0 - .dw 0x6fc0, 0xc819, 0x6fff, 0xc819, 0x21, 0 - .dw 0x7040, 0xc819, 0x707f, 0xc819, 0x21, 0 - .dw 0x70c0, 0xc819, 0x70ff, 0xc819, 0x21, 0 - .dw 0x7140, 0xc819, 0x717f, 0xc819, 0x21, 0 - .dw 0x71c0, 0xc819, 0x71ff, 0xc819, 0x21, 0 - .dw 0x7240, 0xc819, 0x727f, 0xc819, 0x21, 0 - .dw 0x72c0, 0xc819, 0x72ff, 0xc819, 0x21, 0 - .dw 0x7340, 0xc819, 0x737f, 0xc819, 0x21, 0 - .dw 0x73c0, 0xc819, 0x73ff, 0xc819, 0x21, 0 - .dw 0x7440, 0xc819, 0x747f, 0xc819, 0x21, 0 - .dw 0x74c0, 0xc819, 0x74ff, 0xc819, 0x21, 0 - .dw 0x7540, 0xc819, 0x757f, 0xc819, 0x21, 0 - .dw 0x75c0, 0xc819, 0x75ff, 0xc819, 0x21, 0 - .dw 0x7640, 0xc819, 0x767f, 0xc819, 0x21, 0 - .dw 0x76c0, 0xc819, 0x76ff, 0xc819, 0x21, 0 - .dw 0x7740, 0xc819, 0x777f, 0xc819, 0x21, 0 - .dw 0x77c0, 0xc819, 0x77ff, 0xc819, 0x21, 0 - .dw 0x7840, 0xc819, 0x787f, 0xc819, 0x21, 0 - .dw 0x78c0, 0xc819, 0x78ff, 0xc819, 0x21, 0 - .dw 0x7940, 0xc819, 0x797f, 0xc819, 0x21, 0 - .dw 0x79c0, 0xc819, 0x9fff, 0xc819, 0x21, 0 - .dw 0xa040, 0xc819, 0xa07f, 0xc819, 0x21, 0 - .dw 0xa0c0, 0xc819, 0xa0ff, 0xc819, 0x21, 0 - .dw 0xa140, 0xc819, 0xa17f, 0xc819, 0x21, 0 - .dw 0xa1c0, 0xc819, 0xa1ff, 0xc819, 0x21, 0 - .dw 0xa240, 0xc819, 0xa27f, 0xc819, 0x21, 0 - .dw 0xa2c0, 0xc819, 0xa2ff, 0xc819, 0x21, 0 - .dw 0xa340, 0xc819, 0xa37f, 0xc819, 0x21, 0 - .dw 0xa3c0, 0xc819, 0xa3ff, 0xc819, 0x21, 0 - .dw 0xa440, 0xc819, 0xa47f, 0xc819, 0x21, 0 - .dw 0xa4c0, 0xc819, 0xa4ff, 0xc819, 0x21, 0 - .dw 0xa540, 0xc819, 0xa57f, 0xc819, 0x21, 0 - .dw 0xa5c0, 0xc819, 0xa5ff, 0xc819, 0x21, 0 - .dw 0xa640, 0xc819, 0xa67f, 0xc819, 0x21, 0 - .dw 0xa6c0, 0xc819, 0xa6ff, 0xc819, 0x21, 0 - .dw 0xa740, 0xc819, 0xa77f, 0xc819, 0x21, 0 - .dw 0xa7c0, 0xc819, 0xa7ff, 0xc819, 0x21, 0 - .dw 0xa840, 0xc819, 0xa87f, 0xc819, 0x21, 0 - .dw 0xa8c0, 0xc819, 0xa8ff, 0xc819, 0x21, 0 - .dw 0xa940, 0xc819, 0xa97f, 0xc819, 0x21, 0 - .dw 0xa9c0, 0xc819, 0xa9ff, 0xc819, 0x21, 0 - .dw 0xaa40, 0xc819, 0xaa7f, 0xc819, 0x21, 0 - .dw 0xaac0, 0xc819, 0xaaff, 0xc819, 0x21, 0 - .dw 0xab40, 0xc819, 0xab7f, 0xc819, 0x21, 0 - .dw 0xabc0, 0xc819, 0xabff, 0xc819, 0x21, 0 - .dw 0xac40, 0xc819, 0xac7f, 0xc819, 0x21, 0 - .dw 0xacc0, 0xc819, 0xacff, 0xc819, 0x21, 0 - .dw 0xad40, 0xc819, 0xad7f, 0xc819, 0x21, 0 - .dw 0xadc0, 0xc819, 0xadff, 0xc819, 0x21, 0 - .dw 0xae40, 0xc819, 0xae7f, 0xc819, 0x21, 0 - .dw 0xaec0, 0xc819, 0xaeff, 0xc819, 0x21, 0 - .dw 0xaf40, 0xc819, 0xaf7f, 0xc819, 0x21, 0 - .dw 0xafc0, 0xc819, 0xafff, 0xc819, 0x21, 0 - .dw 0xb040, 0xc819, 0xb07f, 0xc819, 0x21, 0 - .dw 0xb0c0, 0xc819, 0xb0ff, 0xc819, 0x21, 0 - .dw 0xb140, 0xc819, 0xb17f, 0xc819, 0x21, 0 - .dw 0xb1c0, 0xc819, 0xb1ff, 0xc819, 0x21, 0 - .dw 0xb240, 0xc819, 0xb27f, 0xc819, 0x21, 0 - .dw 0xb2c0, 0xc819, 0xb2ff, 0xc819, 0x21, 0 - .dw 0xb340, 0xc819, 0xb37f, 0xc819, 0x21, 0 - .dw 0xb3c0, 0xc819, 0xb3ff, 0xc819, 0x21, 0 - .dw 0xb440, 0xc819, 0xb47f, 0xc819, 0x21, 0 - .dw 0xb4c0, 0xc819, 0xb4ff, 0xc819, 0x21, 0 - .dw 0xb540, 0xc819, 0xb57f, 0xc819, 0x21, 0 - .dw 0xb5c0, 0xc819, 0xb5ff, 0xc819, 0x21, 0 - .dw 0xb640, 0xc819, 0xb67f, 0xc819, 0x21, 0 - .dw 0xb6c0, 0xc819, 0xb6ff, 0xc819, 0x21, 0 - .dw 0xb740, 0xc819, 0xb77f, 0xc819, 0x21, 0 - .dw 0xb7c0, 0xc819, 0xb7ff, 0xc819, 0x21, 0 - .dw 0xb840, 0xc819, 0xb87f, 0xc819, 0x21, 0 - .dw 0xb8c0, 0xc819, 0xb8ff, 0xc819, 0x21, 0 - .dw 0xb940, 0xc819, 0xb97f, 0xc819, 0x21, 0 - .dw 0xb9c0, 0xc819, 0xdfff, 0xc819, 0x21, 0 - .dw 0xe040, 0xc819, 0xe07f, 0xc819, 0x21, 0 - .dw 0xe0c0, 0xc819, 0xe0ff, 0xc819, 0x21, 0 - .dw 0xe140, 0xc819, 0xe17f, 0xc819, 0x21, 0 - .dw 0xe1c0, 0xc819, 0xe1ff, 0xc819, 0x21, 0 - .dw 0xe240, 0xc819, 0xe27f, 0xc819, 0x21, 0 - .dw 0xe2c0, 0xc819, 0xe2ff, 0xc819, 0x21, 0 - .dw 0xe340, 0xc819, 0xe37f, 0xc819, 0x21, 0 - .dw 0xe3c0, 0xc819, 0xe3ff, 0xc819, 0x21, 0 - .dw 0xe440, 0xc819, 0xe47f, 0xc819, 0x21, 0 - .dw 0xe4c0, 0xc819, 0xe4ff, 0xc819, 0x21, 0 - .dw 0xe540, 0xc819, 0xe57f, 0xc819, 0x21, 0 - .dw 0xe5c0, 0xc819, 0xe5ff, 0xc819, 0x21, 0 - .dw 0xe640, 0xc819, 0xe67f, 0xc819, 0x21, 0 - .dw 0xe6c0, 0xc819, 0xe6ff, 0xc819, 0x21, 0 - .dw 0xe740, 0xc819, 0xe77f, 0xc819, 0x21, 0 - .dw 0xe7c0, 0xc819, 0xe7ff, 0xc819, 0x21, 0 - .dw 0xe840, 0xc819, 0xe87f, 0xc819, 0x21, 0 - .dw 0xe8c0, 0xc819, 0xe8ff, 0xc819, 0x21, 0 - .dw 0xe940, 0xc819, 0xe97f, 0xc819, 0x21, 0 - .dw 0xe9c0, 0xc819, 0xe9ff, 0xc819, 0x21, 0 - .dw 0xea40, 0xc819, 0xea7f, 0xc819, 0x21, 0 - .dw 0xeac0, 0xc819, 0xeaff, 0xc819, 0x21, 0 - .dw 0xeb40, 0xc819, 0xeb7f, 0xc819, 0x21, 0 - .dw 0xebc0, 0xc819, 0xebff, 0xc819, 0x21, 0 - .dw 0xec40, 0xc819, 0xec7f, 0xc819, 0x21, 0 - .dw 0xecc0, 0xc819, 0xecff, 0xc819, 0x21, 0 - .dw 0xed40, 0xc819, 0xed7f, 0xc819, 0x21, 0 - .dw 0xedc0, 0xc819, 0xedff, 0xc819, 0x21, 0 - .dw 0xee40, 0xc819, 0xee7f, 0xc819, 0x21, 0 - .dw 0xeec0, 0xc819, 0xeeff, 0xc819, 0x21, 0 - .dw 0xef40, 0xc819, 0xef7f, 0xc819, 0x21, 0 - .dw 0xefc0, 0xc819, 0xefff, 0xc819, 0x21, 0 - .dw 0xf040, 0xc819, 0xf07f, 0xc819, 0x21, 0 - .dw 0xf0c0, 0xc819, 0xf0ff, 0xc819, 0x21, 0 - .dw 0xf140, 0xc819, 0xf17f, 0xc819, 0x21, 0 - .dw 0xf1c0, 0xc819, 0xf1ff, 0xc819, 0x21, 0 - .dw 0xf240, 0xc819, 0xf27f, 0xc819, 0x21, 0 - .dw 0xf2c0, 0xc819, 0xf2ff, 0xc819, 0x21, 0 - .dw 0xf340, 0xc819, 0xf37f, 0xc819, 0x21, 0 - .dw 0xf3c0, 0xc819, 0xf3ff, 0xc819, 0x21, 0 - .dw 0xf440, 0xc819, 0xf47f, 0xc819, 0x21, 0 - .dw 0xf4c0, 0xc819, 0xf4ff, 0xc819, 0x21, 0 - .dw 0xf540, 0xc819, 0xf57f, 0xc819, 0x21, 0 - .dw 0xf5c0, 0xc819, 0xf5ff, 0xc819, 0x21, 0 - .dw 0xf640, 0xc819, 0xf67f, 0xc819, 0x21, 0 - .dw 0xf6c0, 0xc819, 0xf6ff, 0xc819, 0x21, 0 - .dw 0xf740, 0xc819, 0xf77f, 0xc819, 0x21, 0 - .dw 0xf7c0, 0xc819, 0xf7ff, 0xc819, 0x21, 0 - .dw 0xf840, 0xc819, 0xf87f, 0xc819, 0x21, 0 - .dw 0xf8c0, 0xc819, 0xf8ff, 0xc819, 0x21, 0 - .dw 0xf940, 0xc819, 0xf97f, 0xc819, 0x21, 0 - .dw 0xf9c0, 0xc819, 0x1fff, 0xc81a, 0x21, 0 - .dw 0x2040, 0xc81a, 0x207f, 0xc81a, 0x21, 0 - .dw 0x20c0, 0xc81a, 0x20ff, 0xc81a, 0x21, 0 - .dw 0x2140, 0xc81a, 0x217f, 0xc81a, 0x21, 0 - .dw 0x21c0, 0xc81a, 0x21ff, 0xc81a, 0x21, 0 - .dw 0x2240, 0xc81a, 0x227f, 0xc81a, 0x21, 0 - .dw 0x22c0, 0xc81a, 0x22ff, 0xc81a, 0x21, 0 - .dw 0x2340, 0xc81a, 0x237f, 0xc81a, 0x21, 0 - .dw 0x23c0, 0xc81a, 0x23ff, 0xc81a, 0x21, 0 - .dw 0x2440, 0xc81a, 0x247f, 0xc81a, 0x21, 0 - .dw 0x24c0, 0xc81a, 0x24ff, 0xc81a, 0x21, 0 - .dw 0x2540, 0xc81a, 0x257f, 0xc81a, 0x21, 0 - .dw 0x25c0, 0xc81a, 0x25ff, 0xc81a, 0x21, 0 - .dw 0x2640, 0xc81a, 0x267f, 0xc81a, 0x21, 0 - .dw 0x26c0, 0xc81a, 0x26ff, 0xc81a, 0x21, 0 - .dw 0x2740, 0xc81a, 0x277f, 0xc81a, 0x21, 0 - .dw 0x27c0, 0xc81a, 0x27ff, 0xc81a, 0x21, 0 - .dw 0x2840, 0xc81a, 0x287f, 0xc81a, 0x21, 0 - .dw 0x28c0, 0xc81a, 0x28ff, 0xc81a, 0x21, 0 - .dw 0x2940, 0xc81a, 0x297f, 0xc81a, 0x21, 0 - .dw 0x29c0, 0xc81a, 0x29ff, 0xc81a, 0x21, 0 - .dw 0x2a40, 0xc81a, 0x2a7f, 0xc81a, 0x21, 0 - .dw 0x2ac0, 0xc81a, 0x2aff, 0xc81a, 0x21, 0 - .dw 0x2b40, 0xc81a, 0x2b7f, 0xc81a, 0x21, 0 - .dw 0x2bc0, 0xc81a, 0x2bff, 0xc81a, 0x21, 0 - .dw 0x2c40, 0xc81a, 0x2c7f, 0xc81a, 0x21, 0 - .dw 0x2cc0, 0xc81a, 0x2cff, 0xc81a, 0x21, 0 - .dw 0x2d40, 0xc81a, 0x2d7f, 0xc81a, 0x21, 0 - .dw 0x2dc0, 0xc81a, 0x2dff, 0xc81a, 0x21, 0 - .dw 0x2e40, 0xc81a, 0x2e7f, 0xc81a, 0x21, 0 - .dw 0x2ec0, 0xc81a, 0x2eff, 0xc81a, 0x21, 0 - .dw 0x2f40, 0xc81a, 0x2f7f, 0xc81a, 0x21, 0 - .dw 0x2fc0, 0xc81a, 0x2fff, 0xc81a, 0x21, 0 - .dw 0x3040, 0xc81a, 0x307f, 0xc81a, 0x21, 0 - .dw 0x30c0, 0xc81a, 0x30ff, 0xc81a, 0x21, 0 - .dw 0x3140, 0xc81a, 0x317f, 0xc81a, 0x21, 0 - .dw 0x31c0, 0xc81a, 0x31ff, 0xc81a, 0x21, 0 - .dw 0x3240, 0xc81a, 0x327f, 0xc81a, 0x21, 0 - .dw 0x32c0, 0xc81a, 0x32ff, 0xc81a, 0x21, 0 - .dw 0x3340, 0xc81a, 0x337f, 0xc81a, 0x21, 0 - .dw 0x33c0, 0xc81a, 0x33ff, 0xc81a, 0x21, 0 - .dw 0x3440, 0xc81a, 0x347f, 0xc81a, 0x21, 0 - .dw 0x34c0, 0xc81a, 0x34ff, 0xc81a, 0x21, 0 - .dw 0x3540, 0xc81a, 0x357f, 0xc81a, 0x21, 0 - .dw 0x35c0, 0xc81a, 0x35ff, 0xc81a, 0x21, 0 - .dw 0x3640, 0xc81a, 0x367f, 0xc81a, 0x21, 0 - .dw 0x36c0, 0xc81a, 0x36ff, 0xc81a, 0x21, 0 - .dw 0x3740, 0xc81a, 0x377f, 0xc81a, 0x21, 0 - .dw 0x37c0, 0xc81a, 0x37ff, 0xc81a, 0x21, 0 - .dw 0x3840, 0xc81a, 0x387f, 0xc81a, 0x21, 0 - .dw 0x38c0, 0xc81a, 0x38ff, 0xc81a, 0x21, 0 - .dw 0x3940, 0xc81a, 0x397f, 0xc81a, 0x21, 0 - .dw 0x39c0, 0xc81a, 0x5fff, 0xc81a, 0x21, 0 - .dw 0x6040, 0xc81a, 0x607f, 0xc81a, 0x21, 0 - .dw 0x60c0, 0xc81a, 0x60ff, 0xc81a, 0x21, 0 - .dw 0x6140, 0xc81a, 0x617f, 0xc81a, 0x21, 0 - .dw 0x61c0, 0xc81a, 0x61ff, 0xc81a, 0x21, 0 - .dw 0x6240, 0xc81a, 0x627f, 0xc81a, 0x21, 0 - .dw 0x62c0, 0xc81a, 0x62ff, 0xc81a, 0x21, 0 - .dw 0x6340, 0xc81a, 0x637f, 0xc81a, 0x21, 0 - .dw 0x63c0, 0xc81a, 0x63ff, 0xc81a, 0x21, 0 - .dw 0x6440, 0xc81a, 0x647f, 0xc81a, 0x21, 0 - .dw 0x64c0, 0xc81a, 0x64ff, 0xc81a, 0x21, 0 - .dw 0x6540, 0xc81a, 0x657f, 0xc81a, 0x21, 0 - .dw 0x65c0, 0xc81a, 0x65ff, 0xc81a, 0x21, 0 - .dw 0x6640, 0xc81a, 0x667f, 0xc81a, 0x21, 0 - .dw 0x66c0, 0xc81a, 0x66ff, 0xc81a, 0x21, 0 - .dw 0x6740, 0xc81a, 0x677f, 0xc81a, 0x21, 0 - .dw 0x67c0, 0xc81a, 0x67ff, 0xc81a, 0x21, 0 - .dw 0x6840, 0xc81a, 0x687f, 0xc81a, 0x21, 0 - .dw 0x68c0, 0xc81a, 0x68ff, 0xc81a, 0x21, 0 - .dw 0x6940, 0xc81a, 0x697f, 0xc81a, 0x21, 0 - .dw 0x69c0, 0xc81a, 0x69ff, 0xc81a, 0x21, 0 - .dw 0x6a40, 0xc81a, 0x6a7f, 0xc81a, 0x21, 0 - .dw 0x6ac0, 0xc81a, 0x6aff, 0xc81a, 0x21, 0 - .dw 0x6b40, 0xc81a, 0x6b7f, 0xc81a, 0x21, 0 - .dw 0x6bc0, 0xc81a, 0x6bff, 0xc81a, 0x21, 0 - .dw 0x6c40, 0xc81a, 0x6c7f, 0xc81a, 0x21, 0 - .dw 0x6cc0, 0xc81a, 0x6cff, 0xc81a, 0x21, 0 - .dw 0x6d40, 0xc81a, 0x6d7f, 0xc81a, 0x21, 0 - .dw 0x6dc0, 0xc81a, 0x6dff, 0xc81a, 0x21, 0 - .dw 0x6e40, 0xc81a, 0x6e7f, 0xc81a, 0x21, 0 - .dw 0x6ec0, 0xc81a, 0x6eff, 0xc81a, 0x21, 0 - .dw 0x6f40, 0xc81a, 0x6f7f, 0xc81a, 0x21, 0 - .dw 0x6fc0, 0xc81a, 0x6fff, 0xc81a, 0x21, 0 - .dw 0x7040, 0xc81a, 0x707f, 0xc81a, 0x21, 0 - .dw 0x70c0, 0xc81a, 0x70ff, 0xc81a, 0x21, 0 - .dw 0x7140, 0xc81a, 0x717f, 0xc81a, 0x21, 0 - .dw 0x71c0, 0xc81a, 0x71ff, 0xc81a, 0x21, 0 - .dw 0x7240, 0xc81a, 0x727f, 0xc81a, 0x21, 0 - .dw 0x72c0, 0xc81a, 0x72ff, 0xc81a, 0x21, 0 - .dw 0x7340, 0xc81a, 0x737f, 0xc81a, 0x21, 0 - .dw 0x73c0, 0xc81a, 0x73ff, 0xc81a, 0x21, 0 - .dw 0x7440, 0xc81a, 0x747f, 0xc81a, 0x21, 0 - .dw 0x74c0, 0xc81a, 0x74ff, 0xc81a, 0x21, 0 - .dw 0x7540, 0xc81a, 0x757f, 0xc81a, 0x21, 0 - .dw 0x75c0, 0xc81a, 0x75ff, 0xc81a, 0x21, 0 - .dw 0x7640, 0xc81a, 0x767f, 0xc81a, 0x21, 0 - .dw 0x76c0, 0xc81a, 0x76ff, 0xc81a, 0x21, 0 - .dw 0x7740, 0xc81a, 0x777f, 0xc81a, 0x21, 0 - .dw 0x77c0, 0xc81a, 0x77ff, 0xc81a, 0x21, 0 - .dw 0x7840, 0xc81a, 0x787f, 0xc81a, 0x21, 0 - .dw 0x78c0, 0xc81a, 0x78ff, 0xc81a, 0x21, 0 - .dw 0x7940, 0xc81a, 0x797f, 0xc81a, 0x21, 0 - .dw 0x79c0, 0xc81a, 0x9fff, 0xc81a, 0x21, 0 - .dw 0xa040, 0xc81a, 0xa07f, 0xc81a, 0x21, 0 - .dw 0xa0c0, 0xc81a, 0xa0ff, 0xc81a, 0x21, 0 - .dw 0xa140, 0xc81a, 0xa17f, 0xc81a, 0x21, 0 - .dw 0xa1c0, 0xc81a, 0xa1ff, 0xc81a, 0x21, 0 - .dw 0xa240, 0xc81a, 0xa27f, 0xc81a, 0x21, 0 - .dw 0xa2c0, 0xc81a, 0xa2ff, 0xc81a, 0x21, 0 - .dw 0xa340, 0xc81a, 0xa37f, 0xc81a, 0x21, 0 - .dw 0xa3c0, 0xc81a, 0xa3ff, 0xc81a, 0x21, 0 - .dw 0xa440, 0xc81a, 0xa47f, 0xc81a, 0x21, 0 - .dw 0xa4c0, 0xc81a, 0xa4ff, 0xc81a, 0x21, 0 - .dw 0xa540, 0xc81a, 0xa57f, 0xc81a, 0x21, 0 - .dw 0xa5c0, 0xc81a, 0xa5ff, 0xc81a, 0x21, 0 - .dw 0xa640, 0xc81a, 0xa67f, 0xc81a, 0x21, 0 - .dw 0xa6c0, 0xc81a, 0xa6ff, 0xc81a, 0x21, 0 - .dw 0xa740, 0xc81a, 0xa77f, 0xc81a, 0x21, 0 - .dw 0xa7c0, 0xc81a, 0xa7ff, 0xc81a, 0x21, 0 - .dw 0xa840, 0xc81a, 0xa87f, 0xc81a, 0x21, 0 - .dw 0xa8c0, 0xc81a, 0xa8ff, 0xc81a, 0x21, 0 - .dw 0xa940, 0xc81a, 0xa97f, 0xc81a, 0x21, 0 - .dw 0xa9c0, 0xc81a, 0xa9ff, 0xc81a, 0x21, 0 - .dw 0xaa40, 0xc81a, 0xaa7f, 0xc81a, 0x21, 0 - .dw 0xaac0, 0xc81a, 0xaaff, 0xc81a, 0x21, 0 - .dw 0xab40, 0xc81a, 0xab7f, 0xc81a, 0x21, 0 - .dw 0xabc0, 0xc81a, 0xabff, 0xc81a, 0x21, 0 - .dw 0xac40, 0xc81a, 0xac7f, 0xc81a, 0x21, 0 - .dw 0xacc0, 0xc81a, 0xacff, 0xc81a, 0x21, 0 - .dw 0xad40, 0xc81a, 0xad7f, 0xc81a, 0x21, 0 - .dw 0xadc0, 0xc81a, 0xadff, 0xc81a, 0x21, 0 - .dw 0xae40, 0xc81a, 0xae7f, 0xc81a, 0x21, 0 - .dw 0xaec0, 0xc81a, 0xaeff, 0xc81a, 0x21, 0 - .dw 0xaf40, 0xc81a, 0xaf7f, 0xc81a, 0x21, 0 - .dw 0xafc0, 0xc81a, 0xafff, 0xc81a, 0x21, 0 - .dw 0xb040, 0xc81a, 0xb07f, 0xc81a, 0x21, 0 - .dw 0xb0c0, 0xc81a, 0xb0ff, 0xc81a, 0x21, 0 - .dw 0xb140, 0xc81a, 0xb17f, 0xc81a, 0x21, 0 - .dw 0xb1c0, 0xc81a, 0xb1ff, 0xc81a, 0x21, 0 - .dw 0xb240, 0xc81a, 0xb27f, 0xc81a, 0x21, 0 - .dw 0xb2c0, 0xc81a, 0xb2ff, 0xc81a, 0x21, 0 - .dw 0xb340, 0xc81a, 0xb37f, 0xc81a, 0x21, 0 - .dw 0xb3c0, 0xc81a, 0xb3ff, 0xc81a, 0x21, 0 - .dw 0xb440, 0xc81a, 0xb47f, 0xc81a, 0x21, 0 - .dw 0xb4c0, 0xc81a, 0xb4ff, 0xc81a, 0x21, 0 - .dw 0xb540, 0xc81a, 0xb57f, 0xc81a, 0x21, 0 - .dw 0xb5c0, 0xc81a, 0xb5ff, 0xc81a, 0x21, 0 - .dw 0xb640, 0xc81a, 0xb67f, 0xc81a, 0x21, 0 - .dw 0xb6c0, 0xc81a, 0xb6ff, 0xc81a, 0x21, 0 - .dw 0xb740, 0xc81a, 0xb77f, 0xc81a, 0x21, 0 - .dw 0xb7c0, 0xc81a, 0xb7ff, 0xc81a, 0x21, 0 - .dw 0xb840, 0xc81a, 0xb87f, 0xc81a, 0x21, 0 - .dw 0xb8c0, 0xc81a, 0xb8ff, 0xc81a, 0x21, 0 - .dw 0xb940, 0xc81a, 0xb97f, 0xc81a, 0x21, 0 - .dw 0xb9c0, 0xc81a, 0xdfff, 0xc81a, 0x21, 0 - .dw 0xe040, 0xc81a, 0xe07f, 0xc81a, 0x21, 0 - .dw 0xe0c0, 0xc81a, 0xe0ff, 0xc81a, 0x21, 0 - .dw 0xe140, 0xc81a, 0xe17f, 0xc81a, 0x21, 0 - .dw 0xe1c0, 0xc81a, 0xe1ff, 0xc81a, 0x21, 0 - .dw 0xe240, 0xc81a, 0xe27f, 0xc81a, 0x21, 0 - .dw 0xe2c0, 0xc81a, 0xe2ff, 0xc81a, 0x21, 0 - .dw 0xe340, 0xc81a, 0xe37f, 0xc81a, 0x21, 0 - .dw 0xe3c0, 0xc81a, 0xe3ff, 0xc81a, 0x21, 0 - .dw 0xe440, 0xc81a, 0xe47f, 0xc81a, 0x21, 0 - .dw 0xe4c0, 0xc81a, 0xe4ff, 0xc81a, 0x21, 0 - .dw 0xe540, 0xc81a, 0xe57f, 0xc81a, 0x21, 0 - .dw 0xe5c0, 0xc81a, 0xe5ff, 0xc81a, 0x21, 0 - .dw 0xe640, 0xc81a, 0xe67f, 0xc81a, 0x21, 0 - .dw 0xe6c0, 0xc81a, 0xe6ff, 0xc81a, 0x21, 0 - .dw 0xe740, 0xc81a, 0xe77f, 0xc81a, 0x21, 0 - .dw 0xe7c0, 0xc81a, 0xe7ff, 0xc81a, 0x21, 0 - .dw 0xe840, 0xc81a, 0xe87f, 0xc81a, 0x21, 0 - .dw 0xe8c0, 0xc81a, 0xe8ff, 0xc81a, 0x21, 0 - .dw 0xe940, 0xc81a, 0xe97f, 0xc81a, 0x21, 0 - .dw 0xe9c0, 0xc81a, 0xe9ff, 0xc81a, 0x21, 0 - .dw 0xea40, 0xc81a, 0xea7f, 0xc81a, 0x21, 0 - .dw 0xeac0, 0xc81a, 0xeaff, 0xc81a, 0x21, 0 - .dw 0xeb40, 0xc81a, 0xeb7f, 0xc81a, 0x21, 0 - .dw 0xebc0, 0xc81a, 0xebff, 0xc81a, 0x21, 0 - .dw 0xec40, 0xc81a, 0xec7f, 0xc81a, 0x21, 0 - .dw 0xecc0, 0xc81a, 0xecff, 0xc81a, 0x21, 0 - .dw 0xed40, 0xc81a, 0xed7f, 0xc81a, 0x21, 0 - .dw 0xedc0, 0xc81a, 0xedff, 0xc81a, 0x21, 0 - .dw 0xee40, 0xc81a, 0xee7f, 0xc81a, 0x21, 0 - .dw 0xeec0, 0xc81a, 0xeeff, 0xc81a, 0x21, 0 - .dw 0xef40, 0xc81a, 0xef7f, 0xc81a, 0x21, 0 - .dw 0xefc0, 0xc81a, 0xefff, 0xc81a, 0x21, 0 - .dw 0xf040, 0xc81a, 0xf07f, 0xc81a, 0x21, 0 - .dw 0xf0c0, 0xc81a, 0xf0ff, 0xc81a, 0x21, 0 - .dw 0xf140, 0xc81a, 0xf17f, 0xc81a, 0x21, 0 - .dw 0xf1c0, 0xc81a, 0xf1ff, 0xc81a, 0x21, 0 - .dw 0xf240, 0xc81a, 0xf27f, 0xc81a, 0x21, 0 - .dw 0xf2c0, 0xc81a, 0xf2ff, 0xc81a, 0x21, 0 - .dw 0xf340, 0xc81a, 0xf37f, 0xc81a, 0x21, 0 - .dw 0xf3c0, 0xc81a, 0xf3ff, 0xc81a, 0x21, 0 - .dw 0xf440, 0xc81a, 0xf47f, 0xc81a, 0x21, 0 - .dw 0xf4c0, 0xc81a, 0xf4ff, 0xc81a, 0x21, 0 - .dw 0xf540, 0xc81a, 0xf57f, 0xc81a, 0x21, 0 - .dw 0xf5c0, 0xc81a, 0xf5ff, 0xc81a, 0x21, 0 - .dw 0xf640, 0xc81a, 0xf67f, 0xc81a, 0x21, 0 - .dw 0xf6c0, 0xc81a, 0xf6ff, 0xc81a, 0x21, 0 - .dw 0xf740, 0xc81a, 0xf77f, 0xc81a, 0x21, 0 - .dw 0xf7c0, 0xc81a, 0xf7ff, 0xc81a, 0x21, 0 - .dw 0xf840, 0xc81a, 0xf87f, 0xc81a, 0x21, 0 - .dw 0xf8c0, 0xc81a, 0xf8ff, 0xc81a, 0x21, 0 - .dw 0xf940, 0xc81a, 0xf97f, 0xc81a, 0x21, 0 - .dw 0xf9c0, 0xc81a, 0xffff, 0xc81b, 0x21, 0 - .dw 0x0040, 0xc81c, 0x007f, 0xc81c, 0x21, 0 - .dw 0x00c0, 0xc81c, 0x00ff, 0xc81c, 0x21, 0 - .dw 0x0140, 0xc81c, 0x017f, 0xc81c, 0x21, 0 - .dw 0x01c0, 0xc81c, 0x01ff, 0xc81c, 0x21, 0 - .dw 0x0240, 0xc81c, 0x027f, 0xc81c, 0x21, 0 - .dw 0x02c0, 0xc81c, 0x02ff, 0xc81c, 0x21, 0 - .dw 0x0340, 0xc81c, 0x037f, 0xc81c, 0x21, 0 - .dw 0x03c0, 0xc81c, 0x03ff, 0xc81c, 0x21, 0 - .dw 0x0440, 0xc81c, 0x047f, 0xc81c, 0x21, 0 - .dw 0x04c0, 0xc81c, 0x04ff, 0xc81c, 0x21, 0 - .dw 0x0540, 0xc81c, 0x057f, 0xc81c, 0x21, 0 - .dw 0x05c0, 0xc81c, 0x05ff, 0xc81c, 0x21, 0 - .dw 0x0640, 0xc81c, 0x067f, 0xc81c, 0x21, 0 - .dw 0x06c0, 0xc81c, 0x06ff, 0xc81c, 0x21, 0 - .dw 0x0740, 0xc81c, 0x077f, 0xc81c, 0x21, 0 - .dw 0x07c0, 0xc81c, 0x07ff, 0xc81c, 0x21, 0 - .dw 0x0840, 0xc81c, 0x087f, 0xc81c, 0x21, 0 - .dw 0x08c0, 0xc81c, 0x08ff, 0xc81c, 0x21, 0 - .dw 0x0940, 0xc81c, 0x097f, 0xc81c, 0x21, 0 - .dw 0x09c0, 0xc81c, 0x09ff, 0xc81c, 0x21, 0 - .dw 0x0a40, 0xc81c, 0x0a7f, 0xc81c, 0x21, 0 - .dw 0x0ac0, 0xc81c, 0x0aff, 0xc81c, 0x21, 0 - .dw 0x0b40, 0xc81c, 0x0b7f, 0xc81c, 0x21, 0 - .dw 0x0bc0, 0xc81c, 0x0bff, 0xc81c, 0x21, 0 - .dw 0x0c40, 0xc81c, 0x0c7f, 0xc81c, 0x21, 0 - .dw 0x0cc0, 0xc81c, 0x0cff, 0xc81c, 0x21, 0 - .dw 0x0d40, 0xc81c, 0x0d7f, 0xc81c, 0x21, 0 - .dw 0x0dc0, 0xc81c, 0x0dff, 0xc81c, 0x21, 0 - .dw 0x0e40, 0xc81c, 0x0e7f, 0xc81c, 0x21, 0 - .dw 0x0ec0, 0xc81c, 0x0eff, 0xc81c, 0x21, 0 - .dw 0x0f40, 0xc81c, 0x0f7f, 0xc81c, 0x21, 0 - .dw 0x0fc0, 0xc81c, 0x0fff, 0xc81c, 0x21, 0 - .dw 0x1040, 0xc81c, 0x107f, 0xc81c, 0x21, 0 - .dw 0x10c0, 0xc81c, 0x10ff, 0xc81c, 0x21, 0 - .dw 0x1140, 0xc81c, 0x117f, 0xc81c, 0x21, 0 - .dw 0x11c0, 0xc81c, 0x11ff, 0xc81c, 0x21, 0 - .dw 0x1240, 0xc81c, 0x127f, 0xc81c, 0x21, 0 - .dw 0x12c0, 0xc81c, 0x12ff, 0xc81c, 0x21, 0 - .dw 0x1340, 0xc81c, 0x137f, 0xc81c, 0x21, 0 - .dw 0x13c0, 0xc81c, 0x13ff, 0xc81c, 0x21, 0 - .dw 0x1440, 0xc81c, 0x147f, 0xc81c, 0x21, 0 - .dw 0x14c0, 0xc81c, 0x14ff, 0xc81c, 0x21, 0 - .dw 0x1540, 0xc81c, 0x157f, 0xc81c, 0x21, 0 - .dw 0x15c0, 0xc81c, 0x15ff, 0xc81c, 0x21, 0 - .dw 0x1640, 0xc81c, 0x167f, 0xc81c, 0x21, 0 - .dw 0x16c0, 0xc81c, 0x16ff, 0xc81c, 0x21, 0 - .dw 0x1740, 0xc81c, 0x177f, 0xc81c, 0x21, 0 - .dw 0x17c0, 0xc81c, 0x17ff, 0xc81c, 0x21, 0 - .dw 0x1840, 0xc81c, 0x187f, 0xc81c, 0x21, 0 - .dw 0x18c0, 0xc81c, 0x18ff, 0xc81c, 0x21, 0 - .dw 0x1940, 0xc81c, 0x197f, 0xc81c, 0x21, 0 - .dw 0x19c0, 0xc81c, 0x1fff, 0xc81c, 0x21, 0 - .dw 0x2040, 0xc81c, 0x207f, 0xc81c, 0x21, 0 - .dw 0x20c0, 0xc81c, 0x20ff, 0xc81c, 0x21, 0 - .dw 0x2140, 0xc81c, 0x217f, 0xc81c, 0x21, 0 - .dw 0x21c0, 0xc81c, 0x21ff, 0xc81c, 0x21, 0 - .dw 0x2240, 0xc81c, 0x227f, 0xc81c, 0x21, 0 - .dw 0x22c0, 0xc81c, 0x22ff, 0xc81c, 0x21, 0 - .dw 0x2340, 0xc81c, 0x237f, 0xc81c, 0x21, 0 - .dw 0x23c0, 0xc81c, 0x23ff, 0xc81c, 0x21, 0 - .dw 0x2440, 0xc81c, 0x247f, 0xc81c, 0x21, 0 - .dw 0x24c0, 0xc81c, 0x24ff, 0xc81c, 0x21, 0 - .dw 0x2540, 0xc81c, 0x257f, 0xc81c, 0x21, 0 - .dw 0x25c0, 0xc81c, 0x25ff, 0xc81c, 0x21, 0 - .dw 0x2640, 0xc81c, 0x267f, 0xc81c, 0x21, 0 - .dw 0x26c0, 0xc81c, 0x26ff, 0xc81c, 0x21, 0 - .dw 0x2740, 0xc81c, 0x277f, 0xc81c, 0x21, 0 - .dw 0x27c0, 0xc81c, 0x27ff, 0xc81c, 0x21, 0 - .dw 0x2840, 0xc81c, 0x287f, 0xc81c, 0x21, 0 - .dw 0x28c0, 0xc81c, 0x28ff, 0xc81c, 0x21, 0 - .dw 0x2940, 0xc81c, 0x297f, 0xc81c, 0x21, 0 - .dw 0x29c0, 0xc81c, 0x29ff, 0xc81c, 0x21, 0 - .dw 0x2a40, 0xc81c, 0x2a7f, 0xc81c, 0x21, 0 - .dw 0x2ac0, 0xc81c, 0x2aff, 0xc81c, 0x21, 0 - .dw 0x2b40, 0xc81c, 0x2b7f, 0xc81c, 0x21, 0 - .dw 0x2bc0, 0xc81c, 0x2bff, 0xc81c, 0x21, 0 - .dw 0x2c40, 0xc81c, 0x2c7f, 0xc81c, 0x21, 0 - .dw 0x2cc0, 0xc81c, 0x2cff, 0xc81c, 0x21, 0 - .dw 0x2d40, 0xc81c, 0x2d7f, 0xc81c, 0x21, 0 - .dw 0x2dc0, 0xc81c, 0x2dff, 0xc81c, 0x21, 0 - .dw 0x2e40, 0xc81c, 0x2e7f, 0xc81c, 0x21, 0 - .dw 0x2ec0, 0xc81c, 0x2eff, 0xc81c, 0x21, 0 - .dw 0x2f40, 0xc81c, 0x2f7f, 0xc81c, 0x21, 0 - .dw 0x2fc0, 0xc81c, 0x2fff, 0xc81c, 0x21, 0 - .dw 0x3040, 0xc81c, 0x307f, 0xc81c, 0x21, 0 - .dw 0x30c0, 0xc81c, 0x30ff, 0xc81c, 0x21, 0 - .dw 0x3140, 0xc81c, 0x317f, 0xc81c, 0x21, 0 - .dw 0x31c0, 0xc81c, 0x31ff, 0xc81c, 0x21, 0 - .dw 0x3240, 0xc81c, 0x327f, 0xc81c, 0x21, 0 - .dw 0x32c0, 0xc81c, 0x32ff, 0xc81c, 0x21, 0 - .dw 0x3340, 0xc81c, 0x337f, 0xc81c, 0x21, 0 - .dw 0x33c0, 0xc81c, 0x33ff, 0xc81c, 0x21, 0 - .dw 0x3440, 0xc81c, 0x347f, 0xc81c, 0x21, 0 - .dw 0x34c0, 0xc81c, 0x34ff, 0xc81c, 0x21, 0 - .dw 0x3540, 0xc81c, 0x357f, 0xc81c, 0x21, 0 - .dw 0x35c0, 0xc81c, 0x35ff, 0xc81c, 0x21, 0 - .dw 0x3640, 0xc81c, 0x367f, 0xc81c, 0x21, 0 - .dw 0x36c0, 0xc81c, 0x36ff, 0xc81c, 0x21, 0 - .dw 0x3740, 0xc81c, 0x377f, 0xc81c, 0x21, 0 - .dw 0x37c0, 0xc81c, 0x37ff, 0xc81c, 0x21, 0 - .dw 0x3840, 0xc81c, 0x387f, 0xc81c, 0x21, 0 - .dw 0x38c0, 0xc81c, 0x38ff, 0xc81c, 0x21, 0 - .dw 0x3940, 0xc81c, 0x397f, 0xc81c, 0x21, 0 - .dw 0x39c0, 0xc81c, 0x3fff, 0xc81c, 0x21, 0 - .dw 0x4040, 0xc81c, 0x407f, 0xc81c, 0x21, 0 - .dw 0x40c0, 0xc81c, 0x40ff, 0xc81c, 0x21, 0 - .dw 0x4140, 0xc81c, 0x417f, 0xc81c, 0x21, 0 - .dw 0x41c0, 0xc81c, 0x41ff, 0xc81c, 0x21, 0 - .dw 0x4240, 0xc81c, 0x427f, 0xc81c, 0x21, 0 - .dw 0x42c0, 0xc81c, 0x42ff, 0xc81c, 0x21, 0 - .dw 0x4340, 0xc81c, 0x437f, 0xc81c, 0x21, 0 - .dw 0x43c0, 0xc81c, 0x43ff, 0xc81c, 0x21, 0 - .dw 0x4440, 0xc81c, 0x447f, 0xc81c, 0x21, 0 - .dw 0x44c0, 0xc81c, 0x44ff, 0xc81c, 0x21, 0 - .dw 0x4540, 0xc81c, 0x457f, 0xc81c, 0x21, 0 - .dw 0x45c0, 0xc81c, 0x45ff, 0xc81c, 0x21, 0 - .dw 0x4640, 0xc81c, 0x467f, 0xc81c, 0x21, 0 - .dw 0x46c0, 0xc81c, 0x46ff, 0xc81c, 0x21, 0 - .dw 0x4740, 0xc81c, 0x477f, 0xc81c, 0x21, 0 - .dw 0x47c0, 0xc81c, 0x47ff, 0xc81c, 0x21, 0 - .dw 0x4840, 0xc81c, 0x487f, 0xc81c, 0x21, 0 - .dw 0x48c0, 0xc81c, 0x48ff, 0xc81c, 0x21, 0 - .dw 0x4940, 0xc81c, 0x497f, 0xc81c, 0x21, 0 - .dw 0x49c0, 0xc81c, 0x49ff, 0xc81c, 0x21, 0 - .dw 0x4a40, 0xc81c, 0x4a7f, 0xc81c, 0x21, 0 - .dw 0x4ac0, 0xc81c, 0x4aff, 0xc81c, 0x21, 0 - .dw 0x4b40, 0xc81c, 0x4b7f, 0xc81c, 0x21, 0 - .dw 0x4bc0, 0xc81c, 0x4bff, 0xc81c, 0x21, 0 - .dw 0x4c40, 0xc81c, 0x4c7f, 0xc81c, 0x21, 0 - .dw 0x4cc0, 0xc81c, 0x4cff, 0xc81c, 0x21, 0 - .dw 0x4d40, 0xc81c, 0x4d7f, 0xc81c, 0x21, 0 - .dw 0x4dc0, 0xc81c, 0x4dff, 0xc81c, 0x21, 0 - .dw 0x4e40, 0xc81c, 0x4e7f, 0xc81c, 0x21, 0 - .dw 0x4ec0, 0xc81c, 0x4eff, 0xc81c, 0x21, 0 - .dw 0x4f40, 0xc81c, 0x4f7f, 0xc81c, 0x21, 0 - .dw 0x4fc0, 0xc81c, 0x4fff, 0xc81c, 0x21, 0 - .dw 0x5040, 0xc81c, 0x507f, 0xc81c, 0x21, 0 - .dw 0x50c0, 0xc81c, 0x50ff, 0xc81c, 0x21, 0 - .dw 0x5140, 0xc81c, 0x517f, 0xc81c, 0x21, 0 - .dw 0x51c0, 0xc81c, 0x51ff, 0xc81c, 0x21, 0 - .dw 0x5240, 0xc81c, 0x527f, 0xc81c, 0x21, 0 - .dw 0x52c0, 0xc81c, 0x52ff, 0xc81c, 0x21, 0 - .dw 0x5340, 0xc81c, 0x537f, 0xc81c, 0x21, 0 - .dw 0x53c0, 0xc81c, 0x53ff, 0xc81c, 0x21, 0 - .dw 0x5440, 0xc81c, 0x547f, 0xc81c, 0x21, 0 - .dw 0x54c0, 0xc81c, 0x54ff, 0xc81c, 0x21, 0 - .dw 0x5540, 0xc81c, 0x557f, 0xc81c, 0x21, 0 - .dw 0x55c0, 0xc81c, 0x55ff, 0xc81c, 0x21, 0 - .dw 0x5640, 0xc81c, 0x567f, 0xc81c, 0x21, 0 - .dw 0x56c0, 0xc81c, 0x56ff, 0xc81c, 0x21, 0 - .dw 0x5740, 0xc81c, 0x577f, 0xc81c, 0x21, 0 - .dw 0x57c0, 0xc81c, 0x57ff, 0xc81c, 0x21, 0 - .dw 0x5840, 0xc81c, 0x587f, 0xc81c, 0x21, 0 - .dw 0x58c0, 0xc81c, 0x58ff, 0xc81c, 0x21, 0 - .dw 0x5940, 0xc81c, 0x597f, 0xc81c, 0x21, 0 - .dw 0x59c0, 0xc81c, 0x5fff, 0xc81c, 0x21, 0 - .dw 0x6040, 0xc81c, 0x607f, 0xc81c, 0x21, 0 - .dw 0x60c0, 0xc81c, 0x60ff, 0xc81c, 0x21, 0 - .dw 0x6140, 0xc81c, 0x617f, 0xc81c, 0x21, 0 - .dw 0x61c0, 0xc81c, 0x61ff, 0xc81c, 0x21, 0 - .dw 0x6240, 0xc81c, 0x627f, 0xc81c, 0x21, 0 - .dw 0x62c0, 0xc81c, 0x62ff, 0xc81c, 0x21, 0 - .dw 0x6340, 0xc81c, 0x637f, 0xc81c, 0x21, 0 - .dw 0x63c0, 0xc81c, 0x63ff, 0xc81c, 0x21, 0 - .dw 0x6440, 0xc81c, 0x647f, 0xc81c, 0x21, 0 - .dw 0x64c0, 0xc81c, 0x64ff, 0xc81c, 0x21, 0 - .dw 0x6540, 0xc81c, 0x657f, 0xc81c, 0x21, 0 - .dw 0x65c0, 0xc81c, 0x65ff, 0xc81c, 0x21, 0 - .dw 0x6640, 0xc81c, 0x667f, 0xc81c, 0x21, 0 - .dw 0x66c0, 0xc81c, 0x66ff, 0xc81c, 0x21, 0 - .dw 0x6740, 0xc81c, 0x677f, 0xc81c, 0x21, 0 - .dw 0x67c0, 0xc81c, 0x67ff, 0xc81c, 0x21, 0 - .dw 0x6840, 0xc81c, 0x687f, 0xc81c, 0x21, 0 - .dw 0x68c0, 0xc81c, 0x68ff, 0xc81c, 0x21, 0 - .dw 0x6940, 0xc81c, 0x697f, 0xc81c, 0x21, 0 - .dw 0x69c0, 0xc81c, 0x69ff, 0xc81c, 0x21, 0 - .dw 0x6a40, 0xc81c, 0x6a7f, 0xc81c, 0x21, 0 - .dw 0x6ac0, 0xc81c, 0x6aff, 0xc81c, 0x21, 0 - .dw 0x6b40, 0xc81c, 0x6b7f, 0xc81c, 0x21, 0 - .dw 0x6bc0, 0xc81c, 0x6bff, 0xc81c, 0x21, 0 - .dw 0x6c40, 0xc81c, 0x6c7f, 0xc81c, 0x21, 0 - .dw 0x6cc0, 0xc81c, 0x6cff, 0xc81c, 0x21, 0 - .dw 0x6d40, 0xc81c, 0x6d7f, 0xc81c, 0x21, 0 - .dw 0x6dc0, 0xc81c, 0x6dff, 0xc81c, 0x21, 0 - .dw 0x6e40, 0xc81c, 0x6e7f, 0xc81c, 0x21, 0 - .dw 0x6ec0, 0xc81c, 0x6eff, 0xc81c, 0x21, 0 - .dw 0x6f40, 0xc81c, 0x6f7f, 0xc81c, 0x21, 0 - .dw 0x6fc0, 0xc81c, 0x6fff, 0xc81c, 0x21, 0 - .dw 0x7040, 0xc81c, 0x707f, 0xc81c, 0x21, 0 - .dw 0x70c0, 0xc81c, 0x70ff, 0xc81c, 0x21, 0 - .dw 0x7140, 0xc81c, 0x717f, 0xc81c, 0x21, 0 - .dw 0x71c0, 0xc81c, 0x71ff, 0xc81c, 0x21, 0 - .dw 0x7240, 0xc81c, 0x727f, 0xc81c, 0x21, 0 - .dw 0x72c0, 0xc81c, 0x72ff, 0xc81c, 0x21, 0 - .dw 0x7340, 0xc81c, 0x737f, 0xc81c, 0x21, 0 - .dw 0x73c0, 0xc81c, 0x73ff, 0xc81c, 0x21, 0 - .dw 0x7440, 0xc81c, 0x747f, 0xc81c, 0x21, 0 - .dw 0x74c0, 0xc81c, 0x74ff, 0xc81c, 0x21, 0 - .dw 0x7540, 0xc81c, 0x757f, 0xc81c, 0x21, 0 - .dw 0x75c0, 0xc81c, 0x75ff, 0xc81c, 0x21, 0 - .dw 0x7640, 0xc81c, 0x767f, 0xc81c, 0x21, 0 - .dw 0x76c0, 0xc81c, 0x76ff, 0xc81c, 0x21, 0 - .dw 0x7740, 0xc81c, 0x777f, 0xc81c, 0x21, 0 - .dw 0x77c0, 0xc81c, 0x77ff, 0xc81c, 0x21, 0 - .dw 0x7840, 0xc81c, 0x787f, 0xc81c, 0x21, 0 - .dw 0x78c0, 0xc81c, 0x78ff, 0xc81c, 0x21, 0 - .dw 0x7940, 0xc81c, 0x797f, 0xc81c, 0x21, 0 - .dw 0x79c0, 0xc81c, 0x7fff, 0xc81c, 0x21, 0 - .dw 0x8040, 0xc81c, 0x807f, 0xc81c, 0x21, 0 - .dw 0x80c0, 0xc81c, 0x80ff, 0xc81c, 0x21, 0 - .dw 0x8140, 0xc81c, 0x817f, 0xc81c, 0x21, 0 - .dw 0x81c0, 0xc81c, 0x81ff, 0xc81c, 0x21, 0 - .dw 0x8240, 0xc81c, 0x827f, 0xc81c, 0x21, 0 - .dw 0x82c0, 0xc81c, 0x82ff, 0xc81c, 0x21, 0 - .dw 0x8340, 0xc81c, 0x837f, 0xc81c, 0x21, 0 - .dw 0x83c0, 0xc81c, 0x83ff, 0xc81c, 0x21, 0 - .dw 0x8440, 0xc81c, 0x847f, 0xc81c, 0x21, 0 - .dw 0x84c0, 0xc81c, 0x84ff, 0xc81c, 0x21, 0 - .dw 0x8540, 0xc81c, 0x857f, 0xc81c, 0x21, 0 - .dw 0x85c0, 0xc81c, 0x85ff, 0xc81c, 0x21, 0 - .dw 0x8640, 0xc81c, 0x867f, 0xc81c, 0x21, 0 - .dw 0x86c0, 0xc81c, 0x86ff, 0xc81c, 0x21, 0 - .dw 0x8740, 0xc81c, 0x877f, 0xc81c, 0x21, 0 - .dw 0x87c0, 0xc81c, 0x87ff, 0xc81c, 0x21, 0 - .dw 0x8840, 0xc81c, 0x887f, 0xc81c, 0x21, 0 - .dw 0x88c0, 0xc81c, 0x88ff, 0xc81c, 0x21, 0 - .dw 0x8940, 0xc81c, 0x897f, 0xc81c, 0x21, 0 - .dw 0x89c0, 0xc81c, 0x89ff, 0xc81c, 0x21, 0 - .dw 0x8a40, 0xc81c, 0x8a7f, 0xc81c, 0x21, 0 - .dw 0x8ac0, 0xc81c, 0x8aff, 0xc81c, 0x21, 0 - .dw 0x8b40, 0xc81c, 0x8b7f, 0xc81c, 0x21, 0 - .dw 0x8bc0, 0xc81c, 0x8bff, 0xc81c, 0x21, 0 - .dw 0x8c40, 0xc81c, 0x8c7f, 0xc81c, 0x21, 0 - .dw 0x8cc0, 0xc81c, 0x8cff, 0xc81c, 0x21, 0 - .dw 0x8d40, 0xc81c, 0x8d7f, 0xc81c, 0x21, 0 - .dw 0x8dc0, 0xc81c, 0x8dff, 0xc81c, 0x21, 0 - .dw 0x8e40, 0xc81c, 0x8e7f, 0xc81c, 0x21, 0 - .dw 0x8ec0, 0xc81c, 0x8eff, 0xc81c, 0x21, 0 - .dw 0x8f40, 0xc81c, 0x8f7f, 0xc81c, 0x21, 0 - .dw 0x8fc0, 0xc81c, 0x8fff, 0xc81c, 0x21, 0 - .dw 0x9040, 0xc81c, 0x907f, 0xc81c, 0x21, 0 - .dw 0x90c0, 0xc81c, 0x90ff, 0xc81c, 0x21, 0 - .dw 0x9140, 0xc81c, 0x917f, 0xc81c, 0x21, 0 - .dw 0x91c0, 0xc81c, 0x91ff, 0xc81c, 0x21, 0 - .dw 0x9240, 0xc81c, 0x927f, 0xc81c, 0x21, 0 - .dw 0x92c0, 0xc81c, 0x92ff, 0xc81c, 0x21, 0 - .dw 0x9340, 0xc81c, 0x937f, 0xc81c, 0x21, 0 - .dw 0x93c0, 0xc81c, 0x93ff, 0xc81c, 0x21, 0 - .dw 0x9440, 0xc81c, 0x947f, 0xc81c, 0x21, 0 - .dw 0x94c0, 0xc81c, 0x94ff, 0xc81c, 0x21, 0 - .dw 0x9540, 0xc81c, 0x957f, 0xc81c, 0x21, 0 - .dw 0x95c0, 0xc81c, 0x95ff, 0xc81c, 0x21, 0 - .dw 0x9640, 0xc81c, 0x967f, 0xc81c, 0x21, 0 - .dw 0x96c0, 0xc81c, 0x96ff, 0xc81c, 0x21, 0 - .dw 0x9740, 0xc81c, 0x977f, 0xc81c, 0x21, 0 - .dw 0x97c0, 0xc81c, 0x97ff, 0xc81c, 0x21, 0 - .dw 0x9840, 0xc81c, 0x987f, 0xc81c, 0x21, 0 - .dw 0x98c0, 0xc81c, 0x98ff, 0xc81c, 0x21, 0 - .dw 0x9940, 0xc81c, 0x997f, 0xc81c, 0x21, 0 - .dw 0x99c0, 0xc81c, 0x9fff, 0xc81c, 0x21, 0 - .dw 0xa040, 0xc81c, 0xa07f, 0xc81c, 0x21, 0 - .dw 0xa0c0, 0xc81c, 0xa0ff, 0xc81c, 0x21, 0 - .dw 0xa140, 0xc81c, 0xa17f, 0xc81c, 0x21, 0 - .dw 0xa1c0, 0xc81c, 0xa1ff, 0xc81c, 0x21, 0 - .dw 0xa240, 0xc81c, 0xa27f, 0xc81c, 0x21, 0 - .dw 0xa2c0, 0xc81c, 0xa2ff, 0xc81c, 0x21, 0 - .dw 0xa340, 0xc81c, 0xa37f, 0xc81c, 0x21, 0 - .dw 0xa3c0, 0xc81c, 0xa3ff, 0xc81c, 0x21, 0 - .dw 0xa440, 0xc81c, 0xa47f, 0xc81c, 0x21, 0 - .dw 0xa4c0, 0xc81c, 0xa4ff, 0xc81c, 0x21, 0 - .dw 0xa540, 0xc81c, 0xa57f, 0xc81c, 0x21, 0 - .dw 0xa5c0, 0xc81c, 0xa5ff, 0xc81c, 0x21, 0 - .dw 0xa640, 0xc81c, 0xa67f, 0xc81c, 0x21, 0 - .dw 0xa6c0, 0xc81c, 0xa6ff, 0xc81c, 0x21, 0 - .dw 0xa740, 0xc81c, 0xa77f, 0xc81c, 0x21, 0 - .dw 0xa7c0, 0xc81c, 0xa7ff, 0xc81c, 0x21, 0 - .dw 0xa840, 0xc81c, 0xa87f, 0xc81c, 0x21, 0 - .dw 0xa8c0, 0xc81c, 0xa8ff, 0xc81c, 0x21, 0 - .dw 0xa940, 0xc81c, 0xa97f, 0xc81c, 0x21, 0 - .dw 0xa9c0, 0xc81c, 0xa9ff, 0xc81c, 0x21, 0 - .dw 0xaa40, 0xc81c, 0xaa7f, 0xc81c, 0x21, 0 - .dw 0xaac0, 0xc81c, 0xaaff, 0xc81c, 0x21, 0 - .dw 0xab40, 0xc81c, 0xab7f, 0xc81c, 0x21, 0 - .dw 0xabc0, 0xc81c, 0xabff, 0xc81c, 0x21, 0 - .dw 0xac40, 0xc81c, 0xac7f, 0xc81c, 0x21, 0 - .dw 0xacc0, 0xc81c, 0xacff, 0xc81c, 0x21, 0 - .dw 0xad40, 0xc81c, 0xad7f, 0xc81c, 0x21, 0 - .dw 0xadc0, 0xc81c, 0xadff, 0xc81c, 0x21, 0 - .dw 0xae40, 0xc81c, 0xae7f, 0xc81c, 0x21, 0 - .dw 0xaec0, 0xc81c, 0xaeff, 0xc81c, 0x21, 0 - .dw 0xaf40, 0xc81c, 0xaf7f, 0xc81c, 0x21, 0 - .dw 0xafc0, 0xc81c, 0xafff, 0xc81c, 0x21, 0 - .dw 0xb040, 0xc81c, 0xb07f, 0xc81c, 0x21, 0 - .dw 0xb0c0, 0xc81c, 0xb0ff, 0xc81c, 0x21, 0 - .dw 0xb140, 0xc81c, 0xb17f, 0xc81c, 0x21, 0 - .dw 0xb1c0, 0xc81c, 0xb1ff, 0xc81c, 0x21, 0 - .dw 0xb240, 0xc81c, 0xb27f, 0xc81c, 0x21, 0 - .dw 0xb2c0, 0xc81c, 0xb2ff, 0xc81c, 0x21, 0 - .dw 0xb340, 0xc81c, 0xb37f, 0xc81c, 0x21, 0 - .dw 0xb3c0, 0xc81c, 0xb3ff, 0xc81c, 0x21, 0 - .dw 0xb440, 0xc81c, 0xb47f, 0xc81c, 0x21, 0 - .dw 0xb4c0, 0xc81c, 0xb4ff, 0xc81c, 0x21, 0 - .dw 0xb540, 0xc81c, 0xb57f, 0xc81c, 0x21, 0 - .dw 0xb5c0, 0xc81c, 0xb5ff, 0xc81c, 0x21, 0 - .dw 0xb640, 0xc81c, 0xb67f, 0xc81c, 0x21, 0 - .dw 0xb6c0, 0xc81c, 0xb6ff, 0xc81c, 0x21, 0 - .dw 0xb740, 0xc81c, 0xb77f, 0xc81c, 0x21, 0 - .dw 0xb7c0, 0xc81c, 0xb7ff, 0xc81c, 0x21, 0 - .dw 0xb840, 0xc81c, 0xb87f, 0xc81c, 0x21, 0 - .dw 0xb8c0, 0xc81c, 0xb8ff, 0xc81c, 0x21, 0 - .dw 0xb940, 0xc81c, 0xb97f, 0xc81c, 0x21, 0 - .dw 0xb9c0, 0xc81c, 0xbfff, 0xc81c, 0x21, 0 - .dw 0xc040, 0xc81c, 0xc07f, 0xc81c, 0x21, 0 - .dw 0xc0c0, 0xc81c, 0xc0ff, 0xc81c, 0x21, 0 - .dw 0xc140, 0xc81c, 0xc17f, 0xc81c, 0x21, 0 - .dw 0xc1c0, 0xc81c, 0xc1ff, 0xc81c, 0x21, 0 - .dw 0xc240, 0xc81c, 0xc27f, 0xc81c, 0x21, 0 - .dw 0xc2c0, 0xc81c, 0xc2ff, 0xc81c, 0x21, 0 - .dw 0xc340, 0xc81c, 0xc37f, 0xc81c, 0x21, 0 - .dw 0xc3c0, 0xc81c, 0xc3ff, 0xc81c, 0x21, 0 - .dw 0xc440, 0xc81c, 0xc47f, 0xc81c, 0x21, 0 - .dw 0xc4c0, 0xc81c, 0xc4ff, 0xc81c, 0x21, 0 - .dw 0xc540, 0xc81c, 0xc57f, 0xc81c, 0x21, 0 - .dw 0xc5c0, 0xc81c, 0xc5ff, 0xc81c, 0x21, 0 - .dw 0xc640, 0xc81c, 0xc67f, 0xc81c, 0x21, 0 - .dw 0xc6c0, 0xc81c, 0xc6ff, 0xc81c, 0x21, 0 - .dw 0xc740, 0xc81c, 0xc77f, 0xc81c, 0x21, 0 - .dw 0xc7c0, 0xc81c, 0xc7ff, 0xc81c, 0x21, 0 - .dw 0xc840, 0xc81c, 0xc87f, 0xc81c, 0x21, 0 - .dw 0xc8c0, 0xc81c, 0xc8ff, 0xc81c, 0x21, 0 - .dw 0xc940, 0xc81c, 0xc97f, 0xc81c, 0x21, 0 - .dw 0xc9c0, 0xc81c, 0xc9ff, 0xc81c, 0x21, 0 - .dw 0xca40, 0xc81c, 0xca7f, 0xc81c, 0x21, 0 - .dw 0xcac0, 0xc81c, 0xcaff, 0xc81c, 0x21, 0 - .dw 0xcb40, 0xc81c, 0xcb7f, 0xc81c, 0x21, 0 - .dw 0xcbc0, 0xc81c, 0xcbff, 0xc81c, 0x21, 0 - .dw 0xcc40, 0xc81c, 0xcc7f, 0xc81c, 0x21, 0 - .dw 0xccc0, 0xc81c, 0xccff, 0xc81c, 0x21, 0 - .dw 0xcd40, 0xc81c, 0xcd7f, 0xc81c, 0x21, 0 - .dw 0xcdc0, 0xc81c, 0xcdff, 0xc81c, 0x21, 0 - .dw 0xce40, 0xc81c, 0xce7f, 0xc81c, 0x21, 0 - .dw 0xcec0, 0xc81c, 0xceff, 0xc81c, 0x21, 0 - .dw 0xcf40, 0xc81c, 0xcf7f, 0xc81c, 0x21, 0 - .dw 0xcfc0, 0xc81c, 0xcfff, 0xc81c, 0x21, 0 - .dw 0xd040, 0xc81c, 0xd07f, 0xc81c, 0x21, 0 - .dw 0xd0c0, 0xc81c, 0xd0ff, 0xc81c, 0x21, 0 - .dw 0xd140, 0xc81c, 0xd17f, 0xc81c, 0x21, 0 - .dw 0xd1c0, 0xc81c, 0xd1ff, 0xc81c, 0x21, 0 - .dw 0xd240, 0xc81c, 0xd27f, 0xc81c, 0x21, 0 - .dw 0xd2c0, 0xc81c, 0xd2ff, 0xc81c, 0x21, 0 - .dw 0xd340, 0xc81c, 0xd37f, 0xc81c, 0x21, 0 - .dw 0xd3c0, 0xc81c, 0xd3ff, 0xc81c, 0x21, 0 - .dw 0xd440, 0xc81c, 0xd47f, 0xc81c, 0x21, 0 - .dw 0xd4c0, 0xc81c, 0xd4ff, 0xc81c, 0x21, 0 - .dw 0xd540, 0xc81c, 0xd57f, 0xc81c, 0x21, 0 - .dw 0xd5c0, 0xc81c, 0xd5ff, 0xc81c, 0x21, 0 - .dw 0xd640, 0xc81c, 0xd67f, 0xc81c, 0x21, 0 - .dw 0xd6c0, 0xc81c, 0xd6ff, 0xc81c, 0x21, 0 - .dw 0xd740, 0xc81c, 0xd77f, 0xc81c, 0x21, 0 - .dw 0xd7c0, 0xc81c, 0xd7ff, 0xc81c, 0x21, 0 - .dw 0xd840, 0xc81c, 0xd87f, 0xc81c, 0x21, 0 - .dw 0xd8c0, 0xc81c, 0xd8ff, 0xc81c, 0x21, 0 - .dw 0xd940, 0xc81c, 0xd97f, 0xc81c, 0x21, 0 - .dw 0xd9c0, 0xc81c, 0xdfff, 0xc81c, 0x21, 0 - .dw 0xe040, 0xc81c, 0xe07f, 0xc81c, 0x21, 0 - .dw 0xe0c0, 0xc81c, 0xe0ff, 0xc81c, 0x21, 0 - .dw 0xe140, 0xc81c, 0xe17f, 0xc81c, 0x21, 0 - .dw 0xe1c0, 0xc81c, 0xe1ff, 0xc81c, 0x21, 0 - .dw 0xe240, 0xc81c, 0xe27f, 0xc81c, 0x21, 0 - .dw 0xe2c0, 0xc81c, 0xe2ff, 0xc81c, 0x21, 0 - .dw 0xe340, 0xc81c, 0xe37f, 0xc81c, 0x21, 0 - .dw 0xe3c0, 0xc81c, 0xe3ff, 0xc81c, 0x21, 0 - .dw 0xe440, 0xc81c, 0xe47f, 0xc81c, 0x21, 0 - .dw 0xe4c0, 0xc81c, 0xe4ff, 0xc81c, 0x21, 0 - .dw 0xe540, 0xc81c, 0xe57f, 0xc81c, 0x21, 0 - .dw 0xe5c0, 0xc81c, 0xe5ff, 0xc81c, 0x21, 0 - .dw 0xe640, 0xc81c, 0xe67f, 0xc81c, 0x21, 0 - .dw 0xe6c0, 0xc81c, 0xe6ff, 0xc81c, 0x21, 0 - .dw 0xe740, 0xc81c, 0xe77f, 0xc81c, 0x21, 0 - .dw 0xe7c0, 0xc81c, 0xe7ff, 0xc81c, 0x21, 0 - .dw 0xe840, 0xc81c, 0xe87f, 0xc81c, 0x21, 0 - .dw 0xe8c0, 0xc81c, 0xe8ff, 0xc81c, 0x21, 0 - .dw 0xe940, 0xc81c, 0xe97f, 0xc81c, 0x21, 0 - .dw 0xe9c0, 0xc81c, 0xe9ff, 0xc81c, 0x21, 0 - .dw 0xea40, 0xc81c, 0xea7f, 0xc81c, 0x21, 0 - .dw 0xeac0, 0xc81c, 0xeaff, 0xc81c, 0x21, 0 - .dw 0xeb40, 0xc81c, 0xeb7f, 0xc81c, 0x21, 0 - .dw 0xebc0, 0xc81c, 0xebff, 0xc81c, 0x21, 0 - .dw 0xec40, 0xc81c, 0xec7f, 0xc81c, 0x21, 0 - .dw 0xecc0, 0xc81c, 0xecff, 0xc81c, 0x21, 0 - .dw 0xed40, 0xc81c, 0xed7f, 0xc81c, 0x21, 0 - .dw 0xedc0, 0xc81c, 0xedff, 0xc81c, 0x21, 0 - .dw 0xee40, 0xc81c, 0xee7f, 0xc81c, 0x21, 0 - .dw 0xeec0, 0xc81c, 0xeeff, 0xc81c, 0x21, 0 - .dw 0xef40, 0xc81c, 0xef7f, 0xc81c, 0x21, 0 - .dw 0xefc0, 0xc81c, 0xefff, 0xc81c, 0x21, 0 - .dw 0xf040, 0xc81c, 0xf07f, 0xc81c, 0x21, 0 - .dw 0xf0c0, 0xc81c, 0xf0ff, 0xc81c, 0x21, 0 - .dw 0xf140, 0xc81c, 0xf17f, 0xc81c, 0x21, 0 - .dw 0xf1c0, 0xc81c, 0xf1ff, 0xc81c, 0x21, 0 - .dw 0xf240, 0xc81c, 0xf27f, 0xc81c, 0x21, 0 - .dw 0xf2c0, 0xc81c, 0xf2ff, 0xc81c, 0x21, 0 - .dw 0xf340, 0xc81c, 0xf37f, 0xc81c, 0x21, 0 - .dw 0xf3c0, 0xc81c, 0xf3ff, 0xc81c, 0x21, 0 - .dw 0xf440, 0xc81c, 0xf47f, 0xc81c, 0x21, 0 - .dw 0xf4c0, 0xc81c, 0xf4ff, 0xc81c, 0x21, 0 - .dw 0xf540, 0xc81c, 0xf57f, 0xc81c, 0x21, 0 - .dw 0xf5c0, 0xc81c, 0xf5ff, 0xc81c, 0x21, 0 - .dw 0xf640, 0xc81c, 0xf67f, 0xc81c, 0x21, 0 - .dw 0xf6c0, 0xc81c, 0xf6ff, 0xc81c, 0x21, 0 - .dw 0xf740, 0xc81c, 0xf77f, 0xc81c, 0x21, 0 - .dw 0xf7c0, 0xc81c, 0xf7ff, 0xc81c, 0x21, 0 - .dw 0xf840, 0xc81c, 0xf87f, 0xc81c, 0x21, 0 - .dw 0xf8c0, 0xc81c, 0xf8ff, 0xc81c, 0x21, 0 - .dw 0xf940, 0xc81c, 0xf97f, 0xc81c, 0x21, 0 - .dw 0xf9c0, 0xc81c, 0xffff, 0xc81c, 0x21, 0 - .dw 0x0040, 0xc81d, 0x007f, 0xc81d, 0x21, 0 - .dw 0x00c0, 0xc81d, 0x00ff, 0xc81d, 0x21, 0 - .dw 0x0140, 0xc81d, 0x017f, 0xc81d, 0x21, 0 - .dw 0x01c0, 0xc81d, 0x01ff, 0xc81d, 0x21, 0 - .dw 0x0240, 0xc81d, 0x027f, 0xc81d, 0x21, 0 - .dw 0x02c0, 0xc81d, 0x02ff, 0xc81d, 0x21, 0 - .dw 0x0340, 0xc81d, 0x037f, 0xc81d, 0x21, 0 - .dw 0x03c0, 0xc81d, 0x03ff, 0xc81d, 0x21, 0 - .dw 0x0440, 0xc81d, 0x047f, 0xc81d, 0x21, 0 - .dw 0x04c0, 0xc81d, 0x04ff, 0xc81d, 0x21, 0 - .dw 0x0540, 0xc81d, 0x057f, 0xc81d, 0x21, 0 - .dw 0x05c0, 0xc81d, 0x05ff, 0xc81d, 0x21, 0 - .dw 0x0640, 0xc81d, 0x067f, 0xc81d, 0x21, 0 - .dw 0x06c0, 0xc81d, 0x06ff, 0xc81d, 0x21, 0 - .dw 0x0740, 0xc81d, 0x077f, 0xc81d, 0x21, 0 - .dw 0x07c0, 0xc81d, 0x07ff, 0xc81d, 0x21, 0 - .dw 0x0840, 0xc81d, 0x087f, 0xc81d, 0x21, 0 - .dw 0x08c0, 0xc81d, 0x08ff, 0xc81d, 0x21, 0 - .dw 0x0940, 0xc81d, 0x097f, 0xc81d, 0x21, 0 - .dw 0x09c0, 0xc81d, 0x09ff, 0xc81d, 0x21, 0 - .dw 0x0a40, 0xc81d, 0x0a7f, 0xc81d, 0x21, 0 - .dw 0x0ac0, 0xc81d, 0x0aff, 0xc81d, 0x21, 0 - .dw 0x0b40, 0xc81d, 0x0b7f, 0xc81d, 0x21, 0 - .dw 0x0bc0, 0xc81d, 0x0bff, 0xc81d, 0x21, 0 - .dw 0x0c40, 0xc81d, 0x0c7f, 0xc81d, 0x21, 0 - .dw 0x0cc0, 0xc81d, 0x0cff, 0xc81d, 0x21, 0 - .dw 0x0d40, 0xc81d, 0x0d7f, 0xc81d, 0x21, 0 - .dw 0x0dc0, 0xc81d, 0x0dff, 0xc81d, 0x21, 0 - .dw 0x0e40, 0xc81d, 0x0e7f, 0xc81d, 0x21, 0 - .dw 0x0ec0, 0xc81d, 0x0eff, 0xc81d, 0x21, 0 - .dw 0x0f40, 0xc81d, 0x0f7f, 0xc81d, 0x21, 0 - .dw 0x0fc0, 0xc81d, 0x0fff, 0xc81d, 0x21, 0 - .dw 0x1040, 0xc81d, 0x107f, 0xc81d, 0x21, 0 - .dw 0x10c0, 0xc81d, 0x10ff, 0xc81d, 0x21, 0 - .dw 0x1140, 0xc81d, 0x117f, 0xc81d, 0x21, 0 - .dw 0x11c0, 0xc81d, 0x11ff, 0xc81d, 0x21, 0 - .dw 0x1240, 0xc81d, 0x127f, 0xc81d, 0x21, 0 - .dw 0x12c0, 0xc81d, 0x12ff, 0xc81d, 0x21, 0 - .dw 0x1340, 0xc81d, 0x137f, 0xc81d, 0x21, 0 - .dw 0x13c0, 0xc81d, 0x13ff, 0xc81d, 0x21, 0 - .dw 0x1440, 0xc81d, 0x147f, 0xc81d, 0x21, 0 - .dw 0x14c0, 0xc81d, 0x14ff, 0xc81d, 0x21, 0 - .dw 0x1540, 0xc81d, 0x157f, 0xc81d, 0x21, 0 - .dw 0x15c0, 0xc81d, 0x15ff, 0xc81d, 0x21, 0 - .dw 0x1640, 0xc81d, 0x167f, 0xc81d, 0x21, 0 - .dw 0x16c0, 0xc81d, 0x16ff, 0xc81d, 0x21, 0 - .dw 0x1740, 0xc81d, 0x177f, 0xc81d, 0x21, 0 - .dw 0x17c0, 0xc81d, 0x17ff, 0xc81d, 0x21, 0 - .dw 0x1840, 0xc81d, 0x187f, 0xc81d, 0x21, 0 - .dw 0x18c0, 0xc81d, 0x18ff, 0xc81d, 0x21, 0 - .dw 0x1940, 0xc81d, 0x197f, 0xc81d, 0x21, 0 - .dw 0x19c0, 0xc81d, 0x1fff, 0xc81d, 0x21, 0 - .dw 0x2040, 0xc81d, 0x207f, 0xc81d, 0x21, 0 - .dw 0x20c0, 0xc81d, 0x20ff, 0xc81d, 0x21, 0 - .dw 0x2140, 0xc81d, 0x217f, 0xc81d, 0x21, 0 - .dw 0x21c0, 0xc81d, 0x21ff, 0xc81d, 0x21, 0 - .dw 0x2240, 0xc81d, 0x227f, 0xc81d, 0x21, 0 - .dw 0x22c0, 0xc81d, 0x22ff, 0xc81d, 0x21, 0 - .dw 0x2340, 0xc81d, 0x237f, 0xc81d, 0x21, 0 - .dw 0x23c0, 0xc81d, 0x23ff, 0xc81d, 0x21, 0 - .dw 0x2440, 0xc81d, 0x247f, 0xc81d, 0x21, 0 - .dw 0x24c0, 0xc81d, 0x24ff, 0xc81d, 0x21, 0 - .dw 0x2540, 0xc81d, 0x257f, 0xc81d, 0x21, 0 - .dw 0x25c0, 0xc81d, 0x25ff, 0xc81d, 0x21, 0 - .dw 0x2640, 0xc81d, 0x267f, 0xc81d, 0x21, 0 - .dw 0x26c0, 0xc81d, 0x26ff, 0xc81d, 0x21, 0 - .dw 0x2740, 0xc81d, 0x277f, 0xc81d, 0x21, 0 - .dw 0x27c0, 0xc81d, 0x27ff, 0xc81d, 0x21, 0 - .dw 0x2840, 0xc81d, 0x287f, 0xc81d, 0x21, 0 - .dw 0x28c0, 0xc81d, 0x28ff, 0xc81d, 0x21, 0 - .dw 0x2940, 0xc81d, 0x297f, 0xc81d, 0x21, 0 - .dw 0x29c0, 0xc81d, 0x29ff, 0xc81d, 0x21, 0 - .dw 0x2a40, 0xc81d, 0x2a7f, 0xc81d, 0x21, 0 - .dw 0x2ac0, 0xc81d, 0x2aff, 0xc81d, 0x21, 0 - .dw 0x2b40, 0xc81d, 0x2b7f, 0xc81d, 0x21, 0 - .dw 0x2bc0, 0xc81d, 0x2bff, 0xc81d, 0x21, 0 - .dw 0x2c40, 0xc81d, 0x2c7f, 0xc81d, 0x21, 0 - .dw 0x2cc0, 0xc81d, 0x2cff, 0xc81d, 0x21, 0 - .dw 0x2d40, 0xc81d, 0x2d7f, 0xc81d, 0x21, 0 - .dw 0x2dc0, 0xc81d, 0x2dff, 0xc81d, 0x21, 0 - .dw 0x2e40, 0xc81d, 0x2e7f, 0xc81d, 0x21, 0 - .dw 0x2ec0, 0xc81d, 0x2eff, 0xc81d, 0x21, 0 - .dw 0x2f40, 0xc81d, 0x2f7f, 0xc81d, 0x21, 0 - .dw 0x2fc0, 0xc81d, 0x2fff, 0xc81d, 0x21, 0 - .dw 0x3040, 0xc81d, 0x307f, 0xc81d, 0x21, 0 - .dw 0x30c0, 0xc81d, 0x30ff, 0xc81d, 0x21, 0 - .dw 0x3140, 0xc81d, 0x317f, 0xc81d, 0x21, 0 - .dw 0x31c0, 0xc81d, 0x31ff, 0xc81d, 0x21, 0 - .dw 0x3240, 0xc81d, 0x327f, 0xc81d, 0x21, 0 - .dw 0x32c0, 0xc81d, 0x32ff, 0xc81d, 0x21, 0 - .dw 0x3340, 0xc81d, 0x337f, 0xc81d, 0x21, 0 - .dw 0x33c0, 0xc81d, 0x33ff, 0xc81d, 0x21, 0 - .dw 0x3440, 0xc81d, 0x347f, 0xc81d, 0x21, 0 - .dw 0x34c0, 0xc81d, 0x34ff, 0xc81d, 0x21, 0 - .dw 0x3540, 0xc81d, 0x357f, 0xc81d, 0x21, 0 - .dw 0x35c0, 0xc81d, 0x35ff, 0xc81d, 0x21, 0 - .dw 0x3640, 0xc81d, 0x367f, 0xc81d, 0x21, 0 - .dw 0x36c0, 0xc81d, 0x36ff, 0xc81d, 0x21, 0 - .dw 0x3740, 0xc81d, 0x377f, 0xc81d, 0x21, 0 - .dw 0x37c0, 0xc81d, 0x37ff, 0xc81d, 0x21, 0 - .dw 0x3840, 0xc81d, 0x387f, 0xc81d, 0x21, 0 - .dw 0x38c0, 0xc81d, 0x38ff, 0xc81d, 0x21, 0 - .dw 0x3940, 0xc81d, 0x397f, 0xc81d, 0x21, 0 - .dw 0x39c0, 0xc81d, 0x3fff, 0xc81d, 0x21, 0 - .dw 0x4040, 0xc81d, 0x407f, 0xc81d, 0x21, 0 - .dw 0x40c0, 0xc81d, 0x40ff, 0xc81d, 0x21, 0 - .dw 0x4140, 0xc81d, 0x417f, 0xc81d, 0x21, 0 - .dw 0x41c0, 0xc81d, 0x41ff, 0xc81d, 0x21, 0 - .dw 0x4240, 0xc81d, 0x427f, 0xc81d, 0x21, 0 - .dw 0x42c0, 0xc81d, 0x42ff, 0xc81d, 0x21, 0 - .dw 0x4340, 0xc81d, 0x437f, 0xc81d, 0x21, 0 - .dw 0x43c0, 0xc81d, 0x43ff, 0xc81d, 0x21, 0 - .dw 0x4440, 0xc81d, 0x447f, 0xc81d, 0x21, 0 - .dw 0x44c0, 0xc81d, 0x44ff, 0xc81d, 0x21, 0 - .dw 0x4540, 0xc81d, 0x457f, 0xc81d, 0x21, 0 - .dw 0x45c0, 0xc81d, 0x45ff, 0xc81d, 0x21, 0 - .dw 0x4640, 0xc81d, 0x467f, 0xc81d, 0x21, 0 - .dw 0x46c0, 0xc81d, 0x46ff, 0xc81d, 0x21, 0 - .dw 0x4740, 0xc81d, 0x477f, 0xc81d, 0x21, 0 - .dw 0x47c0, 0xc81d, 0x47ff, 0xc81d, 0x21, 0 - .dw 0x4840, 0xc81d, 0x487f, 0xc81d, 0x21, 0 - .dw 0x48c0, 0xc81d, 0x48ff, 0xc81d, 0x21, 0 - .dw 0x4940, 0xc81d, 0x497f, 0xc81d, 0x21, 0 - .dw 0x49c0, 0xc81d, 0x49ff, 0xc81d, 0x21, 0 - .dw 0x4a40, 0xc81d, 0x4a7f, 0xc81d, 0x21, 0 - .dw 0x4ac0, 0xc81d, 0x4aff, 0xc81d, 0x21, 0 - .dw 0x4b40, 0xc81d, 0x4b7f, 0xc81d, 0x21, 0 - .dw 0x4bc0, 0xc81d, 0x4bff, 0xc81d, 0x21, 0 - .dw 0x4c40, 0xc81d, 0x4c7f, 0xc81d, 0x21, 0 - .dw 0x4cc0, 0xc81d, 0x4cff, 0xc81d, 0x21, 0 - .dw 0x4d40, 0xc81d, 0x4d7f, 0xc81d, 0x21, 0 - .dw 0x4dc0, 0xc81d, 0x4dff, 0xc81d, 0x21, 0 - .dw 0x4e40, 0xc81d, 0x4e7f, 0xc81d, 0x21, 0 - .dw 0x4ec0, 0xc81d, 0x4eff, 0xc81d, 0x21, 0 - .dw 0x4f40, 0xc81d, 0x4f7f, 0xc81d, 0x21, 0 - .dw 0x4fc0, 0xc81d, 0x4fff, 0xc81d, 0x21, 0 - .dw 0x5040, 0xc81d, 0x507f, 0xc81d, 0x21, 0 - .dw 0x50c0, 0xc81d, 0x50ff, 0xc81d, 0x21, 0 - .dw 0x5140, 0xc81d, 0x517f, 0xc81d, 0x21, 0 - .dw 0x51c0, 0xc81d, 0x51ff, 0xc81d, 0x21, 0 - .dw 0x5240, 0xc81d, 0x527f, 0xc81d, 0x21, 0 - .dw 0x52c0, 0xc81d, 0x52ff, 0xc81d, 0x21, 0 - .dw 0x5340, 0xc81d, 0x537f, 0xc81d, 0x21, 0 - .dw 0x53c0, 0xc81d, 0x53ff, 0xc81d, 0x21, 0 - .dw 0x5440, 0xc81d, 0x547f, 0xc81d, 0x21, 0 - .dw 0x54c0, 0xc81d, 0x54ff, 0xc81d, 0x21, 0 - .dw 0x5540, 0xc81d, 0x557f, 0xc81d, 0x21, 0 - .dw 0x55c0, 0xc81d, 0x55ff, 0xc81d, 0x21, 0 - .dw 0x5640, 0xc81d, 0x567f, 0xc81d, 0x21, 0 - .dw 0x56c0, 0xc81d, 0x56ff, 0xc81d, 0x21, 0 - .dw 0x5740, 0xc81d, 0x577f, 0xc81d, 0x21, 0 - .dw 0x57c0, 0xc81d, 0x57ff, 0xc81d, 0x21, 0 - .dw 0x5840, 0xc81d, 0x587f, 0xc81d, 0x21, 0 - .dw 0x58c0, 0xc81d, 0x58ff, 0xc81d, 0x21, 0 - .dw 0x5940, 0xc81d, 0x597f, 0xc81d, 0x21, 0 - .dw 0x59c0, 0xc81d, 0x5fff, 0xc81d, 0x21, 0 - .dw 0x6040, 0xc81d, 0x607f, 0xc81d, 0x21, 0 - .dw 0x60c0, 0xc81d, 0x60ff, 0xc81d, 0x21, 0 - .dw 0x6140, 0xc81d, 0x617f, 0xc81d, 0x21, 0 - .dw 0x61c0, 0xc81d, 0x61ff, 0xc81d, 0x21, 0 - .dw 0x6240, 0xc81d, 0x627f, 0xc81d, 0x21, 0 - .dw 0x62c0, 0xc81d, 0x62ff, 0xc81d, 0x21, 0 - .dw 0x6340, 0xc81d, 0x637f, 0xc81d, 0x21, 0 - .dw 0x63c0, 0xc81d, 0x63ff, 0xc81d, 0x21, 0 - .dw 0x6440, 0xc81d, 0x647f, 0xc81d, 0x21, 0 - .dw 0x64c0, 0xc81d, 0x64ff, 0xc81d, 0x21, 0 - .dw 0x6540, 0xc81d, 0x657f, 0xc81d, 0x21, 0 - .dw 0x65c0, 0xc81d, 0x65ff, 0xc81d, 0x21, 0 - .dw 0x6640, 0xc81d, 0x667f, 0xc81d, 0x21, 0 - .dw 0x66c0, 0xc81d, 0x66ff, 0xc81d, 0x21, 0 - .dw 0x6740, 0xc81d, 0x677f, 0xc81d, 0x21, 0 - .dw 0x67c0, 0xc81d, 0x67ff, 0xc81d, 0x21, 0 - .dw 0x6840, 0xc81d, 0x687f, 0xc81d, 0x21, 0 - .dw 0x68c0, 0xc81d, 0x68ff, 0xc81d, 0x21, 0 - .dw 0x6940, 0xc81d, 0x697f, 0xc81d, 0x21, 0 - .dw 0x69c0, 0xc81d, 0x69ff, 0xc81d, 0x21, 0 - .dw 0x6a40, 0xc81d, 0x6a7f, 0xc81d, 0x21, 0 - .dw 0x6ac0, 0xc81d, 0x6aff, 0xc81d, 0x21, 0 - .dw 0x6b40, 0xc81d, 0x6b7f, 0xc81d, 0x21, 0 - .dw 0x6bc0, 0xc81d, 0x6bff, 0xc81d, 0x21, 0 - .dw 0x6c40, 0xc81d, 0x6c7f, 0xc81d, 0x21, 0 - .dw 0x6cc0, 0xc81d, 0x6cff, 0xc81d, 0x21, 0 - .dw 0x6d40, 0xc81d, 0x6d7f, 0xc81d, 0x21, 0 - .dw 0x6dc0, 0xc81d, 0x6dff, 0xc81d, 0x21, 0 - .dw 0x6e40, 0xc81d, 0x6e7f, 0xc81d, 0x21, 0 - .dw 0x6ec0, 0xc81d, 0x6eff, 0xc81d, 0x21, 0 - .dw 0x6f40, 0xc81d, 0x6f7f, 0xc81d, 0x21, 0 - .dw 0x6fc0, 0xc81d, 0x6fff, 0xc81d, 0x21, 0 - .dw 0x7040, 0xc81d, 0x707f, 0xc81d, 0x21, 0 - .dw 0x70c0, 0xc81d, 0x70ff, 0xc81d, 0x21, 0 - .dw 0x7140, 0xc81d, 0x717f, 0xc81d, 0x21, 0 - .dw 0x71c0, 0xc81d, 0x71ff, 0xc81d, 0x21, 0 - .dw 0x7240, 0xc81d, 0x727f, 0xc81d, 0x21, 0 - .dw 0x72c0, 0xc81d, 0x72ff, 0xc81d, 0x21, 0 - .dw 0x7340, 0xc81d, 0x737f, 0xc81d, 0x21, 0 - .dw 0x73c0, 0xc81d, 0x73ff, 0xc81d, 0x21, 0 - .dw 0x7440, 0xc81d, 0x747f, 0xc81d, 0x21, 0 - .dw 0x74c0, 0xc81d, 0x74ff, 0xc81d, 0x21, 0 - .dw 0x7540, 0xc81d, 0x757f, 0xc81d, 0x21, 0 - .dw 0x75c0, 0xc81d, 0x75ff, 0xc81d, 0x21, 0 - .dw 0x7640, 0xc81d, 0x767f, 0xc81d, 0x21, 0 - .dw 0x76c0, 0xc81d, 0x76ff, 0xc81d, 0x21, 0 - .dw 0x7740, 0xc81d, 0x777f, 0xc81d, 0x21, 0 - .dw 0x77c0, 0xc81d, 0x77ff, 0xc81d, 0x21, 0 - .dw 0x7840, 0xc81d, 0x787f, 0xc81d, 0x21, 0 - .dw 0x78c0, 0xc81d, 0x78ff, 0xc81d, 0x21, 0 - .dw 0x7940, 0xc81d, 0x797f, 0xc81d, 0x21, 0 - .dw 0x79c0, 0xc81d, 0x7fff, 0xc81d, 0x21, 0 - .dw 0x8040, 0xc81d, 0x807f, 0xc81d, 0x21, 0 - .dw 0x80c0, 0xc81d, 0x80ff, 0xc81d, 0x21, 0 - .dw 0x8140, 0xc81d, 0x817f, 0xc81d, 0x21, 0 - .dw 0x81c0, 0xc81d, 0x81ff, 0xc81d, 0x21, 0 - .dw 0x8240, 0xc81d, 0x827f, 0xc81d, 0x21, 0 - .dw 0x82c0, 0xc81d, 0x82ff, 0xc81d, 0x21, 0 - .dw 0x8340, 0xc81d, 0x837f, 0xc81d, 0x21, 0 - .dw 0x83c0, 0xc81d, 0x83ff, 0xc81d, 0x21, 0 - .dw 0x8440, 0xc81d, 0x847f, 0xc81d, 0x21, 0 - .dw 0x84c0, 0xc81d, 0x84ff, 0xc81d, 0x21, 0 - .dw 0x8540, 0xc81d, 0x857f, 0xc81d, 0x21, 0 - .dw 0x85c0, 0xc81d, 0x85ff, 0xc81d, 0x21, 0 - .dw 0x8640, 0xc81d, 0x867f, 0xc81d, 0x21, 0 - .dw 0x86c0, 0xc81d, 0x86ff, 0xc81d, 0x21, 0 - .dw 0x8740, 0xc81d, 0x877f, 0xc81d, 0x21, 0 - .dw 0x87c0, 0xc81d, 0x87ff, 0xc81d, 0x21, 0 - .dw 0x8840, 0xc81d, 0x887f, 0xc81d, 0x21, 0 - .dw 0x88c0, 0xc81d, 0x88ff, 0xc81d, 0x21, 0 - .dw 0x8940, 0xc81d, 0x897f, 0xc81d, 0x21, 0 - .dw 0x89c0, 0xc81d, 0x89ff, 0xc81d, 0x21, 0 - .dw 0x8a40, 0xc81d, 0x8a7f, 0xc81d, 0x21, 0 - .dw 0x8ac0, 0xc81d, 0x8aff, 0xc81d, 0x21, 0 - .dw 0x8b40, 0xc81d, 0x8b7f, 0xc81d, 0x21, 0 - .dw 0x8bc0, 0xc81d, 0x8bff, 0xc81d, 0x21, 0 - .dw 0x8c40, 0xc81d, 0x8c7f, 0xc81d, 0x21, 0 - .dw 0x8cc0, 0xc81d, 0x8cff, 0xc81d, 0x21, 0 - .dw 0x8d40, 0xc81d, 0x8d7f, 0xc81d, 0x21, 0 - .dw 0x8dc0, 0xc81d, 0x8dff, 0xc81d, 0x21, 0 - .dw 0x8e40, 0xc81d, 0x8e7f, 0xc81d, 0x21, 0 - .dw 0x8ec0, 0xc81d, 0x8eff, 0xc81d, 0x21, 0 - .dw 0x8f40, 0xc81d, 0x8f7f, 0xc81d, 0x21, 0 - .dw 0x8fc0, 0xc81d, 0x8fff, 0xc81d, 0x21, 0 - .dw 0x9040, 0xc81d, 0x907f, 0xc81d, 0x21, 0 - .dw 0x90c0, 0xc81d, 0x90ff, 0xc81d, 0x21, 0 - .dw 0x9140, 0xc81d, 0x917f, 0xc81d, 0x21, 0 - .dw 0x91c0, 0xc81d, 0x91ff, 0xc81d, 0x21, 0 - .dw 0x9240, 0xc81d, 0x927f, 0xc81d, 0x21, 0 - .dw 0x92c0, 0xc81d, 0x92ff, 0xc81d, 0x21, 0 - .dw 0x9340, 0xc81d, 0x937f, 0xc81d, 0x21, 0 - .dw 0x93c0, 0xc81d, 0x93ff, 0xc81d, 0x21, 0 - .dw 0x9440, 0xc81d, 0x947f, 0xc81d, 0x21, 0 - .dw 0x94c0, 0xc81d, 0x94ff, 0xc81d, 0x21, 0 - .dw 0x9540, 0xc81d, 0x957f, 0xc81d, 0x21, 0 - .dw 0x95c0, 0xc81d, 0x95ff, 0xc81d, 0x21, 0 - .dw 0x9640, 0xc81d, 0x967f, 0xc81d, 0x21, 0 - .dw 0x96c0, 0xc81d, 0x96ff, 0xc81d, 0x21, 0 - .dw 0x9740, 0xc81d, 0x977f, 0xc81d, 0x21, 0 - .dw 0x97c0, 0xc81d, 0x97ff, 0xc81d, 0x21, 0 - .dw 0x9840, 0xc81d, 0x987f, 0xc81d, 0x21, 0 - .dw 0x98c0, 0xc81d, 0x98ff, 0xc81d, 0x21, 0 - .dw 0x9940, 0xc81d, 0x997f, 0xc81d, 0x21, 0 - .dw 0x99c0, 0xc81d, 0x9fff, 0xc81d, 0x21, 0 - .dw 0xa040, 0xc81d, 0xa07f, 0xc81d, 0x21, 0 - .dw 0xa0c0, 0xc81d, 0xa0ff, 0xc81d, 0x21, 0 - .dw 0xa140, 0xc81d, 0xa17f, 0xc81d, 0x21, 0 - .dw 0xa1c0, 0xc81d, 0xa1ff, 0xc81d, 0x21, 0 - .dw 0xa240, 0xc81d, 0xa27f, 0xc81d, 0x21, 0 - .dw 0xa2c0, 0xc81d, 0xa2ff, 0xc81d, 0x21, 0 - .dw 0xa340, 0xc81d, 0xa37f, 0xc81d, 0x21, 0 - .dw 0xa3c0, 0xc81d, 0xa3ff, 0xc81d, 0x21, 0 - .dw 0xa440, 0xc81d, 0xa47f, 0xc81d, 0x21, 0 - .dw 0xa4c0, 0xc81d, 0xa4ff, 0xc81d, 0x21, 0 - .dw 0xa540, 0xc81d, 0xa57f, 0xc81d, 0x21, 0 - .dw 0xa5c0, 0xc81d, 0xa5ff, 0xc81d, 0x21, 0 - .dw 0xa640, 0xc81d, 0xa67f, 0xc81d, 0x21, 0 - .dw 0xa6c0, 0xc81d, 0xa6ff, 0xc81d, 0x21, 0 - .dw 0xa740, 0xc81d, 0xa77f, 0xc81d, 0x21, 0 - .dw 0xa7c0, 0xc81d, 0xa7ff, 0xc81d, 0x21, 0 - .dw 0xa840, 0xc81d, 0xa87f, 0xc81d, 0x21, 0 - .dw 0xa8c0, 0xc81d, 0xa8ff, 0xc81d, 0x21, 0 - .dw 0xa940, 0xc81d, 0xa97f, 0xc81d, 0x21, 0 - .dw 0xa9c0, 0xc81d, 0xa9ff, 0xc81d, 0x21, 0 - .dw 0xaa40, 0xc81d, 0xaa7f, 0xc81d, 0x21, 0 - .dw 0xaac0, 0xc81d, 0xaaff, 0xc81d, 0x21, 0 - .dw 0xab40, 0xc81d, 0xab7f, 0xc81d, 0x21, 0 - .dw 0xabc0, 0xc81d, 0xabff, 0xc81d, 0x21, 0 - .dw 0xac40, 0xc81d, 0xac7f, 0xc81d, 0x21, 0 - .dw 0xacc0, 0xc81d, 0xacff, 0xc81d, 0x21, 0 - .dw 0xad40, 0xc81d, 0xad7f, 0xc81d, 0x21, 0 - .dw 0xadc0, 0xc81d, 0xadff, 0xc81d, 0x21, 0 - .dw 0xae40, 0xc81d, 0xae7f, 0xc81d, 0x21, 0 - .dw 0xaec0, 0xc81d, 0xaeff, 0xc81d, 0x21, 0 - .dw 0xaf40, 0xc81d, 0xaf7f, 0xc81d, 0x21, 0 - .dw 0xafc0, 0xc81d, 0xafff, 0xc81d, 0x21, 0 - .dw 0xb040, 0xc81d, 0xb07f, 0xc81d, 0x21, 0 - .dw 0xb0c0, 0xc81d, 0xb0ff, 0xc81d, 0x21, 0 - .dw 0xb140, 0xc81d, 0xb17f, 0xc81d, 0x21, 0 - .dw 0xb1c0, 0xc81d, 0xb1ff, 0xc81d, 0x21, 0 - .dw 0xb240, 0xc81d, 0xb27f, 0xc81d, 0x21, 0 - .dw 0xb2c0, 0xc81d, 0xb2ff, 0xc81d, 0x21, 0 - .dw 0xb340, 0xc81d, 0xb37f, 0xc81d, 0x21, 0 - .dw 0xb3c0, 0xc81d, 0xb3ff, 0xc81d, 0x21, 0 - .dw 0xb440, 0xc81d, 0xb47f, 0xc81d, 0x21, 0 - .dw 0xb4c0, 0xc81d, 0xb4ff, 0xc81d, 0x21, 0 - .dw 0xb540, 0xc81d, 0xb57f, 0xc81d, 0x21, 0 - .dw 0xb5c0, 0xc81d, 0xb5ff, 0xc81d, 0x21, 0 - .dw 0xb640, 0xc81d, 0xb67f, 0xc81d, 0x21, 0 - .dw 0xb6c0, 0xc81d, 0xb6ff, 0xc81d, 0x21, 0 - .dw 0xb740, 0xc81d, 0xb77f, 0xc81d, 0x21, 0 - .dw 0xb7c0, 0xc81d, 0xb7ff, 0xc81d, 0x21, 0 - .dw 0xb840, 0xc81d, 0xb87f, 0xc81d, 0x21, 0 - .dw 0xb8c0, 0xc81d, 0xb8ff, 0xc81d, 0x21, 0 - .dw 0xb940, 0xc81d, 0xb97f, 0xc81d, 0x21, 0 - .dw 0xb9c0, 0xc81d, 0xbfff, 0xc81d, 0x21, 0 - .dw 0xc040, 0xc81d, 0xc07f, 0xc81d, 0x21, 0 - .dw 0xc0c0, 0xc81d, 0xc0ff, 0xc81d, 0x21, 0 - .dw 0xc140, 0xc81d, 0xc17f, 0xc81d, 0x21, 0 - .dw 0xc1c0, 0xc81d, 0xc1ff, 0xc81d, 0x21, 0 - .dw 0xc240, 0xc81d, 0xc27f, 0xc81d, 0x21, 0 - .dw 0xc2c0, 0xc81d, 0xc2ff, 0xc81d, 0x21, 0 - .dw 0xc340, 0xc81d, 0xc37f, 0xc81d, 0x21, 0 - .dw 0xc3c0, 0xc81d, 0xc3ff, 0xc81d, 0x21, 0 - .dw 0xc440, 0xc81d, 0xc47f, 0xc81d, 0x21, 0 - .dw 0xc4c0, 0xc81d, 0xc4ff, 0xc81d, 0x21, 0 - .dw 0xc540, 0xc81d, 0xc57f, 0xc81d, 0x21, 0 - .dw 0xc5c0, 0xc81d, 0xc5ff, 0xc81d, 0x21, 0 - .dw 0xc640, 0xc81d, 0xc67f, 0xc81d, 0x21, 0 - .dw 0xc6c0, 0xc81d, 0xc6ff, 0xc81d, 0x21, 0 - .dw 0xc740, 0xc81d, 0xc77f, 0xc81d, 0x21, 0 - .dw 0xc7c0, 0xc81d, 0xc7ff, 0xc81d, 0x21, 0 - .dw 0xc840, 0xc81d, 0xc87f, 0xc81d, 0x21, 0 - .dw 0xc8c0, 0xc81d, 0xc8ff, 0xc81d, 0x21, 0 - .dw 0xc940, 0xc81d, 0xc97f, 0xc81d, 0x21, 0 - .dw 0xc9c0, 0xc81d, 0xc9ff, 0xc81d, 0x21, 0 - .dw 0xca40, 0xc81d, 0xca7f, 0xc81d, 0x21, 0 - .dw 0xcac0, 0xc81d, 0xcaff, 0xc81d, 0x21, 0 - .dw 0xcb40, 0xc81d, 0xcb7f, 0xc81d, 0x21, 0 - .dw 0xcbc0, 0xc81d, 0xcbff, 0xc81d, 0x21, 0 - .dw 0xcc40, 0xc81d, 0xcc7f, 0xc81d, 0x21, 0 - .dw 0xccc0, 0xc81d, 0xccff, 0xc81d, 0x21, 0 - .dw 0xcd40, 0xc81d, 0xcd7f, 0xc81d, 0x21, 0 - .dw 0xcdc0, 0xc81d, 0xcdff, 0xc81d, 0x21, 0 - .dw 0xce40, 0xc81d, 0xce7f, 0xc81d, 0x21, 0 - .dw 0xcec0, 0xc81d, 0xceff, 0xc81d, 0x21, 0 - .dw 0xcf40, 0xc81d, 0xcf7f, 0xc81d, 0x21, 0 - .dw 0xcfc0, 0xc81d, 0xcfff, 0xc81d, 0x21, 0 - .dw 0xd040, 0xc81d, 0xd07f, 0xc81d, 0x21, 0 - .dw 0xd0c0, 0xc81d, 0xd0ff, 0xc81d, 0x21, 0 - .dw 0xd140, 0xc81d, 0xd17f, 0xc81d, 0x21, 0 - .dw 0xd1c0, 0xc81d, 0xd1ff, 0xc81d, 0x21, 0 - .dw 0xd240, 0xc81d, 0xd27f, 0xc81d, 0x21, 0 - .dw 0xd2c0, 0xc81d, 0xd2ff, 0xc81d, 0x21, 0 - .dw 0xd340, 0xc81d, 0xd37f, 0xc81d, 0x21, 0 - .dw 0xd3c0, 0xc81d, 0xd3ff, 0xc81d, 0x21, 0 - .dw 0xd440, 0xc81d, 0xd47f, 0xc81d, 0x21, 0 - .dw 0xd4c0, 0xc81d, 0xd4ff, 0xc81d, 0x21, 0 - .dw 0xd540, 0xc81d, 0xd57f, 0xc81d, 0x21, 0 - .dw 0xd5c0, 0xc81d, 0xd5ff, 0xc81d, 0x21, 0 - .dw 0xd640, 0xc81d, 0xd67f, 0xc81d, 0x21, 0 - .dw 0xd6c0, 0xc81d, 0xd6ff, 0xc81d, 0x21, 0 - .dw 0xd740, 0xc81d, 0xd77f, 0xc81d, 0x21, 0 - .dw 0xd7c0, 0xc81d, 0xd7ff, 0xc81d, 0x21, 0 - .dw 0xd840, 0xc81d, 0xd87f, 0xc81d, 0x21, 0 - .dw 0xd8c0, 0xc81d, 0xd8ff, 0xc81d, 0x21, 0 - .dw 0xd940, 0xc81d, 0xd97f, 0xc81d, 0x21, 0 - .dw 0xd9c0, 0xc81d, 0xdfff, 0xc81d, 0x21, 0 - .dw 0xe040, 0xc81d, 0xe07f, 0xc81d, 0x21, 0 - .dw 0xe0c0, 0xc81d, 0xe0ff, 0xc81d, 0x21, 0 - .dw 0xe140, 0xc81d, 0xe17f, 0xc81d, 0x21, 0 - .dw 0xe1c0, 0xc81d, 0xe1ff, 0xc81d, 0x21, 0 - .dw 0xe240, 0xc81d, 0xe27f, 0xc81d, 0x21, 0 - .dw 0xe2c0, 0xc81d, 0xe2ff, 0xc81d, 0x21, 0 - .dw 0xe340, 0xc81d, 0xe37f, 0xc81d, 0x21, 0 - .dw 0xe3c0, 0xc81d, 0xe3ff, 0xc81d, 0x21, 0 - .dw 0xe440, 0xc81d, 0xe47f, 0xc81d, 0x21, 0 - .dw 0xe4c0, 0xc81d, 0xe4ff, 0xc81d, 0x21, 0 - .dw 0xe540, 0xc81d, 0xe57f, 0xc81d, 0x21, 0 - .dw 0xe5c0, 0xc81d, 0xe5ff, 0xc81d, 0x21, 0 - .dw 0xe640, 0xc81d, 0xe67f, 0xc81d, 0x21, 0 - .dw 0xe6c0, 0xc81d, 0xe6ff, 0xc81d, 0x21, 0 - .dw 0xe740, 0xc81d, 0xe77f, 0xc81d, 0x21, 0 - .dw 0xe7c0, 0xc81d, 0xe7ff, 0xc81d, 0x21, 0 - .dw 0xe840, 0xc81d, 0xe87f, 0xc81d, 0x21, 0 - .dw 0xe8c0, 0xc81d, 0xe8ff, 0xc81d, 0x21, 0 - .dw 0xe940, 0xc81d, 0xe97f, 0xc81d, 0x21, 0 - .dw 0xe9c0, 0xc81d, 0xe9ff, 0xc81d, 0x21, 0 - .dw 0xea40, 0xc81d, 0xea7f, 0xc81d, 0x21, 0 - .dw 0xeac0, 0xc81d, 0xeaff, 0xc81d, 0x21, 0 - .dw 0xeb40, 0xc81d, 0xeb7f, 0xc81d, 0x21, 0 - .dw 0xebc0, 0xc81d, 0xebff, 0xc81d, 0x21, 0 - .dw 0xec40, 0xc81d, 0xec7f, 0xc81d, 0x21, 0 - .dw 0xecc0, 0xc81d, 0xecff, 0xc81d, 0x21, 0 - .dw 0xed40, 0xc81d, 0xed7f, 0xc81d, 0x21, 0 - .dw 0xedc0, 0xc81d, 0xedff, 0xc81d, 0x21, 0 - .dw 0xee40, 0xc81d, 0xee7f, 0xc81d, 0x21, 0 - .dw 0xeec0, 0xc81d, 0xeeff, 0xc81d, 0x21, 0 - .dw 0xef40, 0xc81d, 0xef7f, 0xc81d, 0x21, 0 - .dw 0xefc0, 0xc81d, 0xefff, 0xc81d, 0x21, 0 - .dw 0xf040, 0xc81d, 0xf07f, 0xc81d, 0x21, 0 - .dw 0xf0c0, 0xc81d, 0xf0ff, 0xc81d, 0x21, 0 - .dw 0xf140, 0xc81d, 0xf17f, 0xc81d, 0x21, 0 - .dw 0xf1c0, 0xc81d, 0xf1ff, 0xc81d, 0x21, 0 - .dw 0xf240, 0xc81d, 0xf27f, 0xc81d, 0x21, 0 - .dw 0xf2c0, 0xc81d, 0xf2ff, 0xc81d, 0x21, 0 - .dw 0xf340, 0xc81d, 0xf37f, 0xc81d, 0x21, 0 - .dw 0xf3c0, 0xc81d, 0xf3ff, 0xc81d, 0x21, 0 - .dw 0xf440, 0xc81d, 0xf47f, 0xc81d, 0x21, 0 - .dw 0xf4c0, 0xc81d, 0xf4ff, 0xc81d, 0x21, 0 - .dw 0xf540, 0xc81d, 0xf57f, 0xc81d, 0x21, 0 - .dw 0xf5c0, 0xc81d, 0xf5ff, 0xc81d, 0x21, 0 - .dw 0xf640, 0xc81d, 0xf67f, 0xc81d, 0x21, 0 - .dw 0xf6c0, 0xc81d, 0xf6ff, 0xc81d, 0x21, 0 - .dw 0xf740, 0xc81d, 0xf77f, 0xc81d, 0x21, 0 - .dw 0xf7c0, 0xc81d, 0xf7ff, 0xc81d, 0x21, 0 - .dw 0xf840, 0xc81d, 0xf87f, 0xc81d, 0x21, 0 - .dw 0xf8c0, 0xc81d, 0xf8ff, 0xc81d, 0x21, 0 - .dw 0xf940, 0xc81d, 0xf97f, 0xc81d, 0x21, 0 - .dw 0xf9c0, 0xc81d, 0xffff, 0xc81d, 0x21, 0 - .dw 0x0040, 0xc81e, 0x007f, 0xc81e, 0x21, 0 - .dw 0x00c0, 0xc81e, 0x00ff, 0xc81e, 0x21, 0 - .dw 0x0140, 0xc81e, 0x017f, 0xc81e, 0x21, 0 - .dw 0x01c0, 0xc81e, 0x01ff, 0xc81e, 0x21, 0 - .dw 0x0240, 0xc81e, 0x027f, 0xc81e, 0x21, 0 - .dw 0x02c0, 0xc81e, 0x02ff, 0xc81e, 0x21, 0 - .dw 0x0340, 0xc81e, 0x037f, 0xc81e, 0x21, 0 - .dw 0x03c0, 0xc81e, 0x03ff, 0xc81e, 0x21, 0 - .dw 0x0440, 0xc81e, 0x047f, 0xc81e, 0x21, 0 - .dw 0x04c0, 0xc81e, 0x04ff, 0xc81e, 0x21, 0 - .dw 0x0540, 0xc81e, 0x057f, 0xc81e, 0x21, 0 - .dw 0x05c0, 0xc81e, 0x05ff, 0xc81e, 0x21, 0 - .dw 0x0640, 0xc81e, 0x067f, 0xc81e, 0x21, 0 - .dw 0x06c0, 0xc81e, 0x06ff, 0xc81e, 0x21, 0 - .dw 0x0740, 0xc81e, 0x077f, 0xc81e, 0x21, 0 - .dw 0x07c0, 0xc81e, 0x07ff, 0xc81e, 0x21, 0 - .dw 0x0840, 0xc81e, 0x087f, 0xc81e, 0x21, 0 - .dw 0x08c0, 0xc81e, 0x08ff, 0xc81e, 0x21, 0 - .dw 0x0940, 0xc81e, 0x097f, 0xc81e, 0x21, 0 - .dw 0x09c0, 0xc81e, 0x09ff, 0xc81e, 0x21, 0 - .dw 0x0a40, 0xc81e, 0x0a7f, 0xc81e, 0x21, 0 - .dw 0x0ac0, 0xc81e, 0x0aff, 0xc81e, 0x21, 0 - .dw 0x0b40, 0xc81e, 0x0b7f, 0xc81e, 0x21, 0 - .dw 0x0bc0, 0xc81e, 0x0bff, 0xc81e, 0x21, 0 - .dw 0x0c40, 0xc81e, 0x0c7f, 0xc81e, 0x21, 0 - .dw 0x0cc0, 0xc81e, 0x0cff, 0xc81e, 0x21, 0 - .dw 0x0d40, 0xc81e, 0x0d7f, 0xc81e, 0x21, 0 - .dw 0x0dc0, 0xc81e, 0x0dff, 0xc81e, 0x21, 0 - .dw 0x0e40, 0xc81e, 0x0e7f, 0xc81e, 0x21, 0 - .dw 0x0ec0, 0xc81e, 0x0eff, 0xc81e, 0x21, 0 - .dw 0x0f40, 0xc81e, 0x0f7f, 0xc81e, 0x21, 0 - .dw 0x0fc0, 0xc81e, 0x0fff, 0xc81e, 0x21, 0 - .dw 0x1040, 0xc81e, 0x107f, 0xc81e, 0x21, 0 - .dw 0x10c0, 0xc81e, 0x10ff, 0xc81e, 0x21, 0 - .dw 0x1140, 0xc81e, 0x117f, 0xc81e, 0x21, 0 - .dw 0x11c0, 0xc81e, 0x11ff, 0xc81e, 0x21, 0 - .dw 0x1240, 0xc81e, 0x127f, 0xc81e, 0x21, 0 - .dw 0x12c0, 0xc81e, 0x12ff, 0xc81e, 0x21, 0 - .dw 0x1340, 0xc81e, 0x137f, 0xc81e, 0x21, 0 - .dw 0x13c0, 0xc81e, 0x13ff, 0xc81e, 0x21, 0 - .dw 0x1440, 0xc81e, 0x147f, 0xc81e, 0x21, 0 - .dw 0x14c0, 0xc81e, 0x14ff, 0xc81e, 0x21, 0 - .dw 0x1540, 0xc81e, 0x157f, 0xc81e, 0x21, 0 - .dw 0x15c0, 0xc81e, 0x15ff, 0xc81e, 0x21, 0 - .dw 0x1640, 0xc81e, 0x167f, 0xc81e, 0x21, 0 - .dw 0x16c0, 0xc81e, 0x16ff, 0xc81e, 0x21, 0 - .dw 0x1740, 0xc81e, 0x177f, 0xc81e, 0x21, 0 - .dw 0x17c0, 0xc81e, 0x17ff, 0xc81e, 0x21, 0 - .dw 0x1840, 0xc81e, 0x187f, 0xc81e, 0x21, 0 - .dw 0x18c0, 0xc81e, 0x18ff, 0xc81e, 0x21, 0 - .dw 0x1940, 0xc81e, 0x197f, 0xc81e, 0x21, 0 - .dw 0x19c0, 0xc81e, 0x1fff, 0xc81e, 0x21, 0 - .dw 0x2040, 0xc81e, 0x207f, 0xc81e, 0x21, 0 - .dw 0x20c0, 0xc81e, 0x20ff, 0xc81e, 0x21, 0 - .dw 0x2140, 0xc81e, 0x217f, 0xc81e, 0x21, 0 - .dw 0x21c0, 0xc81e, 0x21ff, 0xc81e, 0x21, 0 - .dw 0x2240, 0xc81e, 0x227f, 0xc81e, 0x21, 0 - .dw 0x22c0, 0xc81e, 0x22ff, 0xc81e, 0x21, 0 - .dw 0x2340, 0xc81e, 0x237f, 0xc81e, 0x21, 0 - .dw 0x23c0, 0xc81e, 0x23ff, 0xc81e, 0x21, 0 - .dw 0x2440, 0xc81e, 0x247f, 0xc81e, 0x21, 0 - .dw 0x24c0, 0xc81e, 0x24ff, 0xc81e, 0x21, 0 - .dw 0x2540, 0xc81e, 0x257f, 0xc81e, 0x21, 0 - .dw 0x25c0, 0xc81e, 0x25ff, 0xc81e, 0x21, 0 - .dw 0x2640, 0xc81e, 0x267f, 0xc81e, 0x21, 0 - .dw 0x26c0, 0xc81e, 0x26ff, 0xc81e, 0x21, 0 - .dw 0x2740, 0xc81e, 0x277f, 0xc81e, 0x21, 0 - .dw 0x27c0, 0xc81e, 0x27ff, 0xc81e, 0x21, 0 - .dw 0x2840, 0xc81e, 0x287f, 0xc81e, 0x21, 0 - .dw 0x28c0, 0xc81e, 0x28ff, 0xc81e, 0x21, 0 - .dw 0x2940, 0xc81e, 0x297f, 0xc81e, 0x21, 0 - .dw 0x29c0, 0xc81e, 0x29ff, 0xc81e, 0x21, 0 - .dw 0x2a40, 0xc81e, 0x2a7f, 0xc81e, 0x21, 0 - .dw 0x2ac0, 0xc81e, 0x2aff, 0xc81e, 0x21, 0 - .dw 0x2b40, 0xc81e, 0x2b7f, 0xc81e, 0x21, 0 - .dw 0x2bc0, 0xc81e, 0x2bff, 0xc81e, 0x21, 0 - .dw 0x2c40, 0xc81e, 0x2c7f, 0xc81e, 0x21, 0 - .dw 0x2cc0, 0xc81e, 0x2cff, 0xc81e, 0x21, 0 - .dw 0x2d40, 0xc81e, 0x2d7f, 0xc81e, 0x21, 0 - .dw 0x2dc0, 0xc81e, 0x2dff, 0xc81e, 0x21, 0 - .dw 0x2e40, 0xc81e, 0x2e7f, 0xc81e, 0x21, 0 - .dw 0x2ec0, 0xc81e, 0x2eff, 0xc81e, 0x21, 0 - .dw 0x2f40, 0xc81e, 0x2f7f, 0xc81e, 0x21, 0 - .dw 0x2fc0, 0xc81e, 0x2fff, 0xc81e, 0x21, 0 - .dw 0x3040, 0xc81e, 0x307f, 0xc81e, 0x21, 0 - .dw 0x30c0, 0xc81e, 0x30ff, 0xc81e, 0x21, 0 - .dw 0x3140, 0xc81e, 0x317f, 0xc81e, 0x21, 0 - .dw 0x31c0, 0xc81e, 0x31ff, 0xc81e, 0x21, 0 - .dw 0x3240, 0xc81e, 0x327f, 0xc81e, 0x21, 0 - .dw 0x32c0, 0xc81e, 0x32ff, 0xc81e, 0x21, 0 - .dw 0x3340, 0xc81e, 0x337f, 0xc81e, 0x21, 0 - .dw 0x33c0, 0xc81e, 0x33ff, 0xc81e, 0x21, 0 - .dw 0x3440, 0xc81e, 0x347f, 0xc81e, 0x21, 0 - .dw 0x34c0, 0xc81e, 0x34ff, 0xc81e, 0x21, 0 - .dw 0x3540, 0xc81e, 0x357f, 0xc81e, 0x21, 0 - .dw 0x35c0, 0xc81e, 0x35ff, 0xc81e, 0x21, 0 - .dw 0x3640, 0xc81e, 0x367f, 0xc81e, 0x21, 0 - .dw 0x36c0, 0xc81e, 0x36ff, 0xc81e, 0x21, 0 - .dw 0x3740, 0xc81e, 0x377f, 0xc81e, 0x21, 0 - .dw 0x37c0, 0xc81e, 0x37ff, 0xc81e, 0x21, 0 - .dw 0x3840, 0xc81e, 0x387f, 0xc81e, 0x21, 0 - .dw 0x38c0, 0xc81e, 0x38ff, 0xc81e, 0x21, 0 - .dw 0x3940, 0xc81e, 0x397f, 0xc81e, 0x21, 0 - .dw 0x39c0, 0xc81e, 0x3fff, 0xc81e, 0x21, 0 - .dw 0x4040, 0xc81e, 0x407f, 0xc81e, 0x21, 0 - .dw 0x40c0, 0xc81e, 0x40ff, 0xc81e, 0x21, 0 - .dw 0x4140, 0xc81e, 0x417f, 0xc81e, 0x21, 0 - .dw 0x41c0, 0xc81e, 0x41ff, 0xc81e, 0x21, 0 - .dw 0x4240, 0xc81e, 0x427f, 0xc81e, 0x21, 0 - .dw 0x42c0, 0xc81e, 0x42ff, 0xc81e, 0x21, 0 - .dw 0x4340, 0xc81e, 0x437f, 0xc81e, 0x21, 0 - .dw 0x43c0, 0xc81e, 0x43ff, 0xc81e, 0x21, 0 - .dw 0x4440, 0xc81e, 0x447f, 0xc81e, 0x21, 0 - .dw 0x44c0, 0xc81e, 0x44ff, 0xc81e, 0x21, 0 - .dw 0x4540, 0xc81e, 0x457f, 0xc81e, 0x21, 0 - .dw 0x45c0, 0xc81e, 0x45ff, 0xc81e, 0x21, 0 - .dw 0x4640, 0xc81e, 0x467f, 0xc81e, 0x21, 0 - .dw 0x46c0, 0xc81e, 0x46ff, 0xc81e, 0x21, 0 - .dw 0x4740, 0xc81e, 0x477f, 0xc81e, 0x21, 0 - .dw 0x47c0, 0xc81e, 0x47ff, 0xc81e, 0x21, 0 - .dw 0x4840, 0xc81e, 0x487f, 0xc81e, 0x21, 0 - .dw 0x48c0, 0xc81e, 0x48ff, 0xc81e, 0x21, 0 - .dw 0x4940, 0xc81e, 0x497f, 0xc81e, 0x21, 0 - .dw 0x49c0, 0xc81e, 0x49ff, 0xc81e, 0x21, 0 - .dw 0x4a40, 0xc81e, 0x4a7f, 0xc81e, 0x21, 0 - .dw 0x4ac0, 0xc81e, 0x4aff, 0xc81e, 0x21, 0 - .dw 0x4b40, 0xc81e, 0x4b7f, 0xc81e, 0x21, 0 - .dw 0x4bc0, 0xc81e, 0x4bff, 0xc81e, 0x21, 0 - .dw 0x4c40, 0xc81e, 0x4c7f, 0xc81e, 0x21, 0 - .dw 0x4cc0, 0xc81e, 0x4cff, 0xc81e, 0x21, 0 - .dw 0x4d40, 0xc81e, 0x4d7f, 0xc81e, 0x21, 0 - .dw 0x4dc0, 0xc81e, 0x4dff, 0xc81e, 0x21, 0 - .dw 0x4e40, 0xc81e, 0x4e7f, 0xc81e, 0x21, 0 - .dw 0x4ec0, 0xc81e, 0x4eff, 0xc81e, 0x21, 0 - .dw 0x4f40, 0xc81e, 0x4f7f, 0xc81e, 0x21, 0 - .dw 0x4fc0, 0xc81e, 0x4fff, 0xc81e, 0x21, 0 - .dw 0x5040, 0xc81e, 0x507f, 0xc81e, 0x21, 0 - .dw 0x50c0, 0xc81e, 0x50ff, 0xc81e, 0x21, 0 - .dw 0x5140, 0xc81e, 0x517f, 0xc81e, 0x21, 0 - .dw 0x51c0, 0xc81e, 0x51ff, 0xc81e, 0x21, 0 - .dw 0x5240, 0xc81e, 0x527f, 0xc81e, 0x21, 0 - .dw 0x52c0, 0xc81e, 0x52ff, 0xc81e, 0x21, 0 - .dw 0x5340, 0xc81e, 0x537f, 0xc81e, 0x21, 0 - .dw 0x53c0, 0xc81e, 0x53ff, 0xc81e, 0x21, 0 - .dw 0x5440, 0xc81e, 0x547f, 0xc81e, 0x21, 0 - .dw 0x54c0, 0xc81e, 0x54ff, 0xc81e, 0x21, 0 - .dw 0x5540, 0xc81e, 0x557f, 0xc81e, 0x21, 0 - .dw 0x55c0, 0xc81e, 0x55ff, 0xc81e, 0x21, 0 - .dw 0x5640, 0xc81e, 0x567f, 0xc81e, 0x21, 0 - .dw 0x56c0, 0xc81e, 0x56ff, 0xc81e, 0x21, 0 - .dw 0x5740, 0xc81e, 0x577f, 0xc81e, 0x21, 0 - .dw 0x57c0, 0xc81e, 0x57ff, 0xc81e, 0x21, 0 - .dw 0x5840, 0xc81e, 0x587f, 0xc81e, 0x21, 0 - .dw 0x58c0, 0xc81e, 0x58ff, 0xc81e, 0x21, 0 - .dw 0x5940, 0xc81e, 0x597f, 0xc81e, 0x21, 0 - .dw 0x59c0, 0xc81e, 0x5fff, 0xc81e, 0x21, 0 - .dw 0x6040, 0xc81e, 0x607f, 0xc81e, 0x21, 0 - .dw 0x60c0, 0xc81e, 0x60ff, 0xc81e, 0x21, 0 - .dw 0x6140, 0xc81e, 0x617f, 0xc81e, 0x21, 0 - .dw 0x61c0, 0xc81e, 0x61ff, 0xc81e, 0x21, 0 - .dw 0x6240, 0xc81e, 0x627f, 0xc81e, 0x21, 0 - .dw 0x62c0, 0xc81e, 0x62ff, 0xc81e, 0x21, 0 - .dw 0x6340, 0xc81e, 0x637f, 0xc81e, 0x21, 0 - .dw 0x63c0, 0xc81e, 0x63ff, 0xc81e, 0x21, 0 - .dw 0x6440, 0xc81e, 0x647f, 0xc81e, 0x21, 0 - .dw 0x64c0, 0xc81e, 0x64ff, 0xc81e, 0x21, 0 - .dw 0x6540, 0xc81e, 0x657f, 0xc81e, 0x21, 0 - .dw 0x65c0, 0xc81e, 0x65ff, 0xc81e, 0x21, 0 - .dw 0x6640, 0xc81e, 0x667f, 0xc81e, 0x21, 0 - .dw 0x66c0, 0xc81e, 0x66ff, 0xc81e, 0x21, 0 - .dw 0x6740, 0xc81e, 0x677f, 0xc81e, 0x21, 0 - .dw 0x67c0, 0xc81e, 0x67ff, 0xc81e, 0x21, 0 - .dw 0x6840, 0xc81e, 0x687f, 0xc81e, 0x21, 0 - .dw 0x68c0, 0xc81e, 0x68ff, 0xc81e, 0x21, 0 - .dw 0x6940, 0xc81e, 0x697f, 0xc81e, 0x21, 0 - .dw 0x69c0, 0xc81e, 0x69ff, 0xc81e, 0x21, 0 - .dw 0x6a40, 0xc81e, 0x6a7f, 0xc81e, 0x21, 0 - .dw 0x6ac0, 0xc81e, 0x6aff, 0xc81e, 0x21, 0 - .dw 0x6b40, 0xc81e, 0x6b7f, 0xc81e, 0x21, 0 - .dw 0x6bc0, 0xc81e, 0x6bff, 0xc81e, 0x21, 0 - .dw 0x6c40, 0xc81e, 0x6c7f, 0xc81e, 0x21, 0 - .dw 0x6cc0, 0xc81e, 0x6cff, 0xc81e, 0x21, 0 - .dw 0x6d40, 0xc81e, 0x6d7f, 0xc81e, 0x21, 0 - .dw 0x6dc0, 0xc81e, 0x6dff, 0xc81e, 0x21, 0 - .dw 0x6e40, 0xc81e, 0x6e7f, 0xc81e, 0x21, 0 - .dw 0x6ec0, 0xc81e, 0x6eff, 0xc81e, 0x21, 0 - .dw 0x6f40, 0xc81e, 0x6f7f, 0xc81e, 0x21, 0 - .dw 0x6fc0, 0xc81e, 0x6fff, 0xc81e, 0x21, 0 - .dw 0x7040, 0xc81e, 0x707f, 0xc81e, 0x21, 0 - .dw 0x70c0, 0xc81e, 0x70ff, 0xc81e, 0x21, 0 - .dw 0x7140, 0xc81e, 0x717f, 0xc81e, 0x21, 0 - .dw 0x71c0, 0xc81e, 0x71ff, 0xc81e, 0x21, 0 - .dw 0x7240, 0xc81e, 0x727f, 0xc81e, 0x21, 0 - .dw 0x72c0, 0xc81e, 0x72ff, 0xc81e, 0x21, 0 - .dw 0x7340, 0xc81e, 0x737f, 0xc81e, 0x21, 0 - .dw 0x73c0, 0xc81e, 0x73ff, 0xc81e, 0x21, 0 - .dw 0x7440, 0xc81e, 0x747f, 0xc81e, 0x21, 0 - .dw 0x74c0, 0xc81e, 0x74ff, 0xc81e, 0x21, 0 - .dw 0x7540, 0xc81e, 0x757f, 0xc81e, 0x21, 0 - .dw 0x75c0, 0xc81e, 0x75ff, 0xc81e, 0x21, 0 - .dw 0x7640, 0xc81e, 0x767f, 0xc81e, 0x21, 0 - .dw 0x76c0, 0xc81e, 0x76ff, 0xc81e, 0x21, 0 - .dw 0x7740, 0xc81e, 0x777f, 0xc81e, 0x21, 0 - .dw 0x77c0, 0xc81e, 0x77ff, 0xc81e, 0x21, 0 - .dw 0x7840, 0xc81e, 0x787f, 0xc81e, 0x21, 0 - .dw 0x78c0, 0xc81e, 0x78ff, 0xc81e, 0x21, 0 - .dw 0x7940, 0xc81e, 0x797f, 0xc81e, 0x21, 0 - .dw 0x79c0, 0xc81e, 0x7fff, 0xc81e, 0x21, 0 - .dw 0x8040, 0xc81e, 0x807f, 0xc81e, 0x21, 0 - .dw 0x80c0, 0xc81e, 0x80ff, 0xc81e, 0x21, 0 - .dw 0x8140, 0xc81e, 0x817f, 0xc81e, 0x21, 0 - .dw 0x81c0, 0xc81e, 0x81ff, 0xc81e, 0x21, 0 - .dw 0x8240, 0xc81e, 0x827f, 0xc81e, 0x21, 0 - .dw 0x82c0, 0xc81e, 0x82ff, 0xc81e, 0x21, 0 - .dw 0x8340, 0xc81e, 0x837f, 0xc81e, 0x21, 0 - .dw 0x83c0, 0xc81e, 0x83ff, 0xc81e, 0x21, 0 - .dw 0x8440, 0xc81e, 0x847f, 0xc81e, 0x21, 0 - .dw 0x84c0, 0xc81e, 0x84ff, 0xc81e, 0x21, 0 - .dw 0x8540, 0xc81e, 0x857f, 0xc81e, 0x21, 0 - .dw 0x85c0, 0xc81e, 0x85ff, 0xc81e, 0x21, 0 - .dw 0x8640, 0xc81e, 0x867f, 0xc81e, 0x21, 0 - .dw 0x86c0, 0xc81e, 0x86ff, 0xc81e, 0x21, 0 - .dw 0x8740, 0xc81e, 0x877f, 0xc81e, 0x21, 0 - .dw 0x87c0, 0xc81e, 0x87ff, 0xc81e, 0x21, 0 - .dw 0x8840, 0xc81e, 0x887f, 0xc81e, 0x21, 0 - .dw 0x88c0, 0xc81e, 0x88ff, 0xc81e, 0x21, 0 - .dw 0x8940, 0xc81e, 0x897f, 0xc81e, 0x21, 0 - .dw 0x89c0, 0xc81e, 0x89ff, 0xc81e, 0x21, 0 - .dw 0x8a40, 0xc81e, 0x8a7f, 0xc81e, 0x21, 0 - .dw 0x8ac0, 0xc81e, 0x8aff, 0xc81e, 0x21, 0 - .dw 0x8b40, 0xc81e, 0x8b7f, 0xc81e, 0x21, 0 - .dw 0x8bc0, 0xc81e, 0x8bff, 0xc81e, 0x21, 0 - .dw 0x8c40, 0xc81e, 0x8c7f, 0xc81e, 0x21, 0 - .dw 0x8cc0, 0xc81e, 0x8cff, 0xc81e, 0x21, 0 - .dw 0x8d40, 0xc81e, 0x8d7f, 0xc81e, 0x21, 0 - .dw 0x8dc0, 0xc81e, 0x8dff, 0xc81e, 0x21, 0 - .dw 0x8e40, 0xc81e, 0x8e7f, 0xc81e, 0x21, 0 - .dw 0x8ec0, 0xc81e, 0x8eff, 0xc81e, 0x21, 0 - .dw 0x8f40, 0xc81e, 0x8f7f, 0xc81e, 0x21, 0 - .dw 0x8fc0, 0xc81e, 0x8fff, 0xc81e, 0x21, 0 - .dw 0x9040, 0xc81e, 0x907f, 0xc81e, 0x21, 0 - .dw 0x90c0, 0xc81e, 0x90ff, 0xc81e, 0x21, 0 - .dw 0x9140, 0xc81e, 0x917f, 0xc81e, 0x21, 0 - .dw 0x91c0, 0xc81e, 0x91ff, 0xc81e, 0x21, 0 - .dw 0x9240, 0xc81e, 0x927f, 0xc81e, 0x21, 0 - .dw 0x92c0, 0xc81e, 0x92ff, 0xc81e, 0x21, 0 - .dw 0x9340, 0xc81e, 0x937f, 0xc81e, 0x21, 0 - .dw 0x93c0, 0xc81e, 0x93ff, 0xc81e, 0x21, 0 - .dw 0x9440, 0xc81e, 0x947f, 0xc81e, 0x21, 0 - .dw 0x94c0, 0xc81e, 0x94ff, 0xc81e, 0x21, 0 - .dw 0x9540, 0xc81e, 0x957f, 0xc81e, 0x21, 0 - .dw 0x95c0, 0xc81e, 0x95ff, 0xc81e, 0x21, 0 - .dw 0x9640, 0xc81e, 0x967f, 0xc81e, 0x21, 0 - .dw 0x96c0, 0xc81e, 0x96ff, 0xc81e, 0x21, 0 - .dw 0x9740, 0xc81e, 0x977f, 0xc81e, 0x21, 0 - .dw 0x97c0, 0xc81e, 0x97ff, 0xc81e, 0x21, 0 - .dw 0x9840, 0xc81e, 0x987f, 0xc81e, 0x21, 0 - .dw 0x98c0, 0xc81e, 0x98ff, 0xc81e, 0x21, 0 - .dw 0x9940, 0xc81e, 0x997f, 0xc81e, 0x21, 0 - .dw 0x99c0, 0xc81e, 0x9fff, 0xc81e, 0x21, 0 - .dw 0xa040, 0xc81e, 0xa07f, 0xc81e, 0x21, 0 - .dw 0xa0c0, 0xc81e, 0xa0ff, 0xc81e, 0x21, 0 - .dw 0xa140, 0xc81e, 0xa17f, 0xc81e, 0x21, 0 - .dw 0xa1c0, 0xc81e, 0xa1ff, 0xc81e, 0x21, 0 - .dw 0xa240, 0xc81e, 0xa27f, 0xc81e, 0x21, 0 - .dw 0xa2c0, 0xc81e, 0xa2ff, 0xc81e, 0x21, 0 - .dw 0xa340, 0xc81e, 0xa37f, 0xc81e, 0x21, 0 - .dw 0xa3c0, 0xc81e, 0xa3ff, 0xc81e, 0x21, 0 - .dw 0xa440, 0xc81e, 0xa47f, 0xc81e, 0x21, 0 - .dw 0xa4c0, 0xc81e, 0xa4ff, 0xc81e, 0x21, 0 - .dw 0xa540, 0xc81e, 0xa57f, 0xc81e, 0x21, 0 - .dw 0xa5c0, 0xc81e, 0xa5ff, 0xc81e, 0x21, 0 - .dw 0xa640, 0xc81e, 0xa67f, 0xc81e, 0x21, 0 - .dw 0xa6c0, 0xc81e, 0xa6ff, 0xc81e, 0x21, 0 - .dw 0xa740, 0xc81e, 0xa77f, 0xc81e, 0x21, 0 - .dw 0xa7c0, 0xc81e, 0xa7ff, 0xc81e, 0x21, 0 - .dw 0xa840, 0xc81e, 0xa87f, 0xc81e, 0x21, 0 - .dw 0xa8c0, 0xc81e, 0xa8ff, 0xc81e, 0x21, 0 - .dw 0xa940, 0xc81e, 0xa97f, 0xc81e, 0x21, 0 - .dw 0xa9c0, 0xc81e, 0xa9ff, 0xc81e, 0x21, 0 - .dw 0xaa40, 0xc81e, 0xaa7f, 0xc81e, 0x21, 0 - .dw 0xaac0, 0xc81e, 0xaaff, 0xc81e, 0x21, 0 - .dw 0xab40, 0xc81e, 0xab7f, 0xc81e, 0x21, 0 - .dw 0xabc0, 0xc81e, 0xabff, 0xc81e, 0x21, 0 - .dw 0xac40, 0xc81e, 0xac7f, 0xc81e, 0x21, 0 - .dw 0xacc0, 0xc81e, 0xacff, 0xc81e, 0x21, 0 - .dw 0xad40, 0xc81e, 0xad7f, 0xc81e, 0x21, 0 - .dw 0xadc0, 0xc81e, 0xadff, 0xc81e, 0x21, 0 - .dw 0xae40, 0xc81e, 0xae7f, 0xc81e, 0x21, 0 - .dw 0xaec0, 0xc81e, 0xaeff, 0xc81e, 0x21, 0 - .dw 0xaf40, 0xc81e, 0xaf7f, 0xc81e, 0x21, 0 - .dw 0xafc0, 0xc81e, 0xafff, 0xc81e, 0x21, 0 - .dw 0xb040, 0xc81e, 0xb07f, 0xc81e, 0x21, 0 - .dw 0xb0c0, 0xc81e, 0xb0ff, 0xc81e, 0x21, 0 - .dw 0xb140, 0xc81e, 0xb17f, 0xc81e, 0x21, 0 - .dw 0xb1c0, 0xc81e, 0xb1ff, 0xc81e, 0x21, 0 - .dw 0xb240, 0xc81e, 0xb27f, 0xc81e, 0x21, 0 - .dw 0xb2c0, 0xc81e, 0xb2ff, 0xc81e, 0x21, 0 - .dw 0xb340, 0xc81e, 0xb37f, 0xc81e, 0x21, 0 - .dw 0xb3c0, 0xc81e, 0xb3ff, 0xc81e, 0x21, 0 - .dw 0xb440, 0xc81e, 0xb47f, 0xc81e, 0x21, 0 - .dw 0xb4c0, 0xc81e, 0xb4ff, 0xc81e, 0x21, 0 - .dw 0xb540, 0xc81e, 0xb57f, 0xc81e, 0x21, 0 - .dw 0xb5c0, 0xc81e, 0xb5ff, 0xc81e, 0x21, 0 - .dw 0xb640, 0xc81e, 0xb67f, 0xc81e, 0x21, 0 - .dw 0xb6c0, 0xc81e, 0xb6ff, 0xc81e, 0x21, 0 - .dw 0xb740, 0xc81e, 0xb77f, 0xc81e, 0x21, 0 - .dw 0xb7c0, 0xc81e, 0xb7ff, 0xc81e, 0x21, 0 - .dw 0xb840, 0xc81e, 0xb87f, 0xc81e, 0x21, 0 - .dw 0xb8c0, 0xc81e, 0xb8ff, 0xc81e, 0x21, 0 - .dw 0xb940, 0xc81e, 0xb97f, 0xc81e, 0x21, 0 - .dw 0xb9c0, 0xc81e, 0xbfff, 0xc81e, 0x21, 0 - .dw 0xc040, 0xc81e, 0xc07f, 0xc81e, 0x21, 0 - .dw 0xc0c0, 0xc81e, 0xc0ff, 0xc81e, 0x21, 0 - .dw 0xc140, 0xc81e, 0xc17f, 0xc81e, 0x21, 0 - .dw 0xc1c0, 0xc81e, 0xc1ff, 0xc81e, 0x21, 0 - .dw 0xc240, 0xc81e, 0xc27f, 0xc81e, 0x21, 0 - .dw 0xc2c0, 0xc81e, 0xc2ff, 0xc81e, 0x21, 0 - .dw 0xc340, 0xc81e, 0xc37f, 0xc81e, 0x21, 0 - .dw 0xc3c0, 0xc81e, 0xc3ff, 0xc81e, 0x21, 0 - .dw 0xc440, 0xc81e, 0xc47f, 0xc81e, 0x21, 0 - .dw 0xc4c0, 0xc81e, 0xc4ff, 0xc81e, 0x21, 0 - .dw 0xc540, 0xc81e, 0xc57f, 0xc81e, 0x21, 0 - .dw 0xc5c0, 0xc81e, 0xc5ff, 0xc81e, 0x21, 0 - .dw 0xc640, 0xc81e, 0xc67f, 0xc81e, 0x21, 0 - .dw 0xc6c0, 0xc81e, 0xc6ff, 0xc81e, 0x21, 0 - .dw 0xc740, 0xc81e, 0xc77f, 0xc81e, 0x21, 0 - .dw 0xc7c0, 0xc81e, 0xc7ff, 0xc81e, 0x21, 0 - .dw 0xc840, 0xc81e, 0xc87f, 0xc81e, 0x21, 0 - .dw 0xc8c0, 0xc81e, 0xc8ff, 0xc81e, 0x21, 0 - .dw 0xc940, 0xc81e, 0xc97f, 0xc81e, 0x21, 0 - .dw 0xc9c0, 0xc81e, 0xc9ff, 0xc81e, 0x21, 0 - .dw 0xca40, 0xc81e, 0xca7f, 0xc81e, 0x21, 0 - .dw 0xcac0, 0xc81e, 0xcaff, 0xc81e, 0x21, 0 - .dw 0xcb40, 0xc81e, 0xcb7f, 0xc81e, 0x21, 0 - .dw 0xcbc0, 0xc81e, 0xcbff, 0xc81e, 0x21, 0 - .dw 0xcc40, 0xc81e, 0xcc7f, 0xc81e, 0x21, 0 - .dw 0xccc0, 0xc81e, 0xccff, 0xc81e, 0x21, 0 - .dw 0xcd40, 0xc81e, 0xcd7f, 0xc81e, 0x21, 0 - .dw 0xcdc0, 0xc81e, 0xcdff, 0xc81e, 0x21, 0 - .dw 0xce40, 0xc81e, 0xce7f, 0xc81e, 0x21, 0 - .dw 0xcec0, 0xc81e, 0xceff, 0xc81e, 0x21, 0 - .dw 0xcf40, 0xc81e, 0xcf7f, 0xc81e, 0x21, 0 - .dw 0xcfc0, 0xc81e, 0xcfff, 0xc81e, 0x21, 0 - .dw 0xd040, 0xc81e, 0xd07f, 0xc81e, 0x21, 0 - .dw 0xd0c0, 0xc81e, 0xd0ff, 0xc81e, 0x21, 0 - .dw 0xd140, 0xc81e, 0xd17f, 0xc81e, 0x21, 0 - .dw 0xd1c0, 0xc81e, 0xd1ff, 0xc81e, 0x21, 0 - .dw 0xd240, 0xc81e, 0xd27f, 0xc81e, 0x21, 0 - .dw 0xd2c0, 0xc81e, 0xd2ff, 0xc81e, 0x21, 0 - .dw 0xd340, 0xc81e, 0xd37f, 0xc81e, 0x21, 0 - .dw 0xd3c0, 0xc81e, 0xd3ff, 0xc81e, 0x21, 0 - .dw 0xd440, 0xc81e, 0xd47f, 0xc81e, 0x21, 0 - .dw 0xd4c0, 0xc81e, 0xd4ff, 0xc81e, 0x21, 0 - .dw 0xd540, 0xc81e, 0xd57f, 0xc81e, 0x21, 0 - .dw 0xd5c0, 0xc81e, 0xd5ff, 0xc81e, 0x21, 0 - .dw 0xd640, 0xc81e, 0xd67f, 0xc81e, 0x21, 0 - .dw 0xd6c0, 0xc81e, 0xd6ff, 0xc81e, 0x21, 0 - .dw 0xd740, 0xc81e, 0xd77f, 0xc81e, 0x21, 0 - .dw 0xd7c0, 0xc81e, 0xd7ff, 0xc81e, 0x21, 0 - .dw 0xd840, 0xc81e, 0xd87f, 0xc81e, 0x21, 0 - .dw 0xd8c0, 0xc81e, 0xd8ff, 0xc81e, 0x21, 0 - .dw 0xd940, 0xc81e, 0xd97f, 0xc81e, 0x21, 0 - .dw 0xd9c0, 0xc81e, 0xdfff, 0xc81e, 0x21, 0 - .dw 0xe040, 0xc81e, 0xe07f, 0xc81e, 0x21, 0 - .dw 0xe0c0, 0xc81e, 0xe0ff, 0xc81e, 0x21, 0 - .dw 0xe140, 0xc81e, 0xe17f, 0xc81e, 0x21, 0 - .dw 0xe1c0, 0xc81e, 0xe1ff, 0xc81e, 0x21, 0 - .dw 0xe240, 0xc81e, 0xe27f, 0xc81e, 0x21, 0 - .dw 0xe2c0, 0xc81e, 0xe2ff, 0xc81e, 0x21, 0 - .dw 0xe340, 0xc81e, 0xe37f, 0xc81e, 0x21, 0 - .dw 0xe3c0, 0xc81e, 0xe3ff, 0xc81e, 0x21, 0 - .dw 0xe440, 0xc81e, 0xe47f, 0xc81e, 0x21, 0 - .dw 0xe4c0, 0xc81e, 0xe4ff, 0xc81e, 0x21, 0 - .dw 0xe540, 0xc81e, 0xe57f, 0xc81e, 0x21, 0 - .dw 0xe5c0, 0xc81e, 0xe5ff, 0xc81e, 0x21, 0 - .dw 0xe640, 0xc81e, 0xe67f, 0xc81e, 0x21, 0 - .dw 0xe6c0, 0xc81e, 0xe6ff, 0xc81e, 0x21, 0 - .dw 0xe740, 0xc81e, 0xe77f, 0xc81e, 0x21, 0 - .dw 0xe7c0, 0xc81e, 0xe7ff, 0xc81e, 0x21, 0 - .dw 0xe840, 0xc81e, 0xe87f, 0xc81e, 0x21, 0 - .dw 0xe8c0, 0xc81e, 0xe8ff, 0xc81e, 0x21, 0 - .dw 0xe940, 0xc81e, 0xe97f, 0xc81e, 0x21, 0 - .dw 0xe9c0, 0xc81e, 0xe9ff, 0xc81e, 0x21, 0 - .dw 0xea40, 0xc81e, 0xea7f, 0xc81e, 0x21, 0 - .dw 0xeac0, 0xc81e, 0xeaff, 0xc81e, 0x21, 0 - .dw 0xeb40, 0xc81e, 0xeb7f, 0xc81e, 0x21, 0 - .dw 0xebc0, 0xc81e, 0xebff, 0xc81e, 0x21, 0 - .dw 0xec40, 0xc81e, 0xec7f, 0xc81e, 0x21, 0 - .dw 0xecc0, 0xc81e, 0xecff, 0xc81e, 0x21, 0 - .dw 0xed40, 0xc81e, 0xed7f, 0xc81e, 0x21, 0 - .dw 0xedc0, 0xc81e, 0xedff, 0xc81e, 0x21, 0 - .dw 0xee40, 0xc81e, 0xee7f, 0xc81e, 0x21, 0 - .dw 0xeec0, 0xc81e, 0xeeff, 0xc81e, 0x21, 0 - .dw 0xef40, 0xc81e, 0xef7f, 0xc81e, 0x21, 0 - .dw 0xefc0, 0xc81e, 0xefff, 0xc81e, 0x21, 0 - .dw 0xf040, 0xc81e, 0xf07f, 0xc81e, 0x21, 0 - .dw 0xf0c0, 0xc81e, 0xf0ff, 0xc81e, 0x21, 0 - .dw 0xf140, 0xc81e, 0xf17f, 0xc81e, 0x21, 0 - .dw 0xf1c0, 0xc81e, 0xf1ff, 0xc81e, 0x21, 0 - .dw 0xf240, 0xc81e, 0xf27f, 0xc81e, 0x21, 0 - .dw 0xf2c0, 0xc81e, 0xf2ff, 0xc81e, 0x21, 0 - .dw 0xf340, 0xc81e, 0xf37f, 0xc81e, 0x21, 0 - .dw 0xf3c0, 0xc81e, 0xf3ff, 0xc81e, 0x21, 0 - .dw 0xf440, 0xc81e, 0xf47f, 0xc81e, 0x21, 0 - .dw 0xf4c0, 0xc81e, 0xf4ff, 0xc81e, 0x21, 0 - .dw 0xf540, 0xc81e, 0xf57f, 0xc81e, 0x21, 0 - .dw 0xf5c0, 0xc81e, 0xf5ff, 0xc81e, 0x21, 0 - .dw 0xf640, 0xc81e, 0xf67f, 0xc81e, 0x21, 0 - .dw 0xf6c0, 0xc81e, 0xf6ff, 0xc81e, 0x21, 0 - .dw 0xf740, 0xc81e, 0xf77f, 0xc81e, 0x21, 0 - .dw 0xf7c0, 0xc81e, 0xf7ff, 0xc81e, 0x21, 0 - .dw 0xf840, 0xc81e, 0xf87f, 0xc81e, 0x21, 0 - .dw 0xf8c0, 0xc81e, 0xf8ff, 0xc81e, 0x21, 0 - .dw 0xf940, 0xc81e, 0xf97f, 0xc81e, 0x21, 0 - .dw 0xf9c0, 0xc81e, 0xffff, 0xc81e, 0x21, 0 - .dw 0x0040, 0xc81f, 0x007f, 0xc81f, 0x21, 0 - .dw 0x00c0, 0xc81f, 0x00ff, 0xc81f, 0x21, 0 - .dw 0x0140, 0xc81f, 0x017f, 0xc81f, 0x21, 0 - .dw 0x01c0, 0xc81f, 0x01ff, 0xc81f, 0x21, 0 - .dw 0x0240, 0xc81f, 0x027f, 0xc81f, 0x21, 0 - .dw 0x02c0, 0xc81f, 0x02ff, 0xc81f, 0x21, 0 - .dw 0x0340, 0xc81f, 0x037f, 0xc81f, 0x21, 0 - .dw 0x03c0, 0xc81f, 0x03ff, 0xc81f, 0x21, 0 - .dw 0x0440, 0xc81f, 0x047f, 0xc81f, 0x21, 0 - .dw 0x04c0, 0xc81f, 0x04ff, 0xc81f, 0x21, 0 - .dw 0x0540, 0xc81f, 0x057f, 0xc81f, 0x21, 0 - .dw 0x05c0, 0xc81f, 0x05ff, 0xc81f, 0x21, 0 - .dw 0x0640, 0xc81f, 0x067f, 0xc81f, 0x21, 0 - .dw 0x06c0, 0xc81f, 0x06ff, 0xc81f, 0x21, 0 - .dw 0x0740, 0xc81f, 0x077f, 0xc81f, 0x21, 0 - .dw 0x07c0, 0xc81f, 0x07ff, 0xc81f, 0x21, 0 - .dw 0x0840, 0xc81f, 0x087f, 0xc81f, 0x21, 0 - .dw 0x08c0, 0xc81f, 0x08ff, 0xc81f, 0x21, 0 - .dw 0x0940, 0xc81f, 0x097f, 0xc81f, 0x21, 0 - .dw 0x09c0, 0xc81f, 0x09ff, 0xc81f, 0x21, 0 - .dw 0x0a40, 0xc81f, 0x0a7f, 0xc81f, 0x21, 0 - .dw 0x0ac0, 0xc81f, 0x0aff, 0xc81f, 0x21, 0 - .dw 0x0b40, 0xc81f, 0x0b7f, 0xc81f, 0x21, 0 - .dw 0x0bc0, 0xc81f, 0x0bff, 0xc81f, 0x21, 0 - .dw 0x0c40, 0xc81f, 0x0c7f, 0xc81f, 0x21, 0 - .dw 0x0cc0, 0xc81f, 0x0cff, 0xc81f, 0x21, 0 - .dw 0x0d40, 0xc81f, 0x0d7f, 0xc81f, 0x21, 0 - .dw 0x0dc0, 0xc81f, 0x0dff, 0xc81f, 0x21, 0 - .dw 0x0e40, 0xc81f, 0x0e7f, 0xc81f, 0x21, 0 - .dw 0x0ec0, 0xc81f, 0x0eff, 0xc81f, 0x21, 0 - .dw 0x0f40, 0xc81f, 0x0f7f, 0xc81f, 0x21, 0 - .dw 0x0fc0, 0xc81f, 0x0fff, 0xc81f, 0x21, 0 - .dw 0x1040, 0xc81f, 0x107f, 0xc81f, 0x21, 0 - .dw 0x10c0, 0xc81f, 0x10ff, 0xc81f, 0x21, 0 - .dw 0x1140, 0xc81f, 0x117f, 0xc81f, 0x21, 0 - .dw 0x11c0, 0xc81f, 0x11ff, 0xc81f, 0x21, 0 - .dw 0x1240, 0xc81f, 0x127f, 0xc81f, 0x21, 0 - .dw 0x12c0, 0xc81f, 0x12ff, 0xc81f, 0x21, 0 - .dw 0x1340, 0xc81f, 0x137f, 0xc81f, 0x21, 0 - .dw 0x13c0, 0xc81f, 0x13ff, 0xc81f, 0x21, 0 - .dw 0x1440, 0xc81f, 0x147f, 0xc81f, 0x21, 0 - .dw 0x14c0, 0xc81f, 0x14ff, 0xc81f, 0x21, 0 - .dw 0x1540, 0xc81f, 0x157f, 0xc81f, 0x21, 0 - .dw 0x15c0, 0xc81f, 0x15ff, 0xc81f, 0x21, 0 - .dw 0x1640, 0xc81f, 0x167f, 0xc81f, 0x21, 0 - .dw 0x16c0, 0xc81f, 0x16ff, 0xc81f, 0x21, 0 - .dw 0x1740, 0xc81f, 0x177f, 0xc81f, 0x21, 0 - .dw 0x17c0, 0xc81f, 0x17ff, 0xc81f, 0x21, 0 - .dw 0x1840, 0xc81f, 0x187f, 0xc81f, 0x21, 0 - .dw 0x18c0, 0xc81f, 0x18ff, 0xc81f, 0x21, 0 - .dw 0x1940, 0xc81f, 0x197f, 0xc81f, 0x21, 0 - .dw 0x19c0, 0xc81f, 0x1fff, 0xc81f, 0x21, 0 - .dw 0x2040, 0xc81f, 0x207f, 0xc81f, 0x21, 0 - .dw 0x20c0, 0xc81f, 0x20ff, 0xc81f, 0x21, 0 - .dw 0x2140, 0xc81f, 0x217f, 0xc81f, 0x21, 0 - .dw 0x21c0, 0xc81f, 0x21ff, 0xc81f, 0x21, 0 - .dw 0x2240, 0xc81f, 0x227f, 0xc81f, 0x21, 0 - .dw 0x22c0, 0xc81f, 0x22ff, 0xc81f, 0x21, 0 - .dw 0x2340, 0xc81f, 0x237f, 0xc81f, 0x21, 0 - .dw 0x23c0, 0xc81f, 0x23ff, 0xc81f, 0x21, 0 - .dw 0x2440, 0xc81f, 0x247f, 0xc81f, 0x21, 0 - .dw 0x24c0, 0xc81f, 0x24ff, 0xc81f, 0x21, 0 - .dw 0x2540, 0xc81f, 0x257f, 0xc81f, 0x21, 0 - .dw 0x25c0, 0xc81f, 0x25ff, 0xc81f, 0x21, 0 - .dw 0x2640, 0xc81f, 0x267f, 0xc81f, 0x21, 0 - .dw 0x26c0, 0xc81f, 0x26ff, 0xc81f, 0x21, 0 - .dw 0x2740, 0xc81f, 0x277f, 0xc81f, 0x21, 0 - .dw 0x27c0, 0xc81f, 0x27ff, 0xc81f, 0x21, 0 - .dw 0x2840, 0xc81f, 0x287f, 0xc81f, 0x21, 0 - .dw 0x28c0, 0xc81f, 0x28ff, 0xc81f, 0x21, 0 - .dw 0x2940, 0xc81f, 0x297f, 0xc81f, 0x21, 0 - .dw 0x29c0, 0xc81f, 0x29ff, 0xc81f, 0x21, 0 - .dw 0x2a40, 0xc81f, 0x2a7f, 0xc81f, 0x21, 0 - .dw 0x2ac0, 0xc81f, 0x2aff, 0xc81f, 0x21, 0 - .dw 0x2b40, 0xc81f, 0x2b7f, 0xc81f, 0x21, 0 - .dw 0x2bc0, 0xc81f, 0x2bff, 0xc81f, 0x21, 0 - .dw 0x2c40, 0xc81f, 0x2c7f, 0xc81f, 0x21, 0 - .dw 0x2cc0, 0xc81f, 0x2cff, 0xc81f, 0x21, 0 - .dw 0x2d40, 0xc81f, 0x2d7f, 0xc81f, 0x21, 0 - .dw 0x2dc0, 0xc81f, 0x2dff, 0xc81f, 0x21, 0 - .dw 0x2e40, 0xc81f, 0x2e7f, 0xc81f, 0x21, 0 - .dw 0x2ec0, 0xc81f, 0x2eff, 0xc81f, 0x21, 0 - .dw 0x2f40, 0xc81f, 0x2f7f, 0xc81f, 0x21, 0 - .dw 0x2fc0, 0xc81f, 0x2fff, 0xc81f, 0x21, 0 - .dw 0x3040, 0xc81f, 0x307f, 0xc81f, 0x21, 0 - .dw 0x30c0, 0xc81f, 0x30ff, 0xc81f, 0x21, 0 - .dw 0x3140, 0xc81f, 0x317f, 0xc81f, 0x21, 0 - .dw 0x31c0, 0xc81f, 0x31ff, 0xc81f, 0x21, 0 - .dw 0x3240, 0xc81f, 0x327f, 0xc81f, 0x21, 0 - .dw 0x32c0, 0xc81f, 0x32ff, 0xc81f, 0x21, 0 - .dw 0x3340, 0xc81f, 0x337f, 0xc81f, 0x21, 0 - .dw 0x33c0, 0xc81f, 0x33ff, 0xc81f, 0x21, 0 - .dw 0x3440, 0xc81f, 0x347f, 0xc81f, 0x21, 0 - .dw 0x34c0, 0xc81f, 0x34ff, 0xc81f, 0x21, 0 - .dw 0x3540, 0xc81f, 0x357f, 0xc81f, 0x21, 0 - .dw 0x35c0, 0xc81f, 0x35ff, 0xc81f, 0x21, 0 - .dw 0x3640, 0xc81f, 0x367f, 0xc81f, 0x21, 0 - .dw 0x36c0, 0xc81f, 0x36ff, 0xc81f, 0x21, 0 - .dw 0x3740, 0xc81f, 0x377f, 0xc81f, 0x21, 0 - .dw 0x37c0, 0xc81f, 0x37ff, 0xc81f, 0x21, 0 - .dw 0x3840, 0xc81f, 0x387f, 0xc81f, 0x21, 0 - .dw 0x38c0, 0xc81f, 0x38ff, 0xc81f, 0x21, 0 - .dw 0x3940, 0xc81f, 0x397f, 0xc81f, 0x21, 0 - .dw 0x39c0, 0xc81f, 0x1fff, 0xc820, 0x21, 0 - .dw 0x3a00, 0xc820, 0x5fff, 0xc820, 0x21, 0 - .dw 0x7a00, 0xc820, 0x9fff, 0xc820, 0x21, 0 - .dw 0xba00, 0xc820, 0xdfff, 0xc820, 0x21, 0 - .dw 0xfa00, 0xc820, 0x1fff, 0xc821, 0x21, 0 - .dw 0x3a00, 0xc821, 0x5fff, 0xc821, 0x21, 0 - .dw 0x7a00, 0xc821, 0x9fff, 0xc821, 0x21, 0 - .dw 0xba00, 0xc821, 0xdfff, 0xc821, 0x21, 0 - .dw 0xfa00, 0xc821, 0x1fff, 0xc822, 0x21, 0 - .dw 0x3a00, 0xc822, 0x5fff, 0xc822, 0x21, 0 - .dw 0x7a00, 0xc822, 0x9fff, 0xc822, 0x21, 0 - .dw 0xba00, 0xc822, 0xdfff, 0xc822, 0x21, 0 - .dw 0xfa00, 0xc822, 0x1fff, 0xc823, 0x21, 0 - .dw 0x3a00, 0xc823, 0xffff, 0xc823, 0x21, 0 - .dw 0x1a00, 0xc824, 0x1fff, 0xc824, 0x21, 0 - .dw 0x3a00, 0xc824, 0x3fff, 0xc824, 0x21, 0 - .dw 0x5a00, 0xc824, 0x5fff, 0xc824, 0x21, 0 - .dw 0x7a00, 0xc824, 0x7fff, 0xc824, 0x21, 0 - .dw 0x9a00, 0xc824, 0x9fff, 0xc824, 0x21, 0 - .dw 0xba00, 0xc824, 0xbfff, 0xc824, 0x21, 0 - .dw 0xda00, 0xc824, 0xdfff, 0xc824, 0x21, 0 - .dw 0xfa00, 0xc824, 0xffff, 0xc824, 0x21, 0 - .dw 0x1a00, 0xc825, 0x1fff, 0xc825, 0x21, 0 - .dw 0x3a00, 0xc825, 0x3fff, 0xc825, 0x21, 0 - .dw 0x5a00, 0xc825, 0x5fff, 0xc825, 0x21, 0 - .dw 0x7a00, 0xc825, 0x7fff, 0xc825, 0x21, 0 - .dw 0x9a00, 0xc825, 0x9fff, 0xc825, 0x21, 0 - .dw 0xba00, 0xc825, 0xbfff, 0xc825, 0x21, 0 - .dw 0xda00, 0xc825, 0xdfff, 0xc825, 0x21, 0 - .dw 0xfa00, 0xc825, 0xffff, 0xc825, 0x21, 0 - .dw 0x1a00, 0xc826, 0x1fff, 0xc826, 0x21, 0 - .dw 0x3a00, 0xc826, 0x3fff, 0xc826, 0x21, 0 - .dw 0x5a00, 0xc826, 0x5fff, 0xc826, 0x21, 0 - .dw 0x7a00, 0xc826, 0x7fff, 0xc826, 0x21, 0 - .dw 0x9a00, 0xc826, 0x9fff, 0xc826, 0x21, 0 - .dw 0xba00, 0xc826, 0xbfff, 0xc826, 0x21, 0 - .dw 0xda00, 0xc826, 0xdfff, 0xc826, 0x21, 0 - .dw 0xfa00, 0xc826, 0xffff, 0xc826, 0x21, 0 - .dw 0x1a00, 0xc827, 0x1fff, 0xc827, 0x21, 0 - .dw 0x3a00, 0xc827, 0x1fff, 0xc828, 0x21, 0 - .dw 0x2040, 0xc828, 0x207f, 0xc828, 0x21, 0 - .dw 0x20c0, 0xc828, 0x20ff, 0xc828, 0x21, 0 - .dw 0x2140, 0xc828, 0x217f, 0xc828, 0x21, 0 - .dw 0x21c0, 0xc828, 0x21ff, 0xc828, 0x21, 0 - .dw 0x2240, 0xc828, 0x227f, 0xc828, 0x21, 0 - .dw 0x22c0, 0xc828, 0x22ff, 0xc828, 0x21, 0 - .dw 0x2340, 0xc828, 0x237f, 0xc828, 0x21, 0 - .dw 0x23c0, 0xc828, 0x23ff, 0xc828, 0x21, 0 - .dw 0x2440, 0xc828, 0x247f, 0xc828, 0x21, 0 - .dw 0x24c0, 0xc828, 0x24ff, 0xc828, 0x21, 0 - .dw 0x2540, 0xc828, 0x257f, 0xc828, 0x21, 0 - .dw 0x25c0, 0xc828, 0x25ff, 0xc828, 0x21, 0 - .dw 0x2640, 0xc828, 0x267f, 0xc828, 0x21, 0 - .dw 0x26c0, 0xc828, 0x26ff, 0xc828, 0x21, 0 - .dw 0x2740, 0xc828, 0x277f, 0xc828, 0x21, 0 - .dw 0x27c0, 0xc828, 0x27ff, 0xc828, 0x21, 0 - .dw 0x2840, 0xc828, 0x287f, 0xc828, 0x21, 0 - .dw 0x28c0, 0xc828, 0x28ff, 0xc828, 0x21, 0 - .dw 0x2940, 0xc828, 0x297f, 0xc828, 0x21, 0 - .dw 0x29c0, 0xc828, 0x29ff, 0xc828, 0x21, 0 - .dw 0x2a40, 0xc828, 0x2a7f, 0xc828, 0x21, 0 - .dw 0x2ac0, 0xc828, 0x2aff, 0xc828, 0x21, 0 - .dw 0x2b40, 0xc828, 0x2b7f, 0xc828, 0x21, 0 - .dw 0x2bc0, 0xc828, 0x2bff, 0xc828, 0x21, 0 - .dw 0x2c40, 0xc828, 0x2c7f, 0xc828, 0x21, 0 - .dw 0x2cc0, 0xc828, 0x2cff, 0xc828, 0x21, 0 - .dw 0x2d40, 0xc828, 0x2d7f, 0xc828, 0x21, 0 - .dw 0x2dc0, 0xc828, 0x2dff, 0xc828, 0x21, 0 - .dw 0x2e40, 0xc828, 0x2e7f, 0xc828, 0x21, 0 - .dw 0x2ec0, 0xc828, 0x2eff, 0xc828, 0x21, 0 - .dw 0x2f40, 0xc828, 0x2f7f, 0xc828, 0x21, 0 - .dw 0x2fc0, 0xc828, 0x2fff, 0xc828, 0x21, 0 - .dw 0x3040, 0xc828, 0x307f, 0xc828, 0x21, 0 - .dw 0x30c0, 0xc828, 0x30ff, 0xc828, 0x21, 0 - .dw 0x3140, 0xc828, 0x317f, 0xc828, 0x21, 0 - .dw 0x31c0, 0xc828, 0x31ff, 0xc828, 0x21, 0 - .dw 0x3240, 0xc828, 0x327f, 0xc828, 0x21, 0 - .dw 0x32c0, 0xc828, 0x32ff, 0xc828, 0x21, 0 - .dw 0x3340, 0xc828, 0x337f, 0xc828, 0x21, 0 - .dw 0x33c0, 0xc828, 0x33ff, 0xc828, 0x21, 0 - .dw 0x3440, 0xc828, 0x347f, 0xc828, 0x21, 0 - .dw 0x34c0, 0xc828, 0x34ff, 0xc828, 0x21, 0 - .dw 0x3540, 0xc828, 0x357f, 0xc828, 0x21, 0 - .dw 0x35c0, 0xc828, 0x35ff, 0xc828, 0x21, 0 - .dw 0x3640, 0xc828, 0x367f, 0xc828, 0x21, 0 - .dw 0x36c0, 0xc828, 0x36ff, 0xc828, 0x21, 0 - .dw 0x3740, 0xc828, 0x377f, 0xc828, 0x21, 0 - .dw 0x37c0, 0xc828, 0x37ff, 0xc828, 0x21, 0 - .dw 0x3840, 0xc828, 0x387f, 0xc828, 0x21, 0 - .dw 0x38c0, 0xc828, 0x38ff, 0xc828, 0x21, 0 - .dw 0x3940, 0xc828, 0x397f, 0xc828, 0x21, 0 - .dw 0x39c0, 0xc828, 0x5fff, 0xc828, 0x21, 0 - .dw 0x6040, 0xc828, 0x607f, 0xc828, 0x21, 0 - .dw 0x60c0, 0xc828, 0x60ff, 0xc828, 0x21, 0 - .dw 0x6140, 0xc828, 0x617f, 0xc828, 0x21, 0 - .dw 0x61c0, 0xc828, 0x61ff, 0xc828, 0x21, 0 - .dw 0x6240, 0xc828, 0x627f, 0xc828, 0x21, 0 - .dw 0x62c0, 0xc828, 0x62ff, 0xc828, 0x21, 0 - .dw 0x6340, 0xc828, 0x637f, 0xc828, 0x21, 0 - .dw 0x63c0, 0xc828, 0x63ff, 0xc828, 0x21, 0 - .dw 0x6440, 0xc828, 0x647f, 0xc828, 0x21, 0 - .dw 0x64c0, 0xc828, 0x64ff, 0xc828, 0x21, 0 - .dw 0x6540, 0xc828, 0x657f, 0xc828, 0x21, 0 - .dw 0x65c0, 0xc828, 0x65ff, 0xc828, 0x21, 0 - .dw 0x6640, 0xc828, 0x667f, 0xc828, 0x21, 0 - .dw 0x66c0, 0xc828, 0x66ff, 0xc828, 0x21, 0 - .dw 0x6740, 0xc828, 0x677f, 0xc828, 0x21, 0 - .dw 0x67c0, 0xc828, 0x67ff, 0xc828, 0x21, 0 - .dw 0x6840, 0xc828, 0x687f, 0xc828, 0x21, 0 - .dw 0x68c0, 0xc828, 0x68ff, 0xc828, 0x21, 0 - .dw 0x6940, 0xc828, 0x697f, 0xc828, 0x21, 0 - .dw 0x69c0, 0xc828, 0x69ff, 0xc828, 0x21, 0 - .dw 0x6a40, 0xc828, 0x6a7f, 0xc828, 0x21, 0 - .dw 0x6ac0, 0xc828, 0x6aff, 0xc828, 0x21, 0 - .dw 0x6b40, 0xc828, 0x6b7f, 0xc828, 0x21, 0 - .dw 0x6bc0, 0xc828, 0x6bff, 0xc828, 0x21, 0 - .dw 0x6c40, 0xc828, 0x6c7f, 0xc828, 0x21, 0 - .dw 0x6cc0, 0xc828, 0x6cff, 0xc828, 0x21, 0 - .dw 0x6d40, 0xc828, 0x6d7f, 0xc828, 0x21, 0 - .dw 0x6dc0, 0xc828, 0x6dff, 0xc828, 0x21, 0 - .dw 0x6e40, 0xc828, 0x6e7f, 0xc828, 0x21, 0 - .dw 0x6ec0, 0xc828, 0x6eff, 0xc828, 0x21, 0 - .dw 0x6f40, 0xc828, 0x6f7f, 0xc828, 0x21, 0 - .dw 0x6fc0, 0xc828, 0x6fff, 0xc828, 0x21, 0 - .dw 0x7040, 0xc828, 0x707f, 0xc828, 0x21, 0 - .dw 0x70c0, 0xc828, 0x70ff, 0xc828, 0x21, 0 - .dw 0x7140, 0xc828, 0x717f, 0xc828, 0x21, 0 - .dw 0x71c0, 0xc828, 0x71ff, 0xc828, 0x21, 0 - .dw 0x7240, 0xc828, 0x727f, 0xc828, 0x21, 0 - .dw 0x72c0, 0xc828, 0x72ff, 0xc828, 0x21, 0 - .dw 0x7340, 0xc828, 0x737f, 0xc828, 0x21, 0 - .dw 0x73c0, 0xc828, 0x73ff, 0xc828, 0x21, 0 - .dw 0x7440, 0xc828, 0x747f, 0xc828, 0x21, 0 - .dw 0x74c0, 0xc828, 0x74ff, 0xc828, 0x21, 0 - .dw 0x7540, 0xc828, 0x757f, 0xc828, 0x21, 0 - .dw 0x75c0, 0xc828, 0x75ff, 0xc828, 0x21, 0 - .dw 0x7640, 0xc828, 0x767f, 0xc828, 0x21, 0 - .dw 0x76c0, 0xc828, 0x76ff, 0xc828, 0x21, 0 - .dw 0x7740, 0xc828, 0x777f, 0xc828, 0x21, 0 - .dw 0x77c0, 0xc828, 0x77ff, 0xc828, 0x21, 0 - .dw 0x7840, 0xc828, 0x787f, 0xc828, 0x21, 0 - .dw 0x78c0, 0xc828, 0x78ff, 0xc828, 0x21, 0 - .dw 0x7940, 0xc828, 0x797f, 0xc828, 0x21, 0 - .dw 0x79c0, 0xc828, 0x9fff, 0xc828, 0x21, 0 - .dw 0xa040, 0xc828, 0xa07f, 0xc828, 0x21, 0 - .dw 0xa0c0, 0xc828, 0xa0ff, 0xc828, 0x21, 0 - .dw 0xa140, 0xc828, 0xa17f, 0xc828, 0x21, 0 - .dw 0xa1c0, 0xc828, 0xa1ff, 0xc828, 0x21, 0 - .dw 0xa240, 0xc828, 0xa27f, 0xc828, 0x21, 0 - .dw 0xa2c0, 0xc828, 0xa2ff, 0xc828, 0x21, 0 - .dw 0xa340, 0xc828, 0xa37f, 0xc828, 0x21, 0 - .dw 0xa3c0, 0xc828, 0xa3ff, 0xc828, 0x21, 0 - .dw 0xa440, 0xc828, 0xa47f, 0xc828, 0x21, 0 - .dw 0xa4c0, 0xc828, 0xa4ff, 0xc828, 0x21, 0 - .dw 0xa540, 0xc828, 0xa57f, 0xc828, 0x21, 0 - .dw 0xa5c0, 0xc828, 0xa5ff, 0xc828, 0x21, 0 - .dw 0xa640, 0xc828, 0xa67f, 0xc828, 0x21, 0 - .dw 0xa6c0, 0xc828, 0xa6ff, 0xc828, 0x21, 0 - .dw 0xa740, 0xc828, 0xa77f, 0xc828, 0x21, 0 - .dw 0xa7c0, 0xc828, 0xa7ff, 0xc828, 0x21, 0 - .dw 0xa840, 0xc828, 0xa87f, 0xc828, 0x21, 0 - .dw 0xa8c0, 0xc828, 0xa8ff, 0xc828, 0x21, 0 - .dw 0xa940, 0xc828, 0xa97f, 0xc828, 0x21, 0 - .dw 0xa9c0, 0xc828, 0xa9ff, 0xc828, 0x21, 0 - .dw 0xaa40, 0xc828, 0xaa7f, 0xc828, 0x21, 0 - .dw 0xaac0, 0xc828, 0xaaff, 0xc828, 0x21, 0 - .dw 0xab40, 0xc828, 0xab7f, 0xc828, 0x21, 0 - .dw 0xabc0, 0xc828, 0xabff, 0xc828, 0x21, 0 - .dw 0xac40, 0xc828, 0xac7f, 0xc828, 0x21, 0 - .dw 0xacc0, 0xc828, 0xacff, 0xc828, 0x21, 0 - .dw 0xad40, 0xc828, 0xad7f, 0xc828, 0x21, 0 - .dw 0xadc0, 0xc828, 0xadff, 0xc828, 0x21, 0 - .dw 0xae40, 0xc828, 0xae7f, 0xc828, 0x21, 0 - .dw 0xaec0, 0xc828, 0xaeff, 0xc828, 0x21, 0 - .dw 0xaf40, 0xc828, 0xaf7f, 0xc828, 0x21, 0 - .dw 0xafc0, 0xc828, 0xafff, 0xc828, 0x21, 0 - .dw 0xb040, 0xc828, 0xb07f, 0xc828, 0x21, 0 - .dw 0xb0c0, 0xc828, 0xb0ff, 0xc828, 0x21, 0 - .dw 0xb140, 0xc828, 0xb17f, 0xc828, 0x21, 0 - .dw 0xb1c0, 0xc828, 0xb1ff, 0xc828, 0x21, 0 - .dw 0xb240, 0xc828, 0xb27f, 0xc828, 0x21, 0 - .dw 0xb2c0, 0xc828, 0xb2ff, 0xc828, 0x21, 0 - .dw 0xb340, 0xc828, 0xb37f, 0xc828, 0x21, 0 - .dw 0xb3c0, 0xc828, 0xb3ff, 0xc828, 0x21, 0 - .dw 0xb440, 0xc828, 0xb47f, 0xc828, 0x21, 0 - .dw 0xb4c0, 0xc828, 0xb4ff, 0xc828, 0x21, 0 - .dw 0xb540, 0xc828, 0xb57f, 0xc828, 0x21, 0 - .dw 0xb5c0, 0xc828, 0xb5ff, 0xc828, 0x21, 0 - .dw 0xb640, 0xc828, 0xb67f, 0xc828, 0x21, 0 - .dw 0xb6c0, 0xc828, 0xb6ff, 0xc828, 0x21, 0 - .dw 0xb740, 0xc828, 0xb77f, 0xc828, 0x21, 0 - .dw 0xb7c0, 0xc828, 0xb7ff, 0xc828, 0x21, 0 - .dw 0xb840, 0xc828, 0xb87f, 0xc828, 0x21, 0 - .dw 0xb8c0, 0xc828, 0xb8ff, 0xc828, 0x21, 0 - .dw 0xb940, 0xc828, 0xb97f, 0xc828, 0x21, 0 - .dw 0xb9c0, 0xc828, 0xdfff, 0xc828, 0x21, 0 - .dw 0xe040, 0xc828, 0xe07f, 0xc828, 0x21, 0 - .dw 0xe0c0, 0xc828, 0xe0ff, 0xc828, 0x21, 0 - .dw 0xe140, 0xc828, 0xe17f, 0xc828, 0x21, 0 - .dw 0xe1c0, 0xc828, 0xe1ff, 0xc828, 0x21, 0 - .dw 0xe240, 0xc828, 0xe27f, 0xc828, 0x21, 0 - .dw 0xe2c0, 0xc828, 0xe2ff, 0xc828, 0x21, 0 - .dw 0xe340, 0xc828, 0xe37f, 0xc828, 0x21, 0 - .dw 0xe3c0, 0xc828, 0xe3ff, 0xc828, 0x21, 0 - .dw 0xe440, 0xc828, 0xe47f, 0xc828, 0x21, 0 - .dw 0xe4c0, 0xc828, 0xe4ff, 0xc828, 0x21, 0 - .dw 0xe540, 0xc828, 0xe57f, 0xc828, 0x21, 0 - .dw 0xe5c0, 0xc828, 0xe5ff, 0xc828, 0x21, 0 - .dw 0xe640, 0xc828, 0xe67f, 0xc828, 0x21, 0 - .dw 0xe6c0, 0xc828, 0xe6ff, 0xc828, 0x21, 0 - .dw 0xe740, 0xc828, 0xe77f, 0xc828, 0x21, 0 - .dw 0xe7c0, 0xc828, 0xe7ff, 0xc828, 0x21, 0 - .dw 0xe840, 0xc828, 0xe87f, 0xc828, 0x21, 0 - .dw 0xe8c0, 0xc828, 0xe8ff, 0xc828, 0x21, 0 - .dw 0xe940, 0xc828, 0xe97f, 0xc828, 0x21, 0 - .dw 0xe9c0, 0xc828, 0xe9ff, 0xc828, 0x21, 0 - .dw 0xea40, 0xc828, 0xea7f, 0xc828, 0x21, 0 - .dw 0xeac0, 0xc828, 0xeaff, 0xc828, 0x21, 0 - .dw 0xeb40, 0xc828, 0xeb7f, 0xc828, 0x21, 0 - .dw 0xebc0, 0xc828, 0xebff, 0xc828, 0x21, 0 - .dw 0xec40, 0xc828, 0xec7f, 0xc828, 0x21, 0 - .dw 0xecc0, 0xc828, 0xecff, 0xc828, 0x21, 0 - .dw 0xed40, 0xc828, 0xed7f, 0xc828, 0x21, 0 - .dw 0xedc0, 0xc828, 0xedff, 0xc828, 0x21, 0 - .dw 0xee40, 0xc828, 0xee7f, 0xc828, 0x21, 0 - .dw 0xeec0, 0xc828, 0xeeff, 0xc828, 0x21, 0 - .dw 0xef40, 0xc828, 0xef7f, 0xc828, 0x21, 0 - .dw 0xefc0, 0xc828, 0xefff, 0xc828, 0x21, 0 - .dw 0xf040, 0xc828, 0xf07f, 0xc828, 0x21, 0 - .dw 0xf0c0, 0xc828, 0xf0ff, 0xc828, 0x21, 0 - .dw 0xf140, 0xc828, 0xf17f, 0xc828, 0x21, 0 - .dw 0xf1c0, 0xc828, 0xf1ff, 0xc828, 0x21, 0 - .dw 0xf240, 0xc828, 0xf27f, 0xc828, 0x21, 0 - .dw 0xf2c0, 0xc828, 0xf2ff, 0xc828, 0x21, 0 - .dw 0xf340, 0xc828, 0xf37f, 0xc828, 0x21, 0 - .dw 0xf3c0, 0xc828, 0xf3ff, 0xc828, 0x21, 0 - .dw 0xf440, 0xc828, 0xf47f, 0xc828, 0x21, 0 - .dw 0xf4c0, 0xc828, 0xf4ff, 0xc828, 0x21, 0 - .dw 0xf540, 0xc828, 0xf57f, 0xc828, 0x21, 0 - .dw 0xf5c0, 0xc828, 0xf5ff, 0xc828, 0x21, 0 - .dw 0xf640, 0xc828, 0xf67f, 0xc828, 0x21, 0 - .dw 0xf6c0, 0xc828, 0xf6ff, 0xc828, 0x21, 0 - .dw 0xf740, 0xc828, 0xf77f, 0xc828, 0x21, 0 - .dw 0xf7c0, 0xc828, 0xf7ff, 0xc828, 0x21, 0 - .dw 0xf840, 0xc828, 0xf87f, 0xc828, 0x21, 0 - .dw 0xf8c0, 0xc828, 0xf8ff, 0xc828, 0x21, 0 - .dw 0xf940, 0xc828, 0xf97f, 0xc828, 0x21, 0 - .dw 0xf9c0, 0xc828, 0x1fff, 0xc829, 0x21, 0 - .dw 0x2040, 0xc829, 0x207f, 0xc829, 0x21, 0 - .dw 0x20c0, 0xc829, 0x20ff, 0xc829, 0x21, 0 - .dw 0x2140, 0xc829, 0x217f, 0xc829, 0x21, 0 - .dw 0x21c0, 0xc829, 0x21ff, 0xc829, 0x21, 0 - .dw 0x2240, 0xc829, 0x227f, 0xc829, 0x21, 0 - .dw 0x22c0, 0xc829, 0x22ff, 0xc829, 0x21, 0 - .dw 0x2340, 0xc829, 0x237f, 0xc829, 0x21, 0 - .dw 0x23c0, 0xc829, 0x23ff, 0xc829, 0x21, 0 - .dw 0x2440, 0xc829, 0x247f, 0xc829, 0x21, 0 - .dw 0x24c0, 0xc829, 0x24ff, 0xc829, 0x21, 0 - .dw 0x2540, 0xc829, 0x257f, 0xc829, 0x21, 0 - .dw 0x25c0, 0xc829, 0x25ff, 0xc829, 0x21, 0 - .dw 0x2640, 0xc829, 0x267f, 0xc829, 0x21, 0 - .dw 0x26c0, 0xc829, 0x26ff, 0xc829, 0x21, 0 - .dw 0x2740, 0xc829, 0x277f, 0xc829, 0x21, 0 - .dw 0x27c0, 0xc829, 0x27ff, 0xc829, 0x21, 0 - .dw 0x2840, 0xc829, 0x287f, 0xc829, 0x21, 0 - .dw 0x28c0, 0xc829, 0x28ff, 0xc829, 0x21, 0 - .dw 0x2940, 0xc829, 0x297f, 0xc829, 0x21, 0 - .dw 0x29c0, 0xc829, 0x29ff, 0xc829, 0x21, 0 - .dw 0x2a40, 0xc829, 0x2a7f, 0xc829, 0x21, 0 - .dw 0x2ac0, 0xc829, 0x2aff, 0xc829, 0x21, 0 - .dw 0x2b40, 0xc829, 0x2b7f, 0xc829, 0x21, 0 - .dw 0x2bc0, 0xc829, 0x2bff, 0xc829, 0x21, 0 - .dw 0x2c40, 0xc829, 0x2c7f, 0xc829, 0x21, 0 - .dw 0x2cc0, 0xc829, 0x2cff, 0xc829, 0x21, 0 - .dw 0x2d40, 0xc829, 0x2d7f, 0xc829, 0x21, 0 - .dw 0x2dc0, 0xc829, 0x2dff, 0xc829, 0x21, 0 - .dw 0x2e40, 0xc829, 0x2e7f, 0xc829, 0x21, 0 - .dw 0x2ec0, 0xc829, 0x2eff, 0xc829, 0x21, 0 - .dw 0x2f40, 0xc829, 0x2f7f, 0xc829, 0x21, 0 - .dw 0x2fc0, 0xc829, 0x2fff, 0xc829, 0x21, 0 - .dw 0x3040, 0xc829, 0x307f, 0xc829, 0x21, 0 - .dw 0x30c0, 0xc829, 0x30ff, 0xc829, 0x21, 0 - .dw 0x3140, 0xc829, 0x317f, 0xc829, 0x21, 0 - .dw 0x31c0, 0xc829, 0x31ff, 0xc829, 0x21, 0 - .dw 0x3240, 0xc829, 0x327f, 0xc829, 0x21, 0 - .dw 0x32c0, 0xc829, 0x32ff, 0xc829, 0x21, 0 - .dw 0x3340, 0xc829, 0x337f, 0xc829, 0x21, 0 - .dw 0x33c0, 0xc829, 0x33ff, 0xc829, 0x21, 0 - .dw 0x3440, 0xc829, 0x347f, 0xc829, 0x21, 0 - .dw 0x34c0, 0xc829, 0x34ff, 0xc829, 0x21, 0 - .dw 0x3540, 0xc829, 0x357f, 0xc829, 0x21, 0 - .dw 0x35c0, 0xc829, 0x35ff, 0xc829, 0x21, 0 - .dw 0x3640, 0xc829, 0x367f, 0xc829, 0x21, 0 - .dw 0x36c0, 0xc829, 0x36ff, 0xc829, 0x21, 0 - .dw 0x3740, 0xc829, 0x377f, 0xc829, 0x21, 0 - .dw 0x37c0, 0xc829, 0x37ff, 0xc829, 0x21, 0 - .dw 0x3840, 0xc829, 0x387f, 0xc829, 0x21, 0 - .dw 0x38c0, 0xc829, 0x38ff, 0xc829, 0x21, 0 - .dw 0x3940, 0xc829, 0x397f, 0xc829, 0x21, 0 - .dw 0x39c0, 0xc829, 0x5fff, 0xc829, 0x21, 0 - .dw 0x6040, 0xc829, 0x607f, 0xc829, 0x21, 0 - .dw 0x60c0, 0xc829, 0x60ff, 0xc829, 0x21, 0 - .dw 0x6140, 0xc829, 0x617f, 0xc829, 0x21, 0 - .dw 0x61c0, 0xc829, 0x61ff, 0xc829, 0x21, 0 - .dw 0x6240, 0xc829, 0x627f, 0xc829, 0x21, 0 - .dw 0x62c0, 0xc829, 0x62ff, 0xc829, 0x21, 0 - .dw 0x6340, 0xc829, 0x637f, 0xc829, 0x21, 0 - .dw 0x63c0, 0xc829, 0x63ff, 0xc829, 0x21, 0 - .dw 0x6440, 0xc829, 0x647f, 0xc829, 0x21, 0 - .dw 0x64c0, 0xc829, 0x64ff, 0xc829, 0x21, 0 - .dw 0x6540, 0xc829, 0x657f, 0xc829, 0x21, 0 - .dw 0x65c0, 0xc829, 0x65ff, 0xc829, 0x21, 0 - .dw 0x6640, 0xc829, 0x667f, 0xc829, 0x21, 0 - .dw 0x66c0, 0xc829, 0x66ff, 0xc829, 0x21, 0 - .dw 0x6740, 0xc829, 0x677f, 0xc829, 0x21, 0 - .dw 0x67c0, 0xc829, 0x67ff, 0xc829, 0x21, 0 - .dw 0x6840, 0xc829, 0x687f, 0xc829, 0x21, 0 - .dw 0x68c0, 0xc829, 0x68ff, 0xc829, 0x21, 0 - .dw 0x6940, 0xc829, 0x697f, 0xc829, 0x21, 0 - .dw 0x69c0, 0xc829, 0x69ff, 0xc829, 0x21, 0 - .dw 0x6a40, 0xc829, 0x6a7f, 0xc829, 0x21, 0 - .dw 0x6ac0, 0xc829, 0x6aff, 0xc829, 0x21, 0 - .dw 0x6b40, 0xc829, 0x6b7f, 0xc829, 0x21, 0 - .dw 0x6bc0, 0xc829, 0x6bff, 0xc829, 0x21, 0 - .dw 0x6c40, 0xc829, 0x6c7f, 0xc829, 0x21, 0 - .dw 0x6cc0, 0xc829, 0x6cff, 0xc829, 0x21, 0 - .dw 0x6d40, 0xc829, 0x6d7f, 0xc829, 0x21, 0 - .dw 0x6dc0, 0xc829, 0x6dff, 0xc829, 0x21, 0 - .dw 0x6e40, 0xc829, 0x6e7f, 0xc829, 0x21, 0 - .dw 0x6ec0, 0xc829, 0x6eff, 0xc829, 0x21, 0 - .dw 0x6f40, 0xc829, 0x6f7f, 0xc829, 0x21, 0 - .dw 0x6fc0, 0xc829, 0x6fff, 0xc829, 0x21, 0 - .dw 0x7040, 0xc829, 0x707f, 0xc829, 0x21, 0 - .dw 0x70c0, 0xc829, 0x70ff, 0xc829, 0x21, 0 - .dw 0x7140, 0xc829, 0x717f, 0xc829, 0x21, 0 - .dw 0x71c0, 0xc829, 0x71ff, 0xc829, 0x21, 0 - .dw 0x7240, 0xc829, 0x727f, 0xc829, 0x21, 0 - .dw 0x72c0, 0xc829, 0x72ff, 0xc829, 0x21, 0 - .dw 0x7340, 0xc829, 0x737f, 0xc829, 0x21, 0 - .dw 0x73c0, 0xc829, 0x73ff, 0xc829, 0x21, 0 - .dw 0x7440, 0xc829, 0x747f, 0xc829, 0x21, 0 - .dw 0x74c0, 0xc829, 0x74ff, 0xc829, 0x21, 0 - .dw 0x7540, 0xc829, 0x757f, 0xc829, 0x21, 0 - .dw 0x75c0, 0xc829, 0x75ff, 0xc829, 0x21, 0 - .dw 0x7640, 0xc829, 0x767f, 0xc829, 0x21, 0 - .dw 0x76c0, 0xc829, 0x76ff, 0xc829, 0x21, 0 - .dw 0x7740, 0xc829, 0x777f, 0xc829, 0x21, 0 - .dw 0x77c0, 0xc829, 0x77ff, 0xc829, 0x21, 0 - .dw 0x7840, 0xc829, 0x787f, 0xc829, 0x21, 0 - .dw 0x78c0, 0xc829, 0x78ff, 0xc829, 0x21, 0 - .dw 0x7940, 0xc829, 0x797f, 0xc829, 0x21, 0 - .dw 0x79c0, 0xc829, 0x9fff, 0xc829, 0x21, 0 - .dw 0xa040, 0xc829, 0xa07f, 0xc829, 0x21, 0 - .dw 0xa0c0, 0xc829, 0xa0ff, 0xc829, 0x21, 0 - .dw 0xa140, 0xc829, 0xa17f, 0xc829, 0x21, 0 - .dw 0xa1c0, 0xc829, 0xa1ff, 0xc829, 0x21, 0 - .dw 0xa240, 0xc829, 0xa27f, 0xc829, 0x21, 0 - .dw 0xa2c0, 0xc829, 0xa2ff, 0xc829, 0x21, 0 - .dw 0xa340, 0xc829, 0xa37f, 0xc829, 0x21, 0 - .dw 0xa3c0, 0xc829, 0xa3ff, 0xc829, 0x21, 0 - .dw 0xa440, 0xc829, 0xa47f, 0xc829, 0x21, 0 - .dw 0xa4c0, 0xc829, 0xa4ff, 0xc829, 0x21, 0 - .dw 0xa540, 0xc829, 0xa57f, 0xc829, 0x21, 0 - .dw 0xa5c0, 0xc829, 0xa5ff, 0xc829, 0x21, 0 - .dw 0xa640, 0xc829, 0xa67f, 0xc829, 0x21, 0 - .dw 0xa6c0, 0xc829, 0xa6ff, 0xc829, 0x21, 0 - .dw 0xa740, 0xc829, 0xa77f, 0xc829, 0x21, 0 - .dw 0xa7c0, 0xc829, 0xa7ff, 0xc829, 0x21, 0 - .dw 0xa840, 0xc829, 0xa87f, 0xc829, 0x21, 0 - .dw 0xa8c0, 0xc829, 0xa8ff, 0xc829, 0x21, 0 - .dw 0xa940, 0xc829, 0xa97f, 0xc829, 0x21, 0 - .dw 0xa9c0, 0xc829, 0xa9ff, 0xc829, 0x21, 0 - .dw 0xaa40, 0xc829, 0xaa7f, 0xc829, 0x21, 0 - .dw 0xaac0, 0xc829, 0xaaff, 0xc829, 0x21, 0 - .dw 0xab40, 0xc829, 0xab7f, 0xc829, 0x21, 0 - .dw 0xabc0, 0xc829, 0xabff, 0xc829, 0x21, 0 - .dw 0xac40, 0xc829, 0xac7f, 0xc829, 0x21, 0 - .dw 0xacc0, 0xc829, 0xacff, 0xc829, 0x21, 0 - .dw 0xad40, 0xc829, 0xad7f, 0xc829, 0x21, 0 - .dw 0xadc0, 0xc829, 0xadff, 0xc829, 0x21, 0 - .dw 0xae40, 0xc829, 0xae7f, 0xc829, 0x21, 0 - .dw 0xaec0, 0xc829, 0xaeff, 0xc829, 0x21, 0 - .dw 0xaf40, 0xc829, 0xaf7f, 0xc829, 0x21, 0 - .dw 0xafc0, 0xc829, 0xafff, 0xc829, 0x21, 0 - .dw 0xb040, 0xc829, 0xb07f, 0xc829, 0x21, 0 - .dw 0xb0c0, 0xc829, 0xb0ff, 0xc829, 0x21, 0 - .dw 0xb140, 0xc829, 0xb17f, 0xc829, 0x21, 0 - .dw 0xb1c0, 0xc829, 0xb1ff, 0xc829, 0x21, 0 - .dw 0xb240, 0xc829, 0xb27f, 0xc829, 0x21, 0 - .dw 0xb2c0, 0xc829, 0xb2ff, 0xc829, 0x21, 0 - .dw 0xb340, 0xc829, 0xb37f, 0xc829, 0x21, 0 - .dw 0xb3c0, 0xc829, 0xb3ff, 0xc829, 0x21, 0 - .dw 0xb440, 0xc829, 0xb47f, 0xc829, 0x21, 0 - .dw 0xb4c0, 0xc829, 0xb4ff, 0xc829, 0x21, 0 - .dw 0xb540, 0xc829, 0xb57f, 0xc829, 0x21, 0 - .dw 0xb5c0, 0xc829, 0xb5ff, 0xc829, 0x21, 0 - .dw 0xb640, 0xc829, 0xb67f, 0xc829, 0x21, 0 - .dw 0xb6c0, 0xc829, 0xb6ff, 0xc829, 0x21, 0 - .dw 0xb740, 0xc829, 0xb77f, 0xc829, 0x21, 0 - .dw 0xb7c0, 0xc829, 0xb7ff, 0xc829, 0x21, 0 - .dw 0xb840, 0xc829, 0xb87f, 0xc829, 0x21, 0 - .dw 0xb8c0, 0xc829, 0xb8ff, 0xc829, 0x21, 0 - .dw 0xb940, 0xc829, 0xb97f, 0xc829, 0x21, 0 - .dw 0xb9c0, 0xc829, 0xdfff, 0xc829, 0x21, 0 - .dw 0xe040, 0xc829, 0xe07f, 0xc829, 0x21, 0 - .dw 0xe0c0, 0xc829, 0xe0ff, 0xc829, 0x21, 0 - .dw 0xe140, 0xc829, 0xe17f, 0xc829, 0x21, 0 - .dw 0xe1c0, 0xc829, 0xe1ff, 0xc829, 0x21, 0 - .dw 0xe240, 0xc829, 0xe27f, 0xc829, 0x21, 0 - .dw 0xe2c0, 0xc829, 0xe2ff, 0xc829, 0x21, 0 - .dw 0xe340, 0xc829, 0xe37f, 0xc829, 0x21, 0 - .dw 0xe3c0, 0xc829, 0xe3ff, 0xc829, 0x21, 0 - .dw 0xe440, 0xc829, 0xe47f, 0xc829, 0x21, 0 - .dw 0xe4c0, 0xc829, 0xe4ff, 0xc829, 0x21, 0 - .dw 0xe540, 0xc829, 0xe57f, 0xc829, 0x21, 0 - .dw 0xe5c0, 0xc829, 0xe5ff, 0xc829, 0x21, 0 - .dw 0xe640, 0xc829, 0xe67f, 0xc829, 0x21, 0 - .dw 0xe6c0, 0xc829, 0xe6ff, 0xc829, 0x21, 0 - .dw 0xe740, 0xc829, 0xe77f, 0xc829, 0x21, 0 - .dw 0xe7c0, 0xc829, 0xe7ff, 0xc829, 0x21, 0 - .dw 0xe840, 0xc829, 0xe87f, 0xc829, 0x21, 0 - .dw 0xe8c0, 0xc829, 0xe8ff, 0xc829, 0x21, 0 - .dw 0xe940, 0xc829, 0xe97f, 0xc829, 0x21, 0 - .dw 0xe9c0, 0xc829, 0xe9ff, 0xc829, 0x21, 0 - .dw 0xea40, 0xc829, 0xea7f, 0xc829, 0x21, 0 - .dw 0xeac0, 0xc829, 0xeaff, 0xc829, 0x21, 0 - .dw 0xeb40, 0xc829, 0xeb7f, 0xc829, 0x21, 0 - .dw 0xebc0, 0xc829, 0xebff, 0xc829, 0x21, 0 - .dw 0xec40, 0xc829, 0xec7f, 0xc829, 0x21, 0 - .dw 0xecc0, 0xc829, 0xecff, 0xc829, 0x21, 0 - .dw 0xed40, 0xc829, 0xed7f, 0xc829, 0x21, 0 - .dw 0xedc0, 0xc829, 0xedff, 0xc829, 0x21, 0 - .dw 0xee40, 0xc829, 0xee7f, 0xc829, 0x21, 0 - .dw 0xeec0, 0xc829, 0xeeff, 0xc829, 0x21, 0 - .dw 0xef40, 0xc829, 0xef7f, 0xc829, 0x21, 0 - .dw 0xefc0, 0xc829, 0xefff, 0xc829, 0x21, 0 - .dw 0xf040, 0xc829, 0xf07f, 0xc829, 0x21, 0 - .dw 0xf0c0, 0xc829, 0xf0ff, 0xc829, 0x21, 0 - .dw 0xf140, 0xc829, 0xf17f, 0xc829, 0x21, 0 - .dw 0xf1c0, 0xc829, 0xf1ff, 0xc829, 0x21, 0 - .dw 0xf240, 0xc829, 0xf27f, 0xc829, 0x21, 0 - .dw 0xf2c0, 0xc829, 0xf2ff, 0xc829, 0x21, 0 - .dw 0xf340, 0xc829, 0xf37f, 0xc829, 0x21, 0 - .dw 0xf3c0, 0xc829, 0xf3ff, 0xc829, 0x21, 0 - .dw 0xf440, 0xc829, 0xf47f, 0xc829, 0x21, 0 - .dw 0xf4c0, 0xc829, 0xf4ff, 0xc829, 0x21, 0 - .dw 0xf540, 0xc829, 0xf57f, 0xc829, 0x21, 0 - .dw 0xf5c0, 0xc829, 0xf5ff, 0xc829, 0x21, 0 - .dw 0xf640, 0xc829, 0xf67f, 0xc829, 0x21, 0 - .dw 0xf6c0, 0xc829, 0xf6ff, 0xc829, 0x21, 0 - .dw 0xf740, 0xc829, 0xf77f, 0xc829, 0x21, 0 - .dw 0xf7c0, 0xc829, 0xf7ff, 0xc829, 0x21, 0 - .dw 0xf840, 0xc829, 0xf87f, 0xc829, 0x21, 0 - .dw 0xf8c0, 0xc829, 0xf8ff, 0xc829, 0x21, 0 - .dw 0xf940, 0xc829, 0xf97f, 0xc829, 0x21, 0 - .dw 0xf9c0, 0xc829, 0x1fff, 0xc82a, 0x21, 0 - .dw 0x2040, 0xc82a, 0x207f, 0xc82a, 0x21, 0 - .dw 0x20c0, 0xc82a, 0x20ff, 0xc82a, 0x21, 0 - .dw 0x2140, 0xc82a, 0x217f, 0xc82a, 0x21, 0 - .dw 0x21c0, 0xc82a, 0x21ff, 0xc82a, 0x21, 0 - .dw 0x2240, 0xc82a, 0x227f, 0xc82a, 0x21, 0 - .dw 0x22c0, 0xc82a, 0x22ff, 0xc82a, 0x21, 0 - .dw 0x2340, 0xc82a, 0x237f, 0xc82a, 0x21, 0 - .dw 0x23c0, 0xc82a, 0x23ff, 0xc82a, 0x21, 0 - .dw 0x2440, 0xc82a, 0x247f, 0xc82a, 0x21, 0 - .dw 0x24c0, 0xc82a, 0x24ff, 0xc82a, 0x21, 0 - .dw 0x2540, 0xc82a, 0x257f, 0xc82a, 0x21, 0 - .dw 0x25c0, 0xc82a, 0x25ff, 0xc82a, 0x21, 0 - .dw 0x2640, 0xc82a, 0x267f, 0xc82a, 0x21, 0 - .dw 0x26c0, 0xc82a, 0x26ff, 0xc82a, 0x21, 0 - .dw 0x2740, 0xc82a, 0x277f, 0xc82a, 0x21, 0 - .dw 0x27c0, 0xc82a, 0x27ff, 0xc82a, 0x21, 0 - .dw 0x2840, 0xc82a, 0x287f, 0xc82a, 0x21, 0 - .dw 0x28c0, 0xc82a, 0x28ff, 0xc82a, 0x21, 0 - .dw 0x2940, 0xc82a, 0x297f, 0xc82a, 0x21, 0 - .dw 0x29c0, 0xc82a, 0x29ff, 0xc82a, 0x21, 0 - .dw 0x2a40, 0xc82a, 0x2a7f, 0xc82a, 0x21, 0 - .dw 0x2ac0, 0xc82a, 0x2aff, 0xc82a, 0x21, 0 - .dw 0x2b40, 0xc82a, 0x2b7f, 0xc82a, 0x21, 0 - .dw 0x2bc0, 0xc82a, 0x2bff, 0xc82a, 0x21, 0 - .dw 0x2c40, 0xc82a, 0x2c7f, 0xc82a, 0x21, 0 - .dw 0x2cc0, 0xc82a, 0x2cff, 0xc82a, 0x21, 0 - .dw 0x2d40, 0xc82a, 0x2d7f, 0xc82a, 0x21, 0 - .dw 0x2dc0, 0xc82a, 0x2dff, 0xc82a, 0x21, 0 - .dw 0x2e40, 0xc82a, 0x2e7f, 0xc82a, 0x21, 0 - .dw 0x2ec0, 0xc82a, 0x2eff, 0xc82a, 0x21, 0 - .dw 0x2f40, 0xc82a, 0x2f7f, 0xc82a, 0x21, 0 - .dw 0x2fc0, 0xc82a, 0x2fff, 0xc82a, 0x21, 0 - .dw 0x3040, 0xc82a, 0x307f, 0xc82a, 0x21, 0 - .dw 0x30c0, 0xc82a, 0x30ff, 0xc82a, 0x21, 0 - .dw 0x3140, 0xc82a, 0x317f, 0xc82a, 0x21, 0 - .dw 0x31c0, 0xc82a, 0x31ff, 0xc82a, 0x21, 0 - .dw 0x3240, 0xc82a, 0x327f, 0xc82a, 0x21, 0 - .dw 0x32c0, 0xc82a, 0x32ff, 0xc82a, 0x21, 0 - .dw 0x3340, 0xc82a, 0x337f, 0xc82a, 0x21, 0 - .dw 0x33c0, 0xc82a, 0x33ff, 0xc82a, 0x21, 0 - .dw 0x3440, 0xc82a, 0x347f, 0xc82a, 0x21, 0 - .dw 0x34c0, 0xc82a, 0x34ff, 0xc82a, 0x21, 0 - .dw 0x3540, 0xc82a, 0x357f, 0xc82a, 0x21, 0 - .dw 0x35c0, 0xc82a, 0x35ff, 0xc82a, 0x21, 0 - .dw 0x3640, 0xc82a, 0x367f, 0xc82a, 0x21, 0 - .dw 0x36c0, 0xc82a, 0x36ff, 0xc82a, 0x21, 0 - .dw 0x3740, 0xc82a, 0x377f, 0xc82a, 0x21, 0 - .dw 0x37c0, 0xc82a, 0x37ff, 0xc82a, 0x21, 0 - .dw 0x3840, 0xc82a, 0x387f, 0xc82a, 0x21, 0 - .dw 0x38c0, 0xc82a, 0x38ff, 0xc82a, 0x21, 0 - .dw 0x3940, 0xc82a, 0x397f, 0xc82a, 0x21, 0 - .dw 0x39c0, 0xc82a, 0x5fff, 0xc82a, 0x21, 0 - .dw 0x6040, 0xc82a, 0x607f, 0xc82a, 0x21, 0 - .dw 0x60c0, 0xc82a, 0x60ff, 0xc82a, 0x21, 0 - .dw 0x6140, 0xc82a, 0x617f, 0xc82a, 0x21, 0 - .dw 0x61c0, 0xc82a, 0x61ff, 0xc82a, 0x21, 0 - .dw 0x6240, 0xc82a, 0x627f, 0xc82a, 0x21, 0 - .dw 0x62c0, 0xc82a, 0x62ff, 0xc82a, 0x21, 0 - .dw 0x6340, 0xc82a, 0x637f, 0xc82a, 0x21, 0 - .dw 0x63c0, 0xc82a, 0x63ff, 0xc82a, 0x21, 0 - .dw 0x6440, 0xc82a, 0x647f, 0xc82a, 0x21, 0 - .dw 0x64c0, 0xc82a, 0x64ff, 0xc82a, 0x21, 0 - .dw 0x6540, 0xc82a, 0x657f, 0xc82a, 0x21, 0 - .dw 0x65c0, 0xc82a, 0x65ff, 0xc82a, 0x21, 0 - .dw 0x6640, 0xc82a, 0x667f, 0xc82a, 0x21, 0 - .dw 0x66c0, 0xc82a, 0x66ff, 0xc82a, 0x21, 0 - .dw 0x6740, 0xc82a, 0x677f, 0xc82a, 0x21, 0 - .dw 0x67c0, 0xc82a, 0x67ff, 0xc82a, 0x21, 0 - .dw 0x6840, 0xc82a, 0x687f, 0xc82a, 0x21, 0 - .dw 0x68c0, 0xc82a, 0x68ff, 0xc82a, 0x21, 0 - .dw 0x6940, 0xc82a, 0x697f, 0xc82a, 0x21, 0 - .dw 0x69c0, 0xc82a, 0x69ff, 0xc82a, 0x21, 0 - .dw 0x6a40, 0xc82a, 0x6a7f, 0xc82a, 0x21, 0 - .dw 0x6ac0, 0xc82a, 0x6aff, 0xc82a, 0x21, 0 - .dw 0x6b40, 0xc82a, 0x6b7f, 0xc82a, 0x21, 0 - .dw 0x6bc0, 0xc82a, 0x6bff, 0xc82a, 0x21, 0 - .dw 0x6c40, 0xc82a, 0x6c7f, 0xc82a, 0x21, 0 - .dw 0x6cc0, 0xc82a, 0x6cff, 0xc82a, 0x21, 0 - .dw 0x6d40, 0xc82a, 0x6d7f, 0xc82a, 0x21, 0 - .dw 0x6dc0, 0xc82a, 0x6dff, 0xc82a, 0x21, 0 - .dw 0x6e40, 0xc82a, 0x6e7f, 0xc82a, 0x21, 0 - .dw 0x6ec0, 0xc82a, 0x6eff, 0xc82a, 0x21, 0 - .dw 0x6f40, 0xc82a, 0x6f7f, 0xc82a, 0x21, 0 - .dw 0x6fc0, 0xc82a, 0x6fff, 0xc82a, 0x21, 0 - .dw 0x7040, 0xc82a, 0x707f, 0xc82a, 0x21, 0 - .dw 0x70c0, 0xc82a, 0x70ff, 0xc82a, 0x21, 0 - .dw 0x7140, 0xc82a, 0x717f, 0xc82a, 0x21, 0 - .dw 0x71c0, 0xc82a, 0x71ff, 0xc82a, 0x21, 0 - .dw 0x7240, 0xc82a, 0x727f, 0xc82a, 0x21, 0 - .dw 0x72c0, 0xc82a, 0x72ff, 0xc82a, 0x21, 0 - .dw 0x7340, 0xc82a, 0x737f, 0xc82a, 0x21, 0 - .dw 0x73c0, 0xc82a, 0x73ff, 0xc82a, 0x21, 0 - .dw 0x7440, 0xc82a, 0x747f, 0xc82a, 0x21, 0 - .dw 0x74c0, 0xc82a, 0x74ff, 0xc82a, 0x21, 0 - .dw 0x7540, 0xc82a, 0x757f, 0xc82a, 0x21, 0 - .dw 0x75c0, 0xc82a, 0x75ff, 0xc82a, 0x21, 0 - .dw 0x7640, 0xc82a, 0x767f, 0xc82a, 0x21, 0 - .dw 0x76c0, 0xc82a, 0x76ff, 0xc82a, 0x21, 0 - .dw 0x7740, 0xc82a, 0x777f, 0xc82a, 0x21, 0 - .dw 0x77c0, 0xc82a, 0x77ff, 0xc82a, 0x21, 0 - .dw 0x7840, 0xc82a, 0x787f, 0xc82a, 0x21, 0 - .dw 0x78c0, 0xc82a, 0x78ff, 0xc82a, 0x21, 0 - .dw 0x7940, 0xc82a, 0x797f, 0xc82a, 0x21, 0 - .dw 0x79c0, 0xc82a, 0x9fff, 0xc82a, 0x21, 0 - .dw 0xa040, 0xc82a, 0xa07f, 0xc82a, 0x21, 0 - .dw 0xa0c0, 0xc82a, 0xa0ff, 0xc82a, 0x21, 0 - .dw 0xa140, 0xc82a, 0xa17f, 0xc82a, 0x21, 0 - .dw 0xa1c0, 0xc82a, 0xa1ff, 0xc82a, 0x21, 0 - .dw 0xa240, 0xc82a, 0xa27f, 0xc82a, 0x21, 0 - .dw 0xa2c0, 0xc82a, 0xa2ff, 0xc82a, 0x21, 0 - .dw 0xa340, 0xc82a, 0xa37f, 0xc82a, 0x21, 0 - .dw 0xa3c0, 0xc82a, 0xa3ff, 0xc82a, 0x21, 0 - .dw 0xa440, 0xc82a, 0xa47f, 0xc82a, 0x21, 0 - .dw 0xa4c0, 0xc82a, 0xa4ff, 0xc82a, 0x21, 0 - .dw 0xa540, 0xc82a, 0xa57f, 0xc82a, 0x21, 0 - .dw 0xa5c0, 0xc82a, 0xa5ff, 0xc82a, 0x21, 0 - .dw 0xa640, 0xc82a, 0xa67f, 0xc82a, 0x21, 0 - .dw 0xa6c0, 0xc82a, 0xa6ff, 0xc82a, 0x21, 0 - .dw 0xa740, 0xc82a, 0xa77f, 0xc82a, 0x21, 0 - .dw 0xa7c0, 0xc82a, 0xa7ff, 0xc82a, 0x21, 0 - .dw 0xa840, 0xc82a, 0xa87f, 0xc82a, 0x21, 0 - .dw 0xa8c0, 0xc82a, 0xa8ff, 0xc82a, 0x21, 0 - .dw 0xa940, 0xc82a, 0xa97f, 0xc82a, 0x21, 0 - .dw 0xa9c0, 0xc82a, 0xa9ff, 0xc82a, 0x21, 0 - .dw 0xaa40, 0xc82a, 0xaa7f, 0xc82a, 0x21, 0 - .dw 0xaac0, 0xc82a, 0xaaff, 0xc82a, 0x21, 0 - .dw 0xab40, 0xc82a, 0xab7f, 0xc82a, 0x21, 0 - .dw 0xabc0, 0xc82a, 0xabff, 0xc82a, 0x21, 0 - .dw 0xac40, 0xc82a, 0xac7f, 0xc82a, 0x21, 0 - .dw 0xacc0, 0xc82a, 0xacff, 0xc82a, 0x21, 0 - .dw 0xad40, 0xc82a, 0xad7f, 0xc82a, 0x21, 0 - .dw 0xadc0, 0xc82a, 0xadff, 0xc82a, 0x21, 0 - .dw 0xae40, 0xc82a, 0xae7f, 0xc82a, 0x21, 0 - .dw 0xaec0, 0xc82a, 0xaeff, 0xc82a, 0x21, 0 - .dw 0xaf40, 0xc82a, 0xaf7f, 0xc82a, 0x21, 0 - .dw 0xafc0, 0xc82a, 0xafff, 0xc82a, 0x21, 0 - .dw 0xb040, 0xc82a, 0xb07f, 0xc82a, 0x21, 0 - .dw 0xb0c0, 0xc82a, 0xb0ff, 0xc82a, 0x21, 0 - .dw 0xb140, 0xc82a, 0xb17f, 0xc82a, 0x21, 0 - .dw 0xb1c0, 0xc82a, 0xb1ff, 0xc82a, 0x21, 0 - .dw 0xb240, 0xc82a, 0xb27f, 0xc82a, 0x21, 0 - .dw 0xb2c0, 0xc82a, 0xb2ff, 0xc82a, 0x21, 0 - .dw 0xb340, 0xc82a, 0xb37f, 0xc82a, 0x21, 0 - .dw 0xb3c0, 0xc82a, 0xb3ff, 0xc82a, 0x21, 0 - .dw 0xb440, 0xc82a, 0xb47f, 0xc82a, 0x21, 0 - .dw 0xb4c0, 0xc82a, 0xb4ff, 0xc82a, 0x21, 0 - .dw 0xb540, 0xc82a, 0xb57f, 0xc82a, 0x21, 0 - .dw 0xb5c0, 0xc82a, 0xb5ff, 0xc82a, 0x21, 0 - .dw 0xb640, 0xc82a, 0xb67f, 0xc82a, 0x21, 0 - .dw 0xb6c0, 0xc82a, 0xb6ff, 0xc82a, 0x21, 0 - .dw 0xb740, 0xc82a, 0xb77f, 0xc82a, 0x21, 0 - .dw 0xb7c0, 0xc82a, 0xb7ff, 0xc82a, 0x21, 0 - .dw 0xb840, 0xc82a, 0xb87f, 0xc82a, 0x21, 0 - .dw 0xb8c0, 0xc82a, 0xb8ff, 0xc82a, 0x21, 0 - .dw 0xb940, 0xc82a, 0xb97f, 0xc82a, 0x21, 0 - .dw 0xb9c0, 0xc82a, 0xdfff, 0xc82a, 0x21, 0 - .dw 0xe040, 0xc82a, 0xe07f, 0xc82a, 0x21, 0 - .dw 0xe0c0, 0xc82a, 0xe0ff, 0xc82a, 0x21, 0 - .dw 0xe140, 0xc82a, 0xe17f, 0xc82a, 0x21, 0 - .dw 0xe1c0, 0xc82a, 0xe1ff, 0xc82a, 0x21, 0 - .dw 0xe240, 0xc82a, 0xe27f, 0xc82a, 0x21, 0 - .dw 0xe2c0, 0xc82a, 0xe2ff, 0xc82a, 0x21, 0 - .dw 0xe340, 0xc82a, 0xe37f, 0xc82a, 0x21, 0 - .dw 0xe3c0, 0xc82a, 0xe3ff, 0xc82a, 0x21, 0 - .dw 0xe440, 0xc82a, 0xe47f, 0xc82a, 0x21, 0 - .dw 0xe4c0, 0xc82a, 0xe4ff, 0xc82a, 0x21, 0 - .dw 0xe540, 0xc82a, 0xe57f, 0xc82a, 0x21, 0 - .dw 0xe5c0, 0xc82a, 0xe5ff, 0xc82a, 0x21, 0 - .dw 0xe640, 0xc82a, 0xe67f, 0xc82a, 0x21, 0 - .dw 0xe6c0, 0xc82a, 0xe6ff, 0xc82a, 0x21, 0 - .dw 0xe740, 0xc82a, 0xe77f, 0xc82a, 0x21, 0 - .dw 0xe7c0, 0xc82a, 0xe7ff, 0xc82a, 0x21, 0 - .dw 0xe840, 0xc82a, 0xe87f, 0xc82a, 0x21, 0 - .dw 0xe8c0, 0xc82a, 0xe8ff, 0xc82a, 0x21, 0 - .dw 0xe940, 0xc82a, 0xe97f, 0xc82a, 0x21, 0 - .dw 0xe9c0, 0xc82a, 0xe9ff, 0xc82a, 0x21, 0 - .dw 0xea40, 0xc82a, 0xea7f, 0xc82a, 0x21, 0 - .dw 0xeac0, 0xc82a, 0xeaff, 0xc82a, 0x21, 0 - .dw 0xeb40, 0xc82a, 0xeb7f, 0xc82a, 0x21, 0 - .dw 0xebc0, 0xc82a, 0xebff, 0xc82a, 0x21, 0 - .dw 0xec40, 0xc82a, 0xec7f, 0xc82a, 0x21, 0 - .dw 0xecc0, 0xc82a, 0xecff, 0xc82a, 0x21, 0 - .dw 0xed40, 0xc82a, 0xed7f, 0xc82a, 0x21, 0 - .dw 0xedc0, 0xc82a, 0xedff, 0xc82a, 0x21, 0 - .dw 0xee40, 0xc82a, 0xee7f, 0xc82a, 0x21, 0 - .dw 0xeec0, 0xc82a, 0xeeff, 0xc82a, 0x21, 0 - .dw 0xef40, 0xc82a, 0xef7f, 0xc82a, 0x21, 0 - .dw 0xefc0, 0xc82a, 0xefff, 0xc82a, 0x21, 0 - .dw 0xf040, 0xc82a, 0xf07f, 0xc82a, 0x21, 0 - .dw 0xf0c0, 0xc82a, 0xf0ff, 0xc82a, 0x21, 0 - .dw 0xf140, 0xc82a, 0xf17f, 0xc82a, 0x21, 0 - .dw 0xf1c0, 0xc82a, 0xf1ff, 0xc82a, 0x21, 0 - .dw 0xf240, 0xc82a, 0xf27f, 0xc82a, 0x21, 0 - .dw 0xf2c0, 0xc82a, 0xf2ff, 0xc82a, 0x21, 0 - .dw 0xf340, 0xc82a, 0xf37f, 0xc82a, 0x21, 0 - .dw 0xf3c0, 0xc82a, 0xf3ff, 0xc82a, 0x21, 0 - .dw 0xf440, 0xc82a, 0xf47f, 0xc82a, 0x21, 0 - .dw 0xf4c0, 0xc82a, 0xf4ff, 0xc82a, 0x21, 0 - .dw 0xf540, 0xc82a, 0xf57f, 0xc82a, 0x21, 0 - .dw 0xf5c0, 0xc82a, 0xf5ff, 0xc82a, 0x21, 0 - .dw 0xf640, 0xc82a, 0xf67f, 0xc82a, 0x21, 0 - .dw 0xf6c0, 0xc82a, 0xf6ff, 0xc82a, 0x21, 0 - .dw 0xf740, 0xc82a, 0xf77f, 0xc82a, 0x21, 0 - .dw 0xf7c0, 0xc82a, 0xf7ff, 0xc82a, 0x21, 0 - .dw 0xf840, 0xc82a, 0xf87f, 0xc82a, 0x21, 0 - .dw 0xf8c0, 0xc82a, 0xf8ff, 0xc82a, 0x21, 0 - .dw 0xf940, 0xc82a, 0xf97f, 0xc82a, 0x21, 0 - .dw 0xf9c0, 0xc82a, 0x1fff, 0xc82b, 0x21, 0 - .dw 0x2040, 0xc82b, 0x207f, 0xc82b, 0x21, 0 - .dw 0x20c0, 0xc82b, 0x20ff, 0xc82b, 0x21, 0 - .dw 0x2140, 0xc82b, 0x217f, 0xc82b, 0x21, 0 - .dw 0x21c0, 0xc82b, 0x21ff, 0xc82b, 0x21, 0 - .dw 0x2240, 0xc82b, 0x227f, 0xc82b, 0x21, 0 - .dw 0x22c0, 0xc82b, 0x22ff, 0xc82b, 0x21, 0 - .dw 0x2340, 0xc82b, 0x237f, 0xc82b, 0x21, 0 - .dw 0x23c0, 0xc82b, 0x23ff, 0xc82b, 0x21, 0 - .dw 0x2440, 0xc82b, 0x247f, 0xc82b, 0x21, 0 - .dw 0x24c0, 0xc82b, 0x24ff, 0xc82b, 0x21, 0 - .dw 0x2540, 0xc82b, 0x257f, 0xc82b, 0x21, 0 - .dw 0x25c0, 0xc82b, 0x25ff, 0xc82b, 0x21, 0 - .dw 0x2640, 0xc82b, 0x267f, 0xc82b, 0x21, 0 - .dw 0x26c0, 0xc82b, 0x26ff, 0xc82b, 0x21, 0 - .dw 0x2740, 0xc82b, 0x277f, 0xc82b, 0x21, 0 - .dw 0x27c0, 0xc82b, 0x27ff, 0xc82b, 0x21, 0 - .dw 0x2840, 0xc82b, 0x287f, 0xc82b, 0x21, 0 - .dw 0x28c0, 0xc82b, 0x28ff, 0xc82b, 0x21, 0 - .dw 0x2940, 0xc82b, 0x297f, 0xc82b, 0x21, 0 - .dw 0x29c0, 0xc82b, 0x29ff, 0xc82b, 0x21, 0 - .dw 0x2a40, 0xc82b, 0x2a7f, 0xc82b, 0x21, 0 - .dw 0x2ac0, 0xc82b, 0x2aff, 0xc82b, 0x21, 0 - .dw 0x2b40, 0xc82b, 0x2b7f, 0xc82b, 0x21, 0 - .dw 0x2bc0, 0xc82b, 0x2bff, 0xc82b, 0x21, 0 - .dw 0x2c40, 0xc82b, 0x2c7f, 0xc82b, 0x21, 0 - .dw 0x2cc0, 0xc82b, 0x2cff, 0xc82b, 0x21, 0 - .dw 0x2d40, 0xc82b, 0x2d7f, 0xc82b, 0x21, 0 - .dw 0x2dc0, 0xc82b, 0x2dff, 0xc82b, 0x21, 0 - .dw 0x2e40, 0xc82b, 0x2e7f, 0xc82b, 0x21, 0 - .dw 0x2ec0, 0xc82b, 0x2eff, 0xc82b, 0x21, 0 - .dw 0x2f40, 0xc82b, 0x2f7f, 0xc82b, 0x21, 0 - .dw 0x2fc0, 0xc82b, 0x2fff, 0xc82b, 0x21, 0 - .dw 0x3040, 0xc82b, 0x307f, 0xc82b, 0x21, 0 - .dw 0x30c0, 0xc82b, 0x30ff, 0xc82b, 0x21, 0 - .dw 0x3140, 0xc82b, 0x317f, 0xc82b, 0x21, 0 - .dw 0x31c0, 0xc82b, 0x31ff, 0xc82b, 0x21, 0 - .dw 0x3240, 0xc82b, 0x327f, 0xc82b, 0x21, 0 - .dw 0x32c0, 0xc82b, 0x32ff, 0xc82b, 0x21, 0 - .dw 0x3340, 0xc82b, 0x337f, 0xc82b, 0x21, 0 - .dw 0x33c0, 0xc82b, 0x33ff, 0xc82b, 0x21, 0 - .dw 0x3440, 0xc82b, 0x347f, 0xc82b, 0x21, 0 - .dw 0x34c0, 0xc82b, 0x34ff, 0xc82b, 0x21, 0 - .dw 0x3540, 0xc82b, 0x357f, 0xc82b, 0x21, 0 - .dw 0x35c0, 0xc82b, 0x35ff, 0xc82b, 0x21, 0 - .dw 0x3640, 0xc82b, 0x367f, 0xc82b, 0x21, 0 - .dw 0x36c0, 0xc82b, 0x36ff, 0xc82b, 0x21, 0 - .dw 0x3740, 0xc82b, 0x377f, 0xc82b, 0x21, 0 - .dw 0x37c0, 0xc82b, 0x37ff, 0xc82b, 0x21, 0 - .dw 0x3840, 0xc82b, 0x387f, 0xc82b, 0x21, 0 - .dw 0x38c0, 0xc82b, 0x38ff, 0xc82b, 0x21, 0 - .dw 0x3940, 0xc82b, 0x397f, 0xc82b, 0x21, 0 - .dw 0x39c0, 0xc82b, 0xffff, 0xc82b, 0x21, 0 - .dw 0x0040, 0xc82c, 0x007f, 0xc82c, 0x21, 0 - .dw 0x00c0, 0xc82c, 0x00ff, 0xc82c, 0x21, 0 - .dw 0x0140, 0xc82c, 0x017f, 0xc82c, 0x21, 0 - .dw 0x01c0, 0xc82c, 0x01ff, 0xc82c, 0x21, 0 - .dw 0x0240, 0xc82c, 0x027f, 0xc82c, 0x21, 0 - .dw 0x02c0, 0xc82c, 0x02ff, 0xc82c, 0x21, 0 - .dw 0x0340, 0xc82c, 0x037f, 0xc82c, 0x21, 0 - .dw 0x03c0, 0xc82c, 0x03ff, 0xc82c, 0x21, 0 - .dw 0x0440, 0xc82c, 0x047f, 0xc82c, 0x21, 0 - .dw 0x04c0, 0xc82c, 0x04ff, 0xc82c, 0x21, 0 - .dw 0x0540, 0xc82c, 0x057f, 0xc82c, 0x21, 0 - .dw 0x05c0, 0xc82c, 0x05ff, 0xc82c, 0x21, 0 - .dw 0x0640, 0xc82c, 0x067f, 0xc82c, 0x21, 0 - .dw 0x06c0, 0xc82c, 0x06ff, 0xc82c, 0x21, 0 - .dw 0x0740, 0xc82c, 0x077f, 0xc82c, 0x21, 0 - .dw 0x07c0, 0xc82c, 0x07ff, 0xc82c, 0x21, 0 - .dw 0x0840, 0xc82c, 0x087f, 0xc82c, 0x21, 0 - .dw 0x08c0, 0xc82c, 0x08ff, 0xc82c, 0x21, 0 - .dw 0x0940, 0xc82c, 0x097f, 0xc82c, 0x21, 0 - .dw 0x09c0, 0xc82c, 0x09ff, 0xc82c, 0x21, 0 - .dw 0x0a40, 0xc82c, 0x0a7f, 0xc82c, 0x21, 0 - .dw 0x0ac0, 0xc82c, 0x0aff, 0xc82c, 0x21, 0 - .dw 0x0b40, 0xc82c, 0x0b7f, 0xc82c, 0x21, 0 - .dw 0x0bc0, 0xc82c, 0x0bff, 0xc82c, 0x21, 0 - .dw 0x0c40, 0xc82c, 0x0c7f, 0xc82c, 0x21, 0 - .dw 0x0cc0, 0xc82c, 0x0cff, 0xc82c, 0x21, 0 - .dw 0x0d40, 0xc82c, 0x0d7f, 0xc82c, 0x21, 0 - .dw 0x0dc0, 0xc82c, 0x0dff, 0xc82c, 0x21, 0 - .dw 0x0e40, 0xc82c, 0x0e7f, 0xc82c, 0x21, 0 - .dw 0x0ec0, 0xc82c, 0x0eff, 0xc82c, 0x21, 0 - .dw 0x0f40, 0xc82c, 0x0f7f, 0xc82c, 0x21, 0 - .dw 0x0fc0, 0xc82c, 0x0fff, 0xc82c, 0x21, 0 - .dw 0x1040, 0xc82c, 0x107f, 0xc82c, 0x21, 0 - .dw 0x10c0, 0xc82c, 0x10ff, 0xc82c, 0x21, 0 - .dw 0x1140, 0xc82c, 0x117f, 0xc82c, 0x21, 0 - .dw 0x11c0, 0xc82c, 0x11ff, 0xc82c, 0x21, 0 - .dw 0x1240, 0xc82c, 0x127f, 0xc82c, 0x21, 0 - .dw 0x12c0, 0xc82c, 0x12ff, 0xc82c, 0x21, 0 - .dw 0x1340, 0xc82c, 0x137f, 0xc82c, 0x21, 0 - .dw 0x13c0, 0xc82c, 0x13ff, 0xc82c, 0x21, 0 - .dw 0x1440, 0xc82c, 0x147f, 0xc82c, 0x21, 0 - .dw 0x14c0, 0xc82c, 0x14ff, 0xc82c, 0x21, 0 - .dw 0x1540, 0xc82c, 0x157f, 0xc82c, 0x21, 0 - .dw 0x15c0, 0xc82c, 0x15ff, 0xc82c, 0x21, 0 - .dw 0x1640, 0xc82c, 0x167f, 0xc82c, 0x21, 0 - .dw 0x16c0, 0xc82c, 0x16ff, 0xc82c, 0x21, 0 - .dw 0x1740, 0xc82c, 0x177f, 0xc82c, 0x21, 0 - .dw 0x17c0, 0xc82c, 0x17ff, 0xc82c, 0x21, 0 - .dw 0x1840, 0xc82c, 0x187f, 0xc82c, 0x21, 0 - .dw 0x18c0, 0xc82c, 0x18ff, 0xc82c, 0x21, 0 - .dw 0x1940, 0xc82c, 0x197f, 0xc82c, 0x21, 0 - .dw 0x19c0, 0xc82c, 0x1fff, 0xc82c, 0x21, 0 - .dw 0x2040, 0xc82c, 0x207f, 0xc82c, 0x21, 0 - .dw 0x20c0, 0xc82c, 0x20ff, 0xc82c, 0x21, 0 - .dw 0x2140, 0xc82c, 0x217f, 0xc82c, 0x21, 0 - .dw 0x21c0, 0xc82c, 0x21ff, 0xc82c, 0x21, 0 - .dw 0x2240, 0xc82c, 0x227f, 0xc82c, 0x21, 0 - .dw 0x22c0, 0xc82c, 0x22ff, 0xc82c, 0x21, 0 - .dw 0x2340, 0xc82c, 0x237f, 0xc82c, 0x21, 0 - .dw 0x23c0, 0xc82c, 0x23ff, 0xc82c, 0x21, 0 - .dw 0x2440, 0xc82c, 0x247f, 0xc82c, 0x21, 0 - .dw 0x24c0, 0xc82c, 0x24ff, 0xc82c, 0x21, 0 - .dw 0x2540, 0xc82c, 0x257f, 0xc82c, 0x21, 0 - .dw 0x25c0, 0xc82c, 0x25ff, 0xc82c, 0x21, 0 - .dw 0x2640, 0xc82c, 0x267f, 0xc82c, 0x21, 0 - .dw 0x26c0, 0xc82c, 0x26ff, 0xc82c, 0x21, 0 - .dw 0x2740, 0xc82c, 0x277f, 0xc82c, 0x21, 0 - .dw 0x27c0, 0xc82c, 0x27ff, 0xc82c, 0x21, 0 - .dw 0x2840, 0xc82c, 0x287f, 0xc82c, 0x21, 0 - .dw 0x28c0, 0xc82c, 0x28ff, 0xc82c, 0x21, 0 - .dw 0x2940, 0xc82c, 0x297f, 0xc82c, 0x21, 0 - .dw 0x29c0, 0xc82c, 0x29ff, 0xc82c, 0x21, 0 - .dw 0x2a40, 0xc82c, 0x2a7f, 0xc82c, 0x21, 0 - .dw 0x2ac0, 0xc82c, 0x2aff, 0xc82c, 0x21, 0 - .dw 0x2b40, 0xc82c, 0x2b7f, 0xc82c, 0x21, 0 - .dw 0x2bc0, 0xc82c, 0x2bff, 0xc82c, 0x21, 0 - .dw 0x2c40, 0xc82c, 0x2c7f, 0xc82c, 0x21, 0 - .dw 0x2cc0, 0xc82c, 0x2cff, 0xc82c, 0x21, 0 - .dw 0x2d40, 0xc82c, 0x2d7f, 0xc82c, 0x21, 0 - .dw 0x2dc0, 0xc82c, 0x2dff, 0xc82c, 0x21, 0 - .dw 0x2e40, 0xc82c, 0x2e7f, 0xc82c, 0x21, 0 - .dw 0x2ec0, 0xc82c, 0x2eff, 0xc82c, 0x21, 0 - .dw 0x2f40, 0xc82c, 0x2f7f, 0xc82c, 0x21, 0 - .dw 0x2fc0, 0xc82c, 0x2fff, 0xc82c, 0x21, 0 - .dw 0x3040, 0xc82c, 0x307f, 0xc82c, 0x21, 0 - .dw 0x30c0, 0xc82c, 0x30ff, 0xc82c, 0x21, 0 - .dw 0x3140, 0xc82c, 0x317f, 0xc82c, 0x21, 0 - .dw 0x31c0, 0xc82c, 0x31ff, 0xc82c, 0x21, 0 - .dw 0x3240, 0xc82c, 0x327f, 0xc82c, 0x21, 0 - .dw 0x32c0, 0xc82c, 0x32ff, 0xc82c, 0x21, 0 - .dw 0x3340, 0xc82c, 0x337f, 0xc82c, 0x21, 0 - .dw 0x33c0, 0xc82c, 0x33ff, 0xc82c, 0x21, 0 - .dw 0x3440, 0xc82c, 0x347f, 0xc82c, 0x21, 0 - .dw 0x34c0, 0xc82c, 0x34ff, 0xc82c, 0x21, 0 - .dw 0x3540, 0xc82c, 0x357f, 0xc82c, 0x21, 0 - .dw 0x35c0, 0xc82c, 0x35ff, 0xc82c, 0x21, 0 - .dw 0x3640, 0xc82c, 0x367f, 0xc82c, 0x21, 0 - .dw 0x36c0, 0xc82c, 0x36ff, 0xc82c, 0x21, 0 - .dw 0x3740, 0xc82c, 0x377f, 0xc82c, 0x21, 0 - .dw 0x37c0, 0xc82c, 0x37ff, 0xc82c, 0x21, 0 - .dw 0x3840, 0xc82c, 0x387f, 0xc82c, 0x21, 0 - .dw 0x38c0, 0xc82c, 0x38ff, 0xc82c, 0x21, 0 - .dw 0x3940, 0xc82c, 0x397f, 0xc82c, 0x21, 0 - .dw 0x39c0, 0xc82c, 0x3fff, 0xc82c, 0x21, 0 - .dw 0x4040, 0xc82c, 0x407f, 0xc82c, 0x21, 0 - .dw 0x40c0, 0xc82c, 0x40ff, 0xc82c, 0x21, 0 - .dw 0x4140, 0xc82c, 0x417f, 0xc82c, 0x21, 0 - .dw 0x41c0, 0xc82c, 0x41ff, 0xc82c, 0x21, 0 - .dw 0x4240, 0xc82c, 0x427f, 0xc82c, 0x21, 0 - .dw 0x42c0, 0xc82c, 0x42ff, 0xc82c, 0x21, 0 - .dw 0x4340, 0xc82c, 0x437f, 0xc82c, 0x21, 0 - .dw 0x43c0, 0xc82c, 0x43ff, 0xc82c, 0x21, 0 - .dw 0x4440, 0xc82c, 0x447f, 0xc82c, 0x21, 0 - .dw 0x44c0, 0xc82c, 0x44ff, 0xc82c, 0x21, 0 - .dw 0x4540, 0xc82c, 0x457f, 0xc82c, 0x21, 0 - .dw 0x45c0, 0xc82c, 0x45ff, 0xc82c, 0x21, 0 - .dw 0x4640, 0xc82c, 0x467f, 0xc82c, 0x21, 0 - .dw 0x46c0, 0xc82c, 0x46ff, 0xc82c, 0x21, 0 - .dw 0x4740, 0xc82c, 0x477f, 0xc82c, 0x21, 0 - .dw 0x47c0, 0xc82c, 0x47ff, 0xc82c, 0x21, 0 - .dw 0x4840, 0xc82c, 0x487f, 0xc82c, 0x21, 0 - .dw 0x48c0, 0xc82c, 0x48ff, 0xc82c, 0x21, 0 - .dw 0x4940, 0xc82c, 0x497f, 0xc82c, 0x21, 0 - .dw 0x49c0, 0xc82c, 0x49ff, 0xc82c, 0x21, 0 - .dw 0x4a40, 0xc82c, 0x4a7f, 0xc82c, 0x21, 0 - .dw 0x4ac0, 0xc82c, 0x4aff, 0xc82c, 0x21, 0 - .dw 0x4b40, 0xc82c, 0x4b7f, 0xc82c, 0x21, 0 - .dw 0x4bc0, 0xc82c, 0x4bff, 0xc82c, 0x21, 0 - .dw 0x4c40, 0xc82c, 0x4c7f, 0xc82c, 0x21, 0 - .dw 0x4cc0, 0xc82c, 0x4cff, 0xc82c, 0x21, 0 - .dw 0x4d40, 0xc82c, 0x4d7f, 0xc82c, 0x21, 0 - .dw 0x4dc0, 0xc82c, 0x4dff, 0xc82c, 0x21, 0 - .dw 0x4e40, 0xc82c, 0x4e7f, 0xc82c, 0x21, 0 - .dw 0x4ec0, 0xc82c, 0x4eff, 0xc82c, 0x21, 0 - .dw 0x4f40, 0xc82c, 0x4f7f, 0xc82c, 0x21, 0 - .dw 0x4fc0, 0xc82c, 0x4fff, 0xc82c, 0x21, 0 - .dw 0x5040, 0xc82c, 0x507f, 0xc82c, 0x21, 0 - .dw 0x50c0, 0xc82c, 0x50ff, 0xc82c, 0x21, 0 - .dw 0x5140, 0xc82c, 0x517f, 0xc82c, 0x21, 0 - .dw 0x51c0, 0xc82c, 0x51ff, 0xc82c, 0x21, 0 - .dw 0x5240, 0xc82c, 0x527f, 0xc82c, 0x21, 0 - .dw 0x52c0, 0xc82c, 0x52ff, 0xc82c, 0x21, 0 - .dw 0x5340, 0xc82c, 0x537f, 0xc82c, 0x21, 0 - .dw 0x53c0, 0xc82c, 0x53ff, 0xc82c, 0x21, 0 - .dw 0x5440, 0xc82c, 0x547f, 0xc82c, 0x21, 0 - .dw 0x54c0, 0xc82c, 0x54ff, 0xc82c, 0x21, 0 - .dw 0x5540, 0xc82c, 0x557f, 0xc82c, 0x21, 0 - .dw 0x55c0, 0xc82c, 0x55ff, 0xc82c, 0x21, 0 - .dw 0x5640, 0xc82c, 0x567f, 0xc82c, 0x21, 0 - .dw 0x56c0, 0xc82c, 0x56ff, 0xc82c, 0x21, 0 - .dw 0x5740, 0xc82c, 0x577f, 0xc82c, 0x21, 0 - .dw 0x57c0, 0xc82c, 0x57ff, 0xc82c, 0x21, 0 - .dw 0x5840, 0xc82c, 0x587f, 0xc82c, 0x21, 0 - .dw 0x58c0, 0xc82c, 0x58ff, 0xc82c, 0x21, 0 - .dw 0x5940, 0xc82c, 0x597f, 0xc82c, 0x21, 0 - .dw 0x59c0, 0xc82c, 0x5fff, 0xc82c, 0x21, 0 - .dw 0x6040, 0xc82c, 0x607f, 0xc82c, 0x21, 0 - .dw 0x60c0, 0xc82c, 0x60ff, 0xc82c, 0x21, 0 - .dw 0x6140, 0xc82c, 0x617f, 0xc82c, 0x21, 0 - .dw 0x61c0, 0xc82c, 0x61ff, 0xc82c, 0x21, 0 - .dw 0x6240, 0xc82c, 0x627f, 0xc82c, 0x21, 0 - .dw 0x62c0, 0xc82c, 0x62ff, 0xc82c, 0x21, 0 - .dw 0x6340, 0xc82c, 0x637f, 0xc82c, 0x21, 0 - .dw 0x63c0, 0xc82c, 0x63ff, 0xc82c, 0x21, 0 - .dw 0x6440, 0xc82c, 0x647f, 0xc82c, 0x21, 0 - .dw 0x64c0, 0xc82c, 0x64ff, 0xc82c, 0x21, 0 - .dw 0x6540, 0xc82c, 0x657f, 0xc82c, 0x21, 0 - .dw 0x65c0, 0xc82c, 0x65ff, 0xc82c, 0x21, 0 - .dw 0x6640, 0xc82c, 0x667f, 0xc82c, 0x21, 0 - .dw 0x66c0, 0xc82c, 0x66ff, 0xc82c, 0x21, 0 - .dw 0x6740, 0xc82c, 0x677f, 0xc82c, 0x21, 0 - .dw 0x67c0, 0xc82c, 0x67ff, 0xc82c, 0x21, 0 - .dw 0x6840, 0xc82c, 0x687f, 0xc82c, 0x21, 0 - .dw 0x68c0, 0xc82c, 0x68ff, 0xc82c, 0x21, 0 - .dw 0x6940, 0xc82c, 0x697f, 0xc82c, 0x21, 0 - .dw 0x69c0, 0xc82c, 0x69ff, 0xc82c, 0x21, 0 - .dw 0x6a40, 0xc82c, 0x6a7f, 0xc82c, 0x21, 0 - .dw 0x6ac0, 0xc82c, 0x6aff, 0xc82c, 0x21, 0 - .dw 0x6b40, 0xc82c, 0x6b7f, 0xc82c, 0x21, 0 - .dw 0x6bc0, 0xc82c, 0x6bff, 0xc82c, 0x21, 0 - .dw 0x6c40, 0xc82c, 0x6c7f, 0xc82c, 0x21, 0 - .dw 0x6cc0, 0xc82c, 0x6cff, 0xc82c, 0x21, 0 - .dw 0x6d40, 0xc82c, 0x6d7f, 0xc82c, 0x21, 0 - .dw 0x6dc0, 0xc82c, 0x6dff, 0xc82c, 0x21, 0 - .dw 0x6e40, 0xc82c, 0x6e7f, 0xc82c, 0x21, 0 - .dw 0x6ec0, 0xc82c, 0x6eff, 0xc82c, 0x21, 0 - .dw 0x6f40, 0xc82c, 0x6f7f, 0xc82c, 0x21, 0 - .dw 0x6fc0, 0xc82c, 0x6fff, 0xc82c, 0x21, 0 - .dw 0x7040, 0xc82c, 0x707f, 0xc82c, 0x21, 0 - .dw 0x70c0, 0xc82c, 0x70ff, 0xc82c, 0x21, 0 - .dw 0x7140, 0xc82c, 0x717f, 0xc82c, 0x21, 0 - .dw 0x71c0, 0xc82c, 0x71ff, 0xc82c, 0x21, 0 - .dw 0x7240, 0xc82c, 0x727f, 0xc82c, 0x21, 0 - .dw 0x72c0, 0xc82c, 0x72ff, 0xc82c, 0x21, 0 - .dw 0x7340, 0xc82c, 0x737f, 0xc82c, 0x21, 0 - .dw 0x73c0, 0xc82c, 0x73ff, 0xc82c, 0x21, 0 - .dw 0x7440, 0xc82c, 0x747f, 0xc82c, 0x21, 0 - .dw 0x74c0, 0xc82c, 0x74ff, 0xc82c, 0x21, 0 - .dw 0x7540, 0xc82c, 0x757f, 0xc82c, 0x21, 0 - .dw 0x75c0, 0xc82c, 0x75ff, 0xc82c, 0x21, 0 - .dw 0x7640, 0xc82c, 0x767f, 0xc82c, 0x21, 0 - .dw 0x76c0, 0xc82c, 0x76ff, 0xc82c, 0x21, 0 - .dw 0x7740, 0xc82c, 0x777f, 0xc82c, 0x21, 0 - .dw 0x77c0, 0xc82c, 0x77ff, 0xc82c, 0x21, 0 - .dw 0x7840, 0xc82c, 0x787f, 0xc82c, 0x21, 0 - .dw 0x78c0, 0xc82c, 0x78ff, 0xc82c, 0x21, 0 - .dw 0x7940, 0xc82c, 0x797f, 0xc82c, 0x21, 0 - .dw 0x79c0, 0xc82c, 0x7fff, 0xc82c, 0x21, 0 - .dw 0x8040, 0xc82c, 0x807f, 0xc82c, 0x21, 0 - .dw 0x80c0, 0xc82c, 0x80ff, 0xc82c, 0x21, 0 - .dw 0x8140, 0xc82c, 0x817f, 0xc82c, 0x21, 0 - .dw 0x81c0, 0xc82c, 0x81ff, 0xc82c, 0x21, 0 - .dw 0x8240, 0xc82c, 0x827f, 0xc82c, 0x21, 0 - .dw 0x82c0, 0xc82c, 0x82ff, 0xc82c, 0x21, 0 - .dw 0x8340, 0xc82c, 0x837f, 0xc82c, 0x21, 0 - .dw 0x83c0, 0xc82c, 0x83ff, 0xc82c, 0x21, 0 - .dw 0x8440, 0xc82c, 0x847f, 0xc82c, 0x21, 0 - .dw 0x84c0, 0xc82c, 0x84ff, 0xc82c, 0x21, 0 - .dw 0x8540, 0xc82c, 0x857f, 0xc82c, 0x21, 0 - .dw 0x85c0, 0xc82c, 0x85ff, 0xc82c, 0x21, 0 - .dw 0x8640, 0xc82c, 0x867f, 0xc82c, 0x21, 0 - .dw 0x86c0, 0xc82c, 0x86ff, 0xc82c, 0x21, 0 - .dw 0x8740, 0xc82c, 0x877f, 0xc82c, 0x21, 0 - .dw 0x87c0, 0xc82c, 0x87ff, 0xc82c, 0x21, 0 - .dw 0x8840, 0xc82c, 0x887f, 0xc82c, 0x21, 0 - .dw 0x88c0, 0xc82c, 0x88ff, 0xc82c, 0x21, 0 - .dw 0x8940, 0xc82c, 0x897f, 0xc82c, 0x21, 0 - .dw 0x89c0, 0xc82c, 0x89ff, 0xc82c, 0x21, 0 - .dw 0x8a40, 0xc82c, 0x8a7f, 0xc82c, 0x21, 0 - .dw 0x8ac0, 0xc82c, 0x8aff, 0xc82c, 0x21, 0 - .dw 0x8b40, 0xc82c, 0x8b7f, 0xc82c, 0x21, 0 - .dw 0x8bc0, 0xc82c, 0x8bff, 0xc82c, 0x21, 0 - .dw 0x8c40, 0xc82c, 0x8c7f, 0xc82c, 0x21, 0 - .dw 0x8cc0, 0xc82c, 0x8cff, 0xc82c, 0x21, 0 - .dw 0x8d40, 0xc82c, 0x8d7f, 0xc82c, 0x21, 0 - .dw 0x8dc0, 0xc82c, 0x8dff, 0xc82c, 0x21, 0 - .dw 0x8e40, 0xc82c, 0x8e7f, 0xc82c, 0x21, 0 - .dw 0x8ec0, 0xc82c, 0x8eff, 0xc82c, 0x21, 0 - .dw 0x8f40, 0xc82c, 0x8f7f, 0xc82c, 0x21, 0 - .dw 0x8fc0, 0xc82c, 0x8fff, 0xc82c, 0x21, 0 - .dw 0x9040, 0xc82c, 0x907f, 0xc82c, 0x21, 0 - .dw 0x90c0, 0xc82c, 0x90ff, 0xc82c, 0x21, 0 - .dw 0x9140, 0xc82c, 0x917f, 0xc82c, 0x21, 0 - .dw 0x91c0, 0xc82c, 0x91ff, 0xc82c, 0x21, 0 - .dw 0x9240, 0xc82c, 0x927f, 0xc82c, 0x21, 0 - .dw 0x92c0, 0xc82c, 0x92ff, 0xc82c, 0x21, 0 - .dw 0x9340, 0xc82c, 0x937f, 0xc82c, 0x21, 0 - .dw 0x93c0, 0xc82c, 0x93ff, 0xc82c, 0x21, 0 - .dw 0x9440, 0xc82c, 0x947f, 0xc82c, 0x21, 0 - .dw 0x94c0, 0xc82c, 0x94ff, 0xc82c, 0x21, 0 - .dw 0x9540, 0xc82c, 0x957f, 0xc82c, 0x21, 0 - .dw 0x95c0, 0xc82c, 0x95ff, 0xc82c, 0x21, 0 - .dw 0x9640, 0xc82c, 0x967f, 0xc82c, 0x21, 0 - .dw 0x96c0, 0xc82c, 0x96ff, 0xc82c, 0x21, 0 - .dw 0x9740, 0xc82c, 0x977f, 0xc82c, 0x21, 0 - .dw 0x97c0, 0xc82c, 0x97ff, 0xc82c, 0x21, 0 - .dw 0x9840, 0xc82c, 0x987f, 0xc82c, 0x21, 0 - .dw 0x98c0, 0xc82c, 0x98ff, 0xc82c, 0x21, 0 - .dw 0x9940, 0xc82c, 0x997f, 0xc82c, 0x21, 0 - .dw 0x99c0, 0xc82c, 0x9fff, 0xc82c, 0x21, 0 - .dw 0xa040, 0xc82c, 0xa07f, 0xc82c, 0x21, 0 - .dw 0xa0c0, 0xc82c, 0xa0ff, 0xc82c, 0x21, 0 - .dw 0xa140, 0xc82c, 0xa17f, 0xc82c, 0x21, 0 - .dw 0xa1c0, 0xc82c, 0xa1ff, 0xc82c, 0x21, 0 - .dw 0xa240, 0xc82c, 0xa27f, 0xc82c, 0x21, 0 - .dw 0xa2c0, 0xc82c, 0xa2ff, 0xc82c, 0x21, 0 - .dw 0xa340, 0xc82c, 0xa37f, 0xc82c, 0x21, 0 - .dw 0xa3c0, 0xc82c, 0xa3ff, 0xc82c, 0x21, 0 - .dw 0xa440, 0xc82c, 0xa47f, 0xc82c, 0x21, 0 - .dw 0xa4c0, 0xc82c, 0xa4ff, 0xc82c, 0x21, 0 - .dw 0xa540, 0xc82c, 0xa57f, 0xc82c, 0x21, 0 - .dw 0xa5c0, 0xc82c, 0xa5ff, 0xc82c, 0x21, 0 - .dw 0xa640, 0xc82c, 0xa67f, 0xc82c, 0x21, 0 - .dw 0xa6c0, 0xc82c, 0xa6ff, 0xc82c, 0x21, 0 - .dw 0xa740, 0xc82c, 0xa77f, 0xc82c, 0x21, 0 - .dw 0xa7c0, 0xc82c, 0xa7ff, 0xc82c, 0x21, 0 - .dw 0xa840, 0xc82c, 0xa87f, 0xc82c, 0x21, 0 - .dw 0xa8c0, 0xc82c, 0xa8ff, 0xc82c, 0x21, 0 - .dw 0xa940, 0xc82c, 0xa97f, 0xc82c, 0x21, 0 - .dw 0xa9c0, 0xc82c, 0xa9ff, 0xc82c, 0x21, 0 - .dw 0xaa40, 0xc82c, 0xaa7f, 0xc82c, 0x21, 0 - .dw 0xaac0, 0xc82c, 0xaaff, 0xc82c, 0x21, 0 - .dw 0xab40, 0xc82c, 0xab7f, 0xc82c, 0x21, 0 - .dw 0xabc0, 0xc82c, 0xabff, 0xc82c, 0x21, 0 - .dw 0xac40, 0xc82c, 0xac7f, 0xc82c, 0x21, 0 - .dw 0xacc0, 0xc82c, 0xacff, 0xc82c, 0x21, 0 - .dw 0xad40, 0xc82c, 0xad7f, 0xc82c, 0x21, 0 - .dw 0xadc0, 0xc82c, 0xadff, 0xc82c, 0x21, 0 - .dw 0xae40, 0xc82c, 0xae7f, 0xc82c, 0x21, 0 - .dw 0xaec0, 0xc82c, 0xaeff, 0xc82c, 0x21, 0 - .dw 0xaf40, 0xc82c, 0xaf7f, 0xc82c, 0x21, 0 - .dw 0xafc0, 0xc82c, 0xafff, 0xc82c, 0x21, 0 - .dw 0xb040, 0xc82c, 0xb07f, 0xc82c, 0x21, 0 - .dw 0xb0c0, 0xc82c, 0xb0ff, 0xc82c, 0x21, 0 - .dw 0xb140, 0xc82c, 0xb17f, 0xc82c, 0x21, 0 - .dw 0xb1c0, 0xc82c, 0xb1ff, 0xc82c, 0x21, 0 - .dw 0xb240, 0xc82c, 0xb27f, 0xc82c, 0x21, 0 - .dw 0xb2c0, 0xc82c, 0xb2ff, 0xc82c, 0x21, 0 - .dw 0xb340, 0xc82c, 0xb37f, 0xc82c, 0x21, 0 - .dw 0xb3c0, 0xc82c, 0xb3ff, 0xc82c, 0x21, 0 - .dw 0xb440, 0xc82c, 0xb47f, 0xc82c, 0x21, 0 - .dw 0xb4c0, 0xc82c, 0xb4ff, 0xc82c, 0x21, 0 - .dw 0xb540, 0xc82c, 0xb57f, 0xc82c, 0x21, 0 - .dw 0xb5c0, 0xc82c, 0xb5ff, 0xc82c, 0x21, 0 - .dw 0xb640, 0xc82c, 0xb67f, 0xc82c, 0x21, 0 - .dw 0xb6c0, 0xc82c, 0xb6ff, 0xc82c, 0x21, 0 - .dw 0xb740, 0xc82c, 0xb77f, 0xc82c, 0x21, 0 - .dw 0xb7c0, 0xc82c, 0xb7ff, 0xc82c, 0x21, 0 - .dw 0xb840, 0xc82c, 0xb87f, 0xc82c, 0x21, 0 - .dw 0xb8c0, 0xc82c, 0xb8ff, 0xc82c, 0x21, 0 - .dw 0xb940, 0xc82c, 0xb97f, 0xc82c, 0x21, 0 - .dw 0xb9c0, 0xc82c, 0xbfff, 0xc82c, 0x21, 0 - .dw 0xc040, 0xc82c, 0xc07f, 0xc82c, 0x21, 0 - .dw 0xc0c0, 0xc82c, 0xc0ff, 0xc82c, 0x21, 0 - .dw 0xc140, 0xc82c, 0xc17f, 0xc82c, 0x21, 0 - .dw 0xc1c0, 0xc82c, 0xc1ff, 0xc82c, 0x21, 0 - .dw 0xc240, 0xc82c, 0xc27f, 0xc82c, 0x21, 0 - .dw 0xc2c0, 0xc82c, 0xc2ff, 0xc82c, 0x21, 0 - .dw 0xc340, 0xc82c, 0xc37f, 0xc82c, 0x21, 0 - .dw 0xc3c0, 0xc82c, 0xc3ff, 0xc82c, 0x21, 0 - .dw 0xc440, 0xc82c, 0xc47f, 0xc82c, 0x21, 0 - .dw 0xc4c0, 0xc82c, 0xc4ff, 0xc82c, 0x21, 0 - .dw 0xc540, 0xc82c, 0xc57f, 0xc82c, 0x21, 0 - .dw 0xc5c0, 0xc82c, 0xc5ff, 0xc82c, 0x21, 0 - .dw 0xc640, 0xc82c, 0xc67f, 0xc82c, 0x21, 0 - .dw 0xc6c0, 0xc82c, 0xc6ff, 0xc82c, 0x21, 0 - .dw 0xc740, 0xc82c, 0xc77f, 0xc82c, 0x21, 0 - .dw 0xc7c0, 0xc82c, 0xc7ff, 0xc82c, 0x21, 0 - .dw 0xc840, 0xc82c, 0xc87f, 0xc82c, 0x21, 0 - .dw 0xc8c0, 0xc82c, 0xc8ff, 0xc82c, 0x21, 0 - .dw 0xc940, 0xc82c, 0xc97f, 0xc82c, 0x21, 0 - .dw 0xc9c0, 0xc82c, 0xc9ff, 0xc82c, 0x21, 0 - .dw 0xca40, 0xc82c, 0xca7f, 0xc82c, 0x21, 0 - .dw 0xcac0, 0xc82c, 0xcaff, 0xc82c, 0x21, 0 - .dw 0xcb40, 0xc82c, 0xcb7f, 0xc82c, 0x21, 0 - .dw 0xcbc0, 0xc82c, 0xcbff, 0xc82c, 0x21, 0 - .dw 0xcc40, 0xc82c, 0xcc7f, 0xc82c, 0x21, 0 - .dw 0xccc0, 0xc82c, 0xccff, 0xc82c, 0x21, 0 - .dw 0xcd40, 0xc82c, 0xcd7f, 0xc82c, 0x21, 0 - .dw 0xcdc0, 0xc82c, 0xcdff, 0xc82c, 0x21, 0 - .dw 0xce40, 0xc82c, 0xce7f, 0xc82c, 0x21, 0 - .dw 0xcec0, 0xc82c, 0xceff, 0xc82c, 0x21, 0 - .dw 0xcf40, 0xc82c, 0xcf7f, 0xc82c, 0x21, 0 - .dw 0xcfc0, 0xc82c, 0xcfff, 0xc82c, 0x21, 0 - .dw 0xd040, 0xc82c, 0xd07f, 0xc82c, 0x21, 0 - .dw 0xd0c0, 0xc82c, 0xd0ff, 0xc82c, 0x21, 0 - .dw 0xd140, 0xc82c, 0xd17f, 0xc82c, 0x21, 0 - .dw 0xd1c0, 0xc82c, 0xd1ff, 0xc82c, 0x21, 0 - .dw 0xd240, 0xc82c, 0xd27f, 0xc82c, 0x21, 0 - .dw 0xd2c0, 0xc82c, 0xd2ff, 0xc82c, 0x21, 0 - .dw 0xd340, 0xc82c, 0xd37f, 0xc82c, 0x21, 0 - .dw 0xd3c0, 0xc82c, 0xd3ff, 0xc82c, 0x21, 0 - .dw 0xd440, 0xc82c, 0xd47f, 0xc82c, 0x21, 0 - .dw 0xd4c0, 0xc82c, 0xd4ff, 0xc82c, 0x21, 0 - .dw 0xd540, 0xc82c, 0xd57f, 0xc82c, 0x21, 0 - .dw 0xd5c0, 0xc82c, 0xd5ff, 0xc82c, 0x21, 0 - .dw 0xd640, 0xc82c, 0xd67f, 0xc82c, 0x21, 0 - .dw 0xd6c0, 0xc82c, 0xd6ff, 0xc82c, 0x21, 0 - .dw 0xd740, 0xc82c, 0xd77f, 0xc82c, 0x21, 0 - .dw 0xd7c0, 0xc82c, 0xd7ff, 0xc82c, 0x21, 0 - .dw 0xd840, 0xc82c, 0xd87f, 0xc82c, 0x21, 0 - .dw 0xd8c0, 0xc82c, 0xd8ff, 0xc82c, 0x21, 0 - .dw 0xd940, 0xc82c, 0xd97f, 0xc82c, 0x21, 0 - .dw 0xd9c0, 0xc82c, 0xdfff, 0xc82c, 0x21, 0 - .dw 0xe040, 0xc82c, 0xe07f, 0xc82c, 0x21, 0 - .dw 0xe0c0, 0xc82c, 0xe0ff, 0xc82c, 0x21, 0 - .dw 0xe140, 0xc82c, 0xe17f, 0xc82c, 0x21, 0 - .dw 0xe1c0, 0xc82c, 0xe1ff, 0xc82c, 0x21, 0 - .dw 0xe240, 0xc82c, 0xe27f, 0xc82c, 0x21, 0 - .dw 0xe2c0, 0xc82c, 0xe2ff, 0xc82c, 0x21, 0 - .dw 0xe340, 0xc82c, 0xe37f, 0xc82c, 0x21, 0 - .dw 0xe3c0, 0xc82c, 0xe3ff, 0xc82c, 0x21, 0 - .dw 0xe440, 0xc82c, 0xe47f, 0xc82c, 0x21, 0 - .dw 0xe4c0, 0xc82c, 0xe4ff, 0xc82c, 0x21, 0 - .dw 0xe540, 0xc82c, 0xe57f, 0xc82c, 0x21, 0 - .dw 0xe5c0, 0xc82c, 0xe5ff, 0xc82c, 0x21, 0 - .dw 0xe640, 0xc82c, 0xe67f, 0xc82c, 0x21, 0 - .dw 0xe6c0, 0xc82c, 0xe6ff, 0xc82c, 0x21, 0 - .dw 0xe740, 0xc82c, 0xe77f, 0xc82c, 0x21, 0 - .dw 0xe7c0, 0xc82c, 0xe7ff, 0xc82c, 0x21, 0 - .dw 0xe840, 0xc82c, 0xe87f, 0xc82c, 0x21, 0 - .dw 0xe8c0, 0xc82c, 0xe8ff, 0xc82c, 0x21, 0 - .dw 0xe940, 0xc82c, 0xe97f, 0xc82c, 0x21, 0 - .dw 0xe9c0, 0xc82c, 0xe9ff, 0xc82c, 0x21, 0 - .dw 0xea40, 0xc82c, 0xea7f, 0xc82c, 0x21, 0 - .dw 0xeac0, 0xc82c, 0xeaff, 0xc82c, 0x21, 0 - .dw 0xeb40, 0xc82c, 0xeb7f, 0xc82c, 0x21, 0 - .dw 0xebc0, 0xc82c, 0xebff, 0xc82c, 0x21, 0 - .dw 0xec40, 0xc82c, 0xec7f, 0xc82c, 0x21, 0 - .dw 0xecc0, 0xc82c, 0xecff, 0xc82c, 0x21, 0 - .dw 0xed40, 0xc82c, 0xed7f, 0xc82c, 0x21, 0 - .dw 0xedc0, 0xc82c, 0xedff, 0xc82c, 0x21, 0 - .dw 0xee40, 0xc82c, 0xee7f, 0xc82c, 0x21, 0 - .dw 0xeec0, 0xc82c, 0xeeff, 0xc82c, 0x21, 0 - .dw 0xef40, 0xc82c, 0xef7f, 0xc82c, 0x21, 0 - .dw 0xefc0, 0xc82c, 0xefff, 0xc82c, 0x21, 0 - .dw 0xf040, 0xc82c, 0xf07f, 0xc82c, 0x21, 0 - .dw 0xf0c0, 0xc82c, 0xf0ff, 0xc82c, 0x21, 0 - .dw 0xf140, 0xc82c, 0xf17f, 0xc82c, 0x21, 0 - .dw 0xf1c0, 0xc82c, 0xf1ff, 0xc82c, 0x21, 0 - .dw 0xf240, 0xc82c, 0xf27f, 0xc82c, 0x21, 0 - .dw 0xf2c0, 0xc82c, 0xf2ff, 0xc82c, 0x21, 0 - .dw 0xf340, 0xc82c, 0xf37f, 0xc82c, 0x21, 0 - .dw 0xf3c0, 0xc82c, 0xf3ff, 0xc82c, 0x21, 0 - .dw 0xf440, 0xc82c, 0xf47f, 0xc82c, 0x21, 0 - .dw 0xf4c0, 0xc82c, 0xf4ff, 0xc82c, 0x21, 0 - .dw 0xf540, 0xc82c, 0xf57f, 0xc82c, 0x21, 0 - .dw 0xf5c0, 0xc82c, 0xf5ff, 0xc82c, 0x21, 0 - .dw 0xf640, 0xc82c, 0xf67f, 0xc82c, 0x21, 0 - .dw 0xf6c0, 0xc82c, 0xf6ff, 0xc82c, 0x21, 0 - .dw 0xf740, 0xc82c, 0xf77f, 0xc82c, 0x21, 0 - .dw 0xf7c0, 0xc82c, 0xf7ff, 0xc82c, 0x21, 0 - .dw 0xf840, 0xc82c, 0xf87f, 0xc82c, 0x21, 0 - .dw 0xf8c0, 0xc82c, 0xf8ff, 0xc82c, 0x21, 0 - .dw 0xf940, 0xc82c, 0xf97f, 0xc82c, 0x21, 0 - .dw 0xf9c0, 0xc82c, 0xffff, 0xc82c, 0x21, 0 - .dw 0x0040, 0xc82d, 0x007f, 0xc82d, 0x21, 0 - .dw 0x00c0, 0xc82d, 0x00ff, 0xc82d, 0x21, 0 - .dw 0x0140, 0xc82d, 0x017f, 0xc82d, 0x21, 0 - .dw 0x01c0, 0xc82d, 0x01ff, 0xc82d, 0x21, 0 - .dw 0x0240, 0xc82d, 0x027f, 0xc82d, 0x21, 0 - .dw 0x02c0, 0xc82d, 0x02ff, 0xc82d, 0x21, 0 - .dw 0x0340, 0xc82d, 0x037f, 0xc82d, 0x21, 0 - .dw 0x03c0, 0xc82d, 0x03ff, 0xc82d, 0x21, 0 - .dw 0x0440, 0xc82d, 0x047f, 0xc82d, 0x21, 0 - .dw 0x04c0, 0xc82d, 0x04ff, 0xc82d, 0x21, 0 - .dw 0x0540, 0xc82d, 0x057f, 0xc82d, 0x21, 0 - .dw 0x05c0, 0xc82d, 0x05ff, 0xc82d, 0x21, 0 - .dw 0x0640, 0xc82d, 0x067f, 0xc82d, 0x21, 0 - .dw 0x06c0, 0xc82d, 0x06ff, 0xc82d, 0x21, 0 - .dw 0x0740, 0xc82d, 0x077f, 0xc82d, 0x21, 0 - .dw 0x07c0, 0xc82d, 0x07ff, 0xc82d, 0x21, 0 - .dw 0x0840, 0xc82d, 0x087f, 0xc82d, 0x21, 0 - .dw 0x08c0, 0xc82d, 0x08ff, 0xc82d, 0x21, 0 - .dw 0x0940, 0xc82d, 0x097f, 0xc82d, 0x21, 0 - .dw 0x09c0, 0xc82d, 0x09ff, 0xc82d, 0x21, 0 - .dw 0x0a40, 0xc82d, 0x0a7f, 0xc82d, 0x21, 0 - .dw 0x0ac0, 0xc82d, 0x0aff, 0xc82d, 0x21, 0 - .dw 0x0b40, 0xc82d, 0x0b7f, 0xc82d, 0x21, 0 - .dw 0x0bc0, 0xc82d, 0x0bff, 0xc82d, 0x21, 0 - .dw 0x0c40, 0xc82d, 0x0c7f, 0xc82d, 0x21, 0 - .dw 0x0cc0, 0xc82d, 0x0cff, 0xc82d, 0x21, 0 - .dw 0x0d40, 0xc82d, 0x0d7f, 0xc82d, 0x21, 0 - .dw 0x0dc0, 0xc82d, 0x0dff, 0xc82d, 0x21, 0 - .dw 0x0e40, 0xc82d, 0x0e7f, 0xc82d, 0x21, 0 - .dw 0x0ec0, 0xc82d, 0x0eff, 0xc82d, 0x21, 0 - .dw 0x0f40, 0xc82d, 0x0f7f, 0xc82d, 0x21, 0 - .dw 0x0fc0, 0xc82d, 0x0fff, 0xc82d, 0x21, 0 - .dw 0x1040, 0xc82d, 0x107f, 0xc82d, 0x21, 0 - .dw 0x10c0, 0xc82d, 0x10ff, 0xc82d, 0x21, 0 - .dw 0x1140, 0xc82d, 0x117f, 0xc82d, 0x21, 0 - .dw 0x11c0, 0xc82d, 0x11ff, 0xc82d, 0x21, 0 - .dw 0x1240, 0xc82d, 0x127f, 0xc82d, 0x21, 0 - .dw 0x12c0, 0xc82d, 0x12ff, 0xc82d, 0x21, 0 - .dw 0x1340, 0xc82d, 0x137f, 0xc82d, 0x21, 0 - .dw 0x13c0, 0xc82d, 0x13ff, 0xc82d, 0x21, 0 - .dw 0x1440, 0xc82d, 0x147f, 0xc82d, 0x21, 0 - .dw 0x14c0, 0xc82d, 0x14ff, 0xc82d, 0x21, 0 - .dw 0x1540, 0xc82d, 0x157f, 0xc82d, 0x21, 0 - .dw 0x15c0, 0xc82d, 0x15ff, 0xc82d, 0x21, 0 - .dw 0x1640, 0xc82d, 0x167f, 0xc82d, 0x21, 0 - .dw 0x16c0, 0xc82d, 0x16ff, 0xc82d, 0x21, 0 - .dw 0x1740, 0xc82d, 0x177f, 0xc82d, 0x21, 0 - .dw 0x17c0, 0xc82d, 0x17ff, 0xc82d, 0x21, 0 - .dw 0x1840, 0xc82d, 0x187f, 0xc82d, 0x21, 0 - .dw 0x18c0, 0xc82d, 0x18ff, 0xc82d, 0x21, 0 - .dw 0x1940, 0xc82d, 0x197f, 0xc82d, 0x21, 0 - .dw 0x19c0, 0xc82d, 0x1fff, 0xc82d, 0x21, 0 - .dw 0x2040, 0xc82d, 0x207f, 0xc82d, 0x21, 0 - .dw 0x20c0, 0xc82d, 0x20ff, 0xc82d, 0x21, 0 - .dw 0x2140, 0xc82d, 0x217f, 0xc82d, 0x21, 0 - .dw 0x21c0, 0xc82d, 0x21ff, 0xc82d, 0x21, 0 - .dw 0x2240, 0xc82d, 0x227f, 0xc82d, 0x21, 0 - .dw 0x22c0, 0xc82d, 0x22ff, 0xc82d, 0x21, 0 - .dw 0x2340, 0xc82d, 0x237f, 0xc82d, 0x21, 0 - .dw 0x23c0, 0xc82d, 0x23ff, 0xc82d, 0x21, 0 - .dw 0x2440, 0xc82d, 0x247f, 0xc82d, 0x21, 0 - .dw 0x24c0, 0xc82d, 0x24ff, 0xc82d, 0x21, 0 - .dw 0x2540, 0xc82d, 0x257f, 0xc82d, 0x21, 0 - .dw 0x25c0, 0xc82d, 0x25ff, 0xc82d, 0x21, 0 - .dw 0x2640, 0xc82d, 0x267f, 0xc82d, 0x21, 0 - .dw 0x26c0, 0xc82d, 0x26ff, 0xc82d, 0x21, 0 - .dw 0x2740, 0xc82d, 0x277f, 0xc82d, 0x21, 0 - .dw 0x27c0, 0xc82d, 0x27ff, 0xc82d, 0x21, 0 - .dw 0x2840, 0xc82d, 0x287f, 0xc82d, 0x21, 0 - .dw 0x28c0, 0xc82d, 0x28ff, 0xc82d, 0x21, 0 - .dw 0x2940, 0xc82d, 0x297f, 0xc82d, 0x21, 0 - .dw 0x29c0, 0xc82d, 0x29ff, 0xc82d, 0x21, 0 - .dw 0x2a40, 0xc82d, 0x2a7f, 0xc82d, 0x21, 0 - .dw 0x2ac0, 0xc82d, 0x2aff, 0xc82d, 0x21, 0 - .dw 0x2b40, 0xc82d, 0x2b7f, 0xc82d, 0x21, 0 - .dw 0x2bc0, 0xc82d, 0x2bff, 0xc82d, 0x21, 0 - .dw 0x2c40, 0xc82d, 0x2c7f, 0xc82d, 0x21, 0 - .dw 0x2cc0, 0xc82d, 0x2cff, 0xc82d, 0x21, 0 - .dw 0x2d40, 0xc82d, 0x2d7f, 0xc82d, 0x21, 0 - .dw 0x2dc0, 0xc82d, 0x2dff, 0xc82d, 0x21, 0 - .dw 0x2e40, 0xc82d, 0x2e7f, 0xc82d, 0x21, 0 - .dw 0x2ec0, 0xc82d, 0x2eff, 0xc82d, 0x21, 0 - .dw 0x2f40, 0xc82d, 0x2f7f, 0xc82d, 0x21, 0 - .dw 0x2fc0, 0xc82d, 0x2fff, 0xc82d, 0x21, 0 - .dw 0x3040, 0xc82d, 0x307f, 0xc82d, 0x21, 0 - .dw 0x30c0, 0xc82d, 0x30ff, 0xc82d, 0x21, 0 - .dw 0x3140, 0xc82d, 0x317f, 0xc82d, 0x21, 0 - .dw 0x31c0, 0xc82d, 0x31ff, 0xc82d, 0x21, 0 - .dw 0x3240, 0xc82d, 0x327f, 0xc82d, 0x21, 0 - .dw 0x32c0, 0xc82d, 0x32ff, 0xc82d, 0x21, 0 - .dw 0x3340, 0xc82d, 0x337f, 0xc82d, 0x21, 0 - .dw 0x33c0, 0xc82d, 0x33ff, 0xc82d, 0x21, 0 - .dw 0x3440, 0xc82d, 0x347f, 0xc82d, 0x21, 0 - .dw 0x34c0, 0xc82d, 0x34ff, 0xc82d, 0x21, 0 - .dw 0x3540, 0xc82d, 0x357f, 0xc82d, 0x21, 0 - .dw 0x35c0, 0xc82d, 0x35ff, 0xc82d, 0x21, 0 - .dw 0x3640, 0xc82d, 0x367f, 0xc82d, 0x21, 0 - .dw 0x36c0, 0xc82d, 0x36ff, 0xc82d, 0x21, 0 - .dw 0x3740, 0xc82d, 0x377f, 0xc82d, 0x21, 0 - .dw 0x37c0, 0xc82d, 0x37ff, 0xc82d, 0x21, 0 - .dw 0x3840, 0xc82d, 0x387f, 0xc82d, 0x21, 0 - .dw 0x38c0, 0xc82d, 0x38ff, 0xc82d, 0x21, 0 - .dw 0x3940, 0xc82d, 0x397f, 0xc82d, 0x21, 0 - .dw 0x39c0, 0xc82d, 0x3fff, 0xc82d, 0x21, 0 - .dw 0x4040, 0xc82d, 0x407f, 0xc82d, 0x21, 0 - .dw 0x40c0, 0xc82d, 0x40ff, 0xc82d, 0x21, 0 - .dw 0x4140, 0xc82d, 0x417f, 0xc82d, 0x21, 0 - .dw 0x41c0, 0xc82d, 0x41ff, 0xc82d, 0x21, 0 - .dw 0x4240, 0xc82d, 0x427f, 0xc82d, 0x21, 0 - .dw 0x42c0, 0xc82d, 0x42ff, 0xc82d, 0x21, 0 - .dw 0x4340, 0xc82d, 0x437f, 0xc82d, 0x21, 0 - .dw 0x43c0, 0xc82d, 0x43ff, 0xc82d, 0x21, 0 - .dw 0x4440, 0xc82d, 0x447f, 0xc82d, 0x21, 0 - .dw 0x44c0, 0xc82d, 0x44ff, 0xc82d, 0x21, 0 - .dw 0x4540, 0xc82d, 0x457f, 0xc82d, 0x21, 0 - .dw 0x45c0, 0xc82d, 0x45ff, 0xc82d, 0x21, 0 - .dw 0x4640, 0xc82d, 0x467f, 0xc82d, 0x21, 0 - .dw 0x46c0, 0xc82d, 0x46ff, 0xc82d, 0x21, 0 - .dw 0x4740, 0xc82d, 0x477f, 0xc82d, 0x21, 0 - .dw 0x47c0, 0xc82d, 0x47ff, 0xc82d, 0x21, 0 - .dw 0x4840, 0xc82d, 0x487f, 0xc82d, 0x21, 0 - .dw 0x48c0, 0xc82d, 0x48ff, 0xc82d, 0x21, 0 - .dw 0x4940, 0xc82d, 0x497f, 0xc82d, 0x21, 0 - .dw 0x49c0, 0xc82d, 0x49ff, 0xc82d, 0x21, 0 - .dw 0x4a40, 0xc82d, 0x4a7f, 0xc82d, 0x21, 0 - .dw 0x4ac0, 0xc82d, 0x4aff, 0xc82d, 0x21, 0 - .dw 0x4b40, 0xc82d, 0x4b7f, 0xc82d, 0x21, 0 - .dw 0x4bc0, 0xc82d, 0x4bff, 0xc82d, 0x21, 0 - .dw 0x4c40, 0xc82d, 0x4c7f, 0xc82d, 0x21, 0 - .dw 0x4cc0, 0xc82d, 0x4cff, 0xc82d, 0x21, 0 - .dw 0x4d40, 0xc82d, 0x4d7f, 0xc82d, 0x21, 0 - .dw 0x4dc0, 0xc82d, 0x4dff, 0xc82d, 0x21, 0 - .dw 0x4e40, 0xc82d, 0x4e7f, 0xc82d, 0x21, 0 - .dw 0x4ec0, 0xc82d, 0x4eff, 0xc82d, 0x21, 0 - .dw 0x4f40, 0xc82d, 0x4f7f, 0xc82d, 0x21, 0 - .dw 0x4fc0, 0xc82d, 0x4fff, 0xc82d, 0x21, 0 - .dw 0x5040, 0xc82d, 0x507f, 0xc82d, 0x21, 0 - .dw 0x50c0, 0xc82d, 0x50ff, 0xc82d, 0x21, 0 - .dw 0x5140, 0xc82d, 0x517f, 0xc82d, 0x21, 0 - .dw 0x51c0, 0xc82d, 0x51ff, 0xc82d, 0x21, 0 - .dw 0x5240, 0xc82d, 0x527f, 0xc82d, 0x21, 0 - .dw 0x52c0, 0xc82d, 0x52ff, 0xc82d, 0x21, 0 - .dw 0x5340, 0xc82d, 0x537f, 0xc82d, 0x21, 0 - .dw 0x53c0, 0xc82d, 0x53ff, 0xc82d, 0x21, 0 - .dw 0x5440, 0xc82d, 0x547f, 0xc82d, 0x21, 0 - .dw 0x54c0, 0xc82d, 0x54ff, 0xc82d, 0x21, 0 - .dw 0x5540, 0xc82d, 0x557f, 0xc82d, 0x21, 0 - .dw 0x55c0, 0xc82d, 0x55ff, 0xc82d, 0x21, 0 - .dw 0x5640, 0xc82d, 0x567f, 0xc82d, 0x21, 0 - .dw 0x56c0, 0xc82d, 0x56ff, 0xc82d, 0x21, 0 - .dw 0x5740, 0xc82d, 0x577f, 0xc82d, 0x21, 0 - .dw 0x57c0, 0xc82d, 0x57ff, 0xc82d, 0x21, 0 - .dw 0x5840, 0xc82d, 0x587f, 0xc82d, 0x21, 0 - .dw 0x58c0, 0xc82d, 0x58ff, 0xc82d, 0x21, 0 - .dw 0x5940, 0xc82d, 0x597f, 0xc82d, 0x21, 0 - .dw 0x59c0, 0xc82d, 0x5fff, 0xc82d, 0x21, 0 - .dw 0x6040, 0xc82d, 0x607f, 0xc82d, 0x21, 0 - .dw 0x60c0, 0xc82d, 0x60ff, 0xc82d, 0x21, 0 - .dw 0x6140, 0xc82d, 0x617f, 0xc82d, 0x21, 0 - .dw 0x61c0, 0xc82d, 0x61ff, 0xc82d, 0x21, 0 - .dw 0x6240, 0xc82d, 0x627f, 0xc82d, 0x21, 0 - .dw 0x62c0, 0xc82d, 0x62ff, 0xc82d, 0x21, 0 - .dw 0x6340, 0xc82d, 0x637f, 0xc82d, 0x21, 0 - .dw 0x63c0, 0xc82d, 0x63ff, 0xc82d, 0x21, 0 - .dw 0x6440, 0xc82d, 0x647f, 0xc82d, 0x21, 0 - .dw 0x64c0, 0xc82d, 0x64ff, 0xc82d, 0x21, 0 - .dw 0x6540, 0xc82d, 0x657f, 0xc82d, 0x21, 0 - .dw 0x65c0, 0xc82d, 0x65ff, 0xc82d, 0x21, 0 - .dw 0x6640, 0xc82d, 0x667f, 0xc82d, 0x21, 0 - .dw 0x66c0, 0xc82d, 0x66ff, 0xc82d, 0x21, 0 - .dw 0x6740, 0xc82d, 0x677f, 0xc82d, 0x21, 0 - .dw 0x67c0, 0xc82d, 0x67ff, 0xc82d, 0x21, 0 - .dw 0x6840, 0xc82d, 0x687f, 0xc82d, 0x21, 0 - .dw 0x68c0, 0xc82d, 0x68ff, 0xc82d, 0x21, 0 - .dw 0x6940, 0xc82d, 0x697f, 0xc82d, 0x21, 0 - .dw 0x69c0, 0xc82d, 0x69ff, 0xc82d, 0x21, 0 - .dw 0x6a40, 0xc82d, 0x6a7f, 0xc82d, 0x21, 0 - .dw 0x6ac0, 0xc82d, 0x6aff, 0xc82d, 0x21, 0 - .dw 0x6b40, 0xc82d, 0x6b7f, 0xc82d, 0x21, 0 - .dw 0x6bc0, 0xc82d, 0x6bff, 0xc82d, 0x21, 0 - .dw 0x6c40, 0xc82d, 0x6c7f, 0xc82d, 0x21, 0 - .dw 0x6cc0, 0xc82d, 0x6cff, 0xc82d, 0x21, 0 - .dw 0x6d40, 0xc82d, 0x6d7f, 0xc82d, 0x21, 0 - .dw 0x6dc0, 0xc82d, 0x6dff, 0xc82d, 0x21, 0 - .dw 0x6e40, 0xc82d, 0x6e7f, 0xc82d, 0x21, 0 - .dw 0x6ec0, 0xc82d, 0x6eff, 0xc82d, 0x21, 0 - .dw 0x6f40, 0xc82d, 0x6f7f, 0xc82d, 0x21, 0 - .dw 0x6fc0, 0xc82d, 0x6fff, 0xc82d, 0x21, 0 - .dw 0x7040, 0xc82d, 0x707f, 0xc82d, 0x21, 0 - .dw 0x70c0, 0xc82d, 0x70ff, 0xc82d, 0x21, 0 - .dw 0x7140, 0xc82d, 0x717f, 0xc82d, 0x21, 0 - .dw 0x71c0, 0xc82d, 0x71ff, 0xc82d, 0x21, 0 - .dw 0x7240, 0xc82d, 0x727f, 0xc82d, 0x21, 0 - .dw 0x72c0, 0xc82d, 0x72ff, 0xc82d, 0x21, 0 - .dw 0x7340, 0xc82d, 0x737f, 0xc82d, 0x21, 0 - .dw 0x73c0, 0xc82d, 0x73ff, 0xc82d, 0x21, 0 - .dw 0x7440, 0xc82d, 0x747f, 0xc82d, 0x21, 0 - .dw 0x74c0, 0xc82d, 0x74ff, 0xc82d, 0x21, 0 - .dw 0x7540, 0xc82d, 0x757f, 0xc82d, 0x21, 0 - .dw 0x75c0, 0xc82d, 0x75ff, 0xc82d, 0x21, 0 - .dw 0x7640, 0xc82d, 0x767f, 0xc82d, 0x21, 0 - .dw 0x76c0, 0xc82d, 0x76ff, 0xc82d, 0x21, 0 - .dw 0x7740, 0xc82d, 0x777f, 0xc82d, 0x21, 0 - .dw 0x77c0, 0xc82d, 0x77ff, 0xc82d, 0x21, 0 - .dw 0x7840, 0xc82d, 0x787f, 0xc82d, 0x21, 0 - .dw 0x78c0, 0xc82d, 0x78ff, 0xc82d, 0x21, 0 - .dw 0x7940, 0xc82d, 0x797f, 0xc82d, 0x21, 0 - .dw 0x79c0, 0xc82d, 0x7fff, 0xc82d, 0x21, 0 - .dw 0x8040, 0xc82d, 0x807f, 0xc82d, 0x21, 0 - .dw 0x80c0, 0xc82d, 0x80ff, 0xc82d, 0x21, 0 - .dw 0x8140, 0xc82d, 0x817f, 0xc82d, 0x21, 0 - .dw 0x81c0, 0xc82d, 0x81ff, 0xc82d, 0x21, 0 - .dw 0x8240, 0xc82d, 0x827f, 0xc82d, 0x21, 0 - .dw 0x82c0, 0xc82d, 0x82ff, 0xc82d, 0x21, 0 - .dw 0x8340, 0xc82d, 0x837f, 0xc82d, 0x21, 0 - .dw 0x83c0, 0xc82d, 0x83ff, 0xc82d, 0x21, 0 - .dw 0x8440, 0xc82d, 0x847f, 0xc82d, 0x21, 0 - .dw 0x84c0, 0xc82d, 0x84ff, 0xc82d, 0x21, 0 - .dw 0x8540, 0xc82d, 0x857f, 0xc82d, 0x21, 0 - .dw 0x85c0, 0xc82d, 0x85ff, 0xc82d, 0x21, 0 - .dw 0x8640, 0xc82d, 0x867f, 0xc82d, 0x21, 0 - .dw 0x86c0, 0xc82d, 0x86ff, 0xc82d, 0x21, 0 - .dw 0x8740, 0xc82d, 0x877f, 0xc82d, 0x21, 0 - .dw 0x87c0, 0xc82d, 0x87ff, 0xc82d, 0x21, 0 - .dw 0x8840, 0xc82d, 0x887f, 0xc82d, 0x21, 0 - .dw 0x88c0, 0xc82d, 0x88ff, 0xc82d, 0x21, 0 - .dw 0x8940, 0xc82d, 0x897f, 0xc82d, 0x21, 0 - .dw 0x89c0, 0xc82d, 0x89ff, 0xc82d, 0x21, 0 - .dw 0x8a40, 0xc82d, 0x8a7f, 0xc82d, 0x21, 0 - .dw 0x8ac0, 0xc82d, 0x8aff, 0xc82d, 0x21, 0 - .dw 0x8b40, 0xc82d, 0x8b7f, 0xc82d, 0x21, 0 - .dw 0x8bc0, 0xc82d, 0x8bff, 0xc82d, 0x21, 0 - .dw 0x8c40, 0xc82d, 0x8c7f, 0xc82d, 0x21, 0 - .dw 0x8cc0, 0xc82d, 0x8cff, 0xc82d, 0x21, 0 - .dw 0x8d40, 0xc82d, 0x8d7f, 0xc82d, 0x21, 0 - .dw 0x8dc0, 0xc82d, 0x8dff, 0xc82d, 0x21, 0 - .dw 0x8e40, 0xc82d, 0x8e7f, 0xc82d, 0x21, 0 - .dw 0x8ec0, 0xc82d, 0x8eff, 0xc82d, 0x21, 0 - .dw 0x8f40, 0xc82d, 0x8f7f, 0xc82d, 0x21, 0 - .dw 0x8fc0, 0xc82d, 0x8fff, 0xc82d, 0x21, 0 - .dw 0x9040, 0xc82d, 0x907f, 0xc82d, 0x21, 0 - .dw 0x90c0, 0xc82d, 0x90ff, 0xc82d, 0x21, 0 - .dw 0x9140, 0xc82d, 0x917f, 0xc82d, 0x21, 0 - .dw 0x91c0, 0xc82d, 0x91ff, 0xc82d, 0x21, 0 - .dw 0x9240, 0xc82d, 0x927f, 0xc82d, 0x21, 0 - .dw 0x92c0, 0xc82d, 0x92ff, 0xc82d, 0x21, 0 - .dw 0x9340, 0xc82d, 0x937f, 0xc82d, 0x21, 0 - .dw 0x93c0, 0xc82d, 0x93ff, 0xc82d, 0x21, 0 - .dw 0x9440, 0xc82d, 0x947f, 0xc82d, 0x21, 0 - .dw 0x94c0, 0xc82d, 0x94ff, 0xc82d, 0x21, 0 - .dw 0x9540, 0xc82d, 0x957f, 0xc82d, 0x21, 0 - .dw 0x95c0, 0xc82d, 0x95ff, 0xc82d, 0x21, 0 - .dw 0x9640, 0xc82d, 0x967f, 0xc82d, 0x21, 0 - .dw 0x96c0, 0xc82d, 0x96ff, 0xc82d, 0x21, 0 - .dw 0x9740, 0xc82d, 0x977f, 0xc82d, 0x21, 0 - .dw 0x97c0, 0xc82d, 0x97ff, 0xc82d, 0x21, 0 - .dw 0x9840, 0xc82d, 0x987f, 0xc82d, 0x21, 0 - .dw 0x98c0, 0xc82d, 0x98ff, 0xc82d, 0x21, 0 - .dw 0x9940, 0xc82d, 0x997f, 0xc82d, 0x21, 0 - .dw 0x99c0, 0xc82d, 0x9fff, 0xc82d, 0x21, 0 - .dw 0xa040, 0xc82d, 0xa07f, 0xc82d, 0x21, 0 - .dw 0xa0c0, 0xc82d, 0xa0ff, 0xc82d, 0x21, 0 - .dw 0xa140, 0xc82d, 0xa17f, 0xc82d, 0x21, 0 - .dw 0xa1c0, 0xc82d, 0xa1ff, 0xc82d, 0x21, 0 - .dw 0xa240, 0xc82d, 0xa27f, 0xc82d, 0x21, 0 - .dw 0xa2c0, 0xc82d, 0xa2ff, 0xc82d, 0x21, 0 - .dw 0xa340, 0xc82d, 0xa37f, 0xc82d, 0x21, 0 - .dw 0xa3c0, 0xc82d, 0xa3ff, 0xc82d, 0x21, 0 - .dw 0xa440, 0xc82d, 0xa47f, 0xc82d, 0x21, 0 - .dw 0xa4c0, 0xc82d, 0xa4ff, 0xc82d, 0x21, 0 - .dw 0xa540, 0xc82d, 0xa57f, 0xc82d, 0x21, 0 - .dw 0xa5c0, 0xc82d, 0xa5ff, 0xc82d, 0x21, 0 - .dw 0xa640, 0xc82d, 0xa67f, 0xc82d, 0x21, 0 - .dw 0xa6c0, 0xc82d, 0xa6ff, 0xc82d, 0x21, 0 - .dw 0xa740, 0xc82d, 0xa77f, 0xc82d, 0x21, 0 - .dw 0xa7c0, 0xc82d, 0xa7ff, 0xc82d, 0x21, 0 - .dw 0xa840, 0xc82d, 0xa87f, 0xc82d, 0x21, 0 - .dw 0xa8c0, 0xc82d, 0xa8ff, 0xc82d, 0x21, 0 - .dw 0xa940, 0xc82d, 0xa97f, 0xc82d, 0x21, 0 - .dw 0xa9c0, 0xc82d, 0xa9ff, 0xc82d, 0x21, 0 - .dw 0xaa40, 0xc82d, 0xaa7f, 0xc82d, 0x21, 0 - .dw 0xaac0, 0xc82d, 0xaaff, 0xc82d, 0x21, 0 - .dw 0xab40, 0xc82d, 0xab7f, 0xc82d, 0x21, 0 - .dw 0xabc0, 0xc82d, 0xabff, 0xc82d, 0x21, 0 - .dw 0xac40, 0xc82d, 0xac7f, 0xc82d, 0x21, 0 - .dw 0xacc0, 0xc82d, 0xacff, 0xc82d, 0x21, 0 - .dw 0xad40, 0xc82d, 0xad7f, 0xc82d, 0x21, 0 - .dw 0xadc0, 0xc82d, 0xadff, 0xc82d, 0x21, 0 - .dw 0xae40, 0xc82d, 0xae7f, 0xc82d, 0x21, 0 - .dw 0xaec0, 0xc82d, 0xaeff, 0xc82d, 0x21, 0 - .dw 0xaf40, 0xc82d, 0xaf7f, 0xc82d, 0x21, 0 - .dw 0xafc0, 0xc82d, 0xafff, 0xc82d, 0x21, 0 - .dw 0xb040, 0xc82d, 0xb07f, 0xc82d, 0x21, 0 - .dw 0xb0c0, 0xc82d, 0xb0ff, 0xc82d, 0x21, 0 - .dw 0xb140, 0xc82d, 0xb17f, 0xc82d, 0x21, 0 - .dw 0xb1c0, 0xc82d, 0xb1ff, 0xc82d, 0x21, 0 - .dw 0xb240, 0xc82d, 0xb27f, 0xc82d, 0x21, 0 - .dw 0xb2c0, 0xc82d, 0xb2ff, 0xc82d, 0x21, 0 - .dw 0xb340, 0xc82d, 0xb37f, 0xc82d, 0x21, 0 - .dw 0xb3c0, 0xc82d, 0xb3ff, 0xc82d, 0x21, 0 - .dw 0xb440, 0xc82d, 0xb47f, 0xc82d, 0x21, 0 - .dw 0xb4c0, 0xc82d, 0xb4ff, 0xc82d, 0x21, 0 - .dw 0xb540, 0xc82d, 0xb57f, 0xc82d, 0x21, 0 - .dw 0xb5c0, 0xc82d, 0xb5ff, 0xc82d, 0x21, 0 - .dw 0xb640, 0xc82d, 0xb67f, 0xc82d, 0x21, 0 - .dw 0xb6c0, 0xc82d, 0xb6ff, 0xc82d, 0x21, 0 - .dw 0xb740, 0xc82d, 0xb77f, 0xc82d, 0x21, 0 - .dw 0xb7c0, 0xc82d, 0xb7ff, 0xc82d, 0x21, 0 - .dw 0xb840, 0xc82d, 0xb87f, 0xc82d, 0x21, 0 - .dw 0xb8c0, 0xc82d, 0xb8ff, 0xc82d, 0x21, 0 - .dw 0xb940, 0xc82d, 0xb97f, 0xc82d, 0x21, 0 - .dw 0xb9c0, 0xc82d, 0xbfff, 0xc82d, 0x21, 0 - .dw 0xc040, 0xc82d, 0xc07f, 0xc82d, 0x21, 0 - .dw 0xc0c0, 0xc82d, 0xc0ff, 0xc82d, 0x21, 0 - .dw 0xc140, 0xc82d, 0xc17f, 0xc82d, 0x21, 0 - .dw 0xc1c0, 0xc82d, 0xc1ff, 0xc82d, 0x21, 0 - .dw 0xc240, 0xc82d, 0xc27f, 0xc82d, 0x21, 0 - .dw 0xc2c0, 0xc82d, 0xc2ff, 0xc82d, 0x21, 0 - .dw 0xc340, 0xc82d, 0xc37f, 0xc82d, 0x21, 0 - .dw 0xc3c0, 0xc82d, 0xc3ff, 0xc82d, 0x21, 0 - .dw 0xc440, 0xc82d, 0xc47f, 0xc82d, 0x21, 0 - .dw 0xc4c0, 0xc82d, 0xc4ff, 0xc82d, 0x21, 0 - .dw 0xc540, 0xc82d, 0xc57f, 0xc82d, 0x21, 0 - .dw 0xc5c0, 0xc82d, 0xc5ff, 0xc82d, 0x21, 0 - .dw 0xc640, 0xc82d, 0xc67f, 0xc82d, 0x21, 0 - .dw 0xc6c0, 0xc82d, 0xc6ff, 0xc82d, 0x21, 0 - .dw 0xc740, 0xc82d, 0xc77f, 0xc82d, 0x21, 0 - .dw 0xc7c0, 0xc82d, 0xc7ff, 0xc82d, 0x21, 0 - .dw 0xc840, 0xc82d, 0xc87f, 0xc82d, 0x21, 0 - .dw 0xc8c0, 0xc82d, 0xc8ff, 0xc82d, 0x21, 0 - .dw 0xc940, 0xc82d, 0xc97f, 0xc82d, 0x21, 0 - .dw 0xc9c0, 0xc82d, 0xc9ff, 0xc82d, 0x21, 0 - .dw 0xca40, 0xc82d, 0xca7f, 0xc82d, 0x21, 0 - .dw 0xcac0, 0xc82d, 0xcaff, 0xc82d, 0x21, 0 - .dw 0xcb40, 0xc82d, 0xcb7f, 0xc82d, 0x21, 0 - .dw 0xcbc0, 0xc82d, 0xcbff, 0xc82d, 0x21, 0 - .dw 0xcc40, 0xc82d, 0xcc7f, 0xc82d, 0x21, 0 - .dw 0xccc0, 0xc82d, 0xccff, 0xc82d, 0x21, 0 - .dw 0xcd40, 0xc82d, 0xcd7f, 0xc82d, 0x21, 0 - .dw 0xcdc0, 0xc82d, 0xcdff, 0xc82d, 0x21, 0 - .dw 0xce40, 0xc82d, 0xce7f, 0xc82d, 0x21, 0 - .dw 0xcec0, 0xc82d, 0xceff, 0xc82d, 0x21, 0 - .dw 0xcf40, 0xc82d, 0xcf7f, 0xc82d, 0x21, 0 - .dw 0xcfc0, 0xc82d, 0xcfff, 0xc82d, 0x21, 0 - .dw 0xd040, 0xc82d, 0xd07f, 0xc82d, 0x21, 0 - .dw 0xd0c0, 0xc82d, 0xd0ff, 0xc82d, 0x21, 0 - .dw 0xd140, 0xc82d, 0xd17f, 0xc82d, 0x21, 0 - .dw 0xd1c0, 0xc82d, 0xd1ff, 0xc82d, 0x21, 0 - .dw 0xd240, 0xc82d, 0xd27f, 0xc82d, 0x21, 0 - .dw 0xd2c0, 0xc82d, 0xd2ff, 0xc82d, 0x21, 0 - .dw 0xd340, 0xc82d, 0xd37f, 0xc82d, 0x21, 0 - .dw 0xd3c0, 0xc82d, 0xd3ff, 0xc82d, 0x21, 0 - .dw 0xd440, 0xc82d, 0xd47f, 0xc82d, 0x21, 0 - .dw 0xd4c0, 0xc82d, 0xd4ff, 0xc82d, 0x21, 0 - .dw 0xd540, 0xc82d, 0xd57f, 0xc82d, 0x21, 0 - .dw 0xd5c0, 0xc82d, 0xd5ff, 0xc82d, 0x21, 0 - .dw 0xd640, 0xc82d, 0xd67f, 0xc82d, 0x21, 0 - .dw 0xd6c0, 0xc82d, 0xd6ff, 0xc82d, 0x21, 0 - .dw 0xd740, 0xc82d, 0xd77f, 0xc82d, 0x21, 0 - .dw 0xd7c0, 0xc82d, 0xd7ff, 0xc82d, 0x21, 0 - .dw 0xd840, 0xc82d, 0xd87f, 0xc82d, 0x21, 0 - .dw 0xd8c0, 0xc82d, 0xd8ff, 0xc82d, 0x21, 0 - .dw 0xd940, 0xc82d, 0xd97f, 0xc82d, 0x21, 0 - .dw 0xd9c0, 0xc82d, 0xdfff, 0xc82d, 0x21, 0 - .dw 0xe040, 0xc82d, 0xe07f, 0xc82d, 0x21, 0 - .dw 0xe0c0, 0xc82d, 0xe0ff, 0xc82d, 0x21, 0 - .dw 0xe140, 0xc82d, 0xe17f, 0xc82d, 0x21, 0 - .dw 0xe1c0, 0xc82d, 0xe1ff, 0xc82d, 0x21, 0 - .dw 0xe240, 0xc82d, 0xe27f, 0xc82d, 0x21, 0 - .dw 0xe2c0, 0xc82d, 0xe2ff, 0xc82d, 0x21, 0 - .dw 0xe340, 0xc82d, 0xe37f, 0xc82d, 0x21, 0 - .dw 0xe3c0, 0xc82d, 0xe3ff, 0xc82d, 0x21, 0 - .dw 0xe440, 0xc82d, 0xe47f, 0xc82d, 0x21, 0 - .dw 0xe4c0, 0xc82d, 0xe4ff, 0xc82d, 0x21, 0 - .dw 0xe540, 0xc82d, 0xe57f, 0xc82d, 0x21, 0 - .dw 0xe5c0, 0xc82d, 0xe5ff, 0xc82d, 0x21, 0 - .dw 0xe640, 0xc82d, 0xe67f, 0xc82d, 0x21, 0 - .dw 0xe6c0, 0xc82d, 0xe6ff, 0xc82d, 0x21, 0 - .dw 0xe740, 0xc82d, 0xe77f, 0xc82d, 0x21, 0 - .dw 0xe7c0, 0xc82d, 0xe7ff, 0xc82d, 0x21, 0 - .dw 0xe840, 0xc82d, 0xe87f, 0xc82d, 0x21, 0 - .dw 0xe8c0, 0xc82d, 0xe8ff, 0xc82d, 0x21, 0 - .dw 0xe940, 0xc82d, 0xe97f, 0xc82d, 0x21, 0 - .dw 0xe9c0, 0xc82d, 0xe9ff, 0xc82d, 0x21, 0 - .dw 0xea40, 0xc82d, 0xea7f, 0xc82d, 0x21, 0 - .dw 0xeac0, 0xc82d, 0xeaff, 0xc82d, 0x21, 0 - .dw 0xeb40, 0xc82d, 0xeb7f, 0xc82d, 0x21, 0 - .dw 0xebc0, 0xc82d, 0xebff, 0xc82d, 0x21, 0 - .dw 0xec40, 0xc82d, 0xec7f, 0xc82d, 0x21, 0 - .dw 0xecc0, 0xc82d, 0xecff, 0xc82d, 0x21, 0 - .dw 0xed40, 0xc82d, 0xed7f, 0xc82d, 0x21, 0 - .dw 0xedc0, 0xc82d, 0xedff, 0xc82d, 0x21, 0 - .dw 0xee40, 0xc82d, 0xee7f, 0xc82d, 0x21, 0 - .dw 0xeec0, 0xc82d, 0xeeff, 0xc82d, 0x21, 0 - .dw 0xef40, 0xc82d, 0xef7f, 0xc82d, 0x21, 0 - .dw 0xefc0, 0xc82d, 0xefff, 0xc82d, 0x21, 0 - .dw 0xf040, 0xc82d, 0xf07f, 0xc82d, 0x21, 0 - .dw 0xf0c0, 0xc82d, 0xf0ff, 0xc82d, 0x21, 0 - .dw 0xf140, 0xc82d, 0xf17f, 0xc82d, 0x21, 0 - .dw 0xf1c0, 0xc82d, 0xf1ff, 0xc82d, 0x21, 0 - .dw 0xf240, 0xc82d, 0xf27f, 0xc82d, 0x21, 0 - .dw 0xf2c0, 0xc82d, 0xf2ff, 0xc82d, 0x21, 0 - .dw 0xf340, 0xc82d, 0xf37f, 0xc82d, 0x21, 0 - .dw 0xf3c0, 0xc82d, 0xf3ff, 0xc82d, 0x21, 0 - .dw 0xf440, 0xc82d, 0xf47f, 0xc82d, 0x21, 0 - .dw 0xf4c0, 0xc82d, 0xf4ff, 0xc82d, 0x21, 0 - .dw 0xf540, 0xc82d, 0xf57f, 0xc82d, 0x21, 0 - .dw 0xf5c0, 0xc82d, 0xf5ff, 0xc82d, 0x21, 0 - .dw 0xf640, 0xc82d, 0xf67f, 0xc82d, 0x21, 0 - .dw 0xf6c0, 0xc82d, 0xf6ff, 0xc82d, 0x21, 0 - .dw 0xf740, 0xc82d, 0xf77f, 0xc82d, 0x21, 0 - .dw 0xf7c0, 0xc82d, 0xf7ff, 0xc82d, 0x21, 0 - .dw 0xf840, 0xc82d, 0xf87f, 0xc82d, 0x21, 0 - .dw 0xf8c0, 0xc82d, 0xf8ff, 0xc82d, 0x21, 0 - .dw 0xf940, 0xc82d, 0xf97f, 0xc82d, 0x21, 0 - .dw 0xf9c0, 0xc82d, 0xffff, 0xc82d, 0x21, 0 - .dw 0x0040, 0xc82e, 0x007f, 0xc82e, 0x21, 0 - .dw 0x00c0, 0xc82e, 0x00ff, 0xc82e, 0x21, 0 - .dw 0x0140, 0xc82e, 0x017f, 0xc82e, 0x21, 0 - .dw 0x01c0, 0xc82e, 0x01ff, 0xc82e, 0x21, 0 - .dw 0x0240, 0xc82e, 0x027f, 0xc82e, 0x21, 0 - .dw 0x02c0, 0xc82e, 0x02ff, 0xc82e, 0x21, 0 - .dw 0x0340, 0xc82e, 0x037f, 0xc82e, 0x21, 0 - .dw 0x03c0, 0xc82e, 0x03ff, 0xc82e, 0x21, 0 - .dw 0x0440, 0xc82e, 0x047f, 0xc82e, 0x21, 0 - .dw 0x04c0, 0xc82e, 0x04ff, 0xc82e, 0x21, 0 - .dw 0x0540, 0xc82e, 0x057f, 0xc82e, 0x21, 0 - .dw 0x05c0, 0xc82e, 0x05ff, 0xc82e, 0x21, 0 - .dw 0x0640, 0xc82e, 0x067f, 0xc82e, 0x21, 0 - .dw 0x06c0, 0xc82e, 0x06ff, 0xc82e, 0x21, 0 - .dw 0x0740, 0xc82e, 0x077f, 0xc82e, 0x21, 0 - .dw 0x07c0, 0xc82e, 0x07ff, 0xc82e, 0x21, 0 - .dw 0x0840, 0xc82e, 0x087f, 0xc82e, 0x21, 0 - .dw 0x08c0, 0xc82e, 0x08ff, 0xc82e, 0x21, 0 - .dw 0x0940, 0xc82e, 0x097f, 0xc82e, 0x21, 0 - .dw 0x09c0, 0xc82e, 0x09ff, 0xc82e, 0x21, 0 - .dw 0x0a40, 0xc82e, 0x0a7f, 0xc82e, 0x21, 0 - .dw 0x0ac0, 0xc82e, 0x0aff, 0xc82e, 0x21, 0 - .dw 0x0b40, 0xc82e, 0x0b7f, 0xc82e, 0x21, 0 - .dw 0x0bc0, 0xc82e, 0x0bff, 0xc82e, 0x21, 0 - .dw 0x0c40, 0xc82e, 0x0c7f, 0xc82e, 0x21, 0 - .dw 0x0cc0, 0xc82e, 0x0cff, 0xc82e, 0x21, 0 - .dw 0x0d40, 0xc82e, 0x0d7f, 0xc82e, 0x21, 0 - .dw 0x0dc0, 0xc82e, 0x0dff, 0xc82e, 0x21, 0 - .dw 0x0e40, 0xc82e, 0x0e7f, 0xc82e, 0x21, 0 - .dw 0x0ec0, 0xc82e, 0x0eff, 0xc82e, 0x21, 0 - .dw 0x0f40, 0xc82e, 0x0f7f, 0xc82e, 0x21, 0 - .dw 0x0fc0, 0xc82e, 0x0fff, 0xc82e, 0x21, 0 - .dw 0x1040, 0xc82e, 0x107f, 0xc82e, 0x21, 0 - .dw 0x10c0, 0xc82e, 0x10ff, 0xc82e, 0x21, 0 - .dw 0x1140, 0xc82e, 0x117f, 0xc82e, 0x21, 0 - .dw 0x11c0, 0xc82e, 0x11ff, 0xc82e, 0x21, 0 - .dw 0x1240, 0xc82e, 0x127f, 0xc82e, 0x21, 0 - .dw 0x12c0, 0xc82e, 0x12ff, 0xc82e, 0x21, 0 - .dw 0x1340, 0xc82e, 0x137f, 0xc82e, 0x21, 0 - .dw 0x13c0, 0xc82e, 0x13ff, 0xc82e, 0x21, 0 - .dw 0x1440, 0xc82e, 0x147f, 0xc82e, 0x21, 0 - .dw 0x14c0, 0xc82e, 0x14ff, 0xc82e, 0x21, 0 - .dw 0x1540, 0xc82e, 0x157f, 0xc82e, 0x21, 0 - .dw 0x15c0, 0xc82e, 0x15ff, 0xc82e, 0x21, 0 - .dw 0x1640, 0xc82e, 0x167f, 0xc82e, 0x21, 0 - .dw 0x16c0, 0xc82e, 0x16ff, 0xc82e, 0x21, 0 - .dw 0x1740, 0xc82e, 0x177f, 0xc82e, 0x21, 0 - .dw 0x17c0, 0xc82e, 0x17ff, 0xc82e, 0x21, 0 - .dw 0x1840, 0xc82e, 0x187f, 0xc82e, 0x21, 0 - .dw 0x18c0, 0xc82e, 0x18ff, 0xc82e, 0x21, 0 - .dw 0x1940, 0xc82e, 0x197f, 0xc82e, 0x21, 0 - .dw 0x19c0, 0xc82e, 0x1fff, 0xc82e, 0x21, 0 - .dw 0x2040, 0xc82e, 0x207f, 0xc82e, 0x21, 0 - .dw 0x20c0, 0xc82e, 0x20ff, 0xc82e, 0x21, 0 - .dw 0x2140, 0xc82e, 0x217f, 0xc82e, 0x21, 0 - .dw 0x21c0, 0xc82e, 0x21ff, 0xc82e, 0x21, 0 - .dw 0x2240, 0xc82e, 0x227f, 0xc82e, 0x21, 0 - .dw 0x22c0, 0xc82e, 0x22ff, 0xc82e, 0x21, 0 - .dw 0x2340, 0xc82e, 0x237f, 0xc82e, 0x21, 0 - .dw 0x23c0, 0xc82e, 0x23ff, 0xc82e, 0x21, 0 - .dw 0x2440, 0xc82e, 0x247f, 0xc82e, 0x21, 0 - .dw 0x24c0, 0xc82e, 0x24ff, 0xc82e, 0x21, 0 - .dw 0x2540, 0xc82e, 0x257f, 0xc82e, 0x21, 0 - .dw 0x25c0, 0xc82e, 0x25ff, 0xc82e, 0x21, 0 - .dw 0x2640, 0xc82e, 0x267f, 0xc82e, 0x21, 0 - .dw 0x26c0, 0xc82e, 0x26ff, 0xc82e, 0x21, 0 - .dw 0x2740, 0xc82e, 0x277f, 0xc82e, 0x21, 0 - .dw 0x27c0, 0xc82e, 0x27ff, 0xc82e, 0x21, 0 - .dw 0x2840, 0xc82e, 0x287f, 0xc82e, 0x21, 0 - .dw 0x28c0, 0xc82e, 0x28ff, 0xc82e, 0x21, 0 - .dw 0x2940, 0xc82e, 0x297f, 0xc82e, 0x21, 0 - .dw 0x29c0, 0xc82e, 0x29ff, 0xc82e, 0x21, 0 - .dw 0x2a40, 0xc82e, 0x2a7f, 0xc82e, 0x21, 0 - .dw 0x2ac0, 0xc82e, 0x2aff, 0xc82e, 0x21, 0 - .dw 0x2b40, 0xc82e, 0x2b7f, 0xc82e, 0x21, 0 - .dw 0x2bc0, 0xc82e, 0x2bff, 0xc82e, 0x21, 0 - .dw 0x2c40, 0xc82e, 0x2c7f, 0xc82e, 0x21, 0 - .dw 0x2cc0, 0xc82e, 0x2cff, 0xc82e, 0x21, 0 - .dw 0x2d40, 0xc82e, 0x2d7f, 0xc82e, 0x21, 0 - .dw 0x2dc0, 0xc82e, 0x2dff, 0xc82e, 0x21, 0 - .dw 0x2e40, 0xc82e, 0x2e7f, 0xc82e, 0x21, 0 - .dw 0x2ec0, 0xc82e, 0x2eff, 0xc82e, 0x21, 0 - .dw 0x2f40, 0xc82e, 0x2f7f, 0xc82e, 0x21, 0 - .dw 0x2fc0, 0xc82e, 0x2fff, 0xc82e, 0x21, 0 - .dw 0x3040, 0xc82e, 0x307f, 0xc82e, 0x21, 0 - .dw 0x30c0, 0xc82e, 0x30ff, 0xc82e, 0x21, 0 - .dw 0x3140, 0xc82e, 0x317f, 0xc82e, 0x21, 0 - .dw 0x31c0, 0xc82e, 0x31ff, 0xc82e, 0x21, 0 - .dw 0x3240, 0xc82e, 0x327f, 0xc82e, 0x21, 0 - .dw 0x32c0, 0xc82e, 0x32ff, 0xc82e, 0x21, 0 - .dw 0x3340, 0xc82e, 0x337f, 0xc82e, 0x21, 0 - .dw 0x33c0, 0xc82e, 0x33ff, 0xc82e, 0x21, 0 - .dw 0x3440, 0xc82e, 0x347f, 0xc82e, 0x21, 0 - .dw 0x34c0, 0xc82e, 0x34ff, 0xc82e, 0x21, 0 - .dw 0x3540, 0xc82e, 0x357f, 0xc82e, 0x21, 0 - .dw 0x35c0, 0xc82e, 0x35ff, 0xc82e, 0x21, 0 - .dw 0x3640, 0xc82e, 0x367f, 0xc82e, 0x21, 0 - .dw 0x36c0, 0xc82e, 0x36ff, 0xc82e, 0x21, 0 - .dw 0x3740, 0xc82e, 0x377f, 0xc82e, 0x21, 0 - .dw 0x37c0, 0xc82e, 0x37ff, 0xc82e, 0x21, 0 - .dw 0x3840, 0xc82e, 0x387f, 0xc82e, 0x21, 0 - .dw 0x38c0, 0xc82e, 0x38ff, 0xc82e, 0x21, 0 - .dw 0x3940, 0xc82e, 0x397f, 0xc82e, 0x21, 0 - .dw 0x39c0, 0xc82e, 0x3fff, 0xc82e, 0x21, 0 - .dw 0x4040, 0xc82e, 0x407f, 0xc82e, 0x21, 0 - .dw 0x40c0, 0xc82e, 0x40ff, 0xc82e, 0x21, 0 - .dw 0x4140, 0xc82e, 0x417f, 0xc82e, 0x21, 0 - .dw 0x41c0, 0xc82e, 0x41ff, 0xc82e, 0x21, 0 - .dw 0x4240, 0xc82e, 0x427f, 0xc82e, 0x21, 0 - .dw 0x42c0, 0xc82e, 0x42ff, 0xc82e, 0x21, 0 - .dw 0x4340, 0xc82e, 0x437f, 0xc82e, 0x21, 0 - .dw 0x43c0, 0xc82e, 0x43ff, 0xc82e, 0x21, 0 - .dw 0x4440, 0xc82e, 0x447f, 0xc82e, 0x21, 0 - .dw 0x44c0, 0xc82e, 0x44ff, 0xc82e, 0x21, 0 - .dw 0x4540, 0xc82e, 0x457f, 0xc82e, 0x21, 0 - .dw 0x45c0, 0xc82e, 0x45ff, 0xc82e, 0x21, 0 - .dw 0x4640, 0xc82e, 0x467f, 0xc82e, 0x21, 0 - .dw 0x46c0, 0xc82e, 0x46ff, 0xc82e, 0x21, 0 - .dw 0x4740, 0xc82e, 0x477f, 0xc82e, 0x21, 0 - .dw 0x47c0, 0xc82e, 0x47ff, 0xc82e, 0x21, 0 - .dw 0x4840, 0xc82e, 0x487f, 0xc82e, 0x21, 0 - .dw 0x48c0, 0xc82e, 0x48ff, 0xc82e, 0x21, 0 - .dw 0x4940, 0xc82e, 0x497f, 0xc82e, 0x21, 0 - .dw 0x49c0, 0xc82e, 0x49ff, 0xc82e, 0x21, 0 - .dw 0x4a40, 0xc82e, 0x4a7f, 0xc82e, 0x21, 0 - .dw 0x4ac0, 0xc82e, 0x4aff, 0xc82e, 0x21, 0 - .dw 0x4b40, 0xc82e, 0x4b7f, 0xc82e, 0x21, 0 - .dw 0x4bc0, 0xc82e, 0x4bff, 0xc82e, 0x21, 0 - .dw 0x4c40, 0xc82e, 0x4c7f, 0xc82e, 0x21, 0 - .dw 0x4cc0, 0xc82e, 0x4cff, 0xc82e, 0x21, 0 - .dw 0x4d40, 0xc82e, 0x4d7f, 0xc82e, 0x21, 0 - .dw 0x4dc0, 0xc82e, 0x4dff, 0xc82e, 0x21, 0 - .dw 0x4e40, 0xc82e, 0x4e7f, 0xc82e, 0x21, 0 - .dw 0x4ec0, 0xc82e, 0x4eff, 0xc82e, 0x21, 0 - .dw 0x4f40, 0xc82e, 0x4f7f, 0xc82e, 0x21, 0 - .dw 0x4fc0, 0xc82e, 0x4fff, 0xc82e, 0x21, 0 - .dw 0x5040, 0xc82e, 0x507f, 0xc82e, 0x21, 0 - .dw 0x50c0, 0xc82e, 0x50ff, 0xc82e, 0x21, 0 - .dw 0x5140, 0xc82e, 0x517f, 0xc82e, 0x21, 0 - .dw 0x51c0, 0xc82e, 0x51ff, 0xc82e, 0x21, 0 - .dw 0x5240, 0xc82e, 0x527f, 0xc82e, 0x21, 0 - .dw 0x52c0, 0xc82e, 0x52ff, 0xc82e, 0x21, 0 - .dw 0x5340, 0xc82e, 0x537f, 0xc82e, 0x21, 0 - .dw 0x53c0, 0xc82e, 0x53ff, 0xc82e, 0x21, 0 - .dw 0x5440, 0xc82e, 0x547f, 0xc82e, 0x21, 0 - .dw 0x54c0, 0xc82e, 0x54ff, 0xc82e, 0x21, 0 - .dw 0x5540, 0xc82e, 0x557f, 0xc82e, 0x21, 0 - .dw 0x55c0, 0xc82e, 0x55ff, 0xc82e, 0x21, 0 - .dw 0x5640, 0xc82e, 0x567f, 0xc82e, 0x21, 0 - .dw 0x56c0, 0xc82e, 0x56ff, 0xc82e, 0x21, 0 - .dw 0x5740, 0xc82e, 0x577f, 0xc82e, 0x21, 0 - .dw 0x57c0, 0xc82e, 0x57ff, 0xc82e, 0x21, 0 - .dw 0x5840, 0xc82e, 0x587f, 0xc82e, 0x21, 0 - .dw 0x58c0, 0xc82e, 0x58ff, 0xc82e, 0x21, 0 - .dw 0x5940, 0xc82e, 0x597f, 0xc82e, 0x21, 0 - .dw 0x59c0, 0xc82e, 0x5fff, 0xc82e, 0x21, 0 - .dw 0x6040, 0xc82e, 0x607f, 0xc82e, 0x21, 0 - .dw 0x60c0, 0xc82e, 0x60ff, 0xc82e, 0x21, 0 - .dw 0x6140, 0xc82e, 0x617f, 0xc82e, 0x21, 0 - .dw 0x61c0, 0xc82e, 0x61ff, 0xc82e, 0x21, 0 - .dw 0x6240, 0xc82e, 0x627f, 0xc82e, 0x21, 0 - .dw 0x62c0, 0xc82e, 0x62ff, 0xc82e, 0x21, 0 - .dw 0x6340, 0xc82e, 0x637f, 0xc82e, 0x21, 0 - .dw 0x63c0, 0xc82e, 0x63ff, 0xc82e, 0x21, 0 - .dw 0x6440, 0xc82e, 0x647f, 0xc82e, 0x21, 0 - .dw 0x64c0, 0xc82e, 0x64ff, 0xc82e, 0x21, 0 - .dw 0x6540, 0xc82e, 0x657f, 0xc82e, 0x21, 0 - .dw 0x65c0, 0xc82e, 0x65ff, 0xc82e, 0x21, 0 - .dw 0x6640, 0xc82e, 0x667f, 0xc82e, 0x21, 0 - .dw 0x66c0, 0xc82e, 0x66ff, 0xc82e, 0x21, 0 - .dw 0x6740, 0xc82e, 0x677f, 0xc82e, 0x21, 0 - .dw 0x67c0, 0xc82e, 0x67ff, 0xc82e, 0x21, 0 - .dw 0x6840, 0xc82e, 0x687f, 0xc82e, 0x21, 0 - .dw 0x68c0, 0xc82e, 0x68ff, 0xc82e, 0x21, 0 - .dw 0x6940, 0xc82e, 0x697f, 0xc82e, 0x21, 0 - .dw 0x69c0, 0xc82e, 0x69ff, 0xc82e, 0x21, 0 - .dw 0x6a40, 0xc82e, 0x6a7f, 0xc82e, 0x21, 0 - .dw 0x6ac0, 0xc82e, 0x6aff, 0xc82e, 0x21, 0 - .dw 0x6b40, 0xc82e, 0x6b7f, 0xc82e, 0x21, 0 - .dw 0x6bc0, 0xc82e, 0x6bff, 0xc82e, 0x21, 0 - .dw 0x6c40, 0xc82e, 0x6c7f, 0xc82e, 0x21, 0 - .dw 0x6cc0, 0xc82e, 0x6cff, 0xc82e, 0x21, 0 - .dw 0x6d40, 0xc82e, 0x6d7f, 0xc82e, 0x21, 0 - .dw 0x6dc0, 0xc82e, 0x6dff, 0xc82e, 0x21, 0 - .dw 0x6e40, 0xc82e, 0x6e7f, 0xc82e, 0x21, 0 - .dw 0x6ec0, 0xc82e, 0x6eff, 0xc82e, 0x21, 0 - .dw 0x6f40, 0xc82e, 0x6f7f, 0xc82e, 0x21, 0 - .dw 0x6fc0, 0xc82e, 0x6fff, 0xc82e, 0x21, 0 - .dw 0x7040, 0xc82e, 0x707f, 0xc82e, 0x21, 0 - .dw 0x70c0, 0xc82e, 0x70ff, 0xc82e, 0x21, 0 - .dw 0x7140, 0xc82e, 0x717f, 0xc82e, 0x21, 0 - .dw 0x71c0, 0xc82e, 0x71ff, 0xc82e, 0x21, 0 - .dw 0x7240, 0xc82e, 0x727f, 0xc82e, 0x21, 0 - .dw 0x72c0, 0xc82e, 0x72ff, 0xc82e, 0x21, 0 - .dw 0x7340, 0xc82e, 0x737f, 0xc82e, 0x21, 0 - .dw 0x73c0, 0xc82e, 0x73ff, 0xc82e, 0x21, 0 - .dw 0x7440, 0xc82e, 0x747f, 0xc82e, 0x21, 0 - .dw 0x74c0, 0xc82e, 0x74ff, 0xc82e, 0x21, 0 - .dw 0x7540, 0xc82e, 0x757f, 0xc82e, 0x21, 0 - .dw 0x75c0, 0xc82e, 0x75ff, 0xc82e, 0x21, 0 - .dw 0x7640, 0xc82e, 0x767f, 0xc82e, 0x21, 0 - .dw 0x76c0, 0xc82e, 0x76ff, 0xc82e, 0x21, 0 - .dw 0x7740, 0xc82e, 0x777f, 0xc82e, 0x21, 0 - .dw 0x77c0, 0xc82e, 0x77ff, 0xc82e, 0x21, 0 - .dw 0x7840, 0xc82e, 0x787f, 0xc82e, 0x21, 0 - .dw 0x78c0, 0xc82e, 0x78ff, 0xc82e, 0x21, 0 - .dw 0x7940, 0xc82e, 0x797f, 0xc82e, 0x21, 0 - .dw 0x79c0, 0xc82e, 0x7fff, 0xc82e, 0x21, 0 - .dw 0x8040, 0xc82e, 0x807f, 0xc82e, 0x21, 0 - .dw 0x80c0, 0xc82e, 0x80ff, 0xc82e, 0x21, 0 - .dw 0x8140, 0xc82e, 0x817f, 0xc82e, 0x21, 0 - .dw 0x81c0, 0xc82e, 0x81ff, 0xc82e, 0x21, 0 - .dw 0x8240, 0xc82e, 0x827f, 0xc82e, 0x21, 0 - .dw 0x82c0, 0xc82e, 0x82ff, 0xc82e, 0x21, 0 - .dw 0x8340, 0xc82e, 0x837f, 0xc82e, 0x21, 0 - .dw 0x83c0, 0xc82e, 0x83ff, 0xc82e, 0x21, 0 - .dw 0x8440, 0xc82e, 0x847f, 0xc82e, 0x21, 0 - .dw 0x84c0, 0xc82e, 0x84ff, 0xc82e, 0x21, 0 - .dw 0x8540, 0xc82e, 0x857f, 0xc82e, 0x21, 0 - .dw 0x85c0, 0xc82e, 0x85ff, 0xc82e, 0x21, 0 - .dw 0x8640, 0xc82e, 0x867f, 0xc82e, 0x21, 0 - .dw 0x86c0, 0xc82e, 0x86ff, 0xc82e, 0x21, 0 - .dw 0x8740, 0xc82e, 0x877f, 0xc82e, 0x21, 0 - .dw 0x87c0, 0xc82e, 0x87ff, 0xc82e, 0x21, 0 - .dw 0x8840, 0xc82e, 0x887f, 0xc82e, 0x21, 0 - .dw 0x88c0, 0xc82e, 0x88ff, 0xc82e, 0x21, 0 - .dw 0x8940, 0xc82e, 0x897f, 0xc82e, 0x21, 0 - .dw 0x89c0, 0xc82e, 0x89ff, 0xc82e, 0x21, 0 - .dw 0x8a40, 0xc82e, 0x8a7f, 0xc82e, 0x21, 0 - .dw 0x8ac0, 0xc82e, 0x8aff, 0xc82e, 0x21, 0 - .dw 0x8b40, 0xc82e, 0x8b7f, 0xc82e, 0x21, 0 - .dw 0x8bc0, 0xc82e, 0x8bff, 0xc82e, 0x21, 0 - .dw 0x8c40, 0xc82e, 0x8c7f, 0xc82e, 0x21, 0 - .dw 0x8cc0, 0xc82e, 0x8cff, 0xc82e, 0x21, 0 - .dw 0x8d40, 0xc82e, 0x8d7f, 0xc82e, 0x21, 0 - .dw 0x8dc0, 0xc82e, 0x8dff, 0xc82e, 0x21, 0 - .dw 0x8e40, 0xc82e, 0x8e7f, 0xc82e, 0x21, 0 - .dw 0x8ec0, 0xc82e, 0x8eff, 0xc82e, 0x21, 0 - .dw 0x8f40, 0xc82e, 0x8f7f, 0xc82e, 0x21, 0 - .dw 0x8fc0, 0xc82e, 0x8fff, 0xc82e, 0x21, 0 - .dw 0x9040, 0xc82e, 0x907f, 0xc82e, 0x21, 0 - .dw 0x90c0, 0xc82e, 0x90ff, 0xc82e, 0x21, 0 - .dw 0x9140, 0xc82e, 0x917f, 0xc82e, 0x21, 0 - .dw 0x91c0, 0xc82e, 0x91ff, 0xc82e, 0x21, 0 - .dw 0x9240, 0xc82e, 0x927f, 0xc82e, 0x21, 0 - .dw 0x92c0, 0xc82e, 0x92ff, 0xc82e, 0x21, 0 - .dw 0x9340, 0xc82e, 0x937f, 0xc82e, 0x21, 0 - .dw 0x93c0, 0xc82e, 0x93ff, 0xc82e, 0x21, 0 - .dw 0x9440, 0xc82e, 0x947f, 0xc82e, 0x21, 0 - .dw 0x94c0, 0xc82e, 0x94ff, 0xc82e, 0x21, 0 - .dw 0x9540, 0xc82e, 0x957f, 0xc82e, 0x21, 0 - .dw 0x95c0, 0xc82e, 0x95ff, 0xc82e, 0x21, 0 - .dw 0x9640, 0xc82e, 0x967f, 0xc82e, 0x21, 0 - .dw 0x96c0, 0xc82e, 0x96ff, 0xc82e, 0x21, 0 - .dw 0x9740, 0xc82e, 0x977f, 0xc82e, 0x21, 0 - .dw 0x97c0, 0xc82e, 0x97ff, 0xc82e, 0x21, 0 - .dw 0x9840, 0xc82e, 0x987f, 0xc82e, 0x21, 0 - .dw 0x98c0, 0xc82e, 0x98ff, 0xc82e, 0x21, 0 - .dw 0x9940, 0xc82e, 0x997f, 0xc82e, 0x21, 0 - .dw 0x99c0, 0xc82e, 0x9fff, 0xc82e, 0x21, 0 - .dw 0xa040, 0xc82e, 0xa07f, 0xc82e, 0x21, 0 - .dw 0xa0c0, 0xc82e, 0xa0ff, 0xc82e, 0x21, 0 - .dw 0xa140, 0xc82e, 0xa17f, 0xc82e, 0x21, 0 - .dw 0xa1c0, 0xc82e, 0xa1ff, 0xc82e, 0x21, 0 - .dw 0xa240, 0xc82e, 0xa27f, 0xc82e, 0x21, 0 - .dw 0xa2c0, 0xc82e, 0xa2ff, 0xc82e, 0x21, 0 - .dw 0xa340, 0xc82e, 0xa37f, 0xc82e, 0x21, 0 - .dw 0xa3c0, 0xc82e, 0xa3ff, 0xc82e, 0x21, 0 - .dw 0xa440, 0xc82e, 0xa47f, 0xc82e, 0x21, 0 - .dw 0xa4c0, 0xc82e, 0xa4ff, 0xc82e, 0x21, 0 - .dw 0xa540, 0xc82e, 0xa57f, 0xc82e, 0x21, 0 - .dw 0xa5c0, 0xc82e, 0xa5ff, 0xc82e, 0x21, 0 - .dw 0xa640, 0xc82e, 0xa67f, 0xc82e, 0x21, 0 - .dw 0xa6c0, 0xc82e, 0xa6ff, 0xc82e, 0x21, 0 - .dw 0xa740, 0xc82e, 0xa77f, 0xc82e, 0x21, 0 - .dw 0xa7c0, 0xc82e, 0xa7ff, 0xc82e, 0x21, 0 - .dw 0xa840, 0xc82e, 0xa87f, 0xc82e, 0x21, 0 - .dw 0xa8c0, 0xc82e, 0xa8ff, 0xc82e, 0x21, 0 - .dw 0xa940, 0xc82e, 0xa97f, 0xc82e, 0x21, 0 - .dw 0xa9c0, 0xc82e, 0xa9ff, 0xc82e, 0x21, 0 - .dw 0xaa40, 0xc82e, 0xaa7f, 0xc82e, 0x21, 0 - .dw 0xaac0, 0xc82e, 0xaaff, 0xc82e, 0x21, 0 - .dw 0xab40, 0xc82e, 0xab7f, 0xc82e, 0x21, 0 - .dw 0xabc0, 0xc82e, 0xabff, 0xc82e, 0x21, 0 - .dw 0xac40, 0xc82e, 0xac7f, 0xc82e, 0x21, 0 - .dw 0xacc0, 0xc82e, 0xacff, 0xc82e, 0x21, 0 - .dw 0xad40, 0xc82e, 0xad7f, 0xc82e, 0x21, 0 - .dw 0xadc0, 0xc82e, 0xadff, 0xc82e, 0x21, 0 - .dw 0xae40, 0xc82e, 0xae7f, 0xc82e, 0x21, 0 - .dw 0xaec0, 0xc82e, 0xaeff, 0xc82e, 0x21, 0 - .dw 0xaf40, 0xc82e, 0xaf7f, 0xc82e, 0x21, 0 - .dw 0xafc0, 0xc82e, 0xafff, 0xc82e, 0x21, 0 - .dw 0xb040, 0xc82e, 0xb07f, 0xc82e, 0x21, 0 - .dw 0xb0c0, 0xc82e, 0xb0ff, 0xc82e, 0x21, 0 - .dw 0xb140, 0xc82e, 0xb17f, 0xc82e, 0x21, 0 - .dw 0xb1c0, 0xc82e, 0xb1ff, 0xc82e, 0x21, 0 - .dw 0xb240, 0xc82e, 0xb27f, 0xc82e, 0x21, 0 - .dw 0xb2c0, 0xc82e, 0xb2ff, 0xc82e, 0x21, 0 - .dw 0xb340, 0xc82e, 0xb37f, 0xc82e, 0x21, 0 - .dw 0xb3c0, 0xc82e, 0xb3ff, 0xc82e, 0x21, 0 - .dw 0xb440, 0xc82e, 0xb47f, 0xc82e, 0x21, 0 - .dw 0xb4c0, 0xc82e, 0xb4ff, 0xc82e, 0x21, 0 - .dw 0xb540, 0xc82e, 0xb57f, 0xc82e, 0x21, 0 - .dw 0xb5c0, 0xc82e, 0xb5ff, 0xc82e, 0x21, 0 - .dw 0xb640, 0xc82e, 0xb67f, 0xc82e, 0x21, 0 - .dw 0xb6c0, 0xc82e, 0xb6ff, 0xc82e, 0x21, 0 - .dw 0xb740, 0xc82e, 0xb77f, 0xc82e, 0x21, 0 - .dw 0xb7c0, 0xc82e, 0xb7ff, 0xc82e, 0x21, 0 - .dw 0xb840, 0xc82e, 0xb87f, 0xc82e, 0x21, 0 - .dw 0xb8c0, 0xc82e, 0xb8ff, 0xc82e, 0x21, 0 - .dw 0xb940, 0xc82e, 0xb97f, 0xc82e, 0x21, 0 - .dw 0xb9c0, 0xc82e, 0xbfff, 0xc82e, 0x21, 0 - .dw 0xc040, 0xc82e, 0xc07f, 0xc82e, 0x21, 0 - .dw 0xc0c0, 0xc82e, 0xc0ff, 0xc82e, 0x21, 0 - .dw 0xc140, 0xc82e, 0xc17f, 0xc82e, 0x21, 0 - .dw 0xc1c0, 0xc82e, 0xc1ff, 0xc82e, 0x21, 0 - .dw 0xc240, 0xc82e, 0xc27f, 0xc82e, 0x21, 0 - .dw 0xc2c0, 0xc82e, 0xc2ff, 0xc82e, 0x21, 0 - .dw 0xc340, 0xc82e, 0xc37f, 0xc82e, 0x21, 0 - .dw 0xc3c0, 0xc82e, 0xc3ff, 0xc82e, 0x21, 0 - .dw 0xc440, 0xc82e, 0xc47f, 0xc82e, 0x21, 0 - .dw 0xc4c0, 0xc82e, 0xc4ff, 0xc82e, 0x21, 0 - .dw 0xc540, 0xc82e, 0xc57f, 0xc82e, 0x21, 0 - .dw 0xc5c0, 0xc82e, 0xc5ff, 0xc82e, 0x21, 0 - .dw 0xc640, 0xc82e, 0xc67f, 0xc82e, 0x21, 0 - .dw 0xc6c0, 0xc82e, 0xc6ff, 0xc82e, 0x21, 0 - .dw 0xc740, 0xc82e, 0xc77f, 0xc82e, 0x21, 0 - .dw 0xc7c0, 0xc82e, 0xc7ff, 0xc82e, 0x21, 0 - .dw 0xc840, 0xc82e, 0xc87f, 0xc82e, 0x21, 0 - .dw 0xc8c0, 0xc82e, 0xc8ff, 0xc82e, 0x21, 0 - .dw 0xc940, 0xc82e, 0xc97f, 0xc82e, 0x21, 0 - .dw 0xc9c0, 0xc82e, 0xc9ff, 0xc82e, 0x21, 0 - .dw 0xca40, 0xc82e, 0xca7f, 0xc82e, 0x21, 0 - .dw 0xcac0, 0xc82e, 0xcaff, 0xc82e, 0x21, 0 - .dw 0xcb40, 0xc82e, 0xcb7f, 0xc82e, 0x21, 0 - .dw 0xcbc0, 0xc82e, 0xcbff, 0xc82e, 0x21, 0 - .dw 0xcc40, 0xc82e, 0xcc7f, 0xc82e, 0x21, 0 - .dw 0xccc0, 0xc82e, 0xccff, 0xc82e, 0x21, 0 - .dw 0xcd40, 0xc82e, 0xcd7f, 0xc82e, 0x21, 0 - .dw 0xcdc0, 0xc82e, 0xcdff, 0xc82e, 0x21, 0 - .dw 0xce40, 0xc82e, 0xce7f, 0xc82e, 0x21, 0 - .dw 0xcec0, 0xc82e, 0xceff, 0xc82e, 0x21, 0 - .dw 0xcf40, 0xc82e, 0xcf7f, 0xc82e, 0x21, 0 - .dw 0xcfc0, 0xc82e, 0xcfff, 0xc82e, 0x21, 0 - .dw 0xd040, 0xc82e, 0xd07f, 0xc82e, 0x21, 0 - .dw 0xd0c0, 0xc82e, 0xd0ff, 0xc82e, 0x21, 0 - .dw 0xd140, 0xc82e, 0xd17f, 0xc82e, 0x21, 0 - .dw 0xd1c0, 0xc82e, 0xd1ff, 0xc82e, 0x21, 0 - .dw 0xd240, 0xc82e, 0xd27f, 0xc82e, 0x21, 0 - .dw 0xd2c0, 0xc82e, 0xd2ff, 0xc82e, 0x21, 0 - .dw 0xd340, 0xc82e, 0xd37f, 0xc82e, 0x21, 0 - .dw 0xd3c0, 0xc82e, 0xd3ff, 0xc82e, 0x21, 0 - .dw 0xd440, 0xc82e, 0xd47f, 0xc82e, 0x21, 0 - .dw 0xd4c0, 0xc82e, 0xd4ff, 0xc82e, 0x21, 0 - .dw 0xd540, 0xc82e, 0xd57f, 0xc82e, 0x21, 0 - .dw 0xd5c0, 0xc82e, 0xd5ff, 0xc82e, 0x21, 0 - .dw 0xd640, 0xc82e, 0xd67f, 0xc82e, 0x21, 0 - .dw 0xd6c0, 0xc82e, 0xd6ff, 0xc82e, 0x21, 0 - .dw 0xd740, 0xc82e, 0xd77f, 0xc82e, 0x21, 0 - .dw 0xd7c0, 0xc82e, 0xd7ff, 0xc82e, 0x21, 0 - .dw 0xd840, 0xc82e, 0xd87f, 0xc82e, 0x21, 0 - .dw 0xd8c0, 0xc82e, 0xd8ff, 0xc82e, 0x21, 0 - .dw 0xd940, 0xc82e, 0xd97f, 0xc82e, 0x21, 0 - .dw 0xd9c0, 0xc82e, 0xdfff, 0xc82e, 0x21, 0 - .dw 0xe040, 0xc82e, 0xe07f, 0xc82e, 0x21, 0 - .dw 0xe0c0, 0xc82e, 0xe0ff, 0xc82e, 0x21, 0 - .dw 0xe140, 0xc82e, 0xe17f, 0xc82e, 0x21, 0 - .dw 0xe1c0, 0xc82e, 0xe1ff, 0xc82e, 0x21, 0 - .dw 0xe240, 0xc82e, 0xe27f, 0xc82e, 0x21, 0 - .dw 0xe2c0, 0xc82e, 0xe2ff, 0xc82e, 0x21, 0 - .dw 0xe340, 0xc82e, 0xe37f, 0xc82e, 0x21, 0 - .dw 0xe3c0, 0xc82e, 0xe3ff, 0xc82e, 0x21, 0 - .dw 0xe440, 0xc82e, 0xe47f, 0xc82e, 0x21, 0 - .dw 0xe4c0, 0xc82e, 0xe4ff, 0xc82e, 0x21, 0 - .dw 0xe540, 0xc82e, 0xe57f, 0xc82e, 0x21, 0 - .dw 0xe5c0, 0xc82e, 0xe5ff, 0xc82e, 0x21, 0 - .dw 0xe640, 0xc82e, 0xe67f, 0xc82e, 0x21, 0 - .dw 0xe6c0, 0xc82e, 0xe6ff, 0xc82e, 0x21, 0 - .dw 0xe740, 0xc82e, 0xe77f, 0xc82e, 0x21, 0 - .dw 0xe7c0, 0xc82e, 0xe7ff, 0xc82e, 0x21, 0 - .dw 0xe840, 0xc82e, 0xe87f, 0xc82e, 0x21, 0 - .dw 0xe8c0, 0xc82e, 0xe8ff, 0xc82e, 0x21, 0 - .dw 0xe940, 0xc82e, 0xe97f, 0xc82e, 0x21, 0 - .dw 0xe9c0, 0xc82e, 0xe9ff, 0xc82e, 0x21, 0 - .dw 0xea40, 0xc82e, 0xea7f, 0xc82e, 0x21, 0 - .dw 0xeac0, 0xc82e, 0xeaff, 0xc82e, 0x21, 0 - .dw 0xeb40, 0xc82e, 0xeb7f, 0xc82e, 0x21, 0 - .dw 0xebc0, 0xc82e, 0xebff, 0xc82e, 0x21, 0 - .dw 0xec40, 0xc82e, 0xec7f, 0xc82e, 0x21, 0 - .dw 0xecc0, 0xc82e, 0xecff, 0xc82e, 0x21, 0 - .dw 0xed40, 0xc82e, 0xed7f, 0xc82e, 0x21, 0 - .dw 0xedc0, 0xc82e, 0xedff, 0xc82e, 0x21, 0 - .dw 0xee40, 0xc82e, 0xee7f, 0xc82e, 0x21, 0 - .dw 0xeec0, 0xc82e, 0xeeff, 0xc82e, 0x21, 0 - .dw 0xef40, 0xc82e, 0xef7f, 0xc82e, 0x21, 0 - .dw 0xefc0, 0xc82e, 0xefff, 0xc82e, 0x21, 0 - .dw 0xf040, 0xc82e, 0xf07f, 0xc82e, 0x21, 0 - .dw 0xf0c0, 0xc82e, 0xf0ff, 0xc82e, 0x21, 0 - .dw 0xf140, 0xc82e, 0xf17f, 0xc82e, 0x21, 0 - .dw 0xf1c0, 0xc82e, 0xf1ff, 0xc82e, 0x21, 0 - .dw 0xf240, 0xc82e, 0xf27f, 0xc82e, 0x21, 0 - .dw 0xf2c0, 0xc82e, 0xf2ff, 0xc82e, 0x21, 0 - .dw 0xf340, 0xc82e, 0xf37f, 0xc82e, 0x21, 0 - .dw 0xf3c0, 0xc82e, 0xf3ff, 0xc82e, 0x21, 0 - .dw 0xf440, 0xc82e, 0xf47f, 0xc82e, 0x21, 0 - .dw 0xf4c0, 0xc82e, 0xf4ff, 0xc82e, 0x21, 0 - .dw 0xf540, 0xc82e, 0xf57f, 0xc82e, 0x21, 0 - .dw 0xf5c0, 0xc82e, 0xf5ff, 0xc82e, 0x21, 0 - .dw 0xf640, 0xc82e, 0xf67f, 0xc82e, 0x21, 0 - .dw 0xf6c0, 0xc82e, 0xf6ff, 0xc82e, 0x21, 0 - .dw 0xf740, 0xc82e, 0xf77f, 0xc82e, 0x21, 0 - .dw 0xf7c0, 0xc82e, 0xf7ff, 0xc82e, 0x21, 0 - .dw 0xf840, 0xc82e, 0xf87f, 0xc82e, 0x21, 0 - .dw 0xf8c0, 0xc82e, 0xf8ff, 0xc82e, 0x21, 0 - .dw 0xf940, 0xc82e, 0xf97f, 0xc82e, 0x21, 0 - .dw 0xf9c0, 0xc82e, 0xffff, 0xc82e, 0x21, 0 - .dw 0x0040, 0xc82f, 0x007f, 0xc82f, 0x21, 0 - .dw 0x00c0, 0xc82f, 0x00ff, 0xc82f, 0x21, 0 - .dw 0x0140, 0xc82f, 0x017f, 0xc82f, 0x21, 0 - .dw 0x01c0, 0xc82f, 0x01ff, 0xc82f, 0x21, 0 - .dw 0x0240, 0xc82f, 0x027f, 0xc82f, 0x21, 0 - .dw 0x02c0, 0xc82f, 0x02ff, 0xc82f, 0x21, 0 - .dw 0x0340, 0xc82f, 0x037f, 0xc82f, 0x21, 0 - .dw 0x03c0, 0xc82f, 0x03ff, 0xc82f, 0x21, 0 - .dw 0x0440, 0xc82f, 0x047f, 0xc82f, 0x21, 0 - .dw 0x04c0, 0xc82f, 0x04ff, 0xc82f, 0x21, 0 - .dw 0x0540, 0xc82f, 0x057f, 0xc82f, 0x21, 0 - .dw 0x05c0, 0xc82f, 0x05ff, 0xc82f, 0x21, 0 - .dw 0x0640, 0xc82f, 0x067f, 0xc82f, 0x21, 0 - .dw 0x06c0, 0xc82f, 0x06ff, 0xc82f, 0x21, 0 - .dw 0x0740, 0xc82f, 0x077f, 0xc82f, 0x21, 0 - .dw 0x07c0, 0xc82f, 0x07ff, 0xc82f, 0x21, 0 - .dw 0x0840, 0xc82f, 0x087f, 0xc82f, 0x21, 0 - .dw 0x08c0, 0xc82f, 0x08ff, 0xc82f, 0x21, 0 - .dw 0x0940, 0xc82f, 0x097f, 0xc82f, 0x21, 0 - .dw 0x09c0, 0xc82f, 0x09ff, 0xc82f, 0x21, 0 - .dw 0x0a40, 0xc82f, 0x0a7f, 0xc82f, 0x21, 0 - .dw 0x0ac0, 0xc82f, 0x0aff, 0xc82f, 0x21, 0 - .dw 0x0b40, 0xc82f, 0x0b7f, 0xc82f, 0x21, 0 - .dw 0x0bc0, 0xc82f, 0x0bff, 0xc82f, 0x21, 0 - .dw 0x0c40, 0xc82f, 0x0c7f, 0xc82f, 0x21, 0 - .dw 0x0cc0, 0xc82f, 0x0cff, 0xc82f, 0x21, 0 - .dw 0x0d40, 0xc82f, 0x0d7f, 0xc82f, 0x21, 0 - .dw 0x0dc0, 0xc82f, 0x0dff, 0xc82f, 0x21, 0 - .dw 0x0e40, 0xc82f, 0x0e7f, 0xc82f, 0x21, 0 - .dw 0x0ec0, 0xc82f, 0x0eff, 0xc82f, 0x21, 0 - .dw 0x0f40, 0xc82f, 0x0f7f, 0xc82f, 0x21, 0 - .dw 0x0fc0, 0xc82f, 0x0fff, 0xc82f, 0x21, 0 - .dw 0x1040, 0xc82f, 0x107f, 0xc82f, 0x21, 0 - .dw 0x10c0, 0xc82f, 0x10ff, 0xc82f, 0x21, 0 - .dw 0x1140, 0xc82f, 0x117f, 0xc82f, 0x21, 0 - .dw 0x11c0, 0xc82f, 0x11ff, 0xc82f, 0x21, 0 - .dw 0x1240, 0xc82f, 0x127f, 0xc82f, 0x21, 0 - .dw 0x12c0, 0xc82f, 0x12ff, 0xc82f, 0x21, 0 - .dw 0x1340, 0xc82f, 0x137f, 0xc82f, 0x21, 0 - .dw 0x13c0, 0xc82f, 0x13ff, 0xc82f, 0x21, 0 - .dw 0x1440, 0xc82f, 0x147f, 0xc82f, 0x21, 0 - .dw 0x14c0, 0xc82f, 0x14ff, 0xc82f, 0x21, 0 - .dw 0x1540, 0xc82f, 0x157f, 0xc82f, 0x21, 0 - .dw 0x15c0, 0xc82f, 0x15ff, 0xc82f, 0x21, 0 - .dw 0x1640, 0xc82f, 0x167f, 0xc82f, 0x21, 0 - .dw 0x16c0, 0xc82f, 0x16ff, 0xc82f, 0x21, 0 - .dw 0x1740, 0xc82f, 0x177f, 0xc82f, 0x21, 0 - .dw 0x17c0, 0xc82f, 0x17ff, 0xc82f, 0x21, 0 - .dw 0x1840, 0xc82f, 0x187f, 0xc82f, 0x21, 0 - .dw 0x18c0, 0xc82f, 0x18ff, 0xc82f, 0x21, 0 - .dw 0x1940, 0xc82f, 0x197f, 0xc82f, 0x21, 0 - .dw 0x19c0, 0xc82f, 0x1fff, 0xc82f, 0x21, 0 - .dw 0x2040, 0xc82f, 0x207f, 0xc82f, 0x21, 0 - .dw 0x20c0, 0xc82f, 0x20ff, 0xc82f, 0x21, 0 - .dw 0x2140, 0xc82f, 0x217f, 0xc82f, 0x21, 0 - .dw 0x21c0, 0xc82f, 0x21ff, 0xc82f, 0x21, 0 - .dw 0x2240, 0xc82f, 0x227f, 0xc82f, 0x21, 0 - .dw 0x22c0, 0xc82f, 0x22ff, 0xc82f, 0x21, 0 - .dw 0x2340, 0xc82f, 0x237f, 0xc82f, 0x21, 0 - .dw 0x23c0, 0xc82f, 0x23ff, 0xc82f, 0x21, 0 - .dw 0x2440, 0xc82f, 0x247f, 0xc82f, 0x21, 0 - .dw 0x24c0, 0xc82f, 0x24ff, 0xc82f, 0x21, 0 - .dw 0x2540, 0xc82f, 0x257f, 0xc82f, 0x21, 0 - .dw 0x25c0, 0xc82f, 0x25ff, 0xc82f, 0x21, 0 - .dw 0x2640, 0xc82f, 0x267f, 0xc82f, 0x21, 0 - .dw 0x26c0, 0xc82f, 0x26ff, 0xc82f, 0x21, 0 - .dw 0x2740, 0xc82f, 0x277f, 0xc82f, 0x21, 0 - .dw 0x27c0, 0xc82f, 0x27ff, 0xc82f, 0x21, 0 - .dw 0x2840, 0xc82f, 0x287f, 0xc82f, 0x21, 0 - .dw 0x28c0, 0xc82f, 0x28ff, 0xc82f, 0x21, 0 - .dw 0x2940, 0xc82f, 0x297f, 0xc82f, 0x21, 0 - .dw 0x29c0, 0xc82f, 0x29ff, 0xc82f, 0x21, 0 - .dw 0x2a40, 0xc82f, 0x2a7f, 0xc82f, 0x21, 0 - .dw 0x2ac0, 0xc82f, 0x2aff, 0xc82f, 0x21, 0 - .dw 0x2b40, 0xc82f, 0x2b7f, 0xc82f, 0x21, 0 - .dw 0x2bc0, 0xc82f, 0x2bff, 0xc82f, 0x21, 0 - .dw 0x2c40, 0xc82f, 0x2c7f, 0xc82f, 0x21, 0 - .dw 0x2cc0, 0xc82f, 0x2cff, 0xc82f, 0x21, 0 - .dw 0x2d40, 0xc82f, 0x2d7f, 0xc82f, 0x21, 0 - .dw 0x2dc0, 0xc82f, 0x2dff, 0xc82f, 0x21, 0 - .dw 0x2e40, 0xc82f, 0x2e7f, 0xc82f, 0x21, 0 - .dw 0x2ec0, 0xc82f, 0x2eff, 0xc82f, 0x21, 0 - .dw 0x2f40, 0xc82f, 0x2f7f, 0xc82f, 0x21, 0 - .dw 0x2fc0, 0xc82f, 0x2fff, 0xc82f, 0x21, 0 - .dw 0x3040, 0xc82f, 0x307f, 0xc82f, 0x21, 0 - .dw 0x30c0, 0xc82f, 0x30ff, 0xc82f, 0x21, 0 - .dw 0x3140, 0xc82f, 0x317f, 0xc82f, 0x21, 0 - .dw 0x31c0, 0xc82f, 0x31ff, 0xc82f, 0x21, 0 - .dw 0x3240, 0xc82f, 0x327f, 0xc82f, 0x21, 0 - .dw 0x32c0, 0xc82f, 0x32ff, 0xc82f, 0x21, 0 - .dw 0x3340, 0xc82f, 0x337f, 0xc82f, 0x21, 0 - .dw 0x33c0, 0xc82f, 0x33ff, 0xc82f, 0x21, 0 - .dw 0x3440, 0xc82f, 0x347f, 0xc82f, 0x21, 0 - .dw 0x34c0, 0xc82f, 0x34ff, 0xc82f, 0x21, 0 - .dw 0x3540, 0xc82f, 0x357f, 0xc82f, 0x21, 0 - .dw 0x35c0, 0xc82f, 0x35ff, 0xc82f, 0x21, 0 - .dw 0x3640, 0xc82f, 0x367f, 0xc82f, 0x21, 0 - .dw 0x36c0, 0xc82f, 0x36ff, 0xc82f, 0x21, 0 - .dw 0x3740, 0xc82f, 0x377f, 0xc82f, 0x21, 0 - .dw 0x37c0, 0xc82f, 0x37ff, 0xc82f, 0x21, 0 - .dw 0x3840, 0xc82f, 0x387f, 0xc82f, 0x21, 0 - .dw 0x38c0, 0xc82f, 0x38ff, 0xc82f, 0x21, 0 - .dw 0x3940, 0xc82f, 0x397f, 0xc82f, 0x21, 0 - .dw 0x39c0, 0xc82f, 0x1fff, 0xc830, 0x21, 0 - .dw 0x3a00, 0xc830, 0x5fff, 0xc830, 0x21, 0 - .dw 0x7a00, 0xc830, 0x9fff, 0xc830, 0x21, 0 - .dw 0xba00, 0xc830, 0xdfff, 0xc830, 0x21, 0 - .dw 0xfa00, 0xc830, 0x1fff, 0xc831, 0x21, 0 - .dw 0x3a00, 0xc831, 0x5fff, 0xc831, 0x21, 0 - .dw 0x7a00, 0xc831, 0x9fff, 0xc831, 0x21, 0 - .dw 0xba00, 0xc831, 0xdfff, 0xc831, 0x21, 0 - .dw 0xfa00, 0xc831, 0x1fff, 0xc832, 0x21, 0 - .dw 0x3a00, 0xc832, 0x5fff, 0xc832, 0x21, 0 - .dw 0x7a00, 0xc832, 0x9fff, 0xc832, 0x21, 0 - .dw 0xba00, 0xc832, 0xdfff, 0xc832, 0x21, 0 - .dw 0xfa00, 0xc832, 0xffff, 0xc833, 0x21, 0 - .dw 0x1a00, 0xc834, 0x1fff, 0xc834, 0x21, 0 - .dw 0x3a00, 0xc834, 0x3fff, 0xc834, 0x21, 0 - .dw 0x5a00, 0xc834, 0x5fff, 0xc834, 0x21, 0 - .dw 0x7a00, 0xc834, 0x7fff, 0xc834, 0x21, 0 - .dw 0x9a00, 0xc834, 0x9fff, 0xc834, 0x21, 0 - .dw 0xba00, 0xc834, 0xbfff, 0xc834, 0x21, 0 - .dw 0xda00, 0xc834, 0xdfff, 0xc834, 0x21, 0 - .dw 0xfa00, 0xc834, 0xffff, 0xc834, 0x21, 0 - .dw 0x1a00, 0xc835, 0x1fff, 0xc835, 0x21, 0 - .dw 0x3a00, 0xc835, 0x3fff, 0xc835, 0x21, 0 - .dw 0x5a00, 0xc835, 0x5fff, 0xc835, 0x21, 0 - .dw 0x7a00, 0xc835, 0x7fff, 0xc835, 0x21, 0 - .dw 0x9a00, 0xc835, 0x9fff, 0xc835, 0x21, 0 - .dw 0xba00, 0xc835, 0xbfff, 0xc835, 0x21, 0 - .dw 0xda00, 0xc835, 0xdfff, 0xc835, 0x21, 0 - .dw 0xfa00, 0xc835, 0xffff, 0xc835, 0x21, 0 - .dw 0x1a00, 0xc836, 0x1fff, 0xc836, 0x21, 0 - .dw 0x3a00, 0xc836, 0x3fff, 0xc836, 0x21, 0 - .dw 0x5a00, 0xc836, 0x5fff, 0xc836, 0x21, 0 - .dw 0x7a00, 0xc836, 0x7fff, 0xc836, 0x21, 0 - .dw 0x9a00, 0xc836, 0x9fff, 0xc836, 0x21, 0 - .dw 0xba00, 0xc836, 0xbfff, 0xc836, 0x21, 0 - .dw 0xda00, 0xc836, 0xdfff, 0xc836, 0x21, 0 - .dw 0xfa00, 0xc836, 0xffff, 0xc836, 0x21, 0 - .dw 0x1a00, 0xc837, 0x1fff, 0xc837, 0x21, 0 - .dw 0x3a00, 0xc837, 0x1fff, 0xc838, 0x21, 0 - .dw 0x2040, 0xc838, 0x207f, 0xc838, 0x21, 0 - .dw 0x20c0, 0xc838, 0x20ff, 0xc838, 0x21, 0 - .dw 0x2140, 0xc838, 0x217f, 0xc838, 0x21, 0 - .dw 0x21c0, 0xc838, 0x21ff, 0xc838, 0x21, 0 - .dw 0x2240, 0xc838, 0x227f, 0xc838, 0x21, 0 - .dw 0x22c0, 0xc838, 0x22ff, 0xc838, 0x21, 0 - .dw 0x2340, 0xc838, 0x237f, 0xc838, 0x21, 0 - .dw 0x23c0, 0xc838, 0x23ff, 0xc838, 0x21, 0 - .dw 0x2440, 0xc838, 0x247f, 0xc838, 0x21, 0 - .dw 0x24c0, 0xc838, 0x24ff, 0xc838, 0x21, 0 - .dw 0x2540, 0xc838, 0x257f, 0xc838, 0x21, 0 - .dw 0x25c0, 0xc838, 0x25ff, 0xc838, 0x21, 0 - .dw 0x2640, 0xc838, 0x267f, 0xc838, 0x21, 0 - .dw 0x26c0, 0xc838, 0x26ff, 0xc838, 0x21, 0 - .dw 0x2740, 0xc838, 0x277f, 0xc838, 0x21, 0 - .dw 0x27c0, 0xc838, 0x27ff, 0xc838, 0x21, 0 - .dw 0x2840, 0xc838, 0x287f, 0xc838, 0x21, 0 - .dw 0x28c0, 0xc838, 0x28ff, 0xc838, 0x21, 0 - .dw 0x2940, 0xc838, 0x297f, 0xc838, 0x21, 0 - .dw 0x29c0, 0xc838, 0x29ff, 0xc838, 0x21, 0 - .dw 0x2a40, 0xc838, 0x2a7f, 0xc838, 0x21, 0 - .dw 0x2ac0, 0xc838, 0x2aff, 0xc838, 0x21, 0 - .dw 0x2b40, 0xc838, 0x2b7f, 0xc838, 0x21, 0 - .dw 0x2bc0, 0xc838, 0x2bff, 0xc838, 0x21, 0 - .dw 0x2c40, 0xc838, 0x2c7f, 0xc838, 0x21, 0 - .dw 0x2cc0, 0xc838, 0x2cff, 0xc838, 0x21, 0 - .dw 0x2d40, 0xc838, 0x2d7f, 0xc838, 0x21, 0 - .dw 0x2dc0, 0xc838, 0x2dff, 0xc838, 0x21, 0 - .dw 0x2e40, 0xc838, 0x2e7f, 0xc838, 0x21, 0 - .dw 0x2ec0, 0xc838, 0x2eff, 0xc838, 0x21, 0 - .dw 0x2f40, 0xc838, 0x2f7f, 0xc838, 0x21, 0 - .dw 0x2fc0, 0xc838, 0x2fff, 0xc838, 0x21, 0 - .dw 0x3040, 0xc838, 0x307f, 0xc838, 0x21, 0 - .dw 0x30c0, 0xc838, 0x30ff, 0xc838, 0x21, 0 - .dw 0x3140, 0xc838, 0x317f, 0xc838, 0x21, 0 - .dw 0x31c0, 0xc838, 0x31ff, 0xc838, 0x21, 0 - .dw 0x3240, 0xc838, 0x327f, 0xc838, 0x21, 0 - .dw 0x32c0, 0xc838, 0x32ff, 0xc838, 0x21, 0 - .dw 0x3340, 0xc838, 0x337f, 0xc838, 0x21, 0 - .dw 0x33c0, 0xc838, 0x33ff, 0xc838, 0x21, 0 - .dw 0x3440, 0xc838, 0x347f, 0xc838, 0x21, 0 - .dw 0x34c0, 0xc838, 0x34ff, 0xc838, 0x21, 0 - .dw 0x3540, 0xc838, 0x357f, 0xc838, 0x21, 0 - .dw 0x35c0, 0xc838, 0x35ff, 0xc838, 0x21, 0 - .dw 0x3640, 0xc838, 0x367f, 0xc838, 0x21, 0 - .dw 0x36c0, 0xc838, 0x36ff, 0xc838, 0x21, 0 - .dw 0x3740, 0xc838, 0x377f, 0xc838, 0x21, 0 - .dw 0x37c0, 0xc838, 0x37ff, 0xc838, 0x21, 0 - .dw 0x3840, 0xc838, 0x387f, 0xc838, 0x21, 0 - .dw 0x38c0, 0xc838, 0x38ff, 0xc838, 0x21, 0 - .dw 0x3940, 0xc838, 0x397f, 0xc838, 0x21, 0 - .dw 0x39c0, 0xc838, 0x5fff, 0xc838, 0x21, 0 - .dw 0x6040, 0xc838, 0x607f, 0xc838, 0x21, 0 - .dw 0x60c0, 0xc838, 0x60ff, 0xc838, 0x21, 0 - .dw 0x6140, 0xc838, 0x617f, 0xc838, 0x21, 0 - .dw 0x61c0, 0xc838, 0x61ff, 0xc838, 0x21, 0 - .dw 0x6240, 0xc838, 0x627f, 0xc838, 0x21, 0 - .dw 0x62c0, 0xc838, 0x62ff, 0xc838, 0x21, 0 - .dw 0x6340, 0xc838, 0x637f, 0xc838, 0x21, 0 - .dw 0x63c0, 0xc838, 0x63ff, 0xc838, 0x21, 0 - .dw 0x6440, 0xc838, 0x647f, 0xc838, 0x21, 0 - .dw 0x64c0, 0xc838, 0x64ff, 0xc838, 0x21, 0 - .dw 0x6540, 0xc838, 0x657f, 0xc838, 0x21, 0 - .dw 0x65c0, 0xc838, 0x65ff, 0xc838, 0x21, 0 - .dw 0x6640, 0xc838, 0x667f, 0xc838, 0x21, 0 - .dw 0x66c0, 0xc838, 0x66ff, 0xc838, 0x21, 0 - .dw 0x6740, 0xc838, 0x677f, 0xc838, 0x21, 0 - .dw 0x67c0, 0xc838, 0x67ff, 0xc838, 0x21, 0 - .dw 0x6840, 0xc838, 0x687f, 0xc838, 0x21, 0 - .dw 0x68c0, 0xc838, 0x68ff, 0xc838, 0x21, 0 - .dw 0x6940, 0xc838, 0x697f, 0xc838, 0x21, 0 - .dw 0x69c0, 0xc838, 0x69ff, 0xc838, 0x21, 0 - .dw 0x6a40, 0xc838, 0x6a7f, 0xc838, 0x21, 0 - .dw 0x6ac0, 0xc838, 0x6aff, 0xc838, 0x21, 0 - .dw 0x6b40, 0xc838, 0x6b7f, 0xc838, 0x21, 0 - .dw 0x6bc0, 0xc838, 0x6bff, 0xc838, 0x21, 0 - .dw 0x6c40, 0xc838, 0x6c7f, 0xc838, 0x21, 0 - .dw 0x6cc0, 0xc838, 0x6cff, 0xc838, 0x21, 0 - .dw 0x6d40, 0xc838, 0x6d7f, 0xc838, 0x21, 0 - .dw 0x6dc0, 0xc838, 0x6dff, 0xc838, 0x21, 0 - .dw 0x6e40, 0xc838, 0x6e7f, 0xc838, 0x21, 0 - .dw 0x6ec0, 0xc838, 0x6eff, 0xc838, 0x21, 0 - .dw 0x6f40, 0xc838, 0x6f7f, 0xc838, 0x21, 0 - .dw 0x6fc0, 0xc838, 0x6fff, 0xc838, 0x21, 0 - .dw 0x7040, 0xc838, 0x707f, 0xc838, 0x21, 0 - .dw 0x70c0, 0xc838, 0x70ff, 0xc838, 0x21, 0 - .dw 0x7140, 0xc838, 0x717f, 0xc838, 0x21, 0 - .dw 0x71c0, 0xc838, 0x71ff, 0xc838, 0x21, 0 - .dw 0x7240, 0xc838, 0x727f, 0xc838, 0x21, 0 - .dw 0x72c0, 0xc838, 0x72ff, 0xc838, 0x21, 0 - .dw 0x7340, 0xc838, 0x737f, 0xc838, 0x21, 0 - .dw 0x73c0, 0xc838, 0x73ff, 0xc838, 0x21, 0 - .dw 0x7440, 0xc838, 0x747f, 0xc838, 0x21, 0 - .dw 0x74c0, 0xc838, 0x74ff, 0xc838, 0x21, 0 - .dw 0x7540, 0xc838, 0x757f, 0xc838, 0x21, 0 - .dw 0x75c0, 0xc838, 0x75ff, 0xc838, 0x21, 0 - .dw 0x7640, 0xc838, 0x767f, 0xc838, 0x21, 0 - .dw 0x76c0, 0xc838, 0x76ff, 0xc838, 0x21, 0 - .dw 0x7740, 0xc838, 0x777f, 0xc838, 0x21, 0 - .dw 0x77c0, 0xc838, 0x77ff, 0xc838, 0x21, 0 - .dw 0x7840, 0xc838, 0x787f, 0xc838, 0x21, 0 - .dw 0x78c0, 0xc838, 0x78ff, 0xc838, 0x21, 0 - .dw 0x7940, 0xc838, 0x797f, 0xc838, 0x21, 0 - .dw 0x79c0, 0xc838, 0x9fff, 0xc838, 0x21, 0 - .dw 0xa040, 0xc838, 0xa07f, 0xc838, 0x21, 0 - .dw 0xa0c0, 0xc838, 0xa0ff, 0xc838, 0x21, 0 - .dw 0xa140, 0xc838, 0xa17f, 0xc838, 0x21, 0 - .dw 0xa1c0, 0xc838, 0xa1ff, 0xc838, 0x21, 0 - .dw 0xa240, 0xc838, 0xa27f, 0xc838, 0x21, 0 - .dw 0xa2c0, 0xc838, 0xa2ff, 0xc838, 0x21, 0 - .dw 0xa340, 0xc838, 0xa37f, 0xc838, 0x21, 0 - .dw 0xa3c0, 0xc838, 0xa3ff, 0xc838, 0x21, 0 - .dw 0xa440, 0xc838, 0xa47f, 0xc838, 0x21, 0 - .dw 0xa4c0, 0xc838, 0xa4ff, 0xc838, 0x21, 0 - .dw 0xa540, 0xc838, 0xa57f, 0xc838, 0x21, 0 - .dw 0xa5c0, 0xc838, 0xa5ff, 0xc838, 0x21, 0 - .dw 0xa640, 0xc838, 0xa67f, 0xc838, 0x21, 0 - .dw 0xa6c0, 0xc838, 0xa6ff, 0xc838, 0x21, 0 - .dw 0xa740, 0xc838, 0xa77f, 0xc838, 0x21, 0 - .dw 0xa7c0, 0xc838, 0xa7ff, 0xc838, 0x21, 0 - .dw 0xa840, 0xc838, 0xa87f, 0xc838, 0x21, 0 - .dw 0xa8c0, 0xc838, 0xa8ff, 0xc838, 0x21, 0 - .dw 0xa940, 0xc838, 0xa97f, 0xc838, 0x21, 0 - .dw 0xa9c0, 0xc838, 0xa9ff, 0xc838, 0x21, 0 - .dw 0xaa40, 0xc838, 0xaa7f, 0xc838, 0x21, 0 - .dw 0xaac0, 0xc838, 0xaaff, 0xc838, 0x21, 0 - .dw 0xab40, 0xc838, 0xab7f, 0xc838, 0x21, 0 - .dw 0xabc0, 0xc838, 0xabff, 0xc838, 0x21, 0 - .dw 0xac40, 0xc838, 0xac7f, 0xc838, 0x21, 0 - .dw 0xacc0, 0xc838, 0xacff, 0xc838, 0x21, 0 - .dw 0xad40, 0xc838, 0xad7f, 0xc838, 0x21, 0 - .dw 0xadc0, 0xc838, 0xadff, 0xc838, 0x21, 0 - .dw 0xae40, 0xc838, 0xae7f, 0xc838, 0x21, 0 - .dw 0xaec0, 0xc838, 0xaeff, 0xc838, 0x21, 0 - .dw 0xaf40, 0xc838, 0xaf7f, 0xc838, 0x21, 0 - .dw 0xafc0, 0xc838, 0xafff, 0xc838, 0x21, 0 - .dw 0xb040, 0xc838, 0xb07f, 0xc838, 0x21, 0 - .dw 0xb0c0, 0xc838, 0xb0ff, 0xc838, 0x21, 0 - .dw 0xb140, 0xc838, 0xb17f, 0xc838, 0x21, 0 - .dw 0xb1c0, 0xc838, 0xb1ff, 0xc838, 0x21, 0 - .dw 0xb240, 0xc838, 0xb27f, 0xc838, 0x21, 0 - .dw 0xb2c0, 0xc838, 0xb2ff, 0xc838, 0x21, 0 - .dw 0xb340, 0xc838, 0xb37f, 0xc838, 0x21, 0 - .dw 0xb3c0, 0xc838, 0xb3ff, 0xc838, 0x21, 0 - .dw 0xb440, 0xc838, 0xb47f, 0xc838, 0x21, 0 - .dw 0xb4c0, 0xc838, 0xb4ff, 0xc838, 0x21, 0 - .dw 0xb540, 0xc838, 0xb57f, 0xc838, 0x21, 0 - .dw 0xb5c0, 0xc838, 0xb5ff, 0xc838, 0x21, 0 - .dw 0xb640, 0xc838, 0xb67f, 0xc838, 0x21, 0 - .dw 0xb6c0, 0xc838, 0xb6ff, 0xc838, 0x21, 0 - .dw 0xb740, 0xc838, 0xb77f, 0xc838, 0x21, 0 - .dw 0xb7c0, 0xc838, 0xb7ff, 0xc838, 0x21, 0 - .dw 0xb840, 0xc838, 0xb87f, 0xc838, 0x21, 0 - .dw 0xb8c0, 0xc838, 0xb8ff, 0xc838, 0x21, 0 - .dw 0xb940, 0xc838, 0xb97f, 0xc838, 0x21, 0 - .dw 0xb9c0, 0xc838, 0xdfff, 0xc838, 0x21, 0 - .dw 0xe040, 0xc838, 0xe07f, 0xc838, 0x21, 0 - .dw 0xe0c0, 0xc838, 0xe0ff, 0xc838, 0x21, 0 - .dw 0xe140, 0xc838, 0xe17f, 0xc838, 0x21, 0 - .dw 0xe1c0, 0xc838, 0xe1ff, 0xc838, 0x21, 0 - .dw 0xe240, 0xc838, 0xe27f, 0xc838, 0x21, 0 - .dw 0xe2c0, 0xc838, 0xe2ff, 0xc838, 0x21, 0 - .dw 0xe340, 0xc838, 0xe37f, 0xc838, 0x21, 0 - .dw 0xe3c0, 0xc838, 0xe3ff, 0xc838, 0x21, 0 - .dw 0xe440, 0xc838, 0xe47f, 0xc838, 0x21, 0 - .dw 0xe4c0, 0xc838, 0xe4ff, 0xc838, 0x21, 0 - .dw 0xe540, 0xc838, 0xe57f, 0xc838, 0x21, 0 - .dw 0xe5c0, 0xc838, 0xe5ff, 0xc838, 0x21, 0 - .dw 0xe640, 0xc838, 0xe67f, 0xc838, 0x21, 0 - .dw 0xe6c0, 0xc838, 0xe6ff, 0xc838, 0x21, 0 - .dw 0xe740, 0xc838, 0xe77f, 0xc838, 0x21, 0 - .dw 0xe7c0, 0xc838, 0xe7ff, 0xc838, 0x21, 0 - .dw 0xe840, 0xc838, 0xe87f, 0xc838, 0x21, 0 - .dw 0xe8c0, 0xc838, 0xe8ff, 0xc838, 0x21, 0 - .dw 0xe940, 0xc838, 0xe97f, 0xc838, 0x21, 0 - .dw 0xe9c0, 0xc838, 0xe9ff, 0xc838, 0x21, 0 - .dw 0xea40, 0xc838, 0xea7f, 0xc838, 0x21, 0 - .dw 0xeac0, 0xc838, 0xeaff, 0xc838, 0x21, 0 - .dw 0xeb40, 0xc838, 0xeb7f, 0xc838, 0x21, 0 - .dw 0xebc0, 0xc838, 0xebff, 0xc838, 0x21, 0 - .dw 0xec40, 0xc838, 0xec7f, 0xc838, 0x21, 0 - .dw 0xecc0, 0xc838, 0xecff, 0xc838, 0x21, 0 - .dw 0xed40, 0xc838, 0xed7f, 0xc838, 0x21, 0 - .dw 0xedc0, 0xc838, 0xedff, 0xc838, 0x21, 0 - .dw 0xee40, 0xc838, 0xee7f, 0xc838, 0x21, 0 - .dw 0xeec0, 0xc838, 0xeeff, 0xc838, 0x21, 0 - .dw 0xef40, 0xc838, 0xef7f, 0xc838, 0x21, 0 - .dw 0xefc0, 0xc838, 0xefff, 0xc838, 0x21, 0 - .dw 0xf040, 0xc838, 0xf07f, 0xc838, 0x21, 0 - .dw 0xf0c0, 0xc838, 0xf0ff, 0xc838, 0x21, 0 - .dw 0xf140, 0xc838, 0xf17f, 0xc838, 0x21, 0 - .dw 0xf1c0, 0xc838, 0xf1ff, 0xc838, 0x21, 0 - .dw 0xf240, 0xc838, 0xf27f, 0xc838, 0x21, 0 - .dw 0xf2c0, 0xc838, 0xf2ff, 0xc838, 0x21, 0 - .dw 0xf340, 0xc838, 0xf37f, 0xc838, 0x21, 0 - .dw 0xf3c0, 0xc838, 0xf3ff, 0xc838, 0x21, 0 - .dw 0xf440, 0xc838, 0xf47f, 0xc838, 0x21, 0 - .dw 0xf4c0, 0xc838, 0xf4ff, 0xc838, 0x21, 0 - .dw 0xf540, 0xc838, 0xf57f, 0xc838, 0x21, 0 - .dw 0xf5c0, 0xc838, 0xf5ff, 0xc838, 0x21, 0 - .dw 0xf640, 0xc838, 0xf67f, 0xc838, 0x21, 0 - .dw 0xf6c0, 0xc838, 0xf6ff, 0xc838, 0x21, 0 - .dw 0xf740, 0xc838, 0xf77f, 0xc838, 0x21, 0 - .dw 0xf7c0, 0xc838, 0xf7ff, 0xc838, 0x21, 0 - .dw 0xf840, 0xc838, 0xf87f, 0xc838, 0x21, 0 - .dw 0xf8c0, 0xc838, 0xf8ff, 0xc838, 0x21, 0 - .dw 0xf940, 0xc838, 0xf97f, 0xc838, 0x21, 0 - .dw 0xf9c0, 0xc838, 0x1fff, 0xc839, 0x21, 0 - .dw 0x2040, 0xc839, 0x207f, 0xc839, 0x21, 0 - .dw 0x20c0, 0xc839, 0x20ff, 0xc839, 0x21, 0 - .dw 0x2140, 0xc839, 0x217f, 0xc839, 0x21, 0 - .dw 0x21c0, 0xc839, 0x21ff, 0xc839, 0x21, 0 - .dw 0x2240, 0xc839, 0x227f, 0xc839, 0x21, 0 - .dw 0x22c0, 0xc839, 0x22ff, 0xc839, 0x21, 0 - .dw 0x2340, 0xc839, 0x237f, 0xc839, 0x21, 0 - .dw 0x23c0, 0xc839, 0x23ff, 0xc839, 0x21, 0 - .dw 0x2440, 0xc839, 0x247f, 0xc839, 0x21, 0 - .dw 0x24c0, 0xc839, 0x24ff, 0xc839, 0x21, 0 - .dw 0x2540, 0xc839, 0x257f, 0xc839, 0x21, 0 - .dw 0x25c0, 0xc839, 0x25ff, 0xc839, 0x21, 0 - .dw 0x2640, 0xc839, 0x267f, 0xc839, 0x21, 0 - .dw 0x26c0, 0xc839, 0x26ff, 0xc839, 0x21, 0 - .dw 0x2740, 0xc839, 0x277f, 0xc839, 0x21, 0 - .dw 0x27c0, 0xc839, 0x27ff, 0xc839, 0x21, 0 - .dw 0x2840, 0xc839, 0x287f, 0xc839, 0x21, 0 - .dw 0x28c0, 0xc839, 0x28ff, 0xc839, 0x21, 0 - .dw 0x2940, 0xc839, 0x297f, 0xc839, 0x21, 0 - .dw 0x29c0, 0xc839, 0x29ff, 0xc839, 0x21, 0 - .dw 0x2a40, 0xc839, 0x2a7f, 0xc839, 0x21, 0 - .dw 0x2ac0, 0xc839, 0x2aff, 0xc839, 0x21, 0 - .dw 0x2b40, 0xc839, 0x2b7f, 0xc839, 0x21, 0 - .dw 0x2bc0, 0xc839, 0x2bff, 0xc839, 0x21, 0 - .dw 0x2c40, 0xc839, 0x2c7f, 0xc839, 0x21, 0 - .dw 0x2cc0, 0xc839, 0x2cff, 0xc839, 0x21, 0 - .dw 0x2d40, 0xc839, 0x2d7f, 0xc839, 0x21, 0 - .dw 0x2dc0, 0xc839, 0x2dff, 0xc839, 0x21, 0 - .dw 0x2e40, 0xc839, 0x2e7f, 0xc839, 0x21, 0 - .dw 0x2ec0, 0xc839, 0x2eff, 0xc839, 0x21, 0 - .dw 0x2f40, 0xc839, 0x2f7f, 0xc839, 0x21, 0 - .dw 0x2fc0, 0xc839, 0x2fff, 0xc839, 0x21, 0 - .dw 0x3040, 0xc839, 0x307f, 0xc839, 0x21, 0 - .dw 0x30c0, 0xc839, 0x30ff, 0xc839, 0x21, 0 - .dw 0x3140, 0xc839, 0x317f, 0xc839, 0x21, 0 - .dw 0x31c0, 0xc839, 0x31ff, 0xc839, 0x21, 0 - .dw 0x3240, 0xc839, 0x327f, 0xc839, 0x21, 0 - .dw 0x32c0, 0xc839, 0x32ff, 0xc839, 0x21, 0 - .dw 0x3340, 0xc839, 0x337f, 0xc839, 0x21, 0 - .dw 0x33c0, 0xc839, 0x33ff, 0xc839, 0x21, 0 - .dw 0x3440, 0xc839, 0x347f, 0xc839, 0x21, 0 - .dw 0x34c0, 0xc839, 0x34ff, 0xc839, 0x21, 0 - .dw 0x3540, 0xc839, 0x357f, 0xc839, 0x21, 0 - .dw 0x35c0, 0xc839, 0x35ff, 0xc839, 0x21, 0 - .dw 0x3640, 0xc839, 0x367f, 0xc839, 0x21, 0 - .dw 0x36c0, 0xc839, 0x36ff, 0xc839, 0x21, 0 - .dw 0x3740, 0xc839, 0x377f, 0xc839, 0x21, 0 - .dw 0x37c0, 0xc839, 0x37ff, 0xc839, 0x21, 0 - .dw 0x3840, 0xc839, 0x387f, 0xc839, 0x21, 0 - .dw 0x38c0, 0xc839, 0x38ff, 0xc839, 0x21, 0 - .dw 0x3940, 0xc839, 0x397f, 0xc839, 0x21, 0 - .dw 0x39c0, 0xc839, 0x5fff, 0xc839, 0x21, 0 - .dw 0x6040, 0xc839, 0x607f, 0xc839, 0x21, 0 - .dw 0x60c0, 0xc839, 0x60ff, 0xc839, 0x21, 0 - .dw 0x6140, 0xc839, 0x617f, 0xc839, 0x21, 0 - .dw 0x61c0, 0xc839, 0x61ff, 0xc839, 0x21, 0 - .dw 0x6240, 0xc839, 0x627f, 0xc839, 0x21, 0 - .dw 0x62c0, 0xc839, 0x62ff, 0xc839, 0x21, 0 - .dw 0x6340, 0xc839, 0x637f, 0xc839, 0x21, 0 - .dw 0x63c0, 0xc839, 0x63ff, 0xc839, 0x21, 0 - .dw 0x6440, 0xc839, 0x647f, 0xc839, 0x21, 0 - .dw 0x64c0, 0xc839, 0x64ff, 0xc839, 0x21, 0 - .dw 0x6540, 0xc839, 0x657f, 0xc839, 0x21, 0 - .dw 0x65c0, 0xc839, 0x65ff, 0xc839, 0x21, 0 - .dw 0x6640, 0xc839, 0x667f, 0xc839, 0x21, 0 - .dw 0x66c0, 0xc839, 0x66ff, 0xc839, 0x21, 0 - .dw 0x6740, 0xc839, 0x677f, 0xc839, 0x21, 0 - .dw 0x67c0, 0xc839, 0x67ff, 0xc839, 0x21, 0 - .dw 0x6840, 0xc839, 0x687f, 0xc839, 0x21, 0 - .dw 0x68c0, 0xc839, 0x68ff, 0xc839, 0x21, 0 - .dw 0x6940, 0xc839, 0x697f, 0xc839, 0x21, 0 - .dw 0x69c0, 0xc839, 0x69ff, 0xc839, 0x21, 0 - .dw 0x6a40, 0xc839, 0x6a7f, 0xc839, 0x21, 0 - .dw 0x6ac0, 0xc839, 0x6aff, 0xc839, 0x21, 0 - .dw 0x6b40, 0xc839, 0x6b7f, 0xc839, 0x21, 0 - .dw 0x6bc0, 0xc839, 0x6bff, 0xc839, 0x21, 0 - .dw 0x6c40, 0xc839, 0x6c7f, 0xc839, 0x21, 0 - .dw 0x6cc0, 0xc839, 0x6cff, 0xc839, 0x21, 0 - .dw 0x6d40, 0xc839, 0x6d7f, 0xc839, 0x21, 0 - .dw 0x6dc0, 0xc839, 0x6dff, 0xc839, 0x21, 0 - .dw 0x6e40, 0xc839, 0x6e7f, 0xc839, 0x21, 0 - .dw 0x6ec0, 0xc839, 0x6eff, 0xc839, 0x21, 0 - .dw 0x6f40, 0xc839, 0x6f7f, 0xc839, 0x21, 0 - .dw 0x6fc0, 0xc839, 0x6fff, 0xc839, 0x21, 0 - .dw 0x7040, 0xc839, 0x707f, 0xc839, 0x21, 0 - .dw 0x70c0, 0xc839, 0x70ff, 0xc839, 0x21, 0 - .dw 0x7140, 0xc839, 0x717f, 0xc839, 0x21, 0 - .dw 0x71c0, 0xc839, 0x71ff, 0xc839, 0x21, 0 - .dw 0x7240, 0xc839, 0x727f, 0xc839, 0x21, 0 - .dw 0x72c0, 0xc839, 0x72ff, 0xc839, 0x21, 0 - .dw 0x7340, 0xc839, 0x737f, 0xc839, 0x21, 0 - .dw 0x73c0, 0xc839, 0x73ff, 0xc839, 0x21, 0 - .dw 0x7440, 0xc839, 0x747f, 0xc839, 0x21, 0 - .dw 0x74c0, 0xc839, 0x74ff, 0xc839, 0x21, 0 - .dw 0x7540, 0xc839, 0x757f, 0xc839, 0x21, 0 - .dw 0x75c0, 0xc839, 0x75ff, 0xc839, 0x21, 0 - .dw 0x7640, 0xc839, 0x767f, 0xc839, 0x21, 0 - .dw 0x76c0, 0xc839, 0x76ff, 0xc839, 0x21, 0 - .dw 0x7740, 0xc839, 0x777f, 0xc839, 0x21, 0 - .dw 0x77c0, 0xc839, 0x77ff, 0xc839, 0x21, 0 - .dw 0x7840, 0xc839, 0x787f, 0xc839, 0x21, 0 - .dw 0x78c0, 0xc839, 0x78ff, 0xc839, 0x21, 0 - .dw 0x7940, 0xc839, 0x797f, 0xc839, 0x21, 0 - .dw 0x79c0, 0xc839, 0x9fff, 0xc839, 0x21, 0 - .dw 0xa040, 0xc839, 0xa07f, 0xc839, 0x21, 0 - .dw 0xa0c0, 0xc839, 0xa0ff, 0xc839, 0x21, 0 - .dw 0xa140, 0xc839, 0xa17f, 0xc839, 0x21, 0 - .dw 0xa1c0, 0xc839, 0xa1ff, 0xc839, 0x21, 0 - .dw 0xa240, 0xc839, 0xa27f, 0xc839, 0x21, 0 - .dw 0xa2c0, 0xc839, 0xa2ff, 0xc839, 0x21, 0 - .dw 0xa340, 0xc839, 0xa37f, 0xc839, 0x21, 0 - .dw 0xa3c0, 0xc839, 0xa3ff, 0xc839, 0x21, 0 - .dw 0xa440, 0xc839, 0xa47f, 0xc839, 0x21, 0 - .dw 0xa4c0, 0xc839, 0xa4ff, 0xc839, 0x21, 0 - .dw 0xa540, 0xc839, 0xa57f, 0xc839, 0x21, 0 - .dw 0xa5c0, 0xc839, 0xa5ff, 0xc839, 0x21, 0 - .dw 0xa640, 0xc839, 0xa67f, 0xc839, 0x21, 0 - .dw 0xa6c0, 0xc839, 0xa6ff, 0xc839, 0x21, 0 - .dw 0xa740, 0xc839, 0xa77f, 0xc839, 0x21, 0 - .dw 0xa7c0, 0xc839, 0xa7ff, 0xc839, 0x21, 0 - .dw 0xa840, 0xc839, 0xa87f, 0xc839, 0x21, 0 - .dw 0xa8c0, 0xc839, 0xa8ff, 0xc839, 0x21, 0 - .dw 0xa940, 0xc839, 0xa97f, 0xc839, 0x21, 0 - .dw 0xa9c0, 0xc839, 0xa9ff, 0xc839, 0x21, 0 - .dw 0xaa40, 0xc839, 0xaa7f, 0xc839, 0x21, 0 - .dw 0xaac0, 0xc839, 0xaaff, 0xc839, 0x21, 0 - .dw 0xab40, 0xc839, 0xab7f, 0xc839, 0x21, 0 - .dw 0xabc0, 0xc839, 0xabff, 0xc839, 0x21, 0 - .dw 0xac40, 0xc839, 0xac7f, 0xc839, 0x21, 0 - .dw 0xacc0, 0xc839, 0xacff, 0xc839, 0x21, 0 - .dw 0xad40, 0xc839, 0xad7f, 0xc839, 0x21, 0 - .dw 0xadc0, 0xc839, 0xadff, 0xc839, 0x21, 0 - .dw 0xae40, 0xc839, 0xae7f, 0xc839, 0x21, 0 - .dw 0xaec0, 0xc839, 0xaeff, 0xc839, 0x21, 0 - .dw 0xaf40, 0xc839, 0xaf7f, 0xc839, 0x21, 0 - .dw 0xafc0, 0xc839, 0xafff, 0xc839, 0x21, 0 - .dw 0xb040, 0xc839, 0xb07f, 0xc839, 0x21, 0 - .dw 0xb0c0, 0xc839, 0xb0ff, 0xc839, 0x21, 0 - .dw 0xb140, 0xc839, 0xb17f, 0xc839, 0x21, 0 - .dw 0xb1c0, 0xc839, 0xb1ff, 0xc839, 0x21, 0 - .dw 0xb240, 0xc839, 0xb27f, 0xc839, 0x21, 0 - .dw 0xb2c0, 0xc839, 0xb2ff, 0xc839, 0x21, 0 - .dw 0xb340, 0xc839, 0xb37f, 0xc839, 0x21, 0 - .dw 0xb3c0, 0xc839, 0xb3ff, 0xc839, 0x21, 0 - .dw 0xb440, 0xc839, 0xb47f, 0xc839, 0x21, 0 - .dw 0xb4c0, 0xc839, 0xb4ff, 0xc839, 0x21, 0 - .dw 0xb540, 0xc839, 0xb57f, 0xc839, 0x21, 0 - .dw 0xb5c0, 0xc839, 0xb5ff, 0xc839, 0x21, 0 - .dw 0xb640, 0xc839, 0xb67f, 0xc839, 0x21, 0 - .dw 0xb6c0, 0xc839, 0xb6ff, 0xc839, 0x21, 0 - .dw 0xb740, 0xc839, 0xb77f, 0xc839, 0x21, 0 - .dw 0xb7c0, 0xc839, 0xb7ff, 0xc839, 0x21, 0 - .dw 0xb840, 0xc839, 0xb87f, 0xc839, 0x21, 0 - .dw 0xb8c0, 0xc839, 0xb8ff, 0xc839, 0x21, 0 - .dw 0xb940, 0xc839, 0xb97f, 0xc839, 0x21, 0 - .dw 0xb9c0, 0xc839, 0xdfff, 0xc839, 0x21, 0 - .dw 0xe040, 0xc839, 0xe07f, 0xc839, 0x21, 0 - .dw 0xe0c0, 0xc839, 0xe0ff, 0xc839, 0x21, 0 - .dw 0xe140, 0xc839, 0xe17f, 0xc839, 0x21, 0 - .dw 0xe1c0, 0xc839, 0xe1ff, 0xc839, 0x21, 0 - .dw 0xe240, 0xc839, 0xe27f, 0xc839, 0x21, 0 - .dw 0xe2c0, 0xc839, 0xe2ff, 0xc839, 0x21, 0 - .dw 0xe340, 0xc839, 0xe37f, 0xc839, 0x21, 0 - .dw 0xe3c0, 0xc839, 0xe3ff, 0xc839, 0x21, 0 - .dw 0xe440, 0xc839, 0xe47f, 0xc839, 0x21, 0 - .dw 0xe4c0, 0xc839, 0xe4ff, 0xc839, 0x21, 0 - .dw 0xe540, 0xc839, 0xe57f, 0xc839, 0x21, 0 - .dw 0xe5c0, 0xc839, 0xe5ff, 0xc839, 0x21, 0 - .dw 0xe640, 0xc839, 0xe67f, 0xc839, 0x21, 0 - .dw 0xe6c0, 0xc839, 0xe6ff, 0xc839, 0x21, 0 - .dw 0xe740, 0xc839, 0xe77f, 0xc839, 0x21, 0 - .dw 0xe7c0, 0xc839, 0xe7ff, 0xc839, 0x21, 0 - .dw 0xe840, 0xc839, 0xe87f, 0xc839, 0x21, 0 - .dw 0xe8c0, 0xc839, 0xe8ff, 0xc839, 0x21, 0 - .dw 0xe940, 0xc839, 0xe97f, 0xc839, 0x21, 0 - .dw 0xe9c0, 0xc839, 0xe9ff, 0xc839, 0x21, 0 - .dw 0xea40, 0xc839, 0xea7f, 0xc839, 0x21, 0 - .dw 0xeac0, 0xc839, 0xeaff, 0xc839, 0x21, 0 - .dw 0xeb40, 0xc839, 0xeb7f, 0xc839, 0x21, 0 - .dw 0xebc0, 0xc839, 0xebff, 0xc839, 0x21, 0 - .dw 0xec40, 0xc839, 0xec7f, 0xc839, 0x21, 0 - .dw 0xecc0, 0xc839, 0xecff, 0xc839, 0x21, 0 - .dw 0xed40, 0xc839, 0xed7f, 0xc839, 0x21, 0 - .dw 0xedc0, 0xc839, 0xedff, 0xc839, 0x21, 0 - .dw 0xee40, 0xc839, 0xee7f, 0xc839, 0x21, 0 - .dw 0xeec0, 0xc839, 0xeeff, 0xc839, 0x21, 0 - .dw 0xef40, 0xc839, 0xef7f, 0xc839, 0x21, 0 - .dw 0xefc0, 0xc839, 0xefff, 0xc839, 0x21, 0 - .dw 0xf040, 0xc839, 0xf07f, 0xc839, 0x21, 0 - .dw 0xf0c0, 0xc839, 0xf0ff, 0xc839, 0x21, 0 - .dw 0xf140, 0xc839, 0xf17f, 0xc839, 0x21, 0 - .dw 0xf1c0, 0xc839, 0xf1ff, 0xc839, 0x21, 0 - .dw 0xf240, 0xc839, 0xf27f, 0xc839, 0x21, 0 - .dw 0xf2c0, 0xc839, 0xf2ff, 0xc839, 0x21, 0 - .dw 0xf340, 0xc839, 0xf37f, 0xc839, 0x21, 0 - .dw 0xf3c0, 0xc839, 0xf3ff, 0xc839, 0x21, 0 - .dw 0xf440, 0xc839, 0xf47f, 0xc839, 0x21, 0 - .dw 0xf4c0, 0xc839, 0xf4ff, 0xc839, 0x21, 0 - .dw 0xf540, 0xc839, 0xf57f, 0xc839, 0x21, 0 - .dw 0xf5c0, 0xc839, 0xf5ff, 0xc839, 0x21, 0 - .dw 0xf640, 0xc839, 0xf67f, 0xc839, 0x21, 0 - .dw 0xf6c0, 0xc839, 0xf6ff, 0xc839, 0x21, 0 - .dw 0xf740, 0xc839, 0xf77f, 0xc839, 0x21, 0 - .dw 0xf7c0, 0xc839, 0xf7ff, 0xc839, 0x21, 0 - .dw 0xf840, 0xc839, 0xf87f, 0xc839, 0x21, 0 - .dw 0xf8c0, 0xc839, 0xf8ff, 0xc839, 0x21, 0 - .dw 0xf940, 0xc839, 0xf97f, 0xc839, 0x21, 0 - .dw 0xf9c0, 0xc839, 0x1fff, 0xc83a, 0x21, 0 - .dw 0x2040, 0xc83a, 0x207f, 0xc83a, 0x21, 0 - .dw 0x20c0, 0xc83a, 0x20ff, 0xc83a, 0x21, 0 - .dw 0x2140, 0xc83a, 0x217f, 0xc83a, 0x21, 0 - .dw 0x21c0, 0xc83a, 0x21ff, 0xc83a, 0x21, 0 - .dw 0x2240, 0xc83a, 0x227f, 0xc83a, 0x21, 0 - .dw 0x22c0, 0xc83a, 0x22ff, 0xc83a, 0x21, 0 - .dw 0x2340, 0xc83a, 0x237f, 0xc83a, 0x21, 0 - .dw 0x23c0, 0xc83a, 0x23ff, 0xc83a, 0x21, 0 - .dw 0x2440, 0xc83a, 0x247f, 0xc83a, 0x21, 0 - .dw 0x24c0, 0xc83a, 0x24ff, 0xc83a, 0x21, 0 - .dw 0x2540, 0xc83a, 0x257f, 0xc83a, 0x21, 0 - .dw 0x25c0, 0xc83a, 0x25ff, 0xc83a, 0x21, 0 - .dw 0x2640, 0xc83a, 0x267f, 0xc83a, 0x21, 0 - .dw 0x26c0, 0xc83a, 0x26ff, 0xc83a, 0x21, 0 - .dw 0x2740, 0xc83a, 0x277f, 0xc83a, 0x21, 0 - .dw 0x27c0, 0xc83a, 0x27ff, 0xc83a, 0x21, 0 - .dw 0x2840, 0xc83a, 0x287f, 0xc83a, 0x21, 0 - .dw 0x28c0, 0xc83a, 0x28ff, 0xc83a, 0x21, 0 - .dw 0x2940, 0xc83a, 0x297f, 0xc83a, 0x21, 0 - .dw 0x29c0, 0xc83a, 0x29ff, 0xc83a, 0x21, 0 - .dw 0x2a40, 0xc83a, 0x2a7f, 0xc83a, 0x21, 0 - .dw 0x2ac0, 0xc83a, 0x2aff, 0xc83a, 0x21, 0 - .dw 0x2b40, 0xc83a, 0x2b7f, 0xc83a, 0x21, 0 - .dw 0x2bc0, 0xc83a, 0x2bff, 0xc83a, 0x21, 0 - .dw 0x2c40, 0xc83a, 0x2c7f, 0xc83a, 0x21, 0 - .dw 0x2cc0, 0xc83a, 0x2cff, 0xc83a, 0x21, 0 - .dw 0x2d40, 0xc83a, 0x2d7f, 0xc83a, 0x21, 0 - .dw 0x2dc0, 0xc83a, 0x2dff, 0xc83a, 0x21, 0 - .dw 0x2e40, 0xc83a, 0x2e7f, 0xc83a, 0x21, 0 - .dw 0x2ec0, 0xc83a, 0x2eff, 0xc83a, 0x21, 0 - .dw 0x2f40, 0xc83a, 0x2f7f, 0xc83a, 0x21, 0 - .dw 0x2fc0, 0xc83a, 0x2fff, 0xc83a, 0x21, 0 - .dw 0x3040, 0xc83a, 0x307f, 0xc83a, 0x21, 0 - .dw 0x30c0, 0xc83a, 0x30ff, 0xc83a, 0x21, 0 - .dw 0x3140, 0xc83a, 0x317f, 0xc83a, 0x21, 0 - .dw 0x31c0, 0xc83a, 0x31ff, 0xc83a, 0x21, 0 - .dw 0x3240, 0xc83a, 0x327f, 0xc83a, 0x21, 0 - .dw 0x32c0, 0xc83a, 0x32ff, 0xc83a, 0x21, 0 - .dw 0x3340, 0xc83a, 0x337f, 0xc83a, 0x21, 0 - .dw 0x33c0, 0xc83a, 0x33ff, 0xc83a, 0x21, 0 - .dw 0x3440, 0xc83a, 0x347f, 0xc83a, 0x21, 0 - .dw 0x34c0, 0xc83a, 0x34ff, 0xc83a, 0x21, 0 - .dw 0x3540, 0xc83a, 0x357f, 0xc83a, 0x21, 0 - .dw 0x35c0, 0xc83a, 0x35ff, 0xc83a, 0x21, 0 - .dw 0x3640, 0xc83a, 0x367f, 0xc83a, 0x21, 0 - .dw 0x36c0, 0xc83a, 0x36ff, 0xc83a, 0x21, 0 - .dw 0x3740, 0xc83a, 0x377f, 0xc83a, 0x21, 0 - .dw 0x37c0, 0xc83a, 0x37ff, 0xc83a, 0x21, 0 - .dw 0x3840, 0xc83a, 0x387f, 0xc83a, 0x21, 0 - .dw 0x38c0, 0xc83a, 0x38ff, 0xc83a, 0x21, 0 - .dw 0x3940, 0xc83a, 0x397f, 0xc83a, 0x21, 0 - .dw 0x39c0, 0xc83a, 0x5fff, 0xc83a, 0x21, 0 - .dw 0x6040, 0xc83a, 0x607f, 0xc83a, 0x21, 0 - .dw 0x60c0, 0xc83a, 0x60ff, 0xc83a, 0x21, 0 - .dw 0x6140, 0xc83a, 0x617f, 0xc83a, 0x21, 0 - .dw 0x61c0, 0xc83a, 0x61ff, 0xc83a, 0x21, 0 - .dw 0x6240, 0xc83a, 0x627f, 0xc83a, 0x21, 0 - .dw 0x62c0, 0xc83a, 0x62ff, 0xc83a, 0x21, 0 - .dw 0x6340, 0xc83a, 0x637f, 0xc83a, 0x21, 0 - .dw 0x63c0, 0xc83a, 0x63ff, 0xc83a, 0x21, 0 - .dw 0x6440, 0xc83a, 0x647f, 0xc83a, 0x21, 0 - .dw 0x64c0, 0xc83a, 0x64ff, 0xc83a, 0x21, 0 - .dw 0x6540, 0xc83a, 0x657f, 0xc83a, 0x21, 0 - .dw 0x65c0, 0xc83a, 0x65ff, 0xc83a, 0x21, 0 - .dw 0x6640, 0xc83a, 0x667f, 0xc83a, 0x21, 0 - .dw 0x66c0, 0xc83a, 0x66ff, 0xc83a, 0x21, 0 - .dw 0x6740, 0xc83a, 0x677f, 0xc83a, 0x21, 0 - .dw 0x67c0, 0xc83a, 0x67ff, 0xc83a, 0x21, 0 - .dw 0x6840, 0xc83a, 0x687f, 0xc83a, 0x21, 0 - .dw 0x68c0, 0xc83a, 0x68ff, 0xc83a, 0x21, 0 - .dw 0x6940, 0xc83a, 0x697f, 0xc83a, 0x21, 0 - .dw 0x69c0, 0xc83a, 0x69ff, 0xc83a, 0x21, 0 - .dw 0x6a40, 0xc83a, 0x6a7f, 0xc83a, 0x21, 0 - .dw 0x6ac0, 0xc83a, 0x6aff, 0xc83a, 0x21, 0 - .dw 0x6b40, 0xc83a, 0x6b7f, 0xc83a, 0x21, 0 - .dw 0x6bc0, 0xc83a, 0x6bff, 0xc83a, 0x21, 0 - .dw 0x6c40, 0xc83a, 0x6c7f, 0xc83a, 0x21, 0 - .dw 0x6cc0, 0xc83a, 0x6cff, 0xc83a, 0x21, 0 - .dw 0x6d40, 0xc83a, 0x6d7f, 0xc83a, 0x21, 0 - .dw 0x6dc0, 0xc83a, 0x6dff, 0xc83a, 0x21, 0 - .dw 0x6e40, 0xc83a, 0x6e7f, 0xc83a, 0x21, 0 - .dw 0x6ec0, 0xc83a, 0x6eff, 0xc83a, 0x21, 0 - .dw 0x6f40, 0xc83a, 0x6f7f, 0xc83a, 0x21, 0 - .dw 0x6fc0, 0xc83a, 0x6fff, 0xc83a, 0x21, 0 - .dw 0x7040, 0xc83a, 0x707f, 0xc83a, 0x21, 0 - .dw 0x70c0, 0xc83a, 0x70ff, 0xc83a, 0x21, 0 - .dw 0x7140, 0xc83a, 0x717f, 0xc83a, 0x21, 0 - .dw 0x71c0, 0xc83a, 0x71ff, 0xc83a, 0x21, 0 - .dw 0x7240, 0xc83a, 0x727f, 0xc83a, 0x21, 0 - .dw 0x72c0, 0xc83a, 0x72ff, 0xc83a, 0x21, 0 - .dw 0x7340, 0xc83a, 0x737f, 0xc83a, 0x21, 0 - .dw 0x73c0, 0xc83a, 0x73ff, 0xc83a, 0x21, 0 - .dw 0x7440, 0xc83a, 0x747f, 0xc83a, 0x21, 0 - .dw 0x74c0, 0xc83a, 0x74ff, 0xc83a, 0x21, 0 - .dw 0x7540, 0xc83a, 0x757f, 0xc83a, 0x21, 0 - .dw 0x75c0, 0xc83a, 0x75ff, 0xc83a, 0x21, 0 - .dw 0x7640, 0xc83a, 0x767f, 0xc83a, 0x21, 0 - .dw 0x76c0, 0xc83a, 0x76ff, 0xc83a, 0x21, 0 - .dw 0x7740, 0xc83a, 0x777f, 0xc83a, 0x21, 0 - .dw 0x77c0, 0xc83a, 0x77ff, 0xc83a, 0x21, 0 - .dw 0x7840, 0xc83a, 0x787f, 0xc83a, 0x21, 0 - .dw 0x78c0, 0xc83a, 0x78ff, 0xc83a, 0x21, 0 - .dw 0x7940, 0xc83a, 0x797f, 0xc83a, 0x21, 0 - .dw 0x79c0, 0xc83a, 0x9fff, 0xc83a, 0x21, 0 - .dw 0xa040, 0xc83a, 0xa07f, 0xc83a, 0x21, 0 - .dw 0xa0c0, 0xc83a, 0xa0ff, 0xc83a, 0x21, 0 - .dw 0xa140, 0xc83a, 0xa17f, 0xc83a, 0x21, 0 - .dw 0xa1c0, 0xc83a, 0xa1ff, 0xc83a, 0x21, 0 - .dw 0xa240, 0xc83a, 0xa27f, 0xc83a, 0x21, 0 - .dw 0xa2c0, 0xc83a, 0xa2ff, 0xc83a, 0x21, 0 - .dw 0xa340, 0xc83a, 0xa37f, 0xc83a, 0x21, 0 - .dw 0xa3c0, 0xc83a, 0xa3ff, 0xc83a, 0x21, 0 - .dw 0xa440, 0xc83a, 0xa47f, 0xc83a, 0x21, 0 - .dw 0xa4c0, 0xc83a, 0xa4ff, 0xc83a, 0x21, 0 - .dw 0xa540, 0xc83a, 0xa57f, 0xc83a, 0x21, 0 - .dw 0xa5c0, 0xc83a, 0xa5ff, 0xc83a, 0x21, 0 - .dw 0xa640, 0xc83a, 0xa67f, 0xc83a, 0x21, 0 - .dw 0xa6c0, 0xc83a, 0xa6ff, 0xc83a, 0x21, 0 - .dw 0xa740, 0xc83a, 0xa77f, 0xc83a, 0x21, 0 - .dw 0xa7c0, 0xc83a, 0xa7ff, 0xc83a, 0x21, 0 - .dw 0xa840, 0xc83a, 0xa87f, 0xc83a, 0x21, 0 - .dw 0xa8c0, 0xc83a, 0xa8ff, 0xc83a, 0x21, 0 - .dw 0xa940, 0xc83a, 0xa97f, 0xc83a, 0x21, 0 - .dw 0xa9c0, 0xc83a, 0xa9ff, 0xc83a, 0x21, 0 - .dw 0xaa40, 0xc83a, 0xaa7f, 0xc83a, 0x21, 0 - .dw 0xaac0, 0xc83a, 0xaaff, 0xc83a, 0x21, 0 - .dw 0xab40, 0xc83a, 0xab7f, 0xc83a, 0x21, 0 - .dw 0xabc0, 0xc83a, 0xabff, 0xc83a, 0x21, 0 - .dw 0xac40, 0xc83a, 0xac7f, 0xc83a, 0x21, 0 - .dw 0xacc0, 0xc83a, 0xacff, 0xc83a, 0x21, 0 - .dw 0xad40, 0xc83a, 0xad7f, 0xc83a, 0x21, 0 - .dw 0xadc0, 0xc83a, 0xadff, 0xc83a, 0x21, 0 - .dw 0xae40, 0xc83a, 0xae7f, 0xc83a, 0x21, 0 - .dw 0xaec0, 0xc83a, 0xaeff, 0xc83a, 0x21, 0 - .dw 0xaf40, 0xc83a, 0xaf7f, 0xc83a, 0x21, 0 - .dw 0xafc0, 0xc83a, 0xafff, 0xc83a, 0x21, 0 - .dw 0xb040, 0xc83a, 0xb07f, 0xc83a, 0x21, 0 - .dw 0xb0c0, 0xc83a, 0xb0ff, 0xc83a, 0x21, 0 - .dw 0xb140, 0xc83a, 0xb17f, 0xc83a, 0x21, 0 - .dw 0xb1c0, 0xc83a, 0xb1ff, 0xc83a, 0x21, 0 - .dw 0xb240, 0xc83a, 0xb27f, 0xc83a, 0x21, 0 - .dw 0xb2c0, 0xc83a, 0xb2ff, 0xc83a, 0x21, 0 - .dw 0xb340, 0xc83a, 0xb37f, 0xc83a, 0x21, 0 - .dw 0xb3c0, 0xc83a, 0xb3ff, 0xc83a, 0x21, 0 - .dw 0xb440, 0xc83a, 0xb47f, 0xc83a, 0x21, 0 - .dw 0xb4c0, 0xc83a, 0xb4ff, 0xc83a, 0x21, 0 - .dw 0xb540, 0xc83a, 0xb57f, 0xc83a, 0x21, 0 - .dw 0xb5c0, 0xc83a, 0xb5ff, 0xc83a, 0x21, 0 - .dw 0xb640, 0xc83a, 0xb67f, 0xc83a, 0x21, 0 - .dw 0xb6c0, 0xc83a, 0xb6ff, 0xc83a, 0x21, 0 - .dw 0xb740, 0xc83a, 0xb77f, 0xc83a, 0x21, 0 - .dw 0xb7c0, 0xc83a, 0xb7ff, 0xc83a, 0x21, 0 - .dw 0xb840, 0xc83a, 0xb87f, 0xc83a, 0x21, 0 - .dw 0xb8c0, 0xc83a, 0xb8ff, 0xc83a, 0x21, 0 - .dw 0xb940, 0xc83a, 0xb97f, 0xc83a, 0x21, 0 - .dw 0xb9c0, 0xc83a, 0xdfff, 0xc83a, 0x21, 0 - .dw 0xe040, 0xc83a, 0xe07f, 0xc83a, 0x21, 0 - .dw 0xe0c0, 0xc83a, 0xe0ff, 0xc83a, 0x21, 0 - .dw 0xe140, 0xc83a, 0xe17f, 0xc83a, 0x21, 0 - .dw 0xe1c0, 0xc83a, 0xe1ff, 0xc83a, 0x21, 0 - .dw 0xe240, 0xc83a, 0xe27f, 0xc83a, 0x21, 0 - .dw 0xe2c0, 0xc83a, 0xe2ff, 0xc83a, 0x21, 0 - .dw 0xe340, 0xc83a, 0xe37f, 0xc83a, 0x21, 0 - .dw 0xe3c0, 0xc83a, 0xe3ff, 0xc83a, 0x21, 0 - .dw 0xe440, 0xc83a, 0xe47f, 0xc83a, 0x21, 0 - .dw 0xe4c0, 0xc83a, 0xe4ff, 0xc83a, 0x21, 0 - .dw 0xe540, 0xc83a, 0xe57f, 0xc83a, 0x21, 0 - .dw 0xe5c0, 0xc83a, 0xe5ff, 0xc83a, 0x21, 0 - .dw 0xe640, 0xc83a, 0xe67f, 0xc83a, 0x21, 0 - .dw 0xe6c0, 0xc83a, 0xe6ff, 0xc83a, 0x21, 0 - .dw 0xe740, 0xc83a, 0xe77f, 0xc83a, 0x21, 0 - .dw 0xe7c0, 0xc83a, 0xe7ff, 0xc83a, 0x21, 0 - .dw 0xe840, 0xc83a, 0xe87f, 0xc83a, 0x21, 0 - .dw 0xe8c0, 0xc83a, 0xe8ff, 0xc83a, 0x21, 0 - .dw 0xe940, 0xc83a, 0xe97f, 0xc83a, 0x21, 0 - .dw 0xe9c0, 0xc83a, 0xe9ff, 0xc83a, 0x21, 0 - .dw 0xea40, 0xc83a, 0xea7f, 0xc83a, 0x21, 0 - .dw 0xeac0, 0xc83a, 0xeaff, 0xc83a, 0x21, 0 - .dw 0xeb40, 0xc83a, 0xeb7f, 0xc83a, 0x21, 0 - .dw 0xebc0, 0xc83a, 0xebff, 0xc83a, 0x21, 0 - .dw 0xec40, 0xc83a, 0xec7f, 0xc83a, 0x21, 0 - .dw 0xecc0, 0xc83a, 0xecff, 0xc83a, 0x21, 0 - .dw 0xed40, 0xc83a, 0xed7f, 0xc83a, 0x21, 0 - .dw 0xedc0, 0xc83a, 0xedff, 0xc83a, 0x21, 0 - .dw 0xee40, 0xc83a, 0xee7f, 0xc83a, 0x21, 0 - .dw 0xeec0, 0xc83a, 0xeeff, 0xc83a, 0x21, 0 - .dw 0xef40, 0xc83a, 0xef7f, 0xc83a, 0x21, 0 - .dw 0xefc0, 0xc83a, 0xefff, 0xc83a, 0x21, 0 - .dw 0xf040, 0xc83a, 0xf07f, 0xc83a, 0x21, 0 - .dw 0xf0c0, 0xc83a, 0xf0ff, 0xc83a, 0x21, 0 - .dw 0xf140, 0xc83a, 0xf17f, 0xc83a, 0x21, 0 - .dw 0xf1c0, 0xc83a, 0xf1ff, 0xc83a, 0x21, 0 - .dw 0xf240, 0xc83a, 0xf27f, 0xc83a, 0x21, 0 - .dw 0xf2c0, 0xc83a, 0xf2ff, 0xc83a, 0x21, 0 - .dw 0xf340, 0xc83a, 0xf37f, 0xc83a, 0x21, 0 - .dw 0xf3c0, 0xc83a, 0xf3ff, 0xc83a, 0x21, 0 - .dw 0xf440, 0xc83a, 0xf47f, 0xc83a, 0x21, 0 - .dw 0xf4c0, 0xc83a, 0xf4ff, 0xc83a, 0x21, 0 - .dw 0xf540, 0xc83a, 0xf57f, 0xc83a, 0x21, 0 - .dw 0xf5c0, 0xc83a, 0xf5ff, 0xc83a, 0x21, 0 - .dw 0xf640, 0xc83a, 0xf67f, 0xc83a, 0x21, 0 - .dw 0xf6c0, 0xc83a, 0xf6ff, 0xc83a, 0x21, 0 - .dw 0xf740, 0xc83a, 0xf77f, 0xc83a, 0x21, 0 - .dw 0xf7c0, 0xc83a, 0xf7ff, 0xc83a, 0x21, 0 - .dw 0xf840, 0xc83a, 0xf87f, 0xc83a, 0x21, 0 - .dw 0xf8c0, 0xc83a, 0xf8ff, 0xc83a, 0x21, 0 - .dw 0xf940, 0xc83a, 0xf97f, 0xc83a, 0x21, 0 - .dw 0xf9c0, 0xc83a, 0xffff, 0xc83b, 0x21, 0 - .dw 0x0040, 0xc83c, 0x007f, 0xc83c, 0x21, 0 - .dw 0x00c0, 0xc83c, 0x00ff, 0xc83c, 0x21, 0 - .dw 0x0140, 0xc83c, 0x017f, 0xc83c, 0x21, 0 - .dw 0x01c0, 0xc83c, 0x01ff, 0xc83c, 0x21, 0 - .dw 0x0240, 0xc83c, 0x027f, 0xc83c, 0x21, 0 - .dw 0x02c0, 0xc83c, 0x02ff, 0xc83c, 0x21, 0 - .dw 0x0340, 0xc83c, 0x037f, 0xc83c, 0x21, 0 - .dw 0x03c0, 0xc83c, 0x03ff, 0xc83c, 0x21, 0 - .dw 0x0440, 0xc83c, 0x047f, 0xc83c, 0x21, 0 - .dw 0x04c0, 0xc83c, 0x04ff, 0xc83c, 0x21, 0 - .dw 0x0540, 0xc83c, 0x057f, 0xc83c, 0x21, 0 - .dw 0x05c0, 0xc83c, 0x05ff, 0xc83c, 0x21, 0 - .dw 0x0640, 0xc83c, 0x067f, 0xc83c, 0x21, 0 - .dw 0x06c0, 0xc83c, 0x06ff, 0xc83c, 0x21, 0 - .dw 0x0740, 0xc83c, 0x077f, 0xc83c, 0x21, 0 - .dw 0x07c0, 0xc83c, 0x07ff, 0xc83c, 0x21, 0 - .dw 0x0840, 0xc83c, 0x087f, 0xc83c, 0x21, 0 - .dw 0x08c0, 0xc83c, 0x08ff, 0xc83c, 0x21, 0 - .dw 0x0940, 0xc83c, 0x097f, 0xc83c, 0x21, 0 - .dw 0x09c0, 0xc83c, 0x09ff, 0xc83c, 0x21, 0 - .dw 0x0a40, 0xc83c, 0x0a7f, 0xc83c, 0x21, 0 - .dw 0x0ac0, 0xc83c, 0x0aff, 0xc83c, 0x21, 0 - .dw 0x0b40, 0xc83c, 0x0b7f, 0xc83c, 0x21, 0 - .dw 0x0bc0, 0xc83c, 0x0bff, 0xc83c, 0x21, 0 - .dw 0x0c40, 0xc83c, 0x0c7f, 0xc83c, 0x21, 0 - .dw 0x0cc0, 0xc83c, 0x0cff, 0xc83c, 0x21, 0 - .dw 0x0d40, 0xc83c, 0x0d7f, 0xc83c, 0x21, 0 - .dw 0x0dc0, 0xc83c, 0x0dff, 0xc83c, 0x21, 0 - .dw 0x0e40, 0xc83c, 0x0e7f, 0xc83c, 0x21, 0 - .dw 0x0ec0, 0xc83c, 0x0eff, 0xc83c, 0x21, 0 - .dw 0x0f40, 0xc83c, 0x0f7f, 0xc83c, 0x21, 0 - .dw 0x0fc0, 0xc83c, 0x0fff, 0xc83c, 0x21, 0 - .dw 0x1040, 0xc83c, 0x107f, 0xc83c, 0x21, 0 - .dw 0x10c0, 0xc83c, 0x10ff, 0xc83c, 0x21, 0 - .dw 0x1140, 0xc83c, 0x117f, 0xc83c, 0x21, 0 - .dw 0x11c0, 0xc83c, 0x11ff, 0xc83c, 0x21, 0 - .dw 0x1240, 0xc83c, 0x127f, 0xc83c, 0x21, 0 - .dw 0x12c0, 0xc83c, 0x12ff, 0xc83c, 0x21, 0 - .dw 0x1340, 0xc83c, 0x137f, 0xc83c, 0x21, 0 - .dw 0x13c0, 0xc83c, 0x13ff, 0xc83c, 0x21, 0 - .dw 0x1440, 0xc83c, 0x147f, 0xc83c, 0x21, 0 - .dw 0x14c0, 0xc83c, 0x14ff, 0xc83c, 0x21, 0 - .dw 0x1540, 0xc83c, 0x157f, 0xc83c, 0x21, 0 - .dw 0x15c0, 0xc83c, 0x15ff, 0xc83c, 0x21, 0 - .dw 0x1640, 0xc83c, 0x167f, 0xc83c, 0x21, 0 - .dw 0x16c0, 0xc83c, 0x16ff, 0xc83c, 0x21, 0 - .dw 0x1740, 0xc83c, 0x177f, 0xc83c, 0x21, 0 - .dw 0x17c0, 0xc83c, 0x17ff, 0xc83c, 0x21, 0 - .dw 0x1840, 0xc83c, 0x187f, 0xc83c, 0x21, 0 - .dw 0x18c0, 0xc83c, 0x18ff, 0xc83c, 0x21, 0 - .dw 0x1940, 0xc83c, 0x197f, 0xc83c, 0x21, 0 - .dw 0x19c0, 0xc83c, 0x1fff, 0xc83c, 0x21, 0 - .dw 0x2040, 0xc83c, 0x207f, 0xc83c, 0x21, 0 - .dw 0x20c0, 0xc83c, 0x20ff, 0xc83c, 0x21, 0 - .dw 0x2140, 0xc83c, 0x217f, 0xc83c, 0x21, 0 - .dw 0x21c0, 0xc83c, 0x21ff, 0xc83c, 0x21, 0 - .dw 0x2240, 0xc83c, 0x227f, 0xc83c, 0x21, 0 - .dw 0x22c0, 0xc83c, 0x22ff, 0xc83c, 0x21, 0 - .dw 0x2340, 0xc83c, 0x237f, 0xc83c, 0x21, 0 - .dw 0x23c0, 0xc83c, 0x23ff, 0xc83c, 0x21, 0 - .dw 0x2440, 0xc83c, 0x247f, 0xc83c, 0x21, 0 - .dw 0x24c0, 0xc83c, 0x24ff, 0xc83c, 0x21, 0 - .dw 0x2540, 0xc83c, 0x257f, 0xc83c, 0x21, 0 - .dw 0x25c0, 0xc83c, 0x25ff, 0xc83c, 0x21, 0 - .dw 0x2640, 0xc83c, 0x267f, 0xc83c, 0x21, 0 - .dw 0x26c0, 0xc83c, 0x26ff, 0xc83c, 0x21, 0 - .dw 0x2740, 0xc83c, 0x277f, 0xc83c, 0x21, 0 - .dw 0x27c0, 0xc83c, 0x27ff, 0xc83c, 0x21, 0 - .dw 0x2840, 0xc83c, 0x287f, 0xc83c, 0x21, 0 - .dw 0x28c0, 0xc83c, 0x28ff, 0xc83c, 0x21, 0 - .dw 0x2940, 0xc83c, 0x297f, 0xc83c, 0x21, 0 - .dw 0x29c0, 0xc83c, 0x29ff, 0xc83c, 0x21, 0 - .dw 0x2a40, 0xc83c, 0x2a7f, 0xc83c, 0x21, 0 - .dw 0x2ac0, 0xc83c, 0x2aff, 0xc83c, 0x21, 0 - .dw 0x2b40, 0xc83c, 0x2b7f, 0xc83c, 0x21, 0 - .dw 0x2bc0, 0xc83c, 0x2bff, 0xc83c, 0x21, 0 - .dw 0x2c40, 0xc83c, 0x2c7f, 0xc83c, 0x21, 0 - .dw 0x2cc0, 0xc83c, 0x2cff, 0xc83c, 0x21, 0 - .dw 0x2d40, 0xc83c, 0x2d7f, 0xc83c, 0x21, 0 - .dw 0x2dc0, 0xc83c, 0x2dff, 0xc83c, 0x21, 0 - .dw 0x2e40, 0xc83c, 0x2e7f, 0xc83c, 0x21, 0 - .dw 0x2ec0, 0xc83c, 0x2eff, 0xc83c, 0x21, 0 - .dw 0x2f40, 0xc83c, 0x2f7f, 0xc83c, 0x21, 0 - .dw 0x2fc0, 0xc83c, 0x2fff, 0xc83c, 0x21, 0 - .dw 0x3040, 0xc83c, 0x307f, 0xc83c, 0x21, 0 - .dw 0x30c0, 0xc83c, 0x30ff, 0xc83c, 0x21, 0 - .dw 0x3140, 0xc83c, 0x317f, 0xc83c, 0x21, 0 - .dw 0x31c0, 0xc83c, 0x31ff, 0xc83c, 0x21, 0 - .dw 0x3240, 0xc83c, 0x327f, 0xc83c, 0x21, 0 - .dw 0x32c0, 0xc83c, 0x32ff, 0xc83c, 0x21, 0 - .dw 0x3340, 0xc83c, 0x337f, 0xc83c, 0x21, 0 - .dw 0x33c0, 0xc83c, 0x33ff, 0xc83c, 0x21, 0 - .dw 0x3440, 0xc83c, 0x347f, 0xc83c, 0x21, 0 - .dw 0x34c0, 0xc83c, 0x34ff, 0xc83c, 0x21, 0 - .dw 0x3540, 0xc83c, 0x357f, 0xc83c, 0x21, 0 - .dw 0x35c0, 0xc83c, 0x35ff, 0xc83c, 0x21, 0 - .dw 0x3640, 0xc83c, 0x367f, 0xc83c, 0x21, 0 - .dw 0x36c0, 0xc83c, 0x36ff, 0xc83c, 0x21, 0 - .dw 0x3740, 0xc83c, 0x377f, 0xc83c, 0x21, 0 - .dw 0x37c0, 0xc83c, 0x37ff, 0xc83c, 0x21, 0 - .dw 0x3840, 0xc83c, 0x387f, 0xc83c, 0x21, 0 - .dw 0x38c0, 0xc83c, 0x38ff, 0xc83c, 0x21, 0 - .dw 0x3940, 0xc83c, 0x397f, 0xc83c, 0x21, 0 - .dw 0x39c0, 0xc83c, 0x3fff, 0xc83c, 0x21, 0 - .dw 0x4040, 0xc83c, 0x407f, 0xc83c, 0x21, 0 - .dw 0x40c0, 0xc83c, 0x40ff, 0xc83c, 0x21, 0 - .dw 0x4140, 0xc83c, 0x417f, 0xc83c, 0x21, 0 - .dw 0x41c0, 0xc83c, 0x41ff, 0xc83c, 0x21, 0 - .dw 0x4240, 0xc83c, 0x427f, 0xc83c, 0x21, 0 - .dw 0x42c0, 0xc83c, 0x42ff, 0xc83c, 0x21, 0 - .dw 0x4340, 0xc83c, 0x437f, 0xc83c, 0x21, 0 - .dw 0x43c0, 0xc83c, 0x43ff, 0xc83c, 0x21, 0 - .dw 0x4440, 0xc83c, 0x447f, 0xc83c, 0x21, 0 - .dw 0x44c0, 0xc83c, 0x44ff, 0xc83c, 0x21, 0 - .dw 0x4540, 0xc83c, 0x457f, 0xc83c, 0x21, 0 - .dw 0x45c0, 0xc83c, 0x45ff, 0xc83c, 0x21, 0 - .dw 0x4640, 0xc83c, 0x467f, 0xc83c, 0x21, 0 - .dw 0x46c0, 0xc83c, 0x46ff, 0xc83c, 0x21, 0 - .dw 0x4740, 0xc83c, 0x477f, 0xc83c, 0x21, 0 - .dw 0x47c0, 0xc83c, 0x47ff, 0xc83c, 0x21, 0 - .dw 0x4840, 0xc83c, 0x487f, 0xc83c, 0x21, 0 - .dw 0x48c0, 0xc83c, 0x48ff, 0xc83c, 0x21, 0 - .dw 0x4940, 0xc83c, 0x497f, 0xc83c, 0x21, 0 - .dw 0x49c0, 0xc83c, 0x49ff, 0xc83c, 0x21, 0 - .dw 0x4a40, 0xc83c, 0x4a7f, 0xc83c, 0x21, 0 - .dw 0x4ac0, 0xc83c, 0x4aff, 0xc83c, 0x21, 0 - .dw 0x4b40, 0xc83c, 0x4b7f, 0xc83c, 0x21, 0 - .dw 0x4bc0, 0xc83c, 0x4bff, 0xc83c, 0x21, 0 - .dw 0x4c40, 0xc83c, 0x4c7f, 0xc83c, 0x21, 0 - .dw 0x4cc0, 0xc83c, 0x4cff, 0xc83c, 0x21, 0 - .dw 0x4d40, 0xc83c, 0x4d7f, 0xc83c, 0x21, 0 - .dw 0x4dc0, 0xc83c, 0x4dff, 0xc83c, 0x21, 0 - .dw 0x4e40, 0xc83c, 0x4e7f, 0xc83c, 0x21, 0 - .dw 0x4ec0, 0xc83c, 0x4eff, 0xc83c, 0x21, 0 - .dw 0x4f40, 0xc83c, 0x4f7f, 0xc83c, 0x21, 0 - .dw 0x4fc0, 0xc83c, 0x4fff, 0xc83c, 0x21, 0 - .dw 0x5040, 0xc83c, 0x507f, 0xc83c, 0x21, 0 - .dw 0x50c0, 0xc83c, 0x50ff, 0xc83c, 0x21, 0 - .dw 0x5140, 0xc83c, 0x517f, 0xc83c, 0x21, 0 - .dw 0x51c0, 0xc83c, 0x51ff, 0xc83c, 0x21, 0 - .dw 0x5240, 0xc83c, 0x527f, 0xc83c, 0x21, 0 - .dw 0x52c0, 0xc83c, 0x52ff, 0xc83c, 0x21, 0 - .dw 0x5340, 0xc83c, 0x537f, 0xc83c, 0x21, 0 - .dw 0x53c0, 0xc83c, 0x53ff, 0xc83c, 0x21, 0 - .dw 0x5440, 0xc83c, 0x547f, 0xc83c, 0x21, 0 - .dw 0x54c0, 0xc83c, 0x54ff, 0xc83c, 0x21, 0 - .dw 0x5540, 0xc83c, 0x557f, 0xc83c, 0x21, 0 - .dw 0x55c0, 0xc83c, 0x55ff, 0xc83c, 0x21, 0 - .dw 0x5640, 0xc83c, 0x567f, 0xc83c, 0x21, 0 - .dw 0x56c0, 0xc83c, 0x56ff, 0xc83c, 0x21, 0 - .dw 0x5740, 0xc83c, 0x577f, 0xc83c, 0x21, 0 - .dw 0x57c0, 0xc83c, 0x57ff, 0xc83c, 0x21, 0 - .dw 0x5840, 0xc83c, 0x587f, 0xc83c, 0x21, 0 - .dw 0x58c0, 0xc83c, 0x58ff, 0xc83c, 0x21, 0 - .dw 0x5940, 0xc83c, 0x597f, 0xc83c, 0x21, 0 - .dw 0x59c0, 0xc83c, 0x5fff, 0xc83c, 0x21, 0 - .dw 0x6040, 0xc83c, 0x607f, 0xc83c, 0x21, 0 - .dw 0x60c0, 0xc83c, 0x60ff, 0xc83c, 0x21, 0 - .dw 0x6140, 0xc83c, 0x617f, 0xc83c, 0x21, 0 - .dw 0x61c0, 0xc83c, 0x61ff, 0xc83c, 0x21, 0 - .dw 0x6240, 0xc83c, 0x627f, 0xc83c, 0x21, 0 - .dw 0x62c0, 0xc83c, 0x62ff, 0xc83c, 0x21, 0 - .dw 0x6340, 0xc83c, 0x637f, 0xc83c, 0x21, 0 - .dw 0x63c0, 0xc83c, 0x63ff, 0xc83c, 0x21, 0 - .dw 0x6440, 0xc83c, 0x647f, 0xc83c, 0x21, 0 - .dw 0x64c0, 0xc83c, 0x64ff, 0xc83c, 0x21, 0 - .dw 0x6540, 0xc83c, 0x657f, 0xc83c, 0x21, 0 - .dw 0x65c0, 0xc83c, 0x65ff, 0xc83c, 0x21, 0 - .dw 0x6640, 0xc83c, 0x667f, 0xc83c, 0x21, 0 - .dw 0x66c0, 0xc83c, 0x66ff, 0xc83c, 0x21, 0 - .dw 0x6740, 0xc83c, 0x677f, 0xc83c, 0x21, 0 - .dw 0x67c0, 0xc83c, 0x67ff, 0xc83c, 0x21, 0 - .dw 0x6840, 0xc83c, 0x687f, 0xc83c, 0x21, 0 - .dw 0x68c0, 0xc83c, 0x68ff, 0xc83c, 0x21, 0 - .dw 0x6940, 0xc83c, 0x697f, 0xc83c, 0x21, 0 - .dw 0x69c0, 0xc83c, 0x69ff, 0xc83c, 0x21, 0 - .dw 0x6a40, 0xc83c, 0x6a7f, 0xc83c, 0x21, 0 - .dw 0x6ac0, 0xc83c, 0x6aff, 0xc83c, 0x21, 0 - .dw 0x6b40, 0xc83c, 0x6b7f, 0xc83c, 0x21, 0 - .dw 0x6bc0, 0xc83c, 0x6bff, 0xc83c, 0x21, 0 - .dw 0x6c40, 0xc83c, 0x6c7f, 0xc83c, 0x21, 0 - .dw 0x6cc0, 0xc83c, 0x6cff, 0xc83c, 0x21, 0 - .dw 0x6d40, 0xc83c, 0x6d7f, 0xc83c, 0x21, 0 - .dw 0x6dc0, 0xc83c, 0x6dff, 0xc83c, 0x21, 0 - .dw 0x6e40, 0xc83c, 0x6e7f, 0xc83c, 0x21, 0 - .dw 0x6ec0, 0xc83c, 0x6eff, 0xc83c, 0x21, 0 - .dw 0x6f40, 0xc83c, 0x6f7f, 0xc83c, 0x21, 0 - .dw 0x6fc0, 0xc83c, 0x6fff, 0xc83c, 0x21, 0 - .dw 0x7040, 0xc83c, 0x707f, 0xc83c, 0x21, 0 - .dw 0x70c0, 0xc83c, 0x70ff, 0xc83c, 0x21, 0 - .dw 0x7140, 0xc83c, 0x717f, 0xc83c, 0x21, 0 - .dw 0x71c0, 0xc83c, 0x71ff, 0xc83c, 0x21, 0 - .dw 0x7240, 0xc83c, 0x727f, 0xc83c, 0x21, 0 - .dw 0x72c0, 0xc83c, 0x72ff, 0xc83c, 0x21, 0 - .dw 0x7340, 0xc83c, 0x737f, 0xc83c, 0x21, 0 - .dw 0x73c0, 0xc83c, 0x73ff, 0xc83c, 0x21, 0 - .dw 0x7440, 0xc83c, 0x747f, 0xc83c, 0x21, 0 - .dw 0x74c0, 0xc83c, 0x74ff, 0xc83c, 0x21, 0 - .dw 0x7540, 0xc83c, 0x757f, 0xc83c, 0x21, 0 - .dw 0x75c0, 0xc83c, 0x75ff, 0xc83c, 0x21, 0 - .dw 0x7640, 0xc83c, 0x767f, 0xc83c, 0x21, 0 - .dw 0x76c0, 0xc83c, 0x76ff, 0xc83c, 0x21, 0 - .dw 0x7740, 0xc83c, 0x777f, 0xc83c, 0x21, 0 - .dw 0x77c0, 0xc83c, 0x77ff, 0xc83c, 0x21, 0 - .dw 0x7840, 0xc83c, 0x787f, 0xc83c, 0x21, 0 - .dw 0x78c0, 0xc83c, 0x78ff, 0xc83c, 0x21, 0 - .dw 0x7940, 0xc83c, 0x797f, 0xc83c, 0x21, 0 - .dw 0x79c0, 0xc83c, 0x7fff, 0xc83c, 0x21, 0 - .dw 0x8040, 0xc83c, 0x807f, 0xc83c, 0x21, 0 - .dw 0x80c0, 0xc83c, 0x80ff, 0xc83c, 0x21, 0 - .dw 0x8140, 0xc83c, 0x817f, 0xc83c, 0x21, 0 - .dw 0x81c0, 0xc83c, 0x81ff, 0xc83c, 0x21, 0 - .dw 0x8240, 0xc83c, 0x827f, 0xc83c, 0x21, 0 - .dw 0x82c0, 0xc83c, 0x82ff, 0xc83c, 0x21, 0 - .dw 0x8340, 0xc83c, 0x837f, 0xc83c, 0x21, 0 - .dw 0x83c0, 0xc83c, 0x83ff, 0xc83c, 0x21, 0 - .dw 0x8440, 0xc83c, 0x847f, 0xc83c, 0x21, 0 - .dw 0x84c0, 0xc83c, 0x84ff, 0xc83c, 0x21, 0 - .dw 0x8540, 0xc83c, 0x857f, 0xc83c, 0x21, 0 - .dw 0x85c0, 0xc83c, 0x85ff, 0xc83c, 0x21, 0 - .dw 0x8640, 0xc83c, 0x867f, 0xc83c, 0x21, 0 - .dw 0x86c0, 0xc83c, 0x86ff, 0xc83c, 0x21, 0 - .dw 0x8740, 0xc83c, 0x877f, 0xc83c, 0x21, 0 - .dw 0x87c0, 0xc83c, 0x87ff, 0xc83c, 0x21, 0 - .dw 0x8840, 0xc83c, 0x887f, 0xc83c, 0x21, 0 - .dw 0x88c0, 0xc83c, 0x88ff, 0xc83c, 0x21, 0 - .dw 0x8940, 0xc83c, 0x897f, 0xc83c, 0x21, 0 - .dw 0x89c0, 0xc83c, 0x89ff, 0xc83c, 0x21, 0 - .dw 0x8a40, 0xc83c, 0x8a7f, 0xc83c, 0x21, 0 - .dw 0x8ac0, 0xc83c, 0x8aff, 0xc83c, 0x21, 0 - .dw 0x8b40, 0xc83c, 0x8b7f, 0xc83c, 0x21, 0 - .dw 0x8bc0, 0xc83c, 0x8bff, 0xc83c, 0x21, 0 - .dw 0x8c40, 0xc83c, 0x8c7f, 0xc83c, 0x21, 0 - .dw 0x8cc0, 0xc83c, 0x8cff, 0xc83c, 0x21, 0 - .dw 0x8d40, 0xc83c, 0x8d7f, 0xc83c, 0x21, 0 - .dw 0x8dc0, 0xc83c, 0x8dff, 0xc83c, 0x21, 0 - .dw 0x8e40, 0xc83c, 0x8e7f, 0xc83c, 0x21, 0 - .dw 0x8ec0, 0xc83c, 0x8eff, 0xc83c, 0x21, 0 - .dw 0x8f40, 0xc83c, 0x8f7f, 0xc83c, 0x21, 0 - .dw 0x8fc0, 0xc83c, 0x8fff, 0xc83c, 0x21, 0 - .dw 0x9040, 0xc83c, 0x907f, 0xc83c, 0x21, 0 - .dw 0x90c0, 0xc83c, 0x90ff, 0xc83c, 0x21, 0 - .dw 0x9140, 0xc83c, 0x917f, 0xc83c, 0x21, 0 - .dw 0x91c0, 0xc83c, 0x91ff, 0xc83c, 0x21, 0 - .dw 0x9240, 0xc83c, 0x927f, 0xc83c, 0x21, 0 - .dw 0x92c0, 0xc83c, 0x92ff, 0xc83c, 0x21, 0 - .dw 0x9340, 0xc83c, 0x937f, 0xc83c, 0x21, 0 - .dw 0x93c0, 0xc83c, 0x93ff, 0xc83c, 0x21, 0 - .dw 0x9440, 0xc83c, 0x947f, 0xc83c, 0x21, 0 - .dw 0x94c0, 0xc83c, 0x94ff, 0xc83c, 0x21, 0 - .dw 0x9540, 0xc83c, 0x957f, 0xc83c, 0x21, 0 - .dw 0x95c0, 0xc83c, 0x95ff, 0xc83c, 0x21, 0 - .dw 0x9640, 0xc83c, 0x967f, 0xc83c, 0x21, 0 - .dw 0x96c0, 0xc83c, 0x96ff, 0xc83c, 0x21, 0 - .dw 0x9740, 0xc83c, 0x977f, 0xc83c, 0x21, 0 - .dw 0x97c0, 0xc83c, 0x97ff, 0xc83c, 0x21, 0 - .dw 0x9840, 0xc83c, 0x987f, 0xc83c, 0x21, 0 - .dw 0x98c0, 0xc83c, 0x98ff, 0xc83c, 0x21, 0 - .dw 0x9940, 0xc83c, 0x997f, 0xc83c, 0x21, 0 - .dw 0x99c0, 0xc83c, 0x9fff, 0xc83c, 0x21, 0 - .dw 0xa040, 0xc83c, 0xa07f, 0xc83c, 0x21, 0 - .dw 0xa0c0, 0xc83c, 0xa0ff, 0xc83c, 0x21, 0 - .dw 0xa140, 0xc83c, 0xa17f, 0xc83c, 0x21, 0 - .dw 0xa1c0, 0xc83c, 0xa1ff, 0xc83c, 0x21, 0 - .dw 0xa240, 0xc83c, 0xa27f, 0xc83c, 0x21, 0 - .dw 0xa2c0, 0xc83c, 0xa2ff, 0xc83c, 0x21, 0 - .dw 0xa340, 0xc83c, 0xa37f, 0xc83c, 0x21, 0 - .dw 0xa3c0, 0xc83c, 0xa3ff, 0xc83c, 0x21, 0 - .dw 0xa440, 0xc83c, 0xa47f, 0xc83c, 0x21, 0 - .dw 0xa4c0, 0xc83c, 0xa4ff, 0xc83c, 0x21, 0 - .dw 0xa540, 0xc83c, 0xa57f, 0xc83c, 0x21, 0 - .dw 0xa5c0, 0xc83c, 0xa5ff, 0xc83c, 0x21, 0 - .dw 0xa640, 0xc83c, 0xa67f, 0xc83c, 0x21, 0 - .dw 0xa6c0, 0xc83c, 0xa6ff, 0xc83c, 0x21, 0 - .dw 0xa740, 0xc83c, 0xa77f, 0xc83c, 0x21, 0 - .dw 0xa7c0, 0xc83c, 0xa7ff, 0xc83c, 0x21, 0 - .dw 0xa840, 0xc83c, 0xa87f, 0xc83c, 0x21, 0 - .dw 0xa8c0, 0xc83c, 0xa8ff, 0xc83c, 0x21, 0 - .dw 0xa940, 0xc83c, 0xa97f, 0xc83c, 0x21, 0 - .dw 0xa9c0, 0xc83c, 0xa9ff, 0xc83c, 0x21, 0 - .dw 0xaa40, 0xc83c, 0xaa7f, 0xc83c, 0x21, 0 - .dw 0xaac0, 0xc83c, 0xaaff, 0xc83c, 0x21, 0 - .dw 0xab40, 0xc83c, 0xab7f, 0xc83c, 0x21, 0 - .dw 0xabc0, 0xc83c, 0xabff, 0xc83c, 0x21, 0 - .dw 0xac40, 0xc83c, 0xac7f, 0xc83c, 0x21, 0 - .dw 0xacc0, 0xc83c, 0xacff, 0xc83c, 0x21, 0 - .dw 0xad40, 0xc83c, 0xad7f, 0xc83c, 0x21, 0 - .dw 0xadc0, 0xc83c, 0xadff, 0xc83c, 0x21, 0 - .dw 0xae40, 0xc83c, 0xae7f, 0xc83c, 0x21, 0 - .dw 0xaec0, 0xc83c, 0xaeff, 0xc83c, 0x21, 0 - .dw 0xaf40, 0xc83c, 0xaf7f, 0xc83c, 0x21, 0 - .dw 0xafc0, 0xc83c, 0xafff, 0xc83c, 0x21, 0 - .dw 0xb040, 0xc83c, 0xb07f, 0xc83c, 0x21, 0 - .dw 0xb0c0, 0xc83c, 0xb0ff, 0xc83c, 0x21, 0 - .dw 0xb140, 0xc83c, 0xb17f, 0xc83c, 0x21, 0 - .dw 0xb1c0, 0xc83c, 0xb1ff, 0xc83c, 0x21, 0 - .dw 0xb240, 0xc83c, 0xb27f, 0xc83c, 0x21, 0 - .dw 0xb2c0, 0xc83c, 0xb2ff, 0xc83c, 0x21, 0 - .dw 0xb340, 0xc83c, 0xb37f, 0xc83c, 0x21, 0 - .dw 0xb3c0, 0xc83c, 0xb3ff, 0xc83c, 0x21, 0 - .dw 0xb440, 0xc83c, 0xb47f, 0xc83c, 0x21, 0 - .dw 0xb4c0, 0xc83c, 0xb4ff, 0xc83c, 0x21, 0 - .dw 0xb540, 0xc83c, 0xb57f, 0xc83c, 0x21, 0 - .dw 0xb5c0, 0xc83c, 0xb5ff, 0xc83c, 0x21, 0 - .dw 0xb640, 0xc83c, 0xb67f, 0xc83c, 0x21, 0 - .dw 0xb6c0, 0xc83c, 0xb6ff, 0xc83c, 0x21, 0 - .dw 0xb740, 0xc83c, 0xb77f, 0xc83c, 0x21, 0 - .dw 0xb7c0, 0xc83c, 0xb7ff, 0xc83c, 0x21, 0 - .dw 0xb840, 0xc83c, 0xb87f, 0xc83c, 0x21, 0 - .dw 0xb8c0, 0xc83c, 0xb8ff, 0xc83c, 0x21, 0 - .dw 0xb940, 0xc83c, 0xb97f, 0xc83c, 0x21, 0 - .dw 0xb9c0, 0xc83c, 0xbfff, 0xc83c, 0x21, 0 - .dw 0xc040, 0xc83c, 0xc07f, 0xc83c, 0x21, 0 - .dw 0xc0c0, 0xc83c, 0xc0ff, 0xc83c, 0x21, 0 - .dw 0xc140, 0xc83c, 0xc17f, 0xc83c, 0x21, 0 - .dw 0xc1c0, 0xc83c, 0xc1ff, 0xc83c, 0x21, 0 - .dw 0xc240, 0xc83c, 0xc27f, 0xc83c, 0x21, 0 - .dw 0xc2c0, 0xc83c, 0xc2ff, 0xc83c, 0x21, 0 - .dw 0xc340, 0xc83c, 0xc37f, 0xc83c, 0x21, 0 - .dw 0xc3c0, 0xc83c, 0xc3ff, 0xc83c, 0x21, 0 - .dw 0xc440, 0xc83c, 0xc47f, 0xc83c, 0x21, 0 - .dw 0xc4c0, 0xc83c, 0xc4ff, 0xc83c, 0x21, 0 - .dw 0xc540, 0xc83c, 0xc57f, 0xc83c, 0x21, 0 - .dw 0xc5c0, 0xc83c, 0xc5ff, 0xc83c, 0x21, 0 - .dw 0xc640, 0xc83c, 0xc67f, 0xc83c, 0x21, 0 - .dw 0xc6c0, 0xc83c, 0xc6ff, 0xc83c, 0x21, 0 - .dw 0xc740, 0xc83c, 0xc77f, 0xc83c, 0x21, 0 - .dw 0xc7c0, 0xc83c, 0xc7ff, 0xc83c, 0x21, 0 - .dw 0xc840, 0xc83c, 0xc87f, 0xc83c, 0x21, 0 - .dw 0xc8c0, 0xc83c, 0xc8ff, 0xc83c, 0x21, 0 - .dw 0xc940, 0xc83c, 0xc97f, 0xc83c, 0x21, 0 - .dw 0xc9c0, 0xc83c, 0xc9ff, 0xc83c, 0x21, 0 - .dw 0xca40, 0xc83c, 0xca7f, 0xc83c, 0x21, 0 - .dw 0xcac0, 0xc83c, 0xcaff, 0xc83c, 0x21, 0 - .dw 0xcb40, 0xc83c, 0xcb7f, 0xc83c, 0x21, 0 - .dw 0xcbc0, 0xc83c, 0xcbff, 0xc83c, 0x21, 0 - .dw 0xcc40, 0xc83c, 0xcc7f, 0xc83c, 0x21, 0 - .dw 0xccc0, 0xc83c, 0xccff, 0xc83c, 0x21, 0 - .dw 0xcd40, 0xc83c, 0xcd7f, 0xc83c, 0x21, 0 - .dw 0xcdc0, 0xc83c, 0xcdff, 0xc83c, 0x21, 0 - .dw 0xce40, 0xc83c, 0xce7f, 0xc83c, 0x21, 0 - .dw 0xcec0, 0xc83c, 0xceff, 0xc83c, 0x21, 0 - .dw 0xcf40, 0xc83c, 0xcf7f, 0xc83c, 0x21, 0 - .dw 0xcfc0, 0xc83c, 0xcfff, 0xc83c, 0x21, 0 - .dw 0xd040, 0xc83c, 0xd07f, 0xc83c, 0x21, 0 - .dw 0xd0c0, 0xc83c, 0xd0ff, 0xc83c, 0x21, 0 - .dw 0xd140, 0xc83c, 0xd17f, 0xc83c, 0x21, 0 - .dw 0xd1c0, 0xc83c, 0xd1ff, 0xc83c, 0x21, 0 - .dw 0xd240, 0xc83c, 0xd27f, 0xc83c, 0x21, 0 - .dw 0xd2c0, 0xc83c, 0xd2ff, 0xc83c, 0x21, 0 - .dw 0xd340, 0xc83c, 0xd37f, 0xc83c, 0x21, 0 - .dw 0xd3c0, 0xc83c, 0xd3ff, 0xc83c, 0x21, 0 - .dw 0xd440, 0xc83c, 0xd47f, 0xc83c, 0x21, 0 - .dw 0xd4c0, 0xc83c, 0xd4ff, 0xc83c, 0x21, 0 - .dw 0xd540, 0xc83c, 0xd57f, 0xc83c, 0x21, 0 - .dw 0xd5c0, 0xc83c, 0xd5ff, 0xc83c, 0x21, 0 - .dw 0xd640, 0xc83c, 0xd67f, 0xc83c, 0x21, 0 - .dw 0xd6c0, 0xc83c, 0xd6ff, 0xc83c, 0x21, 0 - .dw 0xd740, 0xc83c, 0xd77f, 0xc83c, 0x21, 0 - .dw 0xd7c0, 0xc83c, 0xd7ff, 0xc83c, 0x21, 0 - .dw 0xd840, 0xc83c, 0xd87f, 0xc83c, 0x21, 0 - .dw 0xd8c0, 0xc83c, 0xd8ff, 0xc83c, 0x21, 0 - .dw 0xd940, 0xc83c, 0xd97f, 0xc83c, 0x21, 0 - .dw 0xd9c0, 0xc83c, 0xdfff, 0xc83c, 0x21, 0 - .dw 0xe040, 0xc83c, 0xe07f, 0xc83c, 0x21, 0 - .dw 0xe0c0, 0xc83c, 0xe0ff, 0xc83c, 0x21, 0 - .dw 0xe140, 0xc83c, 0xe17f, 0xc83c, 0x21, 0 - .dw 0xe1c0, 0xc83c, 0xe1ff, 0xc83c, 0x21, 0 - .dw 0xe240, 0xc83c, 0xe27f, 0xc83c, 0x21, 0 - .dw 0xe2c0, 0xc83c, 0xe2ff, 0xc83c, 0x21, 0 - .dw 0xe340, 0xc83c, 0xe37f, 0xc83c, 0x21, 0 - .dw 0xe3c0, 0xc83c, 0xe3ff, 0xc83c, 0x21, 0 - .dw 0xe440, 0xc83c, 0xe47f, 0xc83c, 0x21, 0 - .dw 0xe4c0, 0xc83c, 0xe4ff, 0xc83c, 0x21, 0 - .dw 0xe540, 0xc83c, 0xe57f, 0xc83c, 0x21, 0 - .dw 0xe5c0, 0xc83c, 0xe5ff, 0xc83c, 0x21, 0 - .dw 0xe640, 0xc83c, 0xe67f, 0xc83c, 0x21, 0 - .dw 0xe6c0, 0xc83c, 0xe6ff, 0xc83c, 0x21, 0 - .dw 0xe740, 0xc83c, 0xe77f, 0xc83c, 0x21, 0 - .dw 0xe7c0, 0xc83c, 0xe7ff, 0xc83c, 0x21, 0 - .dw 0xe840, 0xc83c, 0xe87f, 0xc83c, 0x21, 0 - .dw 0xe8c0, 0xc83c, 0xe8ff, 0xc83c, 0x21, 0 - .dw 0xe940, 0xc83c, 0xe97f, 0xc83c, 0x21, 0 - .dw 0xe9c0, 0xc83c, 0xe9ff, 0xc83c, 0x21, 0 - .dw 0xea40, 0xc83c, 0xea7f, 0xc83c, 0x21, 0 - .dw 0xeac0, 0xc83c, 0xeaff, 0xc83c, 0x21, 0 - .dw 0xeb40, 0xc83c, 0xeb7f, 0xc83c, 0x21, 0 - .dw 0xebc0, 0xc83c, 0xebff, 0xc83c, 0x21, 0 - .dw 0xec40, 0xc83c, 0xec7f, 0xc83c, 0x21, 0 - .dw 0xecc0, 0xc83c, 0xecff, 0xc83c, 0x21, 0 - .dw 0xed40, 0xc83c, 0xed7f, 0xc83c, 0x21, 0 - .dw 0xedc0, 0xc83c, 0xedff, 0xc83c, 0x21, 0 - .dw 0xee40, 0xc83c, 0xee7f, 0xc83c, 0x21, 0 - .dw 0xeec0, 0xc83c, 0xeeff, 0xc83c, 0x21, 0 - .dw 0xef40, 0xc83c, 0xef7f, 0xc83c, 0x21, 0 - .dw 0xefc0, 0xc83c, 0xefff, 0xc83c, 0x21, 0 - .dw 0xf040, 0xc83c, 0xf07f, 0xc83c, 0x21, 0 - .dw 0xf0c0, 0xc83c, 0xf0ff, 0xc83c, 0x21, 0 - .dw 0xf140, 0xc83c, 0xf17f, 0xc83c, 0x21, 0 - .dw 0xf1c0, 0xc83c, 0xf1ff, 0xc83c, 0x21, 0 - .dw 0xf240, 0xc83c, 0xf27f, 0xc83c, 0x21, 0 - .dw 0xf2c0, 0xc83c, 0xf2ff, 0xc83c, 0x21, 0 - .dw 0xf340, 0xc83c, 0xf37f, 0xc83c, 0x21, 0 - .dw 0xf3c0, 0xc83c, 0xf3ff, 0xc83c, 0x21, 0 - .dw 0xf440, 0xc83c, 0xf47f, 0xc83c, 0x21, 0 - .dw 0xf4c0, 0xc83c, 0xf4ff, 0xc83c, 0x21, 0 - .dw 0xf540, 0xc83c, 0xf57f, 0xc83c, 0x21, 0 - .dw 0xf5c0, 0xc83c, 0xf5ff, 0xc83c, 0x21, 0 - .dw 0xf640, 0xc83c, 0xf67f, 0xc83c, 0x21, 0 - .dw 0xf6c0, 0xc83c, 0xf6ff, 0xc83c, 0x21, 0 - .dw 0xf740, 0xc83c, 0xf77f, 0xc83c, 0x21, 0 - .dw 0xf7c0, 0xc83c, 0xf7ff, 0xc83c, 0x21, 0 - .dw 0xf840, 0xc83c, 0xf87f, 0xc83c, 0x21, 0 - .dw 0xf8c0, 0xc83c, 0xf8ff, 0xc83c, 0x21, 0 - .dw 0xf940, 0xc83c, 0xf97f, 0xc83c, 0x21, 0 - .dw 0xf9c0, 0xc83c, 0xffff, 0xc83c, 0x21, 0 - .dw 0x0040, 0xc83d, 0x007f, 0xc83d, 0x21, 0 - .dw 0x00c0, 0xc83d, 0x00ff, 0xc83d, 0x21, 0 - .dw 0x0140, 0xc83d, 0x017f, 0xc83d, 0x21, 0 - .dw 0x01c0, 0xc83d, 0x01ff, 0xc83d, 0x21, 0 - .dw 0x0240, 0xc83d, 0x027f, 0xc83d, 0x21, 0 - .dw 0x02c0, 0xc83d, 0x02ff, 0xc83d, 0x21, 0 - .dw 0x0340, 0xc83d, 0x037f, 0xc83d, 0x21, 0 - .dw 0x03c0, 0xc83d, 0x03ff, 0xc83d, 0x21, 0 - .dw 0x0440, 0xc83d, 0x047f, 0xc83d, 0x21, 0 - .dw 0x04c0, 0xc83d, 0x04ff, 0xc83d, 0x21, 0 - .dw 0x0540, 0xc83d, 0x057f, 0xc83d, 0x21, 0 - .dw 0x05c0, 0xc83d, 0x05ff, 0xc83d, 0x21, 0 - .dw 0x0640, 0xc83d, 0x067f, 0xc83d, 0x21, 0 - .dw 0x06c0, 0xc83d, 0x06ff, 0xc83d, 0x21, 0 - .dw 0x0740, 0xc83d, 0x077f, 0xc83d, 0x21, 0 - .dw 0x07c0, 0xc83d, 0x07ff, 0xc83d, 0x21, 0 - .dw 0x0840, 0xc83d, 0x087f, 0xc83d, 0x21, 0 - .dw 0x08c0, 0xc83d, 0x08ff, 0xc83d, 0x21, 0 - .dw 0x0940, 0xc83d, 0x097f, 0xc83d, 0x21, 0 - .dw 0x09c0, 0xc83d, 0x09ff, 0xc83d, 0x21, 0 - .dw 0x0a40, 0xc83d, 0x0a7f, 0xc83d, 0x21, 0 - .dw 0x0ac0, 0xc83d, 0x0aff, 0xc83d, 0x21, 0 - .dw 0x0b40, 0xc83d, 0x0b7f, 0xc83d, 0x21, 0 - .dw 0x0bc0, 0xc83d, 0x0bff, 0xc83d, 0x21, 0 - .dw 0x0c40, 0xc83d, 0x0c7f, 0xc83d, 0x21, 0 - .dw 0x0cc0, 0xc83d, 0x0cff, 0xc83d, 0x21, 0 - .dw 0x0d40, 0xc83d, 0x0d7f, 0xc83d, 0x21, 0 - .dw 0x0dc0, 0xc83d, 0x0dff, 0xc83d, 0x21, 0 - .dw 0x0e40, 0xc83d, 0x0e7f, 0xc83d, 0x21, 0 - .dw 0x0ec0, 0xc83d, 0x0eff, 0xc83d, 0x21, 0 - .dw 0x0f40, 0xc83d, 0x0f7f, 0xc83d, 0x21, 0 - .dw 0x0fc0, 0xc83d, 0x0fff, 0xc83d, 0x21, 0 - .dw 0x1040, 0xc83d, 0x107f, 0xc83d, 0x21, 0 - .dw 0x10c0, 0xc83d, 0x10ff, 0xc83d, 0x21, 0 - .dw 0x1140, 0xc83d, 0x117f, 0xc83d, 0x21, 0 - .dw 0x11c0, 0xc83d, 0x11ff, 0xc83d, 0x21, 0 - .dw 0x1240, 0xc83d, 0x127f, 0xc83d, 0x21, 0 - .dw 0x12c0, 0xc83d, 0x12ff, 0xc83d, 0x21, 0 - .dw 0x1340, 0xc83d, 0x137f, 0xc83d, 0x21, 0 - .dw 0x13c0, 0xc83d, 0x13ff, 0xc83d, 0x21, 0 - .dw 0x1440, 0xc83d, 0x147f, 0xc83d, 0x21, 0 - .dw 0x14c0, 0xc83d, 0x14ff, 0xc83d, 0x21, 0 - .dw 0x1540, 0xc83d, 0x157f, 0xc83d, 0x21, 0 - .dw 0x15c0, 0xc83d, 0x15ff, 0xc83d, 0x21, 0 - .dw 0x1640, 0xc83d, 0x167f, 0xc83d, 0x21, 0 - .dw 0x16c0, 0xc83d, 0x16ff, 0xc83d, 0x21, 0 - .dw 0x1740, 0xc83d, 0x177f, 0xc83d, 0x21, 0 - .dw 0x17c0, 0xc83d, 0x17ff, 0xc83d, 0x21, 0 - .dw 0x1840, 0xc83d, 0x187f, 0xc83d, 0x21, 0 - .dw 0x18c0, 0xc83d, 0x18ff, 0xc83d, 0x21, 0 - .dw 0x1940, 0xc83d, 0x197f, 0xc83d, 0x21, 0 - .dw 0x19c0, 0xc83d, 0x1fff, 0xc83d, 0x21, 0 - .dw 0x2040, 0xc83d, 0x207f, 0xc83d, 0x21, 0 - .dw 0x20c0, 0xc83d, 0x20ff, 0xc83d, 0x21, 0 - .dw 0x2140, 0xc83d, 0x217f, 0xc83d, 0x21, 0 - .dw 0x21c0, 0xc83d, 0x21ff, 0xc83d, 0x21, 0 - .dw 0x2240, 0xc83d, 0x227f, 0xc83d, 0x21, 0 - .dw 0x22c0, 0xc83d, 0x22ff, 0xc83d, 0x21, 0 - .dw 0x2340, 0xc83d, 0x237f, 0xc83d, 0x21, 0 - .dw 0x23c0, 0xc83d, 0x23ff, 0xc83d, 0x21, 0 - .dw 0x2440, 0xc83d, 0x247f, 0xc83d, 0x21, 0 - .dw 0x24c0, 0xc83d, 0x24ff, 0xc83d, 0x21, 0 - .dw 0x2540, 0xc83d, 0x257f, 0xc83d, 0x21, 0 - .dw 0x25c0, 0xc83d, 0x25ff, 0xc83d, 0x21, 0 - .dw 0x2640, 0xc83d, 0x267f, 0xc83d, 0x21, 0 - .dw 0x26c0, 0xc83d, 0x26ff, 0xc83d, 0x21, 0 - .dw 0x2740, 0xc83d, 0x277f, 0xc83d, 0x21, 0 - .dw 0x27c0, 0xc83d, 0x27ff, 0xc83d, 0x21, 0 - .dw 0x2840, 0xc83d, 0x287f, 0xc83d, 0x21, 0 - .dw 0x28c0, 0xc83d, 0x28ff, 0xc83d, 0x21, 0 - .dw 0x2940, 0xc83d, 0x297f, 0xc83d, 0x21, 0 - .dw 0x29c0, 0xc83d, 0x29ff, 0xc83d, 0x21, 0 - .dw 0x2a40, 0xc83d, 0x2a7f, 0xc83d, 0x21, 0 - .dw 0x2ac0, 0xc83d, 0x2aff, 0xc83d, 0x21, 0 - .dw 0x2b40, 0xc83d, 0x2b7f, 0xc83d, 0x21, 0 - .dw 0x2bc0, 0xc83d, 0x2bff, 0xc83d, 0x21, 0 - .dw 0x2c40, 0xc83d, 0x2c7f, 0xc83d, 0x21, 0 - .dw 0x2cc0, 0xc83d, 0x2cff, 0xc83d, 0x21, 0 - .dw 0x2d40, 0xc83d, 0x2d7f, 0xc83d, 0x21, 0 - .dw 0x2dc0, 0xc83d, 0x2dff, 0xc83d, 0x21, 0 - .dw 0x2e40, 0xc83d, 0x2e7f, 0xc83d, 0x21, 0 - .dw 0x2ec0, 0xc83d, 0x2eff, 0xc83d, 0x21, 0 - .dw 0x2f40, 0xc83d, 0x2f7f, 0xc83d, 0x21, 0 - .dw 0x2fc0, 0xc83d, 0x2fff, 0xc83d, 0x21, 0 - .dw 0x3040, 0xc83d, 0x307f, 0xc83d, 0x21, 0 - .dw 0x30c0, 0xc83d, 0x30ff, 0xc83d, 0x21, 0 - .dw 0x3140, 0xc83d, 0x317f, 0xc83d, 0x21, 0 - .dw 0x31c0, 0xc83d, 0x31ff, 0xc83d, 0x21, 0 - .dw 0x3240, 0xc83d, 0x327f, 0xc83d, 0x21, 0 - .dw 0x32c0, 0xc83d, 0x32ff, 0xc83d, 0x21, 0 - .dw 0x3340, 0xc83d, 0x337f, 0xc83d, 0x21, 0 - .dw 0x33c0, 0xc83d, 0x33ff, 0xc83d, 0x21, 0 - .dw 0x3440, 0xc83d, 0x347f, 0xc83d, 0x21, 0 - .dw 0x34c0, 0xc83d, 0x34ff, 0xc83d, 0x21, 0 - .dw 0x3540, 0xc83d, 0x357f, 0xc83d, 0x21, 0 - .dw 0x35c0, 0xc83d, 0x35ff, 0xc83d, 0x21, 0 - .dw 0x3640, 0xc83d, 0x367f, 0xc83d, 0x21, 0 - .dw 0x36c0, 0xc83d, 0x36ff, 0xc83d, 0x21, 0 - .dw 0x3740, 0xc83d, 0x377f, 0xc83d, 0x21, 0 - .dw 0x37c0, 0xc83d, 0x37ff, 0xc83d, 0x21, 0 - .dw 0x3840, 0xc83d, 0x387f, 0xc83d, 0x21, 0 - .dw 0x38c0, 0xc83d, 0x38ff, 0xc83d, 0x21, 0 - .dw 0x3940, 0xc83d, 0x397f, 0xc83d, 0x21, 0 - .dw 0x39c0, 0xc83d, 0x3fff, 0xc83d, 0x21, 0 - .dw 0x4040, 0xc83d, 0x407f, 0xc83d, 0x21, 0 - .dw 0x40c0, 0xc83d, 0x40ff, 0xc83d, 0x21, 0 - .dw 0x4140, 0xc83d, 0x417f, 0xc83d, 0x21, 0 - .dw 0x41c0, 0xc83d, 0x41ff, 0xc83d, 0x21, 0 - .dw 0x4240, 0xc83d, 0x427f, 0xc83d, 0x21, 0 - .dw 0x42c0, 0xc83d, 0x42ff, 0xc83d, 0x21, 0 - .dw 0x4340, 0xc83d, 0x437f, 0xc83d, 0x21, 0 - .dw 0x43c0, 0xc83d, 0x43ff, 0xc83d, 0x21, 0 - .dw 0x4440, 0xc83d, 0x447f, 0xc83d, 0x21, 0 - .dw 0x44c0, 0xc83d, 0x44ff, 0xc83d, 0x21, 0 - .dw 0x4540, 0xc83d, 0x457f, 0xc83d, 0x21, 0 - .dw 0x45c0, 0xc83d, 0x45ff, 0xc83d, 0x21, 0 - .dw 0x4640, 0xc83d, 0x467f, 0xc83d, 0x21, 0 - .dw 0x46c0, 0xc83d, 0x46ff, 0xc83d, 0x21, 0 - .dw 0x4740, 0xc83d, 0x477f, 0xc83d, 0x21, 0 - .dw 0x47c0, 0xc83d, 0x47ff, 0xc83d, 0x21, 0 - .dw 0x4840, 0xc83d, 0x487f, 0xc83d, 0x21, 0 - .dw 0x48c0, 0xc83d, 0x48ff, 0xc83d, 0x21, 0 - .dw 0x4940, 0xc83d, 0x497f, 0xc83d, 0x21, 0 - .dw 0x49c0, 0xc83d, 0x49ff, 0xc83d, 0x21, 0 - .dw 0x4a40, 0xc83d, 0x4a7f, 0xc83d, 0x21, 0 - .dw 0x4ac0, 0xc83d, 0x4aff, 0xc83d, 0x21, 0 - .dw 0x4b40, 0xc83d, 0x4b7f, 0xc83d, 0x21, 0 - .dw 0x4bc0, 0xc83d, 0x4bff, 0xc83d, 0x21, 0 - .dw 0x4c40, 0xc83d, 0x4c7f, 0xc83d, 0x21, 0 - .dw 0x4cc0, 0xc83d, 0x4cff, 0xc83d, 0x21, 0 - .dw 0x4d40, 0xc83d, 0x4d7f, 0xc83d, 0x21, 0 - .dw 0x4dc0, 0xc83d, 0x4dff, 0xc83d, 0x21, 0 - .dw 0x4e40, 0xc83d, 0x4e7f, 0xc83d, 0x21, 0 - .dw 0x4ec0, 0xc83d, 0x4eff, 0xc83d, 0x21, 0 - .dw 0x4f40, 0xc83d, 0x4f7f, 0xc83d, 0x21, 0 - .dw 0x4fc0, 0xc83d, 0x4fff, 0xc83d, 0x21, 0 - .dw 0x5040, 0xc83d, 0x507f, 0xc83d, 0x21, 0 - .dw 0x50c0, 0xc83d, 0x50ff, 0xc83d, 0x21, 0 - .dw 0x5140, 0xc83d, 0x517f, 0xc83d, 0x21, 0 - .dw 0x51c0, 0xc83d, 0x51ff, 0xc83d, 0x21, 0 - .dw 0x5240, 0xc83d, 0x527f, 0xc83d, 0x21, 0 - .dw 0x52c0, 0xc83d, 0x52ff, 0xc83d, 0x21, 0 - .dw 0x5340, 0xc83d, 0x537f, 0xc83d, 0x21, 0 - .dw 0x53c0, 0xc83d, 0x53ff, 0xc83d, 0x21, 0 - .dw 0x5440, 0xc83d, 0x547f, 0xc83d, 0x21, 0 - .dw 0x54c0, 0xc83d, 0x54ff, 0xc83d, 0x21, 0 - .dw 0x5540, 0xc83d, 0x557f, 0xc83d, 0x21, 0 - .dw 0x55c0, 0xc83d, 0x55ff, 0xc83d, 0x21, 0 - .dw 0x5640, 0xc83d, 0x567f, 0xc83d, 0x21, 0 - .dw 0x56c0, 0xc83d, 0x56ff, 0xc83d, 0x21, 0 - .dw 0x5740, 0xc83d, 0x577f, 0xc83d, 0x21, 0 - .dw 0x57c0, 0xc83d, 0x57ff, 0xc83d, 0x21, 0 - .dw 0x5840, 0xc83d, 0x587f, 0xc83d, 0x21, 0 - .dw 0x58c0, 0xc83d, 0x58ff, 0xc83d, 0x21, 0 - .dw 0x5940, 0xc83d, 0x597f, 0xc83d, 0x21, 0 - .dw 0x59c0, 0xc83d, 0x5fff, 0xc83d, 0x21, 0 - .dw 0x6040, 0xc83d, 0x607f, 0xc83d, 0x21, 0 - .dw 0x60c0, 0xc83d, 0x60ff, 0xc83d, 0x21, 0 - .dw 0x6140, 0xc83d, 0x617f, 0xc83d, 0x21, 0 - .dw 0x61c0, 0xc83d, 0x61ff, 0xc83d, 0x21, 0 - .dw 0x6240, 0xc83d, 0x627f, 0xc83d, 0x21, 0 - .dw 0x62c0, 0xc83d, 0x62ff, 0xc83d, 0x21, 0 - .dw 0x6340, 0xc83d, 0x637f, 0xc83d, 0x21, 0 - .dw 0x63c0, 0xc83d, 0x63ff, 0xc83d, 0x21, 0 - .dw 0x6440, 0xc83d, 0x647f, 0xc83d, 0x21, 0 - .dw 0x64c0, 0xc83d, 0x64ff, 0xc83d, 0x21, 0 - .dw 0x6540, 0xc83d, 0x657f, 0xc83d, 0x21, 0 - .dw 0x65c0, 0xc83d, 0x65ff, 0xc83d, 0x21, 0 - .dw 0x6640, 0xc83d, 0x667f, 0xc83d, 0x21, 0 - .dw 0x66c0, 0xc83d, 0x66ff, 0xc83d, 0x21, 0 - .dw 0x6740, 0xc83d, 0x677f, 0xc83d, 0x21, 0 - .dw 0x67c0, 0xc83d, 0x67ff, 0xc83d, 0x21, 0 - .dw 0x6840, 0xc83d, 0x687f, 0xc83d, 0x21, 0 - .dw 0x68c0, 0xc83d, 0x68ff, 0xc83d, 0x21, 0 - .dw 0x6940, 0xc83d, 0x697f, 0xc83d, 0x21, 0 - .dw 0x69c0, 0xc83d, 0x69ff, 0xc83d, 0x21, 0 - .dw 0x6a40, 0xc83d, 0x6a7f, 0xc83d, 0x21, 0 - .dw 0x6ac0, 0xc83d, 0x6aff, 0xc83d, 0x21, 0 - .dw 0x6b40, 0xc83d, 0x6b7f, 0xc83d, 0x21, 0 - .dw 0x6bc0, 0xc83d, 0x6bff, 0xc83d, 0x21, 0 - .dw 0x6c40, 0xc83d, 0x6c7f, 0xc83d, 0x21, 0 - .dw 0x6cc0, 0xc83d, 0x6cff, 0xc83d, 0x21, 0 - .dw 0x6d40, 0xc83d, 0x6d7f, 0xc83d, 0x21, 0 - .dw 0x6dc0, 0xc83d, 0x6dff, 0xc83d, 0x21, 0 - .dw 0x6e40, 0xc83d, 0x6e7f, 0xc83d, 0x21, 0 - .dw 0x6ec0, 0xc83d, 0x6eff, 0xc83d, 0x21, 0 - .dw 0x6f40, 0xc83d, 0x6f7f, 0xc83d, 0x21, 0 - .dw 0x6fc0, 0xc83d, 0x6fff, 0xc83d, 0x21, 0 - .dw 0x7040, 0xc83d, 0x707f, 0xc83d, 0x21, 0 - .dw 0x70c0, 0xc83d, 0x70ff, 0xc83d, 0x21, 0 - .dw 0x7140, 0xc83d, 0x717f, 0xc83d, 0x21, 0 - .dw 0x71c0, 0xc83d, 0x71ff, 0xc83d, 0x21, 0 - .dw 0x7240, 0xc83d, 0x727f, 0xc83d, 0x21, 0 - .dw 0x72c0, 0xc83d, 0x72ff, 0xc83d, 0x21, 0 - .dw 0x7340, 0xc83d, 0x737f, 0xc83d, 0x21, 0 - .dw 0x73c0, 0xc83d, 0x73ff, 0xc83d, 0x21, 0 - .dw 0x7440, 0xc83d, 0x747f, 0xc83d, 0x21, 0 - .dw 0x74c0, 0xc83d, 0x74ff, 0xc83d, 0x21, 0 - .dw 0x7540, 0xc83d, 0x757f, 0xc83d, 0x21, 0 - .dw 0x75c0, 0xc83d, 0x75ff, 0xc83d, 0x21, 0 - .dw 0x7640, 0xc83d, 0x767f, 0xc83d, 0x21, 0 - .dw 0x76c0, 0xc83d, 0x76ff, 0xc83d, 0x21, 0 - .dw 0x7740, 0xc83d, 0x777f, 0xc83d, 0x21, 0 - .dw 0x77c0, 0xc83d, 0x77ff, 0xc83d, 0x21, 0 - .dw 0x7840, 0xc83d, 0x787f, 0xc83d, 0x21, 0 - .dw 0x78c0, 0xc83d, 0x78ff, 0xc83d, 0x21, 0 - .dw 0x7940, 0xc83d, 0x797f, 0xc83d, 0x21, 0 - .dw 0x79c0, 0xc83d, 0x7fff, 0xc83d, 0x21, 0 - .dw 0x8040, 0xc83d, 0x807f, 0xc83d, 0x21, 0 - .dw 0x80c0, 0xc83d, 0x80ff, 0xc83d, 0x21, 0 - .dw 0x8140, 0xc83d, 0x817f, 0xc83d, 0x21, 0 - .dw 0x81c0, 0xc83d, 0x81ff, 0xc83d, 0x21, 0 - .dw 0x8240, 0xc83d, 0x827f, 0xc83d, 0x21, 0 - .dw 0x82c0, 0xc83d, 0x82ff, 0xc83d, 0x21, 0 - .dw 0x8340, 0xc83d, 0x837f, 0xc83d, 0x21, 0 - .dw 0x83c0, 0xc83d, 0x83ff, 0xc83d, 0x21, 0 - .dw 0x8440, 0xc83d, 0x847f, 0xc83d, 0x21, 0 - .dw 0x84c0, 0xc83d, 0x84ff, 0xc83d, 0x21, 0 - .dw 0x8540, 0xc83d, 0x857f, 0xc83d, 0x21, 0 - .dw 0x85c0, 0xc83d, 0x85ff, 0xc83d, 0x21, 0 - .dw 0x8640, 0xc83d, 0x867f, 0xc83d, 0x21, 0 - .dw 0x86c0, 0xc83d, 0x86ff, 0xc83d, 0x21, 0 - .dw 0x8740, 0xc83d, 0x877f, 0xc83d, 0x21, 0 - .dw 0x87c0, 0xc83d, 0x87ff, 0xc83d, 0x21, 0 - .dw 0x8840, 0xc83d, 0x887f, 0xc83d, 0x21, 0 - .dw 0x88c0, 0xc83d, 0x88ff, 0xc83d, 0x21, 0 - .dw 0x8940, 0xc83d, 0x897f, 0xc83d, 0x21, 0 - .dw 0x89c0, 0xc83d, 0x89ff, 0xc83d, 0x21, 0 - .dw 0x8a40, 0xc83d, 0x8a7f, 0xc83d, 0x21, 0 - .dw 0x8ac0, 0xc83d, 0x8aff, 0xc83d, 0x21, 0 - .dw 0x8b40, 0xc83d, 0x8b7f, 0xc83d, 0x21, 0 - .dw 0x8bc0, 0xc83d, 0x8bff, 0xc83d, 0x21, 0 - .dw 0x8c40, 0xc83d, 0x8c7f, 0xc83d, 0x21, 0 - .dw 0x8cc0, 0xc83d, 0x8cff, 0xc83d, 0x21, 0 - .dw 0x8d40, 0xc83d, 0x8d7f, 0xc83d, 0x21, 0 - .dw 0x8dc0, 0xc83d, 0x8dff, 0xc83d, 0x21, 0 - .dw 0x8e40, 0xc83d, 0x8e7f, 0xc83d, 0x21, 0 - .dw 0x8ec0, 0xc83d, 0x8eff, 0xc83d, 0x21, 0 - .dw 0x8f40, 0xc83d, 0x8f7f, 0xc83d, 0x21, 0 - .dw 0x8fc0, 0xc83d, 0x8fff, 0xc83d, 0x21, 0 - .dw 0x9040, 0xc83d, 0x907f, 0xc83d, 0x21, 0 - .dw 0x90c0, 0xc83d, 0x90ff, 0xc83d, 0x21, 0 - .dw 0x9140, 0xc83d, 0x917f, 0xc83d, 0x21, 0 - .dw 0x91c0, 0xc83d, 0x91ff, 0xc83d, 0x21, 0 - .dw 0x9240, 0xc83d, 0x927f, 0xc83d, 0x21, 0 - .dw 0x92c0, 0xc83d, 0x92ff, 0xc83d, 0x21, 0 - .dw 0x9340, 0xc83d, 0x937f, 0xc83d, 0x21, 0 - .dw 0x93c0, 0xc83d, 0x93ff, 0xc83d, 0x21, 0 - .dw 0x9440, 0xc83d, 0x947f, 0xc83d, 0x21, 0 - .dw 0x94c0, 0xc83d, 0x94ff, 0xc83d, 0x21, 0 - .dw 0x9540, 0xc83d, 0x957f, 0xc83d, 0x21, 0 - .dw 0x95c0, 0xc83d, 0x95ff, 0xc83d, 0x21, 0 - .dw 0x9640, 0xc83d, 0x967f, 0xc83d, 0x21, 0 - .dw 0x96c0, 0xc83d, 0x96ff, 0xc83d, 0x21, 0 - .dw 0x9740, 0xc83d, 0x977f, 0xc83d, 0x21, 0 - .dw 0x97c0, 0xc83d, 0x97ff, 0xc83d, 0x21, 0 - .dw 0x9840, 0xc83d, 0x987f, 0xc83d, 0x21, 0 - .dw 0x98c0, 0xc83d, 0x98ff, 0xc83d, 0x21, 0 - .dw 0x9940, 0xc83d, 0x997f, 0xc83d, 0x21, 0 - .dw 0x99c0, 0xc83d, 0x9fff, 0xc83d, 0x21, 0 - .dw 0xa040, 0xc83d, 0xa07f, 0xc83d, 0x21, 0 - .dw 0xa0c0, 0xc83d, 0xa0ff, 0xc83d, 0x21, 0 - .dw 0xa140, 0xc83d, 0xa17f, 0xc83d, 0x21, 0 - .dw 0xa1c0, 0xc83d, 0xa1ff, 0xc83d, 0x21, 0 - .dw 0xa240, 0xc83d, 0xa27f, 0xc83d, 0x21, 0 - .dw 0xa2c0, 0xc83d, 0xa2ff, 0xc83d, 0x21, 0 - .dw 0xa340, 0xc83d, 0xa37f, 0xc83d, 0x21, 0 - .dw 0xa3c0, 0xc83d, 0xa3ff, 0xc83d, 0x21, 0 - .dw 0xa440, 0xc83d, 0xa47f, 0xc83d, 0x21, 0 - .dw 0xa4c0, 0xc83d, 0xa4ff, 0xc83d, 0x21, 0 - .dw 0xa540, 0xc83d, 0xa57f, 0xc83d, 0x21, 0 - .dw 0xa5c0, 0xc83d, 0xa5ff, 0xc83d, 0x21, 0 - .dw 0xa640, 0xc83d, 0xa67f, 0xc83d, 0x21, 0 - .dw 0xa6c0, 0xc83d, 0xa6ff, 0xc83d, 0x21, 0 - .dw 0xa740, 0xc83d, 0xa77f, 0xc83d, 0x21, 0 - .dw 0xa7c0, 0xc83d, 0xa7ff, 0xc83d, 0x21, 0 - .dw 0xa840, 0xc83d, 0xa87f, 0xc83d, 0x21, 0 - .dw 0xa8c0, 0xc83d, 0xa8ff, 0xc83d, 0x21, 0 - .dw 0xa940, 0xc83d, 0xa97f, 0xc83d, 0x21, 0 - .dw 0xa9c0, 0xc83d, 0xa9ff, 0xc83d, 0x21, 0 - .dw 0xaa40, 0xc83d, 0xaa7f, 0xc83d, 0x21, 0 - .dw 0xaac0, 0xc83d, 0xaaff, 0xc83d, 0x21, 0 - .dw 0xab40, 0xc83d, 0xab7f, 0xc83d, 0x21, 0 - .dw 0xabc0, 0xc83d, 0xabff, 0xc83d, 0x21, 0 - .dw 0xac40, 0xc83d, 0xac7f, 0xc83d, 0x21, 0 - .dw 0xacc0, 0xc83d, 0xacff, 0xc83d, 0x21, 0 - .dw 0xad40, 0xc83d, 0xad7f, 0xc83d, 0x21, 0 - .dw 0xadc0, 0xc83d, 0xadff, 0xc83d, 0x21, 0 - .dw 0xae40, 0xc83d, 0xae7f, 0xc83d, 0x21, 0 - .dw 0xaec0, 0xc83d, 0xaeff, 0xc83d, 0x21, 0 - .dw 0xaf40, 0xc83d, 0xaf7f, 0xc83d, 0x21, 0 - .dw 0xafc0, 0xc83d, 0xafff, 0xc83d, 0x21, 0 - .dw 0xb040, 0xc83d, 0xb07f, 0xc83d, 0x21, 0 - .dw 0xb0c0, 0xc83d, 0xb0ff, 0xc83d, 0x21, 0 - .dw 0xb140, 0xc83d, 0xb17f, 0xc83d, 0x21, 0 - .dw 0xb1c0, 0xc83d, 0xb1ff, 0xc83d, 0x21, 0 - .dw 0xb240, 0xc83d, 0xb27f, 0xc83d, 0x21, 0 - .dw 0xb2c0, 0xc83d, 0xb2ff, 0xc83d, 0x21, 0 - .dw 0xb340, 0xc83d, 0xb37f, 0xc83d, 0x21, 0 - .dw 0xb3c0, 0xc83d, 0xb3ff, 0xc83d, 0x21, 0 - .dw 0xb440, 0xc83d, 0xb47f, 0xc83d, 0x21, 0 - .dw 0xb4c0, 0xc83d, 0xb4ff, 0xc83d, 0x21, 0 - .dw 0xb540, 0xc83d, 0xb57f, 0xc83d, 0x21, 0 - .dw 0xb5c0, 0xc83d, 0xb5ff, 0xc83d, 0x21, 0 - .dw 0xb640, 0xc83d, 0xb67f, 0xc83d, 0x21, 0 - .dw 0xb6c0, 0xc83d, 0xb6ff, 0xc83d, 0x21, 0 - .dw 0xb740, 0xc83d, 0xb77f, 0xc83d, 0x21, 0 - .dw 0xb7c0, 0xc83d, 0xb7ff, 0xc83d, 0x21, 0 - .dw 0xb840, 0xc83d, 0xb87f, 0xc83d, 0x21, 0 - .dw 0xb8c0, 0xc83d, 0xb8ff, 0xc83d, 0x21, 0 - .dw 0xb940, 0xc83d, 0xb97f, 0xc83d, 0x21, 0 - .dw 0xb9c0, 0xc83d, 0xbfff, 0xc83d, 0x21, 0 - .dw 0xc040, 0xc83d, 0xc07f, 0xc83d, 0x21, 0 - .dw 0xc0c0, 0xc83d, 0xc0ff, 0xc83d, 0x21, 0 - .dw 0xc140, 0xc83d, 0xc17f, 0xc83d, 0x21, 0 - .dw 0xc1c0, 0xc83d, 0xc1ff, 0xc83d, 0x21, 0 - .dw 0xc240, 0xc83d, 0xc27f, 0xc83d, 0x21, 0 - .dw 0xc2c0, 0xc83d, 0xc2ff, 0xc83d, 0x21, 0 - .dw 0xc340, 0xc83d, 0xc37f, 0xc83d, 0x21, 0 - .dw 0xc3c0, 0xc83d, 0xc3ff, 0xc83d, 0x21, 0 - .dw 0xc440, 0xc83d, 0xc47f, 0xc83d, 0x21, 0 - .dw 0xc4c0, 0xc83d, 0xc4ff, 0xc83d, 0x21, 0 - .dw 0xc540, 0xc83d, 0xc57f, 0xc83d, 0x21, 0 - .dw 0xc5c0, 0xc83d, 0xc5ff, 0xc83d, 0x21, 0 - .dw 0xc640, 0xc83d, 0xc67f, 0xc83d, 0x21, 0 - .dw 0xc6c0, 0xc83d, 0xc6ff, 0xc83d, 0x21, 0 - .dw 0xc740, 0xc83d, 0xc77f, 0xc83d, 0x21, 0 - .dw 0xc7c0, 0xc83d, 0xc7ff, 0xc83d, 0x21, 0 - .dw 0xc840, 0xc83d, 0xc87f, 0xc83d, 0x21, 0 - .dw 0xc8c0, 0xc83d, 0xc8ff, 0xc83d, 0x21, 0 - .dw 0xc940, 0xc83d, 0xc97f, 0xc83d, 0x21, 0 - .dw 0xc9c0, 0xc83d, 0xc9ff, 0xc83d, 0x21, 0 - .dw 0xca40, 0xc83d, 0xca7f, 0xc83d, 0x21, 0 - .dw 0xcac0, 0xc83d, 0xcaff, 0xc83d, 0x21, 0 - .dw 0xcb40, 0xc83d, 0xcb7f, 0xc83d, 0x21, 0 - .dw 0xcbc0, 0xc83d, 0xcbff, 0xc83d, 0x21, 0 - .dw 0xcc40, 0xc83d, 0xcc7f, 0xc83d, 0x21, 0 - .dw 0xccc0, 0xc83d, 0xccff, 0xc83d, 0x21, 0 - .dw 0xcd40, 0xc83d, 0xcd7f, 0xc83d, 0x21, 0 - .dw 0xcdc0, 0xc83d, 0xcdff, 0xc83d, 0x21, 0 - .dw 0xce40, 0xc83d, 0xce7f, 0xc83d, 0x21, 0 - .dw 0xcec0, 0xc83d, 0xceff, 0xc83d, 0x21, 0 - .dw 0xcf40, 0xc83d, 0xcf7f, 0xc83d, 0x21, 0 - .dw 0xcfc0, 0xc83d, 0xcfff, 0xc83d, 0x21, 0 - .dw 0xd040, 0xc83d, 0xd07f, 0xc83d, 0x21, 0 - .dw 0xd0c0, 0xc83d, 0xd0ff, 0xc83d, 0x21, 0 - .dw 0xd140, 0xc83d, 0xd17f, 0xc83d, 0x21, 0 - .dw 0xd1c0, 0xc83d, 0xd1ff, 0xc83d, 0x21, 0 - .dw 0xd240, 0xc83d, 0xd27f, 0xc83d, 0x21, 0 - .dw 0xd2c0, 0xc83d, 0xd2ff, 0xc83d, 0x21, 0 - .dw 0xd340, 0xc83d, 0xd37f, 0xc83d, 0x21, 0 - .dw 0xd3c0, 0xc83d, 0xd3ff, 0xc83d, 0x21, 0 - .dw 0xd440, 0xc83d, 0xd47f, 0xc83d, 0x21, 0 - .dw 0xd4c0, 0xc83d, 0xd4ff, 0xc83d, 0x21, 0 - .dw 0xd540, 0xc83d, 0xd57f, 0xc83d, 0x21, 0 - .dw 0xd5c0, 0xc83d, 0xd5ff, 0xc83d, 0x21, 0 - .dw 0xd640, 0xc83d, 0xd67f, 0xc83d, 0x21, 0 - .dw 0xd6c0, 0xc83d, 0xd6ff, 0xc83d, 0x21, 0 - .dw 0xd740, 0xc83d, 0xd77f, 0xc83d, 0x21, 0 - .dw 0xd7c0, 0xc83d, 0xd7ff, 0xc83d, 0x21, 0 - .dw 0xd840, 0xc83d, 0xd87f, 0xc83d, 0x21, 0 - .dw 0xd8c0, 0xc83d, 0xd8ff, 0xc83d, 0x21, 0 - .dw 0xd940, 0xc83d, 0xd97f, 0xc83d, 0x21, 0 - .dw 0xd9c0, 0xc83d, 0xdfff, 0xc83d, 0x21, 0 - .dw 0xe040, 0xc83d, 0xe07f, 0xc83d, 0x21, 0 - .dw 0xe0c0, 0xc83d, 0xe0ff, 0xc83d, 0x21, 0 - .dw 0xe140, 0xc83d, 0xe17f, 0xc83d, 0x21, 0 - .dw 0xe1c0, 0xc83d, 0xe1ff, 0xc83d, 0x21, 0 - .dw 0xe240, 0xc83d, 0xe27f, 0xc83d, 0x21, 0 - .dw 0xe2c0, 0xc83d, 0xe2ff, 0xc83d, 0x21, 0 - .dw 0xe340, 0xc83d, 0xe37f, 0xc83d, 0x21, 0 - .dw 0xe3c0, 0xc83d, 0xe3ff, 0xc83d, 0x21, 0 - .dw 0xe440, 0xc83d, 0xe47f, 0xc83d, 0x21, 0 - .dw 0xe4c0, 0xc83d, 0xe4ff, 0xc83d, 0x21, 0 - .dw 0xe540, 0xc83d, 0xe57f, 0xc83d, 0x21, 0 - .dw 0xe5c0, 0xc83d, 0xe5ff, 0xc83d, 0x21, 0 - .dw 0xe640, 0xc83d, 0xe67f, 0xc83d, 0x21, 0 - .dw 0xe6c0, 0xc83d, 0xe6ff, 0xc83d, 0x21, 0 - .dw 0xe740, 0xc83d, 0xe77f, 0xc83d, 0x21, 0 - .dw 0xe7c0, 0xc83d, 0xe7ff, 0xc83d, 0x21, 0 - .dw 0xe840, 0xc83d, 0xe87f, 0xc83d, 0x21, 0 - .dw 0xe8c0, 0xc83d, 0xe8ff, 0xc83d, 0x21, 0 - .dw 0xe940, 0xc83d, 0xe97f, 0xc83d, 0x21, 0 - .dw 0xe9c0, 0xc83d, 0xe9ff, 0xc83d, 0x21, 0 - .dw 0xea40, 0xc83d, 0xea7f, 0xc83d, 0x21, 0 - .dw 0xeac0, 0xc83d, 0xeaff, 0xc83d, 0x21, 0 - .dw 0xeb40, 0xc83d, 0xeb7f, 0xc83d, 0x21, 0 - .dw 0xebc0, 0xc83d, 0xebff, 0xc83d, 0x21, 0 - .dw 0xec40, 0xc83d, 0xec7f, 0xc83d, 0x21, 0 - .dw 0xecc0, 0xc83d, 0xecff, 0xc83d, 0x21, 0 - .dw 0xed40, 0xc83d, 0xed7f, 0xc83d, 0x21, 0 - .dw 0xedc0, 0xc83d, 0xedff, 0xc83d, 0x21, 0 - .dw 0xee40, 0xc83d, 0xee7f, 0xc83d, 0x21, 0 - .dw 0xeec0, 0xc83d, 0xeeff, 0xc83d, 0x21, 0 - .dw 0xef40, 0xc83d, 0xef7f, 0xc83d, 0x21, 0 - .dw 0xefc0, 0xc83d, 0xefff, 0xc83d, 0x21, 0 - .dw 0xf040, 0xc83d, 0xf07f, 0xc83d, 0x21, 0 - .dw 0xf0c0, 0xc83d, 0xf0ff, 0xc83d, 0x21, 0 - .dw 0xf140, 0xc83d, 0xf17f, 0xc83d, 0x21, 0 - .dw 0xf1c0, 0xc83d, 0xf1ff, 0xc83d, 0x21, 0 - .dw 0xf240, 0xc83d, 0xf27f, 0xc83d, 0x21, 0 - .dw 0xf2c0, 0xc83d, 0xf2ff, 0xc83d, 0x21, 0 - .dw 0xf340, 0xc83d, 0xf37f, 0xc83d, 0x21, 0 - .dw 0xf3c0, 0xc83d, 0xf3ff, 0xc83d, 0x21, 0 - .dw 0xf440, 0xc83d, 0xf47f, 0xc83d, 0x21, 0 - .dw 0xf4c0, 0xc83d, 0xf4ff, 0xc83d, 0x21, 0 - .dw 0xf540, 0xc83d, 0xf57f, 0xc83d, 0x21, 0 - .dw 0xf5c0, 0xc83d, 0xf5ff, 0xc83d, 0x21, 0 - .dw 0xf640, 0xc83d, 0xf67f, 0xc83d, 0x21, 0 - .dw 0xf6c0, 0xc83d, 0xf6ff, 0xc83d, 0x21, 0 - .dw 0xf740, 0xc83d, 0xf77f, 0xc83d, 0x21, 0 - .dw 0xf7c0, 0xc83d, 0xf7ff, 0xc83d, 0x21, 0 - .dw 0xf840, 0xc83d, 0xf87f, 0xc83d, 0x21, 0 - .dw 0xf8c0, 0xc83d, 0xf8ff, 0xc83d, 0x21, 0 - .dw 0xf940, 0xc83d, 0xf97f, 0xc83d, 0x21, 0 - .dw 0xf9c0, 0xc83d, 0xffff, 0xc83d, 0x21, 0 - .dw 0x0040, 0xc83e, 0x007f, 0xc83e, 0x21, 0 - .dw 0x00c0, 0xc83e, 0x00ff, 0xc83e, 0x21, 0 - .dw 0x0140, 0xc83e, 0x017f, 0xc83e, 0x21, 0 - .dw 0x01c0, 0xc83e, 0x01ff, 0xc83e, 0x21, 0 - .dw 0x0240, 0xc83e, 0x027f, 0xc83e, 0x21, 0 - .dw 0x02c0, 0xc83e, 0x02ff, 0xc83e, 0x21, 0 - .dw 0x0340, 0xc83e, 0x037f, 0xc83e, 0x21, 0 - .dw 0x03c0, 0xc83e, 0x03ff, 0xc83e, 0x21, 0 - .dw 0x0440, 0xc83e, 0x047f, 0xc83e, 0x21, 0 - .dw 0x04c0, 0xc83e, 0x04ff, 0xc83e, 0x21, 0 - .dw 0x0540, 0xc83e, 0x057f, 0xc83e, 0x21, 0 - .dw 0x05c0, 0xc83e, 0x05ff, 0xc83e, 0x21, 0 - .dw 0x0640, 0xc83e, 0x067f, 0xc83e, 0x21, 0 - .dw 0x06c0, 0xc83e, 0x06ff, 0xc83e, 0x21, 0 - .dw 0x0740, 0xc83e, 0x077f, 0xc83e, 0x21, 0 - .dw 0x07c0, 0xc83e, 0x07ff, 0xc83e, 0x21, 0 - .dw 0x0840, 0xc83e, 0x087f, 0xc83e, 0x21, 0 - .dw 0x08c0, 0xc83e, 0x08ff, 0xc83e, 0x21, 0 - .dw 0x0940, 0xc83e, 0x097f, 0xc83e, 0x21, 0 - .dw 0x09c0, 0xc83e, 0x09ff, 0xc83e, 0x21, 0 - .dw 0x0a40, 0xc83e, 0x0a7f, 0xc83e, 0x21, 0 - .dw 0x0ac0, 0xc83e, 0x0aff, 0xc83e, 0x21, 0 - .dw 0x0b40, 0xc83e, 0x0b7f, 0xc83e, 0x21, 0 - .dw 0x0bc0, 0xc83e, 0x0bff, 0xc83e, 0x21, 0 - .dw 0x0c40, 0xc83e, 0x0c7f, 0xc83e, 0x21, 0 - .dw 0x0cc0, 0xc83e, 0x0cff, 0xc83e, 0x21, 0 - .dw 0x0d40, 0xc83e, 0x0d7f, 0xc83e, 0x21, 0 - .dw 0x0dc0, 0xc83e, 0x0dff, 0xc83e, 0x21, 0 - .dw 0x0e40, 0xc83e, 0x0e7f, 0xc83e, 0x21, 0 - .dw 0x0ec0, 0xc83e, 0x0eff, 0xc83e, 0x21, 0 - .dw 0x0f40, 0xc83e, 0x0f7f, 0xc83e, 0x21, 0 - .dw 0x0fc0, 0xc83e, 0x0fff, 0xc83e, 0x21, 0 - .dw 0x1040, 0xc83e, 0x107f, 0xc83e, 0x21, 0 - .dw 0x10c0, 0xc83e, 0x10ff, 0xc83e, 0x21, 0 - .dw 0x1140, 0xc83e, 0x117f, 0xc83e, 0x21, 0 - .dw 0x11c0, 0xc83e, 0x11ff, 0xc83e, 0x21, 0 - .dw 0x1240, 0xc83e, 0x127f, 0xc83e, 0x21, 0 - .dw 0x12c0, 0xc83e, 0x12ff, 0xc83e, 0x21, 0 - .dw 0x1340, 0xc83e, 0x137f, 0xc83e, 0x21, 0 - .dw 0x13c0, 0xc83e, 0x13ff, 0xc83e, 0x21, 0 - .dw 0x1440, 0xc83e, 0x147f, 0xc83e, 0x21, 0 - .dw 0x14c0, 0xc83e, 0x14ff, 0xc83e, 0x21, 0 - .dw 0x1540, 0xc83e, 0x157f, 0xc83e, 0x21, 0 - .dw 0x15c0, 0xc83e, 0x15ff, 0xc83e, 0x21, 0 - .dw 0x1640, 0xc83e, 0x167f, 0xc83e, 0x21, 0 - .dw 0x16c0, 0xc83e, 0x16ff, 0xc83e, 0x21, 0 - .dw 0x1740, 0xc83e, 0x177f, 0xc83e, 0x21, 0 - .dw 0x17c0, 0xc83e, 0x17ff, 0xc83e, 0x21, 0 - .dw 0x1840, 0xc83e, 0x187f, 0xc83e, 0x21, 0 - .dw 0x18c0, 0xc83e, 0x18ff, 0xc83e, 0x21, 0 - .dw 0x1940, 0xc83e, 0x197f, 0xc83e, 0x21, 0 - .dw 0x19c0, 0xc83e, 0x1fff, 0xc83e, 0x21, 0 - .dw 0x2040, 0xc83e, 0x207f, 0xc83e, 0x21, 0 - .dw 0x20c0, 0xc83e, 0x20ff, 0xc83e, 0x21, 0 - .dw 0x2140, 0xc83e, 0x217f, 0xc83e, 0x21, 0 - .dw 0x21c0, 0xc83e, 0x21ff, 0xc83e, 0x21, 0 - .dw 0x2240, 0xc83e, 0x227f, 0xc83e, 0x21, 0 - .dw 0x22c0, 0xc83e, 0x22ff, 0xc83e, 0x21, 0 - .dw 0x2340, 0xc83e, 0x237f, 0xc83e, 0x21, 0 - .dw 0x23c0, 0xc83e, 0x23ff, 0xc83e, 0x21, 0 - .dw 0x2440, 0xc83e, 0x247f, 0xc83e, 0x21, 0 - .dw 0x24c0, 0xc83e, 0x24ff, 0xc83e, 0x21, 0 - .dw 0x2540, 0xc83e, 0x257f, 0xc83e, 0x21, 0 - .dw 0x25c0, 0xc83e, 0x25ff, 0xc83e, 0x21, 0 - .dw 0x2640, 0xc83e, 0x267f, 0xc83e, 0x21, 0 - .dw 0x26c0, 0xc83e, 0x26ff, 0xc83e, 0x21, 0 - .dw 0x2740, 0xc83e, 0x277f, 0xc83e, 0x21, 0 - .dw 0x27c0, 0xc83e, 0x27ff, 0xc83e, 0x21, 0 - .dw 0x2840, 0xc83e, 0x287f, 0xc83e, 0x21, 0 - .dw 0x28c0, 0xc83e, 0x28ff, 0xc83e, 0x21, 0 - .dw 0x2940, 0xc83e, 0x297f, 0xc83e, 0x21, 0 - .dw 0x29c0, 0xc83e, 0x29ff, 0xc83e, 0x21, 0 - .dw 0x2a40, 0xc83e, 0x2a7f, 0xc83e, 0x21, 0 - .dw 0x2ac0, 0xc83e, 0x2aff, 0xc83e, 0x21, 0 - .dw 0x2b40, 0xc83e, 0x2b7f, 0xc83e, 0x21, 0 - .dw 0x2bc0, 0xc83e, 0x2bff, 0xc83e, 0x21, 0 - .dw 0x2c40, 0xc83e, 0x2c7f, 0xc83e, 0x21, 0 - .dw 0x2cc0, 0xc83e, 0x2cff, 0xc83e, 0x21, 0 - .dw 0x2d40, 0xc83e, 0x2d7f, 0xc83e, 0x21, 0 - .dw 0x2dc0, 0xc83e, 0x2dff, 0xc83e, 0x21, 0 - .dw 0x2e40, 0xc83e, 0x2e7f, 0xc83e, 0x21, 0 - .dw 0x2ec0, 0xc83e, 0x2eff, 0xc83e, 0x21, 0 - .dw 0x2f40, 0xc83e, 0x2f7f, 0xc83e, 0x21, 0 - .dw 0x2fc0, 0xc83e, 0x2fff, 0xc83e, 0x21, 0 - .dw 0x3040, 0xc83e, 0x307f, 0xc83e, 0x21, 0 - .dw 0x30c0, 0xc83e, 0x30ff, 0xc83e, 0x21, 0 - .dw 0x3140, 0xc83e, 0x317f, 0xc83e, 0x21, 0 - .dw 0x31c0, 0xc83e, 0x31ff, 0xc83e, 0x21, 0 - .dw 0x3240, 0xc83e, 0x327f, 0xc83e, 0x21, 0 - .dw 0x32c0, 0xc83e, 0x32ff, 0xc83e, 0x21, 0 - .dw 0x3340, 0xc83e, 0x337f, 0xc83e, 0x21, 0 - .dw 0x33c0, 0xc83e, 0x33ff, 0xc83e, 0x21, 0 - .dw 0x3440, 0xc83e, 0x347f, 0xc83e, 0x21, 0 - .dw 0x34c0, 0xc83e, 0x34ff, 0xc83e, 0x21, 0 - .dw 0x3540, 0xc83e, 0x357f, 0xc83e, 0x21, 0 - .dw 0x35c0, 0xc83e, 0x35ff, 0xc83e, 0x21, 0 - .dw 0x3640, 0xc83e, 0x367f, 0xc83e, 0x21, 0 - .dw 0x36c0, 0xc83e, 0x36ff, 0xc83e, 0x21, 0 - .dw 0x3740, 0xc83e, 0x377f, 0xc83e, 0x21, 0 - .dw 0x37c0, 0xc83e, 0x37ff, 0xc83e, 0x21, 0 - .dw 0x3840, 0xc83e, 0x387f, 0xc83e, 0x21, 0 - .dw 0x38c0, 0xc83e, 0x38ff, 0xc83e, 0x21, 0 - .dw 0x3940, 0xc83e, 0x397f, 0xc83e, 0x21, 0 - .dw 0x39c0, 0xc83e, 0x3fff, 0xc83e, 0x21, 0 - .dw 0x4040, 0xc83e, 0x407f, 0xc83e, 0x21, 0 - .dw 0x40c0, 0xc83e, 0x40ff, 0xc83e, 0x21, 0 - .dw 0x4140, 0xc83e, 0x417f, 0xc83e, 0x21, 0 - .dw 0x41c0, 0xc83e, 0x41ff, 0xc83e, 0x21, 0 - .dw 0x4240, 0xc83e, 0x427f, 0xc83e, 0x21, 0 - .dw 0x42c0, 0xc83e, 0x42ff, 0xc83e, 0x21, 0 - .dw 0x4340, 0xc83e, 0x437f, 0xc83e, 0x21, 0 - .dw 0x43c0, 0xc83e, 0x43ff, 0xc83e, 0x21, 0 - .dw 0x4440, 0xc83e, 0x447f, 0xc83e, 0x21, 0 - .dw 0x44c0, 0xc83e, 0x44ff, 0xc83e, 0x21, 0 - .dw 0x4540, 0xc83e, 0x457f, 0xc83e, 0x21, 0 - .dw 0x45c0, 0xc83e, 0x45ff, 0xc83e, 0x21, 0 - .dw 0x4640, 0xc83e, 0x467f, 0xc83e, 0x21, 0 - .dw 0x46c0, 0xc83e, 0x46ff, 0xc83e, 0x21, 0 - .dw 0x4740, 0xc83e, 0x477f, 0xc83e, 0x21, 0 - .dw 0x47c0, 0xc83e, 0x47ff, 0xc83e, 0x21, 0 - .dw 0x4840, 0xc83e, 0x487f, 0xc83e, 0x21, 0 - .dw 0x48c0, 0xc83e, 0x48ff, 0xc83e, 0x21, 0 - .dw 0x4940, 0xc83e, 0x497f, 0xc83e, 0x21, 0 - .dw 0x49c0, 0xc83e, 0x49ff, 0xc83e, 0x21, 0 - .dw 0x4a40, 0xc83e, 0x4a7f, 0xc83e, 0x21, 0 - .dw 0x4ac0, 0xc83e, 0x4aff, 0xc83e, 0x21, 0 - .dw 0x4b40, 0xc83e, 0x4b7f, 0xc83e, 0x21, 0 - .dw 0x4bc0, 0xc83e, 0x4bff, 0xc83e, 0x21, 0 - .dw 0x4c40, 0xc83e, 0x4c7f, 0xc83e, 0x21, 0 - .dw 0x4cc0, 0xc83e, 0x4cff, 0xc83e, 0x21, 0 - .dw 0x4d40, 0xc83e, 0x4d7f, 0xc83e, 0x21, 0 - .dw 0x4dc0, 0xc83e, 0x4dff, 0xc83e, 0x21, 0 - .dw 0x4e40, 0xc83e, 0x4e7f, 0xc83e, 0x21, 0 - .dw 0x4ec0, 0xc83e, 0x4eff, 0xc83e, 0x21, 0 - .dw 0x4f40, 0xc83e, 0x4f7f, 0xc83e, 0x21, 0 - .dw 0x4fc0, 0xc83e, 0x4fff, 0xc83e, 0x21, 0 - .dw 0x5040, 0xc83e, 0x507f, 0xc83e, 0x21, 0 - .dw 0x50c0, 0xc83e, 0x50ff, 0xc83e, 0x21, 0 - .dw 0x5140, 0xc83e, 0x517f, 0xc83e, 0x21, 0 - .dw 0x51c0, 0xc83e, 0x51ff, 0xc83e, 0x21, 0 - .dw 0x5240, 0xc83e, 0x527f, 0xc83e, 0x21, 0 - .dw 0x52c0, 0xc83e, 0x52ff, 0xc83e, 0x21, 0 - .dw 0x5340, 0xc83e, 0x537f, 0xc83e, 0x21, 0 - .dw 0x53c0, 0xc83e, 0x53ff, 0xc83e, 0x21, 0 - .dw 0x5440, 0xc83e, 0x547f, 0xc83e, 0x21, 0 - .dw 0x54c0, 0xc83e, 0x54ff, 0xc83e, 0x21, 0 - .dw 0x5540, 0xc83e, 0x557f, 0xc83e, 0x21, 0 - .dw 0x55c0, 0xc83e, 0x55ff, 0xc83e, 0x21, 0 - .dw 0x5640, 0xc83e, 0x567f, 0xc83e, 0x21, 0 - .dw 0x56c0, 0xc83e, 0x56ff, 0xc83e, 0x21, 0 - .dw 0x5740, 0xc83e, 0x577f, 0xc83e, 0x21, 0 - .dw 0x57c0, 0xc83e, 0x57ff, 0xc83e, 0x21, 0 - .dw 0x5840, 0xc83e, 0x587f, 0xc83e, 0x21, 0 - .dw 0x58c0, 0xc83e, 0x58ff, 0xc83e, 0x21, 0 - .dw 0x5940, 0xc83e, 0x597f, 0xc83e, 0x21, 0 - .dw 0x59c0, 0xc83e, 0x5fff, 0xc83e, 0x21, 0 - .dw 0x6040, 0xc83e, 0x607f, 0xc83e, 0x21, 0 - .dw 0x60c0, 0xc83e, 0x60ff, 0xc83e, 0x21, 0 - .dw 0x6140, 0xc83e, 0x617f, 0xc83e, 0x21, 0 - .dw 0x61c0, 0xc83e, 0x61ff, 0xc83e, 0x21, 0 - .dw 0x6240, 0xc83e, 0x627f, 0xc83e, 0x21, 0 - .dw 0x62c0, 0xc83e, 0x62ff, 0xc83e, 0x21, 0 - .dw 0x6340, 0xc83e, 0x637f, 0xc83e, 0x21, 0 - .dw 0x63c0, 0xc83e, 0x63ff, 0xc83e, 0x21, 0 - .dw 0x6440, 0xc83e, 0x647f, 0xc83e, 0x21, 0 - .dw 0x64c0, 0xc83e, 0x64ff, 0xc83e, 0x21, 0 - .dw 0x6540, 0xc83e, 0x657f, 0xc83e, 0x21, 0 - .dw 0x65c0, 0xc83e, 0x65ff, 0xc83e, 0x21, 0 - .dw 0x6640, 0xc83e, 0x667f, 0xc83e, 0x21, 0 - .dw 0x66c0, 0xc83e, 0x66ff, 0xc83e, 0x21, 0 - .dw 0x6740, 0xc83e, 0x677f, 0xc83e, 0x21, 0 - .dw 0x67c0, 0xc83e, 0x67ff, 0xc83e, 0x21, 0 - .dw 0x6840, 0xc83e, 0x687f, 0xc83e, 0x21, 0 - .dw 0x68c0, 0xc83e, 0x68ff, 0xc83e, 0x21, 0 - .dw 0x6940, 0xc83e, 0x697f, 0xc83e, 0x21, 0 - .dw 0x69c0, 0xc83e, 0x69ff, 0xc83e, 0x21, 0 - .dw 0x6a40, 0xc83e, 0x6a7f, 0xc83e, 0x21, 0 - .dw 0x6ac0, 0xc83e, 0x6aff, 0xc83e, 0x21, 0 - .dw 0x6b40, 0xc83e, 0x6b7f, 0xc83e, 0x21, 0 - .dw 0x6bc0, 0xc83e, 0x6bff, 0xc83e, 0x21, 0 - .dw 0x6c40, 0xc83e, 0x6c7f, 0xc83e, 0x21, 0 - .dw 0x6cc0, 0xc83e, 0x6cff, 0xc83e, 0x21, 0 - .dw 0x6d40, 0xc83e, 0x6d7f, 0xc83e, 0x21, 0 - .dw 0x6dc0, 0xc83e, 0x6dff, 0xc83e, 0x21, 0 - .dw 0x6e40, 0xc83e, 0x6e7f, 0xc83e, 0x21, 0 - .dw 0x6ec0, 0xc83e, 0x6eff, 0xc83e, 0x21, 0 - .dw 0x6f40, 0xc83e, 0x6f7f, 0xc83e, 0x21, 0 - .dw 0x6fc0, 0xc83e, 0x6fff, 0xc83e, 0x21, 0 - .dw 0x7040, 0xc83e, 0x707f, 0xc83e, 0x21, 0 - .dw 0x70c0, 0xc83e, 0x70ff, 0xc83e, 0x21, 0 - .dw 0x7140, 0xc83e, 0x717f, 0xc83e, 0x21, 0 - .dw 0x71c0, 0xc83e, 0x71ff, 0xc83e, 0x21, 0 - .dw 0x7240, 0xc83e, 0x727f, 0xc83e, 0x21, 0 - .dw 0x72c0, 0xc83e, 0x72ff, 0xc83e, 0x21, 0 - .dw 0x7340, 0xc83e, 0x737f, 0xc83e, 0x21, 0 - .dw 0x73c0, 0xc83e, 0x73ff, 0xc83e, 0x21, 0 - .dw 0x7440, 0xc83e, 0x747f, 0xc83e, 0x21, 0 - .dw 0x74c0, 0xc83e, 0x74ff, 0xc83e, 0x21, 0 - .dw 0x7540, 0xc83e, 0x757f, 0xc83e, 0x21, 0 - .dw 0x75c0, 0xc83e, 0x75ff, 0xc83e, 0x21, 0 - .dw 0x7640, 0xc83e, 0x767f, 0xc83e, 0x21, 0 - .dw 0x76c0, 0xc83e, 0x76ff, 0xc83e, 0x21, 0 - .dw 0x7740, 0xc83e, 0x777f, 0xc83e, 0x21, 0 - .dw 0x77c0, 0xc83e, 0x77ff, 0xc83e, 0x21, 0 - .dw 0x7840, 0xc83e, 0x787f, 0xc83e, 0x21, 0 - .dw 0x78c0, 0xc83e, 0x78ff, 0xc83e, 0x21, 0 - .dw 0x7940, 0xc83e, 0x797f, 0xc83e, 0x21, 0 - .dw 0x79c0, 0xc83e, 0x7fff, 0xc83e, 0x21, 0 - .dw 0x8040, 0xc83e, 0x807f, 0xc83e, 0x21, 0 - .dw 0x80c0, 0xc83e, 0x80ff, 0xc83e, 0x21, 0 - .dw 0x8140, 0xc83e, 0x817f, 0xc83e, 0x21, 0 - .dw 0x81c0, 0xc83e, 0x81ff, 0xc83e, 0x21, 0 - .dw 0x8240, 0xc83e, 0x827f, 0xc83e, 0x21, 0 - .dw 0x82c0, 0xc83e, 0x82ff, 0xc83e, 0x21, 0 - .dw 0x8340, 0xc83e, 0x837f, 0xc83e, 0x21, 0 - .dw 0x83c0, 0xc83e, 0x83ff, 0xc83e, 0x21, 0 - .dw 0x8440, 0xc83e, 0x847f, 0xc83e, 0x21, 0 - .dw 0x84c0, 0xc83e, 0x84ff, 0xc83e, 0x21, 0 - .dw 0x8540, 0xc83e, 0x857f, 0xc83e, 0x21, 0 - .dw 0x85c0, 0xc83e, 0x85ff, 0xc83e, 0x21, 0 - .dw 0x8640, 0xc83e, 0x867f, 0xc83e, 0x21, 0 - .dw 0x86c0, 0xc83e, 0x86ff, 0xc83e, 0x21, 0 - .dw 0x8740, 0xc83e, 0x877f, 0xc83e, 0x21, 0 - .dw 0x87c0, 0xc83e, 0x87ff, 0xc83e, 0x21, 0 - .dw 0x8840, 0xc83e, 0x887f, 0xc83e, 0x21, 0 - .dw 0x88c0, 0xc83e, 0x88ff, 0xc83e, 0x21, 0 - .dw 0x8940, 0xc83e, 0x897f, 0xc83e, 0x21, 0 - .dw 0x89c0, 0xc83e, 0x89ff, 0xc83e, 0x21, 0 - .dw 0x8a40, 0xc83e, 0x8a7f, 0xc83e, 0x21, 0 - .dw 0x8ac0, 0xc83e, 0x8aff, 0xc83e, 0x21, 0 - .dw 0x8b40, 0xc83e, 0x8b7f, 0xc83e, 0x21, 0 - .dw 0x8bc0, 0xc83e, 0x8bff, 0xc83e, 0x21, 0 - .dw 0x8c40, 0xc83e, 0x8c7f, 0xc83e, 0x21, 0 - .dw 0x8cc0, 0xc83e, 0x8cff, 0xc83e, 0x21, 0 - .dw 0x8d40, 0xc83e, 0x8d7f, 0xc83e, 0x21, 0 - .dw 0x8dc0, 0xc83e, 0x8dff, 0xc83e, 0x21, 0 - .dw 0x8e40, 0xc83e, 0x8e7f, 0xc83e, 0x21, 0 - .dw 0x8ec0, 0xc83e, 0x8eff, 0xc83e, 0x21, 0 - .dw 0x8f40, 0xc83e, 0x8f7f, 0xc83e, 0x21, 0 - .dw 0x8fc0, 0xc83e, 0x8fff, 0xc83e, 0x21, 0 - .dw 0x9040, 0xc83e, 0x907f, 0xc83e, 0x21, 0 - .dw 0x90c0, 0xc83e, 0x90ff, 0xc83e, 0x21, 0 - .dw 0x9140, 0xc83e, 0x917f, 0xc83e, 0x21, 0 - .dw 0x91c0, 0xc83e, 0x91ff, 0xc83e, 0x21, 0 - .dw 0x9240, 0xc83e, 0x927f, 0xc83e, 0x21, 0 - .dw 0x92c0, 0xc83e, 0x92ff, 0xc83e, 0x21, 0 - .dw 0x9340, 0xc83e, 0x937f, 0xc83e, 0x21, 0 - .dw 0x93c0, 0xc83e, 0x93ff, 0xc83e, 0x21, 0 - .dw 0x9440, 0xc83e, 0x947f, 0xc83e, 0x21, 0 - .dw 0x94c0, 0xc83e, 0x94ff, 0xc83e, 0x21, 0 - .dw 0x9540, 0xc83e, 0x957f, 0xc83e, 0x21, 0 - .dw 0x95c0, 0xc83e, 0x95ff, 0xc83e, 0x21, 0 - .dw 0x9640, 0xc83e, 0x967f, 0xc83e, 0x21, 0 - .dw 0x96c0, 0xc83e, 0x96ff, 0xc83e, 0x21, 0 - .dw 0x9740, 0xc83e, 0x977f, 0xc83e, 0x21, 0 - .dw 0x97c0, 0xc83e, 0x97ff, 0xc83e, 0x21, 0 - .dw 0x9840, 0xc83e, 0x987f, 0xc83e, 0x21, 0 - .dw 0x98c0, 0xc83e, 0x98ff, 0xc83e, 0x21, 0 - .dw 0x9940, 0xc83e, 0x997f, 0xc83e, 0x21, 0 - .dw 0x99c0, 0xc83e, 0x9fff, 0xc83e, 0x21, 0 - .dw 0xa040, 0xc83e, 0xa07f, 0xc83e, 0x21, 0 - .dw 0xa0c0, 0xc83e, 0xa0ff, 0xc83e, 0x21, 0 - .dw 0xa140, 0xc83e, 0xa17f, 0xc83e, 0x21, 0 - .dw 0xa1c0, 0xc83e, 0xa1ff, 0xc83e, 0x21, 0 - .dw 0xa240, 0xc83e, 0xa27f, 0xc83e, 0x21, 0 - .dw 0xa2c0, 0xc83e, 0xa2ff, 0xc83e, 0x21, 0 - .dw 0xa340, 0xc83e, 0xa37f, 0xc83e, 0x21, 0 - .dw 0xa3c0, 0xc83e, 0xa3ff, 0xc83e, 0x21, 0 - .dw 0xa440, 0xc83e, 0xa47f, 0xc83e, 0x21, 0 - .dw 0xa4c0, 0xc83e, 0xa4ff, 0xc83e, 0x21, 0 - .dw 0xa540, 0xc83e, 0xa57f, 0xc83e, 0x21, 0 - .dw 0xa5c0, 0xc83e, 0xa5ff, 0xc83e, 0x21, 0 - .dw 0xa640, 0xc83e, 0xa67f, 0xc83e, 0x21, 0 - .dw 0xa6c0, 0xc83e, 0xa6ff, 0xc83e, 0x21, 0 - .dw 0xa740, 0xc83e, 0xa77f, 0xc83e, 0x21, 0 - .dw 0xa7c0, 0xc83e, 0xa7ff, 0xc83e, 0x21, 0 - .dw 0xa840, 0xc83e, 0xa87f, 0xc83e, 0x21, 0 - .dw 0xa8c0, 0xc83e, 0xa8ff, 0xc83e, 0x21, 0 - .dw 0xa940, 0xc83e, 0xa97f, 0xc83e, 0x21, 0 - .dw 0xa9c0, 0xc83e, 0xa9ff, 0xc83e, 0x21, 0 - .dw 0xaa40, 0xc83e, 0xaa7f, 0xc83e, 0x21, 0 - .dw 0xaac0, 0xc83e, 0xaaff, 0xc83e, 0x21, 0 - .dw 0xab40, 0xc83e, 0xab7f, 0xc83e, 0x21, 0 - .dw 0xabc0, 0xc83e, 0xabff, 0xc83e, 0x21, 0 - .dw 0xac40, 0xc83e, 0xac7f, 0xc83e, 0x21, 0 - .dw 0xacc0, 0xc83e, 0xacff, 0xc83e, 0x21, 0 - .dw 0xad40, 0xc83e, 0xad7f, 0xc83e, 0x21, 0 - .dw 0xadc0, 0xc83e, 0xadff, 0xc83e, 0x21, 0 - .dw 0xae40, 0xc83e, 0xae7f, 0xc83e, 0x21, 0 - .dw 0xaec0, 0xc83e, 0xaeff, 0xc83e, 0x21, 0 - .dw 0xaf40, 0xc83e, 0xaf7f, 0xc83e, 0x21, 0 - .dw 0xafc0, 0xc83e, 0xafff, 0xc83e, 0x21, 0 - .dw 0xb040, 0xc83e, 0xb07f, 0xc83e, 0x21, 0 - .dw 0xb0c0, 0xc83e, 0xb0ff, 0xc83e, 0x21, 0 - .dw 0xb140, 0xc83e, 0xb17f, 0xc83e, 0x21, 0 - .dw 0xb1c0, 0xc83e, 0xb1ff, 0xc83e, 0x21, 0 - .dw 0xb240, 0xc83e, 0xb27f, 0xc83e, 0x21, 0 - .dw 0xb2c0, 0xc83e, 0xb2ff, 0xc83e, 0x21, 0 - .dw 0xb340, 0xc83e, 0xb37f, 0xc83e, 0x21, 0 - .dw 0xb3c0, 0xc83e, 0xb3ff, 0xc83e, 0x21, 0 - .dw 0xb440, 0xc83e, 0xb47f, 0xc83e, 0x21, 0 - .dw 0xb4c0, 0xc83e, 0xb4ff, 0xc83e, 0x21, 0 - .dw 0xb540, 0xc83e, 0xb57f, 0xc83e, 0x21, 0 - .dw 0xb5c0, 0xc83e, 0xb5ff, 0xc83e, 0x21, 0 - .dw 0xb640, 0xc83e, 0xb67f, 0xc83e, 0x21, 0 - .dw 0xb6c0, 0xc83e, 0xb6ff, 0xc83e, 0x21, 0 - .dw 0xb740, 0xc83e, 0xb77f, 0xc83e, 0x21, 0 - .dw 0xb7c0, 0xc83e, 0xb7ff, 0xc83e, 0x21, 0 - .dw 0xb840, 0xc83e, 0xb87f, 0xc83e, 0x21, 0 - .dw 0xb8c0, 0xc83e, 0xb8ff, 0xc83e, 0x21, 0 - .dw 0xb940, 0xc83e, 0xb97f, 0xc83e, 0x21, 0 - .dw 0xb9c0, 0xc83e, 0xbfff, 0xc83e, 0x21, 0 - .dw 0xc040, 0xc83e, 0xc07f, 0xc83e, 0x21, 0 - .dw 0xc0c0, 0xc83e, 0xc0ff, 0xc83e, 0x21, 0 - .dw 0xc140, 0xc83e, 0xc17f, 0xc83e, 0x21, 0 - .dw 0xc1c0, 0xc83e, 0xc1ff, 0xc83e, 0x21, 0 - .dw 0xc240, 0xc83e, 0xc27f, 0xc83e, 0x21, 0 - .dw 0xc2c0, 0xc83e, 0xc2ff, 0xc83e, 0x21, 0 - .dw 0xc340, 0xc83e, 0xc37f, 0xc83e, 0x21, 0 - .dw 0xc3c0, 0xc83e, 0xc3ff, 0xc83e, 0x21, 0 - .dw 0xc440, 0xc83e, 0xc47f, 0xc83e, 0x21, 0 - .dw 0xc4c0, 0xc83e, 0xc4ff, 0xc83e, 0x21, 0 - .dw 0xc540, 0xc83e, 0xc57f, 0xc83e, 0x21, 0 - .dw 0xc5c0, 0xc83e, 0xc5ff, 0xc83e, 0x21, 0 - .dw 0xc640, 0xc83e, 0xc67f, 0xc83e, 0x21, 0 - .dw 0xc6c0, 0xc83e, 0xc6ff, 0xc83e, 0x21, 0 - .dw 0xc740, 0xc83e, 0xc77f, 0xc83e, 0x21, 0 - .dw 0xc7c0, 0xc83e, 0xc7ff, 0xc83e, 0x21, 0 - .dw 0xc840, 0xc83e, 0xc87f, 0xc83e, 0x21, 0 - .dw 0xc8c0, 0xc83e, 0xc8ff, 0xc83e, 0x21, 0 - .dw 0xc940, 0xc83e, 0xc97f, 0xc83e, 0x21, 0 - .dw 0xc9c0, 0xc83e, 0xc9ff, 0xc83e, 0x21, 0 - .dw 0xca40, 0xc83e, 0xca7f, 0xc83e, 0x21, 0 - .dw 0xcac0, 0xc83e, 0xcaff, 0xc83e, 0x21, 0 - .dw 0xcb40, 0xc83e, 0xcb7f, 0xc83e, 0x21, 0 - .dw 0xcbc0, 0xc83e, 0xcbff, 0xc83e, 0x21, 0 - .dw 0xcc40, 0xc83e, 0xcc7f, 0xc83e, 0x21, 0 - .dw 0xccc0, 0xc83e, 0xccff, 0xc83e, 0x21, 0 - .dw 0xcd40, 0xc83e, 0xcd7f, 0xc83e, 0x21, 0 - .dw 0xcdc0, 0xc83e, 0xcdff, 0xc83e, 0x21, 0 - .dw 0xce40, 0xc83e, 0xce7f, 0xc83e, 0x21, 0 - .dw 0xcec0, 0xc83e, 0xceff, 0xc83e, 0x21, 0 - .dw 0xcf40, 0xc83e, 0xcf7f, 0xc83e, 0x21, 0 - .dw 0xcfc0, 0xc83e, 0xcfff, 0xc83e, 0x21, 0 - .dw 0xd040, 0xc83e, 0xd07f, 0xc83e, 0x21, 0 - .dw 0xd0c0, 0xc83e, 0xd0ff, 0xc83e, 0x21, 0 - .dw 0xd140, 0xc83e, 0xd17f, 0xc83e, 0x21, 0 - .dw 0xd1c0, 0xc83e, 0xd1ff, 0xc83e, 0x21, 0 - .dw 0xd240, 0xc83e, 0xd27f, 0xc83e, 0x21, 0 - .dw 0xd2c0, 0xc83e, 0xd2ff, 0xc83e, 0x21, 0 - .dw 0xd340, 0xc83e, 0xd37f, 0xc83e, 0x21, 0 - .dw 0xd3c0, 0xc83e, 0xd3ff, 0xc83e, 0x21, 0 - .dw 0xd440, 0xc83e, 0xd47f, 0xc83e, 0x21, 0 - .dw 0xd4c0, 0xc83e, 0xd4ff, 0xc83e, 0x21, 0 - .dw 0xd540, 0xc83e, 0xd57f, 0xc83e, 0x21, 0 - .dw 0xd5c0, 0xc83e, 0xd5ff, 0xc83e, 0x21, 0 - .dw 0xd640, 0xc83e, 0xd67f, 0xc83e, 0x21, 0 - .dw 0xd6c0, 0xc83e, 0xd6ff, 0xc83e, 0x21, 0 - .dw 0xd740, 0xc83e, 0xd77f, 0xc83e, 0x21, 0 - .dw 0xd7c0, 0xc83e, 0xd7ff, 0xc83e, 0x21, 0 - .dw 0xd840, 0xc83e, 0xd87f, 0xc83e, 0x21, 0 - .dw 0xd8c0, 0xc83e, 0xd8ff, 0xc83e, 0x21, 0 - .dw 0xd940, 0xc83e, 0xd97f, 0xc83e, 0x21, 0 - .dw 0xd9c0, 0xc83e, 0xdfff, 0xc83e, 0x21, 0 - .dw 0xe040, 0xc83e, 0xe07f, 0xc83e, 0x21, 0 - .dw 0xe0c0, 0xc83e, 0xe0ff, 0xc83e, 0x21, 0 - .dw 0xe140, 0xc83e, 0xe17f, 0xc83e, 0x21, 0 - .dw 0xe1c0, 0xc83e, 0xe1ff, 0xc83e, 0x21, 0 - .dw 0xe240, 0xc83e, 0xe27f, 0xc83e, 0x21, 0 - .dw 0xe2c0, 0xc83e, 0xe2ff, 0xc83e, 0x21, 0 - .dw 0xe340, 0xc83e, 0xe37f, 0xc83e, 0x21, 0 - .dw 0xe3c0, 0xc83e, 0xe3ff, 0xc83e, 0x21, 0 - .dw 0xe440, 0xc83e, 0xe47f, 0xc83e, 0x21, 0 - .dw 0xe4c0, 0xc83e, 0xe4ff, 0xc83e, 0x21, 0 - .dw 0xe540, 0xc83e, 0xe57f, 0xc83e, 0x21, 0 - .dw 0xe5c0, 0xc83e, 0xe5ff, 0xc83e, 0x21, 0 - .dw 0xe640, 0xc83e, 0xe67f, 0xc83e, 0x21, 0 - .dw 0xe6c0, 0xc83e, 0xe6ff, 0xc83e, 0x21, 0 - .dw 0xe740, 0xc83e, 0xe77f, 0xc83e, 0x21, 0 - .dw 0xe7c0, 0xc83e, 0xe7ff, 0xc83e, 0x21, 0 - .dw 0xe840, 0xc83e, 0xe87f, 0xc83e, 0x21, 0 - .dw 0xe8c0, 0xc83e, 0xe8ff, 0xc83e, 0x21, 0 - .dw 0xe940, 0xc83e, 0xe97f, 0xc83e, 0x21, 0 - .dw 0xe9c0, 0xc83e, 0xe9ff, 0xc83e, 0x21, 0 - .dw 0xea40, 0xc83e, 0xea7f, 0xc83e, 0x21, 0 - .dw 0xeac0, 0xc83e, 0xeaff, 0xc83e, 0x21, 0 - .dw 0xeb40, 0xc83e, 0xeb7f, 0xc83e, 0x21, 0 - .dw 0xebc0, 0xc83e, 0xebff, 0xc83e, 0x21, 0 - .dw 0xec40, 0xc83e, 0xec7f, 0xc83e, 0x21, 0 - .dw 0xecc0, 0xc83e, 0xecff, 0xc83e, 0x21, 0 - .dw 0xed40, 0xc83e, 0xed7f, 0xc83e, 0x21, 0 - .dw 0xedc0, 0xc83e, 0xedff, 0xc83e, 0x21, 0 - .dw 0xee40, 0xc83e, 0xee7f, 0xc83e, 0x21, 0 - .dw 0xeec0, 0xc83e, 0xeeff, 0xc83e, 0x21, 0 - .dw 0xef40, 0xc83e, 0xef7f, 0xc83e, 0x21, 0 - .dw 0xefc0, 0xc83e, 0xefff, 0xc83e, 0x21, 0 - .dw 0xf040, 0xc83e, 0xf07f, 0xc83e, 0x21, 0 - .dw 0xf0c0, 0xc83e, 0xf0ff, 0xc83e, 0x21, 0 - .dw 0xf140, 0xc83e, 0xf17f, 0xc83e, 0x21, 0 - .dw 0xf1c0, 0xc83e, 0xf1ff, 0xc83e, 0x21, 0 - .dw 0xf240, 0xc83e, 0xf27f, 0xc83e, 0x21, 0 - .dw 0xf2c0, 0xc83e, 0xf2ff, 0xc83e, 0x21, 0 - .dw 0xf340, 0xc83e, 0xf37f, 0xc83e, 0x21, 0 - .dw 0xf3c0, 0xc83e, 0xf3ff, 0xc83e, 0x21, 0 - .dw 0xf440, 0xc83e, 0xf47f, 0xc83e, 0x21, 0 - .dw 0xf4c0, 0xc83e, 0xf4ff, 0xc83e, 0x21, 0 - .dw 0xf540, 0xc83e, 0xf57f, 0xc83e, 0x21, 0 - .dw 0xf5c0, 0xc83e, 0xf5ff, 0xc83e, 0x21, 0 - .dw 0xf640, 0xc83e, 0xf67f, 0xc83e, 0x21, 0 - .dw 0xf6c0, 0xc83e, 0xf6ff, 0xc83e, 0x21, 0 - .dw 0xf740, 0xc83e, 0xf77f, 0xc83e, 0x21, 0 - .dw 0xf7c0, 0xc83e, 0xf7ff, 0xc83e, 0x21, 0 - .dw 0xf840, 0xc83e, 0xf87f, 0xc83e, 0x21, 0 - .dw 0xf8c0, 0xc83e, 0xf8ff, 0xc83e, 0x21, 0 - .dw 0xf940, 0xc83e, 0xf97f, 0xc83e, 0x21, 0 - .dw 0xf9c0, 0xc83e, 0xffff, 0xc83e, 0x21, 0 - .dw 0x0040, 0xc83f, 0x007f, 0xc83f, 0x21, 0 - .dw 0x00c0, 0xc83f, 0x00ff, 0xc83f, 0x21, 0 - .dw 0x0140, 0xc83f, 0x017f, 0xc83f, 0x21, 0 - .dw 0x01c0, 0xc83f, 0x01ff, 0xc83f, 0x21, 0 - .dw 0x0240, 0xc83f, 0x027f, 0xc83f, 0x21, 0 - .dw 0x02c0, 0xc83f, 0x02ff, 0xc83f, 0x21, 0 - .dw 0x0340, 0xc83f, 0x037f, 0xc83f, 0x21, 0 - .dw 0x03c0, 0xc83f, 0x03ff, 0xc83f, 0x21, 0 - .dw 0x0440, 0xc83f, 0x047f, 0xc83f, 0x21, 0 - .dw 0x04c0, 0xc83f, 0x04ff, 0xc83f, 0x21, 0 - .dw 0x0540, 0xc83f, 0x057f, 0xc83f, 0x21, 0 - .dw 0x05c0, 0xc83f, 0x05ff, 0xc83f, 0x21, 0 - .dw 0x0640, 0xc83f, 0x067f, 0xc83f, 0x21, 0 - .dw 0x06c0, 0xc83f, 0x06ff, 0xc83f, 0x21, 0 - .dw 0x0740, 0xc83f, 0x077f, 0xc83f, 0x21, 0 - .dw 0x07c0, 0xc83f, 0x07ff, 0xc83f, 0x21, 0 - .dw 0x0840, 0xc83f, 0x087f, 0xc83f, 0x21, 0 - .dw 0x08c0, 0xc83f, 0x08ff, 0xc83f, 0x21, 0 - .dw 0x0940, 0xc83f, 0x097f, 0xc83f, 0x21, 0 - .dw 0x09c0, 0xc83f, 0x09ff, 0xc83f, 0x21, 0 - .dw 0x0a40, 0xc83f, 0x0a7f, 0xc83f, 0x21, 0 - .dw 0x0ac0, 0xc83f, 0x0aff, 0xc83f, 0x21, 0 - .dw 0x0b40, 0xc83f, 0x0b7f, 0xc83f, 0x21, 0 - .dw 0x0bc0, 0xc83f, 0x0bff, 0xc83f, 0x21, 0 - .dw 0x0c40, 0xc83f, 0x0c7f, 0xc83f, 0x21, 0 - .dw 0x0cc0, 0xc83f, 0x0cff, 0xc83f, 0x21, 0 - .dw 0x0d40, 0xc83f, 0x0d7f, 0xc83f, 0x21, 0 - .dw 0x0dc0, 0xc83f, 0x0dff, 0xc83f, 0x21, 0 - .dw 0x0e40, 0xc83f, 0x0e7f, 0xc83f, 0x21, 0 - .dw 0x0ec0, 0xc83f, 0x0eff, 0xc83f, 0x21, 0 - .dw 0x0f40, 0xc83f, 0x0f7f, 0xc83f, 0x21, 0 - .dw 0x0fc0, 0xc83f, 0x0fff, 0xc83f, 0x21, 0 - .dw 0x1040, 0xc83f, 0x107f, 0xc83f, 0x21, 0 - .dw 0x10c0, 0xc83f, 0x10ff, 0xc83f, 0x21, 0 - .dw 0x1140, 0xc83f, 0x117f, 0xc83f, 0x21, 0 - .dw 0x11c0, 0xc83f, 0x11ff, 0xc83f, 0x21, 0 - .dw 0x1240, 0xc83f, 0x127f, 0xc83f, 0x21, 0 - .dw 0x12c0, 0xc83f, 0x12ff, 0xc83f, 0x21, 0 - .dw 0x1340, 0xc83f, 0x137f, 0xc83f, 0x21, 0 - .dw 0x13c0, 0xc83f, 0x13ff, 0xc83f, 0x21, 0 - .dw 0x1440, 0xc83f, 0x147f, 0xc83f, 0x21, 0 - .dw 0x14c0, 0xc83f, 0x14ff, 0xc83f, 0x21, 0 - .dw 0x1540, 0xc83f, 0x157f, 0xc83f, 0x21, 0 - .dw 0x15c0, 0xc83f, 0x15ff, 0xc83f, 0x21, 0 - .dw 0x1640, 0xc83f, 0x167f, 0xc83f, 0x21, 0 - .dw 0x16c0, 0xc83f, 0x16ff, 0xc83f, 0x21, 0 - .dw 0x1740, 0xc83f, 0x177f, 0xc83f, 0x21, 0 - .dw 0x17c0, 0xc83f, 0x17ff, 0xc83f, 0x21, 0 - .dw 0x1840, 0xc83f, 0x187f, 0xc83f, 0x21, 0 - .dw 0x18c0, 0xc83f, 0x18ff, 0xc83f, 0x21, 0 - .dw 0x1940, 0xc83f, 0x197f, 0xc83f, 0x21, 0 - .dw 0x19c0, 0xc83f, 0x1fff, 0xc83f, 0x21, 0 - .dw 0x2040, 0xc83f, 0x207f, 0xc83f, 0x21, 0 - .dw 0x20c0, 0xc83f, 0x20ff, 0xc83f, 0x21, 0 - .dw 0x2140, 0xc83f, 0x217f, 0xc83f, 0x21, 0 - .dw 0x21c0, 0xc83f, 0x21ff, 0xc83f, 0x21, 0 - .dw 0x2240, 0xc83f, 0x227f, 0xc83f, 0x21, 0 - .dw 0x22c0, 0xc83f, 0x22ff, 0xc83f, 0x21, 0 - .dw 0x2340, 0xc83f, 0x237f, 0xc83f, 0x21, 0 - .dw 0x23c0, 0xc83f, 0x23ff, 0xc83f, 0x21, 0 - .dw 0x2440, 0xc83f, 0x247f, 0xc83f, 0x21, 0 - .dw 0x24c0, 0xc83f, 0x24ff, 0xc83f, 0x21, 0 - .dw 0x2540, 0xc83f, 0x257f, 0xc83f, 0x21, 0 - .dw 0x25c0, 0xc83f, 0x25ff, 0xc83f, 0x21, 0 - .dw 0x2640, 0xc83f, 0x267f, 0xc83f, 0x21, 0 - .dw 0x26c0, 0xc83f, 0x26ff, 0xc83f, 0x21, 0 - .dw 0x2740, 0xc83f, 0x277f, 0xc83f, 0x21, 0 - .dw 0x27c0, 0xc83f, 0x27ff, 0xc83f, 0x21, 0 - .dw 0x2840, 0xc83f, 0x287f, 0xc83f, 0x21, 0 - .dw 0x28c0, 0xc83f, 0x28ff, 0xc83f, 0x21, 0 - .dw 0x2940, 0xc83f, 0x297f, 0xc83f, 0x21, 0 - .dw 0x29c0, 0xc83f, 0x29ff, 0xc83f, 0x21, 0 - .dw 0x2a40, 0xc83f, 0x2a7f, 0xc83f, 0x21, 0 - .dw 0x2ac0, 0xc83f, 0x2aff, 0xc83f, 0x21, 0 - .dw 0x2b40, 0xc83f, 0x2b7f, 0xc83f, 0x21, 0 - .dw 0x2bc0, 0xc83f, 0x2bff, 0xc83f, 0x21, 0 - .dw 0x2c40, 0xc83f, 0x2c7f, 0xc83f, 0x21, 0 - .dw 0x2cc0, 0xc83f, 0x2cff, 0xc83f, 0x21, 0 - .dw 0x2d40, 0xc83f, 0x2d7f, 0xc83f, 0x21, 0 - .dw 0x2dc0, 0xc83f, 0x2dff, 0xc83f, 0x21, 0 - .dw 0x2e40, 0xc83f, 0x2e7f, 0xc83f, 0x21, 0 - .dw 0x2ec0, 0xc83f, 0x2eff, 0xc83f, 0x21, 0 - .dw 0x2f40, 0xc83f, 0x2f7f, 0xc83f, 0x21, 0 - .dw 0x2fc0, 0xc83f, 0x2fff, 0xc83f, 0x21, 0 - .dw 0x3040, 0xc83f, 0x307f, 0xc83f, 0x21, 0 - .dw 0x30c0, 0xc83f, 0x30ff, 0xc83f, 0x21, 0 - .dw 0x3140, 0xc83f, 0x317f, 0xc83f, 0x21, 0 - .dw 0x31c0, 0xc83f, 0x31ff, 0xc83f, 0x21, 0 - .dw 0x3240, 0xc83f, 0x327f, 0xc83f, 0x21, 0 - .dw 0x32c0, 0xc83f, 0x32ff, 0xc83f, 0x21, 0 - .dw 0x3340, 0xc83f, 0x337f, 0xc83f, 0x21, 0 - .dw 0x33c0, 0xc83f, 0x33ff, 0xc83f, 0x21, 0 - .dw 0x3440, 0xc83f, 0x347f, 0xc83f, 0x21, 0 - .dw 0x34c0, 0xc83f, 0x34ff, 0xc83f, 0x21, 0 - .dw 0x3540, 0xc83f, 0x357f, 0xc83f, 0x21, 0 - .dw 0x35c0, 0xc83f, 0x35ff, 0xc83f, 0x21, 0 - .dw 0x3640, 0xc83f, 0x367f, 0xc83f, 0x21, 0 - .dw 0x36c0, 0xc83f, 0x36ff, 0xc83f, 0x21, 0 - .dw 0x3740, 0xc83f, 0x377f, 0xc83f, 0x21, 0 - .dw 0x37c0, 0xc83f, 0x37ff, 0xc83f, 0x21, 0 - .dw 0x3840, 0xc83f, 0x387f, 0xc83f, 0x21, 0 - .dw 0x38c0, 0xc83f, 0x38ff, 0xc83f, 0x21, 0 - .dw 0x3940, 0xc83f, 0x397f, 0xc83f, 0x21, 0 - .dw 0x39c0, 0xc83f, 0x1fff, 0xc840, 0x21, 0 - .dw 0x3a00, 0xc840, 0x5fff, 0xc840, 0x21, 0 - .dw 0x7a00, 0xc840, 0x9fff, 0xc840, 0x21, 0 - .dw 0xba00, 0xc840, 0xdfff, 0xc840, 0x21, 0 - .dw 0xfa00, 0xc840, 0x1fff, 0xc841, 0x21, 0 - .dw 0x3a00, 0xc841, 0x5fff, 0xc841, 0x21, 0 - .dw 0x7a00, 0xc841, 0x9fff, 0xc841, 0x21, 0 - .dw 0xba00, 0xc841, 0xdfff, 0xc841, 0x21, 0 - .dw 0xfa00, 0xc841, 0x1fff, 0xc842, 0x21, 0 - .dw 0x3a00, 0xc842, 0x5fff, 0xc842, 0x21, 0 - .dw 0x7a00, 0xc842, 0x9fff, 0xc842, 0x21, 0 - .dw 0xba00, 0xc842, 0xdfff, 0xc842, 0x21, 0 - .dw 0xfa00, 0xc842, 0x1fff, 0xc843, 0x21, 0 - .dw 0x3a00, 0xc843, 0xffff, 0xc843, 0x21, 0 - .dw 0x1a00, 0xc844, 0x1fff, 0xc844, 0x21, 0 - .dw 0x3a00, 0xc844, 0x3fff, 0xc844, 0x21, 0 - .dw 0x5a00, 0xc844, 0x5fff, 0xc844, 0x21, 0 - .dw 0x7a00, 0xc844, 0x7fff, 0xc844, 0x21, 0 - .dw 0x9a00, 0xc844, 0x9fff, 0xc844, 0x21, 0 - .dw 0xba00, 0xc844, 0xbfff, 0xc844, 0x21, 0 - .dw 0xda00, 0xc844, 0xdfff, 0xc844, 0x21, 0 - .dw 0xfa00, 0xc844, 0xffff, 0xc844, 0x21, 0 - .dw 0x1a00, 0xc845, 0x1fff, 0xc845, 0x21, 0 - .dw 0x3a00, 0xc845, 0x3fff, 0xc845, 0x21, 0 - .dw 0x5a00, 0xc845, 0x5fff, 0xc845, 0x21, 0 - .dw 0x7a00, 0xc845, 0x7fff, 0xc845, 0x21, 0 - .dw 0x9a00, 0xc845, 0x9fff, 0xc845, 0x21, 0 - .dw 0xba00, 0xc845, 0xbfff, 0xc845, 0x21, 0 - .dw 0xda00, 0xc845, 0xdfff, 0xc845, 0x21, 0 - .dw 0xfa00, 0xc845, 0xffff, 0xc845, 0x21, 0 - .dw 0x1a00, 0xc846, 0x1fff, 0xc846, 0x21, 0 - .dw 0x3a00, 0xc846, 0x3fff, 0xc846, 0x21, 0 - .dw 0x5a00, 0xc846, 0x5fff, 0xc846, 0x21, 0 - .dw 0x7a00, 0xc846, 0x7fff, 0xc846, 0x21, 0 - .dw 0x9a00, 0xc846, 0x9fff, 0xc846, 0x21, 0 - .dw 0xba00, 0xc846, 0xbfff, 0xc846, 0x21, 0 - .dw 0xda00, 0xc846, 0xdfff, 0xc846, 0x21, 0 - .dw 0xfa00, 0xc846, 0xffff, 0xc846, 0x21, 0 - .dw 0x1a00, 0xc847, 0x1fff, 0xc847, 0x21, 0 - .dw 0x3a00, 0xc847, 0x1fff, 0xc850, 0x21, 0 - .dw 0x3a00, 0xc850, 0x5fff, 0xc850, 0x21, 0 - .dw 0x7a00, 0xc850, 0x9fff, 0xc850, 0x21, 0 - .dw 0xba00, 0xc850, 0xdfff, 0xc850, 0x21, 0 - .dw 0xfa00, 0xc850, 0x1fff, 0xc851, 0x21, 0 - .dw 0x3a00, 0xc851, 0x5fff, 0xc851, 0x21, 0 - .dw 0x7a00, 0xc851, 0x9fff, 0xc851, 0x21, 0 - .dw 0xba00, 0xc851, 0xdfff, 0xc851, 0x21, 0 - .dw 0xfa00, 0xc851, 0x1fff, 0xc852, 0x21, 0 - .dw 0x3a00, 0xc852, 0x5fff, 0xc852, 0x21, 0 - .dw 0x7a00, 0xc852, 0x9fff, 0xc852, 0x21, 0 - .dw 0xba00, 0xc852, 0xdfff, 0xc852, 0x21, 0 - .dw 0xfa00, 0xc852, 0xffff, 0xc853, 0x21, 0 - .dw 0x1a00, 0xc854, 0x1fff, 0xc854, 0x21, 0 - .dw 0x3a00, 0xc854, 0x3fff, 0xc854, 0x21, 0 - .dw 0x5a00, 0xc854, 0x5fff, 0xc854, 0x21, 0 - .dw 0x7a00, 0xc854, 0x7fff, 0xc854, 0x21, 0 - .dw 0x9a00, 0xc854, 0x9fff, 0xc854, 0x21, 0 - .dw 0xba00, 0xc854, 0xbfff, 0xc854, 0x21, 0 - .dw 0xda00, 0xc854, 0xdfff, 0xc854, 0x21, 0 - .dw 0xfa00, 0xc854, 0xffff, 0xc854, 0x21, 0 - .dw 0x1a00, 0xc855, 0x1fff, 0xc855, 0x21, 0 - .dw 0x3a00, 0xc855, 0x3fff, 0xc855, 0x21, 0 - .dw 0x5a00, 0xc855, 0x5fff, 0xc855, 0x21, 0 - .dw 0x7a00, 0xc855, 0x7fff, 0xc855, 0x21, 0 - .dw 0x9a00, 0xc855, 0x9fff, 0xc855, 0x21, 0 - .dw 0xba00, 0xc855, 0xbfff, 0xc855, 0x21, 0 - .dw 0xda00, 0xc855, 0xdfff, 0xc855, 0x21, 0 - .dw 0xfa00, 0xc855, 0xffff, 0xc855, 0x21, 0 - .dw 0x1a00, 0xc856, 0x1fff, 0xc856, 0x21, 0 - .dw 0x3a00, 0xc856, 0x3fff, 0xc856, 0x21, 0 - .dw 0x5a00, 0xc856, 0x5fff, 0xc856, 0x21, 0 - .dw 0x7a00, 0xc856, 0x7fff, 0xc856, 0x21, 0 - .dw 0x9a00, 0xc856, 0x9fff, 0xc856, 0x21, 0 - .dw 0xba00, 0xc856, 0xbfff, 0xc856, 0x21, 0 - .dw 0xda00, 0xc856, 0xdfff, 0xc856, 0x21, 0 - .dw 0xfa00, 0xc856, 0xffff, 0xc856, 0x21, 0 - .dw 0x1a00, 0xc857, 0x1fff, 0xc857, 0x21, 0 - .dw 0x3a00, 0xc857, 0xffff, 0xc85f, 0x21, 0 - .dw 0x1a00, 0xc860, 0x3fff, 0xc860, 0x21, 0 - .dw 0x5a00, 0xc860, 0x7fff, 0xc860, 0x21, 0 - .dw 0x9a00, 0xc860, 0xbfff, 0xc860, 0x21, 0 - .dw 0xda00, 0xc860, 0xffff, 0xc860, 0x21, 0 - .dw 0x1a00, 0xc861, 0x3fff, 0xc861, 0x21, 0 - .dw 0x5a00, 0xc861, 0x7fff, 0xc861, 0x21, 0 - .dw 0x9a00, 0xc861, 0xbfff, 0xc861, 0x21, 0 - .dw 0xda00, 0xc861, 0xffff, 0xc861, 0x21, 0 - .dw 0x1a00, 0xc862, 0x3fff, 0xc862, 0x21, 0 - .dw 0x5a00, 0xc862, 0x7fff, 0xc862, 0x21, 0 - .dw 0x9a00, 0xc862, 0xbfff, 0xc862, 0x21, 0 - .dw 0xda00, 0xc862, 0xffff, 0xc862, 0x21, 0 - .dw 0x1a00, 0xc863, 0xffff, 0xc86f, 0x21, 0 - .dw 0x1a00, 0xc870, 0x3fff, 0xc870, 0x21, 0 - .dw 0x5a00, 0xc870, 0x7fff, 0xc870, 0x21, 0 - .dw 0x9a00, 0xc870, 0xbfff, 0xc870, 0x21, 0 - .dw 0xda00, 0xc870, 0xffff, 0xc870, 0x21, 0 - .dw 0x1a00, 0xc871, 0x3fff, 0xc871, 0x21, 0 - .dw 0x5a00, 0xc871, 0x7fff, 0xc871, 0x21, 0 - .dw 0x9a00, 0xc871, 0xbfff, 0xc871, 0x21, 0 - .dw 0xda00, 0xc871, 0xffff, 0xc871, 0x21, 0 - .dw 0x1a00, 0xc872, 0x3fff, 0xc872, 0x21, 0 - .dw 0x5a00, 0xc872, 0x7fff, 0xc872, 0x21, 0 - .dw 0x9a00, 0xc872, 0xbfff, 0xc872, 0x21, 0 - .dw 0xda00, 0xc872, 0xffff, 0xc87f, 0x21, 0 - .dw 0x1a00, 0xc880, 0x1fff, 0xc880, 0x21, 0 - .dw 0x3a00, 0xc880, 0x3fff, 0xc880, 0x21, 0 - .dw 0x5a00, 0xc880, 0x5fff, 0xc880, 0x21, 0 - .dw 0x7a00, 0xc880, 0x7fff, 0xc880, 0x21, 0 - .dw 0x9a00, 0xc880, 0x9fff, 0xc880, 0x21, 0 - .dw 0xba00, 0xc880, 0xbfff, 0xc880, 0x21, 0 - .dw 0xda00, 0xc880, 0xdfff, 0xc880, 0x21, 0 - .dw 0xfa00, 0xc880, 0xffff, 0xc880, 0x21, 0 - .dw 0x1a00, 0xc881, 0x1fff, 0xc881, 0x21, 0 - .dw 0x3a00, 0xc881, 0x3fff, 0xc881, 0x21, 0 - .dw 0x5a00, 0xc881, 0x5fff, 0xc881, 0x21, 0 - .dw 0x7a00, 0xc881, 0x7fff, 0xc881, 0x21, 0 - .dw 0x9a00, 0xc881, 0x9fff, 0xc881, 0x21, 0 - .dw 0xba00, 0xc881, 0xbfff, 0xc881, 0x21, 0 - .dw 0xda00, 0xc881, 0xdfff, 0xc881, 0x21, 0 - .dw 0xfa00, 0xc881, 0xffff, 0xc881, 0x21, 0 - .dw 0x1a00, 0xc882, 0x1fff, 0xc882, 0x21, 0 - .dw 0x3a00, 0xc882, 0x3fff, 0xc882, 0x21, 0 - .dw 0x5a00, 0xc882, 0x5fff, 0xc882, 0x21, 0 - .dw 0x7a00, 0xc882, 0x7fff, 0xc882, 0x21, 0 - .dw 0x9a00, 0xc882, 0x9fff, 0xc882, 0x21, 0 - .dw 0xba00, 0xc882, 0xbfff, 0xc882, 0x21, 0 - .dw 0xda00, 0xc882, 0xdfff, 0xc882, 0x21, 0 - .dw 0xfa00, 0xc882, 0xffff, 0xc882, 0x21, 0 - .dw 0x1a00, 0xc883, 0x1fff, 0xc883, 0x21, 0 - .dw 0x3a00, 0xc883, 0xffff, 0xc883, 0x21, 0 - .dw 0x1a00, 0xc884, 0x1fff, 0xc884, 0x21, 0 - .dw 0x3a00, 0xc884, 0x3fff, 0xc884, 0x21, 0 - .dw 0x5a00, 0xc884, 0x5fff, 0xc884, 0x21, 0 - .dw 0x7a00, 0xc884, 0x7fff, 0xc884, 0x21, 0 - .dw 0x9a00, 0xc884, 0x9fff, 0xc884, 0x21, 0 - .dw 0xba00, 0xc884, 0xbfff, 0xc884, 0x21, 0 - .dw 0xda00, 0xc884, 0xdfff, 0xc884, 0x21, 0 - .dw 0xfa00, 0xc884, 0xffff, 0xc884, 0x21, 0 - .dw 0x1a00, 0xc885, 0x1fff, 0xc885, 0x21, 0 - .dw 0x3a00, 0xc885, 0x3fff, 0xc885, 0x21, 0 - .dw 0x5a00, 0xc885, 0x5fff, 0xc885, 0x21, 0 - .dw 0x7a00, 0xc885, 0x7fff, 0xc885, 0x21, 0 - .dw 0x9a00, 0xc885, 0x9fff, 0xc885, 0x21, 0 - .dw 0xba00, 0xc885, 0xbfff, 0xc885, 0x21, 0 - .dw 0xda00, 0xc885, 0xdfff, 0xc885, 0x21, 0 - .dw 0xfa00, 0xc885, 0xffff, 0xc885, 0x21, 0 - .dw 0x1a00, 0xc886, 0x1fff, 0xc886, 0x21, 0 - .dw 0x3a00, 0xc886, 0x3fff, 0xc886, 0x21, 0 - .dw 0x5a00, 0xc886, 0x5fff, 0xc886, 0x21, 0 - .dw 0x7a00, 0xc886, 0x7fff, 0xc886, 0x21, 0 - .dw 0x9a00, 0xc886, 0x9fff, 0xc886, 0x21, 0 - .dw 0xba00, 0xc886, 0xbfff, 0xc886, 0x21, 0 - .dw 0xda00, 0xc886, 0xdfff, 0xc886, 0x21, 0 - .dw 0xfa00, 0xc886, 0xffff, 0xc886, 0x21, 0 - .dw 0x1a00, 0xc887, 0x1fff, 0xc887, 0x21, 0 - .dw 0x3a00, 0xc887, 0x1fff, 0xc888, 0x21, 0 - .dw 0x2040, 0xc888, 0x207f, 0xc888, 0x21, 0 - .dw 0x20c0, 0xc888, 0x20ff, 0xc888, 0x21, 0 - .dw 0x2140, 0xc888, 0x217f, 0xc888, 0x21, 0 - .dw 0x21c0, 0xc888, 0x21ff, 0xc888, 0x21, 0 - .dw 0x2240, 0xc888, 0x227f, 0xc888, 0x21, 0 - .dw 0x22c0, 0xc888, 0x22ff, 0xc888, 0x21, 0 - .dw 0x2340, 0xc888, 0x237f, 0xc888, 0x21, 0 - .dw 0x23c0, 0xc888, 0x23ff, 0xc888, 0x21, 0 - .dw 0x2440, 0xc888, 0x247f, 0xc888, 0x21, 0 - .dw 0x24c0, 0xc888, 0x24ff, 0xc888, 0x21, 0 - .dw 0x2540, 0xc888, 0x257f, 0xc888, 0x21, 0 - .dw 0x25c0, 0xc888, 0x25ff, 0xc888, 0x21, 0 - .dw 0x2640, 0xc888, 0x267f, 0xc888, 0x21, 0 - .dw 0x26c0, 0xc888, 0x26ff, 0xc888, 0x21, 0 - .dw 0x2740, 0xc888, 0x277f, 0xc888, 0x21, 0 - .dw 0x27c0, 0xc888, 0x27ff, 0xc888, 0x21, 0 - .dw 0x2840, 0xc888, 0x287f, 0xc888, 0x21, 0 - .dw 0x28c0, 0xc888, 0x28ff, 0xc888, 0x21, 0 - .dw 0x2940, 0xc888, 0x297f, 0xc888, 0x21, 0 - .dw 0x29c0, 0xc888, 0x29ff, 0xc888, 0x21, 0 - .dw 0x2a40, 0xc888, 0x2a7f, 0xc888, 0x21, 0 - .dw 0x2ac0, 0xc888, 0x2aff, 0xc888, 0x21, 0 - .dw 0x2b40, 0xc888, 0x2b7f, 0xc888, 0x21, 0 - .dw 0x2bc0, 0xc888, 0x2bff, 0xc888, 0x21, 0 - .dw 0x2c40, 0xc888, 0x2c7f, 0xc888, 0x21, 0 - .dw 0x2cc0, 0xc888, 0x2cff, 0xc888, 0x21, 0 - .dw 0x2d40, 0xc888, 0x2d7f, 0xc888, 0x21, 0 - .dw 0x2dc0, 0xc888, 0x2dff, 0xc888, 0x21, 0 - .dw 0x2e40, 0xc888, 0x2e7f, 0xc888, 0x21, 0 - .dw 0x2ec0, 0xc888, 0x2eff, 0xc888, 0x21, 0 - .dw 0x2f40, 0xc888, 0x2f7f, 0xc888, 0x21, 0 - .dw 0x2fc0, 0xc888, 0x2fff, 0xc888, 0x21, 0 - .dw 0x3040, 0xc888, 0x307f, 0xc888, 0x21, 0 - .dw 0x30c0, 0xc888, 0x30ff, 0xc888, 0x21, 0 - .dw 0x3140, 0xc888, 0x317f, 0xc888, 0x21, 0 - .dw 0x31c0, 0xc888, 0x31ff, 0xc888, 0x21, 0 - .dw 0x3240, 0xc888, 0x327f, 0xc888, 0x21, 0 - .dw 0x32c0, 0xc888, 0x32ff, 0xc888, 0x21, 0 - .dw 0x3340, 0xc888, 0x337f, 0xc888, 0x21, 0 - .dw 0x33c0, 0xc888, 0x33ff, 0xc888, 0x21, 0 - .dw 0x3440, 0xc888, 0x347f, 0xc888, 0x21, 0 - .dw 0x34c0, 0xc888, 0x34ff, 0xc888, 0x21, 0 - .dw 0x3540, 0xc888, 0x357f, 0xc888, 0x21, 0 - .dw 0x35c0, 0xc888, 0x35ff, 0xc888, 0x21, 0 - .dw 0x3640, 0xc888, 0x367f, 0xc888, 0x21, 0 - .dw 0x36c0, 0xc888, 0x36ff, 0xc888, 0x21, 0 - .dw 0x3740, 0xc888, 0x377f, 0xc888, 0x21, 0 - .dw 0x37c0, 0xc888, 0x37ff, 0xc888, 0x21, 0 - .dw 0x3840, 0xc888, 0x387f, 0xc888, 0x21, 0 - .dw 0x38c0, 0xc888, 0x38ff, 0xc888, 0x21, 0 - .dw 0x3940, 0xc888, 0x397f, 0xc888, 0x21, 0 - .dw 0x39c0, 0xc888, 0x5fff, 0xc888, 0x21, 0 - .dw 0x6040, 0xc888, 0x607f, 0xc888, 0x21, 0 - .dw 0x60c0, 0xc888, 0x60ff, 0xc888, 0x21, 0 - .dw 0x6140, 0xc888, 0x617f, 0xc888, 0x21, 0 - .dw 0x61c0, 0xc888, 0x61ff, 0xc888, 0x21, 0 - .dw 0x6240, 0xc888, 0x627f, 0xc888, 0x21, 0 - .dw 0x62c0, 0xc888, 0x62ff, 0xc888, 0x21, 0 - .dw 0x6340, 0xc888, 0x637f, 0xc888, 0x21, 0 - .dw 0x63c0, 0xc888, 0x63ff, 0xc888, 0x21, 0 - .dw 0x6440, 0xc888, 0x647f, 0xc888, 0x21, 0 - .dw 0x64c0, 0xc888, 0x64ff, 0xc888, 0x21, 0 - .dw 0x6540, 0xc888, 0x657f, 0xc888, 0x21, 0 - .dw 0x65c0, 0xc888, 0x65ff, 0xc888, 0x21, 0 - .dw 0x6640, 0xc888, 0x667f, 0xc888, 0x21, 0 - .dw 0x66c0, 0xc888, 0x66ff, 0xc888, 0x21, 0 - .dw 0x6740, 0xc888, 0x677f, 0xc888, 0x21, 0 - .dw 0x67c0, 0xc888, 0x67ff, 0xc888, 0x21, 0 - .dw 0x6840, 0xc888, 0x687f, 0xc888, 0x21, 0 - .dw 0x68c0, 0xc888, 0x68ff, 0xc888, 0x21, 0 - .dw 0x6940, 0xc888, 0x697f, 0xc888, 0x21, 0 - .dw 0x69c0, 0xc888, 0x69ff, 0xc888, 0x21, 0 - .dw 0x6a40, 0xc888, 0x6a7f, 0xc888, 0x21, 0 - .dw 0x6ac0, 0xc888, 0x6aff, 0xc888, 0x21, 0 - .dw 0x6b40, 0xc888, 0x6b7f, 0xc888, 0x21, 0 - .dw 0x6bc0, 0xc888, 0x6bff, 0xc888, 0x21, 0 - .dw 0x6c40, 0xc888, 0x6c7f, 0xc888, 0x21, 0 - .dw 0x6cc0, 0xc888, 0x6cff, 0xc888, 0x21, 0 - .dw 0x6d40, 0xc888, 0x6d7f, 0xc888, 0x21, 0 - .dw 0x6dc0, 0xc888, 0x6dff, 0xc888, 0x21, 0 - .dw 0x6e40, 0xc888, 0x6e7f, 0xc888, 0x21, 0 - .dw 0x6ec0, 0xc888, 0x6eff, 0xc888, 0x21, 0 - .dw 0x6f40, 0xc888, 0x6f7f, 0xc888, 0x21, 0 - .dw 0x6fc0, 0xc888, 0x6fff, 0xc888, 0x21, 0 - .dw 0x7040, 0xc888, 0x707f, 0xc888, 0x21, 0 - .dw 0x70c0, 0xc888, 0x70ff, 0xc888, 0x21, 0 - .dw 0x7140, 0xc888, 0x717f, 0xc888, 0x21, 0 - .dw 0x71c0, 0xc888, 0x71ff, 0xc888, 0x21, 0 - .dw 0x7240, 0xc888, 0x727f, 0xc888, 0x21, 0 - .dw 0x72c0, 0xc888, 0x72ff, 0xc888, 0x21, 0 - .dw 0x7340, 0xc888, 0x737f, 0xc888, 0x21, 0 - .dw 0x73c0, 0xc888, 0x73ff, 0xc888, 0x21, 0 - .dw 0x7440, 0xc888, 0x747f, 0xc888, 0x21, 0 - .dw 0x74c0, 0xc888, 0x74ff, 0xc888, 0x21, 0 - .dw 0x7540, 0xc888, 0x757f, 0xc888, 0x21, 0 - .dw 0x75c0, 0xc888, 0x75ff, 0xc888, 0x21, 0 - .dw 0x7640, 0xc888, 0x767f, 0xc888, 0x21, 0 - .dw 0x76c0, 0xc888, 0x76ff, 0xc888, 0x21, 0 - .dw 0x7740, 0xc888, 0x777f, 0xc888, 0x21, 0 - .dw 0x77c0, 0xc888, 0x77ff, 0xc888, 0x21, 0 - .dw 0x7840, 0xc888, 0x787f, 0xc888, 0x21, 0 - .dw 0x78c0, 0xc888, 0x78ff, 0xc888, 0x21, 0 - .dw 0x7940, 0xc888, 0x797f, 0xc888, 0x21, 0 - .dw 0x79c0, 0xc888, 0x9fff, 0xc888, 0x21, 0 - .dw 0xa040, 0xc888, 0xa07f, 0xc888, 0x21, 0 - .dw 0xa0c0, 0xc888, 0xa0ff, 0xc888, 0x21, 0 - .dw 0xa140, 0xc888, 0xa17f, 0xc888, 0x21, 0 - .dw 0xa1c0, 0xc888, 0xa1ff, 0xc888, 0x21, 0 - .dw 0xa240, 0xc888, 0xa27f, 0xc888, 0x21, 0 - .dw 0xa2c0, 0xc888, 0xa2ff, 0xc888, 0x21, 0 - .dw 0xa340, 0xc888, 0xa37f, 0xc888, 0x21, 0 - .dw 0xa3c0, 0xc888, 0xa3ff, 0xc888, 0x21, 0 - .dw 0xa440, 0xc888, 0xa47f, 0xc888, 0x21, 0 - .dw 0xa4c0, 0xc888, 0xa4ff, 0xc888, 0x21, 0 - .dw 0xa540, 0xc888, 0xa57f, 0xc888, 0x21, 0 - .dw 0xa5c0, 0xc888, 0xa5ff, 0xc888, 0x21, 0 - .dw 0xa640, 0xc888, 0xa67f, 0xc888, 0x21, 0 - .dw 0xa6c0, 0xc888, 0xa6ff, 0xc888, 0x21, 0 - .dw 0xa740, 0xc888, 0xa77f, 0xc888, 0x21, 0 - .dw 0xa7c0, 0xc888, 0xa7ff, 0xc888, 0x21, 0 - .dw 0xa840, 0xc888, 0xa87f, 0xc888, 0x21, 0 - .dw 0xa8c0, 0xc888, 0xa8ff, 0xc888, 0x21, 0 - .dw 0xa940, 0xc888, 0xa97f, 0xc888, 0x21, 0 - .dw 0xa9c0, 0xc888, 0xa9ff, 0xc888, 0x21, 0 - .dw 0xaa40, 0xc888, 0xaa7f, 0xc888, 0x21, 0 - .dw 0xaac0, 0xc888, 0xaaff, 0xc888, 0x21, 0 - .dw 0xab40, 0xc888, 0xab7f, 0xc888, 0x21, 0 - .dw 0xabc0, 0xc888, 0xabff, 0xc888, 0x21, 0 - .dw 0xac40, 0xc888, 0xac7f, 0xc888, 0x21, 0 - .dw 0xacc0, 0xc888, 0xacff, 0xc888, 0x21, 0 - .dw 0xad40, 0xc888, 0xad7f, 0xc888, 0x21, 0 - .dw 0xadc0, 0xc888, 0xadff, 0xc888, 0x21, 0 - .dw 0xae40, 0xc888, 0xae7f, 0xc888, 0x21, 0 - .dw 0xaec0, 0xc888, 0xaeff, 0xc888, 0x21, 0 - .dw 0xaf40, 0xc888, 0xaf7f, 0xc888, 0x21, 0 - .dw 0xafc0, 0xc888, 0xafff, 0xc888, 0x21, 0 - .dw 0xb040, 0xc888, 0xb07f, 0xc888, 0x21, 0 - .dw 0xb0c0, 0xc888, 0xb0ff, 0xc888, 0x21, 0 - .dw 0xb140, 0xc888, 0xb17f, 0xc888, 0x21, 0 - .dw 0xb1c0, 0xc888, 0xb1ff, 0xc888, 0x21, 0 - .dw 0xb240, 0xc888, 0xb27f, 0xc888, 0x21, 0 - .dw 0xb2c0, 0xc888, 0xb2ff, 0xc888, 0x21, 0 - .dw 0xb340, 0xc888, 0xb37f, 0xc888, 0x21, 0 - .dw 0xb3c0, 0xc888, 0xb3ff, 0xc888, 0x21, 0 - .dw 0xb440, 0xc888, 0xb47f, 0xc888, 0x21, 0 - .dw 0xb4c0, 0xc888, 0xb4ff, 0xc888, 0x21, 0 - .dw 0xb540, 0xc888, 0xb57f, 0xc888, 0x21, 0 - .dw 0xb5c0, 0xc888, 0xb5ff, 0xc888, 0x21, 0 - .dw 0xb640, 0xc888, 0xb67f, 0xc888, 0x21, 0 - .dw 0xb6c0, 0xc888, 0xb6ff, 0xc888, 0x21, 0 - .dw 0xb740, 0xc888, 0xb77f, 0xc888, 0x21, 0 - .dw 0xb7c0, 0xc888, 0xb7ff, 0xc888, 0x21, 0 - .dw 0xb840, 0xc888, 0xb87f, 0xc888, 0x21, 0 - .dw 0xb8c0, 0xc888, 0xb8ff, 0xc888, 0x21, 0 - .dw 0xb940, 0xc888, 0xb97f, 0xc888, 0x21, 0 - .dw 0xb9c0, 0xc888, 0xdfff, 0xc888, 0x21, 0 - .dw 0xe040, 0xc888, 0xe07f, 0xc888, 0x21, 0 - .dw 0xe0c0, 0xc888, 0xe0ff, 0xc888, 0x21, 0 - .dw 0xe140, 0xc888, 0xe17f, 0xc888, 0x21, 0 - .dw 0xe1c0, 0xc888, 0xe1ff, 0xc888, 0x21, 0 - .dw 0xe240, 0xc888, 0xe27f, 0xc888, 0x21, 0 - .dw 0xe2c0, 0xc888, 0xe2ff, 0xc888, 0x21, 0 - .dw 0xe340, 0xc888, 0xe37f, 0xc888, 0x21, 0 - .dw 0xe3c0, 0xc888, 0xe3ff, 0xc888, 0x21, 0 - .dw 0xe440, 0xc888, 0xe47f, 0xc888, 0x21, 0 - .dw 0xe4c0, 0xc888, 0xe4ff, 0xc888, 0x21, 0 - .dw 0xe540, 0xc888, 0xe57f, 0xc888, 0x21, 0 - .dw 0xe5c0, 0xc888, 0xe5ff, 0xc888, 0x21, 0 - .dw 0xe640, 0xc888, 0xe67f, 0xc888, 0x21, 0 - .dw 0xe6c0, 0xc888, 0xe6ff, 0xc888, 0x21, 0 - .dw 0xe740, 0xc888, 0xe77f, 0xc888, 0x21, 0 - .dw 0xe7c0, 0xc888, 0xe7ff, 0xc888, 0x21, 0 - .dw 0xe840, 0xc888, 0xe87f, 0xc888, 0x21, 0 - .dw 0xe8c0, 0xc888, 0xe8ff, 0xc888, 0x21, 0 - .dw 0xe940, 0xc888, 0xe97f, 0xc888, 0x21, 0 - .dw 0xe9c0, 0xc888, 0xe9ff, 0xc888, 0x21, 0 - .dw 0xea40, 0xc888, 0xea7f, 0xc888, 0x21, 0 - .dw 0xeac0, 0xc888, 0xeaff, 0xc888, 0x21, 0 - .dw 0xeb40, 0xc888, 0xeb7f, 0xc888, 0x21, 0 - .dw 0xebc0, 0xc888, 0xebff, 0xc888, 0x21, 0 - .dw 0xec40, 0xc888, 0xec7f, 0xc888, 0x21, 0 - .dw 0xecc0, 0xc888, 0xecff, 0xc888, 0x21, 0 - .dw 0xed40, 0xc888, 0xed7f, 0xc888, 0x21, 0 - .dw 0xedc0, 0xc888, 0xedff, 0xc888, 0x21, 0 - .dw 0xee40, 0xc888, 0xee7f, 0xc888, 0x21, 0 - .dw 0xeec0, 0xc888, 0xeeff, 0xc888, 0x21, 0 - .dw 0xef40, 0xc888, 0xef7f, 0xc888, 0x21, 0 - .dw 0xefc0, 0xc888, 0xefff, 0xc888, 0x21, 0 - .dw 0xf040, 0xc888, 0xf07f, 0xc888, 0x21, 0 - .dw 0xf0c0, 0xc888, 0xf0ff, 0xc888, 0x21, 0 - .dw 0xf140, 0xc888, 0xf17f, 0xc888, 0x21, 0 - .dw 0xf1c0, 0xc888, 0xf1ff, 0xc888, 0x21, 0 - .dw 0xf240, 0xc888, 0xf27f, 0xc888, 0x21, 0 - .dw 0xf2c0, 0xc888, 0xf2ff, 0xc888, 0x21, 0 - .dw 0xf340, 0xc888, 0xf37f, 0xc888, 0x21, 0 - .dw 0xf3c0, 0xc888, 0xf3ff, 0xc888, 0x21, 0 - .dw 0xf440, 0xc888, 0xf47f, 0xc888, 0x21, 0 - .dw 0xf4c0, 0xc888, 0xf4ff, 0xc888, 0x21, 0 - .dw 0xf540, 0xc888, 0xf57f, 0xc888, 0x21, 0 - .dw 0xf5c0, 0xc888, 0xf5ff, 0xc888, 0x21, 0 - .dw 0xf640, 0xc888, 0xf67f, 0xc888, 0x21, 0 - .dw 0xf6c0, 0xc888, 0xf6ff, 0xc888, 0x21, 0 - .dw 0xf740, 0xc888, 0xf77f, 0xc888, 0x21, 0 - .dw 0xf7c0, 0xc888, 0xf7ff, 0xc888, 0x21, 0 - .dw 0xf840, 0xc888, 0xf87f, 0xc888, 0x21, 0 - .dw 0xf8c0, 0xc888, 0xf8ff, 0xc888, 0x21, 0 - .dw 0xf940, 0xc888, 0xf97f, 0xc888, 0x21, 0 - .dw 0xf9c0, 0xc888, 0x1fff, 0xc889, 0x21, 0 - .dw 0x2040, 0xc889, 0x207f, 0xc889, 0x21, 0 - .dw 0x20c0, 0xc889, 0x20ff, 0xc889, 0x21, 0 - .dw 0x2140, 0xc889, 0x217f, 0xc889, 0x21, 0 - .dw 0x21c0, 0xc889, 0x21ff, 0xc889, 0x21, 0 - .dw 0x2240, 0xc889, 0x227f, 0xc889, 0x21, 0 - .dw 0x22c0, 0xc889, 0x22ff, 0xc889, 0x21, 0 - .dw 0x2340, 0xc889, 0x237f, 0xc889, 0x21, 0 - .dw 0x23c0, 0xc889, 0x23ff, 0xc889, 0x21, 0 - .dw 0x2440, 0xc889, 0x247f, 0xc889, 0x21, 0 - .dw 0x24c0, 0xc889, 0x24ff, 0xc889, 0x21, 0 - .dw 0x2540, 0xc889, 0x257f, 0xc889, 0x21, 0 - .dw 0x25c0, 0xc889, 0x25ff, 0xc889, 0x21, 0 - .dw 0x2640, 0xc889, 0x267f, 0xc889, 0x21, 0 - .dw 0x26c0, 0xc889, 0x26ff, 0xc889, 0x21, 0 - .dw 0x2740, 0xc889, 0x277f, 0xc889, 0x21, 0 - .dw 0x27c0, 0xc889, 0x27ff, 0xc889, 0x21, 0 - .dw 0x2840, 0xc889, 0x287f, 0xc889, 0x21, 0 - .dw 0x28c0, 0xc889, 0x28ff, 0xc889, 0x21, 0 - .dw 0x2940, 0xc889, 0x297f, 0xc889, 0x21, 0 - .dw 0x29c0, 0xc889, 0x29ff, 0xc889, 0x21, 0 - .dw 0x2a40, 0xc889, 0x2a7f, 0xc889, 0x21, 0 - .dw 0x2ac0, 0xc889, 0x2aff, 0xc889, 0x21, 0 - .dw 0x2b40, 0xc889, 0x2b7f, 0xc889, 0x21, 0 - .dw 0x2bc0, 0xc889, 0x2bff, 0xc889, 0x21, 0 - .dw 0x2c40, 0xc889, 0x2c7f, 0xc889, 0x21, 0 - .dw 0x2cc0, 0xc889, 0x2cff, 0xc889, 0x21, 0 - .dw 0x2d40, 0xc889, 0x2d7f, 0xc889, 0x21, 0 - .dw 0x2dc0, 0xc889, 0x2dff, 0xc889, 0x21, 0 - .dw 0x2e40, 0xc889, 0x2e7f, 0xc889, 0x21, 0 - .dw 0x2ec0, 0xc889, 0x2eff, 0xc889, 0x21, 0 - .dw 0x2f40, 0xc889, 0x2f7f, 0xc889, 0x21, 0 - .dw 0x2fc0, 0xc889, 0x2fff, 0xc889, 0x21, 0 - .dw 0x3040, 0xc889, 0x307f, 0xc889, 0x21, 0 - .dw 0x30c0, 0xc889, 0x30ff, 0xc889, 0x21, 0 - .dw 0x3140, 0xc889, 0x317f, 0xc889, 0x21, 0 - .dw 0x31c0, 0xc889, 0x31ff, 0xc889, 0x21, 0 - .dw 0x3240, 0xc889, 0x327f, 0xc889, 0x21, 0 - .dw 0x32c0, 0xc889, 0x32ff, 0xc889, 0x21, 0 - .dw 0x3340, 0xc889, 0x337f, 0xc889, 0x21, 0 - .dw 0x33c0, 0xc889, 0x33ff, 0xc889, 0x21, 0 - .dw 0x3440, 0xc889, 0x347f, 0xc889, 0x21, 0 - .dw 0x34c0, 0xc889, 0x34ff, 0xc889, 0x21, 0 - .dw 0x3540, 0xc889, 0x357f, 0xc889, 0x21, 0 - .dw 0x35c0, 0xc889, 0x35ff, 0xc889, 0x21, 0 - .dw 0x3640, 0xc889, 0x367f, 0xc889, 0x21, 0 - .dw 0x36c0, 0xc889, 0x36ff, 0xc889, 0x21, 0 - .dw 0x3740, 0xc889, 0x377f, 0xc889, 0x21, 0 - .dw 0x37c0, 0xc889, 0x37ff, 0xc889, 0x21, 0 - .dw 0x3840, 0xc889, 0x387f, 0xc889, 0x21, 0 - .dw 0x38c0, 0xc889, 0x38ff, 0xc889, 0x21, 0 - .dw 0x3940, 0xc889, 0x397f, 0xc889, 0x21, 0 - .dw 0x39c0, 0xc889, 0x5fff, 0xc889, 0x21, 0 - .dw 0x6040, 0xc889, 0x607f, 0xc889, 0x21, 0 - .dw 0x60c0, 0xc889, 0x60ff, 0xc889, 0x21, 0 - .dw 0x6140, 0xc889, 0x617f, 0xc889, 0x21, 0 - .dw 0x61c0, 0xc889, 0x61ff, 0xc889, 0x21, 0 - .dw 0x6240, 0xc889, 0x627f, 0xc889, 0x21, 0 - .dw 0x62c0, 0xc889, 0x62ff, 0xc889, 0x21, 0 - .dw 0x6340, 0xc889, 0x637f, 0xc889, 0x21, 0 - .dw 0x63c0, 0xc889, 0x63ff, 0xc889, 0x21, 0 - .dw 0x6440, 0xc889, 0x647f, 0xc889, 0x21, 0 - .dw 0x64c0, 0xc889, 0x64ff, 0xc889, 0x21, 0 - .dw 0x6540, 0xc889, 0x657f, 0xc889, 0x21, 0 - .dw 0x65c0, 0xc889, 0x65ff, 0xc889, 0x21, 0 - .dw 0x6640, 0xc889, 0x667f, 0xc889, 0x21, 0 - .dw 0x66c0, 0xc889, 0x66ff, 0xc889, 0x21, 0 - .dw 0x6740, 0xc889, 0x677f, 0xc889, 0x21, 0 - .dw 0x67c0, 0xc889, 0x67ff, 0xc889, 0x21, 0 - .dw 0x6840, 0xc889, 0x687f, 0xc889, 0x21, 0 - .dw 0x68c0, 0xc889, 0x68ff, 0xc889, 0x21, 0 - .dw 0x6940, 0xc889, 0x697f, 0xc889, 0x21, 0 - .dw 0x69c0, 0xc889, 0x69ff, 0xc889, 0x21, 0 - .dw 0x6a40, 0xc889, 0x6a7f, 0xc889, 0x21, 0 - .dw 0x6ac0, 0xc889, 0x6aff, 0xc889, 0x21, 0 - .dw 0x6b40, 0xc889, 0x6b7f, 0xc889, 0x21, 0 - .dw 0x6bc0, 0xc889, 0x6bff, 0xc889, 0x21, 0 - .dw 0x6c40, 0xc889, 0x6c7f, 0xc889, 0x21, 0 - .dw 0x6cc0, 0xc889, 0x6cff, 0xc889, 0x21, 0 - .dw 0x6d40, 0xc889, 0x6d7f, 0xc889, 0x21, 0 - .dw 0x6dc0, 0xc889, 0x6dff, 0xc889, 0x21, 0 - .dw 0x6e40, 0xc889, 0x6e7f, 0xc889, 0x21, 0 - .dw 0x6ec0, 0xc889, 0x6eff, 0xc889, 0x21, 0 - .dw 0x6f40, 0xc889, 0x6f7f, 0xc889, 0x21, 0 - .dw 0x6fc0, 0xc889, 0x6fff, 0xc889, 0x21, 0 - .dw 0x7040, 0xc889, 0x707f, 0xc889, 0x21, 0 - .dw 0x70c0, 0xc889, 0x70ff, 0xc889, 0x21, 0 - .dw 0x7140, 0xc889, 0x717f, 0xc889, 0x21, 0 - .dw 0x71c0, 0xc889, 0x71ff, 0xc889, 0x21, 0 - .dw 0x7240, 0xc889, 0x727f, 0xc889, 0x21, 0 - .dw 0x72c0, 0xc889, 0x72ff, 0xc889, 0x21, 0 - .dw 0x7340, 0xc889, 0x737f, 0xc889, 0x21, 0 - .dw 0x73c0, 0xc889, 0x73ff, 0xc889, 0x21, 0 - .dw 0x7440, 0xc889, 0x747f, 0xc889, 0x21, 0 - .dw 0x74c0, 0xc889, 0x74ff, 0xc889, 0x21, 0 - .dw 0x7540, 0xc889, 0x757f, 0xc889, 0x21, 0 - .dw 0x75c0, 0xc889, 0x75ff, 0xc889, 0x21, 0 - .dw 0x7640, 0xc889, 0x767f, 0xc889, 0x21, 0 - .dw 0x76c0, 0xc889, 0x76ff, 0xc889, 0x21, 0 - .dw 0x7740, 0xc889, 0x777f, 0xc889, 0x21, 0 - .dw 0x77c0, 0xc889, 0x77ff, 0xc889, 0x21, 0 - .dw 0x7840, 0xc889, 0x787f, 0xc889, 0x21, 0 - .dw 0x78c0, 0xc889, 0x78ff, 0xc889, 0x21, 0 - .dw 0x7940, 0xc889, 0x797f, 0xc889, 0x21, 0 - .dw 0x79c0, 0xc889, 0x9fff, 0xc889, 0x21, 0 - .dw 0xa040, 0xc889, 0xa07f, 0xc889, 0x21, 0 - .dw 0xa0c0, 0xc889, 0xa0ff, 0xc889, 0x21, 0 - .dw 0xa140, 0xc889, 0xa17f, 0xc889, 0x21, 0 - .dw 0xa1c0, 0xc889, 0xa1ff, 0xc889, 0x21, 0 - .dw 0xa240, 0xc889, 0xa27f, 0xc889, 0x21, 0 - .dw 0xa2c0, 0xc889, 0xa2ff, 0xc889, 0x21, 0 - .dw 0xa340, 0xc889, 0xa37f, 0xc889, 0x21, 0 - .dw 0xa3c0, 0xc889, 0xa3ff, 0xc889, 0x21, 0 - .dw 0xa440, 0xc889, 0xa47f, 0xc889, 0x21, 0 - .dw 0xa4c0, 0xc889, 0xa4ff, 0xc889, 0x21, 0 - .dw 0xa540, 0xc889, 0xa57f, 0xc889, 0x21, 0 - .dw 0xa5c0, 0xc889, 0xa5ff, 0xc889, 0x21, 0 - .dw 0xa640, 0xc889, 0xa67f, 0xc889, 0x21, 0 - .dw 0xa6c0, 0xc889, 0xa6ff, 0xc889, 0x21, 0 - .dw 0xa740, 0xc889, 0xa77f, 0xc889, 0x21, 0 - .dw 0xa7c0, 0xc889, 0xa7ff, 0xc889, 0x21, 0 - .dw 0xa840, 0xc889, 0xa87f, 0xc889, 0x21, 0 - .dw 0xa8c0, 0xc889, 0xa8ff, 0xc889, 0x21, 0 - .dw 0xa940, 0xc889, 0xa97f, 0xc889, 0x21, 0 - .dw 0xa9c0, 0xc889, 0xa9ff, 0xc889, 0x21, 0 - .dw 0xaa40, 0xc889, 0xaa7f, 0xc889, 0x21, 0 - .dw 0xaac0, 0xc889, 0xaaff, 0xc889, 0x21, 0 - .dw 0xab40, 0xc889, 0xab7f, 0xc889, 0x21, 0 - .dw 0xabc0, 0xc889, 0xabff, 0xc889, 0x21, 0 - .dw 0xac40, 0xc889, 0xac7f, 0xc889, 0x21, 0 - .dw 0xacc0, 0xc889, 0xacff, 0xc889, 0x21, 0 - .dw 0xad40, 0xc889, 0xad7f, 0xc889, 0x21, 0 - .dw 0xadc0, 0xc889, 0xadff, 0xc889, 0x21, 0 - .dw 0xae40, 0xc889, 0xae7f, 0xc889, 0x21, 0 - .dw 0xaec0, 0xc889, 0xaeff, 0xc889, 0x21, 0 - .dw 0xaf40, 0xc889, 0xaf7f, 0xc889, 0x21, 0 - .dw 0xafc0, 0xc889, 0xafff, 0xc889, 0x21, 0 - .dw 0xb040, 0xc889, 0xb07f, 0xc889, 0x21, 0 - .dw 0xb0c0, 0xc889, 0xb0ff, 0xc889, 0x21, 0 - .dw 0xb140, 0xc889, 0xb17f, 0xc889, 0x21, 0 - .dw 0xb1c0, 0xc889, 0xb1ff, 0xc889, 0x21, 0 - .dw 0xb240, 0xc889, 0xb27f, 0xc889, 0x21, 0 - .dw 0xb2c0, 0xc889, 0xb2ff, 0xc889, 0x21, 0 - .dw 0xb340, 0xc889, 0xb37f, 0xc889, 0x21, 0 - .dw 0xb3c0, 0xc889, 0xb3ff, 0xc889, 0x21, 0 - .dw 0xb440, 0xc889, 0xb47f, 0xc889, 0x21, 0 - .dw 0xb4c0, 0xc889, 0xb4ff, 0xc889, 0x21, 0 - .dw 0xb540, 0xc889, 0xb57f, 0xc889, 0x21, 0 - .dw 0xb5c0, 0xc889, 0xb5ff, 0xc889, 0x21, 0 - .dw 0xb640, 0xc889, 0xb67f, 0xc889, 0x21, 0 - .dw 0xb6c0, 0xc889, 0xb6ff, 0xc889, 0x21, 0 - .dw 0xb740, 0xc889, 0xb77f, 0xc889, 0x21, 0 - .dw 0xb7c0, 0xc889, 0xb7ff, 0xc889, 0x21, 0 - .dw 0xb840, 0xc889, 0xb87f, 0xc889, 0x21, 0 - .dw 0xb8c0, 0xc889, 0xb8ff, 0xc889, 0x21, 0 - .dw 0xb940, 0xc889, 0xb97f, 0xc889, 0x21, 0 - .dw 0xb9c0, 0xc889, 0xdfff, 0xc889, 0x21, 0 - .dw 0xe040, 0xc889, 0xe07f, 0xc889, 0x21, 0 - .dw 0xe0c0, 0xc889, 0xe0ff, 0xc889, 0x21, 0 - .dw 0xe140, 0xc889, 0xe17f, 0xc889, 0x21, 0 - .dw 0xe1c0, 0xc889, 0xe1ff, 0xc889, 0x21, 0 - .dw 0xe240, 0xc889, 0xe27f, 0xc889, 0x21, 0 - .dw 0xe2c0, 0xc889, 0xe2ff, 0xc889, 0x21, 0 - .dw 0xe340, 0xc889, 0xe37f, 0xc889, 0x21, 0 - .dw 0xe3c0, 0xc889, 0xe3ff, 0xc889, 0x21, 0 - .dw 0xe440, 0xc889, 0xe47f, 0xc889, 0x21, 0 - .dw 0xe4c0, 0xc889, 0xe4ff, 0xc889, 0x21, 0 - .dw 0xe540, 0xc889, 0xe57f, 0xc889, 0x21, 0 - .dw 0xe5c0, 0xc889, 0xe5ff, 0xc889, 0x21, 0 - .dw 0xe640, 0xc889, 0xe67f, 0xc889, 0x21, 0 - .dw 0xe6c0, 0xc889, 0xe6ff, 0xc889, 0x21, 0 - .dw 0xe740, 0xc889, 0xe77f, 0xc889, 0x21, 0 - .dw 0xe7c0, 0xc889, 0xe7ff, 0xc889, 0x21, 0 - .dw 0xe840, 0xc889, 0xe87f, 0xc889, 0x21, 0 - .dw 0xe8c0, 0xc889, 0xe8ff, 0xc889, 0x21, 0 - .dw 0xe940, 0xc889, 0xe97f, 0xc889, 0x21, 0 - .dw 0xe9c0, 0xc889, 0xe9ff, 0xc889, 0x21, 0 - .dw 0xea40, 0xc889, 0xea7f, 0xc889, 0x21, 0 - .dw 0xeac0, 0xc889, 0xeaff, 0xc889, 0x21, 0 - .dw 0xeb40, 0xc889, 0xeb7f, 0xc889, 0x21, 0 - .dw 0xebc0, 0xc889, 0xebff, 0xc889, 0x21, 0 - .dw 0xec40, 0xc889, 0xec7f, 0xc889, 0x21, 0 - .dw 0xecc0, 0xc889, 0xecff, 0xc889, 0x21, 0 - .dw 0xed40, 0xc889, 0xed7f, 0xc889, 0x21, 0 - .dw 0xedc0, 0xc889, 0xedff, 0xc889, 0x21, 0 - .dw 0xee40, 0xc889, 0xee7f, 0xc889, 0x21, 0 - .dw 0xeec0, 0xc889, 0xeeff, 0xc889, 0x21, 0 - .dw 0xef40, 0xc889, 0xef7f, 0xc889, 0x21, 0 - .dw 0xefc0, 0xc889, 0xefff, 0xc889, 0x21, 0 - .dw 0xf040, 0xc889, 0xf07f, 0xc889, 0x21, 0 - .dw 0xf0c0, 0xc889, 0xf0ff, 0xc889, 0x21, 0 - .dw 0xf140, 0xc889, 0xf17f, 0xc889, 0x21, 0 - .dw 0xf1c0, 0xc889, 0xf1ff, 0xc889, 0x21, 0 - .dw 0xf240, 0xc889, 0xf27f, 0xc889, 0x21, 0 - .dw 0xf2c0, 0xc889, 0xf2ff, 0xc889, 0x21, 0 - .dw 0xf340, 0xc889, 0xf37f, 0xc889, 0x21, 0 - .dw 0xf3c0, 0xc889, 0xf3ff, 0xc889, 0x21, 0 - .dw 0xf440, 0xc889, 0xf47f, 0xc889, 0x21, 0 - .dw 0xf4c0, 0xc889, 0xf4ff, 0xc889, 0x21, 0 - .dw 0xf540, 0xc889, 0xf57f, 0xc889, 0x21, 0 - .dw 0xf5c0, 0xc889, 0xf5ff, 0xc889, 0x21, 0 - .dw 0xf640, 0xc889, 0xf67f, 0xc889, 0x21, 0 - .dw 0xf6c0, 0xc889, 0xf6ff, 0xc889, 0x21, 0 - .dw 0xf740, 0xc889, 0xf77f, 0xc889, 0x21, 0 - .dw 0xf7c0, 0xc889, 0xf7ff, 0xc889, 0x21, 0 - .dw 0xf840, 0xc889, 0xf87f, 0xc889, 0x21, 0 - .dw 0xf8c0, 0xc889, 0xf8ff, 0xc889, 0x21, 0 - .dw 0xf940, 0xc889, 0xf97f, 0xc889, 0x21, 0 - .dw 0xf9c0, 0xc889, 0x1fff, 0xc88a, 0x21, 0 - .dw 0x2040, 0xc88a, 0x207f, 0xc88a, 0x21, 0 - .dw 0x20c0, 0xc88a, 0x20ff, 0xc88a, 0x21, 0 - .dw 0x2140, 0xc88a, 0x217f, 0xc88a, 0x21, 0 - .dw 0x21c0, 0xc88a, 0x21ff, 0xc88a, 0x21, 0 - .dw 0x2240, 0xc88a, 0x227f, 0xc88a, 0x21, 0 - .dw 0x22c0, 0xc88a, 0x22ff, 0xc88a, 0x21, 0 - .dw 0x2340, 0xc88a, 0x237f, 0xc88a, 0x21, 0 - .dw 0x23c0, 0xc88a, 0x23ff, 0xc88a, 0x21, 0 - .dw 0x2440, 0xc88a, 0x247f, 0xc88a, 0x21, 0 - .dw 0x24c0, 0xc88a, 0x24ff, 0xc88a, 0x21, 0 - .dw 0x2540, 0xc88a, 0x257f, 0xc88a, 0x21, 0 - .dw 0x25c0, 0xc88a, 0x25ff, 0xc88a, 0x21, 0 - .dw 0x2640, 0xc88a, 0x267f, 0xc88a, 0x21, 0 - .dw 0x26c0, 0xc88a, 0x26ff, 0xc88a, 0x21, 0 - .dw 0x2740, 0xc88a, 0x277f, 0xc88a, 0x21, 0 - .dw 0x27c0, 0xc88a, 0x27ff, 0xc88a, 0x21, 0 - .dw 0x2840, 0xc88a, 0x287f, 0xc88a, 0x21, 0 - .dw 0x28c0, 0xc88a, 0x28ff, 0xc88a, 0x21, 0 - .dw 0x2940, 0xc88a, 0x297f, 0xc88a, 0x21, 0 - .dw 0x29c0, 0xc88a, 0x29ff, 0xc88a, 0x21, 0 - .dw 0x2a40, 0xc88a, 0x2a7f, 0xc88a, 0x21, 0 - .dw 0x2ac0, 0xc88a, 0x2aff, 0xc88a, 0x21, 0 - .dw 0x2b40, 0xc88a, 0x2b7f, 0xc88a, 0x21, 0 - .dw 0x2bc0, 0xc88a, 0x2bff, 0xc88a, 0x21, 0 - .dw 0x2c40, 0xc88a, 0x2c7f, 0xc88a, 0x21, 0 - .dw 0x2cc0, 0xc88a, 0x2cff, 0xc88a, 0x21, 0 - .dw 0x2d40, 0xc88a, 0x2d7f, 0xc88a, 0x21, 0 - .dw 0x2dc0, 0xc88a, 0x2dff, 0xc88a, 0x21, 0 - .dw 0x2e40, 0xc88a, 0x2e7f, 0xc88a, 0x21, 0 - .dw 0x2ec0, 0xc88a, 0x2eff, 0xc88a, 0x21, 0 - .dw 0x2f40, 0xc88a, 0x2f7f, 0xc88a, 0x21, 0 - .dw 0x2fc0, 0xc88a, 0x2fff, 0xc88a, 0x21, 0 - .dw 0x3040, 0xc88a, 0x307f, 0xc88a, 0x21, 0 - .dw 0x30c0, 0xc88a, 0x30ff, 0xc88a, 0x21, 0 - .dw 0x3140, 0xc88a, 0x317f, 0xc88a, 0x21, 0 - .dw 0x31c0, 0xc88a, 0x31ff, 0xc88a, 0x21, 0 - .dw 0x3240, 0xc88a, 0x327f, 0xc88a, 0x21, 0 - .dw 0x32c0, 0xc88a, 0x32ff, 0xc88a, 0x21, 0 - .dw 0x3340, 0xc88a, 0x337f, 0xc88a, 0x21, 0 - .dw 0x33c0, 0xc88a, 0x33ff, 0xc88a, 0x21, 0 - .dw 0x3440, 0xc88a, 0x347f, 0xc88a, 0x21, 0 - .dw 0x34c0, 0xc88a, 0x34ff, 0xc88a, 0x21, 0 - .dw 0x3540, 0xc88a, 0x357f, 0xc88a, 0x21, 0 - .dw 0x35c0, 0xc88a, 0x35ff, 0xc88a, 0x21, 0 - .dw 0x3640, 0xc88a, 0x367f, 0xc88a, 0x21, 0 - .dw 0x36c0, 0xc88a, 0x36ff, 0xc88a, 0x21, 0 - .dw 0x3740, 0xc88a, 0x377f, 0xc88a, 0x21, 0 - .dw 0x37c0, 0xc88a, 0x37ff, 0xc88a, 0x21, 0 - .dw 0x3840, 0xc88a, 0x387f, 0xc88a, 0x21, 0 - .dw 0x38c0, 0xc88a, 0x38ff, 0xc88a, 0x21, 0 - .dw 0x3940, 0xc88a, 0x397f, 0xc88a, 0x21, 0 - .dw 0x39c0, 0xc88a, 0x5fff, 0xc88a, 0x21, 0 - .dw 0x6040, 0xc88a, 0x607f, 0xc88a, 0x21, 0 - .dw 0x60c0, 0xc88a, 0x60ff, 0xc88a, 0x21, 0 - .dw 0x6140, 0xc88a, 0x617f, 0xc88a, 0x21, 0 - .dw 0x61c0, 0xc88a, 0x61ff, 0xc88a, 0x21, 0 - .dw 0x6240, 0xc88a, 0x627f, 0xc88a, 0x21, 0 - .dw 0x62c0, 0xc88a, 0x62ff, 0xc88a, 0x21, 0 - .dw 0x6340, 0xc88a, 0x637f, 0xc88a, 0x21, 0 - .dw 0x63c0, 0xc88a, 0x63ff, 0xc88a, 0x21, 0 - .dw 0x6440, 0xc88a, 0x647f, 0xc88a, 0x21, 0 - .dw 0x64c0, 0xc88a, 0x64ff, 0xc88a, 0x21, 0 - .dw 0x6540, 0xc88a, 0x657f, 0xc88a, 0x21, 0 - .dw 0x65c0, 0xc88a, 0x65ff, 0xc88a, 0x21, 0 - .dw 0x6640, 0xc88a, 0x667f, 0xc88a, 0x21, 0 - .dw 0x66c0, 0xc88a, 0x66ff, 0xc88a, 0x21, 0 - .dw 0x6740, 0xc88a, 0x677f, 0xc88a, 0x21, 0 - .dw 0x67c0, 0xc88a, 0x67ff, 0xc88a, 0x21, 0 - .dw 0x6840, 0xc88a, 0x687f, 0xc88a, 0x21, 0 - .dw 0x68c0, 0xc88a, 0x68ff, 0xc88a, 0x21, 0 - .dw 0x6940, 0xc88a, 0x697f, 0xc88a, 0x21, 0 - .dw 0x69c0, 0xc88a, 0x69ff, 0xc88a, 0x21, 0 - .dw 0x6a40, 0xc88a, 0x6a7f, 0xc88a, 0x21, 0 - .dw 0x6ac0, 0xc88a, 0x6aff, 0xc88a, 0x21, 0 - .dw 0x6b40, 0xc88a, 0x6b7f, 0xc88a, 0x21, 0 - .dw 0x6bc0, 0xc88a, 0x6bff, 0xc88a, 0x21, 0 - .dw 0x6c40, 0xc88a, 0x6c7f, 0xc88a, 0x21, 0 - .dw 0x6cc0, 0xc88a, 0x6cff, 0xc88a, 0x21, 0 - .dw 0x6d40, 0xc88a, 0x6d7f, 0xc88a, 0x21, 0 - .dw 0x6dc0, 0xc88a, 0x6dff, 0xc88a, 0x21, 0 - .dw 0x6e40, 0xc88a, 0x6e7f, 0xc88a, 0x21, 0 - .dw 0x6ec0, 0xc88a, 0x6eff, 0xc88a, 0x21, 0 - .dw 0x6f40, 0xc88a, 0x6f7f, 0xc88a, 0x21, 0 - .dw 0x6fc0, 0xc88a, 0x6fff, 0xc88a, 0x21, 0 - .dw 0x7040, 0xc88a, 0x707f, 0xc88a, 0x21, 0 - .dw 0x70c0, 0xc88a, 0x70ff, 0xc88a, 0x21, 0 - .dw 0x7140, 0xc88a, 0x717f, 0xc88a, 0x21, 0 - .dw 0x71c0, 0xc88a, 0x71ff, 0xc88a, 0x21, 0 - .dw 0x7240, 0xc88a, 0x727f, 0xc88a, 0x21, 0 - .dw 0x72c0, 0xc88a, 0x72ff, 0xc88a, 0x21, 0 - .dw 0x7340, 0xc88a, 0x737f, 0xc88a, 0x21, 0 - .dw 0x73c0, 0xc88a, 0x73ff, 0xc88a, 0x21, 0 - .dw 0x7440, 0xc88a, 0x747f, 0xc88a, 0x21, 0 - .dw 0x74c0, 0xc88a, 0x74ff, 0xc88a, 0x21, 0 - .dw 0x7540, 0xc88a, 0x757f, 0xc88a, 0x21, 0 - .dw 0x75c0, 0xc88a, 0x75ff, 0xc88a, 0x21, 0 - .dw 0x7640, 0xc88a, 0x767f, 0xc88a, 0x21, 0 - .dw 0x76c0, 0xc88a, 0x76ff, 0xc88a, 0x21, 0 - .dw 0x7740, 0xc88a, 0x777f, 0xc88a, 0x21, 0 - .dw 0x77c0, 0xc88a, 0x77ff, 0xc88a, 0x21, 0 - .dw 0x7840, 0xc88a, 0x787f, 0xc88a, 0x21, 0 - .dw 0x78c0, 0xc88a, 0x78ff, 0xc88a, 0x21, 0 - .dw 0x7940, 0xc88a, 0x797f, 0xc88a, 0x21, 0 - .dw 0x79c0, 0xc88a, 0x9fff, 0xc88a, 0x21, 0 - .dw 0xa040, 0xc88a, 0xa07f, 0xc88a, 0x21, 0 - .dw 0xa0c0, 0xc88a, 0xa0ff, 0xc88a, 0x21, 0 - .dw 0xa140, 0xc88a, 0xa17f, 0xc88a, 0x21, 0 - .dw 0xa1c0, 0xc88a, 0xa1ff, 0xc88a, 0x21, 0 - .dw 0xa240, 0xc88a, 0xa27f, 0xc88a, 0x21, 0 - .dw 0xa2c0, 0xc88a, 0xa2ff, 0xc88a, 0x21, 0 - .dw 0xa340, 0xc88a, 0xa37f, 0xc88a, 0x21, 0 - .dw 0xa3c0, 0xc88a, 0xa3ff, 0xc88a, 0x21, 0 - .dw 0xa440, 0xc88a, 0xa47f, 0xc88a, 0x21, 0 - .dw 0xa4c0, 0xc88a, 0xa4ff, 0xc88a, 0x21, 0 - .dw 0xa540, 0xc88a, 0xa57f, 0xc88a, 0x21, 0 - .dw 0xa5c0, 0xc88a, 0xa5ff, 0xc88a, 0x21, 0 - .dw 0xa640, 0xc88a, 0xa67f, 0xc88a, 0x21, 0 - .dw 0xa6c0, 0xc88a, 0xa6ff, 0xc88a, 0x21, 0 - .dw 0xa740, 0xc88a, 0xa77f, 0xc88a, 0x21, 0 - .dw 0xa7c0, 0xc88a, 0xa7ff, 0xc88a, 0x21, 0 - .dw 0xa840, 0xc88a, 0xa87f, 0xc88a, 0x21, 0 - .dw 0xa8c0, 0xc88a, 0xa8ff, 0xc88a, 0x21, 0 - .dw 0xa940, 0xc88a, 0xa97f, 0xc88a, 0x21, 0 - .dw 0xa9c0, 0xc88a, 0xa9ff, 0xc88a, 0x21, 0 - .dw 0xaa40, 0xc88a, 0xaa7f, 0xc88a, 0x21, 0 - .dw 0xaac0, 0xc88a, 0xaaff, 0xc88a, 0x21, 0 - .dw 0xab40, 0xc88a, 0xab7f, 0xc88a, 0x21, 0 - .dw 0xabc0, 0xc88a, 0xabff, 0xc88a, 0x21, 0 - .dw 0xac40, 0xc88a, 0xac7f, 0xc88a, 0x21, 0 - .dw 0xacc0, 0xc88a, 0xacff, 0xc88a, 0x21, 0 - .dw 0xad40, 0xc88a, 0xad7f, 0xc88a, 0x21, 0 - .dw 0xadc0, 0xc88a, 0xadff, 0xc88a, 0x21, 0 - .dw 0xae40, 0xc88a, 0xae7f, 0xc88a, 0x21, 0 - .dw 0xaec0, 0xc88a, 0xaeff, 0xc88a, 0x21, 0 - .dw 0xaf40, 0xc88a, 0xaf7f, 0xc88a, 0x21, 0 - .dw 0xafc0, 0xc88a, 0xafff, 0xc88a, 0x21, 0 - .dw 0xb040, 0xc88a, 0xb07f, 0xc88a, 0x21, 0 - .dw 0xb0c0, 0xc88a, 0xb0ff, 0xc88a, 0x21, 0 - .dw 0xb140, 0xc88a, 0xb17f, 0xc88a, 0x21, 0 - .dw 0xb1c0, 0xc88a, 0xb1ff, 0xc88a, 0x21, 0 - .dw 0xb240, 0xc88a, 0xb27f, 0xc88a, 0x21, 0 - .dw 0xb2c0, 0xc88a, 0xb2ff, 0xc88a, 0x21, 0 - .dw 0xb340, 0xc88a, 0xb37f, 0xc88a, 0x21, 0 - .dw 0xb3c0, 0xc88a, 0xb3ff, 0xc88a, 0x21, 0 - .dw 0xb440, 0xc88a, 0xb47f, 0xc88a, 0x21, 0 - .dw 0xb4c0, 0xc88a, 0xb4ff, 0xc88a, 0x21, 0 - .dw 0xb540, 0xc88a, 0xb57f, 0xc88a, 0x21, 0 - .dw 0xb5c0, 0xc88a, 0xb5ff, 0xc88a, 0x21, 0 - .dw 0xb640, 0xc88a, 0xb67f, 0xc88a, 0x21, 0 - .dw 0xb6c0, 0xc88a, 0xb6ff, 0xc88a, 0x21, 0 - .dw 0xb740, 0xc88a, 0xb77f, 0xc88a, 0x21, 0 - .dw 0xb7c0, 0xc88a, 0xb7ff, 0xc88a, 0x21, 0 - .dw 0xb840, 0xc88a, 0xb87f, 0xc88a, 0x21, 0 - .dw 0xb8c0, 0xc88a, 0xb8ff, 0xc88a, 0x21, 0 - .dw 0xb940, 0xc88a, 0xb97f, 0xc88a, 0x21, 0 - .dw 0xb9c0, 0xc88a, 0xdfff, 0xc88a, 0x21, 0 - .dw 0xe040, 0xc88a, 0xe07f, 0xc88a, 0x21, 0 - .dw 0xe0c0, 0xc88a, 0xe0ff, 0xc88a, 0x21, 0 - .dw 0xe140, 0xc88a, 0xe17f, 0xc88a, 0x21, 0 - .dw 0xe1c0, 0xc88a, 0xe1ff, 0xc88a, 0x21, 0 - .dw 0xe240, 0xc88a, 0xe27f, 0xc88a, 0x21, 0 - .dw 0xe2c0, 0xc88a, 0xe2ff, 0xc88a, 0x21, 0 - .dw 0xe340, 0xc88a, 0xe37f, 0xc88a, 0x21, 0 - .dw 0xe3c0, 0xc88a, 0xe3ff, 0xc88a, 0x21, 0 - .dw 0xe440, 0xc88a, 0xe47f, 0xc88a, 0x21, 0 - .dw 0xe4c0, 0xc88a, 0xe4ff, 0xc88a, 0x21, 0 - .dw 0xe540, 0xc88a, 0xe57f, 0xc88a, 0x21, 0 - .dw 0xe5c0, 0xc88a, 0xe5ff, 0xc88a, 0x21, 0 - .dw 0xe640, 0xc88a, 0xe67f, 0xc88a, 0x21, 0 - .dw 0xe6c0, 0xc88a, 0xe6ff, 0xc88a, 0x21, 0 - .dw 0xe740, 0xc88a, 0xe77f, 0xc88a, 0x21, 0 - .dw 0xe7c0, 0xc88a, 0xe7ff, 0xc88a, 0x21, 0 - .dw 0xe840, 0xc88a, 0xe87f, 0xc88a, 0x21, 0 - .dw 0xe8c0, 0xc88a, 0xe8ff, 0xc88a, 0x21, 0 - .dw 0xe940, 0xc88a, 0xe97f, 0xc88a, 0x21, 0 - .dw 0xe9c0, 0xc88a, 0xe9ff, 0xc88a, 0x21, 0 - .dw 0xea40, 0xc88a, 0xea7f, 0xc88a, 0x21, 0 - .dw 0xeac0, 0xc88a, 0xeaff, 0xc88a, 0x21, 0 - .dw 0xeb40, 0xc88a, 0xeb7f, 0xc88a, 0x21, 0 - .dw 0xebc0, 0xc88a, 0xebff, 0xc88a, 0x21, 0 - .dw 0xec40, 0xc88a, 0xec7f, 0xc88a, 0x21, 0 - .dw 0xecc0, 0xc88a, 0xecff, 0xc88a, 0x21, 0 - .dw 0xed40, 0xc88a, 0xed7f, 0xc88a, 0x21, 0 - .dw 0xedc0, 0xc88a, 0xedff, 0xc88a, 0x21, 0 - .dw 0xee40, 0xc88a, 0xee7f, 0xc88a, 0x21, 0 - .dw 0xeec0, 0xc88a, 0xeeff, 0xc88a, 0x21, 0 - .dw 0xef40, 0xc88a, 0xef7f, 0xc88a, 0x21, 0 - .dw 0xefc0, 0xc88a, 0xefff, 0xc88a, 0x21, 0 - .dw 0xf040, 0xc88a, 0xf07f, 0xc88a, 0x21, 0 - .dw 0xf0c0, 0xc88a, 0xf0ff, 0xc88a, 0x21, 0 - .dw 0xf140, 0xc88a, 0xf17f, 0xc88a, 0x21, 0 - .dw 0xf1c0, 0xc88a, 0xf1ff, 0xc88a, 0x21, 0 - .dw 0xf240, 0xc88a, 0xf27f, 0xc88a, 0x21, 0 - .dw 0xf2c0, 0xc88a, 0xf2ff, 0xc88a, 0x21, 0 - .dw 0xf340, 0xc88a, 0xf37f, 0xc88a, 0x21, 0 - .dw 0xf3c0, 0xc88a, 0xf3ff, 0xc88a, 0x21, 0 - .dw 0xf440, 0xc88a, 0xf47f, 0xc88a, 0x21, 0 - .dw 0xf4c0, 0xc88a, 0xf4ff, 0xc88a, 0x21, 0 - .dw 0xf540, 0xc88a, 0xf57f, 0xc88a, 0x21, 0 - .dw 0xf5c0, 0xc88a, 0xf5ff, 0xc88a, 0x21, 0 - .dw 0xf640, 0xc88a, 0xf67f, 0xc88a, 0x21, 0 - .dw 0xf6c0, 0xc88a, 0xf6ff, 0xc88a, 0x21, 0 - .dw 0xf740, 0xc88a, 0xf77f, 0xc88a, 0x21, 0 - .dw 0xf7c0, 0xc88a, 0xf7ff, 0xc88a, 0x21, 0 - .dw 0xf840, 0xc88a, 0xf87f, 0xc88a, 0x21, 0 - .dw 0xf8c0, 0xc88a, 0xf8ff, 0xc88a, 0x21, 0 - .dw 0xf940, 0xc88a, 0xf97f, 0xc88a, 0x21, 0 - .dw 0xf9c0, 0xc88a, 0x1fff, 0xc88b, 0x21, 0 - .dw 0x2040, 0xc88b, 0x207f, 0xc88b, 0x21, 0 - .dw 0x20c0, 0xc88b, 0x20ff, 0xc88b, 0x21, 0 - .dw 0x2140, 0xc88b, 0x217f, 0xc88b, 0x21, 0 - .dw 0x21c0, 0xc88b, 0x21ff, 0xc88b, 0x21, 0 - .dw 0x2240, 0xc88b, 0x227f, 0xc88b, 0x21, 0 - .dw 0x22c0, 0xc88b, 0x22ff, 0xc88b, 0x21, 0 - .dw 0x2340, 0xc88b, 0x237f, 0xc88b, 0x21, 0 - .dw 0x23c0, 0xc88b, 0x23ff, 0xc88b, 0x21, 0 - .dw 0x2440, 0xc88b, 0x247f, 0xc88b, 0x21, 0 - .dw 0x24c0, 0xc88b, 0x24ff, 0xc88b, 0x21, 0 - .dw 0x2540, 0xc88b, 0x257f, 0xc88b, 0x21, 0 - .dw 0x25c0, 0xc88b, 0x25ff, 0xc88b, 0x21, 0 - .dw 0x2640, 0xc88b, 0x267f, 0xc88b, 0x21, 0 - .dw 0x26c0, 0xc88b, 0x26ff, 0xc88b, 0x21, 0 - .dw 0x2740, 0xc88b, 0x277f, 0xc88b, 0x21, 0 - .dw 0x27c0, 0xc88b, 0x27ff, 0xc88b, 0x21, 0 - .dw 0x2840, 0xc88b, 0x287f, 0xc88b, 0x21, 0 - .dw 0x28c0, 0xc88b, 0x28ff, 0xc88b, 0x21, 0 - .dw 0x2940, 0xc88b, 0x297f, 0xc88b, 0x21, 0 - .dw 0x29c0, 0xc88b, 0x29ff, 0xc88b, 0x21, 0 - .dw 0x2a40, 0xc88b, 0x2a7f, 0xc88b, 0x21, 0 - .dw 0x2ac0, 0xc88b, 0x2aff, 0xc88b, 0x21, 0 - .dw 0x2b40, 0xc88b, 0x2b7f, 0xc88b, 0x21, 0 - .dw 0x2bc0, 0xc88b, 0x2bff, 0xc88b, 0x21, 0 - .dw 0x2c40, 0xc88b, 0x2c7f, 0xc88b, 0x21, 0 - .dw 0x2cc0, 0xc88b, 0x2cff, 0xc88b, 0x21, 0 - .dw 0x2d40, 0xc88b, 0x2d7f, 0xc88b, 0x21, 0 - .dw 0x2dc0, 0xc88b, 0x2dff, 0xc88b, 0x21, 0 - .dw 0x2e40, 0xc88b, 0x2e7f, 0xc88b, 0x21, 0 - .dw 0x2ec0, 0xc88b, 0x2eff, 0xc88b, 0x21, 0 - .dw 0x2f40, 0xc88b, 0x2f7f, 0xc88b, 0x21, 0 - .dw 0x2fc0, 0xc88b, 0x2fff, 0xc88b, 0x21, 0 - .dw 0x3040, 0xc88b, 0x307f, 0xc88b, 0x21, 0 - .dw 0x30c0, 0xc88b, 0x30ff, 0xc88b, 0x21, 0 - .dw 0x3140, 0xc88b, 0x317f, 0xc88b, 0x21, 0 - .dw 0x31c0, 0xc88b, 0x31ff, 0xc88b, 0x21, 0 - .dw 0x3240, 0xc88b, 0x327f, 0xc88b, 0x21, 0 - .dw 0x32c0, 0xc88b, 0x32ff, 0xc88b, 0x21, 0 - .dw 0x3340, 0xc88b, 0x337f, 0xc88b, 0x21, 0 - .dw 0x33c0, 0xc88b, 0x33ff, 0xc88b, 0x21, 0 - .dw 0x3440, 0xc88b, 0x347f, 0xc88b, 0x21, 0 - .dw 0x34c0, 0xc88b, 0x34ff, 0xc88b, 0x21, 0 - .dw 0x3540, 0xc88b, 0x357f, 0xc88b, 0x21, 0 - .dw 0x35c0, 0xc88b, 0x35ff, 0xc88b, 0x21, 0 - .dw 0x3640, 0xc88b, 0x367f, 0xc88b, 0x21, 0 - .dw 0x36c0, 0xc88b, 0x36ff, 0xc88b, 0x21, 0 - .dw 0x3740, 0xc88b, 0x377f, 0xc88b, 0x21, 0 - .dw 0x37c0, 0xc88b, 0x37ff, 0xc88b, 0x21, 0 - .dw 0x3840, 0xc88b, 0x387f, 0xc88b, 0x21, 0 - .dw 0x38c0, 0xc88b, 0x38ff, 0xc88b, 0x21, 0 - .dw 0x3940, 0xc88b, 0x397f, 0xc88b, 0x21, 0 - .dw 0x39c0, 0xc88b, 0xffff, 0xc88b, 0x21, 0 - .dw 0x0040, 0xc88c, 0x007f, 0xc88c, 0x21, 0 - .dw 0x00c0, 0xc88c, 0x00ff, 0xc88c, 0x21, 0 - .dw 0x0140, 0xc88c, 0x017f, 0xc88c, 0x21, 0 - .dw 0x01c0, 0xc88c, 0x01ff, 0xc88c, 0x21, 0 - .dw 0x0240, 0xc88c, 0x027f, 0xc88c, 0x21, 0 - .dw 0x02c0, 0xc88c, 0x02ff, 0xc88c, 0x21, 0 - .dw 0x0340, 0xc88c, 0x037f, 0xc88c, 0x21, 0 - .dw 0x03c0, 0xc88c, 0x03ff, 0xc88c, 0x21, 0 - .dw 0x0440, 0xc88c, 0x047f, 0xc88c, 0x21, 0 - .dw 0x04c0, 0xc88c, 0x04ff, 0xc88c, 0x21, 0 - .dw 0x0540, 0xc88c, 0x057f, 0xc88c, 0x21, 0 - .dw 0x05c0, 0xc88c, 0x05ff, 0xc88c, 0x21, 0 - .dw 0x0640, 0xc88c, 0x067f, 0xc88c, 0x21, 0 - .dw 0x06c0, 0xc88c, 0x06ff, 0xc88c, 0x21, 0 - .dw 0x0740, 0xc88c, 0x077f, 0xc88c, 0x21, 0 - .dw 0x07c0, 0xc88c, 0x07ff, 0xc88c, 0x21, 0 - .dw 0x0840, 0xc88c, 0x087f, 0xc88c, 0x21, 0 - .dw 0x08c0, 0xc88c, 0x08ff, 0xc88c, 0x21, 0 - .dw 0x0940, 0xc88c, 0x097f, 0xc88c, 0x21, 0 - .dw 0x09c0, 0xc88c, 0x09ff, 0xc88c, 0x21, 0 - .dw 0x0a40, 0xc88c, 0x0a7f, 0xc88c, 0x21, 0 - .dw 0x0ac0, 0xc88c, 0x0aff, 0xc88c, 0x21, 0 - .dw 0x0b40, 0xc88c, 0x0b7f, 0xc88c, 0x21, 0 - .dw 0x0bc0, 0xc88c, 0x0bff, 0xc88c, 0x21, 0 - .dw 0x0c40, 0xc88c, 0x0c7f, 0xc88c, 0x21, 0 - .dw 0x0cc0, 0xc88c, 0x0cff, 0xc88c, 0x21, 0 - .dw 0x0d40, 0xc88c, 0x0d7f, 0xc88c, 0x21, 0 - .dw 0x0dc0, 0xc88c, 0x0dff, 0xc88c, 0x21, 0 - .dw 0x0e40, 0xc88c, 0x0e7f, 0xc88c, 0x21, 0 - .dw 0x0ec0, 0xc88c, 0x0eff, 0xc88c, 0x21, 0 - .dw 0x0f40, 0xc88c, 0x0f7f, 0xc88c, 0x21, 0 - .dw 0x0fc0, 0xc88c, 0x0fff, 0xc88c, 0x21, 0 - .dw 0x1040, 0xc88c, 0x107f, 0xc88c, 0x21, 0 - .dw 0x10c0, 0xc88c, 0x10ff, 0xc88c, 0x21, 0 - .dw 0x1140, 0xc88c, 0x117f, 0xc88c, 0x21, 0 - .dw 0x11c0, 0xc88c, 0x11ff, 0xc88c, 0x21, 0 - .dw 0x1240, 0xc88c, 0x127f, 0xc88c, 0x21, 0 - .dw 0x12c0, 0xc88c, 0x12ff, 0xc88c, 0x21, 0 - .dw 0x1340, 0xc88c, 0x137f, 0xc88c, 0x21, 0 - .dw 0x13c0, 0xc88c, 0x13ff, 0xc88c, 0x21, 0 - .dw 0x1440, 0xc88c, 0x147f, 0xc88c, 0x21, 0 - .dw 0x14c0, 0xc88c, 0x14ff, 0xc88c, 0x21, 0 - .dw 0x1540, 0xc88c, 0x157f, 0xc88c, 0x21, 0 - .dw 0x15c0, 0xc88c, 0x15ff, 0xc88c, 0x21, 0 - .dw 0x1640, 0xc88c, 0x167f, 0xc88c, 0x21, 0 - .dw 0x16c0, 0xc88c, 0x16ff, 0xc88c, 0x21, 0 - .dw 0x1740, 0xc88c, 0x177f, 0xc88c, 0x21, 0 - .dw 0x17c0, 0xc88c, 0x17ff, 0xc88c, 0x21, 0 - .dw 0x1840, 0xc88c, 0x187f, 0xc88c, 0x21, 0 - .dw 0x18c0, 0xc88c, 0x18ff, 0xc88c, 0x21, 0 - .dw 0x1940, 0xc88c, 0x197f, 0xc88c, 0x21, 0 - .dw 0x19c0, 0xc88c, 0x1fff, 0xc88c, 0x21, 0 - .dw 0x2040, 0xc88c, 0x207f, 0xc88c, 0x21, 0 - .dw 0x20c0, 0xc88c, 0x20ff, 0xc88c, 0x21, 0 - .dw 0x2140, 0xc88c, 0x217f, 0xc88c, 0x21, 0 - .dw 0x21c0, 0xc88c, 0x21ff, 0xc88c, 0x21, 0 - .dw 0x2240, 0xc88c, 0x227f, 0xc88c, 0x21, 0 - .dw 0x22c0, 0xc88c, 0x22ff, 0xc88c, 0x21, 0 - .dw 0x2340, 0xc88c, 0x237f, 0xc88c, 0x21, 0 - .dw 0x23c0, 0xc88c, 0x23ff, 0xc88c, 0x21, 0 - .dw 0x2440, 0xc88c, 0x247f, 0xc88c, 0x21, 0 - .dw 0x24c0, 0xc88c, 0x24ff, 0xc88c, 0x21, 0 - .dw 0x2540, 0xc88c, 0x257f, 0xc88c, 0x21, 0 - .dw 0x25c0, 0xc88c, 0x25ff, 0xc88c, 0x21, 0 - .dw 0x2640, 0xc88c, 0x267f, 0xc88c, 0x21, 0 - .dw 0x26c0, 0xc88c, 0x26ff, 0xc88c, 0x21, 0 - .dw 0x2740, 0xc88c, 0x277f, 0xc88c, 0x21, 0 - .dw 0x27c0, 0xc88c, 0x27ff, 0xc88c, 0x21, 0 - .dw 0x2840, 0xc88c, 0x287f, 0xc88c, 0x21, 0 - .dw 0x28c0, 0xc88c, 0x28ff, 0xc88c, 0x21, 0 - .dw 0x2940, 0xc88c, 0x297f, 0xc88c, 0x21, 0 - .dw 0x29c0, 0xc88c, 0x29ff, 0xc88c, 0x21, 0 - .dw 0x2a40, 0xc88c, 0x2a7f, 0xc88c, 0x21, 0 - .dw 0x2ac0, 0xc88c, 0x2aff, 0xc88c, 0x21, 0 - .dw 0x2b40, 0xc88c, 0x2b7f, 0xc88c, 0x21, 0 - .dw 0x2bc0, 0xc88c, 0x2bff, 0xc88c, 0x21, 0 - .dw 0x2c40, 0xc88c, 0x2c7f, 0xc88c, 0x21, 0 - .dw 0x2cc0, 0xc88c, 0x2cff, 0xc88c, 0x21, 0 - .dw 0x2d40, 0xc88c, 0x2d7f, 0xc88c, 0x21, 0 - .dw 0x2dc0, 0xc88c, 0x2dff, 0xc88c, 0x21, 0 - .dw 0x2e40, 0xc88c, 0x2e7f, 0xc88c, 0x21, 0 - .dw 0x2ec0, 0xc88c, 0x2eff, 0xc88c, 0x21, 0 - .dw 0x2f40, 0xc88c, 0x2f7f, 0xc88c, 0x21, 0 - .dw 0x2fc0, 0xc88c, 0x2fff, 0xc88c, 0x21, 0 - .dw 0x3040, 0xc88c, 0x307f, 0xc88c, 0x21, 0 - .dw 0x30c0, 0xc88c, 0x30ff, 0xc88c, 0x21, 0 - .dw 0x3140, 0xc88c, 0x317f, 0xc88c, 0x21, 0 - .dw 0x31c0, 0xc88c, 0x31ff, 0xc88c, 0x21, 0 - .dw 0x3240, 0xc88c, 0x327f, 0xc88c, 0x21, 0 - .dw 0x32c0, 0xc88c, 0x32ff, 0xc88c, 0x21, 0 - .dw 0x3340, 0xc88c, 0x337f, 0xc88c, 0x21, 0 - .dw 0x33c0, 0xc88c, 0x33ff, 0xc88c, 0x21, 0 - .dw 0x3440, 0xc88c, 0x347f, 0xc88c, 0x21, 0 - .dw 0x34c0, 0xc88c, 0x34ff, 0xc88c, 0x21, 0 - .dw 0x3540, 0xc88c, 0x357f, 0xc88c, 0x21, 0 - .dw 0x35c0, 0xc88c, 0x35ff, 0xc88c, 0x21, 0 - .dw 0x3640, 0xc88c, 0x367f, 0xc88c, 0x21, 0 - .dw 0x36c0, 0xc88c, 0x36ff, 0xc88c, 0x21, 0 - .dw 0x3740, 0xc88c, 0x377f, 0xc88c, 0x21, 0 - .dw 0x37c0, 0xc88c, 0x37ff, 0xc88c, 0x21, 0 - .dw 0x3840, 0xc88c, 0x387f, 0xc88c, 0x21, 0 - .dw 0x38c0, 0xc88c, 0x38ff, 0xc88c, 0x21, 0 - .dw 0x3940, 0xc88c, 0x397f, 0xc88c, 0x21, 0 - .dw 0x39c0, 0xc88c, 0x3fff, 0xc88c, 0x21, 0 - .dw 0x4040, 0xc88c, 0x407f, 0xc88c, 0x21, 0 - .dw 0x40c0, 0xc88c, 0x40ff, 0xc88c, 0x21, 0 - .dw 0x4140, 0xc88c, 0x417f, 0xc88c, 0x21, 0 - .dw 0x41c0, 0xc88c, 0x41ff, 0xc88c, 0x21, 0 - .dw 0x4240, 0xc88c, 0x427f, 0xc88c, 0x21, 0 - .dw 0x42c0, 0xc88c, 0x42ff, 0xc88c, 0x21, 0 - .dw 0x4340, 0xc88c, 0x437f, 0xc88c, 0x21, 0 - .dw 0x43c0, 0xc88c, 0x43ff, 0xc88c, 0x21, 0 - .dw 0x4440, 0xc88c, 0x447f, 0xc88c, 0x21, 0 - .dw 0x44c0, 0xc88c, 0x44ff, 0xc88c, 0x21, 0 - .dw 0x4540, 0xc88c, 0x457f, 0xc88c, 0x21, 0 - .dw 0x45c0, 0xc88c, 0x45ff, 0xc88c, 0x21, 0 - .dw 0x4640, 0xc88c, 0x467f, 0xc88c, 0x21, 0 - .dw 0x46c0, 0xc88c, 0x46ff, 0xc88c, 0x21, 0 - .dw 0x4740, 0xc88c, 0x477f, 0xc88c, 0x21, 0 - .dw 0x47c0, 0xc88c, 0x47ff, 0xc88c, 0x21, 0 - .dw 0x4840, 0xc88c, 0x487f, 0xc88c, 0x21, 0 - .dw 0x48c0, 0xc88c, 0x48ff, 0xc88c, 0x21, 0 - .dw 0x4940, 0xc88c, 0x497f, 0xc88c, 0x21, 0 - .dw 0x49c0, 0xc88c, 0x49ff, 0xc88c, 0x21, 0 - .dw 0x4a40, 0xc88c, 0x4a7f, 0xc88c, 0x21, 0 - .dw 0x4ac0, 0xc88c, 0x4aff, 0xc88c, 0x21, 0 - .dw 0x4b40, 0xc88c, 0x4b7f, 0xc88c, 0x21, 0 - .dw 0x4bc0, 0xc88c, 0x4bff, 0xc88c, 0x21, 0 - .dw 0x4c40, 0xc88c, 0x4c7f, 0xc88c, 0x21, 0 - .dw 0x4cc0, 0xc88c, 0x4cff, 0xc88c, 0x21, 0 - .dw 0x4d40, 0xc88c, 0x4d7f, 0xc88c, 0x21, 0 - .dw 0x4dc0, 0xc88c, 0x4dff, 0xc88c, 0x21, 0 - .dw 0x4e40, 0xc88c, 0x4e7f, 0xc88c, 0x21, 0 - .dw 0x4ec0, 0xc88c, 0x4eff, 0xc88c, 0x21, 0 - .dw 0x4f40, 0xc88c, 0x4f7f, 0xc88c, 0x21, 0 - .dw 0x4fc0, 0xc88c, 0x4fff, 0xc88c, 0x21, 0 - .dw 0x5040, 0xc88c, 0x507f, 0xc88c, 0x21, 0 - .dw 0x50c0, 0xc88c, 0x50ff, 0xc88c, 0x21, 0 - .dw 0x5140, 0xc88c, 0x517f, 0xc88c, 0x21, 0 - .dw 0x51c0, 0xc88c, 0x51ff, 0xc88c, 0x21, 0 - .dw 0x5240, 0xc88c, 0x527f, 0xc88c, 0x21, 0 - .dw 0x52c0, 0xc88c, 0x52ff, 0xc88c, 0x21, 0 - .dw 0x5340, 0xc88c, 0x537f, 0xc88c, 0x21, 0 - .dw 0x53c0, 0xc88c, 0x53ff, 0xc88c, 0x21, 0 - .dw 0x5440, 0xc88c, 0x547f, 0xc88c, 0x21, 0 - .dw 0x54c0, 0xc88c, 0x54ff, 0xc88c, 0x21, 0 - .dw 0x5540, 0xc88c, 0x557f, 0xc88c, 0x21, 0 - .dw 0x55c0, 0xc88c, 0x55ff, 0xc88c, 0x21, 0 - .dw 0x5640, 0xc88c, 0x567f, 0xc88c, 0x21, 0 - .dw 0x56c0, 0xc88c, 0x56ff, 0xc88c, 0x21, 0 - .dw 0x5740, 0xc88c, 0x577f, 0xc88c, 0x21, 0 - .dw 0x57c0, 0xc88c, 0x57ff, 0xc88c, 0x21, 0 - .dw 0x5840, 0xc88c, 0x587f, 0xc88c, 0x21, 0 - .dw 0x58c0, 0xc88c, 0x58ff, 0xc88c, 0x21, 0 - .dw 0x5940, 0xc88c, 0x597f, 0xc88c, 0x21, 0 - .dw 0x59c0, 0xc88c, 0x5fff, 0xc88c, 0x21, 0 - .dw 0x6040, 0xc88c, 0x607f, 0xc88c, 0x21, 0 - .dw 0x60c0, 0xc88c, 0x60ff, 0xc88c, 0x21, 0 - .dw 0x6140, 0xc88c, 0x617f, 0xc88c, 0x21, 0 - .dw 0x61c0, 0xc88c, 0x61ff, 0xc88c, 0x21, 0 - .dw 0x6240, 0xc88c, 0x627f, 0xc88c, 0x21, 0 - .dw 0x62c0, 0xc88c, 0x62ff, 0xc88c, 0x21, 0 - .dw 0x6340, 0xc88c, 0x637f, 0xc88c, 0x21, 0 - .dw 0x63c0, 0xc88c, 0x63ff, 0xc88c, 0x21, 0 - .dw 0x6440, 0xc88c, 0x647f, 0xc88c, 0x21, 0 - .dw 0x64c0, 0xc88c, 0x64ff, 0xc88c, 0x21, 0 - .dw 0x6540, 0xc88c, 0x657f, 0xc88c, 0x21, 0 - .dw 0x65c0, 0xc88c, 0x65ff, 0xc88c, 0x21, 0 - .dw 0x6640, 0xc88c, 0x667f, 0xc88c, 0x21, 0 - .dw 0x66c0, 0xc88c, 0x66ff, 0xc88c, 0x21, 0 - .dw 0x6740, 0xc88c, 0x677f, 0xc88c, 0x21, 0 - .dw 0x67c0, 0xc88c, 0x67ff, 0xc88c, 0x21, 0 - .dw 0x6840, 0xc88c, 0x687f, 0xc88c, 0x21, 0 - .dw 0x68c0, 0xc88c, 0x68ff, 0xc88c, 0x21, 0 - .dw 0x6940, 0xc88c, 0x697f, 0xc88c, 0x21, 0 - .dw 0x69c0, 0xc88c, 0x69ff, 0xc88c, 0x21, 0 - .dw 0x6a40, 0xc88c, 0x6a7f, 0xc88c, 0x21, 0 - .dw 0x6ac0, 0xc88c, 0x6aff, 0xc88c, 0x21, 0 - .dw 0x6b40, 0xc88c, 0x6b7f, 0xc88c, 0x21, 0 - .dw 0x6bc0, 0xc88c, 0x6bff, 0xc88c, 0x21, 0 - .dw 0x6c40, 0xc88c, 0x6c7f, 0xc88c, 0x21, 0 - .dw 0x6cc0, 0xc88c, 0x6cff, 0xc88c, 0x21, 0 - .dw 0x6d40, 0xc88c, 0x6d7f, 0xc88c, 0x21, 0 - .dw 0x6dc0, 0xc88c, 0x6dff, 0xc88c, 0x21, 0 - .dw 0x6e40, 0xc88c, 0x6e7f, 0xc88c, 0x21, 0 - .dw 0x6ec0, 0xc88c, 0x6eff, 0xc88c, 0x21, 0 - .dw 0x6f40, 0xc88c, 0x6f7f, 0xc88c, 0x21, 0 - .dw 0x6fc0, 0xc88c, 0x6fff, 0xc88c, 0x21, 0 - .dw 0x7040, 0xc88c, 0x707f, 0xc88c, 0x21, 0 - .dw 0x70c0, 0xc88c, 0x70ff, 0xc88c, 0x21, 0 - .dw 0x7140, 0xc88c, 0x717f, 0xc88c, 0x21, 0 - .dw 0x71c0, 0xc88c, 0x71ff, 0xc88c, 0x21, 0 - .dw 0x7240, 0xc88c, 0x727f, 0xc88c, 0x21, 0 - .dw 0x72c0, 0xc88c, 0x72ff, 0xc88c, 0x21, 0 - .dw 0x7340, 0xc88c, 0x737f, 0xc88c, 0x21, 0 - .dw 0x73c0, 0xc88c, 0x73ff, 0xc88c, 0x21, 0 - .dw 0x7440, 0xc88c, 0x747f, 0xc88c, 0x21, 0 - .dw 0x74c0, 0xc88c, 0x74ff, 0xc88c, 0x21, 0 - .dw 0x7540, 0xc88c, 0x757f, 0xc88c, 0x21, 0 - .dw 0x75c0, 0xc88c, 0x75ff, 0xc88c, 0x21, 0 - .dw 0x7640, 0xc88c, 0x767f, 0xc88c, 0x21, 0 - .dw 0x76c0, 0xc88c, 0x76ff, 0xc88c, 0x21, 0 - .dw 0x7740, 0xc88c, 0x777f, 0xc88c, 0x21, 0 - .dw 0x77c0, 0xc88c, 0x77ff, 0xc88c, 0x21, 0 - .dw 0x7840, 0xc88c, 0x787f, 0xc88c, 0x21, 0 - .dw 0x78c0, 0xc88c, 0x78ff, 0xc88c, 0x21, 0 - .dw 0x7940, 0xc88c, 0x797f, 0xc88c, 0x21, 0 - .dw 0x79c0, 0xc88c, 0x7fff, 0xc88c, 0x21, 0 - .dw 0x8040, 0xc88c, 0x807f, 0xc88c, 0x21, 0 - .dw 0x80c0, 0xc88c, 0x80ff, 0xc88c, 0x21, 0 - .dw 0x8140, 0xc88c, 0x817f, 0xc88c, 0x21, 0 - .dw 0x81c0, 0xc88c, 0x81ff, 0xc88c, 0x21, 0 - .dw 0x8240, 0xc88c, 0x827f, 0xc88c, 0x21, 0 - .dw 0x82c0, 0xc88c, 0x82ff, 0xc88c, 0x21, 0 - .dw 0x8340, 0xc88c, 0x837f, 0xc88c, 0x21, 0 - .dw 0x83c0, 0xc88c, 0x83ff, 0xc88c, 0x21, 0 - .dw 0x8440, 0xc88c, 0x847f, 0xc88c, 0x21, 0 - .dw 0x84c0, 0xc88c, 0x84ff, 0xc88c, 0x21, 0 - .dw 0x8540, 0xc88c, 0x857f, 0xc88c, 0x21, 0 - .dw 0x85c0, 0xc88c, 0x85ff, 0xc88c, 0x21, 0 - .dw 0x8640, 0xc88c, 0x867f, 0xc88c, 0x21, 0 - .dw 0x86c0, 0xc88c, 0x86ff, 0xc88c, 0x21, 0 - .dw 0x8740, 0xc88c, 0x877f, 0xc88c, 0x21, 0 - .dw 0x87c0, 0xc88c, 0x87ff, 0xc88c, 0x21, 0 - .dw 0x8840, 0xc88c, 0x887f, 0xc88c, 0x21, 0 - .dw 0x88c0, 0xc88c, 0x88ff, 0xc88c, 0x21, 0 - .dw 0x8940, 0xc88c, 0x897f, 0xc88c, 0x21, 0 - .dw 0x89c0, 0xc88c, 0x89ff, 0xc88c, 0x21, 0 - .dw 0x8a40, 0xc88c, 0x8a7f, 0xc88c, 0x21, 0 - .dw 0x8ac0, 0xc88c, 0x8aff, 0xc88c, 0x21, 0 - .dw 0x8b40, 0xc88c, 0x8b7f, 0xc88c, 0x21, 0 - .dw 0x8bc0, 0xc88c, 0x8bff, 0xc88c, 0x21, 0 - .dw 0x8c40, 0xc88c, 0x8c7f, 0xc88c, 0x21, 0 - .dw 0x8cc0, 0xc88c, 0x8cff, 0xc88c, 0x21, 0 - .dw 0x8d40, 0xc88c, 0x8d7f, 0xc88c, 0x21, 0 - .dw 0x8dc0, 0xc88c, 0x8dff, 0xc88c, 0x21, 0 - .dw 0x8e40, 0xc88c, 0x8e7f, 0xc88c, 0x21, 0 - .dw 0x8ec0, 0xc88c, 0x8eff, 0xc88c, 0x21, 0 - .dw 0x8f40, 0xc88c, 0x8f7f, 0xc88c, 0x21, 0 - .dw 0x8fc0, 0xc88c, 0x8fff, 0xc88c, 0x21, 0 - .dw 0x9040, 0xc88c, 0x907f, 0xc88c, 0x21, 0 - .dw 0x90c0, 0xc88c, 0x90ff, 0xc88c, 0x21, 0 - .dw 0x9140, 0xc88c, 0x917f, 0xc88c, 0x21, 0 - .dw 0x91c0, 0xc88c, 0x91ff, 0xc88c, 0x21, 0 - .dw 0x9240, 0xc88c, 0x927f, 0xc88c, 0x21, 0 - .dw 0x92c0, 0xc88c, 0x92ff, 0xc88c, 0x21, 0 - .dw 0x9340, 0xc88c, 0x937f, 0xc88c, 0x21, 0 - .dw 0x93c0, 0xc88c, 0x93ff, 0xc88c, 0x21, 0 - .dw 0x9440, 0xc88c, 0x947f, 0xc88c, 0x21, 0 - .dw 0x94c0, 0xc88c, 0x94ff, 0xc88c, 0x21, 0 - .dw 0x9540, 0xc88c, 0x957f, 0xc88c, 0x21, 0 - .dw 0x95c0, 0xc88c, 0x95ff, 0xc88c, 0x21, 0 - .dw 0x9640, 0xc88c, 0x967f, 0xc88c, 0x21, 0 - .dw 0x96c0, 0xc88c, 0x96ff, 0xc88c, 0x21, 0 - .dw 0x9740, 0xc88c, 0x977f, 0xc88c, 0x21, 0 - .dw 0x97c0, 0xc88c, 0x97ff, 0xc88c, 0x21, 0 - .dw 0x9840, 0xc88c, 0x987f, 0xc88c, 0x21, 0 - .dw 0x98c0, 0xc88c, 0x98ff, 0xc88c, 0x21, 0 - .dw 0x9940, 0xc88c, 0x997f, 0xc88c, 0x21, 0 - .dw 0x99c0, 0xc88c, 0x9fff, 0xc88c, 0x21, 0 - .dw 0xa040, 0xc88c, 0xa07f, 0xc88c, 0x21, 0 - .dw 0xa0c0, 0xc88c, 0xa0ff, 0xc88c, 0x21, 0 - .dw 0xa140, 0xc88c, 0xa17f, 0xc88c, 0x21, 0 - .dw 0xa1c0, 0xc88c, 0xa1ff, 0xc88c, 0x21, 0 - .dw 0xa240, 0xc88c, 0xa27f, 0xc88c, 0x21, 0 - .dw 0xa2c0, 0xc88c, 0xa2ff, 0xc88c, 0x21, 0 - .dw 0xa340, 0xc88c, 0xa37f, 0xc88c, 0x21, 0 - .dw 0xa3c0, 0xc88c, 0xa3ff, 0xc88c, 0x21, 0 - .dw 0xa440, 0xc88c, 0xa47f, 0xc88c, 0x21, 0 - .dw 0xa4c0, 0xc88c, 0xa4ff, 0xc88c, 0x21, 0 - .dw 0xa540, 0xc88c, 0xa57f, 0xc88c, 0x21, 0 - .dw 0xa5c0, 0xc88c, 0xa5ff, 0xc88c, 0x21, 0 - .dw 0xa640, 0xc88c, 0xa67f, 0xc88c, 0x21, 0 - .dw 0xa6c0, 0xc88c, 0xa6ff, 0xc88c, 0x21, 0 - .dw 0xa740, 0xc88c, 0xa77f, 0xc88c, 0x21, 0 - .dw 0xa7c0, 0xc88c, 0xa7ff, 0xc88c, 0x21, 0 - .dw 0xa840, 0xc88c, 0xa87f, 0xc88c, 0x21, 0 - .dw 0xa8c0, 0xc88c, 0xa8ff, 0xc88c, 0x21, 0 - .dw 0xa940, 0xc88c, 0xa97f, 0xc88c, 0x21, 0 - .dw 0xa9c0, 0xc88c, 0xa9ff, 0xc88c, 0x21, 0 - .dw 0xaa40, 0xc88c, 0xaa7f, 0xc88c, 0x21, 0 - .dw 0xaac0, 0xc88c, 0xaaff, 0xc88c, 0x21, 0 - .dw 0xab40, 0xc88c, 0xab7f, 0xc88c, 0x21, 0 - .dw 0xabc0, 0xc88c, 0xabff, 0xc88c, 0x21, 0 - .dw 0xac40, 0xc88c, 0xac7f, 0xc88c, 0x21, 0 - .dw 0xacc0, 0xc88c, 0xacff, 0xc88c, 0x21, 0 - .dw 0xad40, 0xc88c, 0xad7f, 0xc88c, 0x21, 0 - .dw 0xadc0, 0xc88c, 0xadff, 0xc88c, 0x21, 0 - .dw 0xae40, 0xc88c, 0xae7f, 0xc88c, 0x21, 0 - .dw 0xaec0, 0xc88c, 0xaeff, 0xc88c, 0x21, 0 - .dw 0xaf40, 0xc88c, 0xaf7f, 0xc88c, 0x21, 0 - .dw 0xafc0, 0xc88c, 0xafff, 0xc88c, 0x21, 0 - .dw 0xb040, 0xc88c, 0xb07f, 0xc88c, 0x21, 0 - .dw 0xb0c0, 0xc88c, 0xb0ff, 0xc88c, 0x21, 0 - .dw 0xb140, 0xc88c, 0xb17f, 0xc88c, 0x21, 0 - .dw 0xb1c0, 0xc88c, 0xb1ff, 0xc88c, 0x21, 0 - .dw 0xb240, 0xc88c, 0xb27f, 0xc88c, 0x21, 0 - .dw 0xb2c0, 0xc88c, 0xb2ff, 0xc88c, 0x21, 0 - .dw 0xb340, 0xc88c, 0xb37f, 0xc88c, 0x21, 0 - .dw 0xb3c0, 0xc88c, 0xb3ff, 0xc88c, 0x21, 0 - .dw 0xb440, 0xc88c, 0xb47f, 0xc88c, 0x21, 0 - .dw 0xb4c0, 0xc88c, 0xb4ff, 0xc88c, 0x21, 0 - .dw 0xb540, 0xc88c, 0xb57f, 0xc88c, 0x21, 0 - .dw 0xb5c0, 0xc88c, 0xb5ff, 0xc88c, 0x21, 0 - .dw 0xb640, 0xc88c, 0xb67f, 0xc88c, 0x21, 0 - .dw 0xb6c0, 0xc88c, 0xb6ff, 0xc88c, 0x21, 0 - .dw 0xb740, 0xc88c, 0xb77f, 0xc88c, 0x21, 0 - .dw 0xb7c0, 0xc88c, 0xb7ff, 0xc88c, 0x21, 0 - .dw 0xb840, 0xc88c, 0xb87f, 0xc88c, 0x21, 0 - .dw 0xb8c0, 0xc88c, 0xb8ff, 0xc88c, 0x21, 0 - .dw 0xb940, 0xc88c, 0xb97f, 0xc88c, 0x21, 0 - .dw 0xb9c0, 0xc88c, 0xbfff, 0xc88c, 0x21, 0 - .dw 0xc040, 0xc88c, 0xc07f, 0xc88c, 0x21, 0 - .dw 0xc0c0, 0xc88c, 0xc0ff, 0xc88c, 0x21, 0 - .dw 0xc140, 0xc88c, 0xc17f, 0xc88c, 0x21, 0 - .dw 0xc1c0, 0xc88c, 0xc1ff, 0xc88c, 0x21, 0 - .dw 0xc240, 0xc88c, 0xc27f, 0xc88c, 0x21, 0 - .dw 0xc2c0, 0xc88c, 0xc2ff, 0xc88c, 0x21, 0 - .dw 0xc340, 0xc88c, 0xc37f, 0xc88c, 0x21, 0 - .dw 0xc3c0, 0xc88c, 0xc3ff, 0xc88c, 0x21, 0 - .dw 0xc440, 0xc88c, 0xc47f, 0xc88c, 0x21, 0 - .dw 0xc4c0, 0xc88c, 0xc4ff, 0xc88c, 0x21, 0 - .dw 0xc540, 0xc88c, 0xc57f, 0xc88c, 0x21, 0 - .dw 0xc5c0, 0xc88c, 0xc5ff, 0xc88c, 0x21, 0 - .dw 0xc640, 0xc88c, 0xc67f, 0xc88c, 0x21, 0 - .dw 0xc6c0, 0xc88c, 0xc6ff, 0xc88c, 0x21, 0 - .dw 0xc740, 0xc88c, 0xc77f, 0xc88c, 0x21, 0 - .dw 0xc7c0, 0xc88c, 0xc7ff, 0xc88c, 0x21, 0 - .dw 0xc840, 0xc88c, 0xc87f, 0xc88c, 0x21, 0 - .dw 0xc8c0, 0xc88c, 0xc8ff, 0xc88c, 0x21, 0 - .dw 0xc940, 0xc88c, 0xc97f, 0xc88c, 0x21, 0 - .dw 0xc9c0, 0xc88c, 0xc9ff, 0xc88c, 0x21, 0 - .dw 0xca40, 0xc88c, 0xca7f, 0xc88c, 0x21, 0 - .dw 0xcac0, 0xc88c, 0xcaff, 0xc88c, 0x21, 0 - .dw 0xcb40, 0xc88c, 0xcb7f, 0xc88c, 0x21, 0 - .dw 0xcbc0, 0xc88c, 0xcbff, 0xc88c, 0x21, 0 - .dw 0xcc40, 0xc88c, 0xcc7f, 0xc88c, 0x21, 0 - .dw 0xccc0, 0xc88c, 0xccff, 0xc88c, 0x21, 0 - .dw 0xcd40, 0xc88c, 0xcd7f, 0xc88c, 0x21, 0 - .dw 0xcdc0, 0xc88c, 0xcdff, 0xc88c, 0x21, 0 - .dw 0xce40, 0xc88c, 0xce7f, 0xc88c, 0x21, 0 - .dw 0xcec0, 0xc88c, 0xceff, 0xc88c, 0x21, 0 - .dw 0xcf40, 0xc88c, 0xcf7f, 0xc88c, 0x21, 0 - .dw 0xcfc0, 0xc88c, 0xcfff, 0xc88c, 0x21, 0 - .dw 0xd040, 0xc88c, 0xd07f, 0xc88c, 0x21, 0 - .dw 0xd0c0, 0xc88c, 0xd0ff, 0xc88c, 0x21, 0 - .dw 0xd140, 0xc88c, 0xd17f, 0xc88c, 0x21, 0 - .dw 0xd1c0, 0xc88c, 0xd1ff, 0xc88c, 0x21, 0 - .dw 0xd240, 0xc88c, 0xd27f, 0xc88c, 0x21, 0 - .dw 0xd2c0, 0xc88c, 0xd2ff, 0xc88c, 0x21, 0 - .dw 0xd340, 0xc88c, 0xd37f, 0xc88c, 0x21, 0 - .dw 0xd3c0, 0xc88c, 0xd3ff, 0xc88c, 0x21, 0 - .dw 0xd440, 0xc88c, 0xd47f, 0xc88c, 0x21, 0 - .dw 0xd4c0, 0xc88c, 0xd4ff, 0xc88c, 0x21, 0 - .dw 0xd540, 0xc88c, 0xd57f, 0xc88c, 0x21, 0 - .dw 0xd5c0, 0xc88c, 0xd5ff, 0xc88c, 0x21, 0 - .dw 0xd640, 0xc88c, 0xd67f, 0xc88c, 0x21, 0 - .dw 0xd6c0, 0xc88c, 0xd6ff, 0xc88c, 0x21, 0 - .dw 0xd740, 0xc88c, 0xd77f, 0xc88c, 0x21, 0 - .dw 0xd7c0, 0xc88c, 0xd7ff, 0xc88c, 0x21, 0 - .dw 0xd840, 0xc88c, 0xd87f, 0xc88c, 0x21, 0 - .dw 0xd8c0, 0xc88c, 0xd8ff, 0xc88c, 0x21, 0 - .dw 0xd940, 0xc88c, 0xd97f, 0xc88c, 0x21, 0 - .dw 0xd9c0, 0xc88c, 0xdfff, 0xc88c, 0x21, 0 - .dw 0xe040, 0xc88c, 0xe07f, 0xc88c, 0x21, 0 - .dw 0xe0c0, 0xc88c, 0xe0ff, 0xc88c, 0x21, 0 - .dw 0xe140, 0xc88c, 0xe17f, 0xc88c, 0x21, 0 - .dw 0xe1c0, 0xc88c, 0xe1ff, 0xc88c, 0x21, 0 - .dw 0xe240, 0xc88c, 0xe27f, 0xc88c, 0x21, 0 - .dw 0xe2c0, 0xc88c, 0xe2ff, 0xc88c, 0x21, 0 - .dw 0xe340, 0xc88c, 0xe37f, 0xc88c, 0x21, 0 - .dw 0xe3c0, 0xc88c, 0xe3ff, 0xc88c, 0x21, 0 - .dw 0xe440, 0xc88c, 0xe47f, 0xc88c, 0x21, 0 - .dw 0xe4c0, 0xc88c, 0xe4ff, 0xc88c, 0x21, 0 - .dw 0xe540, 0xc88c, 0xe57f, 0xc88c, 0x21, 0 - .dw 0xe5c0, 0xc88c, 0xe5ff, 0xc88c, 0x21, 0 - .dw 0xe640, 0xc88c, 0xe67f, 0xc88c, 0x21, 0 - .dw 0xe6c0, 0xc88c, 0xe6ff, 0xc88c, 0x21, 0 - .dw 0xe740, 0xc88c, 0xe77f, 0xc88c, 0x21, 0 - .dw 0xe7c0, 0xc88c, 0xe7ff, 0xc88c, 0x21, 0 - .dw 0xe840, 0xc88c, 0xe87f, 0xc88c, 0x21, 0 - .dw 0xe8c0, 0xc88c, 0xe8ff, 0xc88c, 0x21, 0 - .dw 0xe940, 0xc88c, 0xe97f, 0xc88c, 0x21, 0 - .dw 0xe9c0, 0xc88c, 0xe9ff, 0xc88c, 0x21, 0 - .dw 0xea40, 0xc88c, 0xea7f, 0xc88c, 0x21, 0 - .dw 0xeac0, 0xc88c, 0xeaff, 0xc88c, 0x21, 0 - .dw 0xeb40, 0xc88c, 0xeb7f, 0xc88c, 0x21, 0 - .dw 0xebc0, 0xc88c, 0xebff, 0xc88c, 0x21, 0 - .dw 0xec40, 0xc88c, 0xec7f, 0xc88c, 0x21, 0 - .dw 0xecc0, 0xc88c, 0xecff, 0xc88c, 0x21, 0 - .dw 0xed40, 0xc88c, 0xed7f, 0xc88c, 0x21, 0 - .dw 0xedc0, 0xc88c, 0xedff, 0xc88c, 0x21, 0 - .dw 0xee40, 0xc88c, 0xee7f, 0xc88c, 0x21, 0 - .dw 0xeec0, 0xc88c, 0xeeff, 0xc88c, 0x21, 0 - .dw 0xef40, 0xc88c, 0xef7f, 0xc88c, 0x21, 0 - .dw 0xefc0, 0xc88c, 0xefff, 0xc88c, 0x21, 0 - .dw 0xf040, 0xc88c, 0xf07f, 0xc88c, 0x21, 0 - .dw 0xf0c0, 0xc88c, 0xf0ff, 0xc88c, 0x21, 0 - .dw 0xf140, 0xc88c, 0xf17f, 0xc88c, 0x21, 0 - .dw 0xf1c0, 0xc88c, 0xf1ff, 0xc88c, 0x21, 0 - .dw 0xf240, 0xc88c, 0xf27f, 0xc88c, 0x21, 0 - .dw 0xf2c0, 0xc88c, 0xf2ff, 0xc88c, 0x21, 0 - .dw 0xf340, 0xc88c, 0xf37f, 0xc88c, 0x21, 0 - .dw 0xf3c0, 0xc88c, 0xf3ff, 0xc88c, 0x21, 0 - .dw 0xf440, 0xc88c, 0xf47f, 0xc88c, 0x21, 0 - .dw 0xf4c0, 0xc88c, 0xf4ff, 0xc88c, 0x21, 0 - .dw 0xf540, 0xc88c, 0xf57f, 0xc88c, 0x21, 0 - .dw 0xf5c0, 0xc88c, 0xf5ff, 0xc88c, 0x21, 0 - .dw 0xf640, 0xc88c, 0xf67f, 0xc88c, 0x21, 0 - .dw 0xf6c0, 0xc88c, 0xf6ff, 0xc88c, 0x21, 0 - .dw 0xf740, 0xc88c, 0xf77f, 0xc88c, 0x21, 0 - .dw 0xf7c0, 0xc88c, 0xf7ff, 0xc88c, 0x21, 0 - .dw 0xf840, 0xc88c, 0xf87f, 0xc88c, 0x21, 0 - .dw 0xf8c0, 0xc88c, 0xf8ff, 0xc88c, 0x21, 0 - .dw 0xf940, 0xc88c, 0xf97f, 0xc88c, 0x21, 0 - .dw 0xf9c0, 0xc88c, 0xffff, 0xc88c, 0x21, 0 - .dw 0x0040, 0xc88d, 0x007f, 0xc88d, 0x21, 0 - .dw 0x00c0, 0xc88d, 0x00ff, 0xc88d, 0x21, 0 - .dw 0x0140, 0xc88d, 0x017f, 0xc88d, 0x21, 0 - .dw 0x01c0, 0xc88d, 0x01ff, 0xc88d, 0x21, 0 - .dw 0x0240, 0xc88d, 0x027f, 0xc88d, 0x21, 0 - .dw 0x02c0, 0xc88d, 0x02ff, 0xc88d, 0x21, 0 - .dw 0x0340, 0xc88d, 0x037f, 0xc88d, 0x21, 0 - .dw 0x03c0, 0xc88d, 0x03ff, 0xc88d, 0x21, 0 - .dw 0x0440, 0xc88d, 0x047f, 0xc88d, 0x21, 0 - .dw 0x04c0, 0xc88d, 0x04ff, 0xc88d, 0x21, 0 - .dw 0x0540, 0xc88d, 0x057f, 0xc88d, 0x21, 0 - .dw 0x05c0, 0xc88d, 0x05ff, 0xc88d, 0x21, 0 - .dw 0x0640, 0xc88d, 0x067f, 0xc88d, 0x21, 0 - .dw 0x06c0, 0xc88d, 0x06ff, 0xc88d, 0x21, 0 - .dw 0x0740, 0xc88d, 0x077f, 0xc88d, 0x21, 0 - .dw 0x07c0, 0xc88d, 0x07ff, 0xc88d, 0x21, 0 - .dw 0x0840, 0xc88d, 0x087f, 0xc88d, 0x21, 0 - .dw 0x08c0, 0xc88d, 0x08ff, 0xc88d, 0x21, 0 - .dw 0x0940, 0xc88d, 0x097f, 0xc88d, 0x21, 0 - .dw 0x09c0, 0xc88d, 0x09ff, 0xc88d, 0x21, 0 - .dw 0x0a40, 0xc88d, 0x0a7f, 0xc88d, 0x21, 0 - .dw 0x0ac0, 0xc88d, 0x0aff, 0xc88d, 0x21, 0 - .dw 0x0b40, 0xc88d, 0x0b7f, 0xc88d, 0x21, 0 - .dw 0x0bc0, 0xc88d, 0x0bff, 0xc88d, 0x21, 0 - .dw 0x0c40, 0xc88d, 0x0c7f, 0xc88d, 0x21, 0 - .dw 0x0cc0, 0xc88d, 0x0cff, 0xc88d, 0x21, 0 - .dw 0x0d40, 0xc88d, 0x0d7f, 0xc88d, 0x21, 0 - .dw 0x0dc0, 0xc88d, 0x0dff, 0xc88d, 0x21, 0 - .dw 0x0e40, 0xc88d, 0x0e7f, 0xc88d, 0x21, 0 - .dw 0x0ec0, 0xc88d, 0x0eff, 0xc88d, 0x21, 0 - .dw 0x0f40, 0xc88d, 0x0f7f, 0xc88d, 0x21, 0 - .dw 0x0fc0, 0xc88d, 0x0fff, 0xc88d, 0x21, 0 - .dw 0x1040, 0xc88d, 0x107f, 0xc88d, 0x21, 0 - .dw 0x10c0, 0xc88d, 0x10ff, 0xc88d, 0x21, 0 - .dw 0x1140, 0xc88d, 0x117f, 0xc88d, 0x21, 0 - .dw 0x11c0, 0xc88d, 0x11ff, 0xc88d, 0x21, 0 - .dw 0x1240, 0xc88d, 0x127f, 0xc88d, 0x21, 0 - .dw 0x12c0, 0xc88d, 0x12ff, 0xc88d, 0x21, 0 - .dw 0x1340, 0xc88d, 0x137f, 0xc88d, 0x21, 0 - .dw 0x13c0, 0xc88d, 0x13ff, 0xc88d, 0x21, 0 - .dw 0x1440, 0xc88d, 0x147f, 0xc88d, 0x21, 0 - .dw 0x14c0, 0xc88d, 0x14ff, 0xc88d, 0x21, 0 - .dw 0x1540, 0xc88d, 0x157f, 0xc88d, 0x21, 0 - .dw 0x15c0, 0xc88d, 0x15ff, 0xc88d, 0x21, 0 - .dw 0x1640, 0xc88d, 0x167f, 0xc88d, 0x21, 0 - .dw 0x16c0, 0xc88d, 0x16ff, 0xc88d, 0x21, 0 - .dw 0x1740, 0xc88d, 0x177f, 0xc88d, 0x21, 0 - .dw 0x17c0, 0xc88d, 0x17ff, 0xc88d, 0x21, 0 - .dw 0x1840, 0xc88d, 0x187f, 0xc88d, 0x21, 0 - .dw 0x18c0, 0xc88d, 0x18ff, 0xc88d, 0x21, 0 - .dw 0x1940, 0xc88d, 0x197f, 0xc88d, 0x21, 0 - .dw 0x19c0, 0xc88d, 0x1fff, 0xc88d, 0x21, 0 - .dw 0x2040, 0xc88d, 0x207f, 0xc88d, 0x21, 0 - .dw 0x20c0, 0xc88d, 0x20ff, 0xc88d, 0x21, 0 - .dw 0x2140, 0xc88d, 0x217f, 0xc88d, 0x21, 0 - .dw 0x21c0, 0xc88d, 0x21ff, 0xc88d, 0x21, 0 - .dw 0x2240, 0xc88d, 0x227f, 0xc88d, 0x21, 0 - .dw 0x22c0, 0xc88d, 0x22ff, 0xc88d, 0x21, 0 - .dw 0x2340, 0xc88d, 0x237f, 0xc88d, 0x21, 0 - .dw 0x23c0, 0xc88d, 0x23ff, 0xc88d, 0x21, 0 - .dw 0x2440, 0xc88d, 0x247f, 0xc88d, 0x21, 0 - .dw 0x24c0, 0xc88d, 0x24ff, 0xc88d, 0x21, 0 - .dw 0x2540, 0xc88d, 0x257f, 0xc88d, 0x21, 0 - .dw 0x25c0, 0xc88d, 0x25ff, 0xc88d, 0x21, 0 - .dw 0x2640, 0xc88d, 0x267f, 0xc88d, 0x21, 0 - .dw 0x26c0, 0xc88d, 0x26ff, 0xc88d, 0x21, 0 - .dw 0x2740, 0xc88d, 0x277f, 0xc88d, 0x21, 0 - .dw 0x27c0, 0xc88d, 0x27ff, 0xc88d, 0x21, 0 - .dw 0x2840, 0xc88d, 0x287f, 0xc88d, 0x21, 0 - .dw 0x28c0, 0xc88d, 0x28ff, 0xc88d, 0x21, 0 - .dw 0x2940, 0xc88d, 0x297f, 0xc88d, 0x21, 0 - .dw 0x29c0, 0xc88d, 0x29ff, 0xc88d, 0x21, 0 - .dw 0x2a40, 0xc88d, 0x2a7f, 0xc88d, 0x21, 0 - .dw 0x2ac0, 0xc88d, 0x2aff, 0xc88d, 0x21, 0 - .dw 0x2b40, 0xc88d, 0x2b7f, 0xc88d, 0x21, 0 - .dw 0x2bc0, 0xc88d, 0x2bff, 0xc88d, 0x21, 0 - .dw 0x2c40, 0xc88d, 0x2c7f, 0xc88d, 0x21, 0 - .dw 0x2cc0, 0xc88d, 0x2cff, 0xc88d, 0x21, 0 - .dw 0x2d40, 0xc88d, 0x2d7f, 0xc88d, 0x21, 0 - .dw 0x2dc0, 0xc88d, 0x2dff, 0xc88d, 0x21, 0 - .dw 0x2e40, 0xc88d, 0x2e7f, 0xc88d, 0x21, 0 - .dw 0x2ec0, 0xc88d, 0x2eff, 0xc88d, 0x21, 0 - .dw 0x2f40, 0xc88d, 0x2f7f, 0xc88d, 0x21, 0 - .dw 0x2fc0, 0xc88d, 0x2fff, 0xc88d, 0x21, 0 - .dw 0x3040, 0xc88d, 0x307f, 0xc88d, 0x21, 0 - .dw 0x30c0, 0xc88d, 0x30ff, 0xc88d, 0x21, 0 - .dw 0x3140, 0xc88d, 0x317f, 0xc88d, 0x21, 0 - .dw 0x31c0, 0xc88d, 0x31ff, 0xc88d, 0x21, 0 - .dw 0x3240, 0xc88d, 0x327f, 0xc88d, 0x21, 0 - .dw 0x32c0, 0xc88d, 0x32ff, 0xc88d, 0x21, 0 - .dw 0x3340, 0xc88d, 0x337f, 0xc88d, 0x21, 0 - .dw 0x33c0, 0xc88d, 0x33ff, 0xc88d, 0x21, 0 - .dw 0x3440, 0xc88d, 0x347f, 0xc88d, 0x21, 0 - .dw 0x34c0, 0xc88d, 0x34ff, 0xc88d, 0x21, 0 - .dw 0x3540, 0xc88d, 0x357f, 0xc88d, 0x21, 0 - .dw 0x35c0, 0xc88d, 0x35ff, 0xc88d, 0x21, 0 - .dw 0x3640, 0xc88d, 0x367f, 0xc88d, 0x21, 0 - .dw 0x36c0, 0xc88d, 0x36ff, 0xc88d, 0x21, 0 - .dw 0x3740, 0xc88d, 0x377f, 0xc88d, 0x21, 0 - .dw 0x37c0, 0xc88d, 0x37ff, 0xc88d, 0x21, 0 - .dw 0x3840, 0xc88d, 0x387f, 0xc88d, 0x21, 0 - .dw 0x38c0, 0xc88d, 0x38ff, 0xc88d, 0x21, 0 - .dw 0x3940, 0xc88d, 0x397f, 0xc88d, 0x21, 0 - .dw 0x39c0, 0xc88d, 0x3fff, 0xc88d, 0x21, 0 - .dw 0x4040, 0xc88d, 0x407f, 0xc88d, 0x21, 0 - .dw 0x40c0, 0xc88d, 0x40ff, 0xc88d, 0x21, 0 - .dw 0x4140, 0xc88d, 0x417f, 0xc88d, 0x21, 0 - .dw 0x41c0, 0xc88d, 0x41ff, 0xc88d, 0x21, 0 - .dw 0x4240, 0xc88d, 0x427f, 0xc88d, 0x21, 0 - .dw 0x42c0, 0xc88d, 0x42ff, 0xc88d, 0x21, 0 - .dw 0x4340, 0xc88d, 0x437f, 0xc88d, 0x21, 0 - .dw 0x43c0, 0xc88d, 0x43ff, 0xc88d, 0x21, 0 - .dw 0x4440, 0xc88d, 0x447f, 0xc88d, 0x21, 0 - .dw 0x44c0, 0xc88d, 0x44ff, 0xc88d, 0x21, 0 - .dw 0x4540, 0xc88d, 0x457f, 0xc88d, 0x21, 0 - .dw 0x45c0, 0xc88d, 0x45ff, 0xc88d, 0x21, 0 - .dw 0x4640, 0xc88d, 0x467f, 0xc88d, 0x21, 0 - .dw 0x46c0, 0xc88d, 0x46ff, 0xc88d, 0x21, 0 - .dw 0x4740, 0xc88d, 0x477f, 0xc88d, 0x21, 0 - .dw 0x47c0, 0xc88d, 0x47ff, 0xc88d, 0x21, 0 - .dw 0x4840, 0xc88d, 0x487f, 0xc88d, 0x21, 0 - .dw 0x48c0, 0xc88d, 0x48ff, 0xc88d, 0x21, 0 - .dw 0x4940, 0xc88d, 0x497f, 0xc88d, 0x21, 0 - .dw 0x49c0, 0xc88d, 0x49ff, 0xc88d, 0x21, 0 - .dw 0x4a40, 0xc88d, 0x4a7f, 0xc88d, 0x21, 0 - .dw 0x4ac0, 0xc88d, 0x4aff, 0xc88d, 0x21, 0 - .dw 0x4b40, 0xc88d, 0x4b7f, 0xc88d, 0x21, 0 - .dw 0x4bc0, 0xc88d, 0x4bff, 0xc88d, 0x21, 0 - .dw 0x4c40, 0xc88d, 0x4c7f, 0xc88d, 0x21, 0 - .dw 0x4cc0, 0xc88d, 0x4cff, 0xc88d, 0x21, 0 - .dw 0x4d40, 0xc88d, 0x4d7f, 0xc88d, 0x21, 0 - .dw 0x4dc0, 0xc88d, 0x4dff, 0xc88d, 0x21, 0 - .dw 0x4e40, 0xc88d, 0x4e7f, 0xc88d, 0x21, 0 - .dw 0x4ec0, 0xc88d, 0x4eff, 0xc88d, 0x21, 0 - .dw 0x4f40, 0xc88d, 0x4f7f, 0xc88d, 0x21, 0 - .dw 0x4fc0, 0xc88d, 0x4fff, 0xc88d, 0x21, 0 - .dw 0x5040, 0xc88d, 0x507f, 0xc88d, 0x21, 0 - .dw 0x50c0, 0xc88d, 0x50ff, 0xc88d, 0x21, 0 - .dw 0x5140, 0xc88d, 0x517f, 0xc88d, 0x21, 0 - .dw 0x51c0, 0xc88d, 0x51ff, 0xc88d, 0x21, 0 - .dw 0x5240, 0xc88d, 0x527f, 0xc88d, 0x21, 0 - .dw 0x52c0, 0xc88d, 0x52ff, 0xc88d, 0x21, 0 - .dw 0x5340, 0xc88d, 0x537f, 0xc88d, 0x21, 0 - .dw 0x53c0, 0xc88d, 0x53ff, 0xc88d, 0x21, 0 - .dw 0x5440, 0xc88d, 0x547f, 0xc88d, 0x21, 0 - .dw 0x54c0, 0xc88d, 0x54ff, 0xc88d, 0x21, 0 - .dw 0x5540, 0xc88d, 0x557f, 0xc88d, 0x21, 0 - .dw 0x55c0, 0xc88d, 0x55ff, 0xc88d, 0x21, 0 - .dw 0x5640, 0xc88d, 0x567f, 0xc88d, 0x21, 0 - .dw 0x56c0, 0xc88d, 0x56ff, 0xc88d, 0x21, 0 - .dw 0x5740, 0xc88d, 0x577f, 0xc88d, 0x21, 0 - .dw 0x57c0, 0xc88d, 0x57ff, 0xc88d, 0x21, 0 - .dw 0x5840, 0xc88d, 0x587f, 0xc88d, 0x21, 0 - .dw 0x58c0, 0xc88d, 0x58ff, 0xc88d, 0x21, 0 - .dw 0x5940, 0xc88d, 0x597f, 0xc88d, 0x21, 0 - .dw 0x59c0, 0xc88d, 0x5fff, 0xc88d, 0x21, 0 - .dw 0x6040, 0xc88d, 0x607f, 0xc88d, 0x21, 0 - .dw 0x60c0, 0xc88d, 0x60ff, 0xc88d, 0x21, 0 - .dw 0x6140, 0xc88d, 0x617f, 0xc88d, 0x21, 0 - .dw 0x61c0, 0xc88d, 0x61ff, 0xc88d, 0x21, 0 - .dw 0x6240, 0xc88d, 0x627f, 0xc88d, 0x21, 0 - .dw 0x62c0, 0xc88d, 0x62ff, 0xc88d, 0x21, 0 - .dw 0x6340, 0xc88d, 0x637f, 0xc88d, 0x21, 0 - .dw 0x63c0, 0xc88d, 0x63ff, 0xc88d, 0x21, 0 - .dw 0x6440, 0xc88d, 0x647f, 0xc88d, 0x21, 0 - .dw 0x64c0, 0xc88d, 0x64ff, 0xc88d, 0x21, 0 - .dw 0x6540, 0xc88d, 0x657f, 0xc88d, 0x21, 0 - .dw 0x65c0, 0xc88d, 0x65ff, 0xc88d, 0x21, 0 - .dw 0x6640, 0xc88d, 0x667f, 0xc88d, 0x21, 0 - .dw 0x66c0, 0xc88d, 0x66ff, 0xc88d, 0x21, 0 - .dw 0x6740, 0xc88d, 0x677f, 0xc88d, 0x21, 0 - .dw 0x67c0, 0xc88d, 0x67ff, 0xc88d, 0x21, 0 - .dw 0x6840, 0xc88d, 0x687f, 0xc88d, 0x21, 0 - .dw 0x68c0, 0xc88d, 0x68ff, 0xc88d, 0x21, 0 - .dw 0x6940, 0xc88d, 0x697f, 0xc88d, 0x21, 0 - .dw 0x69c0, 0xc88d, 0x69ff, 0xc88d, 0x21, 0 - .dw 0x6a40, 0xc88d, 0x6a7f, 0xc88d, 0x21, 0 - .dw 0x6ac0, 0xc88d, 0x6aff, 0xc88d, 0x21, 0 - .dw 0x6b40, 0xc88d, 0x6b7f, 0xc88d, 0x21, 0 - .dw 0x6bc0, 0xc88d, 0x6bff, 0xc88d, 0x21, 0 - .dw 0x6c40, 0xc88d, 0x6c7f, 0xc88d, 0x21, 0 - .dw 0x6cc0, 0xc88d, 0x6cff, 0xc88d, 0x21, 0 - .dw 0x6d40, 0xc88d, 0x6d7f, 0xc88d, 0x21, 0 - .dw 0x6dc0, 0xc88d, 0x6dff, 0xc88d, 0x21, 0 - .dw 0x6e40, 0xc88d, 0x6e7f, 0xc88d, 0x21, 0 - .dw 0x6ec0, 0xc88d, 0x6eff, 0xc88d, 0x21, 0 - .dw 0x6f40, 0xc88d, 0x6f7f, 0xc88d, 0x21, 0 - .dw 0x6fc0, 0xc88d, 0x6fff, 0xc88d, 0x21, 0 - .dw 0x7040, 0xc88d, 0x707f, 0xc88d, 0x21, 0 - .dw 0x70c0, 0xc88d, 0x70ff, 0xc88d, 0x21, 0 - .dw 0x7140, 0xc88d, 0x717f, 0xc88d, 0x21, 0 - .dw 0x71c0, 0xc88d, 0x71ff, 0xc88d, 0x21, 0 - .dw 0x7240, 0xc88d, 0x727f, 0xc88d, 0x21, 0 - .dw 0x72c0, 0xc88d, 0x72ff, 0xc88d, 0x21, 0 - .dw 0x7340, 0xc88d, 0x737f, 0xc88d, 0x21, 0 - .dw 0x73c0, 0xc88d, 0x73ff, 0xc88d, 0x21, 0 - .dw 0x7440, 0xc88d, 0x747f, 0xc88d, 0x21, 0 - .dw 0x74c0, 0xc88d, 0x74ff, 0xc88d, 0x21, 0 - .dw 0x7540, 0xc88d, 0x757f, 0xc88d, 0x21, 0 - .dw 0x75c0, 0xc88d, 0x75ff, 0xc88d, 0x21, 0 - .dw 0x7640, 0xc88d, 0x767f, 0xc88d, 0x21, 0 - .dw 0x76c0, 0xc88d, 0x76ff, 0xc88d, 0x21, 0 - .dw 0x7740, 0xc88d, 0x777f, 0xc88d, 0x21, 0 - .dw 0x77c0, 0xc88d, 0x77ff, 0xc88d, 0x21, 0 - .dw 0x7840, 0xc88d, 0x787f, 0xc88d, 0x21, 0 - .dw 0x78c0, 0xc88d, 0x78ff, 0xc88d, 0x21, 0 - .dw 0x7940, 0xc88d, 0x797f, 0xc88d, 0x21, 0 - .dw 0x79c0, 0xc88d, 0x7fff, 0xc88d, 0x21, 0 - .dw 0x8040, 0xc88d, 0x807f, 0xc88d, 0x21, 0 - .dw 0x80c0, 0xc88d, 0x80ff, 0xc88d, 0x21, 0 - .dw 0x8140, 0xc88d, 0x817f, 0xc88d, 0x21, 0 - .dw 0x81c0, 0xc88d, 0x81ff, 0xc88d, 0x21, 0 - .dw 0x8240, 0xc88d, 0x827f, 0xc88d, 0x21, 0 - .dw 0x82c0, 0xc88d, 0x82ff, 0xc88d, 0x21, 0 - .dw 0x8340, 0xc88d, 0x837f, 0xc88d, 0x21, 0 - .dw 0x83c0, 0xc88d, 0x83ff, 0xc88d, 0x21, 0 - .dw 0x8440, 0xc88d, 0x847f, 0xc88d, 0x21, 0 - .dw 0x84c0, 0xc88d, 0x84ff, 0xc88d, 0x21, 0 - .dw 0x8540, 0xc88d, 0x857f, 0xc88d, 0x21, 0 - .dw 0x85c0, 0xc88d, 0x85ff, 0xc88d, 0x21, 0 - .dw 0x8640, 0xc88d, 0x867f, 0xc88d, 0x21, 0 - .dw 0x86c0, 0xc88d, 0x86ff, 0xc88d, 0x21, 0 - .dw 0x8740, 0xc88d, 0x877f, 0xc88d, 0x21, 0 - .dw 0x87c0, 0xc88d, 0x87ff, 0xc88d, 0x21, 0 - .dw 0x8840, 0xc88d, 0x887f, 0xc88d, 0x21, 0 - .dw 0x88c0, 0xc88d, 0x88ff, 0xc88d, 0x21, 0 - .dw 0x8940, 0xc88d, 0x897f, 0xc88d, 0x21, 0 - .dw 0x89c0, 0xc88d, 0x89ff, 0xc88d, 0x21, 0 - .dw 0x8a40, 0xc88d, 0x8a7f, 0xc88d, 0x21, 0 - .dw 0x8ac0, 0xc88d, 0x8aff, 0xc88d, 0x21, 0 - .dw 0x8b40, 0xc88d, 0x8b7f, 0xc88d, 0x21, 0 - .dw 0x8bc0, 0xc88d, 0x8bff, 0xc88d, 0x21, 0 - .dw 0x8c40, 0xc88d, 0x8c7f, 0xc88d, 0x21, 0 - .dw 0x8cc0, 0xc88d, 0x8cff, 0xc88d, 0x21, 0 - .dw 0x8d40, 0xc88d, 0x8d7f, 0xc88d, 0x21, 0 - .dw 0x8dc0, 0xc88d, 0x8dff, 0xc88d, 0x21, 0 - .dw 0x8e40, 0xc88d, 0x8e7f, 0xc88d, 0x21, 0 - .dw 0x8ec0, 0xc88d, 0x8eff, 0xc88d, 0x21, 0 - .dw 0x8f40, 0xc88d, 0x8f7f, 0xc88d, 0x21, 0 - .dw 0x8fc0, 0xc88d, 0x8fff, 0xc88d, 0x21, 0 - .dw 0x9040, 0xc88d, 0x907f, 0xc88d, 0x21, 0 - .dw 0x90c0, 0xc88d, 0x90ff, 0xc88d, 0x21, 0 - .dw 0x9140, 0xc88d, 0x917f, 0xc88d, 0x21, 0 - .dw 0x91c0, 0xc88d, 0x91ff, 0xc88d, 0x21, 0 - .dw 0x9240, 0xc88d, 0x927f, 0xc88d, 0x21, 0 - .dw 0x92c0, 0xc88d, 0x92ff, 0xc88d, 0x21, 0 - .dw 0x9340, 0xc88d, 0x937f, 0xc88d, 0x21, 0 - .dw 0x93c0, 0xc88d, 0x93ff, 0xc88d, 0x21, 0 - .dw 0x9440, 0xc88d, 0x947f, 0xc88d, 0x21, 0 - .dw 0x94c0, 0xc88d, 0x94ff, 0xc88d, 0x21, 0 - .dw 0x9540, 0xc88d, 0x957f, 0xc88d, 0x21, 0 - .dw 0x95c0, 0xc88d, 0x95ff, 0xc88d, 0x21, 0 - .dw 0x9640, 0xc88d, 0x967f, 0xc88d, 0x21, 0 - .dw 0x96c0, 0xc88d, 0x96ff, 0xc88d, 0x21, 0 - .dw 0x9740, 0xc88d, 0x977f, 0xc88d, 0x21, 0 - .dw 0x97c0, 0xc88d, 0x97ff, 0xc88d, 0x21, 0 - .dw 0x9840, 0xc88d, 0x987f, 0xc88d, 0x21, 0 - .dw 0x98c0, 0xc88d, 0x98ff, 0xc88d, 0x21, 0 - .dw 0x9940, 0xc88d, 0x997f, 0xc88d, 0x21, 0 - .dw 0x99c0, 0xc88d, 0x9fff, 0xc88d, 0x21, 0 - .dw 0xa040, 0xc88d, 0xa07f, 0xc88d, 0x21, 0 - .dw 0xa0c0, 0xc88d, 0xa0ff, 0xc88d, 0x21, 0 - .dw 0xa140, 0xc88d, 0xa17f, 0xc88d, 0x21, 0 - .dw 0xa1c0, 0xc88d, 0xa1ff, 0xc88d, 0x21, 0 - .dw 0xa240, 0xc88d, 0xa27f, 0xc88d, 0x21, 0 - .dw 0xa2c0, 0xc88d, 0xa2ff, 0xc88d, 0x21, 0 - .dw 0xa340, 0xc88d, 0xa37f, 0xc88d, 0x21, 0 - .dw 0xa3c0, 0xc88d, 0xa3ff, 0xc88d, 0x21, 0 - .dw 0xa440, 0xc88d, 0xa47f, 0xc88d, 0x21, 0 - .dw 0xa4c0, 0xc88d, 0xa4ff, 0xc88d, 0x21, 0 - .dw 0xa540, 0xc88d, 0xa57f, 0xc88d, 0x21, 0 - .dw 0xa5c0, 0xc88d, 0xa5ff, 0xc88d, 0x21, 0 - .dw 0xa640, 0xc88d, 0xa67f, 0xc88d, 0x21, 0 - .dw 0xa6c0, 0xc88d, 0xa6ff, 0xc88d, 0x21, 0 - .dw 0xa740, 0xc88d, 0xa77f, 0xc88d, 0x21, 0 - .dw 0xa7c0, 0xc88d, 0xa7ff, 0xc88d, 0x21, 0 - .dw 0xa840, 0xc88d, 0xa87f, 0xc88d, 0x21, 0 - .dw 0xa8c0, 0xc88d, 0xa8ff, 0xc88d, 0x21, 0 - .dw 0xa940, 0xc88d, 0xa97f, 0xc88d, 0x21, 0 - .dw 0xa9c0, 0xc88d, 0xa9ff, 0xc88d, 0x21, 0 - .dw 0xaa40, 0xc88d, 0xaa7f, 0xc88d, 0x21, 0 - .dw 0xaac0, 0xc88d, 0xaaff, 0xc88d, 0x21, 0 - .dw 0xab40, 0xc88d, 0xab7f, 0xc88d, 0x21, 0 - .dw 0xabc0, 0xc88d, 0xabff, 0xc88d, 0x21, 0 - .dw 0xac40, 0xc88d, 0xac7f, 0xc88d, 0x21, 0 - .dw 0xacc0, 0xc88d, 0xacff, 0xc88d, 0x21, 0 - .dw 0xad40, 0xc88d, 0xad7f, 0xc88d, 0x21, 0 - .dw 0xadc0, 0xc88d, 0xadff, 0xc88d, 0x21, 0 - .dw 0xae40, 0xc88d, 0xae7f, 0xc88d, 0x21, 0 - .dw 0xaec0, 0xc88d, 0xaeff, 0xc88d, 0x21, 0 - .dw 0xaf40, 0xc88d, 0xaf7f, 0xc88d, 0x21, 0 - .dw 0xafc0, 0xc88d, 0xafff, 0xc88d, 0x21, 0 - .dw 0xb040, 0xc88d, 0xb07f, 0xc88d, 0x21, 0 - .dw 0xb0c0, 0xc88d, 0xb0ff, 0xc88d, 0x21, 0 - .dw 0xb140, 0xc88d, 0xb17f, 0xc88d, 0x21, 0 - .dw 0xb1c0, 0xc88d, 0xb1ff, 0xc88d, 0x21, 0 - .dw 0xb240, 0xc88d, 0xb27f, 0xc88d, 0x21, 0 - .dw 0xb2c0, 0xc88d, 0xb2ff, 0xc88d, 0x21, 0 - .dw 0xb340, 0xc88d, 0xb37f, 0xc88d, 0x21, 0 - .dw 0xb3c0, 0xc88d, 0xb3ff, 0xc88d, 0x21, 0 - .dw 0xb440, 0xc88d, 0xb47f, 0xc88d, 0x21, 0 - .dw 0xb4c0, 0xc88d, 0xb4ff, 0xc88d, 0x21, 0 - .dw 0xb540, 0xc88d, 0xb57f, 0xc88d, 0x21, 0 - .dw 0xb5c0, 0xc88d, 0xb5ff, 0xc88d, 0x21, 0 - .dw 0xb640, 0xc88d, 0xb67f, 0xc88d, 0x21, 0 - .dw 0xb6c0, 0xc88d, 0xb6ff, 0xc88d, 0x21, 0 - .dw 0xb740, 0xc88d, 0xb77f, 0xc88d, 0x21, 0 - .dw 0xb7c0, 0xc88d, 0xb7ff, 0xc88d, 0x21, 0 - .dw 0xb840, 0xc88d, 0xb87f, 0xc88d, 0x21, 0 - .dw 0xb8c0, 0xc88d, 0xb8ff, 0xc88d, 0x21, 0 - .dw 0xb940, 0xc88d, 0xb97f, 0xc88d, 0x21, 0 - .dw 0xb9c0, 0xc88d, 0xbfff, 0xc88d, 0x21, 0 - .dw 0xc040, 0xc88d, 0xc07f, 0xc88d, 0x21, 0 - .dw 0xc0c0, 0xc88d, 0xc0ff, 0xc88d, 0x21, 0 - .dw 0xc140, 0xc88d, 0xc17f, 0xc88d, 0x21, 0 - .dw 0xc1c0, 0xc88d, 0xc1ff, 0xc88d, 0x21, 0 - .dw 0xc240, 0xc88d, 0xc27f, 0xc88d, 0x21, 0 - .dw 0xc2c0, 0xc88d, 0xc2ff, 0xc88d, 0x21, 0 - .dw 0xc340, 0xc88d, 0xc37f, 0xc88d, 0x21, 0 - .dw 0xc3c0, 0xc88d, 0xc3ff, 0xc88d, 0x21, 0 - .dw 0xc440, 0xc88d, 0xc47f, 0xc88d, 0x21, 0 - .dw 0xc4c0, 0xc88d, 0xc4ff, 0xc88d, 0x21, 0 - .dw 0xc540, 0xc88d, 0xc57f, 0xc88d, 0x21, 0 - .dw 0xc5c0, 0xc88d, 0xc5ff, 0xc88d, 0x21, 0 - .dw 0xc640, 0xc88d, 0xc67f, 0xc88d, 0x21, 0 - .dw 0xc6c0, 0xc88d, 0xc6ff, 0xc88d, 0x21, 0 - .dw 0xc740, 0xc88d, 0xc77f, 0xc88d, 0x21, 0 - .dw 0xc7c0, 0xc88d, 0xc7ff, 0xc88d, 0x21, 0 - .dw 0xc840, 0xc88d, 0xc87f, 0xc88d, 0x21, 0 - .dw 0xc8c0, 0xc88d, 0xc8ff, 0xc88d, 0x21, 0 - .dw 0xc940, 0xc88d, 0xc97f, 0xc88d, 0x21, 0 - .dw 0xc9c0, 0xc88d, 0xc9ff, 0xc88d, 0x21, 0 - .dw 0xca40, 0xc88d, 0xca7f, 0xc88d, 0x21, 0 - .dw 0xcac0, 0xc88d, 0xcaff, 0xc88d, 0x21, 0 - .dw 0xcb40, 0xc88d, 0xcb7f, 0xc88d, 0x21, 0 - .dw 0xcbc0, 0xc88d, 0xcbff, 0xc88d, 0x21, 0 - .dw 0xcc40, 0xc88d, 0xcc7f, 0xc88d, 0x21, 0 - .dw 0xccc0, 0xc88d, 0xccff, 0xc88d, 0x21, 0 - .dw 0xcd40, 0xc88d, 0xcd7f, 0xc88d, 0x21, 0 - .dw 0xcdc0, 0xc88d, 0xcdff, 0xc88d, 0x21, 0 - .dw 0xce40, 0xc88d, 0xce7f, 0xc88d, 0x21, 0 - .dw 0xcec0, 0xc88d, 0xceff, 0xc88d, 0x21, 0 - .dw 0xcf40, 0xc88d, 0xcf7f, 0xc88d, 0x21, 0 - .dw 0xcfc0, 0xc88d, 0xcfff, 0xc88d, 0x21, 0 - .dw 0xd040, 0xc88d, 0xd07f, 0xc88d, 0x21, 0 - .dw 0xd0c0, 0xc88d, 0xd0ff, 0xc88d, 0x21, 0 - .dw 0xd140, 0xc88d, 0xd17f, 0xc88d, 0x21, 0 - .dw 0xd1c0, 0xc88d, 0xd1ff, 0xc88d, 0x21, 0 - .dw 0xd240, 0xc88d, 0xd27f, 0xc88d, 0x21, 0 - .dw 0xd2c0, 0xc88d, 0xd2ff, 0xc88d, 0x21, 0 - .dw 0xd340, 0xc88d, 0xd37f, 0xc88d, 0x21, 0 - .dw 0xd3c0, 0xc88d, 0xd3ff, 0xc88d, 0x21, 0 - .dw 0xd440, 0xc88d, 0xd47f, 0xc88d, 0x21, 0 - .dw 0xd4c0, 0xc88d, 0xd4ff, 0xc88d, 0x21, 0 - .dw 0xd540, 0xc88d, 0xd57f, 0xc88d, 0x21, 0 - .dw 0xd5c0, 0xc88d, 0xd5ff, 0xc88d, 0x21, 0 - .dw 0xd640, 0xc88d, 0xd67f, 0xc88d, 0x21, 0 - .dw 0xd6c0, 0xc88d, 0xd6ff, 0xc88d, 0x21, 0 - .dw 0xd740, 0xc88d, 0xd77f, 0xc88d, 0x21, 0 - .dw 0xd7c0, 0xc88d, 0xd7ff, 0xc88d, 0x21, 0 - .dw 0xd840, 0xc88d, 0xd87f, 0xc88d, 0x21, 0 - .dw 0xd8c0, 0xc88d, 0xd8ff, 0xc88d, 0x21, 0 - .dw 0xd940, 0xc88d, 0xd97f, 0xc88d, 0x21, 0 - .dw 0xd9c0, 0xc88d, 0xdfff, 0xc88d, 0x21, 0 - .dw 0xe040, 0xc88d, 0xe07f, 0xc88d, 0x21, 0 - .dw 0xe0c0, 0xc88d, 0xe0ff, 0xc88d, 0x21, 0 - .dw 0xe140, 0xc88d, 0xe17f, 0xc88d, 0x21, 0 - .dw 0xe1c0, 0xc88d, 0xe1ff, 0xc88d, 0x21, 0 - .dw 0xe240, 0xc88d, 0xe27f, 0xc88d, 0x21, 0 - .dw 0xe2c0, 0xc88d, 0xe2ff, 0xc88d, 0x21, 0 - .dw 0xe340, 0xc88d, 0xe37f, 0xc88d, 0x21, 0 - .dw 0xe3c0, 0xc88d, 0xe3ff, 0xc88d, 0x21, 0 - .dw 0xe440, 0xc88d, 0xe47f, 0xc88d, 0x21, 0 - .dw 0xe4c0, 0xc88d, 0xe4ff, 0xc88d, 0x21, 0 - .dw 0xe540, 0xc88d, 0xe57f, 0xc88d, 0x21, 0 - .dw 0xe5c0, 0xc88d, 0xe5ff, 0xc88d, 0x21, 0 - .dw 0xe640, 0xc88d, 0xe67f, 0xc88d, 0x21, 0 - .dw 0xe6c0, 0xc88d, 0xe6ff, 0xc88d, 0x21, 0 - .dw 0xe740, 0xc88d, 0xe77f, 0xc88d, 0x21, 0 - .dw 0xe7c0, 0xc88d, 0xe7ff, 0xc88d, 0x21, 0 - .dw 0xe840, 0xc88d, 0xe87f, 0xc88d, 0x21, 0 - .dw 0xe8c0, 0xc88d, 0xe8ff, 0xc88d, 0x21, 0 - .dw 0xe940, 0xc88d, 0xe97f, 0xc88d, 0x21, 0 - .dw 0xe9c0, 0xc88d, 0xe9ff, 0xc88d, 0x21, 0 - .dw 0xea40, 0xc88d, 0xea7f, 0xc88d, 0x21, 0 - .dw 0xeac0, 0xc88d, 0xeaff, 0xc88d, 0x21, 0 - .dw 0xeb40, 0xc88d, 0xeb7f, 0xc88d, 0x21, 0 - .dw 0xebc0, 0xc88d, 0xebff, 0xc88d, 0x21, 0 - .dw 0xec40, 0xc88d, 0xec7f, 0xc88d, 0x21, 0 - .dw 0xecc0, 0xc88d, 0xecff, 0xc88d, 0x21, 0 - .dw 0xed40, 0xc88d, 0xed7f, 0xc88d, 0x21, 0 - .dw 0xedc0, 0xc88d, 0xedff, 0xc88d, 0x21, 0 - .dw 0xee40, 0xc88d, 0xee7f, 0xc88d, 0x21, 0 - .dw 0xeec0, 0xc88d, 0xeeff, 0xc88d, 0x21, 0 - .dw 0xef40, 0xc88d, 0xef7f, 0xc88d, 0x21, 0 - .dw 0xefc0, 0xc88d, 0xefff, 0xc88d, 0x21, 0 - .dw 0xf040, 0xc88d, 0xf07f, 0xc88d, 0x21, 0 - .dw 0xf0c0, 0xc88d, 0xf0ff, 0xc88d, 0x21, 0 - .dw 0xf140, 0xc88d, 0xf17f, 0xc88d, 0x21, 0 - .dw 0xf1c0, 0xc88d, 0xf1ff, 0xc88d, 0x21, 0 - .dw 0xf240, 0xc88d, 0xf27f, 0xc88d, 0x21, 0 - .dw 0xf2c0, 0xc88d, 0xf2ff, 0xc88d, 0x21, 0 - .dw 0xf340, 0xc88d, 0xf37f, 0xc88d, 0x21, 0 - .dw 0xf3c0, 0xc88d, 0xf3ff, 0xc88d, 0x21, 0 - .dw 0xf440, 0xc88d, 0xf47f, 0xc88d, 0x21, 0 - .dw 0xf4c0, 0xc88d, 0xf4ff, 0xc88d, 0x21, 0 - .dw 0xf540, 0xc88d, 0xf57f, 0xc88d, 0x21, 0 - .dw 0xf5c0, 0xc88d, 0xf5ff, 0xc88d, 0x21, 0 - .dw 0xf640, 0xc88d, 0xf67f, 0xc88d, 0x21, 0 - .dw 0xf6c0, 0xc88d, 0xf6ff, 0xc88d, 0x21, 0 - .dw 0xf740, 0xc88d, 0xf77f, 0xc88d, 0x21, 0 - .dw 0xf7c0, 0xc88d, 0xf7ff, 0xc88d, 0x21, 0 - .dw 0xf840, 0xc88d, 0xf87f, 0xc88d, 0x21, 0 - .dw 0xf8c0, 0xc88d, 0xf8ff, 0xc88d, 0x21, 0 - .dw 0xf940, 0xc88d, 0xf97f, 0xc88d, 0x21, 0 - .dw 0xf9c0, 0xc88d, 0xffff, 0xc88d, 0x21, 0 - .dw 0x0040, 0xc88e, 0x007f, 0xc88e, 0x21, 0 - .dw 0x00c0, 0xc88e, 0x00ff, 0xc88e, 0x21, 0 - .dw 0x0140, 0xc88e, 0x017f, 0xc88e, 0x21, 0 - .dw 0x01c0, 0xc88e, 0x01ff, 0xc88e, 0x21, 0 - .dw 0x0240, 0xc88e, 0x027f, 0xc88e, 0x21, 0 - .dw 0x02c0, 0xc88e, 0x02ff, 0xc88e, 0x21, 0 - .dw 0x0340, 0xc88e, 0x037f, 0xc88e, 0x21, 0 - .dw 0x03c0, 0xc88e, 0x03ff, 0xc88e, 0x21, 0 - .dw 0x0440, 0xc88e, 0x047f, 0xc88e, 0x21, 0 - .dw 0x04c0, 0xc88e, 0x04ff, 0xc88e, 0x21, 0 - .dw 0x0540, 0xc88e, 0x057f, 0xc88e, 0x21, 0 - .dw 0x05c0, 0xc88e, 0x05ff, 0xc88e, 0x21, 0 - .dw 0x0640, 0xc88e, 0x067f, 0xc88e, 0x21, 0 - .dw 0x06c0, 0xc88e, 0x06ff, 0xc88e, 0x21, 0 - .dw 0x0740, 0xc88e, 0x077f, 0xc88e, 0x21, 0 - .dw 0x07c0, 0xc88e, 0x07ff, 0xc88e, 0x21, 0 - .dw 0x0840, 0xc88e, 0x087f, 0xc88e, 0x21, 0 - .dw 0x08c0, 0xc88e, 0x08ff, 0xc88e, 0x21, 0 - .dw 0x0940, 0xc88e, 0x097f, 0xc88e, 0x21, 0 - .dw 0x09c0, 0xc88e, 0x09ff, 0xc88e, 0x21, 0 - .dw 0x0a40, 0xc88e, 0x0a7f, 0xc88e, 0x21, 0 - .dw 0x0ac0, 0xc88e, 0x0aff, 0xc88e, 0x21, 0 - .dw 0x0b40, 0xc88e, 0x0b7f, 0xc88e, 0x21, 0 - .dw 0x0bc0, 0xc88e, 0x0bff, 0xc88e, 0x21, 0 - .dw 0x0c40, 0xc88e, 0x0c7f, 0xc88e, 0x21, 0 - .dw 0x0cc0, 0xc88e, 0x0cff, 0xc88e, 0x21, 0 - .dw 0x0d40, 0xc88e, 0x0d7f, 0xc88e, 0x21, 0 - .dw 0x0dc0, 0xc88e, 0x0dff, 0xc88e, 0x21, 0 - .dw 0x0e40, 0xc88e, 0x0e7f, 0xc88e, 0x21, 0 - .dw 0x0ec0, 0xc88e, 0x0eff, 0xc88e, 0x21, 0 - .dw 0x0f40, 0xc88e, 0x0f7f, 0xc88e, 0x21, 0 - .dw 0x0fc0, 0xc88e, 0x0fff, 0xc88e, 0x21, 0 - .dw 0x1040, 0xc88e, 0x107f, 0xc88e, 0x21, 0 - .dw 0x10c0, 0xc88e, 0x10ff, 0xc88e, 0x21, 0 - .dw 0x1140, 0xc88e, 0x117f, 0xc88e, 0x21, 0 - .dw 0x11c0, 0xc88e, 0x11ff, 0xc88e, 0x21, 0 - .dw 0x1240, 0xc88e, 0x127f, 0xc88e, 0x21, 0 - .dw 0x12c0, 0xc88e, 0x12ff, 0xc88e, 0x21, 0 - .dw 0x1340, 0xc88e, 0x137f, 0xc88e, 0x21, 0 - .dw 0x13c0, 0xc88e, 0x13ff, 0xc88e, 0x21, 0 - .dw 0x1440, 0xc88e, 0x147f, 0xc88e, 0x21, 0 - .dw 0x14c0, 0xc88e, 0x14ff, 0xc88e, 0x21, 0 - .dw 0x1540, 0xc88e, 0x157f, 0xc88e, 0x21, 0 - .dw 0x15c0, 0xc88e, 0x15ff, 0xc88e, 0x21, 0 - .dw 0x1640, 0xc88e, 0x167f, 0xc88e, 0x21, 0 - .dw 0x16c0, 0xc88e, 0x16ff, 0xc88e, 0x21, 0 - .dw 0x1740, 0xc88e, 0x177f, 0xc88e, 0x21, 0 - .dw 0x17c0, 0xc88e, 0x17ff, 0xc88e, 0x21, 0 - .dw 0x1840, 0xc88e, 0x187f, 0xc88e, 0x21, 0 - .dw 0x18c0, 0xc88e, 0x18ff, 0xc88e, 0x21, 0 - .dw 0x1940, 0xc88e, 0x197f, 0xc88e, 0x21, 0 - .dw 0x19c0, 0xc88e, 0x1fff, 0xc88e, 0x21, 0 - .dw 0x2040, 0xc88e, 0x207f, 0xc88e, 0x21, 0 - .dw 0x20c0, 0xc88e, 0x20ff, 0xc88e, 0x21, 0 - .dw 0x2140, 0xc88e, 0x217f, 0xc88e, 0x21, 0 - .dw 0x21c0, 0xc88e, 0x21ff, 0xc88e, 0x21, 0 - .dw 0x2240, 0xc88e, 0x227f, 0xc88e, 0x21, 0 - .dw 0x22c0, 0xc88e, 0x22ff, 0xc88e, 0x21, 0 - .dw 0x2340, 0xc88e, 0x237f, 0xc88e, 0x21, 0 - .dw 0x23c0, 0xc88e, 0x23ff, 0xc88e, 0x21, 0 - .dw 0x2440, 0xc88e, 0x247f, 0xc88e, 0x21, 0 - .dw 0x24c0, 0xc88e, 0x24ff, 0xc88e, 0x21, 0 - .dw 0x2540, 0xc88e, 0x257f, 0xc88e, 0x21, 0 - .dw 0x25c0, 0xc88e, 0x25ff, 0xc88e, 0x21, 0 - .dw 0x2640, 0xc88e, 0x267f, 0xc88e, 0x21, 0 - .dw 0x26c0, 0xc88e, 0x26ff, 0xc88e, 0x21, 0 - .dw 0x2740, 0xc88e, 0x277f, 0xc88e, 0x21, 0 - .dw 0x27c0, 0xc88e, 0x27ff, 0xc88e, 0x21, 0 - .dw 0x2840, 0xc88e, 0x287f, 0xc88e, 0x21, 0 - .dw 0x28c0, 0xc88e, 0x28ff, 0xc88e, 0x21, 0 - .dw 0x2940, 0xc88e, 0x297f, 0xc88e, 0x21, 0 - .dw 0x29c0, 0xc88e, 0x29ff, 0xc88e, 0x21, 0 - .dw 0x2a40, 0xc88e, 0x2a7f, 0xc88e, 0x21, 0 - .dw 0x2ac0, 0xc88e, 0x2aff, 0xc88e, 0x21, 0 - .dw 0x2b40, 0xc88e, 0x2b7f, 0xc88e, 0x21, 0 - .dw 0x2bc0, 0xc88e, 0x2bff, 0xc88e, 0x21, 0 - .dw 0x2c40, 0xc88e, 0x2c7f, 0xc88e, 0x21, 0 - .dw 0x2cc0, 0xc88e, 0x2cff, 0xc88e, 0x21, 0 - .dw 0x2d40, 0xc88e, 0x2d7f, 0xc88e, 0x21, 0 - .dw 0x2dc0, 0xc88e, 0x2dff, 0xc88e, 0x21, 0 - .dw 0x2e40, 0xc88e, 0x2e7f, 0xc88e, 0x21, 0 - .dw 0x2ec0, 0xc88e, 0x2eff, 0xc88e, 0x21, 0 - .dw 0x2f40, 0xc88e, 0x2f7f, 0xc88e, 0x21, 0 - .dw 0x2fc0, 0xc88e, 0x2fff, 0xc88e, 0x21, 0 - .dw 0x3040, 0xc88e, 0x307f, 0xc88e, 0x21, 0 - .dw 0x30c0, 0xc88e, 0x30ff, 0xc88e, 0x21, 0 - .dw 0x3140, 0xc88e, 0x317f, 0xc88e, 0x21, 0 - .dw 0x31c0, 0xc88e, 0x31ff, 0xc88e, 0x21, 0 - .dw 0x3240, 0xc88e, 0x327f, 0xc88e, 0x21, 0 - .dw 0x32c0, 0xc88e, 0x32ff, 0xc88e, 0x21, 0 - .dw 0x3340, 0xc88e, 0x337f, 0xc88e, 0x21, 0 - .dw 0x33c0, 0xc88e, 0x33ff, 0xc88e, 0x21, 0 - .dw 0x3440, 0xc88e, 0x347f, 0xc88e, 0x21, 0 - .dw 0x34c0, 0xc88e, 0x34ff, 0xc88e, 0x21, 0 - .dw 0x3540, 0xc88e, 0x357f, 0xc88e, 0x21, 0 - .dw 0x35c0, 0xc88e, 0x35ff, 0xc88e, 0x21, 0 - .dw 0x3640, 0xc88e, 0x367f, 0xc88e, 0x21, 0 - .dw 0x36c0, 0xc88e, 0x36ff, 0xc88e, 0x21, 0 - .dw 0x3740, 0xc88e, 0x377f, 0xc88e, 0x21, 0 - .dw 0x37c0, 0xc88e, 0x37ff, 0xc88e, 0x21, 0 - .dw 0x3840, 0xc88e, 0x387f, 0xc88e, 0x21, 0 - .dw 0x38c0, 0xc88e, 0x38ff, 0xc88e, 0x21, 0 - .dw 0x3940, 0xc88e, 0x397f, 0xc88e, 0x21, 0 - .dw 0x39c0, 0xc88e, 0x3fff, 0xc88e, 0x21, 0 - .dw 0x4040, 0xc88e, 0x407f, 0xc88e, 0x21, 0 - .dw 0x40c0, 0xc88e, 0x40ff, 0xc88e, 0x21, 0 - .dw 0x4140, 0xc88e, 0x417f, 0xc88e, 0x21, 0 - .dw 0x41c0, 0xc88e, 0x41ff, 0xc88e, 0x21, 0 - .dw 0x4240, 0xc88e, 0x427f, 0xc88e, 0x21, 0 - .dw 0x42c0, 0xc88e, 0x42ff, 0xc88e, 0x21, 0 - .dw 0x4340, 0xc88e, 0x437f, 0xc88e, 0x21, 0 - .dw 0x43c0, 0xc88e, 0x43ff, 0xc88e, 0x21, 0 - .dw 0x4440, 0xc88e, 0x447f, 0xc88e, 0x21, 0 - .dw 0x44c0, 0xc88e, 0x44ff, 0xc88e, 0x21, 0 - .dw 0x4540, 0xc88e, 0x457f, 0xc88e, 0x21, 0 - .dw 0x45c0, 0xc88e, 0x45ff, 0xc88e, 0x21, 0 - .dw 0x4640, 0xc88e, 0x467f, 0xc88e, 0x21, 0 - .dw 0x46c0, 0xc88e, 0x46ff, 0xc88e, 0x21, 0 - .dw 0x4740, 0xc88e, 0x477f, 0xc88e, 0x21, 0 - .dw 0x47c0, 0xc88e, 0x47ff, 0xc88e, 0x21, 0 - .dw 0x4840, 0xc88e, 0x487f, 0xc88e, 0x21, 0 - .dw 0x48c0, 0xc88e, 0x48ff, 0xc88e, 0x21, 0 - .dw 0x4940, 0xc88e, 0x497f, 0xc88e, 0x21, 0 - .dw 0x49c0, 0xc88e, 0x49ff, 0xc88e, 0x21, 0 - .dw 0x4a40, 0xc88e, 0x4a7f, 0xc88e, 0x21, 0 - .dw 0x4ac0, 0xc88e, 0x4aff, 0xc88e, 0x21, 0 - .dw 0x4b40, 0xc88e, 0x4b7f, 0xc88e, 0x21, 0 - .dw 0x4bc0, 0xc88e, 0x4bff, 0xc88e, 0x21, 0 - .dw 0x4c40, 0xc88e, 0x4c7f, 0xc88e, 0x21, 0 - .dw 0x4cc0, 0xc88e, 0x4cff, 0xc88e, 0x21, 0 - .dw 0x4d40, 0xc88e, 0x4d7f, 0xc88e, 0x21, 0 - .dw 0x4dc0, 0xc88e, 0x4dff, 0xc88e, 0x21, 0 - .dw 0x4e40, 0xc88e, 0x4e7f, 0xc88e, 0x21, 0 - .dw 0x4ec0, 0xc88e, 0x4eff, 0xc88e, 0x21, 0 - .dw 0x4f40, 0xc88e, 0x4f7f, 0xc88e, 0x21, 0 - .dw 0x4fc0, 0xc88e, 0x4fff, 0xc88e, 0x21, 0 - .dw 0x5040, 0xc88e, 0x507f, 0xc88e, 0x21, 0 - .dw 0x50c0, 0xc88e, 0x50ff, 0xc88e, 0x21, 0 - .dw 0x5140, 0xc88e, 0x517f, 0xc88e, 0x21, 0 - .dw 0x51c0, 0xc88e, 0x51ff, 0xc88e, 0x21, 0 - .dw 0x5240, 0xc88e, 0x527f, 0xc88e, 0x21, 0 - .dw 0x52c0, 0xc88e, 0x52ff, 0xc88e, 0x21, 0 - .dw 0x5340, 0xc88e, 0x537f, 0xc88e, 0x21, 0 - .dw 0x53c0, 0xc88e, 0x53ff, 0xc88e, 0x21, 0 - .dw 0x5440, 0xc88e, 0x547f, 0xc88e, 0x21, 0 - .dw 0x54c0, 0xc88e, 0x54ff, 0xc88e, 0x21, 0 - .dw 0x5540, 0xc88e, 0x557f, 0xc88e, 0x21, 0 - .dw 0x55c0, 0xc88e, 0x55ff, 0xc88e, 0x21, 0 - .dw 0x5640, 0xc88e, 0x567f, 0xc88e, 0x21, 0 - .dw 0x56c0, 0xc88e, 0x56ff, 0xc88e, 0x21, 0 - .dw 0x5740, 0xc88e, 0x577f, 0xc88e, 0x21, 0 - .dw 0x57c0, 0xc88e, 0x57ff, 0xc88e, 0x21, 0 - .dw 0x5840, 0xc88e, 0x587f, 0xc88e, 0x21, 0 - .dw 0x58c0, 0xc88e, 0x58ff, 0xc88e, 0x21, 0 - .dw 0x5940, 0xc88e, 0x597f, 0xc88e, 0x21, 0 - .dw 0x59c0, 0xc88e, 0x5fff, 0xc88e, 0x21, 0 - .dw 0x6040, 0xc88e, 0x607f, 0xc88e, 0x21, 0 - .dw 0x60c0, 0xc88e, 0x60ff, 0xc88e, 0x21, 0 - .dw 0x6140, 0xc88e, 0x617f, 0xc88e, 0x21, 0 - .dw 0x61c0, 0xc88e, 0x61ff, 0xc88e, 0x21, 0 - .dw 0x6240, 0xc88e, 0x627f, 0xc88e, 0x21, 0 - .dw 0x62c0, 0xc88e, 0x62ff, 0xc88e, 0x21, 0 - .dw 0x6340, 0xc88e, 0x637f, 0xc88e, 0x21, 0 - .dw 0x63c0, 0xc88e, 0x63ff, 0xc88e, 0x21, 0 - .dw 0x6440, 0xc88e, 0x647f, 0xc88e, 0x21, 0 - .dw 0x64c0, 0xc88e, 0x64ff, 0xc88e, 0x21, 0 - .dw 0x6540, 0xc88e, 0x657f, 0xc88e, 0x21, 0 - .dw 0x65c0, 0xc88e, 0x65ff, 0xc88e, 0x21, 0 - .dw 0x6640, 0xc88e, 0x667f, 0xc88e, 0x21, 0 - .dw 0x66c0, 0xc88e, 0x66ff, 0xc88e, 0x21, 0 - .dw 0x6740, 0xc88e, 0x677f, 0xc88e, 0x21, 0 - .dw 0x67c0, 0xc88e, 0x67ff, 0xc88e, 0x21, 0 - .dw 0x6840, 0xc88e, 0x687f, 0xc88e, 0x21, 0 - .dw 0x68c0, 0xc88e, 0x68ff, 0xc88e, 0x21, 0 - .dw 0x6940, 0xc88e, 0x697f, 0xc88e, 0x21, 0 - .dw 0x69c0, 0xc88e, 0x69ff, 0xc88e, 0x21, 0 - .dw 0x6a40, 0xc88e, 0x6a7f, 0xc88e, 0x21, 0 - .dw 0x6ac0, 0xc88e, 0x6aff, 0xc88e, 0x21, 0 - .dw 0x6b40, 0xc88e, 0x6b7f, 0xc88e, 0x21, 0 - .dw 0x6bc0, 0xc88e, 0x6bff, 0xc88e, 0x21, 0 - .dw 0x6c40, 0xc88e, 0x6c7f, 0xc88e, 0x21, 0 - .dw 0x6cc0, 0xc88e, 0x6cff, 0xc88e, 0x21, 0 - .dw 0x6d40, 0xc88e, 0x6d7f, 0xc88e, 0x21, 0 - .dw 0x6dc0, 0xc88e, 0x6dff, 0xc88e, 0x21, 0 - .dw 0x6e40, 0xc88e, 0x6e7f, 0xc88e, 0x21, 0 - .dw 0x6ec0, 0xc88e, 0x6eff, 0xc88e, 0x21, 0 - .dw 0x6f40, 0xc88e, 0x6f7f, 0xc88e, 0x21, 0 - .dw 0x6fc0, 0xc88e, 0x6fff, 0xc88e, 0x21, 0 - .dw 0x7040, 0xc88e, 0x707f, 0xc88e, 0x21, 0 - .dw 0x70c0, 0xc88e, 0x70ff, 0xc88e, 0x21, 0 - .dw 0x7140, 0xc88e, 0x717f, 0xc88e, 0x21, 0 - .dw 0x71c0, 0xc88e, 0x71ff, 0xc88e, 0x21, 0 - .dw 0x7240, 0xc88e, 0x727f, 0xc88e, 0x21, 0 - .dw 0x72c0, 0xc88e, 0x72ff, 0xc88e, 0x21, 0 - .dw 0x7340, 0xc88e, 0x737f, 0xc88e, 0x21, 0 - .dw 0x73c0, 0xc88e, 0x73ff, 0xc88e, 0x21, 0 - .dw 0x7440, 0xc88e, 0x747f, 0xc88e, 0x21, 0 - .dw 0x74c0, 0xc88e, 0x74ff, 0xc88e, 0x21, 0 - .dw 0x7540, 0xc88e, 0x757f, 0xc88e, 0x21, 0 - .dw 0x75c0, 0xc88e, 0x75ff, 0xc88e, 0x21, 0 - .dw 0x7640, 0xc88e, 0x767f, 0xc88e, 0x21, 0 - .dw 0x76c0, 0xc88e, 0x76ff, 0xc88e, 0x21, 0 - .dw 0x7740, 0xc88e, 0x777f, 0xc88e, 0x21, 0 - .dw 0x77c0, 0xc88e, 0x77ff, 0xc88e, 0x21, 0 - .dw 0x7840, 0xc88e, 0x787f, 0xc88e, 0x21, 0 - .dw 0x78c0, 0xc88e, 0x78ff, 0xc88e, 0x21, 0 - .dw 0x7940, 0xc88e, 0x797f, 0xc88e, 0x21, 0 - .dw 0x79c0, 0xc88e, 0x7fff, 0xc88e, 0x21, 0 - .dw 0x8040, 0xc88e, 0x807f, 0xc88e, 0x21, 0 - .dw 0x80c0, 0xc88e, 0x80ff, 0xc88e, 0x21, 0 - .dw 0x8140, 0xc88e, 0x817f, 0xc88e, 0x21, 0 - .dw 0x81c0, 0xc88e, 0x81ff, 0xc88e, 0x21, 0 - .dw 0x8240, 0xc88e, 0x827f, 0xc88e, 0x21, 0 - .dw 0x82c0, 0xc88e, 0x82ff, 0xc88e, 0x21, 0 - .dw 0x8340, 0xc88e, 0x837f, 0xc88e, 0x21, 0 - .dw 0x83c0, 0xc88e, 0x83ff, 0xc88e, 0x21, 0 - .dw 0x8440, 0xc88e, 0x847f, 0xc88e, 0x21, 0 - .dw 0x84c0, 0xc88e, 0x84ff, 0xc88e, 0x21, 0 - .dw 0x8540, 0xc88e, 0x857f, 0xc88e, 0x21, 0 - .dw 0x85c0, 0xc88e, 0x85ff, 0xc88e, 0x21, 0 - .dw 0x8640, 0xc88e, 0x867f, 0xc88e, 0x21, 0 - .dw 0x86c0, 0xc88e, 0x86ff, 0xc88e, 0x21, 0 - .dw 0x8740, 0xc88e, 0x877f, 0xc88e, 0x21, 0 - .dw 0x87c0, 0xc88e, 0x87ff, 0xc88e, 0x21, 0 - .dw 0x8840, 0xc88e, 0x887f, 0xc88e, 0x21, 0 - .dw 0x88c0, 0xc88e, 0x88ff, 0xc88e, 0x21, 0 - .dw 0x8940, 0xc88e, 0x897f, 0xc88e, 0x21, 0 - .dw 0x89c0, 0xc88e, 0x89ff, 0xc88e, 0x21, 0 - .dw 0x8a40, 0xc88e, 0x8a7f, 0xc88e, 0x21, 0 - .dw 0x8ac0, 0xc88e, 0x8aff, 0xc88e, 0x21, 0 - .dw 0x8b40, 0xc88e, 0x8b7f, 0xc88e, 0x21, 0 - .dw 0x8bc0, 0xc88e, 0x8bff, 0xc88e, 0x21, 0 - .dw 0x8c40, 0xc88e, 0x8c7f, 0xc88e, 0x21, 0 - .dw 0x8cc0, 0xc88e, 0x8cff, 0xc88e, 0x21, 0 - .dw 0x8d40, 0xc88e, 0x8d7f, 0xc88e, 0x21, 0 - .dw 0x8dc0, 0xc88e, 0x8dff, 0xc88e, 0x21, 0 - .dw 0x8e40, 0xc88e, 0x8e7f, 0xc88e, 0x21, 0 - .dw 0x8ec0, 0xc88e, 0x8eff, 0xc88e, 0x21, 0 - .dw 0x8f40, 0xc88e, 0x8f7f, 0xc88e, 0x21, 0 - .dw 0x8fc0, 0xc88e, 0x8fff, 0xc88e, 0x21, 0 - .dw 0x9040, 0xc88e, 0x907f, 0xc88e, 0x21, 0 - .dw 0x90c0, 0xc88e, 0x90ff, 0xc88e, 0x21, 0 - .dw 0x9140, 0xc88e, 0x917f, 0xc88e, 0x21, 0 - .dw 0x91c0, 0xc88e, 0x91ff, 0xc88e, 0x21, 0 - .dw 0x9240, 0xc88e, 0x927f, 0xc88e, 0x21, 0 - .dw 0x92c0, 0xc88e, 0x92ff, 0xc88e, 0x21, 0 - .dw 0x9340, 0xc88e, 0x937f, 0xc88e, 0x21, 0 - .dw 0x93c0, 0xc88e, 0x93ff, 0xc88e, 0x21, 0 - .dw 0x9440, 0xc88e, 0x947f, 0xc88e, 0x21, 0 - .dw 0x94c0, 0xc88e, 0x94ff, 0xc88e, 0x21, 0 - .dw 0x9540, 0xc88e, 0x957f, 0xc88e, 0x21, 0 - .dw 0x95c0, 0xc88e, 0x95ff, 0xc88e, 0x21, 0 - .dw 0x9640, 0xc88e, 0x967f, 0xc88e, 0x21, 0 - .dw 0x96c0, 0xc88e, 0x96ff, 0xc88e, 0x21, 0 - .dw 0x9740, 0xc88e, 0x977f, 0xc88e, 0x21, 0 - .dw 0x97c0, 0xc88e, 0x97ff, 0xc88e, 0x21, 0 - .dw 0x9840, 0xc88e, 0x987f, 0xc88e, 0x21, 0 - .dw 0x98c0, 0xc88e, 0x98ff, 0xc88e, 0x21, 0 - .dw 0x9940, 0xc88e, 0x997f, 0xc88e, 0x21, 0 - .dw 0x99c0, 0xc88e, 0x9fff, 0xc88e, 0x21, 0 - .dw 0xa040, 0xc88e, 0xa07f, 0xc88e, 0x21, 0 - .dw 0xa0c0, 0xc88e, 0xa0ff, 0xc88e, 0x21, 0 - .dw 0xa140, 0xc88e, 0xa17f, 0xc88e, 0x21, 0 - .dw 0xa1c0, 0xc88e, 0xa1ff, 0xc88e, 0x21, 0 - .dw 0xa240, 0xc88e, 0xa27f, 0xc88e, 0x21, 0 - .dw 0xa2c0, 0xc88e, 0xa2ff, 0xc88e, 0x21, 0 - .dw 0xa340, 0xc88e, 0xa37f, 0xc88e, 0x21, 0 - .dw 0xa3c0, 0xc88e, 0xa3ff, 0xc88e, 0x21, 0 - .dw 0xa440, 0xc88e, 0xa47f, 0xc88e, 0x21, 0 - .dw 0xa4c0, 0xc88e, 0xa4ff, 0xc88e, 0x21, 0 - .dw 0xa540, 0xc88e, 0xa57f, 0xc88e, 0x21, 0 - .dw 0xa5c0, 0xc88e, 0xa5ff, 0xc88e, 0x21, 0 - .dw 0xa640, 0xc88e, 0xa67f, 0xc88e, 0x21, 0 - .dw 0xa6c0, 0xc88e, 0xa6ff, 0xc88e, 0x21, 0 - .dw 0xa740, 0xc88e, 0xa77f, 0xc88e, 0x21, 0 - .dw 0xa7c0, 0xc88e, 0xa7ff, 0xc88e, 0x21, 0 - .dw 0xa840, 0xc88e, 0xa87f, 0xc88e, 0x21, 0 - .dw 0xa8c0, 0xc88e, 0xa8ff, 0xc88e, 0x21, 0 - .dw 0xa940, 0xc88e, 0xa97f, 0xc88e, 0x21, 0 - .dw 0xa9c0, 0xc88e, 0xa9ff, 0xc88e, 0x21, 0 - .dw 0xaa40, 0xc88e, 0xaa7f, 0xc88e, 0x21, 0 - .dw 0xaac0, 0xc88e, 0xaaff, 0xc88e, 0x21, 0 - .dw 0xab40, 0xc88e, 0xab7f, 0xc88e, 0x21, 0 - .dw 0xabc0, 0xc88e, 0xabff, 0xc88e, 0x21, 0 - .dw 0xac40, 0xc88e, 0xac7f, 0xc88e, 0x21, 0 - .dw 0xacc0, 0xc88e, 0xacff, 0xc88e, 0x21, 0 - .dw 0xad40, 0xc88e, 0xad7f, 0xc88e, 0x21, 0 - .dw 0xadc0, 0xc88e, 0xadff, 0xc88e, 0x21, 0 - .dw 0xae40, 0xc88e, 0xae7f, 0xc88e, 0x21, 0 - .dw 0xaec0, 0xc88e, 0xaeff, 0xc88e, 0x21, 0 - .dw 0xaf40, 0xc88e, 0xaf7f, 0xc88e, 0x21, 0 - .dw 0xafc0, 0xc88e, 0xafff, 0xc88e, 0x21, 0 - .dw 0xb040, 0xc88e, 0xb07f, 0xc88e, 0x21, 0 - .dw 0xb0c0, 0xc88e, 0xb0ff, 0xc88e, 0x21, 0 - .dw 0xb140, 0xc88e, 0xb17f, 0xc88e, 0x21, 0 - .dw 0xb1c0, 0xc88e, 0xb1ff, 0xc88e, 0x21, 0 - .dw 0xb240, 0xc88e, 0xb27f, 0xc88e, 0x21, 0 - .dw 0xb2c0, 0xc88e, 0xb2ff, 0xc88e, 0x21, 0 - .dw 0xb340, 0xc88e, 0xb37f, 0xc88e, 0x21, 0 - .dw 0xb3c0, 0xc88e, 0xb3ff, 0xc88e, 0x21, 0 - .dw 0xb440, 0xc88e, 0xb47f, 0xc88e, 0x21, 0 - .dw 0xb4c0, 0xc88e, 0xb4ff, 0xc88e, 0x21, 0 - .dw 0xb540, 0xc88e, 0xb57f, 0xc88e, 0x21, 0 - .dw 0xb5c0, 0xc88e, 0xb5ff, 0xc88e, 0x21, 0 - .dw 0xb640, 0xc88e, 0xb67f, 0xc88e, 0x21, 0 - .dw 0xb6c0, 0xc88e, 0xb6ff, 0xc88e, 0x21, 0 - .dw 0xb740, 0xc88e, 0xb77f, 0xc88e, 0x21, 0 - .dw 0xb7c0, 0xc88e, 0xb7ff, 0xc88e, 0x21, 0 - .dw 0xb840, 0xc88e, 0xb87f, 0xc88e, 0x21, 0 - .dw 0xb8c0, 0xc88e, 0xb8ff, 0xc88e, 0x21, 0 - .dw 0xb940, 0xc88e, 0xb97f, 0xc88e, 0x21, 0 - .dw 0xb9c0, 0xc88e, 0xbfff, 0xc88e, 0x21, 0 - .dw 0xc040, 0xc88e, 0xc07f, 0xc88e, 0x21, 0 - .dw 0xc0c0, 0xc88e, 0xc0ff, 0xc88e, 0x21, 0 - .dw 0xc140, 0xc88e, 0xc17f, 0xc88e, 0x21, 0 - .dw 0xc1c0, 0xc88e, 0xc1ff, 0xc88e, 0x21, 0 - .dw 0xc240, 0xc88e, 0xc27f, 0xc88e, 0x21, 0 - .dw 0xc2c0, 0xc88e, 0xc2ff, 0xc88e, 0x21, 0 - .dw 0xc340, 0xc88e, 0xc37f, 0xc88e, 0x21, 0 - .dw 0xc3c0, 0xc88e, 0xc3ff, 0xc88e, 0x21, 0 - .dw 0xc440, 0xc88e, 0xc47f, 0xc88e, 0x21, 0 - .dw 0xc4c0, 0xc88e, 0xc4ff, 0xc88e, 0x21, 0 - .dw 0xc540, 0xc88e, 0xc57f, 0xc88e, 0x21, 0 - .dw 0xc5c0, 0xc88e, 0xc5ff, 0xc88e, 0x21, 0 - .dw 0xc640, 0xc88e, 0xc67f, 0xc88e, 0x21, 0 - .dw 0xc6c0, 0xc88e, 0xc6ff, 0xc88e, 0x21, 0 - .dw 0xc740, 0xc88e, 0xc77f, 0xc88e, 0x21, 0 - .dw 0xc7c0, 0xc88e, 0xc7ff, 0xc88e, 0x21, 0 - .dw 0xc840, 0xc88e, 0xc87f, 0xc88e, 0x21, 0 - .dw 0xc8c0, 0xc88e, 0xc8ff, 0xc88e, 0x21, 0 - .dw 0xc940, 0xc88e, 0xc97f, 0xc88e, 0x21, 0 - .dw 0xc9c0, 0xc88e, 0xc9ff, 0xc88e, 0x21, 0 - .dw 0xca40, 0xc88e, 0xca7f, 0xc88e, 0x21, 0 - .dw 0xcac0, 0xc88e, 0xcaff, 0xc88e, 0x21, 0 - .dw 0xcb40, 0xc88e, 0xcb7f, 0xc88e, 0x21, 0 - .dw 0xcbc0, 0xc88e, 0xcbff, 0xc88e, 0x21, 0 - .dw 0xcc40, 0xc88e, 0xcc7f, 0xc88e, 0x21, 0 - .dw 0xccc0, 0xc88e, 0xccff, 0xc88e, 0x21, 0 - .dw 0xcd40, 0xc88e, 0xcd7f, 0xc88e, 0x21, 0 - .dw 0xcdc0, 0xc88e, 0xcdff, 0xc88e, 0x21, 0 - .dw 0xce40, 0xc88e, 0xce7f, 0xc88e, 0x21, 0 - .dw 0xcec0, 0xc88e, 0xceff, 0xc88e, 0x21, 0 - .dw 0xcf40, 0xc88e, 0xcf7f, 0xc88e, 0x21, 0 - .dw 0xcfc0, 0xc88e, 0xcfff, 0xc88e, 0x21, 0 - .dw 0xd040, 0xc88e, 0xd07f, 0xc88e, 0x21, 0 - .dw 0xd0c0, 0xc88e, 0xd0ff, 0xc88e, 0x21, 0 - .dw 0xd140, 0xc88e, 0xd17f, 0xc88e, 0x21, 0 - .dw 0xd1c0, 0xc88e, 0xd1ff, 0xc88e, 0x21, 0 - .dw 0xd240, 0xc88e, 0xd27f, 0xc88e, 0x21, 0 - .dw 0xd2c0, 0xc88e, 0xd2ff, 0xc88e, 0x21, 0 - .dw 0xd340, 0xc88e, 0xd37f, 0xc88e, 0x21, 0 - .dw 0xd3c0, 0xc88e, 0xd3ff, 0xc88e, 0x21, 0 - .dw 0xd440, 0xc88e, 0xd47f, 0xc88e, 0x21, 0 - .dw 0xd4c0, 0xc88e, 0xd4ff, 0xc88e, 0x21, 0 - .dw 0xd540, 0xc88e, 0xd57f, 0xc88e, 0x21, 0 - .dw 0xd5c0, 0xc88e, 0xd5ff, 0xc88e, 0x21, 0 - .dw 0xd640, 0xc88e, 0xd67f, 0xc88e, 0x21, 0 - .dw 0xd6c0, 0xc88e, 0xd6ff, 0xc88e, 0x21, 0 - .dw 0xd740, 0xc88e, 0xd77f, 0xc88e, 0x21, 0 - .dw 0xd7c0, 0xc88e, 0xd7ff, 0xc88e, 0x21, 0 - .dw 0xd840, 0xc88e, 0xd87f, 0xc88e, 0x21, 0 - .dw 0xd8c0, 0xc88e, 0xd8ff, 0xc88e, 0x21, 0 - .dw 0xd940, 0xc88e, 0xd97f, 0xc88e, 0x21, 0 - .dw 0xd9c0, 0xc88e, 0xdfff, 0xc88e, 0x21, 0 - .dw 0xe040, 0xc88e, 0xe07f, 0xc88e, 0x21, 0 - .dw 0xe0c0, 0xc88e, 0xe0ff, 0xc88e, 0x21, 0 - .dw 0xe140, 0xc88e, 0xe17f, 0xc88e, 0x21, 0 - .dw 0xe1c0, 0xc88e, 0xe1ff, 0xc88e, 0x21, 0 - .dw 0xe240, 0xc88e, 0xe27f, 0xc88e, 0x21, 0 - .dw 0xe2c0, 0xc88e, 0xe2ff, 0xc88e, 0x21, 0 - .dw 0xe340, 0xc88e, 0xe37f, 0xc88e, 0x21, 0 - .dw 0xe3c0, 0xc88e, 0xe3ff, 0xc88e, 0x21, 0 - .dw 0xe440, 0xc88e, 0xe47f, 0xc88e, 0x21, 0 - .dw 0xe4c0, 0xc88e, 0xe4ff, 0xc88e, 0x21, 0 - .dw 0xe540, 0xc88e, 0xe57f, 0xc88e, 0x21, 0 - .dw 0xe5c0, 0xc88e, 0xe5ff, 0xc88e, 0x21, 0 - .dw 0xe640, 0xc88e, 0xe67f, 0xc88e, 0x21, 0 - .dw 0xe6c0, 0xc88e, 0xe6ff, 0xc88e, 0x21, 0 - .dw 0xe740, 0xc88e, 0xe77f, 0xc88e, 0x21, 0 - .dw 0xe7c0, 0xc88e, 0xe7ff, 0xc88e, 0x21, 0 - .dw 0xe840, 0xc88e, 0xe87f, 0xc88e, 0x21, 0 - .dw 0xe8c0, 0xc88e, 0xe8ff, 0xc88e, 0x21, 0 - .dw 0xe940, 0xc88e, 0xe97f, 0xc88e, 0x21, 0 - .dw 0xe9c0, 0xc88e, 0xe9ff, 0xc88e, 0x21, 0 - .dw 0xea40, 0xc88e, 0xea7f, 0xc88e, 0x21, 0 - .dw 0xeac0, 0xc88e, 0xeaff, 0xc88e, 0x21, 0 - .dw 0xeb40, 0xc88e, 0xeb7f, 0xc88e, 0x21, 0 - .dw 0xebc0, 0xc88e, 0xebff, 0xc88e, 0x21, 0 - .dw 0xec40, 0xc88e, 0xec7f, 0xc88e, 0x21, 0 - .dw 0xecc0, 0xc88e, 0xecff, 0xc88e, 0x21, 0 - .dw 0xed40, 0xc88e, 0xed7f, 0xc88e, 0x21, 0 - .dw 0xedc0, 0xc88e, 0xedff, 0xc88e, 0x21, 0 - .dw 0xee40, 0xc88e, 0xee7f, 0xc88e, 0x21, 0 - .dw 0xeec0, 0xc88e, 0xeeff, 0xc88e, 0x21, 0 - .dw 0xef40, 0xc88e, 0xef7f, 0xc88e, 0x21, 0 - .dw 0xefc0, 0xc88e, 0xefff, 0xc88e, 0x21, 0 - .dw 0xf040, 0xc88e, 0xf07f, 0xc88e, 0x21, 0 - .dw 0xf0c0, 0xc88e, 0xf0ff, 0xc88e, 0x21, 0 - .dw 0xf140, 0xc88e, 0xf17f, 0xc88e, 0x21, 0 - .dw 0xf1c0, 0xc88e, 0xf1ff, 0xc88e, 0x21, 0 - .dw 0xf240, 0xc88e, 0xf27f, 0xc88e, 0x21, 0 - .dw 0xf2c0, 0xc88e, 0xf2ff, 0xc88e, 0x21, 0 - .dw 0xf340, 0xc88e, 0xf37f, 0xc88e, 0x21, 0 - .dw 0xf3c0, 0xc88e, 0xf3ff, 0xc88e, 0x21, 0 - .dw 0xf440, 0xc88e, 0xf47f, 0xc88e, 0x21, 0 - .dw 0xf4c0, 0xc88e, 0xf4ff, 0xc88e, 0x21, 0 - .dw 0xf540, 0xc88e, 0xf57f, 0xc88e, 0x21, 0 - .dw 0xf5c0, 0xc88e, 0xf5ff, 0xc88e, 0x21, 0 - .dw 0xf640, 0xc88e, 0xf67f, 0xc88e, 0x21, 0 - .dw 0xf6c0, 0xc88e, 0xf6ff, 0xc88e, 0x21, 0 - .dw 0xf740, 0xc88e, 0xf77f, 0xc88e, 0x21, 0 - .dw 0xf7c0, 0xc88e, 0xf7ff, 0xc88e, 0x21, 0 - .dw 0xf840, 0xc88e, 0xf87f, 0xc88e, 0x21, 0 - .dw 0xf8c0, 0xc88e, 0xf8ff, 0xc88e, 0x21, 0 - .dw 0xf940, 0xc88e, 0xf97f, 0xc88e, 0x21, 0 - .dw 0xf9c0, 0xc88e, 0xffff, 0xc88e, 0x21, 0 - .dw 0x0040, 0xc88f, 0x007f, 0xc88f, 0x21, 0 - .dw 0x00c0, 0xc88f, 0x00ff, 0xc88f, 0x21, 0 - .dw 0x0140, 0xc88f, 0x017f, 0xc88f, 0x21, 0 - .dw 0x01c0, 0xc88f, 0x01ff, 0xc88f, 0x21, 0 - .dw 0x0240, 0xc88f, 0x027f, 0xc88f, 0x21, 0 - .dw 0x02c0, 0xc88f, 0x02ff, 0xc88f, 0x21, 0 - .dw 0x0340, 0xc88f, 0x037f, 0xc88f, 0x21, 0 - .dw 0x03c0, 0xc88f, 0x03ff, 0xc88f, 0x21, 0 - .dw 0x0440, 0xc88f, 0x047f, 0xc88f, 0x21, 0 - .dw 0x04c0, 0xc88f, 0x04ff, 0xc88f, 0x21, 0 - .dw 0x0540, 0xc88f, 0x057f, 0xc88f, 0x21, 0 - .dw 0x05c0, 0xc88f, 0x05ff, 0xc88f, 0x21, 0 - .dw 0x0640, 0xc88f, 0x067f, 0xc88f, 0x21, 0 - .dw 0x06c0, 0xc88f, 0x06ff, 0xc88f, 0x21, 0 - .dw 0x0740, 0xc88f, 0x077f, 0xc88f, 0x21, 0 - .dw 0x07c0, 0xc88f, 0x07ff, 0xc88f, 0x21, 0 - .dw 0x0840, 0xc88f, 0x087f, 0xc88f, 0x21, 0 - .dw 0x08c0, 0xc88f, 0x08ff, 0xc88f, 0x21, 0 - .dw 0x0940, 0xc88f, 0x097f, 0xc88f, 0x21, 0 - .dw 0x09c0, 0xc88f, 0x09ff, 0xc88f, 0x21, 0 - .dw 0x0a40, 0xc88f, 0x0a7f, 0xc88f, 0x21, 0 - .dw 0x0ac0, 0xc88f, 0x0aff, 0xc88f, 0x21, 0 - .dw 0x0b40, 0xc88f, 0x0b7f, 0xc88f, 0x21, 0 - .dw 0x0bc0, 0xc88f, 0x0bff, 0xc88f, 0x21, 0 - .dw 0x0c40, 0xc88f, 0x0c7f, 0xc88f, 0x21, 0 - .dw 0x0cc0, 0xc88f, 0x0cff, 0xc88f, 0x21, 0 - .dw 0x0d40, 0xc88f, 0x0d7f, 0xc88f, 0x21, 0 - .dw 0x0dc0, 0xc88f, 0x0dff, 0xc88f, 0x21, 0 - .dw 0x0e40, 0xc88f, 0x0e7f, 0xc88f, 0x21, 0 - .dw 0x0ec0, 0xc88f, 0x0eff, 0xc88f, 0x21, 0 - .dw 0x0f40, 0xc88f, 0x0f7f, 0xc88f, 0x21, 0 - .dw 0x0fc0, 0xc88f, 0x0fff, 0xc88f, 0x21, 0 - .dw 0x1040, 0xc88f, 0x107f, 0xc88f, 0x21, 0 - .dw 0x10c0, 0xc88f, 0x10ff, 0xc88f, 0x21, 0 - .dw 0x1140, 0xc88f, 0x117f, 0xc88f, 0x21, 0 - .dw 0x11c0, 0xc88f, 0x11ff, 0xc88f, 0x21, 0 - .dw 0x1240, 0xc88f, 0x127f, 0xc88f, 0x21, 0 - .dw 0x12c0, 0xc88f, 0x12ff, 0xc88f, 0x21, 0 - .dw 0x1340, 0xc88f, 0x137f, 0xc88f, 0x21, 0 - .dw 0x13c0, 0xc88f, 0x13ff, 0xc88f, 0x21, 0 - .dw 0x1440, 0xc88f, 0x147f, 0xc88f, 0x21, 0 - .dw 0x14c0, 0xc88f, 0x14ff, 0xc88f, 0x21, 0 - .dw 0x1540, 0xc88f, 0x157f, 0xc88f, 0x21, 0 - .dw 0x15c0, 0xc88f, 0x15ff, 0xc88f, 0x21, 0 - .dw 0x1640, 0xc88f, 0x167f, 0xc88f, 0x21, 0 - .dw 0x16c0, 0xc88f, 0x16ff, 0xc88f, 0x21, 0 - .dw 0x1740, 0xc88f, 0x177f, 0xc88f, 0x21, 0 - .dw 0x17c0, 0xc88f, 0x17ff, 0xc88f, 0x21, 0 - .dw 0x1840, 0xc88f, 0x187f, 0xc88f, 0x21, 0 - .dw 0x18c0, 0xc88f, 0x18ff, 0xc88f, 0x21, 0 - .dw 0x1940, 0xc88f, 0x197f, 0xc88f, 0x21, 0 - .dw 0x19c0, 0xc88f, 0x1fff, 0xc88f, 0x21, 0 - .dw 0x2040, 0xc88f, 0x207f, 0xc88f, 0x21, 0 - .dw 0x20c0, 0xc88f, 0x20ff, 0xc88f, 0x21, 0 - .dw 0x2140, 0xc88f, 0x217f, 0xc88f, 0x21, 0 - .dw 0x21c0, 0xc88f, 0x21ff, 0xc88f, 0x21, 0 - .dw 0x2240, 0xc88f, 0x227f, 0xc88f, 0x21, 0 - .dw 0x22c0, 0xc88f, 0x22ff, 0xc88f, 0x21, 0 - .dw 0x2340, 0xc88f, 0x237f, 0xc88f, 0x21, 0 - .dw 0x23c0, 0xc88f, 0x23ff, 0xc88f, 0x21, 0 - .dw 0x2440, 0xc88f, 0x247f, 0xc88f, 0x21, 0 - .dw 0x24c0, 0xc88f, 0x24ff, 0xc88f, 0x21, 0 - .dw 0x2540, 0xc88f, 0x257f, 0xc88f, 0x21, 0 - .dw 0x25c0, 0xc88f, 0x25ff, 0xc88f, 0x21, 0 - .dw 0x2640, 0xc88f, 0x267f, 0xc88f, 0x21, 0 - .dw 0x26c0, 0xc88f, 0x26ff, 0xc88f, 0x21, 0 - .dw 0x2740, 0xc88f, 0x277f, 0xc88f, 0x21, 0 - .dw 0x27c0, 0xc88f, 0x27ff, 0xc88f, 0x21, 0 - .dw 0x2840, 0xc88f, 0x287f, 0xc88f, 0x21, 0 - .dw 0x28c0, 0xc88f, 0x28ff, 0xc88f, 0x21, 0 - .dw 0x2940, 0xc88f, 0x297f, 0xc88f, 0x21, 0 - .dw 0x29c0, 0xc88f, 0x29ff, 0xc88f, 0x21, 0 - .dw 0x2a40, 0xc88f, 0x2a7f, 0xc88f, 0x21, 0 - .dw 0x2ac0, 0xc88f, 0x2aff, 0xc88f, 0x21, 0 - .dw 0x2b40, 0xc88f, 0x2b7f, 0xc88f, 0x21, 0 - .dw 0x2bc0, 0xc88f, 0x2bff, 0xc88f, 0x21, 0 - .dw 0x2c40, 0xc88f, 0x2c7f, 0xc88f, 0x21, 0 - .dw 0x2cc0, 0xc88f, 0x2cff, 0xc88f, 0x21, 0 - .dw 0x2d40, 0xc88f, 0x2d7f, 0xc88f, 0x21, 0 - .dw 0x2dc0, 0xc88f, 0x2dff, 0xc88f, 0x21, 0 - .dw 0x2e40, 0xc88f, 0x2e7f, 0xc88f, 0x21, 0 - .dw 0x2ec0, 0xc88f, 0x2eff, 0xc88f, 0x21, 0 - .dw 0x2f40, 0xc88f, 0x2f7f, 0xc88f, 0x21, 0 - .dw 0x2fc0, 0xc88f, 0x2fff, 0xc88f, 0x21, 0 - .dw 0x3040, 0xc88f, 0x307f, 0xc88f, 0x21, 0 - .dw 0x30c0, 0xc88f, 0x30ff, 0xc88f, 0x21, 0 - .dw 0x3140, 0xc88f, 0x317f, 0xc88f, 0x21, 0 - .dw 0x31c0, 0xc88f, 0x31ff, 0xc88f, 0x21, 0 - .dw 0x3240, 0xc88f, 0x327f, 0xc88f, 0x21, 0 - .dw 0x32c0, 0xc88f, 0x32ff, 0xc88f, 0x21, 0 - .dw 0x3340, 0xc88f, 0x337f, 0xc88f, 0x21, 0 - .dw 0x33c0, 0xc88f, 0x33ff, 0xc88f, 0x21, 0 - .dw 0x3440, 0xc88f, 0x347f, 0xc88f, 0x21, 0 - .dw 0x34c0, 0xc88f, 0x34ff, 0xc88f, 0x21, 0 - .dw 0x3540, 0xc88f, 0x357f, 0xc88f, 0x21, 0 - .dw 0x35c0, 0xc88f, 0x35ff, 0xc88f, 0x21, 0 - .dw 0x3640, 0xc88f, 0x367f, 0xc88f, 0x21, 0 - .dw 0x36c0, 0xc88f, 0x36ff, 0xc88f, 0x21, 0 - .dw 0x3740, 0xc88f, 0x377f, 0xc88f, 0x21, 0 - .dw 0x37c0, 0xc88f, 0x37ff, 0xc88f, 0x21, 0 - .dw 0x3840, 0xc88f, 0x387f, 0xc88f, 0x21, 0 - .dw 0x38c0, 0xc88f, 0x38ff, 0xc88f, 0x21, 0 - .dw 0x3940, 0xc88f, 0x397f, 0xc88f, 0x21, 0 - .dw 0x39c0, 0xc88f, 0xffff, 0xc88f, 0x21, 0 - .dw 0x1a00, 0xc890, 0x1fff, 0xc890, 0x21, 0 - .dw 0x3a00, 0xc890, 0x3fff, 0xc890, 0x21, 0 - .dw 0x5a00, 0xc890, 0x5fff, 0xc890, 0x21, 0 - .dw 0x7a00, 0xc890, 0x7fff, 0xc890, 0x21, 0 - .dw 0x9a00, 0xc890, 0x9fff, 0xc890, 0x21, 0 - .dw 0xba00, 0xc890, 0xbfff, 0xc890, 0x21, 0 - .dw 0xda00, 0xc890, 0xdfff, 0xc890, 0x21, 0 - .dw 0xfa00, 0xc890, 0xffff, 0xc890, 0x21, 0 - .dw 0x1a00, 0xc891, 0x1fff, 0xc891, 0x21, 0 - .dw 0x3a00, 0xc891, 0x3fff, 0xc891, 0x21, 0 - .dw 0x5a00, 0xc891, 0x5fff, 0xc891, 0x21, 0 - .dw 0x7a00, 0xc891, 0x7fff, 0xc891, 0x21, 0 - .dw 0x9a00, 0xc891, 0x9fff, 0xc891, 0x21, 0 - .dw 0xba00, 0xc891, 0xbfff, 0xc891, 0x21, 0 - .dw 0xda00, 0xc891, 0xdfff, 0xc891, 0x21, 0 - .dw 0xfa00, 0xc891, 0xffff, 0xc891, 0x21, 0 - .dw 0x1a00, 0xc892, 0x1fff, 0xc892, 0x21, 0 - .dw 0x3a00, 0xc892, 0x3fff, 0xc892, 0x21, 0 - .dw 0x5a00, 0xc892, 0x5fff, 0xc892, 0x21, 0 - .dw 0x7a00, 0xc892, 0x7fff, 0xc892, 0x21, 0 - .dw 0x9a00, 0xc892, 0x9fff, 0xc892, 0x21, 0 - .dw 0xba00, 0xc892, 0xbfff, 0xc892, 0x21, 0 - .dw 0xda00, 0xc892, 0xdfff, 0xc892, 0x21, 0 - .dw 0xfa00, 0xc892, 0xffff, 0xc893, 0x21, 0 - .dw 0x1a00, 0xc894, 0x1fff, 0xc894, 0x21, 0 - .dw 0x3a00, 0xc894, 0x3fff, 0xc894, 0x21, 0 - .dw 0x5a00, 0xc894, 0x5fff, 0xc894, 0x21, 0 - .dw 0x7a00, 0xc894, 0x7fff, 0xc894, 0x21, 0 - .dw 0x9a00, 0xc894, 0x9fff, 0xc894, 0x21, 0 - .dw 0xba00, 0xc894, 0xbfff, 0xc894, 0x21, 0 - .dw 0xda00, 0xc894, 0xdfff, 0xc894, 0x21, 0 - .dw 0xfa00, 0xc894, 0xffff, 0xc894, 0x21, 0 - .dw 0x1a00, 0xc895, 0x1fff, 0xc895, 0x21, 0 - .dw 0x3a00, 0xc895, 0x3fff, 0xc895, 0x21, 0 - .dw 0x5a00, 0xc895, 0x5fff, 0xc895, 0x21, 0 - .dw 0x7a00, 0xc895, 0x7fff, 0xc895, 0x21, 0 - .dw 0x9a00, 0xc895, 0x9fff, 0xc895, 0x21, 0 - .dw 0xba00, 0xc895, 0xbfff, 0xc895, 0x21, 0 - .dw 0xda00, 0xc895, 0xdfff, 0xc895, 0x21, 0 - .dw 0xfa00, 0xc895, 0xffff, 0xc895, 0x21, 0 - .dw 0x1a00, 0xc896, 0x1fff, 0xc896, 0x21, 0 - .dw 0x3a00, 0xc896, 0x3fff, 0xc896, 0x21, 0 - .dw 0x5a00, 0xc896, 0x5fff, 0xc896, 0x21, 0 - .dw 0x7a00, 0xc896, 0x7fff, 0xc896, 0x21, 0 - .dw 0x9a00, 0xc896, 0x9fff, 0xc896, 0x21, 0 - .dw 0xba00, 0xc896, 0xbfff, 0xc896, 0x21, 0 - .dw 0xda00, 0xc896, 0xdfff, 0xc896, 0x21, 0 - .dw 0xfa00, 0xc896, 0xffff, 0xc896, 0x21, 0 - .dw 0x1a00, 0xc897, 0x1fff, 0xc897, 0x21, 0 - .dw 0x3a00, 0xc897, 0x1fff, 0xc898, 0x21, 0 - .dw 0x2040, 0xc898, 0x207f, 0xc898, 0x21, 0 - .dw 0x20c0, 0xc898, 0x20ff, 0xc898, 0x21, 0 - .dw 0x2140, 0xc898, 0x217f, 0xc898, 0x21, 0 - .dw 0x21c0, 0xc898, 0x21ff, 0xc898, 0x21, 0 - .dw 0x2240, 0xc898, 0x227f, 0xc898, 0x21, 0 - .dw 0x22c0, 0xc898, 0x22ff, 0xc898, 0x21, 0 - .dw 0x2340, 0xc898, 0x237f, 0xc898, 0x21, 0 - .dw 0x23c0, 0xc898, 0x23ff, 0xc898, 0x21, 0 - .dw 0x2440, 0xc898, 0x247f, 0xc898, 0x21, 0 - .dw 0x24c0, 0xc898, 0x24ff, 0xc898, 0x21, 0 - .dw 0x2540, 0xc898, 0x257f, 0xc898, 0x21, 0 - .dw 0x25c0, 0xc898, 0x25ff, 0xc898, 0x21, 0 - .dw 0x2640, 0xc898, 0x267f, 0xc898, 0x21, 0 - .dw 0x26c0, 0xc898, 0x26ff, 0xc898, 0x21, 0 - .dw 0x2740, 0xc898, 0x277f, 0xc898, 0x21, 0 - .dw 0x27c0, 0xc898, 0x27ff, 0xc898, 0x21, 0 - .dw 0x2840, 0xc898, 0x287f, 0xc898, 0x21, 0 - .dw 0x28c0, 0xc898, 0x28ff, 0xc898, 0x21, 0 - .dw 0x2940, 0xc898, 0x297f, 0xc898, 0x21, 0 - .dw 0x29c0, 0xc898, 0x29ff, 0xc898, 0x21, 0 - .dw 0x2a40, 0xc898, 0x2a7f, 0xc898, 0x21, 0 - .dw 0x2ac0, 0xc898, 0x2aff, 0xc898, 0x21, 0 - .dw 0x2b40, 0xc898, 0x2b7f, 0xc898, 0x21, 0 - .dw 0x2bc0, 0xc898, 0x2bff, 0xc898, 0x21, 0 - .dw 0x2c40, 0xc898, 0x2c7f, 0xc898, 0x21, 0 - .dw 0x2cc0, 0xc898, 0x2cff, 0xc898, 0x21, 0 - .dw 0x2d40, 0xc898, 0x2d7f, 0xc898, 0x21, 0 - .dw 0x2dc0, 0xc898, 0x2dff, 0xc898, 0x21, 0 - .dw 0x2e40, 0xc898, 0x2e7f, 0xc898, 0x21, 0 - .dw 0x2ec0, 0xc898, 0x2eff, 0xc898, 0x21, 0 - .dw 0x2f40, 0xc898, 0x2f7f, 0xc898, 0x21, 0 - .dw 0x2fc0, 0xc898, 0x2fff, 0xc898, 0x21, 0 - .dw 0x3040, 0xc898, 0x307f, 0xc898, 0x21, 0 - .dw 0x30c0, 0xc898, 0x30ff, 0xc898, 0x21, 0 - .dw 0x3140, 0xc898, 0x317f, 0xc898, 0x21, 0 - .dw 0x31c0, 0xc898, 0x31ff, 0xc898, 0x21, 0 - .dw 0x3240, 0xc898, 0x327f, 0xc898, 0x21, 0 - .dw 0x32c0, 0xc898, 0x32ff, 0xc898, 0x21, 0 - .dw 0x3340, 0xc898, 0x337f, 0xc898, 0x21, 0 - .dw 0x33c0, 0xc898, 0x33ff, 0xc898, 0x21, 0 - .dw 0x3440, 0xc898, 0x347f, 0xc898, 0x21, 0 - .dw 0x34c0, 0xc898, 0x34ff, 0xc898, 0x21, 0 - .dw 0x3540, 0xc898, 0x357f, 0xc898, 0x21, 0 - .dw 0x35c0, 0xc898, 0x35ff, 0xc898, 0x21, 0 - .dw 0x3640, 0xc898, 0x367f, 0xc898, 0x21, 0 - .dw 0x36c0, 0xc898, 0x36ff, 0xc898, 0x21, 0 - .dw 0x3740, 0xc898, 0x377f, 0xc898, 0x21, 0 - .dw 0x37c0, 0xc898, 0x37ff, 0xc898, 0x21, 0 - .dw 0x3840, 0xc898, 0x387f, 0xc898, 0x21, 0 - .dw 0x38c0, 0xc898, 0x38ff, 0xc898, 0x21, 0 - .dw 0x3940, 0xc898, 0x397f, 0xc898, 0x21, 0 - .dw 0x39c0, 0xc898, 0x5fff, 0xc898, 0x21, 0 - .dw 0x6040, 0xc898, 0x607f, 0xc898, 0x21, 0 - .dw 0x60c0, 0xc898, 0x60ff, 0xc898, 0x21, 0 - .dw 0x6140, 0xc898, 0x617f, 0xc898, 0x21, 0 - .dw 0x61c0, 0xc898, 0x61ff, 0xc898, 0x21, 0 - .dw 0x6240, 0xc898, 0x627f, 0xc898, 0x21, 0 - .dw 0x62c0, 0xc898, 0x62ff, 0xc898, 0x21, 0 - .dw 0x6340, 0xc898, 0x637f, 0xc898, 0x21, 0 - .dw 0x63c0, 0xc898, 0x63ff, 0xc898, 0x21, 0 - .dw 0x6440, 0xc898, 0x647f, 0xc898, 0x21, 0 - .dw 0x64c0, 0xc898, 0x64ff, 0xc898, 0x21, 0 - .dw 0x6540, 0xc898, 0x657f, 0xc898, 0x21, 0 - .dw 0x65c0, 0xc898, 0x65ff, 0xc898, 0x21, 0 - .dw 0x6640, 0xc898, 0x667f, 0xc898, 0x21, 0 - .dw 0x66c0, 0xc898, 0x66ff, 0xc898, 0x21, 0 - .dw 0x6740, 0xc898, 0x677f, 0xc898, 0x21, 0 - .dw 0x67c0, 0xc898, 0x67ff, 0xc898, 0x21, 0 - .dw 0x6840, 0xc898, 0x687f, 0xc898, 0x21, 0 - .dw 0x68c0, 0xc898, 0x68ff, 0xc898, 0x21, 0 - .dw 0x6940, 0xc898, 0x697f, 0xc898, 0x21, 0 - .dw 0x69c0, 0xc898, 0x69ff, 0xc898, 0x21, 0 - .dw 0x6a40, 0xc898, 0x6a7f, 0xc898, 0x21, 0 - .dw 0x6ac0, 0xc898, 0x6aff, 0xc898, 0x21, 0 - .dw 0x6b40, 0xc898, 0x6b7f, 0xc898, 0x21, 0 - .dw 0x6bc0, 0xc898, 0x6bff, 0xc898, 0x21, 0 - .dw 0x6c40, 0xc898, 0x6c7f, 0xc898, 0x21, 0 - .dw 0x6cc0, 0xc898, 0x6cff, 0xc898, 0x21, 0 - .dw 0x6d40, 0xc898, 0x6d7f, 0xc898, 0x21, 0 - .dw 0x6dc0, 0xc898, 0x6dff, 0xc898, 0x21, 0 - .dw 0x6e40, 0xc898, 0x6e7f, 0xc898, 0x21, 0 - .dw 0x6ec0, 0xc898, 0x6eff, 0xc898, 0x21, 0 - .dw 0x6f40, 0xc898, 0x6f7f, 0xc898, 0x21, 0 - .dw 0x6fc0, 0xc898, 0x6fff, 0xc898, 0x21, 0 - .dw 0x7040, 0xc898, 0x707f, 0xc898, 0x21, 0 - .dw 0x70c0, 0xc898, 0x70ff, 0xc898, 0x21, 0 - .dw 0x7140, 0xc898, 0x717f, 0xc898, 0x21, 0 - .dw 0x71c0, 0xc898, 0x71ff, 0xc898, 0x21, 0 - .dw 0x7240, 0xc898, 0x727f, 0xc898, 0x21, 0 - .dw 0x72c0, 0xc898, 0x72ff, 0xc898, 0x21, 0 - .dw 0x7340, 0xc898, 0x737f, 0xc898, 0x21, 0 - .dw 0x73c0, 0xc898, 0x73ff, 0xc898, 0x21, 0 - .dw 0x7440, 0xc898, 0x747f, 0xc898, 0x21, 0 - .dw 0x74c0, 0xc898, 0x74ff, 0xc898, 0x21, 0 - .dw 0x7540, 0xc898, 0x757f, 0xc898, 0x21, 0 - .dw 0x75c0, 0xc898, 0x75ff, 0xc898, 0x21, 0 - .dw 0x7640, 0xc898, 0x767f, 0xc898, 0x21, 0 - .dw 0x76c0, 0xc898, 0x76ff, 0xc898, 0x21, 0 - .dw 0x7740, 0xc898, 0x777f, 0xc898, 0x21, 0 - .dw 0x77c0, 0xc898, 0x77ff, 0xc898, 0x21, 0 - .dw 0x7840, 0xc898, 0x787f, 0xc898, 0x21, 0 - .dw 0x78c0, 0xc898, 0x78ff, 0xc898, 0x21, 0 - .dw 0x7940, 0xc898, 0x797f, 0xc898, 0x21, 0 - .dw 0x79c0, 0xc898, 0x9fff, 0xc898, 0x21, 0 - .dw 0xa040, 0xc898, 0xa07f, 0xc898, 0x21, 0 - .dw 0xa0c0, 0xc898, 0xa0ff, 0xc898, 0x21, 0 - .dw 0xa140, 0xc898, 0xa17f, 0xc898, 0x21, 0 - .dw 0xa1c0, 0xc898, 0xa1ff, 0xc898, 0x21, 0 - .dw 0xa240, 0xc898, 0xa27f, 0xc898, 0x21, 0 - .dw 0xa2c0, 0xc898, 0xa2ff, 0xc898, 0x21, 0 - .dw 0xa340, 0xc898, 0xa37f, 0xc898, 0x21, 0 - .dw 0xa3c0, 0xc898, 0xa3ff, 0xc898, 0x21, 0 - .dw 0xa440, 0xc898, 0xa47f, 0xc898, 0x21, 0 - .dw 0xa4c0, 0xc898, 0xa4ff, 0xc898, 0x21, 0 - .dw 0xa540, 0xc898, 0xa57f, 0xc898, 0x21, 0 - .dw 0xa5c0, 0xc898, 0xa5ff, 0xc898, 0x21, 0 - .dw 0xa640, 0xc898, 0xa67f, 0xc898, 0x21, 0 - .dw 0xa6c0, 0xc898, 0xa6ff, 0xc898, 0x21, 0 - .dw 0xa740, 0xc898, 0xa77f, 0xc898, 0x21, 0 - .dw 0xa7c0, 0xc898, 0xa7ff, 0xc898, 0x21, 0 - .dw 0xa840, 0xc898, 0xa87f, 0xc898, 0x21, 0 - .dw 0xa8c0, 0xc898, 0xa8ff, 0xc898, 0x21, 0 - .dw 0xa940, 0xc898, 0xa97f, 0xc898, 0x21, 0 - .dw 0xa9c0, 0xc898, 0xa9ff, 0xc898, 0x21, 0 - .dw 0xaa40, 0xc898, 0xaa7f, 0xc898, 0x21, 0 - .dw 0xaac0, 0xc898, 0xaaff, 0xc898, 0x21, 0 - .dw 0xab40, 0xc898, 0xab7f, 0xc898, 0x21, 0 - .dw 0xabc0, 0xc898, 0xabff, 0xc898, 0x21, 0 - .dw 0xac40, 0xc898, 0xac7f, 0xc898, 0x21, 0 - .dw 0xacc0, 0xc898, 0xacff, 0xc898, 0x21, 0 - .dw 0xad40, 0xc898, 0xad7f, 0xc898, 0x21, 0 - .dw 0xadc0, 0xc898, 0xadff, 0xc898, 0x21, 0 - .dw 0xae40, 0xc898, 0xae7f, 0xc898, 0x21, 0 - .dw 0xaec0, 0xc898, 0xaeff, 0xc898, 0x21, 0 - .dw 0xaf40, 0xc898, 0xaf7f, 0xc898, 0x21, 0 - .dw 0xafc0, 0xc898, 0xafff, 0xc898, 0x21, 0 - .dw 0xb040, 0xc898, 0xb07f, 0xc898, 0x21, 0 - .dw 0xb0c0, 0xc898, 0xb0ff, 0xc898, 0x21, 0 - .dw 0xb140, 0xc898, 0xb17f, 0xc898, 0x21, 0 - .dw 0xb1c0, 0xc898, 0xb1ff, 0xc898, 0x21, 0 - .dw 0xb240, 0xc898, 0xb27f, 0xc898, 0x21, 0 - .dw 0xb2c0, 0xc898, 0xb2ff, 0xc898, 0x21, 0 - .dw 0xb340, 0xc898, 0xb37f, 0xc898, 0x21, 0 - .dw 0xb3c0, 0xc898, 0xb3ff, 0xc898, 0x21, 0 - .dw 0xb440, 0xc898, 0xb47f, 0xc898, 0x21, 0 - .dw 0xb4c0, 0xc898, 0xb4ff, 0xc898, 0x21, 0 - .dw 0xb540, 0xc898, 0xb57f, 0xc898, 0x21, 0 - .dw 0xb5c0, 0xc898, 0xb5ff, 0xc898, 0x21, 0 - .dw 0xb640, 0xc898, 0xb67f, 0xc898, 0x21, 0 - .dw 0xb6c0, 0xc898, 0xb6ff, 0xc898, 0x21, 0 - .dw 0xb740, 0xc898, 0xb77f, 0xc898, 0x21, 0 - .dw 0xb7c0, 0xc898, 0xb7ff, 0xc898, 0x21, 0 - .dw 0xb840, 0xc898, 0xb87f, 0xc898, 0x21, 0 - .dw 0xb8c0, 0xc898, 0xb8ff, 0xc898, 0x21, 0 - .dw 0xb940, 0xc898, 0xb97f, 0xc898, 0x21, 0 - .dw 0xb9c0, 0xc898, 0xdfff, 0xc898, 0x21, 0 - .dw 0xe040, 0xc898, 0xe07f, 0xc898, 0x21, 0 - .dw 0xe0c0, 0xc898, 0xe0ff, 0xc898, 0x21, 0 - .dw 0xe140, 0xc898, 0xe17f, 0xc898, 0x21, 0 - .dw 0xe1c0, 0xc898, 0xe1ff, 0xc898, 0x21, 0 - .dw 0xe240, 0xc898, 0xe27f, 0xc898, 0x21, 0 - .dw 0xe2c0, 0xc898, 0xe2ff, 0xc898, 0x21, 0 - .dw 0xe340, 0xc898, 0xe37f, 0xc898, 0x21, 0 - .dw 0xe3c0, 0xc898, 0xe3ff, 0xc898, 0x21, 0 - .dw 0xe440, 0xc898, 0xe47f, 0xc898, 0x21, 0 - .dw 0xe4c0, 0xc898, 0xe4ff, 0xc898, 0x21, 0 - .dw 0xe540, 0xc898, 0xe57f, 0xc898, 0x21, 0 - .dw 0xe5c0, 0xc898, 0xe5ff, 0xc898, 0x21, 0 - .dw 0xe640, 0xc898, 0xe67f, 0xc898, 0x21, 0 - .dw 0xe6c0, 0xc898, 0xe6ff, 0xc898, 0x21, 0 - .dw 0xe740, 0xc898, 0xe77f, 0xc898, 0x21, 0 - .dw 0xe7c0, 0xc898, 0xe7ff, 0xc898, 0x21, 0 - .dw 0xe840, 0xc898, 0xe87f, 0xc898, 0x21, 0 - .dw 0xe8c0, 0xc898, 0xe8ff, 0xc898, 0x21, 0 - .dw 0xe940, 0xc898, 0xe97f, 0xc898, 0x21, 0 - .dw 0xe9c0, 0xc898, 0xe9ff, 0xc898, 0x21, 0 - .dw 0xea40, 0xc898, 0xea7f, 0xc898, 0x21, 0 - .dw 0xeac0, 0xc898, 0xeaff, 0xc898, 0x21, 0 - .dw 0xeb40, 0xc898, 0xeb7f, 0xc898, 0x21, 0 - .dw 0xebc0, 0xc898, 0xebff, 0xc898, 0x21, 0 - .dw 0xec40, 0xc898, 0xec7f, 0xc898, 0x21, 0 - .dw 0xecc0, 0xc898, 0xecff, 0xc898, 0x21, 0 - .dw 0xed40, 0xc898, 0xed7f, 0xc898, 0x21, 0 - .dw 0xedc0, 0xc898, 0xedff, 0xc898, 0x21, 0 - .dw 0xee40, 0xc898, 0xee7f, 0xc898, 0x21, 0 - .dw 0xeec0, 0xc898, 0xeeff, 0xc898, 0x21, 0 - .dw 0xef40, 0xc898, 0xef7f, 0xc898, 0x21, 0 - .dw 0xefc0, 0xc898, 0xefff, 0xc898, 0x21, 0 - .dw 0xf040, 0xc898, 0xf07f, 0xc898, 0x21, 0 - .dw 0xf0c0, 0xc898, 0xf0ff, 0xc898, 0x21, 0 - .dw 0xf140, 0xc898, 0xf17f, 0xc898, 0x21, 0 - .dw 0xf1c0, 0xc898, 0xf1ff, 0xc898, 0x21, 0 - .dw 0xf240, 0xc898, 0xf27f, 0xc898, 0x21, 0 - .dw 0xf2c0, 0xc898, 0xf2ff, 0xc898, 0x21, 0 - .dw 0xf340, 0xc898, 0xf37f, 0xc898, 0x21, 0 - .dw 0xf3c0, 0xc898, 0xf3ff, 0xc898, 0x21, 0 - .dw 0xf440, 0xc898, 0xf47f, 0xc898, 0x21, 0 - .dw 0xf4c0, 0xc898, 0xf4ff, 0xc898, 0x21, 0 - .dw 0xf540, 0xc898, 0xf57f, 0xc898, 0x21, 0 - .dw 0xf5c0, 0xc898, 0xf5ff, 0xc898, 0x21, 0 - .dw 0xf640, 0xc898, 0xf67f, 0xc898, 0x21, 0 - .dw 0xf6c0, 0xc898, 0xf6ff, 0xc898, 0x21, 0 - .dw 0xf740, 0xc898, 0xf77f, 0xc898, 0x21, 0 - .dw 0xf7c0, 0xc898, 0xf7ff, 0xc898, 0x21, 0 - .dw 0xf840, 0xc898, 0xf87f, 0xc898, 0x21, 0 - .dw 0xf8c0, 0xc898, 0xf8ff, 0xc898, 0x21, 0 - .dw 0xf940, 0xc898, 0xf97f, 0xc898, 0x21, 0 - .dw 0xf9c0, 0xc898, 0x1fff, 0xc899, 0x21, 0 - .dw 0x2040, 0xc899, 0x207f, 0xc899, 0x21, 0 - .dw 0x20c0, 0xc899, 0x20ff, 0xc899, 0x21, 0 - .dw 0x2140, 0xc899, 0x217f, 0xc899, 0x21, 0 - .dw 0x21c0, 0xc899, 0x21ff, 0xc899, 0x21, 0 - .dw 0x2240, 0xc899, 0x227f, 0xc899, 0x21, 0 - .dw 0x22c0, 0xc899, 0x22ff, 0xc899, 0x21, 0 - .dw 0x2340, 0xc899, 0x237f, 0xc899, 0x21, 0 - .dw 0x23c0, 0xc899, 0x23ff, 0xc899, 0x21, 0 - .dw 0x2440, 0xc899, 0x247f, 0xc899, 0x21, 0 - .dw 0x24c0, 0xc899, 0x24ff, 0xc899, 0x21, 0 - .dw 0x2540, 0xc899, 0x257f, 0xc899, 0x21, 0 - .dw 0x25c0, 0xc899, 0x25ff, 0xc899, 0x21, 0 - .dw 0x2640, 0xc899, 0x267f, 0xc899, 0x21, 0 - .dw 0x26c0, 0xc899, 0x26ff, 0xc899, 0x21, 0 - .dw 0x2740, 0xc899, 0x277f, 0xc899, 0x21, 0 - .dw 0x27c0, 0xc899, 0x27ff, 0xc899, 0x21, 0 - .dw 0x2840, 0xc899, 0x287f, 0xc899, 0x21, 0 - .dw 0x28c0, 0xc899, 0x28ff, 0xc899, 0x21, 0 - .dw 0x2940, 0xc899, 0x297f, 0xc899, 0x21, 0 - .dw 0x29c0, 0xc899, 0x29ff, 0xc899, 0x21, 0 - .dw 0x2a40, 0xc899, 0x2a7f, 0xc899, 0x21, 0 - .dw 0x2ac0, 0xc899, 0x2aff, 0xc899, 0x21, 0 - .dw 0x2b40, 0xc899, 0x2b7f, 0xc899, 0x21, 0 - .dw 0x2bc0, 0xc899, 0x2bff, 0xc899, 0x21, 0 - .dw 0x2c40, 0xc899, 0x2c7f, 0xc899, 0x21, 0 - .dw 0x2cc0, 0xc899, 0x2cff, 0xc899, 0x21, 0 - .dw 0x2d40, 0xc899, 0x2d7f, 0xc899, 0x21, 0 - .dw 0x2dc0, 0xc899, 0x2dff, 0xc899, 0x21, 0 - .dw 0x2e40, 0xc899, 0x2e7f, 0xc899, 0x21, 0 - .dw 0x2ec0, 0xc899, 0x2eff, 0xc899, 0x21, 0 - .dw 0x2f40, 0xc899, 0x2f7f, 0xc899, 0x21, 0 - .dw 0x2fc0, 0xc899, 0x2fff, 0xc899, 0x21, 0 - .dw 0x3040, 0xc899, 0x307f, 0xc899, 0x21, 0 - .dw 0x30c0, 0xc899, 0x30ff, 0xc899, 0x21, 0 - .dw 0x3140, 0xc899, 0x317f, 0xc899, 0x21, 0 - .dw 0x31c0, 0xc899, 0x31ff, 0xc899, 0x21, 0 - .dw 0x3240, 0xc899, 0x327f, 0xc899, 0x21, 0 - .dw 0x32c0, 0xc899, 0x32ff, 0xc899, 0x21, 0 - .dw 0x3340, 0xc899, 0x337f, 0xc899, 0x21, 0 - .dw 0x33c0, 0xc899, 0x33ff, 0xc899, 0x21, 0 - .dw 0x3440, 0xc899, 0x347f, 0xc899, 0x21, 0 - .dw 0x34c0, 0xc899, 0x34ff, 0xc899, 0x21, 0 - .dw 0x3540, 0xc899, 0x357f, 0xc899, 0x21, 0 - .dw 0x35c0, 0xc899, 0x35ff, 0xc899, 0x21, 0 - .dw 0x3640, 0xc899, 0x367f, 0xc899, 0x21, 0 - .dw 0x36c0, 0xc899, 0x36ff, 0xc899, 0x21, 0 - .dw 0x3740, 0xc899, 0x377f, 0xc899, 0x21, 0 - .dw 0x37c0, 0xc899, 0x37ff, 0xc899, 0x21, 0 - .dw 0x3840, 0xc899, 0x387f, 0xc899, 0x21, 0 - .dw 0x38c0, 0xc899, 0x38ff, 0xc899, 0x21, 0 - .dw 0x3940, 0xc899, 0x397f, 0xc899, 0x21, 0 - .dw 0x39c0, 0xc899, 0x5fff, 0xc899, 0x21, 0 - .dw 0x6040, 0xc899, 0x607f, 0xc899, 0x21, 0 - .dw 0x60c0, 0xc899, 0x60ff, 0xc899, 0x21, 0 - .dw 0x6140, 0xc899, 0x617f, 0xc899, 0x21, 0 - .dw 0x61c0, 0xc899, 0x61ff, 0xc899, 0x21, 0 - .dw 0x6240, 0xc899, 0x627f, 0xc899, 0x21, 0 - .dw 0x62c0, 0xc899, 0x62ff, 0xc899, 0x21, 0 - .dw 0x6340, 0xc899, 0x637f, 0xc899, 0x21, 0 - .dw 0x63c0, 0xc899, 0x63ff, 0xc899, 0x21, 0 - .dw 0x6440, 0xc899, 0x647f, 0xc899, 0x21, 0 - .dw 0x64c0, 0xc899, 0x64ff, 0xc899, 0x21, 0 - .dw 0x6540, 0xc899, 0x657f, 0xc899, 0x21, 0 - .dw 0x65c0, 0xc899, 0x65ff, 0xc899, 0x21, 0 - .dw 0x6640, 0xc899, 0x667f, 0xc899, 0x21, 0 - .dw 0x66c0, 0xc899, 0x66ff, 0xc899, 0x21, 0 - .dw 0x6740, 0xc899, 0x677f, 0xc899, 0x21, 0 - .dw 0x67c0, 0xc899, 0x67ff, 0xc899, 0x21, 0 - .dw 0x6840, 0xc899, 0x687f, 0xc899, 0x21, 0 - .dw 0x68c0, 0xc899, 0x68ff, 0xc899, 0x21, 0 - .dw 0x6940, 0xc899, 0x697f, 0xc899, 0x21, 0 - .dw 0x69c0, 0xc899, 0x69ff, 0xc899, 0x21, 0 - .dw 0x6a40, 0xc899, 0x6a7f, 0xc899, 0x21, 0 - .dw 0x6ac0, 0xc899, 0x6aff, 0xc899, 0x21, 0 - .dw 0x6b40, 0xc899, 0x6b7f, 0xc899, 0x21, 0 - .dw 0x6bc0, 0xc899, 0x6bff, 0xc899, 0x21, 0 - .dw 0x6c40, 0xc899, 0x6c7f, 0xc899, 0x21, 0 - .dw 0x6cc0, 0xc899, 0x6cff, 0xc899, 0x21, 0 - .dw 0x6d40, 0xc899, 0x6d7f, 0xc899, 0x21, 0 - .dw 0x6dc0, 0xc899, 0x6dff, 0xc899, 0x21, 0 - .dw 0x6e40, 0xc899, 0x6e7f, 0xc899, 0x21, 0 - .dw 0x6ec0, 0xc899, 0x6eff, 0xc899, 0x21, 0 - .dw 0x6f40, 0xc899, 0x6f7f, 0xc899, 0x21, 0 - .dw 0x6fc0, 0xc899, 0x6fff, 0xc899, 0x21, 0 - .dw 0x7040, 0xc899, 0x707f, 0xc899, 0x21, 0 - .dw 0x70c0, 0xc899, 0x70ff, 0xc899, 0x21, 0 - .dw 0x7140, 0xc899, 0x717f, 0xc899, 0x21, 0 - .dw 0x71c0, 0xc899, 0x71ff, 0xc899, 0x21, 0 - .dw 0x7240, 0xc899, 0x727f, 0xc899, 0x21, 0 - .dw 0x72c0, 0xc899, 0x72ff, 0xc899, 0x21, 0 - .dw 0x7340, 0xc899, 0x737f, 0xc899, 0x21, 0 - .dw 0x73c0, 0xc899, 0x73ff, 0xc899, 0x21, 0 - .dw 0x7440, 0xc899, 0x747f, 0xc899, 0x21, 0 - .dw 0x74c0, 0xc899, 0x74ff, 0xc899, 0x21, 0 - .dw 0x7540, 0xc899, 0x757f, 0xc899, 0x21, 0 - .dw 0x75c0, 0xc899, 0x75ff, 0xc899, 0x21, 0 - .dw 0x7640, 0xc899, 0x767f, 0xc899, 0x21, 0 - .dw 0x76c0, 0xc899, 0x76ff, 0xc899, 0x21, 0 - .dw 0x7740, 0xc899, 0x777f, 0xc899, 0x21, 0 - .dw 0x77c0, 0xc899, 0x77ff, 0xc899, 0x21, 0 - .dw 0x7840, 0xc899, 0x787f, 0xc899, 0x21, 0 - .dw 0x78c0, 0xc899, 0x78ff, 0xc899, 0x21, 0 - .dw 0x7940, 0xc899, 0x797f, 0xc899, 0x21, 0 - .dw 0x79c0, 0xc899, 0x9fff, 0xc899, 0x21, 0 - .dw 0xa040, 0xc899, 0xa07f, 0xc899, 0x21, 0 - .dw 0xa0c0, 0xc899, 0xa0ff, 0xc899, 0x21, 0 - .dw 0xa140, 0xc899, 0xa17f, 0xc899, 0x21, 0 - .dw 0xa1c0, 0xc899, 0xa1ff, 0xc899, 0x21, 0 - .dw 0xa240, 0xc899, 0xa27f, 0xc899, 0x21, 0 - .dw 0xa2c0, 0xc899, 0xa2ff, 0xc899, 0x21, 0 - .dw 0xa340, 0xc899, 0xa37f, 0xc899, 0x21, 0 - .dw 0xa3c0, 0xc899, 0xa3ff, 0xc899, 0x21, 0 - .dw 0xa440, 0xc899, 0xa47f, 0xc899, 0x21, 0 - .dw 0xa4c0, 0xc899, 0xa4ff, 0xc899, 0x21, 0 - .dw 0xa540, 0xc899, 0xa57f, 0xc899, 0x21, 0 - .dw 0xa5c0, 0xc899, 0xa5ff, 0xc899, 0x21, 0 - .dw 0xa640, 0xc899, 0xa67f, 0xc899, 0x21, 0 - .dw 0xa6c0, 0xc899, 0xa6ff, 0xc899, 0x21, 0 - .dw 0xa740, 0xc899, 0xa77f, 0xc899, 0x21, 0 - .dw 0xa7c0, 0xc899, 0xa7ff, 0xc899, 0x21, 0 - .dw 0xa840, 0xc899, 0xa87f, 0xc899, 0x21, 0 - .dw 0xa8c0, 0xc899, 0xa8ff, 0xc899, 0x21, 0 - .dw 0xa940, 0xc899, 0xa97f, 0xc899, 0x21, 0 - .dw 0xa9c0, 0xc899, 0xa9ff, 0xc899, 0x21, 0 - .dw 0xaa40, 0xc899, 0xaa7f, 0xc899, 0x21, 0 - .dw 0xaac0, 0xc899, 0xaaff, 0xc899, 0x21, 0 - .dw 0xab40, 0xc899, 0xab7f, 0xc899, 0x21, 0 - .dw 0xabc0, 0xc899, 0xabff, 0xc899, 0x21, 0 - .dw 0xac40, 0xc899, 0xac7f, 0xc899, 0x21, 0 - .dw 0xacc0, 0xc899, 0xacff, 0xc899, 0x21, 0 - .dw 0xad40, 0xc899, 0xad7f, 0xc899, 0x21, 0 - .dw 0xadc0, 0xc899, 0xadff, 0xc899, 0x21, 0 - .dw 0xae40, 0xc899, 0xae7f, 0xc899, 0x21, 0 - .dw 0xaec0, 0xc899, 0xaeff, 0xc899, 0x21, 0 - .dw 0xaf40, 0xc899, 0xaf7f, 0xc899, 0x21, 0 - .dw 0xafc0, 0xc899, 0xafff, 0xc899, 0x21, 0 - .dw 0xb040, 0xc899, 0xb07f, 0xc899, 0x21, 0 - .dw 0xb0c0, 0xc899, 0xb0ff, 0xc899, 0x21, 0 - .dw 0xb140, 0xc899, 0xb17f, 0xc899, 0x21, 0 - .dw 0xb1c0, 0xc899, 0xb1ff, 0xc899, 0x21, 0 - .dw 0xb240, 0xc899, 0xb27f, 0xc899, 0x21, 0 - .dw 0xb2c0, 0xc899, 0xb2ff, 0xc899, 0x21, 0 - .dw 0xb340, 0xc899, 0xb37f, 0xc899, 0x21, 0 - .dw 0xb3c0, 0xc899, 0xb3ff, 0xc899, 0x21, 0 - .dw 0xb440, 0xc899, 0xb47f, 0xc899, 0x21, 0 - .dw 0xb4c0, 0xc899, 0xb4ff, 0xc899, 0x21, 0 - .dw 0xb540, 0xc899, 0xb57f, 0xc899, 0x21, 0 - .dw 0xb5c0, 0xc899, 0xb5ff, 0xc899, 0x21, 0 - .dw 0xb640, 0xc899, 0xb67f, 0xc899, 0x21, 0 - .dw 0xb6c0, 0xc899, 0xb6ff, 0xc899, 0x21, 0 - .dw 0xb740, 0xc899, 0xb77f, 0xc899, 0x21, 0 - .dw 0xb7c0, 0xc899, 0xb7ff, 0xc899, 0x21, 0 - .dw 0xb840, 0xc899, 0xb87f, 0xc899, 0x21, 0 - .dw 0xb8c0, 0xc899, 0xb8ff, 0xc899, 0x21, 0 - .dw 0xb940, 0xc899, 0xb97f, 0xc899, 0x21, 0 - .dw 0xb9c0, 0xc899, 0xdfff, 0xc899, 0x21, 0 - .dw 0xe040, 0xc899, 0xe07f, 0xc899, 0x21, 0 - .dw 0xe0c0, 0xc899, 0xe0ff, 0xc899, 0x21, 0 - .dw 0xe140, 0xc899, 0xe17f, 0xc899, 0x21, 0 - .dw 0xe1c0, 0xc899, 0xe1ff, 0xc899, 0x21, 0 - .dw 0xe240, 0xc899, 0xe27f, 0xc899, 0x21, 0 - .dw 0xe2c0, 0xc899, 0xe2ff, 0xc899, 0x21, 0 - .dw 0xe340, 0xc899, 0xe37f, 0xc899, 0x21, 0 - .dw 0xe3c0, 0xc899, 0xe3ff, 0xc899, 0x21, 0 - .dw 0xe440, 0xc899, 0xe47f, 0xc899, 0x21, 0 - .dw 0xe4c0, 0xc899, 0xe4ff, 0xc899, 0x21, 0 - .dw 0xe540, 0xc899, 0xe57f, 0xc899, 0x21, 0 - .dw 0xe5c0, 0xc899, 0xe5ff, 0xc899, 0x21, 0 - .dw 0xe640, 0xc899, 0xe67f, 0xc899, 0x21, 0 - .dw 0xe6c0, 0xc899, 0xe6ff, 0xc899, 0x21, 0 - .dw 0xe740, 0xc899, 0xe77f, 0xc899, 0x21, 0 - .dw 0xe7c0, 0xc899, 0xe7ff, 0xc899, 0x21, 0 - .dw 0xe840, 0xc899, 0xe87f, 0xc899, 0x21, 0 - .dw 0xe8c0, 0xc899, 0xe8ff, 0xc899, 0x21, 0 - .dw 0xe940, 0xc899, 0xe97f, 0xc899, 0x21, 0 - .dw 0xe9c0, 0xc899, 0xe9ff, 0xc899, 0x21, 0 - .dw 0xea40, 0xc899, 0xea7f, 0xc899, 0x21, 0 - .dw 0xeac0, 0xc899, 0xeaff, 0xc899, 0x21, 0 - .dw 0xeb40, 0xc899, 0xeb7f, 0xc899, 0x21, 0 - .dw 0xebc0, 0xc899, 0xebff, 0xc899, 0x21, 0 - .dw 0xec40, 0xc899, 0xec7f, 0xc899, 0x21, 0 - .dw 0xecc0, 0xc899, 0xecff, 0xc899, 0x21, 0 - .dw 0xed40, 0xc899, 0xed7f, 0xc899, 0x21, 0 - .dw 0xedc0, 0xc899, 0xedff, 0xc899, 0x21, 0 - .dw 0xee40, 0xc899, 0xee7f, 0xc899, 0x21, 0 - .dw 0xeec0, 0xc899, 0xeeff, 0xc899, 0x21, 0 - .dw 0xef40, 0xc899, 0xef7f, 0xc899, 0x21, 0 - .dw 0xefc0, 0xc899, 0xefff, 0xc899, 0x21, 0 - .dw 0xf040, 0xc899, 0xf07f, 0xc899, 0x21, 0 - .dw 0xf0c0, 0xc899, 0xf0ff, 0xc899, 0x21, 0 - .dw 0xf140, 0xc899, 0xf17f, 0xc899, 0x21, 0 - .dw 0xf1c0, 0xc899, 0xf1ff, 0xc899, 0x21, 0 - .dw 0xf240, 0xc899, 0xf27f, 0xc899, 0x21, 0 - .dw 0xf2c0, 0xc899, 0xf2ff, 0xc899, 0x21, 0 - .dw 0xf340, 0xc899, 0xf37f, 0xc899, 0x21, 0 - .dw 0xf3c0, 0xc899, 0xf3ff, 0xc899, 0x21, 0 - .dw 0xf440, 0xc899, 0xf47f, 0xc899, 0x21, 0 - .dw 0xf4c0, 0xc899, 0xf4ff, 0xc899, 0x21, 0 - .dw 0xf540, 0xc899, 0xf57f, 0xc899, 0x21, 0 - .dw 0xf5c0, 0xc899, 0xf5ff, 0xc899, 0x21, 0 - .dw 0xf640, 0xc899, 0xf67f, 0xc899, 0x21, 0 - .dw 0xf6c0, 0xc899, 0xf6ff, 0xc899, 0x21, 0 - .dw 0xf740, 0xc899, 0xf77f, 0xc899, 0x21, 0 - .dw 0xf7c0, 0xc899, 0xf7ff, 0xc899, 0x21, 0 - .dw 0xf840, 0xc899, 0xf87f, 0xc899, 0x21, 0 - .dw 0xf8c0, 0xc899, 0xf8ff, 0xc899, 0x21, 0 - .dw 0xf940, 0xc899, 0xf97f, 0xc899, 0x21, 0 - .dw 0xf9c0, 0xc899, 0x1fff, 0xc89a, 0x21, 0 - .dw 0x2040, 0xc89a, 0x207f, 0xc89a, 0x21, 0 - .dw 0x20c0, 0xc89a, 0x20ff, 0xc89a, 0x21, 0 - .dw 0x2140, 0xc89a, 0x217f, 0xc89a, 0x21, 0 - .dw 0x21c0, 0xc89a, 0x21ff, 0xc89a, 0x21, 0 - .dw 0x2240, 0xc89a, 0x227f, 0xc89a, 0x21, 0 - .dw 0x22c0, 0xc89a, 0x22ff, 0xc89a, 0x21, 0 - .dw 0x2340, 0xc89a, 0x237f, 0xc89a, 0x21, 0 - .dw 0x23c0, 0xc89a, 0x23ff, 0xc89a, 0x21, 0 - .dw 0x2440, 0xc89a, 0x247f, 0xc89a, 0x21, 0 - .dw 0x24c0, 0xc89a, 0x24ff, 0xc89a, 0x21, 0 - .dw 0x2540, 0xc89a, 0x257f, 0xc89a, 0x21, 0 - .dw 0x25c0, 0xc89a, 0x25ff, 0xc89a, 0x21, 0 - .dw 0x2640, 0xc89a, 0x267f, 0xc89a, 0x21, 0 - .dw 0x26c0, 0xc89a, 0x26ff, 0xc89a, 0x21, 0 - .dw 0x2740, 0xc89a, 0x277f, 0xc89a, 0x21, 0 - .dw 0x27c0, 0xc89a, 0x27ff, 0xc89a, 0x21, 0 - .dw 0x2840, 0xc89a, 0x287f, 0xc89a, 0x21, 0 - .dw 0x28c0, 0xc89a, 0x28ff, 0xc89a, 0x21, 0 - .dw 0x2940, 0xc89a, 0x297f, 0xc89a, 0x21, 0 - .dw 0x29c0, 0xc89a, 0x29ff, 0xc89a, 0x21, 0 - .dw 0x2a40, 0xc89a, 0x2a7f, 0xc89a, 0x21, 0 - .dw 0x2ac0, 0xc89a, 0x2aff, 0xc89a, 0x21, 0 - .dw 0x2b40, 0xc89a, 0x2b7f, 0xc89a, 0x21, 0 - .dw 0x2bc0, 0xc89a, 0x2bff, 0xc89a, 0x21, 0 - .dw 0x2c40, 0xc89a, 0x2c7f, 0xc89a, 0x21, 0 - .dw 0x2cc0, 0xc89a, 0x2cff, 0xc89a, 0x21, 0 - .dw 0x2d40, 0xc89a, 0x2d7f, 0xc89a, 0x21, 0 - .dw 0x2dc0, 0xc89a, 0x2dff, 0xc89a, 0x21, 0 - .dw 0x2e40, 0xc89a, 0x2e7f, 0xc89a, 0x21, 0 - .dw 0x2ec0, 0xc89a, 0x2eff, 0xc89a, 0x21, 0 - .dw 0x2f40, 0xc89a, 0x2f7f, 0xc89a, 0x21, 0 - .dw 0x2fc0, 0xc89a, 0x2fff, 0xc89a, 0x21, 0 - .dw 0x3040, 0xc89a, 0x307f, 0xc89a, 0x21, 0 - .dw 0x30c0, 0xc89a, 0x30ff, 0xc89a, 0x21, 0 - .dw 0x3140, 0xc89a, 0x317f, 0xc89a, 0x21, 0 - .dw 0x31c0, 0xc89a, 0x31ff, 0xc89a, 0x21, 0 - .dw 0x3240, 0xc89a, 0x327f, 0xc89a, 0x21, 0 - .dw 0x32c0, 0xc89a, 0x32ff, 0xc89a, 0x21, 0 - .dw 0x3340, 0xc89a, 0x337f, 0xc89a, 0x21, 0 - .dw 0x33c0, 0xc89a, 0x33ff, 0xc89a, 0x21, 0 - .dw 0x3440, 0xc89a, 0x347f, 0xc89a, 0x21, 0 - .dw 0x34c0, 0xc89a, 0x34ff, 0xc89a, 0x21, 0 - .dw 0x3540, 0xc89a, 0x357f, 0xc89a, 0x21, 0 - .dw 0x35c0, 0xc89a, 0x35ff, 0xc89a, 0x21, 0 - .dw 0x3640, 0xc89a, 0x367f, 0xc89a, 0x21, 0 - .dw 0x36c0, 0xc89a, 0x36ff, 0xc89a, 0x21, 0 - .dw 0x3740, 0xc89a, 0x377f, 0xc89a, 0x21, 0 - .dw 0x37c0, 0xc89a, 0x37ff, 0xc89a, 0x21, 0 - .dw 0x3840, 0xc89a, 0x387f, 0xc89a, 0x21, 0 - .dw 0x38c0, 0xc89a, 0x38ff, 0xc89a, 0x21, 0 - .dw 0x3940, 0xc89a, 0x397f, 0xc89a, 0x21, 0 - .dw 0x39c0, 0xc89a, 0x5fff, 0xc89a, 0x21, 0 - .dw 0x6040, 0xc89a, 0x607f, 0xc89a, 0x21, 0 - .dw 0x60c0, 0xc89a, 0x60ff, 0xc89a, 0x21, 0 - .dw 0x6140, 0xc89a, 0x617f, 0xc89a, 0x21, 0 - .dw 0x61c0, 0xc89a, 0x61ff, 0xc89a, 0x21, 0 - .dw 0x6240, 0xc89a, 0x627f, 0xc89a, 0x21, 0 - .dw 0x62c0, 0xc89a, 0x62ff, 0xc89a, 0x21, 0 - .dw 0x6340, 0xc89a, 0x637f, 0xc89a, 0x21, 0 - .dw 0x63c0, 0xc89a, 0x63ff, 0xc89a, 0x21, 0 - .dw 0x6440, 0xc89a, 0x647f, 0xc89a, 0x21, 0 - .dw 0x64c0, 0xc89a, 0x64ff, 0xc89a, 0x21, 0 - .dw 0x6540, 0xc89a, 0x657f, 0xc89a, 0x21, 0 - .dw 0x65c0, 0xc89a, 0x65ff, 0xc89a, 0x21, 0 - .dw 0x6640, 0xc89a, 0x667f, 0xc89a, 0x21, 0 - .dw 0x66c0, 0xc89a, 0x66ff, 0xc89a, 0x21, 0 - .dw 0x6740, 0xc89a, 0x677f, 0xc89a, 0x21, 0 - .dw 0x67c0, 0xc89a, 0x67ff, 0xc89a, 0x21, 0 - .dw 0x6840, 0xc89a, 0x687f, 0xc89a, 0x21, 0 - .dw 0x68c0, 0xc89a, 0x68ff, 0xc89a, 0x21, 0 - .dw 0x6940, 0xc89a, 0x697f, 0xc89a, 0x21, 0 - .dw 0x69c0, 0xc89a, 0x69ff, 0xc89a, 0x21, 0 - .dw 0x6a40, 0xc89a, 0x6a7f, 0xc89a, 0x21, 0 - .dw 0x6ac0, 0xc89a, 0x6aff, 0xc89a, 0x21, 0 - .dw 0x6b40, 0xc89a, 0x6b7f, 0xc89a, 0x21, 0 - .dw 0x6bc0, 0xc89a, 0x6bff, 0xc89a, 0x21, 0 - .dw 0x6c40, 0xc89a, 0x6c7f, 0xc89a, 0x21, 0 - .dw 0x6cc0, 0xc89a, 0x6cff, 0xc89a, 0x21, 0 - .dw 0x6d40, 0xc89a, 0x6d7f, 0xc89a, 0x21, 0 - .dw 0x6dc0, 0xc89a, 0x6dff, 0xc89a, 0x21, 0 - .dw 0x6e40, 0xc89a, 0x6e7f, 0xc89a, 0x21, 0 - .dw 0x6ec0, 0xc89a, 0x6eff, 0xc89a, 0x21, 0 - .dw 0x6f40, 0xc89a, 0x6f7f, 0xc89a, 0x21, 0 - .dw 0x6fc0, 0xc89a, 0x6fff, 0xc89a, 0x21, 0 - .dw 0x7040, 0xc89a, 0x707f, 0xc89a, 0x21, 0 - .dw 0x70c0, 0xc89a, 0x70ff, 0xc89a, 0x21, 0 - .dw 0x7140, 0xc89a, 0x717f, 0xc89a, 0x21, 0 - .dw 0x71c0, 0xc89a, 0x71ff, 0xc89a, 0x21, 0 - .dw 0x7240, 0xc89a, 0x727f, 0xc89a, 0x21, 0 - .dw 0x72c0, 0xc89a, 0x72ff, 0xc89a, 0x21, 0 - .dw 0x7340, 0xc89a, 0x737f, 0xc89a, 0x21, 0 - .dw 0x73c0, 0xc89a, 0x73ff, 0xc89a, 0x21, 0 - .dw 0x7440, 0xc89a, 0x747f, 0xc89a, 0x21, 0 - .dw 0x74c0, 0xc89a, 0x74ff, 0xc89a, 0x21, 0 - .dw 0x7540, 0xc89a, 0x757f, 0xc89a, 0x21, 0 - .dw 0x75c0, 0xc89a, 0x75ff, 0xc89a, 0x21, 0 - .dw 0x7640, 0xc89a, 0x767f, 0xc89a, 0x21, 0 - .dw 0x76c0, 0xc89a, 0x76ff, 0xc89a, 0x21, 0 - .dw 0x7740, 0xc89a, 0x777f, 0xc89a, 0x21, 0 - .dw 0x77c0, 0xc89a, 0x77ff, 0xc89a, 0x21, 0 - .dw 0x7840, 0xc89a, 0x787f, 0xc89a, 0x21, 0 - .dw 0x78c0, 0xc89a, 0x78ff, 0xc89a, 0x21, 0 - .dw 0x7940, 0xc89a, 0x797f, 0xc89a, 0x21, 0 - .dw 0x79c0, 0xc89a, 0x9fff, 0xc89a, 0x21, 0 - .dw 0xa040, 0xc89a, 0xa07f, 0xc89a, 0x21, 0 - .dw 0xa0c0, 0xc89a, 0xa0ff, 0xc89a, 0x21, 0 - .dw 0xa140, 0xc89a, 0xa17f, 0xc89a, 0x21, 0 - .dw 0xa1c0, 0xc89a, 0xa1ff, 0xc89a, 0x21, 0 - .dw 0xa240, 0xc89a, 0xa27f, 0xc89a, 0x21, 0 - .dw 0xa2c0, 0xc89a, 0xa2ff, 0xc89a, 0x21, 0 - .dw 0xa340, 0xc89a, 0xa37f, 0xc89a, 0x21, 0 - .dw 0xa3c0, 0xc89a, 0xa3ff, 0xc89a, 0x21, 0 - .dw 0xa440, 0xc89a, 0xa47f, 0xc89a, 0x21, 0 - .dw 0xa4c0, 0xc89a, 0xa4ff, 0xc89a, 0x21, 0 - .dw 0xa540, 0xc89a, 0xa57f, 0xc89a, 0x21, 0 - .dw 0xa5c0, 0xc89a, 0xa5ff, 0xc89a, 0x21, 0 - .dw 0xa640, 0xc89a, 0xa67f, 0xc89a, 0x21, 0 - .dw 0xa6c0, 0xc89a, 0xa6ff, 0xc89a, 0x21, 0 - .dw 0xa740, 0xc89a, 0xa77f, 0xc89a, 0x21, 0 - .dw 0xa7c0, 0xc89a, 0xa7ff, 0xc89a, 0x21, 0 - .dw 0xa840, 0xc89a, 0xa87f, 0xc89a, 0x21, 0 - .dw 0xa8c0, 0xc89a, 0xa8ff, 0xc89a, 0x21, 0 - .dw 0xa940, 0xc89a, 0xa97f, 0xc89a, 0x21, 0 - .dw 0xa9c0, 0xc89a, 0xa9ff, 0xc89a, 0x21, 0 - .dw 0xaa40, 0xc89a, 0xaa7f, 0xc89a, 0x21, 0 - .dw 0xaac0, 0xc89a, 0xaaff, 0xc89a, 0x21, 0 - .dw 0xab40, 0xc89a, 0xab7f, 0xc89a, 0x21, 0 - .dw 0xabc0, 0xc89a, 0xabff, 0xc89a, 0x21, 0 - .dw 0xac40, 0xc89a, 0xac7f, 0xc89a, 0x21, 0 - .dw 0xacc0, 0xc89a, 0xacff, 0xc89a, 0x21, 0 - .dw 0xad40, 0xc89a, 0xad7f, 0xc89a, 0x21, 0 - .dw 0xadc0, 0xc89a, 0xadff, 0xc89a, 0x21, 0 - .dw 0xae40, 0xc89a, 0xae7f, 0xc89a, 0x21, 0 - .dw 0xaec0, 0xc89a, 0xaeff, 0xc89a, 0x21, 0 - .dw 0xaf40, 0xc89a, 0xaf7f, 0xc89a, 0x21, 0 - .dw 0xafc0, 0xc89a, 0xafff, 0xc89a, 0x21, 0 - .dw 0xb040, 0xc89a, 0xb07f, 0xc89a, 0x21, 0 - .dw 0xb0c0, 0xc89a, 0xb0ff, 0xc89a, 0x21, 0 - .dw 0xb140, 0xc89a, 0xb17f, 0xc89a, 0x21, 0 - .dw 0xb1c0, 0xc89a, 0xb1ff, 0xc89a, 0x21, 0 - .dw 0xb240, 0xc89a, 0xb27f, 0xc89a, 0x21, 0 - .dw 0xb2c0, 0xc89a, 0xb2ff, 0xc89a, 0x21, 0 - .dw 0xb340, 0xc89a, 0xb37f, 0xc89a, 0x21, 0 - .dw 0xb3c0, 0xc89a, 0xb3ff, 0xc89a, 0x21, 0 - .dw 0xb440, 0xc89a, 0xb47f, 0xc89a, 0x21, 0 - .dw 0xb4c0, 0xc89a, 0xb4ff, 0xc89a, 0x21, 0 - .dw 0xb540, 0xc89a, 0xb57f, 0xc89a, 0x21, 0 - .dw 0xb5c0, 0xc89a, 0xb5ff, 0xc89a, 0x21, 0 - .dw 0xb640, 0xc89a, 0xb67f, 0xc89a, 0x21, 0 - .dw 0xb6c0, 0xc89a, 0xb6ff, 0xc89a, 0x21, 0 - .dw 0xb740, 0xc89a, 0xb77f, 0xc89a, 0x21, 0 - .dw 0xb7c0, 0xc89a, 0xb7ff, 0xc89a, 0x21, 0 - .dw 0xb840, 0xc89a, 0xb87f, 0xc89a, 0x21, 0 - .dw 0xb8c0, 0xc89a, 0xb8ff, 0xc89a, 0x21, 0 - .dw 0xb940, 0xc89a, 0xb97f, 0xc89a, 0x21, 0 - .dw 0xb9c0, 0xc89a, 0xdfff, 0xc89a, 0x21, 0 - .dw 0xe040, 0xc89a, 0xe07f, 0xc89a, 0x21, 0 - .dw 0xe0c0, 0xc89a, 0xe0ff, 0xc89a, 0x21, 0 - .dw 0xe140, 0xc89a, 0xe17f, 0xc89a, 0x21, 0 - .dw 0xe1c0, 0xc89a, 0xe1ff, 0xc89a, 0x21, 0 - .dw 0xe240, 0xc89a, 0xe27f, 0xc89a, 0x21, 0 - .dw 0xe2c0, 0xc89a, 0xe2ff, 0xc89a, 0x21, 0 - .dw 0xe340, 0xc89a, 0xe37f, 0xc89a, 0x21, 0 - .dw 0xe3c0, 0xc89a, 0xe3ff, 0xc89a, 0x21, 0 - .dw 0xe440, 0xc89a, 0xe47f, 0xc89a, 0x21, 0 - .dw 0xe4c0, 0xc89a, 0xe4ff, 0xc89a, 0x21, 0 - .dw 0xe540, 0xc89a, 0xe57f, 0xc89a, 0x21, 0 - .dw 0xe5c0, 0xc89a, 0xe5ff, 0xc89a, 0x21, 0 - .dw 0xe640, 0xc89a, 0xe67f, 0xc89a, 0x21, 0 - .dw 0xe6c0, 0xc89a, 0xe6ff, 0xc89a, 0x21, 0 - .dw 0xe740, 0xc89a, 0xe77f, 0xc89a, 0x21, 0 - .dw 0xe7c0, 0xc89a, 0xe7ff, 0xc89a, 0x21, 0 - .dw 0xe840, 0xc89a, 0xe87f, 0xc89a, 0x21, 0 - .dw 0xe8c0, 0xc89a, 0xe8ff, 0xc89a, 0x21, 0 - .dw 0xe940, 0xc89a, 0xe97f, 0xc89a, 0x21, 0 - .dw 0xe9c0, 0xc89a, 0xe9ff, 0xc89a, 0x21, 0 - .dw 0xea40, 0xc89a, 0xea7f, 0xc89a, 0x21, 0 - .dw 0xeac0, 0xc89a, 0xeaff, 0xc89a, 0x21, 0 - .dw 0xeb40, 0xc89a, 0xeb7f, 0xc89a, 0x21, 0 - .dw 0xebc0, 0xc89a, 0xebff, 0xc89a, 0x21, 0 - .dw 0xec40, 0xc89a, 0xec7f, 0xc89a, 0x21, 0 - .dw 0xecc0, 0xc89a, 0xecff, 0xc89a, 0x21, 0 - .dw 0xed40, 0xc89a, 0xed7f, 0xc89a, 0x21, 0 - .dw 0xedc0, 0xc89a, 0xedff, 0xc89a, 0x21, 0 - .dw 0xee40, 0xc89a, 0xee7f, 0xc89a, 0x21, 0 - .dw 0xeec0, 0xc89a, 0xeeff, 0xc89a, 0x21, 0 - .dw 0xef40, 0xc89a, 0xef7f, 0xc89a, 0x21, 0 - .dw 0xefc0, 0xc89a, 0xefff, 0xc89a, 0x21, 0 - .dw 0xf040, 0xc89a, 0xf07f, 0xc89a, 0x21, 0 - .dw 0xf0c0, 0xc89a, 0xf0ff, 0xc89a, 0x21, 0 - .dw 0xf140, 0xc89a, 0xf17f, 0xc89a, 0x21, 0 - .dw 0xf1c0, 0xc89a, 0xf1ff, 0xc89a, 0x21, 0 - .dw 0xf240, 0xc89a, 0xf27f, 0xc89a, 0x21, 0 - .dw 0xf2c0, 0xc89a, 0xf2ff, 0xc89a, 0x21, 0 - .dw 0xf340, 0xc89a, 0xf37f, 0xc89a, 0x21, 0 - .dw 0xf3c0, 0xc89a, 0xf3ff, 0xc89a, 0x21, 0 - .dw 0xf440, 0xc89a, 0xf47f, 0xc89a, 0x21, 0 - .dw 0xf4c0, 0xc89a, 0xf4ff, 0xc89a, 0x21, 0 - .dw 0xf540, 0xc89a, 0xf57f, 0xc89a, 0x21, 0 - .dw 0xf5c0, 0xc89a, 0xf5ff, 0xc89a, 0x21, 0 - .dw 0xf640, 0xc89a, 0xf67f, 0xc89a, 0x21, 0 - .dw 0xf6c0, 0xc89a, 0xf6ff, 0xc89a, 0x21, 0 - .dw 0xf740, 0xc89a, 0xf77f, 0xc89a, 0x21, 0 - .dw 0xf7c0, 0xc89a, 0xf7ff, 0xc89a, 0x21, 0 - .dw 0xf840, 0xc89a, 0xf87f, 0xc89a, 0x21, 0 - .dw 0xf8c0, 0xc89a, 0xf8ff, 0xc89a, 0x21, 0 - .dw 0xf940, 0xc89a, 0xf97f, 0xc89a, 0x21, 0 - .dw 0xf9c0, 0xc89a, 0xffff, 0xc89b, 0x21, 0 - .dw 0x0040, 0xc89c, 0x007f, 0xc89c, 0x21, 0 - .dw 0x00c0, 0xc89c, 0x00ff, 0xc89c, 0x21, 0 - .dw 0x0140, 0xc89c, 0x017f, 0xc89c, 0x21, 0 - .dw 0x01c0, 0xc89c, 0x01ff, 0xc89c, 0x21, 0 - .dw 0x0240, 0xc89c, 0x027f, 0xc89c, 0x21, 0 - .dw 0x02c0, 0xc89c, 0x02ff, 0xc89c, 0x21, 0 - .dw 0x0340, 0xc89c, 0x037f, 0xc89c, 0x21, 0 - .dw 0x03c0, 0xc89c, 0x03ff, 0xc89c, 0x21, 0 - .dw 0x0440, 0xc89c, 0x047f, 0xc89c, 0x21, 0 - .dw 0x04c0, 0xc89c, 0x04ff, 0xc89c, 0x21, 0 - .dw 0x0540, 0xc89c, 0x057f, 0xc89c, 0x21, 0 - .dw 0x05c0, 0xc89c, 0x05ff, 0xc89c, 0x21, 0 - .dw 0x0640, 0xc89c, 0x067f, 0xc89c, 0x21, 0 - .dw 0x06c0, 0xc89c, 0x06ff, 0xc89c, 0x21, 0 - .dw 0x0740, 0xc89c, 0x077f, 0xc89c, 0x21, 0 - .dw 0x07c0, 0xc89c, 0x07ff, 0xc89c, 0x21, 0 - .dw 0x0840, 0xc89c, 0x087f, 0xc89c, 0x21, 0 - .dw 0x08c0, 0xc89c, 0x08ff, 0xc89c, 0x21, 0 - .dw 0x0940, 0xc89c, 0x097f, 0xc89c, 0x21, 0 - .dw 0x09c0, 0xc89c, 0x09ff, 0xc89c, 0x21, 0 - .dw 0x0a40, 0xc89c, 0x0a7f, 0xc89c, 0x21, 0 - .dw 0x0ac0, 0xc89c, 0x0aff, 0xc89c, 0x21, 0 - .dw 0x0b40, 0xc89c, 0x0b7f, 0xc89c, 0x21, 0 - .dw 0x0bc0, 0xc89c, 0x0bff, 0xc89c, 0x21, 0 - .dw 0x0c40, 0xc89c, 0x0c7f, 0xc89c, 0x21, 0 - .dw 0x0cc0, 0xc89c, 0x0cff, 0xc89c, 0x21, 0 - .dw 0x0d40, 0xc89c, 0x0d7f, 0xc89c, 0x21, 0 - .dw 0x0dc0, 0xc89c, 0x0dff, 0xc89c, 0x21, 0 - .dw 0x0e40, 0xc89c, 0x0e7f, 0xc89c, 0x21, 0 - .dw 0x0ec0, 0xc89c, 0x0eff, 0xc89c, 0x21, 0 - .dw 0x0f40, 0xc89c, 0x0f7f, 0xc89c, 0x21, 0 - .dw 0x0fc0, 0xc89c, 0x0fff, 0xc89c, 0x21, 0 - .dw 0x1040, 0xc89c, 0x107f, 0xc89c, 0x21, 0 - .dw 0x10c0, 0xc89c, 0x10ff, 0xc89c, 0x21, 0 - .dw 0x1140, 0xc89c, 0x117f, 0xc89c, 0x21, 0 - .dw 0x11c0, 0xc89c, 0x11ff, 0xc89c, 0x21, 0 - .dw 0x1240, 0xc89c, 0x127f, 0xc89c, 0x21, 0 - .dw 0x12c0, 0xc89c, 0x12ff, 0xc89c, 0x21, 0 - .dw 0x1340, 0xc89c, 0x137f, 0xc89c, 0x21, 0 - .dw 0x13c0, 0xc89c, 0x13ff, 0xc89c, 0x21, 0 - .dw 0x1440, 0xc89c, 0x147f, 0xc89c, 0x21, 0 - .dw 0x14c0, 0xc89c, 0x14ff, 0xc89c, 0x21, 0 - .dw 0x1540, 0xc89c, 0x157f, 0xc89c, 0x21, 0 - .dw 0x15c0, 0xc89c, 0x15ff, 0xc89c, 0x21, 0 - .dw 0x1640, 0xc89c, 0x167f, 0xc89c, 0x21, 0 - .dw 0x16c0, 0xc89c, 0x16ff, 0xc89c, 0x21, 0 - .dw 0x1740, 0xc89c, 0x177f, 0xc89c, 0x21, 0 - .dw 0x17c0, 0xc89c, 0x17ff, 0xc89c, 0x21, 0 - .dw 0x1840, 0xc89c, 0x187f, 0xc89c, 0x21, 0 - .dw 0x18c0, 0xc89c, 0x18ff, 0xc89c, 0x21, 0 - .dw 0x1940, 0xc89c, 0x197f, 0xc89c, 0x21, 0 - .dw 0x19c0, 0xc89c, 0x1fff, 0xc89c, 0x21, 0 - .dw 0x2040, 0xc89c, 0x207f, 0xc89c, 0x21, 0 - .dw 0x20c0, 0xc89c, 0x20ff, 0xc89c, 0x21, 0 - .dw 0x2140, 0xc89c, 0x217f, 0xc89c, 0x21, 0 - .dw 0x21c0, 0xc89c, 0x21ff, 0xc89c, 0x21, 0 - .dw 0x2240, 0xc89c, 0x227f, 0xc89c, 0x21, 0 - .dw 0x22c0, 0xc89c, 0x22ff, 0xc89c, 0x21, 0 - .dw 0x2340, 0xc89c, 0x237f, 0xc89c, 0x21, 0 - .dw 0x23c0, 0xc89c, 0x23ff, 0xc89c, 0x21, 0 - .dw 0x2440, 0xc89c, 0x247f, 0xc89c, 0x21, 0 - .dw 0x24c0, 0xc89c, 0x24ff, 0xc89c, 0x21, 0 - .dw 0x2540, 0xc89c, 0x257f, 0xc89c, 0x21, 0 - .dw 0x25c0, 0xc89c, 0x25ff, 0xc89c, 0x21, 0 - .dw 0x2640, 0xc89c, 0x267f, 0xc89c, 0x21, 0 - .dw 0x26c0, 0xc89c, 0x26ff, 0xc89c, 0x21, 0 - .dw 0x2740, 0xc89c, 0x277f, 0xc89c, 0x21, 0 - .dw 0x27c0, 0xc89c, 0x27ff, 0xc89c, 0x21, 0 - .dw 0x2840, 0xc89c, 0x287f, 0xc89c, 0x21, 0 - .dw 0x28c0, 0xc89c, 0x28ff, 0xc89c, 0x21, 0 - .dw 0x2940, 0xc89c, 0x297f, 0xc89c, 0x21, 0 - .dw 0x29c0, 0xc89c, 0x29ff, 0xc89c, 0x21, 0 - .dw 0x2a40, 0xc89c, 0x2a7f, 0xc89c, 0x21, 0 - .dw 0x2ac0, 0xc89c, 0x2aff, 0xc89c, 0x21, 0 - .dw 0x2b40, 0xc89c, 0x2b7f, 0xc89c, 0x21, 0 - .dw 0x2bc0, 0xc89c, 0x2bff, 0xc89c, 0x21, 0 - .dw 0x2c40, 0xc89c, 0x2c7f, 0xc89c, 0x21, 0 - .dw 0x2cc0, 0xc89c, 0x2cff, 0xc89c, 0x21, 0 - .dw 0x2d40, 0xc89c, 0x2d7f, 0xc89c, 0x21, 0 - .dw 0x2dc0, 0xc89c, 0x2dff, 0xc89c, 0x21, 0 - .dw 0x2e40, 0xc89c, 0x2e7f, 0xc89c, 0x21, 0 - .dw 0x2ec0, 0xc89c, 0x2eff, 0xc89c, 0x21, 0 - .dw 0x2f40, 0xc89c, 0x2f7f, 0xc89c, 0x21, 0 - .dw 0x2fc0, 0xc89c, 0x2fff, 0xc89c, 0x21, 0 - .dw 0x3040, 0xc89c, 0x307f, 0xc89c, 0x21, 0 - .dw 0x30c0, 0xc89c, 0x30ff, 0xc89c, 0x21, 0 - .dw 0x3140, 0xc89c, 0x317f, 0xc89c, 0x21, 0 - .dw 0x31c0, 0xc89c, 0x31ff, 0xc89c, 0x21, 0 - .dw 0x3240, 0xc89c, 0x327f, 0xc89c, 0x21, 0 - .dw 0x32c0, 0xc89c, 0x32ff, 0xc89c, 0x21, 0 - .dw 0x3340, 0xc89c, 0x337f, 0xc89c, 0x21, 0 - .dw 0x33c0, 0xc89c, 0x33ff, 0xc89c, 0x21, 0 - .dw 0x3440, 0xc89c, 0x347f, 0xc89c, 0x21, 0 - .dw 0x34c0, 0xc89c, 0x34ff, 0xc89c, 0x21, 0 - .dw 0x3540, 0xc89c, 0x357f, 0xc89c, 0x21, 0 - .dw 0x35c0, 0xc89c, 0x35ff, 0xc89c, 0x21, 0 - .dw 0x3640, 0xc89c, 0x367f, 0xc89c, 0x21, 0 - .dw 0x36c0, 0xc89c, 0x36ff, 0xc89c, 0x21, 0 - .dw 0x3740, 0xc89c, 0x377f, 0xc89c, 0x21, 0 - .dw 0x37c0, 0xc89c, 0x37ff, 0xc89c, 0x21, 0 - .dw 0x3840, 0xc89c, 0x387f, 0xc89c, 0x21, 0 - .dw 0x38c0, 0xc89c, 0x38ff, 0xc89c, 0x21, 0 - .dw 0x3940, 0xc89c, 0x397f, 0xc89c, 0x21, 0 - .dw 0x39c0, 0xc89c, 0x3fff, 0xc89c, 0x21, 0 - .dw 0x4040, 0xc89c, 0x407f, 0xc89c, 0x21, 0 - .dw 0x40c0, 0xc89c, 0x40ff, 0xc89c, 0x21, 0 - .dw 0x4140, 0xc89c, 0x417f, 0xc89c, 0x21, 0 - .dw 0x41c0, 0xc89c, 0x41ff, 0xc89c, 0x21, 0 - .dw 0x4240, 0xc89c, 0x427f, 0xc89c, 0x21, 0 - .dw 0x42c0, 0xc89c, 0x42ff, 0xc89c, 0x21, 0 - .dw 0x4340, 0xc89c, 0x437f, 0xc89c, 0x21, 0 - .dw 0x43c0, 0xc89c, 0x43ff, 0xc89c, 0x21, 0 - .dw 0x4440, 0xc89c, 0x447f, 0xc89c, 0x21, 0 - .dw 0x44c0, 0xc89c, 0x44ff, 0xc89c, 0x21, 0 - .dw 0x4540, 0xc89c, 0x457f, 0xc89c, 0x21, 0 - .dw 0x45c0, 0xc89c, 0x45ff, 0xc89c, 0x21, 0 - .dw 0x4640, 0xc89c, 0x467f, 0xc89c, 0x21, 0 - .dw 0x46c0, 0xc89c, 0x46ff, 0xc89c, 0x21, 0 - .dw 0x4740, 0xc89c, 0x477f, 0xc89c, 0x21, 0 - .dw 0x47c0, 0xc89c, 0x47ff, 0xc89c, 0x21, 0 - .dw 0x4840, 0xc89c, 0x487f, 0xc89c, 0x21, 0 - .dw 0x48c0, 0xc89c, 0x48ff, 0xc89c, 0x21, 0 - .dw 0x4940, 0xc89c, 0x497f, 0xc89c, 0x21, 0 - .dw 0x49c0, 0xc89c, 0x49ff, 0xc89c, 0x21, 0 - .dw 0x4a40, 0xc89c, 0x4a7f, 0xc89c, 0x21, 0 - .dw 0x4ac0, 0xc89c, 0x4aff, 0xc89c, 0x21, 0 - .dw 0x4b40, 0xc89c, 0x4b7f, 0xc89c, 0x21, 0 - .dw 0x4bc0, 0xc89c, 0x4bff, 0xc89c, 0x21, 0 - .dw 0x4c40, 0xc89c, 0x4c7f, 0xc89c, 0x21, 0 - .dw 0x4cc0, 0xc89c, 0x4cff, 0xc89c, 0x21, 0 - .dw 0x4d40, 0xc89c, 0x4d7f, 0xc89c, 0x21, 0 - .dw 0x4dc0, 0xc89c, 0x4dff, 0xc89c, 0x21, 0 - .dw 0x4e40, 0xc89c, 0x4e7f, 0xc89c, 0x21, 0 - .dw 0x4ec0, 0xc89c, 0x4eff, 0xc89c, 0x21, 0 - .dw 0x4f40, 0xc89c, 0x4f7f, 0xc89c, 0x21, 0 - .dw 0x4fc0, 0xc89c, 0x4fff, 0xc89c, 0x21, 0 - .dw 0x5040, 0xc89c, 0x507f, 0xc89c, 0x21, 0 - .dw 0x50c0, 0xc89c, 0x50ff, 0xc89c, 0x21, 0 - .dw 0x5140, 0xc89c, 0x517f, 0xc89c, 0x21, 0 - .dw 0x51c0, 0xc89c, 0x51ff, 0xc89c, 0x21, 0 - .dw 0x5240, 0xc89c, 0x527f, 0xc89c, 0x21, 0 - .dw 0x52c0, 0xc89c, 0x52ff, 0xc89c, 0x21, 0 - .dw 0x5340, 0xc89c, 0x537f, 0xc89c, 0x21, 0 - .dw 0x53c0, 0xc89c, 0x53ff, 0xc89c, 0x21, 0 - .dw 0x5440, 0xc89c, 0x547f, 0xc89c, 0x21, 0 - .dw 0x54c0, 0xc89c, 0x54ff, 0xc89c, 0x21, 0 - .dw 0x5540, 0xc89c, 0x557f, 0xc89c, 0x21, 0 - .dw 0x55c0, 0xc89c, 0x55ff, 0xc89c, 0x21, 0 - .dw 0x5640, 0xc89c, 0x567f, 0xc89c, 0x21, 0 - .dw 0x56c0, 0xc89c, 0x56ff, 0xc89c, 0x21, 0 - .dw 0x5740, 0xc89c, 0x577f, 0xc89c, 0x21, 0 - .dw 0x57c0, 0xc89c, 0x57ff, 0xc89c, 0x21, 0 - .dw 0x5840, 0xc89c, 0x587f, 0xc89c, 0x21, 0 - .dw 0x58c0, 0xc89c, 0x58ff, 0xc89c, 0x21, 0 - .dw 0x5940, 0xc89c, 0x597f, 0xc89c, 0x21, 0 - .dw 0x59c0, 0xc89c, 0x5fff, 0xc89c, 0x21, 0 - .dw 0x6040, 0xc89c, 0x607f, 0xc89c, 0x21, 0 - .dw 0x60c0, 0xc89c, 0x60ff, 0xc89c, 0x21, 0 - .dw 0x6140, 0xc89c, 0x617f, 0xc89c, 0x21, 0 - .dw 0x61c0, 0xc89c, 0x61ff, 0xc89c, 0x21, 0 - .dw 0x6240, 0xc89c, 0x627f, 0xc89c, 0x21, 0 - .dw 0x62c0, 0xc89c, 0x62ff, 0xc89c, 0x21, 0 - .dw 0x6340, 0xc89c, 0x637f, 0xc89c, 0x21, 0 - .dw 0x63c0, 0xc89c, 0x63ff, 0xc89c, 0x21, 0 - .dw 0x6440, 0xc89c, 0x647f, 0xc89c, 0x21, 0 - .dw 0x64c0, 0xc89c, 0x64ff, 0xc89c, 0x21, 0 - .dw 0x6540, 0xc89c, 0x657f, 0xc89c, 0x21, 0 - .dw 0x65c0, 0xc89c, 0x65ff, 0xc89c, 0x21, 0 - .dw 0x6640, 0xc89c, 0x667f, 0xc89c, 0x21, 0 - .dw 0x66c0, 0xc89c, 0x66ff, 0xc89c, 0x21, 0 - .dw 0x6740, 0xc89c, 0x677f, 0xc89c, 0x21, 0 - .dw 0x67c0, 0xc89c, 0x67ff, 0xc89c, 0x21, 0 - .dw 0x6840, 0xc89c, 0x687f, 0xc89c, 0x21, 0 - .dw 0x68c0, 0xc89c, 0x68ff, 0xc89c, 0x21, 0 - .dw 0x6940, 0xc89c, 0x697f, 0xc89c, 0x21, 0 - .dw 0x69c0, 0xc89c, 0x69ff, 0xc89c, 0x21, 0 - .dw 0x6a40, 0xc89c, 0x6a7f, 0xc89c, 0x21, 0 - .dw 0x6ac0, 0xc89c, 0x6aff, 0xc89c, 0x21, 0 - .dw 0x6b40, 0xc89c, 0x6b7f, 0xc89c, 0x21, 0 - .dw 0x6bc0, 0xc89c, 0x6bff, 0xc89c, 0x21, 0 - .dw 0x6c40, 0xc89c, 0x6c7f, 0xc89c, 0x21, 0 - .dw 0x6cc0, 0xc89c, 0x6cff, 0xc89c, 0x21, 0 - .dw 0x6d40, 0xc89c, 0x6d7f, 0xc89c, 0x21, 0 - .dw 0x6dc0, 0xc89c, 0x6dff, 0xc89c, 0x21, 0 - .dw 0x6e40, 0xc89c, 0x6e7f, 0xc89c, 0x21, 0 - .dw 0x6ec0, 0xc89c, 0x6eff, 0xc89c, 0x21, 0 - .dw 0x6f40, 0xc89c, 0x6f7f, 0xc89c, 0x21, 0 - .dw 0x6fc0, 0xc89c, 0x6fff, 0xc89c, 0x21, 0 - .dw 0x7040, 0xc89c, 0x707f, 0xc89c, 0x21, 0 - .dw 0x70c0, 0xc89c, 0x70ff, 0xc89c, 0x21, 0 - .dw 0x7140, 0xc89c, 0x717f, 0xc89c, 0x21, 0 - .dw 0x71c0, 0xc89c, 0x71ff, 0xc89c, 0x21, 0 - .dw 0x7240, 0xc89c, 0x727f, 0xc89c, 0x21, 0 - .dw 0x72c0, 0xc89c, 0x72ff, 0xc89c, 0x21, 0 - .dw 0x7340, 0xc89c, 0x737f, 0xc89c, 0x21, 0 - .dw 0x73c0, 0xc89c, 0x73ff, 0xc89c, 0x21, 0 - .dw 0x7440, 0xc89c, 0x747f, 0xc89c, 0x21, 0 - .dw 0x74c0, 0xc89c, 0x74ff, 0xc89c, 0x21, 0 - .dw 0x7540, 0xc89c, 0x757f, 0xc89c, 0x21, 0 - .dw 0x75c0, 0xc89c, 0x75ff, 0xc89c, 0x21, 0 - .dw 0x7640, 0xc89c, 0x767f, 0xc89c, 0x21, 0 - .dw 0x76c0, 0xc89c, 0x76ff, 0xc89c, 0x21, 0 - .dw 0x7740, 0xc89c, 0x777f, 0xc89c, 0x21, 0 - .dw 0x77c0, 0xc89c, 0x77ff, 0xc89c, 0x21, 0 - .dw 0x7840, 0xc89c, 0x787f, 0xc89c, 0x21, 0 - .dw 0x78c0, 0xc89c, 0x78ff, 0xc89c, 0x21, 0 - .dw 0x7940, 0xc89c, 0x797f, 0xc89c, 0x21, 0 - .dw 0x79c0, 0xc89c, 0x7fff, 0xc89c, 0x21, 0 - .dw 0x8040, 0xc89c, 0x807f, 0xc89c, 0x21, 0 - .dw 0x80c0, 0xc89c, 0x80ff, 0xc89c, 0x21, 0 - .dw 0x8140, 0xc89c, 0x817f, 0xc89c, 0x21, 0 - .dw 0x81c0, 0xc89c, 0x81ff, 0xc89c, 0x21, 0 - .dw 0x8240, 0xc89c, 0x827f, 0xc89c, 0x21, 0 - .dw 0x82c0, 0xc89c, 0x82ff, 0xc89c, 0x21, 0 - .dw 0x8340, 0xc89c, 0x837f, 0xc89c, 0x21, 0 - .dw 0x83c0, 0xc89c, 0x83ff, 0xc89c, 0x21, 0 - .dw 0x8440, 0xc89c, 0x847f, 0xc89c, 0x21, 0 - .dw 0x84c0, 0xc89c, 0x84ff, 0xc89c, 0x21, 0 - .dw 0x8540, 0xc89c, 0x857f, 0xc89c, 0x21, 0 - .dw 0x85c0, 0xc89c, 0x85ff, 0xc89c, 0x21, 0 - .dw 0x8640, 0xc89c, 0x867f, 0xc89c, 0x21, 0 - .dw 0x86c0, 0xc89c, 0x86ff, 0xc89c, 0x21, 0 - .dw 0x8740, 0xc89c, 0x877f, 0xc89c, 0x21, 0 - .dw 0x87c0, 0xc89c, 0x87ff, 0xc89c, 0x21, 0 - .dw 0x8840, 0xc89c, 0x887f, 0xc89c, 0x21, 0 - .dw 0x88c0, 0xc89c, 0x88ff, 0xc89c, 0x21, 0 - .dw 0x8940, 0xc89c, 0x897f, 0xc89c, 0x21, 0 - .dw 0x89c0, 0xc89c, 0x89ff, 0xc89c, 0x21, 0 - .dw 0x8a40, 0xc89c, 0x8a7f, 0xc89c, 0x21, 0 - .dw 0x8ac0, 0xc89c, 0x8aff, 0xc89c, 0x21, 0 - .dw 0x8b40, 0xc89c, 0x8b7f, 0xc89c, 0x21, 0 - .dw 0x8bc0, 0xc89c, 0x8bff, 0xc89c, 0x21, 0 - .dw 0x8c40, 0xc89c, 0x8c7f, 0xc89c, 0x21, 0 - .dw 0x8cc0, 0xc89c, 0x8cff, 0xc89c, 0x21, 0 - .dw 0x8d40, 0xc89c, 0x8d7f, 0xc89c, 0x21, 0 - .dw 0x8dc0, 0xc89c, 0x8dff, 0xc89c, 0x21, 0 - .dw 0x8e40, 0xc89c, 0x8e7f, 0xc89c, 0x21, 0 - .dw 0x8ec0, 0xc89c, 0x8eff, 0xc89c, 0x21, 0 - .dw 0x8f40, 0xc89c, 0x8f7f, 0xc89c, 0x21, 0 - .dw 0x8fc0, 0xc89c, 0x8fff, 0xc89c, 0x21, 0 - .dw 0x9040, 0xc89c, 0x907f, 0xc89c, 0x21, 0 - .dw 0x90c0, 0xc89c, 0x90ff, 0xc89c, 0x21, 0 - .dw 0x9140, 0xc89c, 0x917f, 0xc89c, 0x21, 0 - .dw 0x91c0, 0xc89c, 0x91ff, 0xc89c, 0x21, 0 - .dw 0x9240, 0xc89c, 0x927f, 0xc89c, 0x21, 0 - .dw 0x92c0, 0xc89c, 0x92ff, 0xc89c, 0x21, 0 - .dw 0x9340, 0xc89c, 0x937f, 0xc89c, 0x21, 0 - .dw 0x93c0, 0xc89c, 0x93ff, 0xc89c, 0x21, 0 - .dw 0x9440, 0xc89c, 0x947f, 0xc89c, 0x21, 0 - .dw 0x94c0, 0xc89c, 0x94ff, 0xc89c, 0x21, 0 - .dw 0x9540, 0xc89c, 0x957f, 0xc89c, 0x21, 0 - .dw 0x95c0, 0xc89c, 0x95ff, 0xc89c, 0x21, 0 - .dw 0x9640, 0xc89c, 0x967f, 0xc89c, 0x21, 0 - .dw 0x96c0, 0xc89c, 0x96ff, 0xc89c, 0x21, 0 - .dw 0x9740, 0xc89c, 0x977f, 0xc89c, 0x21, 0 - .dw 0x97c0, 0xc89c, 0x97ff, 0xc89c, 0x21, 0 - .dw 0x9840, 0xc89c, 0x987f, 0xc89c, 0x21, 0 - .dw 0x98c0, 0xc89c, 0x98ff, 0xc89c, 0x21, 0 - .dw 0x9940, 0xc89c, 0x997f, 0xc89c, 0x21, 0 - .dw 0x99c0, 0xc89c, 0x9fff, 0xc89c, 0x21, 0 - .dw 0xa040, 0xc89c, 0xa07f, 0xc89c, 0x21, 0 - .dw 0xa0c0, 0xc89c, 0xa0ff, 0xc89c, 0x21, 0 - .dw 0xa140, 0xc89c, 0xa17f, 0xc89c, 0x21, 0 - .dw 0xa1c0, 0xc89c, 0xa1ff, 0xc89c, 0x21, 0 - .dw 0xa240, 0xc89c, 0xa27f, 0xc89c, 0x21, 0 - .dw 0xa2c0, 0xc89c, 0xa2ff, 0xc89c, 0x21, 0 - .dw 0xa340, 0xc89c, 0xa37f, 0xc89c, 0x21, 0 - .dw 0xa3c0, 0xc89c, 0xa3ff, 0xc89c, 0x21, 0 - .dw 0xa440, 0xc89c, 0xa47f, 0xc89c, 0x21, 0 - .dw 0xa4c0, 0xc89c, 0xa4ff, 0xc89c, 0x21, 0 - .dw 0xa540, 0xc89c, 0xa57f, 0xc89c, 0x21, 0 - .dw 0xa5c0, 0xc89c, 0xa5ff, 0xc89c, 0x21, 0 - .dw 0xa640, 0xc89c, 0xa67f, 0xc89c, 0x21, 0 - .dw 0xa6c0, 0xc89c, 0xa6ff, 0xc89c, 0x21, 0 - .dw 0xa740, 0xc89c, 0xa77f, 0xc89c, 0x21, 0 - .dw 0xa7c0, 0xc89c, 0xa7ff, 0xc89c, 0x21, 0 - .dw 0xa840, 0xc89c, 0xa87f, 0xc89c, 0x21, 0 - .dw 0xa8c0, 0xc89c, 0xa8ff, 0xc89c, 0x21, 0 - .dw 0xa940, 0xc89c, 0xa97f, 0xc89c, 0x21, 0 - .dw 0xa9c0, 0xc89c, 0xa9ff, 0xc89c, 0x21, 0 - .dw 0xaa40, 0xc89c, 0xaa7f, 0xc89c, 0x21, 0 - .dw 0xaac0, 0xc89c, 0xaaff, 0xc89c, 0x21, 0 - .dw 0xab40, 0xc89c, 0xab7f, 0xc89c, 0x21, 0 - .dw 0xabc0, 0xc89c, 0xabff, 0xc89c, 0x21, 0 - .dw 0xac40, 0xc89c, 0xac7f, 0xc89c, 0x21, 0 - .dw 0xacc0, 0xc89c, 0xacff, 0xc89c, 0x21, 0 - .dw 0xad40, 0xc89c, 0xad7f, 0xc89c, 0x21, 0 - .dw 0xadc0, 0xc89c, 0xadff, 0xc89c, 0x21, 0 - .dw 0xae40, 0xc89c, 0xae7f, 0xc89c, 0x21, 0 - .dw 0xaec0, 0xc89c, 0xaeff, 0xc89c, 0x21, 0 - .dw 0xaf40, 0xc89c, 0xaf7f, 0xc89c, 0x21, 0 - .dw 0xafc0, 0xc89c, 0xafff, 0xc89c, 0x21, 0 - .dw 0xb040, 0xc89c, 0xb07f, 0xc89c, 0x21, 0 - .dw 0xb0c0, 0xc89c, 0xb0ff, 0xc89c, 0x21, 0 - .dw 0xb140, 0xc89c, 0xb17f, 0xc89c, 0x21, 0 - .dw 0xb1c0, 0xc89c, 0xb1ff, 0xc89c, 0x21, 0 - .dw 0xb240, 0xc89c, 0xb27f, 0xc89c, 0x21, 0 - .dw 0xb2c0, 0xc89c, 0xb2ff, 0xc89c, 0x21, 0 - .dw 0xb340, 0xc89c, 0xb37f, 0xc89c, 0x21, 0 - .dw 0xb3c0, 0xc89c, 0xb3ff, 0xc89c, 0x21, 0 - .dw 0xb440, 0xc89c, 0xb47f, 0xc89c, 0x21, 0 - .dw 0xb4c0, 0xc89c, 0xb4ff, 0xc89c, 0x21, 0 - .dw 0xb540, 0xc89c, 0xb57f, 0xc89c, 0x21, 0 - .dw 0xb5c0, 0xc89c, 0xb5ff, 0xc89c, 0x21, 0 - .dw 0xb640, 0xc89c, 0xb67f, 0xc89c, 0x21, 0 - .dw 0xb6c0, 0xc89c, 0xb6ff, 0xc89c, 0x21, 0 - .dw 0xb740, 0xc89c, 0xb77f, 0xc89c, 0x21, 0 - .dw 0xb7c0, 0xc89c, 0xb7ff, 0xc89c, 0x21, 0 - .dw 0xb840, 0xc89c, 0xb87f, 0xc89c, 0x21, 0 - .dw 0xb8c0, 0xc89c, 0xb8ff, 0xc89c, 0x21, 0 - .dw 0xb940, 0xc89c, 0xb97f, 0xc89c, 0x21, 0 - .dw 0xb9c0, 0xc89c, 0xbfff, 0xc89c, 0x21, 0 - .dw 0xc040, 0xc89c, 0xc07f, 0xc89c, 0x21, 0 - .dw 0xc0c0, 0xc89c, 0xc0ff, 0xc89c, 0x21, 0 - .dw 0xc140, 0xc89c, 0xc17f, 0xc89c, 0x21, 0 - .dw 0xc1c0, 0xc89c, 0xc1ff, 0xc89c, 0x21, 0 - .dw 0xc240, 0xc89c, 0xc27f, 0xc89c, 0x21, 0 - .dw 0xc2c0, 0xc89c, 0xc2ff, 0xc89c, 0x21, 0 - .dw 0xc340, 0xc89c, 0xc37f, 0xc89c, 0x21, 0 - .dw 0xc3c0, 0xc89c, 0xc3ff, 0xc89c, 0x21, 0 - .dw 0xc440, 0xc89c, 0xc47f, 0xc89c, 0x21, 0 - .dw 0xc4c0, 0xc89c, 0xc4ff, 0xc89c, 0x21, 0 - .dw 0xc540, 0xc89c, 0xc57f, 0xc89c, 0x21, 0 - .dw 0xc5c0, 0xc89c, 0xc5ff, 0xc89c, 0x21, 0 - .dw 0xc640, 0xc89c, 0xc67f, 0xc89c, 0x21, 0 - .dw 0xc6c0, 0xc89c, 0xc6ff, 0xc89c, 0x21, 0 - .dw 0xc740, 0xc89c, 0xc77f, 0xc89c, 0x21, 0 - .dw 0xc7c0, 0xc89c, 0xc7ff, 0xc89c, 0x21, 0 - .dw 0xc840, 0xc89c, 0xc87f, 0xc89c, 0x21, 0 - .dw 0xc8c0, 0xc89c, 0xc8ff, 0xc89c, 0x21, 0 - .dw 0xc940, 0xc89c, 0xc97f, 0xc89c, 0x21, 0 - .dw 0xc9c0, 0xc89c, 0xc9ff, 0xc89c, 0x21, 0 - .dw 0xca40, 0xc89c, 0xca7f, 0xc89c, 0x21, 0 - .dw 0xcac0, 0xc89c, 0xcaff, 0xc89c, 0x21, 0 - .dw 0xcb40, 0xc89c, 0xcb7f, 0xc89c, 0x21, 0 - .dw 0xcbc0, 0xc89c, 0xcbff, 0xc89c, 0x21, 0 - .dw 0xcc40, 0xc89c, 0xcc7f, 0xc89c, 0x21, 0 - .dw 0xccc0, 0xc89c, 0xccff, 0xc89c, 0x21, 0 - .dw 0xcd40, 0xc89c, 0xcd7f, 0xc89c, 0x21, 0 - .dw 0xcdc0, 0xc89c, 0xcdff, 0xc89c, 0x21, 0 - .dw 0xce40, 0xc89c, 0xce7f, 0xc89c, 0x21, 0 - .dw 0xcec0, 0xc89c, 0xceff, 0xc89c, 0x21, 0 - .dw 0xcf40, 0xc89c, 0xcf7f, 0xc89c, 0x21, 0 - .dw 0xcfc0, 0xc89c, 0xcfff, 0xc89c, 0x21, 0 - .dw 0xd040, 0xc89c, 0xd07f, 0xc89c, 0x21, 0 - .dw 0xd0c0, 0xc89c, 0xd0ff, 0xc89c, 0x21, 0 - .dw 0xd140, 0xc89c, 0xd17f, 0xc89c, 0x21, 0 - .dw 0xd1c0, 0xc89c, 0xd1ff, 0xc89c, 0x21, 0 - .dw 0xd240, 0xc89c, 0xd27f, 0xc89c, 0x21, 0 - .dw 0xd2c0, 0xc89c, 0xd2ff, 0xc89c, 0x21, 0 - .dw 0xd340, 0xc89c, 0xd37f, 0xc89c, 0x21, 0 - .dw 0xd3c0, 0xc89c, 0xd3ff, 0xc89c, 0x21, 0 - .dw 0xd440, 0xc89c, 0xd47f, 0xc89c, 0x21, 0 - .dw 0xd4c0, 0xc89c, 0xd4ff, 0xc89c, 0x21, 0 - .dw 0xd540, 0xc89c, 0xd57f, 0xc89c, 0x21, 0 - .dw 0xd5c0, 0xc89c, 0xd5ff, 0xc89c, 0x21, 0 - .dw 0xd640, 0xc89c, 0xd67f, 0xc89c, 0x21, 0 - .dw 0xd6c0, 0xc89c, 0xd6ff, 0xc89c, 0x21, 0 - .dw 0xd740, 0xc89c, 0xd77f, 0xc89c, 0x21, 0 - .dw 0xd7c0, 0xc89c, 0xd7ff, 0xc89c, 0x21, 0 - .dw 0xd840, 0xc89c, 0xd87f, 0xc89c, 0x21, 0 - .dw 0xd8c0, 0xc89c, 0xd8ff, 0xc89c, 0x21, 0 - .dw 0xd940, 0xc89c, 0xd97f, 0xc89c, 0x21, 0 - .dw 0xd9c0, 0xc89c, 0xdfff, 0xc89c, 0x21, 0 - .dw 0xe040, 0xc89c, 0xe07f, 0xc89c, 0x21, 0 - .dw 0xe0c0, 0xc89c, 0xe0ff, 0xc89c, 0x21, 0 - .dw 0xe140, 0xc89c, 0xe17f, 0xc89c, 0x21, 0 - .dw 0xe1c0, 0xc89c, 0xe1ff, 0xc89c, 0x21, 0 - .dw 0xe240, 0xc89c, 0xe27f, 0xc89c, 0x21, 0 - .dw 0xe2c0, 0xc89c, 0xe2ff, 0xc89c, 0x21, 0 - .dw 0xe340, 0xc89c, 0xe37f, 0xc89c, 0x21, 0 - .dw 0xe3c0, 0xc89c, 0xe3ff, 0xc89c, 0x21, 0 - .dw 0xe440, 0xc89c, 0xe47f, 0xc89c, 0x21, 0 - .dw 0xe4c0, 0xc89c, 0xe4ff, 0xc89c, 0x21, 0 - .dw 0xe540, 0xc89c, 0xe57f, 0xc89c, 0x21, 0 - .dw 0xe5c0, 0xc89c, 0xe5ff, 0xc89c, 0x21, 0 - .dw 0xe640, 0xc89c, 0xe67f, 0xc89c, 0x21, 0 - .dw 0xe6c0, 0xc89c, 0xe6ff, 0xc89c, 0x21, 0 - .dw 0xe740, 0xc89c, 0xe77f, 0xc89c, 0x21, 0 - .dw 0xe7c0, 0xc89c, 0xe7ff, 0xc89c, 0x21, 0 - .dw 0xe840, 0xc89c, 0xe87f, 0xc89c, 0x21, 0 - .dw 0xe8c0, 0xc89c, 0xe8ff, 0xc89c, 0x21, 0 - .dw 0xe940, 0xc89c, 0xe97f, 0xc89c, 0x21, 0 - .dw 0xe9c0, 0xc89c, 0xe9ff, 0xc89c, 0x21, 0 - .dw 0xea40, 0xc89c, 0xea7f, 0xc89c, 0x21, 0 - .dw 0xeac0, 0xc89c, 0xeaff, 0xc89c, 0x21, 0 - .dw 0xeb40, 0xc89c, 0xeb7f, 0xc89c, 0x21, 0 - .dw 0xebc0, 0xc89c, 0xebff, 0xc89c, 0x21, 0 - .dw 0xec40, 0xc89c, 0xec7f, 0xc89c, 0x21, 0 - .dw 0xecc0, 0xc89c, 0xecff, 0xc89c, 0x21, 0 - .dw 0xed40, 0xc89c, 0xed7f, 0xc89c, 0x21, 0 - .dw 0xedc0, 0xc89c, 0xedff, 0xc89c, 0x21, 0 - .dw 0xee40, 0xc89c, 0xee7f, 0xc89c, 0x21, 0 - .dw 0xeec0, 0xc89c, 0xeeff, 0xc89c, 0x21, 0 - .dw 0xef40, 0xc89c, 0xef7f, 0xc89c, 0x21, 0 - .dw 0xefc0, 0xc89c, 0xefff, 0xc89c, 0x21, 0 - .dw 0xf040, 0xc89c, 0xf07f, 0xc89c, 0x21, 0 - .dw 0xf0c0, 0xc89c, 0xf0ff, 0xc89c, 0x21, 0 - .dw 0xf140, 0xc89c, 0xf17f, 0xc89c, 0x21, 0 - .dw 0xf1c0, 0xc89c, 0xf1ff, 0xc89c, 0x21, 0 - .dw 0xf240, 0xc89c, 0xf27f, 0xc89c, 0x21, 0 - .dw 0xf2c0, 0xc89c, 0xf2ff, 0xc89c, 0x21, 0 - .dw 0xf340, 0xc89c, 0xf37f, 0xc89c, 0x21, 0 - .dw 0xf3c0, 0xc89c, 0xf3ff, 0xc89c, 0x21, 0 - .dw 0xf440, 0xc89c, 0xf47f, 0xc89c, 0x21, 0 - .dw 0xf4c0, 0xc89c, 0xf4ff, 0xc89c, 0x21, 0 - .dw 0xf540, 0xc89c, 0xf57f, 0xc89c, 0x21, 0 - .dw 0xf5c0, 0xc89c, 0xf5ff, 0xc89c, 0x21, 0 - .dw 0xf640, 0xc89c, 0xf67f, 0xc89c, 0x21, 0 - .dw 0xf6c0, 0xc89c, 0xf6ff, 0xc89c, 0x21, 0 - .dw 0xf740, 0xc89c, 0xf77f, 0xc89c, 0x21, 0 - .dw 0xf7c0, 0xc89c, 0xf7ff, 0xc89c, 0x21, 0 - .dw 0xf840, 0xc89c, 0xf87f, 0xc89c, 0x21, 0 - .dw 0xf8c0, 0xc89c, 0xf8ff, 0xc89c, 0x21, 0 - .dw 0xf940, 0xc89c, 0xf97f, 0xc89c, 0x21, 0 - .dw 0xf9c0, 0xc89c, 0xffff, 0xc89c, 0x21, 0 - .dw 0x0040, 0xc89d, 0x007f, 0xc89d, 0x21, 0 - .dw 0x00c0, 0xc89d, 0x00ff, 0xc89d, 0x21, 0 - .dw 0x0140, 0xc89d, 0x017f, 0xc89d, 0x21, 0 - .dw 0x01c0, 0xc89d, 0x01ff, 0xc89d, 0x21, 0 - .dw 0x0240, 0xc89d, 0x027f, 0xc89d, 0x21, 0 - .dw 0x02c0, 0xc89d, 0x02ff, 0xc89d, 0x21, 0 - .dw 0x0340, 0xc89d, 0x037f, 0xc89d, 0x21, 0 - .dw 0x03c0, 0xc89d, 0x03ff, 0xc89d, 0x21, 0 - .dw 0x0440, 0xc89d, 0x047f, 0xc89d, 0x21, 0 - .dw 0x04c0, 0xc89d, 0x04ff, 0xc89d, 0x21, 0 - .dw 0x0540, 0xc89d, 0x057f, 0xc89d, 0x21, 0 - .dw 0x05c0, 0xc89d, 0x05ff, 0xc89d, 0x21, 0 - .dw 0x0640, 0xc89d, 0x067f, 0xc89d, 0x21, 0 - .dw 0x06c0, 0xc89d, 0x06ff, 0xc89d, 0x21, 0 - .dw 0x0740, 0xc89d, 0x077f, 0xc89d, 0x21, 0 - .dw 0x07c0, 0xc89d, 0x07ff, 0xc89d, 0x21, 0 - .dw 0x0840, 0xc89d, 0x087f, 0xc89d, 0x21, 0 - .dw 0x08c0, 0xc89d, 0x08ff, 0xc89d, 0x21, 0 - .dw 0x0940, 0xc89d, 0x097f, 0xc89d, 0x21, 0 - .dw 0x09c0, 0xc89d, 0x09ff, 0xc89d, 0x21, 0 - .dw 0x0a40, 0xc89d, 0x0a7f, 0xc89d, 0x21, 0 - .dw 0x0ac0, 0xc89d, 0x0aff, 0xc89d, 0x21, 0 - .dw 0x0b40, 0xc89d, 0x0b7f, 0xc89d, 0x21, 0 - .dw 0x0bc0, 0xc89d, 0x0bff, 0xc89d, 0x21, 0 - .dw 0x0c40, 0xc89d, 0x0c7f, 0xc89d, 0x21, 0 - .dw 0x0cc0, 0xc89d, 0x0cff, 0xc89d, 0x21, 0 - .dw 0x0d40, 0xc89d, 0x0d7f, 0xc89d, 0x21, 0 - .dw 0x0dc0, 0xc89d, 0x0dff, 0xc89d, 0x21, 0 - .dw 0x0e40, 0xc89d, 0x0e7f, 0xc89d, 0x21, 0 - .dw 0x0ec0, 0xc89d, 0x0eff, 0xc89d, 0x21, 0 - .dw 0x0f40, 0xc89d, 0x0f7f, 0xc89d, 0x21, 0 - .dw 0x0fc0, 0xc89d, 0x0fff, 0xc89d, 0x21, 0 - .dw 0x1040, 0xc89d, 0x107f, 0xc89d, 0x21, 0 - .dw 0x10c0, 0xc89d, 0x10ff, 0xc89d, 0x21, 0 - .dw 0x1140, 0xc89d, 0x117f, 0xc89d, 0x21, 0 - .dw 0x11c0, 0xc89d, 0x11ff, 0xc89d, 0x21, 0 - .dw 0x1240, 0xc89d, 0x127f, 0xc89d, 0x21, 0 - .dw 0x12c0, 0xc89d, 0x12ff, 0xc89d, 0x21, 0 - .dw 0x1340, 0xc89d, 0x137f, 0xc89d, 0x21, 0 - .dw 0x13c0, 0xc89d, 0x13ff, 0xc89d, 0x21, 0 - .dw 0x1440, 0xc89d, 0x147f, 0xc89d, 0x21, 0 - .dw 0x14c0, 0xc89d, 0x14ff, 0xc89d, 0x21, 0 - .dw 0x1540, 0xc89d, 0x157f, 0xc89d, 0x21, 0 - .dw 0x15c0, 0xc89d, 0x15ff, 0xc89d, 0x21, 0 - .dw 0x1640, 0xc89d, 0x167f, 0xc89d, 0x21, 0 - .dw 0x16c0, 0xc89d, 0x16ff, 0xc89d, 0x21, 0 - .dw 0x1740, 0xc89d, 0x177f, 0xc89d, 0x21, 0 - .dw 0x17c0, 0xc89d, 0x17ff, 0xc89d, 0x21, 0 - .dw 0x1840, 0xc89d, 0x187f, 0xc89d, 0x21, 0 - .dw 0x18c0, 0xc89d, 0x18ff, 0xc89d, 0x21, 0 - .dw 0x1940, 0xc89d, 0x197f, 0xc89d, 0x21, 0 - .dw 0x19c0, 0xc89d, 0x1fff, 0xc89d, 0x21, 0 - .dw 0x2040, 0xc89d, 0x207f, 0xc89d, 0x21, 0 - .dw 0x20c0, 0xc89d, 0x20ff, 0xc89d, 0x21, 0 - .dw 0x2140, 0xc89d, 0x217f, 0xc89d, 0x21, 0 - .dw 0x21c0, 0xc89d, 0x21ff, 0xc89d, 0x21, 0 - .dw 0x2240, 0xc89d, 0x227f, 0xc89d, 0x21, 0 - .dw 0x22c0, 0xc89d, 0x22ff, 0xc89d, 0x21, 0 - .dw 0x2340, 0xc89d, 0x237f, 0xc89d, 0x21, 0 - .dw 0x23c0, 0xc89d, 0x23ff, 0xc89d, 0x21, 0 - .dw 0x2440, 0xc89d, 0x247f, 0xc89d, 0x21, 0 - .dw 0x24c0, 0xc89d, 0x24ff, 0xc89d, 0x21, 0 - .dw 0x2540, 0xc89d, 0x257f, 0xc89d, 0x21, 0 - .dw 0x25c0, 0xc89d, 0x25ff, 0xc89d, 0x21, 0 - .dw 0x2640, 0xc89d, 0x267f, 0xc89d, 0x21, 0 - .dw 0x26c0, 0xc89d, 0x26ff, 0xc89d, 0x21, 0 - .dw 0x2740, 0xc89d, 0x277f, 0xc89d, 0x21, 0 - .dw 0x27c0, 0xc89d, 0x27ff, 0xc89d, 0x21, 0 - .dw 0x2840, 0xc89d, 0x287f, 0xc89d, 0x21, 0 - .dw 0x28c0, 0xc89d, 0x28ff, 0xc89d, 0x21, 0 - .dw 0x2940, 0xc89d, 0x297f, 0xc89d, 0x21, 0 - .dw 0x29c0, 0xc89d, 0x29ff, 0xc89d, 0x21, 0 - .dw 0x2a40, 0xc89d, 0x2a7f, 0xc89d, 0x21, 0 - .dw 0x2ac0, 0xc89d, 0x2aff, 0xc89d, 0x21, 0 - .dw 0x2b40, 0xc89d, 0x2b7f, 0xc89d, 0x21, 0 - .dw 0x2bc0, 0xc89d, 0x2bff, 0xc89d, 0x21, 0 - .dw 0x2c40, 0xc89d, 0x2c7f, 0xc89d, 0x21, 0 - .dw 0x2cc0, 0xc89d, 0x2cff, 0xc89d, 0x21, 0 - .dw 0x2d40, 0xc89d, 0x2d7f, 0xc89d, 0x21, 0 - .dw 0x2dc0, 0xc89d, 0x2dff, 0xc89d, 0x21, 0 - .dw 0x2e40, 0xc89d, 0x2e7f, 0xc89d, 0x21, 0 - .dw 0x2ec0, 0xc89d, 0x2eff, 0xc89d, 0x21, 0 - .dw 0x2f40, 0xc89d, 0x2f7f, 0xc89d, 0x21, 0 - .dw 0x2fc0, 0xc89d, 0x2fff, 0xc89d, 0x21, 0 - .dw 0x3040, 0xc89d, 0x307f, 0xc89d, 0x21, 0 - .dw 0x30c0, 0xc89d, 0x30ff, 0xc89d, 0x21, 0 - .dw 0x3140, 0xc89d, 0x317f, 0xc89d, 0x21, 0 - .dw 0x31c0, 0xc89d, 0x31ff, 0xc89d, 0x21, 0 - .dw 0x3240, 0xc89d, 0x327f, 0xc89d, 0x21, 0 - .dw 0x32c0, 0xc89d, 0x32ff, 0xc89d, 0x21, 0 - .dw 0x3340, 0xc89d, 0x337f, 0xc89d, 0x21, 0 - .dw 0x33c0, 0xc89d, 0x33ff, 0xc89d, 0x21, 0 - .dw 0x3440, 0xc89d, 0x347f, 0xc89d, 0x21, 0 - .dw 0x34c0, 0xc89d, 0x34ff, 0xc89d, 0x21, 0 - .dw 0x3540, 0xc89d, 0x357f, 0xc89d, 0x21, 0 - .dw 0x35c0, 0xc89d, 0x35ff, 0xc89d, 0x21, 0 - .dw 0x3640, 0xc89d, 0x367f, 0xc89d, 0x21, 0 - .dw 0x36c0, 0xc89d, 0x36ff, 0xc89d, 0x21, 0 - .dw 0x3740, 0xc89d, 0x377f, 0xc89d, 0x21, 0 - .dw 0x37c0, 0xc89d, 0x37ff, 0xc89d, 0x21, 0 - .dw 0x3840, 0xc89d, 0x387f, 0xc89d, 0x21, 0 - .dw 0x38c0, 0xc89d, 0x38ff, 0xc89d, 0x21, 0 - .dw 0x3940, 0xc89d, 0x397f, 0xc89d, 0x21, 0 - .dw 0x39c0, 0xc89d, 0x3fff, 0xc89d, 0x21, 0 - .dw 0x4040, 0xc89d, 0x407f, 0xc89d, 0x21, 0 - .dw 0x40c0, 0xc89d, 0x40ff, 0xc89d, 0x21, 0 - .dw 0x4140, 0xc89d, 0x417f, 0xc89d, 0x21, 0 - .dw 0x41c0, 0xc89d, 0x41ff, 0xc89d, 0x21, 0 - .dw 0x4240, 0xc89d, 0x427f, 0xc89d, 0x21, 0 - .dw 0x42c0, 0xc89d, 0x42ff, 0xc89d, 0x21, 0 - .dw 0x4340, 0xc89d, 0x437f, 0xc89d, 0x21, 0 - .dw 0x43c0, 0xc89d, 0x43ff, 0xc89d, 0x21, 0 - .dw 0x4440, 0xc89d, 0x447f, 0xc89d, 0x21, 0 - .dw 0x44c0, 0xc89d, 0x44ff, 0xc89d, 0x21, 0 - .dw 0x4540, 0xc89d, 0x457f, 0xc89d, 0x21, 0 - .dw 0x45c0, 0xc89d, 0x45ff, 0xc89d, 0x21, 0 - .dw 0x4640, 0xc89d, 0x467f, 0xc89d, 0x21, 0 - .dw 0x46c0, 0xc89d, 0x46ff, 0xc89d, 0x21, 0 - .dw 0x4740, 0xc89d, 0x477f, 0xc89d, 0x21, 0 - .dw 0x47c0, 0xc89d, 0x47ff, 0xc89d, 0x21, 0 - .dw 0x4840, 0xc89d, 0x487f, 0xc89d, 0x21, 0 - .dw 0x48c0, 0xc89d, 0x48ff, 0xc89d, 0x21, 0 - .dw 0x4940, 0xc89d, 0x497f, 0xc89d, 0x21, 0 - .dw 0x49c0, 0xc89d, 0x49ff, 0xc89d, 0x21, 0 - .dw 0x4a40, 0xc89d, 0x4a7f, 0xc89d, 0x21, 0 - .dw 0x4ac0, 0xc89d, 0x4aff, 0xc89d, 0x21, 0 - .dw 0x4b40, 0xc89d, 0x4b7f, 0xc89d, 0x21, 0 - .dw 0x4bc0, 0xc89d, 0x4bff, 0xc89d, 0x21, 0 - .dw 0x4c40, 0xc89d, 0x4c7f, 0xc89d, 0x21, 0 - .dw 0x4cc0, 0xc89d, 0x4cff, 0xc89d, 0x21, 0 - .dw 0x4d40, 0xc89d, 0x4d7f, 0xc89d, 0x21, 0 - .dw 0x4dc0, 0xc89d, 0x4dff, 0xc89d, 0x21, 0 - .dw 0x4e40, 0xc89d, 0x4e7f, 0xc89d, 0x21, 0 - .dw 0x4ec0, 0xc89d, 0x4eff, 0xc89d, 0x21, 0 - .dw 0x4f40, 0xc89d, 0x4f7f, 0xc89d, 0x21, 0 - .dw 0x4fc0, 0xc89d, 0x4fff, 0xc89d, 0x21, 0 - .dw 0x5040, 0xc89d, 0x507f, 0xc89d, 0x21, 0 - .dw 0x50c0, 0xc89d, 0x50ff, 0xc89d, 0x21, 0 - .dw 0x5140, 0xc89d, 0x517f, 0xc89d, 0x21, 0 - .dw 0x51c0, 0xc89d, 0x51ff, 0xc89d, 0x21, 0 - .dw 0x5240, 0xc89d, 0x527f, 0xc89d, 0x21, 0 - .dw 0x52c0, 0xc89d, 0x52ff, 0xc89d, 0x21, 0 - .dw 0x5340, 0xc89d, 0x537f, 0xc89d, 0x21, 0 - .dw 0x53c0, 0xc89d, 0x53ff, 0xc89d, 0x21, 0 - .dw 0x5440, 0xc89d, 0x547f, 0xc89d, 0x21, 0 - .dw 0x54c0, 0xc89d, 0x54ff, 0xc89d, 0x21, 0 - .dw 0x5540, 0xc89d, 0x557f, 0xc89d, 0x21, 0 - .dw 0x55c0, 0xc89d, 0x55ff, 0xc89d, 0x21, 0 - .dw 0x5640, 0xc89d, 0x567f, 0xc89d, 0x21, 0 - .dw 0x56c0, 0xc89d, 0x56ff, 0xc89d, 0x21, 0 - .dw 0x5740, 0xc89d, 0x577f, 0xc89d, 0x21, 0 - .dw 0x57c0, 0xc89d, 0x57ff, 0xc89d, 0x21, 0 - .dw 0x5840, 0xc89d, 0x587f, 0xc89d, 0x21, 0 - .dw 0x58c0, 0xc89d, 0x58ff, 0xc89d, 0x21, 0 - .dw 0x5940, 0xc89d, 0x597f, 0xc89d, 0x21, 0 - .dw 0x59c0, 0xc89d, 0x5fff, 0xc89d, 0x21, 0 - .dw 0x6040, 0xc89d, 0x607f, 0xc89d, 0x21, 0 - .dw 0x60c0, 0xc89d, 0x60ff, 0xc89d, 0x21, 0 - .dw 0x6140, 0xc89d, 0x617f, 0xc89d, 0x21, 0 - .dw 0x61c0, 0xc89d, 0x61ff, 0xc89d, 0x21, 0 - .dw 0x6240, 0xc89d, 0x627f, 0xc89d, 0x21, 0 - .dw 0x62c0, 0xc89d, 0x62ff, 0xc89d, 0x21, 0 - .dw 0x6340, 0xc89d, 0x637f, 0xc89d, 0x21, 0 - .dw 0x63c0, 0xc89d, 0x63ff, 0xc89d, 0x21, 0 - .dw 0x6440, 0xc89d, 0x647f, 0xc89d, 0x21, 0 - .dw 0x64c0, 0xc89d, 0x64ff, 0xc89d, 0x21, 0 - .dw 0x6540, 0xc89d, 0x657f, 0xc89d, 0x21, 0 - .dw 0x65c0, 0xc89d, 0x65ff, 0xc89d, 0x21, 0 - .dw 0x6640, 0xc89d, 0x667f, 0xc89d, 0x21, 0 - .dw 0x66c0, 0xc89d, 0x66ff, 0xc89d, 0x21, 0 - .dw 0x6740, 0xc89d, 0x677f, 0xc89d, 0x21, 0 - .dw 0x67c0, 0xc89d, 0x67ff, 0xc89d, 0x21, 0 - .dw 0x6840, 0xc89d, 0x687f, 0xc89d, 0x21, 0 - .dw 0x68c0, 0xc89d, 0x68ff, 0xc89d, 0x21, 0 - .dw 0x6940, 0xc89d, 0x697f, 0xc89d, 0x21, 0 - .dw 0x69c0, 0xc89d, 0x69ff, 0xc89d, 0x21, 0 - .dw 0x6a40, 0xc89d, 0x6a7f, 0xc89d, 0x21, 0 - .dw 0x6ac0, 0xc89d, 0x6aff, 0xc89d, 0x21, 0 - .dw 0x6b40, 0xc89d, 0x6b7f, 0xc89d, 0x21, 0 - .dw 0x6bc0, 0xc89d, 0x6bff, 0xc89d, 0x21, 0 - .dw 0x6c40, 0xc89d, 0x6c7f, 0xc89d, 0x21, 0 - .dw 0x6cc0, 0xc89d, 0x6cff, 0xc89d, 0x21, 0 - .dw 0x6d40, 0xc89d, 0x6d7f, 0xc89d, 0x21, 0 - .dw 0x6dc0, 0xc89d, 0x6dff, 0xc89d, 0x21, 0 - .dw 0x6e40, 0xc89d, 0x6e7f, 0xc89d, 0x21, 0 - .dw 0x6ec0, 0xc89d, 0x6eff, 0xc89d, 0x21, 0 - .dw 0x6f40, 0xc89d, 0x6f7f, 0xc89d, 0x21, 0 - .dw 0x6fc0, 0xc89d, 0x6fff, 0xc89d, 0x21, 0 - .dw 0x7040, 0xc89d, 0x707f, 0xc89d, 0x21, 0 - .dw 0x70c0, 0xc89d, 0x70ff, 0xc89d, 0x21, 0 - .dw 0x7140, 0xc89d, 0x717f, 0xc89d, 0x21, 0 - .dw 0x71c0, 0xc89d, 0x71ff, 0xc89d, 0x21, 0 - .dw 0x7240, 0xc89d, 0x727f, 0xc89d, 0x21, 0 - .dw 0x72c0, 0xc89d, 0x72ff, 0xc89d, 0x21, 0 - .dw 0x7340, 0xc89d, 0x737f, 0xc89d, 0x21, 0 - .dw 0x73c0, 0xc89d, 0x73ff, 0xc89d, 0x21, 0 - .dw 0x7440, 0xc89d, 0x747f, 0xc89d, 0x21, 0 - .dw 0x74c0, 0xc89d, 0x74ff, 0xc89d, 0x21, 0 - .dw 0x7540, 0xc89d, 0x757f, 0xc89d, 0x21, 0 - .dw 0x75c0, 0xc89d, 0x75ff, 0xc89d, 0x21, 0 - .dw 0x7640, 0xc89d, 0x767f, 0xc89d, 0x21, 0 - .dw 0x76c0, 0xc89d, 0x76ff, 0xc89d, 0x21, 0 - .dw 0x7740, 0xc89d, 0x777f, 0xc89d, 0x21, 0 - .dw 0x77c0, 0xc89d, 0x77ff, 0xc89d, 0x21, 0 - .dw 0x7840, 0xc89d, 0x787f, 0xc89d, 0x21, 0 - .dw 0x78c0, 0xc89d, 0x78ff, 0xc89d, 0x21, 0 - .dw 0x7940, 0xc89d, 0x797f, 0xc89d, 0x21, 0 - .dw 0x79c0, 0xc89d, 0x7fff, 0xc89d, 0x21, 0 - .dw 0x8040, 0xc89d, 0x807f, 0xc89d, 0x21, 0 - .dw 0x80c0, 0xc89d, 0x80ff, 0xc89d, 0x21, 0 - .dw 0x8140, 0xc89d, 0x817f, 0xc89d, 0x21, 0 - .dw 0x81c0, 0xc89d, 0x81ff, 0xc89d, 0x21, 0 - .dw 0x8240, 0xc89d, 0x827f, 0xc89d, 0x21, 0 - .dw 0x82c0, 0xc89d, 0x82ff, 0xc89d, 0x21, 0 - .dw 0x8340, 0xc89d, 0x837f, 0xc89d, 0x21, 0 - .dw 0x83c0, 0xc89d, 0x83ff, 0xc89d, 0x21, 0 - .dw 0x8440, 0xc89d, 0x847f, 0xc89d, 0x21, 0 - .dw 0x84c0, 0xc89d, 0x84ff, 0xc89d, 0x21, 0 - .dw 0x8540, 0xc89d, 0x857f, 0xc89d, 0x21, 0 - .dw 0x85c0, 0xc89d, 0x85ff, 0xc89d, 0x21, 0 - .dw 0x8640, 0xc89d, 0x867f, 0xc89d, 0x21, 0 - .dw 0x86c0, 0xc89d, 0x86ff, 0xc89d, 0x21, 0 - .dw 0x8740, 0xc89d, 0x877f, 0xc89d, 0x21, 0 - .dw 0x87c0, 0xc89d, 0x87ff, 0xc89d, 0x21, 0 - .dw 0x8840, 0xc89d, 0x887f, 0xc89d, 0x21, 0 - .dw 0x88c0, 0xc89d, 0x88ff, 0xc89d, 0x21, 0 - .dw 0x8940, 0xc89d, 0x897f, 0xc89d, 0x21, 0 - .dw 0x89c0, 0xc89d, 0x89ff, 0xc89d, 0x21, 0 - .dw 0x8a40, 0xc89d, 0x8a7f, 0xc89d, 0x21, 0 - .dw 0x8ac0, 0xc89d, 0x8aff, 0xc89d, 0x21, 0 - .dw 0x8b40, 0xc89d, 0x8b7f, 0xc89d, 0x21, 0 - .dw 0x8bc0, 0xc89d, 0x8bff, 0xc89d, 0x21, 0 - .dw 0x8c40, 0xc89d, 0x8c7f, 0xc89d, 0x21, 0 - .dw 0x8cc0, 0xc89d, 0x8cff, 0xc89d, 0x21, 0 - .dw 0x8d40, 0xc89d, 0x8d7f, 0xc89d, 0x21, 0 - .dw 0x8dc0, 0xc89d, 0x8dff, 0xc89d, 0x21, 0 - .dw 0x8e40, 0xc89d, 0x8e7f, 0xc89d, 0x21, 0 - .dw 0x8ec0, 0xc89d, 0x8eff, 0xc89d, 0x21, 0 - .dw 0x8f40, 0xc89d, 0x8f7f, 0xc89d, 0x21, 0 - .dw 0x8fc0, 0xc89d, 0x8fff, 0xc89d, 0x21, 0 - .dw 0x9040, 0xc89d, 0x907f, 0xc89d, 0x21, 0 - .dw 0x90c0, 0xc89d, 0x90ff, 0xc89d, 0x21, 0 - .dw 0x9140, 0xc89d, 0x917f, 0xc89d, 0x21, 0 - .dw 0x91c0, 0xc89d, 0x91ff, 0xc89d, 0x21, 0 - .dw 0x9240, 0xc89d, 0x927f, 0xc89d, 0x21, 0 - .dw 0x92c0, 0xc89d, 0x92ff, 0xc89d, 0x21, 0 - .dw 0x9340, 0xc89d, 0x937f, 0xc89d, 0x21, 0 - .dw 0x93c0, 0xc89d, 0x93ff, 0xc89d, 0x21, 0 - .dw 0x9440, 0xc89d, 0x947f, 0xc89d, 0x21, 0 - .dw 0x94c0, 0xc89d, 0x94ff, 0xc89d, 0x21, 0 - .dw 0x9540, 0xc89d, 0x957f, 0xc89d, 0x21, 0 - .dw 0x95c0, 0xc89d, 0x95ff, 0xc89d, 0x21, 0 - .dw 0x9640, 0xc89d, 0x967f, 0xc89d, 0x21, 0 - .dw 0x96c0, 0xc89d, 0x96ff, 0xc89d, 0x21, 0 - .dw 0x9740, 0xc89d, 0x977f, 0xc89d, 0x21, 0 - .dw 0x97c0, 0xc89d, 0x97ff, 0xc89d, 0x21, 0 - .dw 0x9840, 0xc89d, 0x987f, 0xc89d, 0x21, 0 - .dw 0x98c0, 0xc89d, 0x98ff, 0xc89d, 0x21, 0 - .dw 0x9940, 0xc89d, 0x997f, 0xc89d, 0x21, 0 - .dw 0x99c0, 0xc89d, 0x9fff, 0xc89d, 0x21, 0 - .dw 0xa040, 0xc89d, 0xa07f, 0xc89d, 0x21, 0 - .dw 0xa0c0, 0xc89d, 0xa0ff, 0xc89d, 0x21, 0 - .dw 0xa140, 0xc89d, 0xa17f, 0xc89d, 0x21, 0 - .dw 0xa1c0, 0xc89d, 0xa1ff, 0xc89d, 0x21, 0 - .dw 0xa240, 0xc89d, 0xa27f, 0xc89d, 0x21, 0 - .dw 0xa2c0, 0xc89d, 0xa2ff, 0xc89d, 0x21, 0 - .dw 0xa340, 0xc89d, 0xa37f, 0xc89d, 0x21, 0 - .dw 0xa3c0, 0xc89d, 0xa3ff, 0xc89d, 0x21, 0 - .dw 0xa440, 0xc89d, 0xa47f, 0xc89d, 0x21, 0 - .dw 0xa4c0, 0xc89d, 0xa4ff, 0xc89d, 0x21, 0 - .dw 0xa540, 0xc89d, 0xa57f, 0xc89d, 0x21, 0 - .dw 0xa5c0, 0xc89d, 0xa5ff, 0xc89d, 0x21, 0 - .dw 0xa640, 0xc89d, 0xa67f, 0xc89d, 0x21, 0 - .dw 0xa6c0, 0xc89d, 0xa6ff, 0xc89d, 0x21, 0 - .dw 0xa740, 0xc89d, 0xa77f, 0xc89d, 0x21, 0 - .dw 0xa7c0, 0xc89d, 0xa7ff, 0xc89d, 0x21, 0 - .dw 0xa840, 0xc89d, 0xa87f, 0xc89d, 0x21, 0 - .dw 0xa8c0, 0xc89d, 0xa8ff, 0xc89d, 0x21, 0 - .dw 0xa940, 0xc89d, 0xa97f, 0xc89d, 0x21, 0 - .dw 0xa9c0, 0xc89d, 0xa9ff, 0xc89d, 0x21, 0 - .dw 0xaa40, 0xc89d, 0xaa7f, 0xc89d, 0x21, 0 - .dw 0xaac0, 0xc89d, 0xaaff, 0xc89d, 0x21, 0 - .dw 0xab40, 0xc89d, 0xab7f, 0xc89d, 0x21, 0 - .dw 0xabc0, 0xc89d, 0xabff, 0xc89d, 0x21, 0 - .dw 0xac40, 0xc89d, 0xac7f, 0xc89d, 0x21, 0 - .dw 0xacc0, 0xc89d, 0xacff, 0xc89d, 0x21, 0 - .dw 0xad40, 0xc89d, 0xad7f, 0xc89d, 0x21, 0 - .dw 0xadc0, 0xc89d, 0xadff, 0xc89d, 0x21, 0 - .dw 0xae40, 0xc89d, 0xae7f, 0xc89d, 0x21, 0 - .dw 0xaec0, 0xc89d, 0xaeff, 0xc89d, 0x21, 0 - .dw 0xaf40, 0xc89d, 0xaf7f, 0xc89d, 0x21, 0 - .dw 0xafc0, 0xc89d, 0xafff, 0xc89d, 0x21, 0 - .dw 0xb040, 0xc89d, 0xb07f, 0xc89d, 0x21, 0 - .dw 0xb0c0, 0xc89d, 0xb0ff, 0xc89d, 0x21, 0 - .dw 0xb140, 0xc89d, 0xb17f, 0xc89d, 0x21, 0 - .dw 0xb1c0, 0xc89d, 0xb1ff, 0xc89d, 0x21, 0 - .dw 0xb240, 0xc89d, 0xb27f, 0xc89d, 0x21, 0 - .dw 0xb2c0, 0xc89d, 0xb2ff, 0xc89d, 0x21, 0 - .dw 0xb340, 0xc89d, 0xb37f, 0xc89d, 0x21, 0 - .dw 0xb3c0, 0xc89d, 0xb3ff, 0xc89d, 0x21, 0 - .dw 0xb440, 0xc89d, 0xb47f, 0xc89d, 0x21, 0 - .dw 0xb4c0, 0xc89d, 0xb4ff, 0xc89d, 0x21, 0 - .dw 0xb540, 0xc89d, 0xb57f, 0xc89d, 0x21, 0 - .dw 0xb5c0, 0xc89d, 0xb5ff, 0xc89d, 0x21, 0 - .dw 0xb640, 0xc89d, 0xb67f, 0xc89d, 0x21, 0 - .dw 0xb6c0, 0xc89d, 0xb6ff, 0xc89d, 0x21, 0 - .dw 0xb740, 0xc89d, 0xb77f, 0xc89d, 0x21, 0 - .dw 0xb7c0, 0xc89d, 0xb7ff, 0xc89d, 0x21, 0 - .dw 0xb840, 0xc89d, 0xb87f, 0xc89d, 0x21, 0 - .dw 0xb8c0, 0xc89d, 0xb8ff, 0xc89d, 0x21, 0 - .dw 0xb940, 0xc89d, 0xb97f, 0xc89d, 0x21, 0 - .dw 0xb9c0, 0xc89d, 0xbfff, 0xc89d, 0x21, 0 - .dw 0xc040, 0xc89d, 0xc07f, 0xc89d, 0x21, 0 - .dw 0xc0c0, 0xc89d, 0xc0ff, 0xc89d, 0x21, 0 - .dw 0xc140, 0xc89d, 0xc17f, 0xc89d, 0x21, 0 - .dw 0xc1c0, 0xc89d, 0xc1ff, 0xc89d, 0x21, 0 - .dw 0xc240, 0xc89d, 0xc27f, 0xc89d, 0x21, 0 - .dw 0xc2c0, 0xc89d, 0xc2ff, 0xc89d, 0x21, 0 - .dw 0xc340, 0xc89d, 0xc37f, 0xc89d, 0x21, 0 - .dw 0xc3c0, 0xc89d, 0xc3ff, 0xc89d, 0x21, 0 - .dw 0xc440, 0xc89d, 0xc47f, 0xc89d, 0x21, 0 - .dw 0xc4c0, 0xc89d, 0xc4ff, 0xc89d, 0x21, 0 - .dw 0xc540, 0xc89d, 0xc57f, 0xc89d, 0x21, 0 - .dw 0xc5c0, 0xc89d, 0xc5ff, 0xc89d, 0x21, 0 - .dw 0xc640, 0xc89d, 0xc67f, 0xc89d, 0x21, 0 - .dw 0xc6c0, 0xc89d, 0xc6ff, 0xc89d, 0x21, 0 - .dw 0xc740, 0xc89d, 0xc77f, 0xc89d, 0x21, 0 - .dw 0xc7c0, 0xc89d, 0xc7ff, 0xc89d, 0x21, 0 - .dw 0xc840, 0xc89d, 0xc87f, 0xc89d, 0x21, 0 - .dw 0xc8c0, 0xc89d, 0xc8ff, 0xc89d, 0x21, 0 - .dw 0xc940, 0xc89d, 0xc97f, 0xc89d, 0x21, 0 - .dw 0xc9c0, 0xc89d, 0xc9ff, 0xc89d, 0x21, 0 - .dw 0xca40, 0xc89d, 0xca7f, 0xc89d, 0x21, 0 - .dw 0xcac0, 0xc89d, 0xcaff, 0xc89d, 0x21, 0 - .dw 0xcb40, 0xc89d, 0xcb7f, 0xc89d, 0x21, 0 - .dw 0xcbc0, 0xc89d, 0xcbff, 0xc89d, 0x21, 0 - .dw 0xcc40, 0xc89d, 0xcc7f, 0xc89d, 0x21, 0 - .dw 0xccc0, 0xc89d, 0xccff, 0xc89d, 0x21, 0 - .dw 0xcd40, 0xc89d, 0xcd7f, 0xc89d, 0x21, 0 - .dw 0xcdc0, 0xc89d, 0xcdff, 0xc89d, 0x21, 0 - .dw 0xce40, 0xc89d, 0xce7f, 0xc89d, 0x21, 0 - .dw 0xcec0, 0xc89d, 0xceff, 0xc89d, 0x21, 0 - .dw 0xcf40, 0xc89d, 0xcf7f, 0xc89d, 0x21, 0 - .dw 0xcfc0, 0xc89d, 0xcfff, 0xc89d, 0x21, 0 - .dw 0xd040, 0xc89d, 0xd07f, 0xc89d, 0x21, 0 - .dw 0xd0c0, 0xc89d, 0xd0ff, 0xc89d, 0x21, 0 - .dw 0xd140, 0xc89d, 0xd17f, 0xc89d, 0x21, 0 - .dw 0xd1c0, 0xc89d, 0xd1ff, 0xc89d, 0x21, 0 - .dw 0xd240, 0xc89d, 0xd27f, 0xc89d, 0x21, 0 - .dw 0xd2c0, 0xc89d, 0xd2ff, 0xc89d, 0x21, 0 - .dw 0xd340, 0xc89d, 0xd37f, 0xc89d, 0x21, 0 - .dw 0xd3c0, 0xc89d, 0xd3ff, 0xc89d, 0x21, 0 - .dw 0xd440, 0xc89d, 0xd47f, 0xc89d, 0x21, 0 - .dw 0xd4c0, 0xc89d, 0xd4ff, 0xc89d, 0x21, 0 - .dw 0xd540, 0xc89d, 0xd57f, 0xc89d, 0x21, 0 - .dw 0xd5c0, 0xc89d, 0xd5ff, 0xc89d, 0x21, 0 - .dw 0xd640, 0xc89d, 0xd67f, 0xc89d, 0x21, 0 - .dw 0xd6c0, 0xc89d, 0xd6ff, 0xc89d, 0x21, 0 - .dw 0xd740, 0xc89d, 0xd77f, 0xc89d, 0x21, 0 - .dw 0xd7c0, 0xc89d, 0xd7ff, 0xc89d, 0x21, 0 - .dw 0xd840, 0xc89d, 0xd87f, 0xc89d, 0x21, 0 - .dw 0xd8c0, 0xc89d, 0xd8ff, 0xc89d, 0x21, 0 - .dw 0xd940, 0xc89d, 0xd97f, 0xc89d, 0x21, 0 - .dw 0xd9c0, 0xc89d, 0xdfff, 0xc89d, 0x21, 0 - .dw 0xe040, 0xc89d, 0xe07f, 0xc89d, 0x21, 0 - .dw 0xe0c0, 0xc89d, 0xe0ff, 0xc89d, 0x21, 0 - .dw 0xe140, 0xc89d, 0xe17f, 0xc89d, 0x21, 0 - .dw 0xe1c0, 0xc89d, 0xe1ff, 0xc89d, 0x21, 0 - .dw 0xe240, 0xc89d, 0xe27f, 0xc89d, 0x21, 0 - .dw 0xe2c0, 0xc89d, 0xe2ff, 0xc89d, 0x21, 0 - .dw 0xe340, 0xc89d, 0xe37f, 0xc89d, 0x21, 0 - .dw 0xe3c0, 0xc89d, 0xe3ff, 0xc89d, 0x21, 0 - .dw 0xe440, 0xc89d, 0xe47f, 0xc89d, 0x21, 0 - .dw 0xe4c0, 0xc89d, 0xe4ff, 0xc89d, 0x21, 0 - .dw 0xe540, 0xc89d, 0xe57f, 0xc89d, 0x21, 0 - .dw 0xe5c0, 0xc89d, 0xe5ff, 0xc89d, 0x21, 0 - .dw 0xe640, 0xc89d, 0xe67f, 0xc89d, 0x21, 0 - .dw 0xe6c0, 0xc89d, 0xe6ff, 0xc89d, 0x21, 0 - .dw 0xe740, 0xc89d, 0xe77f, 0xc89d, 0x21, 0 - .dw 0xe7c0, 0xc89d, 0xe7ff, 0xc89d, 0x21, 0 - .dw 0xe840, 0xc89d, 0xe87f, 0xc89d, 0x21, 0 - .dw 0xe8c0, 0xc89d, 0xe8ff, 0xc89d, 0x21, 0 - .dw 0xe940, 0xc89d, 0xe97f, 0xc89d, 0x21, 0 - .dw 0xe9c0, 0xc89d, 0xe9ff, 0xc89d, 0x21, 0 - .dw 0xea40, 0xc89d, 0xea7f, 0xc89d, 0x21, 0 - .dw 0xeac0, 0xc89d, 0xeaff, 0xc89d, 0x21, 0 - .dw 0xeb40, 0xc89d, 0xeb7f, 0xc89d, 0x21, 0 - .dw 0xebc0, 0xc89d, 0xebff, 0xc89d, 0x21, 0 - .dw 0xec40, 0xc89d, 0xec7f, 0xc89d, 0x21, 0 - .dw 0xecc0, 0xc89d, 0xecff, 0xc89d, 0x21, 0 - .dw 0xed40, 0xc89d, 0xed7f, 0xc89d, 0x21, 0 - .dw 0xedc0, 0xc89d, 0xedff, 0xc89d, 0x21, 0 - .dw 0xee40, 0xc89d, 0xee7f, 0xc89d, 0x21, 0 - .dw 0xeec0, 0xc89d, 0xeeff, 0xc89d, 0x21, 0 - .dw 0xef40, 0xc89d, 0xef7f, 0xc89d, 0x21, 0 - .dw 0xefc0, 0xc89d, 0xefff, 0xc89d, 0x21, 0 - .dw 0xf040, 0xc89d, 0xf07f, 0xc89d, 0x21, 0 - .dw 0xf0c0, 0xc89d, 0xf0ff, 0xc89d, 0x21, 0 - .dw 0xf140, 0xc89d, 0xf17f, 0xc89d, 0x21, 0 - .dw 0xf1c0, 0xc89d, 0xf1ff, 0xc89d, 0x21, 0 - .dw 0xf240, 0xc89d, 0xf27f, 0xc89d, 0x21, 0 - .dw 0xf2c0, 0xc89d, 0xf2ff, 0xc89d, 0x21, 0 - .dw 0xf340, 0xc89d, 0xf37f, 0xc89d, 0x21, 0 - .dw 0xf3c0, 0xc89d, 0xf3ff, 0xc89d, 0x21, 0 - .dw 0xf440, 0xc89d, 0xf47f, 0xc89d, 0x21, 0 - .dw 0xf4c0, 0xc89d, 0xf4ff, 0xc89d, 0x21, 0 - .dw 0xf540, 0xc89d, 0xf57f, 0xc89d, 0x21, 0 - .dw 0xf5c0, 0xc89d, 0xf5ff, 0xc89d, 0x21, 0 - .dw 0xf640, 0xc89d, 0xf67f, 0xc89d, 0x21, 0 - .dw 0xf6c0, 0xc89d, 0xf6ff, 0xc89d, 0x21, 0 - .dw 0xf740, 0xc89d, 0xf77f, 0xc89d, 0x21, 0 - .dw 0xf7c0, 0xc89d, 0xf7ff, 0xc89d, 0x21, 0 - .dw 0xf840, 0xc89d, 0xf87f, 0xc89d, 0x21, 0 - .dw 0xf8c0, 0xc89d, 0xf8ff, 0xc89d, 0x21, 0 - .dw 0xf940, 0xc89d, 0xf97f, 0xc89d, 0x21, 0 - .dw 0xf9c0, 0xc89d, 0xffff, 0xc89d, 0x21, 0 - .dw 0x0040, 0xc89e, 0x007f, 0xc89e, 0x21, 0 - .dw 0x00c0, 0xc89e, 0x00ff, 0xc89e, 0x21, 0 - .dw 0x0140, 0xc89e, 0x017f, 0xc89e, 0x21, 0 - .dw 0x01c0, 0xc89e, 0x01ff, 0xc89e, 0x21, 0 - .dw 0x0240, 0xc89e, 0x027f, 0xc89e, 0x21, 0 - .dw 0x02c0, 0xc89e, 0x02ff, 0xc89e, 0x21, 0 - .dw 0x0340, 0xc89e, 0x037f, 0xc89e, 0x21, 0 - .dw 0x03c0, 0xc89e, 0x03ff, 0xc89e, 0x21, 0 - .dw 0x0440, 0xc89e, 0x047f, 0xc89e, 0x21, 0 - .dw 0x04c0, 0xc89e, 0x04ff, 0xc89e, 0x21, 0 - .dw 0x0540, 0xc89e, 0x057f, 0xc89e, 0x21, 0 - .dw 0x05c0, 0xc89e, 0x05ff, 0xc89e, 0x21, 0 - .dw 0x0640, 0xc89e, 0x067f, 0xc89e, 0x21, 0 - .dw 0x06c0, 0xc89e, 0x06ff, 0xc89e, 0x21, 0 - .dw 0x0740, 0xc89e, 0x077f, 0xc89e, 0x21, 0 - .dw 0x07c0, 0xc89e, 0x07ff, 0xc89e, 0x21, 0 - .dw 0x0840, 0xc89e, 0x087f, 0xc89e, 0x21, 0 - .dw 0x08c0, 0xc89e, 0x08ff, 0xc89e, 0x21, 0 - .dw 0x0940, 0xc89e, 0x097f, 0xc89e, 0x21, 0 - .dw 0x09c0, 0xc89e, 0x09ff, 0xc89e, 0x21, 0 - .dw 0x0a40, 0xc89e, 0x0a7f, 0xc89e, 0x21, 0 - .dw 0x0ac0, 0xc89e, 0x0aff, 0xc89e, 0x21, 0 - .dw 0x0b40, 0xc89e, 0x0b7f, 0xc89e, 0x21, 0 - .dw 0x0bc0, 0xc89e, 0x0bff, 0xc89e, 0x21, 0 - .dw 0x0c40, 0xc89e, 0x0c7f, 0xc89e, 0x21, 0 - .dw 0x0cc0, 0xc89e, 0x0cff, 0xc89e, 0x21, 0 - .dw 0x0d40, 0xc89e, 0x0d7f, 0xc89e, 0x21, 0 - .dw 0x0dc0, 0xc89e, 0x0dff, 0xc89e, 0x21, 0 - .dw 0x0e40, 0xc89e, 0x0e7f, 0xc89e, 0x21, 0 - .dw 0x0ec0, 0xc89e, 0x0eff, 0xc89e, 0x21, 0 - .dw 0x0f40, 0xc89e, 0x0f7f, 0xc89e, 0x21, 0 - .dw 0x0fc0, 0xc89e, 0x0fff, 0xc89e, 0x21, 0 - .dw 0x1040, 0xc89e, 0x107f, 0xc89e, 0x21, 0 - .dw 0x10c0, 0xc89e, 0x10ff, 0xc89e, 0x21, 0 - .dw 0x1140, 0xc89e, 0x117f, 0xc89e, 0x21, 0 - .dw 0x11c0, 0xc89e, 0x11ff, 0xc89e, 0x21, 0 - .dw 0x1240, 0xc89e, 0x127f, 0xc89e, 0x21, 0 - .dw 0x12c0, 0xc89e, 0x12ff, 0xc89e, 0x21, 0 - .dw 0x1340, 0xc89e, 0x137f, 0xc89e, 0x21, 0 - .dw 0x13c0, 0xc89e, 0x13ff, 0xc89e, 0x21, 0 - .dw 0x1440, 0xc89e, 0x147f, 0xc89e, 0x21, 0 - .dw 0x14c0, 0xc89e, 0x14ff, 0xc89e, 0x21, 0 - .dw 0x1540, 0xc89e, 0x157f, 0xc89e, 0x21, 0 - .dw 0x15c0, 0xc89e, 0x15ff, 0xc89e, 0x21, 0 - .dw 0x1640, 0xc89e, 0x167f, 0xc89e, 0x21, 0 - .dw 0x16c0, 0xc89e, 0x16ff, 0xc89e, 0x21, 0 - .dw 0x1740, 0xc89e, 0x177f, 0xc89e, 0x21, 0 - .dw 0x17c0, 0xc89e, 0x17ff, 0xc89e, 0x21, 0 - .dw 0x1840, 0xc89e, 0x187f, 0xc89e, 0x21, 0 - .dw 0x18c0, 0xc89e, 0x18ff, 0xc89e, 0x21, 0 - .dw 0x1940, 0xc89e, 0x197f, 0xc89e, 0x21, 0 - .dw 0x19c0, 0xc89e, 0x1fff, 0xc89e, 0x21, 0 - .dw 0x2040, 0xc89e, 0x207f, 0xc89e, 0x21, 0 - .dw 0x20c0, 0xc89e, 0x20ff, 0xc89e, 0x21, 0 - .dw 0x2140, 0xc89e, 0x217f, 0xc89e, 0x21, 0 - .dw 0x21c0, 0xc89e, 0x21ff, 0xc89e, 0x21, 0 - .dw 0x2240, 0xc89e, 0x227f, 0xc89e, 0x21, 0 - .dw 0x22c0, 0xc89e, 0x22ff, 0xc89e, 0x21, 0 - .dw 0x2340, 0xc89e, 0x237f, 0xc89e, 0x21, 0 - .dw 0x23c0, 0xc89e, 0x23ff, 0xc89e, 0x21, 0 - .dw 0x2440, 0xc89e, 0x247f, 0xc89e, 0x21, 0 - .dw 0x24c0, 0xc89e, 0x24ff, 0xc89e, 0x21, 0 - .dw 0x2540, 0xc89e, 0x257f, 0xc89e, 0x21, 0 - .dw 0x25c0, 0xc89e, 0x25ff, 0xc89e, 0x21, 0 - .dw 0x2640, 0xc89e, 0x267f, 0xc89e, 0x21, 0 - .dw 0x26c0, 0xc89e, 0x26ff, 0xc89e, 0x21, 0 - .dw 0x2740, 0xc89e, 0x277f, 0xc89e, 0x21, 0 - .dw 0x27c0, 0xc89e, 0x27ff, 0xc89e, 0x21, 0 - .dw 0x2840, 0xc89e, 0x287f, 0xc89e, 0x21, 0 - .dw 0x28c0, 0xc89e, 0x28ff, 0xc89e, 0x21, 0 - .dw 0x2940, 0xc89e, 0x297f, 0xc89e, 0x21, 0 - .dw 0x29c0, 0xc89e, 0x29ff, 0xc89e, 0x21, 0 - .dw 0x2a40, 0xc89e, 0x2a7f, 0xc89e, 0x21, 0 - .dw 0x2ac0, 0xc89e, 0x2aff, 0xc89e, 0x21, 0 - .dw 0x2b40, 0xc89e, 0x2b7f, 0xc89e, 0x21, 0 - .dw 0x2bc0, 0xc89e, 0x2bff, 0xc89e, 0x21, 0 - .dw 0x2c40, 0xc89e, 0x2c7f, 0xc89e, 0x21, 0 - .dw 0x2cc0, 0xc89e, 0x2cff, 0xc89e, 0x21, 0 - .dw 0x2d40, 0xc89e, 0x2d7f, 0xc89e, 0x21, 0 - .dw 0x2dc0, 0xc89e, 0x2dff, 0xc89e, 0x21, 0 - .dw 0x2e40, 0xc89e, 0x2e7f, 0xc89e, 0x21, 0 - .dw 0x2ec0, 0xc89e, 0x2eff, 0xc89e, 0x21, 0 - .dw 0x2f40, 0xc89e, 0x2f7f, 0xc89e, 0x21, 0 - .dw 0x2fc0, 0xc89e, 0x2fff, 0xc89e, 0x21, 0 - .dw 0x3040, 0xc89e, 0x307f, 0xc89e, 0x21, 0 - .dw 0x30c0, 0xc89e, 0x30ff, 0xc89e, 0x21, 0 - .dw 0x3140, 0xc89e, 0x317f, 0xc89e, 0x21, 0 - .dw 0x31c0, 0xc89e, 0x31ff, 0xc89e, 0x21, 0 - .dw 0x3240, 0xc89e, 0x327f, 0xc89e, 0x21, 0 - .dw 0x32c0, 0xc89e, 0x32ff, 0xc89e, 0x21, 0 - .dw 0x3340, 0xc89e, 0x337f, 0xc89e, 0x21, 0 - .dw 0x33c0, 0xc89e, 0x33ff, 0xc89e, 0x21, 0 - .dw 0x3440, 0xc89e, 0x347f, 0xc89e, 0x21, 0 - .dw 0x34c0, 0xc89e, 0x34ff, 0xc89e, 0x21, 0 - .dw 0x3540, 0xc89e, 0x357f, 0xc89e, 0x21, 0 - .dw 0x35c0, 0xc89e, 0x35ff, 0xc89e, 0x21, 0 - .dw 0x3640, 0xc89e, 0x367f, 0xc89e, 0x21, 0 - .dw 0x36c0, 0xc89e, 0x36ff, 0xc89e, 0x21, 0 - .dw 0x3740, 0xc89e, 0x377f, 0xc89e, 0x21, 0 - .dw 0x37c0, 0xc89e, 0x37ff, 0xc89e, 0x21, 0 - .dw 0x3840, 0xc89e, 0x387f, 0xc89e, 0x21, 0 - .dw 0x38c0, 0xc89e, 0x38ff, 0xc89e, 0x21, 0 - .dw 0x3940, 0xc89e, 0x397f, 0xc89e, 0x21, 0 - .dw 0x39c0, 0xc89e, 0x3fff, 0xc89e, 0x21, 0 - .dw 0x4040, 0xc89e, 0x407f, 0xc89e, 0x21, 0 - .dw 0x40c0, 0xc89e, 0x40ff, 0xc89e, 0x21, 0 - .dw 0x4140, 0xc89e, 0x417f, 0xc89e, 0x21, 0 - .dw 0x41c0, 0xc89e, 0x41ff, 0xc89e, 0x21, 0 - .dw 0x4240, 0xc89e, 0x427f, 0xc89e, 0x21, 0 - .dw 0x42c0, 0xc89e, 0x42ff, 0xc89e, 0x21, 0 - .dw 0x4340, 0xc89e, 0x437f, 0xc89e, 0x21, 0 - .dw 0x43c0, 0xc89e, 0x43ff, 0xc89e, 0x21, 0 - .dw 0x4440, 0xc89e, 0x447f, 0xc89e, 0x21, 0 - .dw 0x44c0, 0xc89e, 0x44ff, 0xc89e, 0x21, 0 - .dw 0x4540, 0xc89e, 0x457f, 0xc89e, 0x21, 0 - .dw 0x45c0, 0xc89e, 0x45ff, 0xc89e, 0x21, 0 - .dw 0x4640, 0xc89e, 0x467f, 0xc89e, 0x21, 0 - .dw 0x46c0, 0xc89e, 0x46ff, 0xc89e, 0x21, 0 - .dw 0x4740, 0xc89e, 0x477f, 0xc89e, 0x21, 0 - .dw 0x47c0, 0xc89e, 0x47ff, 0xc89e, 0x21, 0 - .dw 0x4840, 0xc89e, 0x487f, 0xc89e, 0x21, 0 - .dw 0x48c0, 0xc89e, 0x48ff, 0xc89e, 0x21, 0 - .dw 0x4940, 0xc89e, 0x497f, 0xc89e, 0x21, 0 - .dw 0x49c0, 0xc89e, 0x49ff, 0xc89e, 0x21, 0 - .dw 0x4a40, 0xc89e, 0x4a7f, 0xc89e, 0x21, 0 - .dw 0x4ac0, 0xc89e, 0x4aff, 0xc89e, 0x21, 0 - .dw 0x4b40, 0xc89e, 0x4b7f, 0xc89e, 0x21, 0 - .dw 0x4bc0, 0xc89e, 0x4bff, 0xc89e, 0x21, 0 - .dw 0x4c40, 0xc89e, 0x4c7f, 0xc89e, 0x21, 0 - .dw 0x4cc0, 0xc89e, 0x4cff, 0xc89e, 0x21, 0 - .dw 0x4d40, 0xc89e, 0x4d7f, 0xc89e, 0x21, 0 - .dw 0x4dc0, 0xc89e, 0x4dff, 0xc89e, 0x21, 0 - .dw 0x4e40, 0xc89e, 0x4e7f, 0xc89e, 0x21, 0 - .dw 0x4ec0, 0xc89e, 0x4eff, 0xc89e, 0x21, 0 - .dw 0x4f40, 0xc89e, 0x4f7f, 0xc89e, 0x21, 0 - .dw 0x4fc0, 0xc89e, 0x4fff, 0xc89e, 0x21, 0 - .dw 0x5040, 0xc89e, 0x507f, 0xc89e, 0x21, 0 - .dw 0x50c0, 0xc89e, 0x50ff, 0xc89e, 0x21, 0 - .dw 0x5140, 0xc89e, 0x517f, 0xc89e, 0x21, 0 - .dw 0x51c0, 0xc89e, 0x51ff, 0xc89e, 0x21, 0 - .dw 0x5240, 0xc89e, 0x527f, 0xc89e, 0x21, 0 - .dw 0x52c0, 0xc89e, 0x52ff, 0xc89e, 0x21, 0 - .dw 0x5340, 0xc89e, 0x537f, 0xc89e, 0x21, 0 - .dw 0x53c0, 0xc89e, 0x53ff, 0xc89e, 0x21, 0 - .dw 0x5440, 0xc89e, 0x547f, 0xc89e, 0x21, 0 - .dw 0x54c0, 0xc89e, 0x54ff, 0xc89e, 0x21, 0 - .dw 0x5540, 0xc89e, 0x557f, 0xc89e, 0x21, 0 - .dw 0x55c0, 0xc89e, 0x55ff, 0xc89e, 0x21, 0 - .dw 0x5640, 0xc89e, 0x567f, 0xc89e, 0x21, 0 - .dw 0x56c0, 0xc89e, 0x56ff, 0xc89e, 0x21, 0 - .dw 0x5740, 0xc89e, 0x577f, 0xc89e, 0x21, 0 - .dw 0x57c0, 0xc89e, 0x57ff, 0xc89e, 0x21, 0 - .dw 0x5840, 0xc89e, 0x587f, 0xc89e, 0x21, 0 - .dw 0x58c0, 0xc89e, 0x58ff, 0xc89e, 0x21, 0 - .dw 0x5940, 0xc89e, 0x597f, 0xc89e, 0x21, 0 - .dw 0x59c0, 0xc89e, 0x5fff, 0xc89e, 0x21, 0 - .dw 0x6040, 0xc89e, 0x607f, 0xc89e, 0x21, 0 - .dw 0x60c0, 0xc89e, 0x60ff, 0xc89e, 0x21, 0 - .dw 0x6140, 0xc89e, 0x617f, 0xc89e, 0x21, 0 - .dw 0x61c0, 0xc89e, 0x61ff, 0xc89e, 0x21, 0 - .dw 0x6240, 0xc89e, 0x627f, 0xc89e, 0x21, 0 - .dw 0x62c0, 0xc89e, 0x62ff, 0xc89e, 0x21, 0 - .dw 0x6340, 0xc89e, 0x637f, 0xc89e, 0x21, 0 - .dw 0x63c0, 0xc89e, 0x63ff, 0xc89e, 0x21, 0 - .dw 0x6440, 0xc89e, 0x647f, 0xc89e, 0x21, 0 - .dw 0x64c0, 0xc89e, 0x64ff, 0xc89e, 0x21, 0 - .dw 0x6540, 0xc89e, 0x657f, 0xc89e, 0x21, 0 - .dw 0x65c0, 0xc89e, 0x65ff, 0xc89e, 0x21, 0 - .dw 0x6640, 0xc89e, 0x667f, 0xc89e, 0x21, 0 - .dw 0x66c0, 0xc89e, 0x66ff, 0xc89e, 0x21, 0 - .dw 0x6740, 0xc89e, 0x677f, 0xc89e, 0x21, 0 - .dw 0x67c0, 0xc89e, 0x67ff, 0xc89e, 0x21, 0 - .dw 0x6840, 0xc89e, 0x687f, 0xc89e, 0x21, 0 - .dw 0x68c0, 0xc89e, 0x68ff, 0xc89e, 0x21, 0 - .dw 0x6940, 0xc89e, 0x697f, 0xc89e, 0x21, 0 - .dw 0x69c0, 0xc89e, 0x69ff, 0xc89e, 0x21, 0 - .dw 0x6a40, 0xc89e, 0x6a7f, 0xc89e, 0x21, 0 - .dw 0x6ac0, 0xc89e, 0x6aff, 0xc89e, 0x21, 0 - .dw 0x6b40, 0xc89e, 0x6b7f, 0xc89e, 0x21, 0 - .dw 0x6bc0, 0xc89e, 0x6bff, 0xc89e, 0x21, 0 - .dw 0x6c40, 0xc89e, 0x6c7f, 0xc89e, 0x21, 0 - .dw 0x6cc0, 0xc89e, 0x6cff, 0xc89e, 0x21, 0 - .dw 0x6d40, 0xc89e, 0x6d7f, 0xc89e, 0x21, 0 - .dw 0x6dc0, 0xc89e, 0x6dff, 0xc89e, 0x21, 0 - .dw 0x6e40, 0xc89e, 0x6e7f, 0xc89e, 0x21, 0 - .dw 0x6ec0, 0xc89e, 0x6eff, 0xc89e, 0x21, 0 - .dw 0x6f40, 0xc89e, 0x6f7f, 0xc89e, 0x21, 0 - .dw 0x6fc0, 0xc89e, 0x6fff, 0xc89e, 0x21, 0 - .dw 0x7040, 0xc89e, 0x707f, 0xc89e, 0x21, 0 - .dw 0x70c0, 0xc89e, 0x70ff, 0xc89e, 0x21, 0 - .dw 0x7140, 0xc89e, 0x717f, 0xc89e, 0x21, 0 - .dw 0x71c0, 0xc89e, 0x71ff, 0xc89e, 0x21, 0 - .dw 0x7240, 0xc89e, 0x727f, 0xc89e, 0x21, 0 - .dw 0x72c0, 0xc89e, 0x72ff, 0xc89e, 0x21, 0 - .dw 0x7340, 0xc89e, 0x737f, 0xc89e, 0x21, 0 - .dw 0x73c0, 0xc89e, 0x73ff, 0xc89e, 0x21, 0 - .dw 0x7440, 0xc89e, 0x747f, 0xc89e, 0x21, 0 - .dw 0x74c0, 0xc89e, 0x74ff, 0xc89e, 0x21, 0 - .dw 0x7540, 0xc89e, 0x757f, 0xc89e, 0x21, 0 - .dw 0x75c0, 0xc89e, 0x75ff, 0xc89e, 0x21, 0 - .dw 0x7640, 0xc89e, 0x767f, 0xc89e, 0x21, 0 - .dw 0x76c0, 0xc89e, 0x76ff, 0xc89e, 0x21, 0 - .dw 0x7740, 0xc89e, 0x777f, 0xc89e, 0x21, 0 - .dw 0x77c0, 0xc89e, 0x77ff, 0xc89e, 0x21, 0 - .dw 0x7840, 0xc89e, 0x787f, 0xc89e, 0x21, 0 - .dw 0x78c0, 0xc89e, 0x78ff, 0xc89e, 0x21, 0 - .dw 0x7940, 0xc89e, 0x797f, 0xc89e, 0x21, 0 - .dw 0x79c0, 0xc89e, 0x7fff, 0xc89e, 0x21, 0 - .dw 0x8040, 0xc89e, 0x807f, 0xc89e, 0x21, 0 - .dw 0x80c0, 0xc89e, 0x80ff, 0xc89e, 0x21, 0 - .dw 0x8140, 0xc89e, 0x817f, 0xc89e, 0x21, 0 - .dw 0x81c0, 0xc89e, 0x81ff, 0xc89e, 0x21, 0 - .dw 0x8240, 0xc89e, 0x827f, 0xc89e, 0x21, 0 - .dw 0x82c0, 0xc89e, 0x82ff, 0xc89e, 0x21, 0 - .dw 0x8340, 0xc89e, 0x837f, 0xc89e, 0x21, 0 - .dw 0x83c0, 0xc89e, 0x83ff, 0xc89e, 0x21, 0 - .dw 0x8440, 0xc89e, 0x847f, 0xc89e, 0x21, 0 - .dw 0x84c0, 0xc89e, 0x84ff, 0xc89e, 0x21, 0 - .dw 0x8540, 0xc89e, 0x857f, 0xc89e, 0x21, 0 - .dw 0x85c0, 0xc89e, 0x85ff, 0xc89e, 0x21, 0 - .dw 0x8640, 0xc89e, 0x867f, 0xc89e, 0x21, 0 - .dw 0x86c0, 0xc89e, 0x86ff, 0xc89e, 0x21, 0 - .dw 0x8740, 0xc89e, 0x877f, 0xc89e, 0x21, 0 - .dw 0x87c0, 0xc89e, 0x87ff, 0xc89e, 0x21, 0 - .dw 0x8840, 0xc89e, 0x887f, 0xc89e, 0x21, 0 - .dw 0x88c0, 0xc89e, 0x88ff, 0xc89e, 0x21, 0 - .dw 0x8940, 0xc89e, 0x897f, 0xc89e, 0x21, 0 - .dw 0x89c0, 0xc89e, 0x89ff, 0xc89e, 0x21, 0 - .dw 0x8a40, 0xc89e, 0x8a7f, 0xc89e, 0x21, 0 - .dw 0x8ac0, 0xc89e, 0x8aff, 0xc89e, 0x21, 0 - .dw 0x8b40, 0xc89e, 0x8b7f, 0xc89e, 0x21, 0 - .dw 0x8bc0, 0xc89e, 0x8bff, 0xc89e, 0x21, 0 - .dw 0x8c40, 0xc89e, 0x8c7f, 0xc89e, 0x21, 0 - .dw 0x8cc0, 0xc89e, 0x8cff, 0xc89e, 0x21, 0 - .dw 0x8d40, 0xc89e, 0x8d7f, 0xc89e, 0x21, 0 - .dw 0x8dc0, 0xc89e, 0x8dff, 0xc89e, 0x21, 0 - .dw 0x8e40, 0xc89e, 0x8e7f, 0xc89e, 0x21, 0 - .dw 0x8ec0, 0xc89e, 0x8eff, 0xc89e, 0x21, 0 - .dw 0x8f40, 0xc89e, 0x8f7f, 0xc89e, 0x21, 0 - .dw 0x8fc0, 0xc89e, 0x8fff, 0xc89e, 0x21, 0 - .dw 0x9040, 0xc89e, 0x907f, 0xc89e, 0x21, 0 - .dw 0x90c0, 0xc89e, 0x90ff, 0xc89e, 0x21, 0 - .dw 0x9140, 0xc89e, 0x917f, 0xc89e, 0x21, 0 - .dw 0x91c0, 0xc89e, 0x91ff, 0xc89e, 0x21, 0 - .dw 0x9240, 0xc89e, 0x927f, 0xc89e, 0x21, 0 - .dw 0x92c0, 0xc89e, 0x92ff, 0xc89e, 0x21, 0 - .dw 0x9340, 0xc89e, 0x937f, 0xc89e, 0x21, 0 - .dw 0x93c0, 0xc89e, 0x93ff, 0xc89e, 0x21, 0 - .dw 0x9440, 0xc89e, 0x947f, 0xc89e, 0x21, 0 - .dw 0x94c0, 0xc89e, 0x94ff, 0xc89e, 0x21, 0 - .dw 0x9540, 0xc89e, 0x957f, 0xc89e, 0x21, 0 - .dw 0x95c0, 0xc89e, 0x95ff, 0xc89e, 0x21, 0 - .dw 0x9640, 0xc89e, 0x967f, 0xc89e, 0x21, 0 - .dw 0x96c0, 0xc89e, 0x96ff, 0xc89e, 0x21, 0 - .dw 0x9740, 0xc89e, 0x977f, 0xc89e, 0x21, 0 - .dw 0x97c0, 0xc89e, 0x97ff, 0xc89e, 0x21, 0 - .dw 0x9840, 0xc89e, 0x987f, 0xc89e, 0x21, 0 - .dw 0x98c0, 0xc89e, 0x98ff, 0xc89e, 0x21, 0 - .dw 0x9940, 0xc89e, 0x997f, 0xc89e, 0x21, 0 - .dw 0x99c0, 0xc89e, 0x9fff, 0xc89e, 0x21, 0 - .dw 0xa040, 0xc89e, 0xa07f, 0xc89e, 0x21, 0 - .dw 0xa0c0, 0xc89e, 0xa0ff, 0xc89e, 0x21, 0 - .dw 0xa140, 0xc89e, 0xa17f, 0xc89e, 0x21, 0 - .dw 0xa1c0, 0xc89e, 0xa1ff, 0xc89e, 0x21, 0 - .dw 0xa240, 0xc89e, 0xa27f, 0xc89e, 0x21, 0 - .dw 0xa2c0, 0xc89e, 0xa2ff, 0xc89e, 0x21, 0 - .dw 0xa340, 0xc89e, 0xa37f, 0xc89e, 0x21, 0 - .dw 0xa3c0, 0xc89e, 0xa3ff, 0xc89e, 0x21, 0 - .dw 0xa440, 0xc89e, 0xa47f, 0xc89e, 0x21, 0 - .dw 0xa4c0, 0xc89e, 0xa4ff, 0xc89e, 0x21, 0 - .dw 0xa540, 0xc89e, 0xa57f, 0xc89e, 0x21, 0 - .dw 0xa5c0, 0xc89e, 0xa5ff, 0xc89e, 0x21, 0 - .dw 0xa640, 0xc89e, 0xa67f, 0xc89e, 0x21, 0 - .dw 0xa6c0, 0xc89e, 0xa6ff, 0xc89e, 0x21, 0 - .dw 0xa740, 0xc89e, 0xa77f, 0xc89e, 0x21, 0 - .dw 0xa7c0, 0xc89e, 0xa7ff, 0xc89e, 0x21, 0 - .dw 0xa840, 0xc89e, 0xa87f, 0xc89e, 0x21, 0 - .dw 0xa8c0, 0xc89e, 0xa8ff, 0xc89e, 0x21, 0 - .dw 0xa940, 0xc89e, 0xa97f, 0xc89e, 0x21, 0 - .dw 0xa9c0, 0xc89e, 0xa9ff, 0xc89e, 0x21, 0 - .dw 0xaa40, 0xc89e, 0xaa7f, 0xc89e, 0x21, 0 - .dw 0xaac0, 0xc89e, 0xaaff, 0xc89e, 0x21, 0 - .dw 0xab40, 0xc89e, 0xab7f, 0xc89e, 0x21, 0 - .dw 0xabc0, 0xc89e, 0xabff, 0xc89e, 0x21, 0 - .dw 0xac40, 0xc89e, 0xac7f, 0xc89e, 0x21, 0 - .dw 0xacc0, 0xc89e, 0xacff, 0xc89e, 0x21, 0 - .dw 0xad40, 0xc89e, 0xad7f, 0xc89e, 0x21, 0 - .dw 0xadc0, 0xc89e, 0xadff, 0xc89e, 0x21, 0 - .dw 0xae40, 0xc89e, 0xae7f, 0xc89e, 0x21, 0 - .dw 0xaec0, 0xc89e, 0xaeff, 0xc89e, 0x21, 0 - .dw 0xaf40, 0xc89e, 0xaf7f, 0xc89e, 0x21, 0 - .dw 0xafc0, 0xc89e, 0xafff, 0xc89e, 0x21, 0 - .dw 0xb040, 0xc89e, 0xb07f, 0xc89e, 0x21, 0 - .dw 0xb0c0, 0xc89e, 0xb0ff, 0xc89e, 0x21, 0 - .dw 0xb140, 0xc89e, 0xb17f, 0xc89e, 0x21, 0 - .dw 0xb1c0, 0xc89e, 0xb1ff, 0xc89e, 0x21, 0 - .dw 0xb240, 0xc89e, 0xb27f, 0xc89e, 0x21, 0 - .dw 0xb2c0, 0xc89e, 0xb2ff, 0xc89e, 0x21, 0 - .dw 0xb340, 0xc89e, 0xb37f, 0xc89e, 0x21, 0 - .dw 0xb3c0, 0xc89e, 0xb3ff, 0xc89e, 0x21, 0 - .dw 0xb440, 0xc89e, 0xb47f, 0xc89e, 0x21, 0 - .dw 0xb4c0, 0xc89e, 0xb4ff, 0xc89e, 0x21, 0 - .dw 0xb540, 0xc89e, 0xb57f, 0xc89e, 0x21, 0 - .dw 0xb5c0, 0xc89e, 0xb5ff, 0xc89e, 0x21, 0 - .dw 0xb640, 0xc89e, 0xb67f, 0xc89e, 0x21, 0 - .dw 0xb6c0, 0xc89e, 0xb6ff, 0xc89e, 0x21, 0 - .dw 0xb740, 0xc89e, 0xb77f, 0xc89e, 0x21, 0 - .dw 0xb7c0, 0xc89e, 0xb7ff, 0xc89e, 0x21, 0 - .dw 0xb840, 0xc89e, 0xb87f, 0xc89e, 0x21, 0 - .dw 0xb8c0, 0xc89e, 0xb8ff, 0xc89e, 0x21, 0 - .dw 0xb940, 0xc89e, 0xb97f, 0xc89e, 0x21, 0 - .dw 0xb9c0, 0xc89e, 0xbfff, 0xc89e, 0x21, 0 - .dw 0xc040, 0xc89e, 0xc07f, 0xc89e, 0x21, 0 - .dw 0xc0c0, 0xc89e, 0xc0ff, 0xc89e, 0x21, 0 - .dw 0xc140, 0xc89e, 0xc17f, 0xc89e, 0x21, 0 - .dw 0xc1c0, 0xc89e, 0xc1ff, 0xc89e, 0x21, 0 - .dw 0xc240, 0xc89e, 0xc27f, 0xc89e, 0x21, 0 - .dw 0xc2c0, 0xc89e, 0xc2ff, 0xc89e, 0x21, 0 - .dw 0xc340, 0xc89e, 0xc37f, 0xc89e, 0x21, 0 - .dw 0xc3c0, 0xc89e, 0xc3ff, 0xc89e, 0x21, 0 - .dw 0xc440, 0xc89e, 0xc47f, 0xc89e, 0x21, 0 - .dw 0xc4c0, 0xc89e, 0xc4ff, 0xc89e, 0x21, 0 - .dw 0xc540, 0xc89e, 0xc57f, 0xc89e, 0x21, 0 - .dw 0xc5c0, 0xc89e, 0xc5ff, 0xc89e, 0x21, 0 - .dw 0xc640, 0xc89e, 0xc67f, 0xc89e, 0x21, 0 - .dw 0xc6c0, 0xc89e, 0xc6ff, 0xc89e, 0x21, 0 - .dw 0xc740, 0xc89e, 0xc77f, 0xc89e, 0x21, 0 - .dw 0xc7c0, 0xc89e, 0xc7ff, 0xc89e, 0x21, 0 - .dw 0xc840, 0xc89e, 0xc87f, 0xc89e, 0x21, 0 - .dw 0xc8c0, 0xc89e, 0xc8ff, 0xc89e, 0x21, 0 - .dw 0xc940, 0xc89e, 0xc97f, 0xc89e, 0x21, 0 - .dw 0xc9c0, 0xc89e, 0xc9ff, 0xc89e, 0x21, 0 - .dw 0xca40, 0xc89e, 0xca7f, 0xc89e, 0x21, 0 - .dw 0xcac0, 0xc89e, 0xcaff, 0xc89e, 0x21, 0 - .dw 0xcb40, 0xc89e, 0xcb7f, 0xc89e, 0x21, 0 - .dw 0xcbc0, 0xc89e, 0xcbff, 0xc89e, 0x21, 0 - .dw 0xcc40, 0xc89e, 0xcc7f, 0xc89e, 0x21, 0 - .dw 0xccc0, 0xc89e, 0xccff, 0xc89e, 0x21, 0 - .dw 0xcd40, 0xc89e, 0xcd7f, 0xc89e, 0x21, 0 - .dw 0xcdc0, 0xc89e, 0xcdff, 0xc89e, 0x21, 0 - .dw 0xce40, 0xc89e, 0xce7f, 0xc89e, 0x21, 0 - .dw 0xcec0, 0xc89e, 0xceff, 0xc89e, 0x21, 0 - .dw 0xcf40, 0xc89e, 0xcf7f, 0xc89e, 0x21, 0 - .dw 0xcfc0, 0xc89e, 0xcfff, 0xc89e, 0x21, 0 - .dw 0xd040, 0xc89e, 0xd07f, 0xc89e, 0x21, 0 - .dw 0xd0c0, 0xc89e, 0xd0ff, 0xc89e, 0x21, 0 - .dw 0xd140, 0xc89e, 0xd17f, 0xc89e, 0x21, 0 - .dw 0xd1c0, 0xc89e, 0xd1ff, 0xc89e, 0x21, 0 - .dw 0xd240, 0xc89e, 0xd27f, 0xc89e, 0x21, 0 - .dw 0xd2c0, 0xc89e, 0xd2ff, 0xc89e, 0x21, 0 - .dw 0xd340, 0xc89e, 0xd37f, 0xc89e, 0x21, 0 - .dw 0xd3c0, 0xc89e, 0xd3ff, 0xc89e, 0x21, 0 - .dw 0xd440, 0xc89e, 0xd47f, 0xc89e, 0x21, 0 - .dw 0xd4c0, 0xc89e, 0xd4ff, 0xc89e, 0x21, 0 - .dw 0xd540, 0xc89e, 0xd57f, 0xc89e, 0x21, 0 - .dw 0xd5c0, 0xc89e, 0xd5ff, 0xc89e, 0x21, 0 - .dw 0xd640, 0xc89e, 0xd67f, 0xc89e, 0x21, 0 - .dw 0xd6c0, 0xc89e, 0xd6ff, 0xc89e, 0x21, 0 - .dw 0xd740, 0xc89e, 0xd77f, 0xc89e, 0x21, 0 - .dw 0xd7c0, 0xc89e, 0xd7ff, 0xc89e, 0x21, 0 - .dw 0xd840, 0xc89e, 0xd87f, 0xc89e, 0x21, 0 - .dw 0xd8c0, 0xc89e, 0xd8ff, 0xc89e, 0x21, 0 - .dw 0xd940, 0xc89e, 0xd97f, 0xc89e, 0x21, 0 - .dw 0xd9c0, 0xc89e, 0xdfff, 0xc89e, 0x21, 0 - .dw 0xe040, 0xc89e, 0xe07f, 0xc89e, 0x21, 0 - .dw 0xe0c0, 0xc89e, 0xe0ff, 0xc89e, 0x21, 0 - .dw 0xe140, 0xc89e, 0xe17f, 0xc89e, 0x21, 0 - .dw 0xe1c0, 0xc89e, 0xe1ff, 0xc89e, 0x21, 0 - .dw 0xe240, 0xc89e, 0xe27f, 0xc89e, 0x21, 0 - .dw 0xe2c0, 0xc89e, 0xe2ff, 0xc89e, 0x21, 0 - .dw 0xe340, 0xc89e, 0xe37f, 0xc89e, 0x21, 0 - .dw 0xe3c0, 0xc89e, 0xe3ff, 0xc89e, 0x21, 0 - .dw 0xe440, 0xc89e, 0xe47f, 0xc89e, 0x21, 0 - .dw 0xe4c0, 0xc89e, 0xe4ff, 0xc89e, 0x21, 0 - .dw 0xe540, 0xc89e, 0xe57f, 0xc89e, 0x21, 0 - .dw 0xe5c0, 0xc89e, 0xe5ff, 0xc89e, 0x21, 0 - .dw 0xe640, 0xc89e, 0xe67f, 0xc89e, 0x21, 0 - .dw 0xe6c0, 0xc89e, 0xe6ff, 0xc89e, 0x21, 0 - .dw 0xe740, 0xc89e, 0xe77f, 0xc89e, 0x21, 0 - .dw 0xe7c0, 0xc89e, 0xe7ff, 0xc89e, 0x21, 0 - .dw 0xe840, 0xc89e, 0xe87f, 0xc89e, 0x21, 0 - .dw 0xe8c0, 0xc89e, 0xe8ff, 0xc89e, 0x21, 0 - .dw 0xe940, 0xc89e, 0xe97f, 0xc89e, 0x21, 0 - .dw 0xe9c0, 0xc89e, 0xe9ff, 0xc89e, 0x21, 0 - .dw 0xea40, 0xc89e, 0xea7f, 0xc89e, 0x21, 0 - .dw 0xeac0, 0xc89e, 0xeaff, 0xc89e, 0x21, 0 - .dw 0xeb40, 0xc89e, 0xeb7f, 0xc89e, 0x21, 0 - .dw 0xebc0, 0xc89e, 0xebff, 0xc89e, 0x21, 0 - .dw 0xec40, 0xc89e, 0xec7f, 0xc89e, 0x21, 0 - .dw 0xecc0, 0xc89e, 0xecff, 0xc89e, 0x21, 0 - .dw 0xed40, 0xc89e, 0xed7f, 0xc89e, 0x21, 0 - .dw 0xedc0, 0xc89e, 0xedff, 0xc89e, 0x21, 0 - .dw 0xee40, 0xc89e, 0xee7f, 0xc89e, 0x21, 0 - .dw 0xeec0, 0xc89e, 0xeeff, 0xc89e, 0x21, 0 - .dw 0xef40, 0xc89e, 0xef7f, 0xc89e, 0x21, 0 - .dw 0xefc0, 0xc89e, 0xefff, 0xc89e, 0x21, 0 - .dw 0xf040, 0xc89e, 0xf07f, 0xc89e, 0x21, 0 - .dw 0xf0c0, 0xc89e, 0xf0ff, 0xc89e, 0x21, 0 - .dw 0xf140, 0xc89e, 0xf17f, 0xc89e, 0x21, 0 - .dw 0xf1c0, 0xc89e, 0xf1ff, 0xc89e, 0x21, 0 - .dw 0xf240, 0xc89e, 0xf27f, 0xc89e, 0x21, 0 - .dw 0xf2c0, 0xc89e, 0xf2ff, 0xc89e, 0x21, 0 - .dw 0xf340, 0xc89e, 0xf37f, 0xc89e, 0x21, 0 - .dw 0xf3c0, 0xc89e, 0xf3ff, 0xc89e, 0x21, 0 - .dw 0xf440, 0xc89e, 0xf47f, 0xc89e, 0x21, 0 - .dw 0xf4c0, 0xc89e, 0xf4ff, 0xc89e, 0x21, 0 - .dw 0xf540, 0xc89e, 0xf57f, 0xc89e, 0x21, 0 - .dw 0xf5c0, 0xc89e, 0xf5ff, 0xc89e, 0x21, 0 - .dw 0xf640, 0xc89e, 0xf67f, 0xc89e, 0x21, 0 - .dw 0xf6c0, 0xc89e, 0xf6ff, 0xc89e, 0x21, 0 - .dw 0xf740, 0xc89e, 0xf77f, 0xc89e, 0x21, 0 - .dw 0xf7c0, 0xc89e, 0xf7ff, 0xc89e, 0x21, 0 - .dw 0xf840, 0xc89e, 0xf87f, 0xc89e, 0x21, 0 - .dw 0xf8c0, 0xc89e, 0xf8ff, 0xc89e, 0x21, 0 - .dw 0xf940, 0xc89e, 0xf97f, 0xc89e, 0x21, 0 - .dw 0xf9c0, 0xc89e, 0xffff, 0xc89e, 0x21, 0 - .dw 0x0040, 0xc89f, 0x007f, 0xc89f, 0x21, 0 - .dw 0x00c0, 0xc89f, 0x00ff, 0xc89f, 0x21, 0 - .dw 0x0140, 0xc89f, 0x017f, 0xc89f, 0x21, 0 - .dw 0x01c0, 0xc89f, 0x01ff, 0xc89f, 0x21, 0 - .dw 0x0240, 0xc89f, 0x027f, 0xc89f, 0x21, 0 - .dw 0x02c0, 0xc89f, 0x02ff, 0xc89f, 0x21, 0 - .dw 0x0340, 0xc89f, 0x037f, 0xc89f, 0x21, 0 - .dw 0x03c0, 0xc89f, 0x03ff, 0xc89f, 0x21, 0 - .dw 0x0440, 0xc89f, 0x047f, 0xc89f, 0x21, 0 - .dw 0x04c0, 0xc89f, 0x04ff, 0xc89f, 0x21, 0 - .dw 0x0540, 0xc89f, 0x057f, 0xc89f, 0x21, 0 - .dw 0x05c0, 0xc89f, 0x05ff, 0xc89f, 0x21, 0 - .dw 0x0640, 0xc89f, 0x067f, 0xc89f, 0x21, 0 - .dw 0x06c0, 0xc89f, 0x06ff, 0xc89f, 0x21, 0 - .dw 0x0740, 0xc89f, 0x077f, 0xc89f, 0x21, 0 - .dw 0x07c0, 0xc89f, 0x07ff, 0xc89f, 0x21, 0 - .dw 0x0840, 0xc89f, 0x087f, 0xc89f, 0x21, 0 - .dw 0x08c0, 0xc89f, 0x08ff, 0xc89f, 0x21, 0 - .dw 0x0940, 0xc89f, 0x097f, 0xc89f, 0x21, 0 - .dw 0x09c0, 0xc89f, 0x09ff, 0xc89f, 0x21, 0 - .dw 0x0a40, 0xc89f, 0x0a7f, 0xc89f, 0x21, 0 - .dw 0x0ac0, 0xc89f, 0x0aff, 0xc89f, 0x21, 0 - .dw 0x0b40, 0xc89f, 0x0b7f, 0xc89f, 0x21, 0 - .dw 0x0bc0, 0xc89f, 0x0bff, 0xc89f, 0x21, 0 - .dw 0x0c40, 0xc89f, 0x0c7f, 0xc89f, 0x21, 0 - .dw 0x0cc0, 0xc89f, 0x0cff, 0xc89f, 0x21, 0 - .dw 0x0d40, 0xc89f, 0x0d7f, 0xc89f, 0x21, 0 - .dw 0x0dc0, 0xc89f, 0x0dff, 0xc89f, 0x21, 0 - .dw 0x0e40, 0xc89f, 0x0e7f, 0xc89f, 0x21, 0 - .dw 0x0ec0, 0xc89f, 0x0eff, 0xc89f, 0x21, 0 - .dw 0x0f40, 0xc89f, 0x0f7f, 0xc89f, 0x21, 0 - .dw 0x0fc0, 0xc89f, 0x0fff, 0xc89f, 0x21, 0 - .dw 0x1040, 0xc89f, 0x107f, 0xc89f, 0x21, 0 - .dw 0x10c0, 0xc89f, 0x10ff, 0xc89f, 0x21, 0 - .dw 0x1140, 0xc89f, 0x117f, 0xc89f, 0x21, 0 - .dw 0x11c0, 0xc89f, 0x11ff, 0xc89f, 0x21, 0 - .dw 0x1240, 0xc89f, 0x127f, 0xc89f, 0x21, 0 - .dw 0x12c0, 0xc89f, 0x12ff, 0xc89f, 0x21, 0 - .dw 0x1340, 0xc89f, 0x137f, 0xc89f, 0x21, 0 - .dw 0x13c0, 0xc89f, 0x13ff, 0xc89f, 0x21, 0 - .dw 0x1440, 0xc89f, 0x147f, 0xc89f, 0x21, 0 - .dw 0x14c0, 0xc89f, 0x14ff, 0xc89f, 0x21, 0 - .dw 0x1540, 0xc89f, 0x157f, 0xc89f, 0x21, 0 - .dw 0x15c0, 0xc89f, 0x15ff, 0xc89f, 0x21, 0 - .dw 0x1640, 0xc89f, 0x167f, 0xc89f, 0x21, 0 - .dw 0x16c0, 0xc89f, 0x16ff, 0xc89f, 0x21, 0 - .dw 0x1740, 0xc89f, 0x177f, 0xc89f, 0x21, 0 - .dw 0x17c0, 0xc89f, 0x17ff, 0xc89f, 0x21, 0 - .dw 0x1840, 0xc89f, 0x187f, 0xc89f, 0x21, 0 - .dw 0x18c0, 0xc89f, 0x18ff, 0xc89f, 0x21, 0 - .dw 0x1940, 0xc89f, 0x197f, 0xc89f, 0x21, 0 - .dw 0x19c0, 0xc89f, 0x1fff, 0xc89f, 0x21, 0 - .dw 0x2040, 0xc89f, 0x207f, 0xc89f, 0x21, 0 - .dw 0x20c0, 0xc89f, 0x20ff, 0xc89f, 0x21, 0 - .dw 0x2140, 0xc89f, 0x217f, 0xc89f, 0x21, 0 - .dw 0x21c0, 0xc89f, 0x21ff, 0xc89f, 0x21, 0 - .dw 0x2240, 0xc89f, 0x227f, 0xc89f, 0x21, 0 - .dw 0x22c0, 0xc89f, 0x22ff, 0xc89f, 0x21, 0 - .dw 0x2340, 0xc89f, 0x237f, 0xc89f, 0x21, 0 - .dw 0x23c0, 0xc89f, 0x23ff, 0xc89f, 0x21, 0 - .dw 0x2440, 0xc89f, 0x247f, 0xc89f, 0x21, 0 - .dw 0x24c0, 0xc89f, 0x24ff, 0xc89f, 0x21, 0 - .dw 0x2540, 0xc89f, 0x257f, 0xc89f, 0x21, 0 - .dw 0x25c0, 0xc89f, 0x25ff, 0xc89f, 0x21, 0 - .dw 0x2640, 0xc89f, 0x267f, 0xc89f, 0x21, 0 - .dw 0x26c0, 0xc89f, 0x26ff, 0xc89f, 0x21, 0 - .dw 0x2740, 0xc89f, 0x277f, 0xc89f, 0x21, 0 - .dw 0x27c0, 0xc89f, 0x27ff, 0xc89f, 0x21, 0 - .dw 0x2840, 0xc89f, 0x287f, 0xc89f, 0x21, 0 - .dw 0x28c0, 0xc89f, 0x28ff, 0xc89f, 0x21, 0 - .dw 0x2940, 0xc89f, 0x297f, 0xc89f, 0x21, 0 - .dw 0x29c0, 0xc89f, 0x29ff, 0xc89f, 0x21, 0 - .dw 0x2a40, 0xc89f, 0x2a7f, 0xc89f, 0x21, 0 - .dw 0x2ac0, 0xc89f, 0x2aff, 0xc89f, 0x21, 0 - .dw 0x2b40, 0xc89f, 0x2b7f, 0xc89f, 0x21, 0 - .dw 0x2bc0, 0xc89f, 0x2bff, 0xc89f, 0x21, 0 - .dw 0x2c40, 0xc89f, 0x2c7f, 0xc89f, 0x21, 0 - .dw 0x2cc0, 0xc89f, 0x2cff, 0xc89f, 0x21, 0 - .dw 0x2d40, 0xc89f, 0x2d7f, 0xc89f, 0x21, 0 - .dw 0x2dc0, 0xc89f, 0x2dff, 0xc89f, 0x21, 0 - .dw 0x2e40, 0xc89f, 0x2e7f, 0xc89f, 0x21, 0 - .dw 0x2ec0, 0xc89f, 0x2eff, 0xc89f, 0x21, 0 - .dw 0x2f40, 0xc89f, 0x2f7f, 0xc89f, 0x21, 0 - .dw 0x2fc0, 0xc89f, 0x2fff, 0xc89f, 0x21, 0 - .dw 0x3040, 0xc89f, 0x307f, 0xc89f, 0x21, 0 - .dw 0x30c0, 0xc89f, 0x30ff, 0xc89f, 0x21, 0 - .dw 0x3140, 0xc89f, 0x317f, 0xc89f, 0x21, 0 - .dw 0x31c0, 0xc89f, 0x31ff, 0xc89f, 0x21, 0 - .dw 0x3240, 0xc89f, 0x327f, 0xc89f, 0x21, 0 - .dw 0x32c0, 0xc89f, 0x32ff, 0xc89f, 0x21, 0 - .dw 0x3340, 0xc89f, 0x337f, 0xc89f, 0x21, 0 - .dw 0x33c0, 0xc89f, 0x33ff, 0xc89f, 0x21, 0 - .dw 0x3440, 0xc89f, 0x347f, 0xc89f, 0x21, 0 - .dw 0x34c0, 0xc89f, 0x34ff, 0xc89f, 0x21, 0 - .dw 0x3540, 0xc89f, 0x357f, 0xc89f, 0x21, 0 - .dw 0x35c0, 0xc89f, 0x35ff, 0xc89f, 0x21, 0 - .dw 0x3640, 0xc89f, 0x367f, 0xc89f, 0x21, 0 - .dw 0x36c0, 0xc89f, 0x36ff, 0xc89f, 0x21, 0 - .dw 0x3740, 0xc89f, 0x377f, 0xc89f, 0x21, 0 - .dw 0x37c0, 0xc89f, 0x37ff, 0xc89f, 0x21, 0 - .dw 0x3840, 0xc89f, 0x387f, 0xc89f, 0x21, 0 - .dw 0x38c0, 0xc89f, 0x38ff, 0xc89f, 0x21, 0 - .dw 0x3940, 0xc89f, 0x397f, 0xc89f, 0x21, 0 - .dw 0x39c0, 0xc89f, 0x1fff, 0xc8c0, 0x21, 0 - .dw 0x3a00, 0xc8c0, 0x5fff, 0xc8c0, 0x21, 0 - .dw 0x7a00, 0xc8c0, 0x9fff, 0xc8c0, 0x21, 0 - .dw 0xba00, 0xc8c0, 0xdfff, 0xc8c0, 0x21, 0 - .dw 0xfa00, 0xc8c0, 0x1fff, 0xc8c1, 0x21, 0 - .dw 0x3a00, 0xc8c1, 0x5fff, 0xc8c1, 0x21, 0 - .dw 0x7a00, 0xc8c1, 0x9fff, 0xc8c1, 0x21, 0 - .dw 0xba00, 0xc8c1, 0xdfff, 0xc8c1, 0x21, 0 - .dw 0xfa00, 0xc8c1, 0x1fff, 0xc8c2, 0x21, 0 - .dw 0x3a00, 0xc8c2, 0x5fff, 0xc8c2, 0x21, 0 - .dw 0x7a00, 0xc8c2, 0x9fff, 0xc8c2, 0x21, 0 - .dw 0xba00, 0xc8c2, 0xdfff, 0xc8c2, 0x21, 0 - .dw 0xfa00, 0xc8c2, 0x1fff, 0xc8c3, 0x21, 0 - .dw 0x3a00, 0xc8c3, 0xffff, 0xc8c3, 0x21, 0 - .dw 0x1a00, 0xc8c4, 0x1fff, 0xc8c4, 0x21, 0 - .dw 0x3a00, 0xc8c4, 0x3fff, 0xc8c4, 0x21, 0 - .dw 0x5a00, 0xc8c4, 0x5fff, 0xc8c4, 0x21, 0 - .dw 0x7a00, 0xc8c4, 0x7fff, 0xc8c4, 0x21, 0 - .dw 0x9a00, 0xc8c4, 0x9fff, 0xc8c4, 0x21, 0 - .dw 0xba00, 0xc8c4, 0xbfff, 0xc8c4, 0x21, 0 - .dw 0xda00, 0xc8c4, 0xdfff, 0xc8c4, 0x21, 0 - .dw 0xfa00, 0xc8c4, 0xffff, 0xc8c4, 0x21, 0 - .dw 0x1a00, 0xc8c5, 0x1fff, 0xc8c5, 0x21, 0 - .dw 0x3a00, 0xc8c5, 0x3fff, 0xc8c5, 0x21, 0 - .dw 0x5a00, 0xc8c5, 0x5fff, 0xc8c5, 0x21, 0 - .dw 0x7a00, 0xc8c5, 0x7fff, 0xc8c5, 0x21, 0 - .dw 0x9a00, 0xc8c5, 0x9fff, 0xc8c5, 0x21, 0 - .dw 0xba00, 0xc8c5, 0xbfff, 0xc8c5, 0x21, 0 - .dw 0xda00, 0xc8c5, 0xdfff, 0xc8c5, 0x21, 0 - .dw 0xfa00, 0xc8c5, 0xffff, 0xc8c5, 0x21, 0 - .dw 0x1a00, 0xc8c6, 0x1fff, 0xc8c6, 0x21, 0 - .dw 0x3a00, 0xc8c6, 0x3fff, 0xc8c6, 0x21, 0 - .dw 0x5a00, 0xc8c6, 0x5fff, 0xc8c6, 0x21, 0 - .dw 0x7a00, 0xc8c6, 0x7fff, 0xc8c6, 0x21, 0 - .dw 0x9a00, 0xc8c6, 0x9fff, 0xc8c6, 0x21, 0 - .dw 0xba00, 0xc8c6, 0xbfff, 0xc8c6, 0x21, 0 - .dw 0xda00, 0xc8c6, 0xdfff, 0xc8c6, 0x21, 0 - .dw 0xfa00, 0xc8c6, 0xffff, 0xc8c6, 0x21, 0 - .dw 0x1a00, 0xc8c7, 0x1fff, 0xc8c7, 0x21, 0 - .dw 0x3a00, 0xc8c7, 0x1fff, 0xc8d0, 0x21, 0 - .dw 0x3a00, 0xc8d0, 0x5fff, 0xc8d0, 0x21, 0 - .dw 0x7a00, 0xc8d0, 0x9fff, 0xc8d0, 0x21, 0 - .dw 0xba00, 0xc8d0, 0xdfff, 0xc8d0, 0x21, 0 - .dw 0xfa00, 0xc8d0, 0x1fff, 0xc8d1, 0x21, 0 - .dw 0x3a00, 0xc8d1, 0x5fff, 0xc8d1, 0x21, 0 - .dw 0x7a00, 0xc8d1, 0x9fff, 0xc8d1, 0x21, 0 - .dw 0xba00, 0xc8d1, 0xdfff, 0xc8d1, 0x21, 0 - .dw 0xfa00, 0xc8d1, 0x1fff, 0xc8d2, 0x21, 0 - .dw 0x3a00, 0xc8d2, 0x5fff, 0xc8d2, 0x21, 0 - .dw 0x7a00, 0xc8d2, 0x9fff, 0xc8d2, 0x21, 0 - .dw 0xba00, 0xc8d2, 0xdfff, 0xc8d2, 0x21, 0 - .dw 0xfa00, 0xc8d2, 0xffff, 0xc8d3, 0x21, 0 - .dw 0x1a00, 0xc8d4, 0x1fff, 0xc8d4, 0x21, 0 - .dw 0x3a00, 0xc8d4, 0x3fff, 0xc8d4, 0x21, 0 - .dw 0x5a00, 0xc8d4, 0x5fff, 0xc8d4, 0x21, 0 - .dw 0x7a00, 0xc8d4, 0x7fff, 0xc8d4, 0x21, 0 - .dw 0x9a00, 0xc8d4, 0x9fff, 0xc8d4, 0x21, 0 - .dw 0xba00, 0xc8d4, 0xbfff, 0xc8d4, 0x21, 0 - .dw 0xda00, 0xc8d4, 0xdfff, 0xc8d4, 0x21, 0 - .dw 0xfa00, 0xc8d4, 0xffff, 0xc8d4, 0x21, 0 - .dw 0x1a00, 0xc8d5, 0x1fff, 0xc8d5, 0x21, 0 - .dw 0x3a00, 0xc8d5, 0x3fff, 0xc8d5, 0x21, 0 - .dw 0x5a00, 0xc8d5, 0x5fff, 0xc8d5, 0x21, 0 - .dw 0x7a00, 0xc8d5, 0x7fff, 0xc8d5, 0x21, 0 - .dw 0x9a00, 0xc8d5, 0x9fff, 0xc8d5, 0x21, 0 - .dw 0xba00, 0xc8d5, 0xbfff, 0xc8d5, 0x21, 0 - .dw 0xda00, 0xc8d5, 0xdfff, 0xc8d5, 0x21, 0 - .dw 0xfa00, 0xc8d5, 0xffff, 0xc8d5, 0x21, 0 - .dw 0x1a00, 0xc8d6, 0x1fff, 0xc8d6, 0x21, 0 - .dw 0x3a00, 0xc8d6, 0x3fff, 0xc8d6, 0x21, 0 - .dw 0x5a00, 0xc8d6, 0x5fff, 0xc8d6, 0x21, 0 - .dw 0x7a00, 0xc8d6, 0x7fff, 0xc8d6, 0x21, 0 - .dw 0x9a00, 0xc8d6, 0x9fff, 0xc8d6, 0x21, 0 - .dw 0xba00, 0xc8d6, 0xbfff, 0xc8d6, 0x21, 0 - .dw 0xda00, 0xc8d6, 0xdfff, 0xc8d6, 0x21, 0 - .dw 0xfa00, 0xc8d6, 0xffff, 0xc8d6, 0x21, 0 - .dw 0x1a00, 0xc8d7, 0x1fff, 0xc8d7, 0x21, 0 - .dw 0x3a00, 0xc8d7, 0xffff, 0xc8ff, 0x21, 0 - .dw 0x1a00, 0xc900, 0x1fff, 0xc900, 0x21, 0 - .dw 0x3a00, 0xc900, 0x3fff, 0xc900, 0x21, 0 - .dw 0x5a00, 0xc900, 0x5fff, 0xc900, 0x21, 0 - .dw 0x7a00, 0xc900, 0x7fff, 0xc900, 0x21, 0 - .dw 0x9a00, 0xc900, 0x9fff, 0xc900, 0x21, 0 - .dw 0xba00, 0xc900, 0xbfff, 0xc900, 0x21, 0 - .dw 0xda00, 0xc900, 0xdfff, 0xc900, 0x21, 0 - .dw 0xfa00, 0xc900, 0xffff, 0xc900, 0x21, 0 - .dw 0x1a00, 0xc901, 0x1fff, 0xc901, 0x21, 0 - .dw 0x3a00, 0xc901, 0x3fff, 0xc901, 0x21, 0 - .dw 0x5a00, 0xc901, 0x5fff, 0xc901, 0x21, 0 - .dw 0x7a00, 0xc901, 0x7fff, 0xc901, 0x21, 0 - .dw 0x9a00, 0xc901, 0x9fff, 0xc901, 0x21, 0 - .dw 0xba00, 0xc901, 0xbfff, 0xc901, 0x21, 0 - .dw 0xda00, 0xc901, 0xdfff, 0xc901, 0x21, 0 - .dw 0xfa00, 0xc901, 0xffff, 0xc901, 0x21, 0 - .dw 0x1a00, 0xc902, 0x1fff, 0xc902, 0x21, 0 - .dw 0x3a00, 0xc902, 0x3fff, 0xc902, 0x21, 0 - .dw 0x5a00, 0xc902, 0x5fff, 0xc902, 0x21, 0 - .dw 0x7a00, 0xc902, 0x7fff, 0xc902, 0x21, 0 - .dw 0x9a00, 0xc902, 0x9fff, 0xc902, 0x21, 0 - .dw 0xba00, 0xc902, 0xbfff, 0xc902, 0x21, 0 - .dw 0xda00, 0xc902, 0xdfff, 0xc902, 0x21, 0 - .dw 0xfa00, 0xc902, 0xffff, 0xc902, 0x21, 0 - .dw 0x1a00, 0xc903, 0x1fff, 0xc903, 0x21, 0 - .dw 0x3a00, 0xc903, 0xffff, 0xc903, 0x21, 0 - .dw 0x1a00, 0xc904, 0x1fff, 0xc904, 0x21, 0 - .dw 0x3a00, 0xc904, 0x3fff, 0xc904, 0x21, 0 - .dw 0x5a00, 0xc904, 0x5fff, 0xc904, 0x21, 0 - .dw 0x7a00, 0xc904, 0x7fff, 0xc904, 0x21, 0 - .dw 0x9a00, 0xc904, 0x9fff, 0xc904, 0x21, 0 - .dw 0xba00, 0xc904, 0xbfff, 0xc904, 0x21, 0 - .dw 0xda00, 0xc904, 0xdfff, 0xc904, 0x21, 0 - .dw 0xfa00, 0xc904, 0xffff, 0xc904, 0x21, 0 - .dw 0x1a00, 0xc905, 0x1fff, 0xc905, 0x21, 0 - .dw 0x3a00, 0xc905, 0x3fff, 0xc905, 0x21, 0 - .dw 0x5a00, 0xc905, 0x5fff, 0xc905, 0x21, 0 - .dw 0x7a00, 0xc905, 0x7fff, 0xc905, 0x21, 0 - .dw 0x9a00, 0xc905, 0x9fff, 0xc905, 0x21, 0 - .dw 0xba00, 0xc905, 0xbfff, 0xc905, 0x21, 0 - .dw 0xda00, 0xc905, 0xdfff, 0xc905, 0x21, 0 - .dw 0xfa00, 0xc905, 0xffff, 0xc905, 0x21, 0 - .dw 0x1a00, 0xc906, 0x1fff, 0xc906, 0x21, 0 - .dw 0x3a00, 0xc906, 0x3fff, 0xc906, 0x21, 0 - .dw 0x5a00, 0xc906, 0x5fff, 0xc906, 0x21, 0 - .dw 0x7a00, 0xc906, 0x7fff, 0xc906, 0x21, 0 - .dw 0x9a00, 0xc906, 0x9fff, 0xc906, 0x21, 0 - .dw 0xba00, 0xc906, 0xbfff, 0xc906, 0x21, 0 - .dw 0xda00, 0xc906, 0xdfff, 0xc906, 0x21, 0 - .dw 0xfa00, 0xc906, 0xffff, 0xc906, 0x21, 0 - .dw 0x1a00, 0xc907, 0x1fff, 0xc907, 0x21, 0 - .dw 0x3a00, 0xc907, 0x1fff, 0xc908, 0x21, 0 - .dw 0x2040, 0xc908, 0x207f, 0xc908, 0x21, 0 - .dw 0x20c0, 0xc908, 0x20ff, 0xc908, 0x21, 0 - .dw 0x2140, 0xc908, 0x217f, 0xc908, 0x21, 0 - .dw 0x21c0, 0xc908, 0x21ff, 0xc908, 0x21, 0 - .dw 0x2240, 0xc908, 0x227f, 0xc908, 0x21, 0 - .dw 0x22c0, 0xc908, 0x22ff, 0xc908, 0x21, 0 - .dw 0x2340, 0xc908, 0x237f, 0xc908, 0x21, 0 - .dw 0x23c0, 0xc908, 0x23ff, 0xc908, 0x21, 0 - .dw 0x2440, 0xc908, 0x247f, 0xc908, 0x21, 0 - .dw 0x24c0, 0xc908, 0x24ff, 0xc908, 0x21, 0 - .dw 0x2540, 0xc908, 0x257f, 0xc908, 0x21, 0 - .dw 0x25c0, 0xc908, 0x25ff, 0xc908, 0x21, 0 - .dw 0x2640, 0xc908, 0x267f, 0xc908, 0x21, 0 - .dw 0x26c0, 0xc908, 0x26ff, 0xc908, 0x21, 0 - .dw 0x2740, 0xc908, 0x277f, 0xc908, 0x21, 0 - .dw 0x27c0, 0xc908, 0x27ff, 0xc908, 0x21, 0 - .dw 0x2840, 0xc908, 0x287f, 0xc908, 0x21, 0 - .dw 0x28c0, 0xc908, 0x28ff, 0xc908, 0x21, 0 - .dw 0x2940, 0xc908, 0x297f, 0xc908, 0x21, 0 - .dw 0x29c0, 0xc908, 0x29ff, 0xc908, 0x21, 0 - .dw 0x2a40, 0xc908, 0x2a7f, 0xc908, 0x21, 0 - .dw 0x2ac0, 0xc908, 0x2aff, 0xc908, 0x21, 0 - .dw 0x2b40, 0xc908, 0x2b7f, 0xc908, 0x21, 0 - .dw 0x2bc0, 0xc908, 0x2bff, 0xc908, 0x21, 0 - .dw 0x2c40, 0xc908, 0x2c7f, 0xc908, 0x21, 0 - .dw 0x2cc0, 0xc908, 0x2cff, 0xc908, 0x21, 0 - .dw 0x2d40, 0xc908, 0x2d7f, 0xc908, 0x21, 0 - .dw 0x2dc0, 0xc908, 0x2dff, 0xc908, 0x21, 0 - .dw 0x2e40, 0xc908, 0x2e7f, 0xc908, 0x21, 0 - .dw 0x2ec0, 0xc908, 0x2eff, 0xc908, 0x21, 0 - .dw 0x2f40, 0xc908, 0x2f7f, 0xc908, 0x21, 0 - .dw 0x2fc0, 0xc908, 0x2fff, 0xc908, 0x21, 0 - .dw 0x3040, 0xc908, 0x307f, 0xc908, 0x21, 0 - .dw 0x30c0, 0xc908, 0x30ff, 0xc908, 0x21, 0 - .dw 0x3140, 0xc908, 0x317f, 0xc908, 0x21, 0 - .dw 0x31c0, 0xc908, 0x31ff, 0xc908, 0x21, 0 - .dw 0x3240, 0xc908, 0x327f, 0xc908, 0x21, 0 - .dw 0x32c0, 0xc908, 0x32ff, 0xc908, 0x21, 0 - .dw 0x3340, 0xc908, 0x337f, 0xc908, 0x21, 0 - .dw 0x33c0, 0xc908, 0x33ff, 0xc908, 0x21, 0 - .dw 0x3440, 0xc908, 0x347f, 0xc908, 0x21, 0 - .dw 0x34c0, 0xc908, 0x34ff, 0xc908, 0x21, 0 - .dw 0x3540, 0xc908, 0x357f, 0xc908, 0x21, 0 - .dw 0x35c0, 0xc908, 0x35ff, 0xc908, 0x21, 0 - .dw 0x3640, 0xc908, 0x367f, 0xc908, 0x21, 0 - .dw 0x36c0, 0xc908, 0x36ff, 0xc908, 0x21, 0 - .dw 0x3740, 0xc908, 0x377f, 0xc908, 0x21, 0 - .dw 0x37c0, 0xc908, 0x37ff, 0xc908, 0x21, 0 - .dw 0x3840, 0xc908, 0x387f, 0xc908, 0x21, 0 - .dw 0x38c0, 0xc908, 0x38ff, 0xc908, 0x21, 0 - .dw 0x3940, 0xc908, 0x397f, 0xc908, 0x21, 0 - .dw 0x39c0, 0xc908, 0x5fff, 0xc908, 0x21, 0 - .dw 0x6040, 0xc908, 0x607f, 0xc908, 0x21, 0 - .dw 0x60c0, 0xc908, 0x60ff, 0xc908, 0x21, 0 - .dw 0x6140, 0xc908, 0x617f, 0xc908, 0x21, 0 - .dw 0x61c0, 0xc908, 0x61ff, 0xc908, 0x21, 0 - .dw 0x6240, 0xc908, 0x627f, 0xc908, 0x21, 0 - .dw 0x62c0, 0xc908, 0x62ff, 0xc908, 0x21, 0 - .dw 0x6340, 0xc908, 0x637f, 0xc908, 0x21, 0 - .dw 0x63c0, 0xc908, 0x63ff, 0xc908, 0x21, 0 - .dw 0x6440, 0xc908, 0x647f, 0xc908, 0x21, 0 - .dw 0x64c0, 0xc908, 0x64ff, 0xc908, 0x21, 0 - .dw 0x6540, 0xc908, 0x657f, 0xc908, 0x21, 0 - .dw 0x65c0, 0xc908, 0x65ff, 0xc908, 0x21, 0 - .dw 0x6640, 0xc908, 0x667f, 0xc908, 0x21, 0 - .dw 0x66c0, 0xc908, 0x66ff, 0xc908, 0x21, 0 - .dw 0x6740, 0xc908, 0x677f, 0xc908, 0x21, 0 - .dw 0x67c0, 0xc908, 0x67ff, 0xc908, 0x21, 0 - .dw 0x6840, 0xc908, 0x687f, 0xc908, 0x21, 0 - .dw 0x68c0, 0xc908, 0x68ff, 0xc908, 0x21, 0 - .dw 0x6940, 0xc908, 0x697f, 0xc908, 0x21, 0 - .dw 0x69c0, 0xc908, 0x69ff, 0xc908, 0x21, 0 - .dw 0x6a40, 0xc908, 0x6a7f, 0xc908, 0x21, 0 - .dw 0x6ac0, 0xc908, 0x6aff, 0xc908, 0x21, 0 - .dw 0x6b40, 0xc908, 0x6b7f, 0xc908, 0x21, 0 - .dw 0x6bc0, 0xc908, 0x6bff, 0xc908, 0x21, 0 - .dw 0x6c40, 0xc908, 0x6c7f, 0xc908, 0x21, 0 - .dw 0x6cc0, 0xc908, 0x6cff, 0xc908, 0x21, 0 - .dw 0x6d40, 0xc908, 0x6d7f, 0xc908, 0x21, 0 - .dw 0x6dc0, 0xc908, 0x6dff, 0xc908, 0x21, 0 - .dw 0x6e40, 0xc908, 0x6e7f, 0xc908, 0x21, 0 - .dw 0x6ec0, 0xc908, 0x6eff, 0xc908, 0x21, 0 - .dw 0x6f40, 0xc908, 0x6f7f, 0xc908, 0x21, 0 - .dw 0x6fc0, 0xc908, 0x6fff, 0xc908, 0x21, 0 - .dw 0x7040, 0xc908, 0x707f, 0xc908, 0x21, 0 - .dw 0x70c0, 0xc908, 0x70ff, 0xc908, 0x21, 0 - .dw 0x7140, 0xc908, 0x717f, 0xc908, 0x21, 0 - .dw 0x71c0, 0xc908, 0x71ff, 0xc908, 0x21, 0 - .dw 0x7240, 0xc908, 0x727f, 0xc908, 0x21, 0 - .dw 0x72c0, 0xc908, 0x72ff, 0xc908, 0x21, 0 - .dw 0x7340, 0xc908, 0x737f, 0xc908, 0x21, 0 - .dw 0x73c0, 0xc908, 0x73ff, 0xc908, 0x21, 0 - .dw 0x7440, 0xc908, 0x747f, 0xc908, 0x21, 0 - .dw 0x74c0, 0xc908, 0x74ff, 0xc908, 0x21, 0 - .dw 0x7540, 0xc908, 0x757f, 0xc908, 0x21, 0 - .dw 0x75c0, 0xc908, 0x75ff, 0xc908, 0x21, 0 - .dw 0x7640, 0xc908, 0x767f, 0xc908, 0x21, 0 - .dw 0x76c0, 0xc908, 0x76ff, 0xc908, 0x21, 0 - .dw 0x7740, 0xc908, 0x777f, 0xc908, 0x21, 0 - .dw 0x77c0, 0xc908, 0x77ff, 0xc908, 0x21, 0 - .dw 0x7840, 0xc908, 0x787f, 0xc908, 0x21, 0 - .dw 0x78c0, 0xc908, 0x78ff, 0xc908, 0x21, 0 - .dw 0x7940, 0xc908, 0x797f, 0xc908, 0x21, 0 - .dw 0x79c0, 0xc908, 0x9fff, 0xc908, 0x21, 0 - .dw 0xa040, 0xc908, 0xa07f, 0xc908, 0x21, 0 - .dw 0xa0c0, 0xc908, 0xa0ff, 0xc908, 0x21, 0 - .dw 0xa140, 0xc908, 0xa17f, 0xc908, 0x21, 0 - .dw 0xa1c0, 0xc908, 0xa1ff, 0xc908, 0x21, 0 - .dw 0xa240, 0xc908, 0xa27f, 0xc908, 0x21, 0 - .dw 0xa2c0, 0xc908, 0xa2ff, 0xc908, 0x21, 0 - .dw 0xa340, 0xc908, 0xa37f, 0xc908, 0x21, 0 - .dw 0xa3c0, 0xc908, 0xa3ff, 0xc908, 0x21, 0 - .dw 0xa440, 0xc908, 0xa47f, 0xc908, 0x21, 0 - .dw 0xa4c0, 0xc908, 0xa4ff, 0xc908, 0x21, 0 - .dw 0xa540, 0xc908, 0xa57f, 0xc908, 0x21, 0 - .dw 0xa5c0, 0xc908, 0xa5ff, 0xc908, 0x21, 0 - .dw 0xa640, 0xc908, 0xa67f, 0xc908, 0x21, 0 - .dw 0xa6c0, 0xc908, 0xa6ff, 0xc908, 0x21, 0 - .dw 0xa740, 0xc908, 0xa77f, 0xc908, 0x21, 0 - .dw 0xa7c0, 0xc908, 0xa7ff, 0xc908, 0x21, 0 - .dw 0xa840, 0xc908, 0xa87f, 0xc908, 0x21, 0 - .dw 0xa8c0, 0xc908, 0xa8ff, 0xc908, 0x21, 0 - .dw 0xa940, 0xc908, 0xa97f, 0xc908, 0x21, 0 - .dw 0xa9c0, 0xc908, 0xa9ff, 0xc908, 0x21, 0 - .dw 0xaa40, 0xc908, 0xaa7f, 0xc908, 0x21, 0 - .dw 0xaac0, 0xc908, 0xaaff, 0xc908, 0x21, 0 - .dw 0xab40, 0xc908, 0xab7f, 0xc908, 0x21, 0 - .dw 0xabc0, 0xc908, 0xabff, 0xc908, 0x21, 0 - .dw 0xac40, 0xc908, 0xac7f, 0xc908, 0x21, 0 - .dw 0xacc0, 0xc908, 0xacff, 0xc908, 0x21, 0 - .dw 0xad40, 0xc908, 0xad7f, 0xc908, 0x21, 0 - .dw 0xadc0, 0xc908, 0xadff, 0xc908, 0x21, 0 - .dw 0xae40, 0xc908, 0xae7f, 0xc908, 0x21, 0 - .dw 0xaec0, 0xc908, 0xaeff, 0xc908, 0x21, 0 - .dw 0xaf40, 0xc908, 0xaf7f, 0xc908, 0x21, 0 - .dw 0xafc0, 0xc908, 0xafff, 0xc908, 0x21, 0 - .dw 0xb040, 0xc908, 0xb07f, 0xc908, 0x21, 0 - .dw 0xb0c0, 0xc908, 0xb0ff, 0xc908, 0x21, 0 - .dw 0xb140, 0xc908, 0xb17f, 0xc908, 0x21, 0 - .dw 0xb1c0, 0xc908, 0xb1ff, 0xc908, 0x21, 0 - .dw 0xb240, 0xc908, 0xb27f, 0xc908, 0x21, 0 - .dw 0xb2c0, 0xc908, 0xb2ff, 0xc908, 0x21, 0 - .dw 0xb340, 0xc908, 0xb37f, 0xc908, 0x21, 0 - .dw 0xb3c0, 0xc908, 0xb3ff, 0xc908, 0x21, 0 - .dw 0xb440, 0xc908, 0xb47f, 0xc908, 0x21, 0 - .dw 0xb4c0, 0xc908, 0xb4ff, 0xc908, 0x21, 0 - .dw 0xb540, 0xc908, 0xb57f, 0xc908, 0x21, 0 - .dw 0xb5c0, 0xc908, 0xb5ff, 0xc908, 0x21, 0 - .dw 0xb640, 0xc908, 0xb67f, 0xc908, 0x21, 0 - .dw 0xb6c0, 0xc908, 0xb6ff, 0xc908, 0x21, 0 - .dw 0xb740, 0xc908, 0xb77f, 0xc908, 0x21, 0 - .dw 0xb7c0, 0xc908, 0xb7ff, 0xc908, 0x21, 0 - .dw 0xb840, 0xc908, 0xb87f, 0xc908, 0x21, 0 - .dw 0xb8c0, 0xc908, 0xb8ff, 0xc908, 0x21, 0 - .dw 0xb940, 0xc908, 0xb97f, 0xc908, 0x21, 0 - .dw 0xb9c0, 0xc908, 0xdfff, 0xc908, 0x21, 0 - .dw 0xe040, 0xc908, 0xe07f, 0xc908, 0x21, 0 - .dw 0xe0c0, 0xc908, 0xe0ff, 0xc908, 0x21, 0 - .dw 0xe140, 0xc908, 0xe17f, 0xc908, 0x21, 0 - .dw 0xe1c0, 0xc908, 0xe1ff, 0xc908, 0x21, 0 - .dw 0xe240, 0xc908, 0xe27f, 0xc908, 0x21, 0 - .dw 0xe2c0, 0xc908, 0xe2ff, 0xc908, 0x21, 0 - .dw 0xe340, 0xc908, 0xe37f, 0xc908, 0x21, 0 - .dw 0xe3c0, 0xc908, 0xe3ff, 0xc908, 0x21, 0 - .dw 0xe440, 0xc908, 0xe47f, 0xc908, 0x21, 0 - .dw 0xe4c0, 0xc908, 0xe4ff, 0xc908, 0x21, 0 - .dw 0xe540, 0xc908, 0xe57f, 0xc908, 0x21, 0 - .dw 0xe5c0, 0xc908, 0xe5ff, 0xc908, 0x21, 0 - .dw 0xe640, 0xc908, 0xe67f, 0xc908, 0x21, 0 - .dw 0xe6c0, 0xc908, 0xe6ff, 0xc908, 0x21, 0 - .dw 0xe740, 0xc908, 0xe77f, 0xc908, 0x21, 0 - .dw 0xe7c0, 0xc908, 0xe7ff, 0xc908, 0x21, 0 - .dw 0xe840, 0xc908, 0xe87f, 0xc908, 0x21, 0 - .dw 0xe8c0, 0xc908, 0xe8ff, 0xc908, 0x21, 0 - .dw 0xe940, 0xc908, 0xe97f, 0xc908, 0x21, 0 - .dw 0xe9c0, 0xc908, 0xe9ff, 0xc908, 0x21, 0 - .dw 0xea40, 0xc908, 0xea7f, 0xc908, 0x21, 0 - .dw 0xeac0, 0xc908, 0xeaff, 0xc908, 0x21, 0 - .dw 0xeb40, 0xc908, 0xeb7f, 0xc908, 0x21, 0 - .dw 0xebc0, 0xc908, 0xebff, 0xc908, 0x21, 0 - .dw 0xec40, 0xc908, 0xec7f, 0xc908, 0x21, 0 - .dw 0xecc0, 0xc908, 0xecff, 0xc908, 0x21, 0 - .dw 0xed40, 0xc908, 0xed7f, 0xc908, 0x21, 0 - .dw 0xedc0, 0xc908, 0xedff, 0xc908, 0x21, 0 - .dw 0xee40, 0xc908, 0xee7f, 0xc908, 0x21, 0 - .dw 0xeec0, 0xc908, 0xeeff, 0xc908, 0x21, 0 - .dw 0xef40, 0xc908, 0xef7f, 0xc908, 0x21, 0 - .dw 0xefc0, 0xc908, 0xefff, 0xc908, 0x21, 0 - .dw 0xf040, 0xc908, 0xf07f, 0xc908, 0x21, 0 - .dw 0xf0c0, 0xc908, 0xf0ff, 0xc908, 0x21, 0 - .dw 0xf140, 0xc908, 0xf17f, 0xc908, 0x21, 0 - .dw 0xf1c0, 0xc908, 0xf1ff, 0xc908, 0x21, 0 - .dw 0xf240, 0xc908, 0xf27f, 0xc908, 0x21, 0 - .dw 0xf2c0, 0xc908, 0xf2ff, 0xc908, 0x21, 0 - .dw 0xf340, 0xc908, 0xf37f, 0xc908, 0x21, 0 - .dw 0xf3c0, 0xc908, 0xf3ff, 0xc908, 0x21, 0 - .dw 0xf440, 0xc908, 0xf47f, 0xc908, 0x21, 0 - .dw 0xf4c0, 0xc908, 0xf4ff, 0xc908, 0x21, 0 - .dw 0xf540, 0xc908, 0xf57f, 0xc908, 0x21, 0 - .dw 0xf5c0, 0xc908, 0xf5ff, 0xc908, 0x21, 0 - .dw 0xf640, 0xc908, 0xf67f, 0xc908, 0x21, 0 - .dw 0xf6c0, 0xc908, 0xf6ff, 0xc908, 0x21, 0 - .dw 0xf740, 0xc908, 0xf77f, 0xc908, 0x21, 0 - .dw 0xf7c0, 0xc908, 0xf7ff, 0xc908, 0x21, 0 - .dw 0xf840, 0xc908, 0xf87f, 0xc908, 0x21, 0 - .dw 0xf8c0, 0xc908, 0xf8ff, 0xc908, 0x21, 0 - .dw 0xf940, 0xc908, 0xf97f, 0xc908, 0x21, 0 - .dw 0xf9c0, 0xc908, 0x1fff, 0xc909, 0x21, 0 - .dw 0x2040, 0xc909, 0x207f, 0xc909, 0x21, 0 - .dw 0x20c0, 0xc909, 0x20ff, 0xc909, 0x21, 0 - .dw 0x2140, 0xc909, 0x217f, 0xc909, 0x21, 0 - .dw 0x21c0, 0xc909, 0x21ff, 0xc909, 0x21, 0 - .dw 0x2240, 0xc909, 0x227f, 0xc909, 0x21, 0 - .dw 0x22c0, 0xc909, 0x22ff, 0xc909, 0x21, 0 - .dw 0x2340, 0xc909, 0x237f, 0xc909, 0x21, 0 - .dw 0x23c0, 0xc909, 0x23ff, 0xc909, 0x21, 0 - .dw 0x2440, 0xc909, 0x247f, 0xc909, 0x21, 0 - .dw 0x24c0, 0xc909, 0x24ff, 0xc909, 0x21, 0 - .dw 0x2540, 0xc909, 0x257f, 0xc909, 0x21, 0 - .dw 0x25c0, 0xc909, 0x25ff, 0xc909, 0x21, 0 - .dw 0x2640, 0xc909, 0x267f, 0xc909, 0x21, 0 - .dw 0x26c0, 0xc909, 0x26ff, 0xc909, 0x21, 0 - .dw 0x2740, 0xc909, 0x277f, 0xc909, 0x21, 0 - .dw 0x27c0, 0xc909, 0x27ff, 0xc909, 0x21, 0 - .dw 0x2840, 0xc909, 0x287f, 0xc909, 0x21, 0 - .dw 0x28c0, 0xc909, 0x28ff, 0xc909, 0x21, 0 - .dw 0x2940, 0xc909, 0x297f, 0xc909, 0x21, 0 - .dw 0x29c0, 0xc909, 0x29ff, 0xc909, 0x21, 0 - .dw 0x2a40, 0xc909, 0x2a7f, 0xc909, 0x21, 0 - .dw 0x2ac0, 0xc909, 0x2aff, 0xc909, 0x21, 0 - .dw 0x2b40, 0xc909, 0x2b7f, 0xc909, 0x21, 0 - .dw 0x2bc0, 0xc909, 0x2bff, 0xc909, 0x21, 0 - .dw 0x2c40, 0xc909, 0x2c7f, 0xc909, 0x21, 0 - .dw 0x2cc0, 0xc909, 0x2cff, 0xc909, 0x21, 0 - .dw 0x2d40, 0xc909, 0x2d7f, 0xc909, 0x21, 0 - .dw 0x2dc0, 0xc909, 0x2dff, 0xc909, 0x21, 0 - .dw 0x2e40, 0xc909, 0x2e7f, 0xc909, 0x21, 0 - .dw 0x2ec0, 0xc909, 0x2eff, 0xc909, 0x21, 0 - .dw 0x2f40, 0xc909, 0x2f7f, 0xc909, 0x21, 0 - .dw 0x2fc0, 0xc909, 0x2fff, 0xc909, 0x21, 0 - .dw 0x3040, 0xc909, 0x307f, 0xc909, 0x21, 0 - .dw 0x30c0, 0xc909, 0x30ff, 0xc909, 0x21, 0 - .dw 0x3140, 0xc909, 0x317f, 0xc909, 0x21, 0 - .dw 0x31c0, 0xc909, 0x31ff, 0xc909, 0x21, 0 - .dw 0x3240, 0xc909, 0x327f, 0xc909, 0x21, 0 - .dw 0x32c0, 0xc909, 0x32ff, 0xc909, 0x21, 0 - .dw 0x3340, 0xc909, 0x337f, 0xc909, 0x21, 0 - .dw 0x33c0, 0xc909, 0x33ff, 0xc909, 0x21, 0 - .dw 0x3440, 0xc909, 0x347f, 0xc909, 0x21, 0 - .dw 0x34c0, 0xc909, 0x34ff, 0xc909, 0x21, 0 - .dw 0x3540, 0xc909, 0x357f, 0xc909, 0x21, 0 - .dw 0x35c0, 0xc909, 0x35ff, 0xc909, 0x21, 0 - .dw 0x3640, 0xc909, 0x367f, 0xc909, 0x21, 0 - .dw 0x36c0, 0xc909, 0x36ff, 0xc909, 0x21, 0 - .dw 0x3740, 0xc909, 0x377f, 0xc909, 0x21, 0 - .dw 0x37c0, 0xc909, 0x37ff, 0xc909, 0x21, 0 - .dw 0x3840, 0xc909, 0x387f, 0xc909, 0x21, 0 - .dw 0x38c0, 0xc909, 0x38ff, 0xc909, 0x21, 0 - .dw 0x3940, 0xc909, 0x397f, 0xc909, 0x21, 0 - .dw 0x39c0, 0xc909, 0x5fff, 0xc909, 0x21, 0 - .dw 0x6040, 0xc909, 0x607f, 0xc909, 0x21, 0 - .dw 0x60c0, 0xc909, 0x60ff, 0xc909, 0x21, 0 - .dw 0x6140, 0xc909, 0x617f, 0xc909, 0x21, 0 - .dw 0x61c0, 0xc909, 0x61ff, 0xc909, 0x21, 0 - .dw 0x6240, 0xc909, 0x627f, 0xc909, 0x21, 0 - .dw 0x62c0, 0xc909, 0x62ff, 0xc909, 0x21, 0 - .dw 0x6340, 0xc909, 0x637f, 0xc909, 0x21, 0 - .dw 0x63c0, 0xc909, 0x63ff, 0xc909, 0x21, 0 - .dw 0x6440, 0xc909, 0x647f, 0xc909, 0x21, 0 - .dw 0x64c0, 0xc909, 0x64ff, 0xc909, 0x21, 0 - .dw 0x6540, 0xc909, 0x657f, 0xc909, 0x21, 0 - .dw 0x65c0, 0xc909, 0x65ff, 0xc909, 0x21, 0 - .dw 0x6640, 0xc909, 0x667f, 0xc909, 0x21, 0 - .dw 0x66c0, 0xc909, 0x66ff, 0xc909, 0x21, 0 - .dw 0x6740, 0xc909, 0x677f, 0xc909, 0x21, 0 - .dw 0x67c0, 0xc909, 0x67ff, 0xc909, 0x21, 0 - .dw 0x6840, 0xc909, 0x687f, 0xc909, 0x21, 0 - .dw 0x68c0, 0xc909, 0x68ff, 0xc909, 0x21, 0 - .dw 0x6940, 0xc909, 0x697f, 0xc909, 0x21, 0 - .dw 0x69c0, 0xc909, 0x69ff, 0xc909, 0x21, 0 - .dw 0x6a40, 0xc909, 0x6a7f, 0xc909, 0x21, 0 - .dw 0x6ac0, 0xc909, 0x6aff, 0xc909, 0x21, 0 - .dw 0x6b40, 0xc909, 0x6b7f, 0xc909, 0x21, 0 - .dw 0x6bc0, 0xc909, 0x6bff, 0xc909, 0x21, 0 - .dw 0x6c40, 0xc909, 0x6c7f, 0xc909, 0x21, 0 - .dw 0x6cc0, 0xc909, 0x6cff, 0xc909, 0x21, 0 - .dw 0x6d40, 0xc909, 0x6d7f, 0xc909, 0x21, 0 - .dw 0x6dc0, 0xc909, 0x6dff, 0xc909, 0x21, 0 - .dw 0x6e40, 0xc909, 0x6e7f, 0xc909, 0x21, 0 - .dw 0x6ec0, 0xc909, 0x6eff, 0xc909, 0x21, 0 - .dw 0x6f40, 0xc909, 0x6f7f, 0xc909, 0x21, 0 - .dw 0x6fc0, 0xc909, 0x6fff, 0xc909, 0x21, 0 - .dw 0x7040, 0xc909, 0x707f, 0xc909, 0x21, 0 - .dw 0x70c0, 0xc909, 0x70ff, 0xc909, 0x21, 0 - .dw 0x7140, 0xc909, 0x717f, 0xc909, 0x21, 0 - .dw 0x71c0, 0xc909, 0x71ff, 0xc909, 0x21, 0 - .dw 0x7240, 0xc909, 0x727f, 0xc909, 0x21, 0 - .dw 0x72c0, 0xc909, 0x72ff, 0xc909, 0x21, 0 - .dw 0x7340, 0xc909, 0x737f, 0xc909, 0x21, 0 - .dw 0x73c0, 0xc909, 0x73ff, 0xc909, 0x21, 0 - .dw 0x7440, 0xc909, 0x747f, 0xc909, 0x21, 0 - .dw 0x74c0, 0xc909, 0x74ff, 0xc909, 0x21, 0 - .dw 0x7540, 0xc909, 0x757f, 0xc909, 0x21, 0 - .dw 0x75c0, 0xc909, 0x75ff, 0xc909, 0x21, 0 - .dw 0x7640, 0xc909, 0x767f, 0xc909, 0x21, 0 - .dw 0x76c0, 0xc909, 0x76ff, 0xc909, 0x21, 0 - .dw 0x7740, 0xc909, 0x777f, 0xc909, 0x21, 0 - .dw 0x77c0, 0xc909, 0x77ff, 0xc909, 0x21, 0 - .dw 0x7840, 0xc909, 0x787f, 0xc909, 0x21, 0 - .dw 0x78c0, 0xc909, 0x78ff, 0xc909, 0x21, 0 - .dw 0x7940, 0xc909, 0x797f, 0xc909, 0x21, 0 - .dw 0x79c0, 0xc909, 0x9fff, 0xc909, 0x21, 0 - .dw 0xa040, 0xc909, 0xa07f, 0xc909, 0x21, 0 - .dw 0xa0c0, 0xc909, 0xa0ff, 0xc909, 0x21, 0 - .dw 0xa140, 0xc909, 0xa17f, 0xc909, 0x21, 0 - .dw 0xa1c0, 0xc909, 0xa1ff, 0xc909, 0x21, 0 - .dw 0xa240, 0xc909, 0xa27f, 0xc909, 0x21, 0 - .dw 0xa2c0, 0xc909, 0xa2ff, 0xc909, 0x21, 0 - .dw 0xa340, 0xc909, 0xa37f, 0xc909, 0x21, 0 - .dw 0xa3c0, 0xc909, 0xa3ff, 0xc909, 0x21, 0 - .dw 0xa440, 0xc909, 0xa47f, 0xc909, 0x21, 0 - .dw 0xa4c0, 0xc909, 0xa4ff, 0xc909, 0x21, 0 - .dw 0xa540, 0xc909, 0xa57f, 0xc909, 0x21, 0 - .dw 0xa5c0, 0xc909, 0xa5ff, 0xc909, 0x21, 0 - .dw 0xa640, 0xc909, 0xa67f, 0xc909, 0x21, 0 - .dw 0xa6c0, 0xc909, 0xa6ff, 0xc909, 0x21, 0 - .dw 0xa740, 0xc909, 0xa77f, 0xc909, 0x21, 0 - .dw 0xa7c0, 0xc909, 0xa7ff, 0xc909, 0x21, 0 - .dw 0xa840, 0xc909, 0xa87f, 0xc909, 0x21, 0 - .dw 0xa8c0, 0xc909, 0xa8ff, 0xc909, 0x21, 0 - .dw 0xa940, 0xc909, 0xa97f, 0xc909, 0x21, 0 - .dw 0xa9c0, 0xc909, 0xa9ff, 0xc909, 0x21, 0 - .dw 0xaa40, 0xc909, 0xaa7f, 0xc909, 0x21, 0 - .dw 0xaac0, 0xc909, 0xaaff, 0xc909, 0x21, 0 - .dw 0xab40, 0xc909, 0xab7f, 0xc909, 0x21, 0 - .dw 0xabc0, 0xc909, 0xabff, 0xc909, 0x21, 0 - .dw 0xac40, 0xc909, 0xac7f, 0xc909, 0x21, 0 - .dw 0xacc0, 0xc909, 0xacff, 0xc909, 0x21, 0 - .dw 0xad40, 0xc909, 0xad7f, 0xc909, 0x21, 0 - .dw 0xadc0, 0xc909, 0xadff, 0xc909, 0x21, 0 - .dw 0xae40, 0xc909, 0xae7f, 0xc909, 0x21, 0 - .dw 0xaec0, 0xc909, 0xaeff, 0xc909, 0x21, 0 - .dw 0xaf40, 0xc909, 0xaf7f, 0xc909, 0x21, 0 - .dw 0xafc0, 0xc909, 0xafff, 0xc909, 0x21, 0 - .dw 0xb040, 0xc909, 0xb07f, 0xc909, 0x21, 0 - .dw 0xb0c0, 0xc909, 0xb0ff, 0xc909, 0x21, 0 - .dw 0xb140, 0xc909, 0xb17f, 0xc909, 0x21, 0 - .dw 0xb1c0, 0xc909, 0xb1ff, 0xc909, 0x21, 0 - .dw 0xb240, 0xc909, 0xb27f, 0xc909, 0x21, 0 - .dw 0xb2c0, 0xc909, 0xb2ff, 0xc909, 0x21, 0 - .dw 0xb340, 0xc909, 0xb37f, 0xc909, 0x21, 0 - .dw 0xb3c0, 0xc909, 0xb3ff, 0xc909, 0x21, 0 - .dw 0xb440, 0xc909, 0xb47f, 0xc909, 0x21, 0 - .dw 0xb4c0, 0xc909, 0xb4ff, 0xc909, 0x21, 0 - .dw 0xb540, 0xc909, 0xb57f, 0xc909, 0x21, 0 - .dw 0xb5c0, 0xc909, 0xb5ff, 0xc909, 0x21, 0 - .dw 0xb640, 0xc909, 0xb67f, 0xc909, 0x21, 0 - .dw 0xb6c0, 0xc909, 0xb6ff, 0xc909, 0x21, 0 - .dw 0xb740, 0xc909, 0xb77f, 0xc909, 0x21, 0 - .dw 0xb7c0, 0xc909, 0xb7ff, 0xc909, 0x21, 0 - .dw 0xb840, 0xc909, 0xb87f, 0xc909, 0x21, 0 - .dw 0xb8c0, 0xc909, 0xb8ff, 0xc909, 0x21, 0 - .dw 0xb940, 0xc909, 0xb97f, 0xc909, 0x21, 0 - .dw 0xb9c0, 0xc909, 0xdfff, 0xc909, 0x21, 0 - .dw 0xe040, 0xc909, 0xe07f, 0xc909, 0x21, 0 - .dw 0xe0c0, 0xc909, 0xe0ff, 0xc909, 0x21, 0 - .dw 0xe140, 0xc909, 0xe17f, 0xc909, 0x21, 0 - .dw 0xe1c0, 0xc909, 0xe1ff, 0xc909, 0x21, 0 - .dw 0xe240, 0xc909, 0xe27f, 0xc909, 0x21, 0 - .dw 0xe2c0, 0xc909, 0xe2ff, 0xc909, 0x21, 0 - .dw 0xe340, 0xc909, 0xe37f, 0xc909, 0x21, 0 - .dw 0xe3c0, 0xc909, 0xe3ff, 0xc909, 0x21, 0 - .dw 0xe440, 0xc909, 0xe47f, 0xc909, 0x21, 0 - .dw 0xe4c0, 0xc909, 0xe4ff, 0xc909, 0x21, 0 - .dw 0xe540, 0xc909, 0xe57f, 0xc909, 0x21, 0 - .dw 0xe5c0, 0xc909, 0xe5ff, 0xc909, 0x21, 0 - .dw 0xe640, 0xc909, 0xe67f, 0xc909, 0x21, 0 - .dw 0xe6c0, 0xc909, 0xe6ff, 0xc909, 0x21, 0 - .dw 0xe740, 0xc909, 0xe77f, 0xc909, 0x21, 0 - .dw 0xe7c0, 0xc909, 0xe7ff, 0xc909, 0x21, 0 - .dw 0xe840, 0xc909, 0xe87f, 0xc909, 0x21, 0 - .dw 0xe8c0, 0xc909, 0xe8ff, 0xc909, 0x21, 0 - .dw 0xe940, 0xc909, 0xe97f, 0xc909, 0x21, 0 - .dw 0xe9c0, 0xc909, 0xe9ff, 0xc909, 0x21, 0 - .dw 0xea40, 0xc909, 0xea7f, 0xc909, 0x21, 0 - .dw 0xeac0, 0xc909, 0xeaff, 0xc909, 0x21, 0 - .dw 0xeb40, 0xc909, 0xeb7f, 0xc909, 0x21, 0 - .dw 0xebc0, 0xc909, 0xebff, 0xc909, 0x21, 0 - .dw 0xec40, 0xc909, 0xec7f, 0xc909, 0x21, 0 - .dw 0xecc0, 0xc909, 0xecff, 0xc909, 0x21, 0 - .dw 0xed40, 0xc909, 0xed7f, 0xc909, 0x21, 0 - .dw 0xedc0, 0xc909, 0xedff, 0xc909, 0x21, 0 - .dw 0xee40, 0xc909, 0xee7f, 0xc909, 0x21, 0 - .dw 0xeec0, 0xc909, 0xeeff, 0xc909, 0x21, 0 - .dw 0xef40, 0xc909, 0xef7f, 0xc909, 0x21, 0 - .dw 0xefc0, 0xc909, 0xefff, 0xc909, 0x21, 0 - .dw 0xf040, 0xc909, 0xf07f, 0xc909, 0x21, 0 - .dw 0xf0c0, 0xc909, 0xf0ff, 0xc909, 0x21, 0 - .dw 0xf140, 0xc909, 0xf17f, 0xc909, 0x21, 0 - .dw 0xf1c0, 0xc909, 0xf1ff, 0xc909, 0x21, 0 - .dw 0xf240, 0xc909, 0xf27f, 0xc909, 0x21, 0 - .dw 0xf2c0, 0xc909, 0xf2ff, 0xc909, 0x21, 0 - .dw 0xf340, 0xc909, 0xf37f, 0xc909, 0x21, 0 - .dw 0xf3c0, 0xc909, 0xf3ff, 0xc909, 0x21, 0 - .dw 0xf440, 0xc909, 0xf47f, 0xc909, 0x21, 0 - .dw 0xf4c0, 0xc909, 0xf4ff, 0xc909, 0x21, 0 - .dw 0xf540, 0xc909, 0xf57f, 0xc909, 0x21, 0 - .dw 0xf5c0, 0xc909, 0xf5ff, 0xc909, 0x21, 0 - .dw 0xf640, 0xc909, 0xf67f, 0xc909, 0x21, 0 - .dw 0xf6c0, 0xc909, 0xf6ff, 0xc909, 0x21, 0 - .dw 0xf740, 0xc909, 0xf77f, 0xc909, 0x21, 0 - .dw 0xf7c0, 0xc909, 0xf7ff, 0xc909, 0x21, 0 - .dw 0xf840, 0xc909, 0xf87f, 0xc909, 0x21, 0 - .dw 0xf8c0, 0xc909, 0xf8ff, 0xc909, 0x21, 0 - .dw 0xf940, 0xc909, 0xf97f, 0xc909, 0x21, 0 - .dw 0xf9c0, 0xc909, 0x1fff, 0xc90a, 0x21, 0 - .dw 0x2040, 0xc90a, 0x207f, 0xc90a, 0x21, 0 - .dw 0x20c0, 0xc90a, 0x20ff, 0xc90a, 0x21, 0 - .dw 0x2140, 0xc90a, 0x217f, 0xc90a, 0x21, 0 - .dw 0x21c0, 0xc90a, 0x21ff, 0xc90a, 0x21, 0 - .dw 0x2240, 0xc90a, 0x227f, 0xc90a, 0x21, 0 - .dw 0x22c0, 0xc90a, 0x22ff, 0xc90a, 0x21, 0 - .dw 0x2340, 0xc90a, 0x237f, 0xc90a, 0x21, 0 - .dw 0x23c0, 0xc90a, 0x23ff, 0xc90a, 0x21, 0 - .dw 0x2440, 0xc90a, 0x247f, 0xc90a, 0x21, 0 - .dw 0x24c0, 0xc90a, 0x24ff, 0xc90a, 0x21, 0 - .dw 0x2540, 0xc90a, 0x257f, 0xc90a, 0x21, 0 - .dw 0x25c0, 0xc90a, 0x25ff, 0xc90a, 0x21, 0 - .dw 0x2640, 0xc90a, 0x267f, 0xc90a, 0x21, 0 - .dw 0x26c0, 0xc90a, 0x26ff, 0xc90a, 0x21, 0 - .dw 0x2740, 0xc90a, 0x277f, 0xc90a, 0x21, 0 - .dw 0x27c0, 0xc90a, 0x27ff, 0xc90a, 0x21, 0 - .dw 0x2840, 0xc90a, 0x287f, 0xc90a, 0x21, 0 - .dw 0x28c0, 0xc90a, 0x28ff, 0xc90a, 0x21, 0 - .dw 0x2940, 0xc90a, 0x297f, 0xc90a, 0x21, 0 - .dw 0x29c0, 0xc90a, 0x29ff, 0xc90a, 0x21, 0 - .dw 0x2a40, 0xc90a, 0x2a7f, 0xc90a, 0x21, 0 - .dw 0x2ac0, 0xc90a, 0x2aff, 0xc90a, 0x21, 0 - .dw 0x2b40, 0xc90a, 0x2b7f, 0xc90a, 0x21, 0 - .dw 0x2bc0, 0xc90a, 0x2bff, 0xc90a, 0x21, 0 - .dw 0x2c40, 0xc90a, 0x2c7f, 0xc90a, 0x21, 0 - .dw 0x2cc0, 0xc90a, 0x2cff, 0xc90a, 0x21, 0 - .dw 0x2d40, 0xc90a, 0x2d7f, 0xc90a, 0x21, 0 - .dw 0x2dc0, 0xc90a, 0x2dff, 0xc90a, 0x21, 0 - .dw 0x2e40, 0xc90a, 0x2e7f, 0xc90a, 0x21, 0 - .dw 0x2ec0, 0xc90a, 0x2eff, 0xc90a, 0x21, 0 - .dw 0x2f40, 0xc90a, 0x2f7f, 0xc90a, 0x21, 0 - .dw 0x2fc0, 0xc90a, 0x2fff, 0xc90a, 0x21, 0 - .dw 0x3040, 0xc90a, 0x307f, 0xc90a, 0x21, 0 - .dw 0x30c0, 0xc90a, 0x30ff, 0xc90a, 0x21, 0 - .dw 0x3140, 0xc90a, 0x317f, 0xc90a, 0x21, 0 - .dw 0x31c0, 0xc90a, 0x31ff, 0xc90a, 0x21, 0 - .dw 0x3240, 0xc90a, 0x327f, 0xc90a, 0x21, 0 - .dw 0x32c0, 0xc90a, 0x32ff, 0xc90a, 0x21, 0 - .dw 0x3340, 0xc90a, 0x337f, 0xc90a, 0x21, 0 - .dw 0x33c0, 0xc90a, 0x33ff, 0xc90a, 0x21, 0 - .dw 0x3440, 0xc90a, 0x347f, 0xc90a, 0x21, 0 - .dw 0x34c0, 0xc90a, 0x34ff, 0xc90a, 0x21, 0 - .dw 0x3540, 0xc90a, 0x357f, 0xc90a, 0x21, 0 - .dw 0x35c0, 0xc90a, 0x35ff, 0xc90a, 0x21, 0 - .dw 0x3640, 0xc90a, 0x367f, 0xc90a, 0x21, 0 - .dw 0x36c0, 0xc90a, 0x36ff, 0xc90a, 0x21, 0 - .dw 0x3740, 0xc90a, 0x377f, 0xc90a, 0x21, 0 - .dw 0x37c0, 0xc90a, 0x37ff, 0xc90a, 0x21, 0 - .dw 0x3840, 0xc90a, 0x387f, 0xc90a, 0x21, 0 - .dw 0x38c0, 0xc90a, 0x38ff, 0xc90a, 0x21, 0 - .dw 0x3940, 0xc90a, 0x397f, 0xc90a, 0x21, 0 - .dw 0x39c0, 0xc90a, 0x5fff, 0xc90a, 0x21, 0 - .dw 0x6040, 0xc90a, 0x607f, 0xc90a, 0x21, 0 - .dw 0x60c0, 0xc90a, 0x60ff, 0xc90a, 0x21, 0 - .dw 0x6140, 0xc90a, 0x617f, 0xc90a, 0x21, 0 - .dw 0x61c0, 0xc90a, 0x61ff, 0xc90a, 0x21, 0 - .dw 0x6240, 0xc90a, 0x627f, 0xc90a, 0x21, 0 - .dw 0x62c0, 0xc90a, 0x62ff, 0xc90a, 0x21, 0 - .dw 0x6340, 0xc90a, 0x637f, 0xc90a, 0x21, 0 - .dw 0x63c0, 0xc90a, 0x63ff, 0xc90a, 0x21, 0 - .dw 0x6440, 0xc90a, 0x647f, 0xc90a, 0x21, 0 - .dw 0x64c0, 0xc90a, 0x64ff, 0xc90a, 0x21, 0 - .dw 0x6540, 0xc90a, 0x657f, 0xc90a, 0x21, 0 - .dw 0x65c0, 0xc90a, 0x65ff, 0xc90a, 0x21, 0 - .dw 0x6640, 0xc90a, 0x667f, 0xc90a, 0x21, 0 - .dw 0x66c0, 0xc90a, 0x66ff, 0xc90a, 0x21, 0 - .dw 0x6740, 0xc90a, 0x677f, 0xc90a, 0x21, 0 - .dw 0x67c0, 0xc90a, 0x67ff, 0xc90a, 0x21, 0 - .dw 0x6840, 0xc90a, 0x687f, 0xc90a, 0x21, 0 - .dw 0x68c0, 0xc90a, 0x68ff, 0xc90a, 0x21, 0 - .dw 0x6940, 0xc90a, 0x697f, 0xc90a, 0x21, 0 - .dw 0x69c0, 0xc90a, 0x69ff, 0xc90a, 0x21, 0 - .dw 0x6a40, 0xc90a, 0x6a7f, 0xc90a, 0x21, 0 - .dw 0x6ac0, 0xc90a, 0x6aff, 0xc90a, 0x21, 0 - .dw 0x6b40, 0xc90a, 0x6b7f, 0xc90a, 0x21, 0 - .dw 0x6bc0, 0xc90a, 0x6bff, 0xc90a, 0x21, 0 - .dw 0x6c40, 0xc90a, 0x6c7f, 0xc90a, 0x21, 0 - .dw 0x6cc0, 0xc90a, 0x6cff, 0xc90a, 0x21, 0 - .dw 0x6d40, 0xc90a, 0x6d7f, 0xc90a, 0x21, 0 - .dw 0x6dc0, 0xc90a, 0x6dff, 0xc90a, 0x21, 0 - .dw 0x6e40, 0xc90a, 0x6e7f, 0xc90a, 0x21, 0 - .dw 0x6ec0, 0xc90a, 0x6eff, 0xc90a, 0x21, 0 - .dw 0x6f40, 0xc90a, 0x6f7f, 0xc90a, 0x21, 0 - .dw 0x6fc0, 0xc90a, 0x6fff, 0xc90a, 0x21, 0 - .dw 0x7040, 0xc90a, 0x707f, 0xc90a, 0x21, 0 - .dw 0x70c0, 0xc90a, 0x70ff, 0xc90a, 0x21, 0 - .dw 0x7140, 0xc90a, 0x717f, 0xc90a, 0x21, 0 - .dw 0x71c0, 0xc90a, 0x71ff, 0xc90a, 0x21, 0 - .dw 0x7240, 0xc90a, 0x727f, 0xc90a, 0x21, 0 - .dw 0x72c0, 0xc90a, 0x72ff, 0xc90a, 0x21, 0 - .dw 0x7340, 0xc90a, 0x737f, 0xc90a, 0x21, 0 - .dw 0x73c0, 0xc90a, 0x73ff, 0xc90a, 0x21, 0 - .dw 0x7440, 0xc90a, 0x747f, 0xc90a, 0x21, 0 - .dw 0x74c0, 0xc90a, 0x74ff, 0xc90a, 0x21, 0 - .dw 0x7540, 0xc90a, 0x757f, 0xc90a, 0x21, 0 - .dw 0x75c0, 0xc90a, 0x75ff, 0xc90a, 0x21, 0 - .dw 0x7640, 0xc90a, 0x767f, 0xc90a, 0x21, 0 - .dw 0x76c0, 0xc90a, 0x76ff, 0xc90a, 0x21, 0 - .dw 0x7740, 0xc90a, 0x777f, 0xc90a, 0x21, 0 - .dw 0x77c0, 0xc90a, 0x77ff, 0xc90a, 0x21, 0 - .dw 0x7840, 0xc90a, 0x787f, 0xc90a, 0x21, 0 - .dw 0x78c0, 0xc90a, 0x78ff, 0xc90a, 0x21, 0 - .dw 0x7940, 0xc90a, 0x797f, 0xc90a, 0x21, 0 - .dw 0x79c0, 0xc90a, 0x9fff, 0xc90a, 0x21, 0 - .dw 0xa040, 0xc90a, 0xa07f, 0xc90a, 0x21, 0 - .dw 0xa0c0, 0xc90a, 0xa0ff, 0xc90a, 0x21, 0 - .dw 0xa140, 0xc90a, 0xa17f, 0xc90a, 0x21, 0 - .dw 0xa1c0, 0xc90a, 0xa1ff, 0xc90a, 0x21, 0 - .dw 0xa240, 0xc90a, 0xa27f, 0xc90a, 0x21, 0 - .dw 0xa2c0, 0xc90a, 0xa2ff, 0xc90a, 0x21, 0 - .dw 0xa340, 0xc90a, 0xa37f, 0xc90a, 0x21, 0 - .dw 0xa3c0, 0xc90a, 0xa3ff, 0xc90a, 0x21, 0 - .dw 0xa440, 0xc90a, 0xa47f, 0xc90a, 0x21, 0 - .dw 0xa4c0, 0xc90a, 0xa4ff, 0xc90a, 0x21, 0 - .dw 0xa540, 0xc90a, 0xa57f, 0xc90a, 0x21, 0 - .dw 0xa5c0, 0xc90a, 0xa5ff, 0xc90a, 0x21, 0 - .dw 0xa640, 0xc90a, 0xa67f, 0xc90a, 0x21, 0 - .dw 0xa6c0, 0xc90a, 0xa6ff, 0xc90a, 0x21, 0 - .dw 0xa740, 0xc90a, 0xa77f, 0xc90a, 0x21, 0 - .dw 0xa7c0, 0xc90a, 0xa7ff, 0xc90a, 0x21, 0 - .dw 0xa840, 0xc90a, 0xa87f, 0xc90a, 0x21, 0 - .dw 0xa8c0, 0xc90a, 0xa8ff, 0xc90a, 0x21, 0 - .dw 0xa940, 0xc90a, 0xa97f, 0xc90a, 0x21, 0 - .dw 0xa9c0, 0xc90a, 0xa9ff, 0xc90a, 0x21, 0 - .dw 0xaa40, 0xc90a, 0xaa7f, 0xc90a, 0x21, 0 - .dw 0xaac0, 0xc90a, 0xaaff, 0xc90a, 0x21, 0 - .dw 0xab40, 0xc90a, 0xab7f, 0xc90a, 0x21, 0 - .dw 0xabc0, 0xc90a, 0xabff, 0xc90a, 0x21, 0 - .dw 0xac40, 0xc90a, 0xac7f, 0xc90a, 0x21, 0 - .dw 0xacc0, 0xc90a, 0xacff, 0xc90a, 0x21, 0 - .dw 0xad40, 0xc90a, 0xad7f, 0xc90a, 0x21, 0 - .dw 0xadc0, 0xc90a, 0xadff, 0xc90a, 0x21, 0 - .dw 0xae40, 0xc90a, 0xae7f, 0xc90a, 0x21, 0 - .dw 0xaec0, 0xc90a, 0xaeff, 0xc90a, 0x21, 0 - .dw 0xaf40, 0xc90a, 0xaf7f, 0xc90a, 0x21, 0 - .dw 0xafc0, 0xc90a, 0xafff, 0xc90a, 0x21, 0 - .dw 0xb040, 0xc90a, 0xb07f, 0xc90a, 0x21, 0 - .dw 0xb0c0, 0xc90a, 0xb0ff, 0xc90a, 0x21, 0 - .dw 0xb140, 0xc90a, 0xb17f, 0xc90a, 0x21, 0 - .dw 0xb1c0, 0xc90a, 0xb1ff, 0xc90a, 0x21, 0 - .dw 0xb240, 0xc90a, 0xb27f, 0xc90a, 0x21, 0 - .dw 0xb2c0, 0xc90a, 0xb2ff, 0xc90a, 0x21, 0 - .dw 0xb340, 0xc90a, 0xb37f, 0xc90a, 0x21, 0 - .dw 0xb3c0, 0xc90a, 0xb3ff, 0xc90a, 0x21, 0 - .dw 0xb440, 0xc90a, 0xb47f, 0xc90a, 0x21, 0 - .dw 0xb4c0, 0xc90a, 0xb4ff, 0xc90a, 0x21, 0 - .dw 0xb540, 0xc90a, 0xb57f, 0xc90a, 0x21, 0 - .dw 0xb5c0, 0xc90a, 0xb5ff, 0xc90a, 0x21, 0 - .dw 0xb640, 0xc90a, 0xb67f, 0xc90a, 0x21, 0 - .dw 0xb6c0, 0xc90a, 0xb6ff, 0xc90a, 0x21, 0 - .dw 0xb740, 0xc90a, 0xb77f, 0xc90a, 0x21, 0 - .dw 0xb7c0, 0xc90a, 0xb7ff, 0xc90a, 0x21, 0 - .dw 0xb840, 0xc90a, 0xb87f, 0xc90a, 0x21, 0 - .dw 0xb8c0, 0xc90a, 0xb8ff, 0xc90a, 0x21, 0 - .dw 0xb940, 0xc90a, 0xb97f, 0xc90a, 0x21, 0 - .dw 0xb9c0, 0xc90a, 0xdfff, 0xc90a, 0x21, 0 - .dw 0xe040, 0xc90a, 0xe07f, 0xc90a, 0x21, 0 - .dw 0xe0c0, 0xc90a, 0xe0ff, 0xc90a, 0x21, 0 - .dw 0xe140, 0xc90a, 0xe17f, 0xc90a, 0x21, 0 - .dw 0xe1c0, 0xc90a, 0xe1ff, 0xc90a, 0x21, 0 - .dw 0xe240, 0xc90a, 0xe27f, 0xc90a, 0x21, 0 - .dw 0xe2c0, 0xc90a, 0xe2ff, 0xc90a, 0x21, 0 - .dw 0xe340, 0xc90a, 0xe37f, 0xc90a, 0x21, 0 - .dw 0xe3c0, 0xc90a, 0xe3ff, 0xc90a, 0x21, 0 - .dw 0xe440, 0xc90a, 0xe47f, 0xc90a, 0x21, 0 - .dw 0xe4c0, 0xc90a, 0xe4ff, 0xc90a, 0x21, 0 - .dw 0xe540, 0xc90a, 0xe57f, 0xc90a, 0x21, 0 - .dw 0xe5c0, 0xc90a, 0xe5ff, 0xc90a, 0x21, 0 - .dw 0xe640, 0xc90a, 0xe67f, 0xc90a, 0x21, 0 - .dw 0xe6c0, 0xc90a, 0xe6ff, 0xc90a, 0x21, 0 - .dw 0xe740, 0xc90a, 0xe77f, 0xc90a, 0x21, 0 - .dw 0xe7c0, 0xc90a, 0xe7ff, 0xc90a, 0x21, 0 - .dw 0xe840, 0xc90a, 0xe87f, 0xc90a, 0x21, 0 - .dw 0xe8c0, 0xc90a, 0xe8ff, 0xc90a, 0x21, 0 - .dw 0xe940, 0xc90a, 0xe97f, 0xc90a, 0x21, 0 - .dw 0xe9c0, 0xc90a, 0xe9ff, 0xc90a, 0x21, 0 - .dw 0xea40, 0xc90a, 0xea7f, 0xc90a, 0x21, 0 - .dw 0xeac0, 0xc90a, 0xeaff, 0xc90a, 0x21, 0 - .dw 0xeb40, 0xc90a, 0xeb7f, 0xc90a, 0x21, 0 - .dw 0xebc0, 0xc90a, 0xebff, 0xc90a, 0x21, 0 - .dw 0xec40, 0xc90a, 0xec7f, 0xc90a, 0x21, 0 - .dw 0xecc0, 0xc90a, 0xecff, 0xc90a, 0x21, 0 - .dw 0xed40, 0xc90a, 0xed7f, 0xc90a, 0x21, 0 - .dw 0xedc0, 0xc90a, 0xedff, 0xc90a, 0x21, 0 - .dw 0xee40, 0xc90a, 0xee7f, 0xc90a, 0x21, 0 - .dw 0xeec0, 0xc90a, 0xeeff, 0xc90a, 0x21, 0 - .dw 0xef40, 0xc90a, 0xef7f, 0xc90a, 0x21, 0 - .dw 0xefc0, 0xc90a, 0xefff, 0xc90a, 0x21, 0 - .dw 0xf040, 0xc90a, 0xf07f, 0xc90a, 0x21, 0 - .dw 0xf0c0, 0xc90a, 0xf0ff, 0xc90a, 0x21, 0 - .dw 0xf140, 0xc90a, 0xf17f, 0xc90a, 0x21, 0 - .dw 0xf1c0, 0xc90a, 0xf1ff, 0xc90a, 0x21, 0 - .dw 0xf240, 0xc90a, 0xf27f, 0xc90a, 0x21, 0 - .dw 0xf2c0, 0xc90a, 0xf2ff, 0xc90a, 0x21, 0 - .dw 0xf340, 0xc90a, 0xf37f, 0xc90a, 0x21, 0 - .dw 0xf3c0, 0xc90a, 0xf3ff, 0xc90a, 0x21, 0 - .dw 0xf440, 0xc90a, 0xf47f, 0xc90a, 0x21, 0 - .dw 0xf4c0, 0xc90a, 0xf4ff, 0xc90a, 0x21, 0 - .dw 0xf540, 0xc90a, 0xf57f, 0xc90a, 0x21, 0 - .dw 0xf5c0, 0xc90a, 0xf5ff, 0xc90a, 0x21, 0 - .dw 0xf640, 0xc90a, 0xf67f, 0xc90a, 0x21, 0 - .dw 0xf6c0, 0xc90a, 0xf6ff, 0xc90a, 0x21, 0 - .dw 0xf740, 0xc90a, 0xf77f, 0xc90a, 0x21, 0 - .dw 0xf7c0, 0xc90a, 0xf7ff, 0xc90a, 0x21, 0 - .dw 0xf840, 0xc90a, 0xf87f, 0xc90a, 0x21, 0 - .dw 0xf8c0, 0xc90a, 0xf8ff, 0xc90a, 0x21, 0 - .dw 0xf940, 0xc90a, 0xf97f, 0xc90a, 0x21, 0 - .dw 0xf9c0, 0xc90a, 0x1fff, 0xc90b, 0x21, 0 - .dw 0x2040, 0xc90b, 0x207f, 0xc90b, 0x21, 0 - .dw 0x20c0, 0xc90b, 0x20ff, 0xc90b, 0x21, 0 - .dw 0x2140, 0xc90b, 0x217f, 0xc90b, 0x21, 0 - .dw 0x21c0, 0xc90b, 0x21ff, 0xc90b, 0x21, 0 - .dw 0x2240, 0xc90b, 0x227f, 0xc90b, 0x21, 0 - .dw 0x22c0, 0xc90b, 0x22ff, 0xc90b, 0x21, 0 - .dw 0x2340, 0xc90b, 0x237f, 0xc90b, 0x21, 0 - .dw 0x23c0, 0xc90b, 0x23ff, 0xc90b, 0x21, 0 - .dw 0x2440, 0xc90b, 0x247f, 0xc90b, 0x21, 0 - .dw 0x24c0, 0xc90b, 0x24ff, 0xc90b, 0x21, 0 - .dw 0x2540, 0xc90b, 0x257f, 0xc90b, 0x21, 0 - .dw 0x25c0, 0xc90b, 0x25ff, 0xc90b, 0x21, 0 - .dw 0x2640, 0xc90b, 0x267f, 0xc90b, 0x21, 0 - .dw 0x26c0, 0xc90b, 0x26ff, 0xc90b, 0x21, 0 - .dw 0x2740, 0xc90b, 0x277f, 0xc90b, 0x21, 0 - .dw 0x27c0, 0xc90b, 0x27ff, 0xc90b, 0x21, 0 - .dw 0x2840, 0xc90b, 0x287f, 0xc90b, 0x21, 0 - .dw 0x28c0, 0xc90b, 0x28ff, 0xc90b, 0x21, 0 - .dw 0x2940, 0xc90b, 0x297f, 0xc90b, 0x21, 0 - .dw 0x29c0, 0xc90b, 0x29ff, 0xc90b, 0x21, 0 - .dw 0x2a40, 0xc90b, 0x2a7f, 0xc90b, 0x21, 0 - .dw 0x2ac0, 0xc90b, 0x2aff, 0xc90b, 0x21, 0 - .dw 0x2b40, 0xc90b, 0x2b7f, 0xc90b, 0x21, 0 - .dw 0x2bc0, 0xc90b, 0x2bff, 0xc90b, 0x21, 0 - .dw 0x2c40, 0xc90b, 0x2c7f, 0xc90b, 0x21, 0 - .dw 0x2cc0, 0xc90b, 0x2cff, 0xc90b, 0x21, 0 - .dw 0x2d40, 0xc90b, 0x2d7f, 0xc90b, 0x21, 0 - .dw 0x2dc0, 0xc90b, 0x2dff, 0xc90b, 0x21, 0 - .dw 0x2e40, 0xc90b, 0x2e7f, 0xc90b, 0x21, 0 - .dw 0x2ec0, 0xc90b, 0x2eff, 0xc90b, 0x21, 0 - .dw 0x2f40, 0xc90b, 0x2f7f, 0xc90b, 0x21, 0 - .dw 0x2fc0, 0xc90b, 0x2fff, 0xc90b, 0x21, 0 - .dw 0x3040, 0xc90b, 0x307f, 0xc90b, 0x21, 0 - .dw 0x30c0, 0xc90b, 0x30ff, 0xc90b, 0x21, 0 - .dw 0x3140, 0xc90b, 0x317f, 0xc90b, 0x21, 0 - .dw 0x31c0, 0xc90b, 0x31ff, 0xc90b, 0x21, 0 - .dw 0x3240, 0xc90b, 0x327f, 0xc90b, 0x21, 0 - .dw 0x32c0, 0xc90b, 0x32ff, 0xc90b, 0x21, 0 - .dw 0x3340, 0xc90b, 0x337f, 0xc90b, 0x21, 0 - .dw 0x33c0, 0xc90b, 0x33ff, 0xc90b, 0x21, 0 - .dw 0x3440, 0xc90b, 0x347f, 0xc90b, 0x21, 0 - .dw 0x34c0, 0xc90b, 0x34ff, 0xc90b, 0x21, 0 - .dw 0x3540, 0xc90b, 0x357f, 0xc90b, 0x21, 0 - .dw 0x35c0, 0xc90b, 0x35ff, 0xc90b, 0x21, 0 - .dw 0x3640, 0xc90b, 0x367f, 0xc90b, 0x21, 0 - .dw 0x36c0, 0xc90b, 0x36ff, 0xc90b, 0x21, 0 - .dw 0x3740, 0xc90b, 0x377f, 0xc90b, 0x21, 0 - .dw 0x37c0, 0xc90b, 0x37ff, 0xc90b, 0x21, 0 - .dw 0x3840, 0xc90b, 0x387f, 0xc90b, 0x21, 0 - .dw 0x38c0, 0xc90b, 0x38ff, 0xc90b, 0x21, 0 - .dw 0x3940, 0xc90b, 0x397f, 0xc90b, 0x21, 0 - .dw 0x39c0, 0xc90b, 0xffff, 0xc90b, 0x21, 0 - .dw 0x0040, 0xc90c, 0x007f, 0xc90c, 0x21, 0 - .dw 0x00c0, 0xc90c, 0x00ff, 0xc90c, 0x21, 0 - .dw 0x0140, 0xc90c, 0x017f, 0xc90c, 0x21, 0 - .dw 0x01c0, 0xc90c, 0x01ff, 0xc90c, 0x21, 0 - .dw 0x0240, 0xc90c, 0x027f, 0xc90c, 0x21, 0 - .dw 0x02c0, 0xc90c, 0x02ff, 0xc90c, 0x21, 0 - .dw 0x0340, 0xc90c, 0x037f, 0xc90c, 0x21, 0 - .dw 0x03c0, 0xc90c, 0x03ff, 0xc90c, 0x21, 0 - .dw 0x0440, 0xc90c, 0x047f, 0xc90c, 0x21, 0 - .dw 0x04c0, 0xc90c, 0x04ff, 0xc90c, 0x21, 0 - .dw 0x0540, 0xc90c, 0x057f, 0xc90c, 0x21, 0 - .dw 0x05c0, 0xc90c, 0x05ff, 0xc90c, 0x21, 0 - .dw 0x0640, 0xc90c, 0x067f, 0xc90c, 0x21, 0 - .dw 0x06c0, 0xc90c, 0x06ff, 0xc90c, 0x21, 0 - .dw 0x0740, 0xc90c, 0x077f, 0xc90c, 0x21, 0 - .dw 0x07c0, 0xc90c, 0x07ff, 0xc90c, 0x21, 0 - .dw 0x0840, 0xc90c, 0x087f, 0xc90c, 0x21, 0 - .dw 0x08c0, 0xc90c, 0x08ff, 0xc90c, 0x21, 0 - .dw 0x0940, 0xc90c, 0x097f, 0xc90c, 0x21, 0 - .dw 0x09c0, 0xc90c, 0x09ff, 0xc90c, 0x21, 0 - .dw 0x0a40, 0xc90c, 0x0a7f, 0xc90c, 0x21, 0 - .dw 0x0ac0, 0xc90c, 0x0aff, 0xc90c, 0x21, 0 - .dw 0x0b40, 0xc90c, 0x0b7f, 0xc90c, 0x21, 0 - .dw 0x0bc0, 0xc90c, 0x0bff, 0xc90c, 0x21, 0 - .dw 0x0c40, 0xc90c, 0x0c7f, 0xc90c, 0x21, 0 - .dw 0x0cc0, 0xc90c, 0x0cff, 0xc90c, 0x21, 0 - .dw 0x0d40, 0xc90c, 0x0d7f, 0xc90c, 0x21, 0 - .dw 0x0dc0, 0xc90c, 0x0dff, 0xc90c, 0x21, 0 - .dw 0x0e40, 0xc90c, 0x0e7f, 0xc90c, 0x21, 0 - .dw 0x0ec0, 0xc90c, 0x0eff, 0xc90c, 0x21, 0 - .dw 0x0f40, 0xc90c, 0x0f7f, 0xc90c, 0x21, 0 - .dw 0x0fc0, 0xc90c, 0x0fff, 0xc90c, 0x21, 0 - .dw 0x1040, 0xc90c, 0x107f, 0xc90c, 0x21, 0 - .dw 0x10c0, 0xc90c, 0x10ff, 0xc90c, 0x21, 0 - .dw 0x1140, 0xc90c, 0x117f, 0xc90c, 0x21, 0 - .dw 0x11c0, 0xc90c, 0x11ff, 0xc90c, 0x21, 0 - .dw 0x1240, 0xc90c, 0x127f, 0xc90c, 0x21, 0 - .dw 0x12c0, 0xc90c, 0x12ff, 0xc90c, 0x21, 0 - .dw 0x1340, 0xc90c, 0x137f, 0xc90c, 0x21, 0 - .dw 0x13c0, 0xc90c, 0x13ff, 0xc90c, 0x21, 0 - .dw 0x1440, 0xc90c, 0x147f, 0xc90c, 0x21, 0 - .dw 0x14c0, 0xc90c, 0x14ff, 0xc90c, 0x21, 0 - .dw 0x1540, 0xc90c, 0x157f, 0xc90c, 0x21, 0 - .dw 0x15c0, 0xc90c, 0x15ff, 0xc90c, 0x21, 0 - .dw 0x1640, 0xc90c, 0x167f, 0xc90c, 0x21, 0 - .dw 0x16c0, 0xc90c, 0x16ff, 0xc90c, 0x21, 0 - .dw 0x1740, 0xc90c, 0x177f, 0xc90c, 0x21, 0 - .dw 0x17c0, 0xc90c, 0x17ff, 0xc90c, 0x21, 0 - .dw 0x1840, 0xc90c, 0x187f, 0xc90c, 0x21, 0 - .dw 0x18c0, 0xc90c, 0x18ff, 0xc90c, 0x21, 0 - .dw 0x1940, 0xc90c, 0x197f, 0xc90c, 0x21, 0 - .dw 0x19c0, 0xc90c, 0x1fff, 0xc90c, 0x21, 0 - .dw 0x2040, 0xc90c, 0x207f, 0xc90c, 0x21, 0 - .dw 0x20c0, 0xc90c, 0x20ff, 0xc90c, 0x21, 0 - .dw 0x2140, 0xc90c, 0x217f, 0xc90c, 0x21, 0 - .dw 0x21c0, 0xc90c, 0x21ff, 0xc90c, 0x21, 0 - .dw 0x2240, 0xc90c, 0x227f, 0xc90c, 0x21, 0 - .dw 0x22c0, 0xc90c, 0x22ff, 0xc90c, 0x21, 0 - .dw 0x2340, 0xc90c, 0x237f, 0xc90c, 0x21, 0 - .dw 0x23c0, 0xc90c, 0x23ff, 0xc90c, 0x21, 0 - .dw 0x2440, 0xc90c, 0x247f, 0xc90c, 0x21, 0 - .dw 0x24c0, 0xc90c, 0x24ff, 0xc90c, 0x21, 0 - .dw 0x2540, 0xc90c, 0x257f, 0xc90c, 0x21, 0 - .dw 0x25c0, 0xc90c, 0x25ff, 0xc90c, 0x21, 0 - .dw 0x2640, 0xc90c, 0x267f, 0xc90c, 0x21, 0 - .dw 0x26c0, 0xc90c, 0x26ff, 0xc90c, 0x21, 0 - .dw 0x2740, 0xc90c, 0x277f, 0xc90c, 0x21, 0 - .dw 0x27c0, 0xc90c, 0x27ff, 0xc90c, 0x21, 0 - .dw 0x2840, 0xc90c, 0x287f, 0xc90c, 0x21, 0 - .dw 0x28c0, 0xc90c, 0x28ff, 0xc90c, 0x21, 0 - .dw 0x2940, 0xc90c, 0x297f, 0xc90c, 0x21, 0 - .dw 0x29c0, 0xc90c, 0x29ff, 0xc90c, 0x21, 0 - .dw 0x2a40, 0xc90c, 0x2a7f, 0xc90c, 0x21, 0 - .dw 0x2ac0, 0xc90c, 0x2aff, 0xc90c, 0x21, 0 - .dw 0x2b40, 0xc90c, 0x2b7f, 0xc90c, 0x21, 0 - .dw 0x2bc0, 0xc90c, 0x2bff, 0xc90c, 0x21, 0 - .dw 0x2c40, 0xc90c, 0x2c7f, 0xc90c, 0x21, 0 - .dw 0x2cc0, 0xc90c, 0x2cff, 0xc90c, 0x21, 0 - .dw 0x2d40, 0xc90c, 0x2d7f, 0xc90c, 0x21, 0 - .dw 0x2dc0, 0xc90c, 0x2dff, 0xc90c, 0x21, 0 - .dw 0x2e40, 0xc90c, 0x2e7f, 0xc90c, 0x21, 0 - .dw 0x2ec0, 0xc90c, 0x2eff, 0xc90c, 0x21, 0 - .dw 0x2f40, 0xc90c, 0x2f7f, 0xc90c, 0x21, 0 - .dw 0x2fc0, 0xc90c, 0x2fff, 0xc90c, 0x21, 0 - .dw 0x3040, 0xc90c, 0x307f, 0xc90c, 0x21, 0 - .dw 0x30c0, 0xc90c, 0x30ff, 0xc90c, 0x21, 0 - .dw 0x3140, 0xc90c, 0x317f, 0xc90c, 0x21, 0 - .dw 0x31c0, 0xc90c, 0x31ff, 0xc90c, 0x21, 0 - .dw 0x3240, 0xc90c, 0x327f, 0xc90c, 0x21, 0 - .dw 0x32c0, 0xc90c, 0x32ff, 0xc90c, 0x21, 0 - .dw 0x3340, 0xc90c, 0x337f, 0xc90c, 0x21, 0 - .dw 0x33c0, 0xc90c, 0x33ff, 0xc90c, 0x21, 0 - .dw 0x3440, 0xc90c, 0x347f, 0xc90c, 0x21, 0 - .dw 0x34c0, 0xc90c, 0x34ff, 0xc90c, 0x21, 0 - .dw 0x3540, 0xc90c, 0x357f, 0xc90c, 0x21, 0 - .dw 0x35c0, 0xc90c, 0x35ff, 0xc90c, 0x21, 0 - .dw 0x3640, 0xc90c, 0x367f, 0xc90c, 0x21, 0 - .dw 0x36c0, 0xc90c, 0x36ff, 0xc90c, 0x21, 0 - .dw 0x3740, 0xc90c, 0x377f, 0xc90c, 0x21, 0 - .dw 0x37c0, 0xc90c, 0x37ff, 0xc90c, 0x21, 0 - .dw 0x3840, 0xc90c, 0x387f, 0xc90c, 0x21, 0 - .dw 0x38c0, 0xc90c, 0x38ff, 0xc90c, 0x21, 0 - .dw 0x3940, 0xc90c, 0x397f, 0xc90c, 0x21, 0 - .dw 0x39c0, 0xc90c, 0x3fff, 0xc90c, 0x21, 0 - .dw 0x4040, 0xc90c, 0x407f, 0xc90c, 0x21, 0 - .dw 0x40c0, 0xc90c, 0x40ff, 0xc90c, 0x21, 0 - .dw 0x4140, 0xc90c, 0x417f, 0xc90c, 0x21, 0 - .dw 0x41c0, 0xc90c, 0x41ff, 0xc90c, 0x21, 0 - .dw 0x4240, 0xc90c, 0x427f, 0xc90c, 0x21, 0 - .dw 0x42c0, 0xc90c, 0x42ff, 0xc90c, 0x21, 0 - .dw 0x4340, 0xc90c, 0x437f, 0xc90c, 0x21, 0 - .dw 0x43c0, 0xc90c, 0x43ff, 0xc90c, 0x21, 0 - .dw 0x4440, 0xc90c, 0x447f, 0xc90c, 0x21, 0 - .dw 0x44c0, 0xc90c, 0x44ff, 0xc90c, 0x21, 0 - .dw 0x4540, 0xc90c, 0x457f, 0xc90c, 0x21, 0 - .dw 0x45c0, 0xc90c, 0x45ff, 0xc90c, 0x21, 0 - .dw 0x4640, 0xc90c, 0x467f, 0xc90c, 0x21, 0 - .dw 0x46c0, 0xc90c, 0x46ff, 0xc90c, 0x21, 0 - .dw 0x4740, 0xc90c, 0x477f, 0xc90c, 0x21, 0 - .dw 0x47c0, 0xc90c, 0x47ff, 0xc90c, 0x21, 0 - .dw 0x4840, 0xc90c, 0x487f, 0xc90c, 0x21, 0 - .dw 0x48c0, 0xc90c, 0x48ff, 0xc90c, 0x21, 0 - .dw 0x4940, 0xc90c, 0x497f, 0xc90c, 0x21, 0 - .dw 0x49c0, 0xc90c, 0x49ff, 0xc90c, 0x21, 0 - .dw 0x4a40, 0xc90c, 0x4a7f, 0xc90c, 0x21, 0 - .dw 0x4ac0, 0xc90c, 0x4aff, 0xc90c, 0x21, 0 - .dw 0x4b40, 0xc90c, 0x4b7f, 0xc90c, 0x21, 0 - .dw 0x4bc0, 0xc90c, 0x4bff, 0xc90c, 0x21, 0 - .dw 0x4c40, 0xc90c, 0x4c7f, 0xc90c, 0x21, 0 - .dw 0x4cc0, 0xc90c, 0x4cff, 0xc90c, 0x21, 0 - .dw 0x4d40, 0xc90c, 0x4d7f, 0xc90c, 0x21, 0 - .dw 0x4dc0, 0xc90c, 0x4dff, 0xc90c, 0x21, 0 - .dw 0x4e40, 0xc90c, 0x4e7f, 0xc90c, 0x21, 0 - .dw 0x4ec0, 0xc90c, 0x4eff, 0xc90c, 0x21, 0 - .dw 0x4f40, 0xc90c, 0x4f7f, 0xc90c, 0x21, 0 - .dw 0x4fc0, 0xc90c, 0x4fff, 0xc90c, 0x21, 0 - .dw 0x5040, 0xc90c, 0x507f, 0xc90c, 0x21, 0 - .dw 0x50c0, 0xc90c, 0x50ff, 0xc90c, 0x21, 0 - .dw 0x5140, 0xc90c, 0x517f, 0xc90c, 0x21, 0 - .dw 0x51c0, 0xc90c, 0x51ff, 0xc90c, 0x21, 0 - .dw 0x5240, 0xc90c, 0x527f, 0xc90c, 0x21, 0 - .dw 0x52c0, 0xc90c, 0x52ff, 0xc90c, 0x21, 0 - .dw 0x5340, 0xc90c, 0x537f, 0xc90c, 0x21, 0 - .dw 0x53c0, 0xc90c, 0x53ff, 0xc90c, 0x21, 0 - .dw 0x5440, 0xc90c, 0x547f, 0xc90c, 0x21, 0 - .dw 0x54c0, 0xc90c, 0x54ff, 0xc90c, 0x21, 0 - .dw 0x5540, 0xc90c, 0x557f, 0xc90c, 0x21, 0 - .dw 0x55c0, 0xc90c, 0x55ff, 0xc90c, 0x21, 0 - .dw 0x5640, 0xc90c, 0x567f, 0xc90c, 0x21, 0 - .dw 0x56c0, 0xc90c, 0x56ff, 0xc90c, 0x21, 0 - .dw 0x5740, 0xc90c, 0x577f, 0xc90c, 0x21, 0 - .dw 0x57c0, 0xc90c, 0x57ff, 0xc90c, 0x21, 0 - .dw 0x5840, 0xc90c, 0x587f, 0xc90c, 0x21, 0 - .dw 0x58c0, 0xc90c, 0x58ff, 0xc90c, 0x21, 0 - .dw 0x5940, 0xc90c, 0x597f, 0xc90c, 0x21, 0 - .dw 0x59c0, 0xc90c, 0x5fff, 0xc90c, 0x21, 0 - .dw 0x6040, 0xc90c, 0x607f, 0xc90c, 0x21, 0 - .dw 0x60c0, 0xc90c, 0x60ff, 0xc90c, 0x21, 0 - .dw 0x6140, 0xc90c, 0x617f, 0xc90c, 0x21, 0 - .dw 0x61c0, 0xc90c, 0x61ff, 0xc90c, 0x21, 0 - .dw 0x6240, 0xc90c, 0x627f, 0xc90c, 0x21, 0 - .dw 0x62c0, 0xc90c, 0x62ff, 0xc90c, 0x21, 0 - .dw 0x6340, 0xc90c, 0x637f, 0xc90c, 0x21, 0 - .dw 0x63c0, 0xc90c, 0x63ff, 0xc90c, 0x21, 0 - .dw 0x6440, 0xc90c, 0x647f, 0xc90c, 0x21, 0 - .dw 0x64c0, 0xc90c, 0x64ff, 0xc90c, 0x21, 0 - .dw 0x6540, 0xc90c, 0x657f, 0xc90c, 0x21, 0 - .dw 0x65c0, 0xc90c, 0x65ff, 0xc90c, 0x21, 0 - .dw 0x6640, 0xc90c, 0x667f, 0xc90c, 0x21, 0 - .dw 0x66c0, 0xc90c, 0x66ff, 0xc90c, 0x21, 0 - .dw 0x6740, 0xc90c, 0x677f, 0xc90c, 0x21, 0 - .dw 0x67c0, 0xc90c, 0x67ff, 0xc90c, 0x21, 0 - .dw 0x6840, 0xc90c, 0x687f, 0xc90c, 0x21, 0 - .dw 0x68c0, 0xc90c, 0x68ff, 0xc90c, 0x21, 0 - .dw 0x6940, 0xc90c, 0x697f, 0xc90c, 0x21, 0 - .dw 0x69c0, 0xc90c, 0x69ff, 0xc90c, 0x21, 0 - .dw 0x6a40, 0xc90c, 0x6a7f, 0xc90c, 0x21, 0 - .dw 0x6ac0, 0xc90c, 0x6aff, 0xc90c, 0x21, 0 - .dw 0x6b40, 0xc90c, 0x6b7f, 0xc90c, 0x21, 0 - .dw 0x6bc0, 0xc90c, 0x6bff, 0xc90c, 0x21, 0 - .dw 0x6c40, 0xc90c, 0x6c7f, 0xc90c, 0x21, 0 - .dw 0x6cc0, 0xc90c, 0x6cff, 0xc90c, 0x21, 0 - .dw 0x6d40, 0xc90c, 0x6d7f, 0xc90c, 0x21, 0 - .dw 0x6dc0, 0xc90c, 0x6dff, 0xc90c, 0x21, 0 - .dw 0x6e40, 0xc90c, 0x6e7f, 0xc90c, 0x21, 0 - .dw 0x6ec0, 0xc90c, 0x6eff, 0xc90c, 0x21, 0 - .dw 0x6f40, 0xc90c, 0x6f7f, 0xc90c, 0x21, 0 - .dw 0x6fc0, 0xc90c, 0x6fff, 0xc90c, 0x21, 0 - .dw 0x7040, 0xc90c, 0x707f, 0xc90c, 0x21, 0 - .dw 0x70c0, 0xc90c, 0x70ff, 0xc90c, 0x21, 0 - .dw 0x7140, 0xc90c, 0x717f, 0xc90c, 0x21, 0 - .dw 0x71c0, 0xc90c, 0x71ff, 0xc90c, 0x21, 0 - .dw 0x7240, 0xc90c, 0x727f, 0xc90c, 0x21, 0 - .dw 0x72c0, 0xc90c, 0x72ff, 0xc90c, 0x21, 0 - .dw 0x7340, 0xc90c, 0x737f, 0xc90c, 0x21, 0 - .dw 0x73c0, 0xc90c, 0x73ff, 0xc90c, 0x21, 0 - .dw 0x7440, 0xc90c, 0x747f, 0xc90c, 0x21, 0 - .dw 0x74c0, 0xc90c, 0x74ff, 0xc90c, 0x21, 0 - .dw 0x7540, 0xc90c, 0x757f, 0xc90c, 0x21, 0 - .dw 0x75c0, 0xc90c, 0x75ff, 0xc90c, 0x21, 0 - .dw 0x7640, 0xc90c, 0x767f, 0xc90c, 0x21, 0 - .dw 0x76c0, 0xc90c, 0x76ff, 0xc90c, 0x21, 0 - .dw 0x7740, 0xc90c, 0x777f, 0xc90c, 0x21, 0 - .dw 0x77c0, 0xc90c, 0x77ff, 0xc90c, 0x21, 0 - .dw 0x7840, 0xc90c, 0x787f, 0xc90c, 0x21, 0 - .dw 0x78c0, 0xc90c, 0x78ff, 0xc90c, 0x21, 0 - .dw 0x7940, 0xc90c, 0x797f, 0xc90c, 0x21, 0 - .dw 0x79c0, 0xc90c, 0x7fff, 0xc90c, 0x21, 0 - .dw 0x8040, 0xc90c, 0x807f, 0xc90c, 0x21, 0 - .dw 0x80c0, 0xc90c, 0x80ff, 0xc90c, 0x21, 0 - .dw 0x8140, 0xc90c, 0x817f, 0xc90c, 0x21, 0 - .dw 0x81c0, 0xc90c, 0x81ff, 0xc90c, 0x21, 0 - .dw 0x8240, 0xc90c, 0x827f, 0xc90c, 0x21, 0 - .dw 0x82c0, 0xc90c, 0x82ff, 0xc90c, 0x21, 0 - .dw 0x8340, 0xc90c, 0x837f, 0xc90c, 0x21, 0 - .dw 0x83c0, 0xc90c, 0x83ff, 0xc90c, 0x21, 0 - .dw 0x8440, 0xc90c, 0x847f, 0xc90c, 0x21, 0 - .dw 0x84c0, 0xc90c, 0x84ff, 0xc90c, 0x21, 0 - .dw 0x8540, 0xc90c, 0x857f, 0xc90c, 0x21, 0 - .dw 0x85c0, 0xc90c, 0x85ff, 0xc90c, 0x21, 0 - .dw 0x8640, 0xc90c, 0x867f, 0xc90c, 0x21, 0 - .dw 0x86c0, 0xc90c, 0x86ff, 0xc90c, 0x21, 0 - .dw 0x8740, 0xc90c, 0x877f, 0xc90c, 0x21, 0 - .dw 0x87c0, 0xc90c, 0x87ff, 0xc90c, 0x21, 0 - .dw 0x8840, 0xc90c, 0x887f, 0xc90c, 0x21, 0 - .dw 0x88c0, 0xc90c, 0x88ff, 0xc90c, 0x21, 0 - .dw 0x8940, 0xc90c, 0x897f, 0xc90c, 0x21, 0 - .dw 0x89c0, 0xc90c, 0x89ff, 0xc90c, 0x21, 0 - .dw 0x8a40, 0xc90c, 0x8a7f, 0xc90c, 0x21, 0 - .dw 0x8ac0, 0xc90c, 0x8aff, 0xc90c, 0x21, 0 - .dw 0x8b40, 0xc90c, 0x8b7f, 0xc90c, 0x21, 0 - .dw 0x8bc0, 0xc90c, 0x8bff, 0xc90c, 0x21, 0 - .dw 0x8c40, 0xc90c, 0x8c7f, 0xc90c, 0x21, 0 - .dw 0x8cc0, 0xc90c, 0x8cff, 0xc90c, 0x21, 0 - .dw 0x8d40, 0xc90c, 0x8d7f, 0xc90c, 0x21, 0 - .dw 0x8dc0, 0xc90c, 0x8dff, 0xc90c, 0x21, 0 - .dw 0x8e40, 0xc90c, 0x8e7f, 0xc90c, 0x21, 0 - .dw 0x8ec0, 0xc90c, 0x8eff, 0xc90c, 0x21, 0 - .dw 0x8f40, 0xc90c, 0x8f7f, 0xc90c, 0x21, 0 - .dw 0x8fc0, 0xc90c, 0x8fff, 0xc90c, 0x21, 0 - .dw 0x9040, 0xc90c, 0x907f, 0xc90c, 0x21, 0 - .dw 0x90c0, 0xc90c, 0x90ff, 0xc90c, 0x21, 0 - .dw 0x9140, 0xc90c, 0x917f, 0xc90c, 0x21, 0 - .dw 0x91c0, 0xc90c, 0x91ff, 0xc90c, 0x21, 0 - .dw 0x9240, 0xc90c, 0x927f, 0xc90c, 0x21, 0 - .dw 0x92c0, 0xc90c, 0x92ff, 0xc90c, 0x21, 0 - .dw 0x9340, 0xc90c, 0x937f, 0xc90c, 0x21, 0 - .dw 0x93c0, 0xc90c, 0x93ff, 0xc90c, 0x21, 0 - .dw 0x9440, 0xc90c, 0x947f, 0xc90c, 0x21, 0 - .dw 0x94c0, 0xc90c, 0x94ff, 0xc90c, 0x21, 0 - .dw 0x9540, 0xc90c, 0x957f, 0xc90c, 0x21, 0 - .dw 0x95c0, 0xc90c, 0x95ff, 0xc90c, 0x21, 0 - .dw 0x9640, 0xc90c, 0x967f, 0xc90c, 0x21, 0 - .dw 0x96c0, 0xc90c, 0x96ff, 0xc90c, 0x21, 0 - .dw 0x9740, 0xc90c, 0x977f, 0xc90c, 0x21, 0 - .dw 0x97c0, 0xc90c, 0x97ff, 0xc90c, 0x21, 0 - .dw 0x9840, 0xc90c, 0x987f, 0xc90c, 0x21, 0 - .dw 0x98c0, 0xc90c, 0x98ff, 0xc90c, 0x21, 0 - .dw 0x9940, 0xc90c, 0x997f, 0xc90c, 0x21, 0 - .dw 0x99c0, 0xc90c, 0x9fff, 0xc90c, 0x21, 0 - .dw 0xa040, 0xc90c, 0xa07f, 0xc90c, 0x21, 0 - .dw 0xa0c0, 0xc90c, 0xa0ff, 0xc90c, 0x21, 0 - .dw 0xa140, 0xc90c, 0xa17f, 0xc90c, 0x21, 0 - .dw 0xa1c0, 0xc90c, 0xa1ff, 0xc90c, 0x21, 0 - .dw 0xa240, 0xc90c, 0xa27f, 0xc90c, 0x21, 0 - .dw 0xa2c0, 0xc90c, 0xa2ff, 0xc90c, 0x21, 0 - .dw 0xa340, 0xc90c, 0xa37f, 0xc90c, 0x21, 0 - .dw 0xa3c0, 0xc90c, 0xa3ff, 0xc90c, 0x21, 0 - .dw 0xa440, 0xc90c, 0xa47f, 0xc90c, 0x21, 0 - .dw 0xa4c0, 0xc90c, 0xa4ff, 0xc90c, 0x21, 0 - .dw 0xa540, 0xc90c, 0xa57f, 0xc90c, 0x21, 0 - .dw 0xa5c0, 0xc90c, 0xa5ff, 0xc90c, 0x21, 0 - .dw 0xa640, 0xc90c, 0xa67f, 0xc90c, 0x21, 0 - .dw 0xa6c0, 0xc90c, 0xa6ff, 0xc90c, 0x21, 0 - .dw 0xa740, 0xc90c, 0xa77f, 0xc90c, 0x21, 0 - .dw 0xa7c0, 0xc90c, 0xa7ff, 0xc90c, 0x21, 0 - .dw 0xa840, 0xc90c, 0xa87f, 0xc90c, 0x21, 0 - .dw 0xa8c0, 0xc90c, 0xa8ff, 0xc90c, 0x21, 0 - .dw 0xa940, 0xc90c, 0xa97f, 0xc90c, 0x21, 0 - .dw 0xa9c0, 0xc90c, 0xa9ff, 0xc90c, 0x21, 0 - .dw 0xaa40, 0xc90c, 0xaa7f, 0xc90c, 0x21, 0 - .dw 0xaac0, 0xc90c, 0xaaff, 0xc90c, 0x21, 0 - .dw 0xab40, 0xc90c, 0xab7f, 0xc90c, 0x21, 0 - .dw 0xabc0, 0xc90c, 0xabff, 0xc90c, 0x21, 0 - .dw 0xac40, 0xc90c, 0xac7f, 0xc90c, 0x21, 0 - .dw 0xacc0, 0xc90c, 0xacff, 0xc90c, 0x21, 0 - .dw 0xad40, 0xc90c, 0xad7f, 0xc90c, 0x21, 0 - .dw 0xadc0, 0xc90c, 0xadff, 0xc90c, 0x21, 0 - .dw 0xae40, 0xc90c, 0xae7f, 0xc90c, 0x21, 0 - .dw 0xaec0, 0xc90c, 0xaeff, 0xc90c, 0x21, 0 - .dw 0xaf40, 0xc90c, 0xaf7f, 0xc90c, 0x21, 0 - .dw 0xafc0, 0xc90c, 0xafff, 0xc90c, 0x21, 0 - .dw 0xb040, 0xc90c, 0xb07f, 0xc90c, 0x21, 0 - .dw 0xb0c0, 0xc90c, 0xb0ff, 0xc90c, 0x21, 0 - .dw 0xb140, 0xc90c, 0xb17f, 0xc90c, 0x21, 0 - .dw 0xb1c0, 0xc90c, 0xb1ff, 0xc90c, 0x21, 0 - .dw 0xb240, 0xc90c, 0xb27f, 0xc90c, 0x21, 0 - .dw 0xb2c0, 0xc90c, 0xb2ff, 0xc90c, 0x21, 0 - .dw 0xb340, 0xc90c, 0xb37f, 0xc90c, 0x21, 0 - .dw 0xb3c0, 0xc90c, 0xb3ff, 0xc90c, 0x21, 0 - .dw 0xb440, 0xc90c, 0xb47f, 0xc90c, 0x21, 0 - .dw 0xb4c0, 0xc90c, 0xb4ff, 0xc90c, 0x21, 0 - .dw 0xb540, 0xc90c, 0xb57f, 0xc90c, 0x21, 0 - .dw 0xb5c0, 0xc90c, 0xb5ff, 0xc90c, 0x21, 0 - .dw 0xb640, 0xc90c, 0xb67f, 0xc90c, 0x21, 0 - .dw 0xb6c0, 0xc90c, 0xb6ff, 0xc90c, 0x21, 0 - .dw 0xb740, 0xc90c, 0xb77f, 0xc90c, 0x21, 0 - .dw 0xb7c0, 0xc90c, 0xb7ff, 0xc90c, 0x21, 0 - .dw 0xb840, 0xc90c, 0xb87f, 0xc90c, 0x21, 0 - .dw 0xb8c0, 0xc90c, 0xb8ff, 0xc90c, 0x21, 0 - .dw 0xb940, 0xc90c, 0xb97f, 0xc90c, 0x21, 0 - .dw 0xb9c0, 0xc90c, 0xbfff, 0xc90c, 0x21, 0 - .dw 0xc040, 0xc90c, 0xc07f, 0xc90c, 0x21, 0 - .dw 0xc0c0, 0xc90c, 0xc0ff, 0xc90c, 0x21, 0 - .dw 0xc140, 0xc90c, 0xc17f, 0xc90c, 0x21, 0 - .dw 0xc1c0, 0xc90c, 0xc1ff, 0xc90c, 0x21, 0 - .dw 0xc240, 0xc90c, 0xc27f, 0xc90c, 0x21, 0 - .dw 0xc2c0, 0xc90c, 0xc2ff, 0xc90c, 0x21, 0 - .dw 0xc340, 0xc90c, 0xc37f, 0xc90c, 0x21, 0 - .dw 0xc3c0, 0xc90c, 0xc3ff, 0xc90c, 0x21, 0 - .dw 0xc440, 0xc90c, 0xc47f, 0xc90c, 0x21, 0 - .dw 0xc4c0, 0xc90c, 0xc4ff, 0xc90c, 0x21, 0 - .dw 0xc540, 0xc90c, 0xc57f, 0xc90c, 0x21, 0 - .dw 0xc5c0, 0xc90c, 0xc5ff, 0xc90c, 0x21, 0 - .dw 0xc640, 0xc90c, 0xc67f, 0xc90c, 0x21, 0 - .dw 0xc6c0, 0xc90c, 0xc6ff, 0xc90c, 0x21, 0 - .dw 0xc740, 0xc90c, 0xc77f, 0xc90c, 0x21, 0 - .dw 0xc7c0, 0xc90c, 0xc7ff, 0xc90c, 0x21, 0 - .dw 0xc840, 0xc90c, 0xc87f, 0xc90c, 0x21, 0 - .dw 0xc8c0, 0xc90c, 0xc8ff, 0xc90c, 0x21, 0 - .dw 0xc940, 0xc90c, 0xc97f, 0xc90c, 0x21, 0 - .dw 0xc9c0, 0xc90c, 0xc9ff, 0xc90c, 0x21, 0 - .dw 0xca40, 0xc90c, 0xca7f, 0xc90c, 0x21, 0 - .dw 0xcac0, 0xc90c, 0xcaff, 0xc90c, 0x21, 0 - .dw 0xcb40, 0xc90c, 0xcb7f, 0xc90c, 0x21, 0 - .dw 0xcbc0, 0xc90c, 0xcbff, 0xc90c, 0x21, 0 - .dw 0xcc40, 0xc90c, 0xcc7f, 0xc90c, 0x21, 0 - .dw 0xccc0, 0xc90c, 0xccff, 0xc90c, 0x21, 0 - .dw 0xcd40, 0xc90c, 0xcd7f, 0xc90c, 0x21, 0 - .dw 0xcdc0, 0xc90c, 0xcdff, 0xc90c, 0x21, 0 - .dw 0xce40, 0xc90c, 0xce7f, 0xc90c, 0x21, 0 - .dw 0xcec0, 0xc90c, 0xceff, 0xc90c, 0x21, 0 - .dw 0xcf40, 0xc90c, 0xcf7f, 0xc90c, 0x21, 0 - .dw 0xcfc0, 0xc90c, 0xcfff, 0xc90c, 0x21, 0 - .dw 0xd040, 0xc90c, 0xd07f, 0xc90c, 0x21, 0 - .dw 0xd0c0, 0xc90c, 0xd0ff, 0xc90c, 0x21, 0 - .dw 0xd140, 0xc90c, 0xd17f, 0xc90c, 0x21, 0 - .dw 0xd1c0, 0xc90c, 0xd1ff, 0xc90c, 0x21, 0 - .dw 0xd240, 0xc90c, 0xd27f, 0xc90c, 0x21, 0 - .dw 0xd2c0, 0xc90c, 0xd2ff, 0xc90c, 0x21, 0 - .dw 0xd340, 0xc90c, 0xd37f, 0xc90c, 0x21, 0 - .dw 0xd3c0, 0xc90c, 0xd3ff, 0xc90c, 0x21, 0 - .dw 0xd440, 0xc90c, 0xd47f, 0xc90c, 0x21, 0 - .dw 0xd4c0, 0xc90c, 0xd4ff, 0xc90c, 0x21, 0 - .dw 0xd540, 0xc90c, 0xd57f, 0xc90c, 0x21, 0 - .dw 0xd5c0, 0xc90c, 0xd5ff, 0xc90c, 0x21, 0 - .dw 0xd640, 0xc90c, 0xd67f, 0xc90c, 0x21, 0 - .dw 0xd6c0, 0xc90c, 0xd6ff, 0xc90c, 0x21, 0 - .dw 0xd740, 0xc90c, 0xd77f, 0xc90c, 0x21, 0 - .dw 0xd7c0, 0xc90c, 0xd7ff, 0xc90c, 0x21, 0 - .dw 0xd840, 0xc90c, 0xd87f, 0xc90c, 0x21, 0 - .dw 0xd8c0, 0xc90c, 0xd8ff, 0xc90c, 0x21, 0 - .dw 0xd940, 0xc90c, 0xd97f, 0xc90c, 0x21, 0 - .dw 0xd9c0, 0xc90c, 0xdfff, 0xc90c, 0x21, 0 - .dw 0xe040, 0xc90c, 0xe07f, 0xc90c, 0x21, 0 - .dw 0xe0c0, 0xc90c, 0xe0ff, 0xc90c, 0x21, 0 - .dw 0xe140, 0xc90c, 0xe17f, 0xc90c, 0x21, 0 - .dw 0xe1c0, 0xc90c, 0xe1ff, 0xc90c, 0x21, 0 - .dw 0xe240, 0xc90c, 0xe27f, 0xc90c, 0x21, 0 - .dw 0xe2c0, 0xc90c, 0xe2ff, 0xc90c, 0x21, 0 - .dw 0xe340, 0xc90c, 0xe37f, 0xc90c, 0x21, 0 - .dw 0xe3c0, 0xc90c, 0xe3ff, 0xc90c, 0x21, 0 - .dw 0xe440, 0xc90c, 0xe47f, 0xc90c, 0x21, 0 - .dw 0xe4c0, 0xc90c, 0xe4ff, 0xc90c, 0x21, 0 - .dw 0xe540, 0xc90c, 0xe57f, 0xc90c, 0x21, 0 - .dw 0xe5c0, 0xc90c, 0xe5ff, 0xc90c, 0x21, 0 - .dw 0xe640, 0xc90c, 0xe67f, 0xc90c, 0x21, 0 - .dw 0xe6c0, 0xc90c, 0xe6ff, 0xc90c, 0x21, 0 - .dw 0xe740, 0xc90c, 0xe77f, 0xc90c, 0x21, 0 - .dw 0xe7c0, 0xc90c, 0xe7ff, 0xc90c, 0x21, 0 - .dw 0xe840, 0xc90c, 0xe87f, 0xc90c, 0x21, 0 - .dw 0xe8c0, 0xc90c, 0xe8ff, 0xc90c, 0x21, 0 - .dw 0xe940, 0xc90c, 0xe97f, 0xc90c, 0x21, 0 - .dw 0xe9c0, 0xc90c, 0xe9ff, 0xc90c, 0x21, 0 - .dw 0xea40, 0xc90c, 0xea7f, 0xc90c, 0x21, 0 - .dw 0xeac0, 0xc90c, 0xeaff, 0xc90c, 0x21, 0 - .dw 0xeb40, 0xc90c, 0xeb7f, 0xc90c, 0x21, 0 - .dw 0xebc0, 0xc90c, 0xebff, 0xc90c, 0x21, 0 - .dw 0xec40, 0xc90c, 0xec7f, 0xc90c, 0x21, 0 - .dw 0xecc0, 0xc90c, 0xecff, 0xc90c, 0x21, 0 - .dw 0xed40, 0xc90c, 0xed7f, 0xc90c, 0x21, 0 - .dw 0xedc0, 0xc90c, 0xedff, 0xc90c, 0x21, 0 - .dw 0xee40, 0xc90c, 0xee7f, 0xc90c, 0x21, 0 - .dw 0xeec0, 0xc90c, 0xeeff, 0xc90c, 0x21, 0 - .dw 0xef40, 0xc90c, 0xef7f, 0xc90c, 0x21, 0 - .dw 0xefc0, 0xc90c, 0xefff, 0xc90c, 0x21, 0 - .dw 0xf040, 0xc90c, 0xf07f, 0xc90c, 0x21, 0 - .dw 0xf0c0, 0xc90c, 0xf0ff, 0xc90c, 0x21, 0 - .dw 0xf140, 0xc90c, 0xf17f, 0xc90c, 0x21, 0 - .dw 0xf1c0, 0xc90c, 0xf1ff, 0xc90c, 0x21, 0 - .dw 0xf240, 0xc90c, 0xf27f, 0xc90c, 0x21, 0 - .dw 0xf2c0, 0xc90c, 0xf2ff, 0xc90c, 0x21, 0 - .dw 0xf340, 0xc90c, 0xf37f, 0xc90c, 0x21, 0 - .dw 0xf3c0, 0xc90c, 0xf3ff, 0xc90c, 0x21, 0 - .dw 0xf440, 0xc90c, 0xf47f, 0xc90c, 0x21, 0 - .dw 0xf4c0, 0xc90c, 0xf4ff, 0xc90c, 0x21, 0 - .dw 0xf540, 0xc90c, 0xf57f, 0xc90c, 0x21, 0 - .dw 0xf5c0, 0xc90c, 0xf5ff, 0xc90c, 0x21, 0 - .dw 0xf640, 0xc90c, 0xf67f, 0xc90c, 0x21, 0 - .dw 0xf6c0, 0xc90c, 0xf6ff, 0xc90c, 0x21, 0 - .dw 0xf740, 0xc90c, 0xf77f, 0xc90c, 0x21, 0 - .dw 0xf7c0, 0xc90c, 0xf7ff, 0xc90c, 0x21, 0 - .dw 0xf840, 0xc90c, 0xf87f, 0xc90c, 0x21, 0 - .dw 0xf8c0, 0xc90c, 0xf8ff, 0xc90c, 0x21, 0 - .dw 0xf940, 0xc90c, 0xf97f, 0xc90c, 0x21, 0 - .dw 0xf9c0, 0xc90c, 0xffff, 0xc90c, 0x21, 0 - .dw 0x0040, 0xc90d, 0x007f, 0xc90d, 0x21, 0 - .dw 0x00c0, 0xc90d, 0x00ff, 0xc90d, 0x21, 0 - .dw 0x0140, 0xc90d, 0x017f, 0xc90d, 0x21, 0 - .dw 0x01c0, 0xc90d, 0x01ff, 0xc90d, 0x21, 0 - .dw 0x0240, 0xc90d, 0x027f, 0xc90d, 0x21, 0 - .dw 0x02c0, 0xc90d, 0x02ff, 0xc90d, 0x21, 0 - .dw 0x0340, 0xc90d, 0x037f, 0xc90d, 0x21, 0 - .dw 0x03c0, 0xc90d, 0x03ff, 0xc90d, 0x21, 0 - .dw 0x0440, 0xc90d, 0x047f, 0xc90d, 0x21, 0 - .dw 0x04c0, 0xc90d, 0x04ff, 0xc90d, 0x21, 0 - .dw 0x0540, 0xc90d, 0x057f, 0xc90d, 0x21, 0 - .dw 0x05c0, 0xc90d, 0x05ff, 0xc90d, 0x21, 0 - .dw 0x0640, 0xc90d, 0x067f, 0xc90d, 0x21, 0 - .dw 0x06c0, 0xc90d, 0x06ff, 0xc90d, 0x21, 0 - .dw 0x0740, 0xc90d, 0x077f, 0xc90d, 0x21, 0 - .dw 0x07c0, 0xc90d, 0x07ff, 0xc90d, 0x21, 0 - .dw 0x0840, 0xc90d, 0x087f, 0xc90d, 0x21, 0 - .dw 0x08c0, 0xc90d, 0x08ff, 0xc90d, 0x21, 0 - .dw 0x0940, 0xc90d, 0x097f, 0xc90d, 0x21, 0 - .dw 0x09c0, 0xc90d, 0x09ff, 0xc90d, 0x21, 0 - .dw 0x0a40, 0xc90d, 0x0a7f, 0xc90d, 0x21, 0 - .dw 0x0ac0, 0xc90d, 0x0aff, 0xc90d, 0x21, 0 - .dw 0x0b40, 0xc90d, 0x0b7f, 0xc90d, 0x21, 0 - .dw 0x0bc0, 0xc90d, 0x0bff, 0xc90d, 0x21, 0 - .dw 0x0c40, 0xc90d, 0x0c7f, 0xc90d, 0x21, 0 - .dw 0x0cc0, 0xc90d, 0x0cff, 0xc90d, 0x21, 0 - .dw 0x0d40, 0xc90d, 0x0d7f, 0xc90d, 0x21, 0 - .dw 0x0dc0, 0xc90d, 0x0dff, 0xc90d, 0x21, 0 - .dw 0x0e40, 0xc90d, 0x0e7f, 0xc90d, 0x21, 0 - .dw 0x0ec0, 0xc90d, 0x0eff, 0xc90d, 0x21, 0 - .dw 0x0f40, 0xc90d, 0x0f7f, 0xc90d, 0x21, 0 - .dw 0x0fc0, 0xc90d, 0x0fff, 0xc90d, 0x21, 0 - .dw 0x1040, 0xc90d, 0x107f, 0xc90d, 0x21, 0 - .dw 0x10c0, 0xc90d, 0x10ff, 0xc90d, 0x21, 0 - .dw 0x1140, 0xc90d, 0x117f, 0xc90d, 0x21, 0 - .dw 0x11c0, 0xc90d, 0x11ff, 0xc90d, 0x21, 0 - .dw 0x1240, 0xc90d, 0x127f, 0xc90d, 0x21, 0 - .dw 0x12c0, 0xc90d, 0x12ff, 0xc90d, 0x21, 0 - .dw 0x1340, 0xc90d, 0x137f, 0xc90d, 0x21, 0 - .dw 0x13c0, 0xc90d, 0x13ff, 0xc90d, 0x21, 0 - .dw 0x1440, 0xc90d, 0x147f, 0xc90d, 0x21, 0 - .dw 0x14c0, 0xc90d, 0x14ff, 0xc90d, 0x21, 0 - .dw 0x1540, 0xc90d, 0x157f, 0xc90d, 0x21, 0 - .dw 0x15c0, 0xc90d, 0x15ff, 0xc90d, 0x21, 0 - .dw 0x1640, 0xc90d, 0x167f, 0xc90d, 0x21, 0 - .dw 0x16c0, 0xc90d, 0x16ff, 0xc90d, 0x21, 0 - .dw 0x1740, 0xc90d, 0x177f, 0xc90d, 0x21, 0 - .dw 0x17c0, 0xc90d, 0x17ff, 0xc90d, 0x21, 0 - .dw 0x1840, 0xc90d, 0x187f, 0xc90d, 0x21, 0 - .dw 0x18c0, 0xc90d, 0x18ff, 0xc90d, 0x21, 0 - .dw 0x1940, 0xc90d, 0x197f, 0xc90d, 0x21, 0 - .dw 0x19c0, 0xc90d, 0x1fff, 0xc90d, 0x21, 0 - .dw 0x2040, 0xc90d, 0x207f, 0xc90d, 0x21, 0 - .dw 0x20c0, 0xc90d, 0x20ff, 0xc90d, 0x21, 0 - .dw 0x2140, 0xc90d, 0x217f, 0xc90d, 0x21, 0 - .dw 0x21c0, 0xc90d, 0x21ff, 0xc90d, 0x21, 0 - .dw 0x2240, 0xc90d, 0x227f, 0xc90d, 0x21, 0 - .dw 0x22c0, 0xc90d, 0x22ff, 0xc90d, 0x21, 0 - .dw 0x2340, 0xc90d, 0x237f, 0xc90d, 0x21, 0 - .dw 0x23c0, 0xc90d, 0x23ff, 0xc90d, 0x21, 0 - .dw 0x2440, 0xc90d, 0x247f, 0xc90d, 0x21, 0 - .dw 0x24c0, 0xc90d, 0x24ff, 0xc90d, 0x21, 0 - .dw 0x2540, 0xc90d, 0x257f, 0xc90d, 0x21, 0 - .dw 0x25c0, 0xc90d, 0x25ff, 0xc90d, 0x21, 0 - .dw 0x2640, 0xc90d, 0x267f, 0xc90d, 0x21, 0 - .dw 0x26c0, 0xc90d, 0x26ff, 0xc90d, 0x21, 0 - .dw 0x2740, 0xc90d, 0x277f, 0xc90d, 0x21, 0 - .dw 0x27c0, 0xc90d, 0x27ff, 0xc90d, 0x21, 0 - .dw 0x2840, 0xc90d, 0x287f, 0xc90d, 0x21, 0 - .dw 0x28c0, 0xc90d, 0x28ff, 0xc90d, 0x21, 0 - .dw 0x2940, 0xc90d, 0x297f, 0xc90d, 0x21, 0 - .dw 0x29c0, 0xc90d, 0x29ff, 0xc90d, 0x21, 0 - .dw 0x2a40, 0xc90d, 0x2a7f, 0xc90d, 0x21, 0 - .dw 0x2ac0, 0xc90d, 0x2aff, 0xc90d, 0x21, 0 - .dw 0x2b40, 0xc90d, 0x2b7f, 0xc90d, 0x21, 0 - .dw 0x2bc0, 0xc90d, 0x2bff, 0xc90d, 0x21, 0 - .dw 0x2c40, 0xc90d, 0x2c7f, 0xc90d, 0x21, 0 - .dw 0x2cc0, 0xc90d, 0x2cff, 0xc90d, 0x21, 0 - .dw 0x2d40, 0xc90d, 0x2d7f, 0xc90d, 0x21, 0 - .dw 0x2dc0, 0xc90d, 0x2dff, 0xc90d, 0x21, 0 - .dw 0x2e40, 0xc90d, 0x2e7f, 0xc90d, 0x21, 0 - .dw 0x2ec0, 0xc90d, 0x2eff, 0xc90d, 0x21, 0 - .dw 0x2f40, 0xc90d, 0x2f7f, 0xc90d, 0x21, 0 - .dw 0x2fc0, 0xc90d, 0x2fff, 0xc90d, 0x21, 0 - .dw 0x3040, 0xc90d, 0x307f, 0xc90d, 0x21, 0 - .dw 0x30c0, 0xc90d, 0x30ff, 0xc90d, 0x21, 0 - .dw 0x3140, 0xc90d, 0x317f, 0xc90d, 0x21, 0 - .dw 0x31c0, 0xc90d, 0x31ff, 0xc90d, 0x21, 0 - .dw 0x3240, 0xc90d, 0x327f, 0xc90d, 0x21, 0 - .dw 0x32c0, 0xc90d, 0x32ff, 0xc90d, 0x21, 0 - .dw 0x3340, 0xc90d, 0x337f, 0xc90d, 0x21, 0 - .dw 0x33c0, 0xc90d, 0x33ff, 0xc90d, 0x21, 0 - .dw 0x3440, 0xc90d, 0x347f, 0xc90d, 0x21, 0 - .dw 0x34c0, 0xc90d, 0x34ff, 0xc90d, 0x21, 0 - .dw 0x3540, 0xc90d, 0x357f, 0xc90d, 0x21, 0 - .dw 0x35c0, 0xc90d, 0x35ff, 0xc90d, 0x21, 0 - .dw 0x3640, 0xc90d, 0x367f, 0xc90d, 0x21, 0 - .dw 0x36c0, 0xc90d, 0x36ff, 0xc90d, 0x21, 0 - .dw 0x3740, 0xc90d, 0x377f, 0xc90d, 0x21, 0 - .dw 0x37c0, 0xc90d, 0x37ff, 0xc90d, 0x21, 0 - .dw 0x3840, 0xc90d, 0x387f, 0xc90d, 0x21, 0 - .dw 0x38c0, 0xc90d, 0x38ff, 0xc90d, 0x21, 0 - .dw 0x3940, 0xc90d, 0x397f, 0xc90d, 0x21, 0 - .dw 0x39c0, 0xc90d, 0x3fff, 0xc90d, 0x21, 0 - .dw 0x4040, 0xc90d, 0x407f, 0xc90d, 0x21, 0 - .dw 0x40c0, 0xc90d, 0x40ff, 0xc90d, 0x21, 0 - .dw 0x4140, 0xc90d, 0x417f, 0xc90d, 0x21, 0 - .dw 0x41c0, 0xc90d, 0x41ff, 0xc90d, 0x21, 0 - .dw 0x4240, 0xc90d, 0x427f, 0xc90d, 0x21, 0 - .dw 0x42c0, 0xc90d, 0x42ff, 0xc90d, 0x21, 0 - .dw 0x4340, 0xc90d, 0x437f, 0xc90d, 0x21, 0 - .dw 0x43c0, 0xc90d, 0x43ff, 0xc90d, 0x21, 0 - .dw 0x4440, 0xc90d, 0x447f, 0xc90d, 0x21, 0 - .dw 0x44c0, 0xc90d, 0x44ff, 0xc90d, 0x21, 0 - .dw 0x4540, 0xc90d, 0x457f, 0xc90d, 0x21, 0 - .dw 0x45c0, 0xc90d, 0x45ff, 0xc90d, 0x21, 0 - .dw 0x4640, 0xc90d, 0x467f, 0xc90d, 0x21, 0 - .dw 0x46c0, 0xc90d, 0x46ff, 0xc90d, 0x21, 0 - .dw 0x4740, 0xc90d, 0x477f, 0xc90d, 0x21, 0 - .dw 0x47c0, 0xc90d, 0x47ff, 0xc90d, 0x21, 0 - .dw 0x4840, 0xc90d, 0x487f, 0xc90d, 0x21, 0 - .dw 0x48c0, 0xc90d, 0x48ff, 0xc90d, 0x21, 0 - .dw 0x4940, 0xc90d, 0x497f, 0xc90d, 0x21, 0 - .dw 0x49c0, 0xc90d, 0x49ff, 0xc90d, 0x21, 0 - .dw 0x4a40, 0xc90d, 0x4a7f, 0xc90d, 0x21, 0 - .dw 0x4ac0, 0xc90d, 0x4aff, 0xc90d, 0x21, 0 - .dw 0x4b40, 0xc90d, 0x4b7f, 0xc90d, 0x21, 0 - .dw 0x4bc0, 0xc90d, 0x4bff, 0xc90d, 0x21, 0 - .dw 0x4c40, 0xc90d, 0x4c7f, 0xc90d, 0x21, 0 - .dw 0x4cc0, 0xc90d, 0x4cff, 0xc90d, 0x21, 0 - .dw 0x4d40, 0xc90d, 0x4d7f, 0xc90d, 0x21, 0 - .dw 0x4dc0, 0xc90d, 0x4dff, 0xc90d, 0x21, 0 - .dw 0x4e40, 0xc90d, 0x4e7f, 0xc90d, 0x21, 0 - .dw 0x4ec0, 0xc90d, 0x4eff, 0xc90d, 0x21, 0 - .dw 0x4f40, 0xc90d, 0x4f7f, 0xc90d, 0x21, 0 - .dw 0x4fc0, 0xc90d, 0x4fff, 0xc90d, 0x21, 0 - .dw 0x5040, 0xc90d, 0x507f, 0xc90d, 0x21, 0 - .dw 0x50c0, 0xc90d, 0x50ff, 0xc90d, 0x21, 0 - .dw 0x5140, 0xc90d, 0x517f, 0xc90d, 0x21, 0 - .dw 0x51c0, 0xc90d, 0x51ff, 0xc90d, 0x21, 0 - .dw 0x5240, 0xc90d, 0x527f, 0xc90d, 0x21, 0 - .dw 0x52c0, 0xc90d, 0x52ff, 0xc90d, 0x21, 0 - .dw 0x5340, 0xc90d, 0x537f, 0xc90d, 0x21, 0 - .dw 0x53c0, 0xc90d, 0x53ff, 0xc90d, 0x21, 0 - .dw 0x5440, 0xc90d, 0x547f, 0xc90d, 0x21, 0 - .dw 0x54c0, 0xc90d, 0x54ff, 0xc90d, 0x21, 0 - .dw 0x5540, 0xc90d, 0x557f, 0xc90d, 0x21, 0 - .dw 0x55c0, 0xc90d, 0x55ff, 0xc90d, 0x21, 0 - .dw 0x5640, 0xc90d, 0x567f, 0xc90d, 0x21, 0 - .dw 0x56c0, 0xc90d, 0x56ff, 0xc90d, 0x21, 0 - .dw 0x5740, 0xc90d, 0x577f, 0xc90d, 0x21, 0 - .dw 0x57c0, 0xc90d, 0x57ff, 0xc90d, 0x21, 0 - .dw 0x5840, 0xc90d, 0x587f, 0xc90d, 0x21, 0 - .dw 0x58c0, 0xc90d, 0x58ff, 0xc90d, 0x21, 0 - .dw 0x5940, 0xc90d, 0x597f, 0xc90d, 0x21, 0 - .dw 0x59c0, 0xc90d, 0x5fff, 0xc90d, 0x21, 0 - .dw 0x6040, 0xc90d, 0x607f, 0xc90d, 0x21, 0 - .dw 0x60c0, 0xc90d, 0x60ff, 0xc90d, 0x21, 0 - .dw 0x6140, 0xc90d, 0x617f, 0xc90d, 0x21, 0 - .dw 0x61c0, 0xc90d, 0x61ff, 0xc90d, 0x21, 0 - .dw 0x6240, 0xc90d, 0x627f, 0xc90d, 0x21, 0 - .dw 0x62c0, 0xc90d, 0x62ff, 0xc90d, 0x21, 0 - .dw 0x6340, 0xc90d, 0x637f, 0xc90d, 0x21, 0 - .dw 0x63c0, 0xc90d, 0x63ff, 0xc90d, 0x21, 0 - .dw 0x6440, 0xc90d, 0x647f, 0xc90d, 0x21, 0 - .dw 0x64c0, 0xc90d, 0x64ff, 0xc90d, 0x21, 0 - .dw 0x6540, 0xc90d, 0x657f, 0xc90d, 0x21, 0 - .dw 0x65c0, 0xc90d, 0x65ff, 0xc90d, 0x21, 0 - .dw 0x6640, 0xc90d, 0x667f, 0xc90d, 0x21, 0 - .dw 0x66c0, 0xc90d, 0x66ff, 0xc90d, 0x21, 0 - .dw 0x6740, 0xc90d, 0x677f, 0xc90d, 0x21, 0 - .dw 0x67c0, 0xc90d, 0x67ff, 0xc90d, 0x21, 0 - .dw 0x6840, 0xc90d, 0x687f, 0xc90d, 0x21, 0 - .dw 0x68c0, 0xc90d, 0x68ff, 0xc90d, 0x21, 0 - .dw 0x6940, 0xc90d, 0x697f, 0xc90d, 0x21, 0 - .dw 0x69c0, 0xc90d, 0x69ff, 0xc90d, 0x21, 0 - .dw 0x6a40, 0xc90d, 0x6a7f, 0xc90d, 0x21, 0 - .dw 0x6ac0, 0xc90d, 0x6aff, 0xc90d, 0x21, 0 - .dw 0x6b40, 0xc90d, 0x6b7f, 0xc90d, 0x21, 0 - .dw 0x6bc0, 0xc90d, 0x6bff, 0xc90d, 0x21, 0 - .dw 0x6c40, 0xc90d, 0x6c7f, 0xc90d, 0x21, 0 - .dw 0x6cc0, 0xc90d, 0x6cff, 0xc90d, 0x21, 0 - .dw 0x6d40, 0xc90d, 0x6d7f, 0xc90d, 0x21, 0 - .dw 0x6dc0, 0xc90d, 0x6dff, 0xc90d, 0x21, 0 - .dw 0x6e40, 0xc90d, 0x6e7f, 0xc90d, 0x21, 0 - .dw 0x6ec0, 0xc90d, 0x6eff, 0xc90d, 0x21, 0 - .dw 0x6f40, 0xc90d, 0x6f7f, 0xc90d, 0x21, 0 - .dw 0x6fc0, 0xc90d, 0x6fff, 0xc90d, 0x21, 0 - .dw 0x7040, 0xc90d, 0x707f, 0xc90d, 0x21, 0 - .dw 0x70c0, 0xc90d, 0x70ff, 0xc90d, 0x21, 0 - .dw 0x7140, 0xc90d, 0x717f, 0xc90d, 0x21, 0 - .dw 0x71c0, 0xc90d, 0x71ff, 0xc90d, 0x21, 0 - .dw 0x7240, 0xc90d, 0x727f, 0xc90d, 0x21, 0 - .dw 0x72c0, 0xc90d, 0x72ff, 0xc90d, 0x21, 0 - .dw 0x7340, 0xc90d, 0x737f, 0xc90d, 0x21, 0 - .dw 0x73c0, 0xc90d, 0x73ff, 0xc90d, 0x21, 0 - .dw 0x7440, 0xc90d, 0x747f, 0xc90d, 0x21, 0 - .dw 0x74c0, 0xc90d, 0x74ff, 0xc90d, 0x21, 0 - .dw 0x7540, 0xc90d, 0x757f, 0xc90d, 0x21, 0 - .dw 0x75c0, 0xc90d, 0x75ff, 0xc90d, 0x21, 0 - .dw 0x7640, 0xc90d, 0x767f, 0xc90d, 0x21, 0 - .dw 0x76c0, 0xc90d, 0x76ff, 0xc90d, 0x21, 0 - .dw 0x7740, 0xc90d, 0x777f, 0xc90d, 0x21, 0 - .dw 0x77c0, 0xc90d, 0x77ff, 0xc90d, 0x21, 0 - .dw 0x7840, 0xc90d, 0x787f, 0xc90d, 0x21, 0 - .dw 0x78c0, 0xc90d, 0x78ff, 0xc90d, 0x21, 0 - .dw 0x7940, 0xc90d, 0x797f, 0xc90d, 0x21, 0 - .dw 0x79c0, 0xc90d, 0x7fff, 0xc90d, 0x21, 0 - .dw 0x8040, 0xc90d, 0x807f, 0xc90d, 0x21, 0 - .dw 0x80c0, 0xc90d, 0x80ff, 0xc90d, 0x21, 0 - .dw 0x8140, 0xc90d, 0x817f, 0xc90d, 0x21, 0 - .dw 0x81c0, 0xc90d, 0x81ff, 0xc90d, 0x21, 0 - .dw 0x8240, 0xc90d, 0x827f, 0xc90d, 0x21, 0 - .dw 0x82c0, 0xc90d, 0x82ff, 0xc90d, 0x21, 0 - .dw 0x8340, 0xc90d, 0x837f, 0xc90d, 0x21, 0 - .dw 0x83c0, 0xc90d, 0x83ff, 0xc90d, 0x21, 0 - .dw 0x8440, 0xc90d, 0x847f, 0xc90d, 0x21, 0 - .dw 0x84c0, 0xc90d, 0x84ff, 0xc90d, 0x21, 0 - .dw 0x8540, 0xc90d, 0x857f, 0xc90d, 0x21, 0 - .dw 0x85c0, 0xc90d, 0x85ff, 0xc90d, 0x21, 0 - .dw 0x8640, 0xc90d, 0x867f, 0xc90d, 0x21, 0 - .dw 0x86c0, 0xc90d, 0x86ff, 0xc90d, 0x21, 0 - .dw 0x8740, 0xc90d, 0x877f, 0xc90d, 0x21, 0 - .dw 0x87c0, 0xc90d, 0x87ff, 0xc90d, 0x21, 0 - .dw 0x8840, 0xc90d, 0x887f, 0xc90d, 0x21, 0 - .dw 0x88c0, 0xc90d, 0x88ff, 0xc90d, 0x21, 0 - .dw 0x8940, 0xc90d, 0x897f, 0xc90d, 0x21, 0 - .dw 0x89c0, 0xc90d, 0x89ff, 0xc90d, 0x21, 0 - .dw 0x8a40, 0xc90d, 0x8a7f, 0xc90d, 0x21, 0 - .dw 0x8ac0, 0xc90d, 0x8aff, 0xc90d, 0x21, 0 - .dw 0x8b40, 0xc90d, 0x8b7f, 0xc90d, 0x21, 0 - .dw 0x8bc0, 0xc90d, 0x8bff, 0xc90d, 0x21, 0 - .dw 0x8c40, 0xc90d, 0x8c7f, 0xc90d, 0x21, 0 - .dw 0x8cc0, 0xc90d, 0x8cff, 0xc90d, 0x21, 0 - .dw 0x8d40, 0xc90d, 0x8d7f, 0xc90d, 0x21, 0 - .dw 0x8dc0, 0xc90d, 0x8dff, 0xc90d, 0x21, 0 - .dw 0x8e40, 0xc90d, 0x8e7f, 0xc90d, 0x21, 0 - .dw 0x8ec0, 0xc90d, 0x8eff, 0xc90d, 0x21, 0 - .dw 0x8f40, 0xc90d, 0x8f7f, 0xc90d, 0x21, 0 - .dw 0x8fc0, 0xc90d, 0x8fff, 0xc90d, 0x21, 0 - .dw 0x9040, 0xc90d, 0x907f, 0xc90d, 0x21, 0 - .dw 0x90c0, 0xc90d, 0x90ff, 0xc90d, 0x21, 0 - .dw 0x9140, 0xc90d, 0x917f, 0xc90d, 0x21, 0 - .dw 0x91c0, 0xc90d, 0x91ff, 0xc90d, 0x21, 0 - .dw 0x9240, 0xc90d, 0x927f, 0xc90d, 0x21, 0 - .dw 0x92c0, 0xc90d, 0x92ff, 0xc90d, 0x21, 0 - .dw 0x9340, 0xc90d, 0x937f, 0xc90d, 0x21, 0 - .dw 0x93c0, 0xc90d, 0x93ff, 0xc90d, 0x21, 0 - .dw 0x9440, 0xc90d, 0x947f, 0xc90d, 0x21, 0 - .dw 0x94c0, 0xc90d, 0x94ff, 0xc90d, 0x21, 0 - .dw 0x9540, 0xc90d, 0x957f, 0xc90d, 0x21, 0 - .dw 0x95c0, 0xc90d, 0x95ff, 0xc90d, 0x21, 0 - .dw 0x9640, 0xc90d, 0x967f, 0xc90d, 0x21, 0 - .dw 0x96c0, 0xc90d, 0x96ff, 0xc90d, 0x21, 0 - .dw 0x9740, 0xc90d, 0x977f, 0xc90d, 0x21, 0 - .dw 0x97c0, 0xc90d, 0x97ff, 0xc90d, 0x21, 0 - .dw 0x9840, 0xc90d, 0x987f, 0xc90d, 0x21, 0 - .dw 0x98c0, 0xc90d, 0x98ff, 0xc90d, 0x21, 0 - .dw 0x9940, 0xc90d, 0x997f, 0xc90d, 0x21, 0 - .dw 0x99c0, 0xc90d, 0x9fff, 0xc90d, 0x21, 0 - .dw 0xa040, 0xc90d, 0xa07f, 0xc90d, 0x21, 0 - .dw 0xa0c0, 0xc90d, 0xa0ff, 0xc90d, 0x21, 0 - .dw 0xa140, 0xc90d, 0xa17f, 0xc90d, 0x21, 0 - .dw 0xa1c0, 0xc90d, 0xa1ff, 0xc90d, 0x21, 0 - .dw 0xa240, 0xc90d, 0xa27f, 0xc90d, 0x21, 0 - .dw 0xa2c0, 0xc90d, 0xa2ff, 0xc90d, 0x21, 0 - .dw 0xa340, 0xc90d, 0xa37f, 0xc90d, 0x21, 0 - .dw 0xa3c0, 0xc90d, 0xa3ff, 0xc90d, 0x21, 0 - .dw 0xa440, 0xc90d, 0xa47f, 0xc90d, 0x21, 0 - .dw 0xa4c0, 0xc90d, 0xa4ff, 0xc90d, 0x21, 0 - .dw 0xa540, 0xc90d, 0xa57f, 0xc90d, 0x21, 0 - .dw 0xa5c0, 0xc90d, 0xa5ff, 0xc90d, 0x21, 0 - .dw 0xa640, 0xc90d, 0xa67f, 0xc90d, 0x21, 0 - .dw 0xa6c0, 0xc90d, 0xa6ff, 0xc90d, 0x21, 0 - .dw 0xa740, 0xc90d, 0xa77f, 0xc90d, 0x21, 0 - .dw 0xa7c0, 0xc90d, 0xa7ff, 0xc90d, 0x21, 0 - .dw 0xa840, 0xc90d, 0xa87f, 0xc90d, 0x21, 0 - .dw 0xa8c0, 0xc90d, 0xa8ff, 0xc90d, 0x21, 0 - .dw 0xa940, 0xc90d, 0xa97f, 0xc90d, 0x21, 0 - .dw 0xa9c0, 0xc90d, 0xa9ff, 0xc90d, 0x21, 0 - .dw 0xaa40, 0xc90d, 0xaa7f, 0xc90d, 0x21, 0 - .dw 0xaac0, 0xc90d, 0xaaff, 0xc90d, 0x21, 0 - .dw 0xab40, 0xc90d, 0xab7f, 0xc90d, 0x21, 0 - .dw 0xabc0, 0xc90d, 0xabff, 0xc90d, 0x21, 0 - .dw 0xac40, 0xc90d, 0xac7f, 0xc90d, 0x21, 0 - .dw 0xacc0, 0xc90d, 0xacff, 0xc90d, 0x21, 0 - .dw 0xad40, 0xc90d, 0xad7f, 0xc90d, 0x21, 0 - .dw 0xadc0, 0xc90d, 0xadff, 0xc90d, 0x21, 0 - .dw 0xae40, 0xc90d, 0xae7f, 0xc90d, 0x21, 0 - .dw 0xaec0, 0xc90d, 0xaeff, 0xc90d, 0x21, 0 - .dw 0xaf40, 0xc90d, 0xaf7f, 0xc90d, 0x21, 0 - .dw 0xafc0, 0xc90d, 0xafff, 0xc90d, 0x21, 0 - .dw 0xb040, 0xc90d, 0xb07f, 0xc90d, 0x21, 0 - .dw 0xb0c0, 0xc90d, 0xb0ff, 0xc90d, 0x21, 0 - .dw 0xb140, 0xc90d, 0xb17f, 0xc90d, 0x21, 0 - .dw 0xb1c0, 0xc90d, 0xb1ff, 0xc90d, 0x21, 0 - .dw 0xb240, 0xc90d, 0xb27f, 0xc90d, 0x21, 0 - .dw 0xb2c0, 0xc90d, 0xb2ff, 0xc90d, 0x21, 0 - .dw 0xb340, 0xc90d, 0xb37f, 0xc90d, 0x21, 0 - .dw 0xb3c0, 0xc90d, 0xb3ff, 0xc90d, 0x21, 0 - .dw 0xb440, 0xc90d, 0xb47f, 0xc90d, 0x21, 0 - .dw 0xb4c0, 0xc90d, 0xb4ff, 0xc90d, 0x21, 0 - .dw 0xb540, 0xc90d, 0xb57f, 0xc90d, 0x21, 0 - .dw 0xb5c0, 0xc90d, 0xb5ff, 0xc90d, 0x21, 0 - .dw 0xb640, 0xc90d, 0xb67f, 0xc90d, 0x21, 0 - .dw 0xb6c0, 0xc90d, 0xb6ff, 0xc90d, 0x21, 0 - .dw 0xb740, 0xc90d, 0xb77f, 0xc90d, 0x21, 0 - .dw 0xb7c0, 0xc90d, 0xb7ff, 0xc90d, 0x21, 0 - .dw 0xb840, 0xc90d, 0xb87f, 0xc90d, 0x21, 0 - .dw 0xb8c0, 0xc90d, 0xb8ff, 0xc90d, 0x21, 0 - .dw 0xb940, 0xc90d, 0xb97f, 0xc90d, 0x21, 0 - .dw 0xb9c0, 0xc90d, 0xbfff, 0xc90d, 0x21, 0 - .dw 0xc040, 0xc90d, 0xc07f, 0xc90d, 0x21, 0 - .dw 0xc0c0, 0xc90d, 0xc0ff, 0xc90d, 0x21, 0 - .dw 0xc140, 0xc90d, 0xc17f, 0xc90d, 0x21, 0 - .dw 0xc1c0, 0xc90d, 0xc1ff, 0xc90d, 0x21, 0 - .dw 0xc240, 0xc90d, 0xc27f, 0xc90d, 0x21, 0 - .dw 0xc2c0, 0xc90d, 0xc2ff, 0xc90d, 0x21, 0 - .dw 0xc340, 0xc90d, 0xc37f, 0xc90d, 0x21, 0 - .dw 0xc3c0, 0xc90d, 0xc3ff, 0xc90d, 0x21, 0 - .dw 0xc440, 0xc90d, 0xc47f, 0xc90d, 0x21, 0 - .dw 0xc4c0, 0xc90d, 0xc4ff, 0xc90d, 0x21, 0 - .dw 0xc540, 0xc90d, 0xc57f, 0xc90d, 0x21, 0 - .dw 0xc5c0, 0xc90d, 0xc5ff, 0xc90d, 0x21, 0 - .dw 0xc640, 0xc90d, 0xc67f, 0xc90d, 0x21, 0 - .dw 0xc6c0, 0xc90d, 0xc6ff, 0xc90d, 0x21, 0 - .dw 0xc740, 0xc90d, 0xc77f, 0xc90d, 0x21, 0 - .dw 0xc7c0, 0xc90d, 0xc7ff, 0xc90d, 0x21, 0 - .dw 0xc840, 0xc90d, 0xc87f, 0xc90d, 0x21, 0 - .dw 0xc8c0, 0xc90d, 0xc8ff, 0xc90d, 0x21, 0 - .dw 0xc940, 0xc90d, 0xc97f, 0xc90d, 0x21, 0 - .dw 0xc9c0, 0xc90d, 0xc9ff, 0xc90d, 0x21, 0 - .dw 0xca40, 0xc90d, 0xca7f, 0xc90d, 0x21, 0 - .dw 0xcac0, 0xc90d, 0xcaff, 0xc90d, 0x21, 0 - .dw 0xcb40, 0xc90d, 0xcb7f, 0xc90d, 0x21, 0 - .dw 0xcbc0, 0xc90d, 0xcbff, 0xc90d, 0x21, 0 - .dw 0xcc40, 0xc90d, 0xcc7f, 0xc90d, 0x21, 0 - .dw 0xccc0, 0xc90d, 0xccff, 0xc90d, 0x21, 0 - .dw 0xcd40, 0xc90d, 0xcd7f, 0xc90d, 0x21, 0 - .dw 0xcdc0, 0xc90d, 0xcdff, 0xc90d, 0x21, 0 - .dw 0xce40, 0xc90d, 0xce7f, 0xc90d, 0x21, 0 - .dw 0xcec0, 0xc90d, 0xceff, 0xc90d, 0x21, 0 - .dw 0xcf40, 0xc90d, 0xcf7f, 0xc90d, 0x21, 0 - .dw 0xcfc0, 0xc90d, 0xcfff, 0xc90d, 0x21, 0 - .dw 0xd040, 0xc90d, 0xd07f, 0xc90d, 0x21, 0 - .dw 0xd0c0, 0xc90d, 0xd0ff, 0xc90d, 0x21, 0 - .dw 0xd140, 0xc90d, 0xd17f, 0xc90d, 0x21, 0 - .dw 0xd1c0, 0xc90d, 0xd1ff, 0xc90d, 0x21, 0 - .dw 0xd240, 0xc90d, 0xd27f, 0xc90d, 0x21, 0 - .dw 0xd2c0, 0xc90d, 0xd2ff, 0xc90d, 0x21, 0 - .dw 0xd340, 0xc90d, 0xd37f, 0xc90d, 0x21, 0 - .dw 0xd3c0, 0xc90d, 0xd3ff, 0xc90d, 0x21, 0 - .dw 0xd440, 0xc90d, 0xd47f, 0xc90d, 0x21, 0 - .dw 0xd4c0, 0xc90d, 0xd4ff, 0xc90d, 0x21, 0 - .dw 0xd540, 0xc90d, 0xd57f, 0xc90d, 0x21, 0 - .dw 0xd5c0, 0xc90d, 0xd5ff, 0xc90d, 0x21, 0 - .dw 0xd640, 0xc90d, 0xd67f, 0xc90d, 0x21, 0 - .dw 0xd6c0, 0xc90d, 0xd6ff, 0xc90d, 0x21, 0 - .dw 0xd740, 0xc90d, 0xd77f, 0xc90d, 0x21, 0 - .dw 0xd7c0, 0xc90d, 0xd7ff, 0xc90d, 0x21, 0 - .dw 0xd840, 0xc90d, 0xd87f, 0xc90d, 0x21, 0 - .dw 0xd8c0, 0xc90d, 0xd8ff, 0xc90d, 0x21, 0 - .dw 0xd940, 0xc90d, 0xd97f, 0xc90d, 0x21, 0 - .dw 0xd9c0, 0xc90d, 0xdfff, 0xc90d, 0x21, 0 - .dw 0xe040, 0xc90d, 0xe07f, 0xc90d, 0x21, 0 - .dw 0xe0c0, 0xc90d, 0xe0ff, 0xc90d, 0x21, 0 - .dw 0xe140, 0xc90d, 0xe17f, 0xc90d, 0x21, 0 - .dw 0xe1c0, 0xc90d, 0xe1ff, 0xc90d, 0x21, 0 - .dw 0xe240, 0xc90d, 0xe27f, 0xc90d, 0x21, 0 - .dw 0xe2c0, 0xc90d, 0xe2ff, 0xc90d, 0x21, 0 - .dw 0xe340, 0xc90d, 0xe37f, 0xc90d, 0x21, 0 - .dw 0xe3c0, 0xc90d, 0xe3ff, 0xc90d, 0x21, 0 - .dw 0xe440, 0xc90d, 0xe47f, 0xc90d, 0x21, 0 - .dw 0xe4c0, 0xc90d, 0xe4ff, 0xc90d, 0x21, 0 - .dw 0xe540, 0xc90d, 0xe57f, 0xc90d, 0x21, 0 - .dw 0xe5c0, 0xc90d, 0xe5ff, 0xc90d, 0x21, 0 - .dw 0xe640, 0xc90d, 0xe67f, 0xc90d, 0x21, 0 - .dw 0xe6c0, 0xc90d, 0xe6ff, 0xc90d, 0x21, 0 - .dw 0xe740, 0xc90d, 0xe77f, 0xc90d, 0x21, 0 - .dw 0xe7c0, 0xc90d, 0xe7ff, 0xc90d, 0x21, 0 - .dw 0xe840, 0xc90d, 0xe87f, 0xc90d, 0x21, 0 - .dw 0xe8c0, 0xc90d, 0xe8ff, 0xc90d, 0x21, 0 - .dw 0xe940, 0xc90d, 0xe97f, 0xc90d, 0x21, 0 - .dw 0xe9c0, 0xc90d, 0xe9ff, 0xc90d, 0x21, 0 - .dw 0xea40, 0xc90d, 0xea7f, 0xc90d, 0x21, 0 - .dw 0xeac0, 0xc90d, 0xeaff, 0xc90d, 0x21, 0 - .dw 0xeb40, 0xc90d, 0xeb7f, 0xc90d, 0x21, 0 - .dw 0xebc0, 0xc90d, 0xebff, 0xc90d, 0x21, 0 - .dw 0xec40, 0xc90d, 0xec7f, 0xc90d, 0x21, 0 - .dw 0xecc0, 0xc90d, 0xecff, 0xc90d, 0x21, 0 - .dw 0xed40, 0xc90d, 0xed7f, 0xc90d, 0x21, 0 - .dw 0xedc0, 0xc90d, 0xedff, 0xc90d, 0x21, 0 - .dw 0xee40, 0xc90d, 0xee7f, 0xc90d, 0x21, 0 - .dw 0xeec0, 0xc90d, 0xeeff, 0xc90d, 0x21, 0 - .dw 0xef40, 0xc90d, 0xef7f, 0xc90d, 0x21, 0 - .dw 0xefc0, 0xc90d, 0xefff, 0xc90d, 0x21, 0 - .dw 0xf040, 0xc90d, 0xf07f, 0xc90d, 0x21, 0 - .dw 0xf0c0, 0xc90d, 0xf0ff, 0xc90d, 0x21, 0 - .dw 0xf140, 0xc90d, 0xf17f, 0xc90d, 0x21, 0 - .dw 0xf1c0, 0xc90d, 0xf1ff, 0xc90d, 0x21, 0 - .dw 0xf240, 0xc90d, 0xf27f, 0xc90d, 0x21, 0 - .dw 0xf2c0, 0xc90d, 0xf2ff, 0xc90d, 0x21, 0 - .dw 0xf340, 0xc90d, 0xf37f, 0xc90d, 0x21, 0 - .dw 0xf3c0, 0xc90d, 0xf3ff, 0xc90d, 0x21, 0 - .dw 0xf440, 0xc90d, 0xf47f, 0xc90d, 0x21, 0 - .dw 0xf4c0, 0xc90d, 0xf4ff, 0xc90d, 0x21, 0 - .dw 0xf540, 0xc90d, 0xf57f, 0xc90d, 0x21, 0 - .dw 0xf5c0, 0xc90d, 0xf5ff, 0xc90d, 0x21, 0 - .dw 0xf640, 0xc90d, 0xf67f, 0xc90d, 0x21, 0 - .dw 0xf6c0, 0xc90d, 0xf6ff, 0xc90d, 0x21, 0 - .dw 0xf740, 0xc90d, 0xf77f, 0xc90d, 0x21, 0 - .dw 0xf7c0, 0xc90d, 0xf7ff, 0xc90d, 0x21, 0 - .dw 0xf840, 0xc90d, 0xf87f, 0xc90d, 0x21, 0 - .dw 0xf8c0, 0xc90d, 0xf8ff, 0xc90d, 0x21, 0 - .dw 0xf940, 0xc90d, 0xf97f, 0xc90d, 0x21, 0 - .dw 0xf9c0, 0xc90d, 0xffff, 0xc90d, 0x21, 0 - .dw 0x0040, 0xc90e, 0x007f, 0xc90e, 0x21, 0 - .dw 0x00c0, 0xc90e, 0x00ff, 0xc90e, 0x21, 0 - .dw 0x0140, 0xc90e, 0x017f, 0xc90e, 0x21, 0 - .dw 0x01c0, 0xc90e, 0x01ff, 0xc90e, 0x21, 0 - .dw 0x0240, 0xc90e, 0x027f, 0xc90e, 0x21, 0 - .dw 0x02c0, 0xc90e, 0x02ff, 0xc90e, 0x21, 0 - .dw 0x0340, 0xc90e, 0x037f, 0xc90e, 0x21, 0 - .dw 0x03c0, 0xc90e, 0x03ff, 0xc90e, 0x21, 0 - .dw 0x0440, 0xc90e, 0x047f, 0xc90e, 0x21, 0 - .dw 0x04c0, 0xc90e, 0x04ff, 0xc90e, 0x21, 0 - .dw 0x0540, 0xc90e, 0x057f, 0xc90e, 0x21, 0 - .dw 0x05c0, 0xc90e, 0x05ff, 0xc90e, 0x21, 0 - .dw 0x0640, 0xc90e, 0x067f, 0xc90e, 0x21, 0 - .dw 0x06c0, 0xc90e, 0x06ff, 0xc90e, 0x21, 0 - .dw 0x0740, 0xc90e, 0x077f, 0xc90e, 0x21, 0 - .dw 0x07c0, 0xc90e, 0x07ff, 0xc90e, 0x21, 0 - .dw 0x0840, 0xc90e, 0x087f, 0xc90e, 0x21, 0 - .dw 0x08c0, 0xc90e, 0x08ff, 0xc90e, 0x21, 0 - .dw 0x0940, 0xc90e, 0x097f, 0xc90e, 0x21, 0 - .dw 0x09c0, 0xc90e, 0x09ff, 0xc90e, 0x21, 0 - .dw 0x0a40, 0xc90e, 0x0a7f, 0xc90e, 0x21, 0 - .dw 0x0ac0, 0xc90e, 0x0aff, 0xc90e, 0x21, 0 - .dw 0x0b40, 0xc90e, 0x0b7f, 0xc90e, 0x21, 0 - .dw 0x0bc0, 0xc90e, 0x0bff, 0xc90e, 0x21, 0 - .dw 0x0c40, 0xc90e, 0x0c7f, 0xc90e, 0x21, 0 - .dw 0x0cc0, 0xc90e, 0x0cff, 0xc90e, 0x21, 0 - .dw 0x0d40, 0xc90e, 0x0d7f, 0xc90e, 0x21, 0 - .dw 0x0dc0, 0xc90e, 0x0dff, 0xc90e, 0x21, 0 - .dw 0x0e40, 0xc90e, 0x0e7f, 0xc90e, 0x21, 0 - .dw 0x0ec0, 0xc90e, 0x0eff, 0xc90e, 0x21, 0 - .dw 0x0f40, 0xc90e, 0x0f7f, 0xc90e, 0x21, 0 - .dw 0x0fc0, 0xc90e, 0x0fff, 0xc90e, 0x21, 0 - .dw 0x1040, 0xc90e, 0x107f, 0xc90e, 0x21, 0 - .dw 0x10c0, 0xc90e, 0x10ff, 0xc90e, 0x21, 0 - .dw 0x1140, 0xc90e, 0x117f, 0xc90e, 0x21, 0 - .dw 0x11c0, 0xc90e, 0x11ff, 0xc90e, 0x21, 0 - .dw 0x1240, 0xc90e, 0x127f, 0xc90e, 0x21, 0 - .dw 0x12c0, 0xc90e, 0x12ff, 0xc90e, 0x21, 0 - .dw 0x1340, 0xc90e, 0x137f, 0xc90e, 0x21, 0 - .dw 0x13c0, 0xc90e, 0x13ff, 0xc90e, 0x21, 0 - .dw 0x1440, 0xc90e, 0x147f, 0xc90e, 0x21, 0 - .dw 0x14c0, 0xc90e, 0x14ff, 0xc90e, 0x21, 0 - .dw 0x1540, 0xc90e, 0x157f, 0xc90e, 0x21, 0 - .dw 0x15c0, 0xc90e, 0x15ff, 0xc90e, 0x21, 0 - .dw 0x1640, 0xc90e, 0x167f, 0xc90e, 0x21, 0 - .dw 0x16c0, 0xc90e, 0x16ff, 0xc90e, 0x21, 0 - .dw 0x1740, 0xc90e, 0x177f, 0xc90e, 0x21, 0 - .dw 0x17c0, 0xc90e, 0x17ff, 0xc90e, 0x21, 0 - .dw 0x1840, 0xc90e, 0x187f, 0xc90e, 0x21, 0 - .dw 0x18c0, 0xc90e, 0x18ff, 0xc90e, 0x21, 0 - .dw 0x1940, 0xc90e, 0x197f, 0xc90e, 0x21, 0 - .dw 0x19c0, 0xc90e, 0x1fff, 0xc90e, 0x21, 0 - .dw 0x2040, 0xc90e, 0x207f, 0xc90e, 0x21, 0 - .dw 0x20c0, 0xc90e, 0x20ff, 0xc90e, 0x21, 0 - .dw 0x2140, 0xc90e, 0x217f, 0xc90e, 0x21, 0 - .dw 0x21c0, 0xc90e, 0x21ff, 0xc90e, 0x21, 0 - .dw 0x2240, 0xc90e, 0x227f, 0xc90e, 0x21, 0 - .dw 0x22c0, 0xc90e, 0x22ff, 0xc90e, 0x21, 0 - .dw 0x2340, 0xc90e, 0x237f, 0xc90e, 0x21, 0 - .dw 0x23c0, 0xc90e, 0x23ff, 0xc90e, 0x21, 0 - .dw 0x2440, 0xc90e, 0x247f, 0xc90e, 0x21, 0 - .dw 0x24c0, 0xc90e, 0x24ff, 0xc90e, 0x21, 0 - .dw 0x2540, 0xc90e, 0x257f, 0xc90e, 0x21, 0 - .dw 0x25c0, 0xc90e, 0x25ff, 0xc90e, 0x21, 0 - .dw 0x2640, 0xc90e, 0x267f, 0xc90e, 0x21, 0 - .dw 0x26c0, 0xc90e, 0x26ff, 0xc90e, 0x21, 0 - .dw 0x2740, 0xc90e, 0x277f, 0xc90e, 0x21, 0 - .dw 0x27c0, 0xc90e, 0x27ff, 0xc90e, 0x21, 0 - .dw 0x2840, 0xc90e, 0x287f, 0xc90e, 0x21, 0 - .dw 0x28c0, 0xc90e, 0x28ff, 0xc90e, 0x21, 0 - .dw 0x2940, 0xc90e, 0x297f, 0xc90e, 0x21, 0 - .dw 0x29c0, 0xc90e, 0x29ff, 0xc90e, 0x21, 0 - .dw 0x2a40, 0xc90e, 0x2a7f, 0xc90e, 0x21, 0 - .dw 0x2ac0, 0xc90e, 0x2aff, 0xc90e, 0x21, 0 - .dw 0x2b40, 0xc90e, 0x2b7f, 0xc90e, 0x21, 0 - .dw 0x2bc0, 0xc90e, 0x2bff, 0xc90e, 0x21, 0 - .dw 0x2c40, 0xc90e, 0x2c7f, 0xc90e, 0x21, 0 - .dw 0x2cc0, 0xc90e, 0x2cff, 0xc90e, 0x21, 0 - .dw 0x2d40, 0xc90e, 0x2d7f, 0xc90e, 0x21, 0 - .dw 0x2dc0, 0xc90e, 0x2dff, 0xc90e, 0x21, 0 - .dw 0x2e40, 0xc90e, 0x2e7f, 0xc90e, 0x21, 0 - .dw 0x2ec0, 0xc90e, 0x2eff, 0xc90e, 0x21, 0 - .dw 0x2f40, 0xc90e, 0x2f7f, 0xc90e, 0x21, 0 - .dw 0x2fc0, 0xc90e, 0x2fff, 0xc90e, 0x21, 0 - .dw 0x3040, 0xc90e, 0x307f, 0xc90e, 0x21, 0 - .dw 0x30c0, 0xc90e, 0x30ff, 0xc90e, 0x21, 0 - .dw 0x3140, 0xc90e, 0x317f, 0xc90e, 0x21, 0 - .dw 0x31c0, 0xc90e, 0x31ff, 0xc90e, 0x21, 0 - .dw 0x3240, 0xc90e, 0x327f, 0xc90e, 0x21, 0 - .dw 0x32c0, 0xc90e, 0x32ff, 0xc90e, 0x21, 0 - .dw 0x3340, 0xc90e, 0x337f, 0xc90e, 0x21, 0 - .dw 0x33c0, 0xc90e, 0x33ff, 0xc90e, 0x21, 0 - .dw 0x3440, 0xc90e, 0x347f, 0xc90e, 0x21, 0 - .dw 0x34c0, 0xc90e, 0x34ff, 0xc90e, 0x21, 0 - .dw 0x3540, 0xc90e, 0x357f, 0xc90e, 0x21, 0 - .dw 0x35c0, 0xc90e, 0x35ff, 0xc90e, 0x21, 0 - .dw 0x3640, 0xc90e, 0x367f, 0xc90e, 0x21, 0 - .dw 0x36c0, 0xc90e, 0x36ff, 0xc90e, 0x21, 0 - .dw 0x3740, 0xc90e, 0x377f, 0xc90e, 0x21, 0 - .dw 0x37c0, 0xc90e, 0x37ff, 0xc90e, 0x21, 0 - .dw 0x3840, 0xc90e, 0x387f, 0xc90e, 0x21, 0 - .dw 0x38c0, 0xc90e, 0x38ff, 0xc90e, 0x21, 0 - .dw 0x3940, 0xc90e, 0x397f, 0xc90e, 0x21, 0 - .dw 0x39c0, 0xc90e, 0x3fff, 0xc90e, 0x21, 0 - .dw 0x4040, 0xc90e, 0x407f, 0xc90e, 0x21, 0 - .dw 0x40c0, 0xc90e, 0x40ff, 0xc90e, 0x21, 0 - .dw 0x4140, 0xc90e, 0x417f, 0xc90e, 0x21, 0 - .dw 0x41c0, 0xc90e, 0x41ff, 0xc90e, 0x21, 0 - .dw 0x4240, 0xc90e, 0x427f, 0xc90e, 0x21, 0 - .dw 0x42c0, 0xc90e, 0x42ff, 0xc90e, 0x21, 0 - .dw 0x4340, 0xc90e, 0x437f, 0xc90e, 0x21, 0 - .dw 0x43c0, 0xc90e, 0x43ff, 0xc90e, 0x21, 0 - .dw 0x4440, 0xc90e, 0x447f, 0xc90e, 0x21, 0 - .dw 0x44c0, 0xc90e, 0x44ff, 0xc90e, 0x21, 0 - .dw 0x4540, 0xc90e, 0x457f, 0xc90e, 0x21, 0 - .dw 0x45c0, 0xc90e, 0x45ff, 0xc90e, 0x21, 0 - .dw 0x4640, 0xc90e, 0x467f, 0xc90e, 0x21, 0 - .dw 0x46c0, 0xc90e, 0x46ff, 0xc90e, 0x21, 0 - .dw 0x4740, 0xc90e, 0x477f, 0xc90e, 0x21, 0 - .dw 0x47c0, 0xc90e, 0x47ff, 0xc90e, 0x21, 0 - .dw 0x4840, 0xc90e, 0x487f, 0xc90e, 0x21, 0 - .dw 0x48c0, 0xc90e, 0x48ff, 0xc90e, 0x21, 0 - .dw 0x4940, 0xc90e, 0x497f, 0xc90e, 0x21, 0 - .dw 0x49c0, 0xc90e, 0x49ff, 0xc90e, 0x21, 0 - .dw 0x4a40, 0xc90e, 0x4a7f, 0xc90e, 0x21, 0 - .dw 0x4ac0, 0xc90e, 0x4aff, 0xc90e, 0x21, 0 - .dw 0x4b40, 0xc90e, 0x4b7f, 0xc90e, 0x21, 0 - .dw 0x4bc0, 0xc90e, 0x4bff, 0xc90e, 0x21, 0 - .dw 0x4c40, 0xc90e, 0x4c7f, 0xc90e, 0x21, 0 - .dw 0x4cc0, 0xc90e, 0x4cff, 0xc90e, 0x21, 0 - .dw 0x4d40, 0xc90e, 0x4d7f, 0xc90e, 0x21, 0 - .dw 0x4dc0, 0xc90e, 0x4dff, 0xc90e, 0x21, 0 - .dw 0x4e40, 0xc90e, 0x4e7f, 0xc90e, 0x21, 0 - .dw 0x4ec0, 0xc90e, 0x4eff, 0xc90e, 0x21, 0 - .dw 0x4f40, 0xc90e, 0x4f7f, 0xc90e, 0x21, 0 - .dw 0x4fc0, 0xc90e, 0x4fff, 0xc90e, 0x21, 0 - .dw 0x5040, 0xc90e, 0x507f, 0xc90e, 0x21, 0 - .dw 0x50c0, 0xc90e, 0x50ff, 0xc90e, 0x21, 0 - .dw 0x5140, 0xc90e, 0x517f, 0xc90e, 0x21, 0 - .dw 0x51c0, 0xc90e, 0x51ff, 0xc90e, 0x21, 0 - .dw 0x5240, 0xc90e, 0x527f, 0xc90e, 0x21, 0 - .dw 0x52c0, 0xc90e, 0x52ff, 0xc90e, 0x21, 0 - .dw 0x5340, 0xc90e, 0x537f, 0xc90e, 0x21, 0 - .dw 0x53c0, 0xc90e, 0x53ff, 0xc90e, 0x21, 0 - .dw 0x5440, 0xc90e, 0x547f, 0xc90e, 0x21, 0 - .dw 0x54c0, 0xc90e, 0x54ff, 0xc90e, 0x21, 0 - .dw 0x5540, 0xc90e, 0x557f, 0xc90e, 0x21, 0 - .dw 0x55c0, 0xc90e, 0x55ff, 0xc90e, 0x21, 0 - .dw 0x5640, 0xc90e, 0x567f, 0xc90e, 0x21, 0 - .dw 0x56c0, 0xc90e, 0x56ff, 0xc90e, 0x21, 0 - .dw 0x5740, 0xc90e, 0x577f, 0xc90e, 0x21, 0 - .dw 0x57c0, 0xc90e, 0x57ff, 0xc90e, 0x21, 0 - .dw 0x5840, 0xc90e, 0x587f, 0xc90e, 0x21, 0 - .dw 0x58c0, 0xc90e, 0x58ff, 0xc90e, 0x21, 0 - .dw 0x5940, 0xc90e, 0x597f, 0xc90e, 0x21, 0 - .dw 0x59c0, 0xc90e, 0x5fff, 0xc90e, 0x21, 0 - .dw 0x6040, 0xc90e, 0x607f, 0xc90e, 0x21, 0 - .dw 0x60c0, 0xc90e, 0x60ff, 0xc90e, 0x21, 0 - .dw 0x6140, 0xc90e, 0x617f, 0xc90e, 0x21, 0 - .dw 0x61c0, 0xc90e, 0x61ff, 0xc90e, 0x21, 0 - .dw 0x6240, 0xc90e, 0x627f, 0xc90e, 0x21, 0 - .dw 0x62c0, 0xc90e, 0x62ff, 0xc90e, 0x21, 0 - .dw 0x6340, 0xc90e, 0x637f, 0xc90e, 0x21, 0 - .dw 0x63c0, 0xc90e, 0x63ff, 0xc90e, 0x21, 0 - .dw 0x6440, 0xc90e, 0x647f, 0xc90e, 0x21, 0 - .dw 0x64c0, 0xc90e, 0x64ff, 0xc90e, 0x21, 0 - .dw 0x6540, 0xc90e, 0x657f, 0xc90e, 0x21, 0 - .dw 0x65c0, 0xc90e, 0x65ff, 0xc90e, 0x21, 0 - .dw 0x6640, 0xc90e, 0x667f, 0xc90e, 0x21, 0 - .dw 0x66c0, 0xc90e, 0x66ff, 0xc90e, 0x21, 0 - .dw 0x6740, 0xc90e, 0x677f, 0xc90e, 0x21, 0 - .dw 0x67c0, 0xc90e, 0x67ff, 0xc90e, 0x21, 0 - .dw 0x6840, 0xc90e, 0x687f, 0xc90e, 0x21, 0 - .dw 0x68c0, 0xc90e, 0x68ff, 0xc90e, 0x21, 0 - .dw 0x6940, 0xc90e, 0x697f, 0xc90e, 0x21, 0 - .dw 0x69c0, 0xc90e, 0x69ff, 0xc90e, 0x21, 0 - .dw 0x6a40, 0xc90e, 0x6a7f, 0xc90e, 0x21, 0 - .dw 0x6ac0, 0xc90e, 0x6aff, 0xc90e, 0x21, 0 - .dw 0x6b40, 0xc90e, 0x6b7f, 0xc90e, 0x21, 0 - .dw 0x6bc0, 0xc90e, 0x6bff, 0xc90e, 0x21, 0 - .dw 0x6c40, 0xc90e, 0x6c7f, 0xc90e, 0x21, 0 - .dw 0x6cc0, 0xc90e, 0x6cff, 0xc90e, 0x21, 0 - .dw 0x6d40, 0xc90e, 0x6d7f, 0xc90e, 0x21, 0 - .dw 0x6dc0, 0xc90e, 0x6dff, 0xc90e, 0x21, 0 - .dw 0x6e40, 0xc90e, 0x6e7f, 0xc90e, 0x21, 0 - .dw 0x6ec0, 0xc90e, 0x6eff, 0xc90e, 0x21, 0 - .dw 0x6f40, 0xc90e, 0x6f7f, 0xc90e, 0x21, 0 - .dw 0x6fc0, 0xc90e, 0x6fff, 0xc90e, 0x21, 0 - .dw 0x7040, 0xc90e, 0x707f, 0xc90e, 0x21, 0 - .dw 0x70c0, 0xc90e, 0x70ff, 0xc90e, 0x21, 0 - .dw 0x7140, 0xc90e, 0x717f, 0xc90e, 0x21, 0 - .dw 0x71c0, 0xc90e, 0x71ff, 0xc90e, 0x21, 0 - .dw 0x7240, 0xc90e, 0x727f, 0xc90e, 0x21, 0 - .dw 0x72c0, 0xc90e, 0x72ff, 0xc90e, 0x21, 0 - .dw 0x7340, 0xc90e, 0x737f, 0xc90e, 0x21, 0 - .dw 0x73c0, 0xc90e, 0x73ff, 0xc90e, 0x21, 0 - .dw 0x7440, 0xc90e, 0x747f, 0xc90e, 0x21, 0 - .dw 0x74c0, 0xc90e, 0x74ff, 0xc90e, 0x21, 0 - .dw 0x7540, 0xc90e, 0x757f, 0xc90e, 0x21, 0 - .dw 0x75c0, 0xc90e, 0x75ff, 0xc90e, 0x21, 0 - .dw 0x7640, 0xc90e, 0x767f, 0xc90e, 0x21, 0 - .dw 0x76c0, 0xc90e, 0x76ff, 0xc90e, 0x21, 0 - .dw 0x7740, 0xc90e, 0x777f, 0xc90e, 0x21, 0 - .dw 0x77c0, 0xc90e, 0x77ff, 0xc90e, 0x21, 0 - .dw 0x7840, 0xc90e, 0x787f, 0xc90e, 0x21, 0 - .dw 0x78c0, 0xc90e, 0x78ff, 0xc90e, 0x21, 0 - .dw 0x7940, 0xc90e, 0x797f, 0xc90e, 0x21, 0 - .dw 0x79c0, 0xc90e, 0x7fff, 0xc90e, 0x21, 0 - .dw 0x8040, 0xc90e, 0x807f, 0xc90e, 0x21, 0 - .dw 0x80c0, 0xc90e, 0x80ff, 0xc90e, 0x21, 0 - .dw 0x8140, 0xc90e, 0x817f, 0xc90e, 0x21, 0 - .dw 0x81c0, 0xc90e, 0x81ff, 0xc90e, 0x21, 0 - .dw 0x8240, 0xc90e, 0x827f, 0xc90e, 0x21, 0 - .dw 0x82c0, 0xc90e, 0x82ff, 0xc90e, 0x21, 0 - .dw 0x8340, 0xc90e, 0x837f, 0xc90e, 0x21, 0 - .dw 0x83c0, 0xc90e, 0x83ff, 0xc90e, 0x21, 0 - .dw 0x8440, 0xc90e, 0x847f, 0xc90e, 0x21, 0 - .dw 0x84c0, 0xc90e, 0x84ff, 0xc90e, 0x21, 0 - .dw 0x8540, 0xc90e, 0x857f, 0xc90e, 0x21, 0 - .dw 0x85c0, 0xc90e, 0x85ff, 0xc90e, 0x21, 0 - .dw 0x8640, 0xc90e, 0x867f, 0xc90e, 0x21, 0 - .dw 0x86c0, 0xc90e, 0x86ff, 0xc90e, 0x21, 0 - .dw 0x8740, 0xc90e, 0x877f, 0xc90e, 0x21, 0 - .dw 0x87c0, 0xc90e, 0x87ff, 0xc90e, 0x21, 0 - .dw 0x8840, 0xc90e, 0x887f, 0xc90e, 0x21, 0 - .dw 0x88c0, 0xc90e, 0x88ff, 0xc90e, 0x21, 0 - .dw 0x8940, 0xc90e, 0x897f, 0xc90e, 0x21, 0 - .dw 0x89c0, 0xc90e, 0x89ff, 0xc90e, 0x21, 0 - .dw 0x8a40, 0xc90e, 0x8a7f, 0xc90e, 0x21, 0 - .dw 0x8ac0, 0xc90e, 0x8aff, 0xc90e, 0x21, 0 - .dw 0x8b40, 0xc90e, 0x8b7f, 0xc90e, 0x21, 0 - .dw 0x8bc0, 0xc90e, 0x8bff, 0xc90e, 0x21, 0 - .dw 0x8c40, 0xc90e, 0x8c7f, 0xc90e, 0x21, 0 - .dw 0x8cc0, 0xc90e, 0x8cff, 0xc90e, 0x21, 0 - .dw 0x8d40, 0xc90e, 0x8d7f, 0xc90e, 0x21, 0 - .dw 0x8dc0, 0xc90e, 0x8dff, 0xc90e, 0x21, 0 - .dw 0x8e40, 0xc90e, 0x8e7f, 0xc90e, 0x21, 0 - .dw 0x8ec0, 0xc90e, 0x8eff, 0xc90e, 0x21, 0 - .dw 0x8f40, 0xc90e, 0x8f7f, 0xc90e, 0x21, 0 - .dw 0x8fc0, 0xc90e, 0x8fff, 0xc90e, 0x21, 0 - .dw 0x9040, 0xc90e, 0x907f, 0xc90e, 0x21, 0 - .dw 0x90c0, 0xc90e, 0x90ff, 0xc90e, 0x21, 0 - .dw 0x9140, 0xc90e, 0x917f, 0xc90e, 0x21, 0 - .dw 0x91c0, 0xc90e, 0x91ff, 0xc90e, 0x21, 0 - .dw 0x9240, 0xc90e, 0x927f, 0xc90e, 0x21, 0 - .dw 0x92c0, 0xc90e, 0x92ff, 0xc90e, 0x21, 0 - .dw 0x9340, 0xc90e, 0x937f, 0xc90e, 0x21, 0 - .dw 0x93c0, 0xc90e, 0x93ff, 0xc90e, 0x21, 0 - .dw 0x9440, 0xc90e, 0x947f, 0xc90e, 0x21, 0 - .dw 0x94c0, 0xc90e, 0x94ff, 0xc90e, 0x21, 0 - .dw 0x9540, 0xc90e, 0x957f, 0xc90e, 0x21, 0 - .dw 0x95c0, 0xc90e, 0x95ff, 0xc90e, 0x21, 0 - .dw 0x9640, 0xc90e, 0x967f, 0xc90e, 0x21, 0 - .dw 0x96c0, 0xc90e, 0x96ff, 0xc90e, 0x21, 0 - .dw 0x9740, 0xc90e, 0x977f, 0xc90e, 0x21, 0 - .dw 0x97c0, 0xc90e, 0x97ff, 0xc90e, 0x21, 0 - .dw 0x9840, 0xc90e, 0x987f, 0xc90e, 0x21, 0 - .dw 0x98c0, 0xc90e, 0x98ff, 0xc90e, 0x21, 0 - .dw 0x9940, 0xc90e, 0x997f, 0xc90e, 0x21, 0 - .dw 0x99c0, 0xc90e, 0x9fff, 0xc90e, 0x21, 0 - .dw 0xa040, 0xc90e, 0xa07f, 0xc90e, 0x21, 0 - .dw 0xa0c0, 0xc90e, 0xa0ff, 0xc90e, 0x21, 0 - .dw 0xa140, 0xc90e, 0xa17f, 0xc90e, 0x21, 0 - .dw 0xa1c0, 0xc90e, 0xa1ff, 0xc90e, 0x21, 0 - .dw 0xa240, 0xc90e, 0xa27f, 0xc90e, 0x21, 0 - .dw 0xa2c0, 0xc90e, 0xa2ff, 0xc90e, 0x21, 0 - .dw 0xa340, 0xc90e, 0xa37f, 0xc90e, 0x21, 0 - .dw 0xa3c0, 0xc90e, 0xa3ff, 0xc90e, 0x21, 0 - .dw 0xa440, 0xc90e, 0xa47f, 0xc90e, 0x21, 0 - .dw 0xa4c0, 0xc90e, 0xa4ff, 0xc90e, 0x21, 0 - .dw 0xa540, 0xc90e, 0xa57f, 0xc90e, 0x21, 0 - .dw 0xa5c0, 0xc90e, 0xa5ff, 0xc90e, 0x21, 0 - .dw 0xa640, 0xc90e, 0xa67f, 0xc90e, 0x21, 0 - .dw 0xa6c0, 0xc90e, 0xa6ff, 0xc90e, 0x21, 0 - .dw 0xa740, 0xc90e, 0xa77f, 0xc90e, 0x21, 0 - .dw 0xa7c0, 0xc90e, 0xa7ff, 0xc90e, 0x21, 0 - .dw 0xa840, 0xc90e, 0xa87f, 0xc90e, 0x21, 0 - .dw 0xa8c0, 0xc90e, 0xa8ff, 0xc90e, 0x21, 0 - .dw 0xa940, 0xc90e, 0xa97f, 0xc90e, 0x21, 0 - .dw 0xa9c0, 0xc90e, 0xa9ff, 0xc90e, 0x21, 0 - .dw 0xaa40, 0xc90e, 0xaa7f, 0xc90e, 0x21, 0 - .dw 0xaac0, 0xc90e, 0xaaff, 0xc90e, 0x21, 0 - .dw 0xab40, 0xc90e, 0xab7f, 0xc90e, 0x21, 0 - .dw 0xabc0, 0xc90e, 0xabff, 0xc90e, 0x21, 0 - .dw 0xac40, 0xc90e, 0xac7f, 0xc90e, 0x21, 0 - .dw 0xacc0, 0xc90e, 0xacff, 0xc90e, 0x21, 0 - .dw 0xad40, 0xc90e, 0xad7f, 0xc90e, 0x21, 0 - .dw 0xadc0, 0xc90e, 0xadff, 0xc90e, 0x21, 0 - .dw 0xae40, 0xc90e, 0xae7f, 0xc90e, 0x21, 0 - .dw 0xaec0, 0xc90e, 0xaeff, 0xc90e, 0x21, 0 - .dw 0xaf40, 0xc90e, 0xaf7f, 0xc90e, 0x21, 0 - .dw 0xafc0, 0xc90e, 0xafff, 0xc90e, 0x21, 0 - .dw 0xb040, 0xc90e, 0xb07f, 0xc90e, 0x21, 0 - .dw 0xb0c0, 0xc90e, 0xb0ff, 0xc90e, 0x21, 0 - .dw 0xb140, 0xc90e, 0xb17f, 0xc90e, 0x21, 0 - .dw 0xb1c0, 0xc90e, 0xb1ff, 0xc90e, 0x21, 0 - .dw 0xb240, 0xc90e, 0xb27f, 0xc90e, 0x21, 0 - .dw 0xb2c0, 0xc90e, 0xb2ff, 0xc90e, 0x21, 0 - .dw 0xb340, 0xc90e, 0xb37f, 0xc90e, 0x21, 0 - .dw 0xb3c0, 0xc90e, 0xb3ff, 0xc90e, 0x21, 0 - .dw 0xb440, 0xc90e, 0xb47f, 0xc90e, 0x21, 0 - .dw 0xb4c0, 0xc90e, 0xb4ff, 0xc90e, 0x21, 0 - .dw 0xb540, 0xc90e, 0xb57f, 0xc90e, 0x21, 0 - .dw 0xb5c0, 0xc90e, 0xb5ff, 0xc90e, 0x21, 0 - .dw 0xb640, 0xc90e, 0xb67f, 0xc90e, 0x21, 0 - .dw 0xb6c0, 0xc90e, 0xb6ff, 0xc90e, 0x21, 0 - .dw 0xb740, 0xc90e, 0xb77f, 0xc90e, 0x21, 0 - .dw 0xb7c0, 0xc90e, 0xb7ff, 0xc90e, 0x21, 0 - .dw 0xb840, 0xc90e, 0xb87f, 0xc90e, 0x21, 0 - .dw 0xb8c0, 0xc90e, 0xb8ff, 0xc90e, 0x21, 0 - .dw 0xb940, 0xc90e, 0xb97f, 0xc90e, 0x21, 0 - .dw 0xb9c0, 0xc90e, 0xbfff, 0xc90e, 0x21, 0 - .dw 0xc040, 0xc90e, 0xc07f, 0xc90e, 0x21, 0 - .dw 0xc0c0, 0xc90e, 0xc0ff, 0xc90e, 0x21, 0 - .dw 0xc140, 0xc90e, 0xc17f, 0xc90e, 0x21, 0 - .dw 0xc1c0, 0xc90e, 0xc1ff, 0xc90e, 0x21, 0 - .dw 0xc240, 0xc90e, 0xc27f, 0xc90e, 0x21, 0 - .dw 0xc2c0, 0xc90e, 0xc2ff, 0xc90e, 0x21, 0 - .dw 0xc340, 0xc90e, 0xc37f, 0xc90e, 0x21, 0 - .dw 0xc3c0, 0xc90e, 0xc3ff, 0xc90e, 0x21, 0 - .dw 0xc440, 0xc90e, 0xc47f, 0xc90e, 0x21, 0 - .dw 0xc4c0, 0xc90e, 0xc4ff, 0xc90e, 0x21, 0 - .dw 0xc540, 0xc90e, 0xc57f, 0xc90e, 0x21, 0 - .dw 0xc5c0, 0xc90e, 0xc5ff, 0xc90e, 0x21, 0 - .dw 0xc640, 0xc90e, 0xc67f, 0xc90e, 0x21, 0 - .dw 0xc6c0, 0xc90e, 0xc6ff, 0xc90e, 0x21, 0 - .dw 0xc740, 0xc90e, 0xc77f, 0xc90e, 0x21, 0 - .dw 0xc7c0, 0xc90e, 0xc7ff, 0xc90e, 0x21, 0 - .dw 0xc840, 0xc90e, 0xc87f, 0xc90e, 0x21, 0 - .dw 0xc8c0, 0xc90e, 0xc8ff, 0xc90e, 0x21, 0 - .dw 0xc940, 0xc90e, 0xc97f, 0xc90e, 0x21, 0 - .dw 0xc9c0, 0xc90e, 0xc9ff, 0xc90e, 0x21, 0 - .dw 0xca40, 0xc90e, 0xca7f, 0xc90e, 0x21, 0 - .dw 0xcac0, 0xc90e, 0xcaff, 0xc90e, 0x21, 0 - .dw 0xcb40, 0xc90e, 0xcb7f, 0xc90e, 0x21, 0 - .dw 0xcbc0, 0xc90e, 0xcbff, 0xc90e, 0x21, 0 - .dw 0xcc40, 0xc90e, 0xcc7f, 0xc90e, 0x21, 0 - .dw 0xccc0, 0xc90e, 0xccff, 0xc90e, 0x21, 0 - .dw 0xcd40, 0xc90e, 0xcd7f, 0xc90e, 0x21, 0 - .dw 0xcdc0, 0xc90e, 0xcdff, 0xc90e, 0x21, 0 - .dw 0xce40, 0xc90e, 0xce7f, 0xc90e, 0x21, 0 - .dw 0xcec0, 0xc90e, 0xceff, 0xc90e, 0x21, 0 - .dw 0xcf40, 0xc90e, 0xcf7f, 0xc90e, 0x21, 0 - .dw 0xcfc0, 0xc90e, 0xcfff, 0xc90e, 0x21, 0 - .dw 0xd040, 0xc90e, 0xd07f, 0xc90e, 0x21, 0 - .dw 0xd0c0, 0xc90e, 0xd0ff, 0xc90e, 0x21, 0 - .dw 0xd140, 0xc90e, 0xd17f, 0xc90e, 0x21, 0 - .dw 0xd1c0, 0xc90e, 0xd1ff, 0xc90e, 0x21, 0 - .dw 0xd240, 0xc90e, 0xd27f, 0xc90e, 0x21, 0 - .dw 0xd2c0, 0xc90e, 0xd2ff, 0xc90e, 0x21, 0 - .dw 0xd340, 0xc90e, 0xd37f, 0xc90e, 0x21, 0 - .dw 0xd3c0, 0xc90e, 0xd3ff, 0xc90e, 0x21, 0 - .dw 0xd440, 0xc90e, 0xd47f, 0xc90e, 0x21, 0 - .dw 0xd4c0, 0xc90e, 0xd4ff, 0xc90e, 0x21, 0 - .dw 0xd540, 0xc90e, 0xd57f, 0xc90e, 0x21, 0 - .dw 0xd5c0, 0xc90e, 0xd5ff, 0xc90e, 0x21, 0 - .dw 0xd640, 0xc90e, 0xd67f, 0xc90e, 0x21, 0 - .dw 0xd6c0, 0xc90e, 0xd6ff, 0xc90e, 0x21, 0 - .dw 0xd740, 0xc90e, 0xd77f, 0xc90e, 0x21, 0 - .dw 0xd7c0, 0xc90e, 0xd7ff, 0xc90e, 0x21, 0 - .dw 0xd840, 0xc90e, 0xd87f, 0xc90e, 0x21, 0 - .dw 0xd8c0, 0xc90e, 0xd8ff, 0xc90e, 0x21, 0 - .dw 0xd940, 0xc90e, 0xd97f, 0xc90e, 0x21, 0 - .dw 0xd9c0, 0xc90e, 0xdfff, 0xc90e, 0x21, 0 - .dw 0xe040, 0xc90e, 0xe07f, 0xc90e, 0x21, 0 - .dw 0xe0c0, 0xc90e, 0xe0ff, 0xc90e, 0x21, 0 - .dw 0xe140, 0xc90e, 0xe17f, 0xc90e, 0x21, 0 - .dw 0xe1c0, 0xc90e, 0xe1ff, 0xc90e, 0x21, 0 - .dw 0xe240, 0xc90e, 0xe27f, 0xc90e, 0x21, 0 - .dw 0xe2c0, 0xc90e, 0xe2ff, 0xc90e, 0x21, 0 - .dw 0xe340, 0xc90e, 0xe37f, 0xc90e, 0x21, 0 - .dw 0xe3c0, 0xc90e, 0xe3ff, 0xc90e, 0x21, 0 - .dw 0xe440, 0xc90e, 0xe47f, 0xc90e, 0x21, 0 - .dw 0xe4c0, 0xc90e, 0xe4ff, 0xc90e, 0x21, 0 - .dw 0xe540, 0xc90e, 0xe57f, 0xc90e, 0x21, 0 - .dw 0xe5c0, 0xc90e, 0xe5ff, 0xc90e, 0x21, 0 - .dw 0xe640, 0xc90e, 0xe67f, 0xc90e, 0x21, 0 - .dw 0xe6c0, 0xc90e, 0xe6ff, 0xc90e, 0x21, 0 - .dw 0xe740, 0xc90e, 0xe77f, 0xc90e, 0x21, 0 - .dw 0xe7c0, 0xc90e, 0xe7ff, 0xc90e, 0x21, 0 - .dw 0xe840, 0xc90e, 0xe87f, 0xc90e, 0x21, 0 - .dw 0xe8c0, 0xc90e, 0xe8ff, 0xc90e, 0x21, 0 - .dw 0xe940, 0xc90e, 0xe97f, 0xc90e, 0x21, 0 - .dw 0xe9c0, 0xc90e, 0xe9ff, 0xc90e, 0x21, 0 - .dw 0xea40, 0xc90e, 0xea7f, 0xc90e, 0x21, 0 - .dw 0xeac0, 0xc90e, 0xeaff, 0xc90e, 0x21, 0 - .dw 0xeb40, 0xc90e, 0xeb7f, 0xc90e, 0x21, 0 - .dw 0xebc0, 0xc90e, 0xebff, 0xc90e, 0x21, 0 - .dw 0xec40, 0xc90e, 0xec7f, 0xc90e, 0x21, 0 - .dw 0xecc0, 0xc90e, 0xecff, 0xc90e, 0x21, 0 - .dw 0xed40, 0xc90e, 0xed7f, 0xc90e, 0x21, 0 - .dw 0xedc0, 0xc90e, 0xedff, 0xc90e, 0x21, 0 - .dw 0xee40, 0xc90e, 0xee7f, 0xc90e, 0x21, 0 - .dw 0xeec0, 0xc90e, 0xeeff, 0xc90e, 0x21, 0 - .dw 0xef40, 0xc90e, 0xef7f, 0xc90e, 0x21, 0 - .dw 0xefc0, 0xc90e, 0xefff, 0xc90e, 0x21, 0 - .dw 0xf040, 0xc90e, 0xf07f, 0xc90e, 0x21, 0 - .dw 0xf0c0, 0xc90e, 0xf0ff, 0xc90e, 0x21, 0 - .dw 0xf140, 0xc90e, 0xf17f, 0xc90e, 0x21, 0 - .dw 0xf1c0, 0xc90e, 0xf1ff, 0xc90e, 0x21, 0 - .dw 0xf240, 0xc90e, 0xf27f, 0xc90e, 0x21, 0 - .dw 0xf2c0, 0xc90e, 0xf2ff, 0xc90e, 0x21, 0 - .dw 0xf340, 0xc90e, 0xf37f, 0xc90e, 0x21, 0 - .dw 0xf3c0, 0xc90e, 0xf3ff, 0xc90e, 0x21, 0 - .dw 0xf440, 0xc90e, 0xf47f, 0xc90e, 0x21, 0 - .dw 0xf4c0, 0xc90e, 0xf4ff, 0xc90e, 0x21, 0 - .dw 0xf540, 0xc90e, 0xf57f, 0xc90e, 0x21, 0 - .dw 0xf5c0, 0xc90e, 0xf5ff, 0xc90e, 0x21, 0 - .dw 0xf640, 0xc90e, 0xf67f, 0xc90e, 0x21, 0 - .dw 0xf6c0, 0xc90e, 0xf6ff, 0xc90e, 0x21, 0 - .dw 0xf740, 0xc90e, 0xf77f, 0xc90e, 0x21, 0 - .dw 0xf7c0, 0xc90e, 0xf7ff, 0xc90e, 0x21, 0 - .dw 0xf840, 0xc90e, 0xf87f, 0xc90e, 0x21, 0 - .dw 0xf8c0, 0xc90e, 0xf8ff, 0xc90e, 0x21, 0 - .dw 0xf940, 0xc90e, 0xf97f, 0xc90e, 0x21, 0 - .dw 0xf9c0, 0xc90e, 0xffff, 0xc90e, 0x21, 0 - .dw 0x0040, 0xc90f, 0x007f, 0xc90f, 0x21, 0 - .dw 0x00c0, 0xc90f, 0x00ff, 0xc90f, 0x21, 0 - .dw 0x0140, 0xc90f, 0x017f, 0xc90f, 0x21, 0 - .dw 0x01c0, 0xc90f, 0x01ff, 0xc90f, 0x21, 0 - .dw 0x0240, 0xc90f, 0x027f, 0xc90f, 0x21, 0 - .dw 0x02c0, 0xc90f, 0x02ff, 0xc90f, 0x21, 0 - .dw 0x0340, 0xc90f, 0x037f, 0xc90f, 0x21, 0 - .dw 0x03c0, 0xc90f, 0x03ff, 0xc90f, 0x21, 0 - .dw 0x0440, 0xc90f, 0x047f, 0xc90f, 0x21, 0 - .dw 0x04c0, 0xc90f, 0x04ff, 0xc90f, 0x21, 0 - .dw 0x0540, 0xc90f, 0x057f, 0xc90f, 0x21, 0 - .dw 0x05c0, 0xc90f, 0x05ff, 0xc90f, 0x21, 0 - .dw 0x0640, 0xc90f, 0x067f, 0xc90f, 0x21, 0 - .dw 0x06c0, 0xc90f, 0x06ff, 0xc90f, 0x21, 0 - .dw 0x0740, 0xc90f, 0x077f, 0xc90f, 0x21, 0 - .dw 0x07c0, 0xc90f, 0x07ff, 0xc90f, 0x21, 0 - .dw 0x0840, 0xc90f, 0x087f, 0xc90f, 0x21, 0 - .dw 0x08c0, 0xc90f, 0x08ff, 0xc90f, 0x21, 0 - .dw 0x0940, 0xc90f, 0x097f, 0xc90f, 0x21, 0 - .dw 0x09c0, 0xc90f, 0x09ff, 0xc90f, 0x21, 0 - .dw 0x0a40, 0xc90f, 0x0a7f, 0xc90f, 0x21, 0 - .dw 0x0ac0, 0xc90f, 0x0aff, 0xc90f, 0x21, 0 - .dw 0x0b40, 0xc90f, 0x0b7f, 0xc90f, 0x21, 0 - .dw 0x0bc0, 0xc90f, 0x0bff, 0xc90f, 0x21, 0 - .dw 0x0c40, 0xc90f, 0x0c7f, 0xc90f, 0x21, 0 - .dw 0x0cc0, 0xc90f, 0x0cff, 0xc90f, 0x21, 0 - .dw 0x0d40, 0xc90f, 0x0d7f, 0xc90f, 0x21, 0 - .dw 0x0dc0, 0xc90f, 0x0dff, 0xc90f, 0x21, 0 - .dw 0x0e40, 0xc90f, 0x0e7f, 0xc90f, 0x21, 0 - .dw 0x0ec0, 0xc90f, 0x0eff, 0xc90f, 0x21, 0 - .dw 0x0f40, 0xc90f, 0x0f7f, 0xc90f, 0x21, 0 - .dw 0x0fc0, 0xc90f, 0x0fff, 0xc90f, 0x21, 0 - .dw 0x1040, 0xc90f, 0x107f, 0xc90f, 0x21, 0 - .dw 0x10c0, 0xc90f, 0x10ff, 0xc90f, 0x21, 0 - .dw 0x1140, 0xc90f, 0x117f, 0xc90f, 0x21, 0 - .dw 0x11c0, 0xc90f, 0x11ff, 0xc90f, 0x21, 0 - .dw 0x1240, 0xc90f, 0x127f, 0xc90f, 0x21, 0 - .dw 0x12c0, 0xc90f, 0x12ff, 0xc90f, 0x21, 0 - .dw 0x1340, 0xc90f, 0x137f, 0xc90f, 0x21, 0 - .dw 0x13c0, 0xc90f, 0x13ff, 0xc90f, 0x21, 0 - .dw 0x1440, 0xc90f, 0x147f, 0xc90f, 0x21, 0 - .dw 0x14c0, 0xc90f, 0x14ff, 0xc90f, 0x21, 0 - .dw 0x1540, 0xc90f, 0x157f, 0xc90f, 0x21, 0 - .dw 0x15c0, 0xc90f, 0x15ff, 0xc90f, 0x21, 0 - .dw 0x1640, 0xc90f, 0x167f, 0xc90f, 0x21, 0 - .dw 0x16c0, 0xc90f, 0x16ff, 0xc90f, 0x21, 0 - .dw 0x1740, 0xc90f, 0x177f, 0xc90f, 0x21, 0 - .dw 0x17c0, 0xc90f, 0x17ff, 0xc90f, 0x21, 0 - .dw 0x1840, 0xc90f, 0x187f, 0xc90f, 0x21, 0 - .dw 0x18c0, 0xc90f, 0x18ff, 0xc90f, 0x21, 0 - .dw 0x1940, 0xc90f, 0x197f, 0xc90f, 0x21, 0 - .dw 0x19c0, 0xc90f, 0x1fff, 0xc90f, 0x21, 0 - .dw 0x2040, 0xc90f, 0x207f, 0xc90f, 0x21, 0 - .dw 0x20c0, 0xc90f, 0x20ff, 0xc90f, 0x21, 0 - .dw 0x2140, 0xc90f, 0x217f, 0xc90f, 0x21, 0 - .dw 0x21c0, 0xc90f, 0x21ff, 0xc90f, 0x21, 0 - .dw 0x2240, 0xc90f, 0x227f, 0xc90f, 0x21, 0 - .dw 0x22c0, 0xc90f, 0x22ff, 0xc90f, 0x21, 0 - .dw 0x2340, 0xc90f, 0x237f, 0xc90f, 0x21, 0 - .dw 0x23c0, 0xc90f, 0x23ff, 0xc90f, 0x21, 0 - .dw 0x2440, 0xc90f, 0x247f, 0xc90f, 0x21, 0 - .dw 0x24c0, 0xc90f, 0x24ff, 0xc90f, 0x21, 0 - .dw 0x2540, 0xc90f, 0x257f, 0xc90f, 0x21, 0 - .dw 0x25c0, 0xc90f, 0x25ff, 0xc90f, 0x21, 0 - .dw 0x2640, 0xc90f, 0x267f, 0xc90f, 0x21, 0 - .dw 0x26c0, 0xc90f, 0x26ff, 0xc90f, 0x21, 0 - .dw 0x2740, 0xc90f, 0x277f, 0xc90f, 0x21, 0 - .dw 0x27c0, 0xc90f, 0x27ff, 0xc90f, 0x21, 0 - .dw 0x2840, 0xc90f, 0x287f, 0xc90f, 0x21, 0 - .dw 0x28c0, 0xc90f, 0x28ff, 0xc90f, 0x21, 0 - .dw 0x2940, 0xc90f, 0x297f, 0xc90f, 0x21, 0 - .dw 0x29c0, 0xc90f, 0x29ff, 0xc90f, 0x21, 0 - .dw 0x2a40, 0xc90f, 0x2a7f, 0xc90f, 0x21, 0 - .dw 0x2ac0, 0xc90f, 0x2aff, 0xc90f, 0x21, 0 - .dw 0x2b40, 0xc90f, 0x2b7f, 0xc90f, 0x21, 0 - .dw 0x2bc0, 0xc90f, 0x2bff, 0xc90f, 0x21, 0 - .dw 0x2c40, 0xc90f, 0x2c7f, 0xc90f, 0x21, 0 - .dw 0x2cc0, 0xc90f, 0x2cff, 0xc90f, 0x21, 0 - .dw 0x2d40, 0xc90f, 0x2d7f, 0xc90f, 0x21, 0 - .dw 0x2dc0, 0xc90f, 0x2dff, 0xc90f, 0x21, 0 - .dw 0x2e40, 0xc90f, 0x2e7f, 0xc90f, 0x21, 0 - .dw 0x2ec0, 0xc90f, 0x2eff, 0xc90f, 0x21, 0 - .dw 0x2f40, 0xc90f, 0x2f7f, 0xc90f, 0x21, 0 - .dw 0x2fc0, 0xc90f, 0x2fff, 0xc90f, 0x21, 0 - .dw 0x3040, 0xc90f, 0x307f, 0xc90f, 0x21, 0 - .dw 0x30c0, 0xc90f, 0x30ff, 0xc90f, 0x21, 0 - .dw 0x3140, 0xc90f, 0x317f, 0xc90f, 0x21, 0 - .dw 0x31c0, 0xc90f, 0x31ff, 0xc90f, 0x21, 0 - .dw 0x3240, 0xc90f, 0x327f, 0xc90f, 0x21, 0 - .dw 0x32c0, 0xc90f, 0x32ff, 0xc90f, 0x21, 0 - .dw 0x3340, 0xc90f, 0x337f, 0xc90f, 0x21, 0 - .dw 0x33c0, 0xc90f, 0x33ff, 0xc90f, 0x21, 0 - .dw 0x3440, 0xc90f, 0x347f, 0xc90f, 0x21, 0 - .dw 0x34c0, 0xc90f, 0x34ff, 0xc90f, 0x21, 0 - .dw 0x3540, 0xc90f, 0x357f, 0xc90f, 0x21, 0 - .dw 0x35c0, 0xc90f, 0x35ff, 0xc90f, 0x21, 0 - .dw 0x3640, 0xc90f, 0x367f, 0xc90f, 0x21, 0 - .dw 0x36c0, 0xc90f, 0x36ff, 0xc90f, 0x21, 0 - .dw 0x3740, 0xc90f, 0x377f, 0xc90f, 0x21, 0 - .dw 0x37c0, 0xc90f, 0x37ff, 0xc90f, 0x21, 0 - .dw 0x3840, 0xc90f, 0x387f, 0xc90f, 0x21, 0 - .dw 0x38c0, 0xc90f, 0x38ff, 0xc90f, 0x21, 0 - .dw 0x3940, 0xc90f, 0x397f, 0xc90f, 0x21, 0 - .dw 0x39c0, 0xc90f, 0xffff, 0xc90f, 0x21, 0 - .dw 0x1a00, 0xc910, 0x1fff, 0xc910, 0x21, 0 - .dw 0x3a00, 0xc910, 0x3fff, 0xc910, 0x21, 0 - .dw 0x5a00, 0xc910, 0x5fff, 0xc910, 0x21, 0 - .dw 0x7a00, 0xc910, 0x7fff, 0xc910, 0x21, 0 - .dw 0x9a00, 0xc910, 0x9fff, 0xc910, 0x21, 0 - .dw 0xba00, 0xc910, 0xbfff, 0xc910, 0x21, 0 - .dw 0xda00, 0xc910, 0xdfff, 0xc910, 0x21, 0 - .dw 0xfa00, 0xc910, 0xffff, 0xc910, 0x21, 0 - .dw 0x1a00, 0xc911, 0x1fff, 0xc911, 0x21, 0 - .dw 0x3a00, 0xc911, 0x3fff, 0xc911, 0x21, 0 - .dw 0x5a00, 0xc911, 0x5fff, 0xc911, 0x21, 0 - .dw 0x7a00, 0xc911, 0x7fff, 0xc911, 0x21, 0 - .dw 0x9a00, 0xc911, 0x9fff, 0xc911, 0x21, 0 - .dw 0xba00, 0xc911, 0xbfff, 0xc911, 0x21, 0 - .dw 0xda00, 0xc911, 0xdfff, 0xc911, 0x21, 0 - .dw 0xfa00, 0xc911, 0xffff, 0xc911, 0x21, 0 - .dw 0x1a00, 0xc912, 0x1fff, 0xc912, 0x21, 0 - .dw 0x3a00, 0xc912, 0x3fff, 0xc912, 0x21, 0 - .dw 0x5a00, 0xc912, 0x5fff, 0xc912, 0x21, 0 - .dw 0x7a00, 0xc912, 0x7fff, 0xc912, 0x21, 0 - .dw 0x9a00, 0xc912, 0x9fff, 0xc912, 0x21, 0 - .dw 0xba00, 0xc912, 0xbfff, 0xc912, 0x21, 0 - .dw 0xda00, 0xc912, 0xdfff, 0xc912, 0x21, 0 - .dw 0xfa00, 0xc912, 0xffff, 0xc913, 0x21, 0 - .dw 0x1a00, 0xc914, 0x1fff, 0xc914, 0x21, 0 - .dw 0x3a00, 0xc914, 0x3fff, 0xc914, 0x21, 0 - .dw 0x5a00, 0xc914, 0x5fff, 0xc914, 0x21, 0 - .dw 0x7a00, 0xc914, 0x7fff, 0xc914, 0x21, 0 - .dw 0x9a00, 0xc914, 0x9fff, 0xc914, 0x21, 0 - .dw 0xba00, 0xc914, 0xbfff, 0xc914, 0x21, 0 - .dw 0xda00, 0xc914, 0xdfff, 0xc914, 0x21, 0 - .dw 0xfa00, 0xc914, 0xffff, 0xc914, 0x21, 0 - .dw 0x1a00, 0xc915, 0x1fff, 0xc915, 0x21, 0 - .dw 0x3a00, 0xc915, 0x3fff, 0xc915, 0x21, 0 - .dw 0x5a00, 0xc915, 0x5fff, 0xc915, 0x21, 0 - .dw 0x7a00, 0xc915, 0x7fff, 0xc915, 0x21, 0 - .dw 0x9a00, 0xc915, 0x9fff, 0xc915, 0x21, 0 - .dw 0xba00, 0xc915, 0xbfff, 0xc915, 0x21, 0 - .dw 0xda00, 0xc915, 0xdfff, 0xc915, 0x21, 0 - .dw 0xfa00, 0xc915, 0xffff, 0xc915, 0x21, 0 - .dw 0x1a00, 0xc916, 0x1fff, 0xc916, 0x21, 0 - .dw 0x3a00, 0xc916, 0x3fff, 0xc916, 0x21, 0 - .dw 0x5a00, 0xc916, 0x5fff, 0xc916, 0x21, 0 - .dw 0x7a00, 0xc916, 0x7fff, 0xc916, 0x21, 0 - .dw 0x9a00, 0xc916, 0x9fff, 0xc916, 0x21, 0 - .dw 0xba00, 0xc916, 0xbfff, 0xc916, 0x21, 0 - .dw 0xda00, 0xc916, 0xdfff, 0xc916, 0x21, 0 - .dw 0xfa00, 0xc916, 0xffff, 0xc916, 0x21, 0 - .dw 0x1a00, 0xc917, 0x1fff, 0xc917, 0x21, 0 - .dw 0x3a00, 0xc917, 0x1fff, 0xc918, 0x21, 0 - .dw 0x2040, 0xc918, 0x207f, 0xc918, 0x21, 0 - .dw 0x20c0, 0xc918, 0x20ff, 0xc918, 0x21, 0 - .dw 0x2140, 0xc918, 0x217f, 0xc918, 0x21, 0 - .dw 0x21c0, 0xc918, 0x21ff, 0xc918, 0x21, 0 - .dw 0x2240, 0xc918, 0x227f, 0xc918, 0x21, 0 - .dw 0x22c0, 0xc918, 0x22ff, 0xc918, 0x21, 0 - .dw 0x2340, 0xc918, 0x237f, 0xc918, 0x21, 0 - .dw 0x23c0, 0xc918, 0x23ff, 0xc918, 0x21, 0 - .dw 0x2440, 0xc918, 0x247f, 0xc918, 0x21, 0 - .dw 0x24c0, 0xc918, 0x24ff, 0xc918, 0x21, 0 - .dw 0x2540, 0xc918, 0x257f, 0xc918, 0x21, 0 - .dw 0x25c0, 0xc918, 0x25ff, 0xc918, 0x21, 0 - .dw 0x2640, 0xc918, 0x267f, 0xc918, 0x21, 0 - .dw 0x26c0, 0xc918, 0x26ff, 0xc918, 0x21, 0 - .dw 0x2740, 0xc918, 0x277f, 0xc918, 0x21, 0 - .dw 0x27c0, 0xc918, 0x27ff, 0xc918, 0x21, 0 - .dw 0x2840, 0xc918, 0x287f, 0xc918, 0x21, 0 - .dw 0x28c0, 0xc918, 0x28ff, 0xc918, 0x21, 0 - .dw 0x2940, 0xc918, 0x297f, 0xc918, 0x21, 0 - .dw 0x29c0, 0xc918, 0x29ff, 0xc918, 0x21, 0 - .dw 0x2a40, 0xc918, 0x2a7f, 0xc918, 0x21, 0 - .dw 0x2ac0, 0xc918, 0x2aff, 0xc918, 0x21, 0 - .dw 0x2b40, 0xc918, 0x2b7f, 0xc918, 0x21, 0 - .dw 0x2bc0, 0xc918, 0x2bff, 0xc918, 0x21, 0 - .dw 0x2c40, 0xc918, 0x2c7f, 0xc918, 0x21, 0 - .dw 0x2cc0, 0xc918, 0x2cff, 0xc918, 0x21, 0 - .dw 0x2d40, 0xc918, 0x2d7f, 0xc918, 0x21, 0 - .dw 0x2dc0, 0xc918, 0x2dff, 0xc918, 0x21, 0 - .dw 0x2e40, 0xc918, 0x2e7f, 0xc918, 0x21, 0 - .dw 0x2ec0, 0xc918, 0x2eff, 0xc918, 0x21, 0 - .dw 0x2f40, 0xc918, 0x2f7f, 0xc918, 0x21, 0 - .dw 0x2fc0, 0xc918, 0x2fff, 0xc918, 0x21, 0 - .dw 0x3040, 0xc918, 0x307f, 0xc918, 0x21, 0 - .dw 0x30c0, 0xc918, 0x30ff, 0xc918, 0x21, 0 - .dw 0x3140, 0xc918, 0x317f, 0xc918, 0x21, 0 - .dw 0x31c0, 0xc918, 0x31ff, 0xc918, 0x21, 0 - .dw 0x3240, 0xc918, 0x327f, 0xc918, 0x21, 0 - .dw 0x32c0, 0xc918, 0x32ff, 0xc918, 0x21, 0 - .dw 0x3340, 0xc918, 0x337f, 0xc918, 0x21, 0 - .dw 0x33c0, 0xc918, 0x33ff, 0xc918, 0x21, 0 - .dw 0x3440, 0xc918, 0x347f, 0xc918, 0x21, 0 - .dw 0x34c0, 0xc918, 0x34ff, 0xc918, 0x21, 0 - .dw 0x3540, 0xc918, 0x357f, 0xc918, 0x21, 0 - .dw 0x35c0, 0xc918, 0x35ff, 0xc918, 0x21, 0 - .dw 0x3640, 0xc918, 0x367f, 0xc918, 0x21, 0 - .dw 0x36c0, 0xc918, 0x36ff, 0xc918, 0x21, 0 - .dw 0x3740, 0xc918, 0x377f, 0xc918, 0x21, 0 - .dw 0x37c0, 0xc918, 0x37ff, 0xc918, 0x21, 0 - .dw 0x3840, 0xc918, 0x387f, 0xc918, 0x21, 0 - .dw 0x38c0, 0xc918, 0x38ff, 0xc918, 0x21, 0 - .dw 0x3940, 0xc918, 0x397f, 0xc918, 0x21, 0 - .dw 0x39c0, 0xc918, 0x5fff, 0xc918, 0x21, 0 - .dw 0x6040, 0xc918, 0x607f, 0xc918, 0x21, 0 - .dw 0x60c0, 0xc918, 0x60ff, 0xc918, 0x21, 0 - .dw 0x6140, 0xc918, 0x617f, 0xc918, 0x21, 0 - .dw 0x61c0, 0xc918, 0x61ff, 0xc918, 0x21, 0 - .dw 0x6240, 0xc918, 0x627f, 0xc918, 0x21, 0 - .dw 0x62c0, 0xc918, 0x62ff, 0xc918, 0x21, 0 - .dw 0x6340, 0xc918, 0x637f, 0xc918, 0x21, 0 - .dw 0x63c0, 0xc918, 0x63ff, 0xc918, 0x21, 0 - .dw 0x6440, 0xc918, 0x647f, 0xc918, 0x21, 0 - .dw 0x64c0, 0xc918, 0x64ff, 0xc918, 0x21, 0 - .dw 0x6540, 0xc918, 0x657f, 0xc918, 0x21, 0 - .dw 0x65c0, 0xc918, 0x65ff, 0xc918, 0x21, 0 - .dw 0x6640, 0xc918, 0x667f, 0xc918, 0x21, 0 - .dw 0x66c0, 0xc918, 0x66ff, 0xc918, 0x21, 0 - .dw 0x6740, 0xc918, 0x677f, 0xc918, 0x21, 0 - .dw 0x67c0, 0xc918, 0x67ff, 0xc918, 0x21, 0 - .dw 0x6840, 0xc918, 0x687f, 0xc918, 0x21, 0 - .dw 0x68c0, 0xc918, 0x68ff, 0xc918, 0x21, 0 - .dw 0x6940, 0xc918, 0x697f, 0xc918, 0x21, 0 - .dw 0x69c0, 0xc918, 0x69ff, 0xc918, 0x21, 0 - .dw 0x6a40, 0xc918, 0x6a7f, 0xc918, 0x21, 0 - .dw 0x6ac0, 0xc918, 0x6aff, 0xc918, 0x21, 0 - .dw 0x6b40, 0xc918, 0x6b7f, 0xc918, 0x21, 0 - .dw 0x6bc0, 0xc918, 0x6bff, 0xc918, 0x21, 0 - .dw 0x6c40, 0xc918, 0x6c7f, 0xc918, 0x21, 0 - .dw 0x6cc0, 0xc918, 0x6cff, 0xc918, 0x21, 0 - .dw 0x6d40, 0xc918, 0x6d7f, 0xc918, 0x21, 0 - .dw 0x6dc0, 0xc918, 0x6dff, 0xc918, 0x21, 0 - .dw 0x6e40, 0xc918, 0x6e7f, 0xc918, 0x21, 0 - .dw 0x6ec0, 0xc918, 0x6eff, 0xc918, 0x21, 0 - .dw 0x6f40, 0xc918, 0x6f7f, 0xc918, 0x21, 0 - .dw 0x6fc0, 0xc918, 0x6fff, 0xc918, 0x21, 0 - .dw 0x7040, 0xc918, 0x707f, 0xc918, 0x21, 0 - .dw 0x70c0, 0xc918, 0x70ff, 0xc918, 0x21, 0 - .dw 0x7140, 0xc918, 0x717f, 0xc918, 0x21, 0 - .dw 0x71c0, 0xc918, 0x71ff, 0xc918, 0x21, 0 - .dw 0x7240, 0xc918, 0x727f, 0xc918, 0x21, 0 - .dw 0x72c0, 0xc918, 0x72ff, 0xc918, 0x21, 0 - .dw 0x7340, 0xc918, 0x737f, 0xc918, 0x21, 0 - .dw 0x73c0, 0xc918, 0x73ff, 0xc918, 0x21, 0 - .dw 0x7440, 0xc918, 0x747f, 0xc918, 0x21, 0 - .dw 0x74c0, 0xc918, 0x74ff, 0xc918, 0x21, 0 - .dw 0x7540, 0xc918, 0x757f, 0xc918, 0x21, 0 - .dw 0x75c0, 0xc918, 0x75ff, 0xc918, 0x21, 0 - .dw 0x7640, 0xc918, 0x767f, 0xc918, 0x21, 0 - .dw 0x76c0, 0xc918, 0x76ff, 0xc918, 0x21, 0 - .dw 0x7740, 0xc918, 0x777f, 0xc918, 0x21, 0 - .dw 0x77c0, 0xc918, 0x77ff, 0xc918, 0x21, 0 - .dw 0x7840, 0xc918, 0x787f, 0xc918, 0x21, 0 - .dw 0x78c0, 0xc918, 0x78ff, 0xc918, 0x21, 0 - .dw 0x7940, 0xc918, 0x797f, 0xc918, 0x21, 0 - .dw 0x79c0, 0xc918, 0x9fff, 0xc918, 0x21, 0 - .dw 0xa040, 0xc918, 0xa07f, 0xc918, 0x21, 0 - .dw 0xa0c0, 0xc918, 0xa0ff, 0xc918, 0x21, 0 - .dw 0xa140, 0xc918, 0xa17f, 0xc918, 0x21, 0 - .dw 0xa1c0, 0xc918, 0xa1ff, 0xc918, 0x21, 0 - .dw 0xa240, 0xc918, 0xa27f, 0xc918, 0x21, 0 - .dw 0xa2c0, 0xc918, 0xa2ff, 0xc918, 0x21, 0 - .dw 0xa340, 0xc918, 0xa37f, 0xc918, 0x21, 0 - .dw 0xa3c0, 0xc918, 0xa3ff, 0xc918, 0x21, 0 - .dw 0xa440, 0xc918, 0xa47f, 0xc918, 0x21, 0 - .dw 0xa4c0, 0xc918, 0xa4ff, 0xc918, 0x21, 0 - .dw 0xa540, 0xc918, 0xa57f, 0xc918, 0x21, 0 - .dw 0xa5c0, 0xc918, 0xa5ff, 0xc918, 0x21, 0 - .dw 0xa640, 0xc918, 0xa67f, 0xc918, 0x21, 0 - .dw 0xa6c0, 0xc918, 0xa6ff, 0xc918, 0x21, 0 - .dw 0xa740, 0xc918, 0xa77f, 0xc918, 0x21, 0 - .dw 0xa7c0, 0xc918, 0xa7ff, 0xc918, 0x21, 0 - .dw 0xa840, 0xc918, 0xa87f, 0xc918, 0x21, 0 - .dw 0xa8c0, 0xc918, 0xa8ff, 0xc918, 0x21, 0 - .dw 0xa940, 0xc918, 0xa97f, 0xc918, 0x21, 0 - .dw 0xa9c0, 0xc918, 0xa9ff, 0xc918, 0x21, 0 - .dw 0xaa40, 0xc918, 0xaa7f, 0xc918, 0x21, 0 - .dw 0xaac0, 0xc918, 0xaaff, 0xc918, 0x21, 0 - .dw 0xab40, 0xc918, 0xab7f, 0xc918, 0x21, 0 - .dw 0xabc0, 0xc918, 0xabff, 0xc918, 0x21, 0 - .dw 0xac40, 0xc918, 0xac7f, 0xc918, 0x21, 0 - .dw 0xacc0, 0xc918, 0xacff, 0xc918, 0x21, 0 - .dw 0xad40, 0xc918, 0xad7f, 0xc918, 0x21, 0 - .dw 0xadc0, 0xc918, 0xadff, 0xc918, 0x21, 0 - .dw 0xae40, 0xc918, 0xae7f, 0xc918, 0x21, 0 - .dw 0xaec0, 0xc918, 0xaeff, 0xc918, 0x21, 0 - .dw 0xaf40, 0xc918, 0xaf7f, 0xc918, 0x21, 0 - .dw 0xafc0, 0xc918, 0xafff, 0xc918, 0x21, 0 - .dw 0xb040, 0xc918, 0xb07f, 0xc918, 0x21, 0 - .dw 0xb0c0, 0xc918, 0xb0ff, 0xc918, 0x21, 0 - .dw 0xb140, 0xc918, 0xb17f, 0xc918, 0x21, 0 - .dw 0xb1c0, 0xc918, 0xb1ff, 0xc918, 0x21, 0 - .dw 0xb240, 0xc918, 0xb27f, 0xc918, 0x21, 0 - .dw 0xb2c0, 0xc918, 0xb2ff, 0xc918, 0x21, 0 - .dw 0xb340, 0xc918, 0xb37f, 0xc918, 0x21, 0 - .dw 0xb3c0, 0xc918, 0xb3ff, 0xc918, 0x21, 0 - .dw 0xb440, 0xc918, 0xb47f, 0xc918, 0x21, 0 - .dw 0xb4c0, 0xc918, 0xb4ff, 0xc918, 0x21, 0 - .dw 0xb540, 0xc918, 0xb57f, 0xc918, 0x21, 0 - .dw 0xb5c0, 0xc918, 0xb5ff, 0xc918, 0x21, 0 - .dw 0xb640, 0xc918, 0xb67f, 0xc918, 0x21, 0 - .dw 0xb6c0, 0xc918, 0xb6ff, 0xc918, 0x21, 0 - .dw 0xb740, 0xc918, 0xb77f, 0xc918, 0x21, 0 - .dw 0xb7c0, 0xc918, 0xb7ff, 0xc918, 0x21, 0 - .dw 0xb840, 0xc918, 0xb87f, 0xc918, 0x21, 0 - .dw 0xb8c0, 0xc918, 0xb8ff, 0xc918, 0x21, 0 - .dw 0xb940, 0xc918, 0xb97f, 0xc918, 0x21, 0 - .dw 0xb9c0, 0xc918, 0xdfff, 0xc918, 0x21, 0 - .dw 0xe040, 0xc918, 0xe07f, 0xc918, 0x21, 0 - .dw 0xe0c0, 0xc918, 0xe0ff, 0xc918, 0x21, 0 - .dw 0xe140, 0xc918, 0xe17f, 0xc918, 0x21, 0 - .dw 0xe1c0, 0xc918, 0xe1ff, 0xc918, 0x21, 0 - .dw 0xe240, 0xc918, 0xe27f, 0xc918, 0x21, 0 - .dw 0xe2c0, 0xc918, 0xe2ff, 0xc918, 0x21, 0 - .dw 0xe340, 0xc918, 0xe37f, 0xc918, 0x21, 0 - .dw 0xe3c0, 0xc918, 0xe3ff, 0xc918, 0x21, 0 - .dw 0xe440, 0xc918, 0xe47f, 0xc918, 0x21, 0 - .dw 0xe4c0, 0xc918, 0xe4ff, 0xc918, 0x21, 0 - .dw 0xe540, 0xc918, 0xe57f, 0xc918, 0x21, 0 - .dw 0xe5c0, 0xc918, 0xe5ff, 0xc918, 0x21, 0 - .dw 0xe640, 0xc918, 0xe67f, 0xc918, 0x21, 0 - .dw 0xe6c0, 0xc918, 0xe6ff, 0xc918, 0x21, 0 - .dw 0xe740, 0xc918, 0xe77f, 0xc918, 0x21, 0 - .dw 0xe7c0, 0xc918, 0xe7ff, 0xc918, 0x21, 0 - .dw 0xe840, 0xc918, 0xe87f, 0xc918, 0x21, 0 - .dw 0xe8c0, 0xc918, 0xe8ff, 0xc918, 0x21, 0 - .dw 0xe940, 0xc918, 0xe97f, 0xc918, 0x21, 0 - .dw 0xe9c0, 0xc918, 0xe9ff, 0xc918, 0x21, 0 - .dw 0xea40, 0xc918, 0xea7f, 0xc918, 0x21, 0 - .dw 0xeac0, 0xc918, 0xeaff, 0xc918, 0x21, 0 - .dw 0xeb40, 0xc918, 0xeb7f, 0xc918, 0x21, 0 - .dw 0xebc0, 0xc918, 0xebff, 0xc918, 0x21, 0 - .dw 0xec40, 0xc918, 0xec7f, 0xc918, 0x21, 0 - .dw 0xecc0, 0xc918, 0xecff, 0xc918, 0x21, 0 - .dw 0xed40, 0xc918, 0xed7f, 0xc918, 0x21, 0 - .dw 0xedc0, 0xc918, 0xedff, 0xc918, 0x21, 0 - .dw 0xee40, 0xc918, 0xee7f, 0xc918, 0x21, 0 - .dw 0xeec0, 0xc918, 0xeeff, 0xc918, 0x21, 0 - .dw 0xef40, 0xc918, 0xef7f, 0xc918, 0x21, 0 - .dw 0xefc0, 0xc918, 0xefff, 0xc918, 0x21, 0 - .dw 0xf040, 0xc918, 0xf07f, 0xc918, 0x21, 0 - .dw 0xf0c0, 0xc918, 0xf0ff, 0xc918, 0x21, 0 - .dw 0xf140, 0xc918, 0xf17f, 0xc918, 0x21, 0 - .dw 0xf1c0, 0xc918, 0xf1ff, 0xc918, 0x21, 0 - .dw 0xf240, 0xc918, 0xf27f, 0xc918, 0x21, 0 - .dw 0xf2c0, 0xc918, 0xf2ff, 0xc918, 0x21, 0 - .dw 0xf340, 0xc918, 0xf37f, 0xc918, 0x21, 0 - .dw 0xf3c0, 0xc918, 0xf3ff, 0xc918, 0x21, 0 - .dw 0xf440, 0xc918, 0xf47f, 0xc918, 0x21, 0 - .dw 0xf4c0, 0xc918, 0xf4ff, 0xc918, 0x21, 0 - .dw 0xf540, 0xc918, 0xf57f, 0xc918, 0x21, 0 - .dw 0xf5c0, 0xc918, 0xf5ff, 0xc918, 0x21, 0 - .dw 0xf640, 0xc918, 0xf67f, 0xc918, 0x21, 0 - .dw 0xf6c0, 0xc918, 0xf6ff, 0xc918, 0x21, 0 - .dw 0xf740, 0xc918, 0xf77f, 0xc918, 0x21, 0 - .dw 0xf7c0, 0xc918, 0xf7ff, 0xc918, 0x21, 0 - .dw 0xf840, 0xc918, 0xf87f, 0xc918, 0x21, 0 - .dw 0xf8c0, 0xc918, 0xf8ff, 0xc918, 0x21, 0 - .dw 0xf940, 0xc918, 0xf97f, 0xc918, 0x21, 0 - .dw 0xf9c0, 0xc918, 0x1fff, 0xc919, 0x21, 0 - .dw 0x2040, 0xc919, 0x207f, 0xc919, 0x21, 0 - .dw 0x20c0, 0xc919, 0x20ff, 0xc919, 0x21, 0 - .dw 0x2140, 0xc919, 0x217f, 0xc919, 0x21, 0 - .dw 0x21c0, 0xc919, 0x21ff, 0xc919, 0x21, 0 - .dw 0x2240, 0xc919, 0x227f, 0xc919, 0x21, 0 - .dw 0x22c0, 0xc919, 0x22ff, 0xc919, 0x21, 0 - .dw 0x2340, 0xc919, 0x237f, 0xc919, 0x21, 0 - .dw 0x23c0, 0xc919, 0x23ff, 0xc919, 0x21, 0 - .dw 0x2440, 0xc919, 0x247f, 0xc919, 0x21, 0 - .dw 0x24c0, 0xc919, 0x24ff, 0xc919, 0x21, 0 - .dw 0x2540, 0xc919, 0x257f, 0xc919, 0x21, 0 - .dw 0x25c0, 0xc919, 0x25ff, 0xc919, 0x21, 0 - .dw 0x2640, 0xc919, 0x267f, 0xc919, 0x21, 0 - .dw 0x26c0, 0xc919, 0x26ff, 0xc919, 0x21, 0 - .dw 0x2740, 0xc919, 0x277f, 0xc919, 0x21, 0 - .dw 0x27c0, 0xc919, 0x27ff, 0xc919, 0x21, 0 - .dw 0x2840, 0xc919, 0x287f, 0xc919, 0x21, 0 - .dw 0x28c0, 0xc919, 0x28ff, 0xc919, 0x21, 0 - .dw 0x2940, 0xc919, 0x297f, 0xc919, 0x21, 0 - .dw 0x29c0, 0xc919, 0x29ff, 0xc919, 0x21, 0 - .dw 0x2a40, 0xc919, 0x2a7f, 0xc919, 0x21, 0 - .dw 0x2ac0, 0xc919, 0x2aff, 0xc919, 0x21, 0 - .dw 0x2b40, 0xc919, 0x2b7f, 0xc919, 0x21, 0 - .dw 0x2bc0, 0xc919, 0x2bff, 0xc919, 0x21, 0 - .dw 0x2c40, 0xc919, 0x2c7f, 0xc919, 0x21, 0 - .dw 0x2cc0, 0xc919, 0x2cff, 0xc919, 0x21, 0 - .dw 0x2d40, 0xc919, 0x2d7f, 0xc919, 0x21, 0 - .dw 0x2dc0, 0xc919, 0x2dff, 0xc919, 0x21, 0 - .dw 0x2e40, 0xc919, 0x2e7f, 0xc919, 0x21, 0 - .dw 0x2ec0, 0xc919, 0x2eff, 0xc919, 0x21, 0 - .dw 0x2f40, 0xc919, 0x2f7f, 0xc919, 0x21, 0 - .dw 0x2fc0, 0xc919, 0x2fff, 0xc919, 0x21, 0 - .dw 0x3040, 0xc919, 0x307f, 0xc919, 0x21, 0 - .dw 0x30c0, 0xc919, 0x30ff, 0xc919, 0x21, 0 - .dw 0x3140, 0xc919, 0x317f, 0xc919, 0x21, 0 - .dw 0x31c0, 0xc919, 0x31ff, 0xc919, 0x21, 0 - .dw 0x3240, 0xc919, 0x327f, 0xc919, 0x21, 0 - .dw 0x32c0, 0xc919, 0x32ff, 0xc919, 0x21, 0 - .dw 0x3340, 0xc919, 0x337f, 0xc919, 0x21, 0 - .dw 0x33c0, 0xc919, 0x33ff, 0xc919, 0x21, 0 - .dw 0x3440, 0xc919, 0x347f, 0xc919, 0x21, 0 - .dw 0x34c0, 0xc919, 0x34ff, 0xc919, 0x21, 0 - .dw 0x3540, 0xc919, 0x357f, 0xc919, 0x21, 0 - .dw 0x35c0, 0xc919, 0x35ff, 0xc919, 0x21, 0 - .dw 0x3640, 0xc919, 0x367f, 0xc919, 0x21, 0 - .dw 0x36c0, 0xc919, 0x36ff, 0xc919, 0x21, 0 - .dw 0x3740, 0xc919, 0x377f, 0xc919, 0x21, 0 - .dw 0x37c0, 0xc919, 0x37ff, 0xc919, 0x21, 0 - .dw 0x3840, 0xc919, 0x387f, 0xc919, 0x21, 0 - .dw 0x38c0, 0xc919, 0x38ff, 0xc919, 0x21, 0 - .dw 0x3940, 0xc919, 0x397f, 0xc919, 0x21, 0 - .dw 0x39c0, 0xc919, 0x5fff, 0xc919, 0x21, 0 - .dw 0x6040, 0xc919, 0x607f, 0xc919, 0x21, 0 - .dw 0x60c0, 0xc919, 0x60ff, 0xc919, 0x21, 0 - .dw 0x6140, 0xc919, 0x617f, 0xc919, 0x21, 0 - .dw 0x61c0, 0xc919, 0x61ff, 0xc919, 0x21, 0 - .dw 0x6240, 0xc919, 0x627f, 0xc919, 0x21, 0 - .dw 0x62c0, 0xc919, 0x62ff, 0xc919, 0x21, 0 - .dw 0x6340, 0xc919, 0x637f, 0xc919, 0x21, 0 - .dw 0x63c0, 0xc919, 0x63ff, 0xc919, 0x21, 0 - .dw 0x6440, 0xc919, 0x647f, 0xc919, 0x21, 0 - .dw 0x64c0, 0xc919, 0x64ff, 0xc919, 0x21, 0 - .dw 0x6540, 0xc919, 0x657f, 0xc919, 0x21, 0 - .dw 0x65c0, 0xc919, 0x65ff, 0xc919, 0x21, 0 - .dw 0x6640, 0xc919, 0x667f, 0xc919, 0x21, 0 - .dw 0x66c0, 0xc919, 0x66ff, 0xc919, 0x21, 0 - .dw 0x6740, 0xc919, 0x677f, 0xc919, 0x21, 0 - .dw 0x67c0, 0xc919, 0x67ff, 0xc919, 0x21, 0 - .dw 0x6840, 0xc919, 0x687f, 0xc919, 0x21, 0 - .dw 0x68c0, 0xc919, 0x68ff, 0xc919, 0x21, 0 - .dw 0x6940, 0xc919, 0x697f, 0xc919, 0x21, 0 - .dw 0x69c0, 0xc919, 0x69ff, 0xc919, 0x21, 0 - .dw 0x6a40, 0xc919, 0x6a7f, 0xc919, 0x21, 0 - .dw 0x6ac0, 0xc919, 0x6aff, 0xc919, 0x21, 0 - .dw 0x6b40, 0xc919, 0x6b7f, 0xc919, 0x21, 0 - .dw 0x6bc0, 0xc919, 0x6bff, 0xc919, 0x21, 0 - .dw 0x6c40, 0xc919, 0x6c7f, 0xc919, 0x21, 0 - .dw 0x6cc0, 0xc919, 0x6cff, 0xc919, 0x21, 0 - .dw 0x6d40, 0xc919, 0x6d7f, 0xc919, 0x21, 0 - .dw 0x6dc0, 0xc919, 0x6dff, 0xc919, 0x21, 0 - .dw 0x6e40, 0xc919, 0x6e7f, 0xc919, 0x21, 0 - .dw 0x6ec0, 0xc919, 0x6eff, 0xc919, 0x21, 0 - .dw 0x6f40, 0xc919, 0x6f7f, 0xc919, 0x21, 0 - .dw 0x6fc0, 0xc919, 0x6fff, 0xc919, 0x21, 0 - .dw 0x7040, 0xc919, 0x707f, 0xc919, 0x21, 0 - .dw 0x70c0, 0xc919, 0x70ff, 0xc919, 0x21, 0 - .dw 0x7140, 0xc919, 0x717f, 0xc919, 0x21, 0 - .dw 0x71c0, 0xc919, 0x71ff, 0xc919, 0x21, 0 - .dw 0x7240, 0xc919, 0x727f, 0xc919, 0x21, 0 - .dw 0x72c0, 0xc919, 0x72ff, 0xc919, 0x21, 0 - .dw 0x7340, 0xc919, 0x737f, 0xc919, 0x21, 0 - .dw 0x73c0, 0xc919, 0x73ff, 0xc919, 0x21, 0 - .dw 0x7440, 0xc919, 0x747f, 0xc919, 0x21, 0 - .dw 0x74c0, 0xc919, 0x74ff, 0xc919, 0x21, 0 - .dw 0x7540, 0xc919, 0x757f, 0xc919, 0x21, 0 - .dw 0x75c0, 0xc919, 0x75ff, 0xc919, 0x21, 0 - .dw 0x7640, 0xc919, 0x767f, 0xc919, 0x21, 0 - .dw 0x76c0, 0xc919, 0x76ff, 0xc919, 0x21, 0 - .dw 0x7740, 0xc919, 0x777f, 0xc919, 0x21, 0 - .dw 0x77c0, 0xc919, 0x77ff, 0xc919, 0x21, 0 - .dw 0x7840, 0xc919, 0x787f, 0xc919, 0x21, 0 - .dw 0x78c0, 0xc919, 0x78ff, 0xc919, 0x21, 0 - .dw 0x7940, 0xc919, 0x797f, 0xc919, 0x21, 0 - .dw 0x79c0, 0xc919, 0x9fff, 0xc919, 0x21, 0 - .dw 0xa040, 0xc919, 0xa07f, 0xc919, 0x21, 0 - .dw 0xa0c0, 0xc919, 0xa0ff, 0xc919, 0x21, 0 - .dw 0xa140, 0xc919, 0xa17f, 0xc919, 0x21, 0 - .dw 0xa1c0, 0xc919, 0xa1ff, 0xc919, 0x21, 0 - .dw 0xa240, 0xc919, 0xa27f, 0xc919, 0x21, 0 - .dw 0xa2c0, 0xc919, 0xa2ff, 0xc919, 0x21, 0 - .dw 0xa340, 0xc919, 0xa37f, 0xc919, 0x21, 0 - .dw 0xa3c0, 0xc919, 0xa3ff, 0xc919, 0x21, 0 - .dw 0xa440, 0xc919, 0xa47f, 0xc919, 0x21, 0 - .dw 0xa4c0, 0xc919, 0xa4ff, 0xc919, 0x21, 0 - .dw 0xa540, 0xc919, 0xa57f, 0xc919, 0x21, 0 - .dw 0xa5c0, 0xc919, 0xa5ff, 0xc919, 0x21, 0 - .dw 0xa640, 0xc919, 0xa67f, 0xc919, 0x21, 0 - .dw 0xa6c0, 0xc919, 0xa6ff, 0xc919, 0x21, 0 - .dw 0xa740, 0xc919, 0xa77f, 0xc919, 0x21, 0 - .dw 0xa7c0, 0xc919, 0xa7ff, 0xc919, 0x21, 0 - .dw 0xa840, 0xc919, 0xa87f, 0xc919, 0x21, 0 - .dw 0xa8c0, 0xc919, 0xa8ff, 0xc919, 0x21, 0 - .dw 0xa940, 0xc919, 0xa97f, 0xc919, 0x21, 0 - .dw 0xa9c0, 0xc919, 0xa9ff, 0xc919, 0x21, 0 - .dw 0xaa40, 0xc919, 0xaa7f, 0xc919, 0x21, 0 - .dw 0xaac0, 0xc919, 0xaaff, 0xc919, 0x21, 0 - .dw 0xab40, 0xc919, 0xab7f, 0xc919, 0x21, 0 - .dw 0xabc0, 0xc919, 0xabff, 0xc919, 0x21, 0 - .dw 0xac40, 0xc919, 0xac7f, 0xc919, 0x21, 0 - .dw 0xacc0, 0xc919, 0xacff, 0xc919, 0x21, 0 - .dw 0xad40, 0xc919, 0xad7f, 0xc919, 0x21, 0 - .dw 0xadc0, 0xc919, 0xadff, 0xc919, 0x21, 0 - .dw 0xae40, 0xc919, 0xae7f, 0xc919, 0x21, 0 - .dw 0xaec0, 0xc919, 0xaeff, 0xc919, 0x21, 0 - .dw 0xaf40, 0xc919, 0xaf7f, 0xc919, 0x21, 0 - .dw 0xafc0, 0xc919, 0xafff, 0xc919, 0x21, 0 - .dw 0xb040, 0xc919, 0xb07f, 0xc919, 0x21, 0 - .dw 0xb0c0, 0xc919, 0xb0ff, 0xc919, 0x21, 0 - .dw 0xb140, 0xc919, 0xb17f, 0xc919, 0x21, 0 - .dw 0xb1c0, 0xc919, 0xb1ff, 0xc919, 0x21, 0 - .dw 0xb240, 0xc919, 0xb27f, 0xc919, 0x21, 0 - .dw 0xb2c0, 0xc919, 0xb2ff, 0xc919, 0x21, 0 - .dw 0xb340, 0xc919, 0xb37f, 0xc919, 0x21, 0 - .dw 0xb3c0, 0xc919, 0xb3ff, 0xc919, 0x21, 0 - .dw 0xb440, 0xc919, 0xb47f, 0xc919, 0x21, 0 - .dw 0xb4c0, 0xc919, 0xb4ff, 0xc919, 0x21, 0 - .dw 0xb540, 0xc919, 0xb57f, 0xc919, 0x21, 0 - .dw 0xb5c0, 0xc919, 0xb5ff, 0xc919, 0x21, 0 - .dw 0xb640, 0xc919, 0xb67f, 0xc919, 0x21, 0 - .dw 0xb6c0, 0xc919, 0xb6ff, 0xc919, 0x21, 0 - .dw 0xb740, 0xc919, 0xb77f, 0xc919, 0x21, 0 - .dw 0xb7c0, 0xc919, 0xb7ff, 0xc919, 0x21, 0 - .dw 0xb840, 0xc919, 0xb87f, 0xc919, 0x21, 0 - .dw 0xb8c0, 0xc919, 0xb8ff, 0xc919, 0x21, 0 - .dw 0xb940, 0xc919, 0xb97f, 0xc919, 0x21, 0 - .dw 0xb9c0, 0xc919, 0xdfff, 0xc919, 0x21, 0 - .dw 0xe040, 0xc919, 0xe07f, 0xc919, 0x21, 0 - .dw 0xe0c0, 0xc919, 0xe0ff, 0xc919, 0x21, 0 - .dw 0xe140, 0xc919, 0xe17f, 0xc919, 0x21, 0 - .dw 0xe1c0, 0xc919, 0xe1ff, 0xc919, 0x21, 0 - .dw 0xe240, 0xc919, 0xe27f, 0xc919, 0x21, 0 - .dw 0xe2c0, 0xc919, 0xe2ff, 0xc919, 0x21, 0 - .dw 0xe340, 0xc919, 0xe37f, 0xc919, 0x21, 0 - .dw 0xe3c0, 0xc919, 0xe3ff, 0xc919, 0x21, 0 - .dw 0xe440, 0xc919, 0xe47f, 0xc919, 0x21, 0 - .dw 0xe4c0, 0xc919, 0xe4ff, 0xc919, 0x21, 0 - .dw 0xe540, 0xc919, 0xe57f, 0xc919, 0x21, 0 - .dw 0xe5c0, 0xc919, 0xe5ff, 0xc919, 0x21, 0 - .dw 0xe640, 0xc919, 0xe67f, 0xc919, 0x21, 0 - .dw 0xe6c0, 0xc919, 0xe6ff, 0xc919, 0x21, 0 - .dw 0xe740, 0xc919, 0xe77f, 0xc919, 0x21, 0 - .dw 0xe7c0, 0xc919, 0xe7ff, 0xc919, 0x21, 0 - .dw 0xe840, 0xc919, 0xe87f, 0xc919, 0x21, 0 - .dw 0xe8c0, 0xc919, 0xe8ff, 0xc919, 0x21, 0 - .dw 0xe940, 0xc919, 0xe97f, 0xc919, 0x21, 0 - .dw 0xe9c0, 0xc919, 0xe9ff, 0xc919, 0x21, 0 - .dw 0xea40, 0xc919, 0xea7f, 0xc919, 0x21, 0 - .dw 0xeac0, 0xc919, 0xeaff, 0xc919, 0x21, 0 - .dw 0xeb40, 0xc919, 0xeb7f, 0xc919, 0x21, 0 - .dw 0xebc0, 0xc919, 0xebff, 0xc919, 0x21, 0 - .dw 0xec40, 0xc919, 0xec7f, 0xc919, 0x21, 0 - .dw 0xecc0, 0xc919, 0xecff, 0xc919, 0x21, 0 - .dw 0xed40, 0xc919, 0xed7f, 0xc919, 0x21, 0 - .dw 0xedc0, 0xc919, 0xedff, 0xc919, 0x21, 0 - .dw 0xee40, 0xc919, 0xee7f, 0xc919, 0x21, 0 - .dw 0xeec0, 0xc919, 0xeeff, 0xc919, 0x21, 0 - .dw 0xef40, 0xc919, 0xef7f, 0xc919, 0x21, 0 - .dw 0xefc0, 0xc919, 0xefff, 0xc919, 0x21, 0 - .dw 0xf040, 0xc919, 0xf07f, 0xc919, 0x21, 0 - .dw 0xf0c0, 0xc919, 0xf0ff, 0xc919, 0x21, 0 - .dw 0xf140, 0xc919, 0xf17f, 0xc919, 0x21, 0 - .dw 0xf1c0, 0xc919, 0xf1ff, 0xc919, 0x21, 0 - .dw 0xf240, 0xc919, 0xf27f, 0xc919, 0x21, 0 - .dw 0xf2c0, 0xc919, 0xf2ff, 0xc919, 0x21, 0 - .dw 0xf340, 0xc919, 0xf37f, 0xc919, 0x21, 0 - .dw 0xf3c0, 0xc919, 0xf3ff, 0xc919, 0x21, 0 - .dw 0xf440, 0xc919, 0xf47f, 0xc919, 0x21, 0 - .dw 0xf4c0, 0xc919, 0xf4ff, 0xc919, 0x21, 0 - .dw 0xf540, 0xc919, 0xf57f, 0xc919, 0x21, 0 - .dw 0xf5c0, 0xc919, 0xf5ff, 0xc919, 0x21, 0 - .dw 0xf640, 0xc919, 0xf67f, 0xc919, 0x21, 0 - .dw 0xf6c0, 0xc919, 0xf6ff, 0xc919, 0x21, 0 - .dw 0xf740, 0xc919, 0xf77f, 0xc919, 0x21, 0 - .dw 0xf7c0, 0xc919, 0xf7ff, 0xc919, 0x21, 0 - .dw 0xf840, 0xc919, 0xf87f, 0xc919, 0x21, 0 - .dw 0xf8c0, 0xc919, 0xf8ff, 0xc919, 0x21, 0 - .dw 0xf940, 0xc919, 0xf97f, 0xc919, 0x21, 0 - .dw 0xf9c0, 0xc919, 0x1fff, 0xc91a, 0x21, 0 - .dw 0x2040, 0xc91a, 0x207f, 0xc91a, 0x21, 0 - .dw 0x20c0, 0xc91a, 0x20ff, 0xc91a, 0x21, 0 - .dw 0x2140, 0xc91a, 0x217f, 0xc91a, 0x21, 0 - .dw 0x21c0, 0xc91a, 0x21ff, 0xc91a, 0x21, 0 - .dw 0x2240, 0xc91a, 0x227f, 0xc91a, 0x21, 0 - .dw 0x22c0, 0xc91a, 0x22ff, 0xc91a, 0x21, 0 - .dw 0x2340, 0xc91a, 0x237f, 0xc91a, 0x21, 0 - .dw 0x23c0, 0xc91a, 0x23ff, 0xc91a, 0x21, 0 - .dw 0x2440, 0xc91a, 0x247f, 0xc91a, 0x21, 0 - .dw 0x24c0, 0xc91a, 0x24ff, 0xc91a, 0x21, 0 - .dw 0x2540, 0xc91a, 0x257f, 0xc91a, 0x21, 0 - .dw 0x25c0, 0xc91a, 0x25ff, 0xc91a, 0x21, 0 - .dw 0x2640, 0xc91a, 0x267f, 0xc91a, 0x21, 0 - .dw 0x26c0, 0xc91a, 0x26ff, 0xc91a, 0x21, 0 - .dw 0x2740, 0xc91a, 0x277f, 0xc91a, 0x21, 0 - .dw 0x27c0, 0xc91a, 0x27ff, 0xc91a, 0x21, 0 - .dw 0x2840, 0xc91a, 0x287f, 0xc91a, 0x21, 0 - .dw 0x28c0, 0xc91a, 0x28ff, 0xc91a, 0x21, 0 - .dw 0x2940, 0xc91a, 0x297f, 0xc91a, 0x21, 0 - .dw 0x29c0, 0xc91a, 0x29ff, 0xc91a, 0x21, 0 - .dw 0x2a40, 0xc91a, 0x2a7f, 0xc91a, 0x21, 0 - .dw 0x2ac0, 0xc91a, 0x2aff, 0xc91a, 0x21, 0 - .dw 0x2b40, 0xc91a, 0x2b7f, 0xc91a, 0x21, 0 - .dw 0x2bc0, 0xc91a, 0x2bff, 0xc91a, 0x21, 0 - .dw 0x2c40, 0xc91a, 0x2c7f, 0xc91a, 0x21, 0 - .dw 0x2cc0, 0xc91a, 0x2cff, 0xc91a, 0x21, 0 - .dw 0x2d40, 0xc91a, 0x2d7f, 0xc91a, 0x21, 0 - .dw 0x2dc0, 0xc91a, 0x2dff, 0xc91a, 0x21, 0 - .dw 0x2e40, 0xc91a, 0x2e7f, 0xc91a, 0x21, 0 - .dw 0x2ec0, 0xc91a, 0x2eff, 0xc91a, 0x21, 0 - .dw 0x2f40, 0xc91a, 0x2f7f, 0xc91a, 0x21, 0 - .dw 0x2fc0, 0xc91a, 0x2fff, 0xc91a, 0x21, 0 - .dw 0x3040, 0xc91a, 0x307f, 0xc91a, 0x21, 0 - .dw 0x30c0, 0xc91a, 0x30ff, 0xc91a, 0x21, 0 - .dw 0x3140, 0xc91a, 0x317f, 0xc91a, 0x21, 0 - .dw 0x31c0, 0xc91a, 0x31ff, 0xc91a, 0x21, 0 - .dw 0x3240, 0xc91a, 0x327f, 0xc91a, 0x21, 0 - .dw 0x32c0, 0xc91a, 0x32ff, 0xc91a, 0x21, 0 - .dw 0x3340, 0xc91a, 0x337f, 0xc91a, 0x21, 0 - .dw 0x33c0, 0xc91a, 0x33ff, 0xc91a, 0x21, 0 - .dw 0x3440, 0xc91a, 0x347f, 0xc91a, 0x21, 0 - .dw 0x34c0, 0xc91a, 0x34ff, 0xc91a, 0x21, 0 - .dw 0x3540, 0xc91a, 0x357f, 0xc91a, 0x21, 0 - .dw 0x35c0, 0xc91a, 0x35ff, 0xc91a, 0x21, 0 - .dw 0x3640, 0xc91a, 0x367f, 0xc91a, 0x21, 0 - .dw 0x36c0, 0xc91a, 0x36ff, 0xc91a, 0x21, 0 - .dw 0x3740, 0xc91a, 0x377f, 0xc91a, 0x21, 0 - .dw 0x37c0, 0xc91a, 0x37ff, 0xc91a, 0x21, 0 - .dw 0x3840, 0xc91a, 0x387f, 0xc91a, 0x21, 0 - .dw 0x38c0, 0xc91a, 0x38ff, 0xc91a, 0x21, 0 - .dw 0x3940, 0xc91a, 0x397f, 0xc91a, 0x21, 0 - .dw 0x39c0, 0xc91a, 0x5fff, 0xc91a, 0x21, 0 - .dw 0x6040, 0xc91a, 0x607f, 0xc91a, 0x21, 0 - .dw 0x60c0, 0xc91a, 0x60ff, 0xc91a, 0x21, 0 - .dw 0x6140, 0xc91a, 0x617f, 0xc91a, 0x21, 0 - .dw 0x61c0, 0xc91a, 0x61ff, 0xc91a, 0x21, 0 - .dw 0x6240, 0xc91a, 0x627f, 0xc91a, 0x21, 0 - .dw 0x62c0, 0xc91a, 0x62ff, 0xc91a, 0x21, 0 - .dw 0x6340, 0xc91a, 0x637f, 0xc91a, 0x21, 0 - .dw 0x63c0, 0xc91a, 0x63ff, 0xc91a, 0x21, 0 - .dw 0x6440, 0xc91a, 0x647f, 0xc91a, 0x21, 0 - .dw 0x64c0, 0xc91a, 0x64ff, 0xc91a, 0x21, 0 - .dw 0x6540, 0xc91a, 0x657f, 0xc91a, 0x21, 0 - .dw 0x65c0, 0xc91a, 0x65ff, 0xc91a, 0x21, 0 - .dw 0x6640, 0xc91a, 0x667f, 0xc91a, 0x21, 0 - .dw 0x66c0, 0xc91a, 0x66ff, 0xc91a, 0x21, 0 - .dw 0x6740, 0xc91a, 0x677f, 0xc91a, 0x21, 0 - .dw 0x67c0, 0xc91a, 0x67ff, 0xc91a, 0x21, 0 - .dw 0x6840, 0xc91a, 0x687f, 0xc91a, 0x21, 0 - .dw 0x68c0, 0xc91a, 0x68ff, 0xc91a, 0x21, 0 - .dw 0x6940, 0xc91a, 0x697f, 0xc91a, 0x21, 0 - .dw 0x69c0, 0xc91a, 0x69ff, 0xc91a, 0x21, 0 - .dw 0x6a40, 0xc91a, 0x6a7f, 0xc91a, 0x21, 0 - .dw 0x6ac0, 0xc91a, 0x6aff, 0xc91a, 0x21, 0 - .dw 0x6b40, 0xc91a, 0x6b7f, 0xc91a, 0x21, 0 - .dw 0x6bc0, 0xc91a, 0x6bff, 0xc91a, 0x21, 0 - .dw 0x6c40, 0xc91a, 0x6c7f, 0xc91a, 0x21, 0 - .dw 0x6cc0, 0xc91a, 0x6cff, 0xc91a, 0x21, 0 - .dw 0x6d40, 0xc91a, 0x6d7f, 0xc91a, 0x21, 0 - .dw 0x6dc0, 0xc91a, 0x6dff, 0xc91a, 0x21, 0 - .dw 0x6e40, 0xc91a, 0x6e7f, 0xc91a, 0x21, 0 - .dw 0x6ec0, 0xc91a, 0x6eff, 0xc91a, 0x21, 0 - .dw 0x6f40, 0xc91a, 0x6f7f, 0xc91a, 0x21, 0 - .dw 0x6fc0, 0xc91a, 0x6fff, 0xc91a, 0x21, 0 - .dw 0x7040, 0xc91a, 0x707f, 0xc91a, 0x21, 0 - .dw 0x70c0, 0xc91a, 0x70ff, 0xc91a, 0x21, 0 - .dw 0x7140, 0xc91a, 0x717f, 0xc91a, 0x21, 0 - .dw 0x71c0, 0xc91a, 0x71ff, 0xc91a, 0x21, 0 - .dw 0x7240, 0xc91a, 0x727f, 0xc91a, 0x21, 0 - .dw 0x72c0, 0xc91a, 0x72ff, 0xc91a, 0x21, 0 - .dw 0x7340, 0xc91a, 0x737f, 0xc91a, 0x21, 0 - .dw 0x73c0, 0xc91a, 0x73ff, 0xc91a, 0x21, 0 - .dw 0x7440, 0xc91a, 0x747f, 0xc91a, 0x21, 0 - .dw 0x74c0, 0xc91a, 0x74ff, 0xc91a, 0x21, 0 - .dw 0x7540, 0xc91a, 0x757f, 0xc91a, 0x21, 0 - .dw 0x75c0, 0xc91a, 0x75ff, 0xc91a, 0x21, 0 - .dw 0x7640, 0xc91a, 0x767f, 0xc91a, 0x21, 0 - .dw 0x76c0, 0xc91a, 0x76ff, 0xc91a, 0x21, 0 - .dw 0x7740, 0xc91a, 0x777f, 0xc91a, 0x21, 0 - .dw 0x77c0, 0xc91a, 0x77ff, 0xc91a, 0x21, 0 - .dw 0x7840, 0xc91a, 0x787f, 0xc91a, 0x21, 0 - .dw 0x78c0, 0xc91a, 0x78ff, 0xc91a, 0x21, 0 - .dw 0x7940, 0xc91a, 0x797f, 0xc91a, 0x21, 0 - .dw 0x79c0, 0xc91a, 0x9fff, 0xc91a, 0x21, 0 - .dw 0xa040, 0xc91a, 0xa07f, 0xc91a, 0x21, 0 - .dw 0xa0c0, 0xc91a, 0xa0ff, 0xc91a, 0x21, 0 - .dw 0xa140, 0xc91a, 0xa17f, 0xc91a, 0x21, 0 - .dw 0xa1c0, 0xc91a, 0xa1ff, 0xc91a, 0x21, 0 - .dw 0xa240, 0xc91a, 0xa27f, 0xc91a, 0x21, 0 - .dw 0xa2c0, 0xc91a, 0xa2ff, 0xc91a, 0x21, 0 - .dw 0xa340, 0xc91a, 0xa37f, 0xc91a, 0x21, 0 - .dw 0xa3c0, 0xc91a, 0xa3ff, 0xc91a, 0x21, 0 - .dw 0xa440, 0xc91a, 0xa47f, 0xc91a, 0x21, 0 - .dw 0xa4c0, 0xc91a, 0xa4ff, 0xc91a, 0x21, 0 - .dw 0xa540, 0xc91a, 0xa57f, 0xc91a, 0x21, 0 - .dw 0xa5c0, 0xc91a, 0xa5ff, 0xc91a, 0x21, 0 - .dw 0xa640, 0xc91a, 0xa67f, 0xc91a, 0x21, 0 - .dw 0xa6c0, 0xc91a, 0xa6ff, 0xc91a, 0x21, 0 - .dw 0xa740, 0xc91a, 0xa77f, 0xc91a, 0x21, 0 - .dw 0xa7c0, 0xc91a, 0xa7ff, 0xc91a, 0x21, 0 - .dw 0xa840, 0xc91a, 0xa87f, 0xc91a, 0x21, 0 - .dw 0xa8c0, 0xc91a, 0xa8ff, 0xc91a, 0x21, 0 - .dw 0xa940, 0xc91a, 0xa97f, 0xc91a, 0x21, 0 - .dw 0xa9c0, 0xc91a, 0xa9ff, 0xc91a, 0x21, 0 - .dw 0xaa40, 0xc91a, 0xaa7f, 0xc91a, 0x21, 0 - .dw 0xaac0, 0xc91a, 0xaaff, 0xc91a, 0x21, 0 - .dw 0xab40, 0xc91a, 0xab7f, 0xc91a, 0x21, 0 - .dw 0xabc0, 0xc91a, 0xabff, 0xc91a, 0x21, 0 - .dw 0xac40, 0xc91a, 0xac7f, 0xc91a, 0x21, 0 - .dw 0xacc0, 0xc91a, 0xacff, 0xc91a, 0x21, 0 - .dw 0xad40, 0xc91a, 0xad7f, 0xc91a, 0x21, 0 - .dw 0xadc0, 0xc91a, 0xadff, 0xc91a, 0x21, 0 - .dw 0xae40, 0xc91a, 0xae7f, 0xc91a, 0x21, 0 - .dw 0xaec0, 0xc91a, 0xaeff, 0xc91a, 0x21, 0 - .dw 0xaf40, 0xc91a, 0xaf7f, 0xc91a, 0x21, 0 - .dw 0xafc0, 0xc91a, 0xafff, 0xc91a, 0x21, 0 - .dw 0xb040, 0xc91a, 0xb07f, 0xc91a, 0x21, 0 - .dw 0xb0c0, 0xc91a, 0xb0ff, 0xc91a, 0x21, 0 - .dw 0xb140, 0xc91a, 0xb17f, 0xc91a, 0x21, 0 - .dw 0xb1c0, 0xc91a, 0xb1ff, 0xc91a, 0x21, 0 - .dw 0xb240, 0xc91a, 0xb27f, 0xc91a, 0x21, 0 - .dw 0xb2c0, 0xc91a, 0xb2ff, 0xc91a, 0x21, 0 - .dw 0xb340, 0xc91a, 0xb37f, 0xc91a, 0x21, 0 - .dw 0xb3c0, 0xc91a, 0xb3ff, 0xc91a, 0x21, 0 - .dw 0xb440, 0xc91a, 0xb47f, 0xc91a, 0x21, 0 - .dw 0xb4c0, 0xc91a, 0xb4ff, 0xc91a, 0x21, 0 - .dw 0xb540, 0xc91a, 0xb57f, 0xc91a, 0x21, 0 - .dw 0xb5c0, 0xc91a, 0xb5ff, 0xc91a, 0x21, 0 - .dw 0xb640, 0xc91a, 0xb67f, 0xc91a, 0x21, 0 - .dw 0xb6c0, 0xc91a, 0xb6ff, 0xc91a, 0x21, 0 - .dw 0xb740, 0xc91a, 0xb77f, 0xc91a, 0x21, 0 - .dw 0xb7c0, 0xc91a, 0xb7ff, 0xc91a, 0x21, 0 - .dw 0xb840, 0xc91a, 0xb87f, 0xc91a, 0x21, 0 - .dw 0xb8c0, 0xc91a, 0xb8ff, 0xc91a, 0x21, 0 - .dw 0xb940, 0xc91a, 0xb97f, 0xc91a, 0x21, 0 - .dw 0xb9c0, 0xc91a, 0xdfff, 0xc91a, 0x21, 0 - .dw 0xe040, 0xc91a, 0xe07f, 0xc91a, 0x21, 0 - .dw 0xe0c0, 0xc91a, 0xe0ff, 0xc91a, 0x21, 0 - .dw 0xe140, 0xc91a, 0xe17f, 0xc91a, 0x21, 0 - .dw 0xe1c0, 0xc91a, 0xe1ff, 0xc91a, 0x21, 0 - .dw 0xe240, 0xc91a, 0xe27f, 0xc91a, 0x21, 0 - .dw 0xe2c0, 0xc91a, 0xe2ff, 0xc91a, 0x21, 0 - .dw 0xe340, 0xc91a, 0xe37f, 0xc91a, 0x21, 0 - .dw 0xe3c0, 0xc91a, 0xe3ff, 0xc91a, 0x21, 0 - .dw 0xe440, 0xc91a, 0xe47f, 0xc91a, 0x21, 0 - .dw 0xe4c0, 0xc91a, 0xe4ff, 0xc91a, 0x21, 0 - .dw 0xe540, 0xc91a, 0xe57f, 0xc91a, 0x21, 0 - .dw 0xe5c0, 0xc91a, 0xe5ff, 0xc91a, 0x21, 0 - .dw 0xe640, 0xc91a, 0xe67f, 0xc91a, 0x21, 0 - .dw 0xe6c0, 0xc91a, 0xe6ff, 0xc91a, 0x21, 0 - .dw 0xe740, 0xc91a, 0xe77f, 0xc91a, 0x21, 0 - .dw 0xe7c0, 0xc91a, 0xe7ff, 0xc91a, 0x21, 0 - .dw 0xe840, 0xc91a, 0xe87f, 0xc91a, 0x21, 0 - .dw 0xe8c0, 0xc91a, 0xe8ff, 0xc91a, 0x21, 0 - .dw 0xe940, 0xc91a, 0xe97f, 0xc91a, 0x21, 0 - .dw 0xe9c0, 0xc91a, 0xe9ff, 0xc91a, 0x21, 0 - .dw 0xea40, 0xc91a, 0xea7f, 0xc91a, 0x21, 0 - .dw 0xeac0, 0xc91a, 0xeaff, 0xc91a, 0x21, 0 - .dw 0xeb40, 0xc91a, 0xeb7f, 0xc91a, 0x21, 0 - .dw 0xebc0, 0xc91a, 0xebff, 0xc91a, 0x21, 0 - .dw 0xec40, 0xc91a, 0xec7f, 0xc91a, 0x21, 0 - .dw 0xecc0, 0xc91a, 0xecff, 0xc91a, 0x21, 0 - .dw 0xed40, 0xc91a, 0xed7f, 0xc91a, 0x21, 0 - .dw 0xedc0, 0xc91a, 0xedff, 0xc91a, 0x21, 0 - .dw 0xee40, 0xc91a, 0xee7f, 0xc91a, 0x21, 0 - .dw 0xeec0, 0xc91a, 0xeeff, 0xc91a, 0x21, 0 - .dw 0xef40, 0xc91a, 0xef7f, 0xc91a, 0x21, 0 - .dw 0xefc0, 0xc91a, 0xefff, 0xc91a, 0x21, 0 - .dw 0xf040, 0xc91a, 0xf07f, 0xc91a, 0x21, 0 - .dw 0xf0c0, 0xc91a, 0xf0ff, 0xc91a, 0x21, 0 - .dw 0xf140, 0xc91a, 0xf17f, 0xc91a, 0x21, 0 - .dw 0xf1c0, 0xc91a, 0xf1ff, 0xc91a, 0x21, 0 - .dw 0xf240, 0xc91a, 0xf27f, 0xc91a, 0x21, 0 - .dw 0xf2c0, 0xc91a, 0xf2ff, 0xc91a, 0x21, 0 - .dw 0xf340, 0xc91a, 0xf37f, 0xc91a, 0x21, 0 - .dw 0xf3c0, 0xc91a, 0xf3ff, 0xc91a, 0x21, 0 - .dw 0xf440, 0xc91a, 0xf47f, 0xc91a, 0x21, 0 - .dw 0xf4c0, 0xc91a, 0xf4ff, 0xc91a, 0x21, 0 - .dw 0xf540, 0xc91a, 0xf57f, 0xc91a, 0x21, 0 - .dw 0xf5c0, 0xc91a, 0xf5ff, 0xc91a, 0x21, 0 - .dw 0xf640, 0xc91a, 0xf67f, 0xc91a, 0x21, 0 - .dw 0xf6c0, 0xc91a, 0xf6ff, 0xc91a, 0x21, 0 - .dw 0xf740, 0xc91a, 0xf77f, 0xc91a, 0x21, 0 - .dw 0xf7c0, 0xc91a, 0xf7ff, 0xc91a, 0x21, 0 - .dw 0xf840, 0xc91a, 0xf87f, 0xc91a, 0x21, 0 - .dw 0xf8c0, 0xc91a, 0xf8ff, 0xc91a, 0x21, 0 - .dw 0xf940, 0xc91a, 0xf97f, 0xc91a, 0x21, 0 - .dw 0xf9c0, 0xc91a, 0xffff, 0xc91b, 0x21, 0 - .dw 0x0040, 0xc91c, 0x007f, 0xc91c, 0x21, 0 - .dw 0x00c0, 0xc91c, 0x00ff, 0xc91c, 0x21, 0 - .dw 0x0140, 0xc91c, 0x017f, 0xc91c, 0x21, 0 - .dw 0x01c0, 0xc91c, 0x01ff, 0xc91c, 0x21, 0 - .dw 0x0240, 0xc91c, 0x027f, 0xc91c, 0x21, 0 - .dw 0x02c0, 0xc91c, 0x02ff, 0xc91c, 0x21, 0 - .dw 0x0340, 0xc91c, 0x037f, 0xc91c, 0x21, 0 - .dw 0x03c0, 0xc91c, 0x03ff, 0xc91c, 0x21, 0 - .dw 0x0440, 0xc91c, 0x047f, 0xc91c, 0x21, 0 - .dw 0x04c0, 0xc91c, 0x04ff, 0xc91c, 0x21, 0 - .dw 0x0540, 0xc91c, 0x057f, 0xc91c, 0x21, 0 - .dw 0x05c0, 0xc91c, 0x05ff, 0xc91c, 0x21, 0 - .dw 0x0640, 0xc91c, 0x067f, 0xc91c, 0x21, 0 - .dw 0x06c0, 0xc91c, 0x06ff, 0xc91c, 0x21, 0 - .dw 0x0740, 0xc91c, 0x077f, 0xc91c, 0x21, 0 - .dw 0x07c0, 0xc91c, 0x07ff, 0xc91c, 0x21, 0 - .dw 0x0840, 0xc91c, 0x087f, 0xc91c, 0x21, 0 - .dw 0x08c0, 0xc91c, 0x08ff, 0xc91c, 0x21, 0 - .dw 0x0940, 0xc91c, 0x097f, 0xc91c, 0x21, 0 - .dw 0x09c0, 0xc91c, 0x09ff, 0xc91c, 0x21, 0 - .dw 0x0a40, 0xc91c, 0x0a7f, 0xc91c, 0x21, 0 - .dw 0x0ac0, 0xc91c, 0x0aff, 0xc91c, 0x21, 0 - .dw 0x0b40, 0xc91c, 0x0b7f, 0xc91c, 0x21, 0 - .dw 0x0bc0, 0xc91c, 0x0bff, 0xc91c, 0x21, 0 - .dw 0x0c40, 0xc91c, 0x0c7f, 0xc91c, 0x21, 0 - .dw 0x0cc0, 0xc91c, 0x0cff, 0xc91c, 0x21, 0 - .dw 0x0d40, 0xc91c, 0x0d7f, 0xc91c, 0x21, 0 - .dw 0x0dc0, 0xc91c, 0x0dff, 0xc91c, 0x21, 0 - .dw 0x0e40, 0xc91c, 0x0e7f, 0xc91c, 0x21, 0 - .dw 0x0ec0, 0xc91c, 0x0eff, 0xc91c, 0x21, 0 - .dw 0x0f40, 0xc91c, 0x0f7f, 0xc91c, 0x21, 0 - .dw 0x0fc0, 0xc91c, 0x0fff, 0xc91c, 0x21, 0 - .dw 0x1040, 0xc91c, 0x107f, 0xc91c, 0x21, 0 - .dw 0x10c0, 0xc91c, 0x10ff, 0xc91c, 0x21, 0 - .dw 0x1140, 0xc91c, 0x117f, 0xc91c, 0x21, 0 - .dw 0x11c0, 0xc91c, 0x11ff, 0xc91c, 0x21, 0 - .dw 0x1240, 0xc91c, 0x127f, 0xc91c, 0x21, 0 - .dw 0x12c0, 0xc91c, 0x12ff, 0xc91c, 0x21, 0 - .dw 0x1340, 0xc91c, 0x137f, 0xc91c, 0x21, 0 - .dw 0x13c0, 0xc91c, 0x13ff, 0xc91c, 0x21, 0 - .dw 0x1440, 0xc91c, 0x147f, 0xc91c, 0x21, 0 - .dw 0x14c0, 0xc91c, 0x14ff, 0xc91c, 0x21, 0 - .dw 0x1540, 0xc91c, 0x157f, 0xc91c, 0x21, 0 - .dw 0x15c0, 0xc91c, 0x15ff, 0xc91c, 0x21, 0 - .dw 0x1640, 0xc91c, 0x167f, 0xc91c, 0x21, 0 - .dw 0x16c0, 0xc91c, 0x16ff, 0xc91c, 0x21, 0 - .dw 0x1740, 0xc91c, 0x177f, 0xc91c, 0x21, 0 - .dw 0x17c0, 0xc91c, 0x17ff, 0xc91c, 0x21, 0 - .dw 0x1840, 0xc91c, 0x187f, 0xc91c, 0x21, 0 - .dw 0x18c0, 0xc91c, 0x18ff, 0xc91c, 0x21, 0 - .dw 0x1940, 0xc91c, 0x197f, 0xc91c, 0x21, 0 - .dw 0x19c0, 0xc91c, 0x1fff, 0xc91c, 0x21, 0 - .dw 0x2040, 0xc91c, 0x207f, 0xc91c, 0x21, 0 - .dw 0x20c0, 0xc91c, 0x20ff, 0xc91c, 0x21, 0 - .dw 0x2140, 0xc91c, 0x217f, 0xc91c, 0x21, 0 - .dw 0x21c0, 0xc91c, 0x21ff, 0xc91c, 0x21, 0 - .dw 0x2240, 0xc91c, 0x227f, 0xc91c, 0x21, 0 - .dw 0x22c0, 0xc91c, 0x22ff, 0xc91c, 0x21, 0 - .dw 0x2340, 0xc91c, 0x237f, 0xc91c, 0x21, 0 - .dw 0x23c0, 0xc91c, 0x23ff, 0xc91c, 0x21, 0 - .dw 0x2440, 0xc91c, 0x247f, 0xc91c, 0x21, 0 - .dw 0x24c0, 0xc91c, 0x24ff, 0xc91c, 0x21, 0 - .dw 0x2540, 0xc91c, 0x257f, 0xc91c, 0x21, 0 - .dw 0x25c0, 0xc91c, 0x25ff, 0xc91c, 0x21, 0 - .dw 0x2640, 0xc91c, 0x267f, 0xc91c, 0x21, 0 - .dw 0x26c0, 0xc91c, 0x26ff, 0xc91c, 0x21, 0 - .dw 0x2740, 0xc91c, 0x277f, 0xc91c, 0x21, 0 - .dw 0x27c0, 0xc91c, 0x27ff, 0xc91c, 0x21, 0 - .dw 0x2840, 0xc91c, 0x287f, 0xc91c, 0x21, 0 - .dw 0x28c0, 0xc91c, 0x28ff, 0xc91c, 0x21, 0 - .dw 0x2940, 0xc91c, 0x297f, 0xc91c, 0x21, 0 - .dw 0x29c0, 0xc91c, 0x29ff, 0xc91c, 0x21, 0 - .dw 0x2a40, 0xc91c, 0x2a7f, 0xc91c, 0x21, 0 - .dw 0x2ac0, 0xc91c, 0x2aff, 0xc91c, 0x21, 0 - .dw 0x2b40, 0xc91c, 0x2b7f, 0xc91c, 0x21, 0 - .dw 0x2bc0, 0xc91c, 0x2bff, 0xc91c, 0x21, 0 - .dw 0x2c40, 0xc91c, 0x2c7f, 0xc91c, 0x21, 0 - .dw 0x2cc0, 0xc91c, 0x2cff, 0xc91c, 0x21, 0 - .dw 0x2d40, 0xc91c, 0x2d7f, 0xc91c, 0x21, 0 - .dw 0x2dc0, 0xc91c, 0x2dff, 0xc91c, 0x21, 0 - .dw 0x2e40, 0xc91c, 0x2e7f, 0xc91c, 0x21, 0 - .dw 0x2ec0, 0xc91c, 0x2eff, 0xc91c, 0x21, 0 - .dw 0x2f40, 0xc91c, 0x2f7f, 0xc91c, 0x21, 0 - .dw 0x2fc0, 0xc91c, 0x2fff, 0xc91c, 0x21, 0 - .dw 0x3040, 0xc91c, 0x307f, 0xc91c, 0x21, 0 - .dw 0x30c0, 0xc91c, 0x30ff, 0xc91c, 0x21, 0 - .dw 0x3140, 0xc91c, 0x317f, 0xc91c, 0x21, 0 - .dw 0x31c0, 0xc91c, 0x31ff, 0xc91c, 0x21, 0 - .dw 0x3240, 0xc91c, 0x327f, 0xc91c, 0x21, 0 - .dw 0x32c0, 0xc91c, 0x32ff, 0xc91c, 0x21, 0 - .dw 0x3340, 0xc91c, 0x337f, 0xc91c, 0x21, 0 - .dw 0x33c0, 0xc91c, 0x33ff, 0xc91c, 0x21, 0 - .dw 0x3440, 0xc91c, 0x347f, 0xc91c, 0x21, 0 - .dw 0x34c0, 0xc91c, 0x34ff, 0xc91c, 0x21, 0 - .dw 0x3540, 0xc91c, 0x357f, 0xc91c, 0x21, 0 - .dw 0x35c0, 0xc91c, 0x35ff, 0xc91c, 0x21, 0 - .dw 0x3640, 0xc91c, 0x367f, 0xc91c, 0x21, 0 - .dw 0x36c0, 0xc91c, 0x36ff, 0xc91c, 0x21, 0 - .dw 0x3740, 0xc91c, 0x377f, 0xc91c, 0x21, 0 - .dw 0x37c0, 0xc91c, 0x37ff, 0xc91c, 0x21, 0 - .dw 0x3840, 0xc91c, 0x387f, 0xc91c, 0x21, 0 - .dw 0x38c0, 0xc91c, 0x38ff, 0xc91c, 0x21, 0 - .dw 0x3940, 0xc91c, 0x397f, 0xc91c, 0x21, 0 - .dw 0x39c0, 0xc91c, 0x3fff, 0xc91c, 0x21, 0 - .dw 0x4040, 0xc91c, 0x407f, 0xc91c, 0x21, 0 - .dw 0x40c0, 0xc91c, 0x40ff, 0xc91c, 0x21, 0 - .dw 0x4140, 0xc91c, 0x417f, 0xc91c, 0x21, 0 - .dw 0x41c0, 0xc91c, 0x41ff, 0xc91c, 0x21, 0 - .dw 0x4240, 0xc91c, 0x427f, 0xc91c, 0x21, 0 - .dw 0x42c0, 0xc91c, 0x42ff, 0xc91c, 0x21, 0 - .dw 0x4340, 0xc91c, 0x437f, 0xc91c, 0x21, 0 - .dw 0x43c0, 0xc91c, 0x43ff, 0xc91c, 0x21, 0 - .dw 0x4440, 0xc91c, 0x447f, 0xc91c, 0x21, 0 - .dw 0x44c0, 0xc91c, 0x44ff, 0xc91c, 0x21, 0 - .dw 0x4540, 0xc91c, 0x457f, 0xc91c, 0x21, 0 - .dw 0x45c0, 0xc91c, 0x45ff, 0xc91c, 0x21, 0 - .dw 0x4640, 0xc91c, 0x467f, 0xc91c, 0x21, 0 - .dw 0x46c0, 0xc91c, 0x46ff, 0xc91c, 0x21, 0 - .dw 0x4740, 0xc91c, 0x477f, 0xc91c, 0x21, 0 - .dw 0x47c0, 0xc91c, 0x47ff, 0xc91c, 0x21, 0 - .dw 0x4840, 0xc91c, 0x487f, 0xc91c, 0x21, 0 - .dw 0x48c0, 0xc91c, 0x48ff, 0xc91c, 0x21, 0 - .dw 0x4940, 0xc91c, 0x497f, 0xc91c, 0x21, 0 - .dw 0x49c0, 0xc91c, 0x49ff, 0xc91c, 0x21, 0 - .dw 0x4a40, 0xc91c, 0x4a7f, 0xc91c, 0x21, 0 - .dw 0x4ac0, 0xc91c, 0x4aff, 0xc91c, 0x21, 0 - .dw 0x4b40, 0xc91c, 0x4b7f, 0xc91c, 0x21, 0 - .dw 0x4bc0, 0xc91c, 0x4bff, 0xc91c, 0x21, 0 - .dw 0x4c40, 0xc91c, 0x4c7f, 0xc91c, 0x21, 0 - .dw 0x4cc0, 0xc91c, 0x4cff, 0xc91c, 0x21, 0 - .dw 0x4d40, 0xc91c, 0x4d7f, 0xc91c, 0x21, 0 - .dw 0x4dc0, 0xc91c, 0x4dff, 0xc91c, 0x21, 0 - .dw 0x4e40, 0xc91c, 0x4e7f, 0xc91c, 0x21, 0 - .dw 0x4ec0, 0xc91c, 0x4eff, 0xc91c, 0x21, 0 - .dw 0x4f40, 0xc91c, 0x4f7f, 0xc91c, 0x21, 0 - .dw 0x4fc0, 0xc91c, 0x4fff, 0xc91c, 0x21, 0 - .dw 0x5040, 0xc91c, 0x507f, 0xc91c, 0x21, 0 - .dw 0x50c0, 0xc91c, 0x50ff, 0xc91c, 0x21, 0 - .dw 0x5140, 0xc91c, 0x517f, 0xc91c, 0x21, 0 - .dw 0x51c0, 0xc91c, 0x51ff, 0xc91c, 0x21, 0 - .dw 0x5240, 0xc91c, 0x527f, 0xc91c, 0x21, 0 - .dw 0x52c0, 0xc91c, 0x52ff, 0xc91c, 0x21, 0 - .dw 0x5340, 0xc91c, 0x537f, 0xc91c, 0x21, 0 - .dw 0x53c0, 0xc91c, 0x53ff, 0xc91c, 0x21, 0 - .dw 0x5440, 0xc91c, 0x547f, 0xc91c, 0x21, 0 - .dw 0x54c0, 0xc91c, 0x54ff, 0xc91c, 0x21, 0 - .dw 0x5540, 0xc91c, 0x557f, 0xc91c, 0x21, 0 - .dw 0x55c0, 0xc91c, 0x55ff, 0xc91c, 0x21, 0 - .dw 0x5640, 0xc91c, 0x567f, 0xc91c, 0x21, 0 - .dw 0x56c0, 0xc91c, 0x56ff, 0xc91c, 0x21, 0 - .dw 0x5740, 0xc91c, 0x577f, 0xc91c, 0x21, 0 - .dw 0x57c0, 0xc91c, 0x57ff, 0xc91c, 0x21, 0 - .dw 0x5840, 0xc91c, 0x587f, 0xc91c, 0x21, 0 - .dw 0x58c0, 0xc91c, 0x58ff, 0xc91c, 0x21, 0 - .dw 0x5940, 0xc91c, 0x597f, 0xc91c, 0x21, 0 - .dw 0x59c0, 0xc91c, 0x5fff, 0xc91c, 0x21, 0 - .dw 0x6040, 0xc91c, 0x607f, 0xc91c, 0x21, 0 - .dw 0x60c0, 0xc91c, 0x60ff, 0xc91c, 0x21, 0 - .dw 0x6140, 0xc91c, 0x617f, 0xc91c, 0x21, 0 - .dw 0x61c0, 0xc91c, 0x61ff, 0xc91c, 0x21, 0 - .dw 0x6240, 0xc91c, 0x627f, 0xc91c, 0x21, 0 - .dw 0x62c0, 0xc91c, 0x62ff, 0xc91c, 0x21, 0 - .dw 0x6340, 0xc91c, 0x637f, 0xc91c, 0x21, 0 - .dw 0x63c0, 0xc91c, 0x63ff, 0xc91c, 0x21, 0 - .dw 0x6440, 0xc91c, 0x647f, 0xc91c, 0x21, 0 - .dw 0x64c0, 0xc91c, 0x64ff, 0xc91c, 0x21, 0 - .dw 0x6540, 0xc91c, 0x657f, 0xc91c, 0x21, 0 - .dw 0x65c0, 0xc91c, 0x65ff, 0xc91c, 0x21, 0 - .dw 0x6640, 0xc91c, 0x667f, 0xc91c, 0x21, 0 - .dw 0x66c0, 0xc91c, 0x66ff, 0xc91c, 0x21, 0 - .dw 0x6740, 0xc91c, 0x677f, 0xc91c, 0x21, 0 - .dw 0x67c0, 0xc91c, 0x67ff, 0xc91c, 0x21, 0 - .dw 0x6840, 0xc91c, 0x687f, 0xc91c, 0x21, 0 - .dw 0x68c0, 0xc91c, 0x68ff, 0xc91c, 0x21, 0 - .dw 0x6940, 0xc91c, 0x697f, 0xc91c, 0x21, 0 - .dw 0x69c0, 0xc91c, 0x69ff, 0xc91c, 0x21, 0 - .dw 0x6a40, 0xc91c, 0x6a7f, 0xc91c, 0x21, 0 - .dw 0x6ac0, 0xc91c, 0x6aff, 0xc91c, 0x21, 0 - .dw 0x6b40, 0xc91c, 0x6b7f, 0xc91c, 0x21, 0 - .dw 0x6bc0, 0xc91c, 0x6bff, 0xc91c, 0x21, 0 - .dw 0x6c40, 0xc91c, 0x6c7f, 0xc91c, 0x21, 0 - .dw 0x6cc0, 0xc91c, 0x6cff, 0xc91c, 0x21, 0 - .dw 0x6d40, 0xc91c, 0x6d7f, 0xc91c, 0x21, 0 - .dw 0x6dc0, 0xc91c, 0x6dff, 0xc91c, 0x21, 0 - .dw 0x6e40, 0xc91c, 0x6e7f, 0xc91c, 0x21, 0 - .dw 0x6ec0, 0xc91c, 0x6eff, 0xc91c, 0x21, 0 - .dw 0x6f40, 0xc91c, 0x6f7f, 0xc91c, 0x21, 0 - .dw 0x6fc0, 0xc91c, 0x6fff, 0xc91c, 0x21, 0 - .dw 0x7040, 0xc91c, 0x707f, 0xc91c, 0x21, 0 - .dw 0x70c0, 0xc91c, 0x70ff, 0xc91c, 0x21, 0 - .dw 0x7140, 0xc91c, 0x717f, 0xc91c, 0x21, 0 - .dw 0x71c0, 0xc91c, 0x71ff, 0xc91c, 0x21, 0 - .dw 0x7240, 0xc91c, 0x727f, 0xc91c, 0x21, 0 - .dw 0x72c0, 0xc91c, 0x72ff, 0xc91c, 0x21, 0 - .dw 0x7340, 0xc91c, 0x737f, 0xc91c, 0x21, 0 - .dw 0x73c0, 0xc91c, 0x73ff, 0xc91c, 0x21, 0 - .dw 0x7440, 0xc91c, 0x747f, 0xc91c, 0x21, 0 - .dw 0x74c0, 0xc91c, 0x74ff, 0xc91c, 0x21, 0 - .dw 0x7540, 0xc91c, 0x757f, 0xc91c, 0x21, 0 - .dw 0x75c0, 0xc91c, 0x75ff, 0xc91c, 0x21, 0 - .dw 0x7640, 0xc91c, 0x767f, 0xc91c, 0x21, 0 - .dw 0x76c0, 0xc91c, 0x76ff, 0xc91c, 0x21, 0 - .dw 0x7740, 0xc91c, 0x777f, 0xc91c, 0x21, 0 - .dw 0x77c0, 0xc91c, 0x77ff, 0xc91c, 0x21, 0 - .dw 0x7840, 0xc91c, 0x787f, 0xc91c, 0x21, 0 - .dw 0x78c0, 0xc91c, 0x78ff, 0xc91c, 0x21, 0 - .dw 0x7940, 0xc91c, 0x797f, 0xc91c, 0x21, 0 - .dw 0x79c0, 0xc91c, 0x7fff, 0xc91c, 0x21, 0 - .dw 0x8040, 0xc91c, 0x807f, 0xc91c, 0x21, 0 - .dw 0x80c0, 0xc91c, 0x80ff, 0xc91c, 0x21, 0 - .dw 0x8140, 0xc91c, 0x817f, 0xc91c, 0x21, 0 - .dw 0x81c0, 0xc91c, 0x81ff, 0xc91c, 0x21, 0 - .dw 0x8240, 0xc91c, 0x827f, 0xc91c, 0x21, 0 - .dw 0x82c0, 0xc91c, 0x82ff, 0xc91c, 0x21, 0 - .dw 0x8340, 0xc91c, 0x837f, 0xc91c, 0x21, 0 - .dw 0x83c0, 0xc91c, 0x83ff, 0xc91c, 0x21, 0 - .dw 0x8440, 0xc91c, 0x847f, 0xc91c, 0x21, 0 - .dw 0x84c0, 0xc91c, 0x84ff, 0xc91c, 0x21, 0 - .dw 0x8540, 0xc91c, 0x857f, 0xc91c, 0x21, 0 - .dw 0x85c0, 0xc91c, 0x85ff, 0xc91c, 0x21, 0 - .dw 0x8640, 0xc91c, 0x867f, 0xc91c, 0x21, 0 - .dw 0x86c0, 0xc91c, 0x86ff, 0xc91c, 0x21, 0 - .dw 0x8740, 0xc91c, 0x877f, 0xc91c, 0x21, 0 - .dw 0x87c0, 0xc91c, 0x87ff, 0xc91c, 0x21, 0 - .dw 0x8840, 0xc91c, 0x887f, 0xc91c, 0x21, 0 - .dw 0x88c0, 0xc91c, 0x88ff, 0xc91c, 0x21, 0 - .dw 0x8940, 0xc91c, 0x897f, 0xc91c, 0x21, 0 - .dw 0x89c0, 0xc91c, 0x89ff, 0xc91c, 0x21, 0 - .dw 0x8a40, 0xc91c, 0x8a7f, 0xc91c, 0x21, 0 - .dw 0x8ac0, 0xc91c, 0x8aff, 0xc91c, 0x21, 0 - .dw 0x8b40, 0xc91c, 0x8b7f, 0xc91c, 0x21, 0 - .dw 0x8bc0, 0xc91c, 0x8bff, 0xc91c, 0x21, 0 - .dw 0x8c40, 0xc91c, 0x8c7f, 0xc91c, 0x21, 0 - .dw 0x8cc0, 0xc91c, 0x8cff, 0xc91c, 0x21, 0 - .dw 0x8d40, 0xc91c, 0x8d7f, 0xc91c, 0x21, 0 - .dw 0x8dc0, 0xc91c, 0x8dff, 0xc91c, 0x21, 0 - .dw 0x8e40, 0xc91c, 0x8e7f, 0xc91c, 0x21, 0 - .dw 0x8ec0, 0xc91c, 0x8eff, 0xc91c, 0x21, 0 - .dw 0x8f40, 0xc91c, 0x8f7f, 0xc91c, 0x21, 0 - .dw 0x8fc0, 0xc91c, 0x8fff, 0xc91c, 0x21, 0 - .dw 0x9040, 0xc91c, 0x907f, 0xc91c, 0x21, 0 - .dw 0x90c0, 0xc91c, 0x90ff, 0xc91c, 0x21, 0 - .dw 0x9140, 0xc91c, 0x917f, 0xc91c, 0x21, 0 - .dw 0x91c0, 0xc91c, 0x91ff, 0xc91c, 0x21, 0 - .dw 0x9240, 0xc91c, 0x927f, 0xc91c, 0x21, 0 - .dw 0x92c0, 0xc91c, 0x92ff, 0xc91c, 0x21, 0 - .dw 0x9340, 0xc91c, 0x937f, 0xc91c, 0x21, 0 - .dw 0x93c0, 0xc91c, 0x93ff, 0xc91c, 0x21, 0 - .dw 0x9440, 0xc91c, 0x947f, 0xc91c, 0x21, 0 - .dw 0x94c0, 0xc91c, 0x94ff, 0xc91c, 0x21, 0 - .dw 0x9540, 0xc91c, 0x957f, 0xc91c, 0x21, 0 - .dw 0x95c0, 0xc91c, 0x95ff, 0xc91c, 0x21, 0 - .dw 0x9640, 0xc91c, 0x967f, 0xc91c, 0x21, 0 - .dw 0x96c0, 0xc91c, 0x96ff, 0xc91c, 0x21, 0 - .dw 0x9740, 0xc91c, 0x977f, 0xc91c, 0x21, 0 - .dw 0x97c0, 0xc91c, 0x97ff, 0xc91c, 0x21, 0 - .dw 0x9840, 0xc91c, 0x987f, 0xc91c, 0x21, 0 - .dw 0x98c0, 0xc91c, 0x98ff, 0xc91c, 0x21, 0 - .dw 0x9940, 0xc91c, 0x997f, 0xc91c, 0x21, 0 - .dw 0x99c0, 0xc91c, 0x9fff, 0xc91c, 0x21, 0 - .dw 0xa040, 0xc91c, 0xa07f, 0xc91c, 0x21, 0 - .dw 0xa0c0, 0xc91c, 0xa0ff, 0xc91c, 0x21, 0 - .dw 0xa140, 0xc91c, 0xa17f, 0xc91c, 0x21, 0 - .dw 0xa1c0, 0xc91c, 0xa1ff, 0xc91c, 0x21, 0 - .dw 0xa240, 0xc91c, 0xa27f, 0xc91c, 0x21, 0 - .dw 0xa2c0, 0xc91c, 0xa2ff, 0xc91c, 0x21, 0 - .dw 0xa340, 0xc91c, 0xa37f, 0xc91c, 0x21, 0 - .dw 0xa3c0, 0xc91c, 0xa3ff, 0xc91c, 0x21, 0 - .dw 0xa440, 0xc91c, 0xa47f, 0xc91c, 0x21, 0 - .dw 0xa4c0, 0xc91c, 0xa4ff, 0xc91c, 0x21, 0 - .dw 0xa540, 0xc91c, 0xa57f, 0xc91c, 0x21, 0 - .dw 0xa5c0, 0xc91c, 0xa5ff, 0xc91c, 0x21, 0 - .dw 0xa640, 0xc91c, 0xa67f, 0xc91c, 0x21, 0 - .dw 0xa6c0, 0xc91c, 0xa6ff, 0xc91c, 0x21, 0 - .dw 0xa740, 0xc91c, 0xa77f, 0xc91c, 0x21, 0 - .dw 0xa7c0, 0xc91c, 0xa7ff, 0xc91c, 0x21, 0 - .dw 0xa840, 0xc91c, 0xa87f, 0xc91c, 0x21, 0 - .dw 0xa8c0, 0xc91c, 0xa8ff, 0xc91c, 0x21, 0 - .dw 0xa940, 0xc91c, 0xa97f, 0xc91c, 0x21, 0 - .dw 0xa9c0, 0xc91c, 0xa9ff, 0xc91c, 0x21, 0 - .dw 0xaa40, 0xc91c, 0xaa7f, 0xc91c, 0x21, 0 - .dw 0xaac0, 0xc91c, 0xaaff, 0xc91c, 0x21, 0 - .dw 0xab40, 0xc91c, 0xab7f, 0xc91c, 0x21, 0 - .dw 0xabc0, 0xc91c, 0xabff, 0xc91c, 0x21, 0 - .dw 0xac40, 0xc91c, 0xac7f, 0xc91c, 0x21, 0 - .dw 0xacc0, 0xc91c, 0xacff, 0xc91c, 0x21, 0 - .dw 0xad40, 0xc91c, 0xad7f, 0xc91c, 0x21, 0 - .dw 0xadc0, 0xc91c, 0xadff, 0xc91c, 0x21, 0 - .dw 0xae40, 0xc91c, 0xae7f, 0xc91c, 0x21, 0 - .dw 0xaec0, 0xc91c, 0xaeff, 0xc91c, 0x21, 0 - .dw 0xaf40, 0xc91c, 0xaf7f, 0xc91c, 0x21, 0 - .dw 0xafc0, 0xc91c, 0xafff, 0xc91c, 0x21, 0 - .dw 0xb040, 0xc91c, 0xb07f, 0xc91c, 0x21, 0 - .dw 0xb0c0, 0xc91c, 0xb0ff, 0xc91c, 0x21, 0 - .dw 0xb140, 0xc91c, 0xb17f, 0xc91c, 0x21, 0 - .dw 0xb1c0, 0xc91c, 0xb1ff, 0xc91c, 0x21, 0 - .dw 0xb240, 0xc91c, 0xb27f, 0xc91c, 0x21, 0 - .dw 0xb2c0, 0xc91c, 0xb2ff, 0xc91c, 0x21, 0 - .dw 0xb340, 0xc91c, 0xb37f, 0xc91c, 0x21, 0 - .dw 0xb3c0, 0xc91c, 0xb3ff, 0xc91c, 0x21, 0 - .dw 0xb440, 0xc91c, 0xb47f, 0xc91c, 0x21, 0 - .dw 0xb4c0, 0xc91c, 0xb4ff, 0xc91c, 0x21, 0 - .dw 0xb540, 0xc91c, 0xb57f, 0xc91c, 0x21, 0 - .dw 0xb5c0, 0xc91c, 0xb5ff, 0xc91c, 0x21, 0 - .dw 0xb640, 0xc91c, 0xb67f, 0xc91c, 0x21, 0 - .dw 0xb6c0, 0xc91c, 0xb6ff, 0xc91c, 0x21, 0 - .dw 0xb740, 0xc91c, 0xb77f, 0xc91c, 0x21, 0 - .dw 0xb7c0, 0xc91c, 0xb7ff, 0xc91c, 0x21, 0 - .dw 0xb840, 0xc91c, 0xb87f, 0xc91c, 0x21, 0 - .dw 0xb8c0, 0xc91c, 0xb8ff, 0xc91c, 0x21, 0 - .dw 0xb940, 0xc91c, 0xb97f, 0xc91c, 0x21, 0 - .dw 0xb9c0, 0xc91c, 0xbfff, 0xc91c, 0x21, 0 - .dw 0xc040, 0xc91c, 0xc07f, 0xc91c, 0x21, 0 - .dw 0xc0c0, 0xc91c, 0xc0ff, 0xc91c, 0x21, 0 - .dw 0xc140, 0xc91c, 0xc17f, 0xc91c, 0x21, 0 - .dw 0xc1c0, 0xc91c, 0xc1ff, 0xc91c, 0x21, 0 - .dw 0xc240, 0xc91c, 0xc27f, 0xc91c, 0x21, 0 - .dw 0xc2c0, 0xc91c, 0xc2ff, 0xc91c, 0x21, 0 - .dw 0xc340, 0xc91c, 0xc37f, 0xc91c, 0x21, 0 - .dw 0xc3c0, 0xc91c, 0xc3ff, 0xc91c, 0x21, 0 - .dw 0xc440, 0xc91c, 0xc47f, 0xc91c, 0x21, 0 - .dw 0xc4c0, 0xc91c, 0xc4ff, 0xc91c, 0x21, 0 - .dw 0xc540, 0xc91c, 0xc57f, 0xc91c, 0x21, 0 - .dw 0xc5c0, 0xc91c, 0xc5ff, 0xc91c, 0x21, 0 - .dw 0xc640, 0xc91c, 0xc67f, 0xc91c, 0x21, 0 - .dw 0xc6c0, 0xc91c, 0xc6ff, 0xc91c, 0x21, 0 - .dw 0xc740, 0xc91c, 0xc77f, 0xc91c, 0x21, 0 - .dw 0xc7c0, 0xc91c, 0xc7ff, 0xc91c, 0x21, 0 - .dw 0xc840, 0xc91c, 0xc87f, 0xc91c, 0x21, 0 - .dw 0xc8c0, 0xc91c, 0xc8ff, 0xc91c, 0x21, 0 - .dw 0xc940, 0xc91c, 0xc97f, 0xc91c, 0x21, 0 - .dw 0xc9c0, 0xc91c, 0xc9ff, 0xc91c, 0x21, 0 - .dw 0xca40, 0xc91c, 0xca7f, 0xc91c, 0x21, 0 - .dw 0xcac0, 0xc91c, 0xcaff, 0xc91c, 0x21, 0 - .dw 0xcb40, 0xc91c, 0xcb7f, 0xc91c, 0x21, 0 - .dw 0xcbc0, 0xc91c, 0xcbff, 0xc91c, 0x21, 0 - .dw 0xcc40, 0xc91c, 0xcc7f, 0xc91c, 0x21, 0 - .dw 0xccc0, 0xc91c, 0xccff, 0xc91c, 0x21, 0 - .dw 0xcd40, 0xc91c, 0xcd7f, 0xc91c, 0x21, 0 - .dw 0xcdc0, 0xc91c, 0xcdff, 0xc91c, 0x21, 0 - .dw 0xce40, 0xc91c, 0xce7f, 0xc91c, 0x21, 0 - .dw 0xcec0, 0xc91c, 0xceff, 0xc91c, 0x21, 0 - .dw 0xcf40, 0xc91c, 0xcf7f, 0xc91c, 0x21, 0 - .dw 0xcfc0, 0xc91c, 0xcfff, 0xc91c, 0x21, 0 - .dw 0xd040, 0xc91c, 0xd07f, 0xc91c, 0x21, 0 - .dw 0xd0c0, 0xc91c, 0xd0ff, 0xc91c, 0x21, 0 - .dw 0xd140, 0xc91c, 0xd17f, 0xc91c, 0x21, 0 - .dw 0xd1c0, 0xc91c, 0xd1ff, 0xc91c, 0x21, 0 - .dw 0xd240, 0xc91c, 0xd27f, 0xc91c, 0x21, 0 - .dw 0xd2c0, 0xc91c, 0xd2ff, 0xc91c, 0x21, 0 - .dw 0xd340, 0xc91c, 0xd37f, 0xc91c, 0x21, 0 - .dw 0xd3c0, 0xc91c, 0xd3ff, 0xc91c, 0x21, 0 - .dw 0xd440, 0xc91c, 0xd47f, 0xc91c, 0x21, 0 - .dw 0xd4c0, 0xc91c, 0xd4ff, 0xc91c, 0x21, 0 - .dw 0xd540, 0xc91c, 0xd57f, 0xc91c, 0x21, 0 - .dw 0xd5c0, 0xc91c, 0xd5ff, 0xc91c, 0x21, 0 - .dw 0xd640, 0xc91c, 0xd67f, 0xc91c, 0x21, 0 - .dw 0xd6c0, 0xc91c, 0xd6ff, 0xc91c, 0x21, 0 - .dw 0xd740, 0xc91c, 0xd77f, 0xc91c, 0x21, 0 - .dw 0xd7c0, 0xc91c, 0xd7ff, 0xc91c, 0x21, 0 - .dw 0xd840, 0xc91c, 0xd87f, 0xc91c, 0x21, 0 - .dw 0xd8c0, 0xc91c, 0xd8ff, 0xc91c, 0x21, 0 - .dw 0xd940, 0xc91c, 0xd97f, 0xc91c, 0x21, 0 - .dw 0xd9c0, 0xc91c, 0xdfff, 0xc91c, 0x21, 0 - .dw 0xe040, 0xc91c, 0xe07f, 0xc91c, 0x21, 0 - .dw 0xe0c0, 0xc91c, 0xe0ff, 0xc91c, 0x21, 0 - .dw 0xe140, 0xc91c, 0xe17f, 0xc91c, 0x21, 0 - .dw 0xe1c0, 0xc91c, 0xe1ff, 0xc91c, 0x21, 0 - .dw 0xe240, 0xc91c, 0xe27f, 0xc91c, 0x21, 0 - .dw 0xe2c0, 0xc91c, 0xe2ff, 0xc91c, 0x21, 0 - .dw 0xe340, 0xc91c, 0xe37f, 0xc91c, 0x21, 0 - .dw 0xe3c0, 0xc91c, 0xe3ff, 0xc91c, 0x21, 0 - .dw 0xe440, 0xc91c, 0xe47f, 0xc91c, 0x21, 0 - .dw 0xe4c0, 0xc91c, 0xe4ff, 0xc91c, 0x21, 0 - .dw 0xe540, 0xc91c, 0xe57f, 0xc91c, 0x21, 0 - .dw 0xe5c0, 0xc91c, 0xe5ff, 0xc91c, 0x21, 0 - .dw 0xe640, 0xc91c, 0xe67f, 0xc91c, 0x21, 0 - .dw 0xe6c0, 0xc91c, 0xe6ff, 0xc91c, 0x21, 0 - .dw 0xe740, 0xc91c, 0xe77f, 0xc91c, 0x21, 0 - .dw 0xe7c0, 0xc91c, 0xe7ff, 0xc91c, 0x21, 0 - .dw 0xe840, 0xc91c, 0xe87f, 0xc91c, 0x21, 0 - .dw 0xe8c0, 0xc91c, 0xe8ff, 0xc91c, 0x21, 0 - .dw 0xe940, 0xc91c, 0xe97f, 0xc91c, 0x21, 0 - .dw 0xe9c0, 0xc91c, 0xe9ff, 0xc91c, 0x21, 0 - .dw 0xea40, 0xc91c, 0xea7f, 0xc91c, 0x21, 0 - .dw 0xeac0, 0xc91c, 0xeaff, 0xc91c, 0x21, 0 - .dw 0xeb40, 0xc91c, 0xeb7f, 0xc91c, 0x21, 0 - .dw 0xebc0, 0xc91c, 0xebff, 0xc91c, 0x21, 0 - .dw 0xec40, 0xc91c, 0xec7f, 0xc91c, 0x21, 0 - .dw 0xecc0, 0xc91c, 0xecff, 0xc91c, 0x21, 0 - .dw 0xed40, 0xc91c, 0xed7f, 0xc91c, 0x21, 0 - .dw 0xedc0, 0xc91c, 0xedff, 0xc91c, 0x21, 0 - .dw 0xee40, 0xc91c, 0xee7f, 0xc91c, 0x21, 0 - .dw 0xeec0, 0xc91c, 0xeeff, 0xc91c, 0x21, 0 - .dw 0xef40, 0xc91c, 0xef7f, 0xc91c, 0x21, 0 - .dw 0xefc0, 0xc91c, 0xefff, 0xc91c, 0x21, 0 - .dw 0xf040, 0xc91c, 0xf07f, 0xc91c, 0x21, 0 - .dw 0xf0c0, 0xc91c, 0xf0ff, 0xc91c, 0x21, 0 - .dw 0xf140, 0xc91c, 0xf17f, 0xc91c, 0x21, 0 - .dw 0xf1c0, 0xc91c, 0xf1ff, 0xc91c, 0x21, 0 - .dw 0xf240, 0xc91c, 0xf27f, 0xc91c, 0x21, 0 - .dw 0xf2c0, 0xc91c, 0xf2ff, 0xc91c, 0x21, 0 - .dw 0xf340, 0xc91c, 0xf37f, 0xc91c, 0x21, 0 - .dw 0xf3c0, 0xc91c, 0xf3ff, 0xc91c, 0x21, 0 - .dw 0xf440, 0xc91c, 0xf47f, 0xc91c, 0x21, 0 - .dw 0xf4c0, 0xc91c, 0xf4ff, 0xc91c, 0x21, 0 - .dw 0xf540, 0xc91c, 0xf57f, 0xc91c, 0x21, 0 - .dw 0xf5c0, 0xc91c, 0xf5ff, 0xc91c, 0x21, 0 - .dw 0xf640, 0xc91c, 0xf67f, 0xc91c, 0x21, 0 - .dw 0xf6c0, 0xc91c, 0xf6ff, 0xc91c, 0x21, 0 - .dw 0xf740, 0xc91c, 0xf77f, 0xc91c, 0x21, 0 - .dw 0xf7c0, 0xc91c, 0xf7ff, 0xc91c, 0x21, 0 - .dw 0xf840, 0xc91c, 0xf87f, 0xc91c, 0x21, 0 - .dw 0xf8c0, 0xc91c, 0xf8ff, 0xc91c, 0x21, 0 - .dw 0xf940, 0xc91c, 0xf97f, 0xc91c, 0x21, 0 - .dw 0xf9c0, 0xc91c, 0xffff, 0xc91c, 0x21, 0 - .dw 0x0040, 0xc91d, 0x007f, 0xc91d, 0x21, 0 - .dw 0x00c0, 0xc91d, 0x00ff, 0xc91d, 0x21, 0 - .dw 0x0140, 0xc91d, 0x017f, 0xc91d, 0x21, 0 - .dw 0x01c0, 0xc91d, 0x01ff, 0xc91d, 0x21, 0 - .dw 0x0240, 0xc91d, 0x027f, 0xc91d, 0x21, 0 - .dw 0x02c0, 0xc91d, 0x02ff, 0xc91d, 0x21, 0 - .dw 0x0340, 0xc91d, 0x037f, 0xc91d, 0x21, 0 - .dw 0x03c0, 0xc91d, 0x03ff, 0xc91d, 0x21, 0 - .dw 0x0440, 0xc91d, 0x047f, 0xc91d, 0x21, 0 - .dw 0x04c0, 0xc91d, 0x04ff, 0xc91d, 0x21, 0 - .dw 0x0540, 0xc91d, 0x057f, 0xc91d, 0x21, 0 - .dw 0x05c0, 0xc91d, 0x05ff, 0xc91d, 0x21, 0 - .dw 0x0640, 0xc91d, 0x067f, 0xc91d, 0x21, 0 - .dw 0x06c0, 0xc91d, 0x06ff, 0xc91d, 0x21, 0 - .dw 0x0740, 0xc91d, 0x077f, 0xc91d, 0x21, 0 - .dw 0x07c0, 0xc91d, 0x07ff, 0xc91d, 0x21, 0 - .dw 0x0840, 0xc91d, 0x087f, 0xc91d, 0x21, 0 - .dw 0x08c0, 0xc91d, 0x08ff, 0xc91d, 0x21, 0 - .dw 0x0940, 0xc91d, 0x097f, 0xc91d, 0x21, 0 - .dw 0x09c0, 0xc91d, 0x09ff, 0xc91d, 0x21, 0 - .dw 0x0a40, 0xc91d, 0x0a7f, 0xc91d, 0x21, 0 - .dw 0x0ac0, 0xc91d, 0x0aff, 0xc91d, 0x21, 0 - .dw 0x0b40, 0xc91d, 0x0b7f, 0xc91d, 0x21, 0 - .dw 0x0bc0, 0xc91d, 0x0bff, 0xc91d, 0x21, 0 - .dw 0x0c40, 0xc91d, 0x0c7f, 0xc91d, 0x21, 0 - .dw 0x0cc0, 0xc91d, 0x0cff, 0xc91d, 0x21, 0 - .dw 0x0d40, 0xc91d, 0x0d7f, 0xc91d, 0x21, 0 - .dw 0x0dc0, 0xc91d, 0x0dff, 0xc91d, 0x21, 0 - .dw 0x0e40, 0xc91d, 0x0e7f, 0xc91d, 0x21, 0 - .dw 0x0ec0, 0xc91d, 0x0eff, 0xc91d, 0x21, 0 - .dw 0x0f40, 0xc91d, 0x0f7f, 0xc91d, 0x21, 0 - .dw 0x0fc0, 0xc91d, 0x0fff, 0xc91d, 0x21, 0 - .dw 0x1040, 0xc91d, 0x107f, 0xc91d, 0x21, 0 - .dw 0x10c0, 0xc91d, 0x10ff, 0xc91d, 0x21, 0 - .dw 0x1140, 0xc91d, 0x117f, 0xc91d, 0x21, 0 - .dw 0x11c0, 0xc91d, 0x11ff, 0xc91d, 0x21, 0 - .dw 0x1240, 0xc91d, 0x127f, 0xc91d, 0x21, 0 - .dw 0x12c0, 0xc91d, 0x12ff, 0xc91d, 0x21, 0 - .dw 0x1340, 0xc91d, 0x137f, 0xc91d, 0x21, 0 - .dw 0x13c0, 0xc91d, 0x13ff, 0xc91d, 0x21, 0 - .dw 0x1440, 0xc91d, 0x147f, 0xc91d, 0x21, 0 - .dw 0x14c0, 0xc91d, 0x14ff, 0xc91d, 0x21, 0 - .dw 0x1540, 0xc91d, 0x157f, 0xc91d, 0x21, 0 - .dw 0x15c0, 0xc91d, 0x15ff, 0xc91d, 0x21, 0 - .dw 0x1640, 0xc91d, 0x167f, 0xc91d, 0x21, 0 - .dw 0x16c0, 0xc91d, 0x16ff, 0xc91d, 0x21, 0 - .dw 0x1740, 0xc91d, 0x177f, 0xc91d, 0x21, 0 - .dw 0x17c0, 0xc91d, 0x17ff, 0xc91d, 0x21, 0 - .dw 0x1840, 0xc91d, 0x187f, 0xc91d, 0x21, 0 - .dw 0x18c0, 0xc91d, 0x18ff, 0xc91d, 0x21, 0 - .dw 0x1940, 0xc91d, 0x197f, 0xc91d, 0x21, 0 - .dw 0x19c0, 0xc91d, 0x1fff, 0xc91d, 0x21, 0 - .dw 0x2040, 0xc91d, 0x207f, 0xc91d, 0x21, 0 - .dw 0x20c0, 0xc91d, 0x20ff, 0xc91d, 0x21, 0 - .dw 0x2140, 0xc91d, 0x217f, 0xc91d, 0x21, 0 - .dw 0x21c0, 0xc91d, 0x21ff, 0xc91d, 0x21, 0 - .dw 0x2240, 0xc91d, 0x227f, 0xc91d, 0x21, 0 - .dw 0x22c0, 0xc91d, 0x22ff, 0xc91d, 0x21, 0 - .dw 0x2340, 0xc91d, 0x237f, 0xc91d, 0x21, 0 - .dw 0x23c0, 0xc91d, 0x23ff, 0xc91d, 0x21, 0 - .dw 0x2440, 0xc91d, 0x247f, 0xc91d, 0x21, 0 - .dw 0x24c0, 0xc91d, 0x24ff, 0xc91d, 0x21, 0 - .dw 0x2540, 0xc91d, 0x257f, 0xc91d, 0x21, 0 - .dw 0x25c0, 0xc91d, 0x25ff, 0xc91d, 0x21, 0 - .dw 0x2640, 0xc91d, 0x267f, 0xc91d, 0x21, 0 - .dw 0x26c0, 0xc91d, 0x26ff, 0xc91d, 0x21, 0 - .dw 0x2740, 0xc91d, 0x277f, 0xc91d, 0x21, 0 - .dw 0x27c0, 0xc91d, 0x27ff, 0xc91d, 0x21, 0 - .dw 0x2840, 0xc91d, 0x287f, 0xc91d, 0x21, 0 - .dw 0x28c0, 0xc91d, 0x28ff, 0xc91d, 0x21, 0 - .dw 0x2940, 0xc91d, 0x297f, 0xc91d, 0x21, 0 - .dw 0x29c0, 0xc91d, 0x29ff, 0xc91d, 0x21, 0 - .dw 0x2a40, 0xc91d, 0x2a7f, 0xc91d, 0x21, 0 - .dw 0x2ac0, 0xc91d, 0x2aff, 0xc91d, 0x21, 0 - .dw 0x2b40, 0xc91d, 0x2b7f, 0xc91d, 0x21, 0 - .dw 0x2bc0, 0xc91d, 0x2bff, 0xc91d, 0x21, 0 - .dw 0x2c40, 0xc91d, 0x2c7f, 0xc91d, 0x21, 0 - .dw 0x2cc0, 0xc91d, 0x2cff, 0xc91d, 0x21, 0 - .dw 0x2d40, 0xc91d, 0x2d7f, 0xc91d, 0x21, 0 - .dw 0x2dc0, 0xc91d, 0x2dff, 0xc91d, 0x21, 0 - .dw 0x2e40, 0xc91d, 0x2e7f, 0xc91d, 0x21, 0 - .dw 0x2ec0, 0xc91d, 0x2eff, 0xc91d, 0x21, 0 - .dw 0x2f40, 0xc91d, 0x2f7f, 0xc91d, 0x21, 0 - .dw 0x2fc0, 0xc91d, 0x2fff, 0xc91d, 0x21, 0 - .dw 0x3040, 0xc91d, 0x307f, 0xc91d, 0x21, 0 - .dw 0x30c0, 0xc91d, 0x30ff, 0xc91d, 0x21, 0 - .dw 0x3140, 0xc91d, 0x317f, 0xc91d, 0x21, 0 - .dw 0x31c0, 0xc91d, 0x31ff, 0xc91d, 0x21, 0 - .dw 0x3240, 0xc91d, 0x327f, 0xc91d, 0x21, 0 - .dw 0x32c0, 0xc91d, 0x32ff, 0xc91d, 0x21, 0 - .dw 0x3340, 0xc91d, 0x337f, 0xc91d, 0x21, 0 - .dw 0x33c0, 0xc91d, 0x33ff, 0xc91d, 0x21, 0 - .dw 0x3440, 0xc91d, 0x347f, 0xc91d, 0x21, 0 - .dw 0x34c0, 0xc91d, 0x34ff, 0xc91d, 0x21, 0 - .dw 0x3540, 0xc91d, 0x357f, 0xc91d, 0x21, 0 - .dw 0x35c0, 0xc91d, 0x35ff, 0xc91d, 0x21, 0 - .dw 0x3640, 0xc91d, 0x367f, 0xc91d, 0x21, 0 - .dw 0x36c0, 0xc91d, 0x36ff, 0xc91d, 0x21, 0 - .dw 0x3740, 0xc91d, 0x377f, 0xc91d, 0x21, 0 - .dw 0x37c0, 0xc91d, 0x37ff, 0xc91d, 0x21, 0 - .dw 0x3840, 0xc91d, 0x387f, 0xc91d, 0x21, 0 - .dw 0x38c0, 0xc91d, 0x38ff, 0xc91d, 0x21, 0 - .dw 0x3940, 0xc91d, 0x397f, 0xc91d, 0x21, 0 - .dw 0x39c0, 0xc91d, 0x3fff, 0xc91d, 0x21, 0 - .dw 0x4040, 0xc91d, 0x407f, 0xc91d, 0x21, 0 - .dw 0x40c0, 0xc91d, 0x40ff, 0xc91d, 0x21, 0 - .dw 0x4140, 0xc91d, 0x417f, 0xc91d, 0x21, 0 - .dw 0x41c0, 0xc91d, 0x41ff, 0xc91d, 0x21, 0 - .dw 0x4240, 0xc91d, 0x427f, 0xc91d, 0x21, 0 - .dw 0x42c0, 0xc91d, 0x42ff, 0xc91d, 0x21, 0 - .dw 0x4340, 0xc91d, 0x437f, 0xc91d, 0x21, 0 - .dw 0x43c0, 0xc91d, 0x43ff, 0xc91d, 0x21, 0 - .dw 0x4440, 0xc91d, 0x447f, 0xc91d, 0x21, 0 - .dw 0x44c0, 0xc91d, 0x44ff, 0xc91d, 0x21, 0 - .dw 0x4540, 0xc91d, 0x457f, 0xc91d, 0x21, 0 - .dw 0x45c0, 0xc91d, 0x45ff, 0xc91d, 0x21, 0 - .dw 0x4640, 0xc91d, 0x467f, 0xc91d, 0x21, 0 - .dw 0x46c0, 0xc91d, 0x46ff, 0xc91d, 0x21, 0 - .dw 0x4740, 0xc91d, 0x477f, 0xc91d, 0x21, 0 - .dw 0x47c0, 0xc91d, 0x47ff, 0xc91d, 0x21, 0 - .dw 0x4840, 0xc91d, 0x487f, 0xc91d, 0x21, 0 - .dw 0x48c0, 0xc91d, 0x48ff, 0xc91d, 0x21, 0 - .dw 0x4940, 0xc91d, 0x497f, 0xc91d, 0x21, 0 - .dw 0x49c0, 0xc91d, 0x49ff, 0xc91d, 0x21, 0 - .dw 0x4a40, 0xc91d, 0x4a7f, 0xc91d, 0x21, 0 - .dw 0x4ac0, 0xc91d, 0x4aff, 0xc91d, 0x21, 0 - .dw 0x4b40, 0xc91d, 0x4b7f, 0xc91d, 0x21, 0 - .dw 0x4bc0, 0xc91d, 0x4bff, 0xc91d, 0x21, 0 - .dw 0x4c40, 0xc91d, 0x4c7f, 0xc91d, 0x21, 0 - .dw 0x4cc0, 0xc91d, 0x4cff, 0xc91d, 0x21, 0 - .dw 0x4d40, 0xc91d, 0x4d7f, 0xc91d, 0x21, 0 - .dw 0x4dc0, 0xc91d, 0x4dff, 0xc91d, 0x21, 0 - .dw 0x4e40, 0xc91d, 0x4e7f, 0xc91d, 0x21, 0 - .dw 0x4ec0, 0xc91d, 0x4eff, 0xc91d, 0x21, 0 - .dw 0x4f40, 0xc91d, 0x4f7f, 0xc91d, 0x21, 0 - .dw 0x4fc0, 0xc91d, 0x4fff, 0xc91d, 0x21, 0 - .dw 0x5040, 0xc91d, 0x507f, 0xc91d, 0x21, 0 - .dw 0x50c0, 0xc91d, 0x50ff, 0xc91d, 0x21, 0 - .dw 0x5140, 0xc91d, 0x517f, 0xc91d, 0x21, 0 - .dw 0x51c0, 0xc91d, 0x51ff, 0xc91d, 0x21, 0 - .dw 0x5240, 0xc91d, 0x527f, 0xc91d, 0x21, 0 - .dw 0x52c0, 0xc91d, 0x52ff, 0xc91d, 0x21, 0 - .dw 0x5340, 0xc91d, 0x537f, 0xc91d, 0x21, 0 - .dw 0x53c0, 0xc91d, 0x53ff, 0xc91d, 0x21, 0 - .dw 0x5440, 0xc91d, 0x547f, 0xc91d, 0x21, 0 - .dw 0x54c0, 0xc91d, 0x54ff, 0xc91d, 0x21, 0 - .dw 0x5540, 0xc91d, 0x557f, 0xc91d, 0x21, 0 - .dw 0x55c0, 0xc91d, 0x55ff, 0xc91d, 0x21, 0 - .dw 0x5640, 0xc91d, 0x567f, 0xc91d, 0x21, 0 - .dw 0x56c0, 0xc91d, 0x56ff, 0xc91d, 0x21, 0 - .dw 0x5740, 0xc91d, 0x577f, 0xc91d, 0x21, 0 - .dw 0x57c0, 0xc91d, 0x57ff, 0xc91d, 0x21, 0 - .dw 0x5840, 0xc91d, 0x587f, 0xc91d, 0x21, 0 - .dw 0x58c0, 0xc91d, 0x58ff, 0xc91d, 0x21, 0 - .dw 0x5940, 0xc91d, 0x597f, 0xc91d, 0x21, 0 - .dw 0x59c0, 0xc91d, 0x5fff, 0xc91d, 0x21, 0 - .dw 0x6040, 0xc91d, 0x607f, 0xc91d, 0x21, 0 - .dw 0x60c0, 0xc91d, 0x60ff, 0xc91d, 0x21, 0 - .dw 0x6140, 0xc91d, 0x617f, 0xc91d, 0x21, 0 - .dw 0x61c0, 0xc91d, 0x61ff, 0xc91d, 0x21, 0 - .dw 0x6240, 0xc91d, 0x627f, 0xc91d, 0x21, 0 - .dw 0x62c0, 0xc91d, 0x62ff, 0xc91d, 0x21, 0 - .dw 0x6340, 0xc91d, 0x637f, 0xc91d, 0x21, 0 - .dw 0x63c0, 0xc91d, 0x63ff, 0xc91d, 0x21, 0 - .dw 0x6440, 0xc91d, 0x647f, 0xc91d, 0x21, 0 - .dw 0x64c0, 0xc91d, 0x64ff, 0xc91d, 0x21, 0 - .dw 0x6540, 0xc91d, 0x657f, 0xc91d, 0x21, 0 - .dw 0x65c0, 0xc91d, 0x65ff, 0xc91d, 0x21, 0 - .dw 0x6640, 0xc91d, 0x667f, 0xc91d, 0x21, 0 - .dw 0x66c0, 0xc91d, 0x66ff, 0xc91d, 0x21, 0 - .dw 0x6740, 0xc91d, 0x677f, 0xc91d, 0x21, 0 - .dw 0x67c0, 0xc91d, 0x67ff, 0xc91d, 0x21, 0 - .dw 0x6840, 0xc91d, 0x687f, 0xc91d, 0x21, 0 - .dw 0x68c0, 0xc91d, 0x68ff, 0xc91d, 0x21, 0 - .dw 0x6940, 0xc91d, 0x697f, 0xc91d, 0x21, 0 - .dw 0x69c0, 0xc91d, 0x69ff, 0xc91d, 0x21, 0 - .dw 0x6a40, 0xc91d, 0x6a7f, 0xc91d, 0x21, 0 - .dw 0x6ac0, 0xc91d, 0x6aff, 0xc91d, 0x21, 0 - .dw 0x6b40, 0xc91d, 0x6b7f, 0xc91d, 0x21, 0 - .dw 0x6bc0, 0xc91d, 0x6bff, 0xc91d, 0x21, 0 - .dw 0x6c40, 0xc91d, 0x6c7f, 0xc91d, 0x21, 0 - .dw 0x6cc0, 0xc91d, 0x6cff, 0xc91d, 0x21, 0 - .dw 0x6d40, 0xc91d, 0x6d7f, 0xc91d, 0x21, 0 - .dw 0x6dc0, 0xc91d, 0x6dff, 0xc91d, 0x21, 0 - .dw 0x6e40, 0xc91d, 0x6e7f, 0xc91d, 0x21, 0 - .dw 0x6ec0, 0xc91d, 0x6eff, 0xc91d, 0x21, 0 - .dw 0x6f40, 0xc91d, 0x6f7f, 0xc91d, 0x21, 0 - .dw 0x6fc0, 0xc91d, 0x6fff, 0xc91d, 0x21, 0 - .dw 0x7040, 0xc91d, 0x707f, 0xc91d, 0x21, 0 - .dw 0x70c0, 0xc91d, 0x70ff, 0xc91d, 0x21, 0 - .dw 0x7140, 0xc91d, 0x717f, 0xc91d, 0x21, 0 - .dw 0x71c0, 0xc91d, 0x71ff, 0xc91d, 0x21, 0 - .dw 0x7240, 0xc91d, 0x727f, 0xc91d, 0x21, 0 - .dw 0x72c0, 0xc91d, 0x72ff, 0xc91d, 0x21, 0 - .dw 0x7340, 0xc91d, 0x737f, 0xc91d, 0x21, 0 - .dw 0x73c0, 0xc91d, 0x73ff, 0xc91d, 0x21, 0 - .dw 0x7440, 0xc91d, 0x747f, 0xc91d, 0x21, 0 - .dw 0x74c0, 0xc91d, 0x74ff, 0xc91d, 0x21, 0 - .dw 0x7540, 0xc91d, 0x757f, 0xc91d, 0x21, 0 - .dw 0x75c0, 0xc91d, 0x75ff, 0xc91d, 0x21, 0 - .dw 0x7640, 0xc91d, 0x767f, 0xc91d, 0x21, 0 - .dw 0x76c0, 0xc91d, 0x76ff, 0xc91d, 0x21, 0 - .dw 0x7740, 0xc91d, 0x777f, 0xc91d, 0x21, 0 - .dw 0x77c0, 0xc91d, 0x77ff, 0xc91d, 0x21, 0 - .dw 0x7840, 0xc91d, 0x787f, 0xc91d, 0x21, 0 - .dw 0x78c0, 0xc91d, 0x78ff, 0xc91d, 0x21, 0 - .dw 0x7940, 0xc91d, 0x797f, 0xc91d, 0x21, 0 - .dw 0x79c0, 0xc91d, 0x7fff, 0xc91d, 0x21, 0 - .dw 0x8040, 0xc91d, 0x807f, 0xc91d, 0x21, 0 - .dw 0x80c0, 0xc91d, 0x80ff, 0xc91d, 0x21, 0 - .dw 0x8140, 0xc91d, 0x817f, 0xc91d, 0x21, 0 - .dw 0x81c0, 0xc91d, 0x81ff, 0xc91d, 0x21, 0 - .dw 0x8240, 0xc91d, 0x827f, 0xc91d, 0x21, 0 - .dw 0x82c0, 0xc91d, 0x82ff, 0xc91d, 0x21, 0 - .dw 0x8340, 0xc91d, 0x837f, 0xc91d, 0x21, 0 - .dw 0x83c0, 0xc91d, 0x83ff, 0xc91d, 0x21, 0 - .dw 0x8440, 0xc91d, 0x847f, 0xc91d, 0x21, 0 - .dw 0x84c0, 0xc91d, 0x84ff, 0xc91d, 0x21, 0 - .dw 0x8540, 0xc91d, 0x857f, 0xc91d, 0x21, 0 - .dw 0x85c0, 0xc91d, 0x85ff, 0xc91d, 0x21, 0 - .dw 0x8640, 0xc91d, 0x867f, 0xc91d, 0x21, 0 - .dw 0x86c0, 0xc91d, 0x86ff, 0xc91d, 0x21, 0 - .dw 0x8740, 0xc91d, 0x877f, 0xc91d, 0x21, 0 - .dw 0x87c0, 0xc91d, 0x87ff, 0xc91d, 0x21, 0 - .dw 0x8840, 0xc91d, 0x887f, 0xc91d, 0x21, 0 - .dw 0x88c0, 0xc91d, 0x88ff, 0xc91d, 0x21, 0 - .dw 0x8940, 0xc91d, 0x897f, 0xc91d, 0x21, 0 - .dw 0x89c0, 0xc91d, 0x89ff, 0xc91d, 0x21, 0 - .dw 0x8a40, 0xc91d, 0x8a7f, 0xc91d, 0x21, 0 - .dw 0x8ac0, 0xc91d, 0x8aff, 0xc91d, 0x21, 0 - .dw 0x8b40, 0xc91d, 0x8b7f, 0xc91d, 0x21, 0 - .dw 0x8bc0, 0xc91d, 0x8bff, 0xc91d, 0x21, 0 - .dw 0x8c40, 0xc91d, 0x8c7f, 0xc91d, 0x21, 0 - .dw 0x8cc0, 0xc91d, 0x8cff, 0xc91d, 0x21, 0 - .dw 0x8d40, 0xc91d, 0x8d7f, 0xc91d, 0x21, 0 - .dw 0x8dc0, 0xc91d, 0x8dff, 0xc91d, 0x21, 0 - .dw 0x8e40, 0xc91d, 0x8e7f, 0xc91d, 0x21, 0 - .dw 0x8ec0, 0xc91d, 0x8eff, 0xc91d, 0x21, 0 - .dw 0x8f40, 0xc91d, 0x8f7f, 0xc91d, 0x21, 0 - .dw 0x8fc0, 0xc91d, 0x8fff, 0xc91d, 0x21, 0 - .dw 0x9040, 0xc91d, 0x907f, 0xc91d, 0x21, 0 - .dw 0x90c0, 0xc91d, 0x90ff, 0xc91d, 0x21, 0 - .dw 0x9140, 0xc91d, 0x917f, 0xc91d, 0x21, 0 - .dw 0x91c0, 0xc91d, 0x91ff, 0xc91d, 0x21, 0 - .dw 0x9240, 0xc91d, 0x927f, 0xc91d, 0x21, 0 - .dw 0x92c0, 0xc91d, 0x92ff, 0xc91d, 0x21, 0 - .dw 0x9340, 0xc91d, 0x937f, 0xc91d, 0x21, 0 - .dw 0x93c0, 0xc91d, 0x93ff, 0xc91d, 0x21, 0 - .dw 0x9440, 0xc91d, 0x947f, 0xc91d, 0x21, 0 - .dw 0x94c0, 0xc91d, 0x94ff, 0xc91d, 0x21, 0 - .dw 0x9540, 0xc91d, 0x957f, 0xc91d, 0x21, 0 - .dw 0x95c0, 0xc91d, 0x95ff, 0xc91d, 0x21, 0 - .dw 0x9640, 0xc91d, 0x967f, 0xc91d, 0x21, 0 - .dw 0x96c0, 0xc91d, 0x96ff, 0xc91d, 0x21, 0 - .dw 0x9740, 0xc91d, 0x977f, 0xc91d, 0x21, 0 - .dw 0x97c0, 0xc91d, 0x97ff, 0xc91d, 0x21, 0 - .dw 0x9840, 0xc91d, 0x987f, 0xc91d, 0x21, 0 - .dw 0x98c0, 0xc91d, 0x98ff, 0xc91d, 0x21, 0 - .dw 0x9940, 0xc91d, 0x997f, 0xc91d, 0x21, 0 - .dw 0x99c0, 0xc91d, 0x9fff, 0xc91d, 0x21, 0 - .dw 0xa040, 0xc91d, 0xa07f, 0xc91d, 0x21, 0 - .dw 0xa0c0, 0xc91d, 0xa0ff, 0xc91d, 0x21, 0 - .dw 0xa140, 0xc91d, 0xa17f, 0xc91d, 0x21, 0 - .dw 0xa1c0, 0xc91d, 0xa1ff, 0xc91d, 0x21, 0 - .dw 0xa240, 0xc91d, 0xa27f, 0xc91d, 0x21, 0 - .dw 0xa2c0, 0xc91d, 0xa2ff, 0xc91d, 0x21, 0 - .dw 0xa340, 0xc91d, 0xa37f, 0xc91d, 0x21, 0 - .dw 0xa3c0, 0xc91d, 0xa3ff, 0xc91d, 0x21, 0 - .dw 0xa440, 0xc91d, 0xa47f, 0xc91d, 0x21, 0 - .dw 0xa4c0, 0xc91d, 0xa4ff, 0xc91d, 0x21, 0 - .dw 0xa540, 0xc91d, 0xa57f, 0xc91d, 0x21, 0 - .dw 0xa5c0, 0xc91d, 0xa5ff, 0xc91d, 0x21, 0 - .dw 0xa640, 0xc91d, 0xa67f, 0xc91d, 0x21, 0 - .dw 0xa6c0, 0xc91d, 0xa6ff, 0xc91d, 0x21, 0 - .dw 0xa740, 0xc91d, 0xa77f, 0xc91d, 0x21, 0 - .dw 0xa7c0, 0xc91d, 0xa7ff, 0xc91d, 0x21, 0 - .dw 0xa840, 0xc91d, 0xa87f, 0xc91d, 0x21, 0 - .dw 0xa8c0, 0xc91d, 0xa8ff, 0xc91d, 0x21, 0 - .dw 0xa940, 0xc91d, 0xa97f, 0xc91d, 0x21, 0 - .dw 0xa9c0, 0xc91d, 0xa9ff, 0xc91d, 0x21, 0 - .dw 0xaa40, 0xc91d, 0xaa7f, 0xc91d, 0x21, 0 - .dw 0xaac0, 0xc91d, 0xaaff, 0xc91d, 0x21, 0 - .dw 0xab40, 0xc91d, 0xab7f, 0xc91d, 0x21, 0 - .dw 0xabc0, 0xc91d, 0xabff, 0xc91d, 0x21, 0 - .dw 0xac40, 0xc91d, 0xac7f, 0xc91d, 0x21, 0 - .dw 0xacc0, 0xc91d, 0xacff, 0xc91d, 0x21, 0 - .dw 0xad40, 0xc91d, 0xad7f, 0xc91d, 0x21, 0 - .dw 0xadc0, 0xc91d, 0xadff, 0xc91d, 0x21, 0 - .dw 0xae40, 0xc91d, 0xae7f, 0xc91d, 0x21, 0 - .dw 0xaec0, 0xc91d, 0xaeff, 0xc91d, 0x21, 0 - .dw 0xaf40, 0xc91d, 0xaf7f, 0xc91d, 0x21, 0 - .dw 0xafc0, 0xc91d, 0xafff, 0xc91d, 0x21, 0 - .dw 0xb040, 0xc91d, 0xb07f, 0xc91d, 0x21, 0 - .dw 0xb0c0, 0xc91d, 0xb0ff, 0xc91d, 0x21, 0 - .dw 0xb140, 0xc91d, 0xb17f, 0xc91d, 0x21, 0 - .dw 0xb1c0, 0xc91d, 0xb1ff, 0xc91d, 0x21, 0 - .dw 0xb240, 0xc91d, 0xb27f, 0xc91d, 0x21, 0 - .dw 0xb2c0, 0xc91d, 0xb2ff, 0xc91d, 0x21, 0 - .dw 0xb340, 0xc91d, 0xb37f, 0xc91d, 0x21, 0 - .dw 0xb3c0, 0xc91d, 0xb3ff, 0xc91d, 0x21, 0 - .dw 0xb440, 0xc91d, 0xb47f, 0xc91d, 0x21, 0 - .dw 0xb4c0, 0xc91d, 0xb4ff, 0xc91d, 0x21, 0 - .dw 0xb540, 0xc91d, 0xb57f, 0xc91d, 0x21, 0 - .dw 0xb5c0, 0xc91d, 0xb5ff, 0xc91d, 0x21, 0 - .dw 0xb640, 0xc91d, 0xb67f, 0xc91d, 0x21, 0 - .dw 0xb6c0, 0xc91d, 0xb6ff, 0xc91d, 0x21, 0 - .dw 0xb740, 0xc91d, 0xb77f, 0xc91d, 0x21, 0 - .dw 0xb7c0, 0xc91d, 0xb7ff, 0xc91d, 0x21, 0 - .dw 0xb840, 0xc91d, 0xb87f, 0xc91d, 0x21, 0 - .dw 0xb8c0, 0xc91d, 0xb8ff, 0xc91d, 0x21, 0 - .dw 0xb940, 0xc91d, 0xb97f, 0xc91d, 0x21, 0 - .dw 0xb9c0, 0xc91d, 0xbfff, 0xc91d, 0x21, 0 - .dw 0xc040, 0xc91d, 0xc07f, 0xc91d, 0x21, 0 - .dw 0xc0c0, 0xc91d, 0xc0ff, 0xc91d, 0x21, 0 - .dw 0xc140, 0xc91d, 0xc17f, 0xc91d, 0x21, 0 - .dw 0xc1c0, 0xc91d, 0xc1ff, 0xc91d, 0x21, 0 - .dw 0xc240, 0xc91d, 0xc27f, 0xc91d, 0x21, 0 - .dw 0xc2c0, 0xc91d, 0xc2ff, 0xc91d, 0x21, 0 - .dw 0xc340, 0xc91d, 0xc37f, 0xc91d, 0x21, 0 - .dw 0xc3c0, 0xc91d, 0xc3ff, 0xc91d, 0x21, 0 - .dw 0xc440, 0xc91d, 0xc47f, 0xc91d, 0x21, 0 - .dw 0xc4c0, 0xc91d, 0xc4ff, 0xc91d, 0x21, 0 - .dw 0xc540, 0xc91d, 0xc57f, 0xc91d, 0x21, 0 - .dw 0xc5c0, 0xc91d, 0xc5ff, 0xc91d, 0x21, 0 - .dw 0xc640, 0xc91d, 0xc67f, 0xc91d, 0x21, 0 - .dw 0xc6c0, 0xc91d, 0xc6ff, 0xc91d, 0x21, 0 - .dw 0xc740, 0xc91d, 0xc77f, 0xc91d, 0x21, 0 - .dw 0xc7c0, 0xc91d, 0xc7ff, 0xc91d, 0x21, 0 - .dw 0xc840, 0xc91d, 0xc87f, 0xc91d, 0x21, 0 - .dw 0xc8c0, 0xc91d, 0xc8ff, 0xc91d, 0x21, 0 - .dw 0xc940, 0xc91d, 0xc97f, 0xc91d, 0x21, 0 - .dw 0xc9c0, 0xc91d, 0xc9ff, 0xc91d, 0x21, 0 - .dw 0xca40, 0xc91d, 0xca7f, 0xc91d, 0x21, 0 - .dw 0xcac0, 0xc91d, 0xcaff, 0xc91d, 0x21, 0 - .dw 0xcb40, 0xc91d, 0xcb7f, 0xc91d, 0x21, 0 - .dw 0xcbc0, 0xc91d, 0xcbff, 0xc91d, 0x21, 0 - .dw 0xcc40, 0xc91d, 0xcc7f, 0xc91d, 0x21, 0 - .dw 0xccc0, 0xc91d, 0xccff, 0xc91d, 0x21, 0 - .dw 0xcd40, 0xc91d, 0xcd7f, 0xc91d, 0x21, 0 - .dw 0xcdc0, 0xc91d, 0xcdff, 0xc91d, 0x21, 0 - .dw 0xce40, 0xc91d, 0xce7f, 0xc91d, 0x21, 0 - .dw 0xcec0, 0xc91d, 0xceff, 0xc91d, 0x21, 0 - .dw 0xcf40, 0xc91d, 0xcf7f, 0xc91d, 0x21, 0 - .dw 0xcfc0, 0xc91d, 0xcfff, 0xc91d, 0x21, 0 - .dw 0xd040, 0xc91d, 0xd07f, 0xc91d, 0x21, 0 - .dw 0xd0c0, 0xc91d, 0xd0ff, 0xc91d, 0x21, 0 - .dw 0xd140, 0xc91d, 0xd17f, 0xc91d, 0x21, 0 - .dw 0xd1c0, 0xc91d, 0xd1ff, 0xc91d, 0x21, 0 - .dw 0xd240, 0xc91d, 0xd27f, 0xc91d, 0x21, 0 - .dw 0xd2c0, 0xc91d, 0xd2ff, 0xc91d, 0x21, 0 - .dw 0xd340, 0xc91d, 0xd37f, 0xc91d, 0x21, 0 - .dw 0xd3c0, 0xc91d, 0xd3ff, 0xc91d, 0x21, 0 - .dw 0xd440, 0xc91d, 0xd47f, 0xc91d, 0x21, 0 - .dw 0xd4c0, 0xc91d, 0xd4ff, 0xc91d, 0x21, 0 - .dw 0xd540, 0xc91d, 0xd57f, 0xc91d, 0x21, 0 - .dw 0xd5c0, 0xc91d, 0xd5ff, 0xc91d, 0x21, 0 - .dw 0xd640, 0xc91d, 0xd67f, 0xc91d, 0x21, 0 - .dw 0xd6c0, 0xc91d, 0xd6ff, 0xc91d, 0x21, 0 - .dw 0xd740, 0xc91d, 0xd77f, 0xc91d, 0x21, 0 - .dw 0xd7c0, 0xc91d, 0xd7ff, 0xc91d, 0x21, 0 - .dw 0xd840, 0xc91d, 0xd87f, 0xc91d, 0x21, 0 - .dw 0xd8c0, 0xc91d, 0xd8ff, 0xc91d, 0x21, 0 - .dw 0xd940, 0xc91d, 0xd97f, 0xc91d, 0x21, 0 - .dw 0xd9c0, 0xc91d, 0xdfff, 0xc91d, 0x21, 0 - .dw 0xe040, 0xc91d, 0xe07f, 0xc91d, 0x21, 0 - .dw 0xe0c0, 0xc91d, 0xe0ff, 0xc91d, 0x21, 0 - .dw 0xe140, 0xc91d, 0xe17f, 0xc91d, 0x21, 0 - .dw 0xe1c0, 0xc91d, 0xe1ff, 0xc91d, 0x21, 0 - .dw 0xe240, 0xc91d, 0xe27f, 0xc91d, 0x21, 0 - .dw 0xe2c0, 0xc91d, 0xe2ff, 0xc91d, 0x21, 0 - .dw 0xe340, 0xc91d, 0xe37f, 0xc91d, 0x21, 0 - .dw 0xe3c0, 0xc91d, 0xe3ff, 0xc91d, 0x21, 0 - .dw 0xe440, 0xc91d, 0xe47f, 0xc91d, 0x21, 0 - .dw 0xe4c0, 0xc91d, 0xe4ff, 0xc91d, 0x21, 0 - .dw 0xe540, 0xc91d, 0xe57f, 0xc91d, 0x21, 0 - .dw 0xe5c0, 0xc91d, 0xe5ff, 0xc91d, 0x21, 0 - .dw 0xe640, 0xc91d, 0xe67f, 0xc91d, 0x21, 0 - .dw 0xe6c0, 0xc91d, 0xe6ff, 0xc91d, 0x21, 0 - .dw 0xe740, 0xc91d, 0xe77f, 0xc91d, 0x21, 0 - .dw 0xe7c0, 0xc91d, 0xe7ff, 0xc91d, 0x21, 0 - .dw 0xe840, 0xc91d, 0xe87f, 0xc91d, 0x21, 0 - .dw 0xe8c0, 0xc91d, 0xe8ff, 0xc91d, 0x21, 0 - .dw 0xe940, 0xc91d, 0xe97f, 0xc91d, 0x21, 0 - .dw 0xe9c0, 0xc91d, 0xe9ff, 0xc91d, 0x21, 0 - .dw 0xea40, 0xc91d, 0xea7f, 0xc91d, 0x21, 0 - .dw 0xeac0, 0xc91d, 0xeaff, 0xc91d, 0x21, 0 - .dw 0xeb40, 0xc91d, 0xeb7f, 0xc91d, 0x21, 0 - .dw 0xebc0, 0xc91d, 0xebff, 0xc91d, 0x21, 0 - .dw 0xec40, 0xc91d, 0xec7f, 0xc91d, 0x21, 0 - .dw 0xecc0, 0xc91d, 0xecff, 0xc91d, 0x21, 0 - .dw 0xed40, 0xc91d, 0xed7f, 0xc91d, 0x21, 0 - .dw 0xedc0, 0xc91d, 0xedff, 0xc91d, 0x21, 0 - .dw 0xee40, 0xc91d, 0xee7f, 0xc91d, 0x21, 0 - .dw 0xeec0, 0xc91d, 0xeeff, 0xc91d, 0x21, 0 - .dw 0xef40, 0xc91d, 0xef7f, 0xc91d, 0x21, 0 - .dw 0xefc0, 0xc91d, 0xefff, 0xc91d, 0x21, 0 - .dw 0xf040, 0xc91d, 0xf07f, 0xc91d, 0x21, 0 - .dw 0xf0c0, 0xc91d, 0xf0ff, 0xc91d, 0x21, 0 - .dw 0xf140, 0xc91d, 0xf17f, 0xc91d, 0x21, 0 - .dw 0xf1c0, 0xc91d, 0xf1ff, 0xc91d, 0x21, 0 - .dw 0xf240, 0xc91d, 0xf27f, 0xc91d, 0x21, 0 - .dw 0xf2c0, 0xc91d, 0xf2ff, 0xc91d, 0x21, 0 - .dw 0xf340, 0xc91d, 0xf37f, 0xc91d, 0x21, 0 - .dw 0xf3c0, 0xc91d, 0xf3ff, 0xc91d, 0x21, 0 - .dw 0xf440, 0xc91d, 0xf47f, 0xc91d, 0x21, 0 - .dw 0xf4c0, 0xc91d, 0xf4ff, 0xc91d, 0x21, 0 - .dw 0xf540, 0xc91d, 0xf57f, 0xc91d, 0x21, 0 - .dw 0xf5c0, 0xc91d, 0xf5ff, 0xc91d, 0x21, 0 - .dw 0xf640, 0xc91d, 0xf67f, 0xc91d, 0x21, 0 - .dw 0xf6c0, 0xc91d, 0xf6ff, 0xc91d, 0x21, 0 - .dw 0xf740, 0xc91d, 0xf77f, 0xc91d, 0x21, 0 - .dw 0xf7c0, 0xc91d, 0xf7ff, 0xc91d, 0x21, 0 - .dw 0xf840, 0xc91d, 0xf87f, 0xc91d, 0x21, 0 - .dw 0xf8c0, 0xc91d, 0xf8ff, 0xc91d, 0x21, 0 - .dw 0xf940, 0xc91d, 0xf97f, 0xc91d, 0x21, 0 - .dw 0xf9c0, 0xc91d, 0xffff, 0xc91d, 0x21, 0 - .dw 0x0040, 0xc91e, 0x007f, 0xc91e, 0x21, 0 - .dw 0x00c0, 0xc91e, 0x00ff, 0xc91e, 0x21, 0 - .dw 0x0140, 0xc91e, 0x017f, 0xc91e, 0x21, 0 - .dw 0x01c0, 0xc91e, 0x01ff, 0xc91e, 0x21, 0 - .dw 0x0240, 0xc91e, 0x027f, 0xc91e, 0x21, 0 - .dw 0x02c0, 0xc91e, 0x02ff, 0xc91e, 0x21, 0 - .dw 0x0340, 0xc91e, 0x037f, 0xc91e, 0x21, 0 - .dw 0x03c0, 0xc91e, 0x03ff, 0xc91e, 0x21, 0 - .dw 0x0440, 0xc91e, 0x047f, 0xc91e, 0x21, 0 - .dw 0x04c0, 0xc91e, 0x04ff, 0xc91e, 0x21, 0 - .dw 0x0540, 0xc91e, 0x057f, 0xc91e, 0x21, 0 - .dw 0x05c0, 0xc91e, 0x05ff, 0xc91e, 0x21, 0 - .dw 0x0640, 0xc91e, 0x067f, 0xc91e, 0x21, 0 - .dw 0x06c0, 0xc91e, 0x06ff, 0xc91e, 0x21, 0 - .dw 0x0740, 0xc91e, 0x077f, 0xc91e, 0x21, 0 - .dw 0x07c0, 0xc91e, 0x07ff, 0xc91e, 0x21, 0 - .dw 0x0840, 0xc91e, 0x087f, 0xc91e, 0x21, 0 - .dw 0x08c0, 0xc91e, 0x08ff, 0xc91e, 0x21, 0 - .dw 0x0940, 0xc91e, 0x097f, 0xc91e, 0x21, 0 - .dw 0x09c0, 0xc91e, 0x09ff, 0xc91e, 0x21, 0 - .dw 0x0a40, 0xc91e, 0x0a7f, 0xc91e, 0x21, 0 - .dw 0x0ac0, 0xc91e, 0x0aff, 0xc91e, 0x21, 0 - .dw 0x0b40, 0xc91e, 0x0b7f, 0xc91e, 0x21, 0 - .dw 0x0bc0, 0xc91e, 0x0bff, 0xc91e, 0x21, 0 - .dw 0x0c40, 0xc91e, 0x0c7f, 0xc91e, 0x21, 0 - .dw 0x0cc0, 0xc91e, 0x0cff, 0xc91e, 0x21, 0 - .dw 0x0d40, 0xc91e, 0x0d7f, 0xc91e, 0x21, 0 - .dw 0x0dc0, 0xc91e, 0x0dff, 0xc91e, 0x21, 0 - .dw 0x0e40, 0xc91e, 0x0e7f, 0xc91e, 0x21, 0 - .dw 0x0ec0, 0xc91e, 0x0eff, 0xc91e, 0x21, 0 - .dw 0x0f40, 0xc91e, 0x0f7f, 0xc91e, 0x21, 0 - .dw 0x0fc0, 0xc91e, 0x0fff, 0xc91e, 0x21, 0 - .dw 0x1040, 0xc91e, 0x107f, 0xc91e, 0x21, 0 - .dw 0x10c0, 0xc91e, 0x10ff, 0xc91e, 0x21, 0 - .dw 0x1140, 0xc91e, 0x117f, 0xc91e, 0x21, 0 - .dw 0x11c0, 0xc91e, 0x11ff, 0xc91e, 0x21, 0 - .dw 0x1240, 0xc91e, 0x127f, 0xc91e, 0x21, 0 - .dw 0x12c0, 0xc91e, 0x12ff, 0xc91e, 0x21, 0 - .dw 0x1340, 0xc91e, 0x137f, 0xc91e, 0x21, 0 - .dw 0x13c0, 0xc91e, 0x13ff, 0xc91e, 0x21, 0 - .dw 0x1440, 0xc91e, 0x147f, 0xc91e, 0x21, 0 - .dw 0x14c0, 0xc91e, 0x14ff, 0xc91e, 0x21, 0 - .dw 0x1540, 0xc91e, 0x157f, 0xc91e, 0x21, 0 - .dw 0x15c0, 0xc91e, 0x15ff, 0xc91e, 0x21, 0 - .dw 0x1640, 0xc91e, 0x167f, 0xc91e, 0x21, 0 - .dw 0x16c0, 0xc91e, 0x16ff, 0xc91e, 0x21, 0 - .dw 0x1740, 0xc91e, 0x177f, 0xc91e, 0x21, 0 - .dw 0x17c0, 0xc91e, 0x17ff, 0xc91e, 0x21, 0 - .dw 0x1840, 0xc91e, 0x187f, 0xc91e, 0x21, 0 - .dw 0x18c0, 0xc91e, 0x18ff, 0xc91e, 0x21, 0 - .dw 0x1940, 0xc91e, 0x197f, 0xc91e, 0x21, 0 - .dw 0x19c0, 0xc91e, 0x1fff, 0xc91e, 0x21, 0 - .dw 0x2040, 0xc91e, 0x207f, 0xc91e, 0x21, 0 - .dw 0x20c0, 0xc91e, 0x20ff, 0xc91e, 0x21, 0 - .dw 0x2140, 0xc91e, 0x217f, 0xc91e, 0x21, 0 - .dw 0x21c0, 0xc91e, 0x21ff, 0xc91e, 0x21, 0 - .dw 0x2240, 0xc91e, 0x227f, 0xc91e, 0x21, 0 - .dw 0x22c0, 0xc91e, 0x22ff, 0xc91e, 0x21, 0 - .dw 0x2340, 0xc91e, 0x237f, 0xc91e, 0x21, 0 - .dw 0x23c0, 0xc91e, 0x23ff, 0xc91e, 0x21, 0 - .dw 0x2440, 0xc91e, 0x247f, 0xc91e, 0x21, 0 - .dw 0x24c0, 0xc91e, 0x24ff, 0xc91e, 0x21, 0 - .dw 0x2540, 0xc91e, 0x257f, 0xc91e, 0x21, 0 - .dw 0x25c0, 0xc91e, 0x25ff, 0xc91e, 0x21, 0 - .dw 0x2640, 0xc91e, 0x267f, 0xc91e, 0x21, 0 - .dw 0x26c0, 0xc91e, 0x26ff, 0xc91e, 0x21, 0 - .dw 0x2740, 0xc91e, 0x277f, 0xc91e, 0x21, 0 - .dw 0x27c0, 0xc91e, 0x27ff, 0xc91e, 0x21, 0 - .dw 0x2840, 0xc91e, 0x287f, 0xc91e, 0x21, 0 - .dw 0x28c0, 0xc91e, 0x28ff, 0xc91e, 0x21, 0 - .dw 0x2940, 0xc91e, 0x297f, 0xc91e, 0x21, 0 - .dw 0x29c0, 0xc91e, 0x29ff, 0xc91e, 0x21, 0 - .dw 0x2a40, 0xc91e, 0x2a7f, 0xc91e, 0x21, 0 - .dw 0x2ac0, 0xc91e, 0x2aff, 0xc91e, 0x21, 0 - .dw 0x2b40, 0xc91e, 0x2b7f, 0xc91e, 0x21, 0 - .dw 0x2bc0, 0xc91e, 0x2bff, 0xc91e, 0x21, 0 - .dw 0x2c40, 0xc91e, 0x2c7f, 0xc91e, 0x21, 0 - .dw 0x2cc0, 0xc91e, 0x2cff, 0xc91e, 0x21, 0 - .dw 0x2d40, 0xc91e, 0x2d7f, 0xc91e, 0x21, 0 - .dw 0x2dc0, 0xc91e, 0x2dff, 0xc91e, 0x21, 0 - .dw 0x2e40, 0xc91e, 0x2e7f, 0xc91e, 0x21, 0 - .dw 0x2ec0, 0xc91e, 0x2eff, 0xc91e, 0x21, 0 - .dw 0x2f40, 0xc91e, 0x2f7f, 0xc91e, 0x21, 0 - .dw 0x2fc0, 0xc91e, 0x2fff, 0xc91e, 0x21, 0 - .dw 0x3040, 0xc91e, 0x307f, 0xc91e, 0x21, 0 - .dw 0x30c0, 0xc91e, 0x30ff, 0xc91e, 0x21, 0 - .dw 0x3140, 0xc91e, 0x317f, 0xc91e, 0x21, 0 - .dw 0x31c0, 0xc91e, 0x31ff, 0xc91e, 0x21, 0 - .dw 0x3240, 0xc91e, 0x327f, 0xc91e, 0x21, 0 - .dw 0x32c0, 0xc91e, 0x32ff, 0xc91e, 0x21, 0 - .dw 0x3340, 0xc91e, 0x337f, 0xc91e, 0x21, 0 - .dw 0x33c0, 0xc91e, 0x33ff, 0xc91e, 0x21, 0 - .dw 0x3440, 0xc91e, 0x347f, 0xc91e, 0x21, 0 - .dw 0x34c0, 0xc91e, 0x34ff, 0xc91e, 0x21, 0 - .dw 0x3540, 0xc91e, 0x357f, 0xc91e, 0x21, 0 - .dw 0x35c0, 0xc91e, 0x35ff, 0xc91e, 0x21, 0 - .dw 0x3640, 0xc91e, 0x367f, 0xc91e, 0x21, 0 - .dw 0x36c0, 0xc91e, 0x36ff, 0xc91e, 0x21, 0 - .dw 0x3740, 0xc91e, 0x377f, 0xc91e, 0x21, 0 - .dw 0x37c0, 0xc91e, 0x37ff, 0xc91e, 0x21, 0 - .dw 0x3840, 0xc91e, 0x387f, 0xc91e, 0x21, 0 - .dw 0x38c0, 0xc91e, 0x38ff, 0xc91e, 0x21, 0 - .dw 0x3940, 0xc91e, 0x397f, 0xc91e, 0x21, 0 - .dw 0x39c0, 0xc91e, 0x3fff, 0xc91e, 0x21, 0 - .dw 0x4040, 0xc91e, 0x407f, 0xc91e, 0x21, 0 - .dw 0x40c0, 0xc91e, 0x40ff, 0xc91e, 0x21, 0 - .dw 0x4140, 0xc91e, 0x417f, 0xc91e, 0x21, 0 - .dw 0x41c0, 0xc91e, 0x41ff, 0xc91e, 0x21, 0 - .dw 0x4240, 0xc91e, 0x427f, 0xc91e, 0x21, 0 - .dw 0x42c0, 0xc91e, 0x42ff, 0xc91e, 0x21, 0 - .dw 0x4340, 0xc91e, 0x437f, 0xc91e, 0x21, 0 - .dw 0x43c0, 0xc91e, 0x43ff, 0xc91e, 0x21, 0 - .dw 0x4440, 0xc91e, 0x447f, 0xc91e, 0x21, 0 - .dw 0x44c0, 0xc91e, 0x44ff, 0xc91e, 0x21, 0 - .dw 0x4540, 0xc91e, 0x457f, 0xc91e, 0x21, 0 - .dw 0x45c0, 0xc91e, 0x45ff, 0xc91e, 0x21, 0 - .dw 0x4640, 0xc91e, 0x467f, 0xc91e, 0x21, 0 - .dw 0x46c0, 0xc91e, 0x46ff, 0xc91e, 0x21, 0 - .dw 0x4740, 0xc91e, 0x477f, 0xc91e, 0x21, 0 - .dw 0x47c0, 0xc91e, 0x47ff, 0xc91e, 0x21, 0 - .dw 0x4840, 0xc91e, 0x487f, 0xc91e, 0x21, 0 - .dw 0x48c0, 0xc91e, 0x48ff, 0xc91e, 0x21, 0 - .dw 0x4940, 0xc91e, 0x497f, 0xc91e, 0x21, 0 - .dw 0x49c0, 0xc91e, 0x49ff, 0xc91e, 0x21, 0 - .dw 0x4a40, 0xc91e, 0x4a7f, 0xc91e, 0x21, 0 - .dw 0x4ac0, 0xc91e, 0x4aff, 0xc91e, 0x21, 0 - .dw 0x4b40, 0xc91e, 0x4b7f, 0xc91e, 0x21, 0 - .dw 0x4bc0, 0xc91e, 0x4bff, 0xc91e, 0x21, 0 - .dw 0x4c40, 0xc91e, 0x4c7f, 0xc91e, 0x21, 0 - .dw 0x4cc0, 0xc91e, 0x4cff, 0xc91e, 0x21, 0 - .dw 0x4d40, 0xc91e, 0x4d7f, 0xc91e, 0x21, 0 - .dw 0x4dc0, 0xc91e, 0x4dff, 0xc91e, 0x21, 0 - .dw 0x4e40, 0xc91e, 0x4e7f, 0xc91e, 0x21, 0 - .dw 0x4ec0, 0xc91e, 0x4eff, 0xc91e, 0x21, 0 - .dw 0x4f40, 0xc91e, 0x4f7f, 0xc91e, 0x21, 0 - .dw 0x4fc0, 0xc91e, 0x4fff, 0xc91e, 0x21, 0 - .dw 0x5040, 0xc91e, 0x507f, 0xc91e, 0x21, 0 - .dw 0x50c0, 0xc91e, 0x50ff, 0xc91e, 0x21, 0 - .dw 0x5140, 0xc91e, 0x517f, 0xc91e, 0x21, 0 - .dw 0x51c0, 0xc91e, 0x51ff, 0xc91e, 0x21, 0 - .dw 0x5240, 0xc91e, 0x527f, 0xc91e, 0x21, 0 - .dw 0x52c0, 0xc91e, 0x52ff, 0xc91e, 0x21, 0 - .dw 0x5340, 0xc91e, 0x537f, 0xc91e, 0x21, 0 - .dw 0x53c0, 0xc91e, 0x53ff, 0xc91e, 0x21, 0 - .dw 0x5440, 0xc91e, 0x547f, 0xc91e, 0x21, 0 - .dw 0x54c0, 0xc91e, 0x54ff, 0xc91e, 0x21, 0 - .dw 0x5540, 0xc91e, 0x557f, 0xc91e, 0x21, 0 - .dw 0x55c0, 0xc91e, 0x55ff, 0xc91e, 0x21, 0 - .dw 0x5640, 0xc91e, 0x567f, 0xc91e, 0x21, 0 - .dw 0x56c0, 0xc91e, 0x56ff, 0xc91e, 0x21, 0 - .dw 0x5740, 0xc91e, 0x577f, 0xc91e, 0x21, 0 - .dw 0x57c0, 0xc91e, 0x57ff, 0xc91e, 0x21, 0 - .dw 0x5840, 0xc91e, 0x587f, 0xc91e, 0x21, 0 - .dw 0x58c0, 0xc91e, 0x58ff, 0xc91e, 0x21, 0 - .dw 0x5940, 0xc91e, 0x597f, 0xc91e, 0x21, 0 - .dw 0x59c0, 0xc91e, 0x5fff, 0xc91e, 0x21, 0 - .dw 0x6040, 0xc91e, 0x607f, 0xc91e, 0x21, 0 - .dw 0x60c0, 0xc91e, 0x60ff, 0xc91e, 0x21, 0 - .dw 0x6140, 0xc91e, 0x617f, 0xc91e, 0x21, 0 - .dw 0x61c0, 0xc91e, 0x61ff, 0xc91e, 0x21, 0 - .dw 0x6240, 0xc91e, 0x627f, 0xc91e, 0x21, 0 - .dw 0x62c0, 0xc91e, 0x62ff, 0xc91e, 0x21, 0 - .dw 0x6340, 0xc91e, 0x637f, 0xc91e, 0x21, 0 - .dw 0x63c0, 0xc91e, 0x63ff, 0xc91e, 0x21, 0 - .dw 0x6440, 0xc91e, 0x647f, 0xc91e, 0x21, 0 - .dw 0x64c0, 0xc91e, 0x64ff, 0xc91e, 0x21, 0 - .dw 0x6540, 0xc91e, 0x657f, 0xc91e, 0x21, 0 - .dw 0x65c0, 0xc91e, 0x65ff, 0xc91e, 0x21, 0 - .dw 0x6640, 0xc91e, 0x667f, 0xc91e, 0x21, 0 - .dw 0x66c0, 0xc91e, 0x66ff, 0xc91e, 0x21, 0 - .dw 0x6740, 0xc91e, 0x677f, 0xc91e, 0x21, 0 - .dw 0x67c0, 0xc91e, 0x67ff, 0xc91e, 0x21, 0 - .dw 0x6840, 0xc91e, 0x687f, 0xc91e, 0x21, 0 - .dw 0x68c0, 0xc91e, 0x68ff, 0xc91e, 0x21, 0 - .dw 0x6940, 0xc91e, 0x697f, 0xc91e, 0x21, 0 - .dw 0x69c0, 0xc91e, 0x69ff, 0xc91e, 0x21, 0 - .dw 0x6a40, 0xc91e, 0x6a7f, 0xc91e, 0x21, 0 - .dw 0x6ac0, 0xc91e, 0x6aff, 0xc91e, 0x21, 0 - .dw 0x6b40, 0xc91e, 0x6b7f, 0xc91e, 0x21, 0 - .dw 0x6bc0, 0xc91e, 0x6bff, 0xc91e, 0x21, 0 - .dw 0x6c40, 0xc91e, 0x6c7f, 0xc91e, 0x21, 0 - .dw 0x6cc0, 0xc91e, 0x6cff, 0xc91e, 0x21, 0 - .dw 0x6d40, 0xc91e, 0x6d7f, 0xc91e, 0x21, 0 - .dw 0x6dc0, 0xc91e, 0x6dff, 0xc91e, 0x21, 0 - .dw 0x6e40, 0xc91e, 0x6e7f, 0xc91e, 0x21, 0 - .dw 0x6ec0, 0xc91e, 0x6eff, 0xc91e, 0x21, 0 - .dw 0x6f40, 0xc91e, 0x6f7f, 0xc91e, 0x21, 0 - .dw 0x6fc0, 0xc91e, 0x6fff, 0xc91e, 0x21, 0 - .dw 0x7040, 0xc91e, 0x707f, 0xc91e, 0x21, 0 - .dw 0x70c0, 0xc91e, 0x70ff, 0xc91e, 0x21, 0 - .dw 0x7140, 0xc91e, 0x717f, 0xc91e, 0x21, 0 - .dw 0x71c0, 0xc91e, 0x71ff, 0xc91e, 0x21, 0 - .dw 0x7240, 0xc91e, 0x727f, 0xc91e, 0x21, 0 - .dw 0x72c0, 0xc91e, 0x72ff, 0xc91e, 0x21, 0 - .dw 0x7340, 0xc91e, 0x737f, 0xc91e, 0x21, 0 - .dw 0x73c0, 0xc91e, 0x73ff, 0xc91e, 0x21, 0 - .dw 0x7440, 0xc91e, 0x747f, 0xc91e, 0x21, 0 - .dw 0x74c0, 0xc91e, 0x74ff, 0xc91e, 0x21, 0 - .dw 0x7540, 0xc91e, 0x757f, 0xc91e, 0x21, 0 - .dw 0x75c0, 0xc91e, 0x75ff, 0xc91e, 0x21, 0 - .dw 0x7640, 0xc91e, 0x767f, 0xc91e, 0x21, 0 - .dw 0x76c0, 0xc91e, 0x76ff, 0xc91e, 0x21, 0 - .dw 0x7740, 0xc91e, 0x777f, 0xc91e, 0x21, 0 - .dw 0x77c0, 0xc91e, 0x77ff, 0xc91e, 0x21, 0 - .dw 0x7840, 0xc91e, 0x787f, 0xc91e, 0x21, 0 - .dw 0x78c0, 0xc91e, 0x78ff, 0xc91e, 0x21, 0 - .dw 0x7940, 0xc91e, 0x797f, 0xc91e, 0x21, 0 - .dw 0x79c0, 0xc91e, 0x7fff, 0xc91e, 0x21, 0 - .dw 0x8040, 0xc91e, 0x807f, 0xc91e, 0x21, 0 - .dw 0x80c0, 0xc91e, 0x80ff, 0xc91e, 0x21, 0 - .dw 0x8140, 0xc91e, 0x817f, 0xc91e, 0x21, 0 - .dw 0x81c0, 0xc91e, 0x81ff, 0xc91e, 0x21, 0 - .dw 0x8240, 0xc91e, 0x827f, 0xc91e, 0x21, 0 - .dw 0x82c0, 0xc91e, 0x82ff, 0xc91e, 0x21, 0 - .dw 0x8340, 0xc91e, 0x837f, 0xc91e, 0x21, 0 - .dw 0x83c0, 0xc91e, 0x83ff, 0xc91e, 0x21, 0 - .dw 0x8440, 0xc91e, 0x847f, 0xc91e, 0x21, 0 - .dw 0x84c0, 0xc91e, 0x84ff, 0xc91e, 0x21, 0 - .dw 0x8540, 0xc91e, 0x857f, 0xc91e, 0x21, 0 - .dw 0x85c0, 0xc91e, 0x85ff, 0xc91e, 0x21, 0 - .dw 0x8640, 0xc91e, 0x867f, 0xc91e, 0x21, 0 - .dw 0x86c0, 0xc91e, 0x86ff, 0xc91e, 0x21, 0 - .dw 0x8740, 0xc91e, 0x877f, 0xc91e, 0x21, 0 - .dw 0x87c0, 0xc91e, 0x87ff, 0xc91e, 0x21, 0 - .dw 0x8840, 0xc91e, 0x887f, 0xc91e, 0x21, 0 - .dw 0x88c0, 0xc91e, 0x88ff, 0xc91e, 0x21, 0 - .dw 0x8940, 0xc91e, 0x897f, 0xc91e, 0x21, 0 - .dw 0x89c0, 0xc91e, 0x89ff, 0xc91e, 0x21, 0 - .dw 0x8a40, 0xc91e, 0x8a7f, 0xc91e, 0x21, 0 - .dw 0x8ac0, 0xc91e, 0x8aff, 0xc91e, 0x21, 0 - .dw 0x8b40, 0xc91e, 0x8b7f, 0xc91e, 0x21, 0 - .dw 0x8bc0, 0xc91e, 0x8bff, 0xc91e, 0x21, 0 - .dw 0x8c40, 0xc91e, 0x8c7f, 0xc91e, 0x21, 0 - .dw 0x8cc0, 0xc91e, 0x8cff, 0xc91e, 0x21, 0 - .dw 0x8d40, 0xc91e, 0x8d7f, 0xc91e, 0x21, 0 - .dw 0x8dc0, 0xc91e, 0x8dff, 0xc91e, 0x21, 0 - .dw 0x8e40, 0xc91e, 0x8e7f, 0xc91e, 0x21, 0 - .dw 0x8ec0, 0xc91e, 0x8eff, 0xc91e, 0x21, 0 - .dw 0x8f40, 0xc91e, 0x8f7f, 0xc91e, 0x21, 0 - .dw 0x8fc0, 0xc91e, 0x8fff, 0xc91e, 0x21, 0 - .dw 0x9040, 0xc91e, 0x907f, 0xc91e, 0x21, 0 - .dw 0x90c0, 0xc91e, 0x90ff, 0xc91e, 0x21, 0 - .dw 0x9140, 0xc91e, 0x917f, 0xc91e, 0x21, 0 - .dw 0x91c0, 0xc91e, 0x91ff, 0xc91e, 0x21, 0 - .dw 0x9240, 0xc91e, 0x927f, 0xc91e, 0x21, 0 - .dw 0x92c0, 0xc91e, 0x92ff, 0xc91e, 0x21, 0 - .dw 0x9340, 0xc91e, 0x937f, 0xc91e, 0x21, 0 - .dw 0x93c0, 0xc91e, 0x93ff, 0xc91e, 0x21, 0 - .dw 0x9440, 0xc91e, 0x947f, 0xc91e, 0x21, 0 - .dw 0x94c0, 0xc91e, 0x94ff, 0xc91e, 0x21, 0 - .dw 0x9540, 0xc91e, 0x957f, 0xc91e, 0x21, 0 - .dw 0x95c0, 0xc91e, 0x95ff, 0xc91e, 0x21, 0 - .dw 0x9640, 0xc91e, 0x967f, 0xc91e, 0x21, 0 - .dw 0x96c0, 0xc91e, 0x96ff, 0xc91e, 0x21, 0 - .dw 0x9740, 0xc91e, 0x977f, 0xc91e, 0x21, 0 - .dw 0x97c0, 0xc91e, 0x97ff, 0xc91e, 0x21, 0 - .dw 0x9840, 0xc91e, 0x987f, 0xc91e, 0x21, 0 - .dw 0x98c0, 0xc91e, 0x98ff, 0xc91e, 0x21, 0 - .dw 0x9940, 0xc91e, 0x997f, 0xc91e, 0x21, 0 - .dw 0x99c0, 0xc91e, 0x9fff, 0xc91e, 0x21, 0 - .dw 0xa040, 0xc91e, 0xa07f, 0xc91e, 0x21, 0 - .dw 0xa0c0, 0xc91e, 0xa0ff, 0xc91e, 0x21, 0 - .dw 0xa140, 0xc91e, 0xa17f, 0xc91e, 0x21, 0 - .dw 0xa1c0, 0xc91e, 0xa1ff, 0xc91e, 0x21, 0 - .dw 0xa240, 0xc91e, 0xa27f, 0xc91e, 0x21, 0 - .dw 0xa2c0, 0xc91e, 0xa2ff, 0xc91e, 0x21, 0 - .dw 0xa340, 0xc91e, 0xa37f, 0xc91e, 0x21, 0 - .dw 0xa3c0, 0xc91e, 0xa3ff, 0xc91e, 0x21, 0 - .dw 0xa440, 0xc91e, 0xa47f, 0xc91e, 0x21, 0 - .dw 0xa4c0, 0xc91e, 0xa4ff, 0xc91e, 0x21, 0 - .dw 0xa540, 0xc91e, 0xa57f, 0xc91e, 0x21, 0 - .dw 0xa5c0, 0xc91e, 0xa5ff, 0xc91e, 0x21, 0 - .dw 0xa640, 0xc91e, 0xa67f, 0xc91e, 0x21, 0 - .dw 0xa6c0, 0xc91e, 0xa6ff, 0xc91e, 0x21, 0 - .dw 0xa740, 0xc91e, 0xa77f, 0xc91e, 0x21, 0 - .dw 0xa7c0, 0xc91e, 0xa7ff, 0xc91e, 0x21, 0 - .dw 0xa840, 0xc91e, 0xa87f, 0xc91e, 0x21, 0 - .dw 0xa8c0, 0xc91e, 0xa8ff, 0xc91e, 0x21, 0 - .dw 0xa940, 0xc91e, 0xa97f, 0xc91e, 0x21, 0 - .dw 0xa9c0, 0xc91e, 0xa9ff, 0xc91e, 0x21, 0 - .dw 0xaa40, 0xc91e, 0xaa7f, 0xc91e, 0x21, 0 - .dw 0xaac0, 0xc91e, 0xaaff, 0xc91e, 0x21, 0 - .dw 0xab40, 0xc91e, 0xab7f, 0xc91e, 0x21, 0 - .dw 0xabc0, 0xc91e, 0xabff, 0xc91e, 0x21, 0 - .dw 0xac40, 0xc91e, 0xac7f, 0xc91e, 0x21, 0 - .dw 0xacc0, 0xc91e, 0xacff, 0xc91e, 0x21, 0 - .dw 0xad40, 0xc91e, 0xad7f, 0xc91e, 0x21, 0 - .dw 0xadc0, 0xc91e, 0xadff, 0xc91e, 0x21, 0 - .dw 0xae40, 0xc91e, 0xae7f, 0xc91e, 0x21, 0 - .dw 0xaec0, 0xc91e, 0xaeff, 0xc91e, 0x21, 0 - .dw 0xaf40, 0xc91e, 0xaf7f, 0xc91e, 0x21, 0 - .dw 0xafc0, 0xc91e, 0xafff, 0xc91e, 0x21, 0 - .dw 0xb040, 0xc91e, 0xb07f, 0xc91e, 0x21, 0 - .dw 0xb0c0, 0xc91e, 0xb0ff, 0xc91e, 0x21, 0 - .dw 0xb140, 0xc91e, 0xb17f, 0xc91e, 0x21, 0 - .dw 0xb1c0, 0xc91e, 0xb1ff, 0xc91e, 0x21, 0 - .dw 0xb240, 0xc91e, 0xb27f, 0xc91e, 0x21, 0 - .dw 0xb2c0, 0xc91e, 0xb2ff, 0xc91e, 0x21, 0 - .dw 0xb340, 0xc91e, 0xb37f, 0xc91e, 0x21, 0 - .dw 0xb3c0, 0xc91e, 0xb3ff, 0xc91e, 0x21, 0 - .dw 0xb440, 0xc91e, 0xb47f, 0xc91e, 0x21, 0 - .dw 0xb4c0, 0xc91e, 0xb4ff, 0xc91e, 0x21, 0 - .dw 0xb540, 0xc91e, 0xb57f, 0xc91e, 0x21, 0 - .dw 0xb5c0, 0xc91e, 0xb5ff, 0xc91e, 0x21, 0 - .dw 0xb640, 0xc91e, 0xb67f, 0xc91e, 0x21, 0 - .dw 0xb6c0, 0xc91e, 0xb6ff, 0xc91e, 0x21, 0 - .dw 0xb740, 0xc91e, 0xb77f, 0xc91e, 0x21, 0 - .dw 0xb7c0, 0xc91e, 0xb7ff, 0xc91e, 0x21, 0 - .dw 0xb840, 0xc91e, 0xb87f, 0xc91e, 0x21, 0 - .dw 0xb8c0, 0xc91e, 0xb8ff, 0xc91e, 0x21, 0 - .dw 0xb940, 0xc91e, 0xb97f, 0xc91e, 0x21, 0 - .dw 0xb9c0, 0xc91e, 0xbfff, 0xc91e, 0x21, 0 - .dw 0xc040, 0xc91e, 0xc07f, 0xc91e, 0x21, 0 - .dw 0xc0c0, 0xc91e, 0xc0ff, 0xc91e, 0x21, 0 - .dw 0xc140, 0xc91e, 0xc17f, 0xc91e, 0x21, 0 - .dw 0xc1c0, 0xc91e, 0xc1ff, 0xc91e, 0x21, 0 - .dw 0xc240, 0xc91e, 0xc27f, 0xc91e, 0x21, 0 - .dw 0xc2c0, 0xc91e, 0xc2ff, 0xc91e, 0x21, 0 - .dw 0xc340, 0xc91e, 0xc37f, 0xc91e, 0x21, 0 - .dw 0xc3c0, 0xc91e, 0xc3ff, 0xc91e, 0x21, 0 - .dw 0xc440, 0xc91e, 0xc47f, 0xc91e, 0x21, 0 - .dw 0xc4c0, 0xc91e, 0xc4ff, 0xc91e, 0x21, 0 - .dw 0xc540, 0xc91e, 0xc57f, 0xc91e, 0x21, 0 - .dw 0xc5c0, 0xc91e, 0xc5ff, 0xc91e, 0x21, 0 - .dw 0xc640, 0xc91e, 0xc67f, 0xc91e, 0x21, 0 - .dw 0xc6c0, 0xc91e, 0xc6ff, 0xc91e, 0x21, 0 - .dw 0xc740, 0xc91e, 0xc77f, 0xc91e, 0x21, 0 - .dw 0xc7c0, 0xc91e, 0xc7ff, 0xc91e, 0x21, 0 - .dw 0xc840, 0xc91e, 0xc87f, 0xc91e, 0x21, 0 - .dw 0xc8c0, 0xc91e, 0xc8ff, 0xc91e, 0x21, 0 - .dw 0xc940, 0xc91e, 0xc97f, 0xc91e, 0x21, 0 - .dw 0xc9c0, 0xc91e, 0xc9ff, 0xc91e, 0x21, 0 - .dw 0xca40, 0xc91e, 0xca7f, 0xc91e, 0x21, 0 - .dw 0xcac0, 0xc91e, 0xcaff, 0xc91e, 0x21, 0 - .dw 0xcb40, 0xc91e, 0xcb7f, 0xc91e, 0x21, 0 - .dw 0xcbc0, 0xc91e, 0xcbff, 0xc91e, 0x21, 0 - .dw 0xcc40, 0xc91e, 0xcc7f, 0xc91e, 0x21, 0 - .dw 0xccc0, 0xc91e, 0xccff, 0xc91e, 0x21, 0 - .dw 0xcd40, 0xc91e, 0xcd7f, 0xc91e, 0x21, 0 - .dw 0xcdc0, 0xc91e, 0xcdff, 0xc91e, 0x21, 0 - .dw 0xce40, 0xc91e, 0xce7f, 0xc91e, 0x21, 0 - .dw 0xcec0, 0xc91e, 0xceff, 0xc91e, 0x21, 0 - .dw 0xcf40, 0xc91e, 0xcf7f, 0xc91e, 0x21, 0 - .dw 0xcfc0, 0xc91e, 0xcfff, 0xc91e, 0x21, 0 - .dw 0xd040, 0xc91e, 0xd07f, 0xc91e, 0x21, 0 - .dw 0xd0c0, 0xc91e, 0xd0ff, 0xc91e, 0x21, 0 - .dw 0xd140, 0xc91e, 0xd17f, 0xc91e, 0x21, 0 - .dw 0xd1c0, 0xc91e, 0xd1ff, 0xc91e, 0x21, 0 - .dw 0xd240, 0xc91e, 0xd27f, 0xc91e, 0x21, 0 - .dw 0xd2c0, 0xc91e, 0xd2ff, 0xc91e, 0x21, 0 - .dw 0xd340, 0xc91e, 0xd37f, 0xc91e, 0x21, 0 - .dw 0xd3c0, 0xc91e, 0xd3ff, 0xc91e, 0x21, 0 - .dw 0xd440, 0xc91e, 0xd47f, 0xc91e, 0x21, 0 - .dw 0xd4c0, 0xc91e, 0xd4ff, 0xc91e, 0x21, 0 - .dw 0xd540, 0xc91e, 0xd57f, 0xc91e, 0x21, 0 - .dw 0xd5c0, 0xc91e, 0xd5ff, 0xc91e, 0x21, 0 - .dw 0xd640, 0xc91e, 0xd67f, 0xc91e, 0x21, 0 - .dw 0xd6c0, 0xc91e, 0xd6ff, 0xc91e, 0x21, 0 - .dw 0xd740, 0xc91e, 0xd77f, 0xc91e, 0x21, 0 - .dw 0xd7c0, 0xc91e, 0xd7ff, 0xc91e, 0x21, 0 - .dw 0xd840, 0xc91e, 0xd87f, 0xc91e, 0x21, 0 - .dw 0xd8c0, 0xc91e, 0xd8ff, 0xc91e, 0x21, 0 - .dw 0xd940, 0xc91e, 0xd97f, 0xc91e, 0x21, 0 - .dw 0xd9c0, 0xc91e, 0xdfff, 0xc91e, 0x21, 0 - .dw 0xe040, 0xc91e, 0xe07f, 0xc91e, 0x21, 0 - .dw 0xe0c0, 0xc91e, 0xe0ff, 0xc91e, 0x21, 0 - .dw 0xe140, 0xc91e, 0xe17f, 0xc91e, 0x21, 0 - .dw 0xe1c0, 0xc91e, 0xe1ff, 0xc91e, 0x21, 0 - .dw 0xe240, 0xc91e, 0xe27f, 0xc91e, 0x21, 0 - .dw 0xe2c0, 0xc91e, 0xe2ff, 0xc91e, 0x21, 0 - .dw 0xe340, 0xc91e, 0xe37f, 0xc91e, 0x21, 0 - .dw 0xe3c0, 0xc91e, 0xe3ff, 0xc91e, 0x21, 0 - .dw 0xe440, 0xc91e, 0xe47f, 0xc91e, 0x21, 0 - .dw 0xe4c0, 0xc91e, 0xe4ff, 0xc91e, 0x21, 0 - .dw 0xe540, 0xc91e, 0xe57f, 0xc91e, 0x21, 0 - .dw 0xe5c0, 0xc91e, 0xe5ff, 0xc91e, 0x21, 0 - .dw 0xe640, 0xc91e, 0xe67f, 0xc91e, 0x21, 0 - .dw 0xe6c0, 0xc91e, 0xe6ff, 0xc91e, 0x21, 0 - .dw 0xe740, 0xc91e, 0xe77f, 0xc91e, 0x21, 0 - .dw 0xe7c0, 0xc91e, 0xe7ff, 0xc91e, 0x21, 0 - .dw 0xe840, 0xc91e, 0xe87f, 0xc91e, 0x21, 0 - .dw 0xe8c0, 0xc91e, 0xe8ff, 0xc91e, 0x21, 0 - .dw 0xe940, 0xc91e, 0xe97f, 0xc91e, 0x21, 0 - .dw 0xe9c0, 0xc91e, 0xe9ff, 0xc91e, 0x21, 0 - .dw 0xea40, 0xc91e, 0xea7f, 0xc91e, 0x21, 0 - .dw 0xeac0, 0xc91e, 0xeaff, 0xc91e, 0x21, 0 - .dw 0xeb40, 0xc91e, 0xeb7f, 0xc91e, 0x21, 0 - .dw 0xebc0, 0xc91e, 0xebff, 0xc91e, 0x21, 0 - .dw 0xec40, 0xc91e, 0xec7f, 0xc91e, 0x21, 0 - .dw 0xecc0, 0xc91e, 0xecff, 0xc91e, 0x21, 0 - .dw 0xed40, 0xc91e, 0xed7f, 0xc91e, 0x21, 0 - .dw 0xedc0, 0xc91e, 0xedff, 0xc91e, 0x21, 0 - .dw 0xee40, 0xc91e, 0xee7f, 0xc91e, 0x21, 0 - .dw 0xeec0, 0xc91e, 0xeeff, 0xc91e, 0x21, 0 - .dw 0xef40, 0xc91e, 0xef7f, 0xc91e, 0x21, 0 - .dw 0xefc0, 0xc91e, 0xefff, 0xc91e, 0x21, 0 - .dw 0xf040, 0xc91e, 0xf07f, 0xc91e, 0x21, 0 - .dw 0xf0c0, 0xc91e, 0xf0ff, 0xc91e, 0x21, 0 - .dw 0xf140, 0xc91e, 0xf17f, 0xc91e, 0x21, 0 - .dw 0xf1c0, 0xc91e, 0xf1ff, 0xc91e, 0x21, 0 - .dw 0xf240, 0xc91e, 0xf27f, 0xc91e, 0x21, 0 - .dw 0xf2c0, 0xc91e, 0xf2ff, 0xc91e, 0x21, 0 - .dw 0xf340, 0xc91e, 0xf37f, 0xc91e, 0x21, 0 - .dw 0xf3c0, 0xc91e, 0xf3ff, 0xc91e, 0x21, 0 - .dw 0xf440, 0xc91e, 0xf47f, 0xc91e, 0x21, 0 - .dw 0xf4c0, 0xc91e, 0xf4ff, 0xc91e, 0x21, 0 - .dw 0xf540, 0xc91e, 0xf57f, 0xc91e, 0x21, 0 - .dw 0xf5c0, 0xc91e, 0xf5ff, 0xc91e, 0x21, 0 - .dw 0xf640, 0xc91e, 0xf67f, 0xc91e, 0x21, 0 - .dw 0xf6c0, 0xc91e, 0xf6ff, 0xc91e, 0x21, 0 - .dw 0xf740, 0xc91e, 0xf77f, 0xc91e, 0x21, 0 - .dw 0xf7c0, 0xc91e, 0xf7ff, 0xc91e, 0x21, 0 - .dw 0xf840, 0xc91e, 0xf87f, 0xc91e, 0x21, 0 - .dw 0xf8c0, 0xc91e, 0xf8ff, 0xc91e, 0x21, 0 - .dw 0xf940, 0xc91e, 0xf97f, 0xc91e, 0x21, 0 - .dw 0xf9c0, 0xc91e, 0xffff, 0xc91e, 0x21, 0 - .dw 0x0040, 0xc91f, 0x007f, 0xc91f, 0x21, 0 - .dw 0x00c0, 0xc91f, 0x00ff, 0xc91f, 0x21, 0 - .dw 0x0140, 0xc91f, 0x017f, 0xc91f, 0x21, 0 - .dw 0x01c0, 0xc91f, 0x01ff, 0xc91f, 0x21, 0 - .dw 0x0240, 0xc91f, 0x027f, 0xc91f, 0x21, 0 - .dw 0x02c0, 0xc91f, 0x02ff, 0xc91f, 0x21, 0 - .dw 0x0340, 0xc91f, 0x037f, 0xc91f, 0x21, 0 - .dw 0x03c0, 0xc91f, 0x03ff, 0xc91f, 0x21, 0 - .dw 0x0440, 0xc91f, 0x047f, 0xc91f, 0x21, 0 - .dw 0x04c0, 0xc91f, 0x04ff, 0xc91f, 0x21, 0 - .dw 0x0540, 0xc91f, 0x057f, 0xc91f, 0x21, 0 - .dw 0x05c0, 0xc91f, 0x05ff, 0xc91f, 0x21, 0 - .dw 0x0640, 0xc91f, 0x067f, 0xc91f, 0x21, 0 - .dw 0x06c0, 0xc91f, 0x06ff, 0xc91f, 0x21, 0 - .dw 0x0740, 0xc91f, 0x077f, 0xc91f, 0x21, 0 - .dw 0x07c0, 0xc91f, 0x07ff, 0xc91f, 0x21, 0 - .dw 0x0840, 0xc91f, 0x087f, 0xc91f, 0x21, 0 - .dw 0x08c0, 0xc91f, 0x08ff, 0xc91f, 0x21, 0 - .dw 0x0940, 0xc91f, 0x097f, 0xc91f, 0x21, 0 - .dw 0x09c0, 0xc91f, 0x09ff, 0xc91f, 0x21, 0 - .dw 0x0a40, 0xc91f, 0x0a7f, 0xc91f, 0x21, 0 - .dw 0x0ac0, 0xc91f, 0x0aff, 0xc91f, 0x21, 0 - .dw 0x0b40, 0xc91f, 0x0b7f, 0xc91f, 0x21, 0 - .dw 0x0bc0, 0xc91f, 0x0bff, 0xc91f, 0x21, 0 - .dw 0x0c40, 0xc91f, 0x0c7f, 0xc91f, 0x21, 0 - .dw 0x0cc0, 0xc91f, 0x0cff, 0xc91f, 0x21, 0 - .dw 0x0d40, 0xc91f, 0x0d7f, 0xc91f, 0x21, 0 - .dw 0x0dc0, 0xc91f, 0x0dff, 0xc91f, 0x21, 0 - .dw 0x0e40, 0xc91f, 0x0e7f, 0xc91f, 0x21, 0 - .dw 0x0ec0, 0xc91f, 0x0eff, 0xc91f, 0x21, 0 - .dw 0x0f40, 0xc91f, 0x0f7f, 0xc91f, 0x21, 0 - .dw 0x0fc0, 0xc91f, 0x0fff, 0xc91f, 0x21, 0 - .dw 0x1040, 0xc91f, 0x107f, 0xc91f, 0x21, 0 - .dw 0x10c0, 0xc91f, 0x10ff, 0xc91f, 0x21, 0 - .dw 0x1140, 0xc91f, 0x117f, 0xc91f, 0x21, 0 - .dw 0x11c0, 0xc91f, 0x11ff, 0xc91f, 0x21, 0 - .dw 0x1240, 0xc91f, 0x127f, 0xc91f, 0x21, 0 - .dw 0x12c0, 0xc91f, 0x12ff, 0xc91f, 0x21, 0 - .dw 0x1340, 0xc91f, 0x137f, 0xc91f, 0x21, 0 - .dw 0x13c0, 0xc91f, 0x13ff, 0xc91f, 0x21, 0 - .dw 0x1440, 0xc91f, 0x147f, 0xc91f, 0x21, 0 - .dw 0x14c0, 0xc91f, 0x14ff, 0xc91f, 0x21, 0 - .dw 0x1540, 0xc91f, 0x157f, 0xc91f, 0x21, 0 - .dw 0x15c0, 0xc91f, 0x15ff, 0xc91f, 0x21, 0 - .dw 0x1640, 0xc91f, 0x167f, 0xc91f, 0x21, 0 - .dw 0x16c0, 0xc91f, 0x16ff, 0xc91f, 0x21, 0 - .dw 0x1740, 0xc91f, 0x177f, 0xc91f, 0x21, 0 - .dw 0x17c0, 0xc91f, 0x17ff, 0xc91f, 0x21, 0 - .dw 0x1840, 0xc91f, 0x187f, 0xc91f, 0x21, 0 - .dw 0x18c0, 0xc91f, 0x18ff, 0xc91f, 0x21, 0 - .dw 0x1940, 0xc91f, 0x197f, 0xc91f, 0x21, 0 - .dw 0x19c0, 0xc91f, 0x1fff, 0xc91f, 0x21, 0 - .dw 0x2040, 0xc91f, 0x207f, 0xc91f, 0x21, 0 - .dw 0x20c0, 0xc91f, 0x20ff, 0xc91f, 0x21, 0 - .dw 0x2140, 0xc91f, 0x217f, 0xc91f, 0x21, 0 - .dw 0x21c0, 0xc91f, 0x21ff, 0xc91f, 0x21, 0 - .dw 0x2240, 0xc91f, 0x227f, 0xc91f, 0x21, 0 - .dw 0x22c0, 0xc91f, 0x22ff, 0xc91f, 0x21, 0 - .dw 0x2340, 0xc91f, 0x237f, 0xc91f, 0x21, 0 - .dw 0x23c0, 0xc91f, 0x23ff, 0xc91f, 0x21, 0 - .dw 0x2440, 0xc91f, 0x247f, 0xc91f, 0x21, 0 - .dw 0x24c0, 0xc91f, 0x24ff, 0xc91f, 0x21, 0 - .dw 0x2540, 0xc91f, 0x257f, 0xc91f, 0x21, 0 - .dw 0x25c0, 0xc91f, 0x25ff, 0xc91f, 0x21, 0 - .dw 0x2640, 0xc91f, 0x267f, 0xc91f, 0x21, 0 - .dw 0x26c0, 0xc91f, 0x26ff, 0xc91f, 0x21, 0 - .dw 0x2740, 0xc91f, 0x277f, 0xc91f, 0x21, 0 - .dw 0x27c0, 0xc91f, 0x27ff, 0xc91f, 0x21, 0 - .dw 0x2840, 0xc91f, 0x287f, 0xc91f, 0x21, 0 - .dw 0x28c0, 0xc91f, 0x28ff, 0xc91f, 0x21, 0 - .dw 0x2940, 0xc91f, 0x297f, 0xc91f, 0x21, 0 - .dw 0x29c0, 0xc91f, 0x29ff, 0xc91f, 0x21, 0 - .dw 0x2a40, 0xc91f, 0x2a7f, 0xc91f, 0x21, 0 - .dw 0x2ac0, 0xc91f, 0x2aff, 0xc91f, 0x21, 0 - .dw 0x2b40, 0xc91f, 0x2b7f, 0xc91f, 0x21, 0 - .dw 0x2bc0, 0xc91f, 0x2bff, 0xc91f, 0x21, 0 - .dw 0x2c40, 0xc91f, 0x2c7f, 0xc91f, 0x21, 0 - .dw 0x2cc0, 0xc91f, 0x2cff, 0xc91f, 0x21, 0 - .dw 0x2d40, 0xc91f, 0x2d7f, 0xc91f, 0x21, 0 - .dw 0x2dc0, 0xc91f, 0x2dff, 0xc91f, 0x21, 0 - .dw 0x2e40, 0xc91f, 0x2e7f, 0xc91f, 0x21, 0 - .dw 0x2ec0, 0xc91f, 0x2eff, 0xc91f, 0x21, 0 - .dw 0x2f40, 0xc91f, 0x2f7f, 0xc91f, 0x21, 0 - .dw 0x2fc0, 0xc91f, 0x2fff, 0xc91f, 0x21, 0 - .dw 0x3040, 0xc91f, 0x307f, 0xc91f, 0x21, 0 - .dw 0x30c0, 0xc91f, 0x30ff, 0xc91f, 0x21, 0 - .dw 0x3140, 0xc91f, 0x317f, 0xc91f, 0x21, 0 - .dw 0x31c0, 0xc91f, 0x31ff, 0xc91f, 0x21, 0 - .dw 0x3240, 0xc91f, 0x327f, 0xc91f, 0x21, 0 - .dw 0x32c0, 0xc91f, 0x32ff, 0xc91f, 0x21, 0 - .dw 0x3340, 0xc91f, 0x337f, 0xc91f, 0x21, 0 - .dw 0x33c0, 0xc91f, 0x33ff, 0xc91f, 0x21, 0 - .dw 0x3440, 0xc91f, 0x347f, 0xc91f, 0x21, 0 - .dw 0x34c0, 0xc91f, 0x34ff, 0xc91f, 0x21, 0 - .dw 0x3540, 0xc91f, 0x357f, 0xc91f, 0x21, 0 - .dw 0x35c0, 0xc91f, 0x35ff, 0xc91f, 0x21, 0 - .dw 0x3640, 0xc91f, 0x367f, 0xc91f, 0x21, 0 - .dw 0x36c0, 0xc91f, 0x36ff, 0xc91f, 0x21, 0 - .dw 0x3740, 0xc91f, 0x377f, 0xc91f, 0x21, 0 - .dw 0x37c0, 0xc91f, 0x37ff, 0xc91f, 0x21, 0 - .dw 0x3840, 0xc91f, 0x387f, 0xc91f, 0x21, 0 - .dw 0x38c0, 0xc91f, 0x38ff, 0xc91f, 0x21, 0 - .dw 0x3940, 0xc91f, 0x397f, 0xc91f, 0x21, 0 - .dw 0x39c0, 0xc91f, 0x1fff, 0xc920, 0x21, 0 - .dw 0x3a00, 0xc920, 0x5fff, 0xc920, 0x21, 0 - .dw 0x7a00, 0xc920, 0x9fff, 0xc920, 0x21, 0 - .dw 0xba00, 0xc920, 0xdfff, 0xc920, 0x21, 0 - .dw 0xfa00, 0xc920, 0x1fff, 0xc921, 0x21, 0 - .dw 0x3a00, 0xc921, 0x5fff, 0xc921, 0x21, 0 - .dw 0x7a00, 0xc921, 0x9fff, 0xc921, 0x21, 0 - .dw 0xba00, 0xc921, 0xdfff, 0xc921, 0x21, 0 - .dw 0xfa00, 0xc921, 0x1fff, 0xc922, 0x21, 0 - .dw 0x3a00, 0xc922, 0x5fff, 0xc922, 0x21, 0 - .dw 0x7a00, 0xc922, 0x9fff, 0xc922, 0x21, 0 - .dw 0xba00, 0xc922, 0xdfff, 0xc922, 0x21, 0 - .dw 0xfa00, 0xc922, 0x1fff, 0xc923, 0x21, 0 - .dw 0x3a00, 0xc923, 0xffff, 0xc923, 0x21, 0 - .dw 0x1a00, 0xc924, 0x1fff, 0xc924, 0x21, 0 - .dw 0x3a00, 0xc924, 0x3fff, 0xc924, 0x21, 0 - .dw 0x5a00, 0xc924, 0x5fff, 0xc924, 0x21, 0 - .dw 0x7a00, 0xc924, 0x7fff, 0xc924, 0x21, 0 - .dw 0x9a00, 0xc924, 0x9fff, 0xc924, 0x21, 0 - .dw 0xba00, 0xc924, 0xbfff, 0xc924, 0x21, 0 - .dw 0xda00, 0xc924, 0xdfff, 0xc924, 0x21, 0 - .dw 0xfa00, 0xc924, 0xffff, 0xc924, 0x21, 0 - .dw 0x1a00, 0xc925, 0x1fff, 0xc925, 0x21, 0 - .dw 0x3a00, 0xc925, 0x3fff, 0xc925, 0x21, 0 - .dw 0x5a00, 0xc925, 0x5fff, 0xc925, 0x21, 0 - .dw 0x7a00, 0xc925, 0x7fff, 0xc925, 0x21, 0 - .dw 0x9a00, 0xc925, 0x9fff, 0xc925, 0x21, 0 - .dw 0xba00, 0xc925, 0xbfff, 0xc925, 0x21, 0 - .dw 0xda00, 0xc925, 0xdfff, 0xc925, 0x21, 0 - .dw 0xfa00, 0xc925, 0xffff, 0xc925, 0x21, 0 - .dw 0x1a00, 0xc926, 0x1fff, 0xc926, 0x21, 0 - .dw 0x3a00, 0xc926, 0x3fff, 0xc926, 0x21, 0 - .dw 0x5a00, 0xc926, 0x5fff, 0xc926, 0x21, 0 - .dw 0x7a00, 0xc926, 0x7fff, 0xc926, 0x21, 0 - .dw 0x9a00, 0xc926, 0x9fff, 0xc926, 0x21, 0 - .dw 0xba00, 0xc926, 0xbfff, 0xc926, 0x21, 0 - .dw 0xda00, 0xc926, 0xdfff, 0xc926, 0x21, 0 - .dw 0xfa00, 0xc926, 0xffff, 0xc926, 0x21, 0 - .dw 0x1a00, 0xc927, 0x1fff, 0xc927, 0x21, 0 - .dw 0x3a00, 0xc927, 0x1fff, 0xc928, 0x21, 0 - .dw 0x2040, 0xc928, 0x207f, 0xc928, 0x21, 0 - .dw 0x20c0, 0xc928, 0x20ff, 0xc928, 0x21, 0 - .dw 0x2140, 0xc928, 0x217f, 0xc928, 0x21, 0 - .dw 0x21c0, 0xc928, 0x21ff, 0xc928, 0x21, 0 - .dw 0x2240, 0xc928, 0x227f, 0xc928, 0x21, 0 - .dw 0x22c0, 0xc928, 0x22ff, 0xc928, 0x21, 0 - .dw 0x2340, 0xc928, 0x237f, 0xc928, 0x21, 0 - .dw 0x23c0, 0xc928, 0x23ff, 0xc928, 0x21, 0 - .dw 0x2440, 0xc928, 0x247f, 0xc928, 0x21, 0 - .dw 0x24c0, 0xc928, 0x24ff, 0xc928, 0x21, 0 - .dw 0x2540, 0xc928, 0x257f, 0xc928, 0x21, 0 - .dw 0x25c0, 0xc928, 0x25ff, 0xc928, 0x21, 0 - .dw 0x2640, 0xc928, 0x267f, 0xc928, 0x21, 0 - .dw 0x26c0, 0xc928, 0x26ff, 0xc928, 0x21, 0 - .dw 0x2740, 0xc928, 0x277f, 0xc928, 0x21, 0 - .dw 0x27c0, 0xc928, 0x27ff, 0xc928, 0x21, 0 - .dw 0x2840, 0xc928, 0x287f, 0xc928, 0x21, 0 - .dw 0x28c0, 0xc928, 0x28ff, 0xc928, 0x21, 0 - .dw 0x2940, 0xc928, 0x297f, 0xc928, 0x21, 0 - .dw 0x29c0, 0xc928, 0x29ff, 0xc928, 0x21, 0 - .dw 0x2a40, 0xc928, 0x2a7f, 0xc928, 0x21, 0 - .dw 0x2ac0, 0xc928, 0x2aff, 0xc928, 0x21, 0 - .dw 0x2b40, 0xc928, 0x2b7f, 0xc928, 0x21, 0 - .dw 0x2bc0, 0xc928, 0x2bff, 0xc928, 0x21, 0 - .dw 0x2c40, 0xc928, 0x2c7f, 0xc928, 0x21, 0 - .dw 0x2cc0, 0xc928, 0x2cff, 0xc928, 0x21, 0 - .dw 0x2d40, 0xc928, 0x2d7f, 0xc928, 0x21, 0 - .dw 0x2dc0, 0xc928, 0x2dff, 0xc928, 0x21, 0 - .dw 0x2e40, 0xc928, 0x2e7f, 0xc928, 0x21, 0 - .dw 0x2ec0, 0xc928, 0x2eff, 0xc928, 0x21, 0 - .dw 0x2f40, 0xc928, 0x2f7f, 0xc928, 0x21, 0 - .dw 0x2fc0, 0xc928, 0x2fff, 0xc928, 0x21, 0 - .dw 0x3040, 0xc928, 0x307f, 0xc928, 0x21, 0 - .dw 0x30c0, 0xc928, 0x30ff, 0xc928, 0x21, 0 - .dw 0x3140, 0xc928, 0x317f, 0xc928, 0x21, 0 - .dw 0x31c0, 0xc928, 0x31ff, 0xc928, 0x21, 0 - .dw 0x3240, 0xc928, 0x327f, 0xc928, 0x21, 0 - .dw 0x32c0, 0xc928, 0x32ff, 0xc928, 0x21, 0 - .dw 0x3340, 0xc928, 0x337f, 0xc928, 0x21, 0 - .dw 0x33c0, 0xc928, 0x33ff, 0xc928, 0x21, 0 - .dw 0x3440, 0xc928, 0x347f, 0xc928, 0x21, 0 - .dw 0x34c0, 0xc928, 0x34ff, 0xc928, 0x21, 0 - .dw 0x3540, 0xc928, 0x357f, 0xc928, 0x21, 0 - .dw 0x35c0, 0xc928, 0x35ff, 0xc928, 0x21, 0 - .dw 0x3640, 0xc928, 0x367f, 0xc928, 0x21, 0 - .dw 0x36c0, 0xc928, 0x36ff, 0xc928, 0x21, 0 - .dw 0x3740, 0xc928, 0x377f, 0xc928, 0x21, 0 - .dw 0x37c0, 0xc928, 0x37ff, 0xc928, 0x21, 0 - .dw 0x3840, 0xc928, 0x387f, 0xc928, 0x21, 0 - .dw 0x38c0, 0xc928, 0x38ff, 0xc928, 0x21, 0 - .dw 0x3940, 0xc928, 0x397f, 0xc928, 0x21, 0 - .dw 0x39c0, 0xc928, 0x5fff, 0xc928, 0x21, 0 - .dw 0x6040, 0xc928, 0x607f, 0xc928, 0x21, 0 - .dw 0x60c0, 0xc928, 0x60ff, 0xc928, 0x21, 0 - .dw 0x6140, 0xc928, 0x617f, 0xc928, 0x21, 0 - .dw 0x61c0, 0xc928, 0x61ff, 0xc928, 0x21, 0 - .dw 0x6240, 0xc928, 0x627f, 0xc928, 0x21, 0 - .dw 0x62c0, 0xc928, 0x62ff, 0xc928, 0x21, 0 - .dw 0x6340, 0xc928, 0x637f, 0xc928, 0x21, 0 - .dw 0x63c0, 0xc928, 0x63ff, 0xc928, 0x21, 0 - .dw 0x6440, 0xc928, 0x647f, 0xc928, 0x21, 0 - .dw 0x64c0, 0xc928, 0x64ff, 0xc928, 0x21, 0 - .dw 0x6540, 0xc928, 0x657f, 0xc928, 0x21, 0 - .dw 0x65c0, 0xc928, 0x65ff, 0xc928, 0x21, 0 - .dw 0x6640, 0xc928, 0x667f, 0xc928, 0x21, 0 - .dw 0x66c0, 0xc928, 0x66ff, 0xc928, 0x21, 0 - .dw 0x6740, 0xc928, 0x677f, 0xc928, 0x21, 0 - .dw 0x67c0, 0xc928, 0x67ff, 0xc928, 0x21, 0 - .dw 0x6840, 0xc928, 0x687f, 0xc928, 0x21, 0 - .dw 0x68c0, 0xc928, 0x68ff, 0xc928, 0x21, 0 - .dw 0x6940, 0xc928, 0x697f, 0xc928, 0x21, 0 - .dw 0x69c0, 0xc928, 0x69ff, 0xc928, 0x21, 0 - .dw 0x6a40, 0xc928, 0x6a7f, 0xc928, 0x21, 0 - .dw 0x6ac0, 0xc928, 0x6aff, 0xc928, 0x21, 0 - .dw 0x6b40, 0xc928, 0x6b7f, 0xc928, 0x21, 0 - .dw 0x6bc0, 0xc928, 0x6bff, 0xc928, 0x21, 0 - .dw 0x6c40, 0xc928, 0x6c7f, 0xc928, 0x21, 0 - .dw 0x6cc0, 0xc928, 0x6cff, 0xc928, 0x21, 0 - .dw 0x6d40, 0xc928, 0x6d7f, 0xc928, 0x21, 0 - .dw 0x6dc0, 0xc928, 0x6dff, 0xc928, 0x21, 0 - .dw 0x6e40, 0xc928, 0x6e7f, 0xc928, 0x21, 0 - .dw 0x6ec0, 0xc928, 0x6eff, 0xc928, 0x21, 0 - .dw 0x6f40, 0xc928, 0x6f7f, 0xc928, 0x21, 0 - .dw 0x6fc0, 0xc928, 0x6fff, 0xc928, 0x21, 0 - .dw 0x7040, 0xc928, 0x707f, 0xc928, 0x21, 0 - .dw 0x70c0, 0xc928, 0x70ff, 0xc928, 0x21, 0 - .dw 0x7140, 0xc928, 0x717f, 0xc928, 0x21, 0 - .dw 0x71c0, 0xc928, 0x71ff, 0xc928, 0x21, 0 - .dw 0x7240, 0xc928, 0x727f, 0xc928, 0x21, 0 - .dw 0x72c0, 0xc928, 0x72ff, 0xc928, 0x21, 0 - .dw 0x7340, 0xc928, 0x737f, 0xc928, 0x21, 0 - .dw 0x73c0, 0xc928, 0x73ff, 0xc928, 0x21, 0 - .dw 0x7440, 0xc928, 0x747f, 0xc928, 0x21, 0 - .dw 0x74c0, 0xc928, 0x74ff, 0xc928, 0x21, 0 - .dw 0x7540, 0xc928, 0x757f, 0xc928, 0x21, 0 - .dw 0x75c0, 0xc928, 0x75ff, 0xc928, 0x21, 0 - .dw 0x7640, 0xc928, 0x767f, 0xc928, 0x21, 0 - .dw 0x76c0, 0xc928, 0x76ff, 0xc928, 0x21, 0 - .dw 0x7740, 0xc928, 0x777f, 0xc928, 0x21, 0 - .dw 0x77c0, 0xc928, 0x77ff, 0xc928, 0x21, 0 - .dw 0x7840, 0xc928, 0x787f, 0xc928, 0x21, 0 - .dw 0x78c0, 0xc928, 0x78ff, 0xc928, 0x21, 0 - .dw 0x7940, 0xc928, 0x797f, 0xc928, 0x21, 0 - .dw 0x79c0, 0xc928, 0x9fff, 0xc928, 0x21, 0 - .dw 0xa040, 0xc928, 0xa07f, 0xc928, 0x21, 0 - .dw 0xa0c0, 0xc928, 0xa0ff, 0xc928, 0x21, 0 - .dw 0xa140, 0xc928, 0xa17f, 0xc928, 0x21, 0 - .dw 0xa1c0, 0xc928, 0xa1ff, 0xc928, 0x21, 0 - .dw 0xa240, 0xc928, 0xa27f, 0xc928, 0x21, 0 - .dw 0xa2c0, 0xc928, 0xa2ff, 0xc928, 0x21, 0 - .dw 0xa340, 0xc928, 0xa37f, 0xc928, 0x21, 0 - .dw 0xa3c0, 0xc928, 0xa3ff, 0xc928, 0x21, 0 - .dw 0xa440, 0xc928, 0xa47f, 0xc928, 0x21, 0 - .dw 0xa4c0, 0xc928, 0xa4ff, 0xc928, 0x21, 0 - .dw 0xa540, 0xc928, 0xa57f, 0xc928, 0x21, 0 - .dw 0xa5c0, 0xc928, 0xa5ff, 0xc928, 0x21, 0 - .dw 0xa640, 0xc928, 0xa67f, 0xc928, 0x21, 0 - .dw 0xa6c0, 0xc928, 0xa6ff, 0xc928, 0x21, 0 - .dw 0xa740, 0xc928, 0xa77f, 0xc928, 0x21, 0 - .dw 0xa7c0, 0xc928, 0xa7ff, 0xc928, 0x21, 0 - .dw 0xa840, 0xc928, 0xa87f, 0xc928, 0x21, 0 - .dw 0xa8c0, 0xc928, 0xa8ff, 0xc928, 0x21, 0 - .dw 0xa940, 0xc928, 0xa97f, 0xc928, 0x21, 0 - .dw 0xa9c0, 0xc928, 0xa9ff, 0xc928, 0x21, 0 - .dw 0xaa40, 0xc928, 0xaa7f, 0xc928, 0x21, 0 - .dw 0xaac0, 0xc928, 0xaaff, 0xc928, 0x21, 0 - .dw 0xab40, 0xc928, 0xab7f, 0xc928, 0x21, 0 - .dw 0xabc0, 0xc928, 0xabff, 0xc928, 0x21, 0 - .dw 0xac40, 0xc928, 0xac7f, 0xc928, 0x21, 0 - .dw 0xacc0, 0xc928, 0xacff, 0xc928, 0x21, 0 - .dw 0xad40, 0xc928, 0xad7f, 0xc928, 0x21, 0 - .dw 0xadc0, 0xc928, 0xadff, 0xc928, 0x21, 0 - .dw 0xae40, 0xc928, 0xae7f, 0xc928, 0x21, 0 - .dw 0xaec0, 0xc928, 0xaeff, 0xc928, 0x21, 0 - .dw 0xaf40, 0xc928, 0xaf7f, 0xc928, 0x21, 0 - .dw 0xafc0, 0xc928, 0xafff, 0xc928, 0x21, 0 - .dw 0xb040, 0xc928, 0xb07f, 0xc928, 0x21, 0 - .dw 0xb0c0, 0xc928, 0xb0ff, 0xc928, 0x21, 0 - .dw 0xb140, 0xc928, 0xb17f, 0xc928, 0x21, 0 - .dw 0xb1c0, 0xc928, 0xb1ff, 0xc928, 0x21, 0 - .dw 0xb240, 0xc928, 0xb27f, 0xc928, 0x21, 0 - .dw 0xb2c0, 0xc928, 0xb2ff, 0xc928, 0x21, 0 - .dw 0xb340, 0xc928, 0xb37f, 0xc928, 0x21, 0 - .dw 0xb3c0, 0xc928, 0xb3ff, 0xc928, 0x21, 0 - .dw 0xb440, 0xc928, 0xb47f, 0xc928, 0x21, 0 - .dw 0xb4c0, 0xc928, 0xb4ff, 0xc928, 0x21, 0 - .dw 0xb540, 0xc928, 0xb57f, 0xc928, 0x21, 0 - .dw 0xb5c0, 0xc928, 0xb5ff, 0xc928, 0x21, 0 - .dw 0xb640, 0xc928, 0xb67f, 0xc928, 0x21, 0 - .dw 0xb6c0, 0xc928, 0xb6ff, 0xc928, 0x21, 0 - .dw 0xb740, 0xc928, 0xb77f, 0xc928, 0x21, 0 - .dw 0xb7c0, 0xc928, 0xb7ff, 0xc928, 0x21, 0 - .dw 0xb840, 0xc928, 0xb87f, 0xc928, 0x21, 0 - .dw 0xb8c0, 0xc928, 0xb8ff, 0xc928, 0x21, 0 - .dw 0xb940, 0xc928, 0xb97f, 0xc928, 0x21, 0 - .dw 0xb9c0, 0xc928, 0xdfff, 0xc928, 0x21, 0 - .dw 0xe040, 0xc928, 0xe07f, 0xc928, 0x21, 0 - .dw 0xe0c0, 0xc928, 0xe0ff, 0xc928, 0x21, 0 - .dw 0xe140, 0xc928, 0xe17f, 0xc928, 0x21, 0 - .dw 0xe1c0, 0xc928, 0xe1ff, 0xc928, 0x21, 0 - .dw 0xe240, 0xc928, 0xe27f, 0xc928, 0x21, 0 - .dw 0xe2c0, 0xc928, 0xe2ff, 0xc928, 0x21, 0 - .dw 0xe340, 0xc928, 0xe37f, 0xc928, 0x21, 0 - .dw 0xe3c0, 0xc928, 0xe3ff, 0xc928, 0x21, 0 - .dw 0xe440, 0xc928, 0xe47f, 0xc928, 0x21, 0 - .dw 0xe4c0, 0xc928, 0xe4ff, 0xc928, 0x21, 0 - .dw 0xe540, 0xc928, 0xe57f, 0xc928, 0x21, 0 - .dw 0xe5c0, 0xc928, 0xe5ff, 0xc928, 0x21, 0 - .dw 0xe640, 0xc928, 0xe67f, 0xc928, 0x21, 0 - .dw 0xe6c0, 0xc928, 0xe6ff, 0xc928, 0x21, 0 - .dw 0xe740, 0xc928, 0xe77f, 0xc928, 0x21, 0 - .dw 0xe7c0, 0xc928, 0xe7ff, 0xc928, 0x21, 0 - .dw 0xe840, 0xc928, 0xe87f, 0xc928, 0x21, 0 - .dw 0xe8c0, 0xc928, 0xe8ff, 0xc928, 0x21, 0 - .dw 0xe940, 0xc928, 0xe97f, 0xc928, 0x21, 0 - .dw 0xe9c0, 0xc928, 0xe9ff, 0xc928, 0x21, 0 - .dw 0xea40, 0xc928, 0xea7f, 0xc928, 0x21, 0 - .dw 0xeac0, 0xc928, 0xeaff, 0xc928, 0x21, 0 - .dw 0xeb40, 0xc928, 0xeb7f, 0xc928, 0x21, 0 - .dw 0xebc0, 0xc928, 0xebff, 0xc928, 0x21, 0 - .dw 0xec40, 0xc928, 0xec7f, 0xc928, 0x21, 0 - .dw 0xecc0, 0xc928, 0xecff, 0xc928, 0x21, 0 - .dw 0xed40, 0xc928, 0xed7f, 0xc928, 0x21, 0 - .dw 0xedc0, 0xc928, 0xedff, 0xc928, 0x21, 0 - .dw 0xee40, 0xc928, 0xee7f, 0xc928, 0x21, 0 - .dw 0xeec0, 0xc928, 0xeeff, 0xc928, 0x21, 0 - .dw 0xef40, 0xc928, 0xef7f, 0xc928, 0x21, 0 - .dw 0xefc0, 0xc928, 0xefff, 0xc928, 0x21, 0 - .dw 0xf040, 0xc928, 0xf07f, 0xc928, 0x21, 0 - .dw 0xf0c0, 0xc928, 0xf0ff, 0xc928, 0x21, 0 - .dw 0xf140, 0xc928, 0xf17f, 0xc928, 0x21, 0 - .dw 0xf1c0, 0xc928, 0xf1ff, 0xc928, 0x21, 0 - .dw 0xf240, 0xc928, 0xf27f, 0xc928, 0x21, 0 - .dw 0xf2c0, 0xc928, 0xf2ff, 0xc928, 0x21, 0 - .dw 0xf340, 0xc928, 0xf37f, 0xc928, 0x21, 0 - .dw 0xf3c0, 0xc928, 0xf3ff, 0xc928, 0x21, 0 - .dw 0xf440, 0xc928, 0xf47f, 0xc928, 0x21, 0 - .dw 0xf4c0, 0xc928, 0xf4ff, 0xc928, 0x21, 0 - .dw 0xf540, 0xc928, 0xf57f, 0xc928, 0x21, 0 - .dw 0xf5c0, 0xc928, 0xf5ff, 0xc928, 0x21, 0 - .dw 0xf640, 0xc928, 0xf67f, 0xc928, 0x21, 0 - .dw 0xf6c0, 0xc928, 0xf6ff, 0xc928, 0x21, 0 - .dw 0xf740, 0xc928, 0xf77f, 0xc928, 0x21, 0 - .dw 0xf7c0, 0xc928, 0xf7ff, 0xc928, 0x21, 0 - .dw 0xf840, 0xc928, 0xf87f, 0xc928, 0x21, 0 - .dw 0xf8c0, 0xc928, 0xf8ff, 0xc928, 0x21, 0 - .dw 0xf940, 0xc928, 0xf97f, 0xc928, 0x21, 0 - .dw 0xf9c0, 0xc928, 0x1fff, 0xc929, 0x21, 0 - .dw 0x2040, 0xc929, 0x207f, 0xc929, 0x21, 0 - .dw 0x20c0, 0xc929, 0x20ff, 0xc929, 0x21, 0 - .dw 0x2140, 0xc929, 0x217f, 0xc929, 0x21, 0 - .dw 0x21c0, 0xc929, 0x21ff, 0xc929, 0x21, 0 - .dw 0x2240, 0xc929, 0x227f, 0xc929, 0x21, 0 - .dw 0x22c0, 0xc929, 0x22ff, 0xc929, 0x21, 0 - .dw 0x2340, 0xc929, 0x237f, 0xc929, 0x21, 0 - .dw 0x23c0, 0xc929, 0x23ff, 0xc929, 0x21, 0 - .dw 0x2440, 0xc929, 0x247f, 0xc929, 0x21, 0 - .dw 0x24c0, 0xc929, 0x24ff, 0xc929, 0x21, 0 - .dw 0x2540, 0xc929, 0x257f, 0xc929, 0x21, 0 - .dw 0x25c0, 0xc929, 0x25ff, 0xc929, 0x21, 0 - .dw 0x2640, 0xc929, 0x267f, 0xc929, 0x21, 0 - .dw 0x26c0, 0xc929, 0x26ff, 0xc929, 0x21, 0 - .dw 0x2740, 0xc929, 0x277f, 0xc929, 0x21, 0 - .dw 0x27c0, 0xc929, 0x27ff, 0xc929, 0x21, 0 - .dw 0x2840, 0xc929, 0x287f, 0xc929, 0x21, 0 - .dw 0x28c0, 0xc929, 0x28ff, 0xc929, 0x21, 0 - .dw 0x2940, 0xc929, 0x297f, 0xc929, 0x21, 0 - .dw 0x29c0, 0xc929, 0x29ff, 0xc929, 0x21, 0 - .dw 0x2a40, 0xc929, 0x2a7f, 0xc929, 0x21, 0 - .dw 0x2ac0, 0xc929, 0x2aff, 0xc929, 0x21, 0 - .dw 0x2b40, 0xc929, 0x2b7f, 0xc929, 0x21, 0 - .dw 0x2bc0, 0xc929, 0x2bff, 0xc929, 0x21, 0 - .dw 0x2c40, 0xc929, 0x2c7f, 0xc929, 0x21, 0 - .dw 0x2cc0, 0xc929, 0x2cff, 0xc929, 0x21, 0 - .dw 0x2d40, 0xc929, 0x2d7f, 0xc929, 0x21, 0 - .dw 0x2dc0, 0xc929, 0x2dff, 0xc929, 0x21, 0 - .dw 0x2e40, 0xc929, 0x2e7f, 0xc929, 0x21, 0 - .dw 0x2ec0, 0xc929, 0x2eff, 0xc929, 0x21, 0 - .dw 0x2f40, 0xc929, 0x2f7f, 0xc929, 0x21, 0 - .dw 0x2fc0, 0xc929, 0x2fff, 0xc929, 0x21, 0 - .dw 0x3040, 0xc929, 0x307f, 0xc929, 0x21, 0 - .dw 0x30c0, 0xc929, 0x30ff, 0xc929, 0x21, 0 - .dw 0x3140, 0xc929, 0x317f, 0xc929, 0x21, 0 - .dw 0x31c0, 0xc929, 0x31ff, 0xc929, 0x21, 0 - .dw 0x3240, 0xc929, 0x327f, 0xc929, 0x21, 0 - .dw 0x32c0, 0xc929, 0x32ff, 0xc929, 0x21, 0 - .dw 0x3340, 0xc929, 0x337f, 0xc929, 0x21, 0 - .dw 0x33c0, 0xc929, 0x33ff, 0xc929, 0x21, 0 - .dw 0x3440, 0xc929, 0x347f, 0xc929, 0x21, 0 - .dw 0x34c0, 0xc929, 0x34ff, 0xc929, 0x21, 0 - .dw 0x3540, 0xc929, 0x357f, 0xc929, 0x21, 0 - .dw 0x35c0, 0xc929, 0x35ff, 0xc929, 0x21, 0 - .dw 0x3640, 0xc929, 0x367f, 0xc929, 0x21, 0 - .dw 0x36c0, 0xc929, 0x36ff, 0xc929, 0x21, 0 - .dw 0x3740, 0xc929, 0x377f, 0xc929, 0x21, 0 - .dw 0x37c0, 0xc929, 0x37ff, 0xc929, 0x21, 0 - .dw 0x3840, 0xc929, 0x387f, 0xc929, 0x21, 0 - .dw 0x38c0, 0xc929, 0x38ff, 0xc929, 0x21, 0 - .dw 0x3940, 0xc929, 0x397f, 0xc929, 0x21, 0 - .dw 0x39c0, 0xc929, 0x5fff, 0xc929, 0x21, 0 - .dw 0x6040, 0xc929, 0x607f, 0xc929, 0x21, 0 - .dw 0x60c0, 0xc929, 0x60ff, 0xc929, 0x21, 0 - .dw 0x6140, 0xc929, 0x617f, 0xc929, 0x21, 0 - .dw 0x61c0, 0xc929, 0x61ff, 0xc929, 0x21, 0 - .dw 0x6240, 0xc929, 0x627f, 0xc929, 0x21, 0 - .dw 0x62c0, 0xc929, 0x62ff, 0xc929, 0x21, 0 - .dw 0x6340, 0xc929, 0x637f, 0xc929, 0x21, 0 - .dw 0x63c0, 0xc929, 0x63ff, 0xc929, 0x21, 0 - .dw 0x6440, 0xc929, 0x647f, 0xc929, 0x21, 0 - .dw 0x64c0, 0xc929, 0x64ff, 0xc929, 0x21, 0 - .dw 0x6540, 0xc929, 0x657f, 0xc929, 0x21, 0 - .dw 0x65c0, 0xc929, 0x65ff, 0xc929, 0x21, 0 - .dw 0x6640, 0xc929, 0x667f, 0xc929, 0x21, 0 - .dw 0x66c0, 0xc929, 0x66ff, 0xc929, 0x21, 0 - .dw 0x6740, 0xc929, 0x677f, 0xc929, 0x21, 0 - .dw 0x67c0, 0xc929, 0x67ff, 0xc929, 0x21, 0 - .dw 0x6840, 0xc929, 0x687f, 0xc929, 0x21, 0 - .dw 0x68c0, 0xc929, 0x68ff, 0xc929, 0x21, 0 - .dw 0x6940, 0xc929, 0x697f, 0xc929, 0x21, 0 - .dw 0x69c0, 0xc929, 0x69ff, 0xc929, 0x21, 0 - .dw 0x6a40, 0xc929, 0x6a7f, 0xc929, 0x21, 0 - .dw 0x6ac0, 0xc929, 0x6aff, 0xc929, 0x21, 0 - .dw 0x6b40, 0xc929, 0x6b7f, 0xc929, 0x21, 0 - .dw 0x6bc0, 0xc929, 0x6bff, 0xc929, 0x21, 0 - .dw 0x6c40, 0xc929, 0x6c7f, 0xc929, 0x21, 0 - .dw 0x6cc0, 0xc929, 0x6cff, 0xc929, 0x21, 0 - .dw 0x6d40, 0xc929, 0x6d7f, 0xc929, 0x21, 0 - .dw 0x6dc0, 0xc929, 0x6dff, 0xc929, 0x21, 0 - .dw 0x6e40, 0xc929, 0x6e7f, 0xc929, 0x21, 0 - .dw 0x6ec0, 0xc929, 0x6eff, 0xc929, 0x21, 0 - .dw 0x6f40, 0xc929, 0x6f7f, 0xc929, 0x21, 0 - .dw 0x6fc0, 0xc929, 0x6fff, 0xc929, 0x21, 0 - .dw 0x7040, 0xc929, 0x707f, 0xc929, 0x21, 0 - .dw 0x70c0, 0xc929, 0x70ff, 0xc929, 0x21, 0 - .dw 0x7140, 0xc929, 0x717f, 0xc929, 0x21, 0 - .dw 0x71c0, 0xc929, 0x71ff, 0xc929, 0x21, 0 - .dw 0x7240, 0xc929, 0x727f, 0xc929, 0x21, 0 - .dw 0x72c0, 0xc929, 0x72ff, 0xc929, 0x21, 0 - .dw 0x7340, 0xc929, 0x737f, 0xc929, 0x21, 0 - .dw 0x73c0, 0xc929, 0x73ff, 0xc929, 0x21, 0 - .dw 0x7440, 0xc929, 0x747f, 0xc929, 0x21, 0 - .dw 0x74c0, 0xc929, 0x74ff, 0xc929, 0x21, 0 - .dw 0x7540, 0xc929, 0x757f, 0xc929, 0x21, 0 - .dw 0x75c0, 0xc929, 0x75ff, 0xc929, 0x21, 0 - .dw 0x7640, 0xc929, 0x767f, 0xc929, 0x21, 0 - .dw 0x76c0, 0xc929, 0x76ff, 0xc929, 0x21, 0 - .dw 0x7740, 0xc929, 0x777f, 0xc929, 0x21, 0 - .dw 0x77c0, 0xc929, 0x77ff, 0xc929, 0x21, 0 - .dw 0x7840, 0xc929, 0x787f, 0xc929, 0x21, 0 - .dw 0x78c0, 0xc929, 0x78ff, 0xc929, 0x21, 0 - .dw 0x7940, 0xc929, 0x797f, 0xc929, 0x21, 0 - .dw 0x79c0, 0xc929, 0x9fff, 0xc929, 0x21, 0 - .dw 0xa040, 0xc929, 0xa07f, 0xc929, 0x21, 0 - .dw 0xa0c0, 0xc929, 0xa0ff, 0xc929, 0x21, 0 - .dw 0xa140, 0xc929, 0xa17f, 0xc929, 0x21, 0 - .dw 0xa1c0, 0xc929, 0xa1ff, 0xc929, 0x21, 0 - .dw 0xa240, 0xc929, 0xa27f, 0xc929, 0x21, 0 - .dw 0xa2c0, 0xc929, 0xa2ff, 0xc929, 0x21, 0 - .dw 0xa340, 0xc929, 0xa37f, 0xc929, 0x21, 0 - .dw 0xa3c0, 0xc929, 0xa3ff, 0xc929, 0x21, 0 - .dw 0xa440, 0xc929, 0xa47f, 0xc929, 0x21, 0 - .dw 0xa4c0, 0xc929, 0xa4ff, 0xc929, 0x21, 0 - .dw 0xa540, 0xc929, 0xa57f, 0xc929, 0x21, 0 - .dw 0xa5c0, 0xc929, 0xa5ff, 0xc929, 0x21, 0 - .dw 0xa640, 0xc929, 0xa67f, 0xc929, 0x21, 0 - .dw 0xa6c0, 0xc929, 0xa6ff, 0xc929, 0x21, 0 - .dw 0xa740, 0xc929, 0xa77f, 0xc929, 0x21, 0 - .dw 0xa7c0, 0xc929, 0xa7ff, 0xc929, 0x21, 0 - .dw 0xa840, 0xc929, 0xa87f, 0xc929, 0x21, 0 - .dw 0xa8c0, 0xc929, 0xa8ff, 0xc929, 0x21, 0 - .dw 0xa940, 0xc929, 0xa97f, 0xc929, 0x21, 0 - .dw 0xa9c0, 0xc929, 0xa9ff, 0xc929, 0x21, 0 - .dw 0xaa40, 0xc929, 0xaa7f, 0xc929, 0x21, 0 - .dw 0xaac0, 0xc929, 0xaaff, 0xc929, 0x21, 0 - .dw 0xab40, 0xc929, 0xab7f, 0xc929, 0x21, 0 - .dw 0xabc0, 0xc929, 0xabff, 0xc929, 0x21, 0 - .dw 0xac40, 0xc929, 0xac7f, 0xc929, 0x21, 0 - .dw 0xacc0, 0xc929, 0xacff, 0xc929, 0x21, 0 - .dw 0xad40, 0xc929, 0xad7f, 0xc929, 0x21, 0 - .dw 0xadc0, 0xc929, 0xadff, 0xc929, 0x21, 0 - .dw 0xae40, 0xc929, 0xae7f, 0xc929, 0x21, 0 - .dw 0xaec0, 0xc929, 0xaeff, 0xc929, 0x21, 0 - .dw 0xaf40, 0xc929, 0xaf7f, 0xc929, 0x21, 0 - .dw 0xafc0, 0xc929, 0xafff, 0xc929, 0x21, 0 - .dw 0xb040, 0xc929, 0xb07f, 0xc929, 0x21, 0 - .dw 0xb0c0, 0xc929, 0xb0ff, 0xc929, 0x21, 0 - .dw 0xb140, 0xc929, 0xb17f, 0xc929, 0x21, 0 - .dw 0xb1c0, 0xc929, 0xb1ff, 0xc929, 0x21, 0 - .dw 0xb240, 0xc929, 0xb27f, 0xc929, 0x21, 0 - .dw 0xb2c0, 0xc929, 0xb2ff, 0xc929, 0x21, 0 - .dw 0xb340, 0xc929, 0xb37f, 0xc929, 0x21, 0 - .dw 0xb3c0, 0xc929, 0xb3ff, 0xc929, 0x21, 0 - .dw 0xb440, 0xc929, 0xb47f, 0xc929, 0x21, 0 - .dw 0xb4c0, 0xc929, 0xb4ff, 0xc929, 0x21, 0 - .dw 0xb540, 0xc929, 0xb57f, 0xc929, 0x21, 0 - .dw 0xb5c0, 0xc929, 0xb5ff, 0xc929, 0x21, 0 - .dw 0xb640, 0xc929, 0xb67f, 0xc929, 0x21, 0 - .dw 0xb6c0, 0xc929, 0xb6ff, 0xc929, 0x21, 0 - .dw 0xb740, 0xc929, 0xb77f, 0xc929, 0x21, 0 - .dw 0xb7c0, 0xc929, 0xb7ff, 0xc929, 0x21, 0 - .dw 0xb840, 0xc929, 0xb87f, 0xc929, 0x21, 0 - .dw 0xb8c0, 0xc929, 0xb8ff, 0xc929, 0x21, 0 - .dw 0xb940, 0xc929, 0xb97f, 0xc929, 0x21, 0 - .dw 0xb9c0, 0xc929, 0xdfff, 0xc929, 0x21, 0 - .dw 0xe040, 0xc929, 0xe07f, 0xc929, 0x21, 0 - .dw 0xe0c0, 0xc929, 0xe0ff, 0xc929, 0x21, 0 - .dw 0xe140, 0xc929, 0xe17f, 0xc929, 0x21, 0 - .dw 0xe1c0, 0xc929, 0xe1ff, 0xc929, 0x21, 0 - .dw 0xe240, 0xc929, 0xe27f, 0xc929, 0x21, 0 - .dw 0xe2c0, 0xc929, 0xe2ff, 0xc929, 0x21, 0 - .dw 0xe340, 0xc929, 0xe37f, 0xc929, 0x21, 0 - .dw 0xe3c0, 0xc929, 0xe3ff, 0xc929, 0x21, 0 - .dw 0xe440, 0xc929, 0xe47f, 0xc929, 0x21, 0 - .dw 0xe4c0, 0xc929, 0xe4ff, 0xc929, 0x21, 0 - .dw 0xe540, 0xc929, 0xe57f, 0xc929, 0x21, 0 - .dw 0xe5c0, 0xc929, 0xe5ff, 0xc929, 0x21, 0 - .dw 0xe640, 0xc929, 0xe67f, 0xc929, 0x21, 0 - .dw 0xe6c0, 0xc929, 0xe6ff, 0xc929, 0x21, 0 - .dw 0xe740, 0xc929, 0xe77f, 0xc929, 0x21, 0 - .dw 0xe7c0, 0xc929, 0xe7ff, 0xc929, 0x21, 0 - .dw 0xe840, 0xc929, 0xe87f, 0xc929, 0x21, 0 - .dw 0xe8c0, 0xc929, 0xe8ff, 0xc929, 0x21, 0 - .dw 0xe940, 0xc929, 0xe97f, 0xc929, 0x21, 0 - .dw 0xe9c0, 0xc929, 0xe9ff, 0xc929, 0x21, 0 - .dw 0xea40, 0xc929, 0xea7f, 0xc929, 0x21, 0 - .dw 0xeac0, 0xc929, 0xeaff, 0xc929, 0x21, 0 - .dw 0xeb40, 0xc929, 0xeb7f, 0xc929, 0x21, 0 - .dw 0xebc0, 0xc929, 0xebff, 0xc929, 0x21, 0 - .dw 0xec40, 0xc929, 0xec7f, 0xc929, 0x21, 0 - .dw 0xecc0, 0xc929, 0xecff, 0xc929, 0x21, 0 - .dw 0xed40, 0xc929, 0xed7f, 0xc929, 0x21, 0 - .dw 0xedc0, 0xc929, 0xedff, 0xc929, 0x21, 0 - .dw 0xee40, 0xc929, 0xee7f, 0xc929, 0x21, 0 - .dw 0xeec0, 0xc929, 0xeeff, 0xc929, 0x21, 0 - .dw 0xef40, 0xc929, 0xef7f, 0xc929, 0x21, 0 - .dw 0xefc0, 0xc929, 0xefff, 0xc929, 0x21, 0 - .dw 0xf040, 0xc929, 0xf07f, 0xc929, 0x21, 0 - .dw 0xf0c0, 0xc929, 0xf0ff, 0xc929, 0x21, 0 - .dw 0xf140, 0xc929, 0xf17f, 0xc929, 0x21, 0 - .dw 0xf1c0, 0xc929, 0xf1ff, 0xc929, 0x21, 0 - .dw 0xf240, 0xc929, 0xf27f, 0xc929, 0x21, 0 - .dw 0xf2c0, 0xc929, 0xf2ff, 0xc929, 0x21, 0 - .dw 0xf340, 0xc929, 0xf37f, 0xc929, 0x21, 0 - .dw 0xf3c0, 0xc929, 0xf3ff, 0xc929, 0x21, 0 - .dw 0xf440, 0xc929, 0xf47f, 0xc929, 0x21, 0 - .dw 0xf4c0, 0xc929, 0xf4ff, 0xc929, 0x21, 0 - .dw 0xf540, 0xc929, 0xf57f, 0xc929, 0x21, 0 - .dw 0xf5c0, 0xc929, 0xf5ff, 0xc929, 0x21, 0 - .dw 0xf640, 0xc929, 0xf67f, 0xc929, 0x21, 0 - .dw 0xf6c0, 0xc929, 0xf6ff, 0xc929, 0x21, 0 - .dw 0xf740, 0xc929, 0xf77f, 0xc929, 0x21, 0 - .dw 0xf7c0, 0xc929, 0xf7ff, 0xc929, 0x21, 0 - .dw 0xf840, 0xc929, 0xf87f, 0xc929, 0x21, 0 - .dw 0xf8c0, 0xc929, 0xf8ff, 0xc929, 0x21, 0 - .dw 0xf940, 0xc929, 0xf97f, 0xc929, 0x21, 0 - .dw 0xf9c0, 0xc929, 0x1fff, 0xc92a, 0x21, 0 - .dw 0x2040, 0xc92a, 0x207f, 0xc92a, 0x21, 0 - .dw 0x20c0, 0xc92a, 0x20ff, 0xc92a, 0x21, 0 - .dw 0x2140, 0xc92a, 0x217f, 0xc92a, 0x21, 0 - .dw 0x21c0, 0xc92a, 0x21ff, 0xc92a, 0x21, 0 - .dw 0x2240, 0xc92a, 0x227f, 0xc92a, 0x21, 0 - .dw 0x22c0, 0xc92a, 0x22ff, 0xc92a, 0x21, 0 - .dw 0x2340, 0xc92a, 0x237f, 0xc92a, 0x21, 0 - .dw 0x23c0, 0xc92a, 0x23ff, 0xc92a, 0x21, 0 - .dw 0x2440, 0xc92a, 0x247f, 0xc92a, 0x21, 0 - .dw 0x24c0, 0xc92a, 0x24ff, 0xc92a, 0x21, 0 - .dw 0x2540, 0xc92a, 0x257f, 0xc92a, 0x21, 0 - .dw 0x25c0, 0xc92a, 0x25ff, 0xc92a, 0x21, 0 - .dw 0x2640, 0xc92a, 0x267f, 0xc92a, 0x21, 0 - .dw 0x26c0, 0xc92a, 0x26ff, 0xc92a, 0x21, 0 - .dw 0x2740, 0xc92a, 0x277f, 0xc92a, 0x21, 0 - .dw 0x27c0, 0xc92a, 0x27ff, 0xc92a, 0x21, 0 - .dw 0x2840, 0xc92a, 0x287f, 0xc92a, 0x21, 0 - .dw 0x28c0, 0xc92a, 0x28ff, 0xc92a, 0x21, 0 - .dw 0x2940, 0xc92a, 0x297f, 0xc92a, 0x21, 0 - .dw 0x29c0, 0xc92a, 0x29ff, 0xc92a, 0x21, 0 - .dw 0x2a40, 0xc92a, 0x2a7f, 0xc92a, 0x21, 0 - .dw 0x2ac0, 0xc92a, 0x2aff, 0xc92a, 0x21, 0 - .dw 0x2b40, 0xc92a, 0x2b7f, 0xc92a, 0x21, 0 - .dw 0x2bc0, 0xc92a, 0x2bff, 0xc92a, 0x21, 0 - .dw 0x2c40, 0xc92a, 0x2c7f, 0xc92a, 0x21, 0 - .dw 0x2cc0, 0xc92a, 0x2cff, 0xc92a, 0x21, 0 - .dw 0x2d40, 0xc92a, 0x2d7f, 0xc92a, 0x21, 0 - .dw 0x2dc0, 0xc92a, 0x2dff, 0xc92a, 0x21, 0 - .dw 0x2e40, 0xc92a, 0x2e7f, 0xc92a, 0x21, 0 - .dw 0x2ec0, 0xc92a, 0x2eff, 0xc92a, 0x21, 0 - .dw 0x2f40, 0xc92a, 0x2f7f, 0xc92a, 0x21, 0 - .dw 0x2fc0, 0xc92a, 0x2fff, 0xc92a, 0x21, 0 - .dw 0x3040, 0xc92a, 0x307f, 0xc92a, 0x21, 0 - .dw 0x30c0, 0xc92a, 0x30ff, 0xc92a, 0x21, 0 - .dw 0x3140, 0xc92a, 0x317f, 0xc92a, 0x21, 0 - .dw 0x31c0, 0xc92a, 0x31ff, 0xc92a, 0x21, 0 - .dw 0x3240, 0xc92a, 0x327f, 0xc92a, 0x21, 0 - .dw 0x32c0, 0xc92a, 0x32ff, 0xc92a, 0x21, 0 - .dw 0x3340, 0xc92a, 0x337f, 0xc92a, 0x21, 0 - .dw 0x33c0, 0xc92a, 0x33ff, 0xc92a, 0x21, 0 - .dw 0x3440, 0xc92a, 0x347f, 0xc92a, 0x21, 0 - .dw 0x34c0, 0xc92a, 0x34ff, 0xc92a, 0x21, 0 - .dw 0x3540, 0xc92a, 0x357f, 0xc92a, 0x21, 0 - .dw 0x35c0, 0xc92a, 0x35ff, 0xc92a, 0x21, 0 - .dw 0x3640, 0xc92a, 0x367f, 0xc92a, 0x21, 0 - .dw 0x36c0, 0xc92a, 0x36ff, 0xc92a, 0x21, 0 - .dw 0x3740, 0xc92a, 0x377f, 0xc92a, 0x21, 0 - .dw 0x37c0, 0xc92a, 0x37ff, 0xc92a, 0x21, 0 - .dw 0x3840, 0xc92a, 0x387f, 0xc92a, 0x21, 0 - .dw 0x38c0, 0xc92a, 0x38ff, 0xc92a, 0x21, 0 - .dw 0x3940, 0xc92a, 0x397f, 0xc92a, 0x21, 0 - .dw 0x39c0, 0xc92a, 0x5fff, 0xc92a, 0x21, 0 - .dw 0x6040, 0xc92a, 0x607f, 0xc92a, 0x21, 0 - .dw 0x60c0, 0xc92a, 0x60ff, 0xc92a, 0x21, 0 - .dw 0x6140, 0xc92a, 0x617f, 0xc92a, 0x21, 0 - .dw 0x61c0, 0xc92a, 0x61ff, 0xc92a, 0x21, 0 - .dw 0x6240, 0xc92a, 0x627f, 0xc92a, 0x21, 0 - .dw 0x62c0, 0xc92a, 0x62ff, 0xc92a, 0x21, 0 - .dw 0x6340, 0xc92a, 0x637f, 0xc92a, 0x21, 0 - .dw 0x63c0, 0xc92a, 0x63ff, 0xc92a, 0x21, 0 - .dw 0x6440, 0xc92a, 0x647f, 0xc92a, 0x21, 0 - .dw 0x64c0, 0xc92a, 0x64ff, 0xc92a, 0x21, 0 - .dw 0x6540, 0xc92a, 0x657f, 0xc92a, 0x21, 0 - .dw 0x65c0, 0xc92a, 0x65ff, 0xc92a, 0x21, 0 - .dw 0x6640, 0xc92a, 0x667f, 0xc92a, 0x21, 0 - .dw 0x66c0, 0xc92a, 0x66ff, 0xc92a, 0x21, 0 - .dw 0x6740, 0xc92a, 0x677f, 0xc92a, 0x21, 0 - .dw 0x67c0, 0xc92a, 0x67ff, 0xc92a, 0x21, 0 - .dw 0x6840, 0xc92a, 0x687f, 0xc92a, 0x21, 0 - .dw 0x68c0, 0xc92a, 0x68ff, 0xc92a, 0x21, 0 - .dw 0x6940, 0xc92a, 0x697f, 0xc92a, 0x21, 0 - .dw 0x69c0, 0xc92a, 0x69ff, 0xc92a, 0x21, 0 - .dw 0x6a40, 0xc92a, 0x6a7f, 0xc92a, 0x21, 0 - .dw 0x6ac0, 0xc92a, 0x6aff, 0xc92a, 0x21, 0 - .dw 0x6b40, 0xc92a, 0x6b7f, 0xc92a, 0x21, 0 - .dw 0x6bc0, 0xc92a, 0x6bff, 0xc92a, 0x21, 0 - .dw 0x6c40, 0xc92a, 0x6c7f, 0xc92a, 0x21, 0 - .dw 0x6cc0, 0xc92a, 0x6cff, 0xc92a, 0x21, 0 - .dw 0x6d40, 0xc92a, 0x6d7f, 0xc92a, 0x21, 0 - .dw 0x6dc0, 0xc92a, 0x6dff, 0xc92a, 0x21, 0 - .dw 0x6e40, 0xc92a, 0x6e7f, 0xc92a, 0x21, 0 - .dw 0x6ec0, 0xc92a, 0x6eff, 0xc92a, 0x21, 0 - .dw 0x6f40, 0xc92a, 0x6f7f, 0xc92a, 0x21, 0 - .dw 0x6fc0, 0xc92a, 0x6fff, 0xc92a, 0x21, 0 - .dw 0x7040, 0xc92a, 0x707f, 0xc92a, 0x21, 0 - .dw 0x70c0, 0xc92a, 0x70ff, 0xc92a, 0x21, 0 - .dw 0x7140, 0xc92a, 0x717f, 0xc92a, 0x21, 0 - .dw 0x71c0, 0xc92a, 0x71ff, 0xc92a, 0x21, 0 - .dw 0x7240, 0xc92a, 0x727f, 0xc92a, 0x21, 0 - .dw 0x72c0, 0xc92a, 0x72ff, 0xc92a, 0x21, 0 - .dw 0x7340, 0xc92a, 0x737f, 0xc92a, 0x21, 0 - .dw 0x73c0, 0xc92a, 0x73ff, 0xc92a, 0x21, 0 - .dw 0x7440, 0xc92a, 0x747f, 0xc92a, 0x21, 0 - .dw 0x74c0, 0xc92a, 0x74ff, 0xc92a, 0x21, 0 - .dw 0x7540, 0xc92a, 0x757f, 0xc92a, 0x21, 0 - .dw 0x75c0, 0xc92a, 0x75ff, 0xc92a, 0x21, 0 - .dw 0x7640, 0xc92a, 0x767f, 0xc92a, 0x21, 0 - .dw 0x76c0, 0xc92a, 0x76ff, 0xc92a, 0x21, 0 - .dw 0x7740, 0xc92a, 0x777f, 0xc92a, 0x21, 0 - .dw 0x77c0, 0xc92a, 0x77ff, 0xc92a, 0x21, 0 - .dw 0x7840, 0xc92a, 0x787f, 0xc92a, 0x21, 0 - .dw 0x78c0, 0xc92a, 0x78ff, 0xc92a, 0x21, 0 - .dw 0x7940, 0xc92a, 0x797f, 0xc92a, 0x21, 0 - .dw 0x79c0, 0xc92a, 0x9fff, 0xc92a, 0x21, 0 - .dw 0xa040, 0xc92a, 0xa07f, 0xc92a, 0x21, 0 - .dw 0xa0c0, 0xc92a, 0xa0ff, 0xc92a, 0x21, 0 - .dw 0xa140, 0xc92a, 0xa17f, 0xc92a, 0x21, 0 - .dw 0xa1c0, 0xc92a, 0xa1ff, 0xc92a, 0x21, 0 - .dw 0xa240, 0xc92a, 0xa27f, 0xc92a, 0x21, 0 - .dw 0xa2c0, 0xc92a, 0xa2ff, 0xc92a, 0x21, 0 - .dw 0xa340, 0xc92a, 0xa37f, 0xc92a, 0x21, 0 - .dw 0xa3c0, 0xc92a, 0xa3ff, 0xc92a, 0x21, 0 - .dw 0xa440, 0xc92a, 0xa47f, 0xc92a, 0x21, 0 - .dw 0xa4c0, 0xc92a, 0xa4ff, 0xc92a, 0x21, 0 - .dw 0xa540, 0xc92a, 0xa57f, 0xc92a, 0x21, 0 - .dw 0xa5c0, 0xc92a, 0xa5ff, 0xc92a, 0x21, 0 - .dw 0xa640, 0xc92a, 0xa67f, 0xc92a, 0x21, 0 - .dw 0xa6c0, 0xc92a, 0xa6ff, 0xc92a, 0x21, 0 - .dw 0xa740, 0xc92a, 0xa77f, 0xc92a, 0x21, 0 - .dw 0xa7c0, 0xc92a, 0xa7ff, 0xc92a, 0x21, 0 - .dw 0xa840, 0xc92a, 0xa87f, 0xc92a, 0x21, 0 - .dw 0xa8c0, 0xc92a, 0xa8ff, 0xc92a, 0x21, 0 - .dw 0xa940, 0xc92a, 0xa97f, 0xc92a, 0x21, 0 - .dw 0xa9c0, 0xc92a, 0xa9ff, 0xc92a, 0x21, 0 - .dw 0xaa40, 0xc92a, 0xaa7f, 0xc92a, 0x21, 0 - .dw 0xaac0, 0xc92a, 0xaaff, 0xc92a, 0x21, 0 - .dw 0xab40, 0xc92a, 0xab7f, 0xc92a, 0x21, 0 - .dw 0xabc0, 0xc92a, 0xabff, 0xc92a, 0x21, 0 - .dw 0xac40, 0xc92a, 0xac7f, 0xc92a, 0x21, 0 - .dw 0xacc0, 0xc92a, 0xacff, 0xc92a, 0x21, 0 - .dw 0xad40, 0xc92a, 0xad7f, 0xc92a, 0x21, 0 - .dw 0xadc0, 0xc92a, 0xadff, 0xc92a, 0x21, 0 - .dw 0xae40, 0xc92a, 0xae7f, 0xc92a, 0x21, 0 - .dw 0xaec0, 0xc92a, 0xaeff, 0xc92a, 0x21, 0 - .dw 0xaf40, 0xc92a, 0xaf7f, 0xc92a, 0x21, 0 - .dw 0xafc0, 0xc92a, 0xafff, 0xc92a, 0x21, 0 - .dw 0xb040, 0xc92a, 0xb07f, 0xc92a, 0x21, 0 - .dw 0xb0c0, 0xc92a, 0xb0ff, 0xc92a, 0x21, 0 - .dw 0xb140, 0xc92a, 0xb17f, 0xc92a, 0x21, 0 - .dw 0xb1c0, 0xc92a, 0xb1ff, 0xc92a, 0x21, 0 - .dw 0xb240, 0xc92a, 0xb27f, 0xc92a, 0x21, 0 - .dw 0xb2c0, 0xc92a, 0xb2ff, 0xc92a, 0x21, 0 - .dw 0xb340, 0xc92a, 0xb37f, 0xc92a, 0x21, 0 - .dw 0xb3c0, 0xc92a, 0xb3ff, 0xc92a, 0x21, 0 - .dw 0xb440, 0xc92a, 0xb47f, 0xc92a, 0x21, 0 - .dw 0xb4c0, 0xc92a, 0xb4ff, 0xc92a, 0x21, 0 - .dw 0xb540, 0xc92a, 0xb57f, 0xc92a, 0x21, 0 - .dw 0xb5c0, 0xc92a, 0xb5ff, 0xc92a, 0x21, 0 - .dw 0xb640, 0xc92a, 0xb67f, 0xc92a, 0x21, 0 - .dw 0xb6c0, 0xc92a, 0xb6ff, 0xc92a, 0x21, 0 - .dw 0xb740, 0xc92a, 0xb77f, 0xc92a, 0x21, 0 - .dw 0xb7c0, 0xc92a, 0xb7ff, 0xc92a, 0x21, 0 - .dw 0xb840, 0xc92a, 0xb87f, 0xc92a, 0x21, 0 - .dw 0xb8c0, 0xc92a, 0xb8ff, 0xc92a, 0x21, 0 - .dw 0xb940, 0xc92a, 0xb97f, 0xc92a, 0x21, 0 - .dw 0xb9c0, 0xc92a, 0xdfff, 0xc92a, 0x21, 0 - .dw 0xe040, 0xc92a, 0xe07f, 0xc92a, 0x21, 0 - .dw 0xe0c0, 0xc92a, 0xe0ff, 0xc92a, 0x21, 0 - .dw 0xe140, 0xc92a, 0xe17f, 0xc92a, 0x21, 0 - .dw 0xe1c0, 0xc92a, 0xe1ff, 0xc92a, 0x21, 0 - .dw 0xe240, 0xc92a, 0xe27f, 0xc92a, 0x21, 0 - .dw 0xe2c0, 0xc92a, 0xe2ff, 0xc92a, 0x21, 0 - .dw 0xe340, 0xc92a, 0xe37f, 0xc92a, 0x21, 0 - .dw 0xe3c0, 0xc92a, 0xe3ff, 0xc92a, 0x21, 0 - .dw 0xe440, 0xc92a, 0xe47f, 0xc92a, 0x21, 0 - .dw 0xe4c0, 0xc92a, 0xe4ff, 0xc92a, 0x21, 0 - .dw 0xe540, 0xc92a, 0xe57f, 0xc92a, 0x21, 0 - .dw 0xe5c0, 0xc92a, 0xe5ff, 0xc92a, 0x21, 0 - .dw 0xe640, 0xc92a, 0xe67f, 0xc92a, 0x21, 0 - .dw 0xe6c0, 0xc92a, 0xe6ff, 0xc92a, 0x21, 0 - .dw 0xe740, 0xc92a, 0xe77f, 0xc92a, 0x21, 0 - .dw 0xe7c0, 0xc92a, 0xe7ff, 0xc92a, 0x21, 0 - .dw 0xe840, 0xc92a, 0xe87f, 0xc92a, 0x21, 0 - .dw 0xe8c0, 0xc92a, 0xe8ff, 0xc92a, 0x21, 0 - .dw 0xe940, 0xc92a, 0xe97f, 0xc92a, 0x21, 0 - .dw 0xe9c0, 0xc92a, 0xe9ff, 0xc92a, 0x21, 0 - .dw 0xea40, 0xc92a, 0xea7f, 0xc92a, 0x21, 0 - .dw 0xeac0, 0xc92a, 0xeaff, 0xc92a, 0x21, 0 - .dw 0xeb40, 0xc92a, 0xeb7f, 0xc92a, 0x21, 0 - .dw 0xebc0, 0xc92a, 0xebff, 0xc92a, 0x21, 0 - .dw 0xec40, 0xc92a, 0xec7f, 0xc92a, 0x21, 0 - .dw 0xecc0, 0xc92a, 0xecff, 0xc92a, 0x21, 0 - .dw 0xed40, 0xc92a, 0xed7f, 0xc92a, 0x21, 0 - .dw 0xedc0, 0xc92a, 0xedff, 0xc92a, 0x21, 0 - .dw 0xee40, 0xc92a, 0xee7f, 0xc92a, 0x21, 0 - .dw 0xeec0, 0xc92a, 0xeeff, 0xc92a, 0x21, 0 - .dw 0xef40, 0xc92a, 0xef7f, 0xc92a, 0x21, 0 - .dw 0xefc0, 0xc92a, 0xefff, 0xc92a, 0x21, 0 - .dw 0xf040, 0xc92a, 0xf07f, 0xc92a, 0x21, 0 - .dw 0xf0c0, 0xc92a, 0xf0ff, 0xc92a, 0x21, 0 - .dw 0xf140, 0xc92a, 0xf17f, 0xc92a, 0x21, 0 - .dw 0xf1c0, 0xc92a, 0xf1ff, 0xc92a, 0x21, 0 - .dw 0xf240, 0xc92a, 0xf27f, 0xc92a, 0x21, 0 - .dw 0xf2c0, 0xc92a, 0xf2ff, 0xc92a, 0x21, 0 - .dw 0xf340, 0xc92a, 0xf37f, 0xc92a, 0x21, 0 - .dw 0xf3c0, 0xc92a, 0xf3ff, 0xc92a, 0x21, 0 - .dw 0xf440, 0xc92a, 0xf47f, 0xc92a, 0x21, 0 - .dw 0xf4c0, 0xc92a, 0xf4ff, 0xc92a, 0x21, 0 - .dw 0xf540, 0xc92a, 0xf57f, 0xc92a, 0x21, 0 - .dw 0xf5c0, 0xc92a, 0xf5ff, 0xc92a, 0x21, 0 - .dw 0xf640, 0xc92a, 0xf67f, 0xc92a, 0x21, 0 - .dw 0xf6c0, 0xc92a, 0xf6ff, 0xc92a, 0x21, 0 - .dw 0xf740, 0xc92a, 0xf77f, 0xc92a, 0x21, 0 - .dw 0xf7c0, 0xc92a, 0xf7ff, 0xc92a, 0x21, 0 - .dw 0xf840, 0xc92a, 0xf87f, 0xc92a, 0x21, 0 - .dw 0xf8c0, 0xc92a, 0xf8ff, 0xc92a, 0x21, 0 - .dw 0xf940, 0xc92a, 0xf97f, 0xc92a, 0x21, 0 - .dw 0xf9c0, 0xc92a, 0x1fff, 0xc92b, 0x21, 0 - .dw 0x2040, 0xc92b, 0x207f, 0xc92b, 0x21, 0 - .dw 0x20c0, 0xc92b, 0x20ff, 0xc92b, 0x21, 0 - .dw 0x2140, 0xc92b, 0x217f, 0xc92b, 0x21, 0 - .dw 0x21c0, 0xc92b, 0x21ff, 0xc92b, 0x21, 0 - .dw 0x2240, 0xc92b, 0x227f, 0xc92b, 0x21, 0 - .dw 0x22c0, 0xc92b, 0x22ff, 0xc92b, 0x21, 0 - .dw 0x2340, 0xc92b, 0x237f, 0xc92b, 0x21, 0 - .dw 0x23c0, 0xc92b, 0x23ff, 0xc92b, 0x21, 0 - .dw 0x2440, 0xc92b, 0x247f, 0xc92b, 0x21, 0 - .dw 0x24c0, 0xc92b, 0x24ff, 0xc92b, 0x21, 0 - .dw 0x2540, 0xc92b, 0x257f, 0xc92b, 0x21, 0 - .dw 0x25c0, 0xc92b, 0x25ff, 0xc92b, 0x21, 0 - .dw 0x2640, 0xc92b, 0x267f, 0xc92b, 0x21, 0 - .dw 0x26c0, 0xc92b, 0x26ff, 0xc92b, 0x21, 0 - .dw 0x2740, 0xc92b, 0x277f, 0xc92b, 0x21, 0 - .dw 0x27c0, 0xc92b, 0x27ff, 0xc92b, 0x21, 0 - .dw 0x2840, 0xc92b, 0x287f, 0xc92b, 0x21, 0 - .dw 0x28c0, 0xc92b, 0x28ff, 0xc92b, 0x21, 0 - .dw 0x2940, 0xc92b, 0x297f, 0xc92b, 0x21, 0 - .dw 0x29c0, 0xc92b, 0x29ff, 0xc92b, 0x21, 0 - .dw 0x2a40, 0xc92b, 0x2a7f, 0xc92b, 0x21, 0 - .dw 0x2ac0, 0xc92b, 0x2aff, 0xc92b, 0x21, 0 - .dw 0x2b40, 0xc92b, 0x2b7f, 0xc92b, 0x21, 0 - .dw 0x2bc0, 0xc92b, 0x2bff, 0xc92b, 0x21, 0 - .dw 0x2c40, 0xc92b, 0x2c7f, 0xc92b, 0x21, 0 - .dw 0x2cc0, 0xc92b, 0x2cff, 0xc92b, 0x21, 0 - .dw 0x2d40, 0xc92b, 0x2d7f, 0xc92b, 0x21, 0 - .dw 0x2dc0, 0xc92b, 0x2dff, 0xc92b, 0x21, 0 - .dw 0x2e40, 0xc92b, 0x2e7f, 0xc92b, 0x21, 0 - .dw 0x2ec0, 0xc92b, 0x2eff, 0xc92b, 0x21, 0 - .dw 0x2f40, 0xc92b, 0x2f7f, 0xc92b, 0x21, 0 - .dw 0x2fc0, 0xc92b, 0x2fff, 0xc92b, 0x21, 0 - .dw 0x3040, 0xc92b, 0x307f, 0xc92b, 0x21, 0 - .dw 0x30c0, 0xc92b, 0x30ff, 0xc92b, 0x21, 0 - .dw 0x3140, 0xc92b, 0x317f, 0xc92b, 0x21, 0 - .dw 0x31c0, 0xc92b, 0x31ff, 0xc92b, 0x21, 0 - .dw 0x3240, 0xc92b, 0x327f, 0xc92b, 0x21, 0 - .dw 0x32c0, 0xc92b, 0x32ff, 0xc92b, 0x21, 0 - .dw 0x3340, 0xc92b, 0x337f, 0xc92b, 0x21, 0 - .dw 0x33c0, 0xc92b, 0x33ff, 0xc92b, 0x21, 0 - .dw 0x3440, 0xc92b, 0x347f, 0xc92b, 0x21, 0 - .dw 0x34c0, 0xc92b, 0x34ff, 0xc92b, 0x21, 0 - .dw 0x3540, 0xc92b, 0x357f, 0xc92b, 0x21, 0 - .dw 0x35c0, 0xc92b, 0x35ff, 0xc92b, 0x21, 0 - .dw 0x3640, 0xc92b, 0x367f, 0xc92b, 0x21, 0 - .dw 0x36c0, 0xc92b, 0x36ff, 0xc92b, 0x21, 0 - .dw 0x3740, 0xc92b, 0x377f, 0xc92b, 0x21, 0 - .dw 0x37c0, 0xc92b, 0x37ff, 0xc92b, 0x21, 0 - .dw 0x3840, 0xc92b, 0x387f, 0xc92b, 0x21, 0 - .dw 0x38c0, 0xc92b, 0x38ff, 0xc92b, 0x21, 0 - .dw 0x3940, 0xc92b, 0x397f, 0xc92b, 0x21, 0 - .dw 0x39c0, 0xc92b, 0xffff, 0xc92b, 0x21, 0 - .dw 0x0040, 0xc92c, 0x007f, 0xc92c, 0x21, 0 - .dw 0x00c0, 0xc92c, 0x00ff, 0xc92c, 0x21, 0 - .dw 0x0140, 0xc92c, 0x017f, 0xc92c, 0x21, 0 - .dw 0x01c0, 0xc92c, 0x01ff, 0xc92c, 0x21, 0 - .dw 0x0240, 0xc92c, 0x027f, 0xc92c, 0x21, 0 - .dw 0x02c0, 0xc92c, 0x02ff, 0xc92c, 0x21, 0 - .dw 0x0340, 0xc92c, 0x037f, 0xc92c, 0x21, 0 - .dw 0x03c0, 0xc92c, 0x03ff, 0xc92c, 0x21, 0 - .dw 0x0440, 0xc92c, 0x047f, 0xc92c, 0x21, 0 - .dw 0x04c0, 0xc92c, 0x04ff, 0xc92c, 0x21, 0 - .dw 0x0540, 0xc92c, 0x057f, 0xc92c, 0x21, 0 - .dw 0x05c0, 0xc92c, 0x05ff, 0xc92c, 0x21, 0 - .dw 0x0640, 0xc92c, 0x067f, 0xc92c, 0x21, 0 - .dw 0x06c0, 0xc92c, 0x06ff, 0xc92c, 0x21, 0 - .dw 0x0740, 0xc92c, 0x077f, 0xc92c, 0x21, 0 - .dw 0x07c0, 0xc92c, 0x07ff, 0xc92c, 0x21, 0 - .dw 0x0840, 0xc92c, 0x087f, 0xc92c, 0x21, 0 - .dw 0x08c0, 0xc92c, 0x08ff, 0xc92c, 0x21, 0 - .dw 0x0940, 0xc92c, 0x097f, 0xc92c, 0x21, 0 - .dw 0x09c0, 0xc92c, 0x09ff, 0xc92c, 0x21, 0 - .dw 0x0a40, 0xc92c, 0x0a7f, 0xc92c, 0x21, 0 - .dw 0x0ac0, 0xc92c, 0x0aff, 0xc92c, 0x21, 0 - .dw 0x0b40, 0xc92c, 0x0b7f, 0xc92c, 0x21, 0 - .dw 0x0bc0, 0xc92c, 0x0bff, 0xc92c, 0x21, 0 - .dw 0x0c40, 0xc92c, 0x0c7f, 0xc92c, 0x21, 0 - .dw 0x0cc0, 0xc92c, 0x0cff, 0xc92c, 0x21, 0 - .dw 0x0d40, 0xc92c, 0x0d7f, 0xc92c, 0x21, 0 - .dw 0x0dc0, 0xc92c, 0x0dff, 0xc92c, 0x21, 0 - .dw 0x0e40, 0xc92c, 0x0e7f, 0xc92c, 0x21, 0 - .dw 0x0ec0, 0xc92c, 0x0eff, 0xc92c, 0x21, 0 - .dw 0x0f40, 0xc92c, 0x0f7f, 0xc92c, 0x21, 0 - .dw 0x0fc0, 0xc92c, 0x0fff, 0xc92c, 0x21, 0 - .dw 0x1040, 0xc92c, 0x107f, 0xc92c, 0x21, 0 - .dw 0x10c0, 0xc92c, 0x10ff, 0xc92c, 0x21, 0 - .dw 0x1140, 0xc92c, 0x117f, 0xc92c, 0x21, 0 - .dw 0x11c0, 0xc92c, 0x11ff, 0xc92c, 0x21, 0 - .dw 0x1240, 0xc92c, 0x127f, 0xc92c, 0x21, 0 - .dw 0x12c0, 0xc92c, 0x12ff, 0xc92c, 0x21, 0 - .dw 0x1340, 0xc92c, 0x137f, 0xc92c, 0x21, 0 - .dw 0x13c0, 0xc92c, 0x13ff, 0xc92c, 0x21, 0 - .dw 0x1440, 0xc92c, 0x147f, 0xc92c, 0x21, 0 - .dw 0x14c0, 0xc92c, 0x14ff, 0xc92c, 0x21, 0 - .dw 0x1540, 0xc92c, 0x157f, 0xc92c, 0x21, 0 - .dw 0x15c0, 0xc92c, 0x15ff, 0xc92c, 0x21, 0 - .dw 0x1640, 0xc92c, 0x167f, 0xc92c, 0x21, 0 - .dw 0x16c0, 0xc92c, 0x16ff, 0xc92c, 0x21, 0 - .dw 0x1740, 0xc92c, 0x177f, 0xc92c, 0x21, 0 - .dw 0x17c0, 0xc92c, 0x17ff, 0xc92c, 0x21, 0 - .dw 0x1840, 0xc92c, 0x187f, 0xc92c, 0x21, 0 - .dw 0x18c0, 0xc92c, 0x18ff, 0xc92c, 0x21, 0 - .dw 0x1940, 0xc92c, 0x197f, 0xc92c, 0x21, 0 - .dw 0x19c0, 0xc92c, 0x1fff, 0xc92c, 0x21, 0 - .dw 0x2040, 0xc92c, 0x207f, 0xc92c, 0x21, 0 - .dw 0x20c0, 0xc92c, 0x20ff, 0xc92c, 0x21, 0 - .dw 0x2140, 0xc92c, 0x217f, 0xc92c, 0x21, 0 - .dw 0x21c0, 0xc92c, 0x21ff, 0xc92c, 0x21, 0 - .dw 0x2240, 0xc92c, 0x227f, 0xc92c, 0x21, 0 - .dw 0x22c0, 0xc92c, 0x22ff, 0xc92c, 0x21, 0 - .dw 0x2340, 0xc92c, 0x237f, 0xc92c, 0x21, 0 - .dw 0x23c0, 0xc92c, 0x23ff, 0xc92c, 0x21, 0 - .dw 0x2440, 0xc92c, 0x247f, 0xc92c, 0x21, 0 - .dw 0x24c0, 0xc92c, 0x24ff, 0xc92c, 0x21, 0 - .dw 0x2540, 0xc92c, 0x257f, 0xc92c, 0x21, 0 - .dw 0x25c0, 0xc92c, 0x25ff, 0xc92c, 0x21, 0 - .dw 0x2640, 0xc92c, 0x267f, 0xc92c, 0x21, 0 - .dw 0x26c0, 0xc92c, 0x26ff, 0xc92c, 0x21, 0 - .dw 0x2740, 0xc92c, 0x277f, 0xc92c, 0x21, 0 - .dw 0x27c0, 0xc92c, 0x27ff, 0xc92c, 0x21, 0 - .dw 0x2840, 0xc92c, 0x287f, 0xc92c, 0x21, 0 - .dw 0x28c0, 0xc92c, 0x28ff, 0xc92c, 0x21, 0 - .dw 0x2940, 0xc92c, 0x297f, 0xc92c, 0x21, 0 - .dw 0x29c0, 0xc92c, 0x29ff, 0xc92c, 0x21, 0 - .dw 0x2a40, 0xc92c, 0x2a7f, 0xc92c, 0x21, 0 - .dw 0x2ac0, 0xc92c, 0x2aff, 0xc92c, 0x21, 0 - .dw 0x2b40, 0xc92c, 0x2b7f, 0xc92c, 0x21, 0 - .dw 0x2bc0, 0xc92c, 0x2bff, 0xc92c, 0x21, 0 - .dw 0x2c40, 0xc92c, 0x2c7f, 0xc92c, 0x21, 0 - .dw 0x2cc0, 0xc92c, 0x2cff, 0xc92c, 0x21, 0 - .dw 0x2d40, 0xc92c, 0x2d7f, 0xc92c, 0x21, 0 - .dw 0x2dc0, 0xc92c, 0x2dff, 0xc92c, 0x21, 0 - .dw 0x2e40, 0xc92c, 0x2e7f, 0xc92c, 0x21, 0 - .dw 0x2ec0, 0xc92c, 0x2eff, 0xc92c, 0x21, 0 - .dw 0x2f40, 0xc92c, 0x2f7f, 0xc92c, 0x21, 0 - .dw 0x2fc0, 0xc92c, 0x2fff, 0xc92c, 0x21, 0 - .dw 0x3040, 0xc92c, 0x307f, 0xc92c, 0x21, 0 - .dw 0x30c0, 0xc92c, 0x30ff, 0xc92c, 0x21, 0 - .dw 0x3140, 0xc92c, 0x317f, 0xc92c, 0x21, 0 - .dw 0x31c0, 0xc92c, 0x31ff, 0xc92c, 0x21, 0 - .dw 0x3240, 0xc92c, 0x327f, 0xc92c, 0x21, 0 - .dw 0x32c0, 0xc92c, 0x32ff, 0xc92c, 0x21, 0 - .dw 0x3340, 0xc92c, 0x337f, 0xc92c, 0x21, 0 - .dw 0x33c0, 0xc92c, 0x33ff, 0xc92c, 0x21, 0 - .dw 0x3440, 0xc92c, 0x347f, 0xc92c, 0x21, 0 - .dw 0x34c0, 0xc92c, 0x34ff, 0xc92c, 0x21, 0 - .dw 0x3540, 0xc92c, 0x357f, 0xc92c, 0x21, 0 - .dw 0x35c0, 0xc92c, 0x35ff, 0xc92c, 0x21, 0 - .dw 0x3640, 0xc92c, 0x367f, 0xc92c, 0x21, 0 - .dw 0x36c0, 0xc92c, 0x36ff, 0xc92c, 0x21, 0 - .dw 0x3740, 0xc92c, 0x377f, 0xc92c, 0x21, 0 - .dw 0x37c0, 0xc92c, 0x37ff, 0xc92c, 0x21, 0 - .dw 0x3840, 0xc92c, 0x387f, 0xc92c, 0x21, 0 - .dw 0x38c0, 0xc92c, 0x38ff, 0xc92c, 0x21, 0 - .dw 0x3940, 0xc92c, 0x397f, 0xc92c, 0x21, 0 - .dw 0x39c0, 0xc92c, 0x3fff, 0xc92c, 0x21, 0 - .dw 0x4040, 0xc92c, 0x407f, 0xc92c, 0x21, 0 - .dw 0x40c0, 0xc92c, 0x40ff, 0xc92c, 0x21, 0 - .dw 0x4140, 0xc92c, 0x417f, 0xc92c, 0x21, 0 - .dw 0x41c0, 0xc92c, 0x41ff, 0xc92c, 0x21, 0 - .dw 0x4240, 0xc92c, 0x427f, 0xc92c, 0x21, 0 - .dw 0x42c0, 0xc92c, 0x42ff, 0xc92c, 0x21, 0 - .dw 0x4340, 0xc92c, 0x437f, 0xc92c, 0x21, 0 - .dw 0x43c0, 0xc92c, 0x43ff, 0xc92c, 0x21, 0 - .dw 0x4440, 0xc92c, 0x447f, 0xc92c, 0x21, 0 - .dw 0x44c0, 0xc92c, 0x44ff, 0xc92c, 0x21, 0 - .dw 0x4540, 0xc92c, 0x457f, 0xc92c, 0x21, 0 - .dw 0x45c0, 0xc92c, 0x45ff, 0xc92c, 0x21, 0 - .dw 0x4640, 0xc92c, 0x467f, 0xc92c, 0x21, 0 - .dw 0x46c0, 0xc92c, 0x46ff, 0xc92c, 0x21, 0 - .dw 0x4740, 0xc92c, 0x477f, 0xc92c, 0x21, 0 - .dw 0x47c0, 0xc92c, 0x47ff, 0xc92c, 0x21, 0 - .dw 0x4840, 0xc92c, 0x487f, 0xc92c, 0x21, 0 - .dw 0x48c0, 0xc92c, 0x48ff, 0xc92c, 0x21, 0 - .dw 0x4940, 0xc92c, 0x497f, 0xc92c, 0x21, 0 - .dw 0x49c0, 0xc92c, 0x49ff, 0xc92c, 0x21, 0 - .dw 0x4a40, 0xc92c, 0x4a7f, 0xc92c, 0x21, 0 - .dw 0x4ac0, 0xc92c, 0x4aff, 0xc92c, 0x21, 0 - .dw 0x4b40, 0xc92c, 0x4b7f, 0xc92c, 0x21, 0 - .dw 0x4bc0, 0xc92c, 0x4bff, 0xc92c, 0x21, 0 - .dw 0x4c40, 0xc92c, 0x4c7f, 0xc92c, 0x21, 0 - .dw 0x4cc0, 0xc92c, 0x4cff, 0xc92c, 0x21, 0 - .dw 0x4d40, 0xc92c, 0x4d7f, 0xc92c, 0x21, 0 - .dw 0x4dc0, 0xc92c, 0x4dff, 0xc92c, 0x21, 0 - .dw 0x4e40, 0xc92c, 0x4e7f, 0xc92c, 0x21, 0 - .dw 0x4ec0, 0xc92c, 0x4eff, 0xc92c, 0x21, 0 - .dw 0x4f40, 0xc92c, 0x4f7f, 0xc92c, 0x21, 0 - .dw 0x4fc0, 0xc92c, 0x4fff, 0xc92c, 0x21, 0 - .dw 0x5040, 0xc92c, 0x507f, 0xc92c, 0x21, 0 - .dw 0x50c0, 0xc92c, 0x50ff, 0xc92c, 0x21, 0 - .dw 0x5140, 0xc92c, 0x517f, 0xc92c, 0x21, 0 - .dw 0x51c0, 0xc92c, 0x51ff, 0xc92c, 0x21, 0 - .dw 0x5240, 0xc92c, 0x527f, 0xc92c, 0x21, 0 - .dw 0x52c0, 0xc92c, 0x52ff, 0xc92c, 0x21, 0 - .dw 0x5340, 0xc92c, 0x537f, 0xc92c, 0x21, 0 - .dw 0x53c0, 0xc92c, 0x53ff, 0xc92c, 0x21, 0 - .dw 0x5440, 0xc92c, 0x547f, 0xc92c, 0x21, 0 - .dw 0x54c0, 0xc92c, 0x54ff, 0xc92c, 0x21, 0 - .dw 0x5540, 0xc92c, 0x557f, 0xc92c, 0x21, 0 - .dw 0x55c0, 0xc92c, 0x55ff, 0xc92c, 0x21, 0 - .dw 0x5640, 0xc92c, 0x567f, 0xc92c, 0x21, 0 - .dw 0x56c0, 0xc92c, 0x56ff, 0xc92c, 0x21, 0 - .dw 0x5740, 0xc92c, 0x577f, 0xc92c, 0x21, 0 - .dw 0x57c0, 0xc92c, 0x57ff, 0xc92c, 0x21, 0 - .dw 0x5840, 0xc92c, 0x587f, 0xc92c, 0x21, 0 - .dw 0x58c0, 0xc92c, 0x58ff, 0xc92c, 0x21, 0 - .dw 0x5940, 0xc92c, 0x597f, 0xc92c, 0x21, 0 - .dw 0x59c0, 0xc92c, 0x5fff, 0xc92c, 0x21, 0 - .dw 0x6040, 0xc92c, 0x607f, 0xc92c, 0x21, 0 - .dw 0x60c0, 0xc92c, 0x60ff, 0xc92c, 0x21, 0 - .dw 0x6140, 0xc92c, 0x617f, 0xc92c, 0x21, 0 - .dw 0x61c0, 0xc92c, 0x61ff, 0xc92c, 0x21, 0 - .dw 0x6240, 0xc92c, 0x627f, 0xc92c, 0x21, 0 - .dw 0x62c0, 0xc92c, 0x62ff, 0xc92c, 0x21, 0 - .dw 0x6340, 0xc92c, 0x637f, 0xc92c, 0x21, 0 - .dw 0x63c0, 0xc92c, 0x63ff, 0xc92c, 0x21, 0 - .dw 0x6440, 0xc92c, 0x647f, 0xc92c, 0x21, 0 - .dw 0x64c0, 0xc92c, 0x64ff, 0xc92c, 0x21, 0 - .dw 0x6540, 0xc92c, 0x657f, 0xc92c, 0x21, 0 - .dw 0x65c0, 0xc92c, 0x65ff, 0xc92c, 0x21, 0 - .dw 0x6640, 0xc92c, 0x667f, 0xc92c, 0x21, 0 - .dw 0x66c0, 0xc92c, 0x66ff, 0xc92c, 0x21, 0 - .dw 0x6740, 0xc92c, 0x677f, 0xc92c, 0x21, 0 - .dw 0x67c0, 0xc92c, 0x67ff, 0xc92c, 0x21, 0 - .dw 0x6840, 0xc92c, 0x687f, 0xc92c, 0x21, 0 - .dw 0x68c0, 0xc92c, 0x68ff, 0xc92c, 0x21, 0 - .dw 0x6940, 0xc92c, 0x697f, 0xc92c, 0x21, 0 - .dw 0x69c0, 0xc92c, 0x69ff, 0xc92c, 0x21, 0 - .dw 0x6a40, 0xc92c, 0x6a7f, 0xc92c, 0x21, 0 - .dw 0x6ac0, 0xc92c, 0x6aff, 0xc92c, 0x21, 0 - .dw 0x6b40, 0xc92c, 0x6b7f, 0xc92c, 0x21, 0 - .dw 0x6bc0, 0xc92c, 0x6bff, 0xc92c, 0x21, 0 - .dw 0x6c40, 0xc92c, 0x6c7f, 0xc92c, 0x21, 0 - .dw 0x6cc0, 0xc92c, 0x6cff, 0xc92c, 0x21, 0 - .dw 0x6d40, 0xc92c, 0x6d7f, 0xc92c, 0x21, 0 - .dw 0x6dc0, 0xc92c, 0x6dff, 0xc92c, 0x21, 0 - .dw 0x6e40, 0xc92c, 0x6e7f, 0xc92c, 0x21, 0 - .dw 0x6ec0, 0xc92c, 0x6eff, 0xc92c, 0x21, 0 - .dw 0x6f40, 0xc92c, 0x6f7f, 0xc92c, 0x21, 0 - .dw 0x6fc0, 0xc92c, 0x6fff, 0xc92c, 0x21, 0 - .dw 0x7040, 0xc92c, 0x707f, 0xc92c, 0x21, 0 - .dw 0x70c0, 0xc92c, 0x70ff, 0xc92c, 0x21, 0 - .dw 0x7140, 0xc92c, 0x717f, 0xc92c, 0x21, 0 - .dw 0x71c0, 0xc92c, 0x71ff, 0xc92c, 0x21, 0 - .dw 0x7240, 0xc92c, 0x727f, 0xc92c, 0x21, 0 - .dw 0x72c0, 0xc92c, 0x72ff, 0xc92c, 0x21, 0 - .dw 0x7340, 0xc92c, 0x737f, 0xc92c, 0x21, 0 - .dw 0x73c0, 0xc92c, 0x73ff, 0xc92c, 0x21, 0 - .dw 0x7440, 0xc92c, 0x747f, 0xc92c, 0x21, 0 - .dw 0x74c0, 0xc92c, 0x74ff, 0xc92c, 0x21, 0 - .dw 0x7540, 0xc92c, 0x757f, 0xc92c, 0x21, 0 - .dw 0x75c0, 0xc92c, 0x75ff, 0xc92c, 0x21, 0 - .dw 0x7640, 0xc92c, 0x767f, 0xc92c, 0x21, 0 - .dw 0x76c0, 0xc92c, 0x76ff, 0xc92c, 0x21, 0 - .dw 0x7740, 0xc92c, 0x777f, 0xc92c, 0x21, 0 - .dw 0x77c0, 0xc92c, 0x77ff, 0xc92c, 0x21, 0 - .dw 0x7840, 0xc92c, 0x787f, 0xc92c, 0x21, 0 - .dw 0x78c0, 0xc92c, 0x78ff, 0xc92c, 0x21, 0 - .dw 0x7940, 0xc92c, 0x797f, 0xc92c, 0x21, 0 - .dw 0x79c0, 0xc92c, 0x7fff, 0xc92c, 0x21, 0 - .dw 0x8040, 0xc92c, 0x807f, 0xc92c, 0x21, 0 - .dw 0x80c0, 0xc92c, 0x80ff, 0xc92c, 0x21, 0 - .dw 0x8140, 0xc92c, 0x817f, 0xc92c, 0x21, 0 - .dw 0x81c0, 0xc92c, 0x81ff, 0xc92c, 0x21, 0 - .dw 0x8240, 0xc92c, 0x827f, 0xc92c, 0x21, 0 - .dw 0x82c0, 0xc92c, 0x82ff, 0xc92c, 0x21, 0 - .dw 0x8340, 0xc92c, 0x837f, 0xc92c, 0x21, 0 - .dw 0x83c0, 0xc92c, 0x83ff, 0xc92c, 0x21, 0 - .dw 0x8440, 0xc92c, 0x847f, 0xc92c, 0x21, 0 - .dw 0x84c0, 0xc92c, 0x84ff, 0xc92c, 0x21, 0 - .dw 0x8540, 0xc92c, 0x857f, 0xc92c, 0x21, 0 - .dw 0x85c0, 0xc92c, 0x85ff, 0xc92c, 0x21, 0 - .dw 0x8640, 0xc92c, 0x867f, 0xc92c, 0x21, 0 - .dw 0x86c0, 0xc92c, 0x86ff, 0xc92c, 0x21, 0 - .dw 0x8740, 0xc92c, 0x877f, 0xc92c, 0x21, 0 - .dw 0x87c0, 0xc92c, 0x87ff, 0xc92c, 0x21, 0 - .dw 0x8840, 0xc92c, 0x887f, 0xc92c, 0x21, 0 - .dw 0x88c0, 0xc92c, 0x88ff, 0xc92c, 0x21, 0 - .dw 0x8940, 0xc92c, 0x897f, 0xc92c, 0x21, 0 - .dw 0x89c0, 0xc92c, 0x89ff, 0xc92c, 0x21, 0 - .dw 0x8a40, 0xc92c, 0x8a7f, 0xc92c, 0x21, 0 - .dw 0x8ac0, 0xc92c, 0x8aff, 0xc92c, 0x21, 0 - .dw 0x8b40, 0xc92c, 0x8b7f, 0xc92c, 0x21, 0 - .dw 0x8bc0, 0xc92c, 0x8bff, 0xc92c, 0x21, 0 - .dw 0x8c40, 0xc92c, 0x8c7f, 0xc92c, 0x21, 0 - .dw 0x8cc0, 0xc92c, 0x8cff, 0xc92c, 0x21, 0 - .dw 0x8d40, 0xc92c, 0x8d7f, 0xc92c, 0x21, 0 - .dw 0x8dc0, 0xc92c, 0x8dff, 0xc92c, 0x21, 0 - .dw 0x8e40, 0xc92c, 0x8e7f, 0xc92c, 0x21, 0 - .dw 0x8ec0, 0xc92c, 0x8eff, 0xc92c, 0x21, 0 - .dw 0x8f40, 0xc92c, 0x8f7f, 0xc92c, 0x21, 0 - .dw 0x8fc0, 0xc92c, 0x8fff, 0xc92c, 0x21, 0 - .dw 0x9040, 0xc92c, 0x907f, 0xc92c, 0x21, 0 - .dw 0x90c0, 0xc92c, 0x90ff, 0xc92c, 0x21, 0 - .dw 0x9140, 0xc92c, 0x917f, 0xc92c, 0x21, 0 - .dw 0x91c0, 0xc92c, 0x91ff, 0xc92c, 0x21, 0 - .dw 0x9240, 0xc92c, 0x927f, 0xc92c, 0x21, 0 - .dw 0x92c0, 0xc92c, 0x92ff, 0xc92c, 0x21, 0 - .dw 0x9340, 0xc92c, 0x937f, 0xc92c, 0x21, 0 - .dw 0x93c0, 0xc92c, 0x93ff, 0xc92c, 0x21, 0 - .dw 0x9440, 0xc92c, 0x947f, 0xc92c, 0x21, 0 - .dw 0x94c0, 0xc92c, 0x94ff, 0xc92c, 0x21, 0 - .dw 0x9540, 0xc92c, 0x957f, 0xc92c, 0x21, 0 - .dw 0x95c0, 0xc92c, 0x95ff, 0xc92c, 0x21, 0 - .dw 0x9640, 0xc92c, 0x967f, 0xc92c, 0x21, 0 - .dw 0x96c0, 0xc92c, 0x96ff, 0xc92c, 0x21, 0 - .dw 0x9740, 0xc92c, 0x977f, 0xc92c, 0x21, 0 - .dw 0x97c0, 0xc92c, 0x97ff, 0xc92c, 0x21, 0 - .dw 0x9840, 0xc92c, 0x987f, 0xc92c, 0x21, 0 - .dw 0x98c0, 0xc92c, 0x98ff, 0xc92c, 0x21, 0 - .dw 0x9940, 0xc92c, 0x997f, 0xc92c, 0x21, 0 - .dw 0x99c0, 0xc92c, 0x9fff, 0xc92c, 0x21, 0 - .dw 0xa040, 0xc92c, 0xa07f, 0xc92c, 0x21, 0 - .dw 0xa0c0, 0xc92c, 0xa0ff, 0xc92c, 0x21, 0 - .dw 0xa140, 0xc92c, 0xa17f, 0xc92c, 0x21, 0 - .dw 0xa1c0, 0xc92c, 0xa1ff, 0xc92c, 0x21, 0 - .dw 0xa240, 0xc92c, 0xa27f, 0xc92c, 0x21, 0 - .dw 0xa2c0, 0xc92c, 0xa2ff, 0xc92c, 0x21, 0 - .dw 0xa340, 0xc92c, 0xa37f, 0xc92c, 0x21, 0 - .dw 0xa3c0, 0xc92c, 0xa3ff, 0xc92c, 0x21, 0 - .dw 0xa440, 0xc92c, 0xa47f, 0xc92c, 0x21, 0 - .dw 0xa4c0, 0xc92c, 0xa4ff, 0xc92c, 0x21, 0 - .dw 0xa540, 0xc92c, 0xa57f, 0xc92c, 0x21, 0 - .dw 0xa5c0, 0xc92c, 0xa5ff, 0xc92c, 0x21, 0 - .dw 0xa640, 0xc92c, 0xa67f, 0xc92c, 0x21, 0 - .dw 0xa6c0, 0xc92c, 0xa6ff, 0xc92c, 0x21, 0 - .dw 0xa740, 0xc92c, 0xa77f, 0xc92c, 0x21, 0 - .dw 0xa7c0, 0xc92c, 0xa7ff, 0xc92c, 0x21, 0 - .dw 0xa840, 0xc92c, 0xa87f, 0xc92c, 0x21, 0 - .dw 0xa8c0, 0xc92c, 0xa8ff, 0xc92c, 0x21, 0 - .dw 0xa940, 0xc92c, 0xa97f, 0xc92c, 0x21, 0 - .dw 0xa9c0, 0xc92c, 0xa9ff, 0xc92c, 0x21, 0 - .dw 0xaa40, 0xc92c, 0xaa7f, 0xc92c, 0x21, 0 - .dw 0xaac0, 0xc92c, 0xaaff, 0xc92c, 0x21, 0 - .dw 0xab40, 0xc92c, 0xab7f, 0xc92c, 0x21, 0 - .dw 0xabc0, 0xc92c, 0xabff, 0xc92c, 0x21, 0 - .dw 0xac40, 0xc92c, 0xac7f, 0xc92c, 0x21, 0 - .dw 0xacc0, 0xc92c, 0xacff, 0xc92c, 0x21, 0 - .dw 0xad40, 0xc92c, 0xad7f, 0xc92c, 0x21, 0 - .dw 0xadc0, 0xc92c, 0xadff, 0xc92c, 0x21, 0 - .dw 0xae40, 0xc92c, 0xae7f, 0xc92c, 0x21, 0 - .dw 0xaec0, 0xc92c, 0xaeff, 0xc92c, 0x21, 0 - .dw 0xaf40, 0xc92c, 0xaf7f, 0xc92c, 0x21, 0 - .dw 0xafc0, 0xc92c, 0xafff, 0xc92c, 0x21, 0 - .dw 0xb040, 0xc92c, 0xb07f, 0xc92c, 0x21, 0 - .dw 0xb0c0, 0xc92c, 0xb0ff, 0xc92c, 0x21, 0 - .dw 0xb140, 0xc92c, 0xb17f, 0xc92c, 0x21, 0 - .dw 0xb1c0, 0xc92c, 0xb1ff, 0xc92c, 0x21, 0 - .dw 0xb240, 0xc92c, 0xb27f, 0xc92c, 0x21, 0 - .dw 0xb2c0, 0xc92c, 0xb2ff, 0xc92c, 0x21, 0 - .dw 0xb340, 0xc92c, 0xb37f, 0xc92c, 0x21, 0 - .dw 0xb3c0, 0xc92c, 0xb3ff, 0xc92c, 0x21, 0 - .dw 0xb440, 0xc92c, 0xb47f, 0xc92c, 0x21, 0 - .dw 0xb4c0, 0xc92c, 0xb4ff, 0xc92c, 0x21, 0 - .dw 0xb540, 0xc92c, 0xb57f, 0xc92c, 0x21, 0 - .dw 0xb5c0, 0xc92c, 0xb5ff, 0xc92c, 0x21, 0 - .dw 0xb640, 0xc92c, 0xb67f, 0xc92c, 0x21, 0 - .dw 0xb6c0, 0xc92c, 0xb6ff, 0xc92c, 0x21, 0 - .dw 0xb740, 0xc92c, 0xb77f, 0xc92c, 0x21, 0 - .dw 0xb7c0, 0xc92c, 0xb7ff, 0xc92c, 0x21, 0 - .dw 0xb840, 0xc92c, 0xb87f, 0xc92c, 0x21, 0 - .dw 0xb8c0, 0xc92c, 0xb8ff, 0xc92c, 0x21, 0 - .dw 0xb940, 0xc92c, 0xb97f, 0xc92c, 0x21, 0 - .dw 0xb9c0, 0xc92c, 0xbfff, 0xc92c, 0x21, 0 - .dw 0xc040, 0xc92c, 0xc07f, 0xc92c, 0x21, 0 - .dw 0xc0c0, 0xc92c, 0xc0ff, 0xc92c, 0x21, 0 - .dw 0xc140, 0xc92c, 0xc17f, 0xc92c, 0x21, 0 - .dw 0xc1c0, 0xc92c, 0xc1ff, 0xc92c, 0x21, 0 - .dw 0xc240, 0xc92c, 0xc27f, 0xc92c, 0x21, 0 - .dw 0xc2c0, 0xc92c, 0xc2ff, 0xc92c, 0x21, 0 - .dw 0xc340, 0xc92c, 0xc37f, 0xc92c, 0x21, 0 - .dw 0xc3c0, 0xc92c, 0xc3ff, 0xc92c, 0x21, 0 - .dw 0xc440, 0xc92c, 0xc47f, 0xc92c, 0x21, 0 - .dw 0xc4c0, 0xc92c, 0xc4ff, 0xc92c, 0x21, 0 - .dw 0xc540, 0xc92c, 0xc57f, 0xc92c, 0x21, 0 - .dw 0xc5c0, 0xc92c, 0xc5ff, 0xc92c, 0x21, 0 - .dw 0xc640, 0xc92c, 0xc67f, 0xc92c, 0x21, 0 - .dw 0xc6c0, 0xc92c, 0xc6ff, 0xc92c, 0x21, 0 - .dw 0xc740, 0xc92c, 0xc77f, 0xc92c, 0x21, 0 - .dw 0xc7c0, 0xc92c, 0xc7ff, 0xc92c, 0x21, 0 - .dw 0xc840, 0xc92c, 0xc87f, 0xc92c, 0x21, 0 - .dw 0xc8c0, 0xc92c, 0xc8ff, 0xc92c, 0x21, 0 - .dw 0xc940, 0xc92c, 0xc97f, 0xc92c, 0x21, 0 - .dw 0xc9c0, 0xc92c, 0xc9ff, 0xc92c, 0x21, 0 - .dw 0xca40, 0xc92c, 0xca7f, 0xc92c, 0x21, 0 - .dw 0xcac0, 0xc92c, 0xcaff, 0xc92c, 0x21, 0 - .dw 0xcb40, 0xc92c, 0xcb7f, 0xc92c, 0x21, 0 - .dw 0xcbc0, 0xc92c, 0xcbff, 0xc92c, 0x21, 0 - .dw 0xcc40, 0xc92c, 0xcc7f, 0xc92c, 0x21, 0 - .dw 0xccc0, 0xc92c, 0xccff, 0xc92c, 0x21, 0 - .dw 0xcd40, 0xc92c, 0xcd7f, 0xc92c, 0x21, 0 - .dw 0xcdc0, 0xc92c, 0xcdff, 0xc92c, 0x21, 0 - .dw 0xce40, 0xc92c, 0xce7f, 0xc92c, 0x21, 0 - .dw 0xcec0, 0xc92c, 0xceff, 0xc92c, 0x21, 0 - .dw 0xcf40, 0xc92c, 0xcf7f, 0xc92c, 0x21, 0 - .dw 0xcfc0, 0xc92c, 0xcfff, 0xc92c, 0x21, 0 - .dw 0xd040, 0xc92c, 0xd07f, 0xc92c, 0x21, 0 - .dw 0xd0c0, 0xc92c, 0xd0ff, 0xc92c, 0x21, 0 - .dw 0xd140, 0xc92c, 0xd17f, 0xc92c, 0x21, 0 - .dw 0xd1c0, 0xc92c, 0xd1ff, 0xc92c, 0x21, 0 - .dw 0xd240, 0xc92c, 0xd27f, 0xc92c, 0x21, 0 - .dw 0xd2c0, 0xc92c, 0xd2ff, 0xc92c, 0x21, 0 - .dw 0xd340, 0xc92c, 0xd37f, 0xc92c, 0x21, 0 - .dw 0xd3c0, 0xc92c, 0xd3ff, 0xc92c, 0x21, 0 - .dw 0xd440, 0xc92c, 0xd47f, 0xc92c, 0x21, 0 - .dw 0xd4c0, 0xc92c, 0xd4ff, 0xc92c, 0x21, 0 - .dw 0xd540, 0xc92c, 0xd57f, 0xc92c, 0x21, 0 - .dw 0xd5c0, 0xc92c, 0xd5ff, 0xc92c, 0x21, 0 - .dw 0xd640, 0xc92c, 0xd67f, 0xc92c, 0x21, 0 - .dw 0xd6c0, 0xc92c, 0xd6ff, 0xc92c, 0x21, 0 - .dw 0xd740, 0xc92c, 0xd77f, 0xc92c, 0x21, 0 - .dw 0xd7c0, 0xc92c, 0xd7ff, 0xc92c, 0x21, 0 - .dw 0xd840, 0xc92c, 0xd87f, 0xc92c, 0x21, 0 - .dw 0xd8c0, 0xc92c, 0xd8ff, 0xc92c, 0x21, 0 - .dw 0xd940, 0xc92c, 0xd97f, 0xc92c, 0x21, 0 - .dw 0xd9c0, 0xc92c, 0xdfff, 0xc92c, 0x21, 0 - .dw 0xe040, 0xc92c, 0xe07f, 0xc92c, 0x21, 0 - .dw 0xe0c0, 0xc92c, 0xe0ff, 0xc92c, 0x21, 0 - .dw 0xe140, 0xc92c, 0xe17f, 0xc92c, 0x21, 0 - .dw 0xe1c0, 0xc92c, 0xe1ff, 0xc92c, 0x21, 0 - .dw 0xe240, 0xc92c, 0xe27f, 0xc92c, 0x21, 0 - .dw 0xe2c0, 0xc92c, 0xe2ff, 0xc92c, 0x21, 0 - .dw 0xe340, 0xc92c, 0xe37f, 0xc92c, 0x21, 0 - .dw 0xe3c0, 0xc92c, 0xe3ff, 0xc92c, 0x21, 0 - .dw 0xe440, 0xc92c, 0xe47f, 0xc92c, 0x21, 0 - .dw 0xe4c0, 0xc92c, 0xe4ff, 0xc92c, 0x21, 0 - .dw 0xe540, 0xc92c, 0xe57f, 0xc92c, 0x21, 0 - .dw 0xe5c0, 0xc92c, 0xe5ff, 0xc92c, 0x21, 0 - .dw 0xe640, 0xc92c, 0xe67f, 0xc92c, 0x21, 0 - .dw 0xe6c0, 0xc92c, 0xe6ff, 0xc92c, 0x21, 0 - .dw 0xe740, 0xc92c, 0xe77f, 0xc92c, 0x21, 0 - .dw 0xe7c0, 0xc92c, 0xe7ff, 0xc92c, 0x21, 0 - .dw 0xe840, 0xc92c, 0xe87f, 0xc92c, 0x21, 0 - .dw 0xe8c0, 0xc92c, 0xe8ff, 0xc92c, 0x21, 0 - .dw 0xe940, 0xc92c, 0xe97f, 0xc92c, 0x21, 0 - .dw 0xe9c0, 0xc92c, 0xe9ff, 0xc92c, 0x21, 0 - .dw 0xea40, 0xc92c, 0xea7f, 0xc92c, 0x21, 0 - .dw 0xeac0, 0xc92c, 0xeaff, 0xc92c, 0x21, 0 - .dw 0xeb40, 0xc92c, 0xeb7f, 0xc92c, 0x21, 0 - .dw 0xebc0, 0xc92c, 0xebff, 0xc92c, 0x21, 0 - .dw 0xec40, 0xc92c, 0xec7f, 0xc92c, 0x21, 0 - .dw 0xecc0, 0xc92c, 0xecff, 0xc92c, 0x21, 0 - .dw 0xed40, 0xc92c, 0xed7f, 0xc92c, 0x21, 0 - .dw 0xedc0, 0xc92c, 0xedff, 0xc92c, 0x21, 0 - .dw 0xee40, 0xc92c, 0xee7f, 0xc92c, 0x21, 0 - .dw 0xeec0, 0xc92c, 0xeeff, 0xc92c, 0x21, 0 - .dw 0xef40, 0xc92c, 0xef7f, 0xc92c, 0x21, 0 - .dw 0xefc0, 0xc92c, 0xefff, 0xc92c, 0x21, 0 - .dw 0xf040, 0xc92c, 0xf07f, 0xc92c, 0x21, 0 - .dw 0xf0c0, 0xc92c, 0xf0ff, 0xc92c, 0x21, 0 - .dw 0xf140, 0xc92c, 0xf17f, 0xc92c, 0x21, 0 - .dw 0xf1c0, 0xc92c, 0xf1ff, 0xc92c, 0x21, 0 - .dw 0xf240, 0xc92c, 0xf27f, 0xc92c, 0x21, 0 - .dw 0xf2c0, 0xc92c, 0xf2ff, 0xc92c, 0x21, 0 - .dw 0xf340, 0xc92c, 0xf37f, 0xc92c, 0x21, 0 - .dw 0xf3c0, 0xc92c, 0xf3ff, 0xc92c, 0x21, 0 - .dw 0xf440, 0xc92c, 0xf47f, 0xc92c, 0x21, 0 - .dw 0xf4c0, 0xc92c, 0xf4ff, 0xc92c, 0x21, 0 - .dw 0xf540, 0xc92c, 0xf57f, 0xc92c, 0x21, 0 - .dw 0xf5c0, 0xc92c, 0xf5ff, 0xc92c, 0x21, 0 - .dw 0xf640, 0xc92c, 0xf67f, 0xc92c, 0x21, 0 - .dw 0xf6c0, 0xc92c, 0xf6ff, 0xc92c, 0x21, 0 - .dw 0xf740, 0xc92c, 0xf77f, 0xc92c, 0x21, 0 - .dw 0xf7c0, 0xc92c, 0xf7ff, 0xc92c, 0x21, 0 - .dw 0xf840, 0xc92c, 0xf87f, 0xc92c, 0x21, 0 - .dw 0xf8c0, 0xc92c, 0xf8ff, 0xc92c, 0x21, 0 - .dw 0xf940, 0xc92c, 0xf97f, 0xc92c, 0x21, 0 - .dw 0xf9c0, 0xc92c, 0xffff, 0xc92c, 0x21, 0 - .dw 0x0040, 0xc92d, 0x007f, 0xc92d, 0x21, 0 - .dw 0x00c0, 0xc92d, 0x00ff, 0xc92d, 0x21, 0 - .dw 0x0140, 0xc92d, 0x017f, 0xc92d, 0x21, 0 - .dw 0x01c0, 0xc92d, 0x01ff, 0xc92d, 0x21, 0 - .dw 0x0240, 0xc92d, 0x027f, 0xc92d, 0x21, 0 - .dw 0x02c0, 0xc92d, 0x02ff, 0xc92d, 0x21, 0 - .dw 0x0340, 0xc92d, 0x037f, 0xc92d, 0x21, 0 - .dw 0x03c0, 0xc92d, 0x03ff, 0xc92d, 0x21, 0 - .dw 0x0440, 0xc92d, 0x047f, 0xc92d, 0x21, 0 - .dw 0x04c0, 0xc92d, 0x04ff, 0xc92d, 0x21, 0 - .dw 0x0540, 0xc92d, 0x057f, 0xc92d, 0x21, 0 - .dw 0x05c0, 0xc92d, 0x05ff, 0xc92d, 0x21, 0 - .dw 0x0640, 0xc92d, 0x067f, 0xc92d, 0x21, 0 - .dw 0x06c0, 0xc92d, 0x06ff, 0xc92d, 0x21, 0 - .dw 0x0740, 0xc92d, 0x077f, 0xc92d, 0x21, 0 - .dw 0x07c0, 0xc92d, 0x07ff, 0xc92d, 0x21, 0 - .dw 0x0840, 0xc92d, 0x087f, 0xc92d, 0x21, 0 - .dw 0x08c0, 0xc92d, 0x08ff, 0xc92d, 0x21, 0 - .dw 0x0940, 0xc92d, 0x097f, 0xc92d, 0x21, 0 - .dw 0x09c0, 0xc92d, 0x09ff, 0xc92d, 0x21, 0 - .dw 0x0a40, 0xc92d, 0x0a7f, 0xc92d, 0x21, 0 - .dw 0x0ac0, 0xc92d, 0x0aff, 0xc92d, 0x21, 0 - .dw 0x0b40, 0xc92d, 0x0b7f, 0xc92d, 0x21, 0 - .dw 0x0bc0, 0xc92d, 0x0bff, 0xc92d, 0x21, 0 - .dw 0x0c40, 0xc92d, 0x0c7f, 0xc92d, 0x21, 0 - .dw 0x0cc0, 0xc92d, 0x0cff, 0xc92d, 0x21, 0 - .dw 0x0d40, 0xc92d, 0x0d7f, 0xc92d, 0x21, 0 - .dw 0x0dc0, 0xc92d, 0x0dff, 0xc92d, 0x21, 0 - .dw 0x0e40, 0xc92d, 0x0e7f, 0xc92d, 0x21, 0 - .dw 0x0ec0, 0xc92d, 0x0eff, 0xc92d, 0x21, 0 - .dw 0x0f40, 0xc92d, 0x0f7f, 0xc92d, 0x21, 0 - .dw 0x0fc0, 0xc92d, 0x0fff, 0xc92d, 0x21, 0 - .dw 0x1040, 0xc92d, 0x107f, 0xc92d, 0x21, 0 - .dw 0x10c0, 0xc92d, 0x10ff, 0xc92d, 0x21, 0 - .dw 0x1140, 0xc92d, 0x117f, 0xc92d, 0x21, 0 - .dw 0x11c0, 0xc92d, 0x11ff, 0xc92d, 0x21, 0 - .dw 0x1240, 0xc92d, 0x127f, 0xc92d, 0x21, 0 - .dw 0x12c0, 0xc92d, 0x12ff, 0xc92d, 0x21, 0 - .dw 0x1340, 0xc92d, 0x137f, 0xc92d, 0x21, 0 - .dw 0x13c0, 0xc92d, 0x13ff, 0xc92d, 0x21, 0 - .dw 0x1440, 0xc92d, 0x147f, 0xc92d, 0x21, 0 - .dw 0x14c0, 0xc92d, 0x14ff, 0xc92d, 0x21, 0 - .dw 0x1540, 0xc92d, 0x157f, 0xc92d, 0x21, 0 - .dw 0x15c0, 0xc92d, 0x15ff, 0xc92d, 0x21, 0 - .dw 0x1640, 0xc92d, 0x167f, 0xc92d, 0x21, 0 - .dw 0x16c0, 0xc92d, 0x16ff, 0xc92d, 0x21, 0 - .dw 0x1740, 0xc92d, 0x177f, 0xc92d, 0x21, 0 - .dw 0x17c0, 0xc92d, 0x17ff, 0xc92d, 0x21, 0 - .dw 0x1840, 0xc92d, 0x187f, 0xc92d, 0x21, 0 - .dw 0x18c0, 0xc92d, 0x18ff, 0xc92d, 0x21, 0 - .dw 0x1940, 0xc92d, 0x197f, 0xc92d, 0x21, 0 - .dw 0x19c0, 0xc92d, 0x1fff, 0xc92d, 0x21, 0 - .dw 0x2040, 0xc92d, 0x207f, 0xc92d, 0x21, 0 - .dw 0x20c0, 0xc92d, 0x20ff, 0xc92d, 0x21, 0 - .dw 0x2140, 0xc92d, 0x217f, 0xc92d, 0x21, 0 - .dw 0x21c0, 0xc92d, 0x21ff, 0xc92d, 0x21, 0 - .dw 0x2240, 0xc92d, 0x227f, 0xc92d, 0x21, 0 - .dw 0x22c0, 0xc92d, 0x22ff, 0xc92d, 0x21, 0 - .dw 0x2340, 0xc92d, 0x237f, 0xc92d, 0x21, 0 - .dw 0x23c0, 0xc92d, 0x23ff, 0xc92d, 0x21, 0 - .dw 0x2440, 0xc92d, 0x247f, 0xc92d, 0x21, 0 - .dw 0x24c0, 0xc92d, 0x24ff, 0xc92d, 0x21, 0 - .dw 0x2540, 0xc92d, 0x257f, 0xc92d, 0x21, 0 - .dw 0x25c0, 0xc92d, 0x25ff, 0xc92d, 0x21, 0 - .dw 0x2640, 0xc92d, 0x267f, 0xc92d, 0x21, 0 - .dw 0x26c0, 0xc92d, 0x26ff, 0xc92d, 0x21, 0 - .dw 0x2740, 0xc92d, 0x277f, 0xc92d, 0x21, 0 - .dw 0x27c0, 0xc92d, 0x27ff, 0xc92d, 0x21, 0 - .dw 0x2840, 0xc92d, 0x287f, 0xc92d, 0x21, 0 - .dw 0x28c0, 0xc92d, 0x28ff, 0xc92d, 0x21, 0 - .dw 0x2940, 0xc92d, 0x297f, 0xc92d, 0x21, 0 - .dw 0x29c0, 0xc92d, 0x29ff, 0xc92d, 0x21, 0 - .dw 0x2a40, 0xc92d, 0x2a7f, 0xc92d, 0x21, 0 - .dw 0x2ac0, 0xc92d, 0x2aff, 0xc92d, 0x21, 0 - .dw 0x2b40, 0xc92d, 0x2b7f, 0xc92d, 0x21, 0 - .dw 0x2bc0, 0xc92d, 0x2bff, 0xc92d, 0x21, 0 - .dw 0x2c40, 0xc92d, 0x2c7f, 0xc92d, 0x21, 0 - .dw 0x2cc0, 0xc92d, 0x2cff, 0xc92d, 0x21, 0 - .dw 0x2d40, 0xc92d, 0x2d7f, 0xc92d, 0x21, 0 - .dw 0x2dc0, 0xc92d, 0x2dff, 0xc92d, 0x21, 0 - .dw 0x2e40, 0xc92d, 0x2e7f, 0xc92d, 0x21, 0 - .dw 0x2ec0, 0xc92d, 0x2eff, 0xc92d, 0x21, 0 - .dw 0x2f40, 0xc92d, 0x2f7f, 0xc92d, 0x21, 0 - .dw 0x2fc0, 0xc92d, 0x2fff, 0xc92d, 0x21, 0 - .dw 0x3040, 0xc92d, 0x307f, 0xc92d, 0x21, 0 - .dw 0x30c0, 0xc92d, 0x30ff, 0xc92d, 0x21, 0 - .dw 0x3140, 0xc92d, 0x317f, 0xc92d, 0x21, 0 - .dw 0x31c0, 0xc92d, 0x31ff, 0xc92d, 0x21, 0 - .dw 0x3240, 0xc92d, 0x327f, 0xc92d, 0x21, 0 - .dw 0x32c0, 0xc92d, 0x32ff, 0xc92d, 0x21, 0 - .dw 0x3340, 0xc92d, 0x337f, 0xc92d, 0x21, 0 - .dw 0x33c0, 0xc92d, 0x33ff, 0xc92d, 0x21, 0 - .dw 0x3440, 0xc92d, 0x347f, 0xc92d, 0x21, 0 - .dw 0x34c0, 0xc92d, 0x34ff, 0xc92d, 0x21, 0 - .dw 0x3540, 0xc92d, 0x357f, 0xc92d, 0x21, 0 - .dw 0x35c0, 0xc92d, 0x35ff, 0xc92d, 0x21, 0 - .dw 0x3640, 0xc92d, 0x367f, 0xc92d, 0x21, 0 - .dw 0x36c0, 0xc92d, 0x36ff, 0xc92d, 0x21, 0 - .dw 0x3740, 0xc92d, 0x377f, 0xc92d, 0x21, 0 - .dw 0x37c0, 0xc92d, 0x37ff, 0xc92d, 0x21, 0 - .dw 0x3840, 0xc92d, 0x387f, 0xc92d, 0x21, 0 - .dw 0x38c0, 0xc92d, 0x38ff, 0xc92d, 0x21, 0 - .dw 0x3940, 0xc92d, 0x397f, 0xc92d, 0x21, 0 - .dw 0x39c0, 0xc92d, 0x3fff, 0xc92d, 0x21, 0 - .dw 0x4040, 0xc92d, 0x407f, 0xc92d, 0x21, 0 - .dw 0x40c0, 0xc92d, 0x40ff, 0xc92d, 0x21, 0 - .dw 0x4140, 0xc92d, 0x417f, 0xc92d, 0x21, 0 - .dw 0x41c0, 0xc92d, 0x41ff, 0xc92d, 0x21, 0 - .dw 0x4240, 0xc92d, 0x427f, 0xc92d, 0x21, 0 - .dw 0x42c0, 0xc92d, 0x42ff, 0xc92d, 0x21, 0 - .dw 0x4340, 0xc92d, 0x437f, 0xc92d, 0x21, 0 - .dw 0x43c0, 0xc92d, 0x43ff, 0xc92d, 0x21, 0 - .dw 0x4440, 0xc92d, 0x447f, 0xc92d, 0x21, 0 - .dw 0x44c0, 0xc92d, 0x44ff, 0xc92d, 0x21, 0 - .dw 0x4540, 0xc92d, 0x457f, 0xc92d, 0x21, 0 - .dw 0x45c0, 0xc92d, 0x45ff, 0xc92d, 0x21, 0 - .dw 0x4640, 0xc92d, 0x467f, 0xc92d, 0x21, 0 - .dw 0x46c0, 0xc92d, 0x46ff, 0xc92d, 0x21, 0 - .dw 0x4740, 0xc92d, 0x477f, 0xc92d, 0x21, 0 - .dw 0x47c0, 0xc92d, 0x47ff, 0xc92d, 0x21, 0 - .dw 0x4840, 0xc92d, 0x487f, 0xc92d, 0x21, 0 - .dw 0x48c0, 0xc92d, 0x48ff, 0xc92d, 0x21, 0 - .dw 0x4940, 0xc92d, 0x497f, 0xc92d, 0x21, 0 - .dw 0x49c0, 0xc92d, 0x49ff, 0xc92d, 0x21, 0 - .dw 0x4a40, 0xc92d, 0x4a7f, 0xc92d, 0x21, 0 - .dw 0x4ac0, 0xc92d, 0x4aff, 0xc92d, 0x21, 0 - .dw 0x4b40, 0xc92d, 0x4b7f, 0xc92d, 0x21, 0 - .dw 0x4bc0, 0xc92d, 0x4bff, 0xc92d, 0x21, 0 - .dw 0x4c40, 0xc92d, 0x4c7f, 0xc92d, 0x21, 0 - .dw 0x4cc0, 0xc92d, 0x4cff, 0xc92d, 0x21, 0 - .dw 0x4d40, 0xc92d, 0x4d7f, 0xc92d, 0x21, 0 - .dw 0x4dc0, 0xc92d, 0x4dff, 0xc92d, 0x21, 0 - .dw 0x4e40, 0xc92d, 0x4e7f, 0xc92d, 0x21, 0 - .dw 0x4ec0, 0xc92d, 0x4eff, 0xc92d, 0x21, 0 - .dw 0x4f40, 0xc92d, 0x4f7f, 0xc92d, 0x21, 0 - .dw 0x4fc0, 0xc92d, 0x4fff, 0xc92d, 0x21, 0 - .dw 0x5040, 0xc92d, 0x507f, 0xc92d, 0x21, 0 - .dw 0x50c0, 0xc92d, 0x50ff, 0xc92d, 0x21, 0 - .dw 0x5140, 0xc92d, 0x517f, 0xc92d, 0x21, 0 - .dw 0x51c0, 0xc92d, 0x51ff, 0xc92d, 0x21, 0 - .dw 0x5240, 0xc92d, 0x527f, 0xc92d, 0x21, 0 - .dw 0x52c0, 0xc92d, 0x52ff, 0xc92d, 0x21, 0 - .dw 0x5340, 0xc92d, 0x537f, 0xc92d, 0x21, 0 - .dw 0x53c0, 0xc92d, 0x53ff, 0xc92d, 0x21, 0 - .dw 0x5440, 0xc92d, 0x547f, 0xc92d, 0x21, 0 - .dw 0x54c0, 0xc92d, 0x54ff, 0xc92d, 0x21, 0 - .dw 0x5540, 0xc92d, 0x557f, 0xc92d, 0x21, 0 - .dw 0x55c0, 0xc92d, 0x55ff, 0xc92d, 0x21, 0 - .dw 0x5640, 0xc92d, 0x567f, 0xc92d, 0x21, 0 - .dw 0x56c0, 0xc92d, 0x56ff, 0xc92d, 0x21, 0 - .dw 0x5740, 0xc92d, 0x577f, 0xc92d, 0x21, 0 - .dw 0x57c0, 0xc92d, 0x57ff, 0xc92d, 0x21, 0 - .dw 0x5840, 0xc92d, 0x587f, 0xc92d, 0x21, 0 - .dw 0x58c0, 0xc92d, 0x58ff, 0xc92d, 0x21, 0 - .dw 0x5940, 0xc92d, 0x597f, 0xc92d, 0x21, 0 - .dw 0x59c0, 0xc92d, 0x5fff, 0xc92d, 0x21, 0 - .dw 0x6040, 0xc92d, 0x607f, 0xc92d, 0x21, 0 - .dw 0x60c0, 0xc92d, 0x60ff, 0xc92d, 0x21, 0 - .dw 0x6140, 0xc92d, 0x617f, 0xc92d, 0x21, 0 - .dw 0x61c0, 0xc92d, 0x61ff, 0xc92d, 0x21, 0 - .dw 0x6240, 0xc92d, 0x627f, 0xc92d, 0x21, 0 - .dw 0x62c0, 0xc92d, 0x62ff, 0xc92d, 0x21, 0 - .dw 0x6340, 0xc92d, 0x637f, 0xc92d, 0x21, 0 - .dw 0x63c0, 0xc92d, 0x63ff, 0xc92d, 0x21, 0 - .dw 0x6440, 0xc92d, 0x647f, 0xc92d, 0x21, 0 - .dw 0x64c0, 0xc92d, 0x64ff, 0xc92d, 0x21, 0 - .dw 0x6540, 0xc92d, 0x657f, 0xc92d, 0x21, 0 - .dw 0x65c0, 0xc92d, 0x65ff, 0xc92d, 0x21, 0 - .dw 0x6640, 0xc92d, 0x667f, 0xc92d, 0x21, 0 - .dw 0x66c0, 0xc92d, 0x66ff, 0xc92d, 0x21, 0 - .dw 0x6740, 0xc92d, 0x677f, 0xc92d, 0x21, 0 - .dw 0x67c0, 0xc92d, 0x67ff, 0xc92d, 0x21, 0 - .dw 0x6840, 0xc92d, 0x687f, 0xc92d, 0x21, 0 - .dw 0x68c0, 0xc92d, 0x68ff, 0xc92d, 0x21, 0 - .dw 0x6940, 0xc92d, 0x697f, 0xc92d, 0x21, 0 - .dw 0x69c0, 0xc92d, 0x69ff, 0xc92d, 0x21, 0 - .dw 0x6a40, 0xc92d, 0x6a7f, 0xc92d, 0x21, 0 - .dw 0x6ac0, 0xc92d, 0x6aff, 0xc92d, 0x21, 0 - .dw 0x6b40, 0xc92d, 0x6b7f, 0xc92d, 0x21, 0 - .dw 0x6bc0, 0xc92d, 0x6bff, 0xc92d, 0x21, 0 - .dw 0x6c40, 0xc92d, 0x6c7f, 0xc92d, 0x21, 0 - .dw 0x6cc0, 0xc92d, 0x6cff, 0xc92d, 0x21, 0 - .dw 0x6d40, 0xc92d, 0x6d7f, 0xc92d, 0x21, 0 - .dw 0x6dc0, 0xc92d, 0x6dff, 0xc92d, 0x21, 0 - .dw 0x6e40, 0xc92d, 0x6e7f, 0xc92d, 0x21, 0 - .dw 0x6ec0, 0xc92d, 0x6eff, 0xc92d, 0x21, 0 - .dw 0x6f40, 0xc92d, 0x6f7f, 0xc92d, 0x21, 0 - .dw 0x6fc0, 0xc92d, 0x6fff, 0xc92d, 0x21, 0 - .dw 0x7040, 0xc92d, 0x707f, 0xc92d, 0x21, 0 - .dw 0x70c0, 0xc92d, 0x70ff, 0xc92d, 0x21, 0 - .dw 0x7140, 0xc92d, 0x717f, 0xc92d, 0x21, 0 - .dw 0x71c0, 0xc92d, 0x71ff, 0xc92d, 0x21, 0 - .dw 0x7240, 0xc92d, 0x727f, 0xc92d, 0x21, 0 - .dw 0x72c0, 0xc92d, 0x72ff, 0xc92d, 0x21, 0 - .dw 0x7340, 0xc92d, 0x737f, 0xc92d, 0x21, 0 - .dw 0x73c0, 0xc92d, 0x73ff, 0xc92d, 0x21, 0 - .dw 0x7440, 0xc92d, 0x747f, 0xc92d, 0x21, 0 - .dw 0x74c0, 0xc92d, 0x74ff, 0xc92d, 0x21, 0 - .dw 0x7540, 0xc92d, 0x757f, 0xc92d, 0x21, 0 - .dw 0x75c0, 0xc92d, 0x75ff, 0xc92d, 0x21, 0 - .dw 0x7640, 0xc92d, 0x767f, 0xc92d, 0x21, 0 - .dw 0x76c0, 0xc92d, 0x76ff, 0xc92d, 0x21, 0 - .dw 0x7740, 0xc92d, 0x777f, 0xc92d, 0x21, 0 - .dw 0x77c0, 0xc92d, 0x77ff, 0xc92d, 0x21, 0 - .dw 0x7840, 0xc92d, 0x787f, 0xc92d, 0x21, 0 - .dw 0x78c0, 0xc92d, 0x78ff, 0xc92d, 0x21, 0 - .dw 0x7940, 0xc92d, 0x797f, 0xc92d, 0x21, 0 - .dw 0x79c0, 0xc92d, 0x7fff, 0xc92d, 0x21, 0 - .dw 0x8040, 0xc92d, 0x807f, 0xc92d, 0x21, 0 - .dw 0x80c0, 0xc92d, 0x80ff, 0xc92d, 0x21, 0 - .dw 0x8140, 0xc92d, 0x817f, 0xc92d, 0x21, 0 - .dw 0x81c0, 0xc92d, 0x81ff, 0xc92d, 0x21, 0 - .dw 0x8240, 0xc92d, 0x827f, 0xc92d, 0x21, 0 - .dw 0x82c0, 0xc92d, 0x82ff, 0xc92d, 0x21, 0 - .dw 0x8340, 0xc92d, 0x837f, 0xc92d, 0x21, 0 - .dw 0x83c0, 0xc92d, 0x83ff, 0xc92d, 0x21, 0 - .dw 0x8440, 0xc92d, 0x847f, 0xc92d, 0x21, 0 - .dw 0x84c0, 0xc92d, 0x84ff, 0xc92d, 0x21, 0 - .dw 0x8540, 0xc92d, 0x857f, 0xc92d, 0x21, 0 - .dw 0x85c0, 0xc92d, 0x85ff, 0xc92d, 0x21, 0 - .dw 0x8640, 0xc92d, 0x867f, 0xc92d, 0x21, 0 - .dw 0x86c0, 0xc92d, 0x86ff, 0xc92d, 0x21, 0 - .dw 0x8740, 0xc92d, 0x877f, 0xc92d, 0x21, 0 - .dw 0x87c0, 0xc92d, 0x87ff, 0xc92d, 0x21, 0 - .dw 0x8840, 0xc92d, 0x887f, 0xc92d, 0x21, 0 - .dw 0x88c0, 0xc92d, 0x88ff, 0xc92d, 0x21, 0 - .dw 0x8940, 0xc92d, 0x897f, 0xc92d, 0x21, 0 - .dw 0x89c0, 0xc92d, 0x89ff, 0xc92d, 0x21, 0 - .dw 0x8a40, 0xc92d, 0x8a7f, 0xc92d, 0x21, 0 - .dw 0x8ac0, 0xc92d, 0x8aff, 0xc92d, 0x21, 0 - .dw 0x8b40, 0xc92d, 0x8b7f, 0xc92d, 0x21, 0 - .dw 0x8bc0, 0xc92d, 0x8bff, 0xc92d, 0x21, 0 - .dw 0x8c40, 0xc92d, 0x8c7f, 0xc92d, 0x21, 0 - .dw 0x8cc0, 0xc92d, 0x8cff, 0xc92d, 0x21, 0 - .dw 0x8d40, 0xc92d, 0x8d7f, 0xc92d, 0x21, 0 - .dw 0x8dc0, 0xc92d, 0x8dff, 0xc92d, 0x21, 0 - .dw 0x8e40, 0xc92d, 0x8e7f, 0xc92d, 0x21, 0 - .dw 0x8ec0, 0xc92d, 0x8eff, 0xc92d, 0x21, 0 - .dw 0x8f40, 0xc92d, 0x8f7f, 0xc92d, 0x21, 0 - .dw 0x8fc0, 0xc92d, 0x8fff, 0xc92d, 0x21, 0 - .dw 0x9040, 0xc92d, 0x907f, 0xc92d, 0x21, 0 - .dw 0x90c0, 0xc92d, 0x90ff, 0xc92d, 0x21, 0 - .dw 0x9140, 0xc92d, 0x917f, 0xc92d, 0x21, 0 - .dw 0x91c0, 0xc92d, 0x91ff, 0xc92d, 0x21, 0 - .dw 0x9240, 0xc92d, 0x927f, 0xc92d, 0x21, 0 - .dw 0x92c0, 0xc92d, 0x92ff, 0xc92d, 0x21, 0 - .dw 0x9340, 0xc92d, 0x937f, 0xc92d, 0x21, 0 - .dw 0x93c0, 0xc92d, 0x93ff, 0xc92d, 0x21, 0 - .dw 0x9440, 0xc92d, 0x947f, 0xc92d, 0x21, 0 - .dw 0x94c0, 0xc92d, 0x94ff, 0xc92d, 0x21, 0 - .dw 0x9540, 0xc92d, 0x957f, 0xc92d, 0x21, 0 - .dw 0x95c0, 0xc92d, 0x95ff, 0xc92d, 0x21, 0 - .dw 0x9640, 0xc92d, 0x967f, 0xc92d, 0x21, 0 - .dw 0x96c0, 0xc92d, 0x96ff, 0xc92d, 0x21, 0 - .dw 0x9740, 0xc92d, 0x977f, 0xc92d, 0x21, 0 - .dw 0x97c0, 0xc92d, 0x97ff, 0xc92d, 0x21, 0 - .dw 0x9840, 0xc92d, 0x987f, 0xc92d, 0x21, 0 - .dw 0x98c0, 0xc92d, 0x98ff, 0xc92d, 0x21, 0 - .dw 0x9940, 0xc92d, 0x997f, 0xc92d, 0x21, 0 - .dw 0x99c0, 0xc92d, 0x9fff, 0xc92d, 0x21, 0 - .dw 0xa040, 0xc92d, 0xa07f, 0xc92d, 0x21, 0 - .dw 0xa0c0, 0xc92d, 0xa0ff, 0xc92d, 0x21, 0 - .dw 0xa140, 0xc92d, 0xa17f, 0xc92d, 0x21, 0 - .dw 0xa1c0, 0xc92d, 0xa1ff, 0xc92d, 0x21, 0 - .dw 0xa240, 0xc92d, 0xa27f, 0xc92d, 0x21, 0 - .dw 0xa2c0, 0xc92d, 0xa2ff, 0xc92d, 0x21, 0 - .dw 0xa340, 0xc92d, 0xa37f, 0xc92d, 0x21, 0 - .dw 0xa3c0, 0xc92d, 0xa3ff, 0xc92d, 0x21, 0 - .dw 0xa440, 0xc92d, 0xa47f, 0xc92d, 0x21, 0 - .dw 0xa4c0, 0xc92d, 0xa4ff, 0xc92d, 0x21, 0 - .dw 0xa540, 0xc92d, 0xa57f, 0xc92d, 0x21, 0 - .dw 0xa5c0, 0xc92d, 0xa5ff, 0xc92d, 0x21, 0 - .dw 0xa640, 0xc92d, 0xa67f, 0xc92d, 0x21, 0 - .dw 0xa6c0, 0xc92d, 0xa6ff, 0xc92d, 0x21, 0 - .dw 0xa740, 0xc92d, 0xa77f, 0xc92d, 0x21, 0 - .dw 0xa7c0, 0xc92d, 0xa7ff, 0xc92d, 0x21, 0 - .dw 0xa840, 0xc92d, 0xa87f, 0xc92d, 0x21, 0 - .dw 0xa8c0, 0xc92d, 0xa8ff, 0xc92d, 0x21, 0 - .dw 0xa940, 0xc92d, 0xa97f, 0xc92d, 0x21, 0 - .dw 0xa9c0, 0xc92d, 0xa9ff, 0xc92d, 0x21, 0 - .dw 0xaa40, 0xc92d, 0xaa7f, 0xc92d, 0x21, 0 - .dw 0xaac0, 0xc92d, 0xaaff, 0xc92d, 0x21, 0 - .dw 0xab40, 0xc92d, 0xab7f, 0xc92d, 0x21, 0 - .dw 0xabc0, 0xc92d, 0xabff, 0xc92d, 0x21, 0 - .dw 0xac40, 0xc92d, 0xac7f, 0xc92d, 0x21, 0 - .dw 0xacc0, 0xc92d, 0xacff, 0xc92d, 0x21, 0 - .dw 0xad40, 0xc92d, 0xad7f, 0xc92d, 0x21, 0 - .dw 0xadc0, 0xc92d, 0xadff, 0xc92d, 0x21, 0 - .dw 0xae40, 0xc92d, 0xae7f, 0xc92d, 0x21, 0 - .dw 0xaec0, 0xc92d, 0xaeff, 0xc92d, 0x21, 0 - .dw 0xaf40, 0xc92d, 0xaf7f, 0xc92d, 0x21, 0 - .dw 0xafc0, 0xc92d, 0xafff, 0xc92d, 0x21, 0 - .dw 0xb040, 0xc92d, 0xb07f, 0xc92d, 0x21, 0 - .dw 0xb0c0, 0xc92d, 0xb0ff, 0xc92d, 0x21, 0 - .dw 0xb140, 0xc92d, 0xb17f, 0xc92d, 0x21, 0 - .dw 0xb1c0, 0xc92d, 0xb1ff, 0xc92d, 0x21, 0 - .dw 0xb240, 0xc92d, 0xb27f, 0xc92d, 0x21, 0 - .dw 0xb2c0, 0xc92d, 0xb2ff, 0xc92d, 0x21, 0 - .dw 0xb340, 0xc92d, 0xb37f, 0xc92d, 0x21, 0 - .dw 0xb3c0, 0xc92d, 0xb3ff, 0xc92d, 0x21, 0 - .dw 0xb440, 0xc92d, 0xb47f, 0xc92d, 0x21, 0 - .dw 0xb4c0, 0xc92d, 0xb4ff, 0xc92d, 0x21, 0 - .dw 0xb540, 0xc92d, 0xb57f, 0xc92d, 0x21, 0 - .dw 0xb5c0, 0xc92d, 0xb5ff, 0xc92d, 0x21, 0 - .dw 0xb640, 0xc92d, 0xb67f, 0xc92d, 0x21, 0 - .dw 0xb6c0, 0xc92d, 0xb6ff, 0xc92d, 0x21, 0 - .dw 0xb740, 0xc92d, 0xb77f, 0xc92d, 0x21, 0 - .dw 0xb7c0, 0xc92d, 0xb7ff, 0xc92d, 0x21, 0 - .dw 0xb840, 0xc92d, 0xb87f, 0xc92d, 0x21, 0 - .dw 0xb8c0, 0xc92d, 0xb8ff, 0xc92d, 0x21, 0 - .dw 0xb940, 0xc92d, 0xb97f, 0xc92d, 0x21, 0 - .dw 0xb9c0, 0xc92d, 0xbfff, 0xc92d, 0x21, 0 - .dw 0xc040, 0xc92d, 0xc07f, 0xc92d, 0x21, 0 - .dw 0xc0c0, 0xc92d, 0xc0ff, 0xc92d, 0x21, 0 - .dw 0xc140, 0xc92d, 0xc17f, 0xc92d, 0x21, 0 - .dw 0xc1c0, 0xc92d, 0xc1ff, 0xc92d, 0x21, 0 - .dw 0xc240, 0xc92d, 0xc27f, 0xc92d, 0x21, 0 - .dw 0xc2c0, 0xc92d, 0xc2ff, 0xc92d, 0x21, 0 - .dw 0xc340, 0xc92d, 0xc37f, 0xc92d, 0x21, 0 - .dw 0xc3c0, 0xc92d, 0xc3ff, 0xc92d, 0x21, 0 - .dw 0xc440, 0xc92d, 0xc47f, 0xc92d, 0x21, 0 - .dw 0xc4c0, 0xc92d, 0xc4ff, 0xc92d, 0x21, 0 - .dw 0xc540, 0xc92d, 0xc57f, 0xc92d, 0x21, 0 - .dw 0xc5c0, 0xc92d, 0xc5ff, 0xc92d, 0x21, 0 - .dw 0xc640, 0xc92d, 0xc67f, 0xc92d, 0x21, 0 - .dw 0xc6c0, 0xc92d, 0xc6ff, 0xc92d, 0x21, 0 - .dw 0xc740, 0xc92d, 0xc77f, 0xc92d, 0x21, 0 - .dw 0xc7c0, 0xc92d, 0xc7ff, 0xc92d, 0x21, 0 - .dw 0xc840, 0xc92d, 0xc87f, 0xc92d, 0x21, 0 - .dw 0xc8c0, 0xc92d, 0xc8ff, 0xc92d, 0x21, 0 - .dw 0xc940, 0xc92d, 0xc97f, 0xc92d, 0x21, 0 - .dw 0xc9c0, 0xc92d, 0xc9ff, 0xc92d, 0x21, 0 - .dw 0xca40, 0xc92d, 0xca7f, 0xc92d, 0x21, 0 - .dw 0xcac0, 0xc92d, 0xcaff, 0xc92d, 0x21, 0 - .dw 0xcb40, 0xc92d, 0xcb7f, 0xc92d, 0x21, 0 - .dw 0xcbc0, 0xc92d, 0xcbff, 0xc92d, 0x21, 0 - .dw 0xcc40, 0xc92d, 0xcc7f, 0xc92d, 0x21, 0 - .dw 0xccc0, 0xc92d, 0xccff, 0xc92d, 0x21, 0 - .dw 0xcd40, 0xc92d, 0xcd7f, 0xc92d, 0x21, 0 - .dw 0xcdc0, 0xc92d, 0xcdff, 0xc92d, 0x21, 0 - .dw 0xce40, 0xc92d, 0xce7f, 0xc92d, 0x21, 0 - .dw 0xcec0, 0xc92d, 0xceff, 0xc92d, 0x21, 0 - .dw 0xcf40, 0xc92d, 0xcf7f, 0xc92d, 0x21, 0 - .dw 0xcfc0, 0xc92d, 0xcfff, 0xc92d, 0x21, 0 - .dw 0xd040, 0xc92d, 0xd07f, 0xc92d, 0x21, 0 - .dw 0xd0c0, 0xc92d, 0xd0ff, 0xc92d, 0x21, 0 - .dw 0xd140, 0xc92d, 0xd17f, 0xc92d, 0x21, 0 - .dw 0xd1c0, 0xc92d, 0xd1ff, 0xc92d, 0x21, 0 - .dw 0xd240, 0xc92d, 0xd27f, 0xc92d, 0x21, 0 - .dw 0xd2c0, 0xc92d, 0xd2ff, 0xc92d, 0x21, 0 - .dw 0xd340, 0xc92d, 0xd37f, 0xc92d, 0x21, 0 - .dw 0xd3c0, 0xc92d, 0xd3ff, 0xc92d, 0x21, 0 - .dw 0xd440, 0xc92d, 0xd47f, 0xc92d, 0x21, 0 - .dw 0xd4c0, 0xc92d, 0xd4ff, 0xc92d, 0x21, 0 - .dw 0xd540, 0xc92d, 0xd57f, 0xc92d, 0x21, 0 - .dw 0xd5c0, 0xc92d, 0xd5ff, 0xc92d, 0x21, 0 - .dw 0xd640, 0xc92d, 0xd67f, 0xc92d, 0x21, 0 - .dw 0xd6c0, 0xc92d, 0xd6ff, 0xc92d, 0x21, 0 - .dw 0xd740, 0xc92d, 0xd77f, 0xc92d, 0x21, 0 - .dw 0xd7c0, 0xc92d, 0xd7ff, 0xc92d, 0x21, 0 - .dw 0xd840, 0xc92d, 0xd87f, 0xc92d, 0x21, 0 - .dw 0xd8c0, 0xc92d, 0xd8ff, 0xc92d, 0x21, 0 - .dw 0xd940, 0xc92d, 0xd97f, 0xc92d, 0x21, 0 - .dw 0xd9c0, 0xc92d, 0xdfff, 0xc92d, 0x21, 0 - .dw 0xe040, 0xc92d, 0xe07f, 0xc92d, 0x21, 0 - .dw 0xe0c0, 0xc92d, 0xe0ff, 0xc92d, 0x21, 0 - .dw 0xe140, 0xc92d, 0xe17f, 0xc92d, 0x21, 0 - .dw 0xe1c0, 0xc92d, 0xe1ff, 0xc92d, 0x21, 0 - .dw 0xe240, 0xc92d, 0xe27f, 0xc92d, 0x21, 0 - .dw 0xe2c0, 0xc92d, 0xe2ff, 0xc92d, 0x21, 0 - .dw 0xe340, 0xc92d, 0xe37f, 0xc92d, 0x21, 0 - .dw 0xe3c0, 0xc92d, 0xe3ff, 0xc92d, 0x21, 0 - .dw 0xe440, 0xc92d, 0xe47f, 0xc92d, 0x21, 0 - .dw 0xe4c0, 0xc92d, 0xe4ff, 0xc92d, 0x21, 0 - .dw 0xe540, 0xc92d, 0xe57f, 0xc92d, 0x21, 0 - .dw 0xe5c0, 0xc92d, 0xe5ff, 0xc92d, 0x21, 0 - .dw 0xe640, 0xc92d, 0xe67f, 0xc92d, 0x21, 0 - .dw 0xe6c0, 0xc92d, 0xe6ff, 0xc92d, 0x21, 0 - .dw 0xe740, 0xc92d, 0xe77f, 0xc92d, 0x21, 0 - .dw 0xe7c0, 0xc92d, 0xe7ff, 0xc92d, 0x21, 0 - .dw 0xe840, 0xc92d, 0xe87f, 0xc92d, 0x21, 0 - .dw 0xe8c0, 0xc92d, 0xe8ff, 0xc92d, 0x21, 0 - .dw 0xe940, 0xc92d, 0xe97f, 0xc92d, 0x21, 0 - .dw 0xe9c0, 0xc92d, 0xe9ff, 0xc92d, 0x21, 0 - .dw 0xea40, 0xc92d, 0xea7f, 0xc92d, 0x21, 0 - .dw 0xeac0, 0xc92d, 0xeaff, 0xc92d, 0x21, 0 - .dw 0xeb40, 0xc92d, 0xeb7f, 0xc92d, 0x21, 0 - .dw 0xebc0, 0xc92d, 0xebff, 0xc92d, 0x21, 0 - .dw 0xec40, 0xc92d, 0xec7f, 0xc92d, 0x21, 0 - .dw 0xecc0, 0xc92d, 0xecff, 0xc92d, 0x21, 0 - .dw 0xed40, 0xc92d, 0xed7f, 0xc92d, 0x21, 0 - .dw 0xedc0, 0xc92d, 0xedff, 0xc92d, 0x21, 0 - .dw 0xee40, 0xc92d, 0xee7f, 0xc92d, 0x21, 0 - .dw 0xeec0, 0xc92d, 0xeeff, 0xc92d, 0x21, 0 - .dw 0xef40, 0xc92d, 0xef7f, 0xc92d, 0x21, 0 - .dw 0xefc0, 0xc92d, 0xefff, 0xc92d, 0x21, 0 - .dw 0xf040, 0xc92d, 0xf07f, 0xc92d, 0x21, 0 - .dw 0xf0c0, 0xc92d, 0xf0ff, 0xc92d, 0x21, 0 - .dw 0xf140, 0xc92d, 0xf17f, 0xc92d, 0x21, 0 - .dw 0xf1c0, 0xc92d, 0xf1ff, 0xc92d, 0x21, 0 - .dw 0xf240, 0xc92d, 0xf27f, 0xc92d, 0x21, 0 - .dw 0xf2c0, 0xc92d, 0xf2ff, 0xc92d, 0x21, 0 - .dw 0xf340, 0xc92d, 0xf37f, 0xc92d, 0x21, 0 - .dw 0xf3c0, 0xc92d, 0xf3ff, 0xc92d, 0x21, 0 - .dw 0xf440, 0xc92d, 0xf47f, 0xc92d, 0x21, 0 - .dw 0xf4c0, 0xc92d, 0xf4ff, 0xc92d, 0x21, 0 - .dw 0xf540, 0xc92d, 0xf57f, 0xc92d, 0x21, 0 - .dw 0xf5c0, 0xc92d, 0xf5ff, 0xc92d, 0x21, 0 - .dw 0xf640, 0xc92d, 0xf67f, 0xc92d, 0x21, 0 - .dw 0xf6c0, 0xc92d, 0xf6ff, 0xc92d, 0x21, 0 - .dw 0xf740, 0xc92d, 0xf77f, 0xc92d, 0x21, 0 - .dw 0xf7c0, 0xc92d, 0xf7ff, 0xc92d, 0x21, 0 - .dw 0xf840, 0xc92d, 0xf87f, 0xc92d, 0x21, 0 - .dw 0xf8c0, 0xc92d, 0xf8ff, 0xc92d, 0x21, 0 - .dw 0xf940, 0xc92d, 0xf97f, 0xc92d, 0x21, 0 - .dw 0xf9c0, 0xc92d, 0xffff, 0xc92d, 0x21, 0 - .dw 0x0040, 0xc92e, 0x007f, 0xc92e, 0x21, 0 - .dw 0x00c0, 0xc92e, 0x00ff, 0xc92e, 0x21, 0 - .dw 0x0140, 0xc92e, 0x017f, 0xc92e, 0x21, 0 - .dw 0x01c0, 0xc92e, 0x01ff, 0xc92e, 0x21, 0 - .dw 0x0240, 0xc92e, 0x027f, 0xc92e, 0x21, 0 - .dw 0x02c0, 0xc92e, 0x02ff, 0xc92e, 0x21, 0 - .dw 0x0340, 0xc92e, 0x037f, 0xc92e, 0x21, 0 - .dw 0x03c0, 0xc92e, 0x03ff, 0xc92e, 0x21, 0 - .dw 0x0440, 0xc92e, 0x047f, 0xc92e, 0x21, 0 - .dw 0x04c0, 0xc92e, 0x04ff, 0xc92e, 0x21, 0 - .dw 0x0540, 0xc92e, 0x057f, 0xc92e, 0x21, 0 - .dw 0x05c0, 0xc92e, 0x05ff, 0xc92e, 0x21, 0 - .dw 0x0640, 0xc92e, 0x067f, 0xc92e, 0x21, 0 - .dw 0x06c0, 0xc92e, 0x06ff, 0xc92e, 0x21, 0 - .dw 0x0740, 0xc92e, 0x077f, 0xc92e, 0x21, 0 - .dw 0x07c0, 0xc92e, 0x07ff, 0xc92e, 0x21, 0 - .dw 0x0840, 0xc92e, 0x087f, 0xc92e, 0x21, 0 - .dw 0x08c0, 0xc92e, 0x08ff, 0xc92e, 0x21, 0 - .dw 0x0940, 0xc92e, 0x097f, 0xc92e, 0x21, 0 - .dw 0x09c0, 0xc92e, 0x09ff, 0xc92e, 0x21, 0 - .dw 0x0a40, 0xc92e, 0x0a7f, 0xc92e, 0x21, 0 - .dw 0x0ac0, 0xc92e, 0x0aff, 0xc92e, 0x21, 0 - .dw 0x0b40, 0xc92e, 0x0b7f, 0xc92e, 0x21, 0 - .dw 0x0bc0, 0xc92e, 0x0bff, 0xc92e, 0x21, 0 - .dw 0x0c40, 0xc92e, 0x0c7f, 0xc92e, 0x21, 0 - .dw 0x0cc0, 0xc92e, 0x0cff, 0xc92e, 0x21, 0 - .dw 0x0d40, 0xc92e, 0x0d7f, 0xc92e, 0x21, 0 - .dw 0x0dc0, 0xc92e, 0x0dff, 0xc92e, 0x21, 0 - .dw 0x0e40, 0xc92e, 0x0e7f, 0xc92e, 0x21, 0 - .dw 0x0ec0, 0xc92e, 0x0eff, 0xc92e, 0x21, 0 - .dw 0x0f40, 0xc92e, 0x0f7f, 0xc92e, 0x21, 0 - .dw 0x0fc0, 0xc92e, 0x0fff, 0xc92e, 0x21, 0 - .dw 0x1040, 0xc92e, 0x107f, 0xc92e, 0x21, 0 - .dw 0x10c0, 0xc92e, 0x10ff, 0xc92e, 0x21, 0 - .dw 0x1140, 0xc92e, 0x117f, 0xc92e, 0x21, 0 - .dw 0x11c0, 0xc92e, 0x11ff, 0xc92e, 0x21, 0 - .dw 0x1240, 0xc92e, 0x127f, 0xc92e, 0x21, 0 - .dw 0x12c0, 0xc92e, 0x12ff, 0xc92e, 0x21, 0 - .dw 0x1340, 0xc92e, 0x137f, 0xc92e, 0x21, 0 - .dw 0x13c0, 0xc92e, 0x13ff, 0xc92e, 0x21, 0 - .dw 0x1440, 0xc92e, 0x147f, 0xc92e, 0x21, 0 - .dw 0x14c0, 0xc92e, 0x14ff, 0xc92e, 0x21, 0 - .dw 0x1540, 0xc92e, 0x157f, 0xc92e, 0x21, 0 - .dw 0x15c0, 0xc92e, 0x15ff, 0xc92e, 0x21, 0 - .dw 0x1640, 0xc92e, 0x167f, 0xc92e, 0x21, 0 - .dw 0x16c0, 0xc92e, 0x16ff, 0xc92e, 0x21, 0 - .dw 0x1740, 0xc92e, 0x177f, 0xc92e, 0x21, 0 - .dw 0x17c0, 0xc92e, 0x17ff, 0xc92e, 0x21, 0 - .dw 0x1840, 0xc92e, 0x187f, 0xc92e, 0x21, 0 - .dw 0x18c0, 0xc92e, 0x18ff, 0xc92e, 0x21, 0 - .dw 0x1940, 0xc92e, 0x197f, 0xc92e, 0x21, 0 - .dw 0x19c0, 0xc92e, 0x1fff, 0xc92e, 0x21, 0 - .dw 0x2040, 0xc92e, 0x207f, 0xc92e, 0x21, 0 - .dw 0x20c0, 0xc92e, 0x20ff, 0xc92e, 0x21, 0 - .dw 0x2140, 0xc92e, 0x217f, 0xc92e, 0x21, 0 - .dw 0x21c0, 0xc92e, 0x21ff, 0xc92e, 0x21, 0 - .dw 0x2240, 0xc92e, 0x227f, 0xc92e, 0x21, 0 - .dw 0x22c0, 0xc92e, 0x22ff, 0xc92e, 0x21, 0 - .dw 0x2340, 0xc92e, 0x237f, 0xc92e, 0x21, 0 - .dw 0x23c0, 0xc92e, 0x23ff, 0xc92e, 0x21, 0 - .dw 0x2440, 0xc92e, 0x247f, 0xc92e, 0x21, 0 - .dw 0x24c0, 0xc92e, 0x24ff, 0xc92e, 0x21, 0 - .dw 0x2540, 0xc92e, 0x257f, 0xc92e, 0x21, 0 - .dw 0x25c0, 0xc92e, 0x25ff, 0xc92e, 0x21, 0 - .dw 0x2640, 0xc92e, 0x267f, 0xc92e, 0x21, 0 - .dw 0x26c0, 0xc92e, 0x26ff, 0xc92e, 0x21, 0 - .dw 0x2740, 0xc92e, 0x277f, 0xc92e, 0x21, 0 - .dw 0x27c0, 0xc92e, 0x27ff, 0xc92e, 0x21, 0 - .dw 0x2840, 0xc92e, 0x287f, 0xc92e, 0x21, 0 - .dw 0x28c0, 0xc92e, 0x28ff, 0xc92e, 0x21, 0 - .dw 0x2940, 0xc92e, 0x297f, 0xc92e, 0x21, 0 - .dw 0x29c0, 0xc92e, 0x29ff, 0xc92e, 0x21, 0 - .dw 0x2a40, 0xc92e, 0x2a7f, 0xc92e, 0x21, 0 - .dw 0x2ac0, 0xc92e, 0x2aff, 0xc92e, 0x21, 0 - .dw 0x2b40, 0xc92e, 0x2b7f, 0xc92e, 0x21, 0 - .dw 0x2bc0, 0xc92e, 0x2bff, 0xc92e, 0x21, 0 - .dw 0x2c40, 0xc92e, 0x2c7f, 0xc92e, 0x21, 0 - .dw 0x2cc0, 0xc92e, 0x2cff, 0xc92e, 0x21, 0 - .dw 0x2d40, 0xc92e, 0x2d7f, 0xc92e, 0x21, 0 - .dw 0x2dc0, 0xc92e, 0x2dff, 0xc92e, 0x21, 0 - .dw 0x2e40, 0xc92e, 0x2e7f, 0xc92e, 0x21, 0 - .dw 0x2ec0, 0xc92e, 0x2eff, 0xc92e, 0x21, 0 - .dw 0x2f40, 0xc92e, 0x2f7f, 0xc92e, 0x21, 0 - .dw 0x2fc0, 0xc92e, 0x2fff, 0xc92e, 0x21, 0 - .dw 0x3040, 0xc92e, 0x307f, 0xc92e, 0x21, 0 - .dw 0x30c0, 0xc92e, 0x30ff, 0xc92e, 0x21, 0 - .dw 0x3140, 0xc92e, 0x317f, 0xc92e, 0x21, 0 - .dw 0x31c0, 0xc92e, 0x31ff, 0xc92e, 0x21, 0 - .dw 0x3240, 0xc92e, 0x327f, 0xc92e, 0x21, 0 - .dw 0x32c0, 0xc92e, 0x32ff, 0xc92e, 0x21, 0 - .dw 0x3340, 0xc92e, 0x337f, 0xc92e, 0x21, 0 - .dw 0x33c0, 0xc92e, 0x33ff, 0xc92e, 0x21, 0 - .dw 0x3440, 0xc92e, 0x347f, 0xc92e, 0x21, 0 - .dw 0x34c0, 0xc92e, 0x34ff, 0xc92e, 0x21, 0 - .dw 0x3540, 0xc92e, 0x357f, 0xc92e, 0x21, 0 - .dw 0x35c0, 0xc92e, 0x35ff, 0xc92e, 0x21, 0 - .dw 0x3640, 0xc92e, 0x367f, 0xc92e, 0x21, 0 - .dw 0x36c0, 0xc92e, 0x36ff, 0xc92e, 0x21, 0 - .dw 0x3740, 0xc92e, 0x377f, 0xc92e, 0x21, 0 - .dw 0x37c0, 0xc92e, 0x37ff, 0xc92e, 0x21, 0 - .dw 0x3840, 0xc92e, 0x387f, 0xc92e, 0x21, 0 - .dw 0x38c0, 0xc92e, 0x38ff, 0xc92e, 0x21, 0 - .dw 0x3940, 0xc92e, 0x397f, 0xc92e, 0x21, 0 - .dw 0x39c0, 0xc92e, 0x3fff, 0xc92e, 0x21, 0 - .dw 0x4040, 0xc92e, 0x407f, 0xc92e, 0x21, 0 - .dw 0x40c0, 0xc92e, 0x40ff, 0xc92e, 0x21, 0 - .dw 0x4140, 0xc92e, 0x417f, 0xc92e, 0x21, 0 - .dw 0x41c0, 0xc92e, 0x41ff, 0xc92e, 0x21, 0 - .dw 0x4240, 0xc92e, 0x427f, 0xc92e, 0x21, 0 - .dw 0x42c0, 0xc92e, 0x42ff, 0xc92e, 0x21, 0 - .dw 0x4340, 0xc92e, 0x437f, 0xc92e, 0x21, 0 - .dw 0x43c0, 0xc92e, 0x43ff, 0xc92e, 0x21, 0 - .dw 0x4440, 0xc92e, 0x447f, 0xc92e, 0x21, 0 - .dw 0x44c0, 0xc92e, 0x44ff, 0xc92e, 0x21, 0 - .dw 0x4540, 0xc92e, 0x457f, 0xc92e, 0x21, 0 - .dw 0x45c0, 0xc92e, 0x45ff, 0xc92e, 0x21, 0 - .dw 0x4640, 0xc92e, 0x467f, 0xc92e, 0x21, 0 - .dw 0x46c0, 0xc92e, 0x46ff, 0xc92e, 0x21, 0 - .dw 0x4740, 0xc92e, 0x477f, 0xc92e, 0x21, 0 - .dw 0x47c0, 0xc92e, 0x47ff, 0xc92e, 0x21, 0 - .dw 0x4840, 0xc92e, 0x487f, 0xc92e, 0x21, 0 - .dw 0x48c0, 0xc92e, 0x48ff, 0xc92e, 0x21, 0 - .dw 0x4940, 0xc92e, 0x497f, 0xc92e, 0x21, 0 - .dw 0x49c0, 0xc92e, 0x49ff, 0xc92e, 0x21, 0 - .dw 0x4a40, 0xc92e, 0x4a7f, 0xc92e, 0x21, 0 - .dw 0x4ac0, 0xc92e, 0x4aff, 0xc92e, 0x21, 0 - .dw 0x4b40, 0xc92e, 0x4b7f, 0xc92e, 0x21, 0 - .dw 0x4bc0, 0xc92e, 0x4bff, 0xc92e, 0x21, 0 - .dw 0x4c40, 0xc92e, 0x4c7f, 0xc92e, 0x21, 0 - .dw 0x4cc0, 0xc92e, 0x4cff, 0xc92e, 0x21, 0 - .dw 0x4d40, 0xc92e, 0x4d7f, 0xc92e, 0x21, 0 - .dw 0x4dc0, 0xc92e, 0x4dff, 0xc92e, 0x21, 0 - .dw 0x4e40, 0xc92e, 0x4e7f, 0xc92e, 0x21, 0 - .dw 0x4ec0, 0xc92e, 0x4eff, 0xc92e, 0x21, 0 - .dw 0x4f40, 0xc92e, 0x4f7f, 0xc92e, 0x21, 0 - .dw 0x4fc0, 0xc92e, 0x4fff, 0xc92e, 0x21, 0 - .dw 0x5040, 0xc92e, 0x507f, 0xc92e, 0x21, 0 - .dw 0x50c0, 0xc92e, 0x50ff, 0xc92e, 0x21, 0 - .dw 0x5140, 0xc92e, 0x517f, 0xc92e, 0x21, 0 - .dw 0x51c0, 0xc92e, 0x51ff, 0xc92e, 0x21, 0 - .dw 0x5240, 0xc92e, 0x527f, 0xc92e, 0x21, 0 - .dw 0x52c0, 0xc92e, 0x52ff, 0xc92e, 0x21, 0 - .dw 0x5340, 0xc92e, 0x537f, 0xc92e, 0x21, 0 - .dw 0x53c0, 0xc92e, 0x53ff, 0xc92e, 0x21, 0 - .dw 0x5440, 0xc92e, 0x547f, 0xc92e, 0x21, 0 - .dw 0x54c0, 0xc92e, 0x54ff, 0xc92e, 0x21, 0 - .dw 0x5540, 0xc92e, 0x557f, 0xc92e, 0x21, 0 - .dw 0x55c0, 0xc92e, 0x55ff, 0xc92e, 0x21, 0 - .dw 0x5640, 0xc92e, 0x567f, 0xc92e, 0x21, 0 - .dw 0x56c0, 0xc92e, 0x56ff, 0xc92e, 0x21, 0 - .dw 0x5740, 0xc92e, 0x577f, 0xc92e, 0x21, 0 - .dw 0x57c0, 0xc92e, 0x57ff, 0xc92e, 0x21, 0 - .dw 0x5840, 0xc92e, 0x587f, 0xc92e, 0x21, 0 - .dw 0x58c0, 0xc92e, 0x58ff, 0xc92e, 0x21, 0 - .dw 0x5940, 0xc92e, 0x597f, 0xc92e, 0x21, 0 - .dw 0x59c0, 0xc92e, 0x5fff, 0xc92e, 0x21, 0 - .dw 0x6040, 0xc92e, 0x607f, 0xc92e, 0x21, 0 - .dw 0x60c0, 0xc92e, 0x60ff, 0xc92e, 0x21, 0 - .dw 0x6140, 0xc92e, 0x617f, 0xc92e, 0x21, 0 - .dw 0x61c0, 0xc92e, 0x61ff, 0xc92e, 0x21, 0 - .dw 0x6240, 0xc92e, 0x627f, 0xc92e, 0x21, 0 - .dw 0x62c0, 0xc92e, 0x62ff, 0xc92e, 0x21, 0 - .dw 0x6340, 0xc92e, 0x637f, 0xc92e, 0x21, 0 - .dw 0x63c0, 0xc92e, 0x63ff, 0xc92e, 0x21, 0 - .dw 0x6440, 0xc92e, 0x647f, 0xc92e, 0x21, 0 - .dw 0x64c0, 0xc92e, 0x64ff, 0xc92e, 0x21, 0 - .dw 0x6540, 0xc92e, 0x657f, 0xc92e, 0x21, 0 - .dw 0x65c0, 0xc92e, 0x65ff, 0xc92e, 0x21, 0 - .dw 0x6640, 0xc92e, 0x667f, 0xc92e, 0x21, 0 - .dw 0x66c0, 0xc92e, 0x66ff, 0xc92e, 0x21, 0 - .dw 0x6740, 0xc92e, 0x677f, 0xc92e, 0x21, 0 - .dw 0x67c0, 0xc92e, 0x67ff, 0xc92e, 0x21, 0 - .dw 0x6840, 0xc92e, 0x687f, 0xc92e, 0x21, 0 - .dw 0x68c0, 0xc92e, 0x68ff, 0xc92e, 0x21, 0 - .dw 0x6940, 0xc92e, 0x697f, 0xc92e, 0x21, 0 - .dw 0x69c0, 0xc92e, 0x69ff, 0xc92e, 0x21, 0 - .dw 0x6a40, 0xc92e, 0x6a7f, 0xc92e, 0x21, 0 - .dw 0x6ac0, 0xc92e, 0x6aff, 0xc92e, 0x21, 0 - .dw 0x6b40, 0xc92e, 0x6b7f, 0xc92e, 0x21, 0 - .dw 0x6bc0, 0xc92e, 0x6bff, 0xc92e, 0x21, 0 - .dw 0x6c40, 0xc92e, 0x6c7f, 0xc92e, 0x21, 0 - .dw 0x6cc0, 0xc92e, 0x6cff, 0xc92e, 0x21, 0 - .dw 0x6d40, 0xc92e, 0x6d7f, 0xc92e, 0x21, 0 - .dw 0x6dc0, 0xc92e, 0x6dff, 0xc92e, 0x21, 0 - .dw 0x6e40, 0xc92e, 0x6e7f, 0xc92e, 0x21, 0 - .dw 0x6ec0, 0xc92e, 0x6eff, 0xc92e, 0x21, 0 - .dw 0x6f40, 0xc92e, 0x6f7f, 0xc92e, 0x21, 0 - .dw 0x6fc0, 0xc92e, 0x6fff, 0xc92e, 0x21, 0 - .dw 0x7040, 0xc92e, 0x707f, 0xc92e, 0x21, 0 - .dw 0x70c0, 0xc92e, 0x70ff, 0xc92e, 0x21, 0 - .dw 0x7140, 0xc92e, 0x717f, 0xc92e, 0x21, 0 - .dw 0x71c0, 0xc92e, 0x71ff, 0xc92e, 0x21, 0 - .dw 0x7240, 0xc92e, 0x727f, 0xc92e, 0x21, 0 - .dw 0x72c0, 0xc92e, 0x72ff, 0xc92e, 0x21, 0 - .dw 0x7340, 0xc92e, 0x737f, 0xc92e, 0x21, 0 - .dw 0x73c0, 0xc92e, 0x73ff, 0xc92e, 0x21, 0 - .dw 0x7440, 0xc92e, 0x747f, 0xc92e, 0x21, 0 - .dw 0x74c0, 0xc92e, 0x74ff, 0xc92e, 0x21, 0 - .dw 0x7540, 0xc92e, 0x757f, 0xc92e, 0x21, 0 - .dw 0x75c0, 0xc92e, 0x75ff, 0xc92e, 0x21, 0 - .dw 0x7640, 0xc92e, 0x767f, 0xc92e, 0x21, 0 - .dw 0x76c0, 0xc92e, 0x76ff, 0xc92e, 0x21, 0 - .dw 0x7740, 0xc92e, 0x777f, 0xc92e, 0x21, 0 - .dw 0x77c0, 0xc92e, 0x77ff, 0xc92e, 0x21, 0 - .dw 0x7840, 0xc92e, 0x787f, 0xc92e, 0x21, 0 - .dw 0x78c0, 0xc92e, 0x78ff, 0xc92e, 0x21, 0 - .dw 0x7940, 0xc92e, 0x797f, 0xc92e, 0x21, 0 - .dw 0x79c0, 0xc92e, 0x7fff, 0xc92e, 0x21, 0 - .dw 0x8040, 0xc92e, 0x807f, 0xc92e, 0x21, 0 - .dw 0x80c0, 0xc92e, 0x80ff, 0xc92e, 0x21, 0 - .dw 0x8140, 0xc92e, 0x817f, 0xc92e, 0x21, 0 - .dw 0x81c0, 0xc92e, 0x81ff, 0xc92e, 0x21, 0 - .dw 0x8240, 0xc92e, 0x827f, 0xc92e, 0x21, 0 - .dw 0x82c0, 0xc92e, 0x82ff, 0xc92e, 0x21, 0 - .dw 0x8340, 0xc92e, 0x837f, 0xc92e, 0x21, 0 - .dw 0x83c0, 0xc92e, 0x83ff, 0xc92e, 0x21, 0 - .dw 0x8440, 0xc92e, 0x847f, 0xc92e, 0x21, 0 - .dw 0x84c0, 0xc92e, 0x84ff, 0xc92e, 0x21, 0 - .dw 0x8540, 0xc92e, 0x857f, 0xc92e, 0x21, 0 - .dw 0x85c0, 0xc92e, 0x85ff, 0xc92e, 0x21, 0 - .dw 0x8640, 0xc92e, 0x867f, 0xc92e, 0x21, 0 - .dw 0x86c0, 0xc92e, 0x86ff, 0xc92e, 0x21, 0 - .dw 0x8740, 0xc92e, 0x877f, 0xc92e, 0x21, 0 - .dw 0x87c0, 0xc92e, 0x87ff, 0xc92e, 0x21, 0 - .dw 0x8840, 0xc92e, 0x887f, 0xc92e, 0x21, 0 - .dw 0x88c0, 0xc92e, 0x88ff, 0xc92e, 0x21, 0 - .dw 0x8940, 0xc92e, 0x897f, 0xc92e, 0x21, 0 - .dw 0x89c0, 0xc92e, 0x89ff, 0xc92e, 0x21, 0 - .dw 0x8a40, 0xc92e, 0x8a7f, 0xc92e, 0x21, 0 - .dw 0x8ac0, 0xc92e, 0x8aff, 0xc92e, 0x21, 0 - .dw 0x8b40, 0xc92e, 0x8b7f, 0xc92e, 0x21, 0 - .dw 0x8bc0, 0xc92e, 0x8bff, 0xc92e, 0x21, 0 - .dw 0x8c40, 0xc92e, 0x8c7f, 0xc92e, 0x21, 0 - .dw 0x8cc0, 0xc92e, 0x8cff, 0xc92e, 0x21, 0 - .dw 0x8d40, 0xc92e, 0x8d7f, 0xc92e, 0x21, 0 - .dw 0x8dc0, 0xc92e, 0x8dff, 0xc92e, 0x21, 0 - .dw 0x8e40, 0xc92e, 0x8e7f, 0xc92e, 0x21, 0 - .dw 0x8ec0, 0xc92e, 0x8eff, 0xc92e, 0x21, 0 - .dw 0x8f40, 0xc92e, 0x8f7f, 0xc92e, 0x21, 0 - .dw 0x8fc0, 0xc92e, 0x8fff, 0xc92e, 0x21, 0 - .dw 0x9040, 0xc92e, 0x907f, 0xc92e, 0x21, 0 - .dw 0x90c0, 0xc92e, 0x90ff, 0xc92e, 0x21, 0 - .dw 0x9140, 0xc92e, 0x917f, 0xc92e, 0x21, 0 - .dw 0x91c0, 0xc92e, 0x91ff, 0xc92e, 0x21, 0 - .dw 0x9240, 0xc92e, 0x927f, 0xc92e, 0x21, 0 - .dw 0x92c0, 0xc92e, 0x92ff, 0xc92e, 0x21, 0 - .dw 0x9340, 0xc92e, 0x937f, 0xc92e, 0x21, 0 - .dw 0x93c0, 0xc92e, 0x93ff, 0xc92e, 0x21, 0 - .dw 0x9440, 0xc92e, 0x947f, 0xc92e, 0x21, 0 - .dw 0x94c0, 0xc92e, 0x94ff, 0xc92e, 0x21, 0 - .dw 0x9540, 0xc92e, 0x957f, 0xc92e, 0x21, 0 - .dw 0x95c0, 0xc92e, 0x95ff, 0xc92e, 0x21, 0 - .dw 0x9640, 0xc92e, 0x967f, 0xc92e, 0x21, 0 - .dw 0x96c0, 0xc92e, 0x96ff, 0xc92e, 0x21, 0 - .dw 0x9740, 0xc92e, 0x977f, 0xc92e, 0x21, 0 - .dw 0x97c0, 0xc92e, 0x97ff, 0xc92e, 0x21, 0 - .dw 0x9840, 0xc92e, 0x987f, 0xc92e, 0x21, 0 - .dw 0x98c0, 0xc92e, 0x98ff, 0xc92e, 0x21, 0 - .dw 0x9940, 0xc92e, 0x997f, 0xc92e, 0x21, 0 - .dw 0x99c0, 0xc92e, 0x9fff, 0xc92e, 0x21, 0 - .dw 0xa040, 0xc92e, 0xa07f, 0xc92e, 0x21, 0 - .dw 0xa0c0, 0xc92e, 0xa0ff, 0xc92e, 0x21, 0 - .dw 0xa140, 0xc92e, 0xa17f, 0xc92e, 0x21, 0 - .dw 0xa1c0, 0xc92e, 0xa1ff, 0xc92e, 0x21, 0 - .dw 0xa240, 0xc92e, 0xa27f, 0xc92e, 0x21, 0 - .dw 0xa2c0, 0xc92e, 0xa2ff, 0xc92e, 0x21, 0 - .dw 0xa340, 0xc92e, 0xa37f, 0xc92e, 0x21, 0 - .dw 0xa3c0, 0xc92e, 0xa3ff, 0xc92e, 0x21, 0 - .dw 0xa440, 0xc92e, 0xa47f, 0xc92e, 0x21, 0 - .dw 0xa4c0, 0xc92e, 0xa4ff, 0xc92e, 0x21, 0 - .dw 0xa540, 0xc92e, 0xa57f, 0xc92e, 0x21, 0 - .dw 0xa5c0, 0xc92e, 0xa5ff, 0xc92e, 0x21, 0 - .dw 0xa640, 0xc92e, 0xa67f, 0xc92e, 0x21, 0 - .dw 0xa6c0, 0xc92e, 0xa6ff, 0xc92e, 0x21, 0 - .dw 0xa740, 0xc92e, 0xa77f, 0xc92e, 0x21, 0 - .dw 0xa7c0, 0xc92e, 0xa7ff, 0xc92e, 0x21, 0 - .dw 0xa840, 0xc92e, 0xa87f, 0xc92e, 0x21, 0 - .dw 0xa8c0, 0xc92e, 0xa8ff, 0xc92e, 0x21, 0 - .dw 0xa940, 0xc92e, 0xa97f, 0xc92e, 0x21, 0 - .dw 0xa9c0, 0xc92e, 0xa9ff, 0xc92e, 0x21, 0 - .dw 0xaa40, 0xc92e, 0xaa7f, 0xc92e, 0x21, 0 - .dw 0xaac0, 0xc92e, 0xaaff, 0xc92e, 0x21, 0 - .dw 0xab40, 0xc92e, 0xab7f, 0xc92e, 0x21, 0 - .dw 0xabc0, 0xc92e, 0xabff, 0xc92e, 0x21, 0 - .dw 0xac40, 0xc92e, 0xac7f, 0xc92e, 0x21, 0 - .dw 0xacc0, 0xc92e, 0xacff, 0xc92e, 0x21, 0 - .dw 0xad40, 0xc92e, 0xad7f, 0xc92e, 0x21, 0 - .dw 0xadc0, 0xc92e, 0xadff, 0xc92e, 0x21, 0 - .dw 0xae40, 0xc92e, 0xae7f, 0xc92e, 0x21, 0 - .dw 0xaec0, 0xc92e, 0xaeff, 0xc92e, 0x21, 0 - .dw 0xaf40, 0xc92e, 0xaf7f, 0xc92e, 0x21, 0 - .dw 0xafc0, 0xc92e, 0xafff, 0xc92e, 0x21, 0 - .dw 0xb040, 0xc92e, 0xb07f, 0xc92e, 0x21, 0 - .dw 0xb0c0, 0xc92e, 0xb0ff, 0xc92e, 0x21, 0 - .dw 0xb140, 0xc92e, 0xb17f, 0xc92e, 0x21, 0 - .dw 0xb1c0, 0xc92e, 0xb1ff, 0xc92e, 0x21, 0 - .dw 0xb240, 0xc92e, 0xb27f, 0xc92e, 0x21, 0 - .dw 0xb2c0, 0xc92e, 0xb2ff, 0xc92e, 0x21, 0 - .dw 0xb340, 0xc92e, 0xb37f, 0xc92e, 0x21, 0 - .dw 0xb3c0, 0xc92e, 0xb3ff, 0xc92e, 0x21, 0 - .dw 0xb440, 0xc92e, 0xb47f, 0xc92e, 0x21, 0 - .dw 0xb4c0, 0xc92e, 0xb4ff, 0xc92e, 0x21, 0 - .dw 0xb540, 0xc92e, 0xb57f, 0xc92e, 0x21, 0 - .dw 0xb5c0, 0xc92e, 0xb5ff, 0xc92e, 0x21, 0 - .dw 0xb640, 0xc92e, 0xb67f, 0xc92e, 0x21, 0 - .dw 0xb6c0, 0xc92e, 0xb6ff, 0xc92e, 0x21, 0 - .dw 0xb740, 0xc92e, 0xb77f, 0xc92e, 0x21, 0 - .dw 0xb7c0, 0xc92e, 0xb7ff, 0xc92e, 0x21, 0 - .dw 0xb840, 0xc92e, 0xb87f, 0xc92e, 0x21, 0 - .dw 0xb8c0, 0xc92e, 0xb8ff, 0xc92e, 0x21, 0 - .dw 0xb940, 0xc92e, 0xb97f, 0xc92e, 0x21, 0 - .dw 0xb9c0, 0xc92e, 0xbfff, 0xc92e, 0x21, 0 - .dw 0xc040, 0xc92e, 0xc07f, 0xc92e, 0x21, 0 - .dw 0xc0c0, 0xc92e, 0xc0ff, 0xc92e, 0x21, 0 - .dw 0xc140, 0xc92e, 0xc17f, 0xc92e, 0x21, 0 - .dw 0xc1c0, 0xc92e, 0xc1ff, 0xc92e, 0x21, 0 - .dw 0xc240, 0xc92e, 0xc27f, 0xc92e, 0x21, 0 - .dw 0xc2c0, 0xc92e, 0xc2ff, 0xc92e, 0x21, 0 - .dw 0xc340, 0xc92e, 0xc37f, 0xc92e, 0x21, 0 - .dw 0xc3c0, 0xc92e, 0xc3ff, 0xc92e, 0x21, 0 - .dw 0xc440, 0xc92e, 0xc47f, 0xc92e, 0x21, 0 - .dw 0xc4c0, 0xc92e, 0xc4ff, 0xc92e, 0x21, 0 - .dw 0xc540, 0xc92e, 0xc57f, 0xc92e, 0x21, 0 - .dw 0xc5c0, 0xc92e, 0xc5ff, 0xc92e, 0x21, 0 - .dw 0xc640, 0xc92e, 0xc67f, 0xc92e, 0x21, 0 - .dw 0xc6c0, 0xc92e, 0xc6ff, 0xc92e, 0x21, 0 - .dw 0xc740, 0xc92e, 0xc77f, 0xc92e, 0x21, 0 - .dw 0xc7c0, 0xc92e, 0xc7ff, 0xc92e, 0x21, 0 - .dw 0xc840, 0xc92e, 0xc87f, 0xc92e, 0x21, 0 - .dw 0xc8c0, 0xc92e, 0xc8ff, 0xc92e, 0x21, 0 - .dw 0xc940, 0xc92e, 0xc97f, 0xc92e, 0x21, 0 - .dw 0xc9c0, 0xc92e, 0xc9ff, 0xc92e, 0x21, 0 - .dw 0xca40, 0xc92e, 0xca7f, 0xc92e, 0x21, 0 - .dw 0xcac0, 0xc92e, 0xcaff, 0xc92e, 0x21, 0 - .dw 0xcb40, 0xc92e, 0xcb7f, 0xc92e, 0x21, 0 - .dw 0xcbc0, 0xc92e, 0xcbff, 0xc92e, 0x21, 0 - .dw 0xcc40, 0xc92e, 0xcc7f, 0xc92e, 0x21, 0 - .dw 0xccc0, 0xc92e, 0xccff, 0xc92e, 0x21, 0 - .dw 0xcd40, 0xc92e, 0xcd7f, 0xc92e, 0x21, 0 - .dw 0xcdc0, 0xc92e, 0xcdff, 0xc92e, 0x21, 0 - .dw 0xce40, 0xc92e, 0xce7f, 0xc92e, 0x21, 0 - .dw 0xcec0, 0xc92e, 0xceff, 0xc92e, 0x21, 0 - .dw 0xcf40, 0xc92e, 0xcf7f, 0xc92e, 0x21, 0 - .dw 0xcfc0, 0xc92e, 0xcfff, 0xc92e, 0x21, 0 - .dw 0xd040, 0xc92e, 0xd07f, 0xc92e, 0x21, 0 - .dw 0xd0c0, 0xc92e, 0xd0ff, 0xc92e, 0x21, 0 - .dw 0xd140, 0xc92e, 0xd17f, 0xc92e, 0x21, 0 - .dw 0xd1c0, 0xc92e, 0xd1ff, 0xc92e, 0x21, 0 - .dw 0xd240, 0xc92e, 0xd27f, 0xc92e, 0x21, 0 - .dw 0xd2c0, 0xc92e, 0xd2ff, 0xc92e, 0x21, 0 - .dw 0xd340, 0xc92e, 0xd37f, 0xc92e, 0x21, 0 - .dw 0xd3c0, 0xc92e, 0xd3ff, 0xc92e, 0x21, 0 - .dw 0xd440, 0xc92e, 0xd47f, 0xc92e, 0x21, 0 - .dw 0xd4c0, 0xc92e, 0xd4ff, 0xc92e, 0x21, 0 - .dw 0xd540, 0xc92e, 0xd57f, 0xc92e, 0x21, 0 - .dw 0xd5c0, 0xc92e, 0xd5ff, 0xc92e, 0x21, 0 - .dw 0xd640, 0xc92e, 0xd67f, 0xc92e, 0x21, 0 - .dw 0xd6c0, 0xc92e, 0xd6ff, 0xc92e, 0x21, 0 - .dw 0xd740, 0xc92e, 0xd77f, 0xc92e, 0x21, 0 - .dw 0xd7c0, 0xc92e, 0xd7ff, 0xc92e, 0x21, 0 - .dw 0xd840, 0xc92e, 0xd87f, 0xc92e, 0x21, 0 - .dw 0xd8c0, 0xc92e, 0xd8ff, 0xc92e, 0x21, 0 - .dw 0xd940, 0xc92e, 0xd97f, 0xc92e, 0x21, 0 - .dw 0xd9c0, 0xc92e, 0xdfff, 0xc92e, 0x21, 0 - .dw 0xe040, 0xc92e, 0xe07f, 0xc92e, 0x21, 0 - .dw 0xe0c0, 0xc92e, 0xe0ff, 0xc92e, 0x21, 0 - .dw 0xe140, 0xc92e, 0xe17f, 0xc92e, 0x21, 0 - .dw 0xe1c0, 0xc92e, 0xe1ff, 0xc92e, 0x21, 0 - .dw 0xe240, 0xc92e, 0xe27f, 0xc92e, 0x21, 0 - .dw 0xe2c0, 0xc92e, 0xe2ff, 0xc92e, 0x21, 0 - .dw 0xe340, 0xc92e, 0xe37f, 0xc92e, 0x21, 0 - .dw 0xe3c0, 0xc92e, 0xe3ff, 0xc92e, 0x21, 0 - .dw 0xe440, 0xc92e, 0xe47f, 0xc92e, 0x21, 0 - .dw 0xe4c0, 0xc92e, 0xe4ff, 0xc92e, 0x21, 0 - .dw 0xe540, 0xc92e, 0xe57f, 0xc92e, 0x21, 0 - .dw 0xe5c0, 0xc92e, 0xe5ff, 0xc92e, 0x21, 0 - .dw 0xe640, 0xc92e, 0xe67f, 0xc92e, 0x21, 0 - .dw 0xe6c0, 0xc92e, 0xe6ff, 0xc92e, 0x21, 0 - .dw 0xe740, 0xc92e, 0xe77f, 0xc92e, 0x21, 0 - .dw 0xe7c0, 0xc92e, 0xe7ff, 0xc92e, 0x21, 0 - .dw 0xe840, 0xc92e, 0xe87f, 0xc92e, 0x21, 0 - .dw 0xe8c0, 0xc92e, 0xe8ff, 0xc92e, 0x21, 0 - .dw 0xe940, 0xc92e, 0xe97f, 0xc92e, 0x21, 0 - .dw 0xe9c0, 0xc92e, 0xe9ff, 0xc92e, 0x21, 0 - .dw 0xea40, 0xc92e, 0xea7f, 0xc92e, 0x21, 0 - .dw 0xeac0, 0xc92e, 0xeaff, 0xc92e, 0x21, 0 - .dw 0xeb40, 0xc92e, 0xeb7f, 0xc92e, 0x21, 0 - .dw 0xebc0, 0xc92e, 0xebff, 0xc92e, 0x21, 0 - .dw 0xec40, 0xc92e, 0xec7f, 0xc92e, 0x21, 0 - .dw 0xecc0, 0xc92e, 0xecff, 0xc92e, 0x21, 0 - .dw 0xed40, 0xc92e, 0xed7f, 0xc92e, 0x21, 0 - .dw 0xedc0, 0xc92e, 0xedff, 0xc92e, 0x21, 0 - .dw 0xee40, 0xc92e, 0xee7f, 0xc92e, 0x21, 0 - .dw 0xeec0, 0xc92e, 0xeeff, 0xc92e, 0x21, 0 - .dw 0xef40, 0xc92e, 0xef7f, 0xc92e, 0x21, 0 - .dw 0xefc0, 0xc92e, 0xefff, 0xc92e, 0x21, 0 - .dw 0xf040, 0xc92e, 0xf07f, 0xc92e, 0x21, 0 - .dw 0xf0c0, 0xc92e, 0xf0ff, 0xc92e, 0x21, 0 - .dw 0xf140, 0xc92e, 0xf17f, 0xc92e, 0x21, 0 - .dw 0xf1c0, 0xc92e, 0xf1ff, 0xc92e, 0x21, 0 - .dw 0xf240, 0xc92e, 0xf27f, 0xc92e, 0x21, 0 - .dw 0xf2c0, 0xc92e, 0xf2ff, 0xc92e, 0x21, 0 - .dw 0xf340, 0xc92e, 0xf37f, 0xc92e, 0x21, 0 - .dw 0xf3c0, 0xc92e, 0xf3ff, 0xc92e, 0x21, 0 - .dw 0xf440, 0xc92e, 0xf47f, 0xc92e, 0x21, 0 - .dw 0xf4c0, 0xc92e, 0xf4ff, 0xc92e, 0x21, 0 - .dw 0xf540, 0xc92e, 0xf57f, 0xc92e, 0x21, 0 - .dw 0xf5c0, 0xc92e, 0xf5ff, 0xc92e, 0x21, 0 - .dw 0xf640, 0xc92e, 0xf67f, 0xc92e, 0x21, 0 - .dw 0xf6c0, 0xc92e, 0xf6ff, 0xc92e, 0x21, 0 - .dw 0xf740, 0xc92e, 0xf77f, 0xc92e, 0x21, 0 - .dw 0xf7c0, 0xc92e, 0xf7ff, 0xc92e, 0x21, 0 - .dw 0xf840, 0xc92e, 0xf87f, 0xc92e, 0x21, 0 - .dw 0xf8c0, 0xc92e, 0xf8ff, 0xc92e, 0x21, 0 - .dw 0xf940, 0xc92e, 0xf97f, 0xc92e, 0x21, 0 - .dw 0xf9c0, 0xc92e, 0xffff, 0xc92e, 0x21, 0 - .dw 0x0040, 0xc92f, 0x007f, 0xc92f, 0x21, 0 - .dw 0x00c0, 0xc92f, 0x00ff, 0xc92f, 0x21, 0 - .dw 0x0140, 0xc92f, 0x017f, 0xc92f, 0x21, 0 - .dw 0x01c0, 0xc92f, 0x01ff, 0xc92f, 0x21, 0 - .dw 0x0240, 0xc92f, 0x027f, 0xc92f, 0x21, 0 - .dw 0x02c0, 0xc92f, 0x02ff, 0xc92f, 0x21, 0 - .dw 0x0340, 0xc92f, 0x037f, 0xc92f, 0x21, 0 - .dw 0x03c0, 0xc92f, 0x03ff, 0xc92f, 0x21, 0 - .dw 0x0440, 0xc92f, 0x047f, 0xc92f, 0x21, 0 - .dw 0x04c0, 0xc92f, 0x04ff, 0xc92f, 0x21, 0 - .dw 0x0540, 0xc92f, 0x057f, 0xc92f, 0x21, 0 - .dw 0x05c0, 0xc92f, 0x05ff, 0xc92f, 0x21, 0 - .dw 0x0640, 0xc92f, 0x067f, 0xc92f, 0x21, 0 - .dw 0x06c0, 0xc92f, 0x06ff, 0xc92f, 0x21, 0 - .dw 0x0740, 0xc92f, 0x077f, 0xc92f, 0x21, 0 - .dw 0x07c0, 0xc92f, 0x07ff, 0xc92f, 0x21, 0 - .dw 0x0840, 0xc92f, 0x087f, 0xc92f, 0x21, 0 - .dw 0x08c0, 0xc92f, 0x08ff, 0xc92f, 0x21, 0 - .dw 0x0940, 0xc92f, 0x097f, 0xc92f, 0x21, 0 - .dw 0x09c0, 0xc92f, 0x09ff, 0xc92f, 0x21, 0 - .dw 0x0a40, 0xc92f, 0x0a7f, 0xc92f, 0x21, 0 - .dw 0x0ac0, 0xc92f, 0x0aff, 0xc92f, 0x21, 0 - .dw 0x0b40, 0xc92f, 0x0b7f, 0xc92f, 0x21, 0 - .dw 0x0bc0, 0xc92f, 0x0bff, 0xc92f, 0x21, 0 - .dw 0x0c40, 0xc92f, 0x0c7f, 0xc92f, 0x21, 0 - .dw 0x0cc0, 0xc92f, 0x0cff, 0xc92f, 0x21, 0 - .dw 0x0d40, 0xc92f, 0x0d7f, 0xc92f, 0x21, 0 - .dw 0x0dc0, 0xc92f, 0x0dff, 0xc92f, 0x21, 0 - .dw 0x0e40, 0xc92f, 0x0e7f, 0xc92f, 0x21, 0 - .dw 0x0ec0, 0xc92f, 0x0eff, 0xc92f, 0x21, 0 - .dw 0x0f40, 0xc92f, 0x0f7f, 0xc92f, 0x21, 0 - .dw 0x0fc0, 0xc92f, 0x0fff, 0xc92f, 0x21, 0 - .dw 0x1040, 0xc92f, 0x107f, 0xc92f, 0x21, 0 - .dw 0x10c0, 0xc92f, 0x10ff, 0xc92f, 0x21, 0 - .dw 0x1140, 0xc92f, 0x117f, 0xc92f, 0x21, 0 - .dw 0x11c0, 0xc92f, 0x11ff, 0xc92f, 0x21, 0 - .dw 0x1240, 0xc92f, 0x127f, 0xc92f, 0x21, 0 - .dw 0x12c0, 0xc92f, 0x12ff, 0xc92f, 0x21, 0 - .dw 0x1340, 0xc92f, 0x137f, 0xc92f, 0x21, 0 - .dw 0x13c0, 0xc92f, 0x13ff, 0xc92f, 0x21, 0 - .dw 0x1440, 0xc92f, 0x147f, 0xc92f, 0x21, 0 - .dw 0x14c0, 0xc92f, 0x14ff, 0xc92f, 0x21, 0 - .dw 0x1540, 0xc92f, 0x157f, 0xc92f, 0x21, 0 - .dw 0x15c0, 0xc92f, 0x15ff, 0xc92f, 0x21, 0 - .dw 0x1640, 0xc92f, 0x167f, 0xc92f, 0x21, 0 - .dw 0x16c0, 0xc92f, 0x16ff, 0xc92f, 0x21, 0 - .dw 0x1740, 0xc92f, 0x177f, 0xc92f, 0x21, 0 - .dw 0x17c0, 0xc92f, 0x17ff, 0xc92f, 0x21, 0 - .dw 0x1840, 0xc92f, 0x187f, 0xc92f, 0x21, 0 - .dw 0x18c0, 0xc92f, 0x18ff, 0xc92f, 0x21, 0 - .dw 0x1940, 0xc92f, 0x197f, 0xc92f, 0x21, 0 - .dw 0x19c0, 0xc92f, 0x1fff, 0xc92f, 0x21, 0 - .dw 0x2040, 0xc92f, 0x207f, 0xc92f, 0x21, 0 - .dw 0x20c0, 0xc92f, 0x20ff, 0xc92f, 0x21, 0 - .dw 0x2140, 0xc92f, 0x217f, 0xc92f, 0x21, 0 - .dw 0x21c0, 0xc92f, 0x21ff, 0xc92f, 0x21, 0 - .dw 0x2240, 0xc92f, 0x227f, 0xc92f, 0x21, 0 - .dw 0x22c0, 0xc92f, 0x22ff, 0xc92f, 0x21, 0 - .dw 0x2340, 0xc92f, 0x237f, 0xc92f, 0x21, 0 - .dw 0x23c0, 0xc92f, 0x23ff, 0xc92f, 0x21, 0 - .dw 0x2440, 0xc92f, 0x247f, 0xc92f, 0x21, 0 - .dw 0x24c0, 0xc92f, 0x24ff, 0xc92f, 0x21, 0 - .dw 0x2540, 0xc92f, 0x257f, 0xc92f, 0x21, 0 - .dw 0x25c0, 0xc92f, 0x25ff, 0xc92f, 0x21, 0 - .dw 0x2640, 0xc92f, 0x267f, 0xc92f, 0x21, 0 - .dw 0x26c0, 0xc92f, 0x26ff, 0xc92f, 0x21, 0 - .dw 0x2740, 0xc92f, 0x277f, 0xc92f, 0x21, 0 - .dw 0x27c0, 0xc92f, 0x27ff, 0xc92f, 0x21, 0 - .dw 0x2840, 0xc92f, 0x287f, 0xc92f, 0x21, 0 - .dw 0x28c0, 0xc92f, 0x28ff, 0xc92f, 0x21, 0 - .dw 0x2940, 0xc92f, 0x297f, 0xc92f, 0x21, 0 - .dw 0x29c0, 0xc92f, 0x29ff, 0xc92f, 0x21, 0 - .dw 0x2a40, 0xc92f, 0x2a7f, 0xc92f, 0x21, 0 - .dw 0x2ac0, 0xc92f, 0x2aff, 0xc92f, 0x21, 0 - .dw 0x2b40, 0xc92f, 0x2b7f, 0xc92f, 0x21, 0 - .dw 0x2bc0, 0xc92f, 0x2bff, 0xc92f, 0x21, 0 - .dw 0x2c40, 0xc92f, 0x2c7f, 0xc92f, 0x21, 0 - .dw 0x2cc0, 0xc92f, 0x2cff, 0xc92f, 0x21, 0 - .dw 0x2d40, 0xc92f, 0x2d7f, 0xc92f, 0x21, 0 - .dw 0x2dc0, 0xc92f, 0x2dff, 0xc92f, 0x21, 0 - .dw 0x2e40, 0xc92f, 0x2e7f, 0xc92f, 0x21, 0 - .dw 0x2ec0, 0xc92f, 0x2eff, 0xc92f, 0x21, 0 - .dw 0x2f40, 0xc92f, 0x2f7f, 0xc92f, 0x21, 0 - .dw 0x2fc0, 0xc92f, 0x2fff, 0xc92f, 0x21, 0 - .dw 0x3040, 0xc92f, 0x307f, 0xc92f, 0x21, 0 - .dw 0x30c0, 0xc92f, 0x30ff, 0xc92f, 0x21, 0 - .dw 0x3140, 0xc92f, 0x317f, 0xc92f, 0x21, 0 - .dw 0x31c0, 0xc92f, 0x31ff, 0xc92f, 0x21, 0 - .dw 0x3240, 0xc92f, 0x327f, 0xc92f, 0x21, 0 - .dw 0x32c0, 0xc92f, 0x32ff, 0xc92f, 0x21, 0 - .dw 0x3340, 0xc92f, 0x337f, 0xc92f, 0x21, 0 - .dw 0x33c0, 0xc92f, 0x33ff, 0xc92f, 0x21, 0 - .dw 0x3440, 0xc92f, 0x347f, 0xc92f, 0x21, 0 - .dw 0x34c0, 0xc92f, 0x34ff, 0xc92f, 0x21, 0 - .dw 0x3540, 0xc92f, 0x357f, 0xc92f, 0x21, 0 - .dw 0x35c0, 0xc92f, 0x35ff, 0xc92f, 0x21, 0 - .dw 0x3640, 0xc92f, 0x367f, 0xc92f, 0x21, 0 - .dw 0x36c0, 0xc92f, 0x36ff, 0xc92f, 0x21, 0 - .dw 0x3740, 0xc92f, 0x377f, 0xc92f, 0x21, 0 - .dw 0x37c0, 0xc92f, 0x37ff, 0xc92f, 0x21, 0 - .dw 0x3840, 0xc92f, 0x387f, 0xc92f, 0x21, 0 - .dw 0x38c0, 0xc92f, 0x38ff, 0xc92f, 0x21, 0 - .dw 0x3940, 0xc92f, 0x397f, 0xc92f, 0x21, 0 - .dw 0x39c0, 0xc92f, 0x1fff, 0xc930, 0x21, 0 - .dw 0x3a00, 0xc930, 0x5fff, 0xc930, 0x21, 0 - .dw 0x7a00, 0xc930, 0x9fff, 0xc930, 0x21, 0 - .dw 0xba00, 0xc930, 0xdfff, 0xc930, 0x21, 0 - .dw 0xfa00, 0xc930, 0x1fff, 0xc931, 0x21, 0 - .dw 0x3a00, 0xc931, 0x5fff, 0xc931, 0x21, 0 - .dw 0x7a00, 0xc931, 0x9fff, 0xc931, 0x21, 0 - .dw 0xba00, 0xc931, 0xdfff, 0xc931, 0x21, 0 - .dw 0xfa00, 0xc931, 0x1fff, 0xc932, 0x21, 0 - .dw 0x3a00, 0xc932, 0x5fff, 0xc932, 0x21, 0 - .dw 0x7a00, 0xc932, 0x9fff, 0xc932, 0x21, 0 - .dw 0xba00, 0xc932, 0xdfff, 0xc932, 0x21, 0 - .dw 0xfa00, 0xc932, 0xffff, 0xc933, 0x21, 0 - .dw 0x1a00, 0xc934, 0x1fff, 0xc934, 0x21, 0 - .dw 0x3a00, 0xc934, 0x3fff, 0xc934, 0x21, 0 - .dw 0x5a00, 0xc934, 0x5fff, 0xc934, 0x21, 0 - .dw 0x7a00, 0xc934, 0x7fff, 0xc934, 0x21, 0 - .dw 0x9a00, 0xc934, 0x9fff, 0xc934, 0x21, 0 - .dw 0xba00, 0xc934, 0xbfff, 0xc934, 0x21, 0 - .dw 0xda00, 0xc934, 0xdfff, 0xc934, 0x21, 0 - .dw 0xfa00, 0xc934, 0xffff, 0xc934, 0x21, 0 - .dw 0x1a00, 0xc935, 0x1fff, 0xc935, 0x21, 0 - .dw 0x3a00, 0xc935, 0x3fff, 0xc935, 0x21, 0 - .dw 0x5a00, 0xc935, 0x5fff, 0xc935, 0x21, 0 - .dw 0x7a00, 0xc935, 0x7fff, 0xc935, 0x21, 0 - .dw 0x9a00, 0xc935, 0x9fff, 0xc935, 0x21, 0 - .dw 0xba00, 0xc935, 0xbfff, 0xc935, 0x21, 0 - .dw 0xda00, 0xc935, 0xdfff, 0xc935, 0x21, 0 - .dw 0xfa00, 0xc935, 0xffff, 0xc935, 0x21, 0 - .dw 0x1a00, 0xc936, 0x1fff, 0xc936, 0x21, 0 - .dw 0x3a00, 0xc936, 0x3fff, 0xc936, 0x21, 0 - .dw 0x5a00, 0xc936, 0x5fff, 0xc936, 0x21, 0 - .dw 0x7a00, 0xc936, 0x7fff, 0xc936, 0x21, 0 - .dw 0x9a00, 0xc936, 0x9fff, 0xc936, 0x21, 0 - .dw 0xba00, 0xc936, 0xbfff, 0xc936, 0x21, 0 - .dw 0xda00, 0xc936, 0xdfff, 0xc936, 0x21, 0 - .dw 0xfa00, 0xc936, 0xffff, 0xc936, 0x21, 0 - .dw 0x1a00, 0xc937, 0x1fff, 0xc937, 0x21, 0 - .dw 0x3a00, 0xc937, 0x1fff, 0xc938, 0x21, 0 - .dw 0x2040, 0xc938, 0x207f, 0xc938, 0x21, 0 - .dw 0x20c0, 0xc938, 0x20ff, 0xc938, 0x21, 0 - .dw 0x2140, 0xc938, 0x217f, 0xc938, 0x21, 0 - .dw 0x21c0, 0xc938, 0x21ff, 0xc938, 0x21, 0 - .dw 0x2240, 0xc938, 0x227f, 0xc938, 0x21, 0 - .dw 0x22c0, 0xc938, 0x22ff, 0xc938, 0x21, 0 - .dw 0x2340, 0xc938, 0x237f, 0xc938, 0x21, 0 - .dw 0x23c0, 0xc938, 0x23ff, 0xc938, 0x21, 0 - .dw 0x2440, 0xc938, 0x247f, 0xc938, 0x21, 0 - .dw 0x24c0, 0xc938, 0x24ff, 0xc938, 0x21, 0 - .dw 0x2540, 0xc938, 0x257f, 0xc938, 0x21, 0 - .dw 0x25c0, 0xc938, 0x25ff, 0xc938, 0x21, 0 - .dw 0x2640, 0xc938, 0x267f, 0xc938, 0x21, 0 - .dw 0x26c0, 0xc938, 0x26ff, 0xc938, 0x21, 0 - .dw 0x2740, 0xc938, 0x277f, 0xc938, 0x21, 0 - .dw 0x27c0, 0xc938, 0x27ff, 0xc938, 0x21, 0 - .dw 0x2840, 0xc938, 0x287f, 0xc938, 0x21, 0 - .dw 0x28c0, 0xc938, 0x28ff, 0xc938, 0x21, 0 - .dw 0x2940, 0xc938, 0x297f, 0xc938, 0x21, 0 - .dw 0x29c0, 0xc938, 0x29ff, 0xc938, 0x21, 0 - .dw 0x2a40, 0xc938, 0x2a7f, 0xc938, 0x21, 0 - .dw 0x2ac0, 0xc938, 0x2aff, 0xc938, 0x21, 0 - .dw 0x2b40, 0xc938, 0x2b7f, 0xc938, 0x21, 0 - .dw 0x2bc0, 0xc938, 0x2bff, 0xc938, 0x21, 0 - .dw 0x2c40, 0xc938, 0x2c7f, 0xc938, 0x21, 0 - .dw 0x2cc0, 0xc938, 0x2cff, 0xc938, 0x21, 0 - .dw 0x2d40, 0xc938, 0x2d7f, 0xc938, 0x21, 0 - .dw 0x2dc0, 0xc938, 0x2dff, 0xc938, 0x21, 0 - .dw 0x2e40, 0xc938, 0x2e7f, 0xc938, 0x21, 0 - .dw 0x2ec0, 0xc938, 0x2eff, 0xc938, 0x21, 0 - .dw 0x2f40, 0xc938, 0x2f7f, 0xc938, 0x21, 0 - .dw 0x2fc0, 0xc938, 0x2fff, 0xc938, 0x21, 0 - .dw 0x3040, 0xc938, 0x307f, 0xc938, 0x21, 0 - .dw 0x30c0, 0xc938, 0x30ff, 0xc938, 0x21, 0 - .dw 0x3140, 0xc938, 0x317f, 0xc938, 0x21, 0 - .dw 0x31c0, 0xc938, 0x31ff, 0xc938, 0x21, 0 - .dw 0x3240, 0xc938, 0x327f, 0xc938, 0x21, 0 - .dw 0x32c0, 0xc938, 0x32ff, 0xc938, 0x21, 0 - .dw 0x3340, 0xc938, 0x337f, 0xc938, 0x21, 0 - .dw 0x33c0, 0xc938, 0x33ff, 0xc938, 0x21, 0 - .dw 0x3440, 0xc938, 0x347f, 0xc938, 0x21, 0 - .dw 0x34c0, 0xc938, 0x34ff, 0xc938, 0x21, 0 - .dw 0x3540, 0xc938, 0x357f, 0xc938, 0x21, 0 - .dw 0x35c0, 0xc938, 0x35ff, 0xc938, 0x21, 0 - .dw 0x3640, 0xc938, 0x367f, 0xc938, 0x21, 0 - .dw 0x36c0, 0xc938, 0x36ff, 0xc938, 0x21, 0 - .dw 0x3740, 0xc938, 0x377f, 0xc938, 0x21, 0 - .dw 0x37c0, 0xc938, 0x37ff, 0xc938, 0x21, 0 - .dw 0x3840, 0xc938, 0x387f, 0xc938, 0x21, 0 - .dw 0x38c0, 0xc938, 0x38ff, 0xc938, 0x21, 0 - .dw 0x3940, 0xc938, 0x397f, 0xc938, 0x21, 0 - .dw 0x39c0, 0xc938, 0x5fff, 0xc938, 0x21, 0 - .dw 0x6040, 0xc938, 0x607f, 0xc938, 0x21, 0 - .dw 0x60c0, 0xc938, 0x60ff, 0xc938, 0x21, 0 - .dw 0x6140, 0xc938, 0x617f, 0xc938, 0x21, 0 - .dw 0x61c0, 0xc938, 0x61ff, 0xc938, 0x21, 0 - .dw 0x6240, 0xc938, 0x627f, 0xc938, 0x21, 0 - .dw 0x62c0, 0xc938, 0x62ff, 0xc938, 0x21, 0 - .dw 0x6340, 0xc938, 0x637f, 0xc938, 0x21, 0 - .dw 0x63c0, 0xc938, 0x63ff, 0xc938, 0x21, 0 - .dw 0x6440, 0xc938, 0x647f, 0xc938, 0x21, 0 - .dw 0x64c0, 0xc938, 0x64ff, 0xc938, 0x21, 0 - .dw 0x6540, 0xc938, 0x657f, 0xc938, 0x21, 0 - .dw 0x65c0, 0xc938, 0x65ff, 0xc938, 0x21, 0 - .dw 0x6640, 0xc938, 0x667f, 0xc938, 0x21, 0 - .dw 0x66c0, 0xc938, 0x66ff, 0xc938, 0x21, 0 - .dw 0x6740, 0xc938, 0x677f, 0xc938, 0x21, 0 - .dw 0x67c0, 0xc938, 0x67ff, 0xc938, 0x21, 0 - .dw 0x6840, 0xc938, 0x687f, 0xc938, 0x21, 0 - .dw 0x68c0, 0xc938, 0x68ff, 0xc938, 0x21, 0 - .dw 0x6940, 0xc938, 0x697f, 0xc938, 0x21, 0 - .dw 0x69c0, 0xc938, 0x69ff, 0xc938, 0x21, 0 - .dw 0x6a40, 0xc938, 0x6a7f, 0xc938, 0x21, 0 - .dw 0x6ac0, 0xc938, 0x6aff, 0xc938, 0x21, 0 - .dw 0x6b40, 0xc938, 0x6b7f, 0xc938, 0x21, 0 - .dw 0x6bc0, 0xc938, 0x6bff, 0xc938, 0x21, 0 - .dw 0x6c40, 0xc938, 0x6c7f, 0xc938, 0x21, 0 - .dw 0x6cc0, 0xc938, 0x6cff, 0xc938, 0x21, 0 - .dw 0x6d40, 0xc938, 0x6d7f, 0xc938, 0x21, 0 - .dw 0x6dc0, 0xc938, 0x6dff, 0xc938, 0x21, 0 - .dw 0x6e40, 0xc938, 0x6e7f, 0xc938, 0x21, 0 - .dw 0x6ec0, 0xc938, 0x6eff, 0xc938, 0x21, 0 - .dw 0x6f40, 0xc938, 0x6f7f, 0xc938, 0x21, 0 - .dw 0x6fc0, 0xc938, 0x6fff, 0xc938, 0x21, 0 - .dw 0x7040, 0xc938, 0x707f, 0xc938, 0x21, 0 - .dw 0x70c0, 0xc938, 0x70ff, 0xc938, 0x21, 0 - .dw 0x7140, 0xc938, 0x717f, 0xc938, 0x21, 0 - .dw 0x71c0, 0xc938, 0x71ff, 0xc938, 0x21, 0 - .dw 0x7240, 0xc938, 0x727f, 0xc938, 0x21, 0 - .dw 0x72c0, 0xc938, 0x72ff, 0xc938, 0x21, 0 - .dw 0x7340, 0xc938, 0x737f, 0xc938, 0x21, 0 - .dw 0x73c0, 0xc938, 0x73ff, 0xc938, 0x21, 0 - .dw 0x7440, 0xc938, 0x747f, 0xc938, 0x21, 0 - .dw 0x74c0, 0xc938, 0x74ff, 0xc938, 0x21, 0 - .dw 0x7540, 0xc938, 0x757f, 0xc938, 0x21, 0 - .dw 0x75c0, 0xc938, 0x75ff, 0xc938, 0x21, 0 - .dw 0x7640, 0xc938, 0x767f, 0xc938, 0x21, 0 - .dw 0x76c0, 0xc938, 0x76ff, 0xc938, 0x21, 0 - .dw 0x7740, 0xc938, 0x777f, 0xc938, 0x21, 0 - .dw 0x77c0, 0xc938, 0x77ff, 0xc938, 0x21, 0 - .dw 0x7840, 0xc938, 0x787f, 0xc938, 0x21, 0 - .dw 0x78c0, 0xc938, 0x78ff, 0xc938, 0x21, 0 - .dw 0x7940, 0xc938, 0x797f, 0xc938, 0x21, 0 - .dw 0x79c0, 0xc938, 0x9fff, 0xc938, 0x21, 0 - .dw 0xa040, 0xc938, 0xa07f, 0xc938, 0x21, 0 - .dw 0xa0c0, 0xc938, 0xa0ff, 0xc938, 0x21, 0 - .dw 0xa140, 0xc938, 0xa17f, 0xc938, 0x21, 0 - .dw 0xa1c0, 0xc938, 0xa1ff, 0xc938, 0x21, 0 - .dw 0xa240, 0xc938, 0xa27f, 0xc938, 0x21, 0 - .dw 0xa2c0, 0xc938, 0xa2ff, 0xc938, 0x21, 0 - .dw 0xa340, 0xc938, 0xa37f, 0xc938, 0x21, 0 - .dw 0xa3c0, 0xc938, 0xa3ff, 0xc938, 0x21, 0 - .dw 0xa440, 0xc938, 0xa47f, 0xc938, 0x21, 0 - .dw 0xa4c0, 0xc938, 0xa4ff, 0xc938, 0x21, 0 - .dw 0xa540, 0xc938, 0xa57f, 0xc938, 0x21, 0 - .dw 0xa5c0, 0xc938, 0xa5ff, 0xc938, 0x21, 0 - .dw 0xa640, 0xc938, 0xa67f, 0xc938, 0x21, 0 - .dw 0xa6c0, 0xc938, 0xa6ff, 0xc938, 0x21, 0 - .dw 0xa740, 0xc938, 0xa77f, 0xc938, 0x21, 0 - .dw 0xa7c0, 0xc938, 0xa7ff, 0xc938, 0x21, 0 - .dw 0xa840, 0xc938, 0xa87f, 0xc938, 0x21, 0 - .dw 0xa8c0, 0xc938, 0xa8ff, 0xc938, 0x21, 0 - .dw 0xa940, 0xc938, 0xa97f, 0xc938, 0x21, 0 - .dw 0xa9c0, 0xc938, 0xa9ff, 0xc938, 0x21, 0 - .dw 0xaa40, 0xc938, 0xaa7f, 0xc938, 0x21, 0 - .dw 0xaac0, 0xc938, 0xaaff, 0xc938, 0x21, 0 - .dw 0xab40, 0xc938, 0xab7f, 0xc938, 0x21, 0 - .dw 0xabc0, 0xc938, 0xabff, 0xc938, 0x21, 0 - .dw 0xac40, 0xc938, 0xac7f, 0xc938, 0x21, 0 - .dw 0xacc0, 0xc938, 0xacff, 0xc938, 0x21, 0 - .dw 0xad40, 0xc938, 0xad7f, 0xc938, 0x21, 0 - .dw 0xadc0, 0xc938, 0xadff, 0xc938, 0x21, 0 - .dw 0xae40, 0xc938, 0xae7f, 0xc938, 0x21, 0 - .dw 0xaec0, 0xc938, 0xaeff, 0xc938, 0x21, 0 - .dw 0xaf40, 0xc938, 0xaf7f, 0xc938, 0x21, 0 - .dw 0xafc0, 0xc938, 0xafff, 0xc938, 0x21, 0 - .dw 0xb040, 0xc938, 0xb07f, 0xc938, 0x21, 0 - .dw 0xb0c0, 0xc938, 0xb0ff, 0xc938, 0x21, 0 - .dw 0xb140, 0xc938, 0xb17f, 0xc938, 0x21, 0 - .dw 0xb1c0, 0xc938, 0xb1ff, 0xc938, 0x21, 0 - .dw 0xb240, 0xc938, 0xb27f, 0xc938, 0x21, 0 - .dw 0xb2c0, 0xc938, 0xb2ff, 0xc938, 0x21, 0 - .dw 0xb340, 0xc938, 0xb37f, 0xc938, 0x21, 0 - .dw 0xb3c0, 0xc938, 0xb3ff, 0xc938, 0x21, 0 - .dw 0xb440, 0xc938, 0xb47f, 0xc938, 0x21, 0 - .dw 0xb4c0, 0xc938, 0xb4ff, 0xc938, 0x21, 0 - .dw 0xb540, 0xc938, 0xb57f, 0xc938, 0x21, 0 - .dw 0xb5c0, 0xc938, 0xb5ff, 0xc938, 0x21, 0 - .dw 0xb640, 0xc938, 0xb67f, 0xc938, 0x21, 0 - .dw 0xb6c0, 0xc938, 0xb6ff, 0xc938, 0x21, 0 - .dw 0xb740, 0xc938, 0xb77f, 0xc938, 0x21, 0 - .dw 0xb7c0, 0xc938, 0xb7ff, 0xc938, 0x21, 0 - .dw 0xb840, 0xc938, 0xb87f, 0xc938, 0x21, 0 - .dw 0xb8c0, 0xc938, 0xb8ff, 0xc938, 0x21, 0 - .dw 0xb940, 0xc938, 0xb97f, 0xc938, 0x21, 0 - .dw 0xb9c0, 0xc938, 0xdfff, 0xc938, 0x21, 0 - .dw 0xe040, 0xc938, 0xe07f, 0xc938, 0x21, 0 - .dw 0xe0c0, 0xc938, 0xe0ff, 0xc938, 0x21, 0 - .dw 0xe140, 0xc938, 0xe17f, 0xc938, 0x21, 0 - .dw 0xe1c0, 0xc938, 0xe1ff, 0xc938, 0x21, 0 - .dw 0xe240, 0xc938, 0xe27f, 0xc938, 0x21, 0 - .dw 0xe2c0, 0xc938, 0xe2ff, 0xc938, 0x21, 0 - .dw 0xe340, 0xc938, 0xe37f, 0xc938, 0x21, 0 - .dw 0xe3c0, 0xc938, 0xe3ff, 0xc938, 0x21, 0 - .dw 0xe440, 0xc938, 0xe47f, 0xc938, 0x21, 0 - .dw 0xe4c0, 0xc938, 0xe4ff, 0xc938, 0x21, 0 - .dw 0xe540, 0xc938, 0xe57f, 0xc938, 0x21, 0 - .dw 0xe5c0, 0xc938, 0xe5ff, 0xc938, 0x21, 0 - .dw 0xe640, 0xc938, 0xe67f, 0xc938, 0x21, 0 - .dw 0xe6c0, 0xc938, 0xe6ff, 0xc938, 0x21, 0 - .dw 0xe740, 0xc938, 0xe77f, 0xc938, 0x21, 0 - .dw 0xe7c0, 0xc938, 0xe7ff, 0xc938, 0x21, 0 - .dw 0xe840, 0xc938, 0xe87f, 0xc938, 0x21, 0 - .dw 0xe8c0, 0xc938, 0xe8ff, 0xc938, 0x21, 0 - .dw 0xe940, 0xc938, 0xe97f, 0xc938, 0x21, 0 - .dw 0xe9c0, 0xc938, 0xe9ff, 0xc938, 0x21, 0 - .dw 0xea40, 0xc938, 0xea7f, 0xc938, 0x21, 0 - .dw 0xeac0, 0xc938, 0xeaff, 0xc938, 0x21, 0 - .dw 0xeb40, 0xc938, 0xeb7f, 0xc938, 0x21, 0 - .dw 0xebc0, 0xc938, 0xebff, 0xc938, 0x21, 0 - .dw 0xec40, 0xc938, 0xec7f, 0xc938, 0x21, 0 - .dw 0xecc0, 0xc938, 0xecff, 0xc938, 0x21, 0 - .dw 0xed40, 0xc938, 0xed7f, 0xc938, 0x21, 0 - .dw 0xedc0, 0xc938, 0xedff, 0xc938, 0x21, 0 - .dw 0xee40, 0xc938, 0xee7f, 0xc938, 0x21, 0 - .dw 0xeec0, 0xc938, 0xeeff, 0xc938, 0x21, 0 - .dw 0xef40, 0xc938, 0xef7f, 0xc938, 0x21, 0 - .dw 0xefc0, 0xc938, 0xefff, 0xc938, 0x21, 0 - .dw 0xf040, 0xc938, 0xf07f, 0xc938, 0x21, 0 - .dw 0xf0c0, 0xc938, 0xf0ff, 0xc938, 0x21, 0 - .dw 0xf140, 0xc938, 0xf17f, 0xc938, 0x21, 0 - .dw 0xf1c0, 0xc938, 0xf1ff, 0xc938, 0x21, 0 - .dw 0xf240, 0xc938, 0xf27f, 0xc938, 0x21, 0 - .dw 0xf2c0, 0xc938, 0xf2ff, 0xc938, 0x21, 0 - .dw 0xf340, 0xc938, 0xf37f, 0xc938, 0x21, 0 - .dw 0xf3c0, 0xc938, 0xf3ff, 0xc938, 0x21, 0 - .dw 0xf440, 0xc938, 0xf47f, 0xc938, 0x21, 0 - .dw 0xf4c0, 0xc938, 0xf4ff, 0xc938, 0x21, 0 - .dw 0xf540, 0xc938, 0xf57f, 0xc938, 0x21, 0 - .dw 0xf5c0, 0xc938, 0xf5ff, 0xc938, 0x21, 0 - .dw 0xf640, 0xc938, 0xf67f, 0xc938, 0x21, 0 - .dw 0xf6c0, 0xc938, 0xf6ff, 0xc938, 0x21, 0 - .dw 0xf740, 0xc938, 0xf77f, 0xc938, 0x21, 0 - .dw 0xf7c0, 0xc938, 0xf7ff, 0xc938, 0x21, 0 - .dw 0xf840, 0xc938, 0xf87f, 0xc938, 0x21, 0 - .dw 0xf8c0, 0xc938, 0xf8ff, 0xc938, 0x21, 0 - .dw 0xf940, 0xc938, 0xf97f, 0xc938, 0x21, 0 - .dw 0xf9c0, 0xc938, 0x1fff, 0xc939, 0x21, 0 - .dw 0x2040, 0xc939, 0x207f, 0xc939, 0x21, 0 - .dw 0x20c0, 0xc939, 0x20ff, 0xc939, 0x21, 0 - .dw 0x2140, 0xc939, 0x217f, 0xc939, 0x21, 0 - .dw 0x21c0, 0xc939, 0x21ff, 0xc939, 0x21, 0 - .dw 0x2240, 0xc939, 0x227f, 0xc939, 0x21, 0 - .dw 0x22c0, 0xc939, 0x22ff, 0xc939, 0x21, 0 - .dw 0x2340, 0xc939, 0x237f, 0xc939, 0x21, 0 - .dw 0x23c0, 0xc939, 0x23ff, 0xc939, 0x21, 0 - .dw 0x2440, 0xc939, 0x247f, 0xc939, 0x21, 0 - .dw 0x24c0, 0xc939, 0x24ff, 0xc939, 0x21, 0 - .dw 0x2540, 0xc939, 0x257f, 0xc939, 0x21, 0 - .dw 0x25c0, 0xc939, 0x25ff, 0xc939, 0x21, 0 - .dw 0x2640, 0xc939, 0x267f, 0xc939, 0x21, 0 - .dw 0x26c0, 0xc939, 0x26ff, 0xc939, 0x21, 0 - .dw 0x2740, 0xc939, 0x277f, 0xc939, 0x21, 0 - .dw 0x27c0, 0xc939, 0x27ff, 0xc939, 0x21, 0 - .dw 0x2840, 0xc939, 0x287f, 0xc939, 0x21, 0 - .dw 0x28c0, 0xc939, 0x28ff, 0xc939, 0x21, 0 - .dw 0x2940, 0xc939, 0x297f, 0xc939, 0x21, 0 - .dw 0x29c0, 0xc939, 0x29ff, 0xc939, 0x21, 0 - .dw 0x2a40, 0xc939, 0x2a7f, 0xc939, 0x21, 0 - .dw 0x2ac0, 0xc939, 0x2aff, 0xc939, 0x21, 0 - .dw 0x2b40, 0xc939, 0x2b7f, 0xc939, 0x21, 0 - .dw 0x2bc0, 0xc939, 0x2bff, 0xc939, 0x21, 0 - .dw 0x2c40, 0xc939, 0x2c7f, 0xc939, 0x21, 0 - .dw 0x2cc0, 0xc939, 0x2cff, 0xc939, 0x21, 0 - .dw 0x2d40, 0xc939, 0x2d7f, 0xc939, 0x21, 0 - .dw 0x2dc0, 0xc939, 0x2dff, 0xc939, 0x21, 0 - .dw 0x2e40, 0xc939, 0x2e7f, 0xc939, 0x21, 0 - .dw 0x2ec0, 0xc939, 0x2eff, 0xc939, 0x21, 0 - .dw 0x2f40, 0xc939, 0x2f7f, 0xc939, 0x21, 0 - .dw 0x2fc0, 0xc939, 0x2fff, 0xc939, 0x21, 0 - .dw 0x3040, 0xc939, 0x307f, 0xc939, 0x21, 0 - .dw 0x30c0, 0xc939, 0x30ff, 0xc939, 0x21, 0 - .dw 0x3140, 0xc939, 0x317f, 0xc939, 0x21, 0 - .dw 0x31c0, 0xc939, 0x31ff, 0xc939, 0x21, 0 - .dw 0x3240, 0xc939, 0x327f, 0xc939, 0x21, 0 - .dw 0x32c0, 0xc939, 0x32ff, 0xc939, 0x21, 0 - .dw 0x3340, 0xc939, 0x337f, 0xc939, 0x21, 0 - .dw 0x33c0, 0xc939, 0x33ff, 0xc939, 0x21, 0 - .dw 0x3440, 0xc939, 0x347f, 0xc939, 0x21, 0 - .dw 0x34c0, 0xc939, 0x34ff, 0xc939, 0x21, 0 - .dw 0x3540, 0xc939, 0x357f, 0xc939, 0x21, 0 - .dw 0x35c0, 0xc939, 0x35ff, 0xc939, 0x21, 0 - .dw 0x3640, 0xc939, 0x367f, 0xc939, 0x21, 0 - .dw 0x36c0, 0xc939, 0x36ff, 0xc939, 0x21, 0 - .dw 0x3740, 0xc939, 0x377f, 0xc939, 0x21, 0 - .dw 0x37c0, 0xc939, 0x37ff, 0xc939, 0x21, 0 - .dw 0x3840, 0xc939, 0x387f, 0xc939, 0x21, 0 - .dw 0x38c0, 0xc939, 0x38ff, 0xc939, 0x21, 0 - .dw 0x3940, 0xc939, 0x397f, 0xc939, 0x21, 0 - .dw 0x39c0, 0xc939, 0x5fff, 0xc939, 0x21, 0 - .dw 0x6040, 0xc939, 0x607f, 0xc939, 0x21, 0 - .dw 0x60c0, 0xc939, 0x60ff, 0xc939, 0x21, 0 - .dw 0x6140, 0xc939, 0x617f, 0xc939, 0x21, 0 - .dw 0x61c0, 0xc939, 0x61ff, 0xc939, 0x21, 0 - .dw 0x6240, 0xc939, 0x627f, 0xc939, 0x21, 0 - .dw 0x62c0, 0xc939, 0x62ff, 0xc939, 0x21, 0 - .dw 0x6340, 0xc939, 0x637f, 0xc939, 0x21, 0 - .dw 0x63c0, 0xc939, 0x63ff, 0xc939, 0x21, 0 - .dw 0x6440, 0xc939, 0x647f, 0xc939, 0x21, 0 - .dw 0x64c0, 0xc939, 0x64ff, 0xc939, 0x21, 0 - .dw 0x6540, 0xc939, 0x657f, 0xc939, 0x21, 0 - .dw 0x65c0, 0xc939, 0x65ff, 0xc939, 0x21, 0 - .dw 0x6640, 0xc939, 0x667f, 0xc939, 0x21, 0 - .dw 0x66c0, 0xc939, 0x66ff, 0xc939, 0x21, 0 - .dw 0x6740, 0xc939, 0x677f, 0xc939, 0x21, 0 - .dw 0x67c0, 0xc939, 0x67ff, 0xc939, 0x21, 0 - .dw 0x6840, 0xc939, 0x687f, 0xc939, 0x21, 0 - .dw 0x68c0, 0xc939, 0x68ff, 0xc939, 0x21, 0 - .dw 0x6940, 0xc939, 0x697f, 0xc939, 0x21, 0 - .dw 0x69c0, 0xc939, 0x69ff, 0xc939, 0x21, 0 - .dw 0x6a40, 0xc939, 0x6a7f, 0xc939, 0x21, 0 - .dw 0x6ac0, 0xc939, 0x6aff, 0xc939, 0x21, 0 - .dw 0x6b40, 0xc939, 0x6b7f, 0xc939, 0x21, 0 - .dw 0x6bc0, 0xc939, 0x6bff, 0xc939, 0x21, 0 - .dw 0x6c40, 0xc939, 0x6c7f, 0xc939, 0x21, 0 - .dw 0x6cc0, 0xc939, 0x6cff, 0xc939, 0x21, 0 - .dw 0x6d40, 0xc939, 0x6d7f, 0xc939, 0x21, 0 - .dw 0x6dc0, 0xc939, 0x6dff, 0xc939, 0x21, 0 - .dw 0x6e40, 0xc939, 0x6e7f, 0xc939, 0x21, 0 - .dw 0x6ec0, 0xc939, 0x6eff, 0xc939, 0x21, 0 - .dw 0x6f40, 0xc939, 0x6f7f, 0xc939, 0x21, 0 - .dw 0x6fc0, 0xc939, 0x6fff, 0xc939, 0x21, 0 - .dw 0x7040, 0xc939, 0x707f, 0xc939, 0x21, 0 - .dw 0x70c0, 0xc939, 0x70ff, 0xc939, 0x21, 0 - .dw 0x7140, 0xc939, 0x717f, 0xc939, 0x21, 0 - .dw 0x71c0, 0xc939, 0x71ff, 0xc939, 0x21, 0 - .dw 0x7240, 0xc939, 0x727f, 0xc939, 0x21, 0 - .dw 0x72c0, 0xc939, 0x72ff, 0xc939, 0x21, 0 - .dw 0x7340, 0xc939, 0x737f, 0xc939, 0x21, 0 - .dw 0x73c0, 0xc939, 0x73ff, 0xc939, 0x21, 0 - .dw 0x7440, 0xc939, 0x747f, 0xc939, 0x21, 0 - .dw 0x74c0, 0xc939, 0x74ff, 0xc939, 0x21, 0 - .dw 0x7540, 0xc939, 0x757f, 0xc939, 0x21, 0 - .dw 0x75c0, 0xc939, 0x75ff, 0xc939, 0x21, 0 - .dw 0x7640, 0xc939, 0x767f, 0xc939, 0x21, 0 - .dw 0x76c0, 0xc939, 0x76ff, 0xc939, 0x21, 0 - .dw 0x7740, 0xc939, 0x777f, 0xc939, 0x21, 0 - .dw 0x77c0, 0xc939, 0x77ff, 0xc939, 0x21, 0 - .dw 0x7840, 0xc939, 0x787f, 0xc939, 0x21, 0 - .dw 0x78c0, 0xc939, 0x78ff, 0xc939, 0x21, 0 - .dw 0x7940, 0xc939, 0x797f, 0xc939, 0x21, 0 - .dw 0x79c0, 0xc939, 0x9fff, 0xc939, 0x21, 0 - .dw 0xa040, 0xc939, 0xa07f, 0xc939, 0x21, 0 - .dw 0xa0c0, 0xc939, 0xa0ff, 0xc939, 0x21, 0 - .dw 0xa140, 0xc939, 0xa17f, 0xc939, 0x21, 0 - .dw 0xa1c0, 0xc939, 0xa1ff, 0xc939, 0x21, 0 - .dw 0xa240, 0xc939, 0xa27f, 0xc939, 0x21, 0 - .dw 0xa2c0, 0xc939, 0xa2ff, 0xc939, 0x21, 0 - .dw 0xa340, 0xc939, 0xa37f, 0xc939, 0x21, 0 - .dw 0xa3c0, 0xc939, 0xa3ff, 0xc939, 0x21, 0 - .dw 0xa440, 0xc939, 0xa47f, 0xc939, 0x21, 0 - .dw 0xa4c0, 0xc939, 0xa4ff, 0xc939, 0x21, 0 - .dw 0xa540, 0xc939, 0xa57f, 0xc939, 0x21, 0 - .dw 0xa5c0, 0xc939, 0xa5ff, 0xc939, 0x21, 0 - .dw 0xa640, 0xc939, 0xa67f, 0xc939, 0x21, 0 - .dw 0xa6c0, 0xc939, 0xa6ff, 0xc939, 0x21, 0 - .dw 0xa740, 0xc939, 0xa77f, 0xc939, 0x21, 0 - .dw 0xa7c0, 0xc939, 0xa7ff, 0xc939, 0x21, 0 - .dw 0xa840, 0xc939, 0xa87f, 0xc939, 0x21, 0 - .dw 0xa8c0, 0xc939, 0xa8ff, 0xc939, 0x21, 0 - .dw 0xa940, 0xc939, 0xa97f, 0xc939, 0x21, 0 - .dw 0xa9c0, 0xc939, 0xa9ff, 0xc939, 0x21, 0 - .dw 0xaa40, 0xc939, 0xaa7f, 0xc939, 0x21, 0 - .dw 0xaac0, 0xc939, 0xaaff, 0xc939, 0x21, 0 - .dw 0xab40, 0xc939, 0xab7f, 0xc939, 0x21, 0 - .dw 0xabc0, 0xc939, 0xabff, 0xc939, 0x21, 0 - .dw 0xac40, 0xc939, 0xac7f, 0xc939, 0x21, 0 - .dw 0xacc0, 0xc939, 0xacff, 0xc939, 0x21, 0 - .dw 0xad40, 0xc939, 0xad7f, 0xc939, 0x21, 0 - .dw 0xadc0, 0xc939, 0xadff, 0xc939, 0x21, 0 - .dw 0xae40, 0xc939, 0xae7f, 0xc939, 0x21, 0 - .dw 0xaec0, 0xc939, 0xaeff, 0xc939, 0x21, 0 - .dw 0xaf40, 0xc939, 0xaf7f, 0xc939, 0x21, 0 - .dw 0xafc0, 0xc939, 0xafff, 0xc939, 0x21, 0 - .dw 0xb040, 0xc939, 0xb07f, 0xc939, 0x21, 0 - .dw 0xb0c0, 0xc939, 0xb0ff, 0xc939, 0x21, 0 - .dw 0xb140, 0xc939, 0xb17f, 0xc939, 0x21, 0 - .dw 0xb1c0, 0xc939, 0xb1ff, 0xc939, 0x21, 0 - .dw 0xb240, 0xc939, 0xb27f, 0xc939, 0x21, 0 - .dw 0xb2c0, 0xc939, 0xb2ff, 0xc939, 0x21, 0 - .dw 0xb340, 0xc939, 0xb37f, 0xc939, 0x21, 0 - .dw 0xb3c0, 0xc939, 0xb3ff, 0xc939, 0x21, 0 - .dw 0xb440, 0xc939, 0xb47f, 0xc939, 0x21, 0 - .dw 0xb4c0, 0xc939, 0xb4ff, 0xc939, 0x21, 0 - .dw 0xb540, 0xc939, 0xb57f, 0xc939, 0x21, 0 - .dw 0xb5c0, 0xc939, 0xb5ff, 0xc939, 0x21, 0 - .dw 0xb640, 0xc939, 0xb67f, 0xc939, 0x21, 0 - .dw 0xb6c0, 0xc939, 0xb6ff, 0xc939, 0x21, 0 - .dw 0xb740, 0xc939, 0xb77f, 0xc939, 0x21, 0 - .dw 0xb7c0, 0xc939, 0xb7ff, 0xc939, 0x21, 0 - .dw 0xb840, 0xc939, 0xb87f, 0xc939, 0x21, 0 - .dw 0xb8c0, 0xc939, 0xb8ff, 0xc939, 0x21, 0 - .dw 0xb940, 0xc939, 0xb97f, 0xc939, 0x21, 0 - .dw 0xb9c0, 0xc939, 0xdfff, 0xc939, 0x21, 0 - .dw 0xe040, 0xc939, 0xe07f, 0xc939, 0x21, 0 - .dw 0xe0c0, 0xc939, 0xe0ff, 0xc939, 0x21, 0 - .dw 0xe140, 0xc939, 0xe17f, 0xc939, 0x21, 0 - .dw 0xe1c0, 0xc939, 0xe1ff, 0xc939, 0x21, 0 - .dw 0xe240, 0xc939, 0xe27f, 0xc939, 0x21, 0 - .dw 0xe2c0, 0xc939, 0xe2ff, 0xc939, 0x21, 0 - .dw 0xe340, 0xc939, 0xe37f, 0xc939, 0x21, 0 - .dw 0xe3c0, 0xc939, 0xe3ff, 0xc939, 0x21, 0 - .dw 0xe440, 0xc939, 0xe47f, 0xc939, 0x21, 0 - .dw 0xe4c0, 0xc939, 0xe4ff, 0xc939, 0x21, 0 - .dw 0xe540, 0xc939, 0xe57f, 0xc939, 0x21, 0 - .dw 0xe5c0, 0xc939, 0xe5ff, 0xc939, 0x21, 0 - .dw 0xe640, 0xc939, 0xe67f, 0xc939, 0x21, 0 - .dw 0xe6c0, 0xc939, 0xe6ff, 0xc939, 0x21, 0 - .dw 0xe740, 0xc939, 0xe77f, 0xc939, 0x21, 0 - .dw 0xe7c0, 0xc939, 0xe7ff, 0xc939, 0x21, 0 - .dw 0xe840, 0xc939, 0xe87f, 0xc939, 0x21, 0 - .dw 0xe8c0, 0xc939, 0xe8ff, 0xc939, 0x21, 0 - .dw 0xe940, 0xc939, 0xe97f, 0xc939, 0x21, 0 - .dw 0xe9c0, 0xc939, 0xe9ff, 0xc939, 0x21, 0 - .dw 0xea40, 0xc939, 0xea7f, 0xc939, 0x21, 0 - .dw 0xeac0, 0xc939, 0xeaff, 0xc939, 0x21, 0 - .dw 0xeb40, 0xc939, 0xeb7f, 0xc939, 0x21, 0 - .dw 0xebc0, 0xc939, 0xebff, 0xc939, 0x21, 0 - .dw 0xec40, 0xc939, 0xec7f, 0xc939, 0x21, 0 - .dw 0xecc0, 0xc939, 0xecff, 0xc939, 0x21, 0 - .dw 0xed40, 0xc939, 0xed7f, 0xc939, 0x21, 0 - .dw 0xedc0, 0xc939, 0xedff, 0xc939, 0x21, 0 - .dw 0xee40, 0xc939, 0xee7f, 0xc939, 0x21, 0 - .dw 0xeec0, 0xc939, 0xeeff, 0xc939, 0x21, 0 - .dw 0xef40, 0xc939, 0xef7f, 0xc939, 0x21, 0 - .dw 0xefc0, 0xc939, 0xefff, 0xc939, 0x21, 0 - .dw 0xf040, 0xc939, 0xf07f, 0xc939, 0x21, 0 - .dw 0xf0c0, 0xc939, 0xf0ff, 0xc939, 0x21, 0 - .dw 0xf140, 0xc939, 0xf17f, 0xc939, 0x21, 0 - .dw 0xf1c0, 0xc939, 0xf1ff, 0xc939, 0x21, 0 - .dw 0xf240, 0xc939, 0xf27f, 0xc939, 0x21, 0 - .dw 0xf2c0, 0xc939, 0xf2ff, 0xc939, 0x21, 0 - .dw 0xf340, 0xc939, 0xf37f, 0xc939, 0x21, 0 - .dw 0xf3c0, 0xc939, 0xf3ff, 0xc939, 0x21, 0 - .dw 0xf440, 0xc939, 0xf47f, 0xc939, 0x21, 0 - .dw 0xf4c0, 0xc939, 0xf4ff, 0xc939, 0x21, 0 - .dw 0xf540, 0xc939, 0xf57f, 0xc939, 0x21, 0 - .dw 0xf5c0, 0xc939, 0xf5ff, 0xc939, 0x21, 0 - .dw 0xf640, 0xc939, 0xf67f, 0xc939, 0x21, 0 - .dw 0xf6c0, 0xc939, 0xf6ff, 0xc939, 0x21, 0 - .dw 0xf740, 0xc939, 0xf77f, 0xc939, 0x21, 0 - .dw 0xf7c0, 0xc939, 0xf7ff, 0xc939, 0x21, 0 - .dw 0xf840, 0xc939, 0xf87f, 0xc939, 0x21, 0 - .dw 0xf8c0, 0xc939, 0xf8ff, 0xc939, 0x21, 0 - .dw 0xf940, 0xc939, 0xf97f, 0xc939, 0x21, 0 - .dw 0xf9c0, 0xc939, 0x1fff, 0xc93a, 0x21, 0 - .dw 0x2040, 0xc93a, 0x207f, 0xc93a, 0x21, 0 - .dw 0x20c0, 0xc93a, 0x20ff, 0xc93a, 0x21, 0 - .dw 0x2140, 0xc93a, 0x217f, 0xc93a, 0x21, 0 - .dw 0x21c0, 0xc93a, 0x21ff, 0xc93a, 0x21, 0 - .dw 0x2240, 0xc93a, 0x227f, 0xc93a, 0x21, 0 - .dw 0x22c0, 0xc93a, 0x22ff, 0xc93a, 0x21, 0 - .dw 0x2340, 0xc93a, 0x237f, 0xc93a, 0x21, 0 - .dw 0x23c0, 0xc93a, 0x23ff, 0xc93a, 0x21, 0 - .dw 0x2440, 0xc93a, 0x247f, 0xc93a, 0x21, 0 - .dw 0x24c0, 0xc93a, 0x24ff, 0xc93a, 0x21, 0 - .dw 0x2540, 0xc93a, 0x257f, 0xc93a, 0x21, 0 - .dw 0x25c0, 0xc93a, 0x25ff, 0xc93a, 0x21, 0 - .dw 0x2640, 0xc93a, 0x267f, 0xc93a, 0x21, 0 - .dw 0x26c0, 0xc93a, 0x26ff, 0xc93a, 0x21, 0 - .dw 0x2740, 0xc93a, 0x277f, 0xc93a, 0x21, 0 - .dw 0x27c0, 0xc93a, 0x27ff, 0xc93a, 0x21, 0 - .dw 0x2840, 0xc93a, 0x287f, 0xc93a, 0x21, 0 - .dw 0x28c0, 0xc93a, 0x28ff, 0xc93a, 0x21, 0 - .dw 0x2940, 0xc93a, 0x297f, 0xc93a, 0x21, 0 - .dw 0x29c0, 0xc93a, 0x29ff, 0xc93a, 0x21, 0 - .dw 0x2a40, 0xc93a, 0x2a7f, 0xc93a, 0x21, 0 - .dw 0x2ac0, 0xc93a, 0x2aff, 0xc93a, 0x21, 0 - .dw 0x2b40, 0xc93a, 0x2b7f, 0xc93a, 0x21, 0 - .dw 0x2bc0, 0xc93a, 0x2bff, 0xc93a, 0x21, 0 - .dw 0x2c40, 0xc93a, 0x2c7f, 0xc93a, 0x21, 0 - .dw 0x2cc0, 0xc93a, 0x2cff, 0xc93a, 0x21, 0 - .dw 0x2d40, 0xc93a, 0x2d7f, 0xc93a, 0x21, 0 - .dw 0x2dc0, 0xc93a, 0x2dff, 0xc93a, 0x21, 0 - .dw 0x2e40, 0xc93a, 0x2e7f, 0xc93a, 0x21, 0 - .dw 0x2ec0, 0xc93a, 0x2eff, 0xc93a, 0x21, 0 - .dw 0x2f40, 0xc93a, 0x2f7f, 0xc93a, 0x21, 0 - .dw 0x2fc0, 0xc93a, 0x2fff, 0xc93a, 0x21, 0 - .dw 0x3040, 0xc93a, 0x307f, 0xc93a, 0x21, 0 - .dw 0x30c0, 0xc93a, 0x30ff, 0xc93a, 0x21, 0 - .dw 0x3140, 0xc93a, 0x317f, 0xc93a, 0x21, 0 - .dw 0x31c0, 0xc93a, 0x31ff, 0xc93a, 0x21, 0 - .dw 0x3240, 0xc93a, 0x327f, 0xc93a, 0x21, 0 - .dw 0x32c0, 0xc93a, 0x32ff, 0xc93a, 0x21, 0 - .dw 0x3340, 0xc93a, 0x337f, 0xc93a, 0x21, 0 - .dw 0x33c0, 0xc93a, 0x33ff, 0xc93a, 0x21, 0 - .dw 0x3440, 0xc93a, 0x347f, 0xc93a, 0x21, 0 - .dw 0x34c0, 0xc93a, 0x34ff, 0xc93a, 0x21, 0 - .dw 0x3540, 0xc93a, 0x357f, 0xc93a, 0x21, 0 - .dw 0x35c0, 0xc93a, 0x35ff, 0xc93a, 0x21, 0 - .dw 0x3640, 0xc93a, 0x367f, 0xc93a, 0x21, 0 - .dw 0x36c0, 0xc93a, 0x36ff, 0xc93a, 0x21, 0 - .dw 0x3740, 0xc93a, 0x377f, 0xc93a, 0x21, 0 - .dw 0x37c0, 0xc93a, 0x37ff, 0xc93a, 0x21, 0 - .dw 0x3840, 0xc93a, 0x387f, 0xc93a, 0x21, 0 - .dw 0x38c0, 0xc93a, 0x38ff, 0xc93a, 0x21, 0 - .dw 0x3940, 0xc93a, 0x397f, 0xc93a, 0x21, 0 - .dw 0x39c0, 0xc93a, 0x5fff, 0xc93a, 0x21, 0 - .dw 0x6040, 0xc93a, 0x607f, 0xc93a, 0x21, 0 - .dw 0x60c0, 0xc93a, 0x60ff, 0xc93a, 0x21, 0 - .dw 0x6140, 0xc93a, 0x617f, 0xc93a, 0x21, 0 - .dw 0x61c0, 0xc93a, 0x61ff, 0xc93a, 0x21, 0 - .dw 0x6240, 0xc93a, 0x627f, 0xc93a, 0x21, 0 - .dw 0x62c0, 0xc93a, 0x62ff, 0xc93a, 0x21, 0 - .dw 0x6340, 0xc93a, 0x637f, 0xc93a, 0x21, 0 - .dw 0x63c0, 0xc93a, 0x63ff, 0xc93a, 0x21, 0 - .dw 0x6440, 0xc93a, 0x647f, 0xc93a, 0x21, 0 - .dw 0x64c0, 0xc93a, 0x64ff, 0xc93a, 0x21, 0 - .dw 0x6540, 0xc93a, 0x657f, 0xc93a, 0x21, 0 - .dw 0x65c0, 0xc93a, 0x65ff, 0xc93a, 0x21, 0 - .dw 0x6640, 0xc93a, 0x667f, 0xc93a, 0x21, 0 - .dw 0x66c0, 0xc93a, 0x66ff, 0xc93a, 0x21, 0 - .dw 0x6740, 0xc93a, 0x677f, 0xc93a, 0x21, 0 - .dw 0x67c0, 0xc93a, 0x67ff, 0xc93a, 0x21, 0 - .dw 0x6840, 0xc93a, 0x687f, 0xc93a, 0x21, 0 - .dw 0x68c0, 0xc93a, 0x68ff, 0xc93a, 0x21, 0 - .dw 0x6940, 0xc93a, 0x697f, 0xc93a, 0x21, 0 - .dw 0x69c0, 0xc93a, 0x69ff, 0xc93a, 0x21, 0 - .dw 0x6a40, 0xc93a, 0x6a7f, 0xc93a, 0x21, 0 - .dw 0x6ac0, 0xc93a, 0x6aff, 0xc93a, 0x21, 0 - .dw 0x6b40, 0xc93a, 0x6b7f, 0xc93a, 0x21, 0 - .dw 0x6bc0, 0xc93a, 0x6bff, 0xc93a, 0x21, 0 - .dw 0x6c40, 0xc93a, 0x6c7f, 0xc93a, 0x21, 0 - .dw 0x6cc0, 0xc93a, 0x6cff, 0xc93a, 0x21, 0 - .dw 0x6d40, 0xc93a, 0x6d7f, 0xc93a, 0x21, 0 - .dw 0x6dc0, 0xc93a, 0x6dff, 0xc93a, 0x21, 0 - .dw 0x6e40, 0xc93a, 0x6e7f, 0xc93a, 0x21, 0 - .dw 0x6ec0, 0xc93a, 0x6eff, 0xc93a, 0x21, 0 - .dw 0x6f40, 0xc93a, 0x6f7f, 0xc93a, 0x21, 0 - .dw 0x6fc0, 0xc93a, 0x6fff, 0xc93a, 0x21, 0 - .dw 0x7040, 0xc93a, 0x707f, 0xc93a, 0x21, 0 - .dw 0x70c0, 0xc93a, 0x70ff, 0xc93a, 0x21, 0 - .dw 0x7140, 0xc93a, 0x717f, 0xc93a, 0x21, 0 - .dw 0x71c0, 0xc93a, 0x71ff, 0xc93a, 0x21, 0 - .dw 0x7240, 0xc93a, 0x727f, 0xc93a, 0x21, 0 - .dw 0x72c0, 0xc93a, 0x72ff, 0xc93a, 0x21, 0 - .dw 0x7340, 0xc93a, 0x737f, 0xc93a, 0x21, 0 - .dw 0x73c0, 0xc93a, 0x73ff, 0xc93a, 0x21, 0 - .dw 0x7440, 0xc93a, 0x747f, 0xc93a, 0x21, 0 - .dw 0x74c0, 0xc93a, 0x74ff, 0xc93a, 0x21, 0 - .dw 0x7540, 0xc93a, 0x757f, 0xc93a, 0x21, 0 - .dw 0x75c0, 0xc93a, 0x75ff, 0xc93a, 0x21, 0 - .dw 0x7640, 0xc93a, 0x767f, 0xc93a, 0x21, 0 - .dw 0x76c0, 0xc93a, 0x76ff, 0xc93a, 0x21, 0 - .dw 0x7740, 0xc93a, 0x777f, 0xc93a, 0x21, 0 - .dw 0x77c0, 0xc93a, 0x77ff, 0xc93a, 0x21, 0 - .dw 0x7840, 0xc93a, 0x787f, 0xc93a, 0x21, 0 - .dw 0x78c0, 0xc93a, 0x78ff, 0xc93a, 0x21, 0 - .dw 0x7940, 0xc93a, 0x797f, 0xc93a, 0x21, 0 - .dw 0x79c0, 0xc93a, 0x9fff, 0xc93a, 0x21, 0 - .dw 0xa040, 0xc93a, 0xa07f, 0xc93a, 0x21, 0 - .dw 0xa0c0, 0xc93a, 0xa0ff, 0xc93a, 0x21, 0 - .dw 0xa140, 0xc93a, 0xa17f, 0xc93a, 0x21, 0 - .dw 0xa1c0, 0xc93a, 0xa1ff, 0xc93a, 0x21, 0 - .dw 0xa240, 0xc93a, 0xa27f, 0xc93a, 0x21, 0 - .dw 0xa2c0, 0xc93a, 0xa2ff, 0xc93a, 0x21, 0 - .dw 0xa340, 0xc93a, 0xa37f, 0xc93a, 0x21, 0 - .dw 0xa3c0, 0xc93a, 0xa3ff, 0xc93a, 0x21, 0 - .dw 0xa440, 0xc93a, 0xa47f, 0xc93a, 0x21, 0 - .dw 0xa4c0, 0xc93a, 0xa4ff, 0xc93a, 0x21, 0 - .dw 0xa540, 0xc93a, 0xa57f, 0xc93a, 0x21, 0 - .dw 0xa5c0, 0xc93a, 0xa5ff, 0xc93a, 0x21, 0 - .dw 0xa640, 0xc93a, 0xa67f, 0xc93a, 0x21, 0 - .dw 0xa6c0, 0xc93a, 0xa6ff, 0xc93a, 0x21, 0 - .dw 0xa740, 0xc93a, 0xa77f, 0xc93a, 0x21, 0 - .dw 0xa7c0, 0xc93a, 0xa7ff, 0xc93a, 0x21, 0 - .dw 0xa840, 0xc93a, 0xa87f, 0xc93a, 0x21, 0 - .dw 0xa8c0, 0xc93a, 0xa8ff, 0xc93a, 0x21, 0 - .dw 0xa940, 0xc93a, 0xa97f, 0xc93a, 0x21, 0 - .dw 0xa9c0, 0xc93a, 0xa9ff, 0xc93a, 0x21, 0 - .dw 0xaa40, 0xc93a, 0xaa7f, 0xc93a, 0x21, 0 - .dw 0xaac0, 0xc93a, 0xaaff, 0xc93a, 0x21, 0 - .dw 0xab40, 0xc93a, 0xab7f, 0xc93a, 0x21, 0 - .dw 0xabc0, 0xc93a, 0xabff, 0xc93a, 0x21, 0 - .dw 0xac40, 0xc93a, 0xac7f, 0xc93a, 0x21, 0 - .dw 0xacc0, 0xc93a, 0xacff, 0xc93a, 0x21, 0 - .dw 0xad40, 0xc93a, 0xad7f, 0xc93a, 0x21, 0 - .dw 0xadc0, 0xc93a, 0xadff, 0xc93a, 0x21, 0 - .dw 0xae40, 0xc93a, 0xae7f, 0xc93a, 0x21, 0 - .dw 0xaec0, 0xc93a, 0xaeff, 0xc93a, 0x21, 0 - .dw 0xaf40, 0xc93a, 0xaf7f, 0xc93a, 0x21, 0 - .dw 0xafc0, 0xc93a, 0xafff, 0xc93a, 0x21, 0 - .dw 0xb040, 0xc93a, 0xb07f, 0xc93a, 0x21, 0 - .dw 0xb0c0, 0xc93a, 0xb0ff, 0xc93a, 0x21, 0 - .dw 0xb140, 0xc93a, 0xb17f, 0xc93a, 0x21, 0 - .dw 0xb1c0, 0xc93a, 0xb1ff, 0xc93a, 0x21, 0 - .dw 0xb240, 0xc93a, 0xb27f, 0xc93a, 0x21, 0 - .dw 0xb2c0, 0xc93a, 0xb2ff, 0xc93a, 0x21, 0 - .dw 0xb340, 0xc93a, 0xb37f, 0xc93a, 0x21, 0 - .dw 0xb3c0, 0xc93a, 0xb3ff, 0xc93a, 0x21, 0 - .dw 0xb440, 0xc93a, 0xb47f, 0xc93a, 0x21, 0 - .dw 0xb4c0, 0xc93a, 0xb4ff, 0xc93a, 0x21, 0 - .dw 0xb540, 0xc93a, 0xb57f, 0xc93a, 0x21, 0 - .dw 0xb5c0, 0xc93a, 0xb5ff, 0xc93a, 0x21, 0 - .dw 0xb640, 0xc93a, 0xb67f, 0xc93a, 0x21, 0 - .dw 0xb6c0, 0xc93a, 0xb6ff, 0xc93a, 0x21, 0 - .dw 0xb740, 0xc93a, 0xb77f, 0xc93a, 0x21, 0 - .dw 0xb7c0, 0xc93a, 0xb7ff, 0xc93a, 0x21, 0 - .dw 0xb840, 0xc93a, 0xb87f, 0xc93a, 0x21, 0 - .dw 0xb8c0, 0xc93a, 0xb8ff, 0xc93a, 0x21, 0 - .dw 0xb940, 0xc93a, 0xb97f, 0xc93a, 0x21, 0 - .dw 0xb9c0, 0xc93a, 0xdfff, 0xc93a, 0x21, 0 - .dw 0xe040, 0xc93a, 0xe07f, 0xc93a, 0x21, 0 - .dw 0xe0c0, 0xc93a, 0xe0ff, 0xc93a, 0x21, 0 - .dw 0xe140, 0xc93a, 0xe17f, 0xc93a, 0x21, 0 - .dw 0xe1c0, 0xc93a, 0xe1ff, 0xc93a, 0x21, 0 - .dw 0xe240, 0xc93a, 0xe27f, 0xc93a, 0x21, 0 - .dw 0xe2c0, 0xc93a, 0xe2ff, 0xc93a, 0x21, 0 - .dw 0xe340, 0xc93a, 0xe37f, 0xc93a, 0x21, 0 - .dw 0xe3c0, 0xc93a, 0xe3ff, 0xc93a, 0x21, 0 - .dw 0xe440, 0xc93a, 0xe47f, 0xc93a, 0x21, 0 - .dw 0xe4c0, 0xc93a, 0xe4ff, 0xc93a, 0x21, 0 - .dw 0xe540, 0xc93a, 0xe57f, 0xc93a, 0x21, 0 - .dw 0xe5c0, 0xc93a, 0xe5ff, 0xc93a, 0x21, 0 - .dw 0xe640, 0xc93a, 0xe67f, 0xc93a, 0x21, 0 - .dw 0xe6c0, 0xc93a, 0xe6ff, 0xc93a, 0x21, 0 - .dw 0xe740, 0xc93a, 0xe77f, 0xc93a, 0x21, 0 - .dw 0xe7c0, 0xc93a, 0xe7ff, 0xc93a, 0x21, 0 - .dw 0xe840, 0xc93a, 0xe87f, 0xc93a, 0x21, 0 - .dw 0xe8c0, 0xc93a, 0xe8ff, 0xc93a, 0x21, 0 - .dw 0xe940, 0xc93a, 0xe97f, 0xc93a, 0x21, 0 - .dw 0xe9c0, 0xc93a, 0xe9ff, 0xc93a, 0x21, 0 - .dw 0xea40, 0xc93a, 0xea7f, 0xc93a, 0x21, 0 - .dw 0xeac0, 0xc93a, 0xeaff, 0xc93a, 0x21, 0 - .dw 0xeb40, 0xc93a, 0xeb7f, 0xc93a, 0x21, 0 - .dw 0xebc0, 0xc93a, 0xebff, 0xc93a, 0x21, 0 - .dw 0xec40, 0xc93a, 0xec7f, 0xc93a, 0x21, 0 - .dw 0xecc0, 0xc93a, 0xecff, 0xc93a, 0x21, 0 - .dw 0xed40, 0xc93a, 0xed7f, 0xc93a, 0x21, 0 - .dw 0xedc0, 0xc93a, 0xedff, 0xc93a, 0x21, 0 - .dw 0xee40, 0xc93a, 0xee7f, 0xc93a, 0x21, 0 - .dw 0xeec0, 0xc93a, 0xeeff, 0xc93a, 0x21, 0 - .dw 0xef40, 0xc93a, 0xef7f, 0xc93a, 0x21, 0 - .dw 0xefc0, 0xc93a, 0xefff, 0xc93a, 0x21, 0 - .dw 0xf040, 0xc93a, 0xf07f, 0xc93a, 0x21, 0 - .dw 0xf0c0, 0xc93a, 0xf0ff, 0xc93a, 0x21, 0 - .dw 0xf140, 0xc93a, 0xf17f, 0xc93a, 0x21, 0 - .dw 0xf1c0, 0xc93a, 0xf1ff, 0xc93a, 0x21, 0 - .dw 0xf240, 0xc93a, 0xf27f, 0xc93a, 0x21, 0 - .dw 0xf2c0, 0xc93a, 0xf2ff, 0xc93a, 0x21, 0 - .dw 0xf340, 0xc93a, 0xf37f, 0xc93a, 0x21, 0 - .dw 0xf3c0, 0xc93a, 0xf3ff, 0xc93a, 0x21, 0 - .dw 0xf440, 0xc93a, 0xf47f, 0xc93a, 0x21, 0 - .dw 0xf4c0, 0xc93a, 0xf4ff, 0xc93a, 0x21, 0 - .dw 0xf540, 0xc93a, 0xf57f, 0xc93a, 0x21, 0 - .dw 0xf5c0, 0xc93a, 0xf5ff, 0xc93a, 0x21, 0 - .dw 0xf640, 0xc93a, 0xf67f, 0xc93a, 0x21, 0 - .dw 0xf6c0, 0xc93a, 0xf6ff, 0xc93a, 0x21, 0 - .dw 0xf740, 0xc93a, 0xf77f, 0xc93a, 0x21, 0 - .dw 0xf7c0, 0xc93a, 0xf7ff, 0xc93a, 0x21, 0 - .dw 0xf840, 0xc93a, 0xf87f, 0xc93a, 0x21, 0 - .dw 0xf8c0, 0xc93a, 0xf8ff, 0xc93a, 0x21, 0 - .dw 0xf940, 0xc93a, 0xf97f, 0xc93a, 0x21, 0 - .dw 0xf9c0, 0xc93a, 0xffff, 0xc93b, 0x21, 0 - .dw 0x0040, 0xc93c, 0x007f, 0xc93c, 0x21, 0 - .dw 0x00c0, 0xc93c, 0x00ff, 0xc93c, 0x21, 0 - .dw 0x0140, 0xc93c, 0x017f, 0xc93c, 0x21, 0 - .dw 0x01c0, 0xc93c, 0x01ff, 0xc93c, 0x21, 0 - .dw 0x0240, 0xc93c, 0x027f, 0xc93c, 0x21, 0 - .dw 0x02c0, 0xc93c, 0x02ff, 0xc93c, 0x21, 0 - .dw 0x0340, 0xc93c, 0x037f, 0xc93c, 0x21, 0 - .dw 0x03c0, 0xc93c, 0x03ff, 0xc93c, 0x21, 0 - .dw 0x0440, 0xc93c, 0x047f, 0xc93c, 0x21, 0 - .dw 0x04c0, 0xc93c, 0x04ff, 0xc93c, 0x21, 0 - .dw 0x0540, 0xc93c, 0x057f, 0xc93c, 0x21, 0 - .dw 0x05c0, 0xc93c, 0x05ff, 0xc93c, 0x21, 0 - .dw 0x0640, 0xc93c, 0x067f, 0xc93c, 0x21, 0 - .dw 0x06c0, 0xc93c, 0x06ff, 0xc93c, 0x21, 0 - .dw 0x0740, 0xc93c, 0x077f, 0xc93c, 0x21, 0 - .dw 0x07c0, 0xc93c, 0x07ff, 0xc93c, 0x21, 0 - .dw 0x0840, 0xc93c, 0x087f, 0xc93c, 0x21, 0 - .dw 0x08c0, 0xc93c, 0x08ff, 0xc93c, 0x21, 0 - .dw 0x0940, 0xc93c, 0x097f, 0xc93c, 0x21, 0 - .dw 0x09c0, 0xc93c, 0x09ff, 0xc93c, 0x21, 0 - .dw 0x0a40, 0xc93c, 0x0a7f, 0xc93c, 0x21, 0 - .dw 0x0ac0, 0xc93c, 0x0aff, 0xc93c, 0x21, 0 - .dw 0x0b40, 0xc93c, 0x0b7f, 0xc93c, 0x21, 0 - .dw 0x0bc0, 0xc93c, 0x0bff, 0xc93c, 0x21, 0 - .dw 0x0c40, 0xc93c, 0x0c7f, 0xc93c, 0x21, 0 - .dw 0x0cc0, 0xc93c, 0x0cff, 0xc93c, 0x21, 0 - .dw 0x0d40, 0xc93c, 0x0d7f, 0xc93c, 0x21, 0 - .dw 0x0dc0, 0xc93c, 0x0dff, 0xc93c, 0x21, 0 - .dw 0x0e40, 0xc93c, 0x0e7f, 0xc93c, 0x21, 0 - .dw 0x0ec0, 0xc93c, 0x0eff, 0xc93c, 0x21, 0 - .dw 0x0f40, 0xc93c, 0x0f7f, 0xc93c, 0x21, 0 - .dw 0x0fc0, 0xc93c, 0x0fff, 0xc93c, 0x21, 0 - .dw 0x1040, 0xc93c, 0x107f, 0xc93c, 0x21, 0 - .dw 0x10c0, 0xc93c, 0x10ff, 0xc93c, 0x21, 0 - .dw 0x1140, 0xc93c, 0x117f, 0xc93c, 0x21, 0 - .dw 0x11c0, 0xc93c, 0x11ff, 0xc93c, 0x21, 0 - .dw 0x1240, 0xc93c, 0x127f, 0xc93c, 0x21, 0 - .dw 0x12c0, 0xc93c, 0x12ff, 0xc93c, 0x21, 0 - .dw 0x1340, 0xc93c, 0x137f, 0xc93c, 0x21, 0 - .dw 0x13c0, 0xc93c, 0x13ff, 0xc93c, 0x21, 0 - .dw 0x1440, 0xc93c, 0x147f, 0xc93c, 0x21, 0 - .dw 0x14c0, 0xc93c, 0x14ff, 0xc93c, 0x21, 0 - .dw 0x1540, 0xc93c, 0x157f, 0xc93c, 0x21, 0 - .dw 0x15c0, 0xc93c, 0x15ff, 0xc93c, 0x21, 0 - .dw 0x1640, 0xc93c, 0x167f, 0xc93c, 0x21, 0 - .dw 0x16c0, 0xc93c, 0x16ff, 0xc93c, 0x21, 0 - .dw 0x1740, 0xc93c, 0x177f, 0xc93c, 0x21, 0 - .dw 0x17c0, 0xc93c, 0x17ff, 0xc93c, 0x21, 0 - .dw 0x1840, 0xc93c, 0x187f, 0xc93c, 0x21, 0 - .dw 0x18c0, 0xc93c, 0x18ff, 0xc93c, 0x21, 0 - .dw 0x1940, 0xc93c, 0x197f, 0xc93c, 0x21, 0 - .dw 0x19c0, 0xc93c, 0x1fff, 0xc93c, 0x21, 0 - .dw 0x2040, 0xc93c, 0x207f, 0xc93c, 0x21, 0 - .dw 0x20c0, 0xc93c, 0x20ff, 0xc93c, 0x21, 0 - .dw 0x2140, 0xc93c, 0x217f, 0xc93c, 0x21, 0 - .dw 0x21c0, 0xc93c, 0x21ff, 0xc93c, 0x21, 0 - .dw 0x2240, 0xc93c, 0x227f, 0xc93c, 0x21, 0 - .dw 0x22c0, 0xc93c, 0x22ff, 0xc93c, 0x21, 0 - .dw 0x2340, 0xc93c, 0x237f, 0xc93c, 0x21, 0 - .dw 0x23c0, 0xc93c, 0x23ff, 0xc93c, 0x21, 0 - .dw 0x2440, 0xc93c, 0x247f, 0xc93c, 0x21, 0 - .dw 0x24c0, 0xc93c, 0x24ff, 0xc93c, 0x21, 0 - .dw 0x2540, 0xc93c, 0x257f, 0xc93c, 0x21, 0 - .dw 0x25c0, 0xc93c, 0x25ff, 0xc93c, 0x21, 0 - .dw 0x2640, 0xc93c, 0x267f, 0xc93c, 0x21, 0 - .dw 0x26c0, 0xc93c, 0x26ff, 0xc93c, 0x21, 0 - .dw 0x2740, 0xc93c, 0x277f, 0xc93c, 0x21, 0 - .dw 0x27c0, 0xc93c, 0x27ff, 0xc93c, 0x21, 0 - .dw 0x2840, 0xc93c, 0x287f, 0xc93c, 0x21, 0 - .dw 0x28c0, 0xc93c, 0x28ff, 0xc93c, 0x21, 0 - .dw 0x2940, 0xc93c, 0x297f, 0xc93c, 0x21, 0 - .dw 0x29c0, 0xc93c, 0x29ff, 0xc93c, 0x21, 0 - .dw 0x2a40, 0xc93c, 0x2a7f, 0xc93c, 0x21, 0 - .dw 0x2ac0, 0xc93c, 0x2aff, 0xc93c, 0x21, 0 - .dw 0x2b40, 0xc93c, 0x2b7f, 0xc93c, 0x21, 0 - .dw 0x2bc0, 0xc93c, 0x2bff, 0xc93c, 0x21, 0 - .dw 0x2c40, 0xc93c, 0x2c7f, 0xc93c, 0x21, 0 - .dw 0x2cc0, 0xc93c, 0x2cff, 0xc93c, 0x21, 0 - .dw 0x2d40, 0xc93c, 0x2d7f, 0xc93c, 0x21, 0 - .dw 0x2dc0, 0xc93c, 0x2dff, 0xc93c, 0x21, 0 - .dw 0x2e40, 0xc93c, 0x2e7f, 0xc93c, 0x21, 0 - .dw 0x2ec0, 0xc93c, 0x2eff, 0xc93c, 0x21, 0 - .dw 0x2f40, 0xc93c, 0x2f7f, 0xc93c, 0x21, 0 - .dw 0x2fc0, 0xc93c, 0x2fff, 0xc93c, 0x21, 0 - .dw 0x3040, 0xc93c, 0x307f, 0xc93c, 0x21, 0 - .dw 0x30c0, 0xc93c, 0x30ff, 0xc93c, 0x21, 0 - .dw 0x3140, 0xc93c, 0x317f, 0xc93c, 0x21, 0 - .dw 0x31c0, 0xc93c, 0x31ff, 0xc93c, 0x21, 0 - .dw 0x3240, 0xc93c, 0x327f, 0xc93c, 0x21, 0 - .dw 0x32c0, 0xc93c, 0x32ff, 0xc93c, 0x21, 0 - .dw 0x3340, 0xc93c, 0x337f, 0xc93c, 0x21, 0 - .dw 0x33c0, 0xc93c, 0x33ff, 0xc93c, 0x21, 0 - .dw 0x3440, 0xc93c, 0x347f, 0xc93c, 0x21, 0 - .dw 0x34c0, 0xc93c, 0x34ff, 0xc93c, 0x21, 0 - .dw 0x3540, 0xc93c, 0x357f, 0xc93c, 0x21, 0 - .dw 0x35c0, 0xc93c, 0x35ff, 0xc93c, 0x21, 0 - .dw 0x3640, 0xc93c, 0x367f, 0xc93c, 0x21, 0 - .dw 0x36c0, 0xc93c, 0x36ff, 0xc93c, 0x21, 0 - .dw 0x3740, 0xc93c, 0x377f, 0xc93c, 0x21, 0 - .dw 0x37c0, 0xc93c, 0x37ff, 0xc93c, 0x21, 0 - .dw 0x3840, 0xc93c, 0x387f, 0xc93c, 0x21, 0 - .dw 0x38c0, 0xc93c, 0x38ff, 0xc93c, 0x21, 0 - .dw 0x3940, 0xc93c, 0x397f, 0xc93c, 0x21, 0 - .dw 0x39c0, 0xc93c, 0x3fff, 0xc93c, 0x21, 0 - .dw 0x4040, 0xc93c, 0x407f, 0xc93c, 0x21, 0 - .dw 0x40c0, 0xc93c, 0x40ff, 0xc93c, 0x21, 0 - .dw 0x4140, 0xc93c, 0x417f, 0xc93c, 0x21, 0 - .dw 0x41c0, 0xc93c, 0x41ff, 0xc93c, 0x21, 0 - .dw 0x4240, 0xc93c, 0x427f, 0xc93c, 0x21, 0 - .dw 0x42c0, 0xc93c, 0x42ff, 0xc93c, 0x21, 0 - .dw 0x4340, 0xc93c, 0x437f, 0xc93c, 0x21, 0 - .dw 0x43c0, 0xc93c, 0x43ff, 0xc93c, 0x21, 0 - .dw 0x4440, 0xc93c, 0x447f, 0xc93c, 0x21, 0 - .dw 0x44c0, 0xc93c, 0x44ff, 0xc93c, 0x21, 0 - .dw 0x4540, 0xc93c, 0x457f, 0xc93c, 0x21, 0 - .dw 0x45c0, 0xc93c, 0x45ff, 0xc93c, 0x21, 0 - .dw 0x4640, 0xc93c, 0x467f, 0xc93c, 0x21, 0 - .dw 0x46c0, 0xc93c, 0x46ff, 0xc93c, 0x21, 0 - .dw 0x4740, 0xc93c, 0x477f, 0xc93c, 0x21, 0 - .dw 0x47c0, 0xc93c, 0x47ff, 0xc93c, 0x21, 0 - .dw 0x4840, 0xc93c, 0x487f, 0xc93c, 0x21, 0 - .dw 0x48c0, 0xc93c, 0x48ff, 0xc93c, 0x21, 0 - .dw 0x4940, 0xc93c, 0x497f, 0xc93c, 0x21, 0 - .dw 0x49c0, 0xc93c, 0x49ff, 0xc93c, 0x21, 0 - .dw 0x4a40, 0xc93c, 0x4a7f, 0xc93c, 0x21, 0 - .dw 0x4ac0, 0xc93c, 0x4aff, 0xc93c, 0x21, 0 - .dw 0x4b40, 0xc93c, 0x4b7f, 0xc93c, 0x21, 0 - .dw 0x4bc0, 0xc93c, 0x4bff, 0xc93c, 0x21, 0 - .dw 0x4c40, 0xc93c, 0x4c7f, 0xc93c, 0x21, 0 - .dw 0x4cc0, 0xc93c, 0x4cff, 0xc93c, 0x21, 0 - .dw 0x4d40, 0xc93c, 0x4d7f, 0xc93c, 0x21, 0 - .dw 0x4dc0, 0xc93c, 0x4dff, 0xc93c, 0x21, 0 - .dw 0x4e40, 0xc93c, 0x4e7f, 0xc93c, 0x21, 0 - .dw 0x4ec0, 0xc93c, 0x4eff, 0xc93c, 0x21, 0 - .dw 0x4f40, 0xc93c, 0x4f7f, 0xc93c, 0x21, 0 - .dw 0x4fc0, 0xc93c, 0x4fff, 0xc93c, 0x21, 0 - .dw 0x5040, 0xc93c, 0x507f, 0xc93c, 0x21, 0 - .dw 0x50c0, 0xc93c, 0x50ff, 0xc93c, 0x21, 0 - .dw 0x5140, 0xc93c, 0x517f, 0xc93c, 0x21, 0 - .dw 0x51c0, 0xc93c, 0x51ff, 0xc93c, 0x21, 0 - .dw 0x5240, 0xc93c, 0x527f, 0xc93c, 0x21, 0 - .dw 0x52c0, 0xc93c, 0x52ff, 0xc93c, 0x21, 0 - .dw 0x5340, 0xc93c, 0x537f, 0xc93c, 0x21, 0 - .dw 0x53c0, 0xc93c, 0x53ff, 0xc93c, 0x21, 0 - .dw 0x5440, 0xc93c, 0x547f, 0xc93c, 0x21, 0 - .dw 0x54c0, 0xc93c, 0x54ff, 0xc93c, 0x21, 0 - .dw 0x5540, 0xc93c, 0x557f, 0xc93c, 0x21, 0 - .dw 0x55c0, 0xc93c, 0x55ff, 0xc93c, 0x21, 0 - .dw 0x5640, 0xc93c, 0x567f, 0xc93c, 0x21, 0 - .dw 0x56c0, 0xc93c, 0x56ff, 0xc93c, 0x21, 0 - .dw 0x5740, 0xc93c, 0x577f, 0xc93c, 0x21, 0 - .dw 0x57c0, 0xc93c, 0x57ff, 0xc93c, 0x21, 0 - .dw 0x5840, 0xc93c, 0x587f, 0xc93c, 0x21, 0 - .dw 0x58c0, 0xc93c, 0x58ff, 0xc93c, 0x21, 0 - .dw 0x5940, 0xc93c, 0x597f, 0xc93c, 0x21, 0 - .dw 0x59c0, 0xc93c, 0x5fff, 0xc93c, 0x21, 0 - .dw 0x6040, 0xc93c, 0x607f, 0xc93c, 0x21, 0 - .dw 0x60c0, 0xc93c, 0x60ff, 0xc93c, 0x21, 0 - .dw 0x6140, 0xc93c, 0x617f, 0xc93c, 0x21, 0 - .dw 0x61c0, 0xc93c, 0x61ff, 0xc93c, 0x21, 0 - .dw 0x6240, 0xc93c, 0x627f, 0xc93c, 0x21, 0 - .dw 0x62c0, 0xc93c, 0x62ff, 0xc93c, 0x21, 0 - .dw 0x6340, 0xc93c, 0x637f, 0xc93c, 0x21, 0 - .dw 0x63c0, 0xc93c, 0x63ff, 0xc93c, 0x21, 0 - .dw 0x6440, 0xc93c, 0x647f, 0xc93c, 0x21, 0 - .dw 0x64c0, 0xc93c, 0x64ff, 0xc93c, 0x21, 0 - .dw 0x6540, 0xc93c, 0x657f, 0xc93c, 0x21, 0 - .dw 0x65c0, 0xc93c, 0x65ff, 0xc93c, 0x21, 0 - .dw 0x6640, 0xc93c, 0x667f, 0xc93c, 0x21, 0 - .dw 0x66c0, 0xc93c, 0x66ff, 0xc93c, 0x21, 0 - .dw 0x6740, 0xc93c, 0x677f, 0xc93c, 0x21, 0 - .dw 0x67c0, 0xc93c, 0x67ff, 0xc93c, 0x21, 0 - .dw 0x6840, 0xc93c, 0x687f, 0xc93c, 0x21, 0 - .dw 0x68c0, 0xc93c, 0x68ff, 0xc93c, 0x21, 0 - .dw 0x6940, 0xc93c, 0x697f, 0xc93c, 0x21, 0 - .dw 0x69c0, 0xc93c, 0x69ff, 0xc93c, 0x21, 0 - .dw 0x6a40, 0xc93c, 0x6a7f, 0xc93c, 0x21, 0 - .dw 0x6ac0, 0xc93c, 0x6aff, 0xc93c, 0x21, 0 - .dw 0x6b40, 0xc93c, 0x6b7f, 0xc93c, 0x21, 0 - .dw 0x6bc0, 0xc93c, 0x6bff, 0xc93c, 0x21, 0 - .dw 0x6c40, 0xc93c, 0x6c7f, 0xc93c, 0x21, 0 - .dw 0x6cc0, 0xc93c, 0x6cff, 0xc93c, 0x21, 0 - .dw 0x6d40, 0xc93c, 0x6d7f, 0xc93c, 0x21, 0 - .dw 0x6dc0, 0xc93c, 0x6dff, 0xc93c, 0x21, 0 - .dw 0x6e40, 0xc93c, 0x6e7f, 0xc93c, 0x21, 0 - .dw 0x6ec0, 0xc93c, 0x6eff, 0xc93c, 0x21, 0 - .dw 0x6f40, 0xc93c, 0x6f7f, 0xc93c, 0x21, 0 - .dw 0x6fc0, 0xc93c, 0x6fff, 0xc93c, 0x21, 0 - .dw 0x7040, 0xc93c, 0x707f, 0xc93c, 0x21, 0 - .dw 0x70c0, 0xc93c, 0x70ff, 0xc93c, 0x21, 0 - .dw 0x7140, 0xc93c, 0x717f, 0xc93c, 0x21, 0 - .dw 0x71c0, 0xc93c, 0x71ff, 0xc93c, 0x21, 0 - .dw 0x7240, 0xc93c, 0x727f, 0xc93c, 0x21, 0 - .dw 0x72c0, 0xc93c, 0x72ff, 0xc93c, 0x21, 0 - .dw 0x7340, 0xc93c, 0x737f, 0xc93c, 0x21, 0 - .dw 0x73c0, 0xc93c, 0x73ff, 0xc93c, 0x21, 0 - .dw 0x7440, 0xc93c, 0x747f, 0xc93c, 0x21, 0 - .dw 0x74c0, 0xc93c, 0x74ff, 0xc93c, 0x21, 0 - .dw 0x7540, 0xc93c, 0x757f, 0xc93c, 0x21, 0 - .dw 0x75c0, 0xc93c, 0x75ff, 0xc93c, 0x21, 0 - .dw 0x7640, 0xc93c, 0x767f, 0xc93c, 0x21, 0 - .dw 0x76c0, 0xc93c, 0x76ff, 0xc93c, 0x21, 0 - .dw 0x7740, 0xc93c, 0x777f, 0xc93c, 0x21, 0 - .dw 0x77c0, 0xc93c, 0x77ff, 0xc93c, 0x21, 0 - .dw 0x7840, 0xc93c, 0x787f, 0xc93c, 0x21, 0 - .dw 0x78c0, 0xc93c, 0x78ff, 0xc93c, 0x21, 0 - .dw 0x7940, 0xc93c, 0x797f, 0xc93c, 0x21, 0 - .dw 0x79c0, 0xc93c, 0x7fff, 0xc93c, 0x21, 0 - .dw 0x8040, 0xc93c, 0x807f, 0xc93c, 0x21, 0 - .dw 0x80c0, 0xc93c, 0x80ff, 0xc93c, 0x21, 0 - .dw 0x8140, 0xc93c, 0x817f, 0xc93c, 0x21, 0 - .dw 0x81c0, 0xc93c, 0x81ff, 0xc93c, 0x21, 0 - .dw 0x8240, 0xc93c, 0x827f, 0xc93c, 0x21, 0 - .dw 0x82c0, 0xc93c, 0x82ff, 0xc93c, 0x21, 0 - .dw 0x8340, 0xc93c, 0x837f, 0xc93c, 0x21, 0 - .dw 0x83c0, 0xc93c, 0x83ff, 0xc93c, 0x21, 0 - .dw 0x8440, 0xc93c, 0x847f, 0xc93c, 0x21, 0 - .dw 0x84c0, 0xc93c, 0x84ff, 0xc93c, 0x21, 0 - .dw 0x8540, 0xc93c, 0x857f, 0xc93c, 0x21, 0 - .dw 0x85c0, 0xc93c, 0x85ff, 0xc93c, 0x21, 0 - .dw 0x8640, 0xc93c, 0x867f, 0xc93c, 0x21, 0 - .dw 0x86c0, 0xc93c, 0x86ff, 0xc93c, 0x21, 0 - .dw 0x8740, 0xc93c, 0x877f, 0xc93c, 0x21, 0 - .dw 0x87c0, 0xc93c, 0x87ff, 0xc93c, 0x21, 0 - .dw 0x8840, 0xc93c, 0x887f, 0xc93c, 0x21, 0 - .dw 0x88c0, 0xc93c, 0x88ff, 0xc93c, 0x21, 0 - .dw 0x8940, 0xc93c, 0x897f, 0xc93c, 0x21, 0 - .dw 0x89c0, 0xc93c, 0x89ff, 0xc93c, 0x21, 0 - .dw 0x8a40, 0xc93c, 0x8a7f, 0xc93c, 0x21, 0 - .dw 0x8ac0, 0xc93c, 0x8aff, 0xc93c, 0x21, 0 - .dw 0x8b40, 0xc93c, 0x8b7f, 0xc93c, 0x21, 0 - .dw 0x8bc0, 0xc93c, 0x8bff, 0xc93c, 0x21, 0 - .dw 0x8c40, 0xc93c, 0x8c7f, 0xc93c, 0x21, 0 - .dw 0x8cc0, 0xc93c, 0x8cff, 0xc93c, 0x21, 0 - .dw 0x8d40, 0xc93c, 0x8d7f, 0xc93c, 0x21, 0 - .dw 0x8dc0, 0xc93c, 0x8dff, 0xc93c, 0x21, 0 - .dw 0x8e40, 0xc93c, 0x8e7f, 0xc93c, 0x21, 0 - .dw 0x8ec0, 0xc93c, 0x8eff, 0xc93c, 0x21, 0 - .dw 0x8f40, 0xc93c, 0x8f7f, 0xc93c, 0x21, 0 - .dw 0x8fc0, 0xc93c, 0x8fff, 0xc93c, 0x21, 0 - .dw 0x9040, 0xc93c, 0x907f, 0xc93c, 0x21, 0 - .dw 0x90c0, 0xc93c, 0x90ff, 0xc93c, 0x21, 0 - .dw 0x9140, 0xc93c, 0x917f, 0xc93c, 0x21, 0 - .dw 0x91c0, 0xc93c, 0x91ff, 0xc93c, 0x21, 0 - .dw 0x9240, 0xc93c, 0x927f, 0xc93c, 0x21, 0 - .dw 0x92c0, 0xc93c, 0x92ff, 0xc93c, 0x21, 0 - .dw 0x9340, 0xc93c, 0x937f, 0xc93c, 0x21, 0 - .dw 0x93c0, 0xc93c, 0x93ff, 0xc93c, 0x21, 0 - .dw 0x9440, 0xc93c, 0x947f, 0xc93c, 0x21, 0 - .dw 0x94c0, 0xc93c, 0x94ff, 0xc93c, 0x21, 0 - .dw 0x9540, 0xc93c, 0x957f, 0xc93c, 0x21, 0 - .dw 0x95c0, 0xc93c, 0x95ff, 0xc93c, 0x21, 0 - .dw 0x9640, 0xc93c, 0x967f, 0xc93c, 0x21, 0 - .dw 0x96c0, 0xc93c, 0x96ff, 0xc93c, 0x21, 0 - .dw 0x9740, 0xc93c, 0x977f, 0xc93c, 0x21, 0 - .dw 0x97c0, 0xc93c, 0x97ff, 0xc93c, 0x21, 0 - .dw 0x9840, 0xc93c, 0x987f, 0xc93c, 0x21, 0 - .dw 0x98c0, 0xc93c, 0x98ff, 0xc93c, 0x21, 0 - .dw 0x9940, 0xc93c, 0x997f, 0xc93c, 0x21, 0 - .dw 0x99c0, 0xc93c, 0x9fff, 0xc93c, 0x21, 0 - .dw 0xa040, 0xc93c, 0xa07f, 0xc93c, 0x21, 0 - .dw 0xa0c0, 0xc93c, 0xa0ff, 0xc93c, 0x21, 0 - .dw 0xa140, 0xc93c, 0xa17f, 0xc93c, 0x21, 0 - .dw 0xa1c0, 0xc93c, 0xa1ff, 0xc93c, 0x21, 0 - .dw 0xa240, 0xc93c, 0xa27f, 0xc93c, 0x21, 0 - .dw 0xa2c0, 0xc93c, 0xa2ff, 0xc93c, 0x21, 0 - .dw 0xa340, 0xc93c, 0xa37f, 0xc93c, 0x21, 0 - .dw 0xa3c0, 0xc93c, 0xa3ff, 0xc93c, 0x21, 0 - .dw 0xa440, 0xc93c, 0xa47f, 0xc93c, 0x21, 0 - .dw 0xa4c0, 0xc93c, 0xa4ff, 0xc93c, 0x21, 0 - .dw 0xa540, 0xc93c, 0xa57f, 0xc93c, 0x21, 0 - .dw 0xa5c0, 0xc93c, 0xa5ff, 0xc93c, 0x21, 0 - .dw 0xa640, 0xc93c, 0xa67f, 0xc93c, 0x21, 0 - .dw 0xa6c0, 0xc93c, 0xa6ff, 0xc93c, 0x21, 0 - .dw 0xa740, 0xc93c, 0xa77f, 0xc93c, 0x21, 0 - .dw 0xa7c0, 0xc93c, 0xa7ff, 0xc93c, 0x21, 0 - .dw 0xa840, 0xc93c, 0xa87f, 0xc93c, 0x21, 0 - .dw 0xa8c0, 0xc93c, 0xa8ff, 0xc93c, 0x21, 0 - .dw 0xa940, 0xc93c, 0xa97f, 0xc93c, 0x21, 0 - .dw 0xa9c0, 0xc93c, 0xa9ff, 0xc93c, 0x21, 0 - .dw 0xaa40, 0xc93c, 0xaa7f, 0xc93c, 0x21, 0 - .dw 0xaac0, 0xc93c, 0xaaff, 0xc93c, 0x21, 0 - .dw 0xab40, 0xc93c, 0xab7f, 0xc93c, 0x21, 0 - .dw 0xabc0, 0xc93c, 0xabff, 0xc93c, 0x21, 0 - .dw 0xac40, 0xc93c, 0xac7f, 0xc93c, 0x21, 0 - .dw 0xacc0, 0xc93c, 0xacff, 0xc93c, 0x21, 0 - .dw 0xad40, 0xc93c, 0xad7f, 0xc93c, 0x21, 0 - .dw 0xadc0, 0xc93c, 0xadff, 0xc93c, 0x21, 0 - .dw 0xae40, 0xc93c, 0xae7f, 0xc93c, 0x21, 0 - .dw 0xaec0, 0xc93c, 0xaeff, 0xc93c, 0x21, 0 - .dw 0xaf40, 0xc93c, 0xaf7f, 0xc93c, 0x21, 0 - .dw 0xafc0, 0xc93c, 0xafff, 0xc93c, 0x21, 0 - .dw 0xb040, 0xc93c, 0xb07f, 0xc93c, 0x21, 0 - .dw 0xb0c0, 0xc93c, 0xb0ff, 0xc93c, 0x21, 0 - .dw 0xb140, 0xc93c, 0xb17f, 0xc93c, 0x21, 0 - .dw 0xb1c0, 0xc93c, 0xb1ff, 0xc93c, 0x21, 0 - .dw 0xb240, 0xc93c, 0xb27f, 0xc93c, 0x21, 0 - .dw 0xb2c0, 0xc93c, 0xb2ff, 0xc93c, 0x21, 0 - .dw 0xb340, 0xc93c, 0xb37f, 0xc93c, 0x21, 0 - .dw 0xb3c0, 0xc93c, 0xb3ff, 0xc93c, 0x21, 0 - .dw 0xb440, 0xc93c, 0xb47f, 0xc93c, 0x21, 0 - .dw 0xb4c0, 0xc93c, 0xb4ff, 0xc93c, 0x21, 0 - .dw 0xb540, 0xc93c, 0xb57f, 0xc93c, 0x21, 0 - .dw 0xb5c0, 0xc93c, 0xb5ff, 0xc93c, 0x21, 0 - .dw 0xb640, 0xc93c, 0xb67f, 0xc93c, 0x21, 0 - .dw 0xb6c0, 0xc93c, 0xb6ff, 0xc93c, 0x21, 0 - .dw 0xb740, 0xc93c, 0xb77f, 0xc93c, 0x21, 0 - .dw 0xb7c0, 0xc93c, 0xb7ff, 0xc93c, 0x21, 0 - .dw 0xb840, 0xc93c, 0xb87f, 0xc93c, 0x21, 0 - .dw 0xb8c0, 0xc93c, 0xb8ff, 0xc93c, 0x21, 0 - .dw 0xb940, 0xc93c, 0xb97f, 0xc93c, 0x21, 0 - .dw 0xb9c0, 0xc93c, 0xbfff, 0xc93c, 0x21, 0 - .dw 0xc040, 0xc93c, 0xc07f, 0xc93c, 0x21, 0 - .dw 0xc0c0, 0xc93c, 0xc0ff, 0xc93c, 0x21, 0 - .dw 0xc140, 0xc93c, 0xc17f, 0xc93c, 0x21, 0 - .dw 0xc1c0, 0xc93c, 0xc1ff, 0xc93c, 0x21, 0 - .dw 0xc240, 0xc93c, 0xc27f, 0xc93c, 0x21, 0 - .dw 0xc2c0, 0xc93c, 0xc2ff, 0xc93c, 0x21, 0 - .dw 0xc340, 0xc93c, 0xc37f, 0xc93c, 0x21, 0 - .dw 0xc3c0, 0xc93c, 0xc3ff, 0xc93c, 0x21, 0 - .dw 0xc440, 0xc93c, 0xc47f, 0xc93c, 0x21, 0 - .dw 0xc4c0, 0xc93c, 0xc4ff, 0xc93c, 0x21, 0 - .dw 0xc540, 0xc93c, 0xc57f, 0xc93c, 0x21, 0 - .dw 0xc5c0, 0xc93c, 0xc5ff, 0xc93c, 0x21, 0 - .dw 0xc640, 0xc93c, 0xc67f, 0xc93c, 0x21, 0 - .dw 0xc6c0, 0xc93c, 0xc6ff, 0xc93c, 0x21, 0 - .dw 0xc740, 0xc93c, 0xc77f, 0xc93c, 0x21, 0 - .dw 0xc7c0, 0xc93c, 0xc7ff, 0xc93c, 0x21, 0 - .dw 0xc840, 0xc93c, 0xc87f, 0xc93c, 0x21, 0 - .dw 0xc8c0, 0xc93c, 0xc8ff, 0xc93c, 0x21, 0 - .dw 0xc940, 0xc93c, 0xc97f, 0xc93c, 0x21, 0 - .dw 0xc9c0, 0xc93c, 0xc9ff, 0xc93c, 0x21, 0 - .dw 0xca40, 0xc93c, 0xca7f, 0xc93c, 0x21, 0 - .dw 0xcac0, 0xc93c, 0xcaff, 0xc93c, 0x21, 0 - .dw 0xcb40, 0xc93c, 0xcb7f, 0xc93c, 0x21, 0 - .dw 0xcbc0, 0xc93c, 0xcbff, 0xc93c, 0x21, 0 - .dw 0xcc40, 0xc93c, 0xcc7f, 0xc93c, 0x21, 0 - .dw 0xccc0, 0xc93c, 0xccff, 0xc93c, 0x21, 0 - .dw 0xcd40, 0xc93c, 0xcd7f, 0xc93c, 0x21, 0 - .dw 0xcdc0, 0xc93c, 0xcdff, 0xc93c, 0x21, 0 - .dw 0xce40, 0xc93c, 0xce7f, 0xc93c, 0x21, 0 - .dw 0xcec0, 0xc93c, 0xceff, 0xc93c, 0x21, 0 - .dw 0xcf40, 0xc93c, 0xcf7f, 0xc93c, 0x21, 0 - .dw 0xcfc0, 0xc93c, 0xcfff, 0xc93c, 0x21, 0 - .dw 0xd040, 0xc93c, 0xd07f, 0xc93c, 0x21, 0 - .dw 0xd0c0, 0xc93c, 0xd0ff, 0xc93c, 0x21, 0 - .dw 0xd140, 0xc93c, 0xd17f, 0xc93c, 0x21, 0 - .dw 0xd1c0, 0xc93c, 0xd1ff, 0xc93c, 0x21, 0 - .dw 0xd240, 0xc93c, 0xd27f, 0xc93c, 0x21, 0 - .dw 0xd2c0, 0xc93c, 0xd2ff, 0xc93c, 0x21, 0 - .dw 0xd340, 0xc93c, 0xd37f, 0xc93c, 0x21, 0 - .dw 0xd3c0, 0xc93c, 0xd3ff, 0xc93c, 0x21, 0 - .dw 0xd440, 0xc93c, 0xd47f, 0xc93c, 0x21, 0 - .dw 0xd4c0, 0xc93c, 0xd4ff, 0xc93c, 0x21, 0 - .dw 0xd540, 0xc93c, 0xd57f, 0xc93c, 0x21, 0 - .dw 0xd5c0, 0xc93c, 0xd5ff, 0xc93c, 0x21, 0 - .dw 0xd640, 0xc93c, 0xd67f, 0xc93c, 0x21, 0 - .dw 0xd6c0, 0xc93c, 0xd6ff, 0xc93c, 0x21, 0 - .dw 0xd740, 0xc93c, 0xd77f, 0xc93c, 0x21, 0 - .dw 0xd7c0, 0xc93c, 0xd7ff, 0xc93c, 0x21, 0 - .dw 0xd840, 0xc93c, 0xd87f, 0xc93c, 0x21, 0 - .dw 0xd8c0, 0xc93c, 0xd8ff, 0xc93c, 0x21, 0 - .dw 0xd940, 0xc93c, 0xd97f, 0xc93c, 0x21, 0 - .dw 0xd9c0, 0xc93c, 0xdfff, 0xc93c, 0x21, 0 - .dw 0xe040, 0xc93c, 0xe07f, 0xc93c, 0x21, 0 - .dw 0xe0c0, 0xc93c, 0xe0ff, 0xc93c, 0x21, 0 - .dw 0xe140, 0xc93c, 0xe17f, 0xc93c, 0x21, 0 - .dw 0xe1c0, 0xc93c, 0xe1ff, 0xc93c, 0x21, 0 - .dw 0xe240, 0xc93c, 0xe27f, 0xc93c, 0x21, 0 - .dw 0xe2c0, 0xc93c, 0xe2ff, 0xc93c, 0x21, 0 - .dw 0xe340, 0xc93c, 0xe37f, 0xc93c, 0x21, 0 - .dw 0xe3c0, 0xc93c, 0xe3ff, 0xc93c, 0x21, 0 - .dw 0xe440, 0xc93c, 0xe47f, 0xc93c, 0x21, 0 - .dw 0xe4c0, 0xc93c, 0xe4ff, 0xc93c, 0x21, 0 - .dw 0xe540, 0xc93c, 0xe57f, 0xc93c, 0x21, 0 - .dw 0xe5c0, 0xc93c, 0xe5ff, 0xc93c, 0x21, 0 - .dw 0xe640, 0xc93c, 0xe67f, 0xc93c, 0x21, 0 - .dw 0xe6c0, 0xc93c, 0xe6ff, 0xc93c, 0x21, 0 - .dw 0xe740, 0xc93c, 0xe77f, 0xc93c, 0x21, 0 - .dw 0xe7c0, 0xc93c, 0xe7ff, 0xc93c, 0x21, 0 - .dw 0xe840, 0xc93c, 0xe87f, 0xc93c, 0x21, 0 - .dw 0xe8c0, 0xc93c, 0xe8ff, 0xc93c, 0x21, 0 - .dw 0xe940, 0xc93c, 0xe97f, 0xc93c, 0x21, 0 - .dw 0xe9c0, 0xc93c, 0xe9ff, 0xc93c, 0x21, 0 - .dw 0xea40, 0xc93c, 0xea7f, 0xc93c, 0x21, 0 - .dw 0xeac0, 0xc93c, 0xeaff, 0xc93c, 0x21, 0 - .dw 0xeb40, 0xc93c, 0xeb7f, 0xc93c, 0x21, 0 - .dw 0xebc0, 0xc93c, 0xebff, 0xc93c, 0x21, 0 - .dw 0xec40, 0xc93c, 0xec7f, 0xc93c, 0x21, 0 - .dw 0xecc0, 0xc93c, 0xecff, 0xc93c, 0x21, 0 - .dw 0xed40, 0xc93c, 0xed7f, 0xc93c, 0x21, 0 - .dw 0xedc0, 0xc93c, 0xedff, 0xc93c, 0x21, 0 - .dw 0xee40, 0xc93c, 0xee7f, 0xc93c, 0x21, 0 - .dw 0xeec0, 0xc93c, 0xeeff, 0xc93c, 0x21, 0 - .dw 0xef40, 0xc93c, 0xef7f, 0xc93c, 0x21, 0 - .dw 0xefc0, 0xc93c, 0xefff, 0xc93c, 0x21, 0 - .dw 0xf040, 0xc93c, 0xf07f, 0xc93c, 0x21, 0 - .dw 0xf0c0, 0xc93c, 0xf0ff, 0xc93c, 0x21, 0 - .dw 0xf140, 0xc93c, 0xf17f, 0xc93c, 0x21, 0 - .dw 0xf1c0, 0xc93c, 0xf1ff, 0xc93c, 0x21, 0 - .dw 0xf240, 0xc93c, 0xf27f, 0xc93c, 0x21, 0 - .dw 0xf2c0, 0xc93c, 0xf2ff, 0xc93c, 0x21, 0 - .dw 0xf340, 0xc93c, 0xf37f, 0xc93c, 0x21, 0 - .dw 0xf3c0, 0xc93c, 0xf3ff, 0xc93c, 0x21, 0 - .dw 0xf440, 0xc93c, 0xf47f, 0xc93c, 0x21, 0 - .dw 0xf4c0, 0xc93c, 0xf4ff, 0xc93c, 0x21, 0 - .dw 0xf540, 0xc93c, 0xf57f, 0xc93c, 0x21, 0 - .dw 0xf5c0, 0xc93c, 0xf5ff, 0xc93c, 0x21, 0 - .dw 0xf640, 0xc93c, 0xf67f, 0xc93c, 0x21, 0 - .dw 0xf6c0, 0xc93c, 0xf6ff, 0xc93c, 0x21, 0 - .dw 0xf740, 0xc93c, 0xf77f, 0xc93c, 0x21, 0 - .dw 0xf7c0, 0xc93c, 0xf7ff, 0xc93c, 0x21, 0 - .dw 0xf840, 0xc93c, 0xf87f, 0xc93c, 0x21, 0 - .dw 0xf8c0, 0xc93c, 0xf8ff, 0xc93c, 0x21, 0 - .dw 0xf940, 0xc93c, 0xf97f, 0xc93c, 0x21, 0 - .dw 0xf9c0, 0xc93c, 0xffff, 0xc93c, 0x21, 0 - .dw 0x0040, 0xc93d, 0x007f, 0xc93d, 0x21, 0 - .dw 0x00c0, 0xc93d, 0x00ff, 0xc93d, 0x21, 0 - .dw 0x0140, 0xc93d, 0x017f, 0xc93d, 0x21, 0 - .dw 0x01c0, 0xc93d, 0x01ff, 0xc93d, 0x21, 0 - .dw 0x0240, 0xc93d, 0x027f, 0xc93d, 0x21, 0 - .dw 0x02c0, 0xc93d, 0x02ff, 0xc93d, 0x21, 0 - .dw 0x0340, 0xc93d, 0x037f, 0xc93d, 0x21, 0 - .dw 0x03c0, 0xc93d, 0x03ff, 0xc93d, 0x21, 0 - .dw 0x0440, 0xc93d, 0x047f, 0xc93d, 0x21, 0 - .dw 0x04c0, 0xc93d, 0x04ff, 0xc93d, 0x21, 0 - .dw 0x0540, 0xc93d, 0x057f, 0xc93d, 0x21, 0 - .dw 0x05c0, 0xc93d, 0x05ff, 0xc93d, 0x21, 0 - .dw 0x0640, 0xc93d, 0x067f, 0xc93d, 0x21, 0 - .dw 0x06c0, 0xc93d, 0x06ff, 0xc93d, 0x21, 0 - .dw 0x0740, 0xc93d, 0x077f, 0xc93d, 0x21, 0 - .dw 0x07c0, 0xc93d, 0x07ff, 0xc93d, 0x21, 0 - .dw 0x0840, 0xc93d, 0x087f, 0xc93d, 0x21, 0 - .dw 0x08c0, 0xc93d, 0x08ff, 0xc93d, 0x21, 0 - .dw 0x0940, 0xc93d, 0x097f, 0xc93d, 0x21, 0 - .dw 0x09c0, 0xc93d, 0x09ff, 0xc93d, 0x21, 0 - .dw 0x0a40, 0xc93d, 0x0a7f, 0xc93d, 0x21, 0 - .dw 0x0ac0, 0xc93d, 0x0aff, 0xc93d, 0x21, 0 - .dw 0x0b40, 0xc93d, 0x0b7f, 0xc93d, 0x21, 0 - .dw 0x0bc0, 0xc93d, 0x0bff, 0xc93d, 0x21, 0 - .dw 0x0c40, 0xc93d, 0x0c7f, 0xc93d, 0x21, 0 - .dw 0x0cc0, 0xc93d, 0x0cff, 0xc93d, 0x21, 0 - .dw 0x0d40, 0xc93d, 0x0d7f, 0xc93d, 0x21, 0 - .dw 0x0dc0, 0xc93d, 0x0dff, 0xc93d, 0x21, 0 - .dw 0x0e40, 0xc93d, 0x0e7f, 0xc93d, 0x21, 0 - .dw 0x0ec0, 0xc93d, 0x0eff, 0xc93d, 0x21, 0 - .dw 0x0f40, 0xc93d, 0x0f7f, 0xc93d, 0x21, 0 - .dw 0x0fc0, 0xc93d, 0x0fff, 0xc93d, 0x21, 0 - .dw 0x1040, 0xc93d, 0x107f, 0xc93d, 0x21, 0 - .dw 0x10c0, 0xc93d, 0x10ff, 0xc93d, 0x21, 0 - .dw 0x1140, 0xc93d, 0x117f, 0xc93d, 0x21, 0 - .dw 0x11c0, 0xc93d, 0x11ff, 0xc93d, 0x21, 0 - .dw 0x1240, 0xc93d, 0x127f, 0xc93d, 0x21, 0 - .dw 0x12c0, 0xc93d, 0x12ff, 0xc93d, 0x21, 0 - .dw 0x1340, 0xc93d, 0x137f, 0xc93d, 0x21, 0 - .dw 0x13c0, 0xc93d, 0x13ff, 0xc93d, 0x21, 0 - .dw 0x1440, 0xc93d, 0x147f, 0xc93d, 0x21, 0 - .dw 0x14c0, 0xc93d, 0x14ff, 0xc93d, 0x21, 0 - .dw 0x1540, 0xc93d, 0x157f, 0xc93d, 0x21, 0 - .dw 0x15c0, 0xc93d, 0x15ff, 0xc93d, 0x21, 0 - .dw 0x1640, 0xc93d, 0x167f, 0xc93d, 0x21, 0 - .dw 0x16c0, 0xc93d, 0x16ff, 0xc93d, 0x21, 0 - .dw 0x1740, 0xc93d, 0x177f, 0xc93d, 0x21, 0 - .dw 0x17c0, 0xc93d, 0x17ff, 0xc93d, 0x21, 0 - .dw 0x1840, 0xc93d, 0x187f, 0xc93d, 0x21, 0 - .dw 0x18c0, 0xc93d, 0x18ff, 0xc93d, 0x21, 0 - .dw 0x1940, 0xc93d, 0x197f, 0xc93d, 0x21, 0 - .dw 0x19c0, 0xc93d, 0x1fff, 0xc93d, 0x21, 0 - .dw 0x2040, 0xc93d, 0x207f, 0xc93d, 0x21, 0 - .dw 0x20c0, 0xc93d, 0x20ff, 0xc93d, 0x21, 0 - .dw 0x2140, 0xc93d, 0x217f, 0xc93d, 0x21, 0 - .dw 0x21c0, 0xc93d, 0x21ff, 0xc93d, 0x21, 0 - .dw 0x2240, 0xc93d, 0x227f, 0xc93d, 0x21, 0 - .dw 0x22c0, 0xc93d, 0x22ff, 0xc93d, 0x21, 0 - .dw 0x2340, 0xc93d, 0x237f, 0xc93d, 0x21, 0 - .dw 0x23c0, 0xc93d, 0x23ff, 0xc93d, 0x21, 0 - .dw 0x2440, 0xc93d, 0x247f, 0xc93d, 0x21, 0 - .dw 0x24c0, 0xc93d, 0x24ff, 0xc93d, 0x21, 0 - .dw 0x2540, 0xc93d, 0x257f, 0xc93d, 0x21, 0 - .dw 0x25c0, 0xc93d, 0x25ff, 0xc93d, 0x21, 0 - .dw 0x2640, 0xc93d, 0x267f, 0xc93d, 0x21, 0 - .dw 0x26c0, 0xc93d, 0x26ff, 0xc93d, 0x21, 0 - .dw 0x2740, 0xc93d, 0x277f, 0xc93d, 0x21, 0 - .dw 0x27c0, 0xc93d, 0x27ff, 0xc93d, 0x21, 0 - .dw 0x2840, 0xc93d, 0x287f, 0xc93d, 0x21, 0 - .dw 0x28c0, 0xc93d, 0x28ff, 0xc93d, 0x21, 0 - .dw 0x2940, 0xc93d, 0x297f, 0xc93d, 0x21, 0 - .dw 0x29c0, 0xc93d, 0x29ff, 0xc93d, 0x21, 0 - .dw 0x2a40, 0xc93d, 0x2a7f, 0xc93d, 0x21, 0 - .dw 0x2ac0, 0xc93d, 0x2aff, 0xc93d, 0x21, 0 - .dw 0x2b40, 0xc93d, 0x2b7f, 0xc93d, 0x21, 0 - .dw 0x2bc0, 0xc93d, 0x2bff, 0xc93d, 0x21, 0 - .dw 0x2c40, 0xc93d, 0x2c7f, 0xc93d, 0x21, 0 - .dw 0x2cc0, 0xc93d, 0x2cff, 0xc93d, 0x21, 0 - .dw 0x2d40, 0xc93d, 0x2d7f, 0xc93d, 0x21, 0 - .dw 0x2dc0, 0xc93d, 0x2dff, 0xc93d, 0x21, 0 - .dw 0x2e40, 0xc93d, 0x2e7f, 0xc93d, 0x21, 0 - .dw 0x2ec0, 0xc93d, 0x2eff, 0xc93d, 0x21, 0 - .dw 0x2f40, 0xc93d, 0x2f7f, 0xc93d, 0x21, 0 - .dw 0x2fc0, 0xc93d, 0x2fff, 0xc93d, 0x21, 0 - .dw 0x3040, 0xc93d, 0x307f, 0xc93d, 0x21, 0 - .dw 0x30c0, 0xc93d, 0x30ff, 0xc93d, 0x21, 0 - .dw 0x3140, 0xc93d, 0x317f, 0xc93d, 0x21, 0 - .dw 0x31c0, 0xc93d, 0x31ff, 0xc93d, 0x21, 0 - .dw 0x3240, 0xc93d, 0x327f, 0xc93d, 0x21, 0 - .dw 0x32c0, 0xc93d, 0x32ff, 0xc93d, 0x21, 0 - .dw 0x3340, 0xc93d, 0x337f, 0xc93d, 0x21, 0 - .dw 0x33c0, 0xc93d, 0x33ff, 0xc93d, 0x21, 0 - .dw 0x3440, 0xc93d, 0x347f, 0xc93d, 0x21, 0 - .dw 0x34c0, 0xc93d, 0x34ff, 0xc93d, 0x21, 0 - .dw 0x3540, 0xc93d, 0x357f, 0xc93d, 0x21, 0 - .dw 0x35c0, 0xc93d, 0x35ff, 0xc93d, 0x21, 0 - .dw 0x3640, 0xc93d, 0x367f, 0xc93d, 0x21, 0 - .dw 0x36c0, 0xc93d, 0x36ff, 0xc93d, 0x21, 0 - .dw 0x3740, 0xc93d, 0x377f, 0xc93d, 0x21, 0 - .dw 0x37c0, 0xc93d, 0x37ff, 0xc93d, 0x21, 0 - .dw 0x3840, 0xc93d, 0x387f, 0xc93d, 0x21, 0 - .dw 0x38c0, 0xc93d, 0x38ff, 0xc93d, 0x21, 0 - .dw 0x3940, 0xc93d, 0x397f, 0xc93d, 0x21, 0 - .dw 0x39c0, 0xc93d, 0x3fff, 0xc93d, 0x21, 0 - .dw 0x4040, 0xc93d, 0x407f, 0xc93d, 0x21, 0 - .dw 0x40c0, 0xc93d, 0x40ff, 0xc93d, 0x21, 0 - .dw 0x4140, 0xc93d, 0x417f, 0xc93d, 0x21, 0 - .dw 0x41c0, 0xc93d, 0x41ff, 0xc93d, 0x21, 0 - .dw 0x4240, 0xc93d, 0x427f, 0xc93d, 0x21, 0 - .dw 0x42c0, 0xc93d, 0x42ff, 0xc93d, 0x21, 0 - .dw 0x4340, 0xc93d, 0x437f, 0xc93d, 0x21, 0 - .dw 0x43c0, 0xc93d, 0x43ff, 0xc93d, 0x21, 0 - .dw 0x4440, 0xc93d, 0x447f, 0xc93d, 0x21, 0 - .dw 0x44c0, 0xc93d, 0x44ff, 0xc93d, 0x21, 0 - .dw 0x4540, 0xc93d, 0x457f, 0xc93d, 0x21, 0 - .dw 0x45c0, 0xc93d, 0x45ff, 0xc93d, 0x21, 0 - .dw 0x4640, 0xc93d, 0x467f, 0xc93d, 0x21, 0 - .dw 0x46c0, 0xc93d, 0x46ff, 0xc93d, 0x21, 0 - .dw 0x4740, 0xc93d, 0x477f, 0xc93d, 0x21, 0 - .dw 0x47c0, 0xc93d, 0x47ff, 0xc93d, 0x21, 0 - .dw 0x4840, 0xc93d, 0x487f, 0xc93d, 0x21, 0 - .dw 0x48c0, 0xc93d, 0x48ff, 0xc93d, 0x21, 0 - .dw 0x4940, 0xc93d, 0x497f, 0xc93d, 0x21, 0 - .dw 0x49c0, 0xc93d, 0x49ff, 0xc93d, 0x21, 0 - .dw 0x4a40, 0xc93d, 0x4a7f, 0xc93d, 0x21, 0 - .dw 0x4ac0, 0xc93d, 0x4aff, 0xc93d, 0x21, 0 - .dw 0x4b40, 0xc93d, 0x4b7f, 0xc93d, 0x21, 0 - .dw 0x4bc0, 0xc93d, 0x4bff, 0xc93d, 0x21, 0 - .dw 0x4c40, 0xc93d, 0x4c7f, 0xc93d, 0x21, 0 - .dw 0x4cc0, 0xc93d, 0x4cff, 0xc93d, 0x21, 0 - .dw 0x4d40, 0xc93d, 0x4d7f, 0xc93d, 0x21, 0 - .dw 0x4dc0, 0xc93d, 0x4dff, 0xc93d, 0x21, 0 - .dw 0x4e40, 0xc93d, 0x4e7f, 0xc93d, 0x21, 0 - .dw 0x4ec0, 0xc93d, 0x4eff, 0xc93d, 0x21, 0 - .dw 0x4f40, 0xc93d, 0x4f7f, 0xc93d, 0x21, 0 - .dw 0x4fc0, 0xc93d, 0x4fff, 0xc93d, 0x21, 0 - .dw 0x5040, 0xc93d, 0x507f, 0xc93d, 0x21, 0 - .dw 0x50c0, 0xc93d, 0x50ff, 0xc93d, 0x21, 0 - .dw 0x5140, 0xc93d, 0x517f, 0xc93d, 0x21, 0 - .dw 0x51c0, 0xc93d, 0x51ff, 0xc93d, 0x21, 0 - .dw 0x5240, 0xc93d, 0x527f, 0xc93d, 0x21, 0 - .dw 0x52c0, 0xc93d, 0x52ff, 0xc93d, 0x21, 0 - .dw 0x5340, 0xc93d, 0x537f, 0xc93d, 0x21, 0 - .dw 0x53c0, 0xc93d, 0x53ff, 0xc93d, 0x21, 0 - .dw 0x5440, 0xc93d, 0x547f, 0xc93d, 0x21, 0 - .dw 0x54c0, 0xc93d, 0x54ff, 0xc93d, 0x21, 0 - .dw 0x5540, 0xc93d, 0x557f, 0xc93d, 0x21, 0 - .dw 0x55c0, 0xc93d, 0x55ff, 0xc93d, 0x21, 0 - .dw 0x5640, 0xc93d, 0x567f, 0xc93d, 0x21, 0 - .dw 0x56c0, 0xc93d, 0x56ff, 0xc93d, 0x21, 0 - .dw 0x5740, 0xc93d, 0x577f, 0xc93d, 0x21, 0 - .dw 0x57c0, 0xc93d, 0x57ff, 0xc93d, 0x21, 0 - .dw 0x5840, 0xc93d, 0x587f, 0xc93d, 0x21, 0 - .dw 0x58c0, 0xc93d, 0x58ff, 0xc93d, 0x21, 0 - .dw 0x5940, 0xc93d, 0x597f, 0xc93d, 0x21, 0 - .dw 0x59c0, 0xc93d, 0x5fff, 0xc93d, 0x21, 0 - .dw 0x6040, 0xc93d, 0x607f, 0xc93d, 0x21, 0 - .dw 0x60c0, 0xc93d, 0x60ff, 0xc93d, 0x21, 0 - .dw 0x6140, 0xc93d, 0x617f, 0xc93d, 0x21, 0 - .dw 0x61c0, 0xc93d, 0x61ff, 0xc93d, 0x21, 0 - .dw 0x6240, 0xc93d, 0x627f, 0xc93d, 0x21, 0 - .dw 0x62c0, 0xc93d, 0x62ff, 0xc93d, 0x21, 0 - .dw 0x6340, 0xc93d, 0x637f, 0xc93d, 0x21, 0 - .dw 0x63c0, 0xc93d, 0x63ff, 0xc93d, 0x21, 0 - .dw 0x6440, 0xc93d, 0x647f, 0xc93d, 0x21, 0 - .dw 0x64c0, 0xc93d, 0x64ff, 0xc93d, 0x21, 0 - .dw 0x6540, 0xc93d, 0x657f, 0xc93d, 0x21, 0 - .dw 0x65c0, 0xc93d, 0x65ff, 0xc93d, 0x21, 0 - .dw 0x6640, 0xc93d, 0x667f, 0xc93d, 0x21, 0 - .dw 0x66c0, 0xc93d, 0x66ff, 0xc93d, 0x21, 0 - .dw 0x6740, 0xc93d, 0x677f, 0xc93d, 0x21, 0 - .dw 0x67c0, 0xc93d, 0x67ff, 0xc93d, 0x21, 0 - .dw 0x6840, 0xc93d, 0x687f, 0xc93d, 0x21, 0 - .dw 0x68c0, 0xc93d, 0x68ff, 0xc93d, 0x21, 0 - .dw 0x6940, 0xc93d, 0x697f, 0xc93d, 0x21, 0 - .dw 0x69c0, 0xc93d, 0x69ff, 0xc93d, 0x21, 0 - .dw 0x6a40, 0xc93d, 0x6a7f, 0xc93d, 0x21, 0 - .dw 0x6ac0, 0xc93d, 0x6aff, 0xc93d, 0x21, 0 - .dw 0x6b40, 0xc93d, 0x6b7f, 0xc93d, 0x21, 0 - .dw 0x6bc0, 0xc93d, 0x6bff, 0xc93d, 0x21, 0 - .dw 0x6c40, 0xc93d, 0x6c7f, 0xc93d, 0x21, 0 - .dw 0x6cc0, 0xc93d, 0x6cff, 0xc93d, 0x21, 0 - .dw 0x6d40, 0xc93d, 0x6d7f, 0xc93d, 0x21, 0 - .dw 0x6dc0, 0xc93d, 0x6dff, 0xc93d, 0x21, 0 - .dw 0x6e40, 0xc93d, 0x6e7f, 0xc93d, 0x21, 0 - .dw 0x6ec0, 0xc93d, 0x6eff, 0xc93d, 0x21, 0 - .dw 0x6f40, 0xc93d, 0x6f7f, 0xc93d, 0x21, 0 - .dw 0x6fc0, 0xc93d, 0x6fff, 0xc93d, 0x21, 0 - .dw 0x7040, 0xc93d, 0x707f, 0xc93d, 0x21, 0 - .dw 0x70c0, 0xc93d, 0x70ff, 0xc93d, 0x21, 0 - .dw 0x7140, 0xc93d, 0x717f, 0xc93d, 0x21, 0 - .dw 0x71c0, 0xc93d, 0x71ff, 0xc93d, 0x21, 0 - .dw 0x7240, 0xc93d, 0x727f, 0xc93d, 0x21, 0 - .dw 0x72c0, 0xc93d, 0x72ff, 0xc93d, 0x21, 0 - .dw 0x7340, 0xc93d, 0x737f, 0xc93d, 0x21, 0 - .dw 0x73c0, 0xc93d, 0x73ff, 0xc93d, 0x21, 0 - .dw 0x7440, 0xc93d, 0x747f, 0xc93d, 0x21, 0 - .dw 0x74c0, 0xc93d, 0x74ff, 0xc93d, 0x21, 0 - .dw 0x7540, 0xc93d, 0x757f, 0xc93d, 0x21, 0 - .dw 0x75c0, 0xc93d, 0x75ff, 0xc93d, 0x21, 0 - .dw 0x7640, 0xc93d, 0x767f, 0xc93d, 0x21, 0 - .dw 0x76c0, 0xc93d, 0x76ff, 0xc93d, 0x21, 0 - .dw 0x7740, 0xc93d, 0x777f, 0xc93d, 0x21, 0 - .dw 0x77c0, 0xc93d, 0x77ff, 0xc93d, 0x21, 0 - .dw 0x7840, 0xc93d, 0x787f, 0xc93d, 0x21, 0 - .dw 0x78c0, 0xc93d, 0x78ff, 0xc93d, 0x21, 0 - .dw 0x7940, 0xc93d, 0x797f, 0xc93d, 0x21, 0 - .dw 0x79c0, 0xc93d, 0x7fff, 0xc93d, 0x21, 0 - .dw 0x8040, 0xc93d, 0x807f, 0xc93d, 0x21, 0 - .dw 0x80c0, 0xc93d, 0x80ff, 0xc93d, 0x21, 0 - .dw 0x8140, 0xc93d, 0x817f, 0xc93d, 0x21, 0 - .dw 0x81c0, 0xc93d, 0x81ff, 0xc93d, 0x21, 0 - .dw 0x8240, 0xc93d, 0x827f, 0xc93d, 0x21, 0 - .dw 0x82c0, 0xc93d, 0x82ff, 0xc93d, 0x21, 0 - .dw 0x8340, 0xc93d, 0x837f, 0xc93d, 0x21, 0 - .dw 0x83c0, 0xc93d, 0x83ff, 0xc93d, 0x21, 0 - .dw 0x8440, 0xc93d, 0x847f, 0xc93d, 0x21, 0 - .dw 0x84c0, 0xc93d, 0x84ff, 0xc93d, 0x21, 0 - .dw 0x8540, 0xc93d, 0x857f, 0xc93d, 0x21, 0 - .dw 0x85c0, 0xc93d, 0x85ff, 0xc93d, 0x21, 0 - .dw 0x8640, 0xc93d, 0x867f, 0xc93d, 0x21, 0 - .dw 0x86c0, 0xc93d, 0x86ff, 0xc93d, 0x21, 0 - .dw 0x8740, 0xc93d, 0x877f, 0xc93d, 0x21, 0 - .dw 0x87c0, 0xc93d, 0x87ff, 0xc93d, 0x21, 0 - .dw 0x8840, 0xc93d, 0x887f, 0xc93d, 0x21, 0 - .dw 0x88c0, 0xc93d, 0x88ff, 0xc93d, 0x21, 0 - .dw 0x8940, 0xc93d, 0x897f, 0xc93d, 0x21, 0 - .dw 0x89c0, 0xc93d, 0x89ff, 0xc93d, 0x21, 0 - .dw 0x8a40, 0xc93d, 0x8a7f, 0xc93d, 0x21, 0 - .dw 0x8ac0, 0xc93d, 0x8aff, 0xc93d, 0x21, 0 - .dw 0x8b40, 0xc93d, 0x8b7f, 0xc93d, 0x21, 0 - .dw 0x8bc0, 0xc93d, 0x8bff, 0xc93d, 0x21, 0 - .dw 0x8c40, 0xc93d, 0x8c7f, 0xc93d, 0x21, 0 - .dw 0x8cc0, 0xc93d, 0x8cff, 0xc93d, 0x21, 0 - .dw 0x8d40, 0xc93d, 0x8d7f, 0xc93d, 0x21, 0 - .dw 0x8dc0, 0xc93d, 0x8dff, 0xc93d, 0x21, 0 - .dw 0x8e40, 0xc93d, 0x8e7f, 0xc93d, 0x21, 0 - .dw 0x8ec0, 0xc93d, 0x8eff, 0xc93d, 0x21, 0 - .dw 0x8f40, 0xc93d, 0x8f7f, 0xc93d, 0x21, 0 - .dw 0x8fc0, 0xc93d, 0x8fff, 0xc93d, 0x21, 0 - .dw 0x9040, 0xc93d, 0x907f, 0xc93d, 0x21, 0 - .dw 0x90c0, 0xc93d, 0x90ff, 0xc93d, 0x21, 0 - .dw 0x9140, 0xc93d, 0x917f, 0xc93d, 0x21, 0 - .dw 0x91c0, 0xc93d, 0x91ff, 0xc93d, 0x21, 0 - .dw 0x9240, 0xc93d, 0x927f, 0xc93d, 0x21, 0 - .dw 0x92c0, 0xc93d, 0x92ff, 0xc93d, 0x21, 0 - .dw 0x9340, 0xc93d, 0x937f, 0xc93d, 0x21, 0 - .dw 0x93c0, 0xc93d, 0x93ff, 0xc93d, 0x21, 0 - .dw 0x9440, 0xc93d, 0x947f, 0xc93d, 0x21, 0 - .dw 0x94c0, 0xc93d, 0x94ff, 0xc93d, 0x21, 0 - .dw 0x9540, 0xc93d, 0x957f, 0xc93d, 0x21, 0 - .dw 0x95c0, 0xc93d, 0x95ff, 0xc93d, 0x21, 0 - .dw 0x9640, 0xc93d, 0x967f, 0xc93d, 0x21, 0 - .dw 0x96c0, 0xc93d, 0x96ff, 0xc93d, 0x21, 0 - .dw 0x9740, 0xc93d, 0x977f, 0xc93d, 0x21, 0 - .dw 0x97c0, 0xc93d, 0x97ff, 0xc93d, 0x21, 0 - .dw 0x9840, 0xc93d, 0x987f, 0xc93d, 0x21, 0 - .dw 0x98c0, 0xc93d, 0x98ff, 0xc93d, 0x21, 0 - .dw 0x9940, 0xc93d, 0x997f, 0xc93d, 0x21, 0 - .dw 0x99c0, 0xc93d, 0x9fff, 0xc93d, 0x21, 0 - .dw 0xa040, 0xc93d, 0xa07f, 0xc93d, 0x21, 0 - .dw 0xa0c0, 0xc93d, 0xa0ff, 0xc93d, 0x21, 0 - .dw 0xa140, 0xc93d, 0xa17f, 0xc93d, 0x21, 0 - .dw 0xa1c0, 0xc93d, 0xa1ff, 0xc93d, 0x21, 0 - .dw 0xa240, 0xc93d, 0xa27f, 0xc93d, 0x21, 0 - .dw 0xa2c0, 0xc93d, 0xa2ff, 0xc93d, 0x21, 0 - .dw 0xa340, 0xc93d, 0xa37f, 0xc93d, 0x21, 0 - .dw 0xa3c0, 0xc93d, 0xa3ff, 0xc93d, 0x21, 0 - .dw 0xa440, 0xc93d, 0xa47f, 0xc93d, 0x21, 0 - .dw 0xa4c0, 0xc93d, 0xa4ff, 0xc93d, 0x21, 0 - .dw 0xa540, 0xc93d, 0xa57f, 0xc93d, 0x21, 0 - .dw 0xa5c0, 0xc93d, 0xa5ff, 0xc93d, 0x21, 0 - .dw 0xa640, 0xc93d, 0xa67f, 0xc93d, 0x21, 0 - .dw 0xa6c0, 0xc93d, 0xa6ff, 0xc93d, 0x21, 0 - .dw 0xa740, 0xc93d, 0xa77f, 0xc93d, 0x21, 0 - .dw 0xa7c0, 0xc93d, 0xa7ff, 0xc93d, 0x21, 0 - .dw 0xa840, 0xc93d, 0xa87f, 0xc93d, 0x21, 0 - .dw 0xa8c0, 0xc93d, 0xa8ff, 0xc93d, 0x21, 0 - .dw 0xa940, 0xc93d, 0xa97f, 0xc93d, 0x21, 0 - .dw 0xa9c0, 0xc93d, 0xa9ff, 0xc93d, 0x21, 0 - .dw 0xaa40, 0xc93d, 0xaa7f, 0xc93d, 0x21, 0 - .dw 0xaac0, 0xc93d, 0xaaff, 0xc93d, 0x21, 0 - .dw 0xab40, 0xc93d, 0xab7f, 0xc93d, 0x21, 0 - .dw 0xabc0, 0xc93d, 0xabff, 0xc93d, 0x21, 0 - .dw 0xac40, 0xc93d, 0xac7f, 0xc93d, 0x21, 0 - .dw 0xacc0, 0xc93d, 0xacff, 0xc93d, 0x21, 0 - .dw 0xad40, 0xc93d, 0xad7f, 0xc93d, 0x21, 0 - .dw 0xadc0, 0xc93d, 0xadff, 0xc93d, 0x21, 0 - .dw 0xae40, 0xc93d, 0xae7f, 0xc93d, 0x21, 0 - .dw 0xaec0, 0xc93d, 0xaeff, 0xc93d, 0x21, 0 - .dw 0xaf40, 0xc93d, 0xaf7f, 0xc93d, 0x21, 0 - .dw 0xafc0, 0xc93d, 0xafff, 0xc93d, 0x21, 0 - .dw 0xb040, 0xc93d, 0xb07f, 0xc93d, 0x21, 0 - .dw 0xb0c0, 0xc93d, 0xb0ff, 0xc93d, 0x21, 0 - .dw 0xb140, 0xc93d, 0xb17f, 0xc93d, 0x21, 0 - .dw 0xb1c0, 0xc93d, 0xb1ff, 0xc93d, 0x21, 0 - .dw 0xb240, 0xc93d, 0xb27f, 0xc93d, 0x21, 0 - .dw 0xb2c0, 0xc93d, 0xb2ff, 0xc93d, 0x21, 0 - .dw 0xb340, 0xc93d, 0xb37f, 0xc93d, 0x21, 0 - .dw 0xb3c0, 0xc93d, 0xb3ff, 0xc93d, 0x21, 0 - .dw 0xb440, 0xc93d, 0xb47f, 0xc93d, 0x21, 0 - .dw 0xb4c0, 0xc93d, 0xb4ff, 0xc93d, 0x21, 0 - .dw 0xb540, 0xc93d, 0xb57f, 0xc93d, 0x21, 0 - .dw 0xb5c0, 0xc93d, 0xb5ff, 0xc93d, 0x21, 0 - .dw 0xb640, 0xc93d, 0xb67f, 0xc93d, 0x21, 0 - .dw 0xb6c0, 0xc93d, 0xb6ff, 0xc93d, 0x21, 0 - .dw 0xb740, 0xc93d, 0xb77f, 0xc93d, 0x21, 0 - .dw 0xb7c0, 0xc93d, 0xb7ff, 0xc93d, 0x21, 0 - .dw 0xb840, 0xc93d, 0xb87f, 0xc93d, 0x21, 0 - .dw 0xb8c0, 0xc93d, 0xb8ff, 0xc93d, 0x21, 0 - .dw 0xb940, 0xc93d, 0xb97f, 0xc93d, 0x21, 0 - .dw 0xb9c0, 0xc93d, 0xbfff, 0xc93d, 0x21, 0 - .dw 0xc040, 0xc93d, 0xc07f, 0xc93d, 0x21, 0 - .dw 0xc0c0, 0xc93d, 0xc0ff, 0xc93d, 0x21, 0 - .dw 0xc140, 0xc93d, 0xc17f, 0xc93d, 0x21, 0 - .dw 0xc1c0, 0xc93d, 0xc1ff, 0xc93d, 0x21, 0 - .dw 0xc240, 0xc93d, 0xc27f, 0xc93d, 0x21, 0 - .dw 0xc2c0, 0xc93d, 0xc2ff, 0xc93d, 0x21, 0 - .dw 0xc340, 0xc93d, 0xc37f, 0xc93d, 0x21, 0 - .dw 0xc3c0, 0xc93d, 0xc3ff, 0xc93d, 0x21, 0 - .dw 0xc440, 0xc93d, 0xc47f, 0xc93d, 0x21, 0 - .dw 0xc4c0, 0xc93d, 0xc4ff, 0xc93d, 0x21, 0 - .dw 0xc540, 0xc93d, 0xc57f, 0xc93d, 0x21, 0 - .dw 0xc5c0, 0xc93d, 0xc5ff, 0xc93d, 0x21, 0 - .dw 0xc640, 0xc93d, 0xc67f, 0xc93d, 0x21, 0 - .dw 0xc6c0, 0xc93d, 0xc6ff, 0xc93d, 0x21, 0 - .dw 0xc740, 0xc93d, 0xc77f, 0xc93d, 0x21, 0 - .dw 0xc7c0, 0xc93d, 0xc7ff, 0xc93d, 0x21, 0 - .dw 0xc840, 0xc93d, 0xc87f, 0xc93d, 0x21, 0 - .dw 0xc8c0, 0xc93d, 0xc8ff, 0xc93d, 0x21, 0 - .dw 0xc940, 0xc93d, 0xc97f, 0xc93d, 0x21, 0 - .dw 0xc9c0, 0xc93d, 0xc9ff, 0xc93d, 0x21, 0 - .dw 0xca40, 0xc93d, 0xca7f, 0xc93d, 0x21, 0 - .dw 0xcac0, 0xc93d, 0xcaff, 0xc93d, 0x21, 0 - .dw 0xcb40, 0xc93d, 0xcb7f, 0xc93d, 0x21, 0 - .dw 0xcbc0, 0xc93d, 0xcbff, 0xc93d, 0x21, 0 - .dw 0xcc40, 0xc93d, 0xcc7f, 0xc93d, 0x21, 0 - .dw 0xccc0, 0xc93d, 0xccff, 0xc93d, 0x21, 0 - .dw 0xcd40, 0xc93d, 0xcd7f, 0xc93d, 0x21, 0 - .dw 0xcdc0, 0xc93d, 0xcdff, 0xc93d, 0x21, 0 - .dw 0xce40, 0xc93d, 0xce7f, 0xc93d, 0x21, 0 - .dw 0xcec0, 0xc93d, 0xceff, 0xc93d, 0x21, 0 - .dw 0xcf40, 0xc93d, 0xcf7f, 0xc93d, 0x21, 0 - .dw 0xcfc0, 0xc93d, 0xcfff, 0xc93d, 0x21, 0 - .dw 0xd040, 0xc93d, 0xd07f, 0xc93d, 0x21, 0 - .dw 0xd0c0, 0xc93d, 0xd0ff, 0xc93d, 0x21, 0 - .dw 0xd140, 0xc93d, 0xd17f, 0xc93d, 0x21, 0 - .dw 0xd1c0, 0xc93d, 0xd1ff, 0xc93d, 0x21, 0 - .dw 0xd240, 0xc93d, 0xd27f, 0xc93d, 0x21, 0 - .dw 0xd2c0, 0xc93d, 0xd2ff, 0xc93d, 0x21, 0 - .dw 0xd340, 0xc93d, 0xd37f, 0xc93d, 0x21, 0 - .dw 0xd3c0, 0xc93d, 0xd3ff, 0xc93d, 0x21, 0 - .dw 0xd440, 0xc93d, 0xd47f, 0xc93d, 0x21, 0 - .dw 0xd4c0, 0xc93d, 0xd4ff, 0xc93d, 0x21, 0 - .dw 0xd540, 0xc93d, 0xd57f, 0xc93d, 0x21, 0 - .dw 0xd5c0, 0xc93d, 0xd5ff, 0xc93d, 0x21, 0 - .dw 0xd640, 0xc93d, 0xd67f, 0xc93d, 0x21, 0 - .dw 0xd6c0, 0xc93d, 0xd6ff, 0xc93d, 0x21, 0 - .dw 0xd740, 0xc93d, 0xd77f, 0xc93d, 0x21, 0 - .dw 0xd7c0, 0xc93d, 0xd7ff, 0xc93d, 0x21, 0 - .dw 0xd840, 0xc93d, 0xd87f, 0xc93d, 0x21, 0 - .dw 0xd8c0, 0xc93d, 0xd8ff, 0xc93d, 0x21, 0 - .dw 0xd940, 0xc93d, 0xd97f, 0xc93d, 0x21, 0 - .dw 0xd9c0, 0xc93d, 0xdfff, 0xc93d, 0x21, 0 - .dw 0xe040, 0xc93d, 0xe07f, 0xc93d, 0x21, 0 - .dw 0xe0c0, 0xc93d, 0xe0ff, 0xc93d, 0x21, 0 - .dw 0xe140, 0xc93d, 0xe17f, 0xc93d, 0x21, 0 - .dw 0xe1c0, 0xc93d, 0xe1ff, 0xc93d, 0x21, 0 - .dw 0xe240, 0xc93d, 0xe27f, 0xc93d, 0x21, 0 - .dw 0xe2c0, 0xc93d, 0xe2ff, 0xc93d, 0x21, 0 - .dw 0xe340, 0xc93d, 0xe37f, 0xc93d, 0x21, 0 - .dw 0xe3c0, 0xc93d, 0xe3ff, 0xc93d, 0x21, 0 - .dw 0xe440, 0xc93d, 0xe47f, 0xc93d, 0x21, 0 - .dw 0xe4c0, 0xc93d, 0xe4ff, 0xc93d, 0x21, 0 - .dw 0xe540, 0xc93d, 0xe57f, 0xc93d, 0x21, 0 - .dw 0xe5c0, 0xc93d, 0xe5ff, 0xc93d, 0x21, 0 - .dw 0xe640, 0xc93d, 0xe67f, 0xc93d, 0x21, 0 - .dw 0xe6c0, 0xc93d, 0xe6ff, 0xc93d, 0x21, 0 - .dw 0xe740, 0xc93d, 0xe77f, 0xc93d, 0x21, 0 - .dw 0xe7c0, 0xc93d, 0xe7ff, 0xc93d, 0x21, 0 - .dw 0xe840, 0xc93d, 0xe87f, 0xc93d, 0x21, 0 - .dw 0xe8c0, 0xc93d, 0xe8ff, 0xc93d, 0x21, 0 - .dw 0xe940, 0xc93d, 0xe97f, 0xc93d, 0x21, 0 - .dw 0xe9c0, 0xc93d, 0xe9ff, 0xc93d, 0x21, 0 - .dw 0xea40, 0xc93d, 0xea7f, 0xc93d, 0x21, 0 - .dw 0xeac0, 0xc93d, 0xeaff, 0xc93d, 0x21, 0 - .dw 0xeb40, 0xc93d, 0xeb7f, 0xc93d, 0x21, 0 - .dw 0xebc0, 0xc93d, 0xebff, 0xc93d, 0x21, 0 - .dw 0xec40, 0xc93d, 0xec7f, 0xc93d, 0x21, 0 - .dw 0xecc0, 0xc93d, 0xecff, 0xc93d, 0x21, 0 - .dw 0xed40, 0xc93d, 0xed7f, 0xc93d, 0x21, 0 - .dw 0xedc0, 0xc93d, 0xedff, 0xc93d, 0x21, 0 - .dw 0xee40, 0xc93d, 0xee7f, 0xc93d, 0x21, 0 - .dw 0xeec0, 0xc93d, 0xeeff, 0xc93d, 0x21, 0 - .dw 0xef40, 0xc93d, 0xef7f, 0xc93d, 0x21, 0 - .dw 0xefc0, 0xc93d, 0xefff, 0xc93d, 0x21, 0 - .dw 0xf040, 0xc93d, 0xf07f, 0xc93d, 0x21, 0 - .dw 0xf0c0, 0xc93d, 0xf0ff, 0xc93d, 0x21, 0 - .dw 0xf140, 0xc93d, 0xf17f, 0xc93d, 0x21, 0 - .dw 0xf1c0, 0xc93d, 0xf1ff, 0xc93d, 0x21, 0 - .dw 0xf240, 0xc93d, 0xf27f, 0xc93d, 0x21, 0 - .dw 0xf2c0, 0xc93d, 0xf2ff, 0xc93d, 0x21, 0 - .dw 0xf340, 0xc93d, 0xf37f, 0xc93d, 0x21, 0 - .dw 0xf3c0, 0xc93d, 0xf3ff, 0xc93d, 0x21, 0 - .dw 0xf440, 0xc93d, 0xf47f, 0xc93d, 0x21, 0 - .dw 0xf4c0, 0xc93d, 0xf4ff, 0xc93d, 0x21, 0 - .dw 0xf540, 0xc93d, 0xf57f, 0xc93d, 0x21, 0 - .dw 0xf5c0, 0xc93d, 0xf5ff, 0xc93d, 0x21, 0 - .dw 0xf640, 0xc93d, 0xf67f, 0xc93d, 0x21, 0 - .dw 0xf6c0, 0xc93d, 0xf6ff, 0xc93d, 0x21, 0 - .dw 0xf740, 0xc93d, 0xf77f, 0xc93d, 0x21, 0 - .dw 0xf7c0, 0xc93d, 0xf7ff, 0xc93d, 0x21, 0 - .dw 0xf840, 0xc93d, 0xf87f, 0xc93d, 0x21, 0 - .dw 0xf8c0, 0xc93d, 0xf8ff, 0xc93d, 0x21, 0 - .dw 0xf940, 0xc93d, 0xf97f, 0xc93d, 0x21, 0 - .dw 0xf9c0, 0xc93d, 0xffff, 0xc93d, 0x21, 0 - .dw 0x0040, 0xc93e, 0x007f, 0xc93e, 0x21, 0 - .dw 0x00c0, 0xc93e, 0x00ff, 0xc93e, 0x21, 0 - .dw 0x0140, 0xc93e, 0x017f, 0xc93e, 0x21, 0 - .dw 0x01c0, 0xc93e, 0x01ff, 0xc93e, 0x21, 0 - .dw 0x0240, 0xc93e, 0x027f, 0xc93e, 0x21, 0 - .dw 0x02c0, 0xc93e, 0x02ff, 0xc93e, 0x21, 0 - .dw 0x0340, 0xc93e, 0x037f, 0xc93e, 0x21, 0 - .dw 0x03c0, 0xc93e, 0x03ff, 0xc93e, 0x21, 0 - .dw 0x0440, 0xc93e, 0x047f, 0xc93e, 0x21, 0 - .dw 0x04c0, 0xc93e, 0x04ff, 0xc93e, 0x21, 0 - .dw 0x0540, 0xc93e, 0x057f, 0xc93e, 0x21, 0 - .dw 0x05c0, 0xc93e, 0x05ff, 0xc93e, 0x21, 0 - .dw 0x0640, 0xc93e, 0x067f, 0xc93e, 0x21, 0 - .dw 0x06c0, 0xc93e, 0x06ff, 0xc93e, 0x21, 0 - .dw 0x0740, 0xc93e, 0x077f, 0xc93e, 0x21, 0 - .dw 0x07c0, 0xc93e, 0x07ff, 0xc93e, 0x21, 0 - .dw 0x0840, 0xc93e, 0x087f, 0xc93e, 0x21, 0 - .dw 0x08c0, 0xc93e, 0x08ff, 0xc93e, 0x21, 0 - .dw 0x0940, 0xc93e, 0x097f, 0xc93e, 0x21, 0 - .dw 0x09c0, 0xc93e, 0x09ff, 0xc93e, 0x21, 0 - .dw 0x0a40, 0xc93e, 0x0a7f, 0xc93e, 0x21, 0 - .dw 0x0ac0, 0xc93e, 0x0aff, 0xc93e, 0x21, 0 - .dw 0x0b40, 0xc93e, 0x0b7f, 0xc93e, 0x21, 0 - .dw 0x0bc0, 0xc93e, 0x0bff, 0xc93e, 0x21, 0 - .dw 0x0c40, 0xc93e, 0x0c7f, 0xc93e, 0x21, 0 - .dw 0x0cc0, 0xc93e, 0x0cff, 0xc93e, 0x21, 0 - .dw 0x0d40, 0xc93e, 0x0d7f, 0xc93e, 0x21, 0 - .dw 0x0dc0, 0xc93e, 0x0dff, 0xc93e, 0x21, 0 - .dw 0x0e40, 0xc93e, 0x0e7f, 0xc93e, 0x21, 0 - .dw 0x0ec0, 0xc93e, 0x0eff, 0xc93e, 0x21, 0 - .dw 0x0f40, 0xc93e, 0x0f7f, 0xc93e, 0x21, 0 - .dw 0x0fc0, 0xc93e, 0x0fff, 0xc93e, 0x21, 0 - .dw 0x1040, 0xc93e, 0x107f, 0xc93e, 0x21, 0 - .dw 0x10c0, 0xc93e, 0x10ff, 0xc93e, 0x21, 0 - .dw 0x1140, 0xc93e, 0x117f, 0xc93e, 0x21, 0 - .dw 0x11c0, 0xc93e, 0x11ff, 0xc93e, 0x21, 0 - .dw 0x1240, 0xc93e, 0x127f, 0xc93e, 0x21, 0 - .dw 0x12c0, 0xc93e, 0x12ff, 0xc93e, 0x21, 0 - .dw 0x1340, 0xc93e, 0x137f, 0xc93e, 0x21, 0 - .dw 0x13c0, 0xc93e, 0x13ff, 0xc93e, 0x21, 0 - .dw 0x1440, 0xc93e, 0x147f, 0xc93e, 0x21, 0 - .dw 0x14c0, 0xc93e, 0x14ff, 0xc93e, 0x21, 0 - .dw 0x1540, 0xc93e, 0x157f, 0xc93e, 0x21, 0 - .dw 0x15c0, 0xc93e, 0x15ff, 0xc93e, 0x21, 0 - .dw 0x1640, 0xc93e, 0x167f, 0xc93e, 0x21, 0 - .dw 0x16c0, 0xc93e, 0x16ff, 0xc93e, 0x21, 0 - .dw 0x1740, 0xc93e, 0x177f, 0xc93e, 0x21, 0 - .dw 0x17c0, 0xc93e, 0x17ff, 0xc93e, 0x21, 0 - .dw 0x1840, 0xc93e, 0x187f, 0xc93e, 0x21, 0 - .dw 0x18c0, 0xc93e, 0x18ff, 0xc93e, 0x21, 0 - .dw 0x1940, 0xc93e, 0x197f, 0xc93e, 0x21, 0 - .dw 0x19c0, 0xc93e, 0x1fff, 0xc93e, 0x21, 0 - .dw 0x2040, 0xc93e, 0x207f, 0xc93e, 0x21, 0 - .dw 0x20c0, 0xc93e, 0x20ff, 0xc93e, 0x21, 0 - .dw 0x2140, 0xc93e, 0x217f, 0xc93e, 0x21, 0 - .dw 0x21c0, 0xc93e, 0x21ff, 0xc93e, 0x21, 0 - .dw 0x2240, 0xc93e, 0x227f, 0xc93e, 0x21, 0 - .dw 0x22c0, 0xc93e, 0x22ff, 0xc93e, 0x21, 0 - .dw 0x2340, 0xc93e, 0x237f, 0xc93e, 0x21, 0 - .dw 0x23c0, 0xc93e, 0x23ff, 0xc93e, 0x21, 0 - .dw 0x2440, 0xc93e, 0x247f, 0xc93e, 0x21, 0 - .dw 0x24c0, 0xc93e, 0x24ff, 0xc93e, 0x21, 0 - .dw 0x2540, 0xc93e, 0x257f, 0xc93e, 0x21, 0 - .dw 0x25c0, 0xc93e, 0x25ff, 0xc93e, 0x21, 0 - .dw 0x2640, 0xc93e, 0x267f, 0xc93e, 0x21, 0 - .dw 0x26c0, 0xc93e, 0x26ff, 0xc93e, 0x21, 0 - .dw 0x2740, 0xc93e, 0x277f, 0xc93e, 0x21, 0 - .dw 0x27c0, 0xc93e, 0x27ff, 0xc93e, 0x21, 0 - .dw 0x2840, 0xc93e, 0x287f, 0xc93e, 0x21, 0 - .dw 0x28c0, 0xc93e, 0x28ff, 0xc93e, 0x21, 0 - .dw 0x2940, 0xc93e, 0x297f, 0xc93e, 0x21, 0 - .dw 0x29c0, 0xc93e, 0x29ff, 0xc93e, 0x21, 0 - .dw 0x2a40, 0xc93e, 0x2a7f, 0xc93e, 0x21, 0 - .dw 0x2ac0, 0xc93e, 0x2aff, 0xc93e, 0x21, 0 - .dw 0x2b40, 0xc93e, 0x2b7f, 0xc93e, 0x21, 0 - .dw 0x2bc0, 0xc93e, 0x2bff, 0xc93e, 0x21, 0 - .dw 0x2c40, 0xc93e, 0x2c7f, 0xc93e, 0x21, 0 - .dw 0x2cc0, 0xc93e, 0x2cff, 0xc93e, 0x21, 0 - .dw 0x2d40, 0xc93e, 0x2d7f, 0xc93e, 0x21, 0 - .dw 0x2dc0, 0xc93e, 0x2dff, 0xc93e, 0x21, 0 - .dw 0x2e40, 0xc93e, 0x2e7f, 0xc93e, 0x21, 0 - .dw 0x2ec0, 0xc93e, 0x2eff, 0xc93e, 0x21, 0 - .dw 0x2f40, 0xc93e, 0x2f7f, 0xc93e, 0x21, 0 - .dw 0x2fc0, 0xc93e, 0x2fff, 0xc93e, 0x21, 0 - .dw 0x3040, 0xc93e, 0x307f, 0xc93e, 0x21, 0 - .dw 0x30c0, 0xc93e, 0x30ff, 0xc93e, 0x21, 0 - .dw 0x3140, 0xc93e, 0x317f, 0xc93e, 0x21, 0 - .dw 0x31c0, 0xc93e, 0x31ff, 0xc93e, 0x21, 0 - .dw 0x3240, 0xc93e, 0x327f, 0xc93e, 0x21, 0 - .dw 0x32c0, 0xc93e, 0x32ff, 0xc93e, 0x21, 0 - .dw 0x3340, 0xc93e, 0x337f, 0xc93e, 0x21, 0 - .dw 0x33c0, 0xc93e, 0x33ff, 0xc93e, 0x21, 0 - .dw 0x3440, 0xc93e, 0x347f, 0xc93e, 0x21, 0 - .dw 0x34c0, 0xc93e, 0x34ff, 0xc93e, 0x21, 0 - .dw 0x3540, 0xc93e, 0x357f, 0xc93e, 0x21, 0 - .dw 0x35c0, 0xc93e, 0x35ff, 0xc93e, 0x21, 0 - .dw 0x3640, 0xc93e, 0x367f, 0xc93e, 0x21, 0 - .dw 0x36c0, 0xc93e, 0x36ff, 0xc93e, 0x21, 0 - .dw 0x3740, 0xc93e, 0x377f, 0xc93e, 0x21, 0 - .dw 0x37c0, 0xc93e, 0x37ff, 0xc93e, 0x21, 0 - .dw 0x3840, 0xc93e, 0x387f, 0xc93e, 0x21, 0 - .dw 0x38c0, 0xc93e, 0x38ff, 0xc93e, 0x21, 0 - .dw 0x3940, 0xc93e, 0x397f, 0xc93e, 0x21, 0 - .dw 0x39c0, 0xc93e, 0x3fff, 0xc93e, 0x21, 0 - .dw 0x4040, 0xc93e, 0x407f, 0xc93e, 0x21, 0 - .dw 0x40c0, 0xc93e, 0x40ff, 0xc93e, 0x21, 0 - .dw 0x4140, 0xc93e, 0x417f, 0xc93e, 0x21, 0 - .dw 0x41c0, 0xc93e, 0x41ff, 0xc93e, 0x21, 0 - .dw 0x4240, 0xc93e, 0x427f, 0xc93e, 0x21, 0 - .dw 0x42c0, 0xc93e, 0x42ff, 0xc93e, 0x21, 0 - .dw 0x4340, 0xc93e, 0x437f, 0xc93e, 0x21, 0 - .dw 0x43c0, 0xc93e, 0x43ff, 0xc93e, 0x21, 0 - .dw 0x4440, 0xc93e, 0x447f, 0xc93e, 0x21, 0 - .dw 0x44c0, 0xc93e, 0x44ff, 0xc93e, 0x21, 0 - .dw 0x4540, 0xc93e, 0x457f, 0xc93e, 0x21, 0 - .dw 0x45c0, 0xc93e, 0x45ff, 0xc93e, 0x21, 0 - .dw 0x4640, 0xc93e, 0x467f, 0xc93e, 0x21, 0 - .dw 0x46c0, 0xc93e, 0x46ff, 0xc93e, 0x21, 0 - .dw 0x4740, 0xc93e, 0x477f, 0xc93e, 0x21, 0 - .dw 0x47c0, 0xc93e, 0x47ff, 0xc93e, 0x21, 0 - .dw 0x4840, 0xc93e, 0x487f, 0xc93e, 0x21, 0 - .dw 0x48c0, 0xc93e, 0x48ff, 0xc93e, 0x21, 0 - .dw 0x4940, 0xc93e, 0x497f, 0xc93e, 0x21, 0 - .dw 0x49c0, 0xc93e, 0x49ff, 0xc93e, 0x21, 0 - .dw 0x4a40, 0xc93e, 0x4a7f, 0xc93e, 0x21, 0 - .dw 0x4ac0, 0xc93e, 0x4aff, 0xc93e, 0x21, 0 - .dw 0x4b40, 0xc93e, 0x4b7f, 0xc93e, 0x21, 0 - .dw 0x4bc0, 0xc93e, 0x4bff, 0xc93e, 0x21, 0 - .dw 0x4c40, 0xc93e, 0x4c7f, 0xc93e, 0x21, 0 - .dw 0x4cc0, 0xc93e, 0x4cff, 0xc93e, 0x21, 0 - .dw 0x4d40, 0xc93e, 0x4d7f, 0xc93e, 0x21, 0 - .dw 0x4dc0, 0xc93e, 0x4dff, 0xc93e, 0x21, 0 - .dw 0x4e40, 0xc93e, 0x4e7f, 0xc93e, 0x21, 0 - .dw 0x4ec0, 0xc93e, 0x4eff, 0xc93e, 0x21, 0 - .dw 0x4f40, 0xc93e, 0x4f7f, 0xc93e, 0x21, 0 - .dw 0x4fc0, 0xc93e, 0x4fff, 0xc93e, 0x21, 0 - .dw 0x5040, 0xc93e, 0x507f, 0xc93e, 0x21, 0 - .dw 0x50c0, 0xc93e, 0x50ff, 0xc93e, 0x21, 0 - .dw 0x5140, 0xc93e, 0x517f, 0xc93e, 0x21, 0 - .dw 0x51c0, 0xc93e, 0x51ff, 0xc93e, 0x21, 0 - .dw 0x5240, 0xc93e, 0x527f, 0xc93e, 0x21, 0 - .dw 0x52c0, 0xc93e, 0x52ff, 0xc93e, 0x21, 0 - .dw 0x5340, 0xc93e, 0x537f, 0xc93e, 0x21, 0 - .dw 0x53c0, 0xc93e, 0x53ff, 0xc93e, 0x21, 0 - .dw 0x5440, 0xc93e, 0x547f, 0xc93e, 0x21, 0 - .dw 0x54c0, 0xc93e, 0x54ff, 0xc93e, 0x21, 0 - .dw 0x5540, 0xc93e, 0x557f, 0xc93e, 0x21, 0 - .dw 0x55c0, 0xc93e, 0x55ff, 0xc93e, 0x21, 0 - .dw 0x5640, 0xc93e, 0x567f, 0xc93e, 0x21, 0 - .dw 0x56c0, 0xc93e, 0x56ff, 0xc93e, 0x21, 0 - .dw 0x5740, 0xc93e, 0x577f, 0xc93e, 0x21, 0 - .dw 0x57c0, 0xc93e, 0x57ff, 0xc93e, 0x21, 0 - .dw 0x5840, 0xc93e, 0x587f, 0xc93e, 0x21, 0 - .dw 0x58c0, 0xc93e, 0x58ff, 0xc93e, 0x21, 0 - .dw 0x5940, 0xc93e, 0x597f, 0xc93e, 0x21, 0 - .dw 0x59c0, 0xc93e, 0x5fff, 0xc93e, 0x21, 0 - .dw 0x6040, 0xc93e, 0x607f, 0xc93e, 0x21, 0 - .dw 0x60c0, 0xc93e, 0x60ff, 0xc93e, 0x21, 0 - .dw 0x6140, 0xc93e, 0x617f, 0xc93e, 0x21, 0 - .dw 0x61c0, 0xc93e, 0x61ff, 0xc93e, 0x21, 0 - .dw 0x6240, 0xc93e, 0x627f, 0xc93e, 0x21, 0 - .dw 0x62c0, 0xc93e, 0x62ff, 0xc93e, 0x21, 0 - .dw 0x6340, 0xc93e, 0x637f, 0xc93e, 0x21, 0 - .dw 0x63c0, 0xc93e, 0x63ff, 0xc93e, 0x21, 0 - .dw 0x6440, 0xc93e, 0x647f, 0xc93e, 0x21, 0 - .dw 0x64c0, 0xc93e, 0x64ff, 0xc93e, 0x21, 0 - .dw 0x6540, 0xc93e, 0x657f, 0xc93e, 0x21, 0 - .dw 0x65c0, 0xc93e, 0x65ff, 0xc93e, 0x21, 0 - .dw 0x6640, 0xc93e, 0x667f, 0xc93e, 0x21, 0 - .dw 0x66c0, 0xc93e, 0x66ff, 0xc93e, 0x21, 0 - .dw 0x6740, 0xc93e, 0x677f, 0xc93e, 0x21, 0 - .dw 0x67c0, 0xc93e, 0x67ff, 0xc93e, 0x21, 0 - .dw 0x6840, 0xc93e, 0x687f, 0xc93e, 0x21, 0 - .dw 0x68c0, 0xc93e, 0x68ff, 0xc93e, 0x21, 0 - .dw 0x6940, 0xc93e, 0x697f, 0xc93e, 0x21, 0 - .dw 0x69c0, 0xc93e, 0x69ff, 0xc93e, 0x21, 0 - .dw 0x6a40, 0xc93e, 0x6a7f, 0xc93e, 0x21, 0 - .dw 0x6ac0, 0xc93e, 0x6aff, 0xc93e, 0x21, 0 - .dw 0x6b40, 0xc93e, 0x6b7f, 0xc93e, 0x21, 0 - .dw 0x6bc0, 0xc93e, 0x6bff, 0xc93e, 0x21, 0 - .dw 0x6c40, 0xc93e, 0x6c7f, 0xc93e, 0x21, 0 - .dw 0x6cc0, 0xc93e, 0x6cff, 0xc93e, 0x21, 0 - .dw 0x6d40, 0xc93e, 0x6d7f, 0xc93e, 0x21, 0 - .dw 0x6dc0, 0xc93e, 0x6dff, 0xc93e, 0x21, 0 - .dw 0x6e40, 0xc93e, 0x6e7f, 0xc93e, 0x21, 0 - .dw 0x6ec0, 0xc93e, 0x6eff, 0xc93e, 0x21, 0 - .dw 0x6f40, 0xc93e, 0x6f7f, 0xc93e, 0x21, 0 - .dw 0x6fc0, 0xc93e, 0x6fff, 0xc93e, 0x21, 0 - .dw 0x7040, 0xc93e, 0x707f, 0xc93e, 0x21, 0 - .dw 0x70c0, 0xc93e, 0x70ff, 0xc93e, 0x21, 0 - .dw 0x7140, 0xc93e, 0x717f, 0xc93e, 0x21, 0 - .dw 0x71c0, 0xc93e, 0x71ff, 0xc93e, 0x21, 0 - .dw 0x7240, 0xc93e, 0x727f, 0xc93e, 0x21, 0 - .dw 0x72c0, 0xc93e, 0x72ff, 0xc93e, 0x21, 0 - .dw 0x7340, 0xc93e, 0x737f, 0xc93e, 0x21, 0 - .dw 0x73c0, 0xc93e, 0x73ff, 0xc93e, 0x21, 0 - .dw 0x7440, 0xc93e, 0x747f, 0xc93e, 0x21, 0 - .dw 0x74c0, 0xc93e, 0x74ff, 0xc93e, 0x21, 0 - .dw 0x7540, 0xc93e, 0x757f, 0xc93e, 0x21, 0 - .dw 0x75c0, 0xc93e, 0x75ff, 0xc93e, 0x21, 0 - .dw 0x7640, 0xc93e, 0x767f, 0xc93e, 0x21, 0 - .dw 0x76c0, 0xc93e, 0x76ff, 0xc93e, 0x21, 0 - .dw 0x7740, 0xc93e, 0x777f, 0xc93e, 0x21, 0 - .dw 0x77c0, 0xc93e, 0x77ff, 0xc93e, 0x21, 0 - .dw 0x7840, 0xc93e, 0x787f, 0xc93e, 0x21, 0 - .dw 0x78c0, 0xc93e, 0x78ff, 0xc93e, 0x21, 0 - .dw 0x7940, 0xc93e, 0x797f, 0xc93e, 0x21, 0 - .dw 0x79c0, 0xc93e, 0x7fff, 0xc93e, 0x21, 0 - .dw 0x8040, 0xc93e, 0x807f, 0xc93e, 0x21, 0 - .dw 0x80c0, 0xc93e, 0x80ff, 0xc93e, 0x21, 0 - .dw 0x8140, 0xc93e, 0x817f, 0xc93e, 0x21, 0 - .dw 0x81c0, 0xc93e, 0x81ff, 0xc93e, 0x21, 0 - .dw 0x8240, 0xc93e, 0x827f, 0xc93e, 0x21, 0 - .dw 0x82c0, 0xc93e, 0x82ff, 0xc93e, 0x21, 0 - .dw 0x8340, 0xc93e, 0x837f, 0xc93e, 0x21, 0 - .dw 0x83c0, 0xc93e, 0x83ff, 0xc93e, 0x21, 0 - .dw 0x8440, 0xc93e, 0x847f, 0xc93e, 0x21, 0 - .dw 0x84c0, 0xc93e, 0x84ff, 0xc93e, 0x21, 0 - .dw 0x8540, 0xc93e, 0x857f, 0xc93e, 0x21, 0 - .dw 0x85c0, 0xc93e, 0x85ff, 0xc93e, 0x21, 0 - .dw 0x8640, 0xc93e, 0x867f, 0xc93e, 0x21, 0 - .dw 0x86c0, 0xc93e, 0x86ff, 0xc93e, 0x21, 0 - .dw 0x8740, 0xc93e, 0x877f, 0xc93e, 0x21, 0 - .dw 0x87c0, 0xc93e, 0x87ff, 0xc93e, 0x21, 0 - .dw 0x8840, 0xc93e, 0x887f, 0xc93e, 0x21, 0 - .dw 0x88c0, 0xc93e, 0x88ff, 0xc93e, 0x21, 0 - .dw 0x8940, 0xc93e, 0x897f, 0xc93e, 0x21, 0 - .dw 0x89c0, 0xc93e, 0x89ff, 0xc93e, 0x21, 0 - .dw 0x8a40, 0xc93e, 0x8a7f, 0xc93e, 0x21, 0 - .dw 0x8ac0, 0xc93e, 0x8aff, 0xc93e, 0x21, 0 - .dw 0x8b40, 0xc93e, 0x8b7f, 0xc93e, 0x21, 0 - .dw 0x8bc0, 0xc93e, 0x8bff, 0xc93e, 0x21, 0 - .dw 0x8c40, 0xc93e, 0x8c7f, 0xc93e, 0x21, 0 - .dw 0x8cc0, 0xc93e, 0x8cff, 0xc93e, 0x21, 0 - .dw 0x8d40, 0xc93e, 0x8d7f, 0xc93e, 0x21, 0 - .dw 0x8dc0, 0xc93e, 0x8dff, 0xc93e, 0x21, 0 - .dw 0x8e40, 0xc93e, 0x8e7f, 0xc93e, 0x21, 0 - .dw 0x8ec0, 0xc93e, 0x8eff, 0xc93e, 0x21, 0 - .dw 0x8f40, 0xc93e, 0x8f7f, 0xc93e, 0x21, 0 - .dw 0x8fc0, 0xc93e, 0x8fff, 0xc93e, 0x21, 0 - .dw 0x9040, 0xc93e, 0x907f, 0xc93e, 0x21, 0 - .dw 0x90c0, 0xc93e, 0x90ff, 0xc93e, 0x21, 0 - .dw 0x9140, 0xc93e, 0x917f, 0xc93e, 0x21, 0 - .dw 0x91c0, 0xc93e, 0x91ff, 0xc93e, 0x21, 0 - .dw 0x9240, 0xc93e, 0x927f, 0xc93e, 0x21, 0 - .dw 0x92c0, 0xc93e, 0x92ff, 0xc93e, 0x21, 0 - .dw 0x9340, 0xc93e, 0x937f, 0xc93e, 0x21, 0 - .dw 0x93c0, 0xc93e, 0x93ff, 0xc93e, 0x21, 0 - .dw 0x9440, 0xc93e, 0x947f, 0xc93e, 0x21, 0 - .dw 0x94c0, 0xc93e, 0x94ff, 0xc93e, 0x21, 0 - .dw 0x9540, 0xc93e, 0x957f, 0xc93e, 0x21, 0 - .dw 0x95c0, 0xc93e, 0x95ff, 0xc93e, 0x21, 0 - .dw 0x9640, 0xc93e, 0x967f, 0xc93e, 0x21, 0 - .dw 0x96c0, 0xc93e, 0x96ff, 0xc93e, 0x21, 0 - .dw 0x9740, 0xc93e, 0x977f, 0xc93e, 0x21, 0 - .dw 0x97c0, 0xc93e, 0x97ff, 0xc93e, 0x21, 0 - .dw 0x9840, 0xc93e, 0x987f, 0xc93e, 0x21, 0 - .dw 0x98c0, 0xc93e, 0x98ff, 0xc93e, 0x21, 0 - .dw 0x9940, 0xc93e, 0x997f, 0xc93e, 0x21, 0 - .dw 0x99c0, 0xc93e, 0x9fff, 0xc93e, 0x21, 0 - .dw 0xa040, 0xc93e, 0xa07f, 0xc93e, 0x21, 0 - .dw 0xa0c0, 0xc93e, 0xa0ff, 0xc93e, 0x21, 0 - .dw 0xa140, 0xc93e, 0xa17f, 0xc93e, 0x21, 0 - .dw 0xa1c0, 0xc93e, 0xa1ff, 0xc93e, 0x21, 0 - .dw 0xa240, 0xc93e, 0xa27f, 0xc93e, 0x21, 0 - .dw 0xa2c0, 0xc93e, 0xa2ff, 0xc93e, 0x21, 0 - .dw 0xa340, 0xc93e, 0xa37f, 0xc93e, 0x21, 0 - .dw 0xa3c0, 0xc93e, 0xa3ff, 0xc93e, 0x21, 0 - .dw 0xa440, 0xc93e, 0xa47f, 0xc93e, 0x21, 0 - .dw 0xa4c0, 0xc93e, 0xa4ff, 0xc93e, 0x21, 0 - .dw 0xa540, 0xc93e, 0xa57f, 0xc93e, 0x21, 0 - .dw 0xa5c0, 0xc93e, 0xa5ff, 0xc93e, 0x21, 0 - .dw 0xa640, 0xc93e, 0xa67f, 0xc93e, 0x21, 0 - .dw 0xa6c0, 0xc93e, 0xa6ff, 0xc93e, 0x21, 0 - .dw 0xa740, 0xc93e, 0xa77f, 0xc93e, 0x21, 0 - .dw 0xa7c0, 0xc93e, 0xa7ff, 0xc93e, 0x21, 0 - .dw 0xa840, 0xc93e, 0xa87f, 0xc93e, 0x21, 0 - .dw 0xa8c0, 0xc93e, 0xa8ff, 0xc93e, 0x21, 0 - .dw 0xa940, 0xc93e, 0xa97f, 0xc93e, 0x21, 0 - .dw 0xa9c0, 0xc93e, 0xa9ff, 0xc93e, 0x21, 0 - .dw 0xaa40, 0xc93e, 0xaa7f, 0xc93e, 0x21, 0 - .dw 0xaac0, 0xc93e, 0xaaff, 0xc93e, 0x21, 0 - .dw 0xab40, 0xc93e, 0xab7f, 0xc93e, 0x21, 0 - .dw 0xabc0, 0xc93e, 0xabff, 0xc93e, 0x21, 0 - .dw 0xac40, 0xc93e, 0xac7f, 0xc93e, 0x21, 0 - .dw 0xacc0, 0xc93e, 0xacff, 0xc93e, 0x21, 0 - .dw 0xad40, 0xc93e, 0xad7f, 0xc93e, 0x21, 0 - .dw 0xadc0, 0xc93e, 0xadff, 0xc93e, 0x21, 0 - .dw 0xae40, 0xc93e, 0xae7f, 0xc93e, 0x21, 0 - .dw 0xaec0, 0xc93e, 0xaeff, 0xc93e, 0x21, 0 - .dw 0xaf40, 0xc93e, 0xaf7f, 0xc93e, 0x21, 0 - .dw 0xafc0, 0xc93e, 0xafff, 0xc93e, 0x21, 0 - .dw 0xb040, 0xc93e, 0xb07f, 0xc93e, 0x21, 0 - .dw 0xb0c0, 0xc93e, 0xb0ff, 0xc93e, 0x21, 0 - .dw 0xb140, 0xc93e, 0xb17f, 0xc93e, 0x21, 0 - .dw 0xb1c0, 0xc93e, 0xb1ff, 0xc93e, 0x21, 0 - .dw 0xb240, 0xc93e, 0xb27f, 0xc93e, 0x21, 0 - .dw 0xb2c0, 0xc93e, 0xb2ff, 0xc93e, 0x21, 0 - .dw 0xb340, 0xc93e, 0xb37f, 0xc93e, 0x21, 0 - .dw 0xb3c0, 0xc93e, 0xb3ff, 0xc93e, 0x21, 0 - .dw 0xb440, 0xc93e, 0xb47f, 0xc93e, 0x21, 0 - .dw 0xb4c0, 0xc93e, 0xb4ff, 0xc93e, 0x21, 0 - .dw 0xb540, 0xc93e, 0xb57f, 0xc93e, 0x21, 0 - .dw 0xb5c0, 0xc93e, 0xb5ff, 0xc93e, 0x21, 0 - .dw 0xb640, 0xc93e, 0xb67f, 0xc93e, 0x21, 0 - .dw 0xb6c0, 0xc93e, 0xb6ff, 0xc93e, 0x21, 0 - .dw 0xb740, 0xc93e, 0xb77f, 0xc93e, 0x21, 0 - .dw 0xb7c0, 0xc93e, 0xb7ff, 0xc93e, 0x21, 0 - .dw 0xb840, 0xc93e, 0xb87f, 0xc93e, 0x21, 0 - .dw 0xb8c0, 0xc93e, 0xb8ff, 0xc93e, 0x21, 0 - .dw 0xb940, 0xc93e, 0xb97f, 0xc93e, 0x21, 0 - .dw 0xb9c0, 0xc93e, 0xbfff, 0xc93e, 0x21, 0 - .dw 0xc040, 0xc93e, 0xc07f, 0xc93e, 0x21, 0 - .dw 0xc0c0, 0xc93e, 0xc0ff, 0xc93e, 0x21, 0 - .dw 0xc140, 0xc93e, 0xc17f, 0xc93e, 0x21, 0 - .dw 0xc1c0, 0xc93e, 0xc1ff, 0xc93e, 0x21, 0 - .dw 0xc240, 0xc93e, 0xc27f, 0xc93e, 0x21, 0 - .dw 0xc2c0, 0xc93e, 0xc2ff, 0xc93e, 0x21, 0 - .dw 0xc340, 0xc93e, 0xc37f, 0xc93e, 0x21, 0 - .dw 0xc3c0, 0xc93e, 0xc3ff, 0xc93e, 0x21, 0 - .dw 0xc440, 0xc93e, 0xc47f, 0xc93e, 0x21, 0 - .dw 0xc4c0, 0xc93e, 0xc4ff, 0xc93e, 0x21, 0 - .dw 0xc540, 0xc93e, 0xc57f, 0xc93e, 0x21, 0 - .dw 0xc5c0, 0xc93e, 0xc5ff, 0xc93e, 0x21, 0 - .dw 0xc640, 0xc93e, 0xc67f, 0xc93e, 0x21, 0 - .dw 0xc6c0, 0xc93e, 0xc6ff, 0xc93e, 0x21, 0 - .dw 0xc740, 0xc93e, 0xc77f, 0xc93e, 0x21, 0 - .dw 0xc7c0, 0xc93e, 0xc7ff, 0xc93e, 0x21, 0 - .dw 0xc840, 0xc93e, 0xc87f, 0xc93e, 0x21, 0 - .dw 0xc8c0, 0xc93e, 0xc8ff, 0xc93e, 0x21, 0 - .dw 0xc940, 0xc93e, 0xc97f, 0xc93e, 0x21, 0 - .dw 0xc9c0, 0xc93e, 0xc9ff, 0xc93e, 0x21, 0 - .dw 0xca40, 0xc93e, 0xca7f, 0xc93e, 0x21, 0 - .dw 0xcac0, 0xc93e, 0xcaff, 0xc93e, 0x21, 0 - .dw 0xcb40, 0xc93e, 0xcb7f, 0xc93e, 0x21, 0 - .dw 0xcbc0, 0xc93e, 0xcbff, 0xc93e, 0x21, 0 - .dw 0xcc40, 0xc93e, 0xcc7f, 0xc93e, 0x21, 0 - .dw 0xccc0, 0xc93e, 0xccff, 0xc93e, 0x21, 0 - .dw 0xcd40, 0xc93e, 0xcd7f, 0xc93e, 0x21, 0 - .dw 0xcdc0, 0xc93e, 0xcdff, 0xc93e, 0x21, 0 - .dw 0xce40, 0xc93e, 0xce7f, 0xc93e, 0x21, 0 - .dw 0xcec0, 0xc93e, 0xceff, 0xc93e, 0x21, 0 - .dw 0xcf40, 0xc93e, 0xcf7f, 0xc93e, 0x21, 0 - .dw 0xcfc0, 0xc93e, 0xcfff, 0xc93e, 0x21, 0 - .dw 0xd040, 0xc93e, 0xd07f, 0xc93e, 0x21, 0 - .dw 0xd0c0, 0xc93e, 0xd0ff, 0xc93e, 0x21, 0 - .dw 0xd140, 0xc93e, 0xd17f, 0xc93e, 0x21, 0 - .dw 0xd1c0, 0xc93e, 0xd1ff, 0xc93e, 0x21, 0 - .dw 0xd240, 0xc93e, 0xd27f, 0xc93e, 0x21, 0 - .dw 0xd2c0, 0xc93e, 0xd2ff, 0xc93e, 0x21, 0 - .dw 0xd340, 0xc93e, 0xd37f, 0xc93e, 0x21, 0 - .dw 0xd3c0, 0xc93e, 0xd3ff, 0xc93e, 0x21, 0 - .dw 0xd440, 0xc93e, 0xd47f, 0xc93e, 0x21, 0 - .dw 0xd4c0, 0xc93e, 0xd4ff, 0xc93e, 0x21, 0 - .dw 0xd540, 0xc93e, 0xd57f, 0xc93e, 0x21, 0 - .dw 0xd5c0, 0xc93e, 0xd5ff, 0xc93e, 0x21, 0 - .dw 0xd640, 0xc93e, 0xd67f, 0xc93e, 0x21, 0 - .dw 0xd6c0, 0xc93e, 0xd6ff, 0xc93e, 0x21, 0 - .dw 0xd740, 0xc93e, 0xd77f, 0xc93e, 0x21, 0 - .dw 0xd7c0, 0xc93e, 0xd7ff, 0xc93e, 0x21, 0 - .dw 0xd840, 0xc93e, 0xd87f, 0xc93e, 0x21, 0 - .dw 0xd8c0, 0xc93e, 0xd8ff, 0xc93e, 0x21, 0 - .dw 0xd940, 0xc93e, 0xd97f, 0xc93e, 0x21, 0 - .dw 0xd9c0, 0xc93e, 0xdfff, 0xc93e, 0x21, 0 - .dw 0xe040, 0xc93e, 0xe07f, 0xc93e, 0x21, 0 - .dw 0xe0c0, 0xc93e, 0xe0ff, 0xc93e, 0x21, 0 - .dw 0xe140, 0xc93e, 0xe17f, 0xc93e, 0x21, 0 - .dw 0xe1c0, 0xc93e, 0xe1ff, 0xc93e, 0x21, 0 - .dw 0xe240, 0xc93e, 0xe27f, 0xc93e, 0x21, 0 - .dw 0xe2c0, 0xc93e, 0xe2ff, 0xc93e, 0x21, 0 - .dw 0xe340, 0xc93e, 0xe37f, 0xc93e, 0x21, 0 - .dw 0xe3c0, 0xc93e, 0xe3ff, 0xc93e, 0x21, 0 - .dw 0xe440, 0xc93e, 0xe47f, 0xc93e, 0x21, 0 - .dw 0xe4c0, 0xc93e, 0xe4ff, 0xc93e, 0x21, 0 - .dw 0xe540, 0xc93e, 0xe57f, 0xc93e, 0x21, 0 - .dw 0xe5c0, 0xc93e, 0xe5ff, 0xc93e, 0x21, 0 - .dw 0xe640, 0xc93e, 0xe67f, 0xc93e, 0x21, 0 - .dw 0xe6c0, 0xc93e, 0xe6ff, 0xc93e, 0x21, 0 - .dw 0xe740, 0xc93e, 0xe77f, 0xc93e, 0x21, 0 - .dw 0xe7c0, 0xc93e, 0xe7ff, 0xc93e, 0x21, 0 - .dw 0xe840, 0xc93e, 0xe87f, 0xc93e, 0x21, 0 - .dw 0xe8c0, 0xc93e, 0xe8ff, 0xc93e, 0x21, 0 - .dw 0xe940, 0xc93e, 0xe97f, 0xc93e, 0x21, 0 - .dw 0xe9c0, 0xc93e, 0xe9ff, 0xc93e, 0x21, 0 - .dw 0xea40, 0xc93e, 0xea7f, 0xc93e, 0x21, 0 - .dw 0xeac0, 0xc93e, 0xeaff, 0xc93e, 0x21, 0 - .dw 0xeb40, 0xc93e, 0xeb7f, 0xc93e, 0x21, 0 - .dw 0xebc0, 0xc93e, 0xebff, 0xc93e, 0x21, 0 - .dw 0xec40, 0xc93e, 0xec7f, 0xc93e, 0x21, 0 - .dw 0xecc0, 0xc93e, 0xecff, 0xc93e, 0x21, 0 - .dw 0xed40, 0xc93e, 0xed7f, 0xc93e, 0x21, 0 - .dw 0xedc0, 0xc93e, 0xedff, 0xc93e, 0x21, 0 - .dw 0xee40, 0xc93e, 0xee7f, 0xc93e, 0x21, 0 - .dw 0xeec0, 0xc93e, 0xeeff, 0xc93e, 0x21, 0 - .dw 0xef40, 0xc93e, 0xef7f, 0xc93e, 0x21, 0 - .dw 0xefc0, 0xc93e, 0xefff, 0xc93e, 0x21, 0 - .dw 0xf040, 0xc93e, 0xf07f, 0xc93e, 0x21, 0 - .dw 0xf0c0, 0xc93e, 0xf0ff, 0xc93e, 0x21, 0 - .dw 0xf140, 0xc93e, 0xf17f, 0xc93e, 0x21, 0 - .dw 0xf1c0, 0xc93e, 0xf1ff, 0xc93e, 0x21, 0 - .dw 0xf240, 0xc93e, 0xf27f, 0xc93e, 0x21, 0 - .dw 0xf2c0, 0xc93e, 0xf2ff, 0xc93e, 0x21, 0 - .dw 0xf340, 0xc93e, 0xf37f, 0xc93e, 0x21, 0 - .dw 0xf3c0, 0xc93e, 0xf3ff, 0xc93e, 0x21, 0 - .dw 0xf440, 0xc93e, 0xf47f, 0xc93e, 0x21, 0 - .dw 0xf4c0, 0xc93e, 0xf4ff, 0xc93e, 0x21, 0 - .dw 0xf540, 0xc93e, 0xf57f, 0xc93e, 0x21, 0 - .dw 0xf5c0, 0xc93e, 0xf5ff, 0xc93e, 0x21, 0 - .dw 0xf640, 0xc93e, 0xf67f, 0xc93e, 0x21, 0 - .dw 0xf6c0, 0xc93e, 0xf6ff, 0xc93e, 0x21, 0 - .dw 0xf740, 0xc93e, 0xf77f, 0xc93e, 0x21, 0 - .dw 0xf7c0, 0xc93e, 0xf7ff, 0xc93e, 0x21, 0 - .dw 0xf840, 0xc93e, 0xf87f, 0xc93e, 0x21, 0 - .dw 0xf8c0, 0xc93e, 0xf8ff, 0xc93e, 0x21, 0 - .dw 0xf940, 0xc93e, 0xf97f, 0xc93e, 0x21, 0 - .dw 0xf9c0, 0xc93e, 0xffff, 0xc93e, 0x21, 0 - .dw 0x0040, 0xc93f, 0x007f, 0xc93f, 0x21, 0 - .dw 0x00c0, 0xc93f, 0x00ff, 0xc93f, 0x21, 0 - .dw 0x0140, 0xc93f, 0x017f, 0xc93f, 0x21, 0 - .dw 0x01c0, 0xc93f, 0x01ff, 0xc93f, 0x21, 0 - .dw 0x0240, 0xc93f, 0x027f, 0xc93f, 0x21, 0 - .dw 0x02c0, 0xc93f, 0x02ff, 0xc93f, 0x21, 0 - .dw 0x0340, 0xc93f, 0x037f, 0xc93f, 0x21, 0 - .dw 0x03c0, 0xc93f, 0x03ff, 0xc93f, 0x21, 0 - .dw 0x0440, 0xc93f, 0x047f, 0xc93f, 0x21, 0 - .dw 0x04c0, 0xc93f, 0x04ff, 0xc93f, 0x21, 0 - .dw 0x0540, 0xc93f, 0x057f, 0xc93f, 0x21, 0 - .dw 0x05c0, 0xc93f, 0x05ff, 0xc93f, 0x21, 0 - .dw 0x0640, 0xc93f, 0x067f, 0xc93f, 0x21, 0 - .dw 0x06c0, 0xc93f, 0x06ff, 0xc93f, 0x21, 0 - .dw 0x0740, 0xc93f, 0x077f, 0xc93f, 0x21, 0 - .dw 0x07c0, 0xc93f, 0x07ff, 0xc93f, 0x21, 0 - .dw 0x0840, 0xc93f, 0x087f, 0xc93f, 0x21, 0 - .dw 0x08c0, 0xc93f, 0x08ff, 0xc93f, 0x21, 0 - .dw 0x0940, 0xc93f, 0x097f, 0xc93f, 0x21, 0 - .dw 0x09c0, 0xc93f, 0x09ff, 0xc93f, 0x21, 0 - .dw 0x0a40, 0xc93f, 0x0a7f, 0xc93f, 0x21, 0 - .dw 0x0ac0, 0xc93f, 0x0aff, 0xc93f, 0x21, 0 - .dw 0x0b40, 0xc93f, 0x0b7f, 0xc93f, 0x21, 0 - .dw 0x0bc0, 0xc93f, 0x0bff, 0xc93f, 0x21, 0 - .dw 0x0c40, 0xc93f, 0x0c7f, 0xc93f, 0x21, 0 - .dw 0x0cc0, 0xc93f, 0x0cff, 0xc93f, 0x21, 0 - .dw 0x0d40, 0xc93f, 0x0d7f, 0xc93f, 0x21, 0 - .dw 0x0dc0, 0xc93f, 0x0dff, 0xc93f, 0x21, 0 - .dw 0x0e40, 0xc93f, 0x0e7f, 0xc93f, 0x21, 0 - .dw 0x0ec0, 0xc93f, 0x0eff, 0xc93f, 0x21, 0 - .dw 0x0f40, 0xc93f, 0x0f7f, 0xc93f, 0x21, 0 - .dw 0x0fc0, 0xc93f, 0x0fff, 0xc93f, 0x21, 0 - .dw 0x1040, 0xc93f, 0x107f, 0xc93f, 0x21, 0 - .dw 0x10c0, 0xc93f, 0x10ff, 0xc93f, 0x21, 0 - .dw 0x1140, 0xc93f, 0x117f, 0xc93f, 0x21, 0 - .dw 0x11c0, 0xc93f, 0x11ff, 0xc93f, 0x21, 0 - .dw 0x1240, 0xc93f, 0x127f, 0xc93f, 0x21, 0 - .dw 0x12c0, 0xc93f, 0x12ff, 0xc93f, 0x21, 0 - .dw 0x1340, 0xc93f, 0x137f, 0xc93f, 0x21, 0 - .dw 0x13c0, 0xc93f, 0x13ff, 0xc93f, 0x21, 0 - .dw 0x1440, 0xc93f, 0x147f, 0xc93f, 0x21, 0 - .dw 0x14c0, 0xc93f, 0x14ff, 0xc93f, 0x21, 0 - .dw 0x1540, 0xc93f, 0x157f, 0xc93f, 0x21, 0 - .dw 0x15c0, 0xc93f, 0x15ff, 0xc93f, 0x21, 0 - .dw 0x1640, 0xc93f, 0x167f, 0xc93f, 0x21, 0 - .dw 0x16c0, 0xc93f, 0x16ff, 0xc93f, 0x21, 0 - .dw 0x1740, 0xc93f, 0x177f, 0xc93f, 0x21, 0 - .dw 0x17c0, 0xc93f, 0x17ff, 0xc93f, 0x21, 0 - .dw 0x1840, 0xc93f, 0x187f, 0xc93f, 0x21, 0 - .dw 0x18c0, 0xc93f, 0x18ff, 0xc93f, 0x21, 0 - .dw 0x1940, 0xc93f, 0x197f, 0xc93f, 0x21, 0 - .dw 0x19c0, 0xc93f, 0x1fff, 0xc93f, 0x21, 0 - .dw 0x2040, 0xc93f, 0x207f, 0xc93f, 0x21, 0 - .dw 0x20c0, 0xc93f, 0x20ff, 0xc93f, 0x21, 0 - .dw 0x2140, 0xc93f, 0x217f, 0xc93f, 0x21, 0 - .dw 0x21c0, 0xc93f, 0x21ff, 0xc93f, 0x21, 0 - .dw 0x2240, 0xc93f, 0x227f, 0xc93f, 0x21, 0 - .dw 0x22c0, 0xc93f, 0x22ff, 0xc93f, 0x21, 0 - .dw 0x2340, 0xc93f, 0x237f, 0xc93f, 0x21, 0 - .dw 0x23c0, 0xc93f, 0x23ff, 0xc93f, 0x21, 0 - .dw 0x2440, 0xc93f, 0x247f, 0xc93f, 0x21, 0 - .dw 0x24c0, 0xc93f, 0x24ff, 0xc93f, 0x21, 0 - .dw 0x2540, 0xc93f, 0x257f, 0xc93f, 0x21, 0 - .dw 0x25c0, 0xc93f, 0x25ff, 0xc93f, 0x21, 0 - .dw 0x2640, 0xc93f, 0x267f, 0xc93f, 0x21, 0 - .dw 0x26c0, 0xc93f, 0x26ff, 0xc93f, 0x21, 0 - .dw 0x2740, 0xc93f, 0x277f, 0xc93f, 0x21, 0 - .dw 0x27c0, 0xc93f, 0x27ff, 0xc93f, 0x21, 0 - .dw 0x2840, 0xc93f, 0x287f, 0xc93f, 0x21, 0 - .dw 0x28c0, 0xc93f, 0x28ff, 0xc93f, 0x21, 0 - .dw 0x2940, 0xc93f, 0x297f, 0xc93f, 0x21, 0 - .dw 0x29c0, 0xc93f, 0x29ff, 0xc93f, 0x21, 0 - .dw 0x2a40, 0xc93f, 0x2a7f, 0xc93f, 0x21, 0 - .dw 0x2ac0, 0xc93f, 0x2aff, 0xc93f, 0x21, 0 - .dw 0x2b40, 0xc93f, 0x2b7f, 0xc93f, 0x21, 0 - .dw 0x2bc0, 0xc93f, 0x2bff, 0xc93f, 0x21, 0 - .dw 0x2c40, 0xc93f, 0x2c7f, 0xc93f, 0x21, 0 - .dw 0x2cc0, 0xc93f, 0x2cff, 0xc93f, 0x21, 0 - .dw 0x2d40, 0xc93f, 0x2d7f, 0xc93f, 0x21, 0 - .dw 0x2dc0, 0xc93f, 0x2dff, 0xc93f, 0x21, 0 - .dw 0x2e40, 0xc93f, 0x2e7f, 0xc93f, 0x21, 0 - .dw 0x2ec0, 0xc93f, 0x2eff, 0xc93f, 0x21, 0 - .dw 0x2f40, 0xc93f, 0x2f7f, 0xc93f, 0x21, 0 - .dw 0x2fc0, 0xc93f, 0x2fff, 0xc93f, 0x21, 0 - .dw 0x3040, 0xc93f, 0x307f, 0xc93f, 0x21, 0 - .dw 0x30c0, 0xc93f, 0x30ff, 0xc93f, 0x21, 0 - .dw 0x3140, 0xc93f, 0x317f, 0xc93f, 0x21, 0 - .dw 0x31c0, 0xc93f, 0x31ff, 0xc93f, 0x21, 0 - .dw 0x3240, 0xc93f, 0x327f, 0xc93f, 0x21, 0 - .dw 0x32c0, 0xc93f, 0x32ff, 0xc93f, 0x21, 0 - .dw 0x3340, 0xc93f, 0x337f, 0xc93f, 0x21, 0 - .dw 0x33c0, 0xc93f, 0x33ff, 0xc93f, 0x21, 0 - .dw 0x3440, 0xc93f, 0x347f, 0xc93f, 0x21, 0 - .dw 0x34c0, 0xc93f, 0x34ff, 0xc93f, 0x21, 0 - .dw 0x3540, 0xc93f, 0x357f, 0xc93f, 0x21, 0 - .dw 0x35c0, 0xc93f, 0x35ff, 0xc93f, 0x21, 0 - .dw 0x3640, 0xc93f, 0x367f, 0xc93f, 0x21, 0 - .dw 0x36c0, 0xc93f, 0x36ff, 0xc93f, 0x21, 0 - .dw 0x3740, 0xc93f, 0x377f, 0xc93f, 0x21, 0 - .dw 0x37c0, 0xc93f, 0x37ff, 0xc93f, 0x21, 0 - .dw 0x3840, 0xc93f, 0x387f, 0xc93f, 0x21, 0 - .dw 0x38c0, 0xc93f, 0x38ff, 0xc93f, 0x21, 0 - .dw 0x3940, 0xc93f, 0x397f, 0xc93f, 0x21, 0 - .dw 0x39c0, 0xc93f, 0x1fff, 0xc960, 0x21, 0 - .dw 0x3a00, 0xc960, 0x5fff, 0xc960, 0x21, 0 - .dw 0x7a00, 0xc960, 0x9fff, 0xc960, 0x21, 0 - .dw 0xba00, 0xc960, 0xdfff, 0xc960, 0x21, 0 - .dw 0xfa00, 0xc960, 0x1fff, 0xc961, 0x21, 0 - .dw 0x3a00, 0xc961, 0x5fff, 0xc961, 0x21, 0 - .dw 0x7a00, 0xc961, 0x9fff, 0xc961, 0x21, 0 - .dw 0xba00, 0xc961, 0xdfff, 0xc961, 0x21, 0 - .dw 0xfa00, 0xc961, 0x1fff, 0xc962, 0x21, 0 - .dw 0x3a00, 0xc962, 0x5fff, 0xc962, 0x21, 0 - .dw 0x7a00, 0xc962, 0x9fff, 0xc962, 0x21, 0 - .dw 0xba00, 0xc962, 0xdfff, 0xc962, 0x21, 0 - .dw 0xfa00, 0xc962, 0x1fff, 0xc963, 0x21, 0 - .dw 0x3a00, 0xc963, 0xffff, 0xc963, 0x21, 0 - .dw 0x1a00, 0xc964, 0x1fff, 0xc964, 0x21, 0 - .dw 0x3a00, 0xc964, 0x3fff, 0xc964, 0x21, 0 - .dw 0x5a00, 0xc964, 0x5fff, 0xc964, 0x21, 0 - .dw 0x7a00, 0xc964, 0x7fff, 0xc964, 0x21, 0 - .dw 0x9a00, 0xc964, 0x9fff, 0xc964, 0x21, 0 - .dw 0xba00, 0xc964, 0xbfff, 0xc964, 0x21, 0 - .dw 0xda00, 0xc964, 0xdfff, 0xc964, 0x21, 0 - .dw 0xfa00, 0xc964, 0xffff, 0xc964, 0x21, 0 - .dw 0x1a00, 0xc965, 0x1fff, 0xc965, 0x21, 0 - .dw 0x3a00, 0xc965, 0x3fff, 0xc965, 0x21, 0 - .dw 0x5a00, 0xc965, 0x5fff, 0xc965, 0x21, 0 - .dw 0x7a00, 0xc965, 0x7fff, 0xc965, 0x21, 0 - .dw 0x9a00, 0xc965, 0x9fff, 0xc965, 0x21, 0 - .dw 0xba00, 0xc965, 0xbfff, 0xc965, 0x21, 0 - .dw 0xda00, 0xc965, 0xdfff, 0xc965, 0x21, 0 - .dw 0xfa00, 0xc965, 0xffff, 0xc965, 0x21, 0 - .dw 0x1a00, 0xc966, 0x1fff, 0xc966, 0x21, 0 - .dw 0x3a00, 0xc966, 0x3fff, 0xc966, 0x21, 0 - .dw 0x5a00, 0xc966, 0x5fff, 0xc966, 0x21, 0 - .dw 0x7a00, 0xc966, 0x7fff, 0xc966, 0x21, 0 - .dw 0x9a00, 0xc966, 0x9fff, 0xc966, 0x21, 0 - .dw 0xba00, 0xc966, 0xbfff, 0xc966, 0x21, 0 - .dw 0xda00, 0xc966, 0xdfff, 0xc966, 0x21, 0 - .dw 0xfa00, 0xc966, 0xffff, 0xc966, 0x21, 0 - .dw 0x1a00, 0xc967, 0x1fff, 0xc967, 0x21, 0 - .dw 0x3a00, 0xc967, 0x1fff, 0xc970, 0x21, 0 - .dw 0x3a00, 0xc970, 0x5fff, 0xc970, 0x21, 0 - .dw 0x7a00, 0xc970, 0x9fff, 0xc970, 0x21, 0 - .dw 0xba00, 0xc970, 0xdfff, 0xc970, 0x21, 0 - .dw 0xfa00, 0xc970, 0x1fff, 0xc971, 0x21, 0 - .dw 0x3a00, 0xc971, 0x5fff, 0xc971, 0x21, 0 - .dw 0x7a00, 0xc971, 0x9fff, 0xc971, 0x21, 0 - .dw 0xba00, 0xc971, 0xdfff, 0xc971, 0x21, 0 - .dw 0xfa00, 0xc971, 0x1fff, 0xc972, 0x21, 0 - .dw 0x3a00, 0xc972, 0x5fff, 0xc972, 0x21, 0 - .dw 0x7a00, 0xc972, 0x9fff, 0xc972, 0x21, 0 - .dw 0xba00, 0xc972, 0xdfff, 0xc972, 0x21, 0 - .dw 0xfa00, 0xc972, 0xffff, 0xc973, 0x21, 0 - .dw 0x1a00, 0xc974, 0x1fff, 0xc974, 0x21, 0 - .dw 0x3a00, 0xc974, 0x3fff, 0xc974, 0x21, 0 - .dw 0x5a00, 0xc974, 0x5fff, 0xc974, 0x21, 0 - .dw 0x7a00, 0xc974, 0x7fff, 0xc974, 0x21, 0 - .dw 0x9a00, 0xc974, 0x9fff, 0xc974, 0x21, 0 - .dw 0xba00, 0xc974, 0xbfff, 0xc974, 0x21, 0 - .dw 0xda00, 0xc974, 0xdfff, 0xc974, 0x21, 0 - .dw 0xfa00, 0xc974, 0xffff, 0xc974, 0x21, 0 - .dw 0x1a00, 0xc975, 0x1fff, 0xc975, 0x21, 0 - .dw 0x3a00, 0xc975, 0x3fff, 0xc975, 0x21, 0 - .dw 0x5a00, 0xc975, 0x5fff, 0xc975, 0x21, 0 - .dw 0x7a00, 0xc975, 0x7fff, 0xc975, 0x21, 0 - .dw 0x9a00, 0xc975, 0x9fff, 0xc975, 0x21, 0 - .dw 0xba00, 0xc975, 0xbfff, 0xc975, 0x21, 0 - .dw 0xda00, 0xc975, 0xdfff, 0xc975, 0x21, 0 - .dw 0xfa00, 0xc975, 0xffff, 0xc975, 0x21, 0 - .dw 0x1a00, 0xc976, 0x1fff, 0xc976, 0x21, 0 - .dw 0x3a00, 0xc976, 0x3fff, 0xc976, 0x21, 0 - .dw 0x5a00, 0xc976, 0x5fff, 0xc976, 0x21, 0 - .dw 0x7a00, 0xc976, 0x7fff, 0xc976, 0x21, 0 - .dw 0x9a00, 0xc976, 0x9fff, 0xc976, 0x21, 0 - .dw 0xba00, 0xc976, 0xbfff, 0xc976, 0x21, 0 - .dw 0xda00, 0xc976, 0xdfff, 0xc976, 0x21, 0 - .dw 0xfa00, 0xc976, 0xffff, 0xc976, 0x21, 0 - .dw 0x1a00, 0xc977, 0x1fff, 0xc977, 0x21, 0 - .dw 0x3a00, 0xc977, 0x1fff, 0xc980, 0x21, 0 - .dw 0x3a00, 0xc980, 0x5fff, 0xc980, 0x21, 0 - .dw 0x7a00, 0xc980, 0x9fff, 0xc980, 0x21, 0 - .dw 0xba00, 0xc980, 0xdfff, 0xc980, 0x21, 0 - .dw 0xfa00, 0xc980, 0x1fff, 0xc981, 0x21, 0 - .dw 0x3a00, 0xc981, 0x5fff, 0xc981, 0x21, 0 - .dw 0x7a00, 0xc981, 0x9fff, 0xc981, 0x21, 0 - .dw 0xba00, 0xc981, 0xdfff, 0xc981, 0x21, 0 - .dw 0xfa00, 0xc981, 0x1fff, 0xc982, 0x21, 0 - .dw 0x3a00, 0xc982, 0x5fff, 0xc982, 0x21, 0 - .dw 0x7a00, 0xc982, 0x9fff, 0xc982, 0x21, 0 - .dw 0xba00, 0xc982, 0xdfff, 0xc982, 0x21, 0 - .dw 0xfa00, 0xc982, 0x1fff, 0xc983, 0x21, 0 - .dw 0x3a00, 0xc983, 0xffff, 0xc983, 0x21, 0 - .dw 0x1a00, 0xc984, 0x1fff, 0xc984, 0x21, 0 - .dw 0x3a00, 0xc984, 0x3fff, 0xc984, 0x21, 0 - .dw 0x5a00, 0xc984, 0x5fff, 0xc984, 0x21, 0 - .dw 0x7a00, 0xc984, 0x7fff, 0xc984, 0x21, 0 - .dw 0x9a00, 0xc984, 0x9fff, 0xc984, 0x21, 0 - .dw 0xba00, 0xc984, 0xbfff, 0xc984, 0x21, 0 - .dw 0xda00, 0xc984, 0xdfff, 0xc984, 0x21, 0 - .dw 0xfa00, 0xc984, 0xffff, 0xc984, 0x21, 0 - .dw 0x1a00, 0xc985, 0x1fff, 0xc985, 0x21, 0 - .dw 0x3a00, 0xc985, 0x3fff, 0xc985, 0x21, 0 - .dw 0x5a00, 0xc985, 0x5fff, 0xc985, 0x21, 0 - .dw 0x7a00, 0xc985, 0x7fff, 0xc985, 0x21, 0 - .dw 0x9a00, 0xc985, 0x9fff, 0xc985, 0x21, 0 - .dw 0xba00, 0xc985, 0xbfff, 0xc985, 0x21, 0 - .dw 0xda00, 0xc985, 0xdfff, 0xc985, 0x21, 0 - .dw 0xfa00, 0xc985, 0xffff, 0xc985, 0x21, 0 - .dw 0x1a00, 0xc986, 0x1fff, 0xc986, 0x21, 0 - .dw 0x3a00, 0xc986, 0x3fff, 0xc986, 0x21, 0 - .dw 0x5a00, 0xc986, 0x5fff, 0xc986, 0x21, 0 - .dw 0x7a00, 0xc986, 0x7fff, 0xc986, 0x21, 0 - .dw 0x9a00, 0xc986, 0x9fff, 0xc986, 0x21, 0 - .dw 0xba00, 0xc986, 0xbfff, 0xc986, 0x21, 0 - .dw 0xda00, 0xc986, 0xdfff, 0xc986, 0x21, 0 - .dw 0xfa00, 0xc986, 0xffff, 0xc986, 0x21, 0 - .dw 0x1a00, 0xc987, 0x1fff, 0xc987, 0x21, 0 - .dw 0x3a00, 0xc987, 0x1fff, 0xc988, 0x21, 0 - .dw 0x2040, 0xc988, 0x207f, 0xc988, 0x21, 0 - .dw 0x20c0, 0xc988, 0x20ff, 0xc988, 0x21, 0 - .dw 0x2140, 0xc988, 0x217f, 0xc988, 0x21, 0 - .dw 0x21c0, 0xc988, 0x21ff, 0xc988, 0x21, 0 - .dw 0x2240, 0xc988, 0x227f, 0xc988, 0x21, 0 - .dw 0x22c0, 0xc988, 0x22ff, 0xc988, 0x21, 0 - .dw 0x2340, 0xc988, 0x237f, 0xc988, 0x21, 0 - .dw 0x23c0, 0xc988, 0x23ff, 0xc988, 0x21, 0 - .dw 0x2440, 0xc988, 0x247f, 0xc988, 0x21, 0 - .dw 0x24c0, 0xc988, 0x24ff, 0xc988, 0x21, 0 - .dw 0x2540, 0xc988, 0x257f, 0xc988, 0x21, 0 - .dw 0x25c0, 0xc988, 0x25ff, 0xc988, 0x21, 0 - .dw 0x2640, 0xc988, 0x267f, 0xc988, 0x21, 0 - .dw 0x26c0, 0xc988, 0x26ff, 0xc988, 0x21, 0 - .dw 0x2740, 0xc988, 0x277f, 0xc988, 0x21, 0 - .dw 0x27c0, 0xc988, 0x27ff, 0xc988, 0x21, 0 - .dw 0x2840, 0xc988, 0x287f, 0xc988, 0x21, 0 - .dw 0x28c0, 0xc988, 0x28ff, 0xc988, 0x21, 0 - .dw 0x2940, 0xc988, 0x297f, 0xc988, 0x21, 0 - .dw 0x29c0, 0xc988, 0x29ff, 0xc988, 0x21, 0 - .dw 0x2a40, 0xc988, 0x2a7f, 0xc988, 0x21, 0 - .dw 0x2ac0, 0xc988, 0x2aff, 0xc988, 0x21, 0 - .dw 0x2b40, 0xc988, 0x2b7f, 0xc988, 0x21, 0 - .dw 0x2bc0, 0xc988, 0x2bff, 0xc988, 0x21, 0 - .dw 0x2c40, 0xc988, 0x2c7f, 0xc988, 0x21, 0 - .dw 0x2cc0, 0xc988, 0x2cff, 0xc988, 0x21, 0 - .dw 0x2d40, 0xc988, 0x2d7f, 0xc988, 0x21, 0 - .dw 0x2dc0, 0xc988, 0x2dff, 0xc988, 0x21, 0 - .dw 0x2e40, 0xc988, 0x2e7f, 0xc988, 0x21, 0 - .dw 0x2ec0, 0xc988, 0x2eff, 0xc988, 0x21, 0 - .dw 0x2f40, 0xc988, 0x2f7f, 0xc988, 0x21, 0 - .dw 0x2fc0, 0xc988, 0x2fff, 0xc988, 0x21, 0 - .dw 0x3040, 0xc988, 0x307f, 0xc988, 0x21, 0 - .dw 0x30c0, 0xc988, 0x30ff, 0xc988, 0x21, 0 - .dw 0x3140, 0xc988, 0x317f, 0xc988, 0x21, 0 - .dw 0x31c0, 0xc988, 0x31ff, 0xc988, 0x21, 0 - .dw 0x3240, 0xc988, 0x327f, 0xc988, 0x21, 0 - .dw 0x32c0, 0xc988, 0x32ff, 0xc988, 0x21, 0 - .dw 0x3340, 0xc988, 0x337f, 0xc988, 0x21, 0 - .dw 0x33c0, 0xc988, 0x33ff, 0xc988, 0x21, 0 - .dw 0x3440, 0xc988, 0x347f, 0xc988, 0x21, 0 - .dw 0x34c0, 0xc988, 0x34ff, 0xc988, 0x21, 0 - .dw 0x3540, 0xc988, 0x357f, 0xc988, 0x21, 0 - .dw 0x35c0, 0xc988, 0x35ff, 0xc988, 0x21, 0 - .dw 0x3640, 0xc988, 0x367f, 0xc988, 0x21, 0 - .dw 0x36c0, 0xc988, 0x36ff, 0xc988, 0x21, 0 - .dw 0x3740, 0xc988, 0x377f, 0xc988, 0x21, 0 - .dw 0x37c0, 0xc988, 0x37ff, 0xc988, 0x21, 0 - .dw 0x3840, 0xc988, 0x387f, 0xc988, 0x21, 0 - .dw 0x38c0, 0xc988, 0x38ff, 0xc988, 0x21, 0 - .dw 0x3940, 0xc988, 0x397f, 0xc988, 0x21, 0 - .dw 0x39c0, 0xc988, 0x5fff, 0xc988, 0x21, 0 - .dw 0x6040, 0xc988, 0x607f, 0xc988, 0x21, 0 - .dw 0x60c0, 0xc988, 0x60ff, 0xc988, 0x21, 0 - .dw 0x6140, 0xc988, 0x617f, 0xc988, 0x21, 0 - .dw 0x61c0, 0xc988, 0x61ff, 0xc988, 0x21, 0 - .dw 0x6240, 0xc988, 0x627f, 0xc988, 0x21, 0 - .dw 0x62c0, 0xc988, 0x62ff, 0xc988, 0x21, 0 - .dw 0x6340, 0xc988, 0x637f, 0xc988, 0x21, 0 - .dw 0x63c0, 0xc988, 0x63ff, 0xc988, 0x21, 0 - .dw 0x6440, 0xc988, 0x647f, 0xc988, 0x21, 0 - .dw 0x64c0, 0xc988, 0x64ff, 0xc988, 0x21, 0 - .dw 0x6540, 0xc988, 0x657f, 0xc988, 0x21, 0 - .dw 0x65c0, 0xc988, 0x65ff, 0xc988, 0x21, 0 - .dw 0x6640, 0xc988, 0x667f, 0xc988, 0x21, 0 - .dw 0x66c0, 0xc988, 0x66ff, 0xc988, 0x21, 0 - .dw 0x6740, 0xc988, 0x677f, 0xc988, 0x21, 0 - .dw 0x67c0, 0xc988, 0x67ff, 0xc988, 0x21, 0 - .dw 0x6840, 0xc988, 0x687f, 0xc988, 0x21, 0 - .dw 0x68c0, 0xc988, 0x68ff, 0xc988, 0x21, 0 - .dw 0x6940, 0xc988, 0x697f, 0xc988, 0x21, 0 - .dw 0x69c0, 0xc988, 0x69ff, 0xc988, 0x21, 0 - .dw 0x6a40, 0xc988, 0x6a7f, 0xc988, 0x21, 0 - .dw 0x6ac0, 0xc988, 0x6aff, 0xc988, 0x21, 0 - .dw 0x6b40, 0xc988, 0x6b7f, 0xc988, 0x21, 0 - .dw 0x6bc0, 0xc988, 0x6bff, 0xc988, 0x21, 0 - .dw 0x6c40, 0xc988, 0x6c7f, 0xc988, 0x21, 0 - .dw 0x6cc0, 0xc988, 0x6cff, 0xc988, 0x21, 0 - .dw 0x6d40, 0xc988, 0x6d7f, 0xc988, 0x21, 0 - .dw 0x6dc0, 0xc988, 0x6dff, 0xc988, 0x21, 0 - .dw 0x6e40, 0xc988, 0x6e7f, 0xc988, 0x21, 0 - .dw 0x6ec0, 0xc988, 0x6eff, 0xc988, 0x21, 0 - .dw 0x6f40, 0xc988, 0x6f7f, 0xc988, 0x21, 0 - .dw 0x6fc0, 0xc988, 0x6fff, 0xc988, 0x21, 0 - .dw 0x7040, 0xc988, 0x707f, 0xc988, 0x21, 0 - .dw 0x70c0, 0xc988, 0x70ff, 0xc988, 0x21, 0 - .dw 0x7140, 0xc988, 0x717f, 0xc988, 0x21, 0 - .dw 0x71c0, 0xc988, 0x71ff, 0xc988, 0x21, 0 - .dw 0x7240, 0xc988, 0x727f, 0xc988, 0x21, 0 - .dw 0x72c0, 0xc988, 0x72ff, 0xc988, 0x21, 0 - .dw 0x7340, 0xc988, 0x737f, 0xc988, 0x21, 0 - .dw 0x73c0, 0xc988, 0x73ff, 0xc988, 0x21, 0 - .dw 0x7440, 0xc988, 0x747f, 0xc988, 0x21, 0 - .dw 0x74c0, 0xc988, 0x74ff, 0xc988, 0x21, 0 - .dw 0x7540, 0xc988, 0x757f, 0xc988, 0x21, 0 - .dw 0x75c0, 0xc988, 0x75ff, 0xc988, 0x21, 0 - .dw 0x7640, 0xc988, 0x767f, 0xc988, 0x21, 0 - .dw 0x76c0, 0xc988, 0x76ff, 0xc988, 0x21, 0 - .dw 0x7740, 0xc988, 0x777f, 0xc988, 0x21, 0 - .dw 0x77c0, 0xc988, 0x77ff, 0xc988, 0x21, 0 - .dw 0x7840, 0xc988, 0x787f, 0xc988, 0x21, 0 - .dw 0x78c0, 0xc988, 0x78ff, 0xc988, 0x21, 0 - .dw 0x7940, 0xc988, 0x797f, 0xc988, 0x21, 0 - .dw 0x79c0, 0xc988, 0x9fff, 0xc988, 0x21, 0 - .dw 0xa040, 0xc988, 0xa07f, 0xc988, 0x21, 0 - .dw 0xa0c0, 0xc988, 0xa0ff, 0xc988, 0x21, 0 - .dw 0xa140, 0xc988, 0xa17f, 0xc988, 0x21, 0 - .dw 0xa1c0, 0xc988, 0xa1ff, 0xc988, 0x21, 0 - .dw 0xa240, 0xc988, 0xa27f, 0xc988, 0x21, 0 - .dw 0xa2c0, 0xc988, 0xa2ff, 0xc988, 0x21, 0 - .dw 0xa340, 0xc988, 0xa37f, 0xc988, 0x21, 0 - .dw 0xa3c0, 0xc988, 0xa3ff, 0xc988, 0x21, 0 - .dw 0xa440, 0xc988, 0xa47f, 0xc988, 0x21, 0 - .dw 0xa4c0, 0xc988, 0xa4ff, 0xc988, 0x21, 0 - .dw 0xa540, 0xc988, 0xa57f, 0xc988, 0x21, 0 - .dw 0xa5c0, 0xc988, 0xa5ff, 0xc988, 0x21, 0 - .dw 0xa640, 0xc988, 0xa67f, 0xc988, 0x21, 0 - .dw 0xa6c0, 0xc988, 0xa6ff, 0xc988, 0x21, 0 - .dw 0xa740, 0xc988, 0xa77f, 0xc988, 0x21, 0 - .dw 0xa7c0, 0xc988, 0xa7ff, 0xc988, 0x21, 0 - .dw 0xa840, 0xc988, 0xa87f, 0xc988, 0x21, 0 - .dw 0xa8c0, 0xc988, 0xa8ff, 0xc988, 0x21, 0 - .dw 0xa940, 0xc988, 0xa97f, 0xc988, 0x21, 0 - .dw 0xa9c0, 0xc988, 0xa9ff, 0xc988, 0x21, 0 - .dw 0xaa40, 0xc988, 0xaa7f, 0xc988, 0x21, 0 - .dw 0xaac0, 0xc988, 0xaaff, 0xc988, 0x21, 0 - .dw 0xab40, 0xc988, 0xab7f, 0xc988, 0x21, 0 - .dw 0xabc0, 0xc988, 0xabff, 0xc988, 0x21, 0 - .dw 0xac40, 0xc988, 0xac7f, 0xc988, 0x21, 0 - .dw 0xacc0, 0xc988, 0xacff, 0xc988, 0x21, 0 - .dw 0xad40, 0xc988, 0xad7f, 0xc988, 0x21, 0 - .dw 0xadc0, 0xc988, 0xadff, 0xc988, 0x21, 0 - .dw 0xae40, 0xc988, 0xae7f, 0xc988, 0x21, 0 - .dw 0xaec0, 0xc988, 0xaeff, 0xc988, 0x21, 0 - .dw 0xaf40, 0xc988, 0xaf7f, 0xc988, 0x21, 0 - .dw 0xafc0, 0xc988, 0xafff, 0xc988, 0x21, 0 - .dw 0xb040, 0xc988, 0xb07f, 0xc988, 0x21, 0 - .dw 0xb0c0, 0xc988, 0xb0ff, 0xc988, 0x21, 0 - .dw 0xb140, 0xc988, 0xb17f, 0xc988, 0x21, 0 - .dw 0xb1c0, 0xc988, 0xb1ff, 0xc988, 0x21, 0 - .dw 0xb240, 0xc988, 0xb27f, 0xc988, 0x21, 0 - .dw 0xb2c0, 0xc988, 0xb2ff, 0xc988, 0x21, 0 - .dw 0xb340, 0xc988, 0xb37f, 0xc988, 0x21, 0 - .dw 0xb3c0, 0xc988, 0xb3ff, 0xc988, 0x21, 0 - .dw 0xb440, 0xc988, 0xb47f, 0xc988, 0x21, 0 - .dw 0xb4c0, 0xc988, 0xb4ff, 0xc988, 0x21, 0 - .dw 0xb540, 0xc988, 0xb57f, 0xc988, 0x21, 0 - .dw 0xb5c0, 0xc988, 0xb5ff, 0xc988, 0x21, 0 - .dw 0xb640, 0xc988, 0xb67f, 0xc988, 0x21, 0 - .dw 0xb6c0, 0xc988, 0xb6ff, 0xc988, 0x21, 0 - .dw 0xb740, 0xc988, 0xb77f, 0xc988, 0x21, 0 - .dw 0xb7c0, 0xc988, 0xb7ff, 0xc988, 0x21, 0 - .dw 0xb840, 0xc988, 0xb87f, 0xc988, 0x21, 0 - .dw 0xb8c0, 0xc988, 0xb8ff, 0xc988, 0x21, 0 - .dw 0xb940, 0xc988, 0xb97f, 0xc988, 0x21, 0 - .dw 0xb9c0, 0xc988, 0xdfff, 0xc988, 0x21, 0 - .dw 0xe040, 0xc988, 0xe07f, 0xc988, 0x21, 0 - .dw 0xe0c0, 0xc988, 0xe0ff, 0xc988, 0x21, 0 - .dw 0xe140, 0xc988, 0xe17f, 0xc988, 0x21, 0 - .dw 0xe1c0, 0xc988, 0xe1ff, 0xc988, 0x21, 0 - .dw 0xe240, 0xc988, 0xe27f, 0xc988, 0x21, 0 - .dw 0xe2c0, 0xc988, 0xe2ff, 0xc988, 0x21, 0 - .dw 0xe340, 0xc988, 0xe37f, 0xc988, 0x21, 0 - .dw 0xe3c0, 0xc988, 0xe3ff, 0xc988, 0x21, 0 - .dw 0xe440, 0xc988, 0xe47f, 0xc988, 0x21, 0 - .dw 0xe4c0, 0xc988, 0xe4ff, 0xc988, 0x21, 0 - .dw 0xe540, 0xc988, 0xe57f, 0xc988, 0x21, 0 - .dw 0xe5c0, 0xc988, 0xe5ff, 0xc988, 0x21, 0 - .dw 0xe640, 0xc988, 0xe67f, 0xc988, 0x21, 0 - .dw 0xe6c0, 0xc988, 0xe6ff, 0xc988, 0x21, 0 - .dw 0xe740, 0xc988, 0xe77f, 0xc988, 0x21, 0 - .dw 0xe7c0, 0xc988, 0xe7ff, 0xc988, 0x21, 0 - .dw 0xe840, 0xc988, 0xe87f, 0xc988, 0x21, 0 - .dw 0xe8c0, 0xc988, 0xe8ff, 0xc988, 0x21, 0 - .dw 0xe940, 0xc988, 0xe97f, 0xc988, 0x21, 0 - .dw 0xe9c0, 0xc988, 0xe9ff, 0xc988, 0x21, 0 - .dw 0xea40, 0xc988, 0xea7f, 0xc988, 0x21, 0 - .dw 0xeac0, 0xc988, 0xeaff, 0xc988, 0x21, 0 - .dw 0xeb40, 0xc988, 0xeb7f, 0xc988, 0x21, 0 - .dw 0xebc0, 0xc988, 0xebff, 0xc988, 0x21, 0 - .dw 0xec40, 0xc988, 0xec7f, 0xc988, 0x21, 0 - .dw 0xecc0, 0xc988, 0xecff, 0xc988, 0x21, 0 - .dw 0xed40, 0xc988, 0xed7f, 0xc988, 0x21, 0 - .dw 0xedc0, 0xc988, 0xedff, 0xc988, 0x21, 0 - .dw 0xee40, 0xc988, 0xee7f, 0xc988, 0x21, 0 - .dw 0xeec0, 0xc988, 0xeeff, 0xc988, 0x21, 0 - .dw 0xef40, 0xc988, 0xef7f, 0xc988, 0x21, 0 - .dw 0xefc0, 0xc988, 0xefff, 0xc988, 0x21, 0 - .dw 0xf040, 0xc988, 0xf07f, 0xc988, 0x21, 0 - .dw 0xf0c0, 0xc988, 0xf0ff, 0xc988, 0x21, 0 - .dw 0xf140, 0xc988, 0xf17f, 0xc988, 0x21, 0 - .dw 0xf1c0, 0xc988, 0xf1ff, 0xc988, 0x21, 0 - .dw 0xf240, 0xc988, 0xf27f, 0xc988, 0x21, 0 - .dw 0xf2c0, 0xc988, 0xf2ff, 0xc988, 0x21, 0 - .dw 0xf340, 0xc988, 0xf37f, 0xc988, 0x21, 0 - .dw 0xf3c0, 0xc988, 0xf3ff, 0xc988, 0x21, 0 - .dw 0xf440, 0xc988, 0xf47f, 0xc988, 0x21, 0 - .dw 0xf4c0, 0xc988, 0xf4ff, 0xc988, 0x21, 0 - .dw 0xf540, 0xc988, 0xf57f, 0xc988, 0x21, 0 - .dw 0xf5c0, 0xc988, 0xf5ff, 0xc988, 0x21, 0 - .dw 0xf640, 0xc988, 0xf67f, 0xc988, 0x21, 0 - .dw 0xf6c0, 0xc988, 0xf6ff, 0xc988, 0x21, 0 - .dw 0xf740, 0xc988, 0xf77f, 0xc988, 0x21, 0 - .dw 0xf7c0, 0xc988, 0xf7ff, 0xc988, 0x21, 0 - .dw 0xf840, 0xc988, 0xf87f, 0xc988, 0x21, 0 - .dw 0xf8c0, 0xc988, 0xf8ff, 0xc988, 0x21, 0 - .dw 0xf940, 0xc988, 0xf97f, 0xc988, 0x21, 0 - .dw 0xf9c0, 0xc988, 0x1fff, 0xc989, 0x21, 0 - .dw 0x2040, 0xc989, 0x207f, 0xc989, 0x21, 0 - .dw 0x20c0, 0xc989, 0x20ff, 0xc989, 0x21, 0 - .dw 0x2140, 0xc989, 0x217f, 0xc989, 0x21, 0 - .dw 0x21c0, 0xc989, 0x21ff, 0xc989, 0x21, 0 - .dw 0x2240, 0xc989, 0x227f, 0xc989, 0x21, 0 - .dw 0x22c0, 0xc989, 0x22ff, 0xc989, 0x21, 0 - .dw 0x2340, 0xc989, 0x237f, 0xc989, 0x21, 0 - .dw 0x23c0, 0xc989, 0x23ff, 0xc989, 0x21, 0 - .dw 0x2440, 0xc989, 0x247f, 0xc989, 0x21, 0 - .dw 0x24c0, 0xc989, 0x24ff, 0xc989, 0x21, 0 - .dw 0x2540, 0xc989, 0x257f, 0xc989, 0x21, 0 - .dw 0x25c0, 0xc989, 0x25ff, 0xc989, 0x21, 0 - .dw 0x2640, 0xc989, 0x267f, 0xc989, 0x21, 0 - .dw 0x26c0, 0xc989, 0x26ff, 0xc989, 0x21, 0 - .dw 0x2740, 0xc989, 0x277f, 0xc989, 0x21, 0 - .dw 0x27c0, 0xc989, 0x27ff, 0xc989, 0x21, 0 - .dw 0x2840, 0xc989, 0x287f, 0xc989, 0x21, 0 - .dw 0x28c0, 0xc989, 0x28ff, 0xc989, 0x21, 0 - .dw 0x2940, 0xc989, 0x297f, 0xc989, 0x21, 0 - .dw 0x29c0, 0xc989, 0x29ff, 0xc989, 0x21, 0 - .dw 0x2a40, 0xc989, 0x2a7f, 0xc989, 0x21, 0 - .dw 0x2ac0, 0xc989, 0x2aff, 0xc989, 0x21, 0 - .dw 0x2b40, 0xc989, 0x2b7f, 0xc989, 0x21, 0 - .dw 0x2bc0, 0xc989, 0x2bff, 0xc989, 0x21, 0 - .dw 0x2c40, 0xc989, 0x2c7f, 0xc989, 0x21, 0 - .dw 0x2cc0, 0xc989, 0x2cff, 0xc989, 0x21, 0 - .dw 0x2d40, 0xc989, 0x2d7f, 0xc989, 0x21, 0 - .dw 0x2dc0, 0xc989, 0x2dff, 0xc989, 0x21, 0 - .dw 0x2e40, 0xc989, 0x2e7f, 0xc989, 0x21, 0 - .dw 0x2ec0, 0xc989, 0x2eff, 0xc989, 0x21, 0 - .dw 0x2f40, 0xc989, 0x2f7f, 0xc989, 0x21, 0 - .dw 0x2fc0, 0xc989, 0x2fff, 0xc989, 0x21, 0 - .dw 0x3040, 0xc989, 0x307f, 0xc989, 0x21, 0 - .dw 0x30c0, 0xc989, 0x30ff, 0xc989, 0x21, 0 - .dw 0x3140, 0xc989, 0x317f, 0xc989, 0x21, 0 - .dw 0x31c0, 0xc989, 0x31ff, 0xc989, 0x21, 0 - .dw 0x3240, 0xc989, 0x327f, 0xc989, 0x21, 0 - .dw 0x32c0, 0xc989, 0x32ff, 0xc989, 0x21, 0 - .dw 0x3340, 0xc989, 0x337f, 0xc989, 0x21, 0 - .dw 0x33c0, 0xc989, 0x33ff, 0xc989, 0x21, 0 - .dw 0x3440, 0xc989, 0x347f, 0xc989, 0x21, 0 - .dw 0x34c0, 0xc989, 0x34ff, 0xc989, 0x21, 0 - .dw 0x3540, 0xc989, 0x357f, 0xc989, 0x21, 0 - .dw 0x35c0, 0xc989, 0x35ff, 0xc989, 0x21, 0 - .dw 0x3640, 0xc989, 0x367f, 0xc989, 0x21, 0 - .dw 0x36c0, 0xc989, 0x36ff, 0xc989, 0x21, 0 - .dw 0x3740, 0xc989, 0x377f, 0xc989, 0x21, 0 - .dw 0x37c0, 0xc989, 0x37ff, 0xc989, 0x21, 0 - .dw 0x3840, 0xc989, 0x387f, 0xc989, 0x21, 0 - .dw 0x38c0, 0xc989, 0x38ff, 0xc989, 0x21, 0 - .dw 0x3940, 0xc989, 0x397f, 0xc989, 0x21, 0 - .dw 0x39c0, 0xc989, 0x5fff, 0xc989, 0x21, 0 - .dw 0x6040, 0xc989, 0x607f, 0xc989, 0x21, 0 - .dw 0x60c0, 0xc989, 0x60ff, 0xc989, 0x21, 0 - .dw 0x6140, 0xc989, 0x617f, 0xc989, 0x21, 0 - .dw 0x61c0, 0xc989, 0x61ff, 0xc989, 0x21, 0 - .dw 0x6240, 0xc989, 0x627f, 0xc989, 0x21, 0 - .dw 0x62c0, 0xc989, 0x62ff, 0xc989, 0x21, 0 - .dw 0x6340, 0xc989, 0x637f, 0xc989, 0x21, 0 - .dw 0x63c0, 0xc989, 0x63ff, 0xc989, 0x21, 0 - .dw 0x6440, 0xc989, 0x647f, 0xc989, 0x21, 0 - .dw 0x64c0, 0xc989, 0x64ff, 0xc989, 0x21, 0 - .dw 0x6540, 0xc989, 0x657f, 0xc989, 0x21, 0 - .dw 0x65c0, 0xc989, 0x65ff, 0xc989, 0x21, 0 - .dw 0x6640, 0xc989, 0x667f, 0xc989, 0x21, 0 - .dw 0x66c0, 0xc989, 0x66ff, 0xc989, 0x21, 0 - .dw 0x6740, 0xc989, 0x677f, 0xc989, 0x21, 0 - .dw 0x67c0, 0xc989, 0x67ff, 0xc989, 0x21, 0 - .dw 0x6840, 0xc989, 0x687f, 0xc989, 0x21, 0 - .dw 0x68c0, 0xc989, 0x68ff, 0xc989, 0x21, 0 - .dw 0x6940, 0xc989, 0x697f, 0xc989, 0x21, 0 - .dw 0x69c0, 0xc989, 0x69ff, 0xc989, 0x21, 0 - .dw 0x6a40, 0xc989, 0x6a7f, 0xc989, 0x21, 0 - .dw 0x6ac0, 0xc989, 0x6aff, 0xc989, 0x21, 0 - .dw 0x6b40, 0xc989, 0x6b7f, 0xc989, 0x21, 0 - .dw 0x6bc0, 0xc989, 0x6bff, 0xc989, 0x21, 0 - .dw 0x6c40, 0xc989, 0x6c7f, 0xc989, 0x21, 0 - .dw 0x6cc0, 0xc989, 0x6cff, 0xc989, 0x21, 0 - .dw 0x6d40, 0xc989, 0x6d7f, 0xc989, 0x21, 0 - .dw 0x6dc0, 0xc989, 0x6dff, 0xc989, 0x21, 0 - .dw 0x6e40, 0xc989, 0x6e7f, 0xc989, 0x21, 0 - .dw 0x6ec0, 0xc989, 0x6eff, 0xc989, 0x21, 0 - .dw 0x6f40, 0xc989, 0x6f7f, 0xc989, 0x21, 0 - .dw 0x6fc0, 0xc989, 0x6fff, 0xc989, 0x21, 0 - .dw 0x7040, 0xc989, 0x707f, 0xc989, 0x21, 0 - .dw 0x70c0, 0xc989, 0x70ff, 0xc989, 0x21, 0 - .dw 0x7140, 0xc989, 0x717f, 0xc989, 0x21, 0 - .dw 0x71c0, 0xc989, 0x71ff, 0xc989, 0x21, 0 - .dw 0x7240, 0xc989, 0x727f, 0xc989, 0x21, 0 - .dw 0x72c0, 0xc989, 0x72ff, 0xc989, 0x21, 0 - .dw 0x7340, 0xc989, 0x737f, 0xc989, 0x21, 0 - .dw 0x73c0, 0xc989, 0x73ff, 0xc989, 0x21, 0 - .dw 0x7440, 0xc989, 0x747f, 0xc989, 0x21, 0 - .dw 0x74c0, 0xc989, 0x74ff, 0xc989, 0x21, 0 - .dw 0x7540, 0xc989, 0x757f, 0xc989, 0x21, 0 - .dw 0x75c0, 0xc989, 0x75ff, 0xc989, 0x21, 0 - .dw 0x7640, 0xc989, 0x767f, 0xc989, 0x21, 0 - .dw 0x76c0, 0xc989, 0x76ff, 0xc989, 0x21, 0 - .dw 0x7740, 0xc989, 0x777f, 0xc989, 0x21, 0 - .dw 0x77c0, 0xc989, 0x77ff, 0xc989, 0x21, 0 - .dw 0x7840, 0xc989, 0x787f, 0xc989, 0x21, 0 - .dw 0x78c0, 0xc989, 0x78ff, 0xc989, 0x21, 0 - .dw 0x7940, 0xc989, 0x797f, 0xc989, 0x21, 0 - .dw 0x79c0, 0xc989, 0x9fff, 0xc989, 0x21, 0 - .dw 0xa040, 0xc989, 0xa07f, 0xc989, 0x21, 0 - .dw 0xa0c0, 0xc989, 0xa0ff, 0xc989, 0x21, 0 - .dw 0xa140, 0xc989, 0xa17f, 0xc989, 0x21, 0 - .dw 0xa1c0, 0xc989, 0xa1ff, 0xc989, 0x21, 0 - .dw 0xa240, 0xc989, 0xa27f, 0xc989, 0x21, 0 - .dw 0xa2c0, 0xc989, 0xa2ff, 0xc989, 0x21, 0 - .dw 0xa340, 0xc989, 0xa37f, 0xc989, 0x21, 0 - .dw 0xa3c0, 0xc989, 0xa3ff, 0xc989, 0x21, 0 - .dw 0xa440, 0xc989, 0xa47f, 0xc989, 0x21, 0 - .dw 0xa4c0, 0xc989, 0xa4ff, 0xc989, 0x21, 0 - .dw 0xa540, 0xc989, 0xa57f, 0xc989, 0x21, 0 - .dw 0xa5c0, 0xc989, 0xa5ff, 0xc989, 0x21, 0 - .dw 0xa640, 0xc989, 0xa67f, 0xc989, 0x21, 0 - .dw 0xa6c0, 0xc989, 0xa6ff, 0xc989, 0x21, 0 - .dw 0xa740, 0xc989, 0xa77f, 0xc989, 0x21, 0 - .dw 0xa7c0, 0xc989, 0xa7ff, 0xc989, 0x21, 0 - .dw 0xa840, 0xc989, 0xa87f, 0xc989, 0x21, 0 - .dw 0xa8c0, 0xc989, 0xa8ff, 0xc989, 0x21, 0 - .dw 0xa940, 0xc989, 0xa97f, 0xc989, 0x21, 0 - .dw 0xa9c0, 0xc989, 0xa9ff, 0xc989, 0x21, 0 - .dw 0xaa40, 0xc989, 0xaa7f, 0xc989, 0x21, 0 - .dw 0xaac0, 0xc989, 0xaaff, 0xc989, 0x21, 0 - .dw 0xab40, 0xc989, 0xab7f, 0xc989, 0x21, 0 - .dw 0xabc0, 0xc989, 0xabff, 0xc989, 0x21, 0 - .dw 0xac40, 0xc989, 0xac7f, 0xc989, 0x21, 0 - .dw 0xacc0, 0xc989, 0xacff, 0xc989, 0x21, 0 - .dw 0xad40, 0xc989, 0xad7f, 0xc989, 0x21, 0 - .dw 0xadc0, 0xc989, 0xadff, 0xc989, 0x21, 0 - .dw 0xae40, 0xc989, 0xae7f, 0xc989, 0x21, 0 - .dw 0xaec0, 0xc989, 0xaeff, 0xc989, 0x21, 0 - .dw 0xaf40, 0xc989, 0xaf7f, 0xc989, 0x21, 0 - .dw 0xafc0, 0xc989, 0xafff, 0xc989, 0x21, 0 - .dw 0xb040, 0xc989, 0xb07f, 0xc989, 0x21, 0 - .dw 0xb0c0, 0xc989, 0xb0ff, 0xc989, 0x21, 0 - .dw 0xb140, 0xc989, 0xb17f, 0xc989, 0x21, 0 - .dw 0xb1c0, 0xc989, 0xb1ff, 0xc989, 0x21, 0 - .dw 0xb240, 0xc989, 0xb27f, 0xc989, 0x21, 0 - .dw 0xb2c0, 0xc989, 0xb2ff, 0xc989, 0x21, 0 - .dw 0xb340, 0xc989, 0xb37f, 0xc989, 0x21, 0 - .dw 0xb3c0, 0xc989, 0xb3ff, 0xc989, 0x21, 0 - .dw 0xb440, 0xc989, 0xb47f, 0xc989, 0x21, 0 - .dw 0xb4c0, 0xc989, 0xb4ff, 0xc989, 0x21, 0 - .dw 0xb540, 0xc989, 0xb57f, 0xc989, 0x21, 0 - .dw 0xb5c0, 0xc989, 0xb5ff, 0xc989, 0x21, 0 - .dw 0xb640, 0xc989, 0xb67f, 0xc989, 0x21, 0 - .dw 0xb6c0, 0xc989, 0xb6ff, 0xc989, 0x21, 0 - .dw 0xb740, 0xc989, 0xb77f, 0xc989, 0x21, 0 - .dw 0xb7c0, 0xc989, 0xb7ff, 0xc989, 0x21, 0 - .dw 0xb840, 0xc989, 0xb87f, 0xc989, 0x21, 0 - .dw 0xb8c0, 0xc989, 0xb8ff, 0xc989, 0x21, 0 - .dw 0xb940, 0xc989, 0xb97f, 0xc989, 0x21, 0 - .dw 0xb9c0, 0xc989, 0xdfff, 0xc989, 0x21, 0 - .dw 0xe040, 0xc989, 0xe07f, 0xc989, 0x21, 0 - .dw 0xe0c0, 0xc989, 0xe0ff, 0xc989, 0x21, 0 - .dw 0xe140, 0xc989, 0xe17f, 0xc989, 0x21, 0 - .dw 0xe1c0, 0xc989, 0xe1ff, 0xc989, 0x21, 0 - .dw 0xe240, 0xc989, 0xe27f, 0xc989, 0x21, 0 - .dw 0xe2c0, 0xc989, 0xe2ff, 0xc989, 0x21, 0 - .dw 0xe340, 0xc989, 0xe37f, 0xc989, 0x21, 0 - .dw 0xe3c0, 0xc989, 0xe3ff, 0xc989, 0x21, 0 - .dw 0xe440, 0xc989, 0xe47f, 0xc989, 0x21, 0 - .dw 0xe4c0, 0xc989, 0xe4ff, 0xc989, 0x21, 0 - .dw 0xe540, 0xc989, 0xe57f, 0xc989, 0x21, 0 - .dw 0xe5c0, 0xc989, 0xe5ff, 0xc989, 0x21, 0 - .dw 0xe640, 0xc989, 0xe67f, 0xc989, 0x21, 0 - .dw 0xe6c0, 0xc989, 0xe6ff, 0xc989, 0x21, 0 - .dw 0xe740, 0xc989, 0xe77f, 0xc989, 0x21, 0 - .dw 0xe7c0, 0xc989, 0xe7ff, 0xc989, 0x21, 0 - .dw 0xe840, 0xc989, 0xe87f, 0xc989, 0x21, 0 - .dw 0xe8c0, 0xc989, 0xe8ff, 0xc989, 0x21, 0 - .dw 0xe940, 0xc989, 0xe97f, 0xc989, 0x21, 0 - .dw 0xe9c0, 0xc989, 0xe9ff, 0xc989, 0x21, 0 - .dw 0xea40, 0xc989, 0xea7f, 0xc989, 0x21, 0 - .dw 0xeac0, 0xc989, 0xeaff, 0xc989, 0x21, 0 - .dw 0xeb40, 0xc989, 0xeb7f, 0xc989, 0x21, 0 - .dw 0xebc0, 0xc989, 0xebff, 0xc989, 0x21, 0 - .dw 0xec40, 0xc989, 0xec7f, 0xc989, 0x21, 0 - .dw 0xecc0, 0xc989, 0xecff, 0xc989, 0x21, 0 - .dw 0xed40, 0xc989, 0xed7f, 0xc989, 0x21, 0 - .dw 0xedc0, 0xc989, 0xedff, 0xc989, 0x21, 0 - .dw 0xee40, 0xc989, 0xee7f, 0xc989, 0x21, 0 - .dw 0xeec0, 0xc989, 0xeeff, 0xc989, 0x21, 0 - .dw 0xef40, 0xc989, 0xef7f, 0xc989, 0x21, 0 - .dw 0xefc0, 0xc989, 0xefff, 0xc989, 0x21, 0 - .dw 0xf040, 0xc989, 0xf07f, 0xc989, 0x21, 0 - .dw 0xf0c0, 0xc989, 0xf0ff, 0xc989, 0x21, 0 - .dw 0xf140, 0xc989, 0xf17f, 0xc989, 0x21, 0 - .dw 0xf1c0, 0xc989, 0xf1ff, 0xc989, 0x21, 0 - .dw 0xf240, 0xc989, 0xf27f, 0xc989, 0x21, 0 - .dw 0xf2c0, 0xc989, 0xf2ff, 0xc989, 0x21, 0 - .dw 0xf340, 0xc989, 0xf37f, 0xc989, 0x21, 0 - .dw 0xf3c0, 0xc989, 0xf3ff, 0xc989, 0x21, 0 - .dw 0xf440, 0xc989, 0xf47f, 0xc989, 0x21, 0 - .dw 0xf4c0, 0xc989, 0xf4ff, 0xc989, 0x21, 0 - .dw 0xf540, 0xc989, 0xf57f, 0xc989, 0x21, 0 - .dw 0xf5c0, 0xc989, 0xf5ff, 0xc989, 0x21, 0 - .dw 0xf640, 0xc989, 0xf67f, 0xc989, 0x21, 0 - .dw 0xf6c0, 0xc989, 0xf6ff, 0xc989, 0x21, 0 - .dw 0xf740, 0xc989, 0xf77f, 0xc989, 0x21, 0 - .dw 0xf7c0, 0xc989, 0xf7ff, 0xc989, 0x21, 0 - .dw 0xf840, 0xc989, 0xf87f, 0xc989, 0x21, 0 - .dw 0xf8c0, 0xc989, 0xf8ff, 0xc989, 0x21, 0 - .dw 0xf940, 0xc989, 0xf97f, 0xc989, 0x21, 0 - .dw 0xf9c0, 0xc989, 0x1fff, 0xc98a, 0x21, 0 - .dw 0x2040, 0xc98a, 0x207f, 0xc98a, 0x21, 0 - .dw 0x20c0, 0xc98a, 0x20ff, 0xc98a, 0x21, 0 - .dw 0x2140, 0xc98a, 0x217f, 0xc98a, 0x21, 0 - .dw 0x21c0, 0xc98a, 0x21ff, 0xc98a, 0x21, 0 - .dw 0x2240, 0xc98a, 0x227f, 0xc98a, 0x21, 0 - .dw 0x22c0, 0xc98a, 0x22ff, 0xc98a, 0x21, 0 - .dw 0x2340, 0xc98a, 0x237f, 0xc98a, 0x21, 0 - .dw 0x23c0, 0xc98a, 0x23ff, 0xc98a, 0x21, 0 - .dw 0x2440, 0xc98a, 0x247f, 0xc98a, 0x21, 0 - .dw 0x24c0, 0xc98a, 0x24ff, 0xc98a, 0x21, 0 - .dw 0x2540, 0xc98a, 0x257f, 0xc98a, 0x21, 0 - .dw 0x25c0, 0xc98a, 0x25ff, 0xc98a, 0x21, 0 - .dw 0x2640, 0xc98a, 0x267f, 0xc98a, 0x21, 0 - .dw 0x26c0, 0xc98a, 0x26ff, 0xc98a, 0x21, 0 - .dw 0x2740, 0xc98a, 0x277f, 0xc98a, 0x21, 0 - .dw 0x27c0, 0xc98a, 0x27ff, 0xc98a, 0x21, 0 - .dw 0x2840, 0xc98a, 0x287f, 0xc98a, 0x21, 0 - .dw 0x28c0, 0xc98a, 0x28ff, 0xc98a, 0x21, 0 - .dw 0x2940, 0xc98a, 0x297f, 0xc98a, 0x21, 0 - .dw 0x29c0, 0xc98a, 0x29ff, 0xc98a, 0x21, 0 - .dw 0x2a40, 0xc98a, 0x2a7f, 0xc98a, 0x21, 0 - .dw 0x2ac0, 0xc98a, 0x2aff, 0xc98a, 0x21, 0 - .dw 0x2b40, 0xc98a, 0x2b7f, 0xc98a, 0x21, 0 - .dw 0x2bc0, 0xc98a, 0x2bff, 0xc98a, 0x21, 0 - .dw 0x2c40, 0xc98a, 0x2c7f, 0xc98a, 0x21, 0 - .dw 0x2cc0, 0xc98a, 0x2cff, 0xc98a, 0x21, 0 - .dw 0x2d40, 0xc98a, 0x2d7f, 0xc98a, 0x21, 0 - .dw 0x2dc0, 0xc98a, 0x2dff, 0xc98a, 0x21, 0 - .dw 0x2e40, 0xc98a, 0x2e7f, 0xc98a, 0x21, 0 - .dw 0x2ec0, 0xc98a, 0x2eff, 0xc98a, 0x21, 0 - .dw 0x2f40, 0xc98a, 0x2f7f, 0xc98a, 0x21, 0 - .dw 0x2fc0, 0xc98a, 0x2fff, 0xc98a, 0x21, 0 - .dw 0x3040, 0xc98a, 0x307f, 0xc98a, 0x21, 0 - .dw 0x30c0, 0xc98a, 0x30ff, 0xc98a, 0x21, 0 - .dw 0x3140, 0xc98a, 0x317f, 0xc98a, 0x21, 0 - .dw 0x31c0, 0xc98a, 0x31ff, 0xc98a, 0x21, 0 - .dw 0x3240, 0xc98a, 0x327f, 0xc98a, 0x21, 0 - .dw 0x32c0, 0xc98a, 0x32ff, 0xc98a, 0x21, 0 - .dw 0x3340, 0xc98a, 0x337f, 0xc98a, 0x21, 0 - .dw 0x33c0, 0xc98a, 0x33ff, 0xc98a, 0x21, 0 - .dw 0x3440, 0xc98a, 0x347f, 0xc98a, 0x21, 0 - .dw 0x34c0, 0xc98a, 0x34ff, 0xc98a, 0x21, 0 - .dw 0x3540, 0xc98a, 0x357f, 0xc98a, 0x21, 0 - .dw 0x35c0, 0xc98a, 0x35ff, 0xc98a, 0x21, 0 - .dw 0x3640, 0xc98a, 0x367f, 0xc98a, 0x21, 0 - .dw 0x36c0, 0xc98a, 0x36ff, 0xc98a, 0x21, 0 - .dw 0x3740, 0xc98a, 0x377f, 0xc98a, 0x21, 0 - .dw 0x37c0, 0xc98a, 0x37ff, 0xc98a, 0x21, 0 - .dw 0x3840, 0xc98a, 0x387f, 0xc98a, 0x21, 0 - .dw 0x38c0, 0xc98a, 0x38ff, 0xc98a, 0x21, 0 - .dw 0x3940, 0xc98a, 0x397f, 0xc98a, 0x21, 0 - .dw 0x39c0, 0xc98a, 0x5fff, 0xc98a, 0x21, 0 - .dw 0x6040, 0xc98a, 0x607f, 0xc98a, 0x21, 0 - .dw 0x60c0, 0xc98a, 0x60ff, 0xc98a, 0x21, 0 - .dw 0x6140, 0xc98a, 0x617f, 0xc98a, 0x21, 0 - .dw 0x61c0, 0xc98a, 0x61ff, 0xc98a, 0x21, 0 - .dw 0x6240, 0xc98a, 0x627f, 0xc98a, 0x21, 0 - .dw 0x62c0, 0xc98a, 0x62ff, 0xc98a, 0x21, 0 - .dw 0x6340, 0xc98a, 0x637f, 0xc98a, 0x21, 0 - .dw 0x63c0, 0xc98a, 0x63ff, 0xc98a, 0x21, 0 - .dw 0x6440, 0xc98a, 0x647f, 0xc98a, 0x21, 0 - .dw 0x64c0, 0xc98a, 0x64ff, 0xc98a, 0x21, 0 - .dw 0x6540, 0xc98a, 0x657f, 0xc98a, 0x21, 0 - .dw 0x65c0, 0xc98a, 0x65ff, 0xc98a, 0x21, 0 - .dw 0x6640, 0xc98a, 0x667f, 0xc98a, 0x21, 0 - .dw 0x66c0, 0xc98a, 0x66ff, 0xc98a, 0x21, 0 - .dw 0x6740, 0xc98a, 0x677f, 0xc98a, 0x21, 0 - .dw 0x67c0, 0xc98a, 0x67ff, 0xc98a, 0x21, 0 - .dw 0x6840, 0xc98a, 0x687f, 0xc98a, 0x21, 0 - .dw 0x68c0, 0xc98a, 0x68ff, 0xc98a, 0x21, 0 - .dw 0x6940, 0xc98a, 0x697f, 0xc98a, 0x21, 0 - .dw 0x69c0, 0xc98a, 0x69ff, 0xc98a, 0x21, 0 - .dw 0x6a40, 0xc98a, 0x6a7f, 0xc98a, 0x21, 0 - .dw 0x6ac0, 0xc98a, 0x6aff, 0xc98a, 0x21, 0 - .dw 0x6b40, 0xc98a, 0x6b7f, 0xc98a, 0x21, 0 - .dw 0x6bc0, 0xc98a, 0x6bff, 0xc98a, 0x21, 0 - .dw 0x6c40, 0xc98a, 0x6c7f, 0xc98a, 0x21, 0 - .dw 0x6cc0, 0xc98a, 0x6cff, 0xc98a, 0x21, 0 - .dw 0x6d40, 0xc98a, 0x6d7f, 0xc98a, 0x21, 0 - .dw 0x6dc0, 0xc98a, 0x6dff, 0xc98a, 0x21, 0 - .dw 0x6e40, 0xc98a, 0x6e7f, 0xc98a, 0x21, 0 - .dw 0x6ec0, 0xc98a, 0x6eff, 0xc98a, 0x21, 0 - .dw 0x6f40, 0xc98a, 0x6f7f, 0xc98a, 0x21, 0 - .dw 0x6fc0, 0xc98a, 0x6fff, 0xc98a, 0x21, 0 - .dw 0x7040, 0xc98a, 0x707f, 0xc98a, 0x21, 0 - .dw 0x70c0, 0xc98a, 0x70ff, 0xc98a, 0x21, 0 - .dw 0x7140, 0xc98a, 0x717f, 0xc98a, 0x21, 0 - .dw 0x71c0, 0xc98a, 0x71ff, 0xc98a, 0x21, 0 - .dw 0x7240, 0xc98a, 0x727f, 0xc98a, 0x21, 0 - .dw 0x72c0, 0xc98a, 0x72ff, 0xc98a, 0x21, 0 - .dw 0x7340, 0xc98a, 0x737f, 0xc98a, 0x21, 0 - .dw 0x73c0, 0xc98a, 0x73ff, 0xc98a, 0x21, 0 - .dw 0x7440, 0xc98a, 0x747f, 0xc98a, 0x21, 0 - .dw 0x74c0, 0xc98a, 0x74ff, 0xc98a, 0x21, 0 - .dw 0x7540, 0xc98a, 0x757f, 0xc98a, 0x21, 0 - .dw 0x75c0, 0xc98a, 0x75ff, 0xc98a, 0x21, 0 - .dw 0x7640, 0xc98a, 0x767f, 0xc98a, 0x21, 0 - .dw 0x76c0, 0xc98a, 0x76ff, 0xc98a, 0x21, 0 - .dw 0x7740, 0xc98a, 0x777f, 0xc98a, 0x21, 0 - .dw 0x77c0, 0xc98a, 0x77ff, 0xc98a, 0x21, 0 - .dw 0x7840, 0xc98a, 0x787f, 0xc98a, 0x21, 0 - .dw 0x78c0, 0xc98a, 0x78ff, 0xc98a, 0x21, 0 - .dw 0x7940, 0xc98a, 0x797f, 0xc98a, 0x21, 0 - .dw 0x79c0, 0xc98a, 0x9fff, 0xc98a, 0x21, 0 - .dw 0xa040, 0xc98a, 0xa07f, 0xc98a, 0x21, 0 - .dw 0xa0c0, 0xc98a, 0xa0ff, 0xc98a, 0x21, 0 - .dw 0xa140, 0xc98a, 0xa17f, 0xc98a, 0x21, 0 - .dw 0xa1c0, 0xc98a, 0xa1ff, 0xc98a, 0x21, 0 - .dw 0xa240, 0xc98a, 0xa27f, 0xc98a, 0x21, 0 - .dw 0xa2c0, 0xc98a, 0xa2ff, 0xc98a, 0x21, 0 - .dw 0xa340, 0xc98a, 0xa37f, 0xc98a, 0x21, 0 - .dw 0xa3c0, 0xc98a, 0xa3ff, 0xc98a, 0x21, 0 - .dw 0xa440, 0xc98a, 0xa47f, 0xc98a, 0x21, 0 - .dw 0xa4c0, 0xc98a, 0xa4ff, 0xc98a, 0x21, 0 - .dw 0xa540, 0xc98a, 0xa57f, 0xc98a, 0x21, 0 - .dw 0xa5c0, 0xc98a, 0xa5ff, 0xc98a, 0x21, 0 - .dw 0xa640, 0xc98a, 0xa67f, 0xc98a, 0x21, 0 - .dw 0xa6c0, 0xc98a, 0xa6ff, 0xc98a, 0x21, 0 - .dw 0xa740, 0xc98a, 0xa77f, 0xc98a, 0x21, 0 - .dw 0xa7c0, 0xc98a, 0xa7ff, 0xc98a, 0x21, 0 - .dw 0xa840, 0xc98a, 0xa87f, 0xc98a, 0x21, 0 - .dw 0xa8c0, 0xc98a, 0xa8ff, 0xc98a, 0x21, 0 - .dw 0xa940, 0xc98a, 0xa97f, 0xc98a, 0x21, 0 - .dw 0xa9c0, 0xc98a, 0xa9ff, 0xc98a, 0x21, 0 - .dw 0xaa40, 0xc98a, 0xaa7f, 0xc98a, 0x21, 0 - .dw 0xaac0, 0xc98a, 0xaaff, 0xc98a, 0x21, 0 - .dw 0xab40, 0xc98a, 0xab7f, 0xc98a, 0x21, 0 - .dw 0xabc0, 0xc98a, 0xabff, 0xc98a, 0x21, 0 - .dw 0xac40, 0xc98a, 0xac7f, 0xc98a, 0x21, 0 - .dw 0xacc0, 0xc98a, 0xacff, 0xc98a, 0x21, 0 - .dw 0xad40, 0xc98a, 0xad7f, 0xc98a, 0x21, 0 - .dw 0xadc0, 0xc98a, 0xadff, 0xc98a, 0x21, 0 - .dw 0xae40, 0xc98a, 0xae7f, 0xc98a, 0x21, 0 - .dw 0xaec0, 0xc98a, 0xaeff, 0xc98a, 0x21, 0 - .dw 0xaf40, 0xc98a, 0xaf7f, 0xc98a, 0x21, 0 - .dw 0xafc0, 0xc98a, 0xafff, 0xc98a, 0x21, 0 - .dw 0xb040, 0xc98a, 0xb07f, 0xc98a, 0x21, 0 - .dw 0xb0c0, 0xc98a, 0xb0ff, 0xc98a, 0x21, 0 - .dw 0xb140, 0xc98a, 0xb17f, 0xc98a, 0x21, 0 - .dw 0xb1c0, 0xc98a, 0xb1ff, 0xc98a, 0x21, 0 - .dw 0xb240, 0xc98a, 0xb27f, 0xc98a, 0x21, 0 - .dw 0xb2c0, 0xc98a, 0xb2ff, 0xc98a, 0x21, 0 - .dw 0xb340, 0xc98a, 0xb37f, 0xc98a, 0x21, 0 - .dw 0xb3c0, 0xc98a, 0xb3ff, 0xc98a, 0x21, 0 - .dw 0xb440, 0xc98a, 0xb47f, 0xc98a, 0x21, 0 - .dw 0xb4c0, 0xc98a, 0xb4ff, 0xc98a, 0x21, 0 - .dw 0xb540, 0xc98a, 0xb57f, 0xc98a, 0x21, 0 - .dw 0xb5c0, 0xc98a, 0xb5ff, 0xc98a, 0x21, 0 - .dw 0xb640, 0xc98a, 0xb67f, 0xc98a, 0x21, 0 - .dw 0xb6c0, 0xc98a, 0xb6ff, 0xc98a, 0x21, 0 - .dw 0xb740, 0xc98a, 0xb77f, 0xc98a, 0x21, 0 - .dw 0xb7c0, 0xc98a, 0xb7ff, 0xc98a, 0x21, 0 - .dw 0xb840, 0xc98a, 0xb87f, 0xc98a, 0x21, 0 - .dw 0xb8c0, 0xc98a, 0xb8ff, 0xc98a, 0x21, 0 - .dw 0xb940, 0xc98a, 0xb97f, 0xc98a, 0x21, 0 - .dw 0xb9c0, 0xc98a, 0xdfff, 0xc98a, 0x21, 0 - .dw 0xe040, 0xc98a, 0xe07f, 0xc98a, 0x21, 0 - .dw 0xe0c0, 0xc98a, 0xe0ff, 0xc98a, 0x21, 0 - .dw 0xe140, 0xc98a, 0xe17f, 0xc98a, 0x21, 0 - .dw 0xe1c0, 0xc98a, 0xe1ff, 0xc98a, 0x21, 0 - .dw 0xe240, 0xc98a, 0xe27f, 0xc98a, 0x21, 0 - .dw 0xe2c0, 0xc98a, 0xe2ff, 0xc98a, 0x21, 0 - .dw 0xe340, 0xc98a, 0xe37f, 0xc98a, 0x21, 0 - .dw 0xe3c0, 0xc98a, 0xe3ff, 0xc98a, 0x21, 0 - .dw 0xe440, 0xc98a, 0xe47f, 0xc98a, 0x21, 0 - .dw 0xe4c0, 0xc98a, 0xe4ff, 0xc98a, 0x21, 0 - .dw 0xe540, 0xc98a, 0xe57f, 0xc98a, 0x21, 0 - .dw 0xe5c0, 0xc98a, 0xe5ff, 0xc98a, 0x21, 0 - .dw 0xe640, 0xc98a, 0xe67f, 0xc98a, 0x21, 0 - .dw 0xe6c0, 0xc98a, 0xe6ff, 0xc98a, 0x21, 0 - .dw 0xe740, 0xc98a, 0xe77f, 0xc98a, 0x21, 0 - .dw 0xe7c0, 0xc98a, 0xe7ff, 0xc98a, 0x21, 0 - .dw 0xe840, 0xc98a, 0xe87f, 0xc98a, 0x21, 0 - .dw 0xe8c0, 0xc98a, 0xe8ff, 0xc98a, 0x21, 0 - .dw 0xe940, 0xc98a, 0xe97f, 0xc98a, 0x21, 0 - .dw 0xe9c0, 0xc98a, 0xe9ff, 0xc98a, 0x21, 0 - .dw 0xea40, 0xc98a, 0xea7f, 0xc98a, 0x21, 0 - .dw 0xeac0, 0xc98a, 0xeaff, 0xc98a, 0x21, 0 - .dw 0xeb40, 0xc98a, 0xeb7f, 0xc98a, 0x21, 0 - .dw 0xebc0, 0xc98a, 0xebff, 0xc98a, 0x21, 0 - .dw 0xec40, 0xc98a, 0xec7f, 0xc98a, 0x21, 0 - .dw 0xecc0, 0xc98a, 0xecff, 0xc98a, 0x21, 0 - .dw 0xed40, 0xc98a, 0xed7f, 0xc98a, 0x21, 0 - .dw 0xedc0, 0xc98a, 0xedff, 0xc98a, 0x21, 0 - .dw 0xee40, 0xc98a, 0xee7f, 0xc98a, 0x21, 0 - .dw 0xeec0, 0xc98a, 0xeeff, 0xc98a, 0x21, 0 - .dw 0xef40, 0xc98a, 0xef7f, 0xc98a, 0x21, 0 - .dw 0xefc0, 0xc98a, 0xefff, 0xc98a, 0x21, 0 - .dw 0xf040, 0xc98a, 0xf07f, 0xc98a, 0x21, 0 - .dw 0xf0c0, 0xc98a, 0xf0ff, 0xc98a, 0x21, 0 - .dw 0xf140, 0xc98a, 0xf17f, 0xc98a, 0x21, 0 - .dw 0xf1c0, 0xc98a, 0xf1ff, 0xc98a, 0x21, 0 - .dw 0xf240, 0xc98a, 0xf27f, 0xc98a, 0x21, 0 - .dw 0xf2c0, 0xc98a, 0xf2ff, 0xc98a, 0x21, 0 - .dw 0xf340, 0xc98a, 0xf37f, 0xc98a, 0x21, 0 - .dw 0xf3c0, 0xc98a, 0xf3ff, 0xc98a, 0x21, 0 - .dw 0xf440, 0xc98a, 0xf47f, 0xc98a, 0x21, 0 - .dw 0xf4c0, 0xc98a, 0xf4ff, 0xc98a, 0x21, 0 - .dw 0xf540, 0xc98a, 0xf57f, 0xc98a, 0x21, 0 - .dw 0xf5c0, 0xc98a, 0xf5ff, 0xc98a, 0x21, 0 - .dw 0xf640, 0xc98a, 0xf67f, 0xc98a, 0x21, 0 - .dw 0xf6c0, 0xc98a, 0xf6ff, 0xc98a, 0x21, 0 - .dw 0xf740, 0xc98a, 0xf77f, 0xc98a, 0x21, 0 - .dw 0xf7c0, 0xc98a, 0xf7ff, 0xc98a, 0x21, 0 - .dw 0xf840, 0xc98a, 0xf87f, 0xc98a, 0x21, 0 - .dw 0xf8c0, 0xc98a, 0xf8ff, 0xc98a, 0x21, 0 - .dw 0xf940, 0xc98a, 0xf97f, 0xc98a, 0x21, 0 - .dw 0xf9c0, 0xc98a, 0x1fff, 0xc98b, 0x21, 0 - .dw 0x2040, 0xc98b, 0x207f, 0xc98b, 0x21, 0 - .dw 0x20c0, 0xc98b, 0x20ff, 0xc98b, 0x21, 0 - .dw 0x2140, 0xc98b, 0x217f, 0xc98b, 0x21, 0 - .dw 0x21c0, 0xc98b, 0x21ff, 0xc98b, 0x21, 0 - .dw 0x2240, 0xc98b, 0x227f, 0xc98b, 0x21, 0 - .dw 0x22c0, 0xc98b, 0x22ff, 0xc98b, 0x21, 0 - .dw 0x2340, 0xc98b, 0x237f, 0xc98b, 0x21, 0 - .dw 0x23c0, 0xc98b, 0x23ff, 0xc98b, 0x21, 0 - .dw 0x2440, 0xc98b, 0x247f, 0xc98b, 0x21, 0 - .dw 0x24c0, 0xc98b, 0x24ff, 0xc98b, 0x21, 0 - .dw 0x2540, 0xc98b, 0x257f, 0xc98b, 0x21, 0 - .dw 0x25c0, 0xc98b, 0x25ff, 0xc98b, 0x21, 0 - .dw 0x2640, 0xc98b, 0x267f, 0xc98b, 0x21, 0 - .dw 0x26c0, 0xc98b, 0x26ff, 0xc98b, 0x21, 0 - .dw 0x2740, 0xc98b, 0x277f, 0xc98b, 0x21, 0 - .dw 0x27c0, 0xc98b, 0x27ff, 0xc98b, 0x21, 0 - .dw 0x2840, 0xc98b, 0x287f, 0xc98b, 0x21, 0 - .dw 0x28c0, 0xc98b, 0x28ff, 0xc98b, 0x21, 0 - .dw 0x2940, 0xc98b, 0x297f, 0xc98b, 0x21, 0 - .dw 0x29c0, 0xc98b, 0x29ff, 0xc98b, 0x21, 0 - .dw 0x2a40, 0xc98b, 0x2a7f, 0xc98b, 0x21, 0 - .dw 0x2ac0, 0xc98b, 0x2aff, 0xc98b, 0x21, 0 - .dw 0x2b40, 0xc98b, 0x2b7f, 0xc98b, 0x21, 0 - .dw 0x2bc0, 0xc98b, 0x2bff, 0xc98b, 0x21, 0 - .dw 0x2c40, 0xc98b, 0x2c7f, 0xc98b, 0x21, 0 - .dw 0x2cc0, 0xc98b, 0x2cff, 0xc98b, 0x21, 0 - .dw 0x2d40, 0xc98b, 0x2d7f, 0xc98b, 0x21, 0 - .dw 0x2dc0, 0xc98b, 0x2dff, 0xc98b, 0x21, 0 - .dw 0x2e40, 0xc98b, 0x2e7f, 0xc98b, 0x21, 0 - .dw 0x2ec0, 0xc98b, 0x2eff, 0xc98b, 0x21, 0 - .dw 0x2f40, 0xc98b, 0x2f7f, 0xc98b, 0x21, 0 - .dw 0x2fc0, 0xc98b, 0x2fff, 0xc98b, 0x21, 0 - .dw 0x3040, 0xc98b, 0x307f, 0xc98b, 0x21, 0 - .dw 0x30c0, 0xc98b, 0x30ff, 0xc98b, 0x21, 0 - .dw 0x3140, 0xc98b, 0x317f, 0xc98b, 0x21, 0 - .dw 0x31c0, 0xc98b, 0x31ff, 0xc98b, 0x21, 0 - .dw 0x3240, 0xc98b, 0x327f, 0xc98b, 0x21, 0 - .dw 0x32c0, 0xc98b, 0x32ff, 0xc98b, 0x21, 0 - .dw 0x3340, 0xc98b, 0x337f, 0xc98b, 0x21, 0 - .dw 0x33c0, 0xc98b, 0x33ff, 0xc98b, 0x21, 0 - .dw 0x3440, 0xc98b, 0x347f, 0xc98b, 0x21, 0 - .dw 0x34c0, 0xc98b, 0x34ff, 0xc98b, 0x21, 0 - .dw 0x3540, 0xc98b, 0x357f, 0xc98b, 0x21, 0 - .dw 0x35c0, 0xc98b, 0x35ff, 0xc98b, 0x21, 0 - .dw 0x3640, 0xc98b, 0x367f, 0xc98b, 0x21, 0 - .dw 0x36c0, 0xc98b, 0x36ff, 0xc98b, 0x21, 0 - .dw 0x3740, 0xc98b, 0x377f, 0xc98b, 0x21, 0 - .dw 0x37c0, 0xc98b, 0x37ff, 0xc98b, 0x21, 0 - .dw 0x3840, 0xc98b, 0x387f, 0xc98b, 0x21, 0 - .dw 0x38c0, 0xc98b, 0x38ff, 0xc98b, 0x21, 0 - .dw 0x3940, 0xc98b, 0x397f, 0xc98b, 0x21, 0 - .dw 0x39c0, 0xc98b, 0xffff, 0xc98b, 0x21, 0 - .dw 0x0040, 0xc98c, 0x007f, 0xc98c, 0x21, 0 - .dw 0x00c0, 0xc98c, 0x00ff, 0xc98c, 0x21, 0 - .dw 0x0140, 0xc98c, 0x017f, 0xc98c, 0x21, 0 - .dw 0x01c0, 0xc98c, 0x01ff, 0xc98c, 0x21, 0 - .dw 0x0240, 0xc98c, 0x027f, 0xc98c, 0x21, 0 - .dw 0x02c0, 0xc98c, 0x02ff, 0xc98c, 0x21, 0 - .dw 0x0340, 0xc98c, 0x037f, 0xc98c, 0x21, 0 - .dw 0x03c0, 0xc98c, 0x03ff, 0xc98c, 0x21, 0 - .dw 0x0440, 0xc98c, 0x047f, 0xc98c, 0x21, 0 - .dw 0x04c0, 0xc98c, 0x04ff, 0xc98c, 0x21, 0 - .dw 0x0540, 0xc98c, 0x057f, 0xc98c, 0x21, 0 - .dw 0x05c0, 0xc98c, 0x05ff, 0xc98c, 0x21, 0 - .dw 0x0640, 0xc98c, 0x067f, 0xc98c, 0x21, 0 - .dw 0x06c0, 0xc98c, 0x06ff, 0xc98c, 0x21, 0 - .dw 0x0740, 0xc98c, 0x077f, 0xc98c, 0x21, 0 - .dw 0x07c0, 0xc98c, 0x07ff, 0xc98c, 0x21, 0 - .dw 0x0840, 0xc98c, 0x087f, 0xc98c, 0x21, 0 - .dw 0x08c0, 0xc98c, 0x08ff, 0xc98c, 0x21, 0 - .dw 0x0940, 0xc98c, 0x097f, 0xc98c, 0x21, 0 - .dw 0x09c0, 0xc98c, 0x09ff, 0xc98c, 0x21, 0 - .dw 0x0a40, 0xc98c, 0x0a7f, 0xc98c, 0x21, 0 - .dw 0x0ac0, 0xc98c, 0x0aff, 0xc98c, 0x21, 0 - .dw 0x0b40, 0xc98c, 0x0b7f, 0xc98c, 0x21, 0 - .dw 0x0bc0, 0xc98c, 0x0bff, 0xc98c, 0x21, 0 - .dw 0x0c40, 0xc98c, 0x0c7f, 0xc98c, 0x21, 0 - .dw 0x0cc0, 0xc98c, 0x0cff, 0xc98c, 0x21, 0 - .dw 0x0d40, 0xc98c, 0x0d7f, 0xc98c, 0x21, 0 - .dw 0x0dc0, 0xc98c, 0x0dff, 0xc98c, 0x21, 0 - .dw 0x0e40, 0xc98c, 0x0e7f, 0xc98c, 0x21, 0 - .dw 0x0ec0, 0xc98c, 0x0eff, 0xc98c, 0x21, 0 - .dw 0x0f40, 0xc98c, 0x0f7f, 0xc98c, 0x21, 0 - .dw 0x0fc0, 0xc98c, 0x0fff, 0xc98c, 0x21, 0 - .dw 0x1040, 0xc98c, 0x107f, 0xc98c, 0x21, 0 - .dw 0x10c0, 0xc98c, 0x10ff, 0xc98c, 0x21, 0 - .dw 0x1140, 0xc98c, 0x117f, 0xc98c, 0x21, 0 - .dw 0x11c0, 0xc98c, 0x11ff, 0xc98c, 0x21, 0 - .dw 0x1240, 0xc98c, 0x127f, 0xc98c, 0x21, 0 - .dw 0x12c0, 0xc98c, 0x12ff, 0xc98c, 0x21, 0 - .dw 0x1340, 0xc98c, 0x137f, 0xc98c, 0x21, 0 - .dw 0x13c0, 0xc98c, 0x13ff, 0xc98c, 0x21, 0 - .dw 0x1440, 0xc98c, 0x147f, 0xc98c, 0x21, 0 - .dw 0x14c0, 0xc98c, 0x14ff, 0xc98c, 0x21, 0 - .dw 0x1540, 0xc98c, 0x157f, 0xc98c, 0x21, 0 - .dw 0x15c0, 0xc98c, 0x15ff, 0xc98c, 0x21, 0 - .dw 0x1640, 0xc98c, 0x167f, 0xc98c, 0x21, 0 - .dw 0x16c0, 0xc98c, 0x16ff, 0xc98c, 0x21, 0 - .dw 0x1740, 0xc98c, 0x177f, 0xc98c, 0x21, 0 - .dw 0x17c0, 0xc98c, 0x17ff, 0xc98c, 0x21, 0 - .dw 0x1840, 0xc98c, 0x187f, 0xc98c, 0x21, 0 - .dw 0x18c0, 0xc98c, 0x18ff, 0xc98c, 0x21, 0 - .dw 0x1940, 0xc98c, 0x197f, 0xc98c, 0x21, 0 - .dw 0x19c0, 0xc98c, 0x1fff, 0xc98c, 0x21, 0 - .dw 0x2040, 0xc98c, 0x207f, 0xc98c, 0x21, 0 - .dw 0x20c0, 0xc98c, 0x20ff, 0xc98c, 0x21, 0 - .dw 0x2140, 0xc98c, 0x217f, 0xc98c, 0x21, 0 - .dw 0x21c0, 0xc98c, 0x21ff, 0xc98c, 0x21, 0 - .dw 0x2240, 0xc98c, 0x227f, 0xc98c, 0x21, 0 - .dw 0x22c0, 0xc98c, 0x22ff, 0xc98c, 0x21, 0 - .dw 0x2340, 0xc98c, 0x237f, 0xc98c, 0x21, 0 - .dw 0x23c0, 0xc98c, 0x23ff, 0xc98c, 0x21, 0 - .dw 0x2440, 0xc98c, 0x247f, 0xc98c, 0x21, 0 - .dw 0x24c0, 0xc98c, 0x24ff, 0xc98c, 0x21, 0 - .dw 0x2540, 0xc98c, 0x257f, 0xc98c, 0x21, 0 - .dw 0x25c0, 0xc98c, 0x25ff, 0xc98c, 0x21, 0 - .dw 0x2640, 0xc98c, 0x267f, 0xc98c, 0x21, 0 - .dw 0x26c0, 0xc98c, 0x26ff, 0xc98c, 0x21, 0 - .dw 0x2740, 0xc98c, 0x277f, 0xc98c, 0x21, 0 - .dw 0x27c0, 0xc98c, 0x27ff, 0xc98c, 0x21, 0 - .dw 0x2840, 0xc98c, 0x287f, 0xc98c, 0x21, 0 - .dw 0x28c0, 0xc98c, 0x28ff, 0xc98c, 0x21, 0 - .dw 0x2940, 0xc98c, 0x297f, 0xc98c, 0x21, 0 - .dw 0x29c0, 0xc98c, 0x29ff, 0xc98c, 0x21, 0 - .dw 0x2a40, 0xc98c, 0x2a7f, 0xc98c, 0x21, 0 - .dw 0x2ac0, 0xc98c, 0x2aff, 0xc98c, 0x21, 0 - .dw 0x2b40, 0xc98c, 0x2b7f, 0xc98c, 0x21, 0 - .dw 0x2bc0, 0xc98c, 0x2bff, 0xc98c, 0x21, 0 - .dw 0x2c40, 0xc98c, 0x2c7f, 0xc98c, 0x21, 0 - .dw 0x2cc0, 0xc98c, 0x2cff, 0xc98c, 0x21, 0 - .dw 0x2d40, 0xc98c, 0x2d7f, 0xc98c, 0x21, 0 - .dw 0x2dc0, 0xc98c, 0x2dff, 0xc98c, 0x21, 0 - .dw 0x2e40, 0xc98c, 0x2e7f, 0xc98c, 0x21, 0 - .dw 0x2ec0, 0xc98c, 0x2eff, 0xc98c, 0x21, 0 - .dw 0x2f40, 0xc98c, 0x2f7f, 0xc98c, 0x21, 0 - .dw 0x2fc0, 0xc98c, 0x2fff, 0xc98c, 0x21, 0 - .dw 0x3040, 0xc98c, 0x307f, 0xc98c, 0x21, 0 - .dw 0x30c0, 0xc98c, 0x30ff, 0xc98c, 0x21, 0 - .dw 0x3140, 0xc98c, 0x317f, 0xc98c, 0x21, 0 - .dw 0x31c0, 0xc98c, 0x31ff, 0xc98c, 0x21, 0 - .dw 0x3240, 0xc98c, 0x327f, 0xc98c, 0x21, 0 - .dw 0x32c0, 0xc98c, 0x32ff, 0xc98c, 0x21, 0 - .dw 0x3340, 0xc98c, 0x337f, 0xc98c, 0x21, 0 - .dw 0x33c0, 0xc98c, 0x33ff, 0xc98c, 0x21, 0 - .dw 0x3440, 0xc98c, 0x347f, 0xc98c, 0x21, 0 - .dw 0x34c0, 0xc98c, 0x34ff, 0xc98c, 0x21, 0 - .dw 0x3540, 0xc98c, 0x357f, 0xc98c, 0x21, 0 - .dw 0x35c0, 0xc98c, 0x35ff, 0xc98c, 0x21, 0 - .dw 0x3640, 0xc98c, 0x367f, 0xc98c, 0x21, 0 - .dw 0x36c0, 0xc98c, 0x36ff, 0xc98c, 0x21, 0 - .dw 0x3740, 0xc98c, 0x377f, 0xc98c, 0x21, 0 - .dw 0x37c0, 0xc98c, 0x37ff, 0xc98c, 0x21, 0 - .dw 0x3840, 0xc98c, 0x387f, 0xc98c, 0x21, 0 - .dw 0x38c0, 0xc98c, 0x38ff, 0xc98c, 0x21, 0 - .dw 0x3940, 0xc98c, 0x397f, 0xc98c, 0x21, 0 - .dw 0x39c0, 0xc98c, 0x3fff, 0xc98c, 0x21, 0 - .dw 0x4040, 0xc98c, 0x407f, 0xc98c, 0x21, 0 - .dw 0x40c0, 0xc98c, 0x40ff, 0xc98c, 0x21, 0 - .dw 0x4140, 0xc98c, 0x417f, 0xc98c, 0x21, 0 - .dw 0x41c0, 0xc98c, 0x41ff, 0xc98c, 0x21, 0 - .dw 0x4240, 0xc98c, 0x427f, 0xc98c, 0x21, 0 - .dw 0x42c0, 0xc98c, 0x42ff, 0xc98c, 0x21, 0 - .dw 0x4340, 0xc98c, 0x437f, 0xc98c, 0x21, 0 - .dw 0x43c0, 0xc98c, 0x43ff, 0xc98c, 0x21, 0 - .dw 0x4440, 0xc98c, 0x447f, 0xc98c, 0x21, 0 - .dw 0x44c0, 0xc98c, 0x44ff, 0xc98c, 0x21, 0 - .dw 0x4540, 0xc98c, 0x457f, 0xc98c, 0x21, 0 - .dw 0x45c0, 0xc98c, 0x45ff, 0xc98c, 0x21, 0 - .dw 0x4640, 0xc98c, 0x467f, 0xc98c, 0x21, 0 - .dw 0x46c0, 0xc98c, 0x46ff, 0xc98c, 0x21, 0 - .dw 0x4740, 0xc98c, 0x477f, 0xc98c, 0x21, 0 - .dw 0x47c0, 0xc98c, 0x47ff, 0xc98c, 0x21, 0 - .dw 0x4840, 0xc98c, 0x487f, 0xc98c, 0x21, 0 - .dw 0x48c0, 0xc98c, 0x48ff, 0xc98c, 0x21, 0 - .dw 0x4940, 0xc98c, 0x497f, 0xc98c, 0x21, 0 - .dw 0x49c0, 0xc98c, 0x49ff, 0xc98c, 0x21, 0 - .dw 0x4a40, 0xc98c, 0x4a7f, 0xc98c, 0x21, 0 - .dw 0x4ac0, 0xc98c, 0x4aff, 0xc98c, 0x21, 0 - .dw 0x4b40, 0xc98c, 0x4b7f, 0xc98c, 0x21, 0 - .dw 0x4bc0, 0xc98c, 0x4bff, 0xc98c, 0x21, 0 - .dw 0x4c40, 0xc98c, 0x4c7f, 0xc98c, 0x21, 0 - .dw 0x4cc0, 0xc98c, 0x4cff, 0xc98c, 0x21, 0 - .dw 0x4d40, 0xc98c, 0x4d7f, 0xc98c, 0x21, 0 - .dw 0x4dc0, 0xc98c, 0x4dff, 0xc98c, 0x21, 0 - .dw 0x4e40, 0xc98c, 0x4e7f, 0xc98c, 0x21, 0 - .dw 0x4ec0, 0xc98c, 0x4eff, 0xc98c, 0x21, 0 - .dw 0x4f40, 0xc98c, 0x4f7f, 0xc98c, 0x21, 0 - .dw 0x4fc0, 0xc98c, 0x4fff, 0xc98c, 0x21, 0 - .dw 0x5040, 0xc98c, 0x507f, 0xc98c, 0x21, 0 - .dw 0x50c0, 0xc98c, 0x50ff, 0xc98c, 0x21, 0 - .dw 0x5140, 0xc98c, 0x517f, 0xc98c, 0x21, 0 - .dw 0x51c0, 0xc98c, 0x51ff, 0xc98c, 0x21, 0 - .dw 0x5240, 0xc98c, 0x527f, 0xc98c, 0x21, 0 - .dw 0x52c0, 0xc98c, 0x52ff, 0xc98c, 0x21, 0 - .dw 0x5340, 0xc98c, 0x537f, 0xc98c, 0x21, 0 - .dw 0x53c0, 0xc98c, 0x53ff, 0xc98c, 0x21, 0 - .dw 0x5440, 0xc98c, 0x547f, 0xc98c, 0x21, 0 - .dw 0x54c0, 0xc98c, 0x54ff, 0xc98c, 0x21, 0 - .dw 0x5540, 0xc98c, 0x557f, 0xc98c, 0x21, 0 - .dw 0x55c0, 0xc98c, 0x55ff, 0xc98c, 0x21, 0 - .dw 0x5640, 0xc98c, 0x567f, 0xc98c, 0x21, 0 - .dw 0x56c0, 0xc98c, 0x56ff, 0xc98c, 0x21, 0 - .dw 0x5740, 0xc98c, 0x577f, 0xc98c, 0x21, 0 - .dw 0x57c0, 0xc98c, 0x57ff, 0xc98c, 0x21, 0 - .dw 0x5840, 0xc98c, 0x587f, 0xc98c, 0x21, 0 - .dw 0x58c0, 0xc98c, 0x58ff, 0xc98c, 0x21, 0 - .dw 0x5940, 0xc98c, 0x597f, 0xc98c, 0x21, 0 - .dw 0x59c0, 0xc98c, 0x5fff, 0xc98c, 0x21, 0 - .dw 0x6040, 0xc98c, 0x607f, 0xc98c, 0x21, 0 - .dw 0x60c0, 0xc98c, 0x60ff, 0xc98c, 0x21, 0 - .dw 0x6140, 0xc98c, 0x617f, 0xc98c, 0x21, 0 - .dw 0x61c0, 0xc98c, 0x61ff, 0xc98c, 0x21, 0 - .dw 0x6240, 0xc98c, 0x627f, 0xc98c, 0x21, 0 - .dw 0x62c0, 0xc98c, 0x62ff, 0xc98c, 0x21, 0 - .dw 0x6340, 0xc98c, 0x637f, 0xc98c, 0x21, 0 - .dw 0x63c0, 0xc98c, 0x63ff, 0xc98c, 0x21, 0 - .dw 0x6440, 0xc98c, 0x647f, 0xc98c, 0x21, 0 - .dw 0x64c0, 0xc98c, 0x64ff, 0xc98c, 0x21, 0 - .dw 0x6540, 0xc98c, 0x657f, 0xc98c, 0x21, 0 - .dw 0x65c0, 0xc98c, 0x65ff, 0xc98c, 0x21, 0 - .dw 0x6640, 0xc98c, 0x667f, 0xc98c, 0x21, 0 - .dw 0x66c0, 0xc98c, 0x66ff, 0xc98c, 0x21, 0 - .dw 0x6740, 0xc98c, 0x677f, 0xc98c, 0x21, 0 - .dw 0x67c0, 0xc98c, 0x67ff, 0xc98c, 0x21, 0 - .dw 0x6840, 0xc98c, 0x687f, 0xc98c, 0x21, 0 - .dw 0x68c0, 0xc98c, 0x68ff, 0xc98c, 0x21, 0 - .dw 0x6940, 0xc98c, 0x697f, 0xc98c, 0x21, 0 - .dw 0x69c0, 0xc98c, 0x69ff, 0xc98c, 0x21, 0 - .dw 0x6a40, 0xc98c, 0x6a7f, 0xc98c, 0x21, 0 - .dw 0x6ac0, 0xc98c, 0x6aff, 0xc98c, 0x21, 0 - .dw 0x6b40, 0xc98c, 0x6b7f, 0xc98c, 0x21, 0 - .dw 0x6bc0, 0xc98c, 0x6bff, 0xc98c, 0x21, 0 - .dw 0x6c40, 0xc98c, 0x6c7f, 0xc98c, 0x21, 0 - .dw 0x6cc0, 0xc98c, 0x6cff, 0xc98c, 0x21, 0 - .dw 0x6d40, 0xc98c, 0x6d7f, 0xc98c, 0x21, 0 - .dw 0x6dc0, 0xc98c, 0x6dff, 0xc98c, 0x21, 0 - .dw 0x6e40, 0xc98c, 0x6e7f, 0xc98c, 0x21, 0 - .dw 0x6ec0, 0xc98c, 0x6eff, 0xc98c, 0x21, 0 - .dw 0x6f40, 0xc98c, 0x6f7f, 0xc98c, 0x21, 0 - .dw 0x6fc0, 0xc98c, 0x6fff, 0xc98c, 0x21, 0 - .dw 0x7040, 0xc98c, 0x707f, 0xc98c, 0x21, 0 - .dw 0x70c0, 0xc98c, 0x70ff, 0xc98c, 0x21, 0 - .dw 0x7140, 0xc98c, 0x717f, 0xc98c, 0x21, 0 - .dw 0x71c0, 0xc98c, 0x71ff, 0xc98c, 0x21, 0 - .dw 0x7240, 0xc98c, 0x727f, 0xc98c, 0x21, 0 - .dw 0x72c0, 0xc98c, 0x72ff, 0xc98c, 0x21, 0 - .dw 0x7340, 0xc98c, 0x737f, 0xc98c, 0x21, 0 - .dw 0x73c0, 0xc98c, 0x73ff, 0xc98c, 0x21, 0 - .dw 0x7440, 0xc98c, 0x747f, 0xc98c, 0x21, 0 - .dw 0x74c0, 0xc98c, 0x74ff, 0xc98c, 0x21, 0 - .dw 0x7540, 0xc98c, 0x757f, 0xc98c, 0x21, 0 - .dw 0x75c0, 0xc98c, 0x75ff, 0xc98c, 0x21, 0 - .dw 0x7640, 0xc98c, 0x767f, 0xc98c, 0x21, 0 - .dw 0x76c0, 0xc98c, 0x76ff, 0xc98c, 0x21, 0 - .dw 0x7740, 0xc98c, 0x777f, 0xc98c, 0x21, 0 - .dw 0x77c0, 0xc98c, 0x77ff, 0xc98c, 0x21, 0 - .dw 0x7840, 0xc98c, 0x787f, 0xc98c, 0x21, 0 - .dw 0x78c0, 0xc98c, 0x78ff, 0xc98c, 0x21, 0 - .dw 0x7940, 0xc98c, 0x797f, 0xc98c, 0x21, 0 - .dw 0x79c0, 0xc98c, 0x7fff, 0xc98c, 0x21, 0 - .dw 0x8040, 0xc98c, 0x807f, 0xc98c, 0x21, 0 - .dw 0x80c0, 0xc98c, 0x80ff, 0xc98c, 0x21, 0 - .dw 0x8140, 0xc98c, 0x817f, 0xc98c, 0x21, 0 - .dw 0x81c0, 0xc98c, 0x81ff, 0xc98c, 0x21, 0 - .dw 0x8240, 0xc98c, 0x827f, 0xc98c, 0x21, 0 - .dw 0x82c0, 0xc98c, 0x82ff, 0xc98c, 0x21, 0 - .dw 0x8340, 0xc98c, 0x837f, 0xc98c, 0x21, 0 - .dw 0x83c0, 0xc98c, 0x83ff, 0xc98c, 0x21, 0 - .dw 0x8440, 0xc98c, 0x847f, 0xc98c, 0x21, 0 - .dw 0x84c0, 0xc98c, 0x84ff, 0xc98c, 0x21, 0 - .dw 0x8540, 0xc98c, 0x857f, 0xc98c, 0x21, 0 - .dw 0x85c0, 0xc98c, 0x85ff, 0xc98c, 0x21, 0 - .dw 0x8640, 0xc98c, 0x867f, 0xc98c, 0x21, 0 - .dw 0x86c0, 0xc98c, 0x86ff, 0xc98c, 0x21, 0 - .dw 0x8740, 0xc98c, 0x877f, 0xc98c, 0x21, 0 - .dw 0x87c0, 0xc98c, 0x87ff, 0xc98c, 0x21, 0 - .dw 0x8840, 0xc98c, 0x887f, 0xc98c, 0x21, 0 - .dw 0x88c0, 0xc98c, 0x88ff, 0xc98c, 0x21, 0 - .dw 0x8940, 0xc98c, 0x897f, 0xc98c, 0x21, 0 - .dw 0x89c0, 0xc98c, 0x89ff, 0xc98c, 0x21, 0 - .dw 0x8a40, 0xc98c, 0x8a7f, 0xc98c, 0x21, 0 - .dw 0x8ac0, 0xc98c, 0x8aff, 0xc98c, 0x21, 0 - .dw 0x8b40, 0xc98c, 0x8b7f, 0xc98c, 0x21, 0 - .dw 0x8bc0, 0xc98c, 0x8bff, 0xc98c, 0x21, 0 - .dw 0x8c40, 0xc98c, 0x8c7f, 0xc98c, 0x21, 0 - .dw 0x8cc0, 0xc98c, 0x8cff, 0xc98c, 0x21, 0 - .dw 0x8d40, 0xc98c, 0x8d7f, 0xc98c, 0x21, 0 - .dw 0x8dc0, 0xc98c, 0x8dff, 0xc98c, 0x21, 0 - .dw 0x8e40, 0xc98c, 0x8e7f, 0xc98c, 0x21, 0 - .dw 0x8ec0, 0xc98c, 0x8eff, 0xc98c, 0x21, 0 - .dw 0x8f40, 0xc98c, 0x8f7f, 0xc98c, 0x21, 0 - .dw 0x8fc0, 0xc98c, 0x8fff, 0xc98c, 0x21, 0 - .dw 0x9040, 0xc98c, 0x907f, 0xc98c, 0x21, 0 - .dw 0x90c0, 0xc98c, 0x90ff, 0xc98c, 0x21, 0 - .dw 0x9140, 0xc98c, 0x917f, 0xc98c, 0x21, 0 - .dw 0x91c0, 0xc98c, 0x91ff, 0xc98c, 0x21, 0 - .dw 0x9240, 0xc98c, 0x927f, 0xc98c, 0x21, 0 - .dw 0x92c0, 0xc98c, 0x92ff, 0xc98c, 0x21, 0 - .dw 0x9340, 0xc98c, 0x937f, 0xc98c, 0x21, 0 - .dw 0x93c0, 0xc98c, 0x93ff, 0xc98c, 0x21, 0 - .dw 0x9440, 0xc98c, 0x947f, 0xc98c, 0x21, 0 - .dw 0x94c0, 0xc98c, 0x94ff, 0xc98c, 0x21, 0 - .dw 0x9540, 0xc98c, 0x957f, 0xc98c, 0x21, 0 - .dw 0x95c0, 0xc98c, 0x95ff, 0xc98c, 0x21, 0 - .dw 0x9640, 0xc98c, 0x967f, 0xc98c, 0x21, 0 - .dw 0x96c0, 0xc98c, 0x96ff, 0xc98c, 0x21, 0 - .dw 0x9740, 0xc98c, 0x977f, 0xc98c, 0x21, 0 - .dw 0x97c0, 0xc98c, 0x97ff, 0xc98c, 0x21, 0 - .dw 0x9840, 0xc98c, 0x987f, 0xc98c, 0x21, 0 - .dw 0x98c0, 0xc98c, 0x98ff, 0xc98c, 0x21, 0 - .dw 0x9940, 0xc98c, 0x997f, 0xc98c, 0x21, 0 - .dw 0x99c0, 0xc98c, 0x9fff, 0xc98c, 0x21, 0 - .dw 0xa040, 0xc98c, 0xa07f, 0xc98c, 0x21, 0 - .dw 0xa0c0, 0xc98c, 0xa0ff, 0xc98c, 0x21, 0 - .dw 0xa140, 0xc98c, 0xa17f, 0xc98c, 0x21, 0 - .dw 0xa1c0, 0xc98c, 0xa1ff, 0xc98c, 0x21, 0 - .dw 0xa240, 0xc98c, 0xa27f, 0xc98c, 0x21, 0 - .dw 0xa2c0, 0xc98c, 0xa2ff, 0xc98c, 0x21, 0 - .dw 0xa340, 0xc98c, 0xa37f, 0xc98c, 0x21, 0 - .dw 0xa3c0, 0xc98c, 0xa3ff, 0xc98c, 0x21, 0 - .dw 0xa440, 0xc98c, 0xa47f, 0xc98c, 0x21, 0 - .dw 0xa4c0, 0xc98c, 0xa4ff, 0xc98c, 0x21, 0 - .dw 0xa540, 0xc98c, 0xa57f, 0xc98c, 0x21, 0 - .dw 0xa5c0, 0xc98c, 0xa5ff, 0xc98c, 0x21, 0 - .dw 0xa640, 0xc98c, 0xa67f, 0xc98c, 0x21, 0 - .dw 0xa6c0, 0xc98c, 0xa6ff, 0xc98c, 0x21, 0 - .dw 0xa740, 0xc98c, 0xa77f, 0xc98c, 0x21, 0 - .dw 0xa7c0, 0xc98c, 0xa7ff, 0xc98c, 0x21, 0 - .dw 0xa840, 0xc98c, 0xa87f, 0xc98c, 0x21, 0 - .dw 0xa8c0, 0xc98c, 0xa8ff, 0xc98c, 0x21, 0 - .dw 0xa940, 0xc98c, 0xa97f, 0xc98c, 0x21, 0 - .dw 0xa9c0, 0xc98c, 0xa9ff, 0xc98c, 0x21, 0 - .dw 0xaa40, 0xc98c, 0xaa7f, 0xc98c, 0x21, 0 - .dw 0xaac0, 0xc98c, 0xaaff, 0xc98c, 0x21, 0 - .dw 0xab40, 0xc98c, 0xab7f, 0xc98c, 0x21, 0 - .dw 0xabc0, 0xc98c, 0xabff, 0xc98c, 0x21, 0 - .dw 0xac40, 0xc98c, 0xac7f, 0xc98c, 0x21, 0 - .dw 0xacc0, 0xc98c, 0xacff, 0xc98c, 0x21, 0 - .dw 0xad40, 0xc98c, 0xad7f, 0xc98c, 0x21, 0 - .dw 0xadc0, 0xc98c, 0xadff, 0xc98c, 0x21, 0 - .dw 0xae40, 0xc98c, 0xae7f, 0xc98c, 0x21, 0 - .dw 0xaec0, 0xc98c, 0xaeff, 0xc98c, 0x21, 0 - .dw 0xaf40, 0xc98c, 0xaf7f, 0xc98c, 0x21, 0 - .dw 0xafc0, 0xc98c, 0xafff, 0xc98c, 0x21, 0 - .dw 0xb040, 0xc98c, 0xb07f, 0xc98c, 0x21, 0 - .dw 0xb0c0, 0xc98c, 0xb0ff, 0xc98c, 0x21, 0 - .dw 0xb140, 0xc98c, 0xb17f, 0xc98c, 0x21, 0 - .dw 0xb1c0, 0xc98c, 0xb1ff, 0xc98c, 0x21, 0 - .dw 0xb240, 0xc98c, 0xb27f, 0xc98c, 0x21, 0 - .dw 0xb2c0, 0xc98c, 0xb2ff, 0xc98c, 0x21, 0 - .dw 0xb340, 0xc98c, 0xb37f, 0xc98c, 0x21, 0 - .dw 0xb3c0, 0xc98c, 0xb3ff, 0xc98c, 0x21, 0 - .dw 0xb440, 0xc98c, 0xb47f, 0xc98c, 0x21, 0 - .dw 0xb4c0, 0xc98c, 0xb4ff, 0xc98c, 0x21, 0 - .dw 0xb540, 0xc98c, 0xb57f, 0xc98c, 0x21, 0 - .dw 0xb5c0, 0xc98c, 0xb5ff, 0xc98c, 0x21, 0 - .dw 0xb640, 0xc98c, 0xb67f, 0xc98c, 0x21, 0 - .dw 0xb6c0, 0xc98c, 0xb6ff, 0xc98c, 0x21, 0 - .dw 0xb740, 0xc98c, 0xb77f, 0xc98c, 0x21, 0 - .dw 0xb7c0, 0xc98c, 0xb7ff, 0xc98c, 0x21, 0 - .dw 0xb840, 0xc98c, 0xb87f, 0xc98c, 0x21, 0 - .dw 0xb8c0, 0xc98c, 0xb8ff, 0xc98c, 0x21, 0 - .dw 0xb940, 0xc98c, 0xb97f, 0xc98c, 0x21, 0 - .dw 0xb9c0, 0xc98c, 0xbfff, 0xc98c, 0x21, 0 - .dw 0xc040, 0xc98c, 0xc07f, 0xc98c, 0x21, 0 - .dw 0xc0c0, 0xc98c, 0xc0ff, 0xc98c, 0x21, 0 - .dw 0xc140, 0xc98c, 0xc17f, 0xc98c, 0x21, 0 - .dw 0xc1c0, 0xc98c, 0xc1ff, 0xc98c, 0x21, 0 - .dw 0xc240, 0xc98c, 0xc27f, 0xc98c, 0x21, 0 - .dw 0xc2c0, 0xc98c, 0xc2ff, 0xc98c, 0x21, 0 - .dw 0xc340, 0xc98c, 0xc37f, 0xc98c, 0x21, 0 - .dw 0xc3c0, 0xc98c, 0xc3ff, 0xc98c, 0x21, 0 - .dw 0xc440, 0xc98c, 0xc47f, 0xc98c, 0x21, 0 - .dw 0xc4c0, 0xc98c, 0xc4ff, 0xc98c, 0x21, 0 - .dw 0xc540, 0xc98c, 0xc57f, 0xc98c, 0x21, 0 - .dw 0xc5c0, 0xc98c, 0xc5ff, 0xc98c, 0x21, 0 - .dw 0xc640, 0xc98c, 0xc67f, 0xc98c, 0x21, 0 - .dw 0xc6c0, 0xc98c, 0xc6ff, 0xc98c, 0x21, 0 - .dw 0xc740, 0xc98c, 0xc77f, 0xc98c, 0x21, 0 - .dw 0xc7c0, 0xc98c, 0xc7ff, 0xc98c, 0x21, 0 - .dw 0xc840, 0xc98c, 0xc87f, 0xc98c, 0x21, 0 - .dw 0xc8c0, 0xc98c, 0xc8ff, 0xc98c, 0x21, 0 - .dw 0xc940, 0xc98c, 0xc97f, 0xc98c, 0x21, 0 - .dw 0xc9c0, 0xc98c, 0xc9ff, 0xc98c, 0x21, 0 - .dw 0xca40, 0xc98c, 0xca7f, 0xc98c, 0x21, 0 - .dw 0xcac0, 0xc98c, 0xcaff, 0xc98c, 0x21, 0 - .dw 0xcb40, 0xc98c, 0xcb7f, 0xc98c, 0x21, 0 - .dw 0xcbc0, 0xc98c, 0xcbff, 0xc98c, 0x21, 0 - .dw 0xcc40, 0xc98c, 0xcc7f, 0xc98c, 0x21, 0 - .dw 0xccc0, 0xc98c, 0xccff, 0xc98c, 0x21, 0 - .dw 0xcd40, 0xc98c, 0xcd7f, 0xc98c, 0x21, 0 - .dw 0xcdc0, 0xc98c, 0xcdff, 0xc98c, 0x21, 0 - .dw 0xce40, 0xc98c, 0xce7f, 0xc98c, 0x21, 0 - .dw 0xcec0, 0xc98c, 0xceff, 0xc98c, 0x21, 0 - .dw 0xcf40, 0xc98c, 0xcf7f, 0xc98c, 0x21, 0 - .dw 0xcfc0, 0xc98c, 0xcfff, 0xc98c, 0x21, 0 - .dw 0xd040, 0xc98c, 0xd07f, 0xc98c, 0x21, 0 - .dw 0xd0c0, 0xc98c, 0xd0ff, 0xc98c, 0x21, 0 - .dw 0xd140, 0xc98c, 0xd17f, 0xc98c, 0x21, 0 - .dw 0xd1c0, 0xc98c, 0xd1ff, 0xc98c, 0x21, 0 - .dw 0xd240, 0xc98c, 0xd27f, 0xc98c, 0x21, 0 - .dw 0xd2c0, 0xc98c, 0xd2ff, 0xc98c, 0x21, 0 - .dw 0xd340, 0xc98c, 0xd37f, 0xc98c, 0x21, 0 - .dw 0xd3c0, 0xc98c, 0xd3ff, 0xc98c, 0x21, 0 - .dw 0xd440, 0xc98c, 0xd47f, 0xc98c, 0x21, 0 - .dw 0xd4c0, 0xc98c, 0xd4ff, 0xc98c, 0x21, 0 - .dw 0xd540, 0xc98c, 0xd57f, 0xc98c, 0x21, 0 - .dw 0xd5c0, 0xc98c, 0xd5ff, 0xc98c, 0x21, 0 - .dw 0xd640, 0xc98c, 0xd67f, 0xc98c, 0x21, 0 - .dw 0xd6c0, 0xc98c, 0xd6ff, 0xc98c, 0x21, 0 - .dw 0xd740, 0xc98c, 0xd77f, 0xc98c, 0x21, 0 - .dw 0xd7c0, 0xc98c, 0xd7ff, 0xc98c, 0x21, 0 - .dw 0xd840, 0xc98c, 0xd87f, 0xc98c, 0x21, 0 - .dw 0xd8c0, 0xc98c, 0xd8ff, 0xc98c, 0x21, 0 - .dw 0xd940, 0xc98c, 0xd97f, 0xc98c, 0x21, 0 - .dw 0xd9c0, 0xc98c, 0xdfff, 0xc98c, 0x21, 0 - .dw 0xe040, 0xc98c, 0xe07f, 0xc98c, 0x21, 0 - .dw 0xe0c0, 0xc98c, 0xe0ff, 0xc98c, 0x21, 0 - .dw 0xe140, 0xc98c, 0xe17f, 0xc98c, 0x21, 0 - .dw 0xe1c0, 0xc98c, 0xe1ff, 0xc98c, 0x21, 0 - .dw 0xe240, 0xc98c, 0xe27f, 0xc98c, 0x21, 0 - .dw 0xe2c0, 0xc98c, 0xe2ff, 0xc98c, 0x21, 0 - .dw 0xe340, 0xc98c, 0xe37f, 0xc98c, 0x21, 0 - .dw 0xe3c0, 0xc98c, 0xe3ff, 0xc98c, 0x21, 0 - .dw 0xe440, 0xc98c, 0xe47f, 0xc98c, 0x21, 0 - .dw 0xe4c0, 0xc98c, 0xe4ff, 0xc98c, 0x21, 0 - .dw 0xe540, 0xc98c, 0xe57f, 0xc98c, 0x21, 0 - .dw 0xe5c0, 0xc98c, 0xe5ff, 0xc98c, 0x21, 0 - .dw 0xe640, 0xc98c, 0xe67f, 0xc98c, 0x21, 0 - .dw 0xe6c0, 0xc98c, 0xe6ff, 0xc98c, 0x21, 0 - .dw 0xe740, 0xc98c, 0xe77f, 0xc98c, 0x21, 0 - .dw 0xe7c0, 0xc98c, 0xe7ff, 0xc98c, 0x21, 0 - .dw 0xe840, 0xc98c, 0xe87f, 0xc98c, 0x21, 0 - .dw 0xe8c0, 0xc98c, 0xe8ff, 0xc98c, 0x21, 0 - .dw 0xe940, 0xc98c, 0xe97f, 0xc98c, 0x21, 0 - .dw 0xe9c0, 0xc98c, 0xe9ff, 0xc98c, 0x21, 0 - .dw 0xea40, 0xc98c, 0xea7f, 0xc98c, 0x21, 0 - .dw 0xeac0, 0xc98c, 0xeaff, 0xc98c, 0x21, 0 - .dw 0xeb40, 0xc98c, 0xeb7f, 0xc98c, 0x21, 0 - .dw 0xebc0, 0xc98c, 0xebff, 0xc98c, 0x21, 0 - .dw 0xec40, 0xc98c, 0xec7f, 0xc98c, 0x21, 0 - .dw 0xecc0, 0xc98c, 0xecff, 0xc98c, 0x21, 0 - .dw 0xed40, 0xc98c, 0xed7f, 0xc98c, 0x21, 0 - .dw 0xedc0, 0xc98c, 0xedff, 0xc98c, 0x21, 0 - .dw 0xee40, 0xc98c, 0xee7f, 0xc98c, 0x21, 0 - .dw 0xeec0, 0xc98c, 0xeeff, 0xc98c, 0x21, 0 - .dw 0xef40, 0xc98c, 0xef7f, 0xc98c, 0x21, 0 - .dw 0xefc0, 0xc98c, 0xefff, 0xc98c, 0x21, 0 - .dw 0xf040, 0xc98c, 0xf07f, 0xc98c, 0x21, 0 - .dw 0xf0c0, 0xc98c, 0xf0ff, 0xc98c, 0x21, 0 - .dw 0xf140, 0xc98c, 0xf17f, 0xc98c, 0x21, 0 - .dw 0xf1c0, 0xc98c, 0xf1ff, 0xc98c, 0x21, 0 - .dw 0xf240, 0xc98c, 0xf27f, 0xc98c, 0x21, 0 - .dw 0xf2c0, 0xc98c, 0xf2ff, 0xc98c, 0x21, 0 - .dw 0xf340, 0xc98c, 0xf37f, 0xc98c, 0x21, 0 - .dw 0xf3c0, 0xc98c, 0xf3ff, 0xc98c, 0x21, 0 - .dw 0xf440, 0xc98c, 0xf47f, 0xc98c, 0x21, 0 - .dw 0xf4c0, 0xc98c, 0xf4ff, 0xc98c, 0x21, 0 - .dw 0xf540, 0xc98c, 0xf57f, 0xc98c, 0x21, 0 - .dw 0xf5c0, 0xc98c, 0xf5ff, 0xc98c, 0x21, 0 - .dw 0xf640, 0xc98c, 0xf67f, 0xc98c, 0x21, 0 - .dw 0xf6c0, 0xc98c, 0xf6ff, 0xc98c, 0x21, 0 - .dw 0xf740, 0xc98c, 0xf77f, 0xc98c, 0x21, 0 - .dw 0xf7c0, 0xc98c, 0xf7ff, 0xc98c, 0x21, 0 - .dw 0xf840, 0xc98c, 0xf87f, 0xc98c, 0x21, 0 - .dw 0xf8c0, 0xc98c, 0xf8ff, 0xc98c, 0x21, 0 - .dw 0xf940, 0xc98c, 0xf97f, 0xc98c, 0x21, 0 - .dw 0xf9c0, 0xc98c, 0xffff, 0xc98c, 0x21, 0 - .dw 0x0040, 0xc98d, 0x007f, 0xc98d, 0x21, 0 - .dw 0x00c0, 0xc98d, 0x00ff, 0xc98d, 0x21, 0 - .dw 0x0140, 0xc98d, 0x017f, 0xc98d, 0x21, 0 - .dw 0x01c0, 0xc98d, 0x01ff, 0xc98d, 0x21, 0 - .dw 0x0240, 0xc98d, 0x027f, 0xc98d, 0x21, 0 - .dw 0x02c0, 0xc98d, 0x02ff, 0xc98d, 0x21, 0 - .dw 0x0340, 0xc98d, 0x037f, 0xc98d, 0x21, 0 - .dw 0x03c0, 0xc98d, 0x03ff, 0xc98d, 0x21, 0 - .dw 0x0440, 0xc98d, 0x047f, 0xc98d, 0x21, 0 - .dw 0x04c0, 0xc98d, 0x04ff, 0xc98d, 0x21, 0 - .dw 0x0540, 0xc98d, 0x057f, 0xc98d, 0x21, 0 - .dw 0x05c0, 0xc98d, 0x05ff, 0xc98d, 0x21, 0 - .dw 0x0640, 0xc98d, 0x067f, 0xc98d, 0x21, 0 - .dw 0x06c0, 0xc98d, 0x06ff, 0xc98d, 0x21, 0 - .dw 0x0740, 0xc98d, 0x077f, 0xc98d, 0x21, 0 - .dw 0x07c0, 0xc98d, 0x07ff, 0xc98d, 0x21, 0 - .dw 0x0840, 0xc98d, 0x087f, 0xc98d, 0x21, 0 - .dw 0x08c0, 0xc98d, 0x08ff, 0xc98d, 0x21, 0 - .dw 0x0940, 0xc98d, 0x097f, 0xc98d, 0x21, 0 - .dw 0x09c0, 0xc98d, 0x09ff, 0xc98d, 0x21, 0 - .dw 0x0a40, 0xc98d, 0x0a7f, 0xc98d, 0x21, 0 - .dw 0x0ac0, 0xc98d, 0x0aff, 0xc98d, 0x21, 0 - .dw 0x0b40, 0xc98d, 0x0b7f, 0xc98d, 0x21, 0 - .dw 0x0bc0, 0xc98d, 0x0bff, 0xc98d, 0x21, 0 - .dw 0x0c40, 0xc98d, 0x0c7f, 0xc98d, 0x21, 0 - .dw 0x0cc0, 0xc98d, 0x0cff, 0xc98d, 0x21, 0 - .dw 0x0d40, 0xc98d, 0x0d7f, 0xc98d, 0x21, 0 - .dw 0x0dc0, 0xc98d, 0x0dff, 0xc98d, 0x21, 0 - .dw 0x0e40, 0xc98d, 0x0e7f, 0xc98d, 0x21, 0 - .dw 0x0ec0, 0xc98d, 0x0eff, 0xc98d, 0x21, 0 - .dw 0x0f40, 0xc98d, 0x0f7f, 0xc98d, 0x21, 0 - .dw 0x0fc0, 0xc98d, 0x0fff, 0xc98d, 0x21, 0 - .dw 0x1040, 0xc98d, 0x107f, 0xc98d, 0x21, 0 - .dw 0x10c0, 0xc98d, 0x10ff, 0xc98d, 0x21, 0 - .dw 0x1140, 0xc98d, 0x117f, 0xc98d, 0x21, 0 - .dw 0x11c0, 0xc98d, 0x11ff, 0xc98d, 0x21, 0 - .dw 0x1240, 0xc98d, 0x127f, 0xc98d, 0x21, 0 - .dw 0x12c0, 0xc98d, 0x12ff, 0xc98d, 0x21, 0 - .dw 0x1340, 0xc98d, 0x137f, 0xc98d, 0x21, 0 - .dw 0x13c0, 0xc98d, 0x13ff, 0xc98d, 0x21, 0 - .dw 0x1440, 0xc98d, 0x147f, 0xc98d, 0x21, 0 - .dw 0x14c0, 0xc98d, 0x14ff, 0xc98d, 0x21, 0 - .dw 0x1540, 0xc98d, 0x157f, 0xc98d, 0x21, 0 - .dw 0x15c0, 0xc98d, 0x15ff, 0xc98d, 0x21, 0 - .dw 0x1640, 0xc98d, 0x167f, 0xc98d, 0x21, 0 - .dw 0x16c0, 0xc98d, 0x16ff, 0xc98d, 0x21, 0 - .dw 0x1740, 0xc98d, 0x177f, 0xc98d, 0x21, 0 - .dw 0x17c0, 0xc98d, 0x17ff, 0xc98d, 0x21, 0 - .dw 0x1840, 0xc98d, 0x187f, 0xc98d, 0x21, 0 - .dw 0x18c0, 0xc98d, 0x18ff, 0xc98d, 0x21, 0 - .dw 0x1940, 0xc98d, 0x197f, 0xc98d, 0x21, 0 - .dw 0x19c0, 0xc98d, 0x1fff, 0xc98d, 0x21, 0 - .dw 0x2040, 0xc98d, 0x207f, 0xc98d, 0x21, 0 - .dw 0x20c0, 0xc98d, 0x20ff, 0xc98d, 0x21, 0 - .dw 0x2140, 0xc98d, 0x217f, 0xc98d, 0x21, 0 - .dw 0x21c0, 0xc98d, 0x21ff, 0xc98d, 0x21, 0 - .dw 0x2240, 0xc98d, 0x227f, 0xc98d, 0x21, 0 - .dw 0x22c0, 0xc98d, 0x22ff, 0xc98d, 0x21, 0 - .dw 0x2340, 0xc98d, 0x237f, 0xc98d, 0x21, 0 - .dw 0x23c0, 0xc98d, 0x23ff, 0xc98d, 0x21, 0 - .dw 0x2440, 0xc98d, 0x247f, 0xc98d, 0x21, 0 - .dw 0x24c0, 0xc98d, 0x24ff, 0xc98d, 0x21, 0 - .dw 0x2540, 0xc98d, 0x257f, 0xc98d, 0x21, 0 - .dw 0x25c0, 0xc98d, 0x25ff, 0xc98d, 0x21, 0 - .dw 0x2640, 0xc98d, 0x267f, 0xc98d, 0x21, 0 - .dw 0x26c0, 0xc98d, 0x26ff, 0xc98d, 0x21, 0 - .dw 0x2740, 0xc98d, 0x277f, 0xc98d, 0x21, 0 - .dw 0x27c0, 0xc98d, 0x27ff, 0xc98d, 0x21, 0 - .dw 0x2840, 0xc98d, 0x287f, 0xc98d, 0x21, 0 - .dw 0x28c0, 0xc98d, 0x28ff, 0xc98d, 0x21, 0 - .dw 0x2940, 0xc98d, 0x297f, 0xc98d, 0x21, 0 - .dw 0x29c0, 0xc98d, 0x29ff, 0xc98d, 0x21, 0 - .dw 0x2a40, 0xc98d, 0x2a7f, 0xc98d, 0x21, 0 - .dw 0x2ac0, 0xc98d, 0x2aff, 0xc98d, 0x21, 0 - .dw 0x2b40, 0xc98d, 0x2b7f, 0xc98d, 0x21, 0 - .dw 0x2bc0, 0xc98d, 0x2bff, 0xc98d, 0x21, 0 - .dw 0x2c40, 0xc98d, 0x2c7f, 0xc98d, 0x21, 0 - .dw 0x2cc0, 0xc98d, 0x2cff, 0xc98d, 0x21, 0 - .dw 0x2d40, 0xc98d, 0x2d7f, 0xc98d, 0x21, 0 - .dw 0x2dc0, 0xc98d, 0x2dff, 0xc98d, 0x21, 0 - .dw 0x2e40, 0xc98d, 0x2e7f, 0xc98d, 0x21, 0 - .dw 0x2ec0, 0xc98d, 0x2eff, 0xc98d, 0x21, 0 - .dw 0x2f40, 0xc98d, 0x2f7f, 0xc98d, 0x21, 0 - .dw 0x2fc0, 0xc98d, 0x2fff, 0xc98d, 0x21, 0 - .dw 0x3040, 0xc98d, 0x307f, 0xc98d, 0x21, 0 - .dw 0x30c0, 0xc98d, 0x30ff, 0xc98d, 0x21, 0 - .dw 0x3140, 0xc98d, 0x317f, 0xc98d, 0x21, 0 - .dw 0x31c0, 0xc98d, 0x31ff, 0xc98d, 0x21, 0 - .dw 0x3240, 0xc98d, 0x327f, 0xc98d, 0x21, 0 - .dw 0x32c0, 0xc98d, 0x32ff, 0xc98d, 0x21, 0 - .dw 0x3340, 0xc98d, 0x337f, 0xc98d, 0x21, 0 - .dw 0x33c0, 0xc98d, 0x33ff, 0xc98d, 0x21, 0 - .dw 0x3440, 0xc98d, 0x347f, 0xc98d, 0x21, 0 - .dw 0x34c0, 0xc98d, 0x34ff, 0xc98d, 0x21, 0 - .dw 0x3540, 0xc98d, 0x357f, 0xc98d, 0x21, 0 - .dw 0x35c0, 0xc98d, 0x35ff, 0xc98d, 0x21, 0 - .dw 0x3640, 0xc98d, 0x367f, 0xc98d, 0x21, 0 - .dw 0x36c0, 0xc98d, 0x36ff, 0xc98d, 0x21, 0 - .dw 0x3740, 0xc98d, 0x377f, 0xc98d, 0x21, 0 - .dw 0x37c0, 0xc98d, 0x37ff, 0xc98d, 0x21, 0 - .dw 0x3840, 0xc98d, 0x387f, 0xc98d, 0x21, 0 - .dw 0x38c0, 0xc98d, 0x38ff, 0xc98d, 0x21, 0 - .dw 0x3940, 0xc98d, 0x397f, 0xc98d, 0x21, 0 - .dw 0x39c0, 0xc98d, 0x3fff, 0xc98d, 0x21, 0 - .dw 0x4040, 0xc98d, 0x407f, 0xc98d, 0x21, 0 - .dw 0x40c0, 0xc98d, 0x40ff, 0xc98d, 0x21, 0 - .dw 0x4140, 0xc98d, 0x417f, 0xc98d, 0x21, 0 - .dw 0x41c0, 0xc98d, 0x41ff, 0xc98d, 0x21, 0 - .dw 0x4240, 0xc98d, 0x427f, 0xc98d, 0x21, 0 - .dw 0x42c0, 0xc98d, 0x42ff, 0xc98d, 0x21, 0 - .dw 0x4340, 0xc98d, 0x437f, 0xc98d, 0x21, 0 - .dw 0x43c0, 0xc98d, 0x43ff, 0xc98d, 0x21, 0 - .dw 0x4440, 0xc98d, 0x447f, 0xc98d, 0x21, 0 - .dw 0x44c0, 0xc98d, 0x44ff, 0xc98d, 0x21, 0 - .dw 0x4540, 0xc98d, 0x457f, 0xc98d, 0x21, 0 - .dw 0x45c0, 0xc98d, 0x45ff, 0xc98d, 0x21, 0 - .dw 0x4640, 0xc98d, 0x467f, 0xc98d, 0x21, 0 - .dw 0x46c0, 0xc98d, 0x46ff, 0xc98d, 0x21, 0 - .dw 0x4740, 0xc98d, 0x477f, 0xc98d, 0x21, 0 - .dw 0x47c0, 0xc98d, 0x47ff, 0xc98d, 0x21, 0 - .dw 0x4840, 0xc98d, 0x487f, 0xc98d, 0x21, 0 - .dw 0x48c0, 0xc98d, 0x48ff, 0xc98d, 0x21, 0 - .dw 0x4940, 0xc98d, 0x497f, 0xc98d, 0x21, 0 - .dw 0x49c0, 0xc98d, 0x49ff, 0xc98d, 0x21, 0 - .dw 0x4a40, 0xc98d, 0x4a7f, 0xc98d, 0x21, 0 - .dw 0x4ac0, 0xc98d, 0x4aff, 0xc98d, 0x21, 0 - .dw 0x4b40, 0xc98d, 0x4b7f, 0xc98d, 0x21, 0 - .dw 0x4bc0, 0xc98d, 0x4bff, 0xc98d, 0x21, 0 - .dw 0x4c40, 0xc98d, 0x4c7f, 0xc98d, 0x21, 0 - .dw 0x4cc0, 0xc98d, 0x4cff, 0xc98d, 0x21, 0 - .dw 0x4d40, 0xc98d, 0x4d7f, 0xc98d, 0x21, 0 - .dw 0x4dc0, 0xc98d, 0x4dff, 0xc98d, 0x21, 0 - .dw 0x4e40, 0xc98d, 0x4e7f, 0xc98d, 0x21, 0 - .dw 0x4ec0, 0xc98d, 0x4eff, 0xc98d, 0x21, 0 - .dw 0x4f40, 0xc98d, 0x4f7f, 0xc98d, 0x21, 0 - .dw 0x4fc0, 0xc98d, 0x4fff, 0xc98d, 0x21, 0 - .dw 0x5040, 0xc98d, 0x507f, 0xc98d, 0x21, 0 - .dw 0x50c0, 0xc98d, 0x50ff, 0xc98d, 0x21, 0 - .dw 0x5140, 0xc98d, 0x517f, 0xc98d, 0x21, 0 - .dw 0x51c0, 0xc98d, 0x51ff, 0xc98d, 0x21, 0 - .dw 0x5240, 0xc98d, 0x527f, 0xc98d, 0x21, 0 - .dw 0x52c0, 0xc98d, 0x52ff, 0xc98d, 0x21, 0 - .dw 0x5340, 0xc98d, 0x537f, 0xc98d, 0x21, 0 - .dw 0x53c0, 0xc98d, 0x53ff, 0xc98d, 0x21, 0 - .dw 0x5440, 0xc98d, 0x547f, 0xc98d, 0x21, 0 - .dw 0x54c0, 0xc98d, 0x54ff, 0xc98d, 0x21, 0 - .dw 0x5540, 0xc98d, 0x557f, 0xc98d, 0x21, 0 - .dw 0x55c0, 0xc98d, 0x55ff, 0xc98d, 0x21, 0 - .dw 0x5640, 0xc98d, 0x567f, 0xc98d, 0x21, 0 - .dw 0x56c0, 0xc98d, 0x56ff, 0xc98d, 0x21, 0 - .dw 0x5740, 0xc98d, 0x577f, 0xc98d, 0x21, 0 - .dw 0x57c0, 0xc98d, 0x57ff, 0xc98d, 0x21, 0 - .dw 0x5840, 0xc98d, 0x587f, 0xc98d, 0x21, 0 - .dw 0x58c0, 0xc98d, 0x58ff, 0xc98d, 0x21, 0 - .dw 0x5940, 0xc98d, 0x597f, 0xc98d, 0x21, 0 - .dw 0x59c0, 0xc98d, 0x5fff, 0xc98d, 0x21, 0 - .dw 0x6040, 0xc98d, 0x607f, 0xc98d, 0x21, 0 - .dw 0x60c0, 0xc98d, 0x60ff, 0xc98d, 0x21, 0 - .dw 0x6140, 0xc98d, 0x617f, 0xc98d, 0x21, 0 - .dw 0x61c0, 0xc98d, 0x61ff, 0xc98d, 0x21, 0 - .dw 0x6240, 0xc98d, 0x627f, 0xc98d, 0x21, 0 - .dw 0x62c0, 0xc98d, 0x62ff, 0xc98d, 0x21, 0 - .dw 0x6340, 0xc98d, 0x637f, 0xc98d, 0x21, 0 - .dw 0x63c0, 0xc98d, 0x63ff, 0xc98d, 0x21, 0 - .dw 0x6440, 0xc98d, 0x647f, 0xc98d, 0x21, 0 - .dw 0x64c0, 0xc98d, 0x64ff, 0xc98d, 0x21, 0 - .dw 0x6540, 0xc98d, 0x657f, 0xc98d, 0x21, 0 - .dw 0x65c0, 0xc98d, 0x65ff, 0xc98d, 0x21, 0 - .dw 0x6640, 0xc98d, 0x667f, 0xc98d, 0x21, 0 - .dw 0x66c0, 0xc98d, 0x66ff, 0xc98d, 0x21, 0 - .dw 0x6740, 0xc98d, 0x677f, 0xc98d, 0x21, 0 - .dw 0x67c0, 0xc98d, 0x67ff, 0xc98d, 0x21, 0 - .dw 0x6840, 0xc98d, 0x687f, 0xc98d, 0x21, 0 - .dw 0x68c0, 0xc98d, 0x68ff, 0xc98d, 0x21, 0 - .dw 0x6940, 0xc98d, 0x697f, 0xc98d, 0x21, 0 - .dw 0x69c0, 0xc98d, 0x69ff, 0xc98d, 0x21, 0 - .dw 0x6a40, 0xc98d, 0x6a7f, 0xc98d, 0x21, 0 - .dw 0x6ac0, 0xc98d, 0x6aff, 0xc98d, 0x21, 0 - .dw 0x6b40, 0xc98d, 0x6b7f, 0xc98d, 0x21, 0 - .dw 0x6bc0, 0xc98d, 0x6bff, 0xc98d, 0x21, 0 - .dw 0x6c40, 0xc98d, 0x6c7f, 0xc98d, 0x21, 0 - .dw 0x6cc0, 0xc98d, 0x6cff, 0xc98d, 0x21, 0 - .dw 0x6d40, 0xc98d, 0x6d7f, 0xc98d, 0x21, 0 - .dw 0x6dc0, 0xc98d, 0x6dff, 0xc98d, 0x21, 0 - .dw 0x6e40, 0xc98d, 0x6e7f, 0xc98d, 0x21, 0 - .dw 0x6ec0, 0xc98d, 0x6eff, 0xc98d, 0x21, 0 - .dw 0x6f40, 0xc98d, 0x6f7f, 0xc98d, 0x21, 0 - .dw 0x6fc0, 0xc98d, 0x6fff, 0xc98d, 0x21, 0 - .dw 0x7040, 0xc98d, 0x707f, 0xc98d, 0x21, 0 - .dw 0x70c0, 0xc98d, 0x70ff, 0xc98d, 0x21, 0 - .dw 0x7140, 0xc98d, 0x717f, 0xc98d, 0x21, 0 - .dw 0x71c0, 0xc98d, 0x71ff, 0xc98d, 0x21, 0 - .dw 0x7240, 0xc98d, 0x727f, 0xc98d, 0x21, 0 - .dw 0x72c0, 0xc98d, 0x72ff, 0xc98d, 0x21, 0 - .dw 0x7340, 0xc98d, 0x737f, 0xc98d, 0x21, 0 - .dw 0x73c0, 0xc98d, 0x73ff, 0xc98d, 0x21, 0 - .dw 0x7440, 0xc98d, 0x747f, 0xc98d, 0x21, 0 - .dw 0x74c0, 0xc98d, 0x74ff, 0xc98d, 0x21, 0 - .dw 0x7540, 0xc98d, 0x757f, 0xc98d, 0x21, 0 - .dw 0x75c0, 0xc98d, 0x75ff, 0xc98d, 0x21, 0 - .dw 0x7640, 0xc98d, 0x767f, 0xc98d, 0x21, 0 - .dw 0x76c0, 0xc98d, 0x76ff, 0xc98d, 0x21, 0 - .dw 0x7740, 0xc98d, 0x777f, 0xc98d, 0x21, 0 - .dw 0x77c0, 0xc98d, 0x77ff, 0xc98d, 0x21, 0 - .dw 0x7840, 0xc98d, 0x787f, 0xc98d, 0x21, 0 - .dw 0x78c0, 0xc98d, 0x78ff, 0xc98d, 0x21, 0 - .dw 0x7940, 0xc98d, 0x797f, 0xc98d, 0x21, 0 - .dw 0x79c0, 0xc98d, 0x7fff, 0xc98d, 0x21, 0 - .dw 0x8040, 0xc98d, 0x807f, 0xc98d, 0x21, 0 - .dw 0x80c0, 0xc98d, 0x80ff, 0xc98d, 0x21, 0 - .dw 0x8140, 0xc98d, 0x817f, 0xc98d, 0x21, 0 - .dw 0x81c0, 0xc98d, 0x81ff, 0xc98d, 0x21, 0 - .dw 0x8240, 0xc98d, 0x827f, 0xc98d, 0x21, 0 - .dw 0x82c0, 0xc98d, 0x82ff, 0xc98d, 0x21, 0 - .dw 0x8340, 0xc98d, 0x837f, 0xc98d, 0x21, 0 - .dw 0x83c0, 0xc98d, 0x83ff, 0xc98d, 0x21, 0 - .dw 0x8440, 0xc98d, 0x847f, 0xc98d, 0x21, 0 - .dw 0x84c0, 0xc98d, 0x84ff, 0xc98d, 0x21, 0 - .dw 0x8540, 0xc98d, 0x857f, 0xc98d, 0x21, 0 - .dw 0x85c0, 0xc98d, 0x85ff, 0xc98d, 0x21, 0 - .dw 0x8640, 0xc98d, 0x867f, 0xc98d, 0x21, 0 - .dw 0x86c0, 0xc98d, 0x86ff, 0xc98d, 0x21, 0 - .dw 0x8740, 0xc98d, 0x877f, 0xc98d, 0x21, 0 - .dw 0x87c0, 0xc98d, 0x87ff, 0xc98d, 0x21, 0 - .dw 0x8840, 0xc98d, 0x887f, 0xc98d, 0x21, 0 - .dw 0x88c0, 0xc98d, 0x88ff, 0xc98d, 0x21, 0 - .dw 0x8940, 0xc98d, 0x897f, 0xc98d, 0x21, 0 - .dw 0x89c0, 0xc98d, 0x89ff, 0xc98d, 0x21, 0 - .dw 0x8a40, 0xc98d, 0x8a7f, 0xc98d, 0x21, 0 - .dw 0x8ac0, 0xc98d, 0x8aff, 0xc98d, 0x21, 0 - .dw 0x8b40, 0xc98d, 0x8b7f, 0xc98d, 0x21, 0 - .dw 0x8bc0, 0xc98d, 0x8bff, 0xc98d, 0x21, 0 - .dw 0x8c40, 0xc98d, 0x8c7f, 0xc98d, 0x21, 0 - .dw 0x8cc0, 0xc98d, 0x8cff, 0xc98d, 0x21, 0 - .dw 0x8d40, 0xc98d, 0x8d7f, 0xc98d, 0x21, 0 - .dw 0x8dc0, 0xc98d, 0x8dff, 0xc98d, 0x21, 0 - .dw 0x8e40, 0xc98d, 0x8e7f, 0xc98d, 0x21, 0 - .dw 0x8ec0, 0xc98d, 0x8eff, 0xc98d, 0x21, 0 - .dw 0x8f40, 0xc98d, 0x8f7f, 0xc98d, 0x21, 0 - .dw 0x8fc0, 0xc98d, 0x8fff, 0xc98d, 0x21, 0 - .dw 0x9040, 0xc98d, 0x907f, 0xc98d, 0x21, 0 - .dw 0x90c0, 0xc98d, 0x90ff, 0xc98d, 0x21, 0 - .dw 0x9140, 0xc98d, 0x917f, 0xc98d, 0x21, 0 - .dw 0x91c0, 0xc98d, 0x91ff, 0xc98d, 0x21, 0 - .dw 0x9240, 0xc98d, 0x927f, 0xc98d, 0x21, 0 - .dw 0x92c0, 0xc98d, 0x92ff, 0xc98d, 0x21, 0 - .dw 0x9340, 0xc98d, 0x937f, 0xc98d, 0x21, 0 - .dw 0x93c0, 0xc98d, 0x93ff, 0xc98d, 0x21, 0 - .dw 0x9440, 0xc98d, 0x947f, 0xc98d, 0x21, 0 - .dw 0x94c0, 0xc98d, 0x94ff, 0xc98d, 0x21, 0 - .dw 0x9540, 0xc98d, 0x957f, 0xc98d, 0x21, 0 - .dw 0x95c0, 0xc98d, 0x95ff, 0xc98d, 0x21, 0 - .dw 0x9640, 0xc98d, 0x967f, 0xc98d, 0x21, 0 - .dw 0x96c0, 0xc98d, 0x96ff, 0xc98d, 0x21, 0 - .dw 0x9740, 0xc98d, 0x977f, 0xc98d, 0x21, 0 - .dw 0x97c0, 0xc98d, 0x97ff, 0xc98d, 0x21, 0 - .dw 0x9840, 0xc98d, 0x987f, 0xc98d, 0x21, 0 - .dw 0x98c0, 0xc98d, 0x98ff, 0xc98d, 0x21, 0 - .dw 0x9940, 0xc98d, 0x997f, 0xc98d, 0x21, 0 - .dw 0x99c0, 0xc98d, 0x9fff, 0xc98d, 0x21, 0 - .dw 0xa040, 0xc98d, 0xa07f, 0xc98d, 0x21, 0 - .dw 0xa0c0, 0xc98d, 0xa0ff, 0xc98d, 0x21, 0 - .dw 0xa140, 0xc98d, 0xa17f, 0xc98d, 0x21, 0 - .dw 0xa1c0, 0xc98d, 0xa1ff, 0xc98d, 0x21, 0 - .dw 0xa240, 0xc98d, 0xa27f, 0xc98d, 0x21, 0 - .dw 0xa2c0, 0xc98d, 0xa2ff, 0xc98d, 0x21, 0 - .dw 0xa340, 0xc98d, 0xa37f, 0xc98d, 0x21, 0 - .dw 0xa3c0, 0xc98d, 0xa3ff, 0xc98d, 0x21, 0 - .dw 0xa440, 0xc98d, 0xa47f, 0xc98d, 0x21, 0 - .dw 0xa4c0, 0xc98d, 0xa4ff, 0xc98d, 0x21, 0 - .dw 0xa540, 0xc98d, 0xa57f, 0xc98d, 0x21, 0 - .dw 0xa5c0, 0xc98d, 0xa5ff, 0xc98d, 0x21, 0 - .dw 0xa640, 0xc98d, 0xa67f, 0xc98d, 0x21, 0 - .dw 0xa6c0, 0xc98d, 0xa6ff, 0xc98d, 0x21, 0 - .dw 0xa740, 0xc98d, 0xa77f, 0xc98d, 0x21, 0 - .dw 0xa7c0, 0xc98d, 0xa7ff, 0xc98d, 0x21, 0 - .dw 0xa840, 0xc98d, 0xa87f, 0xc98d, 0x21, 0 - .dw 0xa8c0, 0xc98d, 0xa8ff, 0xc98d, 0x21, 0 - .dw 0xa940, 0xc98d, 0xa97f, 0xc98d, 0x21, 0 - .dw 0xa9c0, 0xc98d, 0xa9ff, 0xc98d, 0x21, 0 - .dw 0xaa40, 0xc98d, 0xaa7f, 0xc98d, 0x21, 0 - .dw 0xaac0, 0xc98d, 0xaaff, 0xc98d, 0x21, 0 - .dw 0xab40, 0xc98d, 0xab7f, 0xc98d, 0x21, 0 - .dw 0xabc0, 0xc98d, 0xabff, 0xc98d, 0x21, 0 - .dw 0xac40, 0xc98d, 0xac7f, 0xc98d, 0x21, 0 - .dw 0xacc0, 0xc98d, 0xacff, 0xc98d, 0x21, 0 - .dw 0xad40, 0xc98d, 0xad7f, 0xc98d, 0x21, 0 - .dw 0xadc0, 0xc98d, 0xadff, 0xc98d, 0x21, 0 - .dw 0xae40, 0xc98d, 0xae7f, 0xc98d, 0x21, 0 - .dw 0xaec0, 0xc98d, 0xaeff, 0xc98d, 0x21, 0 - .dw 0xaf40, 0xc98d, 0xaf7f, 0xc98d, 0x21, 0 - .dw 0xafc0, 0xc98d, 0xafff, 0xc98d, 0x21, 0 - .dw 0xb040, 0xc98d, 0xb07f, 0xc98d, 0x21, 0 - .dw 0xb0c0, 0xc98d, 0xb0ff, 0xc98d, 0x21, 0 - .dw 0xb140, 0xc98d, 0xb17f, 0xc98d, 0x21, 0 - .dw 0xb1c0, 0xc98d, 0xb1ff, 0xc98d, 0x21, 0 - .dw 0xb240, 0xc98d, 0xb27f, 0xc98d, 0x21, 0 - .dw 0xb2c0, 0xc98d, 0xb2ff, 0xc98d, 0x21, 0 - .dw 0xb340, 0xc98d, 0xb37f, 0xc98d, 0x21, 0 - .dw 0xb3c0, 0xc98d, 0xb3ff, 0xc98d, 0x21, 0 - .dw 0xb440, 0xc98d, 0xb47f, 0xc98d, 0x21, 0 - .dw 0xb4c0, 0xc98d, 0xb4ff, 0xc98d, 0x21, 0 - .dw 0xb540, 0xc98d, 0xb57f, 0xc98d, 0x21, 0 - .dw 0xb5c0, 0xc98d, 0xb5ff, 0xc98d, 0x21, 0 - .dw 0xb640, 0xc98d, 0xb67f, 0xc98d, 0x21, 0 - .dw 0xb6c0, 0xc98d, 0xb6ff, 0xc98d, 0x21, 0 - .dw 0xb740, 0xc98d, 0xb77f, 0xc98d, 0x21, 0 - .dw 0xb7c0, 0xc98d, 0xb7ff, 0xc98d, 0x21, 0 - .dw 0xb840, 0xc98d, 0xb87f, 0xc98d, 0x21, 0 - .dw 0xb8c0, 0xc98d, 0xb8ff, 0xc98d, 0x21, 0 - .dw 0xb940, 0xc98d, 0xb97f, 0xc98d, 0x21, 0 - .dw 0xb9c0, 0xc98d, 0xbfff, 0xc98d, 0x21, 0 - .dw 0xc040, 0xc98d, 0xc07f, 0xc98d, 0x21, 0 - .dw 0xc0c0, 0xc98d, 0xc0ff, 0xc98d, 0x21, 0 - .dw 0xc140, 0xc98d, 0xc17f, 0xc98d, 0x21, 0 - .dw 0xc1c0, 0xc98d, 0xc1ff, 0xc98d, 0x21, 0 - .dw 0xc240, 0xc98d, 0xc27f, 0xc98d, 0x21, 0 - .dw 0xc2c0, 0xc98d, 0xc2ff, 0xc98d, 0x21, 0 - .dw 0xc340, 0xc98d, 0xc37f, 0xc98d, 0x21, 0 - .dw 0xc3c0, 0xc98d, 0xc3ff, 0xc98d, 0x21, 0 - .dw 0xc440, 0xc98d, 0xc47f, 0xc98d, 0x21, 0 - .dw 0xc4c0, 0xc98d, 0xc4ff, 0xc98d, 0x21, 0 - .dw 0xc540, 0xc98d, 0xc57f, 0xc98d, 0x21, 0 - .dw 0xc5c0, 0xc98d, 0xc5ff, 0xc98d, 0x21, 0 - .dw 0xc640, 0xc98d, 0xc67f, 0xc98d, 0x21, 0 - .dw 0xc6c0, 0xc98d, 0xc6ff, 0xc98d, 0x21, 0 - .dw 0xc740, 0xc98d, 0xc77f, 0xc98d, 0x21, 0 - .dw 0xc7c0, 0xc98d, 0xc7ff, 0xc98d, 0x21, 0 - .dw 0xc840, 0xc98d, 0xc87f, 0xc98d, 0x21, 0 - .dw 0xc8c0, 0xc98d, 0xc8ff, 0xc98d, 0x21, 0 - .dw 0xc940, 0xc98d, 0xc97f, 0xc98d, 0x21, 0 - .dw 0xc9c0, 0xc98d, 0xc9ff, 0xc98d, 0x21, 0 - .dw 0xca40, 0xc98d, 0xca7f, 0xc98d, 0x21, 0 - .dw 0xcac0, 0xc98d, 0xcaff, 0xc98d, 0x21, 0 - .dw 0xcb40, 0xc98d, 0xcb7f, 0xc98d, 0x21, 0 - .dw 0xcbc0, 0xc98d, 0xcbff, 0xc98d, 0x21, 0 - .dw 0xcc40, 0xc98d, 0xcc7f, 0xc98d, 0x21, 0 - .dw 0xccc0, 0xc98d, 0xccff, 0xc98d, 0x21, 0 - .dw 0xcd40, 0xc98d, 0xcd7f, 0xc98d, 0x21, 0 - .dw 0xcdc0, 0xc98d, 0xcdff, 0xc98d, 0x21, 0 - .dw 0xce40, 0xc98d, 0xce7f, 0xc98d, 0x21, 0 - .dw 0xcec0, 0xc98d, 0xceff, 0xc98d, 0x21, 0 - .dw 0xcf40, 0xc98d, 0xcf7f, 0xc98d, 0x21, 0 - .dw 0xcfc0, 0xc98d, 0xcfff, 0xc98d, 0x21, 0 - .dw 0xd040, 0xc98d, 0xd07f, 0xc98d, 0x21, 0 - .dw 0xd0c0, 0xc98d, 0xd0ff, 0xc98d, 0x21, 0 - .dw 0xd140, 0xc98d, 0xd17f, 0xc98d, 0x21, 0 - .dw 0xd1c0, 0xc98d, 0xd1ff, 0xc98d, 0x21, 0 - .dw 0xd240, 0xc98d, 0xd27f, 0xc98d, 0x21, 0 - .dw 0xd2c0, 0xc98d, 0xd2ff, 0xc98d, 0x21, 0 - .dw 0xd340, 0xc98d, 0xd37f, 0xc98d, 0x21, 0 - .dw 0xd3c0, 0xc98d, 0xd3ff, 0xc98d, 0x21, 0 - .dw 0xd440, 0xc98d, 0xd47f, 0xc98d, 0x21, 0 - .dw 0xd4c0, 0xc98d, 0xd4ff, 0xc98d, 0x21, 0 - .dw 0xd540, 0xc98d, 0xd57f, 0xc98d, 0x21, 0 - .dw 0xd5c0, 0xc98d, 0xd5ff, 0xc98d, 0x21, 0 - .dw 0xd640, 0xc98d, 0xd67f, 0xc98d, 0x21, 0 - .dw 0xd6c0, 0xc98d, 0xd6ff, 0xc98d, 0x21, 0 - .dw 0xd740, 0xc98d, 0xd77f, 0xc98d, 0x21, 0 - .dw 0xd7c0, 0xc98d, 0xd7ff, 0xc98d, 0x21, 0 - .dw 0xd840, 0xc98d, 0xd87f, 0xc98d, 0x21, 0 - .dw 0xd8c0, 0xc98d, 0xd8ff, 0xc98d, 0x21, 0 - .dw 0xd940, 0xc98d, 0xd97f, 0xc98d, 0x21, 0 - .dw 0xd9c0, 0xc98d, 0xdfff, 0xc98d, 0x21, 0 - .dw 0xe040, 0xc98d, 0xe07f, 0xc98d, 0x21, 0 - .dw 0xe0c0, 0xc98d, 0xe0ff, 0xc98d, 0x21, 0 - .dw 0xe140, 0xc98d, 0xe17f, 0xc98d, 0x21, 0 - .dw 0xe1c0, 0xc98d, 0xe1ff, 0xc98d, 0x21, 0 - .dw 0xe240, 0xc98d, 0xe27f, 0xc98d, 0x21, 0 - .dw 0xe2c0, 0xc98d, 0xe2ff, 0xc98d, 0x21, 0 - .dw 0xe340, 0xc98d, 0xe37f, 0xc98d, 0x21, 0 - .dw 0xe3c0, 0xc98d, 0xe3ff, 0xc98d, 0x21, 0 - .dw 0xe440, 0xc98d, 0xe47f, 0xc98d, 0x21, 0 - .dw 0xe4c0, 0xc98d, 0xe4ff, 0xc98d, 0x21, 0 - .dw 0xe540, 0xc98d, 0xe57f, 0xc98d, 0x21, 0 - .dw 0xe5c0, 0xc98d, 0xe5ff, 0xc98d, 0x21, 0 - .dw 0xe640, 0xc98d, 0xe67f, 0xc98d, 0x21, 0 - .dw 0xe6c0, 0xc98d, 0xe6ff, 0xc98d, 0x21, 0 - .dw 0xe740, 0xc98d, 0xe77f, 0xc98d, 0x21, 0 - .dw 0xe7c0, 0xc98d, 0xe7ff, 0xc98d, 0x21, 0 - .dw 0xe840, 0xc98d, 0xe87f, 0xc98d, 0x21, 0 - .dw 0xe8c0, 0xc98d, 0xe8ff, 0xc98d, 0x21, 0 - .dw 0xe940, 0xc98d, 0xe97f, 0xc98d, 0x21, 0 - .dw 0xe9c0, 0xc98d, 0xe9ff, 0xc98d, 0x21, 0 - .dw 0xea40, 0xc98d, 0xea7f, 0xc98d, 0x21, 0 - .dw 0xeac0, 0xc98d, 0xeaff, 0xc98d, 0x21, 0 - .dw 0xeb40, 0xc98d, 0xeb7f, 0xc98d, 0x21, 0 - .dw 0xebc0, 0xc98d, 0xebff, 0xc98d, 0x21, 0 - .dw 0xec40, 0xc98d, 0xec7f, 0xc98d, 0x21, 0 - .dw 0xecc0, 0xc98d, 0xecff, 0xc98d, 0x21, 0 - .dw 0xed40, 0xc98d, 0xed7f, 0xc98d, 0x21, 0 - .dw 0xedc0, 0xc98d, 0xedff, 0xc98d, 0x21, 0 - .dw 0xee40, 0xc98d, 0xee7f, 0xc98d, 0x21, 0 - .dw 0xeec0, 0xc98d, 0xeeff, 0xc98d, 0x21, 0 - .dw 0xef40, 0xc98d, 0xef7f, 0xc98d, 0x21, 0 - .dw 0xefc0, 0xc98d, 0xefff, 0xc98d, 0x21, 0 - .dw 0xf040, 0xc98d, 0xf07f, 0xc98d, 0x21, 0 - .dw 0xf0c0, 0xc98d, 0xf0ff, 0xc98d, 0x21, 0 - .dw 0xf140, 0xc98d, 0xf17f, 0xc98d, 0x21, 0 - .dw 0xf1c0, 0xc98d, 0xf1ff, 0xc98d, 0x21, 0 - .dw 0xf240, 0xc98d, 0xf27f, 0xc98d, 0x21, 0 - .dw 0xf2c0, 0xc98d, 0xf2ff, 0xc98d, 0x21, 0 - .dw 0xf340, 0xc98d, 0xf37f, 0xc98d, 0x21, 0 - .dw 0xf3c0, 0xc98d, 0xf3ff, 0xc98d, 0x21, 0 - .dw 0xf440, 0xc98d, 0xf47f, 0xc98d, 0x21, 0 - .dw 0xf4c0, 0xc98d, 0xf4ff, 0xc98d, 0x21, 0 - .dw 0xf540, 0xc98d, 0xf57f, 0xc98d, 0x21, 0 - .dw 0xf5c0, 0xc98d, 0xf5ff, 0xc98d, 0x21, 0 - .dw 0xf640, 0xc98d, 0xf67f, 0xc98d, 0x21, 0 - .dw 0xf6c0, 0xc98d, 0xf6ff, 0xc98d, 0x21, 0 - .dw 0xf740, 0xc98d, 0xf77f, 0xc98d, 0x21, 0 - .dw 0xf7c0, 0xc98d, 0xf7ff, 0xc98d, 0x21, 0 - .dw 0xf840, 0xc98d, 0xf87f, 0xc98d, 0x21, 0 - .dw 0xf8c0, 0xc98d, 0xf8ff, 0xc98d, 0x21, 0 - .dw 0xf940, 0xc98d, 0xf97f, 0xc98d, 0x21, 0 - .dw 0xf9c0, 0xc98d, 0xffff, 0xc98d, 0x21, 0 - .dw 0x0040, 0xc98e, 0x007f, 0xc98e, 0x21, 0 - .dw 0x00c0, 0xc98e, 0x00ff, 0xc98e, 0x21, 0 - .dw 0x0140, 0xc98e, 0x017f, 0xc98e, 0x21, 0 - .dw 0x01c0, 0xc98e, 0x01ff, 0xc98e, 0x21, 0 - .dw 0x0240, 0xc98e, 0x027f, 0xc98e, 0x21, 0 - .dw 0x02c0, 0xc98e, 0x02ff, 0xc98e, 0x21, 0 - .dw 0x0340, 0xc98e, 0x037f, 0xc98e, 0x21, 0 - .dw 0x03c0, 0xc98e, 0x03ff, 0xc98e, 0x21, 0 - .dw 0x0440, 0xc98e, 0x047f, 0xc98e, 0x21, 0 - .dw 0x04c0, 0xc98e, 0x04ff, 0xc98e, 0x21, 0 - .dw 0x0540, 0xc98e, 0x057f, 0xc98e, 0x21, 0 - .dw 0x05c0, 0xc98e, 0x05ff, 0xc98e, 0x21, 0 - .dw 0x0640, 0xc98e, 0x067f, 0xc98e, 0x21, 0 - .dw 0x06c0, 0xc98e, 0x06ff, 0xc98e, 0x21, 0 - .dw 0x0740, 0xc98e, 0x077f, 0xc98e, 0x21, 0 - .dw 0x07c0, 0xc98e, 0x07ff, 0xc98e, 0x21, 0 - .dw 0x0840, 0xc98e, 0x087f, 0xc98e, 0x21, 0 - .dw 0x08c0, 0xc98e, 0x08ff, 0xc98e, 0x21, 0 - .dw 0x0940, 0xc98e, 0x097f, 0xc98e, 0x21, 0 - .dw 0x09c0, 0xc98e, 0x09ff, 0xc98e, 0x21, 0 - .dw 0x0a40, 0xc98e, 0x0a7f, 0xc98e, 0x21, 0 - .dw 0x0ac0, 0xc98e, 0x0aff, 0xc98e, 0x21, 0 - .dw 0x0b40, 0xc98e, 0x0b7f, 0xc98e, 0x21, 0 - .dw 0x0bc0, 0xc98e, 0x0bff, 0xc98e, 0x21, 0 - .dw 0x0c40, 0xc98e, 0x0c7f, 0xc98e, 0x21, 0 - .dw 0x0cc0, 0xc98e, 0x0cff, 0xc98e, 0x21, 0 - .dw 0x0d40, 0xc98e, 0x0d7f, 0xc98e, 0x21, 0 - .dw 0x0dc0, 0xc98e, 0x0dff, 0xc98e, 0x21, 0 - .dw 0x0e40, 0xc98e, 0x0e7f, 0xc98e, 0x21, 0 - .dw 0x0ec0, 0xc98e, 0x0eff, 0xc98e, 0x21, 0 - .dw 0x0f40, 0xc98e, 0x0f7f, 0xc98e, 0x21, 0 - .dw 0x0fc0, 0xc98e, 0x0fff, 0xc98e, 0x21, 0 - .dw 0x1040, 0xc98e, 0x107f, 0xc98e, 0x21, 0 - .dw 0x10c0, 0xc98e, 0x10ff, 0xc98e, 0x21, 0 - .dw 0x1140, 0xc98e, 0x117f, 0xc98e, 0x21, 0 - .dw 0x11c0, 0xc98e, 0x11ff, 0xc98e, 0x21, 0 - .dw 0x1240, 0xc98e, 0x127f, 0xc98e, 0x21, 0 - .dw 0x12c0, 0xc98e, 0x12ff, 0xc98e, 0x21, 0 - .dw 0x1340, 0xc98e, 0x137f, 0xc98e, 0x21, 0 - .dw 0x13c0, 0xc98e, 0x13ff, 0xc98e, 0x21, 0 - .dw 0x1440, 0xc98e, 0x147f, 0xc98e, 0x21, 0 - .dw 0x14c0, 0xc98e, 0x14ff, 0xc98e, 0x21, 0 - .dw 0x1540, 0xc98e, 0x157f, 0xc98e, 0x21, 0 - .dw 0x15c0, 0xc98e, 0x15ff, 0xc98e, 0x21, 0 - .dw 0x1640, 0xc98e, 0x167f, 0xc98e, 0x21, 0 - .dw 0x16c0, 0xc98e, 0x16ff, 0xc98e, 0x21, 0 - .dw 0x1740, 0xc98e, 0x177f, 0xc98e, 0x21, 0 - .dw 0x17c0, 0xc98e, 0x17ff, 0xc98e, 0x21, 0 - .dw 0x1840, 0xc98e, 0x187f, 0xc98e, 0x21, 0 - .dw 0x18c0, 0xc98e, 0x18ff, 0xc98e, 0x21, 0 - .dw 0x1940, 0xc98e, 0x197f, 0xc98e, 0x21, 0 - .dw 0x19c0, 0xc98e, 0x1fff, 0xc98e, 0x21, 0 - .dw 0x2040, 0xc98e, 0x207f, 0xc98e, 0x21, 0 - .dw 0x20c0, 0xc98e, 0x20ff, 0xc98e, 0x21, 0 - .dw 0x2140, 0xc98e, 0x217f, 0xc98e, 0x21, 0 - .dw 0x21c0, 0xc98e, 0x21ff, 0xc98e, 0x21, 0 - .dw 0x2240, 0xc98e, 0x227f, 0xc98e, 0x21, 0 - .dw 0x22c0, 0xc98e, 0x22ff, 0xc98e, 0x21, 0 - .dw 0x2340, 0xc98e, 0x237f, 0xc98e, 0x21, 0 - .dw 0x23c0, 0xc98e, 0x23ff, 0xc98e, 0x21, 0 - .dw 0x2440, 0xc98e, 0x247f, 0xc98e, 0x21, 0 - .dw 0x24c0, 0xc98e, 0x24ff, 0xc98e, 0x21, 0 - .dw 0x2540, 0xc98e, 0x257f, 0xc98e, 0x21, 0 - .dw 0x25c0, 0xc98e, 0x25ff, 0xc98e, 0x21, 0 - .dw 0x2640, 0xc98e, 0x267f, 0xc98e, 0x21, 0 - .dw 0x26c0, 0xc98e, 0x26ff, 0xc98e, 0x21, 0 - .dw 0x2740, 0xc98e, 0x277f, 0xc98e, 0x21, 0 - .dw 0x27c0, 0xc98e, 0x27ff, 0xc98e, 0x21, 0 - .dw 0x2840, 0xc98e, 0x287f, 0xc98e, 0x21, 0 - .dw 0x28c0, 0xc98e, 0x28ff, 0xc98e, 0x21, 0 - .dw 0x2940, 0xc98e, 0x297f, 0xc98e, 0x21, 0 - .dw 0x29c0, 0xc98e, 0x29ff, 0xc98e, 0x21, 0 - .dw 0x2a40, 0xc98e, 0x2a7f, 0xc98e, 0x21, 0 - .dw 0x2ac0, 0xc98e, 0x2aff, 0xc98e, 0x21, 0 - .dw 0x2b40, 0xc98e, 0x2b7f, 0xc98e, 0x21, 0 - .dw 0x2bc0, 0xc98e, 0x2bff, 0xc98e, 0x21, 0 - .dw 0x2c40, 0xc98e, 0x2c7f, 0xc98e, 0x21, 0 - .dw 0x2cc0, 0xc98e, 0x2cff, 0xc98e, 0x21, 0 - .dw 0x2d40, 0xc98e, 0x2d7f, 0xc98e, 0x21, 0 - .dw 0x2dc0, 0xc98e, 0x2dff, 0xc98e, 0x21, 0 - .dw 0x2e40, 0xc98e, 0x2e7f, 0xc98e, 0x21, 0 - .dw 0x2ec0, 0xc98e, 0x2eff, 0xc98e, 0x21, 0 - .dw 0x2f40, 0xc98e, 0x2f7f, 0xc98e, 0x21, 0 - .dw 0x2fc0, 0xc98e, 0x2fff, 0xc98e, 0x21, 0 - .dw 0x3040, 0xc98e, 0x307f, 0xc98e, 0x21, 0 - .dw 0x30c0, 0xc98e, 0x30ff, 0xc98e, 0x21, 0 - .dw 0x3140, 0xc98e, 0x317f, 0xc98e, 0x21, 0 - .dw 0x31c0, 0xc98e, 0x31ff, 0xc98e, 0x21, 0 - .dw 0x3240, 0xc98e, 0x327f, 0xc98e, 0x21, 0 - .dw 0x32c0, 0xc98e, 0x32ff, 0xc98e, 0x21, 0 - .dw 0x3340, 0xc98e, 0x337f, 0xc98e, 0x21, 0 - .dw 0x33c0, 0xc98e, 0x33ff, 0xc98e, 0x21, 0 - .dw 0x3440, 0xc98e, 0x347f, 0xc98e, 0x21, 0 - .dw 0x34c0, 0xc98e, 0x34ff, 0xc98e, 0x21, 0 - .dw 0x3540, 0xc98e, 0x357f, 0xc98e, 0x21, 0 - .dw 0x35c0, 0xc98e, 0x35ff, 0xc98e, 0x21, 0 - .dw 0x3640, 0xc98e, 0x367f, 0xc98e, 0x21, 0 - .dw 0x36c0, 0xc98e, 0x36ff, 0xc98e, 0x21, 0 - .dw 0x3740, 0xc98e, 0x377f, 0xc98e, 0x21, 0 - .dw 0x37c0, 0xc98e, 0x37ff, 0xc98e, 0x21, 0 - .dw 0x3840, 0xc98e, 0x387f, 0xc98e, 0x21, 0 - .dw 0x38c0, 0xc98e, 0x38ff, 0xc98e, 0x21, 0 - .dw 0x3940, 0xc98e, 0x397f, 0xc98e, 0x21, 0 - .dw 0x39c0, 0xc98e, 0x3fff, 0xc98e, 0x21, 0 - .dw 0x4040, 0xc98e, 0x407f, 0xc98e, 0x21, 0 - .dw 0x40c0, 0xc98e, 0x40ff, 0xc98e, 0x21, 0 - .dw 0x4140, 0xc98e, 0x417f, 0xc98e, 0x21, 0 - .dw 0x41c0, 0xc98e, 0x41ff, 0xc98e, 0x21, 0 - .dw 0x4240, 0xc98e, 0x427f, 0xc98e, 0x21, 0 - .dw 0x42c0, 0xc98e, 0x42ff, 0xc98e, 0x21, 0 - .dw 0x4340, 0xc98e, 0x437f, 0xc98e, 0x21, 0 - .dw 0x43c0, 0xc98e, 0x43ff, 0xc98e, 0x21, 0 - .dw 0x4440, 0xc98e, 0x447f, 0xc98e, 0x21, 0 - .dw 0x44c0, 0xc98e, 0x44ff, 0xc98e, 0x21, 0 - .dw 0x4540, 0xc98e, 0x457f, 0xc98e, 0x21, 0 - .dw 0x45c0, 0xc98e, 0x45ff, 0xc98e, 0x21, 0 - .dw 0x4640, 0xc98e, 0x467f, 0xc98e, 0x21, 0 - .dw 0x46c0, 0xc98e, 0x46ff, 0xc98e, 0x21, 0 - .dw 0x4740, 0xc98e, 0x477f, 0xc98e, 0x21, 0 - .dw 0x47c0, 0xc98e, 0x47ff, 0xc98e, 0x21, 0 - .dw 0x4840, 0xc98e, 0x487f, 0xc98e, 0x21, 0 - .dw 0x48c0, 0xc98e, 0x48ff, 0xc98e, 0x21, 0 - .dw 0x4940, 0xc98e, 0x497f, 0xc98e, 0x21, 0 - .dw 0x49c0, 0xc98e, 0x49ff, 0xc98e, 0x21, 0 - .dw 0x4a40, 0xc98e, 0x4a7f, 0xc98e, 0x21, 0 - .dw 0x4ac0, 0xc98e, 0x4aff, 0xc98e, 0x21, 0 - .dw 0x4b40, 0xc98e, 0x4b7f, 0xc98e, 0x21, 0 - .dw 0x4bc0, 0xc98e, 0x4bff, 0xc98e, 0x21, 0 - .dw 0x4c40, 0xc98e, 0x4c7f, 0xc98e, 0x21, 0 - .dw 0x4cc0, 0xc98e, 0x4cff, 0xc98e, 0x21, 0 - .dw 0x4d40, 0xc98e, 0x4d7f, 0xc98e, 0x21, 0 - .dw 0x4dc0, 0xc98e, 0x4dff, 0xc98e, 0x21, 0 - .dw 0x4e40, 0xc98e, 0x4e7f, 0xc98e, 0x21, 0 - .dw 0x4ec0, 0xc98e, 0x4eff, 0xc98e, 0x21, 0 - .dw 0x4f40, 0xc98e, 0x4f7f, 0xc98e, 0x21, 0 - .dw 0x4fc0, 0xc98e, 0x4fff, 0xc98e, 0x21, 0 - .dw 0x5040, 0xc98e, 0x507f, 0xc98e, 0x21, 0 - .dw 0x50c0, 0xc98e, 0x50ff, 0xc98e, 0x21, 0 - .dw 0x5140, 0xc98e, 0x517f, 0xc98e, 0x21, 0 - .dw 0x51c0, 0xc98e, 0x51ff, 0xc98e, 0x21, 0 - .dw 0x5240, 0xc98e, 0x527f, 0xc98e, 0x21, 0 - .dw 0x52c0, 0xc98e, 0x52ff, 0xc98e, 0x21, 0 - .dw 0x5340, 0xc98e, 0x537f, 0xc98e, 0x21, 0 - .dw 0x53c0, 0xc98e, 0x53ff, 0xc98e, 0x21, 0 - .dw 0x5440, 0xc98e, 0x547f, 0xc98e, 0x21, 0 - .dw 0x54c0, 0xc98e, 0x54ff, 0xc98e, 0x21, 0 - .dw 0x5540, 0xc98e, 0x557f, 0xc98e, 0x21, 0 - .dw 0x55c0, 0xc98e, 0x55ff, 0xc98e, 0x21, 0 - .dw 0x5640, 0xc98e, 0x567f, 0xc98e, 0x21, 0 - .dw 0x56c0, 0xc98e, 0x56ff, 0xc98e, 0x21, 0 - .dw 0x5740, 0xc98e, 0x577f, 0xc98e, 0x21, 0 - .dw 0x57c0, 0xc98e, 0x57ff, 0xc98e, 0x21, 0 - .dw 0x5840, 0xc98e, 0x587f, 0xc98e, 0x21, 0 - .dw 0x58c0, 0xc98e, 0x58ff, 0xc98e, 0x21, 0 - .dw 0x5940, 0xc98e, 0x597f, 0xc98e, 0x21, 0 - .dw 0x59c0, 0xc98e, 0x5fff, 0xc98e, 0x21, 0 - .dw 0x6040, 0xc98e, 0x607f, 0xc98e, 0x21, 0 - .dw 0x60c0, 0xc98e, 0x60ff, 0xc98e, 0x21, 0 - .dw 0x6140, 0xc98e, 0x617f, 0xc98e, 0x21, 0 - .dw 0x61c0, 0xc98e, 0x61ff, 0xc98e, 0x21, 0 - .dw 0x6240, 0xc98e, 0x627f, 0xc98e, 0x21, 0 - .dw 0x62c0, 0xc98e, 0x62ff, 0xc98e, 0x21, 0 - .dw 0x6340, 0xc98e, 0x637f, 0xc98e, 0x21, 0 - .dw 0x63c0, 0xc98e, 0x63ff, 0xc98e, 0x21, 0 - .dw 0x6440, 0xc98e, 0x647f, 0xc98e, 0x21, 0 - .dw 0x64c0, 0xc98e, 0x64ff, 0xc98e, 0x21, 0 - .dw 0x6540, 0xc98e, 0x657f, 0xc98e, 0x21, 0 - .dw 0x65c0, 0xc98e, 0x65ff, 0xc98e, 0x21, 0 - .dw 0x6640, 0xc98e, 0x667f, 0xc98e, 0x21, 0 - .dw 0x66c0, 0xc98e, 0x66ff, 0xc98e, 0x21, 0 - .dw 0x6740, 0xc98e, 0x677f, 0xc98e, 0x21, 0 - .dw 0x67c0, 0xc98e, 0x67ff, 0xc98e, 0x21, 0 - .dw 0x6840, 0xc98e, 0x687f, 0xc98e, 0x21, 0 - .dw 0x68c0, 0xc98e, 0x68ff, 0xc98e, 0x21, 0 - .dw 0x6940, 0xc98e, 0x697f, 0xc98e, 0x21, 0 - .dw 0x69c0, 0xc98e, 0x69ff, 0xc98e, 0x21, 0 - .dw 0x6a40, 0xc98e, 0x6a7f, 0xc98e, 0x21, 0 - .dw 0x6ac0, 0xc98e, 0x6aff, 0xc98e, 0x21, 0 - .dw 0x6b40, 0xc98e, 0x6b7f, 0xc98e, 0x21, 0 - .dw 0x6bc0, 0xc98e, 0x6bff, 0xc98e, 0x21, 0 - .dw 0x6c40, 0xc98e, 0x6c7f, 0xc98e, 0x21, 0 - .dw 0x6cc0, 0xc98e, 0x6cff, 0xc98e, 0x21, 0 - .dw 0x6d40, 0xc98e, 0x6d7f, 0xc98e, 0x21, 0 - .dw 0x6dc0, 0xc98e, 0x6dff, 0xc98e, 0x21, 0 - .dw 0x6e40, 0xc98e, 0x6e7f, 0xc98e, 0x21, 0 - .dw 0x6ec0, 0xc98e, 0x6eff, 0xc98e, 0x21, 0 - .dw 0x6f40, 0xc98e, 0x6f7f, 0xc98e, 0x21, 0 - .dw 0x6fc0, 0xc98e, 0x6fff, 0xc98e, 0x21, 0 - .dw 0x7040, 0xc98e, 0x707f, 0xc98e, 0x21, 0 - .dw 0x70c0, 0xc98e, 0x70ff, 0xc98e, 0x21, 0 - .dw 0x7140, 0xc98e, 0x717f, 0xc98e, 0x21, 0 - .dw 0x71c0, 0xc98e, 0x71ff, 0xc98e, 0x21, 0 - .dw 0x7240, 0xc98e, 0x727f, 0xc98e, 0x21, 0 - .dw 0x72c0, 0xc98e, 0x72ff, 0xc98e, 0x21, 0 - .dw 0x7340, 0xc98e, 0x737f, 0xc98e, 0x21, 0 - .dw 0x73c0, 0xc98e, 0x73ff, 0xc98e, 0x21, 0 - .dw 0x7440, 0xc98e, 0x747f, 0xc98e, 0x21, 0 - .dw 0x74c0, 0xc98e, 0x74ff, 0xc98e, 0x21, 0 - .dw 0x7540, 0xc98e, 0x757f, 0xc98e, 0x21, 0 - .dw 0x75c0, 0xc98e, 0x75ff, 0xc98e, 0x21, 0 - .dw 0x7640, 0xc98e, 0x767f, 0xc98e, 0x21, 0 - .dw 0x76c0, 0xc98e, 0x76ff, 0xc98e, 0x21, 0 - .dw 0x7740, 0xc98e, 0x777f, 0xc98e, 0x21, 0 - .dw 0x77c0, 0xc98e, 0x77ff, 0xc98e, 0x21, 0 - .dw 0x7840, 0xc98e, 0x787f, 0xc98e, 0x21, 0 - .dw 0x78c0, 0xc98e, 0x78ff, 0xc98e, 0x21, 0 - .dw 0x7940, 0xc98e, 0x797f, 0xc98e, 0x21, 0 - .dw 0x79c0, 0xc98e, 0x7fff, 0xc98e, 0x21, 0 - .dw 0x8040, 0xc98e, 0x807f, 0xc98e, 0x21, 0 - .dw 0x80c0, 0xc98e, 0x80ff, 0xc98e, 0x21, 0 - .dw 0x8140, 0xc98e, 0x817f, 0xc98e, 0x21, 0 - .dw 0x81c0, 0xc98e, 0x81ff, 0xc98e, 0x21, 0 - .dw 0x8240, 0xc98e, 0x827f, 0xc98e, 0x21, 0 - .dw 0x82c0, 0xc98e, 0x82ff, 0xc98e, 0x21, 0 - .dw 0x8340, 0xc98e, 0x837f, 0xc98e, 0x21, 0 - .dw 0x83c0, 0xc98e, 0x83ff, 0xc98e, 0x21, 0 - .dw 0x8440, 0xc98e, 0x847f, 0xc98e, 0x21, 0 - .dw 0x84c0, 0xc98e, 0x84ff, 0xc98e, 0x21, 0 - .dw 0x8540, 0xc98e, 0x857f, 0xc98e, 0x21, 0 - .dw 0x85c0, 0xc98e, 0x85ff, 0xc98e, 0x21, 0 - .dw 0x8640, 0xc98e, 0x867f, 0xc98e, 0x21, 0 - .dw 0x86c0, 0xc98e, 0x86ff, 0xc98e, 0x21, 0 - .dw 0x8740, 0xc98e, 0x877f, 0xc98e, 0x21, 0 - .dw 0x87c0, 0xc98e, 0x87ff, 0xc98e, 0x21, 0 - .dw 0x8840, 0xc98e, 0x887f, 0xc98e, 0x21, 0 - .dw 0x88c0, 0xc98e, 0x88ff, 0xc98e, 0x21, 0 - .dw 0x8940, 0xc98e, 0x897f, 0xc98e, 0x21, 0 - .dw 0x89c0, 0xc98e, 0x89ff, 0xc98e, 0x21, 0 - .dw 0x8a40, 0xc98e, 0x8a7f, 0xc98e, 0x21, 0 - .dw 0x8ac0, 0xc98e, 0x8aff, 0xc98e, 0x21, 0 - .dw 0x8b40, 0xc98e, 0x8b7f, 0xc98e, 0x21, 0 - .dw 0x8bc0, 0xc98e, 0x8bff, 0xc98e, 0x21, 0 - .dw 0x8c40, 0xc98e, 0x8c7f, 0xc98e, 0x21, 0 - .dw 0x8cc0, 0xc98e, 0x8cff, 0xc98e, 0x21, 0 - .dw 0x8d40, 0xc98e, 0x8d7f, 0xc98e, 0x21, 0 - .dw 0x8dc0, 0xc98e, 0x8dff, 0xc98e, 0x21, 0 - .dw 0x8e40, 0xc98e, 0x8e7f, 0xc98e, 0x21, 0 - .dw 0x8ec0, 0xc98e, 0x8eff, 0xc98e, 0x21, 0 - .dw 0x8f40, 0xc98e, 0x8f7f, 0xc98e, 0x21, 0 - .dw 0x8fc0, 0xc98e, 0x8fff, 0xc98e, 0x21, 0 - .dw 0x9040, 0xc98e, 0x907f, 0xc98e, 0x21, 0 - .dw 0x90c0, 0xc98e, 0x90ff, 0xc98e, 0x21, 0 - .dw 0x9140, 0xc98e, 0x917f, 0xc98e, 0x21, 0 - .dw 0x91c0, 0xc98e, 0x91ff, 0xc98e, 0x21, 0 - .dw 0x9240, 0xc98e, 0x927f, 0xc98e, 0x21, 0 - .dw 0x92c0, 0xc98e, 0x92ff, 0xc98e, 0x21, 0 - .dw 0x9340, 0xc98e, 0x937f, 0xc98e, 0x21, 0 - .dw 0x93c0, 0xc98e, 0x93ff, 0xc98e, 0x21, 0 - .dw 0x9440, 0xc98e, 0x947f, 0xc98e, 0x21, 0 - .dw 0x94c0, 0xc98e, 0x94ff, 0xc98e, 0x21, 0 - .dw 0x9540, 0xc98e, 0x957f, 0xc98e, 0x21, 0 - .dw 0x95c0, 0xc98e, 0x95ff, 0xc98e, 0x21, 0 - .dw 0x9640, 0xc98e, 0x967f, 0xc98e, 0x21, 0 - .dw 0x96c0, 0xc98e, 0x96ff, 0xc98e, 0x21, 0 - .dw 0x9740, 0xc98e, 0x977f, 0xc98e, 0x21, 0 - .dw 0x97c0, 0xc98e, 0x97ff, 0xc98e, 0x21, 0 - .dw 0x9840, 0xc98e, 0x987f, 0xc98e, 0x21, 0 - .dw 0x98c0, 0xc98e, 0x98ff, 0xc98e, 0x21, 0 - .dw 0x9940, 0xc98e, 0x997f, 0xc98e, 0x21, 0 - .dw 0x99c0, 0xc98e, 0x9fff, 0xc98e, 0x21, 0 - .dw 0xa040, 0xc98e, 0xa07f, 0xc98e, 0x21, 0 - .dw 0xa0c0, 0xc98e, 0xa0ff, 0xc98e, 0x21, 0 - .dw 0xa140, 0xc98e, 0xa17f, 0xc98e, 0x21, 0 - .dw 0xa1c0, 0xc98e, 0xa1ff, 0xc98e, 0x21, 0 - .dw 0xa240, 0xc98e, 0xa27f, 0xc98e, 0x21, 0 - .dw 0xa2c0, 0xc98e, 0xa2ff, 0xc98e, 0x21, 0 - .dw 0xa340, 0xc98e, 0xa37f, 0xc98e, 0x21, 0 - .dw 0xa3c0, 0xc98e, 0xa3ff, 0xc98e, 0x21, 0 - .dw 0xa440, 0xc98e, 0xa47f, 0xc98e, 0x21, 0 - .dw 0xa4c0, 0xc98e, 0xa4ff, 0xc98e, 0x21, 0 - .dw 0xa540, 0xc98e, 0xa57f, 0xc98e, 0x21, 0 - .dw 0xa5c0, 0xc98e, 0xa5ff, 0xc98e, 0x21, 0 - .dw 0xa640, 0xc98e, 0xa67f, 0xc98e, 0x21, 0 - .dw 0xa6c0, 0xc98e, 0xa6ff, 0xc98e, 0x21, 0 - .dw 0xa740, 0xc98e, 0xa77f, 0xc98e, 0x21, 0 - .dw 0xa7c0, 0xc98e, 0xa7ff, 0xc98e, 0x21, 0 - .dw 0xa840, 0xc98e, 0xa87f, 0xc98e, 0x21, 0 - .dw 0xa8c0, 0xc98e, 0xa8ff, 0xc98e, 0x21, 0 - .dw 0xa940, 0xc98e, 0xa97f, 0xc98e, 0x21, 0 - .dw 0xa9c0, 0xc98e, 0xa9ff, 0xc98e, 0x21, 0 - .dw 0xaa40, 0xc98e, 0xaa7f, 0xc98e, 0x21, 0 - .dw 0xaac0, 0xc98e, 0xaaff, 0xc98e, 0x21, 0 - .dw 0xab40, 0xc98e, 0xab7f, 0xc98e, 0x21, 0 - .dw 0xabc0, 0xc98e, 0xabff, 0xc98e, 0x21, 0 - .dw 0xac40, 0xc98e, 0xac7f, 0xc98e, 0x21, 0 - .dw 0xacc0, 0xc98e, 0xacff, 0xc98e, 0x21, 0 - .dw 0xad40, 0xc98e, 0xad7f, 0xc98e, 0x21, 0 - .dw 0xadc0, 0xc98e, 0xadff, 0xc98e, 0x21, 0 - .dw 0xae40, 0xc98e, 0xae7f, 0xc98e, 0x21, 0 - .dw 0xaec0, 0xc98e, 0xaeff, 0xc98e, 0x21, 0 - .dw 0xaf40, 0xc98e, 0xaf7f, 0xc98e, 0x21, 0 - .dw 0xafc0, 0xc98e, 0xafff, 0xc98e, 0x21, 0 - .dw 0xb040, 0xc98e, 0xb07f, 0xc98e, 0x21, 0 - .dw 0xb0c0, 0xc98e, 0xb0ff, 0xc98e, 0x21, 0 - .dw 0xb140, 0xc98e, 0xb17f, 0xc98e, 0x21, 0 - .dw 0xb1c0, 0xc98e, 0xb1ff, 0xc98e, 0x21, 0 - .dw 0xb240, 0xc98e, 0xb27f, 0xc98e, 0x21, 0 - .dw 0xb2c0, 0xc98e, 0xb2ff, 0xc98e, 0x21, 0 - .dw 0xb340, 0xc98e, 0xb37f, 0xc98e, 0x21, 0 - .dw 0xb3c0, 0xc98e, 0xb3ff, 0xc98e, 0x21, 0 - .dw 0xb440, 0xc98e, 0xb47f, 0xc98e, 0x21, 0 - .dw 0xb4c0, 0xc98e, 0xb4ff, 0xc98e, 0x21, 0 - .dw 0xb540, 0xc98e, 0xb57f, 0xc98e, 0x21, 0 - .dw 0xb5c0, 0xc98e, 0xb5ff, 0xc98e, 0x21, 0 - .dw 0xb640, 0xc98e, 0xb67f, 0xc98e, 0x21, 0 - .dw 0xb6c0, 0xc98e, 0xb6ff, 0xc98e, 0x21, 0 - .dw 0xb740, 0xc98e, 0xb77f, 0xc98e, 0x21, 0 - .dw 0xb7c0, 0xc98e, 0xb7ff, 0xc98e, 0x21, 0 - .dw 0xb840, 0xc98e, 0xb87f, 0xc98e, 0x21, 0 - .dw 0xb8c0, 0xc98e, 0xb8ff, 0xc98e, 0x21, 0 - .dw 0xb940, 0xc98e, 0xb97f, 0xc98e, 0x21, 0 - .dw 0xb9c0, 0xc98e, 0xbfff, 0xc98e, 0x21, 0 - .dw 0xc040, 0xc98e, 0xc07f, 0xc98e, 0x21, 0 - .dw 0xc0c0, 0xc98e, 0xc0ff, 0xc98e, 0x21, 0 - .dw 0xc140, 0xc98e, 0xc17f, 0xc98e, 0x21, 0 - .dw 0xc1c0, 0xc98e, 0xc1ff, 0xc98e, 0x21, 0 - .dw 0xc240, 0xc98e, 0xc27f, 0xc98e, 0x21, 0 - .dw 0xc2c0, 0xc98e, 0xc2ff, 0xc98e, 0x21, 0 - .dw 0xc340, 0xc98e, 0xc37f, 0xc98e, 0x21, 0 - .dw 0xc3c0, 0xc98e, 0xc3ff, 0xc98e, 0x21, 0 - .dw 0xc440, 0xc98e, 0xc47f, 0xc98e, 0x21, 0 - .dw 0xc4c0, 0xc98e, 0xc4ff, 0xc98e, 0x21, 0 - .dw 0xc540, 0xc98e, 0xc57f, 0xc98e, 0x21, 0 - .dw 0xc5c0, 0xc98e, 0xc5ff, 0xc98e, 0x21, 0 - .dw 0xc640, 0xc98e, 0xc67f, 0xc98e, 0x21, 0 - .dw 0xc6c0, 0xc98e, 0xc6ff, 0xc98e, 0x21, 0 - .dw 0xc740, 0xc98e, 0xc77f, 0xc98e, 0x21, 0 - .dw 0xc7c0, 0xc98e, 0xc7ff, 0xc98e, 0x21, 0 - .dw 0xc840, 0xc98e, 0xc87f, 0xc98e, 0x21, 0 - .dw 0xc8c0, 0xc98e, 0xc8ff, 0xc98e, 0x21, 0 - .dw 0xc940, 0xc98e, 0xc97f, 0xc98e, 0x21, 0 - .dw 0xc9c0, 0xc98e, 0xc9ff, 0xc98e, 0x21, 0 - .dw 0xca40, 0xc98e, 0xca7f, 0xc98e, 0x21, 0 - .dw 0xcac0, 0xc98e, 0xcaff, 0xc98e, 0x21, 0 - .dw 0xcb40, 0xc98e, 0xcb7f, 0xc98e, 0x21, 0 - .dw 0xcbc0, 0xc98e, 0xcbff, 0xc98e, 0x21, 0 - .dw 0xcc40, 0xc98e, 0xcc7f, 0xc98e, 0x21, 0 - .dw 0xccc0, 0xc98e, 0xccff, 0xc98e, 0x21, 0 - .dw 0xcd40, 0xc98e, 0xcd7f, 0xc98e, 0x21, 0 - .dw 0xcdc0, 0xc98e, 0xcdff, 0xc98e, 0x21, 0 - .dw 0xce40, 0xc98e, 0xce7f, 0xc98e, 0x21, 0 - .dw 0xcec0, 0xc98e, 0xceff, 0xc98e, 0x21, 0 - .dw 0xcf40, 0xc98e, 0xcf7f, 0xc98e, 0x21, 0 - .dw 0xcfc0, 0xc98e, 0xcfff, 0xc98e, 0x21, 0 - .dw 0xd040, 0xc98e, 0xd07f, 0xc98e, 0x21, 0 - .dw 0xd0c0, 0xc98e, 0xd0ff, 0xc98e, 0x21, 0 - .dw 0xd140, 0xc98e, 0xd17f, 0xc98e, 0x21, 0 - .dw 0xd1c0, 0xc98e, 0xd1ff, 0xc98e, 0x21, 0 - .dw 0xd240, 0xc98e, 0xd27f, 0xc98e, 0x21, 0 - .dw 0xd2c0, 0xc98e, 0xd2ff, 0xc98e, 0x21, 0 - .dw 0xd340, 0xc98e, 0xd37f, 0xc98e, 0x21, 0 - .dw 0xd3c0, 0xc98e, 0xd3ff, 0xc98e, 0x21, 0 - .dw 0xd440, 0xc98e, 0xd47f, 0xc98e, 0x21, 0 - .dw 0xd4c0, 0xc98e, 0xd4ff, 0xc98e, 0x21, 0 - .dw 0xd540, 0xc98e, 0xd57f, 0xc98e, 0x21, 0 - .dw 0xd5c0, 0xc98e, 0xd5ff, 0xc98e, 0x21, 0 - .dw 0xd640, 0xc98e, 0xd67f, 0xc98e, 0x21, 0 - .dw 0xd6c0, 0xc98e, 0xd6ff, 0xc98e, 0x21, 0 - .dw 0xd740, 0xc98e, 0xd77f, 0xc98e, 0x21, 0 - .dw 0xd7c0, 0xc98e, 0xd7ff, 0xc98e, 0x21, 0 - .dw 0xd840, 0xc98e, 0xd87f, 0xc98e, 0x21, 0 - .dw 0xd8c0, 0xc98e, 0xd8ff, 0xc98e, 0x21, 0 - .dw 0xd940, 0xc98e, 0xd97f, 0xc98e, 0x21, 0 - .dw 0xd9c0, 0xc98e, 0xdfff, 0xc98e, 0x21, 0 - .dw 0xe040, 0xc98e, 0xe07f, 0xc98e, 0x21, 0 - .dw 0xe0c0, 0xc98e, 0xe0ff, 0xc98e, 0x21, 0 - .dw 0xe140, 0xc98e, 0xe17f, 0xc98e, 0x21, 0 - .dw 0xe1c0, 0xc98e, 0xe1ff, 0xc98e, 0x21, 0 - .dw 0xe240, 0xc98e, 0xe27f, 0xc98e, 0x21, 0 - .dw 0xe2c0, 0xc98e, 0xe2ff, 0xc98e, 0x21, 0 - .dw 0xe340, 0xc98e, 0xe37f, 0xc98e, 0x21, 0 - .dw 0xe3c0, 0xc98e, 0xe3ff, 0xc98e, 0x21, 0 - .dw 0xe440, 0xc98e, 0xe47f, 0xc98e, 0x21, 0 - .dw 0xe4c0, 0xc98e, 0xe4ff, 0xc98e, 0x21, 0 - .dw 0xe540, 0xc98e, 0xe57f, 0xc98e, 0x21, 0 - .dw 0xe5c0, 0xc98e, 0xe5ff, 0xc98e, 0x21, 0 - .dw 0xe640, 0xc98e, 0xe67f, 0xc98e, 0x21, 0 - .dw 0xe6c0, 0xc98e, 0xe6ff, 0xc98e, 0x21, 0 - .dw 0xe740, 0xc98e, 0xe77f, 0xc98e, 0x21, 0 - .dw 0xe7c0, 0xc98e, 0xe7ff, 0xc98e, 0x21, 0 - .dw 0xe840, 0xc98e, 0xe87f, 0xc98e, 0x21, 0 - .dw 0xe8c0, 0xc98e, 0xe8ff, 0xc98e, 0x21, 0 - .dw 0xe940, 0xc98e, 0xe97f, 0xc98e, 0x21, 0 - .dw 0xe9c0, 0xc98e, 0xe9ff, 0xc98e, 0x21, 0 - .dw 0xea40, 0xc98e, 0xea7f, 0xc98e, 0x21, 0 - .dw 0xeac0, 0xc98e, 0xeaff, 0xc98e, 0x21, 0 - .dw 0xeb40, 0xc98e, 0xeb7f, 0xc98e, 0x21, 0 - .dw 0xebc0, 0xc98e, 0xebff, 0xc98e, 0x21, 0 - .dw 0xec40, 0xc98e, 0xec7f, 0xc98e, 0x21, 0 - .dw 0xecc0, 0xc98e, 0xecff, 0xc98e, 0x21, 0 - .dw 0xed40, 0xc98e, 0xed7f, 0xc98e, 0x21, 0 - .dw 0xedc0, 0xc98e, 0xedff, 0xc98e, 0x21, 0 - .dw 0xee40, 0xc98e, 0xee7f, 0xc98e, 0x21, 0 - .dw 0xeec0, 0xc98e, 0xeeff, 0xc98e, 0x21, 0 - .dw 0xef40, 0xc98e, 0xef7f, 0xc98e, 0x21, 0 - .dw 0xefc0, 0xc98e, 0xefff, 0xc98e, 0x21, 0 - .dw 0xf040, 0xc98e, 0xf07f, 0xc98e, 0x21, 0 - .dw 0xf0c0, 0xc98e, 0xf0ff, 0xc98e, 0x21, 0 - .dw 0xf140, 0xc98e, 0xf17f, 0xc98e, 0x21, 0 - .dw 0xf1c0, 0xc98e, 0xf1ff, 0xc98e, 0x21, 0 - .dw 0xf240, 0xc98e, 0xf27f, 0xc98e, 0x21, 0 - .dw 0xf2c0, 0xc98e, 0xf2ff, 0xc98e, 0x21, 0 - .dw 0xf340, 0xc98e, 0xf37f, 0xc98e, 0x21, 0 - .dw 0xf3c0, 0xc98e, 0xf3ff, 0xc98e, 0x21, 0 - .dw 0xf440, 0xc98e, 0xf47f, 0xc98e, 0x21, 0 - .dw 0xf4c0, 0xc98e, 0xf4ff, 0xc98e, 0x21, 0 - .dw 0xf540, 0xc98e, 0xf57f, 0xc98e, 0x21, 0 - .dw 0xf5c0, 0xc98e, 0xf5ff, 0xc98e, 0x21, 0 - .dw 0xf640, 0xc98e, 0xf67f, 0xc98e, 0x21, 0 - .dw 0xf6c0, 0xc98e, 0xf6ff, 0xc98e, 0x21, 0 - .dw 0xf740, 0xc98e, 0xf77f, 0xc98e, 0x21, 0 - .dw 0xf7c0, 0xc98e, 0xf7ff, 0xc98e, 0x21, 0 - .dw 0xf840, 0xc98e, 0xf87f, 0xc98e, 0x21, 0 - .dw 0xf8c0, 0xc98e, 0xf8ff, 0xc98e, 0x21, 0 - .dw 0xf940, 0xc98e, 0xf97f, 0xc98e, 0x21, 0 - .dw 0xf9c0, 0xc98e, 0xffff, 0xc98e, 0x21, 0 - .dw 0x0040, 0xc98f, 0x007f, 0xc98f, 0x21, 0 - .dw 0x00c0, 0xc98f, 0x00ff, 0xc98f, 0x21, 0 - .dw 0x0140, 0xc98f, 0x017f, 0xc98f, 0x21, 0 - .dw 0x01c0, 0xc98f, 0x01ff, 0xc98f, 0x21, 0 - .dw 0x0240, 0xc98f, 0x027f, 0xc98f, 0x21, 0 - .dw 0x02c0, 0xc98f, 0x02ff, 0xc98f, 0x21, 0 - .dw 0x0340, 0xc98f, 0x037f, 0xc98f, 0x21, 0 - .dw 0x03c0, 0xc98f, 0x03ff, 0xc98f, 0x21, 0 - .dw 0x0440, 0xc98f, 0x047f, 0xc98f, 0x21, 0 - .dw 0x04c0, 0xc98f, 0x04ff, 0xc98f, 0x21, 0 - .dw 0x0540, 0xc98f, 0x057f, 0xc98f, 0x21, 0 - .dw 0x05c0, 0xc98f, 0x05ff, 0xc98f, 0x21, 0 - .dw 0x0640, 0xc98f, 0x067f, 0xc98f, 0x21, 0 - .dw 0x06c0, 0xc98f, 0x06ff, 0xc98f, 0x21, 0 - .dw 0x0740, 0xc98f, 0x077f, 0xc98f, 0x21, 0 - .dw 0x07c0, 0xc98f, 0x07ff, 0xc98f, 0x21, 0 - .dw 0x0840, 0xc98f, 0x087f, 0xc98f, 0x21, 0 - .dw 0x08c0, 0xc98f, 0x08ff, 0xc98f, 0x21, 0 - .dw 0x0940, 0xc98f, 0x097f, 0xc98f, 0x21, 0 - .dw 0x09c0, 0xc98f, 0x09ff, 0xc98f, 0x21, 0 - .dw 0x0a40, 0xc98f, 0x0a7f, 0xc98f, 0x21, 0 - .dw 0x0ac0, 0xc98f, 0x0aff, 0xc98f, 0x21, 0 - .dw 0x0b40, 0xc98f, 0x0b7f, 0xc98f, 0x21, 0 - .dw 0x0bc0, 0xc98f, 0x0bff, 0xc98f, 0x21, 0 - .dw 0x0c40, 0xc98f, 0x0c7f, 0xc98f, 0x21, 0 - .dw 0x0cc0, 0xc98f, 0x0cff, 0xc98f, 0x21, 0 - .dw 0x0d40, 0xc98f, 0x0d7f, 0xc98f, 0x21, 0 - .dw 0x0dc0, 0xc98f, 0x0dff, 0xc98f, 0x21, 0 - .dw 0x0e40, 0xc98f, 0x0e7f, 0xc98f, 0x21, 0 - .dw 0x0ec0, 0xc98f, 0x0eff, 0xc98f, 0x21, 0 - .dw 0x0f40, 0xc98f, 0x0f7f, 0xc98f, 0x21, 0 - .dw 0x0fc0, 0xc98f, 0x0fff, 0xc98f, 0x21, 0 - .dw 0x1040, 0xc98f, 0x107f, 0xc98f, 0x21, 0 - .dw 0x10c0, 0xc98f, 0x10ff, 0xc98f, 0x21, 0 - .dw 0x1140, 0xc98f, 0x117f, 0xc98f, 0x21, 0 - .dw 0x11c0, 0xc98f, 0x11ff, 0xc98f, 0x21, 0 - .dw 0x1240, 0xc98f, 0x127f, 0xc98f, 0x21, 0 - .dw 0x12c0, 0xc98f, 0x12ff, 0xc98f, 0x21, 0 - .dw 0x1340, 0xc98f, 0x137f, 0xc98f, 0x21, 0 - .dw 0x13c0, 0xc98f, 0x13ff, 0xc98f, 0x21, 0 - .dw 0x1440, 0xc98f, 0x147f, 0xc98f, 0x21, 0 - .dw 0x14c0, 0xc98f, 0x14ff, 0xc98f, 0x21, 0 - .dw 0x1540, 0xc98f, 0x157f, 0xc98f, 0x21, 0 - .dw 0x15c0, 0xc98f, 0x15ff, 0xc98f, 0x21, 0 - .dw 0x1640, 0xc98f, 0x167f, 0xc98f, 0x21, 0 - .dw 0x16c0, 0xc98f, 0x16ff, 0xc98f, 0x21, 0 - .dw 0x1740, 0xc98f, 0x177f, 0xc98f, 0x21, 0 - .dw 0x17c0, 0xc98f, 0x17ff, 0xc98f, 0x21, 0 - .dw 0x1840, 0xc98f, 0x187f, 0xc98f, 0x21, 0 - .dw 0x18c0, 0xc98f, 0x18ff, 0xc98f, 0x21, 0 - .dw 0x1940, 0xc98f, 0x197f, 0xc98f, 0x21, 0 - .dw 0x19c0, 0xc98f, 0x1fff, 0xc98f, 0x21, 0 - .dw 0x2040, 0xc98f, 0x207f, 0xc98f, 0x21, 0 - .dw 0x20c0, 0xc98f, 0x20ff, 0xc98f, 0x21, 0 - .dw 0x2140, 0xc98f, 0x217f, 0xc98f, 0x21, 0 - .dw 0x21c0, 0xc98f, 0x21ff, 0xc98f, 0x21, 0 - .dw 0x2240, 0xc98f, 0x227f, 0xc98f, 0x21, 0 - .dw 0x22c0, 0xc98f, 0x22ff, 0xc98f, 0x21, 0 - .dw 0x2340, 0xc98f, 0x237f, 0xc98f, 0x21, 0 - .dw 0x23c0, 0xc98f, 0x23ff, 0xc98f, 0x21, 0 - .dw 0x2440, 0xc98f, 0x247f, 0xc98f, 0x21, 0 - .dw 0x24c0, 0xc98f, 0x24ff, 0xc98f, 0x21, 0 - .dw 0x2540, 0xc98f, 0x257f, 0xc98f, 0x21, 0 - .dw 0x25c0, 0xc98f, 0x25ff, 0xc98f, 0x21, 0 - .dw 0x2640, 0xc98f, 0x267f, 0xc98f, 0x21, 0 - .dw 0x26c0, 0xc98f, 0x26ff, 0xc98f, 0x21, 0 - .dw 0x2740, 0xc98f, 0x277f, 0xc98f, 0x21, 0 - .dw 0x27c0, 0xc98f, 0x27ff, 0xc98f, 0x21, 0 - .dw 0x2840, 0xc98f, 0x287f, 0xc98f, 0x21, 0 - .dw 0x28c0, 0xc98f, 0x28ff, 0xc98f, 0x21, 0 - .dw 0x2940, 0xc98f, 0x297f, 0xc98f, 0x21, 0 - .dw 0x29c0, 0xc98f, 0x29ff, 0xc98f, 0x21, 0 - .dw 0x2a40, 0xc98f, 0x2a7f, 0xc98f, 0x21, 0 - .dw 0x2ac0, 0xc98f, 0x2aff, 0xc98f, 0x21, 0 - .dw 0x2b40, 0xc98f, 0x2b7f, 0xc98f, 0x21, 0 - .dw 0x2bc0, 0xc98f, 0x2bff, 0xc98f, 0x21, 0 - .dw 0x2c40, 0xc98f, 0x2c7f, 0xc98f, 0x21, 0 - .dw 0x2cc0, 0xc98f, 0x2cff, 0xc98f, 0x21, 0 - .dw 0x2d40, 0xc98f, 0x2d7f, 0xc98f, 0x21, 0 - .dw 0x2dc0, 0xc98f, 0x2dff, 0xc98f, 0x21, 0 - .dw 0x2e40, 0xc98f, 0x2e7f, 0xc98f, 0x21, 0 - .dw 0x2ec0, 0xc98f, 0x2eff, 0xc98f, 0x21, 0 - .dw 0x2f40, 0xc98f, 0x2f7f, 0xc98f, 0x21, 0 - .dw 0x2fc0, 0xc98f, 0x2fff, 0xc98f, 0x21, 0 - .dw 0x3040, 0xc98f, 0x307f, 0xc98f, 0x21, 0 - .dw 0x30c0, 0xc98f, 0x30ff, 0xc98f, 0x21, 0 - .dw 0x3140, 0xc98f, 0x317f, 0xc98f, 0x21, 0 - .dw 0x31c0, 0xc98f, 0x31ff, 0xc98f, 0x21, 0 - .dw 0x3240, 0xc98f, 0x327f, 0xc98f, 0x21, 0 - .dw 0x32c0, 0xc98f, 0x32ff, 0xc98f, 0x21, 0 - .dw 0x3340, 0xc98f, 0x337f, 0xc98f, 0x21, 0 - .dw 0x33c0, 0xc98f, 0x33ff, 0xc98f, 0x21, 0 - .dw 0x3440, 0xc98f, 0x347f, 0xc98f, 0x21, 0 - .dw 0x34c0, 0xc98f, 0x34ff, 0xc98f, 0x21, 0 - .dw 0x3540, 0xc98f, 0x357f, 0xc98f, 0x21, 0 - .dw 0x35c0, 0xc98f, 0x35ff, 0xc98f, 0x21, 0 - .dw 0x3640, 0xc98f, 0x367f, 0xc98f, 0x21, 0 - .dw 0x36c0, 0xc98f, 0x36ff, 0xc98f, 0x21, 0 - .dw 0x3740, 0xc98f, 0x377f, 0xc98f, 0x21, 0 - .dw 0x37c0, 0xc98f, 0x37ff, 0xc98f, 0x21, 0 - .dw 0x3840, 0xc98f, 0x387f, 0xc98f, 0x21, 0 - .dw 0x38c0, 0xc98f, 0x38ff, 0xc98f, 0x21, 0 - .dw 0x3940, 0xc98f, 0x397f, 0xc98f, 0x21, 0 - .dw 0x39c0, 0xc98f, 0x1fff, 0xc990, 0x21, 0 - .dw 0x3a00, 0xc990, 0x5fff, 0xc990, 0x21, 0 - .dw 0x7a00, 0xc990, 0x9fff, 0xc990, 0x21, 0 - .dw 0xba00, 0xc990, 0xdfff, 0xc990, 0x21, 0 - .dw 0xfa00, 0xc990, 0x1fff, 0xc991, 0x21, 0 - .dw 0x3a00, 0xc991, 0x5fff, 0xc991, 0x21, 0 - .dw 0x7a00, 0xc991, 0x9fff, 0xc991, 0x21, 0 - .dw 0xba00, 0xc991, 0xdfff, 0xc991, 0x21, 0 - .dw 0xfa00, 0xc991, 0x1fff, 0xc992, 0x21, 0 - .dw 0x3a00, 0xc992, 0x5fff, 0xc992, 0x21, 0 - .dw 0x7a00, 0xc992, 0x9fff, 0xc992, 0x21, 0 - .dw 0xba00, 0xc992, 0xdfff, 0xc992, 0x21, 0 - .dw 0xfa00, 0xc992, 0xffff, 0xc993, 0x21, 0 - .dw 0x1a00, 0xc994, 0x1fff, 0xc994, 0x21, 0 - .dw 0x3a00, 0xc994, 0x3fff, 0xc994, 0x21, 0 - .dw 0x5a00, 0xc994, 0x5fff, 0xc994, 0x21, 0 - .dw 0x7a00, 0xc994, 0x7fff, 0xc994, 0x21, 0 - .dw 0x9a00, 0xc994, 0x9fff, 0xc994, 0x21, 0 - .dw 0xba00, 0xc994, 0xbfff, 0xc994, 0x21, 0 - .dw 0xda00, 0xc994, 0xdfff, 0xc994, 0x21, 0 - .dw 0xfa00, 0xc994, 0xffff, 0xc994, 0x21, 0 - .dw 0x1a00, 0xc995, 0x1fff, 0xc995, 0x21, 0 - .dw 0x3a00, 0xc995, 0x3fff, 0xc995, 0x21, 0 - .dw 0x5a00, 0xc995, 0x5fff, 0xc995, 0x21, 0 - .dw 0x7a00, 0xc995, 0x7fff, 0xc995, 0x21, 0 - .dw 0x9a00, 0xc995, 0x9fff, 0xc995, 0x21, 0 - .dw 0xba00, 0xc995, 0xbfff, 0xc995, 0x21, 0 - .dw 0xda00, 0xc995, 0xdfff, 0xc995, 0x21, 0 - .dw 0xfa00, 0xc995, 0xffff, 0xc995, 0x21, 0 - .dw 0x1a00, 0xc996, 0x1fff, 0xc996, 0x21, 0 - .dw 0x3a00, 0xc996, 0x3fff, 0xc996, 0x21, 0 - .dw 0x5a00, 0xc996, 0x5fff, 0xc996, 0x21, 0 - .dw 0x7a00, 0xc996, 0x7fff, 0xc996, 0x21, 0 - .dw 0x9a00, 0xc996, 0x9fff, 0xc996, 0x21, 0 - .dw 0xba00, 0xc996, 0xbfff, 0xc996, 0x21, 0 - .dw 0xda00, 0xc996, 0xdfff, 0xc996, 0x21, 0 - .dw 0xfa00, 0xc996, 0xffff, 0xc996, 0x21, 0 - .dw 0x1a00, 0xc997, 0x1fff, 0xc997, 0x21, 0 - .dw 0x3a00, 0xc997, 0x1fff, 0xc998, 0x21, 0 - .dw 0x2040, 0xc998, 0x207f, 0xc998, 0x21, 0 - .dw 0x20c0, 0xc998, 0x20ff, 0xc998, 0x21, 0 - .dw 0x2140, 0xc998, 0x217f, 0xc998, 0x21, 0 - .dw 0x21c0, 0xc998, 0x21ff, 0xc998, 0x21, 0 - .dw 0x2240, 0xc998, 0x227f, 0xc998, 0x21, 0 - .dw 0x22c0, 0xc998, 0x22ff, 0xc998, 0x21, 0 - .dw 0x2340, 0xc998, 0x237f, 0xc998, 0x21, 0 - .dw 0x23c0, 0xc998, 0x23ff, 0xc998, 0x21, 0 - .dw 0x2440, 0xc998, 0x247f, 0xc998, 0x21, 0 - .dw 0x24c0, 0xc998, 0x24ff, 0xc998, 0x21, 0 - .dw 0x2540, 0xc998, 0x257f, 0xc998, 0x21, 0 - .dw 0x25c0, 0xc998, 0x25ff, 0xc998, 0x21, 0 - .dw 0x2640, 0xc998, 0x267f, 0xc998, 0x21, 0 - .dw 0x26c0, 0xc998, 0x26ff, 0xc998, 0x21, 0 - .dw 0x2740, 0xc998, 0x277f, 0xc998, 0x21, 0 - .dw 0x27c0, 0xc998, 0x27ff, 0xc998, 0x21, 0 - .dw 0x2840, 0xc998, 0x287f, 0xc998, 0x21, 0 - .dw 0x28c0, 0xc998, 0x28ff, 0xc998, 0x21, 0 - .dw 0x2940, 0xc998, 0x297f, 0xc998, 0x21, 0 - .dw 0x29c0, 0xc998, 0x29ff, 0xc998, 0x21, 0 - .dw 0x2a40, 0xc998, 0x2a7f, 0xc998, 0x21, 0 - .dw 0x2ac0, 0xc998, 0x2aff, 0xc998, 0x21, 0 - .dw 0x2b40, 0xc998, 0x2b7f, 0xc998, 0x21, 0 - .dw 0x2bc0, 0xc998, 0x2bff, 0xc998, 0x21, 0 - .dw 0x2c40, 0xc998, 0x2c7f, 0xc998, 0x21, 0 - .dw 0x2cc0, 0xc998, 0x2cff, 0xc998, 0x21, 0 - .dw 0x2d40, 0xc998, 0x2d7f, 0xc998, 0x21, 0 - .dw 0x2dc0, 0xc998, 0x2dff, 0xc998, 0x21, 0 - .dw 0x2e40, 0xc998, 0x2e7f, 0xc998, 0x21, 0 - .dw 0x2ec0, 0xc998, 0x2eff, 0xc998, 0x21, 0 - .dw 0x2f40, 0xc998, 0x2f7f, 0xc998, 0x21, 0 - .dw 0x2fc0, 0xc998, 0x2fff, 0xc998, 0x21, 0 - .dw 0x3040, 0xc998, 0x307f, 0xc998, 0x21, 0 - .dw 0x30c0, 0xc998, 0x30ff, 0xc998, 0x21, 0 - .dw 0x3140, 0xc998, 0x317f, 0xc998, 0x21, 0 - .dw 0x31c0, 0xc998, 0x31ff, 0xc998, 0x21, 0 - .dw 0x3240, 0xc998, 0x327f, 0xc998, 0x21, 0 - .dw 0x32c0, 0xc998, 0x32ff, 0xc998, 0x21, 0 - .dw 0x3340, 0xc998, 0x337f, 0xc998, 0x21, 0 - .dw 0x33c0, 0xc998, 0x33ff, 0xc998, 0x21, 0 - .dw 0x3440, 0xc998, 0x347f, 0xc998, 0x21, 0 - .dw 0x34c0, 0xc998, 0x34ff, 0xc998, 0x21, 0 - .dw 0x3540, 0xc998, 0x357f, 0xc998, 0x21, 0 - .dw 0x35c0, 0xc998, 0x35ff, 0xc998, 0x21, 0 - .dw 0x3640, 0xc998, 0x367f, 0xc998, 0x21, 0 - .dw 0x36c0, 0xc998, 0x36ff, 0xc998, 0x21, 0 - .dw 0x3740, 0xc998, 0x377f, 0xc998, 0x21, 0 - .dw 0x37c0, 0xc998, 0x37ff, 0xc998, 0x21, 0 - .dw 0x3840, 0xc998, 0x387f, 0xc998, 0x21, 0 - .dw 0x38c0, 0xc998, 0x38ff, 0xc998, 0x21, 0 - .dw 0x3940, 0xc998, 0x397f, 0xc998, 0x21, 0 - .dw 0x39c0, 0xc998, 0x5fff, 0xc998, 0x21, 0 - .dw 0x6040, 0xc998, 0x607f, 0xc998, 0x21, 0 - .dw 0x60c0, 0xc998, 0x60ff, 0xc998, 0x21, 0 - .dw 0x6140, 0xc998, 0x617f, 0xc998, 0x21, 0 - .dw 0x61c0, 0xc998, 0x61ff, 0xc998, 0x21, 0 - .dw 0x6240, 0xc998, 0x627f, 0xc998, 0x21, 0 - .dw 0x62c0, 0xc998, 0x62ff, 0xc998, 0x21, 0 - .dw 0x6340, 0xc998, 0x637f, 0xc998, 0x21, 0 - .dw 0x63c0, 0xc998, 0x63ff, 0xc998, 0x21, 0 - .dw 0x6440, 0xc998, 0x647f, 0xc998, 0x21, 0 - .dw 0x64c0, 0xc998, 0x64ff, 0xc998, 0x21, 0 - .dw 0x6540, 0xc998, 0x657f, 0xc998, 0x21, 0 - .dw 0x65c0, 0xc998, 0x65ff, 0xc998, 0x21, 0 - .dw 0x6640, 0xc998, 0x667f, 0xc998, 0x21, 0 - .dw 0x66c0, 0xc998, 0x66ff, 0xc998, 0x21, 0 - .dw 0x6740, 0xc998, 0x677f, 0xc998, 0x21, 0 - .dw 0x67c0, 0xc998, 0x67ff, 0xc998, 0x21, 0 - .dw 0x6840, 0xc998, 0x687f, 0xc998, 0x21, 0 - .dw 0x68c0, 0xc998, 0x68ff, 0xc998, 0x21, 0 - .dw 0x6940, 0xc998, 0x697f, 0xc998, 0x21, 0 - .dw 0x69c0, 0xc998, 0x69ff, 0xc998, 0x21, 0 - .dw 0x6a40, 0xc998, 0x6a7f, 0xc998, 0x21, 0 - .dw 0x6ac0, 0xc998, 0x6aff, 0xc998, 0x21, 0 - .dw 0x6b40, 0xc998, 0x6b7f, 0xc998, 0x21, 0 - .dw 0x6bc0, 0xc998, 0x6bff, 0xc998, 0x21, 0 - .dw 0x6c40, 0xc998, 0x6c7f, 0xc998, 0x21, 0 - .dw 0x6cc0, 0xc998, 0x6cff, 0xc998, 0x21, 0 - .dw 0x6d40, 0xc998, 0x6d7f, 0xc998, 0x21, 0 - .dw 0x6dc0, 0xc998, 0x6dff, 0xc998, 0x21, 0 - .dw 0x6e40, 0xc998, 0x6e7f, 0xc998, 0x21, 0 - .dw 0x6ec0, 0xc998, 0x6eff, 0xc998, 0x21, 0 - .dw 0x6f40, 0xc998, 0x6f7f, 0xc998, 0x21, 0 - .dw 0x6fc0, 0xc998, 0x6fff, 0xc998, 0x21, 0 - .dw 0x7040, 0xc998, 0x707f, 0xc998, 0x21, 0 - .dw 0x70c0, 0xc998, 0x70ff, 0xc998, 0x21, 0 - .dw 0x7140, 0xc998, 0x717f, 0xc998, 0x21, 0 - .dw 0x71c0, 0xc998, 0x71ff, 0xc998, 0x21, 0 - .dw 0x7240, 0xc998, 0x727f, 0xc998, 0x21, 0 - .dw 0x72c0, 0xc998, 0x72ff, 0xc998, 0x21, 0 - .dw 0x7340, 0xc998, 0x737f, 0xc998, 0x21, 0 - .dw 0x73c0, 0xc998, 0x73ff, 0xc998, 0x21, 0 - .dw 0x7440, 0xc998, 0x747f, 0xc998, 0x21, 0 - .dw 0x74c0, 0xc998, 0x74ff, 0xc998, 0x21, 0 - .dw 0x7540, 0xc998, 0x757f, 0xc998, 0x21, 0 - .dw 0x75c0, 0xc998, 0x75ff, 0xc998, 0x21, 0 - .dw 0x7640, 0xc998, 0x767f, 0xc998, 0x21, 0 - .dw 0x76c0, 0xc998, 0x76ff, 0xc998, 0x21, 0 - .dw 0x7740, 0xc998, 0x777f, 0xc998, 0x21, 0 - .dw 0x77c0, 0xc998, 0x77ff, 0xc998, 0x21, 0 - .dw 0x7840, 0xc998, 0x787f, 0xc998, 0x21, 0 - .dw 0x78c0, 0xc998, 0x78ff, 0xc998, 0x21, 0 - .dw 0x7940, 0xc998, 0x797f, 0xc998, 0x21, 0 - .dw 0x79c0, 0xc998, 0x9fff, 0xc998, 0x21, 0 - .dw 0xa040, 0xc998, 0xa07f, 0xc998, 0x21, 0 - .dw 0xa0c0, 0xc998, 0xa0ff, 0xc998, 0x21, 0 - .dw 0xa140, 0xc998, 0xa17f, 0xc998, 0x21, 0 - .dw 0xa1c0, 0xc998, 0xa1ff, 0xc998, 0x21, 0 - .dw 0xa240, 0xc998, 0xa27f, 0xc998, 0x21, 0 - .dw 0xa2c0, 0xc998, 0xa2ff, 0xc998, 0x21, 0 - .dw 0xa340, 0xc998, 0xa37f, 0xc998, 0x21, 0 - .dw 0xa3c0, 0xc998, 0xa3ff, 0xc998, 0x21, 0 - .dw 0xa440, 0xc998, 0xa47f, 0xc998, 0x21, 0 - .dw 0xa4c0, 0xc998, 0xa4ff, 0xc998, 0x21, 0 - .dw 0xa540, 0xc998, 0xa57f, 0xc998, 0x21, 0 - .dw 0xa5c0, 0xc998, 0xa5ff, 0xc998, 0x21, 0 - .dw 0xa640, 0xc998, 0xa67f, 0xc998, 0x21, 0 - .dw 0xa6c0, 0xc998, 0xa6ff, 0xc998, 0x21, 0 - .dw 0xa740, 0xc998, 0xa77f, 0xc998, 0x21, 0 - .dw 0xa7c0, 0xc998, 0xa7ff, 0xc998, 0x21, 0 - .dw 0xa840, 0xc998, 0xa87f, 0xc998, 0x21, 0 - .dw 0xa8c0, 0xc998, 0xa8ff, 0xc998, 0x21, 0 - .dw 0xa940, 0xc998, 0xa97f, 0xc998, 0x21, 0 - .dw 0xa9c0, 0xc998, 0xa9ff, 0xc998, 0x21, 0 - .dw 0xaa40, 0xc998, 0xaa7f, 0xc998, 0x21, 0 - .dw 0xaac0, 0xc998, 0xaaff, 0xc998, 0x21, 0 - .dw 0xab40, 0xc998, 0xab7f, 0xc998, 0x21, 0 - .dw 0xabc0, 0xc998, 0xabff, 0xc998, 0x21, 0 - .dw 0xac40, 0xc998, 0xac7f, 0xc998, 0x21, 0 - .dw 0xacc0, 0xc998, 0xacff, 0xc998, 0x21, 0 - .dw 0xad40, 0xc998, 0xad7f, 0xc998, 0x21, 0 - .dw 0xadc0, 0xc998, 0xadff, 0xc998, 0x21, 0 - .dw 0xae40, 0xc998, 0xae7f, 0xc998, 0x21, 0 - .dw 0xaec0, 0xc998, 0xaeff, 0xc998, 0x21, 0 - .dw 0xaf40, 0xc998, 0xaf7f, 0xc998, 0x21, 0 - .dw 0xafc0, 0xc998, 0xafff, 0xc998, 0x21, 0 - .dw 0xb040, 0xc998, 0xb07f, 0xc998, 0x21, 0 - .dw 0xb0c0, 0xc998, 0xb0ff, 0xc998, 0x21, 0 - .dw 0xb140, 0xc998, 0xb17f, 0xc998, 0x21, 0 - .dw 0xb1c0, 0xc998, 0xb1ff, 0xc998, 0x21, 0 - .dw 0xb240, 0xc998, 0xb27f, 0xc998, 0x21, 0 - .dw 0xb2c0, 0xc998, 0xb2ff, 0xc998, 0x21, 0 - .dw 0xb340, 0xc998, 0xb37f, 0xc998, 0x21, 0 - .dw 0xb3c0, 0xc998, 0xb3ff, 0xc998, 0x21, 0 - .dw 0xb440, 0xc998, 0xb47f, 0xc998, 0x21, 0 - .dw 0xb4c0, 0xc998, 0xb4ff, 0xc998, 0x21, 0 - .dw 0xb540, 0xc998, 0xb57f, 0xc998, 0x21, 0 - .dw 0xb5c0, 0xc998, 0xb5ff, 0xc998, 0x21, 0 - .dw 0xb640, 0xc998, 0xb67f, 0xc998, 0x21, 0 - .dw 0xb6c0, 0xc998, 0xb6ff, 0xc998, 0x21, 0 - .dw 0xb740, 0xc998, 0xb77f, 0xc998, 0x21, 0 - .dw 0xb7c0, 0xc998, 0xb7ff, 0xc998, 0x21, 0 - .dw 0xb840, 0xc998, 0xb87f, 0xc998, 0x21, 0 - .dw 0xb8c0, 0xc998, 0xb8ff, 0xc998, 0x21, 0 - .dw 0xb940, 0xc998, 0xb97f, 0xc998, 0x21, 0 - .dw 0xb9c0, 0xc998, 0xdfff, 0xc998, 0x21, 0 - .dw 0xe040, 0xc998, 0xe07f, 0xc998, 0x21, 0 - .dw 0xe0c0, 0xc998, 0xe0ff, 0xc998, 0x21, 0 - .dw 0xe140, 0xc998, 0xe17f, 0xc998, 0x21, 0 - .dw 0xe1c0, 0xc998, 0xe1ff, 0xc998, 0x21, 0 - .dw 0xe240, 0xc998, 0xe27f, 0xc998, 0x21, 0 - .dw 0xe2c0, 0xc998, 0xe2ff, 0xc998, 0x21, 0 - .dw 0xe340, 0xc998, 0xe37f, 0xc998, 0x21, 0 - .dw 0xe3c0, 0xc998, 0xe3ff, 0xc998, 0x21, 0 - .dw 0xe440, 0xc998, 0xe47f, 0xc998, 0x21, 0 - .dw 0xe4c0, 0xc998, 0xe4ff, 0xc998, 0x21, 0 - .dw 0xe540, 0xc998, 0xe57f, 0xc998, 0x21, 0 - .dw 0xe5c0, 0xc998, 0xe5ff, 0xc998, 0x21, 0 - .dw 0xe640, 0xc998, 0xe67f, 0xc998, 0x21, 0 - .dw 0xe6c0, 0xc998, 0xe6ff, 0xc998, 0x21, 0 - .dw 0xe740, 0xc998, 0xe77f, 0xc998, 0x21, 0 - .dw 0xe7c0, 0xc998, 0xe7ff, 0xc998, 0x21, 0 - .dw 0xe840, 0xc998, 0xe87f, 0xc998, 0x21, 0 - .dw 0xe8c0, 0xc998, 0xe8ff, 0xc998, 0x21, 0 - .dw 0xe940, 0xc998, 0xe97f, 0xc998, 0x21, 0 - .dw 0xe9c0, 0xc998, 0xe9ff, 0xc998, 0x21, 0 - .dw 0xea40, 0xc998, 0xea7f, 0xc998, 0x21, 0 - .dw 0xeac0, 0xc998, 0xeaff, 0xc998, 0x21, 0 - .dw 0xeb40, 0xc998, 0xeb7f, 0xc998, 0x21, 0 - .dw 0xebc0, 0xc998, 0xebff, 0xc998, 0x21, 0 - .dw 0xec40, 0xc998, 0xec7f, 0xc998, 0x21, 0 - .dw 0xecc0, 0xc998, 0xecff, 0xc998, 0x21, 0 - .dw 0xed40, 0xc998, 0xed7f, 0xc998, 0x21, 0 - .dw 0xedc0, 0xc998, 0xedff, 0xc998, 0x21, 0 - .dw 0xee40, 0xc998, 0xee7f, 0xc998, 0x21, 0 - .dw 0xeec0, 0xc998, 0xeeff, 0xc998, 0x21, 0 - .dw 0xef40, 0xc998, 0xef7f, 0xc998, 0x21, 0 - .dw 0xefc0, 0xc998, 0xefff, 0xc998, 0x21, 0 - .dw 0xf040, 0xc998, 0xf07f, 0xc998, 0x21, 0 - .dw 0xf0c0, 0xc998, 0xf0ff, 0xc998, 0x21, 0 - .dw 0xf140, 0xc998, 0xf17f, 0xc998, 0x21, 0 - .dw 0xf1c0, 0xc998, 0xf1ff, 0xc998, 0x21, 0 - .dw 0xf240, 0xc998, 0xf27f, 0xc998, 0x21, 0 - .dw 0xf2c0, 0xc998, 0xf2ff, 0xc998, 0x21, 0 - .dw 0xf340, 0xc998, 0xf37f, 0xc998, 0x21, 0 - .dw 0xf3c0, 0xc998, 0xf3ff, 0xc998, 0x21, 0 - .dw 0xf440, 0xc998, 0xf47f, 0xc998, 0x21, 0 - .dw 0xf4c0, 0xc998, 0xf4ff, 0xc998, 0x21, 0 - .dw 0xf540, 0xc998, 0xf57f, 0xc998, 0x21, 0 - .dw 0xf5c0, 0xc998, 0xf5ff, 0xc998, 0x21, 0 - .dw 0xf640, 0xc998, 0xf67f, 0xc998, 0x21, 0 - .dw 0xf6c0, 0xc998, 0xf6ff, 0xc998, 0x21, 0 - .dw 0xf740, 0xc998, 0xf77f, 0xc998, 0x21, 0 - .dw 0xf7c0, 0xc998, 0xf7ff, 0xc998, 0x21, 0 - .dw 0xf840, 0xc998, 0xf87f, 0xc998, 0x21, 0 - .dw 0xf8c0, 0xc998, 0xf8ff, 0xc998, 0x21, 0 - .dw 0xf940, 0xc998, 0xf97f, 0xc998, 0x21, 0 - .dw 0xf9c0, 0xc998, 0x1fff, 0xc999, 0x21, 0 - .dw 0x2040, 0xc999, 0x207f, 0xc999, 0x21, 0 - .dw 0x20c0, 0xc999, 0x20ff, 0xc999, 0x21, 0 - .dw 0x2140, 0xc999, 0x217f, 0xc999, 0x21, 0 - .dw 0x21c0, 0xc999, 0x21ff, 0xc999, 0x21, 0 - .dw 0x2240, 0xc999, 0x227f, 0xc999, 0x21, 0 - .dw 0x22c0, 0xc999, 0x22ff, 0xc999, 0x21, 0 - .dw 0x2340, 0xc999, 0x237f, 0xc999, 0x21, 0 - .dw 0x23c0, 0xc999, 0x23ff, 0xc999, 0x21, 0 - .dw 0x2440, 0xc999, 0x247f, 0xc999, 0x21, 0 - .dw 0x24c0, 0xc999, 0x24ff, 0xc999, 0x21, 0 - .dw 0x2540, 0xc999, 0x257f, 0xc999, 0x21, 0 - .dw 0x25c0, 0xc999, 0x25ff, 0xc999, 0x21, 0 - .dw 0x2640, 0xc999, 0x267f, 0xc999, 0x21, 0 - .dw 0x26c0, 0xc999, 0x26ff, 0xc999, 0x21, 0 - .dw 0x2740, 0xc999, 0x277f, 0xc999, 0x21, 0 - .dw 0x27c0, 0xc999, 0x27ff, 0xc999, 0x21, 0 - .dw 0x2840, 0xc999, 0x287f, 0xc999, 0x21, 0 - .dw 0x28c0, 0xc999, 0x28ff, 0xc999, 0x21, 0 - .dw 0x2940, 0xc999, 0x297f, 0xc999, 0x21, 0 - .dw 0x29c0, 0xc999, 0x29ff, 0xc999, 0x21, 0 - .dw 0x2a40, 0xc999, 0x2a7f, 0xc999, 0x21, 0 - .dw 0x2ac0, 0xc999, 0x2aff, 0xc999, 0x21, 0 - .dw 0x2b40, 0xc999, 0x2b7f, 0xc999, 0x21, 0 - .dw 0x2bc0, 0xc999, 0x2bff, 0xc999, 0x21, 0 - .dw 0x2c40, 0xc999, 0x2c7f, 0xc999, 0x21, 0 - .dw 0x2cc0, 0xc999, 0x2cff, 0xc999, 0x21, 0 - .dw 0x2d40, 0xc999, 0x2d7f, 0xc999, 0x21, 0 - .dw 0x2dc0, 0xc999, 0x2dff, 0xc999, 0x21, 0 - .dw 0x2e40, 0xc999, 0x2e7f, 0xc999, 0x21, 0 - .dw 0x2ec0, 0xc999, 0x2eff, 0xc999, 0x21, 0 - .dw 0x2f40, 0xc999, 0x2f7f, 0xc999, 0x21, 0 - .dw 0x2fc0, 0xc999, 0x2fff, 0xc999, 0x21, 0 - .dw 0x3040, 0xc999, 0x307f, 0xc999, 0x21, 0 - .dw 0x30c0, 0xc999, 0x30ff, 0xc999, 0x21, 0 - .dw 0x3140, 0xc999, 0x317f, 0xc999, 0x21, 0 - .dw 0x31c0, 0xc999, 0x31ff, 0xc999, 0x21, 0 - .dw 0x3240, 0xc999, 0x327f, 0xc999, 0x21, 0 - .dw 0x32c0, 0xc999, 0x32ff, 0xc999, 0x21, 0 - .dw 0x3340, 0xc999, 0x337f, 0xc999, 0x21, 0 - .dw 0x33c0, 0xc999, 0x33ff, 0xc999, 0x21, 0 - .dw 0x3440, 0xc999, 0x347f, 0xc999, 0x21, 0 - .dw 0x34c0, 0xc999, 0x34ff, 0xc999, 0x21, 0 - .dw 0x3540, 0xc999, 0x357f, 0xc999, 0x21, 0 - .dw 0x35c0, 0xc999, 0x35ff, 0xc999, 0x21, 0 - .dw 0x3640, 0xc999, 0x367f, 0xc999, 0x21, 0 - .dw 0x36c0, 0xc999, 0x36ff, 0xc999, 0x21, 0 - .dw 0x3740, 0xc999, 0x377f, 0xc999, 0x21, 0 - .dw 0x37c0, 0xc999, 0x37ff, 0xc999, 0x21, 0 - .dw 0x3840, 0xc999, 0x387f, 0xc999, 0x21, 0 - .dw 0x38c0, 0xc999, 0x38ff, 0xc999, 0x21, 0 - .dw 0x3940, 0xc999, 0x397f, 0xc999, 0x21, 0 - .dw 0x39c0, 0xc999, 0x5fff, 0xc999, 0x21, 0 - .dw 0x6040, 0xc999, 0x607f, 0xc999, 0x21, 0 - .dw 0x60c0, 0xc999, 0x60ff, 0xc999, 0x21, 0 - .dw 0x6140, 0xc999, 0x617f, 0xc999, 0x21, 0 - .dw 0x61c0, 0xc999, 0x61ff, 0xc999, 0x21, 0 - .dw 0x6240, 0xc999, 0x627f, 0xc999, 0x21, 0 - .dw 0x62c0, 0xc999, 0x62ff, 0xc999, 0x21, 0 - .dw 0x6340, 0xc999, 0x637f, 0xc999, 0x21, 0 - .dw 0x63c0, 0xc999, 0x63ff, 0xc999, 0x21, 0 - .dw 0x6440, 0xc999, 0x647f, 0xc999, 0x21, 0 - .dw 0x64c0, 0xc999, 0x64ff, 0xc999, 0x21, 0 - .dw 0x6540, 0xc999, 0x657f, 0xc999, 0x21, 0 - .dw 0x65c0, 0xc999, 0x65ff, 0xc999, 0x21, 0 - .dw 0x6640, 0xc999, 0x667f, 0xc999, 0x21, 0 - .dw 0x66c0, 0xc999, 0x66ff, 0xc999, 0x21, 0 - .dw 0x6740, 0xc999, 0x677f, 0xc999, 0x21, 0 - .dw 0x67c0, 0xc999, 0x67ff, 0xc999, 0x21, 0 - .dw 0x6840, 0xc999, 0x687f, 0xc999, 0x21, 0 - .dw 0x68c0, 0xc999, 0x68ff, 0xc999, 0x21, 0 - .dw 0x6940, 0xc999, 0x697f, 0xc999, 0x21, 0 - .dw 0x69c0, 0xc999, 0x69ff, 0xc999, 0x21, 0 - .dw 0x6a40, 0xc999, 0x6a7f, 0xc999, 0x21, 0 - .dw 0x6ac0, 0xc999, 0x6aff, 0xc999, 0x21, 0 - .dw 0x6b40, 0xc999, 0x6b7f, 0xc999, 0x21, 0 - .dw 0x6bc0, 0xc999, 0x6bff, 0xc999, 0x21, 0 - .dw 0x6c40, 0xc999, 0x6c7f, 0xc999, 0x21, 0 - .dw 0x6cc0, 0xc999, 0x6cff, 0xc999, 0x21, 0 - .dw 0x6d40, 0xc999, 0x6d7f, 0xc999, 0x21, 0 - .dw 0x6dc0, 0xc999, 0x6dff, 0xc999, 0x21, 0 - .dw 0x6e40, 0xc999, 0x6e7f, 0xc999, 0x21, 0 - .dw 0x6ec0, 0xc999, 0x6eff, 0xc999, 0x21, 0 - .dw 0x6f40, 0xc999, 0x6f7f, 0xc999, 0x21, 0 - .dw 0x6fc0, 0xc999, 0x6fff, 0xc999, 0x21, 0 - .dw 0x7040, 0xc999, 0x707f, 0xc999, 0x21, 0 - .dw 0x70c0, 0xc999, 0x70ff, 0xc999, 0x21, 0 - .dw 0x7140, 0xc999, 0x717f, 0xc999, 0x21, 0 - .dw 0x71c0, 0xc999, 0x71ff, 0xc999, 0x21, 0 - .dw 0x7240, 0xc999, 0x727f, 0xc999, 0x21, 0 - .dw 0x72c0, 0xc999, 0x72ff, 0xc999, 0x21, 0 - .dw 0x7340, 0xc999, 0x737f, 0xc999, 0x21, 0 - .dw 0x73c0, 0xc999, 0x73ff, 0xc999, 0x21, 0 - .dw 0x7440, 0xc999, 0x747f, 0xc999, 0x21, 0 - .dw 0x74c0, 0xc999, 0x74ff, 0xc999, 0x21, 0 - .dw 0x7540, 0xc999, 0x757f, 0xc999, 0x21, 0 - .dw 0x75c0, 0xc999, 0x75ff, 0xc999, 0x21, 0 - .dw 0x7640, 0xc999, 0x767f, 0xc999, 0x21, 0 - .dw 0x76c0, 0xc999, 0x76ff, 0xc999, 0x21, 0 - .dw 0x7740, 0xc999, 0x777f, 0xc999, 0x21, 0 - .dw 0x77c0, 0xc999, 0x77ff, 0xc999, 0x21, 0 - .dw 0x7840, 0xc999, 0x787f, 0xc999, 0x21, 0 - .dw 0x78c0, 0xc999, 0x78ff, 0xc999, 0x21, 0 - .dw 0x7940, 0xc999, 0x797f, 0xc999, 0x21, 0 - .dw 0x79c0, 0xc999, 0x9fff, 0xc999, 0x21, 0 - .dw 0xa040, 0xc999, 0xa07f, 0xc999, 0x21, 0 - .dw 0xa0c0, 0xc999, 0xa0ff, 0xc999, 0x21, 0 - .dw 0xa140, 0xc999, 0xa17f, 0xc999, 0x21, 0 - .dw 0xa1c0, 0xc999, 0xa1ff, 0xc999, 0x21, 0 - .dw 0xa240, 0xc999, 0xa27f, 0xc999, 0x21, 0 - .dw 0xa2c0, 0xc999, 0xa2ff, 0xc999, 0x21, 0 - .dw 0xa340, 0xc999, 0xa37f, 0xc999, 0x21, 0 - .dw 0xa3c0, 0xc999, 0xa3ff, 0xc999, 0x21, 0 - .dw 0xa440, 0xc999, 0xa47f, 0xc999, 0x21, 0 - .dw 0xa4c0, 0xc999, 0xa4ff, 0xc999, 0x21, 0 - .dw 0xa540, 0xc999, 0xa57f, 0xc999, 0x21, 0 - .dw 0xa5c0, 0xc999, 0xa5ff, 0xc999, 0x21, 0 - .dw 0xa640, 0xc999, 0xa67f, 0xc999, 0x21, 0 - .dw 0xa6c0, 0xc999, 0xa6ff, 0xc999, 0x21, 0 - .dw 0xa740, 0xc999, 0xa77f, 0xc999, 0x21, 0 - .dw 0xa7c0, 0xc999, 0xa7ff, 0xc999, 0x21, 0 - .dw 0xa840, 0xc999, 0xa87f, 0xc999, 0x21, 0 - .dw 0xa8c0, 0xc999, 0xa8ff, 0xc999, 0x21, 0 - .dw 0xa940, 0xc999, 0xa97f, 0xc999, 0x21, 0 - .dw 0xa9c0, 0xc999, 0xa9ff, 0xc999, 0x21, 0 - .dw 0xaa40, 0xc999, 0xaa7f, 0xc999, 0x21, 0 - .dw 0xaac0, 0xc999, 0xaaff, 0xc999, 0x21, 0 - .dw 0xab40, 0xc999, 0xab7f, 0xc999, 0x21, 0 - .dw 0xabc0, 0xc999, 0xabff, 0xc999, 0x21, 0 - .dw 0xac40, 0xc999, 0xac7f, 0xc999, 0x21, 0 - .dw 0xacc0, 0xc999, 0xacff, 0xc999, 0x21, 0 - .dw 0xad40, 0xc999, 0xad7f, 0xc999, 0x21, 0 - .dw 0xadc0, 0xc999, 0xadff, 0xc999, 0x21, 0 - .dw 0xae40, 0xc999, 0xae7f, 0xc999, 0x21, 0 - .dw 0xaec0, 0xc999, 0xaeff, 0xc999, 0x21, 0 - .dw 0xaf40, 0xc999, 0xaf7f, 0xc999, 0x21, 0 - .dw 0xafc0, 0xc999, 0xafff, 0xc999, 0x21, 0 - .dw 0xb040, 0xc999, 0xb07f, 0xc999, 0x21, 0 - .dw 0xb0c0, 0xc999, 0xb0ff, 0xc999, 0x21, 0 - .dw 0xb140, 0xc999, 0xb17f, 0xc999, 0x21, 0 - .dw 0xb1c0, 0xc999, 0xb1ff, 0xc999, 0x21, 0 - .dw 0xb240, 0xc999, 0xb27f, 0xc999, 0x21, 0 - .dw 0xb2c0, 0xc999, 0xb2ff, 0xc999, 0x21, 0 - .dw 0xb340, 0xc999, 0xb37f, 0xc999, 0x21, 0 - .dw 0xb3c0, 0xc999, 0xb3ff, 0xc999, 0x21, 0 - .dw 0xb440, 0xc999, 0xb47f, 0xc999, 0x21, 0 - .dw 0xb4c0, 0xc999, 0xb4ff, 0xc999, 0x21, 0 - .dw 0xb540, 0xc999, 0xb57f, 0xc999, 0x21, 0 - .dw 0xb5c0, 0xc999, 0xb5ff, 0xc999, 0x21, 0 - .dw 0xb640, 0xc999, 0xb67f, 0xc999, 0x21, 0 - .dw 0xb6c0, 0xc999, 0xb6ff, 0xc999, 0x21, 0 - .dw 0xb740, 0xc999, 0xb77f, 0xc999, 0x21, 0 - .dw 0xb7c0, 0xc999, 0xb7ff, 0xc999, 0x21, 0 - .dw 0xb840, 0xc999, 0xb87f, 0xc999, 0x21, 0 - .dw 0xb8c0, 0xc999, 0xb8ff, 0xc999, 0x21, 0 - .dw 0xb940, 0xc999, 0xb97f, 0xc999, 0x21, 0 - .dw 0xb9c0, 0xc999, 0xdfff, 0xc999, 0x21, 0 - .dw 0xe040, 0xc999, 0xe07f, 0xc999, 0x21, 0 - .dw 0xe0c0, 0xc999, 0xe0ff, 0xc999, 0x21, 0 - .dw 0xe140, 0xc999, 0xe17f, 0xc999, 0x21, 0 - .dw 0xe1c0, 0xc999, 0xe1ff, 0xc999, 0x21, 0 - .dw 0xe240, 0xc999, 0xe27f, 0xc999, 0x21, 0 - .dw 0xe2c0, 0xc999, 0xe2ff, 0xc999, 0x21, 0 - .dw 0xe340, 0xc999, 0xe37f, 0xc999, 0x21, 0 - .dw 0xe3c0, 0xc999, 0xe3ff, 0xc999, 0x21, 0 - .dw 0xe440, 0xc999, 0xe47f, 0xc999, 0x21, 0 - .dw 0xe4c0, 0xc999, 0xe4ff, 0xc999, 0x21, 0 - .dw 0xe540, 0xc999, 0xe57f, 0xc999, 0x21, 0 - .dw 0xe5c0, 0xc999, 0xe5ff, 0xc999, 0x21, 0 - .dw 0xe640, 0xc999, 0xe67f, 0xc999, 0x21, 0 - .dw 0xe6c0, 0xc999, 0xe6ff, 0xc999, 0x21, 0 - .dw 0xe740, 0xc999, 0xe77f, 0xc999, 0x21, 0 - .dw 0xe7c0, 0xc999, 0xe7ff, 0xc999, 0x21, 0 - .dw 0xe840, 0xc999, 0xe87f, 0xc999, 0x21, 0 - .dw 0xe8c0, 0xc999, 0xe8ff, 0xc999, 0x21, 0 - .dw 0xe940, 0xc999, 0xe97f, 0xc999, 0x21, 0 - .dw 0xe9c0, 0xc999, 0xe9ff, 0xc999, 0x21, 0 - .dw 0xea40, 0xc999, 0xea7f, 0xc999, 0x21, 0 - .dw 0xeac0, 0xc999, 0xeaff, 0xc999, 0x21, 0 - .dw 0xeb40, 0xc999, 0xeb7f, 0xc999, 0x21, 0 - .dw 0xebc0, 0xc999, 0xebff, 0xc999, 0x21, 0 - .dw 0xec40, 0xc999, 0xec7f, 0xc999, 0x21, 0 - .dw 0xecc0, 0xc999, 0xecff, 0xc999, 0x21, 0 - .dw 0xed40, 0xc999, 0xed7f, 0xc999, 0x21, 0 - .dw 0xedc0, 0xc999, 0xedff, 0xc999, 0x21, 0 - .dw 0xee40, 0xc999, 0xee7f, 0xc999, 0x21, 0 - .dw 0xeec0, 0xc999, 0xeeff, 0xc999, 0x21, 0 - .dw 0xef40, 0xc999, 0xef7f, 0xc999, 0x21, 0 - .dw 0xefc0, 0xc999, 0xefff, 0xc999, 0x21, 0 - .dw 0xf040, 0xc999, 0xf07f, 0xc999, 0x21, 0 - .dw 0xf0c0, 0xc999, 0xf0ff, 0xc999, 0x21, 0 - .dw 0xf140, 0xc999, 0xf17f, 0xc999, 0x21, 0 - .dw 0xf1c0, 0xc999, 0xf1ff, 0xc999, 0x21, 0 - .dw 0xf240, 0xc999, 0xf27f, 0xc999, 0x21, 0 - .dw 0xf2c0, 0xc999, 0xf2ff, 0xc999, 0x21, 0 - .dw 0xf340, 0xc999, 0xf37f, 0xc999, 0x21, 0 - .dw 0xf3c0, 0xc999, 0xf3ff, 0xc999, 0x21, 0 - .dw 0xf440, 0xc999, 0xf47f, 0xc999, 0x21, 0 - .dw 0xf4c0, 0xc999, 0xf4ff, 0xc999, 0x21, 0 - .dw 0xf540, 0xc999, 0xf57f, 0xc999, 0x21, 0 - .dw 0xf5c0, 0xc999, 0xf5ff, 0xc999, 0x21, 0 - .dw 0xf640, 0xc999, 0xf67f, 0xc999, 0x21, 0 - .dw 0xf6c0, 0xc999, 0xf6ff, 0xc999, 0x21, 0 - .dw 0xf740, 0xc999, 0xf77f, 0xc999, 0x21, 0 - .dw 0xf7c0, 0xc999, 0xf7ff, 0xc999, 0x21, 0 - .dw 0xf840, 0xc999, 0xf87f, 0xc999, 0x21, 0 - .dw 0xf8c0, 0xc999, 0xf8ff, 0xc999, 0x21, 0 - .dw 0xf940, 0xc999, 0xf97f, 0xc999, 0x21, 0 - .dw 0xf9c0, 0xc999, 0x1fff, 0xc99a, 0x21, 0 - .dw 0x2040, 0xc99a, 0x207f, 0xc99a, 0x21, 0 - .dw 0x20c0, 0xc99a, 0x20ff, 0xc99a, 0x21, 0 - .dw 0x2140, 0xc99a, 0x217f, 0xc99a, 0x21, 0 - .dw 0x21c0, 0xc99a, 0x21ff, 0xc99a, 0x21, 0 - .dw 0x2240, 0xc99a, 0x227f, 0xc99a, 0x21, 0 - .dw 0x22c0, 0xc99a, 0x22ff, 0xc99a, 0x21, 0 - .dw 0x2340, 0xc99a, 0x237f, 0xc99a, 0x21, 0 - .dw 0x23c0, 0xc99a, 0x23ff, 0xc99a, 0x21, 0 - .dw 0x2440, 0xc99a, 0x247f, 0xc99a, 0x21, 0 - .dw 0x24c0, 0xc99a, 0x24ff, 0xc99a, 0x21, 0 - .dw 0x2540, 0xc99a, 0x257f, 0xc99a, 0x21, 0 - .dw 0x25c0, 0xc99a, 0x25ff, 0xc99a, 0x21, 0 - .dw 0x2640, 0xc99a, 0x267f, 0xc99a, 0x21, 0 - .dw 0x26c0, 0xc99a, 0x26ff, 0xc99a, 0x21, 0 - .dw 0x2740, 0xc99a, 0x277f, 0xc99a, 0x21, 0 - .dw 0x27c0, 0xc99a, 0x27ff, 0xc99a, 0x21, 0 - .dw 0x2840, 0xc99a, 0x287f, 0xc99a, 0x21, 0 - .dw 0x28c0, 0xc99a, 0x28ff, 0xc99a, 0x21, 0 - .dw 0x2940, 0xc99a, 0x297f, 0xc99a, 0x21, 0 - .dw 0x29c0, 0xc99a, 0x29ff, 0xc99a, 0x21, 0 - .dw 0x2a40, 0xc99a, 0x2a7f, 0xc99a, 0x21, 0 - .dw 0x2ac0, 0xc99a, 0x2aff, 0xc99a, 0x21, 0 - .dw 0x2b40, 0xc99a, 0x2b7f, 0xc99a, 0x21, 0 - .dw 0x2bc0, 0xc99a, 0x2bff, 0xc99a, 0x21, 0 - .dw 0x2c40, 0xc99a, 0x2c7f, 0xc99a, 0x21, 0 - .dw 0x2cc0, 0xc99a, 0x2cff, 0xc99a, 0x21, 0 - .dw 0x2d40, 0xc99a, 0x2d7f, 0xc99a, 0x21, 0 - .dw 0x2dc0, 0xc99a, 0x2dff, 0xc99a, 0x21, 0 - .dw 0x2e40, 0xc99a, 0x2e7f, 0xc99a, 0x21, 0 - .dw 0x2ec0, 0xc99a, 0x2eff, 0xc99a, 0x21, 0 - .dw 0x2f40, 0xc99a, 0x2f7f, 0xc99a, 0x21, 0 - .dw 0x2fc0, 0xc99a, 0x2fff, 0xc99a, 0x21, 0 - .dw 0x3040, 0xc99a, 0x307f, 0xc99a, 0x21, 0 - .dw 0x30c0, 0xc99a, 0x30ff, 0xc99a, 0x21, 0 - .dw 0x3140, 0xc99a, 0x317f, 0xc99a, 0x21, 0 - .dw 0x31c0, 0xc99a, 0x31ff, 0xc99a, 0x21, 0 - .dw 0x3240, 0xc99a, 0x327f, 0xc99a, 0x21, 0 - .dw 0x32c0, 0xc99a, 0x32ff, 0xc99a, 0x21, 0 - .dw 0x3340, 0xc99a, 0x337f, 0xc99a, 0x21, 0 - .dw 0x33c0, 0xc99a, 0x33ff, 0xc99a, 0x21, 0 - .dw 0x3440, 0xc99a, 0x347f, 0xc99a, 0x21, 0 - .dw 0x34c0, 0xc99a, 0x34ff, 0xc99a, 0x21, 0 - .dw 0x3540, 0xc99a, 0x357f, 0xc99a, 0x21, 0 - .dw 0x35c0, 0xc99a, 0x35ff, 0xc99a, 0x21, 0 - .dw 0x3640, 0xc99a, 0x367f, 0xc99a, 0x21, 0 - .dw 0x36c0, 0xc99a, 0x36ff, 0xc99a, 0x21, 0 - .dw 0x3740, 0xc99a, 0x377f, 0xc99a, 0x21, 0 - .dw 0x37c0, 0xc99a, 0x37ff, 0xc99a, 0x21, 0 - .dw 0x3840, 0xc99a, 0x387f, 0xc99a, 0x21, 0 - .dw 0x38c0, 0xc99a, 0x38ff, 0xc99a, 0x21, 0 - .dw 0x3940, 0xc99a, 0x397f, 0xc99a, 0x21, 0 - .dw 0x39c0, 0xc99a, 0x5fff, 0xc99a, 0x21, 0 - .dw 0x6040, 0xc99a, 0x607f, 0xc99a, 0x21, 0 - .dw 0x60c0, 0xc99a, 0x60ff, 0xc99a, 0x21, 0 - .dw 0x6140, 0xc99a, 0x617f, 0xc99a, 0x21, 0 - .dw 0x61c0, 0xc99a, 0x61ff, 0xc99a, 0x21, 0 - .dw 0x6240, 0xc99a, 0x627f, 0xc99a, 0x21, 0 - .dw 0x62c0, 0xc99a, 0x62ff, 0xc99a, 0x21, 0 - .dw 0x6340, 0xc99a, 0x637f, 0xc99a, 0x21, 0 - .dw 0x63c0, 0xc99a, 0x63ff, 0xc99a, 0x21, 0 - .dw 0x6440, 0xc99a, 0x647f, 0xc99a, 0x21, 0 - .dw 0x64c0, 0xc99a, 0x64ff, 0xc99a, 0x21, 0 - .dw 0x6540, 0xc99a, 0x657f, 0xc99a, 0x21, 0 - .dw 0x65c0, 0xc99a, 0x65ff, 0xc99a, 0x21, 0 - .dw 0x6640, 0xc99a, 0x667f, 0xc99a, 0x21, 0 - .dw 0x66c0, 0xc99a, 0x66ff, 0xc99a, 0x21, 0 - .dw 0x6740, 0xc99a, 0x677f, 0xc99a, 0x21, 0 - .dw 0x67c0, 0xc99a, 0x67ff, 0xc99a, 0x21, 0 - .dw 0x6840, 0xc99a, 0x687f, 0xc99a, 0x21, 0 - .dw 0x68c0, 0xc99a, 0x68ff, 0xc99a, 0x21, 0 - .dw 0x6940, 0xc99a, 0x697f, 0xc99a, 0x21, 0 - .dw 0x69c0, 0xc99a, 0x69ff, 0xc99a, 0x21, 0 - .dw 0x6a40, 0xc99a, 0x6a7f, 0xc99a, 0x21, 0 - .dw 0x6ac0, 0xc99a, 0x6aff, 0xc99a, 0x21, 0 - .dw 0x6b40, 0xc99a, 0x6b7f, 0xc99a, 0x21, 0 - .dw 0x6bc0, 0xc99a, 0x6bff, 0xc99a, 0x21, 0 - .dw 0x6c40, 0xc99a, 0x6c7f, 0xc99a, 0x21, 0 - .dw 0x6cc0, 0xc99a, 0x6cff, 0xc99a, 0x21, 0 - .dw 0x6d40, 0xc99a, 0x6d7f, 0xc99a, 0x21, 0 - .dw 0x6dc0, 0xc99a, 0x6dff, 0xc99a, 0x21, 0 - .dw 0x6e40, 0xc99a, 0x6e7f, 0xc99a, 0x21, 0 - .dw 0x6ec0, 0xc99a, 0x6eff, 0xc99a, 0x21, 0 - .dw 0x6f40, 0xc99a, 0x6f7f, 0xc99a, 0x21, 0 - .dw 0x6fc0, 0xc99a, 0x6fff, 0xc99a, 0x21, 0 - .dw 0x7040, 0xc99a, 0x707f, 0xc99a, 0x21, 0 - .dw 0x70c0, 0xc99a, 0x70ff, 0xc99a, 0x21, 0 - .dw 0x7140, 0xc99a, 0x717f, 0xc99a, 0x21, 0 - .dw 0x71c0, 0xc99a, 0x71ff, 0xc99a, 0x21, 0 - .dw 0x7240, 0xc99a, 0x727f, 0xc99a, 0x21, 0 - .dw 0x72c0, 0xc99a, 0x72ff, 0xc99a, 0x21, 0 - .dw 0x7340, 0xc99a, 0x737f, 0xc99a, 0x21, 0 - .dw 0x73c0, 0xc99a, 0x73ff, 0xc99a, 0x21, 0 - .dw 0x7440, 0xc99a, 0x747f, 0xc99a, 0x21, 0 - .dw 0x74c0, 0xc99a, 0x74ff, 0xc99a, 0x21, 0 - .dw 0x7540, 0xc99a, 0x757f, 0xc99a, 0x21, 0 - .dw 0x75c0, 0xc99a, 0x75ff, 0xc99a, 0x21, 0 - .dw 0x7640, 0xc99a, 0x767f, 0xc99a, 0x21, 0 - .dw 0x76c0, 0xc99a, 0x76ff, 0xc99a, 0x21, 0 - .dw 0x7740, 0xc99a, 0x777f, 0xc99a, 0x21, 0 - .dw 0x77c0, 0xc99a, 0x77ff, 0xc99a, 0x21, 0 - .dw 0x7840, 0xc99a, 0x787f, 0xc99a, 0x21, 0 - .dw 0x78c0, 0xc99a, 0x78ff, 0xc99a, 0x21, 0 - .dw 0x7940, 0xc99a, 0x797f, 0xc99a, 0x21, 0 - .dw 0x79c0, 0xc99a, 0x9fff, 0xc99a, 0x21, 0 - .dw 0xa040, 0xc99a, 0xa07f, 0xc99a, 0x21, 0 - .dw 0xa0c0, 0xc99a, 0xa0ff, 0xc99a, 0x21, 0 - .dw 0xa140, 0xc99a, 0xa17f, 0xc99a, 0x21, 0 - .dw 0xa1c0, 0xc99a, 0xa1ff, 0xc99a, 0x21, 0 - .dw 0xa240, 0xc99a, 0xa27f, 0xc99a, 0x21, 0 - .dw 0xa2c0, 0xc99a, 0xa2ff, 0xc99a, 0x21, 0 - .dw 0xa340, 0xc99a, 0xa37f, 0xc99a, 0x21, 0 - .dw 0xa3c0, 0xc99a, 0xa3ff, 0xc99a, 0x21, 0 - .dw 0xa440, 0xc99a, 0xa47f, 0xc99a, 0x21, 0 - .dw 0xa4c0, 0xc99a, 0xa4ff, 0xc99a, 0x21, 0 - .dw 0xa540, 0xc99a, 0xa57f, 0xc99a, 0x21, 0 - .dw 0xa5c0, 0xc99a, 0xa5ff, 0xc99a, 0x21, 0 - .dw 0xa640, 0xc99a, 0xa67f, 0xc99a, 0x21, 0 - .dw 0xa6c0, 0xc99a, 0xa6ff, 0xc99a, 0x21, 0 - .dw 0xa740, 0xc99a, 0xa77f, 0xc99a, 0x21, 0 - .dw 0xa7c0, 0xc99a, 0xa7ff, 0xc99a, 0x21, 0 - .dw 0xa840, 0xc99a, 0xa87f, 0xc99a, 0x21, 0 - .dw 0xa8c0, 0xc99a, 0xa8ff, 0xc99a, 0x21, 0 - .dw 0xa940, 0xc99a, 0xa97f, 0xc99a, 0x21, 0 - .dw 0xa9c0, 0xc99a, 0xa9ff, 0xc99a, 0x21, 0 - .dw 0xaa40, 0xc99a, 0xaa7f, 0xc99a, 0x21, 0 - .dw 0xaac0, 0xc99a, 0xaaff, 0xc99a, 0x21, 0 - .dw 0xab40, 0xc99a, 0xab7f, 0xc99a, 0x21, 0 - .dw 0xabc0, 0xc99a, 0xabff, 0xc99a, 0x21, 0 - .dw 0xac40, 0xc99a, 0xac7f, 0xc99a, 0x21, 0 - .dw 0xacc0, 0xc99a, 0xacff, 0xc99a, 0x21, 0 - .dw 0xad40, 0xc99a, 0xad7f, 0xc99a, 0x21, 0 - .dw 0xadc0, 0xc99a, 0xadff, 0xc99a, 0x21, 0 - .dw 0xae40, 0xc99a, 0xae7f, 0xc99a, 0x21, 0 - .dw 0xaec0, 0xc99a, 0xaeff, 0xc99a, 0x21, 0 - .dw 0xaf40, 0xc99a, 0xaf7f, 0xc99a, 0x21, 0 - .dw 0xafc0, 0xc99a, 0xafff, 0xc99a, 0x21, 0 - .dw 0xb040, 0xc99a, 0xb07f, 0xc99a, 0x21, 0 - .dw 0xb0c0, 0xc99a, 0xb0ff, 0xc99a, 0x21, 0 - .dw 0xb140, 0xc99a, 0xb17f, 0xc99a, 0x21, 0 - .dw 0xb1c0, 0xc99a, 0xb1ff, 0xc99a, 0x21, 0 - .dw 0xb240, 0xc99a, 0xb27f, 0xc99a, 0x21, 0 - .dw 0xb2c0, 0xc99a, 0xb2ff, 0xc99a, 0x21, 0 - .dw 0xb340, 0xc99a, 0xb37f, 0xc99a, 0x21, 0 - .dw 0xb3c0, 0xc99a, 0xb3ff, 0xc99a, 0x21, 0 - .dw 0xb440, 0xc99a, 0xb47f, 0xc99a, 0x21, 0 - .dw 0xb4c0, 0xc99a, 0xb4ff, 0xc99a, 0x21, 0 - .dw 0xb540, 0xc99a, 0xb57f, 0xc99a, 0x21, 0 - .dw 0xb5c0, 0xc99a, 0xb5ff, 0xc99a, 0x21, 0 - .dw 0xb640, 0xc99a, 0xb67f, 0xc99a, 0x21, 0 - .dw 0xb6c0, 0xc99a, 0xb6ff, 0xc99a, 0x21, 0 - .dw 0xb740, 0xc99a, 0xb77f, 0xc99a, 0x21, 0 - .dw 0xb7c0, 0xc99a, 0xb7ff, 0xc99a, 0x21, 0 - .dw 0xb840, 0xc99a, 0xb87f, 0xc99a, 0x21, 0 - .dw 0xb8c0, 0xc99a, 0xb8ff, 0xc99a, 0x21, 0 - .dw 0xb940, 0xc99a, 0xb97f, 0xc99a, 0x21, 0 - .dw 0xb9c0, 0xc99a, 0xdfff, 0xc99a, 0x21, 0 - .dw 0xe040, 0xc99a, 0xe07f, 0xc99a, 0x21, 0 - .dw 0xe0c0, 0xc99a, 0xe0ff, 0xc99a, 0x21, 0 - .dw 0xe140, 0xc99a, 0xe17f, 0xc99a, 0x21, 0 - .dw 0xe1c0, 0xc99a, 0xe1ff, 0xc99a, 0x21, 0 - .dw 0xe240, 0xc99a, 0xe27f, 0xc99a, 0x21, 0 - .dw 0xe2c0, 0xc99a, 0xe2ff, 0xc99a, 0x21, 0 - .dw 0xe340, 0xc99a, 0xe37f, 0xc99a, 0x21, 0 - .dw 0xe3c0, 0xc99a, 0xe3ff, 0xc99a, 0x21, 0 - .dw 0xe440, 0xc99a, 0xe47f, 0xc99a, 0x21, 0 - .dw 0xe4c0, 0xc99a, 0xe4ff, 0xc99a, 0x21, 0 - .dw 0xe540, 0xc99a, 0xe57f, 0xc99a, 0x21, 0 - .dw 0xe5c0, 0xc99a, 0xe5ff, 0xc99a, 0x21, 0 - .dw 0xe640, 0xc99a, 0xe67f, 0xc99a, 0x21, 0 - .dw 0xe6c0, 0xc99a, 0xe6ff, 0xc99a, 0x21, 0 - .dw 0xe740, 0xc99a, 0xe77f, 0xc99a, 0x21, 0 - .dw 0xe7c0, 0xc99a, 0xe7ff, 0xc99a, 0x21, 0 - .dw 0xe840, 0xc99a, 0xe87f, 0xc99a, 0x21, 0 - .dw 0xe8c0, 0xc99a, 0xe8ff, 0xc99a, 0x21, 0 - .dw 0xe940, 0xc99a, 0xe97f, 0xc99a, 0x21, 0 - .dw 0xe9c0, 0xc99a, 0xe9ff, 0xc99a, 0x21, 0 - .dw 0xea40, 0xc99a, 0xea7f, 0xc99a, 0x21, 0 - .dw 0xeac0, 0xc99a, 0xeaff, 0xc99a, 0x21, 0 - .dw 0xeb40, 0xc99a, 0xeb7f, 0xc99a, 0x21, 0 - .dw 0xebc0, 0xc99a, 0xebff, 0xc99a, 0x21, 0 - .dw 0xec40, 0xc99a, 0xec7f, 0xc99a, 0x21, 0 - .dw 0xecc0, 0xc99a, 0xecff, 0xc99a, 0x21, 0 - .dw 0xed40, 0xc99a, 0xed7f, 0xc99a, 0x21, 0 - .dw 0xedc0, 0xc99a, 0xedff, 0xc99a, 0x21, 0 - .dw 0xee40, 0xc99a, 0xee7f, 0xc99a, 0x21, 0 - .dw 0xeec0, 0xc99a, 0xeeff, 0xc99a, 0x21, 0 - .dw 0xef40, 0xc99a, 0xef7f, 0xc99a, 0x21, 0 - .dw 0xefc0, 0xc99a, 0xefff, 0xc99a, 0x21, 0 - .dw 0xf040, 0xc99a, 0xf07f, 0xc99a, 0x21, 0 - .dw 0xf0c0, 0xc99a, 0xf0ff, 0xc99a, 0x21, 0 - .dw 0xf140, 0xc99a, 0xf17f, 0xc99a, 0x21, 0 - .dw 0xf1c0, 0xc99a, 0xf1ff, 0xc99a, 0x21, 0 - .dw 0xf240, 0xc99a, 0xf27f, 0xc99a, 0x21, 0 - .dw 0xf2c0, 0xc99a, 0xf2ff, 0xc99a, 0x21, 0 - .dw 0xf340, 0xc99a, 0xf37f, 0xc99a, 0x21, 0 - .dw 0xf3c0, 0xc99a, 0xf3ff, 0xc99a, 0x21, 0 - .dw 0xf440, 0xc99a, 0xf47f, 0xc99a, 0x21, 0 - .dw 0xf4c0, 0xc99a, 0xf4ff, 0xc99a, 0x21, 0 - .dw 0xf540, 0xc99a, 0xf57f, 0xc99a, 0x21, 0 - .dw 0xf5c0, 0xc99a, 0xf5ff, 0xc99a, 0x21, 0 - .dw 0xf640, 0xc99a, 0xf67f, 0xc99a, 0x21, 0 - .dw 0xf6c0, 0xc99a, 0xf6ff, 0xc99a, 0x21, 0 - .dw 0xf740, 0xc99a, 0xf77f, 0xc99a, 0x21, 0 - .dw 0xf7c0, 0xc99a, 0xf7ff, 0xc99a, 0x21, 0 - .dw 0xf840, 0xc99a, 0xf87f, 0xc99a, 0x21, 0 - .dw 0xf8c0, 0xc99a, 0xf8ff, 0xc99a, 0x21, 0 - .dw 0xf940, 0xc99a, 0xf97f, 0xc99a, 0x21, 0 - .dw 0xf9c0, 0xc99a, 0xffff, 0xc99b, 0x21, 0 - .dw 0x0040, 0xc99c, 0x007f, 0xc99c, 0x21, 0 - .dw 0x00c0, 0xc99c, 0x00ff, 0xc99c, 0x21, 0 - .dw 0x0140, 0xc99c, 0x017f, 0xc99c, 0x21, 0 - .dw 0x01c0, 0xc99c, 0x01ff, 0xc99c, 0x21, 0 - .dw 0x0240, 0xc99c, 0x027f, 0xc99c, 0x21, 0 - .dw 0x02c0, 0xc99c, 0x02ff, 0xc99c, 0x21, 0 - .dw 0x0340, 0xc99c, 0x037f, 0xc99c, 0x21, 0 - .dw 0x03c0, 0xc99c, 0x03ff, 0xc99c, 0x21, 0 - .dw 0x0440, 0xc99c, 0x047f, 0xc99c, 0x21, 0 - .dw 0x04c0, 0xc99c, 0x04ff, 0xc99c, 0x21, 0 - .dw 0x0540, 0xc99c, 0x057f, 0xc99c, 0x21, 0 - .dw 0x05c0, 0xc99c, 0x05ff, 0xc99c, 0x21, 0 - .dw 0x0640, 0xc99c, 0x067f, 0xc99c, 0x21, 0 - .dw 0x06c0, 0xc99c, 0x06ff, 0xc99c, 0x21, 0 - .dw 0x0740, 0xc99c, 0x077f, 0xc99c, 0x21, 0 - .dw 0x07c0, 0xc99c, 0x07ff, 0xc99c, 0x21, 0 - .dw 0x0840, 0xc99c, 0x087f, 0xc99c, 0x21, 0 - .dw 0x08c0, 0xc99c, 0x08ff, 0xc99c, 0x21, 0 - .dw 0x0940, 0xc99c, 0x097f, 0xc99c, 0x21, 0 - .dw 0x09c0, 0xc99c, 0x09ff, 0xc99c, 0x21, 0 - .dw 0x0a40, 0xc99c, 0x0a7f, 0xc99c, 0x21, 0 - .dw 0x0ac0, 0xc99c, 0x0aff, 0xc99c, 0x21, 0 - .dw 0x0b40, 0xc99c, 0x0b7f, 0xc99c, 0x21, 0 - .dw 0x0bc0, 0xc99c, 0x0bff, 0xc99c, 0x21, 0 - .dw 0x0c40, 0xc99c, 0x0c7f, 0xc99c, 0x21, 0 - .dw 0x0cc0, 0xc99c, 0x0cff, 0xc99c, 0x21, 0 - .dw 0x0d40, 0xc99c, 0x0d7f, 0xc99c, 0x21, 0 - .dw 0x0dc0, 0xc99c, 0x0dff, 0xc99c, 0x21, 0 - .dw 0x0e40, 0xc99c, 0x0e7f, 0xc99c, 0x21, 0 - .dw 0x0ec0, 0xc99c, 0x0eff, 0xc99c, 0x21, 0 - .dw 0x0f40, 0xc99c, 0x0f7f, 0xc99c, 0x21, 0 - .dw 0x0fc0, 0xc99c, 0x0fff, 0xc99c, 0x21, 0 - .dw 0x1040, 0xc99c, 0x107f, 0xc99c, 0x21, 0 - .dw 0x10c0, 0xc99c, 0x10ff, 0xc99c, 0x21, 0 - .dw 0x1140, 0xc99c, 0x117f, 0xc99c, 0x21, 0 - .dw 0x11c0, 0xc99c, 0x11ff, 0xc99c, 0x21, 0 - .dw 0x1240, 0xc99c, 0x127f, 0xc99c, 0x21, 0 - .dw 0x12c0, 0xc99c, 0x12ff, 0xc99c, 0x21, 0 - .dw 0x1340, 0xc99c, 0x137f, 0xc99c, 0x21, 0 - .dw 0x13c0, 0xc99c, 0x13ff, 0xc99c, 0x21, 0 - .dw 0x1440, 0xc99c, 0x147f, 0xc99c, 0x21, 0 - .dw 0x14c0, 0xc99c, 0x14ff, 0xc99c, 0x21, 0 - .dw 0x1540, 0xc99c, 0x157f, 0xc99c, 0x21, 0 - .dw 0x15c0, 0xc99c, 0x15ff, 0xc99c, 0x21, 0 - .dw 0x1640, 0xc99c, 0x167f, 0xc99c, 0x21, 0 - .dw 0x16c0, 0xc99c, 0x16ff, 0xc99c, 0x21, 0 - .dw 0x1740, 0xc99c, 0x177f, 0xc99c, 0x21, 0 - .dw 0x17c0, 0xc99c, 0x17ff, 0xc99c, 0x21, 0 - .dw 0x1840, 0xc99c, 0x187f, 0xc99c, 0x21, 0 - .dw 0x18c0, 0xc99c, 0x18ff, 0xc99c, 0x21, 0 - .dw 0x1940, 0xc99c, 0x197f, 0xc99c, 0x21, 0 - .dw 0x19c0, 0xc99c, 0x1fff, 0xc99c, 0x21, 0 - .dw 0x2040, 0xc99c, 0x207f, 0xc99c, 0x21, 0 - .dw 0x20c0, 0xc99c, 0x20ff, 0xc99c, 0x21, 0 - .dw 0x2140, 0xc99c, 0x217f, 0xc99c, 0x21, 0 - .dw 0x21c0, 0xc99c, 0x21ff, 0xc99c, 0x21, 0 - .dw 0x2240, 0xc99c, 0x227f, 0xc99c, 0x21, 0 - .dw 0x22c0, 0xc99c, 0x22ff, 0xc99c, 0x21, 0 - .dw 0x2340, 0xc99c, 0x237f, 0xc99c, 0x21, 0 - .dw 0x23c0, 0xc99c, 0x23ff, 0xc99c, 0x21, 0 - .dw 0x2440, 0xc99c, 0x247f, 0xc99c, 0x21, 0 - .dw 0x24c0, 0xc99c, 0x24ff, 0xc99c, 0x21, 0 - .dw 0x2540, 0xc99c, 0x257f, 0xc99c, 0x21, 0 - .dw 0x25c0, 0xc99c, 0x25ff, 0xc99c, 0x21, 0 - .dw 0x2640, 0xc99c, 0x267f, 0xc99c, 0x21, 0 - .dw 0x26c0, 0xc99c, 0x26ff, 0xc99c, 0x21, 0 - .dw 0x2740, 0xc99c, 0x277f, 0xc99c, 0x21, 0 - .dw 0x27c0, 0xc99c, 0x27ff, 0xc99c, 0x21, 0 - .dw 0x2840, 0xc99c, 0x287f, 0xc99c, 0x21, 0 - .dw 0x28c0, 0xc99c, 0x28ff, 0xc99c, 0x21, 0 - .dw 0x2940, 0xc99c, 0x297f, 0xc99c, 0x21, 0 - .dw 0x29c0, 0xc99c, 0x29ff, 0xc99c, 0x21, 0 - .dw 0x2a40, 0xc99c, 0x2a7f, 0xc99c, 0x21, 0 - .dw 0x2ac0, 0xc99c, 0x2aff, 0xc99c, 0x21, 0 - .dw 0x2b40, 0xc99c, 0x2b7f, 0xc99c, 0x21, 0 - .dw 0x2bc0, 0xc99c, 0x2bff, 0xc99c, 0x21, 0 - .dw 0x2c40, 0xc99c, 0x2c7f, 0xc99c, 0x21, 0 - .dw 0x2cc0, 0xc99c, 0x2cff, 0xc99c, 0x21, 0 - .dw 0x2d40, 0xc99c, 0x2d7f, 0xc99c, 0x21, 0 - .dw 0x2dc0, 0xc99c, 0x2dff, 0xc99c, 0x21, 0 - .dw 0x2e40, 0xc99c, 0x2e7f, 0xc99c, 0x21, 0 - .dw 0x2ec0, 0xc99c, 0x2eff, 0xc99c, 0x21, 0 - .dw 0x2f40, 0xc99c, 0x2f7f, 0xc99c, 0x21, 0 - .dw 0x2fc0, 0xc99c, 0x2fff, 0xc99c, 0x21, 0 - .dw 0x3040, 0xc99c, 0x307f, 0xc99c, 0x21, 0 - .dw 0x30c0, 0xc99c, 0x30ff, 0xc99c, 0x21, 0 - .dw 0x3140, 0xc99c, 0x317f, 0xc99c, 0x21, 0 - .dw 0x31c0, 0xc99c, 0x31ff, 0xc99c, 0x21, 0 - .dw 0x3240, 0xc99c, 0x327f, 0xc99c, 0x21, 0 - .dw 0x32c0, 0xc99c, 0x32ff, 0xc99c, 0x21, 0 - .dw 0x3340, 0xc99c, 0x337f, 0xc99c, 0x21, 0 - .dw 0x33c0, 0xc99c, 0x33ff, 0xc99c, 0x21, 0 - .dw 0x3440, 0xc99c, 0x347f, 0xc99c, 0x21, 0 - .dw 0x34c0, 0xc99c, 0x34ff, 0xc99c, 0x21, 0 - .dw 0x3540, 0xc99c, 0x357f, 0xc99c, 0x21, 0 - .dw 0x35c0, 0xc99c, 0x35ff, 0xc99c, 0x21, 0 - .dw 0x3640, 0xc99c, 0x367f, 0xc99c, 0x21, 0 - .dw 0x36c0, 0xc99c, 0x36ff, 0xc99c, 0x21, 0 - .dw 0x3740, 0xc99c, 0x377f, 0xc99c, 0x21, 0 - .dw 0x37c0, 0xc99c, 0x37ff, 0xc99c, 0x21, 0 - .dw 0x3840, 0xc99c, 0x387f, 0xc99c, 0x21, 0 - .dw 0x38c0, 0xc99c, 0x38ff, 0xc99c, 0x21, 0 - .dw 0x3940, 0xc99c, 0x397f, 0xc99c, 0x21, 0 - .dw 0x39c0, 0xc99c, 0x3fff, 0xc99c, 0x21, 0 - .dw 0x4040, 0xc99c, 0x407f, 0xc99c, 0x21, 0 - .dw 0x40c0, 0xc99c, 0x40ff, 0xc99c, 0x21, 0 - .dw 0x4140, 0xc99c, 0x417f, 0xc99c, 0x21, 0 - .dw 0x41c0, 0xc99c, 0x41ff, 0xc99c, 0x21, 0 - .dw 0x4240, 0xc99c, 0x427f, 0xc99c, 0x21, 0 - .dw 0x42c0, 0xc99c, 0x42ff, 0xc99c, 0x21, 0 - .dw 0x4340, 0xc99c, 0x437f, 0xc99c, 0x21, 0 - .dw 0x43c0, 0xc99c, 0x43ff, 0xc99c, 0x21, 0 - .dw 0x4440, 0xc99c, 0x447f, 0xc99c, 0x21, 0 - .dw 0x44c0, 0xc99c, 0x44ff, 0xc99c, 0x21, 0 - .dw 0x4540, 0xc99c, 0x457f, 0xc99c, 0x21, 0 - .dw 0x45c0, 0xc99c, 0x45ff, 0xc99c, 0x21, 0 - .dw 0x4640, 0xc99c, 0x467f, 0xc99c, 0x21, 0 - .dw 0x46c0, 0xc99c, 0x46ff, 0xc99c, 0x21, 0 - .dw 0x4740, 0xc99c, 0x477f, 0xc99c, 0x21, 0 - .dw 0x47c0, 0xc99c, 0x47ff, 0xc99c, 0x21, 0 - .dw 0x4840, 0xc99c, 0x487f, 0xc99c, 0x21, 0 - .dw 0x48c0, 0xc99c, 0x48ff, 0xc99c, 0x21, 0 - .dw 0x4940, 0xc99c, 0x497f, 0xc99c, 0x21, 0 - .dw 0x49c0, 0xc99c, 0x49ff, 0xc99c, 0x21, 0 - .dw 0x4a40, 0xc99c, 0x4a7f, 0xc99c, 0x21, 0 - .dw 0x4ac0, 0xc99c, 0x4aff, 0xc99c, 0x21, 0 - .dw 0x4b40, 0xc99c, 0x4b7f, 0xc99c, 0x21, 0 - .dw 0x4bc0, 0xc99c, 0x4bff, 0xc99c, 0x21, 0 - .dw 0x4c40, 0xc99c, 0x4c7f, 0xc99c, 0x21, 0 - .dw 0x4cc0, 0xc99c, 0x4cff, 0xc99c, 0x21, 0 - .dw 0x4d40, 0xc99c, 0x4d7f, 0xc99c, 0x21, 0 - .dw 0x4dc0, 0xc99c, 0x4dff, 0xc99c, 0x21, 0 - .dw 0x4e40, 0xc99c, 0x4e7f, 0xc99c, 0x21, 0 - .dw 0x4ec0, 0xc99c, 0x4eff, 0xc99c, 0x21, 0 - .dw 0x4f40, 0xc99c, 0x4f7f, 0xc99c, 0x21, 0 - .dw 0x4fc0, 0xc99c, 0x4fff, 0xc99c, 0x21, 0 - .dw 0x5040, 0xc99c, 0x507f, 0xc99c, 0x21, 0 - .dw 0x50c0, 0xc99c, 0x50ff, 0xc99c, 0x21, 0 - .dw 0x5140, 0xc99c, 0x517f, 0xc99c, 0x21, 0 - .dw 0x51c0, 0xc99c, 0x51ff, 0xc99c, 0x21, 0 - .dw 0x5240, 0xc99c, 0x527f, 0xc99c, 0x21, 0 - .dw 0x52c0, 0xc99c, 0x52ff, 0xc99c, 0x21, 0 - .dw 0x5340, 0xc99c, 0x537f, 0xc99c, 0x21, 0 - .dw 0x53c0, 0xc99c, 0x53ff, 0xc99c, 0x21, 0 - .dw 0x5440, 0xc99c, 0x547f, 0xc99c, 0x21, 0 - .dw 0x54c0, 0xc99c, 0x54ff, 0xc99c, 0x21, 0 - .dw 0x5540, 0xc99c, 0x557f, 0xc99c, 0x21, 0 - .dw 0x55c0, 0xc99c, 0x55ff, 0xc99c, 0x21, 0 - .dw 0x5640, 0xc99c, 0x567f, 0xc99c, 0x21, 0 - .dw 0x56c0, 0xc99c, 0x56ff, 0xc99c, 0x21, 0 - .dw 0x5740, 0xc99c, 0x577f, 0xc99c, 0x21, 0 - .dw 0x57c0, 0xc99c, 0x57ff, 0xc99c, 0x21, 0 - .dw 0x5840, 0xc99c, 0x587f, 0xc99c, 0x21, 0 - .dw 0x58c0, 0xc99c, 0x58ff, 0xc99c, 0x21, 0 - .dw 0x5940, 0xc99c, 0x597f, 0xc99c, 0x21, 0 - .dw 0x59c0, 0xc99c, 0x5fff, 0xc99c, 0x21, 0 - .dw 0x6040, 0xc99c, 0x607f, 0xc99c, 0x21, 0 - .dw 0x60c0, 0xc99c, 0x60ff, 0xc99c, 0x21, 0 - .dw 0x6140, 0xc99c, 0x617f, 0xc99c, 0x21, 0 - .dw 0x61c0, 0xc99c, 0x61ff, 0xc99c, 0x21, 0 - .dw 0x6240, 0xc99c, 0x627f, 0xc99c, 0x21, 0 - .dw 0x62c0, 0xc99c, 0x62ff, 0xc99c, 0x21, 0 - .dw 0x6340, 0xc99c, 0x637f, 0xc99c, 0x21, 0 - .dw 0x63c0, 0xc99c, 0x63ff, 0xc99c, 0x21, 0 - .dw 0x6440, 0xc99c, 0x647f, 0xc99c, 0x21, 0 - .dw 0x64c0, 0xc99c, 0x64ff, 0xc99c, 0x21, 0 - .dw 0x6540, 0xc99c, 0x657f, 0xc99c, 0x21, 0 - .dw 0x65c0, 0xc99c, 0x65ff, 0xc99c, 0x21, 0 - .dw 0x6640, 0xc99c, 0x667f, 0xc99c, 0x21, 0 - .dw 0x66c0, 0xc99c, 0x66ff, 0xc99c, 0x21, 0 - .dw 0x6740, 0xc99c, 0x677f, 0xc99c, 0x21, 0 - .dw 0x67c0, 0xc99c, 0x67ff, 0xc99c, 0x21, 0 - .dw 0x6840, 0xc99c, 0x687f, 0xc99c, 0x21, 0 - .dw 0x68c0, 0xc99c, 0x68ff, 0xc99c, 0x21, 0 - .dw 0x6940, 0xc99c, 0x697f, 0xc99c, 0x21, 0 - .dw 0x69c0, 0xc99c, 0x69ff, 0xc99c, 0x21, 0 - .dw 0x6a40, 0xc99c, 0x6a7f, 0xc99c, 0x21, 0 - .dw 0x6ac0, 0xc99c, 0x6aff, 0xc99c, 0x21, 0 - .dw 0x6b40, 0xc99c, 0x6b7f, 0xc99c, 0x21, 0 - .dw 0x6bc0, 0xc99c, 0x6bff, 0xc99c, 0x21, 0 - .dw 0x6c40, 0xc99c, 0x6c7f, 0xc99c, 0x21, 0 - .dw 0x6cc0, 0xc99c, 0x6cff, 0xc99c, 0x21, 0 - .dw 0x6d40, 0xc99c, 0x6d7f, 0xc99c, 0x21, 0 - .dw 0x6dc0, 0xc99c, 0x6dff, 0xc99c, 0x21, 0 - .dw 0x6e40, 0xc99c, 0x6e7f, 0xc99c, 0x21, 0 - .dw 0x6ec0, 0xc99c, 0x6eff, 0xc99c, 0x21, 0 - .dw 0x6f40, 0xc99c, 0x6f7f, 0xc99c, 0x21, 0 - .dw 0x6fc0, 0xc99c, 0x6fff, 0xc99c, 0x21, 0 - .dw 0x7040, 0xc99c, 0x707f, 0xc99c, 0x21, 0 - .dw 0x70c0, 0xc99c, 0x70ff, 0xc99c, 0x21, 0 - .dw 0x7140, 0xc99c, 0x717f, 0xc99c, 0x21, 0 - .dw 0x71c0, 0xc99c, 0x71ff, 0xc99c, 0x21, 0 - .dw 0x7240, 0xc99c, 0x727f, 0xc99c, 0x21, 0 - .dw 0x72c0, 0xc99c, 0x72ff, 0xc99c, 0x21, 0 - .dw 0x7340, 0xc99c, 0x737f, 0xc99c, 0x21, 0 - .dw 0x73c0, 0xc99c, 0x73ff, 0xc99c, 0x21, 0 - .dw 0x7440, 0xc99c, 0x747f, 0xc99c, 0x21, 0 - .dw 0x74c0, 0xc99c, 0x74ff, 0xc99c, 0x21, 0 - .dw 0x7540, 0xc99c, 0x757f, 0xc99c, 0x21, 0 - .dw 0x75c0, 0xc99c, 0x75ff, 0xc99c, 0x21, 0 - .dw 0x7640, 0xc99c, 0x767f, 0xc99c, 0x21, 0 - .dw 0x76c0, 0xc99c, 0x76ff, 0xc99c, 0x21, 0 - .dw 0x7740, 0xc99c, 0x777f, 0xc99c, 0x21, 0 - .dw 0x77c0, 0xc99c, 0x77ff, 0xc99c, 0x21, 0 - .dw 0x7840, 0xc99c, 0x787f, 0xc99c, 0x21, 0 - .dw 0x78c0, 0xc99c, 0x78ff, 0xc99c, 0x21, 0 - .dw 0x7940, 0xc99c, 0x797f, 0xc99c, 0x21, 0 - .dw 0x79c0, 0xc99c, 0x7fff, 0xc99c, 0x21, 0 - .dw 0x8040, 0xc99c, 0x807f, 0xc99c, 0x21, 0 - .dw 0x80c0, 0xc99c, 0x80ff, 0xc99c, 0x21, 0 - .dw 0x8140, 0xc99c, 0x817f, 0xc99c, 0x21, 0 - .dw 0x81c0, 0xc99c, 0x81ff, 0xc99c, 0x21, 0 - .dw 0x8240, 0xc99c, 0x827f, 0xc99c, 0x21, 0 - .dw 0x82c0, 0xc99c, 0x82ff, 0xc99c, 0x21, 0 - .dw 0x8340, 0xc99c, 0x837f, 0xc99c, 0x21, 0 - .dw 0x83c0, 0xc99c, 0x83ff, 0xc99c, 0x21, 0 - .dw 0x8440, 0xc99c, 0x847f, 0xc99c, 0x21, 0 - .dw 0x84c0, 0xc99c, 0x84ff, 0xc99c, 0x21, 0 - .dw 0x8540, 0xc99c, 0x857f, 0xc99c, 0x21, 0 - .dw 0x85c0, 0xc99c, 0x85ff, 0xc99c, 0x21, 0 - .dw 0x8640, 0xc99c, 0x867f, 0xc99c, 0x21, 0 - .dw 0x86c0, 0xc99c, 0x86ff, 0xc99c, 0x21, 0 - .dw 0x8740, 0xc99c, 0x877f, 0xc99c, 0x21, 0 - .dw 0x87c0, 0xc99c, 0x87ff, 0xc99c, 0x21, 0 - .dw 0x8840, 0xc99c, 0x887f, 0xc99c, 0x21, 0 - .dw 0x88c0, 0xc99c, 0x88ff, 0xc99c, 0x21, 0 - .dw 0x8940, 0xc99c, 0x897f, 0xc99c, 0x21, 0 - .dw 0x89c0, 0xc99c, 0x89ff, 0xc99c, 0x21, 0 - .dw 0x8a40, 0xc99c, 0x8a7f, 0xc99c, 0x21, 0 - .dw 0x8ac0, 0xc99c, 0x8aff, 0xc99c, 0x21, 0 - .dw 0x8b40, 0xc99c, 0x8b7f, 0xc99c, 0x21, 0 - .dw 0x8bc0, 0xc99c, 0x8bff, 0xc99c, 0x21, 0 - .dw 0x8c40, 0xc99c, 0x8c7f, 0xc99c, 0x21, 0 - .dw 0x8cc0, 0xc99c, 0x8cff, 0xc99c, 0x21, 0 - .dw 0x8d40, 0xc99c, 0x8d7f, 0xc99c, 0x21, 0 - .dw 0x8dc0, 0xc99c, 0x8dff, 0xc99c, 0x21, 0 - .dw 0x8e40, 0xc99c, 0x8e7f, 0xc99c, 0x21, 0 - .dw 0x8ec0, 0xc99c, 0x8eff, 0xc99c, 0x21, 0 - .dw 0x8f40, 0xc99c, 0x8f7f, 0xc99c, 0x21, 0 - .dw 0x8fc0, 0xc99c, 0x8fff, 0xc99c, 0x21, 0 - .dw 0x9040, 0xc99c, 0x907f, 0xc99c, 0x21, 0 - .dw 0x90c0, 0xc99c, 0x90ff, 0xc99c, 0x21, 0 - .dw 0x9140, 0xc99c, 0x917f, 0xc99c, 0x21, 0 - .dw 0x91c0, 0xc99c, 0x91ff, 0xc99c, 0x21, 0 - .dw 0x9240, 0xc99c, 0x927f, 0xc99c, 0x21, 0 - .dw 0x92c0, 0xc99c, 0x92ff, 0xc99c, 0x21, 0 - .dw 0x9340, 0xc99c, 0x937f, 0xc99c, 0x21, 0 - .dw 0x93c0, 0xc99c, 0x93ff, 0xc99c, 0x21, 0 - .dw 0x9440, 0xc99c, 0x947f, 0xc99c, 0x21, 0 - .dw 0x94c0, 0xc99c, 0x94ff, 0xc99c, 0x21, 0 - .dw 0x9540, 0xc99c, 0x957f, 0xc99c, 0x21, 0 - .dw 0x95c0, 0xc99c, 0x95ff, 0xc99c, 0x21, 0 - .dw 0x9640, 0xc99c, 0x967f, 0xc99c, 0x21, 0 - .dw 0x96c0, 0xc99c, 0x96ff, 0xc99c, 0x21, 0 - .dw 0x9740, 0xc99c, 0x977f, 0xc99c, 0x21, 0 - .dw 0x97c0, 0xc99c, 0x97ff, 0xc99c, 0x21, 0 - .dw 0x9840, 0xc99c, 0x987f, 0xc99c, 0x21, 0 - .dw 0x98c0, 0xc99c, 0x98ff, 0xc99c, 0x21, 0 - .dw 0x9940, 0xc99c, 0x997f, 0xc99c, 0x21, 0 - .dw 0x99c0, 0xc99c, 0x9fff, 0xc99c, 0x21, 0 - .dw 0xa040, 0xc99c, 0xa07f, 0xc99c, 0x21, 0 - .dw 0xa0c0, 0xc99c, 0xa0ff, 0xc99c, 0x21, 0 - .dw 0xa140, 0xc99c, 0xa17f, 0xc99c, 0x21, 0 - .dw 0xa1c0, 0xc99c, 0xa1ff, 0xc99c, 0x21, 0 - .dw 0xa240, 0xc99c, 0xa27f, 0xc99c, 0x21, 0 - .dw 0xa2c0, 0xc99c, 0xa2ff, 0xc99c, 0x21, 0 - .dw 0xa340, 0xc99c, 0xa37f, 0xc99c, 0x21, 0 - .dw 0xa3c0, 0xc99c, 0xa3ff, 0xc99c, 0x21, 0 - .dw 0xa440, 0xc99c, 0xa47f, 0xc99c, 0x21, 0 - .dw 0xa4c0, 0xc99c, 0xa4ff, 0xc99c, 0x21, 0 - .dw 0xa540, 0xc99c, 0xa57f, 0xc99c, 0x21, 0 - .dw 0xa5c0, 0xc99c, 0xa5ff, 0xc99c, 0x21, 0 - .dw 0xa640, 0xc99c, 0xa67f, 0xc99c, 0x21, 0 - .dw 0xa6c0, 0xc99c, 0xa6ff, 0xc99c, 0x21, 0 - .dw 0xa740, 0xc99c, 0xa77f, 0xc99c, 0x21, 0 - .dw 0xa7c0, 0xc99c, 0xa7ff, 0xc99c, 0x21, 0 - .dw 0xa840, 0xc99c, 0xa87f, 0xc99c, 0x21, 0 - .dw 0xa8c0, 0xc99c, 0xa8ff, 0xc99c, 0x21, 0 - .dw 0xa940, 0xc99c, 0xa97f, 0xc99c, 0x21, 0 - .dw 0xa9c0, 0xc99c, 0xa9ff, 0xc99c, 0x21, 0 - .dw 0xaa40, 0xc99c, 0xaa7f, 0xc99c, 0x21, 0 - .dw 0xaac0, 0xc99c, 0xaaff, 0xc99c, 0x21, 0 - .dw 0xab40, 0xc99c, 0xab7f, 0xc99c, 0x21, 0 - .dw 0xabc0, 0xc99c, 0xabff, 0xc99c, 0x21, 0 - .dw 0xac40, 0xc99c, 0xac7f, 0xc99c, 0x21, 0 - .dw 0xacc0, 0xc99c, 0xacff, 0xc99c, 0x21, 0 - .dw 0xad40, 0xc99c, 0xad7f, 0xc99c, 0x21, 0 - .dw 0xadc0, 0xc99c, 0xadff, 0xc99c, 0x21, 0 - .dw 0xae40, 0xc99c, 0xae7f, 0xc99c, 0x21, 0 - .dw 0xaec0, 0xc99c, 0xaeff, 0xc99c, 0x21, 0 - .dw 0xaf40, 0xc99c, 0xaf7f, 0xc99c, 0x21, 0 - .dw 0xafc0, 0xc99c, 0xafff, 0xc99c, 0x21, 0 - .dw 0xb040, 0xc99c, 0xb07f, 0xc99c, 0x21, 0 - .dw 0xb0c0, 0xc99c, 0xb0ff, 0xc99c, 0x21, 0 - .dw 0xb140, 0xc99c, 0xb17f, 0xc99c, 0x21, 0 - .dw 0xb1c0, 0xc99c, 0xb1ff, 0xc99c, 0x21, 0 - .dw 0xb240, 0xc99c, 0xb27f, 0xc99c, 0x21, 0 - .dw 0xb2c0, 0xc99c, 0xb2ff, 0xc99c, 0x21, 0 - .dw 0xb340, 0xc99c, 0xb37f, 0xc99c, 0x21, 0 - .dw 0xb3c0, 0xc99c, 0xb3ff, 0xc99c, 0x21, 0 - .dw 0xb440, 0xc99c, 0xb47f, 0xc99c, 0x21, 0 - .dw 0xb4c0, 0xc99c, 0xb4ff, 0xc99c, 0x21, 0 - .dw 0xb540, 0xc99c, 0xb57f, 0xc99c, 0x21, 0 - .dw 0xb5c0, 0xc99c, 0xb5ff, 0xc99c, 0x21, 0 - .dw 0xb640, 0xc99c, 0xb67f, 0xc99c, 0x21, 0 - .dw 0xb6c0, 0xc99c, 0xb6ff, 0xc99c, 0x21, 0 - .dw 0xb740, 0xc99c, 0xb77f, 0xc99c, 0x21, 0 - .dw 0xb7c0, 0xc99c, 0xb7ff, 0xc99c, 0x21, 0 - .dw 0xb840, 0xc99c, 0xb87f, 0xc99c, 0x21, 0 - .dw 0xb8c0, 0xc99c, 0xb8ff, 0xc99c, 0x21, 0 - .dw 0xb940, 0xc99c, 0xb97f, 0xc99c, 0x21, 0 - .dw 0xb9c0, 0xc99c, 0xbfff, 0xc99c, 0x21, 0 - .dw 0xc040, 0xc99c, 0xc07f, 0xc99c, 0x21, 0 - .dw 0xc0c0, 0xc99c, 0xc0ff, 0xc99c, 0x21, 0 - .dw 0xc140, 0xc99c, 0xc17f, 0xc99c, 0x21, 0 - .dw 0xc1c0, 0xc99c, 0xc1ff, 0xc99c, 0x21, 0 - .dw 0xc240, 0xc99c, 0xc27f, 0xc99c, 0x21, 0 - .dw 0xc2c0, 0xc99c, 0xc2ff, 0xc99c, 0x21, 0 - .dw 0xc340, 0xc99c, 0xc37f, 0xc99c, 0x21, 0 - .dw 0xc3c0, 0xc99c, 0xc3ff, 0xc99c, 0x21, 0 - .dw 0xc440, 0xc99c, 0xc47f, 0xc99c, 0x21, 0 - .dw 0xc4c0, 0xc99c, 0xc4ff, 0xc99c, 0x21, 0 - .dw 0xc540, 0xc99c, 0xc57f, 0xc99c, 0x21, 0 - .dw 0xc5c0, 0xc99c, 0xc5ff, 0xc99c, 0x21, 0 - .dw 0xc640, 0xc99c, 0xc67f, 0xc99c, 0x21, 0 - .dw 0xc6c0, 0xc99c, 0xc6ff, 0xc99c, 0x21, 0 - .dw 0xc740, 0xc99c, 0xc77f, 0xc99c, 0x21, 0 - .dw 0xc7c0, 0xc99c, 0xc7ff, 0xc99c, 0x21, 0 - .dw 0xc840, 0xc99c, 0xc87f, 0xc99c, 0x21, 0 - .dw 0xc8c0, 0xc99c, 0xc8ff, 0xc99c, 0x21, 0 - .dw 0xc940, 0xc99c, 0xc97f, 0xc99c, 0x21, 0 - .dw 0xc9c0, 0xc99c, 0xc9ff, 0xc99c, 0x21, 0 - .dw 0xca40, 0xc99c, 0xca7f, 0xc99c, 0x21, 0 - .dw 0xcac0, 0xc99c, 0xcaff, 0xc99c, 0x21, 0 - .dw 0xcb40, 0xc99c, 0xcb7f, 0xc99c, 0x21, 0 - .dw 0xcbc0, 0xc99c, 0xcbff, 0xc99c, 0x21, 0 - .dw 0xcc40, 0xc99c, 0xcc7f, 0xc99c, 0x21, 0 - .dw 0xccc0, 0xc99c, 0xccff, 0xc99c, 0x21, 0 - .dw 0xcd40, 0xc99c, 0xcd7f, 0xc99c, 0x21, 0 - .dw 0xcdc0, 0xc99c, 0xcdff, 0xc99c, 0x21, 0 - .dw 0xce40, 0xc99c, 0xce7f, 0xc99c, 0x21, 0 - .dw 0xcec0, 0xc99c, 0xceff, 0xc99c, 0x21, 0 - .dw 0xcf40, 0xc99c, 0xcf7f, 0xc99c, 0x21, 0 - .dw 0xcfc0, 0xc99c, 0xcfff, 0xc99c, 0x21, 0 - .dw 0xd040, 0xc99c, 0xd07f, 0xc99c, 0x21, 0 - .dw 0xd0c0, 0xc99c, 0xd0ff, 0xc99c, 0x21, 0 - .dw 0xd140, 0xc99c, 0xd17f, 0xc99c, 0x21, 0 - .dw 0xd1c0, 0xc99c, 0xd1ff, 0xc99c, 0x21, 0 - .dw 0xd240, 0xc99c, 0xd27f, 0xc99c, 0x21, 0 - .dw 0xd2c0, 0xc99c, 0xd2ff, 0xc99c, 0x21, 0 - .dw 0xd340, 0xc99c, 0xd37f, 0xc99c, 0x21, 0 - .dw 0xd3c0, 0xc99c, 0xd3ff, 0xc99c, 0x21, 0 - .dw 0xd440, 0xc99c, 0xd47f, 0xc99c, 0x21, 0 - .dw 0xd4c0, 0xc99c, 0xd4ff, 0xc99c, 0x21, 0 - .dw 0xd540, 0xc99c, 0xd57f, 0xc99c, 0x21, 0 - .dw 0xd5c0, 0xc99c, 0xd5ff, 0xc99c, 0x21, 0 - .dw 0xd640, 0xc99c, 0xd67f, 0xc99c, 0x21, 0 - .dw 0xd6c0, 0xc99c, 0xd6ff, 0xc99c, 0x21, 0 - .dw 0xd740, 0xc99c, 0xd77f, 0xc99c, 0x21, 0 - .dw 0xd7c0, 0xc99c, 0xd7ff, 0xc99c, 0x21, 0 - .dw 0xd840, 0xc99c, 0xd87f, 0xc99c, 0x21, 0 - .dw 0xd8c0, 0xc99c, 0xd8ff, 0xc99c, 0x21, 0 - .dw 0xd940, 0xc99c, 0xd97f, 0xc99c, 0x21, 0 - .dw 0xd9c0, 0xc99c, 0xdfff, 0xc99c, 0x21, 0 - .dw 0xe040, 0xc99c, 0xe07f, 0xc99c, 0x21, 0 - .dw 0xe0c0, 0xc99c, 0xe0ff, 0xc99c, 0x21, 0 - .dw 0xe140, 0xc99c, 0xe17f, 0xc99c, 0x21, 0 - .dw 0xe1c0, 0xc99c, 0xe1ff, 0xc99c, 0x21, 0 - .dw 0xe240, 0xc99c, 0xe27f, 0xc99c, 0x21, 0 - .dw 0xe2c0, 0xc99c, 0xe2ff, 0xc99c, 0x21, 0 - .dw 0xe340, 0xc99c, 0xe37f, 0xc99c, 0x21, 0 - .dw 0xe3c0, 0xc99c, 0xe3ff, 0xc99c, 0x21, 0 - .dw 0xe440, 0xc99c, 0xe47f, 0xc99c, 0x21, 0 - .dw 0xe4c0, 0xc99c, 0xe4ff, 0xc99c, 0x21, 0 - .dw 0xe540, 0xc99c, 0xe57f, 0xc99c, 0x21, 0 - .dw 0xe5c0, 0xc99c, 0xe5ff, 0xc99c, 0x21, 0 - .dw 0xe640, 0xc99c, 0xe67f, 0xc99c, 0x21, 0 - .dw 0xe6c0, 0xc99c, 0xe6ff, 0xc99c, 0x21, 0 - .dw 0xe740, 0xc99c, 0xe77f, 0xc99c, 0x21, 0 - .dw 0xe7c0, 0xc99c, 0xe7ff, 0xc99c, 0x21, 0 - .dw 0xe840, 0xc99c, 0xe87f, 0xc99c, 0x21, 0 - .dw 0xe8c0, 0xc99c, 0xe8ff, 0xc99c, 0x21, 0 - .dw 0xe940, 0xc99c, 0xe97f, 0xc99c, 0x21, 0 - .dw 0xe9c0, 0xc99c, 0xe9ff, 0xc99c, 0x21, 0 - .dw 0xea40, 0xc99c, 0xea7f, 0xc99c, 0x21, 0 - .dw 0xeac0, 0xc99c, 0xeaff, 0xc99c, 0x21, 0 - .dw 0xeb40, 0xc99c, 0xeb7f, 0xc99c, 0x21, 0 - .dw 0xebc0, 0xc99c, 0xebff, 0xc99c, 0x21, 0 - .dw 0xec40, 0xc99c, 0xec7f, 0xc99c, 0x21, 0 - .dw 0xecc0, 0xc99c, 0xecff, 0xc99c, 0x21, 0 - .dw 0xed40, 0xc99c, 0xed7f, 0xc99c, 0x21, 0 - .dw 0xedc0, 0xc99c, 0xedff, 0xc99c, 0x21, 0 - .dw 0xee40, 0xc99c, 0xee7f, 0xc99c, 0x21, 0 - .dw 0xeec0, 0xc99c, 0xeeff, 0xc99c, 0x21, 0 - .dw 0xef40, 0xc99c, 0xef7f, 0xc99c, 0x21, 0 - .dw 0xefc0, 0xc99c, 0xefff, 0xc99c, 0x21, 0 - .dw 0xf040, 0xc99c, 0xf07f, 0xc99c, 0x21, 0 - .dw 0xf0c0, 0xc99c, 0xf0ff, 0xc99c, 0x21, 0 - .dw 0xf140, 0xc99c, 0xf17f, 0xc99c, 0x21, 0 - .dw 0xf1c0, 0xc99c, 0xf1ff, 0xc99c, 0x21, 0 - .dw 0xf240, 0xc99c, 0xf27f, 0xc99c, 0x21, 0 - .dw 0xf2c0, 0xc99c, 0xf2ff, 0xc99c, 0x21, 0 - .dw 0xf340, 0xc99c, 0xf37f, 0xc99c, 0x21, 0 - .dw 0xf3c0, 0xc99c, 0xf3ff, 0xc99c, 0x21, 0 - .dw 0xf440, 0xc99c, 0xf47f, 0xc99c, 0x21, 0 - .dw 0xf4c0, 0xc99c, 0xf4ff, 0xc99c, 0x21, 0 - .dw 0xf540, 0xc99c, 0xf57f, 0xc99c, 0x21, 0 - .dw 0xf5c0, 0xc99c, 0xf5ff, 0xc99c, 0x21, 0 - .dw 0xf640, 0xc99c, 0xf67f, 0xc99c, 0x21, 0 - .dw 0xf6c0, 0xc99c, 0xf6ff, 0xc99c, 0x21, 0 - .dw 0xf740, 0xc99c, 0xf77f, 0xc99c, 0x21, 0 - .dw 0xf7c0, 0xc99c, 0xf7ff, 0xc99c, 0x21, 0 - .dw 0xf840, 0xc99c, 0xf87f, 0xc99c, 0x21, 0 - .dw 0xf8c0, 0xc99c, 0xf8ff, 0xc99c, 0x21, 0 - .dw 0xf940, 0xc99c, 0xf97f, 0xc99c, 0x21, 0 - .dw 0xf9c0, 0xc99c, 0xffff, 0xc99c, 0x21, 0 - .dw 0x0040, 0xc99d, 0x007f, 0xc99d, 0x21, 0 - .dw 0x00c0, 0xc99d, 0x00ff, 0xc99d, 0x21, 0 - .dw 0x0140, 0xc99d, 0x017f, 0xc99d, 0x21, 0 - .dw 0x01c0, 0xc99d, 0x01ff, 0xc99d, 0x21, 0 - .dw 0x0240, 0xc99d, 0x027f, 0xc99d, 0x21, 0 - .dw 0x02c0, 0xc99d, 0x02ff, 0xc99d, 0x21, 0 - .dw 0x0340, 0xc99d, 0x037f, 0xc99d, 0x21, 0 - .dw 0x03c0, 0xc99d, 0x03ff, 0xc99d, 0x21, 0 - .dw 0x0440, 0xc99d, 0x047f, 0xc99d, 0x21, 0 - .dw 0x04c0, 0xc99d, 0x04ff, 0xc99d, 0x21, 0 - .dw 0x0540, 0xc99d, 0x057f, 0xc99d, 0x21, 0 - .dw 0x05c0, 0xc99d, 0x05ff, 0xc99d, 0x21, 0 - .dw 0x0640, 0xc99d, 0x067f, 0xc99d, 0x21, 0 - .dw 0x06c0, 0xc99d, 0x06ff, 0xc99d, 0x21, 0 - .dw 0x0740, 0xc99d, 0x077f, 0xc99d, 0x21, 0 - .dw 0x07c0, 0xc99d, 0x07ff, 0xc99d, 0x21, 0 - .dw 0x0840, 0xc99d, 0x087f, 0xc99d, 0x21, 0 - .dw 0x08c0, 0xc99d, 0x08ff, 0xc99d, 0x21, 0 - .dw 0x0940, 0xc99d, 0x097f, 0xc99d, 0x21, 0 - .dw 0x09c0, 0xc99d, 0x09ff, 0xc99d, 0x21, 0 - .dw 0x0a40, 0xc99d, 0x0a7f, 0xc99d, 0x21, 0 - .dw 0x0ac0, 0xc99d, 0x0aff, 0xc99d, 0x21, 0 - .dw 0x0b40, 0xc99d, 0x0b7f, 0xc99d, 0x21, 0 - .dw 0x0bc0, 0xc99d, 0x0bff, 0xc99d, 0x21, 0 - .dw 0x0c40, 0xc99d, 0x0c7f, 0xc99d, 0x21, 0 - .dw 0x0cc0, 0xc99d, 0x0cff, 0xc99d, 0x21, 0 - .dw 0x0d40, 0xc99d, 0x0d7f, 0xc99d, 0x21, 0 - .dw 0x0dc0, 0xc99d, 0x0dff, 0xc99d, 0x21, 0 - .dw 0x0e40, 0xc99d, 0x0e7f, 0xc99d, 0x21, 0 - .dw 0x0ec0, 0xc99d, 0x0eff, 0xc99d, 0x21, 0 - .dw 0x0f40, 0xc99d, 0x0f7f, 0xc99d, 0x21, 0 - .dw 0x0fc0, 0xc99d, 0x0fff, 0xc99d, 0x21, 0 - .dw 0x1040, 0xc99d, 0x107f, 0xc99d, 0x21, 0 - .dw 0x10c0, 0xc99d, 0x10ff, 0xc99d, 0x21, 0 - .dw 0x1140, 0xc99d, 0x117f, 0xc99d, 0x21, 0 - .dw 0x11c0, 0xc99d, 0x11ff, 0xc99d, 0x21, 0 - .dw 0x1240, 0xc99d, 0x127f, 0xc99d, 0x21, 0 - .dw 0x12c0, 0xc99d, 0x12ff, 0xc99d, 0x21, 0 - .dw 0x1340, 0xc99d, 0x137f, 0xc99d, 0x21, 0 - .dw 0x13c0, 0xc99d, 0x13ff, 0xc99d, 0x21, 0 - .dw 0x1440, 0xc99d, 0x147f, 0xc99d, 0x21, 0 - .dw 0x14c0, 0xc99d, 0x14ff, 0xc99d, 0x21, 0 - .dw 0x1540, 0xc99d, 0x157f, 0xc99d, 0x21, 0 - .dw 0x15c0, 0xc99d, 0x15ff, 0xc99d, 0x21, 0 - .dw 0x1640, 0xc99d, 0x167f, 0xc99d, 0x21, 0 - .dw 0x16c0, 0xc99d, 0x16ff, 0xc99d, 0x21, 0 - .dw 0x1740, 0xc99d, 0x177f, 0xc99d, 0x21, 0 - .dw 0x17c0, 0xc99d, 0x17ff, 0xc99d, 0x21, 0 - .dw 0x1840, 0xc99d, 0x187f, 0xc99d, 0x21, 0 - .dw 0x18c0, 0xc99d, 0x18ff, 0xc99d, 0x21, 0 - .dw 0x1940, 0xc99d, 0x197f, 0xc99d, 0x21, 0 - .dw 0x19c0, 0xc99d, 0x1fff, 0xc99d, 0x21, 0 - .dw 0x2040, 0xc99d, 0x207f, 0xc99d, 0x21, 0 - .dw 0x20c0, 0xc99d, 0x20ff, 0xc99d, 0x21, 0 - .dw 0x2140, 0xc99d, 0x217f, 0xc99d, 0x21, 0 - .dw 0x21c0, 0xc99d, 0x21ff, 0xc99d, 0x21, 0 - .dw 0x2240, 0xc99d, 0x227f, 0xc99d, 0x21, 0 - .dw 0x22c0, 0xc99d, 0x22ff, 0xc99d, 0x21, 0 - .dw 0x2340, 0xc99d, 0x237f, 0xc99d, 0x21, 0 - .dw 0x23c0, 0xc99d, 0x23ff, 0xc99d, 0x21, 0 - .dw 0x2440, 0xc99d, 0x247f, 0xc99d, 0x21, 0 - .dw 0x24c0, 0xc99d, 0x24ff, 0xc99d, 0x21, 0 - .dw 0x2540, 0xc99d, 0x257f, 0xc99d, 0x21, 0 - .dw 0x25c0, 0xc99d, 0x25ff, 0xc99d, 0x21, 0 - .dw 0x2640, 0xc99d, 0x267f, 0xc99d, 0x21, 0 - .dw 0x26c0, 0xc99d, 0x26ff, 0xc99d, 0x21, 0 - .dw 0x2740, 0xc99d, 0x277f, 0xc99d, 0x21, 0 - .dw 0x27c0, 0xc99d, 0x27ff, 0xc99d, 0x21, 0 - .dw 0x2840, 0xc99d, 0x287f, 0xc99d, 0x21, 0 - .dw 0x28c0, 0xc99d, 0x28ff, 0xc99d, 0x21, 0 - .dw 0x2940, 0xc99d, 0x297f, 0xc99d, 0x21, 0 - .dw 0x29c0, 0xc99d, 0x29ff, 0xc99d, 0x21, 0 - .dw 0x2a40, 0xc99d, 0x2a7f, 0xc99d, 0x21, 0 - .dw 0x2ac0, 0xc99d, 0x2aff, 0xc99d, 0x21, 0 - .dw 0x2b40, 0xc99d, 0x2b7f, 0xc99d, 0x21, 0 - .dw 0x2bc0, 0xc99d, 0x2bff, 0xc99d, 0x21, 0 - .dw 0x2c40, 0xc99d, 0x2c7f, 0xc99d, 0x21, 0 - .dw 0x2cc0, 0xc99d, 0x2cff, 0xc99d, 0x21, 0 - .dw 0x2d40, 0xc99d, 0x2d7f, 0xc99d, 0x21, 0 - .dw 0x2dc0, 0xc99d, 0x2dff, 0xc99d, 0x21, 0 - .dw 0x2e40, 0xc99d, 0x2e7f, 0xc99d, 0x21, 0 - .dw 0x2ec0, 0xc99d, 0x2eff, 0xc99d, 0x21, 0 - .dw 0x2f40, 0xc99d, 0x2f7f, 0xc99d, 0x21, 0 - .dw 0x2fc0, 0xc99d, 0x2fff, 0xc99d, 0x21, 0 - .dw 0x3040, 0xc99d, 0x307f, 0xc99d, 0x21, 0 - .dw 0x30c0, 0xc99d, 0x30ff, 0xc99d, 0x21, 0 - .dw 0x3140, 0xc99d, 0x317f, 0xc99d, 0x21, 0 - .dw 0x31c0, 0xc99d, 0x31ff, 0xc99d, 0x21, 0 - .dw 0x3240, 0xc99d, 0x327f, 0xc99d, 0x21, 0 - .dw 0x32c0, 0xc99d, 0x32ff, 0xc99d, 0x21, 0 - .dw 0x3340, 0xc99d, 0x337f, 0xc99d, 0x21, 0 - .dw 0x33c0, 0xc99d, 0x33ff, 0xc99d, 0x21, 0 - .dw 0x3440, 0xc99d, 0x347f, 0xc99d, 0x21, 0 - .dw 0x34c0, 0xc99d, 0x34ff, 0xc99d, 0x21, 0 - .dw 0x3540, 0xc99d, 0x357f, 0xc99d, 0x21, 0 - .dw 0x35c0, 0xc99d, 0x35ff, 0xc99d, 0x21, 0 - .dw 0x3640, 0xc99d, 0x367f, 0xc99d, 0x21, 0 - .dw 0x36c0, 0xc99d, 0x36ff, 0xc99d, 0x21, 0 - .dw 0x3740, 0xc99d, 0x377f, 0xc99d, 0x21, 0 - .dw 0x37c0, 0xc99d, 0x37ff, 0xc99d, 0x21, 0 - .dw 0x3840, 0xc99d, 0x387f, 0xc99d, 0x21, 0 - .dw 0x38c0, 0xc99d, 0x38ff, 0xc99d, 0x21, 0 - .dw 0x3940, 0xc99d, 0x397f, 0xc99d, 0x21, 0 - .dw 0x39c0, 0xc99d, 0x3fff, 0xc99d, 0x21, 0 - .dw 0x4040, 0xc99d, 0x407f, 0xc99d, 0x21, 0 - .dw 0x40c0, 0xc99d, 0x40ff, 0xc99d, 0x21, 0 - .dw 0x4140, 0xc99d, 0x417f, 0xc99d, 0x21, 0 - .dw 0x41c0, 0xc99d, 0x41ff, 0xc99d, 0x21, 0 - .dw 0x4240, 0xc99d, 0x427f, 0xc99d, 0x21, 0 - .dw 0x42c0, 0xc99d, 0x42ff, 0xc99d, 0x21, 0 - .dw 0x4340, 0xc99d, 0x437f, 0xc99d, 0x21, 0 - .dw 0x43c0, 0xc99d, 0x43ff, 0xc99d, 0x21, 0 - .dw 0x4440, 0xc99d, 0x447f, 0xc99d, 0x21, 0 - .dw 0x44c0, 0xc99d, 0x44ff, 0xc99d, 0x21, 0 - .dw 0x4540, 0xc99d, 0x457f, 0xc99d, 0x21, 0 - .dw 0x45c0, 0xc99d, 0x45ff, 0xc99d, 0x21, 0 - .dw 0x4640, 0xc99d, 0x467f, 0xc99d, 0x21, 0 - .dw 0x46c0, 0xc99d, 0x46ff, 0xc99d, 0x21, 0 - .dw 0x4740, 0xc99d, 0x477f, 0xc99d, 0x21, 0 - .dw 0x47c0, 0xc99d, 0x47ff, 0xc99d, 0x21, 0 - .dw 0x4840, 0xc99d, 0x487f, 0xc99d, 0x21, 0 - .dw 0x48c0, 0xc99d, 0x48ff, 0xc99d, 0x21, 0 - .dw 0x4940, 0xc99d, 0x497f, 0xc99d, 0x21, 0 - .dw 0x49c0, 0xc99d, 0x49ff, 0xc99d, 0x21, 0 - .dw 0x4a40, 0xc99d, 0x4a7f, 0xc99d, 0x21, 0 - .dw 0x4ac0, 0xc99d, 0x4aff, 0xc99d, 0x21, 0 - .dw 0x4b40, 0xc99d, 0x4b7f, 0xc99d, 0x21, 0 - .dw 0x4bc0, 0xc99d, 0x4bff, 0xc99d, 0x21, 0 - .dw 0x4c40, 0xc99d, 0x4c7f, 0xc99d, 0x21, 0 - .dw 0x4cc0, 0xc99d, 0x4cff, 0xc99d, 0x21, 0 - .dw 0x4d40, 0xc99d, 0x4d7f, 0xc99d, 0x21, 0 - .dw 0x4dc0, 0xc99d, 0x4dff, 0xc99d, 0x21, 0 - .dw 0x4e40, 0xc99d, 0x4e7f, 0xc99d, 0x21, 0 - .dw 0x4ec0, 0xc99d, 0x4eff, 0xc99d, 0x21, 0 - .dw 0x4f40, 0xc99d, 0x4f7f, 0xc99d, 0x21, 0 - .dw 0x4fc0, 0xc99d, 0x4fff, 0xc99d, 0x21, 0 - .dw 0x5040, 0xc99d, 0x507f, 0xc99d, 0x21, 0 - .dw 0x50c0, 0xc99d, 0x50ff, 0xc99d, 0x21, 0 - .dw 0x5140, 0xc99d, 0x517f, 0xc99d, 0x21, 0 - .dw 0x51c0, 0xc99d, 0x51ff, 0xc99d, 0x21, 0 - .dw 0x5240, 0xc99d, 0x527f, 0xc99d, 0x21, 0 - .dw 0x52c0, 0xc99d, 0x52ff, 0xc99d, 0x21, 0 - .dw 0x5340, 0xc99d, 0x537f, 0xc99d, 0x21, 0 - .dw 0x53c0, 0xc99d, 0x53ff, 0xc99d, 0x21, 0 - .dw 0x5440, 0xc99d, 0x547f, 0xc99d, 0x21, 0 - .dw 0x54c0, 0xc99d, 0x54ff, 0xc99d, 0x21, 0 - .dw 0x5540, 0xc99d, 0x557f, 0xc99d, 0x21, 0 - .dw 0x55c0, 0xc99d, 0x55ff, 0xc99d, 0x21, 0 - .dw 0x5640, 0xc99d, 0x567f, 0xc99d, 0x21, 0 - .dw 0x56c0, 0xc99d, 0x56ff, 0xc99d, 0x21, 0 - .dw 0x5740, 0xc99d, 0x577f, 0xc99d, 0x21, 0 - .dw 0x57c0, 0xc99d, 0x57ff, 0xc99d, 0x21, 0 - .dw 0x5840, 0xc99d, 0x587f, 0xc99d, 0x21, 0 - .dw 0x58c0, 0xc99d, 0x58ff, 0xc99d, 0x21, 0 - .dw 0x5940, 0xc99d, 0x597f, 0xc99d, 0x21, 0 - .dw 0x59c0, 0xc99d, 0x5fff, 0xc99d, 0x21, 0 - .dw 0x6040, 0xc99d, 0x607f, 0xc99d, 0x21, 0 - .dw 0x60c0, 0xc99d, 0x60ff, 0xc99d, 0x21, 0 - .dw 0x6140, 0xc99d, 0x617f, 0xc99d, 0x21, 0 - .dw 0x61c0, 0xc99d, 0x61ff, 0xc99d, 0x21, 0 - .dw 0x6240, 0xc99d, 0x627f, 0xc99d, 0x21, 0 - .dw 0x62c0, 0xc99d, 0x62ff, 0xc99d, 0x21, 0 - .dw 0x6340, 0xc99d, 0x637f, 0xc99d, 0x21, 0 - .dw 0x63c0, 0xc99d, 0x63ff, 0xc99d, 0x21, 0 - .dw 0x6440, 0xc99d, 0x647f, 0xc99d, 0x21, 0 - .dw 0x64c0, 0xc99d, 0x64ff, 0xc99d, 0x21, 0 - .dw 0x6540, 0xc99d, 0x657f, 0xc99d, 0x21, 0 - .dw 0x65c0, 0xc99d, 0x65ff, 0xc99d, 0x21, 0 - .dw 0x6640, 0xc99d, 0x667f, 0xc99d, 0x21, 0 - .dw 0x66c0, 0xc99d, 0x66ff, 0xc99d, 0x21, 0 - .dw 0x6740, 0xc99d, 0x677f, 0xc99d, 0x21, 0 - .dw 0x67c0, 0xc99d, 0x67ff, 0xc99d, 0x21, 0 - .dw 0x6840, 0xc99d, 0x687f, 0xc99d, 0x21, 0 - .dw 0x68c0, 0xc99d, 0x68ff, 0xc99d, 0x21, 0 - .dw 0x6940, 0xc99d, 0x697f, 0xc99d, 0x21, 0 - .dw 0x69c0, 0xc99d, 0x69ff, 0xc99d, 0x21, 0 - .dw 0x6a40, 0xc99d, 0x6a7f, 0xc99d, 0x21, 0 - .dw 0x6ac0, 0xc99d, 0x6aff, 0xc99d, 0x21, 0 - .dw 0x6b40, 0xc99d, 0x6b7f, 0xc99d, 0x21, 0 - .dw 0x6bc0, 0xc99d, 0x6bff, 0xc99d, 0x21, 0 - .dw 0x6c40, 0xc99d, 0x6c7f, 0xc99d, 0x21, 0 - .dw 0x6cc0, 0xc99d, 0x6cff, 0xc99d, 0x21, 0 - .dw 0x6d40, 0xc99d, 0x6d7f, 0xc99d, 0x21, 0 - .dw 0x6dc0, 0xc99d, 0x6dff, 0xc99d, 0x21, 0 - .dw 0x6e40, 0xc99d, 0x6e7f, 0xc99d, 0x21, 0 - .dw 0x6ec0, 0xc99d, 0x6eff, 0xc99d, 0x21, 0 - .dw 0x6f40, 0xc99d, 0x6f7f, 0xc99d, 0x21, 0 - .dw 0x6fc0, 0xc99d, 0x6fff, 0xc99d, 0x21, 0 - .dw 0x7040, 0xc99d, 0x707f, 0xc99d, 0x21, 0 - .dw 0x70c0, 0xc99d, 0x70ff, 0xc99d, 0x21, 0 - .dw 0x7140, 0xc99d, 0x717f, 0xc99d, 0x21, 0 - .dw 0x71c0, 0xc99d, 0x71ff, 0xc99d, 0x21, 0 - .dw 0x7240, 0xc99d, 0x727f, 0xc99d, 0x21, 0 - .dw 0x72c0, 0xc99d, 0x72ff, 0xc99d, 0x21, 0 - .dw 0x7340, 0xc99d, 0x737f, 0xc99d, 0x21, 0 - .dw 0x73c0, 0xc99d, 0x73ff, 0xc99d, 0x21, 0 - .dw 0x7440, 0xc99d, 0x747f, 0xc99d, 0x21, 0 - .dw 0x74c0, 0xc99d, 0x74ff, 0xc99d, 0x21, 0 - .dw 0x7540, 0xc99d, 0x757f, 0xc99d, 0x21, 0 - .dw 0x75c0, 0xc99d, 0x75ff, 0xc99d, 0x21, 0 - .dw 0x7640, 0xc99d, 0x767f, 0xc99d, 0x21, 0 - .dw 0x76c0, 0xc99d, 0x76ff, 0xc99d, 0x21, 0 - .dw 0x7740, 0xc99d, 0x777f, 0xc99d, 0x21, 0 - .dw 0x77c0, 0xc99d, 0x77ff, 0xc99d, 0x21, 0 - .dw 0x7840, 0xc99d, 0x787f, 0xc99d, 0x21, 0 - .dw 0x78c0, 0xc99d, 0x78ff, 0xc99d, 0x21, 0 - .dw 0x7940, 0xc99d, 0x797f, 0xc99d, 0x21, 0 - .dw 0x79c0, 0xc99d, 0x7fff, 0xc99d, 0x21, 0 - .dw 0x8040, 0xc99d, 0x807f, 0xc99d, 0x21, 0 - .dw 0x80c0, 0xc99d, 0x80ff, 0xc99d, 0x21, 0 - .dw 0x8140, 0xc99d, 0x817f, 0xc99d, 0x21, 0 - .dw 0x81c0, 0xc99d, 0x81ff, 0xc99d, 0x21, 0 - .dw 0x8240, 0xc99d, 0x827f, 0xc99d, 0x21, 0 - .dw 0x82c0, 0xc99d, 0x82ff, 0xc99d, 0x21, 0 - .dw 0x8340, 0xc99d, 0x837f, 0xc99d, 0x21, 0 - .dw 0x83c0, 0xc99d, 0x83ff, 0xc99d, 0x21, 0 - .dw 0x8440, 0xc99d, 0x847f, 0xc99d, 0x21, 0 - .dw 0x84c0, 0xc99d, 0x84ff, 0xc99d, 0x21, 0 - .dw 0x8540, 0xc99d, 0x857f, 0xc99d, 0x21, 0 - .dw 0x85c0, 0xc99d, 0x85ff, 0xc99d, 0x21, 0 - .dw 0x8640, 0xc99d, 0x867f, 0xc99d, 0x21, 0 - .dw 0x86c0, 0xc99d, 0x86ff, 0xc99d, 0x21, 0 - .dw 0x8740, 0xc99d, 0x877f, 0xc99d, 0x21, 0 - .dw 0x87c0, 0xc99d, 0x87ff, 0xc99d, 0x21, 0 - .dw 0x8840, 0xc99d, 0x887f, 0xc99d, 0x21, 0 - .dw 0x88c0, 0xc99d, 0x88ff, 0xc99d, 0x21, 0 - .dw 0x8940, 0xc99d, 0x897f, 0xc99d, 0x21, 0 - .dw 0x89c0, 0xc99d, 0x89ff, 0xc99d, 0x21, 0 - .dw 0x8a40, 0xc99d, 0x8a7f, 0xc99d, 0x21, 0 - .dw 0x8ac0, 0xc99d, 0x8aff, 0xc99d, 0x21, 0 - .dw 0x8b40, 0xc99d, 0x8b7f, 0xc99d, 0x21, 0 - .dw 0x8bc0, 0xc99d, 0x8bff, 0xc99d, 0x21, 0 - .dw 0x8c40, 0xc99d, 0x8c7f, 0xc99d, 0x21, 0 - .dw 0x8cc0, 0xc99d, 0x8cff, 0xc99d, 0x21, 0 - .dw 0x8d40, 0xc99d, 0x8d7f, 0xc99d, 0x21, 0 - .dw 0x8dc0, 0xc99d, 0x8dff, 0xc99d, 0x21, 0 - .dw 0x8e40, 0xc99d, 0x8e7f, 0xc99d, 0x21, 0 - .dw 0x8ec0, 0xc99d, 0x8eff, 0xc99d, 0x21, 0 - .dw 0x8f40, 0xc99d, 0x8f7f, 0xc99d, 0x21, 0 - .dw 0x8fc0, 0xc99d, 0x8fff, 0xc99d, 0x21, 0 - .dw 0x9040, 0xc99d, 0x907f, 0xc99d, 0x21, 0 - .dw 0x90c0, 0xc99d, 0x90ff, 0xc99d, 0x21, 0 - .dw 0x9140, 0xc99d, 0x917f, 0xc99d, 0x21, 0 - .dw 0x91c0, 0xc99d, 0x91ff, 0xc99d, 0x21, 0 - .dw 0x9240, 0xc99d, 0x927f, 0xc99d, 0x21, 0 - .dw 0x92c0, 0xc99d, 0x92ff, 0xc99d, 0x21, 0 - .dw 0x9340, 0xc99d, 0x937f, 0xc99d, 0x21, 0 - .dw 0x93c0, 0xc99d, 0x93ff, 0xc99d, 0x21, 0 - .dw 0x9440, 0xc99d, 0x947f, 0xc99d, 0x21, 0 - .dw 0x94c0, 0xc99d, 0x94ff, 0xc99d, 0x21, 0 - .dw 0x9540, 0xc99d, 0x957f, 0xc99d, 0x21, 0 - .dw 0x95c0, 0xc99d, 0x95ff, 0xc99d, 0x21, 0 - .dw 0x9640, 0xc99d, 0x967f, 0xc99d, 0x21, 0 - .dw 0x96c0, 0xc99d, 0x96ff, 0xc99d, 0x21, 0 - .dw 0x9740, 0xc99d, 0x977f, 0xc99d, 0x21, 0 - .dw 0x97c0, 0xc99d, 0x97ff, 0xc99d, 0x21, 0 - .dw 0x9840, 0xc99d, 0x987f, 0xc99d, 0x21, 0 - .dw 0x98c0, 0xc99d, 0x98ff, 0xc99d, 0x21, 0 - .dw 0x9940, 0xc99d, 0x997f, 0xc99d, 0x21, 0 - .dw 0x99c0, 0xc99d, 0x9fff, 0xc99d, 0x21, 0 - .dw 0xa040, 0xc99d, 0xa07f, 0xc99d, 0x21, 0 - .dw 0xa0c0, 0xc99d, 0xa0ff, 0xc99d, 0x21, 0 - .dw 0xa140, 0xc99d, 0xa17f, 0xc99d, 0x21, 0 - .dw 0xa1c0, 0xc99d, 0xa1ff, 0xc99d, 0x21, 0 - .dw 0xa240, 0xc99d, 0xa27f, 0xc99d, 0x21, 0 - .dw 0xa2c0, 0xc99d, 0xa2ff, 0xc99d, 0x21, 0 - .dw 0xa340, 0xc99d, 0xa37f, 0xc99d, 0x21, 0 - .dw 0xa3c0, 0xc99d, 0xa3ff, 0xc99d, 0x21, 0 - .dw 0xa440, 0xc99d, 0xa47f, 0xc99d, 0x21, 0 - .dw 0xa4c0, 0xc99d, 0xa4ff, 0xc99d, 0x21, 0 - .dw 0xa540, 0xc99d, 0xa57f, 0xc99d, 0x21, 0 - .dw 0xa5c0, 0xc99d, 0xa5ff, 0xc99d, 0x21, 0 - .dw 0xa640, 0xc99d, 0xa67f, 0xc99d, 0x21, 0 - .dw 0xa6c0, 0xc99d, 0xa6ff, 0xc99d, 0x21, 0 - .dw 0xa740, 0xc99d, 0xa77f, 0xc99d, 0x21, 0 - .dw 0xa7c0, 0xc99d, 0xa7ff, 0xc99d, 0x21, 0 - .dw 0xa840, 0xc99d, 0xa87f, 0xc99d, 0x21, 0 - .dw 0xa8c0, 0xc99d, 0xa8ff, 0xc99d, 0x21, 0 - .dw 0xa940, 0xc99d, 0xa97f, 0xc99d, 0x21, 0 - .dw 0xa9c0, 0xc99d, 0xa9ff, 0xc99d, 0x21, 0 - .dw 0xaa40, 0xc99d, 0xaa7f, 0xc99d, 0x21, 0 - .dw 0xaac0, 0xc99d, 0xaaff, 0xc99d, 0x21, 0 - .dw 0xab40, 0xc99d, 0xab7f, 0xc99d, 0x21, 0 - .dw 0xabc0, 0xc99d, 0xabff, 0xc99d, 0x21, 0 - .dw 0xac40, 0xc99d, 0xac7f, 0xc99d, 0x21, 0 - .dw 0xacc0, 0xc99d, 0xacff, 0xc99d, 0x21, 0 - .dw 0xad40, 0xc99d, 0xad7f, 0xc99d, 0x21, 0 - .dw 0xadc0, 0xc99d, 0xadff, 0xc99d, 0x21, 0 - .dw 0xae40, 0xc99d, 0xae7f, 0xc99d, 0x21, 0 - .dw 0xaec0, 0xc99d, 0xaeff, 0xc99d, 0x21, 0 - .dw 0xaf40, 0xc99d, 0xaf7f, 0xc99d, 0x21, 0 - .dw 0xafc0, 0xc99d, 0xafff, 0xc99d, 0x21, 0 - .dw 0xb040, 0xc99d, 0xb07f, 0xc99d, 0x21, 0 - .dw 0xb0c0, 0xc99d, 0xb0ff, 0xc99d, 0x21, 0 - .dw 0xb140, 0xc99d, 0xb17f, 0xc99d, 0x21, 0 - .dw 0xb1c0, 0xc99d, 0xb1ff, 0xc99d, 0x21, 0 - .dw 0xb240, 0xc99d, 0xb27f, 0xc99d, 0x21, 0 - .dw 0xb2c0, 0xc99d, 0xb2ff, 0xc99d, 0x21, 0 - .dw 0xb340, 0xc99d, 0xb37f, 0xc99d, 0x21, 0 - .dw 0xb3c0, 0xc99d, 0xb3ff, 0xc99d, 0x21, 0 - .dw 0xb440, 0xc99d, 0xb47f, 0xc99d, 0x21, 0 - .dw 0xb4c0, 0xc99d, 0xb4ff, 0xc99d, 0x21, 0 - .dw 0xb540, 0xc99d, 0xb57f, 0xc99d, 0x21, 0 - .dw 0xb5c0, 0xc99d, 0xb5ff, 0xc99d, 0x21, 0 - .dw 0xb640, 0xc99d, 0xb67f, 0xc99d, 0x21, 0 - .dw 0xb6c0, 0xc99d, 0xb6ff, 0xc99d, 0x21, 0 - .dw 0xb740, 0xc99d, 0xb77f, 0xc99d, 0x21, 0 - .dw 0xb7c0, 0xc99d, 0xb7ff, 0xc99d, 0x21, 0 - .dw 0xb840, 0xc99d, 0xb87f, 0xc99d, 0x21, 0 - .dw 0xb8c0, 0xc99d, 0xb8ff, 0xc99d, 0x21, 0 - .dw 0xb940, 0xc99d, 0xb97f, 0xc99d, 0x21, 0 - .dw 0xb9c0, 0xc99d, 0xbfff, 0xc99d, 0x21, 0 - .dw 0xc040, 0xc99d, 0xc07f, 0xc99d, 0x21, 0 - .dw 0xc0c0, 0xc99d, 0xc0ff, 0xc99d, 0x21, 0 - .dw 0xc140, 0xc99d, 0xc17f, 0xc99d, 0x21, 0 - .dw 0xc1c0, 0xc99d, 0xc1ff, 0xc99d, 0x21, 0 - .dw 0xc240, 0xc99d, 0xc27f, 0xc99d, 0x21, 0 - .dw 0xc2c0, 0xc99d, 0xc2ff, 0xc99d, 0x21, 0 - .dw 0xc340, 0xc99d, 0xc37f, 0xc99d, 0x21, 0 - .dw 0xc3c0, 0xc99d, 0xc3ff, 0xc99d, 0x21, 0 - .dw 0xc440, 0xc99d, 0xc47f, 0xc99d, 0x21, 0 - .dw 0xc4c0, 0xc99d, 0xc4ff, 0xc99d, 0x21, 0 - .dw 0xc540, 0xc99d, 0xc57f, 0xc99d, 0x21, 0 - .dw 0xc5c0, 0xc99d, 0xc5ff, 0xc99d, 0x21, 0 - .dw 0xc640, 0xc99d, 0xc67f, 0xc99d, 0x21, 0 - .dw 0xc6c0, 0xc99d, 0xc6ff, 0xc99d, 0x21, 0 - .dw 0xc740, 0xc99d, 0xc77f, 0xc99d, 0x21, 0 - .dw 0xc7c0, 0xc99d, 0xc7ff, 0xc99d, 0x21, 0 - .dw 0xc840, 0xc99d, 0xc87f, 0xc99d, 0x21, 0 - .dw 0xc8c0, 0xc99d, 0xc8ff, 0xc99d, 0x21, 0 - .dw 0xc940, 0xc99d, 0xc97f, 0xc99d, 0x21, 0 - .dw 0xc9c0, 0xc99d, 0xc9ff, 0xc99d, 0x21, 0 - .dw 0xca40, 0xc99d, 0xca7f, 0xc99d, 0x21, 0 - .dw 0xcac0, 0xc99d, 0xcaff, 0xc99d, 0x21, 0 - .dw 0xcb40, 0xc99d, 0xcb7f, 0xc99d, 0x21, 0 - .dw 0xcbc0, 0xc99d, 0xcbff, 0xc99d, 0x21, 0 - .dw 0xcc40, 0xc99d, 0xcc7f, 0xc99d, 0x21, 0 - .dw 0xccc0, 0xc99d, 0xccff, 0xc99d, 0x21, 0 - .dw 0xcd40, 0xc99d, 0xcd7f, 0xc99d, 0x21, 0 - .dw 0xcdc0, 0xc99d, 0xcdff, 0xc99d, 0x21, 0 - .dw 0xce40, 0xc99d, 0xce7f, 0xc99d, 0x21, 0 - .dw 0xcec0, 0xc99d, 0xceff, 0xc99d, 0x21, 0 - .dw 0xcf40, 0xc99d, 0xcf7f, 0xc99d, 0x21, 0 - .dw 0xcfc0, 0xc99d, 0xcfff, 0xc99d, 0x21, 0 - .dw 0xd040, 0xc99d, 0xd07f, 0xc99d, 0x21, 0 - .dw 0xd0c0, 0xc99d, 0xd0ff, 0xc99d, 0x21, 0 - .dw 0xd140, 0xc99d, 0xd17f, 0xc99d, 0x21, 0 - .dw 0xd1c0, 0xc99d, 0xd1ff, 0xc99d, 0x21, 0 - .dw 0xd240, 0xc99d, 0xd27f, 0xc99d, 0x21, 0 - .dw 0xd2c0, 0xc99d, 0xd2ff, 0xc99d, 0x21, 0 - .dw 0xd340, 0xc99d, 0xd37f, 0xc99d, 0x21, 0 - .dw 0xd3c0, 0xc99d, 0xd3ff, 0xc99d, 0x21, 0 - .dw 0xd440, 0xc99d, 0xd47f, 0xc99d, 0x21, 0 - .dw 0xd4c0, 0xc99d, 0xd4ff, 0xc99d, 0x21, 0 - .dw 0xd540, 0xc99d, 0xd57f, 0xc99d, 0x21, 0 - .dw 0xd5c0, 0xc99d, 0xd5ff, 0xc99d, 0x21, 0 - .dw 0xd640, 0xc99d, 0xd67f, 0xc99d, 0x21, 0 - .dw 0xd6c0, 0xc99d, 0xd6ff, 0xc99d, 0x21, 0 - .dw 0xd740, 0xc99d, 0xd77f, 0xc99d, 0x21, 0 - .dw 0xd7c0, 0xc99d, 0xd7ff, 0xc99d, 0x21, 0 - .dw 0xd840, 0xc99d, 0xd87f, 0xc99d, 0x21, 0 - .dw 0xd8c0, 0xc99d, 0xd8ff, 0xc99d, 0x21, 0 - .dw 0xd940, 0xc99d, 0xd97f, 0xc99d, 0x21, 0 - .dw 0xd9c0, 0xc99d, 0xdfff, 0xc99d, 0x21, 0 - .dw 0xe040, 0xc99d, 0xe07f, 0xc99d, 0x21, 0 - .dw 0xe0c0, 0xc99d, 0xe0ff, 0xc99d, 0x21, 0 - .dw 0xe140, 0xc99d, 0xe17f, 0xc99d, 0x21, 0 - .dw 0xe1c0, 0xc99d, 0xe1ff, 0xc99d, 0x21, 0 - .dw 0xe240, 0xc99d, 0xe27f, 0xc99d, 0x21, 0 - .dw 0xe2c0, 0xc99d, 0xe2ff, 0xc99d, 0x21, 0 - .dw 0xe340, 0xc99d, 0xe37f, 0xc99d, 0x21, 0 - .dw 0xe3c0, 0xc99d, 0xe3ff, 0xc99d, 0x21, 0 - .dw 0xe440, 0xc99d, 0xe47f, 0xc99d, 0x21, 0 - .dw 0xe4c0, 0xc99d, 0xe4ff, 0xc99d, 0x21, 0 - .dw 0xe540, 0xc99d, 0xe57f, 0xc99d, 0x21, 0 - .dw 0xe5c0, 0xc99d, 0xe5ff, 0xc99d, 0x21, 0 - .dw 0xe640, 0xc99d, 0xe67f, 0xc99d, 0x21, 0 - .dw 0xe6c0, 0xc99d, 0xe6ff, 0xc99d, 0x21, 0 - .dw 0xe740, 0xc99d, 0xe77f, 0xc99d, 0x21, 0 - .dw 0xe7c0, 0xc99d, 0xe7ff, 0xc99d, 0x21, 0 - .dw 0xe840, 0xc99d, 0xe87f, 0xc99d, 0x21, 0 - .dw 0xe8c0, 0xc99d, 0xe8ff, 0xc99d, 0x21, 0 - .dw 0xe940, 0xc99d, 0xe97f, 0xc99d, 0x21, 0 - .dw 0xe9c0, 0xc99d, 0xe9ff, 0xc99d, 0x21, 0 - .dw 0xea40, 0xc99d, 0xea7f, 0xc99d, 0x21, 0 - .dw 0xeac0, 0xc99d, 0xeaff, 0xc99d, 0x21, 0 - .dw 0xeb40, 0xc99d, 0xeb7f, 0xc99d, 0x21, 0 - .dw 0xebc0, 0xc99d, 0xebff, 0xc99d, 0x21, 0 - .dw 0xec40, 0xc99d, 0xec7f, 0xc99d, 0x21, 0 - .dw 0xecc0, 0xc99d, 0xecff, 0xc99d, 0x21, 0 - .dw 0xed40, 0xc99d, 0xed7f, 0xc99d, 0x21, 0 - .dw 0xedc0, 0xc99d, 0xedff, 0xc99d, 0x21, 0 - .dw 0xee40, 0xc99d, 0xee7f, 0xc99d, 0x21, 0 - .dw 0xeec0, 0xc99d, 0xeeff, 0xc99d, 0x21, 0 - .dw 0xef40, 0xc99d, 0xef7f, 0xc99d, 0x21, 0 - .dw 0xefc0, 0xc99d, 0xefff, 0xc99d, 0x21, 0 - .dw 0xf040, 0xc99d, 0xf07f, 0xc99d, 0x21, 0 - .dw 0xf0c0, 0xc99d, 0xf0ff, 0xc99d, 0x21, 0 - .dw 0xf140, 0xc99d, 0xf17f, 0xc99d, 0x21, 0 - .dw 0xf1c0, 0xc99d, 0xf1ff, 0xc99d, 0x21, 0 - .dw 0xf240, 0xc99d, 0xf27f, 0xc99d, 0x21, 0 - .dw 0xf2c0, 0xc99d, 0xf2ff, 0xc99d, 0x21, 0 - .dw 0xf340, 0xc99d, 0xf37f, 0xc99d, 0x21, 0 - .dw 0xf3c0, 0xc99d, 0xf3ff, 0xc99d, 0x21, 0 - .dw 0xf440, 0xc99d, 0xf47f, 0xc99d, 0x21, 0 - .dw 0xf4c0, 0xc99d, 0xf4ff, 0xc99d, 0x21, 0 - .dw 0xf540, 0xc99d, 0xf57f, 0xc99d, 0x21, 0 - .dw 0xf5c0, 0xc99d, 0xf5ff, 0xc99d, 0x21, 0 - .dw 0xf640, 0xc99d, 0xf67f, 0xc99d, 0x21, 0 - .dw 0xf6c0, 0xc99d, 0xf6ff, 0xc99d, 0x21, 0 - .dw 0xf740, 0xc99d, 0xf77f, 0xc99d, 0x21, 0 - .dw 0xf7c0, 0xc99d, 0xf7ff, 0xc99d, 0x21, 0 - .dw 0xf840, 0xc99d, 0xf87f, 0xc99d, 0x21, 0 - .dw 0xf8c0, 0xc99d, 0xf8ff, 0xc99d, 0x21, 0 - .dw 0xf940, 0xc99d, 0xf97f, 0xc99d, 0x21, 0 - .dw 0xf9c0, 0xc99d, 0xffff, 0xc99d, 0x21, 0 - .dw 0x0040, 0xc99e, 0x007f, 0xc99e, 0x21, 0 - .dw 0x00c0, 0xc99e, 0x00ff, 0xc99e, 0x21, 0 - .dw 0x0140, 0xc99e, 0x017f, 0xc99e, 0x21, 0 - .dw 0x01c0, 0xc99e, 0x01ff, 0xc99e, 0x21, 0 - .dw 0x0240, 0xc99e, 0x027f, 0xc99e, 0x21, 0 - .dw 0x02c0, 0xc99e, 0x02ff, 0xc99e, 0x21, 0 - .dw 0x0340, 0xc99e, 0x037f, 0xc99e, 0x21, 0 - .dw 0x03c0, 0xc99e, 0x03ff, 0xc99e, 0x21, 0 - .dw 0x0440, 0xc99e, 0x047f, 0xc99e, 0x21, 0 - .dw 0x04c0, 0xc99e, 0x04ff, 0xc99e, 0x21, 0 - .dw 0x0540, 0xc99e, 0x057f, 0xc99e, 0x21, 0 - .dw 0x05c0, 0xc99e, 0x05ff, 0xc99e, 0x21, 0 - .dw 0x0640, 0xc99e, 0x067f, 0xc99e, 0x21, 0 - .dw 0x06c0, 0xc99e, 0x06ff, 0xc99e, 0x21, 0 - .dw 0x0740, 0xc99e, 0x077f, 0xc99e, 0x21, 0 - .dw 0x07c0, 0xc99e, 0x07ff, 0xc99e, 0x21, 0 - .dw 0x0840, 0xc99e, 0x087f, 0xc99e, 0x21, 0 - .dw 0x08c0, 0xc99e, 0x08ff, 0xc99e, 0x21, 0 - .dw 0x0940, 0xc99e, 0x097f, 0xc99e, 0x21, 0 - .dw 0x09c0, 0xc99e, 0x09ff, 0xc99e, 0x21, 0 - .dw 0x0a40, 0xc99e, 0x0a7f, 0xc99e, 0x21, 0 - .dw 0x0ac0, 0xc99e, 0x0aff, 0xc99e, 0x21, 0 - .dw 0x0b40, 0xc99e, 0x0b7f, 0xc99e, 0x21, 0 - .dw 0x0bc0, 0xc99e, 0x0bff, 0xc99e, 0x21, 0 - .dw 0x0c40, 0xc99e, 0x0c7f, 0xc99e, 0x21, 0 - .dw 0x0cc0, 0xc99e, 0x0cff, 0xc99e, 0x21, 0 - .dw 0x0d40, 0xc99e, 0x0d7f, 0xc99e, 0x21, 0 - .dw 0x0dc0, 0xc99e, 0x0dff, 0xc99e, 0x21, 0 - .dw 0x0e40, 0xc99e, 0x0e7f, 0xc99e, 0x21, 0 - .dw 0x0ec0, 0xc99e, 0x0eff, 0xc99e, 0x21, 0 - .dw 0x0f40, 0xc99e, 0x0f7f, 0xc99e, 0x21, 0 - .dw 0x0fc0, 0xc99e, 0x0fff, 0xc99e, 0x21, 0 - .dw 0x1040, 0xc99e, 0x107f, 0xc99e, 0x21, 0 - .dw 0x10c0, 0xc99e, 0x10ff, 0xc99e, 0x21, 0 - .dw 0x1140, 0xc99e, 0x117f, 0xc99e, 0x21, 0 - .dw 0x11c0, 0xc99e, 0x11ff, 0xc99e, 0x21, 0 - .dw 0x1240, 0xc99e, 0x127f, 0xc99e, 0x21, 0 - .dw 0x12c0, 0xc99e, 0x12ff, 0xc99e, 0x21, 0 - .dw 0x1340, 0xc99e, 0x137f, 0xc99e, 0x21, 0 - .dw 0x13c0, 0xc99e, 0x13ff, 0xc99e, 0x21, 0 - .dw 0x1440, 0xc99e, 0x147f, 0xc99e, 0x21, 0 - .dw 0x14c0, 0xc99e, 0x14ff, 0xc99e, 0x21, 0 - .dw 0x1540, 0xc99e, 0x157f, 0xc99e, 0x21, 0 - .dw 0x15c0, 0xc99e, 0x15ff, 0xc99e, 0x21, 0 - .dw 0x1640, 0xc99e, 0x167f, 0xc99e, 0x21, 0 - .dw 0x16c0, 0xc99e, 0x16ff, 0xc99e, 0x21, 0 - .dw 0x1740, 0xc99e, 0x177f, 0xc99e, 0x21, 0 - .dw 0x17c0, 0xc99e, 0x17ff, 0xc99e, 0x21, 0 - .dw 0x1840, 0xc99e, 0x187f, 0xc99e, 0x21, 0 - .dw 0x18c0, 0xc99e, 0x18ff, 0xc99e, 0x21, 0 - .dw 0x1940, 0xc99e, 0x197f, 0xc99e, 0x21, 0 - .dw 0x19c0, 0xc99e, 0x1fff, 0xc99e, 0x21, 0 - .dw 0x2040, 0xc99e, 0x207f, 0xc99e, 0x21, 0 - .dw 0x20c0, 0xc99e, 0x20ff, 0xc99e, 0x21, 0 - .dw 0x2140, 0xc99e, 0x217f, 0xc99e, 0x21, 0 - .dw 0x21c0, 0xc99e, 0x21ff, 0xc99e, 0x21, 0 - .dw 0x2240, 0xc99e, 0x227f, 0xc99e, 0x21, 0 - .dw 0x22c0, 0xc99e, 0x22ff, 0xc99e, 0x21, 0 - .dw 0x2340, 0xc99e, 0x237f, 0xc99e, 0x21, 0 - .dw 0x23c0, 0xc99e, 0x23ff, 0xc99e, 0x21, 0 - .dw 0x2440, 0xc99e, 0x247f, 0xc99e, 0x21, 0 - .dw 0x24c0, 0xc99e, 0x24ff, 0xc99e, 0x21, 0 - .dw 0x2540, 0xc99e, 0x257f, 0xc99e, 0x21, 0 - .dw 0x25c0, 0xc99e, 0x25ff, 0xc99e, 0x21, 0 - .dw 0x2640, 0xc99e, 0x267f, 0xc99e, 0x21, 0 - .dw 0x26c0, 0xc99e, 0x26ff, 0xc99e, 0x21, 0 - .dw 0x2740, 0xc99e, 0x277f, 0xc99e, 0x21, 0 - .dw 0x27c0, 0xc99e, 0x27ff, 0xc99e, 0x21, 0 - .dw 0x2840, 0xc99e, 0x287f, 0xc99e, 0x21, 0 - .dw 0x28c0, 0xc99e, 0x28ff, 0xc99e, 0x21, 0 - .dw 0x2940, 0xc99e, 0x297f, 0xc99e, 0x21, 0 - .dw 0x29c0, 0xc99e, 0x29ff, 0xc99e, 0x21, 0 - .dw 0x2a40, 0xc99e, 0x2a7f, 0xc99e, 0x21, 0 - .dw 0x2ac0, 0xc99e, 0x2aff, 0xc99e, 0x21, 0 - .dw 0x2b40, 0xc99e, 0x2b7f, 0xc99e, 0x21, 0 - .dw 0x2bc0, 0xc99e, 0x2bff, 0xc99e, 0x21, 0 - .dw 0x2c40, 0xc99e, 0x2c7f, 0xc99e, 0x21, 0 - .dw 0x2cc0, 0xc99e, 0x2cff, 0xc99e, 0x21, 0 - .dw 0x2d40, 0xc99e, 0x2d7f, 0xc99e, 0x21, 0 - .dw 0x2dc0, 0xc99e, 0x2dff, 0xc99e, 0x21, 0 - .dw 0x2e40, 0xc99e, 0x2e7f, 0xc99e, 0x21, 0 - .dw 0x2ec0, 0xc99e, 0x2eff, 0xc99e, 0x21, 0 - .dw 0x2f40, 0xc99e, 0x2f7f, 0xc99e, 0x21, 0 - .dw 0x2fc0, 0xc99e, 0x2fff, 0xc99e, 0x21, 0 - .dw 0x3040, 0xc99e, 0x307f, 0xc99e, 0x21, 0 - .dw 0x30c0, 0xc99e, 0x30ff, 0xc99e, 0x21, 0 - .dw 0x3140, 0xc99e, 0x317f, 0xc99e, 0x21, 0 - .dw 0x31c0, 0xc99e, 0x31ff, 0xc99e, 0x21, 0 - .dw 0x3240, 0xc99e, 0x327f, 0xc99e, 0x21, 0 - .dw 0x32c0, 0xc99e, 0x32ff, 0xc99e, 0x21, 0 - .dw 0x3340, 0xc99e, 0x337f, 0xc99e, 0x21, 0 - .dw 0x33c0, 0xc99e, 0x33ff, 0xc99e, 0x21, 0 - .dw 0x3440, 0xc99e, 0x347f, 0xc99e, 0x21, 0 - .dw 0x34c0, 0xc99e, 0x34ff, 0xc99e, 0x21, 0 - .dw 0x3540, 0xc99e, 0x357f, 0xc99e, 0x21, 0 - .dw 0x35c0, 0xc99e, 0x35ff, 0xc99e, 0x21, 0 - .dw 0x3640, 0xc99e, 0x367f, 0xc99e, 0x21, 0 - .dw 0x36c0, 0xc99e, 0x36ff, 0xc99e, 0x21, 0 - .dw 0x3740, 0xc99e, 0x377f, 0xc99e, 0x21, 0 - .dw 0x37c0, 0xc99e, 0x37ff, 0xc99e, 0x21, 0 - .dw 0x3840, 0xc99e, 0x387f, 0xc99e, 0x21, 0 - .dw 0x38c0, 0xc99e, 0x38ff, 0xc99e, 0x21, 0 - .dw 0x3940, 0xc99e, 0x397f, 0xc99e, 0x21, 0 - .dw 0x39c0, 0xc99e, 0x3fff, 0xc99e, 0x21, 0 - .dw 0x4040, 0xc99e, 0x407f, 0xc99e, 0x21, 0 - .dw 0x40c0, 0xc99e, 0x40ff, 0xc99e, 0x21, 0 - .dw 0x4140, 0xc99e, 0x417f, 0xc99e, 0x21, 0 - .dw 0x41c0, 0xc99e, 0x41ff, 0xc99e, 0x21, 0 - .dw 0x4240, 0xc99e, 0x427f, 0xc99e, 0x21, 0 - .dw 0x42c0, 0xc99e, 0x42ff, 0xc99e, 0x21, 0 - .dw 0x4340, 0xc99e, 0x437f, 0xc99e, 0x21, 0 - .dw 0x43c0, 0xc99e, 0x43ff, 0xc99e, 0x21, 0 - .dw 0x4440, 0xc99e, 0x447f, 0xc99e, 0x21, 0 - .dw 0x44c0, 0xc99e, 0x44ff, 0xc99e, 0x21, 0 - .dw 0x4540, 0xc99e, 0x457f, 0xc99e, 0x21, 0 - .dw 0x45c0, 0xc99e, 0x45ff, 0xc99e, 0x21, 0 - .dw 0x4640, 0xc99e, 0x467f, 0xc99e, 0x21, 0 - .dw 0x46c0, 0xc99e, 0x46ff, 0xc99e, 0x21, 0 - .dw 0x4740, 0xc99e, 0x477f, 0xc99e, 0x21, 0 - .dw 0x47c0, 0xc99e, 0x47ff, 0xc99e, 0x21, 0 - .dw 0x4840, 0xc99e, 0x487f, 0xc99e, 0x21, 0 - .dw 0x48c0, 0xc99e, 0x48ff, 0xc99e, 0x21, 0 - .dw 0x4940, 0xc99e, 0x497f, 0xc99e, 0x21, 0 - .dw 0x49c0, 0xc99e, 0x49ff, 0xc99e, 0x21, 0 - .dw 0x4a40, 0xc99e, 0x4a7f, 0xc99e, 0x21, 0 - .dw 0x4ac0, 0xc99e, 0x4aff, 0xc99e, 0x21, 0 - .dw 0x4b40, 0xc99e, 0x4b7f, 0xc99e, 0x21, 0 - .dw 0x4bc0, 0xc99e, 0x4bff, 0xc99e, 0x21, 0 - .dw 0x4c40, 0xc99e, 0x4c7f, 0xc99e, 0x21, 0 - .dw 0x4cc0, 0xc99e, 0x4cff, 0xc99e, 0x21, 0 - .dw 0x4d40, 0xc99e, 0x4d7f, 0xc99e, 0x21, 0 - .dw 0x4dc0, 0xc99e, 0x4dff, 0xc99e, 0x21, 0 - .dw 0x4e40, 0xc99e, 0x4e7f, 0xc99e, 0x21, 0 - .dw 0x4ec0, 0xc99e, 0x4eff, 0xc99e, 0x21, 0 - .dw 0x4f40, 0xc99e, 0x4f7f, 0xc99e, 0x21, 0 - .dw 0x4fc0, 0xc99e, 0x4fff, 0xc99e, 0x21, 0 - .dw 0x5040, 0xc99e, 0x507f, 0xc99e, 0x21, 0 - .dw 0x50c0, 0xc99e, 0x50ff, 0xc99e, 0x21, 0 - .dw 0x5140, 0xc99e, 0x517f, 0xc99e, 0x21, 0 - .dw 0x51c0, 0xc99e, 0x51ff, 0xc99e, 0x21, 0 - .dw 0x5240, 0xc99e, 0x527f, 0xc99e, 0x21, 0 - .dw 0x52c0, 0xc99e, 0x52ff, 0xc99e, 0x21, 0 - .dw 0x5340, 0xc99e, 0x537f, 0xc99e, 0x21, 0 - .dw 0x53c0, 0xc99e, 0x53ff, 0xc99e, 0x21, 0 - .dw 0x5440, 0xc99e, 0x547f, 0xc99e, 0x21, 0 - .dw 0x54c0, 0xc99e, 0x54ff, 0xc99e, 0x21, 0 - .dw 0x5540, 0xc99e, 0x557f, 0xc99e, 0x21, 0 - .dw 0x55c0, 0xc99e, 0x55ff, 0xc99e, 0x21, 0 - .dw 0x5640, 0xc99e, 0x567f, 0xc99e, 0x21, 0 - .dw 0x56c0, 0xc99e, 0x56ff, 0xc99e, 0x21, 0 - .dw 0x5740, 0xc99e, 0x577f, 0xc99e, 0x21, 0 - .dw 0x57c0, 0xc99e, 0x57ff, 0xc99e, 0x21, 0 - .dw 0x5840, 0xc99e, 0x587f, 0xc99e, 0x21, 0 - .dw 0x58c0, 0xc99e, 0x58ff, 0xc99e, 0x21, 0 - .dw 0x5940, 0xc99e, 0x597f, 0xc99e, 0x21, 0 - .dw 0x59c0, 0xc99e, 0x5fff, 0xc99e, 0x21, 0 - .dw 0x6040, 0xc99e, 0x607f, 0xc99e, 0x21, 0 - .dw 0x60c0, 0xc99e, 0x60ff, 0xc99e, 0x21, 0 - .dw 0x6140, 0xc99e, 0x617f, 0xc99e, 0x21, 0 - .dw 0x61c0, 0xc99e, 0x61ff, 0xc99e, 0x21, 0 - .dw 0x6240, 0xc99e, 0x627f, 0xc99e, 0x21, 0 - .dw 0x62c0, 0xc99e, 0x62ff, 0xc99e, 0x21, 0 - .dw 0x6340, 0xc99e, 0x637f, 0xc99e, 0x21, 0 - .dw 0x63c0, 0xc99e, 0x63ff, 0xc99e, 0x21, 0 - .dw 0x6440, 0xc99e, 0x647f, 0xc99e, 0x21, 0 - .dw 0x64c0, 0xc99e, 0x64ff, 0xc99e, 0x21, 0 - .dw 0x6540, 0xc99e, 0x657f, 0xc99e, 0x21, 0 - .dw 0x65c0, 0xc99e, 0x65ff, 0xc99e, 0x21, 0 - .dw 0x6640, 0xc99e, 0x667f, 0xc99e, 0x21, 0 - .dw 0x66c0, 0xc99e, 0x66ff, 0xc99e, 0x21, 0 - .dw 0x6740, 0xc99e, 0x677f, 0xc99e, 0x21, 0 - .dw 0x67c0, 0xc99e, 0x67ff, 0xc99e, 0x21, 0 - .dw 0x6840, 0xc99e, 0x687f, 0xc99e, 0x21, 0 - .dw 0x68c0, 0xc99e, 0x68ff, 0xc99e, 0x21, 0 - .dw 0x6940, 0xc99e, 0x697f, 0xc99e, 0x21, 0 - .dw 0x69c0, 0xc99e, 0x69ff, 0xc99e, 0x21, 0 - .dw 0x6a40, 0xc99e, 0x6a7f, 0xc99e, 0x21, 0 - .dw 0x6ac0, 0xc99e, 0x6aff, 0xc99e, 0x21, 0 - .dw 0x6b40, 0xc99e, 0x6b7f, 0xc99e, 0x21, 0 - .dw 0x6bc0, 0xc99e, 0x6bff, 0xc99e, 0x21, 0 - .dw 0x6c40, 0xc99e, 0x6c7f, 0xc99e, 0x21, 0 - .dw 0x6cc0, 0xc99e, 0x6cff, 0xc99e, 0x21, 0 - .dw 0x6d40, 0xc99e, 0x6d7f, 0xc99e, 0x21, 0 - .dw 0x6dc0, 0xc99e, 0x6dff, 0xc99e, 0x21, 0 - .dw 0x6e40, 0xc99e, 0x6e7f, 0xc99e, 0x21, 0 - .dw 0x6ec0, 0xc99e, 0x6eff, 0xc99e, 0x21, 0 - .dw 0x6f40, 0xc99e, 0x6f7f, 0xc99e, 0x21, 0 - .dw 0x6fc0, 0xc99e, 0x6fff, 0xc99e, 0x21, 0 - .dw 0x7040, 0xc99e, 0x707f, 0xc99e, 0x21, 0 - .dw 0x70c0, 0xc99e, 0x70ff, 0xc99e, 0x21, 0 - .dw 0x7140, 0xc99e, 0x717f, 0xc99e, 0x21, 0 - .dw 0x71c0, 0xc99e, 0x71ff, 0xc99e, 0x21, 0 - .dw 0x7240, 0xc99e, 0x727f, 0xc99e, 0x21, 0 - .dw 0x72c0, 0xc99e, 0x72ff, 0xc99e, 0x21, 0 - .dw 0x7340, 0xc99e, 0x737f, 0xc99e, 0x21, 0 - .dw 0x73c0, 0xc99e, 0x73ff, 0xc99e, 0x21, 0 - .dw 0x7440, 0xc99e, 0x747f, 0xc99e, 0x21, 0 - .dw 0x74c0, 0xc99e, 0x74ff, 0xc99e, 0x21, 0 - .dw 0x7540, 0xc99e, 0x757f, 0xc99e, 0x21, 0 - .dw 0x75c0, 0xc99e, 0x75ff, 0xc99e, 0x21, 0 - .dw 0x7640, 0xc99e, 0x767f, 0xc99e, 0x21, 0 - .dw 0x76c0, 0xc99e, 0x76ff, 0xc99e, 0x21, 0 - .dw 0x7740, 0xc99e, 0x777f, 0xc99e, 0x21, 0 - .dw 0x77c0, 0xc99e, 0x77ff, 0xc99e, 0x21, 0 - .dw 0x7840, 0xc99e, 0x787f, 0xc99e, 0x21, 0 - .dw 0x78c0, 0xc99e, 0x78ff, 0xc99e, 0x21, 0 - .dw 0x7940, 0xc99e, 0x797f, 0xc99e, 0x21, 0 - .dw 0x79c0, 0xc99e, 0x7fff, 0xc99e, 0x21, 0 - .dw 0x8040, 0xc99e, 0x807f, 0xc99e, 0x21, 0 - .dw 0x80c0, 0xc99e, 0x80ff, 0xc99e, 0x21, 0 - .dw 0x8140, 0xc99e, 0x817f, 0xc99e, 0x21, 0 - .dw 0x81c0, 0xc99e, 0x81ff, 0xc99e, 0x21, 0 - .dw 0x8240, 0xc99e, 0x827f, 0xc99e, 0x21, 0 - .dw 0x82c0, 0xc99e, 0x82ff, 0xc99e, 0x21, 0 - .dw 0x8340, 0xc99e, 0x837f, 0xc99e, 0x21, 0 - .dw 0x83c0, 0xc99e, 0x83ff, 0xc99e, 0x21, 0 - .dw 0x8440, 0xc99e, 0x847f, 0xc99e, 0x21, 0 - .dw 0x84c0, 0xc99e, 0x84ff, 0xc99e, 0x21, 0 - .dw 0x8540, 0xc99e, 0x857f, 0xc99e, 0x21, 0 - .dw 0x85c0, 0xc99e, 0x85ff, 0xc99e, 0x21, 0 - .dw 0x8640, 0xc99e, 0x867f, 0xc99e, 0x21, 0 - .dw 0x86c0, 0xc99e, 0x86ff, 0xc99e, 0x21, 0 - .dw 0x8740, 0xc99e, 0x877f, 0xc99e, 0x21, 0 - .dw 0x87c0, 0xc99e, 0x87ff, 0xc99e, 0x21, 0 - .dw 0x8840, 0xc99e, 0x887f, 0xc99e, 0x21, 0 - .dw 0x88c0, 0xc99e, 0x88ff, 0xc99e, 0x21, 0 - .dw 0x8940, 0xc99e, 0x897f, 0xc99e, 0x21, 0 - .dw 0x89c0, 0xc99e, 0x89ff, 0xc99e, 0x21, 0 - .dw 0x8a40, 0xc99e, 0x8a7f, 0xc99e, 0x21, 0 - .dw 0x8ac0, 0xc99e, 0x8aff, 0xc99e, 0x21, 0 - .dw 0x8b40, 0xc99e, 0x8b7f, 0xc99e, 0x21, 0 - .dw 0x8bc0, 0xc99e, 0x8bff, 0xc99e, 0x21, 0 - .dw 0x8c40, 0xc99e, 0x8c7f, 0xc99e, 0x21, 0 - .dw 0x8cc0, 0xc99e, 0x8cff, 0xc99e, 0x21, 0 - .dw 0x8d40, 0xc99e, 0x8d7f, 0xc99e, 0x21, 0 - .dw 0x8dc0, 0xc99e, 0x8dff, 0xc99e, 0x21, 0 - .dw 0x8e40, 0xc99e, 0x8e7f, 0xc99e, 0x21, 0 - .dw 0x8ec0, 0xc99e, 0x8eff, 0xc99e, 0x21, 0 - .dw 0x8f40, 0xc99e, 0x8f7f, 0xc99e, 0x21, 0 - .dw 0x8fc0, 0xc99e, 0x8fff, 0xc99e, 0x21, 0 - .dw 0x9040, 0xc99e, 0x907f, 0xc99e, 0x21, 0 - .dw 0x90c0, 0xc99e, 0x90ff, 0xc99e, 0x21, 0 - .dw 0x9140, 0xc99e, 0x917f, 0xc99e, 0x21, 0 - .dw 0x91c0, 0xc99e, 0x91ff, 0xc99e, 0x21, 0 - .dw 0x9240, 0xc99e, 0x927f, 0xc99e, 0x21, 0 - .dw 0x92c0, 0xc99e, 0x92ff, 0xc99e, 0x21, 0 - .dw 0x9340, 0xc99e, 0x937f, 0xc99e, 0x21, 0 - .dw 0x93c0, 0xc99e, 0x93ff, 0xc99e, 0x21, 0 - .dw 0x9440, 0xc99e, 0x947f, 0xc99e, 0x21, 0 - .dw 0x94c0, 0xc99e, 0x94ff, 0xc99e, 0x21, 0 - .dw 0x9540, 0xc99e, 0x957f, 0xc99e, 0x21, 0 - .dw 0x95c0, 0xc99e, 0x95ff, 0xc99e, 0x21, 0 - .dw 0x9640, 0xc99e, 0x967f, 0xc99e, 0x21, 0 - .dw 0x96c0, 0xc99e, 0x96ff, 0xc99e, 0x21, 0 - .dw 0x9740, 0xc99e, 0x977f, 0xc99e, 0x21, 0 - .dw 0x97c0, 0xc99e, 0x97ff, 0xc99e, 0x21, 0 - .dw 0x9840, 0xc99e, 0x987f, 0xc99e, 0x21, 0 - .dw 0x98c0, 0xc99e, 0x98ff, 0xc99e, 0x21, 0 - .dw 0x9940, 0xc99e, 0x997f, 0xc99e, 0x21, 0 - .dw 0x99c0, 0xc99e, 0x9fff, 0xc99e, 0x21, 0 - .dw 0xa040, 0xc99e, 0xa07f, 0xc99e, 0x21, 0 - .dw 0xa0c0, 0xc99e, 0xa0ff, 0xc99e, 0x21, 0 - .dw 0xa140, 0xc99e, 0xa17f, 0xc99e, 0x21, 0 - .dw 0xa1c0, 0xc99e, 0xa1ff, 0xc99e, 0x21, 0 - .dw 0xa240, 0xc99e, 0xa27f, 0xc99e, 0x21, 0 - .dw 0xa2c0, 0xc99e, 0xa2ff, 0xc99e, 0x21, 0 - .dw 0xa340, 0xc99e, 0xa37f, 0xc99e, 0x21, 0 - .dw 0xa3c0, 0xc99e, 0xa3ff, 0xc99e, 0x21, 0 - .dw 0xa440, 0xc99e, 0xa47f, 0xc99e, 0x21, 0 - .dw 0xa4c0, 0xc99e, 0xa4ff, 0xc99e, 0x21, 0 - .dw 0xa540, 0xc99e, 0xa57f, 0xc99e, 0x21, 0 - .dw 0xa5c0, 0xc99e, 0xa5ff, 0xc99e, 0x21, 0 - .dw 0xa640, 0xc99e, 0xa67f, 0xc99e, 0x21, 0 - .dw 0xa6c0, 0xc99e, 0xa6ff, 0xc99e, 0x21, 0 - .dw 0xa740, 0xc99e, 0xa77f, 0xc99e, 0x21, 0 - .dw 0xa7c0, 0xc99e, 0xa7ff, 0xc99e, 0x21, 0 - .dw 0xa840, 0xc99e, 0xa87f, 0xc99e, 0x21, 0 - .dw 0xa8c0, 0xc99e, 0xa8ff, 0xc99e, 0x21, 0 - .dw 0xa940, 0xc99e, 0xa97f, 0xc99e, 0x21, 0 - .dw 0xa9c0, 0xc99e, 0xa9ff, 0xc99e, 0x21, 0 - .dw 0xaa40, 0xc99e, 0xaa7f, 0xc99e, 0x21, 0 - .dw 0xaac0, 0xc99e, 0xaaff, 0xc99e, 0x21, 0 - .dw 0xab40, 0xc99e, 0xab7f, 0xc99e, 0x21, 0 - .dw 0xabc0, 0xc99e, 0xabff, 0xc99e, 0x21, 0 - .dw 0xac40, 0xc99e, 0xac7f, 0xc99e, 0x21, 0 - .dw 0xacc0, 0xc99e, 0xacff, 0xc99e, 0x21, 0 - .dw 0xad40, 0xc99e, 0xad7f, 0xc99e, 0x21, 0 - .dw 0xadc0, 0xc99e, 0xadff, 0xc99e, 0x21, 0 - .dw 0xae40, 0xc99e, 0xae7f, 0xc99e, 0x21, 0 - .dw 0xaec0, 0xc99e, 0xaeff, 0xc99e, 0x21, 0 - .dw 0xaf40, 0xc99e, 0xaf7f, 0xc99e, 0x21, 0 - .dw 0xafc0, 0xc99e, 0xafff, 0xc99e, 0x21, 0 - .dw 0xb040, 0xc99e, 0xb07f, 0xc99e, 0x21, 0 - .dw 0xb0c0, 0xc99e, 0xb0ff, 0xc99e, 0x21, 0 - .dw 0xb140, 0xc99e, 0xb17f, 0xc99e, 0x21, 0 - .dw 0xb1c0, 0xc99e, 0xb1ff, 0xc99e, 0x21, 0 - .dw 0xb240, 0xc99e, 0xb27f, 0xc99e, 0x21, 0 - .dw 0xb2c0, 0xc99e, 0xb2ff, 0xc99e, 0x21, 0 - .dw 0xb340, 0xc99e, 0xb37f, 0xc99e, 0x21, 0 - .dw 0xb3c0, 0xc99e, 0xb3ff, 0xc99e, 0x21, 0 - .dw 0xb440, 0xc99e, 0xb47f, 0xc99e, 0x21, 0 - .dw 0xb4c0, 0xc99e, 0xb4ff, 0xc99e, 0x21, 0 - .dw 0xb540, 0xc99e, 0xb57f, 0xc99e, 0x21, 0 - .dw 0xb5c0, 0xc99e, 0xb5ff, 0xc99e, 0x21, 0 - .dw 0xb640, 0xc99e, 0xb67f, 0xc99e, 0x21, 0 - .dw 0xb6c0, 0xc99e, 0xb6ff, 0xc99e, 0x21, 0 - .dw 0xb740, 0xc99e, 0xb77f, 0xc99e, 0x21, 0 - .dw 0xb7c0, 0xc99e, 0xb7ff, 0xc99e, 0x21, 0 - .dw 0xb840, 0xc99e, 0xb87f, 0xc99e, 0x21, 0 - .dw 0xb8c0, 0xc99e, 0xb8ff, 0xc99e, 0x21, 0 - .dw 0xb940, 0xc99e, 0xb97f, 0xc99e, 0x21, 0 - .dw 0xb9c0, 0xc99e, 0xbfff, 0xc99e, 0x21, 0 - .dw 0xc040, 0xc99e, 0xc07f, 0xc99e, 0x21, 0 - .dw 0xc0c0, 0xc99e, 0xc0ff, 0xc99e, 0x21, 0 - .dw 0xc140, 0xc99e, 0xc17f, 0xc99e, 0x21, 0 - .dw 0xc1c0, 0xc99e, 0xc1ff, 0xc99e, 0x21, 0 - .dw 0xc240, 0xc99e, 0xc27f, 0xc99e, 0x21, 0 - .dw 0xc2c0, 0xc99e, 0xc2ff, 0xc99e, 0x21, 0 - .dw 0xc340, 0xc99e, 0xc37f, 0xc99e, 0x21, 0 - .dw 0xc3c0, 0xc99e, 0xc3ff, 0xc99e, 0x21, 0 - .dw 0xc440, 0xc99e, 0xc47f, 0xc99e, 0x21, 0 - .dw 0xc4c0, 0xc99e, 0xc4ff, 0xc99e, 0x21, 0 - .dw 0xc540, 0xc99e, 0xc57f, 0xc99e, 0x21, 0 - .dw 0xc5c0, 0xc99e, 0xc5ff, 0xc99e, 0x21, 0 - .dw 0xc640, 0xc99e, 0xc67f, 0xc99e, 0x21, 0 - .dw 0xc6c0, 0xc99e, 0xc6ff, 0xc99e, 0x21, 0 - .dw 0xc740, 0xc99e, 0xc77f, 0xc99e, 0x21, 0 - .dw 0xc7c0, 0xc99e, 0xc7ff, 0xc99e, 0x21, 0 - .dw 0xc840, 0xc99e, 0xc87f, 0xc99e, 0x21, 0 - .dw 0xc8c0, 0xc99e, 0xc8ff, 0xc99e, 0x21, 0 - .dw 0xc940, 0xc99e, 0xc97f, 0xc99e, 0x21, 0 - .dw 0xc9c0, 0xc99e, 0xc9ff, 0xc99e, 0x21, 0 - .dw 0xca40, 0xc99e, 0xca7f, 0xc99e, 0x21, 0 - .dw 0xcac0, 0xc99e, 0xcaff, 0xc99e, 0x21, 0 - .dw 0xcb40, 0xc99e, 0xcb7f, 0xc99e, 0x21, 0 - .dw 0xcbc0, 0xc99e, 0xcbff, 0xc99e, 0x21, 0 - .dw 0xcc40, 0xc99e, 0xcc7f, 0xc99e, 0x21, 0 - .dw 0xccc0, 0xc99e, 0xccff, 0xc99e, 0x21, 0 - .dw 0xcd40, 0xc99e, 0xcd7f, 0xc99e, 0x21, 0 - .dw 0xcdc0, 0xc99e, 0xcdff, 0xc99e, 0x21, 0 - .dw 0xce40, 0xc99e, 0xce7f, 0xc99e, 0x21, 0 - .dw 0xcec0, 0xc99e, 0xceff, 0xc99e, 0x21, 0 - .dw 0xcf40, 0xc99e, 0xcf7f, 0xc99e, 0x21, 0 - .dw 0xcfc0, 0xc99e, 0xcfff, 0xc99e, 0x21, 0 - .dw 0xd040, 0xc99e, 0xd07f, 0xc99e, 0x21, 0 - .dw 0xd0c0, 0xc99e, 0xd0ff, 0xc99e, 0x21, 0 - .dw 0xd140, 0xc99e, 0xd17f, 0xc99e, 0x21, 0 - .dw 0xd1c0, 0xc99e, 0xd1ff, 0xc99e, 0x21, 0 - .dw 0xd240, 0xc99e, 0xd27f, 0xc99e, 0x21, 0 - .dw 0xd2c0, 0xc99e, 0xd2ff, 0xc99e, 0x21, 0 - .dw 0xd340, 0xc99e, 0xd37f, 0xc99e, 0x21, 0 - .dw 0xd3c0, 0xc99e, 0xd3ff, 0xc99e, 0x21, 0 - .dw 0xd440, 0xc99e, 0xd47f, 0xc99e, 0x21, 0 - .dw 0xd4c0, 0xc99e, 0xd4ff, 0xc99e, 0x21, 0 - .dw 0xd540, 0xc99e, 0xd57f, 0xc99e, 0x21, 0 - .dw 0xd5c0, 0xc99e, 0xd5ff, 0xc99e, 0x21, 0 - .dw 0xd640, 0xc99e, 0xd67f, 0xc99e, 0x21, 0 - .dw 0xd6c0, 0xc99e, 0xd6ff, 0xc99e, 0x21, 0 - .dw 0xd740, 0xc99e, 0xd77f, 0xc99e, 0x21, 0 - .dw 0xd7c0, 0xc99e, 0xd7ff, 0xc99e, 0x21, 0 - .dw 0xd840, 0xc99e, 0xd87f, 0xc99e, 0x21, 0 - .dw 0xd8c0, 0xc99e, 0xd8ff, 0xc99e, 0x21, 0 - .dw 0xd940, 0xc99e, 0xd97f, 0xc99e, 0x21, 0 - .dw 0xd9c0, 0xc99e, 0xdfff, 0xc99e, 0x21, 0 - .dw 0xe040, 0xc99e, 0xe07f, 0xc99e, 0x21, 0 - .dw 0xe0c0, 0xc99e, 0xe0ff, 0xc99e, 0x21, 0 - .dw 0xe140, 0xc99e, 0xe17f, 0xc99e, 0x21, 0 - .dw 0xe1c0, 0xc99e, 0xe1ff, 0xc99e, 0x21, 0 - .dw 0xe240, 0xc99e, 0xe27f, 0xc99e, 0x21, 0 - .dw 0xe2c0, 0xc99e, 0xe2ff, 0xc99e, 0x21, 0 - .dw 0xe340, 0xc99e, 0xe37f, 0xc99e, 0x21, 0 - .dw 0xe3c0, 0xc99e, 0xe3ff, 0xc99e, 0x21, 0 - .dw 0xe440, 0xc99e, 0xe47f, 0xc99e, 0x21, 0 - .dw 0xe4c0, 0xc99e, 0xe4ff, 0xc99e, 0x21, 0 - .dw 0xe540, 0xc99e, 0xe57f, 0xc99e, 0x21, 0 - .dw 0xe5c0, 0xc99e, 0xe5ff, 0xc99e, 0x21, 0 - .dw 0xe640, 0xc99e, 0xe67f, 0xc99e, 0x21, 0 - .dw 0xe6c0, 0xc99e, 0xe6ff, 0xc99e, 0x21, 0 - .dw 0xe740, 0xc99e, 0xe77f, 0xc99e, 0x21, 0 - .dw 0xe7c0, 0xc99e, 0xe7ff, 0xc99e, 0x21, 0 - .dw 0xe840, 0xc99e, 0xe87f, 0xc99e, 0x21, 0 - .dw 0xe8c0, 0xc99e, 0xe8ff, 0xc99e, 0x21, 0 - .dw 0xe940, 0xc99e, 0xe97f, 0xc99e, 0x21, 0 - .dw 0xe9c0, 0xc99e, 0xe9ff, 0xc99e, 0x21, 0 - .dw 0xea40, 0xc99e, 0xea7f, 0xc99e, 0x21, 0 - .dw 0xeac0, 0xc99e, 0xeaff, 0xc99e, 0x21, 0 - .dw 0xeb40, 0xc99e, 0xeb7f, 0xc99e, 0x21, 0 - .dw 0xebc0, 0xc99e, 0xebff, 0xc99e, 0x21, 0 - .dw 0xec40, 0xc99e, 0xec7f, 0xc99e, 0x21, 0 - .dw 0xecc0, 0xc99e, 0xecff, 0xc99e, 0x21, 0 - .dw 0xed40, 0xc99e, 0xed7f, 0xc99e, 0x21, 0 - .dw 0xedc0, 0xc99e, 0xedff, 0xc99e, 0x21, 0 - .dw 0xee40, 0xc99e, 0xee7f, 0xc99e, 0x21, 0 - .dw 0xeec0, 0xc99e, 0xeeff, 0xc99e, 0x21, 0 - .dw 0xef40, 0xc99e, 0xef7f, 0xc99e, 0x21, 0 - .dw 0xefc0, 0xc99e, 0xefff, 0xc99e, 0x21, 0 - .dw 0xf040, 0xc99e, 0xf07f, 0xc99e, 0x21, 0 - .dw 0xf0c0, 0xc99e, 0xf0ff, 0xc99e, 0x21, 0 - .dw 0xf140, 0xc99e, 0xf17f, 0xc99e, 0x21, 0 - .dw 0xf1c0, 0xc99e, 0xf1ff, 0xc99e, 0x21, 0 - .dw 0xf240, 0xc99e, 0xf27f, 0xc99e, 0x21, 0 - .dw 0xf2c0, 0xc99e, 0xf2ff, 0xc99e, 0x21, 0 - .dw 0xf340, 0xc99e, 0xf37f, 0xc99e, 0x21, 0 - .dw 0xf3c0, 0xc99e, 0xf3ff, 0xc99e, 0x21, 0 - .dw 0xf440, 0xc99e, 0xf47f, 0xc99e, 0x21, 0 - .dw 0xf4c0, 0xc99e, 0xf4ff, 0xc99e, 0x21, 0 - .dw 0xf540, 0xc99e, 0xf57f, 0xc99e, 0x21, 0 - .dw 0xf5c0, 0xc99e, 0xf5ff, 0xc99e, 0x21, 0 - .dw 0xf640, 0xc99e, 0xf67f, 0xc99e, 0x21, 0 - .dw 0xf6c0, 0xc99e, 0xf6ff, 0xc99e, 0x21, 0 - .dw 0xf740, 0xc99e, 0xf77f, 0xc99e, 0x21, 0 - .dw 0xf7c0, 0xc99e, 0xf7ff, 0xc99e, 0x21, 0 - .dw 0xf840, 0xc99e, 0xf87f, 0xc99e, 0x21, 0 - .dw 0xf8c0, 0xc99e, 0xf8ff, 0xc99e, 0x21, 0 - .dw 0xf940, 0xc99e, 0xf97f, 0xc99e, 0x21, 0 - .dw 0xf9c0, 0xc99e, 0xffff, 0xc99e, 0x21, 0 - .dw 0x0040, 0xc99f, 0x007f, 0xc99f, 0x21, 0 - .dw 0x00c0, 0xc99f, 0x00ff, 0xc99f, 0x21, 0 - .dw 0x0140, 0xc99f, 0x017f, 0xc99f, 0x21, 0 - .dw 0x01c0, 0xc99f, 0x01ff, 0xc99f, 0x21, 0 - .dw 0x0240, 0xc99f, 0x027f, 0xc99f, 0x21, 0 - .dw 0x02c0, 0xc99f, 0x02ff, 0xc99f, 0x21, 0 - .dw 0x0340, 0xc99f, 0x037f, 0xc99f, 0x21, 0 - .dw 0x03c0, 0xc99f, 0x03ff, 0xc99f, 0x21, 0 - .dw 0x0440, 0xc99f, 0x047f, 0xc99f, 0x21, 0 - .dw 0x04c0, 0xc99f, 0x04ff, 0xc99f, 0x21, 0 - .dw 0x0540, 0xc99f, 0x057f, 0xc99f, 0x21, 0 - .dw 0x05c0, 0xc99f, 0x05ff, 0xc99f, 0x21, 0 - .dw 0x0640, 0xc99f, 0x067f, 0xc99f, 0x21, 0 - .dw 0x06c0, 0xc99f, 0x06ff, 0xc99f, 0x21, 0 - .dw 0x0740, 0xc99f, 0x077f, 0xc99f, 0x21, 0 - .dw 0x07c0, 0xc99f, 0x07ff, 0xc99f, 0x21, 0 - .dw 0x0840, 0xc99f, 0x087f, 0xc99f, 0x21, 0 - .dw 0x08c0, 0xc99f, 0x08ff, 0xc99f, 0x21, 0 - .dw 0x0940, 0xc99f, 0x097f, 0xc99f, 0x21, 0 - .dw 0x09c0, 0xc99f, 0x09ff, 0xc99f, 0x21, 0 - .dw 0x0a40, 0xc99f, 0x0a7f, 0xc99f, 0x21, 0 - .dw 0x0ac0, 0xc99f, 0x0aff, 0xc99f, 0x21, 0 - .dw 0x0b40, 0xc99f, 0x0b7f, 0xc99f, 0x21, 0 - .dw 0x0bc0, 0xc99f, 0x0bff, 0xc99f, 0x21, 0 - .dw 0x0c40, 0xc99f, 0x0c7f, 0xc99f, 0x21, 0 - .dw 0x0cc0, 0xc99f, 0x0cff, 0xc99f, 0x21, 0 - .dw 0x0d40, 0xc99f, 0x0d7f, 0xc99f, 0x21, 0 - .dw 0x0dc0, 0xc99f, 0x0dff, 0xc99f, 0x21, 0 - .dw 0x0e40, 0xc99f, 0x0e7f, 0xc99f, 0x21, 0 - .dw 0x0ec0, 0xc99f, 0x0eff, 0xc99f, 0x21, 0 - .dw 0x0f40, 0xc99f, 0x0f7f, 0xc99f, 0x21, 0 - .dw 0x0fc0, 0xc99f, 0x0fff, 0xc99f, 0x21, 0 - .dw 0x1040, 0xc99f, 0x107f, 0xc99f, 0x21, 0 - .dw 0x10c0, 0xc99f, 0x10ff, 0xc99f, 0x21, 0 - .dw 0x1140, 0xc99f, 0x117f, 0xc99f, 0x21, 0 - .dw 0x11c0, 0xc99f, 0x11ff, 0xc99f, 0x21, 0 - .dw 0x1240, 0xc99f, 0x127f, 0xc99f, 0x21, 0 - .dw 0x12c0, 0xc99f, 0x12ff, 0xc99f, 0x21, 0 - .dw 0x1340, 0xc99f, 0x137f, 0xc99f, 0x21, 0 - .dw 0x13c0, 0xc99f, 0x13ff, 0xc99f, 0x21, 0 - .dw 0x1440, 0xc99f, 0x147f, 0xc99f, 0x21, 0 - .dw 0x14c0, 0xc99f, 0x14ff, 0xc99f, 0x21, 0 - .dw 0x1540, 0xc99f, 0x157f, 0xc99f, 0x21, 0 - .dw 0x15c0, 0xc99f, 0x15ff, 0xc99f, 0x21, 0 - .dw 0x1640, 0xc99f, 0x167f, 0xc99f, 0x21, 0 - .dw 0x16c0, 0xc99f, 0x16ff, 0xc99f, 0x21, 0 - .dw 0x1740, 0xc99f, 0x177f, 0xc99f, 0x21, 0 - .dw 0x17c0, 0xc99f, 0x17ff, 0xc99f, 0x21, 0 - .dw 0x1840, 0xc99f, 0x187f, 0xc99f, 0x21, 0 - .dw 0x18c0, 0xc99f, 0x18ff, 0xc99f, 0x21, 0 - .dw 0x1940, 0xc99f, 0x197f, 0xc99f, 0x21, 0 - .dw 0x19c0, 0xc99f, 0x1fff, 0xc99f, 0x21, 0 - .dw 0x2040, 0xc99f, 0x207f, 0xc99f, 0x21, 0 - .dw 0x20c0, 0xc99f, 0x20ff, 0xc99f, 0x21, 0 - .dw 0x2140, 0xc99f, 0x217f, 0xc99f, 0x21, 0 - .dw 0x21c0, 0xc99f, 0x21ff, 0xc99f, 0x21, 0 - .dw 0x2240, 0xc99f, 0x227f, 0xc99f, 0x21, 0 - .dw 0x22c0, 0xc99f, 0x22ff, 0xc99f, 0x21, 0 - .dw 0x2340, 0xc99f, 0x237f, 0xc99f, 0x21, 0 - .dw 0x23c0, 0xc99f, 0x23ff, 0xc99f, 0x21, 0 - .dw 0x2440, 0xc99f, 0x247f, 0xc99f, 0x21, 0 - .dw 0x24c0, 0xc99f, 0x24ff, 0xc99f, 0x21, 0 - .dw 0x2540, 0xc99f, 0x257f, 0xc99f, 0x21, 0 - .dw 0x25c0, 0xc99f, 0x25ff, 0xc99f, 0x21, 0 - .dw 0x2640, 0xc99f, 0x267f, 0xc99f, 0x21, 0 - .dw 0x26c0, 0xc99f, 0x26ff, 0xc99f, 0x21, 0 - .dw 0x2740, 0xc99f, 0x277f, 0xc99f, 0x21, 0 - .dw 0x27c0, 0xc99f, 0x27ff, 0xc99f, 0x21, 0 - .dw 0x2840, 0xc99f, 0x287f, 0xc99f, 0x21, 0 - .dw 0x28c0, 0xc99f, 0x28ff, 0xc99f, 0x21, 0 - .dw 0x2940, 0xc99f, 0x297f, 0xc99f, 0x21, 0 - .dw 0x29c0, 0xc99f, 0x29ff, 0xc99f, 0x21, 0 - .dw 0x2a40, 0xc99f, 0x2a7f, 0xc99f, 0x21, 0 - .dw 0x2ac0, 0xc99f, 0x2aff, 0xc99f, 0x21, 0 - .dw 0x2b40, 0xc99f, 0x2b7f, 0xc99f, 0x21, 0 - .dw 0x2bc0, 0xc99f, 0x2bff, 0xc99f, 0x21, 0 - .dw 0x2c40, 0xc99f, 0x2c7f, 0xc99f, 0x21, 0 - .dw 0x2cc0, 0xc99f, 0x2cff, 0xc99f, 0x21, 0 - .dw 0x2d40, 0xc99f, 0x2d7f, 0xc99f, 0x21, 0 - .dw 0x2dc0, 0xc99f, 0x2dff, 0xc99f, 0x21, 0 - .dw 0x2e40, 0xc99f, 0x2e7f, 0xc99f, 0x21, 0 - .dw 0x2ec0, 0xc99f, 0x2eff, 0xc99f, 0x21, 0 - .dw 0x2f40, 0xc99f, 0x2f7f, 0xc99f, 0x21, 0 - .dw 0x2fc0, 0xc99f, 0x2fff, 0xc99f, 0x21, 0 - .dw 0x3040, 0xc99f, 0x307f, 0xc99f, 0x21, 0 - .dw 0x30c0, 0xc99f, 0x30ff, 0xc99f, 0x21, 0 - .dw 0x3140, 0xc99f, 0x317f, 0xc99f, 0x21, 0 - .dw 0x31c0, 0xc99f, 0x31ff, 0xc99f, 0x21, 0 - .dw 0x3240, 0xc99f, 0x327f, 0xc99f, 0x21, 0 - .dw 0x32c0, 0xc99f, 0x32ff, 0xc99f, 0x21, 0 - .dw 0x3340, 0xc99f, 0x337f, 0xc99f, 0x21, 0 - .dw 0x33c0, 0xc99f, 0x33ff, 0xc99f, 0x21, 0 - .dw 0x3440, 0xc99f, 0x347f, 0xc99f, 0x21, 0 - .dw 0x34c0, 0xc99f, 0x34ff, 0xc99f, 0x21, 0 - .dw 0x3540, 0xc99f, 0x357f, 0xc99f, 0x21, 0 - .dw 0x35c0, 0xc99f, 0x35ff, 0xc99f, 0x21, 0 - .dw 0x3640, 0xc99f, 0x367f, 0xc99f, 0x21, 0 - .dw 0x36c0, 0xc99f, 0x36ff, 0xc99f, 0x21, 0 - .dw 0x3740, 0xc99f, 0x377f, 0xc99f, 0x21, 0 - .dw 0x37c0, 0xc99f, 0x37ff, 0xc99f, 0x21, 0 - .dw 0x3840, 0xc99f, 0x387f, 0xc99f, 0x21, 0 - .dw 0x38c0, 0xc99f, 0x38ff, 0xc99f, 0x21, 0 - .dw 0x3940, 0xc99f, 0x397f, 0xc99f, 0x21, 0 - .dw 0x39c0, 0xc99f, 0x1fff, 0xca00, 0x21, 0 - .dw 0x2800, 0xca00, 0xffff, 0xca03, 0x21, 0 - .dw 0x0200, 0xca04, 0x1fff, 0xca04, 0x21, 0 - .dw 0x2800, 0xca04, 0x3fff, 0xca04, 0x21, 0 - .dw 0x4200, 0xca04, 0x5fff, 0xca04, 0x21, 0 - .dw 0x6800, 0xca04, 0x7fff, 0xca04, 0x21, 0 - .dw 0x8200, 0xca04, 0x9fff, 0xca04, 0x21, 0 - .dw 0xa800, 0xca04, 0xbfff, 0xca04, 0x21, 0 - .dw 0xc200, 0xca04, 0xdfff, 0xca04, 0x21, 0 - .dw 0xe800, 0xca04, 0x1fff, 0xca08, 0x21, 0 - .dw 0x2040, 0xca08, 0x207f, 0xca08, 0x21, 0 - .dw 0x20c0, 0xca08, 0x20ff, 0xca08, 0x21, 0 - .dw 0x2140, 0xca08, 0x217f, 0xca08, 0x21, 0 - .dw 0x21c0, 0xca08, 0x21ff, 0xca08, 0x21, 0 - .dw 0x2240, 0xca08, 0x227f, 0xca08, 0x21, 0 - .dw 0x22c0, 0xca08, 0x22ff, 0xca08, 0x21, 0 - .dw 0x2340, 0xca08, 0x237f, 0xca08, 0x21, 0 - .dw 0x23c0, 0xca08, 0x23ff, 0xca08, 0x21, 0 - .dw 0x2440, 0xca08, 0x247f, 0xca08, 0x21, 0 - .dw 0x24c0, 0xca08, 0x24ff, 0xca08, 0x21, 0 - .dw 0x2540, 0xca08, 0x257f, 0xca08, 0x21, 0 - .dw 0x25c0, 0xca08, 0x25ff, 0xca08, 0x21, 0 - .dw 0x2640, 0xca08, 0x267f, 0xca08, 0x21, 0 - .dw 0x26c0, 0xca08, 0x26ff, 0xca08, 0x21, 0 - .dw 0x2740, 0xca08, 0x277f, 0xca08, 0x21, 0 - .dw 0x27c0, 0xca08, 0xffff, 0xca0b, 0x21, 0 - .dw 0x0040, 0xca0c, 0x007f, 0xca0c, 0x21, 0 - .dw 0x00c0, 0xca0c, 0x00ff, 0xca0c, 0x21, 0 - .dw 0x0140, 0xca0c, 0x017f, 0xca0c, 0x21, 0 - .dw 0x01c0, 0xca0c, 0x1fff, 0xca0c, 0x21, 0 - .dw 0x2040, 0xca0c, 0x207f, 0xca0c, 0x21, 0 - .dw 0x20c0, 0xca0c, 0x20ff, 0xca0c, 0x21, 0 - .dw 0x2140, 0xca0c, 0x217f, 0xca0c, 0x21, 0 - .dw 0x21c0, 0xca0c, 0x21ff, 0xca0c, 0x21, 0 - .dw 0x2240, 0xca0c, 0x227f, 0xca0c, 0x21, 0 - .dw 0x22c0, 0xca0c, 0x22ff, 0xca0c, 0x21, 0 - .dw 0x2340, 0xca0c, 0x237f, 0xca0c, 0x21, 0 - .dw 0x23c0, 0xca0c, 0x23ff, 0xca0c, 0x21, 0 - .dw 0x2440, 0xca0c, 0x247f, 0xca0c, 0x21, 0 - .dw 0x24c0, 0xca0c, 0x24ff, 0xca0c, 0x21, 0 - .dw 0x2540, 0xca0c, 0x257f, 0xca0c, 0x21, 0 - .dw 0x25c0, 0xca0c, 0x25ff, 0xca0c, 0x21, 0 - .dw 0x2640, 0xca0c, 0x267f, 0xca0c, 0x21, 0 - .dw 0x26c0, 0xca0c, 0x26ff, 0xca0c, 0x21, 0 - .dw 0x2740, 0xca0c, 0x277f, 0xca0c, 0x21, 0 - .dw 0x27c0, 0xca0c, 0x3fff, 0xca0c, 0x21, 0 - .dw 0x4040, 0xca0c, 0x407f, 0xca0c, 0x21, 0 - .dw 0x40c0, 0xca0c, 0x40ff, 0xca0c, 0x21, 0 - .dw 0x4140, 0xca0c, 0x417f, 0xca0c, 0x21, 0 - .dw 0x41c0, 0xca0c, 0x5fff, 0xca0c, 0x21, 0 - .dw 0x6040, 0xca0c, 0x607f, 0xca0c, 0x21, 0 - .dw 0x60c0, 0xca0c, 0x60ff, 0xca0c, 0x21, 0 - .dw 0x6140, 0xca0c, 0x617f, 0xca0c, 0x21, 0 - .dw 0x61c0, 0xca0c, 0x61ff, 0xca0c, 0x21, 0 - .dw 0x6240, 0xca0c, 0x627f, 0xca0c, 0x21, 0 - .dw 0x62c0, 0xca0c, 0x62ff, 0xca0c, 0x21, 0 - .dw 0x6340, 0xca0c, 0x637f, 0xca0c, 0x21, 0 - .dw 0x63c0, 0xca0c, 0x63ff, 0xca0c, 0x21, 0 - .dw 0x6440, 0xca0c, 0x647f, 0xca0c, 0x21, 0 - .dw 0x64c0, 0xca0c, 0x64ff, 0xca0c, 0x21, 0 - .dw 0x6540, 0xca0c, 0x657f, 0xca0c, 0x21, 0 - .dw 0x65c0, 0xca0c, 0x65ff, 0xca0c, 0x21, 0 - .dw 0x6640, 0xca0c, 0x667f, 0xca0c, 0x21, 0 - .dw 0x66c0, 0xca0c, 0x66ff, 0xca0c, 0x21, 0 - .dw 0x6740, 0xca0c, 0x677f, 0xca0c, 0x21, 0 - .dw 0x67c0, 0xca0c, 0x7fff, 0xca0c, 0x21, 0 - .dw 0x8040, 0xca0c, 0x807f, 0xca0c, 0x21, 0 - .dw 0x80c0, 0xca0c, 0x80ff, 0xca0c, 0x21, 0 - .dw 0x8140, 0xca0c, 0x817f, 0xca0c, 0x21, 0 - .dw 0x81c0, 0xca0c, 0x9fff, 0xca0c, 0x21, 0 - .dw 0xa040, 0xca0c, 0xa07f, 0xca0c, 0x21, 0 - .dw 0xa0c0, 0xca0c, 0xa0ff, 0xca0c, 0x21, 0 - .dw 0xa140, 0xca0c, 0xa17f, 0xca0c, 0x21, 0 - .dw 0xa1c0, 0xca0c, 0xa1ff, 0xca0c, 0x21, 0 - .dw 0xa240, 0xca0c, 0xa27f, 0xca0c, 0x21, 0 - .dw 0xa2c0, 0xca0c, 0xa2ff, 0xca0c, 0x21, 0 - .dw 0xa340, 0xca0c, 0xa37f, 0xca0c, 0x21, 0 - .dw 0xa3c0, 0xca0c, 0xa3ff, 0xca0c, 0x21, 0 - .dw 0xa440, 0xca0c, 0xa47f, 0xca0c, 0x21, 0 - .dw 0xa4c0, 0xca0c, 0xa4ff, 0xca0c, 0x21, 0 - .dw 0xa540, 0xca0c, 0xa57f, 0xca0c, 0x21, 0 - .dw 0xa5c0, 0xca0c, 0xa5ff, 0xca0c, 0x21, 0 - .dw 0xa640, 0xca0c, 0xa67f, 0xca0c, 0x21, 0 - .dw 0xa6c0, 0xca0c, 0xa6ff, 0xca0c, 0x21, 0 - .dw 0xa740, 0xca0c, 0xa77f, 0xca0c, 0x21, 0 - .dw 0xa7c0, 0xca0c, 0xbfff, 0xca0c, 0x21, 0 - .dw 0xc040, 0xca0c, 0xc07f, 0xca0c, 0x21, 0 - .dw 0xc0c0, 0xca0c, 0xc0ff, 0xca0c, 0x21, 0 - .dw 0xc140, 0xca0c, 0xc17f, 0xca0c, 0x21, 0 - .dw 0xc1c0, 0xca0c, 0xdfff, 0xca0c, 0x21, 0 - .dw 0xe040, 0xca0c, 0xe07f, 0xca0c, 0x21, 0 - .dw 0xe0c0, 0xca0c, 0xe0ff, 0xca0c, 0x21, 0 - .dw 0xe140, 0xca0c, 0xe17f, 0xca0c, 0x21, 0 - .dw 0xe1c0, 0xca0c, 0xe1ff, 0xca0c, 0x21, 0 - .dw 0xe240, 0xca0c, 0xe27f, 0xca0c, 0x21, 0 - .dw 0xe2c0, 0xca0c, 0xe2ff, 0xca0c, 0x21, 0 - .dw 0xe340, 0xca0c, 0xe37f, 0xca0c, 0x21, 0 - .dw 0xe3c0, 0xca0c, 0xe3ff, 0xca0c, 0x21, 0 - .dw 0xe440, 0xca0c, 0xe47f, 0xca0c, 0x21, 0 - .dw 0xe4c0, 0xca0c, 0xe4ff, 0xca0c, 0x21, 0 - .dw 0xe540, 0xca0c, 0xe57f, 0xca0c, 0x21, 0 - .dw 0xe5c0, 0xca0c, 0xe5ff, 0xca0c, 0x21, 0 - .dw 0xe640, 0xca0c, 0xe67f, 0xca0c, 0x21, 0 - .dw 0xe6c0, 0xca0c, 0xe6ff, 0xca0c, 0x21, 0 - .dw 0xe740, 0xca0c, 0xe77f, 0xca0c, 0x21, 0 - .dw 0xe7c0, 0xca0c, 0xffff, 0xca13, 0x21, 0 - .dw 0x0200, 0xca14, 0x1fff, 0xca14, 0x21, 0 - .dw 0x2800, 0xca14, 0x3fff, 0xca14, 0x21, 0 - .dw 0x4200, 0xca14, 0x5fff, 0xca14, 0x21, 0 - .dw 0x6800, 0xca14, 0x7fff, 0xca14, 0x21, 0 - .dw 0x8200, 0xca14, 0x9fff, 0xca14, 0x21, 0 - .dw 0xa800, 0xca14, 0xbfff, 0xca14, 0x21, 0 - .dw 0xc200, 0xca14, 0xdfff, 0xca14, 0x21, 0 - .dw 0xe800, 0xca14, 0xffff, 0xca1b, 0x21, 0 - .dw 0x0040, 0xca1c, 0x007f, 0xca1c, 0x21, 0 - .dw 0x00c0, 0xca1c, 0x00ff, 0xca1c, 0x21, 0 - .dw 0x0140, 0xca1c, 0x017f, 0xca1c, 0x21, 0 - .dw 0x01c0, 0xca1c, 0x1fff, 0xca1c, 0x21, 0 - .dw 0x2040, 0xca1c, 0x207f, 0xca1c, 0x21, 0 - .dw 0x20c0, 0xca1c, 0x20ff, 0xca1c, 0x21, 0 - .dw 0x2140, 0xca1c, 0x217f, 0xca1c, 0x21, 0 - .dw 0x21c0, 0xca1c, 0x21ff, 0xca1c, 0x21, 0 - .dw 0x2240, 0xca1c, 0x227f, 0xca1c, 0x21, 0 - .dw 0x22c0, 0xca1c, 0x22ff, 0xca1c, 0x21, 0 - .dw 0x2340, 0xca1c, 0x237f, 0xca1c, 0x21, 0 - .dw 0x23c0, 0xca1c, 0x23ff, 0xca1c, 0x21, 0 - .dw 0x2440, 0xca1c, 0x247f, 0xca1c, 0x21, 0 - .dw 0x24c0, 0xca1c, 0x24ff, 0xca1c, 0x21, 0 - .dw 0x2540, 0xca1c, 0x257f, 0xca1c, 0x21, 0 - .dw 0x25c0, 0xca1c, 0x25ff, 0xca1c, 0x21, 0 - .dw 0x2640, 0xca1c, 0x267f, 0xca1c, 0x21, 0 - .dw 0x26c0, 0xca1c, 0x26ff, 0xca1c, 0x21, 0 - .dw 0x2740, 0xca1c, 0x277f, 0xca1c, 0x21, 0 - .dw 0x27c0, 0xca1c, 0x3fff, 0xca1c, 0x21, 0 - .dw 0x4040, 0xca1c, 0x407f, 0xca1c, 0x21, 0 - .dw 0x40c0, 0xca1c, 0x40ff, 0xca1c, 0x21, 0 - .dw 0x4140, 0xca1c, 0x417f, 0xca1c, 0x21, 0 - .dw 0x41c0, 0xca1c, 0x5fff, 0xca1c, 0x21, 0 - .dw 0x6040, 0xca1c, 0x607f, 0xca1c, 0x21, 0 - .dw 0x60c0, 0xca1c, 0x60ff, 0xca1c, 0x21, 0 - .dw 0x6140, 0xca1c, 0x617f, 0xca1c, 0x21, 0 - .dw 0x61c0, 0xca1c, 0x61ff, 0xca1c, 0x21, 0 - .dw 0x6240, 0xca1c, 0x627f, 0xca1c, 0x21, 0 - .dw 0x62c0, 0xca1c, 0x62ff, 0xca1c, 0x21, 0 - .dw 0x6340, 0xca1c, 0x637f, 0xca1c, 0x21, 0 - .dw 0x63c0, 0xca1c, 0x63ff, 0xca1c, 0x21, 0 - .dw 0x6440, 0xca1c, 0x647f, 0xca1c, 0x21, 0 - .dw 0x64c0, 0xca1c, 0x64ff, 0xca1c, 0x21, 0 - .dw 0x6540, 0xca1c, 0x657f, 0xca1c, 0x21, 0 - .dw 0x65c0, 0xca1c, 0x65ff, 0xca1c, 0x21, 0 - .dw 0x6640, 0xca1c, 0x667f, 0xca1c, 0x21, 0 - .dw 0x66c0, 0xca1c, 0x66ff, 0xca1c, 0x21, 0 - .dw 0x6740, 0xca1c, 0x677f, 0xca1c, 0x21, 0 - .dw 0x67c0, 0xca1c, 0x7fff, 0xca1c, 0x21, 0 - .dw 0x8040, 0xca1c, 0x807f, 0xca1c, 0x21, 0 - .dw 0x80c0, 0xca1c, 0x80ff, 0xca1c, 0x21, 0 - .dw 0x8140, 0xca1c, 0x817f, 0xca1c, 0x21, 0 - .dw 0x81c0, 0xca1c, 0x9fff, 0xca1c, 0x21, 0 - .dw 0xa040, 0xca1c, 0xa07f, 0xca1c, 0x21, 0 - .dw 0xa0c0, 0xca1c, 0xa0ff, 0xca1c, 0x21, 0 - .dw 0xa140, 0xca1c, 0xa17f, 0xca1c, 0x21, 0 - .dw 0xa1c0, 0xca1c, 0xa1ff, 0xca1c, 0x21, 0 - .dw 0xa240, 0xca1c, 0xa27f, 0xca1c, 0x21, 0 - .dw 0xa2c0, 0xca1c, 0xa2ff, 0xca1c, 0x21, 0 - .dw 0xa340, 0xca1c, 0xa37f, 0xca1c, 0x21, 0 - .dw 0xa3c0, 0xca1c, 0xa3ff, 0xca1c, 0x21, 0 - .dw 0xa440, 0xca1c, 0xa47f, 0xca1c, 0x21, 0 - .dw 0xa4c0, 0xca1c, 0xa4ff, 0xca1c, 0x21, 0 - .dw 0xa540, 0xca1c, 0xa57f, 0xca1c, 0x21, 0 - .dw 0xa5c0, 0xca1c, 0xa5ff, 0xca1c, 0x21, 0 - .dw 0xa640, 0xca1c, 0xa67f, 0xca1c, 0x21, 0 - .dw 0xa6c0, 0xca1c, 0xa6ff, 0xca1c, 0x21, 0 - .dw 0xa740, 0xca1c, 0xa77f, 0xca1c, 0x21, 0 - .dw 0xa7c0, 0xca1c, 0xbfff, 0xca1c, 0x21, 0 - .dw 0xc040, 0xca1c, 0xc07f, 0xca1c, 0x21, 0 - .dw 0xc0c0, 0xca1c, 0xc0ff, 0xca1c, 0x21, 0 - .dw 0xc140, 0xca1c, 0xc17f, 0xca1c, 0x21, 0 - .dw 0xc1c0, 0xca1c, 0xdfff, 0xca1c, 0x21, 0 - .dw 0xe040, 0xca1c, 0xe07f, 0xca1c, 0x21, 0 - .dw 0xe0c0, 0xca1c, 0xe0ff, 0xca1c, 0x21, 0 - .dw 0xe140, 0xca1c, 0xe17f, 0xca1c, 0x21, 0 - .dw 0xe1c0, 0xca1c, 0xe1ff, 0xca1c, 0x21, 0 - .dw 0xe240, 0xca1c, 0xe27f, 0xca1c, 0x21, 0 - .dw 0xe2c0, 0xca1c, 0xe2ff, 0xca1c, 0x21, 0 - .dw 0xe340, 0xca1c, 0xe37f, 0xca1c, 0x21, 0 - .dw 0xe3c0, 0xca1c, 0xe3ff, 0xca1c, 0x21, 0 - .dw 0xe440, 0xca1c, 0xe47f, 0xca1c, 0x21, 0 - .dw 0xe4c0, 0xca1c, 0xe4ff, 0xca1c, 0x21, 0 - .dw 0xe540, 0xca1c, 0xe57f, 0xca1c, 0x21, 0 - .dw 0xe5c0, 0xca1c, 0xe5ff, 0xca1c, 0x21, 0 - .dw 0xe640, 0xca1c, 0xe67f, 0xca1c, 0x21, 0 - .dw 0xe6c0, 0xca1c, 0xe6ff, 0xca1c, 0x21, 0 - .dw 0xe740, 0xca1c, 0xe77f, 0xca1c, 0x21, 0 - .dw 0xe7c0, 0xca1c, 0x1fff, 0xca20, 0x21, 0 - .dw 0x2800, 0xca20, 0xffff, 0xca23, 0x21, 0 - .dw 0x0200, 0xca24, 0x1fff, 0xca24, 0x21, 0 - .dw 0x2800, 0xca24, 0x3fff, 0xca24, 0x21, 0 - .dw 0x4200, 0xca24, 0x5fff, 0xca24, 0x21, 0 - .dw 0x6800, 0xca24, 0x7fff, 0xca24, 0x21, 0 - .dw 0x8200, 0xca24, 0x9fff, 0xca24, 0x21, 0 - .dw 0xa800, 0xca24, 0xbfff, 0xca24, 0x21, 0 - .dw 0xc200, 0xca24, 0xdfff, 0xca24, 0x21, 0 - .dw 0xe800, 0xca24, 0x1fff, 0xca28, 0x21, 0 - .dw 0x2040, 0xca28, 0x207f, 0xca28, 0x21, 0 - .dw 0x20c0, 0xca28, 0x20ff, 0xca28, 0x21, 0 - .dw 0x2140, 0xca28, 0x217f, 0xca28, 0x21, 0 - .dw 0x21c0, 0xca28, 0x21ff, 0xca28, 0x21, 0 - .dw 0x2240, 0xca28, 0x227f, 0xca28, 0x21, 0 - .dw 0x22c0, 0xca28, 0x22ff, 0xca28, 0x21, 0 - .dw 0x2340, 0xca28, 0x237f, 0xca28, 0x21, 0 - .dw 0x23c0, 0xca28, 0x23ff, 0xca28, 0x21, 0 - .dw 0x2440, 0xca28, 0x247f, 0xca28, 0x21, 0 - .dw 0x24c0, 0xca28, 0x24ff, 0xca28, 0x21, 0 - .dw 0x2540, 0xca28, 0x257f, 0xca28, 0x21, 0 - .dw 0x25c0, 0xca28, 0x25ff, 0xca28, 0x21, 0 - .dw 0x2640, 0xca28, 0x267f, 0xca28, 0x21, 0 - .dw 0x26c0, 0xca28, 0x26ff, 0xca28, 0x21, 0 - .dw 0x2740, 0xca28, 0x277f, 0xca28, 0x21, 0 - .dw 0x27c0, 0xca28, 0xffff, 0xca2b, 0x21, 0 - .dw 0x0040, 0xca2c, 0x007f, 0xca2c, 0x21, 0 - .dw 0x00c0, 0xca2c, 0x00ff, 0xca2c, 0x21, 0 - .dw 0x0140, 0xca2c, 0x017f, 0xca2c, 0x21, 0 - .dw 0x01c0, 0xca2c, 0x1fff, 0xca2c, 0x21, 0 - .dw 0x2040, 0xca2c, 0x207f, 0xca2c, 0x21, 0 - .dw 0x20c0, 0xca2c, 0x20ff, 0xca2c, 0x21, 0 - .dw 0x2140, 0xca2c, 0x217f, 0xca2c, 0x21, 0 - .dw 0x21c0, 0xca2c, 0x21ff, 0xca2c, 0x21, 0 - .dw 0x2240, 0xca2c, 0x227f, 0xca2c, 0x21, 0 - .dw 0x22c0, 0xca2c, 0x22ff, 0xca2c, 0x21, 0 - .dw 0x2340, 0xca2c, 0x237f, 0xca2c, 0x21, 0 - .dw 0x23c0, 0xca2c, 0x23ff, 0xca2c, 0x21, 0 - .dw 0x2440, 0xca2c, 0x247f, 0xca2c, 0x21, 0 - .dw 0x24c0, 0xca2c, 0x24ff, 0xca2c, 0x21, 0 - .dw 0x2540, 0xca2c, 0x257f, 0xca2c, 0x21, 0 - .dw 0x25c0, 0xca2c, 0x25ff, 0xca2c, 0x21, 0 - .dw 0x2640, 0xca2c, 0x267f, 0xca2c, 0x21, 0 - .dw 0x26c0, 0xca2c, 0x26ff, 0xca2c, 0x21, 0 - .dw 0x2740, 0xca2c, 0x277f, 0xca2c, 0x21, 0 - .dw 0x27c0, 0xca2c, 0x3fff, 0xca2c, 0x21, 0 - .dw 0x4040, 0xca2c, 0x407f, 0xca2c, 0x21, 0 - .dw 0x40c0, 0xca2c, 0x40ff, 0xca2c, 0x21, 0 - .dw 0x4140, 0xca2c, 0x417f, 0xca2c, 0x21, 0 - .dw 0x41c0, 0xca2c, 0x5fff, 0xca2c, 0x21, 0 - .dw 0x6040, 0xca2c, 0x607f, 0xca2c, 0x21, 0 - .dw 0x60c0, 0xca2c, 0x60ff, 0xca2c, 0x21, 0 - .dw 0x6140, 0xca2c, 0x617f, 0xca2c, 0x21, 0 - .dw 0x61c0, 0xca2c, 0x61ff, 0xca2c, 0x21, 0 - .dw 0x6240, 0xca2c, 0x627f, 0xca2c, 0x21, 0 - .dw 0x62c0, 0xca2c, 0x62ff, 0xca2c, 0x21, 0 - .dw 0x6340, 0xca2c, 0x637f, 0xca2c, 0x21, 0 - .dw 0x63c0, 0xca2c, 0x63ff, 0xca2c, 0x21, 0 - .dw 0x6440, 0xca2c, 0x647f, 0xca2c, 0x21, 0 - .dw 0x64c0, 0xca2c, 0x64ff, 0xca2c, 0x21, 0 - .dw 0x6540, 0xca2c, 0x657f, 0xca2c, 0x21, 0 - .dw 0x65c0, 0xca2c, 0x65ff, 0xca2c, 0x21, 0 - .dw 0x6640, 0xca2c, 0x667f, 0xca2c, 0x21, 0 - .dw 0x66c0, 0xca2c, 0x66ff, 0xca2c, 0x21, 0 - .dw 0x6740, 0xca2c, 0x677f, 0xca2c, 0x21, 0 - .dw 0x67c0, 0xca2c, 0x7fff, 0xca2c, 0x21, 0 - .dw 0x8040, 0xca2c, 0x807f, 0xca2c, 0x21, 0 - .dw 0x80c0, 0xca2c, 0x80ff, 0xca2c, 0x21, 0 - .dw 0x8140, 0xca2c, 0x817f, 0xca2c, 0x21, 0 - .dw 0x81c0, 0xca2c, 0x9fff, 0xca2c, 0x21, 0 - .dw 0xa040, 0xca2c, 0xa07f, 0xca2c, 0x21, 0 - .dw 0xa0c0, 0xca2c, 0xa0ff, 0xca2c, 0x21, 0 - .dw 0xa140, 0xca2c, 0xa17f, 0xca2c, 0x21, 0 - .dw 0xa1c0, 0xca2c, 0xa1ff, 0xca2c, 0x21, 0 - .dw 0xa240, 0xca2c, 0xa27f, 0xca2c, 0x21, 0 - .dw 0xa2c0, 0xca2c, 0xa2ff, 0xca2c, 0x21, 0 - .dw 0xa340, 0xca2c, 0xa37f, 0xca2c, 0x21, 0 - .dw 0xa3c0, 0xca2c, 0xa3ff, 0xca2c, 0x21, 0 - .dw 0xa440, 0xca2c, 0xa47f, 0xca2c, 0x21, 0 - .dw 0xa4c0, 0xca2c, 0xa4ff, 0xca2c, 0x21, 0 - .dw 0xa540, 0xca2c, 0xa57f, 0xca2c, 0x21, 0 - .dw 0xa5c0, 0xca2c, 0xa5ff, 0xca2c, 0x21, 0 - .dw 0xa640, 0xca2c, 0xa67f, 0xca2c, 0x21, 0 - .dw 0xa6c0, 0xca2c, 0xa6ff, 0xca2c, 0x21, 0 - .dw 0xa740, 0xca2c, 0xa77f, 0xca2c, 0x21, 0 - .dw 0xa7c0, 0xca2c, 0xbfff, 0xca2c, 0x21, 0 - .dw 0xc040, 0xca2c, 0xc07f, 0xca2c, 0x21, 0 - .dw 0xc0c0, 0xca2c, 0xc0ff, 0xca2c, 0x21, 0 - .dw 0xc140, 0xca2c, 0xc17f, 0xca2c, 0x21, 0 - .dw 0xc1c0, 0xca2c, 0xdfff, 0xca2c, 0x21, 0 - .dw 0xe040, 0xca2c, 0xe07f, 0xca2c, 0x21, 0 - .dw 0xe0c0, 0xca2c, 0xe0ff, 0xca2c, 0x21, 0 - .dw 0xe140, 0xca2c, 0xe17f, 0xca2c, 0x21, 0 - .dw 0xe1c0, 0xca2c, 0xe1ff, 0xca2c, 0x21, 0 - .dw 0xe240, 0xca2c, 0xe27f, 0xca2c, 0x21, 0 - .dw 0xe2c0, 0xca2c, 0xe2ff, 0xca2c, 0x21, 0 - .dw 0xe340, 0xca2c, 0xe37f, 0xca2c, 0x21, 0 - .dw 0xe3c0, 0xca2c, 0xe3ff, 0xca2c, 0x21, 0 - .dw 0xe440, 0xca2c, 0xe47f, 0xca2c, 0x21, 0 - .dw 0xe4c0, 0xca2c, 0xe4ff, 0xca2c, 0x21, 0 - .dw 0xe540, 0xca2c, 0xe57f, 0xca2c, 0x21, 0 - .dw 0xe5c0, 0xca2c, 0xe5ff, 0xca2c, 0x21, 0 - .dw 0xe640, 0xca2c, 0xe67f, 0xca2c, 0x21, 0 - .dw 0xe6c0, 0xca2c, 0xe6ff, 0xca2c, 0x21, 0 - .dw 0xe740, 0xca2c, 0xe77f, 0xca2c, 0x21, 0 - .dw 0xe7c0, 0xca2c, 0xffff, 0xca33, 0x21, 0 - .dw 0x0200, 0xca34, 0x1fff, 0xca34, 0x21, 0 - .dw 0x2800, 0xca34, 0x3fff, 0xca34, 0x21, 0 - .dw 0x4200, 0xca34, 0x5fff, 0xca34, 0x21, 0 - .dw 0x6800, 0xca34, 0x7fff, 0xca34, 0x21, 0 - .dw 0x8200, 0xca34, 0x9fff, 0xca34, 0x21, 0 - .dw 0xa800, 0xca34, 0xbfff, 0xca34, 0x21, 0 - .dw 0xc200, 0xca34, 0xdfff, 0xca34, 0x21, 0 - .dw 0xe800, 0xca34, 0xffff, 0xca3b, 0x21, 0 - .dw 0x0040, 0xca3c, 0x007f, 0xca3c, 0x21, 0 - .dw 0x00c0, 0xca3c, 0x00ff, 0xca3c, 0x21, 0 - .dw 0x0140, 0xca3c, 0x017f, 0xca3c, 0x21, 0 - .dw 0x01c0, 0xca3c, 0x1fff, 0xca3c, 0x21, 0 - .dw 0x2040, 0xca3c, 0x207f, 0xca3c, 0x21, 0 - .dw 0x20c0, 0xca3c, 0x20ff, 0xca3c, 0x21, 0 - .dw 0x2140, 0xca3c, 0x217f, 0xca3c, 0x21, 0 - .dw 0x21c0, 0xca3c, 0x21ff, 0xca3c, 0x21, 0 - .dw 0x2240, 0xca3c, 0x227f, 0xca3c, 0x21, 0 - .dw 0x22c0, 0xca3c, 0x22ff, 0xca3c, 0x21, 0 - .dw 0x2340, 0xca3c, 0x237f, 0xca3c, 0x21, 0 - .dw 0x23c0, 0xca3c, 0x23ff, 0xca3c, 0x21, 0 - .dw 0x2440, 0xca3c, 0x247f, 0xca3c, 0x21, 0 - .dw 0x24c0, 0xca3c, 0x24ff, 0xca3c, 0x21, 0 - .dw 0x2540, 0xca3c, 0x257f, 0xca3c, 0x21, 0 - .dw 0x25c0, 0xca3c, 0x25ff, 0xca3c, 0x21, 0 - .dw 0x2640, 0xca3c, 0x267f, 0xca3c, 0x21, 0 - .dw 0x26c0, 0xca3c, 0x26ff, 0xca3c, 0x21, 0 - .dw 0x2740, 0xca3c, 0x277f, 0xca3c, 0x21, 0 - .dw 0x27c0, 0xca3c, 0x3fff, 0xca3c, 0x21, 0 - .dw 0x4040, 0xca3c, 0x407f, 0xca3c, 0x21, 0 - .dw 0x40c0, 0xca3c, 0x40ff, 0xca3c, 0x21, 0 - .dw 0x4140, 0xca3c, 0x417f, 0xca3c, 0x21, 0 - .dw 0x41c0, 0xca3c, 0x5fff, 0xca3c, 0x21, 0 - .dw 0x6040, 0xca3c, 0x607f, 0xca3c, 0x21, 0 - .dw 0x60c0, 0xca3c, 0x60ff, 0xca3c, 0x21, 0 - .dw 0x6140, 0xca3c, 0x617f, 0xca3c, 0x21, 0 - .dw 0x61c0, 0xca3c, 0x61ff, 0xca3c, 0x21, 0 - .dw 0x6240, 0xca3c, 0x627f, 0xca3c, 0x21, 0 - .dw 0x62c0, 0xca3c, 0x62ff, 0xca3c, 0x21, 0 - .dw 0x6340, 0xca3c, 0x637f, 0xca3c, 0x21, 0 - .dw 0x63c0, 0xca3c, 0x63ff, 0xca3c, 0x21, 0 - .dw 0x6440, 0xca3c, 0x647f, 0xca3c, 0x21, 0 - .dw 0x64c0, 0xca3c, 0x64ff, 0xca3c, 0x21, 0 - .dw 0x6540, 0xca3c, 0x657f, 0xca3c, 0x21, 0 - .dw 0x65c0, 0xca3c, 0x65ff, 0xca3c, 0x21, 0 - .dw 0x6640, 0xca3c, 0x667f, 0xca3c, 0x21, 0 - .dw 0x66c0, 0xca3c, 0x66ff, 0xca3c, 0x21, 0 - .dw 0x6740, 0xca3c, 0x677f, 0xca3c, 0x21, 0 - .dw 0x67c0, 0xca3c, 0x7fff, 0xca3c, 0x21, 0 - .dw 0x8040, 0xca3c, 0x807f, 0xca3c, 0x21, 0 - .dw 0x80c0, 0xca3c, 0x80ff, 0xca3c, 0x21, 0 - .dw 0x8140, 0xca3c, 0x817f, 0xca3c, 0x21, 0 - .dw 0x81c0, 0xca3c, 0x9fff, 0xca3c, 0x21, 0 - .dw 0xa040, 0xca3c, 0xa07f, 0xca3c, 0x21, 0 - .dw 0xa0c0, 0xca3c, 0xa0ff, 0xca3c, 0x21, 0 - .dw 0xa140, 0xca3c, 0xa17f, 0xca3c, 0x21, 0 - .dw 0xa1c0, 0xca3c, 0xa1ff, 0xca3c, 0x21, 0 - .dw 0xa240, 0xca3c, 0xa27f, 0xca3c, 0x21, 0 - .dw 0xa2c0, 0xca3c, 0xa2ff, 0xca3c, 0x21, 0 - .dw 0xa340, 0xca3c, 0xa37f, 0xca3c, 0x21, 0 - .dw 0xa3c0, 0xca3c, 0xa3ff, 0xca3c, 0x21, 0 - .dw 0xa440, 0xca3c, 0xa47f, 0xca3c, 0x21, 0 - .dw 0xa4c0, 0xca3c, 0xa4ff, 0xca3c, 0x21, 0 - .dw 0xa540, 0xca3c, 0xa57f, 0xca3c, 0x21, 0 - .dw 0xa5c0, 0xca3c, 0xa5ff, 0xca3c, 0x21, 0 - .dw 0xa640, 0xca3c, 0xa67f, 0xca3c, 0x21, 0 - .dw 0xa6c0, 0xca3c, 0xa6ff, 0xca3c, 0x21, 0 - .dw 0xa740, 0xca3c, 0xa77f, 0xca3c, 0x21, 0 - .dw 0xa7c0, 0xca3c, 0xbfff, 0xca3c, 0x21, 0 - .dw 0xc040, 0xca3c, 0xc07f, 0xca3c, 0x21, 0 - .dw 0xc0c0, 0xca3c, 0xc0ff, 0xca3c, 0x21, 0 - .dw 0xc140, 0xca3c, 0xc17f, 0xca3c, 0x21, 0 - .dw 0xc1c0, 0xca3c, 0xdfff, 0xca3c, 0x21, 0 - .dw 0xe040, 0xca3c, 0xe07f, 0xca3c, 0x21, 0 - .dw 0xe0c0, 0xca3c, 0xe0ff, 0xca3c, 0x21, 0 - .dw 0xe140, 0xca3c, 0xe17f, 0xca3c, 0x21, 0 - .dw 0xe1c0, 0xca3c, 0xe1ff, 0xca3c, 0x21, 0 - .dw 0xe240, 0xca3c, 0xe27f, 0xca3c, 0x21, 0 - .dw 0xe2c0, 0xca3c, 0xe2ff, 0xca3c, 0x21, 0 - .dw 0xe340, 0xca3c, 0xe37f, 0xca3c, 0x21, 0 - .dw 0xe3c0, 0xca3c, 0xe3ff, 0xca3c, 0x21, 0 - .dw 0xe440, 0xca3c, 0xe47f, 0xca3c, 0x21, 0 - .dw 0xe4c0, 0xca3c, 0xe4ff, 0xca3c, 0x21, 0 - .dw 0xe540, 0xca3c, 0xe57f, 0xca3c, 0x21, 0 - .dw 0xe5c0, 0xca3c, 0xe5ff, 0xca3c, 0x21, 0 - .dw 0xe640, 0xca3c, 0xe67f, 0xca3c, 0x21, 0 - .dw 0xe6c0, 0xca3c, 0xe6ff, 0xca3c, 0x21, 0 - .dw 0xe740, 0xca3c, 0xe77f, 0xca3c, 0x21, 0 - .dw 0xe7c0, 0xca3c, 0x1fff, 0xca40, 0x21, 0 - .dw 0x2800, 0xca40, 0xffff, 0xca43, 0x21, 0 - .dw 0x0200, 0xca44, 0x1fff, 0xca44, 0x21, 0 - .dw 0x2800, 0xca44, 0x3fff, 0xca44, 0x21, 0 - .dw 0x4200, 0xca44, 0x5fff, 0xca44, 0x21, 0 - .dw 0x6800, 0xca44, 0x7fff, 0xca44, 0x21, 0 - .dw 0x8200, 0xca44, 0x9fff, 0xca44, 0x21, 0 - .dw 0xa800, 0xca44, 0xbfff, 0xca44, 0x21, 0 - .dw 0xc200, 0xca44, 0xdfff, 0xca44, 0x21, 0 - .dw 0xe800, 0xca44, 0xffff, 0xca53, 0x21, 0 - .dw 0x0200, 0xca54, 0x1fff, 0xca54, 0x21, 0 - .dw 0x2800, 0xca54, 0x3fff, 0xca54, 0x21, 0 - .dw 0x4200, 0xca54, 0x5fff, 0xca54, 0x21, 0 - .dw 0x6800, 0xca54, 0x7fff, 0xca54, 0x21, 0 - .dw 0x8200, 0xca54, 0x9fff, 0xca54, 0x21, 0 - .dw 0xa800, 0xca54, 0xbfff, 0xca54, 0x21, 0 - .dw 0xc200, 0xca54, 0xdfff, 0xca54, 0x21, 0 - .dw 0xe800, 0xca54, 0x1fff, 0xca80, 0x21, 0 - .dw 0x2800, 0xca80, 0xffff, 0xca83, 0x21, 0 - .dw 0x0200, 0xca84, 0x1fff, 0xca84, 0x21, 0 - .dw 0x2800, 0xca84, 0x3fff, 0xca84, 0x21, 0 - .dw 0x4200, 0xca84, 0x5fff, 0xca84, 0x21, 0 - .dw 0x6800, 0xca84, 0x7fff, 0xca84, 0x21, 0 - .dw 0x8200, 0xca84, 0x9fff, 0xca84, 0x21, 0 - .dw 0xa800, 0xca84, 0xbfff, 0xca84, 0x21, 0 - .dw 0xc200, 0xca84, 0xdfff, 0xca84, 0x21, 0 - .dw 0xe800, 0xca84, 0x1fff, 0xca88, 0x21, 0 - .dw 0x2040, 0xca88, 0x207f, 0xca88, 0x21, 0 - .dw 0x20c0, 0xca88, 0x20ff, 0xca88, 0x21, 0 - .dw 0x2140, 0xca88, 0x217f, 0xca88, 0x21, 0 - .dw 0x21c0, 0xca88, 0x21ff, 0xca88, 0x21, 0 - .dw 0x2240, 0xca88, 0x227f, 0xca88, 0x21, 0 - .dw 0x22c0, 0xca88, 0x22ff, 0xca88, 0x21, 0 - .dw 0x2340, 0xca88, 0x237f, 0xca88, 0x21, 0 - .dw 0x23c0, 0xca88, 0x23ff, 0xca88, 0x21, 0 - .dw 0x2440, 0xca88, 0x247f, 0xca88, 0x21, 0 - .dw 0x24c0, 0xca88, 0x24ff, 0xca88, 0x21, 0 - .dw 0x2540, 0xca88, 0x257f, 0xca88, 0x21, 0 - .dw 0x25c0, 0xca88, 0x25ff, 0xca88, 0x21, 0 - .dw 0x2640, 0xca88, 0x267f, 0xca88, 0x21, 0 - .dw 0x26c0, 0xca88, 0x26ff, 0xca88, 0x21, 0 - .dw 0x2740, 0xca88, 0x277f, 0xca88, 0x21, 0 - .dw 0x27c0, 0xca88, 0xffff, 0xca8b, 0x21, 0 - .dw 0x0040, 0xca8c, 0x007f, 0xca8c, 0x21, 0 - .dw 0x00c0, 0xca8c, 0x00ff, 0xca8c, 0x21, 0 - .dw 0x0140, 0xca8c, 0x017f, 0xca8c, 0x21, 0 - .dw 0x01c0, 0xca8c, 0x1fff, 0xca8c, 0x21, 0 - .dw 0x2040, 0xca8c, 0x207f, 0xca8c, 0x21, 0 - .dw 0x20c0, 0xca8c, 0x20ff, 0xca8c, 0x21, 0 - .dw 0x2140, 0xca8c, 0x217f, 0xca8c, 0x21, 0 - .dw 0x21c0, 0xca8c, 0x21ff, 0xca8c, 0x21, 0 - .dw 0x2240, 0xca8c, 0x227f, 0xca8c, 0x21, 0 - .dw 0x22c0, 0xca8c, 0x22ff, 0xca8c, 0x21, 0 - .dw 0x2340, 0xca8c, 0x237f, 0xca8c, 0x21, 0 - .dw 0x23c0, 0xca8c, 0x23ff, 0xca8c, 0x21, 0 - .dw 0x2440, 0xca8c, 0x247f, 0xca8c, 0x21, 0 - .dw 0x24c0, 0xca8c, 0x24ff, 0xca8c, 0x21, 0 - .dw 0x2540, 0xca8c, 0x257f, 0xca8c, 0x21, 0 - .dw 0x25c0, 0xca8c, 0x25ff, 0xca8c, 0x21, 0 - .dw 0x2640, 0xca8c, 0x267f, 0xca8c, 0x21, 0 - .dw 0x26c0, 0xca8c, 0x26ff, 0xca8c, 0x21, 0 - .dw 0x2740, 0xca8c, 0x277f, 0xca8c, 0x21, 0 - .dw 0x27c0, 0xca8c, 0x3fff, 0xca8c, 0x21, 0 - .dw 0x4040, 0xca8c, 0x407f, 0xca8c, 0x21, 0 - .dw 0x40c0, 0xca8c, 0x40ff, 0xca8c, 0x21, 0 - .dw 0x4140, 0xca8c, 0x417f, 0xca8c, 0x21, 0 - .dw 0x41c0, 0xca8c, 0x5fff, 0xca8c, 0x21, 0 - .dw 0x6040, 0xca8c, 0x607f, 0xca8c, 0x21, 0 - .dw 0x60c0, 0xca8c, 0x60ff, 0xca8c, 0x21, 0 - .dw 0x6140, 0xca8c, 0x617f, 0xca8c, 0x21, 0 - .dw 0x61c0, 0xca8c, 0x61ff, 0xca8c, 0x21, 0 - .dw 0x6240, 0xca8c, 0x627f, 0xca8c, 0x21, 0 - .dw 0x62c0, 0xca8c, 0x62ff, 0xca8c, 0x21, 0 - .dw 0x6340, 0xca8c, 0x637f, 0xca8c, 0x21, 0 - .dw 0x63c0, 0xca8c, 0x63ff, 0xca8c, 0x21, 0 - .dw 0x6440, 0xca8c, 0x647f, 0xca8c, 0x21, 0 - .dw 0x64c0, 0xca8c, 0x64ff, 0xca8c, 0x21, 0 - .dw 0x6540, 0xca8c, 0x657f, 0xca8c, 0x21, 0 - .dw 0x65c0, 0xca8c, 0x65ff, 0xca8c, 0x21, 0 - .dw 0x6640, 0xca8c, 0x667f, 0xca8c, 0x21, 0 - .dw 0x66c0, 0xca8c, 0x66ff, 0xca8c, 0x21, 0 - .dw 0x6740, 0xca8c, 0x677f, 0xca8c, 0x21, 0 - .dw 0x67c0, 0xca8c, 0x7fff, 0xca8c, 0x21, 0 - .dw 0x8040, 0xca8c, 0x807f, 0xca8c, 0x21, 0 - .dw 0x80c0, 0xca8c, 0x80ff, 0xca8c, 0x21, 0 - .dw 0x8140, 0xca8c, 0x817f, 0xca8c, 0x21, 0 - .dw 0x81c0, 0xca8c, 0x9fff, 0xca8c, 0x21, 0 - .dw 0xa040, 0xca8c, 0xa07f, 0xca8c, 0x21, 0 - .dw 0xa0c0, 0xca8c, 0xa0ff, 0xca8c, 0x21, 0 - .dw 0xa140, 0xca8c, 0xa17f, 0xca8c, 0x21, 0 - .dw 0xa1c0, 0xca8c, 0xa1ff, 0xca8c, 0x21, 0 - .dw 0xa240, 0xca8c, 0xa27f, 0xca8c, 0x21, 0 - .dw 0xa2c0, 0xca8c, 0xa2ff, 0xca8c, 0x21, 0 - .dw 0xa340, 0xca8c, 0xa37f, 0xca8c, 0x21, 0 - .dw 0xa3c0, 0xca8c, 0xa3ff, 0xca8c, 0x21, 0 - .dw 0xa440, 0xca8c, 0xa47f, 0xca8c, 0x21, 0 - .dw 0xa4c0, 0xca8c, 0xa4ff, 0xca8c, 0x21, 0 - .dw 0xa540, 0xca8c, 0xa57f, 0xca8c, 0x21, 0 - .dw 0xa5c0, 0xca8c, 0xa5ff, 0xca8c, 0x21, 0 - .dw 0xa640, 0xca8c, 0xa67f, 0xca8c, 0x21, 0 - .dw 0xa6c0, 0xca8c, 0xa6ff, 0xca8c, 0x21, 0 - .dw 0xa740, 0xca8c, 0xa77f, 0xca8c, 0x21, 0 - .dw 0xa7c0, 0xca8c, 0xbfff, 0xca8c, 0x21, 0 - .dw 0xc040, 0xca8c, 0xc07f, 0xca8c, 0x21, 0 - .dw 0xc0c0, 0xca8c, 0xc0ff, 0xca8c, 0x21, 0 - .dw 0xc140, 0xca8c, 0xc17f, 0xca8c, 0x21, 0 - .dw 0xc1c0, 0xca8c, 0xdfff, 0xca8c, 0x21, 0 - .dw 0xe040, 0xca8c, 0xe07f, 0xca8c, 0x21, 0 - .dw 0xe0c0, 0xca8c, 0xe0ff, 0xca8c, 0x21, 0 - .dw 0xe140, 0xca8c, 0xe17f, 0xca8c, 0x21, 0 - .dw 0xe1c0, 0xca8c, 0xe1ff, 0xca8c, 0x21, 0 - .dw 0xe240, 0xca8c, 0xe27f, 0xca8c, 0x21, 0 - .dw 0xe2c0, 0xca8c, 0xe2ff, 0xca8c, 0x21, 0 - .dw 0xe340, 0xca8c, 0xe37f, 0xca8c, 0x21, 0 - .dw 0xe3c0, 0xca8c, 0xe3ff, 0xca8c, 0x21, 0 - .dw 0xe440, 0xca8c, 0xe47f, 0xca8c, 0x21, 0 - .dw 0xe4c0, 0xca8c, 0xe4ff, 0xca8c, 0x21, 0 - .dw 0xe540, 0xca8c, 0xe57f, 0xca8c, 0x21, 0 - .dw 0xe5c0, 0xca8c, 0xe5ff, 0xca8c, 0x21, 0 - .dw 0xe640, 0xca8c, 0xe67f, 0xca8c, 0x21, 0 - .dw 0xe6c0, 0xca8c, 0xe6ff, 0xca8c, 0x21, 0 - .dw 0xe740, 0xca8c, 0xe77f, 0xca8c, 0x21, 0 - .dw 0xe7c0, 0xca8c, 0xffff, 0xca93, 0x21, 0 - .dw 0x0200, 0xca94, 0x1fff, 0xca94, 0x21, 0 - .dw 0x2800, 0xca94, 0x3fff, 0xca94, 0x21, 0 - .dw 0x4200, 0xca94, 0x5fff, 0xca94, 0x21, 0 - .dw 0x6800, 0xca94, 0x7fff, 0xca94, 0x21, 0 - .dw 0x8200, 0xca94, 0x9fff, 0xca94, 0x21, 0 - .dw 0xa800, 0xca94, 0xbfff, 0xca94, 0x21, 0 - .dw 0xc200, 0xca94, 0xdfff, 0xca94, 0x21, 0 - .dw 0xe800, 0xca94, 0xffff, 0xca9b, 0x21, 0 - .dw 0x0040, 0xca9c, 0x007f, 0xca9c, 0x21, 0 - .dw 0x00c0, 0xca9c, 0x00ff, 0xca9c, 0x21, 0 - .dw 0x0140, 0xca9c, 0x017f, 0xca9c, 0x21, 0 - .dw 0x01c0, 0xca9c, 0x1fff, 0xca9c, 0x21, 0 - .dw 0x2040, 0xca9c, 0x207f, 0xca9c, 0x21, 0 - .dw 0x20c0, 0xca9c, 0x20ff, 0xca9c, 0x21, 0 - .dw 0x2140, 0xca9c, 0x217f, 0xca9c, 0x21, 0 - .dw 0x21c0, 0xca9c, 0x21ff, 0xca9c, 0x21, 0 - .dw 0x2240, 0xca9c, 0x227f, 0xca9c, 0x21, 0 - .dw 0x22c0, 0xca9c, 0x22ff, 0xca9c, 0x21, 0 - .dw 0x2340, 0xca9c, 0x237f, 0xca9c, 0x21, 0 - .dw 0x23c0, 0xca9c, 0x23ff, 0xca9c, 0x21, 0 - .dw 0x2440, 0xca9c, 0x247f, 0xca9c, 0x21, 0 - .dw 0x24c0, 0xca9c, 0x24ff, 0xca9c, 0x21, 0 - .dw 0x2540, 0xca9c, 0x257f, 0xca9c, 0x21, 0 - .dw 0x25c0, 0xca9c, 0x25ff, 0xca9c, 0x21, 0 - .dw 0x2640, 0xca9c, 0x267f, 0xca9c, 0x21, 0 - .dw 0x26c0, 0xca9c, 0x26ff, 0xca9c, 0x21, 0 - .dw 0x2740, 0xca9c, 0x277f, 0xca9c, 0x21, 0 - .dw 0x27c0, 0xca9c, 0x3fff, 0xca9c, 0x21, 0 - .dw 0x4040, 0xca9c, 0x407f, 0xca9c, 0x21, 0 - .dw 0x40c0, 0xca9c, 0x40ff, 0xca9c, 0x21, 0 - .dw 0x4140, 0xca9c, 0x417f, 0xca9c, 0x21, 0 - .dw 0x41c0, 0xca9c, 0x5fff, 0xca9c, 0x21, 0 - .dw 0x6040, 0xca9c, 0x607f, 0xca9c, 0x21, 0 - .dw 0x60c0, 0xca9c, 0x60ff, 0xca9c, 0x21, 0 - .dw 0x6140, 0xca9c, 0x617f, 0xca9c, 0x21, 0 - .dw 0x61c0, 0xca9c, 0x61ff, 0xca9c, 0x21, 0 - .dw 0x6240, 0xca9c, 0x627f, 0xca9c, 0x21, 0 - .dw 0x62c0, 0xca9c, 0x62ff, 0xca9c, 0x21, 0 - .dw 0x6340, 0xca9c, 0x637f, 0xca9c, 0x21, 0 - .dw 0x63c0, 0xca9c, 0x63ff, 0xca9c, 0x21, 0 - .dw 0x6440, 0xca9c, 0x647f, 0xca9c, 0x21, 0 - .dw 0x64c0, 0xca9c, 0x64ff, 0xca9c, 0x21, 0 - .dw 0x6540, 0xca9c, 0x657f, 0xca9c, 0x21, 0 - .dw 0x65c0, 0xca9c, 0x65ff, 0xca9c, 0x21, 0 - .dw 0x6640, 0xca9c, 0x667f, 0xca9c, 0x21, 0 - .dw 0x66c0, 0xca9c, 0x66ff, 0xca9c, 0x21, 0 - .dw 0x6740, 0xca9c, 0x677f, 0xca9c, 0x21, 0 - .dw 0x67c0, 0xca9c, 0x7fff, 0xca9c, 0x21, 0 - .dw 0x8040, 0xca9c, 0x807f, 0xca9c, 0x21, 0 - .dw 0x80c0, 0xca9c, 0x80ff, 0xca9c, 0x21, 0 - .dw 0x8140, 0xca9c, 0x817f, 0xca9c, 0x21, 0 - .dw 0x81c0, 0xca9c, 0x9fff, 0xca9c, 0x21, 0 - .dw 0xa040, 0xca9c, 0xa07f, 0xca9c, 0x21, 0 - .dw 0xa0c0, 0xca9c, 0xa0ff, 0xca9c, 0x21, 0 - .dw 0xa140, 0xca9c, 0xa17f, 0xca9c, 0x21, 0 - .dw 0xa1c0, 0xca9c, 0xa1ff, 0xca9c, 0x21, 0 - .dw 0xa240, 0xca9c, 0xa27f, 0xca9c, 0x21, 0 - .dw 0xa2c0, 0xca9c, 0xa2ff, 0xca9c, 0x21, 0 - .dw 0xa340, 0xca9c, 0xa37f, 0xca9c, 0x21, 0 - .dw 0xa3c0, 0xca9c, 0xa3ff, 0xca9c, 0x21, 0 - .dw 0xa440, 0xca9c, 0xa47f, 0xca9c, 0x21, 0 - .dw 0xa4c0, 0xca9c, 0xa4ff, 0xca9c, 0x21, 0 - .dw 0xa540, 0xca9c, 0xa57f, 0xca9c, 0x21, 0 - .dw 0xa5c0, 0xca9c, 0xa5ff, 0xca9c, 0x21, 0 - .dw 0xa640, 0xca9c, 0xa67f, 0xca9c, 0x21, 0 - .dw 0xa6c0, 0xca9c, 0xa6ff, 0xca9c, 0x21, 0 - .dw 0xa740, 0xca9c, 0xa77f, 0xca9c, 0x21, 0 - .dw 0xa7c0, 0xca9c, 0xbfff, 0xca9c, 0x21, 0 - .dw 0xc040, 0xca9c, 0xc07f, 0xca9c, 0x21, 0 - .dw 0xc0c0, 0xca9c, 0xc0ff, 0xca9c, 0x21, 0 - .dw 0xc140, 0xca9c, 0xc17f, 0xca9c, 0x21, 0 - .dw 0xc1c0, 0xca9c, 0xdfff, 0xca9c, 0x21, 0 - .dw 0xe040, 0xca9c, 0xe07f, 0xca9c, 0x21, 0 - .dw 0xe0c0, 0xca9c, 0xe0ff, 0xca9c, 0x21, 0 - .dw 0xe140, 0xca9c, 0xe17f, 0xca9c, 0x21, 0 - .dw 0xe1c0, 0xca9c, 0xe1ff, 0xca9c, 0x21, 0 - .dw 0xe240, 0xca9c, 0xe27f, 0xca9c, 0x21, 0 - .dw 0xe2c0, 0xca9c, 0xe2ff, 0xca9c, 0x21, 0 - .dw 0xe340, 0xca9c, 0xe37f, 0xca9c, 0x21, 0 - .dw 0xe3c0, 0xca9c, 0xe3ff, 0xca9c, 0x21, 0 - .dw 0xe440, 0xca9c, 0xe47f, 0xca9c, 0x21, 0 - .dw 0xe4c0, 0xca9c, 0xe4ff, 0xca9c, 0x21, 0 - .dw 0xe540, 0xca9c, 0xe57f, 0xca9c, 0x21, 0 - .dw 0xe5c0, 0xca9c, 0xe5ff, 0xca9c, 0x21, 0 - .dw 0xe640, 0xca9c, 0xe67f, 0xca9c, 0x21, 0 - .dw 0xe6c0, 0xca9c, 0xe6ff, 0xca9c, 0x21, 0 - .dw 0xe740, 0xca9c, 0xe77f, 0xca9c, 0x21, 0 - .dw 0xe7c0, 0xca9c, 0x1fff, 0xcac0, 0x21, 0 - .dw 0x2800, 0xcac0, 0xffff, 0xcac3, 0x21, 0 - .dw 0x0200, 0xcac4, 0x1fff, 0xcac4, 0x21, 0 - .dw 0x2800, 0xcac4, 0x3fff, 0xcac4, 0x21, 0 - .dw 0x4200, 0xcac4, 0x5fff, 0xcac4, 0x21, 0 - .dw 0x6800, 0xcac4, 0x7fff, 0xcac4, 0x21, 0 - .dw 0x8200, 0xcac4, 0x9fff, 0xcac4, 0x21, 0 - .dw 0xa800, 0xcac4, 0xbfff, 0xcac4, 0x21, 0 - .dw 0xc200, 0xcac4, 0xdfff, 0xcac4, 0x21, 0 - .dw 0xe800, 0xcac4, 0xffff, 0xcad3, 0x21, 0 - .dw 0x0200, 0xcad4, 0x1fff, 0xcad4, 0x21, 0 - .dw 0x2800, 0xcad4, 0x3fff, 0xcad4, 0x21, 0 - .dw 0x4200, 0xcad4, 0x5fff, 0xcad4, 0x21, 0 - .dw 0x6800, 0xcad4, 0x7fff, 0xcad4, 0x21, 0 - .dw 0x8200, 0xcad4, 0x9fff, 0xcad4, 0x21, 0 - .dw 0xa800, 0xcad4, 0xbfff, 0xcad4, 0x21, 0 - .dw 0xc200, 0xcad4, 0xdfff, 0xcad4, 0x21, 0 - .dw 0xe800, 0xcad4, 0x1fff, 0xcb00, 0x21, 0 - .dw 0x2800, 0xcb00, 0xffff, 0xcb03, 0x21, 0 - .dw 0x0200, 0xcb04, 0x1fff, 0xcb04, 0x21, 0 - .dw 0x2800, 0xcb04, 0x3fff, 0xcb04, 0x21, 0 - .dw 0x4200, 0xcb04, 0x5fff, 0xcb04, 0x21, 0 - .dw 0x6800, 0xcb04, 0x7fff, 0xcb04, 0x21, 0 - .dw 0x8200, 0xcb04, 0x9fff, 0xcb04, 0x21, 0 - .dw 0xa800, 0xcb04, 0xbfff, 0xcb04, 0x21, 0 - .dw 0xc200, 0xcb04, 0xdfff, 0xcb04, 0x21, 0 - .dw 0xe800, 0xcb04, 0x1fff, 0xcb08, 0x21, 0 - .dw 0x2040, 0xcb08, 0x207f, 0xcb08, 0x21, 0 - .dw 0x20c0, 0xcb08, 0x20ff, 0xcb08, 0x21, 0 - .dw 0x2140, 0xcb08, 0x217f, 0xcb08, 0x21, 0 - .dw 0x21c0, 0xcb08, 0x21ff, 0xcb08, 0x21, 0 - .dw 0x2240, 0xcb08, 0x227f, 0xcb08, 0x21, 0 - .dw 0x22c0, 0xcb08, 0x22ff, 0xcb08, 0x21, 0 - .dw 0x2340, 0xcb08, 0x237f, 0xcb08, 0x21, 0 - .dw 0x23c0, 0xcb08, 0x23ff, 0xcb08, 0x21, 0 - .dw 0x2440, 0xcb08, 0x247f, 0xcb08, 0x21, 0 - .dw 0x24c0, 0xcb08, 0x24ff, 0xcb08, 0x21, 0 - .dw 0x2540, 0xcb08, 0x257f, 0xcb08, 0x21, 0 - .dw 0x25c0, 0xcb08, 0x25ff, 0xcb08, 0x21, 0 - .dw 0x2640, 0xcb08, 0x267f, 0xcb08, 0x21, 0 - .dw 0x26c0, 0xcb08, 0x26ff, 0xcb08, 0x21, 0 - .dw 0x2740, 0xcb08, 0x277f, 0xcb08, 0x21, 0 - .dw 0x27c0, 0xcb08, 0xffff, 0xcb0b, 0x21, 0 - .dw 0x0040, 0xcb0c, 0x007f, 0xcb0c, 0x21, 0 - .dw 0x00c0, 0xcb0c, 0x00ff, 0xcb0c, 0x21, 0 - .dw 0x0140, 0xcb0c, 0x017f, 0xcb0c, 0x21, 0 - .dw 0x01c0, 0xcb0c, 0x1fff, 0xcb0c, 0x21, 0 - .dw 0x2040, 0xcb0c, 0x207f, 0xcb0c, 0x21, 0 - .dw 0x20c0, 0xcb0c, 0x20ff, 0xcb0c, 0x21, 0 - .dw 0x2140, 0xcb0c, 0x217f, 0xcb0c, 0x21, 0 - .dw 0x21c0, 0xcb0c, 0x21ff, 0xcb0c, 0x21, 0 - .dw 0x2240, 0xcb0c, 0x227f, 0xcb0c, 0x21, 0 - .dw 0x22c0, 0xcb0c, 0x22ff, 0xcb0c, 0x21, 0 - .dw 0x2340, 0xcb0c, 0x237f, 0xcb0c, 0x21, 0 - .dw 0x23c0, 0xcb0c, 0x23ff, 0xcb0c, 0x21, 0 - .dw 0x2440, 0xcb0c, 0x247f, 0xcb0c, 0x21, 0 - .dw 0x24c0, 0xcb0c, 0x24ff, 0xcb0c, 0x21, 0 - .dw 0x2540, 0xcb0c, 0x257f, 0xcb0c, 0x21, 0 - .dw 0x25c0, 0xcb0c, 0x25ff, 0xcb0c, 0x21, 0 - .dw 0x2640, 0xcb0c, 0x267f, 0xcb0c, 0x21, 0 - .dw 0x26c0, 0xcb0c, 0x26ff, 0xcb0c, 0x21, 0 - .dw 0x2740, 0xcb0c, 0x277f, 0xcb0c, 0x21, 0 - .dw 0x27c0, 0xcb0c, 0x3fff, 0xcb0c, 0x21, 0 - .dw 0x4040, 0xcb0c, 0x407f, 0xcb0c, 0x21, 0 - .dw 0x40c0, 0xcb0c, 0x40ff, 0xcb0c, 0x21, 0 - .dw 0x4140, 0xcb0c, 0x417f, 0xcb0c, 0x21, 0 - .dw 0x41c0, 0xcb0c, 0x5fff, 0xcb0c, 0x21, 0 - .dw 0x6040, 0xcb0c, 0x607f, 0xcb0c, 0x21, 0 - .dw 0x60c0, 0xcb0c, 0x60ff, 0xcb0c, 0x21, 0 - .dw 0x6140, 0xcb0c, 0x617f, 0xcb0c, 0x21, 0 - .dw 0x61c0, 0xcb0c, 0x61ff, 0xcb0c, 0x21, 0 - .dw 0x6240, 0xcb0c, 0x627f, 0xcb0c, 0x21, 0 - .dw 0x62c0, 0xcb0c, 0x62ff, 0xcb0c, 0x21, 0 - .dw 0x6340, 0xcb0c, 0x637f, 0xcb0c, 0x21, 0 - .dw 0x63c0, 0xcb0c, 0x63ff, 0xcb0c, 0x21, 0 - .dw 0x6440, 0xcb0c, 0x647f, 0xcb0c, 0x21, 0 - .dw 0x64c0, 0xcb0c, 0x64ff, 0xcb0c, 0x21, 0 - .dw 0x6540, 0xcb0c, 0x657f, 0xcb0c, 0x21, 0 - .dw 0x65c0, 0xcb0c, 0x65ff, 0xcb0c, 0x21, 0 - .dw 0x6640, 0xcb0c, 0x667f, 0xcb0c, 0x21, 0 - .dw 0x66c0, 0xcb0c, 0x66ff, 0xcb0c, 0x21, 0 - .dw 0x6740, 0xcb0c, 0x677f, 0xcb0c, 0x21, 0 - .dw 0x67c0, 0xcb0c, 0x7fff, 0xcb0c, 0x21, 0 - .dw 0x8040, 0xcb0c, 0x807f, 0xcb0c, 0x21, 0 - .dw 0x80c0, 0xcb0c, 0x80ff, 0xcb0c, 0x21, 0 - .dw 0x8140, 0xcb0c, 0x817f, 0xcb0c, 0x21, 0 - .dw 0x81c0, 0xcb0c, 0x9fff, 0xcb0c, 0x21, 0 - .dw 0xa040, 0xcb0c, 0xa07f, 0xcb0c, 0x21, 0 - .dw 0xa0c0, 0xcb0c, 0xa0ff, 0xcb0c, 0x21, 0 - .dw 0xa140, 0xcb0c, 0xa17f, 0xcb0c, 0x21, 0 - .dw 0xa1c0, 0xcb0c, 0xa1ff, 0xcb0c, 0x21, 0 - .dw 0xa240, 0xcb0c, 0xa27f, 0xcb0c, 0x21, 0 - .dw 0xa2c0, 0xcb0c, 0xa2ff, 0xcb0c, 0x21, 0 - .dw 0xa340, 0xcb0c, 0xa37f, 0xcb0c, 0x21, 0 - .dw 0xa3c0, 0xcb0c, 0xa3ff, 0xcb0c, 0x21, 0 - .dw 0xa440, 0xcb0c, 0xa47f, 0xcb0c, 0x21, 0 - .dw 0xa4c0, 0xcb0c, 0xa4ff, 0xcb0c, 0x21, 0 - .dw 0xa540, 0xcb0c, 0xa57f, 0xcb0c, 0x21, 0 - .dw 0xa5c0, 0xcb0c, 0xa5ff, 0xcb0c, 0x21, 0 - .dw 0xa640, 0xcb0c, 0xa67f, 0xcb0c, 0x21, 0 - .dw 0xa6c0, 0xcb0c, 0xa6ff, 0xcb0c, 0x21, 0 - .dw 0xa740, 0xcb0c, 0xa77f, 0xcb0c, 0x21, 0 - .dw 0xa7c0, 0xcb0c, 0xbfff, 0xcb0c, 0x21, 0 - .dw 0xc040, 0xcb0c, 0xc07f, 0xcb0c, 0x21, 0 - .dw 0xc0c0, 0xcb0c, 0xc0ff, 0xcb0c, 0x21, 0 - .dw 0xc140, 0xcb0c, 0xc17f, 0xcb0c, 0x21, 0 - .dw 0xc1c0, 0xcb0c, 0xdfff, 0xcb0c, 0x21, 0 - .dw 0xe040, 0xcb0c, 0xe07f, 0xcb0c, 0x21, 0 - .dw 0xe0c0, 0xcb0c, 0xe0ff, 0xcb0c, 0x21, 0 - .dw 0xe140, 0xcb0c, 0xe17f, 0xcb0c, 0x21, 0 - .dw 0xe1c0, 0xcb0c, 0xe1ff, 0xcb0c, 0x21, 0 - .dw 0xe240, 0xcb0c, 0xe27f, 0xcb0c, 0x21, 0 - .dw 0xe2c0, 0xcb0c, 0xe2ff, 0xcb0c, 0x21, 0 - .dw 0xe340, 0xcb0c, 0xe37f, 0xcb0c, 0x21, 0 - .dw 0xe3c0, 0xcb0c, 0xe3ff, 0xcb0c, 0x21, 0 - .dw 0xe440, 0xcb0c, 0xe47f, 0xcb0c, 0x21, 0 - .dw 0xe4c0, 0xcb0c, 0xe4ff, 0xcb0c, 0x21, 0 - .dw 0xe540, 0xcb0c, 0xe57f, 0xcb0c, 0x21, 0 - .dw 0xe5c0, 0xcb0c, 0xe5ff, 0xcb0c, 0x21, 0 - .dw 0xe640, 0xcb0c, 0xe67f, 0xcb0c, 0x21, 0 - .dw 0xe6c0, 0xcb0c, 0xe6ff, 0xcb0c, 0x21, 0 - .dw 0xe740, 0xcb0c, 0xe77f, 0xcb0c, 0x21, 0 - .dw 0xe7c0, 0xcb0c, 0xffff, 0xcb13, 0x21, 0 - .dw 0x0200, 0xcb14, 0x1fff, 0xcb14, 0x21, 0 - .dw 0x2800, 0xcb14, 0x3fff, 0xcb14, 0x21, 0 - .dw 0x4200, 0xcb14, 0x5fff, 0xcb14, 0x21, 0 - .dw 0x6800, 0xcb14, 0x7fff, 0xcb14, 0x21, 0 - .dw 0x8200, 0xcb14, 0x9fff, 0xcb14, 0x21, 0 - .dw 0xa800, 0xcb14, 0xbfff, 0xcb14, 0x21, 0 - .dw 0xc200, 0xcb14, 0xdfff, 0xcb14, 0x21, 0 - .dw 0xe800, 0xcb14, 0xffff, 0xcb1b, 0x21, 0 - .dw 0x0040, 0xcb1c, 0x007f, 0xcb1c, 0x21, 0 - .dw 0x00c0, 0xcb1c, 0x00ff, 0xcb1c, 0x21, 0 - .dw 0x0140, 0xcb1c, 0x017f, 0xcb1c, 0x21, 0 - .dw 0x01c0, 0xcb1c, 0x1fff, 0xcb1c, 0x21, 0 - .dw 0x2040, 0xcb1c, 0x207f, 0xcb1c, 0x21, 0 - .dw 0x20c0, 0xcb1c, 0x20ff, 0xcb1c, 0x21, 0 - .dw 0x2140, 0xcb1c, 0x217f, 0xcb1c, 0x21, 0 - .dw 0x21c0, 0xcb1c, 0x21ff, 0xcb1c, 0x21, 0 - .dw 0x2240, 0xcb1c, 0x227f, 0xcb1c, 0x21, 0 - .dw 0x22c0, 0xcb1c, 0x22ff, 0xcb1c, 0x21, 0 - .dw 0x2340, 0xcb1c, 0x237f, 0xcb1c, 0x21, 0 - .dw 0x23c0, 0xcb1c, 0x23ff, 0xcb1c, 0x21, 0 - .dw 0x2440, 0xcb1c, 0x247f, 0xcb1c, 0x21, 0 - .dw 0x24c0, 0xcb1c, 0x24ff, 0xcb1c, 0x21, 0 - .dw 0x2540, 0xcb1c, 0x257f, 0xcb1c, 0x21, 0 - .dw 0x25c0, 0xcb1c, 0x25ff, 0xcb1c, 0x21, 0 - .dw 0x2640, 0xcb1c, 0x267f, 0xcb1c, 0x21, 0 - .dw 0x26c0, 0xcb1c, 0x26ff, 0xcb1c, 0x21, 0 - .dw 0x2740, 0xcb1c, 0x277f, 0xcb1c, 0x21, 0 - .dw 0x27c0, 0xcb1c, 0x3fff, 0xcb1c, 0x21, 0 - .dw 0x4040, 0xcb1c, 0x407f, 0xcb1c, 0x21, 0 - .dw 0x40c0, 0xcb1c, 0x40ff, 0xcb1c, 0x21, 0 - .dw 0x4140, 0xcb1c, 0x417f, 0xcb1c, 0x21, 0 - .dw 0x41c0, 0xcb1c, 0x5fff, 0xcb1c, 0x21, 0 - .dw 0x6040, 0xcb1c, 0x607f, 0xcb1c, 0x21, 0 - .dw 0x60c0, 0xcb1c, 0x60ff, 0xcb1c, 0x21, 0 - .dw 0x6140, 0xcb1c, 0x617f, 0xcb1c, 0x21, 0 - .dw 0x61c0, 0xcb1c, 0x61ff, 0xcb1c, 0x21, 0 - .dw 0x6240, 0xcb1c, 0x627f, 0xcb1c, 0x21, 0 - .dw 0x62c0, 0xcb1c, 0x62ff, 0xcb1c, 0x21, 0 - .dw 0x6340, 0xcb1c, 0x637f, 0xcb1c, 0x21, 0 - .dw 0x63c0, 0xcb1c, 0x63ff, 0xcb1c, 0x21, 0 - .dw 0x6440, 0xcb1c, 0x647f, 0xcb1c, 0x21, 0 - .dw 0x64c0, 0xcb1c, 0x64ff, 0xcb1c, 0x21, 0 - .dw 0x6540, 0xcb1c, 0x657f, 0xcb1c, 0x21, 0 - .dw 0x65c0, 0xcb1c, 0x65ff, 0xcb1c, 0x21, 0 - .dw 0x6640, 0xcb1c, 0x667f, 0xcb1c, 0x21, 0 - .dw 0x66c0, 0xcb1c, 0x66ff, 0xcb1c, 0x21, 0 - .dw 0x6740, 0xcb1c, 0x677f, 0xcb1c, 0x21, 0 - .dw 0x67c0, 0xcb1c, 0x7fff, 0xcb1c, 0x21, 0 - .dw 0x8040, 0xcb1c, 0x807f, 0xcb1c, 0x21, 0 - .dw 0x80c0, 0xcb1c, 0x80ff, 0xcb1c, 0x21, 0 - .dw 0x8140, 0xcb1c, 0x817f, 0xcb1c, 0x21, 0 - .dw 0x81c0, 0xcb1c, 0x9fff, 0xcb1c, 0x21, 0 - .dw 0xa040, 0xcb1c, 0xa07f, 0xcb1c, 0x21, 0 - .dw 0xa0c0, 0xcb1c, 0xa0ff, 0xcb1c, 0x21, 0 - .dw 0xa140, 0xcb1c, 0xa17f, 0xcb1c, 0x21, 0 - .dw 0xa1c0, 0xcb1c, 0xa1ff, 0xcb1c, 0x21, 0 - .dw 0xa240, 0xcb1c, 0xa27f, 0xcb1c, 0x21, 0 - .dw 0xa2c0, 0xcb1c, 0xa2ff, 0xcb1c, 0x21, 0 - .dw 0xa340, 0xcb1c, 0xa37f, 0xcb1c, 0x21, 0 - .dw 0xa3c0, 0xcb1c, 0xa3ff, 0xcb1c, 0x21, 0 - .dw 0xa440, 0xcb1c, 0xa47f, 0xcb1c, 0x21, 0 - .dw 0xa4c0, 0xcb1c, 0xa4ff, 0xcb1c, 0x21, 0 - .dw 0xa540, 0xcb1c, 0xa57f, 0xcb1c, 0x21, 0 - .dw 0xa5c0, 0xcb1c, 0xa5ff, 0xcb1c, 0x21, 0 - .dw 0xa640, 0xcb1c, 0xa67f, 0xcb1c, 0x21, 0 - .dw 0xa6c0, 0xcb1c, 0xa6ff, 0xcb1c, 0x21, 0 - .dw 0xa740, 0xcb1c, 0xa77f, 0xcb1c, 0x21, 0 - .dw 0xa7c0, 0xcb1c, 0xbfff, 0xcb1c, 0x21, 0 - .dw 0xc040, 0xcb1c, 0xc07f, 0xcb1c, 0x21, 0 - .dw 0xc0c0, 0xcb1c, 0xc0ff, 0xcb1c, 0x21, 0 - .dw 0xc140, 0xcb1c, 0xc17f, 0xcb1c, 0x21, 0 - .dw 0xc1c0, 0xcb1c, 0xdfff, 0xcb1c, 0x21, 0 - .dw 0xe040, 0xcb1c, 0xe07f, 0xcb1c, 0x21, 0 - .dw 0xe0c0, 0xcb1c, 0xe0ff, 0xcb1c, 0x21, 0 - .dw 0xe140, 0xcb1c, 0xe17f, 0xcb1c, 0x21, 0 - .dw 0xe1c0, 0xcb1c, 0xe1ff, 0xcb1c, 0x21, 0 - .dw 0xe240, 0xcb1c, 0xe27f, 0xcb1c, 0x21, 0 - .dw 0xe2c0, 0xcb1c, 0xe2ff, 0xcb1c, 0x21, 0 - .dw 0xe340, 0xcb1c, 0xe37f, 0xcb1c, 0x21, 0 - .dw 0xe3c0, 0xcb1c, 0xe3ff, 0xcb1c, 0x21, 0 - .dw 0xe440, 0xcb1c, 0xe47f, 0xcb1c, 0x21, 0 - .dw 0xe4c0, 0xcb1c, 0xe4ff, 0xcb1c, 0x21, 0 - .dw 0xe540, 0xcb1c, 0xe57f, 0xcb1c, 0x21, 0 - .dw 0xe5c0, 0xcb1c, 0xe5ff, 0xcb1c, 0x21, 0 - .dw 0xe640, 0xcb1c, 0xe67f, 0xcb1c, 0x21, 0 - .dw 0xe6c0, 0xcb1c, 0xe6ff, 0xcb1c, 0x21, 0 - .dw 0xe740, 0xcb1c, 0xe77f, 0xcb1c, 0x21, 0 - .dw 0xe7c0, 0xcb1c, 0x1fff, 0xcb20, 0x21, 0 - .dw 0x2800, 0xcb20, 0xffff, 0xcb23, 0x21, 0 - .dw 0x0200, 0xcb24, 0x1fff, 0xcb24, 0x21, 0 - .dw 0x2800, 0xcb24, 0x3fff, 0xcb24, 0x21, 0 - .dw 0x4200, 0xcb24, 0x5fff, 0xcb24, 0x21, 0 - .dw 0x6800, 0xcb24, 0x7fff, 0xcb24, 0x21, 0 - .dw 0x8200, 0xcb24, 0x9fff, 0xcb24, 0x21, 0 - .dw 0xa800, 0xcb24, 0xbfff, 0xcb24, 0x21, 0 - .dw 0xc200, 0xcb24, 0xdfff, 0xcb24, 0x21, 0 - .dw 0xe800, 0xcb24, 0x1fff, 0xcb28, 0x21, 0 - .dw 0x2040, 0xcb28, 0x207f, 0xcb28, 0x21, 0 - .dw 0x20c0, 0xcb28, 0x20ff, 0xcb28, 0x21, 0 - .dw 0x2140, 0xcb28, 0x217f, 0xcb28, 0x21, 0 - .dw 0x21c0, 0xcb28, 0x21ff, 0xcb28, 0x21, 0 - .dw 0x2240, 0xcb28, 0x227f, 0xcb28, 0x21, 0 - .dw 0x22c0, 0xcb28, 0x22ff, 0xcb28, 0x21, 0 - .dw 0x2340, 0xcb28, 0x237f, 0xcb28, 0x21, 0 - .dw 0x23c0, 0xcb28, 0x23ff, 0xcb28, 0x21, 0 - .dw 0x2440, 0xcb28, 0x247f, 0xcb28, 0x21, 0 - .dw 0x24c0, 0xcb28, 0x24ff, 0xcb28, 0x21, 0 - .dw 0x2540, 0xcb28, 0x257f, 0xcb28, 0x21, 0 - .dw 0x25c0, 0xcb28, 0x25ff, 0xcb28, 0x21, 0 - .dw 0x2640, 0xcb28, 0x267f, 0xcb28, 0x21, 0 - .dw 0x26c0, 0xcb28, 0x26ff, 0xcb28, 0x21, 0 - .dw 0x2740, 0xcb28, 0x277f, 0xcb28, 0x21, 0 - .dw 0x27c0, 0xcb28, 0xffff, 0xcb2b, 0x21, 0 - .dw 0x0040, 0xcb2c, 0x007f, 0xcb2c, 0x21, 0 - .dw 0x00c0, 0xcb2c, 0x00ff, 0xcb2c, 0x21, 0 - .dw 0x0140, 0xcb2c, 0x017f, 0xcb2c, 0x21, 0 - .dw 0x01c0, 0xcb2c, 0x1fff, 0xcb2c, 0x21, 0 - .dw 0x2040, 0xcb2c, 0x207f, 0xcb2c, 0x21, 0 - .dw 0x20c0, 0xcb2c, 0x20ff, 0xcb2c, 0x21, 0 - .dw 0x2140, 0xcb2c, 0x217f, 0xcb2c, 0x21, 0 - .dw 0x21c0, 0xcb2c, 0x21ff, 0xcb2c, 0x21, 0 - .dw 0x2240, 0xcb2c, 0x227f, 0xcb2c, 0x21, 0 - .dw 0x22c0, 0xcb2c, 0x22ff, 0xcb2c, 0x21, 0 - .dw 0x2340, 0xcb2c, 0x237f, 0xcb2c, 0x21, 0 - .dw 0x23c0, 0xcb2c, 0x23ff, 0xcb2c, 0x21, 0 - .dw 0x2440, 0xcb2c, 0x247f, 0xcb2c, 0x21, 0 - .dw 0x24c0, 0xcb2c, 0x24ff, 0xcb2c, 0x21, 0 - .dw 0x2540, 0xcb2c, 0x257f, 0xcb2c, 0x21, 0 - .dw 0x25c0, 0xcb2c, 0x25ff, 0xcb2c, 0x21, 0 - .dw 0x2640, 0xcb2c, 0x267f, 0xcb2c, 0x21, 0 - .dw 0x26c0, 0xcb2c, 0x26ff, 0xcb2c, 0x21, 0 - .dw 0x2740, 0xcb2c, 0x277f, 0xcb2c, 0x21, 0 - .dw 0x27c0, 0xcb2c, 0x3fff, 0xcb2c, 0x21, 0 - .dw 0x4040, 0xcb2c, 0x407f, 0xcb2c, 0x21, 0 - .dw 0x40c0, 0xcb2c, 0x40ff, 0xcb2c, 0x21, 0 - .dw 0x4140, 0xcb2c, 0x417f, 0xcb2c, 0x21, 0 - .dw 0x41c0, 0xcb2c, 0x5fff, 0xcb2c, 0x21, 0 - .dw 0x6040, 0xcb2c, 0x607f, 0xcb2c, 0x21, 0 - .dw 0x60c0, 0xcb2c, 0x60ff, 0xcb2c, 0x21, 0 - .dw 0x6140, 0xcb2c, 0x617f, 0xcb2c, 0x21, 0 - .dw 0x61c0, 0xcb2c, 0x61ff, 0xcb2c, 0x21, 0 - .dw 0x6240, 0xcb2c, 0x627f, 0xcb2c, 0x21, 0 - .dw 0x62c0, 0xcb2c, 0x62ff, 0xcb2c, 0x21, 0 - .dw 0x6340, 0xcb2c, 0x637f, 0xcb2c, 0x21, 0 - .dw 0x63c0, 0xcb2c, 0x63ff, 0xcb2c, 0x21, 0 - .dw 0x6440, 0xcb2c, 0x647f, 0xcb2c, 0x21, 0 - .dw 0x64c0, 0xcb2c, 0x64ff, 0xcb2c, 0x21, 0 - .dw 0x6540, 0xcb2c, 0x657f, 0xcb2c, 0x21, 0 - .dw 0x65c0, 0xcb2c, 0x65ff, 0xcb2c, 0x21, 0 - .dw 0x6640, 0xcb2c, 0x667f, 0xcb2c, 0x21, 0 - .dw 0x66c0, 0xcb2c, 0x66ff, 0xcb2c, 0x21, 0 - .dw 0x6740, 0xcb2c, 0x677f, 0xcb2c, 0x21, 0 - .dw 0x67c0, 0xcb2c, 0x7fff, 0xcb2c, 0x21, 0 - .dw 0x8040, 0xcb2c, 0x807f, 0xcb2c, 0x21, 0 - .dw 0x80c0, 0xcb2c, 0x80ff, 0xcb2c, 0x21, 0 - .dw 0x8140, 0xcb2c, 0x817f, 0xcb2c, 0x21, 0 - .dw 0x81c0, 0xcb2c, 0x9fff, 0xcb2c, 0x21, 0 - .dw 0xa040, 0xcb2c, 0xa07f, 0xcb2c, 0x21, 0 - .dw 0xa0c0, 0xcb2c, 0xa0ff, 0xcb2c, 0x21, 0 - .dw 0xa140, 0xcb2c, 0xa17f, 0xcb2c, 0x21, 0 - .dw 0xa1c0, 0xcb2c, 0xa1ff, 0xcb2c, 0x21, 0 - .dw 0xa240, 0xcb2c, 0xa27f, 0xcb2c, 0x21, 0 - .dw 0xa2c0, 0xcb2c, 0xa2ff, 0xcb2c, 0x21, 0 - .dw 0xa340, 0xcb2c, 0xa37f, 0xcb2c, 0x21, 0 - .dw 0xa3c0, 0xcb2c, 0xa3ff, 0xcb2c, 0x21, 0 - .dw 0xa440, 0xcb2c, 0xa47f, 0xcb2c, 0x21, 0 - .dw 0xa4c0, 0xcb2c, 0xa4ff, 0xcb2c, 0x21, 0 - .dw 0xa540, 0xcb2c, 0xa57f, 0xcb2c, 0x21, 0 - .dw 0xa5c0, 0xcb2c, 0xa5ff, 0xcb2c, 0x21, 0 - .dw 0xa640, 0xcb2c, 0xa67f, 0xcb2c, 0x21, 0 - .dw 0xa6c0, 0xcb2c, 0xa6ff, 0xcb2c, 0x21, 0 - .dw 0xa740, 0xcb2c, 0xa77f, 0xcb2c, 0x21, 0 - .dw 0xa7c0, 0xcb2c, 0xbfff, 0xcb2c, 0x21, 0 - .dw 0xc040, 0xcb2c, 0xc07f, 0xcb2c, 0x21, 0 - .dw 0xc0c0, 0xcb2c, 0xc0ff, 0xcb2c, 0x21, 0 - .dw 0xc140, 0xcb2c, 0xc17f, 0xcb2c, 0x21, 0 - .dw 0xc1c0, 0xcb2c, 0xdfff, 0xcb2c, 0x21, 0 - .dw 0xe040, 0xcb2c, 0xe07f, 0xcb2c, 0x21, 0 - .dw 0xe0c0, 0xcb2c, 0xe0ff, 0xcb2c, 0x21, 0 - .dw 0xe140, 0xcb2c, 0xe17f, 0xcb2c, 0x21, 0 - .dw 0xe1c0, 0xcb2c, 0xe1ff, 0xcb2c, 0x21, 0 - .dw 0xe240, 0xcb2c, 0xe27f, 0xcb2c, 0x21, 0 - .dw 0xe2c0, 0xcb2c, 0xe2ff, 0xcb2c, 0x21, 0 - .dw 0xe340, 0xcb2c, 0xe37f, 0xcb2c, 0x21, 0 - .dw 0xe3c0, 0xcb2c, 0xe3ff, 0xcb2c, 0x21, 0 - .dw 0xe440, 0xcb2c, 0xe47f, 0xcb2c, 0x21, 0 - .dw 0xe4c0, 0xcb2c, 0xe4ff, 0xcb2c, 0x21, 0 - .dw 0xe540, 0xcb2c, 0xe57f, 0xcb2c, 0x21, 0 - .dw 0xe5c0, 0xcb2c, 0xe5ff, 0xcb2c, 0x21, 0 - .dw 0xe640, 0xcb2c, 0xe67f, 0xcb2c, 0x21, 0 - .dw 0xe6c0, 0xcb2c, 0xe6ff, 0xcb2c, 0x21, 0 - .dw 0xe740, 0xcb2c, 0xe77f, 0xcb2c, 0x21, 0 - .dw 0xe7c0, 0xcb2c, 0xffff, 0xcb33, 0x21, 0 - .dw 0x0200, 0xcb34, 0x1fff, 0xcb34, 0x21, 0 - .dw 0x2800, 0xcb34, 0x3fff, 0xcb34, 0x21, 0 - .dw 0x4200, 0xcb34, 0x5fff, 0xcb34, 0x21, 0 - .dw 0x6800, 0xcb34, 0x7fff, 0xcb34, 0x21, 0 - .dw 0x8200, 0xcb34, 0x9fff, 0xcb34, 0x21, 0 - .dw 0xa800, 0xcb34, 0xbfff, 0xcb34, 0x21, 0 - .dw 0xc200, 0xcb34, 0xdfff, 0xcb34, 0x21, 0 - .dw 0xe800, 0xcb34, 0xffff, 0xcb3b, 0x21, 0 - .dw 0x0040, 0xcb3c, 0x007f, 0xcb3c, 0x21, 0 - .dw 0x00c0, 0xcb3c, 0x00ff, 0xcb3c, 0x21, 0 - .dw 0x0140, 0xcb3c, 0x017f, 0xcb3c, 0x21, 0 - .dw 0x01c0, 0xcb3c, 0x1fff, 0xcb3c, 0x21, 0 - .dw 0x2040, 0xcb3c, 0x207f, 0xcb3c, 0x21, 0 - .dw 0x20c0, 0xcb3c, 0x20ff, 0xcb3c, 0x21, 0 - .dw 0x2140, 0xcb3c, 0x217f, 0xcb3c, 0x21, 0 - .dw 0x21c0, 0xcb3c, 0x21ff, 0xcb3c, 0x21, 0 - .dw 0x2240, 0xcb3c, 0x227f, 0xcb3c, 0x21, 0 - .dw 0x22c0, 0xcb3c, 0x22ff, 0xcb3c, 0x21, 0 - .dw 0x2340, 0xcb3c, 0x237f, 0xcb3c, 0x21, 0 - .dw 0x23c0, 0xcb3c, 0x23ff, 0xcb3c, 0x21, 0 - .dw 0x2440, 0xcb3c, 0x247f, 0xcb3c, 0x21, 0 - .dw 0x24c0, 0xcb3c, 0x24ff, 0xcb3c, 0x21, 0 - .dw 0x2540, 0xcb3c, 0x257f, 0xcb3c, 0x21, 0 - .dw 0x25c0, 0xcb3c, 0x25ff, 0xcb3c, 0x21, 0 - .dw 0x2640, 0xcb3c, 0x267f, 0xcb3c, 0x21, 0 - .dw 0x26c0, 0xcb3c, 0x26ff, 0xcb3c, 0x21, 0 - .dw 0x2740, 0xcb3c, 0x277f, 0xcb3c, 0x21, 0 - .dw 0x27c0, 0xcb3c, 0x3fff, 0xcb3c, 0x21, 0 - .dw 0x4040, 0xcb3c, 0x407f, 0xcb3c, 0x21, 0 - .dw 0x40c0, 0xcb3c, 0x40ff, 0xcb3c, 0x21, 0 - .dw 0x4140, 0xcb3c, 0x417f, 0xcb3c, 0x21, 0 - .dw 0x41c0, 0xcb3c, 0x5fff, 0xcb3c, 0x21, 0 - .dw 0x6040, 0xcb3c, 0x607f, 0xcb3c, 0x21, 0 - .dw 0x60c0, 0xcb3c, 0x60ff, 0xcb3c, 0x21, 0 - .dw 0x6140, 0xcb3c, 0x617f, 0xcb3c, 0x21, 0 - .dw 0x61c0, 0xcb3c, 0x61ff, 0xcb3c, 0x21, 0 - .dw 0x6240, 0xcb3c, 0x627f, 0xcb3c, 0x21, 0 - .dw 0x62c0, 0xcb3c, 0x62ff, 0xcb3c, 0x21, 0 - .dw 0x6340, 0xcb3c, 0x637f, 0xcb3c, 0x21, 0 - .dw 0x63c0, 0xcb3c, 0x63ff, 0xcb3c, 0x21, 0 - .dw 0x6440, 0xcb3c, 0x647f, 0xcb3c, 0x21, 0 - .dw 0x64c0, 0xcb3c, 0x64ff, 0xcb3c, 0x21, 0 - .dw 0x6540, 0xcb3c, 0x657f, 0xcb3c, 0x21, 0 - .dw 0x65c0, 0xcb3c, 0x65ff, 0xcb3c, 0x21, 0 - .dw 0x6640, 0xcb3c, 0x667f, 0xcb3c, 0x21, 0 - .dw 0x66c0, 0xcb3c, 0x66ff, 0xcb3c, 0x21, 0 - .dw 0x6740, 0xcb3c, 0x677f, 0xcb3c, 0x21, 0 - .dw 0x67c0, 0xcb3c, 0x7fff, 0xcb3c, 0x21, 0 - .dw 0x8040, 0xcb3c, 0x807f, 0xcb3c, 0x21, 0 - .dw 0x80c0, 0xcb3c, 0x80ff, 0xcb3c, 0x21, 0 - .dw 0x8140, 0xcb3c, 0x817f, 0xcb3c, 0x21, 0 - .dw 0x81c0, 0xcb3c, 0x9fff, 0xcb3c, 0x21, 0 - .dw 0xa040, 0xcb3c, 0xa07f, 0xcb3c, 0x21, 0 - .dw 0xa0c0, 0xcb3c, 0xa0ff, 0xcb3c, 0x21, 0 - .dw 0xa140, 0xcb3c, 0xa17f, 0xcb3c, 0x21, 0 - .dw 0xa1c0, 0xcb3c, 0xa1ff, 0xcb3c, 0x21, 0 - .dw 0xa240, 0xcb3c, 0xa27f, 0xcb3c, 0x21, 0 - .dw 0xa2c0, 0xcb3c, 0xa2ff, 0xcb3c, 0x21, 0 - .dw 0xa340, 0xcb3c, 0xa37f, 0xcb3c, 0x21, 0 - .dw 0xa3c0, 0xcb3c, 0xa3ff, 0xcb3c, 0x21, 0 - .dw 0xa440, 0xcb3c, 0xa47f, 0xcb3c, 0x21, 0 - .dw 0xa4c0, 0xcb3c, 0xa4ff, 0xcb3c, 0x21, 0 - .dw 0xa540, 0xcb3c, 0xa57f, 0xcb3c, 0x21, 0 - .dw 0xa5c0, 0xcb3c, 0xa5ff, 0xcb3c, 0x21, 0 - .dw 0xa640, 0xcb3c, 0xa67f, 0xcb3c, 0x21, 0 - .dw 0xa6c0, 0xcb3c, 0xa6ff, 0xcb3c, 0x21, 0 - .dw 0xa740, 0xcb3c, 0xa77f, 0xcb3c, 0x21, 0 - .dw 0xa7c0, 0xcb3c, 0xbfff, 0xcb3c, 0x21, 0 - .dw 0xc040, 0xcb3c, 0xc07f, 0xcb3c, 0x21, 0 - .dw 0xc0c0, 0xcb3c, 0xc0ff, 0xcb3c, 0x21, 0 - .dw 0xc140, 0xcb3c, 0xc17f, 0xcb3c, 0x21, 0 - .dw 0xc1c0, 0xcb3c, 0xdfff, 0xcb3c, 0x21, 0 - .dw 0xe040, 0xcb3c, 0xe07f, 0xcb3c, 0x21, 0 - .dw 0xe0c0, 0xcb3c, 0xe0ff, 0xcb3c, 0x21, 0 - .dw 0xe140, 0xcb3c, 0xe17f, 0xcb3c, 0x21, 0 - .dw 0xe1c0, 0xcb3c, 0xe1ff, 0xcb3c, 0x21, 0 - .dw 0xe240, 0xcb3c, 0xe27f, 0xcb3c, 0x21, 0 - .dw 0xe2c0, 0xcb3c, 0xe2ff, 0xcb3c, 0x21, 0 - .dw 0xe340, 0xcb3c, 0xe37f, 0xcb3c, 0x21, 0 - .dw 0xe3c0, 0xcb3c, 0xe3ff, 0xcb3c, 0x21, 0 - .dw 0xe440, 0xcb3c, 0xe47f, 0xcb3c, 0x21, 0 - .dw 0xe4c0, 0xcb3c, 0xe4ff, 0xcb3c, 0x21, 0 - .dw 0xe540, 0xcb3c, 0xe57f, 0xcb3c, 0x21, 0 - .dw 0xe5c0, 0xcb3c, 0xe5ff, 0xcb3c, 0x21, 0 - .dw 0xe640, 0xcb3c, 0xe67f, 0xcb3c, 0x21, 0 - .dw 0xe6c0, 0xcb3c, 0xe6ff, 0xcb3c, 0x21, 0 - .dw 0xe740, 0xcb3c, 0xe77f, 0xcb3c, 0x21, 0 - .dw 0xe7c0, 0xcb3c, 0x1fff, 0xcb60, 0x21, 0 - .dw 0x2800, 0xcb60, 0xffff, 0xcb63, 0x21, 0 - .dw 0x0200, 0xcb64, 0x1fff, 0xcb64, 0x21, 0 - .dw 0x2800, 0xcb64, 0x3fff, 0xcb64, 0x21, 0 - .dw 0x4200, 0xcb64, 0x5fff, 0xcb64, 0x21, 0 - .dw 0x6800, 0xcb64, 0x7fff, 0xcb64, 0x21, 0 - .dw 0x8200, 0xcb64, 0x9fff, 0xcb64, 0x21, 0 - .dw 0xa800, 0xcb64, 0xbfff, 0xcb64, 0x21, 0 - .dw 0xc200, 0xcb64, 0xdfff, 0xcb64, 0x21, 0 - .dw 0xe800, 0xcb64, 0xffff, 0xcb73, 0x21, 0 - .dw 0x0200, 0xcb74, 0x1fff, 0xcb74, 0x21, 0 - .dw 0x2800, 0xcb74, 0x3fff, 0xcb74, 0x21, 0 - .dw 0x4200, 0xcb74, 0x5fff, 0xcb74, 0x21, 0 - .dw 0x6800, 0xcb74, 0x7fff, 0xcb74, 0x21, 0 - .dw 0x8200, 0xcb74, 0x9fff, 0xcb74, 0x21, 0 - .dw 0xa800, 0xcb74, 0xbfff, 0xcb74, 0x21, 0 - .dw 0xc200, 0xcb74, 0xdfff, 0xcb74, 0x21, 0 - .dw 0xe800, 0xcb74, 0x1fff, 0xcb80, 0x21, 0 - .dw 0x2800, 0xcb80, 0xffff, 0xcb83, 0x21, 0 - .dw 0x0200, 0xcb84, 0x1fff, 0xcb84, 0x21, 0 - .dw 0x2800, 0xcb84, 0x3fff, 0xcb84, 0x21, 0 - .dw 0x4200, 0xcb84, 0x5fff, 0xcb84, 0x21, 0 - .dw 0x6800, 0xcb84, 0x7fff, 0xcb84, 0x21, 0 - .dw 0x8200, 0xcb84, 0x9fff, 0xcb84, 0x21, 0 - .dw 0xa800, 0xcb84, 0xbfff, 0xcb84, 0x21, 0 - .dw 0xc200, 0xcb84, 0xdfff, 0xcb84, 0x21, 0 - .dw 0xe800, 0xcb84, 0x1fff, 0xcb88, 0x21, 0 - .dw 0x2040, 0xcb88, 0x207f, 0xcb88, 0x21, 0 - .dw 0x20c0, 0xcb88, 0x20ff, 0xcb88, 0x21, 0 - .dw 0x2140, 0xcb88, 0x217f, 0xcb88, 0x21, 0 - .dw 0x21c0, 0xcb88, 0x21ff, 0xcb88, 0x21, 0 - .dw 0x2240, 0xcb88, 0x227f, 0xcb88, 0x21, 0 - .dw 0x22c0, 0xcb88, 0x22ff, 0xcb88, 0x21, 0 - .dw 0x2340, 0xcb88, 0x237f, 0xcb88, 0x21, 0 - .dw 0x23c0, 0xcb88, 0x23ff, 0xcb88, 0x21, 0 - .dw 0x2440, 0xcb88, 0x247f, 0xcb88, 0x21, 0 - .dw 0x24c0, 0xcb88, 0x24ff, 0xcb88, 0x21, 0 - .dw 0x2540, 0xcb88, 0x257f, 0xcb88, 0x21, 0 - .dw 0x25c0, 0xcb88, 0x25ff, 0xcb88, 0x21, 0 - .dw 0x2640, 0xcb88, 0x267f, 0xcb88, 0x21, 0 - .dw 0x26c0, 0xcb88, 0x26ff, 0xcb88, 0x21, 0 - .dw 0x2740, 0xcb88, 0x277f, 0xcb88, 0x21, 0 - .dw 0x27c0, 0xcb88, 0xffff, 0xcb8b, 0x21, 0 - .dw 0x0040, 0xcb8c, 0x007f, 0xcb8c, 0x21, 0 - .dw 0x00c0, 0xcb8c, 0x00ff, 0xcb8c, 0x21, 0 - .dw 0x0140, 0xcb8c, 0x017f, 0xcb8c, 0x21, 0 - .dw 0x01c0, 0xcb8c, 0x1fff, 0xcb8c, 0x21, 0 - .dw 0x2040, 0xcb8c, 0x207f, 0xcb8c, 0x21, 0 - .dw 0x20c0, 0xcb8c, 0x20ff, 0xcb8c, 0x21, 0 - .dw 0x2140, 0xcb8c, 0x217f, 0xcb8c, 0x21, 0 - .dw 0x21c0, 0xcb8c, 0x21ff, 0xcb8c, 0x21, 0 - .dw 0x2240, 0xcb8c, 0x227f, 0xcb8c, 0x21, 0 - .dw 0x22c0, 0xcb8c, 0x22ff, 0xcb8c, 0x21, 0 - .dw 0x2340, 0xcb8c, 0x237f, 0xcb8c, 0x21, 0 - .dw 0x23c0, 0xcb8c, 0x23ff, 0xcb8c, 0x21, 0 - .dw 0x2440, 0xcb8c, 0x247f, 0xcb8c, 0x21, 0 - .dw 0x24c0, 0xcb8c, 0x24ff, 0xcb8c, 0x21, 0 - .dw 0x2540, 0xcb8c, 0x257f, 0xcb8c, 0x21, 0 - .dw 0x25c0, 0xcb8c, 0x25ff, 0xcb8c, 0x21, 0 - .dw 0x2640, 0xcb8c, 0x267f, 0xcb8c, 0x21, 0 - .dw 0x26c0, 0xcb8c, 0x26ff, 0xcb8c, 0x21, 0 - .dw 0x2740, 0xcb8c, 0x277f, 0xcb8c, 0x21, 0 - .dw 0x27c0, 0xcb8c, 0x3fff, 0xcb8c, 0x21, 0 - .dw 0x4040, 0xcb8c, 0x407f, 0xcb8c, 0x21, 0 - .dw 0x40c0, 0xcb8c, 0x40ff, 0xcb8c, 0x21, 0 - .dw 0x4140, 0xcb8c, 0x417f, 0xcb8c, 0x21, 0 - .dw 0x41c0, 0xcb8c, 0x5fff, 0xcb8c, 0x21, 0 - .dw 0x6040, 0xcb8c, 0x607f, 0xcb8c, 0x21, 0 - .dw 0x60c0, 0xcb8c, 0x60ff, 0xcb8c, 0x21, 0 - .dw 0x6140, 0xcb8c, 0x617f, 0xcb8c, 0x21, 0 - .dw 0x61c0, 0xcb8c, 0x61ff, 0xcb8c, 0x21, 0 - .dw 0x6240, 0xcb8c, 0x627f, 0xcb8c, 0x21, 0 - .dw 0x62c0, 0xcb8c, 0x62ff, 0xcb8c, 0x21, 0 - .dw 0x6340, 0xcb8c, 0x637f, 0xcb8c, 0x21, 0 - .dw 0x63c0, 0xcb8c, 0x63ff, 0xcb8c, 0x21, 0 - .dw 0x6440, 0xcb8c, 0x647f, 0xcb8c, 0x21, 0 - .dw 0x64c0, 0xcb8c, 0x64ff, 0xcb8c, 0x21, 0 - .dw 0x6540, 0xcb8c, 0x657f, 0xcb8c, 0x21, 0 - .dw 0x65c0, 0xcb8c, 0x65ff, 0xcb8c, 0x21, 0 - .dw 0x6640, 0xcb8c, 0x667f, 0xcb8c, 0x21, 0 - .dw 0x66c0, 0xcb8c, 0x66ff, 0xcb8c, 0x21, 0 - .dw 0x6740, 0xcb8c, 0x677f, 0xcb8c, 0x21, 0 - .dw 0x67c0, 0xcb8c, 0x7fff, 0xcb8c, 0x21, 0 - .dw 0x8040, 0xcb8c, 0x807f, 0xcb8c, 0x21, 0 - .dw 0x80c0, 0xcb8c, 0x80ff, 0xcb8c, 0x21, 0 - .dw 0x8140, 0xcb8c, 0x817f, 0xcb8c, 0x21, 0 - .dw 0x81c0, 0xcb8c, 0x9fff, 0xcb8c, 0x21, 0 - .dw 0xa040, 0xcb8c, 0xa07f, 0xcb8c, 0x21, 0 - .dw 0xa0c0, 0xcb8c, 0xa0ff, 0xcb8c, 0x21, 0 - .dw 0xa140, 0xcb8c, 0xa17f, 0xcb8c, 0x21, 0 - .dw 0xa1c0, 0xcb8c, 0xa1ff, 0xcb8c, 0x21, 0 - .dw 0xa240, 0xcb8c, 0xa27f, 0xcb8c, 0x21, 0 - .dw 0xa2c0, 0xcb8c, 0xa2ff, 0xcb8c, 0x21, 0 - .dw 0xa340, 0xcb8c, 0xa37f, 0xcb8c, 0x21, 0 - .dw 0xa3c0, 0xcb8c, 0xa3ff, 0xcb8c, 0x21, 0 - .dw 0xa440, 0xcb8c, 0xa47f, 0xcb8c, 0x21, 0 - .dw 0xa4c0, 0xcb8c, 0xa4ff, 0xcb8c, 0x21, 0 - .dw 0xa540, 0xcb8c, 0xa57f, 0xcb8c, 0x21, 0 - .dw 0xa5c0, 0xcb8c, 0xa5ff, 0xcb8c, 0x21, 0 - .dw 0xa640, 0xcb8c, 0xa67f, 0xcb8c, 0x21, 0 - .dw 0xa6c0, 0xcb8c, 0xa6ff, 0xcb8c, 0x21, 0 - .dw 0xa740, 0xcb8c, 0xa77f, 0xcb8c, 0x21, 0 - .dw 0xa7c0, 0xcb8c, 0xbfff, 0xcb8c, 0x21, 0 - .dw 0xc040, 0xcb8c, 0xc07f, 0xcb8c, 0x21, 0 - .dw 0xc0c0, 0xcb8c, 0xc0ff, 0xcb8c, 0x21, 0 - .dw 0xc140, 0xcb8c, 0xc17f, 0xcb8c, 0x21, 0 - .dw 0xc1c0, 0xcb8c, 0xdfff, 0xcb8c, 0x21, 0 - .dw 0xe040, 0xcb8c, 0xe07f, 0xcb8c, 0x21, 0 - .dw 0xe0c0, 0xcb8c, 0xe0ff, 0xcb8c, 0x21, 0 - .dw 0xe140, 0xcb8c, 0xe17f, 0xcb8c, 0x21, 0 - .dw 0xe1c0, 0xcb8c, 0xe1ff, 0xcb8c, 0x21, 0 - .dw 0xe240, 0xcb8c, 0xe27f, 0xcb8c, 0x21, 0 - .dw 0xe2c0, 0xcb8c, 0xe2ff, 0xcb8c, 0x21, 0 - .dw 0xe340, 0xcb8c, 0xe37f, 0xcb8c, 0x21, 0 - .dw 0xe3c0, 0xcb8c, 0xe3ff, 0xcb8c, 0x21, 0 - .dw 0xe440, 0xcb8c, 0xe47f, 0xcb8c, 0x21, 0 - .dw 0xe4c0, 0xcb8c, 0xe4ff, 0xcb8c, 0x21, 0 - .dw 0xe540, 0xcb8c, 0xe57f, 0xcb8c, 0x21, 0 - .dw 0xe5c0, 0xcb8c, 0xe5ff, 0xcb8c, 0x21, 0 - .dw 0xe640, 0xcb8c, 0xe67f, 0xcb8c, 0x21, 0 - .dw 0xe6c0, 0xcb8c, 0xe6ff, 0xcb8c, 0x21, 0 - .dw 0xe740, 0xcb8c, 0xe77f, 0xcb8c, 0x21, 0 - .dw 0xe7c0, 0xcb8c, 0xffff, 0xcb93, 0x21, 0 - .dw 0x0200, 0xcb94, 0x1fff, 0xcb94, 0x21, 0 - .dw 0x2800, 0xcb94, 0x3fff, 0xcb94, 0x21, 0 - .dw 0x4200, 0xcb94, 0x5fff, 0xcb94, 0x21, 0 - .dw 0x6800, 0xcb94, 0x7fff, 0xcb94, 0x21, 0 - .dw 0x8200, 0xcb94, 0x9fff, 0xcb94, 0x21, 0 - .dw 0xa800, 0xcb94, 0xbfff, 0xcb94, 0x21, 0 - .dw 0xc200, 0xcb94, 0xdfff, 0xcb94, 0x21, 0 - .dw 0xe800, 0xcb94, 0xffff, 0xcb9b, 0x21, 0 - .dw 0x0040, 0xcb9c, 0x007f, 0xcb9c, 0x21, 0 - .dw 0x00c0, 0xcb9c, 0x00ff, 0xcb9c, 0x21, 0 - .dw 0x0140, 0xcb9c, 0x017f, 0xcb9c, 0x21, 0 - .dw 0x01c0, 0xcb9c, 0x1fff, 0xcb9c, 0x21, 0 - .dw 0x2040, 0xcb9c, 0x207f, 0xcb9c, 0x21, 0 - .dw 0x20c0, 0xcb9c, 0x20ff, 0xcb9c, 0x21, 0 - .dw 0x2140, 0xcb9c, 0x217f, 0xcb9c, 0x21, 0 - .dw 0x21c0, 0xcb9c, 0x21ff, 0xcb9c, 0x21, 0 - .dw 0x2240, 0xcb9c, 0x227f, 0xcb9c, 0x21, 0 - .dw 0x22c0, 0xcb9c, 0x22ff, 0xcb9c, 0x21, 0 - .dw 0x2340, 0xcb9c, 0x237f, 0xcb9c, 0x21, 0 - .dw 0x23c0, 0xcb9c, 0x23ff, 0xcb9c, 0x21, 0 - .dw 0x2440, 0xcb9c, 0x247f, 0xcb9c, 0x21, 0 - .dw 0x24c0, 0xcb9c, 0x24ff, 0xcb9c, 0x21, 0 - .dw 0x2540, 0xcb9c, 0x257f, 0xcb9c, 0x21, 0 - .dw 0x25c0, 0xcb9c, 0x25ff, 0xcb9c, 0x21, 0 - .dw 0x2640, 0xcb9c, 0x267f, 0xcb9c, 0x21, 0 - .dw 0x26c0, 0xcb9c, 0x26ff, 0xcb9c, 0x21, 0 - .dw 0x2740, 0xcb9c, 0x277f, 0xcb9c, 0x21, 0 - .dw 0x27c0, 0xcb9c, 0x3fff, 0xcb9c, 0x21, 0 - .dw 0x4040, 0xcb9c, 0x407f, 0xcb9c, 0x21, 0 - .dw 0x40c0, 0xcb9c, 0x40ff, 0xcb9c, 0x21, 0 - .dw 0x4140, 0xcb9c, 0x417f, 0xcb9c, 0x21, 0 - .dw 0x41c0, 0xcb9c, 0x5fff, 0xcb9c, 0x21, 0 - .dw 0x6040, 0xcb9c, 0x607f, 0xcb9c, 0x21, 0 - .dw 0x60c0, 0xcb9c, 0x60ff, 0xcb9c, 0x21, 0 - .dw 0x6140, 0xcb9c, 0x617f, 0xcb9c, 0x21, 0 - .dw 0x61c0, 0xcb9c, 0x61ff, 0xcb9c, 0x21, 0 - .dw 0x6240, 0xcb9c, 0x627f, 0xcb9c, 0x21, 0 - .dw 0x62c0, 0xcb9c, 0x62ff, 0xcb9c, 0x21, 0 - .dw 0x6340, 0xcb9c, 0x637f, 0xcb9c, 0x21, 0 - .dw 0x63c0, 0xcb9c, 0x63ff, 0xcb9c, 0x21, 0 - .dw 0x6440, 0xcb9c, 0x647f, 0xcb9c, 0x21, 0 - .dw 0x64c0, 0xcb9c, 0x64ff, 0xcb9c, 0x21, 0 - .dw 0x6540, 0xcb9c, 0x657f, 0xcb9c, 0x21, 0 - .dw 0x65c0, 0xcb9c, 0x65ff, 0xcb9c, 0x21, 0 - .dw 0x6640, 0xcb9c, 0x667f, 0xcb9c, 0x21, 0 - .dw 0x66c0, 0xcb9c, 0x66ff, 0xcb9c, 0x21, 0 - .dw 0x6740, 0xcb9c, 0x677f, 0xcb9c, 0x21, 0 - .dw 0x67c0, 0xcb9c, 0x7fff, 0xcb9c, 0x21, 0 - .dw 0x8040, 0xcb9c, 0x807f, 0xcb9c, 0x21, 0 - .dw 0x80c0, 0xcb9c, 0x80ff, 0xcb9c, 0x21, 0 - .dw 0x8140, 0xcb9c, 0x817f, 0xcb9c, 0x21, 0 - .dw 0x81c0, 0xcb9c, 0x9fff, 0xcb9c, 0x21, 0 - .dw 0xa040, 0xcb9c, 0xa07f, 0xcb9c, 0x21, 0 - .dw 0xa0c0, 0xcb9c, 0xa0ff, 0xcb9c, 0x21, 0 - .dw 0xa140, 0xcb9c, 0xa17f, 0xcb9c, 0x21, 0 - .dw 0xa1c0, 0xcb9c, 0xa1ff, 0xcb9c, 0x21, 0 - .dw 0xa240, 0xcb9c, 0xa27f, 0xcb9c, 0x21, 0 - .dw 0xa2c0, 0xcb9c, 0xa2ff, 0xcb9c, 0x21, 0 - .dw 0xa340, 0xcb9c, 0xa37f, 0xcb9c, 0x21, 0 - .dw 0xa3c0, 0xcb9c, 0xa3ff, 0xcb9c, 0x21, 0 - .dw 0xa440, 0xcb9c, 0xa47f, 0xcb9c, 0x21, 0 - .dw 0xa4c0, 0xcb9c, 0xa4ff, 0xcb9c, 0x21, 0 - .dw 0xa540, 0xcb9c, 0xa57f, 0xcb9c, 0x21, 0 - .dw 0xa5c0, 0xcb9c, 0xa5ff, 0xcb9c, 0x21, 0 - .dw 0xa640, 0xcb9c, 0xa67f, 0xcb9c, 0x21, 0 - .dw 0xa6c0, 0xcb9c, 0xa6ff, 0xcb9c, 0x21, 0 - .dw 0xa740, 0xcb9c, 0xa77f, 0xcb9c, 0x21, 0 - .dw 0xa7c0, 0xcb9c, 0xbfff, 0xcb9c, 0x21, 0 - .dw 0xc040, 0xcb9c, 0xc07f, 0xcb9c, 0x21, 0 - .dw 0xc0c0, 0xcb9c, 0xc0ff, 0xcb9c, 0x21, 0 - .dw 0xc140, 0xcb9c, 0xc17f, 0xcb9c, 0x21, 0 - .dw 0xc1c0, 0xcb9c, 0xdfff, 0xcb9c, 0x21, 0 - .dw 0xe040, 0xcb9c, 0xe07f, 0xcb9c, 0x21, 0 - .dw 0xe0c0, 0xcb9c, 0xe0ff, 0xcb9c, 0x21, 0 - .dw 0xe140, 0xcb9c, 0xe17f, 0xcb9c, 0x21, 0 - .dw 0xe1c0, 0xcb9c, 0xe1ff, 0xcb9c, 0x21, 0 - .dw 0xe240, 0xcb9c, 0xe27f, 0xcb9c, 0x21, 0 - .dw 0xe2c0, 0xcb9c, 0xe2ff, 0xcb9c, 0x21, 0 - .dw 0xe340, 0xcb9c, 0xe37f, 0xcb9c, 0x21, 0 - .dw 0xe3c0, 0xcb9c, 0xe3ff, 0xcb9c, 0x21, 0 - .dw 0xe440, 0xcb9c, 0xe47f, 0xcb9c, 0x21, 0 - .dw 0xe4c0, 0xcb9c, 0xe4ff, 0xcb9c, 0x21, 0 - .dw 0xe540, 0xcb9c, 0xe57f, 0xcb9c, 0x21, 0 - .dw 0xe5c0, 0xcb9c, 0xe5ff, 0xcb9c, 0x21, 0 - .dw 0xe640, 0xcb9c, 0xe67f, 0xcb9c, 0x21, 0 - .dw 0xe6c0, 0xcb9c, 0xe6ff, 0xcb9c, 0x21, 0 - .dw 0xe740, 0xcb9c, 0xe77f, 0xcb9c, 0x21, 0 - .dw 0xe7c0, 0xcb9c, 0xffff, 0xcbff, 0x21, 0 - .dw 0x0000, 0xcc01, 0x003f, 0xcc01, 0x22, 0 - .dw 0x0240, 0xcc01, 0x027f, 0xcc01, 0x22, 0 - .dw 0x0480, 0xcc01, 0x04bf, 0xcc01, 0x22, 0 - .dw 0x06c0, 0xcc01, 0x06ff, 0xcc01, 0x22, 0 - .dw 0x0900, 0xcc01, 0x093f, 0xcc01, 0x22, 0 - .dw 0x0b40, 0xcc01, 0x0b7f, 0xcc01, 0x22, 0 - .dw 0x0d80, 0xcc01, 0x0dbf, 0xcc01, 0x22, 0 - .dw 0x0fc0, 0xcc01, 0x103f, 0xcc01, 0x22, 0 - .dw 0x1240, 0xcc01, 0x127f, 0xcc01, 0x22, 0 - .dw 0x1480, 0xcc01, 0x14bf, 0xcc01, 0x22, 0 - .dw 0x16c0, 0xcc01, 0x16ff, 0xcc01, 0x22, 0 - .dw 0x1900, 0xcc01, 0x193f, 0xcc01, 0x22, 0 - .dw 0x1b40, 0xcc01, 0x1b7f, 0xcc01, 0x22, 0 - .dw 0x1d80, 0xcc01, 0x1dbf, 0xcc01, 0x22, 0 - .dw 0x1fc0, 0xcc01, 0x203f, 0xcc01, 0x22, 0 - .dw 0x2240, 0xcc01, 0x227f, 0xcc01, 0x22, 0 - .dw 0x2480, 0xcc01, 0x24bf, 0xcc01, 0x22, 0 - .dw 0x26c0, 0xcc01, 0x26ff, 0xcc01, 0x22, 0 - .dw 0x2900, 0xcc01, 0x293f, 0xcc01, 0x22, 0 - .dw 0x2b40, 0xcc01, 0x2b7f, 0xcc01, 0x22, 0 - .dw 0x2d80, 0xcc01, 0x2dbf, 0xcc01, 0x22, 0 - .dw 0x2fc0, 0xcc01, 0x303f, 0xcc01, 0x22, 0 - .dw 0x3240, 0xcc01, 0x327f, 0xcc01, 0x22, 0 - .dw 0x3480, 0xcc01, 0x34bf, 0xcc01, 0x22, 0 - .dw 0x36c0, 0xcc01, 0x36ff, 0xcc01, 0x22, 0 - .dw 0x3900, 0xcc01, 0x393f, 0xcc01, 0x22, 0 - .dw 0x3b40, 0xcc01, 0x3b7f, 0xcc01, 0x22, 0 - .dw 0x3d80, 0xcc01, 0x3dbf, 0xcc01, 0x22, 0 - .dw 0x3fc0, 0xcc01, 0x3fff, 0xcc01, 0x22, 0 - .dw 0x4000, 0xcc01, 0x7fff, 0xcc01, 0x21, 0 - .dw 0x8000, 0xcc01, 0x803f, 0xcc01, 0x22, 0 - .dw 0x8240, 0xcc01, 0x827f, 0xcc01, 0x22, 0 - .dw 0x8480, 0xcc01, 0x84bf, 0xcc01, 0x22, 0 - .dw 0x86c0, 0xcc01, 0x86ff, 0xcc01, 0x22, 0 - .dw 0x8900, 0xcc01, 0x893f, 0xcc01, 0x22, 0 - .dw 0x8b40, 0xcc01, 0x8b7f, 0xcc01, 0x22, 0 - .dw 0x8d80, 0xcc01, 0x8dbf, 0xcc01, 0x22, 0 - .dw 0x8fc0, 0xcc01, 0x903f, 0xcc01, 0x22, 0 - .dw 0x9240, 0xcc01, 0x927f, 0xcc01, 0x22, 0 - .dw 0x9480, 0xcc01, 0x94bf, 0xcc01, 0x22, 0 - .dw 0x96c0, 0xcc01, 0x96ff, 0xcc01, 0x22, 0 - .dw 0x9900, 0xcc01, 0x993f, 0xcc01, 0x22, 0 - .dw 0x9b40, 0xcc01, 0x9b7f, 0xcc01, 0x22, 0 - .dw 0x9d80, 0xcc01, 0x9dbf, 0xcc01, 0x22, 0 - .dw 0x9fc0, 0xcc01, 0xa03f, 0xcc01, 0x22, 0 - .dw 0xa240, 0xcc01, 0xa27f, 0xcc01, 0x22, 0 - .dw 0xa480, 0xcc01, 0xa4bf, 0xcc01, 0x22, 0 - .dw 0xa6c0, 0xcc01, 0xa6ff, 0xcc01, 0x22, 0 - .dw 0xa900, 0xcc01, 0xa93f, 0xcc01, 0x22, 0 - .dw 0xab40, 0xcc01, 0xab7f, 0xcc01, 0x22, 0 - .dw 0xad80, 0xcc01, 0xadbf, 0xcc01, 0x22, 0 - .dw 0xafc0, 0xcc01, 0xb03f, 0xcc01, 0x22, 0 - .dw 0xb240, 0xcc01, 0xb27f, 0xcc01, 0x22, 0 - .dw 0xb480, 0xcc01, 0xb4bf, 0xcc01, 0x22, 0 - .dw 0xb6c0, 0xcc01, 0xb6ff, 0xcc01, 0x22, 0 - .dw 0xb900, 0xcc01, 0xb93f, 0xcc01, 0x22, 0 - .dw 0xbb40, 0xcc01, 0xbb7f, 0xcc01, 0x22, 0 - .dw 0xbd80, 0xcc01, 0xbdbf, 0xcc01, 0x22, 0 - .dw 0xbfc0, 0xcc01, 0xc03f, 0xcc01, 0x22, 0 - .dw 0xc240, 0xcc01, 0xc27f, 0xcc01, 0x22, 0 - .dw 0xc480, 0xcc01, 0xc4bf, 0xcc01, 0x22, 0 - .dw 0xc6c0, 0xcc01, 0xc6ff, 0xcc01, 0x22, 0 - .dw 0xc900, 0xcc01, 0xc93f, 0xcc01, 0x22, 0 - .dw 0xcb40, 0xcc01, 0xcb7f, 0xcc01, 0x22, 0 - .dw 0xcd80, 0xcc01, 0xcdbf, 0xcc01, 0x22, 0 - .dw 0xcfc0, 0xcc01, 0xd03f, 0xcc01, 0x22, 0 - .dw 0xd240, 0xcc01, 0xd27f, 0xcc01, 0x22, 0 - .dw 0xd480, 0xcc01, 0xd4bf, 0xcc01, 0x22, 0 - .dw 0xd6c0, 0xcc01, 0xd6ff, 0xcc01, 0x22, 0 - .dw 0xd900, 0xcc01, 0xd93f, 0xcc01, 0x22, 0 - .dw 0xdb40, 0xcc01, 0xdb7f, 0xcc01, 0x22, 0 - .dw 0xdd80, 0xcc01, 0xddbf, 0xcc01, 0x22, 0 - .dw 0xdfc0, 0xcc01, 0xe03f, 0xcc01, 0x22, 0 - .dw 0xe240, 0xcc01, 0xe27f, 0xcc01, 0x22, 0 - .dw 0xe480, 0xcc01, 0xe4bf, 0xcc01, 0x22, 0 - .dw 0xe6c0, 0xcc01, 0xe6ff, 0xcc01, 0x22, 0 - .dw 0xe900, 0xcc01, 0xe93f, 0xcc01, 0x22, 0 - .dw 0xeb40, 0xcc01, 0xeb7f, 0xcc01, 0x22, 0 - .dw 0xed80, 0xcc01, 0xedbf, 0xcc01, 0x22, 0 - .dw 0xefc0, 0xcc01, 0xf03f, 0xcc01, 0x22, 0 - .dw 0xf240, 0xcc01, 0xf27f, 0xcc01, 0x22, 0 - .dw 0xf480, 0xcc01, 0xf4bf, 0xcc01, 0x22, 0 - .dw 0xf6c0, 0xcc01, 0xf6ff, 0xcc01, 0x22, 0 - .dw 0xf900, 0xcc01, 0xf93f, 0xcc01, 0x22, 0 - .dw 0xfb40, 0xcc01, 0xfb7f, 0xcc01, 0x22, 0 - .dw 0xfd80, 0xcc01, 0xfdbf, 0xcc01, 0x22, 0 - .dw 0xffc0, 0xcc01, 0xffff, 0xcc01, 0x22, 0 - .dw 0x1000, 0xcc02, 0x1fff, 0xcc02, 0x21, 0 - .dw 0x3000, 0xcc02, 0x3fff, 0xcc02, 0x21, 0 - .dw 0x5000, 0xcc02, 0x5fff, 0xcc02, 0x21, 0 - .dw 0x7000, 0xcc02, 0x7fff, 0xcc02, 0x21, 0 - .dw 0x9000, 0xcc02, 0x9fff, 0xcc02, 0x21, 0 - .dw 0xb000, 0xcc02, 0xbfff, 0xcc02, 0x21, 0 - .dw 0xd000, 0xcc02, 0xdfff, 0xcc02, 0x21, 0 - .dw 0xf000, 0xcc02, 0xffff, 0xcc02, 0x21, 0 - .dw 0x1000, 0xcc03, 0x1fff, 0xcc03, 0x21, 0 - .dw 0x3000, 0xcc03, 0x3fff, 0xcc03, 0x21, 0 - .dw 0x5000, 0xcc03, 0x5fff, 0xcc03, 0x21, 0 - .dw 0x7000, 0xcc03, 0x7fff, 0xcc03, 0x21, 0 - .dw 0x9000, 0xcc03, 0x9fff, 0xcc03, 0x21, 0 - .dw 0xb000, 0xcc03, 0xbfff, 0xcc03, 0x21, 0 - .dw 0xd000, 0xcc03, 0xdfff, 0xcc03, 0x21, 0 - .dw 0xf000, 0xcc03, 0xffff, 0xcc03, 0x21, 0 - .dw 0x1000, 0xcc04, 0x1fff, 0xcc04, 0x21, 0 - .dw 0x3000, 0xcc04, 0x3fff, 0xcc04, 0x21, 0 - .dw 0x5000, 0xcc04, 0x5fff, 0xcc04, 0x21, 0 - .dw 0x7000, 0xcc04, 0x7fff, 0xcc04, 0x21, 0 - .dw 0x8000, 0xcc04, 0x803f, 0xcc04, 0x22, 0 - .dw 0x8240, 0xcc04, 0x827f, 0xcc04, 0x22, 0 - .dw 0x8480, 0xcc04, 0x84bf, 0xcc04, 0x22, 0 - .dw 0x86c0, 0xcc04, 0x86ff, 0xcc04, 0x22, 0 - .dw 0x8900, 0xcc04, 0x893f, 0xcc04, 0x22, 0 - .dw 0x8b40, 0xcc04, 0x8b7f, 0xcc04, 0x22, 0 - .dw 0x8d80, 0xcc04, 0x8dbf, 0xcc04, 0x22, 0 - .dw 0x8fc0, 0xcc04, 0x8fff, 0xcc04, 0x22, 0 - .dw 0x9000, 0xcc04, 0x9fff, 0xcc04, 0x21, 0 - .dw 0xa000, 0xcc04, 0xa03f, 0xcc04, 0x22, 0 - .dw 0xa240, 0xcc04, 0xa27f, 0xcc04, 0x22, 0 - .dw 0xa480, 0xcc04, 0xa4bf, 0xcc04, 0x22, 0 - .dw 0xa6c0, 0xcc04, 0xa6ff, 0xcc04, 0x22, 0 - .dw 0xa900, 0xcc04, 0xa93f, 0xcc04, 0x22, 0 - .dw 0xab40, 0xcc04, 0xab7f, 0xcc04, 0x22, 0 - .dw 0xad80, 0xcc04, 0xadbf, 0xcc04, 0x22, 0 - .dw 0xafc0, 0xcc04, 0xafff, 0xcc04, 0x22, 0 - .dw 0xb000, 0xcc04, 0xffff, 0xcc04, 0x21, 0 - .dw 0x1000, 0xcc05, 0x3fff, 0xcc05, 0x21, 0 - .dw 0x5000, 0xcc05, 0x8fff, 0xcc05, 0x21, 0 - .dw 0xa000, 0xcc05, 0xcfff, 0xcc05, 0x21, 0 - .dw 0xe000, 0xcc05, 0xffff, 0xcc05, 0x21, 0 - .dw 0x1000, 0xcc06, 0x3fff, 0xcc06, 0x21, 0 - .dw 0x5000, 0xcc06, 0x7fff, 0xcc06, 0x21, 0 - .dw 0x9000, 0xcc06, 0xffff, 0xcc06, 0x21, 0 - .dw 0x1000, 0xcc07, 0x3fff, 0xcc07, 0x21, 0 - .dw 0x5000, 0xcc07, 0x7fff, 0xcc07, 0x21, 0 - .dw 0x9000, 0xcc07, 0xbfff, 0xcc07, 0x21, 0 - .dw 0xd000, 0xcc07, 0xdfff, 0xcc07, 0x21, 0 - .dw 0xf000, 0xcc07, 0xffff, 0xcc07, 0x21, 0 - .dw 0x1000, 0xcc08, 0x1fff, 0xcc08, 0x21, 0 - .dw 0x3000, 0xcc08, 0x3fff, 0xcc08, 0x21, 0 - .dw 0x5000, 0xcc08, 0x5fff, 0xcc08, 0x21, 0 - .dw 0x7000, 0xcc08, 0x7fff, 0xcc08, 0x21, 0 - .dw 0x9000, 0xcc08, 0x9fff, 0xcc08, 0x21, 0 - .dw 0xb000, 0xcc08, 0xbfff, 0xcc08, 0x21, 0 - .dw 0xd000, 0xcc08, 0xdfff, 0xcc08, 0x21, 0 - .dw 0xf000, 0xcc08, 0xffff, 0xcc08, 0x21, 0 - .dw 0x1000, 0xcc09, 0x1fff, 0xcc09, 0x21, 0 - .dw 0x3000, 0xcc09, 0x3fff, 0xcc09, 0x21, 0 - .dw 0x5000, 0xcc09, 0x7fff, 0xcc09, 0x21, 0 - .dw 0x9000, 0xcc09, 0x9fff, 0xcc09, 0x21, 0 - .dw 0xb000, 0xcc09, 0xbfff, 0xcc09, 0x21, 0 - .dw 0xd000, 0xcc09, 0xffff, 0xcc09, 0x21, 0 - .dw 0x1000, 0xcc0a, 0x3fff, 0xcc0a, 0x21, 0 - .dw 0x5000, 0xcc0a, 0xffff, 0xcc0a, 0x21, 0 - .dw 0x1000, 0xcc0b, 0x3fff, 0xcc0b, 0x21, 0 - .dw 0x5000, 0xcc0b, 0x7fff, 0xcc0b, 0x21, 0 - .dw 0x9000, 0xcc0b, 0x9fff, 0xcc0b, 0x21, 0 - .dw 0xb000, 0xcc0b, 0xbfff, 0xcc0b, 0x21, 0 - .dw 0xd000, 0xcc0b, 0xdfff, 0xcc0b, 0x21, 0 - .dw 0xf000, 0xcc0b, 0xffff, 0xcc0b, 0x21, 0 - .dw 0x1000, 0xcc0c, 0x3fff, 0xcc0c, 0x21, 0 - .dw 0x4000, 0xcc0c, 0x403f, 0xcc0c, 0x22, 0 - .dw 0x4240, 0xcc0c, 0x427f, 0xcc0c, 0x22, 0 - .dw 0x4480, 0xcc0c, 0x44bf, 0xcc0c, 0x22, 0 - .dw 0x46c0, 0xcc0c, 0x46ff, 0xcc0c, 0x22, 0 - .dw 0x4900, 0xcc0c, 0x493f, 0xcc0c, 0x22, 0 - .dw 0x4b40, 0xcc0c, 0x4b7f, 0xcc0c, 0x22, 0 - .dw 0x4d80, 0xcc0c, 0x4dbf, 0xcc0c, 0x22, 0 - .dw 0x4fc0, 0xcc0c, 0x4fff, 0xcc0c, 0x22, 0 - .dw 0x5000, 0xcc0c, 0xbfff, 0xcc0c, 0x21, 0 - .dw 0xd000, 0xcc0c, 0xffff, 0xcc0c, 0x21, 0 - .dw 0x0000, 0xcc0d, 0x0fff, 0xcc0d, 0x22, 0 - .dw 0x1000, 0xcc0d, 0x3fff, 0xcc0d, 0x21, 0 - .dw 0x4000, 0xcc0d, 0x4fff, 0xcc0d, 0x22, 0 - .dw 0x5000, 0xcc0d, 0x7fff, 0xcc0d, 0x21, 0 - .dw 0x8000, 0xcc0d, 0x8fff, 0xcc0d, 0x22, 0 - .dw 0x9000, 0xcc0d, 0xbfff, 0xcc0d, 0x21, 0 - .dw 0xc000, 0xcc0d, 0xcfff, 0xcc0d, 0x22, 0 - .dw 0xd000, 0xcc0d, 0xffff, 0xcc0d, 0x21, 0 - .dw 0x1000, 0xcc0e, 0x3fff, 0xcc0e, 0x21, 0 - .dw 0x5000, 0xcc0e, 0xbfff, 0xcc0e, 0x21, 0 - .dw 0xd000, 0xcc0e, 0xbfff, 0xcc0f, 0x21, 0 - .dw 0xd000, 0xcc0f, 0xffff, 0xcc0f, 0x21, 0 - .dw 0x1000, 0xcc10, 0x3fff, 0xcc10, 0x21, 0 - .dw 0x5000, 0xcc10, 0xbfff, 0xcc10, 0x21, 0 - .dw 0xd000, 0xcc10, 0xffff, 0xcc10, 0x21, 0 - .dw 0x0000, 0xcc11, 0x003f, 0xcc11, 0x22, 0 - .dw 0x0240, 0xcc11, 0x027f, 0xcc11, 0x22, 0 - .dw 0x0480, 0xcc11, 0x04bf, 0xcc11, 0x22, 0 - .dw 0x06c0, 0xcc11, 0x06ff, 0xcc11, 0x22, 0 - .dw 0x0900, 0xcc11, 0x093f, 0xcc11, 0x22, 0 - .dw 0x0b40, 0xcc11, 0x0b7f, 0xcc11, 0x22, 0 - .dw 0x0d80, 0xcc11, 0x0dbf, 0xcc11, 0x22, 0 - .dw 0x0fc0, 0xcc11, 0x0fff, 0xcc11, 0x22, 0 - .dw 0x1000, 0xcc11, 0x1fff, 0xcc11, 0x21, 0 - .dw 0x2000, 0xcc11, 0x203f, 0xcc11, 0x22, 0 - .dw 0x2240, 0xcc11, 0x227f, 0xcc11, 0x22, 0 - .dw 0x2480, 0xcc11, 0x24bf, 0xcc11, 0x22, 0 - .dw 0x26c0, 0xcc11, 0x26ff, 0xcc11, 0x22, 0 - .dw 0x2900, 0xcc11, 0x293f, 0xcc11, 0x22, 0 - .dw 0x2b40, 0xcc11, 0x2b7f, 0xcc11, 0x22, 0 - .dw 0x2d80, 0xcc11, 0x2dbf, 0xcc11, 0x22, 0 - .dw 0x2fc0, 0xcc11, 0x2fff, 0xcc11, 0x22, 0 - .dw 0x3000, 0xcc11, 0x3fff, 0xcc11, 0x21, 0 - .dw 0x4000, 0xcc11, 0x403f, 0xcc11, 0x22, 0 - .dw 0x4240, 0xcc11, 0x427f, 0xcc11, 0x22, 0 - .dw 0x4480, 0xcc11, 0x44bf, 0xcc11, 0x22, 0 - .dw 0x46c0, 0xcc11, 0x46ff, 0xcc11, 0x22, 0 - .dw 0x4900, 0xcc11, 0x493f, 0xcc11, 0x22, 0 - .dw 0x4b40, 0xcc11, 0x4b7f, 0xcc11, 0x22, 0 - .dw 0x4d80, 0xcc11, 0x4dbf, 0xcc11, 0x22, 0 - .dw 0x4fc0, 0xcc11, 0x4fff, 0xcc11, 0x22, 0 - .dw 0x5000, 0xcc11, 0x5fff, 0xcc11, 0x21, 0 - .dw 0x6000, 0xcc11, 0x603f, 0xcc11, 0x22, 0 - .dw 0x6240, 0xcc11, 0x627f, 0xcc11, 0x22, 0 - .dw 0x6480, 0xcc11, 0x64bf, 0xcc11, 0x22, 0 - .dw 0x66c0, 0xcc11, 0x66ff, 0xcc11, 0x22, 0 - .dw 0x6900, 0xcc11, 0x693f, 0xcc11, 0x22, 0 - .dw 0x6b40, 0xcc11, 0x6b7f, 0xcc11, 0x22, 0 - .dw 0x6d80, 0xcc11, 0x6dbf, 0xcc11, 0x22, 0 - .dw 0x6fc0, 0xcc11, 0x6fff, 0xcc11, 0x22, 0 - .dw 0x7000, 0xcc11, 0xffff, 0xcc11, 0x21, 0 - .dw 0x0001, 0xcc12, 0x0001, 0xcc12, 0x21, 0 - .dw 0x0003, 0xcc12, 0x000f, 0xcc12, 0x21, 0 - .dw 0x0011, 0xcc12, 0x0011, 0xcc12, 0x21, 0 - .dw 0x0013, 0xcc12, 0x003f, 0xcc12, 0x21, 0 - .dw 0x0041, 0xcc12, 0x0041, 0xcc12, 0x21, 0 - .dw 0x0043, 0xcc12, 0x004f, 0xcc12, 0x21, 0 - .dw 0x0051, 0xcc12, 0x0051, 0xcc12, 0x21, 0 - .dw 0x0053, 0xcc12, 0x007f, 0xcc12, 0x21, 0 - .dw 0x0081, 0xcc12, 0x0081, 0xcc12, 0x21, 0 - .dw 0x0083, 0xcc12, 0x008f, 0xcc12, 0x21, 0 - .dw 0x0091, 0xcc12, 0x0091, 0xcc12, 0x21, 0 - .dw 0x0093, 0xcc12, 0x00bf, 0xcc12, 0x21, 0 - .dw 0x00c1, 0xcc12, 0x00c1, 0xcc12, 0x21, 0 - .dw 0x00c3, 0xcc12, 0x00cf, 0xcc12, 0x21, 0 - .dw 0x00d1, 0xcc12, 0x00d1, 0xcc12, 0x21, 0 - .dw 0x00d3, 0xcc12, 0x00ff, 0xcc12, 0x21, 0 - .dw 0x0101, 0xcc12, 0x0101, 0xcc12, 0x21, 0 - .dw 0x0103, 0xcc12, 0x010f, 0xcc12, 0x21, 0 - .dw 0x0111, 0xcc12, 0x0111, 0xcc12, 0x21, 0 - .dw 0x0113, 0xcc12, 0x013f, 0xcc12, 0x21, 0 - .dw 0x0141, 0xcc12, 0x0141, 0xcc12, 0x21, 0 - .dw 0x0143, 0xcc12, 0x014f, 0xcc12, 0x21, 0 - .dw 0x0151, 0xcc12, 0x0151, 0xcc12, 0x21, 0 - .dw 0x0153, 0xcc12, 0x017f, 0xcc12, 0x21, 0 - .dw 0x0181, 0xcc12, 0x0181, 0xcc12, 0x21, 0 - .dw 0x0183, 0xcc12, 0x018f, 0xcc12, 0x21, 0 - .dw 0x0191, 0xcc12, 0x0191, 0xcc12, 0x21, 0 - .dw 0x0193, 0xcc12, 0x01bf, 0xcc12, 0x21, 0 - .dw 0x01c1, 0xcc12, 0x01c1, 0xcc12, 0x21, 0 - .dw 0x01c3, 0xcc12, 0x01cf, 0xcc12, 0x21, 0 - .dw 0x01d1, 0xcc12, 0x01d1, 0xcc12, 0x21, 0 - .dw 0x01d3, 0xcc12, 0x01ff, 0xcc12, 0x21, 0 - .dw 0x0201, 0xcc12, 0x0201, 0xcc12, 0x21, 0 - .dw 0x0203, 0xcc12, 0x020f, 0xcc12, 0x21, 0 - .dw 0x0211, 0xcc12, 0x0211, 0xcc12, 0x21, 0 - .dw 0x0213, 0xcc12, 0x023f, 0xcc12, 0x21, 0 - .dw 0x0241, 0xcc12, 0x0241, 0xcc12, 0x21, 0 - .dw 0x0243, 0xcc12, 0x024f, 0xcc12, 0x21, 0 - .dw 0x0251, 0xcc12, 0x0251, 0xcc12, 0x21, 0 - .dw 0x0253, 0xcc12, 0x027f, 0xcc12, 0x21, 0 - .dw 0x0281, 0xcc12, 0x0281, 0xcc12, 0x21, 0 - .dw 0x0283, 0xcc12, 0x028f, 0xcc12, 0x21, 0 - .dw 0x0291, 0xcc12, 0x0291, 0xcc12, 0x21, 0 - .dw 0x0293, 0xcc12, 0x02bf, 0xcc12, 0x21, 0 - .dw 0x02c1, 0xcc12, 0x02c1, 0xcc12, 0x21, 0 - .dw 0x02c3, 0xcc12, 0x02cf, 0xcc12, 0x21, 0 - .dw 0x02d1, 0xcc12, 0x02d1, 0xcc12, 0x21, 0 - .dw 0x02d3, 0xcc12, 0x02ff, 0xcc12, 0x21, 0 - .dw 0x0301, 0xcc12, 0x0301, 0xcc12, 0x21, 0 - .dw 0x0303, 0xcc12, 0x030f, 0xcc12, 0x21, 0 - .dw 0x0311, 0xcc12, 0x0311, 0xcc12, 0x21, 0 - .dw 0x0313, 0xcc12, 0x033f, 0xcc12, 0x21, 0 - .dw 0x0341, 0xcc12, 0x0341, 0xcc12, 0x21, 0 - .dw 0x0343, 0xcc12, 0x034f, 0xcc12, 0x21, 0 - .dw 0x0351, 0xcc12, 0x0351, 0xcc12, 0x21, 0 - .dw 0x0353, 0xcc12, 0x037f, 0xcc12, 0x21, 0 - .dw 0x0381, 0xcc12, 0x0381, 0xcc12, 0x21, 0 - .dw 0x0383, 0xcc12, 0x038f, 0xcc12, 0x21, 0 - .dw 0x0391, 0xcc12, 0x0391, 0xcc12, 0x21, 0 - .dw 0x0393, 0xcc12, 0x03bf, 0xcc12, 0x21, 0 - .dw 0x03c1, 0xcc12, 0x03c1, 0xcc12, 0x21, 0 - .dw 0x03c3, 0xcc12, 0x03cf, 0xcc12, 0x21, 0 - .dw 0x03d1, 0xcc12, 0x03d1, 0xcc12, 0x21, 0 - .dw 0x03d3, 0xcc12, 0x03ff, 0xcc12, 0x21, 0 - .dw 0x0401, 0xcc12, 0x0401, 0xcc12, 0x21, 0 - .dw 0x0403, 0xcc12, 0x040f, 0xcc12, 0x21, 0 - .dw 0x0411, 0xcc12, 0x0411, 0xcc12, 0x21, 0 - .dw 0x0413, 0xcc12, 0x043f, 0xcc12, 0x21, 0 - .dw 0x0441, 0xcc12, 0x0441, 0xcc12, 0x21, 0 - .dw 0x0443, 0xcc12, 0x044f, 0xcc12, 0x21, 0 - .dw 0x0451, 0xcc12, 0x0451, 0xcc12, 0x21, 0 - .dw 0x0453, 0xcc12, 0x047f, 0xcc12, 0x21, 0 - .dw 0x0481, 0xcc12, 0x0481, 0xcc12, 0x21, 0 - .dw 0x0483, 0xcc12, 0x048f, 0xcc12, 0x21, 0 - .dw 0x0491, 0xcc12, 0x0491, 0xcc12, 0x21, 0 - .dw 0x0493, 0xcc12, 0x04bf, 0xcc12, 0x21, 0 - .dw 0x04c1, 0xcc12, 0x04c1, 0xcc12, 0x21, 0 - .dw 0x04c3, 0xcc12, 0x04cf, 0xcc12, 0x21, 0 - .dw 0x04d1, 0xcc12, 0x04d1, 0xcc12, 0x21, 0 - .dw 0x04d3, 0xcc12, 0x04ff, 0xcc12, 0x21, 0 - .dw 0x0501, 0xcc12, 0x0501, 0xcc12, 0x21, 0 - .dw 0x0503, 0xcc12, 0x050f, 0xcc12, 0x21, 0 - .dw 0x0511, 0xcc12, 0x0511, 0xcc12, 0x21, 0 - .dw 0x0513, 0xcc12, 0x053f, 0xcc12, 0x21, 0 - .dw 0x0541, 0xcc12, 0x0541, 0xcc12, 0x21, 0 - .dw 0x0543, 0xcc12, 0x054f, 0xcc12, 0x21, 0 - .dw 0x0551, 0xcc12, 0x0551, 0xcc12, 0x21, 0 - .dw 0x0553, 0xcc12, 0x057f, 0xcc12, 0x21, 0 - .dw 0x0581, 0xcc12, 0x0581, 0xcc12, 0x21, 0 - .dw 0x0583, 0xcc12, 0x058f, 0xcc12, 0x21, 0 - .dw 0x0591, 0xcc12, 0x0591, 0xcc12, 0x21, 0 - .dw 0x0593, 0xcc12, 0x05bf, 0xcc12, 0x21, 0 - .dw 0x05c1, 0xcc12, 0x05c1, 0xcc12, 0x21, 0 - .dw 0x05c3, 0xcc12, 0x05cf, 0xcc12, 0x21, 0 - .dw 0x05d1, 0xcc12, 0x05d1, 0xcc12, 0x21, 0 - .dw 0x05d3, 0xcc12, 0x05ff, 0xcc12, 0x21, 0 - .dw 0x0601, 0xcc12, 0x0601, 0xcc12, 0x21, 0 - .dw 0x0603, 0xcc12, 0x060f, 0xcc12, 0x21, 0 - .dw 0x0611, 0xcc12, 0x0611, 0xcc12, 0x21, 0 - .dw 0x0613, 0xcc12, 0x063f, 0xcc12, 0x21, 0 - .dw 0x0641, 0xcc12, 0x0641, 0xcc12, 0x21, 0 - .dw 0x0643, 0xcc12, 0x064f, 0xcc12, 0x21, 0 - .dw 0x0651, 0xcc12, 0x0651, 0xcc12, 0x21, 0 - .dw 0x0653, 0xcc12, 0x067f, 0xcc12, 0x21, 0 - .dw 0x0681, 0xcc12, 0x0681, 0xcc12, 0x21, 0 - .dw 0x0683, 0xcc12, 0x068f, 0xcc12, 0x21, 0 - .dw 0x0691, 0xcc12, 0x0691, 0xcc12, 0x21, 0 - .dw 0x0693, 0xcc12, 0x06bf, 0xcc12, 0x21, 0 - .dw 0x06c1, 0xcc12, 0x06c1, 0xcc12, 0x21, 0 - .dw 0x06c3, 0xcc12, 0x06cf, 0xcc12, 0x21, 0 - .dw 0x06d1, 0xcc12, 0x06d1, 0xcc12, 0x21, 0 - .dw 0x06d3, 0xcc12, 0x06ff, 0xcc12, 0x21, 0 - .dw 0x0701, 0xcc12, 0x0701, 0xcc12, 0x21, 0 - .dw 0x0703, 0xcc12, 0x070f, 0xcc12, 0x21, 0 - .dw 0x0711, 0xcc12, 0x0711, 0xcc12, 0x21, 0 - .dw 0x0713, 0xcc12, 0x073f, 0xcc12, 0x21, 0 - .dw 0x0741, 0xcc12, 0x0741, 0xcc12, 0x21, 0 - .dw 0x0743, 0xcc12, 0x074f, 0xcc12, 0x21, 0 - .dw 0x0751, 0xcc12, 0x0751, 0xcc12, 0x21, 0 - .dw 0x0753, 0xcc12, 0x077f, 0xcc12, 0x21, 0 - .dw 0x0781, 0xcc12, 0x0781, 0xcc12, 0x21, 0 - .dw 0x0783, 0xcc12, 0x078f, 0xcc12, 0x21, 0 - .dw 0x0791, 0xcc12, 0x0791, 0xcc12, 0x21, 0 - .dw 0x0793, 0xcc12, 0x07bf, 0xcc12, 0x21, 0 - .dw 0x07c1, 0xcc12, 0x07c1, 0xcc12, 0x21, 0 - .dw 0x07c3, 0xcc12, 0x07cf, 0xcc12, 0x21, 0 - .dw 0x07d1, 0xcc12, 0x07d1, 0xcc12, 0x21, 0 - .dw 0x07d3, 0xcc12, 0x07ff, 0xcc12, 0x21, 0 - .dw 0x0801, 0xcc12, 0x0801, 0xcc12, 0x21, 0 - .dw 0x0803, 0xcc12, 0x080f, 0xcc12, 0x21, 0 - .dw 0x0811, 0xcc12, 0x0811, 0xcc12, 0x21, 0 - .dw 0x0813, 0xcc12, 0x083f, 0xcc12, 0x21, 0 - .dw 0x0841, 0xcc12, 0x0841, 0xcc12, 0x21, 0 - .dw 0x0843, 0xcc12, 0x084f, 0xcc12, 0x21, 0 - .dw 0x0851, 0xcc12, 0x0851, 0xcc12, 0x21, 0 - .dw 0x0853, 0xcc12, 0x087f, 0xcc12, 0x21, 0 - .dw 0x0881, 0xcc12, 0x0881, 0xcc12, 0x21, 0 - .dw 0x0883, 0xcc12, 0x088f, 0xcc12, 0x21, 0 - .dw 0x0891, 0xcc12, 0x0891, 0xcc12, 0x21, 0 - .dw 0x0893, 0xcc12, 0x08bf, 0xcc12, 0x21, 0 - .dw 0x08c1, 0xcc12, 0x08c1, 0xcc12, 0x21, 0 - .dw 0x08c3, 0xcc12, 0x08cf, 0xcc12, 0x21, 0 - .dw 0x08d1, 0xcc12, 0x08d1, 0xcc12, 0x21, 0 - .dw 0x08d3, 0xcc12, 0x08ff, 0xcc12, 0x21, 0 - .dw 0x0901, 0xcc12, 0x0901, 0xcc12, 0x21, 0 - .dw 0x0903, 0xcc12, 0x090f, 0xcc12, 0x21, 0 - .dw 0x0911, 0xcc12, 0x0911, 0xcc12, 0x21, 0 - .dw 0x0913, 0xcc12, 0x093f, 0xcc12, 0x21, 0 - .dw 0x0941, 0xcc12, 0x0941, 0xcc12, 0x21, 0 - .dw 0x0943, 0xcc12, 0x094f, 0xcc12, 0x21, 0 - .dw 0x0951, 0xcc12, 0x0951, 0xcc12, 0x21, 0 - .dw 0x0953, 0xcc12, 0x097f, 0xcc12, 0x21, 0 - .dw 0x0981, 0xcc12, 0x0981, 0xcc12, 0x21, 0 - .dw 0x0983, 0xcc12, 0x098f, 0xcc12, 0x21, 0 - .dw 0x0991, 0xcc12, 0x0991, 0xcc12, 0x21, 0 - .dw 0x0993, 0xcc12, 0x09bf, 0xcc12, 0x21, 0 - .dw 0x09c1, 0xcc12, 0x09c1, 0xcc12, 0x21, 0 - .dw 0x09c3, 0xcc12, 0x09cf, 0xcc12, 0x21, 0 - .dw 0x09d1, 0xcc12, 0x09d1, 0xcc12, 0x21, 0 - .dw 0x09d3, 0xcc12, 0x09ff, 0xcc12, 0x21, 0 - .dw 0x0a01, 0xcc12, 0x0a01, 0xcc12, 0x21, 0 - .dw 0x0a03, 0xcc12, 0x0a0f, 0xcc12, 0x21, 0 - .dw 0x0a11, 0xcc12, 0x0a11, 0xcc12, 0x21, 0 - .dw 0x0a13, 0xcc12, 0x0a3f, 0xcc12, 0x21, 0 - .dw 0x0a41, 0xcc12, 0x0a41, 0xcc12, 0x21, 0 - .dw 0x0a43, 0xcc12, 0x0a4f, 0xcc12, 0x21, 0 - .dw 0x0a51, 0xcc12, 0x0a51, 0xcc12, 0x21, 0 - .dw 0x0a53, 0xcc12, 0x0a7f, 0xcc12, 0x21, 0 - .dw 0x0a81, 0xcc12, 0x0a81, 0xcc12, 0x21, 0 - .dw 0x0a83, 0xcc12, 0x0a8f, 0xcc12, 0x21, 0 - .dw 0x0a91, 0xcc12, 0x0a91, 0xcc12, 0x21, 0 - .dw 0x0a93, 0xcc12, 0x0abf, 0xcc12, 0x21, 0 - .dw 0x0ac1, 0xcc12, 0x0ac1, 0xcc12, 0x21, 0 - .dw 0x0ac3, 0xcc12, 0x0acf, 0xcc12, 0x21, 0 - .dw 0x0ad1, 0xcc12, 0x0ad1, 0xcc12, 0x21, 0 - .dw 0x0ad3, 0xcc12, 0x0aff, 0xcc12, 0x21, 0 - .dw 0x0b01, 0xcc12, 0x0b01, 0xcc12, 0x21, 0 - .dw 0x0b03, 0xcc12, 0x0b0f, 0xcc12, 0x21, 0 - .dw 0x0b11, 0xcc12, 0x0b11, 0xcc12, 0x21, 0 - .dw 0x0b13, 0xcc12, 0x0b3f, 0xcc12, 0x21, 0 - .dw 0x0b41, 0xcc12, 0x0b41, 0xcc12, 0x21, 0 - .dw 0x0b43, 0xcc12, 0x0b4f, 0xcc12, 0x21, 0 - .dw 0x0b51, 0xcc12, 0x0b51, 0xcc12, 0x21, 0 - .dw 0x0b53, 0xcc12, 0x0b7f, 0xcc12, 0x21, 0 - .dw 0x0b81, 0xcc12, 0x0b81, 0xcc12, 0x21, 0 - .dw 0x0b83, 0xcc12, 0x0b8f, 0xcc12, 0x21, 0 - .dw 0x0b91, 0xcc12, 0x0b91, 0xcc12, 0x21, 0 - .dw 0x0b93, 0xcc12, 0x0bbf, 0xcc12, 0x21, 0 - .dw 0x0bc1, 0xcc12, 0x0bc1, 0xcc12, 0x21, 0 - .dw 0x0bc3, 0xcc12, 0x0bcf, 0xcc12, 0x21, 0 - .dw 0x0bd1, 0xcc12, 0x0bd1, 0xcc12, 0x21, 0 - .dw 0x0bd3, 0xcc12, 0x0bff, 0xcc12, 0x21, 0 - .dw 0x0c01, 0xcc12, 0x0c01, 0xcc12, 0x21, 0 - .dw 0x0c03, 0xcc12, 0x0c0f, 0xcc12, 0x21, 0 - .dw 0x0c11, 0xcc12, 0x0c11, 0xcc12, 0x21, 0 - .dw 0x0c13, 0xcc12, 0x0c3f, 0xcc12, 0x21, 0 - .dw 0x0c41, 0xcc12, 0x0c41, 0xcc12, 0x21, 0 - .dw 0x0c43, 0xcc12, 0x0c4f, 0xcc12, 0x21, 0 - .dw 0x0c51, 0xcc12, 0x0c51, 0xcc12, 0x21, 0 - .dw 0x0c53, 0xcc12, 0x0c7f, 0xcc12, 0x21, 0 - .dw 0x0c81, 0xcc12, 0x0c81, 0xcc12, 0x21, 0 - .dw 0x0c83, 0xcc12, 0x0c8f, 0xcc12, 0x21, 0 - .dw 0x0c91, 0xcc12, 0x0c91, 0xcc12, 0x21, 0 - .dw 0x0c93, 0xcc12, 0x0cbf, 0xcc12, 0x21, 0 - .dw 0x0cc1, 0xcc12, 0x0cc1, 0xcc12, 0x21, 0 - .dw 0x0cc3, 0xcc12, 0x0ccf, 0xcc12, 0x21, 0 - .dw 0x0cd1, 0xcc12, 0x0cd1, 0xcc12, 0x21, 0 - .dw 0x0cd3, 0xcc12, 0x0cff, 0xcc12, 0x21, 0 - .dw 0x0d01, 0xcc12, 0x0d01, 0xcc12, 0x21, 0 - .dw 0x0d03, 0xcc12, 0x0d0f, 0xcc12, 0x21, 0 - .dw 0x0d11, 0xcc12, 0x0d11, 0xcc12, 0x21, 0 - .dw 0x0d13, 0xcc12, 0x0d3f, 0xcc12, 0x21, 0 - .dw 0x0d41, 0xcc12, 0x0d41, 0xcc12, 0x21, 0 - .dw 0x0d43, 0xcc12, 0x0d4f, 0xcc12, 0x21, 0 - .dw 0x0d51, 0xcc12, 0x0d51, 0xcc12, 0x21, 0 - .dw 0x0d53, 0xcc12, 0x0d7f, 0xcc12, 0x21, 0 - .dw 0x0d81, 0xcc12, 0x0d81, 0xcc12, 0x21, 0 - .dw 0x0d83, 0xcc12, 0x0d8f, 0xcc12, 0x21, 0 - .dw 0x0d91, 0xcc12, 0x0d91, 0xcc12, 0x21, 0 - .dw 0x0d93, 0xcc12, 0x0dbf, 0xcc12, 0x21, 0 - .dw 0x0dc1, 0xcc12, 0x0dc1, 0xcc12, 0x21, 0 - .dw 0x0dc3, 0xcc12, 0x0dcf, 0xcc12, 0x21, 0 - .dw 0x0dd1, 0xcc12, 0x0dd1, 0xcc12, 0x21, 0 - .dw 0x0dd3, 0xcc12, 0x0dff, 0xcc12, 0x21, 0 - .dw 0x0e01, 0xcc12, 0x0e01, 0xcc12, 0x21, 0 - .dw 0x0e03, 0xcc12, 0x0e0f, 0xcc12, 0x21, 0 - .dw 0x0e11, 0xcc12, 0x0e11, 0xcc12, 0x21, 0 - .dw 0x0e13, 0xcc12, 0x0e3f, 0xcc12, 0x21, 0 - .dw 0x0e41, 0xcc12, 0x0e41, 0xcc12, 0x21, 0 - .dw 0x0e43, 0xcc12, 0x0e4f, 0xcc12, 0x21, 0 - .dw 0x0e51, 0xcc12, 0x0e51, 0xcc12, 0x21, 0 - .dw 0x0e53, 0xcc12, 0x0e7f, 0xcc12, 0x21, 0 - .dw 0x0e81, 0xcc12, 0x0e81, 0xcc12, 0x21, 0 - .dw 0x0e83, 0xcc12, 0x0e8f, 0xcc12, 0x21, 0 - .dw 0x0e91, 0xcc12, 0x0e91, 0xcc12, 0x21, 0 - .dw 0x0e93, 0xcc12, 0x0ebf, 0xcc12, 0x21, 0 - .dw 0x0ec1, 0xcc12, 0x0ec1, 0xcc12, 0x21, 0 - .dw 0x0ec3, 0xcc12, 0x0ecf, 0xcc12, 0x21, 0 - .dw 0x0ed1, 0xcc12, 0x0ed1, 0xcc12, 0x21, 0 - .dw 0x0ed3, 0xcc12, 0x0eff, 0xcc12, 0x21, 0 - .dw 0x0f01, 0xcc12, 0x0f01, 0xcc12, 0x21, 0 - .dw 0x0f03, 0xcc12, 0x0f0f, 0xcc12, 0x21, 0 - .dw 0x0f11, 0xcc12, 0x0f11, 0xcc12, 0x21, 0 - .dw 0x0f13, 0xcc12, 0x0f3f, 0xcc12, 0x21, 0 - .dw 0x0f41, 0xcc12, 0x0f41, 0xcc12, 0x21, 0 - .dw 0x0f43, 0xcc12, 0x0f4f, 0xcc12, 0x21, 0 - .dw 0x0f51, 0xcc12, 0x0f51, 0xcc12, 0x21, 0 - .dw 0x0f53, 0xcc12, 0x0f7f, 0xcc12, 0x21, 0 - .dw 0x0f81, 0xcc12, 0x0f81, 0xcc12, 0x21, 0 - .dw 0x0f83, 0xcc12, 0x0f8f, 0xcc12, 0x21, 0 - .dw 0x0f91, 0xcc12, 0x0f91, 0xcc12, 0x21, 0 - .dw 0x0f93, 0xcc12, 0x0fbf, 0xcc12, 0x21, 0 - .dw 0x0fc1, 0xcc12, 0x0fc1, 0xcc12, 0x21, 0 - .dw 0x0fc3, 0xcc12, 0x0fcf, 0xcc12, 0x21, 0 - .dw 0x0fd1, 0xcc12, 0x0fd1, 0xcc12, 0x21, 0 - .dw 0x0fd3, 0xcc12, 0x1fff, 0xcc12, 0x21, 0 - .dw 0x2001, 0xcc12, 0x2001, 0xcc12, 0x21, 0 - .dw 0x2003, 0xcc12, 0x200f, 0xcc12, 0x21, 0 - .dw 0x2011, 0xcc12, 0x2011, 0xcc12, 0x21, 0 - .dw 0x2013, 0xcc12, 0x203f, 0xcc12, 0x21, 0 - .dw 0x2041, 0xcc12, 0x2041, 0xcc12, 0x21, 0 - .dw 0x2043, 0xcc12, 0x204f, 0xcc12, 0x21, 0 - .dw 0x2051, 0xcc12, 0x2051, 0xcc12, 0x21, 0 - .dw 0x2053, 0xcc12, 0x207f, 0xcc12, 0x21, 0 - .dw 0x2081, 0xcc12, 0x2081, 0xcc12, 0x21, 0 - .dw 0x2083, 0xcc12, 0x208f, 0xcc12, 0x21, 0 - .dw 0x2091, 0xcc12, 0x2091, 0xcc12, 0x21, 0 - .dw 0x2093, 0xcc12, 0x20bf, 0xcc12, 0x21, 0 - .dw 0x20c1, 0xcc12, 0x20c1, 0xcc12, 0x21, 0 - .dw 0x20c3, 0xcc12, 0x20cf, 0xcc12, 0x21, 0 - .dw 0x20d1, 0xcc12, 0x20d1, 0xcc12, 0x21, 0 - .dw 0x20d3, 0xcc12, 0x20ff, 0xcc12, 0x21, 0 - .dw 0x2101, 0xcc12, 0x2101, 0xcc12, 0x21, 0 - .dw 0x2103, 0xcc12, 0x210f, 0xcc12, 0x21, 0 - .dw 0x2111, 0xcc12, 0x2111, 0xcc12, 0x21, 0 - .dw 0x2113, 0xcc12, 0x213f, 0xcc12, 0x21, 0 - .dw 0x2141, 0xcc12, 0x2141, 0xcc12, 0x21, 0 - .dw 0x2143, 0xcc12, 0x214f, 0xcc12, 0x21, 0 - .dw 0x2151, 0xcc12, 0x2151, 0xcc12, 0x21, 0 - .dw 0x2153, 0xcc12, 0x217f, 0xcc12, 0x21, 0 - .dw 0x2181, 0xcc12, 0x2181, 0xcc12, 0x21, 0 - .dw 0x2183, 0xcc12, 0x218f, 0xcc12, 0x21, 0 - .dw 0x2191, 0xcc12, 0x2191, 0xcc12, 0x21, 0 - .dw 0x2193, 0xcc12, 0x21bf, 0xcc12, 0x21, 0 - .dw 0x21c1, 0xcc12, 0x21c1, 0xcc12, 0x21, 0 - .dw 0x21c3, 0xcc12, 0x21cf, 0xcc12, 0x21, 0 - .dw 0x21d1, 0xcc12, 0x21d1, 0xcc12, 0x21, 0 - .dw 0x21d3, 0xcc12, 0x21ff, 0xcc12, 0x21, 0 - .dw 0x2201, 0xcc12, 0x2201, 0xcc12, 0x21, 0 - .dw 0x2203, 0xcc12, 0x220f, 0xcc12, 0x21, 0 - .dw 0x2211, 0xcc12, 0x2211, 0xcc12, 0x21, 0 - .dw 0x2213, 0xcc12, 0x223f, 0xcc12, 0x21, 0 - .dw 0x2241, 0xcc12, 0x2241, 0xcc12, 0x21, 0 - .dw 0x2243, 0xcc12, 0x224f, 0xcc12, 0x21, 0 - .dw 0x2251, 0xcc12, 0x2251, 0xcc12, 0x21, 0 - .dw 0x2253, 0xcc12, 0x227f, 0xcc12, 0x21, 0 - .dw 0x2281, 0xcc12, 0x2281, 0xcc12, 0x21, 0 - .dw 0x2283, 0xcc12, 0x228f, 0xcc12, 0x21, 0 - .dw 0x2291, 0xcc12, 0x2291, 0xcc12, 0x21, 0 - .dw 0x2293, 0xcc12, 0x22bf, 0xcc12, 0x21, 0 - .dw 0x22c1, 0xcc12, 0x22c1, 0xcc12, 0x21, 0 - .dw 0x22c3, 0xcc12, 0x22cf, 0xcc12, 0x21, 0 - .dw 0x22d1, 0xcc12, 0x22d1, 0xcc12, 0x21, 0 - .dw 0x22d3, 0xcc12, 0x22ff, 0xcc12, 0x21, 0 - .dw 0x2301, 0xcc12, 0x2301, 0xcc12, 0x21, 0 - .dw 0x2303, 0xcc12, 0x230f, 0xcc12, 0x21, 0 - .dw 0x2311, 0xcc12, 0x2311, 0xcc12, 0x21, 0 - .dw 0x2313, 0xcc12, 0x233f, 0xcc12, 0x21, 0 - .dw 0x2341, 0xcc12, 0x2341, 0xcc12, 0x21, 0 - .dw 0x2343, 0xcc12, 0x234f, 0xcc12, 0x21, 0 - .dw 0x2351, 0xcc12, 0x2351, 0xcc12, 0x21, 0 - .dw 0x2353, 0xcc12, 0x237f, 0xcc12, 0x21, 0 - .dw 0x2381, 0xcc12, 0x2381, 0xcc12, 0x21, 0 - .dw 0x2383, 0xcc12, 0x238f, 0xcc12, 0x21, 0 - .dw 0x2391, 0xcc12, 0x2391, 0xcc12, 0x21, 0 - .dw 0x2393, 0xcc12, 0x23bf, 0xcc12, 0x21, 0 - .dw 0x23c1, 0xcc12, 0x23c1, 0xcc12, 0x21, 0 - .dw 0x23c3, 0xcc12, 0x23cf, 0xcc12, 0x21, 0 - .dw 0x23d1, 0xcc12, 0x23d1, 0xcc12, 0x21, 0 - .dw 0x23d3, 0xcc12, 0x23ff, 0xcc12, 0x21, 0 - .dw 0x2401, 0xcc12, 0x2401, 0xcc12, 0x21, 0 - .dw 0x2403, 0xcc12, 0x240f, 0xcc12, 0x21, 0 - .dw 0x2411, 0xcc12, 0x2411, 0xcc12, 0x21, 0 - .dw 0x2413, 0xcc12, 0x243f, 0xcc12, 0x21, 0 - .dw 0x2441, 0xcc12, 0x2441, 0xcc12, 0x21, 0 - .dw 0x2443, 0xcc12, 0x244f, 0xcc12, 0x21, 0 - .dw 0x2451, 0xcc12, 0x2451, 0xcc12, 0x21, 0 - .dw 0x2453, 0xcc12, 0x247f, 0xcc12, 0x21, 0 - .dw 0x2481, 0xcc12, 0x2481, 0xcc12, 0x21, 0 - .dw 0x2483, 0xcc12, 0x248f, 0xcc12, 0x21, 0 - .dw 0x2491, 0xcc12, 0x2491, 0xcc12, 0x21, 0 - .dw 0x2493, 0xcc12, 0x24bf, 0xcc12, 0x21, 0 - .dw 0x24c1, 0xcc12, 0x24c1, 0xcc12, 0x21, 0 - .dw 0x24c3, 0xcc12, 0x24cf, 0xcc12, 0x21, 0 - .dw 0x24d1, 0xcc12, 0x24d1, 0xcc12, 0x21, 0 - .dw 0x24d3, 0xcc12, 0x24ff, 0xcc12, 0x21, 0 - .dw 0x2501, 0xcc12, 0x2501, 0xcc12, 0x21, 0 - .dw 0x2503, 0xcc12, 0x250f, 0xcc12, 0x21, 0 - .dw 0x2511, 0xcc12, 0x2511, 0xcc12, 0x21, 0 - .dw 0x2513, 0xcc12, 0x253f, 0xcc12, 0x21, 0 - .dw 0x2541, 0xcc12, 0x2541, 0xcc12, 0x21, 0 - .dw 0x2543, 0xcc12, 0x254f, 0xcc12, 0x21, 0 - .dw 0x2551, 0xcc12, 0x2551, 0xcc12, 0x21, 0 - .dw 0x2553, 0xcc12, 0x257f, 0xcc12, 0x21, 0 - .dw 0x2581, 0xcc12, 0x2581, 0xcc12, 0x21, 0 - .dw 0x2583, 0xcc12, 0x258f, 0xcc12, 0x21, 0 - .dw 0x2591, 0xcc12, 0x2591, 0xcc12, 0x21, 0 - .dw 0x2593, 0xcc12, 0x25bf, 0xcc12, 0x21, 0 - .dw 0x25c1, 0xcc12, 0x25c1, 0xcc12, 0x21, 0 - .dw 0x25c3, 0xcc12, 0x25cf, 0xcc12, 0x21, 0 - .dw 0x25d1, 0xcc12, 0x25d1, 0xcc12, 0x21, 0 - .dw 0x25d3, 0xcc12, 0x25ff, 0xcc12, 0x21, 0 - .dw 0x2601, 0xcc12, 0x2601, 0xcc12, 0x21, 0 - .dw 0x2603, 0xcc12, 0x260f, 0xcc12, 0x21, 0 - .dw 0x2611, 0xcc12, 0x2611, 0xcc12, 0x21, 0 - .dw 0x2613, 0xcc12, 0x263f, 0xcc12, 0x21, 0 - .dw 0x2641, 0xcc12, 0x2641, 0xcc12, 0x21, 0 - .dw 0x2643, 0xcc12, 0x264f, 0xcc12, 0x21, 0 - .dw 0x2651, 0xcc12, 0x2651, 0xcc12, 0x21, 0 - .dw 0x2653, 0xcc12, 0x267f, 0xcc12, 0x21, 0 - .dw 0x2681, 0xcc12, 0x2681, 0xcc12, 0x21, 0 - .dw 0x2683, 0xcc12, 0x268f, 0xcc12, 0x21, 0 - .dw 0x2691, 0xcc12, 0x2691, 0xcc12, 0x21, 0 - .dw 0x2693, 0xcc12, 0x26bf, 0xcc12, 0x21, 0 - .dw 0x26c1, 0xcc12, 0x26c1, 0xcc12, 0x21, 0 - .dw 0x26c3, 0xcc12, 0x26cf, 0xcc12, 0x21, 0 - .dw 0x26d1, 0xcc12, 0x26d1, 0xcc12, 0x21, 0 - .dw 0x26d3, 0xcc12, 0x26ff, 0xcc12, 0x21, 0 - .dw 0x2701, 0xcc12, 0x2701, 0xcc12, 0x21, 0 - .dw 0x2703, 0xcc12, 0x270f, 0xcc12, 0x21, 0 - .dw 0x2711, 0xcc12, 0x2711, 0xcc12, 0x21, 0 - .dw 0x2713, 0xcc12, 0x273f, 0xcc12, 0x21, 0 - .dw 0x2741, 0xcc12, 0x2741, 0xcc12, 0x21, 0 - .dw 0x2743, 0xcc12, 0x274f, 0xcc12, 0x21, 0 - .dw 0x2751, 0xcc12, 0x2751, 0xcc12, 0x21, 0 - .dw 0x2753, 0xcc12, 0x277f, 0xcc12, 0x21, 0 - .dw 0x2781, 0xcc12, 0x2781, 0xcc12, 0x21, 0 - .dw 0x2783, 0xcc12, 0x278f, 0xcc12, 0x21, 0 - .dw 0x2791, 0xcc12, 0x2791, 0xcc12, 0x21, 0 - .dw 0x2793, 0xcc12, 0x27bf, 0xcc12, 0x21, 0 - .dw 0x27c1, 0xcc12, 0x27c1, 0xcc12, 0x21, 0 - .dw 0x27c3, 0xcc12, 0x27cf, 0xcc12, 0x21, 0 - .dw 0x27d1, 0xcc12, 0x27d1, 0xcc12, 0x21, 0 - .dw 0x27d3, 0xcc12, 0x27ff, 0xcc12, 0x21, 0 - .dw 0x2801, 0xcc12, 0x2801, 0xcc12, 0x21, 0 - .dw 0x2803, 0xcc12, 0x280f, 0xcc12, 0x21, 0 - .dw 0x2811, 0xcc12, 0x2811, 0xcc12, 0x21, 0 - .dw 0x2813, 0xcc12, 0x283f, 0xcc12, 0x21, 0 - .dw 0x2841, 0xcc12, 0x2841, 0xcc12, 0x21, 0 - .dw 0x2843, 0xcc12, 0x284f, 0xcc12, 0x21, 0 - .dw 0x2851, 0xcc12, 0x2851, 0xcc12, 0x21, 0 - .dw 0x2853, 0xcc12, 0x287f, 0xcc12, 0x21, 0 - .dw 0x2881, 0xcc12, 0x2881, 0xcc12, 0x21, 0 - .dw 0x2883, 0xcc12, 0x288f, 0xcc12, 0x21, 0 - .dw 0x2891, 0xcc12, 0x2891, 0xcc12, 0x21, 0 - .dw 0x2893, 0xcc12, 0x28bf, 0xcc12, 0x21, 0 - .dw 0x28c1, 0xcc12, 0x28c1, 0xcc12, 0x21, 0 - .dw 0x28c3, 0xcc12, 0x28cf, 0xcc12, 0x21, 0 - .dw 0x28d1, 0xcc12, 0x28d1, 0xcc12, 0x21, 0 - .dw 0x28d3, 0xcc12, 0x28ff, 0xcc12, 0x21, 0 - .dw 0x2901, 0xcc12, 0x2901, 0xcc12, 0x21, 0 - .dw 0x2903, 0xcc12, 0x290f, 0xcc12, 0x21, 0 - .dw 0x2911, 0xcc12, 0x2911, 0xcc12, 0x21, 0 - .dw 0x2913, 0xcc12, 0x293f, 0xcc12, 0x21, 0 - .dw 0x2941, 0xcc12, 0x2941, 0xcc12, 0x21, 0 - .dw 0x2943, 0xcc12, 0x294f, 0xcc12, 0x21, 0 - .dw 0x2951, 0xcc12, 0x2951, 0xcc12, 0x21, 0 - .dw 0x2953, 0xcc12, 0x297f, 0xcc12, 0x21, 0 - .dw 0x2981, 0xcc12, 0x2981, 0xcc12, 0x21, 0 - .dw 0x2983, 0xcc12, 0x298f, 0xcc12, 0x21, 0 - .dw 0x2991, 0xcc12, 0x2991, 0xcc12, 0x21, 0 - .dw 0x2993, 0xcc12, 0x29bf, 0xcc12, 0x21, 0 - .dw 0x29c1, 0xcc12, 0x29c1, 0xcc12, 0x21, 0 - .dw 0x29c3, 0xcc12, 0x29cf, 0xcc12, 0x21, 0 - .dw 0x29d1, 0xcc12, 0x29d1, 0xcc12, 0x21, 0 - .dw 0x29d3, 0xcc12, 0x29ff, 0xcc12, 0x21, 0 - .dw 0x2a01, 0xcc12, 0x2a01, 0xcc12, 0x21, 0 - .dw 0x2a03, 0xcc12, 0x2a0f, 0xcc12, 0x21, 0 - .dw 0x2a11, 0xcc12, 0x2a11, 0xcc12, 0x21, 0 - .dw 0x2a13, 0xcc12, 0x2a3f, 0xcc12, 0x21, 0 - .dw 0x2a41, 0xcc12, 0x2a41, 0xcc12, 0x21, 0 - .dw 0x2a43, 0xcc12, 0x2a4f, 0xcc12, 0x21, 0 - .dw 0x2a51, 0xcc12, 0x2a51, 0xcc12, 0x21, 0 - .dw 0x2a53, 0xcc12, 0x2a7f, 0xcc12, 0x21, 0 - .dw 0x2a81, 0xcc12, 0x2a81, 0xcc12, 0x21, 0 - .dw 0x2a83, 0xcc12, 0x2a8f, 0xcc12, 0x21, 0 - .dw 0x2a91, 0xcc12, 0x2a91, 0xcc12, 0x21, 0 - .dw 0x2a93, 0xcc12, 0x2abf, 0xcc12, 0x21, 0 - .dw 0x2ac1, 0xcc12, 0x2ac1, 0xcc12, 0x21, 0 - .dw 0x2ac3, 0xcc12, 0x2acf, 0xcc12, 0x21, 0 - .dw 0x2ad1, 0xcc12, 0x2ad1, 0xcc12, 0x21, 0 - .dw 0x2ad3, 0xcc12, 0x2aff, 0xcc12, 0x21, 0 - .dw 0x2b01, 0xcc12, 0x2b01, 0xcc12, 0x21, 0 - .dw 0x2b03, 0xcc12, 0x2b0f, 0xcc12, 0x21, 0 - .dw 0x2b11, 0xcc12, 0x2b11, 0xcc12, 0x21, 0 - .dw 0x2b13, 0xcc12, 0x2b3f, 0xcc12, 0x21, 0 - .dw 0x2b41, 0xcc12, 0x2b41, 0xcc12, 0x21, 0 - .dw 0x2b43, 0xcc12, 0x2b4f, 0xcc12, 0x21, 0 - .dw 0x2b51, 0xcc12, 0x2b51, 0xcc12, 0x21, 0 - .dw 0x2b53, 0xcc12, 0x2b7f, 0xcc12, 0x21, 0 - .dw 0x2b81, 0xcc12, 0x2b81, 0xcc12, 0x21, 0 - .dw 0x2b83, 0xcc12, 0x2b8f, 0xcc12, 0x21, 0 - .dw 0x2b91, 0xcc12, 0x2b91, 0xcc12, 0x21, 0 - .dw 0x2b93, 0xcc12, 0x2bbf, 0xcc12, 0x21, 0 - .dw 0x2bc1, 0xcc12, 0x2bc1, 0xcc12, 0x21, 0 - .dw 0x2bc3, 0xcc12, 0x2bcf, 0xcc12, 0x21, 0 - .dw 0x2bd1, 0xcc12, 0x2bd1, 0xcc12, 0x21, 0 - .dw 0x2bd3, 0xcc12, 0x2bff, 0xcc12, 0x21, 0 - .dw 0x2c01, 0xcc12, 0x2c01, 0xcc12, 0x21, 0 - .dw 0x2c03, 0xcc12, 0x2c0f, 0xcc12, 0x21, 0 - .dw 0x2c11, 0xcc12, 0x2c11, 0xcc12, 0x21, 0 - .dw 0x2c13, 0xcc12, 0x2c3f, 0xcc12, 0x21, 0 - .dw 0x2c41, 0xcc12, 0x2c41, 0xcc12, 0x21, 0 - .dw 0x2c43, 0xcc12, 0x2c4f, 0xcc12, 0x21, 0 - .dw 0x2c51, 0xcc12, 0x2c51, 0xcc12, 0x21, 0 - .dw 0x2c53, 0xcc12, 0x2c7f, 0xcc12, 0x21, 0 - .dw 0x2c81, 0xcc12, 0x2c81, 0xcc12, 0x21, 0 - .dw 0x2c83, 0xcc12, 0x2c8f, 0xcc12, 0x21, 0 - .dw 0x2c91, 0xcc12, 0x2c91, 0xcc12, 0x21, 0 - .dw 0x2c93, 0xcc12, 0x2cbf, 0xcc12, 0x21, 0 - .dw 0x2cc1, 0xcc12, 0x2cc1, 0xcc12, 0x21, 0 - .dw 0x2cc3, 0xcc12, 0x2ccf, 0xcc12, 0x21, 0 - .dw 0x2cd1, 0xcc12, 0x2cd1, 0xcc12, 0x21, 0 - .dw 0x2cd3, 0xcc12, 0x2cff, 0xcc12, 0x21, 0 - .dw 0x2d01, 0xcc12, 0x2d01, 0xcc12, 0x21, 0 - .dw 0x2d03, 0xcc12, 0x2d0f, 0xcc12, 0x21, 0 - .dw 0x2d11, 0xcc12, 0x2d11, 0xcc12, 0x21, 0 - .dw 0x2d13, 0xcc12, 0x2d3f, 0xcc12, 0x21, 0 - .dw 0x2d41, 0xcc12, 0x2d41, 0xcc12, 0x21, 0 - .dw 0x2d43, 0xcc12, 0x2d4f, 0xcc12, 0x21, 0 - .dw 0x2d51, 0xcc12, 0x2d51, 0xcc12, 0x21, 0 - .dw 0x2d53, 0xcc12, 0x2d7f, 0xcc12, 0x21, 0 - .dw 0x2d81, 0xcc12, 0x2d81, 0xcc12, 0x21, 0 - .dw 0x2d83, 0xcc12, 0x2d8f, 0xcc12, 0x21, 0 - .dw 0x2d91, 0xcc12, 0x2d91, 0xcc12, 0x21, 0 - .dw 0x2d93, 0xcc12, 0x2dbf, 0xcc12, 0x21, 0 - .dw 0x2dc1, 0xcc12, 0x2dc1, 0xcc12, 0x21, 0 - .dw 0x2dc3, 0xcc12, 0x2dcf, 0xcc12, 0x21, 0 - .dw 0x2dd1, 0xcc12, 0x2dd1, 0xcc12, 0x21, 0 - .dw 0x2dd3, 0xcc12, 0x2dff, 0xcc12, 0x21, 0 - .dw 0x2e01, 0xcc12, 0x2e01, 0xcc12, 0x21, 0 - .dw 0x2e03, 0xcc12, 0x2e0f, 0xcc12, 0x21, 0 - .dw 0x2e11, 0xcc12, 0x2e11, 0xcc12, 0x21, 0 - .dw 0x2e13, 0xcc12, 0x2e3f, 0xcc12, 0x21, 0 - .dw 0x2e41, 0xcc12, 0x2e41, 0xcc12, 0x21, 0 - .dw 0x2e43, 0xcc12, 0x2e4f, 0xcc12, 0x21, 0 - .dw 0x2e51, 0xcc12, 0x2e51, 0xcc12, 0x21, 0 - .dw 0x2e53, 0xcc12, 0x2e7f, 0xcc12, 0x21, 0 - .dw 0x2e81, 0xcc12, 0x2e81, 0xcc12, 0x21, 0 - .dw 0x2e83, 0xcc12, 0x2e8f, 0xcc12, 0x21, 0 - .dw 0x2e91, 0xcc12, 0x2e91, 0xcc12, 0x21, 0 - .dw 0x2e93, 0xcc12, 0x2ebf, 0xcc12, 0x21, 0 - .dw 0x2ec1, 0xcc12, 0x2ec1, 0xcc12, 0x21, 0 - .dw 0x2ec3, 0xcc12, 0x2ecf, 0xcc12, 0x21, 0 - .dw 0x2ed1, 0xcc12, 0x2ed1, 0xcc12, 0x21, 0 - .dw 0x2ed3, 0xcc12, 0x2eff, 0xcc12, 0x21, 0 - .dw 0x2f01, 0xcc12, 0x2f01, 0xcc12, 0x21, 0 - .dw 0x2f03, 0xcc12, 0x2f0f, 0xcc12, 0x21, 0 - .dw 0x2f11, 0xcc12, 0x2f11, 0xcc12, 0x21, 0 - .dw 0x2f13, 0xcc12, 0x2f3f, 0xcc12, 0x21, 0 - .dw 0x2f41, 0xcc12, 0x2f41, 0xcc12, 0x21, 0 - .dw 0x2f43, 0xcc12, 0x2f4f, 0xcc12, 0x21, 0 - .dw 0x2f51, 0xcc12, 0x2f51, 0xcc12, 0x21, 0 - .dw 0x2f53, 0xcc12, 0x2f7f, 0xcc12, 0x21, 0 - .dw 0x2f81, 0xcc12, 0x2f81, 0xcc12, 0x21, 0 - .dw 0x2f83, 0xcc12, 0x2f8f, 0xcc12, 0x21, 0 - .dw 0x2f91, 0xcc12, 0x2f91, 0xcc12, 0x21, 0 - .dw 0x2f93, 0xcc12, 0x2fbf, 0xcc12, 0x21, 0 - .dw 0x2fc1, 0xcc12, 0x2fc1, 0xcc12, 0x21, 0 - .dw 0x2fc3, 0xcc12, 0x2fcf, 0xcc12, 0x21, 0 - .dw 0x2fd1, 0xcc12, 0x2fd1, 0xcc12, 0x21, 0 - .dw 0x2fd3, 0xcc12, 0xbfff, 0xcc12, 0x21, 0 - .dw 0xd000, 0xcc12, 0xffff, 0xcc13, 0x21, 0 - .dw 0x0001, 0xcc14, 0x0001, 0xcc14, 0x21, 0 - .dw 0x0003, 0xcc14, 0x000f, 0xcc14, 0x21, 0 - .dw 0x0011, 0xcc14, 0x0011, 0xcc14, 0x21, 0 - .dw 0x0013, 0xcc14, 0x003f, 0xcc14, 0x21, 0 - .dw 0x0041, 0xcc14, 0x0041, 0xcc14, 0x21, 0 - .dw 0x0043, 0xcc14, 0x004f, 0xcc14, 0x21, 0 - .dw 0x0051, 0xcc14, 0x0051, 0xcc14, 0x21, 0 - .dw 0x0053, 0xcc14, 0x007f, 0xcc14, 0x21, 0 - .dw 0x0081, 0xcc14, 0x0081, 0xcc14, 0x21, 0 - .dw 0x0083, 0xcc14, 0x008f, 0xcc14, 0x21, 0 - .dw 0x0091, 0xcc14, 0x0091, 0xcc14, 0x21, 0 - .dw 0x0093, 0xcc14, 0x00bf, 0xcc14, 0x21, 0 - .dw 0x00c1, 0xcc14, 0x00c1, 0xcc14, 0x21, 0 - .dw 0x00c3, 0xcc14, 0x00cf, 0xcc14, 0x21, 0 - .dw 0x00d1, 0xcc14, 0x00d1, 0xcc14, 0x21, 0 - .dw 0x00d3, 0xcc14, 0x00ff, 0xcc14, 0x21, 0 - .dw 0x0101, 0xcc14, 0x0101, 0xcc14, 0x21, 0 - .dw 0x0103, 0xcc14, 0x010f, 0xcc14, 0x21, 0 - .dw 0x0111, 0xcc14, 0x0111, 0xcc14, 0x21, 0 - .dw 0x0113, 0xcc14, 0x013f, 0xcc14, 0x21, 0 - .dw 0x0141, 0xcc14, 0x0141, 0xcc14, 0x21, 0 - .dw 0x0143, 0xcc14, 0x014f, 0xcc14, 0x21, 0 - .dw 0x0151, 0xcc14, 0x0151, 0xcc14, 0x21, 0 - .dw 0x0153, 0xcc14, 0x017f, 0xcc14, 0x21, 0 - .dw 0x0181, 0xcc14, 0x0181, 0xcc14, 0x21, 0 - .dw 0x0183, 0xcc14, 0x018f, 0xcc14, 0x21, 0 - .dw 0x0191, 0xcc14, 0x0191, 0xcc14, 0x21, 0 - .dw 0x0193, 0xcc14, 0x01bf, 0xcc14, 0x21, 0 - .dw 0x01c1, 0xcc14, 0x01c1, 0xcc14, 0x21, 0 - .dw 0x01c3, 0xcc14, 0x01cf, 0xcc14, 0x21, 0 - .dw 0x01d1, 0xcc14, 0x01d1, 0xcc14, 0x21, 0 - .dw 0x01d3, 0xcc14, 0x01ff, 0xcc14, 0x21, 0 - .dw 0x0201, 0xcc14, 0x0201, 0xcc14, 0x21, 0 - .dw 0x0203, 0xcc14, 0x020f, 0xcc14, 0x21, 0 - .dw 0x0211, 0xcc14, 0x0211, 0xcc14, 0x21, 0 - .dw 0x0213, 0xcc14, 0x023f, 0xcc14, 0x21, 0 - .dw 0x0241, 0xcc14, 0x0241, 0xcc14, 0x21, 0 - .dw 0x0243, 0xcc14, 0x024f, 0xcc14, 0x21, 0 - .dw 0x0251, 0xcc14, 0x0251, 0xcc14, 0x21, 0 - .dw 0x0253, 0xcc14, 0x027f, 0xcc14, 0x21, 0 - .dw 0x0281, 0xcc14, 0x0281, 0xcc14, 0x21, 0 - .dw 0x0283, 0xcc14, 0x028f, 0xcc14, 0x21, 0 - .dw 0x0291, 0xcc14, 0x0291, 0xcc14, 0x21, 0 - .dw 0x0293, 0xcc14, 0x02bf, 0xcc14, 0x21, 0 - .dw 0x02c1, 0xcc14, 0x02c1, 0xcc14, 0x21, 0 - .dw 0x02c3, 0xcc14, 0x02cf, 0xcc14, 0x21, 0 - .dw 0x02d1, 0xcc14, 0x02d1, 0xcc14, 0x21, 0 - .dw 0x02d3, 0xcc14, 0x02ff, 0xcc14, 0x21, 0 - .dw 0x0301, 0xcc14, 0x0301, 0xcc14, 0x21, 0 - .dw 0x0303, 0xcc14, 0x030f, 0xcc14, 0x21, 0 - .dw 0x0311, 0xcc14, 0x0311, 0xcc14, 0x21, 0 - .dw 0x0313, 0xcc14, 0x033f, 0xcc14, 0x21, 0 - .dw 0x0341, 0xcc14, 0x0341, 0xcc14, 0x21, 0 - .dw 0x0343, 0xcc14, 0x034f, 0xcc14, 0x21, 0 - .dw 0x0351, 0xcc14, 0x0351, 0xcc14, 0x21, 0 - .dw 0x0353, 0xcc14, 0x037f, 0xcc14, 0x21, 0 - .dw 0x0381, 0xcc14, 0x0381, 0xcc14, 0x21, 0 - .dw 0x0383, 0xcc14, 0x038f, 0xcc14, 0x21, 0 - .dw 0x0391, 0xcc14, 0x0391, 0xcc14, 0x21, 0 - .dw 0x0393, 0xcc14, 0x03bf, 0xcc14, 0x21, 0 - .dw 0x03c1, 0xcc14, 0x03c1, 0xcc14, 0x21, 0 - .dw 0x03c3, 0xcc14, 0x03cf, 0xcc14, 0x21, 0 - .dw 0x03d1, 0xcc14, 0x03d1, 0xcc14, 0x21, 0 - .dw 0x03d3, 0xcc14, 0x03ff, 0xcc14, 0x21, 0 - .dw 0x0401, 0xcc14, 0x0401, 0xcc14, 0x21, 0 - .dw 0x0403, 0xcc14, 0x040f, 0xcc14, 0x21, 0 - .dw 0x0411, 0xcc14, 0x0411, 0xcc14, 0x21, 0 - .dw 0x0413, 0xcc14, 0x043f, 0xcc14, 0x21, 0 - .dw 0x0441, 0xcc14, 0x0441, 0xcc14, 0x21, 0 - .dw 0x0443, 0xcc14, 0x044f, 0xcc14, 0x21, 0 - .dw 0x0451, 0xcc14, 0x0451, 0xcc14, 0x21, 0 - .dw 0x0453, 0xcc14, 0x047f, 0xcc14, 0x21, 0 - .dw 0x0481, 0xcc14, 0x0481, 0xcc14, 0x21, 0 - .dw 0x0483, 0xcc14, 0x048f, 0xcc14, 0x21, 0 - .dw 0x0491, 0xcc14, 0x0491, 0xcc14, 0x21, 0 - .dw 0x0493, 0xcc14, 0x04bf, 0xcc14, 0x21, 0 - .dw 0x04c1, 0xcc14, 0x04c1, 0xcc14, 0x21, 0 - .dw 0x04c3, 0xcc14, 0x04cf, 0xcc14, 0x21, 0 - .dw 0x04d1, 0xcc14, 0x04d1, 0xcc14, 0x21, 0 - .dw 0x04d3, 0xcc14, 0x04ff, 0xcc14, 0x21, 0 - .dw 0x0501, 0xcc14, 0x0501, 0xcc14, 0x21, 0 - .dw 0x0503, 0xcc14, 0x050f, 0xcc14, 0x21, 0 - .dw 0x0511, 0xcc14, 0x0511, 0xcc14, 0x21, 0 - .dw 0x0513, 0xcc14, 0x053f, 0xcc14, 0x21, 0 - .dw 0x0541, 0xcc14, 0x0541, 0xcc14, 0x21, 0 - .dw 0x0543, 0xcc14, 0x054f, 0xcc14, 0x21, 0 - .dw 0x0551, 0xcc14, 0x0551, 0xcc14, 0x21, 0 - .dw 0x0553, 0xcc14, 0x057f, 0xcc14, 0x21, 0 - .dw 0x0581, 0xcc14, 0x0581, 0xcc14, 0x21, 0 - .dw 0x0583, 0xcc14, 0x058f, 0xcc14, 0x21, 0 - .dw 0x0591, 0xcc14, 0x0591, 0xcc14, 0x21, 0 - .dw 0x0593, 0xcc14, 0x05bf, 0xcc14, 0x21, 0 - .dw 0x05c1, 0xcc14, 0x05c1, 0xcc14, 0x21, 0 - .dw 0x05c3, 0xcc14, 0x05cf, 0xcc14, 0x21, 0 - .dw 0x05d1, 0xcc14, 0x05d1, 0xcc14, 0x21, 0 - .dw 0x05d3, 0xcc14, 0x05ff, 0xcc14, 0x21, 0 - .dw 0x0601, 0xcc14, 0x0601, 0xcc14, 0x21, 0 - .dw 0x0603, 0xcc14, 0x060f, 0xcc14, 0x21, 0 - .dw 0x0611, 0xcc14, 0x0611, 0xcc14, 0x21, 0 - .dw 0x0613, 0xcc14, 0x063f, 0xcc14, 0x21, 0 - .dw 0x0641, 0xcc14, 0x0641, 0xcc14, 0x21, 0 - .dw 0x0643, 0xcc14, 0x064f, 0xcc14, 0x21, 0 - .dw 0x0651, 0xcc14, 0x0651, 0xcc14, 0x21, 0 - .dw 0x0653, 0xcc14, 0x067f, 0xcc14, 0x21, 0 - .dw 0x0681, 0xcc14, 0x0681, 0xcc14, 0x21, 0 - .dw 0x0683, 0xcc14, 0x068f, 0xcc14, 0x21, 0 - .dw 0x0691, 0xcc14, 0x0691, 0xcc14, 0x21, 0 - .dw 0x0693, 0xcc14, 0x06bf, 0xcc14, 0x21, 0 - .dw 0x06c1, 0xcc14, 0x06c1, 0xcc14, 0x21, 0 - .dw 0x06c3, 0xcc14, 0x06cf, 0xcc14, 0x21, 0 - .dw 0x06d1, 0xcc14, 0x06d1, 0xcc14, 0x21, 0 - .dw 0x06d3, 0xcc14, 0x06ff, 0xcc14, 0x21, 0 - .dw 0x0701, 0xcc14, 0x0701, 0xcc14, 0x21, 0 - .dw 0x0703, 0xcc14, 0x070f, 0xcc14, 0x21, 0 - .dw 0x0711, 0xcc14, 0x0711, 0xcc14, 0x21, 0 - .dw 0x0713, 0xcc14, 0x073f, 0xcc14, 0x21, 0 - .dw 0x0741, 0xcc14, 0x0741, 0xcc14, 0x21, 0 - .dw 0x0743, 0xcc14, 0x074f, 0xcc14, 0x21, 0 - .dw 0x0751, 0xcc14, 0x0751, 0xcc14, 0x21, 0 - .dw 0x0753, 0xcc14, 0x077f, 0xcc14, 0x21, 0 - .dw 0x0781, 0xcc14, 0x0781, 0xcc14, 0x21, 0 - .dw 0x0783, 0xcc14, 0x078f, 0xcc14, 0x21, 0 - .dw 0x0791, 0xcc14, 0x0791, 0xcc14, 0x21, 0 - .dw 0x0793, 0xcc14, 0x07bf, 0xcc14, 0x21, 0 - .dw 0x07c1, 0xcc14, 0x07c1, 0xcc14, 0x21, 0 - .dw 0x07c3, 0xcc14, 0x07cf, 0xcc14, 0x21, 0 - .dw 0x07d1, 0xcc14, 0x07d1, 0xcc14, 0x21, 0 - .dw 0x07d3, 0xcc14, 0x07ff, 0xcc14, 0x21, 0 - .dw 0x0801, 0xcc14, 0x0801, 0xcc14, 0x21, 0 - .dw 0x0803, 0xcc14, 0x080f, 0xcc14, 0x21, 0 - .dw 0x0811, 0xcc14, 0x0811, 0xcc14, 0x21, 0 - .dw 0x0813, 0xcc14, 0x083f, 0xcc14, 0x21, 0 - .dw 0x0841, 0xcc14, 0x0841, 0xcc14, 0x21, 0 - .dw 0x0843, 0xcc14, 0x084f, 0xcc14, 0x21, 0 - .dw 0x0851, 0xcc14, 0x0851, 0xcc14, 0x21, 0 - .dw 0x0853, 0xcc14, 0x087f, 0xcc14, 0x21, 0 - .dw 0x0881, 0xcc14, 0x0881, 0xcc14, 0x21, 0 - .dw 0x0883, 0xcc14, 0x088f, 0xcc14, 0x21, 0 - .dw 0x0891, 0xcc14, 0x0891, 0xcc14, 0x21, 0 - .dw 0x0893, 0xcc14, 0x08bf, 0xcc14, 0x21, 0 - .dw 0x08c1, 0xcc14, 0x08c1, 0xcc14, 0x21, 0 - .dw 0x08c3, 0xcc14, 0x08cf, 0xcc14, 0x21, 0 - .dw 0x08d1, 0xcc14, 0x08d1, 0xcc14, 0x21, 0 - .dw 0x08d3, 0xcc14, 0x08ff, 0xcc14, 0x21, 0 - .dw 0x0901, 0xcc14, 0x0901, 0xcc14, 0x21, 0 - .dw 0x0903, 0xcc14, 0x090f, 0xcc14, 0x21, 0 - .dw 0x0911, 0xcc14, 0x0911, 0xcc14, 0x21, 0 - .dw 0x0913, 0xcc14, 0x093f, 0xcc14, 0x21, 0 - .dw 0x0941, 0xcc14, 0x0941, 0xcc14, 0x21, 0 - .dw 0x0943, 0xcc14, 0x094f, 0xcc14, 0x21, 0 - .dw 0x0951, 0xcc14, 0x0951, 0xcc14, 0x21, 0 - .dw 0x0953, 0xcc14, 0x097f, 0xcc14, 0x21, 0 - .dw 0x0981, 0xcc14, 0x0981, 0xcc14, 0x21, 0 - .dw 0x0983, 0xcc14, 0x098f, 0xcc14, 0x21, 0 - .dw 0x0991, 0xcc14, 0x0991, 0xcc14, 0x21, 0 - .dw 0x0993, 0xcc14, 0x09bf, 0xcc14, 0x21, 0 - .dw 0x09c1, 0xcc14, 0x09c1, 0xcc14, 0x21, 0 - .dw 0x09c3, 0xcc14, 0x09cf, 0xcc14, 0x21, 0 - .dw 0x09d1, 0xcc14, 0x09d1, 0xcc14, 0x21, 0 - .dw 0x09d3, 0xcc14, 0x09ff, 0xcc14, 0x21, 0 - .dw 0x0a01, 0xcc14, 0x0a01, 0xcc14, 0x21, 0 - .dw 0x0a03, 0xcc14, 0x0a0f, 0xcc14, 0x21, 0 - .dw 0x0a11, 0xcc14, 0x0a11, 0xcc14, 0x21, 0 - .dw 0x0a13, 0xcc14, 0x0a3f, 0xcc14, 0x21, 0 - .dw 0x0a41, 0xcc14, 0x0a41, 0xcc14, 0x21, 0 - .dw 0x0a43, 0xcc14, 0x0a4f, 0xcc14, 0x21, 0 - .dw 0x0a51, 0xcc14, 0x0a51, 0xcc14, 0x21, 0 - .dw 0x0a53, 0xcc14, 0x0a7f, 0xcc14, 0x21, 0 - .dw 0x0a81, 0xcc14, 0x0a81, 0xcc14, 0x21, 0 - .dw 0x0a83, 0xcc14, 0x0a8f, 0xcc14, 0x21, 0 - .dw 0x0a91, 0xcc14, 0x0a91, 0xcc14, 0x21, 0 - .dw 0x0a93, 0xcc14, 0x0abf, 0xcc14, 0x21, 0 - .dw 0x0ac1, 0xcc14, 0x0ac1, 0xcc14, 0x21, 0 - .dw 0x0ac3, 0xcc14, 0x0acf, 0xcc14, 0x21, 0 - .dw 0x0ad1, 0xcc14, 0x0ad1, 0xcc14, 0x21, 0 - .dw 0x0ad3, 0xcc14, 0x0aff, 0xcc14, 0x21, 0 - .dw 0x0b01, 0xcc14, 0x0b01, 0xcc14, 0x21, 0 - .dw 0x0b03, 0xcc14, 0x0b0f, 0xcc14, 0x21, 0 - .dw 0x0b11, 0xcc14, 0x0b11, 0xcc14, 0x21, 0 - .dw 0x0b13, 0xcc14, 0x0b3f, 0xcc14, 0x21, 0 - .dw 0x0b41, 0xcc14, 0x0b41, 0xcc14, 0x21, 0 - .dw 0x0b43, 0xcc14, 0x0b4f, 0xcc14, 0x21, 0 - .dw 0x0b51, 0xcc14, 0x0b51, 0xcc14, 0x21, 0 - .dw 0x0b53, 0xcc14, 0x0b7f, 0xcc14, 0x21, 0 - .dw 0x0b81, 0xcc14, 0x0b81, 0xcc14, 0x21, 0 - .dw 0x0b83, 0xcc14, 0x0b8f, 0xcc14, 0x21, 0 - .dw 0x0b91, 0xcc14, 0x0b91, 0xcc14, 0x21, 0 - .dw 0x0b93, 0xcc14, 0x0bbf, 0xcc14, 0x21, 0 - .dw 0x0bc1, 0xcc14, 0x0bc1, 0xcc14, 0x21, 0 - .dw 0x0bc3, 0xcc14, 0x0bcf, 0xcc14, 0x21, 0 - .dw 0x0bd1, 0xcc14, 0x0bd1, 0xcc14, 0x21, 0 - .dw 0x0bd3, 0xcc14, 0x0bff, 0xcc14, 0x21, 0 - .dw 0x0c01, 0xcc14, 0x0c01, 0xcc14, 0x21, 0 - .dw 0x0c03, 0xcc14, 0x0c0f, 0xcc14, 0x21, 0 - .dw 0x0c11, 0xcc14, 0x0c11, 0xcc14, 0x21, 0 - .dw 0x0c13, 0xcc14, 0x0c3f, 0xcc14, 0x21, 0 - .dw 0x0c41, 0xcc14, 0x0c41, 0xcc14, 0x21, 0 - .dw 0x0c43, 0xcc14, 0x0c4f, 0xcc14, 0x21, 0 - .dw 0x0c51, 0xcc14, 0x0c51, 0xcc14, 0x21, 0 - .dw 0x0c53, 0xcc14, 0x0c7f, 0xcc14, 0x21, 0 - .dw 0x0c81, 0xcc14, 0x0c81, 0xcc14, 0x21, 0 - .dw 0x0c83, 0xcc14, 0x0c8f, 0xcc14, 0x21, 0 - .dw 0x0c91, 0xcc14, 0x0c91, 0xcc14, 0x21, 0 - .dw 0x0c93, 0xcc14, 0x0cbf, 0xcc14, 0x21, 0 - .dw 0x0cc1, 0xcc14, 0x0cc1, 0xcc14, 0x21, 0 - .dw 0x0cc3, 0xcc14, 0x0ccf, 0xcc14, 0x21, 0 - .dw 0x0cd1, 0xcc14, 0x0cd1, 0xcc14, 0x21, 0 - .dw 0x0cd3, 0xcc14, 0x0cff, 0xcc14, 0x21, 0 - .dw 0x0d01, 0xcc14, 0x0d01, 0xcc14, 0x21, 0 - .dw 0x0d03, 0xcc14, 0x0d0f, 0xcc14, 0x21, 0 - .dw 0x0d11, 0xcc14, 0x0d11, 0xcc14, 0x21, 0 - .dw 0x0d13, 0xcc14, 0x0d3f, 0xcc14, 0x21, 0 - .dw 0x0d41, 0xcc14, 0x0d41, 0xcc14, 0x21, 0 - .dw 0x0d43, 0xcc14, 0x0d4f, 0xcc14, 0x21, 0 - .dw 0x0d51, 0xcc14, 0x0d51, 0xcc14, 0x21, 0 - .dw 0x0d53, 0xcc14, 0x0d7f, 0xcc14, 0x21, 0 - .dw 0x0d81, 0xcc14, 0x0d81, 0xcc14, 0x21, 0 - .dw 0x0d83, 0xcc14, 0x0d8f, 0xcc14, 0x21, 0 - .dw 0x0d91, 0xcc14, 0x0d91, 0xcc14, 0x21, 0 - .dw 0x0d93, 0xcc14, 0x0dbf, 0xcc14, 0x21, 0 - .dw 0x0dc1, 0xcc14, 0x0dc1, 0xcc14, 0x21, 0 - .dw 0x0dc3, 0xcc14, 0x0dcf, 0xcc14, 0x21, 0 - .dw 0x0dd1, 0xcc14, 0x0dd1, 0xcc14, 0x21, 0 - .dw 0x0dd3, 0xcc14, 0x0dff, 0xcc14, 0x21, 0 - .dw 0x0e01, 0xcc14, 0x0e01, 0xcc14, 0x21, 0 - .dw 0x0e03, 0xcc14, 0x0e0f, 0xcc14, 0x21, 0 - .dw 0x0e11, 0xcc14, 0x0e11, 0xcc14, 0x21, 0 - .dw 0x0e13, 0xcc14, 0x0e3f, 0xcc14, 0x21, 0 - .dw 0x0e41, 0xcc14, 0x0e41, 0xcc14, 0x21, 0 - .dw 0x0e43, 0xcc14, 0x0e4f, 0xcc14, 0x21, 0 - .dw 0x0e51, 0xcc14, 0x0e51, 0xcc14, 0x21, 0 - .dw 0x0e53, 0xcc14, 0x0e7f, 0xcc14, 0x21, 0 - .dw 0x0e81, 0xcc14, 0x0e81, 0xcc14, 0x21, 0 - .dw 0x0e83, 0xcc14, 0x0e8f, 0xcc14, 0x21, 0 - .dw 0x0e91, 0xcc14, 0x0e91, 0xcc14, 0x21, 0 - .dw 0x0e93, 0xcc14, 0x0ebf, 0xcc14, 0x21, 0 - .dw 0x0ec1, 0xcc14, 0x0ec1, 0xcc14, 0x21, 0 - .dw 0x0ec3, 0xcc14, 0x0ecf, 0xcc14, 0x21, 0 - .dw 0x0ed1, 0xcc14, 0x0ed1, 0xcc14, 0x21, 0 - .dw 0x0ed3, 0xcc14, 0x0eff, 0xcc14, 0x21, 0 - .dw 0x0f01, 0xcc14, 0x0f01, 0xcc14, 0x21, 0 - .dw 0x0f03, 0xcc14, 0x0f0f, 0xcc14, 0x21, 0 - .dw 0x0f11, 0xcc14, 0x0f11, 0xcc14, 0x21, 0 - .dw 0x0f13, 0xcc14, 0x0f3f, 0xcc14, 0x21, 0 - .dw 0x0f41, 0xcc14, 0x0f41, 0xcc14, 0x21, 0 - .dw 0x0f43, 0xcc14, 0x0f4f, 0xcc14, 0x21, 0 - .dw 0x0f51, 0xcc14, 0x0f51, 0xcc14, 0x21, 0 - .dw 0x0f53, 0xcc14, 0x0f7f, 0xcc14, 0x21, 0 - .dw 0x0f81, 0xcc14, 0x0f81, 0xcc14, 0x21, 0 - .dw 0x0f83, 0xcc14, 0x0f8f, 0xcc14, 0x21, 0 - .dw 0x0f91, 0xcc14, 0x0f91, 0xcc14, 0x21, 0 - .dw 0x0f93, 0xcc14, 0x0fbf, 0xcc14, 0x21, 0 - .dw 0x0fc1, 0xcc14, 0x0fc1, 0xcc14, 0x21, 0 - .dw 0x0fc3, 0xcc14, 0x0fcf, 0xcc14, 0x21, 0 - .dw 0x0fd1, 0xcc14, 0x0fd1, 0xcc14, 0x21, 0 - .dw 0x0fd3, 0xcc14, 0x1fff, 0xcc14, 0x21, 0 - .dw 0x2001, 0xcc14, 0x2001, 0xcc14, 0x21, 0 - .dw 0x2003, 0xcc14, 0x200f, 0xcc14, 0x21, 0 - .dw 0x2011, 0xcc14, 0x2011, 0xcc14, 0x21, 0 - .dw 0x2013, 0xcc14, 0x203f, 0xcc14, 0x21, 0 - .dw 0x2041, 0xcc14, 0x2041, 0xcc14, 0x21, 0 - .dw 0x2043, 0xcc14, 0x204f, 0xcc14, 0x21, 0 - .dw 0x2051, 0xcc14, 0x2051, 0xcc14, 0x21, 0 - .dw 0x2053, 0xcc14, 0x207f, 0xcc14, 0x21, 0 - .dw 0x2081, 0xcc14, 0x2081, 0xcc14, 0x21, 0 - .dw 0x2083, 0xcc14, 0x208f, 0xcc14, 0x21, 0 - .dw 0x2091, 0xcc14, 0x2091, 0xcc14, 0x21, 0 - .dw 0x2093, 0xcc14, 0x20bf, 0xcc14, 0x21, 0 - .dw 0x20c1, 0xcc14, 0x20c1, 0xcc14, 0x21, 0 - .dw 0x20c3, 0xcc14, 0x20cf, 0xcc14, 0x21, 0 - .dw 0x20d1, 0xcc14, 0x20d1, 0xcc14, 0x21, 0 - .dw 0x20d3, 0xcc14, 0x20ff, 0xcc14, 0x21, 0 - .dw 0x2101, 0xcc14, 0x2101, 0xcc14, 0x21, 0 - .dw 0x2103, 0xcc14, 0x210f, 0xcc14, 0x21, 0 - .dw 0x2111, 0xcc14, 0x2111, 0xcc14, 0x21, 0 - .dw 0x2113, 0xcc14, 0x213f, 0xcc14, 0x21, 0 - .dw 0x2141, 0xcc14, 0x2141, 0xcc14, 0x21, 0 - .dw 0x2143, 0xcc14, 0x214f, 0xcc14, 0x21, 0 - .dw 0x2151, 0xcc14, 0x2151, 0xcc14, 0x21, 0 - .dw 0x2153, 0xcc14, 0x217f, 0xcc14, 0x21, 0 - .dw 0x2181, 0xcc14, 0x2181, 0xcc14, 0x21, 0 - .dw 0x2183, 0xcc14, 0x218f, 0xcc14, 0x21, 0 - .dw 0x2191, 0xcc14, 0x2191, 0xcc14, 0x21, 0 - .dw 0x2193, 0xcc14, 0x21bf, 0xcc14, 0x21, 0 - .dw 0x21c1, 0xcc14, 0x21c1, 0xcc14, 0x21, 0 - .dw 0x21c3, 0xcc14, 0x21cf, 0xcc14, 0x21, 0 - .dw 0x21d1, 0xcc14, 0x21d1, 0xcc14, 0x21, 0 - .dw 0x21d3, 0xcc14, 0x21ff, 0xcc14, 0x21, 0 - .dw 0x2201, 0xcc14, 0x2201, 0xcc14, 0x21, 0 - .dw 0x2203, 0xcc14, 0x220f, 0xcc14, 0x21, 0 - .dw 0x2211, 0xcc14, 0x2211, 0xcc14, 0x21, 0 - .dw 0x2213, 0xcc14, 0x223f, 0xcc14, 0x21, 0 - .dw 0x2241, 0xcc14, 0x2241, 0xcc14, 0x21, 0 - .dw 0x2243, 0xcc14, 0x224f, 0xcc14, 0x21, 0 - .dw 0x2251, 0xcc14, 0x2251, 0xcc14, 0x21, 0 - .dw 0x2253, 0xcc14, 0x227f, 0xcc14, 0x21, 0 - .dw 0x2281, 0xcc14, 0x2281, 0xcc14, 0x21, 0 - .dw 0x2283, 0xcc14, 0x228f, 0xcc14, 0x21, 0 - .dw 0x2291, 0xcc14, 0x2291, 0xcc14, 0x21, 0 - .dw 0x2293, 0xcc14, 0x22bf, 0xcc14, 0x21, 0 - .dw 0x22c1, 0xcc14, 0x22c1, 0xcc14, 0x21, 0 - .dw 0x22c3, 0xcc14, 0x22cf, 0xcc14, 0x21, 0 - .dw 0x22d1, 0xcc14, 0x22d1, 0xcc14, 0x21, 0 - .dw 0x22d3, 0xcc14, 0x22ff, 0xcc14, 0x21, 0 - .dw 0x2301, 0xcc14, 0x2301, 0xcc14, 0x21, 0 - .dw 0x2303, 0xcc14, 0x230f, 0xcc14, 0x21, 0 - .dw 0x2311, 0xcc14, 0x2311, 0xcc14, 0x21, 0 - .dw 0x2313, 0xcc14, 0x233f, 0xcc14, 0x21, 0 - .dw 0x2341, 0xcc14, 0x2341, 0xcc14, 0x21, 0 - .dw 0x2343, 0xcc14, 0x234f, 0xcc14, 0x21, 0 - .dw 0x2351, 0xcc14, 0x2351, 0xcc14, 0x21, 0 - .dw 0x2353, 0xcc14, 0x237f, 0xcc14, 0x21, 0 - .dw 0x2381, 0xcc14, 0x2381, 0xcc14, 0x21, 0 - .dw 0x2383, 0xcc14, 0x238f, 0xcc14, 0x21, 0 - .dw 0x2391, 0xcc14, 0x2391, 0xcc14, 0x21, 0 - .dw 0x2393, 0xcc14, 0x23bf, 0xcc14, 0x21, 0 - .dw 0x23c1, 0xcc14, 0x23c1, 0xcc14, 0x21, 0 - .dw 0x23c3, 0xcc14, 0x23cf, 0xcc14, 0x21, 0 - .dw 0x23d1, 0xcc14, 0x23d1, 0xcc14, 0x21, 0 - .dw 0x23d3, 0xcc14, 0x23ff, 0xcc14, 0x21, 0 - .dw 0x2401, 0xcc14, 0x2401, 0xcc14, 0x21, 0 - .dw 0x2403, 0xcc14, 0x240f, 0xcc14, 0x21, 0 - .dw 0x2411, 0xcc14, 0x2411, 0xcc14, 0x21, 0 - .dw 0x2413, 0xcc14, 0x243f, 0xcc14, 0x21, 0 - .dw 0x2441, 0xcc14, 0x2441, 0xcc14, 0x21, 0 - .dw 0x2443, 0xcc14, 0x244f, 0xcc14, 0x21, 0 - .dw 0x2451, 0xcc14, 0x2451, 0xcc14, 0x21, 0 - .dw 0x2453, 0xcc14, 0x247f, 0xcc14, 0x21, 0 - .dw 0x2481, 0xcc14, 0x2481, 0xcc14, 0x21, 0 - .dw 0x2483, 0xcc14, 0x248f, 0xcc14, 0x21, 0 - .dw 0x2491, 0xcc14, 0x2491, 0xcc14, 0x21, 0 - .dw 0x2493, 0xcc14, 0x24bf, 0xcc14, 0x21, 0 - .dw 0x24c1, 0xcc14, 0x24c1, 0xcc14, 0x21, 0 - .dw 0x24c3, 0xcc14, 0x24cf, 0xcc14, 0x21, 0 - .dw 0x24d1, 0xcc14, 0x24d1, 0xcc14, 0x21, 0 - .dw 0x24d3, 0xcc14, 0x24ff, 0xcc14, 0x21, 0 - .dw 0x2501, 0xcc14, 0x2501, 0xcc14, 0x21, 0 - .dw 0x2503, 0xcc14, 0x250f, 0xcc14, 0x21, 0 - .dw 0x2511, 0xcc14, 0x2511, 0xcc14, 0x21, 0 - .dw 0x2513, 0xcc14, 0x253f, 0xcc14, 0x21, 0 - .dw 0x2541, 0xcc14, 0x2541, 0xcc14, 0x21, 0 - .dw 0x2543, 0xcc14, 0x254f, 0xcc14, 0x21, 0 - .dw 0x2551, 0xcc14, 0x2551, 0xcc14, 0x21, 0 - .dw 0x2553, 0xcc14, 0x257f, 0xcc14, 0x21, 0 - .dw 0x2581, 0xcc14, 0x2581, 0xcc14, 0x21, 0 - .dw 0x2583, 0xcc14, 0x258f, 0xcc14, 0x21, 0 - .dw 0x2591, 0xcc14, 0x2591, 0xcc14, 0x21, 0 - .dw 0x2593, 0xcc14, 0x25bf, 0xcc14, 0x21, 0 - .dw 0x25c1, 0xcc14, 0x25c1, 0xcc14, 0x21, 0 - .dw 0x25c3, 0xcc14, 0x25cf, 0xcc14, 0x21, 0 - .dw 0x25d1, 0xcc14, 0x25d1, 0xcc14, 0x21, 0 - .dw 0x25d3, 0xcc14, 0x25ff, 0xcc14, 0x21, 0 - .dw 0x2601, 0xcc14, 0x2601, 0xcc14, 0x21, 0 - .dw 0x2603, 0xcc14, 0x260f, 0xcc14, 0x21, 0 - .dw 0x2611, 0xcc14, 0x2611, 0xcc14, 0x21, 0 - .dw 0x2613, 0xcc14, 0x263f, 0xcc14, 0x21, 0 - .dw 0x2641, 0xcc14, 0x2641, 0xcc14, 0x21, 0 - .dw 0x2643, 0xcc14, 0x264f, 0xcc14, 0x21, 0 - .dw 0x2651, 0xcc14, 0x2651, 0xcc14, 0x21, 0 - .dw 0x2653, 0xcc14, 0x267f, 0xcc14, 0x21, 0 - .dw 0x2681, 0xcc14, 0x2681, 0xcc14, 0x21, 0 - .dw 0x2683, 0xcc14, 0x268f, 0xcc14, 0x21, 0 - .dw 0x2691, 0xcc14, 0x2691, 0xcc14, 0x21, 0 - .dw 0x2693, 0xcc14, 0x26bf, 0xcc14, 0x21, 0 - .dw 0x26c1, 0xcc14, 0x26c1, 0xcc14, 0x21, 0 - .dw 0x26c3, 0xcc14, 0x26cf, 0xcc14, 0x21, 0 - .dw 0x26d1, 0xcc14, 0x26d1, 0xcc14, 0x21, 0 - .dw 0x26d3, 0xcc14, 0x26ff, 0xcc14, 0x21, 0 - .dw 0x2701, 0xcc14, 0x2701, 0xcc14, 0x21, 0 - .dw 0x2703, 0xcc14, 0x270f, 0xcc14, 0x21, 0 - .dw 0x2711, 0xcc14, 0x2711, 0xcc14, 0x21, 0 - .dw 0x2713, 0xcc14, 0x273f, 0xcc14, 0x21, 0 - .dw 0x2741, 0xcc14, 0x2741, 0xcc14, 0x21, 0 - .dw 0x2743, 0xcc14, 0x274f, 0xcc14, 0x21, 0 - .dw 0x2751, 0xcc14, 0x2751, 0xcc14, 0x21, 0 - .dw 0x2753, 0xcc14, 0x277f, 0xcc14, 0x21, 0 - .dw 0x2781, 0xcc14, 0x2781, 0xcc14, 0x21, 0 - .dw 0x2783, 0xcc14, 0x278f, 0xcc14, 0x21, 0 - .dw 0x2791, 0xcc14, 0x2791, 0xcc14, 0x21, 0 - .dw 0x2793, 0xcc14, 0x27bf, 0xcc14, 0x21, 0 - .dw 0x27c1, 0xcc14, 0x27c1, 0xcc14, 0x21, 0 - .dw 0x27c3, 0xcc14, 0x27cf, 0xcc14, 0x21, 0 - .dw 0x27d1, 0xcc14, 0x27d1, 0xcc14, 0x21, 0 - .dw 0x27d3, 0xcc14, 0x27ff, 0xcc14, 0x21, 0 - .dw 0x2801, 0xcc14, 0x2801, 0xcc14, 0x21, 0 - .dw 0x2803, 0xcc14, 0x280f, 0xcc14, 0x21, 0 - .dw 0x2811, 0xcc14, 0x2811, 0xcc14, 0x21, 0 - .dw 0x2813, 0xcc14, 0x283f, 0xcc14, 0x21, 0 - .dw 0x2841, 0xcc14, 0x2841, 0xcc14, 0x21, 0 - .dw 0x2843, 0xcc14, 0x284f, 0xcc14, 0x21, 0 - .dw 0x2851, 0xcc14, 0x2851, 0xcc14, 0x21, 0 - .dw 0x2853, 0xcc14, 0x287f, 0xcc14, 0x21, 0 - .dw 0x2881, 0xcc14, 0x2881, 0xcc14, 0x21, 0 - .dw 0x2883, 0xcc14, 0x288f, 0xcc14, 0x21, 0 - .dw 0x2891, 0xcc14, 0x2891, 0xcc14, 0x21, 0 - .dw 0x2893, 0xcc14, 0x28bf, 0xcc14, 0x21, 0 - .dw 0x28c1, 0xcc14, 0x28c1, 0xcc14, 0x21, 0 - .dw 0x28c3, 0xcc14, 0x28cf, 0xcc14, 0x21, 0 - .dw 0x28d1, 0xcc14, 0x28d1, 0xcc14, 0x21, 0 - .dw 0x28d3, 0xcc14, 0x28ff, 0xcc14, 0x21, 0 - .dw 0x2901, 0xcc14, 0x2901, 0xcc14, 0x21, 0 - .dw 0x2903, 0xcc14, 0x290f, 0xcc14, 0x21, 0 - .dw 0x2911, 0xcc14, 0x2911, 0xcc14, 0x21, 0 - .dw 0x2913, 0xcc14, 0x293f, 0xcc14, 0x21, 0 - .dw 0x2941, 0xcc14, 0x2941, 0xcc14, 0x21, 0 - .dw 0x2943, 0xcc14, 0x294f, 0xcc14, 0x21, 0 - .dw 0x2951, 0xcc14, 0x2951, 0xcc14, 0x21, 0 - .dw 0x2953, 0xcc14, 0x297f, 0xcc14, 0x21, 0 - .dw 0x2981, 0xcc14, 0x2981, 0xcc14, 0x21, 0 - .dw 0x2983, 0xcc14, 0x298f, 0xcc14, 0x21, 0 - .dw 0x2991, 0xcc14, 0x2991, 0xcc14, 0x21, 0 - .dw 0x2993, 0xcc14, 0x29bf, 0xcc14, 0x21, 0 - .dw 0x29c1, 0xcc14, 0x29c1, 0xcc14, 0x21, 0 - .dw 0x29c3, 0xcc14, 0x29cf, 0xcc14, 0x21, 0 - .dw 0x29d1, 0xcc14, 0x29d1, 0xcc14, 0x21, 0 - .dw 0x29d3, 0xcc14, 0x29ff, 0xcc14, 0x21, 0 - .dw 0x2a01, 0xcc14, 0x2a01, 0xcc14, 0x21, 0 - .dw 0x2a03, 0xcc14, 0x2a0f, 0xcc14, 0x21, 0 - .dw 0x2a11, 0xcc14, 0x2a11, 0xcc14, 0x21, 0 - .dw 0x2a13, 0xcc14, 0x2a3f, 0xcc14, 0x21, 0 - .dw 0x2a41, 0xcc14, 0x2a41, 0xcc14, 0x21, 0 - .dw 0x2a43, 0xcc14, 0x2a4f, 0xcc14, 0x21, 0 - .dw 0x2a51, 0xcc14, 0x2a51, 0xcc14, 0x21, 0 - .dw 0x2a53, 0xcc14, 0x2a7f, 0xcc14, 0x21, 0 - .dw 0x2a81, 0xcc14, 0x2a81, 0xcc14, 0x21, 0 - .dw 0x2a83, 0xcc14, 0x2a8f, 0xcc14, 0x21, 0 - .dw 0x2a91, 0xcc14, 0x2a91, 0xcc14, 0x21, 0 - .dw 0x2a93, 0xcc14, 0x2abf, 0xcc14, 0x21, 0 - .dw 0x2ac1, 0xcc14, 0x2ac1, 0xcc14, 0x21, 0 - .dw 0x2ac3, 0xcc14, 0x2acf, 0xcc14, 0x21, 0 - .dw 0x2ad1, 0xcc14, 0x2ad1, 0xcc14, 0x21, 0 - .dw 0x2ad3, 0xcc14, 0x2aff, 0xcc14, 0x21, 0 - .dw 0x2b01, 0xcc14, 0x2b01, 0xcc14, 0x21, 0 - .dw 0x2b03, 0xcc14, 0x2b0f, 0xcc14, 0x21, 0 - .dw 0x2b11, 0xcc14, 0x2b11, 0xcc14, 0x21, 0 - .dw 0x2b13, 0xcc14, 0x2b3f, 0xcc14, 0x21, 0 - .dw 0x2b41, 0xcc14, 0x2b41, 0xcc14, 0x21, 0 - .dw 0x2b43, 0xcc14, 0x2b4f, 0xcc14, 0x21, 0 - .dw 0x2b51, 0xcc14, 0x2b51, 0xcc14, 0x21, 0 - .dw 0x2b53, 0xcc14, 0x2b7f, 0xcc14, 0x21, 0 - .dw 0x2b81, 0xcc14, 0x2b81, 0xcc14, 0x21, 0 - .dw 0x2b83, 0xcc14, 0x2b8f, 0xcc14, 0x21, 0 - .dw 0x2b91, 0xcc14, 0x2b91, 0xcc14, 0x21, 0 - .dw 0x2b93, 0xcc14, 0x2bbf, 0xcc14, 0x21, 0 - .dw 0x2bc1, 0xcc14, 0x2bc1, 0xcc14, 0x21, 0 - .dw 0x2bc3, 0xcc14, 0x2bcf, 0xcc14, 0x21, 0 - .dw 0x2bd1, 0xcc14, 0x2bd1, 0xcc14, 0x21, 0 - .dw 0x2bd3, 0xcc14, 0x2bff, 0xcc14, 0x21, 0 - .dw 0x2c01, 0xcc14, 0x2c01, 0xcc14, 0x21, 0 - .dw 0x2c03, 0xcc14, 0x2c0f, 0xcc14, 0x21, 0 - .dw 0x2c11, 0xcc14, 0x2c11, 0xcc14, 0x21, 0 - .dw 0x2c13, 0xcc14, 0x2c3f, 0xcc14, 0x21, 0 - .dw 0x2c41, 0xcc14, 0x2c41, 0xcc14, 0x21, 0 - .dw 0x2c43, 0xcc14, 0x2c4f, 0xcc14, 0x21, 0 - .dw 0x2c51, 0xcc14, 0x2c51, 0xcc14, 0x21, 0 - .dw 0x2c53, 0xcc14, 0x2c7f, 0xcc14, 0x21, 0 - .dw 0x2c81, 0xcc14, 0x2c81, 0xcc14, 0x21, 0 - .dw 0x2c83, 0xcc14, 0x2c8f, 0xcc14, 0x21, 0 - .dw 0x2c91, 0xcc14, 0x2c91, 0xcc14, 0x21, 0 - .dw 0x2c93, 0xcc14, 0x2cbf, 0xcc14, 0x21, 0 - .dw 0x2cc1, 0xcc14, 0x2cc1, 0xcc14, 0x21, 0 - .dw 0x2cc3, 0xcc14, 0x2ccf, 0xcc14, 0x21, 0 - .dw 0x2cd1, 0xcc14, 0x2cd1, 0xcc14, 0x21, 0 - .dw 0x2cd3, 0xcc14, 0x2cff, 0xcc14, 0x21, 0 - .dw 0x2d01, 0xcc14, 0x2d01, 0xcc14, 0x21, 0 - .dw 0x2d03, 0xcc14, 0x2d0f, 0xcc14, 0x21, 0 - .dw 0x2d11, 0xcc14, 0x2d11, 0xcc14, 0x21, 0 - .dw 0x2d13, 0xcc14, 0x2d3f, 0xcc14, 0x21, 0 - .dw 0x2d41, 0xcc14, 0x2d41, 0xcc14, 0x21, 0 - .dw 0x2d43, 0xcc14, 0x2d4f, 0xcc14, 0x21, 0 - .dw 0x2d51, 0xcc14, 0x2d51, 0xcc14, 0x21, 0 - .dw 0x2d53, 0xcc14, 0x2d7f, 0xcc14, 0x21, 0 - .dw 0x2d81, 0xcc14, 0x2d81, 0xcc14, 0x21, 0 - .dw 0x2d83, 0xcc14, 0x2d8f, 0xcc14, 0x21, 0 - .dw 0x2d91, 0xcc14, 0x2d91, 0xcc14, 0x21, 0 - .dw 0x2d93, 0xcc14, 0x2dbf, 0xcc14, 0x21, 0 - .dw 0x2dc1, 0xcc14, 0x2dc1, 0xcc14, 0x21, 0 - .dw 0x2dc3, 0xcc14, 0x2dcf, 0xcc14, 0x21, 0 - .dw 0x2dd1, 0xcc14, 0x2dd1, 0xcc14, 0x21, 0 - .dw 0x2dd3, 0xcc14, 0x2dff, 0xcc14, 0x21, 0 - .dw 0x2e01, 0xcc14, 0x2e01, 0xcc14, 0x21, 0 - .dw 0x2e03, 0xcc14, 0x2e0f, 0xcc14, 0x21, 0 - .dw 0x2e11, 0xcc14, 0x2e11, 0xcc14, 0x21, 0 - .dw 0x2e13, 0xcc14, 0x2e3f, 0xcc14, 0x21, 0 - .dw 0x2e41, 0xcc14, 0x2e41, 0xcc14, 0x21, 0 - .dw 0x2e43, 0xcc14, 0x2e4f, 0xcc14, 0x21, 0 - .dw 0x2e51, 0xcc14, 0x2e51, 0xcc14, 0x21, 0 - .dw 0x2e53, 0xcc14, 0x2e7f, 0xcc14, 0x21, 0 - .dw 0x2e81, 0xcc14, 0x2e81, 0xcc14, 0x21, 0 - .dw 0x2e83, 0xcc14, 0x2e8f, 0xcc14, 0x21, 0 - .dw 0x2e91, 0xcc14, 0x2e91, 0xcc14, 0x21, 0 - .dw 0x2e93, 0xcc14, 0x2ebf, 0xcc14, 0x21, 0 - .dw 0x2ec1, 0xcc14, 0x2ec1, 0xcc14, 0x21, 0 - .dw 0x2ec3, 0xcc14, 0x2ecf, 0xcc14, 0x21, 0 - .dw 0x2ed1, 0xcc14, 0x2ed1, 0xcc14, 0x21, 0 - .dw 0x2ed3, 0xcc14, 0x2eff, 0xcc14, 0x21, 0 - .dw 0x2f01, 0xcc14, 0x2f01, 0xcc14, 0x21, 0 - .dw 0x2f03, 0xcc14, 0x2f0f, 0xcc14, 0x21, 0 - .dw 0x2f11, 0xcc14, 0x2f11, 0xcc14, 0x21, 0 - .dw 0x2f13, 0xcc14, 0x2f3f, 0xcc14, 0x21, 0 - .dw 0x2f41, 0xcc14, 0x2f41, 0xcc14, 0x21, 0 - .dw 0x2f43, 0xcc14, 0x2f4f, 0xcc14, 0x21, 0 - .dw 0x2f51, 0xcc14, 0x2f51, 0xcc14, 0x21, 0 - .dw 0x2f53, 0xcc14, 0x2f7f, 0xcc14, 0x21, 0 - .dw 0x2f81, 0xcc14, 0x2f81, 0xcc14, 0x21, 0 - .dw 0x2f83, 0xcc14, 0x2f8f, 0xcc14, 0x21, 0 - .dw 0x2f91, 0xcc14, 0x2f91, 0xcc14, 0x21, 0 - .dw 0x2f93, 0xcc14, 0x2fbf, 0xcc14, 0x21, 0 - .dw 0x2fc1, 0xcc14, 0x2fc1, 0xcc14, 0x21, 0 - .dw 0x2fc3, 0xcc14, 0x2fcf, 0xcc14, 0x21, 0 - .dw 0x2fd1, 0xcc14, 0x2fd1, 0xcc14, 0x21, 0 - .dw 0x2fd3, 0xcc14, 0x3fff, 0xcc14, 0x21, 0 - .dw 0x4001, 0xcc14, 0x4001, 0xcc14, 0x21, 0 - .dw 0x4003, 0xcc14, 0x400f, 0xcc14, 0x21, 0 - .dw 0x4011, 0xcc14, 0x4011, 0xcc14, 0x21, 0 - .dw 0x4013, 0xcc14, 0x403f, 0xcc14, 0x21, 0 - .dw 0x4041, 0xcc14, 0x4041, 0xcc14, 0x21, 0 - .dw 0x4043, 0xcc14, 0x404f, 0xcc14, 0x21, 0 - .dw 0x4051, 0xcc14, 0x4051, 0xcc14, 0x21, 0 - .dw 0x4053, 0xcc14, 0x407f, 0xcc14, 0x21, 0 - .dw 0x4081, 0xcc14, 0x4081, 0xcc14, 0x21, 0 - .dw 0x4083, 0xcc14, 0x408f, 0xcc14, 0x21, 0 - .dw 0x4091, 0xcc14, 0x4091, 0xcc14, 0x21, 0 - .dw 0x4093, 0xcc14, 0x40bf, 0xcc14, 0x21, 0 - .dw 0x40c1, 0xcc14, 0x40c1, 0xcc14, 0x21, 0 - .dw 0x40c3, 0xcc14, 0x40cf, 0xcc14, 0x21, 0 - .dw 0x40d1, 0xcc14, 0x40d1, 0xcc14, 0x21, 0 - .dw 0x40d3, 0xcc14, 0x40ff, 0xcc14, 0x21, 0 - .dw 0x4101, 0xcc14, 0x4101, 0xcc14, 0x21, 0 - .dw 0x4103, 0xcc14, 0x410f, 0xcc14, 0x21, 0 - .dw 0x4111, 0xcc14, 0x4111, 0xcc14, 0x21, 0 - .dw 0x4113, 0xcc14, 0x413f, 0xcc14, 0x21, 0 - .dw 0x4141, 0xcc14, 0x4141, 0xcc14, 0x21, 0 - .dw 0x4143, 0xcc14, 0x414f, 0xcc14, 0x21, 0 - .dw 0x4151, 0xcc14, 0x4151, 0xcc14, 0x21, 0 - .dw 0x4153, 0xcc14, 0x417f, 0xcc14, 0x21, 0 - .dw 0x4181, 0xcc14, 0x4181, 0xcc14, 0x21, 0 - .dw 0x4183, 0xcc14, 0x418f, 0xcc14, 0x21, 0 - .dw 0x4191, 0xcc14, 0x4191, 0xcc14, 0x21, 0 - .dw 0x4193, 0xcc14, 0x41bf, 0xcc14, 0x21, 0 - .dw 0x41c1, 0xcc14, 0x41c1, 0xcc14, 0x21, 0 - .dw 0x41c3, 0xcc14, 0x41cf, 0xcc14, 0x21, 0 - .dw 0x41d1, 0xcc14, 0x41d1, 0xcc14, 0x21, 0 - .dw 0x41d3, 0xcc14, 0x41ff, 0xcc14, 0x21, 0 - .dw 0x4201, 0xcc14, 0x4201, 0xcc14, 0x21, 0 - .dw 0x4203, 0xcc14, 0x420f, 0xcc14, 0x21, 0 - .dw 0x4211, 0xcc14, 0x4211, 0xcc14, 0x21, 0 - .dw 0x4213, 0xcc14, 0x423f, 0xcc14, 0x21, 0 - .dw 0x4241, 0xcc14, 0x4241, 0xcc14, 0x21, 0 - .dw 0x4243, 0xcc14, 0x424f, 0xcc14, 0x21, 0 - .dw 0x4251, 0xcc14, 0x4251, 0xcc14, 0x21, 0 - .dw 0x4253, 0xcc14, 0x427f, 0xcc14, 0x21, 0 - .dw 0x4281, 0xcc14, 0x4281, 0xcc14, 0x21, 0 - .dw 0x4283, 0xcc14, 0x428f, 0xcc14, 0x21, 0 - .dw 0x4291, 0xcc14, 0x4291, 0xcc14, 0x21, 0 - .dw 0x4293, 0xcc14, 0x42bf, 0xcc14, 0x21, 0 - .dw 0x42c1, 0xcc14, 0x42c1, 0xcc14, 0x21, 0 - .dw 0x42c3, 0xcc14, 0x42cf, 0xcc14, 0x21, 0 - .dw 0x42d1, 0xcc14, 0x42d1, 0xcc14, 0x21, 0 - .dw 0x42d3, 0xcc14, 0x42ff, 0xcc14, 0x21, 0 - .dw 0x4301, 0xcc14, 0x4301, 0xcc14, 0x21, 0 - .dw 0x4303, 0xcc14, 0x430f, 0xcc14, 0x21, 0 - .dw 0x4311, 0xcc14, 0x4311, 0xcc14, 0x21, 0 - .dw 0x4313, 0xcc14, 0x433f, 0xcc14, 0x21, 0 - .dw 0x4341, 0xcc14, 0x4341, 0xcc14, 0x21, 0 - .dw 0x4343, 0xcc14, 0x434f, 0xcc14, 0x21, 0 - .dw 0x4351, 0xcc14, 0x4351, 0xcc14, 0x21, 0 - .dw 0x4353, 0xcc14, 0x437f, 0xcc14, 0x21, 0 - .dw 0x4381, 0xcc14, 0x4381, 0xcc14, 0x21, 0 - .dw 0x4383, 0xcc14, 0x438f, 0xcc14, 0x21, 0 - .dw 0x4391, 0xcc14, 0x4391, 0xcc14, 0x21, 0 - .dw 0x4393, 0xcc14, 0x43bf, 0xcc14, 0x21, 0 - .dw 0x43c1, 0xcc14, 0x43c1, 0xcc14, 0x21, 0 - .dw 0x43c3, 0xcc14, 0x43cf, 0xcc14, 0x21, 0 - .dw 0x43d1, 0xcc14, 0x43d1, 0xcc14, 0x21, 0 - .dw 0x43d3, 0xcc14, 0x43ff, 0xcc14, 0x21, 0 - .dw 0x4401, 0xcc14, 0x4401, 0xcc14, 0x21, 0 - .dw 0x4403, 0xcc14, 0x440f, 0xcc14, 0x21, 0 - .dw 0x4411, 0xcc14, 0x4411, 0xcc14, 0x21, 0 - .dw 0x4413, 0xcc14, 0x443f, 0xcc14, 0x21, 0 - .dw 0x4441, 0xcc14, 0x4441, 0xcc14, 0x21, 0 - .dw 0x4443, 0xcc14, 0x444f, 0xcc14, 0x21, 0 - .dw 0x4451, 0xcc14, 0x4451, 0xcc14, 0x21, 0 - .dw 0x4453, 0xcc14, 0x447f, 0xcc14, 0x21, 0 - .dw 0x4481, 0xcc14, 0x4481, 0xcc14, 0x21, 0 - .dw 0x4483, 0xcc14, 0x448f, 0xcc14, 0x21, 0 - .dw 0x4491, 0xcc14, 0x4491, 0xcc14, 0x21, 0 - .dw 0x4493, 0xcc14, 0x44bf, 0xcc14, 0x21, 0 - .dw 0x44c1, 0xcc14, 0x44c1, 0xcc14, 0x21, 0 - .dw 0x44c3, 0xcc14, 0x44cf, 0xcc14, 0x21, 0 - .dw 0x44d1, 0xcc14, 0x44d1, 0xcc14, 0x21, 0 - .dw 0x44d3, 0xcc14, 0x44ff, 0xcc14, 0x21, 0 - .dw 0x4501, 0xcc14, 0x4501, 0xcc14, 0x21, 0 - .dw 0x4503, 0xcc14, 0x450f, 0xcc14, 0x21, 0 - .dw 0x4511, 0xcc14, 0x4511, 0xcc14, 0x21, 0 - .dw 0x4513, 0xcc14, 0x453f, 0xcc14, 0x21, 0 - .dw 0x4541, 0xcc14, 0x4541, 0xcc14, 0x21, 0 - .dw 0x4543, 0xcc14, 0x454f, 0xcc14, 0x21, 0 - .dw 0x4551, 0xcc14, 0x4551, 0xcc14, 0x21, 0 - .dw 0x4553, 0xcc14, 0x457f, 0xcc14, 0x21, 0 - .dw 0x4581, 0xcc14, 0x4581, 0xcc14, 0x21, 0 - .dw 0x4583, 0xcc14, 0x458f, 0xcc14, 0x21, 0 - .dw 0x4591, 0xcc14, 0x4591, 0xcc14, 0x21, 0 - .dw 0x4593, 0xcc14, 0x45bf, 0xcc14, 0x21, 0 - .dw 0x45c1, 0xcc14, 0x45c1, 0xcc14, 0x21, 0 - .dw 0x45c3, 0xcc14, 0x45cf, 0xcc14, 0x21, 0 - .dw 0x45d1, 0xcc14, 0x45d1, 0xcc14, 0x21, 0 - .dw 0x45d3, 0xcc14, 0x45ff, 0xcc14, 0x21, 0 - .dw 0x4601, 0xcc14, 0x4601, 0xcc14, 0x21, 0 - .dw 0x4603, 0xcc14, 0x460f, 0xcc14, 0x21, 0 - .dw 0x4611, 0xcc14, 0x4611, 0xcc14, 0x21, 0 - .dw 0x4613, 0xcc14, 0x463f, 0xcc14, 0x21, 0 - .dw 0x4641, 0xcc14, 0x4641, 0xcc14, 0x21, 0 - .dw 0x4643, 0xcc14, 0x464f, 0xcc14, 0x21, 0 - .dw 0x4651, 0xcc14, 0x4651, 0xcc14, 0x21, 0 - .dw 0x4653, 0xcc14, 0x467f, 0xcc14, 0x21, 0 - .dw 0x4681, 0xcc14, 0x4681, 0xcc14, 0x21, 0 - .dw 0x4683, 0xcc14, 0x468f, 0xcc14, 0x21, 0 - .dw 0x4691, 0xcc14, 0x4691, 0xcc14, 0x21, 0 - .dw 0x4693, 0xcc14, 0x46bf, 0xcc14, 0x21, 0 - .dw 0x46c1, 0xcc14, 0x46c1, 0xcc14, 0x21, 0 - .dw 0x46c3, 0xcc14, 0x46cf, 0xcc14, 0x21, 0 - .dw 0x46d1, 0xcc14, 0x46d1, 0xcc14, 0x21, 0 - .dw 0x46d3, 0xcc14, 0x46ff, 0xcc14, 0x21, 0 - .dw 0x4701, 0xcc14, 0x4701, 0xcc14, 0x21, 0 - .dw 0x4703, 0xcc14, 0x470f, 0xcc14, 0x21, 0 - .dw 0x4711, 0xcc14, 0x4711, 0xcc14, 0x21, 0 - .dw 0x4713, 0xcc14, 0x473f, 0xcc14, 0x21, 0 - .dw 0x4741, 0xcc14, 0x4741, 0xcc14, 0x21, 0 - .dw 0x4743, 0xcc14, 0x474f, 0xcc14, 0x21, 0 - .dw 0x4751, 0xcc14, 0x4751, 0xcc14, 0x21, 0 - .dw 0x4753, 0xcc14, 0x477f, 0xcc14, 0x21, 0 - .dw 0x4781, 0xcc14, 0x4781, 0xcc14, 0x21, 0 - .dw 0x4783, 0xcc14, 0x478f, 0xcc14, 0x21, 0 - .dw 0x4791, 0xcc14, 0x4791, 0xcc14, 0x21, 0 - .dw 0x4793, 0xcc14, 0x47bf, 0xcc14, 0x21, 0 - .dw 0x47c1, 0xcc14, 0x47c1, 0xcc14, 0x21, 0 - .dw 0x47c3, 0xcc14, 0x47cf, 0xcc14, 0x21, 0 - .dw 0x47d1, 0xcc14, 0x47d1, 0xcc14, 0x21, 0 - .dw 0x47d3, 0xcc14, 0x47ff, 0xcc14, 0x21, 0 - .dw 0x4801, 0xcc14, 0x4801, 0xcc14, 0x21, 0 - .dw 0x4803, 0xcc14, 0x480f, 0xcc14, 0x21, 0 - .dw 0x4811, 0xcc14, 0x4811, 0xcc14, 0x21, 0 - .dw 0x4813, 0xcc14, 0x483f, 0xcc14, 0x21, 0 - .dw 0x4841, 0xcc14, 0x4841, 0xcc14, 0x21, 0 - .dw 0x4843, 0xcc14, 0x484f, 0xcc14, 0x21, 0 - .dw 0x4851, 0xcc14, 0x4851, 0xcc14, 0x21, 0 - .dw 0x4853, 0xcc14, 0x487f, 0xcc14, 0x21, 0 - .dw 0x4881, 0xcc14, 0x4881, 0xcc14, 0x21, 0 - .dw 0x4883, 0xcc14, 0x488f, 0xcc14, 0x21, 0 - .dw 0x4891, 0xcc14, 0x4891, 0xcc14, 0x21, 0 - .dw 0x4893, 0xcc14, 0x48bf, 0xcc14, 0x21, 0 - .dw 0x48c1, 0xcc14, 0x48c1, 0xcc14, 0x21, 0 - .dw 0x48c3, 0xcc14, 0x48cf, 0xcc14, 0x21, 0 - .dw 0x48d1, 0xcc14, 0x48d1, 0xcc14, 0x21, 0 - .dw 0x48d3, 0xcc14, 0x48ff, 0xcc14, 0x21, 0 - .dw 0x4901, 0xcc14, 0x4901, 0xcc14, 0x21, 0 - .dw 0x4903, 0xcc14, 0x490f, 0xcc14, 0x21, 0 - .dw 0x4911, 0xcc14, 0x4911, 0xcc14, 0x21, 0 - .dw 0x4913, 0xcc14, 0x493f, 0xcc14, 0x21, 0 - .dw 0x4941, 0xcc14, 0x4941, 0xcc14, 0x21, 0 - .dw 0x4943, 0xcc14, 0x494f, 0xcc14, 0x21, 0 - .dw 0x4951, 0xcc14, 0x4951, 0xcc14, 0x21, 0 - .dw 0x4953, 0xcc14, 0x497f, 0xcc14, 0x21, 0 - .dw 0x4981, 0xcc14, 0x4981, 0xcc14, 0x21, 0 - .dw 0x4983, 0xcc14, 0x498f, 0xcc14, 0x21, 0 - .dw 0x4991, 0xcc14, 0x4991, 0xcc14, 0x21, 0 - .dw 0x4993, 0xcc14, 0x49bf, 0xcc14, 0x21, 0 - .dw 0x49c1, 0xcc14, 0x49c1, 0xcc14, 0x21, 0 - .dw 0x49c3, 0xcc14, 0x49cf, 0xcc14, 0x21, 0 - .dw 0x49d1, 0xcc14, 0x49d1, 0xcc14, 0x21, 0 - .dw 0x49d3, 0xcc14, 0x49ff, 0xcc14, 0x21, 0 - .dw 0x4a01, 0xcc14, 0x4a01, 0xcc14, 0x21, 0 - .dw 0x4a03, 0xcc14, 0x4a0f, 0xcc14, 0x21, 0 - .dw 0x4a11, 0xcc14, 0x4a11, 0xcc14, 0x21, 0 - .dw 0x4a13, 0xcc14, 0x4a3f, 0xcc14, 0x21, 0 - .dw 0x4a41, 0xcc14, 0x4a41, 0xcc14, 0x21, 0 - .dw 0x4a43, 0xcc14, 0x4a4f, 0xcc14, 0x21, 0 - .dw 0x4a51, 0xcc14, 0x4a51, 0xcc14, 0x21, 0 - .dw 0x4a53, 0xcc14, 0x4a7f, 0xcc14, 0x21, 0 - .dw 0x4a81, 0xcc14, 0x4a81, 0xcc14, 0x21, 0 - .dw 0x4a83, 0xcc14, 0x4a8f, 0xcc14, 0x21, 0 - .dw 0x4a91, 0xcc14, 0x4a91, 0xcc14, 0x21, 0 - .dw 0x4a93, 0xcc14, 0x4abf, 0xcc14, 0x21, 0 - .dw 0x4ac1, 0xcc14, 0x4ac1, 0xcc14, 0x21, 0 - .dw 0x4ac3, 0xcc14, 0x4acf, 0xcc14, 0x21, 0 - .dw 0x4ad1, 0xcc14, 0x4ad1, 0xcc14, 0x21, 0 - .dw 0x4ad3, 0xcc14, 0x4aff, 0xcc14, 0x21, 0 - .dw 0x4b01, 0xcc14, 0x4b01, 0xcc14, 0x21, 0 - .dw 0x4b03, 0xcc14, 0x4b0f, 0xcc14, 0x21, 0 - .dw 0x4b11, 0xcc14, 0x4b11, 0xcc14, 0x21, 0 - .dw 0x4b13, 0xcc14, 0x4b3f, 0xcc14, 0x21, 0 - .dw 0x4b41, 0xcc14, 0x4b41, 0xcc14, 0x21, 0 - .dw 0x4b43, 0xcc14, 0x4b4f, 0xcc14, 0x21, 0 - .dw 0x4b51, 0xcc14, 0x4b51, 0xcc14, 0x21, 0 - .dw 0x4b53, 0xcc14, 0x4b7f, 0xcc14, 0x21, 0 - .dw 0x4b81, 0xcc14, 0x4b81, 0xcc14, 0x21, 0 - .dw 0x4b83, 0xcc14, 0x4b8f, 0xcc14, 0x21, 0 - .dw 0x4b91, 0xcc14, 0x4b91, 0xcc14, 0x21, 0 - .dw 0x4b93, 0xcc14, 0x4bbf, 0xcc14, 0x21, 0 - .dw 0x4bc1, 0xcc14, 0x4bc1, 0xcc14, 0x21, 0 - .dw 0x4bc3, 0xcc14, 0x4bcf, 0xcc14, 0x21, 0 - .dw 0x4bd1, 0xcc14, 0x4bd1, 0xcc14, 0x21, 0 - .dw 0x4bd3, 0xcc14, 0x4bff, 0xcc14, 0x21, 0 - .dw 0x4c01, 0xcc14, 0x4c01, 0xcc14, 0x21, 0 - .dw 0x4c03, 0xcc14, 0x4c0f, 0xcc14, 0x21, 0 - .dw 0x4c11, 0xcc14, 0x4c11, 0xcc14, 0x21, 0 - .dw 0x4c13, 0xcc14, 0x4c3f, 0xcc14, 0x21, 0 - .dw 0x4c41, 0xcc14, 0x4c41, 0xcc14, 0x21, 0 - .dw 0x4c43, 0xcc14, 0x4c4f, 0xcc14, 0x21, 0 - .dw 0x4c51, 0xcc14, 0x4c51, 0xcc14, 0x21, 0 - .dw 0x4c53, 0xcc14, 0x4c7f, 0xcc14, 0x21, 0 - .dw 0x4c81, 0xcc14, 0x4c81, 0xcc14, 0x21, 0 - .dw 0x4c83, 0xcc14, 0x4c8f, 0xcc14, 0x21, 0 - .dw 0x4c91, 0xcc14, 0x4c91, 0xcc14, 0x21, 0 - .dw 0x4c93, 0xcc14, 0x4cbf, 0xcc14, 0x21, 0 - .dw 0x4cc1, 0xcc14, 0x4cc1, 0xcc14, 0x21, 0 - .dw 0x4cc3, 0xcc14, 0x4ccf, 0xcc14, 0x21, 0 - .dw 0x4cd1, 0xcc14, 0x4cd1, 0xcc14, 0x21, 0 - .dw 0x4cd3, 0xcc14, 0x4cff, 0xcc14, 0x21, 0 - .dw 0x4d01, 0xcc14, 0x4d01, 0xcc14, 0x21, 0 - .dw 0x4d03, 0xcc14, 0x4d0f, 0xcc14, 0x21, 0 - .dw 0x4d11, 0xcc14, 0x4d11, 0xcc14, 0x21, 0 - .dw 0x4d13, 0xcc14, 0x4d3f, 0xcc14, 0x21, 0 - .dw 0x4d41, 0xcc14, 0x4d41, 0xcc14, 0x21, 0 - .dw 0x4d43, 0xcc14, 0x4d4f, 0xcc14, 0x21, 0 - .dw 0x4d51, 0xcc14, 0x4d51, 0xcc14, 0x21, 0 - .dw 0x4d53, 0xcc14, 0x4d7f, 0xcc14, 0x21, 0 - .dw 0x4d81, 0xcc14, 0x4d81, 0xcc14, 0x21, 0 - .dw 0x4d83, 0xcc14, 0x4d8f, 0xcc14, 0x21, 0 - .dw 0x4d91, 0xcc14, 0x4d91, 0xcc14, 0x21, 0 - .dw 0x4d93, 0xcc14, 0x4dbf, 0xcc14, 0x21, 0 - .dw 0x4dc1, 0xcc14, 0x4dc1, 0xcc14, 0x21, 0 - .dw 0x4dc3, 0xcc14, 0x4dcf, 0xcc14, 0x21, 0 - .dw 0x4dd1, 0xcc14, 0x4dd1, 0xcc14, 0x21, 0 - .dw 0x4dd3, 0xcc14, 0x4dff, 0xcc14, 0x21, 0 - .dw 0x4e01, 0xcc14, 0x4e01, 0xcc14, 0x21, 0 - .dw 0x4e03, 0xcc14, 0x4e0f, 0xcc14, 0x21, 0 - .dw 0x4e11, 0xcc14, 0x4e11, 0xcc14, 0x21, 0 - .dw 0x4e13, 0xcc14, 0x4e3f, 0xcc14, 0x21, 0 - .dw 0x4e41, 0xcc14, 0x4e41, 0xcc14, 0x21, 0 - .dw 0x4e43, 0xcc14, 0x4e4f, 0xcc14, 0x21, 0 - .dw 0x4e51, 0xcc14, 0x4e51, 0xcc14, 0x21, 0 - .dw 0x4e53, 0xcc14, 0x4e7f, 0xcc14, 0x21, 0 - .dw 0x4e81, 0xcc14, 0x4e81, 0xcc14, 0x21, 0 - .dw 0x4e83, 0xcc14, 0x4e8f, 0xcc14, 0x21, 0 - .dw 0x4e91, 0xcc14, 0x4e91, 0xcc14, 0x21, 0 - .dw 0x4e93, 0xcc14, 0x4ebf, 0xcc14, 0x21, 0 - .dw 0x4ec1, 0xcc14, 0x4ec1, 0xcc14, 0x21, 0 - .dw 0x4ec3, 0xcc14, 0x4ecf, 0xcc14, 0x21, 0 - .dw 0x4ed1, 0xcc14, 0x4ed1, 0xcc14, 0x21, 0 - .dw 0x4ed3, 0xcc14, 0x4eff, 0xcc14, 0x21, 0 - .dw 0x4f01, 0xcc14, 0x4f01, 0xcc14, 0x21, 0 - .dw 0x4f03, 0xcc14, 0x4f0f, 0xcc14, 0x21, 0 - .dw 0x4f11, 0xcc14, 0x4f11, 0xcc14, 0x21, 0 - .dw 0x4f13, 0xcc14, 0x4f3f, 0xcc14, 0x21, 0 - .dw 0x4f41, 0xcc14, 0x4f41, 0xcc14, 0x21, 0 - .dw 0x4f43, 0xcc14, 0x4f4f, 0xcc14, 0x21, 0 - .dw 0x4f51, 0xcc14, 0x4f51, 0xcc14, 0x21, 0 - .dw 0x4f53, 0xcc14, 0x4f7f, 0xcc14, 0x21, 0 - .dw 0x4f81, 0xcc14, 0x4f81, 0xcc14, 0x21, 0 - .dw 0x4f83, 0xcc14, 0x4f8f, 0xcc14, 0x21, 0 - .dw 0x4f91, 0xcc14, 0x4f91, 0xcc14, 0x21, 0 - .dw 0x4f93, 0xcc14, 0x4fbf, 0xcc14, 0x21, 0 - .dw 0x4fc1, 0xcc14, 0x4fc1, 0xcc14, 0x21, 0 - .dw 0x4fc3, 0xcc14, 0x4fcf, 0xcc14, 0x21, 0 - .dw 0x4fd1, 0xcc14, 0x4fd1, 0xcc14, 0x21, 0 - .dw 0x4fd3, 0xcc14, 0x5fff, 0xcc14, 0x21, 0 - .dw 0x6001, 0xcc14, 0x6001, 0xcc14, 0x21, 0 - .dw 0x6003, 0xcc14, 0x600f, 0xcc14, 0x21, 0 - .dw 0x6011, 0xcc14, 0x6011, 0xcc14, 0x21, 0 - .dw 0x6013, 0xcc14, 0x603f, 0xcc14, 0x21, 0 - .dw 0x6041, 0xcc14, 0x6041, 0xcc14, 0x21, 0 - .dw 0x6043, 0xcc14, 0x604f, 0xcc14, 0x21, 0 - .dw 0x6051, 0xcc14, 0x6051, 0xcc14, 0x21, 0 - .dw 0x6053, 0xcc14, 0x607f, 0xcc14, 0x21, 0 - .dw 0x6081, 0xcc14, 0x6081, 0xcc14, 0x21, 0 - .dw 0x6083, 0xcc14, 0x608f, 0xcc14, 0x21, 0 - .dw 0x6091, 0xcc14, 0x6091, 0xcc14, 0x21, 0 - .dw 0x6093, 0xcc14, 0x60bf, 0xcc14, 0x21, 0 - .dw 0x60c1, 0xcc14, 0x60c1, 0xcc14, 0x21, 0 - .dw 0x60c3, 0xcc14, 0x60cf, 0xcc14, 0x21, 0 - .dw 0x60d1, 0xcc14, 0x60d1, 0xcc14, 0x21, 0 - .dw 0x60d3, 0xcc14, 0x60ff, 0xcc14, 0x21, 0 - .dw 0x6101, 0xcc14, 0x6101, 0xcc14, 0x21, 0 - .dw 0x6103, 0xcc14, 0x610f, 0xcc14, 0x21, 0 - .dw 0x6111, 0xcc14, 0x6111, 0xcc14, 0x21, 0 - .dw 0x6113, 0xcc14, 0x613f, 0xcc14, 0x21, 0 - .dw 0x6141, 0xcc14, 0x6141, 0xcc14, 0x21, 0 - .dw 0x6143, 0xcc14, 0x614f, 0xcc14, 0x21, 0 - .dw 0x6151, 0xcc14, 0x6151, 0xcc14, 0x21, 0 - .dw 0x6153, 0xcc14, 0x617f, 0xcc14, 0x21, 0 - .dw 0x6181, 0xcc14, 0x6181, 0xcc14, 0x21, 0 - .dw 0x6183, 0xcc14, 0x618f, 0xcc14, 0x21, 0 - .dw 0x6191, 0xcc14, 0x6191, 0xcc14, 0x21, 0 - .dw 0x6193, 0xcc14, 0x61bf, 0xcc14, 0x21, 0 - .dw 0x61c1, 0xcc14, 0x61c1, 0xcc14, 0x21, 0 - .dw 0x61c3, 0xcc14, 0x61cf, 0xcc14, 0x21, 0 - .dw 0x61d1, 0xcc14, 0x61d1, 0xcc14, 0x21, 0 - .dw 0x61d3, 0xcc14, 0x61ff, 0xcc14, 0x21, 0 - .dw 0x6201, 0xcc14, 0x6201, 0xcc14, 0x21, 0 - .dw 0x6203, 0xcc14, 0x620f, 0xcc14, 0x21, 0 - .dw 0x6211, 0xcc14, 0x6211, 0xcc14, 0x21, 0 - .dw 0x6213, 0xcc14, 0x623f, 0xcc14, 0x21, 0 - .dw 0x6241, 0xcc14, 0x6241, 0xcc14, 0x21, 0 - .dw 0x6243, 0xcc14, 0x624f, 0xcc14, 0x21, 0 - .dw 0x6251, 0xcc14, 0x6251, 0xcc14, 0x21, 0 - .dw 0x6253, 0xcc14, 0x627f, 0xcc14, 0x21, 0 - .dw 0x6281, 0xcc14, 0x6281, 0xcc14, 0x21, 0 - .dw 0x6283, 0xcc14, 0x628f, 0xcc14, 0x21, 0 - .dw 0x6291, 0xcc14, 0x6291, 0xcc14, 0x21, 0 - .dw 0x6293, 0xcc14, 0x62bf, 0xcc14, 0x21, 0 - .dw 0x62c1, 0xcc14, 0x62c1, 0xcc14, 0x21, 0 - .dw 0x62c3, 0xcc14, 0x62cf, 0xcc14, 0x21, 0 - .dw 0x62d1, 0xcc14, 0x62d1, 0xcc14, 0x21, 0 - .dw 0x62d3, 0xcc14, 0x62ff, 0xcc14, 0x21, 0 - .dw 0x6301, 0xcc14, 0x6301, 0xcc14, 0x21, 0 - .dw 0x6303, 0xcc14, 0x630f, 0xcc14, 0x21, 0 - .dw 0x6311, 0xcc14, 0x6311, 0xcc14, 0x21, 0 - .dw 0x6313, 0xcc14, 0x633f, 0xcc14, 0x21, 0 - .dw 0x6341, 0xcc14, 0x6341, 0xcc14, 0x21, 0 - .dw 0x6343, 0xcc14, 0x634f, 0xcc14, 0x21, 0 - .dw 0x6351, 0xcc14, 0x6351, 0xcc14, 0x21, 0 - .dw 0x6353, 0xcc14, 0x637f, 0xcc14, 0x21, 0 - .dw 0x6381, 0xcc14, 0x6381, 0xcc14, 0x21, 0 - .dw 0x6383, 0xcc14, 0x638f, 0xcc14, 0x21, 0 - .dw 0x6391, 0xcc14, 0x6391, 0xcc14, 0x21, 0 - .dw 0x6393, 0xcc14, 0x63bf, 0xcc14, 0x21, 0 - .dw 0x63c1, 0xcc14, 0x63c1, 0xcc14, 0x21, 0 - .dw 0x63c3, 0xcc14, 0x63cf, 0xcc14, 0x21, 0 - .dw 0x63d1, 0xcc14, 0x63d1, 0xcc14, 0x21, 0 - .dw 0x63d3, 0xcc14, 0x63ff, 0xcc14, 0x21, 0 - .dw 0x6401, 0xcc14, 0x6401, 0xcc14, 0x21, 0 - .dw 0x6403, 0xcc14, 0x640f, 0xcc14, 0x21, 0 - .dw 0x6411, 0xcc14, 0x6411, 0xcc14, 0x21, 0 - .dw 0x6413, 0xcc14, 0x643f, 0xcc14, 0x21, 0 - .dw 0x6441, 0xcc14, 0x6441, 0xcc14, 0x21, 0 - .dw 0x6443, 0xcc14, 0x644f, 0xcc14, 0x21, 0 - .dw 0x6451, 0xcc14, 0x6451, 0xcc14, 0x21, 0 - .dw 0x6453, 0xcc14, 0x647f, 0xcc14, 0x21, 0 - .dw 0x6481, 0xcc14, 0x6481, 0xcc14, 0x21, 0 - .dw 0x6483, 0xcc14, 0x648f, 0xcc14, 0x21, 0 - .dw 0x6491, 0xcc14, 0x6491, 0xcc14, 0x21, 0 - .dw 0x6493, 0xcc14, 0x64bf, 0xcc14, 0x21, 0 - .dw 0x64c1, 0xcc14, 0x64c1, 0xcc14, 0x21, 0 - .dw 0x64c3, 0xcc14, 0x64cf, 0xcc14, 0x21, 0 - .dw 0x64d1, 0xcc14, 0x64d1, 0xcc14, 0x21, 0 - .dw 0x64d3, 0xcc14, 0x64ff, 0xcc14, 0x21, 0 - .dw 0x6501, 0xcc14, 0x6501, 0xcc14, 0x21, 0 - .dw 0x6503, 0xcc14, 0x650f, 0xcc14, 0x21, 0 - .dw 0x6511, 0xcc14, 0x6511, 0xcc14, 0x21, 0 - .dw 0x6513, 0xcc14, 0x653f, 0xcc14, 0x21, 0 - .dw 0x6541, 0xcc14, 0x6541, 0xcc14, 0x21, 0 - .dw 0x6543, 0xcc14, 0x654f, 0xcc14, 0x21, 0 - .dw 0x6551, 0xcc14, 0x6551, 0xcc14, 0x21, 0 - .dw 0x6553, 0xcc14, 0x657f, 0xcc14, 0x21, 0 - .dw 0x6581, 0xcc14, 0x6581, 0xcc14, 0x21, 0 - .dw 0x6583, 0xcc14, 0x658f, 0xcc14, 0x21, 0 - .dw 0x6591, 0xcc14, 0x6591, 0xcc14, 0x21, 0 - .dw 0x6593, 0xcc14, 0x65bf, 0xcc14, 0x21, 0 - .dw 0x65c1, 0xcc14, 0x65c1, 0xcc14, 0x21, 0 - .dw 0x65c3, 0xcc14, 0x65cf, 0xcc14, 0x21, 0 - .dw 0x65d1, 0xcc14, 0x65d1, 0xcc14, 0x21, 0 - .dw 0x65d3, 0xcc14, 0x65ff, 0xcc14, 0x21, 0 - .dw 0x6601, 0xcc14, 0x6601, 0xcc14, 0x21, 0 - .dw 0x6603, 0xcc14, 0x660f, 0xcc14, 0x21, 0 - .dw 0x6611, 0xcc14, 0x6611, 0xcc14, 0x21, 0 - .dw 0x6613, 0xcc14, 0x663f, 0xcc14, 0x21, 0 - .dw 0x6641, 0xcc14, 0x6641, 0xcc14, 0x21, 0 - .dw 0x6643, 0xcc14, 0x664f, 0xcc14, 0x21, 0 - .dw 0x6651, 0xcc14, 0x6651, 0xcc14, 0x21, 0 - .dw 0x6653, 0xcc14, 0x667f, 0xcc14, 0x21, 0 - .dw 0x6681, 0xcc14, 0x6681, 0xcc14, 0x21, 0 - .dw 0x6683, 0xcc14, 0x668f, 0xcc14, 0x21, 0 - .dw 0x6691, 0xcc14, 0x6691, 0xcc14, 0x21, 0 - .dw 0x6693, 0xcc14, 0x66bf, 0xcc14, 0x21, 0 - .dw 0x66c1, 0xcc14, 0x66c1, 0xcc14, 0x21, 0 - .dw 0x66c3, 0xcc14, 0x66cf, 0xcc14, 0x21, 0 - .dw 0x66d1, 0xcc14, 0x66d1, 0xcc14, 0x21, 0 - .dw 0x66d3, 0xcc14, 0x66ff, 0xcc14, 0x21, 0 - .dw 0x6701, 0xcc14, 0x6701, 0xcc14, 0x21, 0 - .dw 0x6703, 0xcc14, 0x670f, 0xcc14, 0x21, 0 - .dw 0x6711, 0xcc14, 0x6711, 0xcc14, 0x21, 0 - .dw 0x6713, 0xcc14, 0x673f, 0xcc14, 0x21, 0 - .dw 0x6741, 0xcc14, 0x6741, 0xcc14, 0x21, 0 - .dw 0x6743, 0xcc14, 0x674f, 0xcc14, 0x21, 0 - .dw 0x6751, 0xcc14, 0x6751, 0xcc14, 0x21, 0 - .dw 0x6753, 0xcc14, 0x677f, 0xcc14, 0x21, 0 - .dw 0x6781, 0xcc14, 0x6781, 0xcc14, 0x21, 0 - .dw 0x6783, 0xcc14, 0x678f, 0xcc14, 0x21, 0 - .dw 0x6791, 0xcc14, 0x6791, 0xcc14, 0x21, 0 - .dw 0x6793, 0xcc14, 0x67bf, 0xcc14, 0x21, 0 - .dw 0x67c1, 0xcc14, 0x67c1, 0xcc14, 0x21, 0 - .dw 0x67c3, 0xcc14, 0x67cf, 0xcc14, 0x21, 0 - .dw 0x67d1, 0xcc14, 0x67d1, 0xcc14, 0x21, 0 - .dw 0x67d3, 0xcc14, 0x67ff, 0xcc14, 0x21, 0 - .dw 0x6801, 0xcc14, 0x6801, 0xcc14, 0x21, 0 - .dw 0x6803, 0xcc14, 0x680f, 0xcc14, 0x21, 0 - .dw 0x6811, 0xcc14, 0x6811, 0xcc14, 0x21, 0 - .dw 0x6813, 0xcc14, 0x683f, 0xcc14, 0x21, 0 - .dw 0x6841, 0xcc14, 0x6841, 0xcc14, 0x21, 0 - .dw 0x6843, 0xcc14, 0x684f, 0xcc14, 0x21, 0 - .dw 0x6851, 0xcc14, 0x6851, 0xcc14, 0x21, 0 - .dw 0x6853, 0xcc14, 0x687f, 0xcc14, 0x21, 0 - .dw 0x6881, 0xcc14, 0x6881, 0xcc14, 0x21, 0 - .dw 0x6883, 0xcc14, 0x688f, 0xcc14, 0x21, 0 - .dw 0x6891, 0xcc14, 0x6891, 0xcc14, 0x21, 0 - .dw 0x6893, 0xcc14, 0x68bf, 0xcc14, 0x21, 0 - .dw 0x68c1, 0xcc14, 0x68c1, 0xcc14, 0x21, 0 - .dw 0x68c3, 0xcc14, 0x68cf, 0xcc14, 0x21, 0 - .dw 0x68d1, 0xcc14, 0x68d1, 0xcc14, 0x21, 0 - .dw 0x68d3, 0xcc14, 0x68ff, 0xcc14, 0x21, 0 - .dw 0x6901, 0xcc14, 0x6901, 0xcc14, 0x21, 0 - .dw 0x6903, 0xcc14, 0x690f, 0xcc14, 0x21, 0 - .dw 0x6911, 0xcc14, 0x6911, 0xcc14, 0x21, 0 - .dw 0x6913, 0xcc14, 0x693f, 0xcc14, 0x21, 0 - .dw 0x6941, 0xcc14, 0x6941, 0xcc14, 0x21, 0 - .dw 0x6943, 0xcc14, 0x694f, 0xcc14, 0x21, 0 - .dw 0x6951, 0xcc14, 0x6951, 0xcc14, 0x21, 0 - .dw 0x6953, 0xcc14, 0x697f, 0xcc14, 0x21, 0 - .dw 0x6981, 0xcc14, 0x6981, 0xcc14, 0x21, 0 - .dw 0x6983, 0xcc14, 0x698f, 0xcc14, 0x21, 0 - .dw 0x6991, 0xcc14, 0x6991, 0xcc14, 0x21, 0 - .dw 0x6993, 0xcc14, 0x69bf, 0xcc14, 0x21, 0 - .dw 0x69c1, 0xcc14, 0x69c1, 0xcc14, 0x21, 0 - .dw 0x69c3, 0xcc14, 0x69cf, 0xcc14, 0x21, 0 - .dw 0x69d1, 0xcc14, 0x69d1, 0xcc14, 0x21, 0 - .dw 0x69d3, 0xcc14, 0x69ff, 0xcc14, 0x21, 0 - .dw 0x6a01, 0xcc14, 0x6a01, 0xcc14, 0x21, 0 - .dw 0x6a03, 0xcc14, 0x6a0f, 0xcc14, 0x21, 0 - .dw 0x6a11, 0xcc14, 0x6a11, 0xcc14, 0x21, 0 - .dw 0x6a13, 0xcc14, 0x6a3f, 0xcc14, 0x21, 0 - .dw 0x6a41, 0xcc14, 0x6a41, 0xcc14, 0x21, 0 - .dw 0x6a43, 0xcc14, 0x6a4f, 0xcc14, 0x21, 0 - .dw 0x6a51, 0xcc14, 0x6a51, 0xcc14, 0x21, 0 - .dw 0x6a53, 0xcc14, 0x6a7f, 0xcc14, 0x21, 0 - .dw 0x6a81, 0xcc14, 0x6a81, 0xcc14, 0x21, 0 - .dw 0x6a83, 0xcc14, 0x6a8f, 0xcc14, 0x21, 0 - .dw 0x6a91, 0xcc14, 0x6a91, 0xcc14, 0x21, 0 - .dw 0x6a93, 0xcc14, 0x6abf, 0xcc14, 0x21, 0 - .dw 0x6ac1, 0xcc14, 0x6ac1, 0xcc14, 0x21, 0 - .dw 0x6ac3, 0xcc14, 0x6acf, 0xcc14, 0x21, 0 - .dw 0x6ad1, 0xcc14, 0x6ad1, 0xcc14, 0x21, 0 - .dw 0x6ad3, 0xcc14, 0x6aff, 0xcc14, 0x21, 0 - .dw 0x6b01, 0xcc14, 0x6b01, 0xcc14, 0x21, 0 - .dw 0x6b03, 0xcc14, 0x6b0f, 0xcc14, 0x21, 0 - .dw 0x6b11, 0xcc14, 0x6b11, 0xcc14, 0x21, 0 - .dw 0x6b13, 0xcc14, 0x6b3f, 0xcc14, 0x21, 0 - .dw 0x6b41, 0xcc14, 0x6b41, 0xcc14, 0x21, 0 - .dw 0x6b43, 0xcc14, 0x6b4f, 0xcc14, 0x21, 0 - .dw 0x6b51, 0xcc14, 0x6b51, 0xcc14, 0x21, 0 - .dw 0x6b53, 0xcc14, 0x6b7f, 0xcc14, 0x21, 0 - .dw 0x6b81, 0xcc14, 0x6b81, 0xcc14, 0x21, 0 - .dw 0x6b83, 0xcc14, 0x6b8f, 0xcc14, 0x21, 0 - .dw 0x6b91, 0xcc14, 0x6b91, 0xcc14, 0x21, 0 - .dw 0x6b93, 0xcc14, 0x6bbf, 0xcc14, 0x21, 0 - .dw 0x6bc1, 0xcc14, 0x6bc1, 0xcc14, 0x21, 0 - .dw 0x6bc3, 0xcc14, 0x6bcf, 0xcc14, 0x21, 0 - .dw 0x6bd1, 0xcc14, 0x6bd1, 0xcc14, 0x21, 0 - .dw 0x6bd3, 0xcc14, 0x6bff, 0xcc14, 0x21, 0 - .dw 0x6c01, 0xcc14, 0x6c01, 0xcc14, 0x21, 0 - .dw 0x6c03, 0xcc14, 0x6c0f, 0xcc14, 0x21, 0 - .dw 0x6c11, 0xcc14, 0x6c11, 0xcc14, 0x21, 0 - .dw 0x6c13, 0xcc14, 0x6c3f, 0xcc14, 0x21, 0 - .dw 0x6c41, 0xcc14, 0x6c41, 0xcc14, 0x21, 0 - .dw 0x6c43, 0xcc14, 0x6c4f, 0xcc14, 0x21, 0 - .dw 0x6c51, 0xcc14, 0x6c51, 0xcc14, 0x21, 0 - .dw 0x6c53, 0xcc14, 0x6c7f, 0xcc14, 0x21, 0 - .dw 0x6c81, 0xcc14, 0x6c81, 0xcc14, 0x21, 0 - .dw 0x6c83, 0xcc14, 0x6c8f, 0xcc14, 0x21, 0 - .dw 0x6c91, 0xcc14, 0x6c91, 0xcc14, 0x21, 0 - .dw 0x6c93, 0xcc14, 0x6cbf, 0xcc14, 0x21, 0 - .dw 0x6cc1, 0xcc14, 0x6cc1, 0xcc14, 0x21, 0 - .dw 0x6cc3, 0xcc14, 0x6ccf, 0xcc14, 0x21, 0 - .dw 0x6cd1, 0xcc14, 0x6cd1, 0xcc14, 0x21, 0 - .dw 0x6cd3, 0xcc14, 0x6cff, 0xcc14, 0x21, 0 - .dw 0x6d01, 0xcc14, 0x6d01, 0xcc14, 0x21, 0 - .dw 0x6d03, 0xcc14, 0x6d0f, 0xcc14, 0x21, 0 - .dw 0x6d11, 0xcc14, 0x6d11, 0xcc14, 0x21, 0 - .dw 0x6d13, 0xcc14, 0x6d3f, 0xcc14, 0x21, 0 - .dw 0x6d41, 0xcc14, 0x6d41, 0xcc14, 0x21, 0 - .dw 0x6d43, 0xcc14, 0x6d4f, 0xcc14, 0x21, 0 - .dw 0x6d51, 0xcc14, 0x6d51, 0xcc14, 0x21, 0 - .dw 0x6d53, 0xcc14, 0x6d7f, 0xcc14, 0x21, 0 - .dw 0x6d81, 0xcc14, 0x6d81, 0xcc14, 0x21, 0 - .dw 0x6d83, 0xcc14, 0x6d8f, 0xcc14, 0x21, 0 - .dw 0x6d91, 0xcc14, 0x6d91, 0xcc14, 0x21, 0 - .dw 0x6d93, 0xcc14, 0x6dbf, 0xcc14, 0x21, 0 - .dw 0x6dc1, 0xcc14, 0x6dc1, 0xcc14, 0x21, 0 - .dw 0x6dc3, 0xcc14, 0x6dcf, 0xcc14, 0x21, 0 - .dw 0x6dd1, 0xcc14, 0x6dd1, 0xcc14, 0x21, 0 - .dw 0x6dd3, 0xcc14, 0x6dff, 0xcc14, 0x21, 0 - .dw 0x6e01, 0xcc14, 0x6e01, 0xcc14, 0x21, 0 - .dw 0x6e03, 0xcc14, 0x6e0f, 0xcc14, 0x21, 0 - .dw 0x6e11, 0xcc14, 0x6e11, 0xcc14, 0x21, 0 - .dw 0x6e13, 0xcc14, 0x6e3f, 0xcc14, 0x21, 0 - .dw 0x6e41, 0xcc14, 0x6e41, 0xcc14, 0x21, 0 - .dw 0x6e43, 0xcc14, 0x6e4f, 0xcc14, 0x21, 0 - .dw 0x6e51, 0xcc14, 0x6e51, 0xcc14, 0x21, 0 - .dw 0x6e53, 0xcc14, 0x6e7f, 0xcc14, 0x21, 0 - .dw 0x6e81, 0xcc14, 0x6e81, 0xcc14, 0x21, 0 - .dw 0x6e83, 0xcc14, 0x6e8f, 0xcc14, 0x21, 0 - .dw 0x6e91, 0xcc14, 0x6e91, 0xcc14, 0x21, 0 - .dw 0x6e93, 0xcc14, 0x6ebf, 0xcc14, 0x21, 0 - .dw 0x6ec1, 0xcc14, 0x6ec1, 0xcc14, 0x21, 0 - .dw 0x6ec3, 0xcc14, 0x6ecf, 0xcc14, 0x21, 0 - .dw 0x6ed1, 0xcc14, 0x6ed1, 0xcc14, 0x21, 0 - .dw 0x6ed3, 0xcc14, 0x6eff, 0xcc14, 0x21, 0 - .dw 0x6f01, 0xcc14, 0x6f01, 0xcc14, 0x21, 0 - .dw 0x6f03, 0xcc14, 0x6f0f, 0xcc14, 0x21, 0 - .dw 0x6f11, 0xcc14, 0x6f11, 0xcc14, 0x21, 0 - .dw 0x6f13, 0xcc14, 0x6f3f, 0xcc14, 0x21, 0 - .dw 0x6f41, 0xcc14, 0x6f41, 0xcc14, 0x21, 0 - .dw 0x6f43, 0xcc14, 0x6f4f, 0xcc14, 0x21, 0 - .dw 0x6f51, 0xcc14, 0x6f51, 0xcc14, 0x21, 0 - .dw 0x6f53, 0xcc14, 0x6f7f, 0xcc14, 0x21, 0 - .dw 0x6f81, 0xcc14, 0x6f81, 0xcc14, 0x21, 0 - .dw 0x6f83, 0xcc14, 0x6f8f, 0xcc14, 0x21, 0 - .dw 0x6f91, 0xcc14, 0x6f91, 0xcc14, 0x21, 0 - .dw 0x6f93, 0xcc14, 0x6fbf, 0xcc14, 0x21, 0 - .dw 0x6fc1, 0xcc14, 0x6fc1, 0xcc14, 0x21, 0 - .dw 0x6fc3, 0xcc14, 0x6fcf, 0xcc14, 0x21, 0 - .dw 0x6fd1, 0xcc14, 0x6fd1, 0xcc14, 0x21, 0 - .dw 0x6fd3, 0xcc14, 0xffff, 0xcc14, 0x21, 0 - .dw 0x0000, 0xcc15, 0x0000, 0xcc15, 0x22, 0 - .dw 0x0001, 0xcc15, 0x0001, 0xcc15, 0x21, 0 - .dw 0x0002, 0xcc15, 0x0002, 0xcc15, 0x22, 0 - .dw 0x0003, 0xcc15, 0x000f, 0xcc15, 0x21, 0 - .dw 0x0010, 0xcc15, 0x0010, 0xcc15, 0x22, 0 - .dw 0x0011, 0xcc15, 0x0011, 0xcc15, 0x21, 0 - .dw 0x0012, 0xcc15, 0x0012, 0xcc15, 0x22, 0 - .dw 0x0013, 0xcc15, 0x003f, 0xcc15, 0x21, 0 - .dw 0x0041, 0xcc15, 0x0041, 0xcc15, 0x21, 0 - .dw 0x0043, 0xcc15, 0x004f, 0xcc15, 0x21, 0 - .dw 0x0051, 0xcc15, 0x0051, 0xcc15, 0x21, 0 - .dw 0x0053, 0xcc15, 0x007f, 0xcc15, 0x21, 0 - .dw 0x0081, 0xcc15, 0x0081, 0xcc15, 0x21, 0 - .dw 0x0083, 0xcc15, 0x008f, 0xcc15, 0x21, 0 - .dw 0x0091, 0xcc15, 0x0091, 0xcc15, 0x21, 0 - .dw 0x0093, 0xcc15, 0x00bf, 0xcc15, 0x21, 0 - .dw 0x00c1, 0xcc15, 0x00c1, 0xcc15, 0x21, 0 - .dw 0x00c3, 0xcc15, 0x00cf, 0xcc15, 0x21, 0 - .dw 0x00d1, 0xcc15, 0x00d1, 0xcc15, 0x21, 0 - .dw 0x00d3, 0xcc15, 0x00ff, 0xcc15, 0x21, 0 - .dw 0x0101, 0xcc15, 0x0101, 0xcc15, 0x21, 0 - .dw 0x0103, 0xcc15, 0x010f, 0xcc15, 0x21, 0 - .dw 0x0111, 0xcc15, 0x0111, 0xcc15, 0x21, 0 - .dw 0x0113, 0xcc15, 0x013f, 0xcc15, 0x21, 0 - .dw 0x0141, 0xcc15, 0x0141, 0xcc15, 0x21, 0 - .dw 0x0143, 0xcc15, 0x014f, 0xcc15, 0x21, 0 - .dw 0x0151, 0xcc15, 0x0151, 0xcc15, 0x21, 0 - .dw 0x0153, 0xcc15, 0x017f, 0xcc15, 0x21, 0 - .dw 0x0181, 0xcc15, 0x0181, 0xcc15, 0x21, 0 - .dw 0x0183, 0xcc15, 0x018f, 0xcc15, 0x21, 0 - .dw 0x0191, 0xcc15, 0x0191, 0xcc15, 0x21, 0 - .dw 0x0193, 0xcc15, 0x01bf, 0xcc15, 0x21, 0 - .dw 0x01c1, 0xcc15, 0x01c1, 0xcc15, 0x21, 0 - .dw 0x01c3, 0xcc15, 0x01cf, 0xcc15, 0x21, 0 - .dw 0x01d1, 0xcc15, 0x01d1, 0xcc15, 0x21, 0 - .dw 0x01d3, 0xcc15, 0x01ff, 0xcc15, 0x21, 0 - .dw 0x0201, 0xcc15, 0x0201, 0xcc15, 0x21, 0 - .dw 0x0203, 0xcc15, 0x020f, 0xcc15, 0x21, 0 - .dw 0x0211, 0xcc15, 0x0211, 0xcc15, 0x21, 0 - .dw 0x0213, 0xcc15, 0x023f, 0xcc15, 0x21, 0 - .dw 0x0240, 0xcc15, 0x0240, 0xcc15, 0x22, 0 - .dw 0x0241, 0xcc15, 0x0241, 0xcc15, 0x21, 0 - .dw 0x0242, 0xcc15, 0x0242, 0xcc15, 0x22, 0 - .dw 0x0243, 0xcc15, 0x024f, 0xcc15, 0x21, 0 - .dw 0x0250, 0xcc15, 0x0250, 0xcc15, 0x22, 0 - .dw 0x0251, 0xcc15, 0x0251, 0xcc15, 0x21, 0 - .dw 0x0252, 0xcc15, 0x0252, 0xcc15, 0x22, 0 - .dw 0x0253, 0xcc15, 0x027f, 0xcc15, 0x21, 0 - .dw 0x0281, 0xcc15, 0x0281, 0xcc15, 0x21, 0 - .dw 0x0283, 0xcc15, 0x028f, 0xcc15, 0x21, 0 - .dw 0x0291, 0xcc15, 0x0291, 0xcc15, 0x21, 0 - .dw 0x0293, 0xcc15, 0x02bf, 0xcc15, 0x21, 0 - .dw 0x02c1, 0xcc15, 0x02c1, 0xcc15, 0x21, 0 - .dw 0x02c3, 0xcc15, 0x02cf, 0xcc15, 0x21, 0 - .dw 0x02d1, 0xcc15, 0x02d1, 0xcc15, 0x21, 0 - .dw 0x02d3, 0xcc15, 0x02ff, 0xcc15, 0x21, 0 - .dw 0x0301, 0xcc15, 0x0301, 0xcc15, 0x21, 0 - .dw 0x0303, 0xcc15, 0x030f, 0xcc15, 0x21, 0 - .dw 0x0311, 0xcc15, 0x0311, 0xcc15, 0x21, 0 - .dw 0x0313, 0xcc15, 0x033f, 0xcc15, 0x21, 0 - .dw 0x0341, 0xcc15, 0x0341, 0xcc15, 0x21, 0 - .dw 0x0343, 0xcc15, 0x034f, 0xcc15, 0x21, 0 - .dw 0x0351, 0xcc15, 0x0351, 0xcc15, 0x21, 0 - .dw 0x0353, 0xcc15, 0x037f, 0xcc15, 0x21, 0 - .dw 0x0381, 0xcc15, 0x0381, 0xcc15, 0x21, 0 - .dw 0x0383, 0xcc15, 0x038f, 0xcc15, 0x21, 0 - .dw 0x0391, 0xcc15, 0x0391, 0xcc15, 0x21, 0 - .dw 0x0393, 0xcc15, 0x03bf, 0xcc15, 0x21, 0 - .dw 0x03c1, 0xcc15, 0x03c1, 0xcc15, 0x21, 0 - .dw 0x03c3, 0xcc15, 0x03cf, 0xcc15, 0x21, 0 - .dw 0x03d1, 0xcc15, 0x03d1, 0xcc15, 0x21, 0 - .dw 0x03d3, 0xcc15, 0x03ff, 0xcc15, 0x21, 0 - .dw 0x0401, 0xcc15, 0x0401, 0xcc15, 0x21, 0 - .dw 0x0403, 0xcc15, 0x040f, 0xcc15, 0x21, 0 - .dw 0x0411, 0xcc15, 0x0411, 0xcc15, 0x21, 0 - .dw 0x0413, 0xcc15, 0x043f, 0xcc15, 0x21, 0 - .dw 0x0441, 0xcc15, 0x0441, 0xcc15, 0x21, 0 - .dw 0x0443, 0xcc15, 0x044f, 0xcc15, 0x21, 0 - .dw 0x0451, 0xcc15, 0x0451, 0xcc15, 0x21, 0 - .dw 0x0453, 0xcc15, 0x047f, 0xcc15, 0x21, 0 - .dw 0x0480, 0xcc15, 0x0480, 0xcc15, 0x22, 0 - .dw 0x0481, 0xcc15, 0x0481, 0xcc15, 0x21, 0 - .dw 0x0482, 0xcc15, 0x0482, 0xcc15, 0x22, 0 - .dw 0x0483, 0xcc15, 0x048f, 0xcc15, 0x21, 0 - .dw 0x0490, 0xcc15, 0x0490, 0xcc15, 0x22, 0 - .dw 0x0491, 0xcc15, 0x0491, 0xcc15, 0x21, 0 - .dw 0x0492, 0xcc15, 0x0492, 0xcc15, 0x22, 0 - .dw 0x0493, 0xcc15, 0x04bf, 0xcc15, 0x21, 0 - .dw 0x04c1, 0xcc15, 0x04c1, 0xcc15, 0x21, 0 - .dw 0x04c3, 0xcc15, 0x04cf, 0xcc15, 0x21, 0 - .dw 0x04d1, 0xcc15, 0x04d1, 0xcc15, 0x21, 0 - .dw 0x04d3, 0xcc15, 0x04ff, 0xcc15, 0x21, 0 - .dw 0x0501, 0xcc15, 0x0501, 0xcc15, 0x21, 0 - .dw 0x0503, 0xcc15, 0x050f, 0xcc15, 0x21, 0 - .dw 0x0511, 0xcc15, 0x0511, 0xcc15, 0x21, 0 - .dw 0x0513, 0xcc15, 0x053f, 0xcc15, 0x21, 0 - .dw 0x0541, 0xcc15, 0x0541, 0xcc15, 0x21, 0 - .dw 0x0543, 0xcc15, 0x054f, 0xcc15, 0x21, 0 - .dw 0x0551, 0xcc15, 0x0551, 0xcc15, 0x21, 0 - .dw 0x0553, 0xcc15, 0x057f, 0xcc15, 0x21, 0 - .dw 0x0581, 0xcc15, 0x0581, 0xcc15, 0x21, 0 - .dw 0x0583, 0xcc15, 0x058f, 0xcc15, 0x21, 0 - .dw 0x0591, 0xcc15, 0x0591, 0xcc15, 0x21, 0 - .dw 0x0593, 0xcc15, 0x05bf, 0xcc15, 0x21, 0 - .dw 0x05c1, 0xcc15, 0x05c1, 0xcc15, 0x21, 0 - .dw 0x05c3, 0xcc15, 0x05cf, 0xcc15, 0x21, 0 - .dw 0x05d1, 0xcc15, 0x05d1, 0xcc15, 0x21, 0 - .dw 0x05d3, 0xcc15, 0x05ff, 0xcc15, 0x21, 0 - .dw 0x0601, 0xcc15, 0x0601, 0xcc15, 0x21, 0 - .dw 0x0603, 0xcc15, 0x060f, 0xcc15, 0x21, 0 - .dw 0x0611, 0xcc15, 0x0611, 0xcc15, 0x21, 0 - .dw 0x0613, 0xcc15, 0x063f, 0xcc15, 0x21, 0 - .dw 0x0641, 0xcc15, 0x0641, 0xcc15, 0x21, 0 - .dw 0x0643, 0xcc15, 0x064f, 0xcc15, 0x21, 0 - .dw 0x0651, 0xcc15, 0x0651, 0xcc15, 0x21, 0 - .dw 0x0653, 0xcc15, 0x067f, 0xcc15, 0x21, 0 - .dw 0x0681, 0xcc15, 0x0681, 0xcc15, 0x21, 0 - .dw 0x0683, 0xcc15, 0x068f, 0xcc15, 0x21, 0 - .dw 0x0691, 0xcc15, 0x0691, 0xcc15, 0x21, 0 - .dw 0x0693, 0xcc15, 0x06bf, 0xcc15, 0x21, 0 - .dw 0x06c0, 0xcc15, 0x06c0, 0xcc15, 0x22, 0 - .dw 0x06c1, 0xcc15, 0x06c1, 0xcc15, 0x21, 0 - .dw 0x06c2, 0xcc15, 0x06c2, 0xcc15, 0x22, 0 - .dw 0x06c3, 0xcc15, 0x06cf, 0xcc15, 0x21, 0 - .dw 0x06d0, 0xcc15, 0x06d0, 0xcc15, 0x22, 0 - .dw 0x06d1, 0xcc15, 0x06d1, 0xcc15, 0x21, 0 - .dw 0x06d2, 0xcc15, 0x06d2, 0xcc15, 0x22, 0 - .dw 0x06d3, 0xcc15, 0x06ff, 0xcc15, 0x21, 0 - .dw 0x0701, 0xcc15, 0x0701, 0xcc15, 0x21, 0 - .dw 0x0703, 0xcc15, 0x070f, 0xcc15, 0x21, 0 - .dw 0x0711, 0xcc15, 0x0711, 0xcc15, 0x21, 0 - .dw 0x0713, 0xcc15, 0x073f, 0xcc15, 0x21, 0 - .dw 0x0741, 0xcc15, 0x0741, 0xcc15, 0x21, 0 - .dw 0x0743, 0xcc15, 0x074f, 0xcc15, 0x21, 0 - .dw 0x0751, 0xcc15, 0x0751, 0xcc15, 0x21, 0 - .dw 0x0753, 0xcc15, 0x077f, 0xcc15, 0x21, 0 - .dw 0x0781, 0xcc15, 0x0781, 0xcc15, 0x21, 0 - .dw 0x0783, 0xcc15, 0x078f, 0xcc15, 0x21, 0 - .dw 0x0791, 0xcc15, 0x0791, 0xcc15, 0x21, 0 - .dw 0x0793, 0xcc15, 0x07bf, 0xcc15, 0x21, 0 - .dw 0x07c1, 0xcc15, 0x07c1, 0xcc15, 0x21, 0 - .dw 0x07c3, 0xcc15, 0x07cf, 0xcc15, 0x21, 0 - .dw 0x07d1, 0xcc15, 0x07d1, 0xcc15, 0x21, 0 - .dw 0x07d3, 0xcc15, 0x07ff, 0xcc15, 0x21, 0 - .dw 0x0801, 0xcc15, 0x0801, 0xcc15, 0x21, 0 - .dw 0x0803, 0xcc15, 0x080f, 0xcc15, 0x21, 0 - .dw 0x0811, 0xcc15, 0x0811, 0xcc15, 0x21, 0 - .dw 0x0813, 0xcc15, 0x083f, 0xcc15, 0x21, 0 - .dw 0x0841, 0xcc15, 0x0841, 0xcc15, 0x21, 0 - .dw 0x0843, 0xcc15, 0x084f, 0xcc15, 0x21, 0 - .dw 0x0851, 0xcc15, 0x0851, 0xcc15, 0x21, 0 - .dw 0x0853, 0xcc15, 0x087f, 0xcc15, 0x21, 0 - .dw 0x0881, 0xcc15, 0x0881, 0xcc15, 0x21, 0 - .dw 0x0883, 0xcc15, 0x088f, 0xcc15, 0x21, 0 - .dw 0x0891, 0xcc15, 0x0891, 0xcc15, 0x21, 0 - .dw 0x0893, 0xcc15, 0x08bf, 0xcc15, 0x21, 0 - .dw 0x08c1, 0xcc15, 0x08c1, 0xcc15, 0x21, 0 - .dw 0x08c3, 0xcc15, 0x08cf, 0xcc15, 0x21, 0 - .dw 0x08d1, 0xcc15, 0x08d1, 0xcc15, 0x21, 0 - .dw 0x08d3, 0xcc15, 0x08ff, 0xcc15, 0x21, 0 - .dw 0x0900, 0xcc15, 0x0900, 0xcc15, 0x22, 0 - .dw 0x0901, 0xcc15, 0x0901, 0xcc15, 0x21, 0 - .dw 0x0902, 0xcc15, 0x0902, 0xcc15, 0x22, 0 - .dw 0x0903, 0xcc15, 0x090f, 0xcc15, 0x21, 0 - .dw 0x0910, 0xcc15, 0x0910, 0xcc15, 0x22, 0 - .dw 0x0911, 0xcc15, 0x0911, 0xcc15, 0x21, 0 - .dw 0x0912, 0xcc15, 0x0912, 0xcc15, 0x22, 0 - .dw 0x0913, 0xcc15, 0x093f, 0xcc15, 0x21, 0 - .dw 0x0941, 0xcc15, 0x0941, 0xcc15, 0x21, 0 - .dw 0x0943, 0xcc15, 0x094f, 0xcc15, 0x21, 0 - .dw 0x0951, 0xcc15, 0x0951, 0xcc15, 0x21, 0 - .dw 0x0953, 0xcc15, 0x097f, 0xcc15, 0x21, 0 - .dw 0x0981, 0xcc15, 0x0981, 0xcc15, 0x21, 0 - .dw 0x0983, 0xcc15, 0x098f, 0xcc15, 0x21, 0 - .dw 0x0991, 0xcc15, 0x0991, 0xcc15, 0x21, 0 - .dw 0x0993, 0xcc15, 0x09bf, 0xcc15, 0x21, 0 - .dw 0x09c1, 0xcc15, 0x09c1, 0xcc15, 0x21, 0 - .dw 0x09c3, 0xcc15, 0x09cf, 0xcc15, 0x21, 0 - .dw 0x09d1, 0xcc15, 0x09d1, 0xcc15, 0x21, 0 - .dw 0x09d3, 0xcc15, 0x09ff, 0xcc15, 0x21, 0 - .dw 0x0a01, 0xcc15, 0x0a01, 0xcc15, 0x21, 0 - .dw 0x0a03, 0xcc15, 0x0a0f, 0xcc15, 0x21, 0 - .dw 0x0a11, 0xcc15, 0x0a11, 0xcc15, 0x21, 0 - .dw 0x0a13, 0xcc15, 0x0a3f, 0xcc15, 0x21, 0 - .dw 0x0a41, 0xcc15, 0x0a41, 0xcc15, 0x21, 0 - .dw 0x0a43, 0xcc15, 0x0a4f, 0xcc15, 0x21, 0 - .dw 0x0a51, 0xcc15, 0x0a51, 0xcc15, 0x21, 0 - .dw 0x0a53, 0xcc15, 0x0a7f, 0xcc15, 0x21, 0 - .dw 0x0a81, 0xcc15, 0x0a81, 0xcc15, 0x21, 0 - .dw 0x0a83, 0xcc15, 0x0a8f, 0xcc15, 0x21, 0 - .dw 0x0a91, 0xcc15, 0x0a91, 0xcc15, 0x21, 0 - .dw 0x0a93, 0xcc15, 0x0abf, 0xcc15, 0x21, 0 - .dw 0x0ac1, 0xcc15, 0x0ac1, 0xcc15, 0x21, 0 - .dw 0x0ac3, 0xcc15, 0x0acf, 0xcc15, 0x21, 0 - .dw 0x0ad1, 0xcc15, 0x0ad1, 0xcc15, 0x21, 0 - .dw 0x0ad3, 0xcc15, 0x0aff, 0xcc15, 0x21, 0 - .dw 0x0b01, 0xcc15, 0x0b01, 0xcc15, 0x21, 0 - .dw 0x0b03, 0xcc15, 0x0b0f, 0xcc15, 0x21, 0 - .dw 0x0b11, 0xcc15, 0x0b11, 0xcc15, 0x21, 0 - .dw 0x0b13, 0xcc15, 0x0b3f, 0xcc15, 0x21, 0 - .dw 0x0b40, 0xcc15, 0x0b40, 0xcc15, 0x22, 0 - .dw 0x0b41, 0xcc15, 0x0b41, 0xcc15, 0x21, 0 - .dw 0x0b42, 0xcc15, 0x0b42, 0xcc15, 0x22, 0 - .dw 0x0b43, 0xcc15, 0x0b4f, 0xcc15, 0x21, 0 - .dw 0x0b50, 0xcc15, 0x0b50, 0xcc15, 0x22, 0 - .dw 0x0b51, 0xcc15, 0x0b51, 0xcc15, 0x21, 0 - .dw 0x0b52, 0xcc15, 0x0b52, 0xcc15, 0x22, 0 - .dw 0x0b53, 0xcc15, 0x0b7f, 0xcc15, 0x21, 0 - .dw 0x0b81, 0xcc15, 0x0b81, 0xcc15, 0x21, 0 - .dw 0x0b83, 0xcc15, 0x0b8f, 0xcc15, 0x21, 0 - .dw 0x0b91, 0xcc15, 0x0b91, 0xcc15, 0x21, 0 - .dw 0x0b93, 0xcc15, 0x0bbf, 0xcc15, 0x21, 0 - .dw 0x0bc1, 0xcc15, 0x0bc1, 0xcc15, 0x21, 0 - .dw 0x0bc3, 0xcc15, 0x0bcf, 0xcc15, 0x21, 0 - .dw 0x0bd1, 0xcc15, 0x0bd1, 0xcc15, 0x21, 0 - .dw 0x0bd3, 0xcc15, 0x0bff, 0xcc15, 0x21, 0 - .dw 0x0c01, 0xcc15, 0x0c01, 0xcc15, 0x21, 0 - .dw 0x0c03, 0xcc15, 0x0c0f, 0xcc15, 0x21, 0 - .dw 0x0c11, 0xcc15, 0x0c11, 0xcc15, 0x21, 0 - .dw 0x0c13, 0xcc15, 0x0c3f, 0xcc15, 0x21, 0 - .dw 0x0c41, 0xcc15, 0x0c41, 0xcc15, 0x21, 0 - .dw 0x0c43, 0xcc15, 0x0c4f, 0xcc15, 0x21, 0 - .dw 0x0c51, 0xcc15, 0x0c51, 0xcc15, 0x21, 0 - .dw 0x0c53, 0xcc15, 0x0c7f, 0xcc15, 0x21, 0 - .dw 0x0c81, 0xcc15, 0x0c81, 0xcc15, 0x21, 0 - .dw 0x0c83, 0xcc15, 0x0c8f, 0xcc15, 0x21, 0 - .dw 0x0c91, 0xcc15, 0x0c91, 0xcc15, 0x21, 0 - .dw 0x0c93, 0xcc15, 0x0cbf, 0xcc15, 0x21, 0 - .dw 0x0cc1, 0xcc15, 0x0cc1, 0xcc15, 0x21, 0 - .dw 0x0cc3, 0xcc15, 0x0ccf, 0xcc15, 0x21, 0 - .dw 0x0cd1, 0xcc15, 0x0cd1, 0xcc15, 0x21, 0 - .dw 0x0cd3, 0xcc15, 0x0cff, 0xcc15, 0x21, 0 - .dw 0x0d01, 0xcc15, 0x0d01, 0xcc15, 0x21, 0 - .dw 0x0d03, 0xcc15, 0x0d0f, 0xcc15, 0x21, 0 - .dw 0x0d11, 0xcc15, 0x0d11, 0xcc15, 0x21, 0 - .dw 0x0d13, 0xcc15, 0x0d3f, 0xcc15, 0x21, 0 - .dw 0x0d41, 0xcc15, 0x0d41, 0xcc15, 0x21, 0 - .dw 0x0d43, 0xcc15, 0x0d4f, 0xcc15, 0x21, 0 - .dw 0x0d51, 0xcc15, 0x0d51, 0xcc15, 0x21, 0 - .dw 0x0d53, 0xcc15, 0x0d7f, 0xcc15, 0x21, 0 - .dw 0x0d80, 0xcc15, 0x0d80, 0xcc15, 0x22, 0 - .dw 0x0d81, 0xcc15, 0x0d81, 0xcc15, 0x21, 0 - .dw 0x0d82, 0xcc15, 0x0d82, 0xcc15, 0x22, 0 - .dw 0x0d83, 0xcc15, 0x0d8f, 0xcc15, 0x21, 0 - .dw 0x0d90, 0xcc15, 0x0d90, 0xcc15, 0x22, 0 - .dw 0x0d91, 0xcc15, 0x0d91, 0xcc15, 0x21, 0 - .dw 0x0d92, 0xcc15, 0x0d92, 0xcc15, 0x22, 0 - .dw 0x0d93, 0xcc15, 0x0dbf, 0xcc15, 0x21, 0 - .dw 0x0dc1, 0xcc15, 0x0dc1, 0xcc15, 0x21, 0 - .dw 0x0dc3, 0xcc15, 0x0dcf, 0xcc15, 0x21, 0 - .dw 0x0dd1, 0xcc15, 0x0dd1, 0xcc15, 0x21, 0 - .dw 0x0dd3, 0xcc15, 0x0dff, 0xcc15, 0x21, 0 - .dw 0x0e01, 0xcc15, 0x0e01, 0xcc15, 0x21, 0 - .dw 0x0e03, 0xcc15, 0x0e0f, 0xcc15, 0x21, 0 - .dw 0x0e11, 0xcc15, 0x0e11, 0xcc15, 0x21, 0 - .dw 0x0e13, 0xcc15, 0x0e3f, 0xcc15, 0x21, 0 - .dw 0x0e41, 0xcc15, 0x0e41, 0xcc15, 0x21, 0 - .dw 0x0e43, 0xcc15, 0x0e4f, 0xcc15, 0x21, 0 - .dw 0x0e51, 0xcc15, 0x0e51, 0xcc15, 0x21, 0 - .dw 0x0e53, 0xcc15, 0x0e7f, 0xcc15, 0x21, 0 - .dw 0x0e81, 0xcc15, 0x0e81, 0xcc15, 0x21, 0 - .dw 0x0e83, 0xcc15, 0x0e8f, 0xcc15, 0x21, 0 - .dw 0x0e91, 0xcc15, 0x0e91, 0xcc15, 0x21, 0 - .dw 0x0e93, 0xcc15, 0x0ebf, 0xcc15, 0x21, 0 - .dw 0x0ec1, 0xcc15, 0x0ec1, 0xcc15, 0x21, 0 - .dw 0x0ec3, 0xcc15, 0x0ecf, 0xcc15, 0x21, 0 - .dw 0x0ed1, 0xcc15, 0x0ed1, 0xcc15, 0x21, 0 - .dw 0x0ed3, 0xcc15, 0x0eff, 0xcc15, 0x21, 0 - .dw 0x0f01, 0xcc15, 0x0f01, 0xcc15, 0x21, 0 - .dw 0x0f03, 0xcc15, 0x0f0f, 0xcc15, 0x21, 0 - .dw 0x0f11, 0xcc15, 0x0f11, 0xcc15, 0x21, 0 - .dw 0x0f13, 0xcc15, 0x0f3f, 0xcc15, 0x21, 0 - .dw 0x0f41, 0xcc15, 0x0f41, 0xcc15, 0x21, 0 - .dw 0x0f43, 0xcc15, 0x0f4f, 0xcc15, 0x21, 0 - .dw 0x0f51, 0xcc15, 0x0f51, 0xcc15, 0x21, 0 - .dw 0x0f53, 0xcc15, 0x0f7f, 0xcc15, 0x21, 0 - .dw 0x0f81, 0xcc15, 0x0f81, 0xcc15, 0x21, 0 - .dw 0x0f83, 0xcc15, 0x0f8f, 0xcc15, 0x21, 0 - .dw 0x0f91, 0xcc15, 0x0f91, 0xcc15, 0x21, 0 - .dw 0x0f93, 0xcc15, 0x0fbf, 0xcc15, 0x21, 0 - .dw 0x0fc0, 0xcc15, 0x0fc0, 0xcc15, 0x22, 0 - .dw 0x0fc1, 0xcc15, 0x0fc1, 0xcc15, 0x21, 0 - .dw 0x0fc2, 0xcc15, 0x0fc2, 0xcc15, 0x22, 0 - .dw 0x0fc3, 0xcc15, 0x0fcf, 0xcc15, 0x21, 0 - .dw 0x0fd0, 0xcc15, 0x0fd0, 0xcc15, 0x22, 0 - .dw 0x0fd1, 0xcc15, 0x0fd1, 0xcc15, 0x21, 0 - .dw 0x0fd2, 0xcc15, 0x0fd2, 0xcc15, 0x22, 0 - .dw 0x0fd3, 0xcc15, 0x1fff, 0xcc15, 0x21, 0 - .dw 0x2000, 0xcc15, 0x2000, 0xcc15, 0x22, 0 - .dw 0x2001, 0xcc15, 0x2001, 0xcc15, 0x21, 0 - .dw 0x2002, 0xcc15, 0x2002, 0xcc15, 0x22, 0 - .dw 0x2003, 0xcc15, 0x200f, 0xcc15, 0x21, 0 - .dw 0x2010, 0xcc15, 0x2010, 0xcc15, 0x22, 0 - .dw 0x2011, 0xcc15, 0x2011, 0xcc15, 0x21, 0 - .dw 0x2012, 0xcc15, 0x2012, 0xcc15, 0x22, 0 - .dw 0x2013, 0xcc15, 0x203f, 0xcc15, 0x21, 0 - .dw 0x2041, 0xcc15, 0x2041, 0xcc15, 0x21, 0 - .dw 0x2043, 0xcc15, 0x204f, 0xcc15, 0x21, 0 - .dw 0x2051, 0xcc15, 0x2051, 0xcc15, 0x21, 0 - .dw 0x2053, 0xcc15, 0x207f, 0xcc15, 0x21, 0 - .dw 0x2081, 0xcc15, 0x2081, 0xcc15, 0x21, 0 - .dw 0x2083, 0xcc15, 0x208f, 0xcc15, 0x21, 0 - .dw 0x2091, 0xcc15, 0x2091, 0xcc15, 0x21, 0 - .dw 0x2093, 0xcc15, 0x20bf, 0xcc15, 0x21, 0 - .dw 0x20c1, 0xcc15, 0x20c1, 0xcc15, 0x21, 0 - .dw 0x20c3, 0xcc15, 0x20cf, 0xcc15, 0x21, 0 - .dw 0x20d1, 0xcc15, 0x20d1, 0xcc15, 0x21, 0 - .dw 0x20d3, 0xcc15, 0x20ff, 0xcc15, 0x21, 0 - .dw 0x2101, 0xcc15, 0x2101, 0xcc15, 0x21, 0 - .dw 0x2103, 0xcc15, 0x210f, 0xcc15, 0x21, 0 - .dw 0x2111, 0xcc15, 0x2111, 0xcc15, 0x21, 0 - .dw 0x2113, 0xcc15, 0x213f, 0xcc15, 0x21, 0 - .dw 0x2141, 0xcc15, 0x2141, 0xcc15, 0x21, 0 - .dw 0x2143, 0xcc15, 0x214f, 0xcc15, 0x21, 0 - .dw 0x2151, 0xcc15, 0x2151, 0xcc15, 0x21, 0 - .dw 0x2153, 0xcc15, 0x217f, 0xcc15, 0x21, 0 - .dw 0x2181, 0xcc15, 0x2181, 0xcc15, 0x21, 0 - .dw 0x2183, 0xcc15, 0x218f, 0xcc15, 0x21, 0 - .dw 0x2191, 0xcc15, 0x2191, 0xcc15, 0x21, 0 - .dw 0x2193, 0xcc15, 0x21bf, 0xcc15, 0x21, 0 - .dw 0x21c1, 0xcc15, 0x21c1, 0xcc15, 0x21, 0 - .dw 0x21c3, 0xcc15, 0x21cf, 0xcc15, 0x21, 0 - .dw 0x21d1, 0xcc15, 0x21d1, 0xcc15, 0x21, 0 - .dw 0x21d3, 0xcc15, 0x21ff, 0xcc15, 0x21, 0 - .dw 0x2201, 0xcc15, 0x2201, 0xcc15, 0x21, 0 - .dw 0x2203, 0xcc15, 0x220f, 0xcc15, 0x21, 0 - .dw 0x2211, 0xcc15, 0x2211, 0xcc15, 0x21, 0 - .dw 0x2213, 0xcc15, 0x223f, 0xcc15, 0x21, 0 - .dw 0x2240, 0xcc15, 0x2240, 0xcc15, 0x22, 0 - .dw 0x2241, 0xcc15, 0x2241, 0xcc15, 0x21, 0 - .dw 0x2242, 0xcc15, 0x2242, 0xcc15, 0x22, 0 - .dw 0x2243, 0xcc15, 0x224f, 0xcc15, 0x21, 0 - .dw 0x2250, 0xcc15, 0x2250, 0xcc15, 0x22, 0 - .dw 0x2251, 0xcc15, 0x2251, 0xcc15, 0x21, 0 - .dw 0x2252, 0xcc15, 0x2252, 0xcc15, 0x22, 0 - .dw 0x2253, 0xcc15, 0x227f, 0xcc15, 0x21, 0 - .dw 0x2281, 0xcc15, 0x2281, 0xcc15, 0x21, 0 - .dw 0x2283, 0xcc15, 0x228f, 0xcc15, 0x21, 0 - .dw 0x2291, 0xcc15, 0x2291, 0xcc15, 0x21, 0 - .dw 0x2293, 0xcc15, 0x22bf, 0xcc15, 0x21, 0 - .dw 0x22c1, 0xcc15, 0x22c1, 0xcc15, 0x21, 0 - .dw 0x22c3, 0xcc15, 0x22cf, 0xcc15, 0x21, 0 - .dw 0x22d1, 0xcc15, 0x22d1, 0xcc15, 0x21, 0 - .dw 0x22d3, 0xcc15, 0x22ff, 0xcc15, 0x21, 0 - .dw 0x2301, 0xcc15, 0x2301, 0xcc15, 0x21, 0 - .dw 0x2303, 0xcc15, 0x230f, 0xcc15, 0x21, 0 - .dw 0x2311, 0xcc15, 0x2311, 0xcc15, 0x21, 0 - .dw 0x2313, 0xcc15, 0x233f, 0xcc15, 0x21, 0 - .dw 0x2341, 0xcc15, 0x2341, 0xcc15, 0x21, 0 - .dw 0x2343, 0xcc15, 0x234f, 0xcc15, 0x21, 0 - .dw 0x2351, 0xcc15, 0x2351, 0xcc15, 0x21, 0 - .dw 0x2353, 0xcc15, 0x237f, 0xcc15, 0x21, 0 - .dw 0x2381, 0xcc15, 0x2381, 0xcc15, 0x21, 0 - .dw 0x2383, 0xcc15, 0x238f, 0xcc15, 0x21, 0 - .dw 0x2391, 0xcc15, 0x2391, 0xcc15, 0x21, 0 - .dw 0x2393, 0xcc15, 0x23bf, 0xcc15, 0x21, 0 - .dw 0x23c1, 0xcc15, 0x23c1, 0xcc15, 0x21, 0 - .dw 0x23c3, 0xcc15, 0x23cf, 0xcc15, 0x21, 0 - .dw 0x23d1, 0xcc15, 0x23d1, 0xcc15, 0x21, 0 - .dw 0x23d3, 0xcc15, 0x23ff, 0xcc15, 0x21, 0 - .dw 0x2401, 0xcc15, 0x2401, 0xcc15, 0x21, 0 - .dw 0x2403, 0xcc15, 0x240f, 0xcc15, 0x21, 0 - .dw 0x2411, 0xcc15, 0x2411, 0xcc15, 0x21, 0 - .dw 0x2413, 0xcc15, 0x243f, 0xcc15, 0x21, 0 - .dw 0x2441, 0xcc15, 0x2441, 0xcc15, 0x21, 0 - .dw 0x2443, 0xcc15, 0x244f, 0xcc15, 0x21, 0 - .dw 0x2451, 0xcc15, 0x2451, 0xcc15, 0x21, 0 - .dw 0x2453, 0xcc15, 0x247f, 0xcc15, 0x21, 0 - .dw 0x2480, 0xcc15, 0x2480, 0xcc15, 0x22, 0 - .dw 0x2481, 0xcc15, 0x2481, 0xcc15, 0x21, 0 - .dw 0x2482, 0xcc15, 0x2482, 0xcc15, 0x22, 0 - .dw 0x2483, 0xcc15, 0x248f, 0xcc15, 0x21, 0 - .dw 0x2490, 0xcc15, 0x2490, 0xcc15, 0x22, 0 - .dw 0x2491, 0xcc15, 0x2491, 0xcc15, 0x21, 0 - .dw 0x2492, 0xcc15, 0x2492, 0xcc15, 0x22, 0 - .dw 0x2493, 0xcc15, 0x24bf, 0xcc15, 0x21, 0 - .dw 0x24c1, 0xcc15, 0x24c1, 0xcc15, 0x21, 0 - .dw 0x24c3, 0xcc15, 0x24cf, 0xcc15, 0x21, 0 - .dw 0x24d1, 0xcc15, 0x24d1, 0xcc15, 0x21, 0 - .dw 0x24d3, 0xcc15, 0x24ff, 0xcc15, 0x21, 0 - .dw 0x2501, 0xcc15, 0x2501, 0xcc15, 0x21, 0 - .dw 0x2503, 0xcc15, 0x250f, 0xcc15, 0x21, 0 - .dw 0x2511, 0xcc15, 0x2511, 0xcc15, 0x21, 0 - .dw 0x2513, 0xcc15, 0x253f, 0xcc15, 0x21, 0 - .dw 0x2541, 0xcc15, 0x2541, 0xcc15, 0x21, 0 - .dw 0x2543, 0xcc15, 0x254f, 0xcc15, 0x21, 0 - .dw 0x2551, 0xcc15, 0x2551, 0xcc15, 0x21, 0 - .dw 0x2553, 0xcc15, 0x257f, 0xcc15, 0x21, 0 - .dw 0x2581, 0xcc15, 0x2581, 0xcc15, 0x21, 0 - .dw 0x2583, 0xcc15, 0x258f, 0xcc15, 0x21, 0 - .dw 0x2591, 0xcc15, 0x2591, 0xcc15, 0x21, 0 - .dw 0x2593, 0xcc15, 0x25bf, 0xcc15, 0x21, 0 - .dw 0x25c1, 0xcc15, 0x25c1, 0xcc15, 0x21, 0 - .dw 0x25c3, 0xcc15, 0x25cf, 0xcc15, 0x21, 0 - .dw 0x25d1, 0xcc15, 0x25d1, 0xcc15, 0x21, 0 - .dw 0x25d3, 0xcc15, 0x25ff, 0xcc15, 0x21, 0 - .dw 0x2601, 0xcc15, 0x2601, 0xcc15, 0x21, 0 - .dw 0x2603, 0xcc15, 0x260f, 0xcc15, 0x21, 0 - .dw 0x2611, 0xcc15, 0x2611, 0xcc15, 0x21, 0 - .dw 0x2613, 0xcc15, 0x263f, 0xcc15, 0x21, 0 - .dw 0x2641, 0xcc15, 0x2641, 0xcc15, 0x21, 0 - .dw 0x2643, 0xcc15, 0x264f, 0xcc15, 0x21, 0 - .dw 0x2651, 0xcc15, 0x2651, 0xcc15, 0x21, 0 - .dw 0x2653, 0xcc15, 0x267f, 0xcc15, 0x21, 0 - .dw 0x2681, 0xcc15, 0x2681, 0xcc15, 0x21, 0 - .dw 0x2683, 0xcc15, 0x268f, 0xcc15, 0x21, 0 - .dw 0x2691, 0xcc15, 0x2691, 0xcc15, 0x21, 0 - .dw 0x2693, 0xcc15, 0x26bf, 0xcc15, 0x21, 0 - .dw 0x26c0, 0xcc15, 0x26c0, 0xcc15, 0x22, 0 - .dw 0x26c1, 0xcc15, 0x26c1, 0xcc15, 0x21, 0 - .dw 0x26c2, 0xcc15, 0x26c2, 0xcc15, 0x22, 0 - .dw 0x26c3, 0xcc15, 0x26cf, 0xcc15, 0x21, 0 - .dw 0x26d0, 0xcc15, 0x26d0, 0xcc15, 0x22, 0 - .dw 0x26d1, 0xcc15, 0x26d1, 0xcc15, 0x21, 0 - .dw 0x26d2, 0xcc15, 0x26d2, 0xcc15, 0x22, 0 - .dw 0x26d3, 0xcc15, 0x26ff, 0xcc15, 0x21, 0 - .dw 0x2701, 0xcc15, 0x2701, 0xcc15, 0x21, 0 - .dw 0x2703, 0xcc15, 0x270f, 0xcc15, 0x21, 0 - .dw 0x2711, 0xcc15, 0x2711, 0xcc15, 0x21, 0 - .dw 0x2713, 0xcc15, 0x273f, 0xcc15, 0x21, 0 - .dw 0x2741, 0xcc15, 0x2741, 0xcc15, 0x21, 0 - .dw 0x2743, 0xcc15, 0x274f, 0xcc15, 0x21, 0 - .dw 0x2751, 0xcc15, 0x2751, 0xcc15, 0x21, 0 - .dw 0x2753, 0xcc15, 0x277f, 0xcc15, 0x21, 0 - .dw 0x2781, 0xcc15, 0x2781, 0xcc15, 0x21, 0 - .dw 0x2783, 0xcc15, 0x278f, 0xcc15, 0x21, 0 - .dw 0x2791, 0xcc15, 0x2791, 0xcc15, 0x21, 0 - .dw 0x2793, 0xcc15, 0x27bf, 0xcc15, 0x21, 0 - .dw 0x27c1, 0xcc15, 0x27c1, 0xcc15, 0x21, 0 - .dw 0x27c3, 0xcc15, 0x27cf, 0xcc15, 0x21, 0 - .dw 0x27d1, 0xcc15, 0x27d1, 0xcc15, 0x21, 0 - .dw 0x27d3, 0xcc15, 0x27ff, 0xcc15, 0x21, 0 - .dw 0x2801, 0xcc15, 0x2801, 0xcc15, 0x21, 0 - .dw 0x2803, 0xcc15, 0x280f, 0xcc15, 0x21, 0 - .dw 0x2811, 0xcc15, 0x2811, 0xcc15, 0x21, 0 - .dw 0x2813, 0xcc15, 0x283f, 0xcc15, 0x21, 0 - .dw 0x2841, 0xcc15, 0x2841, 0xcc15, 0x21, 0 - .dw 0x2843, 0xcc15, 0x284f, 0xcc15, 0x21, 0 - .dw 0x2851, 0xcc15, 0x2851, 0xcc15, 0x21, 0 - .dw 0x2853, 0xcc15, 0x287f, 0xcc15, 0x21, 0 - .dw 0x2881, 0xcc15, 0x2881, 0xcc15, 0x21, 0 - .dw 0x2883, 0xcc15, 0x288f, 0xcc15, 0x21, 0 - .dw 0x2891, 0xcc15, 0x2891, 0xcc15, 0x21, 0 - .dw 0x2893, 0xcc15, 0x28bf, 0xcc15, 0x21, 0 - .dw 0x28c1, 0xcc15, 0x28c1, 0xcc15, 0x21, 0 - .dw 0x28c3, 0xcc15, 0x28cf, 0xcc15, 0x21, 0 - .dw 0x28d1, 0xcc15, 0x28d1, 0xcc15, 0x21, 0 - .dw 0x28d3, 0xcc15, 0x28ff, 0xcc15, 0x21, 0 - .dw 0x2900, 0xcc15, 0x2900, 0xcc15, 0x22, 0 - .dw 0x2901, 0xcc15, 0x2901, 0xcc15, 0x21, 0 - .dw 0x2902, 0xcc15, 0x2902, 0xcc15, 0x22, 0 - .dw 0x2903, 0xcc15, 0x290f, 0xcc15, 0x21, 0 - .dw 0x2910, 0xcc15, 0x2910, 0xcc15, 0x22, 0 - .dw 0x2911, 0xcc15, 0x2911, 0xcc15, 0x21, 0 - .dw 0x2912, 0xcc15, 0x2912, 0xcc15, 0x22, 0 - .dw 0x2913, 0xcc15, 0x293f, 0xcc15, 0x21, 0 - .dw 0x2941, 0xcc15, 0x2941, 0xcc15, 0x21, 0 - .dw 0x2943, 0xcc15, 0x294f, 0xcc15, 0x21, 0 - .dw 0x2951, 0xcc15, 0x2951, 0xcc15, 0x21, 0 - .dw 0x2953, 0xcc15, 0x297f, 0xcc15, 0x21, 0 - .dw 0x2981, 0xcc15, 0x2981, 0xcc15, 0x21, 0 - .dw 0x2983, 0xcc15, 0x298f, 0xcc15, 0x21, 0 - .dw 0x2991, 0xcc15, 0x2991, 0xcc15, 0x21, 0 - .dw 0x2993, 0xcc15, 0x29bf, 0xcc15, 0x21, 0 - .dw 0x29c1, 0xcc15, 0x29c1, 0xcc15, 0x21, 0 - .dw 0x29c3, 0xcc15, 0x29cf, 0xcc15, 0x21, 0 - .dw 0x29d1, 0xcc15, 0x29d1, 0xcc15, 0x21, 0 - .dw 0x29d3, 0xcc15, 0x29ff, 0xcc15, 0x21, 0 - .dw 0x2a01, 0xcc15, 0x2a01, 0xcc15, 0x21, 0 - .dw 0x2a03, 0xcc15, 0x2a0f, 0xcc15, 0x21, 0 - .dw 0x2a11, 0xcc15, 0x2a11, 0xcc15, 0x21, 0 - .dw 0x2a13, 0xcc15, 0x2a3f, 0xcc15, 0x21, 0 - .dw 0x2a41, 0xcc15, 0x2a41, 0xcc15, 0x21, 0 - .dw 0x2a43, 0xcc15, 0x2a4f, 0xcc15, 0x21, 0 - .dw 0x2a51, 0xcc15, 0x2a51, 0xcc15, 0x21, 0 - .dw 0x2a53, 0xcc15, 0x2a7f, 0xcc15, 0x21, 0 - .dw 0x2a81, 0xcc15, 0x2a81, 0xcc15, 0x21, 0 - .dw 0x2a83, 0xcc15, 0x2a8f, 0xcc15, 0x21, 0 - .dw 0x2a91, 0xcc15, 0x2a91, 0xcc15, 0x21, 0 - .dw 0x2a93, 0xcc15, 0x2abf, 0xcc15, 0x21, 0 - .dw 0x2ac1, 0xcc15, 0x2ac1, 0xcc15, 0x21, 0 - .dw 0x2ac3, 0xcc15, 0x2acf, 0xcc15, 0x21, 0 - .dw 0x2ad1, 0xcc15, 0x2ad1, 0xcc15, 0x21, 0 - .dw 0x2ad3, 0xcc15, 0x2aff, 0xcc15, 0x21, 0 - .dw 0x2b01, 0xcc15, 0x2b01, 0xcc15, 0x21, 0 - .dw 0x2b03, 0xcc15, 0x2b0f, 0xcc15, 0x21, 0 - .dw 0x2b11, 0xcc15, 0x2b11, 0xcc15, 0x21, 0 - .dw 0x2b13, 0xcc15, 0x2b3f, 0xcc15, 0x21, 0 - .dw 0x2b40, 0xcc15, 0x2b40, 0xcc15, 0x22, 0 - .dw 0x2b41, 0xcc15, 0x2b41, 0xcc15, 0x21, 0 - .dw 0x2b42, 0xcc15, 0x2b42, 0xcc15, 0x22, 0 - .dw 0x2b43, 0xcc15, 0x2b4f, 0xcc15, 0x21, 0 - .dw 0x2b50, 0xcc15, 0x2b50, 0xcc15, 0x22, 0 - .dw 0x2b51, 0xcc15, 0x2b51, 0xcc15, 0x21, 0 - .dw 0x2b52, 0xcc15, 0x2b52, 0xcc15, 0x22, 0 - .dw 0x2b53, 0xcc15, 0x2b7f, 0xcc15, 0x21, 0 - .dw 0x2b81, 0xcc15, 0x2b81, 0xcc15, 0x21, 0 - .dw 0x2b83, 0xcc15, 0x2b8f, 0xcc15, 0x21, 0 - .dw 0x2b91, 0xcc15, 0x2b91, 0xcc15, 0x21, 0 - .dw 0x2b93, 0xcc15, 0x2bbf, 0xcc15, 0x21, 0 - .dw 0x2bc1, 0xcc15, 0x2bc1, 0xcc15, 0x21, 0 - .dw 0x2bc3, 0xcc15, 0x2bcf, 0xcc15, 0x21, 0 - .dw 0x2bd1, 0xcc15, 0x2bd1, 0xcc15, 0x21, 0 - .dw 0x2bd3, 0xcc15, 0x2bff, 0xcc15, 0x21, 0 - .dw 0x2c01, 0xcc15, 0x2c01, 0xcc15, 0x21, 0 - .dw 0x2c03, 0xcc15, 0x2c0f, 0xcc15, 0x21, 0 - .dw 0x2c11, 0xcc15, 0x2c11, 0xcc15, 0x21, 0 - .dw 0x2c13, 0xcc15, 0x2c3f, 0xcc15, 0x21, 0 - .dw 0x2c41, 0xcc15, 0x2c41, 0xcc15, 0x21, 0 - .dw 0x2c43, 0xcc15, 0x2c4f, 0xcc15, 0x21, 0 - .dw 0x2c51, 0xcc15, 0x2c51, 0xcc15, 0x21, 0 - .dw 0x2c53, 0xcc15, 0x2c7f, 0xcc15, 0x21, 0 - .dw 0x2c81, 0xcc15, 0x2c81, 0xcc15, 0x21, 0 - .dw 0x2c83, 0xcc15, 0x2c8f, 0xcc15, 0x21, 0 - .dw 0x2c91, 0xcc15, 0x2c91, 0xcc15, 0x21, 0 - .dw 0x2c93, 0xcc15, 0x2cbf, 0xcc15, 0x21, 0 - .dw 0x2cc1, 0xcc15, 0x2cc1, 0xcc15, 0x21, 0 - .dw 0x2cc3, 0xcc15, 0x2ccf, 0xcc15, 0x21, 0 - .dw 0x2cd1, 0xcc15, 0x2cd1, 0xcc15, 0x21, 0 - .dw 0x2cd3, 0xcc15, 0x2cff, 0xcc15, 0x21, 0 - .dw 0x2d01, 0xcc15, 0x2d01, 0xcc15, 0x21, 0 - .dw 0x2d03, 0xcc15, 0x2d0f, 0xcc15, 0x21, 0 - .dw 0x2d11, 0xcc15, 0x2d11, 0xcc15, 0x21, 0 - .dw 0x2d13, 0xcc15, 0x2d3f, 0xcc15, 0x21, 0 - .dw 0x2d41, 0xcc15, 0x2d41, 0xcc15, 0x21, 0 - .dw 0x2d43, 0xcc15, 0x2d4f, 0xcc15, 0x21, 0 - .dw 0x2d51, 0xcc15, 0x2d51, 0xcc15, 0x21, 0 - .dw 0x2d53, 0xcc15, 0x2d7f, 0xcc15, 0x21, 0 - .dw 0x2d80, 0xcc15, 0x2d80, 0xcc15, 0x22, 0 - .dw 0x2d81, 0xcc15, 0x2d81, 0xcc15, 0x21, 0 - .dw 0x2d82, 0xcc15, 0x2d82, 0xcc15, 0x22, 0 - .dw 0x2d83, 0xcc15, 0x2d8f, 0xcc15, 0x21, 0 - .dw 0x2d90, 0xcc15, 0x2d90, 0xcc15, 0x22, 0 - .dw 0x2d91, 0xcc15, 0x2d91, 0xcc15, 0x21, 0 - .dw 0x2d92, 0xcc15, 0x2d92, 0xcc15, 0x22, 0 - .dw 0x2d93, 0xcc15, 0x2dbf, 0xcc15, 0x21, 0 - .dw 0x2dc1, 0xcc15, 0x2dc1, 0xcc15, 0x21, 0 - .dw 0x2dc3, 0xcc15, 0x2dcf, 0xcc15, 0x21, 0 - .dw 0x2dd1, 0xcc15, 0x2dd1, 0xcc15, 0x21, 0 - .dw 0x2dd3, 0xcc15, 0x2dff, 0xcc15, 0x21, 0 - .dw 0x2e01, 0xcc15, 0x2e01, 0xcc15, 0x21, 0 - .dw 0x2e03, 0xcc15, 0x2e0f, 0xcc15, 0x21, 0 - .dw 0x2e11, 0xcc15, 0x2e11, 0xcc15, 0x21, 0 - .dw 0x2e13, 0xcc15, 0x2e3f, 0xcc15, 0x21, 0 - .dw 0x2e41, 0xcc15, 0x2e41, 0xcc15, 0x21, 0 - .dw 0x2e43, 0xcc15, 0x2e4f, 0xcc15, 0x21, 0 - .dw 0x2e51, 0xcc15, 0x2e51, 0xcc15, 0x21, 0 - .dw 0x2e53, 0xcc15, 0x2e7f, 0xcc15, 0x21, 0 - .dw 0x2e81, 0xcc15, 0x2e81, 0xcc15, 0x21, 0 - .dw 0x2e83, 0xcc15, 0x2e8f, 0xcc15, 0x21, 0 - .dw 0x2e91, 0xcc15, 0x2e91, 0xcc15, 0x21, 0 - .dw 0x2e93, 0xcc15, 0x2ebf, 0xcc15, 0x21, 0 - .dw 0x2ec1, 0xcc15, 0x2ec1, 0xcc15, 0x21, 0 - .dw 0x2ec3, 0xcc15, 0x2ecf, 0xcc15, 0x21, 0 - .dw 0x2ed1, 0xcc15, 0x2ed1, 0xcc15, 0x21, 0 - .dw 0x2ed3, 0xcc15, 0x2eff, 0xcc15, 0x21, 0 - .dw 0x2f01, 0xcc15, 0x2f01, 0xcc15, 0x21, 0 - .dw 0x2f03, 0xcc15, 0x2f0f, 0xcc15, 0x21, 0 - .dw 0x2f11, 0xcc15, 0x2f11, 0xcc15, 0x21, 0 - .dw 0x2f13, 0xcc15, 0x2f3f, 0xcc15, 0x21, 0 - .dw 0x2f41, 0xcc15, 0x2f41, 0xcc15, 0x21, 0 - .dw 0x2f43, 0xcc15, 0x2f4f, 0xcc15, 0x21, 0 - .dw 0x2f51, 0xcc15, 0x2f51, 0xcc15, 0x21, 0 - .dw 0x2f53, 0xcc15, 0x2f7f, 0xcc15, 0x21, 0 - .dw 0x2f81, 0xcc15, 0x2f81, 0xcc15, 0x21, 0 - .dw 0x2f83, 0xcc15, 0x2f8f, 0xcc15, 0x21, 0 - .dw 0x2f91, 0xcc15, 0x2f91, 0xcc15, 0x21, 0 - .dw 0x2f93, 0xcc15, 0x2fbf, 0xcc15, 0x21, 0 - .dw 0x2fc0, 0xcc15, 0x2fc0, 0xcc15, 0x22, 0 - .dw 0x2fc1, 0xcc15, 0x2fc1, 0xcc15, 0x21, 0 - .dw 0x2fc2, 0xcc15, 0x2fc2, 0xcc15, 0x22, 0 - .dw 0x2fc3, 0xcc15, 0x2fcf, 0xcc15, 0x21, 0 - .dw 0x2fd0, 0xcc15, 0x2fd0, 0xcc15, 0x22, 0 - .dw 0x2fd1, 0xcc15, 0x2fd1, 0xcc15, 0x21, 0 - .dw 0x2fd2, 0xcc15, 0x2fd2, 0xcc15, 0x22, 0 - .dw 0x2fd3, 0xcc15, 0x3fff, 0xcc15, 0x21, 0 - .dw 0x4000, 0xcc15, 0x4000, 0xcc15, 0x22, 0 - .dw 0x4001, 0xcc15, 0x4001, 0xcc15, 0x21, 0 - .dw 0x4002, 0xcc15, 0x4002, 0xcc15, 0x22, 0 - .dw 0x4003, 0xcc15, 0x400f, 0xcc15, 0x21, 0 - .dw 0x4010, 0xcc15, 0x4010, 0xcc15, 0x22, 0 - .dw 0x4011, 0xcc15, 0x4011, 0xcc15, 0x21, 0 - .dw 0x4012, 0xcc15, 0x4012, 0xcc15, 0x22, 0 - .dw 0x4013, 0xcc15, 0x403f, 0xcc15, 0x21, 0 - .dw 0x4041, 0xcc15, 0x4041, 0xcc15, 0x21, 0 - .dw 0x4043, 0xcc15, 0x404f, 0xcc15, 0x21, 0 - .dw 0x4051, 0xcc15, 0x4051, 0xcc15, 0x21, 0 - .dw 0x4053, 0xcc15, 0x407f, 0xcc15, 0x21, 0 - .dw 0x4081, 0xcc15, 0x4081, 0xcc15, 0x21, 0 - .dw 0x4083, 0xcc15, 0x408f, 0xcc15, 0x21, 0 - .dw 0x4091, 0xcc15, 0x4091, 0xcc15, 0x21, 0 - .dw 0x4093, 0xcc15, 0x40bf, 0xcc15, 0x21, 0 - .dw 0x40c1, 0xcc15, 0x40c1, 0xcc15, 0x21, 0 - .dw 0x40c3, 0xcc15, 0x40cf, 0xcc15, 0x21, 0 - .dw 0x40d1, 0xcc15, 0x40d1, 0xcc15, 0x21, 0 - .dw 0x40d3, 0xcc15, 0x40ff, 0xcc15, 0x21, 0 - .dw 0x4101, 0xcc15, 0x4101, 0xcc15, 0x21, 0 - .dw 0x4103, 0xcc15, 0x410f, 0xcc15, 0x21, 0 - .dw 0x4111, 0xcc15, 0x4111, 0xcc15, 0x21, 0 - .dw 0x4113, 0xcc15, 0x413f, 0xcc15, 0x21, 0 - .dw 0x4141, 0xcc15, 0x4141, 0xcc15, 0x21, 0 - .dw 0x4143, 0xcc15, 0x414f, 0xcc15, 0x21, 0 - .dw 0x4151, 0xcc15, 0x4151, 0xcc15, 0x21, 0 - .dw 0x4153, 0xcc15, 0x417f, 0xcc15, 0x21, 0 - .dw 0x4181, 0xcc15, 0x4181, 0xcc15, 0x21, 0 - .dw 0x4183, 0xcc15, 0x418f, 0xcc15, 0x21, 0 - .dw 0x4191, 0xcc15, 0x4191, 0xcc15, 0x21, 0 - .dw 0x4193, 0xcc15, 0x41bf, 0xcc15, 0x21, 0 - .dw 0x41c1, 0xcc15, 0x41c1, 0xcc15, 0x21, 0 - .dw 0x41c3, 0xcc15, 0x41cf, 0xcc15, 0x21, 0 - .dw 0x41d1, 0xcc15, 0x41d1, 0xcc15, 0x21, 0 - .dw 0x41d3, 0xcc15, 0x41ff, 0xcc15, 0x21, 0 - .dw 0x4201, 0xcc15, 0x4201, 0xcc15, 0x21, 0 - .dw 0x4203, 0xcc15, 0x420f, 0xcc15, 0x21, 0 - .dw 0x4211, 0xcc15, 0x4211, 0xcc15, 0x21, 0 - .dw 0x4213, 0xcc15, 0x423f, 0xcc15, 0x21, 0 - .dw 0x4240, 0xcc15, 0x4240, 0xcc15, 0x22, 0 - .dw 0x4241, 0xcc15, 0x4241, 0xcc15, 0x21, 0 - .dw 0x4242, 0xcc15, 0x4242, 0xcc15, 0x22, 0 - .dw 0x4243, 0xcc15, 0x424f, 0xcc15, 0x21, 0 - .dw 0x4250, 0xcc15, 0x4250, 0xcc15, 0x22, 0 - .dw 0x4251, 0xcc15, 0x4251, 0xcc15, 0x21, 0 - .dw 0x4252, 0xcc15, 0x4252, 0xcc15, 0x22, 0 - .dw 0x4253, 0xcc15, 0x427f, 0xcc15, 0x21, 0 - .dw 0x4281, 0xcc15, 0x4281, 0xcc15, 0x21, 0 - .dw 0x4283, 0xcc15, 0x428f, 0xcc15, 0x21, 0 - .dw 0x4291, 0xcc15, 0x4291, 0xcc15, 0x21, 0 - .dw 0x4293, 0xcc15, 0x42bf, 0xcc15, 0x21, 0 - .dw 0x42c1, 0xcc15, 0x42c1, 0xcc15, 0x21, 0 - .dw 0x42c3, 0xcc15, 0x42cf, 0xcc15, 0x21, 0 - .dw 0x42d1, 0xcc15, 0x42d1, 0xcc15, 0x21, 0 - .dw 0x42d3, 0xcc15, 0x42ff, 0xcc15, 0x21, 0 - .dw 0x4301, 0xcc15, 0x4301, 0xcc15, 0x21, 0 - .dw 0x4303, 0xcc15, 0x430f, 0xcc15, 0x21, 0 - .dw 0x4311, 0xcc15, 0x4311, 0xcc15, 0x21, 0 - .dw 0x4313, 0xcc15, 0x433f, 0xcc15, 0x21, 0 - .dw 0x4341, 0xcc15, 0x4341, 0xcc15, 0x21, 0 - .dw 0x4343, 0xcc15, 0x434f, 0xcc15, 0x21, 0 - .dw 0x4351, 0xcc15, 0x4351, 0xcc15, 0x21, 0 - .dw 0x4353, 0xcc15, 0x437f, 0xcc15, 0x21, 0 - .dw 0x4381, 0xcc15, 0x4381, 0xcc15, 0x21, 0 - .dw 0x4383, 0xcc15, 0x438f, 0xcc15, 0x21, 0 - .dw 0x4391, 0xcc15, 0x4391, 0xcc15, 0x21, 0 - .dw 0x4393, 0xcc15, 0x43bf, 0xcc15, 0x21, 0 - .dw 0x43c1, 0xcc15, 0x43c1, 0xcc15, 0x21, 0 - .dw 0x43c3, 0xcc15, 0x43cf, 0xcc15, 0x21, 0 - .dw 0x43d1, 0xcc15, 0x43d1, 0xcc15, 0x21, 0 - .dw 0x43d3, 0xcc15, 0x43ff, 0xcc15, 0x21, 0 - .dw 0x4401, 0xcc15, 0x4401, 0xcc15, 0x21, 0 - .dw 0x4403, 0xcc15, 0x440f, 0xcc15, 0x21, 0 - .dw 0x4411, 0xcc15, 0x4411, 0xcc15, 0x21, 0 - .dw 0x4413, 0xcc15, 0x443f, 0xcc15, 0x21, 0 - .dw 0x4441, 0xcc15, 0x4441, 0xcc15, 0x21, 0 - .dw 0x4443, 0xcc15, 0x444f, 0xcc15, 0x21, 0 - .dw 0x4451, 0xcc15, 0x4451, 0xcc15, 0x21, 0 - .dw 0x4453, 0xcc15, 0x447f, 0xcc15, 0x21, 0 - .dw 0x4480, 0xcc15, 0x4480, 0xcc15, 0x22, 0 - .dw 0x4481, 0xcc15, 0x4481, 0xcc15, 0x21, 0 - .dw 0x4482, 0xcc15, 0x4482, 0xcc15, 0x22, 0 - .dw 0x4483, 0xcc15, 0x448f, 0xcc15, 0x21, 0 - .dw 0x4490, 0xcc15, 0x4490, 0xcc15, 0x22, 0 - .dw 0x4491, 0xcc15, 0x4491, 0xcc15, 0x21, 0 - .dw 0x4492, 0xcc15, 0x4492, 0xcc15, 0x22, 0 - .dw 0x4493, 0xcc15, 0x44bf, 0xcc15, 0x21, 0 - .dw 0x44c1, 0xcc15, 0x44c1, 0xcc15, 0x21, 0 - .dw 0x44c3, 0xcc15, 0x44cf, 0xcc15, 0x21, 0 - .dw 0x44d1, 0xcc15, 0x44d1, 0xcc15, 0x21, 0 - .dw 0x44d3, 0xcc15, 0x44ff, 0xcc15, 0x21, 0 - .dw 0x4501, 0xcc15, 0x4501, 0xcc15, 0x21, 0 - .dw 0x4503, 0xcc15, 0x450f, 0xcc15, 0x21, 0 - .dw 0x4511, 0xcc15, 0x4511, 0xcc15, 0x21, 0 - .dw 0x4513, 0xcc15, 0x453f, 0xcc15, 0x21, 0 - .dw 0x4541, 0xcc15, 0x4541, 0xcc15, 0x21, 0 - .dw 0x4543, 0xcc15, 0x454f, 0xcc15, 0x21, 0 - .dw 0x4551, 0xcc15, 0x4551, 0xcc15, 0x21, 0 - .dw 0x4553, 0xcc15, 0x457f, 0xcc15, 0x21, 0 - .dw 0x4581, 0xcc15, 0x4581, 0xcc15, 0x21, 0 - .dw 0x4583, 0xcc15, 0x458f, 0xcc15, 0x21, 0 - .dw 0x4591, 0xcc15, 0x4591, 0xcc15, 0x21, 0 - .dw 0x4593, 0xcc15, 0x45bf, 0xcc15, 0x21, 0 - .dw 0x45c1, 0xcc15, 0x45c1, 0xcc15, 0x21, 0 - .dw 0x45c3, 0xcc15, 0x45cf, 0xcc15, 0x21, 0 - .dw 0x45d1, 0xcc15, 0x45d1, 0xcc15, 0x21, 0 - .dw 0x45d3, 0xcc15, 0x45ff, 0xcc15, 0x21, 0 - .dw 0x4601, 0xcc15, 0x4601, 0xcc15, 0x21, 0 - .dw 0x4603, 0xcc15, 0x460f, 0xcc15, 0x21, 0 - .dw 0x4611, 0xcc15, 0x4611, 0xcc15, 0x21, 0 - .dw 0x4613, 0xcc15, 0x463f, 0xcc15, 0x21, 0 - .dw 0x4641, 0xcc15, 0x4641, 0xcc15, 0x21, 0 - .dw 0x4643, 0xcc15, 0x464f, 0xcc15, 0x21, 0 - .dw 0x4651, 0xcc15, 0x4651, 0xcc15, 0x21, 0 - .dw 0x4653, 0xcc15, 0x467f, 0xcc15, 0x21, 0 - .dw 0x4681, 0xcc15, 0x4681, 0xcc15, 0x21, 0 - .dw 0x4683, 0xcc15, 0x468f, 0xcc15, 0x21, 0 - .dw 0x4691, 0xcc15, 0x4691, 0xcc15, 0x21, 0 - .dw 0x4693, 0xcc15, 0x46bf, 0xcc15, 0x21, 0 - .dw 0x46c0, 0xcc15, 0x46c0, 0xcc15, 0x22, 0 - .dw 0x46c1, 0xcc15, 0x46c1, 0xcc15, 0x21, 0 - .dw 0x46c2, 0xcc15, 0x46c2, 0xcc15, 0x22, 0 - .dw 0x46c3, 0xcc15, 0x46cf, 0xcc15, 0x21, 0 - .dw 0x46d0, 0xcc15, 0x46d0, 0xcc15, 0x22, 0 - .dw 0x46d1, 0xcc15, 0x46d1, 0xcc15, 0x21, 0 - .dw 0x46d2, 0xcc15, 0x46d2, 0xcc15, 0x22, 0 - .dw 0x46d3, 0xcc15, 0x46ff, 0xcc15, 0x21, 0 - .dw 0x4701, 0xcc15, 0x4701, 0xcc15, 0x21, 0 - .dw 0x4703, 0xcc15, 0x470f, 0xcc15, 0x21, 0 - .dw 0x4711, 0xcc15, 0x4711, 0xcc15, 0x21, 0 - .dw 0x4713, 0xcc15, 0x473f, 0xcc15, 0x21, 0 - .dw 0x4741, 0xcc15, 0x4741, 0xcc15, 0x21, 0 - .dw 0x4743, 0xcc15, 0x474f, 0xcc15, 0x21, 0 - .dw 0x4751, 0xcc15, 0x4751, 0xcc15, 0x21, 0 - .dw 0x4753, 0xcc15, 0x477f, 0xcc15, 0x21, 0 - .dw 0x4781, 0xcc15, 0x4781, 0xcc15, 0x21, 0 - .dw 0x4783, 0xcc15, 0x478f, 0xcc15, 0x21, 0 - .dw 0x4791, 0xcc15, 0x4791, 0xcc15, 0x21, 0 - .dw 0x4793, 0xcc15, 0x47bf, 0xcc15, 0x21, 0 - .dw 0x47c1, 0xcc15, 0x47c1, 0xcc15, 0x21, 0 - .dw 0x47c3, 0xcc15, 0x47cf, 0xcc15, 0x21, 0 - .dw 0x47d1, 0xcc15, 0x47d1, 0xcc15, 0x21, 0 - .dw 0x47d3, 0xcc15, 0x47ff, 0xcc15, 0x21, 0 - .dw 0x4801, 0xcc15, 0x4801, 0xcc15, 0x21, 0 - .dw 0x4803, 0xcc15, 0x480f, 0xcc15, 0x21, 0 - .dw 0x4811, 0xcc15, 0x4811, 0xcc15, 0x21, 0 - .dw 0x4813, 0xcc15, 0x483f, 0xcc15, 0x21, 0 - .dw 0x4841, 0xcc15, 0x4841, 0xcc15, 0x21, 0 - .dw 0x4843, 0xcc15, 0x484f, 0xcc15, 0x21, 0 - .dw 0x4851, 0xcc15, 0x4851, 0xcc15, 0x21, 0 - .dw 0x4853, 0xcc15, 0x487f, 0xcc15, 0x21, 0 - .dw 0x4881, 0xcc15, 0x4881, 0xcc15, 0x21, 0 - .dw 0x4883, 0xcc15, 0x488f, 0xcc15, 0x21, 0 - .dw 0x4891, 0xcc15, 0x4891, 0xcc15, 0x21, 0 - .dw 0x4893, 0xcc15, 0x48bf, 0xcc15, 0x21, 0 - .dw 0x48c1, 0xcc15, 0x48c1, 0xcc15, 0x21, 0 - .dw 0x48c3, 0xcc15, 0x48cf, 0xcc15, 0x21, 0 - .dw 0x48d1, 0xcc15, 0x48d1, 0xcc15, 0x21, 0 - .dw 0x48d3, 0xcc15, 0x48ff, 0xcc15, 0x21, 0 - .dw 0x4900, 0xcc15, 0x4900, 0xcc15, 0x22, 0 - .dw 0x4901, 0xcc15, 0x4901, 0xcc15, 0x21, 0 - .dw 0x4902, 0xcc15, 0x4902, 0xcc15, 0x22, 0 - .dw 0x4903, 0xcc15, 0x490f, 0xcc15, 0x21, 0 - .dw 0x4910, 0xcc15, 0x4910, 0xcc15, 0x22, 0 - .dw 0x4911, 0xcc15, 0x4911, 0xcc15, 0x21, 0 - .dw 0x4912, 0xcc15, 0x4912, 0xcc15, 0x22, 0 - .dw 0x4913, 0xcc15, 0x493f, 0xcc15, 0x21, 0 - .dw 0x4941, 0xcc15, 0x4941, 0xcc15, 0x21, 0 - .dw 0x4943, 0xcc15, 0x494f, 0xcc15, 0x21, 0 - .dw 0x4951, 0xcc15, 0x4951, 0xcc15, 0x21, 0 - .dw 0x4953, 0xcc15, 0x497f, 0xcc15, 0x21, 0 - .dw 0x4981, 0xcc15, 0x4981, 0xcc15, 0x21, 0 - .dw 0x4983, 0xcc15, 0x498f, 0xcc15, 0x21, 0 - .dw 0x4991, 0xcc15, 0x4991, 0xcc15, 0x21, 0 - .dw 0x4993, 0xcc15, 0x49bf, 0xcc15, 0x21, 0 - .dw 0x49c1, 0xcc15, 0x49c1, 0xcc15, 0x21, 0 - .dw 0x49c3, 0xcc15, 0x49cf, 0xcc15, 0x21, 0 - .dw 0x49d1, 0xcc15, 0x49d1, 0xcc15, 0x21, 0 - .dw 0x49d3, 0xcc15, 0x49ff, 0xcc15, 0x21, 0 - .dw 0x4a01, 0xcc15, 0x4a01, 0xcc15, 0x21, 0 - .dw 0x4a03, 0xcc15, 0x4a0f, 0xcc15, 0x21, 0 - .dw 0x4a11, 0xcc15, 0x4a11, 0xcc15, 0x21, 0 - .dw 0x4a13, 0xcc15, 0x4a3f, 0xcc15, 0x21, 0 - .dw 0x4a41, 0xcc15, 0x4a41, 0xcc15, 0x21, 0 - .dw 0x4a43, 0xcc15, 0x4a4f, 0xcc15, 0x21, 0 - .dw 0x4a51, 0xcc15, 0x4a51, 0xcc15, 0x21, 0 - .dw 0x4a53, 0xcc15, 0x4a7f, 0xcc15, 0x21, 0 - .dw 0x4a81, 0xcc15, 0x4a81, 0xcc15, 0x21, 0 - .dw 0x4a83, 0xcc15, 0x4a8f, 0xcc15, 0x21, 0 - .dw 0x4a91, 0xcc15, 0x4a91, 0xcc15, 0x21, 0 - .dw 0x4a93, 0xcc15, 0x4abf, 0xcc15, 0x21, 0 - .dw 0x4ac1, 0xcc15, 0x4ac1, 0xcc15, 0x21, 0 - .dw 0x4ac3, 0xcc15, 0x4acf, 0xcc15, 0x21, 0 - .dw 0x4ad1, 0xcc15, 0x4ad1, 0xcc15, 0x21, 0 - .dw 0x4ad3, 0xcc15, 0x4aff, 0xcc15, 0x21, 0 - .dw 0x4b01, 0xcc15, 0x4b01, 0xcc15, 0x21, 0 - .dw 0x4b03, 0xcc15, 0x4b0f, 0xcc15, 0x21, 0 - .dw 0x4b11, 0xcc15, 0x4b11, 0xcc15, 0x21, 0 - .dw 0x4b13, 0xcc15, 0x4b3f, 0xcc15, 0x21, 0 - .dw 0x4b40, 0xcc15, 0x4b40, 0xcc15, 0x22, 0 - .dw 0x4b41, 0xcc15, 0x4b41, 0xcc15, 0x21, 0 - .dw 0x4b42, 0xcc15, 0x4b42, 0xcc15, 0x22, 0 - .dw 0x4b43, 0xcc15, 0x4b4f, 0xcc15, 0x21, 0 - .dw 0x4b50, 0xcc15, 0x4b50, 0xcc15, 0x22, 0 - .dw 0x4b51, 0xcc15, 0x4b51, 0xcc15, 0x21, 0 - .dw 0x4b52, 0xcc15, 0x4b52, 0xcc15, 0x22, 0 - .dw 0x4b53, 0xcc15, 0x4b7f, 0xcc15, 0x21, 0 - .dw 0x4b81, 0xcc15, 0x4b81, 0xcc15, 0x21, 0 - .dw 0x4b83, 0xcc15, 0x4b8f, 0xcc15, 0x21, 0 - .dw 0x4b91, 0xcc15, 0x4b91, 0xcc15, 0x21, 0 - .dw 0x4b93, 0xcc15, 0x4bbf, 0xcc15, 0x21, 0 - .dw 0x4bc1, 0xcc15, 0x4bc1, 0xcc15, 0x21, 0 - .dw 0x4bc3, 0xcc15, 0x4bcf, 0xcc15, 0x21, 0 - .dw 0x4bd1, 0xcc15, 0x4bd1, 0xcc15, 0x21, 0 - .dw 0x4bd3, 0xcc15, 0x4bff, 0xcc15, 0x21, 0 - .dw 0x4c01, 0xcc15, 0x4c01, 0xcc15, 0x21, 0 - .dw 0x4c03, 0xcc15, 0x4c0f, 0xcc15, 0x21, 0 - .dw 0x4c11, 0xcc15, 0x4c11, 0xcc15, 0x21, 0 - .dw 0x4c13, 0xcc15, 0x4c3f, 0xcc15, 0x21, 0 - .dw 0x4c41, 0xcc15, 0x4c41, 0xcc15, 0x21, 0 - .dw 0x4c43, 0xcc15, 0x4c4f, 0xcc15, 0x21, 0 - .dw 0x4c51, 0xcc15, 0x4c51, 0xcc15, 0x21, 0 - .dw 0x4c53, 0xcc15, 0x4c7f, 0xcc15, 0x21, 0 - .dw 0x4c81, 0xcc15, 0x4c81, 0xcc15, 0x21, 0 - .dw 0x4c83, 0xcc15, 0x4c8f, 0xcc15, 0x21, 0 - .dw 0x4c91, 0xcc15, 0x4c91, 0xcc15, 0x21, 0 - .dw 0x4c93, 0xcc15, 0x4cbf, 0xcc15, 0x21, 0 - .dw 0x4cc1, 0xcc15, 0x4cc1, 0xcc15, 0x21, 0 - .dw 0x4cc3, 0xcc15, 0x4ccf, 0xcc15, 0x21, 0 - .dw 0x4cd1, 0xcc15, 0x4cd1, 0xcc15, 0x21, 0 - .dw 0x4cd3, 0xcc15, 0x4cff, 0xcc15, 0x21, 0 - .dw 0x4d01, 0xcc15, 0x4d01, 0xcc15, 0x21, 0 - .dw 0x4d03, 0xcc15, 0x4d0f, 0xcc15, 0x21, 0 - .dw 0x4d11, 0xcc15, 0x4d11, 0xcc15, 0x21, 0 - .dw 0x4d13, 0xcc15, 0x4d3f, 0xcc15, 0x21, 0 - .dw 0x4d41, 0xcc15, 0x4d41, 0xcc15, 0x21, 0 - .dw 0x4d43, 0xcc15, 0x4d4f, 0xcc15, 0x21, 0 - .dw 0x4d51, 0xcc15, 0x4d51, 0xcc15, 0x21, 0 - .dw 0x4d53, 0xcc15, 0x4d7f, 0xcc15, 0x21, 0 - .dw 0x4d80, 0xcc15, 0x4d80, 0xcc15, 0x22, 0 - .dw 0x4d81, 0xcc15, 0x4d81, 0xcc15, 0x21, 0 - .dw 0x4d82, 0xcc15, 0x4d82, 0xcc15, 0x22, 0 - .dw 0x4d83, 0xcc15, 0x4d8f, 0xcc15, 0x21, 0 - .dw 0x4d90, 0xcc15, 0x4d90, 0xcc15, 0x22, 0 - .dw 0x4d91, 0xcc15, 0x4d91, 0xcc15, 0x21, 0 - .dw 0x4d92, 0xcc15, 0x4d92, 0xcc15, 0x22, 0 - .dw 0x4d93, 0xcc15, 0x4dbf, 0xcc15, 0x21, 0 - .dw 0x4dc1, 0xcc15, 0x4dc1, 0xcc15, 0x21, 0 - .dw 0x4dc3, 0xcc15, 0x4dcf, 0xcc15, 0x21, 0 - .dw 0x4dd1, 0xcc15, 0x4dd1, 0xcc15, 0x21, 0 - .dw 0x4dd3, 0xcc15, 0x4dff, 0xcc15, 0x21, 0 - .dw 0x4e01, 0xcc15, 0x4e01, 0xcc15, 0x21, 0 - .dw 0x4e03, 0xcc15, 0x4e0f, 0xcc15, 0x21, 0 - .dw 0x4e11, 0xcc15, 0x4e11, 0xcc15, 0x21, 0 - .dw 0x4e13, 0xcc15, 0x4e3f, 0xcc15, 0x21, 0 - .dw 0x4e41, 0xcc15, 0x4e41, 0xcc15, 0x21, 0 - .dw 0x4e43, 0xcc15, 0x4e4f, 0xcc15, 0x21, 0 - .dw 0x4e51, 0xcc15, 0x4e51, 0xcc15, 0x21, 0 - .dw 0x4e53, 0xcc15, 0x4e7f, 0xcc15, 0x21, 0 - .dw 0x4e81, 0xcc15, 0x4e81, 0xcc15, 0x21, 0 - .dw 0x4e83, 0xcc15, 0x4e8f, 0xcc15, 0x21, 0 - .dw 0x4e91, 0xcc15, 0x4e91, 0xcc15, 0x21, 0 - .dw 0x4e93, 0xcc15, 0x4ebf, 0xcc15, 0x21, 0 - .dw 0x4ec1, 0xcc15, 0x4ec1, 0xcc15, 0x21, 0 - .dw 0x4ec3, 0xcc15, 0x4ecf, 0xcc15, 0x21, 0 - .dw 0x4ed1, 0xcc15, 0x4ed1, 0xcc15, 0x21, 0 - .dw 0x4ed3, 0xcc15, 0x4eff, 0xcc15, 0x21, 0 - .dw 0x4f01, 0xcc15, 0x4f01, 0xcc15, 0x21, 0 - .dw 0x4f03, 0xcc15, 0x4f0f, 0xcc15, 0x21, 0 - .dw 0x4f11, 0xcc15, 0x4f11, 0xcc15, 0x21, 0 - .dw 0x4f13, 0xcc15, 0x4f3f, 0xcc15, 0x21, 0 - .dw 0x4f41, 0xcc15, 0x4f41, 0xcc15, 0x21, 0 - .dw 0x4f43, 0xcc15, 0x4f4f, 0xcc15, 0x21, 0 - .dw 0x4f51, 0xcc15, 0x4f51, 0xcc15, 0x21, 0 - .dw 0x4f53, 0xcc15, 0x4f7f, 0xcc15, 0x21, 0 - .dw 0x4f81, 0xcc15, 0x4f81, 0xcc15, 0x21, 0 - .dw 0x4f83, 0xcc15, 0x4f8f, 0xcc15, 0x21, 0 - .dw 0x4f91, 0xcc15, 0x4f91, 0xcc15, 0x21, 0 - .dw 0x4f93, 0xcc15, 0x4fbf, 0xcc15, 0x21, 0 - .dw 0x4fc0, 0xcc15, 0x4fc0, 0xcc15, 0x22, 0 - .dw 0x4fc1, 0xcc15, 0x4fc1, 0xcc15, 0x21, 0 - .dw 0x4fc2, 0xcc15, 0x4fc2, 0xcc15, 0x22, 0 - .dw 0x4fc3, 0xcc15, 0x4fcf, 0xcc15, 0x21, 0 - .dw 0x4fd0, 0xcc15, 0x4fd0, 0xcc15, 0x22, 0 - .dw 0x4fd1, 0xcc15, 0x4fd1, 0xcc15, 0x21, 0 - .dw 0x4fd2, 0xcc15, 0x4fd2, 0xcc15, 0x22, 0 - .dw 0x4fd3, 0xcc15, 0x5fff, 0xcc15, 0x21, 0 - .dw 0x6000, 0xcc15, 0x6000, 0xcc15, 0x22, 0 - .dw 0x6001, 0xcc15, 0x6001, 0xcc15, 0x21, 0 - .dw 0x6002, 0xcc15, 0x6002, 0xcc15, 0x22, 0 - .dw 0x6003, 0xcc15, 0x600f, 0xcc15, 0x21, 0 - .dw 0x6010, 0xcc15, 0x6010, 0xcc15, 0x22, 0 - .dw 0x6011, 0xcc15, 0x6011, 0xcc15, 0x21, 0 - .dw 0x6012, 0xcc15, 0x6012, 0xcc15, 0x22, 0 - .dw 0x6013, 0xcc15, 0x603f, 0xcc15, 0x21, 0 - .dw 0x6041, 0xcc15, 0x6041, 0xcc15, 0x21, 0 - .dw 0x6043, 0xcc15, 0x604f, 0xcc15, 0x21, 0 - .dw 0x6051, 0xcc15, 0x6051, 0xcc15, 0x21, 0 - .dw 0x6053, 0xcc15, 0x607f, 0xcc15, 0x21, 0 - .dw 0x6081, 0xcc15, 0x6081, 0xcc15, 0x21, 0 - .dw 0x6083, 0xcc15, 0x608f, 0xcc15, 0x21, 0 - .dw 0x6091, 0xcc15, 0x6091, 0xcc15, 0x21, 0 - .dw 0x6093, 0xcc15, 0x60bf, 0xcc15, 0x21, 0 - .dw 0x60c1, 0xcc15, 0x60c1, 0xcc15, 0x21, 0 - .dw 0x60c3, 0xcc15, 0x60cf, 0xcc15, 0x21, 0 - .dw 0x60d1, 0xcc15, 0x60d1, 0xcc15, 0x21, 0 - .dw 0x60d3, 0xcc15, 0x60ff, 0xcc15, 0x21, 0 - .dw 0x6101, 0xcc15, 0x6101, 0xcc15, 0x21, 0 - .dw 0x6103, 0xcc15, 0x610f, 0xcc15, 0x21, 0 - .dw 0x6111, 0xcc15, 0x6111, 0xcc15, 0x21, 0 - .dw 0x6113, 0xcc15, 0x613f, 0xcc15, 0x21, 0 - .dw 0x6141, 0xcc15, 0x6141, 0xcc15, 0x21, 0 - .dw 0x6143, 0xcc15, 0x614f, 0xcc15, 0x21, 0 - .dw 0x6151, 0xcc15, 0x6151, 0xcc15, 0x21, 0 - .dw 0x6153, 0xcc15, 0x617f, 0xcc15, 0x21, 0 - .dw 0x6181, 0xcc15, 0x6181, 0xcc15, 0x21, 0 - .dw 0x6183, 0xcc15, 0x618f, 0xcc15, 0x21, 0 - .dw 0x6191, 0xcc15, 0x6191, 0xcc15, 0x21, 0 - .dw 0x6193, 0xcc15, 0x61bf, 0xcc15, 0x21, 0 - .dw 0x61c1, 0xcc15, 0x61c1, 0xcc15, 0x21, 0 - .dw 0x61c3, 0xcc15, 0x61cf, 0xcc15, 0x21, 0 - .dw 0x61d1, 0xcc15, 0x61d1, 0xcc15, 0x21, 0 - .dw 0x61d3, 0xcc15, 0x61ff, 0xcc15, 0x21, 0 - .dw 0x6201, 0xcc15, 0x6201, 0xcc15, 0x21, 0 - .dw 0x6203, 0xcc15, 0x620f, 0xcc15, 0x21, 0 - .dw 0x6211, 0xcc15, 0x6211, 0xcc15, 0x21, 0 - .dw 0x6213, 0xcc15, 0x623f, 0xcc15, 0x21, 0 - .dw 0x6240, 0xcc15, 0x6240, 0xcc15, 0x22, 0 - .dw 0x6241, 0xcc15, 0x6241, 0xcc15, 0x21, 0 - .dw 0x6242, 0xcc15, 0x6242, 0xcc15, 0x22, 0 - .dw 0x6243, 0xcc15, 0x624f, 0xcc15, 0x21, 0 - .dw 0x6250, 0xcc15, 0x6250, 0xcc15, 0x22, 0 - .dw 0x6251, 0xcc15, 0x6251, 0xcc15, 0x21, 0 - .dw 0x6252, 0xcc15, 0x6252, 0xcc15, 0x22, 0 - .dw 0x6253, 0xcc15, 0x627f, 0xcc15, 0x21, 0 - .dw 0x6281, 0xcc15, 0x6281, 0xcc15, 0x21, 0 - .dw 0x6283, 0xcc15, 0x628f, 0xcc15, 0x21, 0 - .dw 0x6291, 0xcc15, 0x6291, 0xcc15, 0x21, 0 - .dw 0x6293, 0xcc15, 0x62bf, 0xcc15, 0x21, 0 - .dw 0x62c1, 0xcc15, 0x62c1, 0xcc15, 0x21, 0 - .dw 0x62c3, 0xcc15, 0x62cf, 0xcc15, 0x21, 0 - .dw 0x62d1, 0xcc15, 0x62d1, 0xcc15, 0x21, 0 - .dw 0x62d3, 0xcc15, 0x62ff, 0xcc15, 0x21, 0 - .dw 0x6301, 0xcc15, 0x6301, 0xcc15, 0x21, 0 - .dw 0x6303, 0xcc15, 0x630f, 0xcc15, 0x21, 0 - .dw 0x6311, 0xcc15, 0x6311, 0xcc15, 0x21, 0 - .dw 0x6313, 0xcc15, 0x633f, 0xcc15, 0x21, 0 - .dw 0x6341, 0xcc15, 0x6341, 0xcc15, 0x21, 0 - .dw 0x6343, 0xcc15, 0x634f, 0xcc15, 0x21, 0 - .dw 0x6351, 0xcc15, 0x6351, 0xcc15, 0x21, 0 - .dw 0x6353, 0xcc15, 0x637f, 0xcc15, 0x21, 0 - .dw 0x6381, 0xcc15, 0x6381, 0xcc15, 0x21, 0 - .dw 0x6383, 0xcc15, 0x638f, 0xcc15, 0x21, 0 - .dw 0x6391, 0xcc15, 0x6391, 0xcc15, 0x21, 0 - .dw 0x6393, 0xcc15, 0x63bf, 0xcc15, 0x21, 0 - .dw 0x63c1, 0xcc15, 0x63c1, 0xcc15, 0x21, 0 - .dw 0x63c3, 0xcc15, 0x63cf, 0xcc15, 0x21, 0 - .dw 0x63d1, 0xcc15, 0x63d1, 0xcc15, 0x21, 0 - .dw 0x63d3, 0xcc15, 0x63ff, 0xcc15, 0x21, 0 - .dw 0x6401, 0xcc15, 0x6401, 0xcc15, 0x21, 0 - .dw 0x6403, 0xcc15, 0x640f, 0xcc15, 0x21, 0 - .dw 0x6411, 0xcc15, 0x6411, 0xcc15, 0x21, 0 - .dw 0x6413, 0xcc15, 0x643f, 0xcc15, 0x21, 0 - .dw 0x6441, 0xcc15, 0x6441, 0xcc15, 0x21, 0 - .dw 0x6443, 0xcc15, 0x644f, 0xcc15, 0x21, 0 - .dw 0x6451, 0xcc15, 0x6451, 0xcc15, 0x21, 0 - .dw 0x6453, 0xcc15, 0x647f, 0xcc15, 0x21, 0 - .dw 0x6480, 0xcc15, 0x6480, 0xcc15, 0x22, 0 - .dw 0x6481, 0xcc15, 0x6481, 0xcc15, 0x21, 0 - .dw 0x6482, 0xcc15, 0x6482, 0xcc15, 0x22, 0 - .dw 0x6483, 0xcc15, 0x648f, 0xcc15, 0x21, 0 - .dw 0x6490, 0xcc15, 0x6490, 0xcc15, 0x22, 0 - .dw 0x6491, 0xcc15, 0x6491, 0xcc15, 0x21, 0 - .dw 0x6492, 0xcc15, 0x6492, 0xcc15, 0x22, 0 - .dw 0x6493, 0xcc15, 0x64bf, 0xcc15, 0x21, 0 - .dw 0x64c1, 0xcc15, 0x64c1, 0xcc15, 0x21, 0 - .dw 0x64c3, 0xcc15, 0x64cf, 0xcc15, 0x21, 0 - .dw 0x64d1, 0xcc15, 0x64d1, 0xcc15, 0x21, 0 - .dw 0x64d3, 0xcc15, 0x64ff, 0xcc15, 0x21, 0 - .dw 0x6501, 0xcc15, 0x6501, 0xcc15, 0x21, 0 - .dw 0x6503, 0xcc15, 0x650f, 0xcc15, 0x21, 0 - .dw 0x6511, 0xcc15, 0x6511, 0xcc15, 0x21, 0 - .dw 0x6513, 0xcc15, 0x653f, 0xcc15, 0x21, 0 - .dw 0x6541, 0xcc15, 0x6541, 0xcc15, 0x21, 0 - .dw 0x6543, 0xcc15, 0x654f, 0xcc15, 0x21, 0 - .dw 0x6551, 0xcc15, 0x6551, 0xcc15, 0x21, 0 - .dw 0x6553, 0xcc15, 0x657f, 0xcc15, 0x21, 0 - .dw 0x6581, 0xcc15, 0x6581, 0xcc15, 0x21, 0 - .dw 0x6583, 0xcc15, 0x658f, 0xcc15, 0x21, 0 - .dw 0x6591, 0xcc15, 0x6591, 0xcc15, 0x21, 0 - .dw 0x6593, 0xcc15, 0x65bf, 0xcc15, 0x21, 0 - .dw 0x65c1, 0xcc15, 0x65c1, 0xcc15, 0x21, 0 - .dw 0x65c3, 0xcc15, 0x65cf, 0xcc15, 0x21, 0 - .dw 0x65d1, 0xcc15, 0x65d1, 0xcc15, 0x21, 0 - .dw 0x65d3, 0xcc15, 0x65ff, 0xcc15, 0x21, 0 - .dw 0x6601, 0xcc15, 0x6601, 0xcc15, 0x21, 0 - .dw 0x6603, 0xcc15, 0x660f, 0xcc15, 0x21, 0 - .dw 0x6611, 0xcc15, 0x6611, 0xcc15, 0x21, 0 - .dw 0x6613, 0xcc15, 0x663f, 0xcc15, 0x21, 0 - .dw 0x6641, 0xcc15, 0x6641, 0xcc15, 0x21, 0 - .dw 0x6643, 0xcc15, 0x664f, 0xcc15, 0x21, 0 - .dw 0x6651, 0xcc15, 0x6651, 0xcc15, 0x21, 0 - .dw 0x6653, 0xcc15, 0x667f, 0xcc15, 0x21, 0 - .dw 0x6681, 0xcc15, 0x6681, 0xcc15, 0x21, 0 - .dw 0x6683, 0xcc15, 0x668f, 0xcc15, 0x21, 0 - .dw 0x6691, 0xcc15, 0x6691, 0xcc15, 0x21, 0 - .dw 0x6693, 0xcc15, 0x66bf, 0xcc15, 0x21, 0 - .dw 0x66c0, 0xcc15, 0x66c0, 0xcc15, 0x22, 0 - .dw 0x66c1, 0xcc15, 0x66c1, 0xcc15, 0x21, 0 - .dw 0x66c2, 0xcc15, 0x66c2, 0xcc15, 0x22, 0 - .dw 0x66c3, 0xcc15, 0x66cf, 0xcc15, 0x21, 0 - .dw 0x66d0, 0xcc15, 0x66d0, 0xcc15, 0x22, 0 - .dw 0x66d1, 0xcc15, 0x66d1, 0xcc15, 0x21, 0 - .dw 0x66d2, 0xcc15, 0x66d2, 0xcc15, 0x22, 0 - .dw 0x66d3, 0xcc15, 0x66ff, 0xcc15, 0x21, 0 - .dw 0x6701, 0xcc15, 0x6701, 0xcc15, 0x21, 0 - .dw 0x6703, 0xcc15, 0x670f, 0xcc15, 0x21, 0 - .dw 0x6711, 0xcc15, 0x6711, 0xcc15, 0x21, 0 - .dw 0x6713, 0xcc15, 0x673f, 0xcc15, 0x21, 0 - .dw 0x6741, 0xcc15, 0x6741, 0xcc15, 0x21, 0 - .dw 0x6743, 0xcc15, 0x674f, 0xcc15, 0x21, 0 - .dw 0x6751, 0xcc15, 0x6751, 0xcc15, 0x21, 0 - .dw 0x6753, 0xcc15, 0x677f, 0xcc15, 0x21, 0 - .dw 0x6781, 0xcc15, 0x6781, 0xcc15, 0x21, 0 - .dw 0x6783, 0xcc15, 0x678f, 0xcc15, 0x21, 0 - .dw 0x6791, 0xcc15, 0x6791, 0xcc15, 0x21, 0 - .dw 0x6793, 0xcc15, 0x67bf, 0xcc15, 0x21, 0 - .dw 0x67c1, 0xcc15, 0x67c1, 0xcc15, 0x21, 0 - .dw 0x67c3, 0xcc15, 0x67cf, 0xcc15, 0x21, 0 - .dw 0x67d1, 0xcc15, 0x67d1, 0xcc15, 0x21, 0 - .dw 0x67d3, 0xcc15, 0x67ff, 0xcc15, 0x21, 0 - .dw 0x6801, 0xcc15, 0x6801, 0xcc15, 0x21, 0 - .dw 0x6803, 0xcc15, 0x680f, 0xcc15, 0x21, 0 - .dw 0x6811, 0xcc15, 0x6811, 0xcc15, 0x21, 0 - .dw 0x6813, 0xcc15, 0x683f, 0xcc15, 0x21, 0 - .dw 0x6841, 0xcc15, 0x6841, 0xcc15, 0x21, 0 - .dw 0x6843, 0xcc15, 0x684f, 0xcc15, 0x21, 0 - .dw 0x6851, 0xcc15, 0x6851, 0xcc15, 0x21, 0 - .dw 0x6853, 0xcc15, 0x687f, 0xcc15, 0x21, 0 - .dw 0x6881, 0xcc15, 0x6881, 0xcc15, 0x21, 0 - .dw 0x6883, 0xcc15, 0x688f, 0xcc15, 0x21, 0 - .dw 0x6891, 0xcc15, 0x6891, 0xcc15, 0x21, 0 - .dw 0x6893, 0xcc15, 0x68bf, 0xcc15, 0x21, 0 - .dw 0x68c1, 0xcc15, 0x68c1, 0xcc15, 0x21, 0 - .dw 0x68c3, 0xcc15, 0x68cf, 0xcc15, 0x21, 0 - .dw 0x68d1, 0xcc15, 0x68d1, 0xcc15, 0x21, 0 - .dw 0x68d3, 0xcc15, 0x68ff, 0xcc15, 0x21, 0 - .dw 0x6900, 0xcc15, 0x6900, 0xcc15, 0x22, 0 - .dw 0x6901, 0xcc15, 0x6901, 0xcc15, 0x21, 0 - .dw 0x6902, 0xcc15, 0x6902, 0xcc15, 0x22, 0 - .dw 0x6903, 0xcc15, 0x690f, 0xcc15, 0x21, 0 - .dw 0x6910, 0xcc15, 0x6910, 0xcc15, 0x22, 0 - .dw 0x6911, 0xcc15, 0x6911, 0xcc15, 0x21, 0 - .dw 0x6912, 0xcc15, 0x6912, 0xcc15, 0x22, 0 - .dw 0x6913, 0xcc15, 0x693f, 0xcc15, 0x21, 0 - .dw 0x6941, 0xcc15, 0x6941, 0xcc15, 0x21, 0 - .dw 0x6943, 0xcc15, 0x694f, 0xcc15, 0x21, 0 - .dw 0x6951, 0xcc15, 0x6951, 0xcc15, 0x21, 0 - .dw 0x6953, 0xcc15, 0x697f, 0xcc15, 0x21, 0 - .dw 0x6981, 0xcc15, 0x6981, 0xcc15, 0x21, 0 - .dw 0x6983, 0xcc15, 0x698f, 0xcc15, 0x21, 0 - .dw 0x6991, 0xcc15, 0x6991, 0xcc15, 0x21, 0 - .dw 0x6993, 0xcc15, 0x69bf, 0xcc15, 0x21, 0 - .dw 0x69c1, 0xcc15, 0x69c1, 0xcc15, 0x21, 0 - .dw 0x69c3, 0xcc15, 0x69cf, 0xcc15, 0x21, 0 - .dw 0x69d1, 0xcc15, 0x69d1, 0xcc15, 0x21, 0 - .dw 0x69d3, 0xcc15, 0x69ff, 0xcc15, 0x21, 0 - .dw 0x6a01, 0xcc15, 0x6a01, 0xcc15, 0x21, 0 - .dw 0x6a03, 0xcc15, 0x6a0f, 0xcc15, 0x21, 0 - .dw 0x6a11, 0xcc15, 0x6a11, 0xcc15, 0x21, 0 - .dw 0x6a13, 0xcc15, 0x6a3f, 0xcc15, 0x21, 0 - .dw 0x6a41, 0xcc15, 0x6a41, 0xcc15, 0x21, 0 - .dw 0x6a43, 0xcc15, 0x6a4f, 0xcc15, 0x21, 0 - .dw 0x6a51, 0xcc15, 0x6a51, 0xcc15, 0x21, 0 - .dw 0x6a53, 0xcc15, 0x6a7f, 0xcc15, 0x21, 0 - .dw 0x6a81, 0xcc15, 0x6a81, 0xcc15, 0x21, 0 - .dw 0x6a83, 0xcc15, 0x6a8f, 0xcc15, 0x21, 0 - .dw 0x6a91, 0xcc15, 0x6a91, 0xcc15, 0x21, 0 - .dw 0x6a93, 0xcc15, 0x6abf, 0xcc15, 0x21, 0 - .dw 0x6ac1, 0xcc15, 0x6ac1, 0xcc15, 0x21, 0 - .dw 0x6ac3, 0xcc15, 0x6acf, 0xcc15, 0x21, 0 - .dw 0x6ad1, 0xcc15, 0x6ad1, 0xcc15, 0x21, 0 - .dw 0x6ad3, 0xcc15, 0x6aff, 0xcc15, 0x21, 0 - .dw 0x6b01, 0xcc15, 0x6b01, 0xcc15, 0x21, 0 - .dw 0x6b03, 0xcc15, 0x6b0f, 0xcc15, 0x21, 0 - .dw 0x6b11, 0xcc15, 0x6b11, 0xcc15, 0x21, 0 - .dw 0x6b13, 0xcc15, 0x6b3f, 0xcc15, 0x21, 0 - .dw 0x6b40, 0xcc15, 0x6b40, 0xcc15, 0x22, 0 - .dw 0x6b41, 0xcc15, 0x6b41, 0xcc15, 0x21, 0 - .dw 0x6b42, 0xcc15, 0x6b42, 0xcc15, 0x22, 0 - .dw 0x6b43, 0xcc15, 0x6b4f, 0xcc15, 0x21, 0 - .dw 0x6b50, 0xcc15, 0x6b50, 0xcc15, 0x22, 0 - .dw 0x6b51, 0xcc15, 0x6b51, 0xcc15, 0x21, 0 - .dw 0x6b52, 0xcc15, 0x6b52, 0xcc15, 0x22, 0 - .dw 0x6b53, 0xcc15, 0x6b7f, 0xcc15, 0x21, 0 - .dw 0x6b81, 0xcc15, 0x6b81, 0xcc15, 0x21, 0 - .dw 0x6b83, 0xcc15, 0x6b8f, 0xcc15, 0x21, 0 - .dw 0x6b91, 0xcc15, 0x6b91, 0xcc15, 0x21, 0 - .dw 0x6b93, 0xcc15, 0x6bbf, 0xcc15, 0x21, 0 - .dw 0x6bc1, 0xcc15, 0x6bc1, 0xcc15, 0x21, 0 - .dw 0x6bc3, 0xcc15, 0x6bcf, 0xcc15, 0x21, 0 - .dw 0x6bd1, 0xcc15, 0x6bd1, 0xcc15, 0x21, 0 - .dw 0x6bd3, 0xcc15, 0x6bff, 0xcc15, 0x21, 0 - .dw 0x6c01, 0xcc15, 0x6c01, 0xcc15, 0x21, 0 - .dw 0x6c03, 0xcc15, 0x6c0f, 0xcc15, 0x21, 0 - .dw 0x6c11, 0xcc15, 0x6c11, 0xcc15, 0x21, 0 - .dw 0x6c13, 0xcc15, 0x6c3f, 0xcc15, 0x21, 0 - .dw 0x6c41, 0xcc15, 0x6c41, 0xcc15, 0x21, 0 - .dw 0x6c43, 0xcc15, 0x6c4f, 0xcc15, 0x21, 0 - .dw 0x6c51, 0xcc15, 0x6c51, 0xcc15, 0x21, 0 - .dw 0x6c53, 0xcc15, 0x6c7f, 0xcc15, 0x21, 0 - .dw 0x6c81, 0xcc15, 0x6c81, 0xcc15, 0x21, 0 - .dw 0x6c83, 0xcc15, 0x6c8f, 0xcc15, 0x21, 0 - .dw 0x6c91, 0xcc15, 0x6c91, 0xcc15, 0x21, 0 - .dw 0x6c93, 0xcc15, 0x6cbf, 0xcc15, 0x21, 0 - .dw 0x6cc1, 0xcc15, 0x6cc1, 0xcc15, 0x21, 0 - .dw 0x6cc3, 0xcc15, 0x6ccf, 0xcc15, 0x21, 0 - .dw 0x6cd1, 0xcc15, 0x6cd1, 0xcc15, 0x21, 0 - .dw 0x6cd3, 0xcc15, 0x6cff, 0xcc15, 0x21, 0 - .dw 0x6d01, 0xcc15, 0x6d01, 0xcc15, 0x21, 0 - .dw 0x6d03, 0xcc15, 0x6d0f, 0xcc15, 0x21, 0 - .dw 0x6d11, 0xcc15, 0x6d11, 0xcc15, 0x21, 0 - .dw 0x6d13, 0xcc15, 0x6d3f, 0xcc15, 0x21, 0 - .dw 0x6d41, 0xcc15, 0x6d41, 0xcc15, 0x21, 0 - .dw 0x6d43, 0xcc15, 0x6d4f, 0xcc15, 0x21, 0 - .dw 0x6d51, 0xcc15, 0x6d51, 0xcc15, 0x21, 0 - .dw 0x6d53, 0xcc15, 0x6d7f, 0xcc15, 0x21, 0 - .dw 0x6d80, 0xcc15, 0x6d80, 0xcc15, 0x22, 0 - .dw 0x6d81, 0xcc15, 0x6d81, 0xcc15, 0x21, 0 - .dw 0x6d82, 0xcc15, 0x6d82, 0xcc15, 0x22, 0 - .dw 0x6d83, 0xcc15, 0x6d8f, 0xcc15, 0x21, 0 - .dw 0x6d90, 0xcc15, 0x6d90, 0xcc15, 0x22, 0 - .dw 0x6d91, 0xcc15, 0x6d91, 0xcc15, 0x21, 0 - .dw 0x6d92, 0xcc15, 0x6d92, 0xcc15, 0x22, 0 - .dw 0x6d93, 0xcc15, 0x6dbf, 0xcc15, 0x21, 0 - .dw 0x6dc1, 0xcc15, 0x6dc1, 0xcc15, 0x21, 0 - .dw 0x6dc3, 0xcc15, 0x6dcf, 0xcc15, 0x21, 0 - .dw 0x6dd1, 0xcc15, 0x6dd1, 0xcc15, 0x21, 0 - .dw 0x6dd3, 0xcc15, 0x6dff, 0xcc15, 0x21, 0 - .dw 0x6e01, 0xcc15, 0x6e01, 0xcc15, 0x21, 0 - .dw 0x6e03, 0xcc15, 0x6e0f, 0xcc15, 0x21, 0 - .dw 0x6e11, 0xcc15, 0x6e11, 0xcc15, 0x21, 0 - .dw 0x6e13, 0xcc15, 0x6e3f, 0xcc15, 0x21, 0 - .dw 0x6e41, 0xcc15, 0x6e41, 0xcc15, 0x21, 0 - .dw 0x6e43, 0xcc15, 0x6e4f, 0xcc15, 0x21, 0 - .dw 0x6e51, 0xcc15, 0x6e51, 0xcc15, 0x21, 0 - .dw 0x6e53, 0xcc15, 0x6e7f, 0xcc15, 0x21, 0 - .dw 0x6e81, 0xcc15, 0x6e81, 0xcc15, 0x21, 0 - .dw 0x6e83, 0xcc15, 0x6e8f, 0xcc15, 0x21, 0 - .dw 0x6e91, 0xcc15, 0x6e91, 0xcc15, 0x21, 0 - .dw 0x6e93, 0xcc15, 0x6ebf, 0xcc15, 0x21, 0 - .dw 0x6ec1, 0xcc15, 0x6ec1, 0xcc15, 0x21, 0 - .dw 0x6ec3, 0xcc15, 0x6ecf, 0xcc15, 0x21, 0 - .dw 0x6ed1, 0xcc15, 0x6ed1, 0xcc15, 0x21, 0 - .dw 0x6ed3, 0xcc15, 0x6eff, 0xcc15, 0x21, 0 - .dw 0x6f01, 0xcc15, 0x6f01, 0xcc15, 0x21, 0 - .dw 0x6f03, 0xcc15, 0x6f0f, 0xcc15, 0x21, 0 - .dw 0x6f11, 0xcc15, 0x6f11, 0xcc15, 0x21, 0 - .dw 0x6f13, 0xcc15, 0x6f3f, 0xcc15, 0x21, 0 - .dw 0x6f41, 0xcc15, 0x6f41, 0xcc15, 0x21, 0 - .dw 0x6f43, 0xcc15, 0x6f4f, 0xcc15, 0x21, 0 - .dw 0x6f51, 0xcc15, 0x6f51, 0xcc15, 0x21, 0 - .dw 0x6f53, 0xcc15, 0x6f7f, 0xcc15, 0x21, 0 - .dw 0x6f81, 0xcc15, 0x6f81, 0xcc15, 0x21, 0 - .dw 0x6f83, 0xcc15, 0x6f8f, 0xcc15, 0x21, 0 - .dw 0x6f91, 0xcc15, 0x6f91, 0xcc15, 0x21, 0 - .dw 0x6f93, 0xcc15, 0x6fbf, 0xcc15, 0x21, 0 - .dw 0x6fc0, 0xcc15, 0x6fc0, 0xcc15, 0x22, 0 - .dw 0x6fc1, 0xcc15, 0x6fc1, 0xcc15, 0x21, 0 - .dw 0x6fc2, 0xcc15, 0x6fc2, 0xcc15, 0x22, 0 - .dw 0x6fc3, 0xcc15, 0x6fcf, 0xcc15, 0x21, 0 - .dw 0x6fd0, 0xcc15, 0x6fd0, 0xcc15, 0x22, 0 - .dw 0x6fd1, 0xcc15, 0x6fd1, 0xcc15, 0x21, 0 - .dw 0x6fd2, 0xcc15, 0x6fd2, 0xcc15, 0x22, 0 - .dw 0x6fd3, 0xcc15, 0xffff, 0xcc15, 0x21, 0 - .dw 0x0001, 0xcc16, 0x0001, 0xcc16, 0x21, 0 - .dw 0x0003, 0xcc16, 0x000f, 0xcc16, 0x21, 0 - .dw 0x0011, 0xcc16, 0x0011, 0xcc16, 0x21, 0 - .dw 0x0013, 0xcc16, 0x003f, 0xcc16, 0x21, 0 - .dw 0x0041, 0xcc16, 0x0041, 0xcc16, 0x21, 0 - .dw 0x0043, 0xcc16, 0x004f, 0xcc16, 0x21, 0 - .dw 0x0051, 0xcc16, 0x0051, 0xcc16, 0x21, 0 - .dw 0x0053, 0xcc16, 0x007f, 0xcc16, 0x21, 0 - .dw 0x0081, 0xcc16, 0x0081, 0xcc16, 0x21, 0 - .dw 0x0083, 0xcc16, 0x008f, 0xcc16, 0x21, 0 - .dw 0x0091, 0xcc16, 0x0091, 0xcc16, 0x21, 0 - .dw 0x0093, 0xcc16, 0x00bf, 0xcc16, 0x21, 0 - .dw 0x00c1, 0xcc16, 0x00c1, 0xcc16, 0x21, 0 - .dw 0x00c3, 0xcc16, 0x00cf, 0xcc16, 0x21, 0 - .dw 0x00d1, 0xcc16, 0x00d1, 0xcc16, 0x21, 0 - .dw 0x00d3, 0xcc16, 0x00ff, 0xcc16, 0x21, 0 - .dw 0x0101, 0xcc16, 0x0101, 0xcc16, 0x21, 0 - .dw 0x0103, 0xcc16, 0x010f, 0xcc16, 0x21, 0 - .dw 0x0111, 0xcc16, 0x0111, 0xcc16, 0x21, 0 - .dw 0x0113, 0xcc16, 0x013f, 0xcc16, 0x21, 0 - .dw 0x0141, 0xcc16, 0x0141, 0xcc16, 0x21, 0 - .dw 0x0143, 0xcc16, 0x014f, 0xcc16, 0x21, 0 - .dw 0x0151, 0xcc16, 0x0151, 0xcc16, 0x21, 0 - .dw 0x0153, 0xcc16, 0x017f, 0xcc16, 0x21, 0 - .dw 0x0181, 0xcc16, 0x0181, 0xcc16, 0x21, 0 - .dw 0x0183, 0xcc16, 0x018f, 0xcc16, 0x21, 0 - .dw 0x0191, 0xcc16, 0x0191, 0xcc16, 0x21, 0 - .dw 0x0193, 0xcc16, 0x01bf, 0xcc16, 0x21, 0 - .dw 0x01c1, 0xcc16, 0x01c1, 0xcc16, 0x21, 0 - .dw 0x01c3, 0xcc16, 0x01cf, 0xcc16, 0x21, 0 - .dw 0x01d1, 0xcc16, 0x01d1, 0xcc16, 0x21, 0 - .dw 0x01d3, 0xcc16, 0x01ff, 0xcc16, 0x21, 0 - .dw 0x0201, 0xcc16, 0x0201, 0xcc16, 0x21, 0 - .dw 0x0203, 0xcc16, 0x020f, 0xcc16, 0x21, 0 - .dw 0x0211, 0xcc16, 0x0211, 0xcc16, 0x21, 0 - .dw 0x0213, 0xcc16, 0x023f, 0xcc16, 0x21, 0 - .dw 0x0241, 0xcc16, 0x0241, 0xcc16, 0x21, 0 - .dw 0x0243, 0xcc16, 0x024f, 0xcc16, 0x21, 0 - .dw 0x0251, 0xcc16, 0x0251, 0xcc16, 0x21, 0 - .dw 0x0253, 0xcc16, 0x027f, 0xcc16, 0x21, 0 - .dw 0x0281, 0xcc16, 0x0281, 0xcc16, 0x21, 0 - .dw 0x0283, 0xcc16, 0x028f, 0xcc16, 0x21, 0 - .dw 0x0291, 0xcc16, 0x0291, 0xcc16, 0x21, 0 - .dw 0x0293, 0xcc16, 0x02bf, 0xcc16, 0x21, 0 - .dw 0x02c1, 0xcc16, 0x02c1, 0xcc16, 0x21, 0 - .dw 0x02c3, 0xcc16, 0x02cf, 0xcc16, 0x21, 0 - .dw 0x02d1, 0xcc16, 0x02d1, 0xcc16, 0x21, 0 - .dw 0x02d3, 0xcc16, 0x02ff, 0xcc16, 0x21, 0 - .dw 0x0301, 0xcc16, 0x0301, 0xcc16, 0x21, 0 - .dw 0x0303, 0xcc16, 0x030f, 0xcc16, 0x21, 0 - .dw 0x0311, 0xcc16, 0x0311, 0xcc16, 0x21, 0 - .dw 0x0313, 0xcc16, 0x033f, 0xcc16, 0x21, 0 - .dw 0x0341, 0xcc16, 0x0341, 0xcc16, 0x21, 0 - .dw 0x0343, 0xcc16, 0x034f, 0xcc16, 0x21, 0 - .dw 0x0351, 0xcc16, 0x0351, 0xcc16, 0x21, 0 - .dw 0x0353, 0xcc16, 0x037f, 0xcc16, 0x21, 0 - .dw 0x0381, 0xcc16, 0x0381, 0xcc16, 0x21, 0 - .dw 0x0383, 0xcc16, 0x038f, 0xcc16, 0x21, 0 - .dw 0x0391, 0xcc16, 0x0391, 0xcc16, 0x21, 0 - .dw 0x0393, 0xcc16, 0x03bf, 0xcc16, 0x21, 0 - .dw 0x03c1, 0xcc16, 0x03c1, 0xcc16, 0x21, 0 - .dw 0x03c3, 0xcc16, 0x03cf, 0xcc16, 0x21, 0 - .dw 0x03d1, 0xcc16, 0x03d1, 0xcc16, 0x21, 0 - .dw 0x03d3, 0xcc16, 0x03ff, 0xcc16, 0x21, 0 - .dw 0x0401, 0xcc16, 0x0401, 0xcc16, 0x21, 0 - .dw 0x0403, 0xcc16, 0x040f, 0xcc16, 0x21, 0 - .dw 0x0411, 0xcc16, 0x0411, 0xcc16, 0x21, 0 - .dw 0x0413, 0xcc16, 0x043f, 0xcc16, 0x21, 0 - .dw 0x0441, 0xcc16, 0x0441, 0xcc16, 0x21, 0 - .dw 0x0443, 0xcc16, 0x044f, 0xcc16, 0x21, 0 - .dw 0x0451, 0xcc16, 0x0451, 0xcc16, 0x21, 0 - .dw 0x0453, 0xcc16, 0x047f, 0xcc16, 0x21, 0 - .dw 0x0481, 0xcc16, 0x0481, 0xcc16, 0x21, 0 - .dw 0x0483, 0xcc16, 0x048f, 0xcc16, 0x21, 0 - .dw 0x0491, 0xcc16, 0x0491, 0xcc16, 0x21, 0 - .dw 0x0493, 0xcc16, 0x04bf, 0xcc16, 0x21, 0 - .dw 0x04c1, 0xcc16, 0x04c1, 0xcc16, 0x21, 0 - .dw 0x04c3, 0xcc16, 0x04cf, 0xcc16, 0x21, 0 - .dw 0x04d1, 0xcc16, 0x04d1, 0xcc16, 0x21, 0 - .dw 0x04d3, 0xcc16, 0x04ff, 0xcc16, 0x21, 0 - .dw 0x0501, 0xcc16, 0x0501, 0xcc16, 0x21, 0 - .dw 0x0503, 0xcc16, 0x050f, 0xcc16, 0x21, 0 - .dw 0x0511, 0xcc16, 0x0511, 0xcc16, 0x21, 0 - .dw 0x0513, 0xcc16, 0x053f, 0xcc16, 0x21, 0 - .dw 0x0541, 0xcc16, 0x0541, 0xcc16, 0x21, 0 - .dw 0x0543, 0xcc16, 0x054f, 0xcc16, 0x21, 0 - .dw 0x0551, 0xcc16, 0x0551, 0xcc16, 0x21, 0 - .dw 0x0553, 0xcc16, 0x057f, 0xcc16, 0x21, 0 - .dw 0x0581, 0xcc16, 0x0581, 0xcc16, 0x21, 0 - .dw 0x0583, 0xcc16, 0x058f, 0xcc16, 0x21, 0 - .dw 0x0591, 0xcc16, 0x0591, 0xcc16, 0x21, 0 - .dw 0x0593, 0xcc16, 0x05bf, 0xcc16, 0x21, 0 - .dw 0x05c1, 0xcc16, 0x05c1, 0xcc16, 0x21, 0 - .dw 0x05c3, 0xcc16, 0x05cf, 0xcc16, 0x21, 0 - .dw 0x05d1, 0xcc16, 0x05d1, 0xcc16, 0x21, 0 - .dw 0x05d3, 0xcc16, 0x05ff, 0xcc16, 0x21, 0 - .dw 0x0601, 0xcc16, 0x0601, 0xcc16, 0x21, 0 - .dw 0x0603, 0xcc16, 0x060f, 0xcc16, 0x21, 0 - .dw 0x0611, 0xcc16, 0x0611, 0xcc16, 0x21, 0 - .dw 0x0613, 0xcc16, 0x063f, 0xcc16, 0x21, 0 - .dw 0x0641, 0xcc16, 0x0641, 0xcc16, 0x21, 0 - .dw 0x0643, 0xcc16, 0x064f, 0xcc16, 0x21, 0 - .dw 0x0651, 0xcc16, 0x0651, 0xcc16, 0x21, 0 - .dw 0x0653, 0xcc16, 0x067f, 0xcc16, 0x21, 0 - .dw 0x0681, 0xcc16, 0x0681, 0xcc16, 0x21, 0 - .dw 0x0683, 0xcc16, 0x068f, 0xcc16, 0x21, 0 - .dw 0x0691, 0xcc16, 0x0691, 0xcc16, 0x21, 0 - .dw 0x0693, 0xcc16, 0x06bf, 0xcc16, 0x21, 0 - .dw 0x06c1, 0xcc16, 0x06c1, 0xcc16, 0x21, 0 - .dw 0x06c3, 0xcc16, 0x06cf, 0xcc16, 0x21, 0 - .dw 0x06d1, 0xcc16, 0x06d1, 0xcc16, 0x21, 0 - .dw 0x06d3, 0xcc16, 0x06ff, 0xcc16, 0x21, 0 - .dw 0x0701, 0xcc16, 0x0701, 0xcc16, 0x21, 0 - .dw 0x0703, 0xcc16, 0x070f, 0xcc16, 0x21, 0 - .dw 0x0711, 0xcc16, 0x0711, 0xcc16, 0x21, 0 - .dw 0x0713, 0xcc16, 0x073f, 0xcc16, 0x21, 0 - .dw 0x0741, 0xcc16, 0x0741, 0xcc16, 0x21, 0 - .dw 0x0743, 0xcc16, 0x074f, 0xcc16, 0x21, 0 - .dw 0x0751, 0xcc16, 0x0751, 0xcc16, 0x21, 0 - .dw 0x0753, 0xcc16, 0x077f, 0xcc16, 0x21, 0 - .dw 0x0781, 0xcc16, 0x0781, 0xcc16, 0x21, 0 - .dw 0x0783, 0xcc16, 0x078f, 0xcc16, 0x21, 0 - .dw 0x0791, 0xcc16, 0x0791, 0xcc16, 0x21, 0 - .dw 0x0793, 0xcc16, 0x07bf, 0xcc16, 0x21, 0 - .dw 0x07c1, 0xcc16, 0x07c1, 0xcc16, 0x21, 0 - .dw 0x07c3, 0xcc16, 0x07cf, 0xcc16, 0x21, 0 - .dw 0x07d1, 0xcc16, 0x07d1, 0xcc16, 0x21, 0 - .dw 0x07d3, 0xcc16, 0x07ff, 0xcc16, 0x21, 0 - .dw 0x0801, 0xcc16, 0x0801, 0xcc16, 0x21, 0 - .dw 0x0803, 0xcc16, 0x080f, 0xcc16, 0x21, 0 - .dw 0x0811, 0xcc16, 0x0811, 0xcc16, 0x21, 0 - .dw 0x0813, 0xcc16, 0x083f, 0xcc16, 0x21, 0 - .dw 0x0841, 0xcc16, 0x0841, 0xcc16, 0x21, 0 - .dw 0x0843, 0xcc16, 0x084f, 0xcc16, 0x21, 0 - .dw 0x0851, 0xcc16, 0x0851, 0xcc16, 0x21, 0 - .dw 0x0853, 0xcc16, 0x087f, 0xcc16, 0x21, 0 - .dw 0x0881, 0xcc16, 0x0881, 0xcc16, 0x21, 0 - .dw 0x0883, 0xcc16, 0x088f, 0xcc16, 0x21, 0 - .dw 0x0891, 0xcc16, 0x0891, 0xcc16, 0x21, 0 - .dw 0x0893, 0xcc16, 0x08bf, 0xcc16, 0x21, 0 - .dw 0x08c1, 0xcc16, 0x08c1, 0xcc16, 0x21, 0 - .dw 0x08c3, 0xcc16, 0x08cf, 0xcc16, 0x21, 0 - .dw 0x08d1, 0xcc16, 0x08d1, 0xcc16, 0x21, 0 - .dw 0x08d3, 0xcc16, 0x08ff, 0xcc16, 0x21, 0 - .dw 0x0901, 0xcc16, 0x0901, 0xcc16, 0x21, 0 - .dw 0x0903, 0xcc16, 0x090f, 0xcc16, 0x21, 0 - .dw 0x0911, 0xcc16, 0x0911, 0xcc16, 0x21, 0 - .dw 0x0913, 0xcc16, 0x093f, 0xcc16, 0x21, 0 - .dw 0x0941, 0xcc16, 0x0941, 0xcc16, 0x21, 0 - .dw 0x0943, 0xcc16, 0x094f, 0xcc16, 0x21, 0 - .dw 0x0951, 0xcc16, 0x0951, 0xcc16, 0x21, 0 - .dw 0x0953, 0xcc16, 0x097f, 0xcc16, 0x21, 0 - .dw 0x0981, 0xcc16, 0x0981, 0xcc16, 0x21, 0 - .dw 0x0983, 0xcc16, 0x098f, 0xcc16, 0x21, 0 - .dw 0x0991, 0xcc16, 0x0991, 0xcc16, 0x21, 0 - .dw 0x0993, 0xcc16, 0x09bf, 0xcc16, 0x21, 0 - .dw 0x09c1, 0xcc16, 0x09c1, 0xcc16, 0x21, 0 - .dw 0x09c3, 0xcc16, 0x09cf, 0xcc16, 0x21, 0 - .dw 0x09d1, 0xcc16, 0x09d1, 0xcc16, 0x21, 0 - .dw 0x09d3, 0xcc16, 0x09ff, 0xcc16, 0x21, 0 - .dw 0x0a01, 0xcc16, 0x0a01, 0xcc16, 0x21, 0 - .dw 0x0a03, 0xcc16, 0x0a0f, 0xcc16, 0x21, 0 - .dw 0x0a11, 0xcc16, 0x0a11, 0xcc16, 0x21, 0 - .dw 0x0a13, 0xcc16, 0x0a3f, 0xcc16, 0x21, 0 - .dw 0x0a41, 0xcc16, 0x0a41, 0xcc16, 0x21, 0 - .dw 0x0a43, 0xcc16, 0x0a4f, 0xcc16, 0x21, 0 - .dw 0x0a51, 0xcc16, 0x0a51, 0xcc16, 0x21, 0 - .dw 0x0a53, 0xcc16, 0x0a7f, 0xcc16, 0x21, 0 - .dw 0x0a81, 0xcc16, 0x0a81, 0xcc16, 0x21, 0 - .dw 0x0a83, 0xcc16, 0x0a8f, 0xcc16, 0x21, 0 - .dw 0x0a91, 0xcc16, 0x0a91, 0xcc16, 0x21, 0 - .dw 0x0a93, 0xcc16, 0x0abf, 0xcc16, 0x21, 0 - .dw 0x0ac1, 0xcc16, 0x0ac1, 0xcc16, 0x21, 0 - .dw 0x0ac3, 0xcc16, 0x0acf, 0xcc16, 0x21, 0 - .dw 0x0ad1, 0xcc16, 0x0ad1, 0xcc16, 0x21, 0 - .dw 0x0ad3, 0xcc16, 0x0aff, 0xcc16, 0x21, 0 - .dw 0x0b01, 0xcc16, 0x0b01, 0xcc16, 0x21, 0 - .dw 0x0b03, 0xcc16, 0x0b0f, 0xcc16, 0x21, 0 - .dw 0x0b11, 0xcc16, 0x0b11, 0xcc16, 0x21, 0 - .dw 0x0b13, 0xcc16, 0x0b3f, 0xcc16, 0x21, 0 - .dw 0x0b41, 0xcc16, 0x0b41, 0xcc16, 0x21, 0 - .dw 0x0b43, 0xcc16, 0x0b4f, 0xcc16, 0x21, 0 - .dw 0x0b51, 0xcc16, 0x0b51, 0xcc16, 0x21, 0 - .dw 0x0b53, 0xcc16, 0x0b7f, 0xcc16, 0x21, 0 - .dw 0x0b81, 0xcc16, 0x0b81, 0xcc16, 0x21, 0 - .dw 0x0b83, 0xcc16, 0x0b8f, 0xcc16, 0x21, 0 - .dw 0x0b91, 0xcc16, 0x0b91, 0xcc16, 0x21, 0 - .dw 0x0b93, 0xcc16, 0x0bbf, 0xcc16, 0x21, 0 - .dw 0x0bc1, 0xcc16, 0x0bc1, 0xcc16, 0x21, 0 - .dw 0x0bc3, 0xcc16, 0x0bcf, 0xcc16, 0x21, 0 - .dw 0x0bd1, 0xcc16, 0x0bd1, 0xcc16, 0x21, 0 - .dw 0x0bd3, 0xcc16, 0x0bff, 0xcc16, 0x21, 0 - .dw 0x0c01, 0xcc16, 0x0c01, 0xcc16, 0x21, 0 - .dw 0x0c03, 0xcc16, 0x0c0f, 0xcc16, 0x21, 0 - .dw 0x0c11, 0xcc16, 0x0c11, 0xcc16, 0x21, 0 - .dw 0x0c13, 0xcc16, 0x0c3f, 0xcc16, 0x21, 0 - .dw 0x0c41, 0xcc16, 0x0c41, 0xcc16, 0x21, 0 - .dw 0x0c43, 0xcc16, 0x0c4f, 0xcc16, 0x21, 0 - .dw 0x0c51, 0xcc16, 0x0c51, 0xcc16, 0x21, 0 - .dw 0x0c53, 0xcc16, 0x0c7f, 0xcc16, 0x21, 0 - .dw 0x0c81, 0xcc16, 0x0c81, 0xcc16, 0x21, 0 - .dw 0x0c83, 0xcc16, 0x0c8f, 0xcc16, 0x21, 0 - .dw 0x0c91, 0xcc16, 0x0c91, 0xcc16, 0x21, 0 - .dw 0x0c93, 0xcc16, 0x0cbf, 0xcc16, 0x21, 0 - .dw 0x0cc1, 0xcc16, 0x0cc1, 0xcc16, 0x21, 0 - .dw 0x0cc3, 0xcc16, 0x0ccf, 0xcc16, 0x21, 0 - .dw 0x0cd1, 0xcc16, 0x0cd1, 0xcc16, 0x21, 0 - .dw 0x0cd3, 0xcc16, 0x0cff, 0xcc16, 0x21, 0 - .dw 0x0d01, 0xcc16, 0x0d01, 0xcc16, 0x21, 0 - .dw 0x0d03, 0xcc16, 0x0d0f, 0xcc16, 0x21, 0 - .dw 0x0d11, 0xcc16, 0x0d11, 0xcc16, 0x21, 0 - .dw 0x0d13, 0xcc16, 0x0d3f, 0xcc16, 0x21, 0 - .dw 0x0d41, 0xcc16, 0x0d41, 0xcc16, 0x21, 0 - .dw 0x0d43, 0xcc16, 0x0d4f, 0xcc16, 0x21, 0 - .dw 0x0d51, 0xcc16, 0x0d51, 0xcc16, 0x21, 0 - .dw 0x0d53, 0xcc16, 0x0d7f, 0xcc16, 0x21, 0 - .dw 0x0d81, 0xcc16, 0x0d81, 0xcc16, 0x21, 0 - .dw 0x0d83, 0xcc16, 0x0d8f, 0xcc16, 0x21, 0 - .dw 0x0d91, 0xcc16, 0x0d91, 0xcc16, 0x21, 0 - .dw 0x0d93, 0xcc16, 0x0dbf, 0xcc16, 0x21, 0 - .dw 0x0dc1, 0xcc16, 0x0dc1, 0xcc16, 0x21, 0 - .dw 0x0dc3, 0xcc16, 0x0dcf, 0xcc16, 0x21, 0 - .dw 0x0dd1, 0xcc16, 0x0dd1, 0xcc16, 0x21, 0 - .dw 0x0dd3, 0xcc16, 0x0dff, 0xcc16, 0x21, 0 - .dw 0x0e01, 0xcc16, 0x0e01, 0xcc16, 0x21, 0 - .dw 0x0e03, 0xcc16, 0x0e0f, 0xcc16, 0x21, 0 - .dw 0x0e11, 0xcc16, 0x0e11, 0xcc16, 0x21, 0 - .dw 0x0e13, 0xcc16, 0x0e3f, 0xcc16, 0x21, 0 - .dw 0x0e41, 0xcc16, 0x0e41, 0xcc16, 0x21, 0 - .dw 0x0e43, 0xcc16, 0x0e4f, 0xcc16, 0x21, 0 - .dw 0x0e51, 0xcc16, 0x0e51, 0xcc16, 0x21, 0 - .dw 0x0e53, 0xcc16, 0x0e7f, 0xcc16, 0x21, 0 - .dw 0x0e81, 0xcc16, 0x0e81, 0xcc16, 0x21, 0 - .dw 0x0e83, 0xcc16, 0x0e8f, 0xcc16, 0x21, 0 - .dw 0x0e91, 0xcc16, 0x0e91, 0xcc16, 0x21, 0 - .dw 0x0e93, 0xcc16, 0x0ebf, 0xcc16, 0x21, 0 - .dw 0x0ec1, 0xcc16, 0x0ec1, 0xcc16, 0x21, 0 - .dw 0x0ec3, 0xcc16, 0x0ecf, 0xcc16, 0x21, 0 - .dw 0x0ed1, 0xcc16, 0x0ed1, 0xcc16, 0x21, 0 - .dw 0x0ed3, 0xcc16, 0x0eff, 0xcc16, 0x21, 0 - .dw 0x0f01, 0xcc16, 0x0f01, 0xcc16, 0x21, 0 - .dw 0x0f03, 0xcc16, 0x0f0f, 0xcc16, 0x21, 0 - .dw 0x0f11, 0xcc16, 0x0f11, 0xcc16, 0x21, 0 - .dw 0x0f13, 0xcc16, 0x0f3f, 0xcc16, 0x21, 0 - .dw 0x0f41, 0xcc16, 0x0f41, 0xcc16, 0x21, 0 - .dw 0x0f43, 0xcc16, 0x0f4f, 0xcc16, 0x21, 0 - .dw 0x0f51, 0xcc16, 0x0f51, 0xcc16, 0x21, 0 - .dw 0x0f53, 0xcc16, 0x0f7f, 0xcc16, 0x21, 0 - .dw 0x0f81, 0xcc16, 0x0f81, 0xcc16, 0x21, 0 - .dw 0x0f83, 0xcc16, 0x0f8f, 0xcc16, 0x21, 0 - .dw 0x0f91, 0xcc16, 0x0f91, 0xcc16, 0x21, 0 - .dw 0x0f93, 0xcc16, 0x0fbf, 0xcc16, 0x21, 0 - .dw 0x0fc1, 0xcc16, 0x0fc1, 0xcc16, 0x21, 0 - .dw 0x0fc3, 0xcc16, 0x0fcf, 0xcc16, 0x21, 0 - .dw 0x0fd1, 0xcc16, 0x0fd1, 0xcc16, 0x21, 0 - .dw 0x0fd3, 0xcc16, 0x1fff, 0xcc16, 0x21, 0 - .dw 0x2001, 0xcc16, 0x2001, 0xcc16, 0x21, 0 - .dw 0x2003, 0xcc16, 0x200f, 0xcc16, 0x21, 0 - .dw 0x2011, 0xcc16, 0x2011, 0xcc16, 0x21, 0 - .dw 0x2013, 0xcc16, 0x203f, 0xcc16, 0x21, 0 - .dw 0x2041, 0xcc16, 0x2041, 0xcc16, 0x21, 0 - .dw 0x2043, 0xcc16, 0x204f, 0xcc16, 0x21, 0 - .dw 0x2051, 0xcc16, 0x2051, 0xcc16, 0x21, 0 - .dw 0x2053, 0xcc16, 0x207f, 0xcc16, 0x21, 0 - .dw 0x2081, 0xcc16, 0x2081, 0xcc16, 0x21, 0 - .dw 0x2083, 0xcc16, 0x208f, 0xcc16, 0x21, 0 - .dw 0x2091, 0xcc16, 0x2091, 0xcc16, 0x21, 0 - .dw 0x2093, 0xcc16, 0x20bf, 0xcc16, 0x21, 0 - .dw 0x20c1, 0xcc16, 0x20c1, 0xcc16, 0x21, 0 - .dw 0x20c3, 0xcc16, 0x20cf, 0xcc16, 0x21, 0 - .dw 0x20d1, 0xcc16, 0x20d1, 0xcc16, 0x21, 0 - .dw 0x20d3, 0xcc16, 0x20ff, 0xcc16, 0x21, 0 - .dw 0x2101, 0xcc16, 0x2101, 0xcc16, 0x21, 0 - .dw 0x2103, 0xcc16, 0x210f, 0xcc16, 0x21, 0 - .dw 0x2111, 0xcc16, 0x2111, 0xcc16, 0x21, 0 - .dw 0x2113, 0xcc16, 0x213f, 0xcc16, 0x21, 0 - .dw 0x2141, 0xcc16, 0x2141, 0xcc16, 0x21, 0 - .dw 0x2143, 0xcc16, 0x214f, 0xcc16, 0x21, 0 - .dw 0x2151, 0xcc16, 0x2151, 0xcc16, 0x21, 0 - .dw 0x2153, 0xcc16, 0x217f, 0xcc16, 0x21, 0 - .dw 0x2181, 0xcc16, 0x2181, 0xcc16, 0x21, 0 - .dw 0x2183, 0xcc16, 0x218f, 0xcc16, 0x21, 0 - .dw 0x2191, 0xcc16, 0x2191, 0xcc16, 0x21, 0 - .dw 0x2193, 0xcc16, 0x21bf, 0xcc16, 0x21, 0 - .dw 0x21c1, 0xcc16, 0x21c1, 0xcc16, 0x21, 0 - .dw 0x21c3, 0xcc16, 0x21cf, 0xcc16, 0x21, 0 - .dw 0x21d1, 0xcc16, 0x21d1, 0xcc16, 0x21, 0 - .dw 0x21d3, 0xcc16, 0x21ff, 0xcc16, 0x21, 0 - .dw 0x2201, 0xcc16, 0x2201, 0xcc16, 0x21, 0 - .dw 0x2203, 0xcc16, 0x220f, 0xcc16, 0x21, 0 - .dw 0x2211, 0xcc16, 0x2211, 0xcc16, 0x21, 0 - .dw 0x2213, 0xcc16, 0x223f, 0xcc16, 0x21, 0 - .dw 0x2241, 0xcc16, 0x2241, 0xcc16, 0x21, 0 - .dw 0x2243, 0xcc16, 0x224f, 0xcc16, 0x21, 0 - .dw 0x2251, 0xcc16, 0x2251, 0xcc16, 0x21, 0 - .dw 0x2253, 0xcc16, 0x227f, 0xcc16, 0x21, 0 - .dw 0x2281, 0xcc16, 0x2281, 0xcc16, 0x21, 0 - .dw 0x2283, 0xcc16, 0x228f, 0xcc16, 0x21, 0 - .dw 0x2291, 0xcc16, 0x2291, 0xcc16, 0x21, 0 - .dw 0x2293, 0xcc16, 0x22bf, 0xcc16, 0x21, 0 - .dw 0x22c1, 0xcc16, 0x22c1, 0xcc16, 0x21, 0 - .dw 0x22c3, 0xcc16, 0x22cf, 0xcc16, 0x21, 0 - .dw 0x22d1, 0xcc16, 0x22d1, 0xcc16, 0x21, 0 - .dw 0x22d3, 0xcc16, 0x22ff, 0xcc16, 0x21, 0 - .dw 0x2301, 0xcc16, 0x2301, 0xcc16, 0x21, 0 - .dw 0x2303, 0xcc16, 0x230f, 0xcc16, 0x21, 0 - .dw 0x2311, 0xcc16, 0x2311, 0xcc16, 0x21, 0 - .dw 0x2313, 0xcc16, 0x233f, 0xcc16, 0x21, 0 - .dw 0x2341, 0xcc16, 0x2341, 0xcc16, 0x21, 0 - .dw 0x2343, 0xcc16, 0x234f, 0xcc16, 0x21, 0 - .dw 0x2351, 0xcc16, 0x2351, 0xcc16, 0x21, 0 - .dw 0x2353, 0xcc16, 0x237f, 0xcc16, 0x21, 0 - .dw 0x2381, 0xcc16, 0x2381, 0xcc16, 0x21, 0 - .dw 0x2383, 0xcc16, 0x238f, 0xcc16, 0x21, 0 - .dw 0x2391, 0xcc16, 0x2391, 0xcc16, 0x21, 0 - .dw 0x2393, 0xcc16, 0x23bf, 0xcc16, 0x21, 0 - .dw 0x23c1, 0xcc16, 0x23c1, 0xcc16, 0x21, 0 - .dw 0x23c3, 0xcc16, 0x23cf, 0xcc16, 0x21, 0 - .dw 0x23d1, 0xcc16, 0x23d1, 0xcc16, 0x21, 0 - .dw 0x23d3, 0xcc16, 0x23ff, 0xcc16, 0x21, 0 - .dw 0x2401, 0xcc16, 0x2401, 0xcc16, 0x21, 0 - .dw 0x2403, 0xcc16, 0x240f, 0xcc16, 0x21, 0 - .dw 0x2411, 0xcc16, 0x2411, 0xcc16, 0x21, 0 - .dw 0x2413, 0xcc16, 0x243f, 0xcc16, 0x21, 0 - .dw 0x2441, 0xcc16, 0x2441, 0xcc16, 0x21, 0 - .dw 0x2443, 0xcc16, 0x244f, 0xcc16, 0x21, 0 - .dw 0x2451, 0xcc16, 0x2451, 0xcc16, 0x21, 0 - .dw 0x2453, 0xcc16, 0x247f, 0xcc16, 0x21, 0 - .dw 0x2481, 0xcc16, 0x2481, 0xcc16, 0x21, 0 - .dw 0x2483, 0xcc16, 0x248f, 0xcc16, 0x21, 0 - .dw 0x2491, 0xcc16, 0x2491, 0xcc16, 0x21, 0 - .dw 0x2493, 0xcc16, 0x24bf, 0xcc16, 0x21, 0 - .dw 0x24c1, 0xcc16, 0x24c1, 0xcc16, 0x21, 0 - .dw 0x24c3, 0xcc16, 0x24cf, 0xcc16, 0x21, 0 - .dw 0x24d1, 0xcc16, 0x24d1, 0xcc16, 0x21, 0 - .dw 0x24d3, 0xcc16, 0x24ff, 0xcc16, 0x21, 0 - .dw 0x2501, 0xcc16, 0x2501, 0xcc16, 0x21, 0 - .dw 0x2503, 0xcc16, 0x250f, 0xcc16, 0x21, 0 - .dw 0x2511, 0xcc16, 0x2511, 0xcc16, 0x21, 0 - .dw 0x2513, 0xcc16, 0x253f, 0xcc16, 0x21, 0 - .dw 0x2541, 0xcc16, 0x2541, 0xcc16, 0x21, 0 - .dw 0x2543, 0xcc16, 0x254f, 0xcc16, 0x21, 0 - .dw 0x2551, 0xcc16, 0x2551, 0xcc16, 0x21, 0 - .dw 0x2553, 0xcc16, 0x257f, 0xcc16, 0x21, 0 - .dw 0x2581, 0xcc16, 0x2581, 0xcc16, 0x21, 0 - .dw 0x2583, 0xcc16, 0x258f, 0xcc16, 0x21, 0 - .dw 0x2591, 0xcc16, 0x2591, 0xcc16, 0x21, 0 - .dw 0x2593, 0xcc16, 0x25bf, 0xcc16, 0x21, 0 - .dw 0x25c1, 0xcc16, 0x25c1, 0xcc16, 0x21, 0 - .dw 0x25c3, 0xcc16, 0x25cf, 0xcc16, 0x21, 0 - .dw 0x25d1, 0xcc16, 0x25d1, 0xcc16, 0x21, 0 - .dw 0x25d3, 0xcc16, 0x25ff, 0xcc16, 0x21, 0 - .dw 0x2601, 0xcc16, 0x2601, 0xcc16, 0x21, 0 - .dw 0x2603, 0xcc16, 0x260f, 0xcc16, 0x21, 0 - .dw 0x2611, 0xcc16, 0x2611, 0xcc16, 0x21, 0 - .dw 0x2613, 0xcc16, 0x263f, 0xcc16, 0x21, 0 - .dw 0x2641, 0xcc16, 0x2641, 0xcc16, 0x21, 0 - .dw 0x2643, 0xcc16, 0x264f, 0xcc16, 0x21, 0 - .dw 0x2651, 0xcc16, 0x2651, 0xcc16, 0x21, 0 - .dw 0x2653, 0xcc16, 0x267f, 0xcc16, 0x21, 0 - .dw 0x2681, 0xcc16, 0x2681, 0xcc16, 0x21, 0 - .dw 0x2683, 0xcc16, 0x268f, 0xcc16, 0x21, 0 - .dw 0x2691, 0xcc16, 0x2691, 0xcc16, 0x21, 0 - .dw 0x2693, 0xcc16, 0x26bf, 0xcc16, 0x21, 0 - .dw 0x26c1, 0xcc16, 0x26c1, 0xcc16, 0x21, 0 - .dw 0x26c3, 0xcc16, 0x26cf, 0xcc16, 0x21, 0 - .dw 0x26d1, 0xcc16, 0x26d1, 0xcc16, 0x21, 0 - .dw 0x26d3, 0xcc16, 0x26ff, 0xcc16, 0x21, 0 - .dw 0x2701, 0xcc16, 0x2701, 0xcc16, 0x21, 0 - .dw 0x2703, 0xcc16, 0x270f, 0xcc16, 0x21, 0 - .dw 0x2711, 0xcc16, 0x2711, 0xcc16, 0x21, 0 - .dw 0x2713, 0xcc16, 0x273f, 0xcc16, 0x21, 0 - .dw 0x2741, 0xcc16, 0x2741, 0xcc16, 0x21, 0 - .dw 0x2743, 0xcc16, 0x274f, 0xcc16, 0x21, 0 - .dw 0x2751, 0xcc16, 0x2751, 0xcc16, 0x21, 0 - .dw 0x2753, 0xcc16, 0x277f, 0xcc16, 0x21, 0 - .dw 0x2781, 0xcc16, 0x2781, 0xcc16, 0x21, 0 - .dw 0x2783, 0xcc16, 0x278f, 0xcc16, 0x21, 0 - .dw 0x2791, 0xcc16, 0x2791, 0xcc16, 0x21, 0 - .dw 0x2793, 0xcc16, 0x27bf, 0xcc16, 0x21, 0 - .dw 0x27c1, 0xcc16, 0x27c1, 0xcc16, 0x21, 0 - .dw 0x27c3, 0xcc16, 0x27cf, 0xcc16, 0x21, 0 - .dw 0x27d1, 0xcc16, 0x27d1, 0xcc16, 0x21, 0 - .dw 0x27d3, 0xcc16, 0x27ff, 0xcc16, 0x21, 0 - .dw 0x2801, 0xcc16, 0x2801, 0xcc16, 0x21, 0 - .dw 0x2803, 0xcc16, 0x280f, 0xcc16, 0x21, 0 - .dw 0x2811, 0xcc16, 0x2811, 0xcc16, 0x21, 0 - .dw 0x2813, 0xcc16, 0x283f, 0xcc16, 0x21, 0 - .dw 0x2841, 0xcc16, 0x2841, 0xcc16, 0x21, 0 - .dw 0x2843, 0xcc16, 0x284f, 0xcc16, 0x21, 0 - .dw 0x2851, 0xcc16, 0x2851, 0xcc16, 0x21, 0 - .dw 0x2853, 0xcc16, 0x287f, 0xcc16, 0x21, 0 - .dw 0x2881, 0xcc16, 0x2881, 0xcc16, 0x21, 0 - .dw 0x2883, 0xcc16, 0x288f, 0xcc16, 0x21, 0 - .dw 0x2891, 0xcc16, 0x2891, 0xcc16, 0x21, 0 - .dw 0x2893, 0xcc16, 0x28bf, 0xcc16, 0x21, 0 - .dw 0x28c1, 0xcc16, 0x28c1, 0xcc16, 0x21, 0 - .dw 0x28c3, 0xcc16, 0x28cf, 0xcc16, 0x21, 0 - .dw 0x28d1, 0xcc16, 0x28d1, 0xcc16, 0x21, 0 - .dw 0x28d3, 0xcc16, 0x28ff, 0xcc16, 0x21, 0 - .dw 0x2901, 0xcc16, 0x2901, 0xcc16, 0x21, 0 - .dw 0x2903, 0xcc16, 0x290f, 0xcc16, 0x21, 0 - .dw 0x2911, 0xcc16, 0x2911, 0xcc16, 0x21, 0 - .dw 0x2913, 0xcc16, 0x293f, 0xcc16, 0x21, 0 - .dw 0x2941, 0xcc16, 0x2941, 0xcc16, 0x21, 0 - .dw 0x2943, 0xcc16, 0x294f, 0xcc16, 0x21, 0 - .dw 0x2951, 0xcc16, 0x2951, 0xcc16, 0x21, 0 - .dw 0x2953, 0xcc16, 0x297f, 0xcc16, 0x21, 0 - .dw 0x2981, 0xcc16, 0x2981, 0xcc16, 0x21, 0 - .dw 0x2983, 0xcc16, 0x298f, 0xcc16, 0x21, 0 - .dw 0x2991, 0xcc16, 0x2991, 0xcc16, 0x21, 0 - .dw 0x2993, 0xcc16, 0x29bf, 0xcc16, 0x21, 0 - .dw 0x29c1, 0xcc16, 0x29c1, 0xcc16, 0x21, 0 - .dw 0x29c3, 0xcc16, 0x29cf, 0xcc16, 0x21, 0 - .dw 0x29d1, 0xcc16, 0x29d1, 0xcc16, 0x21, 0 - .dw 0x29d3, 0xcc16, 0x29ff, 0xcc16, 0x21, 0 - .dw 0x2a01, 0xcc16, 0x2a01, 0xcc16, 0x21, 0 - .dw 0x2a03, 0xcc16, 0x2a0f, 0xcc16, 0x21, 0 - .dw 0x2a11, 0xcc16, 0x2a11, 0xcc16, 0x21, 0 - .dw 0x2a13, 0xcc16, 0x2a3f, 0xcc16, 0x21, 0 - .dw 0x2a41, 0xcc16, 0x2a41, 0xcc16, 0x21, 0 - .dw 0x2a43, 0xcc16, 0x2a4f, 0xcc16, 0x21, 0 - .dw 0x2a51, 0xcc16, 0x2a51, 0xcc16, 0x21, 0 - .dw 0x2a53, 0xcc16, 0x2a7f, 0xcc16, 0x21, 0 - .dw 0x2a81, 0xcc16, 0x2a81, 0xcc16, 0x21, 0 - .dw 0x2a83, 0xcc16, 0x2a8f, 0xcc16, 0x21, 0 - .dw 0x2a91, 0xcc16, 0x2a91, 0xcc16, 0x21, 0 - .dw 0x2a93, 0xcc16, 0x2abf, 0xcc16, 0x21, 0 - .dw 0x2ac1, 0xcc16, 0x2ac1, 0xcc16, 0x21, 0 - .dw 0x2ac3, 0xcc16, 0x2acf, 0xcc16, 0x21, 0 - .dw 0x2ad1, 0xcc16, 0x2ad1, 0xcc16, 0x21, 0 - .dw 0x2ad3, 0xcc16, 0x2aff, 0xcc16, 0x21, 0 - .dw 0x2b01, 0xcc16, 0x2b01, 0xcc16, 0x21, 0 - .dw 0x2b03, 0xcc16, 0x2b0f, 0xcc16, 0x21, 0 - .dw 0x2b11, 0xcc16, 0x2b11, 0xcc16, 0x21, 0 - .dw 0x2b13, 0xcc16, 0x2b3f, 0xcc16, 0x21, 0 - .dw 0x2b41, 0xcc16, 0x2b41, 0xcc16, 0x21, 0 - .dw 0x2b43, 0xcc16, 0x2b4f, 0xcc16, 0x21, 0 - .dw 0x2b51, 0xcc16, 0x2b51, 0xcc16, 0x21, 0 - .dw 0x2b53, 0xcc16, 0x2b7f, 0xcc16, 0x21, 0 - .dw 0x2b81, 0xcc16, 0x2b81, 0xcc16, 0x21, 0 - .dw 0x2b83, 0xcc16, 0x2b8f, 0xcc16, 0x21, 0 - .dw 0x2b91, 0xcc16, 0x2b91, 0xcc16, 0x21, 0 - .dw 0x2b93, 0xcc16, 0x2bbf, 0xcc16, 0x21, 0 - .dw 0x2bc1, 0xcc16, 0x2bc1, 0xcc16, 0x21, 0 - .dw 0x2bc3, 0xcc16, 0x2bcf, 0xcc16, 0x21, 0 - .dw 0x2bd1, 0xcc16, 0x2bd1, 0xcc16, 0x21, 0 - .dw 0x2bd3, 0xcc16, 0x2bff, 0xcc16, 0x21, 0 - .dw 0x2c01, 0xcc16, 0x2c01, 0xcc16, 0x21, 0 - .dw 0x2c03, 0xcc16, 0x2c0f, 0xcc16, 0x21, 0 - .dw 0x2c11, 0xcc16, 0x2c11, 0xcc16, 0x21, 0 - .dw 0x2c13, 0xcc16, 0x2c3f, 0xcc16, 0x21, 0 - .dw 0x2c41, 0xcc16, 0x2c41, 0xcc16, 0x21, 0 - .dw 0x2c43, 0xcc16, 0x2c4f, 0xcc16, 0x21, 0 - .dw 0x2c51, 0xcc16, 0x2c51, 0xcc16, 0x21, 0 - .dw 0x2c53, 0xcc16, 0x2c7f, 0xcc16, 0x21, 0 - .dw 0x2c81, 0xcc16, 0x2c81, 0xcc16, 0x21, 0 - .dw 0x2c83, 0xcc16, 0x2c8f, 0xcc16, 0x21, 0 - .dw 0x2c91, 0xcc16, 0x2c91, 0xcc16, 0x21, 0 - .dw 0x2c93, 0xcc16, 0x2cbf, 0xcc16, 0x21, 0 - .dw 0x2cc1, 0xcc16, 0x2cc1, 0xcc16, 0x21, 0 - .dw 0x2cc3, 0xcc16, 0x2ccf, 0xcc16, 0x21, 0 - .dw 0x2cd1, 0xcc16, 0x2cd1, 0xcc16, 0x21, 0 - .dw 0x2cd3, 0xcc16, 0x2cff, 0xcc16, 0x21, 0 - .dw 0x2d01, 0xcc16, 0x2d01, 0xcc16, 0x21, 0 - .dw 0x2d03, 0xcc16, 0x2d0f, 0xcc16, 0x21, 0 - .dw 0x2d11, 0xcc16, 0x2d11, 0xcc16, 0x21, 0 - .dw 0x2d13, 0xcc16, 0x2d3f, 0xcc16, 0x21, 0 - .dw 0x2d41, 0xcc16, 0x2d41, 0xcc16, 0x21, 0 - .dw 0x2d43, 0xcc16, 0x2d4f, 0xcc16, 0x21, 0 - .dw 0x2d51, 0xcc16, 0x2d51, 0xcc16, 0x21, 0 - .dw 0x2d53, 0xcc16, 0x2d7f, 0xcc16, 0x21, 0 - .dw 0x2d81, 0xcc16, 0x2d81, 0xcc16, 0x21, 0 - .dw 0x2d83, 0xcc16, 0x2d8f, 0xcc16, 0x21, 0 - .dw 0x2d91, 0xcc16, 0x2d91, 0xcc16, 0x21, 0 - .dw 0x2d93, 0xcc16, 0x2dbf, 0xcc16, 0x21, 0 - .dw 0x2dc1, 0xcc16, 0x2dc1, 0xcc16, 0x21, 0 - .dw 0x2dc3, 0xcc16, 0x2dcf, 0xcc16, 0x21, 0 - .dw 0x2dd1, 0xcc16, 0x2dd1, 0xcc16, 0x21, 0 - .dw 0x2dd3, 0xcc16, 0x2dff, 0xcc16, 0x21, 0 - .dw 0x2e01, 0xcc16, 0x2e01, 0xcc16, 0x21, 0 - .dw 0x2e03, 0xcc16, 0x2e0f, 0xcc16, 0x21, 0 - .dw 0x2e11, 0xcc16, 0x2e11, 0xcc16, 0x21, 0 - .dw 0x2e13, 0xcc16, 0x2e3f, 0xcc16, 0x21, 0 - .dw 0x2e41, 0xcc16, 0x2e41, 0xcc16, 0x21, 0 - .dw 0x2e43, 0xcc16, 0x2e4f, 0xcc16, 0x21, 0 - .dw 0x2e51, 0xcc16, 0x2e51, 0xcc16, 0x21, 0 - .dw 0x2e53, 0xcc16, 0x2e7f, 0xcc16, 0x21, 0 - .dw 0x2e81, 0xcc16, 0x2e81, 0xcc16, 0x21, 0 - .dw 0x2e83, 0xcc16, 0x2e8f, 0xcc16, 0x21, 0 - .dw 0x2e91, 0xcc16, 0x2e91, 0xcc16, 0x21, 0 - .dw 0x2e93, 0xcc16, 0x2ebf, 0xcc16, 0x21, 0 - .dw 0x2ec1, 0xcc16, 0x2ec1, 0xcc16, 0x21, 0 - .dw 0x2ec3, 0xcc16, 0x2ecf, 0xcc16, 0x21, 0 - .dw 0x2ed1, 0xcc16, 0x2ed1, 0xcc16, 0x21, 0 - .dw 0x2ed3, 0xcc16, 0x2eff, 0xcc16, 0x21, 0 - .dw 0x2f01, 0xcc16, 0x2f01, 0xcc16, 0x21, 0 - .dw 0x2f03, 0xcc16, 0x2f0f, 0xcc16, 0x21, 0 - .dw 0x2f11, 0xcc16, 0x2f11, 0xcc16, 0x21, 0 - .dw 0x2f13, 0xcc16, 0x2f3f, 0xcc16, 0x21, 0 - .dw 0x2f41, 0xcc16, 0x2f41, 0xcc16, 0x21, 0 - .dw 0x2f43, 0xcc16, 0x2f4f, 0xcc16, 0x21, 0 - .dw 0x2f51, 0xcc16, 0x2f51, 0xcc16, 0x21, 0 - .dw 0x2f53, 0xcc16, 0x2f7f, 0xcc16, 0x21, 0 - .dw 0x2f81, 0xcc16, 0x2f81, 0xcc16, 0x21, 0 - .dw 0x2f83, 0xcc16, 0x2f8f, 0xcc16, 0x21, 0 - .dw 0x2f91, 0xcc16, 0x2f91, 0xcc16, 0x21, 0 - .dw 0x2f93, 0xcc16, 0x2fbf, 0xcc16, 0x21, 0 - .dw 0x2fc1, 0xcc16, 0x2fc1, 0xcc16, 0x21, 0 - .dw 0x2fc3, 0xcc16, 0x2fcf, 0xcc16, 0x21, 0 - .dw 0x2fd1, 0xcc16, 0x2fd1, 0xcc16, 0x21, 0 - .dw 0x2fd3, 0xcc16, 0x3fff, 0xcc16, 0x21, 0 - .dw 0x4001, 0xcc16, 0x4001, 0xcc16, 0x21, 0 - .dw 0x4003, 0xcc16, 0x400f, 0xcc16, 0x21, 0 - .dw 0x4011, 0xcc16, 0x4011, 0xcc16, 0x21, 0 - .dw 0x4013, 0xcc16, 0x403f, 0xcc16, 0x21, 0 - .dw 0x4041, 0xcc16, 0x4041, 0xcc16, 0x21, 0 - .dw 0x4043, 0xcc16, 0x404f, 0xcc16, 0x21, 0 - .dw 0x4051, 0xcc16, 0x4051, 0xcc16, 0x21, 0 - .dw 0x4053, 0xcc16, 0x407f, 0xcc16, 0x21, 0 - .dw 0x4081, 0xcc16, 0x4081, 0xcc16, 0x21, 0 - .dw 0x4083, 0xcc16, 0x408f, 0xcc16, 0x21, 0 - .dw 0x4091, 0xcc16, 0x4091, 0xcc16, 0x21, 0 - .dw 0x4093, 0xcc16, 0x40bf, 0xcc16, 0x21, 0 - .dw 0x40c1, 0xcc16, 0x40c1, 0xcc16, 0x21, 0 - .dw 0x40c3, 0xcc16, 0x40cf, 0xcc16, 0x21, 0 - .dw 0x40d1, 0xcc16, 0x40d1, 0xcc16, 0x21, 0 - .dw 0x40d3, 0xcc16, 0x40ff, 0xcc16, 0x21, 0 - .dw 0x4101, 0xcc16, 0x4101, 0xcc16, 0x21, 0 - .dw 0x4103, 0xcc16, 0x410f, 0xcc16, 0x21, 0 - .dw 0x4111, 0xcc16, 0x4111, 0xcc16, 0x21, 0 - .dw 0x4113, 0xcc16, 0x413f, 0xcc16, 0x21, 0 - .dw 0x4141, 0xcc16, 0x4141, 0xcc16, 0x21, 0 - .dw 0x4143, 0xcc16, 0x414f, 0xcc16, 0x21, 0 - .dw 0x4151, 0xcc16, 0x4151, 0xcc16, 0x21, 0 - .dw 0x4153, 0xcc16, 0x417f, 0xcc16, 0x21, 0 - .dw 0x4181, 0xcc16, 0x4181, 0xcc16, 0x21, 0 - .dw 0x4183, 0xcc16, 0x418f, 0xcc16, 0x21, 0 - .dw 0x4191, 0xcc16, 0x4191, 0xcc16, 0x21, 0 - .dw 0x4193, 0xcc16, 0x41bf, 0xcc16, 0x21, 0 - .dw 0x41c1, 0xcc16, 0x41c1, 0xcc16, 0x21, 0 - .dw 0x41c3, 0xcc16, 0x41cf, 0xcc16, 0x21, 0 - .dw 0x41d1, 0xcc16, 0x41d1, 0xcc16, 0x21, 0 - .dw 0x41d3, 0xcc16, 0x41ff, 0xcc16, 0x21, 0 - .dw 0x4201, 0xcc16, 0x4201, 0xcc16, 0x21, 0 - .dw 0x4203, 0xcc16, 0x420f, 0xcc16, 0x21, 0 - .dw 0x4211, 0xcc16, 0x4211, 0xcc16, 0x21, 0 - .dw 0x4213, 0xcc16, 0x423f, 0xcc16, 0x21, 0 - .dw 0x4241, 0xcc16, 0x4241, 0xcc16, 0x21, 0 - .dw 0x4243, 0xcc16, 0x424f, 0xcc16, 0x21, 0 - .dw 0x4251, 0xcc16, 0x4251, 0xcc16, 0x21, 0 - .dw 0x4253, 0xcc16, 0x427f, 0xcc16, 0x21, 0 - .dw 0x4281, 0xcc16, 0x4281, 0xcc16, 0x21, 0 - .dw 0x4283, 0xcc16, 0x428f, 0xcc16, 0x21, 0 - .dw 0x4291, 0xcc16, 0x4291, 0xcc16, 0x21, 0 - .dw 0x4293, 0xcc16, 0x42bf, 0xcc16, 0x21, 0 - .dw 0x42c1, 0xcc16, 0x42c1, 0xcc16, 0x21, 0 - .dw 0x42c3, 0xcc16, 0x42cf, 0xcc16, 0x21, 0 - .dw 0x42d1, 0xcc16, 0x42d1, 0xcc16, 0x21, 0 - .dw 0x42d3, 0xcc16, 0x42ff, 0xcc16, 0x21, 0 - .dw 0x4301, 0xcc16, 0x4301, 0xcc16, 0x21, 0 - .dw 0x4303, 0xcc16, 0x430f, 0xcc16, 0x21, 0 - .dw 0x4311, 0xcc16, 0x4311, 0xcc16, 0x21, 0 - .dw 0x4313, 0xcc16, 0x433f, 0xcc16, 0x21, 0 - .dw 0x4341, 0xcc16, 0x4341, 0xcc16, 0x21, 0 - .dw 0x4343, 0xcc16, 0x434f, 0xcc16, 0x21, 0 - .dw 0x4351, 0xcc16, 0x4351, 0xcc16, 0x21, 0 - .dw 0x4353, 0xcc16, 0x437f, 0xcc16, 0x21, 0 - .dw 0x4381, 0xcc16, 0x4381, 0xcc16, 0x21, 0 - .dw 0x4383, 0xcc16, 0x438f, 0xcc16, 0x21, 0 - .dw 0x4391, 0xcc16, 0x4391, 0xcc16, 0x21, 0 - .dw 0x4393, 0xcc16, 0x43bf, 0xcc16, 0x21, 0 - .dw 0x43c1, 0xcc16, 0x43c1, 0xcc16, 0x21, 0 - .dw 0x43c3, 0xcc16, 0x43cf, 0xcc16, 0x21, 0 - .dw 0x43d1, 0xcc16, 0x43d1, 0xcc16, 0x21, 0 - .dw 0x43d3, 0xcc16, 0x43ff, 0xcc16, 0x21, 0 - .dw 0x4401, 0xcc16, 0x4401, 0xcc16, 0x21, 0 - .dw 0x4403, 0xcc16, 0x440f, 0xcc16, 0x21, 0 - .dw 0x4411, 0xcc16, 0x4411, 0xcc16, 0x21, 0 - .dw 0x4413, 0xcc16, 0x443f, 0xcc16, 0x21, 0 - .dw 0x4441, 0xcc16, 0x4441, 0xcc16, 0x21, 0 - .dw 0x4443, 0xcc16, 0x444f, 0xcc16, 0x21, 0 - .dw 0x4451, 0xcc16, 0x4451, 0xcc16, 0x21, 0 - .dw 0x4453, 0xcc16, 0x447f, 0xcc16, 0x21, 0 - .dw 0x4481, 0xcc16, 0x4481, 0xcc16, 0x21, 0 - .dw 0x4483, 0xcc16, 0x448f, 0xcc16, 0x21, 0 - .dw 0x4491, 0xcc16, 0x4491, 0xcc16, 0x21, 0 - .dw 0x4493, 0xcc16, 0x44bf, 0xcc16, 0x21, 0 - .dw 0x44c1, 0xcc16, 0x44c1, 0xcc16, 0x21, 0 - .dw 0x44c3, 0xcc16, 0x44cf, 0xcc16, 0x21, 0 - .dw 0x44d1, 0xcc16, 0x44d1, 0xcc16, 0x21, 0 - .dw 0x44d3, 0xcc16, 0x44ff, 0xcc16, 0x21, 0 - .dw 0x4501, 0xcc16, 0x4501, 0xcc16, 0x21, 0 - .dw 0x4503, 0xcc16, 0x450f, 0xcc16, 0x21, 0 - .dw 0x4511, 0xcc16, 0x4511, 0xcc16, 0x21, 0 - .dw 0x4513, 0xcc16, 0x453f, 0xcc16, 0x21, 0 - .dw 0x4541, 0xcc16, 0x4541, 0xcc16, 0x21, 0 - .dw 0x4543, 0xcc16, 0x454f, 0xcc16, 0x21, 0 - .dw 0x4551, 0xcc16, 0x4551, 0xcc16, 0x21, 0 - .dw 0x4553, 0xcc16, 0x457f, 0xcc16, 0x21, 0 - .dw 0x4581, 0xcc16, 0x4581, 0xcc16, 0x21, 0 - .dw 0x4583, 0xcc16, 0x458f, 0xcc16, 0x21, 0 - .dw 0x4591, 0xcc16, 0x4591, 0xcc16, 0x21, 0 - .dw 0x4593, 0xcc16, 0x45bf, 0xcc16, 0x21, 0 - .dw 0x45c1, 0xcc16, 0x45c1, 0xcc16, 0x21, 0 - .dw 0x45c3, 0xcc16, 0x45cf, 0xcc16, 0x21, 0 - .dw 0x45d1, 0xcc16, 0x45d1, 0xcc16, 0x21, 0 - .dw 0x45d3, 0xcc16, 0x45ff, 0xcc16, 0x21, 0 - .dw 0x4601, 0xcc16, 0x4601, 0xcc16, 0x21, 0 - .dw 0x4603, 0xcc16, 0x460f, 0xcc16, 0x21, 0 - .dw 0x4611, 0xcc16, 0x4611, 0xcc16, 0x21, 0 - .dw 0x4613, 0xcc16, 0x463f, 0xcc16, 0x21, 0 - .dw 0x4641, 0xcc16, 0x4641, 0xcc16, 0x21, 0 - .dw 0x4643, 0xcc16, 0x464f, 0xcc16, 0x21, 0 - .dw 0x4651, 0xcc16, 0x4651, 0xcc16, 0x21, 0 - .dw 0x4653, 0xcc16, 0x467f, 0xcc16, 0x21, 0 - .dw 0x4681, 0xcc16, 0x4681, 0xcc16, 0x21, 0 - .dw 0x4683, 0xcc16, 0x468f, 0xcc16, 0x21, 0 - .dw 0x4691, 0xcc16, 0x4691, 0xcc16, 0x21, 0 - .dw 0x4693, 0xcc16, 0x46bf, 0xcc16, 0x21, 0 - .dw 0x46c1, 0xcc16, 0x46c1, 0xcc16, 0x21, 0 - .dw 0x46c3, 0xcc16, 0x46cf, 0xcc16, 0x21, 0 - .dw 0x46d1, 0xcc16, 0x46d1, 0xcc16, 0x21, 0 - .dw 0x46d3, 0xcc16, 0x46ff, 0xcc16, 0x21, 0 - .dw 0x4701, 0xcc16, 0x4701, 0xcc16, 0x21, 0 - .dw 0x4703, 0xcc16, 0x470f, 0xcc16, 0x21, 0 - .dw 0x4711, 0xcc16, 0x4711, 0xcc16, 0x21, 0 - .dw 0x4713, 0xcc16, 0x473f, 0xcc16, 0x21, 0 - .dw 0x4741, 0xcc16, 0x4741, 0xcc16, 0x21, 0 - .dw 0x4743, 0xcc16, 0x474f, 0xcc16, 0x21, 0 - .dw 0x4751, 0xcc16, 0x4751, 0xcc16, 0x21, 0 - .dw 0x4753, 0xcc16, 0x477f, 0xcc16, 0x21, 0 - .dw 0x4781, 0xcc16, 0x4781, 0xcc16, 0x21, 0 - .dw 0x4783, 0xcc16, 0x478f, 0xcc16, 0x21, 0 - .dw 0x4791, 0xcc16, 0x4791, 0xcc16, 0x21, 0 - .dw 0x4793, 0xcc16, 0x47bf, 0xcc16, 0x21, 0 - .dw 0x47c1, 0xcc16, 0x47c1, 0xcc16, 0x21, 0 - .dw 0x47c3, 0xcc16, 0x47cf, 0xcc16, 0x21, 0 - .dw 0x47d1, 0xcc16, 0x47d1, 0xcc16, 0x21, 0 - .dw 0x47d3, 0xcc16, 0x47ff, 0xcc16, 0x21, 0 - .dw 0x4801, 0xcc16, 0x4801, 0xcc16, 0x21, 0 - .dw 0x4803, 0xcc16, 0x480f, 0xcc16, 0x21, 0 - .dw 0x4811, 0xcc16, 0x4811, 0xcc16, 0x21, 0 - .dw 0x4813, 0xcc16, 0x483f, 0xcc16, 0x21, 0 - .dw 0x4841, 0xcc16, 0x4841, 0xcc16, 0x21, 0 - .dw 0x4843, 0xcc16, 0x484f, 0xcc16, 0x21, 0 - .dw 0x4851, 0xcc16, 0x4851, 0xcc16, 0x21, 0 - .dw 0x4853, 0xcc16, 0x487f, 0xcc16, 0x21, 0 - .dw 0x4881, 0xcc16, 0x4881, 0xcc16, 0x21, 0 - .dw 0x4883, 0xcc16, 0x488f, 0xcc16, 0x21, 0 - .dw 0x4891, 0xcc16, 0x4891, 0xcc16, 0x21, 0 - .dw 0x4893, 0xcc16, 0x48bf, 0xcc16, 0x21, 0 - .dw 0x48c1, 0xcc16, 0x48c1, 0xcc16, 0x21, 0 - .dw 0x48c3, 0xcc16, 0x48cf, 0xcc16, 0x21, 0 - .dw 0x48d1, 0xcc16, 0x48d1, 0xcc16, 0x21, 0 - .dw 0x48d3, 0xcc16, 0x48ff, 0xcc16, 0x21, 0 - .dw 0x4901, 0xcc16, 0x4901, 0xcc16, 0x21, 0 - .dw 0x4903, 0xcc16, 0x490f, 0xcc16, 0x21, 0 - .dw 0x4911, 0xcc16, 0x4911, 0xcc16, 0x21, 0 - .dw 0x4913, 0xcc16, 0x493f, 0xcc16, 0x21, 0 - .dw 0x4941, 0xcc16, 0x4941, 0xcc16, 0x21, 0 - .dw 0x4943, 0xcc16, 0x494f, 0xcc16, 0x21, 0 - .dw 0x4951, 0xcc16, 0x4951, 0xcc16, 0x21, 0 - .dw 0x4953, 0xcc16, 0x497f, 0xcc16, 0x21, 0 - .dw 0x4981, 0xcc16, 0x4981, 0xcc16, 0x21, 0 - .dw 0x4983, 0xcc16, 0x498f, 0xcc16, 0x21, 0 - .dw 0x4991, 0xcc16, 0x4991, 0xcc16, 0x21, 0 - .dw 0x4993, 0xcc16, 0x49bf, 0xcc16, 0x21, 0 - .dw 0x49c1, 0xcc16, 0x49c1, 0xcc16, 0x21, 0 - .dw 0x49c3, 0xcc16, 0x49cf, 0xcc16, 0x21, 0 - .dw 0x49d1, 0xcc16, 0x49d1, 0xcc16, 0x21, 0 - .dw 0x49d3, 0xcc16, 0x49ff, 0xcc16, 0x21, 0 - .dw 0x4a01, 0xcc16, 0x4a01, 0xcc16, 0x21, 0 - .dw 0x4a03, 0xcc16, 0x4a0f, 0xcc16, 0x21, 0 - .dw 0x4a11, 0xcc16, 0x4a11, 0xcc16, 0x21, 0 - .dw 0x4a13, 0xcc16, 0x4a3f, 0xcc16, 0x21, 0 - .dw 0x4a41, 0xcc16, 0x4a41, 0xcc16, 0x21, 0 - .dw 0x4a43, 0xcc16, 0x4a4f, 0xcc16, 0x21, 0 - .dw 0x4a51, 0xcc16, 0x4a51, 0xcc16, 0x21, 0 - .dw 0x4a53, 0xcc16, 0x4a7f, 0xcc16, 0x21, 0 - .dw 0x4a81, 0xcc16, 0x4a81, 0xcc16, 0x21, 0 - .dw 0x4a83, 0xcc16, 0x4a8f, 0xcc16, 0x21, 0 - .dw 0x4a91, 0xcc16, 0x4a91, 0xcc16, 0x21, 0 - .dw 0x4a93, 0xcc16, 0x4abf, 0xcc16, 0x21, 0 - .dw 0x4ac1, 0xcc16, 0x4ac1, 0xcc16, 0x21, 0 - .dw 0x4ac3, 0xcc16, 0x4acf, 0xcc16, 0x21, 0 - .dw 0x4ad1, 0xcc16, 0x4ad1, 0xcc16, 0x21, 0 - .dw 0x4ad3, 0xcc16, 0x4aff, 0xcc16, 0x21, 0 - .dw 0x4b01, 0xcc16, 0x4b01, 0xcc16, 0x21, 0 - .dw 0x4b03, 0xcc16, 0x4b0f, 0xcc16, 0x21, 0 - .dw 0x4b11, 0xcc16, 0x4b11, 0xcc16, 0x21, 0 - .dw 0x4b13, 0xcc16, 0x4b3f, 0xcc16, 0x21, 0 - .dw 0x4b41, 0xcc16, 0x4b41, 0xcc16, 0x21, 0 - .dw 0x4b43, 0xcc16, 0x4b4f, 0xcc16, 0x21, 0 - .dw 0x4b51, 0xcc16, 0x4b51, 0xcc16, 0x21, 0 - .dw 0x4b53, 0xcc16, 0x4b7f, 0xcc16, 0x21, 0 - .dw 0x4b81, 0xcc16, 0x4b81, 0xcc16, 0x21, 0 - .dw 0x4b83, 0xcc16, 0x4b8f, 0xcc16, 0x21, 0 - .dw 0x4b91, 0xcc16, 0x4b91, 0xcc16, 0x21, 0 - .dw 0x4b93, 0xcc16, 0x4bbf, 0xcc16, 0x21, 0 - .dw 0x4bc1, 0xcc16, 0x4bc1, 0xcc16, 0x21, 0 - .dw 0x4bc3, 0xcc16, 0x4bcf, 0xcc16, 0x21, 0 - .dw 0x4bd1, 0xcc16, 0x4bd1, 0xcc16, 0x21, 0 - .dw 0x4bd3, 0xcc16, 0x4bff, 0xcc16, 0x21, 0 - .dw 0x4c01, 0xcc16, 0x4c01, 0xcc16, 0x21, 0 - .dw 0x4c03, 0xcc16, 0x4c0f, 0xcc16, 0x21, 0 - .dw 0x4c11, 0xcc16, 0x4c11, 0xcc16, 0x21, 0 - .dw 0x4c13, 0xcc16, 0x4c3f, 0xcc16, 0x21, 0 - .dw 0x4c41, 0xcc16, 0x4c41, 0xcc16, 0x21, 0 - .dw 0x4c43, 0xcc16, 0x4c4f, 0xcc16, 0x21, 0 - .dw 0x4c51, 0xcc16, 0x4c51, 0xcc16, 0x21, 0 - .dw 0x4c53, 0xcc16, 0x4c7f, 0xcc16, 0x21, 0 - .dw 0x4c81, 0xcc16, 0x4c81, 0xcc16, 0x21, 0 - .dw 0x4c83, 0xcc16, 0x4c8f, 0xcc16, 0x21, 0 - .dw 0x4c91, 0xcc16, 0x4c91, 0xcc16, 0x21, 0 - .dw 0x4c93, 0xcc16, 0x4cbf, 0xcc16, 0x21, 0 - .dw 0x4cc1, 0xcc16, 0x4cc1, 0xcc16, 0x21, 0 - .dw 0x4cc3, 0xcc16, 0x4ccf, 0xcc16, 0x21, 0 - .dw 0x4cd1, 0xcc16, 0x4cd1, 0xcc16, 0x21, 0 - .dw 0x4cd3, 0xcc16, 0x4cff, 0xcc16, 0x21, 0 - .dw 0x4d01, 0xcc16, 0x4d01, 0xcc16, 0x21, 0 - .dw 0x4d03, 0xcc16, 0x4d0f, 0xcc16, 0x21, 0 - .dw 0x4d11, 0xcc16, 0x4d11, 0xcc16, 0x21, 0 - .dw 0x4d13, 0xcc16, 0x4d3f, 0xcc16, 0x21, 0 - .dw 0x4d41, 0xcc16, 0x4d41, 0xcc16, 0x21, 0 - .dw 0x4d43, 0xcc16, 0x4d4f, 0xcc16, 0x21, 0 - .dw 0x4d51, 0xcc16, 0x4d51, 0xcc16, 0x21, 0 - .dw 0x4d53, 0xcc16, 0x4d7f, 0xcc16, 0x21, 0 - .dw 0x4d81, 0xcc16, 0x4d81, 0xcc16, 0x21, 0 - .dw 0x4d83, 0xcc16, 0x4d8f, 0xcc16, 0x21, 0 - .dw 0x4d91, 0xcc16, 0x4d91, 0xcc16, 0x21, 0 - .dw 0x4d93, 0xcc16, 0x4dbf, 0xcc16, 0x21, 0 - .dw 0x4dc1, 0xcc16, 0x4dc1, 0xcc16, 0x21, 0 - .dw 0x4dc3, 0xcc16, 0x4dcf, 0xcc16, 0x21, 0 - .dw 0x4dd1, 0xcc16, 0x4dd1, 0xcc16, 0x21, 0 - .dw 0x4dd3, 0xcc16, 0x4dff, 0xcc16, 0x21, 0 - .dw 0x4e01, 0xcc16, 0x4e01, 0xcc16, 0x21, 0 - .dw 0x4e03, 0xcc16, 0x4e0f, 0xcc16, 0x21, 0 - .dw 0x4e11, 0xcc16, 0x4e11, 0xcc16, 0x21, 0 - .dw 0x4e13, 0xcc16, 0x4e3f, 0xcc16, 0x21, 0 - .dw 0x4e41, 0xcc16, 0x4e41, 0xcc16, 0x21, 0 - .dw 0x4e43, 0xcc16, 0x4e4f, 0xcc16, 0x21, 0 - .dw 0x4e51, 0xcc16, 0x4e51, 0xcc16, 0x21, 0 - .dw 0x4e53, 0xcc16, 0x4e7f, 0xcc16, 0x21, 0 - .dw 0x4e81, 0xcc16, 0x4e81, 0xcc16, 0x21, 0 - .dw 0x4e83, 0xcc16, 0x4e8f, 0xcc16, 0x21, 0 - .dw 0x4e91, 0xcc16, 0x4e91, 0xcc16, 0x21, 0 - .dw 0x4e93, 0xcc16, 0x4ebf, 0xcc16, 0x21, 0 - .dw 0x4ec1, 0xcc16, 0x4ec1, 0xcc16, 0x21, 0 - .dw 0x4ec3, 0xcc16, 0x4ecf, 0xcc16, 0x21, 0 - .dw 0x4ed1, 0xcc16, 0x4ed1, 0xcc16, 0x21, 0 - .dw 0x4ed3, 0xcc16, 0x4eff, 0xcc16, 0x21, 0 - .dw 0x4f01, 0xcc16, 0x4f01, 0xcc16, 0x21, 0 - .dw 0x4f03, 0xcc16, 0x4f0f, 0xcc16, 0x21, 0 - .dw 0x4f11, 0xcc16, 0x4f11, 0xcc16, 0x21, 0 - .dw 0x4f13, 0xcc16, 0x4f3f, 0xcc16, 0x21, 0 - .dw 0x4f41, 0xcc16, 0x4f41, 0xcc16, 0x21, 0 - .dw 0x4f43, 0xcc16, 0x4f4f, 0xcc16, 0x21, 0 - .dw 0x4f51, 0xcc16, 0x4f51, 0xcc16, 0x21, 0 - .dw 0x4f53, 0xcc16, 0x4f7f, 0xcc16, 0x21, 0 - .dw 0x4f81, 0xcc16, 0x4f81, 0xcc16, 0x21, 0 - .dw 0x4f83, 0xcc16, 0x4f8f, 0xcc16, 0x21, 0 - .dw 0x4f91, 0xcc16, 0x4f91, 0xcc16, 0x21, 0 - .dw 0x4f93, 0xcc16, 0x4fbf, 0xcc16, 0x21, 0 - .dw 0x4fc1, 0xcc16, 0x4fc1, 0xcc16, 0x21, 0 - .dw 0x4fc3, 0xcc16, 0x4fcf, 0xcc16, 0x21, 0 - .dw 0x4fd1, 0xcc16, 0x4fd1, 0xcc16, 0x21, 0 - .dw 0x4fd3, 0xcc16, 0x5fff, 0xcc16, 0x21, 0 - .dw 0x6001, 0xcc16, 0x6001, 0xcc16, 0x21, 0 - .dw 0x6003, 0xcc16, 0x600f, 0xcc16, 0x21, 0 - .dw 0x6011, 0xcc16, 0x6011, 0xcc16, 0x21, 0 - .dw 0x6013, 0xcc16, 0x603f, 0xcc16, 0x21, 0 - .dw 0x6041, 0xcc16, 0x6041, 0xcc16, 0x21, 0 - .dw 0x6043, 0xcc16, 0x604f, 0xcc16, 0x21, 0 - .dw 0x6051, 0xcc16, 0x6051, 0xcc16, 0x21, 0 - .dw 0x6053, 0xcc16, 0x607f, 0xcc16, 0x21, 0 - .dw 0x6081, 0xcc16, 0x6081, 0xcc16, 0x21, 0 - .dw 0x6083, 0xcc16, 0x608f, 0xcc16, 0x21, 0 - .dw 0x6091, 0xcc16, 0x6091, 0xcc16, 0x21, 0 - .dw 0x6093, 0xcc16, 0x60bf, 0xcc16, 0x21, 0 - .dw 0x60c1, 0xcc16, 0x60c1, 0xcc16, 0x21, 0 - .dw 0x60c3, 0xcc16, 0x60cf, 0xcc16, 0x21, 0 - .dw 0x60d1, 0xcc16, 0x60d1, 0xcc16, 0x21, 0 - .dw 0x60d3, 0xcc16, 0x60ff, 0xcc16, 0x21, 0 - .dw 0x6101, 0xcc16, 0x6101, 0xcc16, 0x21, 0 - .dw 0x6103, 0xcc16, 0x610f, 0xcc16, 0x21, 0 - .dw 0x6111, 0xcc16, 0x6111, 0xcc16, 0x21, 0 - .dw 0x6113, 0xcc16, 0x613f, 0xcc16, 0x21, 0 - .dw 0x6141, 0xcc16, 0x6141, 0xcc16, 0x21, 0 - .dw 0x6143, 0xcc16, 0x614f, 0xcc16, 0x21, 0 - .dw 0x6151, 0xcc16, 0x6151, 0xcc16, 0x21, 0 - .dw 0x6153, 0xcc16, 0x617f, 0xcc16, 0x21, 0 - .dw 0x6181, 0xcc16, 0x6181, 0xcc16, 0x21, 0 - .dw 0x6183, 0xcc16, 0x618f, 0xcc16, 0x21, 0 - .dw 0x6191, 0xcc16, 0x6191, 0xcc16, 0x21, 0 - .dw 0x6193, 0xcc16, 0x61bf, 0xcc16, 0x21, 0 - .dw 0x61c1, 0xcc16, 0x61c1, 0xcc16, 0x21, 0 - .dw 0x61c3, 0xcc16, 0x61cf, 0xcc16, 0x21, 0 - .dw 0x61d1, 0xcc16, 0x61d1, 0xcc16, 0x21, 0 - .dw 0x61d3, 0xcc16, 0x61ff, 0xcc16, 0x21, 0 - .dw 0x6201, 0xcc16, 0x6201, 0xcc16, 0x21, 0 - .dw 0x6203, 0xcc16, 0x620f, 0xcc16, 0x21, 0 - .dw 0x6211, 0xcc16, 0x6211, 0xcc16, 0x21, 0 - .dw 0x6213, 0xcc16, 0x623f, 0xcc16, 0x21, 0 - .dw 0x6241, 0xcc16, 0x6241, 0xcc16, 0x21, 0 - .dw 0x6243, 0xcc16, 0x624f, 0xcc16, 0x21, 0 - .dw 0x6251, 0xcc16, 0x6251, 0xcc16, 0x21, 0 - .dw 0x6253, 0xcc16, 0x627f, 0xcc16, 0x21, 0 - .dw 0x6281, 0xcc16, 0x6281, 0xcc16, 0x21, 0 - .dw 0x6283, 0xcc16, 0x628f, 0xcc16, 0x21, 0 - .dw 0x6291, 0xcc16, 0x6291, 0xcc16, 0x21, 0 - .dw 0x6293, 0xcc16, 0x62bf, 0xcc16, 0x21, 0 - .dw 0x62c1, 0xcc16, 0x62c1, 0xcc16, 0x21, 0 - .dw 0x62c3, 0xcc16, 0x62cf, 0xcc16, 0x21, 0 - .dw 0x62d1, 0xcc16, 0x62d1, 0xcc16, 0x21, 0 - .dw 0x62d3, 0xcc16, 0x62ff, 0xcc16, 0x21, 0 - .dw 0x6301, 0xcc16, 0x6301, 0xcc16, 0x21, 0 - .dw 0x6303, 0xcc16, 0x630f, 0xcc16, 0x21, 0 - .dw 0x6311, 0xcc16, 0x6311, 0xcc16, 0x21, 0 - .dw 0x6313, 0xcc16, 0x633f, 0xcc16, 0x21, 0 - .dw 0x6341, 0xcc16, 0x6341, 0xcc16, 0x21, 0 - .dw 0x6343, 0xcc16, 0x634f, 0xcc16, 0x21, 0 - .dw 0x6351, 0xcc16, 0x6351, 0xcc16, 0x21, 0 - .dw 0x6353, 0xcc16, 0x637f, 0xcc16, 0x21, 0 - .dw 0x6381, 0xcc16, 0x6381, 0xcc16, 0x21, 0 - .dw 0x6383, 0xcc16, 0x638f, 0xcc16, 0x21, 0 - .dw 0x6391, 0xcc16, 0x6391, 0xcc16, 0x21, 0 - .dw 0x6393, 0xcc16, 0x63bf, 0xcc16, 0x21, 0 - .dw 0x63c1, 0xcc16, 0x63c1, 0xcc16, 0x21, 0 - .dw 0x63c3, 0xcc16, 0x63cf, 0xcc16, 0x21, 0 - .dw 0x63d1, 0xcc16, 0x63d1, 0xcc16, 0x21, 0 - .dw 0x63d3, 0xcc16, 0x63ff, 0xcc16, 0x21, 0 - .dw 0x6401, 0xcc16, 0x6401, 0xcc16, 0x21, 0 - .dw 0x6403, 0xcc16, 0x640f, 0xcc16, 0x21, 0 - .dw 0x6411, 0xcc16, 0x6411, 0xcc16, 0x21, 0 - .dw 0x6413, 0xcc16, 0x643f, 0xcc16, 0x21, 0 - .dw 0x6441, 0xcc16, 0x6441, 0xcc16, 0x21, 0 - .dw 0x6443, 0xcc16, 0x644f, 0xcc16, 0x21, 0 - .dw 0x6451, 0xcc16, 0x6451, 0xcc16, 0x21, 0 - .dw 0x6453, 0xcc16, 0x647f, 0xcc16, 0x21, 0 - .dw 0x6481, 0xcc16, 0x6481, 0xcc16, 0x21, 0 - .dw 0x6483, 0xcc16, 0x648f, 0xcc16, 0x21, 0 - .dw 0x6491, 0xcc16, 0x6491, 0xcc16, 0x21, 0 - .dw 0x6493, 0xcc16, 0x64bf, 0xcc16, 0x21, 0 - .dw 0x64c1, 0xcc16, 0x64c1, 0xcc16, 0x21, 0 - .dw 0x64c3, 0xcc16, 0x64cf, 0xcc16, 0x21, 0 - .dw 0x64d1, 0xcc16, 0x64d1, 0xcc16, 0x21, 0 - .dw 0x64d3, 0xcc16, 0x64ff, 0xcc16, 0x21, 0 - .dw 0x6501, 0xcc16, 0x6501, 0xcc16, 0x21, 0 - .dw 0x6503, 0xcc16, 0x650f, 0xcc16, 0x21, 0 - .dw 0x6511, 0xcc16, 0x6511, 0xcc16, 0x21, 0 - .dw 0x6513, 0xcc16, 0x653f, 0xcc16, 0x21, 0 - .dw 0x6541, 0xcc16, 0x6541, 0xcc16, 0x21, 0 - .dw 0x6543, 0xcc16, 0x654f, 0xcc16, 0x21, 0 - .dw 0x6551, 0xcc16, 0x6551, 0xcc16, 0x21, 0 - .dw 0x6553, 0xcc16, 0x657f, 0xcc16, 0x21, 0 - .dw 0x6581, 0xcc16, 0x6581, 0xcc16, 0x21, 0 - .dw 0x6583, 0xcc16, 0x658f, 0xcc16, 0x21, 0 - .dw 0x6591, 0xcc16, 0x6591, 0xcc16, 0x21, 0 - .dw 0x6593, 0xcc16, 0x65bf, 0xcc16, 0x21, 0 - .dw 0x65c1, 0xcc16, 0x65c1, 0xcc16, 0x21, 0 - .dw 0x65c3, 0xcc16, 0x65cf, 0xcc16, 0x21, 0 - .dw 0x65d1, 0xcc16, 0x65d1, 0xcc16, 0x21, 0 - .dw 0x65d3, 0xcc16, 0x65ff, 0xcc16, 0x21, 0 - .dw 0x6601, 0xcc16, 0x6601, 0xcc16, 0x21, 0 - .dw 0x6603, 0xcc16, 0x660f, 0xcc16, 0x21, 0 - .dw 0x6611, 0xcc16, 0x6611, 0xcc16, 0x21, 0 - .dw 0x6613, 0xcc16, 0x663f, 0xcc16, 0x21, 0 - .dw 0x6641, 0xcc16, 0x6641, 0xcc16, 0x21, 0 - .dw 0x6643, 0xcc16, 0x664f, 0xcc16, 0x21, 0 - .dw 0x6651, 0xcc16, 0x6651, 0xcc16, 0x21, 0 - .dw 0x6653, 0xcc16, 0x667f, 0xcc16, 0x21, 0 - .dw 0x6681, 0xcc16, 0x6681, 0xcc16, 0x21, 0 - .dw 0x6683, 0xcc16, 0x668f, 0xcc16, 0x21, 0 - .dw 0x6691, 0xcc16, 0x6691, 0xcc16, 0x21, 0 - .dw 0x6693, 0xcc16, 0x66bf, 0xcc16, 0x21, 0 - .dw 0x66c1, 0xcc16, 0x66c1, 0xcc16, 0x21, 0 - .dw 0x66c3, 0xcc16, 0x66cf, 0xcc16, 0x21, 0 - .dw 0x66d1, 0xcc16, 0x66d1, 0xcc16, 0x21, 0 - .dw 0x66d3, 0xcc16, 0x66ff, 0xcc16, 0x21, 0 - .dw 0x6701, 0xcc16, 0x6701, 0xcc16, 0x21, 0 - .dw 0x6703, 0xcc16, 0x670f, 0xcc16, 0x21, 0 - .dw 0x6711, 0xcc16, 0x6711, 0xcc16, 0x21, 0 - .dw 0x6713, 0xcc16, 0x673f, 0xcc16, 0x21, 0 - .dw 0x6741, 0xcc16, 0x6741, 0xcc16, 0x21, 0 - .dw 0x6743, 0xcc16, 0x674f, 0xcc16, 0x21, 0 - .dw 0x6751, 0xcc16, 0x6751, 0xcc16, 0x21, 0 - .dw 0x6753, 0xcc16, 0x677f, 0xcc16, 0x21, 0 - .dw 0x6781, 0xcc16, 0x6781, 0xcc16, 0x21, 0 - .dw 0x6783, 0xcc16, 0x678f, 0xcc16, 0x21, 0 - .dw 0x6791, 0xcc16, 0x6791, 0xcc16, 0x21, 0 - .dw 0x6793, 0xcc16, 0x67bf, 0xcc16, 0x21, 0 - .dw 0x67c1, 0xcc16, 0x67c1, 0xcc16, 0x21, 0 - .dw 0x67c3, 0xcc16, 0x67cf, 0xcc16, 0x21, 0 - .dw 0x67d1, 0xcc16, 0x67d1, 0xcc16, 0x21, 0 - .dw 0x67d3, 0xcc16, 0x67ff, 0xcc16, 0x21, 0 - .dw 0x6801, 0xcc16, 0x6801, 0xcc16, 0x21, 0 - .dw 0x6803, 0xcc16, 0x680f, 0xcc16, 0x21, 0 - .dw 0x6811, 0xcc16, 0x6811, 0xcc16, 0x21, 0 - .dw 0x6813, 0xcc16, 0x683f, 0xcc16, 0x21, 0 - .dw 0x6841, 0xcc16, 0x6841, 0xcc16, 0x21, 0 - .dw 0x6843, 0xcc16, 0x684f, 0xcc16, 0x21, 0 - .dw 0x6851, 0xcc16, 0x6851, 0xcc16, 0x21, 0 - .dw 0x6853, 0xcc16, 0x687f, 0xcc16, 0x21, 0 - .dw 0x6881, 0xcc16, 0x6881, 0xcc16, 0x21, 0 - .dw 0x6883, 0xcc16, 0x688f, 0xcc16, 0x21, 0 - .dw 0x6891, 0xcc16, 0x6891, 0xcc16, 0x21, 0 - .dw 0x6893, 0xcc16, 0x68bf, 0xcc16, 0x21, 0 - .dw 0x68c1, 0xcc16, 0x68c1, 0xcc16, 0x21, 0 - .dw 0x68c3, 0xcc16, 0x68cf, 0xcc16, 0x21, 0 - .dw 0x68d1, 0xcc16, 0x68d1, 0xcc16, 0x21, 0 - .dw 0x68d3, 0xcc16, 0x68ff, 0xcc16, 0x21, 0 - .dw 0x6901, 0xcc16, 0x6901, 0xcc16, 0x21, 0 - .dw 0x6903, 0xcc16, 0x690f, 0xcc16, 0x21, 0 - .dw 0x6911, 0xcc16, 0x6911, 0xcc16, 0x21, 0 - .dw 0x6913, 0xcc16, 0x693f, 0xcc16, 0x21, 0 - .dw 0x6941, 0xcc16, 0x6941, 0xcc16, 0x21, 0 - .dw 0x6943, 0xcc16, 0x694f, 0xcc16, 0x21, 0 - .dw 0x6951, 0xcc16, 0x6951, 0xcc16, 0x21, 0 - .dw 0x6953, 0xcc16, 0x697f, 0xcc16, 0x21, 0 - .dw 0x6981, 0xcc16, 0x6981, 0xcc16, 0x21, 0 - .dw 0x6983, 0xcc16, 0x698f, 0xcc16, 0x21, 0 - .dw 0x6991, 0xcc16, 0x6991, 0xcc16, 0x21, 0 - .dw 0x6993, 0xcc16, 0x69bf, 0xcc16, 0x21, 0 - .dw 0x69c1, 0xcc16, 0x69c1, 0xcc16, 0x21, 0 - .dw 0x69c3, 0xcc16, 0x69cf, 0xcc16, 0x21, 0 - .dw 0x69d1, 0xcc16, 0x69d1, 0xcc16, 0x21, 0 - .dw 0x69d3, 0xcc16, 0x69ff, 0xcc16, 0x21, 0 - .dw 0x6a01, 0xcc16, 0x6a01, 0xcc16, 0x21, 0 - .dw 0x6a03, 0xcc16, 0x6a0f, 0xcc16, 0x21, 0 - .dw 0x6a11, 0xcc16, 0x6a11, 0xcc16, 0x21, 0 - .dw 0x6a13, 0xcc16, 0x6a3f, 0xcc16, 0x21, 0 - .dw 0x6a41, 0xcc16, 0x6a41, 0xcc16, 0x21, 0 - .dw 0x6a43, 0xcc16, 0x6a4f, 0xcc16, 0x21, 0 - .dw 0x6a51, 0xcc16, 0x6a51, 0xcc16, 0x21, 0 - .dw 0x6a53, 0xcc16, 0x6a7f, 0xcc16, 0x21, 0 - .dw 0x6a81, 0xcc16, 0x6a81, 0xcc16, 0x21, 0 - .dw 0x6a83, 0xcc16, 0x6a8f, 0xcc16, 0x21, 0 - .dw 0x6a91, 0xcc16, 0x6a91, 0xcc16, 0x21, 0 - .dw 0x6a93, 0xcc16, 0x6abf, 0xcc16, 0x21, 0 - .dw 0x6ac1, 0xcc16, 0x6ac1, 0xcc16, 0x21, 0 - .dw 0x6ac3, 0xcc16, 0x6acf, 0xcc16, 0x21, 0 - .dw 0x6ad1, 0xcc16, 0x6ad1, 0xcc16, 0x21, 0 - .dw 0x6ad3, 0xcc16, 0x6aff, 0xcc16, 0x21, 0 - .dw 0x6b01, 0xcc16, 0x6b01, 0xcc16, 0x21, 0 - .dw 0x6b03, 0xcc16, 0x6b0f, 0xcc16, 0x21, 0 - .dw 0x6b11, 0xcc16, 0x6b11, 0xcc16, 0x21, 0 - .dw 0x6b13, 0xcc16, 0x6b3f, 0xcc16, 0x21, 0 - .dw 0x6b41, 0xcc16, 0x6b41, 0xcc16, 0x21, 0 - .dw 0x6b43, 0xcc16, 0x6b4f, 0xcc16, 0x21, 0 - .dw 0x6b51, 0xcc16, 0x6b51, 0xcc16, 0x21, 0 - .dw 0x6b53, 0xcc16, 0x6b7f, 0xcc16, 0x21, 0 - .dw 0x6b81, 0xcc16, 0x6b81, 0xcc16, 0x21, 0 - .dw 0x6b83, 0xcc16, 0x6b8f, 0xcc16, 0x21, 0 - .dw 0x6b91, 0xcc16, 0x6b91, 0xcc16, 0x21, 0 - .dw 0x6b93, 0xcc16, 0x6bbf, 0xcc16, 0x21, 0 - .dw 0x6bc1, 0xcc16, 0x6bc1, 0xcc16, 0x21, 0 - .dw 0x6bc3, 0xcc16, 0x6bcf, 0xcc16, 0x21, 0 - .dw 0x6bd1, 0xcc16, 0x6bd1, 0xcc16, 0x21, 0 - .dw 0x6bd3, 0xcc16, 0x6bff, 0xcc16, 0x21, 0 - .dw 0x6c01, 0xcc16, 0x6c01, 0xcc16, 0x21, 0 - .dw 0x6c03, 0xcc16, 0x6c0f, 0xcc16, 0x21, 0 - .dw 0x6c11, 0xcc16, 0x6c11, 0xcc16, 0x21, 0 - .dw 0x6c13, 0xcc16, 0x6c3f, 0xcc16, 0x21, 0 - .dw 0x6c41, 0xcc16, 0x6c41, 0xcc16, 0x21, 0 - .dw 0x6c43, 0xcc16, 0x6c4f, 0xcc16, 0x21, 0 - .dw 0x6c51, 0xcc16, 0x6c51, 0xcc16, 0x21, 0 - .dw 0x6c53, 0xcc16, 0x6c7f, 0xcc16, 0x21, 0 - .dw 0x6c81, 0xcc16, 0x6c81, 0xcc16, 0x21, 0 - .dw 0x6c83, 0xcc16, 0x6c8f, 0xcc16, 0x21, 0 - .dw 0x6c91, 0xcc16, 0x6c91, 0xcc16, 0x21, 0 - .dw 0x6c93, 0xcc16, 0x6cbf, 0xcc16, 0x21, 0 - .dw 0x6cc1, 0xcc16, 0x6cc1, 0xcc16, 0x21, 0 - .dw 0x6cc3, 0xcc16, 0x6ccf, 0xcc16, 0x21, 0 - .dw 0x6cd1, 0xcc16, 0x6cd1, 0xcc16, 0x21, 0 - .dw 0x6cd3, 0xcc16, 0x6cff, 0xcc16, 0x21, 0 - .dw 0x6d01, 0xcc16, 0x6d01, 0xcc16, 0x21, 0 - .dw 0x6d03, 0xcc16, 0x6d0f, 0xcc16, 0x21, 0 - .dw 0x6d11, 0xcc16, 0x6d11, 0xcc16, 0x21, 0 - .dw 0x6d13, 0xcc16, 0x6d3f, 0xcc16, 0x21, 0 - .dw 0x6d41, 0xcc16, 0x6d41, 0xcc16, 0x21, 0 - .dw 0x6d43, 0xcc16, 0x6d4f, 0xcc16, 0x21, 0 - .dw 0x6d51, 0xcc16, 0x6d51, 0xcc16, 0x21, 0 - .dw 0x6d53, 0xcc16, 0x6d7f, 0xcc16, 0x21, 0 - .dw 0x6d81, 0xcc16, 0x6d81, 0xcc16, 0x21, 0 - .dw 0x6d83, 0xcc16, 0x6d8f, 0xcc16, 0x21, 0 - .dw 0x6d91, 0xcc16, 0x6d91, 0xcc16, 0x21, 0 - .dw 0x6d93, 0xcc16, 0x6dbf, 0xcc16, 0x21, 0 - .dw 0x6dc1, 0xcc16, 0x6dc1, 0xcc16, 0x21, 0 - .dw 0x6dc3, 0xcc16, 0x6dcf, 0xcc16, 0x21, 0 - .dw 0x6dd1, 0xcc16, 0x6dd1, 0xcc16, 0x21, 0 - .dw 0x6dd3, 0xcc16, 0x6dff, 0xcc16, 0x21, 0 - .dw 0x6e01, 0xcc16, 0x6e01, 0xcc16, 0x21, 0 - .dw 0x6e03, 0xcc16, 0x6e0f, 0xcc16, 0x21, 0 - .dw 0x6e11, 0xcc16, 0x6e11, 0xcc16, 0x21, 0 - .dw 0x6e13, 0xcc16, 0x6e3f, 0xcc16, 0x21, 0 - .dw 0x6e41, 0xcc16, 0x6e41, 0xcc16, 0x21, 0 - .dw 0x6e43, 0xcc16, 0x6e4f, 0xcc16, 0x21, 0 - .dw 0x6e51, 0xcc16, 0x6e51, 0xcc16, 0x21, 0 - .dw 0x6e53, 0xcc16, 0x6e7f, 0xcc16, 0x21, 0 - .dw 0x6e81, 0xcc16, 0x6e81, 0xcc16, 0x21, 0 - .dw 0x6e83, 0xcc16, 0x6e8f, 0xcc16, 0x21, 0 - .dw 0x6e91, 0xcc16, 0x6e91, 0xcc16, 0x21, 0 - .dw 0x6e93, 0xcc16, 0x6ebf, 0xcc16, 0x21, 0 - .dw 0x6ec1, 0xcc16, 0x6ec1, 0xcc16, 0x21, 0 - .dw 0x6ec3, 0xcc16, 0x6ecf, 0xcc16, 0x21, 0 - .dw 0x6ed1, 0xcc16, 0x6ed1, 0xcc16, 0x21, 0 - .dw 0x6ed3, 0xcc16, 0x6eff, 0xcc16, 0x21, 0 - .dw 0x6f01, 0xcc16, 0x6f01, 0xcc16, 0x21, 0 - .dw 0x6f03, 0xcc16, 0x6f0f, 0xcc16, 0x21, 0 - .dw 0x6f11, 0xcc16, 0x6f11, 0xcc16, 0x21, 0 - .dw 0x6f13, 0xcc16, 0x6f3f, 0xcc16, 0x21, 0 - .dw 0x6f41, 0xcc16, 0x6f41, 0xcc16, 0x21, 0 - .dw 0x6f43, 0xcc16, 0x6f4f, 0xcc16, 0x21, 0 - .dw 0x6f51, 0xcc16, 0x6f51, 0xcc16, 0x21, 0 - .dw 0x6f53, 0xcc16, 0x6f7f, 0xcc16, 0x21, 0 - .dw 0x6f81, 0xcc16, 0x6f81, 0xcc16, 0x21, 0 - .dw 0x6f83, 0xcc16, 0x6f8f, 0xcc16, 0x21, 0 - .dw 0x6f91, 0xcc16, 0x6f91, 0xcc16, 0x21, 0 - .dw 0x6f93, 0xcc16, 0x6fbf, 0xcc16, 0x21, 0 - .dw 0x6fc1, 0xcc16, 0x6fc1, 0xcc16, 0x21, 0 - .dw 0x6fc3, 0xcc16, 0x6fcf, 0xcc16, 0x21, 0 - .dw 0x6fd1, 0xcc16, 0x6fd1, 0xcc16, 0x21, 0 - .dw 0x6fd3, 0xcc16, 0xffff, 0xcc16, 0x21, 0 - .dw 0x0001, 0xcc17, 0x0001, 0xcc17, 0x21, 0 - .dw 0x0003, 0xcc17, 0x000f, 0xcc17, 0x21, 0 - .dw 0x0011, 0xcc17, 0x0011, 0xcc17, 0x21, 0 - .dw 0x0013, 0xcc17, 0x003f, 0xcc17, 0x21, 0 - .dw 0x0041, 0xcc17, 0x0041, 0xcc17, 0x21, 0 - .dw 0x0043, 0xcc17, 0x004f, 0xcc17, 0x21, 0 - .dw 0x0051, 0xcc17, 0x0051, 0xcc17, 0x21, 0 - .dw 0x0053, 0xcc17, 0x007f, 0xcc17, 0x21, 0 - .dw 0x0081, 0xcc17, 0x0081, 0xcc17, 0x21, 0 - .dw 0x0083, 0xcc17, 0x008f, 0xcc17, 0x21, 0 - .dw 0x0091, 0xcc17, 0x0091, 0xcc17, 0x21, 0 - .dw 0x0093, 0xcc17, 0x00bf, 0xcc17, 0x21, 0 - .dw 0x00c1, 0xcc17, 0x00c1, 0xcc17, 0x21, 0 - .dw 0x00c3, 0xcc17, 0x00cf, 0xcc17, 0x21, 0 - .dw 0x00d1, 0xcc17, 0x00d1, 0xcc17, 0x21, 0 - .dw 0x00d3, 0xcc17, 0x00ff, 0xcc17, 0x21, 0 - .dw 0x0101, 0xcc17, 0x0101, 0xcc17, 0x21, 0 - .dw 0x0103, 0xcc17, 0x010f, 0xcc17, 0x21, 0 - .dw 0x0111, 0xcc17, 0x0111, 0xcc17, 0x21, 0 - .dw 0x0113, 0xcc17, 0x013f, 0xcc17, 0x21, 0 - .dw 0x0141, 0xcc17, 0x0141, 0xcc17, 0x21, 0 - .dw 0x0143, 0xcc17, 0x014f, 0xcc17, 0x21, 0 - .dw 0x0151, 0xcc17, 0x0151, 0xcc17, 0x21, 0 - .dw 0x0153, 0xcc17, 0x017f, 0xcc17, 0x21, 0 - .dw 0x0181, 0xcc17, 0x0181, 0xcc17, 0x21, 0 - .dw 0x0183, 0xcc17, 0x018f, 0xcc17, 0x21, 0 - .dw 0x0191, 0xcc17, 0x0191, 0xcc17, 0x21, 0 - .dw 0x0193, 0xcc17, 0x01bf, 0xcc17, 0x21, 0 - .dw 0x01c1, 0xcc17, 0x01c1, 0xcc17, 0x21, 0 - .dw 0x01c3, 0xcc17, 0x01cf, 0xcc17, 0x21, 0 - .dw 0x01d1, 0xcc17, 0x01d1, 0xcc17, 0x21, 0 - .dw 0x01d3, 0xcc17, 0x01ff, 0xcc17, 0x21, 0 - .dw 0x0201, 0xcc17, 0x0201, 0xcc17, 0x21, 0 - .dw 0x0203, 0xcc17, 0x020f, 0xcc17, 0x21, 0 - .dw 0x0211, 0xcc17, 0x0211, 0xcc17, 0x21, 0 - .dw 0x0213, 0xcc17, 0x023f, 0xcc17, 0x21, 0 - .dw 0x0241, 0xcc17, 0x0241, 0xcc17, 0x21, 0 - .dw 0x0243, 0xcc17, 0x024f, 0xcc17, 0x21, 0 - .dw 0x0251, 0xcc17, 0x0251, 0xcc17, 0x21, 0 - .dw 0x0253, 0xcc17, 0x027f, 0xcc17, 0x21, 0 - .dw 0x0281, 0xcc17, 0x0281, 0xcc17, 0x21, 0 - .dw 0x0283, 0xcc17, 0x028f, 0xcc17, 0x21, 0 - .dw 0x0291, 0xcc17, 0x0291, 0xcc17, 0x21, 0 - .dw 0x0293, 0xcc17, 0x02bf, 0xcc17, 0x21, 0 - .dw 0x02c1, 0xcc17, 0x02c1, 0xcc17, 0x21, 0 - .dw 0x02c3, 0xcc17, 0x02cf, 0xcc17, 0x21, 0 - .dw 0x02d1, 0xcc17, 0x02d1, 0xcc17, 0x21, 0 - .dw 0x02d3, 0xcc17, 0x02ff, 0xcc17, 0x21, 0 - .dw 0x0301, 0xcc17, 0x0301, 0xcc17, 0x21, 0 - .dw 0x0303, 0xcc17, 0x030f, 0xcc17, 0x21, 0 - .dw 0x0311, 0xcc17, 0x0311, 0xcc17, 0x21, 0 - .dw 0x0313, 0xcc17, 0x033f, 0xcc17, 0x21, 0 - .dw 0x0341, 0xcc17, 0x0341, 0xcc17, 0x21, 0 - .dw 0x0343, 0xcc17, 0x034f, 0xcc17, 0x21, 0 - .dw 0x0351, 0xcc17, 0x0351, 0xcc17, 0x21, 0 - .dw 0x0353, 0xcc17, 0x037f, 0xcc17, 0x21, 0 - .dw 0x0381, 0xcc17, 0x0381, 0xcc17, 0x21, 0 - .dw 0x0383, 0xcc17, 0x038f, 0xcc17, 0x21, 0 - .dw 0x0391, 0xcc17, 0x0391, 0xcc17, 0x21, 0 - .dw 0x0393, 0xcc17, 0x03bf, 0xcc17, 0x21, 0 - .dw 0x03c1, 0xcc17, 0x03c1, 0xcc17, 0x21, 0 - .dw 0x03c3, 0xcc17, 0x03cf, 0xcc17, 0x21, 0 - .dw 0x03d1, 0xcc17, 0x03d1, 0xcc17, 0x21, 0 - .dw 0x03d3, 0xcc17, 0x03ff, 0xcc17, 0x21, 0 - .dw 0x0401, 0xcc17, 0x0401, 0xcc17, 0x21, 0 - .dw 0x0403, 0xcc17, 0x040f, 0xcc17, 0x21, 0 - .dw 0x0411, 0xcc17, 0x0411, 0xcc17, 0x21, 0 - .dw 0x0413, 0xcc17, 0x043f, 0xcc17, 0x21, 0 - .dw 0x0441, 0xcc17, 0x0441, 0xcc17, 0x21, 0 - .dw 0x0443, 0xcc17, 0x044f, 0xcc17, 0x21, 0 - .dw 0x0451, 0xcc17, 0x0451, 0xcc17, 0x21, 0 - .dw 0x0453, 0xcc17, 0x047f, 0xcc17, 0x21, 0 - .dw 0x0481, 0xcc17, 0x0481, 0xcc17, 0x21, 0 - .dw 0x0483, 0xcc17, 0x048f, 0xcc17, 0x21, 0 - .dw 0x0491, 0xcc17, 0x0491, 0xcc17, 0x21, 0 - .dw 0x0493, 0xcc17, 0x04bf, 0xcc17, 0x21, 0 - .dw 0x04c1, 0xcc17, 0x04c1, 0xcc17, 0x21, 0 - .dw 0x04c3, 0xcc17, 0x04cf, 0xcc17, 0x21, 0 - .dw 0x04d1, 0xcc17, 0x04d1, 0xcc17, 0x21, 0 - .dw 0x04d3, 0xcc17, 0x04ff, 0xcc17, 0x21, 0 - .dw 0x0501, 0xcc17, 0x0501, 0xcc17, 0x21, 0 - .dw 0x0503, 0xcc17, 0x050f, 0xcc17, 0x21, 0 - .dw 0x0511, 0xcc17, 0x0511, 0xcc17, 0x21, 0 - .dw 0x0513, 0xcc17, 0x053f, 0xcc17, 0x21, 0 - .dw 0x0541, 0xcc17, 0x0541, 0xcc17, 0x21, 0 - .dw 0x0543, 0xcc17, 0x054f, 0xcc17, 0x21, 0 - .dw 0x0551, 0xcc17, 0x0551, 0xcc17, 0x21, 0 - .dw 0x0553, 0xcc17, 0x057f, 0xcc17, 0x21, 0 - .dw 0x0581, 0xcc17, 0x0581, 0xcc17, 0x21, 0 - .dw 0x0583, 0xcc17, 0x058f, 0xcc17, 0x21, 0 - .dw 0x0591, 0xcc17, 0x0591, 0xcc17, 0x21, 0 - .dw 0x0593, 0xcc17, 0x05bf, 0xcc17, 0x21, 0 - .dw 0x05c1, 0xcc17, 0x05c1, 0xcc17, 0x21, 0 - .dw 0x05c3, 0xcc17, 0x05cf, 0xcc17, 0x21, 0 - .dw 0x05d1, 0xcc17, 0x05d1, 0xcc17, 0x21, 0 - .dw 0x05d3, 0xcc17, 0x05ff, 0xcc17, 0x21, 0 - .dw 0x0601, 0xcc17, 0x0601, 0xcc17, 0x21, 0 - .dw 0x0603, 0xcc17, 0x060f, 0xcc17, 0x21, 0 - .dw 0x0611, 0xcc17, 0x0611, 0xcc17, 0x21, 0 - .dw 0x0613, 0xcc17, 0x063f, 0xcc17, 0x21, 0 - .dw 0x0641, 0xcc17, 0x0641, 0xcc17, 0x21, 0 - .dw 0x0643, 0xcc17, 0x064f, 0xcc17, 0x21, 0 - .dw 0x0651, 0xcc17, 0x0651, 0xcc17, 0x21, 0 - .dw 0x0653, 0xcc17, 0x067f, 0xcc17, 0x21, 0 - .dw 0x0681, 0xcc17, 0x0681, 0xcc17, 0x21, 0 - .dw 0x0683, 0xcc17, 0x068f, 0xcc17, 0x21, 0 - .dw 0x0691, 0xcc17, 0x0691, 0xcc17, 0x21, 0 - .dw 0x0693, 0xcc17, 0x06bf, 0xcc17, 0x21, 0 - .dw 0x06c1, 0xcc17, 0x06c1, 0xcc17, 0x21, 0 - .dw 0x06c3, 0xcc17, 0x06cf, 0xcc17, 0x21, 0 - .dw 0x06d1, 0xcc17, 0x06d1, 0xcc17, 0x21, 0 - .dw 0x06d3, 0xcc17, 0x06ff, 0xcc17, 0x21, 0 - .dw 0x0701, 0xcc17, 0x0701, 0xcc17, 0x21, 0 - .dw 0x0703, 0xcc17, 0x070f, 0xcc17, 0x21, 0 - .dw 0x0711, 0xcc17, 0x0711, 0xcc17, 0x21, 0 - .dw 0x0713, 0xcc17, 0x073f, 0xcc17, 0x21, 0 - .dw 0x0741, 0xcc17, 0x0741, 0xcc17, 0x21, 0 - .dw 0x0743, 0xcc17, 0x074f, 0xcc17, 0x21, 0 - .dw 0x0751, 0xcc17, 0x0751, 0xcc17, 0x21, 0 - .dw 0x0753, 0xcc17, 0x077f, 0xcc17, 0x21, 0 - .dw 0x0781, 0xcc17, 0x0781, 0xcc17, 0x21, 0 - .dw 0x0783, 0xcc17, 0x078f, 0xcc17, 0x21, 0 - .dw 0x0791, 0xcc17, 0x0791, 0xcc17, 0x21, 0 - .dw 0x0793, 0xcc17, 0x07bf, 0xcc17, 0x21, 0 - .dw 0x07c1, 0xcc17, 0x07c1, 0xcc17, 0x21, 0 - .dw 0x07c3, 0xcc17, 0x07cf, 0xcc17, 0x21, 0 - .dw 0x07d1, 0xcc17, 0x07d1, 0xcc17, 0x21, 0 - .dw 0x07d3, 0xcc17, 0x07ff, 0xcc17, 0x21, 0 - .dw 0x0801, 0xcc17, 0x0801, 0xcc17, 0x21, 0 - .dw 0x0803, 0xcc17, 0x080f, 0xcc17, 0x21, 0 - .dw 0x0811, 0xcc17, 0x0811, 0xcc17, 0x21, 0 - .dw 0x0813, 0xcc17, 0x083f, 0xcc17, 0x21, 0 - .dw 0x0841, 0xcc17, 0x0841, 0xcc17, 0x21, 0 - .dw 0x0843, 0xcc17, 0x084f, 0xcc17, 0x21, 0 - .dw 0x0851, 0xcc17, 0x0851, 0xcc17, 0x21, 0 - .dw 0x0853, 0xcc17, 0x087f, 0xcc17, 0x21, 0 - .dw 0x0881, 0xcc17, 0x0881, 0xcc17, 0x21, 0 - .dw 0x0883, 0xcc17, 0x088f, 0xcc17, 0x21, 0 - .dw 0x0891, 0xcc17, 0x0891, 0xcc17, 0x21, 0 - .dw 0x0893, 0xcc17, 0x08bf, 0xcc17, 0x21, 0 - .dw 0x08c1, 0xcc17, 0x08c1, 0xcc17, 0x21, 0 - .dw 0x08c3, 0xcc17, 0x08cf, 0xcc17, 0x21, 0 - .dw 0x08d1, 0xcc17, 0x08d1, 0xcc17, 0x21, 0 - .dw 0x08d3, 0xcc17, 0x08ff, 0xcc17, 0x21, 0 - .dw 0x0901, 0xcc17, 0x0901, 0xcc17, 0x21, 0 - .dw 0x0903, 0xcc17, 0x090f, 0xcc17, 0x21, 0 - .dw 0x0911, 0xcc17, 0x0911, 0xcc17, 0x21, 0 - .dw 0x0913, 0xcc17, 0x093f, 0xcc17, 0x21, 0 - .dw 0x0941, 0xcc17, 0x0941, 0xcc17, 0x21, 0 - .dw 0x0943, 0xcc17, 0x094f, 0xcc17, 0x21, 0 - .dw 0x0951, 0xcc17, 0x0951, 0xcc17, 0x21, 0 - .dw 0x0953, 0xcc17, 0x097f, 0xcc17, 0x21, 0 - .dw 0x0981, 0xcc17, 0x0981, 0xcc17, 0x21, 0 - .dw 0x0983, 0xcc17, 0x098f, 0xcc17, 0x21, 0 - .dw 0x0991, 0xcc17, 0x0991, 0xcc17, 0x21, 0 - .dw 0x0993, 0xcc17, 0x09bf, 0xcc17, 0x21, 0 - .dw 0x09c1, 0xcc17, 0x09c1, 0xcc17, 0x21, 0 - .dw 0x09c3, 0xcc17, 0x09cf, 0xcc17, 0x21, 0 - .dw 0x09d1, 0xcc17, 0x09d1, 0xcc17, 0x21, 0 - .dw 0x09d3, 0xcc17, 0x09ff, 0xcc17, 0x21, 0 - .dw 0x0a01, 0xcc17, 0x0a01, 0xcc17, 0x21, 0 - .dw 0x0a03, 0xcc17, 0x0a0f, 0xcc17, 0x21, 0 - .dw 0x0a11, 0xcc17, 0x0a11, 0xcc17, 0x21, 0 - .dw 0x0a13, 0xcc17, 0x0a3f, 0xcc17, 0x21, 0 - .dw 0x0a41, 0xcc17, 0x0a41, 0xcc17, 0x21, 0 - .dw 0x0a43, 0xcc17, 0x0a4f, 0xcc17, 0x21, 0 - .dw 0x0a51, 0xcc17, 0x0a51, 0xcc17, 0x21, 0 - .dw 0x0a53, 0xcc17, 0x0a7f, 0xcc17, 0x21, 0 - .dw 0x0a81, 0xcc17, 0x0a81, 0xcc17, 0x21, 0 - .dw 0x0a83, 0xcc17, 0x0a8f, 0xcc17, 0x21, 0 - .dw 0x0a91, 0xcc17, 0x0a91, 0xcc17, 0x21, 0 - .dw 0x0a93, 0xcc17, 0x0abf, 0xcc17, 0x21, 0 - .dw 0x0ac1, 0xcc17, 0x0ac1, 0xcc17, 0x21, 0 - .dw 0x0ac3, 0xcc17, 0x0acf, 0xcc17, 0x21, 0 - .dw 0x0ad1, 0xcc17, 0x0ad1, 0xcc17, 0x21, 0 - .dw 0x0ad3, 0xcc17, 0x0aff, 0xcc17, 0x21, 0 - .dw 0x0b01, 0xcc17, 0x0b01, 0xcc17, 0x21, 0 - .dw 0x0b03, 0xcc17, 0x0b0f, 0xcc17, 0x21, 0 - .dw 0x0b11, 0xcc17, 0x0b11, 0xcc17, 0x21, 0 - .dw 0x0b13, 0xcc17, 0x0b3f, 0xcc17, 0x21, 0 - .dw 0x0b41, 0xcc17, 0x0b41, 0xcc17, 0x21, 0 - .dw 0x0b43, 0xcc17, 0x0b4f, 0xcc17, 0x21, 0 - .dw 0x0b51, 0xcc17, 0x0b51, 0xcc17, 0x21, 0 - .dw 0x0b53, 0xcc17, 0x0b7f, 0xcc17, 0x21, 0 - .dw 0x0b81, 0xcc17, 0x0b81, 0xcc17, 0x21, 0 - .dw 0x0b83, 0xcc17, 0x0b8f, 0xcc17, 0x21, 0 - .dw 0x0b91, 0xcc17, 0x0b91, 0xcc17, 0x21, 0 - .dw 0x0b93, 0xcc17, 0x0bbf, 0xcc17, 0x21, 0 - .dw 0x0bc1, 0xcc17, 0x0bc1, 0xcc17, 0x21, 0 - .dw 0x0bc3, 0xcc17, 0x0bcf, 0xcc17, 0x21, 0 - .dw 0x0bd1, 0xcc17, 0x0bd1, 0xcc17, 0x21, 0 - .dw 0x0bd3, 0xcc17, 0x0bff, 0xcc17, 0x21, 0 - .dw 0x0c01, 0xcc17, 0x0c01, 0xcc17, 0x21, 0 - .dw 0x0c03, 0xcc17, 0x0c0f, 0xcc17, 0x21, 0 - .dw 0x0c11, 0xcc17, 0x0c11, 0xcc17, 0x21, 0 - .dw 0x0c13, 0xcc17, 0x0c3f, 0xcc17, 0x21, 0 - .dw 0x0c41, 0xcc17, 0x0c41, 0xcc17, 0x21, 0 - .dw 0x0c43, 0xcc17, 0x0c4f, 0xcc17, 0x21, 0 - .dw 0x0c51, 0xcc17, 0x0c51, 0xcc17, 0x21, 0 - .dw 0x0c53, 0xcc17, 0x0c7f, 0xcc17, 0x21, 0 - .dw 0x0c81, 0xcc17, 0x0c81, 0xcc17, 0x21, 0 - .dw 0x0c83, 0xcc17, 0x0c8f, 0xcc17, 0x21, 0 - .dw 0x0c91, 0xcc17, 0x0c91, 0xcc17, 0x21, 0 - .dw 0x0c93, 0xcc17, 0x0cbf, 0xcc17, 0x21, 0 - .dw 0x0cc1, 0xcc17, 0x0cc1, 0xcc17, 0x21, 0 - .dw 0x0cc3, 0xcc17, 0x0ccf, 0xcc17, 0x21, 0 - .dw 0x0cd1, 0xcc17, 0x0cd1, 0xcc17, 0x21, 0 - .dw 0x0cd3, 0xcc17, 0x0cff, 0xcc17, 0x21, 0 - .dw 0x0d01, 0xcc17, 0x0d01, 0xcc17, 0x21, 0 - .dw 0x0d03, 0xcc17, 0x0d0f, 0xcc17, 0x21, 0 - .dw 0x0d11, 0xcc17, 0x0d11, 0xcc17, 0x21, 0 - .dw 0x0d13, 0xcc17, 0x0d3f, 0xcc17, 0x21, 0 - .dw 0x0d41, 0xcc17, 0x0d41, 0xcc17, 0x21, 0 - .dw 0x0d43, 0xcc17, 0x0d4f, 0xcc17, 0x21, 0 - .dw 0x0d51, 0xcc17, 0x0d51, 0xcc17, 0x21, 0 - .dw 0x0d53, 0xcc17, 0x0d7f, 0xcc17, 0x21, 0 - .dw 0x0d81, 0xcc17, 0x0d81, 0xcc17, 0x21, 0 - .dw 0x0d83, 0xcc17, 0x0d8f, 0xcc17, 0x21, 0 - .dw 0x0d91, 0xcc17, 0x0d91, 0xcc17, 0x21, 0 - .dw 0x0d93, 0xcc17, 0x0dbf, 0xcc17, 0x21, 0 - .dw 0x0dc1, 0xcc17, 0x0dc1, 0xcc17, 0x21, 0 - .dw 0x0dc3, 0xcc17, 0x0dcf, 0xcc17, 0x21, 0 - .dw 0x0dd1, 0xcc17, 0x0dd1, 0xcc17, 0x21, 0 - .dw 0x0dd3, 0xcc17, 0x0dff, 0xcc17, 0x21, 0 - .dw 0x0e01, 0xcc17, 0x0e01, 0xcc17, 0x21, 0 - .dw 0x0e03, 0xcc17, 0x0e0f, 0xcc17, 0x21, 0 - .dw 0x0e11, 0xcc17, 0x0e11, 0xcc17, 0x21, 0 - .dw 0x0e13, 0xcc17, 0x0e3f, 0xcc17, 0x21, 0 - .dw 0x0e41, 0xcc17, 0x0e41, 0xcc17, 0x21, 0 - .dw 0x0e43, 0xcc17, 0x0e4f, 0xcc17, 0x21, 0 - .dw 0x0e51, 0xcc17, 0x0e51, 0xcc17, 0x21, 0 - .dw 0x0e53, 0xcc17, 0x0e7f, 0xcc17, 0x21, 0 - .dw 0x0e81, 0xcc17, 0x0e81, 0xcc17, 0x21, 0 - .dw 0x0e83, 0xcc17, 0x0e8f, 0xcc17, 0x21, 0 - .dw 0x0e91, 0xcc17, 0x0e91, 0xcc17, 0x21, 0 - .dw 0x0e93, 0xcc17, 0x0ebf, 0xcc17, 0x21, 0 - .dw 0x0ec1, 0xcc17, 0x0ec1, 0xcc17, 0x21, 0 - .dw 0x0ec3, 0xcc17, 0x0ecf, 0xcc17, 0x21, 0 - .dw 0x0ed1, 0xcc17, 0x0ed1, 0xcc17, 0x21, 0 - .dw 0x0ed3, 0xcc17, 0x0eff, 0xcc17, 0x21, 0 - .dw 0x0f01, 0xcc17, 0x0f01, 0xcc17, 0x21, 0 - .dw 0x0f03, 0xcc17, 0x0f0f, 0xcc17, 0x21, 0 - .dw 0x0f11, 0xcc17, 0x0f11, 0xcc17, 0x21, 0 - .dw 0x0f13, 0xcc17, 0x0f3f, 0xcc17, 0x21, 0 - .dw 0x0f41, 0xcc17, 0x0f41, 0xcc17, 0x21, 0 - .dw 0x0f43, 0xcc17, 0x0f4f, 0xcc17, 0x21, 0 - .dw 0x0f51, 0xcc17, 0x0f51, 0xcc17, 0x21, 0 - .dw 0x0f53, 0xcc17, 0x0f7f, 0xcc17, 0x21, 0 - .dw 0x0f81, 0xcc17, 0x0f81, 0xcc17, 0x21, 0 - .dw 0x0f83, 0xcc17, 0x0f8f, 0xcc17, 0x21, 0 - .dw 0x0f91, 0xcc17, 0x0f91, 0xcc17, 0x21, 0 - .dw 0x0f93, 0xcc17, 0x0fbf, 0xcc17, 0x21, 0 - .dw 0x0fc1, 0xcc17, 0x0fc1, 0xcc17, 0x21, 0 - .dw 0x0fc3, 0xcc17, 0x0fcf, 0xcc17, 0x21, 0 - .dw 0x0fd1, 0xcc17, 0x0fd1, 0xcc17, 0x21, 0 - .dw 0x0fd3, 0xcc17, 0x1fff, 0xcc17, 0x21, 0 - .dw 0x2001, 0xcc17, 0x2001, 0xcc17, 0x21, 0 - .dw 0x2003, 0xcc17, 0x200f, 0xcc17, 0x21, 0 - .dw 0x2011, 0xcc17, 0x2011, 0xcc17, 0x21, 0 - .dw 0x2013, 0xcc17, 0x203f, 0xcc17, 0x21, 0 - .dw 0x2041, 0xcc17, 0x2041, 0xcc17, 0x21, 0 - .dw 0x2043, 0xcc17, 0x204f, 0xcc17, 0x21, 0 - .dw 0x2051, 0xcc17, 0x2051, 0xcc17, 0x21, 0 - .dw 0x2053, 0xcc17, 0x207f, 0xcc17, 0x21, 0 - .dw 0x2081, 0xcc17, 0x2081, 0xcc17, 0x21, 0 - .dw 0x2083, 0xcc17, 0x208f, 0xcc17, 0x21, 0 - .dw 0x2091, 0xcc17, 0x2091, 0xcc17, 0x21, 0 - .dw 0x2093, 0xcc17, 0x20bf, 0xcc17, 0x21, 0 - .dw 0x20c1, 0xcc17, 0x20c1, 0xcc17, 0x21, 0 - .dw 0x20c3, 0xcc17, 0x20cf, 0xcc17, 0x21, 0 - .dw 0x20d1, 0xcc17, 0x20d1, 0xcc17, 0x21, 0 - .dw 0x20d3, 0xcc17, 0x20ff, 0xcc17, 0x21, 0 - .dw 0x2101, 0xcc17, 0x2101, 0xcc17, 0x21, 0 - .dw 0x2103, 0xcc17, 0x210f, 0xcc17, 0x21, 0 - .dw 0x2111, 0xcc17, 0x2111, 0xcc17, 0x21, 0 - .dw 0x2113, 0xcc17, 0x213f, 0xcc17, 0x21, 0 - .dw 0x2141, 0xcc17, 0x2141, 0xcc17, 0x21, 0 - .dw 0x2143, 0xcc17, 0x214f, 0xcc17, 0x21, 0 - .dw 0x2151, 0xcc17, 0x2151, 0xcc17, 0x21, 0 - .dw 0x2153, 0xcc17, 0x217f, 0xcc17, 0x21, 0 - .dw 0x2181, 0xcc17, 0x2181, 0xcc17, 0x21, 0 - .dw 0x2183, 0xcc17, 0x218f, 0xcc17, 0x21, 0 - .dw 0x2191, 0xcc17, 0x2191, 0xcc17, 0x21, 0 - .dw 0x2193, 0xcc17, 0x21bf, 0xcc17, 0x21, 0 - .dw 0x21c1, 0xcc17, 0x21c1, 0xcc17, 0x21, 0 - .dw 0x21c3, 0xcc17, 0x21cf, 0xcc17, 0x21, 0 - .dw 0x21d1, 0xcc17, 0x21d1, 0xcc17, 0x21, 0 - .dw 0x21d3, 0xcc17, 0x21ff, 0xcc17, 0x21, 0 - .dw 0x2201, 0xcc17, 0x2201, 0xcc17, 0x21, 0 - .dw 0x2203, 0xcc17, 0x220f, 0xcc17, 0x21, 0 - .dw 0x2211, 0xcc17, 0x2211, 0xcc17, 0x21, 0 - .dw 0x2213, 0xcc17, 0x223f, 0xcc17, 0x21, 0 - .dw 0x2241, 0xcc17, 0x2241, 0xcc17, 0x21, 0 - .dw 0x2243, 0xcc17, 0x224f, 0xcc17, 0x21, 0 - .dw 0x2251, 0xcc17, 0x2251, 0xcc17, 0x21, 0 - .dw 0x2253, 0xcc17, 0x227f, 0xcc17, 0x21, 0 - .dw 0x2281, 0xcc17, 0x2281, 0xcc17, 0x21, 0 - .dw 0x2283, 0xcc17, 0x228f, 0xcc17, 0x21, 0 - .dw 0x2291, 0xcc17, 0x2291, 0xcc17, 0x21, 0 - .dw 0x2293, 0xcc17, 0x22bf, 0xcc17, 0x21, 0 - .dw 0x22c1, 0xcc17, 0x22c1, 0xcc17, 0x21, 0 - .dw 0x22c3, 0xcc17, 0x22cf, 0xcc17, 0x21, 0 - .dw 0x22d1, 0xcc17, 0x22d1, 0xcc17, 0x21, 0 - .dw 0x22d3, 0xcc17, 0x22ff, 0xcc17, 0x21, 0 - .dw 0x2301, 0xcc17, 0x2301, 0xcc17, 0x21, 0 - .dw 0x2303, 0xcc17, 0x230f, 0xcc17, 0x21, 0 - .dw 0x2311, 0xcc17, 0x2311, 0xcc17, 0x21, 0 - .dw 0x2313, 0xcc17, 0x233f, 0xcc17, 0x21, 0 - .dw 0x2341, 0xcc17, 0x2341, 0xcc17, 0x21, 0 - .dw 0x2343, 0xcc17, 0x234f, 0xcc17, 0x21, 0 - .dw 0x2351, 0xcc17, 0x2351, 0xcc17, 0x21, 0 - .dw 0x2353, 0xcc17, 0x237f, 0xcc17, 0x21, 0 - .dw 0x2381, 0xcc17, 0x2381, 0xcc17, 0x21, 0 - .dw 0x2383, 0xcc17, 0x238f, 0xcc17, 0x21, 0 - .dw 0x2391, 0xcc17, 0x2391, 0xcc17, 0x21, 0 - .dw 0x2393, 0xcc17, 0x23bf, 0xcc17, 0x21, 0 - .dw 0x23c1, 0xcc17, 0x23c1, 0xcc17, 0x21, 0 - .dw 0x23c3, 0xcc17, 0x23cf, 0xcc17, 0x21, 0 - .dw 0x23d1, 0xcc17, 0x23d1, 0xcc17, 0x21, 0 - .dw 0x23d3, 0xcc17, 0x23ff, 0xcc17, 0x21, 0 - .dw 0x2401, 0xcc17, 0x2401, 0xcc17, 0x21, 0 - .dw 0x2403, 0xcc17, 0x240f, 0xcc17, 0x21, 0 - .dw 0x2411, 0xcc17, 0x2411, 0xcc17, 0x21, 0 - .dw 0x2413, 0xcc17, 0x243f, 0xcc17, 0x21, 0 - .dw 0x2441, 0xcc17, 0x2441, 0xcc17, 0x21, 0 - .dw 0x2443, 0xcc17, 0x244f, 0xcc17, 0x21, 0 - .dw 0x2451, 0xcc17, 0x2451, 0xcc17, 0x21, 0 - .dw 0x2453, 0xcc17, 0x247f, 0xcc17, 0x21, 0 - .dw 0x2481, 0xcc17, 0x2481, 0xcc17, 0x21, 0 - .dw 0x2483, 0xcc17, 0x248f, 0xcc17, 0x21, 0 - .dw 0x2491, 0xcc17, 0x2491, 0xcc17, 0x21, 0 - .dw 0x2493, 0xcc17, 0x24bf, 0xcc17, 0x21, 0 - .dw 0x24c1, 0xcc17, 0x24c1, 0xcc17, 0x21, 0 - .dw 0x24c3, 0xcc17, 0x24cf, 0xcc17, 0x21, 0 - .dw 0x24d1, 0xcc17, 0x24d1, 0xcc17, 0x21, 0 - .dw 0x24d3, 0xcc17, 0x24ff, 0xcc17, 0x21, 0 - .dw 0x2501, 0xcc17, 0x2501, 0xcc17, 0x21, 0 - .dw 0x2503, 0xcc17, 0x250f, 0xcc17, 0x21, 0 - .dw 0x2511, 0xcc17, 0x2511, 0xcc17, 0x21, 0 - .dw 0x2513, 0xcc17, 0x253f, 0xcc17, 0x21, 0 - .dw 0x2541, 0xcc17, 0x2541, 0xcc17, 0x21, 0 - .dw 0x2543, 0xcc17, 0x254f, 0xcc17, 0x21, 0 - .dw 0x2551, 0xcc17, 0x2551, 0xcc17, 0x21, 0 - .dw 0x2553, 0xcc17, 0x257f, 0xcc17, 0x21, 0 - .dw 0x2581, 0xcc17, 0x2581, 0xcc17, 0x21, 0 - .dw 0x2583, 0xcc17, 0x258f, 0xcc17, 0x21, 0 - .dw 0x2591, 0xcc17, 0x2591, 0xcc17, 0x21, 0 - .dw 0x2593, 0xcc17, 0x25bf, 0xcc17, 0x21, 0 - .dw 0x25c1, 0xcc17, 0x25c1, 0xcc17, 0x21, 0 - .dw 0x25c3, 0xcc17, 0x25cf, 0xcc17, 0x21, 0 - .dw 0x25d1, 0xcc17, 0x25d1, 0xcc17, 0x21, 0 - .dw 0x25d3, 0xcc17, 0x25ff, 0xcc17, 0x21, 0 - .dw 0x2601, 0xcc17, 0x2601, 0xcc17, 0x21, 0 - .dw 0x2603, 0xcc17, 0x260f, 0xcc17, 0x21, 0 - .dw 0x2611, 0xcc17, 0x2611, 0xcc17, 0x21, 0 - .dw 0x2613, 0xcc17, 0x263f, 0xcc17, 0x21, 0 - .dw 0x2641, 0xcc17, 0x2641, 0xcc17, 0x21, 0 - .dw 0x2643, 0xcc17, 0x264f, 0xcc17, 0x21, 0 - .dw 0x2651, 0xcc17, 0x2651, 0xcc17, 0x21, 0 - .dw 0x2653, 0xcc17, 0x267f, 0xcc17, 0x21, 0 - .dw 0x2681, 0xcc17, 0x2681, 0xcc17, 0x21, 0 - .dw 0x2683, 0xcc17, 0x268f, 0xcc17, 0x21, 0 - .dw 0x2691, 0xcc17, 0x2691, 0xcc17, 0x21, 0 - .dw 0x2693, 0xcc17, 0x26bf, 0xcc17, 0x21, 0 - .dw 0x26c1, 0xcc17, 0x26c1, 0xcc17, 0x21, 0 - .dw 0x26c3, 0xcc17, 0x26cf, 0xcc17, 0x21, 0 - .dw 0x26d1, 0xcc17, 0x26d1, 0xcc17, 0x21, 0 - .dw 0x26d3, 0xcc17, 0x26ff, 0xcc17, 0x21, 0 - .dw 0x2701, 0xcc17, 0x2701, 0xcc17, 0x21, 0 - .dw 0x2703, 0xcc17, 0x270f, 0xcc17, 0x21, 0 - .dw 0x2711, 0xcc17, 0x2711, 0xcc17, 0x21, 0 - .dw 0x2713, 0xcc17, 0x273f, 0xcc17, 0x21, 0 - .dw 0x2741, 0xcc17, 0x2741, 0xcc17, 0x21, 0 - .dw 0x2743, 0xcc17, 0x274f, 0xcc17, 0x21, 0 - .dw 0x2751, 0xcc17, 0x2751, 0xcc17, 0x21, 0 - .dw 0x2753, 0xcc17, 0x277f, 0xcc17, 0x21, 0 - .dw 0x2781, 0xcc17, 0x2781, 0xcc17, 0x21, 0 - .dw 0x2783, 0xcc17, 0x278f, 0xcc17, 0x21, 0 - .dw 0x2791, 0xcc17, 0x2791, 0xcc17, 0x21, 0 - .dw 0x2793, 0xcc17, 0x27bf, 0xcc17, 0x21, 0 - .dw 0x27c1, 0xcc17, 0x27c1, 0xcc17, 0x21, 0 - .dw 0x27c3, 0xcc17, 0x27cf, 0xcc17, 0x21, 0 - .dw 0x27d1, 0xcc17, 0x27d1, 0xcc17, 0x21, 0 - .dw 0x27d3, 0xcc17, 0x27ff, 0xcc17, 0x21, 0 - .dw 0x2801, 0xcc17, 0x2801, 0xcc17, 0x21, 0 - .dw 0x2803, 0xcc17, 0x280f, 0xcc17, 0x21, 0 - .dw 0x2811, 0xcc17, 0x2811, 0xcc17, 0x21, 0 - .dw 0x2813, 0xcc17, 0x283f, 0xcc17, 0x21, 0 - .dw 0x2841, 0xcc17, 0x2841, 0xcc17, 0x21, 0 - .dw 0x2843, 0xcc17, 0x284f, 0xcc17, 0x21, 0 - .dw 0x2851, 0xcc17, 0x2851, 0xcc17, 0x21, 0 - .dw 0x2853, 0xcc17, 0x287f, 0xcc17, 0x21, 0 - .dw 0x2881, 0xcc17, 0x2881, 0xcc17, 0x21, 0 - .dw 0x2883, 0xcc17, 0x288f, 0xcc17, 0x21, 0 - .dw 0x2891, 0xcc17, 0x2891, 0xcc17, 0x21, 0 - .dw 0x2893, 0xcc17, 0x28bf, 0xcc17, 0x21, 0 - .dw 0x28c1, 0xcc17, 0x28c1, 0xcc17, 0x21, 0 - .dw 0x28c3, 0xcc17, 0x28cf, 0xcc17, 0x21, 0 - .dw 0x28d1, 0xcc17, 0x28d1, 0xcc17, 0x21, 0 - .dw 0x28d3, 0xcc17, 0x28ff, 0xcc17, 0x21, 0 - .dw 0x2901, 0xcc17, 0x2901, 0xcc17, 0x21, 0 - .dw 0x2903, 0xcc17, 0x290f, 0xcc17, 0x21, 0 - .dw 0x2911, 0xcc17, 0x2911, 0xcc17, 0x21, 0 - .dw 0x2913, 0xcc17, 0x293f, 0xcc17, 0x21, 0 - .dw 0x2941, 0xcc17, 0x2941, 0xcc17, 0x21, 0 - .dw 0x2943, 0xcc17, 0x294f, 0xcc17, 0x21, 0 - .dw 0x2951, 0xcc17, 0x2951, 0xcc17, 0x21, 0 - .dw 0x2953, 0xcc17, 0x297f, 0xcc17, 0x21, 0 - .dw 0x2981, 0xcc17, 0x2981, 0xcc17, 0x21, 0 - .dw 0x2983, 0xcc17, 0x298f, 0xcc17, 0x21, 0 - .dw 0x2991, 0xcc17, 0x2991, 0xcc17, 0x21, 0 - .dw 0x2993, 0xcc17, 0x29bf, 0xcc17, 0x21, 0 - .dw 0x29c1, 0xcc17, 0x29c1, 0xcc17, 0x21, 0 - .dw 0x29c3, 0xcc17, 0x29cf, 0xcc17, 0x21, 0 - .dw 0x29d1, 0xcc17, 0x29d1, 0xcc17, 0x21, 0 - .dw 0x29d3, 0xcc17, 0x29ff, 0xcc17, 0x21, 0 - .dw 0x2a01, 0xcc17, 0x2a01, 0xcc17, 0x21, 0 - .dw 0x2a03, 0xcc17, 0x2a0f, 0xcc17, 0x21, 0 - .dw 0x2a11, 0xcc17, 0x2a11, 0xcc17, 0x21, 0 - .dw 0x2a13, 0xcc17, 0x2a3f, 0xcc17, 0x21, 0 - .dw 0x2a41, 0xcc17, 0x2a41, 0xcc17, 0x21, 0 - .dw 0x2a43, 0xcc17, 0x2a4f, 0xcc17, 0x21, 0 - .dw 0x2a51, 0xcc17, 0x2a51, 0xcc17, 0x21, 0 - .dw 0x2a53, 0xcc17, 0x2a7f, 0xcc17, 0x21, 0 - .dw 0x2a81, 0xcc17, 0x2a81, 0xcc17, 0x21, 0 - .dw 0x2a83, 0xcc17, 0x2a8f, 0xcc17, 0x21, 0 - .dw 0x2a91, 0xcc17, 0x2a91, 0xcc17, 0x21, 0 - .dw 0x2a93, 0xcc17, 0x2abf, 0xcc17, 0x21, 0 - .dw 0x2ac1, 0xcc17, 0x2ac1, 0xcc17, 0x21, 0 - .dw 0x2ac3, 0xcc17, 0x2acf, 0xcc17, 0x21, 0 - .dw 0x2ad1, 0xcc17, 0x2ad1, 0xcc17, 0x21, 0 - .dw 0x2ad3, 0xcc17, 0x2aff, 0xcc17, 0x21, 0 - .dw 0x2b01, 0xcc17, 0x2b01, 0xcc17, 0x21, 0 - .dw 0x2b03, 0xcc17, 0x2b0f, 0xcc17, 0x21, 0 - .dw 0x2b11, 0xcc17, 0x2b11, 0xcc17, 0x21, 0 - .dw 0x2b13, 0xcc17, 0x2b3f, 0xcc17, 0x21, 0 - .dw 0x2b41, 0xcc17, 0x2b41, 0xcc17, 0x21, 0 - .dw 0x2b43, 0xcc17, 0x2b4f, 0xcc17, 0x21, 0 - .dw 0x2b51, 0xcc17, 0x2b51, 0xcc17, 0x21, 0 - .dw 0x2b53, 0xcc17, 0x2b7f, 0xcc17, 0x21, 0 - .dw 0x2b81, 0xcc17, 0x2b81, 0xcc17, 0x21, 0 - .dw 0x2b83, 0xcc17, 0x2b8f, 0xcc17, 0x21, 0 - .dw 0x2b91, 0xcc17, 0x2b91, 0xcc17, 0x21, 0 - .dw 0x2b93, 0xcc17, 0x2bbf, 0xcc17, 0x21, 0 - .dw 0x2bc1, 0xcc17, 0x2bc1, 0xcc17, 0x21, 0 - .dw 0x2bc3, 0xcc17, 0x2bcf, 0xcc17, 0x21, 0 - .dw 0x2bd1, 0xcc17, 0x2bd1, 0xcc17, 0x21, 0 - .dw 0x2bd3, 0xcc17, 0x2bff, 0xcc17, 0x21, 0 - .dw 0x2c01, 0xcc17, 0x2c01, 0xcc17, 0x21, 0 - .dw 0x2c03, 0xcc17, 0x2c0f, 0xcc17, 0x21, 0 - .dw 0x2c11, 0xcc17, 0x2c11, 0xcc17, 0x21, 0 - .dw 0x2c13, 0xcc17, 0x2c3f, 0xcc17, 0x21, 0 - .dw 0x2c41, 0xcc17, 0x2c41, 0xcc17, 0x21, 0 - .dw 0x2c43, 0xcc17, 0x2c4f, 0xcc17, 0x21, 0 - .dw 0x2c51, 0xcc17, 0x2c51, 0xcc17, 0x21, 0 - .dw 0x2c53, 0xcc17, 0x2c7f, 0xcc17, 0x21, 0 - .dw 0x2c81, 0xcc17, 0x2c81, 0xcc17, 0x21, 0 - .dw 0x2c83, 0xcc17, 0x2c8f, 0xcc17, 0x21, 0 - .dw 0x2c91, 0xcc17, 0x2c91, 0xcc17, 0x21, 0 - .dw 0x2c93, 0xcc17, 0x2cbf, 0xcc17, 0x21, 0 - .dw 0x2cc1, 0xcc17, 0x2cc1, 0xcc17, 0x21, 0 - .dw 0x2cc3, 0xcc17, 0x2ccf, 0xcc17, 0x21, 0 - .dw 0x2cd1, 0xcc17, 0x2cd1, 0xcc17, 0x21, 0 - .dw 0x2cd3, 0xcc17, 0x2cff, 0xcc17, 0x21, 0 - .dw 0x2d01, 0xcc17, 0x2d01, 0xcc17, 0x21, 0 - .dw 0x2d03, 0xcc17, 0x2d0f, 0xcc17, 0x21, 0 - .dw 0x2d11, 0xcc17, 0x2d11, 0xcc17, 0x21, 0 - .dw 0x2d13, 0xcc17, 0x2d3f, 0xcc17, 0x21, 0 - .dw 0x2d41, 0xcc17, 0x2d41, 0xcc17, 0x21, 0 - .dw 0x2d43, 0xcc17, 0x2d4f, 0xcc17, 0x21, 0 - .dw 0x2d51, 0xcc17, 0x2d51, 0xcc17, 0x21, 0 - .dw 0x2d53, 0xcc17, 0x2d7f, 0xcc17, 0x21, 0 - .dw 0x2d81, 0xcc17, 0x2d81, 0xcc17, 0x21, 0 - .dw 0x2d83, 0xcc17, 0x2d8f, 0xcc17, 0x21, 0 - .dw 0x2d91, 0xcc17, 0x2d91, 0xcc17, 0x21, 0 - .dw 0x2d93, 0xcc17, 0x2dbf, 0xcc17, 0x21, 0 - .dw 0x2dc1, 0xcc17, 0x2dc1, 0xcc17, 0x21, 0 - .dw 0x2dc3, 0xcc17, 0x2dcf, 0xcc17, 0x21, 0 - .dw 0x2dd1, 0xcc17, 0x2dd1, 0xcc17, 0x21, 0 - .dw 0x2dd3, 0xcc17, 0x2dff, 0xcc17, 0x21, 0 - .dw 0x2e01, 0xcc17, 0x2e01, 0xcc17, 0x21, 0 - .dw 0x2e03, 0xcc17, 0x2e0f, 0xcc17, 0x21, 0 - .dw 0x2e11, 0xcc17, 0x2e11, 0xcc17, 0x21, 0 - .dw 0x2e13, 0xcc17, 0x2e3f, 0xcc17, 0x21, 0 - .dw 0x2e41, 0xcc17, 0x2e41, 0xcc17, 0x21, 0 - .dw 0x2e43, 0xcc17, 0x2e4f, 0xcc17, 0x21, 0 - .dw 0x2e51, 0xcc17, 0x2e51, 0xcc17, 0x21, 0 - .dw 0x2e53, 0xcc17, 0x2e7f, 0xcc17, 0x21, 0 - .dw 0x2e81, 0xcc17, 0x2e81, 0xcc17, 0x21, 0 - .dw 0x2e83, 0xcc17, 0x2e8f, 0xcc17, 0x21, 0 - .dw 0x2e91, 0xcc17, 0x2e91, 0xcc17, 0x21, 0 - .dw 0x2e93, 0xcc17, 0x2ebf, 0xcc17, 0x21, 0 - .dw 0x2ec1, 0xcc17, 0x2ec1, 0xcc17, 0x21, 0 - .dw 0x2ec3, 0xcc17, 0x2ecf, 0xcc17, 0x21, 0 - .dw 0x2ed1, 0xcc17, 0x2ed1, 0xcc17, 0x21, 0 - .dw 0x2ed3, 0xcc17, 0x2eff, 0xcc17, 0x21, 0 - .dw 0x2f01, 0xcc17, 0x2f01, 0xcc17, 0x21, 0 - .dw 0x2f03, 0xcc17, 0x2f0f, 0xcc17, 0x21, 0 - .dw 0x2f11, 0xcc17, 0x2f11, 0xcc17, 0x21, 0 - .dw 0x2f13, 0xcc17, 0x2f3f, 0xcc17, 0x21, 0 - .dw 0x2f41, 0xcc17, 0x2f41, 0xcc17, 0x21, 0 - .dw 0x2f43, 0xcc17, 0x2f4f, 0xcc17, 0x21, 0 - .dw 0x2f51, 0xcc17, 0x2f51, 0xcc17, 0x21, 0 - .dw 0x2f53, 0xcc17, 0x2f7f, 0xcc17, 0x21, 0 - .dw 0x2f81, 0xcc17, 0x2f81, 0xcc17, 0x21, 0 - .dw 0x2f83, 0xcc17, 0x2f8f, 0xcc17, 0x21, 0 - .dw 0x2f91, 0xcc17, 0x2f91, 0xcc17, 0x21, 0 - .dw 0x2f93, 0xcc17, 0x2fbf, 0xcc17, 0x21, 0 - .dw 0x2fc1, 0xcc17, 0x2fc1, 0xcc17, 0x21, 0 - .dw 0x2fc3, 0xcc17, 0x2fcf, 0xcc17, 0x21, 0 - .dw 0x2fd1, 0xcc17, 0x2fd1, 0xcc17, 0x21, 0 - .dw 0x2fd3, 0xcc17, 0xffff, 0xcc17, 0x21, 0 - .dw 0x1000, 0xcc18, 0x3fff, 0xcc18, 0x21, 0 - .dw 0x4000, 0xcc18, 0x4000, 0xcc18, 0x22, 0 - .dw 0x4001, 0xcc18, 0x4001, 0xcc18, 0x21, 0 - .dw 0x4002, 0xcc18, 0x4002, 0xcc18, 0x22, 0 - .dw 0x4003, 0xcc18, 0x400f, 0xcc18, 0x21, 0 - .dw 0x4010, 0xcc18, 0x4010, 0xcc18, 0x22, 0 - .dw 0x4011, 0xcc18, 0x4011, 0xcc18, 0x21, 0 - .dw 0x4012, 0xcc18, 0x4012, 0xcc18, 0x22, 0 - .dw 0x4013, 0xcc18, 0x403f, 0xcc18, 0x21, 0 - .dw 0x4041, 0xcc18, 0x4041, 0xcc18, 0x21, 0 - .dw 0x4043, 0xcc18, 0x404f, 0xcc18, 0x21, 0 - .dw 0x4051, 0xcc18, 0x4051, 0xcc18, 0x21, 0 - .dw 0x4053, 0xcc18, 0x407f, 0xcc18, 0x21, 0 - .dw 0x4081, 0xcc18, 0x4081, 0xcc18, 0x21, 0 - .dw 0x4083, 0xcc18, 0x408f, 0xcc18, 0x21, 0 - .dw 0x4091, 0xcc18, 0x4091, 0xcc18, 0x21, 0 - .dw 0x4093, 0xcc18, 0x40bf, 0xcc18, 0x21, 0 - .dw 0x40c1, 0xcc18, 0x40c1, 0xcc18, 0x21, 0 - .dw 0x40c3, 0xcc18, 0x40cf, 0xcc18, 0x21, 0 - .dw 0x40d1, 0xcc18, 0x40d1, 0xcc18, 0x21, 0 - .dw 0x40d3, 0xcc18, 0x40ff, 0xcc18, 0x21, 0 - .dw 0x4101, 0xcc18, 0x4101, 0xcc18, 0x21, 0 - .dw 0x4103, 0xcc18, 0x410f, 0xcc18, 0x21, 0 - .dw 0x4111, 0xcc18, 0x4111, 0xcc18, 0x21, 0 - .dw 0x4113, 0xcc18, 0x413f, 0xcc18, 0x21, 0 - .dw 0x4141, 0xcc18, 0x4141, 0xcc18, 0x21, 0 - .dw 0x4143, 0xcc18, 0x414f, 0xcc18, 0x21, 0 - .dw 0x4151, 0xcc18, 0x4151, 0xcc18, 0x21, 0 - .dw 0x4153, 0xcc18, 0x417f, 0xcc18, 0x21, 0 - .dw 0x4181, 0xcc18, 0x4181, 0xcc18, 0x21, 0 - .dw 0x4183, 0xcc18, 0x418f, 0xcc18, 0x21, 0 - .dw 0x4191, 0xcc18, 0x4191, 0xcc18, 0x21, 0 - .dw 0x4193, 0xcc18, 0x41bf, 0xcc18, 0x21, 0 - .dw 0x41c1, 0xcc18, 0x41c1, 0xcc18, 0x21, 0 - .dw 0x41c3, 0xcc18, 0x41cf, 0xcc18, 0x21, 0 - .dw 0x41d1, 0xcc18, 0x41d1, 0xcc18, 0x21, 0 - .dw 0x41d3, 0xcc18, 0x41ff, 0xcc18, 0x21, 0 - .dw 0x4201, 0xcc18, 0x4201, 0xcc18, 0x21, 0 - .dw 0x4203, 0xcc18, 0x420f, 0xcc18, 0x21, 0 - .dw 0x4211, 0xcc18, 0x4211, 0xcc18, 0x21, 0 - .dw 0x4213, 0xcc18, 0x423f, 0xcc18, 0x21, 0 - .dw 0x4240, 0xcc18, 0x4240, 0xcc18, 0x22, 0 - .dw 0x4241, 0xcc18, 0x4241, 0xcc18, 0x21, 0 - .dw 0x4242, 0xcc18, 0x4242, 0xcc18, 0x22, 0 - .dw 0x4243, 0xcc18, 0x424f, 0xcc18, 0x21, 0 - .dw 0x4250, 0xcc18, 0x4250, 0xcc18, 0x22, 0 - .dw 0x4251, 0xcc18, 0x4251, 0xcc18, 0x21, 0 - .dw 0x4252, 0xcc18, 0x4252, 0xcc18, 0x22, 0 - .dw 0x4253, 0xcc18, 0x427f, 0xcc18, 0x21, 0 - .dw 0x4281, 0xcc18, 0x4281, 0xcc18, 0x21, 0 - .dw 0x4283, 0xcc18, 0x428f, 0xcc18, 0x21, 0 - .dw 0x4291, 0xcc18, 0x4291, 0xcc18, 0x21, 0 - .dw 0x4293, 0xcc18, 0x42bf, 0xcc18, 0x21, 0 - .dw 0x42c1, 0xcc18, 0x42c1, 0xcc18, 0x21, 0 - .dw 0x42c3, 0xcc18, 0x42cf, 0xcc18, 0x21, 0 - .dw 0x42d1, 0xcc18, 0x42d1, 0xcc18, 0x21, 0 - .dw 0x42d3, 0xcc18, 0x42ff, 0xcc18, 0x21, 0 - .dw 0x4301, 0xcc18, 0x4301, 0xcc18, 0x21, 0 - .dw 0x4303, 0xcc18, 0x430f, 0xcc18, 0x21, 0 - .dw 0x4311, 0xcc18, 0x4311, 0xcc18, 0x21, 0 - .dw 0x4313, 0xcc18, 0x433f, 0xcc18, 0x21, 0 - .dw 0x4341, 0xcc18, 0x4341, 0xcc18, 0x21, 0 - .dw 0x4343, 0xcc18, 0x434f, 0xcc18, 0x21, 0 - .dw 0x4351, 0xcc18, 0x4351, 0xcc18, 0x21, 0 - .dw 0x4353, 0xcc18, 0x437f, 0xcc18, 0x21, 0 - .dw 0x4381, 0xcc18, 0x4381, 0xcc18, 0x21, 0 - .dw 0x4383, 0xcc18, 0x438f, 0xcc18, 0x21, 0 - .dw 0x4391, 0xcc18, 0x4391, 0xcc18, 0x21, 0 - .dw 0x4393, 0xcc18, 0x43bf, 0xcc18, 0x21, 0 - .dw 0x43c1, 0xcc18, 0x43c1, 0xcc18, 0x21, 0 - .dw 0x43c3, 0xcc18, 0x43cf, 0xcc18, 0x21, 0 - .dw 0x43d1, 0xcc18, 0x43d1, 0xcc18, 0x21, 0 - .dw 0x43d3, 0xcc18, 0x43ff, 0xcc18, 0x21, 0 - .dw 0x4401, 0xcc18, 0x4401, 0xcc18, 0x21, 0 - .dw 0x4403, 0xcc18, 0x440f, 0xcc18, 0x21, 0 - .dw 0x4411, 0xcc18, 0x4411, 0xcc18, 0x21, 0 - .dw 0x4413, 0xcc18, 0x443f, 0xcc18, 0x21, 0 - .dw 0x4441, 0xcc18, 0x4441, 0xcc18, 0x21, 0 - .dw 0x4443, 0xcc18, 0x444f, 0xcc18, 0x21, 0 - .dw 0x4451, 0xcc18, 0x4451, 0xcc18, 0x21, 0 - .dw 0x4453, 0xcc18, 0x447f, 0xcc18, 0x21, 0 - .dw 0x4480, 0xcc18, 0x4480, 0xcc18, 0x22, 0 - .dw 0x4481, 0xcc18, 0x4481, 0xcc18, 0x21, 0 - .dw 0x4482, 0xcc18, 0x4482, 0xcc18, 0x22, 0 - .dw 0x4483, 0xcc18, 0x448f, 0xcc18, 0x21, 0 - .dw 0x4490, 0xcc18, 0x4490, 0xcc18, 0x22, 0 - .dw 0x4491, 0xcc18, 0x4491, 0xcc18, 0x21, 0 - .dw 0x4492, 0xcc18, 0x4492, 0xcc18, 0x22, 0 - .dw 0x4493, 0xcc18, 0x44bf, 0xcc18, 0x21, 0 - .dw 0x44c1, 0xcc18, 0x44c1, 0xcc18, 0x21, 0 - .dw 0x44c3, 0xcc18, 0x44cf, 0xcc18, 0x21, 0 - .dw 0x44d1, 0xcc18, 0x44d1, 0xcc18, 0x21, 0 - .dw 0x44d3, 0xcc18, 0x44ff, 0xcc18, 0x21, 0 - .dw 0x4501, 0xcc18, 0x4501, 0xcc18, 0x21, 0 - .dw 0x4503, 0xcc18, 0x450f, 0xcc18, 0x21, 0 - .dw 0x4511, 0xcc18, 0x4511, 0xcc18, 0x21, 0 - .dw 0x4513, 0xcc18, 0x453f, 0xcc18, 0x21, 0 - .dw 0x4541, 0xcc18, 0x4541, 0xcc18, 0x21, 0 - .dw 0x4543, 0xcc18, 0x454f, 0xcc18, 0x21, 0 - .dw 0x4551, 0xcc18, 0x4551, 0xcc18, 0x21, 0 - .dw 0x4553, 0xcc18, 0x457f, 0xcc18, 0x21, 0 - .dw 0x4581, 0xcc18, 0x4581, 0xcc18, 0x21, 0 - .dw 0x4583, 0xcc18, 0x458f, 0xcc18, 0x21, 0 - .dw 0x4591, 0xcc18, 0x4591, 0xcc18, 0x21, 0 - .dw 0x4593, 0xcc18, 0x45bf, 0xcc18, 0x21, 0 - .dw 0x45c1, 0xcc18, 0x45c1, 0xcc18, 0x21, 0 - .dw 0x45c3, 0xcc18, 0x45cf, 0xcc18, 0x21, 0 - .dw 0x45d1, 0xcc18, 0x45d1, 0xcc18, 0x21, 0 - .dw 0x45d3, 0xcc18, 0x45ff, 0xcc18, 0x21, 0 - .dw 0x4601, 0xcc18, 0x4601, 0xcc18, 0x21, 0 - .dw 0x4603, 0xcc18, 0x460f, 0xcc18, 0x21, 0 - .dw 0x4611, 0xcc18, 0x4611, 0xcc18, 0x21, 0 - .dw 0x4613, 0xcc18, 0x463f, 0xcc18, 0x21, 0 - .dw 0x4641, 0xcc18, 0x4641, 0xcc18, 0x21, 0 - .dw 0x4643, 0xcc18, 0x464f, 0xcc18, 0x21, 0 - .dw 0x4651, 0xcc18, 0x4651, 0xcc18, 0x21, 0 - .dw 0x4653, 0xcc18, 0x467f, 0xcc18, 0x21, 0 - .dw 0x4681, 0xcc18, 0x4681, 0xcc18, 0x21, 0 - .dw 0x4683, 0xcc18, 0x468f, 0xcc18, 0x21, 0 - .dw 0x4691, 0xcc18, 0x4691, 0xcc18, 0x21, 0 - .dw 0x4693, 0xcc18, 0x46bf, 0xcc18, 0x21, 0 - .dw 0x46c0, 0xcc18, 0x46c0, 0xcc18, 0x22, 0 - .dw 0x46c1, 0xcc18, 0x46c1, 0xcc18, 0x21, 0 - .dw 0x46c2, 0xcc18, 0x46c2, 0xcc18, 0x22, 0 - .dw 0x46c3, 0xcc18, 0x46cf, 0xcc18, 0x21, 0 - .dw 0x46d0, 0xcc18, 0x46d0, 0xcc18, 0x22, 0 - .dw 0x46d1, 0xcc18, 0x46d1, 0xcc18, 0x21, 0 - .dw 0x46d2, 0xcc18, 0x46d2, 0xcc18, 0x22, 0 - .dw 0x46d3, 0xcc18, 0x46ff, 0xcc18, 0x21, 0 - .dw 0x4701, 0xcc18, 0x4701, 0xcc18, 0x21, 0 - .dw 0x4703, 0xcc18, 0x470f, 0xcc18, 0x21, 0 - .dw 0x4711, 0xcc18, 0x4711, 0xcc18, 0x21, 0 - .dw 0x4713, 0xcc18, 0x473f, 0xcc18, 0x21, 0 - .dw 0x4741, 0xcc18, 0x4741, 0xcc18, 0x21, 0 - .dw 0x4743, 0xcc18, 0x474f, 0xcc18, 0x21, 0 - .dw 0x4751, 0xcc18, 0x4751, 0xcc18, 0x21, 0 - .dw 0x4753, 0xcc18, 0x477f, 0xcc18, 0x21, 0 - .dw 0x4781, 0xcc18, 0x4781, 0xcc18, 0x21, 0 - .dw 0x4783, 0xcc18, 0x478f, 0xcc18, 0x21, 0 - .dw 0x4791, 0xcc18, 0x4791, 0xcc18, 0x21, 0 - .dw 0x4793, 0xcc18, 0x47bf, 0xcc18, 0x21, 0 - .dw 0x47c1, 0xcc18, 0x47c1, 0xcc18, 0x21, 0 - .dw 0x47c3, 0xcc18, 0x47cf, 0xcc18, 0x21, 0 - .dw 0x47d1, 0xcc18, 0x47d1, 0xcc18, 0x21, 0 - .dw 0x47d3, 0xcc18, 0x47ff, 0xcc18, 0x21, 0 - .dw 0x4801, 0xcc18, 0x4801, 0xcc18, 0x21, 0 - .dw 0x4803, 0xcc18, 0x480f, 0xcc18, 0x21, 0 - .dw 0x4811, 0xcc18, 0x4811, 0xcc18, 0x21, 0 - .dw 0x4813, 0xcc18, 0x483f, 0xcc18, 0x21, 0 - .dw 0x4841, 0xcc18, 0x4841, 0xcc18, 0x21, 0 - .dw 0x4843, 0xcc18, 0x484f, 0xcc18, 0x21, 0 - .dw 0x4851, 0xcc18, 0x4851, 0xcc18, 0x21, 0 - .dw 0x4853, 0xcc18, 0x487f, 0xcc18, 0x21, 0 - .dw 0x4881, 0xcc18, 0x4881, 0xcc18, 0x21, 0 - .dw 0x4883, 0xcc18, 0x488f, 0xcc18, 0x21, 0 - .dw 0x4891, 0xcc18, 0x4891, 0xcc18, 0x21, 0 - .dw 0x4893, 0xcc18, 0x48bf, 0xcc18, 0x21, 0 - .dw 0x48c1, 0xcc18, 0x48c1, 0xcc18, 0x21, 0 - .dw 0x48c3, 0xcc18, 0x48cf, 0xcc18, 0x21, 0 - .dw 0x48d1, 0xcc18, 0x48d1, 0xcc18, 0x21, 0 - .dw 0x48d3, 0xcc18, 0x48ff, 0xcc18, 0x21, 0 - .dw 0x4900, 0xcc18, 0x4900, 0xcc18, 0x22, 0 - .dw 0x4901, 0xcc18, 0x4901, 0xcc18, 0x21, 0 - .dw 0x4902, 0xcc18, 0x4902, 0xcc18, 0x22, 0 - .dw 0x4903, 0xcc18, 0x490f, 0xcc18, 0x21, 0 - .dw 0x4910, 0xcc18, 0x4910, 0xcc18, 0x22, 0 - .dw 0x4911, 0xcc18, 0x4911, 0xcc18, 0x21, 0 - .dw 0x4912, 0xcc18, 0x4912, 0xcc18, 0x22, 0 - .dw 0x4913, 0xcc18, 0x493f, 0xcc18, 0x21, 0 - .dw 0x4941, 0xcc18, 0x4941, 0xcc18, 0x21, 0 - .dw 0x4943, 0xcc18, 0x494f, 0xcc18, 0x21, 0 - .dw 0x4951, 0xcc18, 0x4951, 0xcc18, 0x21, 0 - .dw 0x4953, 0xcc18, 0x497f, 0xcc18, 0x21, 0 - .dw 0x4981, 0xcc18, 0x4981, 0xcc18, 0x21, 0 - .dw 0x4983, 0xcc18, 0x498f, 0xcc18, 0x21, 0 - .dw 0x4991, 0xcc18, 0x4991, 0xcc18, 0x21, 0 - .dw 0x4993, 0xcc18, 0x49bf, 0xcc18, 0x21, 0 - .dw 0x49c1, 0xcc18, 0x49c1, 0xcc18, 0x21, 0 - .dw 0x49c3, 0xcc18, 0x49cf, 0xcc18, 0x21, 0 - .dw 0x49d1, 0xcc18, 0x49d1, 0xcc18, 0x21, 0 - .dw 0x49d3, 0xcc18, 0x49ff, 0xcc18, 0x21, 0 - .dw 0x4a01, 0xcc18, 0x4a01, 0xcc18, 0x21, 0 - .dw 0x4a03, 0xcc18, 0x4a0f, 0xcc18, 0x21, 0 - .dw 0x4a11, 0xcc18, 0x4a11, 0xcc18, 0x21, 0 - .dw 0x4a13, 0xcc18, 0x4a3f, 0xcc18, 0x21, 0 - .dw 0x4a41, 0xcc18, 0x4a41, 0xcc18, 0x21, 0 - .dw 0x4a43, 0xcc18, 0x4a4f, 0xcc18, 0x21, 0 - .dw 0x4a51, 0xcc18, 0x4a51, 0xcc18, 0x21, 0 - .dw 0x4a53, 0xcc18, 0x4a7f, 0xcc18, 0x21, 0 - .dw 0x4a81, 0xcc18, 0x4a81, 0xcc18, 0x21, 0 - .dw 0x4a83, 0xcc18, 0x4a8f, 0xcc18, 0x21, 0 - .dw 0x4a91, 0xcc18, 0x4a91, 0xcc18, 0x21, 0 - .dw 0x4a93, 0xcc18, 0x4abf, 0xcc18, 0x21, 0 - .dw 0x4ac1, 0xcc18, 0x4ac1, 0xcc18, 0x21, 0 - .dw 0x4ac3, 0xcc18, 0x4acf, 0xcc18, 0x21, 0 - .dw 0x4ad1, 0xcc18, 0x4ad1, 0xcc18, 0x21, 0 - .dw 0x4ad3, 0xcc18, 0x4aff, 0xcc18, 0x21, 0 - .dw 0x4b01, 0xcc18, 0x4b01, 0xcc18, 0x21, 0 - .dw 0x4b03, 0xcc18, 0x4b0f, 0xcc18, 0x21, 0 - .dw 0x4b11, 0xcc18, 0x4b11, 0xcc18, 0x21, 0 - .dw 0x4b13, 0xcc18, 0x4b3f, 0xcc18, 0x21, 0 - .dw 0x4b40, 0xcc18, 0x4b40, 0xcc18, 0x22, 0 - .dw 0x4b41, 0xcc18, 0x4b41, 0xcc18, 0x21, 0 - .dw 0x4b42, 0xcc18, 0x4b42, 0xcc18, 0x22, 0 - .dw 0x4b43, 0xcc18, 0x4b4f, 0xcc18, 0x21, 0 - .dw 0x4b50, 0xcc18, 0x4b50, 0xcc18, 0x22, 0 - .dw 0x4b51, 0xcc18, 0x4b51, 0xcc18, 0x21, 0 - .dw 0x4b52, 0xcc18, 0x4b52, 0xcc18, 0x22, 0 - .dw 0x4b53, 0xcc18, 0x4b7f, 0xcc18, 0x21, 0 - .dw 0x4b81, 0xcc18, 0x4b81, 0xcc18, 0x21, 0 - .dw 0x4b83, 0xcc18, 0x4b8f, 0xcc18, 0x21, 0 - .dw 0x4b91, 0xcc18, 0x4b91, 0xcc18, 0x21, 0 - .dw 0x4b93, 0xcc18, 0x4bbf, 0xcc18, 0x21, 0 - .dw 0x4bc1, 0xcc18, 0x4bc1, 0xcc18, 0x21, 0 - .dw 0x4bc3, 0xcc18, 0x4bcf, 0xcc18, 0x21, 0 - .dw 0x4bd1, 0xcc18, 0x4bd1, 0xcc18, 0x21, 0 - .dw 0x4bd3, 0xcc18, 0x4bff, 0xcc18, 0x21, 0 - .dw 0x4c01, 0xcc18, 0x4c01, 0xcc18, 0x21, 0 - .dw 0x4c03, 0xcc18, 0x4c0f, 0xcc18, 0x21, 0 - .dw 0x4c11, 0xcc18, 0x4c11, 0xcc18, 0x21, 0 - .dw 0x4c13, 0xcc18, 0x4c3f, 0xcc18, 0x21, 0 - .dw 0x4c41, 0xcc18, 0x4c41, 0xcc18, 0x21, 0 - .dw 0x4c43, 0xcc18, 0x4c4f, 0xcc18, 0x21, 0 - .dw 0x4c51, 0xcc18, 0x4c51, 0xcc18, 0x21, 0 - .dw 0x4c53, 0xcc18, 0x4c7f, 0xcc18, 0x21, 0 - .dw 0x4c81, 0xcc18, 0x4c81, 0xcc18, 0x21, 0 - .dw 0x4c83, 0xcc18, 0x4c8f, 0xcc18, 0x21, 0 - .dw 0x4c91, 0xcc18, 0x4c91, 0xcc18, 0x21, 0 - .dw 0x4c93, 0xcc18, 0x4cbf, 0xcc18, 0x21, 0 - .dw 0x4cc1, 0xcc18, 0x4cc1, 0xcc18, 0x21, 0 - .dw 0x4cc3, 0xcc18, 0x4ccf, 0xcc18, 0x21, 0 - .dw 0x4cd1, 0xcc18, 0x4cd1, 0xcc18, 0x21, 0 - .dw 0x4cd3, 0xcc18, 0x4cff, 0xcc18, 0x21, 0 - .dw 0x4d01, 0xcc18, 0x4d01, 0xcc18, 0x21, 0 - .dw 0x4d03, 0xcc18, 0x4d0f, 0xcc18, 0x21, 0 - .dw 0x4d11, 0xcc18, 0x4d11, 0xcc18, 0x21, 0 - .dw 0x4d13, 0xcc18, 0x4d3f, 0xcc18, 0x21, 0 - .dw 0x4d41, 0xcc18, 0x4d41, 0xcc18, 0x21, 0 - .dw 0x4d43, 0xcc18, 0x4d4f, 0xcc18, 0x21, 0 - .dw 0x4d51, 0xcc18, 0x4d51, 0xcc18, 0x21, 0 - .dw 0x4d53, 0xcc18, 0x4d7f, 0xcc18, 0x21, 0 - .dw 0x4d80, 0xcc18, 0x4d80, 0xcc18, 0x22, 0 - .dw 0x4d81, 0xcc18, 0x4d81, 0xcc18, 0x21, 0 - .dw 0x4d82, 0xcc18, 0x4d82, 0xcc18, 0x22, 0 - .dw 0x4d83, 0xcc18, 0x4d8f, 0xcc18, 0x21, 0 - .dw 0x4d90, 0xcc18, 0x4d90, 0xcc18, 0x22, 0 - .dw 0x4d91, 0xcc18, 0x4d91, 0xcc18, 0x21, 0 - .dw 0x4d92, 0xcc18, 0x4d92, 0xcc18, 0x22, 0 - .dw 0x4d93, 0xcc18, 0x4dbf, 0xcc18, 0x21, 0 - .dw 0x4dc1, 0xcc18, 0x4dc1, 0xcc18, 0x21, 0 - .dw 0x4dc3, 0xcc18, 0x4dcf, 0xcc18, 0x21, 0 - .dw 0x4dd1, 0xcc18, 0x4dd1, 0xcc18, 0x21, 0 - .dw 0x4dd3, 0xcc18, 0x4dff, 0xcc18, 0x21, 0 - .dw 0x4e01, 0xcc18, 0x4e01, 0xcc18, 0x21, 0 - .dw 0x4e03, 0xcc18, 0x4e0f, 0xcc18, 0x21, 0 - .dw 0x4e11, 0xcc18, 0x4e11, 0xcc18, 0x21, 0 - .dw 0x4e13, 0xcc18, 0x4e3f, 0xcc18, 0x21, 0 - .dw 0x4e41, 0xcc18, 0x4e41, 0xcc18, 0x21, 0 - .dw 0x4e43, 0xcc18, 0x4e4f, 0xcc18, 0x21, 0 - .dw 0x4e51, 0xcc18, 0x4e51, 0xcc18, 0x21, 0 - .dw 0x4e53, 0xcc18, 0x4e7f, 0xcc18, 0x21, 0 - .dw 0x4e81, 0xcc18, 0x4e81, 0xcc18, 0x21, 0 - .dw 0x4e83, 0xcc18, 0x4e8f, 0xcc18, 0x21, 0 - .dw 0x4e91, 0xcc18, 0x4e91, 0xcc18, 0x21, 0 - .dw 0x4e93, 0xcc18, 0x4ebf, 0xcc18, 0x21, 0 - .dw 0x4ec1, 0xcc18, 0x4ec1, 0xcc18, 0x21, 0 - .dw 0x4ec3, 0xcc18, 0x4ecf, 0xcc18, 0x21, 0 - .dw 0x4ed1, 0xcc18, 0x4ed1, 0xcc18, 0x21, 0 - .dw 0x4ed3, 0xcc18, 0x4eff, 0xcc18, 0x21, 0 - .dw 0x4f01, 0xcc18, 0x4f01, 0xcc18, 0x21, 0 - .dw 0x4f03, 0xcc18, 0x4f0f, 0xcc18, 0x21, 0 - .dw 0x4f11, 0xcc18, 0x4f11, 0xcc18, 0x21, 0 - .dw 0x4f13, 0xcc18, 0x4f3f, 0xcc18, 0x21, 0 - .dw 0x4f41, 0xcc18, 0x4f41, 0xcc18, 0x21, 0 - .dw 0x4f43, 0xcc18, 0x4f4f, 0xcc18, 0x21, 0 - .dw 0x4f51, 0xcc18, 0x4f51, 0xcc18, 0x21, 0 - .dw 0x4f53, 0xcc18, 0x4f7f, 0xcc18, 0x21, 0 - .dw 0x4f81, 0xcc18, 0x4f81, 0xcc18, 0x21, 0 - .dw 0x4f83, 0xcc18, 0x4f8f, 0xcc18, 0x21, 0 - .dw 0x4f91, 0xcc18, 0x4f91, 0xcc18, 0x21, 0 - .dw 0x4f93, 0xcc18, 0x4fbf, 0xcc18, 0x21, 0 - .dw 0x4fc0, 0xcc18, 0x4fc0, 0xcc18, 0x22, 0 - .dw 0x4fc1, 0xcc18, 0x4fc1, 0xcc18, 0x21, 0 - .dw 0x4fc2, 0xcc18, 0x4fc2, 0xcc18, 0x22, 0 - .dw 0x4fc3, 0xcc18, 0x4fcf, 0xcc18, 0x21, 0 - .dw 0x4fd0, 0xcc18, 0x4fd0, 0xcc18, 0x22, 0 - .dw 0x4fd1, 0xcc18, 0x4fd1, 0xcc18, 0x21, 0 - .dw 0x4fd2, 0xcc18, 0x4fd2, 0xcc18, 0x22, 0 - .dw 0x4fd3, 0xcc18, 0x5fff, 0xcc18, 0x21, 0 - .dw 0x6000, 0xcc18, 0x6000, 0xcc18, 0x22, 0 - .dw 0x6001, 0xcc18, 0x6001, 0xcc18, 0x21, 0 - .dw 0x6002, 0xcc18, 0x6002, 0xcc18, 0x22, 0 - .dw 0x6003, 0xcc18, 0x600f, 0xcc18, 0x21, 0 - .dw 0x6010, 0xcc18, 0x6010, 0xcc18, 0x22, 0 - .dw 0x6011, 0xcc18, 0x6011, 0xcc18, 0x21, 0 - .dw 0x6012, 0xcc18, 0x6012, 0xcc18, 0x22, 0 - .dw 0x6013, 0xcc18, 0x603f, 0xcc18, 0x21, 0 - .dw 0x6041, 0xcc18, 0x6041, 0xcc18, 0x21, 0 - .dw 0x6043, 0xcc18, 0x604f, 0xcc18, 0x21, 0 - .dw 0x6051, 0xcc18, 0x6051, 0xcc18, 0x21, 0 - .dw 0x6053, 0xcc18, 0x607f, 0xcc18, 0x21, 0 - .dw 0x6081, 0xcc18, 0x6081, 0xcc18, 0x21, 0 - .dw 0x6083, 0xcc18, 0x608f, 0xcc18, 0x21, 0 - .dw 0x6091, 0xcc18, 0x6091, 0xcc18, 0x21, 0 - .dw 0x6093, 0xcc18, 0x60bf, 0xcc18, 0x21, 0 - .dw 0x60c1, 0xcc18, 0x60c1, 0xcc18, 0x21, 0 - .dw 0x60c3, 0xcc18, 0x60cf, 0xcc18, 0x21, 0 - .dw 0x60d1, 0xcc18, 0x60d1, 0xcc18, 0x21, 0 - .dw 0x60d3, 0xcc18, 0x60ff, 0xcc18, 0x21, 0 - .dw 0x6101, 0xcc18, 0x6101, 0xcc18, 0x21, 0 - .dw 0x6103, 0xcc18, 0x610f, 0xcc18, 0x21, 0 - .dw 0x6111, 0xcc18, 0x6111, 0xcc18, 0x21, 0 - .dw 0x6113, 0xcc18, 0x613f, 0xcc18, 0x21, 0 - .dw 0x6141, 0xcc18, 0x6141, 0xcc18, 0x21, 0 - .dw 0x6143, 0xcc18, 0x614f, 0xcc18, 0x21, 0 - .dw 0x6151, 0xcc18, 0x6151, 0xcc18, 0x21, 0 - .dw 0x6153, 0xcc18, 0x617f, 0xcc18, 0x21, 0 - .dw 0x6181, 0xcc18, 0x6181, 0xcc18, 0x21, 0 - .dw 0x6183, 0xcc18, 0x618f, 0xcc18, 0x21, 0 - .dw 0x6191, 0xcc18, 0x6191, 0xcc18, 0x21, 0 - .dw 0x6193, 0xcc18, 0x61bf, 0xcc18, 0x21, 0 - .dw 0x61c1, 0xcc18, 0x61c1, 0xcc18, 0x21, 0 - .dw 0x61c3, 0xcc18, 0x61cf, 0xcc18, 0x21, 0 - .dw 0x61d1, 0xcc18, 0x61d1, 0xcc18, 0x21, 0 - .dw 0x61d3, 0xcc18, 0x61ff, 0xcc18, 0x21, 0 - .dw 0x6201, 0xcc18, 0x6201, 0xcc18, 0x21, 0 - .dw 0x6203, 0xcc18, 0x620f, 0xcc18, 0x21, 0 - .dw 0x6211, 0xcc18, 0x6211, 0xcc18, 0x21, 0 - .dw 0x6213, 0xcc18, 0x623f, 0xcc18, 0x21, 0 - .dw 0x6240, 0xcc18, 0x6240, 0xcc18, 0x22, 0 - .dw 0x6241, 0xcc18, 0x6241, 0xcc18, 0x21, 0 - .dw 0x6242, 0xcc18, 0x6242, 0xcc18, 0x22, 0 - .dw 0x6243, 0xcc18, 0x624f, 0xcc18, 0x21, 0 - .dw 0x6250, 0xcc18, 0x6250, 0xcc18, 0x22, 0 - .dw 0x6251, 0xcc18, 0x6251, 0xcc18, 0x21, 0 - .dw 0x6252, 0xcc18, 0x6252, 0xcc18, 0x22, 0 - .dw 0x6253, 0xcc18, 0x627f, 0xcc18, 0x21, 0 - .dw 0x6281, 0xcc18, 0x6281, 0xcc18, 0x21, 0 - .dw 0x6283, 0xcc18, 0x628f, 0xcc18, 0x21, 0 - .dw 0x6291, 0xcc18, 0x6291, 0xcc18, 0x21, 0 - .dw 0x6293, 0xcc18, 0x62bf, 0xcc18, 0x21, 0 - .dw 0x62c1, 0xcc18, 0x62c1, 0xcc18, 0x21, 0 - .dw 0x62c3, 0xcc18, 0x62cf, 0xcc18, 0x21, 0 - .dw 0x62d1, 0xcc18, 0x62d1, 0xcc18, 0x21, 0 - .dw 0x62d3, 0xcc18, 0x62ff, 0xcc18, 0x21, 0 - .dw 0x6301, 0xcc18, 0x6301, 0xcc18, 0x21, 0 - .dw 0x6303, 0xcc18, 0x630f, 0xcc18, 0x21, 0 - .dw 0x6311, 0xcc18, 0x6311, 0xcc18, 0x21, 0 - .dw 0x6313, 0xcc18, 0x633f, 0xcc18, 0x21, 0 - .dw 0x6341, 0xcc18, 0x6341, 0xcc18, 0x21, 0 - .dw 0x6343, 0xcc18, 0x634f, 0xcc18, 0x21, 0 - .dw 0x6351, 0xcc18, 0x6351, 0xcc18, 0x21, 0 - .dw 0x6353, 0xcc18, 0x637f, 0xcc18, 0x21, 0 - .dw 0x6381, 0xcc18, 0x6381, 0xcc18, 0x21, 0 - .dw 0x6383, 0xcc18, 0x638f, 0xcc18, 0x21, 0 - .dw 0x6391, 0xcc18, 0x6391, 0xcc18, 0x21, 0 - .dw 0x6393, 0xcc18, 0x63bf, 0xcc18, 0x21, 0 - .dw 0x63c1, 0xcc18, 0x63c1, 0xcc18, 0x21, 0 - .dw 0x63c3, 0xcc18, 0x63cf, 0xcc18, 0x21, 0 - .dw 0x63d1, 0xcc18, 0x63d1, 0xcc18, 0x21, 0 - .dw 0x63d3, 0xcc18, 0x63ff, 0xcc18, 0x21, 0 - .dw 0x6401, 0xcc18, 0x6401, 0xcc18, 0x21, 0 - .dw 0x6403, 0xcc18, 0x640f, 0xcc18, 0x21, 0 - .dw 0x6411, 0xcc18, 0x6411, 0xcc18, 0x21, 0 - .dw 0x6413, 0xcc18, 0x643f, 0xcc18, 0x21, 0 - .dw 0x6441, 0xcc18, 0x6441, 0xcc18, 0x21, 0 - .dw 0x6443, 0xcc18, 0x644f, 0xcc18, 0x21, 0 - .dw 0x6451, 0xcc18, 0x6451, 0xcc18, 0x21, 0 - .dw 0x6453, 0xcc18, 0x647f, 0xcc18, 0x21, 0 - .dw 0x6480, 0xcc18, 0x6480, 0xcc18, 0x22, 0 - .dw 0x6481, 0xcc18, 0x6481, 0xcc18, 0x21, 0 - .dw 0x6482, 0xcc18, 0x6482, 0xcc18, 0x22, 0 - .dw 0x6483, 0xcc18, 0x648f, 0xcc18, 0x21, 0 - .dw 0x6490, 0xcc18, 0x6490, 0xcc18, 0x22, 0 - .dw 0x6491, 0xcc18, 0x6491, 0xcc18, 0x21, 0 - .dw 0x6492, 0xcc18, 0x6492, 0xcc18, 0x22, 0 - .dw 0x6493, 0xcc18, 0x64bf, 0xcc18, 0x21, 0 - .dw 0x64c1, 0xcc18, 0x64c1, 0xcc18, 0x21, 0 - .dw 0x64c3, 0xcc18, 0x64cf, 0xcc18, 0x21, 0 - .dw 0x64d1, 0xcc18, 0x64d1, 0xcc18, 0x21, 0 - .dw 0x64d3, 0xcc18, 0x64ff, 0xcc18, 0x21, 0 - .dw 0x6501, 0xcc18, 0x6501, 0xcc18, 0x21, 0 - .dw 0x6503, 0xcc18, 0x650f, 0xcc18, 0x21, 0 - .dw 0x6511, 0xcc18, 0x6511, 0xcc18, 0x21, 0 - .dw 0x6513, 0xcc18, 0x653f, 0xcc18, 0x21, 0 - .dw 0x6541, 0xcc18, 0x6541, 0xcc18, 0x21, 0 - .dw 0x6543, 0xcc18, 0x654f, 0xcc18, 0x21, 0 - .dw 0x6551, 0xcc18, 0x6551, 0xcc18, 0x21, 0 - .dw 0x6553, 0xcc18, 0x657f, 0xcc18, 0x21, 0 - .dw 0x6581, 0xcc18, 0x6581, 0xcc18, 0x21, 0 - .dw 0x6583, 0xcc18, 0x658f, 0xcc18, 0x21, 0 - .dw 0x6591, 0xcc18, 0x6591, 0xcc18, 0x21, 0 - .dw 0x6593, 0xcc18, 0x65bf, 0xcc18, 0x21, 0 - .dw 0x65c1, 0xcc18, 0x65c1, 0xcc18, 0x21, 0 - .dw 0x65c3, 0xcc18, 0x65cf, 0xcc18, 0x21, 0 - .dw 0x65d1, 0xcc18, 0x65d1, 0xcc18, 0x21, 0 - .dw 0x65d3, 0xcc18, 0x65ff, 0xcc18, 0x21, 0 - .dw 0x6601, 0xcc18, 0x6601, 0xcc18, 0x21, 0 - .dw 0x6603, 0xcc18, 0x660f, 0xcc18, 0x21, 0 - .dw 0x6611, 0xcc18, 0x6611, 0xcc18, 0x21, 0 - .dw 0x6613, 0xcc18, 0x663f, 0xcc18, 0x21, 0 - .dw 0x6641, 0xcc18, 0x6641, 0xcc18, 0x21, 0 - .dw 0x6643, 0xcc18, 0x664f, 0xcc18, 0x21, 0 - .dw 0x6651, 0xcc18, 0x6651, 0xcc18, 0x21, 0 - .dw 0x6653, 0xcc18, 0x667f, 0xcc18, 0x21, 0 - .dw 0x6681, 0xcc18, 0x6681, 0xcc18, 0x21, 0 - .dw 0x6683, 0xcc18, 0x668f, 0xcc18, 0x21, 0 - .dw 0x6691, 0xcc18, 0x6691, 0xcc18, 0x21, 0 - .dw 0x6693, 0xcc18, 0x66bf, 0xcc18, 0x21, 0 - .dw 0x66c0, 0xcc18, 0x66c0, 0xcc18, 0x22, 0 - .dw 0x66c1, 0xcc18, 0x66c1, 0xcc18, 0x21, 0 - .dw 0x66c2, 0xcc18, 0x66c2, 0xcc18, 0x22, 0 - .dw 0x66c3, 0xcc18, 0x66cf, 0xcc18, 0x21, 0 - .dw 0x66d0, 0xcc18, 0x66d0, 0xcc18, 0x22, 0 - .dw 0x66d1, 0xcc18, 0x66d1, 0xcc18, 0x21, 0 - .dw 0x66d2, 0xcc18, 0x66d2, 0xcc18, 0x22, 0 - .dw 0x66d3, 0xcc18, 0x66ff, 0xcc18, 0x21, 0 - .dw 0x6701, 0xcc18, 0x6701, 0xcc18, 0x21, 0 - .dw 0x6703, 0xcc18, 0x670f, 0xcc18, 0x21, 0 - .dw 0x6711, 0xcc18, 0x6711, 0xcc18, 0x21, 0 - .dw 0x6713, 0xcc18, 0x673f, 0xcc18, 0x21, 0 - .dw 0x6741, 0xcc18, 0x6741, 0xcc18, 0x21, 0 - .dw 0x6743, 0xcc18, 0x674f, 0xcc18, 0x21, 0 - .dw 0x6751, 0xcc18, 0x6751, 0xcc18, 0x21, 0 - .dw 0x6753, 0xcc18, 0x677f, 0xcc18, 0x21, 0 - .dw 0x6781, 0xcc18, 0x6781, 0xcc18, 0x21, 0 - .dw 0x6783, 0xcc18, 0x678f, 0xcc18, 0x21, 0 - .dw 0x6791, 0xcc18, 0x6791, 0xcc18, 0x21, 0 - .dw 0x6793, 0xcc18, 0x67bf, 0xcc18, 0x21, 0 - .dw 0x67c1, 0xcc18, 0x67c1, 0xcc18, 0x21, 0 - .dw 0x67c3, 0xcc18, 0x67cf, 0xcc18, 0x21, 0 - .dw 0x67d1, 0xcc18, 0x67d1, 0xcc18, 0x21, 0 - .dw 0x67d3, 0xcc18, 0x67ff, 0xcc18, 0x21, 0 - .dw 0x6801, 0xcc18, 0x6801, 0xcc18, 0x21, 0 - .dw 0x6803, 0xcc18, 0x680f, 0xcc18, 0x21, 0 - .dw 0x6811, 0xcc18, 0x6811, 0xcc18, 0x21, 0 - .dw 0x6813, 0xcc18, 0x683f, 0xcc18, 0x21, 0 - .dw 0x6841, 0xcc18, 0x6841, 0xcc18, 0x21, 0 - .dw 0x6843, 0xcc18, 0x684f, 0xcc18, 0x21, 0 - .dw 0x6851, 0xcc18, 0x6851, 0xcc18, 0x21, 0 - .dw 0x6853, 0xcc18, 0x687f, 0xcc18, 0x21, 0 - .dw 0x6881, 0xcc18, 0x6881, 0xcc18, 0x21, 0 - .dw 0x6883, 0xcc18, 0x688f, 0xcc18, 0x21, 0 - .dw 0x6891, 0xcc18, 0x6891, 0xcc18, 0x21, 0 - .dw 0x6893, 0xcc18, 0x68bf, 0xcc18, 0x21, 0 - .dw 0x68c1, 0xcc18, 0x68c1, 0xcc18, 0x21, 0 - .dw 0x68c3, 0xcc18, 0x68cf, 0xcc18, 0x21, 0 - .dw 0x68d1, 0xcc18, 0x68d1, 0xcc18, 0x21, 0 - .dw 0x68d3, 0xcc18, 0x68ff, 0xcc18, 0x21, 0 - .dw 0x6900, 0xcc18, 0x6900, 0xcc18, 0x22, 0 - .dw 0x6901, 0xcc18, 0x6901, 0xcc18, 0x21, 0 - .dw 0x6902, 0xcc18, 0x6902, 0xcc18, 0x22, 0 - .dw 0x6903, 0xcc18, 0x690f, 0xcc18, 0x21, 0 - .dw 0x6910, 0xcc18, 0x6910, 0xcc18, 0x22, 0 - .dw 0x6911, 0xcc18, 0x6911, 0xcc18, 0x21, 0 - .dw 0x6912, 0xcc18, 0x6912, 0xcc18, 0x22, 0 - .dw 0x6913, 0xcc18, 0x693f, 0xcc18, 0x21, 0 - .dw 0x6941, 0xcc18, 0x6941, 0xcc18, 0x21, 0 - .dw 0x6943, 0xcc18, 0x694f, 0xcc18, 0x21, 0 - .dw 0x6951, 0xcc18, 0x6951, 0xcc18, 0x21, 0 - .dw 0x6953, 0xcc18, 0x697f, 0xcc18, 0x21, 0 - .dw 0x6981, 0xcc18, 0x6981, 0xcc18, 0x21, 0 - .dw 0x6983, 0xcc18, 0x698f, 0xcc18, 0x21, 0 - .dw 0x6991, 0xcc18, 0x6991, 0xcc18, 0x21, 0 - .dw 0x6993, 0xcc18, 0x69bf, 0xcc18, 0x21, 0 - .dw 0x69c1, 0xcc18, 0x69c1, 0xcc18, 0x21, 0 - .dw 0x69c3, 0xcc18, 0x69cf, 0xcc18, 0x21, 0 - .dw 0x69d1, 0xcc18, 0x69d1, 0xcc18, 0x21, 0 - .dw 0x69d3, 0xcc18, 0x69ff, 0xcc18, 0x21, 0 - .dw 0x6a01, 0xcc18, 0x6a01, 0xcc18, 0x21, 0 - .dw 0x6a03, 0xcc18, 0x6a0f, 0xcc18, 0x21, 0 - .dw 0x6a11, 0xcc18, 0x6a11, 0xcc18, 0x21, 0 - .dw 0x6a13, 0xcc18, 0x6a3f, 0xcc18, 0x21, 0 - .dw 0x6a41, 0xcc18, 0x6a41, 0xcc18, 0x21, 0 - .dw 0x6a43, 0xcc18, 0x6a4f, 0xcc18, 0x21, 0 - .dw 0x6a51, 0xcc18, 0x6a51, 0xcc18, 0x21, 0 - .dw 0x6a53, 0xcc18, 0x6a7f, 0xcc18, 0x21, 0 - .dw 0x6a81, 0xcc18, 0x6a81, 0xcc18, 0x21, 0 - .dw 0x6a83, 0xcc18, 0x6a8f, 0xcc18, 0x21, 0 - .dw 0x6a91, 0xcc18, 0x6a91, 0xcc18, 0x21, 0 - .dw 0x6a93, 0xcc18, 0x6abf, 0xcc18, 0x21, 0 - .dw 0x6ac1, 0xcc18, 0x6ac1, 0xcc18, 0x21, 0 - .dw 0x6ac3, 0xcc18, 0x6acf, 0xcc18, 0x21, 0 - .dw 0x6ad1, 0xcc18, 0x6ad1, 0xcc18, 0x21, 0 - .dw 0x6ad3, 0xcc18, 0x6aff, 0xcc18, 0x21, 0 - .dw 0x6b01, 0xcc18, 0x6b01, 0xcc18, 0x21, 0 - .dw 0x6b03, 0xcc18, 0x6b0f, 0xcc18, 0x21, 0 - .dw 0x6b11, 0xcc18, 0x6b11, 0xcc18, 0x21, 0 - .dw 0x6b13, 0xcc18, 0x6b3f, 0xcc18, 0x21, 0 - .dw 0x6b40, 0xcc18, 0x6b40, 0xcc18, 0x22, 0 - .dw 0x6b41, 0xcc18, 0x6b41, 0xcc18, 0x21, 0 - .dw 0x6b42, 0xcc18, 0x6b42, 0xcc18, 0x22, 0 - .dw 0x6b43, 0xcc18, 0x6b4f, 0xcc18, 0x21, 0 - .dw 0x6b50, 0xcc18, 0x6b50, 0xcc18, 0x22, 0 - .dw 0x6b51, 0xcc18, 0x6b51, 0xcc18, 0x21, 0 - .dw 0x6b52, 0xcc18, 0x6b52, 0xcc18, 0x22, 0 - .dw 0x6b53, 0xcc18, 0x6b7f, 0xcc18, 0x21, 0 - .dw 0x6b81, 0xcc18, 0x6b81, 0xcc18, 0x21, 0 - .dw 0x6b83, 0xcc18, 0x6b8f, 0xcc18, 0x21, 0 - .dw 0x6b91, 0xcc18, 0x6b91, 0xcc18, 0x21, 0 - .dw 0x6b93, 0xcc18, 0x6bbf, 0xcc18, 0x21, 0 - .dw 0x6bc1, 0xcc18, 0x6bc1, 0xcc18, 0x21, 0 - .dw 0x6bc3, 0xcc18, 0x6bcf, 0xcc18, 0x21, 0 - .dw 0x6bd1, 0xcc18, 0x6bd1, 0xcc18, 0x21, 0 - .dw 0x6bd3, 0xcc18, 0x6bff, 0xcc18, 0x21, 0 - .dw 0x6c01, 0xcc18, 0x6c01, 0xcc18, 0x21, 0 - .dw 0x6c03, 0xcc18, 0x6c0f, 0xcc18, 0x21, 0 - .dw 0x6c11, 0xcc18, 0x6c11, 0xcc18, 0x21, 0 - .dw 0x6c13, 0xcc18, 0x6c3f, 0xcc18, 0x21, 0 - .dw 0x6c41, 0xcc18, 0x6c41, 0xcc18, 0x21, 0 - .dw 0x6c43, 0xcc18, 0x6c4f, 0xcc18, 0x21, 0 - .dw 0x6c51, 0xcc18, 0x6c51, 0xcc18, 0x21, 0 - .dw 0x6c53, 0xcc18, 0x6c7f, 0xcc18, 0x21, 0 - .dw 0x6c81, 0xcc18, 0x6c81, 0xcc18, 0x21, 0 - .dw 0x6c83, 0xcc18, 0x6c8f, 0xcc18, 0x21, 0 - .dw 0x6c91, 0xcc18, 0x6c91, 0xcc18, 0x21, 0 - .dw 0x6c93, 0xcc18, 0x6cbf, 0xcc18, 0x21, 0 - .dw 0x6cc1, 0xcc18, 0x6cc1, 0xcc18, 0x21, 0 - .dw 0x6cc3, 0xcc18, 0x6ccf, 0xcc18, 0x21, 0 - .dw 0x6cd1, 0xcc18, 0x6cd1, 0xcc18, 0x21, 0 - .dw 0x6cd3, 0xcc18, 0x6cff, 0xcc18, 0x21, 0 - .dw 0x6d01, 0xcc18, 0x6d01, 0xcc18, 0x21, 0 - .dw 0x6d03, 0xcc18, 0x6d0f, 0xcc18, 0x21, 0 - .dw 0x6d11, 0xcc18, 0x6d11, 0xcc18, 0x21, 0 - .dw 0x6d13, 0xcc18, 0x6d3f, 0xcc18, 0x21, 0 - .dw 0x6d41, 0xcc18, 0x6d41, 0xcc18, 0x21, 0 - .dw 0x6d43, 0xcc18, 0x6d4f, 0xcc18, 0x21, 0 - .dw 0x6d51, 0xcc18, 0x6d51, 0xcc18, 0x21, 0 - .dw 0x6d53, 0xcc18, 0x6d7f, 0xcc18, 0x21, 0 - .dw 0x6d80, 0xcc18, 0x6d80, 0xcc18, 0x22, 0 - .dw 0x6d81, 0xcc18, 0x6d81, 0xcc18, 0x21, 0 - .dw 0x6d82, 0xcc18, 0x6d82, 0xcc18, 0x22, 0 - .dw 0x6d83, 0xcc18, 0x6d8f, 0xcc18, 0x21, 0 - .dw 0x6d90, 0xcc18, 0x6d90, 0xcc18, 0x22, 0 - .dw 0x6d91, 0xcc18, 0x6d91, 0xcc18, 0x21, 0 - .dw 0x6d92, 0xcc18, 0x6d92, 0xcc18, 0x22, 0 - .dw 0x6d93, 0xcc18, 0x6dbf, 0xcc18, 0x21, 0 - .dw 0x6dc1, 0xcc18, 0x6dc1, 0xcc18, 0x21, 0 - .dw 0x6dc3, 0xcc18, 0x6dcf, 0xcc18, 0x21, 0 - .dw 0x6dd1, 0xcc18, 0x6dd1, 0xcc18, 0x21, 0 - .dw 0x6dd3, 0xcc18, 0x6dff, 0xcc18, 0x21, 0 - .dw 0x6e01, 0xcc18, 0x6e01, 0xcc18, 0x21, 0 - .dw 0x6e03, 0xcc18, 0x6e0f, 0xcc18, 0x21, 0 - .dw 0x6e11, 0xcc18, 0x6e11, 0xcc18, 0x21, 0 - .dw 0x6e13, 0xcc18, 0x6e3f, 0xcc18, 0x21, 0 - .dw 0x6e41, 0xcc18, 0x6e41, 0xcc18, 0x21, 0 - .dw 0x6e43, 0xcc18, 0x6e4f, 0xcc18, 0x21, 0 - .dw 0x6e51, 0xcc18, 0x6e51, 0xcc18, 0x21, 0 - .dw 0x6e53, 0xcc18, 0x6e7f, 0xcc18, 0x21, 0 - .dw 0x6e81, 0xcc18, 0x6e81, 0xcc18, 0x21, 0 - .dw 0x6e83, 0xcc18, 0x6e8f, 0xcc18, 0x21, 0 - .dw 0x6e91, 0xcc18, 0x6e91, 0xcc18, 0x21, 0 - .dw 0x6e93, 0xcc18, 0x6ebf, 0xcc18, 0x21, 0 - .dw 0x6ec1, 0xcc18, 0x6ec1, 0xcc18, 0x21, 0 - .dw 0x6ec3, 0xcc18, 0x6ecf, 0xcc18, 0x21, 0 - .dw 0x6ed1, 0xcc18, 0x6ed1, 0xcc18, 0x21, 0 - .dw 0x6ed3, 0xcc18, 0x6eff, 0xcc18, 0x21, 0 - .dw 0x6f01, 0xcc18, 0x6f01, 0xcc18, 0x21, 0 - .dw 0x6f03, 0xcc18, 0x6f0f, 0xcc18, 0x21, 0 - .dw 0x6f11, 0xcc18, 0x6f11, 0xcc18, 0x21, 0 - .dw 0x6f13, 0xcc18, 0x6f3f, 0xcc18, 0x21, 0 - .dw 0x6f41, 0xcc18, 0x6f41, 0xcc18, 0x21, 0 - .dw 0x6f43, 0xcc18, 0x6f4f, 0xcc18, 0x21, 0 - .dw 0x6f51, 0xcc18, 0x6f51, 0xcc18, 0x21, 0 - .dw 0x6f53, 0xcc18, 0x6f7f, 0xcc18, 0x21, 0 - .dw 0x6f81, 0xcc18, 0x6f81, 0xcc18, 0x21, 0 - .dw 0x6f83, 0xcc18, 0x6f8f, 0xcc18, 0x21, 0 - .dw 0x6f91, 0xcc18, 0x6f91, 0xcc18, 0x21, 0 - .dw 0x6f93, 0xcc18, 0x6fbf, 0xcc18, 0x21, 0 - .dw 0x6fc0, 0xcc18, 0x6fc0, 0xcc18, 0x22, 0 - .dw 0x6fc1, 0xcc18, 0x6fc1, 0xcc18, 0x21, 0 - .dw 0x6fc2, 0xcc18, 0x6fc2, 0xcc18, 0x22, 0 - .dw 0x6fc3, 0xcc18, 0x6fcf, 0xcc18, 0x21, 0 - .dw 0x6fd0, 0xcc18, 0x6fd0, 0xcc18, 0x22, 0 - .dw 0x6fd1, 0xcc18, 0x6fd1, 0xcc18, 0x21, 0 - .dw 0x6fd2, 0xcc18, 0x6fd2, 0xcc18, 0x22, 0 - .dw 0x6fd3, 0xcc18, 0xffff, 0xcc20, 0x21, 0 - .dw 0x0000, 0xcc21, 0x003f, 0xcc21, 0x22, 0 - .dw 0x0240, 0xcc21, 0x027f, 0xcc21, 0x22, 0 - .dw 0x0480, 0xcc21, 0x04bf, 0xcc21, 0x22, 0 - .dw 0x06c0, 0xcc21, 0x06ff, 0xcc21, 0x22, 0 - .dw 0x0900, 0xcc21, 0x093f, 0xcc21, 0x22, 0 - .dw 0x0b40, 0xcc21, 0x0b7f, 0xcc21, 0x22, 0 - .dw 0x0d80, 0xcc21, 0x0dbf, 0xcc21, 0x22, 0 - .dw 0x0fc0, 0xcc21, 0x103f, 0xcc21, 0x22, 0 - .dw 0x1240, 0xcc21, 0x127f, 0xcc21, 0x22, 0 - .dw 0x1480, 0xcc21, 0x14bf, 0xcc21, 0x22, 0 - .dw 0x16c0, 0xcc21, 0x16ff, 0xcc21, 0x22, 0 - .dw 0x1900, 0xcc21, 0x193f, 0xcc21, 0x22, 0 - .dw 0x1b40, 0xcc21, 0x1b7f, 0xcc21, 0x22, 0 - .dw 0x1d80, 0xcc21, 0x1dbf, 0xcc21, 0x22, 0 - .dw 0x1fc0, 0xcc21, 0x203f, 0xcc21, 0x22, 0 - .dw 0x2240, 0xcc21, 0x227f, 0xcc21, 0x22, 0 - .dw 0x2480, 0xcc21, 0x24bf, 0xcc21, 0x22, 0 - .dw 0x26c0, 0xcc21, 0x26ff, 0xcc21, 0x22, 0 - .dw 0x2900, 0xcc21, 0x293f, 0xcc21, 0x22, 0 - .dw 0x2b40, 0xcc21, 0x2b7f, 0xcc21, 0x22, 0 - .dw 0x2d80, 0xcc21, 0x2dbf, 0xcc21, 0x22, 0 - .dw 0x2fc0, 0xcc21, 0x303f, 0xcc21, 0x22, 0 - .dw 0x3240, 0xcc21, 0x327f, 0xcc21, 0x22, 0 - .dw 0x3480, 0xcc21, 0x34bf, 0xcc21, 0x22, 0 - .dw 0x36c0, 0xcc21, 0x36ff, 0xcc21, 0x22, 0 - .dw 0x3900, 0xcc21, 0x393f, 0xcc21, 0x22, 0 - .dw 0x3b40, 0xcc21, 0x3b7f, 0xcc21, 0x22, 0 - .dw 0x3d80, 0xcc21, 0x3dbf, 0xcc21, 0x22, 0 - .dw 0x3fc0, 0xcc21, 0x3fff, 0xcc21, 0x22, 0 - .dw 0x4000, 0xcc21, 0x7fff, 0xcc21, 0x21, 0 - .dw 0x8000, 0xcc21, 0x803f, 0xcc21, 0x22, 0 - .dw 0x8240, 0xcc21, 0x827f, 0xcc21, 0x22, 0 - .dw 0x8480, 0xcc21, 0x84bf, 0xcc21, 0x22, 0 - .dw 0x86c0, 0xcc21, 0x86ff, 0xcc21, 0x22, 0 - .dw 0x8900, 0xcc21, 0x893f, 0xcc21, 0x22, 0 - .dw 0x8b40, 0xcc21, 0x8b7f, 0xcc21, 0x22, 0 - .dw 0x8d80, 0xcc21, 0x8dbf, 0xcc21, 0x22, 0 - .dw 0x8fc0, 0xcc21, 0x903f, 0xcc21, 0x22, 0 - .dw 0x9240, 0xcc21, 0x927f, 0xcc21, 0x22, 0 - .dw 0x9480, 0xcc21, 0x94bf, 0xcc21, 0x22, 0 - .dw 0x96c0, 0xcc21, 0x96ff, 0xcc21, 0x22, 0 - .dw 0x9900, 0xcc21, 0x993f, 0xcc21, 0x22, 0 - .dw 0x9b40, 0xcc21, 0x9b7f, 0xcc21, 0x22, 0 - .dw 0x9d80, 0xcc21, 0x9dbf, 0xcc21, 0x22, 0 - .dw 0x9fc0, 0xcc21, 0xa03f, 0xcc21, 0x22, 0 - .dw 0xa240, 0xcc21, 0xa27f, 0xcc21, 0x22, 0 - .dw 0xa480, 0xcc21, 0xa4bf, 0xcc21, 0x22, 0 - .dw 0xa6c0, 0xcc21, 0xa6ff, 0xcc21, 0x22, 0 - .dw 0xa900, 0xcc21, 0xa93f, 0xcc21, 0x22, 0 - .dw 0xab40, 0xcc21, 0xab7f, 0xcc21, 0x22, 0 - .dw 0xad80, 0xcc21, 0xadbf, 0xcc21, 0x22, 0 - .dw 0xafc0, 0xcc21, 0xb03f, 0xcc21, 0x22, 0 - .dw 0xb240, 0xcc21, 0xb27f, 0xcc21, 0x22, 0 - .dw 0xb480, 0xcc21, 0xb4bf, 0xcc21, 0x22, 0 - .dw 0xb6c0, 0xcc21, 0xb6ff, 0xcc21, 0x22, 0 - .dw 0xb900, 0xcc21, 0xb93f, 0xcc21, 0x22, 0 - .dw 0xbb40, 0xcc21, 0xbb7f, 0xcc21, 0x22, 0 - .dw 0xbd80, 0xcc21, 0xbdbf, 0xcc21, 0x22, 0 - .dw 0xbfc0, 0xcc21, 0xc03f, 0xcc21, 0x22, 0 - .dw 0xc240, 0xcc21, 0xc27f, 0xcc21, 0x22, 0 - .dw 0xc480, 0xcc21, 0xc4bf, 0xcc21, 0x22, 0 - .dw 0xc6c0, 0xcc21, 0xc6ff, 0xcc21, 0x22, 0 - .dw 0xc900, 0xcc21, 0xc93f, 0xcc21, 0x22, 0 - .dw 0xcb40, 0xcc21, 0xcb7f, 0xcc21, 0x22, 0 - .dw 0xcd80, 0xcc21, 0xcdbf, 0xcc21, 0x22, 0 - .dw 0xcfc0, 0xcc21, 0xd03f, 0xcc21, 0x22, 0 - .dw 0xd240, 0xcc21, 0xd27f, 0xcc21, 0x22, 0 - .dw 0xd480, 0xcc21, 0xd4bf, 0xcc21, 0x22, 0 - .dw 0xd6c0, 0xcc21, 0xd6ff, 0xcc21, 0x22, 0 - .dw 0xd900, 0xcc21, 0xd93f, 0xcc21, 0x22, 0 - .dw 0xdb40, 0xcc21, 0xdb7f, 0xcc21, 0x22, 0 - .dw 0xdd80, 0xcc21, 0xddbf, 0xcc21, 0x22, 0 - .dw 0xdfc0, 0xcc21, 0xe03f, 0xcc21, 0x22, 0 - .dw 0xe240, 0xcc21, 0xe27f, 0xcc21, 0x22, 0 - .dw 0xe480, 0xcc21, 0xe4bf, 0xcc21, 0x22, 0 - .dw 0xe6c0, 0xcc21, 0xe6ff, 0xcc21, 0x22, 0 - .dw 0xe900, 0xcc21, 0xe93f, 0xcc21, 0x22, 0 - .dw 0xeb40, 0xcc21, 0xeb7f, 0xcc21, 0x22, 0 - .dw 0xed80, 0xcc21, 0xedbf, 0xcc21, 0x22, 0 - .dw 0xefc0, 0xcc21, 0xf03f, 0xcc21, 0x22, 0 - .dw 0xf240, 0xcc21, 0xf27f, 0xcc21, 0x22, 0 - .dw 0xf480, 0xcc21, 0xf4bf, 0xcc21, 0x22, 0 - .dw 0xf6c0, 0xcc21, 0xf6ff, 0xcc21, 0x22, 0 - .dw 0xf900, 0xcc21, 0xf93f, 0xcc21, 0x22, 0 - .dw 0xfb40, 0xcc21, 0xfb7f, 0xcc21, 0x22, 0 - .dw 0xfd80, 0xcc21, 0xfdbf, 0xcc21, 0x22, 0 - .dw 0xffc0, 0xcc21, 0xffff, 0xcc21, 0x22, 0 - .dw 0x1000, 0xcc22, 0x1fff, 0xcc22, 0x21, 0 - .dw 0x3000, 0xcc22, 0x3fff, 0xcc22, 0x21, 0 - .dw 0x5000, 0xcc22, 0x5fff, 0xcc22, 0x21, 0 - .dw 0x7000, 0xcc22, 0x7fff, 0xcc22, 0x21, 0 - .dw 0x9000, 0xcc22, 0x9fff, 0xcc22, 0x21, 0 - .dw 0xb000, 0xcc22, 0xbfff, 0xcc22, 0x21, 0 - .dw 0xd000, 0xcc22, 0xdfff, 0xcc22, 0x21, 0 - .dw 0xf000, 0xcc22, 0xffff, 0xcc22, 0x21, 0 - .dw 0x1000, 0xcc23, 0x1fff, 0xcc23, 0x21, 0 - .dw 0x3000, 0xcc23, 0x3fff, 0xcc23, 0x21, 0 - .dw 0x5000, 0xcc23, 0x5fff, 0xcc23, 0x21, 0 - .dw 0x7000, 0xcc23, 0x7fff, 0xcc23, 0x21, 0 - .dw 0x9000, 0xcc23, 0x9fff, 0xcc23, 0x21, 0 - .dw 0xb000, 0xcc23, 0xbfff, 0xcc23, 0x21, 0 - .dw 0xd000, 0xcc23, 0xdfff, 0xcc23, 0x21, 0 - .dw 0xf000, 0xcc23, 0xffff, 0xcc24, 0x21, 0 - .dw 0x1000, 0xcc25, 0x3fff, 0xcc25, 0x21, 0 - .dw 0x5000, 0xcc25, 0x8fff, 0xcc25, 0x21, 0 - .dw 0xa000, 0xcc25, 0xcfff, 0xcc25, 0x21, 0 - .dw 0xe000, 0xcc25, 0xffff, 0xcc28, 0x21, 0 - .dw 0x1000, 0xcc29, 0x7fff, 0xcc29, 0x21, 0 - .dw 0x9000, 0xcc29, 0xffff, 0xcc2a, 0x21, 0 - .dw 0x1000, 0xcc2b, 0x3fff, 0xcc2b, 0x21, 0 - .dw 0x5000, 0xcc2b, 0xbfff, 0xcc2c, 0x21, 0 - .dw 0xd000, 0xcc2c, 0xffff, 0xcc2d, 0x21, 0 - .dw 0x1000, 0xcc2e, 0x3fff, 0xcc2e, 0x21, 0 - .dw 0x5000, 0xcc2e, 0xffff, 0xcc2f, 0x21, 0 - .dw 0x1000, 0xcc30, 0x3fff, 0xcc30, 0x21, 0 - .dw 0x5000, 0xcc30, 0xffff, 0xcc35, 0x21, 0 - .dw 0x0001, 0xcc36, 0x0001, 0xcc36, 0x21, 0 - .dw 0x0003, 0xcc36, 0x000f, 0xcc36, 0x21, 0 - .dw 0x0011, 0xcc36, 0x0011, 0xcc36, 0x21, 0 - .dw 0x0013, 0xcc36, 0x003f, 0xcc36, 0x21, 0 - .dw 0x0041, 0xcc36, 0x0041, 0xcc36, 0x21, 0 - .dw 0x0043, 0xcc36, 0x004f, 0xcc36, 0x21, 0 - .dw 0x0051, 0xcc36, 0x0051, 0xcc36, 0x21, 0 - .dw 0x0053, 0xcc36, 0x007f, 0xcc36, 0x21, 0 - .dw 0x0081, 0xcc36, 0x0081, 0xcc36, 0x21, 0 - .dw 0x0083, 0xcc36, 0x008f, 0xcc36, 0x21, 0 - .dw 0x0091, 0xcc36, 0x0091, 0xcc36, 0x21, 0 - .dw 0x0093, 0xcc36, 0x00bf, 0xcc36, 0x21, 0 - .dw 0x00c1, 0xcc36, 0x00c1, 0xcc36, 0x21, 0 - .dw 0x00c3, 0xcc36, 0x00cf, 0xcc36, 0x21, 0 - .dw 0x00d1, 0xcc36, 0x00d1, 0xcc36, 0x21, 0 - .dw 0x00d3, 0xcc36, 0x00ff, 0xcc36, 0x21, 0 - .dw 0x0101, 0xcc36, 0x0101, 0xcc36, 0x21, 0 - .dw 0x0103, 0xcc36, 0x010f, 0xcc36, 0x21, 0 - .dw 0x0111, 0xcc36, 0x0111, 0xcc36, 0x21, 0 - .dw 0x0113, 0xcc36, 0x013f, 0xcc36, 0x21, 0 - .dw 0x0141, 0xcc36, 0x0141, 0xcc36, 0x21, 0 - .dw 0x0143, 0xcc36, 0x014f, 0xcc36, 0x21, 0 - .dw 0x0151, 0xcc36, 0x0151, 0xcc36, 0x21, 0 - .dw 0x0153, 0xcc36, 0x017f, 0xcc36, 0x21, 0 - .dw 0x0181, 0xcc36, 0x0181, 0xcc36, 0x21, 0 - .dw 0x0183, 0xcc36, 0x018f, 0xcc36, 0x21, 0 - .dw 0x0191, 0xcc36, 0x0191, 0xcc36, 0x21, 0 - .dw 0x0193, 0xcc36, 0x01bf, 0xcc36, 0x21, 0 - .dw 0x01c1, 0xcc36, 0x01c1, 0xcc36, 0x21, 0 - .dw 0x01c3, 0xcc36, 0x01cf, 0xcc36, 0x21, 0 - .dw 0x01d1, 0xcc36, 0x01d1, 0xcc36, 0x21, 0 - .dw 0x01d3, 0xcc36, 0x01ff, 0xcc36, 0x21, 0 - .dw 0x0201, 0xcc36, 0x0201, 0xcc36, 0x21, 0 - .dw 0x0203, 0xcc36, 0x020f, 0xcc36, 0x21, 0 - .dw 0x0211, 0xcc36, 0x0211, 0xcc36, 0x21, 0 - .dw 0x0213, 0xcc36, 0x023f, 0xcc36, 0x21, 0 - .dw 0x0241, 0xcc36, 0x0241, 0xcc36, 0x21, 0 - .dw 0x0243, 0xcc36, 0x024f, 0xcc36, 0x21, 0 - .dw 0x0251, 0xcc36, 0x0251, 0xcc36, 0x21, 0 - .dw 0x0253, 0xcc36, 0x027f, 0xcc36, 0x21, 0 - .dw 0x0281, 0xcc36, 0x0281, 0xcc36, 0x21, 0 - .dw 0x0283, 0xcc36, 0x028f, 0xcc36, 0x21, 0 - .dw 0x0291, 0xcc36, 0x0291, 0xcc36, 0x21, 0 - .dw 0x0293, 0xcc36, 0x02bf, 0xcc36, 0x21, 0 - .dw 0x02c1, 0xcc36, 0x02c1, 0xcc36, 0x21, 0 - .dw 0x02c3, 0xcc36, 0x02cf, 0xcc36, 0x21, 0 - .dw 0x02d1, 0xcc36, 0x02d1, 0xcc36, 0x21, 0 - .dw 0x02d3, 0xcc36, 0x02ff, 0xcc36, 0x21, 0 - .dw 0x0301, 0xcc36, 0x0301, 0xcc36, 0x21, 0 - .dw 0x0303, 0xcc36, 0x030f, 0xcc36, 0x21, 0 - .dw 0x0311, 0xcc36, 0x0311, 0xcc36, 0x21, 0 - .dw 0x0313, 0xcc36, 0x033f, 0xcc36, 0x21, 0 - .dw 0x0341, 0xcc36, 0x0341, 0xcc36, 0x21, 0 - .dw 0x0343, 0xcc36, 0x034f, 0xcc36, 0x21, 0 - .dw 0x0351, 0xcc36, 0x0351, 0xcc36, 0x21, 0 - .dw 0x0353, 0xcc36, 0x037f, 0xcc36, 0x21, 0 - .dw 0x0381, 0xcc36, 0x0381, 0xcc36, 0x21, 0 - .dw 0x0383, 0xcc36, 0x038f, 0xcc36, 0x21, 0 - .dw 0x0391, 0xcc36, 0x0391, 0xcc36, 0x21, 0 - .dw 0x0393, 0xcc36, 0x03bf, 0xcc36, 0x21, 0 - .dw 0x03c1, 0xcc36, 0x03c1, 0xcc36, 0x21, 0 - .dw 0x03c3, 0xcc36, 0x03cf, 0xcc36, 0x21, 0 - .dw 0x03d1, 0xcc36, 0x03d1, 0xcc36, 0x21, 0 - .dw 0x03d3, 0xcc36, 0x03ff, 0xcc36, 0x21, 0 - .dw 0x0401, 0xcc36, 0x0401, 0xcc36, 0x21, 0 - .dw 0x0403, 0xcc36, 0x040f, 0xcc36, 0x21, 0 - .dw 0x0411, 0xcc36, 0x0411, 0xcc36, 0x21, 0 - .dw 0x0413, 0xcc36, 0x043f, 0xcc36, 0x21, 0 - .dw 0x0441, 0xcc36, 0x0441, 0xcc36, 0x21, 0 - .dw 0x0443, 0xcc36, 0x044f, 0xcc36, 0x21, 0 - .dw 0x0451, 0xcc36, 0x0451, 0xcc36, 0x21, 0 - .dw 0x0453, 0xcc36, 0x047f, 0xcc36, 0x21, 0 - .dw 0x0481, 0xcc36, 0x0481, 0xcc36, 0x21, 0 - .dw 0x0483, 0xcc36, 0x048f, 0xcc36, 0x21, 0 - .dw 0x0491, 0xcc36, 0x0491, 0xcc36, 0x21, 0 - .dw 0x0493, 0xcc36, 0x04bf, 0xcc36, 0x21, 0 - .dw 0x04c1, 0xcc36, 0x04c1, 0xcc36, 0x21, 0 - .dw 0x04c3, 0xcc36, 0x04cf, 0xcc36, 0x21, 0 - .dw 0x04d1, 0xcc36, 0x04d1, 0xcc36, 0x21, 0 - .dw 0x04d3, 0xcc36, 0x04ff, 0xcc36, 0x21, 0 - .dw 0x0501, 0xcc36, 0x0501, 0xcc36, 0x21, 0 - .dw 0x0503, 0xcc36, 0x050f, 0xcc36, 0x21, 0 - .dw 0x0511, 0xcc36, 0x0511, 0xcc36, 0x21, 0 - .dw 0x0513, 0xcc36, 0x053f, 0xcc36, 0x21, 0 - .dw 0x0541, 0xcc36, 0x0541, 0xcc36, 0x21, 0 - .dw 0x0543, 0xcc36, 0x054f, 0xcc36, 0x21, 0 - .dw 0x0551, 0xcc36, 0x0551, 0xcc36, 0x21, 0 - .dw 0x0553, 0xcc36, 0x057f, 0xcc36, 0x21, 0 - .dw 0x0581, 0xcc36, 0x0581, 0xcc36, 0x21, 0 - .dw 0x0583, 0xcc36, 0x058f, 0xcc36, 0x21, 0 - .dw 0x0591, 0xcc36, 0x0591, 0xcc36, 0x21, 0 - .dw 0x0593, 0xcc36, 0x05bf, 0xcc36, 0x21, 0 - .dw 0x05c1, 0xcc36, 0x05c1, 0xcc36, 0x21, 0 - .dw 0x05c3, 0xcc36, 0x05cf, 0xcc36, 0x21, 0 - .dw 0x05d1, 0xcc36, 0x05d1, 0xcc36, 0x21, 0 - .dw 0x05d3, 0xcc36, 0x05ff, 0xcc36, 0x21, 0 - .dw 0x0601, 0xcc36, 0x0601, 0xcc36, 0x21, 0 - .dw 0x0603, 0xcc36, 0x060f, 0xcc36, 0x21, 0 - .dw 0x0611, 0xcc36, 0x0611, 0xcc36, 0x21, 0 - .dw 0x0613, 0xcc36, 0x063f, 0xcc36, 0x21, 0 - .dw 0x0641, 0xcc36, 0x0641, 0xcc36, 0x21, 0 - .dw 0x0643, 0xcc36, 0x064f, 0xcc36, 0x21, 0 - .dw 0x0651, 0xcc36, 0x0651, 0xcc36, 0x21, 0 - .dw 0x0653, 0xcc36, 0x067f, 0xcc36, 0x21, 0 - .dw 0x0681, 0xcc36, 0x0681, 0xcc36, 0x21, 0 - .dw 0x0683, 0xcc36, 0x068f, 0xcc36, 0x21, 0 - .dw 0x0691, 0xcc36, 0x0691, 0xcc36, 0x21, 0 - .dw 0x0693, 0xcc36, 0x06bf, 0xcc36, 0x21, 0 - .dw 0x06c1, 0xcc36, 0x06c1, 0xcc36, 0x21, 0 - .dw 0x06c3, 0xcc36, 0x06cf, 0xcc36, 0x21, 0 - .dw 0x06d1, 0xcc36, 0x06d1, 0xcc36, 0x21, 0 - .dw 0x06d3, 0xcc36, 0x06ff, 0xcc36, 0x21, 0 - .dw 0x0701, 0xcc36, 0x0701, 0xcc36, 0x21, 0 - .dw 0x0703, 0xcc36, 0x070f, 0xcc36, 0x21, 0 - .dw 0x0711, 0xcc36, 0x0711, 0xcc36, 0x21, 0 - .dw 0x0713, 0xcc36, 0x073f, 0xcc36, 0x21, 0 - .dw 0x0741, 0xcc36, 0x0741, 0xcc36, 0x21, 0 - .dw 0x0743, 0xcc36, 0x074f, 0xcc36, 0x21, 0 - .dw 0x0751, 0xcc36, 0x0751, 0xcc36, 0x21, 0 - .dw 0x0753, 0xcc36, 0x077f, 0xcc36, 0x21, 0 - .dw 0x0781, 0xcc36, 0x0781, 0xcc36, 0x21, 0 - .dw 0x0783, 0xcc36, 0x078f, 0xcc36, 0x21, 0 - .dw 0x0791, 0xcc36, 0x0791, 0xcc36, 0x21, 0 - .dw 0x0793, 0xcc36, 0x07bf, 0xcc36, 0x21, 0 - .dw 0x07c1, 0xcc36, 0x07c1, 0xcc36, 0x21, 0 - .dw 0x07c3, 0xcc36, 0x07cf, 0xcc36, 0x21, 0 - .dw 0x07d1, 0xcc36, 0x07d1, 0xcc36, 0x21, 0 - .dw 0x07d3, 0xcc36, 0x07ff, 0xcc36, 0x21, 0 - .dw 0x0801, 0xcc36, 0x0801, 0xcc36, 0x21, 0 - .dw 0x0803, 0xcc36, 0x080f, 0xcc36, 0x21, 0 - .dw 0x0811, 0xcc36, 0x0811, 0xcc36, 0x21, 0 - .dw 0x0813, 0xcc36, 0x083f, 0xcc36, 0x21, 0 - .dw 0x0841, 0xcc36, 0x0841, 0xcc36, 0x21, 0 - .dw 0x0843, 0xcc36, 0x084f, 0xcc36, 0x21, 0 - .dw 0x0851, 0xcc36, 0x0851, 0xcc36, 0x21, 0 - .dw 0x0853, 0xcc36, 0x087f, 0xcc36, 0x21, 0 - .dw 0x0881, 0xcc36, 0x0881, 0xcc36, 0x21, 0 - .dw 0x0883, 0xcc36, 0x088f, 0xcc36, 0x21, 0 - .dw 0x0891, 0xcc36, 0x0891, 0xcc36, 0x21, 0 - .dw 0x0893, 0xcc36, 0x08bf, 0xcc36, 0x21, 0 - .dw 0x08c1, 0xcc36, 0x08c1, 0xcc36, 0x21, 0 - .dw 0x08c3, 0xcc36, 0x08cf, 0xcc36, 0x21, 0 - .dw 0x08d1, 0xcc36, 0x08d1, 0xcc36, 0x21, 0 - .dw 0x08d3, 0xcc36, 0x08ff, 0xcc36, 0x21, 0 - .dw 0x0901, 0xcc36, 0x0901, 0xcc36, 0x21, 0 - .dw 0x0903, 0xcc36, 0x090f, 0xcc36, 0x21, 0 - .dw 0x0911, 0xcc36, 0x0911, 0xcc36, 0x21, 0 - .dw 0x0913, 0xcc36, 0x093f, 0xcc36, 0x21, 0 - .dw 0x0941, 0xcc36, 0x0941, 0xcc36, 0x21, 0 - .dw 0x0943, 0xcc36, 0x094f, 0xcc36, 0x21, 0 - .dw 0x0951, 0xcc36, 0x0951, 0xcc36, 0x21, 0 - .dw 0x0953, 0xcc36, 0x097f, 0xcc36, 0x21, 0 - .dw 0x0981, 0xcc36, 0x0981, 0xcc36, 0x21, 0 - .dw 0x0983, 0xcc36, 0x098f, 0xcc36, 0x21, 0 - .dw 0x0991, 0xcc36, 0x0991, 0xcc36, 0x21, 0 - .dw 0x0993, 0xcc36, 0x09bf, 0xcc36, 0x21, 0 - .dw 0x09c1, 0xcc36, 0x09c1, 0xcc36, 0x21, 0 - .dw 0x09c3, 0xcc36, 0x09cf, 0xcc36, 0x21, 0 - .dw 0x09d1, 0xcc36, 0x09d1, 0xcc36, 0x21, 0 - .dw 0x09d3, 0xcc36, 0x09ff, 0xcc36, 0x21, 0 - .dw 0x0a01, 0xcc36, 0x0a01, 0xcc36, 0x21, 0 - .dw 0x0a03, 0xcc36, 0x0a0f, 0xcc36, 0x21, 0 - .dw 0x0a11, 0xcc36, 0x0a11, 0xcc36, 0x21, 0 - .dw 0x0a13, 0xcc36, 0x0a3f, 0xcc36, 0x21, 0 - .dw 0x0a41, 0xcc36, 0x0a41, 0xcc36, 0x21, 0 - .dw 0x0a43, 0xcc36, 0x0a4f, 0xcc36, 0x21, 0 - .dw 0x0a51, 0xcc36, 0x0a51, 0xcc36, 0x21, 0 - .dw 0x0a53, 0xcc36, 0x0a7f, 0xcc36, 0x21, 0 - .dw 0x0a81, 0xcc36, 0x0a81, 0xcc36, 0x21, 0 - .dw 0x0a83, 0xcc36, 0x0a8f, 0xcc36, 0x21, 0 - .dw 0x0a91, 0xcc36, 0x0a91, 0xcc36, 0x21, 0 - .dw 0x0a93, 0xcc36, 0x0abf, 0xcc36, 0x21, 0 - .dw 0x0ac1, 0xcc36, 0x0ac1, 0xcc36, 0x21, 0 - .dw 0x0ac3, 0xcc36, 0x0acf, 0xcc36, 0x21, 0 - .dw 0x0ad1, 0xcc36, 0x0ad1, 0xcc36, 0x21, 0 - .dw 0x0ad3, 0xcc36, 0x0aff, 0xcc36, 0x21, 0 - .dw 0x0b01, 0xcc36, 0x0b01, 0xcc36, 0x21, 0 - .dw 0x0b03, 0xcc36, 0x0b0f, 0xcc36, 0x21, 0 - .dw 0x0b11, 0xcc36, 0x0b11, 0xcc36, 0x21, 0 - .dw 0x0b13, 0xcc36, 0x0b3f, 0xcc36, 0x21, 0 - .dw 0x0b41, 0xcc36, 0x0b41, 0xcc36, 0x21, 0 - .dw 0x0b43, 0xcc36, 0x0b4f, 0xcc36, 0x21, 0 - .dw 0x0b51, 0xcc36, 0x0b51, 0xcc36, 0x21, 0 - .dw 0x0b53, 0xcc36, 0x0b7f, 0xcc36, 0x21, 0 - .dw 0x0b81, 0xcc36, 0x0b81, 0xcc36, 0x21, 0 - .dw 0x0b83, 0xcc36, 0x0b8f, 0xcc36, 0x21, 0 - .dw 0x0b91, 0xcc36, 0x0b91, 0xcc36, 0x21, 0 - .dw 0x0b93, 0xcc36, 0x0bbf, 0xcc36, 0x21, 0 - .dw 0x0bc1, 0xcc36, 0x0bc1, 0xcc36, 0x21, 0 - .dw 0x0bc3, 0xcc36, 0x0bcf, 0xcc36, 0x21, 0 - .dw 0x0bd1, 0xcc36, 0x0bd1, 0xcc36, 0x21, 0 - .dw 0x0bd3, 0xcc36, 0x0bff, 0xcc36, 0x21, 0 - .dw 0x0c01, 0xcc36, 0x0c01, 0xcc36, 0x21, 0 - .dw 0x0c03, 0xcc36, 0x0c0f, 0xcc36, 0x21, 0 - .dw 0x0c11, 0xcc36, 0x0c11, 0xcc36, 0x21, 0 - .dw 0x0c13, 0xcc36, 0x0c3f, 0xcc36, 0x21, 0 - .dw 0x0c41, 0xcc36, 0x0c41, 0xcc36, 0x21, 0 - .dw 0x0c43, 0xcc36, 0x0c4f, 0xcc36, 0x21, 0 - .dw 0x0c51, 0xcc36, 0x0c51, 0xcc36, 0x21, 0 - .dw 0x0c53, 0xcc36, 0x0c7f, 0xcc36, 0x21, 0 - .dw 0x0c81, 0xcc36, 0x0c81, 0xcc36, 0x21, 0 - .dw 0x0c83, 0xcc36, 0x0c8f, 0xcc36, 0x21, 0 - .dw 0x0c91, 0xcc36, 0x0c91, 0xcc36, 0x21, 0 - .dw 0x0c93, 0xcc36, 0x0cbf, 0xcc36, 0x21, 0 - .dw 0x0cc1, 0xcc36, 0x0cc1, 0xcc36, 0x21, 0 - .dw 0x0cc3, 0xcc36, 0x0ccf, 0xcc36, 0x21, 0 - .dw 0x0cd1, 0xcc36, 0x0cd1, 0xcc36, 0x21, 0 - .dw 0x0cd3, 0xcc36, 0x0cff, 0xcc36, 0x21, 0 - .dw 0x0d01, 0xcc36, 0x0d01, 0xcc36, 0x21, 0 - .dw 0x0d03, 0xcc36, 0x0d0f, 0xcc36, 0x21, 0 - .dw 0x0d11, 0xcc36, 0x0d11, 0xcc36, 0x21, 0 - .dw 0x0d13, 0xcc36, 0x0d3f, 0xcc36, 0x21, 0 - .dw 0x0d41, 0xcc36, 0x0d41, 0xcc36, 0x21, 0 - .dw 0x0d43, 0xcc36, 0x0d4f, 0xcc36, 0x21, 0 - .dw 0x0d51, 0xcc36, 0x0d51, 0xcc36, 0x21, 0 - .dw 0x0d53, 0xcc36, 0x0d7f, 0xcc36, 0x21, 0 - .dw 0x0d81, 0xcc36, 0x0d81, 0xcc36, 0x21, 0 - .dw 0x0d83, 0xcc36, 0x0d8f, 0xcc36, 0x21, 0 - .dw 0x0d91, 0xcc36, 0x0d91, 0xcc36, 0x21, 0 - .dw 0x0d93, 0xcc36, 0x0dbf, 0xcc36, 0x21, 0 - .dw 0x0dc1, 0xcc36, 0x0dc1, 0xcc36, 0x21, 0 - .dw 0x0dc3, 0xcc36, 0x0dcf, 0xcc36, 0x21, 0 - .dw 0x0dd1, 0xcc36, 0x0dd1, 0xcc36, 0x21, 0 - .dw 0x0dd3, 0xcc36, 0x0dff, 0xcc36, 0x21, 0 - .dw 0x0e01, 0xcc36, 0x0e01, 0xcc36, 0x21, 0 - .dw 0x0e03, 0xcc36, 0x0e0f, 0xcc36, 0x21, 0 - .dw 0x0e11, 0xcc36, 0x0e11, 0xcc36, 0x21, 0 - .dw 0x0e13, 0xcc36, 0x0e3f, 0xcc36, 0x21, 0 - .dw 0x0e41, 0xcc36, 0x0e41, 0xcc36, 0x21, 0 - .dw 0x0e43, 0xcc36, 0x0e4f, 0xcc36, 0x21, 0 - .dw 0x0e51, 0xcc36, 0x0e51, 0xcc36, 0x21, 0 - .dw 0x0e53, 0xcc36, 0x0e7f, 0xcc36, 0x21, 0 - .dw 0x0e81, 0xcc36, 0x0e81, 0xcc36, 0x21, 0 - .dw 0x0e83, 0xcc36, 0x0e8f, 0xcc36, 0x21, 0 - .dw 0x0e91, 0xcc36, 0x0e91, 0xcc36, 0x21, 0 - .dw 0x0e93, 0xcc36, 0x0ebf, 0xcc36, 0x21, 0 - .dw 0x0ec1, 0xcc36, 0x0ec1, 0xcc36, 0x21, 0 - .dw 0x0ec3, 0xcc36, 0x0ecf, 0xcc36, 0x21, 0 - .dw 0x0ed1, 0xcc36, 0x0ed1, 0xcc36, 0x21, 0 - .dw 0x0ed3, 0xcc36, 0x0eff, 0xcc36, 0x21, 0 - .dw 0x0f01, 0xcc36, 0x0f01, 0xcc36, 0x21, 0 - .dw 0x0f03, 0xcc36, 0x0f0f, 0xcc36, 0x21, 0 - .dw 0x0f11, 0xcc36, 0x0f11, 0xcc36, 0x21, 0 - .dw 0x0f13, 0xcc36, 0x0f3f, 0xcc36, 0x21, 0 - .dw 0x0f41, 0xcc36, 0x0f41, 0xcc36, 0x21, 0 - .dw 0x0f43, 0xcc36, 0x0f4f, 0xcc36, 0x21, 0 - .dw 0x0f51, 0xcc36, 0x0f51, 0xcc36, 0x21, 0 - .dw 0x0f53, 0xcc36, 0x0f7f, 0xcc36, 0x21, 0 - .dw 0x0f81, 0xcc36, 0x0f81, 0xcc36, 0x21, 0 - .dw 0x0f83, 0xcc36, 0x0f8f, 0xcc36, 0x21, 0 - .dw 0x0f91, 0xcc36, 0x0f91, 0xcc36, 0x21, 0 - .dw 0x0f93, 0xcc36, 0x0fbf, 0xcc36, 0x21, 0 - .dw 0x0fc1, 0xcc36, 0x0fc1, 0xcc36, 0x21, 0 - .dw 0x0fc3, 0xcc36, 0x0fcf, 0xcc36, 0x21, 0 - .dw 0x0fd1, 0xcc36, 0x0fd1, 0xcc36, 0x21, 0 - .dw 0x0fd3, 0xcc36, 0x1fff, 0xcc36, 0x21, 0 - .dw 0x2001, 0xcc36, 0x2001, 0xcc36, 0x21, 0 - .dw 0x2003, 0xcc36, 0x200f, 0xcc36, 0x21, 0 - .dw 0x2011, 0xcc36, 0x2011, 0xcc36, 0x21, 0 - .dw 0x2013, 0xcc36, 0x203f, 0xcc36, 0x21, 0 - .dw 0x2041, 0xcc36, 0x2041, 0xcc36, 0x21, 0 - .dw 0x2043, 0xcc36, 0x204f, 0xcc36, 0x21, 0 - .dw 0x2051, 0xcc36, 0x2051, 0xcc36, 0x21, 0 - .dw 0x2053, 0xcc36, 0x207f, 0xcc36, 0x21, 0 - .dw 0x2081, 0xcc36, 0x2081, 0xcc36, 0x21, 0 - .dw 0x2083, 0xcc36, 0x208f, 0xcc36, 0x21, 0 - .dw 0x2091, 0xcc36, 0x2091, 0xcc36, 0x21, 0 - .dw 0x2093, 0xcc36, 0x20bf, 0xcc36, 0x21, 0 - .dw 0x20c1, 0xcc36, 0x20c1, 0xcc36, 0x21, 0 - .dw 0x20c3, 0xcc36, 0x20cf, 0xcc36, 0x21, 0 - .dw 0x20d1, 0xcc36, 0x20d1, 0xcc36, 0x21, 0 - .dw 0x20d3, 0xcc36, 0x20ff, 0xcc36, 0x21, 0 - .dw 0x2101, 0xcc36, 0x2101, 0xcc36, 0x21, 0 - .dw 0x2103, 0xcc36, 0x210f, 0xcc36, 0x21, 0 - .dw 0x2111, 0xcc36, 0x2111, 0xcc36, 0x21, 0 - .dw 0x2113, 0xcc36, 0x213f, 0xcc36, 0x21, 0 - .dw 0x2141, 0xcc36, 0x2141, 0xcc36, 0x21, 0 - .dw 0x2143, 0xcc36, 0x214f, 0xcc36, 0x21, 0 - .dw 0x2151, 0xcc36, 0x2151, 0xcc36, 0x21, 0 - .dw 0x2153, 0xcc36, 0x217f, 0xcc36, 0x21, 0 - .dw 0x2181, 0xcc36, 0x2181, 0xcc36, 0x21, 0 - .dw 0x2183, 0xcc36, 0x218f, 0xcc36, 0x21, 0 - .dw 0x2191, 0xcc36, 0x2191, 0xcc36, 0x21, 0 - .dw 0x2193, 0xcc36, 0x21bf, 0xcc36, 0x21, 0 - .dw 0x21c1, 0xcc36, 0x21c1, 0xcc36, 0x21, 0 - .dw 0x21c3, 0xcc36, 0x21cf, 0xcc36, 0x21, 0 - .dw 0x21d1, 0xcc36, 0x21d1, 0xcc36, 0x21, 0 - .dw 0x21d3, 0xcc36, 0x21ff, 0xcc36, 0x21, 0 - .dw 0x2201, 0xcc36, 0x2201, 0xcc36, 0x21, 0 - .dw 0x2203, 0xcc36, 0x220f, 0xcc36, 0x21, 0 - .dw 0x2211, 0xcc36, 0x2211, 0xcc36, 0x21, 0 - .dw 0x2213, 0xcc36, 0x223f, 0xcc36, 0x21, 0 - .dw 0x2241, 0xcc36, 0x2241, 0xcc36, 0x21, 0 - .dw 0x2243, 0xcc36, 0x224f, 0xcc36, 0x21, 0 - .dw 0x2251, 0xcc36, 0x2251, 0xcc36, 0x21, 0 - .dw 0x2253, 0xcc36, 0x227f, 0xcc36, 0x21, 0 - .dw 0x2281, 0xcc36, 0x2281, 0xcc36, 0x21, 0 - .dw 0x2283, 0xcc36, 0x228f, 0xcc36, 0x21, 0 - .dw 0x2291, 0xcc36, 0x2291, 0xcc36, 0x21, 0 - .dw 0x2293, 0xcc36, 0x22bf, 0xcc36, 0x21, 0 - .dw 0x22c1, 0xcc36, 0x22c1, 0xcc36, 0x21, 0 - .dw 0x22c3, 0xcc36, 0x22cf, 0xcc36, 0x21, 0 - .dw 0x22d1, 0xcc36, 0x22d1, 0xcc36, 0x21, 0 - .dw 0x22d3, 0xcc36, 0x22ff, 0xcc36, 0x21, 0 - .dw 0x2301, 0xcc36, 0x2301, 0xcc36, 0x21, 0 - .dw 0x2303, 0xcc36, 0x230f, 0xcc36, 0x21, 0 - .dw 0x2311, 0xcc36, 0x2311, 0xcc36, 0x21, 0 - .dw 0x2313, 0xcc36, 0x233f, 0xcc36, 0x21, 0 - .dw 0x2341, 0xcc36, 0x2341, 0xcc36, 0x21, 0 - .dw 0x2343, 0xcc36, 0x234f, 0xcc36, 0x21, 0 - .dw 0x2351, 0xcc36, 0x2351, 0xcc36, 0x21, 0 - .dw 0x2353, 0xcc36, 0x237f, 0xcc36, 0x21, 0 - .dw 0x2381, 0xcc36, 0x2381, 0xcc36, 0x21, 0 - .dw 0x2383, 0xcc36, 0x238f, 0xcc36, 0x21, 0 - .dw 0x2391, 0xcc36, 0x2391, 0xcc36, 0x21, 0 - .dw 0x2393, 0xcc36, 0x23bf, 0xcc36, 0x21, 0 - .dw 0x23c1, 0xcc36, 0x23c1, 0xcc36, 0x21, 0 - .dw 0x23c3, 0xcc36, 0x23cf, 0xcc36, 0x21, 0 - .dw 0x23d1, 0xcc36, 0x23d1, 0xcc36, 0x21, 0 - .dw 0x23d3, 0xcc36, 0x23ff, 0xcc36, 0x21, 0 - .dw 0x2401, 0xcc36, 0x2401, 0xcc36, 0x21, 0 - .dw 0x2403, 0xcc36, 0x240f, 0xcc36, 0x21, 0 - .dw 0x2411, 0xcc36, 0x2411, 0xcc36, 0x21, 0 - .dw 0x2413, 0xcc36, 0x243f, 0xcc36, 0x21, 0 - .dw 0x2441, 0xcc36, 0x2441, 0xcc36, 0x21, 0 - .dw 0x2443, 0xcc36, 0x244f, 0xcc36, 0x21, 0 - .dw 0x2451, 0xcc36, 0x2451, 0xcc36, 0x21, 0 - .dw 0x2453, 0xcc36, 0x247f, 0xcc36, 0x21, 0 - .dw 0x2481, 0xcc36, 0x2481, 0xcc36, 0x21, 0 - .dw 0x2483, 0xcc36, 0x248f, 0xcc36, 0x21, 0 - .dw 0x2491, 0xcc36, 0x2491, 0xcc36, 0x21, 0 - .dw 0x2493, 0xcc36, 0x24bf, 0xcc36, 0x21, 0 - .dw 0x24c1, 0xcc36, 0x24c1, 0xcc36, 0x21, 0 - .dw 0x24c3, 0xcc36, 0x24cf, 0xcc36, 0x21, 0 - .dw 0x24d1, 0xcc36, 0x24d1, 0xcc36, 0x21, 0 - .dw 0x24d3, 0xcc36, 0x24ff, 0xcc36, 0x21, 0 - .dw 0x2501, 0xcc36, 0x2501, 0xcc36, 0x21, 0 - .dw 0x2503, 0xcc36, 0x250f, 0xcc36, 0x21, 0 - .dw 0x2511, 0xcc36, 0x2511, 0xcc36, 0x21, 0 - .dw 0x2513, 0xcc36, 0x253f, 0xcc36, 0x21, 0 - .dw 0x2541, 0xcc36, 0x2541, 0xcc36, 0x21, 0 - .dw 0x2543, 0xcc36, 0x254f, 0xcc36, 0x21, 0 - .dw 0x2551, 0xcc36, 0x2551, 0xcc36, 0x21, 0 - .dw 0x2553, 0xcc36, 0x257f, 0xcc36, 0x21, 0 - .dw 0x2581, 0xcc36, 0x2581, 0xcc36, 0x21, 0 - .dw 0x2583, 0xcc36, 0x258f, 0xcc36, 0x21, 0 - .dw 0x2591, 0xcc36, 0x2591, 0xcc36, 0x21, 0 - .dw 0x2593, 0xcc36, 0x25bf, 0xcc36, 0x21, 0 - .dw 0x25c1, 0xcc36, 0x25c1, 0xcc36, 0x21, 0 - .dw 0x25c3, 0xcc36, 0x25cf, 0xcc36, 0x21, 0 - .dw 0x25d1, 0xcc36, 0x25d1, 0xcc36, 0x21, 0 - .dw 0x25d3, 0xcc36, 0x25ff, 0xcc36, 0x21, 0 - .dw 0x2601, 0xcc36, 0x2601, 0xcc36, 0x21, 0 - .dw 0x2603, 0xcc36, 0x260f, 0xcc36, 0x21, 0 - .dw 0x2611, 0xcc36, 0x2611, 0xcc36, 0x21, 0 - .dw 0x2613, 0xcc36, 0x263f, 0xcc36, 0x21, 0 - .dw 0x2641, 0xcc36, 0x2641, 0xcc36, 0x21, 0 - .dw 0x2643, 0xcc36, 0x264f, 0xcc36, 0x21, 0 - .dw 0x2651, 0xcc36, 0x2651, 0xcc36, 0x21, 0 - .dw 0x2653, 0xcc36, 0x267f, 0xcc36, 0x21, 0 - .dw 0x2681, 0xcc36, 0x2681, 0xcc36, 0x21, 0 - .dw 0x2683, 0xcc36, 0x268f, 0xcc36, 0x21, 0 - .dw 0x2691, 0xcc36, 0x2691, 0xcc36, 0x21, 0 - .dw 0x2693, 0xcc36, 0x26bf, 0xcc36, 0x21, 0 - .dw 0x26c1, 0xcc36, 0x26c1, 0xcc36, 0x21, 0 - .dw 0x26c3, 0xcc36, 0x26cf, 0xcc36, 0x21, 0 - .dw 0x26d1, 0xcc36, 0x26d1, 0xcc36, 0x21, 0 - .dw 0x26d3, 0xcc36, 0x26ff, 0xcc36, 0x21, 0 - .dw 0x2701, 0xcc36, 0x2701, 0xcc36, 0x21, 0 - .dw 0x2703, 0xcc36, 0x270f, 0xcc36, 0x21, 0 - .dw 0x2711, 0xcc36, 0x2711, 0xcc36, 0x21, 0 - .dw 0x2713, 0xcc36, 0x273f, 0xcc36, 0x21, 0 - .dw 0x2741, 0xcc36, 0x2741, 0xcc36, 0x21, 0 - .dw 0x2743, 0xcc36, 0x274f, 0xcc36, 0x21, 0 - .dw 0x2751, 0xcc36, 0x2751, 0xcc36, 0x21, 0 - .dw 0x2753, 0xcc36, 0x277f, 0xcc36, 0x21, 0 - .dw 0x2781, 0xcc36, 0x2781, 0xcc36, 0x21, 0 - .dw 0x2783, 0xcc36, 0x278f, 0xcc36, 0x21, 0 - .dw 0x2791, 0xcc36, 0x2791, 0xcc36, 0x21, 0 - .dw 0x2793, 0xcc36, 0x27bf, 0xcc36, 0x21, 0 - .dw 0x27c1, 0xcc36, 0x27c1, 0xcc36, 0x21, 0 - .dw 0x27c3, 0xcc36, 0x27cf, 0xcc36, 0x21, 0 - .dw 0x27d1, 0xcc36, 0x27d1, 0xcc36, 0x21, 0 - .dw 0x27d3, 0xcc36, 0x27ff, 0xcc36, 0x21, 0 - .dw 0x2801, 0xcc36, 0x2801, 0xcc36, 0x21, 0 - .dw 0x2803, 0xcc36, 0x280f, 0xcc36, 0x21, 0 - .dw 0x2811, 0xcc36, 0x2811, 0xcc36, 0x21, 0 - .dw 0x2813, 0xcc36, 0x283f, 0xcc36, 0x21, 0 - .dw 0x2841, 0xcc36, 0x2841, 0xcc36, 0x21, 0 - .dw 0x2843, 0xcc36, 0x284f, 0xcc36, 0x21, 0 - .dw 0x2851, 0xcc36, 0x2851, 0xcc36, 0x21, 0 - .dw 0x2853, 0xcc36, 0x287f, 0xcc36, 0x21, 0 - .dw 0x2881, 0xcc36, 0x2881, 0xcc36, 0x21, 0 - .dw 0x2883, 0xcc36, 0x288f, 0xcc36, 0x21, 0 - .dw 0x2891, 0xcc36, 0x2891, 0xcc36, 0x21, 0 - .dw 0x2893, 0xcc36, 0x28bf, 0xcc36, 0x21, 0 - .dw 0x28c1, 0xcc36, 0x28c1, 0xcc36, 0x21, 0 - .dw 0x28c3, 0xcc36, 0x28cf, 0xcc36, 0x21, 0 - .dw 0x28d1, 0xcc36, 0x28d1, 0xcc36, 0x21, 0 - .dw 0x28d3, 0xcc36, 0x28ff, 0xcc36, 0x21, 0 - .dw 0x2901, 0xcc36, 0x2901, 0xcc36, 0x21, 0 - .dw 0x2903, 0xcc36, 0x290f, 0xcc36, 0x21, 0 - .dw 0x2911, 0xcc36, 0x2911, 0xcc36, 0x21, 0 - .dw 0x2913, 0xcc36, 0x293f, 0xcc36, 0x21, 0 - .dw 0x2941, 0xcc36, 0x2941, 0xcc36, 0x21, 0 - .dw 0x2943, 0xcc36, 0x294f, 0xcc36, 0x21, 0 - .dw 0x2951, 0xcc36, 0x2951, 0xcc36, 0x21, 0 - .dw 0x2953, 0xcc36, 0x297f, 0xcc36, 0x21, 0 - .dw 0x2981, 0xcc36, 0x2981, 0xcc36, 0x21, 0 - .dw 0x2983, 0xcc36, 0x298f, 0xcc36, 0x21, 0 - .dw 0x2991, 0xcc36, 0x2991, 0xcc36, 0x21, 0 - .dw 0x2993, 0xcc36, 0x29bf, 0xcc36, 0x21, 0 - .dw 0x29c1, 0xcc36, 0x29c1, 0xcc36, 0x21, 0 - .dw 0x29c3, 0xcc36, 0x29cf, 0xcc36, 0x21, 0 - .dw 0x29d1, 0xcc36, 0x29d1, 0xcc36, 0x21, 0 - .dw 0x29d3, 0xcc36, 0x29ff, 0xcc36, 0x21, 0 - .dw 0x2a01, 0xcc36, 0x2a01, 0xcc36, 0x21, 0 - .dw 0x2a03, 0xcc36, 0x2a0f, 0xcc36, 0x21, 0 - .dw 0x2a11, 0xcc36, 0x2a11, 0xcc36, 0x21, 0 - .dw 0x2a13, 0xcc36, 0x2a3f, 0xcc36, 0x21, 0 - .dw 0x2a41, 0xcc36, 0x2a41, 0xcc36, 0x21, 0 - .dw 0x2a43, 0xcc36, 0x2a4f, 0xcc36, 0x21, 0 - .dw 0x2a51, 0xcc36, 0x2a51, 0xcc36, 0x21, 0 - .dw 0x2a53, 0xcc36, 0x2a7f, 0xcc36, 0x21, 0 - .dw 0x2a81, 0xcc36, 0x2a81, 0xcc36, 0x21, 0 - .dw 0x2a83, 0xcc36, 0x2a8f, 0xcc36, 0x21, 0 - .dw 0x2a91, 0xcc36, 0x2a91, 0xcc36, 0x21, 0 - .dw 0x2a93, 0xcc36, 0x2abf, 0xcc36, 0x21, 0 - .dw 0x2ac1, 0xcc36, 0x2ac1, 0xcc36, 0x21, 0 - .dw 0x2ac3, 0xcc36, 0x2acf, 0xcc36, 0x21, 0 - .dw 0x2ad1, 0xcc36, 0x2ad1, 0xcc36, 0x21, 0 - .dw 0x2ad3, 0xcc36, 0x2aff, 0xcc36, 0x21, 0 - .dw 0x2b01, 0xcc36, 0x2b01, 0xcc36, 0x21, 0 - .dw 0x2b03, 0xcc36, 0x2b0f, 0xcc36, 0x21, 0 - .dw 0x2b11, 0xcc36, 0x2b11, 0xcc36, 0x21, 0 - .dw 0x2b13, 0xcc36, 0x2b3f, 0xcc36, 0x21, 0 - .dw 0x2b41, 0xcc36, 0x2b41, 0xcc36, 0x21, 0 - .dw 0x2b43, 0xcc36, 0x2b4f, 0xcc36, 0x21, 0 - .dw 0x2b51, 0xcc36, 0x2b51, 0xcc36, 0x21, 0 - .dw 0x2b53, 0xcc36, 0x2b7f, 0xcc36, 0x21, 0 - .dw 0x2b81, 0xcc36, 0x2b81, 0xcc36, 0x21, 0 - .dw 0x2b83, 0xcc36, 0x2b8f, 0xcc36, 0x21, 0 - .dw 0x2b91, 0xcc36, 0x2b91, 0xcc36, 0x21, 0 - .dw 0x2b93, 0xcc36, 0x2bbf, 0xcc36, 0x21, 0 - .dw 0x2bc1, 0xcc36, 0x2bc1, 0xcc36, 0x21, 0 - .dw 0x2bc3, 0xcc36, 0x2bcf, 0xcc36, 0x21, 0 - .dw 0x2bd1, 0xcc36, 0x2bd1, 0xcc36, 0x21, 0 - .dw 0x2bd3, 0xcc36, 0x2bff, 0xcc36, 0x21, 0 - .dw 0x2c01, 0xcc36, 0x2c01, 0xcc36, 0x21, 0 - .dw 0x2c03, 0xcc36, 0x2c0f, 0xcc36, 0x21, 0 - .dw 0x2c11, 0xcc36, 0x2c11, 0xcc36, 0x21, 0 - .dw 0x2c13, 0xcc36, 0x2c3f, 0xcc36, 0x21, 0 - .dw 0x2c41, 0xcc36, 0x2c41, 0xcc36, 0x21, 0 - .dw 0x2c43, 0xcc36, 0x2c4f, 0xcc36, 0x21, 0 - .dw 0x2c51, 0xcc36, 0x2c51, 0xcc36, 0x21, 0 - .dw 0x2c53, 0xcc36, 0x2c7f, 0xcc36, 0x21, 0 - .dw 0x2c81, 0xcc36, 0x2c81, 0xcc36, 0x21, 0 - .dw 0x2c83, 0xcc36, 0x2c8f, 0xcc36, 0x21, 0 - .dw 0x2c91, 0xcc36, 0x2c91, 0xcc36, 0x21, 0 - .dw 0x2c93, 0xcc36, 0x2cbf, 0xcc36, 0x21, 0 - .dw 0x2cc1, 0xcc36, 0x2cc1, 0xcc36, 0x21, 0 - .dw 0x2cc3, 0xcc36, 0x2ccf, 0xcc36, 0x21, 0 - .dw 0x2cd1, 0xcc36, 0x2cd1, 0xcc36, 0x21, 0 - .dw 0x2cd3, 0xcc36, 0x2cff, 0xcc36, 0x21, 0 - .dw 0x2d01, 0xcc36, 0x2d01, 0xcc36, 0x21, 0 - .dw 0x2d03, 0xcc36, 0x2d0f, 0xcc36, 0x21, 0 - .dw 0x2d11, 0xcc36, 0x2d11, 0xcc36, 0x21, 0 - .dw 0x2d13, 0xcc36, 0x2d3f, 0xcc36, 0x21, 0 - .dw 0x2d41, 0xcc36, 0x2d41, 0xcc36, 0x21, 0 - .dw 0x2d43, 0xcc36, 0x2d4f, 0xcc36, 0x21, 0 - .dw 0x2d51, 0xcc36, 0x2d51, 0xcc36, 0x21, 0 - .dw 0x2d53, 0xcc36, 0x2d7f, 0xcc36, 0x21, 0 - .dw 0x2d81, 0xcc36, 0x2d81, 0xcc36, 0x21, 0 - .dw 0x2d83, 0xcc36, 0x2d8f, 0xcc36, 0x21, 0 - .dw 0x2d91, 0xcc36, 0x2d91, 0xcc36, 0x21, 0 - .dw 0x2d93, 0xcc36, 0x2dbf, 0xcc36, 0x21, 0 - .dw 0x2dc1, 0xcc36, 0x2dc1, 0xcc36, 0x21, 0 - .dw 0x2dc3, 0xcc36, 0x2dcf, 0xcc36, 0x21, 0 - .dw 0x2dd1, 0xcc36, 0x2dd1, 0xcc36, 0x21, 0 - .dw 0x2dd3, 0xcc36, 0x2dff, 0xcc36, 0x21, 0 - .dw 0x2e01, 0xcc36, 0x2e01, 0xcc36, 0x21, 0 - .dw 0x2e03, 0xcc36, 0x2e0f, 0xcc36, 0x21, 0 - .dw 0x2e11, 0xcc36, 0x2e11, 0xcc36, 0x21, 0 - .dw 0x2e13, 0xcc36, 0x2e3f, 0xcc36, 0x21, 0 - .dw 0x2e41, 0xcc36, 0x2e41, 0xcc36, 0x21, 0 - .dw 0x2e43, 0xcc36, 0x2e4f, 0xcc36, 0x21, 0 - .dw 0x2e51, 0xcc36, 0x2e51, 0xcc36, 0x21, 0 - .dw 0x2e53, 0xcc36, 0x2e7f, 0xcc36, 0x21, 0 - .dw 0x2e81, 0xcc36, 0x2e81, 0xcc36, 0x21, 0 - .dw 0x2e83, 0xcc36, 0x2e8f, 0xcc36, 0x21, 0 - .dw 0x2e91, 0xcc36, 0x2e91, 0xcc36, 0x21, 0 - .dw 0x2e93, 0xcc36, 0x2ebf, 0xcc36, 0x21, 0 - .dw 0x2ec1, 0xcc36, 0x2ec1, 0xcc36, 0x21, 0 - .dw 0x2ec3, 0xcc36, 0x2ecf, 0xcc36, 0x21, 0 - .dw 0x2ed1, 0xcc36, 0x2ed1, 0xcc36, 0x21, 0 - .dw 0x2ed3, 0xcc36, 0x2eff, 0xcc36, 0x21, 0 - .dw 0x2f01, 0xcc36, 0x2f01, 0xcc36, 0x21, 0 - .dw 0x2f03, 0xcc36, 0x2f0f, 0xcc36, 0x21, 0 - .dw 0x2f11, 0xcc36, 0x2f11, 0xcc36, 0x21, 0 - .dw 0x2f13, 0xcc36, 0x2f3f, 0xcc36, 0x21, 0 - .dw 0x2f41, 0xcc36, 0x2f41, 0xcc36, 0x21, 0 - .dw 0x2f43, 0xcc36, 0x2f4f, 0xcc36, 0x21, 0 - .dw 0x2f51, 0xcc36, 0x2f51, 0xcc36, 0x21, 0 - .dw 0x2f53, 0xcc36, 0x2f7f, 0xcc36, 0x21, 0 - .dw 0x2f81, 0xcc36, 0x2f81, 0xcc36, 0x21, 0 - .dw 0x2f83, 0xcc36, 0x2f8f, 0xcc36, 0x21, 0 - .dw 0x2f91, 0xcc36, 0x2f91, 0xcc36, 0x21, 0 - .dw 0x2f93, 0xcc36, 0x2fbf, 0xcc36, 0x21, 0 - .dw 0x2fc1, 0xcc36, 0x2fc1, 0xcc36, 0x21, 0 - .dw 0x2fc3, 0xcc36, 0x2fcf, 0xcc36, 0x21, 0 - .dw 0x2fd1, 0xcc36, 0x2fd1, 0xcc36, 0x21, 0 - .dw 0x2fd3, 0xcc36, 0x3fff, 0xcc36, 0x21, 0 - .dw 0x4001, 0xcc36, 0x4001, 0xcc36, 0x21, 0 - .dw 0x4003, 0xcc36, 0x400f, 0xcc36, 0x21, 0 - .dw 0x4011, 0xcc36, 0x4011, 0xcc36, 0x21, 0 - .dw 0x4013, 0xcc36, 0x403f, 0xcc36, 0x21, 0 - .dw 0x4041, 0xcc36, 0x4041, 0xcc36, 0x21, 0 - .dw 0x4043, 0xcc36, 0x404f, 0xcc36, 0x21, 0 - .dw 0x4051, 0xcc36, 0x4051, 0xcc36, 0x21, 0 - .dw 0x4053, 0xcc36, 0x407f, 0xcc36, 0x21, 0 - .dw 0x4081, 0xcc36, 0x4081, 0xcc36, 0x21, 0 - .dw 0x4083, 0xcc36, 0x408f, 0xcc36, 0x21, 0 - .dw 0x4091, 0xcc36, 0x4091, 0xcc36, 0x21, 0 - .dw 0x4093, 0xcc36, 0x40bf, 0xcc36, 0x21, 0 - .dw 0x40c1, 0xcc36, 0x40c1, 0xcc36, 0x21, 0 - .dw 0x40c3, 0xcc36, 0x40cf, 0xcc36, 0x21, 0 - .dw 0x40d1, 0xcc36, 0x40d1, 0xcc36, 0x21, 0 - .dw 0x40d3, 0xcc36, 0x40ff, 0xcc36, 0x21, 0 - .dw 0x4101, 0xcc36, 0x4101, 0xcc36, 0x21, 0 - .dw 0x4103, 0xcc36, 0x410f, 0xcc36, 0x21, 0 - .dw 0x4111, 0xcc36, 0x4111, 0xcc36, 0x21, 0 - .dw 0x4113, 0xcc36, 0x413f, 0xcc36, 0x21, 0 - .dw 0x4141, 0xcc36, 0x4141, 0xcc36, 0x21, 0 - .dw 0x4143, 0xcc36, 0x414f, 0xcc36, 0x21, 0 - .dw 0x4151, 0xcc36, 0x4151, 0xcc36, 0x21, 0 - .dw 0x4153, 0xcc36, 0x417f, 0xcc36, 0x21, 0 - .dw 0x4181, 0xcc36, 0x4181, 0xcc36, 0x21, 0 - .dw 0x4183, 0xcc36, 0x418f, 0xcc36, 0x21, 0 - .dw 0x4191, 0xcc36, 0x4191, 0xcc36, 0x21, 0 - .dw 0x4193, 0xcc36, 0x41bf, 0xcc36, 0x21, 0 - .dw 0x41c1, 0xcc36, 0x41c1, 0xcc36, 0x21, 0 - .dw 0x41c3, 0xcc36, 0x41cf, 0xcc36, 0x21, 0 - .dw 0x41d1, 0xcc36, 0x41d1, 0xcc36, 0x21, 0 - .dw 0x41d3, 0xcc36, 0x41ff, 0xcc36, 0x21, 0 - .dw 0x4201, 0xcc36, 0x4201, 0xcc36, 0x21, 0 - .dw 0x4203, 0xcc36, 0x420f, 0xcc36, 0x21, 0 - .dw 0x4211, 0xcc36, 0x4211, 0xcc36, 0x21, 0 - .dw 0x4213, 0xcc36, 0x423f, 0xcc36, 0x21, 0 - .dw 0x4241, 0xcc36, 0x4241, 0xcc36, 0x21, 0 - .dw 0x4243, 0xcc36, 0x424f, 0xcc36, 0x21, 0 - .dw 0x4251, 0xcc36, 0x4251, 0xcc36, 0x21, 0 - .dw 0x4253, 0xcc36, 0x427f, 0xcc36, 0x21, 0 - .dw 0x4281, 0xcc36, 0x4281, 0xcc36, 0x21, 0 - .dw 0x4283, 0xcc36, 0x428f, 0xcc36, 0x21, 0 - .dw 0x4291, 0xcc36, 0x4291, 0xcc36, 0x21, 0 - .dw 0x4293, 0xcc36, 0x42bf, 0xcc36, 0x21, 0 - .dw 0x42c1, 0xcc36, 0x42c1, 0xcc36, 0x21, 0 - .dw 0x42c3, 0xcc36, 0x42cf, 0xcc36, 0x21, 0 - .dw 0x42d1, 0xcc36, 0x42d1, 0xcc36, 0x21, 0 - .dw 0x42d3, 0xcc36, 0x42ff, 0xcc36, 0x21, 0 - .dw 0x4301, 0xcc36, 0x4301, 0xcc36, 0x21, 0 - .dw 0x4303, 0xcc36, 0x430f, 0xcc36, 0x21, 0 - .dw 0x4311, 0xcc36, 0x4311, 0xcc36, 0x21, 0 - .dw 0x4313, 0xcc36, 0x433f, 0xcc36, 0x21, 0 - .dw 0x4341, 0xcc36, 0x4341, 0xcc36, 0x21, 0 - .dw 0x4343, 0xcc36, 0x434f, 0xcc36, 0x21, 0 - .dw 0x4351, 0xcc36, 0x4351, 0xcc36, 0x21, 0 - .dw 0x4353, 0xcc36, 0x437f, 0xcc36, 0x21, 0 - .dw 0x4381, 0xcc36, 0x4381, 0xcc36, 0x21, 0 - .dw 0x4383, 0xcc36, 0x438f, 0xcc36, 0x21, 0 - .dw 0x4391, 0xcc36, 0x4391, 0xcc36, 0x21, 0 - .dw 0x4393, 0xcc36, 0x43bf, 0xcc36, 0x21, 0 - .dw 0x43c1, 0xcc36, 0x43c1, 0xcc36, 0x21, 0 - .dw 0x43c3, 0xcc36, 0x43cf, 0xcc36, 0x21, 0 - .dw 0x43d1, 0xcc36, 0x43d1, 0xcc36, 0x21, 0 - .dw 0x43d3, 0xcc36, 0x43ff, 0xcc36, 0x21, 0 - .dw 0x4401, 0xcc36, 0x4401, 0xcc36, 0x21, 0 - .dw 0x4403, 0xcc36, 0x440f, 0xcc36, 0x21, 0 - .dw 0x4411, 0xcc36, 0x4411, 0xcc36, 0x21, 0 - .dw 0x4413, 0xcc36, 0x443f, 0xcc36, 0x21, 0 - .dw 0x4441, 0xcc36, 0x4441, 0xcc36, 0x21, 0 - .dw 0x4443, 0xcc36, 0x444f, 0xcc36, 0x21, 0 - .dw 0x4451, 0xcc36, 0x4451, 0xcc36, 0x21, 0 - .dw 0x4453, 0xcc36, 0x447f, 0xcc36, 0x21, 0 - .dw 0x4481, 0xcc36, 0x4481, 0xcc36, 0x21, 0 - .dw 0x4483, 0xcc36, 0x448f, 0xcc36, 0x21, 0 - .dw 0x4491, 0xcc36, 0x4491, 0xcc36, 0x21, 0 - .dw 0x4493, 0xcc36, 0x44bf, 0xcc36, 0x21, 0 - .dw 0x44c1, 0xcc36, 0x44c1, 0xcc36, 0x21, 0 - .dw 0x44c3, 0xcc36, 0x44cf, 0xcc36, 0x21, 0 - .dw 0x44d1, 0xcc36, 0x44d1, 0xcc36, 0x21, 0 - .dw 0x44d3, 0xcc36, 0x44ff, 0xcc36, 0x21, 0 - .dw 0x4501, 0xcc36, 0x4501, 0xcc36, 0x21, 0 - .dw 0x4503, 0xcc36, 0x450f, 0xcc36, 0x21, 0 - .dw 0x4511, 0xcc36, 0x4511, 0xcc36, 0x21, 0 - .dw 0x4513, 0xcc36, 0x453f, 0xcc36, 0x21, 0 - .dw 0x4541, 0xcc36, 0x4541, 0xcc36, 0x21, 0 - .dw 0x4543, 0xcc36, 0x454f, 0xcc36, 0x21, 0 - .dw 0x4551, 0xcc36, 0x4551, 0xcc36, 0x21, 0 - .dw 0x4553, 0xcc36, 0x457f, 0xcc36, 0x21, 0 - .dw 0x4581, 0xcc36, 0x4581, 0xcc36, 0x21, 0 - .dw 0x4583, 0xcc36, 0x458f, 0xcc36, 0x21, 0 - .dw 0x4591, 0xcc36, 0x4591, 0xcc36, 0x21, 0 - .dw 0x4593, 0xcc36, 0x45bf, 0xcc36, 0x21, 0 - .dw 0x45c1, 0xcc36, 0x45c1, 0xcc36, 0x21, 0 - .dw 0x45c3, 0xcc36, 0x45cf, 0xcc36, 0x21, 0 - .dw 0x45d1, 0xcc36, 0x45d1, 0xcc36, 0x21, 0 - .dw 0x45d3, 0xcc36, 0x45ff, 0xcc36, 0x21, 0 - .dw 0x4601, 0xcc36, 0x4601, 0xcc36, 0x21, 0 - .dw 0x4603, 0xcc36, 0x460f, 0xcc36, 0x21, 0 - .dw 0x4611, 0xcc36, 0x4611, 0xcc36, 0x21, 0 - .dw 0x4613, 0xcc36, 0x463f, 0xcc36, 0x21, 0 - .dw 0x4641, 0xcc36, 0x4641, 0xcc36, 0x21, 0 - .dw 0x4643, 0xcc36, 0x464f, 0xcc36, 0x21, 0 - .dw 0x4651, 0xcc36, 0x4651, 0xcc36, 0x21, 0 - .dw 0x4653, 0xcc36, 0x467f, 0xcc36, 0x21, 0 - .dw 0x4681, 0xcc36, 0x4681, 0xcc36, 0x21, 0 - .dw 0x4683, 0xcc36, 0x468f, 0xcc36, 0x21, 0 - .dw 0x4691, 0xcc36, 0x4691, 0xcc36, 0x21, 0 - .dw 0x4693, 0xcc36, 0x46bf, 0xcc36, 0x21, 0 - .dw 0x46c1, 0xcc36, 0x46c1, 0xcc36, 0x21, 0 - .dw 0x46c3, 0xcc36, 0x46cf, 0xcc36, 0x21, 0 - .dw 0x46d1, 0xcc36, 0x46d1, 0xcc36, 0x21, 0 - .dw 0x46d3, 0xcc36, 0x46ff, 0xcc36, 0x21, 0 - .dw 0x4701, 0xcc36, 0x4701, 0xcc36, 0x21, 0 - .dw 0x4703, 0xcc36, 0x470f, 0xcc36, 0x21, 0 - .dw 0x4711, 0xcc36, 0x4711, 0xcc36, 0x21, 0 - .dw 0x4713, 0xcc36, 0x473f, 0xcc36, 0x21, 0 - .dw 0x4741, 0xcc36, 0x4741, 0xcc36, 0x21, 0 - .dw 0x4743, 0xcc36, 0x474f, 0xcc36, 0x21, 0 - .dw 0x4751, 0xcc36, 0x4751, 0xcc36, 0x21, 0 - .dw 0x4753, 0xcc36, 0x477f, 0xcc36, 0x21, 0 - .dw 0x4781, 0xcc36, 0x4781, 0xcc36, 0x21, 0 - .dw 0x4783, 0xcc36, 0x478f, 0xcc36, 0x21, 0 - .dw 0x4791, 0xcc36, 0x4791, 0xcc36, 0x21, 0 - .dw 0x4793, 0xcc36, 0x47bf, 0xcc36, 0x21, 0 - .dw 0x47c1, 0xcc36, 0x47c1, 0xcc36, 0x21, 0 - .dw 0x47c3, 0xcc36, 0x47cf, 0xcc36, 0x21, 0 - .dw 0x47d1, 0xcc36, 0x47d1, 0xcc36, 0x21, 0 - .dw 0x47d3, 0xcc36, 0x47ff, 0xcc36, 0x21, 0 - .dw 0x4801, 0xcc36, 0x4801, 0xcc36, 0x21, 0 - .dw 0x4803, 0xcc36, 0x480f, 0xcc36, 0x21, 0 - .dw 0x4811, 0xcc36, 0x4811, 0xcc36, 0x21, 0 - .dw 0x4813, 0xcc36, 0x483f, 0xcc36, 0x21, 0 - .dw 0x4841, 0xcc36, 0x4841, 0xcc36, 0x21, 0 - .dw 0x4843, 0xcc36, 0x484f, 0xcc36, 0x21, 0 - .dw 0x4851, 0xcc36, 0x4851, 0xcc36, 0x21, 0 - .dw 0x4853, 0xcc36, 0x487f, 0xcc36, 0x21, 0 - .dw 0x4881, 0xcc36, 0x4881, 0xcc36, 0x21, 0 - .dw 0x4883, 0xcc36, 0x488f, 0xcc36, 0x21, 0 - .dw 0x4891, 0xcc36, 0x4891, 0xcc36, 0x21, 0 - .dw 0x4893, 0xcc36, 0x48bf, 0xcc36, 0x21, 0 - .dw 0x48c1, 0xcc36, 0x48c1, 0xcc36, 0x21, 0 - .dw 0x48c3, 0xcc36, 0x48cf, 0xcc36, 0x21, 0 - .dw 0x48d1, 0xcc36, 0x48d1, 0xcc36, 0x21, 0 - .dw 0x48d3, 0xcc36, 0x48ff, 0xcc36, 0x21, 0 - .dw 0x4901, 0xcc36, 0x4901, 0xcc36, 0x21, 0 - .dw 0x4903, 0xcc36, 0x490f, 0xcc36, 0x21, 0 - .dw 0x4911, 0xcc36, 0x4911, 0xcc36, 0x21, 0 - .dw 0x4913, 0xcc36, 0x493f, 0xcc36, 0x21, 0 - .dw 0x4941, 0xcc36, 0x4941, 0xcc36, 0x21, 0 - .dw 0x4943, 0xcc36, 0x494f, 0xcc36, 0x21, 0 - .dw 0x4951, 0xcc36, 0x4951, 0xcc36, 0x21, 0 - .dw 0x4953, 0xcc36, 0x497f, 0xcc36, 0x21, 0 - .dw 0x4981, 0xcc36, 0x4981, 0xcc36, 0x21, 0 - .dw 0x4983, 0xcc36, 0x498f, 0xcc36, 0x21, 0 - .dw 0x4991, 0xcc36, 0x4991, 0xcc36, 0x21, 0 - .dw 0x4993, 0xcc36, 0x49bf, 0xcc36, 0x21, 0 - .dw 0x49c1, 0xcc36, 0x49c1, 0xcc36, 0x21, 0 - .dw 0x49c3, 0xcc36, 0x49cf, 0xcc36, 0x21, 0 - .dw 0x49d1, 0xcc36, 0x49d1, 0xcc36, 0x21, 0 - .dw 0x49d3, 0xcc36, 0x49ff, 0xcc36, 0x21, 0 - .dw 0x4a01, 0xcc36, 0x4a01, 0xcc36, 0x21, 0 - .dw 0x4a03, 0xcc36, 0x4a0f, 0xcc36, 0x21, 0 - .dw 0x4a11, 0xcc36, 0x4a11, 0xcc36, 0x21, 0 - .dw 0x4a13, 0xcc36, 0x4a3f, 0xcc36, 0x21, 0 - .dw 0x4a41, 0xcc36, 0x4a41, 0xcc36, 0x21, 0 - .dw 0x4a43, 0xcc36, 0x4a4f, 0xcc36, 0x21, 0 - .dw 0x4a51, 0xcc36, 0x4a51, 0xcc36, 0x21, 0 - .dw 0x4a53, 0xcc36, 0x4a7f, 0xcc36, 0x21, 0 - .dw 0x4a81, 0xcc36, 0x4a81, 0xcc36, 0x21, 0 - .dw 0x4a83, 0xcc36, 0x4a8f, 0xcc36, 0x21, 0 - .dw 0x4a91, 0xcc36, 0x4a91, 0xcc36, 0x21, 0 - .dw 0x4a93, 0xcc36, 0x4abf, 0xcc36, 0x21, 0 - .dw 0x4ac1, 0xcc36, 0x4ac1, 0xcc36, 0x21, 0 - .dw 0x4ac3, 0xcc36, 0x4acf, 0xcc36, 0x21, 0 - .dw 0x4ad1, 0xcc36, 0x4ad1, 0xcc36, 0x21, 0 - .dw 0x4ad3, 0xcc36, 0x4aff, 0xcc36, 0x21, 0 - .dw 0x4b01, 0xcc36, 0x4b01, 0xcc36, 0x21, 0 - .dw 0x4b03, 0xcc36, 0x4b0f, 0xcc36, 0x21, 0 - .dw 0x4b11, 0xcc36, 0x4b11, 0xcc36, 0x21, 0 - .dw 0x4b13, 0xcc36, 0x4b3f, 0xcc36, 0x21, 0 - .dw 0x4b41, 0xcc36, 0x4b41, 0xcc36, 0x21, 0 - .dw 0x4b43, 0xcc36, 0x4b4f, 0xcc36, 0x21, 0 - .dw 0x4b51, 0xcc36, 0x4b51, 0xcc36, 0x21, 0 - .dw 0x4b53, 0xcc36, 0x4b7f, 0xcc36, 0x21, 0 - .dw 0x4b81, 0xcc36, 0x4b81, 0xcc36, 0x21, 0 - .dw 0x4b83, 0xcc36, 0x4b8f, 0xcc36, 0x21, 0 - .dw 0x4b91, 0xcc36, 0x4b91, 0xcc36, 0x21, 0 - .dw 0x4b93, 0xcc36, 0x4bbf, 0xcc36, 0x21, 0 - .dw 0x4bc1, 0xcc36, 0x4bc1, 0xcc36, 0x21, 0 - .dw 0x4bc3, 0xcc36, 0x4bcf, 0xcc36, 0x21, 0 - .dw 0x4bd1, 0xcc36, 0x4bd1, 0xcc36, 0x21, 0 - .dw 0x4bd3, 0xcc36, 0x4bff, 0xcc36, 0x21, 0 - .dw 0x4c01, 0xcc36, 0x4c01, 0xcc36, 0x21, 0 - .dw 0x4c03, 0xcc36, 0x4c0f, 0xcc36, 0x21, 0 - .dw 0x4c11, 0xcc36, 0x4c11, 0xcc36, 0x21, 0 - .dw 0x4c13, 0xcc36, 0x4c3f, 0xcc36, 0x21, 0 - .dw 0x4c41, 0xcc36, 0x4c41, 0xcc36, 0x21, 0 - .dw 0x4c43, 0xcc36, 0x4c4f, 0xcc36, 0x21, 0 - .dw 0x4c51, 0xcc36, 0x4c51, 0xcc36, 0x21, 0 - .dw 0x4c53, 0xcc36, 0x4c7f, 0xcc36, 0x21, 0 - .dw 0x4c81, 0xcc36, 0x4c81, 0xcc36, 0x21, 0 - .dw 0x4c83, 0xcc36, 0x4c8f, 0xcc36, 0x21, 0 - .dw 0x4c91, 0xcc36, 0x4c91, 0xcc36, 0x21, 0 - .dw 0x4c93, 0xcc36, 0x4cbf, 0xcc36, 0x21, 0 - .dw 0x4cc1, 0xcc36, 0x4cc1, 0xcc36, 0x21, 0 - .dw 0x4cc3, 0xcc36, 0x4ccf, 0xcc36, 0x21, 0 - .dw 0x4cd1, 0xcc36, 0x4cd1, 0xcc36, 0x21, 0 - .dw 0x4cd3, 0xcc36, 0x4cff, 0xcc36, 0x21, 0 - .dw 0x4d01, 0xcc36, 0x4d01, 0xcc36, 0x21, 0 - .dw 0x4d03, 0xcc36, 0x4d0f, 0xcc36, 0x21, 0 - .dw 0x4d11, 0xcc36, 0x4d11, 0xcc36, 0x21, 0 - .dw 0x4d13, 0xcc36, 0x4d3f, 0xcc36, 0x21, 0 - .dw 0x4d41, 0xcc36, 0x4d41, 0xcc36, 0x21, 0 - .dw 0x4d43, 0xcc36, 0x4d4f, 0xcc36, 0x21, 0 - .dw 0x4d51, 0xcc36, 0x4d51, 0xcc36, 0x21, 0 - .dw 0x4d53, 0xcc36, 0x4d7f, 0xcc36, 0x21, 0 - .dw 0x4d81, 0xcc36, 0x4d81, 0xcc36, 0x21, 0 - .dw 0x4d83, 0xcc36, 0x4d8f, 0xcc36, 0x21, 0 - .dw 0x4d91, 0xcc36, 0x4d91, 0xcc36, 0x21, 0 - .dw 0x4d93, 0xcc36, 0x4dbf, 0xcc36, 0x21, 0 - .dw 0x4dc1, 0xcc36, 0x4dc1, 0xcc36, 0x21, 0 - .dw 0x4dc3, 0xcc36, 0x4dcf, 0xcc36, 0x21, 0 - .dw 0x4dd1, 0xcc36, 0x4dd1, 0xcc36, 0x21, 0 - .dw 0x4dd3, 0xcc36, 0x4dff, 0xcc36, 0x21, 0 - .dw 0x4e01, 0xcc36, 0x4e01, 0xcc36, 0x21, 0 - .dw 0x4e03, 0xcc36, 0x4e0f, 0xcc36, 0x21, 0 - .dw 0x4e11, 0xcc36, 0x4e11, 0xcc36, 0x21, 0 - .dw 0x4e13, 0xcc36, 0x4e3f, 0xcc36, 0x21, 0 - .dw 0x4e41, 0xcc36, 0x4e41, 0xcc36, 0x21, 0 - .dw 0x4e43, 0xcc36, 0x4e4f, 0xcc36, 0x21, 0 - .dw 0x4e51, 0xcc36, 0x4e51, 0xcc36, 0x21, 0 - .dw 0x4e53, 0xcc36, 0x4e7f, 0xcc36, 0x21, 0 - .dw 0x4e81, 0xcc36, 0x4e81, 0xcc36, 0x21, 0 - .dw 0x4e83, 0xcc36, 0x4e8f, 0xcc36, 0x21, 0 - .dw 0x4e91, 0xcc36, 0x4e91, 0xcc36, 0x21, 0 - .dw 0x4e93, 0xcc36, 0x4ebf, 0xcc36, 0x21, 0 - .dw 0x4ec1, 0xcc36, 0x4ec1, 0xcc36, 0x21, 0 - .dw 0x4ec3, 0xcc36, 0x4ecf, 0xcc36, 0x21, 0 - .dw 0x4ed1, 0xcc36, 0x4ed1, 0xcc36, 0x21, 0 - .dw 0x4ed3, 0xcc36, 0x4eff, 0xcc36, 0x21, 0 - .dw 0x4f01, 0xcc36, 0x4f01, 0xcc36, 0x21, 0 - .dw 0x4f03, 0xcc36, 0x4f0f, 0xcc36, 0x21, 0 - .dw 0x4f11, 0xcc36, 0x4f11, 0xcc36, 0x21, 0 - .dw 0x4f13, 0xcc36, 0x4f3f, 0xcc36, 0x21, 0 - .dw 0x4f41, 0xcc36, 0x4f41, 0xcc36, 0x21, 0 - .dw 0x4f43, 0xcc36, 0x4f4f, 0xcc36, 0x21, 0 - .dw 0x4f51, 0xcc36, 0x4f51, 0xcc36, 0x21, 0 - .dw 0x4f53, 0xcc36, 0x4f7f, 0xcc36, 0x21, 0 - .dw 0x4f81, 0xcc36, 0x4f81, 0xcc36, 0x21, 0 - .dw 0x4f83, 0xcc36, 0x4f8f, 0xcc36, 0x21, 0 - .dw 0x4f91, 0xcc36, 0x4f91, 0xcc36, 0x21, 0 - .dw 0x4f93, 0xcc36, 0x4fbf, 0xcc36, 0x21, 0 - .dw 0x4fc1, 0xcc36, 0x4fc1, 0xcc36, 0x21, 0 - .dw 0x4fc3, 0xcc36, 0x4fcf, 0xcc36, 0x21, 0 - .dw 0x4fd1, 0xcc36, 0x4fd1, 0xcc36, 0x21, 0 - .dw 0x4fd3, 0xcc36, 0x5fff, 0xcc36, 0x21, 0 - .dw 0x6001, 0xcc36, 0x6001, 0xcc36, 0x21, 0 - .dw 0x6003, 0xcc36, 0x600f, 0xcc36, 0x21, 0 - .dw 0x6011, 0xcc36, 0x6011, 0xcc36, 0x21, 0 - .dw 0x6013, 0xcc36, 0x603f, 0xcc36, 0x21, 0 - .dw 0x6041, 0xcc36, 0x6041, 0xcc36, 0x21, 0 - .dw 0x6043, 0xcc36, 0x604f, 0xcc36, 0x21, 0 - .dw 0x6051, 0xcc36, 0x6051, 0xcc36, 0x21, 0 - .dw 0x6053, 0xcc36, 0x607f, 0xcc36, 0x21, 0 - .dw 0x6081, 0xcc36, 0x6081, 0xcc36, 0x21, 0 - .dw 0x6083, 0xcc36, 0x608f, 0xcc36, 0x21, 0 - .dw 0x6091, 0xcc36, 0x6091, 0xcc36, 0x21, 0 - .dw 0x6093, 0xcc36, 0x60bf, 0xcc36, 0x21, 0 - .dw 0x60c1, 0xcc36, 0x60c1, 0xcc36, 0x21, 0 - .dw 0x60c3, 0xcc36, 0x60cf, 0xcc36, 0x21, 0 - .dw 0x60d1, 0xcc36, 0x60d1, 0xcc36, 0x21, 0 - .dw 0x60d3, 0xcc36, 0x60ff, 0xcc36, 0x21, 0 - .dw 0x6101, 0xcc36, 0x6101, 0xcc36, 0x21, 0 - .dw 0x6103, 0xcc36, 0x610f, 0xcc36, 0x21, 0 - .dw 0x6111, 0xcc36, 0x6111, 0xcc36, 0x21, 0 - .dw 0x6113, 0xcc36, 0x613f, 0xcc36, 0x21, 0 - .dw 0x6141, 0xcc36, 0x6141, 0xcc36, 0x21, 0 - .dw 0x6143, 0xcc36, 0x614f, 0xcc36, 0x21, 0 - .dw 0x6151, 0xcc36, 0x6151, 0xcc36, 0x21, 0 - .dw 0x6153, 0xcc36, 0x617f, 0xcc36, 0x21, 0 - .dw 0x6181, 0xcc36, 0x6181, 0xcc36, 0x21, 0 - .dw 0x6183, 0xcc36, 0x618f, 0xcc36, 0x21, 0 - .dw 0x6191, 0xcc36, 0x6191, 0xcc36, 0x21, 0 - .dw 0x6193, 0xcc36, 0x61bf, 0xcc36, 0x21, 0 - .dw 0x61c1, 0xcc36, 0x61c1, 0xcc36, 0x21, 0 - .dw 0x61c3, 0xcc36, 0x61cf, 0xcc36, 0x21, 0 - .dw 0x61d1, 0xcc36, 0x61d1, 0xcc36, 0x21, 0 - .dw 0x61d3, 0xcc36, 0x61ff, 0xcc36, 0x21, 0 - .dw 0x6201, 0xcc36, 0x6201, 0xcc36, 0x21, 0 - .dw 0x6203, 0xcc36, 0x620f, 0xcc36, 0x21, 0 - .dw 0x6211, 0xcc36, 0x6211, 0xcc36, 0x21, 0 - .dw 0x6213, 0xcc36, 0x623f, 0xcc36, 0x21, 0 - .dw 0x6241, 0xcc36, 0x6241, 0xcc36, 0x21, 0 - .dw 0x6243, 0xcc36, 0x624f, 0xcc36, 0x21, 0 - .dw 0x6251, 0xcc36, 0x6251, 0xcc36, 0x21, 0 - .dw 0x6253, 0xcc36, 0x627f, 0xcc36, 0x21, 0 - .dw 0x6281, 0xcc36, 0x6281, 0xcc36, 0x21, 0 - .dw 0x6283, 0xcc36, 0x628f, 0xcc36, 0x21, 0 - .dw 0x6291, 0xcc36, 0x6291, 0xcc36, 0x21, 0 - .dw 0x6293, 0xcc36, 0x62bf, 0xcc36, 0x21, 0 - .dw 0x62c1, 0xcc36, 0x62c1, 0xcc36, 0x21, 0 - .dw 0x62c3, 0xcc36, 0x62cf, 0xcc36, 0x21, 0 - .dw 0x62d1, 0xcc36, 0x62d1, 0xcc36, 0x21, 0 - .dw 0x62d3, 0xcc36, 0x62ff, 0xcc36, 0x21, 0 - .dw 0x6301, 0xcc36, 0x6301, 0xcc36, 0x21, 0 - .dw 0x6303, 0xcc36, 0x630f, 0xcc36, 0x21, 0 - .dw 0x6311, 0xcc36, 0x6311, 0xcc36, 0x21, 0 - .dw 0x6313, 0xcc36, 0x633f, 0xcc36, 0x21, 0 - .dw 0x6341, 0xcc36, 0x6341, 0xcc36, 0x21, 0 - .dw 0x6343, 0xcc36, 0x634f, 0xcc36, 0x21, 0 - .dw 0x6351, 0xcc36, 0x6351, 0xcc36, 0x21, 0 - .dw 0x6353, 0xcc36, 0x637f, 0xcc36, 0x21, 0 - .dw 0x6381, 0xcc36, 0x6381, 0xcc36, 0x21, 0 - .dw 0x6383, 0xcc36, 0x638f, 0xcc36, 0x21, 0 - .dw 0x6391, 0xcc36, 0x6391, 0xcc36, 0x21, 0 - .dw 0x6393, 0xcc36, 0x63bf, 0xcc36, 0x21, 0 - .dw 0x63c1, 0xcc36, 0x63c1, 0xcc36, 0x21, 0 - .dw 0x63c3, 0xcc36, 0x63cf, 0xcc36, 0x21, 0 - .dw 0x63d1, 0xcc36, 0x63d1, 0xcc36, 0x21, 0 - .dw 0x63d3, 0xcc36, 0x63ff, 0xcc36, 0x21, 0 - .dw 0x6401, 0xcc36, 0x6401, 0xcc36, 0x21, 0 - .dw 0x6403, 0xcc36, 0x640f, 0xcc36, 0x21, 0 - .dw 0x6411, 0xcc36, 0x6411, 0xcc36, 0x21, 0 - .dw 0x6413, 0xcc36, 0x643f, 0xcc36, 0x21, 0 - .dw 0x6441, 0xcc36, 0x6441, 0xcc36, 0x21, 0 - .dw 0x6443, 0xcc36, 0x644f, 0xcc36, 0x21, 0 - .dw 0x6451, 0xcc36, 0x6451, 0xcc36, 0x21, 0 - .dw 0x6453, 0xcc36, 0x647f, 0xcc36, 0x21, 0 - .dw 0x6481, 0xcc36, 0x6481, 0xcc36, 0x21, 0 - .dw 0x6483, 0xcc36, 0x648f, 0xcc36, 0x21, 0 - .dw 0x6491, 0xcc36, 0x6491, 0xcc36, 0x21, 0 - .dw 0x6493, 0xcc36, 0x64bf, 0xcc36, 0x21, 0 - .dw 0x64c1, 0xcc36, 0x64c1, 0xcc36, 0x21, 0 - .dw 0x64c3, 0xcc36, 0x64cf, 0xcc36, 0x21, 0 - .dw 0x64d1, 0xcc36, 0x64d1, 0xcc36, 0x21, 0 - .dw 0x64d3, 0xcc36, 0x64ff, 0xcc36, 0x21, 0 - .dw 0x6501, 0xcc36, 0x6501, 0xcc36, 0x21, 0 - .dw 0x6503, 0xcc36, 0x650f, 0xcc36, 0x21, 0 - .dw 0x6511, 0xcc36, 0x6511, 0xcc36, 0x21, 0 - .dw 0x6513, 0xcc36, 0x653f, 0xcc36, 0x21, 0 - .dw 0x6541, 0xcc36, 0x6541, 0xcc36, 0x21, 0 - .dw 0x6543, 0xcc36, 0x654f, 0xcc36, 0x21, 0 - .dw 0x6551, 0xcc36, 0x6551, 0xcc36, 0x21, 0 - .dw 0x6553, 0xcc36, 0x657f, 0xcc36, 0x21, 0 - .dw 0x6581, 0xcc36, 0x6581, 0xcc36, 0x21, 0 - .dw 0x6583, 0xcc36, 0x658f, 0xcc36, 0x21, 0 - .dw 0x6591, 0xcc36, 0x6591, 0xcc36, 0x21, 0 - .dw 0x6593, 0xcc36, 0x65bf, 0xcc36, 0x21, 0 - .dw 0x65c1, 0xcc36, 0x65c1, 0xcc36, 0x21, 0 - .dw 0x65c3, 0xcc36, 0x65cf, 0xcc36, 0x21, 0 - .dw 0x65d1, 0xcc36, 0x65d1, 0xcc36, 0x21, 0 - .dw 0x65d3, 0xcc36, 0x65ff, 0xcc36, 0x21, 0 - .dw 0x6601, 0xcc36, 0x6601, 0xcc36, 0x21, 0 - .dw 0x6603, 0xcc36, 0x660f, 0xcc36, 0x21, 0 - .dw 0x6611, 0xcc36, 0x6611, 0xcc36, 0x21, 0 - .dw 0x6613, 0xcc36, 0x663f, 0xcc36, 0x21, 0 - .dw 0x6641, 0xcc36, 0x6641, 0xcc36, 0x21, 0 - .dw 0x6643, 0xcc36, 0x664f, 0xcc36, 0x21, 0 - .dw 0x6651, 0xcc36, 0x6651, 0xcc36, 0x21, 0 - .dw 0x6653, 0xcc36, 0x667f, 0xcc36, 0x21, 0 - .dw 0x6681, 0xcc36, 0x6681, 0xcc36, 0x21, 0 - .dw 0x6683, 0xcc36, 0x668f, 0xcc36, 0x21, 0 - .dw 0x6691, 0xcc36, 0x6691, 0xcc36, 0x21, 0 - .dw 0x6693, 0xcc36, 0x66bf, 0xcc36, 0x21, 0 - .dw 0x66c1, 0xcc36, 0x66c1, 0xcc36, 0x21, 0 - .dw 0x66c3, 0xcc36, 0x66cf, 0xcc36, 0x21, 0 - .dw 0x66d1, 0xcc36, 0x66d1, 0xcc36, 0x21, 0 - .dw 0x66d3, 0xcc36, 0x66ff, 0xcc36, 0x21, 0 - .dw 0x6701, 0xcc36, 0x6701, 0xcc36, 0x21, 0 - .dw 0x6703, 0xcc36, 0x670f, 0xcc36, 0x21, 0 - .dw 0x6711, 0xcc36, 0x6711, 0xcc36, 0x21, 0 - .dw 0x6713, 0xcc36, 0x673f, 0xcc36, 0x21, 0 - .dw 0x6741, 0xcc36, 0x6741, 0xcc36, 0x21, 0 - .dw 0x6743, 0xcc36, 0x674f, 0xcc36, 0x21, 0 - .dw 0x6751, 0xcc36, 0x6751, 0xcc36, 0x21, 0 - .dw 0x6753, 0xcc36, 0x677f, 0xcc36, 0x21, 0 - .dw 0x6781, 0xcc36, 0x6781, 0xcc36, 0x21, 0 - .dw 0x6783, 0xcc36, 0x678f, 0xcc36, 0x21, 0 - .dw 0x6791, 0xcc36, 0x6791, 0xcc36, 0x21, 0 - .dw 0x6793, 0xcc36, 0x67bf, 0xcc36, 0x21, 0 - .dw 0x67c1, 0xcc36, 0x67c1, 0xcc36, 0x21, 0 - .dw 0x67c3, 0xcc36, 0x67cf, 0xcc36, 0x21, 0 - .dw 0x67d1, 0xcc36, 0x67d1, 0xcc36, 0x21, 0 - .dw 0x67d3, 0xcc36, 0x67ff, 0xcc36, 0x21, 0 - .dw 0x6801, 0xcc36, 0x6801, 0xcc36, 0x21, 0 - .dw 0x6803, 0xcc36, 0x680f, 0xcc36, 0x21, 0 - .dw 0x6811, 0xcc36, 0x6811, 0xcc36, 0x21, 0 - .dw 0x6813, 0xcc36, 0x683f, 0xcc36, 0x21, 0 - .dw 0x6841, 0xcc36, 0x6841, 0xcc36, 0x21, 0 - .dw 0x6843, 0xcc36, 0x684f, 0xcc36, 0x21, 0 - .dw 0x6851, 0xcc36, 0x6851, 0xcc36, 0x21, 0 - .dw 0x6853, 0xcc36, 0x687f, 0xcc36, 0x21, 0 - .dw 0x6881, 0xcc36, 0x6881, 0xcc36, 0x21, 0 - .dw 0x6883, 0xcc36, 0x688f, 0xcc36, 0x21, 0 - .dw 0x6891, 0xcc36, 0x6891, 0xcc36, 0x21, 0 - .dw 0x6893, 0xcc36, 0x68bf, 0xcc36, 0x21, 0 - .dw 0x68c1, 0xcc36, 0x68c1, 0xcc36, 0x21, 0 - .dw 0x68c3, 0xcc36, 0x68cf, 0xcc36, 0x21, 0 - .dw 0x68d1, 0xcc36, 0x68d1, 0xcc36, 0x21, 0 - .dw 0x68d3, 0xcc36, 0x68ff, 0xcc36, 0x21, 0 - .dw 0x6901, 0xcc36, 0x6901, 0xcc36, 0x21, 0 - .dw 0x6903, 0xcc36, 0x690f, 0xcc36, 0x21, 0 - .dw 0x6911, 0xcc36, 0x6911, 0xcc36, 0x21, 0 - .dw 0x6913, 0xcc36, 0x693f, 0xcc36, 0x21, 0 - .dw 0x6941, 0xcc36, 0x6941, 0xcc36, 0x21, 0 - .dw 0x6943, 0xcc36, 0x694f, 0xcc36, 0x21, 0 - .dw 0x6951, 0xcc36, 0x6951, 0xcc36, 0x21, 0 - .dw 0x6953, 0xcc36, 0x697f, 0xcc36, 0x21, 0 - .dw 0x6981, 0xcc36, 0x6981, 0xcc36, 0x21, 0 - .dw 0x6983, 0xcc36, 0x698f, 0xcc36, 0x21, 0 - .dw 0x6991, 0xcc36, 0x6991, 0xcc36, 0x21, 0 - .dw 0x6993, 0xcc36, 0x69bf, 0xcc36, 0x21, 0 - .dw 0x69c1, 0xcc36, 0x69c1, 0xcc36, 0x21, 0 - .dw 0x69c3, 0xcc36, 0x69cf, 0xcc36, 0x21, 0 - .dw 0x69d1, 0xcc36, 0x69d1, 0xcc36, 0x21, 0 - .dw 0x69d3, 0xcc36, 0x69ff, 0xcc36, 0x21, 0 - .dw 0x6a01, 0xcc36, 0x6a01, 0xcc36, 0x21, 0 - .dw 0x6a03, 0xcc36, 0x6a0f, 0xcc36, 0x21, 0 - .dw 0x6a11, 0xcc36, 0x6a11, 0xcc36, 0x21, 0 - .dw 0x6a13, 0xcc36, 0x6a3f, 0xcc36, 0x21, 0 - .dw 0x6a41, 0xcc36, 0x6a41, 0xcc36, 0x21, 0 - .dw 0x6a43, 0xcc36, 0x6a4f, 0xcc36, 0x21, 0 - .dw 0x6a51, 0xcc36, 0x6a51, 0xcc36, 0x21, 0 - .dw 0x6a53, 0xcc36, 0x6a7f, 0xcc36, 0x21, 0 - .dw 0x6a81, 0xcc36, 0x6a81, 0xcc36, 0x21, 0 - .dw 0x6a83, 0xcc36, 0x6a8f, 0xcc36, 0x21, 0 - .dw 0x6a91, 0xcc36, 0x6a91, 0xcc36, 0x21, 0 - .dw 0x6a93, 0xcc36, 0x6abf, 0xcc36, 0x21, 0 - .dw 0x6ac1, 0xcc36, 0x6ac1, 0xcc36, 0x21, 0 - .dw 0x6ac3, 0xcc36, 0x6acf, 0xcc36, 0x21, 0 - .dw 0x6ad1, 0xcc36, 0x6ad1, 0xcc36, 0x21, 0 - .dw 0x6ad3, 0xcc36, 0x6aff, 0xcc36, 0x21, 0 - .dw 0x6b01, 0xcc36, 0x6b01, 0xcc36, 0x21, 0 - .dw 0x6b03, 0xcc36, 0x6b0f, 0xcc36, 0x21, 0 - .dw 0x6b11, 0xcc36, 0x6b11, 0xcc36, 0x21, 0 - .dw 0x6b13, 0xcc36, 0x6b3f, 0xcc36, 0x21, 0 - .dw 0x6b41, 0xcc36, 0x6b41, 0xcc36, 0x21, 0 - .dw 0x6b43, 0xcc36, 0x6b4f, 0xcc36, 0x21, 0 - .dw 0x6b51, 0xcc36, 0x6b51, 0xcc36, 0x21, 0 - .dw 0x6b53, 0xcc36, 0x6b7f, 0xcc36, 0x21, 0 - .dw 0x6b81, 0xcc36, 0x6b81, 0xcc36, 0x21, 0 - .dw 0x6b83, 0xcc36, 0x6b8f, 0xcc36, 0x21, 0 - .dw 0x6b91, 0xcc36, 0x6b91, 0xcc36, 0x21, 0 - .dw 0x6b93, 0xcc36, 0x6bbf, 0xcc36, 0x21, 0 - .dw 0x6bc1, 0xcc36, 0x6bc1, 0xcc36, 0x21, 0 - .dw 0x6bc3, 0xcc36, 0x6bcf, 0xcc36, 0x21, 0 - .dw 0x6bd1, 0xcc36, 0x6bd1, 0xcc36, 0x21, 0 - .dw 0x6bd3, 0xcc36, 0x6bff, 0xcc36, 0x21, 0 - .dw 0x6c01, 0xcc36, 0x6c01, 0xcc36, 0x21, 0 - .dw 0x6c03, 0xcc36, 0x6c0f, 0xcc36, 0x21, 0 - .dw 0x6c11, 0xcc36, 0x6c11, 0xcc36, 0x21, 0 - .dw 0x6c13, 0xcc36, 0x6c3f, 0xcc36, 0x21, 0 - .dw 0x6c41, 0xcc36, 0x6c41, 0xcc36, 0x21, 0 - .dw 0x6c43, 0xcc36, 0x6c4f, 0xcc36, 0x21, 0 - .dw 0x6c51, 0xcc36, 0x6c51, 0xcc36, 0x21, 0 - .dw 0x6c53, 0xcc36, 0x6c7f, 0xcc36, 0x21, 0 - .dw 0x6c81, 0xcc36, 0x6c81, 0xcc36, 0x21, 0 - .dw 0x6c83, 0xcc36, 0x6c8f, 0xcc36, 0x21, 0 - .dw 0x6c91, 0xcc36, 0x6c91, 0xcc36, 0x21, 0 - .dw 0x6c93, 0xcc36, 0x6cbf, 0xcc36, 0x21, 0 - .dw 0x6cc1, 0xcc36, 0x6cc1, 0xcc36, 0x21, 0 - .dw 0x6cc3, 0xcc36, 0x6ccf, 0xcc36, 0x21, 0 - .dw 0x6cd1, 0xcc36, 0x6cd1, 0xcc36, 0x21, 0 - .dw 0x6cd3, 0xcc36, 0x6cff, 0xcc36, 0x21, 0 - .dw 0x6d01, 0xcc36, 0x6d01, 0xcc36, 0x21, 0 - .dw 0x6d03, 0xcc36, 0x6d0f, 0xcc36, 0x21, 0 - .dw 0x6d11, 0xcc36, 0x6d11, 0xcc36, 0x21, 0 - .dw 0x6d13, 0xcc36, 0x6d3f, 0xcc36, 0x21, 0 - .dw 0x6d41, 0xcc36, 0x6d41, 0xcc36, 0x21, 0 - .dw 0x6d43, 0xcc36, 0x6d4f, 0xcc36, 0x21, 0 - .dw 0x6d51, 0xcc36, 0x6d51, 0xcc36, 0x21, 0 - .dw 0x6d53, 0xcc36, 0x6d7f, 0xcc36, 0x21, 0 - .dw 0x6d81, 0xcc36, 0x6d81, 0xcc36, 0x21, 0 - .dw 0x6d83, 0xcc36, 0x6d8f, 0xcc36, 0x21, 0 - .dw 0x6d91, 0xcc36, 0x6d91, 0xcc36, 0x21, 0 - .dw 0x6d93, 0xcc36, 0x6dbf, 0xcc36, 0x21, 0 - .dw 0x6dc1, 0xcc36, 0x6dc1, 0xcc36, 0x21, 0 - .dw 0x6dc3, 0xcc36, 0x6dcf, 0xcc36, 0x21, 0 - .dw 0x6dd1, 0xcc36, 0x6dd1, 0xcc36, 0x21, 0 - .dw 0x6dd3, 0xcc36, 0x6dff, 0xcc36, 0x21, 0 - .dw 0x6e01, 0xcc36, 0x6e01, 0xcc36, 0x21, 0 - .dw 0x6e03, 0xcc36, 0x6e0f, 0xcc36, 0x21, 0 - .dw 0x6e11, 0xcc36, 0x6e11, 0xcc36, 0x21, 0 - .dw 0x6e13, 0xcc36, 0x6e3f, 0xcc36, 0x21, 0 - .dw 0x6e41, 0xcc36, 0x6e41, 0xcc36, 0x21, 0 - .dw 0x6e43, 0xcc36, 0x6e4f, 0xcc36, 0x21, 0 - .dw 0x6e51, 0xcc36, 0x6e51, 0xcc36, 0x21, 0 - .dw 0x6e53, 0xcc36, 0x6e7f, 0xcc36, 0x21, 0 - .dw 0x6e81, 0xcc36, 0x6e81, 0xcc36, 0x21, 0 - .dw 0x6e83, 0xcc36, 0x6e8f, 0xcc36, 0x21, 0 - .dw 0x6e91, 0xcc36, 0x6e91, 0xcc36, 0x21, 0 - .dw 0x6e93, 0xcc36, 0x6ebf, 0xcc36, 0x21, 0 - .dw 0x6ec1, 0xcc36, 0x6ec1, 0xcc36, 0x21, 0 - .dw 0x6ec3, 0xcc36, 0x6ecf, 0xcc36, 0x21, 0 - .dw 0x6ed1, 0xcc36, 0x6ed1, 0xcc36, 0x21, 0 - .dw 0x6ed3, 0xcc36, 0x6eff, 0xcc36, 0x21, 0 - .dw 0x6f01, 0xcc36, 0x6f01, 0xcc36, 0x21, 0 - .dw 0x6f03, 0xcc36, 0x6f0f, 0xcc36, 0x21, 0 - .dw 0x6f11, 0xcc36, 0x6f11, 0xcc36, 0x21, 0 - .dw 0x6f13, 0xcc36, 0x6f3f, 0xcc36, 0x21, 0 - .dw 0x6f41, 0xcc36, 0x6f41, 0xcc36, 0x21, 0 - .dw 0x6f43, 0xcc36, 0x6f4f, 0xcc36, 0x21, 0 - .dw 0x6f51, 0xcc36, 0x6f51, 0xcc36, 0x21, 0 - .dw 0x6f53, 0xcc36, 0x6f7f, 0xcc36, 0x21, 0 - .dw 0x6f81, 0xcc36, 0x6f81, 0xcc36, 0x21, 0 - .dw 0x6f83, 0xcc36, 0x6f8f, 0xcc36, 0x21, 0 - .dw 0x6f91, 0xcc36, 0x6f91, 0xcc36, 0x21, 0 - .dw 0x6f93, 0xcc36, 0x6fbf, 0xcc36, 0x21, 0 - .dw 0x6fc1, 0xcc36, 0x6fc1, 0xcc36, 0x21, 0 - .dw 0x6fc3, 0xcc36, 0x6fcf, 0xcc36, 0x21, 0 - .dw 0x6fd1, 0xcc36, 0x6fd1, 0xcc36, 0x21, 0 - .dw 0x6fd3, 0xcc36, 0xffff, 0xcc36, 0x21, 0 - .dw 0x0001, 0xcc37, 0x0001, 0xcc37, 0x21, 0 - .dw 0x0003, 0xcc37, 0x000f, 0xcc37, 0x21, 0 - .dw 0x0011, 0xcc37, 0x0011, 0xcc37, 0x21, 0 - .dw 0x0013, 0xcc37, 0x003f, 0xcc37, 0x21, 0 - .dw 0x0041, 0xcc37, 0x0041, 0xcc37, 0x21, 0 - .dw 0x0043, 0xcc37, 0x004f, 0xcc37, 0x21, 0 - .dw 0x0051, 0xcc37, 0x0051, 0xcc37, 0x21, 0 - .dw 0x0053, 0xcc37, 0x007f, 0xcc37, 0x21, 0 - .dw 0x0081, 0xcc37, 0x0081, 0xcc37, 0x21, 0 - .dw 0x0083, 0xcc37, 0x008f, 0xcc37, 0x21, 0 - .dw 0x0091, 0xcc37, 0x0091, 0xcc37, 0x21, 0 - .dw 0x0093, 0xcc37, 0x00bf, 0xcc37, 0x21, 0 - .dw 0x00c1, 0xcc37, 0x00c1, 0xcc37, 0x21, 0 - .dw 0x00c3, 0xcc37, 0x00cf, 0xcc37, 0x21, 0 - .dw 0x00d1, 0xcc37, 0x00d1, 0xcc37, 0x21, 0 - .dw 0x00d3, 0xcc37, 0x00ff, 0xcc37, 0x21, 0 - .dw 0x0101, 0xcc37, 0x0101, 0xcc37, 0x21, 0 - .dw 0x0103, 0xcc37, 0x010f, 0xcc37, 0x21, 0 - .dw 0x0111, 0xcc37, 0x0111, 0xcc37, 0x21, 0 - .dw 0x0113, 0xcc37, 0x013f, 0xcc37, 0x21, 0 - .dw 0x0141, 0xcc37, 0x0141, 0xcc37, 0x21, 0 - .dw 0x0143, 0xcc37, 0x014f, 0xcc37, 0x21, 0 - .dw 0x0151, 0xcc37, 0x0151, 0xcc37, 0x21, 0 - .dw 0x0153, 0xcc37, 0x017f, 0xcc37, 0x21, 0 - .dw 0x0181, 0xcc37, 0x0181, 0xcc37, 0x21, 0 - .dw 0x0183, 0xcc37, 0x018f, 0xcc37, 0x21, 0 - .dw 0x0191, 0xcc37, 0x0191, 0xcc37, 0x21, 0 - .dw 0x0193, 0xcc37, 0x01bf, 0xcc37, 0x21, 0 - .dw 0x01c1, 0xcc37, 0x01c1, 0xcc37, 0x21, 0 - .dw 0x01c3, 0xcc37, 0x01cf, 0xcc37, 0x21, 0 - .dw 0x01d1, 0xcc37, 0x01d1, 0xcc37, 0x21, 0 - .dw 0x01d3, 0xcc37, 0x01ff, 0xcc37, 0x21, 0 - .dw 0x0201, 0xcc37, 0x0201, 0xcc37, 0x21, 0 - .dw 0x0203, 0xcc37, 0x020f, 0xcc37, 0x21, 0 - .dw 0x0211, 0xcc37, 0x0211, 0xcc37, 0x21, 0 - .dw 0x0213, 0xcc37, 0x023f, 0xcc37, 0x21, 0 - .dw 0x0241, 0xcc37, 0x0241, 0xcc37, 0x21, 0 - .dw 0x0243, 0xcc37, 0x024f, 0xcc37, 0x21, 0 - .dw 0x0251, 0xcc37, 0x0251, 0xcc37, 0x21, 0 - .dw 0x0253, 0xcc37, 0x027f, 0xcc37, 0x21, 0 - .dw 0x0281, 0xcc37, 0x0281, 0xcc37, 0x21, 0 - .dw 0x0283, 0xcc37, 0x028f, 0xcc37, 0x21, 0 - .dw 0x0291, 0xcc37, 0x0291, 0xcc37, 0x21, 0 - .dw 0x0293, 0xcc37, 0x02bf, 0xcc37, 0x21, 0 - .dw 0x02c1, 0xcc37, 0x02c1, 0xcc37, 0x21, 0 - .dw 0x02c3, 0xcc37, 0x02cf, 0xcc37, 0x21, 0 - .dw 0x02d1, 0xcc37, 0x02d1, 0xcc37, 0x21, 0 - .dw 0x02d3, 0xcc37, 0x02ff, 0xcc37, 0x21, 0 - .dw 0x0301, 0xcc37, 0x0301, 0xcc37, 0x21, 0 - .dw 0x0303, 0xcc37, 0x030f, 0xcc37, 0x21, 0 - .dw 0x0311, 0xcc37, 0x0311, 0xcc37, 0x21, 0 - .dw 0x0313, 0xcc37, 0x033f, 0xcc37, 0x21, 0 - .dw 0x0341, 0xcc37, 0x0341, 0xcc37, 0x21, 0 - .dw 0x0343, 0xcc37, 0x034f, 0xcc37, 0x21, 0 - .dw 0x0351, 0xcc37, 0x0351, 0xcc37, 0x21, 0 - .dw 0x0353, 0xcc37, 0x037f, 0xcc37, 0x21, 0 - .dw 0x0381, 0xcc37, 0x0381, 0xcc37, 0x21, 0 - .dw 0x0383, 0xcc37, 0x038f, 0xcc37, 0x21, 0 - .dw 0x0391, 0xcc37, 0x0391, 0xcc37, 0x21, 0 - .dw 0x0393, 0xcc37, 0x03bf, 0xcc37, 0x21, 0 - .dw 0x03c1, 0xcc37, 0x03c1, 0xcc37, 0x21, 0 - .dw 0x03c3, 0xcc37, 0x03cf, 0xcc37, 0x21, 0 - .dw 0x03d1, 0xcc37, 0x03d1, 0xcc37, 0x21, 0 - .dw 0x03d3, 0xcc37, 0x03ff, 0xcc37, 0x21, 0 - .dw 0x0401, 0xcc37, 0x0401, 0xcc37, 0x21, 0 - .dw 0x0403, 0xcc37, 0x040f, 0xcc37, 0x21, 0 - .dw 0x0411, 0xcc37, 0x0411, 0xcc37, 0x21, 0 - .dw 0x0413, 0xcc37, 0x043f, 0xcc37, 0x21, 0 - .dw 0x0441, 0xcc37, 0x0441, 0xcc37, 0x21, 0 - .dw 0x0443, 0xcc37, 0x044f, 0xcc37, 0x21, 0 - .dw 0x0451, 0xcc37, 0x0451, 0xcc37, 0x21, 0 - .dw 0x0453, 0xcc37, 0x047f, 0xcc37, 0x21, 0 - .dw 0x0481, 0xcc37, 0x0481, 0xcc37, 0x21, 0 - .dw 0x0483, 0xcc37, 0x048f, 0xcc37, 0x21, 0 - .dw 0x0491, 0xcc37, 0x0491, 0xcc37, 0x21, 0 - .dw 0x0493, 0xcc37, 0x04bf, 0xcc37, 0x21, 0 - .dw 0x04c1, 0xcc37, 0x04c1, 0xcc37, 0x21, 0 - .dw 0x04c3, 0xcc37, 0x04cf, 0xcc37, 0x21, 0 - .dw 0x04d1, 0xcc37, 0x04d1, 0xcc37, 0x21, 0 - .dw 0x04d3, 0xcc37, 0x04ff, 0xcc37, 0x21, 0 - .dw 0x0501, 0xcc37, 0x0501, 0xcc37, 0x21, 0 - .dw 0x0503, 0xcc37, 0x050f, 0xcc37, 0x21, 0 - .dw 0x0511, 0xcc37, 0x0511, 0xcc37, 0x21, 0 - .dw 0x0513, 0xcc37, 0x053f, 0xcc37, 0x21, 0 - .dw 0x0541, 0xcc37, 0x0541, 0xcc37, 0x21, 0 - .dw 0x0543, 0xcc37, 0x054f, 0xcc37, 0x21, 0 - .dw 0x0551, 0xcc37, 0x0551, 0xcc37, 0x21, 0 - .dw 0x0553, 0xcc37, 0x057f, 0xcc37, 0x21, 0 - .dw 0x0581, 0xcc37, 0x0581, 0xcc37, 0x21, 0 - .dw 0x0583, 0xcc37, 0x058f, 0xcc37, 0x21, 0 - .dw 0x0591, 0xcc37, 0x0591, 0xcc37, 0x21, 0 - .dw 0x0593, 0xcc37, 0x05bf, 0xcc37, 0x21, 0 - .dw 0x05c1, 0xcc37, 0x05c1, 0xcc37, 0x21, 0 - .dw 0x05c3, 0xcc37, 0x05cf, 0xcc37, 0x21, 0 - .dw 0x05d1, 0xcc37, 0x05d1, 0xcc37, 0x21, 0 - .dw 0x05d3, 0xcc37, 0x05ff, 0xcc37, 0x21, 0 - .dw 0x0601, 0xcc37, 0x0601, 0xcc37, 0x21, 0 - .dw 0x0603, 0xcc37, 0x060f, 0xcc37, 0x21, 0 - .dw 0x0611, 0xcc37, 0x0611, 0xcc37, 0x21, 0 - .dw 0x0613, 0xcc37, 0x063f, 0xcc37, 0x21, 0 - .dw 0x0641, 0xcc37, 0x0641, 0xcc37, 0x21, 0 - .dw 0x0643, 0xcc37, 0x064f, 0xcc37, 0x21, 0 - .dw 0x0651, 0xcc37, 0x0651, 0xcc37, 0x21, 0 - .dw 0x0653, 0xcc37, 0x067f, 0xcc37, 0x21, 0 - .dw 0x0681, 0xcc37, 0x0681, 0xcc37, 0x21, 0 - .dw 0x0683, 0xcc37, 0x068f, 0xcc37, 0x21, 0 - .dw 0x0691, 0xcc37, 0x0691, 0xcc37, 0x21, 0 - .dw 0x0693, 0xcc37, 0x06bf, 0xcc37, 0x21, 0 - .dw 0x06c1, 0xcc37, 0x06c1, 0xcc37, 0x21, 0 - .dw 0x06c3, 0xcc37, 0x06cf, 0xcc37, 0x21, 0 - .dw 0x06d1, 0xcc37, 0x06d1, 0xcc37, 0x21, 0 - .dw 0x06d3, 0xcc37, 0x06ff, 0xcc37, 0x21, 0 - .dw 0x0701, 0xcc37, 0x0701, 0xcc37, 0x21, 0 - .dw 0x0703, 0xcc37, 0x070f, 0xcc37, 0x21, 0 - .dw 0x0711, 0xcc37, 0x0711, 0xcc37, 0x21, 0 - .dw 0x0713, 0xcc37, 0x073f, 0xcc37, 0x21, 0 - .dw 0x0741, 0xcc37, 0x0741, 0xcc37, 0x21, 0 - .dw 0x0743, 0xcc37, 0x074f, 0xcc37, 0x21, 0 - .dw 0x0751, 0xcc37, 0x0751, 0xcc37, 0x21, 0 - .dw 0x0753, 0xcc37, 0x077f, 0xcc37, 0x21, 0 - .dw 0x0781, 0xcc37, 0x0781, 0xcc37, 0x21, 0 - .dw 0x0783, 0xcc37, 0x078f, 0xcc37, 0x21, 0 - .dw 0x0791, 0xcc37, 0x0791, 0xcc37, 0x21, 0 - .dw 0x0793, 0xcc37, 0x07bf, 0xcc37, 0x21, 0 - .dw 0x07c1, 0xcc37, 0x07c1, 0xcc37, 0x21, 0 - .dw 0x07c3, 0xcc37, 0x07cf, 0xcc37, 0x21, 0 - .dw 0x07d1, 0xcc37, 0x07d1, 0xcc37, 0x21, 0 - .dw 0x07d3, 0xcc37, 0x07ff, 0xcc37, 0x21, 0 - .dw 0x0801, 0xcc37, 0x0801, 0xcc37, 0x21, 0 - .dw 0x0803, 0xcc37, 0x080f, 0xcc37, 0x21, 0 - .dw 0x0811, 0xcc37, 0x0811, 0xcc37, 0x21, 0 - .dw 0x0813, 0xcc37, 0x083f, 0xcc37, 0x21, 0 - .dw 0x0841, 0xcc37, 0x0841, 0xcc37, 0x21, 0 - .dw 0x0843, 0xcc37, 0x084f, 0xcc37, 0x21, 0 - .dw 0x0851, 0xcc37, 0x0851, 0xcc37, 0x21, 0 - .dw 0x0853, 0xcc37, 0x087f, 0xcc37, 0x21, 0 - .dw 0x0881, 0xcc37, 0x0881, 0xcc37, 0x21, 0 - .dw 0x0883, 0xcc37, 0x088f, 0xcc37, 0x21, 0 - .dw 0x0891, 0xcc37, 0x0891, 0xcc37, 0x21, 0 - .dw 0x0893, 0xcc37, 0x08bf, 0xcc37, 0x21, 0 - .dw 0x08c1, 0xcc37, 0x08c1, 0xcc37, 0x21, 0 - .dw 0x08c3, 0xcc37, 0x08cf, 0xcc37, 0x21, 0 - .dw 0x08d1, 0xcc37, 0x08d1, 0xcc37, 0x21, 0 - .dw 0x08d3, 0xcc37, 0x08ff, 0xcc37, 0x21, 0 - .dw 0x0901, 0xcc37, 0x0901, 0xcc37, 0x21, 0 - .dw 0x0903, 0xcc37, 0x090f, 0xcc37, 0x21, 0 - .dw 0x0911, 0xcc37, 0x0911, 0xcc37, 0x21, 0 - .dw 0x0913, 0xcc37, 0x093f, 0xcc37, 0x21, 0 - .dw 0x0941, 0xcc37, 0x0941, 0xcc37, 0x21, 0 - .dw 0x0943, 0xcc37, 0x094f, 0xcc37, 0x21, 0 - .dw 0x0951, 0xcc37, 0x0951, 0xcc37, 0x21, 0 - .dw 0x0953, 0xcc37, 0x097f, 0xcc37, 0x21, 0 - .dw 0x0981, 0xcc37, 0x0981, 0xcc37, 0x21, 0 - .dw 0x0983, 0xcc37, 0x098f, 0xcc37, 0x21, 0 - .dw 0x0991, 0xcc37, 0x0991, 0xcc37, 0x21, 0 - .dw 0x0993, 0xcc37, 0x09bf, 0xcc37, 0x21, 0 - .dw 0x09c1, 0xcc37, 0x09c1, 0xcc37, 0x21, 0 - .dw 0x09c3, 0xcc37, 0x09cf, 0xcc37, 0x21, 0 - .dw 0x09d1, 0xcc37, 0x09d1, 0xcc37, 0x21, 0 - .dw 0x09d3, 0xcc37, 0x09ff, 0xcc37, 0x21, 0 - .dw 0x0a01, 0xcc37, 0x0a01, 0xcc37, 0x21, 0 - .dw 0x0a03, 0xcc37, 0x0a0f, 0xcc37, 0x21, 0 - .dw 0x0a11, 0xcc37, 0x0a11, 0xcc37, 0x21, 0 - .dw 0x0a13, 0xcc37, 0x0a3f, 0xcc37, 0x21, 0 - .dw 0x0a41, 0xcc37, 0x0a41, 0xcc37, 0x21, 0 - .dw 0x0a43, 0xcc37, 0x0a4f, 0xcc37, 0x21, 0 - .dw 0x0a51, 0xcc37, 0x0a51, 0xcc37, 0x21, 0 - .dw 0x0a53, 0xcc37, 0x0a7f, 0xcc37, 0x21, 0 - .dw 0x0a81, 0xcc37, 0x0a81, 0xcc37, 0x21, 0 - .dw 0x0a83, 0xcc37, 0x0a8f, 0xcc37, 0x21, 0 - .dw 0x0a91, 0xcc37, 0x0a91, 0xcc37, 0x21, 0 - .dw 0x0a93, 0xcc37, 0x0abf, 0xcc37, 0x21, 0 - .dw 0x0ac1, 0xcc37, 0x0ac1, 0xcc37, 0x21, 0 - .dw 0x0ac3, 0xcc37, 0x0acf, 0xcc37, 0x21, 0 - .dw 0x0ad1, 0xcc37, 0x0ad1, 0xcc37, 0x21, 0 - .dw 0x0ad3, 0xcc37, 0x0aff, 0xcc37, 0x21, 0 - .dw 0x0b01, 0xcc37, 0x0b01, 0xcc37, 0x21, 0 - .dw 0x0b03, 0xcc37, 0x0b0f, 0xcc37, 0x21, 0 - .dw 0x0b11, 0xcc37, 0x0b11, 0xcc37, 0x21, 0 - .dw 0x0b13, 0xcc37, 0x0b3f, 0xcc37, 0x21, 0 - .dw 0x0b41, 0xcc37, 0x0b41, 0xcc37, 0x21, 0 - .dw 0x0b43, 0xcc37, 0x0b4f, 0xcc37, 0x21, 0 - .dw 0x0b51, 0xcc37, 0x0b51, 0xcc37, 0x21, 0 - .dw 0x0b53, 0xcc37, 0x0b7f, 0xcc37, 0x21, 0 - .dw 0x0b81, 0xcc37, 0x0b81, 0xcc37, 0x21, 0 - .dw 0x0b83, 0xcc37, 0x0b8f, 0xcc37, 0x21, 0 - .dw 0x0b91, 0xcc37, 0x0b91, 0xcc37, 0x21, 0 - .dw 0x0b93, 0xcc37, 0x0bbf, 0xcc37, 0x21, 0 - .dw 0x0bc1, 0xcc37, 0x0bc1, 0xcc37, 0x21, 0 - .dw 0x0bc3, 0xcc37, 0x0bcf, 0xcc37, 0x21, 0 - .dw 0x0bd1, 0xcc37, 0x0bd1, 0xcc37, 0x21, 0 - .dw 0x0bd3, 0xcc37, 0x0bff, 0xcc37, 0x21, 0 - .dw 0x0c01, 0xcc37, 0x0c01, 0xcc37, 0x21, 0 - .dw 0x0c03, 0xcc37, 0x0c0f, 0xcc37, 0x21, 0 - .dw 0x0c11, 0xcc37, 0x0c11, 0xcc37, 0x21, 0 - .dw 0x0c13, 0xcc37, 0x0c3f, 0xcc37, 0x21, 0 - .dw 0x0c41, 0xcc37, 0x0c41, 0xcc37, 0x21, 0 - .dw 0x0c43, 0xcc37, 0x0c4f, 0xcc37, 0x21, 0 - .dw 0x0c51, 0xcc37, 0x0c51, 0xcc37, 0x21, 0 - .dw 0x0c53, 0xcc37, 0x0c7f, 0xcc37, 0x21, 0 - .dw 0x0c81, 0xcc37, 0x0c81, 0xcc37, 0x21, 0 - .dw 0x0c83, 0xcc37, 0x0c8f, 0xcc37, 0x21, 0 - .dw 0x0c91, 0xcc37, 0x0c91, 0xcc37, 0x21, 0 - .dw 0x0c93, 0xcc37, 0x0cbf, 0xcc37, 0x21, 0 - .dw 0x0cc1, 0xcc37, 0x0cc1, 0xcc37, 0x21, 0 - .dw 0x0cc3, 0xcc37, 0x0ccf, 0xcc37, 0x21, 0 - .dw 0x0cd1, 0xcc37, 0x0cd1, 0xcc37, 0x21, 0 - .dw 0x0cd3, 0xcc37, 0x0cff, 0xcc37, 0x21, 0 - .dw 0x0d01, 0xcc37, 0x0d01, 0xcc37, 0x21, 0 - .dw 0x0d03, 0xcc37, 0x0d0f, 0xcc37, 0x21, 0 - .dw 0x0d11, 0xcc37, 0x0d11, 0xcc37, 0x21, 0 - .dw 0x0d13, 0xcc37, 0x0d3f, 0xcc37, 0x21, 0 - .dw 0x0d41, 0xcc37, 0x0d41, 0xcc37, 0x21, 0 - .dw 0x0d43, 0xcc37, 0x0d4f, 0xcc37, 0x21, 0 - .dw 0x0d51, 0xcc37, 0x0d51, 0xcc37, 0x21, 0 - .dw 0x0d53, 0xcc37, 0x0d7f, 0xcc37, 0x21, 0 - .dw 0x0d81, 0xcc37, 0x0d81, 0xcc37, 0x21, 0 - .dw 0x0d83, 0xcc37, 0x0d8f, 0xcc37, 0x21, 0 - .dw 0x0d91, 0xcc37, 0x0d91, 0xcc37, 0x21, 0 - .dw 0x0d93, 0xcc37, 0x0dbf, 0xcc37, 0x21, 0 - .dw 0x0dc1, 0xcc37, 0x0dc1, 0xcc37, 0x21, 0 - .dw 0x0dc3, 0xcc37, 0x0dcf, 0xcc37, 0x21, 0 - .dw 0x0dd1, 0xcc37, 0x0dd1, 0xcc37, 0x21, 0 - .dw 0x0dd3, 0xcc37, 0x0dff, 0xcc37, 0x21, 0 - .dw 0x0e01, 0xcc37, 0x0e01, 0xcc37, 0x21, 0 - .dw 0x0e03, 0xcc37, 0x0e0f, 0xcc37, 0x21, 0 - .dw 0x0e11, 0xcc37, 0x0e11, 0xcc37, 0x21, 0 - .dw 0x0e13, 0xcc37, 0x0e3f, 0xcc37, 0x21, 0 - .dw 0x0e41, 0xcc37, 0x0e41, 0xcc37, 0x21, 0 - .dw 0x0e43, 0xcc37, 0x0e4f, 0xcc37, 0x21, 0 - .dw 0x0e51, 0xcc37, 0x0e51, 0xcc37, 0x21, 0 - .dw 0x0e53, 0xcc37, 0x0e7f, 0xcc37, 0x21, 0 - .dw 0x0e81, 0xcc37, 0x0e81, 0xcc37, 0x21, 0 - .dw 0x0e83, 0xcc37, 0x0e8f, 0xcc37, 0x21, 0 - .dw 0x0e91, 0xcc37, 0x0e91, 0xcc37, 0x21, 0 - .dw 0x0e93, 0xcc37, 0x0ebf, 0xcc37, 0x21, 0 - .dw 0x0ec1, 0xcc37, 0x0ec1, 0xcc37, 0x21, 0 - .dw 0x0ec3, 0xcc37, 0x0ecf, 0xcc37, 0x21, 0 - .dw 0x0ed1, 0xcc37, 0x0ed1, 0xcc37, 0x21, 0 - .dw 0x0ed3, 0xcc37, 0x0eff, 0xcc37, 0x21, 0 - .dw 0x0f01, 0xcc37, 0x0f01, 0xcc37, 0x21, 0 - .dw 0x0f03, 0xcc37, 0x0f0f, 0xcc37, 0x21, 0 - .dw 0x0f11, 0xcc37, 0x0f11, 0xcc37, 0x21, 0 - .dw 0x0f13, 0xcc37, 0x0f3f, 0xcc37, 0x21, 0 - .dw 0x0f41, 0xcc37, 0x0f41, 0xcc37, 0x21, 0 - .dw 0x0f43, 0xcc37, 0x0f4f, 0xcc37, 0x21, 0 - .dw 0x0f51, 0xcc37, 0x0f51, 0xcc37, 0x21, 0 - .dw 0x0f53, 0xcc37, 0x0f7f, 0xcc37, 0x21, 0 - .dw 0x0f81, 0xcc37, 0x0f81, 0xcc37, 0x21, 0 - .dw 0x0f83, 0xcc37, 0x0f8f, 0xcc37, 0x21, 0 - .dw 0x0f91, 0xcc37, 0x0f91, 0xcc37, 0x21, 0 - .dw 0x0f93, 0xcc37, 0x0fbf, 0xcc37, 0x21, 0 - .dw 0x0fc1, 0xcc37, 0x0fc1, 0xcc37, 0x21, 0 - .dw 0x0fc3, 0xcc37, 0x0fcf, 0xcc37, 0x21, 0 - .dw 0x0fd1, 0xcc37, 0x0fd1, 0xcc37, 0x21, 0 - .dw 0x0fd3, 0xcc37, 0x1fff, 0xcc37, 0x21, 0 - .dw 0x2001, 0xcc37, 0x2001, 0xcc37, 0x21, 0 - .dw 0x2003, 0xcc37, 0x200f, 0xcc37, 0x21, 0 - .dw 0x2011, 0xcc37, 0x2011, 0xcc37, 0x21, 0 - .dw 0x2013, 0xcc37, 0x203f, 0xcc37, 0x21, 0 - .dw 0x2041, 0xcc37, 0x2041, 0xcc37, 0x21, 0 - .dw 0x2043, 0xcc37, 0x204f, 0xcc37, 0x21, 0 - .dw 0x2051, 0xcc37, 0x2051, 0xcc37, 0x21, 0 - .dw 0x2053, 0xcc37, 0x207f, 0xcc37, 0x21, 0 - .dw 0x2081, 0xcc37, 0x2081, 0xcc37, 0x21, 0 - .dw 0x2083, 0xcc37, 0x208f, 0xcc37, 0x21, 0 - .dw 0x2091, 0xcc37, 0x2091, 0xcc37, 0x21, 0 - .dw 0x2093, 0xcc37, 0x20bf, 0xcc37, 0x21, 0 - .dw 0x20c1, 0xcc37, 0x20c1, 0xcc37, 0x21, 0 - .dw 0x20c3, 0xcc37, 0x20cf, 0xcc37, 0x21, 0 - .dw 0x20d1, 0xcc37, 0x20d1, 0xcc37, 0x21, 0 - .dw 0x20d3, 0xcc37, 0x20ff, 0xcc37, 0x21, 0 - .dw 0x2101, 0xcc37, 0x2101, 0xcc37, 0x21, 0 - .dw 0x2103, 0xcc37, 0x210f, 0xcc37, 0x21, 0 - .dw 0x2111, 0xcc37, 0x2111, 0xcc37, 0x21, 0 - .dw 0x2113, 0xcc37, 0x213f, 0xcc37, 0x21, 0 - .dw 0x2141, 0xcc37, 0x2141, 0xcc37, 0x21, 0 - .dw 0x2143, 0xcc37, 0x214f, 0xcc37, 0x21, 0 - .dw 0x2151, 0xcc37, 0x2151, 0xcc37, 0x21, 0 - .dw 0x2153, 0xcc37, 0x217f, 0xcc37, 0x21, 0 - .dw 0x2181, 0xcc37, 0x2181, 0xcc37, 0x21, 0 - .dw 0x2183, 0xcc37, 0x218f, 0xcc37, 0x21, 0 - .dw 0x2191, 0xcc37, 0x2191, 0xcc37, 0x21, 0 - .dw 0x2193, 0xcc37, 0x21bf, 0xcc37, 0x21, 0 - .dw 0x21c1, 0xcc37, 0x21c1, 0xcc37, 0x21, 0 - .dw 0x21c3, 0xcc37, 0x21cf, 0xcc37, 0x21, 0 - .dw 0x21d1, 0xcc37, 0x21d1, 0xcc37, 0x21, 0 - .dw 0x21d3, 0xcc37, 0x21ff, 0xcc37, 0x21, 0 - .dw 0x2201, 0xcc37, 0x2201, 0xcc37, 0x21, 0 - .dw 0x2203, 0xcc37, 0x220f, 0xcc37, 0x21, 0 - .dw 0x2211, 0xcc37, 0x2211, 0xcc37, 0x21, 0 - .dw 0x2213, 0xcc37, 0x223f, 0xcc37, 0x21, 0 - .dw 0x2241, 0xcc37, 0x2241, 0xcc37, 0x21, 0 - .dw 0x2243, 0xcc37, 0x224f, 0xcc37, 0x21, 0 - .dw 0x2251, 0xcc37, 0x2251, 0xcc37, 0x21, 0 - .dw 0x2253, 0xcc37, 0x227f, 0xcc37, 0x21, 0 - .dw 0x2281, 0xcc37, 0x2281, 0xcc37, 0x21, 0 - .dw 0x2283, 0xcc37, 0x228f, 0xcc37, 0x21, 0 - .dw 0x2291, 0xcc37, 0x2291, 0xcc37, 0x21, 0 - .dw 0x2293, 0xcc37, 0x22bf, 0xcc37, 0x21, 0 - .dw 0x22c1, 0xcc37, 0x22c1, 0xcc37, 0x21, 0 - .dw 0x22c3, 0xcc37, 0x22cf, 0xcc37, 0x21, 0 - .dw 0x22d1, 0xcc37, 0x22d1, 0xcc37, 0x21, 0 - .dw 0x22d3, 0xcc37, 0x22ff, 0xcc37, 0x21, 0 - .dw 0x2301, 0xcc37, 0x2301, 0xcc37, 0x21, 0 - .dw 0x2303, 0xcc37, 0x230f, 0xcc37, 0x21, 0 - .dw 0x2311, 0xcc37, 0x2311, 0xcc37, 0x21, 0 - .dw 0x2313, 0xcc37, 0x233f, 0xcc37, 0x21, 0 - .dw 0x2341, 0xcc37, 0x2341, 0xcc37, 0x21, 0 - .dw 0x2343, 0xcc37, 0x234f, 0xcc37, 0x21, 0 - .dw 0x2351, 0xcc37, 0x2351, 0xcc37, 0x21, 0 - .dw 0x2353, 0xcc37, 0x237f, 0xcc37, 0x21, 0 - .dw 0x2381, 0xcc37, 0x2381, 0xcc37, 0x21, 0 - .dw 0x2383, 0xcc37, 0x238f, 0xcc37, 0x21, 0 - .dw 0x2391, 0xcc37, 0x2391, 0xcc37, 0x21, 0 - .dw 0x2393, 0xcc37, 0x23bf, 0xcc37, 0x21, 0 - .dw 0x23c1, 0xcc37, 0x23c1, 0xcc37, 0x21, 0 - .dw 0x23c3, 0xcc37, 0x23cf, 0xcc37, 0x21, 0 - .dw 0x23d1, 0xcc37, 0x23d1, 0xcc37, 0x21, 0 - .dw 0x23d3, 0xcc37, 0x23ff, 0xcc37, 0x21, 0 - .dw 0x2401, 0xcc37, 0x2401, 0xcc37, 0x21, 0 - .dw 0x2403, 0xcc37, 0x240f, 0xcc37, 0x21, 0 - .dw 0x2411, 0xcc37, 0x2411, 0xcc37, 0x21, 0 - .dw 0x2413, 0xcc37, 0x243f, 0xcc37, 0x21, 0 - .dw 0x2441, 0xcc37, 0x2441, 0xcc37, 0x21, 0 - .dw 0x2443, 0xcc37, 0x244f, 0xcc37, 0x21, 0 - .dw 0x2451, 0xcc37, 0x2451, 0xcc37, 0x21, 0 - .dw 0x2453, 0xcc37, 0x247f, 0xcc37, 0x21, 0 - .dw 0x2481, 0xcc37, 0x2481, 0xcc37, 0x21, 0 - .dw 0x2483, 0xcc37, 0x248f, 0xcc37, 0x21, 0 - .dw 0x2491, 0xcc37, 0x2491, 0xcc37, 0x21, 0 - .dw 0x2493, 0xcc37, 0x24bf, 0xcc37, 0x21, 0 - .dw 0x24c1, 0xcc37, 0x24c1, 0xcc37, 0x21, 0 - .dw 0x24c3, 0xcc37, 0x24cf, 0xcc37, 0x21, 0 - .dw 0x24d1, 0xcc37, 0x24d1, 0xcc37, 0x21, 0 - .dw 0x24d3, 0xcc37, 0x24ff, 0xcc37, 0x21, 0 - .dw 0x2501, 0xcc37, 0x2501, 0xcc37, 0x21, 0 - .dw 0x2503, 0xcc37, 0x250f, 0xcc37, 0x21, 0 - .dw 0x2511, 0xcc37, 0x2511, 0xcc37, 0x21, 0 - .dw 0x2513, 0xcc37, 0x253f, 0xcc37, 0x21, 0 - .dw 0x2541, 0xcc37, 0x2541, 0xcc37, 0x21, 0 - .dw 0x2543, 0xcc37, 0x254f, 0xcc37, 0x21, 0 - .dw 0x2551, 0xcc37, 0x2551, 0xcc37, 0x21, 0 - .dw 0x2553, 0xcc37, 0x257f, 0xcc37, 0x21, 0 - .dw 0x2581, 0xcc37, 0x2581, 0xcc37, 0x21, 0 - .dw 0x2583, 0xcc37, 0x258f, 0xcc37, 0x21, 0 - .dw 0x2591, 0xcc37, 0x2591, 0xcc37, 0x21, 0 - .dw 0x2593, 0xcc37, 0x25bf, 0xcc37, 0x21, 0 - .dw 0x25c1, 0xcc37, 0x25c1, 0xcc37, 0x21, 0 - .dw 0x25c3, 0xcc37, 0x25cf, 0xcc37, 0x21, 0 - .dw 0x25d1, 0xcc37, 0x25d1, 0xcc37, 0x21, 0 - .dw 0x25d3, 0xcc37, 0x25ff, 0xcc37, 0x21, 0 - .dw 0x2601, 0xcc37, 0x2601, 0xcc37, 0x21, 0 - .dw 0x2603, 0xcc37, 0x260f, 0xcc37, 0x21, 0 - .dw 0x2611, 0xcc37, 0x2611, 0xcc37, 0x21, 0 - .dw 0x2613, 0xcc37, 0x263f, 0xcc37, 0x21, 0 - .dw 0x2641, 0xcc37, 0x2641, 0xcc37, 0x21, 0 - .dw 0x2643, 0xcc37, 0x264f, 0xcc37, 0x21, 0 - .dw 0x2651, 0xcc37, 0x2651, 0xcc37, 0x21, 0 - .dw 0x2653, 0xcc37, 0x267f, 0xcc37, 0x21, 0 - .dw 0x2681, 0xcc37, 0x2681, 0xcc37, 0x21, 0 - .dw 0x2683, 0xcc37, 0x268f, 0xcc37, 0x21, 0 - .dw 0x2691, 0xcc37, 0x2691, 0xcc37, 0x21, 0 - .dw 0x2693, 0xcc37, 0x26bf, 0xcc37, 0x21, 0 - .dw 0x26c1, 0xcc37, 0x26c1, 0xcc37, 0x21, 0 - .dw 0x26c3, 0xcc37, 0x26cf, 0xcc37, 0x21, 0 - .dw 0x26d1, 0xcc37, 0x26d1, 0xcc37, 0x21, 0 - .dw 0x26d3, 0xcc37, 0x26ff, 0xcc37, 0x21, 0 - .dw 0x2701, 0xcc37, 0x2701, 0xcc37, 0x21, 0 - .dw 0x2703, 0xcc37, 0x270f, 0xcc37, 0x21, 0 - .dw 0x2711, 0xcc37, 0x2711, 0xcc37, 0x21, 0 - .dw 0x2713, 0xcc37, 0x273f, 0xcc37, 0x21, 0 - .dw 0x2741, 0xcc37, 0x2741, 0xcc37, 0x21, 0 - .dw 0x2743, 0xcc37, 0x274f, 0xcc37, 0x21, 0 - .dw 0x2751, 0xcc37, 0x2751, 0xcc37, 0x21, 0 - .dw 0x2753, 0xcc37, 0x277f, 0xcc37, 0x21, 0 - .dw 0x2781, 0xcc37, 0x2781, 0xcc37, 0x21, 0 - .dw 0x2783, 0xcc37, 0x278f, 0xcc37, 0x21, 0 - .dw 0x2791, 0xcc37, 0x2791, 0xcc37, 0x21, 0 - .dw 0x2793, 0xcc37, 0x27bf, 0xcc37, 0x21, 0 - .dw 0x27c1, 0xcc37, 0x27c1, 0xcc37, 0x21, 0 - .dw 0x27c3, 0xcc37, 0x27cf, 0xcc37, 0x21, 0 - .dw 0x27d1, 0xcc37, 0x27d1, 0xcc37, 0x21, 0 - .dw 0x27d3, 0xcc37, 0x27ff, 0xcc37, 0x21, 0 - .dw 0x2801, 0xcc37, 0x2801, 0xcc37, 0x21, 0 - .dw 0x2803, 0xcc37, 0x280f, 0xcc37, 0x21, 0 - .dw 0x2811, 0xcc37, 0x2811, 0xcc37, 0x21, 0 - .dw 0x2813, 0xcc37, 0x283f, 0xcc37, 0x21, 0 - .dw 0x2841, 0xcc37, 0x2841, 0xcc37, 0x21, 0 - .dw 0x2843, 0xcc37, 0x284f, 0xcc37, 0x21, 0 - .dw 0x2851, 0xcc37, 0x2851, 0xcc37, 0x21, 0 - .dw 0x2853, 0xcc37, 0x287f, 0xcc37, 0x21, 0 - .dw 0x2881, 0xcc37, 0x2881, 0xcc37, 0x21, 0 - .dw 0x2883, 0xcc37, 0x288f, 0xcc37, 0x21, 0 - .dw 0x2891, 0xcc37, 0x2891, 0xcc37, 0x21, 0 - .dw 0x2893, 0xcc37, 0x28bf, 0xcc37, 0x21, 0 - .dw 0x28c1, 0xcc37, 0x28c1, 0xcc37, 0x21, 0 - .dw 0x28c3, 0xcc37, 0x28cf, 0xcc37, 0x21, 0 - .dw 0x28d1, 0xcc37, 0x28d1, 0xcc37, 0x21, 0 - .dw 0x28d3, 0xcc37, 0x28ff, 0xcc37, 0x21, 0 - .dw 0x2901, 0xcc37, 0x2901, 0xcc37, 0x21, 0 - .dw 0x2903, 0xcc37, 0x290f, 0xcc37, 0x21, 0 - .dw 0x2911, 0xcc37, 0x2911, 0xcc37, 0x21, 0 - .dw 0x2913, 0xcc37, 0x293f, 0xcc37, 0x21, 0 - .dw 0x2941, 0xcc37, 0x2941, 0xcc37, 0x21, 0 - .dw 0x2943, 0xcc37, 0x294f, 0xcc37, 0x21, 0 - .dw 0x2951, 0xcc37, 0x2951, 0xcc37, 0x21, 0 - .dw 0x2953, 0xcc37, 0x297f, 0xcc37, 0x21, 0 - .dw 0x2981, 0xcc37, 0x2981, 0xcc37, 0x21, 0 - .dw 0x2983, 0xcc37, 0x298f, 0xcc37, 0x21, 0 - .dw 0x2991, 0xcc37, 0x2991, 0xcc37, 0x21, 0 - .dw 0x2993, 0xcc37, 0x29bf, 0xcc37, 0x21, 0 - .dw 0x29c1, 0xcc37, 0x29c1, 0xcc37, 0x21, 0 - .dw 0x29c3, 0xcc37, 0x29cf, 0xcc37, 0x21, 0 - .dw 0x29d1, 0xcc37, 0x29d1, 0xcc37, 0x21, 0 - .dw 0x29d3, 0xcc37, 0x29ff, 0xcc37, 0x21, 0 - .dw 0x2a01, 0xcc37, 0x2a01, 0xcc37, 0x21, 0 - .dw 0x2a03, 0xcc37, 0x2a0f, 0xcc37, 0x21, 0 - .dw 0x2a11, 0xcc37, 0x2a11, 0xcc37, 0x21, 0 - .dw 0x2a13, 0xcc37, 0x2a3f, 0xcc37, 0x21, 0 - .dw 0x2a41, 0xcc37, 0x2a41, 0xcc37, 0x21, 0 - .dw 0x2a43, 0xcc37, 0x2a4f, 0xcc37, 0x21, 0 - .dw 0x2a51, 0xcc37, 0x2a51, 0xcc37, 0x21, 0 - .dw 0x2a53, 0xcc37, 0x2a7f, 0xcc37, 0x21, 0 - .dw 0x2a81, 0xcc37, 0x2a81, 0xcc37, 0x21, 0 - .dw 0x2a83, 0xcc37, 0x2a8f, 0xcc37, 0x21, 0 - .dw 0x2a91, 0xcc37, 0x2a91, 0xcc37, 0x21, 0 - .dw 0x2a93, 0xcc37, 0x2abf, 0xcc37, 0x21, 0 - .dw 0x2ac1, 0xcc37, 0x2ac1, 0xcc37, 0x21, 0 - .dw 0x2ac3, 0xcc37, 0x2acf, 0xcc37, 0x21, 0 - .dw 0x2ad1, 0xcc37, 0x2ad1, 0xcc37, 0x21, 0 - .dw 0x2ad3, 0xcc37, 0x2aff, 0xcc37, 0x21, 0 - .dw 0x2b01, 0xcc37, 0x2b01, 0xcc37, 0x21, 0 - .dw 0x2b03, 0xcc37, 0x2b0f, 0xcc37, 0x21, 0 - .dw 0x2b11, 0xcc37, 0x2b11, 0xcc37, 0x21, 0 - .dw 0x2b13, 0xcc37, 0x2b3f, 0xcc37, 0x21, 0 - .dw 0x2b41, 0xcc37, 0x2b41, 0xcc37, 0x21, 0 - .dw 0x2b43, 0xcc37, 0x2b4f, 0xcc37, 0x21, 0 - .dw 0x2b51, 0xcc37, 0x2b51, 0xcc37, 0x21, 0 - .dw 0x2b53, 0xcc37, 0x2b7f, 0xcc37, 0x21, 0 - .dw 0x2b81, 0xcc37, 0x2b81, 0xcc37, 0x21, 0 - .dw 0x2b83, 0xcc37, 0x2b8f, 0xcc37, 0x21, 0 - .dw 0x2b91, 0xcc37, 0x2b91, 0xcc37, 0x21, 0 - .dw 0x2b93, 0xcc37, 0x2bbf, 0xcc37, 0x21, 0 - .dw 0x2bc1, 0xcc37, 0x2bc1, 0xcc37, 0x21, 0 - .dw 0x2bc3, 0xcc37, 0x2bcf, 0xcc37, 0x21, 0 - .dw 0x2bd1, 0xcc37, 0x2bd1, 0xcc37, 0x21, 0 - .dw 0x2bd3, 0xcc37, 0x2bff, 0xcc37, 0x21, 0 - .dw 0x2c01, 0xcc37, 0x2c01, 0xcc37, 0x21, 0 - .dw 0x2c03, 0xcc37, 0x2c0f, 0xcc37, 0x21, 0 - .dw 0x2c11, 0xcc37, 0x2c11, 0xcc37, 0x21, 0 - .dw 0x2c13, 0xcc37, 0x2c3f, 0xcc37, 0x21, 0 - .dw 0x2c41, 0xcc37, 0x2c41, 0xcc37, 0x21, 0 - .dw 0x2c43, 0xcc37, 0x2c4f, 0xcc37, 0x21, 0 - .dw 0x2c51, 0xcc37, 0x2c51, 0xcc37, 0x21, 0 - .dw 0x2c53, 0xcc37, 0x2c7f, 0xcc37, 0x21, 0 - .dw 0x2c81, 0xcc37, 0x2c81, 0xcc37, 0x21, 0 - .dw 0x2c83, 0xcc37, 0x2c8f, 0xcc37, 0x21, 0 - .dw 0x2c91, 0xcc37, 0x2c91, 0xcc37, 0x21, 0 - .dw 0x2c93, 0xcc37, 0x2cbf, 0xcc37, 0x21, 0 - .dw 0x2cc1, 0xcc37, 0x2cc1, 0xcc37, 0x21, 0 - .dw 0x2cc3, 0xcc37, 0x2ccf, 0xcc37, 0x21, 0 - .dw 0x2cd1, 0xcc37, 0x2cd1, 0xcc37, 0x21, 0 - .dw 0x2cd3, 0xcc37, 0x2cff, 0xcc37, 0x21, 0 - .dw 0x2d01, 0xcc37, 0x2d01, 0xcc37, 0x21, 0 - .dw 0x2d03, 0xcc37, 0x2d0f, 0xcc37, 0x21, 0 - .dw 0x2d11, 0xcc37, 0x2d11, 0xcc37, 0x21, 0 - .dw 0x2d13, 0xcc37, 0x2d3f, 0xcc37, 0x21, 0 - .dw 0x2d41, 0xcc37, 0x2d41, 0xcc37, 0x21, 0 - .dw 0x2d43, 0xcc37, 0x2d4f, 0xcc37, 0x21, 0 - .dw 0x2d51, 0xcc37, 0x2d51, 0xcc37, 0x21, 0 - .dw 0x2d53, 0xcc37, 0x2d7f, 0xcc37, 0x21, 0 - .dw 0x2d81, 0xcc37, 0x2d81, 0xcc37, 0x21, 0 - .dw 0x2d83, 0xcc37, 0x2d8f, 0xcc37, 0x21, 0 - .dw 0x2d91, 0xcc37, 0x2d91, 0xcc37, 0x21, 0 - .dw 0x2d93, 0xcc37, 0x2dbf, 0xcc37, 0x21, 0 - .dw 0x2dc1, 0xcc37, 0x2dc1, 0xcc37, 0x21, 0 - .dw 0x2dc3, 0xcc37, 0x2dcf, 0xcc37, 0x21, 0 - .dw 0x2dd1, 0xcc37, 0x2dd1, 0xcc37, 0x21, 0 - .dw 0x2dd3, 0xcc37, 0x2dff, 0xcc37, 0x21, 0 - .dw 0x2e01, 0xcc37, 0x2e01, 0xcc37, 0x21, 0 - .dw 0x2e03, 0xcc37, 0x2e0f, 0xcc37, 0x21, 0 - .dw 0x2e11, 0xcc37, 0x2e11, 0xcc37, 0x21, 0 - .dw 0x2e13, 0xcc37, 0x2e3f, 0xcc37, 0x21, 0 - .dw 0x2e41, 0xcc37, 0x2e41, 0xcc37, 0x21, 0 - .dw 0x2e43, 0xcc37, 0x2e4f, 0xcc37, 0x21, 0 - .dw 0x2e51, 0xcc37, 0x2e51, 0xcc37, 0x21, 0 - .dw 0x2e53, 0xcc37, 0x2e7f, 0xcc37, 0x21, 0 - .dw 0x2e81, 0xcc37, 0x2e81, 0xcc37, 0x21, 0 - .dw 0x2e83, 0xcc37, 0x2e8f, 0xcc37, 0x21, 0 - .dw 0x2e91, 0xcc37, 0x2e91, 0xcc37, 0x21, 0 - .dw 0x2e93, 0xcc37, 0x2ebf, 0xcc37, 0x21, 0 - .dw 0x2ec1, 0xcc37, 0x2ec1, 0xcc37, 0x21, 0 - .dw 0x2ec3, 0xcc37, 0x2ecf, 0xcc37, 0x21, 0 - .dw 0x2ed1, 0xcc37, 0x2ed1, 0xcc37, 0x21, 0 - .dw 0x2ed3, 0xcc37, 0x2eff, 0xcc37, 0x21, 0 - .dw 0x2f01, 0xcc37, 0x2f01, 0xcc37, 0x21, 0 - .dw 0x2f03, 0xcc37, 0x2f0f, 0xcc37, 0x21, 0 - .dw 0x2f11, 0xcc37, 0x2f11, 0xcc37, 0x21, 0 - .dw 0x2f13, 0xcc37, 0x2f3f, 0xcc37, 0x21, 0 - .dw 0x2f41, 0xcc37, 0x2f41, 0xcc37, 0x21, 0 - .dw 0x2f43, 0xcc37, 0x2f4f, 0xcc37, 0x21, 0 - .dw 0x2f51, 0xcc37, 0x2f51, 0xcc37, 0x21, 0 - .dw 0x2f53, 0xcc37, 0x2f7f, 0xcc37, 0x21, 0 - .dw 0x2f81, 0xcc37, 0x2f81, 0xcc37, 0x21, 0 - .dw 0x2f83, 0xcc37, 0x2f8f, 0xcc37, 0x21, 0 - .dw 0x2f91, 0xcc37, 0x2f91, 0xcc37, 0x21, 0 - .dw 0x2f93, 0xcc37, 0x2fbf, 0xcc37, 0x21, 0 - .dw 0x2fc1, 0xcc37, 0x2fc1, 0xcc37, 0x21, 0 - .dw 0x2fc3, 0xcc37, 0x2fcf, 0xcc37, 0x21, 0 - .dw 0x2fd1, 0xcc37, 0x2fd1, 0xcc37, 0x21, 0 - .dw 0x2fd3, 0xcc37, 0xffff, 0xcdff, 0x21, 0 - .dw 0x0040, 0xce00, 0x01ff, 0xce00, 0x21, 0 - .dw 0x0240, 0xce00, 0x03ff, 0xce00, 0x21, 0 - .dw 0x0440, 0xce00, 0x05ff, 0xce00, 0x21, 0 - .dw 0x0640, 0xce00, 0x07ff, 0xce00, 0x21, 0 - .dw 0x0840, 0xce00, 0x09ff, 0xce00, 0x21, 0 - .dw 0x0a40, 0xce00, 0x0bff, 0xce00, 0x21, 0 - .dw 0x0c40, 0xce00, 0x0dff, 0xce00, 0x21, 0 - .dw 0x0e40, 0xce00, 0x0fff, 0xce00, 0x21, 0 - .dw 0x1040, 0xce00, 0x11ff, 0xce00, 0x21, 0 - .dw 0x1240, 0xce00, 0x13ff, 0xce00, 0x21, 0 - .dw 0x1440, 0xce00, 0x15ff, 0xce00, 0x21, 0 - .dw 0x1640, 0xce00, 0x17ff, 0xce00, 0x21, 0 - .dw 0x1840, 0xce00, 0x19ff, 0xce00, 0x21, 0 - .dw 0x1a40, 0xce00, 0x1bff, 0xce00, 0x21, 0 - .dw 0x1c40, 0xce00, 0x1dff, 0xce00, 0x21, 0 - .dw 0x1e40, 0xce00, 0x1fff, 0xce00, 0x21, 0 - .dw 0x2040, 0xce00, 0x21ff, 0xce00, 0x21, 0 - .dw 0x2240, 0xce00, 0x23ff, 0xce00, 0x21, 0 - .dw 0x2440, 0xce00, 0x25ff, 0xce00, 0x21, 0 - .dw 0x2640, 0xce00, 0x27ff, 0xce00, 0x21, 0 - .dw 0x2840, 0xce00, 0x29ff, 0xce00, 0x21, 0 - .dw 0x2a40, 0xce00, 0x2bff, 0xce00, 0x21, 0 - .dw 0x2c40, 0xce00, 0x2dff, 0xce00, 0x21, 0 - .dw 0x2e40, 0xce00, 0x2fff, 0xce00, 0x21, 0 - .dw 0x3040, 0xce00, 0x31ff, 0xce00, 0x21, 0 - .dw 0x3240, 0xce00, 0x33ff, 0xce00, 0x21, 0 - .dw 0x3440, 0xce00, 0x35ff, 0xce00, 0x21, 0 - .dw 0x3640, 0xce00, 0x37ff, 0xce00, 0x21, 0 - .dw 0x3840, 0xce00, 0x39ff, 0xce00, 0x21, 0 - .dw 0x3a40, 0xce00, 0x3bff, 0xce00, 0x21, 0 - .dw 0x3c40, 0xce00, 0x3dff, 0xce00, 0x21, 0 - .dw 0x3e40, 0xce00, 0x3fff, 0xce00, 0x21, 0 - .dw 0x4040, 0xce00, 0x41ff, 0xce00, 0x21, 0 - .dw 0x4240, 0xce00, 0x43ff, 0xce00, 0x21, 0 - .dw 0x4440, 0xce00, 0x45ff, 0xce00, 0x21, 0 - .dw 0x4640, 0xce00, 0x47ff, 0xce00, 0x21, 0 - .dw 0x4840, 0xce00, 0x49ff, 0xce00, 0x21, 0 - .dw 0x4a40, 0xce00, 0x4bff, 0xce00, 0x21, 0 - .dw 0x4c40, 0xce00, 0x4dff, 0xce00, 0x21, 0 - .dw 0x4e40, 0xce00, 0x4fff, 0xce00, 0x21, 0 - .dw 0x5040, 0xce00, 0x51ff, 0xce00, 0x21, 0 - .dw 0x5240, 0xce00, 0x53ff, 0xce00, 0x21, 0 - .dw 0x5440, 0xce00, 0x55ff, 0xce00, 0x21, 0 - .dw 0x5640, 0xce00, 0x57ff, 0xce00, 0x21, 0 - .dw 0x5840, 0xce00, 0x59ff, 0xce00, 0x21, 0 - .dw 0x5a40, 0xce00, 0x5bff, 0xce00, 0x21, 0 - .dw 0x5c40, 0xce00, 0x5dff, 0xce00, 0x21, 0 - .dw 0x5e40, 0xce00, 0x5fff, 0xce00, 0x21, 0 - .dw 0x6040, 0xce00, 0x61ff, 0xce00, 0x21, 0 - .dw 0x6240, 0xce00, 0x63ff, 0xce00, 0x21, 0 - .dw 0x6440, 0xce00, 0x65ff, 0xce00, 0x21, 0 - .dw 0x6640, 0xce00, 0x67ff, 0xce00, 0x21, 0 - .dw 0x6840, 0xce00, 0x69ff, 0xce00, 0x21, 0 - .dw 0x6a40, 0xce00, 0x6bff, 0xce00, 0x21, 0 - .dw 0x6c40, 0xce00, 0x6dff, 0xce00, 0x21, 0 - .dw 0x6e40, 0xce00, 0x6fff, 0xce00, 0x21, 0 - .dw 0x7040, 0xce00, 0x71ff, 0xce00, 0x21, 0 - .dw 0x7240, 0xce00, 0x73ff, 0xce00, 0x21, 0 - .dw 0x7440, 0xce00, 0x75ff, 0xce00, 0x21, 0 - .dw 0x7640, 0xce00, 0x77ff, 0xce00, 0x21, 0 - .dw 0x7840, 0xce00, 0x79ff, 0xce00, 0x21, 0 - .dw 0x7a40, 0xce00, 0x7bff, 0xce00, 0x21, 0 - .dw 0x7c40, 0xce00, 0x7dff, 0xce00, 0x21, 0 - .dw 0x7e40, 0xce00, 0x7fff, 0xce00, 0x21, 0 - .dw 0x8040, 0xce00, 0x81ff, 0xce00, 0x21, 0 - .dw 0x8240, 0xce00, 0x83ff, 0xce00, 0x21, 0 - .dw 0x8440, 0xce00, 0x85ff, 0xce00, 0x21, 0 - .dw 0x8640, 0xce00, 0x87ff, 0xce00, 0x21, 0 - .dw 0x8840, 0xce00, 0x89ff, 0xce00, 0x21, 0 - .dw 0x8a40, 0xce00, 0x8bff, 0xce00, 0x21, 0 - .dw 0x8c40, 0xce00, 0x8dff, 0xce00, 0x21, 0 - .dw 0x8e40, 0xce00, 0x8fff, 0xce00, 0x21, 0 - .dw 0x9040, 0xce00, 0x91ff, 0xce00, 0x21, 0 - .dw 0x9240, 0xce00, 0x93ff, 0xce00, 0x21, 0 - .dw 0x9440, 0xce00, 0x95ff, 0xce00, 0x21, 0 - .dw 0x9640, 0xce00, 0x97ff, 0xce00, 0x21, 0 - .dw 0x9840, 0xce00, 0x99ff, 0xce00, 0x21, 0 - .dw 0x9a40, 0xce00, 0x9bff, 0xce00, 0x21, 0 - .dw 0x9c40, 0xce00, 0x9dff, 0xce00, 0x21, 0 - .dw 0x9e40, 0xce00, 0x9fff, 0xce00, 0x21, 0 - .dw 0xa040, 0xce00, 0xa1ff, 0xce00, 0x21, 0 - .dw 0xa240, 0xce00, 0xa3ff, 0xce00, 0x21, 0 - .dw 0xa440, 0xce00, 0xa5ff, 0xce00, 0x21, 0 - .dw 0xa640, 0xce00, 0xa7ff, 0xce00, 0x21, 0 - .dw 0xa840, 0xce00, 0xa9ff, 0xce00, 0x21, 0 - .dw 0xaa40, 0xce00, 0xabff, 0xce00, 0x21, 0 - .dw 0xac40, 0xce00, 0xadff, 0xce00, 0x21, 0 - .dw 0xae40, 0xce00, 0xafff, 0xce00, 0x21, 0 - .dw 0xb040, 0xce00, 0xb1ff, 0xce00, 0x21, 0 - .dw 0xb240, 0xce00, 0xb3ff, 0xce00, 0x21, 0 - .dw 0xb440, 0xce00, 0xb5ff, 0xce00, 0x21, 0 - .dw 0xb640, 0xce00, 0xb7ff, 0xce00, 0x21, 0 - .dw 0xb840, 0xce00, 0xb9ff, 0xce00, 0x21, 0 - .dw 0xba40, 0xce00, 0xbbff, 0xce00, 0x21, 0 - .dw 0xbc40, 0xce00, 0xbdff, 0xce00, 0x21, 0 - .dw 0xbe40, 0xce00, 0xffff, 0xce00, 0x21, 0 - .dw 0x0040, 0xce01, 0x01ff, 0xce01, 0x21, 0 - .dw 0x0240, 0xce01, 0x03ff, 0xce01, 0x21, 0 - .dw 0x0440, 0xce01, 0x05ff, 0xce01, 0x21, 0 - .dw 0x0640, 0xce01, 0x07ff, 0xce01, 0x21, 0 - .dw 0x0840, 0xce01, 0x09ff, 0xce01, 0x21, 0 - .dw 0x0a40, 0xce01, 0x0bff, 0xce01, 0x21, 0 - .dw 0x0c40, 0xce01, 0x0dff, 0xce01, 0x21, 0 - .dw 0x0e40, 0xce01, 0x3fff, 0xce01, 0x21, 0 - .dw 0x4040, 0xce01, 0x41ff, 0xce01, 0x21, 0 - .dw 0x4240, 0xce01, 0x43ff, 0xce01, 0x21, 0 - .dw 0x4440, 0xce01, 0x45ff, 0xce01, 0x21, 0 - .dw 0x4640, 0xce01, 0x47ff, 0xce01, 0x21, 0 - .dw 0x4840, 0xce01, 0x49ff, 0xce01, 0x21, 0 - .dw 0x4a40, 0xce01, 0x4bff, 0xce01, 0x21, 0 - .dw 0x4c40, 0xce01, 0x4dff, 0xce01, 0x21, 0 - .dw 0x4e40, 0xce01, 0x7fff, 0xce01, 0x21, 0 - .dw 0x8040, 0xce01, 0x81ff, 0xce01, 0x21, 0 - .dw 0x8240, 0xce01, 0x83ff, 0xce01, 0x21, 0 - .dw 0x8440, 0xce01, 0x85ff, 0xce01, 0x21, 0 - .dw 0x8640, 0xce01, 0x87ff, 0xce01, 0x21, 0 - .dw 0x8840, 0xce01, 0x89ff, 0xce01, 0x21, 0 - .dw 0x8a40, 0xce01, 0x8bff, 0xce01, 0x21, 0 - .dw 0x8c40, 0xce01, 0x8dff, 0xce01, 0x21, 0 - .dw 0x8e40, 0xce01, 0xffff, 0xce01, 0x21, 0 - .dw 0x0040, 0xce02, 0x01ff, 0xce02, 0x21, 0 - .dw 0x0240, 0xce02, 0x03ff, 0xce02, 0x21, 0 - .dw 0x0440, 0xce02, 0x05ff, 0xce02, 0x21, 0 - .dw 0x0640, 0xce02, 0x07ff, 0xce02, 0x21, 0 - .dw 0x0840, 0xce02, 0x09ff, 0xce02, 0x21, 0 - .dw 0x0a40, 0xce02, 0x0bff, 0xce02, 0x21, 0 - .dw 0x0c40, 0xce02, 0x0dff, 0xce02, 0x21, 0 - .dw 0x0e40, 0xce02, 0x3fff, 0xce02, 0x21, 0 - .dw 0x4040, 0xce02, 0x41ff, 0xce02, 0x21, 0 - .dw 0x4240, 0xce02, 0x43ff, 0xce02, 0x21, 0 - .dw 0x4440, 0xce02, 0x45ff, 0xce02, 0x21, 0 - .dw 0x4640, 0xce02, 0x47ff, 0xce02, 0x21, 0 - .dw 0x4840, 0xce02, 0x49ff, 0xce02, 0x21, 0 - .dw 0x4a40, 0xce02, 0x4bff, 0xce02, 0x21, 0 - .dw 0x4c40, 0xce02, 0x4dff, 0xce02, 0x21, 0 - .dw 0x4e40, 0xce02, 0x7fff, 0xce02, 0x21, 0 - .dw 0x8040, 0xce02, 0x81ff, 0xce02, 0x21, 0 - .dw 0x8240, 0xce02, 0x83ff, 0xce02, 0x21, 0 - .dw 0x8440, 0xce02, 0x85ff, 0xce02, 0x21, 0 - .dw 0x8640, 0xce02, 0x87ff, 0xce02, 0x21, 0 - .dw 0x8840, 0xce02, 0x89ff, 0xce02, 0x21, 0 - .dw 0x8a40, 0xce02, 0x8bff, 0xce02, 0x21, 0 - .dw 0x8c40, 0xce02, 0x8dff, 0xce02, 0x21, 0 - .dw 0x8e40, 0xce02, 0xbfff, 0xce02, 0x21, 0 - .dw 0xc040, 0xce02, 0xc1ff, 0xce02, 0x21, 0 - .dw 0xc240, 0xce02, 0xc3ff, 0xce02, 0x21, 0 - .dw 0xc440, 0xce02, 0xc5ff, 0xce02, 0x21, 0 - .dw 0xc640, 0xce02, 0xc7ff, 0xce02, 0x21, 0 - .dw 0xc840, 0xce02, 0xc9ff, 0xce02, 0x21, 0 - .dw 0xca40, 0xce02, 0xcbff, 0xce02, 0x21, 0 - .dw 0xcc40, 0xce02, 0xcdff, 0xce02, 0x21, 0 - .dw 0xce40, 0xce02, 0xffff, 0xce02, 0x21, 0 - .dw 0x0040, 0xce03, 0x01ff, 0xce03, 0x21, 0 - .dw 0x0240, 0xce03, 0x03ff, 0xce03, 0x21, 0 - .dw 0x0440, 0xce03, 0x05ff, 0xce03, 0x21, 0 - .dw 0x0640, 0xce03, 0x07ff, 0xce03, 0x21, 0 - .dw 0x0840, 0xce03, 0x09ff, 0xce03, 0x21, 0 - .dw 0x0a40, 0xce03, 0x0bff, 0xce03, 0x21, 0 - .dw 0x0c40, 0xce03, 0x0dff, 0xce03, 0x21, 0 - .dw 0x0e40, 0xce03, 0x0fff, 0xce03, 0x21, 0 - .dw 0x1040, 0xce03, 0x11ff, 0xce03, 0x21, 0 - .dw 0x1240, 0xce03, 0x13ff, 0xce03, 0x21, 0 - .dw 0x1440, 0xce03, 0x15ff, 0xce03, 0x21, 0 - .dw 0x1640, 0xce03, 0x17ff, 0xce03, 0x21, 0 - .dw 0x1840, 0xce03, 0x19ff, 0xce03, 0x21, 0 - .dw 0x1a40, 0xce03, 0x1bff, 0xce03, 0x21, 0 - .dw 0x1c40, 0xce03, 0x1dff, 0xce03, 0x21, 0 - .dw 0x1e40, 0xce03, 0x3fff, 0xce03, 0x21, 0 - .dw 0x4040, 0xce03, 0x41ff, 0xce03, 0x21, 0 - .dw 0x4240, 0xce03, 0x43ff, 0xce03, 0x21, 0 - .dw 0x4440, 0xce03, 0x45ff, 0xce03, 0x21, 0 - .dw 0x4640, 0xce03, 0x47ff, 0xce03, 0x21, 0 - .dw 0x4840, 0xce03, 0x49ff, 0xce03, 0x21, 0 - .dw 0x4a40, 0xce03, 0x4bff, 0xce03, 0x21, 0 - .dw 0x4c40, 0xce03, 0x4dff, 0xce03, 0x21, 0 - .dw 0x4e40, 0xce03, 0x4fff, 0xce03, 0x21, 0 - .dw 0x5040, 0xce03, 0x51ff, 0xce03, 0x21, 0 - .dw 0x5240, 0xce03, 0x53ff, 0xce03, 0x21, 0 - .dw 0x5440, 0xce03, 0x55ff, 0xce03, 0x21, 0 - .dw 0x5640, 0xce03, 0x57ff, 0xce03, 0x21, 0 - .dw 0x5840, 0xce03, 0x59ff, 0xce03, 0x21, 0 - .dw 0x5a40, 0xce03, 0x5bff, 0xce03, 0x21, 0 - .dw 0x5c40, 0xce03, 0x5dff, 0xce03, 0x21, 0 - .dw 0x5e40, 0xce03, 0x7fff, 0xce03, 0x21, 0 - .dw 0x8040, 0xce03, 0x81ff, 0xce03, 0x21, 0 - .dw 0x8240, 0xce03, 0x83ff, 0xce03, 0x21, 0 - .dw 0x8440, 0xce03, 0x85ff, 0xce03, 0x21, 0 - .dw 0x8640, 0xce03, 0x87ff, 0xce03, 0x21, 0 - .dw 0x8840, 0xce03, 0x89ff, 0xce03, 0x21, 0 - .dw 0x8a40, 0xce03, 0x8bff, 0xce03, 0x21, 0 - .dw 0x8c40, 0xce03, 0x8dff, 0xce03, 0x21, 0 - .dw 0x8e40, 0xce03, 0x8fff, 0xce03, 0x21, 0 - .dw 0x9040, 0xce03, 0x91ff, 0xce03, 0x21, 0 - .dw 0x9240, 0xce03, 0x93ff, 0xce03, 0x21, 0 - .dw 0x9440, 0xce03, 0x95ff, 0xce03, 0x21, 0 - .dw 0x9640, 0xce03, 0x97ff, 0xce03, 0x21, 0 - .dw 0x9840, 0xce03, 0x99ff, 0xce03, 0x21, 0 - .dw 0x9a40, 0xce03, 0x9bff, 0xce03, 0x21, 0 - .dw 0x9c40, 0xce03, 0x9dff, 0xce03, 0x21, 0 - .dw 0x9e40, 0xce03, 0xffff, 0xce03, 0x21, 0 - .dw 0x0040, 0xce04, 0x01ff, 0xce04, 0x21, 0 - .dw 0x0240, 0xce04, 0x03ff, 0xce04, 0x21, 0 - .dw 0x0440, 0xce04, 0x05ff, 0xce04, 0x21, 0 - .dw 0x0640, 0xce04, 0x07ff, 0xce04, 0x21, 0 - .dw 0x0840, 0xce04, 0x09ff, 0xce04, 0x21, 0 - .dw 0x0a40, 0xce04, 0x0bff, 0xce04, 0x21, 0 - .dw 0x0c40, 0xce04, 0x0dff, 0xce04, 0x21, 0 - .dw 0x0e40, 0xce04, 0x3fff, 0xce04, 0x21, 0 - .dw 0x4040, 0xce04, 0x41ff, 0xce04, 0x21, 0 - .dw 0x4240, 0xce04, 0x43ff, 0xce04, 0x21, 0 - .dw 0x4440, 0xce04, 0x45ff, 0xce04, 0x21, 0 - .dw 0x4640, 0xce04, 0x47ff, 0xce04, 0x21, 0 - .dw 0x4840, 0xce04, 0x49ff, 0xce04, 0x21, 0 - .dw 0x4a40, 0xce04, 0x4bff, 0xce04, 0x21, 0 - .dw 0x4c40, 0xce04, 0x4dff, 0xce04, 0x21, 0 - .dw 0x4e40, 0xce04, 0x7fff, 0xce04, 0x21, 0 - .dw 0x8040, 0xce04, 0x81ff, 0xce04, 0x21, 0 - .dw 0x8240, 0xce04, 0x83ff, 0xce04, 0x21, 0 - .dw 0x8440, 0xce04, 0x85ff, 0xce04, 0x21, 0 - .dw 0x8640, 0xce04, 0x87ff, 0xce04, 0x21, 0 - .dw 0x8840, 0xce04, 0x89ff, 0xce04, 0x21, 0 - .dw 0x8a40, 0xce04, 0x8bff, 0xce04, 0x21, 0 - .dw 0x8c40, 0xce04, 0x8dff, 0xce04, 0x21, 0 - .dw 0x8e40, 0xce04, 0xbfff, 0xce04, 0x21, 0 - .dw 0xc040, 0xce04, 0xc1ff, 0xce04, 0x21, 0 - .dw 0xc240, 0xce04, 0xc3ff, 0xce04, 0x21, 0 - .dw 0xc440, 0xce04, 0xc5ff, 0xce04, 0x21, 0 - .dw 0xc640, 0xce04, 0xc7ff, 0xce04, 0x21, 0 - .dw 0xc840, 0xce04, 0xc9ff, 0xce04, 0x21, 0 - .dw 0xca40, 0xce04, 0xcbff, 0xce04, 0x21, 0 - .dw 0xcc40, 0xce04, 0xcdff, 0xce04, 0x21, 0 - .dw 0xce40, 0xce04, 0xffff, 0xce04, 0x21, 0 - .dw 0x0040, 0xce05, 0x01ff, 0xce05, 0x21, 0 - .dw 0x0240, 0xce05, 0x03ff, 0xce05, 0x21, 0 - .dw 0x0440, 0xce05, 0x05ff, 0xce05, 0x21, 0 - .dw 0x0640, 0xce05, 0x07ff, 0xce05, 0x21, 0 - .dw 0x0840, 0xce05, 0x09ff, 0xce05, 0x21, 0 - .dw 0x0a40, 0xce05, 0x0bff, 0xce05, 0x21, 0 - .dw 0x0c40, 0xce05, 0x0dff, 0xce05, 0x21, 0 - .dw 0x0e40, 0xce05, 0x3fff, 0xce05, 0x21, 0 - .dw 0x4040, 0xce05, 0x41ff, 0xce05, 0x21, 0 - .dw 0x4240, 0xce05, 0x43ff, 0xce05, 0x21, 0 - .dw 0x4440, 0xce05, 0x45ff, 0xce05, 0x21, 0 - .dw 0x4640, 0xce05, 0x47ff, 0xce05, 0x21, 0 - .dw 0x4840, 0xce05, 0x49ff, 0xce05, 0x21, 0 - .dw 0x4a40, 0xce05, 0x4bff, 0xce05, 0x21, 0 - .dw 0x4c40, 0xce05, 0x4dff, 0xce05, 0x21, 0 - .dw 0x4e40, 0xce05, 0x7fff, 0xce05, 0x21, 0 - .dw 0x8040, 0xce05, 0x81ff, 0xce05, 0x21, 0 - .dw 0x8240, 0xce05, 0x83ff, 0xce05, 0x21, 0 - .dw 0x8440, 0xce05, 0x85ff, 0xce05, 0x21, 0 - .dw 0x8640, 0xce05, 0x87ff, 0xce05, 0x21, 0 - .dw 0x8840, 0xce05, 0x89ff, 0xce05, 0x21, 0 - .dw 0x8a40, 0xce05, 0x8bff, 0xce05, 0x21, 0 - .dw 0x8c40, 0xce05, 0x8dff, 0xce05, 0x21, 0 - .dw 0x8e40, 0xce05, 0xffff, 0xce05, 0x21, 0 - .dw 0x0040, 0xce06, 0x01ff, 0xce06, 0x21, 0 - .dw 0x0240, 0xce06, 0x03ff, 0xce06, 0x21, 0 - .dw 0x0440, 0xce06, 0x05ff, 0xce06, 0x21, 0 - .dw 0x0640, 0xce06, 0x07ff, 0xce06, 0x21, 0 - .dw 0x0840, 0xce06, 0x09ff, 0xce06, 0x21, 0 - .dw 0x0a40, 0xce06, 0x0bff, 0xce06, 0x21, 0 - .dw 0x0c40, 0xce06, 0x0dff, 0xce06, 0x21, 0 - .dw 0x0e40, 0xce06, 0x3fff, 0xce06, 0x21, 0 - .dw 0x4040, 0xce06, 0x41ff, 0xce06, 0x21, 0 - .dw 0x4240, 0xce06, 0x43ff, 0xce06, 0x21, 0 - .dw 0x4440, 0xce06, 0x45ff, 0xce06, 0x21, 0 - .dw 0x4640, 0xce06, 0x47ff, 0xce06, 0x21, 0 - .dw 0x4840, 0xce06, 0x49ff, 0xce06, 0x21, 0 - .dw 0x4a40, 0xce06, 0x4bff, 0xce06, 0x21, 0 - .dw 0x4c40, 0xce06, 0x4dff, 0xce06, 0x21, 0 - .dw 0x4e40, 0xce06, 0xbfff, 0xce06, 0x21, 0 - .dw 0xc040, 0xce06, 0xc1ff, 0xce06, 0x21, 0 - .dw 0xc240, 0xce06, 0xc3ff, 0xce06, 0x21, 0 - .dw 0xc440, 0xce06, 0xc5ff, 0xce06, 0x21, 0 - .dw 0xc640, 0xce06, 0xc7ff, 0xce06, 0x21, 0 - .dw 0xc840, 0xce06, 0xc9ff, 0xce06, 0x21, 0 - .dw 0xca40, 0xce06, 0xcbff, 0xce06, 0x21, 0 - .dw 0xcc40, 0xce06, 0xcdff, 0xce06, 0x21, 0 - .dw 0xce40, 0xce06, 0xffff, 0xce06, 0x21, 0 - .dw 0x0040, 0xce07, 0x01ff, 0xce07, 0x21, 0 - .dw 0x0240, 0xce07, 0x03ff, 0xce07, 0x21, 0 - .dw 0x0440, 0xce07, 0x05ff, 0xce07, 0x21, 0 - .dw 0x0640, 0xce07, 0x07ff, 0xce07, 0x21, 0 - .dw 0x0840, 0xce07, 0x09ff, 0xce07, 0x21, 0 - .dw 0x0a40, 0xce07, 0x0bff, 0xce07, 0x21, 0 - .dw 0x0c40, 0xce07, 0x0dff, 0xce07, 0x21, 0 - .dw 0x0e40, 0xce07, 0x3fff, 0xce07, 0x21, 0 - .dw 0x4040, 0xce07, 0x41ff, 0xce07, 0x21, 0 - .dw 0x4240, 0xce07, 0x43ff, 0xce07, 0x21, 0 - .dw 0x4440, 0xce07, 0x45ff, 0xce07, 0x21, 0 - .dw 0x4640, 0xce07, 0x47ff, 0xce07, 0x21, 0 - .dw 0x4840, 0xce07, 0x49ff, 0xce07, 0x21, 0 - .dw 0x4a40, 0xce07, 0x4bff, 0xce07, 0x21, 0 - .dw 0x4c40, 0xce07, 0x4dff, 0xce07, 0x21, 0 - .dw 0x4e40, 0xce07, 0x7fff, 0xce07, 0x21, 0 - .dw 0x8040, 0xce07, 0x81ff, 0xce07, 0x21, 0 - .dw 0x8240, 0xce07, 0x83ff, 0xce07, 0x21, 0 - .dw 0x8440, 0xce07, 0x85ff, 0xce07, 0x21, 0 - .dw 0x8640, 0xce07, 0x87ff, 0xce07, 0x21, 0 - .dw 0x8840, 0xce07, 0x89ff, 0xce07, 0x21, 0 - .dw 0x8a40, 0xce07, 0x8bff, 0xce07, 0x21, 0 - .dw 0x8c40, 0xce07, 0x8dff, 0xce07, 0x21, 0 - .dw 0x8e40, 0xce07, 0xbfff, 0xce07, 0x21, 0 - .dw 0xc040, 0xce07, 0xc1ff, 0xce07, 0x21, 0 - .dw 0xc240, 0xce07, 0xc3ff, 0xce07, 0x21, 0 - .dw 0xc440, 0xce07, 0xc5ff, 0xce07, 0x21, 0 - .dw 0xc640, 0xce07, 0xc7ff, 0xce07, 0x21, 0 - .dw 0xc840, 0xce07, 0xc9ff, 0xce07, 0x21, 0 - .dw 0xca40, 0xce07, 0xcbff, 0xce07, 0x21, 0 - .dw 0xcc40, 0xce07, 0xcdff, 0xce07, 0x21, 0 - .dw 0xce40, 0xce07, 0xffff, 0xce07, 0x21, 0 - .dw 0x0000, 0xce08, 0x0000, 0xce08, 0x22, 0 - .dw 0x0009, 0xce08, 0x0009, 0xce08, 0x22, 0 - .dw 0x0012, 0xce08, 0x0012, 0xce08, 0x22, 0 - .dw 0x001b, 0xce08, 0x001b, 0xce08, 0x22, 0 - .dw 0x0024, 0xce08, 0x0024, 0xce08, 0x22, 0 - .dw 0x002d, 0xce08, 0x002d, 0xce08, 0x22, 0 - .dw 0x0036, 0xce08, 0x0036, 0xce08, 0x22, 0 - .dw 0x003f, 0xce08, 0x003f, 0xce08, 0x22, 0 - .dw 0x0040, 0xce08, 0x01ff, 0xce08, 0x21, 0 - .dw 0x0200, 0xce08, 0x0200, 0xce08, 0x22, 0 - .dw 0x0209, 0xce08, 0x0209, 0xce08, 0x22, 0 - .dw 0x0212, 0xce08, 0x0212, 0xce08, 0x22, 0 - .dw 0x021b, 0xce08, 0x021b, 0xce08, 0x22, 0 - .dw 0x0224, 0xce08, 0x0224, 0xce08, 0x22, 0 - .dw 0x022d, 0xce08, 0x022d, 0xce08, 0x22, 0 - .dw 0x0236, 0xce08, 0x0236, 0xce08, 0x22, 0 - .dw 0x023f, 0xce08, 0x023f, 0xce08, 0x22, 0 - .dw 0x0240, 0xce08, 0x03ff, 0xce08, 0x21, 0 - .dw 0x0400, 0xce08, 0x0400, 0xce08, 0x22, 0 - .dw 0x0409, 0xce08, 0x0409, 0xce08, 0x22, 0 - .dw 0x0412, 0xce08, 0x0412, 0xce08, 0x22, 0 - .dw 0x041b, 0xce08, 0x041b, 0xce08, 0x22, 0 - .dw 0x0424, 0xce08, 0x0424, 0xce08, 0x22, 0 - .dw 0x042d, 0xce08, 0x042d, 0xce08, 0x22, 0 - .dw 0x0436, 0xce08, 0x0436, 0xce08, 0x22, 0 - .dw 0x043f, 0xce08, 0x043f, 0xce08, 0x22, 0 - .dw 0x0440, 0xce08, 0x05ff, 0xce08, 0x21, 0 - .dw 0x0600, 0xce08, 0x0600, 0xce08, 0x22, 0 - .dw 0x0609, 0xce08, 0x0609, 0xce08, 0x22, 0 - .dw 0x0612, 0xce08, 0x0612, 0xce08, 0x22, 0 - .dw 0x061b, 0xce08, 0x061b, 0xce08, 0x22, 0 - .dw 0x0624, 0xce08, 0x0624, 0xce08, 0x22, 0 - .dw 0x062d, 0xce08, 0x062d, 0xce08, 0x22, 0 - .dw 0x0636, 0xce08, 0x0636, 0xce08, 0x22, 0 - .dw 0x063f, 0xce08, 0x063f, 0xce08, 0x22, 0 - .dw 0x0640, 0xce08, 0x07ff, 0xce08, 0x21, 0 - .dw 0x0800, 0xce08, 0x0800, 0xce08, 0x22, 0 - .dw 0x0809, 0xce08, 0x0809, 0xce08, 0x22, 0 - .dw 0x0812, 0xce08, 0x0812, 0xce08, 0x22, 0 - .dw 0x081b, 0xce08, 0x081b, 0xce08, 0x22, 0 - .dw 0x0824, 0xce08, 0x0824, 0xce08, 0x22, 0 - .dw 0x082d, 0xce08, 0x082d, 0xce08, 0x22, 0 - .dw 0x0836, 0xce08, 0x0836, 0xce08, 0x22, 0 - .dw 0x083f, 0xce08, 0x083f, 0xce08, 0x22, 0 - .dw 0x0840, 0xce08, 0x09ff, 0xce08, 0x21, 0 - .dw 0x0a00, 0xce08, 0x0a00, 0xce08, 0x22, 0 - .dw 0x0a09, 0xce08, 0x0a09, 0xce08, 0x22, 0 - .dw 0x0a12, 0xce08, 0x0a12, 0xce08, 0x22, 0 - .dw 0x0a1b, 0xce08, 0x0a1b, 0xce08, 0x22, 0 - .dw 0x0a24, 0xce08, 0x0a24, 0xce08, 0x22, 0 - .dw 0x0a2d, 0xce08, 0x0a2d, 0xce08, 0x22, 0 - .dw 0x0a36, 0xce08, 0x0a36, 0xce08, 0x22, 0 - .dw 0x0a3f, 0xce08, 0x0a3f, 0xce08, 0x22, 0 - .dw 0x0a40, 0xce08, 0x0bff, 0xce08, 0x21, 0 - .dw 0x0c00, 0xce08, 0x0c00, 0xce08, 0x22, 0 - .dw 0x0c09, 0xce08, 0x0c09, 0xce08, 0x22, 0 - .dw 0x0c12, 0xce08, 0x0c12, 0xce08, 0x22, 0 - .dw 0x0c1b, 0xce08, 0x0c1b, 0xce08, 0x22, 0 - .dw 0x0c24, 0xce08, 0x0c24, 0xce08, 0x22, 0 - .dw 0x0c2d, 0xce08, 0x0c2d, 0xce08, 0x22, 0 - .dw 0x0c36, 0xce08, 0x0c36, 0xce08, 0x22, 0 - .dw 0x0c3f, 0xce08, 0x0c3f, 0xce08, 0x22, 0 - .dw 0x0c40, 0xce08, 0x0dff, 0xce08, 0x21, 0 - .dw 0x0e00, 0xce08, 0x0e00, 0xce08, 0x22, 0 - .dw 0x0e09, 0xce08, 0x0e09, 0xce08, 0x22, 0 - .dw 0x0e12, 0xce08, 0x0e12, 0xce08, 0x22, 0 - .dw 0x0e1b, 0xce08, 0x0e1b, 0xce08, 0x22, 0 - .dw 0x0e24, 0xce08, 0x0e24, 0xce08, 0x22, 0 - .dw 0x0e2d, 0xce08, 0x0e2d, 0xce08, 0x22, 0 - .dw 0x0e36, 0xce08, 0x0e36, 0xce08, 0x22, 0 - .dw 0x0e3f, 0xce08, 0x0e3f, 0xce08, 0x22, 0 - .dw 0x0e40, 0xce08, 0x3fff, 0xce08, 0x21, 0 - .dw 0x4000, 0xce08, 0x4000, 0xce08, 0x22, 0 - .dw 0x4009, 0xce08, 0x4009, 0xce08, 0x22, 0 - .dw 0x4012, 0xce08, 0x4012, 0xce08, 0x22, 0 - .dw 0x401b, 0xce08, 0x401b, 0xce08, 0x22, 0 - .dw 0x4024, 0xce08, 0x4024, 0xce08, 0x22, 0 - .dw 0x402d, 0xce08, 0x402d, 0xce08, 0x22, 0 - .dw 0x4036, 0xce08, 0x4036, 0xce08, 0x22, 0 - .dw 0x403f, 0xce08, 0x403f, 0xce08, 0x22, 0 - .dw 0x4040, 0xce08, 0x41ff, 0xce08, 0x21, 0 - .dw 0x4200, 0xce08, 0x4200, 0xce08, 0x22, 0 - .dw 0x4209, 0xce08, 0x4209, 0xce08, 0x22, 0 - .dw 0x4212, 0xce08, 0x4212, 0xce08, 0x22, 0 - .dw 0x421b, 0xce08, 0x421b, 0xce08, 0x22, 0 - .dw 0x4224, 0xce08, 0x4224, 0xce08, 0x22, 0 - .dw 0x422d, 0xce08, 0x422d, 0xce08, 0x22, 0 - .dw 0x4236, 0xce08, 0x4236, 0xce08, 0x22, 0 - .dw 0x423f, 0xce08, 0x423f, 0xce08, 0x22, 0 - .dw 0x4240, 0xce08, 0x43ff, 0xce08, 0x21, 0 - .dw 0x4400, 0xce08, 0x4400, 0xce08, 0x22, 0 - .dw 0x4409, 0xce08, 0x4409, 0xce08, 0x22, 0 - .dw 0x4412, 0xce08, 0x4412, 0xce08, 0x22, 0 - .dw 0x441b, 0xce08, 0x441b, 0xce08, 0x22, 0 - .dw 0x4424, 0xce08, 0x4424, 0xce08, 0x22, 0 - .dw 0x442d, 0xce08, 0x442d, 0xce08, 0x22, 0 - .dw 0x4436, 0xce08, 0x4436, 0xce08, 0x22, 0 - .dw 0x443f, 0xce08, 0x443f, 0xce08, 0x22, 0 - .dw 0x4440, 0xce08, 0x45ff, 0xce08, 0x21, 0 - .dw 0x4600, 0xce08, 0x4600, 0xce08, 0x22, 0 - .dw 0x4609, 0xce08, 0x4609, 0xce08, 0x22, 0 - .dw 0x4612, 0xce08, 0x4612, 0xce08, 0x22, 0 - .dw 0x461b, 0xce08, 0x461b, 0xce08, 0x22, 0 - .dw 0x4624, 0xce08, 0x4624, 0xce08, 0x22, 0 - .dw 0x462d, 0xce08, 0x462d, 0xce08, 0x22, 0 - .dw 0x4636, 0xce08, 0x4636, 0xce08, 0x22, 0 - .dw 0x463f, 0xce08, 0x463f, 0xce08, 0x22, 0 - .dw 0x4640, 0xce08, 0x47ff, 0xce08, 0x21, 0 - .dw 0x4800, 0xce08, 0x4800, 0xce08, 0x22, 0 - .dw 0x4809, 0xce08, 0x4809, 0xce08, 0x22, 0 - .dw 0x4812, 0xce08, 0x4812, 0xce08, 0x22, 0 - .dw 0x481b, 0xce08, 0x481b, 0xce08, 0x22, 0 - .dw 0x4824, 0xce08, 0x4824, 0xce08, 0x22, 0 - .dw 0x482d, 0xce08, 0x482d, 0xce08, 0x22, 0 - .dw 0x4836, 0xce08, 0x4836, 0xce08, 0x22, 0 - .dw 0x483f, 0xce08, 0x483f, 0xce08, 0x22, 0 - .dw 0x4840, 0xce08, 0x49ff, 0xce08, 0x21, 0 - .dw 0x4a00, 0xce08, 0x4a00, 0xce08, 0x22, 0 - .dw 0x4a09, 0xce08, 0x4a09, 0xce08, 0x22, 0 - .dw 0x4a12, 0xce08, 0x4a12, 0xce08, 0x22, 0 - .dw 0x4a1b, 0xce08, 0x4a1b, 0xce08, 0x22, 0 - .dw 0x4a24, 0xce08, 0x4a24, 0xce08, 0x22, 0 - .dw 0x4a2d, 0xce08, 0x4a2d, 0xce08, 0x22, 0 - .dw 0x4a36, 0xce08, 0x4a36, 0xce08, 0x22, 0 - .dw 0x4a3f, 0xce08, 0x4a3f, 0xce08, 0x22, 0 - .dw 0x4a40, 0xce08, 0x4bff, 0xce08, 0x21, 0 - .dw 0x4c00, 0xce08, 0x4c00, 0xce08, 0x22, 0 - .dw 0x4c09, 0xce08, 0x4c09, 0xce08, 0x22, 0 - .dw 0x4c12, 0xce08, 0x4c12, 0xce08, 0x22, 0 - .dw 0x4c1b, 0xce08, 0x4c1b, 0xce08, 0x22, 0 - .dw 0x4c24, 0xce08, 0x4c24, 0xce08, 0x22, 0 - .dw 0x4c2d, 0xce08, 0x4c2d, 0xce08, 0x22, 0 - .dw 0x4c36, 0xce08, 0x4c36, 0xce08, 0x22, 0 - .dw 0x4c3f, 0xce08, 0x4c3f, 0xce08, 0x22, 0 - .dw 0x4c40, 0xce08, 0x4dff, 0xce08, 0x21, 0 - .dw 0x4e00, 0xce08, 0x4e00, 0xce08, 0x22, 0 - .dw 0x4e09, 0xce08, 0x4e09, 0xce08, 0x22, 0 - .dw 0x4e12, 0xce08, 0x4e12, 0xce08, 0x22, 0 - .dw 0x4e1b, 0xce08, 0x4e1b, 0xce08, 0x22, 0 - .dw 0x4e24, 0xce08, 0x4e24, 0xce08, 0x22, 0 - .dw 0x4e2d, 0xce08, 0x4e2d, 0xce08, 0x22, 0 - .dw 0x4e36, 0xce08, 0x4e36, 0xce08, 0x22, 0 - .dw 0x4e3f, 0xce08, 0x4e3f, 0xce08, 0x22, 0 - .dw 0x4e40, 0xce08, 0xffff, 0xce08, 0x21, 0 - .dw 0x0040, 0xce09, 0x01ff, 0xce09, 0x21, 0 - .dw 0x0240, 0xce09, 0x03ff, 0xce09, 0x21, 0 - .dw 0x0440, 0xce09, 0x05ff, 0xce09, 0x21, 0 - .dw 0x0640, 0xce09, 0x07ff, 0xce09, 0x21, 0 - .dw 0x0840, 0xce09, 0x09ff, 0xce09, 0x21, 0 - .dw 0x0a40, 0xce09, 0x0bff, 0xce09, 0x21, 0 - .dw 0x0c40, 0xce09, 0x0dff, 0xce09, 0x21, 0 - .dw 0x0e40, 0xce09, 0x3fff, 0xce09, 0x21, 0 - .dw 0x4040, 0xce09, 0x41ff, 0xce09, 0x21, 0 - .dw 0x4240, 0xce09, 0x43ff, 0xce09, 0x21, 0 - .dw 0x4440, 0xce09, 0x45ff, 0xce09, 0x21, 0 - .dw 0x4640, 0xce09, 0x47ff, 0xce09, 0x21, 0 - .dw 0x4840, 0xce09, 0x49ff, 0xce09, 0x21, 0 - .dw 0x4a40, 0xce09, 0x4bff, 0xce09, 0x21, 0 - .dw 0x4c40, 0xce09, 0x4dff, 0xce09, 0x21, 0 - .dw 0x4e40, 0xce09, 0x7fff, 0xce09, 0x21, 0 - .dw 0x8040, 0xce09, 0x81ff, 0xce09, 0x21, 0 - .dw 0x8240, 0xce09, 0x83ff, 0xce09, 0x21, 0 - .dw 0x8440, 0xce09, 0x85ff, 0xce09, 0x21, 0 - .dw 0x8640, 0xce09, 0x87ff, 0xce09, 0x21, 0 - .dw 0x8840, 0xce09, 0x89ff, 0xce09, 0x21, 0 - .dw 0x8a40, 0xce09, 0x8bff, 0xce09, 0x21, 0 - .dw 0x8c40, 0xce09, 0x8dff, 0xce09, 0x21, 0 - .dw 0x8e40, 0xce09, 0xbfff, 0xce09, 0x21, 0 - .dw 0xc040, 0xce09, 0xc1ff, 0xce09, 0x21, 0 - .dw 0xc240, 0xce09, 0xc3ff, 0xce09, 0x21, 0 - .dw 0xc440, 0xce09, 0xc5ff, 0xce09, 0x21, 0 - .dw 0xc640, 0xce09, 0xc7ff, 0xce09, 0x21, 0 - .dw 0xc840, 0xce09, 0xc9ff, 0xce09, 0x21, 0 - .dw 0xca40, 0xce09, 0xcbff, 0xce09, 0x21, 0 - .dw 0xcc40, 0xce09, 0xcdff, 0xce09, 0x21, 0 - .dw 0xce40, 0xce09, 0xffff, 0xce09, 0x21, 0 - .dw 0x0040, 0xce0a, 0x01ff, 0xce0a, 0x21, 0 - .dw 0x0240, 0xce0a, 0x03ff, 0xce0a, 0x21, 0 - .dw 0x0440, 0xce0a, 0x05ff, 0xce0a, 0x21, 0 - .dw 0x0640, 0xce0a, 0x07ff, 0xce0a, 0x21, 0 - .dw 0x0840, 0xce0a, 0x09ff, 0xce0a, 0x21, 0 - .dw 0x0a40, 0xce0a, 0x0bff, 0xce0a, 0x21, 0 - .dw 0x0c40, 0xce0a, 0x0dff, 0xce0a, 0x21, 0 - .dw 0x0e40, 0xce0a, 0x3fff, 0xce0a, 0x21, 0 - .dw 0x4040, 0xce0a, 0x41ff, 0xce0a, 0x21, 0 - .dw 0x4240, 0xce0a, 0x43ff, 0xce0a, 0x21, 0 - .dw 0x4440, 0xce0a, 0x45ff, 0xce0a, 0x21, 0 - .dw 0x4640, 0xce0a, 0x47ff, 0xce0a, 0x21, 0 - .dw 0x4840, 0xce0a, 0x49ff, 0xce0a, 0x21, 0 - .dw 0x4a40, 0xce0a, 0x4bff, 0xce0a, 0x21, 0 - .dw 0x4c40, 0xce0a, 0x4dff, 0xce0a, 0x21, 0 - .dw 0x4e40, 0xce0a, 0x7fff, 0xce0a, 0x21, 0 - .dw 0x8040, 0xce0a, 0x81ff, 0xce0a, 0x21, 0 - .dw 0x8240, 0xce0a, 0x83ff, 0xce0a, 0x21, 0 - .dw 0x8440, 0xce0a, 0x85ff, 0xce0a, 0x21, 0 - .dw 0x8640, 0xce0a, 0x87ff, 0xce0a, 0x21, 0 - .dw 0x8840, 0xce0a, 0x89ff, 0xce0a, 0x21, 0 - .dw 0x8a40, 0xce0a, 0x8bff, 0xce0a, 0x21, 0 - .dw 0x8c40, 0xce0a, 0x8dff, 0xce0a, 0x21, 0 - .dw 0x8e40, 0xce0a, 0xbfff, 0xce0a, 0x21, 0 - .dw 0xc040, 0xce0a, 0xc1ff, 0xce0a, 0x21, 0 - .dw 0xc240, 0xce0a, 0xc3ff, 0xce0a, 0x21, 0 - .dw 0xc440, 0xce0a, 0xc5ff, 0xce0a, 0x21, 0 - .dw 0xc640, 0xce0a, 0xc7ff, 0xce0a, 0x21, 0 - .dw 0xc840, 0xce0a, 0xc9ff, 0xce0a, 0x21, 0 - .dw 0xca40, 0xce0a, 0xcbff, 0xce0a, 0x21, 0 - .dw 0xcc40, 0xce0a, 0xcdff, 0xce0a, 0x21, 0 - .dw 0xce40, 0xce0a, 0xffff, 0xce0a, 0x21, 0 - .dw 0x0040, 0xce0b, 0x01ff, 0xce0b, 0x21, 0 - .dw 0x0240, 0xce0b, 0x03ff, 0xce0b, 0x21, 0 - .dw 0x0440, 0xce0b, 0x05ff, 0xce0b, 0x21, 0 - .dw 0x0640, 0xce0b, 0x07ff, 0xce0b, 0x21, 0 - .dw 0x0840, 0xce0b, 0x09ff, 0xce0b, 0x21, 0 - .dw 0x0a40, 0xce0b, 0x0bff, 0xce0b, 0x21, 0 - .dw 0x0c40, 0xce0b, 0x0dff, 0xce0b, 0x21, 0 - .dw 0x0e40, 0xce0b, 0x3fff, 0xce0b, 0x21, 0 - .dw 0x4040, 0xce0b, 0x41ff, 0xce0b, 0x21, 0 - .dw 0x4240, 0xce0b, 0x43ff, 0xce0b, 0x21, 0 - .dw 0x4440, 0xce0b, 0x45ff, 0xce0b, 0x21, 0 - .dw 0x4640, 0xce0b, 0x47ff, 0xce0b, 0x21, 0 - .dw 0x4840, 0xce0b, 0x49ff, 0xce0b, 0x21, 0 - .dw 0x4a40, 0xce0b, 0x4bff, 0xce0b, 0x21, 0 - .dw 0x4c40, 0xce0b, 0x4dff, 0xce0b, 0x21, 0 - .dw 0x4e40, 0xce0b, 0xffff, 0xce0b, 0x21, 0 - .dw 0x0040, 0xce0c, 0x01ff, 0xce0c, 0x21, 0 - .dw 0x0240, 0xce0c, 0x03ff, 0xce0c, 0x21, 0 - .dw 0x0440, 0xce0c, 0x05ff, 0xce0c, 0x21, 0 - .dw 0x0640, 0xce0c, 0x07ff, 0xce0c, 0x21, 0 - .dw 0x0840, 0xce0c, 0x09ff, 0xce0c, 0x21, 0 - .dw 0x0a40, 0xce0c, 0x0bff, 0xce0c, 0x21, 0 - .dw 0x0c40, 0xce0c, 0x0dff, 0xce0c, 0x21, 0 - .dw 0x0e40, 0xce0c, 0x3fff, 0xce0c, 0x21, 0 - .dw 0x4040, 0xce0c, 0x41ff, 0xce0c, 0x21, 0 - .dw 0x4240, 0xce0c, 0x43ff, 0xce0c, 0x21, 0 - .dw 0x4440, 0xce0c, 0x45ff, 0xce0c, 0x21, 0 - .dw 0x4640, 0xce0c, 0x47ff, 0xce0c, 0x21, 0 - .dw 0x4840, 0xce0c, 0x49ff, 0xce0c, 0x21, 0 - .dw 0x4a40, 0xce0c, 0x4bff, 0xce0c, 0x21, 0 - .dw 0x4c40, 0xce0c, 0x4dff, 0xce0c, 0x21, 0 - .dw 0x4e40, 0xce0c, 0xffff, 0xce0c, 0x21, 0 - .dw 0x0040, 0xce0d, 0x01ff, 0xce0d, 0x21, 0 - .dw 0x0240, 0xce0d, 0x03ff, 0xce0d, 0x21, 0 - .dw 0x0440, 0xce0d, 0x05ff, 0xce0d, 0x21, 0 - .dw 0x0640, 0xce0d, 0x07ff, 0xce0d, 0x21, 0 - .dw 0x0840, 0xce0d, 0x09ff, 0xce0d, 0x21, 0 - .dw 0x0a40, 0xce0d, 0x0bff, 0xce0d, 0x21, 0 - .dw 0x0c40, 0xce0d, 0x0dff, 0xce0d, 0x21, 0 - .dw 0x0e40, 0xce0d, 0x3fff, 0xce0d, 0x21, 0 - .dw 0x4040, 0xce0d, 0x41ff, 0xce0d, 0x21, 0 - .dw 0x4240, 0xce0d, 0x43ff, 0xce0d, 0x21, 0 - .dw 0x4440, 0xce0d, 0x45ff, 0xce0d, 0x21, 0 - .dw 0x4640, 0xce0d, 0x47ff, 0xce0d, 0x21, 0 - .dw 0x4840, 0xce0d, 0x49ff, 0xce0d, 0x21, 0 - .dw 0x4a40, 0xce0d, 0x4bff, 0xce0d, 0x21, 0 - .dw 0x4c40, 0xce0d, 0x4dff, 0xce0d, 0x21, 0 - .dw 0x4e40, 0xce0d, 0x7fff, 0xce0d, 0x21, 0 - .dw 0x8040, 0xce0d, 0x81ff, 0xce0d, 0x21, 0 - .dw 0x8240, 0xce0d, 0x83ff, 0xce0d, 0x21, 0 - .dw 0x8440, 0xce0d, 0x85ff, 0xce0d, 0x21, 0 - .dw 0x8640, 0xce0d, 0x87ff, 0xce0d, 0x21, 0 - .dw 0x8840, 0xce0d, 0x89ff, 0xce0d, 0x21, 0 - .dw 0x8a40, 0xce0d, 0x8bff, 0xce0d, 0x21, 0 - .dw 0x8c40, 0xce0d, 0x8dff, 0xce0d, 0x21, 0 - .dw 0x8e40, 0xce0d, 0xffff, 0xce7f, 0x21, 0 - .dw 0xc000, 0xce80, 0xffff, 0xce80, 0x21, 0 - .dw 0x1000, 0xce81, 0x3fff, 0xce81, 0x21, 0 - .dw 0x5000, 0xce81, 0x7fff, 0xce81, 0x21, 0 - .dw 0x9000, 0xce81, 0xffff, 0xce81, 0x21, 0 - .dw 0x1000, 0xce82, 0x3fff, 0xce82, 0x21, 0 - .dw 0x5000, 0xce82, 0x7fff, 0xce82, 0x21, 0 - .dw 0x9000, 0xce82, 0xbfff, 0xce82, 0x21, 0 - .dw 0xd000, 0xce82, 0xffff, 0xce82, 0x21, 0 - .dw 0x2000, 0xce83, 0x3fff, 0xce83, 0x21, 0 - .dw 0x6000, 0xce83, 0x7fff, 0xce83, 0x21, 0 - .dw 0xa000, 0xce83, 0xffff, 0xffff, 0x21, 0 - .dw 0x0000, 0x0000, 0x0000, 0x0000, 0x00, 0 -.endm - - se_all_test diff --git a/sim/testsuite/sim/bfin/se_all64bitg1opcodes.S b/sim/testsuite/sim/bfin/se_all64bitg1opcodes.S deleted file mode 100644 index aae10f0..0000000 --- a/sim/testsuite/sim/bfin/se_all64bitg1opcodes.S +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Blackfin testcase for testing illegal/legal 64-bit opcodes (group 1) - * from userspace. we track all instructions which cause some sort of - * exception when run from userspace, this is normally EXCAUSE : - * - 0x22 : illegal instruction combination - * and walk every instruction from 0x0000 to 0xffff - */ - -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - -#define SE_ALL_BITS 16 -#include "se_allopcodes.h" - -.macro se_all_load_insn - R2 = W[P5 + 4]; - R0 = R2; -.endm - -.macro se_all_next_insn - /* increment, and go again. */ - R0 = R2; - - R0 += 1; - /* finish once we hit the 32bit limit */ - imm32 R1, 0x10000; - CC = R1 == R0; - IF CC JUMP pass_lvl; - - W[P5 + 4] = R0; -.endm - -.macro se_all_insn_init - MNOP || NOP || NOP; -.endm -.macro se_all_insn_table - /* this table must be sorted, and end with zero */ - /* start end SEQSTAT */ - .dw 0x0001, 0x7fff, 0x22 - .dw 0x9040, 0x9040, 0x22 - .dw 0x9049, 0x9049, 0x22 - .dw 0x9052, 0x9052, 0x22 - .dw 0x905b, 0x905b, 0x22 - .dw 0x9064, 0x9064, 0x22 - .dw 0x906d, 0x906d, 0x22 - .dw 0x9076, 0x9076, 0x22 - .dw 0x907f, 0x907f, 0x22 - .dw 0x90c0, 0x90c0, 0x22 - .dw 0x90c9, 0x90c9, 0x22 - .dw 0x90d2, 0x90d2, 0x22 - .dw 0x90db, 0x90db, 0x22 - .dw 0x90e4, 0x90e4, 0x22 - .dw 0x90ed, 0x90ed, 0x22 - .dw 0x90f6, 0x90f6, 0x22 - .dw 0x90ff, 0x90ff, 0x22 - .dw 0x9180, 0x91ff, 0x22 - .dw 0x9380, 0x93ff, 0x22 - .dw 0x9580, 0x95ff, 0x22 - .dw 0x9640, 0x967f, 0x22 - .dw 0x96c0, 0x96ff, 0x22 - .dw 0x9740, 0x97ff, 0x22 - .dw 0x9980, 0x99ff, 0x22 - .dw 0x9a40, 0x9a7f, 0x22 - .dw 0x9ac0, 0x9aff, 0x22 - .dw 0x9b40, 0x9bff, 0x22 - .dw 0x9c60, 0x9c7f, 0x22 - .dw 0x9ce0, 0x9cff, 0x22 - .dw 0x9d60, 0x9d7f, 0x22 - .dw 0x9ef0, 0x9eff, 0x22 - .dw 0x9f70, 0x9f7f, 0x22 - .dw 0xc000, 0xffff, 0x22 - .dw 0x0000, 0x0000, 0x00 -.endm - - se_all_test diff --git a/sim/testsuite/sim/bfin/se_all64bitg2opcodes.S b/sim/testsuite/sim/bfin/se_all64bitg2opcodes.S deleted file mode 100644 index 99de3ac..0000000 --- a/sim/testsuite/sim/bfin/se_all64bitg2opcodes.S +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Blackfin testcase for testing illegal/legal 64-bit opcodes (group 2) - * from userspace. we track all instructions which cause some sort of - * exception when run from userspace, this is normally EXCAUSE : - * - 0x22 : illegal instruction combination - * and walk every instruction from 0x0000 to 0xffff - */ - -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - -#define SE_ALL_BITS 16 -#include "se_allopcodes.h" - -.macro se_all_load_insn - R2 = W[P5 + 6]; - R0 = R2; -.endm - -.macro se_all_next_insn - /* increment, and go again. */ - R0 = R2; - - R0 += 1; - /* finish once we hit the 32bit limit */ - imm32 R1, 0x10000; - CC = R1 == R0; - IF CC JUMP pass_lvl; - - W[P5 + 6] = R0; -.endm - -.macro se_all_insn_init - MNOP || NOP || NOP; -.endm -.macro se_all_insn_table - /* this table must be sorted, and end with zero */ - /* start end SEQSTAT */ - .dw 0x0001, 0x9bff, 0x22 - .dw 0x9c60, 0x9c7f, 0x22 - .dw 0x9ce0, 0x9cff, 0x22 - .dw 0x9d60, 0x9d7f, 0x22 - .dw 0x9e60, 0x9e7f, 0x22 - .dw 0x9ee0, 0x9eff, 0x22 - .dw 0x9f60, 0x9f7f, 0x22 - .dw 0xa000, 0xffff, 0x22 - .dw 0x0000, 0x0000, 0x00 -.endm - - se_all_test diff --git a/sim/testsuite/sim/bfin/se_allopcodes.h b/sim/testsuite/sim/bfin/se_allopcodes.h deleted file mode 100644 index 796d5c4..0000000 --- a/sim/testsuite/sim/bfin/se_allopcodes.h +++ /dev/null @@ -1,239 +0,0 @@ -/* - * set up pointers to valid data (32Meg), to reduce address violations - */ -.macro reset_dags - imm32 r0, 0x2000000; - l0 = 0; l1 = 0; l2 = 0; l3 = 0; - p0 = r0; p1 = r0; p2 = r0; p3 = r0; p4 = r0; p5 = r0; - usp = r0; fp = r0; - i0 = r0; i1 = r0; i2 = r0; i3 = r0; - b0 = r0; b1 = r0; b2 = r0; b3 = r0; -.endm - -#if SE_ALL_BITS == 32 -# define LOAD_PFX -#elif SE_ALL_BITS == 16 -# define LOAD_PFX W -#else -# error "Please define SE_ALL_BITS" -#endif - -/* - * execute a test of an opcode space. host test - * has to fill out a number of callbacks. - * - * se_all_insn_init - * the first insn to start executing - * se_all_insn_table - * the table of insn ranges and expected seqstat - * - * se_all_load_insn - * in: P5 - * out: R0, R2 - * scratch: R1 - * load current user insn via register P5 into R0. - * register R2 is available for caching with se_all_next_insn. - * se_all_load_table - * in: P1 - * out: R7, R6, R5 - * scratch: R1 - * load insn range/seqstat entry from table via register P1 - * R7: low range - * R6: high range - * R5: seqstat - * - * se_all_next_insn - * in: P5, R2 - * out: - * scratch: all but P5 - * advance current insn to next one for testing. register R2 - * is retained from se_all_load_insn. write out new insn to - * the location via register P5. - * - * se_all_new_insn_stub - * se_all_new_insn_log - * for handling of new insns ... generally not needed once done - */ -.macro se_all_test - start - - /* Set up exception handler */ - imm32 P4, EVT3; - loadsym R1, _evx; - [P4] = R1; - - /* set up the _location */ - loadsym P0, _location - loadsym P1, _table; - [P0] = P1; - - /* Enable single stepping */ - R0 = 1; - SYSCFG = R0; - - /* Lower to the code we want to single step through */ - loadsym P1, _usr; - RETI = P1; - - /* set up pointers to valid data (32Meg), to reduce address violations */ - reset_dags - - RTI; - -pass_lvl: - dbg_pass; -fail_lvl: - dbg_fail; - -_evx: - /* Make sure exception reason is as we expect */ - R3 = SEQSTAT; - R4 = 0x3f; - R3 = R3 & R4; - - /* find a match */ - loadsym P5, _usr; - loadsym P4, _location; - P1 = [P4]; - se_all_load_insn - -_match: - P2 = P1; - se_all_load_table - - /* is this the end of the table? */ - CC = R7 == 0; - IF CC jump _new_instruction; - - /* is the opcode (R0) greater than the 2nd entry in the table (R6) */ - /* if so look at the next line in the table */ - CC = R6 < R0; - if CC jump _match; - - /* is the opcode (R0) smaller than the first entry in the table (R7) */ - /* this means it's somewhere between the two lines, and should be legal */ - CC = R7 <= R0; - if !CC jump _legal_instruction; - - /* is the current EXCAUSE (R3), the same as the table (R5) */ - /* if not, fail */ - CC = R3 == R5 - if !CC jump fail_lvl; - -_match_done: - /* back up, and store the location to search next */ - [P4] = P2; - - /* it matches, so fall through */ - jump _next_instruction; - -_new_instruction: - /* The table is generated in memory and can be extracted: - (gdb) dump binary memory bin &table next_location - - 16bit: - $ od -j6 -x --width=4 bin | \ - awk '{ s=last; e=strtonum("0x"$2); \ - printf "\t.dw 0x%04x,\t0x%04x,\t\t0x%02x\n", \ - s, e-1, strtonum("0x"seq); \ - last=e; seq=$3}' - - 32bit: - $ od -j12 -x --width=8 bin | \ - awk '{ s=last; e=strtonum("0x"$3$2); \ - printf "\t.dw 0x%04x, 0x%04x,\t0x%04x, 0x%04x,\t\t0x%02x, 0\n", \ - and(s,0xffff), rshift(s,16), and(e-1,0xffff), rshift(e-1,16), \ - strtonum("0x"seq); \ - last=e; seq=$3}' - - This should be much faster than dumping over serial/jtag. */ - se_all_new_insn_stub - - /* output the insn (R0) and excause (R3) if diff from last */ - loadsym P0, _last_excause; - R2 = [P0]; - CC = R2 == R3; - IF CC jump _next_instruction; - [P0] = R3; - - se_all_new_insn_log - -_legal_instruction: - R4 = 0x10; - CC = R3 == R4; - IF !CC JUMP fail_lvl; - /* it wasn't in the list, and was a single step, so fall through */ - -_next_instruction: - se_all_next_insn - -.ifdef BFIN_JTAG - /* Make sure the opcode isn't in a write buffer */ - SSYNC; -.endif - - R1 = P5; - RETX = R1; - - /* set up pointers to valid data (32Meg), to reduce address violations */ - reset_dags - RETS = r0; - - RTX; - -.section .text.usr - .align 4 -_usr: - se_all_insn_init - loadsym P0, fail_lvl; - JUMP (P0); - -.data - .align 4; -_last_excause: - .dd 0xffff -_next_location: - .dd _table_end -_location: - .dd 0 -_table: - se_all_insn_table -_table_end: -.endm - -.macro se_all_load_table - R7 = LOAD_PFX[P1++]; - R6 = LOAD_PFX[P1++]; - R5 = LOAD_PFX[P1++]; -.endm - -#ifndef SE_ALL_NEW_INSN_STUB -.macro se_all_new_insn_stub - jump fail_lvl; -.endm -#endif - -.macro se_all_new_insn_log -.ifdef BFIN_JTAG_xxxxx - R1 = R0; -#if SE_ALL_BITS == 32 - R0 = 0x8; - call __emu_out; - R0 = R1; - call __emu_out; - R0 = R3; -#else - R0 = 0x4; - call __emu_out; - R0 = R1 << 16; - R0 = R0 | R3; -#endif - call __emu_out; -.else - loadsym P0, _next_location; - P1 = [P0]; - LOAD_PFX[P1++] = R0; - LOAD_PFX[P1++] = R3; - [P0] = P1; -.endif -.endm diff --git a/sim/testsuite/sim/bfin/se_brtarget_stall.S b/sim/testsuite/sim/bfin/se_brtarget_stall.S deleted file mode 100644 index 066602b..0000000 --- a/sim/testsuite/sim/bfin/se_brtarget_stall.S +++ /dev/null @@ -1,462 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_brtarget_stall/se_brtarget_stall.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE 0x00000500 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000020 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef IMASK -#define IMASK 0xFFE02104 -#endif -#ifndef DMEM_CONTROL -#define DMEM_CONTROL 0xFFE00004 -#endif -#ifndef DCPLB_ADDR0 -#define DCPLB_ADDR0 0xFFE00100 -#endif -#ifndef DCPLB_DATA0 -#define DCPLB_DATA0 0xFFE00200 -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - -///////////////////////////////////////////////////////////////////////////// -//////////////////////// CPLB Setup ///////////////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - // Setup CPLB for Data Memory starting at 0x00F0_0000; -WR_MMR(DCPLB_DATA0, 0x0003109d, p0, r0); // Page Size = 4MB - // CPLB_L1_CHLB = 1 - // CPLB_DIRTY = 1 - // CPLB_USER_RD = 1 - // CPLB_USER_WR = 1 - // CPLB_SUPV_WR = 1 - // CPLB_VALID = 1 - // - - // Setup CPLB Address to point to 0x00F0_0000 -WR_MMR_LABEL(DCPLB_ADDR0, data, p0, r0); - - // Enable CPLB's -WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1 - // ENDCPLB = 1 - // DMC = 11 - // Sync it! -CSYNC; - - - // Return to Supervisor Code -RAISE 15; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -NOP; - P0 = 0x0100 (Z); - P0.H = 0x00f0; -JUMP.S lab1; // Branch in EX1 - - -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - -lab1: - [ -- SP ] = ( R7:3 ); - P0 = 0x0200 (Z); - P0.H = 0x00f0; -RTI; -JUMP.S 8; // Branch in EX1 -NOP; -NOP; -NOP; - [ -- SP ] = ( R7:4 ); - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -data: -.section MEM_0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_0x00F00200,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_bug_ui.S b/sim/testsuite/sim/bfin/se_bug_ui.S deleted file mode 100644 index 4922d97..0000000 --- a/sim/testsuite/sim/bfin/se_bug_ui.S +++ /dev/null @@ -1,296 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_bug_ui/se_bug_ui.dsp -// Description: 16 bit special cases Undefined Instructions in Supervisor Mode -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 // change for how much stack you need -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; - -LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - - P0 += 4; // EVT0 not used (Emulation) - - P0 += 4; // EVT1 not used (Reset) - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - P0 += 4; // EVT4 not used (Global Interrupt Enable) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: - -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - // count of UI's will be in r5, which was initialized to 0 by header - - .dw 0x41FD ; - .dw 0x41FE ; - .dw 0x41FF ; - .dw 0x9040 ; - .dw 0x9049 ; - .dw 0x9052 ; - .dw 0x905B ; - .dw 0x9064 ; - .dw 0x906D ; - .dw 0x9076 ; - .dw 0x907F ; - .dw 0x90C0 ; - .dw 0x90C9 ; - .dw 0x90D2 ; - .dw 0x90DB ; - .dw 0x90E4 ; - .dw 0x90ED ; - .dw 0x90F6 ; - .dw 0x90FF ; - .dw 0x9180 ; - - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - // Xhandler counts all EXCAUSE = 0x21; -CHECKREG(r5, 20); // count of all 16 bit UI's. - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - // 16 bit illegal opcode handler - skips bad instruction - - // handler MADE LEAN and destructive so test runs more quckly - // se_undefinedinstruction1.dsp tests using a "nice" handler - -// [--sp] = ASTAT; // save what we damage -// [--sp] = (r7 - r6); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction -CC = r7 == r6; -IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave - - R6 = 0x22; // Also accept illegal insn combo -CC = r7 == r6; -IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave - -dbg_fail; - -UNDEFINEDINSTRUCTION: - R7 = RETX; // Fix up return address - - R7 += 2; // skip offending 16 bit instruction - -RETX = r7; // and put back in RETX - - R5 += 1; // Increment global counter - -OUT: -// (r7 - r6) = [sp++]; -// ASTAT = [sp++]; - -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - // padding for the icache - -EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_bug_ui2.S b/sim/testsuite/sim/bfin/se_bug_ui2.S deleted file mode 100644 index 5e0af4c..0000000 --- a/sim/testsuite/sim/bfin/se_bug_ui2.S +++ /dev/null @@ -1,296 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_bug_ui2/se_bug_ui2.dsp -// Description: 16 bit special cases Undefined Instructions in Supervisor Mode -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 // change for how much stack you need -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; - -LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - - P0 += 4; // EVT0 not used (Emulation) - - P0 += 4; // EVT1 not used (Reset) - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - P0 += 4; // EVT4 not used (Global Interrupt Enable) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: - -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - // count of UI's will be in r5, which was initialized to 0 by header - -// .dw 0x41FD ; -// .dw 0x41FE ; -// .dw 0x41FF ; - .dw 0x9040 ; - .dw 0x9049 ; - .dw 0x9052 ; - .dw 0x905B ; - .dw 0x9064 ; - .dw 0x906D ; - .dw 0x9076 ; - .dw 0x907F ; - .dw 0x90C0 ; - .dw 0x90C9 ; - .dw 0x90D2 ; - .dw 0x90DB ; - .dw 0x90E4 ; - .dw 0x90ED ; - .dw 0x90F6 ; - .dw 0x90FF ; - .dw 0x9180 ; - - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - // Xhandler counts all EXCAUSE = 0x21; -CHECKREG(r5, 17); // count of all 16 bit UI's. - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - // 16 bit illegal opcode handler - skips bad instruction - - // handler MADE LEAN and destructive so test runs more quckly - // se_undefinedinstruction1.dsp tests using a "nice" handler - -// [--sp] = ASTAT; // save what we damage -// [--sp] = (r7 - r6); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction -CC = r7 == r6; -IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave - - R6 = 0x22; // Also accept illegal insn combo -CC = r7 == r6; -IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave - -dbg_fail; - -UNDEFINEDINSTRUCTION: - R7 = RETX; // Fix up return address - - R7 += 2; // skip offending 16 bit instruction - -RETX = r7; // and put back in RETX - - R5 += 1; // Increment global counter - -OUT: -// (r7 - r6) = [sp++]; -// ASTAT = [sp++]; - -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - // padding for the icache - -EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_bug_ui3.S b/sim/testsuite/sim/bfin/se_bug_ui3.S deleted file mode 100644 index 3c0ff77..0000000 --- a/sim/testsuite/sim/bfin/se_bug_ui3.S +++ /dev/null @@ -1,300 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_bug_ui3/se_bug_ui3.dsp -// Description: 32 bit special cases Undefined Instructions in Supervisor Mode -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 // change for how much stack you need -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; - -LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - - P0 += 4; // EVT0 not used (Emulation) - - P0 += 4; // EVT1 not used (Reset) - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - P0 += 4; // EVT4 not used (Global Interrupt Enable) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: - -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - // count of UI's will be in r5, which was initialized to 0 by header - .dw 0xC0E0 ; - .dw 0x2000 ; - .dw 0xC140 ; - .dw 0x2000 ; - .dw 0xC1A0 ; - .dw 0x2000 ; - .dw 0xC1C0 ; - .dw 0x2000 ; - .dw 0xC1E0 ; - .dw 0x2000 ; - - .dw 0xC0E4 ; - .dw 0x0 ; - .dw 0xC144 ; - .dw 0x0 ; - .dw 0xC1A4 ; - .dw 0x0 ; - .dw 0xC1C4 ; - .dw 0x0 ; - .dw 0xC1E4 ; - .dw 0x0 ; - - .dw 0xC0E4 ; - .dw 0x2000 ; - .dw 0xC144 ; - .dw 0x2000 ; - .dw 0xC1A4 ; - .dw 0x2000 ; - .dw 0xC1C4 ; - .dw 0x2000 ; - .dw 0xC1E4 ; - .dw 0x2000 ; - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - // Xhandler counts all EXCAUSE = 0x21; -CHECKREG(r5, 15); // count of all 16 bit UI's. - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - // 32 bit illegal opcode handler - skips bad instruction - - // handler MADE LEAN and destructive so test runs more quckly - // se_undefinedinstruction1.dsp tests using a "nice" handler - -// [--sp] = ASTAT; // save what we damage -// [--sp] = (r7 - r6); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction -CC = r7 == r6; -IF !CC JUMP OUT; // If EXCAUSE != 0x21 then leave - -UNDEFINEDINSTRUCTION: - R7 = RETX; // Fix up return address - - R7 += 4; // skip offending 32 bit instruction - -RETX = r7; // and put back in RETX - - R5 += 1; // Increment global counter - -OUT: -// (r7 - r6) = [sp++]; -// ASTAT = [sp++]; - -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - // padding for the icache - -EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_cc2stat_haz.S b/sim/testsuite/sim/bfin/se_cc2stat_haz.S deleted file mode 100644 index 7bb1a24..0000000 --- a/sim/testsuite/sim/bfin/se_cc2stat_haz.S +++ /dev/null @@ -1,632 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_cc2stat_haz/se_cc2stat_haz.dsp -// Description: -// Verify CC hazards under the following condition: -// -// (1a) cc2stat (that modifies CC) followed by that uses CC -// (1b) same as (1a) but kill cc2stat instruction in WB -// -// (2a) cc2stat (that modifies CC) followed by conditional branch (predicted) -// (2b) same as (2a) but kill cc2stat instruction in WB -// -// (3a) cc2stat (that modifies CC) followed by conditional branch (mispredicted) -// (3b) same as (3a) but kill cc2stat instruction in WB -// -// (4a) cc2stat (that modifies CC) followed by testset -// (4b) same as (4a) but kill cc2stat instruction in WB -// -// (5a) cc2stat (that modifies CC) followed by dag instruction that modifies CC -// (5b) same as (5a) but kill cc2stat instruction in WB -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// ---------------------------------------------------------------- -// Include Files -// ---------------------------------------------------------------- - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -// ---------------------------------------------------------------- -// Defines -// ---------------------------------------------------------------- - -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_1 // -#endif - -// ---------------------------------------------------------------- -// Reset ISR -// - set the processor operating modes -// - initialize registers -// - etc ... -// ---------------------------------------------------------------- - -RST_ISR: - - // Initialize data registers - //INIT_R_REGS(0); - R7 = 0; - R6 = 0; - R5 = 0; - R4 = 0; - R3 = 0; - R2 = 0; - R1 = 0; - R0 = 0; - - // Initialize pointer registers -INIT_P_REGS(0); - - // Initialize address registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the address of the checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Inhibit events during MMR writes -CLI R1; - - // Setup user stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup kernel stack -LD32_LABEL(sp, KSTACK); - - // Setup frame pointer -FP = SP; - - // Setup event vector table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (EVT0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (EVT1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (EVT2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (EVT3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // EVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (EVT5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (EVT6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Set the EVT_OVERRIDE MMR -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - // Disable L1 data cache -WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0); - - // Mask interrupts (*) - R1 = -1; - - // Wait for MMR writes to finish -CSYNC; - - // Re-enable events -STI R1; - - // Reset accumulator registers - A0 = 0; - A1 = 0; - - // Reset loop counters to deterministic values - R0 = 0 (Z); - -LT0 = R0; -LB0 = R0; -LC0 = R0; -LT1 = R0; -LB1 = R0; -LC1 = R0; - - // Reset other internal regs -ASTAT = R0; -SYSCFG = R0; -RETS = R0; - - // Setup the test to run in USER mode -LD32_LABEL(r0, USER_CODE); -RETI = R0; - - // Setup the test to run in SUPERVISOR mode - // Comment the following line for a USER mode test -JUMP.S SUPERVISOR_CODE; -RTI; - -SUPERVISOR_CODE: - // Load IVG15 general handler (Int15) with MAIN_CODE -LD32_LABEL(p1, MAIN_CODE); - -LD32(p0, EVT15); - -CLI R1; - [ P0 ] = P1; -CSYNC; -STI R1; - - // Take Int15 which branch to MAIN_CODE after RTI -RAISE 15; -RTI; - -USER_CODE: - // Setup the stack pointer and the frame pointer -LD32_LABEL(sp, USTACK); -FP = SP; -JUMP.S MAIN_CODE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// ISR Table -// ---------------------------------------------------------------- - - -// ---------------------------------------------------------------- -// EMU ISR -// ---------------------------------------------------------------- - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// NMI ISR -// ---------------------------------------------------------------- - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// EXC ISR -// ---------------------------------------------------------------- - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// HWE ISR -// ---------------------------------------------------------------- - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// TMR ISR -// ---------------------------------------------------------------- - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV7 ISR -// ---------------------------------------------------------------- - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV8 ISR -// ---------------------------------------------------------------- - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV9 ISR -// ---------------------------------------------------------------- - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV10 ISR -// ---------------------------------------------------------------- - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV11 ISR -// ---------------------------------------------------------------- - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV12 ISR -// ---------------------------------------------------------------- - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV13 ISR -// ---------------------------------------------------------------- - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV14 ISR -// ---------------------------------------------------------------- - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV15 ISR -// ---------------------------------------------------------------- - - IGV15_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// Main Code -// ---------------------------------------------------------------- - - -MAIN_CODE: - // Enable interrupts in SUPERVISOR mode - // Comment the following line for a USER mode test - [ -- SP ] = RETI; - - // Start of the program code - R0 = 0; - R1 = 1; - R2 = 2; - - // Verify CC hazards under the following condition: - // - // (1a) cc2stat (that modifies CC) followed by that uses CC - A0 = 0; - A1 = R1; -CC = R0 < R2; -CC = AV0; - A0 = BXORSHIFT( A0 , A1, CC ); - R7 = CC; CHECKREG(R7, 0); - R6 = A0; CHECKREG(R6, 0); - R6 = A0.X; CHECKREG(R6, 0); - R7 = A1; CHECKREG(R7, 1); - R7 = A1.X; CHECKREG(R7, 0); - - // (1b) same as (1a) but kill cc2stat instruction in WB - A0 = R1; - A1 = R1; -CC = R0 < R2; -EXCPT 3; -CC = AV0; - A0 = BXORSHIFT( A0 , A1, CC ); - R7 = CC; CHECKREG(R7, 0); - R6 = A0; CHECKREG(R6, 3); - R6 = A0.X; CHECKREG(R6, 0); - R7 = A1; CHECKREG(R7, 1); - R7 = A1.X; CHECKREG(R7, 0); - - // (2a) cc2stat (that modifies CC) followed by conditional branch (predicted) - R3 = 0; - A0 = 0; - A1 = R1; -CC = R0 < R2; -CC = AV0; -IF !CC JUMP INC_R3_TO_10 (BP); - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; -INC_R3_TO_10: - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - - // (2b) same as (2a) but kill cc2stat instruction in WB - A0 = 0; - A1 = R1; -CC = R0 < R2; -EXCPT 3; -CC = AV0; -IF !CC JUMP INC_R3_TO_20 (BP); - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; -INC_R3_TO_20: - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - R3 += 1; - - // (3a) cc2stat (that modifies CC) followed by conditional branch (mispredicted) - A0 = 0; - A1 = R1; -CC = R0 < R2; -CC = AV0; -IF CC JUMP INC_R3_TO_20 (BP); - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - - // (3b) same as (3a) but kill cc2stat instruction in WB - A0 = 0; - A1 = R1; -CC = R0 < R2; -EXCPT 3; -CC = AV0; -IF CC JUMP INC_R3_TO_20 (BP); - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - R3 += 2; - -CHECKREG(r3, 60); - -dbg_pass; - - // (4a) cc2stat (that modifies CC) followed by testset -LD32(p0, DATA_ADDR_3); //LD32(p0, 0xff000000); -LD32(p1, DATA_ADDR_2); //LD32(p1, 0xffe00000); - [ P0 ] = R0; - - A0 = 0; - A1 = R1; -CC = R0 < R2; -CC = AV0; -QUERY_0: -TESTSET ( P0 ); -IF !CC JUMP QUERY_0; - [ P0 ] = R1; -CHECKMEM32(DATA_ADDR_3, 1); //CHECKMEM32(0xff000000, 1); - [ P0 ] = R0; -CHECKMEM32(DATA_ADDR_3, 0); //CHECKMEM32(0xff000000, 0); - - // (4b) same as (4a) but kill cc2stat instruction in WB - A0 = 0; - A1 = R1; -CC = R0 < R2; -EXCPT 3; -CC = AV0; -QUERY_1: -TESTSET ( P0 ); -IF !CC JUMP QUERY_1; - [ P0 ] = R2; -CHECKMEM32(DATA_ADDR_3, 2); //CHECKMEM32(0xff000000, 2); - [ P0 ] = R0; -CHECKMEM32(DATA_ADDR_3, 0); //CHECKMEM32(0xff000000, 0); - - // (5a) cc2stat (that modifies CC) followed by dag instruction that modifies CC - A0 = 0; - A1 = R1; -CC = R0 < R2; -CC = AV0; -CC = P0 < P1; - - // (5b) same as (5a) but kill cc2stat instruction in WB - A0 = 0; - A1 = R1; -CC = R0 < R2; -EXCPT 3; -CC = AV0; -CC = P0 < P1; - - -END: -dbg_pass; - -// ---------------------------------------------------------------- -// Data Segment -// - define kernel and user stacks -// ---------------------------------------------------------------- - -.data - DATA: - .space (STACKSIZE); - - .space (STACKSIZE); - KSTACK: - - .space (STACKSIZE); - USTACK: diff --git a/sim/testsuite/sim/bfin/se_cc_kill.S b/sim/testsuite/sim/bfin/se_cc_kill.S deleted file mode 100644 index 5d0aead..0000000 --- a/sim/testsuite/sim/bfin/se_cc_kill.S +++ /dev/null @@ -1,480 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_cc_kill/se_cc_kill.dsp -// Description: -// Verify CC kill under the following condition: -// -// (1) CC = AZ killed in WB -// (2) CC = AN killed in WB -// (3) CC = AC killed in WB -// (4) CC = AV0 killed in WB -// (5) CC = AV1 killed in WB -// (6) CC = AQ killed in WB -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// ---------------------------------------------------------------- -// Include Files -// ---------------------------------------------------------------- - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -// ---------------------------------------------------------------- -// Defines -// ---------------------------------------------------------------- - -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_1 // -#endif - - -// ---------------------------------------------------------------- -// Reset ISR -// - set the processor operating modes -// - initialize registers -// - etc ... -// ---------------------------------------------------------------- - -RST_ISR: - - // Initialize data registers - //INIT_R_REGS(0); - R7 = 0; - R6 = 0; - R5 = 0; - R4 = 0; - R3 = 0; - R2 = 0; - R1 = 0; - R0 = 0; - - // Initialize pointer registers -INIT_P_REGS(0); - - // Initialize address registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the address of the checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Inhibit events during MMR writes -CLI R1; - - // Setup user stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup kernel stack -LD32_LABEL(sp, KSTACK); - - // Setup frame pointer -FP = SP; - - // Setup event vector table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (EVT0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (EVT1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (EVT2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (EVT3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // EVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (EVT5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (EVT6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Set the EVT_OVERRIDE MMR -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - // Disable L1 data cache -WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0); - - // Mask interrupts (*) - R1 = -1; - - // Wait for MMR writes to finish -CSYNC; - - // Re-enable events -STI R1; - - // Reset loop counters to deterministic values - R0 = 0 (Z); - -LT0 = R0; -LB0 = R0; -LC0 = R0; -LT1 = R0; -LB1 = R0; -LC1 = R0; - - // Reset other internal regs -ASTAT = R0; -SYSCFG = R0; -RETS = R0; - - // Setup the test to run in USER mode -LD32_LABEL(r0, USER_CODE); -RETI = R0; - - // Setup the test to run in SUPERVISOR mode - // Comment the following line for a USER mode test -JUMP.S SUPERVISOR_CODE; -RTI; - -SUPERVISOR_CODE: - // Load IVG15 general handler (Int15) with MAIN_CODE -LD32_LABEL(p1, MAIN_CODE); - -LD32(p0, EVT15); - -CLI R1; - [ P0 ] = P1; -CSYNC; -STI R1; - - // Take Int15 which branch to MAIN_CODE after RTI -RAISE 15; -RTI; - -USER_CODE: - // Setup the stack pointer and the frame pointer -LD32_LABEL(sp, USTACK); -FP = SP; -JUMP.S MAIN_CODE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// ISR Table -// ---------------------------------------------------------------- - - -// ---------------------------------------------------------------- -// EMU ISR -// ---------------------------------------------------------------- - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// NMI ISR -// ---------------------------------------------------------------- - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// EXC ISR -// ---------------------------------------------------------------- - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// HWE ISR -// ---------------------------------------------------------------- - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// TMR ISR -// ---------------------------------------------------------------- - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV7 ISR -// ---------------------------------------------------------------- - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV8 ISR -// ---------------------------------------------------------------- - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV9 ISR -// ---------------------------------------------------------------- - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV10 ISR -// ---------------------------------------------------------------- - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV11 ISR -// ---------------------------------------------------------------- - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV12 ISR -// ---------------------------------------------------------------- - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV13 ISR -// ---------------------------------------------------------------- - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV14 ISR -// ---------------------------------------------------------------- - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// IGV15 ISR -// ---------------------------------------------------------------- - - IGV15_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -// ---------------------------------------------------------------- -// Main Code -// ---------------------------------------------------------------- - - -MAIN_CODE: - // Enable interrupts in SUPERVISOR mode - // Comment the following line for a USER mode test - [ -- SP ] = RETI; - - // Start of the program code - - // Verify CC kill under the following condition: - - // (1) CC = AZ killed in WB -CC = R2 < R3; -EXCPT 3; -CC = AZ; - - // (2) CC = AN killed in WB -CC = R2 == R3; -EXCPT 3; -CC = AN; - - // (3) CC = AC killed in WB -CC = R2 < R3; -EXCPT 3; -CC = AC0; - - // (4) CC = AV0 killed in WB -CC = R2 == R3; -EXCPT 3; -CC = AV0; - - // (5) CC = AV1 killed in WB -CC = R2 == R3; -EXCPT 3; -CC = AV1; - - // (6) CC = AQ killed in WB -CC = R2 == R3; -EXCPT 3; -CC = AQ; - - -END: -dbg_pass; - -// ---------------------------------------------------------------- -// Data Segment -// - define kernel and user stacks -// ---------------------------------------------------------------- - -.data - DATA: - .space (STACKSIZE); - - .space (STACKSIZE); - KSTACK: - - .space (STACKSIZE); - USTACK: diff --git a/sim/testsuite/sim/bfin/se_cof.S b/sim/testsuite/sim/bfin/se_cof.S deleted file mode 100644 index 4802cce..0000000 --- a/sim/testsuite/sim/bfin/se_cof.S +++ /dev/null @@ -1,424 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_cof/se_cof.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -NOP; - //lz(p0) = 0x0004; - //h(p0) = 0xffe0; -LD32(p0, DMEM_CONTROL); -CSYNC; - R0 = [ P0 ]; // MMR load will Stall -JUMP.S lab1; // Branch in EX1 - - -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - -lab1: - [ -- SP ] = ( R7:3 ); -IF !CC JUMP 2; // Mispredicted branch; -NOP; -JUMP.S lab2; // Branch in EX1 -NOP; -NOP; -NOP; -NOP; - -lab2: -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_3 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_3 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_event_quad.S b/sim/testsuite/sim/bfin/se_event_quad.S deleted file mode 100644 index 0a1611b..0000000 --- a/sim/testsuite/sim/bfin/se_event_quad.S +++ /dev/null @@ -1,436 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_event_quad/se_event_quad.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE 0x00000500 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef IMASK -#define IMASK 0xFFE02104 -#endif -#ifndef DMEM_CONTROL -#define DMEM_CONTROL 0xFFE00004 -#endif -#ifndef DCPLB_ADDR0 -#define DCPLB_ADDR0 0xFFE00100 -#endif -#ifndef DCPLB_DATA0 -#define DCPLB_DATA0 0xFFE00200 -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - - P0 = 0x5 (Z); - P1 = 0xa (Z); - - P2 = 0x0100 (Z); - P2.H = 0x00f0; - R0 = 0xf0f0 (Z); - R0.H = 0x0f0f; - -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; - -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_0x00F00100,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; -.dd 0x05050505; -.dd 0x06060606; -.dd 0x07070707; -.dd 0x08080808; -.dd 0x09090909; -.dd 0x0a0a0a0a; -.dd 0x0b0b0b0b; -.dd 0x0c0c0c0c; -.dd 0x0d0d0d0d; -.dd 0x0e0e0e0e; -.dd 0x0f0f0f0f; - -// Define Kernal Stack -.section MEM_0x00F00210,"aw" - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_excpt_dagprotviol.S b/sim/testsuite/sim/bfin/se_excpt_dagprotviol.S deleted file mode 100644 index 48e496b..0000000 --- a/sim/testsuite/sim/bfin/se_excpt_dagprotviol.S +++ /dev/null @@ -1,281 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_excpt_dagprotviol/se_excpt_dagprotviol.dsp -// Description: EXCPT instruction combined with DAG Misaligned Access -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x100 // change for how much stack you need -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; - -LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - - P0 += 4; // EVT0 not used (Emulation) - - P0 += 4; // EVT1 not used (Reset) - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - P0 += 4; // EVT4 not used (Global Interrupt Enable) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -RETI = r0; // prevent Xs later on -RETX = r0; -RETN = r0; -RETE = r0; - - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -// JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -FP = SP; -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests -// [--sp] = RETI; // enable interrupts in supervisor mode - - R0 = 0; - R1 = -1; -LD32_LABEL(p1, USTACK); - P1 += 1; // misalign it - -EXCPT 2; // the RAISE should not prevent the EXCPT from being taken - R2 = [ P1 ]; - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - -CHECKREG(r5, 2); // check the flag - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - - [ -- SP ] = ASTAT; // save what we damage - [ -- SP ] = ( R7:6 ); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 instruction -CC = r7 == r6; -IF CC JUMP EXCPT2; - - R6 = 0x24; // EXCAUSE 0x24 means DAG misalign -CC = r7 == r6; -IF CC JUMP DGPROTVIOL; - -JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop - -EXCPT2: - R5 = 1; // Set a Flag -JUMP.S OUT; - -DGPROTVIOL: - R7 = RETX; // Fix up return address - - R7 += 2; // skip offending 16 bit instruction - -RETX = r7; // and put back in RETX - - R5 <<= 1; // Alter Global Flag - -OUT: - ( R7:6 ) = [ SP ++ ]; -ASTAT = [sp++]; -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - // padding for the icache - -EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_excpt_ifprotviol.S b/sim/testsuite/sim/bfin/se_excpt_ifprotviol.S deleted file mode 100644 index 50207fc..0000000 --- a/sim/testsuite/sim/bfin/se_excpt_ifprotviol.S +++ /dev/null @@ -1,280 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_excpt_ifprotviol/se_excpt_ifprotviol.dsp -// Description: EXCPT instruction and IF Prot Viol priority -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x100 // change for how much stack you need -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; - -LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - - P0 += 4; // EVT0 not used (Emulation) - - P0 += 4; // EVT1 not used (Reset) - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - P0 += 4; // EVT4 not used (Global Interrupt Enable) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -RETI = r0; // prevent Xs later on -RETX = r0; -RETN = r0; -RETE = r0; - - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -// JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -FP = SP; -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests -// [--sp] = RETI; // enable interrupts in supervisor mode - - R0 = 0; - R1 = -1; - - -EXCPT 2; // the RAISE should not prevent the EXCPT from being taken -RAISE 15; - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - -CHECKREG(r5, 2); // check the flag - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - - [ -- SP ] = ASTAT; // save what we damage - [ -- SP ] = ( R7:6 ); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 instruction -CC = r7 == r6; -IF CC JUMP EXCPT2; - - R6 = 0x2E; // EXCAUSE 0x2E means Illegal Use Supervisor Resource -CC = r7 == r6; -IF CC JUMP IFPROTVIOL; - -JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop - -EXCPT2: - R5 = 1; // Set a Flag -JUMP.S OUT; - -IFPROTVIOL: - R7 = RETX; // Fix up return address - - R7 += 2; // skip offending 16 bit instruction - -RETX = r7; // and put back in RETX - - R5 <<= 1; // Alter Global Flag - -OUT: - ( R7:6 ) = [ SP ++ ]; -ASTAT = [sp++]; -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - // padding for the icache - -EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_excpt_ssstep.S b/sim/testsuite/sim/bfin/se_excpt_ssstep.S deleted file mode 100644 index 5cb5558..0000000 --- a/sim/testsuite/sim/bfin/se_excpt_ssstep.S +++ /dev/null @@ -1,290 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_excpt_ssstep/se_excpt_ssstep.dsp -// Description: EXCPT instruction vs Single Step Exception Priority -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -//include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - - R0 = 1; - -SYSCFG = r0; // Enable Supervisor Single Step - -CHECK_INIT_DEF(p2); //CHECK_INIT(p2, 0x2000); - - -// Comment the following line for a USER Mode test - -// JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// - -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests -// [--sp] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - R0 = 0; - R0 = 0; - R0 = 0; - R0 = 0; - R0 = 0; -EXCPT 15; // single step shouldn't happen for this. - R0 = 0; - R0 = 0; - R0 = 0; - R0 = 0; - R0 = 0; - -EXCPT 3; // turn off single step via handler - -CHECKREG(r4, 1); // one EXCPT 15 instruction -CHECKREG(r5, 14); // 14 instructions are executed before we disable single step - - - // PUT YOUR TEST HERE! - - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - [ -- SP ] = ASTAT; // save what we damage - [ -- SP ] = ( R7:6 ); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x10; // EXCAUSE 0x10 means Single Step -CC = r7 == r6; -IF CC JUMP SINGLESTEP (BP); // Go to Single Step Handler - - R6 = 15; // EXCAUSE 15 means EXCPT 15 instruction -CC = r7 == r6; -IF CC JUMP EXCPT15 (BP); - -SYSCFG = r0; // otherwise must be an EXCPT, so turn off singlestep - -JUMP.S OUT; - -EXCPT15: - R4 += 1; // R4 counts EXCPT 15s -JUMP.S OUT; - -SINGLESTEP: - R5 += 1; // R5 counts single step events - -OUT: - ( R7:6 ) = [ SP ++ ]; -ASTAT = [sp++]; -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_illegalcombination.S b/sim/testsuite/sim/bfin/se_illegalcombination.S deleted file mode 100644 index 0fe5f27..0000000 --- a/sim/testsuite/sim/bfin/se_illegalcombination.S +++ /dev/null @@ -1,622 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_illegalcombination/se_illegalcombination.dsp -// Description: Multi-issue Illegal Combinations -# mach: bfin -# sim: --environment operating -# xfail: "missing a few checks; hardware doesnt seem to match PRM?" bfin-* - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x100 // change for how much stack you need -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; - -LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - - P0 += 4; // EVT0 not used (Emulation) - - P0 += 4; // EVT1 not used (Reset) - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - P0 += 4; // EVT4 not used (Global Interrupt Enable) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - A0 = 0; // reset accumulators - A1 = 0; - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: - -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - // PUT YOUR TEST HERE! - -// Slot 0 can only be LDST LOAD with search instruction (2 instrs) - - - .dw 0xcc0d //(R0,R1)=SEARCH R2(GT)||[P0]=R3||NOP; - .dw 0x0210 - .dw 0x9303 - .dw 0x0000 -// (r0,r1) = search r2 gt, nop, r3 = [i0]; // nop supposedly ok -( R0 , R1 ) = SEARCH R2 (GT) || R4 = [ P0 ++ P1 ] || NOP; - -// only nop or dspLDST allowed in slot 1 (1 instr) - - // a0 = r0, nop, [p0] = r3; - .dw 0xCC09; // can't assemble - .dw 0x2000; - .dw 0x0000; - .dw 0x9303; - -// Slot 0 illegal opcodes (1 instr) - - // a0 = r0, raise 15, nop; - .dw 0xCC09; // can't assemble - .dw 0x2000; - .dw 0x009F; - .dw 0x0000; - -// multiissue with two stores (8 instrs) - - - .dw 0xcc09 //A0=R0||W[P3]=R5.L||[I0]=R4; - .dw 0x2000 - .dw 0x8b5b - .dw 0x9f04 - - .dw 0xcc09 //A0=R0||[I2]=R2||[I0]=R4; - .dw 0x2000 - .dw 0x9f12 - .dw 0x9f04 - - .dw 0xcc09 //A0=R0||[P3]=R0||[I0]=R4; - .dw 0x2000 - .dw 0x9318 - .dw 0x9f04 - - .dw 0xcc09 //A0=R0||[P3]=P0||[I0]=R4; - .dw 0x2000 - .dw 0x9358 - .dw 0x9f04 - - .dw 0xcc09 //A0=R0||[FP+-36]=R0||[I0]=R4; - .dw 0x2000 - .dw 0xbb70 - .dw 0x9f04 - - .dw 0xcc09 //A0=R0||[FP+-48]=P0||[I0]=R4; - .dw 0x2000 - .dw 0xbb48 - .dw 0x9f04 - - .dw 0xcc09 //A0=R0||[P3+0x20]=R1||[I0]=R4; - .dw 0x2000 - .dw 0xb219 - .dw 0x9f04 - - .dw 0xcc09 //A0=R0||[P3+0x20]=P1||[I0]=R4; - .dw 0x2000 - .dw 0xbe19 - .dw 0x9f04 - -// multiissue two instructions can't modify same ireg (6 instrs) - - - .dw 0xcc09 //A0=R0||I0+=M1(BREV)||R1.L=W[I0++]; - .dw 0x2000 - .dw 0x9ee4 - .dw 0x9c21 - - .dw 0xcc09 //A0=R0||I1-=M3||R0=[I1++M3]; - .dw 0x2000 - .dw 0x9e7d - .dw 0x9de8 - - .dw 0xcc09 //A0=R0||I2+=2||W[I2++]=R0.L; - .dw 0x2000 - .dw 0x9f62 - .dw 0x9e30 - - .dw 0xcc09 //A0=R0||I3-=4||[I3++M1]=R7; - .dw 0x2000 - .dw 0x9f6f - .dw 0x9fbf - - .dw 0xcc09 //A0=R0||R1.L=W[I1++]||W[I1++]=R2.L; - .dw 0x2000 - .dw 0x9c29 - .dw 0x9e2a - - .dw 0xcc09 //A0=R0||[I2++M3]=R7||R6=[I2++M0]; - .dw 0x2000 - .dw 0x9ff7 - .dw 0x9d96 - -// multiissue two instructions can't load same dreg (9 instrs) - - - .dw 0xcc09 //A0=R0||R0.L=W[P0++P2]||R0=[I0++]; - .dw 0x2000 - .dw 0x8210 - .dw 0x9c00 - - .dw 0xcc09 //A0=R0||R1=W[P0++P3](X)||R1.L=W[I2]; - .dw 0x2000 - .dw 0x8e58 - .dw 0x9d31 - - .dw 0xcc09 //A0=R0||R2=W[P0++P3](X)||R2=[I1++M3]; - .dw 0x2000 - .dw 0x8e98 - .dw 0x9dea - - .dw 0xcc09 //A0=R0||R3=[I0++]||R3=[I1++]; - .dw 0x2000 - .dw 0x9c03 - .dw 0x9c0b - - .dw 0xcc09 //A0=R0||R4.L=W[I2]||R4.L=W[I3]; - .dw 0x2000 - .dw 0x9d34 - .dw 0x9d3c - - .dw 0xcc09 //A0=R0||R5=[I1++M3]||R5.L=W[I2++]; - .dw 0x2000 - .dw 0x9ded - .dw 0x9c35 - - .dw 0xcc09 //A0=R0||R6=[P0]||R6=[I0++]; - .dw 0x2000 - .dw 0x9106 - .dw 0x9c06 - - .dw 0xcc09 //A0=R0||R7=[FP+-56]||R7.L=W[I1]; - .dw 0x2000 - .dw 0xb927 - .dw 0x9d2f - - .dw 0xcc09 //A0=R0||R0=W[P1+0x1e](X)||R0=[I0++]; - .dw 0x2000 - .dw 0xabc8 - .dw 0x9c00 - -// dsp32alu instructions with one dest and slot 0 multi with same dest (1 ins) - - - .dw 0xcc00 //R0=R2+|+R3||R0=W[P1+0x1e](X)||NOP; - .dw 0x0013 - .dw 0xabc8 - .dw 0x0000 - // other slot 0 dreg cases already covered - -// dsp32alu one dest and slot 1 multi with same dest (1 ins) - - - .dw 0xcc18 //R1=BYTEPACK(R4,R5)||NOP||R1.L=W[I2]; - .dw 0x0225 - .dw 0x0000 - .dw 0x9d31 - // other slot 1 dreg dest cases already covered - -// dsp32alu dual dests and slot 0 multi with either same dest (2 instrs) - - - .dw 0xcc18 //(R2,R3)=BYTEUNPACKR1:0||R2=W[P0++P3](X)||NOP; - .dw 0x4680 - .dw 0x8e98 - .dw 0x0000 - - .dw 0xcc01 //R2=R2+|+R3,R3=R2-|-R3||R3=[P3]||NOP; - .dw 0x0693 - .dw 0x911b - .dw 0x0000 - -// dsp32alu dual dests and slot 1 multi with either same dest (2 instrs) - - - .dw 0xcc18 //(R4,R5)=BYTEUNPACKR1:0||NOP||R4=[I1++M3]; - .dw 0x4b00 - .dw 0x0000 - .dw 0x9dec - - .dw 0xcc01 //R4=R2+|+R3,R5=R2-|-R3||NOP||R5.L=W[I2++]; - .dw 0x0b13 - .dw 0x0000 - .dw 0x9c35 - -// dsp32shift one dest and slot 0 multi with same dest (1 instruction) - - - .dw 0xce0d //R6=ALIGN8(R4,R5)||R6=[P0]||NOP; - .dw 0x0c2c - .dw 0x9106 - .dw 0x0000 - -// dsp32shift one dest and slot 1 multi with same dest (1 instruction) - - - .dw 0xce00 //R7.L=ASHIFTR0.HBYR7.L||NOP||R7.L=W[I1]; - .dw 0x1e38 - .dw 0x0000 - .dw 0x9d2f - -// dsp32shift two dests and slot 0 multi with either same dest (2 instrs) - - - .dw 0xce08 //BITMUX(R0,R1,A0)(ASR)||R0.L=W[P0++P2]||NOP; - .dw 0x0001 - .dw 0x8210 - .dw 0x0000 - - .dw 0xce08 //BITMUX(R2,R3,A0)(ASL)||R3=[I0++]||NOP; - .dw 0x4013 - .dw 0x9c03 - .dw 0x0000 - -// dsp32shift two dests and slot 1 multi with either same dest (2 instrs) - - - .dw 0xce08 //BITMUX(R4,R5,A0)(ASR)||NOP||R4.H=W[I3]; - .dw 0x0025 - .dw 0x0000 - .dw 0x9d5c - - .dw 0xce08 //BITMUX(R6,R7,A0)(ASL)||NOP||R7.L=W[I1]; - .dw 0x4037 - .dw 0x0000 - .dw 0x9d2f - -// dsp32shiftimm one dest and slot 0 with same dest (1 instr) - - - .dw 0xce80 //R1.L=R0.H<<0x7||R1=W[P0++P3](X)||NOP; - .dw 0x1238 - .dw 0x8e58 - .dw 0x0000 - -// dsp32shiftimm one dest and slot 1 with same dest (1 instr) - - - .dw 0xce81 //R5=R2<<0x9(V)||NOP||R5.L=W[I2++]; - .dw 0x0a4a - .dw 0x0000 - .dw 0x9c35 - -// dsp32mac one dest and slot 0 multi with same dest (1 inst) - - - .dw 0xc805 //A0+=R1.H*R0.L,R6.H=(A1+=R1.L*R0.H)||R6=W[P0++P3](X)||NOP; - .dw 0x4d88 - .dw 0x8f98 - .dw 0x0000 - -// dsp32mult one dest and slot 0 multi with same dest (1 inst) - - - .dw 0xca04 //R7.H=R3.L*R4.H||R7=[FP+-56]||NOP; - .dw 0x41dc - .dw 0xb927 - .dw 0x0000 - -// dsp32 mac one dest and slot 1 multi with same dest (1 inst) - - - .dw 0xc805 //A0+=R1.H*R0.L,R0.H=(A1+=R1.L*R0.H)||NOP||R0=[I0++]; - .dw 0x4c08 - .dw 0x0000 - .dw 0x9c00 - -// dsp32mult one dest and slot 1 multi with same dest (1 inst) - - - .dw 0xca04 //R1.H=R3.L*R4.H||NOP||R1.H=W[I1]; - .dw 0x405c - .dw 0x0000 - .dw 0x9d49 - -// dsp32mac write to register pair and slot 0 same dest - even (1 instr) - - - .dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||R2=W[P0++P3](X)||NOP; - .dw 0x6c88 - .dw 0x8e98 - .dw 0x0000 - -// dsp32mult write to register pair and slot 0 same dest - even (1 instr) - - - .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R4=[P0++P1]||NOP; - .dw 0x6508 - .dw 0x8108 - .dw 0x0000 - -// dsp32mac write to register pair and slot 1 same dest - even (1 instr) - - - .dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||NOP||R2=[I1++M3]; - .dw 0x6c88 - .dw 0x0000 - .dw 0x9dea - -// dsp32mult write to register pair and slot 1 same dest - even (1 instr) - - - .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R4=[I1++M3]; - .dw 0x6508 - .dw 0x0000 - .dw 0x9dec - -// dsp32mac write to register pair and slot 0 same dest - odd (1 instr) - - - .dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||R3=W[P0++P3](X)||NOP; - .dw 0x4c88 - .dw 0x8ed8 - .dw 0x0000 - -// dsp32mult write to register pair and slot 0 same dest - odd (1 instr) - - - .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R5=[P0++P1]||NOP; - .dw 0x6508 - .dw 0x8148 - .dw 0x0000 - -// dsp32mac write to register pair and slot 1 same dest - odd (1 instr) - - - .dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||NOP||R3=[I1++M3]; - .dw 0x4c88 - .dw 0x0000 - .dw 0x9deb - -// dsp32mult write to register pair and slot 1 same dest - odd (1 instr) - - - .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R5=[I1++M3]; - .dw 0x6508 - .dw 0x0000 - .dw 0x9ded - -// CHECKER - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - // Xhandler counts all EXCAUSE = 0x22; -CHECKREG(r5, 53); // count of all Illegal Combination Exceptions. - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - // 16 bit illegal opcode handler - skips bad instruction - - [ -- SP ] = ASTAT; // save what we damage - [ -- SP ] = ( R7:6 ); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x22; // EXCAUSE 0x22 means I-Fetch Undefined Instruction -CC = r7 == r6; -IF CC JUMP ILLEGALCOMBINATION; // If EXCAUSE != 0x22 then leave - -dbg_fail; -JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop - -ILLEGALCOMBINATION: - R7 = RETX; // Fix up return address - - R7 += 8; // skip offending 64 bit instruction - -RETX = r7; // and put back in RETX - - R5 += 1; // Increment global counter - -OUT: - ( R7:6 ) = [ SP ++ ]; -ASTAT = [sp++]; - -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - // padding for the icache - -EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_kill_wbbr.S b/sim/testsuite/sim/bfin/se_kill_wbbr.S deleted file mode 100644 index 80ec7d1..0000000 --- a/sim/testsuite/sim/bfin/se_kill_wbbr.S +++ /dev/null @@ -1,422 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_kill_wbbr/se_kill_wbbr.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Load RETS -LD32_LABEL(r0, USER_CODE); -RETS = R0; - - // Return to Supervisor Code -RAISE 2; -RAISE 5; -RAISE 6; -RAISE 7; -RAISE 8; -RAISE 9; -RAISE 10; -RAISE 11; -RAISE 12; -RAISE 13; -RAISE 14; -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; -IF !CC JUMP 2; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; -NOP; -IF !CC JUMP 2; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; -CSYNC; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; -NOP; -CSYNC; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; -SSYNC; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; -NOP; -SSYNC; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; -NOP; -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; -NOP; -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -RTI; -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -EXCPT 0x5; -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_2 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_2 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.section MEM_(DATA_ADDR_2 + 0x110) //.data 0x00F00210,"aw" - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_kills2.S b/sim/testsuite/sim/bfin/se_kills2.S deleted file mode 100644 index 73f9d28..0000000 --- a/sim/testsuite/sim/bfin/se_kills2.S +++ /dev/null @@ -1,148 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_kills2/se_kills2.dsp -// Description: Test se_kill for all supported types of RTL1 instructions -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(selfcheck.inc) -include(std.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -SP = 0 (Z); -SP.L = KSTACK; // setup the stack pointer -SP.H = KSTACK; -FP = SP; // and frame pointer - -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -ASTAT = r0; // reset sequencer registers - -// -// The Main Program -// - -START: - - // **** YOUR CODE GOES HERE **** - // CHECK_INIT(p0, 0xFF7FFFFC); // original -CHECK_INIT_DEF(p0); - - R0 = 0; - R1 = 1; - R2 = 2; - R3 = 3; - R4 = 4; - R5 = 5; - R6 = 6; - R7 = 7; - P1 = 11; - // Assume CC is reset to 0. -IF !CC JUMP NEXT1; // following instruction should be killed -RAISE 13; - -NEXT1: - IF !CC JUMP NEXT2; -EXCPT 15; - -NEXT2: - IF !CC JUMP NEXT3; - ( R7:0, P5:0 ) = [ SP ++ ]; - -NEXT3: - IF !CC JUMP NEXT4; - [ -- SP ] = ( R7:0, P5:0 ); - -NEXT4: - IF !CC JUMP NEXT5; -EMUEXCPT; - -NEXT5: - IF !CC JUMP NEXT6; -.dd 0xFACEBABE - -NEXT6: - IF !CC JUMP NEXT7; -LINK 12; - -NEXT7: - IF !CC JUMP NEXT8; -UNLINK; - -NEXT8: - IF !CC JUMP NEXT9; -LSETUP (NEXT10, NEXT11) lc0 = p0; - -NEXT9: - IF !CC JUMP NEXT10; - -NEXT10: - IF !CC JUMP NEXT11; - -NEXT11: - IF !CC JUMP NEXT12; - -NEXT12: - IF !CC JUMP NEXT13; - -NEXT13: - IF !CC JUMP NEXT14; - -NEXT14: - IF !CC JUMP NEXT15; - -NEXT15: - IF !CC JUMP NEXT16; - -NEXT16: - -END: -CHECKREG(r0, 0); -CHECKREG(r1, 1); -CHECKREG(r2, 2); -CHECKREG(r3, 3); -CHECKREG(r4, 4); -CHECKREG(r5, 5); -CHECKREG(r6, 6); -CHECKREG(r7, 7); - -dbg_pass; // Call Endtest Macro - -//********************************************************************* -// -// Data Segment -// - -//.data 0xF0000000 -.data -DATA: - .space (0x010); // Some data space - -// Stack Segments - - .space (STACKSIZE); -KSTACK: diff --git a/sim/testsuite/sim/bfin/se_loop_disable.S b/sim/testsuite/sim/bfin/se_loop_disable.S deleted file mode 100644 index 3b84d8c..0000000 --- a/sim/testsuite/sim/bfin/se_loop_disable.S +++ /dev/null @@ -1,408 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_disable/se_loop_disable.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - P1 = 0x3 (Z); - -LSETUP ( 1f , 1f ) LC0 = P1; -1:R7 += 1; -LSETUP ( 1f , 1f ) LC0 = P1; -1:R6 += 1; -LC0 = P0; -LD32_LABEL(r0, l0t); -LD32_LABEL(r1, l0b); -LT0 = r0; -LB0 = r1; -l0t:R3 += 3; - R1 += 1; - R4 += 4; - R5 += 5; - R6 += 6; -l0b:R2 += 2; - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_3 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_( DATA_ADDR_3 + 100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.section MEM_( DATA_ADDR_3 + 110) //.data 0x00F00210,"aw" - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_kill.S b/sim/testsuite/sim/bfin/se_loop_kill.S deleted file mode 100644 index 6a2b633..0000000 --- a/sim/testsuite/sim/bfin/se_loop_kill.S +++ /dev/null @@ -1,519 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_kill/se_loop_kill.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE 0x00000500 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef IMASK -#define IMASK 0xFFE02104 -#endif -#ifndef DMEM_CONTROL -#define DMEM_CONTROL 0xFFE00004 -#endif -#ifndef DCPLB_ADDR0 -#define DCPLB_ADDR0 0xFFE00100 -#endif -#ifndef DCPLB_DATA0 -#define DCPLB_DATA0 0xFFE00200 -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - P1 = 0x3 (Z); - P2 = 0x0200 (Z); - P2.H = 0x00F0; - [ -- SP ] = P0; - [ -- SP ] = P0; -SSYNC; - -LD32_LABEL(r0, l0t); -LD32_LABEL(r1, l0b); -LT0 = r0; -LB0 = r1; -EXCPT 0x5; // Will kill mv2lc in EX3 -NOP; -LC0 = P0; -l0t:R3 += 3; - R1 += 1; - R4 += 4; - R5 += 5; - R6 += 6; -l0b:R2 += 2; - -LD32_LABEL(r0, l2t); -LD32_LABEL(r1, l2b); -LT0 = r0; -LB0 = r1; -EXCPT 0x5; // Will kill mv2lc in EX3 when stalled -LC0 = [ SP ++ ]; -l2t:R3 += 3; - R1 += 1; - R4 += 4; - R5 += 5; - R6 += 6; -l2b:R2 += 2; - -LD32_LABEL(r0, l1t); -LD32_LABEL(r1, l1b); -LT1 = r0; -LB1 = r1; -EXCPT 0x5; // Will kill mv2lc in EX3 when stalled -LC1 = [ SP ++ ]; -l1t:R3 += 3; - R1 += 1; - R4 += 4; - R5 += 5; - R6 += 6; -l1b:R2 += 2; - -LD32_LABEL(r0, l3t); -LD32_LABEL(r1, l3b); -LT1 = r0; -LB1 = r1; -EXCPT 0x5; // Will kill mv2lc in EX3 -NOP; -LC1 = P0; -l3t:R3 += 3; - R1 += 1; - R4 += 4; - R5 += 5; - R6 += 6; -l3b:R2 += 2; - -EXCPT 0x6; // Will kill Lsetup in EX2 -NOP; -NOP; -LSETUP ( l1e , l1e ) LC0 = P1; -l1e:R7 += 1; - -EXCPT 0x6; // Will kill Lsetup in EX2 -NOP; -NOP; -LSETUP ( m1e , m1e ) LC1 = P1; -m1e:R7 += 1; - -EXCPT 0x6; // Will kill Lsetup in EX1 -NOP; -NOP; -NOP; -LSETUP ( l2e , l2e ) LC0 = P1; -l2e:R7 += 1; - -EXCPT 0x6; // Will kill Lsetup in EX1 -NOP; -NOP; -NOP; -LSETUP ( m2e , m2e ) LC1 = P1; -m2e:R7 += 1; - -NOP; -NOP; -NOP; - -EXCPT 0x6; // Will kill Lsetup in EX2 when stalled - R0 = [ P2 ++ ]; -LSETUP ( l3e , l3e ) LC0 = P1; -l3e:R7 += 1; - -EXCPT 0x6; // Will kill Lsetup in EX2 when stalled - R0 = [ P2 ++ ]; -LSETUP ( m3e , m3e ) LC1 = P1; -m3e:R7 += 1; - -EXCPT 0x6; // Will kill Lsetup in EX1 when stalled - R0 = [ P2 ++ ]; -NOP; -LSETUP ( l4e , l4e ) LC0 = P1; -l4e:R7 += 1; - -EXCPT 0x6; // Will kill Lsetup in EX1 when stalled - R0 = [ P2 ++ ]; -NOP; -LSETUP ( m4e , m4e ) LC1 = P1; -m4e:R7 += 1; - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_0x00F00200,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.section MEM_0x00F00210,"aw" - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_kill_01.S b/sim/testsuite/sim/bfin/se_loop_kill_01.S deleted file mode 100644 index 55b6273..0000000 --- a/sim/testsuite/sim/bfin/se_loop_kill_01.S +++ /dev/null @@ -1,521 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_kill_01/se_loop_kill_01.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE 0x00000500 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef IMASK -#define IMASK 0xFFE02104 -#endif -#ifndef DMEM_CONTROL -#define DMEM_CONTROL 0xFFE00004 -#endif -#ifndef DCPLB_ADDR0 -#define DCPLB_ADDR0 0xFFE00100 -#endif -#ifndef DCPLB_DATA0 -#define DCPLB_DATA0 0xFFE00200 -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - P1 = 0x3 (Z); - P2 = 0x0200 (Z); - P2.H = 0x00F0; - [ -- SP ] = P0; - [ -- SP ] = P0; -SSYNC; - -LD32_LABEL(r0, l0t); -LD32_LABEL(r1, l0b); - [ -- SP ] = R0; - [ -- SP ] = R1; -SSYNC; -LB0 = [sp++]; -EXCPT 0x5; // Will kill mv2lc in EX3 -LC0 = P0; -LT0 = [sp++]; -l0t:R3 += 3; - R1 += 1; - R4 += 4; - R5 += 5; - R6 += 6; -l0b:R2 += 2; - -LD32_LABEL(r0, l2t); -LD32_LABEL(r1, l2b); -LT0 = r0; -LB0 = r1; -EXCPT 0x5; // Will kill mv2lc in EX3 when stalled -LC0 = [ SP ++ ]; -l2t:R3 += 3; - R1 += 1; - R4 += 4; - R5 += 5; - R6 += 6; -l2b:R2 += 2; - -LD32_LABEL(r0, l1t); -LD32_LABEL(r1, l1b); -LT1 = r0; -LB1 = r1; -EXCPT 0x5; // Will kill mv2lc in EX3 when stalled -LC1 = [ SP ++ ]; -l1t:R3 += 3; - R1 += 1; - R4 += 4; - R5 += 5; - R6 += 6; -l1b:R2 += 2; - -LD32_LABEL(r0, l3t); -LD32_LABEL(r1, l3b); -LT1 = r0; -LB1 = r1; -EXCPT 0x5; // Will kill mv2lc in EX3 -NOP; -LC1 = P0; -l3t:R3 += 3; - R1 += 1; - R4 += 4; - R5 += 5; - R6 += 6; -l3b:R2 += 2; - -EXCPT 0x6; // Will kill Lsetup in EX2 -NOP; -NOP; -LSETUP ( l1e , l1e ) LC0 = P1; -l1e:R7 += 1; - -EXCPT 0x6; // Will kill Lsetup in EX2 -NOP; -NOP; -LSETUP ( m1e , m1e ) LC1 = P1; -m1e:R7 += 1; - -EXCPT 0x6; // Will kill Lsetup in EX1 -NOP; -NOP; -NOP; -LSETUP ( l2e , l2e ) LC0 = P1; -l2e:R7 += 1; - -EXCPT 0x6; // Will kill Lsetup in EX1 -NOP; -NOP; -NOP; -LSETUP ( m2e , m2e ) LC1 = P1; -m2e:R7 += 1; - -NOP; -NOP; -NOP; - -EXCPT 0x6; // Will kill Lsetup in EX2 when stalled - R0 = [ P2 ++ ]; -LSETUP ( l3e , l3e ) LC0 = P1; -l3e:R7 += 1; - -EXCPT 0x6; // Will kill Lsetup in EX2 when stalled - R0 = [ P2 ++ ]; -LSETUP ( m3e , m3e ) LC1 = P1; -m3e:R7 += 1; - -EXCPT 0x6; // Will kill Lsetup in EX1 when stalled - R0 = [ P2 ++ ]; -NOP; -LSETUP ( l4e , l4e ) LC0 = P1; -l4e:R7 += 1; - -EXCPT 0x6; // Will kill Lsetup in EX1 when stalled - R0 = [ P2 ++ ]; -NOP; -LSETUP ( m4e , m4e ) LC1 = P1; -m4e:R7 += 1; - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_0x00F00200,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.section MEM_0x00F00210,"aw" - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_kill_dcr.S b/sim/testsuite/sim/bfin/se_loop_kill_dcr.S deleted file mode 100644 index 13bf16a..0000000 --- a/sim/testsuite/sim/bfin/se_loop_kill_dcr.S +++ /dev/null @@ -1,914 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr/se_loop_kill_dcr.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x1 (Z); - P1 = 0x2 (Z); - P2 = 0x3 (Z); - P3 = 0x4 (Z); - P4 = 0x5 (Z); - -///////////////////////////////////////////////////////////////////////////// -// Loop 0 (with Kill WB) -///////////////////////////////////////////////////////////////////////////// - - // Kill Valid Dcr in WB -LSETUP ( L0T , L0T ) LC0 = P0; -EXCPT 0x5; -L0T:R0 += 5; - - // Kill Valid Dcr in EX3 -LSETUP ( L1T , L1B ) LC0 = P0; -EXCPT 0x5; -L1T:R0 += 5; -L1B:R1 += 4; - - // Kill Valid Dcr in EX2 -LSETUP ( L2T , L2B ) LC0 = P0; -EXCPT 0x5; -L2T:R0 += 5; - R1 += 4; -L2B:R2 += 3; - - // Kill Valid Dcr in EX1 -LSETUP ( L3T , L3B ) LC0 = P0; -EXCPT 0x5; -L3T:R0 += 5; - R1 += 4; - R2 += 3; -L3B:R3 += 2; - - // Kill Valid Dcr in AC -LSETUP ( L4T , L4B ) LC0 = P0; -EXCPT 0x5; -L4T:R0 += 5; - R1 += 4; - R2 += 3; - R3 += 2; -L4B:R4 += 1; - - // Kill Valid Dcr in WB, EX3 -LSETUP ( L5T , L5T ) LC0 = P1; -EXCPT 0x5; -L5T:R1 += 5; - - // Kill Valid Dcr in EX3, EX2 -LSETUP ( L6T , L6T ) LC0 = P1; -EXCPT 0x5; -NOP; -L6T:R2 += 5; - - // Kill Valid Dcr in EX2, EX1 -LSETUP ( L7T , L7T ) LC0 = P1; -EXCPT 0x5; -NOP; -NOP; -L7T:R3 += 5; - - // Kill Valid Dcr in EX1, AC -LSETUP ( L8T , L8T ) LC0 = P1; -EXCPT 0x5; -NOP; -NOP; -NOP; -L8T:R4 += 5; - - // Kill Valid Dcr in WB, EX3, EX2 -LSETUP ( L9T , L9T ) LC0 = P2; -EXCPT 0x5; -L9T:R5 += 5; - - // Kill Valid Dcr in EX3, EX2, EX1 -LSETUP ( LAT , LAT ) LC0 = P2; -EXCPT 0x5; -NOP; -LAT: - R6 += 6; - - // Kill Valid Dcr in EX2, EX1, AC -LSETUP ( LBT , LBT ) LC0 = P2; -EXCPT 0x5; -NOP; -NOP; -LBT: - R5 += 5; - - // Kill Valid Dcr in WB, EX3, EX2, EX1 -LSETUP ( LCT , LCT ) LC0 = P3; -EXCPT 0x5; -LCT: - R7 += 7; - - // Kill Valid Dcr in EX3, EX2, EX1, AC -LSETUP ( LDT , LDT ) LC0 = P3; -EXCPT 0x5; -NOP; -LDT: - R0 += 7; - - // Kill Valid Dcr in WB, EX3, EX2, EX1, AC -LSETUP ( LET , LET ) LC0 = P4; -EXCPT 0x5; -LET: - R1 += 1; - - // Kill Valid Dcr in WB, EX2 -LSETUP ( LFT , LFB ) LC0 = P1; -LFT: - EXCPT 0x5; -LFB: - R1 += 2; - - // Kill Valid Dcr in WB, EX1 -LSETUP ( LGT , LGB ) LC0 = P1; -LGT: - R2 += 3; -EXCPT 0x5; -LGB: - R1 += 2; - - // Kill Valid Dcr in WB, AC -LSETUP ( LHT , LHB ) LC0 = P1; -LHT: - R2 += 3; - R3 += 4; -EXCPT 0x5; -LHB: - R1 += 2; - - // Kill Valid Dcr in EX3, EX1 -LSETUP ( LIT , LIB ) LC0 = P1; -EXCPT 0x5; -LIT: - R2 += 1; -LIB: - R1 += 2; - - // Kill Valid Dcr in EX3, AC -LSETUP ( LJT , LJB ) LC0 = P1; -LJT: - EXCPT 0x5; - R2 += 1; -LJB: - R1 += 2; - - // Kill Valid Dcr in EX2, AC -LSETUP ( LKT , LKB ) LC0 = P1; -EXCPT 0x5; -NOP; -LKT: - R2 += 1; -LKB: - R1 += 2; - - // Kill Valid Dcr in WB, EX2, AC -LSETUP ( LLT , LLB ) LC0 = P2; -LLT: - EXCPT 0x5; -LLB: - R2 += 2; - - -///////////////////////////////////////////////////////////////////////////// -// Loop 1 (with Kill WB) -///////////////////////////////////////////////////////////////////////////// - - // Kill Valid Dcr in WB -LSETUP ( M0T , M0T ) LC1 = P0; -EXCPT 0x5; -M0T:R0 += 5; - - // Kill Valid Dcr in EX3 -LSETUP ( M1T , M1B ) LC1 = P0; -EXCPT 0x5; -M1T:R0 += 5; -M1B:R1 += 4; - - // Kill Valid Dcr in EX2 -LSETUP ( M2T , M2B ) LC1 = P0; -EXCPT 0x5; -M2T:R0 += 5; - R1 += 4; -M2B:R2 += 3; - - // Kill Valid Dcr in EX1 -LSETUP ( M3T , M3B ) LC1 = P0; -EXCPT 0x5; -M3T:R0 += 5; - R1 += 4; - R2 += 3; -M3B:R3 += 2; - - // Kill Valid Dcr in AC -LSETUP ( M4T , M4B ) LC1 = P0; -EXCPT 0x5; -M4T:R0 += 5; - R1 += 4; - R2 += 3; - R3 += 2; -M4B:R4 += 1; - - // Kill Valid Dcr in WB, EX3 -LSETUP ( M5T , M5T ) LC1 = P1; -EXCPT 0x5; -M5T:R1 += 5; - - // Kill Valid Dcr in EX3, EX2 -LSETUP ( M6T , M6T ) LC1 = P1; -EXCPT 0x5; -NOP; -M6T:R2 += 5; - - // Kill Valid Dcr in EX2, EX1 -LSETUP ( M7T , M7T ) LC1 = P1; -EXCPT 0x5; -NOP; -NOP; -M7T:R3 += 5; - - // Kill Valid Dcr in EX1, AC -LSETUP ( M8T , M8T ) LC1 = P1; -EXCPT 0x5; -NOP; -NOP; -NOP; -M8T:R4 += 5; - - // Kill Valid Dcr in WB, EX3, EX2 -LSETUP ( M9T , M9T ) LC1 = P2; -EXCPT 0x5; -M9T:R5 += 5; - - // Kill Valid Dcr in EX3, EX2, EX1 -LSETUP ( MAT , MAT ) LC1 = P2; -EXCPT 0x5; -NOP; -MAT: - R6 += 6; - - // Kill Valid Dcr in EX2, EX1, AC -LSETUP ( MBT , MBT ) LC1 = P2; -EXCPT 0x5; -NOP; -NOP; -MBT: - R5 += 5; - - // Kill Valid Dcr in WB, EX3, EX2, EX1 -LSETUP ( MCT , MCT ) LC1 = P3; -EXCPT 0x5; -MCT: - R7 += 7; - - // Kill Valid Dcr in EX3, EX2, EX1, AC -LSETUP ( MDT , MDT ) LC1 = P3; -EXCPT 0x5; -NOP; -MDT: - R0 += 7; - - // Kill Valid Dcr in WB, EX3, EX2, EX1, AC -LSETUP ( MET , MET ) LC1 = P4; -EXCPT 0x5; -MET: - R1 += 1; - - // Kill Valid Dcr in WB, EX2 -LSETUP ( MFT , MFB ) LC1 = P1; -MFT: - EXCPT 0x5; -MFB: - R1 += 2; - - // Kill Valid Dcr in WB, EX1 -LSETUP ( MGT , MGB ) LC1 = P1; -MGT: - R2 += 3; -EXCPT 0x5; -MGB: - R1 += 2; - - // Kill Valid Dcr in WB, AC -LSETUP ( MHT , MHB ) LC1 = P1; -MHT: - R2 += 3; - R3 += 4; -EXCPT 0x5; -MHB: - R1 += 2; - - // Kill Valid Dcr in EX3, EX1 -LSETUP ( MIT , MIB ) LC1 = P1; -EXCPT 0x5; -MIT: - R2 += 1; -MIB: - R1 += 2; - - // Kill Valid Dcr in EX3, AC -LSETUP ( MJT , MJB ) LC1 = P1; -MJT: - EXCPT 0x5; - R2 += 1; -MJB: - R1 += 2; - - // Kill Valid Dcr in EX2, AC -LSETUP ( MKT , MKB ) LC1 = P1; -EXCPT 0x5; -NOP; -MKT: - R2 += 1; -MKB: - R1 += 2; - - // Kill Valid Dcr in WB, EX2, AC -LSETUP ( MLT , MLB ) LC1 = P2; -MLT: - EXCPT 0x5; -MLB: - R2 += 2; - -///////////////////////////////////////////////////////////////////////////// -// Loop 0 (with Kill EX3) -///////////////////////////////////////////////////////////////////////////// - - // Kill Valid Dcr in EX3 -LSETUP ( N1T , N1T ) LC0 = P0; -CSYNC; -N1T:R0 += 5; - - // Kill Valid Dcr in EX2 -LSETUP ( N2T , N2B ) LC0 = P0; -CSYNC; -N2T:R0 += 5; -N2B:R2 += 3; - - // Kill Valid Dcr in EX1 -LSETUP ( N3T , N3B ) LC0 = P0; -CSYNC; -N3T:R0 += 5; - R2 += 3; -N3B:R3 += 2; - - // Kill Valid Dcr in AC -LSETUP ( N4T , N4B ) LC0 = P0; -CSYNC; -N4T:R0 += 5; - R2 += 3; - R3 += 2; -N4B:R4 += 1; - - // Kill Valid Dcr in EX3, EX2 -LSETUP ( N6T , N6T ) LC0 = P1; -CSYNC; -N6T:R2 += 5; - - // Kill Valid Dcr in EX2, EX1 -LSETUP ( N7T , N7T ) LC0 = P1; -CSYNC; -NOP; -N7T:R3 += 5; - - // Kill Valid Dcr in EX1, AC -LSETUP ( N8T , N8T ) LC0 = P1; -CSYNC; -NOP; -NOP; -N8T:R4 += 5; - - // Kill Valid Dcr in EX3, EX2, EX1 -LSETUP ( NAT , NAT ) LC0 = P2; -CSYNC; -NAT: - R6 += 6; - - // Kill Valid Dcr in EX2, EX1, AC -LSETUP ( NBT , NBT ) LC0 = P2; -CSYNC; -NOP; -NBT: - R5 += 5; - - // Kill Valid Dcr in EX3, EX2, EX1, AC -LSETUP ( NDT , NDT ) LC0 = P3; -CSYNC; -NDT: - R0 += 7; - - // Kill Valid Dcr in EX3, EX1 -LSETUP ( NIT , NIB ) LC0 = P1; -NIT: - CSYNC; -NIB: - R1 += 2; - - // Kill Valid Dcr in EX3, AC -LSETUP ( NJT , NJB ) LC0 = P1; -NJT: - R2 += 1; -CSYNC; -NJB: - R1 += 2; - - // Kill Valid Dcr in EX2, AC -LSETUP ( NKT , NKB ) LC0 = P1; -CSYNC; -NKT: - R2 += 1; -NKB: - R1 += 2; - -///////////////////////////////////////////////////////////////////////////// -// Loop 1 (with Kill EX3) -///////////////////////////////////////////////////////////////////////////// - - // Kill Valid Dcr in EX3 -LSETUP ( O1T , O1T ) LC1 = P0; -CSYNC; -O1T:R0 += 5; - - // Kill Valid Dcr in EX2 -LSETUP ( O2T , O2B ) LC1 = P0; -CSYNC; -O2T:R0 += 5; -O2B:R2 += 3; - - // Kill Valid Dcr in EX1 -LSETUP ( O3T , O3B ) LC1 = P0; -CSYNC; -O3T:R0 += 5; - R2 += 3; -O3B:R3 += 2; - - // Kill Valid Dcr in AC -LSETUP ( O4T , O4B ) LC1 = P0; -CSYNC; -O4T:R0 += 5; - R2 += 3; - R3 += 2; -O4B:R4 += 1; - - // Kill Valid Dcr in EX3, EX2 -LSETUP ( O6T , O6T ) LC1 = P1; -CSYNC; -O6T:R2 += 5; - - // Kill Valid Dcr in EX2, EX1 -LSETUP ( O7T , O7T ) LC1 = P1; -CSYNC; -NOP; -O7T:R3 += 5; - - // Kill Valid Dcr in EX1, AC -LSETUP ( O8T , O8T ) LC1 = P1; -CSYNC; -NOP; -NOP; -O8T:R4 += 5; - - // Kill Valid Dcr in EX3, EX2, EX1 -LSETUP ( OAT , OAT ) LC1 = P2; -CSYNC; -OAT: - R6 += 6; - - // Kill Valid Dcr in EX2, EX1, AC -LSETUP ( OBT , OBT ) LC1 = P2; -CSYNC; -NOP; -OBT: - R5 += 5; - - // Kill Valid Dcr in EX3, EX2, EX1, AC -LSETUP ( ODT , ODT ) LC1 = P3; -CSYNC; -ODT: - R0 += 7; - - // Kill Valid Dcr in EX3, EX1 -LSETUP ( OIT , OIB ) LC1 = P1; -OIT: - CSYNC; -OIB: - R1 += 2; - - // Kill Valid Dcr in EX3, AC -LSETUP ( OJT , OJB ) LC1 = P1; -OJT: - R2 += 1; -CSYNC; -OJB: - R1 += 2; - - // Kill Valid Dcr in EX2, AC -LSETUP ( OKT , OKB ) LC1 = P1; -CSYNC; -OKT: - R2 += 1; -OKB: - R1 += 2; - -///////////////////////////////////////////////////////////////////////////// -// Loop 0 (with Kill AC) -///////////////////////////////////////////////////////////////////////////// - - // Kill Valid Dcr in AC -LSETUP ( P4T , P4T ) LC0 = P0; -JUMP.S 2; -P4T:R0 += 5; - -///////////////////////////////////////////////////////////////////////////// -// Loop 1 (with Kill AC) -///////////////////////////////////////////////////////////////////////////// - - // Kill Valid Dcr in AC -LSETUP ( Q4T , Q4T ) LC1 = P0; -JUMP.S 2; -Q4T:R0 += 5; - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_kill_dcr_01.S b/sim/testsuite/sim/bfin/se_loop_kill_dcr_01.S deleted file mode 100644 index 39a2e8d..0000000 --- a/sim/testsuite/sim/bfin/se_loop_kill_dcr_01.S +++ /dev/null @@ -1,917 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr_01/se_loop_kill_dcr_01.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x1 (Z); - P1 = 0x2 (Z); - P2 = 0x3 (Z); - P3 = 0x4 (Z); - P4 = 0x5 (Z); - -///////////////////////////////////////////////////////////////////////////// -// Loop 0 (with Kill WB) -///////////////////////////////////////////////////////////////////////////// - - // Kill Valid Dcr in WB -LSETUP ( L0T , L0T ) LC0 = P0; -EXCPT 0x5; -L0T:R0 += 5; - - // Kill Valid Dcr in EX3 -LSETUP ( L1T , L1B ) LC0 = P0; -EXCPT 0x5; -L1T:R0 += 5; -L1B:R1 += 4; - - // Kill Valid Dcr in EX2 -LSETUP ( L2T , L2B ) LC0 = P0; -EXCPT 0x5; -L2T:R0 += 5; - R1 += 4; -L2B:R2 += 3; - - // Kill Valid Dcr in EX1 -LSETUP ( L3T , L3B ) LC0 = P0; -EXCPT 0x5; -L3T:R0 += 5; - R1 += 4; - R2 += 3; -L3B:R3 += 2; - - // Kill Valid Dcr in AC -LSETUP ( L4T , L4B ) LC0 = P0; -EXCPT 0x5; -L4T:R0 += 5; - R1 += 4; - R2 += 3; - R3 += 2; -L4B:R4 += 1; - - // Kill Valid Dcr in WB, EX3 -LSETUP ( L5T , L5T ) LC0 = P1; -EXCPT 0x5; -L5T:R1 += 5; - - // Kill Valid Dcr in EX3, EX2 -LSETUP ( L6T , L6T ) LC0 = P1; -EXCPT 0x5; -NOP; -L6T:R2 += 5; - - // Kill Valid Dcr in EX2, EX1 -LSETUP ( L7T , L7T ) LC0 = P1; -EXCPT 0x5; -NOP; -NOP; -L7T:R3 += 5; - - // Kill Valid Dcr in EX1, AC -LSETUP ( L8T , L8T ) LC0 = P1; -EXCPT 0x5; -NOP; -NOP; -NOP; -L8T:R4 += 5; - - // Kill Valid Dcr in WB, EX3, EX2 -LSETUP ( L9T , L9T ) LC0 = P2; -EXCPT 0x5; -L9T:R5 += 5; - - // Kill Valid Dcr in EX3, EX2, EX1 -LSETUP ( LAT , LAT ) LC0 = P2; -EXCPT 0x5; -NOP; -LAT: - R6 += 6; - - // Kill Valid Dcr in EX2, EX1, AC -LSETUP ( LBT , LBT ) LC0 = P2; -EXCPT 0x5; -NOP; -NOP; -LBT: - R5 += 5; - - // Kill Valid Dcr in WB, EX3, EX2, EX1 -LSETUP ( LCT , LCT ) LC0 = P3; -EXCPT 0x5; -LCT: - R7 += 7; - - // Kill Valid Dcr in EX3, EX2, EX1, AC -LSETUP ( LDT , LDT ) LC0 = P3; -EXCPT 0x5; -NOP; -LDT: - R0 += 7; - - // Kill Valid Dcr in WB, EX3, EX2, EX1, AC -LSETUP ( LET , LET ) LC0 = P4; -EXCPT 0x5; -LET: - R1 += 1; - - // Kill Valid Dcr in WB, EX2 -LSETUP ( LFT , LFB ) LC0 = P1; -LFT: - EXCPT 0x5; -LFB: - R1 += 2; - - // Kill Valid Dcr in WB, EX1 -LSETUP ( LGT , LGB ) LC0 = P1; -LGT: - R2 += 3; -EXCPT 0x5; -LGB: - R1 += 2; - - // Kill Valid Dcr in WB, AC -LSETUP ( LHT , LHB ) LC0 = P1; -LHT: - R2 += 3; - R3 += 4; -EXCPT 0x5; -LHB: - R1 += 2; - - // Kill Valid Dcr in EX3, EX1 -LSETUP ( LIT , LIB ) LC0 = P1; -EXCPT 0x5; -LIT: - R2 += 1; -LIB: - R1 += 2; - - // Kill Valid Dcr in EX3, AC -LSETUP ( LJT , LJB ) LC0 = P1; -LJT: - EXCPT 0x5; - R2 += 1; -LJB: - R1 += 2; - - // Kill Valid Dcr in EX2, AC -LSETUP ( LKT , LKB ) LC0 = P1; -EXCPT 0x5; -NOP; -LKT: - R2 += 1; -LKB: - R1 += 2; - - // Kill Valid Dcr in WB, EX2, AC -LSETUP ( LLT , LLB ) LC0 = P2; -LLT: - EXCPT 0x5; -LLB: - R2 += 2; - - -///////////////////////////////////////////////////////////////////////////// -// Loop 1 (with Kill WB) -///////////////////////////////////////////////////////////////////////////// - - // Kill Valid Dcr in WB -LSETUP ( M0T , M0T ) LC1 = P0; -EXCPT 0x5; -M0T:R0 += 5; - - // Kill Valid Dcr in EX3 -LSETUP ( M1T , M1B ) LC1 = P0; -EXCPT 0x5; -M1T:R0 += 5; -M1B:R1 += 4; - - // Kill Valid Dcr in EX2 -LSETUP ( M2T , M2B ) LC1 = P0; -EXCPT 0x5; -M2T:R0 += 5; - R1 += 4; -M2B:R2 += 3; - - // Kill Valid Dcr in EX1 -LSETUP ( M3T , M3B ) LC1 = P0; -EXCPT 0x5; -M3T:R0 += 5; - R1 += 4; - R2 += 3; -M3B:R3 += 2; - - // Kill Valid Dcr in AC -LSETUP ( M4T , M4B ) LC1 = P0; -EXCPT 0x5; -M4T:R0 += 5; - R1 += 4; - R2 += 3; - R3 += 2; -M4B:R4 += 1; - - // Kill Valid Dcr in WB, EX3 -LSETUP ( M5T , M5T ) LC1 = P1; -EXCPT 0x5; -M5T:R1 += 5; - - // Kill Valid Dcr in EX3, EX2 -LSETUP ( M6T , M6T ) LC1 = P1; -EXCPT 0x5; -NOP; -M6T:R2 += 5; - - // Kill Valid Dcr in EX2, EX1 -LSETUP ( M7T , M7T ) LC1 = P1; -EXCPT 0x5; -NOP; -NOP; -M7T:R3 += 5; - - // Kill Valid Dcr in EX1, AC -LSETUP ( M8T , M8T ) LC1 = P1; -EXCPT 0x5; -NOP; -NOP; -NOP; -M8T:R4 += 5; - - // Kill Valid Dcr in WB, EX3, EX2 -LSETUP ( M9T , M9T ) LC1 = P2; -EXCPT 0x5; -M9T:R5 += 5; - - // Kill Valid Dcr in EX3, EX2, EX1 -LSETUP ( MAT , MAT ) LC1 = P2; -EXCPT 0x5; -NOP; -MAT: - R6 += 6; - - // Kill Valid Dcr in EX2, EX1, AC -LSETUP ( MBT , MBT ) LC1 = P2; -EXCPT 0x5; -NOP; -NOP; -MBT: - R5 += 5; - - // Kill Valid Dcr in WB, EX3, EX2, EX1 -LSETUP ( MCT , MCT ) LC1 = P3; -EXCPT 0x5; -MCT: - R7 += 7; - - // Kill Valid Dcr in EX3, EX2, EX1, AC -LSETUP ( MDT , MDT ) LC1 = P3; -EXCPT 0x5; -NOP; -MDT: - R0 += 7; - - // Kill Valid Dcr in WB, EX3, EX2, EX1, AC -LSETUP ( MET , MET ) LC1 = P4; -EXCPT 0x5; -MET: - R1 += 1; - - // Kill Valid Dcr in WB, EX2 -LSETUP ( MFT , MFB ) LC1 = P1; -MFT: - EXCPT 0x5; -MFB: - R1 += 2; - - // Kill Valid Dcr in WB, EX1 -LSETUP ( MGT , MGB ) LC1 = P1; -MGT: - R2 += 3; -EXCPT 0x5; -MGB: - R1 += 2; - - // Kill Valid Dcr in WB, AC -LSETUP ( MHT , MHB ) LC1 = P1; -MHT: - R2 += 3; - R3 += 4; -EXCPT 0x5; -MHB: - R1 += 2; - - // Kill Valid Dcr in EX3, EX1 -LSETUP ( MIT , MIB ) LC1 = P1; -EXCPT 0x5; -MIT: - R2 += 1; -MIB: - R1 += 2; - - // Kill Valid Dcr in EX3, AC -LSETUP ( MJT , MJB ) LC1 = P1; -MJT: - EXCPT 0x5; - R2 += 1; -MJB: - R1 += 2; - - // Kill Valid Dcr in EX2, AC -LSETUP ( MKT , MKB ) LC1 = P1; -EXCPT 0x5; -NOP; -MKT: - R2 += 1; -MKB: - R1 += 2; - - // Kill Valid Dcr in WB, EX2, AC -LSETUP ( MLT , MLB ) LC1 = P2; -MLT: - EXCPT 0x5; -MLB: - R2 += 2; - -///////////////////////////////////////////////////////////////////////////// -// Loop 0 (with Kill EX3) -///////////////////////////////////////////////////////////////////////////// - - R0 = 1; -CC = R0; - - // Kill %Valid Dcr in EX3 -LSETUP ( N1T , N1T ) LC0 = P0; -IF CC JUMP 2; -N1T:R0 += 5; - - // Kill Valid Dcr in EX2 -LSETUP ( N2T , N2B ) LC0 = P0; -IF CC JUMP 2; -N2T:R0 += 5; -N2B:R2 += 3; - - // Kill Valid Dcr in EX1 -LSETUP ( N3T , N3B ) LC0 = P0; -IF CC JUMP 2; -N3T:R0 += 5; - R2 += 3; -N3B:R3 += 2; - - // Kill Valid Dcr in AC -LSETUP ( N4T , N4B ) LC0 = P0; -IF CC JUMP 2; -N4T:R0 += 5; - R2 += 3; - R3 += 2; -N4B:R4 += 1; - - // Kill Valid Dcr in EX3, EX2 -LSETUP ( N6T , N6T ) LC0 = P1; -IF CC JUMP 2; -N6T:R2 += 5; - - // Kill Valid Dcr in EX2, EX1 -LSETUP ( N7T , N7T ) LC0 = P1; -IF CC JUMP 2; -NOP; -N7T:R3 += 5; - - // Kill Valid Dcr in EX1, AC -LSETUP ( N8T , N8T ) LC0 = P1; -IF CC JUMP 2; -NOP; -NOP; -N8T:R4 += 5; - - // Kill Valid Dcr in EX3, EX2, EX1 -LSETUP ( NAT , NAT ) LC0 = P2; -IF CC JUMP 2; -NAT: - R6 += 6; - - // Kill Valid Dcr in EX2, EX1, AC -LSETUP ( NBT , NBT ) LC0 = P2; -IF CC JUMP 2; -NOP; -NBT: - R5 += 5; - - // Kill Valid Dcr in EX3, EX2, EX1, AC -LSETUP ( NDT , NDT ) LC0 = P3; -IF CC JUMP 2; -NDT: - R0 += 7; - - // Kill Valid Dcr in EX3, EX1 -LSETUP ( NIT , NIB ) LC0 = P1; -NIT: - IF CC JUMP 2; -NIB: - R1 += 2; - - // Kill Valid Dcr in EX3, AC -LSETUP ( NJT , NJB ) LC0 = P1; -NJT: - R2 += 1; -IF CC JUMP 2; -NJB: - R1 += 2; - - // Kill Valid Dcr in EX2, AC -LSETUP ( NKT , NKB ) LC0 = P1; -IF CC JUMP 2; -NKT: - R2 += 1; -NKB: - R1 += 2; - -///////////////////////////////////////////////////////////////////////////// -// Loop 1 (with Kill EX3) -///////////////////////////////////////////////////////////////////////////// - - // Kill %Valid Dcr in EX3 -LSETUP ( O1T , O1T ) LC1 = P0; -IF CC JUMP 2; -O1T:R0 += 5; - - // Kill Valid Dcr in EX2 -LSETUP ( O2T , O2B ) LC1 = P0; -IF CC JUMP 2; -O2T:R0 += 5; -O2B:R2 += 3; - - // Kill Valid Dcr in EX1 -LSETUP ( O3T , O3B ) LC1 = P0; -IF CC JUMP 2; -O3T:R0 += 5; - R2 += 3; -O3B:R3 += 2; - - // Kill Valid Dcr in AC -LSETUP ( O4T , O4B ) LC1 = P0; -IF CC JUMP 2; -O4T:R0 += 5; - R2 += 3; - R3 += 2; -O4B:R4 += 1; - - // Kill Valid Dcr in EX3, EX2 -LSETUP ( O6T , O6T ) LC1 = P1; -IF CC JUMP 2; -O6T:R2 += 5; - - // Kill Valid Dcr in EX2, EX1 -LSETUP ( O7T , O7T ) LC1 = P1; -IF CC JUMP 2; -NOP; -O7T:R3 += 5; - - // Kill Valid Dcr in EX1, AC -LSETUP ( O8T , O8T ) LC1 = P1; -IF CC JUMP 2; -NOP; -NOP; -O8T:R4 += 5; - - // Kill Valid Dcr in EX3, EX2, EX1 -LSETUP ( OAT , OAT ) LC1 = P2; -IF CC JUMP 2; -OAT: - R6 += 6; - - // Kill Valid Dcr in EX2, EX1, AC -LSETUP ( OBT , OBT ) LC1 = P2; -IF CC JUMP 2; -NOP; -OBT: - R5 += 5; - - // Kill Valid Dcr in EX3, EX2, EX1, AC -LSETUP ( ODT , ODT ) LC1 = P3; -IF CC JUMP 2; -ODT: - R0 += 7; - - // Kill Valid Dcr in EX3, EX1 -LSETUP ( OIT , OIB ) LC1 = P1; -OIT: - IF CC JUMP 2; -OIB: - R1 += 2; - - // Kill Valid Dcr in EX3, AC -LSETUP ( OJT , OJB ) LC1 = P1; -OJT: - R2 += 1; -IF CC JUMP 2; -OJB: - R1 += 2; - - // Kill Valid Dcr in EX2, AC -LSETUP ( OKT , OKB ) LC1 = P1; -IF CC JUMP 2; -OKT: - R2 += 1; -OKB: - R1 += 2; - -///////////////////////////////////////////////////////////////////////////// -// Loop 0 (with Kill AC) -///////////////////////////////////////////////////////////////////////////// - - // Kill Valid Dcr in AC -LSETUP ( P4T , P4T ) LC0 = P0; -JUMP.S 2; -P4T:R0 += 5; - -///////////////////////////////////////////////////////////////////////////// -// Loop 1 (with Kill AC) -///////////////////////////////////////////////////////////////////////////// - - // Kill Valid Dcr in AC -LSETUP ( Q4T , Q4T ) LC1 = P0; -JUMP.S 2; -Q4T:R0 += 5; - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_lr.S b/sim/testsuite/sim/bfin/se_loop_lr.S deleted file mode 100644 index 71e0308..0000000 --- a/sim/testsuite/sim/bfin/se_loop_lr.S +++ /dev/null @@ -1,507 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_lr/se_loop_lr.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - P1 = 0x3 (Z); - - -LD32_LABEL(r0, l1e); -LSETUP ( l1e , l1e ) LC0 = P1; -l1s:LT0 = R0; -l1e:[ -- SP ] = R7; - - -LD32_LABEL(r0, ls1); -LSETUP ( l2s , l2e ) LC0 = P0; -l2s:LB0 = R0; -ls1:R6 += 2; -l2e:[ -- SP ] = ( R7:5 ); - - -LD32_LABEL(r0, ls2); -LD32_LABEL(r1, ls3); -LSETUP ( l3s , l3e ) LC0 = P0; -l3s:LT0 = R0; -ls2:LB0 = R1; -ls3:R7 += 3; -l3e:[ -- SP ] = ( R7:5 ); - - -LD32_LABEL(r0, ls4); -LD32_LABEL(r1, ls5); -LSETUP ( l4s , l4e ) LC0 = P0; -l4s:LT0 = R0; -LB0 = r1; -ls4:R7 += 3; -ls5:R4 += 4; -l4e:[ -- SP ] = ( R7:4 ); - -LD32_LABEL(r0, ls6); -LD32_LABEL(r1, ls7); -LSETUP ( l5s , l5e ) LC0 = P0; -l5s:LB0 = R1; -LT0 = r0; -ls6:R7 += 3; - R4 += 4; - R5 += 3; -ls7:R6 += 3; -l5e:[ -- SP ] = ( R7:4 ); - -LD32_LABEL(r0, ls8); -LD32_LABEL(r1, ls9); -LSETUP ( l6s , l6e ) LC0 = P0; -l6s:R5 += 1; -LB0 = r1; -LT0 = r0; -ls8:R7 += 3; - R4 += 4; - R5 += 3; - R7 += 5; -ls9:R7 += 5; -l6e:[ -- SP ] = ( R7:4 ); - - -NOP; -NOP; - -LD32_LABEL(r0, m1e); -LSETUP ( m1e , m1e ) LC1 = P1; -m1s:LT0 = R0; -m1e:[ -- SP ] = R7; - - -LD32_LABEL(r0, ms1); -LSETUP ( m2s , m2e ) LC1 = P0; -m2s:LB0 = R0; -ms1:R6 += 2; -m2e:[ -- SP ] = ( R7:5 ); - - -LD32_LABEL(r0, ms2); -LD32_LABEL(r1, ms3); -LSETUP ( m3s , m3e ) LC1 = P0; -m3s:LT0 = R0; -ms2:LB0 = R1; -ms3:R7 += 3; -m3e:[ -- SP ] = ( R7:5 ); - - -LD32_LABEL(r0, ms4); -LD32_LABEL(r1, ms5); -LSETUP ( m4s , m4e ) LC1 = P0; -m4s:LT0 = R0; -LB0 = r1; -ms4:R7 += 3; -ms5:R4 += 4; -m4e:[ -- SP ] = ( R7:4 ); - -LD32_LABEL(r0, ms6); -LD32_LABEL(r1, ms7); -LSETUP ( m5s , m5e ) LC1 = P0; -m5s:LB0 = R1; -LT0 = r0; -ms6:R7 += 3; - R4 += 4; - R5 += 3; -ms7:R6 += 3; -m5e:[ -- SP ] = ( R7:4 ); - -LD32_LABEL(r0, ms8); -LD32_LABEL(r1, ms9); -LSETUP ( m6s , m6e ) LC1 = P0; -m6s:R5 += 1; -LB0 = r1; -LT0 = r0; -ms8:R7 += 3; - R4 += 4; - R5 += 3; - R7 += 5; -ms9:R7 += 5; -m6e:[ -- SP ] = ( R7:4 ); - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S b/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S deleted file mode 100644 index a3b2c24..0000000 --- a/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S +++ /dev/null @@ -1,612 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lb_stall/se_loop_mv2lb_stall.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE 0x00000500 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef IMASK -#define IMASK 0xFFE02104 -#endif -#ifndef DMEM_CONTROL -#define DMEM_CONTROL 0xFFE00004 -#endif -#ifndef DCPLB_ADDR0 -#define DCPLB_ADDR0 0xFFE00100 -#endif -#ifndef DCPLB_DATA0 -#define DCPLB_DATA0 0xFFE00200 -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - P1 = 0x3 (Z); - P2 = 0x0100 (Z); - P2.H = 0x00f0; - - // Loop 0 -LD32_LABEL(r0, L0T); -LD32_LABEL(r1, L0B); -LC0 = p1; -LT0 = r0; - R0 = [ P2 ++ ]; -LB0 = r1; -L0T:R3 += 4; - R2 += 3; - R4 += 5; - R5 += 6; - R6 += 7; -L0B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L1T); -LD32_LABEL(r1, L1B); -LT0 = r0; -LC0 = p1; - R0 = [ P2 ++ ]; -NOP; -LB0 = r1; -L1T:R4 += 5; - R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; -L1B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L2T); -LD32_LABEL(r1, L2B); -LT0 = r0; -LC0 = p1; - R0 = [ P2 ++ ]; -NOP; -NOP; -LB0 = r1; -L2T:R5 += 6; - R2 += 3; - R3 += 4; - R4 += 5; - R6 += 7; -L2B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L3T); -LD32_LABEL(r1, L3B); -LT0 = r0; -LC0 = p1; - R0 = [ P2 ++ ]; -NOP; -NOP; -NOP; -LB0 = r1; -L3T:R2 += 3; - R5 += 6; - R6 += 7; - R3 += 4; - R4 += 5; -L3B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L4T); -LD32_LABEL(r1, L4B); -LT0 = r0; -LC0 = p1; - R0 = [ P2 ++ ]; -NOP; -NOP; -NOP; -NOP; -LB0 = r1; -L4T:R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; - R4 += 5; -L4B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L5T); -LD32_LABEL(r1, L5B); - [ -- SP ] = R1; -SSYNC; -LT0 = r0; -LC0 = p0; - R0 = [ P2 ++ ]; -LB0 = [sp++]; -L5T:R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; - R4 += 5; -L5B:R7 += 8; - - - // Loop 1 -LD32_LABEL(r0, M0T); -LD32_LABEL(r1, M0B); -LT1 = r0; -LC1 = p1; - R0 = [ P2 ++ ]; -LB1 = r1; -M0T:R3 += 4; - R2 += 3; - R4 += 5; - R5 += 6; - R6 += 7; -M0B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M1T); -LD32_LABEL(r1, M1B); -LT1 = r0; -LC1 = p1; - R0 = [ P2 ++ ]; -NOP; -LB1 = r1; -M1T:R4 += 5; - R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; -M1B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M2T); -LD32_LABEL(r1, M2B); -LT1 = r0; -LC1 = p1; - R0 = [ P2 ++ ]; -NOP; -NOP; -LB1 = r1; -M2T:R5 += 6; - R2 += 3; - R3 += 4; - R4 += 5; - R6 += 7; -M2B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M3T); -LD32_LABEL(r1, M3B); -LT1 = r0; -LC1 = p1; - R0 = [ P2 ++ ]; -NOP; -NOP; -NOP; -LB1 = r1; -M3T:R2 += 3; - R5 += 6; - R6 += 7; - R3 += 4; - R4 += 5; -M3B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M4T); -LD32_LABEL(r1, M4B); -LT1 = r0; -LC1 = p1; - R0 = [ P2 ++ ]; -NOP; -NOP; -NOP; -NOP; -LB1 = r1; -M4T:R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; - R4 += 5; -M4B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M5T); -LD32_LABEL(r1, M5B); - [ -- SP ] = R1; -SSYNC; -LT1 = r0; -LC1 = p0; - R0 = [ P2 ++ ]; -LB1 = [sp++]; -M5T:R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; - R4 += 5; -M5B:R7 += 8; - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_0x00F00100,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; -.dd 0x05050505; -.dd 0x06060606; -.dd 0x07070707; -.dd 0x08080808; -.dd 0x09090909; -.dd 0x0a0a0a0a; -.dd 0x0b0b0b0b; -.dd 0x0c0c0c0c; -.dd 0x0d0d0d0d; -.dd 0x0e0e0e0e; -.dd 0x0f0f0f0f; - -// Define Kernal Stack -.section MEM_0x00F00210,"aw" - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_mv2lc.S b/sim/testsuite/sim/bfin/se_loop_mv2lc.S deleted file mode 100644 index 69adeca..0000000 --- a/sim/testsuite/sim/bfin/se_loop_mv2lc.S +++ /dev/null @@ -1,777 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lc/se_loop_mv2lc.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - P1 = 0x3 (Z); - - // Loop 0 -LD32_LABEL(r0, L0T); -LD32_LABEL(r1, L0B); -LT0 = r0; -LB0 = r1; - -LC0 = P0; -NOP; -JUMP.S 2; - -JUMP.S 6; -NOP; -LC0 = P0; -LC0 = P1; -L0T:R2 += 3; - R3 += 4; - R4 += 5; - R5 += 6; - R6 += 7; -L0B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, L1T); -LD32_LABEL(r1, L1B); -LT1 = r0; -LB1 = r1; - -LC1 = P0; -NOP; -JUMP.S 2; - -JUMP.S 6; -NOP; -LC1 = P0; -LC1 = P1; -L1T:R2 += 3; - R3 += 4; - R4 += 5; - R5 += 6; - R6 += 7; -L1B:R7 += 8; - - // Loop 0 -LSETUP ( L2T , L2T ) LC0 = P0; -NOP; -NOP; -NOP; -LC0 = P1; -L2T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; -L2B:R7 += 6; - -LC0 = P1; -NOP; -NOP; -NOP; -LSETUP ( L3T , L3T ) LC0 = P0; -L3T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; -L3B:R7 += 6; - -LSETUP ( L4T , L4B ) LC0 = P0; -NOP; -NOP; -LC0 = P1; -L4T:R2 += 1; -L4B:R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - -LC0 = P1; -NOP; -NOP; -LSETUP ( L5T , L5B ) LC0 = P0; -L5T:R2 += 1; -L5B:R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - -LSETUP ( L6T , L6B ) LC0 = P0; -NOP; -LC0 = P1; -L6T:R2 += 1; - R3 += 2; -L6B:R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - -LC0 = P1; -NOP; -LSETUP ( L7T , L7B ) LC0 = P0; -L7T:R2 += 1; - R3 += 2; -L7B:R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - -LSETUP ( L8T , L8B ) LC0 = P0; -LC0 = P1; -L8T:R2 += 1; - R3 += 2; - R4 += 3; -L8B:R5 += 4; - R6 += 5; - R7 += 6; - -LC0 = P1; -LSETUP ( L9T , L9B ) LC0 = P0; -L9T:R2 += 1; - R3 += 2; - R4 += 3; -L9B:R5 += 4; - R6 += 5; - R7 += 6; - - - // Loop 1 -LSETUP ( M2T , M2T ) LC1 = P0; -NOP; -NOP; -NOP; -LC1 = P1; -M2T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; -M2B:R7 += 6; - -LC1 = P1; -NOP; -NOP; -NOP; -LSETUP ( M3T , M3T ) LC1 = P0; -M3T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; -M3B:R7 += 6; - -LSETUP ( M4T , M4B ) LC1 = P0; -NOP; -NOP; -LC1 = P1; -M4T:R2 += 1; -M4B:R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - -LC1 = P1; -NOP; -NOP; -LSETUP ( M5T , M5B ) LC1 = P0; -M5T:R2 += 1; -M5B:R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - -LSETUP ( M6T , M6B ) LC1 = P0; -NOP; -LC1 = P1; -M6T:R2 += 1; - R3 += 2; -M6B:R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - -LC1 = P1; -NOP; -LSETUP ( M7T , M7B ) LC1 = P0; -M7T:R2 += 1; - R3 += 2; -M7B:R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - -LSETUP ( M8T , M8B ) LC1 = P0; -LC1 = P1; -M8T:R2 += 1; - R3 += 2; - R4 += 3; -M8B:R5 += 4; - R6 += 5; - R7 += 6; - -LC1 = P1; -LSETUP ( M9T , M9B ) LC1 = P0; -M9T:R2 += 1; - R3 += 2; - R4 += 3; -M9B:R5 += 4; - R6 += 5; - R7 += 6; - - // Loop 0 -LSETUP ( N2T , N2B ) LC0 = P0 >> 1; -NOP; -NOP; -NOP; -LC0 = P1; -N2T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; -N2B:R7 += 6; - -LC0 = P1; -NOP; -NOP; -NOP; -LSETUP ( N3T , N3B ) LC0 = P0 >> 1; -N3T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; -N3B:R7 += 6; - -LSETUP ( N4T , N4B ) LC0 = P0 >> 1; -NOP; -NOP; -LC0 = P1; -N4T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; -N4B:R6 += 5; - R7 += 6; - -LC0 = P1; -NOP; -NOP; -LSETUP ( N5T , N5B ) LC0 = P0 >> 1; -N5T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; -N5B:R6 += 5; - R7 += 6; - -LSETUP ( N6T , N6B ) LC0 = P0 >> 1; -NOP; -LC0 = P1; -N6T:R2 += 1; - R3 += 2; - R4 += 3; -N6B:R5 += 4; - R6 += 5; - R7 += 6; - -LC0 = P1; -NOP; -LSETUP ( N7T , N7B ) LC0 = P0 >> 1; -N7T:R2 += 1; - R3 += 2; - R4 += 3; -N7B:R5 += 4; - R6 += 5; - R7 += 6; - -LSETUP ( N8T , N8T ) LC0 = P0 >> 1; -LC0 = P1; -N8T:R2 += 1; - R3 += 2; -N8B:R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - -LC0 = P1; -LSETUP ( N9T , N9T ) LC0 = P0 >> 1; -N9T:R2 += 1; - R3 += 2; -N9B:R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - - - // Loop 1 -LSETUP ( O2T , O2B ) LC1 = P0 >> 1; -NOP; -NOP; -NOP; -LC1 = P1; -O2T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; -O2B:R7 += 6; - -LC1 = P1; -NOP; -NOP; -NOP; -LSETUP ( O3T , O3B ) LC1 = P0 >> 1; -O3T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; -O3B:R7 += 6; - -LSETUP ( O4T , O4B ) LC1 = P0 >> 1; -NOP; -NOP; -LC1 = P1; -O4T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; -O4B:R6 += 5; - R7 += 6; - -LC1 = P1; -NOP; -NOP; -LSETUP ( O5T , O5B ) LC1 = P0 >> 1; -O5T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; -O5B:R6 += 5; - R7 += 6; - -LSETUP ( O6T , O6B ) LC1 = P0 >> 1; -NOP; -LC1 = P1; -O6T:R2 += 1; - R3 += 2; - R4 += 3; -O6B:R5 += 4; - R6 += 5; - R7 += 6; - -LC1 = P1; -NOP; -LSETUP ( O7T , O7B ) LC1 = P0 >> 1; -O7T:R2 += 1; - R3 += 2; - R4 += 3; -O7B:R5 += 4; - R6 += 5; - R7 += 6; - -LSETUP ( O8T , O8T ) LC1 = P0 >> 1; -LC1 = P1; -O8T:R2 += 1; - R3 += 2; -O8B:R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - -LC1 = P1; -LSETUP ( O9T , O9T ) LC1 = P0 >> 1; -O9T:R2 += 1; - R3 += 2; -O9B:R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S b/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S deleted file mode 100644 index ecd98bf..0000000 --- a/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S +++ /dev/null @@ -1,612 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lc_stall/se_loop_mv2lc_stall.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE 0x00000500 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef IMASK -#define IMASK 0xFFE02104 -#endif -#ifndef DMEM_CONTROL -#define DMEM_CONTROL 0xFFE00004 -#endif -#ifndef DCPLB_ADDR0 -#define DCPLB_ADDR0 0xFFE00100 -#endif -#ifndef DCPLB_DATA0 -#define DCPLB_DATA0 0xFFE00200 -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - P1 = 0x3 (Z); - P2 = 0x0100 (Z); - P2.H = 0x00f0; - - // 2 pushes of P0 onto the Stack; - [ -- SP ] = P0; - [ -- SP ] = P0; - - // Loop 0 -LD32_LABEL(r0, L0T); -LD32_LABEL(r1, L0B); -LT0 = r0; -LB0 = r1; - R0 = [ P2 ++ ]; -LC0 = p1; -L0T:R3 += 4; - R2 += 3; - R4 += 5; - R5 += 6; - R6 += 7; -L0B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L1T); -LD32_LABEL(r1, L1B); -LT0 = r0; -LB0 = r1; - R0 = [ P2 ++ ]; -NOP; -LC0 = p1; -L1T:R4 += 5; - R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; -L1B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L2T); -LD32_LABEL(r1, L2B); -LT0 = r0; -LB0 = r1; - R0 = [ P2 ++ ]; -NOP; -NOP; -LC0 = p1; -L2T:R5 += 6; - R2 += 3; - R3 += 4; - R4 += 5; - R6 += 7; -L2B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L3T); -LD32_LABEL(r1, L3B); -LT0 = r0; -LB0 = r1; - R0 = [ P2 ++ ]; -NOP; -NOP; -NOP; -LC0 = p1; -L3T:R2 += 3; - R5 += 6; - R6 += 7; - R3 += 4; - R4 += 5; -L3B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L4T); -LD32_LABEL(r1, L4B); -LT0 = r0; -LB0 = r1; - R0 = [ P2 ++ ]; -NOP; -NOP; -NOP; -NOP; -LC0 = p1; -L4T:R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; - R4 += 5; -L4B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L5T); -LD32_LABEL(r1, L5B); -LT0 = r0; -LB0 = r1; - R0 = [ P2 ++ ]; -LC0 = [sp++]; -L5T:R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; - R4 += 5; -L5B:R7 += 8; - - - // Loop 1 -LD32_LABEL(r0, M0T); -LD32_LABEL(r1, M0B); -LT1 = r0; -LB1 = r1; - R0 = [ P2 ++ ]; -LC1 = p1; -M0T:R3 += 4; - R2 += 3; - R4 += 5; - R5 += 6; - R6 += 7; -M0B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M1T); -LD32_LABEL(r1, M1B); -LT1 = r0; -LB1 = r1; - R0 = [ P2 ++ ]; -NOP; -LC1 = p1; -M1T:R4 += 5; - R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; -M1B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M2T); -LD32_LABEL(r1, M2B); -LT1 = r0; -LB1 = r1; - R0 = [ P2 ++ ]; -NOP; -NOP; -LC1 = p1; -M2T:R5 += 6; - R2 += 3; - R3 += 4; - R4 += 5; - R6 += 7; -M2B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M3T); -LD32_LABEL(r1, M3B); -LT1 = r0; -LB1 = r1; - R0 = [ P2 ++ ]; -NOP; -NOP; -NOP; -LC1 = p1; -M3T:R2 += 3; - R5 += 6; - R6 += 7; - R3 += 4; - R4 += 5; -M3B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M4T); -LD32_LABEL(r1, M4B); -LT1 = r0; -LB1 = r1; - R0 = [ P2 ++ ]; -NOP; -NOP; -NOP; -NOP; -LC1 = p1; -M4T:R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; - R4 += 5; -M4B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M5T); -LD32_LABEL(r1, M5B); -LT1 = r0; -LB1 = r1; - R0 = [ P2 ++ ]; -LC1 = [sp++]; -M5T:R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; - R4 += 5; -M5B:R7 += 8; - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_0x00F00100,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; -.dd 0x05050505; -.dd 0x06060606; -.dd 0x07070707; -.dd 0x08080808; -.dd 0x09090909; -.dd 0x0a0a0a0a; -.dd 0x0b0b0b0b; -.dd 0x0c0c0c0c; -.dd 0x0d0d0d0d; -.dd 0x0e0e0e0e; -.dd 0x0f0f0f0f; - -// Define Kernal Stack -.section MEM_0x00F00210,"aw" - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S b/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S deleted file mode 100644 index 36d2d73..0000000 --- a/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S +++ /dev/null @@ -1,612 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lt_stall/se_loop_mv2lt_stall.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE 0x00000500 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef IMASK -#define IMASK 0xFFE02104 -#endif -#ifndef DMEM_CONTROL -#define DMEM_CONTROL 0xFFE00004 -#endif -#ifndef DCPLB_ADDR0 -#define DCPLB_ADDR0 0xFFE00100 -#endif -#ifndef DCPLB_DATA0 -#define DCPLB_DATA0 0xFFE00200 -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - P1 = 0x3 (Z); - P2 = 0x0100 (Z); - P2.H = 0x00f0; - - // Loop 0 -LD32_LABEL(r0, L0T); -LD32_LABEL(r1, L0B); -LC0 = p1; -LB0 = r1; - R5 = [ P2 ++ ]; -LT0 = r0; -L0T:R3 += 4; - R2 += 3; - R4 += 5; - R5 += 6; - R6 += 7; -L0B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L1T); -LD32_LABEL(r1, L1B); -LB0 = r1; -LC0 = p1; - R5 = [ P2 ++ ]; -NOP; -LT0 = r0; -L1T:R4 += 5; - R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; -L1B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L2T); -LD32_LABEL(r1, L2B); -LB0 = r1; -LC0 = p1; - R5 = [ P2 ++ ]; -NOP; -NOP; -LT0 = r0; -L2T:R5 += 6; - R2 += 3; - R3 += 4; - R4 += 5; - R6 += 7; -L2B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L3T); -LD32_LABEL(r1, L3B); -LB0 = r1; -LC0 = p1; - R5 = [ P2 ++ ]; -NOP; -NOP; -NOP; -LT0 = r0; -L3T:R2 += 3; - R5 += 6; - R6 += 7; - R3 += 4; - R4 += 5; -L3B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L4T); -LD32_LABEL(r1, L4B); -LB0 = r1; -LC0 = p1; - R5 = [ P2 ++ ]; -NOP; -NOP; -NOP; -NOP; -LT0 = r0; -L4T:R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; - R4 += 5; -L4B:R7 += 8; - - // Loop 0 -LD32_LABEL(r0, L5T); -LD32_LABEL(r1, L5B); - [ -- SP ] = R0; -SSYNC; -LB0 = r1; -LC0 = p0; - R5 = [ P2 ++ ]; -LT0 = [sp++]; -L5T:R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; - R4 += 5; -L5B:R7 += 8; - - - // Loop 1 -LD32_LABEL(r0, M0T); -LD32_LABEL(r1, M0B); -LB1 = r1; -LC1 = p1; - R5 = [ P2 ++ ]; -LT1 = r0; -M0T:R3 += 4; - R2 += 3; - R4 += 5; - R5 += 6; - R6 += 7; -M0B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M1T); -LD32_LABEL(r1, M1B); -LB1 = r1; -LC1 = p1; - R5 = [ P2 ++ ]; -NOP; -LT1 = r0; -M1T:R4 += 5; - R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; -M1B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M2T); -LD32_LABEL(r1, M2B); -LB1 = r1; -LC1 = p1; - R5 = [ P2 ++ ]; -NOP; -NOP; -LT1 = r0; -M2T:R5 += 6; - R2 += 3; - R3 += 4; - R4 += 5; - R6 += 7; -M2B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M3T); -LD32_LABEL(r1, M3B); -LB1 = r1; -LC1 = p1; - R5 = [ P2 ++ ]; -NOP; -NOP; -NOP; -LT1 = r0; -M3T:R2 += 3; - R5 += 6; - R6 += 7; - R3 += 4; - R4 += 5; -M3B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M4T); -LD32_LABEL(r1, M4B); -LB1 = r1; -LC1 = p1; - R5 = [ P2 ++ ]; -NOP; -NOP; -NOP; -NOP; -LT1 = r0; -M4T:R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; - R4 += 5; -M4B:R7 += 8; - - // Loop 1 -LD32_LABEL(r0, M5T); -LD32_LABEL(r1, M5B); - [ -- SP ] = R0; -SSYNC; -LB1 = r1; -LC1 = p0; - R5 = [ P2 ++ ]; -LT1 = [sp++]; -M5T:R2 += 3; - R3 += 4; - R5 += 6; - R6 += 7; - R4 += 5; -M5B:R7 += 8; - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_0x00F00100,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; -.dd 0x05050505; -.dd 0x06060606; -.dd 0x07070707; -.dd 0x08080808; -.dd 0x09090909; -.dd 0x0a0a0a0a; -.dd 0x0b0b0b0b; -.dd 0x0c0c0c0c; -.dd 0x0d0d0d0d; -.dd 0x0e0e0e0e; -.dd 0x0f0f0f0f; - -// Define Kernal Stack -.section MEM_0x00F00210,"aw" - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_nest_ppm.S b/sim/testsuite/sim/bfin/se_loop_nest_ppm.S deleted file mode 100644 index 81613db..0000000 --- a/sim/testsuite/sim/bfin/se_loop_nest_ppm.S +++ /dev/null @@ -1,442 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm/se_loop_nest_ppm.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - P1 = 0x4 (Z); - -LSETUP ( l0s , l0s ) LC0 = P0; -LSETUP ( l0s , l0s ) LC1 = P1; -l0s:[ -- SP ] = ( R7:5 ); - -LSETUP ( l1s , l1e ) LC0 = P0; -LSETUP ( l1e , l1e ) LC1 = P1; -l1s:R5 += 1; -l1e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l2s , l2e ) LC0 = P0; -LSETUP ( l2e , l2e ) LC1 = P1; -l2s:R5 += 1; - R6 += 2; -l2e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l3s , l3e ) LC0 = P0; -LSETUP ( l3e , l3e ) LC1 = P1; -l3s:R5 += 1; - R6 += 2; - R7 += 3; -l3e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l4s , l4e ) LC0 = P0; -LSETUP ( l4e , l4e ) LC1 = P1; -l4s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; -l4e:[ -- SP ] = ( R7:4 ); - -LSETUP ( l5s , l5e ) LC0 = P0; -LSETUP ( l5e , l5e ) LC1 = P1; -l5s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; -l5e:[ -- SP ] = ( R7:4 ); - -LSETUP ( l6s , l6e ) LC0 = P0; -LSETUP ( l6e , l6e ) LC1 = P1; -l6s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; - R7 += 5; -l6e:[ -- SP ] = ( R7:4 ); - -NOP; -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_nest_ppm_1.S b/sim/testsuite/sim/bfin/se_loop_nest_ppm_1.S deleted file mode 100644 index 6eab92f..0000000 --- a/sim/testsuite/sim/bfin/se_loop_nest_ppm_1.S +++ /dev/null @@ -1,442 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_1/se_loop_nest_ppm_1.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - P1 = 0x4 (Z); - -LSETUP ( l0s , l0s ) LC0 = P0; -LSETUP ( l0s , l0s ) LC1 = P1; -l0s:[ -- SP ] = ( R7:5 ); - -LSETUP ( l1s , l1e ) LC0 = P0; -LSETUP ( l1s , l1e ) LC1 = P1; -l1s:R5 += 1; -l1e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l2s , l2e ) LC0 = P0; -LSETUP ( l2s , l2e ) LC1 = P1; -l2s:R5 += 1; - R6 += 2; -l2e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l3s , l3e ) LC0 = P0; -LSETUP ( l3s , l3e ) LC1 = P1; -l3s:R5 += 1; - R6 += 2; - R7 += 3; -l3e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l4s , l4e ) LC0 = P0; -LSETUP ( l4s , l4e ) LC1 = P1; -l4s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; -l4e:[ -- SP ] = ( R7:4 ); - -LSETUP ( l5s , l5e ) LC0 = P0; -LSETUP ( l5s , l5e ) LC1 = P1; -l5s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; -l5e:[ -- SP ] = ( R7:4 ); - -LSETUP ( l6s , l6e ) LC1 = P0; -LSETUP ( l6s , l6e ) LC1 = P1; -l6s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; - R7 += 5; -l6e:[ -- SP ] = ( R7:4 ); - -NOP; -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_nest_ppm_2.S b/sim/testsuite/sim/bfin/se_loop_nest_ppm_2.S deleted file mode 100644 index bf842ed..0000000 --- a/sim/testsuite/sim/bfin/se_loop_nest_ppm_2.S +++ /dev/null @@ -1,491 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_2/se_loop_nest_ppm_2.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - P1 = 0x3 (Z); - -// lsetup (l0s, l0s) lc0 = p0; -LSETUP ( l0s , l0s ) LC0 = P1; -l0s:[ -- SP ] = ( R7:5 ); - -LSETUP ( l1s , l1e ) LC0 = P0; -LSETUP ( l1e , l1e ) LC0 = P1; -l1s:R5 += 1; -l1e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l2s , l2e ) LC0 = P0; -LSETUP ( l2e , l2e ) LC0 = P1; -l2s:R5 += 1; - R6 += 2; -l2e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l3s , l3e ) LC0 = P0; -LSETUP ( l3e , l3e ) LC0 = P1; -l3s:R5 += 1; - R6 += 2; - R7 += 3; -l3e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l4s , l4e ) LC0 = P0; -LSETUP ( l4e , l4e ) LC0 = P1; -l4s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; -l4e:[ -- SP ] = ( R7:4 ); - -LSETUP ( l5s , l5e ) LC0 = P0; -LSETUP ( l5e , l5e ) LC0 = P1; -l5s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; -l5e:[ -- SP ] = ( R7:4 ); - -LSETUP ( l6s , l6e ) LC0 = P0; -LSETUP ( l6e , l6e ) LC0 = P1; -l6s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; - R7 += 5; -l6e:[ -- SP ] = ( R7:4 ); - -NOP; - -LSETUP ( m0s , m0s ) LC1 = P0; -LSETUP ( m0s , m0s ) LC1 = P1; -m0s:[ -- SP ] = ( R7:5 ); - -LSETUP ( m1s , m1e ) LC1 = P0; -LSETUP ( m1e , m1e ) LC1 = P1; -m1s:R5 += 1; -m1e:[ -- SP ] = ( R7:5 ); - -LSETUP ( m2s , m2e ) LC1 = P0; -LSETUP ( m2e , m2e ) LC1 = P1; -m2s:R5 += 1; - R6 += 2; -m2e:[ -- SP ] = ( R7:5 ); - -LSETUP ( m3s , m3e ) LC1 = P0; -LSETUP ( m3e , m3e ) LC1 = P1; -m3s:R5 += 1; - R6 += 2; - R7 += 3; -m3e:[ -- SP ] = ( R7:5 ); - -LSETUP ( m4s , m4e ) LC1 = P0; -LSETUP ( m4e , m4e ) LC1 = P1; -m4s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; -m4e:[ -- SP ] = ( R7:4 ); - -LSETUP ( m5s , m5e ) LC1 = P0; -LSETUP ( m5e , m5e ) LC1 = P1; -m5s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; -m5e:[ -- SP ] = ( R7:4 ); - -LSETUP ( m6s , m6e ) LC1 = P0; -LSETUP ( m6e , m6e ) LC1 = P1; -m6s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; - R7 += 5; -m6e:[ -- SP ] = ( R7:4 ); -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_ppm.S b/sim/testsuite/sim/bfin/se_loop_ppm.S deleted file mode 100644 index b551baf..0000000 --- a/sim/testsuite/sim/bfin/se_loop_ppm.S +++ /dev/null @@ -1,477 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_ppm/se_loop_ppm.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - -LSETUP ( l0s , l0s ) LC0 = P0; -l0s:[ -- SP ] = ( R7:5 ); - -LSETUP ( l1s , l1e ) LC0 = P0; -l1s:R5 += 1; -l1e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l2s , l2e ) LC0 = P0; -l2s:R5 += 1; - R6 += 2; -l2e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l3s , l3e ) LC0 = P0; -l3s:R5 += 1; - R6 += 2; - R7 += 3; -l3e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l4s , l4e ) LC0 = P0; -l4s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; -l4e:[ -- SP ] = ( R7:4 ); - -LSETUP ( l5s , l5e ) LC0 = P0; -l5s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; -l5e:[ -- SP ] = ( R7:4 ); - -LSETUP ( l6s , l6e ) LC1 = P0; -l6s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; - R7 += 5; -l6e:[ -- SP ] = ( R7:4 ); - -NOP; - -LSETUP ( m0s , m0s ) LC1 = P0; -m0s:[ -- SP ] = ( R7:5 ); - -LSETUP ( m1s , m1e ) LC1 = P0; -m1s:R5 += 1; -m1e:[ -- SP ] = ( R7:5 ); - -LSETUP ( m2s , m2e ) LC1 = P0; -m2s:R5 += 1; - R6 += 2; -m2e:[ -- SP ] = ( R7:5 ); - -LSETUP ( m3s , m3e ) LC1 = P0; -m3s:R5 += 1; - R6 += 2; - R7 += 3; -m3e:[ -- SP ] = ( R7:5 ); - -LSETUP ( m4s , m4e ) LC1 = P0; -m4s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; -m4e:[ -- SP ] = ( R7:4 ); - -LSETUP ( m5s , m5e ) LC1 = P0; -m5s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; -m5e:[ -- SP ] = ( R7:4 ); - -LSETUP ( m6s , m6e ) LC1 = P0; -m6s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; - R7 += 5; -m6e:[ -- SP ] = ( R7:4 ); - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_ppm_1.S b/sim/testsuite/sim/bfin/se_loop_ppm_1.S deleted file mode 100644 index db8e2ca..0000000 --- a/sim/testsuite/sim/bfin/se_loop_ppm_1.S +++ /dev/null @@ -1,519 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_ppm_1/se_loop_ppm_1.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - -LSETUP ( l0s , l0s ) LC0 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -l0s:[ -- SP ] = ( R7:5 ); - -LSETUP ( l1s , l1e ) LC0 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -l1s:R5 += 1; -l1e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l2s , l2e ) LC0 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -l2s:R5 += 1; - R6 += 2; -l2e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l3s , l3e ) LC0 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -l3s:R5 += 1; - R6 += 2; - R7 += 3; -l3e:[ -- SP ] = ( R7:5 ); - -LSETUP ( l4s , l4e ) LC0 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -l4s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; -l4e:[ -- SP ] = ( R7:4 ); - -LSETUP ( l5s , l5e ) LC0 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -l5s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; -l5e:[ -- SP ] = ( R7:4 ); - -LSETUP ( l6s , l6e ) LC1 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -l6s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; - R7 += 5; -l6e:[ -- SP ] = ( R7:4 ); - -NOP; - -LSETUP ( m0s , m0s ) LC1 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -m0s:[ -- SP ] = ( R7:5 ); - -LSETUP ( m1s , m1e ) LC1 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -m1s:R5 += 1; -m1e:[ -- SP ] = ( R7:5 ); - -LSETUP ( m2s , m2e ) LC1 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -m2s:R5 += 1; - R6 += 2; -m2e:[ -- SP ] = ( R7:5 ); - -LSETUP ( m3s , m3e ) LC1 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -m3s:R5 += 1; - R6 += 2; - R7 += 3; -m3e:[ -- SP ] = ( R7:5 ); - -LSETUP ( m4s , m4e ) LC1 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -m4s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; -m4e:[ -- SP ] = ( R7:4 ); - -LSETUP ( m5s , m5e ) LC1 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -m5s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; -m5e:[ -- SP ] = ( R7:4 ); - -LSETUP ( m6s , m6e ) LC1 = P0; - R0 += 1; - R4 += 3; - R5 += 5; -m6s:R5 += 1; - R6 += 2; - R7 += 3; - R4 += 4; - R5 += 3; - R7 += 5; -m6e:[ -- SP ] = ( R7:4 ); - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_ppm_int.S b/sim/testsuite/sim/bfin/se_loop_ppm_int.S deleted file mode 100644 index eed16b4..0000000 --- a/sim/testsuite/sim/bfin/se_loop_ppm_int.S +++ /dev/null @@ -1,429 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_loop_ppm_int/se_loop_ppm_int.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Sync it! -CSYNC; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; -NOP;NOP;NOP;NOP; - - P0 = 0x5 (Z); - -LSETUP ( l0s , l0s ) LC0 = P0; -CSYNC; -l0s:[ -- SP ] = ( R7:5 ); - -LSETUP ( l3s , l3e ) LC0 = P0; -l3s:[ -- SP ] = ( R7:5 ); - R6 += 2; - R7 += 3; -NOP; - -CSYNC; -NOP; -NOP; -NOP; -l3e:R5 += 1; - -NOP; - -LSETUP ( m0s , m0s ) LC1 = P0; -CSYNC; -m0s:[ -- SP ] = ( R7:5 ); - -LSETUP ( m3s , m3e ) LC1 = P0; -m3s:[ -- SP ] = ( R7:5 ); - R6 += 2; - R7 += 3; -NOP; - -CSYNC; -NOP; -NOP; -NOP; -m3e:R5 += 1; - -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_lsetup_kill.S b/sim/testsuite/sim/bfin/se_lsetup_kill.S deleted file mode 100644 index 65d3441..0000000 --- a/sim/testsuite/sim/bfin/se_lsetup_kill.S +++ /dev/null @@ -1,776 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_lsetup_kill/se_lsetup_kill.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - - P0 = 0x5 (Z); - P1 = 0xa (Z); - -NOP; -NOP; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -///////////////////////////////////////////////////////////////////////////// -// Loop 0 (Kill Lsetup in WB) -///////////////////////////////////////////////////////////////////////////// - -EXCPT 0x5; -LSETUP ( L0T , L0T ) LC0 = P0; -L0T:R0 += 5; - -EXCPT 0x5; -LSETUP ( L1T , L1B ) LC0 = P0; -L1T:R0 += 5; -L1B:R1 += 4; - -EXCPT 0x5; -LSETUP ( L2T , L2B ) LC0 = P0; -L2T:R0 += 5; - R1 += 4; -L2B:R2 += 3; - -EXCPT 0x5; -LSETUP ( L3T , L3B ) LC0 = P0; -L3T:R0 += 5; - R1 += 4; - R2 += 3; -L3B:R3 += 2; - -EXCPT 0x5; -LSETUP ( L4T , L4B ) LC0 = P0; -L4T:R0 += 5; - R1 += 4; - R2 += 3; - R3 += 2; -L4B:R4 += 1; - -///////////////////////////////////////////////////////////////////////////// -// Loop 1 (Kill Lsetup in WB) -///////////////////////////////////////////////////////////////////////////// - -EXCPT 0x5; -LSETUP ( M0T , M0T ) LC1 = P0; -M0T:R0 += 5; - -EXCPT 0x5; -LSETUP ( M1T , M1B ) LC1 = P0; -M1T:R0 += 5; -M1B:R1 += 4; - -EXCPT 0x5; -LSETUP ( M2T , M2B ) LC1 = P0; -M2T:R0 += 5; - R1 += 4; -M2B:R2 += 3; - -EXCPT 0x5; -LSETUP ( M3T , M3B ) LC1 = P0; -M3T:R0 += 5; - R1 += 4; - R2 += 3; -M3B:R3 += 2; - -EXCPT 0x5; -LSETUP ( M4T , M4B ) LC1 = P0; -M4T:R0 += 5; - R1 += 4; - R2 += 3; - R3 += 2; -M4B:R4 += 1; - -///////////////////////////////////////////////////////////////////////////// -// Loop 0 (Kill during the last iteration at each pipe stage) -///////////////////////////////////////////////////////////////////////////// - -LSETUP ( N0T , N0B ) LC0 = P1; -NOP; -N0T:R0 = LC0; -CC = R0 == 1; -IF !CC JUMP N0B (BP); - R0 += 1; - R1 += 2; -EXCPT 0x5; -N0B:R2 += 3; - -LSETUP ( N1T , N1B ) LC0 = P1; -NOP; -N1T:R0 = LC0; - R0 += 1; - R1 += 2; -CC = R0 == 1; -IF !CC JUMP N1B (BP); -EXCPT 0x5; -N1B:R2 += 3; - -LSETUP ( N2T , N2B ) LC0 = P1; -NOP; -N2T:R0 = LC0; -CC = R0 == 1; -IF !CC JUMP N2B (BP); - R0 += 1; - R1 += 2; -EXCPT 0x5; - R3 += 4; -N2B:R2 += 3; - -LSETUP ( N3T , N3B ) LC0 = P1; -NOP; -N3T:R0 = LC0; - R0 += 1; - R1 += 2; -CC = R0 == 1; -IF !CC JUMP N3B (BP); -EXCPT 0x5; - R3 += 4; -N3B:R2 += 3; - -LSETUP ( N4T , N4B ) LC0 = P1; -NOP; -N4T:R0 = LC0; -CC = R0 == 1; -IF !CC JUMP N4B (BP); - R0 += 1; - R1 += 2; -EXCPT 0x5; - R3 += 4; - R4 += 5; -N4B:R2 += 3; - -LSETUP ( N5T , N5B ) LC0 = P1; -NOP; -N5T:R0 = LC0; - R0 += 1; - R1 += 2; -CC = R0 == 1; -IF !CC JUMP N5B (BP); -EXCPT 0x5; - R3 += 4; - R4 += 5; -N5B:R2 += 3; - -LSETUP ( N6T , N6B ) LC0 = P1; -NOP; -N6T:R0 = LC0; -CC = R0 == 1; -IF !CC JUMP N6B (BP); - R0 += 1; - R1 += 2; -EXCPT 0x5; - R3 += 4; - R4 += 5; - R5 += 6; -N6B:R2 += 3; - -LSETUP ( N7T , N7B ) LC0 = P1; -NOP; -N7T:R0 = LC0; - R0 += 1; - R1 += 2; -CC = R0 == 1; -IF !CC JUMP N7B (BP); -EXCPT 0x5; - R3 += 4; - R4 += 5; - R5 += 6; -N7B:R2 += 3; - -LSETUP ( N8T , N8B ) LC0 = P1; -NOP; -N8T:R0 = LC0; -CC = R0 == 1; -IF !CC JUMP N8B (BP); - R0 += 1; - R1 += 2; -EXCPT 0x5; - R3 += 4; - R4 += 5; - R5 += 6; - R6 += 7; -N8B:R2 += 3; - -LSETUP ( N9T , N9B ) LC0 = P1; -NOP; -N9T:R0 = LC0; - R0 += 1; - R1 += 2; -CC = R0 == 1; -IF !CC JUMP N9B (BP); -EXCPT 0x5; - R3 += 4; - R4 += 5; - R5 += 6; - R6 += 7; -N9B:R2 += 3; - -LSETUP ( NAT , NAB ) LC0 = P1; -NOP; -NAT: - R0 = LC0; -CC = R0 == 1; -IF !CC JUMP NAB (BP); - R0 += 1; - R1 += 2; -EXCPT 0x5; - R3 += 4; - R4 += 5; - R5 += 6; - R6 += 7; - R7 += 8; -NAB: - R2 += 3; - -LSETUP ( NBT , NBB ) LC0 = P1; -NOP; -NBT: - R0 = LC0; - R0 += 1; - R1 += 2; -CC = R0 == 1; -IF !CC JUMP NBB (BP); -EXCPT 0x5; - R3 += 4; - R4 += 5; - R5 += 6; - R6 += 7; - R7 += 8; -NBB: - R2 += 3; - - -///////////////////////////////////////////////////////////////////////////// -// Loop 1 (Kill during the last iteration at each pipe stage) -///////////////////////////////////////////////////////////////////////////// - -LSETUP ( O0T , O0B ) LC1 = P1; -NOP; -O0T:R0 = LC1; -CC = R0 == 1; -IF !CC JUMP O0B (BP); - R0 += 1; - R1 += 2; -EXCPT 0x5; -O0B:R2 += 3; - -LSETUP ( O1T , O1B ) LC1 = P1; -NOP; -O1T:R0 = LC1; - R0 += 1; - R1 += 2; -CC = R0 == 1; -IF !CC JUMP O1B (BP); -EXCPT 0x5; -O1B:R2 += 3; - -LSETUP ( O2T , O2B ) LC1 = P1; -NOP; -O2T:R0 = LC1; -CC = R0 == 1; -IF !CC JUMP O2B (BP); - R0 += 1; - R1 += 2; -EXCPT 0x5; - R3 += 4; -O2B:R2 += 3; - -LSETUP ( O3T , O3B ) LC1 = P1; -NOP; -O3T:R0 = LC1; - R0 += 1; - R1 += 2; -CC = R0 == 1; -IF !CC JUMP O3B (BP); -EXCPT 0x5; - R3 += 4; -O3B:R2 += 3; - -LSETUP ( O4T , O4B ) LC1 = P1; -NOP; -O4T:R0 = LC1; -CC = R0 == 1; -IF !CC JUMP O4B (BP); - R0 += 1; - R1 += 2; -EXCPT 0x5; - R3 += 4; - R4 += 5; -O4B:R2 += 3; - -LSETUP ( O5T , O5B ) LC1 = P1; -NOP; -O5T:R0 = LC1; - R0 += 1; - R1 += 2; -CC = R0 == 1; -IF !CC JUMP O5B (BP); -EXCPT 0x5; - R3 += 4; - R4 += 5; -O5B:R2 += 3; - -LSETUP ( O6T , O6B ) LC1 = P1; -NOP; -O6T:R0 = LC1; -CC = R0 == 1; -IF !CC JUMP O6B (BP); - R0 += 1; - R1 += 2; -EXCPT 0x5; - R3 += 4; - R4 += 5; - R5 += 6; -O6B:R2 += 3; - -LSETUP ( O7T , O7B ) LC1 = P1; -NOP; -O7T:R0 = LC1; - R0 += 1; - R1 += 2; -CC = R0 == 1; -IF !CC JUMP O7B (BP); -EXCPT 0x5; - R3 += 4; - R4 += 5; - R5 += 6; -O7B:R2 += 3; - -LSETUP ( O8T , O8B ) LC1 = P1; -NOP; -O8T:R0 = LC1; -CC = R0 == 1; -IF !CC JUMP O8B (BP); - R0 += 1; - R1 += 2; -EXCPT 0x5; - R3 += 4; - R4 += 5; - R5 += 6; - R6 += 7; -O8B:R2 += 3; - -LSETUP ( O9T , O9B ) LC1 = P1; -NOP; -O9T:R0 = LC1; - R0 += 1; - R1 += 2; -CC = R0 == 1; -IF !CC JUMP O9B (BP); -EXCPT 0x5; - R3 += 4; - R4 += 5; - R5 += 6; - R6 += 7; -O9B:R2 += 3; - -LSETUP ( OAT , OAB ) LC1 = P1; -NOP; -OAT: - R0 = LC1; -CC = R0 == 1; -IF !CC JUMP OAB (BP); - R0 += 1; - R1 += 2; -EXCPT 0x5; - R3 += 4; - R4 += 5; - R5 += 6; - R6 += 7; - R7 += 8; -OAB: - R2 += 3; - -LSETUP ( OBT , OBB ) LC1 = P1; -NOP; -OBT: - R0 = LC1; - R0 += 1; - R1 += 2; -CC = R0 == 1; -IF !CC JUMP OBB (BP); -EXCPT 0x5; - R3 += 4; - R4 += 5; - R5 += 6; - R6 += 7; - R7 += 8; -OBB: - R2 += 3; - -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_misaligned_fetch.S b/sim/testsuite/sim/bfin/se_misaligned_fetch.S deleted file mode 100644 index 2249243..0000000 --- a/sim/testsuite/sim/bfin/se_misaligned_fetch.S +++ /dev/null @@ -1,286 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_misaligned_fetch/se_misaligned_fetch.dsp -// Description: attempt to fetch code from misaligned address -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT); // Setup Event Vectors and Handlers - -CLI R0; // hold off nonmaskables while writing EVTs - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - R0 = -1; // Change this to mask interrupts (*) - [ P0 ] = R0; // IMASK -CSYNC; // wait for MMR writes -STI R0; // reenable events - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -// JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests -// [--sp] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - -LD32_LABEL(p1, TARGET); - - P1 += 1; // cause access to be misaligned - -JUMP ( P1 ); // should cause misaligned - - R1 += 1; - R1 += 1; - R1 += 1; - R1 += 1; - R1 += 1; - R1 += 1; - R1 += 1; - R1 += 1; - -TARGET: -NOP; -NOP; -NOP; - - // PUT YOUR TEST HERE! - - -END: -CHECKREG(r5, 0xFFFFFFFF); // handler sets this if reached - -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - [ -- SP ] = ASTAT; // save what we damage - [ -- SP ] = ( R7:6 ); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x2A; // EXCAUSE 0x2A means I-Fetch Misaligned Access -CC = r7 == r6; -IF CC JUMP IFETCHMISALIGNED; // If EXCAUSE != 0x2A then leave - -dbg_pass; // if the EXCAUSE is wrong the test will infinite loop - -IFETCHMISALIGNED: - R7 = P1; // Fix up return address -BITCLR(r7, 0); // Strip off errant LSB -RETX = r7; // and put back in RETX - - R5 = -1; // set flag to indicate success - -OUT: - ( R7:6 ) = [ SP ++ ]; -ASTAT = [sp++]; -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_more_ret_haz.S b/sim/testsuite/sim/bfin/se_more_ret_haz.S deleted file mode 100644 index c25ddca..0000000 --- a/sim/testsuite/sim/bfin/se_more_ret_haz.S +++ /dev/null @@ -1,271 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_more_ret_haz/se_more_ret_haz.dsp -// Description: Return insts following pop, move. -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT15 -#define EVT15 0xFFE0203C -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -LD32_LABEL(sp, KSTACK); // setup the stack pointer -FP = SP; // and frame pointer - -CLI R1; - -LD32(p0, EVT); // Setup Event Vectors and Handlers - -LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - [ P0 ++ ] = R0; // IVT4 not used - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; -STI R1; - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start - -RAISE 15; // after we RTI, INT 15 should be taken - -NOP; // Workaround for Bug 217 -RTI; - -// -// The Main Program -// - -STARTUSER: -LD32_LABEL(sp, USTACK); // setup the stack pointer -FP = SP; // set frame pointer -JUMP BEGIN; - -//********************************************************************* - -BEGIN: -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - // PUT YOUR TEST HERE! - // Can't Raise 0, 3, or 4 - - // Raise 1 requires some intelligence so the test - // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) -RAISE 2; - R2.L = 0xBAD; -CHECKREG(r2, 0); - -AFTER_RTN: -EXCPT 5; - R2.L = 0xBAD; -CHECKREG(r2, 0); - -AFTER_RTX: -RAISE 5; - R2.L = 0xBAD; -CHECKREG(r2, 0); - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -EHANDLE: // Emulation Handler 0 -RTE; - -RHANDLE: // Reset Handler 1 -RTI; - -NHANDLE: // NMI Handler 2 - R1.L = AFTER_RTN; - R1.H = AFTER_RTN; - [ -- SP ] = R1; -RETN = [ SP ++ ]; -RTN; - -XHANDLE: // Exception Handler 3 - R1.L = AFTER_RTX; - R1.H = AFTER_RTX; - [ -- SP ] = R1; -RETX = [ SP ++ ]; -RTX; - -HWHANDLE: // HW Error Handler 5 - R1.L = END; - R1.H = END; - [ -- SP ] = R1; -RETI = [ SP ++ ]; -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - -NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_mv2lp.S b/sim/testsuite/sim/bfin/se_mv2lp.S deleted file mode 100644 index 09feafc..0000000 --- a/sim/testsuite/sim/bfin/se_mv2lp.S +++ /dev/null @@ -1,481 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_mv2lp/se_mv2lp.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_1 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - - P0 = 0x5 (Z); - P1 = 0xa (Z); - - P2 = 0x0100 (Z); - P2.H = 0x00f0; - -LD32_LABEL(r0, L0T); -LD32_LABEL(r1, L0B); -LSETUP ( L0T , L0B ) LC0 = P0; -L0T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - R0 += 2; - R1 += 2; -LT0 = R0; -LB0 = R1; -L0B:R7 += 6; - R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; - -LD32_LABEL(r0, L1T); -LD32_LABEL(r1, L1B); -LSETUP ( L1T , L1B ) LC1 = P0; -L1T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - R0 += 2; - R1 += 2; -LT1 = R0; -LB1 = R1; -L1B:R7 += 6; - R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; - -LD32_LABEL(r0, L2T); -LD32_LABEL(r1, L2B); -LSETUP ( L2T , L2B ) LC0 = P0; -L2T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - R0 += 2; - R1 += -2; -LT0 = R0; -LB0 = R1; - R7 += 6; - R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; -L2B:R6 += 5; - -LD32_LABEL(r0, L3T); -LD32_LABEL(r1, L3B); -LSETUP ( L3T , L3B ) LC1 = P0; -L3T:R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; - R6 += 5; - R7 += 6; - R0 += 2; - R1 += -2; -LT1 = R0; -LB1 = R1; - R7 += 6; - R2 += 1; - R3 += 2; - R4 += 3; - R5 += 4; -L3B:R6 += 5; - -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; -.dd 0x05050505; -.dd 0x06060606; -.dd 0x07070707; -.dd 0x08080808; -.dd 0x09090909; -.dd 0x0a0a0a0a; -.dd 0x0b0b0b0b; -.dd 0x0c0c0c0c; -.dd 0x0d0d0d0d; -.dd 0x0e0e0e0e; -.dd 0x0f0f0f0f; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_oneins_zoff.S b/sim/testsuite/sim/bfin/se_oneins_zoff.S deleted file mode 100644 index 79259fc..0000000 --- a/sim/testsuite/sim/bfin/se_oneins_zoff.S +++ /dev/null @@ -1,487 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_oneins_zoff/se_oneins_zoff.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE 0x00000500 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef IMASK -#define IMASK 0xFFE02104 -#endif -#ifndef DMEM_CONTROL -#define DMEM_CONTROL 0xFFE00004 -#endif -#ifndef DCPLB_ADDR0 -#define DCPLB_ADDR0 0xFFE00100 -#endif -#ifndef DCPLB_DATA0 -#define DCPLB_DATA0 0xFFE00200 -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Return to Supervisor Code -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - - P0 = 0x5 (Z); - P1 = 0xa (Z); - - P2 = 0x0100 (Z); - P2.H = 0x00f0; - -///////////////////////////////////////////////////////////////////////////// -// Loop 0 (One instruction Zero-offset) -///////////////////////////////////////////////////////////////////////////// - - R0 = [ P2 ++ ]; -LSETUP ( L0T , L0T ) LC0 = P0; -L0T:R0 += 5; - - R1 = [ P2 ++ ]; -NOP; -LSETUP ( L1T , L1T ) LC0 = P0; -L1T:R1 += 5; - - R2 = [ P2 ++ ]; -NOP; -NOP; -LSETUP ( L2T , L2T ) LC0 = P0; -L2T:R2 += 5; - - R3 = [ P2 ++ ]; -NOP; -NOP; -NOP; -LSETUP ( L3T , L3T ) LC0 = P0; -L3T:R3 += 5; - - R4 = [ P2 ++ ]; -NOP; -NOP; -NOP; -NOP; -LSETUP ( L4T , L4T ) LC0 = P0; -L4T:R4 += 5; - - -///////////////////////////////////////////////////////////////////////////// -// Loop 1 (One instruction Zero-offset) -///////////////////////////////////////////////////////////////////////////// - - R0 = [ P2 ++ ]; -LSETUP ( M0T , M0T ) LC1 = P0; -M0T:R0 += 5; - - R1 = [ P2 ++ ]; -NOP; -LSETUP ( M1T , M1T ) LC1 = P0; -M1T:R1 += 5; - - R2 = [ P2 ++ ]; -NOP; -NOP; -LSETUP ( M2T , M2T ) LC1 = P0; -M2T:R2 += 5; - - R3 = [ P2 ++ ]; -NOP; -NOP; -NOP; -LSETUP ( M3T , M3T ) LC1 = P0; -M3T:R3 += 5; - - R4 = [ P2 ++ ]; -NOP; -NOP; -NOP; -NOP; -LSETUP ( M4T , M4T ) LC1 = P0; -M4T:R4 += 5; - - -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_0x00F00100,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; -.dd 0x05050505; -.dd 0x06060606; -.dd 0x07070707; -.dd 0x08080808; -.dd 0x09090909; -.dd 0x0a0a0a0a; -.dd 0x0b0b0b0b; -.dd 0x0c0c0c0c; -.dd 0x0d0d0d0d; -.dd 0x0e0e0e0e; -.dd 0x0f0f0f0f; - -// Define Kernal Stack -.section MEM_0x00F00210,"aw" - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_popkill.S b/sim/testsuite/sim/bfin/se_popkill.S deleted file mode 100644 index 550db19..0000000 --- a/sim/testsuite/sim/bfin/se_popkill.S +++ /dev/null @@ -1,566 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_popkill/se_popkill.dsp -// Description: Kill pops to sysregs in WB -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_RST_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_RST_2 // -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef IMASK -#define IMASK 0xFFE02104 -#endif -#ifndef DMEM_CONTROL -#define DMEM_CONTROL 0xFFE00004 -#endif -#ifndef DCPLB_ADDR0 -#define DCPLB_ADDR0 0xFFE00100 -#endif -#ifndef DCPLB_DATA0 -#define DCPLB_DATA0 0xFFE00200 -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - -///////////////////////////////////////////////////////////////////////////// -//////////////////////// CPLB Setup ///////////////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - // Setup CPLB for Data Memory starting at 0x00F0_0000; -WR_MMR(DCPLB_DATA0, DATA_ADDR_1, p0, r0); - //WR_MMR(DCPLB_DATA0, 0x00031005, p0, r0); // Page Size = 4MB - // CPLB_L1_CHLB = 1 - // CPLB_USER_RD = 1 - // CPLB_VALID = 1 - // - - // Setup CPLB Address to point to 0x00F0_0000 -WR_MMR(DCPLB_ADDR0, DATA_ADDR_2, p0, r0); - //WR_MMR(DCPLB_ADDR0, 0x00F00000, p0, r0); - - // Enable CPLB's -WR_MMR(DMEM_CONTROL, DATA_ADDR_3, p0, r0); - //WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1 - // ENDCPLB = 1 - // DMC = 11 - // Sync it! -CSYNC; - - - // Return to Supervisor Code -RAISE 15; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - - R3 = SEQSTAT; - R4 = RETX; - R4 += 8; -RETX = R4; -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -NOP; -ASTAT = R7; -RETS = R7; -LC0 = R7; -LB0 = R7; -LT0 = R7; -LC1 = R7; -LB1 = R7; -LT1 = R7; -CYCLES = R7; -CYCLES2 = R7; -SYSCFG = R7; -RETN = R7; -RETX = R7; -RETE = R7; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -EXCPT 1; -ASTAT = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 2; -RETS = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 3; -LC0 = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 4; -LT0 = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 5; -LB0 = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 6; -LC1 = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 7; -LB1 = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 8; -LT1 = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 9; -CYCLES = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 10; -CYCLES2 = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 11; -SYSCFG = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 12; -RETI = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 13; -RETX = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 14; -RETN = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; -EXCPT 15; -RETE = [ SP ++ ]; -NOP; -NOP; -NOP; -NOP; - -NOP; -NOP; -NOP; -NOP; - - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -// Define Kernal Stack -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -.section MEM_DATA_ADDR_2 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; -.dd 0xdeadbeef; - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_regmv_usp_sysreg.S b/sim/testsuite/sim/bfin/se_regmv_usp_sysreg.S deleted file mode 100644 index 9d776ac..0000000 --- a/sim/testsuite/sim/bfin/se_regmv_usp_sysreg.S +++ /dev/null @@ -1,171 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_regmv_usp_sysreg/se_regmv_usp_sysreg.dsp -// Description: RegMV USP to SYSREG -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(selfcheck.inc) -include(std.inc) -include(symtable.inc) - -//********************************************************************* - -BEGIN: - - // KLUDGE: from perl script must place cycles 2 write before cycles - // write, and cycles 2 read AFTER cycles read - - // PUT YOUR TEST HERE! - R0 = 0; -SP = R0; -SYSCFG = R0; - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - - R0 = 0x59c4 (Z); - R0.H = 0x95a6; -USP = R0; -ASTAT = USP; - R1 = ASTAT; - - R0 = 0xd4a4 (Z); - R0.H = 0xd16c; -USP = R0; -RETS = USP; - R1 = RETS; -CHECKREG(r1, 3513570468); - - R0 = 0x2bca (Z); - R0.H = 0x6ad8; -USP = R0; -LC0 = USP; - R1 = LC0; -CHECKREG(r1, 1792551882); - - R0 = 0x6d4a (Z); - R0.H = 0xada2; -USP = R0; -LT0 = USP; - R1 = LT0; -CHECKREG(r1, 2913103178); - - R0 = 0x6b18 (Z); - R0.H = 0x931c; -USP = R0; -LB0 = USP; - R1 = LB0; -CHECKREG(r1, 2468113176); - - R0 = 0x62da (Z); - R0.H = 0x16ee; -USP = R0; -LC1 = USP; - R1 = LC1; -CHECKREG(r1, 384721626); - - R0 = 0x7c60 (Z); - R0.H = 0xf7c8; -USP = R0; -LT1 = USP; - R1 = LT1; -CHECKREG(r1, 4157111392); - - R0 = 0x182 (Z); - R0.H = 0x942; -USP = R0; -LB1 = USP; - R1 = LB1; -CHECKREG(r1, 155320706); - - R0 = 0xd5a2 (Z); - R0.H = 0x8782; -USP = R0; -CYCLES2 = USP; - // KLUDGE - moved read after that for cycles - - R0 = 0x297c (Z); - R0.H = 0x9d06; -USP = R0; -CYCLES = USP; - R1 = CYCLES; -CHECKREG(r1, 2634426748); - R1 = CYCLES2; // KLUDGE moved read after that for cycles -CHECKREG(r1, 2273498530); - - R0 = 0x8c66 (Z); - R0.H = 0x3d64; -USP = R0; -SEQSTAT = USP; - R1 = SEQSTAT; - - R0 = 0x3b8c (Z); - R0.H = 0xdcd4; -USP = R0; -SYSCFG = USP; - R1 = SYSCFG; - - R0 = 0xb1ae (Z); - R0.H = 0x6f6; -USP = R0; -RETI = USP; - R1 = RETI; -CHECKREG(r1, 116830638); - - R0 = 0x32b0 (Z); - R0.H = 0x9b7e; -USP = R0; -RETX = USP; - R1 = RETX; -CHECKREG(r1, 2608738992); - - R0 = 0xea72 (Z); - R0.H = 0x11ea; -USP = R0; -RETN = USP; - R1 = RETN; -CHECKREG(r1, 300608114); - - R0 = 0x2c58 (Z); - R0.H = 0xb13a; -USP = R0; -RETE = USP; - R1 = RETE; -CHECKREG(r1, 2973379672); - -// Sanity check -USP = R0; -USP = R1; -USP = R2; -USP = R3; -USP = R4; -USP = R5; -USP = R6; -USP = R7; -USP = P0; -USP = P1; -USP = P2; -USP = P3; -USP = P4; -USP = P5; -USP = SP; -USP = FP; -USP = A0.X; -USP = A0.W; -USP = A1.X; -USP = A1.W; -A0.X = USP; -A0.W = USP; -A1.X = USP; -A1.W = USP; - -END: -dbg_pass; // End the test - -//********************************************************************* diff --git a/sim/testsuite/sim/bfin/se_rets_hazard.s b/sim/testsuite/sim/bfin/se_rets_hazard.s deleted file mode 100644 index 7406e87..0000000 --- a/sim/testsuite/sim/bfin/se_rets_hazard.s +++ /dev/null @@ -1,55 +0,0 @@ -//Original:/testcases/seq/se_rets_hazard/se_rets_hazard.dsp -# mach: bfin - -.include "testutils.inc" - start - - -BOOT: - FP = SP; // and frame pointer - - INIT_R_REGS 0; // initialize general purpose regs - - - - - ASTAT = r0; // reset sequencer registers - -// The Main Program - - -START: - loadsym r1, SUB1; - RETS = r1; - RTS; - -MID1: - CHECKREG r6, 0; // shouldn't be BAD - R6.L = 0xBAD2; // In case we come back to MID1 - loadsym P1, MID2; - CALL ( P1 ); - RTS; - -MID2: - loadsym R1, END; - RETS = r1; - [ -- SP ] = I0; - LINK 0; - I0 = FP; - UNLINK; - RTS; - -END: - - pass // Call Endtest Macro - -// Subroutines and Functions - -SUB1: // Code goes here - CHECKREG r7, 0; // should be if sub executed - R7.L = 0xBAD; // In case we come back to SUB1 - loadsym R2, MID1; - [ -- SP ] = R2; - RETS = [sp++]; - RTS; - R6.L = 0xBAD; diff --git a/sim/testsuite/sim/bfin/se_rts_rti.S b/sim/testsuite/sim/bfin/se_rts_rti.S deleted file mode 100644 index 8767d67..0000000 --- a/sim/testsuite/sim/bfin/se_rts_rti.S +++ /dev/null @@ -1,442 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_rts_rti/se_rts_rti.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) -include(symtable.inc) -include(mmrs.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE CODE_ADDR_1 // -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE CODE_ADDR_2 // -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT0); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - - // Load RETS -LD32_LABEL(r0, USER_CODE); -RETS = R0; - - // Return to Supervisor Code -RAISE 2; -RAISE 5; -RAISE 6; -RAISE 7; -RAISE 8; -RAISE 9; -RAISE 10; -RAISE 11; -RAISE 12; -RAISE 13; -RAISE 14; -RAISE 15; -NOP; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -RTI; -NOP; -NOP; -RTS; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -EXCPT 0x5; -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" -.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -// Define Kernal Stack -.data - .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> - KSTACK : - - .space (STACKSIZE); - USTACK : - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_ssstep_dagprotviol.S b/sim/testsuite/sim/bfin/se_ssstep_dagprotviol.S deleted file mode 100644 index bd4daf3..0000000 --- a/sim/testsuite/sim/bfin/se_ssstep_dagprotviol.S +++ /dev/null @@ -1,297 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_ssstep_dagprotviol/se_ssstep_dagprotviol.dsp -// Description: prioritize DAG Protection Violation and Supervisor Single Step -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 // change for how much stack you need -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; - -LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - - P0 += 4; // EVT0 not used (Emulation) - - P0 += 4; // EVT1 not used (Reset) - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - P0 += 4; // EVT4 not used (Global Interrupt Enable) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -RETS = r0; // prevent X's breaking LINK instruction - - R0 = 1; -SYSCFG = r0; // enable ssstep - - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -// JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: - -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests -// [--sp] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - // PUT YOUR TEST HERE! - -NOP; - I0 += 2; - I1 += 2; - I2 += 2; - R7 = [ P0 ]; // cause DAG PROTECTION VIOLATION (p0 is an MMR) - I3 += 2; - - -EXCPT 2; // turn off SSSTEP - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - -CHECKREG(r5, 7); // check the flag (# SSSTEP) -CHECKREG(r4, 1); // check the flag (# illegal opcodes) - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - - [ -- SP ] = ASTAT; // save what we damage - [ -- SP ] = ( R7:6 ); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 -CC = r7 == r6; -IF CC JUMP EXCPT2; - - R6 = 0x10; // EXCAUSE 0x10 means Single Step -CC = r7 == r6; -IF CC JUMP SSSTEP (BP); - - R6 = 0x23; // EXCAUSE 0x23 means DAG Protection Violation -CC = r7 == r6; -IF CC JUMP DAGPROTVIOL (BP); - -JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop - -EXCPT2: // turn off SSSTEP - R7 = 0; -SYSCFG = r7; -JUMP.S OUT; - -SSSTEP: - R5 += 1; // increment a counter -JUMP.S OUT; - -DAGPROTVIOL: - R7 = RETX; - R7 += 2; -RETX = R7; // skip offending instruction - - R4 += 1; // increment another counter - -OUT: - ( R7:6 ) = [ SP ++ ]; -ASTAT = [sp++]; -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - // padding for the icache - -EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; - -// -// Data Segment -// - -.section MEM_DATA_ADDR_1 //.data 0xE0000000,"aw" -DATA: - .space (0x10); - -DATADUMMY: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_ssync.S b/sim/testsuite/sim/bfin/se_ssync.S deleted file mode 100644 index e59f2f5..0000000 --- a/sim/testsuite/sim/bfin/se_ssync.S +++ /dev/null @@ -1,61 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_ssync/se_ssync.dsp -// Description: Test SSYNC by writing a bunch of MMRs and verifying read -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 // change for how much stack you need -#endif - -LD32(p0, EVT5); -LD32(r0, 0x55555555); -LD32(p1, EVT6); -LD32(r1, 0xAAAAAAAA); -LD32(p2, EVT7); -LD32(r2, 0xBABEFACE); -LD32(p3, EVT8); -LD32(r3, 0xCFCFCFCF); -LD32(p4, EVT9); -LD32(r4, 0xDEADBEEF); -LD32(p5, EVT10); -LD32(r5, 0xBAD1BAD1); - - [ P0 ] = R0; // write the MMRS - [ P1 ] = R1; - [ P2 ] = R2; - [ P3 ] = R3; - [ P4 ] = R4; - [ P5 ] = R5; - -SSYNC; // wait for it - - R7 = [ P5 ]; // read back MMRs - R6 = [ P4 ]; // should be updated - R5 = [ P3 ]; - R4 = [ P2 ]; - R3 = [ P1 ]; - R2 = [ P0 ]; - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - -CHECKREG(r2, 0x55555555); -CHECKREG(r3, 0xAAAAAAAA); -CHECKREG(r4, 0xBABEFACE); -CHECKREG(r5, 0xCFCFCFCF); -CHECKREG(r6, 0xDEADBEEF); -CHECKREG(r7, 0xBAD1BAD1); - -dbg_pass; diff --git a/sim/testsuite/sim/bfin/se_stall_if2.S b/sim/testsuite/sim/bfin/se_stall_if2.S deleted file mode 100644 index a6c939f..0000000 --- a/sim/testsuite/sim/bfin/se_stall_if2.S +++ /dev/null @@ -1,458 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_stall_if2/se_stall_if2.dsp -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Include Files ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -include(std.inc) -include(selfcheck.inc) - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// Defines ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -#ifndef USER_CODE_SPACE -#define USER_CODE_SPACE 0x00000500 -#endif -#ifndef STACKSIZE -#define STACKSIZE 0x00000010 -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif -#ifndef EVT -#define EVT 0xFFE02000 -#endif -#ifndef EVT_OVERRIDE -#define EVT_OVERRIDE 0xFFE02100 -#endif -#ifndef IMASK -#define IMASK 0xFFE02104 -#endif -#ifndef DMEM_CONTROL -#define DMEM_CONTROL 0xFFE00004 -#endif -#ifndef DCPLB_ADDR0 -#define DCPLB_ADDR0 0xFFE00100 -#endif -#ifndef DCPLB_DATA0 -#define DCPLB_DATA0 0xFFE00200 -#endif - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// RESET ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - RST_ISR : - - // Initialize Dregs -INIT_R_REGS(0); - - // Initialize Pregs -INIT_P_REGS(0); - - // Initialize ILBM Registers -INIT_I_REGS(0); -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - - // Initialize the Address of the Checkreg data segment - // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** -CHECK_INIT(p5, 0x00BFFFFC); - - // Setup User Stack -LD32_LABEL(sp, USTACK); -USP = SP; - - // Setup Kernel Stack -LD32_LABEL(sp, KSTACK); - - // Setup Frame Pointer -FP = SP; - - // Setup Event Vector Table -LD32(p0, EVT); - -LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) - [ P0 ++ ] = R0; -LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) - [ P0 ++ ] = R0; -LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) - [ P0 ++ ] = R0; -LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) - [ P0 ++ ] = R0; - [ P0 ++ ] = R0; // IVT4 not used -LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) - [ P0 ++ ] = R0; -LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler - [ P0 ++ ] = R0; -LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler - [ P0 ++ ] = R0; - - // Setup the EVT_OVERRIDE MMR - R0 = 0; -LD32(p0, EVT_OVERRIDE); - [ P0 ] = R0; - - // Setup Interrupt Mask - R0 = -1; -LD32(p0, IMASK); - [ P0 ] = R0; - -///////////////////////////////////////////////////////////////////////////// -//////////////////////// CPLB Setup ///////////////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - // Setup CPLB for Data Memory starting at 0x00F0_0000; -WR_MMR(DCPLB_DATA0, 0x00031005, p0, r0); // Page Size = 4MB - // CPLB_L1_CHLB = 1 - // CPLB_USER_RD = 1 - // CPLB_VALID = 1 - // - - // Setup CPLB Address to point to 0x00F0_0000 -WR_MMR(DCPLB_ADDR0, 0x00F00000, p0, r0); - - // Enable CPLB's -WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1 - // ENDCPLB = 1 - // DMC = 11 - // Sync it! -CSYNC; - - - // Return to Supervisor Code -RAISE 15; - -LD32_LABEL(r0, USER_CODE); -RETI = R0; -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EMU ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EMU_ISR : - -RTE; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// NMI ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - NMI_ISR : - -RTN; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// EXC ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - EXC_ISR : - -RTX; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// HWE ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - HWE_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// TMR ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - TMR_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV7 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV7_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV8 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV8_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV9 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV9_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV10 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV10_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV11 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV11_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV12 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV12_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV13 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV13_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV14 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV14_ISR : - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// IGV15 ISR ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - IGV15_ISR : - -NOP; - P0 = 0x0100 (Z); - P0.H = 0x00f0; - R0 = [ P0 ++ ]; -JUMP.S lab1; // Branch in EX1 - - -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; -NOP; - -lab1: - P0 = 0x0200 (Z); - P0.H = 0x00f0; -RTI; - R1 = [ P0 ++ ]; -JUMP.S 8; // Branch in EX1 -NOP; -NOP; -NOP; - -RTI; - -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF -.dw 0xFFFF - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// USER CODE ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - - - USER_CODE : - -NOP; -NOP; -NOP; -NOP; -dbg_pass; // Call Endtest Macro - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// DATA MEMRORY ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// - -// Define Kernal Stack -.section MEM_0xE0000000,"aw" - .space (STACKSIZE); - KSTACK : - - .space (STACKSIZE); - USTACK : - -.section MEM_0x00F00100,"aw" -.dd 0xdeadbeef; -.section MEM_0x00F00200,"aw" -.dd 0x01010101; -.dd 0x02020202; -.dd 0x03030303; -.dd 0x04040404; - -///////////////////////////////////////////////////////////////////////////// -///////////////////////// END OF TEST ///////////////////////////// -///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_undefinedinstruction1.S b/sim/testsuite/sim/bfin/se_undefinedinstruction1.S deleted file mode 100644 index 5337a74..0000000 --- a/sim/testsuite/sim/bfin/se_undefinedinstruction1.S +++ /dev/null @@ -1,1102 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction1/se_undefinedinstruction1.dsp -// Description: 16 bit "holes" Undefined Instructions in Supervisor Mode -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 // change for how much stack you need -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; - -LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - - P0 += 4; // EVT0 not used (Emulation) - - P0 += 4; // EVT1 not used (Reset) - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - P0 += 4; // EVT4 not used (Global Interrupt Enable) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - A0 = 0; // reset accumulators - A1 = 0; - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: - -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - // count of UI's will be in r5, which was initialized to 0 by header - - - .dw 0x1 ; - .dw 0x2 ; - .dw 0x3 ; - .dw 0x4 ; - .dw 0x5 ; - .dw 0x6 ; - .dw 0x7 ; - .dw 0x8 ; - .dw 0x9 ; - .dw 0xA ; - .dw 0xB ; - .dw 0xC ; - .dw 0xD ; - .dw 0xE ; - .dw 0xF ; - .dw 0x15 ; - .dw 0x16 ; - .dw 0x17 ; - .dw 0x18 ; - .dw 0x19 ; - .dw 0x1A ; - .dw 0x1B ; - .dw 0x1C ; - .dw 0x1D ; - .dw 0x1E ; - .dw 0x1F ; - .dw 0x21 ; - .dw 0x22 ; - .dw 0x26 ; - .dw 0x27 ; // XXX: hardware doesnt trigger illegal exception ? - .dw 0x28 ; - .dw 0x29 ; - .dw 0x2A ; - .dw 0x2B ; - .dw 0x2C ; - .dw 0x2D ; - .dw 0x2E ; - .dw 0x2F ; - .dw 0x38 ; - .dw 0x39 ; - .dw 0x3A ; - .dw 0x3B ; - .dw 0x3C ; - .dw 0x3D ; - .dw 0x3E ; - .dw 0x3F ; - .dw 0x48 ; - .dw 0x49 ; - .dw 0x4A ; - .dw 0x4B ; - .dw 0x4C ; - .dw 0x4D ; - .dw 0x4E ; - .dw 0x4F ; - .dw 0x58 ; - .dw 0x59 ; - .dw 0x5A ; - .dw 0x5B ; - .dw 0x5C ; - .dw 0x5D ; - .dw 0x5E ; - .dw 0x5F ; - .dw 0x68 ; - .dw 0x69 ; - .dw 0x6A ; - .dw 0x6B ; - .dw 0x6C ; - .dw 0x6D ; - .dw 0x6E ; - .dw 0x6F ; - .dw 0x78 ; - .dw 0x79 ; - .dw 0x7A ; - .dw 0x7B ; - .dw 0x7C ; - .dw 0x7D ; - .dw 0x7E ; - .dw 0x7F ; - .dw 0x88 ; - .dw 0x89 ; - .dw 0x8A ; - .dw 0x8B ; - .dw 0x8C ; - .dw 0x8D ; - .dw 0x8E ; - .dw 0x8F ; - .dw 0xB8 ; - .dw 0xB9 ; - .dw 0xBA ; - .dw 0xBB ; - .dw 0xBC ; - .dw 0xBD ; - .dw 0xBE ; - .dw 0xBF ; - .dw 0xC0 ; - .dw 0xC1 ; - .dw 0xC2 ; - .dw 0xC3 ; - .dw 0xC4 ; - .dw 0xC5 ; - .dw 0xC6 ; - .dw 0xC7 ; - .dw 0xC8 ; - .dw 0xC9 ; - .dw 0xCA ; - .dw 0xCB ; - .dw 0xCC ; - .dw 0xCD ; - .dw 0xCE ; - .dw 0xCF ; - .dw 0xD0 ; - .dw 0xD1 ; - .dw 0xD2 ; - .dw 0xD3 ; - .dw 0xD4 ; - .dw 0xD5 ; - .dw 0xD6 ; - .dw 0xD7 ; - .dw 0xD8 ; - .dw 0xD9 ; - .dw 0xDA ; - .dw 0xDB ; - .dw 0xDC ; - .dw 0xDD ; - .dw 0xDE ; - .dw 0xDF ; - .dw 0xE0 ; - .dw 0xE1 ; - .dw 0xE2 ; - .dw 0xE3 ; - .dw 0xE4 ; - .dw 0xE5 ; - .dw 0xE6 ; - .dw 0xE7 ; - .dw 0xE8 ; - .dw 0xE9 ; - .dw 0xEA ; - .dw 0xEB ; - .dw 0xEC ; - .dw 0xED ; - .dw 0xEE ; - .dw 0xEF ; - .dw 0xF0 ; - .dw 0xF1 ; - .dw 0xF2 ; - .dw 0xF3 ; - .dw 0xF4 ; - .dw 0xF5 ; - .dw 0xF6 ; - .dw 0xF7 ; - .dw 0xF8 ; - .dw 0xF9 ; - .dw 0xFA ; - .dw 0xFB ; - .dw 0xFC ; - .dw 0xFD ; - .dw 0xFE ; - .dw 0xFF ; - .dw 0x220 ; - .dw 0x221 ; - .dw 0x222 ; - .dw 0x223 ; - .dw 0x224 ; - .dw 0x225 ; - .dw 0x226 ; - .dw 0x227 ; - .dw 0x228 ; - .dw 0x229 ; - .dw 0x22A ; - .dw 0x22B ; - .dw 0x22C ; - .dw 0x22D ; - .dw 0x22E ; - .dw 0x22F ; - .dw 0x230 ; - .dw 0x231 ; - .dw 0x232 ; - .dw 0x233 ; - .dw 0x234 ; - .dw 0x235 ; - .dw 0x236 ; - .dw 0x237 ; - .dw 0x238 ; - .dw 0x239 ; - .dw 0x23A ; - .dw 0x23B ; - .dw 0x23C ; - .dw 0x23D ; - .dw 0x23E ; - .dw 0x23F ; - .dw 0x280 ; - .dw 0x281 ; - .dw 0x282 ; - .dw 0x283 ; - .dw 0x284 ; - .dw 0x285 ; - .dw 0x286 ; - .dw 0x287 ; - .dw 0x288 ; - .dw 0x289 ; - .dw 0x28A ; - .dw 0x28B ; - .dw 0x28C ; - .dw 0x28D ; - .dw 0x28E ; - .dw 0x28F ; - .dw 0x290 ; - .dw 0x291 ; - .dw 0x292 ; - .dw 0x293 ; - .dw 0x294 ; - .dw 0x295 ; - .dw 0x296 ; - .dw 0x297 ; - .dw 0x298 ; - .dw 0x299 ; - .dw 0x29A ; - .dw 0x29B ; - .dw 0x29C ; - .dw 0x29D ; - .dw 0x29E ; - .dw 0x29F ; - .dw 0x2A0 ; - .dw 0x2A1 ; - .dw 0x2A2 ; - .dw 0x2A3 ; - .dw 0x2A4 ; - .dw 0x2A5 ; - .dw 0x2A6 ; - .dw 0x2A7 ; - .dw 0x2A8 ; - .dw 0x2A9 ; - .dw 0x2AA ; - .dw 0x2AB ; - .dw 0x2AC ; - .dw 0x2AD ; - .dw 0x2AE ; - .dw 0x2AF ; - .dw 0x2B0 ; - .dw 0x2B1 ; - .dw 0x2B2 ; - .dw 0x2B3 ; - .dw 0x2B4 ; - .dw 0x2B5 ; - .dw 0x2B6 ; - .dw 0x2B7 ; - .dw 0x2B8 ; - .dw 0x2B9 ; - .dw 0x2BA ; - .dw 0x2BB ; - .dw 0x2BC ; - .dw 0x2BD ; - .dw 0x2BE ; - .dw 0x2BF ; - .dw 0x2C0 ; - .dw 0x2C1 ; - .dw 0x2C2 ; - .dw 0x2C3 ; - .dw 0x2C4 ; - .dw 0x2C5 ; - .dw 0x2C6 ; - .dw 0x2C7 ; - .dw 0x2C8 ; - .dw 0x2C9 ; - .dw 0x2CA ; - .dw 0x2CB ; - .dw 0x2CC ; - .dw 0x2CD ; - .dw 0x2CE ; - .dw 0x2CF ; - .dw 0x2D0 ; - .dw 0x2D1 ; - .dw 0x2D2 ; - .dw 0x2D3 ; - .dw 0x2D4 ; - .dw 0x2D5 ; - .dw 0x2D6 ; - .dw 0x2D7 ; - .dw 0x2D8 ; - .dw 0x2D9 ; - .dw 0x2DA ; - .dw 0x2DB ; - .dw 0x2DC ; - .dw 0x2DD ; - .dw 0x2DE ; - .dw 0x2DF ; - .dw 0x2E0 ; - .dw 0x2E1 ; - .dw 0x2E2 ; - .dw 0x2E3 ; - .dw 0x2E4 ; - .dw 0x2E5 ; - .dw 0x2E6 ; - .dw 0x2E7 ; - .dw 0x2E8 ; - .dw 0x2E9 ; - .dw 0x2EA ; - .dw 0x2EB ; - .dw 0x2EC ; - .dw 0x2ED ; - .dw 0x2EE ; - .dw 0x2EF ; - .dw 0x2F0 ; - .dw 0x2F1 ; - .dw 0x2F2 ; - .dw 0x2F3 ; - .dw 0x2F4 ; - .dw 0x2F5 ; - .dw 0x2F6 ; - .dw 0x2F7 ; - .dw 0x2F8 ; - .dw 0x2F9 ; - .dw 0x2FA ; - .dw 0x2FB ; - .dw 0x2FC ; - .dw 0x2FD ; - .dw 0x2FE ; - .dw 0x2FF ; - .dw 0x4600 ; - .dw 0x4601 ; - .dw 0x4602 ; - .dw 0x4603 ; - .dw 0x4604 ; - .dw 0x4605 ; - .dw 0x4606 ; - .dw 0x4607 ; - .dw 0x4608 ; - .dw 0x4609 ; - .dw 0x460A ; - .dw 0x460B ; - .dw 0x460C ; - .dw 0x460D ; - .dw 0x460E ; - .dw 0x460F ; - .dw 0x4610 ; - .dw 0x4611 ; - .dw 0x4612 ; - .dw 0x4613 ; - .dw 0x4614 ; - .dw 0x4615 ; - .dw 0x4616 ; - .dw 0x4617 ; - .dw 0x4618 ; - .dw 0x4619 ; - .dw 0x461A ; - .dw 0x461B ; - .dw 0x461C ; - .dw 0x461D ; - .dw 0x461E ; - .dw 0x461F ; - .dw 0x4620 ; - .dw 0x4621 ; - .dw 0x4622 ; - .dw 0x4623 ; - .dw 0x4624 ; - .dw 0x4625 ; - .dw 0x4626 ; - .dw 0x4627 ; - .dw 0x4628 ; - .dw 0x4629 ; - .dw 0x462A ; - .dw 0x462B ; - .dw 0x462C ; - .dw 0x462D ; - .dw 0x462E ; - .dw 0x462F ; - .dw 0x4630 ; - .dw 0x4631 ; - .dw 0x4632 ; - .dw 0x4633 ; - .dw 0x4634 ; - .dw 0x4635 ; - .dw 0x4636 ; - .dw 0x4637 ; - .dw 0x4638 ; - .dw 0x4639 ; - .dw 0x463A ; - .dw 0x463B ; - .dw 0x463C ; - .dw 0x463D ; - .dw 0x463E ; - .dw 0x463F ; - .dw 0x4640 ; - .dw 0x4641 ; - .dw 0x4642 ; - .dw 0x4643 ; - .dw 0x4644 ; - .dw 0x4645 ; - .dw 0x4646 ; - .dw 0x4647 ; - .dw 0x4648 ; - .dw 0x4649 ; - .dw 0x464A ; - .dw 0x464B ; - .dw 0x464C ; - .dw 0x464D ; - .dw 0x464E ; - .dw 0x464F ; - .dw 0x4650 ; - .dw 0x4651 ; - .dw 0x4652 ; - .dw 0x4653 ; - .dw 0x4654 ; - .dw 0x4655 ; - .dw 0x4656 ; - .dw 0x4657 ; - .dw 0x4658 ; - .dw 0x4659 ; - .dw 0x465A ; - .dw 0x465B ; - .dw 0x465C ; - .dw 0x465D ; - .dw 0x465E ; - .dw 0x465F ; - .dw 0x4660 ; - .dw 0x4661 ; - .dw 0x4662 ; - .dw 0x4663 ; - .dw 0x4664 ; - .dw 0x4665 ; - .dw 0x4666 ; - .dw 0x4667 ; - .dw 0x4668 ; - .dw 0x4669 ; - .dw 0x466A ; - .dw 0x466B ; - .dw 0x466C ; - .dw 0x466D ; - .dw 0x466E ; - .dw 0x466F ; - .dw 0x4670 ; - .dw 0x4671 ; - .dw 0x4672 ; - .dw 0x4673 ; - .dw 0x4674 ; - .dw 0x4675 ; - .dw 0x4676 ; - .dw 0x4677 ; - .dw 0x4678 ; - .dw 0x4679 ; - .dw 0x467A ; - .dw 0x467B ; - .dw 0x467C ; - .dw 0x467D ; - .dw 0x467E ; - .dw 0x467F ; - .dw 0x4680 ; - .dw 0x4681 ; - .dw 0x4682 ; - .dw 0x4683 ; - .dw 0x4684 ; - .dw 0x4685 ; - .dw 0x4686 ; - .dw 0x4687 ; - .dw 0x4688 ; - .dw 0x4689 ; - .dw 0x468A ; - .dw 0x468B ; - .dw 0x468C ; - .dw 0x468D ; - .dw 0x468E ; - .dw 0x468F ; - .dw 0x4690 ; - .dw 0x4691 ; - .dw 0x4692 ; - .dw 0x4693 ; - .dw 0x4694 ; - .dw 0x4695 ; - .dw 0x4696 ; - .dw 0x4697 ; - .dw 0x4698 ; - .dw 0x4699 ; - .dw 0x469A ; - .dw 0x469B ; - .dw 0x469C ; - .dw 0x469D ; - .dw 0x469E ; - .dw 0x469F ; - .dw 0x46A0 ; - .dw 0x46A1 ; - .dw 0x46A2 ; - .dw 0x46A3 ; - .dw 0x46A4 ; - .dw 0x46A5 ; - .dw 0x46A6 ; - .dw 0x46A7 ; - .dw 0x46A8 ; - .dw 0x46A9 ; - .dw 0x46AA ; - .dw 0x46AB ; - .dw 0x46AC ; - .dw 0x46AD ; - .dw 0x46AE ; - .dw 0x46AF ; - .dw 0x46B0 ; - .dw 0x46B1 ; - .dw 0x46B2 ; - .dw 0x46B3 ; - .dw 0x46B4 ; - .dw 0x46B5 ; - .dw 0x46B6 ; - .dw 0x46B7 ; - .dw 0x46B8 ; - .dw 0x46B9 ; - .dw 0x46BA ; - .dw 0x46BB ; - .dw 0x46BC ; - .dw 0x46BD ; - .dw 0x46BE ; - .dw 0x46BF ; - .dw 0x46C0 ; - .dw 0x46C1 ; - .dw 0x46C2 ; - .dw 0x46C3 ; - .dw 0x46C4 ; - .dw 0x46C5 ; - .dw 0x46C6 ; - .dw 0x46C7 ; - .dw 0x46C8 ; - .dw 0x46C9 ; - .dw 0x46CA ; - .dw 0x46CB ; - .dw 0x46CC ; - .dw 0x46CD ; - .dw 0x46CE ; - .dw 0x46CF ; - .dw 0x46D0 ; - .dw 0x46D1 ; - .dw 0x46D2 ; - .dw 0x46D3 ; - .dw 0x46D4 ; - .dw 0x46D5 ; - .dw 0x46D6 ; - .dw 0x46D7 ; - .dw 0x46D8 ; - .dw 0x46D9 ; - .dw 0x46DA ; - .dw 0x46DB ; - .dw 0x46DC ; - .dw 0x46DD ; - .dw 0x46DE ; - .dw 0x46DF ; - .dw 0x46E0 ; - .dw 0x46E1 ; - .dw 0x46E2 ; - .dw 0x46E3 ; - .dw 0x46E4 ; - .dw 0x46E5 ; - .dw 0x46E6 ; - .dw 0x46E7 ; - .dw 0x46E8 ; - .dw 0x46E9 ; - .dw 0x46EA ; - .dw 0x46EB ; - .dw 0x46EC ; - .dw 0x46ED ; - .dw 0x46EE ; - .dw 0x46EF ; - .dw 0x46F0 ; - .dw 0x46F1 ; - .dw 0x46F2 ; - .dw 0x46F3 ; - .dw 0x46F4 ; - .dw 0x46F5 ; - .dw 0x46F6 ; - .dw 0x46F7 ; - .dw 0x46F8 ; - .dw 0x46F9 ; - .dw 0x46FA ; - .dw 0x46FB ; - .dw 0x46FC ; - .dw 0x46FD ; - .dw 0x46FE ; - .dw 0x46FF ; - .dw 0x4700 ; - .dw 0x4701 ; - .dw 0x4702 ; - .dw 0x4703 ; - .dw 0x4704 ; - .dw 0x4705 ; - .dw 0x4706 ; - .dw 0x4707 ; - .dw 0x4708 ; - .dw 0x4709 ; - .dw 0x470A ; - .dw 0x470B ; - .dw 0x470C ; - .dw 0x470D ; - .dw 0x470E ; - .dw 0x470F ; - .dw 0x4710 ; - .dw 0x4711 ; - .dw 0x4712 ; - .dw 0x4713 ; - .dw 0x4714 ; - .dw 0x4715 ; - .dw 0x4716 ; - .dw 0x4717 ; - .dw 0x4718 ; - .dw 0x4719 ; - .dw 0x471A ; - .dw 0x471B ; - .dw 0x471C ; - .dw 0x471D ; - .dw 0x471E ; - .dw 0x471F ; - .dw 0x4720 ; - .dw 0x4721 ; - .dw 0x4722 ; - .dw 0x4723 ; - .dw 0x4724 ; - .dw 0x4725 ; - .dw 0x4726 ; - .dw 0x4727 ; - .dw 0x4728 ; - .dw 0x4729 ; - .dw 0x472A ; - .dw 0x472B ; - .dw 0x472C ; - .dw 0x472D ; - .dw 0x472E ; - .dw 0x472F ; - .dw 0x4730 ; - .dw 0x4731 ; - .dw 0x4732 ; - .dw 0x4733 ; - .dw 0x4734 ; - .dw 0x4735 ; - .dw 0x4736 ; - .dw 0x4737 ; - .dw 0x4738 ; - .dw 0x4739 ; - .dw 0x473A ; - .dw 0x473B ; - .dw 0x473C ; - .dw 0x473D ; - .dw 0x473E ; - .dw 0x473F ; - .dw 0x4740 ; - .dw 0x4741 ; - .dw 0x4742 ; - .dw 0x4743 ; - .dw 0x4744 ; - .dw 0x4745 ; - .dw 0x4746 ; - .dw 0x4747 ; - .dw 0x4748 ; - .dw 0x4749 ; - .dw 0x474A ; - .dw 0x474B ; - .dw 0x474C ; - .dw 0x474D ; - .dw 0x474E ; - .dw 0x474F ; - .dw 0x4750 ; - .dw 0x4751 ; - .dw 0x4752 ; - .dw 0x4753 ; - .dw 0x4754 ; - .dw 0x4755 ; - .dw 0x4756 ; - .dw 0x4757 ; - .dw 0x4758 ; - .dw 0x4759 ; - .dw 0x475A ; - .dw 0x475B ; - .dw 0x475C ; - .dw 0x475D ; - .dw 0x475E ; - .dw 0x475F ; - .dw 0x4760 ; - .dw 0x4761 ; - .dw 0x4762 ; - .dw 0x4763 ; - .dw 0x4764 ; - .dw 0x4765 ; - .dw 0x4766 ; - .dw 0x4767 ; - .dw 0x4768 ; - .dw 0x4769 ; - .dw 0x476A ; - .dw 0x476B ; - .dw 0x476C ; - .dw 0x476D ; - .dw 0x476E ; - .dw 0x476F ; - .dw 0x4770 ; - .dw 0x4771 ; - .dw 0x4772 ; - .dw 0x4773 ; - .dw 0x4774 ; - .dw 0x4775 ; - .dw 0x4776 ; - .dw 0x4777 ; - .dw 0x4778 ; - .dw 0x4779 ; - .dw 0x477A ; - .dw 0x477B ; - .dw 0x477C ; - .dw 0x477D ; - .dw 0x477E ; - .dw 0x477F ; - .dw 0x4780 ; - .dw 0x4781 ; - .dw 0x4782 ; - .dw 0x4783 ; - .dw 0x4784 ; - .dw 0x4785 ; - .dw 0x4786 ; - .dw 0x4787 ; - .dw 0x4788 ; - .dw 0x4789 ; - .dw 0x478A ; - .dw 0x478B ; - .dw 0x478C ; - .dw 0x478D ; - .dw 0x478E ; - .dw 0x478F ; - .dw 0x4790 ; - .dw 0x4791 ; - .dw 0x4792 ; - .dw 0x4793 ; - .dw 0x4794 ; - .dw 0x4795 ; - .dw 0x4796 ; - .dw 0x4797 ; - .dw 0x4798 ; - .dw 0x4799 ; - .dw 0x479A ; - .dw 0x479B ; - .dw 0x479C ; - .dw 0x479D ; - .dw 0x479E ; - .dw 0x479F ; - .dw 0x47A0 ; - .dw 0x47A1 ; - .dw 0x47A2 ; - .dw 0x47A3 ; - .dw 0x47A4 ; - .dw 0x47A5 ; - .dw 0x47A6 ; - .dw 0x47A7 ; - .dw 0x47A8 ; - .dw 0x47A9 ; - .dw 0x47AA ; - .dw 0x47AB ; - .dw 0x47AC ; - .dw 0x47AD ; - .dw 0x47AE ; - .dw 0x47AF ; - .dw 0x47B0 ; - .dw 0x47B1 ; - .dw 0x47B2 ; - .dw 0x47B3 ; - .dw 0x47B4 ; - .dw 0x47B5 ; - .dw 0x47B6 ; - .dw 0x47B7 ; - .dw 0x47B8 ; - .dw 0x47B9 ; - .dw 0x47BA ; - .dw 0x47BB ; - .dw 0x47BC ; - .dw 0x47BD ; - .dw 0x47BE ; - .dw 0x47BF ; - .dw 0x47C0 ; - .dw 0x47C1 ; - .dw 0x47C2 ; - .dw 0x47C3 ; - .dw 0x47C4 ; - .dw 0x47C5 ; - .dw 0x47C6 ; - .dw 0x47C7 ; - .dw 0x47C8 ; - .dw 0x47C9 ; - .dw 0x47CA ; - .dw 0x47CB ; - .dw 0x47CC ; - .dw 0x47CD ; - .dw 0x47CE ; - .dw 0x47CF ; - .dw 0x47D0 ; - .dw 0x47D1 ; - .dw 0x47D2 ; - .dw 0x47D3 ; - .dw 0x47D4 ; - .dw 0x47D5 ; - .dw 0x47D6 ; - .dw 0x47D7 ; - .dw 0x47D8 ; - .dw 0x47D9 ; - .dw 0x47DA ; - .dw 0x47DB ; - .dw 0x47DC ; - .dw 0x47DD ; - .dw 0x47DE ; - .dw 0x47DF ; - .dw 0x47E0 ; - .dw 0x47E1 ; - .dw 0x47E2 ; - .dw 0x47E3 ; - .dw 0x47E4 ; - .dw 0x47E5 ; - .dw 0x47E6 ; - .dw 0x47E7 ; - .dw 0x47E8 ; - .dw 0x47E9 ; - .dw 0x47EA ; - .dw 0x47EB ; - .dw 0x47EC ; - .dw 0x47ED ; - .dw 0x47EE ; - .dw 0x47EF ; - .dw 0x47F0 ; - .dw 0x47F1 ; - .dw 0x47F2 ; - .dw 0x47F3 ; - .dw 0x47F4 ; - .dw 0x47F5 ; - .dw 0x47F6 ; - .dw 0x47F7 ; - .dw 0x47F8 ; - .dw 0x47F9 ; - .dw 0x47FA ; - .dw 0x47FB ; - .dw 0x47FC ; - .dw 0x47FD ; - .dw 0x47FE ; - .dw 0x47FF ; - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - // Xhandler counts all EXCAUSE = 0x21; -CHECKREG(r5, 830); // count of all 16 bit UI's. - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - // 16 bit illegal opcode handler - skips bad instruction - - [ -- SP ] = ASTAT; // save what we damage - [ -- SP ] = ( R7:6 ); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction -CC = r7 == r6; -IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave - -JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop - -UNDEFINEDINSTRUCTION: - R7 = RETX; // Fix up return address - - R7 += 2; // skip offending 16 bit instruction - -RETX = r7; // and put back in RETX - - R5 += 1; // Increment global counter - -OUT: - ( R7:6 ) = [ SP ++ ]; -ASTAT = [sp++]; - -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - // padding for the icache - -EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_undefinedinstruction2.S b/sim/testsuite/sim/bfin/se_undefinedinstruction2.S deleted file mode 100644 index d21e375..0000000 --- a/sim/testsuite/sim/bfin/se_undefinedinstruction2.S +++ /dev/null @@ -1,3147 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction2/se_undefinedinstruction2.dsp -// Description: 16 bit special cases Undefined Instructions in Supervisor Mode -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 // change for how much stack you need -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; - -LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - - P0 += 4; // EVT0 not used (Emulation) - - P0 += 4; // EVT1 not used (Reset) - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - P0 += 4; // EVT4 not used (Global Interrupt Enable) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - A0 = 0; // reset accumulators - A1 = 0; - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); -r4 = p1; - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: - -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - // count of UI's will be in r5, which was initialized to 0 by header - -// 16 bit special cases COUNT = 830 - .dw 0x10E ; - .dw 0x124 ; -.ifndef BFIN_HW - // XXX: hardware doesnt trigger illegal exception ? - .dw 0x125 ; -.endif - .dw 0x164 ; -.ifndef BFIN_HW - // XXX: hardware doesnt trigger illegal exception ? - .dw 0x165 ; -.endif - .dw 0x128 ; - .dw 0x129 ; - .dw 0x12A ; - .dw 0x12B ; - .dw 0x12C ; - .dw 0x12D ; - .dw 0x12E ; - .dw 0x12F ; - .dw 0x168 ; - .dw 0x169 ; - .dw 0x16A ; - .dw 0x16B ; - .dw 0x16C ; - .dw 0x16D ; - .dw 0x16E ; - .dw 0x16F ; -#if 0 - // EMUDAT = [SP++]; is valid - .dw 0x13F ; - // [SP++] = EMUDAT; is valid - .dw 0x17F ; -#endif - .dw 0x486 ; - .dw 0x487 ; - .dw 0x210 ; - .dw 0x211 ; - .dw 0x212 ; - .dw 0x213 ; - .dw 0x214 ; - .dw 0x215 ; - .dw 0x216 ; - .dw 0x217 ; - .dw 0x305 ; -#if 0 - // Not documented, but hardware takes them - // CC = - .dw 0x307 ; - .dw 0x308 ; - .dw 0x309 ; - .dw 0x30A ; - .dw 0x30B ; - .dw 0x30C ; - .dw 0x30D ; - .dw 0x30E ; - .dw 0x30F ; - .dw 0x310 ; - .dw 0x311 ; - .dw 0x312 ; - .dw 0x313 ; - .dw 0x314 ; - .dw 0x315 ; - .dw 0x316 ; - .dw 0x317 ; - .dw 0x318 ; - .dw 0x319 ; - .dw 0x31A ; - .dw 0x31B ; - .dw 0x31C ; - .dw 0x31D ; - .dw 0x31E ; - .dw 0x31F ; -#endif - .dw 0x325 ; -#if 0 - // Not documented, but hardware takes them - // CC |= - .dw 0x327 ; - .dw 0x328 ; - .dw 0x329 ; - .dw 0x32A ; - .dw 0x32B ; - .dw 0x32C ; - .dw 0x32D ; - .dw 0x32E ; - .dw 0x32F ; - .dw 0x330 ; - .dw 0x331 ; - .dw 0x332 ; - .dw 0x333 ; - .dw 0x334 ; - .dw 0x335 ; - .dw 0x336 ; - .dw 0x337 ; - .dw 0x338 ; - .dw 0x339 ; - .dw 0x33A ; - .dw 0x33B ; - .dw 0x33C ; - .dw 0x33D ; - .dw 0x33E ; - .dw 0x33F ; -#endif - .dw 0x345 ; -#if 0 - // Not documented, but hardware takes them - // CC &= - .dw 0x347 ; - .dw 0x348 ; - .dw 0x349 ; - .dw 0x34A ; - .dw 0x34B ; - .dw 0x34C ; - .dw 0x34D ; - .dw 0x34E ; - .dw 0x34F ; - .dw 0x350 ; - .dw 0x351 ; - .dw 0x352 ; - .dw 0x353 ; - .dw 0x354 ; - .dw 0x355 ; - .dw 0x356 ; - .dw 0x357 ; - .dw 0x358 ; - .dw 0x359 ; - .dw 0x35A ; - .dw 0x35B ; - .dw 0x35C ; - .dw 0x35D ; - .dw 0x35E ; - .dw 0x35F ; -#endif - .dw 0x365 ; -#if 0 - // Not documented, but hardware takes them - // CC ^= - .dw 0x367 ; - .dw 0x368 ; - .dw 0x369 ; - .dw 0x36A ; - .dw 0x36B ; - .dw 0x36C ; - .dw 0x36D ; - .dw 0x36E ; - .dw 0x36F ; - .dw 0x370 ; - .dw 0x371 ; - .dw 0x372 ; - .dw 0x373 ; - .dw 0x374 ; - .dw 0x375 ; - .dw 0x376 ; - .dw 0x377 ; - .dw 0x378 ; - .dw 0x379 ; - .dw 0x37A ; - .dw 0x37B ; - .dw 0x37C ; - .dw 0x37D ; - .dw 0x37E ; - .dw 0x37F ; -#endif - .dw 0x385 ; -#if 0 - // Not documented, but hardware takes them - // = CC - .dw 0x387 ; - .dw 0x388 ; - .dw 0x389 ; - .dw 0x38A ; - .dw 0x38B ; - .dw 0x38C ; - .dw 0x38D ; - .dw 0x38E ; - .dw 0x38F ; - .dw 0x390 ; - .dw 0x391 ; - .dw 0x392 ; - .dw 0x393 ; - .dw 0x394 ; - .dw 0x395 ; - .dw 0x396 ; - .dw 0x397 ; - .dw 0x398 ; - .dw 0x399 ; - .dw 0x39A ; - .dw 0x39B ; - .dw 0x39C ; - .dw 0x39D ; - .dw 0x39E ; - .dw 0x39F ; -#endif - .dw 0x3A5 ; -#if 0 - // Not documented, but hardware takes them - // |= CC - .dw 0x3A7 ; - .dw 0x3A8 ; - .dw 0x3A9 ; - .dw 0x3AA ; - .dw 0x3AB ; - .dw 0x3AC ; - .dw 0x3AD ; - .dw 0x3AE ; - .dw 0x3AF ; - .dw 0x3B0 ; - .dw 0x3B1 ; - .dw 0x3B2 ; - .dw 0x3B3 ; - .dw 0x3B4 ; - .dw 0x3B5 ; - .dw 0x3B6 ; - .dw 0x3B7 ; - .dw 0x3B8 ; - .dw 0x3B9 ; - .dw 0x3BA ; - .dw 0x3BB ; - .dw 0x3BC ; - .dw 0x3BD ; - .dw 0x3BE ; - .dw 0x3BF ; -#endif - .dw 0x3C5 ; -#if 0 - // Not documented, but hardware takes them - // &= CC - .dw 0x3C7 ; - .dw 0x3C8 ; - .dw 0x3C9 ; - .dw 0x3CA ; - .dw 0x3CB ; - .dw 0x3CC ; - .dw 0x3CD ; - .dw 0x3CE ; - .dw 0x3CF ; - .dw 0x3D0 ; - .dw 0x3D1 ; - .dw 0x3D2 ; - .dw 0x3D3 ; - .dw 0x3D4 ; - .dw 0x3D5 ; - .dw 0x3D6 ; - .dw 0x3D7 ; - .dw 0x3D8 ; - .dw 0x3D9 ; - .dw 0x3DA ; - .dw 0x3DB ; - .dw 0x3DC ; - .dw 0x3DD ; - .dw 0x3DE ; - .dw 0x3DF ; -#endif - .dw 0x3E5 ; -#if 0 - // Not documented, but hardware takes them - // ^= CC - .dw 0x3E7 ; - .dw 0x3E8 ; - .dw 0x3E9 ; - .dw 0x3EA ; - .dw 0x3EB ; - .dw 0x3EC ; - .dw 0x3ED ; - .dw 0x3EE ; - .dw 0x3EF ; - .dw 0x3F0 ; - .dw 0x3F1 ; - .dw 0x3F2 ; - .dw 0x3F3 ; - .dw 0x3F4 ; - .dw 0x3F5 ; - .dw 0x3F6 ; - .dw 0x3F7 ; - .dw 0x3F8 ; - .dw 0x3F9 ; - .dw 0x3FA ; - .dw 0x3FB ; - .dw 0x3FC ; - .dw 0x3FD ; - .dw 0x3FE ; - .dw 0x3FF ; -#endif - .dw 0x3A00 ; - .dw 0x3A01 ; - .dw 0x3A02 ; - .dw 0x3A03 ; - .dw 0x3A04 ; - .dw 0x3A05 ; - .dw 0x3A06 ; - .dw 0x3A07 ; - .dw 0x3A08 ; - .dw 0x3A09 ; - .dw 0x3A0A ; - .dw 0x3A0B ; - .dw 0x3A0C ; - .dw 0x3A0D ; - .dw 0x3A0E ; - .dw 0x3A0F ; - .dw 0x3A10 ; - .dw 0x3A11 ; - .dw 0x3A12 ; - .dw 0x3A13 ; - .dw 0x3A14 ; - .dw 0x3A15 ; - .dw 0x3A16 ; - .dw 0x3A17 ; - .dw 0x3A18 ; - .dw 0x3A19 ; - .dw 0x3A1A ; - .dw 0x3A1B ; - .dw 0x3A1C ; - .dw 0x3A1D ; - .dw 0x3A1E ; - .dw 0x3A1F ; - .dw 0x3A20 ; - .dw 0x3A21 ; - .dw 0x3A22 ; - .dw 0x3A23 ; - .dw 0x3A24 ; - .dw 0x3A25 ; - .dw 0x3A26 ; - .dw 0x3A27 ; - .dw 0x3A28 ; - .dw 0x3A29 ; - .dw 0x3A2A ; - .dw 0x3A2B ; - .dw 0x3A2C ; - .dw 0x3A2D ; - .dw 0x3A2E ; - .dw 0x3A2F ; - .dw 0x3A30 ; - .dw 0x3A31 ; - .dw 0x3A32 ; - .dw 0x3A33 ; - .dw 0x3A34 ; - .dw 0x3A35 ; - .dw 0x3A36 ; - .dw 0x3A37 ; - .dw 0x3A38 ; - .dw 0x3A39 ; - .dw 0x3A3A ; - .dw 0x3A3B ; - .dw 0x3A3C ; - .dw 0x3A3D ; - .dw 0x3A3E ; - .dw 0x3A3F ; - .dw 0x3A40 ; - .dw 0x3A41 ; - .dw 0x3A42 ; - .dw 0x3A43 ; - .dw 0x3A44 ; - .dw 0x3A45 ; - .dw 0x3A46 ; - .dw 0x3A47 ; - .dw 0x3A48 ; - .dw 0x3A49 ; - .dw 0x3A4A ; - .dw 0x3A4B ; - .dw 0x3A4C ; - .dw 0x3A4D ; - .dw 0x3A4E ; - .dw 0x3A4F ; - .dw 0x3A50 ; - .dw 0x3A51 ; - .dw 0x3A52 ; - .dw 0x3A53 ; - .dw 0x3A54 ; - .dw 0x3A55 ; - .dw 0x3A56 ; - .dw 0x3A57 ; - .dw 0x3A58 ; - .dw 0x3A59 ; - .dw 0x3A5A ; - .dw 0x3A5B ; - .dw 0x3A5C ; - .dw 0x3A5D ; - .dw 0x3A5E ; - .dw 0x3A5F ; - .dw 0x3A60 ; - .dw 0x3A61 ; - .dw 0x3A62 ; - .dw 0x3A63 ; - .dw 0x3A64 ; - .dw 0x3A65 ; - .dw 0x3A66 ; - .dw 0x3A67 ; - .dw 0x3A68 ; - .dw 0x3A69 ; - .dw 0x3A6A ; - .dw 0x3A6B ; - .dw 0x3A6C ; - .dw 0x3A6D ; - .dw 0x3A6E ; - .dw 0x3A6F ; - .dw 0x3A70 ; - .dw 0x3A71 ; - .dw 0x3A72 ; - .dw 0x3A73 ; - .dw 0x3A74 ; - .dw 0x3A75 ; - .dw 0x3A76 ; - .dw 0x3A77 ; - .dw 0x3A78 ; - .dw 0x3A79 ; - .dw 0x3A7A ; - .dw 0x3A7B ; - .dw 0x3A7C ; - .dw 0x3A7D ; - .dw 0x3A7E ; - .dw 0x3A7F ; - .dw 0x3A80 ; - .dw 0x3A81 ; - .dw 0x3A82 ; - .dw 0x3A83 ; - .dw 0x3A84 ; - .dw 0x3A85 ; - .dw 0x3A86 ; - .dw 0x3A87 ; - .dw 0x3A88 ; - .dw 0x3A89 ; - .dw 0x3A8A ; - .dw 0x3A8B ; - .dw 0x3A8C ; - .dw 0x3A8D ; - .dw 0x3A8E ; - .dw 0x3A8F ; - .dw 0x3A90 ; - .dw 0x3A91 ; - .dw 0x3A92 ; - .dw 0x3A93 ; - .dw 0x3A94 ; - .dw 0x3A95 ; - .dw 0x3A96 ; - .dw 0x3A97 ; - .dw 0x3A98 ; - .dw 0x3A99 ; - .dw 0x3A9A ; - .dw 0x3A9B ; - .dw 0x3A9C ; - .dw 0x3A9D ; - .dw 0x3A9E ; - .dw 0x3A9F ; - .dw 0x3AA0 ; - .dw 0x3AA1 ; - .dw 0x3AA2 ; - .dw 0x3AA3 ; - .dw 0x3AA4 ; - .dw 0x3AA5 ; - .dw 0x3AA6 ; - .dw 0x3AA7 ; - .dw 0x3AA8 ; - .dw 0x3AA9 ; - .dw 0x3AAA ; - .dw 0x3AAB ; - .dw 0x3AAC ; - .dw 0x3AAD ; - .dw 0x3AAE ; - .dw 0x3AAF ; - .dw 0x3AB0 ; - .dw 0x3AB1 ; - .dw 0x3AB2 ; - .dw 0x3AB3 ; - .dw 0x3AB4 ; - .dw 0x3AB5 ; - .dw 0x3AB6 ; - .dw 0x3AB7 ; - .dw 0x3AB8 ; - .dw 0x3AB9 ; - .dw 0x3ABA ; - .dw 0x3ABB ; - .dw 0x3ABC ; - .dw 0x3ABD ; - .dw 0x3ABE ; - .dw 0x3ABF ; - .dw 0x3AC0 ; - .dw 0x3AC1 ; - .dw 0x3AC2 ; - .dw 0x3AC3 ; - .dw 0x3AC4 ; - .dw 0x3AC5 ; - .dw 0x3AC6 ; - .dw 0x3AC7 ; - .dw 0x3AC8 ; - .dw 0x3AC9 ; - .dw 0x3ACA ; - .dw 0x3ACB ; - .dw 0x3ACC ; - .dw 0x3ACD ; - .dw 0x3ACE ; - .dw 0x3ACF ; - .dw 0x3AD0 ; - .dw 0x3AD1 ; - .dw 0x3AD2 ; - .dw 0x3AD3 ; - .dw 0x3AD4 ; - .dw 0x3AD5 ; - .dw 0x3AD6 ; - .dw 0x3AD7 ; - .dw 0x3AD8 ; - .dw 0x3AD9 ; - .dw 0x3ADA ; - .dw 0x3ADB ; - .dw 0x3ADC ; - .dw 0x3ADD ; - .dw 0x3ADE ; - .dw 0x3ADF ; - .dw 0x3AE0 ; - .dw 0x3AE1 ; - .dw 0x3AE2 ; - .dw 0x3AE3 ; - .dw 0x3AE4 ; - .dw 0x3AE5 ; - .dw 0x3AE6 ; - .dw 0x3AE7 ; - .dw 0x3AE8 ; - .dw 0x3AE9 ; - .dw 0x3AEA ; - .dw 0x3AEB ; - .dw 0x3AEC ; - .dw 0x3AED ; - .dw 0x3AEE ; - .dw 0x3AEF ; - .dw 0x3AF0 ; - .dw 0x3AF1 ; - .dw 0x3AF2 ; - .dw 0x3AF3 ; - .dw 0x3AF4 ; - .dw 0x3AF5 ; - .dw 0x3AF6 ; - .dw 0x3AF7 ; - .dw 0x3AF8 ; - .dw 0x3AF9 ; - .dw 0x3AFA ; - .dw 0x3AFB ; - .dw 0x3AFC ; - .dw 0x3AFD ; - .dw 0x3AFE ; - .dw 0x3AFF ; - .dw 0x3B00 ; - .dw 0x3B01 ; - .dw 0x3B02 ; - .dw 0x3B03 ; - .dw 0x3B04 ; - .dw 0x3B05 ; - .dw 0x3B06 ; - .dw 0x3B07 ; - .dw 0x3B08 ; - .dw 0x3B09 ; - .dw 0x3B0A ; - .dw 0x3B0B ; - .dw 0x3B0C ; - .dw 0x3B0D ; - .dw 0x3B0E ; - .dw 0x3B0F ; - .dw 0x3B10 ; - .dw 0x3B11 ; - .dw 0x3B12 ; - .dw 0x3B13 ; - .dw 0x3B14 ; - .dw 0x3B15 ; - .dw 0x3B16 ; - .dw 0x3B17 ; - .dw 0x3B18 ; - .dw 0x3B19 ; - .dw 0x3B1A ; - .dw 0x3B1B ; - .dw 0x3B1C ; - .dw 0x3B1D ; - .dw 0x3B1E ; - .dw 0x3B1F ; - .dw 0x3B20 ; - .dw 0x3B21 ; - .dw 0x3B22 ; - .dw 0x3B23 ; - .dw 0x3B24 ; - .dw 0x3B25 ; - .dw 0x3B26 ; - .dw 0x3B27 ; - .dw 0x3B28 ; - .dw 0x3B29 ; - .dw 0x3B2A ; - .dw 0x3B2B ; - .dw 0x3B2C ; - .dw 0x3B2D ; - .dw 0x3B2E ; - .dw 0x3B2F ; - .dw 0x3B30 ; - .dw 0x3B31 ; - .dw 0x3B32 ; - .dw 0x3B33 ; - .dw 0x3B34 ; - .dw 0x3B35 ; - .dw 0x3B36 ; - .dw 0x3B37 ; - .dw 0x3B38 ; - .dw 0x3B39 ; - .dw 0x3B3A ; - .dw 0x3B3B ; - .dw 0x3B3C ; - .dw 0x3B3D ; - .dw 0x3B3E ; - .dw 0x3B3F ; - .dw 0x3B40 ; - .dw 0x3B41 ; - .dw 0x3B42 ; - .dw 0x3B43 ; - .dw 0x3B44 ; - .dw 0x3B45 ; - .dw 0x3B46 ; - .dw 0x3B47 ; - .dw 0x3B48 ; - .dw 0x3B49 ; - .dw 0x3B4A ; - .dw 0x3B4B ; - .dw 0x3B4C ; - .dw 0x3B4D ; - .dw 0x3B4E ; - .dw 0x3B4F ; - .dw 0x3B50 ; - .dw 0x3B51 ; - .dw 0x3B52 ; - .dw 0x3B53 ; - .dw 0x3B54 ; - .dw 0x3B55 ; - .dw 0x3B56 ; - .dw 0x3B57 ; - .dw 0x3B58 ; - .dw 0x3B59 ; - .dw 0x3B5A ; - .dw 0x3B5B ; - .dw 0x3B5C ; - .dw 0x3B5D ; - .dw 0x3B5E ; - .dw 0x3B5F ; - .dw 0x3B60 ; - .dw 0x3B61 ; - .dw 0x3B62 ; - .dw 0x3B63 ; - .dw 0x3B64 ; - .dw 0x3B65 ; - .dw 0x3B66 ; - .dw 0x3B67 ; - .dw 0x3B68 ; - .dw 0x3B69 ; - .dw 0x3B6A ; - .dw 0x3B6B ; - .dw 0x3B6C ; - .dw 0x3B6D ; - .dw 0x3B6E ; - .dw 0x3B6F ; - .dw 0x3B70 ; - .dw 0x3B71 ; - .dw 0x3B72 ; - .dw 0x3B73 ; - .dw 0x3B74 ; - .dw 0x3B75 ; - .dw 0x3B76 ; - .dw 0x3B77 ; - .dw 0x3B78 ; - .dw 0x3B79 ; - .dw 0x3B7A ; - .dw 0x3B7B ; - .dw 0x3B7C ; - .dw 0x3B7D ; - .dw 0x3B7E ; - .dw 0x3B7F ; - .dw 0x3B80 ; - .dw 0x3B81 ; - .dw 0x3B82 ; - .dw 0x3B83 ; - .dw 0x3B84 ; - .dw 0x3B85 ; - .dw 0x3B86 ; - .dw 0x3B87 ; - .dw 0x3B88 ; - .dw 0x3B89 ; - .dw 0x3B8A ; - .dw 0x3B8B ; - .dw 0x3B8C ; - .dw 0x3B8D ; - .dw 0x3B8E ; - .dw 0x3B8F ; - .dw 0x3B90 ; - .dw 0x3B91 ; - .dw 0x3B92 ; - .dw 0x3B93 ; - .dw 0x3B94 ; - .dw 0x3B95 ; - .dw 0x3B96 ; - .dw 0x3B97 ; - .dw 0x3B98 ; - .dw 0x3B99 ; - .dw 0x3B9A ; - .dw 0x3B9B ; - .dw 0x3B9C ; - .dw 0x3B9D ; - .dw 0x3B9E ; - .dw 0x3B9F ; - .dw 0x3BA0 ; - .dw 0x3BA1 ; - .dw 0x3BA2 ; - .dw 0x3BA3 ; - .dw 0x3BA4 ; - .dw 0x3BA5 ; - .dw 0x3BA6 ; - .dw 0x3BA7 ; - .dw 0x3BA8 ; - .dw 0x3BA9 ; - .dw 0x3BAA ; - .dw 0x3BAB ; - .dw 0x3BAC ; - .dw 0x3BAD ; - .dw 0x3BAE ; - .dw 0x3BAF ; - .dw 0x3BB0 ; - .dw 0x3BB1 ; - .dw 0x3BB2 ; - .dw 0x3BB3 ; - .dw 0x3BB4 ; - .dw 0x3BB5 ; - .dw 0x3BB6 ; - .dw 0x3BB7 ; - .dw 0x3BB8 ; - .dw 0x3BB9 ; - .dw 0x3BBA ; - .dw 0x3BBB ; - .dw 0x3BBC ; - .dw 0x3BBD ; - .dw 0x3BBE ; - .dw 0x3BBF ; - .dw 0x3BC0 ; - .dw 0x3BC1 ; - .dw 0x3BC2 ; - .dw 0x3BC3 ; - .dw 0x3BC4 ; - .dw 0x3BC5 ; - .dw 0x3BC6 ; - .dw 0x3BC7 ; - .dw 0x3BC8 ; - .dw 0x3BC9 ; - .dw 0x3BCA ; - .dw 0x3BCB ; - .dw 0x3BCC ; - .dw 0x3BCD ; - .dw 0x3BCE ; - .dw 0x3BCF ; - .dw 0x3BD0 ; - .dw 0x3BD1 ; - .dw 0x3BD2 ; - .dw 0x3BD3 ; - .dw 0x3BD4 ; - .dw 0x3BD5 ; - .dw 0x3BD6 ; - .dw 0x3BD7 ; - .dw 0x3BD8 ; - .dw 0x3BD9 ; - .dw 0x3BDA ; - .dw 0x3BDB ; - .dw 0x3BDC ; - .dw 0x3BDD ; - .dw 0x3BDE ; - .dw 0x3BDF ; - .dw 0x3BE0 ; - .dw 0x3BE1 ; - .dw 0x3BE2 ; - .dw 0x3BE3 ; - .dw 0x3BE4 ; - .dw 0x3BE5 ; - .dw 0x3BE6 ; - .dw 0x3BE7 ; - .dw 0x3BE8 ; - .dw 0x3BE9 ; - .dw 0x3BEA ; - .dw 0x3BEB ; - .dw 0x3BEC ; - .dw 0x3BED ; - .dw 0x3BEE ; - .dw 0x3BEF ; - .dw 0x3BF0 ; - .dw 0x3BF1 ; - .dw 0x3BF2 ; - .dw 0x3BF3 ; - .dw 0x3BF4 ; - .dw 0x3BF5 ; - .dw 0x3BF6 ; - .dw 0x3BF7 ; - .dw 0x3BF8 ; - .dw 0x3BF9 ; - .dw 0x3BFA ; - .dw 0x3BFB ; - .dw 0x3BFC ; - .dw 0x3BFD ; - .dw 0x3BFE ; - .dw 0x3BFF ; - .dw 0x3140 ; - .dw 0x3141 ; - .dw 0x3142 ; - .dw 0x3143 ; - .dw 0x3144 ; - .dw 0x3145 ; - .dw 0x3146 ; - .dw 0x3147 ; - .dw 0x3148 ; - .dw 0x3149 ; - .dw 0x314A ; - .dw 0x314B ; - .dw 0x314C ; - .dw 0x314D ; - .dw 0x314E ; - .dw 0x314F ; - .dw 0x3150 ; - .dw 0x3151 ; - .dw 0x3152 ; - .dw 0x3153 ; - .dw 0x3154 ; - .dw 0x3155 ; - .dw 0x3156 ; - .dw 0x3157 ; - .dw 0x3158 ; - .dw 0x3159 ; - .dw 0x315A ; - .dw 0x315B ; - .dw 0x315C ; - .dw 0x315D ; - .dw 0x315E ; - .dw 0x315F ; - .dw 0x3160 ; - .dw 0x3161 ; - .dw 0x3162 ; - .dw 0x3163 ; - .dw 0x3164 ; - .dw 0x3165 ; - .dw 0x3166 ; - .dw 0x3167 ; - .dw 0x3168 ; - .dw 0x3169 ; - .dw 0x316A ; - .dw 0x316B ; - .dw 0x316C ; - .dw 0x316D ; - .dw 0x316E ; - .dw 0x316F ; - .dw 0x3170 ; - .dw 0x3171 ; - .dw 0x3172 ; - .dw 0x3173 ; - .dw 0x3174 ; - .dw 0x3175 ; - .dw 0x3176 ; - .dw 0x3177 ; - .dw 0x3178 ; - .dw 0x3179 ; - .dw 0x317A ; - .dw 0x317B ; - .dw 0x317C ; - .dw 0x317D ; - .dw 0x317E ; - .dw 0x317F ; - .dw 0x3340 ; - .dw 0x3341 ; - .dw 0x3342 ; - .dw 0x3343 ; - .dw 0x3344 ; - .dw 0x3345 ; - .dw 0x3346 ; - .dw 0x3347 ; - .dw 0x3348 ; - .dw 0x3349 ; - .dw 0x334A ; - .dw 0x334B ; - .dw 0x334C ; - .dw 0x334D ; - .dw 0x334E ; - .dw 0x334F ; - .dw 0x3350 ; - .dw 0x3351 ; - .dw 0x3352 ; - .dw 0x3353 ; - .dw 0x3354 ; - .dw 0x3355 ; - .dw 0x3356 ; - .dw 0x3357 ; - .dw 0x3358 ; - .dw 0x3359 ; - .dw 0x335A ; - .dw 0x335B ; - .dw 0x335C ; - .dw 0x335D ; - .dw 0x335E ; - .dw 0x335F ; - .dw 0x3360 ; - .dw 0x3361 ; - .dw 0x3362 ; - .dw 0x3363 ; - .dw 0x3364 ; - .dw 0x3365 ; - .dw 0x3366 ; - .dw 0x3367 ; - .dw 0x3368 ; - .dw 0x3369 ; - .dw 0x336A ; - .dw 0x336B ; - .dw 0x336C ; - .dw 0x336D ; - .dw 0x336E ; - .dw 0x336F ; - .dw 0x3370 ; - .dw 0x3371 ; - .dw 0x3372 ; - .dw 0x3373 ; - .dw 0x3374 ; - .dw 0x3375 ; - .dw 0x3376 ; - .dw 0x3377 ; - .dw 0x3378 ; - .dw 0x3379 ; - .dw 0x337A ; - .dw 0x337B ; - .dw 0x337C ; - .dw 0x337D ; - .dw 0x337E ; - .dw 0x337F ; - .dw 0x3540 ; - .dw 0x3541 ; - .dw 0x3542 ; - .dw 0x3543 ; - .dw 0x3544 ; - .dw 0x3545 ; - .dw 0x3546 ; - .dw 0x3547 ; - .dw 0x3548 ; - .dw 0x3549 ; - .dw 0x354A ; - .dw 0x354B ; - .dw 0x354C ; - .dw 0x354D ; - .dw 0x354E ; - .dw 0x354F ; - .dw 0x3550 ; - .dw 0x3551 ; - .dw 0x3552 ; - .dw 0x3553 ; - .dw 0x3554 ; - .dw 0x3555 ; - .dw 0x3556 ; - .dw 0x3557 ; - .dw 0x3558 ; - .dw 0x3559 ; - .dw 0x355A ; - .dw 0x355B ; - .dw 0x355C ; - .dw 0x355D ; - .dw 0x355E ; - .dw 0x355F ; - .dw 0x3560 ; - .dw 0x3561 ; - .dw 0x3562 ; - .dw 0x3563 ; - .dw 0x3564 ; - .dw 0x3565 ; - .dw 0x3566 ; - .dw 0x3567 ; - .dw 0x3568 ; - .dw 0x3569 ; - .dw 0x356A ; - .dw 0x356B ; - .dw 0x356C ; - .dw 0x356D ; - .dw 0x356E ; - .dw 0x356F ; - .dw 0x3570 ; - .dw 0x3571 ; - .dw 0x3572 ; - .dw 0x3573 ; - .dw 0x3574 ; - .dw 0x3575 ; - .dw 0x3576 ; - .dw 0x3577 ; - .dw 0x3578 ; - .dw 0x3579 ; - .dw 0x357A ; - .dw 0x357B ; - .dw 0x357C ; - .dw 0x357D ; - .dw 0x357E ; - .dw 0x357F ; - .dw 0x3740 ; - .dw 0x3741 ; - .dw 0x3742 ; - .dw 0x3743 ; - .dw 0x3744 ; - .dw 0x3745 ; - .dw 0x3746 ; - .dw 0x3747 ; - .dw 0x3748 ; - .dw 0x3749 ; - .dw 0x374A ; - .dw 0x374B ; - .dw 0x374C ; - .dw 0x374D ; - .dw 0x374E ; - .dw 0x374F ; - .dw 0x3750 ; - .dw 0x3751 ; - .dw 0x3752 ; - .dw 0x3753 ; - .dw 0x3754 ; - .dw 0x3755 ; - .dw 0x3756 ; - .dw 0x3757 ; - .dw 0x3758 ; - .dw 0x3759 ; - .dw 0x375A ; - .dw 0x375B ; - .dw 0x375C ; - .dw 0x375D ; - .dw 0x375E ; - .dw 0x375F ; - .dw 0x3760 ; - .dw 0x3761 ; - .dw 0x3762 ; - .dw 0x3763 ; - .dw 0x3764 ; - .dw 0x3765 ; - .dw 0x3766 ; - .dw 0x3767 ; - .dw 0x3768 ; - .dw 0x3769 ; - .dw 0x376A ; - .dw 0x376B ; - .dw 0x376C ; - .dw 0x376D ; - .dw 0x376E ; - .dw 0x376F ; - .dw 0x3770 ; - .dw 0x3771 ; - .dw 0x3772 ; - .dw 0x3773 ; - .dw 0x3774 ; - .dw 0x3775 ; - .dw 0x3776 ; - .dw 0x3777 ; - .dw 0x3778 ; - .dw 0x3779 ; - .dw 0x377A ; - .dw 0x377B ; - .dw 0x377C ; - .dw 0x377D ; - .dw 0x377E ; - .dw 0x377F ; - .dw 0x3940 ; - .dw 0x3941 ; - .dw 0x3942 ; - .dw 0x3943 ; - .dw 0x3944 ; - .dw 0x3945 ; - .dw 0x3946 ; - .dw 0x3947 ; - .dw 0x3948 ; - .dw 0x3949 ; - .dw 0x394A ; - .dw 0x394B ; - .dw 0x394C ; - .dw 0x394D ; - .dw 0x394E ; - .dw 0x394F ; - .dw 0x3950 ; - .dw 0x3951 ; - .dw 0x3952 ; - .dw 0x3953 ; - .dw 0x3954 ; - .dw 0x3955 ; - .dw 0x3956 ; - .dw 0x3957 ; - .dw 0x3958 ; - .dw 0x3959 ; - .dw 0x395A ; - .dw 0x395B ; - .dw 0x395C ; - .dw 0x395D ; - .dw 0x395E ; - .dw 0x395F ; - .dw 0x3960 ; - .dw 0x3961 ; - .dw 0x3962 ; - .dw 0x3963 ; - .dw 0x3964 ; - .dw 0x3965 ; - .dw 0x3966 ; - .dw 0x3967 ; - .dw 0x3968 ; - .dw 0x3969 ; - .dw 0x396A ; - .dw 0x396B ; - .dw 0x396C ; - .dw 0x396D ; - .dw 0x396E ; - .dw 0x396F ; - .dw 0x3970 ; - .dw 0x3971 ; - .dw 0x3972 ; - .dw 0x3973 ; - .dw 0x3974 ; - .dw 0x3975 ; - .dw 0x3976 ; - .dw 0x3977 ; - .dw 0x3978 ; - .dw 0x3979 ; - .dw 0x397A ; - .dw 0x397B ; - .dw 0x397C ; - .dw 0x397D ; - .dw 0x397E ; - .dw 0x397F ; - .dw 0x3D40 ; - .dw 0x3D41 ; - .dw 0x3D42 ; - .dw 0x3D43 ; - .dw 0x3D44 ; - .dw 0x3D45 ; - .dw 0x3D46 ; - .dw 0x3D47 ; - .dw 0x3D48 ; - .dw 0x3D49 ; - .dw 0x3D4A ; - .dw 0x3D4B ; - .dw 0x3D4C ; - .dw 0x3D4D ; - .dw 0x3D4E ; - .dw 0x3D4F ; - .dw 0x3D50 ; - .dw 0x3D51 ; - .dw 0x3D52 ; - .dw 0x3D53 ; - .dw 0x3D54 ; - .dw 0x3D55 ; - .dw 0x3D56 ; - .dw 0x3D57 ; - .dw 0x3D58 ; - .dw 0x3D59 ; - .dw 0x3D5A ; - .dw 0x3D5B ; - .dw 0x3D5C ; - .dw 0x3D5D ; - .dw 0x3D5E ; - .dw 0x3D5F ; - .dw 0x3D60 ; - .dw 0x3D61 ; - .dw 0x3D62 ; - .dw 0x3D63 ; - .dw 0x3D64 ; - .dw 0x3D65 ; - .dw 0x3D66 ; - .dw 0x3D67 ; - .dw 0x3D68 ; - .dw 0x3D69 ; - .dw 0x3D6A ; - .dw 0x3D6B ; - .dw 0x3D6C ; - .dw 0x3D6D ; - .dw 0x3D6E ; - .dw 0x3D6F ; - .dw 0x3D70 ; - .dw 0x3D71 ; - .dw 0x3D72 ; - .dw 0x3D73 ; - .dw 0x3D74 ; - .dw 0x3D75 ; - .dw 0x3D76 ; - .dw 0x3D77 ; - .dw 0x3D78 ; - .dw 0x3D79 ; - .dw 0x3D7A ; - .dw 0x3D7B ; - .dw 0x3D7C ; - .dw 0x3D7D ; - .dw 0x3D7E ; - .dw 0x3D7F ; - .dw 0x3F40 ; - .dw 0x3F41 ; - .dw 0x3F42 ; - .dw 0x3F43 ; - .dw 0x3F44 ; - .dw 0x3F45 ; - .dw 0x3F46 ; - .dw 0x3F47 ; - .dw 0x3F48 ; - .dw 0x3F49 ; - .dw 0x3F4A ; - .dw 0x3F4B ; - .dw 0x3F4C ; - .dw 0x3F4D ; - .dw 0x3F4E ; - .dw 0x3F4F ; - .dw 0x3F50 ; - .dw 0x3F51 ; - .dw 0x3F52 ; - .dw 0x3F53 ; - .dw 0x3F54 ; - .dw 0x3F55 ; - .dw 0x3F56 ; - .dw 0x3F57 ; - .dw 0x3F58 ; - .dw 0x3F59 ; - .dw 0x3F5A ; - .dw 0x3F5B ; - .dw 0x3F5C ; - .dw 0x3F5D ; - .dw 0x3F5E ; - .dw 0x3F5F ; - .dw 0x3F60 ; - .dw 0x3F61 ; - .dw 0x3F62 ; - .dw 0x3F63 ; - .dw 0x3F64 ; - .dw 0x3F65 ; - .dw 0x3F66 ; - .dw 0x3F67 ; - .dw 0x3F68 ; - .dw 0x3F69 ; - .dw 0x3F6A ; - .dw 0x3F6B ; - .dw 0x3F6C ; - .dw 0x3F6D ; - .dw 0x3F6E ; - .dw 0x3F6F ; - .dw 0x3F70 ; - .dw 0x3F71 ; - .dw 0x3F72 ; - .dw 0x3F73 ; - .dw 0x3F74 ; - .dw 0x3F75 ; - .dw 0x3F76 ; - .dw 0x3F77 ; - .dw 0x3F78 ; - .dw 0x3F79 ; - .dw 0x3F7A ; - .dw 0x3F7B ; - .dw 0x3F7C ; - .dw 0x3F7D ; - .dw 0x3F7E ; - .dw 0x3F7F ; - .dw 0x3104 ; - .dw 0x3105 ; - .dw 0x310C ; - .dw 0x310D ; - .dw 0x3114 ; - .dw 0x3115 ; - .dw 0x311C ; - .dw 0x311D ; - .dw 0x3124 ; - .dw 0x3125 ; - .dw 0x312C ; - .dw 0x312D ; - .dw 0x3134 ; - .dw 0x3135 ; - .dw 0x313C ; - .dw 0x313D ; - .dw 0x3304 ; - .dw 0x3305 ; - .dw 0x330C ; - .dw 0x330D ; - .dw 0x3314 ; - .dw 0x3315 ; - .dw 0x331C ; - .dw 0x331D ; - .dw 0x3324 ; - .dw 0x3325 ; - .dw 0x332C ; - .dw 0x332D ; - .dw 0x3334 ; - .dw 0x3335 ; - .dw 0x333C ; - .dw 0x333D ; - .dw 0x3504 ; - .dw 0x3505 ; - .dw 0x350C ; - .dw 0x350D ; - .dw 0x3514 ; - .dw 0x3515 ; - .dw 0x351C ; - .dw 0x351D ; - .dw 0x3524 ; - .dw 0x3525 ; - .dw 0x352C ; - .dw 0x352D ; - .dw 0x3534 ; - .dw 0x3535 ; - .dw 0x353C ; - .dw 0x353D ; - .dw 0x3704 ; - .dw 0x3705 ; - .dw 0x370C ; - .dw 0x370D ; - .dw 0x3714 ; - .dw 0x3715 ; - .dw 0x371C ; - .dw 0x371D ; - .dw 0x3724 ; - .dw 0x3725 ; - .dw 0x372C ; - .dw 0x372D ; - .dw 0x3734 ; - .dw 0x3735 ; - .dw 0x373C ; - .dw 0x373D ; - .dw 0x3904 ; - .dw 0x3905 ; - .dw 0x390C ; - .dw 0x390D ; - .dw 0x3914 ; - .dw 0x3915 ; - .dw 0x391C ; - .dw 0x391D ; - .dw 0x3924 ; - .dw 0x3925 ; - .dw 0x392C ; - .dw 0x392D ; - .dw 0x3934 ; - .dw 0x3935 ; - .dw 0x393C ; - .dw 0x393D ; - .dw 0x3D04 ; - .dw 0x3D05 ; - .dw 0x3D0C ; - .dw 0x3D0D ; - .dw 0x3D14 ; - .dw 0x3D15 ; - .dw 0x3D1C ; - .dw 0x3D1D ; - .dw 0x3D24 ; - .dw 0x3D25 ; - .dw 0x3D2C ; - .dw 0x3D2D ; - .dw 0x3D34 ; - .dw 0x3D35 ; - .dw 0x3D3C ; - .dw 0x3D3D ; - .dw 0x3F04 ; - .dw 0x3F05 ; - .dw 0x3F0C ; - .dw 0x3F0D ; - .dw 0x3F14 ; - .dw 0x3F15 ; - .dw 0x3F1C ; - .dw 0x3F1D ; - .dw 0x3F24 ; - .dw 0x3F25 ; - .dw 0x3F2C ; - .dw 0x3F2D ; - .dw 0x3F34 ; - .dw 0x3F35 ; - .dw 0x3F3C ; - .dw 0x3F3D ; - .dw 0x3820 ; - .dw 0x3821 ; - .dw 0x3822 ; - .dw 0x3823 ; - .dw 0x3824 ; - .dw 0x3825 ; - .dw 0x3826 ; - .dw 0x3827 ; - .dw 0x3828 ; - .dw 0x3829 ; - .dw 0x382A ; - .dw 0x382B ; - .dw 0x382C ; - .dw 0x382D ; - .dw 0x382E ; - .dw 0x382F ; - .dw 0x3860 ; - .dw 0x3861 ; - .dw 0x3862 ; - .dw 0x3863 ; - .dw 0x3864 ; - .dw 0x3865 ; - .dw 0x3866 ; - .dw 0x3867 ; - .dw 0x3868 ; - .dw 0x3869 ; - .dw 0x386A ; - .dw 0x386B ; - .dw 0x386C ; - .dw 0x386D ; - .dw 0x386E ; - .dw 0x386F ; - .dw 0x38A0 ; - .dw 0x38A1 ; - .dw 0x38A2 ; - .dw 0x38A3 ; - .dw 0x38A4 ; - .dw 0x38A5 ; - .dw 0x38A6 ; - .dw 0x38A7 ; - .dw 0x38A8 ; - .dw 0x38A9 ; - .dw 0x38AA ; - .dw 0x38AB ; - .dw 0x38AC ; - .dw 0x38AD ; - .dw 0x38AE ; - .dw 0x38AF ; - .dw 0x38E0 ; - .dw 0x38E1 ; - .dw 0x38E2 ; - .dw 0x38E3 ; - .dw 0x38E4 ; - .dw 0x38E5 ; - .dw 0x38E6 ; - .dw 0x38E7 ; - .dw 0x38E8 ; - .dw 0x38E9 ; - .dw 0x38EA ; - .dw 0x38EB ; - .dw 0x38EC ; - .dw 0x38ED ; - .dw 0x38EE ; - .dw 0x38EF ; - .dw 0x3920 ; - .dw 0x3921 ; - .dw 0x3922 ; - .dw 0x3923 ; - .dw 0x3924 ; - .dw 0x3925 ; - .dw 0x3926 ; - .dw 0x3927 ; - .dw 0x3928 ; - .dw 0x3929 ; - .dw 0x392A ; - .dw 0x392B ; - .dw 0x392C ; - .dw 0x392D ; - .dw 0x392E ; - .dw 0x392F ; - .dw 0x39A0 ; - .dw 0x39A1 ; - .dw 0x39A2 ; - .dw 0x39A3 ; - .dw 0x39A4 ; - .dw 0x39A5 ; - .dw 0x39A6 ; - .dw 0x39A7 ; - .dw 0x39A8 ; - .dw 0x39A9 ; - .dw 0x39AA ; - .dw 0x39AB ; - .dw 0x39AC ; - .dw 0x39AD ; - .dw 0x39AE ; - .dw 0x39AF ; - .dw 0x39E0 ; - .dw 0x39E1 ; - .dw 0x39E2 ; - .dw 0x39E3 ; - .dw 0x39E4 ; - .dw 0x39E5 ; - .dw 0x39E6 ; - .dw 0x39E7 ; - .dw 0x39E8 ; - .dw 0x39E9 ; - .dw 0x39EA ; - .dw 0x39EB ; - .dw 0x39EC ; - .dw 0x39ED ; - .dw 0x39EE ; - .dw 0x39EF ; -#if 0 - // EMUDAT = Dreg; is valid - .dw 0x3E38 ; - .dw 0x3E39 ; - .dw 0x3E3A ; - .dw 0x3E3B ; - .dw 0x3E3C ; - .dw 0x3E3D ; - .dw 0x3E3E ; - .dw 0x3E3F ; - // EMUDAT = Preg; is valid - .dw 0x3E78 ; - .dw 0x3E79 ; - .dw 0x3E7A ; - .dw 0x3E7B ; - .dw 0x3E7C ; - .dw 0x3E7D ; - .dw 0x3E7E ; - .dw 0x3E7F ; - // EMUDAT = Ireg; is valid - .dw 0x3EB8 ; - .dw 0x3EB9 ; - .dw 0x3EBA ; - .dw 0x3EBB ; - // EMUDAT = Mreg; is valid - .dw 0x3EBC ; - .dw 0x3EBD ; - .dw 0x3EBE ; - .dw 0x3EBF ; - // EMUDAT = Breg; is valid - .dw 0x3EF8 ; - .dw 0x3EF9 ; - .dw 0x3EFA ; - .dw 0x3EFB ; - // EMUDAT = Lreg; is valid - .dw 0x3EFC ; - .dw 0x3EFD ; - .dw 0x3EFE ; - .dw 0x3EFF ; - // EMUDAT = Areg; is valid - .dw 0x3F38 ; - .dw 0x3F39 ; - .dw 0x3F3A ; - .dw 0x3F3B ; -#endif - .dw 0x3F3C ; - .dw 0x3F3D ; -#if 0 - // EMUDAT = ASTAT; is valid - .dw 0x3F3E ; - // EMUDAT = RETS; is valid - .dw 0x3F3F ; - // EMUDAT = loopregs; is valid - .dw 0x3FB8 ; - .dw 0x3FB9 ; - .dw 0x3FBA ; - .dw 0x3FBB ; - .dw 0x3FBC ; - .dw 0x3FBD ; - // EMUDAT = cycles; is valid - .dw 0x3FBE ; - .dw 0x3FBF ; - // EMUDAT = USP; is valid - .dw 0x3FF8 ; - // EMUDAT = SEQSTAT; is valid - .dw 0x3FF9 ; - // EMUDAT = SYSCFG; is valid - .dw 0x3FFA ; - // EMDUAT = RET[IXNE]; is valid - .dw 0x3FFB ; - .dw 0x3FFC ; - .dw 0x3FFD ; - .dw 0x3FFE ; - // EMUDAT = EMUDAT; is valid - .dw 0x3FFF ; - // Dreg = EMUDAT; is valid - .dw 0x31C7 ; - .dw 0x31CF ; - .dw 0x31D7 ; - .dw 0x31DF ; -#if 0 - // R4 = EMUDAT; breaks the test - .dw 0x31E7 ; - // R5 = EMUDAT; breaks the test - .dw 0x31EF ; -#endif - .dw 0x31F7 ; - .dw 0x31FF ; - // Preg = EMUDAT; is valid - .dw 0x33C7 ; - .dw 0x33CF ; - .dw 0x33D7 ; - .dw 0x33DF ; - .dw 0x33E7 ; - .dw 0x33EF ; - .dw 0x33F7 ; - .dw 0x33FF ; - // Ireg = EMUDAT; is valid - .dw 0x35C7 ; - .dw 0x35CF ; - .dw 0x35D7 ; - .dw 0x35DF ; - // Mreg = EMUDAT; is valid - .dw 0x35E7 ; - .dw 0x35EF ; - .dw 0x35F7 ; - .dw 0x35FF ; - // EMUDAT = Breg; is valid - .dw 0x37C7 ; - .dw 0x37CF ; - .dw 0x37D7 ; - .dw 0x37DF ; - // EMUDAT = Lreg; is valid - .dw 0x37E7 ; - .dw 0x37EF ; - .dw 0x37F7 ; - .dw 0x37FF ; -#endif - .dw 0x39C7 ; - .dw 0x39CF ; - .dw 0x39D7 ; - .dw 0x39DF ; - .dw 0x39E7 ; - .dw 0x39EF ; -#if 0 - // ASTAT = EMUDAT; is valid - .dw 0x39F7 ; - // RETS = EMUDAT; is valid - .dw 0x39FF ; - // loopregs = EMUDAT; is valid - .dw 0x3DC7 ; - .dw 0x3DCF ; - .dw 0x3DD7 ; - .dw 0x3DDF ; - .dw 0x3DE7 ; - .dw 0x3DEF ; - // cycles = EMUDAT; is valid - .dw 0x3DF7 ; - .dw 0x3DFF ; - // USP = EMUDAT; is valid - .dw 0x3FC7 ; - // SEQSTAT = EMUDAT; is valid - .dw 0x3FCF ; - // SYSCFG = EMUDAT; is valid - .dw 0x3FD7 ; - // RET[IXNE] = EMUDAT; is valid - .dw 0x3FDF ; - .dw 0x3FE7 ; - .dw 0x3FEF ; - .dw 0x3FF7 ; - // EMUDAT = EMUDAT; is valid - .dw 0x3FFF ; -#endif - .dw 0x3D80 ; - .dw 0x3D81 ; - .dw 0x3D82 ; - .dw 0x3D83 ; - .dw 0x3D84 ; - .dw 0x3D85 ; - .dw 0x3D86 ; - .dw 0x3D87 ; - .dw 0x3D88 ; - .dw 0x3D89 ; - .dw 0x3D8A ; - .dw 0x3D8B ; - .dw 0x3D8C ; - .dw 0x3D8D ; - .dw 0x3D8E ; - .dw 0x3D8F ; - .dw 0x3D90 ; - .dw 0x3D91 ; - .dw 0x3D92 ; - .dw 0x3D93 ; - .dw 0x3D94 ; - .dw 0x3D95 ; - .dw 0x3D96 ; - .dw 0x3D97 ; - .dw 0x3D98 ; - .dw 0x3D99 ; - .dw 0x3D9A ; - .dw 0x3D9B ; - .dw 0x3D9C ; - .dw 0x3D9D ; - .dw 0x3D9E ; - .dw 0x3D9F ; - .dw 0x3DA0 ; - .dw 0x3DA1 ; - .dw 0x3DA2 ; - .dw 0x3DA3 ; - .dw 0x3DA4 ; - .dw 0x3DA5 ; - .dw 0x3DA6 ; - .dw 0x3DA7 ; - .dw 0x3DA8 ; - .dw 0x3DA9 ; - .dw 0x3DAA ; - .dw 0x3DAB ; - .dw 0x3DAC ; - .dw 0x3DAD ; - .dw 0x3DAE ; - .dw 0x3DAF ; - .dw 0x3DB0 ; - .dw 0x3DB1 ; - .dw 0x3DB2 ; - .dw 0x3DB3 ; - .dw 0x3DB4 ; - .dw 0x3DB5 ; - .dw 0x3DB6 ; - .dw 0x3DB7 ; - .dw 0x3DB8 ; - .dw 0x3DB9 ; - .dw 0x3DBA ; - .dw 0x3DBB ; - .dw 0x3DBC ; - .dw 0x3DBD ; - .dw 0x3DBE ; - .dw 0x3DBF ; - .dw 0x3DC1 ; - .dw 0x3DC2 ; - .dw 0x3DC3 ; - .dw 0x3DC4 ; - .dw 0x3DC5 ; - .dw 0x3DC6 ; -#if 0 - // loopregs = EMUDAT; is valid - .dw 0x3DC7 ; -#endif - .dw 0x3DC9 ; - .dw 0x3DCA ; - .dw 0x3DCB ; - .dw 0x3DCC ; - .dw 0x3DCD ; - .dw 0x3DCE ; -#if 0 - // loopregs = EMUDAT; is valid - .dw 0x3DCF ; -#endif - .dw 0x3DD1 ; - .dw 0x3DD2 ; - .dw 0x3DD3 ; - .dw 0x3DD4 ; - .dw 0x3DD5 ; - .dw 0x3DD6 ; -#if 0 - // loopregs = EMUDAT; is valid - .dw 0x3DD7 ; -#endif - .dw 0x3DD9 ; - .dw 0x3DDA ; - .dw 0x3DDB ; - .dw 0x3DDC ; - .dw 0x3DDD ; - .dw 0x3DDE ; -#if 0 - // loopregs = EMUDAT; is valid - .dw 0x3DDF ; -#endif - .dw 0x3DE1 ; - .dw 0x3DE2 ; - .dw 0x3DE3 ; - .dw 0x3DE4 ; - .dw 0x3DE5 ; - .dw 0x3DE6 ; -#if 0 - // loopregs = EMUDAT; is valid - .dw 0x3DE7 ; -#endif - .dw 0x3DE9 ; - .dw 0x3DEA ; - .dw 0x3DEB ; - .dw 0x3DEC ; - .dw 0x3DED ; - .dw 0x3DEE ; -#if 0 - // loopregs = EMUDAT; is valid - .dw 0x3DEF ; -#endif - .dw 0x3DF1 ; - .dw 0x3DF2 ; - .dw 0x3DF3 ; - .dw 0x3DF4 ; - .dw 0x3DF5 ; - .dw 0x3DF6 ; -#if 0 - // cycles = EMUDAT; is valid - .dw 0x3DF7 ; -#endif - .dw 0x3DF9 ; - .dw 0x3DFA ; - .dw 0x3DFB ; - .dw 0x3DFC ; - .dw 0x3DFD ; - .dw 0x3DFE ; -#if 0 - // cycles = EMUDAT; is valid - .dw 0x3DFF ; -#endif - .dw 0x3F88 ; - .dw 0x3F89 ; - .dw 0x3F8A ; - .dw 0x3F8B ; - .dw 0x3F8C ; - .dw 0x3F8D ; - .dw 0x3F8E ; - .dw 0x3F8F ; - .dw 0x3F90 ; - .dw 0x3F91 ; - .dw 0x3F92 ; - .dw 0x3F93 ; - .dw 0x3F94 ; - .dw 0x3F95 ; - .dw 0x3F96 ; - .dw 0x3F97 ; - .dw 0x3F98 ; - .dw 0x3F99 ; - .dw 0x3F9A ; - .dw 0x3F9B ; - .dw 0x3F9C ; - .dw 0x3F9D ; - .dw 0x3F9E ; - .dw 0x3F9F ; - .dw 0x3FA0 ; - .dw 0x3FA1 ; - .dw 0x3FA2 ; - .dw 0x3FA3 ; - .dw 0x3FA4 ; - .dw 0x3FA5 ; - .dw 0x3FA6 ; - .dw 0x3FA7 ; - .dw 0x3FA8 ; - .dw 0x3FA9 ; - .dw 0x3FAA ; - .dw 0x3FAB ; - .dw 0x3FAC ; - .dw 0x3FAD ; - .dw 0x3FAE ; - .dw 0x3FAF ; - .dw 0x3FB0 ; - .dw 0x3FB1 ; - .dw 0x3FB2 ; - .dw 0x3FB3 ; - .dw 0x3FB4 ; - .dw 0x3FB5 ; - .dw 0x3FB6 ; - .dw 0x3FB7 ; -#if 0 - // EMUDAT = loopregs; is valid - .dw 0x3FB8 ; - .dw 0x3FB9 ; - .dw 0x3FBA ; - .dw 0x3FBB ; - .dw 0x3FBC ; - .dw 0x3FBD ; - // EMUDAT = cycles; is valid - .dw 0x3FBE ; - .dw 0x3FBF ; -#endif - .dw 0x3FC9 ; - .dw 0x3FCA ; - .dw 0x3FCB ; - .dw 0x3FCC ; - .dw 0x3FCD ; - .dw 0x3FCE ; -#if 0 - // SEQSTAT = EMUDAT; is valid - .dw 0x3FCF ; -#endif - .dw 0x3FD1 ; - .dw 0x3FD2 ; - .dw 0x3FD3 ; - .dw 0x3FD4 ; - .dw 0x3FD5 ; - .dw 0x3FD6 ; -#if 0 - // SYSCFG = EMUDAT; is valid - .dw 0x3FD7 ; -#endif - .dw 0x3FD9 ; - .dw 0x3FDA ; - .dw 0x3FDB ; - .dw 0x3FDC ; - .dw 0x3FDD ; - .dw 0x3FDE ; -#if 0 - // RET[IXNE] = EMUDAT; is valid - .dw 0x3FDF ; -#endif - .dw 0x3FE1 ; - .dw 0x3FE2 ; - .dw 0x3FE3 ; - .dw 0x3FE4 ; - .dw 0x3FE5 ; - .dw 0x3FE6 ; -#if 0 - // RET[IXNE] = EMUDAT; is valid - .dw 0x3FE7 ; -#endif - .dw 0x3FE9 ; - .dw 0x3FEA ; - .dw 0x3FEB ; - .dw 0x3FEC ; - .dw 0x3FED ; - .dw 0x3FEE ; -#if 0 - // RET[IXNE] = EMUDAT; is valid - .dw 0x3FEF ; -#endif - .dw 0x3FF1 ; - .dw 0x3FF2 ; - .dw 0x3FF3 ; - .dw 0x3FF4 ; - .dw 0x3FF5 ; - .dw 0x3FF6 ; -#if 0 - // RET[IXNE] = EMUDAT; is valid - .dw 0x3FF7 ; - // EMUDAT = SEQSTAT; is valid - .dw 0x3FF9 ; - // EMUDAT = SYSCFG; is valid - .dw 0x3FFA ; - // EMDUAT = RET[IXNE]; is valid - .dw 0x3FFB ; - .dw 0x3FFC ; - .dw 0x3FFD ; - .dw 0x3FFE ; - // EMUDAT = EMUDAT; is valid - .dw 0x3FFF ; -#endif - .dw 0x39B0 ; - .dw 0x39B1 ; - .dw 0x39B2 ; - .dw 0x39B3 ; - .dw 0x39B4 ; - .dw 0x39B5 ; - .dw 0x39B6 ; - .dw 0x39B7 ; - .dw 0x39B8 ; - .dw 0x39B9 ; - .dw 0x39BA ; - .dw 0x39BB ; - .dw 0x39BC ; - .dw 0x39BD ; - .dw 0x39BE ; - .dw 0x39BF ; - .dw 0x39F1 ; - .dw 0x39F2 ; - .dw 0x39F3 ; - .dw 0x39F4 ; - .dw 0x39F5 ; - .dw 0x39F6 ; -#if 0 - // ASTAT = EMUDAT; is valid - .dw 0x39F7 ; -#endif - .dw 0x39F9 ; - .dw 0x39FA ; - .dw 0x39FB ; - .dw 0x39FC ; - .dw 0x39FD ; - .dw 0x39FE ; -#if 0 - // RETS = EMUDAT; is valid - .dw 0x39FF ; -#endif - .dw 0x3D06 ; - .dw 0x3D07 ; - .dw 0x3D0E ; - .dw 0x3D0F ; - .dw 0x3D16 ; - .dw 0x3D17 ; - .dw 0x3D1E ; - .dw 0x3D1F ; - .dw 0x3D26 ; - .dw 0x3D27 ; - .dw 0x3D2E ; - .dw 0x3D2F ; - .dw 0x3D36 ; - .dw 0x3D37 ; - .dw 0x3D3E ; - .dw 0x3D3F ; - .dw 0x3F0E ; - .dw 0x3F0F ; - .dw 0x3F16 ; - .dw 0x3F17 ; - .dw 0x3F1E ; - .dw 0x3F1F ; - .dw 0x3F26 ; - .dw 0x3F27 ; - .dw 0x3F2E ; - .dw 0x3F2F ; - .dw 0x3F36 ; - .dw 0x3F37 ; -#if 0 - // EMUDAT = ASTAT; is valid - .dw 0x3F3E ; - // EMUDAT = RETS; is valid - .dw 0x3F3F ; -#endif - .dw 0x3936 ; - .dw 0x3937 ; - .dw 0x393E ; - .dw 0x393F ; - .dw 0x3C80 ; - .dw 0x3C81 ; - .dw 0x3C82 ; - .dw 0x3C83 ; - .dw 0x3C84 ; - .dw 0x3C85 ; - .dw 0x3C86 ; - .dw 0x3C87 ; - .dw 0x3C88 ; - .dw 0x3C89 ; - .dw 0x3C8A ; - .dw 0x3C8B ; - .dw 0x3C8C ; - .dw 0x3C8D ; - .dw 0x3C8E ; - .dw 0x3C8F ; - .dw 0x3C90 ; - .dw 0x3C91 ; - .dw 0x3C92 ; - .dw 0x3C93 ; - .dw 0x3C94 ; - .dw 0x3C95 ; - .dw 0x3C96 ; - .dw 0x3C97 ; - .dw 0x3C98 ; - .dw 0x3C99 ; - .dw 0x3C9A ; - .dw 0x3C9B ; - .dw 0x3C9C ; - .dw 0x3C9D ; - .dw 0x3C9E ; - .dw 0x3C9F ; - .dw 0x3CA0 ; - .dw 0x3CA1 ; - .dw 0x3CA2 ; - .dw 0x3CA3 ; - .dw 0x3CA4 ; - .dw 0x3CA5 ; - .dw 0x3CA6 ; - .dw 0x3CA7 ; - .dw 0x3CA8 ; - .dw 0x3CA9 ; - .dw 0x3CAA ; - .dw 0x3CAB ; - .dw 0x3CAC ; - .dw 0x3CAD ; - .dw 0x3CAE ; - .dw 0x3CAF ; - .dw 0x3CB0 ; - .dw 0x3CB1 ; - .dw 0x3CB2 ; - .dw 0x3CB3 ; - .dw 0x3CB4 ; - .dw 0x3CB5 ; - .dw 0x3CB6 ; - .dw 0x3CB7 ; - .dw 0x3CB8 ; - .dw 0x3CB9 ; - .dw 0x3CBA ; - .dw 0x3CBB ; - .dw 0x3CBC ; - .dw 0x3CBD ; - .dw 0x3CBE ; - .dw 0x3CBF ; - .dw 0x3CC0 ; - .dw 0x3CC1 ; - .dw 0x3CC2 ; - .dw 0x3CC3 ; - .dw 0x3CC4 ; - .dw 0x3CC5 ; - .dw 0x3CC6 ; - .dw 0x3CC7 ; - .dw 0x3CC8 ; - .dw 0x3CC9 ; - .dw 0x3CCA ; - .dw 0x3CCB ; - .dw 0x3CCC ; - .dw 0x3CCD ; - .dw 0x3CCE ; - .dw 0x3CCF ; - .dw 0x3CD0 ; - .dw 0x3CD1 ; - .dw 0x3CD2 ; - .dw 0x3CD3 ; - .dw 0x3CD4 ; - .dw 0x3CD5 ; - .dw 0x3CD6 ; - .dw 0x3CD7 ; - .dw 0x3CD8 ; - .dw 0x3CD9 ; - .dw 0x3CDA ; - .dw 0x3CDB ; - .dw 0x3CDC ; - .dw 0x3CDD ; - .dw 0x3CDE ; - .dw 0x3CDF ; - .dw 0x3CE0 ; - .dw 0x3CE1 ; - .dw 0x3CE2 ; - .dw 0x3CE3 ; - .dw 0x3CE4 ; - .dw 0x3CE5 ; - .dw 0x3CE6 ; - .dw 0x3CE7 ; - .dw 0x3CE8 ; - .dw 0x3CE9 ; - .dw 0x3CEA ; - .dw 0x3CEB ; - .dw 0x3CEC ; - .dw 0x3CED ; - .dw 0x3CEE ; - .dw 0x3CEF ; - .dw 0x3CF0 ; - .dw 0x3CF1 ; - .dw 0x3CF2 ; - .dw 0x3CF3 ; - .dw 0x3CF4 ; - .dw 0x3CF5 ; - .dw 0x3CF6 ; - .dw 0x3CF7 ; - .dw 0x3CF8 ; - .dw 0x3CF9 ; - .dw 0x3CFA ; - .dw 0x3CFB ; - .dw 0x3CFC ; - .dw 0x3CFD ; - .dw 0x3CFE ; - .dw 0x3CFF ; - .dw 0x3E88 ; - .dw 0x3E89 ; - .dw 0x3E8A ; - .dw 0x3E8B ; - .dw 0x3E8C ; - .dw 0x3E8D ; - .dw 0x3E8E ; - .dw 0x3E8F ; - .dw 0x3E90 ; - .dw 0x3E91 ; - .dw 0x3E92 ; - .dw 0x3E93 ; - .dw 0x3E94 ; - .dw 0x3E95 ; - .dw 0x3E96 ; - .dw 0x3E97 ; - .dw 0x3E98 ; - .dw 0x3E99 ; - .dw 0x3E9A ; - .dw 0x3E9B ; - .dw 0x3E9C ; - .dw 0x3E9D ; - .dw 0x3E9E ; - .dw 0x3E9F ; - .dw 0x3EA0 ; - .dw 0x3EA1 ; - .dw 0x3EA2 ; - .dw 0x3EA3 ; - .dw 0x3EA4 ; - .dw 0x3EA5 ; - .dw 0x3EA6 ; - .dw 0x3EA7 ; - .dw 0x3EA8 ; - .dw 0x3EA9 ; - .dw 0x3EAA ; - .dw 0x3EAB ; - .dw 0x3EAC ; - .dw 0x3EAD ; - .dw 0x3EAE ; - .dw 0x3EAF ; - .dw 0x3EB0 ; - .dw 0x3EB1 ; - .dw 0x3EB2 ; - .dw 0x3EB3 ; - .dw 0x3EB4 ; - .dw 0x3EB5 ; - .dw 0x3EB6 ; - .dw 0x3EB7 ; -#if 0 - // EMUDAT = Ireg; is valid - .dw 0x3EB8 ; - .dw 0x3EB9 ; - .dw 0x3EBA ; - .dw 0x3EBB ; - // EMUDAT = Mreg; is valid - .dw 0x3EBC ; - .dw 0x3EBD ; - .dw 0x3EBE ; - .dw 0x3EBF ; -#endif - .dw 0x3EC8 ; - .dw 0x3EC9 ; - .dw 0x3ECA ; - .dw 0x3ECB ; - .dw 0x3ECC ; - .dw 0x3ECD ; - .dw 0x3ECE ; - .dw 0x3ECF ; - .dw 0x3ED0 ; - .dw 0x3ED1 ; - .dw 0x3ED2 ; - .dw 0x3ED3 ; - .dw 0x3ED4 ; - .dw 0x3ED5 ; - .dw 0x3ED6 ; - .dw 0x3ED7 ; - .dw 0x3ED8 ; - .dw 0x3ED9 ; - .dw 0x3EDA ; - .dw 0x3EDB ; - .dw 0x3EDC ; - .dw 0x3EDD ; - .dw 0x3EDE ; - .dw 0x3EDF ; - .dw 0x3EE0 ; - .dw 0x3EE1 ; - .dw 0x3EE2 ; - .dw 0x3EE3 ; - .dw 0x3EE4 ; - .dw 0x3EE5 ; - .dw 0x3EE6 ; - .dw 0x3EE7 ; - .dw 0x3EE8 ; - .dw 0x3EE9 ; - .dw 0x3EEA ; - .dw 0x3EEB ; - .dw 0x3EEC ; - .dw 0x3EED ; - .dw 0x3EEE ; - .dw 0x3EEF ; - .dw 0x3EF0 ; - .dw 0x3EF1 ; - .dw 0x3EF2 ; - .dw 0x3EF3 ; - .dw 0x3EF4 ; - .dw 0x3EF5 ; - .dw 0x3EF6 ; - .dw 0x3EF7 ; -#if 0 - // EMUDAT = Breg; is valid - .dw 0x3EF8 ; - .dw 0x3EF9 ; - .dw 0x3EFA ; - .dw 0x3EFB ; - // EMUDAT = Lreg; is valid - .dw 0x3EFC ; - .dw 0x3EFD ; - .dw 0x3EFE ; - .dw 0x3EFF ; -#endif - .dw 0x38B0 ; - .dw 0x38B1 ; - .dw 0x38B2 ; - .dw 0x38B3 ; - .dw 0x38B4 ; - .dw 0x38B5 ; - .dw 0x38B6 ; - .dw 0x38B7 ; - .dw 0x38B8 ; - .dw 0x38B9 ; - .dw 0x38BA ; - .dw 0x38BB ; - .dw 0x38BC ; - .dw 0x38BD ; - .dw 0x38BE ; - .dw 0x38BF ; - .dw 0x38F0 ; - .dw 0x38F1 ; - .dw 0x38F2 ; - .dw 0x38F3 ; - .dw 0x38F4 ; - .dw 0x38F5 ; - .dw 0x38F6 ; - .dw 0x38F7 ; - .dw 0x38F8 ; - .dw 0x38F9 ; - .dw 0x38FA ; - .dw 0x38FB ; - .dw 0x38FC ; - .dw 0x38FD ; - .dw 0x38FE ; - .dw 0x38FF ; -#if 0 - // Preg = sysreg; is valid - .dw 0x3380 ; - .dw 0x3381 ; - .dw 0x3382 ; - .dw 0x3383 ; - .dw 0x3384 ; - .dw 0x3385 ; - .dw 0x3386 ; - .dw 0x3387 ; - .dw 0x3388 ; - .dw 0x3389 ; - .dw 0x338A ; - .dw 0x338B ; - .dw 0x338C ; - .dw 0x338D ; - .dw 0x338E ; - .dw 0x338F ; - .dw 0x3390 ; - .dw 0x3391 ; - .dw 0x3392 ; - .dw 0x3393 ; - .dw 0x3394 ; - .dw 0x3395 ; - .dw 0x3396 ; - .dw 0x3397 ; - .dw 0x3398 ; - .dw 0x3399 ; - .dw 0x339A ; - .dw 0x339B ; - .dw 0x339C ; - .dw 0x339D ; - .dw 0x339E ; - .dw 0x339F ; - .dw 0x33A0 ; - .dw 0x33A1 ; - .dw 0x33A2 ; - .dw 0x33A3 ; - .dw 0x33A4 ; - .dw 0x33A5 ; - .dw 0x33A6 ; - .dw 0x33A7 ; - .dw 0x33A8 ; - .dw 0x33A9 ; - .dw 0x33AA ; - .dw 0x33AB ; - .dw 0x33AC ; - .dw 0x33AD ; - .dw 0x33AE ; - .dw 0x33AF ; - .dw 0x33B0 ; - .dw 0x33B1 ; - .dw 0x33B2 ; - .dw 0x33B3 ; - .dw 0x33B4 ; - .dw 0x33B5 ; - .dw 0x33B6 ; - .dw 0x33B7 ; - .dw 0x33B8 ; - .dw 0x33B9 ; - .dw 0x33BA ; - .dw 0x33BB ; - .dw 0x33BC ; - .dw 0x33BD ; - .dw 0x33BE ; - .dw 0x33BF ; - .dw 0x33C1 ; - .dw 0x33C2 ; - .dw 0x33C3 ; - .dw 0x33C4 ; - .dw 0x33C5 ; - .dw 0x33C6 ; - .dw 0x33C7 ; - .dw 0x33C9 ; - .dw 0x33CA ; - .dw 0x33CB ; - .dw 0x33CC ; - .dw 0x33CD ; - .dw 0x33CE ; - .dw 0x33CF ; - .dw 0x33D1 ; - .dw 0x33D2 ; - .dw 0x33D3 ; - .dw 0x33D4 ; - .dw 0x33D5 ; - .dw 0x33D6 ; - .dw 0x33D7 ; - .dw 0x33D9 ; - .dw 0x33DA ; - .dw 0x33DB ; - .dw 0x33DC ; - .dw 0x33DD ; - .dw 0x33DE ; - .dw 0x33DF ; - .dw 0x33E1 ; - .dw 0x33E2 ; - .dw 0x33E3 ; - .dw 0x33E4 ; - .dw 0x33E5 ; - .dw 0x33E6 ; - .dw 0x33E7 ; - .dw 0x33E9 ; - .dw 0x33EA ; - .dw 0x33EB ; - .dw 0x33EC ; - .dw 0x33ED ; - .dw 0x33EE ; - .dw 0x33EF ; - .dw 0x33F1 ; - .dw 0x33F2 ; - .dw 0x33F3 ; - .dw 0x33F4 ; - .dw 0x33F5 ; - .dw 0x33F6 ; - .dw 0x33F7 ; - .dw 0x33F9 ; - .dw 0x33FA ; - .dw 0x33FB ; - .dw 0x33FC ; - .dw 0x33FD ; - .dw 0x33FE ; - .dw 0x33FF ; - .dw 0x3306 ; - .dw 0x3307 ; - .dw 0x330E ; - .dw 0x330F ; - .dw 0x3316 ; - .dw 0x3317 ; - .dw 0x331E ; - .dw 0x331F ; - .dw 0x3326 ; - .dw 0x3327 ; - .dw 0x332E ; - .dw 0x332F ; - .dw 0x3336 ; - .dw 0x3337 ; - .dw 0x333E ; - .dw 0x333F ; -#endif - .dw 0x3580 ; - .dw 0x3581 ; - .dw 0x3582 ; - .dw 0x3583 ; - .dw 0x3584 ; - .dw 0x3585 ; - .dw 0x3586 ; - .dw 0x3587 ; - .dw 0x3588 ; - .dw 0x3589 ; - .dw 0x358A ; - .dw 0x358B ; - .dw 0x358C ; - .dw 0x358D ; - .dw 0x358E ; - .dw 0x358F ; - .dw 0x3590 ; - .dw 0x3591 ; - .dw 0x3592 ; - .dw 0x3593 ; - .dw 0x3594 ; - .dw 0x3595 ; - .dw 0x3596 ; - .dw 0x3597 ; - .dw 0x3598 ; - .dw 0x3599 ; - .dw 0x359A ; - .dw 0x359B ; - .dw 0x359C ; - .dw 0x359D ; - .dw 0x359E ; - .dw 0x359F ; - .dw 0x35A0 ; - .dw 0x35A1 ; - .dw 0x35A2 ; - .dw 0x35A3 ; - .dw 0x35A4 ; - .dw 0x35A5 ; - .dw 0x35A6 ; - .dw 0x35A7 ; - .dw 0x35A8 ; - .dw 0x35A9 ; - .dw 0x35AA ; - .dw 0x35AB ; - .dw 0x35AC ; - .dw 0x35AD ; - .dw 0x35AE ; - .dw 0x35AF ; - .dw 0x35B0 ; - .dw 0x35B1 ; - .dw 0x35B2 ; - .dw 0x35B3 ; - .dw 0x35B4 ; - .dw 0x35B5 ; - .dw 0x35B6 ; - .dw 0x35B7 ; - .dw 0x35B8 ; - .dw 0x35B9 ; - .dw 0x35BA ; - .dw 0x35BB ; - .dw 0x35BC ; - .dw 0x35BD ; - .dw 0x35BE ; - .dw 0x35BF ; - .dw 0x35C1 ; - .dw 0x35C2 ; - .dw 0x35C3 ; - .dw 0x35C4 ; - .dw 0x35C5 ; - .dw 0x35C6 ; -#if 0 - // Ireg = EMUDAT; is valid - .dw 0x35C7 ; -#endif - .dw 0x35C9 ; - .dw 0x35CA ; - .dw 0x35CB ; - .dw 0x35CC ; - .dw 0x35CD ; - .dw 0x35CE ; -#if 0 - // Ireg = EMUDAT; is valid - .dw 0x35CF ; -#endif - .dw 0x35D1 ; - .dw 0x35D2 ; - .dw 0x35D3 ; - .dw 0x35D4 ; - .dw 0x35D5 ; - .dw 0x35D6 ; -#if 0 - // Ireg = EMUDAT; is valid - .dw 0x35D7 ; -#endif - .dw 0x35D9 ; - .dw 0x35DA ; - .dw 0x35DB ; - .dw 0x35DC ; - .dw 0x35DD ; - .dw 0x35DE ; -#if 0 - // Ireg = EMUDAT; is valid - .dw 0x35DF ; -#endif - .dw 0x35E1 ; - .dw 0x35E2 ; - .dw 0x35E3 ; - .dw 0x35E4 ; - .dw 0x35E5 ; - .dw 0x35E6 ; -#if 0 - // Mreg = EMUDAT; is valid - .dw 0x35E7 ; -#endif - .dw 0x35E9 ; - .dw 0x35EA ; - .dw 0x35EB ; - .dw 0x35EC ; - .dw 0x35ED ; - .dw 0x35EE ; -#if 0 - // Mreg = EMUDAT; is valid - .dw 0x35EF ; -#endif - .dw 0x35F1 ; - .dw 0x35F2 ; - .dw 0x35F3 ; - .dw 0x35F4 ; - .dw 0x35F5 ; - .dw 0x35F6 ; -#if 0 - // Mreg = EMUDAT; is valid - .dw 0x35F7 ; -#endif - .dw 0x35F9 ; - .dw 0x35FA ; - .dw 0x35FB ; - .dw 0x35FC ; - .dw 0x35FD ; - .dw 0x35FE ; -#if 0 - // Mreg = EMUDAT; is valid - .dw 0x35FF ; -#endif - .dw 0x3780 ; - .dw 0x3781 ; - .dw 0x3782 ; - .dw 0x3783 ; - .dw 0x3784 ; - .dw 0x3785 ; - .dw 0x3786 ; - .dw 0x3787 ; - .dw 0x3788 ; - .dw 0x3789 ; - .dw 0x378A ; - .dw 0x378B ; - .dw 0x378C ; - .dw 0x378D ; - .dw 0x378E ; - .dw 0x378F ; - .dw 0x3790 ; - .dw 0x3791 ; - .dw 0x3792 ; - .dw 0x3793 ; - .dw 0x3794 ; - .dw 0x3795 ; - .dw 0x3796 ; - .dw 0x3797 ; - .dw 0x3798 ; - .dw 0x3799 ; - .dw 0x379A ; - .dw 0x379B ; - .dw 0x379C ; - .dw 0x379D ; - .dw 0x379E ; - .dw 0x379F ; - .dw 0x37A0 ; - .dw 0x37A1 ; - .dw 0x37A2 ; - .dw 0x37A3 ; - .dw 0x37A4 ; - .dw 0x37A5 ; - .dw 0x37A6 ; - .dw 0x37A7 ; - .dw 0x37A8 ; - .dw 0x37A9 ; - .dw 0x37AA ; - .dw 0x37AB ; - .dw 0x37AC ; - .dw 0x37AD ; - .dw 0x37AE ; - .dw 0x37AF ; - .dw 0x37B0 ; - .dw 0x37B1 ; - .dw 0x37B2 ; - .dw 0x37B3 ; - .dw 0x37B4 ; - .dw 0x37B5 ; - .dw 0x37B6 ; - .dw 0x37B7 ; - .dw 0x37B8 ; - .dw 0x37B9 ; - .dw 0x37BA ; - .dw 0x37BB ; - .dw 0x37BC ; - .dw 0x37BD ; - .dw 0x37BE ; - .dw 0x37BF ; - .dw 0x37C1 ; - .dw 0x37C2 ; - .dw 0x37C3 ; - .dw 0x37C4 ; - .dw 0x37C5 ; - .dw 0x37C6 ; -#if 0 - // EMUDAT = Breg; is valid - .dw 0x37C7 ; -#endif - .dw 0x37C9 ; - .dw 0x37CA ; - .dw 0x37CB ; - .dw 0x37CC ; - .dw 0x37CD ; - .dw 0x37CE ; -#if 0 - // EMUDAT = Breg; is valid - .dw 0x37CF ; -#endif - .dw 0x37D1 ; - .dw 0x37D2 ; - .dw 0x37D3 ; - .dw 0x37D4 ; - .dw 0x37D5 ; - .dw 0x37D6 ; -#if 0 - // EMUDAT = Breg; is valid - .dw 0x37D7 ; -#endif - .dw 0x37D9 ; - .dw 0x37DA ; - .dw 0x37DB ; - .dw 0x37DC ; - .dw 0x37DD ; - .dw 0x37DE ; -#if 0 - // EMUDAT = Breg; is valid - .dw 0x37DF ; -#endif - .dw 0x37E1 ; - .dw 0x37E2 ; - .dw 0x37E3 ; - .dw 0x37E4 ; - .dw 0x37E5 ; - .dw 0x37E6 ; -#if 0 - // EMUDAT = Lreg; is valid - .dw 0x37E7 ; -#endif - .dw 0x37E9 ; - .dw 0x37EA ; - .dw 0x37EB ; - .dw 0x37EC ; - .dw 0x37ED ; - .dw 0x37EE ; -#if 0 - // EMUDAT = Lreg; is valid - .dw 0x37EF ; -#endif - .dw 0x37F1 ; - .dw 0x37F2 ; - .dw 0x37F3 ; - .dw 0x37F4 ; - .dw 0x37F5 ; - .dw 0x37F6 ; -#if 0 - // EMUDAT = Lreg; is valid - .dw 0x37F7 ; -#endif - .dw 0x37F9 ; - .dw 0x37FA ; - .dw 0x37FB ; - .dw 0x37FC ; - .dw 0x37FD ; - .dw 0x37FE ; -#if 0 - // EMUDAT = Lreg; is valid - .dw 0x37FF ; -#endif - .dw 0x3506 ; - .dw 0x3507 ; - .dw 0x350E ; - .dw 0x350F ; - .dw 0x3516 ; - .dw 0x3517 ; - .dw 0x351E ; - .dw 0x351F ; - .dw 0x3526 ; - .dw 0x3527 ; - .dw 0x352E ; - .dw 0x352F ; - .dw 0x3536 ; - .dw 0x3537 ; - .dw 0x353E ; - .dw 0x353F ; - .dw 0x3706 ; - .dw 0x3707 ; - .dw 0x370E ; - .dw 0x370F ; - .dw 0x3716 ; - .dw 0x3717 ; - .dw 0x371E ; - .dw 0x371F ; - .dw 0x3726 ; - .dw 0x3727 ; - .dw 0x372E ; - .dw 0x372F ; - .dw 0x3736 ; - .dw 0x3737 ; - .dw 0x373E ; - .dw 0x373F ; - .dw 0x4180 ; - .dw 0x4181 ; - .dw 0x4182 ; - .dw 0x4183 ; - .dw 0x4184 ; - .dw 0x4185 ; - .dw 0x4186 ; - .dw 0x4187 ; - .dw 0x4188 ; - .dw 0x4189 ; - .dw 0x418A ; - .dw 0x418B ; - .dw 0x418C ; - .dw 0x418D ; - .dw 0x418E ; - .dw 0x418F ; - .dw 0x4190 ; - .dw 0x4191 ; - .dw 0x4192 ; - .dw 0x4193 ; - .dw 0x4194 ; - .dw 0x4195 ; - .dw 0x4196 ; - .dw 0x4197 ; - .dw 0x4198 ; - .dw 0x4199 ; - .dw 0x419A ; - .dw 0x419B ; - .dw 0x419C ; - .dw 0x419D ; - .dw 0x419E ; - .dw 0x419F ; - .dw 0x41A0 ; - .dw 0x41A1 ; - .dw 0x41A2 ; - .dw 0x41A3 ; - .dw 0x41A4 ; - .dw 0x41A5 ; - .dw 0x41A6 ; - .dw 0x41A7 ; - .dw 0x41A8 ; - .dw 0x41A9 ; - .dw 0x41AA ; - .dw 0x41AB ; - .dw 0x41AC ; - .dw 0x41AD ; - .dw 0x41AE ; - .dw 0x41AF ; - .dw 0x41B0 ; - .dw 0x41B1 ; - .dw 0x41B2 ; - .dw 0x41B3 ; - .dw 0x41B4 ; - .dw 0x41B5 ; - .dw 0x41B6 ; - .dw 0x41B7 ; - .dw 0x41B8 ; - .dw 0x41B9 ; - .dw 0x41BA ; - .dw 0x41BB ; - .dw 0x41BC ; - .dw 0x41BD ; - .dw 0x41BE ; - .dw 0x41BF ; - .dw 0x41C0 ; - .dw 0x41C1 ; - .dw 0x41C2 ; - .dw 0x41C3 ; - .dw 0x41C4 ; - .dw 0x41C5 ; - .dw 0x41C6 ; - .dw 0x41C7 ; - .dw 0x41C8 ; - .dw 0x41C9 ; - .dw 0x41CA ; - .dw 0x41CB ; - .dw 0x41CC ; - .dw 0x41CD ; - .dw 0x41CE ; - .dw 0x41CF ; - .dw 0x41D0 ; - .dw 0x41D1 ; - .dw 0x41D2 ; - .dw 0x41D3 ; - .dw 0x41D4 ; - .dw 0x41D5 ; - .dw 0x41D6 ; - .dw 0x41D7 ; - .dw 0x41D8 ; - .dw 0x41D9 ; - .dw 0x41DA ; - .dw 0x41DB ; - .dw 0x41DC ; - .dw 0x41DD ; - .dw 0x41DE ; - .dw 0x41DF ; - .dw 0x41E0 ; - .dw 0x41E1 ; - .dw 0x41E2 ; - .dw 0x41E3 ; - .dw 0x41E4 ; - .dw 0x41E5 ; - .dw 0x41E6 ; - .dw 0x41E7 ; - .dw 0x41E8 ; - .dw 0x41E9 ; - .dw 0x41EA ; - .dw 0x41EB ; - .dw 0x41EC ; - .dw 0x41ED ; - .dw 0x41EE ; - .dw 0x41EF ; - .dw 0x41F0 ; - .dw 0x41F1 ; - .dw 0x41F2 ; - .dw 0x41F3 ; - .dw 0x41F4 ; - .dw 0x41F5 ; - .dw 0x41F6 ; - .dw 0x41F7 ; - .dw 0x41F8 ; - .dw 0x41F9 ; - .dw 0x41FA ; - .dw 0x41FB ; - .dw 0x41FC ; - .dw 0x41FD ; - .dw 0x41FE ; - .dw 0x41FF ; -.ifndef BFIN_HW - // XXX: These cause double fault on hardware when run in IVG15 !? - .dw 0x9040 ; - .dw 0x9049 ; - .dw 0x9052 ; - .dw 0x905B ; - .dw 0x9064 ; - .dw 0x906D ; - .dw 0x9076 ; - .dw 0x907F ; - .dw 0x90C0 ; - .dw 0x90C9 ; - .dw 0x90D2 ; - .dw 0x90DB ; - .dw 0x90E4 ; - .dw 0x90ED ; - .dw 0x90F6 ; - .dw 0x90FF ; -.endif - .dw 0x9180 ; -// Starting 32bit s section COUNT = 3481 - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - // Xhandler counts all EXCAUSE = 0x21; -.ifndef BFIN_HW -CHECKREG(r5, 2651 - 507); // count of all 16 bit UI's. -.else -CHECKREG(r5, 2651 - 524); // count of all 16 bit UI's. -.endif - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - // 16 bit illegal opcode handler - skips bad instruction - - // handler MADE LEAN and destructive so test runs more quckly - // se_undefinedinstruction1.dsp tests using a "nice" handler - -// [--sp] = ASTAT; // save what we damage -// [--sp] = (r7 - r6); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction -CC = r7 == r6; -IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave - - R6 = 0x22; // Also accept illegal insn combo -CC = r7 == r6; -IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave - -dbg_fail; - -UNDEFINEDINSTRUCTION: - R7 = RETX; // Fix up return address - - r4 += 2; - CC = r4 == r7; - if !CC jump fail; - - R7 += 2; // skip offending 16 bit instruction - -RETX = r7; // and put back in RETX - - R5 += 1; // Increment global counter - -OUT: -// (r7 - r6) = [sp++]; -// ASTAT = [sp++]; - -RTX; -fail: -dbg_fail; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - // padding for the icache - -EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_undefinedinstruction3.S b/sim/testsuite/sim/bfin/se_undefinedinstruction3.S deleted file mode 100644 index 0acfb88..0000000 --- a/sim/testsuite/sim/bfin/se_undefinedinstruction3.S +++ /dev/null @@ -1,6022 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction3/se_undefinedinstruction3.dsp -// Description: 32 bit special cases Undefined Instructions in Supervisor Mode -# mach: bfin -# sim: --environment operating -# xfail: "missing checks in A0/A1 macfunc" bfin-* - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 // change for how much stack you need -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; - -LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - - P0 += 4; // EVT0 not used (Emulation) - - P0 += 4; // EVT1 not used (Reset) - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - P0 += 4; // EVT4 not used (Global Interrupt Enable) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - A0 = 0; // reset accumulators - A1 = 0; - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: - -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** - - // count of UI's will be in r5, which was initialized to 0 by header - - .dw 0xE802 ; - .dw 0xB3FD ; - .dw 0xE803 ; - .dw 0xD461 ; - .dw 0xE804 ; - .dw 0x36A1 ; - .dw 0xE805 ; - .dw 0x7FED ; - .dw 0xE806 ; - .dw 0xFEB3 ; - .dw 0xE807 ; - .dw 0x8785 ; - .dw 0xE808 ; - .dw 0x2F21 ; - .dw 0xE809 ; - .dw 0x2889 ; - .dw 0xE80A ; - .dw 0x96B7 ; - .dw 0xE80B ; - .dw 0x8357 ; - .dw 0xE80C ; - .dw 0x5D07 ; - .dw 0xE80D ; - .dw 0x13D5 ; - .dw 0xE80E ; - .dw 0x1C11 ; - .dw 0xE80F ; - .dw 0x19D3 ; - .dw 0xE810 ; - .dw 0xBF4B ; - .dw 0xE811 ; - .dw 0xEF89 ; - .dw 0xE812 ; - .dw 0x2BD ; - .dw 0xE813 ; - .dw 0x6FC5 ; - .dw 0xE814 ; - .dw 0x89F1 ; - .dw 0xE815 ; - .dw 0x1D13 ; - .dw 0xE816 ; - .dw 0xA03F ; - .dw 0xE817 ; - .dw 0x9681 ; - .dw 0xE818 ; - .dw 0x2961 ; - .dw 0xE819 ; - .dw 0xEE23 ; - .dw 0xE81A ; - .dw 0x7ABB ; - .dw 0xE81B ; - .dw 0x8927 ; - .dw 0xE81C ; - .dw 0x2343 ; - .dw 0xE81D ; - .dw 0x308F ; - .dw 0xE81E ; - .dw 0x718F ; - .dw 0xE81F ; - .dw 0xC549 ; - .dw 0xE820 ; - .dw 0x2CD3 ; - .dw 0xE821 ; - .dw 0x81D9 ; - .dw 0xE822 ; - .dw 0xD76B ; - .dw 0xE823 ; - .dw 0xB735 ; - .dw 0xE824 ; - .dw 0x4EBB ; - .dw 0xE825 ; - .dw 0x6223 ; - .dw 0xE826 ; - .dw 0x15EB ; - .dw 0xE827 ; - .dw 0xB19F ; - .dw 0xE828 ; - .dw 0x6E6B ; - .dw 0xE829 ; - .dw 0x7EA3 ; - .dw 0xE82A ; - .dw 0xF2A7 ; - .dw 0xE82B ; - .dw 0xA8E1 ; - .dw 0xE82C ; - .dw 0x14ED ; - .dw 0xE82D ; - .dw 0x2BA5 ; - .dw 0xE82E ; - .dw 0xDD5 ; - .dw 0xE82F ; - .dw 0x69AD ; - .dw 0xE830 ; - .dw 0xCB47 ; - .dw 0xE831 ; - .dw 0x85F7 ; - .dw 0xE832 ; - .dw 0xB25D ; - .dw 0xE833 ; - .dw 0x8351 ; - .dw 0xE834 ; - .dw 0xE445 ; - .dw 0xE835 ; - .dw 0x33E5 ; - .dw 0xE836 ; - .dw 0x8F6B ; - .dw 0xE837 ; - .dw 0x9D5B ; - .dw 0xE838 ; - .dw 0xBE1 ; - .dw 0xE839 ; - .dw 0x3DB9 ; - .dw 0xE83A ; - .dw 0x7391 ; - .dw 0xE83B ; - .dw 0x70E5 ; - .dw 0xE83C ; - .dw 0x7409 ; - .dw 0xE83D ; - .dw 0xF5A9 ; - .dw 0xE83E ; - .dw 0xA15B ; - .dw 0xE83F ; - .dw 0x1D3F ; - .dw 0xE840 ; - .dw 0xF709 ; - .dw 0xE841 ; - .dw 0x6751 ; - .dw 0xE842 ; - .dw 0xD565 ; - .dw 0xE843 ; - .dw 0x1035 ; - .dw 0xE844 ; - .dw 0x755 ; - .dw 0xE845 ; - .dw 0x46AD ; - .dw 0xE846 ; - .dw 0x95F3 ; - .dw 0xE847 ; - .dw 0x39B3 ; - .dw 0xE848 ; - .dw 0xC4EB ; - .dw 0xE849 ; - .dw 0xD693 ; - .dw 0xE84A ; - .dw 0xE40F ; - .dw 0xE84B ; - .dw 0xC30F ; - .dw 0xE84C ; - .dw 0x101F ; - .dw 0xE84D ; - .dw 0xBEA7 ; - .dw 0xE84E ; - .dw 0xE617 ; - .dw 0xE84F ; - .dw 0x1BD ; - .dw 0xE850 ; - .dw 0xF203 ; - .dw 0xE851 ; - .dw 0x48D5 ; - .dw 0xE852 ; - .dw 0xA3DD ; - .dw 0xE853 ; - .dw 0xDD7F ; - .dw 0xE854 ; - .dw 0x3233 ; - .dw 0xE855 ; - .dw 0xFE45 ; - .dw 0xE856 ; - .dw 0x6C3D ; - .dw 0xE857 ; - .dw 0x6225 ; - .dw 0xE858 ; - .dw 0x722F ; - .dw 0xE859 ; - .dw 0x1BDD ; - .dw 0xE85A ; - .dw 0xFC35 ; - .dw 0xE85B ; - .dw 0xB4C1 ; - .dw 0xE85C ; - .dw 0xA635 ; - .dw 0xE85D ; - .dw 0xD62D ; - .dw 0xE85E ; - .dw 0xFF7D ; - .dw 0xE85F ; - .dw 0x2463 ; - .dw 0xE860 ; - .dw 0x439B ; - .dw 0xE861 ; - .dw 0xE4EF ; - .dw 0xE862 ; - .dw 0x299 ; - .dw 0xE863 ; - .dw 0x8E4F ; - .dw 0xE864 ; - .dw 0xFCA1 ; - .dw 0xE865 ; - .dw 0x4DFD ; - .dw 0xE866 ; - .dw 0x6E7D ; - .dw 0xE867 ; - .dw 0xCDAF ; - .dw 0xE868 ; - .dw 0x61D1 ; - .dw 0xE869 ; - .dw 0xE7C7 ; - .dw 0xE86A ; - .dw 0xA59D ; - .dw 0xE86B ; - .dw 0x6ED7 ; - .dw 0xE86C ; - .dw 0x40CF ; - .dw 0xE86D ; - .dw 0x8B4B ; - .dw 0xE86E ; - .dw 0xDA83 ; - .dw 0xE86F ; - .dw 0x5DF1 ; - .dw 0xE870 ; - .dw 0x18B5 ; - .dw 0xE871 ; - .dw 0x6D91 ; - .dw 0xE872 ; - .dw 0xB7EF ; - .dw 0xE873 ; - .dw 0xC941 ; - .dw 0xE874 ; - .dw 0x7BE9 ; - .dw 0xE875 ; - .dw 0x98A3 ; - .dw 0xE876 ; - .dw 0x7269 ; - .dw 0xE877 ; - .dw 0xEECF ; - .dw 0xE878 ; - .dw 0xB77B ; - .dw 0xE879 ; - .dw 0xFBFD ; - .dw 0xE87A ; - .dw 0x5B59 ; - .dw 0xE87B ; - .dw 0xDAD ; - .dw 0xE87C ; - .dw 0x97F5 ; - .dw 0xE87D ; - .dw 0xC8B ; - .dw 0xE87E ; - .dw 0x8DA1 ; - .dw 0xE87F ; - .dw 0x32A5 ; - .dw 0xE880 ; - .dw 0xA3B7 ; - .dw 0xE881 ; - .dw 0x6C27 ; - .dw 0xE882 ; - .dw 0xCBB7 ; - .dw 0xE883 ; - .dw 0x1873 ; - .dw 0xE884 ; - .dw 0xA2CF ; - .dw 0xE885 ; - .dw 0x9083 ; - .dw 0xE886 ; - .dw 0x2737 ; - .dw 0xE887 ; - .dw 0xD383 ; - .dw 0xE888 ; - .dw 0xCC51 ; - .dw 0xE889 ; - .dw 0xE1AD ; - .dw 0xE88A ; - .dw 0x8A01 ; - .dw 0xE88B ; - .dw 0x8123 ; - .dw 0xE88C ; - .dw 0x712D ; - .dw 0xE88D ; - .dw 0x47FF ; - .dw 0xE88E ; - .dw 0xB8CD ; - .dw 0xE88F ; - .dw 0xB23B ; - .dw 0xE890 ; - .dw 0x7C89 ; - .dw 0xE891 ; - .dw 0xA19F ; - .dw 0xE892 ; - .dw 0xE745 ; - .dw 0xE893 ; - .dw 0xC985 ; - .dw 0xE894 ; - .dw 0xA199 ; - .dw 0xE895 ; - .dw 0x176F ; - .dw 0xE896 ; - .dw 0x759D ; - .dw 0xE897 ; - .dw 0x54B ; - .dw 0xE898 ; - .dw 0x8EF7 ; - .dw 0xE899 ; - .dw 0xC987 ; - .dw 0xE89A ; - .dw 0xEFAB ; - .dw 0xE89B ; - .dw 0x6C97 ; - .dw 0xE89C ; - .dw 0xFF7B ; - .dw 0xE89D ; - .dw 0xCB35 ; - .dw 0xE89E ; - .dw 0xE57B ; - .dw 0xE89F ; - .dw 0x57F1 ; - .dw 0xE8A0 ; - .dw 0x8F ; - .dw 0xE8A1 ; - .dw 0xE667 ; - .dw 0xE8A2 ; - .dw 0xB56F ; - .dw 0xE8A3 ; - .dw 0xCD93 ; - .dw 0xE8A4 ; - .dw 0x460F ; - .dw 0xE8A5 ; - .dw 0x1EAF ; - .dw 0xE8A6 ; - .dw 0xDFD1 ; - .dw 0xE8A7 ; - .dw 0x6921 ; - .dw 0xE8A8 ; - .dw 0xE397 ; - .dw 0xE8A9 ; - .dw 0x6BB9 ; - .dw 0xE8AA ; - .dw 0xFBEB ; - .dw 0xE8AB ; - .dw 0x6E7 ; - .dw 0xE8AC ; - .dw 0x4367 ; - .dw 0xE8AD ; - .dw 0xA337 ; - .dw 0xE8AE ; - .dw 0xE6A3 ; - .dw 0xE8AF ; - .dw 0xEA89 ; - .dw 0xE8B0 ; - .dw 0xB2B1 ; - .dw 0xE8B1 ; - .dw 0xA6D ; - .dw 0xE8B2 ; - .dw 0x428D ; - .dw 0xE8B3 ; - .dw 0x993D ; - .dw 0xE8B4 ; - .dw 0x5B73 ; - .dw 0xE8B5 ; - .dw 0x8717 ; - .dw 0xE8B6 ; - .dw 0xE189 ; - .dw 0xE8B7 ; - .dw 0x1F87 ; - .dw 0xE8B8 ; - .dw 0x3D3 ; - .dw 0xE8B9 ; - .dw 0xE7ED ; - .dw 0xE8BA ; - .dw 0x2FDB ; - .dw 0xE8BB ; - .dw 0xFA71 ; - .dw 0xE8BC ; - .dw 0x6AF7 ; - .dw 0xE8BD ; - .dw 0x3C97 ; - .dw 0xE8BE ; - .dw 0x38B9 ; - .dw 0xE8BF ; - .dw 0x5C3B ; - .dw 0xE8C0 ; - .dw 0x9B53 ; - .dw 0xE8C1 ; - .dw 0xB51F ; - .dw 0xE8C2 ; - .dw 0x5C73 ; - .dw 0xE8C3 ; - .dw 0x49D ; - .dw 0xE8C4 ; - .dw 0xA8F ; - .dw 0xE8C5 ; - .dw 0xF3 ; - .dw 0xE8C6 ; - .dw 0x4FFB ; - .dw 0xE8C7 ; - .dw 0x6479 ; - .dw 0xE8C8 ; - .dw 0xDED5 ; - .dw 0xE8C9 ; - .dw 0xA557 ; - .dw 0xE8CA ; - .dw 0x7E0D ; - .dw 0xE8CB ; - .dw 0x4513 ; - .dw 0xE8CC ; - .dw 0x31AF ; - .dw 0xE8CD ; - .dw 0x4361 ; - .dw 0xE8CE ; - .dw 0x61B5 ; - .dw 0xE8CF ; - .dw 0xAACB ; - .dw 0xE8D0 ; - .dw 0xA85B ; - .dw 0xE8D1 ; - .dw 0x4569 ; - .dw 0xE8D2 ; - .dw 0xF277 ; - .dw 0xE8D3 ; - .dw 0x2B57 ; - .dw 0xE8D4 ; - .dw 0x39A5 ; - .dw 0xE8D5 ; - .dw 0xEC0F ; - .dw 0xE8D6 ; - .dw 0xB9DF ; - .dw 0xE8D7 ; - .dw 0x6F75 ; - .dw 0xE8D8 ; - .dw 0x793F ; - .dw 0xE8D9 ; - .dw 0x32A1 ; - .dw 0xE8DA ; - .dw 0xAA99 ; - .dw 0xE8DB ; - .dw 0x1829 ; - .dw 0xE8DC ; - .dw 0x4097 ; - .dw 0xE8DD ; - .dw 0x8323 ; - .dw 0xE8DE ; - .dw 0x510B ; - .dw 0xE8DF ; - .dw 0xBF73 ; - .dw 0xE8E0 ; - .dw 0xD31 ; - .dw 0xE8E1 ; - .dw 0xB1BD ; - .dw 0xE8E2 ; - .dw 0x756F ; - .dw 0xE8E3 ; - .dw 0x4C83 ; - .dw 0xE8E4 ; - .dw 0xEC7F ; - .dw 0xE8E5 ; - .dw 0x37BB ; - .dw 0xE8E6 ; - .dw 0xC767 ; - .dw 0xE8E7 ; - .dw 0x5379 ; - .dw 0xE8E8 ; - .dw 0x4D39 ; - .dw 0xE8E9 ; - .dw 0x25F9 ; - .dw 0xE8EA ; - .dw 0xAB13 ; - .dw 0xE8EB ; - .dw 0xB895 ; - .dw 0xE8EC ; - .dw 0x8E35 ; - .dw 0xE8ED ; - .dw 0xC6EB ; - .dw 0xE8EE ; - .dw 0xBFB3 ; - .dw 0xE8EF ; - .dw 0x4EF3 ; - .dw 0xE8F0 ; - .dw 0xA2B9 ; - .dw 0xE8F1 ; - .dw 0x6807 ; - .dw 0xE8F2 ; - .dw 0x37B3 ; - .dw 0xE8F3 ; - .dw 0xAAC3 ; - .dw 0xE8F4 ; - .dw 0xA461 ; - .dw 0xE8F5 ; - .dw 0x42C3 ; - .dw 0xE8F6 ; - .dw 0x9A4B ; - .dw 0xE8F7 ; - .dw 0xDF03 ; - .dw 0xE8F8 ; - .dw 0xAA6B ; - .dw 0xE8F9 ; - .dw 0xFD0F ; - .dw 0xE8FA ; - .dw 0x695 ; - .dw 0xE8FB ; - .dw 0x5EB1 ; - .dw 0xE8FC ; - .dw 0xBE8D ; - .dw 0xE8FD ; - .dw 0xB949 ; - .dw 0xE8FE ; - .dw 0x9023 ; - .dw 0xE8FF ; - .dw 0xB987 ; - .dw 0xE900 ; - .dw 0x475B ; - .dw 0xE901 ; - .dw 0x2DB5 ; - .dw 0xE902 ; - .dw 0xCD17 ; - .dw 0xE903 ; - .dw 0x6C33 ; - .dw 0xE904 ; - .dw 0xC013 ; - .dw 0xE905 ; - .dw 0xBB77 ; - .dw 0xE906 ; - .dw 0x2DC3 ; - .dw 0xE907 ; - .dw 0x7C11 ; - .dw 0xE908 ; - .dw 0x15F7 ; - .dw 0xE909 ; - .dw 0xFD0F ; - .dw 0xE90A ; - .dw 0x35B1 ; - .dw 0xE90B ; - .dw 0x165D ; - .dw 0xE90C ; - .dw 0x8327 ; - .dw 0xE90D ; - .dw 0xC449 ; - .dw 0xE90E ; - .dw 0x2E4F ; - .dw 0xE90F ; - .dw 0xEAEF ; - .dw 0xE910 ; - .dw 0x3EFB ; - .dw 0xE911 ; - .dw 0xFFB3 ; - .dw 0xE912 ; - .dw 0x6AF3 ; - .dw 0xE913 ; - .dw 0x7A73 ; - .dw 0xE914 ; - .dw 0xDBD7 ; - .dw 0xE915 ; - .dw 0x7FA7 ; - .dw 0xE916 ; - .dw 0xB681 ; - .dw 0xE917 ; - .dw 0x1023 ; - .dw 0xE918 ; - .dw 0xAA85 ; - .dw 0xE919 ; - .dw 0x12A9 ; - .dw 0xE91A ; - .dw 0x27F ; - .dw 0xE91B ; - .dw 0x9EF7 ; - .dw 0xE91C ; - .dw 0xFB09 ; - .dw 0xE91D ; - .dw 0xF179 ; - .dw 0xE91E ; - .dw 0xEFAD ; - .dw 0xE91F ; - .dw 0x3A67 ; - .dw 0xE920 ; - .dw 0x9301 ; - .dw 0xE921 ; - .dw 0xF273 ; - .dw 0xE922 ; - .dw 0x4819 ; - .dw 0xE923 ; - .dw 0x629F ; - .dw 0xE924 ; - .dw 0x3177 ; - .dw 0xE925 ; - .dw 0x7C9B ; - .dw 0xE926 ; - .dw 0x2BD ; - .dw 0xE927 ; - .dw 0xDC33 ; - .dw 0xE928 ; - .dw 0x783B ; - .dw 0xE929 ; - .dw 0xB20B ; - .dw 0xE92A ; - .dw 0xE895 ; - .dw 0xE92B ; - .dw 0x4B5D ; - .dw 0xE92C ; - .dw 0x12B7 ; - .dw 0xE92D ; - .dw 0xC9E7 ; - .dw 0xE92E ; - .dw 0x7335 ; - .dw 0xE92F ; - .dw 0x4AB1 ; - .dw 0xE930 ; - .dw 0x7251 ; - .dw 0xE931 ; - .dw 0x11E1 ; - .dw 0xE932 ; - .dw 0xFCE3 ; - .dw 0xE933 ; - .dw 0x3557 ; - .dw 0xE934 ; - .dw 0xF837 ; - .dw 0xE935 ; - .dw 0x8F27 ; - .dw 0xE936 ; - .dw 0xDA2F ; - .dw 0xE937 ; - .dw 0x5CC3 ; - .dw 0xE938 ; - .dw 0xE4BD ; - .dw 0xE939 ; - .dw 0xB6DF ; - .dw 0xE93A ; - .dw 0x7509 ; - .dw 0xE93B ; - .dw 0xE1EB ; - .dw 0xE93C ; - .dw 0xE439 ; - .dw 0xE93D ; - .dw 0x3621 ; - .dw 0xE93E ; - .dw 0x15D ; - .dw 0xE93F ; - .dw 0xEA05 ; - .dw 0xE940 ; - .dw 0x9151 ; - .dw 0xE941 ; - .dw 0x4169 ; - .dw 0xE942 ; - .dw 0xE325 ; - .dw 0xE943 ; - .dw 0x66B5 ; - .dw 0xE944 ; - .dw 0xC4DD ; - .dw 0xE945 ; - .dw 0x6395 ; - .dw 0xE946 ; - .dw 0x5E09 ; - .dw 0xE947 ; - .dw 0x29CD ; - .dw 0xE948 ; - .dw 0xB35 ; - .dw 0xE949 ; - .dw 0x4459 ; - .dw 0xE94A ; - .dw 0xA671 ; - .dw 0xE94B ; - .dw 0x7C83 ; - .dw 0xE94C ; - .dw 0x1715 ; - .dw 0xE94D ; - .dw 0x5E37 ; - .dw 0xE94E ; - .dw 0xEC19 ; - .dw 0xE94F ; - .dw 0xF227 ; - .dw 0xE950 ; - .dw 0x89E9 ; - .dw 0xE951 ; - .dw 0x1BFD ; - .dw 0xE952 ; - .dw 0x7637 ; - .dw 0xE953 ; - .dw 0xAE5B ; - .dw 0xE954 ; - .dw 0xE9AF ; - .dw 0xE955 ; - .dw 0x55B5 ; - .dw 0xE956 ; - .dw 0x6905 ; - .dw 0xE957 ; - .dw 0xD6D3 ; - .dw 0xE958 ; - .dw 0x1C47 ; - .dw 0xE959 ; - .dw 0xA523 ; - .dw 0xE95A ; - .dw 0x4CE1 ; - .dw 0xE95B ; - .dw 0x687F ; - .dw 0xE95C ; - .dw 0x404F ; - .dw 0xE95D ; - .dw 0x89B5 ; - .dw 0xE95E ; - .dw 0xEEE1 ; - .dw 0xE95F ; - .dw 0x2851 ; - .dw 0xE960 ; - .dw 0x3B7D ; - .dw 0xE961 ; - .dw 0xD409 ; - .dw 0xE962 ; - .dw 0xB2ED ; - .dw 0xE963 ; - .dw 0xE767 ; - .dw 0xE964 ; - .dw 0xD673 ; - .dw 0xE965 ; - .dw 0x50D5 ; - .dw 0xE966 ; - .dw 0xEF57 ; - .dw 0xE967 ; - .dw 0xD2D1 ; - .dw 0xE968 ; - .dw 0xBE17 ; - .dw 0xE969 ; - .dw 0x2B6B ; - .dw 0xE96A ; - .dw 0x69F1 ; - .dw 0xE96B ; - .dw 0x6C1 ; - .dw 0xE96C ; - .dw 0x426F ; - .dw 0xE96D ; - .dw 0xFFA9 ; - .dw 0xE96E ; - .dw 0x8EA9 ; - .dw 0xE96F ; - .dw 0x1D41 ; - .dw 0xE970 ; - .dw 0x2AF5 ; - .dw 0xE971 ; - .dw 0x1379 ; - .dw 0xE972 ; - .dw 0x779D ; - .dw 0xE973 ; - .dw 0xF075 ; - .dw 0xE974 ; - .dw 0x7871 ; - .dw 0xE975 ; - .dw 0xAFC1 ; - .dw 0xE976 ; - .dw 0x5EB3 ; - .dw 0xE977 ; - .dw 0x4845 ; - .dw 0xE978 ; - .dw 0x6C4F ; - .dw 0xE979 ; - .dw 0x10E1 ; - .dw 0xE97A ; - .dw 0x90B7 ; - .dw 0xE97B ; - .dw 0xABA3 ; - .dw 0xE97C ; - .dw 0xAD7B ; - .dw 0xE97D ; - .dw 0xE6A3 ; - .dw 0xE97E ; - .dw 0x79E9 ; - .dw 0xE97F ; - .dw 0xD37 ; - .dw 0xE980 ; - .dw 0xE2B5 ; - .dw 0xE981 ; - .dw 0xDBBF ; - .dw 0xE982 ; - .dw 0xE41D ; - .dw 0xE983 ; - .dw 0x8BA3 ; - .dw 0xE984 ; - .dw 0x9A6B ; - .dw 0xE985 ; - .dw 0x1CCB ; - .dw 0xE986 ; - .dw 0xFE53 ; - .dw 0xE987 ; - .dw 0xFD2D ; - .dw 0xE988 ; - .dw 0xD811 ; - .dw 0xE989 ; - .dw 0x56B1 ; - .dw 0xE98A ; - .dw 0x45C9 ; - .dw 0xE98B ; - .dw 0x7F05 ; - .dw 0xE98C ; - .dw 0x1EF7 ; - .dw 0xE98D ; - .dw 0x24AF ; - .dw 0xE98E ; - .dw 0xE895 ; - .dw 0xE98F ; - .dw 0xBFF1 ; - .dw 0xE990 ; - .dw 0x52A5 ; - .dw 0xE991 ; - .dw 0x65C7 ; - .dw 0xE992 ; - .dw 0xB9C5 ; - .dw 0xE993 ; - .dw 0x3E8F ; - .dw 0xE994 ; - .dw 0x44AB ; - .dw 0xE995 ; - .dw 0x71BD ; - .dw 0xE996 ; - .dw 0x4EEB ; - .dw 0xE997 ; - .dw 0x3307 ; - .dw 0xE998 ; - .dw 0x4807 ; - .dw 0xE999 ; - .dw 0xA58B ; - .dw 0xE99A ; - .dw 0x5F3B ; - .dw 0xE99B ; - .dw 0x5C45 ; - .dw 0xE99C ; - .dw 0xA1EB ; - .dw 0xE99D ; - .dw 0x3F5B ; - .dw 0xE99E ; - .dw 0xFC25 ; - .dw 0xE99F ; - .dw 0x68AD ; - .dw 0xE9A0 ; - .dw 0x3029 ; - .dw 0xE9A1 ; - .dw 0x1FD ; - .dw 0xE9A2 ; - .dw 0xBB69 ; - .dw 0xE9A3 ; - .dw 0x3259 ; - .dw 0xE9A4 ; - .dw 0x1CF5 ; - .dw 0xE9A5 ; - .dw 0x97E5 ; - .dw 0xE9A6 ; - .dw 0x6AB1 ; - .dw 0xE9A7 ; - .dw 0x86D3 ; - .dw 0xE9A8 ; - .dw 0xF853 ; - .dw 0xE9A9 ; - .dw 0x2D9B ; - .dw 0xE9AA ; - .dw 0x64A5 ; - .dw 0xE9AB ; - .dw 0xB23F ; - .dw 0xE9AC ; - .dw 0xEDD ; - .dw 0xE9AD ; - .dw 0x3BB5 ; - .dw 0xE9AE ; - .dw 0x1F8F ; - .dw 0xE9AF ; - .dw 0x8627 ; - .dw 0xE9B0 ; - .dw 0x5627 ; - .dw 0xE9B1 ; - .dw 0xF853 ; - .dw 0xE9B2 ; - .dw 0xD5F ; - .dw 0xE9B3 ; - .dw 0x139F ; - .dw 0xE9B4 ; - .dw 0xC691 ; - .dw 0xE9B5 ; - .dw 0x6815 ; - .dw 0xE9B6 ; - .dw 0x655B ; - .dw 0xE9B7 ; - .dw 0xD10B ; - .dw 0xE9B8 ; - .dw 0x7A9D ; - .dw 0xE9B9 ; - .dw 0x868F ; - .dw 0xE9BA ; - .dw 0xEF1F ; - .dw 0xE9BB ; - .dw 0x6355 ; - .dw 0xE9BC ; - .dw 0x6BD3 ; - .dw 0xE9BD ; - .dw 0x7E4B ; - .dw 0xE9BE ; - .dw 0x6747 ; - .dw 0xE9BF ; - .dw 0xC29D ; - .dw 0xE9C0 ; - .dw 0x2507 ; - .dw 0xE9C1 ; - .dw 0x6833 ; - .dw 0xE9C2 ; - .dw 0x957F ; - .dw 0xE9C3 ; - .dw 0xF27B ; - .dw 0xE9C4 ; - .dw 0x4241 ; - .dw 0xE9C5 ; - .dw 0x8A97 ; - .dw 0xE9C6 ; - .dw 0xAC1D ; - .dw 0xE9C7 ; - .dw 0x5B1 ; - .dw 0xE9C8 ; - .dw 0x160B ; - .dw 0xE9C9 ; - .dw 0x8F99 ; - .dw 0xE9CA ; - .dw 0x939 ; - .dw 0xE9CB ; - .dw 0xA561 ; - .dw 0xE9CC ; - .dw 0x4C51 ; - .dw 0xE9CD ; - .dw 0xAB2D ; - .dw 0xE9CE ; - .dw 0xF143 ; - .dw 0xE9CF ; - .dw 0xD3CF ; - .dw 0xE9D0 ; - .dw 0xE2AD ; - .dw 0xE9D1 ; - .dw 0x288F ; - .dw 0xE9D2 ; - .dw 0x5B1D ; - .dw 0xE9D3 ; - .dw 0x228F ; - .dw 0xE9D4 ; - .dw 0x4E4D ; - .dw 0xE9D5 ; - .dw 0x573B ; - .dw 0xE9D6 ; - .dw 0x65B1 ; - .dw 0xE9D7 ; - .dw 0x143F ; - .dw 0xE9D8 ; - .dw 0x2743 ; - .dw 0xE9D9 ; - .dw 0x4F61 ; - .dw 0xE9DA ; - .dw 0x8F0F ; - .dw 0xE9DB ; - .dw 0xE1C5 ; - .dw 0xE9DC ; - .dw 0x315D ; - .dw 0xE9DD ; - .dw 0x85E7 ; - .dw 0xE9DE ; - .dw 0x44FB ; - .dw 0xE9DF ; - .dw 0x5AFB ; - .dw 0xE9E0 ; - .dw 0x1A81 ; - .dw 0xE9E1 ; - .dw 0xA7D3 ; - .dw 0xE9E2 ; - .dw 0xE70F ; - .dw 0xE9E3 ; - .dw 0x1AF7 ; - .dw 0xE9E4 ; - .dw 0xC67D ; - .dw 0xE9E5 ; - .dw 0xB54D ; - .dw 0xE9E6 ; - .dw 0xD24B ; - .dw 0xE9E7 ; - .dw 0xC7B7 ; - .dw 0xE9E8 ; - .dw 0x806B ; - .dw 0xE9E9 ; - .dw 0xD419 ; - .dw 0xE9EA ; - .dw 0x8E35 ; - .dw 0xE9EB ; - .dw 0x955B ; - .dw 0xE9EC ; - .dw 0xE981 ; - .dw 0xE9ED ; - .dw 0xD187 ; - .dw 0xE9EE ; - .dw 0xB365 ; - .dw 0xE9EF ; - .dw 0xC4DF ; - .dw 0xE9F0 ; - .dw 0xFD67 ; - .dw 0xE9F1 ; - .dw 0xCBEB ; - .dw 0xE9F2 ; - .dw 0xA3AD ; - .dw 0xE9F3 ; - .dw 0x5653 ; - .dw 0xE9F4 ; - .dw 0x415 ; - .dw 0xE9F5 ; - .dw 0xFB9F ; - .dw 0xE9F6 ; - .dw 0xABA3 ; - .dw 0xE9F7 ; - .dw 0xA695 ; - .dw 0xE9F8 ; - .dw 0xC929 ; - .dw 0xE9F9 ; - .dw 0x136F ; - .dw 0xE9FA ; - .dw 0xA5BF ; - .dw 0xE9FB ; - .dw 0x3083 ; - .dw 0xE9FC ; - .dw 0xF0BF ; - .dw 0xE9FD ; - .dw 0x309B ; - .dw 0xE9FE ; - .dw 0xB6F5 ; - .dw 0xE9FF ; - .dw 0x29B7 ; - .dw 0xEA00 ; - .dw 0xC1C5 ; - .dw 0xEA01 ; - .dw 0xD249 ; - .dw 0xEA02 ; - .dw 0x3CCB ; - .dw 0xEA03 ; - .dw 0x32BF ; - .dw 0xEA04 ; - .dw 0x3DDB ; - .dw 0xEA05 ; - .dw 0xD07B ; - .dw 0xEA06 ; - .dw 0x84EB ; - .dw 0xEA07 ; - .dw 0xD2D7 ; - .dw 0xEA08 ; - .dw 0xDEA3 ; - .dw 0xEA09 ; - .dw 0xCA8F ; - .dw 0xEA0A ; - .dw 0x6645 ; - .dw 0xEA0B ; - .dw 0xF71B ; - .dw 0xEA0C ; - .dw 0xD09F ; - .dw 0xEA0D ; - .dw 0x533 ; - .dw 0xEA0E ; - .dw 0x53A3 ; - .dw 0xEA0F ; - .dw 0x2D41 ; - .dw 0xEA10 ; - .dw 0x383 ; - .dw 0xEA11 ; - .dw 0x2FD7 ; - .dw 0xEA12 ; - .dw 0xFFBF ; - .dw 0xEA13 ; - .dw 0xD1DB ; - .dw 0xEA14 ; - .dw 0xE815 ; - .dw 0xEA15 ; - .dw 0x9B1 ; - .dw 0xEA16 ; - .dw 0x2ADB ; - .dw 0xEA17 ; - .dw 0xE9FB ; - .dw 0xEA18 ; - .dw 0x337F ; - .dw 0xEA19 ; - .dw 0x5E29 ; - .dw 0xEA1A ; - .dw 0xB1DD ; - .dw 0xEA1B ; - .dw 0xE07F ; - .dw 0xEA1C ; - .dw 0x8025 ; - .dw 0xEA1D ; - .dw 0x50DB ; - .dw 0xEA1E ; - .dw 0x76E3 ; - .dw 0xEA1F ; - .dw 0xDEBF ; - .dw 0xEA20 ; - .dw 0x2407 ; - .dw 0xEA21 ; - .dw 0x7107 ; - .dw 0xEA22 ; - .dw 0x3B5F ; - .dw 0xEA23 ; - .dw 0xF8C1 ; - .dw 0xEA24 ; - .dw 0x148B ; - .dw 0xEA25 ; - .dw 0x8C8D ; - .dw 0xEA26 ; - .dw 0x3A9 ; - .dw 0xEA27 ; - .dw 0xE4FF ; - .dw 0xEA28 ; - .dw 0x2FE3 ; - .dw 0xEA29 ; - .dw 0xBA69 ; - .dw 0xEA2A ; - .dw 0x1C1D ; - .dw 0xEA2B ; - .dw 0x7791 ; - .dw 0xEA2C ; - .dw 0xC3D9 ; - .dw 0xEA2D ; - .dw 0x94A1 ; - .dw 0xEA2E ; - .dw 0x57AD ; - .dw 0xEA2F ; - .dw 0x98EB ; - .dw 0xEA30 ; - .dw 0xAA33 ; - .dw 0xEA31 ; - .dw 0x19C3 ; - .dw 0xEA32 ; - .dw 0xA003 ; - .dw 0xEA33 ; - .dw 0xF015 ; - .dw 0xEA34 ; - .dw 0xD27F ; - .dw 0xEA35 ; - .dw 0x2DE1 ; - .dw 0xEA36 ; - .dw 0x6F0B ; - .dw 0xEA37 ; - .dw 0xF863 ; - .dw 0xEA38 ; - .dw 0x9173 ; - .dw 0xEA39 ; - .dw 0x32FD ; - .dw 0xEA3A ; - .dw 0x4A19 ; - .dw 0xEA3B ; - .dw 0xBAAB ; - .dw 0xEA3C ; - .dw 0x8DC1 ; - .dw 0xEA3D ; - .dw 0xB113 ; - .dw 0xEA3E ; - .dw 0xD677 ; - .dw 0xEA3F ; - .dw 0xE203 ; - .dw 0xEA40 ; - .dw 0xA271 ; - .dw 0xEA41 ; - .dw 0x857B ; - .dw 0xEA42 ; - .dw 0x9F7F ; - .dw 0xEA43 ; - .dw 0x63EF ; - .dw 0xEA44 ; - .dw 0x8EBB ; - .dw 0xEA45 ; - .dw 0x91F7 ; - .dw 0xEA46 ; - .dw 0x2639 ; - .dw 0xEA47 ; - .dw 0x7421 ; - .dw 0xEA48 ; - .dw 0xCB59 ; - .dw 0xEA49 ; - .dw 0x6317 ; - .dw 0xEA4A ; - .dw 0x5269 ; - .dw 0xEA4B ; - .dw 0xFBAF ; - .dw 0xEA4C ; - .dw 0x5D63 ; - .dw 0xEA4D ; - .dw 0xC63F ; - .dw 0xEA4E ; - .dw 0xDD33 ; - .dw 0xEA4F ; - .dw 0x4BC7 ; - .dw 0xEA50 ; - .dw 0xFEA7 ; - .dw 0xEA51 ; - .dw 0xC71F ; - .dw 0xEA52 ; - .dw 0xCD29 ; - .dw 0xEA53 ; - .dw 0x43F1 ; - .dw 0xEA54 ; - .dw 0x7383 ; - .dw 0xEA55 ; - .dw 0xC9D ; - .dw 0xEA56 ; - .dw 0x9BE5 ; - .dw 0xEA57 ; - .dw 0xA3BB ; - .dw 0xEA58 ; - .dw 0x6637 ; - .dw 0xEA59 ; - .dw 0xD5F ; - .dw 0xEA5A ; - .dw 0x1D23 ; - .dw 0xEA5B ; - .dw 0xBFF7 ; - .dw 0xEA5C ; - .dw 0x9FC3 ; - .dw 0xEA5D ; - .dw 0x13B5 ; - .dw 0xEA5E ; - .dw 0xBF5D ; - .dw 0xEA5F ; - .dw 0x5375 ; - .dw 0xEA60 ; - .dw 0xF639 ; - .dw 0xEA61 ; - .dw 0x8919 ; - .dw 0xEA62 ; - .dw 0x3DD9 ; - .dw 0xEA63 ; - .dw 0xA337 ; - .dw 0xEA64 ; - .dw 0xC89D ; - .dw 0xEA65 ; - .dw 0x8125 ; - .dw 0xEA66 ; - .dw 0x5C47 ; - .dw 0xEA67 ; - .dw 0xAE2B ; - .dw 0xEA68 ; - .dw 0x6035 ; - .dw 0xEA69 ; - .dw 0xFC07 ; - .dw 0xEA6A ; - .dw 0xC3DD ; - .dw 0xEA6B ; - .dw 0xA063 ; - .dw 0xEA6C ; - .dw 0xF69 ; - .dw 0xEA6D ; - .dw 0xD881 ; - .dw 0xEA6E ; - .dw 0x99E7 ; - .dw 0xEA6F ; - .dw 0x41C9 ; - .dw 0xEA70 ; - .dw 0x660F ; - .dw 0xEA71 ; - .dw 0xED5B ; - .dw 0xEA72 ; - .dw 0xE7E3 ; - .dw 0xEA73 ; - .dw 0x9861 ; - .dw 0xEA74 ; - .dw 0x534F ; - .dw 0xEA75 ; - .dw 0x4259 ; - .dw 0xEA76 ; - .dw 0x6D17 ; - .dw 0xEA77 ; - .dw 0x75F3 ; - .dw 0xEA78 ; - .dw 0x8CFB ; - .dw 0xEA79 ; - .dw 0xE0BD ; - .dw 0xEA7A ; - .dw 0xF1AD ; - .dw 0xEA7B ; - .dw 0x2951 ; - .dw 0xEA7C ; - .dw 0x1459 ; - .dw 0xEA7D ; - .dw 0x3331 ; - .dw 0xEA7E ; - .dw 0xB349 ; - .dw 0xEA7F ; - .dw 0xB03 ; - .dw 0xEA80 ; - .dw 0x308B ; - .dw 0xEA81 ; - .dw 0x6D4F ; - .dw 0xEA82 ; - .dw 0x31D ; - .dw 0xEA83 ; - .dw 0x1D8B ; - .dw 0xEA84 ; - .dw 0xB661 ; - .dw 0xEA85 ; - .dw 0xF289 ; - .dw 0xEA86 ; - .dw 0xAD87 ; - .dw 0xEA87 ; - .dw 0x790F ; - .dw 0xEA88 ; - .dw 0xF5AB ; - .dw 0xEA89 ; - .dw 0x34AD ; - .dw 0xEA8A ; - .dw 0x4327 ; - .dw 0xEA8B ; - .dw 0xBA9D ; - .dw 0xEA8C ; - .dw 0x241B ; - .dw 0xEA8D ; - .dw 0x1D5 ; - .dw 0xEA8E ; - .dw 0xDB77 ; - .dw 0xEA8F ; - .dw 0x2EE1 ; - .dw 0xEA90 ; - .dw 0x9D99 ; - .dw 0xEA91 ; - .dw 0xB9E5 ; - .dw 0xEA92 ; - .dw 0x68DD ; - .dw 0xEA93 ; - .dw 0xF053 ; - .dw 0xEA94 ; - .dw 0xD215 ; - .dw 0xEA95 ; - .dw 0x6383 ; - .dw 0xEA96 ; - .dw 0x3651 ; - .dw 0xEA97 ; - .dw 0xB0FD ; - .dw 0xEA98 ; - .dw 0x38ED ; - .dw 0xEA99 ; - .dw 0x1885 ; - .dw 0xEA9A ; - .dw 0xA665 ; - .dw 0xEA9B ; - .dw 0x67A9 ; - .dw 0xEA9C ; - .dw 0x21B5 ; - .dw 0xEA9D ; - .dw 0xC1F9 ; - .dw 0xEA9E ; - .dw 0xCBE7 ; - .dw 0xEA9F ; - .dw 0x989F ; - .dw 0xEAA0 ; - .dw 0xBA99 ; - .dw 0xEAA1 ; - .dw 0x9B8D ; - .dw 0xEAA2 ; - .dw 0xF3FB ; - .dw 0xEAA3 ; - .dw 0x71D9 ; - .dw 0xEAA4 ; - .dw 0x2435 ; - .dw 0xEAA5 ; - .dw 0x7693 ; - .dw 0xEAA6 ; - .dw 0xB9A7 ; - .dw 0xEAA7 ; - .dw 0x72BB ; - .dw 0xEAA8 ; - .dw 0xEAE7 ; - .dw 0xEAA9 ; - .dw 0x3475 ; - .dw 0xEAAA ; - .dw 0xBAF9 ; - .dw 0xEAAB ; - .dw 0xD74F ; - .dw 0xEAAC ; - .dw 0xBDAB ; - .dw 0xEAAD ; - .dw 0x70A9 ; - .dw 0xEAAE ; - .dw 0x8793 ; - .dw 0xEAAF ; - .dw 0x7EFD ; - .dw 0xEAB0 ; - .dw 0xBA75 ; - .dw 0xEAB1 ; - .dw 0xD231 ; - .dw 0xEAB2 ; - .dw 0xE0CB ; - .dw 0xEAB3 ; - .dw 0x86B9 ; - .dw 0xEAB4 ; - .dw 0x2805 ; - .dw 0xEAB5 ; - .dw 0xFC89 ; - .dw 0xEAB6 ; - .dw 0xE343 ; - .dw 0xEAB7 ; - .dw 0x4EC7 ; - .dw 0xEAB8 ; - .dw 0xF53F ; - .dw 0xEAB9 ; - .dw 0x982B ; - .dw 0xEABA ; - .dw 0x31FB ; - .dw 0xEABB ; - .dw 0x23F1 ; - .dw 0xEABC ; - .dw 0xD607 ; - .dw 0xEABD ; - .dw 0x6A79 ; - .dw 0xEABE ; - .dw 0xBAEB ; - .dw 0xEABF ; - .dw 0x4437 ; - .dw 0xEAC0 ; - .dw 0x5593 ; - .dw 0xEAC1 ; - .dw 0xF541 ; - .dw 0xEAC2 ; - .dw 0x2D23 ; - .dw 0xEAC3 ; - .dw 0x7711 ; - .dw 0xEAC4 ; - .dw 0xB64B ; - .dw 0xEAC5 ; - .dw 0x95B3 ; - .dw 0xEAC6 ; - .dw 0xB859 ; - .dw 0xEAC7 ; - .dw 0xF11F ; - .dw 0xEAC8 ; - .dw 0xF71B ; - .dw 0xEAC9 ; - .dw 0x9AD1 ; - .dw 0xEACA ; - .dw 0x2DFF ; - .dw 0xEACB ; - .dw 0xBB69 ; - .dw 0xEACC ; - .dw 0xD649 ; - .dw 0xEACD ; - .dw 0x4B71 ; - .dw 0xEACE ; - .dw 0x1BEB ; - .dw 0xEACF ; - .dw 0x560D ; - .dw 0xEAD0 ; - .dw 0x29D7 ; - .dw 0xEAD1 ; - .dw 0x53AD ; - .dw 0xEAD2 ; - .dw 0xF85B ; - .dw 0xEAD3 ; - .dw 0xCE81 ; - .dw 0xEAD4 ; - .dw 0x654F ; - .dw 0xEAD5 ; - .dw 0x91DF ; - .dw 0xEAD6 ; - .dw 0xF79D ; - .dw 0xEAD7 ; - .dw 0x143 ; - .dw 0xEAD8 ; - .dw 0xA521 ; - .dw 0xEAD9 ; - .dw 0xBB1B ; - .dw 0xEADA ; - .dw 0xA31F ; - .dw 0xEADB ; - .dw 0x3F17 ; - .dw 0xEADC ; - .dw 0x177D ; - .dw 0xEADD ; - .dw 0xCF23 ; - .dw 0xEADE ; - .dw 0xCA05 ; - .dw 0xEADF ; - .dw 0xDBD ; - .dw 0xEAE0 ; - .dw 0x1AA7 ; - .dw 0xEAE1 ; - .dw 0xD3DF ; - .dw 0xEAE2 ; - .dw 0xE347 ; - .dw 0xEAE3 ; - .dw 0x3C25 ; - .dw 0xEAE4 ; - .dw 0xE8D3 ; - .dw 0xEAE5 ; - .dw 0xD059 ; - .dw 0xEAE6 ; - .dw 0x7949 ; - .dw 0xEAE7 ; - .dw 0x22D ; - .dw 0xEAE8 ; - .dw 0x2975 ; - .dw 0xEAE9 ; - .dw 0x7F33 ; - .dw 0xEAEA ; - .dw 0xB6ED ; - .dw 0xEAEB ; - .dw 0x63D9 ; - .dw 0xEAEC ; - .dw 0x4025 ; - .dw 0xEAED ; - .dw 0xB09B ; - .dw 0xEAEE ; - .dw 0xAE2F ; - .dw 0xEAEF ; - .dw 0x9003 ; - .dw 0xEAF0 ; - .dw 0xB0EB ; - .dw 0xEAF1 ; - .dw 0xD3C7 ; - .dw 0xEAF2 ; - .dw 0x703D ; - .dw 0xEAF3 ; - .dw 0x729B ; - .dw 0xEAF4 ; - .dw 0x7221 ; - .dw 0xEAF5 ; - .dw 0x9FF1 ; - .dw 0xEAF6 ; - .dw 0x8F11 ; - .dw 0xEAF7 ; - .dw 0x325F ; - .dw 0xEAF8 ; - .dw 0x83C1 ; - .dw 0xEAF9 ; - .dw 0x54C7 ; - .dw 0xEAFA ; - .dw 0x2081 ; - .dw 0xEAFB ; - .dw 0xD20D ; - .dw 0xEAFC ; - .dw 0xA449 ; - .dw 0xEAFD ; - .dw 0x8A67 ; - .dw 0xEAFE ; - .dw 0xDAE1 ; - .dw 0xEAFF ; - .dw 0xAD1F ; - .dw 0xEB00 ; - .dw 0x7B07 ; - .dw 0xEB01 ; - .dw 0x8D3 ; - .dw 0xEB02 ; - .dw 0x6315 ; - .dw 0xEB03 ; - .dw 0x803 ; - .dw 0xEB04 ; - .dw 0xFFB ; - .dw 0xEB05 ; - .dw 0x9EF5 ; - .dw 0xEB06 ; - .dw 0x642B ; - .dw 0xEB07 ; - .dw 0x6BD5 ; - .dw 0xEB08 ; - .dw 0xE929 ; - .dw 0xEB09 ; - .dw 0x7107 ; - .dw 0xEB0A ; - .dw 0x8871 ; - .dw 0xEB0B ; - .dw 0x58F ; - .dw 0xEB0C ; - .dw 0xA56D ; - .dw 0xEB0D ; - .dw 0xB695 ; - .dw 0xEB0E ; - .dw 0xEC0F ; - .dw 0xEB0F ; - .dw 0xC0CD ; - .dw 0xEB10 ; - .dw 0x6CE3 ; - .dw 0xEB11 ; - .dw 0x5FF3 ; - .dw 0xEB12 ; - .dw 0x2123 ; - .dw 0xEB13 ; - .dw 0x55F9 ; - .dw 0xEB14 ; - .dw 0xEAB ; - .dw 0xEB15 ; - .dw 0x9B33 ; - .dw 0xEB16 ; - .dw 0x5D4D ; - .dw 0xEB17 ; - .dw 0x40D ; - .dw 0xEB18 ; - .dw 0x2451 ; - .dw 0xEB19 ; - .dw 0xB09F ; - .dw 0xEB1A ; - .dw 0xE8D1 ; - .dw 0xEB1B ; - .dw 0x2DC1 ; - .dw 0xEB1C ; - .dw 0x129B ; - .dw 0xEB1D ; - .dw 0x2EB5 ; - .dw 0xEB1E ; - .dw 0x6731 ; - .dw 0xEB1F ; - .dw 0x924D ; - .dw 0xEB20 ; - .dw 0x3FE3 ; - .dw 0xEB21 ; - .dw 0xDD91 ; - .dw 0xEB22 ; - .dw 0x113D ; - .dw 0xEB23 ; - .dw 0x599D ; - .dw 0xEB24 ; - .dw 0x57F7 ; - .dw 0xEB25 ; - .dw 0x71F7 ; - .dw 0xEB26 ; - .dw 0x78AD ; - .dw 0xEB27 ; - .dw 0xAC03 ; - .dw 0xEB28 ; - .dw 0xF563 ; - .dw 0xEB29 ; - .dw 0x77BF ; - .dw 0xEB2A ; - .dw 0xED3B ; - .dw 0xEB2B ; - .dw 0xD7D ; - .dw 0xEB2C ; - .dw 0x8855 ; - .dw 0xEB2D ; - .dw 0x6BD1 ; - .dw 0xEB2E ; - .dw 0x1B3D ; - .dw 0xEB2F ; - .dw 0x345D ; - .dw 0xEB30 ; - .dw 0xD2EF ; - .dw 0xEB31 ; - .dw 0x7D9D ; - .dw 0xEB32 ; - .dw 0xFBB9 ; - .dw 0xEB33 ; - .dw 0x938B ; - .dw 0xEB34 ; - .dw 0xD321 ; - .dw 0xEB35 ; - .dw 0xF011 ; - .dw 0xEB36 ; - .dw 0xAE01 ; - .dw 0xEB37 ; - .dw 0x503B ; - .dw 0xEB38 ; - .dw 0x7201 ; - .dw 0xEB39 ; - .dw 0x9215 ; - .dw 0xEB3A ; - .dw 0x52C1 ; - .dw 0xEB3B ; - .dw 0xDB23 ; - .dw 0xEB3C ; - .dw 0xD0A1 ; - .dw 0xEB3D ; - .dw 0x467B ; - .dw 0xEB3E ; - .dw 0x80A7 ; - .dw 0xEB3F ; - .dw 0xE539 ; - .dw 0xEB40 ; - .dw 0x8A6B ; - .dw 0xEB41 ; - .dw 0x1385 ; - .dw 0xEB42 ; - .dw 0x6A6F ; - .dw 0xEB43 ; - .dw 0xE7E1 ; - .dw 0xEB44 ; - .dw 0xC4F1 ; - .dw 0xEB45 ; - .dw 0xB1CF ; - .dw 0xEB46 ; - .dw 0x4E7F ; - .dw 0xEB47 ; - .dw 0xF8AD ; - .dw 0xEB48 ; - .dw 0x6553 ; - .dw 0xEB49 ; - .dw 0x12CB ; - .dw 0xEB4A ; - .dw 0x47FB ; - .dw 0xEB4B ; - .dw 0x2091 ; - .dw 0xEB4C ; - .dw 0x4307 ; - .dw 0xEB4D ; - .dw 0xD6C1 ; - .dw 0xEB4E ; - .dw 0x1967 ; - .dw 0xEB4F ; - .dw 0xEEA1 ; - .dw 0xEB50 ; - .dw 0xB03D ; - .dw 0xEB51 ; - .dw 0x2A37 ; - .dw 0xEB52 ; - .dw 0x8B3 ; - .dw 0xEB53 ; - .dw 0x7E3D ; - .dw 0xEB54 ; - .dw 0x2FAF ; - .dw 0xEB55 ; - .dw 0x2FD ; - .dw 0xEB56 ; - .dw 0x64DD ; - .dw 0xEB57 ; - .dw 0xA8D9 ; - .dw 0xEB58 ; - .dw 0xAFFF ; - .dw 0xEB59 ; - .dw 0x3495 ; - .dw 0xEB5A ; - .dw 0xCCFF ; - .dw 0xEB5B ; - .dw 0x9B25 ; - .dw 0xEB5C ; - .dw 0x248D ; - .dw 0xEB5D ; - .dw 0x542D ; - .dw 0xEB5E ; - .dw 0xD0F1 ; - .dw 0xEB5F ; - .dw 0x85D1 ; - .dw 0xEB60 ; - .dw 0xD3CD ; - .dw 0xEB61 ; - .dw 0xE423 ; - .dw 0xEB62 ; - .dw 0x35D ; - .dw 0xEB63 ; - .dw 0xA1BF ; - .dw 0xEB64 ; - .dw 0x331F ; - .dw 0xEB65 ; - .dw 0xBEED ; - .dw 0xEB66 ; - .dw 0x1551 ; - .dw 0xEB67 ; - .dw 0x3FBD ; - .dw 0xEB68 ; - .dw 0xA82B ; - .dw 0xEB69 ; - .dw 0x399B ; - .dw 0xEB6A ; - .dw 0x1361 ; - .dw 0xEB6B ; - .dw 0x1BBD ; - .dw 0xEB6C ; - .dw 0x7B9 ; - .dw 0xEB6D ; - .dw 0xF5D1 ; - .dw 0xEB6E ; - .dw 0x5C3D ; - .dw 0xEB6F ; - .dw 0xAB89 ; - .dw 0xEB70 ; - .dw 0x29FF ; - .dw 0xEB71 ; - .dw 0xDB33 ; - .dw 0xEB72 ; - .dw 0x68BF ; - .dw 0xEB73 ; - .dw 0xA105 ; - .dw 0xEB74 ; - .dw 0x6C87 ; - .dw 0xEB75 ; - .dw 0x3069 ; - .dw 0xEB76 ; - .dw 0xFD91 ; - .dw 0xEB77 ; - .dw 0x57D9 ; - .dw 0xEB78 ; - .dw 0x797D ; - .dw 0xEB79 ; - .dw 0x4B91 ; - .dw 0xEB7A ; - .dw 0xDE3B ; - .dw 0xEB7B ; - .dw 0x66B7 ; - .dw 0xEB7C ; - .dw 0x2C8F ; - .dw 0xEB7D ; - .dw 0xD239 ; - .dw 0xEB7E ; - .dw 0x99BF ; - .dw 0xEB7F ; - .dw 0xC07 ; - .dw 0xEB80 ; - .dw 0xED3B ; - .dw 0xEB81 ; - .dw 0xD7 ; - .dw 0xEB82 ; - .dw 0x88B3 ; - .dw 0xEB83 ; - .dw 0xAE29 ; - .dw 0xEB84 ; - .dw 0x56AD ; - .dw 0xEB85 ; - .dw 0xF1BF ; - .dw 0xEB86 ; - .dw 0x94D3 ; - .dw 0xEB87 ; - .dw 0x2727 ; - .dw 0xEB88 ; - .dw 0x851B ; - .dw 0xEB89 ; - .dw 0x5B9F ; - .dw 0xEB8A ; - .dw 0xE21F ; - .dw 0xEB8B ; - .dw 0x13EF ; - .dw 0xEB8C ; - .dw 0xE097 ; - .dw 0xEB8D ; - .dw 0xBF73 ; - .dw 0xEB8E ; - .dw 0xF16F ; - .dw 0xEB8F ; - .dw 0xDF07 ; - .dw 0xEB90 ; - .dw 0xBD65 ; - .dw 0xEB91 ; - .dw 0x7DFD ; - .dw 0xEB92 ; - .dw 0x548D ; - .dw 0xEB93 ; - .dw 0xBECD ; - .dw 0xEB94 ; - .dw 0xA9D7 ; - .dw 0xEB95 ; - .dw 0xCCC1 ; - .dw 0xEB96 ; - .dw 0x8BCD ; - .dw 0xEB97 ; - .dw 0x5F29 ; - .dw 0xEB98 ; - .dw 0xC1AB ; - .dw 0xEB99 ; - .dw 0x279 ; - .dw 0xEB9A ; - .dw 0x2525 ; - .dw 0xEB9B ; - .dw 0x6EC5 ; - .dw 0xEB9C ; - .dw 0xDED5 ; - .dw 0xEB9D ; - .dw 0x330D ; - .dw 0xEB9E ; - .dw 0xB4C3 ; - .dw 0xEB9F ; - .dw 0xC7C9 ; - .dw 0xEBA0 ; - .dw 0xFFE3 ; - .dw 0xEBA1 ; - .dw 0x9313 ; - .dw 0xEBA2 ; - .dw 0xBF25 ; - .dw 0xEBA3 ; - .dw 0x6C0F ; - .dw 0xEBA4 ; - .dw 0xBBCD ; - .dw 0xEBA5 ; - .dw 0x9AB9 ; - .dw 0xEBA6 ; - .dw 0x2CB7 ; - .dw 0xEBA7 ; - .dw 0xCDB ; - .dw 0xEBA8 ; - .dw 0x1B53 ; - .dw 0xEBA9 ; - .dw 0x6047 ; - .dw 0xEBAA ; - .dw 0x5EE3 ; - .dw 0xEBAB ; - .dw 0x5619 ; - .dw 0xEBAC ; - .dw 0xAFD3 ; - .dw 0xEBAD ; - .dw 0x2217 ; - .dw 0xEBAE ; - .dw 0x7EAF ; - .dw 0xEBAF ; - .dw 0xB50B ; - .dw 0xEBB0 ; - .dw 0x3F9D ; - .dw 0xEBB1 ; - .dw 0x7807 ; - .dw 0xEBB2 ; - .dw 0x1CCF ; - .dw 0xEBB3 ; - .dw 0xD28B ; - .dw 0xEBB4 ; - .dw 0xDFD3 ; - .dw 0xEBB5 ; - .dw 0x2477 ; - .dw 0xEBB6 ; - .dw 0xBB43 ; - .dw 0xEBB7 ; - .dw 0x78BB ; - .dw 0xEBB8 ; - .dw 0xD3B9 ; - .dw 0xEBB9 ; - .dw 0xFCBD ; - .dw 0xEBBA ; - .dw 0x586F ; - .dw 0xEBBB ; - .dw 0x1C45 ; - .dw 0xEBBC ; - .dw 0x993 ; - .dw 0xEBBD ; - .dw 0xE11D ; - .dw 0xEBBE ; - .dw 0x93A9 ; - .dw 0xEBBF ; - .dw 0xC109 ; - .dw 0xEBC0 ; - .dw 0x8CF7 ; - .dw 0xEBC1 ; - .dw 0x3C47 ; - .dw 0xEBC2 ; - .dw 0x8361 ; - .dw 0xEBC3 ; - .dw 0x725F ; - .dw 0xEBC4 ; - .dw 0xC6AF ; - .dw 0xEBC5 ; - .dw 0x249 ; - .dw 0xEBC6 ; - .dw 0xD4AB ; - .dw 0xEBC7 ; - .dw 0x6C7 ; - .dw 0xEBC8 ; - .dw 0xE201 ; - .dw 0xEBC9 ; - .dw 0xA703 ; - .dw 0xEBCA ; - .dw 0x4C5D ; - .dw 0xEBCB ; - .dw 0x6729 ; - .dw 0xEBCC ; - .dw 0x2F9B ; - .dw 0xEBCD ; - .dw 0x42D ; - .dw 0xEBCE ; - .dw 0x41A9 ; - .dw 0xEBCF ; - .dw 0x1183 ; - .dw 0xEBD0 ; - .dw 0xDDD9 ; - .dw 0xEBD1 ; - .dw 0xA6C1 ; - .dw 0xEBD2 ; - .dw 0x2A31 ; - .dw 0xEBD3 ; - .dw 0xF29 ; - .dw 0xEBD4 ; - .dw 0xDEA7 ; - .dw 0xEBD5 ; - .dw 0x7BFB ; - .dw 0xEBD6 ; - .dw 0xCFA1 ; - .dw 0xEBD7 ; - .dw 0x167D ; - .dw 0xEBD8 ; - .dw 0x52D5 ; - .dw 0xEBD9 ; - .dw 0x55CB ; - .dw 0xEBDA ; - .dw 0x46C5 ; - .dw 0xEBDB ; - .dw 0x1021 ; - .dw 0xEBDC ; - .dw 0x52F3 ; - .dw 0xEBDD ; - .dw 0x3ED7 ; - .dw 0xEBDE ; - .dw 0x4025 ; - .dw 0xEBDF ; - .dw 0xB7B5 ; - .dw 0xEBE0 ; - .dw 0x6DA7 ; - .dw 0xEBE1 ; - .dw 0x15E3 ; - .dw 0xEBE2 ; - .dw 0xCA17 ; - .dw 0xEBE3 ; - .dw 0x9009 ; - .dw 0xEBE4 ; - .dw 0xB381 ; - .dw 0xEBE5 ; - .dw 0x68DD ; - .dw 0xEBE6 ; - .dw 0x1C5F ; - .dw 0xEBE7 ; - .dw 0xE2DB ; - .dw 0xEBE8 ; - .dw 0xA857 ; - .dw 0xEBE9 ; - .dw 0x743 ; - .dw 0xEBEA ; - .dw 0x853D ; - .dw 0xEBEB ; - .dw 0x40F ; - .dw 0xEBEC ; - .dw 0xF221 ; - .dw 0xEBED ; - .dw 0x4425 ; - .dw 0xEBEE ; - .dw 0x1011 ; - .dw 0xEBEF ; - .dw 0x905F ; - .dw 0xEBF0 ; - .dw 0x1D49 ; - .dw 0xEBF1 ; - .dw 0x5F9B ; - .dw 0xEBF2 ; - .dw 0xFD67 ; - .dw 0xEBF3 ; - .dw 0xDF9B ; - .dw 0xEBF4 ; - .dw 0x4E83 ; - .dw 0xEBF5 ; - .dw 0xFBD ; - .dw 0xEBF6 ; - .dw 0xA497 ; - .dw 0xEBF7 ; - .dw 0x6261 ; - .dw 0xEBF8 ; - .dw 0x3A31 ; - .dw 0xEBF9 ; - .dw 0xA117 ; - .dw 0xEBFA ; - .dw 0xD6DB ; - .dw 0xEBFB ; - .dw 0x234D ; - .dw 0xEBFC ; - .dw 0x392B ; - .dw 0xEBFD ; - .dw 0xA6A9 ; - .dw 0xEBFE ; - .dw 0x5BE5 ; - .dw 0xEBFF ; - .dw 0x23BD ; - .dw 0xEC00 ; - .dw 0xD323 ; - .dw 0xEC01 ; - .dw 0xB157 ; - .dw 0xEC02 ; - .dw 0x9FF7 ; - .dw 0xEC03 ; - .dw 0xCBFF ; - .dw 0xEC04 ; - .dw 0x9675 ; - .dw 0xEC05 ; - .dw 0x6E9 ; - .dw 0xEC06 ; - .dw 0x2B83 ; - .dw 0xEC07 ; - .dw 0x2709 ; - .dw 0xEC08 ; - .dw 0x9585 ; - .dw 0xEC09 ; - .dw 0xD077 ; - .dw 0xEC0A ; - .dw 0xFC33 ; - .dw 0xEC0B ; - .dw 0x21BD ; - .dw 0xEC0C ; - .dw 0x6195 ; - .dw 0xEC0D ; - .dw 0xB86F ; - .dw 0xEC0E ; - .dw 0x5795 ; - .dw 0xEC0F ; - .dw 0x8591 ; - .dw 0xEC10 ; - .dw 0xDB1B ; - .dw 0xEC11 ; - .dw 0x7005 ; - .dw 0xEC12 ; - .dw 0x2F1F ; - .dw 0xEC13 ; - .dw 0xE6D1 ; - .dw 0xEC14 ; - .dw 0xAF9B ; - .dw 0xEC15 ; - .dw 0x142D ; - .dw 0xEC16 ; - .dw 0xADD5 ; - .dw 0xEC17 ; - .dw 0x3E55 ; - .dw 0xEC18 ; - .dw 0xDCFB ; - .dw 0xEC19 ; - .dw 0xEA0F ; - .dw 0xEC1A ; - .dw 0x75F ; - .dw 0xEC1B ; - .dw 0x66B9 ; - .dw 0xEC1C ; - .dw 0x1267 ; - .dw 0xEC1D ; - .dw 0x6B05 ; - .dw 0xEC1E ; - .dw 0x2099 ; - .dw 0xEC1F ; - .dw 0x3513 ; - .dw 0xEC20 ; - .dw 0x4699 ; - .dw 0xEC21 ; - .dw 0x1813 ; - .dw 0xEC22 ; - .dw 0x29B3 ; - .dw 0xEC23 ; - .dw 0x652F ; - .dw 0xEC24 ; - .dw 0x5BB9 ; - .dw 0xEC25 ; - .dw 0xCD9 ; - .dw 0xEC26 ; - .dw 0xC1C7 ; - .dw 0xEC27 ; - .dw 0x1141 ; - .dw 0xEC28 ; - .dw 0x28BB ; - .dw 0xEC29 ; - .dw 0xCA0D ; - .dw 0xEC2A ; - .dw 0xBBF1 ; - .dw 0xEC2B ; - .dw 0xED21 ; - .dw 0xEC2C ; - .dw 0xC027 ; - .dw 0xEC2D ; - .dw 0x2F7B ; - .dw 0xEC2E ; - .dw 0x1DE5 ; - .dw 0xEC2F ; - .dw 0xFD07 ; - .dw 0xEC30 ; - .dw 0x4C81 ; - .dw 0xEC31 ; - .dw 0x1D6F ; - .dw 0xEC32 ; - .dw 0x7009 ; - .dw 0xEC33 ; - .dw 0xFFB9 ; - .dw 0xEC34 ; - .dw 0x5A19 ; - .dw 0xEC35 ; - .dw 0xB5BB ; - .dw 0xEC36 ; - .dw 0xF70D ; - .dw 0xEC37 ; - .dw 0x4449 ; - .dw 0xEC38 ; - .dw 0xE667 ; - .dw 0xEC39 ; - .dw 0xB423 ; - .dw 0xEC3A ; - .dw 0xEF01 ; - .dw 0xEC3B ; - .dw 0x2353 ; - .dw 0xEC3C ; - .dw 0xCD9 ; - .dw 0xEC3D ; - .dw 0xD65D ; - .dw 0xEC3E ; - .dw 0x5FF1 ; - .dw 0xEC3F ; - .dw 0xD3A7 ; - .dw 0xEC40 ; - .dw 0xA93B ; - .dw 0xEC41 ; - .dw 0xCB87 ; - .dw 0xEC42 ; - .dw 0xA3F7 ; - .dw 0xEC43 ; - .dw 0xD28B ; - .dw 0xEC44 ; - .dw 0xC781 ; - .dw 0xEC45 ; - .dw 0xA31F ; - .dw 0xEC46 ; - .dw 0x36DD ; - .dw 0xEC47 ; - .dw 0x976F ; - .dw 0xEC48 ; - .dw 0x3927 ; - .dw 0xEC49 ; - .dw 0x3379 ; - .dw 0xEC4A ; - .dw 0xE725 ; - .dw 0xEC4B ; - .dw 0xCB2D ; - .dw 0xEC4C ; - .dw 0x2805 ; - .dw 0xEC4D ; - .dw 0x6FB9 ; - .dw 0xEC4E ; - .dw 0xB1 ; - .dw 0xEC4F ; - .dw 0xBAB1 ; - .dw 0xEC50 ; - .dw 0xFEAB ; - .dw 0xEC51 ; - .dw 0x2549 ; - .dw 0xEC52 ; - .dw 0x88D5 ; - .dw 0xEC53 ; - .dw 0x3D43 ; - .dw 0xEC54 ; - .dw 0x7E33 ; - .dw 0xEC55 ; - .dw 0x18D5 ; - .dw 0xEC56 ; - .dw 0x23EB ; - .dw 0xEC57 ; - .dw 0xC62F ; - .dw 0xEC58 ; - .dw 0x59A1 ; - .dw 0xEC59 ; - .dw 0xFAC1 ; - .dw 0xEC5A ; - .dw 0xBC71 ; - .dw 0xEC5B ; - .dw 0xDA0D ; - .dw 0xEC5C ; - .dw 0x2EB1 ; - .dw 0xEC5D ; - .dw 0x2B1D ; - .dw 0xEC5E ; - .dw 0x839D ; - .dw 0xEC5F ; - .dw 0x9F67 ; - .dw 0xEC60 ; - .dw 0x3437 ; - .dw 0xEC61 ; - .dw 0xC523 ; - .dw 0xEC62 ; - .dw 0x6377 ; - .dw 0xEC63 ; - .dw 0xC301 ; - .dw 0xEC64 ; - .dw 0x75F9 ; - .dw 0xEC65 ; - .dw 0xEA2B ; - .dw 0xEC66 ; - .dw 0x7A71 ; - .dw 0xEC67 ; - .dw 0x6789 ; - .dw 0xEC68 ; - .dw 0xF5F9 ; - .dw 0xEC69 ; - .dw 0xC429 ; - .dw 0xEC6A ; - .dw 0xB87F ; - .dw 0xEC6B ; - .dw 0x58CF ; - .dw 0xEC6C ; - .dw 0x8B61 ; - .dw 0xEC6D ; - .dw 0x3799 ; - .dw 0xEC6E ; - .dw 0x35AB ; - .dw 0xEC6F ; - .dw 0x3A81 ; - .dw 0xEC70 ; - .dw 0xD6C7 ; - .dw 0xEC71 ; - .dw 0xBD03 ; - .dw 0xEC72 ; - .dw 0x5A35 ; - .dw 0xEC73 ; - .dw 0xEA61 ; - .dw 0xEC74 ; - .dw 0x2415 ; - .dw 0xEC75 ; - .dw 0x59EF ; - .dw 0xEC76 ; - .dw 0x7023 ; - .dw 0xEC77 ; - .dw 0xCDF7 ; - .dw 0xEC78 ; - .dw 0x91D9 ; - .dw 0xEC79 ; - .dw 0x315D ; - .dw 0xEC7A ; - .dw 0xB661 ; - .dw 0xEC7B ; - .dw 0x43D3 ; - .dw 0xEC7C ; - .dw 0x561D ; - .dw 0xEC7D ; - .dw 0xA3B7 ; - .dw 0xEC7E ; - .dw 0x8D4F ; - .dw 0xEC7F ; - .dw 0xF043 ; - .dw 0xEC80 ; - .dw 0x78C1 ; - .dw 0xEC81 ; - .dw 0x7657 ; - .dw 0xEC82 ; - .dw 0xD4E1 ; - .dw 0xEC83 ; - .dw 0x1D81 ; - .dw 0xEC84 ; - .dw 0xDB51 ; - .dw 0xEC85 ; - .dw 0xFA6F ; - .dw 0xEC86 ; - .dw 0x1437 ; - .dw 0xEC87 ; - .dw 0xE779 ; - .dw 0xEC88 ; - .dw 0xE665 ; - .dw 0xEC89 ; - .dw 0xAB8B ; - .dw 0xEC8A ; - .dw 0x82AF ; - .dw 0xEC8B ; - .dw 0x6AF9 ; - .dw 0xEC8C ; - .dw 0xB46B ; - .dw 0xEC8D ; - .dw 0x3D89 ; - .dw 0xEC8E ; - .dw 0x8A81 ; - .dw 0xEC8F ; - .dw 0xB067 ; - .dw 0xEC90 ; - .dw 0x1207 ; - .dw 0xEC91 ; - .dw 0x920D ; - .dw 0xEC92 ; - .dw 0xDCD5 ; - .dw 0xEC93 ; - .dw 0x8A01 ; - .dw 0xEC94 ; - .dw 0x2BF3 ; - .dw 0xEC95 ; - .dw 0x8D77 ; - .dw 0xEC96 ; - .dw 0xAF63 ; - .dw 0xEC97 ; - .dw 0x1D8F ; - .dw 0xEC98 ; - .dw 0x4243 ; - .dw 0xEC99 ; - .dw 0x4363 ; - .dw 0xEC9A ; - .dw 0x3B7F ; - .dw 0xEC9B ; - .dw 0x519B ; - .dw 0xEC9C ; - .dw 0x394F ; - .dw 0xEC9D ; - .dw 0x729B ; - .dw 0xEC9E ; - .dw 0x16B5 ; - .dw 0xEC9F ; - .dw 0xD62B ; - .dw 0xECA0 ; - .dw 0x6005 ; - .dw 0xECA1 ; - .dw 0xC893 ; - .dw 0xECA2 ; - .dw 0x7CE7 ; - .dw 0xECA3 ; - .dw 0xFD ; - .dw 0xECA4 ; - .dw 0x43BD ; - .dw 0xECA5 ; - .dw 0xE457 ; - .dw 0xECA6 ; - .dw 0x23DD ; - .dw 0xECA7 ; - .dw 0x3533 ; - .dw 0xECA8 ; - .dw 0xE997 ; - .dw 0xECA9 ; - .dw 0x9113 ; - .dw 0xECAA ; - .dw 0xB065 ; - .dw 0xECAB ; - .dw 0xE99 ; - .dw 0xECAC ; - .dw 0x4551 ; - .dw 0xECAD ; - .dw 0x2FFD ; - .dw 0xECAE ; - .dw 0x64E1 ; - .dw 0xECAF ; - .dw 0x851 ; - .dw 0xECB0 ; - .dw 0x459B ; - .dw 0xECB1 ; - .dw 0xC9D5 ; - .dw 0xECB2 ; - .dw 0x2169 ; - .dw 0xECB3 ; - .dw 0xD715 ; - .dw 0xECB4 ; - .dw 0x4DF7 ; - .dw 0xECB5 ; - .dw 0xBFDB ; - .dw 0xECB6 ; - .dw 0x4D5B ; - .dw 0xECB7 ; - .dw 0x2EE7 ; - .dw 0xECB8 ; - .dw 0x760B ; - .dw 0xECB9 ; - .dw 0x9447 ; - .dw 0xECBA ; - .dw 0xC279 ; - .dw 0xECBB ; - .dw 0x2C4F ; - .dw 0xECBC ; - .dw 0x6675 ; - .dw 0xECBD ; - .dw 0xC23B ; - .dw 0xECBE ; - .dw 0x517F ; - .dw 0xECBF ; - .dw 0x1913 ; - .dw 0xECC0 ; - .dw 0x2B33 ; - .dw 0xECC1 ; - .dw 0x1D45 ; - .dw 0xECC2 ; - .dw 0xF835 ; - .dw 0xECC3 ; - .dw 0xC463 ; - .dw 0xECC4 ; - .dw 0xD369 ; - .dw 0xECC5 ; - .dw 0xB055 ; - .dw 0xECC6 ; - .dw 0x6115 ; - .dw 0xECC7 ; - .dw 0x26A7 ; - .dw 0xECC8 ; - .dw 0x36C1 ; - .dw 0xECC9 ; - .dw 0x942D ; - .dw 0xECCA ; - .dw 0xC453 ; - .dw 0xECCB ; - .dw 0x889F ; - .dw 0xECCC ; - .dw 0xB845 ; - .dw 0xECCD ; - .dw 0xB561 ; - .dw 0xECCE ; - .dw 0xC281 ; - .dw 0xECCF ; - .dw 0xE62F ; - .dw 0xECD0 ; - .dw 0x5EB3 ; - .dw 0xECD1 ; - .dw 0x1CF ; - .dw 0xECD2 ; - .dw 0x509F ; - .dw 0xECD3 ; - .dw 0xC48B ; - .dw 0xECD4 ; - .dw 0x1A57 ; - .dw 0xECD5 ; - .dw 0xF58F ; - .dw 0xECD6 ; - .dw 0x4DBD ; - .dw 0xECD7 ; - .dw 0x33F1 ; - .dw 0xECD8 ; - .dw 0x9061 ; - .dw 0xECD9 ; - .dw 0xFF75 ; - .dw 0xECDA ; - .dw 0xDA05 ; - .dw 0xECDB ; - .dw 0x34E5 ; - .dw 0xECDC ; - .dw 0x43C3 ; - .dw 0xECDD ; - .dw 0xB503 ; - .dw 0xECDE ; - .dw 0x75D ; - .dw 0xECDF ; - .dw 0x38E5 ; - .dw 0xECE0 ; - .dw 0x737F ; - .dw 0xECE1 ; - .dw 0x4DE1 ; - .dw 0xECE2 ; - .dw 0xFB7F ; - .dw 0xECE3 ; - .dw 0xF6A5 ; - .dw 0xECE4 ; - .dw 0x8687 ; - .dw 0xECE5 ; - .dw 0x5ED9 ; - .dw 0xECE6 ; - .dw 0x1B8B ; - .dw 0xECE7 ; - .dw 0x49C3 ; - .dw 0xECE8 ; - .dw 0x5D11 ; - .dw 0xECE9 ; - .dw 0x4C4B ; - .dw 0xECEA ; - .dw 0x5925 ; - .dw 0xECEB ; - .dw 0x55FD ; - .dw 0xECEC ; - .dw 0x5F77 ; - .dw 0xECED ; - .dw 0x6C29 ; - .dw 0xECEE ; - .dw 0x390B ; - .dw 0xECEF ; - .dw 0xA5F3 ; - .dw 0xECF0 ; - .dw 0xA27D ; - .dw 0xECF1 ; - .dw 0x4F69 ; - .dw 0xECF2 ; - .dw 0xAB29 ; - .dw 0xECF3 ; - .dw 0x7D53 ; - .dw 0xECF4 ; - .dw 0xF93F ; - .dw 0xECF5 ; - .dw 0x2B01 ; - .dw 0xECF6 ; - .dw 0x4C35 ; - .dw 0xECF7 ; - .dw 0x169B ; - .dw 0xECF8 ; - .dw 0x4C79 ; - .dw 0xECF9 ; - .dw 0xD85F ; - .dw 0xECFA ; - .dw 0x28CD ; - .dw 0xECFB ; - .dw 0x447 ; - .dw 0xECFC ; - .dw 0xF65 ; - .dw 0xECFD ; - .dw 0x6565 ; - .dw 0xECFE ; - .dw 0x99FF ; - .dw 0xECFF ; - .dw 0x6D95 ; - .dw 0xED00 ; - .dw 0x2A15 ; - .dw 0xED01 ; - .dw 0xABD3 ; - .dw 0xED02 ; - .dw 0x5373 ; - .dw 0xED03 ; - .dw 0x5EB1 ; - .dw 0xED04 ; - .dw 0x3145 ; - .dw 0xED05 ; - .dw 0xE853 ; - .dw 0xED06 ; - .dw 0x3AF3 ; - .dw 0xED07 ; - .dw 0xE477 ; - .dw 0xED08 ; - .dw 0x43BB ; - .dw 0xED09 ; - .dw 0xC8DF ; - .dw 0xED0A ; - .dw 0x218F ; - .dw 0xED0B ; - .dw 0x2BA1 ; - .dw 0xED0C ; - .dw 0x6515 ; - .dw 0xED0D ; - .dw 0xEAC1 ; - .dw 0xED0E ; - .dw 0xF631 ; - .dw 0xED0F ; - .dw 0x5B8B ; - .dw 0xED10 ; - .dw 0xAE2B ; - .dw 0xED11 ; - .dw 0x4011 ; - .dw 0xED12 ; - .dw 0x89B3 ; - .dw 0xED13 ; - .dw 0x645F ; - .dw 0xED14 ; - .dw 0x2AE1 ; - .dw 0xED15 ; - .dw 0x549F ; - .dw 0xED16 ; - .dw 0x7C77 ; - .dw 0xED17 ; - .dw 0x78D5 ; - .dw 0xED18 ; - .dw 0xBD7F ; - .dw 0xED19 ; - .dw 0xEA75 ; - .dw 0xED1A ; - .dw 0x6D83 ; - .dw 0xED1B ; - .dw 0x6B69 ; - .dw 0xED1C ; - .dw 0xDF8D ; - .dw 0xED1D ; - .dw 0xE5CF ; - .dw 0xED1E ; - .dw 0x317 ; - .dw 0xED1F ; - .dw 0xA713 ; - .dw 0xED20 ; - .dw 0x9825 ; - .dw 0xED21 ; - .dw 0x8F ; - .dw 0xED22 ; - .dw 0xE4C1 ; - .dw 0xED23 ; - .dw 0xFB79 ; - .dw 0xED24 ; - .dw 0x7FD5 ; - .dw 0xED25 ; - .dw 0x3D33 ; - .dw 0xED26 ; - .dw 0x3EFB ; - .dw 0xED27 ; - .dw 0xF4B5 ; - .dw 0xED28 ; - .dw 0x29EB ; - .dw 0xED29 ; - .dw 0x9155 ; - .dw 0xED2A ; - .dw 0xE83F ; - .dw 0xED2B ; - .dw 0xF67D ; - .dw 0xED2C ; - .dw 0xCB51 ; - .dw 0xED2D ; - .dw 0xBF9D ; - .dw 0xED2E ; - .dw 0xBFA5 ; - .dw 0xED2F ; - .dw 0xD2E9 ; - .dw 0xED30 ; - .dw 0x76EB ; - .dw 0xED31 ; - .dw 0xD939 ; - .dw 0xED32 ; - .dw 0x5CF1 ; - .dw 0xED33 ; - .dw 0x149F ; - .dw 0xED34 ; - .dw 0xC76B ; - .dw 0xED35 ; - .dw 0x5EDB ; - .dw 0xED36 ; - .dw 0xAA31 ; - .dw 0xED37 ; - .dw 0xB491 ; - .dw 0xED38 ; - .dw 0x4EA3 ; - .dw 0xED39 ; - .dw 0x7929 ; - .dw 0xED3A ; - .dw 0x7ED9 ; - .dw 0xED3B ; - .dw 0x733B ; - .dw 0xED3C ; - .dw 0xA269 ; - .dw 0xED3D ; - .dw 0x40B5 ; - .dw 0xED3E ; - .dw 0xD453 ; - .dw 0xED3F ; - .dw 0x8D4D ; - .dw 0xED40 ; - .dw 0x5EE3 ; - .dw 0xED41 ; - .dw 0x8D81 ; - .dw 0xED42 ; - .dw 0xAC19 ; - .dw 0xED43 ; - .dw 0x3EB ; - .dw 0xED44 ; - .dw 0xF667 ; - .dw 0xED45 ; - .dw 0x45E9 ; - .dw 0xED46 ; - .dw 0x3F53 ; - .dw 0xED47 ; - .dw 0x306B ; - .dw 0xED48 ; - .dw 0xA6D1 ; - .dw 0xED49 ; - .dw 0xA51F ; - .dw 0xED4A ; - .dw 0x8FE7 ; - .dw 0xED4B ; - .dw 0xDB7F ; - .dw 0xED4C ; - .dw 0x6C5B ; - .dw 0xED4D ; - .dw 0x7129 ; - .dw 0xED4E ; - .dw 0xF315 ; - .dw 0xED4F ; - .dw 0x8FFB ; - .dw 0xED50 ; - .dw 0x49F1 ; - .dw 0xED51 ; - .dw 0x9853 ; - .dw 0xED52 ; - .dw 0xAD8F ; - .dw 0xED53 ; - .dw 0x60FF ; - .dw 0xED54 ; - .dw 0xBF0F ; - .dw 0xED55 ; - .dw 0x2E27 ; - .dw 0xED56 ; - .dw 0x3913 ; - .dw 0xED57 ; - .dw 0xDBBF ; - .dw 0xED58 ; - .dw 0xC319 ; - .dw 0xED59 ; - .dw 0x3FE7 ; - .dw 0xED5A ; - .dw 0x4B7D ; - .dw 0xED5B ; - .dw 0x5CAB ; - .dw 0xED5C ; - .dw 0x1E2B ; - .dw 0xED5D ; - .dw 0x7885 ; - .dw 0xED5E ; - .dw 0x3761 ; - .dw 0xED5F ; - .dw 0x8033 ; - .dw 0xED60 ; - .dw 0x777B ; - .dw 0xED61 ; - .dw 0xC1B ; - .dw 0xED62 ; - .dw 0xBE2B ; - .dw 0xED63 ; - .dw 0xE6F9 ; - .dw 0xED64 ; - .dw 0xF12B ; - .dw 0xED65 ; - .dw 0xE2E3 ; - .dw 0xED66 ; - .dw 0xEBAB ; - .dw 0xED67 ; - .dw 0x58B ; - .dw 0xED68 ; - .dw 0xA99F ; - .dw 0xED69 ; - .dw 0x7BAD ; - .dw 0xED6A ; - .dw 0x1333 ; - .dw 0xED6B ; - .dw 0x3799 ; - .dw 0xED6C ; - .dw 0xFA61 ; - .dw 0xED6D ; - .dw 0x7DD7 ; - .dw 0xED6E ; - .dw 0x8631 ; - .dw 0xED6F ; - .dw 0xCEB1 ; - .dw 0xED70 ; - .dw 0xCC69 ; - .dw 0xED71 ; - .dw 0x72CB ; - .dw 0xED72 ; - .dw 0x1C41 ; - .dw 0xED73 ; - .dw 0x5475 ; - .dw 0xED74 ; - .dw 0xD9FD ; - .dw 0xED75 ; - .dw 0x9EEF ; - .dw 0xED76 ; - .dw 0x24CF ; - .dw 0xED77 ; - .dw 0xB84D ; - .dw 0xED78 ; - .dw 0x360D ; - .dw 0xED79 ; - .dw 0x7221 ; - .dw 0xED7A ; - .dw 0xDA1F ; - .dw 0xED7B ; - .dw 0xA0A9 ; - .dw 0xED7C ; - .dw 0xF103 ; - .dw 0xED7D ; - .dw 0x87AF ; - .dw 0xED7E ; - .dw 0xEDF7 ; - .dw 0xED7F ; - .dw 0x97B7 ; - .dw 0xED80 ; - .dw 0x331F ; - .dw 0xED81 ; - .dw 0xADCF ; - .dw 0xED82 ; - .dw 0x47A9 ; - .dw 0xED83 ; - .dw 0x4B91 ; - .dw 0xED84 ; - .dw 0xA44F ; - .dw 0xED85 ; - .dw 0xEC95 ; - .dw 0xED86 ; - .dw 0x8BB3 ; - .dw 0xED87 ; - .dw 0x9A03 ; - .dw 0xED88 ; - .dw 0x7985 ; - .dw 0xED89 ; - .dw 0x46F ; - .dw 0xED8A ; - .dw 0x84D7 ; - .dw 0xED8B ; - .dw 0x9FB9 ; - .dw 0xED8C ; - .dw 0xFF95 ; - .dw 0xED8D ; - .dw 0x5C17 ; - .dw 0xED8E ; - .dw 0x6A9 ; - .dw 0xED8F ; - .dw 0x82FD ; - .dw 0xED90 ; - .dw 0xFB83 ; - .dw 0xED91 ; - .dw 0xD613 ; - .dw 0xED92 ; - .dw 0x61B7 ; - .dw 0xED93 ; - .dw 0x31EB ; - .dw 0xED94 ; - .dw 0xB865 ; - .dw 0xED95 ; - .dw 0x85A5 ; - .dw 0xED96 ; - .dw 0x111 ; - .dw 0xED97 ; - .dw 0xCC2B ; - .dw 0xED98 ; - .dw 0x1AB1 ; - .dw 0xED99 ; - .dw 0xBB47 ; - .dw 0xED9A ; - .dw 0x496F ; - .dw 0xED9B ; - .dw 0xF027 ; - .dw 0xED9C ; - .dw 0x911F ; - .dw 0xED9D ; - .dw 0x60A1 ; - .dw 0xED9E ; - .dw 0x51BF ; - .dw 0xED9F ; - .dw 0xA3C7 ; - .dw 0xEDA0 ; - .dw 0x3AFD ; - .dw 0xEDA1 ; - .dw 0x1C09 ; - .dw 0xEDA2 ; - .dw 0x8D41 ; - .dw 0xEDA3 ; - .dw 0x10A3 ; - .dw 0xEDA4 ; - .dw 0x1C05 ; - .dw 0xEDA5 ; - .dw 0x336D ; - .dw 0xEDA6 ; - .dw 0xFF1D ; - .dw 0xEDA7 ; - .dw 0xCBC3 ; - .dw 0xEDA8 ; - .dw 0xB5B3 ; - .dw 0xEDA9 ; - .dw 0xA6D5 ; - .dw 0xEDAA ; - .dw 0xF7F ; - .dw 0xEDAB ; - .dw 0xE0D1 ; - .dw 0xEDAC ; - .dw 0xDE27 ; - .dw 0xEDAD ; - .dw 0x7A5B ; - .dw 0xEDAE ; - .dw 0x9A2D ; - .dw 0xEDAF ; - .dw 0x58CF ; - .dw 0xEDB0 ; - .dw 0x2C73 ; - .dw 0xEDB1 ; - .dw 0xA79B ; - .dw 0xEDB2 ; - .dw 0x4E9D ; - .dw 0xEDB3 ; - .dw 0x7457 ; - .dw 0xEDB4 ; - .dw 0xD275 ; - .dw 0xEDB5 ; - .dw 0xAEB9 ; - .dw 0xEDB6 ; - .dw 0xF98D ; - .dw 0xEDB7 ; - .dw 0x514B ; - .dw 0xEDB8 ; - .dw 0x3C33 ; - .dw 0xEDB9 ; - .dw 0x3EC9 ; - .dw 0xEDBA ; - .dw 0xD01D ; - .dw 0xEDBB ; - .dw 0x3413 ; - .dw 0xEDBC ; - .dw 0x4CB1 ; - .dw 0xEDBD ; - .dw 0xEDCF ; - .dw 0xEDBE ; - .dw 0x546B ; - .dw 0xEDBF ; - .dw 0x2C53 ; - .dw 0xEDC0 ; - .dw 0x9047 ; - .dw 0xEDC1 ; - .dw 0x783B ; - .dw 0xEDC2 ; - .dw 0xEBA3 ; - .dw 0xEDC3 ; - .dw 0x4D21 ; - .dw 0xEDC4 ; - .dw 0x3C7B ; - .dw 0xEDC5 ; - .dw 0x7FD9 ; - .dw 0xEDC6 ; - .dw 0xBD97 ; - .dw 0xEDC7 ; - .dw 0x30BD ; - .dw 0xEDC8 ; - .dw 0x5557 ; - .dw 0xEDC9 ; - .dw 0x424F ; - .dw 0xEDCA ; - .dw 0xF5DF ; - .dw 0xEDCB ; - .dw 0xFFCF ; - .dw 0xEDCC ; - .dw 0xD047 ; - .dw 0xEDCD ; - .dw 0x3F0F ; - .dw 0xEDCE ; - .dw 0xFE6F ; - .dw 0xEDCF ; - .dw 0xB415 ; - .dw 0xEDD0 ; - .dw 0xC65 ; - .dw 0xEDD1 ; - .dw 0x44D5 ; - .dw 0xEDD2 ; - .dw 0xCBA5 ; - .dw 0xEDD3 ; - .dw 0xCEA3 ; - .dw 0xEDD4 ; - .dw 0x785F ; - .dw 0xEDD5 ; - .dw 0xDE9B ; - .dw 0xEDD6 ; - .dw 0xD1F1 ; - .dw 0xEDD7 ; - .dw 0x399B ; - .dw 0xEDD8 ; - .dw 0xBDC5 ; - .dw 0xEDD9 ; - .dw 0x9815 ; - .dw 0xEDDA ; - .dw 0xBCDB ; - .dw 0xEDDB ; - .dw 0x8D5F ; - .dw 0xEDDC ; - .dw 0x49E9 ; - .dw 0xEDDD ; - .dw 0x11A7 ; - .dw 0xEDDE ; - .dw 0x7FAD ; - .dw 0xEDDF ; - .dw 0x714F ; - .dw 0xEDE0 ; - .dw 0x8C2D ; - .dw 0xEDE1 ; - .dw 0x5BD5 ; - .dw 0xEDE2 ; - .dw 0xD77F ; - .dw 0xEDE3 ; - .dw 0x4FF9 ; - .dw 0xEDE4 ; - .dw 0xC1E3 ; - .dw 0xEDE5 ; - .dw 0x924D ; - .dw 0xEDE6 ; - .dw 0xD6D1 ; - .dw 0xEDE7 ; - .dw 0x16E1 ; - .dw 0xEDE8 ; - .dw 0xA7A3 ; - .dw 0xEDE9 ; - .dw 0x2E4D ; - .dw 0xEDEA ; - .dw 0x92A7 ; - .dw 0xEDEB ; - .dw 0x39A3 ; - .dw 0xEDEC ; - .dw 0xE823 ; - .dw 0xEDED ; - .dw 0x8A5 ; - .dw 0xEDEE ; - .dw 0x891D ; - .dw 0xEDEF ; - .dw 0xB0BF ; - .dw 0xEDF0 ; - .dw 0xA089 ; - .dw 0xEDF1 ; - .dw 0x832D ; - .dw 0xEDF2 ; - .dw 0xD981 ; - .dw 0xEDF3 ; - .dw 0x2BC3 ; - .dw 0xEDF4 ; - .dw 0xD251 ; - .dw 0xEDF5 ; - .dw 0xD1BB ; - .dw 0xEDF6 ; - .dw 0xE5ED ; - .dw 0xEDF7 ; - .dw 0x2F0D ; - .dw 0xEDF8 ; - .dw 0x1A97 ; - .dw 0xEDF9 ; - .dw 0xDA9F ; - .dw 0xEDFA ; - .dw 0x7657 ; - .dw 0xEDFB ; - .dw 0x54F9 ; - .dw 0xEDFC ; - .dw 0x86F7 ; - .dw 0xEDFD ; - .dw 0xA697 ; - .dw 0xEDFE ; - .dw 0xF533 ; - .dw 0xEDFF ; - .dw 0x6AA5 ; - .dw 0xEE00 ; - .dw 0xDFDF ; - .dw 0xEE01 ; - .dw 0xD847 ; - .dw 0xEE02 ; - .dw 0xDD85 ; - .dw 0xEE03 ; - .dw 0xA01D ; - .dw 0xEE04 ; - .dw 0x406D ; - .dw 0xEE05 ; - .dw 0x2335 ; - .dw 0xEE06 ; - .dw 0xF27B ; - .dw 0xEE07 ; - .dw 0x841D ; - .dw 0xEE08 ; - .dw 0x53C7 ; - .dw 0xEE09 ; - .dw 0x3A3D ; - .dw 0xEE0A ; - .dw 0x5883 ; - .dw 0xEE0B ; - .dw 0x33F ; - .dw 0xEE0C ; - .dw 0xFED ; - .dw 0xEE0D ; - .dw 0x2D8D ; - .dw 0xEE0E ; - .dw 0x27E7 ; - .dw 0xEE0F ; - .dw 0x22BF ; - .dw 0xEE10 ; - .dw 0x4613 ; - .dw 0xEE11 ; - .dw 0xB015 ; - .dw 0xEE12 ; - .dw 0x90DF ; - .dw 0xEE13 ; - .dw 0xAEA7 ; - .dw 0xEE14 ; - .dw 0xE07F ; - .dw 0xEE15 ; - .dw 0x3C89 ; - .dw 0xEE16 ; - .dw 0x2931 ; - .dw 0xEE17 ; - .dw 0x938F ; - .dw 0xEE18 ; - .dw 0x25D9 ; - .dw 0xEE19 ; - .dw 0x91D5 ; - .dw 0xEE1A ; - .dw 0x7B41 ; - .dw 0xEE1B ; - .dw 0x1BD3 ; - .dw 0xEE1C ; - .dw 0xDA09 ; - .dw 0xEE1D ; - .dw 0x7F11 ; - .dw 0xEE1E ; - .dw 0x6EAD ; - .dw 0xEE1F ; - .dw 0xC849 ; - .dw 0xEE20 ; - .dw 0x948B ; - .dw 0xEE21 ; - .dw 0x7701 ; - .dw 0xEE22 ; - .dw 0xA265 ; - .dw 0xEE23 ; - .dw 0xFC7B ; - .dw 0xEE24 ; - .dw 0x2449 ; - .dw 0xEE25 ; - .dw 0xE305 ; - .dw 0xEE26 ; - .dw 0x5045 ; - .dw 0xEE27 ; - .dw 0x3661 ; - .dw 0xEE28 ; - .dw 0x58F3 ; - .dw 0xEE29 ; - .dw 0xAD93 ; - .dw 0xEE2A ; - .dw 0xD225 ; - .dw 0xEE2B ; - .dw 0x991 ; - .dw 0xEE2C ; - .dw 0x9D3 ; - .dw 0xEE2D ; - .dw 0xFC35 ; - .dw 0xEE2E ; - .dw 0x607D ; - .dw 0xEE2F ; - .dw 0x9603 ; - .dw 0xEE30 ; - .dw 0xB22F ; - .dw 0xEE31 ; - .dw 0x90FD ; - .dw 0xEE32 ; - .dw 0x226F ; - .dw 0xEE33 ; - .dw 0xB23D ; - .dw 0xEE34 ; - .dw 0x7B15 ; - .dw 0xEE35 ; - .dw 0xCB75 ; - .dw 0xEE36 ; - .dw 0x276D ; - .dw 0xEE37 ; - .dw 0x8111 ; - .dw 0xEE38 ; - .dw 0xAB9 ; - .dw 0xEE39 ; - .dw 0xC127 ; - .dw 0xEE3A ; - .dw 0x6249 ; - .dw 0xEE3B ; - .dw 0xAADB ; - .dw 0xEE3C ; - .dw 0xF151 ; - .dw 0xEE3D ; - .dw 0x6587 ; - .dw 0xEE3E ; - .dw 0x3DCB ; - .dw 0xEE3F ; - .dw 0xF229 ; - .dw 0xEE40 ; - .dw 0xB63 ; - .dw 0xEE41 ; - .dw 0x3973 ; - .dw 0xEE42 ; - .dw 0xE2D1 ; - .dw 0xEE43 ; - .dw 0x5C05 ; - .dw 0xEE44 ; - .dw 0xB1A5 ; - .dw 0xEE45 ; - .dw 0x7A29 ; - .dw 0xEE46 ; - .dw 0xC7E1 ; - .dw 0xEE47 ; - .dw 0xA39F ; - .dw 0xEE48 ; - .dw 0xE55 ; - .dw 0xEE49 ; - .dw 0x47BD ; - .dw 0xEE4A ; - .dw 0xA23F ; - .dw 0xEE4B ; - .dw 0x318B ; - .dw 0xEE4C ; - .dw 0x7007 ; - .dw 0xEE4D ; - .dw 0xBB11 ; - .dw 0xEE4E ; - .dw 0x508F ; - .dw 0xEE4F ; - .dw 0x4E7B ; - .dw 0xEE50 ; - .dw 0xF20F ; - .dw 0xEE51 ; - .dw 0x6353 ; - .dw 0xEE52 ; - .dw 0xD6E1 ; - .dw 0xEE53 ; - .dw 0xC975 ; - .dw 0xEE54 ; - .dw 0x5243 ; - .dw 0xEE55 ; - .dw 0x22EF ; - .dw 0xEE56 ; - .dw 0x453 ; - .dw 0xEE57 ; - .dw 0xC985 ; - .dw 0xEE58 ; - .dw 0x4C69 ; - .dw 0xEE59 ; - .dw 0xE403 ; - .dw 0xEE5A ; - .dw 0xDA1F ; - .dw 0xEE5B ; - .dw 0x301 ; - .dw 0xEE5C ; - .dw 0x52FF ; - .dw 0xEE5D ; - .dw 0x1C65 ; - .dw 0xEE5E ; - .dw 0x4C3F ; - .dw 0xEE5F ; - .dw 0x837 ; - .dw 0xEE60 ; - .dw 0xFD97 ; - .dw 0xEE61 ; - .dw 0x990D ; - .dw 0xEE62 ; - .dw 0x7377 ; - .dw 0xEE63 ; - .dw 0xEDA9 ; - .dw 0xEE64 ; - .dw 0x4B3 ; - .dw 0xEE65 ; - .dw 0x8913 ; - .dw 0xEE66 ; - .dw 0xC8FB ; - .dw 0xEE67 ; - .dw 0xF9C5 ; - .dw 0xEE68 ; - .dw 0x231D ; - .dw 0xEE69 ; - .dw 0x4029 ; - .dw 0xEE6A ; - .dw 0x837F ; - .dw 0xEE6B ; - .dw 0x981B ; - .dw 0xEE6C ; - .dw 0xB4B9 ; - .dw 0xEE6D ; - .dw 0xA88F ; - .dw 0xEE6E ; - .dw 0xADCF ; - .dw 0xEE6F ; - .dw 0x4819 ; - .dw 0xEE70 ; - .dw 0x6AE1 ; - .dw 0xEE71 ; - .dw 0xDC8B ; - .dw 0xEE72 ; - .dw 0xEE7 ; - .dw 0xEE73 ; - .dw 0xBF41 ; - .dw 0xEE74 ; - .dw 0xEE3D ; - .dw 0xEE75 ; - .dw 0xDF65 ; - .dw 0xEE76 ; - .dw 0x7B91 ; - .dw 0xEE77 ; - .dw 0xF6DB ; - .dw 0xEE78 ; - .dw 0xC619 ; - .dw 0xEE79 ; - .dw 0xEDDD ; - .dw 0xEE7A ; - .dw 0xA975 ; - .dw 0xEE7B ; - .dw 0x5D37 ; - .dw 0xEE7C ; - .dw 0x5D41 ; - .dw 0xEE7D ; - .dw 0x5E1D ; - .dw 0xEE7E ; - .dw 0x1BB5 ; - .dw 0xEE7F ; - .dw 0xE261 ; - .dw 0xEE80 ; - .dw 0x7C55 ; - .dw 0xEE81 ; - .dw 0x873F ; - .dw 0xEE82 ; - .dw 0x4107 ; - .dw 0xEE83 ; - .dw 0x1859 ; - .dw 0xEE84 ; - .dw 0x11A3 ; - .dw 0xEE85 ; - .dw 0xA833 ; - .dw 0xEE86 ; - .dw 0x5B47 ; - .dw 0xEE87 ; - .dw 0x1EC5 ; - .dw 0xEE88 ; - .dw 0x9E7F ; - .dw 0xEE89 ; - .dw 0x464B ; - .dw 0xEE8A ; - .dw 0x4895 ; - .dw 0xEE8B ; - .dw 0x9233 ; - .dw 0xEE8C ; - .dw 0x2219 ; - .dw 0xEE8D ; - .dw 0xFB1F ; - .dw 0xEE8E ; - .dw 0xC5E9 ; - .dw 0xEE8F ; - .dw 0x36CD ; - .dw 0xEE90 ; - .dw 0xD9D7 ; - .dw 0xEE91 ; - .dw 0x2A13 ; - .dw 0xEE92 ; - .dw 0x432F ; - .dw 0xEE93 ; - .dw 0x968F ; - .dw 0xEE94 ; - .dw 0xAF2F ; - .dw 0xEE95 ; - .dw 0x954B ; - .dw 0xEE96 ; - .dw 0xE0D7 ; - .dw 0xEE97 ; - .dw 0x4B01 ; - .dw 0xEE98 ; - .dw 0xAAF7 ; - .dw 0xEE99 ; - .dw 0x4A21 ; - .dw 0xEE9A ; - .dw 0xAEF9 ; - .dw 0xEE9B ; - .dw 0x2A6B ; - .dw 0xEE9C ; - .dw 0x4649 ; - .dw 0xEE9D ; - .dw 0xDD1F ; - .dw 0xEE9E ; - .dw 0xC5E1 ; - .dw 0xEE9F ; - .dw 0x1099 ; - .dw 0xEEA0 ; - .dw 0xF0CF ; - .dw 0xEEA1 ; - .dw 0x6D77 ; - .dw 0xEEA2 ; - .dw 0x5031 ; - .dw 0xEEA3 ; - .dw 0x7B03 ; - .dw 0xEEA4 ; - .dw 0xA4A3 ; - .dw 0xEEA5 ; - .dw 0x67FB ; - .dw 0xEEA6 ; - .dw 0x1E73 ; - .dw 0xEEA7 ; - .dw 0xB08D ; - .dw 0xEEA8 ; - .dw 0xDFA7 ; - .dw 0xEEA9 ; - .dw 0x818F ; - .dw 0xEEAA ; - .dw 0xDC33 ; - .dw 0xEEAB ; - .dw 0xACC1 ; - .dw 0xEEAC ; - .dw 0xDA55 ; - .dw 0xEEAD ; - .dw 0xE12F ; - .dw 0xEEAE ; - .dw 0x7E91 ; - .dw 0xEEAF ; - .dw 0x8685 ; - .dw 0xEEB0 ; - .dw 0x5421 ; - .dw 0xEEB1 ; - .dw 0xF15B ; - .dw 0xEEB2 ; - .dw 0x467 ; - .dw 0xEEB3 ; - .dw 0x8A51 ; - .dw 0xEEB4 ; - .dw 0xCD49 ; - .dw 0xEEB5 ; - .dw 0xD10F ; - .dw 0xEEB6 ; - .dw 0x1FD5 ; - .dw 0xEEB7 ; - .dw 0xBFE7 ; - .dw 0xEEB8 ; - .dw 0x8635 ; - .dw 0xEEB9 ; - .dw 0xDC43 ; - .dw 0xEEBA ; - .dw 0xE159 ; - .dw 0xEEBB ; - .dw 0x138F ; - .dw 0xEEBC ; - .dw 0x1C45 ; - .dw 0xEEBD ; - .dw 0x43DB ; - .dw 0xEEBE ; - .dw 0xFC71 ; - .dw 0xEEBF ; - .dw 0xDACD ; - .dw 0xEEC0 ; - .dw 0x1C35 ; - .dw 0xEEC1 ; - .dw 0x2D29 ; - .dw 0xEEC2 ; - .dw 0xBDA7 ; - .dw 0xEEC3 ; - .dw 0xEC97 ; - .dw 0xEEC4 ; - .dw 0x61E7 ; - .dw 0xEEC5 ; - .dw 0x50D7 ; - .dw 0xEEC6 ; - .dw 0x4A31 ; - .dw 0xEEC7 ; - .dw 0x50D ; - .dw 0xEEC8 ; - .dw 0x9DC7 ; - .dw 0xEEC9 ; - .dw 0x9169 ; - .dw 0xEECA ; - .dw 0x4105 ; - .dw 0xEECB ; - .dw 0xACB5 ; - .dw 0xEECC ; - .dw 0xD79F ; - .dw 0xEECD ; - .dw 0x8133 ; - .dw 0xEECE ; - .dw 0x5575 ; - .dw 0xEECF ; - .dw 0x5B31 ; - .dw 0xEED0 ; - .dw 0x46EF ; - .dw 0xEED1 ; - .dw 0x4FD1 ; - .dw 0xEED2 ; - .dw 0xFB45 ; - .dw 0xEED3 ; - .dw 0xD75 ; - .dw 0xEED4 ; - .dw 0x58BF ; - .dw 0xEED5 ; - .dw 0x171F ; - .dw 0xEED6 ; - .dw 0xBC3B ; - .dw 0xEED7 ; - .dw 0x77F ; - .dw 0xEED8 ; - .dw 0x3B03 ; - .dw 0xEED9 ; - .dw 0xFFAF ; - .dw 0xEEDA ; - .dw 0x4F4B ; - .dw 0xEEDB ; - .dw 0xF991 ; - .dw 0xEEDC ; - .dw 0xC569 ; - .dw 0xEEDD ; - .dw 0x34C1 ; - .dw 0xEEDE ; - .dw 0x915 ; - .dw 0xEEDF ; - .dw 0x40EF ; - .dw 0xEEE0 ; - .dw 0x17B5 ; - .dw 0xEEE1 ; - .dw 0x1FC3 ; - .dw 0xEEE2 ; - .dw 0xBE17 ; - .dw 0xEEE3 ; - .dw 0x7C07 ; - .dw 0xEEE4 ; - .dw 0xC599 ; - .dw 0xEEE5 ; - .dw 0xE339 ; - .dw 0xEEE6 ; - .dw 0xAE2D ; - .dw 0xEEE7 ; - .dw 0x2A37 ; - .dw 0xEEE8 ; - .dw 0xE80D ; - .dw 0xEEE9 ; - .dw 0x8D45 ; - .dw 0xEEEA ; - .dw 0x91BF ; - .dw 0xEEEB ; - .dw 0x8F01 ; - .dw 0xEEEC ; - .dw 0xEC27 ; - .dw 0xEEED ; - .dw 0xF997 ; - .dw 0xEEEE ; - .dw 0x6047 ; - .dw 0xEEEF ; - .dw 0x90C3 ; - .dw 0xEEF0 ; - .dw 0x776F ; - .dw 0xEEF1 ; - .dw 0xDAE9 ; - .dw 0xEEF2 ; - .dw 0xE873 ; - .dw 0xEEF3 ; - .dw 0xCAEB ; - .dw 0xEEF4 ; - .dw 0x39BD ; - .dw 0xEEF5 ; - .dw 0xE3EF ; - .dw 0xEEF6 ; - .dw 0xD1BB ; - .dw 0xEEF7 ; - .dw 0x8BB7 ; - .dw 0xEEF8 ; - .dw 0x48F ; - .dw 0xEEF9 ; - .dw 0x87D7 ; - .dw 0xEEFA ; - .dw 0x1F79 ; - .dw 0xEEFB ; - .dw 0xF563 ; - .dw 0xEEFC ; - .dw 0xFFE1 ; - .dw 0xEEFD ; - .dw 0x4A41 ; - .dw 0xEEFE ; - .dw 0xCD7F ; - .dw 0xEEFF ; - .dw 0xFAED ; - .dw 0xEF00 ; - .dw 0x5481 ; - .dw 0xEF01 ; - .dw 0x16B3 ; - .dw 0xEF02 ; - .dw 0x9E2F ; - .dw 0xEF03 ; - .dw 0x7041 ; - .dw 0xEF04 ; - .dw 0x23EF ; - .dw 0xEF05 ; - .dw 0x9791 ; - .dw 0xEF06 ; - .dw 0xB21B ; - .dw 0xEF07 ; - .dw 0xE5F9 ; - .dw 0xEF08 ; - .dw 0x25AD ; - .dw 0xEF09 ; - .dw 0x495 ; - .dw 0xEF0A ; - .dw 0x10F ; - .dw 0xEF0B ; - .dw 0x8895 ; - .dw 0xEF0C ; - .dw 0xC21B ; - .dw 0xEF0D ; - .dw 0x60CF ; - .dw 0xEF0E ; - .dw 0x4CB3 ; - .dw 0xEF0F ; - .dw 0xBB29 ; - .dw 0xEF10 ; - .dw 0x2D3 ; - .dw 0xEF11 ; - .dw 0xA00F ; - .dw 0xEF12 ; - .dw 0xA4A3 ; - .dw 0xEF13 ; - .dw 0xA5A5 ; - .dw 0xEF14 ; - .dw 0x3075 ; - .dw 0xEF15 ; - .dw 0xABEB ; - .dw 0xEF16 ; - .dw 0x1403 ; - .dw 0xEF17 ; - .dw 0x6E7F ; - .dw 0xEF18 ; - .dw 0x760B ; - .dw 0xEF19 ; - .dw 0xC02B ; - .dw 0xEF1A ; - .dw 0x9095 ; - .dw 0xEF1B ; - .dw 0x57F3 ; - .dw 0xEF1C ; - .dw 0x61DD ; - .dw 0xEF1D ; - .dw 0x16CB ; - .dw 0xEF1E ; - .dw 0xC35B ; - .dw 0xEF1F ; - .dw 0x78B7 ; - .dw 0xEF20 ; - .dw 0x9BC9 ; - .dw 0xEF21 ; - .dw 0x5B6D ; - .dw 0xEF22 ; - .dw 0xC2A3 ; - .dw 0xEF23 ; - .dw 0x4837 ; - .dw 0xEF24 ; - .dw 0xA915 ; - .dw 0xEF25 ; - .dw 0xDE4D ; - .dw 0xEF26 ; - .dw 0x55A9 ; - .dw 0xEF27 ; - .dw 0xB645 ; - .dw 0xEF28 ; - .dw 0x15D3 ; - .dw 0xEF29 ; - .dw 0xFEC9 ; - .dw 0xEF2A ; - .dw 0xD9A5 ; - .dw 0xEF2B ; - .dw 0x65D ; - .dw 0xEF2C ; - .dw 0xDBAD ; - .dw 0xEF2D ; - .dw 0xC547 ; - .dw 0xEF2E ; - .dw 0x606D ; - .dw 0xEF2F ; - .dw 0x2655 ; - .dw 0xEF30 ; - .dw 0x5E49 ; - .dw 0xEF31 ; - .dw 0x24B7 ; - .dw 0xEF32 ; - .dw 0x2087 ; - .dw 0xEF33 ; - .dw 0xB893 ; - .dw 0xEF34 ; - .dw 0xD515 ; - .dw 0xEF35 ; - .dw 0xDB85 ; - .dw 0xEF36 ; - .dw 0xCEC3 ; - .dw 0xEF37 ; - .dw 0x89C9 ; - .dw 0xEF38 ; - .dw 0x7AA7 ; - .dw 0xEF39 ; - .dw 0x6C1D ; - .dw 0xEF3A ; - .dw 0xF951 ; - .dw 0xEF3B ; - .dw 0xAA33 ; - .dw 0xEF3C ; - .dw 0x5991 ; - .dw 0xEF3D ; - .dw 0x24CF ; - .dw 0xEF3E ; - .dw 0xFC5D ; - .dw 0xEF3F ; - .dw 0xE23F ; - .dw 0xEF40 ; - .dw 0xEBB ; - .dw 0xEF41 ; - .dw 0xAF5D ; - .dw 0xEF42 ; - .dw 0xA823 ; - .dw 0xEF43 ; - .dw 0xBAD7 ; - .dw 0xEF44 ; - .dw 0x593D ; - .dw 0xEF45 ; - .dw 0x1FE1 ; - .dw 0xEF46 ; - .dw 0x3087 ; - .dw 0xEF47 ; - .dw 0xD109 ; - .dw 0xEF48 ; - .dw 0xCFAF ; - .dw 0xEF49 ; - .dw 0xFB51 ; - .dw 0xEF4A ; - .dw 0x7E31 ; - .dw 0xEF4B ; - .dw 0xAD4F ; - .dw 0xEF4C ; - .dw 0x930D ; - .dw 0xEF4D ; - .dw 0x2D71 ; - .dw 0xEF4E ; - .dw 0x7923 ; - .dw 0xEF4F ; - .dw 0xD635 ; - .dw 0xEF50 ; - .dw 0x5703 ; - .dw 0xEF51 ; - .dw 0x664D ; - .dw 0xEF52 ; - .dw 0x64CD ; - .dw 0xEF53 ; - .dw 0x56A1 ; - .dw 0xEF54 ; - .dw 0x97CF ; - .dw 0xEF55 ; - .dw 0xD72F ; - .dw 0xEF56 ; - .dw 0xE5AB ; - .dw 0xEF57 ; - .dw 0x6F85 ; - .dw 0xEF58 ; - .dw 0x5591 ; - .dw 0xEF59 ; - .dw 0xC719 ; - .dw 0xEF5A ; - .dw 0xC85B ; - .dw 0xEF5B ; - .dw 0xAD11 ; - .dw 0xEF5C ; - .dw 0x2D29 ; - .dw 0xEF5D ; - .dw 0xF6BD ; - .dw 0xEF5E ; - .dw 0x2233 ; - .dw 0xEF5F ; - .dw 0x1773 ; - .dw 0xEF60 ; - .dw 0x2689 ; - .dw 0xEF61 ; - .dw 0x4BF5 ; - .dw 0xEF62 ; - .dw 0xE35B ; - .dw 0xEF63 ; - .dw 0xB711 ; - .dw 0xEF64 ; - .dw 0x1095 ; - .dw 0xEF65 ; - .dw 0xBCBB ; - .dw 0xEF66 ; - .dw 0x7265 ; - .dw 0xEF67 ; - .dw 0x2437 ; - .dw 0xEF68 ; - .dw 0xC273 ; - .dw 0xEF69 ; - .dw 0xF19F ; - .dw 0xEF6A ; - .dw 0x6963 ; - .dw 0xEF6B ; - .dw 0x5A55 ; - .dw 0xEF6C ; - .dw 0x1A6B ; - .dw 0xEF6D ; - .dw 0x97BF ; - .dw 0xEF6E ; - .dw 0xC85 ; - .dw 0xEF6F ; - .dw 0x86BB ; - .dw 0xEF70 ; - .dw 0x1231 ; - .dw 0xEF71 ; - .dw 0xDA43 ; - .dw 0xEF72 ; - .dw 0x9225 ; - .dw 0xEF73 ; - .dw 0xAC5 ; - .dw 0xEF74 ; - .dw 0xC0D3 ; - .dw 0xEF75 ; - .dw 0xFB55 ; - .dw 0xEF76 ; - .dw 0xD46B ; - .dw 0xEF77 ; - .dw 0x69A1 ; - .dw 0xEF78 ; - .dw 0xA1FD ; - .dw 0xEF79 ; - .dw 0x8491 ; - .dw 0xEF7A ; - .dw 0x8463 ; - .dw 0xEF7B ; - .dw 0x597D ; - .dw 0xEF7C ; - .dw 0xFAD7 ; - .dw 0xEF7D ; - .dw 0x705 ; - .dw 0xEF7E ; - .dw 0x768D ; - .dw 0xEF7F ; - .dw 0xB045 ; - .dw 0xEF80 ; - .dw 0xB463 ; - .dw 0xEF81 ; - .dw 0xE2A7 ; - .dw 0xEF82 ; - .dw 0x20FF ; - .dw 0xEF83 ; - .dw 0x63D7 ; - .dw 0xEF84 ; - .dw 0x834F ; - .dw 0xEF85 ; - .dw 0xD4B ; - .dw 0xEF86 ; - .dw 0xE2F3 ; - .dw 0xEF87 ; - .dw 0x55BD ; - .dw 0xEF88 ; - .dw 0xB54F ; - .dw 0xEF89 ; - .dw 0x511F ; - .dw 0xEF8A ; - .dw 0x2DED ; - .dw 0xEF8B ; - .dw 0x2265 ; - .dw 0xEF8C ; - .dw 0x7BF5 ; - .dw 0xEF8D ; - .dw 0xFA9D ; - .dw 0xEF8E ; - .dw 0x2843 ; - .dw 0xEF8F ; - .dw 0xABD5 ; - .dw 0xEF90 ; - .dw 0xD03 ; - .dw 0xEF91 ; - .dw 0x6E0B ; - .dw 0xEF92 ; - .dw 0xE13F ; - .dw 0xEF93 ; - .dw 0x97E9 ; - .dw 0xEF94 ; - .dw 0x7051 ; - .dw 0xEF95 ; - .dw 0x9C69 ; - .dw 0xEF96 ; - .dw 0xAEB5 ; - .dw 0xEF97 ; - .dw 0x7A0D ; - .dw 0xEF98 ; - .dw 0x5315 ; - .dw 0xEF99 ; - .dw 0xCFF5 ; - .dw 0xEF9A ; - .dw 0xCC19 ; - .dw 0xEF9B ; - .dw 0xE069 ; - .dw 0xEF9C ; - .dw 0xB8C9 ; - .dw 0xEF9D ; - .dw 0xC815 ; - .dw 0xEF9E ; - .dw 0xD31B ; - .dw 0xEF9F ; - .dw 0xFCA3 ; - .dw 0xEFA0 ; - .dw 0xE179 ; - .dw 0xEFA1 ; - .dw 0x9CDF ; - .dw 0xEFA2 ; - .dw 0x25BB ; - .dw 0xEFA3 ; - .dw 0x2019 ; - .dw 0xEFA4 ; - .dw 0x3D9B ; - .dw 0xEFA5 ; - .dw 0x61FF ; - .dw 0xEFA6 ; - .dw 0xE1E3 ; - .dw 0xEFA7 ; - .dw 0xC38D ; - .dw 0xEFA8 ; - .dw 0xC773 ; - .dw 0xEFA9 ; - .dw 0x141 ; - .dw 0xEFAA ; - .dw 0x767D ; - .dw 0xEFAB ; - .dw 0x5269 ; - .dw 0xEFAC ; - .dw 0x99DB ; - .dw 0xEFAD ; - .dw 0x447D ; - .dw 0xEFAE ; - .dw 0x720D ; - .dw 0xEFAF ; - .dw 0x7173 ; - .dw 0xEFB0 ; - .dw 0x1CA7 ; - .dw 0xEFB1 ; - .dw 0x8711 ; - .dw 0xEFB2 ; - .dw 0xA2CB ; - .dw 0xEFB3 ; - .dw 0xF903 ; - .dw 0xEFB4 ; - .dw 0x9E77 ; - .dw 0xEFB5 ; - .dw 0x6DB ; - .dw 0xEFB6 ; - .dw 0x2035 ; - .dw 0xEFB7 ; - .dw 0x5ABB ; - .dw 0xEFB8 ; - .dw 0xB40F ; - .dw 0xEFB9 ; - .dw 0x4CB5 ; - .dw 0xEFBA ; - .dw 0x562D ; - .dw 0xEFBB ; - .dw 0xAAC3 ; - .dw 0xEFBC ; - .dw 0x3531 ; - .dw 0xEFBD ; - .dw 0xA461 ; - .dw 0xEFBE ; - .dw 0xA98F ; - .dw 0xEFBF ; - .dw 0x47F ; - .dw 0xEFC0 ; - .dw 0x2EF9 ; - .dw 0xEFC1 ; - .dw 0x1C0F ; - .dw 0xEFC2 ; - .dw 0xCE43 ; - .dw 0xEFC3 ; - .dw 0x82C5 ; - .dw 0xEFC4 ; - .dw 0xA3A9 ; - .dw 0xEFC5 ; - .dw 0x34B ; - .dw 0xEFC6 ; - .dw 0x66E3 ; - .dw 0xEFC7 ; - .dw 0x8395 ; - .dw 0xEFC8 ; - .dw 0x700D ; - .dw 0xEFC9 ; - .dw 0x6179 ; - .dw 0xEFCA ; - .dw 0x5C3 ; - .dw 0xEFCB ; - .dw 0x6F55 ; - .dw 0xEFCC ; - .dw 0x2E51 ; - .dw 0xEFCD ; - .dw 0x5BCF ; - .dw 0xEFCE ; - .dw 0x2795 ; - .dw 0xEFCF ; - .dw 0xBB87 ; - .dw 0xEFD0 ; - .dw 0x6E4F ; - .dw 0xEFD1 ; - .dw 0x2C7 ; - .dw 0xEFD2 ; - .dw 0x3F7B ; - .dw 0xEFD3 ; - .dw 0x60FD ; - .dw 0xEFD4 ; - .dw 0x1B77 ; - .dw 0xEFD5 ; - .dw 0x7F1B ; - .dw 0xEFD6 ; - .dw 0x6C9F ; - .dw 0xEFD7 ; - .dw 0x7D99 ; - .dw 0xEFD8 ; - .dw 0x6817 ; - .dw 0xEFD9 ; - .dw 0x163F ; - .dw 0xEFDA ; - .dw 0xF151 ; - .dw 0xEFDB ; - .dw 0x597D ; - .dw 0xEFDC ; - .dw 0x163F ; - .dw 0xEFDD ; - .dw 0xFE55 ; - .dw 0xEFDE ; - .dw 0x395 ; - .dw 0xEFDF ; - .dw 0x87C7 ; - .dw 0xEFE0 ; - .dw 0x7615 ; - .dw 0xEFE1 ; - .dw 0x79A7 ; - .dw 0xEFE2 ; - .dw 0xF45 ; - .dw 0xEFE3 ; - .dw 0x5ACB ; - .dw 0xEFE4 ; - .dw 0xF1A7 ; - .dw 0xEFE5 ; - .dw 0x319B ; - .dw 0xEFE6 ; - .dw 0x1A3 ; - .dw 0xEFE7 ; - .dw 0x63C5 ; - .dw 0xEFE8 ; - .dw 0x7E4F ; - .dw 0xEFE9 ; - .dw 0x4935 ; - .dw 0xEFEA ; - .dw 0xB66F ; - .dw 0xEFEB ; - .dw 0x3617 ; - .dw 0xEFEC ; - .dw 0xCB83 ; - .dw 0xEFED ; - .dw 0x1F03 ; - .dw 0xEFEE ; - .dw 0x1E89 ; - .dw 0xEFEF ; - .dw 0x25FF ; - .dw 0xEFF0 ; - .dw 0x872B ; - .dw 0xEFF1 ; - .dw 0x369D ; - .dw 0xEFF2 ; - .dw 0x37FB ; - .dw 0xEFF3 ; - .dw 0x3ACB ; - .dw 0xEFF4 ; - .dw 0x8F81 ; - .dw 0xEFF5 ; - .dw 0x4199 ; - .dw 0xEFF6 ; - .dw 0x6FA1 ; - .dw 0xEFF7 ; - .dw 0xC99 ; - .dw 0xEFF8 ; - .dw 0x6A5F ; - .dw 0xEFF9 ; - .dw 0xC007 ; - .dw 0xEFFA ; - .dw 0x8433 ; - .dw 0xEFFB ; - .dw 0xC585 ; - .dw 0xEFFC ; - .dw 0xDA23 ; - .dw 0xEFFD ; - .dw 0x3065 ; - .dw 0xEFFE ; - .dw 0x82E1 ; - .dw 0xEFFF ; - .dw 0xFE6D ; - .dw 0xC700 ; - .dw 0xE7FB ; - .dw 0xC701 ; - .dw 0x4717 ; - .dw 0xC702 ; - .dw 0xF573 ; - .dw 0xC703 ; - .dw 0xAF1D ; - .dw 0xC704 ; - .dw 0x3BC7 ; - .dw 0xC705 ; - .dw 0x2563 ; - .dw 0xC706 ; - .dw 0xD9D3 ; - .dw 0xC707 ; - .dw 0xEA0F ; - .dw 0xC708 ; - .dw 0x1969 ; - .dw 0xC709 ; - .dw 0x7E5 ; - .dw 0xC70A ; - .dw 0x7B31 ; - .dw 0xC70B ; - .dw 0x9BA1 ; - .dw 0xC70C ; - .dw 0xDBA3 ; - .dw 0xC70D ; - .dw 0x6489 ; - .dw 0xC70E ; - .dw 0xC499 ; - .dw 0xC70F ; - .dw 0x4CD ; - .dw 0xC710 ; - .dw 0x446B ; - .dw 0xC711 ; - .dw 0xF003 ; - .dw 0xC712 ; - .dw 0x24FF ; - .dw 0xC713 ; - .dw 0x295D ; - .dw 0xC714 ; - .dw 0x7AC3 ; - .dw 0xC715 ; - .dw 0x82C5 ; - .dw 0xC716 ; - .dw 0x9CED ; - .dw 0xC717 ; - .dw 0xE9A9 ; - .dw 0xC718 ; - .dw 0xE15 ; - .dw 0xC719 ; - .dw 0x557B ; - .dw 0xC71A ; - .dw 0xD83 ; - .dw 0xC71B ; - .dw 0xFFCD ; - .dw 0xC71C ; - .dw 0xD70B ; - .dw 0xC71D ; - .dw 0x8CFD ; - .dw 0xC71E ; - .dw 0x6121 ; - .dw 0xC71F ; - .dw 0x985F ; - .dw 0xC720 ; - .dw 0xDDD ; - .dw 0xC721 ; - .dw 0x8DCF ; - .dw 0xC722 ; - .dw 0xA579 ; - .dw 0xC723 ; - .dw 0xBEA9 ; - .dw 0xC724 ; - .dw 0x6E39 ; - .dw 0xC725 ; - .dw 0xF0F ; - .dw 0xC726 ; - .dw 0xAF23 ; - .dw 0xC727 ; - .dw 0x5461 ; - .dw 0xC728 ; - .dw 0xC08B ; - .dw 0xC729 ; - .dw 0x64F9 ; - .dw 0xC72A ; - .dw 0x5EBB ; - .dw 0xC72B ; - .dw 0xCCE3 ; - .dw 0xC72C ; - .dw 0xA0E1 ; - .dw 0xC72D ; - .dw 0xFAD1 ; - .dw 0xC72E ; - .dw 0x1F75 ; - .dw 0xC72F ; - .dw 0x63DF ; - .dw 0xC730 ; - .dw 0xDB3D ; - .dw 0xC731 ; - .dw 0x7469 ; - .dw 0xC732 ; - .dw 0xB735 ; - .dw 0xC733 ; - .dw 0x7A1 ; - .dw 0xC734 ; - .dw 0x356F ; - .dw 0xC735 ; - .dw 0x6F0F ; - .dw 0xC736 ; - .dw 0x2F ; - .dw 0xC737 ; - .dw 0xAEB9 ; - .dw 0xC738 ; - .dw 0xFE6D ; - .dw 0xC739 ; - .dw 0x5A0B ; - .dw 0xC73A ; - .dw 0xA3F1 ; - .dw 0xC73B ; - .dw 0x5143 ; - .dw 0xC73C ; - .dw 0x3B29 ; - .dw 0xC73D ; - .dw 0x5E91 ; - .dw 0xC73E ; - .dw 0x7007 ; - .dw 0xC73F ; - .dw 0x3D8D ; - .dw 0xC740 ; - .dw 0xC8EB ; - .dw 0xC741 ; - .dw 0xCF3F ; - .dw 0xC742 ; - .dw 0x5C0B ; - .dw 0xC743 ; - .dw 0x61 ; - .dw 0xC744 ; - .dw 0x4D2B ; - .dw 0xC745 ; - .dw 0x1713 ; - .dw 0xC746 ; - .dw 0xD945 ; - .dw 0xC747 ; - .dw 0x98AD ; - .dw 0xC748 ; - .dw 0x4AE3 ; - .dw 0xC749 ; - .dw 0x9FDF ; - .dw 0xC74A ; - .dw 0x83BB ; - .dw 0xC74B ; - .dw 0x2EC9 ; - .dw 0xC74C ; - .dw 0x356B ; - .dw 0xC74D ; - .dw 0xA84B ; - .dw 0xC74E ; - .dw 0xCCCD ; - .dw 0xC74F ; - .dw 0x727 ; - .dw 0xC750 ; - .dw 0xD8D1 ; - .dw 0xC751 ; - .dw 0x813F ; - .dw 0xC752 ; - .dw 0xB74F ; - .dw 0xC753 ; - .dw 0xE887 ; - .dw 0xC754 ; - .dw 0xEFB3 ; - .dw 0xC755 ; - .dw 0x2AE7 ; - .dw 0xC756 ; - .dw 0x3D1B ; - .dw 0xC757 ; - .dw 0xADBB ; - .dw 0xC758 ; - .dw 0x3E93 ; - .dw 0xC759 ; - .dw 0xC925 ; - .dw 0xC75A ; - .dw 0x762D ; - .dw 0xC75B ; - .dw 0x3AD7 ; - .dw 0xC75C ; - .dw 0xCAB ; - .dw 0xC75D ; - .dw 0xE78D ; - .dw 0xC75E ; - .dw 0x193F ; - .dw 0xC75F ; - .dw 0x8DE9 ; - .dw 0xC760 ; - .dw 0x5255 ; - .dw 0xC761 ; - .dw 0x4D7 ; - .dw 0xC762 ; - .dw 0x6DD7 ; - .dw 0xC763 ; - .dw 0x2333 ; - .dw 0xC764 ; - .dw 0x74CF ; - .dw 0xC765 ; - .dw 0x5DDB ; - .dw 0xC766 ; - .dw 0x47E5 ; - .dw 0xC767 ; - .dw 0x64E1 ; - .dw 0xC768 ; - .dw 0xE7A1 ; - .dw 0xC769 ; - .dw 0x700B ; - .dw 0xC76A ; - .dw 0x24E1 ; - .dw 0xC76B ; - .dw 0x5E49 ; - .dw 0xC76C ; - .dw 0x8B73 ; - .dw 0xC76D ; - .dw 0x2B65 ; - .dw 0xC76E ; - .dw 0x253 ; - .dw 0xC76F ; - .dw 0x6A93 ; - .dw 0xC770 ; - .dw 0x225B ; - .dw 0xC771 ; - .dw 0x4BF5 ; - .dw 0xC772 ; - .dw 0x5F9 ; - .dw 0xC773 ; - .dw 0x1701 ; - .dw 0xC774 ; - .dw 0xB1C3 ; - .dw 0xC775 ; - .dw 0xD2BD ; - .dw 0xC776 ; - .dw 0x8F5D ; - .dw 0xC777 ; - .dw 0xF09F ; - .dw 0xC778 ; - .dw 0x29B7 ; - .dw 0xC779 ; - .dw 0x163D ; - .dw 0xC77A ; - .dw 0xCAE9 ; - .dw 0xC77B ; - .dw 0x757B ; - .dw 0xC77C ; - .dw 0x29C5 ; - .dw 0xC77D ; - .dw 0x6263 ; - .dw 0xC77E ; - .dw 0x5E7D ; - .dw 0xC77F ; - .dw 0xE161 ; - .dw 0xC780 ; - .dw 0x3B49 ; - .dw 0xC781 ; - .dw 0xA005 ; - .dw 0xC782 ; - .dw 0x478D ; - .dw 0xC783 ; - .dw 0xE0F ; - .dw 0xC784 ; - .dw 0x5955 ; - .dw 0xC785 ; - .dw 0xFBD9 ; - .dw 0xC786 ; - .dw 0x82B7 ; - .dw 0xC787 ; - .dw 0x1EEF ; - .dw 0xC788 ; - .dw 0x1DF9 ; - .dw 0xC789 ; - .dw 0x4E9 ; - .dw 0xC78A ; - .dw 0x94DD ; - .dw 0xC78B ; - .dw 0x304D ; - .dw 0xC78C ; - .dw 0x6D27 ; - .dw 0xC78D ; - .dw 0x3A93 ; - .dw 0xC78E ; - .dw 0x8DB3 ; - .dw 0xC78F ; - .dw 0xC213 ; - .dw 0xC790 ; - .dw 0xF507 ; - .dw 0xC791 ; - .dw 0x81F9 ; - .dw 0xC792 ; - .dw 0x9BE7 ; - .dw 0xC793 ; - .dw 0x15FD ; - .dw 0xC794 ; - .dw 0x5BCB ; - .dw 0xC795 ; - .dw 0x7AFF ; - .dw 0xC796 ; - .dw 0xCAA9 ; - .dw 0xC797 ; - .dw 0x3951 ; - .dw 0xC798 ; - .dw 0x730D ; - .dw 0xC799 ; - .dw 0x2CBF ; - .dw 0xC79A ; - .dw 0xD3 ; - .dw 0xC79B ; - .dw 0xF21D ; - .dw 0xC79C ; - .dw 0x48A3 ; - .dw 0xC79D ; - .dw 0x183 ; - .dw 0xC79E ; - .dw 0xD96D ; - .dw 0xC79F ; - .dw 0x47E7 ; - .dw 0xC7A0 ; - .dw 0x6CF9 ; - .dw 0xC7A1 ; - .dw 0x8A3D ; - .dw 0xC7A2 ; - .dw 0x6DDD ; - .dw 0xC7A3 ; - .dw 0xDFE7 ; - .dw 0xC7A4 ; - .dw 0x46EB ; - .dw 0xC7A5 ; - .dw 0x17D ; - .dw 0xC7A6 ; - .dw 0xA96B ; - .dw 0xC7A7 ; - .dw 0xE4C5 ; - .dw 0xC7A8 ; - .dw 0xCD17 ; - .dw 0xC7A9 ; - .dw 0x5ED ; - .dw 0xC7AA ; - .dw 0x3E5F ; - .dw 0xC7AB ; - .dw 0xB1C9 ; - .dw 0xC7AC ; - .dw 0x7CBB ; - .dw 0xC7AD ; - .dw 0x8443 ; - .dw 0xC7AE ; - .dw 0xD4A1 ; - .dw 0xC7AF ; - .dw 0xF999 ; - .dw 0xC7B0 ; - .dw 0xE607 ; - .dw 0xC7B1 ; - .dw 0x48BF ; - .dw 0xC7B2 ; - .dw 0x89C7 ; - .dw 0xC7B3 ; - .dw 0xA06D ; - .dw 0xC7B4 ; - .dw 0xA5FD ; - .dw 0xC7B5 ; - .dw 0x3021 ; - .dw 0xC7B6 ; - .dw 0x5AAF ; - .dw 0xC7B7 ; - .dw 0x1C7 ; - .dw 0xC7B8 ; - .dw 0x25C1 ; - .dw 0xC7B9 ; - .dw 0x701F ; - .dw 0xC7BA ; - .dw 0x8E99 ; - .dw 0xC7BB ; - .dw 0xD9AF ; - .dw 0xC7BC ; - .dw 0xF775 ; - .dw 0xC7BD ; - .dw 0xEF5D ; - .dw 0xC7BE ; - .dw 0xBBC3 ; - .dw 0xC7BF ; - .dw 0x8969 ; - .dw 0xC7C0 ; - .dw 0x2895 ; - .dw 0xC7C1 ; - .dw 0x24ED ; - .dw 0xC7C2 ; - .dw 0x7D79 ; - .dw 0xC7C3 ; - .dw 0xEFA9 ; - .dw 0xC7C4 ; - .dw 0x61C3 ; - .dw 0xC7C5 ; - .dw 0x7737 ; - .dw 0xC7C6 ; - .dw 0x73AD ; - .dw 0xC7C7 ; - .dw 0x8C53 ; - .dw 0xC7C8 ; - .dw 0x2C2D ; - .dw 0xC7C9 ; - .dw 0x9283 ; - .dw 0xC7CA ; - .dw 0xA419 ; - .dw 0xC7CB ; - .dw 0x27AD ; - .dw 0xC7CC ; - .dw 0x345B ; - .dw 0xC7CD ; - .dw 0xAEE3 ; - .dw 0xC7CE ; - .dw 0xD4CB ; - .dw 0xC7CF ; - .dw 0xB513 ; - .dw 0xC7D0 ; - .dw 0xE289 ; - .dw 0xC7D1 ; - .dw 0x3DB5 ; - .dw 0xC7D2 ; - .dw 0xF849 ; - .dw 0xC7D3 ; - .dw 0xA93F ; - .dw 0xC7D4 ; - .dw 0x2087 ; - .dw 0xC7D5 ; - .dw 0xF68F ; - .dw 0xC7D6 ; - .dw 0x431B ; - .dw 0xC7D7 ; - .dw 0x7BEB ; - .dw 0xC7D8 ; - .dw 0xA503 ; - .dw 0xC7D9 ; - .dw 0xBBC9 ; - .dw 0xC7DA ; - .dw 0x2F1 ; - .dw 0xC7DB ; - .dw 0x8D1F ; - .dw 0xC7DC ; - .dw 0x9C6F ; - .dw 0xC7DD ; - .dw 0x4E61 ; - .dw 0xC7DE ; - .dw 0xCF2F ; - .dw 0xC7DF ; - .dw 0x25D7 ; - .dw 0xC7E0 ; - .dw 0x74B ; - .dw 0xC7E1 ; - .dw 0x4983 ; - .dw 0xC7E2 ; - .dw 0x2B0D ; - .dw 0xC7E3 ; - .dw 0xCC47 ; - .dw 0xC7E4 ; - .dw 0xA60D ; - .dw 0xC7E5 ; - .dw 0x5D77 ; - .dw 0xC7E6 ; - .dw 0x312F ; - .dw 0xC7E7 ; - .dw 0xA38B ; - .dw 0xC7E8 ; - .dw 0xCA6B ; - .dw 0xC7E9 ; - .dw 0x421D ; - .dw 0xC7EA ; - .dw 0x60B7 ; - .dw 0xC7EB ; - .dw 0xEE7 ; - .dw 0xC7EC ; - .dw 0xE637 ; - .dw 0xC7ED ; - .dw 0x58E7 ; - .dw 0xC7EE ; - .dw 0x23E1 ; - .dw 0xC7EF ; - .dw 0x5073 ; - .dw 0xC7F0 ; - .dw 0x2FC1 ; - .dw 0xC7F1 ; - .dw 0x7649 ; - .dw 0xC7F2 ; - .dw 0x281D ; - .dw 0xC7F3 ; - .dw 0x5B63 ; - .dw 0xC7F4 ; - .dw 0x339B ; - .dw 0xC7F5 ; - .dw 0xCABD ; - .dw 0xC7F6 ; - .dw 0x1FA1 ; - .dw 0xC7F7 ; - .dw 0x91B3 ; - .dw 0xC7F8 ; - .dw 0xAC07 ; - .dw 0xC7F9 ; - .dw 0x632F ; - .dw 0xC7FA ; - .dw 0x485 ; - .dw 0xC7FB ; - .dw 0xA55F ; - .dw 0xC7FC ; - .dw 0x75BD ; - .dw 0xC7FD ; - .dw 0x38FF ; - .dw 0xC7FE ; - .dw 0x755D ; - .dw 0xC7FF ; - .dw 0x5523 ; - .dw 0xE0C0 ; - .dw 0x0000 ; - .dw 0xE0A0 ; - .dw 0x8000 ; - .dw 0xE1A0 ; - .dw 0x0 ; - .dw 0xC401 ; - .dw 0x4000 ; - .dw 0xC404 ; - .dw 0xC000 ; - .dw 0xC406 ; - .dw 0xC000 ; - .dw 0xC407 ; - .dw 0xC000 ; - .dw 0xC40A ; - .dw 0x8000 ; - .dw 0xC40A ; - .dw 0xC000 ; - .dw 0xC40C ; - .dw 0x8000 ; - .dw 0xC40E ; - .dw 0x8000 ; - .dw 0xC40F ; - .dw 0x0 ; - .dw 0xC40F ; - .dw 0x4000 ; - .dw 0xC40F ; - .dw 0x8000 ; - .dw 0xC410 ; - .dw 0x8000 ; - .dw 0xC411 ; - .dw 0x8000 ; - .dw 0xC411 ; - .dw 0xC000 ; - .dw 0xC412 ; - .dw 0x4000 ; - .dw 0xC412 ; - .dw 0x8000 ; - .dw 0xC413 ; - .dw 0x0 ; - .dw 0xC413 ; - .dw 0x4000 ; - .dw 0xC413 ; - .dw 0x8000 ; - .dw 0xC413 ; - .dw 0xC000 ; - .dw 0xC414 ; - .dw 0x8000 ; - .dw 0xC414 ; - .dw 0xC000 ; - .dw 0xC415 ; - .dw 0x8000 ; - .dw 0xC415 ; - .dw 0xC000 ; - .dw 0xC418 ; - .dw 0x8000 ; - .dw 0xC418 ; - .dw 0xC000 ; - .dw 0xC417 ; - .dw 0x4000 ; - .dw 0xC417 ; - .dw 0x8000 ; - .dw 0xC417 ; - .dw 0xC000 ; - .dw 0xC419 ; - .dw 0x0 ; - .dw 0xC419 ; - .dw 0x4000 ; - .dw 0xC419 ; - .dw 0x8000 ; - .dw 0xC419 ; - .dw 0xC000 ; - .dw 0xC41A ; - .dw 0x0 ; - .dw 0xC41A ; - .dw 0x4000 ; - .dw 0xC41A ; - .dw 0x8000 ; - .dw 0xC41A ; - .dw 0xC000 ; - .dw 0xC41B ; - .dw 0x0 ; - .dw 0xC41B ; - .dw 0x4000 ; - .dw 0xC41B ; - .dw 0x8000 ; - .dw 0xC41B ; - .dw 0xC000 ; - .dw 0xC41C ; - .dw 0x0 ; - .dw 0xC41C ; - .dw 0x4000 ; - .dw 0xC41C ; - .dw 0x8000 ; - .dw 0xC41C ; - .dw 0xC000 ; - .dw 0xC41D ; - .dw 0x0 ; - .dw 0xC41D ; - .dw 0x4000 ; - .dw 0xC41D ; - .dw 0x8000 ; - .dw 0xC41D ; - .dw 0xC000 ; - .dw 0xC41E ; - .dw 0x0 ; - .dw 0xC41E ; - .dw 0x4000 ; - .dw 0xC41E ; - .dw 0x8000 ; - .dw 0xC41E ; - .dw 0xC000 ; - .dw 0xC41F ; - .dw 0x0 ; - .dw 0xC41F ; - .dw 0x4000 ; - .dw 0xC41F ; - .dw 0x8000 ; - .dw 0xC41F ; - .dw 0xC000 ; - .dw 0xC401 ; - .dw 0x0 ; - .dw 0xC401 ; - .dw 0x240 ; - .dw 0xC401 ; - .dw 0x480 ; - .dw 0xC401 ; - .dw 0x6C0 ; - .dw 0xC401 ; - .dw 0x900 ; - .dw 0xC401 ; - .dw 0xB40 ; - .dw 0xC401 ; - .dw 0xD80 ; - .dw 0xC401 ; - .dw 0xFC0 ; - .dw 0xC401 ; - .dw 0x8000 ; - .dw 0xC401 ; - .dw 0x8240 ; - .dw 0xC401 ; - .dw 0x8480 ; - .dw 0xC401 ; - .dw 0x86C0 ; - .dw 0xC401 ; - .dw 0x8900 ; - .dw 0xC401 ; - .dw 0x8B40 ; - .dw 0xC401 ; - .dw 0x8D80 ; - .dw 0xC401 ; - .dw 0x8FC0 ; - .dw 0xC401 ; - .dw 0xC000 ; - .dw 0xC401 ; - .dw 0xC240 ; - .dw 0xC401 ; - .dw 0xC480 ; - .dw 0xC401 ; - .dw 0xC6C0 ; - .dw 0xC401 ; - .dw 0xC900 ; - .dw 0xC401 ; - .dw 0xCB40 ; - .dw 0xC401 ; - .dw 0xCD80 ; - .dw 0xC401 ; - .dw 0xCFC0 ; - .dw 0xC404 ; - .dw 0x8000 ; - .dw 0xC404 ; - .dw 0x8240 ; - .dw 0xC404 ; - .dw 0x8480 ; - .dw 0xC404 ; - .dw 0x86C0 ; - .dw 0xC404 ; - .dw 0x8900 ; - .dw 0xC404 ; - .dw 0x8B40 ; - .dw 0xC404 ; - .dw 0x8D80 ; - .dw 0xC404 ; - .dw 0x8FC0 ; - .dw 0xC40C ; - .dw 0x4000 ; - .dw 0xC40C ; - .dw 0x4240 ; - .dw 0xC40C ; - .dw 0x4480 ; - .dw 0xC40C ; - .dw 0x46C0 ; - .dw 0xC40C ; - .dw 0x4900 ; - .dw 0xC40C ; - .dw 0x4B40 ; - .dw 0xC40C ; - .dw 0x4D80 ; - .dw 0xC40C ; - .dw 0x4FC0 ; - .dw 0xC40D ; - .dw 0x0 ; - .dw 0xC40D ; - .dw 0x240 ; - .dw 0xC40D ; - .dw 0x480 ; - .dw 0xC40D ; - .dw 0x6C0 ; - .dw 0xC40D ; - .dw 0x900 ; - .dw 0xC40D ; - .dw 0xB40 ; - .dw 0xC40D ; - .dw 0xD80 ; - .dw 0xC40D ; - .dw 0xFC0 ; - .dw 0xC40D ; - .dw 0x4000 ; - .dw 0xC40D ; - .dw 0x4240 ; - .dw 0xC40D ; - .dw 0x4480 ; - .dw 0xC40D ; - .dw 0x46C0 ; - .dw 0xC40D ; - .dw 0x4900 ; - .dw 0xC40D ; - .dw 0x4B40 ; - .dw 0xC40D ; - .dw 0x4D80 ; - .dw 0xC40D ; - .dw 0x4FC0 ; - .dw 0xC40D ; - .dw 0x8000 ; - .dw 0xC40D ; - .dw 0x8240 ; - .dw 0xC40D ; - .dw 0x8480 ; - .dw 0xC40D ; - .dw 0x86C0 ; - .dw 0xC40D ; - .dw 0x8900 ; - .dw 0xC40D ; - .dw 0x8B40 ; - .dw 0xC40D ; - .dw 0x8D80 ; - .dw 0xC40D ; - .dw 0x8FC0 ; - .dw 0xC40D ; - .dw 0xC000 ; - .dw 0xC40D ; - .dw 0xC240 ; - .dw 0xC40D ; - .dw 0xC480 ; - .dw 0xC40D ; - .dw 0xC6C0 ; - .dw 0xC40D ; - .dw 0xC900 ; - .dw 0xC40D ; - .dw 0xCB40 ; - .dw 0xC40D ; - .dw 0xCD80 ; - .dw 0xC40D ; - .dw 0xCFC0 ; - .dw 0xC411 ; - .dw 0x0 ; - .dw 0xC411 ; - .dw 0x240 ; - .dw 0xC411 ; - .dw 0x480 ; - .dw 0xC411 ; - .dw 0x6C0 ; - .dw 0xC411 ; - .dw 0x900 ; - .dw 0xC411 ; - .dw 0xB40 ; - .dw 0xC411 ; - .dw 0xD80 ; - .dw 0xC411 ; - .dw 0xFC0 ; - .dw 0xC411 ; - .dw 0x4000 ; - .dw 0xC411 ; - .dw 0x4240 ; - .dw 0xC411 ; - .dw 0x4480 ; - .dw 0xC411 ; - .dw 0x46C0 ; - .dw 0xC411 ; - .dw 0x4900 ; - .dw 0xC411 ; - .dw 0x4B40 ; - .dw 0xC411 ; - .dw 0x4D80 ; - .dw 0xC411 ; - .dw 0x4FC0 ; - .dw 0xC415 ; - .dw 0x0 ; - .dw 0xC415 ; - .dw 0x240 ; - .dw 0xC415 ; - .dw 0x480 ; - .dw 0xC415 ; - .dw 0x6C0 ; - .dw 0xC415 ; - .dw 0x900 ; - .dw 0xC415 ; - .dw 0xB40 ; - .dw 0xC415 ; - .dw 0xD80 ; - .dw 0xC415 ; - .dw 0xFC0 ; - .dw 0xC415 ; - .dw 0x4000 ; - .dw 0xC415 ; - .dw 0x4240 ; - .dw 0xC415 ; - .dw 0x4480 ; - .dw 0xC415 ; - .dw 0x46C0 ; - .dw 0xC415 ; - .dw 0x4900 ; - .dw 0xC415 ; - .dw 0x4B40 ; - .dw 0xC415 ; - .dw 0x4D80 ; - .dw 0xC415 ; - .dw 0x4FC0 ; - .dw 0xC418 ; - .dw 0x4000 ; - .dw 0xC418 ; - .dw 0x4240 ; - .dw 0xC418 ; - .dw 0x4480 ; - .dw 0xC418 ; - .dw 0x46C0 ; - .dw 0xC418 ; - .dw 0x4900 ; - .dw 0xC418 ; - .dw 0x4B40 ; - .dw 0xC418 ; - .dw 0x4D80 ; - .dw 0xC418 ; - .dw 0x4FC0 ; - .dw 0xC412 ; - .dw 0x9 ; - .dw 0xC412 ; - .dw 0x1B ; - .dw 0xC412 ; - .dw 0x24 ; - .dw 0xC412 ; - .dw 0x2D ; - .dw 0xC412 ; - .dw 0x36 ; - .dw 0xC412 ; - .dw 0x3F ; - .dw 0xC414 ; - .dw 0x9 ; - .dw 0xC414 ; - .dw 0x1B ; - .dw 0xC414 ; - .dw 0x24 ; - .dw 0xC414 ; - .dw 0x2D ; - .dw 0xC414 ; - .dw 0x36 ; - .dw 0xC414 ; - .dw 0x3F ; - .dw 0xC414 ; - .dw 0x4009 ; - .dw 0xC414 ; - .dw 0x401B ; - .dw 0xC414 ; - .dw 0x4024 ; - .dw 0xC414 ; - .dw 0x402D ; - .dw 0xC414 ; - .dw 0x4036 ; - .dw 0xC414 ; - .dw 0x403F ; - .dw 0xC415 ; - .dw 0x9 ; - .dw 0xC415 ; - .dw 0x1B ; - .dw 0xC415 ; - .dw 0x24 ; - .dw 0xC415 ; - .dw 0x2D ; - .dw 0xC415 ; - .dw 0x36 ; - .dw 0xC415 ; - .dw 0x3F ; - .dw 0xC415 ; - .dw 0x4009 ; - .dw 0xC415 ; - .dw 0x401B ; - .dw 0xC415 ; - .dw 0x4024 ; - .dw 0xC415 ; - .dw 0x402D ; - .dw 0xC415 ; - .dw 0x4036 ; - .dw 0xC415 ; - .dw 0x403F ; - .dw 0xC416 ; - .dw 0x9 ; - .dw 0xC416 ; - .dw 0x1B ; - .dw 0xC416 ; - .dw 0x24 ; - .dw 0xC416 ; - .dw 0x2D ; - .dw 0xC416 ; - .dw 0x36 ; - .dw 0xC416 ; - .dw 0x3F ; - .dw 0xC416 ; - .dw 0x4009 ; - .dw 0xC416 ; - .dw 0x401B ; - .dw 0xC416 ; - .dw 0x4024 ; - .dw 0xC416 ; - .dw 0x402D ; - .dw 0xC416 ; - .dw 0x4036 ; - .dw 0xC416 ; - .dw 0x403F ; - .dw 0xC416 ; - .dw 0x8009 ; - .dw 0xC416 ; - .dw 0x801B ; - .dw 0xC416 ; - .dw 0x8024 ; - .dw 0xC416 ; - .dw 0x802D ; - .dw 0xC416 ; - .dw 0x8036 ; - .dw 0xC416 ; - .dw 0x803F ; - .dw 0xC416 ; - .dw 0xC009 ; - .dw 0xC416 ; - .dw 0xC01B ; - .dw 0xC416 ; - .dw 0xC024 ; - .dw 0xC416 ; - .dw 0xC02D ; - .dw 0xC416 ; - .dw 0xC036 ; - .dw 0xC416 ; - .dw 0xC03F ; - .dw 0xC417 ; - .dw 0x9 ; - .dw 0xC417 ; - .dw 0x1B ; - .dw 0xC417 ; - .dw 0x24 ; - .dw 0xC417 ; - .dw 0x2D ; - .dw 0xC417 ; - .dw 0x36 ; - .dw 0xC417 ; - .dw 0x3F ; - .dw 0xC418 ; - .dw 0x4009 ; - .dw 0xC418 ; - .dw 0x401B ; - .dw 0xC418 ; - .dw 0x4024 ; - .dw 0xC418 ; - .dw 0x402D ; - .dw 0xC418 ; - .dw 0x4036 ; - .dw 0xC418 ; - .dw 0x403F ; - .dw 0xC600 ; - .dw 0xC000 ; - .dw 0xC601 ; - .dw 0xC000 ; - .dw 0xC603 ; - .dw 0xC000 ; - .dw 0xC605 ; - .dw 0xC000 ; - .dw 0xC608 ; - .dw 0xC000 ; - .dw 0xC60B ; - .dw 0xC000 ; - .dw 0xC60C ; - .dw 0xC000 ; - .dw 0xC60D ; - .dw 0xC000 ; - .dw 0xC606 ; - .dw 0x8000 ; - .dw 0xC608 ; - .dw 0x8000 ; - .dw 0xC60B ; - .dw 0x8000 ; - .dw 0xC60C ; - .dw 0x8000 ; - .dw 0xC60E ; - .dw 0x0 ; - .dw 0xC60E ; - .dw 0x4000 ; - .dw 0xC60E ; - .dw 0x8000 ; - .dw 0xC60E ; - .dw 0xC000 ; - .dw 0xC60F ; - .dw 0x0 ; - .dw 0xC60F ; - .dw 0x4000 ; - .dw 0xC60F ; - .dw 0x8000 ; - .dw 0xC60F ; - .dw 0xC000 ; - .dw 0xC610 ; - .dw 0x0 ; - .dw 0xC610 ; - .dw 0x4000 ; - .dw 0xC610 ; - .dw 0x8000 ; - .dw 0xC610 ; - .dw 0xC000 ; - .dw 0xC611 ; - .dw 0x0 ; - .dw 0xC611 ; - .dw 0x4000 ; - .dw 0xC611 ; - .dw 0x8000 ; - .dw 0xC611 ; - .dw 0xC000 ; - .dw 0xC612 ; - .dw 0x0 ; - .dw 0xC612 ; - .dw 0x4000 ; - .dw 0xC612 ; - .dw 0x8000 ; - .dw 0xC612 ; - .dw 0xC000 ; - .dw 0xC613 ; - .dw 0x0 ; - .dw 0xC613 ; - .dw 0x4000 ; - .dw 0xC613 ; - .dw 0x8000 ; - .dw 0xC613 ; - .dw 0xC000 ; - .dw 0xC614 ; - .dw 0x0 ; - .dw 0xC614 ; - .dw 0x4000 ; - .dw 0xC614 ; - .dw 0x8000 ; - .dw 0xC614 ; - .dw 0xC000 ; - .dw 0xC615 ; - .dw 0x0 ; - .dw 0xC615 ; - .dw 0x4000 ; - .dw 0xC615 ; - .dw 0x8000 ; - .dw 0xC615 ; - .dw 0xC000 ; - .dw 0xC616 ; - .dw 0x0 ; - .dw 0xC616 ; - .dw 0x4000 ; - .dw 0xC616 ; - .dw 0x8000 ; - .dw 0xC616 ; - .dw 0xC000 ; - .dw 0xC617 ; - .dw 0x0 ; - .dw 0xC617 ; - .dw 0x4000 ; - .dw 0xC617 ; - .dw 0x8000 ; - .dw 0xC617 ; - .dw 0xC000 ; - .dw 0xC618 ; - .dw 0x0 ; - .dw 0xC618 ; - .dw 0x4000 ; - .dw 0xC618 ; - .dw 0x8000 ; - .dw 0xC618 ; - .dw 0xC000 ; - .dw 0xC619 ; - .dw 0x0 ; - .dw 0xC619 ; - .dw 0x4000 ; - .dw 0xC619 ; - .dw 0x8000 ; - .dw 0xC619 ; - .dw 0xC000 ; - .dw 0xC61A ; - .dw 0x0 ; - .dw 0xC61A ; - .dw 0x4000 ; - .dw 0xC61A ; - .dw 0x8000 ; - .dw 0xC61A ; - .dw 0xC000 ; - .dw 0xC61B ; - .dw 0x0 ; - .dw 0xC61B ; - .dw 0x4000 ; - .dw 0xC61B ; - .dw 0x8000 ; - .dw 0xC61B ; - .dw 0xC000 ; - .dw 0xC61C ; - .dw 0x0 ; - .dw 0xC61C ; - .dw 0x4000 ; - .dw 0xC61C ; - .dw 0x8000 ; - .dw 0xC61C ; - .dw 0xC000 ; - .dw 0xC61D ; - .dw 0x0 ; - .dw 0xC61D ; - .dw 0x4000 ; - .dw 0xC61D ; - .dw 0x8000 ; - .dw 0xC61D ; - .dw 0xC000 ; - .dw 0xC61E ; - .dw 0x0 ; - .dw 0xC61E ; - .dw 0x4000 ; - .dw 0xC61E ; - .dw 0x8000 ; - .dw 0xC61E ; - .dw 0xC000 ; - .dw 0xC61F ; - .dw 0x0 ; - .dw 0xC61F ; - .dw 0x4000 ; - .dw 0xC61F ; - .dw 0x8000 ; - .dw 0xC61F ; - .dw 0xC000 ; - .dw 0xC608 ; - .dw 0x0 ; - .dw 0xC608 ; - .dw 0x9 ; - .dw 0xC608 ; - .dw 0x12 ; - .dw 0xC608 ; - .dw 0x1B ; - .dw 0xC608 ; - .dw 0x24 ; - .dw 0xC608 ; - .dw 0x2D ; - .dw 0xC608 ; - .dw 0x36 ; - .dw 0xC608 ; - .dw 0x3F ; - .dw 0xC608 ; - .dw 0x4000 ; - .dw 0xC608 ; - .dw 0x4009 ; - .dw 0xC608 ; - .dw 0x4012 ; - .dw 0xC608 ; - .dw 0x401B ; - .dw 0xC608 ; - .dw 0x4024 ; - .dw 0xC608 ; - .dw 0x402D ; - .dw 0xC608 ; - .dw 0x4036 ; - .dw 0xC608 ; - .dw 0x403F ; - .dw 0xC680 ; - .dw 0xC000 ; - .dw 0xC681 ; - .dw 0xC000 ; - .dw 0xC683 ; - .dw 0xC000 ; - .dw 0xC684 ; - .dw 0x0 ; - .dw 0xC684 ; - .dw 0x4000 ; - .dw 0xC684 ; - .dw 0x8000 ; - .dw 0xC684 ; - .dw 0xC000 ; - .dw 0xC685 ; - .dw 0x0 ; - .dw 0xC685 ; - .dw 0x4000 ; - .dw 0xC685 ; - .dw 0x8000 ; - .dw 0xC685 ; - .dw 0xC000 ; - .dw 0xC686 ; - .dw 0x0 ; - .dw 0xC686 ; - .dw 0x4000 ; - .dw 0xC686 ; - .dw 0x8000 ; - .dw 0xC686 ; - .dw 0xC000 ; - .dw 0xC687 ; - .dw 0x0 ; - .dw 0xC687 ; - .dw 0x4000 ; - .dw 0xC687 ; - .dw 0x8000 ; - .dw 0xC687 ; - .dw 0xC000 ; - .dw 0xC688 ; - .dw 0x0 ; - .dw 0xC688 ; - .dw 0x4000 ; - .dw 0xC688 ; - .dw 0x8000 ; - .dw 0xC688 ; - .dw 0xC000 ; - .dw 0xC689 ; - .dw 0x0 ; - .dw 0xC689 ; - .dw 0x4000 ; - .dw 0xC689 ; - .dw 0x8000 ; - .dw 0xC689 ; - .dw 0xC000 ; - .dw 0xC68A ; - .dw 0x0 ; - .dw 0xC68A ; - .dw 0x4000 ; - .dw 0xC68A ; - .dw 0x8000 ; - .dw 0xC68A ; - .dw 0xC000 ; - .dw 0xC68B ; - .dw 0x0 ; - .dw 0xC68B ; - .dw 0x4000 ; - .dw 0xC68B ; - .dw 0x8000 ; - .dw 0xC68B ; - .dw 0xC000 ; - .dw 0xC68C ; - .dw 0x0 ; - .dw 0xC68C ; - .dw 0x4000 ; - .dw 0xC68C ; - .dw 0x8000 ; - .dw 0xC68C ; - .dw 0xC000 ; - .dw 0xC68D ; - .dw 0x0 ; - .dw 0xC68D ; - .dw 0x4000 ; - .dw 0xC68D ; - .dw 0x8000 ; - .dw 0xC68D ; - .dw 0xC000 ; - .dw 0xC68E ; - .dw 0x0 ; - .dw 0xC68E ; - .dw 0x4000 ; - .dw 0xC68E ; - .dw 0x8000 ; - .dw 0xC68E ; - .dw 0xC000 ; - .dw 0xC68F ; - .dw 0x0 ; - .dw 0xC68F ; - .dw 0x4000 ; - .dw 0xC68F ; - .dw 0x8000 ; - .dw 0xC68F ; - .dw 0xC000 ; - .dw 0xC690 ; - .dw 0x0 ; - .dw 0xC690 ; - .dw 0x4000 ; - .dw 0xC690 ; - .dw 0x8000 ; - .dw 0xC690 ; - .dw 0xC000 ; - .dw 0xC691 ; - .dw 0x0 ; - .dw 0xC691 ; - .dw 0x4000 ; - .dw 0xC691 ; - .dw 0x8000 ; - .dw 0xC691 ; - .dw 0xC000 ; - .dw 0xC692 ; - .dw 0x0 ; - .dw 0xC692 ; - .dw 0x4000 ; - .dw 0xC692 ; - .dw 0x8000 ; - .dw 0xC692 ; - .dw 0xC000 ; - .dw 0xC693 ; - .dw 0x0 ; - .dw 0xC693 ; - .dw 0x4000 ; - .dw 0xC693 ; - .dw 0x8000 ; - .dw 0xC693 ; - .dw 0xC000 ; - .dw 0xC694 ; - .dw 0x0 ; - .dw 0xC694 ; - .dw 0x4000 ; - .dw 0xC694 ; - .dw 0x8000 ; - .dw 0xC694 ; - .dw 0xC000 ; - .dw 0xC695 ; - .dw 0x0 ; - .dw 0xC695 ; - .dw 0x4000 ; - .dw 0xC695 ; - .dw 0x8000 ; - .dw 0xC695 ; - .dw 0xC000 ; - .dw 0xC696 ; - .dw 0x0 ; - .dw 0xC696 ; - .dw 0x4000 ; - .dw 0xC696 ; - .dw 0x8000 ; - .dw 0xC696 ; - .dw 0xC000 ; - .dw 0xC697 ; - .dw 0x0 ; - .dw 0xC697 ; - .dw 0x4000 ; - .dw 0xC697 ; - .dw 0x8000 ; - .dw 0xC697 ; - .dw 0xC000 ; - .dw 0xC698 ; - .dw 0x0 ; - .dw 0xC698 ; - .dw 0x4000 ; - .dw 0xC698 ; - .dw 0x8000 ; - .dw 0xC698 ; - .dw 0xC000 ; - .dw 0xC699 ; - .dw 0x0 ; - .dw 0xC699 ; - .dw 0x4000 ; - .dw 0xC699 ; - .dw 0x8000 ; - .dw 0xC699 ; - .dw 0xC000 ; - .dw 0xC69A ; - .dw 0x0 ; - .dw 0xC69A ; - .dw 0x4000 ; - .dw 0xC69A ; - .dw 0x8000 ; - .dw 0xC69A ; - .dw 0xC000 ; - .dw 0xC69B ; - .dw 0x0 ; - .dw 0xC69B ; - .dw 0x4000 ; - .dw 0xC69B ; - .dw 0x8000 ; - .dw 0xC69B ; - .dw 0xC000 ; - .dw 0xC69C ; - .dw 0x0 ; - .dw 0xC69C ; - .dw 0x4000 ; - .dw 0xC69C ; - .dw 0x8000 ; - .dw 0xC69C ; - .dw 0xC000 ; - .dw 0xC69D ; - .dw 0x0 ; - .dw 0xC69D ; - .dw 0x4000 ; - .dw 0xC69D ; - .dw 0x8000 ; - .dw 0xC69D ; - .dw 0xC000 ; - .dw 0xC69E ; - .dw 0x0 ; - .dw 0xC69E ; - .dw 0x4000 ; - .dw 0xC69E ; - .dw 0x8000 ; - .dw 0xC69E ; - .dw 0xC000 ; - .dw 0xC69F ; - .dw 0x0 ; - .dw 0xC69F ; - .dw 0x4000 ; - .dw 0xC69F ; - .dw 0x8000 ; - .dw 0xC69F ; - .dw 0xC000 ; - .dw 0xC008 ; - .dw 0x0 ; - .dw 0xC008 ; - .dw 0x40 ; - .dw 0xC008 ; - .dw 0xC0 ; - .dw 0xC008 ; - .dw 0x140 ; - .dw 0xC008 ; - .dw 0x1C0 ; - .dw 0xC020 ; - .dw 0x0 ; - .dw 0xC040 ; - .dw 0x0 ; - .dw 0xC0A0 ; - .dw 0x0 ; - .dw 0xC0C0 ; - .dw 0x0 ; - .dw 0xC0E0 ; - .dw 0x0 ; - .dw 0xC120 ; - .dw 0x0 ; - .dw 0xC140 ; - .dw 0x0 ; - .dw 0xC160 ; - .dw 0x0 ; - .dw 0xC180 ; - .dw 0x0 ; - .dw 0xC1A0 ; - .dw 0x0 ; - .dw 0xC1C0 ; - .dw 0x0 ; - .dw 0xC1E0 ; - .dw 0x0 ; - .dw 0xC060 ; - .dw 0x2000 ; - .dw 0xC0E0 ; - .dw 0x2000 ; - .dw 0xC140 ; - .dw 0x2000 ; - .dw 0xC1A0 ; - .dw 0x2000 ; - .dw 0xC1C0 ; - .dw 0x2000 ; - .dw 0xC1E0 ; - .dw 0x2000 ; - .dw 0xC064 ; - .dw 0x0 ; - .dw 0xC0E4 ; - .dw 0x0 ; - .dw 0xC144 ; - .dw 0x0 ; - .dw 0xC1A4 ; - .dw 0x0 ; - .dw 0xC1C4 ; - .dw 0x0 ; - .dw 0xC1E4 ; - .dw 0x0 ; - .dw 0xC064 ; - .dw 0x2000 ; - .dw 0xC0E4 ; - .dw 0x2000 ; - .dw 0xC144 ; - .dw 0x2000 ; - .dw 0xC1A4 ; - .dw 0x2000 ; - .dw 0xC1C4 ; - .dw 0x2000 ; - .dw 0xC1E4 ; - .dw 0x2000 ; - .dw 0xC048 ; - .dw 0x2000 ; - .dw 0xC068 ; - .dw 0x2000 ; - .dw 0xC0A8 ; - .dw 0x2000 ; - .dw 0xC0C8 ; - .dw 0x2000 ; - .dw 0xC0E8 ; - .dw 0x2000 ; - .dw 0xC148 ; - .dw 0x2000 ; - .dw 0xC168 ; - .dw 0x2000 ; - .dw 0xC188 ; - .dw 0x2000 ; - .dw 0xC1A8 ; - .dw 0x2000 ; - .dw 0xC1C8 ; - .dw 0x2000 ; - .dw 0xC1E8 ; - .dw 0x2000 ; - .dw 0xC04C ; - .dw 0x0 ; - .dw 0xC06C ; - .dw 0x0 ; - .dw 0xC0AC ; - .dw 0x0 ; - .dw 0xC0CC ; - .dw 0x0 ; - .dw 0xC0EC ; - .dw 0x0 ; - .dw 0xC14C ; - .dw 0x0 ; - .dw 0xC16C ; - .dw 0x0 ; - .dw 0xC18C ; - .dw 0x0 ; - .dw 0xC1AC ; - .dw 0x0 ; - .dw 0xC1CC ; - .dw 0x0 ; - .dw 0xC1EC ; - .dw 0x0 ; - .dw 0xC04C ; - .dw 0x2000 ; - .dw 0xC06C ; - .dw 0x2000 ; - .dw 0xC0AC ; - .dw 0x2000 ; - .dw 0xC0CC ; - .dw 0x2000 ; - .dw 0xC0EC ; - .dw 0x2000 ; - .dw 0xC14C ; - .dw 0x2000 ; - .dw 0xC16C ; - .dw 0x2000 ; - .dw 0xC18C ; - .dw 0x2000 ; - .dw 0xC1AC ; - .dw 0x2000 ; - .dw 0xC1CC ; - .dw 0x2000 ; - .dw 0xC1EC ; - .dw 0x2000 ; - .dw 0xC20C ; - .dw 0x2040 ; - .dw 0xC20C ; - .dw 0x20C0 ; - .dw 0xC20C ; - .dw 0x2140 ; - .dw 0xC20C ; - .dw 0x21C0 ; - .dw 0xC248 ; - .dw 0x2000 ; - .dw 0xC268 ; - .dw 0x2000 ; - .dw 0xC2A8 ; - .dw 0x2000 ; - .dw 0xC2C8 ; - .dw 0x2000 ; - .dw 0xC2E8 ; - .dw 0x2000 ; - .dw 0xC348 ; - .dw 0x2000 ; - .dw 0xC368 ; - .dw 0x2000 ; - .dw 0xC388 ; - .dw 0x2000 ; - .dw 0xC3A8 ; - .dw 0x2000 ; - .dw 0xC3C8 ; - .dw 0x2000 ; - .dw 0xC3E8 ; - .dw 0x2000 ; - .dw 0xC24C ; - .dw 0x0 ; - .dw 0xC26C ; - .dw 0x0 ; - .dw 0xC2AC ; - .dw 0x0 ; - .dw 0xC2CC ; - .dw 0x0 ; - .dw 0xC2EC ; - .dw 0x0 ; - .dw 0xC34C ; - .dw 0x0 ; - .dw 0xC36C ; - .dw 0x0 ; - .dw 0xC38C ; - .dw 0x0 ; - .dw 0xC3AC ; - .dw 0x0 ; - .dw 0xC3CC ; - .dw 0x0 ; - .dw 0xC3EC ; - .dw 0x0 ; - .dw 0xC24C ; - .dw 0x2000 ; - .dw 0xC26C ; - .dw 0x2000 ; - .dw 0xC2AC ; - .dw 0x2000 ; - .dw 0xC2CC ; - .dw 0x2000 ; - .dw 0xC2EC ; - .dw 0x2000 ; - .dw 0xC34C ; - .dw 0x2000 ; - .dw 0xC36C ; - .dw 0x2000 ; - .dw 0xC38C ; - .dw 0x2000 ; - .dw 0xC3AC ; - .dw 0x2000 ; - .dw 0xC3CC ; - .dw 0x2000 ; - .dw 0xC3EC ; - .dw 0x2000 ; - .dw 0xC20D ; - .dw 0x2800 ; - .dw 0xC20E ; - .dw 0x2800 ; - .dw 0xC20F ; - .dw 0x2800 ; - .dw 0xC20D ; - .dw 0x3000 ; - .dw 0xC20E ; - .dw 0x3000 ; - .dw 0xC20F ; - .dw 0x3000 ; - .dw 0xC20D ; - .dw 0x3800 ; - .dw 0xC20E ; - .dw 0x3800 ; - .dw 0xC20F ; - .dw 0x3800 ; - .dw 0xC200 ; - .dw 0x0 ; - .dw 0xC264 ; - .dw 0x2000 ; - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - // Xhandler counts all EXCAUSE = 0x21; -CHECKREG(r5, 2871); // count of all 16 bit UI's. - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - // 32 bit illegal opcode handler - skips bad instruction - - // handler MADE LEAN and destructive so test runs more quckly - // se_undefinedinstruction1.dsp tests using a "nice" handler - -// [--sp] = ASTAT; // save what we damage -// [--sp] = (r7 - r6); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction -CC = r7 == r6; -IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave - - // Also allow 0x22 for illegal instruction combinations (parallel) -R6 = 0x22; -CC = r7 == r6; -IF CC JUMP UNDEFINEDINSTRUCTION; - -dbg_fail; - -UNDEFINEDINSTRUCTION: - R7 = RETX; // Fix up return address - - R7 += 4; // skip offending 32 bit instruction - -RETX = r7; // and put back in RETX - - R5 += 1; // Increment global counter - -OUT: -// (r7 - r6) = [sp++]; -// ASTAT = [sp++]; - -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - // padding for the icache - -EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_undefinedinstruction4.S b/sim/testsuite/sim/bfin/se_undefinedinstruction4.S deleted file mode 100644 index b212c37..0000000 --- a/sim/testsuite/sim/bfin/se_undefinedinstruction4.S +++ /dev/null @@ -1,1298 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction4/se_undefinedinstruction4.dsp -// Description: 64 bit special cases Undefined Instructions in Supervisor Mode -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x10 // change for how much stack you need -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; - -LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - - P0 += 4; // EVT0 not used (Emulation) - - P0 += 4; // EVT1 not used (Reset) - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - P0 += 4; // EVT4 not used (Global Interrupt Enable) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - A0 = 0; // reset accumulators - A1 = 0; - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: - -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests - [ -- SP ] = RETI; // enable interrupts in supervisor mode - - // **** YOUR CODE GOES HERE **** -// Starting 64bit section COUNT = 6406 - .dw 0xCF00 ; - .dw 0xFA4D ; - .dw 0x4973 ; - .dw 0x434D ; - .dw 0xCF01 ; - .dw 0x3CAF ; - .dw 0xE7F7 ; - .dw 0xACAD ; - .dw 0xCF02 ; - .dw 0xC9A3 ; - .dw 0x705D ; - .dw 0x8EFF ; - .dw 0xCF03 ; - .dw 0x242D ; - .dw 0x26ED ; - .dw 0x1C67 ; - .dw 0xCF04 ; - .dw 0xBC83 ; - .dw 0x18BB ; - .dw 0xEF95 ; - .dw 0xCF05 ; - .dw 0xDFA7 ; - .dw 0x6AD9 ; - .dw 0x7FEF ; - .dw 0xCF06 ; - .dw 0x71F3 ; - .dw 0x19CB ; - .dw 0x1F69 ; - .dw 0xCF07 ; - .dw 0xA117 ; - .dw 0x23ED ; - .dw 0xE509 ; - .dw 0xCF08 ; - .dw 0x4DF9 ; - .dw 0x31C3 ; - .dw 0x5207 ; - .dw 0xCF09 ; - .dw 0xF35D ; - .dw 0x998F ; - .dw 0xC1A7 ; - .dw 0xCF0A ; - .dw 0xA7FF ; - .dw 0x73D ; - .dw 0x4ACB ; - .dw 0xCF0B ; - .dw 0xEE29 ; - .dw 0xAAE7 ; - .dw 0x3FD3 ; - .dw 0xCF0C ; - .dw 0xD3B5 ; - .dw 0x5549 ; - .dw 0xBCB7 ; - .dw 0xCF0D ; - .dw 0xF0B7 ; - .dw 0xB91B ; - .dw 0xC01F ; - .dw 0xCF0E ; - .dw 0xC169 ; - .dw 0x3D1F ; - .dw 0xB96B ; - .dw 0xCF0F ; - .dw 0x7CD3 ; - .dw 0xFD95 ; - .dw 0x2EA1 ; - .dw 0xCF10 ; - .dw 0x8907 ; - .dw 0x6013 ; - .dw 0x467D ; - .dw 0xCF11 ; - .dw 0x7F67 ; - .dw 0xFC1F ; - .dw 0x6611 ; - .dw 0xCF12 ; - .dw 0x1BB3 ; - .dw 0xCFE1 ; - .dw 0xF609 ; - .dw 0xCF13 ; - .dw 0x6AF1 ; - .dw 0xC229 ; - .dw 0x8009 ; - .dw 0xCF14 ; - .dw 0xF619 ; - .dw 0xF2C9 ; - .dw 0xF8C7 ; - .dw 0xCF15 ; - .dw 0xE413 ; - .dw 0x99F3 ; - .dw 0x7919 ; - .dw 0xCF16 ; - .dw 0x5E8B ; - .dw 0xCA1 ; - .dw 0xED71 ; - .dw 0xCF17 ; - .dw 0x3FBB ; - .dw 0x221B ; - .dw 0xDA89 ; - .dw 0xCF18 ; - .dw 0xDFED ; - .dw 0x1565 ; - .dw 0x12DB ; - .dw 0xCF19 ; - .dw 0x95FD ; - .dw 0xB71F ; - .dw 0xB9B ; - .dw 0xCF1A ; - .dw 0xAB8F ; - .dw 0xC14F ; - .dw 0xD777 ; - .dw 0xCF1B ; - .dw 0x9427 ; - .dw 0x2E69 ; - .dw 0x5F23 ; - .dw 0xCF1C ; - .dw 0xB9F1 ; - .dw 0xFE17 ; - .dw 0x6AA1 ; - .dw 0xCF1D ; - .dw 0x642B ; - .dw 0x676B ; - .dw 0xCA2B ; - .dw 0xCF1E ; - .dw 0x4399 ; - .dw 0x8C55 ; - .dw 0x5187 ; - .dw 0xCF1F ; - .dw 0xCED5 ; - .dw 0x9163 ; - .dw 0x4B95 ; - .dw 0xCF20 ; - .dw 0xE0F9 ; - .dw 0xA3AF ; - .dw 0x72EB ; - .dw 0xCF21 ; - .dw 0x120B ; - .dw 0x9161 ; - .dw 0x4C73 ; - .dw 0xCF22 ; - .dw 0xA97F ; - .dw 0x9BC3 ; - .dw 0xF2A9 ; - .dw 0xCF23 ; - .dw 0x9B6F ; - .dw 0x15F5 ; - .dw 0x83F3 ; - .dw 0xCF24 ; - .dw 0x67D3 ; - .dw 0x4385 ; - .dw 0xEF37 ; - .dw 0xCF25 ; - .dw 0xD3A3 ; - .dw 0xFB5B ; - .dw 0x119D ; - .dw 0xCF26 ; - .dw 0xCA67 ; - .dw 0xC3F5 ; - .dw 0x2109 ; - .dw 0xCF27 ; - .dw 0x459B ; - .dw 0xC69 ; - .dw 0x6BD3 ; - .dw 0xCF28 ; - .dw 0xBD4B ; - .dw 0x82E1 ; - .dw 0xDD07 ; - .dw 0xCF29 ; - .dw 0x9131 ; - .dw 0x4A0B ; - .dw 0x503B ; - .dw 0xCF2A ; - .dw 0x3383 ; - .dw 0x55B5 ; - .dw 0x7107 ; - .dw 0xCF2B ; - .dw 0x9F5D ; - .dw 0x14B3 ; - .dw 0xF6FF ; - .dw 0xCF2C ; - .dw 0xF3B1 ; - .dw 0x53DF ; - .dw 0x9A93 ; - .dw 0xCF2D ; - .dw 0x5A59 ; - .dw 0x3879 ; - .dw 0x41AD ; - .dw 0xCF2E ; - .dw 0xDD63 ; - .dw 0x9BEF ; - .dw 0x55B3 ; - .dw 0xCF2F ; - .dw 0x9B01 ; - .dw 0x563D ; - .dw 0x598B ; - .dw 0xCF30 ; - .dw 0xF1E3 ; - .dw 0x45E1 ; - .dw 0xD327 ; - .dw 0xCF31 ; - .dw 0xF0C7 ; - .dw 0xD19D ; - .dw 0x110D ; - .dw 0xCF32 ; - .dw 0x94B7 ; - .dw 0x68CF ; - .dw 0x6ADB ; - .dw 0xCF33 ; - .dw 0x4083 ; - .dw 0xAD23 ; - .dw 0x3F8B ; - .dw 0xCF34 ; - .dw 0x55D3 ; - .dw 0x6969 ; - .dw 0x38D9 ; - .dw 0xCF35 ; - .dw 0xD261 ; - .dw 0xF353 ; - .dw 0x1595 ; - .dw 0xCF36 ; - .dw 0x8897 ; - .dw 0x9A6D ; - .dw 0x2093 ; - .dw 0xCF37 ; - .dw 0x2673 ; - .dw 0xD509 ; - .dw 0xF435 ; - .dw 0xCF38 ; - .dw 0x5093 ; - .dw 0x6F8F ; - .dw 0x93D9 ; - .dw 0xCF39 ; - .dw 0xAAE1 ; - .dw 0xE2F1 ; - .dw 0x807F ; - .dw 0xCF3A ; - .dw 0x64D ; - .dw 0xFEF7 ; - .dw 0x103D ; - .dw 0xCF3B ; - .dw 0x1665 ; - .dw 0x1959 ; - .dw 0x608F ; - .dw 0xCF3C ; - .dw 0x43D9 ; - .dw 0x2CDD ; - .dw 0x2F3F ; - .dw 0xCF3D ; - .dw 0x950B ; - .dw 0x3B49 ; - .dw 0x2681 ; - .dw 0xCF3E ; - .dw 0xEA9D ; - .dw 0x8053 ; - .dw 0xC311 ; - .dw 0xCF3F ; - .dw 0x4D3 ; - .dw 0x9311 ; - .dw 0x498B ; - .dw 0xCF40 ; - .dw 0x6909 ; - .dw 0x27C3 ; - .dw 0x2B45 ; - .dw 0xCF41 ; - .dw 0x1347 ; - .dw 0xFC37 ; - .dw 0x8C9D ; - .dw 0xCF42 ; - .dw 0xD08F ; - .dw 0xFF4B ; - .dw 0x3223 ; - .dw 0xCF43 ; - .dw 0x485 ; - .dw 0x7C05 ; - .dw 0xB5BB ; - .dw 0xCF44 ; - .dw 0x49BB ; - .dw 0x5A71 ; - .dw 0xBD1B ; - .dw 0xCF45 ; - .dw 0x27D9 ; - .dw 0x39B ; - .dw 0xE099 ; - .dw 0xCF46 ; - .dw 0x85AF ; - .dw 0xC637 ; - .dw 0xC7EF ; - .dw 0xCF47 ; - .dw 0x5D7B ; - .dw 0x9FAF ; - .dw 0xE277 ; - .dw 0xCF48 ; - .dw 0x51C9 ; - .dw 0xD04B ; - .dw 0xE427 ; - .dw 0xCF49 ; - .dw 0x747B ; - .dw 0xB7F5 ; - .dw 0x4E5 ; - .dw 0xCF4A ; - .dw 0xCBDF ; - .dw 0xFB21 ; - .dw 0x2B5B ; - .dw 0xCF4B ; - .dw 0x6F59 ; - .dw 0x716D ; - .dw 0xB07B ; - .dw 0xCF4C ; - .dw 0x42CB ; - .dw 0x46CB ; - .dw 0x9CD5 ; - .dw 0xCF4D ; - .dw 0xC98B ; - .dw 0x2C5D ; - .dw 0x57FF ; - .dw 0xCF4E ; - .dw 0xF097 ; - .dw 0xF96D ; - .dw 0x9C45 ; - .dw 0xCF4F ; - .dw 0x8743 ; - .dw 0xD053 ; - .dw 0xF01F ; - .dw 0xCF50 ; - .dw 0xD12D ; - .dw 0x79ED ; - .dw 0x18D7 ; - .dw 0xCF51 ; - .dw 0xCB3 ; - .dw 0x860F ; - .dw 0x5F57 ; - .dw 0xCF52 ; - .dw 0x41B7 ; - .dw 0xFB03 ; - .dw 0x2985 ; - .dw 0xCF53 ; - .dw 0x514F ; - .dw 0x6F ; - .dw 0x74F1 ; - .dw 0xCF54 ; - .dw 0x32AF ; - .dw 0x4413 ; - .dw 0x4F1 ; - .dw 0xCF55 ; - .dw 0xDF13 ; - .dw 0xEB77 ; - .dw 0xFDC7 ; - .dw 0xCF56 ; - .dw 0xE7BF ; - .dw 0xF8FB ; - .dw 0x8881 ; - .dw 0xCF57 ; - .dw 0xD71 ; - .dw 0xE18B ; - .dw 0x58E1 ; - .dw 0xCF58 ; - .dw 0xE66B ; - .dw 0x396B ; - .dw 0x6441 ; - .dw 0xCF59 ; - .dw 0xEAE5 ; - .dw 0xC4B9 ; - .dw 0x5D65 ; - .dw 0xCF5A ; - .dw 0x2DA9 ; - .dw 0x2BBB ; - .dw 0xD621 ; - .dw 0xCF5B ; - .dw 0x2FD1 ; - .dw 0xEB81 ; - .dw 0x56F3 ; - .dw 0xCF5C ; - .dw 0x7E67 ; - .dw 0xE6E1 ; - .dw 0x907 ; - .dw 0xCF5D ; - .dw 0x40A3 ; - .dw 0x95B3 ; - .dw 0x3501 ; - .dw 0xCF5E ; - .dw 0xBE25 ; - .dw 0x12A5 ; - .dw 0x96D ; - .dw 0xCF5F ; - .dw 0x94C9 ; - .dw 0xF7F7 ; - .dw 0xA553 ; - .dw 0xCF60 ; - .dw 0xB291 ; - .dw 0x5C7D ; - .dw 0x32ED ; - .dw 0xCF61 ; - .dw 0xABB5 ; - .dw 0x3987 ; - .dw 0x90FB ; - .dw 0xCF62 ; - .dw 0xDE61 ; - .dw 0x6B43 ; - .dw 0x5F83 ; - .dw 0xCF63 ; - .dw 0xF03D ; - .dw 0x61AF ; - .dw 0x3713 ; - .dw 0xCF64 ; - .dw 0x854D ; - .dw 0x2B4B ; - .dw 0x5ACB ; - .dw 0xCF65 ; - .dw 0x669B ; - .dw 0xC7A9 ; - .dw 0xC7B5 ; - .dw 0xCF66 ; - .dw 0x2E5D ; - .dw 0xFFE5 ; - .dw 0x8929 ; - .dw 0xCF67 ; - .dw 0xA089 ; - .dw 0x8151 ; - .dw 0xCD41 ; - .dw 0xCF68 ; - .dw 0xC17F ; - .dw 0x7ECF ; - .dw 0xB3F9 ; - .dw 0xCF69 ; - .dw 0x1689 ; - .dw 0xEA61 ; - .dw 0xC17B ; - .dw 0xCF6A ; - .dw 0xF6A1 ; - .dw 0xB5D1 ; - .dw 0xE1D5 ; - .dw 0xCF6B ; - .dw 0x8CEB ; - .dw 0xFA5 ; - .dw 0xBF9B ; - .dw 0xCF6C ; - .dw 0x9A11 ; - .dw 0x79DB ; - .dw 0x6B09 ; - .dw 0xCF6D ; - .dw 0x769B ; - .dw 0xEED1 ; - .dw 0x3BE3 ; - .dw 0xCF6E ; - .dw 0x8B95 ; - .dw 0xC2E9 ; - .dw 0x782D ; - .dw 0xCF6F ; - .dw 0x3763 ; - .dw 0x756B ; - .dw 0xE4B1 ; - .dw 0xCF70 ; - .dw 0xB2F5 ; - .dw 0x7F09 ; - .dw 0x2A1B ; - .dw 0xCF71 ; - .dw 0x9A79 ; - .dw 0x5685 ; - .dw 0x30BF ; - .dw 0xCF72 ; - .dw 0xCE41 ; - .dw 0x72D1 ; - .dw 0x301B ; - .dw 0xCF73 ; - .dw 0xAA27 ; - .dw 0x909B ; - .dw 0x818D ; - .dw 0xCF74 ; - .dw 0x5BB9 ; - .dw 0x8C95 ; - .dw 0xEA9F ; - .dw 0xCF75 ; - .dw 0x3079 ; - .dw 0x3273 ; - .dw 0x87F ; - .dw 0xCF76 ; - .dw 0x5297 ; - .dw 0x639B ; - .dw 0xC64B ; - .dw 0xCF77 ; - .dw 0x6883 ; - .dw 0xF731 ; - .dw 0xA8DF ; - .dw 0xCF78 ; - .dw 0x4387 ; - .dw 0x53CB ; - .dw 0x9CA1 ; - .dw 0xCF79 ; - .dw 0xAB55 ; - .dw 0xF8B ; - .dw 0xC01D ; - .dw 0xCF7A ; - .dw 0x3335 ; - .dw 0xA1EB ; - .dw 0xFD35 ; - .dw 0xCF7B ; - .dw 0xB3D ; - .dw 0x3F6B ; - .dw 0xF1A1 ; - .dw 0xCF7C ; - .dw 0x6EA9 ; - .dw 0x33F3 ; - .dw 0xAB8B ; - .dw 0xCF7D ; - .dw 0xBB41 ; - .dw 0xBCB7 ; - .dw 0xAA7D ; - .dw 0xCF7E ; - .dw 0x1ABD ; - .dw 0x8C9F ; - .dw 0xBBA9 ; - .dw 0xCF7F ; - .dw 0xB089 ; - .dw 0x55A3 ; - .dw 0xED41 ; - .dw 0xCF80 ; - .dw 0xB59D ; - .dw 0xC0AD ; - .dw 0xE873 ; - .dw 0xCF81 ; - .dw 0xFEA7 ; - .dw 0xB265 ; - .dw 0xF55F ; - .dw 0xCF82 ; - .dw 0x8A87 ; - .dw 0xE7F9 ; - .dw 0x64D3 ; - .dw 0xCF83 ; - .dw 0xE769 ; - .dw 0x6783 ; - .dw 0x4547 ; - .dw 0xCF84 ; - .dw 0x9597 ; - .dw 0xFBE9 ; - .dw 0xE1DD ; - .dw 0xCF85 ; - .dw 0x5239 ; - .dw 0x6397 ; - .dw 0x99C1 ; - .dw 0xCF86 ; - .dw 0xE6FF ; - .dw 0x84B ; - .dw 0x31C7 ; - .dw 0xCF87 ; - .dw 0x3E93 ; - .dw 0x6CDD ; - .dw 0xE883 ; - .dw 0xCF88 ; - .dw 0x9A81 ; - .dw 0xEB3D ; - .dw 0x310B ; - .dw 0xCF89 ; - .dw 0xA8AF ; - .dw 0x405D ; - .dw 0xDFC7 ; - .dw 0xCF8A ; - .dw 0x515B ; - .dw 0x7C13 ; - .dw 0xD483 ; - .dw 0xCF8B ; - .dw 0x1EE3 ; - .dw 0xD5E9 ; - .dw 0x2FAD ; - .dw 0xCF8C ; - .dw 0x2A93 ; - .dw 0xB0E1 ; - .dw 0xC4C1 ; - .dw 0xCF8D ; - .dw 0xD1DD ; - .dw 0xB1E7 ; - .dw 0x1E29 ; - .dw 0xCF8E ; - .dw 0xD6ED ; - .dw 0x1DB1 ; - .dw 0x2C7F ; - .dw 0xCF8F ; - .dw 0x1935 ; - .dw 0x6711 ; - .dw 0x618D ; - .dw 0xCF90 ; - .dw 0xFB4D ; - .dw 0xD003 ; - .dw 0xB185 ; - .dw 0xCF91 ; - .dw 0x1969 ; - .dw 0xD80F ; - .dw 0xDD13 ; - .dw 0xCF92 ; - .dw 0xFDE7 ; - .dw 0xF487 ; - .dw 0x54AB ; - .dw 0xCF93 ; - .dw 0x4FDB ; - .dw 0xCA39 ; - .dw 0x7EAF ; - .dw 0xCF94 ; - .dw 0xF805 ; - .dw 0xC4BF ; - .dw 0x8F77 ; - .dw 0xCF95 ; - .dw 0x24E3 ; - .dw 0x5055 ; - .dw 0x491 ; - .dw 0xCF96 ; - .dw 0x37A9 ; - .dw 0xCD9D ; - .dw 0xD301 ; - .dw 0xCF97 ; - .dw 0x2379 ; - .dw 0xDD89 ; - .dw 0xBC7B ; - .dw 0xCF98 ; - .dw 0xE1F3 ; - .dw 0x977F ; - .dw 0xED8B ; - .dw 0xCF99 ; - .dw 0xF983 ; - .dw 0xCE75 ; - .dw 0x3E75 ; - .dw 0xCF9A ; - .dw 0x4081 ; - .dw 0xF3D5 ; - .dw 0x3185 ; - .dw 0xCF9B ; - .dw 0xCB77 ; - .dw 0x47AD ; - .dw 0x97E9 ; - .dw 0xCF9C ; - .dw 0x71AF ; - .dw 0x93E1 ; - .dw 0xE25B ; - .dw 0xCF9D ; - .dw 0x9139 ; - .dw 0xCE65 ; - .dw 0x33C3 ; - .dw 0xCF9E ; - .dw 0xF4F5 ; - .dw 0xEF8D ; - .dw 0xC8D5 ; - .dw 0xCF9F ; - .dw 0x1E1 ; - .dw 0x59A7 ; - .dw 0xE7A1 ; - .dw 0xCFA0 ; - .dw 0x4241 ; - .dw 0xCB25 ; - .dw 0x4265 ; - .dw 0xCFA1 ; - .dw 0xE769 ; - .dw 0x27E1 ; - .dw 0xCD97 ; - .dw 0xCFA2 ; - .dw 0xA491 ; - .dw 0xB5C1 ; - .dw 0x427 ; - .dw 0xCFA3 ; - .dw 0x6AD7 ; - .dw 0xC611 ; - .dw 0xD5AB ; - .dw 0xCFA4 ; - .dw 0x4DA9 ; - .dw 0x8A15 ; - .dw 0x83DD ; - .dw 0xCFA5 ; - .dw 0xE503 ; - .dw 0xCB71 ; - .dw 0x2189 ; - .dw 0xCFA6 ; - .dw 0x6A27 ; - .dw 0x2EBB ; - .dw 0xE6D9 ; - .dw 0xCFA7 ; - .dw 0xDF6B ; - .dw 0x35E5 ; - .dw 0x288D ; - .dw 0xCFA8 ; - .dw 0x42DD ; - .dw 0x6A67 ; - .dw 0xD7F1 ; - .dw 0xCFA9 ; - .dw 0x143B ; - .dw 0x70F9 ; - .dw 0x319D ; - .dw 0xCFAA ; - .dw 0x919B ; - .dw 0x7C3B ; - .dw 0x1B7B ; - .dw 0xCFAB ; - .dw 0x4413 ; - .dw 0x42CB ; - .dw 0xC3FF ; - .dw 0xCFAC ; - .dw 0x7D61 ; - .dw 0x27AB ; - .dw 0x818B ; - .dw 0xCFAD ; - .dw 0x839F ; - .dw 0x7FB1 ; - .dw 0x27A3 ; - .dw 0xCFAE ; - .dw 0x932D ; - .dw 0xE719 ; - .dw 0x5449 ; - .dw 0xCFAF ; - .dw 0x1289 ; - .dw 0xDED7 ; - .dw 0xC905 ; - .dw 0xCFB0 ; - .dw 0xE641 ; - .dw 0xDFAD ; - .dw 0xF1A5 ; - .dw 0xCFB1 ; - .dw 0xC0D1 ; - .dw 0xF7BD ; - .dw 0x3423 ; - .dw 0xCFB2 ; - .dw 0xAC39 ; - .dw 0xDC73 ; - .dw 0x4545 ; - .dw 0xCFB3 ; - .dw 0x3F39 ; - .dw 0xB1D9 ; - .dw 0x3DA7 ; - .dw 0xCFB4 ; - .dw 0x86A1 ; - .dw 0xE663 ; - .dw 0xB105 ; - .dw 0xCFB5 ; - .dw 0x52A1 ; - .dw 0xA52D ; - .dw 0xB8C7 ; - .dw 0xCFB6 ; - .dw 0x9D8B ; - .dw 0xE251 ; - .dw 0xFFB3 ; - .dw 0xCFB7 ; - .dw 0xA225 ; - .dw 0x7425 ; - .dw 0xA407 ; - .dw 0xCFB8 ; - .dw 0x13C3 ; - .dw 0xD553 ; - .dw 0x9F8F ; - .dw 0xCFB9 ; - .dw 0x9ABF ; - .dw 0x6487 ; - .dw 0xE63D ; - .dw 0xCFBA ; - .dw 0x971B ; - .dw 0xEBCD ; - .dw 0xF725 ; - .dw 0xCFBB ; - .dw 0x8B4F ; - .dw 0xCED3 ; - .dw 0x691B ; - .dw 0xCFBC ; - .dw 0x3C89 ; - .dw 0xFE7B ; - .dw 0x9105 ; - .dw 0xCFBD ; - .dw 0x86D9 ; - .dw 0xC0CD ; - .dw 0x75A5 ; - .dw 0xCFBE ; - .dw 0xD961 ; - .dw 0xF4C1 ; - .dw 0x7801 ; - .dw 0xCFBF ; - .dw 0xAAA3 ; - .dw 0xC993 ; - .dw 0x92C5 ; - .dw 0xCFC0 ; - .dw 0x8D ; - .dw 0xEAB5 ; - .dw 0xCF55 ; - .dw 0xCFC1 ; - .dw 0xF94D ; - .dw 0xB307 ; - .dw 0xA575 ; - .dw 0xCFC2 ; - .dw 0x140F ; - .dw 0x4CE7 ; - .dw 0xD78B ; - .dw 0xCFC3 ; - .dw 0xF359 ; - .dw 0x4DE7 ; - .dw 0x958B ; - .dw 0xCFC4 ; - .dw 0xD893 ; - .dw 0xBA3 ; - .dw 0x8A5D ; - .dw 0xCFC5 ; - .dw 0x5149 ; - .dw 0xCB4B ; - .dw 0x21E3 ; - .dw 0xCFC6 ; - .dw 0xA65 ; - .dw 0x7A85 ; - .dw 0x2571 ; - .dw 0xCFC7 ; - .dw 0xA2DF ; - .dw 0xC7F9 ; - .dw 0xB9AF ; - .dw 0xCFC8 ; - .dw 0xF8A3 ; - .dw 0x491D ; - .dw 0xBD37 ; - .dw 0xCFC9 ; - .dw 0xFA7B ; - .dw 0x8B45 ; - .dw 0xCD ; - .dw 0xCFCA ; - .dw 0x84F3 ; - .dw 0x1C97 ; - .dw 0xA6C7 ; - .dw 0xCFCB ; - .dw 0x1349 ; - .dw 0x6CD9 ; - .dw 0xF7E3 ; - .dw 0xCFCC ; - .dw 0x738D ; - .dw 0x9209 ; - .dw 0x90F9 ; - .dw 0xCFCD ; - .dw 0x6C31 ; - .dw 0x3A3D ; - .dw 0x7921 ; - .dw 0xCFCE ; - .dw 0x18E5 ; - .dw 0xB46F ; - .dw 0xE29B ; - .dw 0xCFCF ; - .dw 0x812D ; - .dw 0x2E4B ; - .dw 0xB56B ; - .dw 0xCFD0 ; - .dw 0x87E5 ; - .dw 0x18D5 ; - .dw 0xC509 ; - .dw 0xCFD1 ; - .dw 0x8005 ; - .dw 0xFAA1 ; - .dw 0x7DC1 ; - .dw 0xCFD2 ; - .dw 0xCCC5 ; - .dw 0xBEE7 ; - .dw 0x87FB ; - .dw 0xCFD3 ; - .dw 0x6D11 ; - .dw 0xE40B ; - .dw 0x47C5 ; - .dw 0xCFD4 ; - .dw 0xDE9F ; - .dw 0x6351 ; - .dw 0x24DB ; - .dw 0xCFD5 ; - .dw 0x8803 ; - .dw 0x690D ; - .dw 0xE3F5 ; - .dw 0xCFD6 ; - .dw 0x22C9 ; - .dw 0x505 ; - .dw 0xF573 ; - .dw 0xCFD7 ; - .dw 0xC055 ; - .dw 0xB295 ; - .dw 0xA7D3 ; - .dw 0xCFD8 ; - .dw 0x305 ; - .dw 0xD61D ; - .dw 0x933B ; - .dw 0xCFD9 ; - .dw 0xC59 ; - .dw 0x8CD1 ; - .dw 0x3D47 ; - .dw 0xCFDA ; - .dw 0x9095 ; - .dw 0x8C21 ; - .dw 0xAA23 ; - .dw 0xCFDB ; - .dw 0x5D97 ; - .dw 0x376F ; - .dw 0x3C85 ; - .dw 0xCFDC ; - .dw 0xDC49 ; - .dw 0xE393 ; - .dw 0xB31B ; - .dw 0xCFDD ; - .dw 0x9871 ; - .dw 0x61FF ; - .dw 0xCF1 ; - .dw 0xCFDE ; - .dw 0xEC8D ; - .dw 0xD8B ; - .dw 0x683D ; - .dw 0xCFDF ; - .dw 0x449D ; - .dw 0x82F5 ; - .dw 0x24FF ; - .dw 0xCFE0 ; - .dw 0x708D ; - .dw 0x8629 ; - .dw 0xB5D3 ; - .dw 0xCFE1 ; - .dw 0x7FA3 ; - .dw 0xC4EB ; - .dw 0x80C7 ; - .dw 0xCFE2 ; - .dw 0xD88F ; - .dw 0x5DBF ; - .dw 0x5113 ; - .dw 0xCFE3 ; - .dw 0xF1BD ; - .dw 0x6797 ; - .dw 0xEA3B ; - .dw 0xCFE4 ; - .dw 0xB965 ; - .dw 0x2E63 ; - .dw 0x56ED ; - .dw 0xCFE5 ; - .dw 0x15B ; - .dw 0x733 ; - .dw 0x5599 ; - .dw 0xCFE6 ; - .dw 0xB249 ; - .dw 0xAAFB ; - .dw 0xC29B ; - .dw 0xCFE7 ; - .dw 0x20C1 ; - .dw 0x26A9 ; - .dw 0x39 ; - .dw 0xCFE8 ; - .dw 0xD1E5 ; - .dw 0xCC2D ; - .dw 0x8D6D ; - .dw 0xCFE9 ; - .dw 0xB4C3 ; - .dw 0xF651 ; - .dw 0xF25 ; - .dw 0xCFEA ; - .dw 0x10F3 ; - .dw 0xFB75 ; - .dw 0x3E79 ; - .dw 0xCFEB ; - .dw 0x9B55 ; - .dw 0x2A7 ; - .dw 0xFEAB ; - .dw 0xCFEC ; - .dw 0x4623 ; - .dw 0x1BCD ; - .dw 0xFA9B ; - .dw 0xCFED ; - .dw 0xA3E3 ; - .dw 0x9B9B ; - .dw 0x2B6F ; - .dw 0xCFEE ; - .dw 0x58A9 ; - .dw 0xD303 ; - .dw 0x2287 ; - .dw 0xCFEF ; - .dw 0x3AF1 ; - .dw 0xBEFF ; - .dw 0xF90B ; - .dw 0xCFF0 ; - .dw 0xCC47 ; - .dw 0xDE4D ; - .dw 0x9E43 ; - .dw 0xCFF1 ; - .dw 0xFE51 ; - .dw 0x7DC7 ; - .dw 0x79BD ; - .dw 0xCFF2 ; - .dw 0x6B1D ; - .dw 0x6835 ; - .dw 0x7AD9 ; - .dw 0xCFF3 ; - .dw 0xC635 ; - .dw 0x955D ; - .dw 0xDE57 ; - .dw 0xCFF4 ; - .dw 0x2F0B ; - .dw 0x2555 ; - .dw 0xD887 ; - .dw 0xCFF5 ; - .dw 0xCB59 ; - .dw 0xAC01 ; - .dw 0x3CEB ; - .dw 0xCFF6 ; - .dw 0xFDF5 ; - .dw 0x510D ; - .dw 0xB54D ; - .dw 0xCFF7 ; - .dw 0xD1DB ; - .dw 0xA867 ; - .dw 0x482F ; - .dw 0xCFF8 ; - .dw 0xB1C9 ; - .dw 0x5AA7 ; - .dw 0x4121 ; - .dw 0xCFF9 ; - .dw 0x83A1 ; - .dw 0x5A65 ; - .dw 0x4161 ; - .dw 0xCFFA ; - .dw 0x9E7F ; - .dw 0xF1F ; - .dw 0x7E8F ; - .dw 0xCFFB ; - .dw 0x4D1F ; - .dw 0x7C11 ; - .dw 0xA17B ; - .dw 0xCFFC ; - .dw 0xB5FD ; - .dw 0x2AF7 ; - .dw 0x5C2B ; - .dw 0xCFFD ; - .dw 0xFA4F ; - .dw 0x580D ; - .dw 0x8E77 ; - .dw 0xCFFE ; - .dw 0xEB0B ; - .dw 0x633B ; - .dw 0x9099 ; - .dw 0xCFFF ; - .dw 0xE1A1 ; - .dw 0x7B5F ; - .dw 0xC9B ; -// COUNT = 6662 - - - - // count of UI's will be in r5, which was initialized to 0 by header - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - // Xhandler counts all EXCAUSE = 0x21; -CHECKREG(r5, 256); // count of all 16 bit UI's. - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - // 64 bit illegal opcode handler - skips bad instruction - - [ -- SP ] = ASTAT; // save what we damage - [ -- SP ] = ( R7:6 ); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE - R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction -CC = r7 == r6; -IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave - -dbg_fail; - -UNDEFINEDINSTRUCTION: - R7 = RETX; // Fix up return address - - R7 += 8; // skip offending 64 bit instruction - -RETX = r7; // and put back in RETX - - R5 += 1; // Increment global counter - -OUT: - ( R7:6 ) = [ SP ++ ]; -ASTAT = [sp++]; - -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - // padding for the icache - -EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/se_usermode_protviol.S b/sim/testsuite/sim/bfin/se_usermode_protviol.S deleted file mode 100644 index 5e8a4cc..0000000 --- a/sim/testsuite/sim/bfin/se_usermode_protviol.S +++ /dev/null @@ -1,317 +0,0 @@ -//Original:/proj/frio/dv/testcases/seq/se_usermode_protviol/se_usermode_protviol.dsp -// Description: User mode "Illegal Use Supervsor Resource" Exceptions -# mach: bfin -# sim: --environment operating - -#include "test.h" -.include "testutils.inc" -start - -// -// Constants and Defines -// - -include(gen_int.inc) -include(selfcheck.inc) -include(std.inc) -include(mmrs.inc) -include(symtable.inc) - -#ifndef STACKSIZE -#define STACKSIZE 0x100 // change for how much stack you need -#endif -#ifndef ITABLE -#define ITABLE 0xF0000000 -#endif - -GEN_INT_INIT(ITABLE) // set location for interrupt table - -// -// Reset/Bootstrap Code -// (Here we should set the processor operating modes, initialize registers, -// etc.) -// - -BOOT: -INIT_R_REGS(0); // initialize general purpose regs - -INIT_P_REGS(0); // initialize the pointers - -INIT_I_REGS(0); // initialize the dsp address regs -INIT_M_REGS(0); -INIT_L_REGS(0); -INIT_B_REGS(0); - -CLI R1; // inhibit events during MMR writes - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -USP = SP; - -LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer -FP = SP; // and frame pointer - -LD32(p0, EVT0); // Setup Event Vectors and Handlers - - P0 += 4; // EVT0 not used (Emulation) - - P0 += 4; // EVT1 not used (Reset) - -LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) - [ P0 ++ ] = R0; - - P0 += 4; // EVT4 not used (Global Interrupt Enable) - -LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I7HANDLE); // IVG7 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I8HANDLE); // IVG8 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I9HANDLE); // IVG9 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I10HANDLE);// IVG10 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I11HANDLE);// IVG11 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I12HANDLE);// IVG12 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I13HANDLE);// IVG13 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I14HANDLE);// IVG14 Handler - [ P0 ++ ] = R0; - -LD32_LABEL(r0, I15HANDLE);// IVG15 Handler - [ P0 ++ ] = R0; - -LD32(p0, EVT_OVERRIDE); - R0 = 0; - [ P0 ++ ] = R0; - - R1 = -1; // Change this to mask interrupts (*) -CSYNC; // wait for MMR writes to finish -STI R1; // sync and reenable events (implicit write to IMASK) - -DUMMY: - - R0 = 0 (Z); - -LT0 = r0; // set loop counters to something deterministic -LB0 = r0; -LC0 = r0; -LT1 = r0; -LB1 = r0; -LC1 = r0; - -ASTAT = r0; // reset other internal regs -SYSCFG = r0; -RETS = r0; // prevent X's breaking LINK instruction - -RETI = r0; // prevent Xs later on -RETX = r0; -RETN = r0; -RETE = r0; - - -// The following code sets up the test for running in USER mode - -LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a - // ReturnFromInterrupt (RTI) -RETI = r0; // We need to load the return address - -// Comment the following line for a USER Mode test - -// JUMP STARTSUP; // jump to code start for SUPERVISOR mode - -RTI; - -STARTSUP: -LD32_LABEL(p1, BEGIN); - -LD32(p0, EVT15); - -CLI R1; // inhibit events during write to MMR - [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start -CSYNC; // wait for it -STI R1; // reenable events with proper imask - -RAISE 15; // after we RTI, INT 15 should be taken - -RTI; - -// -// The Main Program -// - -STARTUSER: - -LD32_LABEL(sp, USTACK); // setup the user stack pointer -FP = SP; -LINK 0; // change for how much stack frame space you need. - -JUMP BEGIN; - -//********************************************************************* - -BEGIN: - - // COMMENT the following line for USER MODE tests -// [--sp] = RETI; // enable interrupts in supervisor mode - - R0 = 0; - R1 = -1; - -// the following instructions should EXCEPT - R6 = 0x2E; // EXCAUSE 0x2E means Illegal Use Supervidor Resource - -RAISE 15; -CLI R0; -STI r0; -// TESTSET (p0); // now allowed in user mode -r5 += 1; -// IDLE; // works in user mode - -USP = r1; -SEQSTAT = r1; -SYSCFG = r1; -RETI = r1; -RETX = r1; -RETN = r1; -RETE = r1; - - R2 = USP; - R2 = SEQSTAT; - R2 = SYSCFG; - R2 = RETI; - R2 = RETX; - R2 = RETN; - R2 = RETE; - - [ -- SP ] = USP; - [ -- SP ] = SEQSTAT; - [ -- SP ] = SYSCFG; - [ -- SP ] = RETI; - [ -- SP ] = RETX; - [ -- SP ] = RETN; - [ -- SP ] = RETE; - -SEQSTAT = [sp++]; -SYSCFG = [sp++]; -RETI = [sp++]; -RETX = [sp++]; -RETN = [sp++]; -RETE = [sp++]; - -RTX; -RTN; -RTI; -RTE; - - R6 = 0x22; // EXCAUSE 0x22 means Illegal Insn Combination -USP = [sp++]; - -CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); - // Xhandler counts all EXCAUSE = 0x2B; -CHECKREG(r5, 36); // count of all IF protection violations. - -END: -dbg_pass; // End the test - -//********************************************************************* - -// -// Handlers for Events -// - -NHANDLE: // NMI Handler 2 -RTN; - -XHANDLE: // Exception Handler 3 - [ -- SP ] = ASTAT; // save what we damage - [ -- SP ] = ( R7:6 ); - R7 = SEQSTAT; - R7 <<= 26; - R7 >>= 26; // only want EXCAUSE -CC = r7 == r6; -IF CC JUMP IFETCHPROTVIOL; // If EXCAUSE != 0x2E then leave - -dbg_fail; // if the EXCAUSE is wrong the test will infinite loop - -IFETCHPROTVIOL: - R7 = RETX; // Fix up return address - R7 += 2; // skip instruction -RETX = r7; // and put back in RETX - - R5 += 1; // Count - -OUT: - ( R7:6 ) = [ SP ++ ]; -ASTAT = [sp++]; -RTX; - -HWHANDLE: // HW Error Handler 5 -RTI; - -THANDLE: // Timer Handler 6 -RTI; - -I7HANDLE: // IVG 7 Handler -RTI; - -I8HANDLE: // IVG 8 Handler -RTI; - -I9HANDLE: // IVG 9 Handler -RTI; - -I10HANDLE: // IVG 10 Handler -RTI; - -I11HANDLE: // IVG 11 Handler -RTI; - -I12HANDLE: // IVG 12 Handler -RTI; - -I13HANDLE: // IVG 13 Handler -RTI; - -I14HANDLE: // IVG 14 Handler -RTI; - -I15HANDLE: // IVG 15 Handler -RTI; - - - // padding for the icache - -EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; - -// -// Data Segment -// - -.data -DATA: - .space (0x10); - -// Stack Segments (Both Kernel and User) - - .space (STACKSIZE); -KSTACK: - - .space (STACKSIZE); -USTACK: diff --git a/sim/testsuite/sim/bfin/seqstat.s b/sim/testsuite/sim/bfin/seqstat.s deleted file mode 100644 index 45fad2c..0000000 --- a/sim/testsuite/sim/bfin/seqstat.s +++ /dev/null @@ -1,25 +0,0 @@ -# Blackfin testcase for SEQSTAT register -# mach: bfin - - .include "testutils.inc" - - .macro seqstat_test val:req - imm32 R0, \val - SEQSTAT = R0; - R1 = SEQSTAT; - CC = R7 == R1; - IF !CC JUMP 1f; - .endm - - start - - # Writes to SEQSTAT should be ignored - R7 = SEQSTAT; - - seqstat_test 0 - seqstat_test 0x1 - seqstat_test -1 - seqstat_test 0xab11cd22 - - pass -1: fail diff --git a/sim/testsuite/sim/bfin/sign.s b/sim/testsuite/sim/bfin/sign.s deleted file mode 100644 index 072263e..0000000 --- a/sim/testsuite/sim/bfin/sign.s +++ /dev/null @@ -1,27 +0,0 @@ -# Blackfin testcase for signbits -# mach: bfin - - .include "testutils.inc" - - start - - .macro check_alu_signbits areg:req - \areg = 0; - R0 = 0x10 (Z); - \areg\().x = R0; - - imm32 r0, 0x60038; - - R0.L = SIGNBITS \areg; - - imm32 r1, 0x6fffa; - CC = R1 == R0; - if ! CC jump 1f; - .endm - - check_alu_signbits A0 - check_alu_signbits A1 - - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/simple0.s b/sim/testsuite/sim/bfin/simple0.s deleted file mode 100644 index 956ce11..0000000 --- a/sim/testsuite/sim/bfin/simple0.s +++ /dev/null @@ -1,10 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - R0 = 5; - R0 += -1; - DBGA ( R0.L , 4 ); - pass diff --git a/sim/testsuite/sim/bfin/sri.s b/sim/testsuite/sim/bfin/sri.s deleted file mode 100644 index 9f90abf..0000000 --- a/sim/testsuite/sim/bfin/sri.s +++ /dev/null @@ -1,21 +0,0 @@ -# Blackfin testcase for BITMUX -# mach: bfin - - .include "testutils.inc" - - start - - r0 = 0; - p2.l = 16; - -ilp: - BITMUX( R6 , R7, A0) (ASR); - p2 += -1; - cc=p2==0; - if !cc jump ilp; - A0 = A0 >> 8; - R0 = A0.w; - [ I1 ++ ] = R0; - nop; - - pass diff --git a/sim/testsuite/sim/bfin/stk.s b/sim/testsuite/sim/bfin/stk.s deleted file mode 100644 index 451a11e..0000000 --- a/sim/testsuite/sim/bfin/stk.s +++ /dev/null @@ -1,78 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - -// load up some registers. -// setup up a global pointer table and load some state. -// save the machine state and clear some of the values. -// then restore and assert some of the values to ensure that -// we maintain consitent machine state. - - R0 = 1; - R1 = 2; - R2 = 3; - R3 = -7; - R4 = 4; - R5 = 5; - R6 = 6; - R7 = 7; - - loadsym P0, a; - _DBG P0; - SP = P0; - FP = P0; - P1 = [ P0 ++ ]; - P2 = [ P0 ++ ]; - P0 += 4; - P4 = [ P0 ++ ]; - P5 = [ P0 ++ ]; - [ -- SP ] = ( R7:0, P5:0 ); - _DBG SP; - _DBG FP; - R0 = R0 ^ R0; - R1 = R1 ^ R1; - R2 = R2 ^ R2; - R4 = R4 ^ R4; - R5 = R5 ^ R5; - R6 = R6 ^ R6; - R7 = R7 ^ R7; - ( R7:0, P5:0 ) = [ SP ++ ]; - DBGA ( R0.L , 1 ); - DBGA ( R2.L , 3 ); - DBGA ( R7.L , 7 ); - R0 = SP; - loadsym R1, a; - CC = R0 == R1; - IF !CC JUMP abrt; - R0 = FP; - CC = R0 == R1; - CC = R0 == R1; - IF !CC JUMP abrt; - - pass -abrt: - fail - - .data -_gptab: - .dw 0x200 - .dw 0x000 - .dw 0x300 - .dw 0x400 - .dw 0x500 - .dw 0x600 - - .space (0x100) -a: - .dw 1 - .dw 2 - .dw 3 - .dw 4 - .dw 5 - .dw 6 - .dw 7 - .dw 8 - .dw 9 - .dw 0xa diff --git a/sim/testsuite/sim/bfin/stk2.s b/sim/testsuite/sim/bfin/stk2.s deleted file mode 100644 index d5cb975..0000000 --- a/sim/testsuite/sim/bfin/stk2.s +++ /dev/null @@ -1,107 +0,0 @@ -// load up some registers. -// setup up a global pointer table and load some state. -// save the machine state and clear some of the values. -// then restore and assert some of the values to ensure that -// we maintain consitent machine state. -# mach: bfin - - -.include "testutils.inc" - start - - R0 = 1; - R1 = 2; - R2 = 3; - R3 = -7; - R4 = 4; - R5 = 5; - R6 = 6; - R7 = 7; - - loadsym P0, a; - P1.L = 0x1000; -//DBG P0; -//DBG P1; - SP = P0; - FP = P0; - - CALL try; - - P1 = [ P0 ++ ]; - P2 = [ P0 ++ ]; - P0 += 4; - P4 = [ P0 ++ ]; - P5 = [ P0 ++ ]; -// DBG; - [ -- SP ] = ( R7:0, P5:0 ); -// DBG SP; -// DBG FP; - R0 = R0 ^ R0; - R1 = R1 ^ R1; - R2 = R2 ^ R2; - R4 = R4 ^ R4; - R5 = R5 ^ R5; - R6 = R6 ^ R6; - R7 = R7 ^ R7; -// DBG; - ( R7:0, P5:0 ) = [ SP ++ ]; - DBGA ( R0.L , 1 ); - DBGA ( R1.L , 2 ); - DBGA ( R2.L , 3 ); - DBGA ( R3.L , 0xfff9 ); - DBGA ( R4.L , 4 ); - DBGA ( R5.L , 5 ); - DBGA ( R6.L , 6 ); - DBGA ( R7.L , 7 ); - - R0 = SP; - loadsym R1, a; - CC = R0 == R1; - IF !CC JUMP abrt; - R0 = FP; - CC = R0 == R1; - CC = R0 == R1; - IF !CC JUMP abrt; - pass -abrt: - fail - -try: - LINK 0; - [ -- SP ] = R7; - [ -- SP ] = R0; - R7 = 0x1234 (X); - [ -- SP ] = R7; - CALL bar; - SP += 4; - R0 = [ SP ++ ]; - R7 = [ SP ++ ]; - UNLINK; - RTS; - -bar: - R0 = [ SP ]; - DBGA ( R0.L , 0x1234 ); - RTS; - - .data -_gptab: - .dw 0x200 - .dw 0x000 - .dw 0x300 - .dw 0x400 - .dw 0x500 - .dw 0x600 - - .space (0x100) -a: - .dw 1 - .dw 2 - .dw 3 - .dw 4 - .dw 5 - .dw 6 - .dw 7 - .dw 8 - .dw 9 - .dw 0xa diff --git a/sim/testsuite/sim/bfin/stk3.s b/sim/testsuite/sim/bfin/stk3.s deleted file mode 100644 index 131f8c5..0000000 --- a/sim/testsuite/sim/bfin/stk3.s +++ /dev/null @@ -1,106 +0,0 @@ -// load up some registers. -// setup up a global pointer table and load some state. -// save the machine state and clear some of the values. -// then restore and assert some of the values to ensure that -// we maintain consitent machine state. - -# mach: bfin - -.include "testutils.inc" - start - - R0 = 1; - R1 = 2; - R2 = 3; - R3 = -7; - R4 = 4; - R5 = 5; - R6 = 6; - R7 = 7; - - loadsym P0, a; - P1.L = 0x1000; - _DBG P0; - _DBG P1; - SP = P0; - FP = P0; - - CALL try; - - P1 = [ P0 ++ ]; - P2 = [ P0 ++ ]; - P0 += 4; - P4 = [ P0 ++ ]; - P5 = [ P0 ++ ]; - [ -- SP ] = ( R7:0, P5:0 ); - _DBG SP; - _DBG FP; - R0 = R0 ^ R0; - R1 = R1 ^ R1; - R2 = R2 ^ R2; - R4 = R4 ^ R4; - R5 = R5 ^ R5; - R6 = R6 ^ R6; - R7 = R7 ^ R7; - ( R7:0, P5:0 ) = [ SP ++ ]; - DBGA ( R0.L , 1 ); - DBGA ( R1.L , 2 ); - DBGA ( R2.L , 3 ); - DBGA ( R3.L , 0xfff9); - DBGA ( R4.L , 4 ); - DBGA ( R5.L , 5 ); - DBGA ( R6.L , 6 ); - DBGA ( R7.L , 7 ); - R0 = SP; - loadsym R1, a; - CC = R0 == R1; - IF !CC JUMP abrt; - R0 = FP; - CC = R0 == R1; - CC = R0 == R1; - IF !CC JUMP abrt; - pass -abrt: - fail; - -try: - LINK 0; - [ -- SP ] = ( R7:0, P5:0 ); - R7 = 0x1234 (X); - [ -- SP ] = R7; - CALL bar; - SP += 4; - ( R7:0, P5:0 ) = [ SP ++ ]; - UNLINK; - RTS; - -bar: - LINK 0; - [ -- SP ] = ( R7:0, P5:0 ); - R0 = [ FP + 8 ]; - DBGA ( R0.L , 0x1234 ); - ( R7:0, P5:0 ) = [ SP ++ ]; - UNLINK; - RTS; - - .data -_gptab: - .dw 0x200 - .dw 0x000 - .dw 0x300 - .dw 0x400 - .dw 0x500 - .dw 0x600 - - .space (0x100) -a: - .dw 1 - .dw 2 - .dw 3 - .dw 4 - .dw 5 - .dw 6 - .dw 7 - .dw 8 - .dw 9 - .dw 0xa diff --git a/sim/testsuite/sim/bfin/stk4.s b/sim/testsuite/sim/bfin/stk4.s deleted file mode 100644 index 797aa78..0000000 --- a/sim/testsuite/sim/bfin/stk4.s +++ /dev/null @@ -1,110 +0,0 @@ -// load up some registers. -// setup up a global pointer table and load some state. -// save the machine state and clear some of the values. -// then restore and assert some of the values to ensure that -// we maintain consitent machine state. -# mach: bfin - -.include "testutils.inc" - start - - R0 = 1; - R1 = 2; - R2 = 3; - R3 = -7; - R4 = 4; - R5 = 5; - R6 = 6; - R7 = 7; - - loadsym P0, a; - P1.L = 0x1000; - _DBG P0; - _DBG P1; - SP = P0; - FP = P0; - - CALL try; - - P1 = [ P0 ++ ]; - P2 = [ P0 ++ ]; - P0 += 4; - P4 = [ P0 ++ ]; - P5 = [ P0 ++ ]; - [ -- SP ] = ( R7:0, P5:0 ); - _DBG SP; - _DBG FP; - R0 = R0 ^ R0; - R1 = R1 ^ R1; - R2 = R2 ^ R2; - R4 = R4 ^ R4; - R5 = R5 ^ R5; - R6 = R6 ^ R6; - R7 = R7 ^ R7; - ( R7:0, P5:0 ) = [ SP ++ ]; - DBGA ( R0.L , 1 ); - DBGA ( R1.L , 2 ); - DBGA ( R2.L , 3 ); - DBGA ( R3.L , 0xfff9 ); - DBGA ( R4.L , 4 ); - DBGA ( R5.L , 5 ); - DBGA ( R6.L , 6 ); - DBGA ( R7.L , 7 ); - R0 = SP; - loadsym R1, a; - CC = R0 == R1; - IF !CC JUMP abrt; - R0 = FP; - CC = R0 == R1; - CC = R0 == R1; - IF !CC JUMP abrt; - pass -abrt: - fail; - -try: - LINK 0; - [ -- SP ] = ( R7:0, P5:0 ); - R7 = 0x1234 (X); - [ -- SP ] = R7; - CALL bar; - R7 = [ SP ++ ]; - ( R7:0, P5:0 ) = [ SP ++ ]; - UNLINK; - RTS; - -bar: - LINK 0; - [ -- SP ] = ( R7:0, P5:0 ); - R0 = [ FP + 8 ]; - DBGA ( R0.L , 0x1234 ); - CALL foo; - ( R7:0, P5:0 ) = [ SP ++ ]; - UNLINK; - RTS; - -foo: - DBGA ( R0.L , 0x1234 ); - RTS; - - .data -_gptab: - .dw 0x200 - .dw 0x000 - .dw 0x300 - .dw 0x400 - .dw 0x500 - .dw 0x600 - - .space (0x100) -a: - .dw 1 - .dw 2 - .dw 3 - .dw 4 - .dw 5 - .dw 6 - .dw 7 - .dw 8 - .dw 9 - .dw 0xa diff --git a/sim/testsuite/sim/bfin/stk5.s b/sim/testsuite/sim/bfin/stk5.s deleted file mode 100644 index e3a8fca..0000000 --- a/sim/testsuite/sim/bfin/stk5.s +++ /dev/null @@ -1,34 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - SP += -12; - FP = SP; - CALL _foo; - - pass - - -_printf: - LINK 0; - [ -- SP ] = ( R7:7, P5:4 ); - R5 = [ FP + 8 ]; - DBGA ( R5.L , 0x1234 ); - R5 = [ FP + 12 ]; - DBGA ( R5.L , 0xdead ); - ( R7:7, P5:4 ) = [ SP ++ ]; - UNLINK; - RTS; - -_foo: - LINK 0; - R5 = 0xdead (Z); - [ -- SP ] = R5; - R5 = 0x1234 (X); - [ -- SP ] = R5; - CALL _printf; - P5 = 8; - SP = SP + P5; - UNLINK; - RTS; diff --git a/sim/testsuite/sim/bfin/stk6.s b/sim/testsuite/sim/bfin/stk6.s deleted file mode 100644 index 89a5e60..0000000 --- a/sim/testsuite/sim/bfin/stk6.s +++ /dev/null @@ -1,58 +0,0 @@ -// setup a dummy stack and put values in memory 0,1,2,3...n -// then restore registers with pop instruction. -# mach: bfin - -.include "testutils.inc" - start - - SP += -12; - - P1 = SP; - R1 = 0; - P5.L = 0xdead; - SP += -((8+5)*4); // lets move the stack pointer and include the current location. i.e. 5 - P4 = (8+6); // 8 data registers and 6 pointer registers are being stored. - LSETUP ( ls0 , le0 ) LC0 = P4; -ls0: - R1 += 1; -le0: - [ P1-- ] = R1; - - ( R7:0, P5:0 ) = [ SP ++ ]; - - DBGA ( R0.L , 1 ); - DBGA ( R1.L , 2 ); - DBGA ( R2.L , 3 ); - DBGA ( R3.L , 4 ); - DBGA ( R4.L , 5 ); - DBGA ( R5.L , 6 ); - DBGA ( R6.L , 7 ); - DBGA ( R7.L , 8 ); - R0 = P0; DBGA ( R0.L , 9 ); - R0 = P1; DBGA ( R0.L , 10 ); - R0 = P2; DBGA ( R0.L , 11 ); - R0 = P3; DBGA ( R0.L , 12 ); - R0 = P4; DBGA ( R0.L , 13 ); - R0 = P5; DBGA ( R0.L , 14 ); - R0 = 1; - - [ -- SP ] = ( R7:0, P5:0 ); - ( R7:0, P5:0 ) = [ SP ++ ]; - - DBGA ( R0.L , 1 ); - DBGA ( R1.L , 2 ); - DBGA ( R2.L , 3 ); - DBGA ( R3.L , 4 ); - DBGA ( R4.L , 5 ); - DBGA ( R5.L , 6 ); - DBGA ( R6.L , 7 ); - DBGA ( R7.L , 8 ); - R0 = P0; DBGA ( R0.L , 9 ); - R0 = P1; DBGA ( R0.L , 10 ); - R0 = P2; DBGA ( R0.L , 11 ); - R0 = P3; DBGA ( R0.L , 12 ); - R0 = P4; DBGA ( R0.L , 13 ); - R0 = P5; DBGA ( R0.L , 14 ); - R0 = 1; - - pass diff --git a/sim/testsuite/sim/bfin/syscfg.s b/sim/testsuite/sim/bfin/syscfg.s deleted file mode 100644 index 05ebeec..0000000 --- a/sim/testsuite/sim/bfin/syscfg.s +++ /dev/null @@ -1,25 +0,0 @@ -# Blackfin testcase for SYSCFG register -# mach: bfin - - .include "testutils.inc" - - .macro syscfg_test val:req - imm32 R0, \val - R0 = SYSCFG; - SYSCFG = R0; - R1 = SYSCFG; - CC = R0 == R1; - IF !CC JUMP 1f; - .endm - - start - - syscfg_test 0 - syscfg_test 1 - syscfg_test -1 - syscfg_test 0x12345678 - # leave in sane state - syscfg_test 0x30 - - pass -1: fail diff --git a/sim/testsuite/sim/bfin/tar10622.s b/sim/testsuite/sim/bfin/tar10622.s deleted file mode 100644 index c3c0a37..0000000 --- a/sim/testsuite/sim/bfin/tar10622.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - r2.l = 0x1234; - r2.h = 0xff90; - - r4=8; - i2=r2; - m2 = 4; - a0 = 0; - r1.l = (a0 += r4.l *r4.l) (IS) || I2 += m2 || nop; - - r0 = i2; - - dbga(r0.l, 0x1238); - dbga(r0.h, 0xff90); - - pass diff --git a/sim/testsuite/sim/bfin/test-dma.h b/sim/testsuite/sim/bfin/test-dma.h deleted file mode 100644 index 2227ff6..0000000 --- a/sim/testsuite/sim/bfin/test-dma.h +++ /dev/null @@ -1,28 +0,0 @@ -struct bfin_dmasg { - bu32 next_desc_addr; - bu32 start_addr; - bu16 cfg; - bu16 x_count; - bs16 x_modify; - bu16 y_count; - bs16 y_modify; -} __attribute__((packed)); - -struct bfin_dma { - bu32 next_desc_ptr; - bu32 start_addr; - - bu16 BFIN_MMR_16 (config); - bu32 _pad0; - bu16 BFIN_MMR_16 (x_count); - bs16 BFIN_MMR_16 (x_modify); - bu16 BFIN_MMR_16 (y_count); - bs16 BFIN_MMR_16 (y_modify); - bu32 curr_desc_ptr, curr_addr; - bu16 BFIN_MMR_16 (irq_status); - bu16 BFIN_MMR_16 (peripheral_map); - bu16 BFIN_MMR_16 (curr_x_count); - bu32 _pad1; - bu16 BFIN_MMR_16 (curr_y_count); - bu32 _pad2; -}; diff --git a/sim/testsuite/sim/bfin/test.h b/sim/testsuite/sim/bfin/test.h deleted file mode 100644 index 38788f8..0000000 --- a/sim/testsuite/sim/bfin/test.h +++ /dev/null @@ -1,134 +0,0 @@ -#ifndef __ASSEMBLER__ -typedef unsigned long bu32; -typedef long bs32; -typedef unsigned short bu16; -typedef short bs16; -typedef unsigned char bu8; -typedef char bs8; -#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) -#define BFIN_MMR_16(mmr) mmr, __pad_##mmr -#include "test-dma.h" -#else -#define __ADSPBF537__ /* XXX: Hack for .S files. */ -#endif -#ifndef __FDPIC__ -#include -#endif - -/* AZ AN AC0_COPY V_COPY CC AQ RND_MOD AC0 AC1 AV0 AV0S AV1 AV1S V VS */ - -#define _AZ (1 << 0) -#define _AN (1 << 1) -#define _AC0_COPY (1 << 2) -#define _V_COPY (1 << 3) -#define _CC (1 << 5) -#define _AQ (1 << 6) -#define _RND_MOD (1 << 8) -#define _AC0 (1 << 12) -#define _AC1 (1 << 13) -#define _AV0 (1 << 16) -#define _AV0S (1 << 17) -#define _AV1 (1 << 18) -#define _AV1S (1 << 19) -#define _V (1 << 24) -#define _VS (1 << 25) - -#define _SET 1 -#define _UNSET 0 - -#define PASS do { puts ("pass"); _exit (0); } while (0) -#define FAIL do { puts ("fail"); _exit (1); } while (0) -#define DBG_PASS do { asm volatile ("outc 'p'; outc 'a'; outc 's'; outc 's'; outc '\n'; hlt;"); } while (1) -#define DBG_FAIL do { asm volatile ("outc 'f'; outc 'a'; outc 'i'; outc 'l'; outc '\n'; abort;"); } while (1) - -#define HI(x) (((x) >> 16) & 0xffff) -#define LO(x) ((x) & 0xffff) - -#define INIT_R_REGS(val) init_r_regs val -#define INIT_P_REGS(val) init_p_regs val -#define INIT_B_REGS(val) init_b_regs val -#define INIT_I_REGS(val) init_i_regs val -#define INIT_L_REGS(val) init_l_regs val -#define INIT_M_REGS(val) init_m_regs val -#define include(...) -#define CHECK_INIT_DEF(...) nop; -#define CHECK_INIT(...) nop; -#define CHECKMEM32(...) -#define GEN_INT_INIT(...) nop; - -#define LD32_LABEL(reg, sym) loadsym reg, sym -#define LD32(reg, val) imm32 reg, val -#define CHECKREG(reg, val) CHECKREG reg, val -#define CHECKREG_SYM_JUMPLESS(reg, sym, scratch_reg) \ - loadsym scratch_reg, sym; \ - cc = reg == scratch_reg; \ - /* Need to avoid jumping for trace buffer. */ \ - if !cc jump fail_lvl; -#define CHECKREG_SYM(reg, sym, scratch_reg) \ - loadsym scratch_reg, sym; \ - cc = reg == scratch_reg; \ - if cc jump 9f; \ - dbg_fail; \ -9: - -#define WR_MMR(mmr, val, mmr_reg, val_reg) \ - imm32 mmr_reg, mmr; \ - imm32 val_reg, val; \ - [mmr_reg] = val_reg; -#define WR_MMR_LABEL(mmr, sym, mmr_reg, sym_reg) \ - loadsym sym_reg, sym; \ - imm32 mmr_reg, mmr; \ - [mmr_reg] = sym_reg; -#define RD_MMR(mmr, mmr_reg, val_reg) \ - imm32 mmr_reg, mmr; \ - val_reg = [mmr_reg]; - -/* Legacy CPLB bits */ -#define CPLB_L1_CACHABLE CPLB_L1_CHBL -#define CPLB_USER_RO CPLB_USER_RD - -#define DATA_ADDR_1 0xff800000 -#define DATA_ADDR_2 0xff900000 -#define DATA_ADDR_3 (DATA_ADDR_1 + 0x2000) - -/* The libgloss headers omit these defines. */ -#define EVT_OVERRIDE 0xFFE02100 -#define EVT_IMASK IMASK - -#define PAGE_SIZE_1K PAGE_SIZE_1KB -#define PAGE_SIZE_4K PAGE_SIZE_4KB -#define PAGE_SIZE_1M PAGE_SIZE_1MB -#define PAGE_SIZE_4M PAGE_SIZE_4MB - -#define CPLB_USER_RW (CPLB_USER_RD | CPLB_USER_WR) - -#define DMC_AB_SRAM 0x0 -#define DMC_AB_CACHE 0xc -#define DMC_ACACHE_BSRAM 0x8 - -#define CPLB_L1SRAM (1 << 5) -#define CPLB_DA0ACC (1 << 6) - -#define FAULT_CPLB0 (1 << 0) -#define FAULT_CPLB1 (1 << 1) -#define FAULT_CPLB2 (1 << 2) -#define FAULT_CPLB3 (1 << 3) -#define FAULT_CPLB4 (1 << 4) -#define FAULT_CPLB5 (1 << 5) -#define FAULT_CPLB6 (1 << 6) -#define FAULT_CPLB7 (1 << 7) -#define FAULT_CPLB8 (1 << 8) -#define FAULT_CPLB9 (1 << 9) -#define FAULT_CPLB10 (1 << 10) -#define FAULT_CPLB11 (1 << 11) -#define FAULT_CPLB12 (1 << 12) -#define FAULT_CPLB13 (1 << 13) -#define FAULT_CPLB14 (1 << 14) -#define FAULT_CPLB15 (1 << 15) -#define FAULT_READ (0 << 16) -#define FAULT_WRITE (1 << 16) -#define FAULT_USER (0 << 17) -#define FAULT_SUPV (1 << 17) -#define FAULT_DAG0 (0 << 18) -#define FAULT_DAG1 (1 << 18) -#define FAULT_ILLADDR (1 << 19) diff --git a/sim/testsuite/sim/bfin/testset.s b/sim/testsuite/sim/bfin/testset.s deleted file mode 100644 index 57eaa5c..0000000 --- a/sim/testsuite/sim/bfin/testset.s +++ /dev/null @@ -1,73 +0,0 @@ -# Blackfin testcase for playing with TESTSET -# mach: bfin - - .include "testutils.inc" - - start - - .macro _ts val:req - /* Load value to the external data storage */ - imm32 R0, \val - [P4] = R0; - FLUSHINV[P4]; - SSYNC; - mnop; - - imm32 R1, 0xdeadbeef - imm32 R2, 0xdeadbeef - - TESTSET (P4); - SSYNC; - mnop; - mnop; - - /* TESTSET will set CC based on low byte == 0 */ - .if \val & 0xff - if CC jump 1f; - .else - if ! CC jump 1f; - .endif - - /* Regardless of CC, the byte MSB is set to 1 */ - imm32 R1, \val | 0x80 - - /* Make sure the result is what we want */ - R2 = [P4]; - FLUSHINV[P4]; - SSYNC; - mnop; - CC = R2 == R1; - if ! CC jump 1f; - jump 2f; -1: fail -2: - .endm - .macro ts val:req - _ts \val - _ts ~(\val) - .endm - - loadsym P4, _data - - ts 0x00000000 - ts 0x00000011 - ts 0x11111111 - ts 0x11111101 - ts 0x11111110 - ts 0x111111bb - ts 0xaaaaaa00 - ts 0xabcd2222 - ts 0x000000bb - ts 0x55555555 - ts 0x5555550a - ts 0x00100010 - ts 0x00100100 - ts 0x33333000 - ts 0x000000aa - - pass - -.data -_data: -.long 0 -.size _data, .-_data diff --git a/sim/testsuite/sim/bfin/testset2.s b/sim/testsuite/sim/bfin/testset2.s deleted file mode 100644 index 66b50be..0000000 --- a/sim/testsuite/sim/bfin/testset2.s +++ /dev/null @@ -1,37 +0,0 @@ -// testset instruction -//TESTSET is an atomic test-and-set. -//If the lock was not set prior to the TESTSET, cc is set, the lock bit is set, -//and this processor gets the lock. If the lock was set -//prior to the TESTSET, cc is cleared, the lock bit is still set, -//but the processor fails to acquire the lock. -# mach: bfin - - .include "testutils.inc" - - start - - loadsym P0, datalabel; - - R0 = 0; - CC = R0; - R0 = B [ P0 ] (Z); - DBGA ( R0.L , 0 ); - TESTSET ( P0 ); - R0 = CC; - DBGA ( R0.L , 1 ); - R0 = B [ P0 ] (Z); - DBGA ( R0.L , 0x80 ); - - R0 = 0; - CC = R0; - TESTSET ( P0 ); - R0 = CC; - DBGA ( R0.L , 0 ); - R0 = B [ P0 ] (Z); - DBGA ( R0.L , 0x80 ); - - pass - - .data -datalabel: - .dw 0 diff --git a/sim/testsuite/sim/bfin/testutils.inc b/sim/testsuite/sim/bfin/testutils.inc deleted file mode 100644 index 991d167..0000000 --- a/sim/testsuite/sim/bfin/testutils.inc +++ /dev/null @@ -1,295 +0,0 @@ -# R0 and P0 are used as tmps, consider them call clobbered by these macros. - -# To build for hardware, use: -# bfin-linux-uclibc-gcc -nostdlib -g -Wa,--defsym,BFIN_HOST=1 foo.s - -# MACRO: start -# All assembler tests should start with a call to "start" - .macro start - .text - # Pad with EMUEXCPT to make sure "jump to 0" always fails -__panic: - .rep 0xf - .word 0x0025 - .endr - abort; - jump __panic; - - .global __pass -__pass: - write 1, _passmsg, 5 - exit 0 -.ifdef BFIN_JTAG -__emu_out: - /* DBGSTAT */ - imm32 P0 0xFFE05008; - -1: R7 = [P0]; - CC = BITTST (R7,0); - IF CC JUMP 1b; - - EMUDAT = R0; - RTS; -.endif - .global __fail -__fail: -.ifndef BFIN_HOST - P0.H = _rets; - P0.L = _rets; - R0 = RETS; - R0 += -4; - P1 = 8; - R2 = '9'; - LSETUP (1f, 3f) LC0 = P1; -1: - R1 = R0; - R1 >>= 28; - R1 += 0x30; - CC = R2 < R1; - IF !CC jump 2f; - R1 += 7; -2: - B[P0++] = R1; -3: - R0 <<= 4; - - write 1, _failmsg, 22 -.else - write 1, _failmsg, 5 -.endif - exit 1 - -.ifndef BFIN_HOST - .data -_failmsg: - .ascii "fail at PC=0x" -_rets: - .ascii "12345678\n" -_passmsg: - .ascii "pass\n" - .align 4 -_params: - .long 0 - .long 0 - .long 0 - .long 0 - - .text - .global __start -__start: -.else -.global ___uClibc_main; -___uClibc_main: -.global _main; -_main: -.endif - .endm - -# MACRO: system_call -# Make a libgloss/Linux system call - .macro system_call nr:req - P0 = \nr (X); - EXCPT 0; - .endm - -# MACRO: exit -# Quit the current test - .macro exit rc:req - R0 = \rc (X); -.ifndef BFIN_HOST - P0.H = _params; - P0.L = _params; - [P0] = R0; - R0 = P0; -.endif - system_call 1 - .endm - -# MACRO: pass -# Write 'pass' to stdout via syscalls and quit; -# meant for non-OS operating environments - .macro pass - CALL __pass; - .endm - -# MACRO: fail -# Write 'fail' to stdout via syscalls and quit; -# meant for non-OS operating environments - .macro fail - CALL __fail; - .endm - -# MACRO: write -# Just like the write() C function; uses system calls - .macro write fd:req, buf:req, count:req -.ifndef BFIN_HOST - P0.H = _params; - P0.L = _params; - R0 = \fd (X); - [P0] = R0; - R0.H = \buf; - R0.L = \buf; - [P0 + 4] = R0; - R0 = \count (X); - [P0 + 8] = R0; - R0 = P0; - system_call 5 -.endif - .endm - -# MACRO: outc_str -# Output a string using the debug OUTC insn - .macro outc_str ch:req, more:vararg - OUTC \ch; - .ifnb \more - outc_str \more - .endif - .endm - -# MACRO: dbg_pass -# Write 'pass' to stdout and quit (all via debug insns); -# meant for OS operating environments - .macro dbg_pass -.ifdef BFIN_JTAG - R0 = 6; - CALL __emu_out; - R0.L = 0x6170; /* 'p'=0x70 'a'=0x70 */ - R0.H = 0x7373; /* 's'=0x73 */ - CALL __emu_out; - - R0.L = 0x0A; /* newline */ - R0.H = 0x0000; - CALL __emu_out; -1: - EMUEXCPT; - JUMP 1b; -.else - outc_str 'p', 'a', 's', 's', '\n' - HLT; -.endif - .endm - -# MACRO: dbg_fail -# Write 'fail' to stdout and quit (all via debug insns); -# meant for OS operating environments - .macro dbg_fail -.ifdef BFIN_JTAG - R0 = 6; - CALL __emu_out; - R0.L = 0x6166; /* 'f'=0x66 'a'=0x61 */ - R0.H = 0x6c69; /* 'i'=0x69 'l'=0x6c */ - CALL __emu_out; - - R0.L = 0x0A; /* newline */ - R0.H = 0x0000; - CALL __emu_out; -1: - EMUEXCPT; - JUMP 1b; -.else - outc_str 'f', 'a', 'i', 'l', '\n' -.endif - ABORT; - .endm - -# MACRO: imm32 -# Load a 32bit immediate directly into a register - .macro imm32 reg:req, val:req - .if (\val) & ~0x7fff - \reg\().L = ((\val) & 0xffff); - \reg\().H = (((\val) >> 16) & 0xffff); - .else - \reg = \val; - .endif - .endm - -# MACRO: dmm32 -# Load a 32bit immediate indirectly into a register - .macro dmm32 reg:req, val:req - [--SP] = R0; - imm32 R0, \val - \reg = R0; - R0 = [SP++]; - .endm - -# MACRO: loadsym -# Load a symbol directly into a register -.ifndef BFIN_HOST - .macro loadsym reg:req, sym:req, offset=0 - \reg\().L = (\sym\() + \offset\()); - \reg\().H = (\sym\() + \offset\()); - .endm -.else - .macro loadsym reg:req, sym:req, offset=0 - [--SP] = R0; - R0 = [P3 + \sym\()@GOT17M4]; - .if \offset - [--SP] = R1; - R1 = \offset\() (Z); - R0 = R0 + R1; - R1 = [SP++]; - .endif - \reg = R0; - R0 = [SP++]; - .endm -.endif - -# MACRO: CHECKREG -# Use debug insns to verify the value of a register matches - .macro CHECKREG reg:req, val:req - DBGAL (\reg, ((\val) & 0xffff)); - DBGAH (\reg, (((\val) >> 16) & 0xffff)); - .endm - -# internal helper macros; ignore them - .macro __init_regs reg:req, max:req, x:req, val:req - .ifle (\x - \max) - imm32 \reg\()\x, \val - .endif - .endm - .macro _init_regs reg:req, max:req, val:req - __init_regs \reg, \max, 0, \val - __init_regs \reg, \max, 1, \val - __init_regs \reg, \max, 2, \val - __init_regs \reg, \max, 3, \val - __init_regs \reg, \max, 4, \val - __init_regs \reg, \max, 5, \val - __init_regs \reg, \max, 6, \val - __init_regs \reg, \max, 7, \val - .endm - -# MACRO: init_r_regs -# MACRO: init_p_regs -# MACRO: init_b_regs -# MACRO: init_i_regs -# MACRO: init_l_regs -# MACRO: init_m_regs -# Set the specified group of regs to the specified value - .macro init_r_regs val:req - _init_regs R, 7, \val - .endm - .macro init_p_regs val:req - _init_regs P, 5, \val - .endm - .macro init_b_regs val:req - _init_regs B, 3, \val - .endm - .macro init_i_regs val:req - _init_regs I, 3, \val - .endm - .macro init_l_regs val:req - _init_regs L, 3, \val - .endm - .macro init_m_regs val:req - _init_regs M, 3, \val - .endm - - // the test framework needs things to be quiet, so don't - // print things out by default. - .macro _DBG reg:req - //DBG \reg; - .endm - - .macro _DBGCMPLX reg:req - // - .endm diff --git a/sim/testsuite/sim/bfin/unlink.S b/sim/testsuite/sim/bfin/unlink.S deleted file mode 100644 index 978d39e..0000000 --- a/sim/testsuite/sim/bfin/unlink.S +++ /dev/null @@ -1,68 +0,0 @@ -# Blackfin testcase for unlink insn with any immediate value -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - - start - - /* Set up exception handler */ - imm32 P4, EVT3; - loadsym R1, _evx; - [P4] = R1; - - /* Lower to the code we want to single step through */ - loadsym P1, _usr; - RETI = P1; - - imm32 FP, 0x800000 - imm32 R0, 0x12345678; - [FP] = R0; - imm32 R0, 0x87654321; - [FP + 4] = R0; - - RTI; - -_usr: - imm32 FP, 0x800000 - - .byte 0x01, 0xe8 -.Linsn: - .byte 0, 0 - - imm32 R0, 0x12345678; - R1 = FP; - CC = R0 == R1; - IF !CC jump _fail; - - imm32 R0, 0x87654321; - R1 = RETS; - CC = R0 == R1; - IF !CC jump _fail; - - imm32 R0, 0x800008; - R1 = SP; - CC = R0 == R1; - IF !CC jump _fail; - - loadsym P0, .Linsn; - R0 = W[P0]; - R0 += 1; - W[P0] = R0; - SSYNC; - - R0 = R0.L; - CC = R0 == 0; - IF CC jump _pass; - jump _usr; - - .align 4; -_evx: - dbg_fail; - -_pass: - dbg_pass; - -_fail: - dbg_fail; diff --git a/sim/testsuite/sim/bfin/up0.s b/sim/testsuite/sim/bfin/up0.s deleted file mode 100644 index ed705b8..0000000 --- a/sim/testsuite/sim/bfin/up0.s +++ /dev/null @@ -1,41 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - - R0 = 1; - DBGA ( R0.L , 1 ); - - R1.L = 2; - DBGA ( R1.L , 2 ); - - R2 = 3; - A0.x = R2; - R0 = A0.x; - DBGA ( R0.L , 3 ); - - P0 = 4; - R0 = P0; - DBGA ( R0.L , 4 ); - - R0 = 45; - R1 = 22; - A1 = R0.L * R1.L, A0 = R0.H * R1.H; - _DBG A1; - - loadsym I2, foo; - P0 = I2; - R0 = 0x0333 (X); - R3 = 0x0444 (X); - - R3.L = ( A0 = R0.L * R0.L ) || [ I2 ++ ] = R3 || NOP; - DBGA ( R3.L , 0x14 ); - R0 = [ P0 ]; - DBGA ( R0.L , 0x0444 ); - - pass - - .data -foo: - .space (0x10); diff --git a/sim/testsuite/sim/bfin/usp.S b/sim/testsuite/sim/bfin/usp.S deleted file mode 100644 index e77ff52..0000000 --- a/sim/testsuite/sim/bfin/usp.S +++ /dev/null @@ -1,50 +0,0 @@ -# Blackfin testcase for USP handling -# mach: bfin -# sim: --environment operating - -#include "test.h" - .include "testutils.inc" - - start - - imm32 R5, 0x44455566 - imm32 R6, 0x12345678 - imm32 R7, 0x9abcdef0 - - imm32 p0, EVT3; - loadsym r0, exception; - [p0] = r0; - - loadsym r0, usermode; - reti = r0; - - SP = R6; - USP = R7; - RTI; - -usermode: - # SP should now be USP - R1 = SP; - CC = R1 == R7; - IF !CC JUMP fail; - - # Now set SP to another value - SP = R5; - - # Move up to exception space - EXCPT 0; - -exception: - # SP should be the same as original, but USP should change - R1 = SP; - CC = R1 == R6; - IF !CC JUMP fail; - - R1 = USP; - CC = R1 == R5; - IF !CC JUMP fail; - - dbg_pass - -fail: - dbg_fail diff --git a/sim/testsuite/sim/bfin/vec-abs-2.S b/sim/testsuite/sim/bfin/vec-abs-2.S deleted file mode 100644 index d171e83..0000000 --- a/sim/testsuite/sim/bfin/vec-abs-2.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for vector ABS instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x0; - R0.L = 0x8000; - R1 = ABS R0 (V); - R7 = ASTAT; - R2.H = 0x0; - R2.L = 0x7fff; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AN */ - R3.H = HI(_AN); - R3.L = LO(_AN); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: AZ V V_COPY VS */ - R3.H = HI(_AZ|_V|_V_COPY|_VS); - R3.L = LO(_AZ|_V|_V_COPY|_VS); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC0 AC0_COPY AC1 */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/vec-abs-3.S b/sim/testsuite/sim/bfin/vec-abs-3.S deleted file mode 100644 index bf003a1..0000000 --- a/sim/testsuite/sim/bfin/vec-abs-3.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for vector ABS instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x8000; - R0.L = 0x0; - R1 = ABS R0 (V); - R7 = ASTAT; - R2.H = 0x7fff; - R2.L = 0x0; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AN */ - R3.H = HI(_AN); - R3.L = LO(_AN); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: AZ V V_COPY VS */ - R3.H = HI(_AZ|_V|_V_COPY|_VS); - R3.L = LO(_AZ|_V|_V_COPY|_VS); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC0 AC0_COPY AC1 */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/vec-abs.S b/sim/testsuite/sim/bfin/vec-abs.S deleted file mode 100644 index 97ec84f..0000000 --- a/sim/testsuite/sim/bfin/vec-abs.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for vector ABS instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x1234; - R0.L = 0xcdef; - R1 = ABS R0 (V); - R7 = ASTAT; - R2.H = 0x1234; - R2.L = 0x3211; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AZ AN V V_COPY */ - R3.H = HI(_AZ|_AN|_V|_V_COPY); - R3.L = LO(_AZ|_AN|_V|_V_COPY); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: */ - R3.H = HI(0); - R3.L = LO(0); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/vec-neg-2.S b/sim/testsuite/sim/bfin/vec-neg-2.S deleted file mode 100644 index 9ea15ec..0000000 --- a/sim/testsuite/sim/bfin/vec-neg-2.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for vector negate instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x0; - R0.L = 0x8000; - R1 = -R0 (V); - R7 = ASTAT; - R2.H = 0x0; - R2.L = 0x7fff; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AN AC0 AC0_COPY */ - R3.H = HI(_AN|_AC0|_AC0_COPY); - R3.L = LO(_AN|_AC0|_AC0_COPY); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: AZ V V_COPY VS AC1 */ - R3.H = HI(_AZ|_V|_V_COPY|_VS|_AC1); - R3.L = LO(_AZ|_V|_V_COPY|_VS|_AC1); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/vec-neg-3.S b/sim/testsuite/sim/bfin/vec-neg-3.S deleted file mode 100644 index d748213..0000000 --- a/sim/testsuite/sim/bfin/vec-neg-3.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for vector negate instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x8000; - R0.L = 0x0; - R1 = -R0 (V); - R7 = ASTAT; - R2.H = 0x7fff; - R2.L = 0x0; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AN AC0 AC0_COPY */ - R3.H = HI(_AN|_AC1); - R3.L = LO(_AN|_AC1); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: AZ V V_COPY VS AC1 */ - R3.H = HI(_AZ|_V|_V_COPY|_VS|_AC0|_AC0_COPY); - R3.L = LO(_AZ|_V|_V_COPY|_VS|_AC0|_AC0_COPY); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/vec-neg.S b/sim/testsuite/sim/bfin/vec-neg.S deleted file mode 100644 index 1b9b076..0000000 --- a/sim/testsuite/sim/bfin/vec-neg.S +++ /dev/null @@ -1,42 +0,0 @@ -# Blackfin testcase for vector negate instruction -# mach: bfin - -#include "test.h" - - .include "testutils.inc" - - start - - .global _test -_test: - R6 = ASTAT; - R0.H = 0x1234; - R0.L = 0xcdef; - R1 = -R0 (V); - R7 = ASTAT; - R2.H = 0xedcc; - R2.L = 0x3211; - CC = R1 == R2; - IF !CC JUMP 1f; - /* CLEARED: AZ V V_COPY AC0 AC0_COPY AC1 */ - R3.H = HI(_AZ|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); - R3.L = LO(_AZ|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); - R4 = R7 & R3; - CC = R4 == 0; - IF !CC JUMP 1f; - /* SET: AN */ - R3.H = HI(_AN); - R3.L = LO(_AN); - R4 = R7 & R3; - CC = R3 == R4; - IF !CC JUMP 1f; - /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS */ - R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS); - R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS); - R4 = R6 & R3; - R5 = R7 & R3; - CC = R4 == R5; - IF !CC JUMP 1f; - pass -1: - fail diff --git a/sim/testsuite/sim/bfin/vecadd.s b/sim/testsuite/sim/bfin/vecadd.s deleted file mode 100644 index 7e568ec..0000000 --- a/sim/testsuite/sim/bfin/vecadd.s +++ /dev/null @@ -1,65 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - -// create two short vectors v_a, v_b -// where each element of v_a is the index -// where each element of v_b is 128-index - R2 = 0; - loadsym P0, v_a; - loadsym P1, v_b; - P2 = 0; - R3 = 128 (X); - R0 = 0; - R1 = 128 (X); -L$1: - W [ P0 ++ ] = R0; - W [ P1 ++ ] = R1; - R0 += 1; - R1 += -1; - CC = R0 < R3; - IF CC JUMP L$1 (BP); - - loadsym P0, v_a; - loadsym P1, v_b; - - CALL vecadd; - - loadsym P0, v_c; - R2 = 0; - R3 = 128 (X); -L$3: - R0 = W [ P0 ++ ] (X); - DBGA ( R0.L , 128 ); - R2 += 1; - CC = R2 < R3; - IF CC JUMP L$3; - _DBG R6; - pass - -vecadd: - - loadsym I0, v_a; - loadsym I1, v_b; - loadsym I2, v_c; - - P5 = 128 (X); - LSETUP ( L$2 , L$2end ) LC0 = P5 >> 1; - R0 = [ I0 ++ ]; - R1 = [ I1 ++ ]; -L$2: - R2 = R0 +|+ R1 || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; -L$2end: - [ I2 ++ ] = R2; - - - RTS; - - .data -v_a: - .space (512); -v_b: - .space (512); -v_c: - .space (512); diff --git a/sim/testsuite/sim/bfin/vit_max.s b/sim/testsuite/sim/bfin/vit_max.s deleted file mode 100644 index 35eaa41..0000000 --- a/sim/testsuite/sim/bfin/vit_max.s +++ /dev/null @@ -1,57 +0,0 @@ -# Blackfin testcase for VIT_MAX (taken from PRM) -# mach: bfin - - .include "testutils.inc" - - start - - imm32 R3, 0xFFFF0000 - imm32 R2, 0x0000FFFF - A0 = 0; - R5 = VIT_MAX (R3, R2) (ASL); - R4 = 0 (x); - CC = R5 == R4; - IF !CC JUMP 1f; - imm32 R6, 0x00000002 - R4 = A0; - CC = R4 == R6; - IF !CC JUMP 1f; - - imm32 R1, 0xFEEDBEEF - imm32 R0, 0xDEAF0000 - A0 = 0; - R7 = VIT_MAX (R1, R0) (ASR); - imm32 R4, 0xFEED0000 - CC = R4 == R7; - IF !CC JUMP 1f; - imm32 R6, 0x80000000 - R2 = A0.W; - CC = R2 == R6; - IF !CC JUMP 1f; - - imm32 R1, 0xFFFF0000 - A0 = 0; - R3.L = VIT_MAX (R1) (ASL); - R3 = R3.L; - R4 = 0 (x); - CC = R3 == R4; - IF !CC JUMP 1f; - R6 = A0.W; - CC = R6 == R4; - IF !CC JUMP 1f; - - imm32 R1, 0x1234FADE - imm32 R2, 0xFFFFFFFF - A0.W = R2; - R3.L = VIT_MAX (R1) (ASR); - R3 = R3.L; - imm32 R4 0x00001234 - CC = R4 == R3; - IF !CC JUMP 1f; - imm32 R7, 0xFFFFFFFF - R0 = A0.W; - CC = R7 == R0; - IF !CC JUMP 1f; - - pass -1: fail diff --git a/sim/testsuite/sim/bfin/vit_max2.s b/sim/testsuite/sim/bfin/vit_max2.s deleted file mode 100644 index b7c6a0e..0000000 --- a/sim/testsuite/sim/bfin/vit_max2.s +++ /dev/null @@ -1,53 +0,0 @@ -# Blackfin testcase for parallel VIT_MAX (taken from PRM) -# mach: bfin - - .include "testutils.inc" - - start - - loadsym P0, scratch - - # Do parallel VIT_MAX's with stores to same reg; don't really - # care what the result is of VIT_MAX as long as it doesn't - # clobber the memory store. - - imm32 R1, 0xFFFF0000 - imm32 R2, 0x0000FFFF - imm32 R0, 0xFACE - R0 = VIT_MAX (R1, R2) (ASL) || W[P0] = R0.L; - imm32 R0, 0xFACE - R4 = W[P0]; - CC = R4 == R0; - IF !CC JUMP 1f; - - imm32 R5, 0xFEEDBEEF - imm32 R4, 0xDEAF0000 - imm32 R6, 0xFACE - R6 = VIT_MAX (R5, R4) (ASR) || W[P0] = R6.L; - imm32 R6, 0xFACE - R4 = W[P0]; - CC = R4 == R6; - IF !CC JUMP 1f; - - imm32 R3, 0xFFFF0000 - imm32 R1, 0xFACE - R1.L = VIT_MAX (R3) (ASL) || W[P0] = R1.L; - imm32 R1, 0xFACE - R4 = W[P0]; - CC = R4 == R1; - IF !CC JUMP 1f; - - imm32 R2, 0x1234FADE - imm32 R5, 0xFACE - R5.L = VIT_MAX (R2) (ASR) || W[P0] = R5.L; - imm32 R5, 0xFACE - R4 = W[P0]; - CC = R4 == R5; - IF !CC JUMP 1f; - - pass -1: fail - - .data -scratch: - .dw 0xffff diff --git a/sim/testsuite/sim/bfin/viterbi2.s b/sim/testsuite/sim/bfin/viterbi2.s deleted file mode 100644 index 6fb9ad0..0000000 --- a/sim/testsuite/sim/bfin/viterbi2.s +++ /dev/null @@ -1,254 +0,0 @@ -# mach: bfin - -// The assembly program uses two instructions to speed the decoder inner loop: -// R6= VMAX/VMAX (R5, R4) A0>>2; -// R2 =H+L (SGN(R0)*R1); -// VMAX is a 2-way parallel comparison of four updated path metrics, resulting -// in 2 new path metrics as well as a 2 bit field indicating the selection -// results. This 2 bit field is shifted into accumulator A0. This instruction -// implements the selections of a complete butterfly for a rate 1/n system. -// The H+L(SGN) instruction is used to compute the branch metric used by each -// butterfly. It takes as input a pair of values representing the received -// symbol, and another pair of values which are +1 or -1. The latter come -// from a pre-computed table that holds all the branch metric information for -// a specific set of polynomials. As all symbols are assumed to be binary, -// distance metrics between a received symbol and a branch metric are computed -// by adding and subtracting the values of the symbol according to the -// transition of a branch. - -.include "testutils.inc" - start - - // 16 in bytes for M2 - // A few pointer initializations - // P2 points to decision history, where outputs are stored - loadsym P2, DecisionHistory - - // P4 holds address of APMFrom - loadsym P4, APMFrom; - - // P5 holds address of APMTo - loadsym P5, APMTo; - - // I0 points to precomputed d's - loadsym I0, BranchStorage; - - M2.L = 32; - - loadsym P0, InputData; - - // storage for all precomputed branch metrics - loadsym P1, BranchStorage; - - R6 = 0; R0 = 0; // inits - - R0.L = 0x0001; - R0.H = 0x0001; - [ P1 + 0 ] = R0; - R0.L = 0xffff; - R0.H = 0xffff; - [ P1 + 4 ] = R0; - R0.L = 0xffff; - R0.H = 0x0001; - [ P1 + 8 ] = R0; - R0.L = 0x0001; - R0.H = 0xffff; - [ P1 + 12 ] = R0; - R0.L = 0xffff; - R0.H = 0x0001; - [ P1 + 16 ] = R0; - R0.L = 0x0001; - R0.H = 0xffff; - [ P1 + 20 ] = R0; - R0.L = 0x0001; - R0.H = 0x0001; - [ P1 + 24 ] = R0; - R0.L = 0xffff; - R0.H = 0xffff; - [ P1 + 28 ] = R0; - R0.L = 0x0001; - R0.H = 0xffff; - [ P1 + 32 ] = R0; - R0.L = 0xffff; - R0.H = 0x0001; - [ P1 + 36 ] = R0; - R0.L = 0xffff; - R0.H = 0xffff; - [ P1 + 40 ] = R0; - R0.L = 0x0001; - R0.H = 0x0001; - [ P1 + 44 ] = R0; - R0.L = 0xffff; - R0.H = 0xffff; - [ P1 + 48 ] = R0; - R0.L = 0x0001; - R0.H = 0x0001; - [ P1 + 52 ] = R0; - R0.L = 0x0001; - R0.H = 0xffff; - [ P1 + 56 ] = R0; - R0.L = 0xffff; - R0.H = 0x0001; - [ P1 + 60 ] = R0; - - P1 = 18; - LSETUP ( L$0 , L$0end ) LC0 = P1; // SymNo loop start - -L$0: - - // Get a symbol and leave it resident in R1 - R1 = [ P0 ]; // R1=(InputData[SymNo*2+1] InputData[SymNo*2]) - P0 += 4; - - A0 = 0; - - // I0 points to precomputed D1, D0 - loadsym I0, BranchStorage; - - I1 = P4; // I1 points to APM[From] - I2 = P4; - I2 += M2; // I2 points to APM[From+16] - I3 = P5; // I3 points to APM[To] - - P1 = 16; - P1 += -1; - LSETUP ( L$1 , L$1end ) LC1 = P1; - - // APMFrom and APMTo are in alternate - // memory banks. - - R0 = [ I0 ++ ]; // load R0 = (D1 D0) - R3.L = W [ I1 ++ ]; // load RL3 = PM0 - // (R1 holds current symbol) - - R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L; // apply sum-on-sign instruction - R3.H = W [ I2 ++ ]; // now, R3 = (PM1 PM0) - -L$1: - R5 = R3 +|- R2 , R4 = R3 -|+ R2 || R0 = [ I0 ++ ] || NOP; - // R5 = (PM11 PM01) R4 = (PM10 PM00) - // and load next (D1 D0) - - R6 = VIT_MAX( R5 , R4 ) (ASR) || R3.L = W [ I1 ++ ] || NOP; - // do 2 ACS in parallel - // R6 = (nPM1 nPM0) and update to A0 - -L$1end: - - R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L || R3.H = W [ I2 ++ ] || [ I3 ++ ] = R6; - // store new path metrics in - // two consecutive locations - - R5 = R3 +|- R2 , R4 = R3 -|+ R2; - - R6 = VIT_MAX( R5 , R4 ) (ASR); - - [ I3 ++ ] = R6; - - R7 = A0.w; - [ P2 ] = R7; - P2 += 4; // store history - - FP = P4; // swap pointers From <--> To - P4 = P5; -L$0end: - P5 = FP; - - // check results - loadsym I0, DecisionHistory - - R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x6ff2 ); - R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0xf99f ); - R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x9909 ); - R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x6666 ); - R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x0096 ); - R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x6996 ); - R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x9309 ); - R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x0000 ); - R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0xffff ); - R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0xffff ); - R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0xf0ff ); - R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0xcf00 ); - R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x9009 ); - R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x07f6 ); - R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x6004 ); - R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x6996 ); - R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x8338 ); - R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x3443 ); - R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x6bd6 ); - R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x6197 ); - R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x6c26 ); - R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x0990 ); - - pass - - .data - .align 8 -InputData: - .dw 0x0001 - .dw 0x0001 - .dw 0xffff - .dw 0xfffb - .dw 0x0005 - .dw 0x0001 - .dw 0xfffd - .dw 0xfffd - .dw 0x0005 - .dw 0x0001 - .dw 0x0001 - .dw 0x0001 - .dw 0xffff - .dw 0xfffb - .dw 0x0005 - .dw 0x0001 - .dw 0xfffd - .dw 0xfffd - .dw 0x0005 - .dw 0x0001 - - .align 8 -APMFrom: - .dw 0xc000 - .dw 0x0 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - .dw 0xc000 - - .align 8 -APMTo: - .space (32*8) - - .align 8 -BranchStorage: - .space (32*8) - - .align 8 -DecisionHistory: - .space (18*4) diff --git a/sim/testsuite/sim/bfin/wtf.s b/sim/testsuite/sim/bfin/wtf.s deleted file mode 100644 index 2ec8507..0000000 --- a/sim/testsuite/sim/bfin/wtf.s +++ /dev/null @@ -1,26 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - loadsym p0, foo; - r2 = p0; - r2 += 4; - [p0++]=p0; - loadsym i0, foo; - r0=[i0]; - R3 = P0; - CC = R2 == R3 - if ! CC jump _fail; - R3 = I0; - CC = R0 == R3; - if ! CC jump _fail; - -_halt0: - pass; -_fail: - fail; - - .data -foo: - .space (0x10) diff --git a/sim/testsuite/sim/bfin/x1.s b/sim/testsuite/sim/bfin/x1.s deleted file mode 100644 index 7ef1496..0000000 --- a/sim/testsuite/sim/bfin/x1.s +++ /dev/null @@ -1,79 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - -// 0.5 - imm32 r0, 0x40004000; - imm32 r1, 0x40004000; - R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); - checkreg r2, 0x40004000; - checkreg r3, 0; - - imm32 r1, 0x10001000; - - R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); - checkreg r2, 0x28002800; - checkreg r3, 0x18001800; - - R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR); - checkreg r0, 0x20002000; - checkreg r1, 0x08000800; - - R0 = 1; - R0 <<= 15; - R1 = R0 << 16; - R0 = R0 | R1; - R1 = R0; - checkreg r0, 0x80008000; - checkreg r1, 0x80008000; - - R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); - checkreg r2, 0x80008000; - checkreg r3, 0x0; - - R4 = 0; - R2 = R2 +|+ R4, R3 = R2 -|- R4 (S , ASR); - checkreg r2, 0xc000c000; - checkreg r3, 0xc000c000; - - R2 = R2 +|+ R3, R3 = R2 -|- R3 (S , ASR); - checkreg r2, 0xc000c000; - checkreg r3, 0x0; - - R4 = R2 +|+ R2, R5 = R2 -|- R2 (ASL); - checkreg r4, 0x0 - checkreg r5, 0x0 - - R2 = R2 +|+ R2, R3 = R2 -|- R2 (S , ASL); - checkreg r2, 0x80008000; - checkreg r3, 0x0; - - -imm32 r0, 0x50004000; -imm32 r1, 0x40005000; -R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL); -checkreg r2, 0x7fff7fff; -checkreg r3, 0x2000e000; -R4 = R0 +|+ R1, R5 = R0 -|- R1 (ASL); -checkreg r4, 0x20002000 -checkreg r5, 0x2000e000 - -imm32 r0, 0x30001000; -imm32 r1, 0x10003000; -R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL); -checkreg r2, 0x7fff7fff; -checkreg r3, 0x4000c000; -R4 = R0 +|+ R1, R5 = R0 -|- R1 (ASL); -checkreg r4, 0x80008000 -checkreg r5, 0x4000c000 - -imm32 r0, 0x20001fff; -imm32 r1, 0x1fff2000; -R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL); -checkreg r2, 0x7ffe7ffe; -checkreg r3, 0x0002fffe; - - - pass diff --git a/sim/testsuite/sim/bfin/zcall.s b/sim/testsuite/sim/bfin/zcall.s deleted file mode 100644 index bdb82c7..0000000 --- a/sim/testsuite/sim/bfin/zcall.s +++ /dev/null @@ -1,44 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - FP = SP; - CALL _foo; - pass - -___main: - RTS; - -_m1: - LINK 0; - R7 = [ FP + 8 ]; - DBGA ( R0.L , 1 ); - DBGA ( R1.L , 2 ); - DBGA ( R7.L , 3 ); - UNLINK; - RTS; - -_m2: - LINK 0; - R7 = [ FP + 8 ]; - DBGA ( R0.L , 1 ); - DBGA ( R1.L , 2 ); - DBGA ( R7.L , 3 ); - [ -- SP ] = R7; - CALL _m1; - SP += 4; - UNLINK; - RTS; - -_foo: - LINK 0; - CALL ___main; - R7 = 3; - [ -- SP ] = R7; - R0 = 1; - R1 = 2; - CALL _m2; - SP += 4; - UNLINK; - RTS; diff --git a/sim/testsuite/sim/bfin/zeroflagrnd.s b/sim/testsuite/sim/bfin/zeroflagrnd.s deleted file mode 100644 index 1425c07..0000000 --- a/sim/testsuite/sim/bfin/zeroflagrnd.s +++ /dev/null @@ -1,37 +0,0 @@ -# mach: bfin - -.include "testutils.inc" - start - - init_r_regs 0; - ASTAT=R0; - - R0.L = -32768; - R0.H = -1; - R0.L = R0 (RND); - DBGA ( R0.L , 0 ); - - _DBG R0; -//R0 = ASTAT; -//DBG R0; -//DBGA ( R0.L , 0x1 ); - cc = az; - r0 = cc; - dbga( r0.l, 1); - cc = an; - r0 = cc; - dbga( r0.l, 0); - cc = av0; - r0 = cc; - dbga( r0.l, 0); - cc = av0s; - r0 = cc; - dbga( r0.l, 0); - cc = av1; - r0 = cc; - dbga( r0.l, 0); - cc = av1s; - r0 = cc; - dbga( r0.l, 0); - - pass diff --git a/sim/testsuite/sim/bpf/ChangeLog b/sim/testsuite/sim/bpf/ChangeLog deleted file mode 100644 index 17dd79b..0000000 --- a/sim/testsuite/sim/bpf/ChangeLog +++ /dev/null @@ -1,20 +0,0 @@ -2020-09-08 David Faust - - * alu.s: Correct div and mod tests. - * alu32.s: Likewise. - -2020-08-04 David Faust - Jose E. Marchesi - - * allinsn.exp: New file. - * alu.s: Likewise. - * alu32.s: Likewise. - * endbe.s: Likewise. - * endle.s: Likewise. - * jmp.s: Likewise. - * jmp32.s: Likewise. - * ldabs.s: Likewise. - * mem.s: Likewise. - * mov.s: Likewise. - * testutils.inc: Likewise. - * xadd.s: Likewise. diff --git a/sim/testsuite/sim/bpf/allinsn.exp b/sim/testsuite/sim/bpf/allinsn.exp deleted file mode 100644 index 2cca770..0000000 --- a/sim/testsuite/sim/bpf/allinsn.exp +++ /dev/null @@ -1,26 +0,0 @@ -# eBPF simulator testsuite - -if [istarget bpf-unknown-none] { - # all machines - set all_machs "bpf" - - global global_sim_options - if ![info exists global_sim_options] { - set global_sim_options "--memory-size=4Mb" - } - - global global_ld_options - if ![info exists global_ld_options] { - set global_ld_options "-Ttext=0x0" - } - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/bpf/alu.s b/sim/testsuite/sim/bpf/alu.s deleted file mode 100644 index 4dc37b1..0000000 --- a/sim/testsuite/sim/bpf/alu.s +++ /dev/null @@ -1,121 +0,0 @@ -# mach: bpf -# output: pass\nexit 0 (0x0)\n -;;; alu.s -;;; Tests for ALU64 BPF instructions in simulator - - .include "testutils.inc" - - .text - .global main - .type main, @function -main: - mov %r1, 0 - mov %r2, -1 - - ;; add - add %r1, 1 - add %r2, -1 - add %r1, %r2 - fail_ne %r1, -1 - - ;; sub - sub %r1, %r1 - fail_ne %r1, 0 - sub %r1, 10 - sub %r2, %r1 - fail_ne %r2, 8 - - ;; mul - mul %r2, %r2 ; r2 = 64 - mul %r2, 3 ; r2 = 192 - mov %r1, -3 - mul %r1, %r2 ; r1 = -576 - mul %r2, 0 - fail_ne %r1, -576 - fail_ne %r2, 0 - mul %r1, %r1 - mul %r1, %r1 - fail_ne %r1, 110075314176 - - ;; div - div %r2, %r1 - fail_ne %r2, 0 - div %r1, 10000 - fail_ne %r1, 11007531 - div %r1, %r1 - fail_ne %r1, 1 - - ;; div is unsigned - lddw %r1, -8 - div %r1, 2 - fail_ne %r1, 0x7ffffffffffffffc ; sign bits NOT maintained - large pos. - - ;; and - lddw %r1, 0xaaaaaaaa55555555 - and %r1, 0x55aaaaaa ; we still only have 32-bit imm. - fail_ne %r1, 0x0000000055000000 - lddw %r2, 0x5555555a5aaaaaaa - and %r2, %r1 - fail_ne %r2, 0x0000000050000000 - - ;; or - or %r2, 0xdeadbeef - fail_ne %r2, 0xffffffffdeadbeef ; 0xdeadbeef gets sign extended - lddw %r1, 0xdead00000000beef - lddw %r2, 0x0000123456780000 - or %r1, %r2 - fail_ne %r1, 0xdead12345678beef - - ;; lsh - mov %r1, 0xdeadbeef - lsh %r1, 11 - fail_ne %r1, 0xfffffef56df77800 ; because deadbeef gets sign ext. - mov %r2, 21 - lsh %r1, %r2 - fail_ne %r1, 0xdeadbeef00000000 - - ;; rsh - rsh %r1, 11 - fail_ne %r1, 0x001bd5b7dde00000 ; 0xdeadbeef 00000000 >> 0xb - rsh %r1, %r2 - fail_ne %r1, 0x00000000deadbeef - - ;; arsh - arsh %r1, 8 - fail_ne %r1, 0x0000000000deadbe - lsh %r1, 40 ; r1 = 0xdead be00 0000 0000 - arsh %r1, %r2 ; r1 arsh (r2 == 21) - fail_ne %r1, 0xfffffef56df00000 - - ;; mod - mov %r1, 1025 - mod %r1, 16 - fail_ne %r1, 1 - - ;; mod is unsigned - mov %r1, 1025 - mod %r1, -16 ; mod unsigned -> will treat as large positive - fail_ne %r1, 1025 - - mov %r1, -25 ; -25 is 0xff..ffe7 - mov %r2, 5 ; ... which when unsigned is a large positive - mod %r1, %r2 ; ... which is not evenly divisible by 5 - fail_ne %r1, 1 - - ;; xor - mov %r1, 0 - xor %r1, %r2 - fail_ne %r1, 5 - xor %r1, 0x7eadbeef - fail_ne %r1, 0x7eadbeea - xor %r1, %r1 - fail_ne %r1, 0 - - ;; neg - neg %r2 - fail_ne %r2, -5 - mov %r1, -1025 - neg %r1 - fail_ne %r1, 1025 - - pass diff --git a/sim/testsuite/sim/bpf/alu32.s b/sim/testsuite/sim/bpf/alu32.s deleted file mode 100644 index e8d5062..0000000 --- a/sim/testsuite/sim/bpf/alu32.s +++ /dev/null @@ -1,110 +0,0 @@ -# mach: bpf -# output: pass\nexit 0 (0x0)\n -;; alu32.s -;; Tests for ALU(32) BPF instructions in simulator - - .include "testutils.inc" - - .text - .global main - .type main, @function -main: - mov32 %r1, 10 ; r1 = 10 - mov32 %r2, -5 ; r2 = -5 - - ;; add - add32 %r1, 1 ; r1 += 1 (r1 = 11) - add32 %r2, -1 ; r2 += -1 (r2 = -6) - add32 %r1, %r2 ; r1 += r2 (r1 = 11 + -6 = 5) - fail_ne32 %r1, 5 - - ;; sub - sub32 %r1, 5 ; r1 -= 5 (r1 = 0) - sub32 %r1, -5 ; r1 -= -5 (r1 = 5) - sub32 %r1, %r2 ; r1 -= r2 (r1 = 5 - -6 = 11) - fail_ne32 %r1, 11 - - ;; mul - mul32 %r1, 2 ; r1 *= 2 (r1 = 22) - mul32 %r1, -2 ; r1 *= -2 (r1 = -44) - mul32 %r1, %r2 ; r1 *= r2 (r1 = -44 * -6 = 264) - fail_ne32 %r1, 264 - - ;; div - div32 %r1, 6 - mov32 %r2, 11 - div32 %r1, %r2 - fail_ne32 %r1, 4 - - ;; div is unsigned - mov32 %r1, -8 ; 0xfffffff8 - div32 %r1, 2 - fail_ne32 %r1, 0x7ffffffc ; sign bits are not preserved - - ;; and (bitwise) - mov32 %r1, 0xb ; r1 = (0xb = 0b1011) - mov32 %r2, 0x5 ; r2 = (0x5 = 0b0101) - and32 %r1, 0xa ; r1 &= (0xa = 0b1010) = (0b1010 = 0xa) - fail_ne32 %r1, 0xa - and32 %r1, %r2 ; r1 &= r2 = 0x0 - fail_ne32 %r1, 0x0 - - ;; or (bitwise) - or32 %r1, 0xb - or32 %r1, %r2 - fail_ne32 %r1, 0xf - - ;; lsh (left shift) - lsh32 %r1, 4 ; r1 <<= 4 (r1 = 0xf0) - mov32 %r2, 24 ; r2 = 24 - lsh32 %r1, %r2 - fail_ne32 %r1, 0xf0000000 - - ;; rsh (right logical shift) - rsh32 %r1, 2 - rsh32 %r1, %r2 - fail_ne32 %r1, 0x3c ; (0xf000 0000 >> 26) - - ;; arsh (right arithmetic shift) - arsh32 %r1, 1 - or32 %r1, 0x80000000 - mov32 %r2, 3 - arsh32 %r1, %r2 - fail_ne %r1, 0x00000000F0000003 - ; Note: make sure r1 is NOT sign-extended - ; i.e. upper-32 bits should be untouched - - ;; mod - mov32 %r1, 1025 - mod32 %r1, 16 - fail_ne32 %r1, 1 - - ;; mod is unsigned - mov32 %r1, 1025 - mod32 %r1, -16 ; when unsigned, much larger than 1025 - fail_ne32 %r1, 1025 - - mov32 %r1, -25 ; when unsigned, a large positive which is - mov32 %r2, 5 ; ... not evenly divisible by 5 - mod32 %r1, %r2 - fail_ne32 %r1, 1 - - ;; xor - xor32 %r1, %r2 - fail_ne32 %r1, 4 - xor32 %r1, 0xF000000F - fail_ne %r1, 0xF000000B ; Note: check for (bad) sign-extend - xor32 %r1, %r1 - fail_ne %r1, 0 - - ;; neg - mov32 %r1, -1 - mov32 %r2, 0x7fffffff - neg32 %r1 - neg32 %r2 - fail_ne32 %r1, 1 - fail_ne %r2, 0x80000001 ; Note: check for (bad) sign-extend - neg32 %r2 - fail_ne32 %r2, 0x7fffffff - - pass diff --git a/sim/testsuite/sim/bpf/endbe.s b/sim/testsuite/sim/bpf/endbe.s deleted file mode 100644 index 2f662ae..0000000 --- a/sim/testsuite/sim/bpf/endbe.s +++ /dev/null @@ -1,46 +0,0 @@ -# mach: bpf -# as: --EB -# ld: --EB -# sim: -E big -# output: pass\nexit 0 (0x0)\n -;;; endbe.s -;;; Tests for BPF endianness-conversion instructions in simulator -;;; running in BIG ENDIAN -;;; -;;; Both 'be' and 'le' ISAs have both endbe and endle instructions. - - .include "testutils.inc" - - .text - .global main - .type main, @function -main: - lddw %r1, 0x12345678deadbeef - endle %r1, 64 - fail_ne %r1, 0xefbeadde78563412 - endle %r1, 64 - fail_ne %r1, 0x12345678deadbeef - - ;; `bitsize` < 64 will truncate - endle %r1, 32 - fail_ne %r1, 0xefbeadde - endle %r1, 32 - fail_ne %r1, 0xdeadbeef - - endle %r1, 16 - fail_ne %r1, 0xefbe - endle %r1, 16 - fail_ne %r1, 0xbeef - - ;; endbe on be should be noop (except truncate) - lddw %r1, 0x12345678deadbeef - endbe %r1, 64 - fail_ne %r1, 0x12345678deadbeef - - endbe %r1, 32 - fail_ne %r1, 0xdeadbeef - - endbe %r1, 16 - fail_ne %r1, 0xbeef - - pass diff --git a/sim/testsuite/sim/bpf/endle.s b/sim/testsuite/sim/bpf/endle.s deleted file mode 100644 index d8f5ceb..0000000 --- a/sim/testsuite/sim/bpf/endle.s +++ /dev/null @@ -1,43 +0,0 @@ -# mach: bpf -# output: pass\nexit 0 (0x0)\n -;;; endle.s -;;; Tests for BPF endianness-conversion instructions in simulator -;;; running in LITTLE ENDIAN -;;; -;;; Both 'be' and 'le' ISAs have both endbe and endle instructions. - - .include "testutils.inc" - - .text - .global main - .type main, @function -main: - lddw %r1, 0x12345678deadbeef - endbe %r1, 64 - fail_ne %r1, 0xefbeadde78563412 - endbe %r1, 64 - fail_ne %r1, 0x12345678deadbeef - - ;; `bitsize` < 64 will truncate - endbe %r1, 32 - fail_ne %r1, 0xefbeadde - endbe %r1, 32 - fail_ne %r1, 0xdeadbeef - - endbe %r1, 16 - fail_ne %r1, 0xefbe - endbe %r1, 16 - fail_ne %r1, 0xbeef - - ;; endle on le should be noop (except truncate) - lddw %r1, 0x12345678deadbeef - endle %r1, 64 - fail_ne %r1, 0x12345678deadbeef - - endle %r1, 32 - fail_ne %r1, 0xdeadbeef - - endle %r1, 16 - fail_ne %r1, 0xbeef - - pass diff --git a/sim/testsuite/sim/bpf/jmp.s b/sim/testsuite/sim/bpf/jmp.s deleted file mode 100644 index 5ab5de0..0000000 --- a/sim/testsuite/sim/bpf/jmp.s +++ /dev/null @@ -1,120 +0,0 @@ -# mach: bpf -# output: pass\nexit 0 (0x0)\n -;;; jmp.s -;;; Tests for eBPF JMP instructions in simulator - - .include "testutils.inc" - - .text - .global main - .type main, @function -main: - mov %r1, 5 - mov %r2, 2 - mov %r3, 7 - mov %r4, -1 - - ;; ja - jump absolute (unconditional) - ja 2f -1: fail - -2: ;; jeq - jump eq - jeq %r1, 4, 1b ; no - jeq %r1, %r2, 1b ; no - jeq %r1, 5, 2f ; yes - fail -2: jeq %r1, %r1, 2f ; yes - fail - -2: ;; jgt - jump (unsigned) greater-than - jgt %r1, 6, 1b ; no - jgt %r1, -5, 1b ; no - unsigned - jgt %r1, %r4, 1b ; no - unsigned - jgt %r1, 4, 2f ; yes - fail -2: jgt %r1, %r2, 2f ; yes - fail - -2: ;; jge - jump (unsigned) greater-than-or-equal-to - jge %r1, 6, 1b ; no - jge %r1, 5, 2f ; yes - fail -2: jge %r1, %r3, 1b ; no - jge %r1, -5, 1b ; no - unsigned - jge %r1, %r2, 2f ; yes - fail - -2: ;; jlt - jump (unsigned) less-than - jlt %r1, 5, 1b ; no - jlt %r1, %r2, 1b ; no - jlt %r4, %r1, 1b ; no - unsigned - jlt %r1, 6, 2f ; yes - fail -2: - jlt %r1, %r3, 2f ; yes - fail - -2: ;; jle - jump (unsigned) less-than-or-equal-to - jle %r1, 4, 1b ; no - jle %r1, %r2, 1b ; no - jle %r4, %r1, 1b ; no - jle %r1, 5, 2f ; yes - fail -2: jle %r1, %r1, 2f ; yes - fail - -2: ;; jset - jump "test" (AND) - jset %r1, 2, 1b ; no (5 & 2 = 0) - jset %r1, %r2, 1b ; no (same) - jset %r1, 4, 2f ; yes (5 & 4 != 0) - fail - -2: ;; jne - jump not-equal-to - jne %r1, 5, 1b ; no - jne %r1, %r1, 1b ; no - jne %r1, 6, 2f ; yes - fail -2: jne %r1, %r4, 2f ; yes - fail - -2: ;; jsgt - jump (signed) greater-than - jsgt %r1, %r3, 1b ; no - jsgt %r1, %r1, 1b ; no - jsgt %r1, 5, 1b ; no - jsgt %r1, -4, 2f ; yes - fail -2: jsgt %r1, %r4, 2f ; yes - fail - -2: ;; jsge - jump (signed) greater-than-or-equal-to - jsge %r1, %r3, 1b ; no - jsge %r1, %r1, 2f ; yes - fail -2: jsge %r1, 7, 1b ; no - jsge %r1, -4, 2f ; yes - fail -2: jsge %r1, %r4, 2f ; yes - fail - -2: ;; jslt - jump (signed) less-than - jslt %r1, 5, 1b ; no - jslt %r1, %r2, 1b ; no - jslt %r4, %r1, 2f ; yes - fail -2: jslt %r1, 6, 2f ; yes - fail -2: jslt %r1, %r3, 2f ; yes - fail - -2: ;; jsle - jump (signed) less-than-or-equal-to - jsle %r1, 4, 1b ; no - jsle %r1, %r2, 1b ; no - jsle %r4, %r1, 2f ; yes - fail -2: jsle %r1, 5, 2f ; yes - fail -2: jsle %r1, %r3, 2f ; yes - fail - -2: - pass diff --git a/sim/testsuite/sim/bpf/jmp32.s b/sim/testsuite/sim/bpf/jmp32.s deleted file mode 100644 index a6074cd..0000000 --- a/sim/testsuite/sim/bpf/jmp32.s +++ /dev/null @@ -1,120 +0,0 @@ -# mach: bpf -# output: pass\nexit 0 (0x0)\n -;;; jmp32.s -;;; Tests for eBPF JMP32 instructions in simulator - - .include "testutils.inc" - - .text - .global main - .type main, @function -main: - mov32 %r1, 5 - mov32 %r2, 2 - mov32 %r3, 7 - mov32 %r4, -1 - - ;; ja - jump absolute (unconditional) - ja 2f -1: fail - -2: ;; jeq - jump eq - jeq32 %r1, 4, 1b ; no - jeq32 %r1, %r2, 1b ; no - jeq32 %r1, 5, 2f ; yes - fail -2: jeq32 %r1, %r1, 2f ; yes - fail - -2: ;; jgt - jump (unsigned) greater-than - jgt32 %r1, 6, 1b ; no - jgt32 %r1, -5, 1b ; no - unsigned - jgt32 %r1, %r4, 1b ; no - unsigned - jgt32 %r1, 4, 2f ; yes - fail -2: jgt32 %r1, %r2, 2f ; yes - fail - -2: ;; jge - jump (unsigned) greater-than-or-equal-to - jge32 %r1, 6, 1b ; no - jge32 %r1, 5, 2f ; yes - fail -2: jge32 %r1, %r3, 1b ; no - jge32 %r1, -5, 1b ; no - unsigned - jge32 %r1, %r2, 2f ; yes - fail - -2: ;; jlt - jump (unsigned) less-than - jlt32 %r1, 5, 1b ; no - jlt32 %r1, %r2, 1b ; no - jlt32 %r4, %r1, 1b ; no - unsigned - jlt32 %r1, 6, 2f ; yes - fail -2: - jlt32 %r1, %r3, 2f ; yes - fail - -2: ;; jle - jump (unsigned) less-than-or-equal-to - jle32 %r1, 4, 1b ; no - jle32 %r1, %r2, 1b ; no - jle32 %r4, %r1, 1b ; no - jle32 %r1, 5, 2f ; yes - fail -2: jle32 %r1, %r1, 2f ; yes - fail - -2: ;; jset - jump "test" (AND) - jset32 %r1, 2, 1b ; no (5 & 2 = 0) - jset32 %r1, %r2, 1b ; no (same) - jset32 %r1, 4, 2f ; yes (5 & 4 != 0) - fail - -2: ;; jne - jump not-equal-to - jne32 %r1, 5, 1b ; no - jne32 %r1, %r1, 1b ; no - jne32 %r1, 6, 2f ; yes - fail -2: jne32 %r1, %r4, 2f ; yes - fail - -2: ;; jsgt - jump (signed) greater-than - jsgt32 %r1, %r3, 1b ; no - jsgt32 %r1, %r1, 1b ; no - jsgt32 %r1, 5, 1b ; no - jsgt32 %r1, -4, 2f ; yes - fail -2: jsgt32 %r1, %r4, 2f ; yes - fail - -2: ;; jsge - jump (signed) greater-than-or-equal-to - jsge32 %r1, %r3, 1b ; no - jsge32 %r1, %r1, 2f ; yes - fail -2: jsge32 %r1, 7, 1b ; no - jsge32 %r1, -4, 2f ; yes - fail -2: jsge32 %r1, %r4, 2f ; yes - fail - -2: ;; jslt - jump (signed) less-than - jslt32 %r1, 5, 1b ; no - jslt32 %r1, %r2, 1b ; no - jslt32 %r4, %r1, 2f ; yes - fail -2: jslt32 %r1, 6, 2f ; yes - fail -2: jslt32 %r1, %r3, 2f ; yes - fail - -2: ;; jsle - jump (signed) less-than-or-equal-to - jsle32 %r1, 4, 1b ; no - jsle32 %r1, %r2, 1b ; no - jsle32 %r4, %r1, 2f ; yes - fail -2: jsle32 %r1, 5, 2f ; yes - fail -2: jsle32 %r1, %r3, 2f ; yes - fail - -2: - pass diff --git a/sim/testsuite/sim/bpf/ldabs.s b/sim/testsuite/sim/bpf/ldabs.s deleted file mode 100644 index ae777f1..0000000 --- a/sim/testsuite/sim/bpf/ldabs.s +++ /dev/null @@ -1,87 +0,0 @@ -# mach: bpf -# sim: --skb-data-offset=0x20 -# output: pass\nexit 0 (0x0)\n -;;; ldabs.s -;;; Tests for non-generic BPF load instructions in simulator. -;;; These instructions (ld{abs,ind}{b,h,w,dw}) are used to access -;;; kernel socket data from BPF programs for high performance filters. -;;; -;;; Register r6 is an implicit input holding a pointer to a struct sk_buff. -;;; Register r0 is an implicit output, holding the fetched data. -;;; -;;; e.g. -;;; ldabsw means: -;;; r0 = ntohl (*(u32 *) (((struct sk_buff *)r6)->data + imm32)) -;;; -;;; ldindw means -;;; r0 = ntohl (*(u32 *) (((struct sk_buff *)r6)->data + src_reg + imm32)) - - .include "testutils.inc" - - .text - .global main - .type main, @function -main: - ;; R6 holds a pointer to a struct sk_buff, which we pretend - ;; exists at 0x1000 - mov %r6, 0x1000 - - ;; We configure skb-data-offset=0x20 - ;; This specifies offsetof(struct sk_buff, data), where the field 'data' - ;; is a pointer a data buffer, in this case at 0x2000 - stw [%r6+0x20], 0x2000 - - ;; Write the value 0x7eadbeef into memory at 0x2004 - ;; i.e. offset 4 within the data buffer pointed to by - ;; ((struct sk_buff *)r6)->data - stw [%r6+0x1004], 0xdeadbeef - - ;; Now load data[4] into r0 using the ldabsw instruction - ldabsw 0x4 - - ;; ...and compare to what we expect - fail_ne32 %r0, 0xdeadbeef - - ;; Repeat for a half-word (2-bytes) - sth [%r6+0x1008], 0x1234 - ldabsh 0x8 - fail_ne32 %r0, 0x1234 - - ;; Repeat for a single byte - stb [%r6+0x1010], 0x5a - ldabsb 0x10 - fail_ne32 %r0, 0x5a - - ;; Repeat for a double-word (8-byte) - ;; (note: fail_ne macro uses r0, so copy to another r1 to compare) - lddw %r2, 0x1234deadbeef5678 - stxdw [%r6+0x1018], %r2 - ldabsdw 0x18 - mov %r1, %r0 - fail_ne %r1, 0x1234deadbeef5678 - - ;; Now, we do the same for the indirect loads - mov %r7, 0x100 - stw [%r6+0x1100], 0xfeedbeef - - ldindw %r7, 0x0 - fail_ne32 %r0, 0xfeedbeef - - ;; half-word - sth [%r6+0x1104], 0x6789 - ldindh %r7, 0x4 - fail_ne32 %r0, 0x6789 - - ;; byte - stb [%r6+0x1108], 0x5f - ldindb %r7, 0x8 - fail_ne32 %r0, 0x5f - - ;; double-word - lddw %r2, 0xcafe12345678d00d - stxdw [%r6+0x1110], %r2 - ldinddw %r7, 0x10 - mov %r1, %r0 - fail_ne %r1, 0xcafe12345678d00d - - pass diff --git a/sim/testsuite/sim/bpf/mem.s b/sim/testsuite/sim/bpf/mem.s deleted file mode 100644 index f9c6a19..0000000 --- a/sim/testsuite/sim/bpf/mem.s +++ /dev/null @@ -1,56 +0,0 @@ -# mach: bpf -# output: pass\nexit 0 (0x0)\n -;;; mem.s -;;; Tests for BPF memory (ldx, stx, ..) instructions in simulator - - .include "testutils.inc" - - .text - .global main - .type main, @function -main: - lddw %r1, 0x1234deadbeef5678 - mov %r2, 0x1000 - - ;; basic store/load check - stxb [%r2+0], %r1 - stxh [%r2+2], %r1 - stxw [%r2+4], %r1 - stxdw [%r2+8], %r1 - - stb [%r2+16], 0x5a - sth [%r2+18], 0xcafe - stw [%r2+20], 0xbeefface - stdw [%r2+24], 0x7eadbeef - - ldxb %r1, [%r2+16] - fail_ne %r1, 0x5a - ldxh %r1, [%r2+18] - fail_ne %r1, 0xffffffffffffcafe - ldxw %r1, [%r2+20] - fail_ne %r1, 0xffffffffbeefface - ldxdw %r1, [%r2+24] - fail_ne %r1, 0x7eadbeef - - ldxb %r3, [%r2+0] - fail_ne %r3, 0x78 - ldxh %r3, [%r2+2] - fail_ne %r3, 0x5678 - ldxw %r3, [%r2+4] - fail_ne %r3, 0xffffffffbeef5678 - ldxdw %r3, [%r2+8] - fail_ne %r3, 0x1234deadbeef5678 - - ldxw %r4, [%r2+10] - fail_ne %r4, 0xffffffffdeadbeef - - ;; negative offsets - add %r2, 16 - ldxh %r5, [%r2+-14] - fail_ne %r5, 0x5678 - ldxw %r5, [%r2+-12] - fail_ne %r5, 0xffffffffbeef5678 - ldxdw %r5, [%r2+-8] - fail_ne %r5, 0x1234deadbeef5678 - - pass diff --git a/sim/testsuite/sim/bpf/mov.s b/sim/testsuite/sim/bpf/mov.s deleted file mode 100644 index 6665450..0000000 --- a/sim/testsuite/sim/bpf/mov.s +++ /dev/null @@ -1,54 +0,0 @@ -# mach: bpf -# output: pass\nexit 0 (0x0)\n -;; mov.s -;; Tests for mov and mov32 instructions - - .include "testutils.inc" - - .text - .global main - .type main, @function -main: - ;; some basic sanity checks - mov32 %r1, 5 - fail_ne %r1, 5 - - mov32 %r2, %r1 - fail_ne %r2, 5 - - mov %r2, %r1 - fail_ne %r2, 5 - - mov %r1, -666 - fail_ne %r1, -666 - - ;; should NOT sign extend - mov32 %r1, -1 - fail_ne %r1, 0x00000000ffffffff - - ;; should sign extend - mov %r2, -1 - fail_ne %r2, 0xffffffffffffffff - - mov %r3, 0x80000000 - - ;; should NOT sign extend - mov32 %r4, %r3 - fail_ne %r4, 0x0000000080000000 - - ;; should sign extend - mov %r5, %r3 - fail_ne %r5, 0xffffffff80000000 - - mov32 %r1, -2147483648 - mov32 %r1, %r1 - fail_ne32 %r1, -2147483648 - - ;; casting shenanigans - mov %r1, %r1 - fail_ne %r1, +2147483648 - mov32 %r2, -1 - mov %r2, %r2 - fail_ne %r2, +4294967295 - - pass diff --git a/sim/testsuite/sim/bpf/testutils.inc b/sim/testsuite/sim/bpf/testutils.inc deleted file mode 100644 index d3d6b17..0000000 --- a/sim/testsuite/sim/bpf/testutils.inc +++ /dev/null @@ -1,38 +0,0 @@ - - ;; Print "pass\n" and 'exit 0' - .macro pass - .data -mpass: - .string "pass\n" - .text -_pass: - mov %r1, mpass ; point to "pass\n" string - mov %r2, 5 ; strlen mpass - call 7 ; printk - mov %r0, 0 ; - exit ; exit 0 - .endm - -;;; MACRO fail -;;; Exit with status 1 - .macro fail - mov %r0, 1 - exit - .endm - -;;; MACRO fail_ne32 -;;; Exit with status 1 if \reg32 != \val - .macro fail_ne32 reg val - jeq32 \reg, \val, 2 - mov %r0, 1 - exit - .endm - -;;; MACRO fail_ne -;;; Exit with status1 if \reg ne \val - .macro fail_ne reg val - lddw %r0, \val - jeq \reg, %r0, 2 - mov %r0, 1 - exit - .endm diff --git a/sim/testsuite/sim/bpf/xadd.s b/sim/testsuite/sim/bpf/xadd.s deleted file mode 100644 index be60714..0000000 --- a/sim/testsuite/sim/bpf/xadd.s +++ /dev/null @@ -1,44 +0,0 @@ -# mach: bpf -# output: pass\nexit 0 (0x0)\n -;;; xadd.s -;;; Tests for BPF atomic exchange-and-add instructions in simulator -;;; -;;; The xadd instructions (XADDW, XADDDW) operate on a memory location -;;; specified in $dst + offset16, atomically adding the value in $src. -;;; -;;; In the simulator, there isn't anything else happening. The atomic -;;; instructions are identical to a non-atomic load/add/store. - - .include "testutils.inc" - - .text - .global main - .type main, @function -main: - mov %r1, 0x1000 - mov %r2, 5 - - ;; basic xadd w - stw [%r1+0], 10 - xaddw [%r1+0], %r2 - ldxw %r3, [%r1+0] - fail_ne %r3, 15 - - ;; basic xadd dw - stdw [%r1+8], 42 - xadddw [%r1+8], %r2 - ldxdw %r3, [%r1+8] - fail_ne %r3, 47 - - ;; xadd w negative value - mov %r4, -1 - xaddw [%r1+0], %r4 - ldxw %r3, [%r1+0] - fail_ne %r3, 14 - - ;; xadd dw negative val - xadddw [%r1+8], %r4 - ldxdw %r3, [%r1+8] - fail_ne %r3, 46 - - pass diff --git a/sim/testsuite/sim/cr16/ChangeLog b/sim/testsuite/sim/cr16/ChangeLog deleted file mode 100644 index 4cb008b..0000000 --- a/sim/testsuite/sim/cr16/ChangeLog +++ /dev/null @@ -1,51 +0,0 @@ -2015-12-24 Mike Frysinger - - * allinsn.exp: Append --load-vma to global_sim_options. - * misc.exp: Likewise. - -2015-03-29 Mike Frysinger - - PR sim/12385 - * testutils.inc (START): Add _start symbol. - -2008-05-02 M R Swami Reddy - - * cbitb.cgs, cbitw.cgs, sbitb.cgs, sbitw.cgs, tbit.cgs, tbitb.cgs, - tbitw.cgs, hw-trap.ms, uread16.ms, uread32.ms: New testcases. - addb.cgs, addd.cgs, addi.cgs, andb.cgs, andd.cgs, andw.cgs, ashub.cgs, - ashub_i.cgs, ashud.cgs, ashud_i.cgs, ashuw.cgs, ashuw_i.cgs, cmpi.cgs, - cmpw.cgs, jlt.cgs, jump.cgs, loadd.cgs, loadw.cgs, lshb.cgs, lshb_i.cgs, - lshd.cgs, lshd_i.cgs, lshw.cgs, lshw_i.cgs, movb.cgs, movd.cgs, - movw.cgs, movxb.cgs, movxw.cgs, movzb.cgs, movzw.cgs, mulb.cgs, - muluw.cgs, mulw.cgs, orb.cgs, ord.cgs, orw.cgs, pop1.cgs, pop2.cgs, - pop3.cgs, popret1.cgs, popret2.cgs, popret3.cgs, push1.cgs, push2.cgs, - push3.cgs: Update testcase comment. - bnc8.cgs, bnc24.cgs and ret.cgs: Removed. - -2008-04-08 M R Swami Reddy - - * allinsn.exp: Remove target_alias and global_ld_options. - -2008-02-12 M R Swami Reddy - - * allinsn.exp, misc.exp: New files: Test scripts - testutils.inc: New file: Test macros. - addb.cgs, addd.cgs, addi.cgs, addw.cgs, andb.cgs, andd.cgs, andw.cgs, - ashub.cgs, ashub_i.cgs, ashud.cgs, ashud_i.cgs, ashuw.cgs, ashuw_i.cgs, - bal1_24.cgs, bal2_24.cgs, bcc.cgs, bcs.cgs, beq0b.cgs, beq0w.cgs, - beq.cgs, bge.cgs, bgt.cgs, bhi.cgs, bhs.cgs, bht.cgs, blo.cgs, bls.cgs, - blt.cgs, bnc24.cgs, bnc8.cgs, bne0b.cgs, bne0w.cgs, bne.cgs, br.cgs, - cmpb.cgs, cmpb_i.cgs, cmpd.cgs, cmpd_i.cgs, cmpi.cgs, cmpw.cgs, - cmpw_i.cgs, excp.cgs, hello.ms, jal.cgs, jcc.cgs, jcs.cgs, jeq.cgs, - jfc.cgs, jfs.cgs, jge.cgs, jgt.cgs, jhi.cgs, jhs.cgs, jlo.cgs, jls.cgs, - jlt.cgs, jne.cgs, jump.cgs, loadb.cgs, loadd.cgs, loadm.cgs, loadmp.cgs, - loadw.cgs, lprd-sprd.cgs, lpr-spr.cgs, lshb.cgs, lshb_i.cgs, lshd.cgs, - lshd_i.cgs, lshw.cgs, lshw_i.cgs, macqw.cgs, macsw.cgs, macuw.cgs, - movb.cgs, movd.cgs, movw.cgs, movxb.cgs, movxw.cgs, movzb.cgs, - movzw.cgs, mulb.cgs, mulsb.cgs, mulsw.cgs, muluw.cgs, mulw.cgs, - nop.cgs, orb.cgs, ord.cgs, orw.cgs, pop1.cgs, pop2.cgs, pop3.cgs, - popret1.cgs, popret2.cgs, popret3.cgs, push1.cgs, push2.cgs, push3.cgs, - ret.cgs, scc.cgs, scs.cgs, seq.cgs, sfc.cgs, sfs.cgs, sge.cgs, sgt.cgs, - shi.cgs, shs.cgs, slo.cgs, sls.cgs, slt.cgs, sne.cgs, storb.cgs, - stord.cgs, storw.cgs, subb.cgs, subd.cgs, subi.cgs, subw.cgs, - xorb.cgs, xord.cgs, xorw.cgs: New files diff --git a/sim/testsuite/sim/cr16/addb.cgs b/sim/testsuite/sim/cr16/addb.cgs deleted file mode 100644 index 272804a..0000000 --- a/sim/testsuite/sim/cr16/addb.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# cr16 testcase for addb $sr, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global add -add: - - movb $0x1234,r4 - movb $0x1234,r5 - addb r4, r5 - test_h_gr r5, 0x68 - - pass diff --git a/sim/testsuite/sim/cr16/addd.cgs b/sim/testsuite/sim/cr16/addd.cgs deleted file mode 100644 index c13164d..0000000 --- a/sim/testsuite/sim/cr16/addd.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# cr16 testcase for addd $sr, regp -# mach(): cr16 - - .include "testutils.inc" - - start - - .global addd -addd: - - movd $0x12345678,(r4,r3) - addd $0x44444444,(r4,r3) - - test_h_grp "(r4,r3)", 0x56789abc - - pass diff --git a/sim/testsuite/sim/cr16/addi.cgs b/sim/testsuite/sim/cr16/addi.cgs deleted file mode 100644 index dae8941..0000000 --- a/sim/testsuite/sim/cr16/addi.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# cr16 testcase for addi $imm8, $dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global addi -addi: - - movb $1, r4 - addb $2, r4 - - cmpb $3,r4 - bne not_ok - - movw $0x1234, r5 - addw $0x1234, r5 - test_h_gr r5, 0x2468 - - pass - - movd $0x12345678, (r5,r4) - addd $0x12345678, (r5,r4) - test_h_grp "(r5,r4)", 0x2468acf0 - - pass - -not_ok: - fail diff --git a/sim/testsuite/sim/cr16/addw.cgs b/sim/testsuite/sim/cr16/addw.cgs deleted file mode 100644 index 866349c..0000000 --- a/sim/testsuite/sim/cr16/addw.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# cr16 testcase for addw $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global addw -addw: - - movw $0x1234,r4 - addw $0x1234,r4 - - test_h_gr r4, 0x2468 - - pass diff --git a/sim/testsuite/sim/cr16/allinsn.exp b/sim/testsuite/sim/cr16/allinsn.exp deleted file mode 100644 index 852a673..0000000 --- a/sim/testsuite/sim/cr16/allinsn.exp +++ /dev/null @@ -1,31 +0,0 @@ -# CR16 simulator testsuite. - -if [istarget cr16*-*-*] { - # load support procs - # load_lib cgen.exp - - # all machines - set all_machs "cr16" - - global global_sim_options - if ![info exists global_sim_options] { - set global_sim_options "" - } - set saved_global_sim_options $global_sim_options - # The cr16 linker sets the default LMA base to 0, and all the code - # expects the VMA when running, so use that when running the tests. - set global_sim_options "$saved_global_sim_options --load-vma" - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } - - set global_sim_options $saved_global_sim_options -} diff --git a/sim/testsuite/sim/cr16/andb.cgs b/sim/testsuite/sim/cr16/andb.cgs deleted file mode 100644 index bc201ad..0000000 --- a/sim/testsuite/sim/cr16/andb.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for and $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global and -and: - movb $3, r4 - movb $6, r5 - - andb r4,r5 - - test_h_gr r5, 2 - - pass diff --git a/sim/testsuite/sim/cr16/andd.cgs b/sim/testsuite/sim/cr16/andd.cgs deleted file mode 100644 index 8e72bae..0000000 --- a/sim/testsuite/sim/cr16/andd.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for and $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global and -and: - movd $0x33333333, (r4,r3) - movd $0x66666666, (r6,r5) - - andd (r4,r3), (r6,r5) - - test_h_grp "(r6,r5)", 0x22222222 - - pass diff --git a/sim/testsuite/sim/cr16/andw.cgs b/sim/testsuite/sim/cr16/andw.cgs deleted file mode 100644 index d2d634a..0000000 --- a/sim/testsuite/sim/cr16/andw.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for and $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global and -and: - movw $3, r4 - movw $6, r5 - - andw r4, r5 - - test_h_gr r5, 2 - - pass diff --git a/sim/testsuite/sim/cr16/ashub.cgs b/sim/testsuite/sim/cr16/ashub.cgs deleted file mode 100644 index ef3e94e..0000000 --- a/sim/testsuite/sim/cr16/ashub.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# cr16 testcase for ashub $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global ashub -ashub: - - movw $0x12f1, r4 - movw $4,r5 - ashub r5, r4 - - cmpw $0x1210, r4 - beq ok -not_ok: - fail -ok: - movw $0x12f1, r4 - movw $-4,r5 - ashub r5, r4 - - test_h_gr r4, 0x12ff - - pass diff --git a/sim/testsuite/sim/cr16/ashub_i.cgs b/sim/testsuite/sim/cr16/ashub_i.cgs deleted file mode 100644 index b4765a4..0000000 --- a/sim/testsuite/sim/cr16/ashub_i.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# cr16 testcase for ashub $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global ashub -ashub: - - movw $0x12f1, r4 - ashub $4, r4 - - cmpw $0x1210, r4 - beq ok -not_ok: - fail -ok: - movw $0x12f1, r4 - ashub $-4, r4 - - test_h_gr r4, 0x12ff - - pass diff --git a/sim/testsuite/sim/cr16/ashud.cgs b/sim/testsuite/sim/cr16/ashud.cgs deleted file mode 100644 index c9511da..0000000 --- a/sim/testsuite/sim/cr16/ashud.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# cr16 testcase for ashud $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global ashud -ashud: - - movd $0xf1234567, (r4,r3) - movw $20,r5 - ashud r5, (r4,r3) - - cmpd $0x56700000, (r4,r3) - beq ok -not_ok: - fail -ok: - movd $0xf1234567, (r4,r3) - movw $-20,r5 - ashud r5, (r4,r3) - - test_h_grp "(r4,r3)", -238 - - pass diff --git a/sim/testsuite/sim/cr16/ashud_i.cgs b/sim/testsuite/sim/cr16/ashud_i.cgs deleted file mode 100644 index 3beb4e3..0000000 --- a/sim/testsuite/sim/cr16/ashud_i.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# cr16 testcase for ashud $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global ashud -ashud: - - movd $0xf1234567, (r4,r3) - ashud $20, (r4,r3) - - cmpd $0x56700000, (r4,r3) - beq ok -not_ok: - fail -ok: - movd $0xf1234567, (r4,r3) - ashud $-20, (r4,r3) - - test_h_grp "(r4,r3)", -238 - - pass diff --git a/sim/testsuite/sim/cr16/ashuw.cgs b/sim/testsuite/sim/cr16/ashuw.cgs deleted file mode 100644 index 8f52e35..0000000 --- a/sim/testsuite/sim/cr16/ashuw.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# cr16 testcase for ashuw $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global ashuw -ashuw: - - movw $0x1ff1, r4 - movw $12,r5 - ashuw r5, r4 - - cmpw $0x1000, r4 - beq ok -not_ok: - fail -ok: - movw $0x1ff1, r4 - movw $-12,r5 - ashuw r5, r4 - - test_h_gr r4, 0x1 - - pass diff --git a/sim/testsuite/sim/cr16/ashuw_i.cgs b/sim/testsuite/sim/cr16/ashuw_i.cgs deleted file mode 100644 index 9925914..0000000 --- a/sim/testsuite/sim/cr16/ashuw_i.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# cr16 testcase for ashuw $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global ashuw -ashuw: - - movw $0x1ff1, r4 - ashuw $12, r4 - - cmpw $0x1000, r4 - beq ok -not_ok: - fail -ok: - movw $0x1ff1, r4 - ashuw $-12, r4 - - test_h_gr r4, 0x1 - - pass diff --git a/sim/testsuite/sim/cr16/bal1_24.cgs b/sim/testsuite/sim/cr16/bal1_24.cgs deleted file mode 100644 index a174b31..0000000 --- a/sim/testsuite/sim/cr16/bal1_24.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# cr16 testcase for bal $disp24 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global bal24 -bal24: - bal (ra), ok - - fail - -ok: - pass diff --git a/sim/testsuite/sim/cr16/bal2_24.cgs b/sim/testsuite/sim/cr16/bal2_24.cgs deleted file mode 100644 index 37cda7f..0000000 --- a/sim/testsuite/sim/cr16/bal2_24.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# cr16 testcase for bal $disp24 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global bal24 -bal24: - bal (r12), ok - - fail - -ok: - pass diff --git a/sim/testsuite/sim/cr16/bcc.cgs b/sim/testsuite/sim/cr16/bcc.cgs deleted file mode 100644 index b0bee2b..0000000 --- a/sim/testsuite/sim/cr16/bcc.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# cr16 testcase for beq disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global beq -beq: - mvi_h_condbit 0 - movw $12, r4 - movw $10, r5 - cmpw r4, r5 - bcc ok -not_ok: - fail -ok: - movw $11, r5 - cmpw r4, r5 - beq not_ok - - pass diff --git a/sim/testsuite/sim/cr16/bcs.cgs b/sim/testsuite/sim/cr16/bcs.cgs deleted file mode 100644 index 0ba14b1..0000000 --- a/sim/testsuite/sim/cr16/bcs.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for bcs disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global bcs -bcs: - mvi_h_condbit 0 - movw $12, r4 - movw $10, r5 - subw r4, r5 - bcs ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/beq.cgs b/sim/testsuite/sim/cr16/beq.cgs deleted file mode 100644 index 35ece27..0000000 --- a/sim/testsuite/sim/cr16/beq.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# cr16 testcase for beq disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global beq -beq: - mvi_h_condbit 0 - movw $12, r4 - movw $12, r5 - cmpw r4, r5 - beq ok -not_ok: - fail -ok: - movw $11, r5 - cmpw r4, r5 - beq not_ok - - pass diff --git a/sim/testsuite/sim/cr16/beq0b.cgs b/sim/testsuite/sim/cr16/beq0b.cgs deleted file mode 100644 index af6a26b..0000000 --- a/sim/testsuite/sim/cr16/beq0b.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# cr16 testcase for beq0b reg disp5 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global beq0b -beq0b: - mvi_h_condbit 0 - movw $0x1200, r4 - beq0b r4, 0x1a -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/beq0w.cgs b/sim/testsuite/sim/cr16/beq0w.cgs deleted file mode 100644 index b3805ac..0000000 --- a/sim/testsuite/sim/cr16/beq0w.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# cr16 testcase for beq disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global beq -beq: - mvi_h_condbit 0 - movw $0, r4 - beq0b r4, 0x1a -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/bge.cgs b/sim/testsuite/sim/cr16/bge.cgs deleted file mode 100644 index bb705e7..0000000 --- a/sim/testsuite/sim/cr16/bge.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for beq disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global beq -beq: - mvi_h_condbit 0 - movw $2, r4 - movw $1, r5 - cmpw r4, r5 - bgt ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/bgt.cgs b/sim/testsuite/sim/cr16/bgt.cgs deleted file mode 100644 index bb705e7..0000000 --- a/sim/testsuite/sim/cr16/bgt.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for beq disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global beq -beq: - mvi_h_condbit 0 - movw $2, r4 - movw $1, r5 - cmpw r4, r5 - bgt ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/bhi.cgs b/sim/testsuite/sim/cr16/bhi.cgs deleted file mode 100644 index 9a88af7..0000000 --- a/sim/testsuite/sim/cr16/bhi.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for beq disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global beq -beq: - mvi_h_condbit 0 - movw $2, r4 - movw $1, r5 - cmpw r4, r5 - bhi ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/bhs.cgs b/sim/testsuite/sim/cr16/bhs.cgs deleted file mode 100644 index 97dcc55..0000000 --- a/sim/testsuite/sim/cr16/bhs.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for bhi disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global bhi -bhi: - mvi_h_condbit 0 - movw $2, r4 - movw $1, r5 - cmpw r4, r5 - bhs ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/bht.cgs b/sim/testsuite/sim/cr16/bht.cgs deleted file mode 100644 index 39912e2..0000000 --- a/sim/testsuite/sim/cr16/bht.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for beq disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global beq -beq: - mvi_h_condbit 0 - movw $1, r4 - movw $2, r5 - cmpw r4, r5 - blt ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/blo.cgs b/sim/testsuite/sim/cr16/blo.cgs deleted file mode 100644 index 39912e2..0000000 --- a/sim/testsuite/sim/cr16/blo.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for beq disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global beq -beq: - mvi_h_condbit 0 - movw $1, r4 - movw $2, r5 - cmpw r4, r5 - blt ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/bls.cgs b/sim/testsuite/sim/cr16/bls.cgs deleted file mode 100644 index f394570..0000000 --- a/sim/testsuite/sim/cr16/bls.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for beq disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global beq -beq: - mvi_h_condbit 0 - movw $1, r4 - movw $2, r5 - cmpw r4, r5 - bls ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/blt.cgs b/sim/testsuite/sim/cr16/blt.cgs deleted file mode 100644 index 39912e2..0000000 --- a/sim/testsuite/sim/cr16/blt.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for beq disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global beq -beq: - mvi_h_condbit 0 - movw $1, r4 - movw $2, r5 - cmpw r4, r5 - blt ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/bne.cgs b/sim/testsuite/sim/cr16/bne.cgs deleted file mode 100644 index 3740f24..0000000 --- a/sim/testsuite/sim/cr16/bne.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# cr16 testcase for bne disp16 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global bne -bne: - movw $1, r4 - movw $2, r5 - cmpw r4,r5 - bne test0pass -test1fail: - fail - -test0pass: - movw $1, r5 - cmpw r4,r5 - bne test1fail - - pass diff --git a/sim/testsuite/sim/cr16/bne0b.cgs b/sim/testsuite/sim/cr16/bne0b.cgs deleted file mode 100644 index 63f3cad..0000000 --- a/sim/testsuite/sim/cr16/bne0b.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# cr16 testcase for bne0b reg disp5 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global ne0b -bne0b: - mvi_h_condbit 0 - movw $0x1201, r4 - bne0b r4, 0x1a -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/bne0w.cgs b/sim/testsuite/sim/cr16/bne0w.cgs deleted file mode 100644 index f45e399..0000000 --- a/sim/testsuite/sim/cr16/bne0w.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# cr16 testcase for bne0w reg disp5 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global bne0w -bne0w: - mvi_h_condbit 0 - movw $1, r4 - bne0w r4, 0x1a -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/br.cgs b/sim/testsuite/sim/cr16/br.cgs deleted file mode 100644 index f7ba86d..0000000 --- a/sim/testsuite/sim/cr16/br.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# cr16 testcase for bc $disp24 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global bc24 -bc24: - - mvi_h_condbit 0 - bne test0fail - br test0pass -test0fail: - fail -test0pass: - - mvi_h_condbit 1 - bne test1pass - fail -test1pass: - - pass - diff --git a/sim/testsuite/sim/cr16/cbitb.cgs b/sim/testsuite/sim/cr16/cbitb.cgs deleted file mode 100644 index 473fd71..0000000 --- a/sim/testsuite/sim/cr16/cbitb.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# cr16 testcase for cbitb $bit_pos, ABS/REGP/REG -# mach: cr16 - - .include "testutils.inc" - - start - - .global cbitb -cbitb: - cbitb $0,_y - loadw _y, r1 - cmpb $0xfe, r1 - beq ok1 -not_ok: - fail - -ok1: - movd $_y, (r1,r0) - cbitb $1,0(r1,r0) - loadw _y, r1 - cmpb $0xfc, r1 - beq ok2 - br not_ok -ok2: - - movw $_y, r1 - cbitb $2,0(r1) - loadw _y, r1 - cmpb $0xf8, r1 - beq ok3 - br not_ok -ok3: - pass - -_y: .word 0xff diff --git a/sim/testsuite/sim/cr16/cbitw.cgs b/sim/testsuite/sim/cr16/cbitw.cgs deleted file mode 100644 index a97698c..0000000 --- a/sim/testsuite/sim/cr16/cbitw.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# cr16 testcase for cbitw -# mach: cr16 - - .include "testutils.inc" - - start - - .global cbitw -cbitw: - cbitw $4,_y - loadw _y, r1 - cmpb $0xef, r1 - beq ok1 -not_ok: - fail - -ok1: - movd $_y, (r1,r0) - cbitw $5,0(r1,r0) - loadw _y, r1 - cmpb $0xcf, r1 - beq ok2 - br not_ok -ok2: - - movw $_y, r1 - cbitw $6,0(r1) - loadw _y, r1 - cmpb $0x8f, r1 - beq ok3 - br not_ok -ok3: - pass - -_y: .word 0xff diff --git a/sim/testsuite/sim/cr16/cmpb.cgs b/sim/testsuite/sim/cr16/cmpb.cgs deleted file mode 100644 index 50984bf..0000000 --- a/sim/testsuite/sim/cr16/cmpb.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# cr16 testcase for cmpb reg1, reg2 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global cmpb -cmpb: - mvi_h_condbit 0 - movw $0x2311, r4 - movw $0x4211, r5 - cmpb r4,r5 - beq ok -not_ok: - fail -ok: - mvi_h_condbit 1 - movw $0x4222, r5 - cmpb r4,r5 - beq not_ok - - pass diff --git a/sim/testsuite/sim/cr16/cmpb_i.cgs b/sim/testsuite/sim/cr16/cmpb_i.cgs deleted file mode 100644 index 591abe9..0000000 --- a/sim/testsuite/sim/cr16/cmpb_i.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for cmpb $imm4, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global cmpb_i -cmpb_i: - mvi_h_condbit 0 - movw $0x2311, r4 - cmpb $0x4211, r4 - beq ok -not_ok: - fail -ok: - mvi_h_condbit 1 - cmpb $0x4222,r4 - beq not_ok - - pass diff --git a/sim/testsuite/sim/cr16/cmpd.cgs b/sim/testsuite/sim/cr16/cmpd.cgs deleted file mode 100644 index cc9e55d..0000000 --- a/sim/testsuite/sim/cr16/cmpd.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# cr16 testcase for cmpd (regp), (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global cmpd -cmpd: - mvi_h_condbit 0 - movd $0x12345678, (r4,r3) - movd $0x12345678, (r6,r5) - cmpd (r4,r3), (r6,r5) - beq ok -not_ok: - fail -ok: - mvi_h_condbit 1 - movd $0x12341234, (r6,r5) - cmpd (r4,r3), (r6,r5) - beq not_ok - - pass diff --git a/sim/testsuite/sim/cr16/cmpd_i.cgs b/sim/testsuite/sim/cr16/cmpd_i.cgs deleted file mode 100644 index ad6018a..0000000 --- a/sim/testsuite/sim/cr16/cmpd_i.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for cmpb $imm32,(regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global cmpd_i -cmpd_i: - mvi_h_condbit 0 - movd $0x12345678, (r4,r3) - cmpd $0x12345678, (r4,r3) - beq ok -not_ok: - fail -ok: - mvi_h_condbit 1 - cmpd $0x12341234, (r4,r3) - beq not_ok - - pass diff --git a/sim/testsuite/sim/cr16/cmpi.cgs b/sim/testsuite/sim/cr16/cmpi.cgs deleted file mode 100644 index cff17e8..0000000 --- a/sim/testsuite/sim/cr16/cmpi.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# cr16 testcase for cmpi $imm16, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global cmpi -cmpi: - mvi_h_condbit 0 - movw $1, r4 - cmpw $1, r4 - beq ok -not_ok: - fail -ok: - mvi_h_condbit 1 - movw $2, r4 - cmpw $2, r4 - bne not_ok - - - pass diff --git a/sim/testsuite/sim/cr16/cmpw.cgs b/sim/testsuite/sim/cr16/cmpw.cgs deleted file mode 100644 index 9d333fb..0000000 --- a/sim/testsuite/sim/cr16/cmpw.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# cr16 testcase for cmp $imm, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global cmp -cmp: - mvi_h_condbit 0 - movw $0x1234, r4 - movw $0x1234, r5 - cmpb r4,r5 - beq ok -not_ok: - fail -ok: - mvi_h_condbit 1 - movw $0x2222, r5 - cmpw r4,r5 - beq not_ok - - pass diff --git a/sim/testsuite/sim/cr16/cmpw_i.cgs b/sim/testsuite/sim/cr16/cmpw_i.cgs deleted file mode 100644 index 31f701c..0000000 --- a/sim/testsuite/sim/cr16/cmpw_i.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for cmpw_i $imm16, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global cmpw_i -cmpw_i: - mvi_h_condbit 0 - movw $0x1234, r4 - cmpw $0x1234, r4 - beq ok -not_ok: - fail -ok: - mvi_h_condbit 1 - cmpw $0x2222, r4 - beq not_ok - - pass diff --git a/sim/testsuite/sim/cr16/excp.cgs b/sim/testsuite/sim/cr16/excp.cgs deleted file mode 100644 index 82d445a..0000000 --- a/sim/testsuite/sim/cr16/excp.cgs +++ /dev/null @@ -1,110 +0,0 @@ -# cr16 testcase for excp uimm4 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global excp -excp: - pass # pass macro use the excp 8 - -## Test 1: bbpsw = 0, bpsw = 1, psw = 0 -# -# # bbsm = 0, bie = 0, bbcond = 0 -# movw $0, r4 -# lpr r4, cr8 -# -# # bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 -# movw $0xc100, r4 -# lpr r4, cr0 -# -# # bbpc = 0 -# movw $0, r4 -# mvtc r4, bbpc -# -# # bpc = 42 -# mvaddr_h_gr r4, 42 -# mvtc r4, bpc -# -# # Copy excp2_handler to excp area of memory. -# ld24 r0,#0x48 # address of excp 2 handler -# ld24 r1,#excp2_handler -# ld r2,@r1 -# st r2,@r0 -# # Set up return address. -# ld24 r5,#excp2_ret1 -# -#excp_insn1: -# excp 2 -# fail -# -#excp2_ret1: -# # test bbsm = 1, bbie = 1, bbcond = 1 -# mvfc r4, cr8 -# test_h_gr r4, 0xc1 -# -# # test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0 -# mvfc r4, cr0 -# test_h_gr r4, 0 -# -# # test bbpc = 42 -# mvfc r4, bbpc -# test_h_gr r4, 42 -# -# # test bpc = proper return address -# mvfc r4, bpc -# test_h_gr r4, excp_insn1 + 4 -# -## Test 2: bbpsw = 1, bpsw = 0, psw = 1 -# -# # bbsm = 1, bie = 1, bbcond = 1 -# mvi_h_gr r4, 0xc1 -# mvtc r4, cr8 -# -# # bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 -# mvi_h_gr r4, 0xc1 -# mvtc r4, cr0 -# -# # bbpc = 42 -# mvaddr_h_gr r4, 42 -# mvtc r4, bbpc -# -# # bpc = 0 -# mvaddr_h_gr r4, 0 -# mvtc r4, bpc -# -# # Set up return address. -# ld24 r5,#excp2_ret2 -# -#excp_insn2: -# excp #2 -# fail -# -#excp2_ret2: -# # test bbsm = 0, bbie = 0, bbcond = 0 -# mvfc r4, cr8 -# test_h_gr r4, 0 -# -# # test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0 -# mvfc r4, cr0 -# test_h_gr r4, 0xc180 -# -# # test bbpc = 0 -# mvfc r4, bbpc -# test_h_gr r4, 0 -# -# # test bpc = proper return address -# mvfc r4, bpc -# test_h_gr r4, excp_insn2 + 4 -# -# pass -# -# .data -# -## Don't use rte as it will undo the effects of excp we're testing. -# -# .p2align 2 -#excp2_handler: -# jmp r5 -# nop diff --git a/sim/testsuite/sim/cr16/hello.ms b/sim/testsuite/sim/cr16/hello.ms deleted file mode 100644 index ab6c482..0000000 --- a/sim/testsuite/sim/cr16/hello.ms +++ /dev/null @@ -1,19 +0,0 @@ -# output(): Hello world!\n -# mach(): cr16 - - .globl _start -_start: - -# write (hello world) - movw $1,r2 - movd $hello,(r4,r3) - loadw length,r5 - movw $0x404,r0 - excp 8 -# exit (0) - movw $0,r2 - movw $0x410,r0 - excp 8 - -length: .long 14 -hello: .ascii "Hello world!\r\n" diff --git a/sim/testsuite/sim/cr16/hw-trap.ms b/sim/testsuite/sim/cr16/hw-trap.ms deleted file mode 100644 index 8c8c185..0000000 --- a/sim/testsuite/sim/cr16/hw-trap.ms +++ /dev/null @@ -1,10 +0,0 @@ -# mach(): cr16 - - .include "testutils.inc" - - start - -# perform trap - movw $0,r2 - movw $0x410,r0 - pass # the pass macro use the trap 8 diff --git a/sim/testsuite/sim/cr16/jal.cgs b/sim/testsuite/sim/cr16/jal.cgs deleted file mode 100644 index 106c864..0000000 --- a/sim/testsuite/sim/cr16/jal.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# cr16 testcase for jal $sr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jal -jal: - movd $ok1, (r5, r4) - lshd $-1, (r5,r4) - jal (ra), (r5,r4) -not_ok: - fail -ok1: - movd $not_ok, (r7, r6) - lshd $-1, (r7,r6) - cmpd (r7,r6), (ra) - beq ok2 - br not_ok -ok2: - movd $ok3, (r5, r4) - lshd $-1, (r5,r4) - jal (r1,r0), (r5,r4) -not_ok1: - br not_ok -ok3: - movd $not_ok1, (r7, r6) - lshd $-1, (r7,r6) - cmpd (r7,r6), (r1,r0) - beq ok4 - br not_ok -ok4: - - pass diff --git a/sim/testsuite/sim/cr16/jcc.cgs b/sim/testsuite/sim/cr16/jcc.cgs deleted file mode 100644 index 84db77a..0000000 --- a/sim/testsuite/sim/cr16/jcc.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jcc (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jcc -jcc: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $12, r4 - movw $10, r5 - cmpw r4, r5 - jcc (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jcs.cgs b/sim/testsuite/sim/cr16/jcs.cgs deleted file mode 100644 index 91d40a3..0000000 --- a/sim/testsuite/sim/cr16/jcs.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jcs (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jcs -jcs: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $12, r4 - movw $10, r5 - subw r4, r5 - jcs (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jeq.cgs b/sim/testsuite/sim/cr16/jeq.cgs deleted file mode 100644 index 824828d..0000000 --- a/sim/testsuite/sim/cr16/jeq.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jeq (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jeq -jeq: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $12, r4 - movw $12, r5 - cmpw r4, r5 - jeq (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jfc.cgs b/sim/testsuite/sim/cr16/jfc.cgs deleted file mode 100644 index 0bf1c29..0000000 --- a/sim/testsuite/sim/cr16/jfc.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jfc (repl) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jfc -jfc: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $2, r4 - movw $1, r5 - subw r4, r5 - jfc (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jfs.cgs b/sim/testsuite/sim/cr16/jfs.cgs deleted file mode 100644 index c14f565..0000000 --- a/sim/testsuite/sim/cr16/jfs.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jfs (repl) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jfs -jfs: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $0xaa, r4 - movw $0xaa, r5 - addb r4, r5 - jfs (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jge.cgs b/sim/testsuite/sim/cr16/jge.cgs deleted file mode 100644 index 685ba4c..0000000 --- a/sim/testsuite/sim/cr16/jge.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jge (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jge -jge: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $2, r4 - movw $1, r5 - cmpw r4, r5 - jge (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jgt.cgs b/sim/testsuite/sim/cr16/jgt.cgs deleted file mode 100644 index e1bed75..0000000 --- a/sim/testsuite/sim/cr16/jgt.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jgt (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jgt -jgt: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $2, r4 - movw $1, r5 - cmpw r4, r5 - jgt (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jhi.cgs b/sim/testsuite/sim/cr16/jhi.cgs deleted file mode 100644 index 0959d1d..0000000 --- a/sim/testsuite/sim/cr16/jhi.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jeq (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jeq -jeq: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $2, r4 - movw $1, r5 - cmpw r4, r5 - jhi (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jhs.cgs b/sim/testsuite/sim/cr16/jhs.cgs deleted file mode 100644 index 80a3944..0000000 --- a/sim/testsuite/sim/cr16/jhs.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jhs (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jhs -jhs: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $1, r4 - movw $2, r5 - subw r4, r5 - jhs (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jlo.cgs b/sim/testsuite/sim/cr16/jlo.cgs deleted file mode 100644 index cf00e3e..0000000 --- a/sim/testsuite/sim/cr16/jlo.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jlo (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jlo -jlo: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $1, r4 - movw $2, r5 - cmpw r4, r5 - jlo (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jls.cgs b/sim/testsuite/sim/cr16/jls.cgs deleted file mode 100644 index be50f74..0000000 --- a/sim/testsuite/sim/cr16/jls.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jeq (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jeq -jeq: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $1, r4 - movw $2, r5 - cmpw r4, r5 - jls (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jlt.cgs b/sim/testsuite/sim/cr16/jlt.cgs deleted file mode 100644 index ca93cf1..0000000 --- a/sim/testsuite/sim/cr16/jlt.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jlt (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jlt -jlt: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $1, r4 - movw $2, r5 - cmpw r4, r5 - jlt (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jne.cgs b/sim/testsuite/sim/cr16/jne.cgs deleted file mode 100644 index fb86889..0000000 --- a/sim/testsuite/sim/cr16/jne.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for jne (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jne -jne: - movd $ok, (r7,r6) - lshd $-1, (r7,r6) - - mvi_h_condbit 0 - movw $0, r4 - movw $1, r5 - cmpw r4, r5 - jne (r7,r6) -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/jump.cgs b/sim/testsuite/sim/cr16/jump.cgs deleted file mode 100644 index df20c15..0000000 --- a/sim/testsuite/sim/cr16/jump.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for jmp (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global jmp -jmp: - movd $ok1, (r4,r3) - jump (r4,r3) - fail -ok1: - movd $ok2, (r4,r3) - jump (r4,r3) - fail -ok2: - pass diff --git a/sim/testsuite/sim/cr16/loadb.cgs b/sim/testsuite/sim/cr16/loadb.cgs deleted file mode 100644 index c591ec9..0000000 --- a/sim/testsuite/sim/cr16/loadb.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for loadb $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global ldb -ldb: - movd $data_loc, (r4,r3) - movw $0,r5 - - loadb 0(r4,r3),r5 - - test_h_gr r5, 0x78 # little endian processor - - pass - -data_loc: - .word 0x5678 - diff --git a/sim/testsuite/sim/cr16/loadd.cgs b/sim/testsuite/sim/cr16/loadd.cgs deleted file mode 100644 index b6a851d..0000000 --- a/sim/testsuite/sim/cr16/loadd.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for loadd 0(regp),regp -# mach(): cr16 - - .include "testutils.inc" - - start - - .global ldb -ldb: - movd $data_loc, (r4,r3) - movd $0,(r6,r5) - - loadd 0(r4,r3),(r6,r5) - - test_h_grp "(r6, r5)", 0x12345678 # little endian processor - - pass - -data_loc: - .long 0x12345678 - diff --git a/sim/testsuite/sim/cr16/loadm.cgs b/sim/testsuite/sim/cr16/loadm.cgs deleted file mode 100644 index 8bd6d11..0000000 --- a/sim/testsuite/sim/cr16/loadm.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# cr16 testcase for loadm count -# mach(): cr16 - - .include "testutils.inc" - - start - - .global loadm -loadm: - movw $0x1000, r0 - movw $0x12, r2 - storw r2, 0x1000 - movw $0x34, r3 - storw r3, 0x1002 - movw $0x56, r4 - storw r4, 0x1004 - movw $0x78, r5 - storw r5, 0x1006 - - loadm $4 - - cmpw $0x12,r2 - beq ok1 -not_ok: - fail -ok1: - cmpw $0x34,r3 - beq ok2 - br not_ok -ok2: - cmpw $0x56,r4 - beq ok3 - br not_ok -ok3: - cmpw $0x78,r5 - beq ok4 - br not_ok -ok4: - pass - pass - diff --git a/sim/testsuite/sim/cr16/loadmp.cgs b/sim/testsuite/sim/cr16/loadmp.cgs deleted file mode 100644 index 6003c3f..0000000 --- a/sim/testsuite/sim/cr16/loadmp.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# cr16 testcase for loadmp count -# mach(): cr16 - - .include "testutils.inc" - - start - - .global loadmp -loadmp: - movd $0x1000, (r1,r0) - movw $0x12, r2 - storw r2, 0x1000 - movw $0x34, r3 - storw r3, 0x1002 - movw $0x56, r4 - storw r4, 0x1004 - movw $0x78, r5 - storw r5, 0x1006 - - loadmp $4 - - cmpw $0x12,r2 - beq ok1 -not_ok: - fail -ok1: - cmpw $0x34,r3 - beq ok2 - br not_ok -ok2: - cmpw $0x56,r4 - beq ok3 - br not_ok -ok3: - cmpw $0x78,r5 - beq ok4 - br not_ok -ok4: - pass - diff --git a/sim/testsuite/sim/cr16/loadw.cgs b/sim/testsuite/sim/cr16/loadw.cgs deleted file mode 100644 index 8faf616..0000000 --- a/sim/testsuite/sim/cr16/loadw.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for loadw 0(regp), (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global ldb -ldb: - movd $data_loc, (r4,r3) - movw $0,r5 - - loadw 0(r4,r3),r5 - - test_h_gr r5, 0x5678 # little endian processor - - pass - -data_loc: - .word 0x5678 - diff --git a/sim/testsuite/sim/cr16/lpr-spr.cgs b/sim/testsuite/sim/cr16/lpr-spr.cgs deleted file mode 100644 index c2679ea..0000000 --- a/sim/testsuite/sim/cr16/lpr-spr.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for lpr reg, preg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global lpr -lpr: - movw $0x1234,r3 - lpr r3, psr - - spr psr,r5 - - - test_h_gr r5, 0x1234 - - pass diff --git a/sim/testsuite/sim/cr16/lprd-sprd.cgs b/sim/testsuite/sim/cr16/lprd-sprd.cgs deleted file mode 100644 index 3df8de3..0000000 --- a/sim/testsuite/sim/cr16/lprd-sprd.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for lprd reg, preg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global lprd -lprd: - movd $0x12345678,(r4,r3) - lprd (r4,r3), psr - - sprd psr,(r6,r5) - - - test_h_grp "(r6,r5)", 0x12345678 - - pass diff --git a/sim/testsuite/sim/cr16/lshb.cgs b/sim/testsuite/sim/cr16/lshb.cgs deleted file mode 100644 index 59ddbba..0000000 --- a/sim/testsuite/sim/cr16/lshb.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# cr16 testcase for lshb count, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global lshb -lshb: - movb $6, r4 - movb $1, r5 - lshb r5, r4 - test_h_gr r4, 12 - - pass diff --git a/sim/testsuite/sim/cr16/lshb_i.cgs b/sim/testsuite/sim/cr16/lshb_i.cgs deleted file mode 100644 index 10d3085..0000000 --- a/sim/testsuite/sim/cr16/lshb_i.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# cr16 testcase for lshb_i $uimm5, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global lshb_i -lshb_i: - movb $6,r4 - lshb $1, r4 - test_h_gr r4, 12 - - pass diff --git a/sim/testsuite/sim/cr16/lshd.cgs b/sim/testsuite/sim/cr16/lshd.cgs deleted file mode 100644 index e146ca1..0000000 --- a/sim/testsuite/sim/cr16/lshd.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# cr16 testcase for lshd reg, regp -# mach(): cr16 - - .include "testutils.inc" - - start - - .global lshd -lshd: - movd $0x12345678, (r4,r3) - movw $0x10, r5 - lshd r5, (r4,r3) - test_h_grp "(r4,r3)", 0x56780000 - - pass diff --git a/sim/testsuite/sim/cr16/lshd_i.cgs b/sim/testsuite/sim/cr16/lshd_i.cgs deleted file mode 100644 index aa65933..0000000 --- a/sim/testsuite/sim/cr16/lshd_i.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# cr16 testcase for lshb_i $uimm5, regp -# mach(): cr16 - - .include "testutils.inc" - - start - - .global lshb_i -lshb_i: - movd $0x12345678,(r4,r3) - lshd $16, (r4,r3) - test_h_grp "(r4,r3)", 0x56780000 - - pass diff --git a/sim/testsuite/sim/cr16/lshw.cgs b/sim/testsuite/sim/cr16/lshw.cgs deleted file mode 100644 index a10edff..0000000 --- a/sim/testsuite/sim/cr16/lshw.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# cr16 testcase for lshw reg, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global lshw -lshw: - movw $0x1234, r4 - movw $8, r5 - lshw r5, r4 - test_h_gr r4, 0x3400 - - pass diff --git a/sim/testsuite/sim/cr16/lshw_i.cgs b/sim/testsuite/sim/cr16/lshw_i.cgs deleted file mode 100644 index 9e94a5e..0000000 --- a/sim/testsuite/sim/cr16/lshw_i.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# cr16 testcase for lshb_i $uimm4, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global lshb_i -lshb_i: - movw $0x1234,r4 - lshw $8, r4 - test_h_gr r4, 0x3400 - - pass diff --git a/sim/testsuite/sim/cr16/macqw.cgs b/sim/testsuite/sim/cr16/macqw.cgs deleted file mode 100644 index 4c6da4f..0000000 --- a/sim/testsuite/sim/cr16/macqw.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# cr16 testcase for macqw reg, (regp) -# mach(): cr16 - - .include "testutils.inc" - - start # REVIST to update testcase - - .global macqw -macqw: - movw $0x123,r3 - movw $0x456,r4 - macqw r3, r4, (r6,r5) - test_h_grp "(r6,r5)", 0x4edc2 - - pass diff --git a/sim/testsuite/sim/cr16/macsw.cgs b/sim/testsuite/sim/cr16/macsw.cgs deleted file mode 100644 index 8a0f227..0000000 --- a/sim/testsuite/sim/cr16/macsw.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# cr16 testcase for macsw reg, (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global macsw # REVISIT to update this testcase -macsw: - movw $0x123,r3 - movw $0x456,r4 - macsw r3,r4, (r6,r5) - test_h_grp "(r6,r5)", 0x4edc2 - - pass diff --git a/sim/testsuite/sim/cr16/macuw.cgs b/sim/testsuite/sim/cr16/macuw.cgs deleted file mode 100644 index ea4c3fc..0000000 --- a/sim/testsuite/sim/cr16/macuw.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# cr16 testcase for macuw reg, reg, (regp) -# mach(): cr16 - - .include "testutils.inc" - - start # REVIST to update testcase - - .global macuw -macuw: - movw $0x123,r3 - movw $0x456,r4 - macuw r3, r4, (r6,r5) - test_h_grp "(r6,r5)", 0x4edc2 - - pass diff --git a/sim/testsuite/sim/cr16/misc.exp b/sim/testsuite/sim/cr16/misc.exp deleted file mode 100644 index 39dd3a4..0000000 --- a/sim/testsuite/sim/cr16/misc.exp +++ /dev/null @@ -1,31 +0,0 @@ -# Miscellaneous CR16 simulator testcases - -if [istarget cr16*-*-*] { - # load support procs - # load_lib cgen.exp - - # all machines - set all_machs "cr16" - - global global_sim_options - if ![info exists global_sim_options] { - set global_sim_options "" - } - set saved_global_sim_options $global_sim_options - # The cr16 linker sets the default LMA base to 0, and all the code - # expects the VMA when running, so use that when running the tests. - set global_sim_options "$saved_global_sim_options --load-vma" - - # The .ms suffix is for "miscellaneous .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } - - set global_sim_options $saved_global_sim_options -} diff --git a/sim/testsuite/sim/cr16/movb.cgs b/sim/testsuite/sim/cr16/movb.cgs deleted file mode 100644 index fc8fcba..0000000 --- a/sim/testsuite/sim/cr16/movb.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for movb $imm, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global movb -movb: - movb $1, r4 - movb $0, r5 - - movb r4, r5 - - test_h_gr r5, 1 - - pass diff --git a/sim/testsuite/sim/cr16/movd.cgs b/sim/testsuite/sim/cr16/movd.cgs deleted file mode 100644 index 8b1b638..0000000 --- a/sim/testsuite/sim/cr16/movd.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# cr16 testcase for movd $imm32, regp -# mach(): cr16 - - .include "testutils.inc" - - start - - .global movd -movd: - movd $0x12345678, (r4,r3) - - movd (r4,r3), (r6,r5) - - test_h_grp "(r6,r5)", 0x12345678 - - pass diff --git a/sim/testsuite/sim/cr16/movw.cgs b/sim/testsuite/sim/cr16/movw.cgs deleted file mode 100644 index e14afb0..0000000 --- a/sim/testsuite/sim/cr16/movw.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# cr16 testcase for movw $imm16, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global movw -movw: - movw $0x1234, r4 - - movw r4, r5 - - test_h_gr r5, 0x1234 - - pass diff --git a/sim/testsuite/sim/cr16/movxb.cgs b/sim/testsuite/sim/cr16/movxb.cgs deleted file mode 100644 index 3c356c9..0000000 --- a/sim/testsuite/sim/cr16/movxb.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for movb $imm4, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global movb -movb: - movb $0xf, r4 - movw $0x1234, r5 - - movxb r4, r5 - - test_h_gr r5, 0xf - - pass diff --git a/sim/testsuite/sim/cr16/movxw.cgs b/sim/testsuite/sim/cr16/movxw.cgs deleted file mode 100644 index 77dea80..0000000 --- a/sim/testsuite/sim/cr16/movxw.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for movw reg, regp -# mach(): cr16 - - .include "testutils.inc" - - start - - .global movw -movw: - movw $0x1234, r4 - movd $0, (r6,r5) - - movxw r4, (r6,r5) - - test_h_grp "(r6, r5)", 0x1234 - - pass diff --git a/sim/testsuite/sim/cr16/movzb.cgs b/sim/testsuite/sim/cr16/movzb.cgs deleted file mode 100644 index acbe2b6..0000000 --- a/sim/testsuite/sim/cr16/movzb.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for movzb reg, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global movzb -movzb: - movw $0x120f, r4 - movw $0x1200, r5 - - movzb r4, r5 - - test_h_gr r5, 0xf - - pass diff --git a/sim/testsuite/sim/cr16/movzw.cgs b/sim/testsuite/sim/cr16/movzw.cgs deleted file mode 100644 index 93855e4..0000000 --- a/sim/testsuite/sim/cr16/movzw.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for movzw reg, regp -# mach(): cr16 - - .include "testutils.inc" - - start - - .global movzw -movzw: - movb $0xff, r4 - movd $0x12345678,(r6, r5) - - movzw r4, (r6,r5) - - test_h_grp "(r6, r5)", 0xff - - pass diff --git a/sim/testsuite/sim/cr16/mulb.cgs b/sim/testsuite/sim/cr16/mulb.cgs deleted file mode 100644 index c4b859f..0000000 --- a/sim/testsuite/sim/cr16/mulb.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# cr16 testcase for mulb $imm4/imm16/reg,$reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global mulb -mulb: - movw $0x1234,r4 - movw $0x4567,r5 - - mulb r4, r5 - cmpb $0xec, r5 - beq ok1 -not_ok: - fail - -ok1: - movw $3,r4 - mulb $7,r4 - cmpb $21, r4 - beq ok - br not_ok -ok: - movw $3,r4 - mulb $0x1207, r4 - test_h_gr r4, 21 - - pass diff --git a/sim/testsuite/sim/cr16/mulsb.cgs b/sim/testsuite/sim/cr16/mulsb.cgs deleted file mode 100644 index 60912af..0000000 --- a/sim/testsuite/sim/cr16/mulsb.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# cr16 testcase for mulsb $imm4/imm16/reg, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global mulsb -mulsb: - movw $-3,r4 - movw $7,r5 - - mulsb r4, r5 - cmpw $-21, r5 - beq ok1 -not_ok: - fail - -ok1: - movw $3,r4 - mulw $7, r4 - test_h_gr r4, 21 - - pass diff --git a/sim/testsuite/sim/cr16/mulsw.cgs b/sim/testsuite/sim/cr16/mulsw.cgs deleted file mode 100644 index 5bf5ac1..0000000 --- a/sim/testsuite/sim/cr16/mulsw.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# cr16 testcase for mulsw reg, (regp) -# mach(): cr16 - - .include "testutils.inc" - - start - - .global mulsw -mulsw: - movw $0xfff,r4 # fix for 0xffff - movd $0xffffffff,(r6,r5) - - mulsw r4, (r6,r5) - test_h_grp "(r6,r5)", 0xfffff001 - - pass diff --git a/sim/testsuite/sim/cr16/muluw.cgs b/sim/testsuite/sim/cr16/muluw.cgs deleted file mode 100644 index 71f7ee0..0000000 --- a/sim/testsuite/sim/cr16/muluw.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# cr16 testcase for muluw reg, regp -# mach(): cr16 - - .include "testutils.inc" - - start - - .global muluw -muluw: - movw $0xfff,r4 # fix for 0xffff - movd $0xffffffff,(r6,r5) - - muluw r4, (r6,r5) - test_h_grp "(r6,r5)", 0xffef001 - - pass diff --git a/sim/testsuite/sim/cr16/mulw.cgs b/sim/testsuite/sim/cr16/mulw.cgs deleted file mode 100644 index cbd4552..0000000 --- a/sim/testsuite/sim/cr16/mulw.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# cr16 testcase for mulw reg reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global mulw -mulw: - movw $0x1234,r4 - movw $0x1234,r5 - - mulw r4, r5 - cmpw $0x5a90, r5 - beq ok1 -not_ok: - fail - -ok1: - mulw $0x1234, r4 - test_h_gr r4, 0x5a90 - - pass diff --git a/sim/testsuite/sim/cr16/nop.cgs b/sim/testsuite/sim/cr16/nop.cgs deleted file mode 100644 index e29fa93..0000000 --- a/sim/testsuite/sim/cr16/nop.cgs +++ /dev/null @@ -1,11 +0,0 @@ -# cr16 testcase for nop -# mach(): cr16 - - .include "testutils.inc" - - start - - .global nop -nop: - nop - pass diff --git a/sim/testsuite/sim/cr16/orb.cgs b/sim/testsuite/sim/cr16/orb.cgs deleted file mode 100644 index 43ce26b..0000000 --- a/sim/testsuite/sim/cr16/orb.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for orb $imm, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global orb -orb: - movb $3, r4 - movb $6, r5 - - orb r4,r5 - - test_h_gr r5, 7 - - pass diff --git a/sim/testsuite/sim/cr16/ord.cgs b/sim/testsuite/sim/cr16/ord.cgs deleted file mode 100644 index e682d3a..0000000 --- a/sim/testsuite/sim/cr16/ord.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for ord $imm32, regp -# mach(): cr16 - - .include "testutils.inc" - - start - - .global ord -ord: - movd $0x33333333, (r4,r3) - movd $0x66666666, (r6,r5) - - ord (r4,r3), (r6,r5) - - test_h_grp "(r6,r5)", 0x77777777 - - pass diff --git a/sim/testsuite/sim/cr16/orw.cgs b/sim/testsuite/sim/cr16/orw.cgs deleted file mode 100644 index 4c1b529..0000000 --- a/sim/testsuite/sim/cr16/orw.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for orw reg, reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global orw -orw: - movw $3, r4 - movw $6, r5 - - orw r4, r5 - - test_h_gr r5, 7 - - pass diff --git a/sim/testsuite/sim/cr16/pop1.cgs b/sim/testsuite/sim/cr16/pop1.cgs deleted file mode 100644 index cf2a02d..0000000 --- a/sim/testsuite/sim/cr16/pop1.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# cr16 testcase for pop count reg RA insns. -# mach: cr16 - - .include "testutils.inc" - - start - - .global pop1 -pop1: - movd $0x1000, (sp) - movw $0x2f50, r3 - storw r3, 0x1000 - movw $0x107e, r3 - storw r3, 0x1002 - movw $0x35ec, r3 - storw r3, 0x1004 - - movd $0xabcd, (r3,r2) - stord (r3,r2), 0x1006 - - pop $3,r5, RA - - cmpw $0x2f50,r5 - beq ok1 - br not_ok -not_ok: - fail -ok1: - cmpw $0x107e,r6 - beq ok2 - br not_ok -ok2: - cmpw $0x35ec,r7 - beq ok3 - br not_ok - -ok3: - cmpd $0xabcd, (ra) - beq ok4 - br not_ok -ok4: - pass diff --git a/sim/testsuite/sim/cr16/pop2.cgs b/sim/testsuite/sim/cr16/pop2.cgs deleted file mode 100644 index aa3a9ec..0000000 --- a/sim/testsuite/sim/cr16/pop2.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# cr16 testcase for pop count reg insns. -# mach: cr16 - - .include "testutils.inc" - - start - - .global pop2 -pop2: - movd $0x1000, (sp) - movw $0x2f50, r3 - storw r3, 0x1000 - movw $0x107e, r3 - storw r3, 0x1002 - movw $0x35ec, r3 - storw r3, 0x1004 - - pop $3,r5 - - cmpw $0x2f50,r5 - beq ok1 - br not_ok -not_ok: - fail -ok1: - cmpw $0x107e,r6 - beq ok2 - br not_ok -ok2: - cmpw $0x35ec,r7 - beq ok3 - br not_ok - -ok3: - pass diff --git a/sim/testsuite/sim/cr16/pop3.cgs b/sim/testsuite/sim/cr16/pop3.cgs deleted file mode 100644 index 13478f1..0000000 --- a/sim/testsuite/sim/cr16/pop3.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# cr16 testcase for pop RA insns. -# mach: cr16 - - .include "testutils.inc" - - start - - .global pop3 -pop3: - movd $0x1006, (sp) - movd $0xabcd, (r3,r2) - stord (r3,r2), 0x1006 - pop RA - - - cmpd $0xabcd, (ra) - beq ok - br not_ok -not_ok: - fail -ok: - pass - - diff --git a/sim/testsuite/sim/cr16/popret1.cgs b/sim/testsuite/sim/cr16/popret1.cgs deleted file mode 100644 index a34b0fb..0000000 --- a/sim/testsuite/sim/cr16/popret1.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# cr16 testcase for popret count reg RA insns. -# mach: cr16 - - .include "testutils.inc" - - start - - .global popret1 -popret1: - movd $0x1000, (sp) - movw $0x2f50, r3 - storw r3, 0x1000 - movw $0x107e, r3 - storw r3, 0x1002 - movw $0x35ec, r3 - storw r3, 0x1004 - - movd $ok, (r3,r2) # jump to ok - lshd $-1, (r3,r2) - stord (r3,r2), 0x1006 - - popret $3,r5, RA - -ok: - cmpw $0x2f50,r5 - beq ok1 - br not_ok -not_ok: - fail -ok1: - cmpw $0x107e,r6 - beq ok2 - br not_ok -ok2: - cmpw $0x35ec,r7 - beq ok3 - br not_ok - -ok3: - pass diff --git a/sim/testsuite/sim/cr16/popret2.cgs b/sim/testsuite/sim/cr16/popret2.cgs deleted file mode 100644 index 5a7f905..0000000 --- a/sim/testsuite/sim/cr16/popret2.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# cr16 testcase for popret count reg insns. -# mach: cr16 - - .include "testutils.inc" - - start - - .global popret2 -popret2: - movd $0x1000, (sp) - movw $0x2f50, r3 - storw r3, 0x1000 - movw $0x107e, r3 - storw r3, 0x1002 - movw $0x35ec, r3 - storw r3, 0x1004 - - movd $ok, (ra) - lshd $-1, (ra) - stord (ra), 0x1006 - - popret $3,r5 - -ok: - cmpw $0x2f50,r5 - beq ok1 - br not_ok -not_ok: - fail -ok1: - cmpw $0x107e,r6 - beq ok2 - br not_ok -ok2: - cmpw $0x35ec,r7 - beq ok3 - br not_ok - -ok3: - pass diff --git a/sim/testsuite/sim/cr16/popret3.cgs b/sim/testsuite/sim/cr16/popret3.cgs deleted file mode 100644 index 31aaa9b..0000000 --- a/sim/testsuite/sim/cr16/popret3.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for popret RA insns. -# mach: cr16 - - .include "testutils.inc" - - start - - .global popret3 -popret3: - movd $0x1006, (sp) - movd $ok, (ra) - lshd $-1, (ra) - stord (ra), 0x1006 - popret RA - -ok: - pass diff --git a/sim/testsuite/sim/cr16/push1.cgs b/sim/testsuite/sim/cr16/push1.cgs deleted file mode 100644 index 12d50a6..0000000 --- a/sim/testsuite/sim/cr16/push1.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# cr16 testcase for push count reg RA insns. -# mach: cr16 - - .include "testutils.inc" - - start - - .global push1 -push1: - movd $0x100a, (sp) - movd $0xabcd, (ra) - movw $0x2f50, r5 - movw $0x107e, r6 - movw $0x35ed, r7 - push $3,r5,RA - - loadw 0x1000, r3 - cmpw r3,r5 - beq ok1 - br not_ok -not_ok: - fail -ok1: - loadw 0x1002, r3 - cmpw r3,r6 - beq ok2 - br not_ok -ok2: - loadw 0x1004, r3 - cmpw r3,r7 - beq ok3 - br not_ok - -ok3: - loadd 0x1006, (r3,r2) - cmpd (r3,r2), (ra) - beq ok4 - br not_ok - -ok4: - pass diff --git a/sim/testsuite/sim/cr16/push2.cgs b/sim/testsuite/sim/cr16/push2.cgs deleted file mode 100644 index 76c1a37..0000000 --- a/sim/testsuite/sim/cr16/push2.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# cr16 testcase for push count reg insns. -# mach: cr16 - - .include "testutils.inc" - - start - - .global push2 -push2: - movd $0x1006, (sp) - movw $0x2f50, r5 - movw $0x107e, r6 - movw $0x35ed, r7 - push $3,r5 - - loadw 0x1000, r3 - cmpw r3,r5 - beq ok1 - br not_ok -not_ok: - fail -ok1: - loadw 0x1002, r3 - cmpw r3,r6 - beq ok2 - br not_ok -ok2: - loadw 0x1004, r3 - cmpw r3,r7 - beq ok3 - br not_ok - -ok3: - pass - - diff --git a/sim/testsuite/sim/cr16/push3.cgs b/sim/testsuite/sim/cr16/push3.cgs deleted file mode 100644 index f9f5c26..0000000 --- a/sim/testsuite/sim/cr16/push3.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# cr16 testcase for push RA insns. -# mach: cr16 - - .include "testutils.inc" - - start - - .global push1 -push1: - movd $0x1006, (sp) - movd $0xabcd, (ra) - push RA - - - loadd 0x1002, (r3,r2) - cmpd (r3,r2), (ra) - beq ok - br not_ok -not_ok: - fail -ok: - pass - - diff --git a/sim/testsuite/sim/cr16/sbitb.cgs b/sim/testsuite/sim/cr16/sbitb.cgs deleted file mode 100644 index b98329c..0000000 --- a/sim/testsuite/sim/cr16/sbitb.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# cr16 testcase for sbitb $count, reg/regp/mem -# mach: cr16 - - .include "testutils.inc" - - start - - .global sbitb -sbitb: - sbitb $0,_y - loadw _y, r1 - cmpb $0xf1, r1 - beq ok1 -not_ok: - fail - -ok1: - movd $_y, (r1,r0) - sbitb $1,0(r1,r0) - loadw _y, r1 - cmpb $0xf3, r1 - beq ok2 - br not_ok -ok2: - - movw $_y, r1 - sbitb $2,0(r1) - loadw _y, r1 - cmpb $0xf7, r1 - beq ok3 - br not_ok -ok3: - pass - -_y: .word 0xf0 diff --git a/sim/testsuite/sim/cr16/sbitw.cgs b/sim/testsuite/sim/cr16/sbitw.cgs deleted file mode 100644 index 2a9a828..0000000 --- a/sim/testsuite/sim/cr16/sbitw.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# cr16 testcase for sbitw -# mach: cr16 - - .include "testutils.inc" - - start - - .global sbitw -sbitw: - sbitw $4,_y - loadw _y, r1 - cmpb $0x1f, r1 - beq ok1 -not_ok: - fail - -ok1: - movd $_y, (r1,r0) - sbitw $5,0(r1,r0) - loadw _y, r1 - cmpb $0x3f, r1 - beq ok2 - br not_ok -ok2: - - movw $_y, r1 - sbitw $6,0(r1) - loadw _y, r1 - cmpb $0x7f, r1 - beq ok3 - br not_ok -ok3: - pass - -_y: .word 0x0f diff --git a/sim/testsuite/sim/cr16/scc.cgs b/sim/testsuite/sim/cr16/scc.cgs deleted file mode 100644 index ac592e0..0000000 --- a/sim/testsuite/sim/cr16/scc.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for scc reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global scc -scc: - mvi_h_condbit 0 - movw $12, r4 - movw $10, r5 - cmpw r4, r5 - scc r3 - - cmpw $1, r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/scs.cgs b/sim/testsuite/sim/cr16/scs.cgs deleted file mode 100644 index a34e094..0000000 --- a/sim/testsuite/sim/cr16/scs.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for scs reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global scs -scs: - mvi_h_condbit 0 - movw $12, r4 - movw $10, r5 - subw r4, r5 - scs r3 - - cmpw $1, r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/seq.cgs b/sim/testsuite/sim/cr16/seq.cgs deleted file mode 100644 index 1b4ad79..0000000 --- a/sim/testsuite/sim/cr16/seq.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# cr16 testcase for seq reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global seq -seq: - mvi_h_condbit 0 - movw $12, r4 - movw $12, r5 - cmpw r4, r5 - seq r3 - cmpw $1, r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/sfc.cgs b/sim/testsuite/sim/cr16/sfc.cgs deleted file mode 100644 index 1221f8e..0000000 --- a/sim/testsuite/sim/cr16/sfc.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# cr16 testcase for sfc rep -# mach(): cr16 - - .include "testutils.inc" - - start - - .global sfc -sfc: - mvi_h_condbit 0 - movw $2, r4 - movw $1, r5 - subw r4, r5 - sfc r3 - cmpw $1, r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/sfs.cgs b/sim/testsuite/sim/cr16/sfs.cgs deleted file mode 100644 index 5663bfb..0000000 --- a/sim/testsuite/sim/cr16/sfs.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for sfs reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global sfs -sfs: - mvi_h_condbit 0 - movw $0xaa, r4 - movw $0xaa, r5 - addb r4, r5 - sfs r3 - - cmpw $1, r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/sge.cgs b/sim/testsuite/sim/cr16/sge.cgs deleted file mode 100644 index 7a65658..0000000 --- a/sim/testsuite/sim/cr16/sge.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# cr16 testcase for sge reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global sge -sge: - mvi_h_condbit 0 - movw $2, r4 - movw $1, r5 - cmpw r4, r5 - sge r3 - cmpw $1, r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/sgt.cgs b/sim/testsuite/sim/cr16/sgt.cgs deleted file mode 100644 index cc47ea3..0000000 --- a/sim/testsuite/sim/cr16/sgt.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# cr16 testcase for sgt reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global sgt -sgt: - mvi_h_condbit 0 - movw $2, r4 - movw $1, r5 - cmpw r4, r5 - sgt r3 - cmpw $1, r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/shi.cgs b/sim/testsuite/sim/cr16/shi.cgs deleted file mode 100644 index 5188a51..0000000 --- a/sim/testsuite/sim/cr16/shi.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for shi reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global shi -shi: - mvi_h_condbit 0 - movw $2, r4 - movw $1, r5 - cmpw r4, r5 - shi r3 - - cmpw $1,r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/shs.cgs b/sim/testsuite/sim/cr16/shs.cgs deleted file mode 100644 index 2a10324..0000000 --- a/sim/testsuite/sim/cr16/shs.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for shs reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global shs -shs: - mvi_h_condbit 0 - movw $1, r4 - movw $2, r5 - subw r4, r5 - shs r3 - - cmpw $1, r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/slo.cgs b/sim/testsuite/sim/cr16/slo.cgs deleted file mode 100644 index 4e9332a..0000000 --- a/sim/testsuite/sim/cr16/slo.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for slo reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global slo -slo: - mvi_h_condbit 0 - movw $1, r4 - movw $2, r5 - cmpw r4, r5 - slo r3 - - cmpw $1, r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/sls.cgs b/sim/testsuite/sim/cr16/sls.cgs deleted file mode 100644 index aab309c..0000000 --- a/sim/testsuite/sim/cr16/sls.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for sls reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global sls -sls: - mvi_h_condbit 0 - movw $1, r4 - movw $2, r5 - cmpw r4, r5 - sls r3 - - cmpw $1, r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/slt.cgs b/sim/testsuite/sim/cr16/slt.cgs deleted file mode 100644 index a4fa1b5..0000000 --- a/sim/testsuite/sim/cr16/slt.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for slt rep -# mach(): cr16 - - .include "testutils.inc" - - start - - .global slt -slt: - mvi_h_condbit 0 - movw $1, r4 - movw $2, r5 - cmpw r4, r5 - slt r3 - - cmpw $1,r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/sne.cgs b/sim/testsuite/sim/cr16/sne.cgs deleted file mode 100644 index 0d2ccc5..0000000 --- a/sim/testsuite/sim/cr16/sne.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for sne reg -# mach(): cr16 - - .include "testutils.inc" - - start - - .global sne -sne: - mvi_h_condbit 0 - movw $0, r4 - movw $1, r5 - cmpw r4, r5 - sne r3 - - cmpw $1, r3 - beq ok -not_ok: - fail -ok: - pass diff --git a/sim/testsuite/sim/cr16/storb.cgs b/sim/testsuite/sim/cr16/storb.cgs deleted file mode 100644 index 289055d..0000000 --- a/sim/testsuite/sim/cr16/storb.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for st $src1,@$src2 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global st -st: - movd $data_loc, (r4,r3) - movw $1,r5 - - storw r5, 0(r4,r3) - - loadw 0(r4,r3),r1 - test_h_gr r1, 1 - - pass - -data_loc: - .word 0 diff --git a/sim/testsuite/sim/cr16/stord.cgs b/sim/testsuite/sim/cr16/stord.cgs deleted file mode 100644 index 64f40c1..0000000 --- a/sim/testsuite/sim/cr16/stord.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for st $src1,@$src2 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global st -st: - movd $data_loc, (r4,r3) - movd $0x12345678, (r6,r5) - - stord (r6,r5),0(r4,r3) - - loadd 0(r4,r3), (r1,r0) - test_h_grp "( r1,r0)", 0x12345678 - - pass - -data_loc: - .word 0 diff --git a/sim/testsuite/sim/cr16/storw.cgs b/sim/testsuite/sim/cr16/storw.cgs deleted file mode 100644 index 9287636..0000000 --- a/sim/testsuite/sim/cr16/storw.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# cr16 testcase for st $src1,@$src2 -# mach(): cr16 - - .include "testutils.inc" - - start - - .global st -st: - movd $data_loc, (r4,r3) - movw $0x1234,r5 - - storw r5,0(r4,r3) - - loadw 0(r4,r3),r1 - test_h_gr r1, 0x1234 - - pass - -data_loc: - .word 0 diff --git a/sim/testsuite/sim/cr16/subb.cgs b/sim/testsuite/sim/cr16/subb.cgs deleted file mode 100644 index 6a893dd..0000000 --- a/sim/testsuite/sim/cr16/subb.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for subb $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global subb -subb: - - movb $7, r4 - movb $3, r5 - - subb r5, r4 - - test_h_gr r4, 4 - - pass diff --git a/sim/testsuite/sim/cr16/subd.cgs b/sim/testsuite/sim/cr16/subd.cgs deleted file mode 100644 index 2e2a334..0000000 --- a/sim/testsuite/sim/cr16/subd.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for subd $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global subd -subd: - - movd $0x12345678, (r4,r3) - movd $0x11111111, (r6,r5) - - subd (r6,r5), (r4,r3) - - test_h_grp "(r4,r3)", 0x1234567 - - pass diff --git a/sim/testsuite/sim/cr16/subi.cgs b/sim/testsuite/sim/cr16/subi.cgs deleted file mode 100644 index 5d0fa1a..0000000 --- a/sim/testsuite/sim/cr16/subi.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# cr16 testcase for addi #$simm8, $dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global addi -addi: - - movb $1, r4 - addb $2, r4 - - cmpb $3,r4 - bne not_ok - - movw $0x1234, r5 - addw $0x1234, r5 - test_h_gr r5, 0x2468 - - pass - - movd $0x12345678, (r5,r4) - addd $0x12345678, (r5,r4) - test_h_grp "(r5,r4)", 0x2468acf0 - - pass - -not_ok: - fail diff --git a/sim/testsuite/sim/cr16/subw.cgs b/sim/testsuite/sim/cr16/subw.cgs deleted file mode 100644 index 12a1229..0000000 --- a/sim/testsuite/sim/cr16/subw.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# cr16 testcase for subw $sr,$dr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global subw -subw: - - movw $0x1234, r4 - movw $0x1111, r5 - - subw r5, r4 - - test_h_gr r4, 0x123 - - pass diff --git a/sim/testsuite/sim/cr16/tbit.cgs b/sim/testsuite/sim/cr16/tbit.cgs deleted file mode 100644 index ac1b7e2..0000000 --- a/sim/testsuite/sim/cr16/tbit.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# cr16 testcase for tbit -# mach: cr16 - - .include "testutils.inc" - - start - - .global tbit -tbit: - movw $0, r1 - lpr r1, psr - movw $0x7, r1 - tbit $0, r1 - spr psr, r1 - cmpb $0x20, r1 - beq ok1 -not_ok: - fail - -ok1: - movw $0, r1 - lpr r1, psr - movw $0xa, r1 - movw $0x1, r2 - tbit r2,r1 - spr psr, r1 - cmpb $0x20, r1 - beq ok2 - br not_ok -ok2: - pass diff --git a/sim/testsuite/sim/cr16/tbitb.cgs b/sim/testsuite/sim/cr16/tbitb.cgs deleted file mode 100644 index 57a8ab2..0000000 --- a/sim/testsuite/sim/cr16/tbitb.cgs +++ /dev/null @@ -1,33 +0,0 @@ -# cr16 testcase for tbitb -# mach: cr16 - - .include "testutils.inc" - - start - - .global tbitb -tbitb: - movw $0, r1 - lpr r1, psr - movw $_y, r1 - tbitb $0, 0(r1) - spr psr, r1 - cmpb $0x20, r1 - beq ok1 -not_ok: - fail - -ok1: - movw $0, r1 - lpr r1, psr - movd $_y, (r1,r0) - tbitb $1,0(r1,r0) - spr psr, r1 - cmpb $0x20, r1 - beq ok2 - br not_ok -ok2: - - pass - -_y: .word 0xf7 diff --git a/sim/testsuite/sim/cr16/tbitw.cgs b/sim/testsuite/sim/cr16/tbitw.cgs deleted file mode 100644 index 018c73e..0000000 --- a/sim/testsuite/sim/cr16/tbitw.cgs +++ /dev/null @@ -1,33 +0,0 @@ -# cr16 testcase for tbitw -# mach: cr16 - - .include "testutils.inc" - - start - - .global tbitw -tbitw: - movw $0, r1 - lpr r1, psr - tbitw $0,_y - spr psr, r1 - cmpb $0x20, r1 - beq ok1 -not_ok: - fail - -ok1: - movw $0, r1 - lpr r1, psr - movd $_y, (r1,r0) - tbitw $1,0(r1,r0) - loadw _y, r1 - spr psr, r1 - cmpb $0x20, r1 - beq ok2 - br not_ok -ok2: - - pass - -_y: .word 0xf7 diff --git a/sim/testsuite/sim/cr16/testutils.inc b/sim/testsuite/sim/cr16/testutils.inc deleted file mode 100644 index 1b82dc6..0000000 --- a/sim/testsuite/sim/cr16/testutils.inc +++ /dev/null @@ -1,74 +0,0 @@ -# r0-r5 are used as tmps, consider them call clobbered by these macros. - - .macro START - .data -failmsg: - .ascii "fail\n" -passmsg: - .ascii "pass\n" - .text - .global _START -_START: - .global _start -_start: - .endm - - .macro exit rc - movw $\rc,r2 - movw $0x410,r0 - excp 8 - .endm - - .macro pass - movw $1, r2 - movd $passmsg,(r4,r3) - movw $5, r5 - movw $0x404, r0 - excp 8 - exit 0 - .endm - - .macro fail - movw $1, r2 - movd $failmsg,(r4,r3) - movw $5, r5 - movw $0x404, r0 - excp 8 - exit 1 - .endm - -# Other macros know this only clobbers r0. - .macro test_h_gr reg, val - movw $\val,r0 - cmpw \reg, r0 - beq test_gr - fail -test_gr: - .endm - - .macro test_h_grp regp, val - movd $\val,(r1,r0) - cmpd \regp,(r1,r0) - beq test_grp - fail -test_grp: - .endm - - - .macro mvi_h_condbit val - movw $0, r0 - movw $\val, r1 - cmpw r0, r1 - .endm - - .macro test_h_condbit val - .if \val - br test_c1 - fail -test_c1: - .else - br test_c0 - fail -test_c0: - .endif - .endm diff --git a/sim/testsuite/sim/cr16/uread16.ms b/sim/testsuite/sim/cr16/uread16.ms deleted file mode 100644 index 54253b4..0000000 --- a/sim/testsuite/sim/cr16/uread16.ms +++ /dev/null @@ -1,17 +0,0 @@ -# mach: cr16 - - .include "testutils.inc" - - start - - .global read16 -read16: - loadw foo,r1 - cmpw $42, r1 - beq ok - fail -ok: - pass - -foo: - .word 42 diff --git a/sim/testsuite/sim/cr16/uread32.ms b/sim/testsuite/sim/cr16/uread32.ms deleted file mode 100644 index c2181e5..0000000 --- a/sim/testsuite/sim/cr16/uread32.ms +++ /dev/null @@ -1,17 +0,0 @@ -# mach: cr16 - - .include "testutils.inc" - - start - - .global read32 -read32: - loadd foo, (r1,r0) - cmpd $0x12345678, (r1,r0) - beq ok - fail -ok: - pass - -foo: - .long 0x12345678 diff --git a/sim/testsuite/sim/cr16/xorb.cgs b/sim/testsuite/sim/cr16/xorb.cgs deleted file mode 100644 index 4ee4b2d..0000000 --- a/sim/testsuite/sim/cr16/xorb.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for xor $dr,$sr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global xor -xor: - movb $3, r4 - movb $6, r5 - - xorb r4,r5 - - test_h_gr r5, 5 - - pass diff --git a/sim/testsuite/sim/cr16/xord.cgs b/sim/testsuite/sim/cr16/xord.cgs deleted file mode 100644 index 3bbcac0..0000000 --- a/sim/testsuite/sim/cr16/xord.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for xor $dr,$sr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global xor -xor: - movd $0x33333333, (r4,r3) - movd $0x66666666, (r6,r5) - - xord (r4,r3), (r6,r5) - - test_h_grp "(r6,r5)", 0x55555555 - - pass diff --git a/sim/testsuite/sim/cr16/xorw.cgs b/sim/testsuite/sim/cr16/xorw.cgs deleted file mode 100644 index d82faa3..0000000 --- a/sim/testsuite/sim/cr16/xorw.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# cr16 testcase for xor $dr,$sr -# mach(): cr16 - - .include "testutils.inc" - - start - - .global xor -xor: - movw $3, r4 - movw $6, r5 - - xorw r4, r5 - - test_h_gr r5, 5 - - pass diff --git a/sim/testsuite/sim/cris/ChangeLog b/sim/testsuite/sim/cris/ChangeLog deleted file mode 100644 index 16c7c27..0000000 --- a/sim/testsuite/sim/cris/ChangeLog +++ /dev/null @@ -1,204 +0,0 @@ -2021-01-15 Mike Frysinger - - * c/c.exp: Change sim_run return to return_code. Set status to - pass/fail based on return_code. - * hw/rv-n-cris/rvc.exp (sim_has_rv_and_cris): Compare return_code - to 0. - -2021-01-09 Mike Frysinger - - * readlink4.c (main): Change rindex to strrchr. - -2021-01-07 Mike Frysinger - - PR ld/13900 - * c/helloaout.c: Disable test - -2021-01-07 Mike Frysinger - - * c/c.exp [cris*-*-elf] (CFLAGS_FOR_TARGET): Add -sim. - -2021-01-07 Mike Frysinger - - * c/kill2.c: Include unistd.h. - * c/pipe1.c, c/sched1.c, c/sched2.c, c/sched3.c, c/sched4.c, - c/sig5.c, c/sig8.c: Likewise. - * c/openpf1.c (main): Change close to fclose. - * c/openpf2.c: Likewise. - -2016-01-04 Mike Frysinger - - * asm/opterr1.ms: Update expected output. - * asm/opterr2.ms: Likewise. - -2015-12-25 Mike Frysinger - - * asm/io1.ms: Update expected output. - -2015-12-25 Mike Frysinger - - * hw/rv-n-cris/rvc.exp (rvdummy): Set up sane default. - -2012-03-24 Mike Frysinger - - * c/clone5.c: Update output to ignore decoded signal string. - * c/fcntl1.c, c/kill2.c, c/kill3.c, c/mprotect1.c, c/pipe5.c, - c/readlink5.c, c/rtsigprocmask1.c, c/rtsigsuspend1.c, c/sig10.c, - c/sig11.c, c/sig3.c, c/sig4.c, c/sig5.c, c/sig6.c, c/sig7.c, - c/sig8.c, c/sigreturn1.c, c/sigreturn2.c, c/syscall1.c, - c/syscall2.c, c/syscall3.c, c/syscall4.c, c/sysctl2.c: Likewise. - -2012-03-21 Mike Frysinger - - * asm/addqpc.ms: Update output to ignore decoded signal string. - * asm/boundmv32.ms, asm/fidxd.ms, asm/fidxi.ms, asm/ftagd.ms, - asm/ftagi.ms, asm/halt.ms, asm/io6.ms, asm/io7.ms, asm/io8.ms, - asm/io9.ms, asm/movecpc.ms, asm/movempc.ms, asm/movepcb.ms, - asm/movepcd.ms, asm/movepcw.ms, asm/moveqpc.ms, asm/moverbpc.ms, - asm/moverdpc.ms, asm/moverpcb.ms, asm/moverpcw.ms, asm/moverwpc.ms, - asm/movppc.ms, asm/movrss.ms, asm/movscpc.ms, asm/movsmpc.ms, - asm/movsrpc.ms, asm/movssr.ms, asm/movucpc.ms, asm/movumpc.ms, - asm/movurpc.ms, asm/msteppc1.ms, asm/msteppc2.ms, asm/msteppc3.ms, - asm/rfg.ms, asm/sbfs.ms, asm/subqpc.ms: Likewise. - -2010-10-07 Hans-Peter Nilsson - - * c/seek3.c, c/seek4.c: New tests. - -2010-08-24 Hans-Peter Nilsson - - * asm/nonvcv32.ms: Neutralize changed &&-in-macro gas syntax. - -2009-01-18 Hans-Peter Nilsson - - * asm/opterr5.ms, asm/opterr4.ms, - asm/opterr3.ms, asm/bare3.ms: New tests. - -2009-01-06 Hans-Peter Nilsson - - * c/mmap5.c, c/mmap6.c, c/mmap7.c, - c/mmap8.c, c/hellodyn3.c: New tests. - -2009-01-03 Hans-Peter Nilsson - - * c/settls1.c: New test. - * c/exitg1.c, c/exitg2.c: New tests. - * c/uname1.c: New test. - * c/mmap1.c (MMAP_FLAGS): Default-define to - MAP_PRIVATE and use this macro in the mmap call. - * c/mmap4.c: New test. - * c/access1.c: New test. - * asm/pid1.ms: New test. - -2008-12-30 Hans-Peter Nilsson - - * asm/badarch1.ms: Tweak error message match. - - * asm/badarch1.ms, c/badldso1.c, - c/badldso2.c, c/badldso3.c, - c/helloaout.c, c/hellodyn.c, - c/hellodyn2.c, c/writev1.c, - c/writev2.c: New tests. - * c/c.exp: If compiler links libc.so when attempting to - link dynamically, create symlink named "lib" to the directory - where it is found. Handle new test-case option "dynamic". - - * asm/opterr1.ms, asm/opterr2.ms: Adjust for - differences in getopt_long error message quoting. - -2007-11-08 Hans-Peter Nilsson - - * asm/x0-v10.ms, asm/x0-v32.ms: Tweak - stack-pointer match pattern for 4K host environment. - -2007-10-22 Edgar E. Iglesias - Hans-Peter Nilsson - - * asm/testutils.inc (test_move_cc): Add missing call to - test_cc. - * asm/asr.ms: Correct expected condition code flags. - * asm/boundr.ms: Ditto. - * asm/dstep.ms: Ditto. - * asm/lsr.ms: Ditto. - * asm/movecr.ms: Ditto. - * asm/mover.ms: Ditto. - * asm/neg.ms: Ditto. Use test_cc, not test_move_cc. - * asm/op3.ms: Check the condition code flags after the insn - under test. - * asm/movecrt10.ms: Update expected number of simulated - cycles. - * asm/movecrt32.ms: Ditto. - * asm/jsr.ms: Don't use local label 8. - * asm/nonvcv32.ms: New test. - -2007-10-11 Jesper Nilsson - - * c/freopen2.c: Added testcase. - -2006-10-02 Hans-Peter Nilsson - Edgar E. Iglesias - - * c/clone5.c, c/mprotect1.c, - c/rtsigprocmask1.c, c/rtsigsuspend1.c, - c/sig7.c, c/sigreturn1.c, - c/sigreturn2.c, c/syscall1.c, - c/syscall2.c, c/sysctl2.c, c/fcntl1.c, - c/readlink2.c: Add code to print ENOSYS if syscall being - tested returns ENOSYS. Add early exit where needed. Change any - existing code to print "xyzzy", not "pass". - * asm/option3.ms, asm/option4.ms, - c/clone6.c, c/fcntl2.c, - c/mprotect2.c, c/readlink11.c, - c/rtsigprocmask2.c, c/rtsigsuspend2.c, - c/sig13.c, c/sigreturn3.c, - c/sigreturn4.c, c/syscall3.c, - c/syscall4.c, c/syscall5.c, - c/syscall6.c, c/syscall7.c, - c/syscall8.c, c/sysctl3.c: New tests. - -2006-09-30 Hans-Peter Nilsson - - * c/pipe2.c: Adjust expected output. - (process): Don't write as much to the pipe as to trig the - inordinate-amount test in the sim pipe machinery. Correct test of - write return-value; check only that pipemax bytes were - successfully written. For error-case, emit strerror as well. - (main): Add a second read. - -2006-04-08 Hans-Peter Nilsson - - * hw/rv-n-cris/irq6.ms: New test. - -2006-04-03 Hans-Peter Nilsson - - * hw: New directory for subdirectories with tests. - * hw/rv-n-cris: New directory with tests. - -2006-04-02 Hans-Peter Nilsson - - * asm/testutils.inc (test_h_mem): Use register prefix. - (testr_h_dr, test_h_dr, ldmem_h_gr, mvr_h_mem): Ditto. Correct - syntax. - - * asm/x0-v10.ms, asm/x0-v32.ms: Widen regexp for - stack pointer values. - -2006-02-23 Hans-Peter Nilsson - - * c/time2.c: New test. - -2006-01-10 Hans-Peter Nilsson - - * asm/x1-v10.ms, asm/x3-v10.ms, - asm/x7-v10.ms: Update expected cycle output. - -2005-12-06 Hans-Peter Nilsson - - * asm/movmp8.ms, asm/pcplus.ms: New tests. - * asm/movmp.ms: Do not write to P0, P4 or P8. - * asm/raw13.ms: Write to MOF instead of WZ (P4). - -2005-11-21 Hans-Peter Nilsson - - * asm, c: New directory with C and assembly tests for the CRIS - simulator. diff --git a/sim/testsuite/sim/cris/asm/abs.ms b/sim/testsuite/sim/cris/asm/abs.ms deleted file mode 100644 index a428434..0000000 --- a/sim/testsuite/sim/cris/asm/abs.ms +++ /dev/null @@ -1,50 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1\n0\n80000000\n7fffffff\n2a\n1\nffff\n1f\n0\n - - .include "testutils.inc" - start - moveq -1,r3 - - abs r3,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - moveq 0,r3 - dumpr3 ; 0 - - move.d 0x80000000,r4 - abs r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 80000000 - - move.d 0x7fffffff,r4 - abs r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 7fffffff - - move.d 42,r3 - abs r3,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2a - - moveq 1,r6 - abs r6,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - move.d 0xffff,r3 - abs r3,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq -31,r5 - abs r5,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1f - - moveq 0,r5 - abs r5,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/addc.ms b/sim/testsuite/sim/cris/asm/addc.ms deleted file mode 100644 index 8b7fa72..0000000 --- a/sim/testsuite/sim/cris/asm/addc.ms +++ /dev/null @@ -1,81 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n - - .include "testutils.inc" - start - moveq -1,r3 - add.d 2,r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - moveq 2,r3 - add.d -1,r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - move.d 0xffff,r3 - add.d 0xffff,r3 - test_cc 0 0 0 0 - dumpr3 ; 1fffe - - moveq -1,r3 - add.d -1,r3 - test_cc 1 0 0 1 - dumpr3 ; fffffffe - - move.d 0x78134452,r3 - add.d 0x5432f789,r3 - test_cc 1 0 1 0 - dumpr3 ; cc463bdb - - moveq -1,r3 - add.w 2,r3 - test_cc 0 0 0 1 - dumpr3 ; ffff0001 - - moveq 2,r3 - add.w -1,r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - move.d 0xffff,r3 - add.w 0xffff,r3 - test_cc 1 0 0 1 - dumpr3 ; fffe - - move.d 0xfedaffff,r3 - add.w 0xffff,r3 - test_cc 1 0 0 1 - dumpr3 ; fedafffe - - move.d 0x78134452,r3 - add.w 0xf789,r3 - test_cc 0 0 0 1 - dumpr3 ; 78133bdb - - moveq -1,r3 - add.b 2,r3 - test_cc 0 0 0 1 - dumpr3 ; ffffff01 - - moveq 2,r3 - add.b -1,r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - move.d 0xff,r3 - add.b 0xff,r3 - test_cc 1 0 0 1 - dumpr3 ; fe - - move.d 0xfeda49ff,r3 - add.b 0xff,r3 - test_cc 1 0 0 1 - dumpr3 ; feda49fe - - move.d 0x78134452,r3 - add.b 0x89,r3 - test_cc 1 0 0 0 - dumpr3 ; 781344db - - quit diff --git a/sim/testsuite/sim/cris/asm/addcpc.ms b/sim/testsuite/sim/cris/asm/addcpc.ms deleted file mode 100644 index 0302fa2..0000000 --- a/sim/testsuite/sim/cris/asm/addcpc.ms +++ /dev/null @@ -1,35 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# output: 2f\n31\n - -# Test that the special case add.d const,pc works. - - .include "testutils.inc" - start -x: - add.d y-y0,pc -y0: - quit - - .space 1000 - quit - quit - quit - quit - quit -z: - move.d 49,r3 - dumpr3 - quit - - .space 1000 - quit - quit - quit - quit - quit -y: - move.d 47,r3 - dumpr3 - add.d z-z0,pc -z0: - quit diff --git a/sim/testsuite/sim/cris/asm/addcv32c.ms b/sim/testsuite/sim/cris/asm/addcv32c.ms deleted file mode 100644 index 0264fae..0000000 --- a/sim/testsuite/sim/cris/asm/addcv32c.ms +++ /dev/null @@ -1,50 +0,0 @@ -# mach: crisv32 -# output: 0\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n - - .include "testutils.inc" - start - clearf cz - moveq 0,r3 - addc 0,r3 - test_cc 0 0 0 0 - dumpr3 ; 0 - - setf z - moveq 0,r3 - addc 0,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - setf cz - moveq 0,r3 - addc 0,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - clearf c - moveq -1,r3 - addc 2,r3 - test_cc 0 0 0 1 - dumpr3 ; 1+c - - moveq 2,r3 - addc -1,r3 - test_cc 0 0 0 1 - dumpr3 ; 2+c - - move.d 0xffff,r3 - addc 0xffff,r3 - test_cc 0 0 0 0 - dumpr3 ; 1ffff - - moveq -1,r3 - addc -1,r3 - test_cc 1 0 0 1 - dumpr3 ; fffffffe+c - - move.d 0x78134452,r3 - addc 0x5432f789,r3 - test_cc 1 0 1 0 - dumpr3 ; cc463bdc - - quit diff --git a/sim/testsuite/sim/cris/asm/addcv32m.ms b/sim/testsuite/sim/cris/asm/addcv32m.ms deleted file mode 100644 index 13139b2..0000000 --- a/sim/testsuite/sim/cris/asm/addcv32m.ms +++ /dev/null @@ -1,69 +0,0 @@ -# mach: crisv32 -# output: 0\n0\n1\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n - - .include "testutils.inc" - .data -x: - .dword 0,0,2,-1,0xffff,-1,0x5432f789 - - start - move.d x,r5 - clearf cz - moveq 0,r3 - addc [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; 0 - - setf z - moveq 0,r3 - addc [r5],r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - setf c - moveq 0,r3 - addc [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - clearf c - moveq 0,r3 - addc [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; 0 - - setf c - moveq 0,r3 - addc [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - clearf c - moveq -1,r3 - addc [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 1+c - - moveq 2,r3 - addc [r5],r3 - moveq 4,r6 - addi r6.b,r5 - test_cc 0 0 0 1 - dumpr3 ; 2+c - - move.d 0xffff,r3 - addc [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; 1ffff - - moveq -1,r3 - addc [r5+],r3 - test_cc 1 0 0 1 - dumpr3 ; fffffffe+c - - move.d 0x78134452,r3 - addc [r5+],r3 - test_cc 1 0 1 0 - dumpr3 ; cc463bdc - - quit diff --git a/sim/testsuite/sim/cris/asm/addcv32r.ms b/sim/testsuite/sim/cris/asm/addcv32r.ms deleted file mode 100644 index 20aeb12..0000000 --- a/sim/testsuite/sim/cris/asm/addcv32r.ms +++ /dev/null @@ -1,57 +0,0 @@ -# mach: crisv32 -# output: 0\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n - - .include "testutils.inc" - start - clearf cz - moveq 0,r3 - moveq 0,r4 - addc r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 0 - - setf z - moveq 0,r3 - moveq 0,r4 - addc r4,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - setf cz - moveq 0,r3 - moveq 0,r4 - addc r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - moveq -1,r3 - moveq 2,r4 - addc r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 1+c - - moveq 2,r3 - moveq -1,r4 - addc r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 2+c - - move.d 0xffff,r4 - move.d r4,r3 - addc r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1ffff - - moveq -1,r4 - move.d r4,r3 - addc r4,r3 - test_cc 1 0 0 1 - dumpr3 ; fffffffe+c - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - addc r4,r3 - test_cc 1 0 1 0 - dumpr3 ; cc463bdc - - quit diff --git a/sim/testsuite/sim/cris/asm/addi.ms b/sim/testsuite/sim/cris/asm/addi.ms deleted file mode 100644 index 2fa2723..0000000 --- a/sim/testsuite/sim/cris/asm/addi.ms +++ /dev/null @@ -1,57 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 0\n1\n2\n4\nbe02460f\n69d035a6\nc16c14d4\n - - .include "testutils.inc" - start - moveq 0,r3 - moveq 0,r4 - clearf zcvn - addi r4.b,r3 - test_cc 0 0 0 0 - dumpr3 ; 0 - - moveq 0,r3 - moveq 1,r4 - setf zcvn - addi r4.b,r3 - test_cc 1 1 1 1 - dumpr3 ; 1 - - moveq 0,r3 - moveq 1,r4 - setf cv - clearf zn - addi r4.w,r3 - test_cc 0 0 1 1 - dumpr3 ; 2 - - moveq 0,r3 - moveq 1,r4 - clearf cv - setf zn - addi r4.d,r3 - test_cc 1 1 0 0 - dumpr3 ; 4 - - move.d 0x12345678,r3 - move.d 0xabcdef97,r4 - clearf cn - setf zv - addi r4.b,r3 - test_cc 0 1 1 0 - dumpr3 ; be02460f - - move.d 0x12345678,r3 - move.d 0xabcdef97,r4 - setf cn - clearf zv - addi r4.w,r3 - test_cc 1 0 0 1 - dumpr3 ; 69d035a6 - - move.d 0x12345678,r3 - move.d 0xabcdef97,r4 - addi r4.d,r3 - dumpr3 ; c16c14d4 - - quit diff --git a/sim/testsuite/sim/cris/asm/addiv32.ms b/sim/testsuite/sim/cris/asm/addiv32.ms deleted file mode 100644 index 8040afc..0000000 --- a/sim/testsuite/sim/cris/asm/addiv32.ms +++ /dev/null @@ -1,62 +0,0 @@ -# mach: crisv32 -# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n - - .include "testutils.inc" - .data -x: - .dword 0x55aa77ff - .dword 0xccff2244 - .dword 0x88ccee19 - - start - setf cv - moveq -1,r0 - move.d x-32768,r5 - move.d 32769,r6 - addi r6.b,r5,acr - test_cc 0 0 1 1 - move.d [acr],r3 - dumpr3 ; 4455aa77 - - addu.w 32771,r5 - setf znvc - moveq -1,r8 - addi r8.w,r5,acr - test_cc 1 1 1 1 - move.d [acr],r3 - dumpr3 ; 4455aa77 - - moveq 5,r10 - clearf znvc - addi r10.b,acr,acr - test_cc 0 0 0 0 - move.d [acr],r3 - dumpr3 ; ee19ccff - - subq 1,r5 - move.d r5,r8 - subq 1,r8 - moveq 1,r9 - addi r9.d,r8,acr - test_cc 0 0 0 0 - movu.w [acr],r3 - dumpr3 ; ff22 - - moveq -2,r11 - addi r11.w,acr,acr - move.d [acr],r3 - dumpr3 ; 4455aa77 - - moveq 5,r9 - addi r9.d,acr,acr - subq 18,acr - move.d [acr],r3 - dumpr3 ; ff224455 - - move.d -76789888/4,r12 - addi r12.d,r5,acr - add.d 76789886,acr - move.d [acr],r3 - dumpr3 ; 55aa77ff - - quit diff --git a/sim/testsuite/sim/cris/asm/addm.ms b/sim/testsuite/sim/cris/asm/addm.ms deleted file mode 100644 index c214e3a..0000000 --- a/sim/testsuite/sim/cris/asm/addm.ms +++ /dev/null @@ -1,96 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n781344d0\n - - .include "testutils.inc" - .data -x: - .dword 2,-1,0xffff,-1,0x5432f789 - .word 2,-1,0xffff,0xf789 - .byte 2,0xff,0x89 - .byte 0x7e - - start - moveq -1,r3 - move.d x,r5 - add.d [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - moveq 2,r3 - add.d [r5],r3 - test_cc 0 0 0 1 - addq 4,r5 - dumpr3 ; 1 - - move.d 0xffff,r3 - add.d [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; 1fffe - - moveq -1,r3 - add.d [r5+],r3 - test_cc 1 0 0 1 - dumpr3 ; fffffffe - - move.d 0x78134452,r3 - add.d [r5+],r3 - test_cc 1 0 1 0 - dumpr3 ; cc463bdb - - moveq -1,r3 - add.w [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; ffff0001 - - moveq 2,r3 - add.w [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - move.d 0xffff,r3 - add.w [r5],r3 - test_cc 1 0 0 1 - dumpr3 ; fffe - - move.d 0xfedaffff,r3 - add.w [r5+],r3 - test_cc 1 0 0 1 - dumpr3 ; fedafffe - - move.d 0x78134452,r3 - add.w [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 78133bdb - - moveq -1,r3 - add.b [r5],r3 - test_cc 0 0 0 1 - addq 1,r5 - dumpr3 ; ffffff01 - - moveq 2,r3 - add.b [r5],r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - move.d 0xff,r3 - add.b [r5],r3 - test_cc 1 0 0 1 - dumpr3 ; fe - - move.d 0xfeda49ff,r3 - add.b [r5+],r3 - test_cc 1 0 0 1 - dumpr3 ; feda49fe - - move.d 0x78134452,r3 - add.b [r5+],r3 - test_cc 1 0 0 0 - dumpr3 ; 781344db - - move.d 0x78134452,r3 - add.b [r5],r3 - test_cc 1 0 1 0 - dumpr3 ; 781344d0 - - quit diff --git a/sim/testsuite/sim/cris/asm/addoc.ms b/sim/testsuite/sim/cris/asm/addoc.ms deleted file mode 100644 index fe269d2..0000000 --- a/sim/testsuite/sim/cris/asm/addoc.ms +++ /dev/null @@ -1,44 +0,0 @@ -# mach: crisv32 -# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n - - .include "testutils.inc" - .data -x: - .dword 0x55aa77ff - .dword 0xccff2244 - .dword 0x88ccee19 - - start - moveq -1,r0 - move.d x-32768,r5 - addo.d 32769,r5,acr - move.d [acr],r3 - dumpr3 ; 4455aa77 - - addu.w 32770,r5 - addo.w -1,r5,acr - move.d [acr],r3 - dumpr3 ; 4455aa77 - - addo.d 5,acr,acr - move.d [acr],r3 - dumpr3 ; ee19ccff - - addo.b 3,r5,acr - movu.w [acr],r3 - dumpr3 ; ff22 - - addo.b -4,acr,acr - move.d [acr],r3 - dumpr3 ; 4455aa77 - - addo.w 2,acr,acr - move.d [acr],r3 - dumpr3 ; ff224455 - - addo.d -76789887,r5,acr - add.d 76789885,acr - move.d [acr],r3 - dumpr3 ; 55aa77ff - - quit diff --git a/sim/testsuite/sim/cris/asm/addom.ms b/sim/testsuite/sim/cris/asm/addom.ms deleted file mode 100644 index 4e4ebb1..0000000 --- a/sim/testsuite/sim/cris/asm/addom.ms +++ /dev/null @@ -1,55 +0,0 @@ -# mach: crisv32 -# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n - - .include "testutils.inc" - .data -x: - .dword 0x55aa77ff - .dword 0xccff2244 - .dword 0x88ccee19 -y: - .dword 32769 - .word -1 - .dword 5 - .byte 3,-4 - .word 2 - .dword -76789887 - - start - moveq -1,r0 - move.d x-32768,r5 - move.d y,r13 - addo.d [r13+],r5,acr - move.d [acr],r3 - dumpr3 ; 4455aa77 - - addu.w 32770,r5 - addo.w [r13+],r5,acr - move.d [acr],r3 - dumpr3 ; 4455aa77 - - addo.d [r13],acr,acr - addq 4,r13 - move.d [acr],r3 - dumpr3 ; ee19ccff - - addo.b [r13+],r5,acr - movu.w [acr],r3 - dumpr3 ; ff22 - - addo.b [r13],acr,acr - addq 1,r13 - move.d [acr],r3 - dumpr3 ; 4455aa77 - - addo.w [r13],acr,acr - addq 2,r13 - move.d [acr],r3 - dumpr3 ; ff224455 - - addo.d [r13+],r5,acr - add.d 76789885,acr - move.d [acr],r3 - dumpr3 ; 55aa77ff - - quit diff --git a/sim/testsuite/sim/cris/asm/addoq.ms b/sim/testsuite/sim/cris/asm/addoq.ms deleted file mode 100644 index f4b6083..0000000 --- a/sim/testsuite/sim/cris/asm/addoq.ms +++ /dev/null @@ -1,31 +0,0 @@ -# mach: crisv32 -# output: ccff2244\n88ccee19\n55aa77ff\n19cc\n - - .include "testutils.inc" - .data -x: - .dword 0x55aa77ff - .dword 0xccff2244 - .dword 0x88ccee19 - start - moveq -1,r0 - move.d x+4,r5 - setf zvnc - addoq 0,r5,acr - test_cc 1 1 1 1 - move.d [acr],r3 - dumpr3 ; ccff2244 - setf zvnc - addoq 4,r5,acr - test_cc 1 1 1 1 - move.d [acr],r3 - dumpr3 ; 88ccee19 - clearf zvnc - addoq -8,acr,acr - test_cc 0 0 0 0 - move.d [acr],r3 - dumpr3 ; 55aa77ff - addoq 3,r5,acr - movu.w [acr],r3 - dumpr3 ; 19cc - quit diff --git a/sim/testsuite/sim/cris/asm/addq.ms b/sim/testsuite/sim/cris/asm/addq.ms deleted file mode 100644 index 6a27ac5..0000000 --- a/sim/testsuite/sim/cris/asm/addq.ms +++ /dev/null @@ -1,47 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: ffffffff\n0\n1\n100\n10000\n47\n67\na6\n80000001\n - - .include "testutils.inc" - start - moveq -2,r3 - addq 1,r3 - test_cc 1 0 0 0 - dumpr3 - - addq 1,r3 - test_cc 0 1 0 1 - dumpr3 - - addq 1,r3 - test_cc 0 0 0 0 - dumpr3 - - move.d 0xff,r3 - addq 1,r3 - test_cc 0 0 0 0 - dumpr3 - - move.d 0xffff,r3 - addq 1,r3 - test_cc 0 0 0 0 - dumpr3 - - move.d 0x42,r3 - addq 5,r3 - test_cc 0 0 0 0 - dumpr3 - - addq 32,r3 - test_cc 0 0 0 0 - dumpr3 - - addq 63,r3 - test_cc 0 0 0 0 - dumpr3 - - move.d 0x7ffffffe,r3 - addq 3,r3 - test_cc 1 0 1 0 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/addqpc.ms b/sim/testsuite/sim/cris/asm/addqpc.ms deleted file mode 100644 index ba5a1ec..0000000 --- a/sim/testsuite/sim/cris/asm/addqpc.ms +++ /dev/null @@ -1,8 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - addq 1,pc - diff --git a/sim/testsuite/sim/cris/asm/addr.ms b/sim/testsuite/sim/cris/asm/addr.ms deleted file mode 100644 index c1b9348..0000000 --- a/sim/testsuite/sim/cris/asm/addr.ms +++ /dev/null @@ -1,96 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n - - .include "testutils.inc" - start - moveq -1,r3 - moveq 2,r4 - add.d r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - moveq 2,r3 - moveq -1,r4 - add.d r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - move.d 0xffff,r4 - move.d r4,r3 - add.d r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1fffe - - moveq -1,r4 - move.d r4,r3 - add.d r4,r3 - test_cc 1 0 0 1 - dumpr3 ; fffffffe - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - add.d r4,r3 - test_cc 1 0 1 0 - dumpr3 ; cc463bdb - - moveq -1,r3 - moveq 2,r4 - add.w r4,r3 - test_cc 0 0 0 1 - dumpr3 ; ffff0001 - - moveq 2,r3 - moveq -1,r4 - add.w r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - move.d 0xffff,r4 - move.d r4,r3 - add.w r4,r3 - test_cc 1 0 0 1 - dumpr3 ; fffe - - move.d 0xfedaffff,r4 - move.d r4,r3 - add.w r4,r3 - test_cc 1 0 0 1 - dumpr3 ; fedafffe - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - add.w r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 78133bdb - - moveq -1,r3 - moveq 2,r4 - add.b r4,r3 - test_cc 0 0 0 1 - dumpr3 ; ffffff01 - - moveq 2,r3 - moveq -1,r4 - add.b r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - move.d 0xff,r4 - move.d r4,r3 - add.b r4,r3 - test_cc 1 0 0 1 - dumpr3 ; fe - - move.d 0xfeda49ff,r4 - move.d r4,r3 - add.b r4,r3 - test_cc 1 0 0 1 - dumpr3 ; feda49fe - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - add.b r4,r3 - test_cc 1 0 0 0 - dumpr3 ; 781344db - - quit diff --git a/sim/testsuite/sim/cris/asm/addswpc.ms b/sim/testsuite/sim/cris/asm/addswpc.ms deleted file mode 100644 index a7ac754..0000000 --- a/sim/testsuite/sim/cris/asm/addswpc.ms +++ /dev/null @@ -1,61 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# output: 7\n - -# Test that the special case adds.w [pc+rN.w],pc works. - - .include "testutils.inc" - start -x: - moveq 0,r3 - ba xy - moveq 5,r2 - -ok: - moveq 7,r3 - dumpr3 - quit - -xy: - adds.w [pc+r2.w],pc -y: - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word ok-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y - .word x0-y -x0: - quit diff --git a/sim/testsuite/sim/cris/asm/addxc.ms b/sim/testsuite/sim/cris/asm/addxc.ms deleted file mode 100644 index 0e346df..0000000 --- a/sim/testsuite/sim/cris/asm/addxc.ms +++ /dev/null @@ -1,91 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n - - .include "testutils.inc" - start - moveq 2,r3 - adds.b 0xff,r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - moveq 2,r3 - adds.w 0xffff,r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - moveq 2,r3 - addu.b 0xff,r3 - dumpr3 ; 101 - - moveq 2,r3 - move.d 0xffffffff,r4 - addu.w -1,r3 - test_cc 0 0 0 0 - dumpr3 ; 10001 - - move.d 0xffff,r3 - addu.b -1,r3 - test_cc 0 0 0 0 - dumpr3 ; 100fe - - move.d 0xffff,r3 - addu.w -1,r3 - test_cc 0 0 0 0 - dumpr3 ; 1fffe - - move.d 0xffff,r3 - adds.b 0xff,r3 - test_cc 0 0 0 1 - dumpr3 ; fffe - - move.d 0xffff,r3 - adds.w 0xffff,r3 - test_cc 0 0 0 1 - dumpr3 ; fffe - - moveq -1,r3 - adds.b 0xff,r3 - test_cc 1 0 0 1 - dumpr3 ; fffffffe - - moveq -1,r3 - adds.w 0xff,r3 - test_cc 0 0 0 1 - dumpr3 ; fe - - moveq -1,r3 - adds.w 0xffff,r3 - test_cc 1 0 0 1 - dumpr3 ; fffffffe - - move.d 0x78134452,r3 - addu.b 0x89,r3 - test_cc 0 0 0 0 - dumpr3 ; 781344db - - move.d 0x78134452,r3 - adds.b 0x89,r3 - test_cc 0 0 0 1 - dumpr3 ; 781343db - - move.d 0x78134452,r3 - addu.w 0xf789,r3 - test_cc 0 0 0 0 - dumpr3 ; 78143bdb - - move.d 0x78134452,r3 - adds.w 0xf789,r3 - test_cc 0 0 0 1 - dumpr3 ; 78133bdb - - move.d 0x7fffffee,r3 - addu.b 0xff,r3 - test_cc 1 0 1 0 - dumpr3 ; 800000ed - - move.d 0x1,r3 - adds.w 0xffff,r3 - test_cc 0 1 0 1 - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/addxm.ms b/sim/testsuite/sim/cris/asm/addxm.ms deleted file mode 100644 index 40ae9aa..0000000 --- a/sim/testsuite/sim/cris/asm/addxm.ms +++ /dev/null @@ -1,106 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n - - .include "testutils.inc" - .data -x: - .byte 0xff - .word 0xffff - .word 0xff - .word 0xffff - .byte 0x89 - .word 0xf789 - .byte 0xff - .word 0xffff - - start - moveq 2,r3 - move.d x,r5 - adds.b [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - moveq 2,r3 - adds.w [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - moveq 2,r3 - subq 3,r5 - addu.b [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; 101 - - moveq 2,r3 - addu.w [r5+],r3 - subq 3,r5 - test_cc 0 0 0 0 - dumpr3 ; 10001 - - move.d 0xffff,r3 - addu.b [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; 100fe - - move.d 0xffff,r3 - addu.w [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; 1fffe - - move.d 0xffff,r3 - adds.b [r5],r3 - test_cc 0 0 0 1 - dumpr3 ; fffe - - move.d 0xffff,r3 - adds.w [r5],r3 - test_cc 0 0 0 1 - dumpr3 ; fffe - - moveq -1,r3 - adds.b [r5],r3 - test_cc 1 0 0 1 - addq 3,r5 - dumpr3 ; fffffffe - - moveq -1,r3 - adds.w [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; fe - - moveq -1,r3 - adds.w [r5+],r3 - test_cc 1 0 0 1 - dumpr3 ; fffffffe - - move.d 0x78134452,r3 - addu.b [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; 781344db - - move.d 0x78134452,r3 - adds.b [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 781343db - - move.d 0x78134452,r3 - addu.w [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; 78143bdb - - move.d 0x78134452,r3 - adds.w [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 78133bdb - - move.d 0x7fffffee,r3 - addu.b [r5+],r3 - test_cc 1 0 1 0 - dumpr3 ; 800000ed - - move.d 0x1,r3 - adds.w [r5+],r3 - test_cc 0 1 0 1 - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/addxr.ms b/sim/testsuite/sim/cris/asm/addxr.ms deleted file mode 100644 index 8234ac3..0000000 --- a/sim/testsuite/sim/cris/asm/addxr.ms +++ /dev/null @@ -1,93 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n - - .include "testutils.inc" - start - moveq 2,r3 - move.d 0xff,r4 - adds.b r4,r3 - dumpr3 ; 1 - - moveq 2,r3 - move.d 0xffff,r4 - adds.w r4,r3 - dumpr3 ; 1 - - moveq 2,r3 - move.d 0xffff,r4 - addu.b r4,r3 - dumpr3 ; 101 - - moveq 2,r3 - move.d 0xffffffff,r4 - addu.w r4,r3 - dumpr3 ; 10001 - - move.d 0xffff,r3 - move.d 0xffffffff,r4 - addu.b r4,r3 - dumpr3 ; 100fe - - move.d 0xffff,r3 - move.d 0xffffffff,r4 - addu.w r4,r3 - dumpr3 ; 1fffe - - move.d 0xffff,r3 - move.d 0xff,r4 - adds.b r4,r3 - dumpr3 ; fffe - - move.d 0xffff,r4 - move.d r4,r3 - adds.w r4,r3 - dumpr3 ; fffe - - moveq -1,r3 - move.d 0xff,r4 - adds.b r4,r3 - dumpr3 ; fffffffe - - moveq -1,r3 - move.d 0xff,r4 - adds.w r4,r3 - dumpr3 ; fe - - moveq -1,r3 - move.d 0xffff,r4 - adds.w r4,r3 - dumpr3 ; fffffffe - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - addu.b r4,r3 - dumpr3 ; 781344db - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - adds.b r4,r3 - dumpr3 ; 781343db - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - addu.w r4,r3 - dumpr3 ; 78143bdb - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - adds.w r4,r3 - dumpr3 ; 78133bdb - - move.d 0x7fffffee,r3 - move.d 0xff,r4 - addu.b r4,r3 - test_cc 1 0 1 0 - dumpr3 ; 800000ed - - move.d 0x1,r3 - move.d 0xffff,r4 - adds.w r4,r3 - test_cc 0 1 0 1 - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/andc.ms b/sim/testsuite/sim/cris/asm/andc.ms deleted file mode 100644 index e800a0a..0000000 --- a/sim/testsuite/sim/cris/asm/andc.ms +++ /dev/null @@ -1,80 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n - - .include "testutils.inc" - start - moveq -1,r3 - and.d 2,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq 2,r3 - and.d -1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xffff,r3 - and.d 0xffff,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq -1,r3 - and.d -1,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x78134452,r3 - and.d 0x5432f789,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 50124400 - - moveq -1,r3 - and.w 2,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff0002 - - moveq 2,r3 - and.w -1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xfffff,r3 - and.w 0xffff,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fffff - - move.d 0xfedaffaf,r3 - and.w 0xff5f,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fedaff0f - - move.d 0x78134452,r3 - and.w 0xf789,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 78134400 - - moveq -1,r3 - and.b 2,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffffff02 - - moveq 2,r3 - and.b -1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xfa7,r3 - and.b 0x5a,r3 - test_move_cc 0 0 0 0 - dumpr3 ; f02 - - move.d 0x78134453,r3 - and.b 0x89,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 78134401 - - and.b 0,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 78134400 - - quit diff --git a/sim/testsuite/sim/cris/asm/andm.ms b/sim/testsuite/sim/cris/asm/andm.ms deleted file mode 100644 index 4e1a34b..0000000 --- a/sim/testsuite/sim/cris/asm/andm.ms +++ /dev/null @@ -1,90 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n - - .include "testutils.inc" - .data -x: - .dword 2,-1,0xffff,-1,0x5432f789 - .word 2,-1,0xffff,0xff5f,0xf789 - .byte 2,-1,0x5a,0x89,0 - - start - moveq -1,r3 - move.d x,r5 - and.d [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq 2,r3 - and.d [r5],r3 - test_move_cc 0 0 0 0 - addq 4,r5 - dumpr3 ; 2 - - move.d 0xffff,r3 - and.d [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq -1,r3 - and.d [r5+],r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x78134452,r3 - and.d [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 50124400 - - moveq -1,r3 - and.w [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff0002 - - moveq 2,r3 - and.w [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xfffff,r3 - and.w [r5],r3 - test_move_cc 1 0 0 0 - addq 2,r5 - dumpr3 ; fffff - - move.d 0xfedaffaf,r3 - and.w [r5+],r3 - test_move_cc 1 0 0 0 - dumpr3 ; fedaff0f - - move.d 0x78134452,r3 - and.w [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 78134400 - - moveq -1,r3 - and.b [r5],r3 - test_move_cc 0 0 0 0 - addq 1,r5 - dumpr3 ; ffffff02 - - moveq 2,r3 - and.b [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xfa7,r3 - and.b [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; f02 - - move.d 0x78134453,r3 - and.b [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 78134401 - - and.b [r5],r3 - test_move_cc 0 1 0 0 - dumpr3 ; 78134400 - - quit diff --git a/sim/testsuite/sim/cris/asm/andq.ms b/sim/testsuite/sim/cris/asm/andq.ms deleted file mode 100644 index e515b3e..0000000 --- a/sim/testsuite/sim/cris/asm/andq.ms +++ /dev/null @@ -1,46 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 2\n2\nffff\nffffffff\n1f\nffffffe0\n78134452\n0\n - - .include "testutils.inc" - start - moveq -1,r3 - andq 2,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq 2,r3 - andq -1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xffff,r3 - andq -1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq -1,r3 - andq -1,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - andq 31,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1f - - moveq -1,r3 - andq -32,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffe0 - - move.d 0x78134457,r3 - andq -14,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 78134452 - - moveq 0,r3 - andq -14,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/andr.ms b/sim/testsuite/sim/cris/asm/andr.ms deleted file mode 100644 index f5d90e2..0000000 --- a/sim/testsuite/sim/cris/asm/andr.ms +++ /dev/null @@ -1,95 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n - - .include "testutils.inc" - start - moveq -1,r3 - moveq 2,r4 - and.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq 2,r3 - moveq -1,r4 - and.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xffff,r4 - move.d r4,r3 - and.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq -1,r4 - move.d r4,r3 - and.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - and.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 50124400 - - moveq -1,r3 - moveq 2,r4 - and.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff0002 - - moveq 2,r3 - moveq -1,r4 - and.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xfffff,r3 - move.d 0xffff,r4 - and.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fffff - - move.d 0xfedaffaf,r3 - move.d 0xff5f,r4 - and.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fedaff0f - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - and.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 78134400 - - moveq -1,r3 - moveq 2,r4 - and.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffffff02 - - moveq 2,r3 - moveq -1,r4 - and.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0x5a,r4 - move.d 0xfa7,r3 - and.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; f02 - - move.d 0x5432f789,r4 - move.d 0x78134453,r3 - and.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 78134401 - - moveq 0,r7 - and.b r7,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 78134400 - - quit diff --git a/sim/testsuite/sim/cris/asm/asm.exp b/sim/testsuite/sim/cris/asm/asm.exp deleted file mode 100644 index 415bbf1..0000000 --- a/sim/testsuite/sim/cris/asm/asm.exp +++ /dev/null @@ -1,45 +0,0 @@ -# Copyright (C) 2005-2021 Free Software Foundation, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -# Miscellaneous CRIS simulator testcases in assembly code. - -if [istarget cris*-*-*] { - global ASFLAGS_FOR_TARGET - # All machines we test and the corresponding assembler option. Needs - # update if we build the simulator for crisv0 crisv3 and crisv8 too. - - set combos {{"crisv10" "--march=v10 --no-mul-bug-abort"} - {"crisv32" "--march=v32"}} - - # We need to pass different assembler flags for each machine. - # Specifying it here rather than adding a specifier to each and every - # test-file is preferrable. - - foreach combo $combos { - set mach [lindex $combo 0] - set ASFLAGS_FOR_TARGET "[lindex $combo 1]" - - # The .ms suffix is for "miscellaneous .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $mach - } - } -} diff --git a/sim/testsuite/sim/cris/asm/asr.ms b/sim/testsuite/sim/cris/asm/asr.ms deleted file mode 100644 index 066bc73..0000000 --- a/sim/testsuite/sim/cris/asm/asr.ms +++ /dev/null @@ -1,228 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: ffffffff\n1\nffffffff\nffffffff\n5a67f\nffffffff\nffffffff\nffffffff\nf699fc67\nffffffff\n1\nffffffff\nffffffff\n5a67f\nda67ffff\nda67ffff\nda67ffff\nda67fc67\nffffffff\nffffffff\n1\nffffffff\nffffffff\n5a670007\nda67f1ff\nda67f1ff\nda67f1ff\nda67f1e7\nffffffff\nffffffff\n1\nffffffff\nffffffff\nffffffff\n5a67f1ff\n5a67f1f9\n0\n5a670000\n - - .include "testutils.inc" - start - moveq -1,r3 - asrq 0,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - asrq 1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - moveq -1,r3 - asrq 31,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - asrq 15,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x5a67f19f,r3 - asrq 12,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 5a67f - - move.d 0xda67f19f,r3 - move.d 31,r4 - asr.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0xda67f19f,r3 - move.d 32,r4 - asr.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0xda67f19f,r3 - move.d 33,r4 - asr.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0xda67f19f,r3 - move.d 66,r4 - asr.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; f699fc67 - - moveq -1,r3 - moveq 0,r4 - asr.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - moveq 1,r4 - asr.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - moveq -1,r3 - moveq 31,r4 - asr.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 15,r4 - asr.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x5a67f19f,r3 - moveq 12,r4 - asr.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 5a67f - - move.d 0xda67f19f,r3 - move.d 31,r4 - asr.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; da67ffff - - move.d 0xda67f19f,r3 - move.d 32,r4 - asr.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; da67ffff - - move.d 0xda67f19f,r3 - move.d 33,r4 - asr.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; da67ffff - - move.d 0xda67f19f,r3 - move.d 66,r4 - asr.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; da67fc67 - - moveq -1,r3 - moveq 0,r4 - asr.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 1,r4 - asr.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - moveq 1,r4 - asr.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - moveq -1,r3 - moveq 31,r4 - asr.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 15,r4 - asr.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x5a67719f,r3 - moveq 12,r4 - asr.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 5a670007 - - move.d 0xda67f19f,r3 - move.d 31,r4 - asr.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; da67f1ff - - move.d 0xda67f19f,r3 - move.d 32,r4 - asr.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; da67f1ff - - move.d 0xda67f19f,r3 - move.d 33,r4 - asr.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; da67f1ff - - move.d 0xda67f19f,r3 - move.d 66,r4 - asr.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; da67f1e7 - - moveq -1,r3 - moveq 0,r4 - asr.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 1,r4 - asr.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - moveq 1,r4 - asr.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - moveq -1,r3 - moveq 31,r4 - asr.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 15,r4 - asr.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 7,r4 - asr.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x5a67f19f,r3 - moveq 12,r4 - asr.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 5a67f1ff - - move.d 0x5a67f19f,r3 - moveq 4,r4 - asr.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 5a67f1f9 - - move.d 0x5a67f19f,r3 - asrq 31,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x5a67419f,r3 - moveq 16,r4 - asr.w r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 5a670000 - - quit diff --git a/sim/testsuite/sim/cris/asm/ba.ms b/sim/testsuite/sim/cris/asm/ba.ms deleted file mode 100644 index 1211962..0000000 --- a/sim/testsuite/sim/cris/asm/ba.ms +++ /dev/null @@ -1,93 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: a\n - - .include "testutils.inc" - - .if ..asm.arch.cris.v32 - .set smalloffset,0 - .set largeoffset,0 - .else - .set smalloffset,2 - .set largeoffset,4 - .endif - - start - moveq 0,r3 - -; Short forward branch. - ba 0f - addq 1,r3 - fail - -; Max short forward branch. -1: - ba 2f - addq 1,r3 - fail - -; Short backward branch. -0: - ba 1b - addq 1,r3 - fail - - .space 254-2+smalloffset+1b-.,0 - moveq 0,r3 - -2: -; Transit branch (long). - ba 3f - addq 1,r3 - fail - - moveq 0,r3 -4: -; Long forward branch. - ba 5f - addq 1,r3 - fail - - .space 256-2-smalloffset+4b-.,0 - - moveq 0,r3 - -; Max short backward branch. -3: - ba 4b - addq 1,r3 - fail - -5: -; Max long forward branch. - ba 6f - addq 1,r3 - fail - - .space 32766+largeoffset-2+5b-.,0 - - moveq 0,r3 -6: -; Transit branch. - ba 7f - addq 1,r3 - fail - - moveq 0,r3 -9: - dumpr3 - quit - -; Transit branch. - moveq 0,r3 -7: - ba 8f - addq 1,r3 - fail - - .space 32768-largeoffset+9b-.,0 - -8: -; Max long backward branch. - ba 9b - addq 1,r3 - fail diff --git a/sim/testsuite/sim/cris/asm/badarch1.ms b/sim/testsuite/sim/cris/asm/badarch1.ms deleted file mode 100644 index 3d0d812..0000000 --- a/sim/testsuite/sim/cris/asm/badarch1.ms +++ /dev/null @@ -1,5 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# xerror: -# output: *not a CRIS program* -# sim: /bin/sh - .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/bare1.ms b/sim/testsuite/sim/cris/asm/bare1.ms deleted file mode 100644 index 6c7d0d2..0000000 --- a/sim/testsuite/sim/cris/asm/bare1.ms +++ /dev/null @@ -1,24 +0,0 @@ -# mach: crisv32 -# ld: --section-start=.text=0 -# output: 0\n0\n4\n42\n -# sim: --cris-naked - -; Check that we don't get signs of an initialized environment -; when --cris-naked. - - .include "testutils.inc" - .text - .global _start -_start: - nop - nop -start2: - move.d $r10,$r3 - dumpr3 - move.d $sp,$r3 - dumpr3 - lapc start2,$r3 - dumpr3 - move.d 0x42,$r3 - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/bare2.ms b/sim/testsuite/sim/cris/asm/bare2.ms deleted file mode 100644 index f30fd10..0000000 --- a/sim/testsuite/sim/cris/asm/bare2.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv32 -# output: 0\n0\n4\n42\n -# sim: --cris-naked --target binary --architecture crisv32 -# ld: --oformat binary - -; Check that we can run a naked binary with the same expected -; results as an ELF "executable". - - .include "bare1.ms" diff --git a/sim/testsuite/sim/cris/asm/bare3.ms b/sim/testsuite/sim/cris/asm/bare3.ms deleted file mode 100644 index 103530d..0000000 --- a/sim/testsuite/sim/cris/asm/bare3.ms +++ /dev/null @@ -1,41 +0,0 @@ -# mach: crisv32 -# ld: -N --oformat binary --section-start=.text=0x10000000 -# sim: --architecture crisv32 --target binary --cris-program-offset=0x10000000 --cris-start-address=0x10000040 --cris-naked --memory-region 0x10000000,0x1000 - .include "testutils.inc" - -; Test that we can load a binary program at a non-zero address. -; Also serves to exercise the --cris-program-offset and -; --cris-start-address options. - -; Make sure starting at the first address does fail. - fail - -; ...and that we know an offset we can jump for it to work, and all we -; have to assume is that "fail" takes no more than 64 bytes. - .p2align 6 - ba _start - nop - -; - start -x: - -; Make sure we're loaded at the linked address. Since we're re-used -; in other tests, we have to provide for non-v32 as well. - .if ..asm.arch.cris.v32 - lapcq .,$r0 - .else - move.d $pc,$r0 - subq .-x,$r0 - .endif - - cmp.d x,$r0 - bne y - nop - pass -y: - fail - -; Make sure we have enough contents for the mapping. - .data - .fill 4096,1,0 diff --git a/sim/testsuite/sim/cris/asm/bas.ms b/sim/testsuite/sim/cris/asm/bas.ms deleted file mode 100644 index 084b5bf..0000000 --- a/sim/testsuite/sim/cris/asm/bas.ms +++ /dev/null @@ -1,102 +0,0 @@ -# mach: crisv32 -# output: 0\n0\n0\nfb349abc\n0\n12124243\n0\n0\neab5baad\n0\nefb37832\n - - .include "testutils.inc" - start -x: - setf zncv - bsr 0f - nop -0: - test_cc 1 1 1 1 - move srp,r3 - sub.d 0b,r3 - dumpr3 - - bas 1f,mof - moveq 0,r0 -6: - nop - quit - -2: - move srp,r3 - sub.d 3f,r3 - dumpr3 - move srp,r4 - subq 4,r4 - move.d [r4],r3 - dumpr3 - - basc 4f,mof - nop - .dword 0x12124243 -7: - nop - quit - -8: - move mof,r3 - sub.d 7f,r3 - dumpr3 - - move mof,r4 - subq 4,r4 - move.d [r4],r3 - dumpr3 - - jasc 9f,mof - nop - .dword 0xefb37832 -0: - quit - - quit -9: - move mof,r3 - sub.d 0b,r3 - dumpr3 - - move mof,r4 - subq 4,r4 - move.d [r4],r3 - dumpr3 - - quit - -4: - move mof,r3 - sub.d 7b,r3 - dumpr3 - move mof,r4 - subq 4,r4 - move.d [r4],r3 - dumpr3 - basc 5f,bz - moveq 0,r3 - .dword 0x7634aeba - quit - - .space 32770,0 -1: - move mof,r3 - sub.d 6b,r3 - dumpr3 - - bsrc 2b - nop - .dword 0xfb349abc -3: - - quit - -5: - move mof,r3 - sub.d 7b,r3 - dumpr3 - move.d 8b,r6 - jasc r6,mof - nop - .dword 0xeab5baad -7: - quit diff --git a/sim/testsuite/sim/cris/asm/bccb.ms b/sim/testsuite/sim/cris/asm/bccb.ms deleted file mode 100644 index da5e415..0000000 --- a/sim/testsuite/sim/cris/asm/bccb.ms +++ /dev/null @@ -1,181 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1c\n - - .include "testutils.inc" - start - moveq 0,r3 - - clearf nzvc - setf nzv - bcc 0f - addq 1,r3 - fail - -0: - clearf nzvc - setf nzv - bcs dofail - addq 1,r3 - - clearf nzvc - setf ncv - bne 1f - addq 1,r3 - -dofail: - fail - -1: - clearf nzvc - setf ncv - beq dofail - addq 1,r3 - - clearf nzvc - setf ncz - bvc 2f - addq 1,r3 - fail - -2: - clearf nzvc - setf ncz - bvs dofail - addq 1,r3 - - clearf nzvc - setf vcz - bpl 3f - addq 1,r3 - fail - -3: - clearf nzvc - setf vcz - bmi dofail - addq 1,r3 - - clearf nzvc - setf nv - bls dofail - addq 1,r3 - - clearf nzvc - setf nv - bhi 4f - addq 1,r3 - fail - -4: - clearf nzvc - setf zc - bge 5f - addq 1,r3 - fail - -5: - clearf nzvc - setf zc - blt dofail - addq 1,r3 - - clearf nzvc - setf c - bgt 6f - addq 1,r3 - fail - -6: - clearf nzvc - setf c - ble dofail - addq 1,r3 - -;;;;;;;;;; - - setf nzvc - clearf nzv - bcc dofail - addq 1,r3 - - setf nzvc - clearf nzv - bcs 0f - addq 1,r3 - fail - -0: - setf nzvc - clearf ncv - bne dofail - addq 1,r3 - - setf nzvc - clearf ncv - beq 1f - addq 1,r3 - fail - -1: - setf nzvc - clearf ncz - bvc dofail - addq 1,r3 - - setf nzvc - clearf ncz - bvs 2f - addq 1,r3 - fail - -2: - setf nzvc - clearf vcz - bpl dofail - addq 1,r3 - - setf nzvc - clearf vcz - bmi 3f - addq 1,r3 - fail - -3: - setf nzvc - clearf nv - bls 4f - addq 1,r3 - fail - -4: - setf nzvc - clearf nv - bhi dofail - addq 1,r3 - - setf zvc - clearf nzc - bge dofail - addq 1,r3 - - setf nzc - clearf vzc - blt 5f - addq 1,r3 - fail - -5: - setf nzvc - clearf c - bgt dofail - addq 1,r3 - - setf nzvc - clearf c - ble 6f - addq 1,r3 - fail - -6: - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/bdapc.ms b/sim/testsuite/sim/cris/asm/bdapc.ms deleted file mode 100644 index cfedd8b..0000000 --- a/sim/testsuite/sim/cris/asm/bdapc.ms +++ /dev/null @@ -1,57 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 -# output: 4455aa77\n4455aa77\nee19ccff\n88ccee19\nff22\n4455aa77\nff224455\n55aa77ff\n - - .include "testutils.inc" - .data -x: - .dword 0x55aa77ff - .dword 0xccff2244 - .dword 0x88ccee19 - .dword 0xb232765a - - start - moveq -1,r0 - moveq -1,r2 - move.d x-32768,r5 - move.d [r5+32769],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 4455aa77 - - addu.w 32770,r5 - bdap.w -1,r5 - move.d [r0],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 4455aa77 - - bdap.d 4,r5 - move.d [r2+],r3 - test_move_cc 1 0 0 0 - dumpr3 ; ee19ccff - - bdap.b 2,r2 - move.d [r3],r3 - test_move_cc 1 0 0 0 - dumpr3 ; 88ccee19 - - bdap.b 3,r5 - movu.w [r4+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; ff22 - - bdap.b -4,r4 - move.d [r6+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 4455aa77 - - bdap.w 2,r6 - move.d [r3],r9 - test_move_cc 1 0 0 0 - dumpr3 ; ff224455 - - add.d 76789885,r5 - bdap.d -76789887,r5 - move.d [r3],r9 - test_move_cc 0 0 0 0 - dumpr3 ; 55aa77ff - - quit diff --git a/sim/testsuite/sim/cris/asm/bdapm.ms b/sim/testsuite/sim/cris/asm/bdapm.ms deleted file mode 100644 index 26bc4ad..0000000 --- a/sim/testsuite/sim/cris/asm/bdapm.ms +++ /dev/null @@ -1,56 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 -# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n - - .include "testutils.inc" - .data -x: - .dword 0x55aa77ff - .dword 0xccff2244 - .dword 0x88ccee19 -y: - .dword 32769 - .word -1 - .dword 5 - .byte 3,-4 - .word 2 - .dword -76789887 - - start - moveq -1,r0 - move.d x-32768,r5 - move.d y,r13 - bdap.d [r13+],r5 - move.d [r3],r9 - test_move_cc 0 0 0 0 - dumpr3 ; 4455aa77 - - addu.w 32770,r5 - bdap.w [r13+],r5 - move.d [r9+],r3 - dumpr3 ; 4455aa77 - - bdap.d [r13],r9 - move.d [r3],r7 - addq 4,r13 - dumpr3 ; ee19ccff - - bdap.b [r13+],r5 - movu.w [r7+],r3 - dumpr3 ; ff22 - - bdap.b [r13],r7 - move.d [r7+],r3 - addq 1,r13 - dumpr3 ; 4455aa77 - - bdap.w [r13],r7 - move.d [r3],r3 - addq 2,r13 - dumpr3 ; ff224455 - - add.d 76789885,r5 - bdap.d [r13+],r5 - move.d [r3],r9 - dumpr3 ; 55aa77ff - - quit diff --git a/sim/testsuite/sim/cris/asm/bdapq.ms b/sim/testsuite/sim/cris/asm/bdapq.ms deleted file mode 100644 index a0ba406..0000000 --- a/sim/testsuite/sim/cris/asm/bdapq.ms +++ /dev/null @@ -1,29 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 -# output: ccff2244\n88ccee19\n55aa77ff\n19cc\n0\n - - .include "testutils.inc" - .data -x: - .dword 0x55aa77ff - .dword 0xccff2244 - .dword 0x88ccee19 - .dword 0 - start - moveq -1,r0 - move.d x+4,r5 - move.d [r5+0],r3 - test_move_cc 1 0 0 0 - dumpr3 ; ccff2244 - move.d [r5=r5+4],r3 - test_move_cc 1 0 0 0 - dumpr3 ; 88ccee19 - move.d [r5=r5-8],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 55aa77ff - movu.w [r5+7],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 19cc - move.d [r5+12],r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - quit diff --git a/sim/testsuite/sim/cris/asm/bdapqpc.ms b/sim/testsuite/sim/cris/asm/bdapqpc.ms deleted file mode 100644 index f2209ef..0000000 --- a/sim/testsuite/sim/cris/asm/bdapqpc.ms +++ /dev/null @@ -1,30 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# output: aaeebb11\nde378218\n - -# Test that the special case "X [pc+I],Y" works, where I byte-sized. - - .include "testutils.inc" - start -x: -; FIXME: Gas bugs are making this a bit harder than necessary. -; move.d [pc+y-(.+2)],r3 - move.d [pc+8],r3 -yy: - jump zz - -y: - .dword 0xaaeebb11 -y2: - .dword 0xde378218 - -zz: - dumpr3 - jump z - quit - -; Check a negative offset. - .space 50 -z: - move.d [pc+y2-(.+2)],r3 - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/biap.ms b/sim/testsuite/sim/cris/asm/biap.ms deleted file mode 100644 index a51a918..0000000 --- a/sim/testsuite/sim/cris/asm/biap.ms +++ /dev/null @@ -1,56 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 -# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n - - .include "testutils.inc" - .data -x: - .dword 0x55aa77ff - .dword 0xccff2244 - .dword 0x88ccee19 - - start - moveq -1,r0 - move.d x-32768,r5 - move.d 32769,r6 - move.d [r5+r6.b],r3 - test_cc 0 0 0 0 - dumpr3 ; 4455aa77 - - addu.w 32771,r5 - moveq -1,r8 - move.d [r11=r5+r8.w],r3 - test_cc 0 0 0 0 - dumpr3 ; 4455aa77 - - moveq 5,r10 - move.d [r11+r10.b],r3 - test_cc 1 0 0 0 - dumpr3 ; ee19ccff - - subq 1,r5 - move.d r5,r8 - subq 1,r8 - moveq 1,r9 - movu.w [r12=r8+r9.d],r3 - test_cc 0 0 0 0 - dumpr3 ; ff22 - - moveq -2,r11 - move.d [r13=r12+r11.w],r3 - test_cc 0 0 0 0 - dumpr3 ; 4455aa77 - - subq 18,r13 - moveq 5,r9 - move.d [r13+r9.d],r3 - test_cc 1 0 0 0 - dumpr3 ; ff224455 - - move.d r5,r7 - add.d 76789886,r7 - move.d -76789888/4,r12 - move.d [r7+r12.d],r3 - test_cc 0 0 0 0 - dumpr3 ; 55aa77ff - - quit diff --git a/sim/testsuite/sim/cris/asm/boundc.ms b/sim/testsuite/sim/cris/asm/boundc.ms deleted file mode 100644 index 0b2be13..0000000 --- a/sim/testsuite/sim/cris/asm/boundc.ms +++ /dev/null @@ -1,101 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 2\n2\nffff\nffffffff\n5432f789\n2\nffff\n2\nffff\nffff\nf789\n2\n2\nff\nff\nff\n89\n0\nff\n - - .include "testutils.inc" - start - moveq -1,r3 - moveq 2,r4 - bound.d 2,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq 2,r3 - bound.d 0xffffffff,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xffff,r3 - bound.d 0xffff,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq -1,r3 - bound.d 0xffffffff,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x78134452,r3 - bound.d 0x5432f789,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 5432f789 - - moveq -1,r3 - bound.w 2,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq -1,r3 - bound.w 0xffff,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq 2,r3 - bound.w 0xffff,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xffff,r3 - bound.w 0xffff,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - move.d 0xfedaffff,r3 - bound.w 0xffff,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - move.d 0x78134452,r3 - bound.w 0xf789,r3 - test_move_cc 0 0 0 0 - dumpr3 ; f789 - - moveq -1,r3 - bound.b 2,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq 2,r3 - bound.b 0xff,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq -1,r3 - bound.b 0xff,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ff - - move.d 0xff,r3 - bound.b 0xff,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ff - - move.d 0xfeda49ff,r3 - bound.b 0xff,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ff - - move.d 0x78134452,r3 - bound.b 0x89,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 89 - - bound.w 0,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0xffff,r3 - bound.b -1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ff - - quit diff --git a/sim/testsuite/sim/cris/asm/boundm.ms b/sim/testsuite/sim/cris/asm/boundm.ms deleted file mode 100644 index 91019dd..0000000 --- a/sim/testsuite/sim/cris/asm/boundm.ms +++ /dev/null @@ -1,105 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 -# output: 2\n2\nffff\nffffffff\n5432f789\n2\nffff\n2\nffff\nffff\nf789\n2\n2\nff\nff\nff\n89\n0\n - - .include "testutils.inc" - .data -x: - .dword 2,-1,0xffff,-1,0x5432f789 - .word 2,0xffff,0xf789 - .byte 2,0xff,0x89,0 - - start - move.d x,r5 - - moveq -1,r3 - moveq 2,r4 - bound.d [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq 2,r3 - bound.d [r5],r3 - test_move_cc 0 0 0 0 - addq 4,r5 - dumpr3 ; 2 - - move.d 0xffff,r3 - bound.d [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq -1,r3 - bound.d [r5+],r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x78134452,r3 - bound.d [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 5432f789 - - moveq -1,r3 - bound.w [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq -1,r3 - bound.w [r5],r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq 2,r3 - bound.w [r5],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xffff,r3 - bound.w [r5],r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - move.d 0xfedaffff,r3 - bound.w [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - move.d 0x78134452,r3 - bound.w [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; f789 - - moveq -1,r3 - bound.b [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq 2,r3 - bound.b [r5],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq -1,r3 - bound.b [r5],r3 - test_move_cc 0 0 0 0 - dumpr3 ; ff - - move.d 0xff,r3 - bound.b [r5],r3 - test_move_cc 0 0 0 0 - dumpr3 ; ff - - move.d 0xfeda49ff,r3 - bound.b [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; ff - - move.d 0x78134452,r3 - bound.b [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 89 - - bound.b [r5],r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/boundmv32.ms b/sim/testsuite/sim/cris/asm/boundmv32.ms deleted file mode 100644 index 560276e..0000000 --- a/sim/testsuite/sim/cris/asm/boundmv32.ms +++ /dev/null @@ -1,15 +0,0 @@ -# mach: crisv32 -# xerror: -# output: program stopped with signal 4 (*).\n - .include "testutils.inc" - -; Check that bound with a memory operand is invalid. - start - move.d 0f,r5 - move.d r5,r3 - .byte 0xd5,0x39 ; bound.d [r5],r3 -- we can't assemble it. - pass - -0: - .dword 0b - diff --git a/sim/testsuite/sim/cris/asm/boundr.ms b/sim/testsuite/sim/cris/asm/boundr.ms deleted file mode 100644 index 053c4ae..0000000 --- a/sim/testsuite/sim/cris/asm/boundr.ms +++ /dev/null @@ -1,125 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 2\n2\nffff\nffffffff\n5432f789\n2\n2\nffff\nffff\nffff\nf789\n2\n2\nff\nff\n89\nfeda4953\nfeda4962\n0\n0\n - - .include "testutils.inc" - start - moveq -1,r3 - moveq 2,r4 - bound.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq 2,r3 - moveq -1,r4 - bound.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xffff,r4 - move.d r4,r3 - bound.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq -1,r4 - move.d r4,r3 - bound.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - bound.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 5432f789 - - moveq -1,r3 - moveq 2,r4 - bound.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq 2,r3 - moveq -1,r4 - bound.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq -1,r3 - bound.w r3,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - move.d 0xffff,r4 - move.d r4,r3 - bound.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - move.d 0xfedaffff,r4 - move.d r4,r3 - bound.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - bound.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; f789 - - moveq -1,r3 - moveq 2,r4 - bound.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - moveq 2,r3 - moveq -1,r4 - bound.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xff,r4 - move.d r4,r3 - bound.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ff - - move.d 0xfeda49ff,r4 - move.d r4,r3 - bound.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ff - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - bound.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 89 - - move.d 0xfeda4956,r3 - move.d 0xfeda4953,r4 - bound.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; feda4953 - - move.d 0xfeda4962,r3 - move.d 0xfeda4963,r4 - bound.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; feda4962 - - move.d 0xfeda4956,r3 - move.d 0,r4 - bound.d r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0xfeda4956,r4 - move.d 0,r3 - bound.d r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/break.ms b/sim/testsuite/sim/cris/asm/break.ms deleted file mode 100644 index c1a7a96..0000000 --- a/sim/testsuite/sim/cris/asm/break.ms +++ /dev/null @@ -1,15 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# sim: --trace-core=on -# ld: --section-start=.text=0 -# output: read-2 exec:0x00000002 -> 0x05b0\nread-2 exec:0x00000004 -> 0xe93f\n - -; First test: Must exit gracefully. - - .include "testutils.inc" - -; This first insn isn't executed (it's a filler); it would fail -; ungracefully if executed. - - startnostack - setf - quit diff --git a/sim/testsuite/sim/cris/asm/btst.ms b/sim/testsuite/sim/cris/asm/btst.ms deleted file mode 100644 index b63e8f2..0000000 --- a/sim/testsuite/sim/cris/asm/btst.ms +++ /dev/null @@ -1,87 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1111\n - - .include "testutils.inc" - start - clearf nzvc - moveq -1,r3 - .if ..asm.arch.cris.v32 - .else - setf vc - .endif - btstq 0,r3 - test_cc 1 0 0 0 - - moveq 2,r3 - btstq 1,r3 - test_cc 1 0 0 0 - - moveq 4,r3 - btstq 1,r3 - test_cc 0 1 0 0 - - moveq -1,r3 - btstq 31,r3 - test_cc 1 0 0 0 - - move.d 0x5a67f19f,r3 - btstq 12,r3 - test_cc 1 0 0 0 - - move.d 0xda67f19f,r3 - move.d 29,r4 - btst r4,r3 - test_cc 0 0 0 0 - - move.d 0xda67f19f,r3 - move.d 32,r4 - btst r4,r3 - test_cc 1 0 0 0 - - move.d 0xda67f191,r3 - move.d 33,r4 - btst r4,r3 - test_cc 0 0 0 0 - - moveq -1,r3 - moveq 0,r4 - btst r4,r3 - test_cc 1 0 0 0 - - moveq 2,r3 - moveq 1,r4 - btst r4,r3 - test_cc 1 0 0 0 - - moveq -1,r3 - moveq 31,r4 - btst r4,r3 - test_cc 1 0 0 0 - - moveq 4,r3 - btstq 1,r3 - test_cc 0 1 0 0 - - moveq -1,r3 - moveq 15,r4 - btst r4,r3 - test_cc 1 0 0 0 - - move.d 0x5a67f19f,r3 - moveq 12,r4 - btst r4,r3 - test_cc 1 0 0 0 - - move.d 0x5a678000,r3 - moveq 11,r4 - btst r4,r3 - test_cc 0 1 0 0 - - move.d 0x5a67f19f,r3 - btst r3,r3 - test_cc 0 0 0 0 - - move.d 0x1111,r3 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/ccr-v10.ms b/sim/testsuite/sim/cris/asm/ccr-v10.ms deleted file mode 100644 index 39602f0..0000000 --- a/sim/testsuite/sim/cris/asm/ccr-v10.ms +++ /dev/null @@ -1,79 +0,0 @@ -# mach: crisv10 -# output: ff\nff\n0\n0\n80\n40\n20\n10\n8\n4\n2\n1\n80\n40\n20\n10\n8\n4\n2\n1\n42\n - -; Check that flag settings affect ccr and dccr and vice versa. - - .include "testutils.inc" - start - clear.d r3 - setf mbixnzvc - move ccr,r3 - dumpr3 - - clear.d r3 - setf mbixnzvc - move dccr,r3 - dumpr3 - - clear.d r3 - clearf mbixnzvc - move ccr,r3 - dumpr3 - - clear.d r3 - clearf mbixnzvc - move dccr,r3 - dumpr3 - - .macro testfr BIT REG - clear.d r3 - clearf mbixnzvc - setf \BIT - move \REG,r3 - dumpr3 - .endm - - testfr m ccr - testfr b ccr - testfr i ccr - testfr x ccr - testfr n ccr - testfr z ccr - testfr v ccr - testfr c ccr - - testfr m dccr - testfr b dccr - testfr i dccr - testfr x dccr - testfr n dccr - testfr z dccr - testfr v dccr - testfr c dccr - -; Check only the nzvc bits; do the other bits in special tests as they're -; implemented. - .macro test_get_cc N Z V C - clearf znvc - move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccr - test_cc \N \Z \V \C - setf znvc - move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),dccr - test_cc \N \Z \V \C - move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4 - setf znvc - move r4,ccr - test_cc \N \Z \V \C - clearf znvc - move r4,dccr - test_cc \N \Z \V \C - .endm - - test_get_cc 1 0 0 0 - test_get_cc 0 1 0 0 - test_get_cc 0 0 1 0 - test_get_cc 0 0 0 1 - - move.d 0x42,r3 - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/ccs-v32.ms b/sim/testsuite/sim/cris/asm/ccs-v32.ms deleted file mode 100644 index 8dc6026..0000000 --- a/sim/testsuite/sim/cris/asm/ccs-v32.ms +++ /dev/null @@ -1,73 +0,0 @@ -# mach: crisv32 -# output: bf\n0\n80\n20\n10\n8\n4\n2\n1\n40\nfade040\n3ade0040\nfade040\n42\n - -; Check flag settings. - - .include "testutils.inc" - start - clear.d r3 - setf pixnzvc ; Setting U(ser mode) would restrict tests of other flags. - move ccs,r3 - dumpr3 - - clear.d r3 - clearf puixnzvc - move ccs,r3 - dumpr3 - - .macro testf BIT - clear.d r3 - clearf puixnzvc - setf \BIT - move ccs,r3 - dumpr3 - .endm - - testf p - testf i - testf x - testf n - testf z - testf v - testf c - testf u ; Can't test i-flag or clear u after this point. - - .macro test_get_cc N Z V C - clearf znvc - move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccs - test_cc \N \Z \V \C - setf znvc - move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccs - test_cc \N \Z \V \C - move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4 - setf znvc - move r4,ccs - test_cc \N \Z \V \C - clearf znvc - move r4,ccs - test_cc \N \Z \V \C - .endm - - test_get_cc 1 0 0 0 - test_get_cc 0 1 0 0 - test_get_cc 0 0 1 0 - test_get_cc 0 0 0 1 - -; Test that the U bit sticks. - move 0x0fade000,ccs - move ccs,r3 - dumpr3 - -; Check that the M and Q bits can't be set in user mode. - move 0xfade0000,ccs - move ccs,r3 - dumpr3 - - move 0x0fade000,ccs - move ccs,r3 - dumpr3 - - move.d 0x42,r3 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/clearfv10.ms b/sim/testsuite/sim/cris/asm/clearfv10.ms deleted file mode 100644 index d910842..0000000 --- a/sim/testsuite/sim/cris/asm/clearfv10.ms +++ /dev/null @@ -1,12 +0,0 @@ -# mach: crisv10 -# output: ef\n - -; Check that "clearf x" doesn't trivially fail. - - .include "testutils.inc" - start - setf mbixnzvc - clearf x ; Actually, x would be cleared by almost-all other insns. - move dccr,r3 - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/clearfv32.ms b/sim/testsuite/sim/cris/asm/clearfv32.ms deleted file mode 100644 index b1dd3de..0000000 --- a/sim/testsuite/sim/cris/asm/clearfv32.ms +++ /dev/null @@ -1,12 +0,0 @@ -# mach: crisv32 -# output: ef\n - -; Check that "clearf x" doesn't trivially fail. - - .include "testutils.inc" - start - setf puixnzvc - clearf x ; Actually, x would be cleared by almost-all other insns. - move ccs,r3 - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/clrjmp1.ms b/sim/testsuite/sim/cris/asm/clrjmp1.ms deleted file mode 100644 index 1a76e7f..0000000 --- a/sim/testsuite/sim/cris/asm/clrjmp1.ms +++ /dev/null @@ -1,36 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: ffffff00\n - -; A bug resulting in a non-effectual clear.b discovered running the GCC -; testsuite; jump actually wrote to p0. - - .include "testutils.inc" - - start - jump 1f - nop - .p2align 8 -1: - move.d y,r4 - - .if 0 == ..asm.arch.cris.v32 -; There was a bug causing this insn to set special register p0 -; (byte-clear) to 8 (low 8 bits of location after insn). - jump [r4+] - .endif - -1: - move.d 0f,r4 - -; The corresponding bug would cause this insn too, to set p0. - jump r4 - nop - quit -0: - moveq -1,r3 - clear.b r3 - dumpr3 - quit - -y: - .dword 1b diff --git a/sim/testsuite/sim/cris/asm/cmpc.ms b/sim/testsuite/sim/cris/asm/cmpc.ms deleted file mode 100644 index 8600f5f..0000000 --- a/sim/testsuite/sim/cris/asm/cmpc.ms +++ /dev/null @@ -1,86 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649282\n - - .include "testutils.inc" - start - moveq -1,r3 - cmp.d -2,r3 - test_cc 0 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - cmp.d 1,r3 - test_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xffff,r3 - cmp.d -0xffff,r3 - test_cc 0 0 0 1 - dumpr3 ; ffff - - moveq -1,r3 - cmp.d 1,r3 - test_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x78134452,r3 - cmp.d -0x5432f789,r3 - test_cc 1 0 1 1 - dumpr3 ; 78134452 - - moveq -1,r3 - cmp.w -2,r3 - test_cc 0 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - cmp.w 1,r3 - test_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xffff,r3 - cmp.w 1,r3 - test_cc 1 0 0 0 - dumpr3 ; ffff - - move.d 0xfedaffff,r3 - cmp.w 1,r3 - test_cc 1 0 0 0 - dumpr3 ; fedaffff - - move.d 0x78134452,r3 - cmp.w 0x877,r3 - test_cc 0 0 0 0 - dumpr3 ; 78134452 - - moveq -1,r3 - cmp.b -2,r3 - test_cc 0 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - cmp.b 1,r3 - test_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xff,r3 - cmp.b 1,r3 - test_cc 1 0 0 0 - dumpr3 ; ff - - move.d 0xfeda49ff,r3 - cmp.b 1,r3 - test_cc 1 0 0 0 - dumpr3 ; feda49ff - - move.d 0x78134452,r3 - cmp.b 0x77,r3 - test_cc 1 0 0 1 - dumpr3 ; 78134452 - - move.d 0x85649282,r3 - cmp.b 0x82,r3 - test_cc 0 1 0 0 - dumpr3 ; 85649282 - - quit diff --git a/sim/testsuite/sim/cris/asm/cmpm.ms b/sim/testsuite/sim/cris/asm/cmpm.ms deleted file mode 100644 index 753f2d3..0000000 --- a/sim/testsuite/sim/cris/asm/cmpm.ms +++ /dev/null @@ -1,96 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649222\n - - .include "testutils.inc" - .data -x: - .dword -2,1,-0xffff,1,-0x5432f789 - .word -2,1,1,0x877 - .byte -2,1,0x77 - .byte 0x22 - - start - moveq -1,r3 - move.d x,r5 - cmp.d [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - cmp.d [r5],r3 - test_cc 0 0 0 0 - addq 4,r5 - dumpr3 ; 2 - - move.d 0xffff,r3 - cmp.d [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; ffff - - moveq -1,r3 - cmp.d [r5+],r3 - test_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x78134452,r3 - cmp.d [r5+],r3 - test_cc 1 0 1 1 - dumpr3 ; 78134452 - - moveq -1,r3 - cmp.w [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - cmp.w [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xffff,r3 - cmp.w [r5],r3 - test_cc 1 0 0 0 - dumpr3 ; ffff - - move.d 0xfedaffff,r3 - cmp.w [r5+],r3 - test_cc 1 0 0 0 - dumpr3 ; fedaffff - - move.d 0x78134452,r3 - cmp.w [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; 78134452 - - moveq -1,r3 - cmp.b [r5],r3 - test_cc 0 0 0 0 - addq 1,r5 - dumpr3 ; ffffffff - - moveq 2,r3 - cmp.b [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xff,r3 - cmp.b [r5],r3 - test_cc 1 0 0 0 - dumpr3 ; ff - - move.d 0xfeda49ff,r3 - cmp.b [r5+],r3 - test_cc 1 0 0 0 - dumpr3 ; feda49ff - - move.d 0x78134452,r3 - cmp.b [r5+],r3 - test_cc 1 0 0 1 - dumpr3 ; 78134452 - - move.d 0x85649222,r3 - cmp.b [r5],r3 - test_cc 0 1 0 0 - dumpr3 ; 85649222 - - quit diff --git a/sim/testsuite/sim/cris/asm/cmpq.ms b/sim/testsuite/sim/cris/asm/cmpq.ms deleted file mode 100644 index 7e40be4..0000000 --- a/sim/testsuite/sim/cris/asm/cmpq.ms +++ /dev/null @@ -1,75 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: 1\n1\n1\n1f\n1f\nffffffe1\nffffffe1\nffffffe0\n0\n0\nffffffff\nffffffff\n10000\n100\n5678900\n - - .include "testutils.inc" - start - moveq 1,r3 - cmpq 1,r3 - test_cc 0 1 0 0 - dumpr3 ; 1 - - cmpq -1,r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - cmpq 31,r3 - test_cc 1 0 0 1 - dumpr3 ; 1 - - moveq 31,r3 - cmpq 31,r3 - test_cc 0 1 0 0 - dumpr3 ; 1f - - cmpq -31,r3 - test_cc 0 0 0 1 - dumpr3 ; 1f - - movs.b -31,r3 - cmpq -31,r3 - test_cc 0 1 0 0 - dumpr3 ; ffffffe1 - - cmpq -32,r3 - test_cc 0 0 0 0 - dumpr3 ; ffffffe1 - - movs.b -32,r3 - cmpq -32,r3 - test_cc 0 1 0 0 - dumpr3 ; ffffffe0 - - moveq 0,r3 - cmpq 1,r3 - test_cc 1 0 0 1 - dumpr3 ; 0 - - cmpq -32,r3 - test_cc 0 0 0 1 - dumpr3 ; 0 - - moveq -1,r3 - cmpq 1,r3 - test_cc 1 0 0 0 - dumpr3 ; ffffffff - - cmpq -1,r3 - test_cc 0 1 0 0 - dumpr3 ; ffffffff - - move.d 0x10000,r3 - cmpq 1,r3 - test_cc 0 0 0 0 - dumpr3 ; 10000 - - move.d 0x100,r3 - cmpq 1,r3 - test_cc 0 0 0 0 - dumpr3 ; 100 - - move.d 0x5678900,r3 - cmpq 7,r3 - test_cc 0 0 0 0 - dumpr3 ; 5678900 - - quit diff --git a/sim/testsuite/sim/cris/asm/cmpr.ms b/sim/testsuite/sim/cris/asm/cmpr.ms deleted file mode 100644 index 6730a00..0000000 --- a/sim/testsuite/sim/cris/asm/cmpr.ms +++ /dev/null @@ -1,102 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649222\n - - .include "testutils.inc" - start - moveq -1,r3 - moveq -2,r4 - cmp.d r4,r3 - test_cc 0 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - moveq 1,r4 - cmp.d r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xffff,r3 - move.d -0xffff,r4 - cmp.d r4,r3 - test_cc 0 0 0 1 - dumpr3 ; ffff - - moveq 1,r4 - moveq -1,r3 - cmp.d r4,r3 - test_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d -0x5432f789,r4 - move.d 0x78134452,r3 - cmp.d r4,r3 - test_cc 1 0 1 1 - dumpr3 ; 78134452 - - moveq -1,r3 - moveq -2,r4 - cmp.w r4,r3 - test_cc 0 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - moveq 1,r4 - cmp.w r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 2 - - move.d 0xffff,r3 - move.d -0xffff,r4 - cmp.w r4,r3 - test_cc 1 0 0 0 - dumpr3 ; ffff - - move.d 0xfedaffff,r3 - move.d -0xfedaffff,r4 - cmp.w r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fedaffff - - move.d -0x5432f789,r4 - move.d 0x78134452,r3 - cmp.w r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 78134452 - - moveq -1,r3 - moveq -2,r4 - cmp.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - moveq 1,r4 - cmp.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 2 - - move.d -0xff,r4 - move.d 0xff,r3 - cmp.b r4,r3 - test_cc 1 0 0 0 - dumpr3 ; ff - - move.d -0xfeda49ff,r4 - move.d 0xfeda49ff,r3 - cmp.b r4,r3 - test_cc 1 0 0 0 - dumpr3 ; feda49ff - - move.d -0x5432f789,r4 - move.d 0x78134452,r3 - cmp.b r4,r3 - test_cc 1 0 0 1 - dumpr3 ; 78134452 - - move.d 0x85649222,r3 - move.d 0x77445622,r4 - cmp.b r4,r3 - test_cc 0 1 0 0 - dumpr3 ; 85649222 - - quit diff --git a/sim/testsuite/sim/cris/asm/cmpxc.ms b/sim/testsuite/sim/cris/asm/cmpxc.ms deleted file mode 100644 index d9acd8f..0000000 --- a/sim/testsuite/sim/cris/asm/cmpxc.ms +++ /dev/null @@ -1,92 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 2\n2\n2\n2\nffff\nffff\nffff\nffff\nffffffff\nffffffff\nffffffff\n78134452\n78134452\n78134452\n78134452\n4452\n80000032\n - - .include "testutils.inc" - start - moveq 2,r3 - cmps.b 0xff,r3 - test_cc 0 0 0 1 - dumpr3 ; 2 - - moveq 2,r3 - cmps.w 0xffff,r3 - test_cc 0 0 0 1 - dumpr3 ; 2 - - moveq 2,r3 - cmpu.b 0xff,r3 - test_cc 1 0 0 1 - dumpr3 ; 2 - - moveq 2,r3 - move.d 0xffffffff,r4 - cmpu.w -1,r3 - test_cc 1 0 0 1 - dumpr3 ; 2 - - move.d 0xffff,r3 - cmpu.b -1,r3 - test_cc 0 0 0 0 - dumpr3 ; ffff - - move.d 0xffff,r3 - cmpu.w -1,r3 - test_cc 0 1 0 0 - dumpr3 ; ffff - - move.d 0xffff,r3 - cmps.b 0xff,r3 - test_cc 0 0 0 1 - dumpr3 ; ffff - - move.d 0xffff,r3 - cmps.w 0xffff,r3 - test_cc 0 0 0 1 - dumpr3 ; ffff - - moveq -1,r3 - cmps.b 0xff,r3 - test_cc 0 1 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - cmps.w 0xff,r3 - test_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - cmps.w 0xffff,r3 - test_cc 0 1 0 0 - dumpr3 ; ffffffff - - move.d 0x78134452,r3 - cmpu.b 0x89,r3 - test_cc 0 0 0 0 - dumpr3 ; 78134452 - - move.d 0x78134452,r3 - cmps.b 0x89,r3 - test_cc 0 0 0 1 - dumpr3 ; 78134452 - - move.d 0x78134452,r3 - cmpu.w 0xf789,r3 - test_cc 0 0 0 0 - dumpr3 ; 78134452 - - move.d 0x78134452,r3 - cmps.w 0xf789,r3 - test_cc 0 0 0 1 - dumpr3 ; 78134452 - - move.d 0x4452,r3 - cmps.w 0x8002,r3 - test_cc 0 0 0 1 - dumpr3 ; 4452 - - move.d 0x80000032,r3 - cmpu.w 0x764,r3 - test_cc 0 0 1 0 - dumpr3 ; 80000032 - - quit diff --git a/sim/testsuite/sim/cris/asm/cmpxm.ms b/sim/testsuite/sim/cris/asm/cmpxm.ms deleted file mode 100644 index 6a87ab04..0000000 --- a/sim/testsuite/sim/cris/asm/cmpxm.ms +++ /dev/null @@ -1,106 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 2\n2\n2\n2\nffff\nffff\nffff\nffff\nffffffff\nffffffff\nffffffff\n78134452\n78134452\n78134452\n78134452\n4452\n80000032\n - - .include "testutils.inc" - .data -x: - .byte 0xff - .word 0xffff - .word 0xff - .word 0xffff - .byte 0x89 - .word 0xf789 - .word 0x8002 - .word 0x764 - - start - moveq 2,r3 - move.d x,r5 - cmps.b [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 2 - - moveq 2,r3 - cmps.w [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 2 - - moveq 2,r3 - subq 3,r5 - cmpu.b [r5+],r3 - test_cc 1 0 0 1 - dumpr3 ; 2 - - moveq 2,r3 - cmpu.w [r5+],r3 - test_cc 1 0 0 1 - subq 3,r5 - dumpr3 ; 2 - - move.d 0xffff,r3 - cmpu.b [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; ffff - - move.d 0xffff,r3 - cmpu.w [r5],r3 - test_cc 0 1 0 0 - dumpr3 ; ffff - - move.d 0xffff,r3 - cmps.b [r5],r3 - test_cc 0 0 0 1 - dumpr3 ; ffff - - move.d 0xffff,r3 - cmps.w [r5],r3 - test_cc 0 0 0 1 - dumpr3 ; ffff - - moveq -1,r3 - cmps.b [r5],r3 - test_cc 0 1 0 0 - addq 3,r5 - dumpr3 ; ffffffff - - moveq -1,r3 - cmps.w [r5+],r3 - test_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - cmps.w [r5+],r3 - test_cc 0 1 0 0 - dumpr3 ; ffffffff - - move.d 0x78134452,r3 - cmpu.b [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; 78134452 - - move.d 0x78134452,r3 - cmps.b [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 78134452 - - move.d 0x78134452,r3 - cmpu.w [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; 78134452 - - move.d 0x78134452,r3 - cmps.w [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 78134452 - - move.d 0x4452,r3 - cmps.w [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 4452 - - move.d 0x80000032,r3 - cmpu.w [r5+],r3 - test_cc 0 0 1 0 - dumpr3 ; 80000032 - - quit diff --git a/sim/testsuite/sim/cris/asm/dflags.ms b/sim/testsuite/sim/cris/asm/dflags.ms deleted file mode 100644 index 2735014..0000000 --- a/sim/testsuite/sim/cris/asm/dflags.ms +++ /dev/null @@ -1,62 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: 31\n - -; Check that flag settings in the delay slot for a conditional branch do -; not affect the branch. - - .include "testutils.inc" - - start - moveq 1,r3 - moveq 0,r4 - -; 8-bit branches. - - move.d r4,r4 - bne 0f - move.d r3,r3 - bne 1f - move.d r4,r4 - nop -0: - quit - -1: - move.d r3,r3 - beq 0b - move.d r4,r4 - beq 4f - move.d r3,r3 - nop - quit -4: - jump 2f - nop - .space 1000 - -; 16-bit branches - -2: - move.d r4,r4 - bne 0b - move.d r3,r3 - bne 3f - move.d r4,r4 - nop - quit - .space 1000 - -3: - move.d r3,r3 - beq 0b - move.d r4,r4 - beq 4f - move.d r3,r3 - nop - quit - .space 1000 - -4: - move.d 0x31,r3 - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/dip.ms b/sim/testsuite/sim/cris/asm/dip.ms deleted file mode 100644 index ff79f22..0000000 --- a/sim/testsuite/sim/cris/asm/dip.ms +++ /dev/null @@ -1,41 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 -# output: 4455aa77\nee19ccff\nb232765a\nff22\n5a88ccee\n - - .include "testutils.inc" - .data -x: - .dword 0x55aa77ff - .dword 0xccff2244 - .dword 0x88ccee19 - .dword 0xb232765a -y: - .dword x+12 - .dword x+5 - .dword x+9 - - start - moveq -1,r0 - moveq -1,r2 - move.d [x+1],r3 - test_cc 0 0 0 0 - dumpr3 ; 4455aa77 - - move.d [x+6],r3 - test_cc 1 0 0 0 - dumpr3 ; ee19ccff - - move.d y,r8 - move.d [[r8+]],r3 - test_cc 1 0 0 0 - dumpr3 ; b232765a - - movu.w [[r8]],r3 - test_cc 0 0 0 0 - dumpr3 ; ff22 - addq 4,r8 - - move.d [[r8]],r3 - test_cc 0 0 0 0 - dumpr3 ; 5a88ccee - - quit diff --git a/sim/testsuite/sim/cris/asm/dstep.ms b/sim/testsuite/sim/cris/asm/dstep.ms deleted file mode 100644 index 8b32240..0000000 --- a/sim/testsuite/sim/cris/asm/dstep.ms +++ /dev/null @@ -1,42 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: fffffffc\n4\nffff\nfffffffe\n9bf3911b\n0\n - - .include "testutils.inc" - start - moveq -1,r3 - moveq 2,r4 - dstep r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fffffffc - - moveq 2,r3 - moveq -1,r4 - dstep r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 4 - - move.d 0xffff,r4 - move.d r4,r3 - dstep r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq -1,r4 - move.d r4,r3 - dstep r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fffffffe - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - dstep r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 9bf3911b - - move.d 0xffff,r3 - move.d 0x1fffe,r4 - dstep r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/fidxd.ms b/sim/testsuite/sim/cris/asm/fidxd.ms deleted file mode 100644 index 8158682..0000000 --- a/sim/testsuite/sim/cris/asm/fidxd.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv32 -# xerror: -# output: FIDXD isn't implemented\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - fidxd [r3] - - quit diff --git a/sim/testsuite/sim/cris/asm/fidxi.ms b/sim/testsuite/sim/cris/asm/fidxi.ms deleted file mode 100644 index 1c41ed4..0000000 --- a/sim/testsuite/sim/cris/asm/fidxi.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv32 -# xerror: -# output: FIDXI isn't implemented\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - fidxi [r5] - - quit diff --git a/sim/testsuite/sim/cris/asm/ftagd.ms b/sim/testsuite/sim/cris/asm/ftagd.ms deleted file mode 100644 index 74d4de3..0000000 --- a/sim/testsuite/sim/cris/asm/ftagd.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv32 -# xerror: -# output: FTAGD isn't implemented\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - ftagd [r11] - - quit diff --git a/sim/testsuite/sim/cris/asm/ftagi.ms b/sim/testsuite/sim/cris/asm/ftagi.ms deleted file mode 100644 index 187d22d..0000000 --- a/sim/testsuite/sim/cris/asm/ftagi.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv32 -# xerror: -# output: FTAGI isn't implemented\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - ftagi [r8] - - quit diff --git a/sim/testsuite/sim/cris/asm/halt.ms b/sim/testsuite/sim/cris/asm/halt.ms deleted file mode 100644 index fb4dcb0..0000000 --- a/sim/testsuite/sim/cris/asm/halt.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv32 -# xerror: -# output: HALT isn't implemented\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - halt - - quit diff --git a/sim/testsuite/sim/cris/asm/io1.ms b/sim/testsuite/sim/cris/asm/io1.ms deleted file mode 100644 index 3d252ae..0000000 --- a/sim/testsuite/sim/cris/asm/io1.ms +++ /dev/null @@ -1,8 +0,0 @@ -# mach: crisv32 -# sim: --cris-900000xx --memory-region 0x90000000,0x10 -# xerror: -# output: /core/cris_900000xx: memory map 0:0x90000000..0x900000ff (256 bytes) overlaps 0:0x90000000..0x9000000f (16 bytes)\nQuit Simulator\n - -; Check that I/O region overlap is detected. - - .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/io2.ms b/sim/testsuite/sim/cris/asm/io2.ms deleted file mode 100644 index f6341d3..0000000 --- a/sim/testsuite/sim/cris/asm/io2.ms +++ /dev/null @@ -1,18 +0,0 @@ -# mach: crisv32 -# sim: --cris-900000xx -# xerror: -# output: b1e\n - -; Check correct "fail" exit. - - .include "testutils.inc" - start - move.d 0xb1e,$r3 - dumpr3 - move.d 0x90000008,$acr - move.d $acr,[$acr] - move.d 0xbadc0de,$r3 - dumpr3 -0: - ba 0b - nop diff --git a/sim/testsuite/sim/cris/asm/io3.ms b/sim/testsuite/sim/cris/asm/io3.ms deleted file mode 100644 index 664dc61..0000000 --- a/sim/testsuite/sim/cris/asm/io3.ms +++ /dev/null @@ -1,17 +0,0 @@ -# mach: crisv32 -# sim: --cris-900000xx -# output: ce11d0c\n - -; Check correct "pass" exit. - - .include "testutils.inc" - start - move.d 0x0ce11d0c,$r3 - dumpr3 - move.d 0x90000004,$acr - move.d $acr,[$acr] - move.d 0xbadc0de,$r3 - dumpr3 -0: - ba 0b - nop diff --git a/sim/testsuite/sim/cris/asm/io4.ms b/sim/testsuite/sim/cris/asm/io4.ms deleted file mode 100644 index f925dbd..0000000 --- a/sim/testsuite/sim/cris/asm/io4.ms +++ /dev/null @@ -1,18 +0,0 @@ -# mach: crisv32 -# xerror: -# output: b1e\n - -; Check correct "fail" exit. - - .include "testutils.inc" - start - move.d 0xb1e,$r3 - dumpr3 - moveq 1,$r9 - moveq 2,$r10 - break 13 - move.d 0xbadc0de,$r3 - dumpr3 -0: - ba 0b - nop diff --git a/sim/testsuite/sim/cris/asm/io5.ms b/sim/testsuite/sim/cris/asm/io5.ms deleted file mode 100644 index 178a4d7..0000000 --- a/sim/testsuite/sim/cris/asm/io5.ms +++ /dev/null @@ -1,17 +0,0 @@ -# mach: crisv32 -# output: ce11d0c\n - -; Check correct "pass" exit. - - .include "testutils.inc" - start - move.d 0x0ce11d0c,$r3 - dumpr3 - moveq 1,$r9 - moveq 0,$r10 - break 13 - move.d 0xbadc0de,$r3 - dumpr3 -0: - ba 0b - nop diff --git a/sim/testsuite/sim/cris/asm/io6.ms b/sim/testsuite/sim/cris/asm/io6.ms deleted file mode 100644 index 3af3536..0000000 --- a/sim/testsuite/sim/cris/asm/io6.ms +++ /dev/null @@ -1,22 +0,0 @@ -# mach: crisv32 -# ld: --section-start=.text=0 -# sim: --cris-900000xx -# xerror: -# output: b1e\n -# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n -# output: program stopped with signal 11 (*).\n - -; Check that invalid access to the simulator area is recognized. -; "FAIL" area. - - .include "testutils.inc" - start - move.d 0xb1e,$r3 - dumpr3 - move.d 0x90000008,$acr - clear.d [$acr] - move.d 0xbadc0de,$r3 - dumpr3 -0: - ba 0b - nop diff --git a/sim/testsuite/sim/cris/asm/io7.ms b/sim/testsuite/sim/cris/asm/io7.ms deleted file mode 100644 index 84488e9..0000000 --- a/sim/testsuite/sim/cris/asm/io7.ms +++ /dev/null @@ -1,22 +0,0 @@ -# mach: crisv32 -# ld: --section-start=.text=0 -# sim: --cris-900000xx -# xerror: -# output: ce11d0c\n -# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n -# output: program stopped with signal 11 (*).\n - -; Check that invalid access to the simulator area is recognized. -; "PASS" area. - - .include "testutils.inc" - start - move.d 0x0ce11d0c,$r3 - dumpr3 - move.d 0x90000004,$acr - clear.d [$acr] - move.d 0xbadc0de,$r3 - dumpr3 -0: - ba 0b - nop diff --git a/sim/testsuite/sim/cris/asm/io8.ms b/sim/testsuite/sim/cris/asm/io8.ms deleted file mode 100644 index 49163fd..0000000 --- a/sim/testsuite/sim/cris/asm/io8.ms +++ /dev/null @@ -1,21 +0,0 @@ -# mach: crisv32 -# ld: --section-start=.text=0 -# xerror: -# output: b1e\n -# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n -# output: program stopped with signal 11 (*).\n - -; Check invalid access valid with --cris-900000xx. -; "FAIL" area. - - .include "testutils.inc" - start - move.d 0xb1e,$r3 - dumpr3 - move.d 0x90000008,$acr - move.d $acr,[$acr] - move.d 0xbadc0de,$r3 - dumpr3 -0: - ba 0b - nop diff --git a/sim/testsuite/sim/cris/asm/io9.ms b/sim/testsuite/sim/cris/asm/io9.ms deleted file mode 100644 index 3b929a3..0000000 --- a/sim/testsuite/sim/cris/asm/io9.ms +++ /dev/null @@ -1,21 +0,0 @@ -# mach: crisv32 -# ld: --section-start=.text=0 -# xerror: -# output: ce11d0c\n -# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n -# output: program stopped with signal 11 (*).\n - -; Check invalid access valid with --cris-900000xx. -; "PASS" area. - - .include "testutils.inc" - start - move.d 0x0ce11d0c,$r3 - dumpr3 - move.d 0x90000004,$acr - move.d $acr,[$acr] - move.d 0xbadc0de,$r3 - dumpr3 -0: - ba 0b - nop diff --git a/sim/testsuite/sim/cris/asm/jsr.ms b/sim/testsuite/sim/cris/asm/jsr.ms deleted file mode 100644 index c684fd3..0000000 --- a/sim/testsuite/sim/cris/asm/jsr.ms +++ /dev/null @@ -1,86 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: 0\n0\n0\n0\n0\n0\n - -# Test that jsr Rn and jsr [PC+] work. - - .include "testutils.inc" - start -x: - move.d 0f,r6 - setf nzvc - jsr r6 - .if ..asm.arch.cris.v32 - nop - .endif -0: - test_move_cc 1 1 1 1 - move srp,r3 - sub.d 0b,r3 - dumpr3 - - move.d 1f,r0 - setf nzvc - jsr r0 - .if ..asm.arch.cris.v32 - moveq 0,r0 - .endif -6: - nop - quit - -2: - test_move_cc 0 0 0 0 - move srp,r3 - sub.d 3f,r3 - dumpr3 - jsr 4f - .if ..asm.arch.cris.v32 - nop - .endif -7: - nop - quit - -; Can't use local label 8 or 9, as they're used by test_move_cc. -y: - move srp,r3 - sub.d 7b,r3 - dumpr3 - quit - -4: - move srp,r3 - sub.d 7b,r3 - dumpr3 - move.d 5f,r3 - jump r3 - .if ..asm.arch.cris.v32 - moveq 0,r3 - .endif - quit - - .space 32770,0 -1: - test_move_cc 1 1 1 1 - move srp,r3 - sub.d 6b,r3 - dumpr3 - - clearf cznv - jsr 2b - .if ..asm.arch.cris.v32 - nop - .endif -3: - - quit - -5: - move srp,r3 - sub.d 7b,r3 - dumpr3 - jump y - .if ..asm.arch.cris.v32 - nop - .endif - quit diff --git a/sim/testsuite/sim/cris/asm/jsrmv10.ms b/sim/testsuite/sim/cris/asm/jsrmv10.ms deleted file mode 100644 index fa9af06..0000000 --- a/sim/testsuite/sim/cris/asm/jsrmv10.ms +++ /dev/null @@ -1,40 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# output: 23\n - -# Test that jsr [] records the correct return-address. - - .include "testutils.inc" - start -x: - moveq 0,r3 - jsr [z] - addq 1,r3 - nop - nop - nop - nop - nop - move.d w,r2 - jsr [r2] - addq 1,r3 - nop - nop - nop - nop - nop - dumpr3 ; 23 - quit -y: - ret - addq 1,r3 - quit - -v: - ret - addq 32,r3 - quit - -z: - .dword y -w: - .dword v diff --git a/sim/testsuite/sim/cris/asm/jumpmp.ms b/sim/testsuite/sim/cris/asm/jumpmp.ms deleted file mode 100644 index dd21e9c..0000000 --- a/sim/testsuite/sim/cris/asm/jumpmp.ms +++ /dev/null @@ -1,21 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# output: bed0bed1\n - -# Test that jump indirect clears the "prefixed" -# bit. - - .include "testutils.inc" - .data -w: - .dword x1 -y: - .dword 0xbed0bed1 - - start -x: - move.d y,r3 - jump [w] -x1: - move.d [r3],r3 - dumpr3 ; bed0bed1 - quit diff --git a/sim/testsuite/sim/cris/asm/jumppv32.ms b/sim/testsuite/sim/cris/asm/jumppv32.ms deleted file mode 100644 index c37f42d..0000000 --- a/sim/testsuite/sim/cris/asm/jumppv32.ms +++ /dev/null @@ -1,28 +0,0 @@ -# mach: crisv32 -# output: 2222\n - -# Test that jump Pd works. - - .include "testutils.inc" - start -x: - setf zvnc - move 0f,srp - test_cc 1 1 1 1 - jump srp - nop - quit - -0: - test_cc 1 1 1 1 - move 1f,mof - jump mof - nop - quit - - .space 32768,0 - quit -1: - move.d 0x2222,r3 - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/lapc.ms b/sim/testsuite/sim/cris/asm/lapc.ms deleted file mode 100644 index bacd881..0000000 --- a/sim/testsuite/sim/cris/asm/lapc.ms +++ /dev/null @@ -1,78 +0,0 @@ -# mach: crisv32 -# output: 0\n0\nfffffffa\nfffffffe\nffffffda\n1e\n1e\n0\n - - .include "testutils.inc" - -; To accommodate dumpr3 with more than one instruction, keep it -; out of lapc operand ranges and difference calculations. - - start - lapc.d 0f,r3 -0: - sub.d .,r3 - dumpr3 ; 0 - - lapcq 0f,r3 -0: - sub.d .,r3 - dumpr3 ; 0 - - lapc.d .,r3 - sub.d .,r3 - dumpr3 ; fffffffa - - lapcq .,r3 - sub.d .,r3 - dumpr3 ; fffffffe - -0: - .rept 16 - nop - .endr - lapc.d 0b,r3 - sub.d .,r3 - dumpr3 ; ffffffda - - setf zcvn - lapc.d 0f,r3 - test_cc 1 1 1 1 - sub.d .,r3 - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop -0: - dumpr3 ; 1e -0: - lapcq 0f,r3 - sub.d 0b,r3 - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop -0: - dumpr3 ; 1e - clearf cn - setf zv -1: - lapcq .,r3 - test_cc 0 1 1 0 - sub.d 1b,r3 - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/lsl.ms b/sim/testsuite/sim/cris/asm/lsl.ms deleted file mode 100644 index a2658b8..0000000 --- a/sim/testsuite/sim/cris/asm/lsl.ms +++ /dev/null @@ -1,217 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: ffffffff\n4\n80000000\nffff8000\n7f19f000\n80000000\n0\n0\n699fc67c\nffffffff\n4\n80000000\nffff8000\n7f19f000\nda670000\nda670000\nda670000\nda67c67c\nffffffff\nfffafffe\n4\nffff0000\nffff8000\n5a67f000\nda67f100\nda67f100\nda67f100\nda67f17c\nfff3faff\nfff3fafe\n4\nffffff00\nffffff00\nffffff80\n5a67f100\n5a67f1f0\n - - .include "testutils.inc" - start - moveq -1,r3 - lslq 0,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - lslq 1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 4 - - moveq -1,r3 - lslq 31,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 80000000 - - moveq -1,r3 - lslq 15,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffff8000 - - move.d 0x5a67f19f,r3 - lslq 12,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 7f19f000 - - move.d 0xda67f19f,r3 - move.d 31,r4 - lsl.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 80000000 - - move.d 0xda67f19f,r3 - move.d 32,r4 - lsl.d r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0xda67f19f,r3 - move.d 33,r4 - lsl.d r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0xda67f19f,r3 - move.d 66,r4 - lsl.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 699fc67c - - moveq -1,r3 - moveq 0,r4 - lsl.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - moveq 1,r4 - lsl.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 4 - - moveq -1,r3 - moveq 31,r4 - lsl.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 80000000 - - moveq -1,r3 - moveq 15,r4 - lsl.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffff8000 - - move.d 0x5a67f19f,r3 - moveq 12,r4 - lsl.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 7f19f000 - - move.d 0xda67f19f,r3 - move.d 31,r4 - lsl.w r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; da670000 - - move.d 0xda67f19f,r3 - move.d 32,r4 - lsl.w r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; da670000 - - move.d 0xda67f19f,r3 - move.d 33,r4 - lsl.w r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; da670000 - - move.d 0xda67f19f,r3 - move.d 66,r4 - lsl.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; da67c67c - - moveq -1,r3 - moveq 0,r4 - lsl.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0xfffaffff,r3 - moveq 1,r4 - lsl.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fffafffe - - moveq 2,r3 - moveq 1,r4 - lsl.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 4 - - moveq -1,r3 - moveq 31,r4 - lsl.w r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; ffff0000 - - moveq -1,r3 - moveq 15,r4 - lsl.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffff8000 - - move.d 0x5a67f19f,r3 - moveq 12,r4 - lsl.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 5a67f000 - - move.d 0xda67f19f,r3 - move.d 31,r4 - lsl.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; da67f100 - - move.d 0xda67f19f,r3 - move.d 32,r4 - lsl.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; da67f100 - - move.d 0xda67f19f,r3 - move.d 33,r4 - lsl.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; da67f100 - - move.d 0xda67f19f,r3 - move.d 66,r4 - lsl.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; da67f17c - - move.d 0xfff3faff,r3 - moveq 0,r4 - lsl.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fff3faff - - move.d 0xfff3faff,r3 - moveq 1,r4 - lsl.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fff3fafe - - moveq 2,r3 - moveq 1,r4 - lsl.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 4 - - moveq -1,r3 - moveq 31,r4 - lsl.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; ffffff00 - - moveq -1,r3 - moveq 15,r4 - lsl.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; ffffff00 - - moveq -1,r3 - moveq 7,r4 - lsl.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffff80 - - move.d 0x5a67f19f,r3 - moveq 12,r4 - lsl.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 5a67f100 - - move.d 0x5a67f19f,r3 - moveq 4,r4 - lsl.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 5a67f1f0 - - quit diff --git a/sim/testsuite/sim/cris/asm/lsr.ms b/sim/testsuite/sim/cris/asm/lsr.ms deleted file mode 100644 index a7c5d3d..0000000 --- a/sim/testsuite/sim/cris/asm/lsr.ms +++ /dev/null @@ -1,217 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: ffffffff\n1\n1\n1ffff\n5a67f\n1\n0\n0\n3699fc67\nffffffff\n1\n1\n1ffff\n5a67f\nda670000\nda670000\nda670000\nda673c67\nffffffff\nffff7fff\n1\nffff0000\nffff0001\n5a67000f\nda67f100\nda67f100\nda67f100\nda67f127\nffffffff\nffffff7f\n1\nffffff00\nffffff00\nffffff01\n5a67f100\n5a67f109\n - - .include "testutils.inc" - start - moveq -1,r3 - lsrq 0,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - lsrq 1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - moveq -1,r3 - lsrq 31,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - moveq -1,r3 - lsrq 15,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1ffff - - move.d 0x5a67f19f,r3 - lsrq 12,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 5a67f - - move.d 0xda67f19f,r3 - move.d 31,r4 - lsr.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - move.d 0xda67f19f,r3 - move.d 32,r4 - lsr.d r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0xda67f19f,r3 - move.d 33,r4 - lsr.d r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0xda67f19f,r3 - move.d 66,r4 - lsr.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3699fc67 - - moveq -1,r3 - moveq 0,r4 - lsr.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq 2,r3 - moveq 1,r4 - lsr.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - moveq -1,r3 - moveq 31,r4 - lsr.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - moveq -1,r3 - moveq 15,r4 - lsr.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1ffff - - move.d 0x5a67f19f,r3 - moveq 12,r4 - lsr.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 5a67f - - move.d 0xda67f19f,r3 - move.d 31,r4 - lsr.w r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; da670000 - - move.d 0xda67f19f,r3 - move.d 32,r4 - lsr.w r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; da670000 - - move.d 0xda67f19f,r3 - move.d 33,r4 - lsr.w r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; da670000 - - move.d 0xda67f19f,r3 - move.d 66,r4 - lsr.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; da673c67 - - moveq -1,r3 - moveq 0,r4 - lsr.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 1,r4 - lsr.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff7fff - - moveq 2,r3 - moveq 1,r4 - lsr.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - moveq -1,r3 - moveq 31,r4 - lsr.w r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; ffff0000 - - moveq -1,r3 - moveq 15,r4 - lsr.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff0001 - - move.d 0x5a67f19f,r3 - moveq 12,r4 - lsr.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 5a67000f - - move.d 0xda67f19f,r3 - move.d 31,r4 - lsr.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; da67f100 - - move.d 0xda67f19f,r3 - move.d 32,r4 - lsr.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; da67f100 - - move.d 0xda67f19f,r3 - move.d 33,r4 - lsr.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; da67f100 - - move.d 0xda67f19f,r3 - move.d 66,r4 - lsr.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; da67f127 - - moveq -1,r3 - moveq 0,r4 - lsr.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 1,r4 - lsr.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffffff7f - - moveq 2,r3 - moveq 1,r4 - lsr.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - moveq -1,r3 - moveq 31,r4 - lsr.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; ffffff00 - - moveq -1,r3 - moveq 15,r4 - lsr.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; ffffff00 - - moveq -1,r3 - moveq 7,r4 - lsr.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffffff01 - - move.d 0x5a67f19f,r3 - moveq 12,r4 - lsr.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 5a67f100 - - move.d 0x5a67f19f,r3 - moveq 4,r4 - lsr.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 5a67f109 - - quit diff --git a/sim/testsuite/sim/cris/asm/lz.ms b/sim/testsuite/sim/cris/asm/lz.ms deleted file mode 100644 index 8a4bb3c..0000000 --- a/sim/testsuite/sim/cris/asm/lz.ms +++ /dev/null @@ -1,52 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 0\n20\n0\n1\n1\n1a\n1f\n10\n1e\n - - .include "testutils.inc" - start - moveq -1,r3 - - lz r3,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - moveq 0,r3 - lz r3,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 20 - - move.d 0x80000000,r4 - lz r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x40000000,r4 - lz r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - move.d 0x7fffffff,r4 - lz r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1 - - move.d 42,r3 - lz r3,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1a - - moveq 1,r6 - lz r6,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1f - - move.d 0xffff,r3 - lz r3,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 10 - - moveq 2,r5 - lz r5,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1e - - quit diff --git a/sim/testsuite/sim/cris/asm/mcp.ms b/sim/testsuite/sim/cris/asm/mcp.ms deleted file mode 100644 index 9aee39c..0000000 --- a/sim/testsuite/sim/cris/asm/mcp.ms +++ /dev/null @@ -1,49 +0,0 @@ -# mach: crisv32 -# output: fffffffe\n1\n1ffff\nfffffffe\ncc463bdc\n4c463bdc\n0\n - - .include "testutils.inc" - start - -; Set R, clear C. - move 0x100,ccs - moveq -5,r3 - move 2,mof - mcp mof,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - - moveq 2,r3 - move -1,srp - mcp srp,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - move 0xffff,srp - move srp,r3 - mcp srp,r3 - test_cc 0 0 0 0 - dumpr3 ; 1ffff - - move -1,mof - move mof,r3 - mcp mof,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - - move 0x5432f789,mof - move.d 0x78134452,r3 - mcp mof,r3 - test_cc 1 0 1 0 - dumpr3 ; cc463bdc - - move 0x80000000,srp - mcp srp,r3 - test_cc 0 0 1 0 - dumpr3 ; 4c463bdc - - move 0xb3b9c423,srp - mcp srp,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/movdelsr1.ms b/sim/testsuite/sim/cris/asm/movdelsr1.ms deleted file mode 100644 index fe33d67..0000000 --- a/sim/testsuite/sim/cris/asm/movdelsr1.ms +++ /dev/null @@ -1,33 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: aa117acd\n -# output: eeaabb42\n - -; Bug with move to special register in delay slot, due to -; special flush-insn-cache simulator use. Ordinary move worked; -; special register caused branch to fail. - - .include "testutils.inc" - start - move -1,srp - - move.d 0xaa117acd,r1 - moveq 3,r9 - cmpq 1,r9 - bhi 0f - move.d r1,r3 - - fail -0: - dumpr3 - - move.d 0xeeaabb42,r1 - moveq 3,r9 - cmpq 1,r9 - bhi 0f - move r1,srp - - fail -0: - move srp,r3 - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/movecpc.ms b/sim/testsuite/sim/cris/asm/movecpc.ms deleted file mode 100644 index 880a0f8..0000000 --- a/sim/testsuite/sim/cris/asm/movecpc.ms +++ /dev/null @@ -1,19 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register * PC is not implemented.\nprogram stopped with signal 5 (*).\n - -# We deliberately match both "read from" and "write to" above. - - .include "testutils.inc" - startnostack - moveq -1,r3 - move.b 0x42,pc - dumpr3 - - move.w 0x4321,pc - dumpr3 - - move.d 0x76543210,pc - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movecr.ms b/sim/testsuite/sim/cris/asm/movecr.ms deleted file mode 100644 index 01bf7f0..0000000 --- a/sim/testsuite/sim/cris/asm/movecr.ms +++ /dev/null @@ -1,37 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n - -; Move constant byte, word, dword to register. Check that no extension is -; performed, that only part of the register is set. - - .include "testutils.inc" - startnostack - moveq -1,r3 - move.b 0x42,r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq 0,r3 - move.b 0x94,r3 - test_move_cc 1 0 0 0 - dumpr3 - - moveq -1,r3 - move.w 0x4321,r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq 0,r3 - move.w 0x9234,r3 - test_move_cc 1 0 0 0 - dumpr3 - - move.d 0x76543210,r3 - test_move_cc 0 0 0 0 - dumpr3 - - move.w 0,r3 - test_move_cc 0 1 0 0 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movecrt10.ms b/sim/testsuite/sim/cris/asm/movecrt10.ms deleted file mode 100644 index d965bbc..0000000 --- a/sim/testsuite/sim/cris/asm/movecrt10.ms +++ /dev/null @@ -1,17 +0,0 @@ -#mach: crisv10 -#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n -#output: Basic clock cycles, total @: 82\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "movecr.ms" - -# This test-case is accidentally the same; gets the same cycle -# count as movecrt32.ms, but please keep them separate. diff --git a/sim/testsuite/sim/cris/asm/movecrt32.ms b/sim/testsuite/sim/cris/asm/movecrt32.ms deleted file mode 100644 index 75833a4..0000000 --- a/sim/testsuite/sim/cris/asm/movecrt32.ms +++ /dev/null @@ -1,14 +0,0 @@ -#mach: crisv32 -#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n -#output: Basic clock cycles, total @: 82\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "movecr.ms" diff --git a/sim/testsuite/sim/cris/asm/movect10.ms b/sim/testsuite/sim/cris/asm/movect10.ms deleted file mode 100644 index f1e3229e..0000000 --- a/sim/testsuite/sim/cris/asm/movect10.ms +++ /dev/null @@ -1,18 +0,0 @@ -#mach: crisv10 -#output: Basic clock cycles, total @: 3\n -#output: Memory source stall cycles: 1\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - - .include "testutils.inc" - startnostack - nop - move.d 0xff004567,r5 - break 15 diff --git a/sim/testsuite/sim/cris/asm/movei.ms b/sim/testsuite/sim/cris/asm/movei.ms deleted file mode 100644 index 8d55ae1..0000000 --- a/sim/testsuite/sim/cris/asm/movei.ms +++ /dev/null @@ -1,47 +0,0 @@ -# mach: crisv32 -# output: fffffffe\n -# output: fffffffe\n - -; Check basic integral-write semantics regarding flags. - - .include "testutils.inc" - start - -; A write that works. Check that flags are set correspondingly. - move.d d,r4 - moveq -2,r5 - setf c - clearf p - move.d [r4],r3 - ax - move.d r5,[r4] - move.d [r4],r3 - - bcc 0f - nop - fail - -0: - dumpr3 ; fffffffe - -; A write that fails; check flags too. - move.d d,r4 - moveq 23,r5 - setf p - clearf c - move.d [r4],r3 - ax - move.d r5,[r4] - move.d [r4],r3 - - bcs 0f - nop - fail - -0: - dumpr3 ; fffffffe - quit - - .data -d: - .dword 42424242 diff --git a/sim/testsuite/sim/cris/asm/movempc.ms b/sim/testsuite/sim/cris/asm/movempc.ms deleted file mode 100644 index cbbfcc1..0000000 --- a/sim/testsuite/sim/cris/asm/movempc.ms +++ /dev/null @@ -1,8 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - move.d _start,r12 - move.d [r12],pc diff --git a/sim/testsuite/sim/cris/asm/movemr.ms b/sim/testsuite/sim/cris/asm/movemr.ms deleted file mode 100644 index 02f0085..0000000 --- a/sim/testsuite/sim/cris/asm/movemr.ms +++ /dev/null @@ -1,79 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: 12345678\n10234567\n12345678\n12344567\n12344523\n76543210\nffffffaa\naa\n9911\nffff9911\n78\n56\n3456\n6712\n - - .include "testutils.inc" - start - - .data -mem1: - .dword 0x12345678 -mem2: - .word 0x4567 -mem3: - .byte 0x23 - .dword 0x76543210 - .byte 0xaa,0x11,0x99 - - .text - move.d mem1,r2 - move.d [r2],r3 - test_move_cc 0 0 0 0 - dumpr3 - - move.d mem2,r3 - move.d [r3],r3 - test_move_cc 0 0 0 0 - dumpr3 - - move.d mem1,r2 - move.d [r2+],r3 - test_move_cc 0 0 0 0 - dumpr3 - - move.w [r2+],r3 - test_move_cc 0 0 0 0 - dumpr3 - - move.b [r2+],r3 - test_move_cc 0 0 0 0 - dumpr3 - - move.d [r2+],r3 - test_move_cc 0 0 0 0 - dumpr3 - - movs.b [r2],r3 - test_move_cc 1 0 0 0 - dumpr3 - - movu.b [r2+],r3 - test_move_cc 0 0 0 0 - dumpr3 - - movu.w [r2],r3 - test_move_cc 0 0 0 0 - dumpr3 - - movs.w [r2+],r3 - test_move_cc 1 0 0 0 - dumpr3 - - move.d mem1,r13 - movs.b [r13+],r3 - test_move_cc 0 0 0 0 - dumpr3 - - movu.b [r13],r3 - test_move_cc 0 0 0 0 - dumpr3 - - movs.w [r13+],r3 - test_move_cc 0 0 0 0 - dumpr3 - - movu.w [r13+],r3 - test_move_cc 0 0 0 0 - dumpr3 - - quit - diff --git a/sim/testsuite/sim/cris/asm/movemrv10.ms b/sim/testsuite/sim/cris/asm/movemrv10.ms deleted file mode 100644 index 9fbb878..0000000 --- a/sim/testsuite/sim/cris/asm/movemrv10.ms +++ /dev/null @@ -1,101 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 -# output: 15\nffff1234\n2\n7\nb\n16\nf\n2\nf\nffffffef\n7\nfffffff4\nf\nfffffff2\nd\n10\nfffffff2\n8\nfffffff4\n - - .include "testutils.inc" - .data -x: - .dword 8,9,10,11 -y: - .dword -12,13,-14,15,16 - - start - moveq 7,r0 - moveq 2,r1 - move.d 0xffff1234,r2 - moveq 21,r3 - move.d x,r4 - setf zcvn - movem r2,[r4+] - test_cc 1 1 1 1 - subq 12,r4 - - dumpr3 ; 15 - - move.d [r4+],r3 - dumpr3 ; ffff1234 - - move.d [r4+],r3 - dumpr3 ; 2 - - move.d [r4+],r3 - dumpr3 ; 7 - - move.d [r4+],r3 - dumpr3 ; b - - subq 16,r4 - moveq 22,r0 - moveq 15,r1 - clearf zcvn - movem r0,[r4] - test_cc 0 0 0 0 - move.d [r4+],r3 - dumpr3 ; 16 - - move.d r1,r3 - dumpr3 ; f - - move.d [r4+],r3 - dumpr3 ; 2 - - moveq 10,r2 - moveq -17,r0 - clearf zc - setf vn - movem r1,[r4=r4-8] - test_cc 1 0 1 0 - move.d [r4+],r3 - dumpr3 ; f - - move.d [r4+],r3 - dumpr3 ; ffffffef - - move.d [r4+],r3 - dumpr3 ; 7 - - move.d y,r4 - setf zc - clearf vn - movem [r4+],r3 - test_cc 0 1 0 1 - dumpr3 ; fffffff4 - - move.d r0,r3 - dumpr3 ; f - - move.d r1,r3 - dumpr3 ; fffffff2 - - moveq -12,r1 - - move.d r2,r3 - dumpr3 ; d - - move.d [r4],r3 - dumpr3 ; 10 - - setf zcvn - movem [r5=r4-8],r0 - test_cc 1 1 1 1 - move.d r0,r3 - dumpr3 ; fffffff2 - - sub.d r5,r4 - move.d r4,r3 - dumpr3 ; 8 - - move.d r1,r3 - dumpr3 ; fffffff4 - - quit - diff --git a/sim/testsuite/sim/cris/asm/movemrv32.ms b/sim/testsuite/sim/cris/asm/movemrv32.ms deleted file mode 100644 index 15fcd4c..0000000 --- a/sim/testsuite/sim/cris/asm/movemrv32.ms +++ /dev/null @@ -1,97 +0,0 @@ -# mach: crisv32 -# output: 15\n7\n2\nffff1234\nb\n16\nf\n2\nffffffef\nf\nffff1234\nf\nfffffff4\nd\nfffffff2\n10\nfffffff2\nd\n - - .include "testutils.inc" - .data -x: - .dword 8,9,10,11 -y: - .dword -12,13,-14,15,16 - - start - moveq 7,r0 - moveq 2,r1 - move.d 0xffff1234,r2 - moveq 21,r3 - move.d x,r4 - setf zcvn - movem r2,[r4+] - test_cc 1 1 1 1 - subq 12,r4 - - dumpr3 ; 15 - - move.d [r4+],r3 - dumpr3 ; 7 - - move.d [r4+],r3 - dumpr3 ; 2 - - move.d [r4+],r3 - dumpr3 ; ffff1234 - - move.d [r4+],r3 - dumpr3 ; b - - subq 16,r4 - moveq 22,r0 - moveq 15,r1 - clearf zcvn - movem r0,[r4] - test_cc 0 0 0 0 - move.d [r4+],r3 - dumpr3 ; 16 - - move.d r1,r3 - dumpr3 ; f - - move.d [r4+],r3 - dumpr3 ; 2 - - subq 8,r4 - moveq 10,r2 - moveq -17,r0 - clearf zc - setf vn - movem r1,[r4] - test_cc 1 0 1 0 - move.d [r4+],r3 - dumpr3 ; ffffffef - - move.d [r4+],r3 - dumpr3 ; f - - move.d [r4+],r3 - dumpr3 ; ffff1234 - - move.d y,r4 - setf zc - clearf vn - movem [r4+],r3 - test_cc 0 1 0 1 - dumpr3 ; f - - move.d r0,r3 - dumpr3 ; fffffff4 - - move.d r1,r3 - dumpr3 ; d - - move.d r2,r3 - dumpr3 ; fffffff2 - - move.d [r4],r3 - dumpr3 ; 10 - - subq 8,r4 - setf zcvn - movem [r4+],r0 - test_cc 1 1 1 1 - move.d r0,r3 - dumpr3 ; fffffff2 - - move.d r1,r3 - dumpr3 ; d - - quit - diff --git a/sim/testsuite/sim/cris/asm/movepcb.ms b/sim/testsuite/sim/cris/asm/movepcb.ms deleted file mode 100644 index b06932e..0000000 --- a/sim/testsuite/sim/cris/asm/movepcb.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - startnostack - setf - test.b pc - quit diff --git a/sim/testsuite/sim/cris/asm/movepcd.ms b/sim/testsuite/sim/cris/asm/movepcd.ms deleted file mode 100644 index 2ed0060..0000000 --- a/sim/testsuite/sim/cris/asm/movepcd.ms +++ /dev/null @@ -1,16 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register * PC is not implemented.\nprogram stopped with signal 5 (*).\n - -# Both source and dest contain PC for "test.d r" (move.d r,r). Ideally, -# the output message should say "read" of PC, but we allow PC as source in -# a move.d r,R insn, so there's no logical way to get that, short of a -# special pattern, which would be just too ugly. The output message says -# "write", but let's match "read" too so we won't fail if things suddenly -# improve. - - .include "testutils.inc" - startnostack - setf - test.d pc - quit diff --git a/sim/testsuite/sim/cris/asm/movepcw.ms b/sim/testsuite/sim/cris/asm/movepcw.ms deleted file mode 100644 index 0f3b6a2..0000000 --- a/sim/testsuite/sim/cris/asm/movepcw.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - startnostack - setf - test.w pc - quit diff --git a/sim/testsuite/sim/cris/asm/moveq.ms b/sim/testsuite/sim/cris/asm/moveq.ms deleted file mode 100644 index 121cbda..0000000 --- a/sim/testsuite/sim/cris/asm/moveq.ms +++ /dev/null @@ -1,15 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# sim: --trace-core=on -# ld: --section-start=.text=0 -# output: read-2 exec:0x00000002 -> 0x3262\nread-2 exec:0x00000004 -> 0xe93e\nffffffe2\nread-2 exec:0x00000006 -> 0x324d\nread-2 exec:0x00000008 -> 0xe93e\nd\nread-2 exec:0x0000000a -> 0xe93f\n - -; Output a positive and a negative number, set from moveq. - - .include "testutils.inc" - startnostack - moveq -30,r3 - dumpr3 - moveq 13,r3 - dumpr3 - quit - diff --git a/sim/testsuite/sim/cris/asm/moveqpc.ms b/sim/testsuite/sim/cris/asm/moveqpc.ms deleted file mode 100644 index d5e856b..0000000 --- a/sim/testsuite/sim/cris/asm/moveqpc.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - startnostack - setf - moveq -30,pc - quit diff --git a/sim/testsuite/sim/cris/asm/mover.ms b/sim/testsuite/sim/cris/asm/mover.ms deleted file mode 100644 index 41a6474..0000000 --- a/sim/testsuite/sim/cris/asm/mover.ms +++ /dev/null @@ -1,29 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: ffffff05\nffff0005\n5\nffffff00\n - -; Move between registers. Check that just the subreg is copied. - - .include "testutils.inc" - startnostack - moveq -30,r3 - moveq 5,r4 - move.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 - - move.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 - - move.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq -1,r3 - moveq 0,r4 - move.b r4,r3 - test_move_cc 0 1 0 0 - dumpr3 - - quit - diff --git a/sim/testsuite/sim/cris/asm/moverbpc.ms b/sim/testsuite/sim/cris/asm/moverbpc.ms deleted file mode 100644 index b5ea388..0000000 --- a/sim/testsuite/sim/cris/asm/moverbpc.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - startnostack - setf - move.d r5,pc - quit diff --git a/sim/testsuite/sim/cris/asm/moverdpc.ms b/sim/testsuite/sim/cris/asm/moverdpc.ms deleted file mode 100644 index b5ea388..0000000 --- a/sim/testsuite/sim/cris/asm/moverdpc.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - startnostack - setf - move.d r5,pc - quit diff --git a/sim/testsuite/sim/cris/asm/moverm.ms b/sim/testsuite/sim/cris/asm/moverm.ms deleted file mode 100644 index be8126f..0000000 --- a/sim/testsuite/sim/cris/asm/moverm.ms +++ /dev/null @@ -1,45 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: 7823fec2\n10231879\n102318fe\n - - .include "testutils.inc" - start - - .data -mem1: - .dword 0x12345678 -mem2: - .word 0x4567 -mem3: - .byte 0x23 - .dword 0x76543210 - .byte 0xaa,0x11,0x99 - - .text - move.d mem1,r2 - move.d 0x7823fec2,r4 - setf nzvc - move.d r4,[r2+] - test_cc 1 1 1 1 - subq 4,r2 - move.d [r2],r3 - dumpr3 ; 7823fec2 - - move.d mem2,r3 - move.d 0x45231879,r4 - clearf nzvc - move.w r4,[r3] - test_cc 0 0 0 0 - move.d [r3],r3 - dumpr3 ; 10231879 - - move.d mem2,r2 - moveq -2,r4 - clearf nc - setf zv - move.b r4,[r2+] - test_cc 0 1 1 0 - subq 1,r2 - move.d [r2],r3 - dumpr3 ; 102318ff - - quit diff --git a/sim/testsuite/sim/cris/asm/moverpcb.ms b/sim/testsuite/sim/cris/asm/moverpcb.ms deleted file mode 100644 index 13e04b1..0000000 --- a/sim/testsuite/sim/cris/asm/moverpcb.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - startnostack - setf - move.b pc,r5 - quit diff --git a/sim/testsuite/sim/cris/asm/moverpcd.ms b/sim/testsuite/sim/cris/asm/moverpcd.ms deleted file mode 100644 index b7a54ea..0000000 --- a/sim/testsuite/sim/cris/asm/moverpcd.ms +++ /dev/null @@ -1,13 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# output: 4\n - -# Test that move.d pc,R works. - - .include "testutils.inc" - start -x: - move.d pc,r3 -y: - sub.d y-4,r3 - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/moverpcw.ms b/sim/testsuite/sim/cris/asm/moverpcw.ms deleted file mode 100644 index 9b8f929..0000000 --- a/sim/testsuite/sim/cris/asm/moverpcw.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - startnostack - setf - move.w pc,r2 - quit diff --git a/sim/testsuite/sim/cris/asm/moverwpc.ms b/sim/testsuite/sim/cris/asm/moverwpc.ms deleted file mode 100644 index b5ea388..0000000 --- a/sim/testsuite/sim/cris/asm/moverwpc.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - startnostack - setf - move.d r5,pc - quit diff --git a/sim/testsuite/sim/cris/asm/movesmp.ms b/sim/testsuite/sim/cris/asm/movesmp.ms deleted file mode 100644 index a85dfc8..0000000 --- a/sim/testsuite/sim/cris/asm/movesmp.ms +++ /dev/null @@ -1,28 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# output: bed0bed1\nabedab0d\nbed0bed1\n - -# Test that move to and from special register and memory clears the -# "prefixed" bit. - - .include "testutils.inc" - .data -w: - .dword 0 -y: - .dword 0xbed0bed1 -z: - .dword 0xabedab0d - - start -x: - move.d y,r3 - clear.d [w] - move.d [r3],r3 - dumpr3 ; bed0bed1 - move.d z,r3 - move [w+4],srp - move.d [r3],r3 - dumpr3 ; abedab0d - move srp,r3 - dumpr3 ; bed0bed1 - quit diff --git a/sim/testsuite/sim/cris/asm/movmp.ms b/sim/testsuite/sim/cris/asm/movmp.ms deleted file mode 100644 index d864692..0000000 --- a/sim/testsuite/sim/cris/asm/movmp.ms +++ /dev/null @@ -1,127 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: ffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nbb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n - -# Test generic "move Ps,[]" and "move [],Pd" insns; the ones with -# functionality common to all models. - - .include "testutils.inc" - start - - .data -filler: - .byte 0xaa - .word 0x4433 - .dword 0x55778866 - .byte 0xcc - - .text -; Test that writing to zero-registers is a nop - .if 0 - ; We used to just ignore the writes, but now an error is emitted. We - ; keep the test-code but disabled, in case we need to change this again. - move 0xaa,p0 - move 0x4433,p4 - move 0x55774433,p8 - .endif - - moveq -1,r3 - setf zcvn - clear.b r3 - test_cc 1 1 1 1 - dumpr3 - - moveq -1,r3 - clearf zcvn - clear.w r3 - test_cc 0 0 0 0 - dumpr3 - - moveq -1,r3 - clear.d r3 - dumpr3 - -; "Write" using ordinary memory references too. - .if 0 ; See ".if 0" above. - move.d filler,r6 - move [r6],p0 - move [r6],p4 - move [r6],p8 - .endif - - moveq -1,r3 - clear.b r3 - dumpr3 - - moveq -1,r3 - clear.w r3 - dumpr3 - - moveq -1,r3 - clear.d r3 - dumpr3 - -; And postincremented. - .if 0 ; See ".if 0" above. - move [r6+],p0 - move [r6+],p4 - move [r6+],p8 - .endif - - moveq -1,r3 - clear.b r3 - dumpr3 - - moveq -1,r3 - clear.w r3 - dumpr3 - - moveq -1,r3 - clear.d r3 - dumpr3 - -; Now see that we can write to the registers too. - -; [PC+] - move.d filler,r9 - move 0xbb113344,srp - move srp,r3 - dumpr3 - -; [R+] - move [r9+],srp - move srp,r3 - dumpr3 - -; [R] - move [r9],srp - move srp,r3 - dumpr3 - -; And check writing to memory, clear and srp. - - move.d filler,r9 - move 0xabcde012,srp - setf zcvn - move srp,[r9+] - test_cc 1 1 1 1 - subq 4,r9 - move.d [r9],r3 - dumpr3 - - clearf zcvn - clear.b [r9] - test_cc 0 0 0 0 - move.d [r9],r3 - dumpr3 - - addq 2,r9 - clear.w [r9+] - subq 2,r9 - move.d [r9],r3 - dumpr3 - - clear.d [r9] - move.d [r9],r3 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movmp8.ms b/sim/testsuite/sim/cris/asm/movmp8.ms deleted file mode 100644 index ffb3854..0000000 --- a/sim/testsuite/sim/cris/asm/movmp8.ms +++ /dev/null @@ -1,33 +0,0 @@ -# mach: crisv3 crisv8 crisv10 - -# Make sure that "move [$sp=$sp+16],$p8" works; used in Linux. - - .include "testutils.inc" - startnostack - move.d x,$sp - moveq 0,$r3 - move [$sp=$sp+16],$p8 - ; Z not changed. - bne 0f - nop - cmp.d x+16,$sp - bne 0f - nop - move $p8,$r3 - ; Z not changed. - bne 0f - ; P8 still 0. - test.d $r3 - bne 0f - nop - pass -0: - fail - - .data -x: - .dword 0xffffffff - .dword 0xffffffff - .dword 0xffffffff - .dword 0xffffffff - .dword 0xffffffff diff --git a/sim/testsuite/sim/cris/asm/movpmv10.ms b/sim/testsuite/sim/cris/asm/movpmv10.ms deleted file mode 100644 index 72dcee7..0000000 --- a/sim/testsuite/sim/cris/asm/movpmv10.ms +++ /dev/null @@ -1,35 +0,0 @@ -# mach: crisv10 -# output: 1122330a\nbb113344\naa557711\n - -# Test v10-specific special registers. FIXME: ccr, irp, bar, brp, usp. - - .include "testutils.inc" - start - .data -store: - .dword 0x11223344 - .dword 0x77665544 - - .text - moveq -1,r3 - move.d store,r4 - clearf zcvn - move vr,[r4] - test_cc 0 0 0 0 - move [r4+],mof - move mof,r3 - dumpr3 - - moveq -1,r3 - move 0xbb113344,mof - move mof,r3 - dumpr3 - - move 0xaa557711,mof - setf zcvn - move mof,[r4] - test_cc 1 1 1 1 - move.d [r4],r3 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movpmv32.ms b/sim/testsuite/sim/cris/asm/movpmv32.ms deleted file mode 100644 index 6d17338..0000000 --- a/sim/testsuite/sim/cris/asm/movpmv32.ms +++ /dev/null @@ -1,35 +0,0 @@ -# mach: crisv32 -# output: 11223320\nbb113344\naa557711\n - -# Test v32-specific special registers. FIXME: more registers. - - .include "testutils.inc" - start - .data -store: - .dword 0x11223344 - .dword 0x77665544 - - .text - moveq -1,r3 - move.d store,r4 - move vr,[r4] - move [r4+],mof - move mof,r3 - dumpr3 - - moveq -1,r3 - clearf zcvn - move 0xbb113344,mof - test_cc 0 0 0 0 - move mof,r3 - dumpr3 - - setf zcvn - move 0xaa557711,mof - test_cc 1 1 1 1 - move mof,[r4] - move.d [r4],r3 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movppc.ms b/sim/testsuite/sim/cris/asm/movppc.ms deleted file mode 100644 index ee7e8d1..0000000 --- a/sim/testsuite/sim/cris/asm/movppc.ms +++ /dev/null @@ -1,7 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - move srp,[PC+] diff --git a/sim/testsuite/sim/cris/asm/movpr.ms b/sim/testsuite/sim/cris/asm/movpr.ms deleted file mode 100644 index 4279a73..0000000 --- a/sim/testsuite/sim/cris/asm/movpr.ms +++ /dev/null @@ -1,28 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: ffffff00\nffff0000\n0\nbb113344\n - -# Test generic "move Ps,Rd" and "move Rs,Pd" insns; the ones with -# functionality common to all models. - - .include "testutils.inc" - start - moveq -1,r3 - clear.b r3 - dumpr3 - - moveq -1,r3 - clear.w r3 - dumpr3 - - moveq -1,r3 - clear.d r3 - dumpr3 - - moveq -1,r3 - move.d 0xbb113344,r4 - setf zcvn - move r4,srp - move srp,r3 - test_cc 1 1 1 1 - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/movprv10.ms b/sim/testsuite/sim/cris/asm/movprv10.ms deleted file mode 100644 index 29a10b5..0000000 --- a/sim/testsuite/sim/cris/asm/movprv10.ms +++ /dev/null @@ -1,21 +0,0 @@ -# mach: crisv10 -# output: ffffff0a\nbb113344\n - -# Test v10-specific special registers. FIXME: ccr, irp, bar, brp, usp. - - .include "testutils.inc" - start - moveq -1,r3 - setf zcvn - move vr,r3 - test_cc 1 1 1 1 - dumpr3 - - moveq -1,r3 - move.d 0xbb113344,r4 - clearf zcvn - move r4,mof - move mof,r3 - test_cc 0 0 0 0 - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/movprv32.ms b/sim/testsuite/sim/cris/asm/movprv32.ms deleted file mode 100644 index 5a2f4dd..0000000 --- a/sim/testsuite/sim/cris/asm/movprv32.ms +++ /dev/null @@ -1,21 +0,0 @@ -# mach: crisv32 -# output: ffffff20\nbb113344\n - -# Test v32-specific special registers. FIXME: more registers. - - .include "testutils.inc" - start - moveq -1,r3 - setf zcvn - move vr,r3 - test_cc 1 1 1 1 - dumpr3 - - moveq -1,r3 - move.d 0xbb113344,r4 - clearf cvnz - move r4,mof - test_cc 0 0 0 0 - move mof,r3 - dumpr3 - quit diff --git a/sim/testsuite/sim/cris/asm/movrss.ms b/sim/testsuite/sim/cris/asm/movrss.ms deleted file mode 100644 index 42305f9..0000000 --- a/sim/testsuite/sim/cris/asm/movrss.ms +++ /dev/null @@ -1,8 +0,0 @@ -# mach: crisv32 -# xerror: -# output: Write to support register is unimplemented\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - move R3,S0 - diff --git a/sim/testsuite/sim/cris/asm/movscpc.ms b/sim/testsuite/sim/cris/asm/movscpc.ms deleted file mode 100644 index 9861896..0000000 --- a/sim/testsuite/sim/cris/asm/movscpc.ms +++ /dev/null @@ -1,13 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - movs.b 0x42,pc - dumpr3 - - movs.w 0x4321,pc - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movscr.ms b/sim/testsuite/sim/cris/asm/movscr.ms deleted file mode 100644 index 457cca8..0000000 --- a/sim/testsuite/sim/cris/asm/movscr.ms +++ /dev/null @@ -1,29 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: 42\nffffff85\n7685\nffff8765\n0\n - -; Move constant byte, word, dword to register. Check that sign-extension -; is performed. - - .include "testutils.inc" - start - moveq -1,r3 - movs.b 0x42,r3 - dumpr3 - - movs.b 0x85,r3 - test_move_cc 1 0 0 0 - dumpr3 - - movs.w 0x7685,r3 - test_move_cc 0 0 0 0 - dumpr3 - - movs.w 0x8765,r3 - test_move_cc 1 0 0 0 - dumpr3 - - movs.w 0,r3 - test_move_cc 0 1 0 0 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movsm.ms b/sim/testsuite/sim/cris/asm/movsm.ms deleted file mode 100644 index 59973d1..0000000 --- a/sim/testsuite/sim/cris/asm/movsm.ms +++ /dev/null @@ -1,44 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: 5\nfffffff5\n5\nfffffff5\n0\n - -; Movs between registers. Check that sign-extension is performed and the -; full register is set. - - .include "testutils.inc" - - .data -x: - .byte 5,-11 - .word 5,-11 - .word 0 - - start - move.d x,r5 - - moveq -1,r3 - movs.b [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq 0,r3 - movs.b [r5],r3 - test_move_cc 1 0 0 0 - addq 1,r5 - dumpr3 - - moveq -1,r3 - movs.w [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq 0,r3 - movs.w [r5],r3 - test_move_cc 1 0 0 0 - addq 2,r5 - dumpr3 - - movs.w [r5],r3 - test_move_cc 0 1 0 0 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movsmpc.ms b/sim/testsuite/sim/cris/asm/movsmpc.ms deleted file mode 100644 index 95f40ad..0000000 --- a/sim/testsuite/sim/cris/asm/movsmpc.ms +++ /dev/null @@ -1,8 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - move.d _start,r12 - movs.w [r12],pc diff --git a/sim/testsuite/sim/cris/asm/movsr.ms b/sim/testsuite/sim/cris/asm/movsr.ms deleted file mode 100644 index 283975f..0000000 --- a/sim/testsuite/sim/cris/asm/movsr.ms +++ /dev/null @@ -1,46 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: 5\nfffffff5\n5\nfffffff5\n0\n - -; Movs between registers. Check that sign-extension is performed and the -; full register is set. - - .include "testutils.inc" - start - moveq -1,r5 - moveq 5,r4 - move.b r4,r5 - moveq -1,r3 - movs.b r5,r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq 0,r5 - moveq -11,r4 - move.b r4,r5 - moveq 0,r3 - movs.b r5,r3 - test_move_cc 1 0 0 0 - dumpr3 - - moveq -1,r5 - moveq 5,r4 - move.w r4,r5 - moveq -1,r3 - movs.w r5,r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq 0,r5 - moveq -11,r4 - move.w r4,r5 - moveq 0,r3 - movs.w r5,r3 - test_move_cc 1 0 0 0 - dumpr3 - - moveq 0,r5 - movs.b r5,r3 - test_move_cc 0 1 0 0 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movsrpc.ms b/sim/testsuite/sim/cris/asm/movsrpc.ms deleted file mode 100644 index 6971e37..0000000 --- a/sim/testsuite/sim/cris/asm/movsrpc.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - setf - movs.w r0,pc - quit diff --git a/sim/testsuite/sim/cris/asm/movssr.ms b/sim/testsuite/sim/cris/asm/movssr.ms deleted file mode 100644 index 79e4fbd..0000000 --- a/sim/testsuite/sim/cris/asm/movssr.ms +++ /dev/null @@ -1,8 +0,0 @@ -# mach: crisv32 -# xerror: -# output: Read of support register is unimplemented\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - move S0,R3 - diff --git a/sim/testsuite/sim/cris/asm/movucpc.ms b/sim/testsuite/sim/cris/asm/movucpc.ms deleted file mode 100644 index aec82d1..0000000 --- a/sim/testsuite/sim/cris/asm/movucpc.ms +++ /dev/null @@ -1,10 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - movu.w 0x4321,pc - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movucr.ms b/sim/testsuite/sim/cris/asm/movucr.ms deleted file mode 100644 index 7508ff8..0000000 --- a/sim/testsuite/sim/cris/asm/movucr.ms +++ /dev/null @@ -1,33 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: 42\n85\n7685\n8765\n0\n - -; Move constant byte, word, dword to register. Check that zero-extension -; is performed. - - .include "testutils.inc" - start - moveq -1,r3 - movu.b 0x42,r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq -1,r3 - movu.b 0x85,r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq -1,r3 - movu.w 0x7685,r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq -1,r3 - movu.w 0x8765,r3 - test_move_cc 0 0 0 0 - dumpr3 - - movu.b 0,r3 - test_move_cc 0 1 0 0 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movum.ms b/sim/testsuite/sim/cris/asm/movum.ms deleted file mode 100644 index c6ea625..0000000 --- a/sim/testsuite/sim/cris/asm/movum.ms +++ /dev/null @@ -1,40 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: 5\nf5\n5\nfff5\n0\n - -; Movu between registers. Check that zero-extension is performed and the -; full register is set. - - .include "testutils.inc" - - .data -x: - .byte 5,-11 - .word 5,-11 - .word 0 - - start - move.d x,r5 - - movu.b [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 - - movu.b [r5],r3 - test_move_cc 0 0 0 0 - addq 1,r5 - dumpr3 - - movu.w [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 - - movu.w [r5],r3 - test_move_cc 0 0 0 0 - addq 2,r5 - dumpr3 - - movu.w [r5],r3 - test_move_cc 0 1 0 0 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movumpc.ms b/sim/testsuite/sim/cris/asm/movumpc.ms deleted file mode 100644 index 9bfc492..0000000 --- a/sim/testsuite/sim/cris/asm/movumpc.ms +++ /dev/null @@ -1,8 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - move.d _start,r1 - movu.b [r1+],pc diff --git a/sim/testsuite/sim/cris/asm/movur.ms b/sim/testsuite/sim/cris/asm/movur.ms deleted file mode 100644 index a46d54d..0000000 --- a/sim/testsuite/sim/cris/asm/movur.ms +++ /dev/null @@ -1,45 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: 5\nf5\n5\nfff5\n0\n - -; Movu between registers. Check that zero-extension is performed and the -; full register is set. - - .include "testutils.inc" - start - moveq -1,r5 - moveq 5,r4 - move.b r4,r5 - moveq -1,r3 - movu.b r5,r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq 0,r5 - moveq -11,r4 - move.b r4,r5 - moveq -1,r3 - movu.b r5,r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq -1,r5 - moveq 5,r4 - move.w r4,r5 - moveq -1,r3 - movu.w r5,r3 - test_move_cc 0 0 0 0 - dumpr3 - - moveq 0,r5 - moveq -11,r4 - move.w r4,r5 - moveq -1,r3 - movu.w r5,r3 - test_move_cc 0 0 0 0 - dumpr3 - - movu.w 0,r3 - test_move_cc 0 1 0 0 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/movurpc.ms b/sim/testsuite/sim/cris/asm/movurpc.ms deleted file mode 100644 index 3d75110..0000000 --- a/sim/testsuite/sim/cris/asm/movurpc.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - setf - movu.b r3,pc - quit diff --git a/sim/testsuite/sim/cris/asm/mstep.ms b/sim/testsuite/sim/cris/asm/mstep.ms deleted file mode 100644 index 74aa20d..0000000 --- a/sim/testsuite/sim/cris/asm/mstep.ms +++ /dev/null @@ -1,108 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -#output: fffffffe\n -#output: 3\n -#output: 1fffe\n -#output: 2fffd\n -#output: fffffffd\n -#output: ffffffff\n -#output: f02688a4\n -#output: 1fffe\n -#output: fffffffe\n -#output: fffffffe\n -#output: fffffff9\n -#output: 0\n -#output: 4459802d\n -#output: 4459802d\n - - .include "testutils.inc" - start - moveq -1,r3 - moveq 2,r4 - mstep r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fffffffe - - moveq 2,r3 - moveq -1,r4 - mstep r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - move.d 0xffff,r4 - move.d r4,r3 - mstep r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1fffe - - move.d 0xffff,r4 - move.d r4,r3 - setf n - mstep r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2fffd - - moveq -1,r4 - move.d r4,r3 - mstep r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fffffffd - - moveq -1,r3 - moveq 1,r4 - setf n - mstep r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - mstep r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; f02688a4 - - move.d 0xffff,r3 - move.d 0x1fffe,r4 - mstep r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1fffe - - move.d 0x7fffffff,r3 - moveq 5,r5 - mstep r5,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fffffffe - - move.d 0x7fffffff,r3 - moveq 0,r5 - mstep r5,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fffffffe - - move.d 0x7fffffff,r3 - moveq -5,r5 - mstep r5,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fffffff9 - - move.d 0x7fffffff,r3 - moveq 2,r5 - setf n - mstep r5,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - setf n - mstep r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 4459802d - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - setf nc - mstep r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 4459802d - - quit diff --git a/sim/testsuite/sim/cris/asm/msteppc1.ms b/sim/testsuite/sim/cris/asm/msteppc1.ms deleted file mode 100644 index d21ffd7..0000000 --- a/sim/testsuite/sim/cris/asm/msteppc1.ms +++ /dev/null @@ -1,8 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register read of PC is not implemented.\n -# output: program stopped with signal 5 (*).\n - - .include "testutils.inc" - start - mstep pc,r2 diff --git a/sim/testsuite/sim/cris/asm/msteppc2.ms b/sim/testsuite/sim/cris/asm/msteppc2.ms deleted file mode 100644 index 69bfbaf..0000000 --- a/sim/testsuite/sim/cris/asm/msteppc2.ms +++ /dev/null @@ -1,8 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register read of PC is not implemented.\n -# output: program stopped with signal 5 (*).\n - - .include "testutils.inc" - start - mstep r2,pc diff --git a/sim/testsuite/sim/cris/asm/msteppc3.ms b/sim/testsuite/sim/cris/asm/msteppc3.ms deleted file mode 100644 index 09e87a3..0000000 --- a/sim/testsuite/sim/cris/asm/msteppc3.ms +++ /dev/null @@ -1,8 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register read of PC is not implemented.\n -# output: program stopped with signal 5 (*).\n - - .include "testutils.inc" - start - mstep pc,pc diff --git a/sim/testsuite/sim/cris/asm/mulv10.ms b/sim/testsuite/sim/cris/asm/mulv10.ms deleted file mode 100644 index 43511f7..0000000 --- a/sim/testsuite/sim/cris/asm/mulv10.ms +++ /dev/null @@ -1,29 +0,0 @@ -# mach: crisv8 crisv10 -# output: fffffffe\n -# output: ffffffff\n -# output: fffffffe\n -# output: 1\n - -; Check that carry is cleared on v8, v10. - - .include "testutils.inc" - start - moveq -1,r3 - moveq 2,r4 - setf c - muls.d r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 2,r4 - setf c - mulu.d r4,r3 - test_cc 0 0 1 0 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; 1 - - quit diff --git a/sim/testsuite/sim/cris/asm/mulv32.ms b/sim/testsuite/sim/cris/asm/mulv32.ms deleted file mode 100644 index 6d2edcb..0000000 --- a/sim/testsuite/sim/cris/asm/mulv32.ms +++ /dev/null @@ -1,51 +0,0 @@ -# mach: crisv32 -# output: fffffffe\n -# output: ffffffff\n -# output: fffffffe\n -# output: 1\n -# output: fffffffe\n -# output: ffffffff\n -# output: fffffffe\n -# output: 1\n - -; Check that carry is not modified on v32. - - .include "testutils.inc" - start - moveq -1,r3 - moveq 2,r4 - setf c - muls.d r4,r3 - test_cc 1 0 0 1 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 2,r4 - setf c - mulu.d r4,r3 - test_cc 0 0 1 1 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; 1 - - moveq -1,r3 - moveq 2,r4 - clearf c - muls.d r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 2,r4 - clearf c - mulu.d r4,r3 - test_cc 0 0 1 0 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; 1 - - quit diff --git a/sim/testsuite/sim/cris/asm/mulx.ms b/sim/testsuite/sim/cris/asm/mulx.ms deleted file mode 100644 index 1fc6261..0000000 --- a/sim/testsuite/sim/cris/asm/mulx.ms +++ /dev/null @@ -1,246 +0,0 @@ -# mach: crisv10 crisv32 -# output: fffffffe\nffffffff\nfffffffe\n1\nfffffffe\nffffffff\nfffffffe\n1\nfffe0001\n0\nfffe0001\n0\n1\n0\n1\nfffffffe\n193eade2\n277e3a49\n193eade2\n277e3a49\nfffffffe\nffffffff\n1fffe\n0\nfffffffe\nffffffff\n1fffe\n0\n1\n0\nfffe0001\n0\nfdbdade2\nffffffff\n420fade2\n0\nfffffffe\nffffffff\n1fe\n0\nfffffffe\nffffffff\n1fe\n0\n1\n0\nfe01\n0\n1\n0\nfe01\n0\nffffd9e2\nffffffff\n2be2\n0\n0\n0\n0\n0\n - - .include "testutils.inc" - start - moveq -1,r3 - moveq 2,r4 - muls.d r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 2,r4 - mulu.d r4,r3 - test_cc 0 0 1 0 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; 1 - - moveq 2,r3 - moveq -1,r4 - muls.d r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; ffffffff - - moveq 2,r3 - moveq -1,r4 - mulu.d r4,r3 - test_cc 0 0 1 0 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; 1 - - move.d 0xffff,r4 - move.d r4,r3 - muls.d r4,r3 - test_cc 0 0 1 0 - dumpr3 ; fffe0001 - move mof,r3 - dumpr3 ; 0 - - move.d 0xffff,r4 - move.d r4,r3 - mulu.d r4,r3 - test_cc 0 0 0 0 - dumpr3 ; fffe0001 - move mof,r3 - dumpr3 ; 0 - - moveq -1,r4 - move.d r4,r3 - muls.d r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - move mof,r3 - dumpr3 ; 0 - - moveq -1,r4 - move.d r4,r3 - mulu.d r4,r3 - test_cc 1 0 1 0 - dumpr3 ; 1 - move mof,r3 - dumpr3 ; fffffffe - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - muls.d r4,r3 - test_cc 0 0 1 0 - dumpr3 ; 193eade2 - move mof,r3 - dumpr3 ; 277e3a49 - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - mulu.d r4,r3 - test_cc 0 0 1 0 - dumpr3 ; 193eade2 - move mof,r3 - dumpr3 ; 277e3a49 - - move.d 0xffff,r3 - moveq 2,r4 - muls.w r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 2,r4 - mulu.w r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1fffe - move mof,r3 - dumpr3 ; 0 - - moveq 2,r3 - move.d 0xffff,r4 - muls.w r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; ffffffff - - moveq 2,r3 - moveq -1,r4 - mulu.w r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1fffe - move mof,r3 - dumpr3 ; 0 - - move.d 0xffff,r4 - move.d r4,r3 - muls.w r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - move mof,r3 - dumpr3 ; 0 - - moveq -1,r4 - move.d r4,r3 - mulu.w r4,r3 - test_cc 0 0 0 0 - dumpr3 ; fffe0001 - move mof,r3 - dumpr3 ; 0 - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - muls.w r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fdbdade2 - move mof,r3 - dumpr3 ; ffffffff - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - mulu.w r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 420fade2 - move mof,r3 - dumpr3 ; 0 - - move.d 0xff,r3 - moveq 2,r4 - muls.b r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; ffffffff - - moveq -1,r3 - moveq 2,r4 - mulu.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1fe - move mof,r3 - dumpr3 ; 0 - - moveq 2,r3 - moveq -1,r4 - muls.b r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - move mof,r3 - dumpr3 ; ffffffff - - moveq 2,r3 - moveq -1,r4 - mulu.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1fe - move mof,r3 - dumpr3 ; 0 - - move.d 0xff,r4 - move.d r4,r3 - muls.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - move mof,r3 - dumpr3 ; 0 - - moveq -1,r4 - move.d r4,r3 - mulu.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; fe01 - move mof,r3 - dumpr3 ; 0 - - move.d 0xfeda49ff,r4 - move.d r4,r3 - muls.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - move mof,r3 - dumpr3 ; 0 - - move.d 0xfeda49ff,r4 - move.d r4,r3 - mulu.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; fe01 - move mof,r3 - dumpr3 ; 0 - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - muls.b r4,r3 - test_cc 1 0 0 0 - dumpr3 ; ffffd9e2 - move mof,r3 - dumpr3 ; ffffffff - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - mulu.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 2be2 - move mof,r3 - dumpr3 ; 0 - - moveq 0,r3 - move.d 0xf87f4aeb,r4 - muls.d r4,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - move mof,r3 - dumpr3 ; 0 - - move.d 0xf87f4aeb,r3 - moveq 0,r4 - mulu.d r4,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - move mof,r3 - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/neg.ms b/sim/testsuite/sim/cris/asm/neg.ms deleted file mode 100644 index 0a922a6..0000000 --- a/sim/testsuite/sim/cris/asm/neg.ms +++ /dev/null @@ -1,102 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: ffffffff\nffffffff\n0\n80000000\n1\nba987655\nffff\nffff\n0\n89ab8000\nffff0001\n45677655\nff\nff\n0\n89abae80\nffffff01\n45678955\n - - .include "testutils.inc" - start - moveq 0,r3 - moveq 1,r4 - neg.d r4,r3 - test_cc 1 0 0 1 - dumpr3 ; ffffffff - - moveq 1,r3 - moveq 0,r4 - neg.d r3,r3 - test_cc 1 0 0 1 - dumpr3 ; ffffffff - - moveq 0,r3 - neg.d r3,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x80000000,r3 - neg.d r3,r3 - test_cc 1 0 1 1 - dumpr3 ; 80000000 - - moveq -1,r3 - neg.d r3,r3 - test_cc 0 0 0 1 - dumpr3 ; 1 - - move.d 0x456789ab,r3 - neg.d r3,r3 - test_cc 1 0 0 1 - dumpr3 ; ba987655 - - moveq 0,r3 - moveq 1,r4 - neg.w r4,r3 - test_cc 1 0 0 1 - dumpr3 ; ffff - - moveq 1,r3 - moveq 0,r4 - neg.w r3,r3 - test_cc 1 0 0 1 - dumpr3 ; ffff - - moveq 0,r3 - neg.w r3,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x89ab8000,r3 - neg.w r3,r3 - test_cc 1 0 1 1 - dumpr3 ; 89ab8000 - - moveq -1,r3 - neg.w r3,r3 - test_cc 0 0 0 1 - dumpr3 ; ffff0001 - - move.d 0x456789ab,r3 - neg.w r3,r3 - test_cc 0 0 0 1 - dumpr3 ; 45677655 - - moveq 0,r3 - moveq 1,r4 - neg.b r4,r3 - test_cc 1 0 0 1 - dumpr3 ; ff - - moveq 1,r3 - moveq 0,r4 - neg.b r3,r3 - test_cc 1 0 0 1 - dumpr3 ; ff - - moveq 0,r3 - neg.b r3,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x89abae80,r3 - neg.b r3,r3 - test_cc 1 0 1 1 - dumpr3 ; 89abae80 - - moveq -1,r3 - neg.b r3,r3 - test_cc 0 0 0 1 - dumpr3 ; ffffff01 - - move.d 0x456789ab,r3 - neg.b r3,r3 - test_cc 0 0 0 1 - dumpr3 ; 45678955 - - quit diff --git a/sim/testsuite/sim/cris/asm/nonvcv32.ms b/sim/testsuite/sim/cris/asm/nonvcv32.ms deleted file mode 100644 index 98af367..0000000 --- a/sim/testsuite/sim/cris/asm/nonvcv32.ms +++ /dev/null @@ -1,167 +0,0 @@ -# mach: crisv32 - - .include "testutils.inc" - -; Check for various non-arithmetic insns that C and V are not affected -; on v32 (where they were on v10), as the generic tests don't cover -; that; they are cleared before testing. - -; First, a macro testing that VC are unaffected, not counting previous -; register contents. - .macro nonvc0 insn op - move.d $r0,$r3 - setf vc - .ifnc \insn,swapnwbr - \insn \op,$r3 - .else - \insn $r3 - .endif - bcc 9f - nop - bvc 9f - nop - move.d $r0,$r3 - clearf vc - .ifnc \insn,swapnwbr - \insn \op,$r3 - .else - \insn $r3 - .endif - bcs 9f - nop - bvc 8f - nop -9: - fail -8: - .endm - -; Use the above, but initialize the non-parameter operand to a value. - .macro nonvc1 insn val op - move.d \val,$r0 - nonvc0 \insn,\op - .endm - -; Use the above, iterating over various values. - .macro nonvc2 insn op - .irp p,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000 - nonvc1 \insn,\p,\op - nonvc1 \insn,-\p,\op - .endr - .endm - - .macro nonvc2q insn op min=-63 max=63 - .if (\op >= \min) && (\op <= \max) - nonvc2 \insn,\op - .endif - .endm - -; The above, for each .b .w .d insn variant. - .macro nonvcbwd insn op - .irp s,.b,.w,.d - nonvc2 \insn\s,\op - .endr - .endm - -; For various insns with register, dword constant and memory operands. - .macro nonvcitermcd op=[$r4] - nonvc2 and.d,\op - nonvc2 move.d,\op - nonvc2 or.d,\op - .endm - -; Similar, for various insns with register, word constant and memory operands. - .macro nonvcitermcw op=[$r4] - nonvcitermcd \op - nonvc2 and.w,\op - nonvc2 move.w,\op - nonvc2 or.w,\op - nonvc2 movs.w,\op - nonvc2 movu.w,\op - .endm - -; Similar, for various insns with register, byte constant and memory operands. - .macro nonvcitermcb op=[$r4] - nonvcitermcw \op - nonvc2 and.b,\op - nonvc2 move.b,\op - nonvc2 or.b,\op - nonvc2 movs.b,\op - nonvc2 movu.b,\op - .endm - -; Similar, for insns with quick constant operands. - .macro nonvciterq op - nonvcitermcb \op - nonvc2 bound.b,\op - nonvc2q andq,\op,min=-32,max=31 - nonvc2q asrq,\op,min=0,max=31 - nonvc2q lsrq,\op,min=0,max=31 - nonvc2q orq,\op,min=-32,max=31 - nonvc2q moveq,\op,min=-32,max=31 - .endm - -; Similar, for insns with register operands. - .macro nonvciterr op - nonvcitermcb \op - nonvcbwd bound,\op - nonvc2 abs,\op - nonvcbwd asr,\op - nonvc2 dstep,\op - nonvcbwd lsr,\op - nonvcbwd lsl,\op - nonvc2 lz,\op - nonvc2 swapnwbr - nonvc2 xor,\op - .endm - -; Test all applicable constant, register and memory variants of a value. - .macro tst op -; Constants - .if (\op <= 31) && (\op >= -32) - nonvciterq \op - .elseif (\op <= 255) && (\op >= -128) - nonvcitermcb \op - nonvcbwd bound,\op - .elseif (\op <= 65535) && (\op >= -32767) - nonvcitermcw \op - nonvc2 bound.w,\op - nonvc2 bound.d,\op - .else - nonvcitermcd \op - nonvc2 bound.d,\op - .endif -; Registers - move.d \op,$r4 - nonvciterr $r4 -; Memory - nonvcitermcb [$r5] - addq 4,$r5 - .section .rodata - .dword \op - .previous - .endm - -; As above but negation too. - .macro tstpm op - tst \op - tst -\op - .endm - - -; Set up for the actual test. - - start - move.d c0,$r5 - - .section .rodata -c0: - .previous - -; Finally, test. - - .irp x,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000 - tstpm \x - .endr - - pass diff --git a/sim/testsuite/sim/cris/asm/nopv10t.ms b/sim/testsuite/sim/cris/asm/nopv10t.ms deleted file mode 100644 index d96eaf0..0000000 --- a/sim/testsuite/sim/cris/asm/nopv10t.ms +++ /dev/null @@ -1,13 +0,0 @@ -#mach: crisv0 crisv3 crisv8 crisv10 -#output: Basic clock cycles, total @: 5\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/nopv32t.ms b/sim/testsuite/sim/cris/asm/nopv32t.ms deleted file mode 100644 index 794d19b..0000000 --- a/sim/testsuite/sim/cris/asm/nopv32t.ms +++ /dev/null @@ -1,21 +0,0 @@ -#mach: crisv32 -#output: Basic clock cycles, total @: 5\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - .global _start -_start: - nop - nop - nop - nop - nop - break 15 diff --git a/sim/testsuite/sim/cris/asm/nopv32t2.ms b/sim/testsuite/sim/cris/asm/nopv32t2.ms deleted file mode 100644 index 760a539..0000000 --- a/sim/testsuite/sim/cris/asm/nopv32t2.ms +++ /dev/null @@ -1,13 +0,0 @@ -#mach: crisv10 crisv32 -#output: Clock cycles including stall cycles for unaligned accesses @: 5\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=unaligned - .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/nopv32t3.ms b/sim/testsuite/sim/cris/asm/nopv32t3.ms deleted file mode 100644 index d8b2351..0000000 --- a/sim/testsuite/sim/cris/asm/nopv32t3.ms +++ /dev/null @@ -1,13 +0,0 @@ -#mach: crisv10 crisv32 -#output: Schedulable clock cycles, total @: 5\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=schedulable - .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/nopv32t4.ms b/sim/testsuite/sim/cris/asm/nopv32t4.ms deleted file mode 100644 index 98f336b..0000000 --- a/sim/testsuite/sim/cris/asm/nopv32t4.ms +++ /dev/null @@ -1,13 +0,0 @@ -#mach: crisv10 crisv32 -#output: All accounted clock cycles, total @: 5\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=all - .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/not.ms b/sim/testsuite/sim/cris/asm/not.ms deleted file mode 100644 index 4416bbc..0000000 --- a/sim/testsuite/sim/cris/asm/not.ms +++ /dev/null @@ -1,31 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: fffffffe\nfffffffd\nffff0f00\n0\n87ecbbad\n - - .include "testutils.inc" - start - moveq 1,r3 - not r3 - test_move_cc 1 0 0 0 - dumpr3 ; fffffffe - - moveq 2,r3 - not r3 - test_move_cc 1 0 0 0 - dumpr3 ; fffffffd - - move.d 0xf0ff,r3 - not r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffff0f00 - - moveq -1,r3 - not r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x78134452,r3 - not r3 - test_move_cc 1 0 0 0 - dumpr3 ; 87ecbbad - - quit diff --git a/sim/testsuite/sim/cris/asm/op3.ms b/sim/testsuite/sim/cris/asm/op3.ms deleted file mode 100644 index 05e974c..0000000 --- a/sim/testsuite/sim/cris/asm/op3.ms +++ /dev/null @@ -1,98 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 -# output: ee19cd0b\nee197761\nccff2244\n55aa77ff\nffffaa77\naa\n4243ab11\n424377ab\nfdedaaf0\n4242dd68\n4242dd68\n40025567\n57eb77ff\n55aa77ff\n - - .include "testutils.inc" - .data -x: - .dword 0x55aa77ff - .dword 0xccff2244 - .dword 0x88ccee19 - - start - move.d x,r10 - moveq 0,r3 - moveq 12,r4 - add.d [r10+6],r4,r3 - test_cc 1 0 0 0 - dumpr3 ; ee19cd0b - - move.d 0x1267,r7 - subu.w [r10+2],r3,r8 - test_cc 1 0 0 0 - move.d r8,r3 - dumpr3 ; ee197761 - - moveq 1,r8 - bound.d [r10+r8.d],r3,r5 - test_move_cc 1 0 0 0 - move.d r5,r3 - dumpr3 ; ccff2244 - -; Also applies to move insns. Bleah. - moveq 0,r5 - bdap 0,r10 - move.d [r3],r5 - test_move_cc 0 0 0 0 - dumpr3 ; 55aa77ff - - moveq 0,r5 - bdap 1,r10 - movs.w [r3],r5 - test_move_cc 1 0 0 0 - dumpr3 ; ffffaa77 - - moveq 0,r5 - bdap 2,r10 - movu.b [r3],r5 - test_move_cc 0 0 0 0 - dumpr3 ; aa - - move.d 0x42435567,r8 - bdap 2,r10 - adds.w [r3],r8 - test_cc 0 0 0 0 - dumpr3 ; 4243ab11 - - move.d 0x42435567,r8 - bdap 4,r10 - addu.w [r3],r8 - test_cc 0 0 0 0 - dumpr3 ; 424377ab - - move.d 0x42435567,r8 - bdap 1,r10 - sub.d [r3],r8 - test_cc 1 0 0 1 - dumpr3 ; fdedaaf0 - - move.d 0x42435567,r8 - bdap 0,r10 - subs.w [r3],r8 - test_cc 0 0 0 0 - dumpr3 ; 4242dd68 - - move.d 0x42435567,r8 - bdap 0,r10 - subu.w [r3],r8 - test_cc 0 0 0 0 - dumpr3 ; 4242dd68 - - move.d 0x42435567,r8 - bdap 0,r10 - and.d [r3],r8 - test_move_cc 0 0 0 0 - dumpr3 ; 40025567 - - move.d 0x42435567,r8 - bdap 0,r10 - or.d [r3],r8 - test_move_cc 0 0 0 0 - dumpr3 ; 57eb77ff - - move.d 0xc2435567,r8 - bdap 0,r10 - bound.d [r3],r8 - test_move_cc 0 0 0 0 - dumpr3 ; 55aa77ff - - quit diff --git a/sim/testsuite/sim/cris/asm/opterr1.ms b/sim/testsuite/sim/cris/asm/opterr1.ms deleted file mode 100644 index 409f58b..0000000 --- a/sim/testsuite/sim/cris/asm/opterr1.ms +++ /dev/null @@ -1,5 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# xerror: -# output: *: unrecognized option [`']--cris-stats=xyz'\nUse --help for a complete list of options.\n -# sim: --cris-stats=xyz - .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/opterr2.ms b/sim/testsuite/sim/cris/asm/opterr2.ms deleted file mode 100644 index 084d61e..0000000 --- a/sim/testsuite/sim/cris/asm/opterr2.ms +++ /dev/null @@ -1,5 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# xerror: -# output: *: unrecognized option [`']--cris-xyz'\nUse --help for a complete list of options.\n -# sim: --cris-xyz - .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/opterr3.ms b/sim/testsuite/sim/cris/asm/opterr3.ms deleted file mode 100644 index 8d602be..0000000 --- a/sim/testsuite/sim/cris/asm/opterr3.ms +++ /dev/null @@ -1,10 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# ld: -N --oformat binary --section-start=.text=0x10000000 -# sim: --cris-naked --memory-mapfile -# xerror: -# output: Usage: run \[options\] program \[program args\]\n*\n -# progopts: --memory-region 0x10000000,0x1000 - .include "bare3.ms" - -; Check that we get an error for wrong usage, not a SEGV for lack of -; bfd when missing the program argument (can't use *only* mapped files). diff --git a/sim/testsuite/sim/cris/asm/opterr4.ms b/sim/testsuite/sim/cris/asm/opterr4.ms deleted file mode 100644 index a4ffc6b..0000000 --- a/sim/testsuite/sim/cris/asm/opterr4.ms +++ /dev/null @@ -1,7 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# xerror: -# output: Invalid option [`']--cris-start-address=x'\n -# sim: --cris-start-address=x - .include "nopv32t.ms" - -; Check that we recognize wrong usage of the --cris-start-address option. diff --git a/sim/testsuite/sim/cris/asm/opterr5.ms b/sim/testsuite/sim/cris/asm/opterr5.ms deleted file mode 100644 index 3d1b591..0000000 --- a/sim/testsuite/sim/cris/asm/opterr5.ms +++ /dev/null @@ -1,7 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# xerror: -# output: Invalid option [`']--cris-program-offset=x'\n -# sim: --cris-program-offset=x - .include "nopv32t.ms" - -; Check that we recognize wrong usage of the --cris-program-offset option. diff --git a/sim/testsuite/sim/cris/asm/option1.ms b/sim/testsuite/sim/cris/asm/option1.ms deleted file mode 100644 index 387a01f..0000000 --- a/sim/testsuite/sim/cris/asm/option1.ms +++ /dev/null @@ -1,7 +0,0 @@ -#mach: crisv0 crisv3 crisv8 crisv10 crisv32 -#sim: --cris-trace=foo -#xerror: -#output: Unknown option `--cris-trace=foo'\n - .include "testutils.inc" - start - fail diff --git a/sim/testsuite/sim/cris/asm/option2.ms b/sim/testsuite/sim/cris/asm/option2.ms deleted file mode 100644 index 4ac6a86..0000000 --- a/sim/testsuite/sim/cris/asm/option2.ms +++ /dev/null @@ -1,5 +0,0 @@ -#mach: crisv0 crisv3 crisv8 crisv10 crisv32 -#sim: --sysroot=/non/exist/dir -#output: run: can't change directory to "/non/exist/dir"\n -#xerror: - .include "option1.ms" diff --git a/sim/testsuite/sim/cris/asm/option3.ms b/sim/testsuite/sim/cris/asm/option3.ms deleted file mode 100644 index 75ddb44..0000000 --- a/sim/testsuite/sim/cris/asm/option3.ms +++ /dev/null @@ -1,7 +0,0 @@ -#mach: crisv0 crisv3 crisv8 crisv10 crisv32 -#sim: --cris-cycles=foo -#xerror: -#output: Unknown option `--cris-cycles=foo'\n - .include "testutils.inc" - start - fail diff --git a/sim/testsuite/sim/cris/asm/option4.ms b/sim/testsuite/sim/cris/asm/option4.ms deleted file mode 100644 index e0bc691..0000000 --- a/sim/testsuite/sim/cris/asm/option4.ms +++ /dev/null @@ -1,7 +0,0 @@ -#mach: crisv0 crisv3 crisv8 crisv10 crisv32 -#sim: --cris-unknown-syscall=foo -#xerror: -#output: Unknown option `--cris-unknown-syscall=foo'\n - .include "testutils.inc" - start - fail diff --git a/sim/testsuite/sim/cris/asm/orc.ms b/sim/testsuite/sim/cris/asm/orc.ms deleted file mode 100644 index d8fbe70..0000000 --- a/sim/testsuite/sim/cris/asm/orc.ms +++ /dev/null @@ -1,71 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n - - .include "testutils.inc" - start - moveq 1,r3 - or.d 2,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - moveq 2,r3 - or.d 1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - move.d 0xf0ff,r3 - or.d 0xff0f,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq -1,r3 - or.d -1,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x78134452,r3 - or.d 0x5432f789,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 7c33f7db - - move.d 0xffff0001,r3 - or.w 2,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff0003 - - moveq 2,r3 - or.w 1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - move.d 0xfedaffaf,r3 - or.w 0xff5f,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fedaffff - - move.d 0x78134452,r3 - or.w 0xf789,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 7813f7db - - moveq 1,r3 - or.b 2,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - moveq 2,r3 - or.b 1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - move.d 0xfa3,r3 - or.b 0x4a,r3 - test_move_cc 1 0 0 0 - dumpr3 ; feb - - move.d 0x78134453,r3 - or.b 0x89,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 781344db - - quit diff --git a/sim/testsuite/sim/cris/asm/orm.ms b/sim/testsuite/sim/cris/asm/orm.ms deleted file mode 100644 index f2bdaae..0000000 --- a/sim/testsuite/sim/cris/asm/orm.ms +++ /dev/null @@ -1,75 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n - - .include "testutils.inc" - .data -x: - .dword 2,1,0xff0f,-1,0x5432f789 - .word 2,1,0xff5f,0xf789 - .byte 2,1,0x4a,0x89 - - start - moveq 1,r3 - move.d x,r5 - or.d [r5+],r3 - dumpr3 ; 3 - - moveq 2,r3 - or.d [r5],r3 - addq 4,r5 - dumpr3 ; 3 - - move.d 0xf0ff,r3 - or.d [r5+],r3 - dumpr3 ; ffff - - moveq -1,r3 - or.d [r5+],r3 - dumpr3 ; ffffffff - - move.d 0x78134452,r3 - or.d [r5+],r3 - dumpr3 ; 7c33f7db - - move.d 0xffff0001,r3 - or.w [r5+],r3 - dumpr3 ; ffff0003 - - moveq 2,r3 - or.w [r5],r3 - addq 2,r5 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - move.d 0xfedaffaf,r3 - or.w [r5+],r3 - test_move_cc 1 0 0 0 - dumpr3 ; fedaffff - - move.d 0x78134452,r3 - or.w [r5+],r3 - test_move_cc 1 0 0 0 - dumpr3 ; 7813f7db - - moveq 1,r3 - or.b [r5+],r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - moveq 2,r3 - or.b [r5],r3 - addq 1,r5 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - move.d 0xfa3,r3 - or.b [r5+],r3 - test_move_cc 1 0 0 0 - dumpr3 ; feb - - move.d 0x78134453,r3 - or.b [r5],r3 - test_move_cc 1 0 0 0 - dumpr3 ; 781344db - - quit diff --git a/sim/testsuite/sim/cris/asm/orq.ms b/sim/testsuite/sim/cris/asm/orq.ms deleted file mode 100644 index 905a961..0000000 --- a/sim/testsuite/sim/cris/asm/orq.ms +++ /dev/null @@ -1,41 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 3\n3\nffffffff\nffffffff\n1f\nffffffe0\n7813445e\n - - .include "testutils.inc" - start - moveq 1,r3 - orq 2,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - moveq 2,r3 - orq 1,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - move.d 0xf0ff,r3 - orq -1,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq 0,r3 - orq -1,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - moveq 0,r3 - orq 31,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1f - - moveq 0,r3 - orq -32,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffe0 - - move.d 0x78134452,r3 - orq 12,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 7813445e - - quit diff --git a/sim/testsuite/sim/cris/asm/orr.ms b/sim/testsuite/sim/cris/asm/orr.ms deleted file mode 100644 index 54d033b..0000000 --- a/sim/testsuite/sim/cris/asm/orr.ms +++ /dev/null @@ -1,84 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n - - .include "testutils.inc" - start - moveq 1,r3 - moveq 2,r4 - or.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - moveq 2,r3 - moveq 1,r4 - or.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - move.d 0xff0f,r4 - move.d 0xf0ff,r3 - or.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff - - moveq -1,r4 - move.d r4,r3 - or.d r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - or.d r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 7c33f7db - - move.d 0xffff0001,r3 - moveq 2,r4 - or.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ffff0003 - - moveq 2,r3 - move.d 0xffff0001,r4 - or.w r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - move.d 0xfedaffaf,r3 - move.d 0xffffff5f,r4 - or.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; fedaffff - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - or.w r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 7813f7db - - moveq 1,r3 - move.d 0xffffff02,r4 - or.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - moveq 2,r3 - moveq 1,r4 - or.b r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - move.d 0x4a,r4 - move.d 0xfa3,r3 - or.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; feb - - move.d 0x5432f789,r4 - move.d 0x78134453,r3 - or.b r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; 781344db - - quit diff --git a/sim/testsuite/sim/cris/asm/pcplus.ms b/sim/testsuite/sim/cris/asm/pcplus.ms deleted file mode 100644 index 99cd46a..0000000 --- a/sim/testsuite/sim/cris/asm/pcplus.ms +++ /dev/null @@ -1,46 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 - -; Test that a forward as well as backward 32-bit "branch" expansion -; works including that the right offset is applied. - - .macro nop32 - .rept 32 - nop - .endr - .endm - - .include "testutils.inc" - start - jump start1 - fail - - nop32 - subq 63,$r10 -9: subq 1,$r10 - nop32 - jump 0f - - fail -0: move [$pc=$pc+1f-6-0b],$p0 - nop32 - fail - - .skip 32768,0 - - nop32 - subq 63,$r10 -1: - subq 1,$r10 - nop32 - test.d $r10 - bne 7f - nop - pass -7: - fail - -start1: - moveq 2,$r10 -0: move [$pc=$pc+9b-6-0b],$p0 - subq 63,$r10 - fail diff --git a/sim/testsuite/sim/cris/asm/pid1.ms b/sim/testsuite/sim/cris/asm/pid1.ms deleted file mode 100644 index 16e3489..0000000 --- a/sim/testsuite/sim/cris/asm/pid1.ms +++ /dev/null @@ -1,45 +0,0 @@ -# mach: crisv32 -# output: 0\ncafebabe\nbaddbeef\necc0d00d\nc0ceface\npass\n - -; Check that the PID register has the right size, 32 bits: check -; immediate, to/from register and memory. (This has to be done in -; supervisor mode, so don't set u.) - - .include "testutils.inc" - .macro dumpid - move $pid,$r3 - dumpr3 - .endm - - start - moveq -1,$r3 - move 0,$pid - dumpid ; 0 - move 0xcafebabe,$pid - dumpid ; cafebabe - move.d 0xbaddbeef,$r2 - move $r2,$pid - dumpid ; baddbeef - move.d 0f,$r0 - move [$r0+],$pid - cmp.d 0f+4,$r0 - beq 1f - nop -dofail: - fail -0: - .dword 0xecc0d00d -0: - .dword 0xc0ceface -1: - dumpid ; ecc0d00d - move.d 0b,$r1 - move 0xc0ceface,$pid - move $pid,[$r1+] - cmp.d 0b+4,$r1 - bne dofail - subq 4,$r1 - nop - move.d [$r1],$r3 - dumpr3 ; c0ceface - pass diff --git a/sim/testsuite/sim/cris/asm/raw1.ms b/sim/testsuite/sim/cris/asm/raw1.ms deleted file mode 100644 index fd2fcb2..0000000 --- a/sim/testsuite/sim/cris/asm/raw1.ms +++ /dev/null @@ -1,22 +0,0 @@ -; Checking read-after-write: read-then-read unaffected. -#mach: crisv32 -#output: Basic clock cycles, total @: 4\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - move.d [$r0],$r2 - move.d [$r1],$r4 - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw10.ms b/sim/testsuite/sim/cris/asm/raw10.ms deleted file mode 100644 index a9faee9..0000000 --- a/sim/testsuite/sim/cris/asm/raw10.ms +++ /dev/null @@ -1,22 +0,0 @@ -; Checking read-after-write: swrite-then-read 2 cycles. -#mach: crisv32 -#output: Basic clock cycles, total @: 4\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 2\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - clear.d [$r0] - move [$r1],$srp - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw11.ms b/sim/testsuite/sim/cris/asm/raw11.ms deleted file mode 100644 index 38bf274..0000000 --- a/sim/testsuite/sim/cris/asm/raw11.ms +++ /dev/null @@ -1,23 +0,0 @@ -; Checking read-after-write: swrite-then-nop-read 2 cycles. -#mach: crisv32 -#output: Basic clock cycles, total @: 5\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 2\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - clear.d [$r0] - nop - move [$r1],$srp - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw12.ms b/sim/testsuite/sim/cris/asm/raw12.ms deleted file mode 100644 index d8ffa45..0000000 --- a/sim/testsuite/sim/cris/asm/raw12.ms +++ /dev/null @@ -1,24 +0,0 @@ -; Checking read-after-write: swrite-then-nop-nop-read unaffected. -#mach: crisv32 -#output: Basic clock cycles, total @: 6\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - clear.d [$r0] - nop - nop - move [$r1],$srp - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw13.ms b/sim/testsuite/sim/cris/asm/raw13.ms deleted file mode 100644 index e5e2e52..0000000 --- a/sim/testsuite/sim/cris/asm/raw13.ms +++ /dev/null @@ -1,22 +0,0 @@ -; Checking read-after-write: write-MOF-then-read unaffected. -#mach: crisv32 -#output: Basic clock cycles, total @: 4\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - move [$r0],$mof - move [$r1],$srp - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw14.ms b/sim/testsuite/sim/cris/asm/raw14.ms deleted file mode 100644 index f086328..0000000 --- a/sim/testsuite/sim/cris/asm/raw14.ms +++ /dev/null @@ -1,14 +0,0 @@ -; Checking read-after-write: cycles included in "schedulable". -#mach: crisv32 -#output: Schedulable clock cycles, total @: 6\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 2\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=schedulable - .include "raw4.ms" diff --git a/sim/testsuite/sim/cris/asm/raw15.ms b/sim/testsuite/sim/cris/asm/raw15.ms deleted file mode 100644 index 3f49067..0000000 --- a/sim/testsuite/sim/cris/asm/raw15.ms +++ /dev/null @@ -1,14 +0,0 @@ -; Checking read-after-write: cycles included in "all". -#mach: crisv32 -#output: All accounted clock cycles, total @: 6\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 2\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=all - .include "raw4.ms" diff --git a/sim/testsuite/sim/cris/asm/raw16.ms b/sim/testsuite/sim/cris/asm/raw16.ms deleted file mode 100644 index 07977cc..0000000 --- a/sim/testsuite/sim/cris/asm/raw16.ms +++ /dev/null @@ -1,14 +0,0 @@ -; Checking read-after-write: cycles included in "unaligned". -#mach: crisv32 -#output: Clock cycles including stall cycles for unaligned accesses @: 4\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 2\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=unaligned - .include "raw4.ms" diff --git a/sim/testsuite/sim/cris/asm/raw17.ms b/sim/testsuite/sim/cris/asm/raw17.ms deleted file mode 100644 index 07d18c5..0000000 --- a/sim/testsuite/sim/cris/asm/raw17.ms +++ /dev/null @@ -1,29 +0,0 @@ -; Checking read-after-write: different read-after-write combinations. -#mach: crisv32 -#output: Basic clock cycles, total @: 11\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 8\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - move.d $r1,[$r0] - move.d [$r1],$r2 - move.d [$r1],$r2 - clear.d [$r0] - move.d [$r1],$r2 - movem $r0,[$r1] - movem [$r1],$r0 - move $srp,[$r1] - move.d [$r1],$r0 - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw2.ms b/sim/testsuite/sim/cris/asm/raw2.ms deleted file mode 100644 index cbbc47d..0000000 --- a/sim/testsuite/sim/cris/asm/raw2.ms +++ /dev/null @@ -1,22 +0,0 @@ -; Checking read-after-write: write-then-write unaffected. -#mach: crisv32 -#output: Basic clock cycles, total @: 4\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - move.d $r1,[$r0] - move.d $r0,[$r1] - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw3.ms b/sim/testsuite/sim/cris/asm/raw3.ms deleted file mode 100644 index 1c9a86b..0000000 --- a/sim/testsuite/sim/cris/asm/raw3.ms +++ /dev/null @@ -1,22 +0,0 @@ -; Checking read-after-write: read-then-write unaffected. -#mach: crisv32 -#output: Basic clock cycles, total @: 4\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - move.d [$r0],$r2 - move.d $r0,[$r1] - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw4.ms b/sim/testsuite/sim/cris/asm/raw4.ms deleted file mode 100644 index 75a77e9..0000000 --- a/sim/testsuite/sim/cris/asm/raw4.ms +++ /dev/null @@ -1,22 +0,0 @@ -; Checking read-after-write: write-then-read 2 cycles. -#mach: crisv32 -#output: Basic clock cycles, total @: 4\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 2\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - move.d $r1,[$r0] - move.d [$r1],$r2 - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw5.ms b/sim/testsuite/sim/cris/asm/raw5.ms deleted file mode 100644 index 670e143..0000000 --- a/sim/testsuite/sim/cris/asm/raw5.ms +++ /dev/null @@ -1,23 +0,0 @@ -; Checking read-after-write: write-then-nop-read 2 cycles. -#mach: crisv32 -#output: Basic clock cycles, total @: 5\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 2\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - move.d $r1,[$r0] - nop - move.d [$r1],$r2 - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw6.ms b/sim/testsuite/sim/cris/asm/raw6.ms deleted file mode 100644 index d6e6636..0000000 --- a/sim/testsuite/sim/cris/asm/raw6.ms +++ /dev/null @@ -1,24 +0,0 @@ -; Checking read-after-write: write-then-nop-nop-read unaffected. -#mach: crisv32 -#output: Basic clock cycles, total @: 6\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - move.d $r1,[$r0] - nop - nop - move.d [$r1],$r2 - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw7.ms b/sim/testsuite/sim/cris/asm/raw7.ms deleted file mode 100644 index 99da5f7..0000000 --- a/sim/testsuite/sim/cris/asm/raw7.ms +++ /dev/null @@ -1,25 +0,0 @@ -; Checking read-after-write: movemwrite-then-read 2 cycles. -#mach: crisv32 -#ld: --section-start=.text=0 -#output: Basic clock cycles, total @: 6\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 2\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 1\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4*11 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - nop - nop - movem $r10,[$r0] - move.d [$r1],$r2 - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw8.ms b/sim/testsuite/sim/cris/asm/raw8.ms deleted file mode 100644 index 8e42b95..0000000 --- a/sim/testsuite/sim/cris/asm/raw8.ms +++ /dev/null @@ -1,26 +0,0 @@ -; Checking read-after-write: movemwrite-then-nop-read 2 cycles. -#mach: crisv32 -#ld: --section-start=.text=0 -#output: Basic clock cycles, total @: 7\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 2\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 1\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4*11 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - nop - nop - movem $r10,[$r0] - nop - move.d [$r1],$r2 - break 15 diff --git a/sim/testsuite/sim/cris/asm/raw9.ms b/sim/testsuite/sim/cris/asm/raw9.ms deleted file mode 100644 index 5c3881e..0000000 --- a/sim/testsuite/sim/cris/asm/raw9.ms +++ /dev/null @@ -1,27 +0,0 @@ -; Checking read-after-write: movemwrite-then-nop-nop-read unaffected. -#mach: crisv32 -#ld: --section-start=.text=0 -#output: Basic clock cycles, total @: 8\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 1\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "testutils.inc" - startnostack - .lcomm x,4*11 - .lcomm y,4 - move.d x,$r0 - move.d y,$r1 - nop - nop - movem $r10,[$r0] - nop - nop - move.d [$r1],$r2 - break 15 diff --git a/sim/testsuite/sim/cris/asm/ret.ms b/sim/testsuite/sim/cris/asm/ret.ms deleted file mode 100644 index 578c5e1..0000000 --- a/sim/testsuite/sim/cris/asm/ret.ms +++ /dev/null @@ -1,25 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# output: 3\n - -# Test that ret works. - - .include "testutils.inc" - start -x: - moveq 0,r3 - jsr z -w: - quit -y: - addq 1,r3 - dumpr3 - quit - -z: - addq 1,r3 - move srp,r2 - add.d y-w,r2 - move r2,srp - ret - addq 1,r3 - quit diff --git a/sim/testsuite/sim/cris/asm/rfe.ms b/sim/testsuite/sim/cris/asm/rfe.ms deleted file mode 100644 index 8d53778..0000000 --- a/sim/testsuite/sim/cris/asm/rfe.ms +++ /dev/null @@ -1,47 +0,0 @@ -# mach: crisv32 -# output: 4000c3af\n40000020\n40000080\n40000000\n - -; Check that RFE affects CCS the right way. - - .include "testutils.inc" - start - -; Set SPC to 1 to disable single step exceptions when S flag is set. - move 1,spc - -; CCS: -; 31 24 23 16 15 8 7 0 -; +---+-----------+-------+-------+-----------+---+---------------+ -; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| -; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | -; +---+-----------+-------+-------+-----------+---+---------------+ - -; Clear S R P U I X N Z V C, set S1 R1 P1 (not U1) I1 X1 N1 Z1 V1 C1, -; clear S2 R2 P2 U2 N2 Z2 V2 C2, Q; set I2 X2 M: -; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 - move 0x430efc00,ccs - - test_cc 0 0 0 0 - - rfe - test_cc 1 1 1 1 - move ccs,r3 - dumpr3 ; 0x4000c3af - - rfe - test_cc 0 0 0 0 - move ccs,r3 - dumpr3 ; 0x40000020 - - rfe - test_cc 0 0 0 0 - move ccs,r3 - dumpr3 ; 0x40000080 - - or.w 0x100,r3 - move $r3,ccs - rfe - move ccs,r3 - dumpr3 ; 0x40000000 - - quit diff --git a/sim/testsuite/sim/cris/asm/rfg.ms b/sim/testsuite/sim/cris/asm/rfg.ms deleted file mode 100644 index aa664b2..0000000 --- a/sim/testsuite/sim/cris/asm/rfg.ms +++ /dev/null @@ -1,9 +0,0 @@ -# mach: crisv32 -# xerror: -# output: RFG isn't implemented\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - rfg - - quit diff --git a/sim/testsuite/sim/cris/asm/rfn.ms b/sim/testsuite/sim/cris/asm/rfn.ms deleted file mode 100644 index 8f12530..0000000 --- a/sim/testsuite/sim/cris/asm/rfn.ms +++ /dev/null @@ -1,53 +0,0 @@ -# mach: crisv32 -# output: c008c1af\n40000220\n40000080\n40000000\n - -; Check that RFN affects CCS the right way. - - .include "testutils.inc" - start - -; Set SPC to 1 to disable single step exceptions when S flag is set. - move 1,spc - -; CCS: -; 31 24 23 16 15 8 7 0 -; +---+-----------+-------+-------+-----------+---+---------------+ -; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| -; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | -; +---+-----------+-------+-------+-----------+---+---------------+ - -; Clear S R P U I X N Z V C, set R1 P1 (not U1) I1 X1 N1 Z1 V1 C1, -; clear S1 R2 P2 U2 N2 Z2 V2 C2, set S2 I2 X2 Q, clear M: -; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 - move 0xa306fc00,ccs - - test_cc 0 0 0 0 - - rfn - test_cc 1 1 1 1 - move ccs,r3 - dumpr3 ; 0xc008c1af - - and.d 0x3fffffff,r3 - move r3,ccs - rfn - test_cc 0 0 0 0 - move ccs,r3 - dumpr3 ; 0x40000220 - - and.d 0x3fffffff,r3 - move r3,ccs - rfn - test_cc 0 0 0 0 - move ccs,r3 - dumpr3 ; 0x40000080 - - and.d 0x3fffffff,r3 - move r3,ccs - or.w 0x100,r3 - move r3,ccs - rfn - move ccs,r3 - dumpr3 ; 0x40000000 - - quit diff --git a/sim/testsuite/sim/cris/asm/sbfs.ms b/sim/testsuite/sim/cris/asm/sbfs.ms deleted file mode 100644 index 5714b52..0000000 --- a/sim/testsuite/sim/cris/asm/sbfs.ms +++ /dev/null @@ -1,7 +0,0 @@ -# mach: crisv10 -# xerror: -# output: SBFS isn't implemented\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - sbfs [r10] diff --git a/sim/testsuite/sim/cris/asm/scc.ms b/sim/testsuite/sim/cris/asm/scc.ms deleted file mode 100644 index 5925f8a..0000000 --- a/sim/testsuite/sim/cris/asm/scc.ms +++ /dev/null @@ -1,89 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n0\n1\n1\n0\n1\n0\n0\n1\n1\n0\n1\n1\n0\n - - .include "testutils.inc" - - start - clearf nzvc - scc r3 - dumpr3 ; 1 - scs r3 - dumpr3 ; 0 - sne r3 - dumpr3 ; 1 - seq r3 - dumpr3 ; 0 - svc r3 - dumpr3 ; 1 - svs r3 - dumpr3 ; 0 - spl r3 - dumpr3 ; 1 - smi r3 - dumpr3 ; 0 - sls r3 - dumpr3 ; 0 - shi r3 - dumpr3 ; 1 - sge r3 - dumpr3 ; 1 - slt r3 - dumpr3 ; 0 - sgt r3 - dumpr3 ; 1 - sle r3 - dumpr3 ; 0 - sa r3 - dumpr3 ; 1 - setf nzvc - scc r3 - dumpr3 ; 0 - scs r3 - dumpr3 ; 1 - sne r3 - dumpr3 ; 0 - svc r3 - dumpr3 ; 0 - svs r3 - dumpr3 ; 1 - spl r3 - dumpr3 ; 0 - smi r3 - dumpr3 ; 1 - sls r3 - dumpr3 ; 1 - shi r3 - dumpr3 ; 0 - sge r3 - dumpr3 ; 1 - slt r3 - dumpr3 ; 0 - sgt r3 - dumpr3 ; 0 - sle r3 - dumpr3 ; 1 - sa r3 - dumpr3 ; 1 - clearf n - sge r3 - dumpr3 ; 0 - slt r3 - dumpr3 ; 1 - - .if ..asm.arch.cris.v32 - setf p - ssb r3 - .else - moveq 1,r3 - .endif - dumpr3 ; 1 - - .if ..asm.arch.cris.v32 - clearf p - ssb r3 - .else - moveq 0,r3 - .endif - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/sfe.ms b/sim/testsuite/sim/cris/asm/sfe.ms deleted file mode 100644 index b4b8e7c..0000000 --- a/sim/testsuite/sim/cris/asm/sfe.ms +++ /dev/null @@ -1,51 +0,0 @@ -# mach: crisv32 -# output: 4000c800\nc3221800\nc8606400\n48606400\n419d8260\n - -; Check that SFE affects CCS the right way. - - .include "testutils.inc" - start - -; Set SPC to 1 to disable single step exceptions when S flag is set. - move 1,spc - -; CCS: -; 31 24 23 16 15 8 7 0 -; +---+-----------+-------+-------+-----------+---+---------------+ -; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| -; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | -; +---+-----------+-------+-------+-----------+---+---------------+ - - move 0x40000000,ccs - setf ixv - sfe - move ccs,r3 - dumpr3 ; 0x4000c800 - or.d 0x80000000,r3 - move r3,ccs - - setf pzv - sfe - move ccs,r3 - dumpr3 ; 0xc3221800 - - setf xnc - sfe - move ccs,r3 - dumpr3 ; 0xc8606400 - -; Clear Q, so we don't get S and Q at the same time when we set S. - lslq 1,r3 - lsrq 1,r3 - move r3,ccs - move ccs,r3 - dumpr3 ; 0x48606400 - - or.w 0x300,r3 - move r3,ccs - setf ui - sfe - move ccs,r3 - dumpr3 ; 0x419d8260 - - quit diff --git a/sim/testsuite/sim/cris/asm/subc.ms b/sim/testsuite/sim/cris/asm/subc.ms deleted file mode 100644 index 35d4e84..0000000 --- a/sim/testsuite/sim/cris/asm/subc.ms +++ /dev/null @@ -1,86 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n - - .include "testutils.inc" - start - moveq -1,r3 - sub.d -2,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - moveq 2,r3 - sub.d 1,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - move.d 0xffff,r3 - sub.d -0xffff,r3 - test_cc 0 0 0 1 - dumpr3 ; 1fffe - - moveq -1,r3 - sub.d 1,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - - move.d 0x78134452,r3 - sub.d -0x5432f789,r3 - test_cc 1 0 1 1 - dumpr3 ; cc463bdb - - moveq -1,r3 - sub.w -2,r3 - test_cc 0 0 0 0 - dumpr3 ; ffff0001 - - moveq 2,r3 - sub.w 1,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - move.d 0xffff,r3 - sub.w 1,r3 - test_cc 1 0 0 0 - dumpr3 ; fffe - - move.d 0xfedaffff,r3 - sub.w 1,r3 - test_cc 1 0 0 0 - dumpr3 ; fedafffe - - move.d 0x78134452,r3 - sub.w 0x877,r3 - test_cc 0 0 0 0 - dumpr3 ; 78133bdb - - moveq -1,r3 - sub.b -2,r3 - test_cc 0 0 0 0 - dumpr3 ; ffffff01 - - moveq 2,r3 - sub.b 1,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - move.d 0xff,r3 - sub.b 1,r3 - test_cc 1 0 0 0 - dumpr3 ; fe - - move.d 0xfeda49ff,r3 - sub.b 1,r3 - test_cc 1 0 0 0 - dumpr3 ; feda49fe - - move.d 0x78134452,r3 - sub.b 0x77,r3 - test_cc 1 0 0 1 - dumpr3 ; 781344db - - move.d 0x85649282,r3 - sub.b 0x82,r3 - test_cc 0 1 0 0 - dumpr3 ; 85649200 - - quit diff --git a/sim/testsuite/sim/cris/asm/subm.ms b/sim/testsuite/sim/cris/asm/subm.ms deleted file mode 100644 index d84f34a..0000000 --- a/sim/testsuite/sim/cris/asm/subm.ms +++ /dev/null @@ -1,96 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n - - .include "testutils.inc" - .data -x: - .dword -2,1,-0xffff,1,-0x5432f789 - .word -2,1,1,0x877 - .byte -2,1,0x77 - .byte 0x22 - - start - moveq -1,r3 - move.d x,r5 - sub.d [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - moveq 2,r3 - sub.d [r5],r3 - test_cc 0 0 0 0 - addq 4,r5 - dumpr3 ; 1 - - move.d 0xffff,r3 - sub.d [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 1fffe - - moveq -1,r3 - sub.d [r5+],r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - - move.d 0x78134452,r3 - sub.d [r5+],r3 - test_cc 1 0 1 1 - dumpr3 ; cc463bdb - - moveq -1,r3 - sub.w [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; ffff0001 - - moveq 2,r3 - sub.w [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - move.d 0xffff,r3 - sub.w [r5],r3 - test_cc 1 0 0 0 - dumpr3 ; fffe - - move.d 0xfedaffff,r3 - sub.w [r5+],r3 - test_cc 1 0 0 0 - dumpr3 ; fedafffe - - move.d 0x78134452,r3 - sub.w [r5+],r3 - test_cc 0 0 0 0 - dumpr3 ; 78133bdb - - moveq -1,r3 - sub.b [r5],r3 - test_cc 0 0 0 0 - addq 1,r5 - dumpr3 ; ffffff01 - - moveq 2,r3 - sub.b [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - move.d 0xff,r3 - sub.b [r5],r3 - test_cc 1 0 0 0 - dumpr3 ; fe - - move.d 0xfeda49ff,r3 - sub.b [r5+],r3 - test_cc 1 0 0 0 - dumpr3 ; feda49fe - - move.d 0x78134452,r3 - sub.b [r5+],r3 - test_cc 1 0 0 1 - dumpr3 ; 781344db - - move.d 0x85649222,r3 - sub.b [r5],r3 - test_cc 0 1 0 0 - dumpr3 ; 85649200 - - quit diff --git a/sim/testsuite/sim/cris/asm/subq.ms b/sim/testsuite/sim/cris/asm/subq.ms deleted file mode 100644 index 7b09267..0000000 --- a/sim/testsuite/sim/cris/asm/subq.ms +++ /dev/null @@ -1,52 +0,0 @@ -# mach: crisv3 crisv8 crisv10 crisv32 -# output: 0\nffffffff\nfffffffe\nffff\nff\n56788f9\n56788d9\n567889a\n0\n7ffffffc\n - - .include "testutils.inc" - start - moveq 1,r3 - subq 1,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - subq 1,r3 - test_cc 1 0 0 1 - dumpr3 ; ffffffff - - subq 1,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - - move.d 0x10000,r3 - subq 1,r3 - test_cc 0 0 0 0 - dumpr3 ; ffff - - move.d 0x100,r3 - subq 1,r3 - test_cc 0 0 0 0 - dumpr3 ; ff - - move.d 0x5678900,r3 - subq 7,r3 - test_cc 0 0 0 0 - dumpr3 ; 56788f9 - - subq 32,r3 - test_cc 0 0 0 0 - dumpr3 ; 56788d9 - - subq 63,r3 - test_cc 0 0 0 0 - dumpr3 ; 567889a - - move.d 34,r3 - subq 34,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x80000024,r3 - subq 40,r3 - test_cc 0 0 1 0 - dumpr3 ; 7ffffffc - - quit diff --git a/sim/testsuite/sim/cris/asm/subqpc.ms b/sim/testsuite/sim/cris/asm/subqpc.ms deleted file mode 100644 index e2679a3..0000000 --- a/sim/testsuite/sim/cris/asm/subqpc.ms +++ /dev/null @@ -1,8 +0,0 @@ -# mach: crisv3 crisv8 crisv10 -# xerror: -# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n - - .include "testutils.inc" - start - subq 31,pc - diff --git a/sim/testsuite/sim/cris/asm/subr.ms b/sim/testsuite/sim/cris/asm/subr.ms deleted file mode 100644 index ea77b77..0000000 --- a/sim/testsuite/sim/cris/asm/subr.ms +++ /dev/null @@ -1,102 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n - - .include "testutils.inc" - start - moveq -1,r3 - moveq -2,r4 - sub.d r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - moveq 2,r3 - moveq 1,r4 - sub.d r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - move.d 0xffff,r3 - move.d -0xffff,r4 - sub.d r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 1fffe - - moveq 1,r4 - moveq -1,r3 - sub.d r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fffffffe - - move.d -0x5432f789,r4 - move.d 0x78134452,r3 - sub.d r4,r3 - test_cc 1 0 1 1 - dumpr3 ; cc463bdb - - moveq -1,r3 - moveq -2,r4 - sub.w r4,r3 - test_cc 0 0 0 0 - dumpr3 ; ffff0001 - - moveq 2,r3 - moveq 1,r4 - sub.w r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - move.d 0xffff,r3 - move.d -0xffff,r4 - sub.w r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fffe - - move.d 0xfedaffff,r3 - move.d -0xfedaffff,r4 - sub.w r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fedafffe - - move.d -0x5432f789,r4 - move.d 0x78134452,r3 - sub.w r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 78133bdb - - moveq -1,r3 - moveq -2,r4 - sub.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; ffffff01 - - moveq 2,r3 - moveq 1,r4 - sub.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 1 - - move.d -0xff,r4 - move.d 0xff,r3 - sub.b r4,r3 - test_cc 1 0 0 0 - dumpr3 ; fe - - move.d -0xfeda49ff,r4 - move.d 0xfeda49ff,r3 - sub.b r4,r3 - test_cc 1 0 0 0 - dumpr3 ; feda49fe - - move.d -0x5432f789,r4 - move.d 0x78134452,r3 - sub.b r4,r3 - test_cc 1 0 0 1 - dumpr3 ; 781344db - - move.d 0x85649222,r3 - move.d 0x77445622,r4 - sub.b r4,r3 - test_cc 0 1 0 0 - dumpr3 ; 85649200 - - quit diff --git a/sim/testsuite/sim/cris/asm/subxc.ms b/sim/testsuite/sim/cris/asm/subxc.ms deleted file mode 100644 index bd76adb..0000000 --- a/sim/testsuite/sim/cris/asm/subxc.ms +++ /dev/null @@ -1,92 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n - - .include "testutils.inc" - start - moveq 2,r3 - subs.b 0xff,r3 - test_cc 0 0 0 1 - dumpr3 ; 3 - - moveq 2,r3 - subs.w 0xffff,r3 - test_cc 0 0 0 1 - dumpr3 ; 3 - - moveq 2,r3 - subu.b 0xff,r3 - test_cc 1 0 0 1 - dumpr3 ; ffffff03 - - moveq 2,r3 - move.d 0xffffffff,r4 - subu.w -1,r3 - test_cc 1 0 0 1 - dumpr3 ; ffff0003 - - move.d 0xffff,r3 - subu.b -1,r3 - test_cc 0 0 0 0 - dumpr3 ; ff00 - - move.d 0xffff,r3 - subu.w -1,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0xffff,r3 - subs.b 0xff,r3 - test_cc 0 0 0 1 - dumpr3 ; 10000 - - move.d 0xffff,r3 - subs.w 0xffff,r3 - test_cc 0 0 0 1 - dumpr3 ; 10000 - - moveq -1,r3 - subs.b 0xff,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - moveq -1,r3 - subs.w 0xff,r3 - test_cc 1 0 0 0 - dumpr3 ; ffffff00 - - moveq -1,r3 - subs.w 0xffff,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x78134452,r3 - subu.b 0x89,r3 - test_cc 0 0 0 0 - dumpr3 ; 781343c9 - - move.d 0x78134452,r3 - subs.b 0x89,r3 - test_cc 0 0 0 1 - dumpr3 ; 781344c9 - - move.d 0x78134452,r3 - subu.w 0xf789,r3 - test_cc 0 0 0 0 - dumpr3 ; 78124cc9 - - move.d 0x78134452,r3 - subs.w 0xf789,r3 - test_cc 0 0 0 1 - dumpr3 ; 78134cc9 - - move.d 0x4452,r3 - subs.w 0x8002,r3 - test_cc 0 0 0 1 - dumpr3 ; c450 - - move.d 0x80000032,r3 - subu.w 0x764,r3 - test_cc 0 0 1 0 - dumpr3 ; 7ffff8ce - - quit diff --git a/sim/testsuite/sim/cris/asm/subxm.ms b/sim/testsuite/sim/cris/asm/subxm.ms deleted file mode 100644 index a4537d1..0000000 --- a/sim/testsuite/sim/cris/asm/subxm.ms +++ /dev/null @@ -1,106 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n - - .include "testutils.inc" - .data -x: - .byte 0xff - .word 0xffff - .word 0xff - .word 0xffff - .byte 0x89 - .word 0xf789 - .word 0x8002 - .word 0x764 - - start - moveq 2,r3 - move.d x,r5 - subs.b [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 3 - - moveq 2,r3 - subs.w [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 3 - - moveq 2,r3 - subq 3,r5 - subu.b [r5+],r3 - test_cc 1 0 0 1 - dumpr3 ; ffffff03 - - moveq 2,r3 - subu.w [r5+],r3 - test_cc 1 0 0 1 - subq 3,r5 - dumpr3 ; ffff0003 - - move.d 0xffff,r3 - subu.b [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; ff00 - - move.d 0xffff,r3 - subu.w [r5],r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0xffff,r3 - subs.b [r5],r3 - test_cc 0 0 0 1 - dumpr3 ; 10000 - - move.d 0xffff,r3 - subs.w [r5],r3 - test_cc 0 0 0 1 - dumpr3 ; 10000 - - moveq -1,r3 - subs.b [r5],r3 - test_cc 0 1 0 0 - addq 3,r5 - dumpr3 ; 0 - - moveq -1,r3 - subs.w [r5+],r3 - test_cc 1 0 0 0 - dumpr3 ; ffffff00 - - moveq -1,r3 - subs.w [r5+],r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x78134452,r3 - subu.b [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; 781343c9 - - move.d 0x78134452,r3 - subs.b [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 781344c9 - - move.d 0x78134452,r3 - subu.w [r5],r3 - test_cc 0 0 0 0 - dumpr3 ; 78124cc9 - - move.d 0x78134452,r3 - subs.w [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; 78134cc9 - - move.d 0x4452,r3 - subs.w [r5+],r3 - test_cc 0 0 0 1 - dumpr3 ; c450 - - move.d 0x80000032,r3 - subu.w [r5+],r3 - test_cc 0 0 1 0 - dumpr3 ; 7ffff8ce - - quit diff --git a/sim/testsuite/sim/cris/asm/subxr.ms b/sim/testsuite/sim/cris/asm/subxr.ms deleted file mode 100644 index e894596..0000000 --- a/sim/testsuite/sim/cris/asm/subxr.ms +++ /dev/null @@ -1,108 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n - - .include "testutils.inc" - start - moveq 2,r3 - move.d 0xff,r4 - subs.b r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 3 - - moveq 2,r3 - move.d 0xffff,r4 - subs.w r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 3 - - moveq 2,r3 - move.d 0xffff,r4 - subu.b r4,r3 - test_cc 1 0 0 1 - dumpr3 ; ffffff03 - - moveq 2,r3 - move.d 0xffffffff,r4 - subu.w r4,r3 - test_cc 1 0 0 1 - dumpr3 ; ffff0003 - - move.d 0xffff,r3 - move.d 0xffffffff,r4 - subu.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; ff00 - - move.d 0xffff,r3 - move.d 0xffffffff,r4 - subu.w r4,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0xffff,r3 - move.d 0xff,r4 - subs.b r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 10000 - - move.d 0xffff,r4 - move.d r4,r3 - subs.w r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 10000 - - moveq -1,r3 - move.d 0xff,r4 - subs.b r4,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - moveq -1,r3 - move.d 0xff,r4 - subs.w r4,r3 - test_cc 1 0 0 0 - dumpr3 ; ffffff00 - - moveq -1,r3 - move.d 0xffff,r4 - subs.w r4,r3 - test_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - subu.b r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 781343c9 - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - subs.b r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 781344c9 - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - subu.w r4,r3 - test_cc 0 0 0 0 - dumpr3 ; 78124cc9 - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - subs.w r4,r3 - test_cc 0 0 0 1 - dumpr3 ; 78134cc9 - - move.d 0x4452,r3 - move.d 0x78568002,r4 - subs.w r4,r3 - test_cc 0 0 0 1 - dumpr3 ; c450 - - move.d 0x80000032,r3 - move.d 0xffff0764,r4 - subu.w r4,r3 - test_cc 0 0 1 0 - dumpr3 ; 7ffff8ce - - quit diff --git a/sim/testsuite/sim/cris/asm/swap.ms b/sim/testsuite/sim/cris/asm/swap.ms deleted file mode 100644 index de7ca49..0000000 --- a/sim/testsuite/sim/cris/asm/swap.ms +++ /dev/null @@ -1,87 +0,0 @@ -# mach: crisv8 crisv10 crisv32 -# output: 1ec8224a\n13785244\nc81e4a22\n44527813\n224a1ec8\n52441378\n4a22c81e\n87ecbbad\ne137ddb5\nec87adbb\n37e1b5dd\nbbad87ec\nddb5e137\nadbbec87\nb5dd37e1\n0\n - - .include "testutils.inc" - start - move.d 0x78134452,r4 - move.d r4,r3 - swapr r3 - test_move_cc 0 0 0 0 - dumpr3 ; 1ec8224a - - move.d r4,r3 - swapb r3 - test_move_cc 0 0 0 0 - dumpr3 ; 13785244 - - move.d r4,r3 - swapbr r3 - test_move_cc 1 0 0 0 - dumpr3 ; c81e4a22 - - move.d r4,r3 - swapw r3 - test_move_cc 0 0 0 0 - dumpr3 ; 44527813 - - move.d r4,r3 - swapwr r3 - test_move_cc 0 0 0 0 - dumpr3 ; 224a1ec8 - - move.d r4,r3 - swapwb r3 - test_move_cc 0 0 0 0 - dumpr3 ; 52441378 - - move.d r4,r3 - swapwbr r3 - test_move_cc 0 0 0 0 - dumpr3 ; 4a22c81e - - move.d r4,r3 - swapn r3 - test_move_cc 1 0 0 0 - dumpr3 ; 87ecbbad - - move.d r4,r3 - swapnr r3 - test_move_cc 1 0 0 0 - dumpr3 ; e137ddb5 - - move.d r4,r3 - swapnb r3 - test_move_cc 1 0 0 0 - dumpr3 ; ec87adbb - - move.d r4,r3 - swapnbr r3 - test_move_cc 0 0 0 0 - dumpr3 ; 37e1b5dd - - move.d r4,r3 - swapnw r3 - test_move_cc 1 0 0 0 - dumpr3 ; bbad87ec - - move.d r4,r3 - swapnwr r3 - test_move_cc 1 0 0 0 - dumpr3 ; ddb5e137 - - move.d r4,r3 - swapnwb r3 - test_move_cc 1 0 0 0 - dumpr3 ; adbbec87 - - move.d r4,r3 - swapnwbr r3 - test_move_cc 1 0 0 0 - dumpr3 ; b5dd37e1 - - moveq -1,r3 - swapnwbr r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/tb.ms b/sim/testsuite/sim/cris/asm/tb.ms deleted file mode 100644 index eb6eaf9..0000000 --- a/sim/testsuite/sim/cris/asm/tb.ms +++ /dev/null @@ -1,72 +0,0 @@ -#mach: crisv32 -#output: Basic clock cycles, total @: 54\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 18\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - -; Check branch penalties. It is assumed that the taken-counters -; in the bimodal branch-predictors start at 0, meaning two taken -; branches are required for a branch to be predicted as taken -; for each counter, from reset. None of these branches go -; to the end of a cache-line and none map to the same counter. - - .include "testutils.inc" - startnostack - ba 0f ; No penalty: always-taken condition not "predicted". - nop - nop -0: - setf c - bcs 0f ; Penalty 2 cycles. - nop - - nop -0: - clearf c - bcc 0f ; Penalty 2 cycles, though branch is a nop. - moveq 4,r0 ; Execute 5 times: - -0: - move.d r0,r0 - bne 0b ; Mispredicted 3 out of 5 times: penalty 3*2 cycles. - subq 1,r0 - -0: - beq 0f ; Not taken; no penalty. - nop - - nop -0: - -; (Almost) same insns, but with 16-bit bCC insns. - - ba 0f ; No penalty: always-taken condition not "predicted". - nop - .space 520 -0: - setf c - bcs 0f ; Penalty 2 cycles. - nop - - .space 520 -0: - moveq 4,r0 ; Execute 5 times: -0: - ba 1f - move.d r0,r0 ; Mispredicted 3 out of 5 times: - .space 520 -1: - bne 0b ; Penalty 3*2 cycles. - subq 1,r0 - - beq 0f ; Not taken; no penalty. - nop -0: - break 15 diff --git a/sim/testsuite/sim/cris/asm/test.ms b/sim/testsuite/sim/cris/asm/test.ms deleted file mode 100644 index 93c4f59..0000000 --- a/sim/testsuite/sim/cris/asm/test.ms +++ /dev/null @@ -1,80 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 1\n - - .include "testutils.inc" - .data -x: - .dword 0,2,-1,0x80000000,0x5432f789 - .word 0,2,-1,0xffff,0xf789 - .byte 0,2,0xff,0x89 - - start - clearf nzvc - moveq -1,r3 - move.d x,r5 - setf vc - test.d [r5+] - test_cc 0 1 0 0 - - setf vc - test.d [r5] - test_cc 0 0 0 0 - - addq 4,r5 - - setf vc - test.d [r5+] - test_cc 1 0 0 0 - - setf vc - test.d [r5+] - test_cc 1 0 0 0 - - setf vc - test.d [r5+] - test_cc 0 0 0 0 - - setf vc - test.w [r5+] - test_cc 0 1 0 0 - - setf vc - test.w [r5] - test_cc 0 0 0 0 - - addq 2,r5 - - setf vc - test.w [r5+] - test_cc 1 0 0 0 - - setf vc - test.w [r5+] - test_cc 1 0 0 0 - - setf vc - test.w [r5+] - test_cc 1 0 0 0 - - setf vc - test.b [r5] - test_cc 0 1 0 0 - - addq 1,r5 - - setf vc - test.b [r5+] - test_cc 0 0 0 0 - - setf vc - test.b [r5+] - test_cc 1 0 0 0 - - setf vc - test.b [r5] - test_cc 1 0 0 0 - - moveq 1,r3 - dumpr3 - - quit diff --git a/sim/testsuite/sim/cris/asm/testutils.inc b/sim/testsuite/sim/cris/asm/testutils.inc deleted file mode 100644 index 962f4fc..0000000 --- a/sim/testsuite/sim/cris/asm/testutils.inc +++ /dev/null @@ -1,361 +0,0 @@ -; Copied from fr30 and modified. -; r9, r11-r13 are used as tmps, consider them call clobbered by these macros. -; -; Do not use the macro counter \@ in macros, there's a bug in -; gas 2.9.1 when it is also a line-separator. -; - - ; Don't require the $-prefix on registers. - .syntax no_register_prefix - - .macro startnostack - .data - .space 64,0 ; Simple stack -stackhi: -failmsg: - .ascii "fail\n" -passmsg: - .ascii "pass\n" - .text - break 11 - .global _start -_start: - .endm - - .macro start - startnostack - move.d stackhi,sp - .endm - -; Exit with return code - .macro exit rc - move.d \rc,r10 - moveq 1,r9 ; == __NR_exit - break 13 - break 15 - .endm - -; Pass the test case - .macro pass - moveq 5,r12 - move.d passmsg,r11 - move.d 1,r10 - moveq 4,r9 ; == __NR_write - break 13 - exit 0 - .endm - -; Fail the testcase - .macro fail -; moveq 5,r12 -; move.d failmsg,r11 -; move.d 1,r10 -; moveq 4,r1 -; break 13 -; exit 1 - break 15 - .endm - - .macro quit - break 15 - .endm - - .macro dumpr3 - break 14 - .endm - -; Load an immediate value into a general register -; TODO: use minimal sized insn - .macro mvi_h_gr val reg - move.d \val,\reg - .endm - -; Load an immediate value into a dedicated register - .macro mvi_h_dr val reg - move.d \val,r9 - move.d r9,\reg - .endm - -; Load a general register into another general register - .macro mvr_h_gr src targ - move.d \src,\targ - .endm - -; Store an immediate into a word in memory - .macro mvi_h_mem val addr - mvi_h_gr \val r11 - mvr_h_mem r11,\addr - .endm - -; Store a register into a word in memory - .macro mvr_h_mem reg addr - move.d \addr,$r13 - move.d \reg,[$r13] - .endm - -; Store the current ps on the stack - .macro save_ps - .if ..asm.arch.cris.v32 - move ccs,acr ; Push will do a "subq" first. - push acr - .else - push dccr - .endif - .endm - -; Load a word value from memory - .macro ldmem_h_gr addr reg - move.d \addr,$r13 - move.d [$r13],\reg - .endm - -; Add 2 general registers - .macro add_h_gr reg1 reg2 - add.d \reg1,\reg2 - .endm - -; Increment a register by and immediate - .macro inci_h_gr inc reg - mvi_h_gr \inc,r11 - add.d r11,\reg - .endm - -; Test the value of an immediate against a general register - .macro test_h_gr val reg - cmp.d \val,\reg - beq 9f - nop - fail -9: - .endm - -; compare two general registers - .macro testr_h_gr reg1 reg2 - cmp.d \reg1,\reg2 - beq 9f - fail -9: - .endm - -; Test the value of an immediate against a dedicated register - .macro test_h_dr val reg - move \reg,$r12 - test_h_gr \val $r12 - .endm - -; Test the value of an general register against a dedicated register - .macro testr_h_dr gr dr - move \dr,$r12 - testr_h_gr \gr $r12 - .endm - -; Compare an immediate with word in memory - .macro test_h_mem val addr - ldmem_h_gr \addr $r12 - test_h_gr \val $r12 - .endm - -; Compare a general register with word in memory - .macro testr_h_mem reg addr - ldmem_h_gr \addr r12 - testr_h_gr \reg r12 - .endm - -; Set the condition codes -; The lower bits of the mask *are* nzvc, so we don't -; have to do anything strange. - .macro set_cc mask - move.w \mask,r13 - .if ..asm.arch.cris.v32 - move r13,ccs - .else - move r13,ccr - .endif - .endm - -; Set the stack mode -; .macro set_s_user -; orccr 0x20 -; .endm -; -; .macro set_s_system -; andccr 0x1f -; .endm -; -;; Test the stack mode -; .macro test_s_user -; mvr_h_gr ps,r9 -; mvi_h_gr 0x20,r11 -; and r11,r9 -; test_h_gr 0x20,r9 -; .endm -; -; .macro test_s_system -; mvr_h_gr ps,r9 -; mvi_h_gr 0x20,r11 -; and r11,r9 -; test_h_gr 0x0,r9 -; .endm - -; Set the interrupt bit -; ??? Do they mean "enable interrupts" or "disable interrupts"? -; Assuming enable here. - .macro set_i val - .if (\val == 1) - ei - .else - di - .endif - .endm - -; Test the stack mode -; .macro test_i val -; mvr_h_gr ps,r9 -; mvi_h_gr 0x10,r11 -; and r11,r9 -; .if (\val == 1) -; test_h_gr 0x10,r9 -; .else -; test_h_gr 0x0,r9 -; .endif -; .endm -; -;; Set the ilm -; .macro set_ilm val -; stilm \val -; .endm -; -;; Test the ilm -; .macro test_ilm val -; mvr_h_gr ps,r9 -; mvi_h_gr 0x1f0000,r11 -; and r11,r9 -; mvi_h_gr \val,r12 -; mvi_h_gr 0x1f,r11 -; and r11,r12 -; lsl 15,r12 -; lsl 1,r12 -; testr_h_gr r9,r12 -; .endm -; -; Test the condition codes - .macro test_cc N Z V C - .if \N - bpl 9f - nop - .else - bmi 9f - nop - .endif - .if \Z - bne 9f - nop - .else - beq 9f - nop - .endif - .if \V - bvc 9f - nop - .else - bvs 9f - nop - .endif - .if \C - bcc 9f - nop - .else - bcs 9f - nop - .endif - ba 8f - nop -9: - fail -8: - .endm - - .macro test_move_cc N Z V C - .if ..asm.arch.cris.v32 - ; V and C aren't affected on v32, so to re-use the test-cases, - ; we fake them cleared. There's a separate test, nonvcv32.ms - ; covering this omission. - clearf vc - test_cc \N \Z 0 0 - .else - test_cc \N \Z \V \C - .endif - .endm - -; Set the division bits -; .macro set_dbits val -; mvr_h_gr ps,r12 -; mvi_h_gr 0xfffff8ff,r11 -; and r11,r12 -; mvi_h_gr \val,r9 -; mvi_h_gr 3,r11 -; and r11,r9 -; lsl 9,r9 -; or r9,r12 -; mvr_h_gr r12,ps -; .endm -; -;; Test the division bits -; .macro test_dbits val -; mvr_h_gr ps,r9 -; lsr 9,r9 -; mvi_h_gr 3,r11 -; and r11,r9 -; test_h_gr \val,r9 -; .endm -; -; Save the return pointer - .macro save_rp - push srp - .ENDM - -; restore the return pointer - .macro restore_rp - pop srp - .endm - -; Ensure branch taken - .macro take_branch opcode - \opcode 9f - nop - fail -9: - .endm - - .macro take_branch_d opcode val - \opcode 9f - nop - move.d \val,r9 - fail -9: - test_h_gr \val,r9 - .endm - -; Ensure branch not taken - .macro no_branch opcode - \opcode 9f - nop - ba 8f - nop -9: - fail -8: - .endm - - .macro no_branch_d opcode val - \opcode 9f - move.d \val,r9 - nop - ba 8f - nop -9: - fail -8: - test_h_gr \val,r9 - .endm - diff --git a/sim/testsuite/sim/cris/asm/tjmpsrv32-2.ms b/sim/testsuite/sim/cris/asm/tjmpsrv32-2.ms deleted file mode 100644 index dee0b29..0000000 --- a/sim/testsuite/sim/cris/asm/tjmpsrv32-2.ms +++ /dev/null @@ -1,55 +0,0 @@ -#mach: crisv32 -#output: Basic clock cycles, total @: 37\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 6\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - -; Check that we correctly account for that a "jas N,Pn", -; "jasc N,Pn", "bas N,Pn" and "basc N,Pn" sets the specific -; special register and causes a pipeline hazard. The amount -; of nops below is a bit inflated, in an attempt to make -; errors more discernible. For special registers, we just -; check SRP. - - .include "testutils.inc" - startnostack - move.d 0f,$r0 - jsr 0f - nop - nop - nop - jsrc 0f - nop - .dword -1 - nop - nop - jsr $r0 - nop - nop - nop - jsrc $r0 - nop - .dword -1 - nop - nop - bsr 0f - nop - nop - nop - bsrc 0f - nop - .dword -1 - nop - nop - break 15 - -0: - ret ; 1 cycle penalty. - nop diff --git a/sim/testsuite/sim/cris/asm/tjmpsrv32.ms b/sim/testsuite/sim/cris/asm/tjmpsrv32.ms deleted file mode 100644 index 1781c4f..0000000 --- a/sim/testsuite/sim/cris/asm/tjmpsrv32.ms +++ /dev/null @@ -1,50 +0,0 @@ -#mach: crisv32 -#output: Basic clock cycles, total @: 17\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 5\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - -; Check that "ret"-type insns get the right number of penalty -; cycles for the special register source. - - .include "testutils.inc" - startnostack - move.d 1f,$r1 - move.d 0f,$r0 - move $r0,$mof - jump $mof ; 2 cycles penalty. - nop - -0: - move [$r1],$srp - nop - ret ; 1 cycle penalty. - nop - - break 15 - -0: - move 2f,$nrp - nop - nop - jump $nrp ; no penalty. - nop - - break 15 - -2: - move 3f,$srp ; 2 cycles penalty. - ret - nop - -3: - break 15 -1: - .dword 0b diff --git a/sim/testsuite/sim/cris/asm/tjsrcv10.ms b/sim/testsuite/sim/cris/asm/tjsrcv10.ms deleted file mode 100644 index 3bc6946..0000000 --- a/sim/testsuite/sim/cris/asm/tjsrcv10.ms +++ /dev/null @@ -1,29 +0,0 @@ -#mach: crisv10 -#output: Basic clock cycles, total @: 6\n -#output: Memory source stall cycles: 1\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - -; Check that the 4-byte-skip doesn't make the simulator barf. -; Nothing deeper. - - .include "testutils.inc" - startnostack - nop - move.d 0f,r5 - jsrc r5 - nop - .dword -1 -0: - jsrc 1f - nop - .dword -2 -1: - break 15 diff --git a/sim/testsuite/sim/cris/asm/tjsrcv32.ms b/sim/testsuite/sim/cris/asm/tjsrcv32.ms deleted file mode 100644 index a777f01..0000000 --- a/sim/testsuite/sim/cris/asm/tjsrcv32.ms +++ /dev/null @@ -1,13 +0,0 @@ -#mach: crisv32 -#output: Basic clock cycles, total @: 6\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 2\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - .include "tjsrcv10.ms" diff --git a/sim/testsuite/sim/cris/asm/tmemv10.ms b/sim/testsuite/sim/cris/asm/tmemv10.ms deleted file mode 100644 index 40b32a9..0000000 --- a/sim/testsuite/sim/cris/asm/tmemv10.ms +++ /dev/null @@ -1,27 +0,0 @@ -#mach: crisv10 -#output: Basic clock cycles, total @: 8\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - -; Check that the memory indirection doesn't make the simulator barf. -; Nothing deeper. - - .include "testutils.inc" - startnostack - move.d 0f,r5 - move.d [r5],r4 - move.d [r5+],r3 - move.d [r5],r2 - break 15 - nop - .p2align 2 -0: - .dword 1,2,3 diff --git a/sim/testsuite/sim/cris/asm/tmemv32.ms b/sim/testsuite/sim/cris/asm/tmemv32.ms deleted file mode 100644 index 81ce211..0000000 --- a/sim/testsuite/sim/cris/asm/tmemv32.ms +++ /dev/null @@ -1,14 +0,0 @@ -#mach: crisv32 -#output: Basic clock cycles, total @: 4\n -#output: Memory source stall cycles: 1\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - - .include "tmemv10.ms" diff --git a/sim/testsuite/sim/cris/asm/tmulv10.ms b/sim/testsuite/sim/cris/asm/tmulv10.ms deleted file mode 100644 index 3d855a2..0000000 --- a/sim/testsuite/sim/cris/asm/tmulv10.ms +++ /dev/null @@ -1,26 +0,0 @@ -#mach: crisv10 -#output: Basic clock cycles, total @: 9\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - -; Check that multiplications do not make the simulator barf. -; Nothing deeper. - - .include "testutils.inc" - startnostack - moveq 1,r3 - moveq 2,r1 - moveq 1,r0 - muls.d r0,r1 - muls.d r0,r3 - mulu.d r1,r3 - break 15 - nop diff --git a/sim/testsuite/sim/cris/asm/tmulv32.ms b/sim/testsuite/sim/cris/asm/tmulv32.ms deleted file mode 100644 index 3326054..0000000 --- a/sim/testsuite/sim/cris/asm/tmulv32.ms +++ /dev/null @@ -1,14 +0,0 @@ -#mach: crisv32 -#output: Basic clock cycles, total @: 6\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 2\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - - .include "tmulv10.ms" diff --git a/sim/testsuite/sim/cris/asm/tmvm1.ms b/sim/testsuite/sim/cris/asm/tmvm1.ms deleted file mode 100644 index c1c925d..0000000 --- a/sim/testsuite/sim/cris/asm/tmvm1.ms +++ /dev/null @@ -1,53 +0,0 @@ -#mach: crisv32 -#output: Basic clock cycles, total @: 18\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 6\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - -; Check that movem to register followed by register write dword -; to one of the registers is logged as needing two stall cycles, -; regardless of size. - - .include "testutils.inc" - startnostack - move.d 0f,r5 - moveq 0,r8 - moveq 0,r9 - - movem [r5],r4 - move.d r8,r1 - addq 1,r1 ; 2 cycles. - - movem [r5],r4 - move.w r8,r1 - addq 1,r1 ; 2 cycles. - - movem [r5],r4 - move.b r8,r1 - addq 1,r1 ; 2 cycles. - - movem [r5],r4 - move.b r8,r1 - addq 1,r9 - - movem [r5],r4 - move.d r8,r1 - addq 1,r8 - - break 15 - - .data - .p2align 5 -0: - .dword 0b - .dword 0b - .dword 0b - .dword 0b - .dword 0b diff --git a/sim/testsuite/sim/cris/asm/tmvm2.ms b/sim/testsuite/sim/cris/asm/tmvm2.ms deleted file mode 100644 index 176d3cc..0000000 --- a/sim/testsuite/sim/cris/asm/tmvm2.ms +++ /dev/null @@ -1,351 +0,0 @@ -#mach: crisv32 -#output: Basic clock cycles, total @: *\n -#output: Memory source stall cycles: 82\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 6\n -#output: Movem destination stall cycles: 880\n -#output: Movem address stall cycles: 4\n -#output: Multiplication source stall cycles: 18\n -#output: Jump source stall cycles: 6\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - - .include "testutils.inc" - -; Macros for testing correctness of movem destination stall -; cycles for various insn types. Beware: macro parameters can -; be comma or space-delimited. There are problems (i.e. bugs) -; with using space-delimited operands and operands with -; non-alphanumeric characters, like "[]-." so use comma for -; them. Lots of trouble passing empty parameters and parameters -; with comma. Ugh. FIXME: Report bugs, fix bugs, fix other -; shortcomings, fix that darn old macro-parameter-in-string. - -; Helper macro. Unfortunately I find no cleaner way to unify -; one and two-operand cases, the main problem being the comma -; operand delimiter clashing with macro operand delimiter. - .macro t_S_x_y S insn x y=none - movem [r7],r6 - .ifc \y,none - .ifc \S,none - \insn \x - .else - \insn\S \x - .endif - .else - .ifc \S,none - \insn \x,\y - .else - \insn\S \x,\y - .endif - .endif - nop - nop - nop - .endm - -; An insn-type that has a single register operand. The register -; may or may not be a source register for the insn. - .macro t_r insn - t_S_x_y none,\insn,r3 - t_S_x_y none,\insn,r8 - .endm - -; An insn-type that jumps to the destination of the register. - .macro t_r_j insn - move.d 0f,r7 - move.d 1f,r8 - move.d r8,r9 - nop - nop - nop - .section ".rodata" - .p2align 5 -0: - .dword 1f - .dword 1f - .dword 1f - .dword 1f - .dword 1f - .dword 1f - .dword 1f - .previous - t_r \insn -1: - .endm - -; An insn-type that has a size-modifier and two register -; operands. - .macro t_xr_r S insn - t_S_x_y \S \insn r3 r8 - t_S_x_y \S \insn r8 r3 - move.d r3,r9 - t_S_x_y \S \insn r4 r3 - t_S_x_y \S \insn r8 r9 - .endm - -; An insn-type that has two register operands. - .macro t_r_r insn - t_xr_r none \insn - .endm - -; An t_r_rx insn with a byte or word-size modifier. - .macro t_wbr_r insn - t_xr_r .b,\insn - t_xr_r .w,\insn - .endm - -; Ditto with a dword-size modifier. - .macro t_dwbr_r insn - t_xr_r .d,\insn - t_wbr_r \insn - .endm - -; An insn-type that has a size-modifier, a constant and a -; register operand. - .macro t_xc_r S insn - t_S_x_y \S \insn 24 r3 - move.d r3,r9 - t_S_x_y \S \insn 24 r8 - .endm - -; An insn-type that has a constant and a register operand. - .macro t_c_r insn - t_xc_r none \insn - .endm - -; An t_c_r insn with a byte or word-size modifier. - .macro t_wbc_r insn - t_xc_r .b,\insn - t_xc_r .w,\insn - .endm - -; Ditto with a dword-size modifier. - .macro t_dwbc_r insn - t_xc_r .d,\insn - t_wbc_r \insn - .endm - -; An insn-type that has size-modifier, a memory operand and a -; register operand. - .macro t_xm_r S insn - move.d 9b,r8 - t_S_x_y \S,\insn,[r4],r3 - move.d r3,r9 - t_S_x_y \S,\insn,[r8],r5 - move.d r5,r9 - t_S_x_y \S,\insn,[r3],r9 - t_S_x_y \S,\insn,[r8],r9 - .endm - -; Ditto, to memory. - .macro t_xr_m S insn - move.d 9b,r8 - t_S_x_y \S,\insn,r3,[r4] - t_S_x_y \S,\insn,r8,[r3] - t_S_x_y \S,\insn,r3,[r8] - t_S_x_y \S,\insn,r9,[r8] - .endm - -; An insn-type that has a memory operand and a register operand. - .macro t_m_r insn - t_xm_r none \insn - .endm - -; An t_m_r insn with a byte or word-size modifier. - .macro t_wbm_r insn - t_xm_r .b,\insn - t_xm_r .w,\insn - .endm - -; Ditto with a dword-size modifier. - .macro t_dwbm_r insn - t_xm_r .d,\insn - t_wbm_r \insn - .endm - -; Insn types of the regular type (r, c, m, size d w b). - .macro t_dwb insn - t_dwbr_r \insn - t_dwbc_r \insn - t_dwbm_r \insn - .endm - -; Similar, sizes w b. - .macro t_wb insn - t_wbr_r \insn - t_wbc_r \insn - t_wbm_r \insn - .endm - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - - startnostack - -; Initialize registers so they don't contain unknowns. - - move.d 9f,r7 - move.d r7,r8 - moveq 0,r9 - -; Movem source area. Register contents must be valid -; addresses, aligned on a cache boundary. - .section ".rodata" - .p2align 5 -9: - .dword 9b - .dword 9b - .dword 9b - .dword 9b - .dword 9b - .dword 9b - .dword 9b - .dword 9b - .dword 9b - .dword 9b - .previous - -; The actual tests. The numbers in the comments specify the -; number of movem destination stall cycles. Some of them may be -; filed as memory source address stalls, multiplication source -; stalls or jump source stalls, duly marked so. - - t_r_r abs ; 3+3 - - t_dwb add ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) - - t_r_r addc ; (3+3+3) - t_c_r addc ; 3 - t_m_r addc ; (3+3+3) (2 mem src) - - t_dwb move ; (3+3)+(3+3+3)*2+3*2+(3+3+3)*3 (6 mem src) - t_xr_m .b move ; 3+3+3 (2 mem src) - t_xr_m .w move ; 3+3+3 (2 mem src) - t_xr_m .d move ; 3+3+3 (2 mem src) - - t_S_x_y none addi r3.b r8 ; 3 - t_S_x_y none addi r8.w r3 ; 3 - t_S_x_y none addi r4.d r3 ; 3 - t_S_x_y none addi r8.w r9 - - ; Addo has three-operand syntax, so we have to expand (a useful - ; subset of) "t_dwb". - t_S_x_y none addi r3.b "r8,acr" ; 3 - t_S_x_y none addi r8.w "r3,acr" ; 3 - t_S_x_y none addi r4.d "r3,acr" ; 3 - t_S_x_y none addi r8.w "r9,acr" - - t_S_x_y .b addo 42 "r8,acr" - t_S_x_y .w addo 4200 "r3,acr" ; 3 - t_S_x_y .d addo 420000 "r3,acr" ; 3 - - move.d 9b,r8 - t_S_x_y .d,addo,[r4],"r3,acr" ; 3 (1 mem src) - t_S_x_y .b,addo,[r3],"r8,acr" ; 3 (1 mem src) - t_S_x_y .w,addo,[r8],"r3,acr" ; 3 - t_S_x_y .w,addo,[r8],"r9,acr" - - ; Similar for addoq. - t_S_x_y none addoq 42 "r8,acr" - t_S_x_y none addoq 42 "r3,acr" ; 3 - - t_c_r addq ; 3 - - t_wb adds ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) - t_wb addu ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) - - t_dwb and ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) - t_c_r andq ; 3 - - t_dwbr_r asr ; (3+3+3)*3 - t_c_r asrq ; 3 - - t_dwbr_r bound ; (3+3+3)*3 - t_dwbc_r bound ; 3*3 - - t_r_r btst ; (3+3+3) - t_c_r btstq ; 3 - - t_dwb cmp ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) - t_c_r cmpq ; 3 - - t_wbc_r cmps ; 3*2 - t_wbc_r cmpu ; 3*2 - t_wbm_r cmps ; (3+3+3)*2 (4 mem src) - t_wbm_r cmpu ; (3+3+3)*2 (4 mem src) - - t_r_r dstep ; (3+3+3) - - ; FIXME: idxd, fidxi, ftagd, ftagi when supported. - - t_r_j jsr ; 3 (2 jump src) - t_r_j jump ; 3 (2 jump src) - - t_c_r lapc.d - -; The "quick operand" must be in range [. to .+15*2] so we can't -; use t_c_r. - t_S_x_y none lapcq .+4 r3 - t_S_x_y none lapcq .+4 r8 - - t_dwbr_r lsl ; (3+3+3)*3 - t_c_r lslq ; 3 - - t_dwbr_r lsr ; (3+3+3)*3 - t_c_r lsrq ; 3 - - t_r_r lz ; 3+3 - - t_S_x_y none mcp srp r3 ; 3 - t_S_x_y none mcp srp r8 - - t_c_r moveq - - t_S_x_y none move srp r8 - t_S_x_y none move srp r3 - t_S_x_y none move r8 srp - t_S_x_y none move r3 srp ; 3 - -; FIXME: move supreg,Rd and move Rs,supreg when supported. - - t_wb movs ; (3+3)*2+0+(3+3)*2 (4 mem src) - t_wb movu ; (3+3)*2+0+(3+3)*2 (4 mem src) - - t_dwbr_r muls ; (3+3+3)*3 (9 mul src) - t_dwbr_r mulu ; (3+3+3)*3 (9 mul src) - - t_dwbr_r neg ; (3+3)*3 - - t_r not ; 3 cycles. - - t_dwb or ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) - t_c_r orq ; 3 - - t_r seq - - t_dwb sub ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) - t_c_r subq ; 3 - - t_wb subs ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) - t_wb subu ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) - - t_r swapw ; 3 cycles. - t_r swapnwbr ; 3 cycles. - - t_r_j jsrc ; 3 (2 jump src) - - t_r_r xor ; (3+3+3) - - move.d 9b,r7 - nop - nop - nop - t_xm_r none movem ; (3+3) (2 mem src, 1+1 movem addr) - ; As implied by the comment, all movem destination penalty - ; cycles (but one) are accounted for as memory source address - ; and movem source penalties. There are also two movem address - ; cache-line straddle penalties. - t_xr_m none movem ; (3+3+2+2) (2 mem, 6 movem src, +2 movem addr) - - break 15 diff --git a/sim/testsuite/sim/cris/asm/tmvmrv10.ms b/sim/testsuite/sim/cris/asm/tmvmrv10.ms deleted file mode 100644 index 66b9b1f..0000000 --- a/sim/testsuite/sim/cris/asm/tmvmrv10.ms +++ /dev/null @@ -1,50 +0,0 @@ -#mach: crisv10 -#output: Basic clock cycles, total @: 45\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - -; Check that movem to register basically looks ok cycle-wise. -; Nothing deep. - - .include "testutils.inc" - startnostack - move.d 0f,r5 - moveq 0,r8 - moveq 0,r9 - -; Adapted from crisv32 movem-to-memory penalty examples many -; revisions ago. - - movem [r5],r4 - test.d [r3] ; 3 cycle penalty on v32 (2 memory source, 1 movem dest). - movem [r5],r4 - subq 1,r8 - test.d [r3] ; 2 cycle penalty on v32. - movem [r5],r4 - subq 1,r1 ; 3 cycle penalty on v32. - movem [r5],r4 - add.d r8,r9 - subq 1,r1 ; 2 cycle penalty on v32. - movem [r5],r4 - add.d r8,r9 - subq 1, r9 - subq 1, r1 ; 1 cycle penalty on v32. - break 15 - - .data - .p2align 5 -0: - .dword 0b - .dword 0b - .dword 0b - .dword 0b - .dword 0b - diff --git a/sim/testsuite/sim/cris/asm/tmvmrv32.ms b/sim/testsuite/sim/cris/asm/tmvmrv32.ms deleted file mode 100644 index 0501747..0000000 --- a/sim/testsuite/sim/cris/asm/tmvmrv32.ms +++ /dev/null @@ -1,14 +0,0 @@ -#mach: crisv32 -#output: Basic clock cycles, total @: 17\n -#output: Memory source stall cycles: 1\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 10\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - - .include "tmvmrv10.ms" diff --git a/sim/testsuite/sim/cris/asm/tmvrmv10.ms b/sim/testsuite/sim/cris/asm/tmvrmv10.ms deleted file mode 100644 index c782997..0000000 --- a/sim/testsuite/sim/cris/asm/tmvrmv10.ms +++ /dev/null @@ -1,40 +0,0 @@ -#mach: crisv10 -#output: Basic clock cycles, total @: 31\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 0\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - -; Check that movem to memory basically looks ok cycle-wise. -; Nothing deep. - - .include "testutils.inc" - startnostack - move.d 0f,r4 - moveq 0,r0 - moveq 1,r3 - moveq 2,r1 - moveq 1,r2 - movem r3,[r4] ; 2 cycles penalty for v32 - movem r3,[r4] ; 0 cycles penalty for v32 - moveq 1,r3 - nop - movem r3,[r4] ; 1 cycle penalty for v32 - moveq 1,r3 - nop - nop - movem r3,[r4] ; 0 cycles penalty for v32 - break 15 - - .data -0: - .dword 0 - .dword 0 - .dword 0 - .dword 0 diff --git a/sim/testsuite/sim/cris/asm/tmvrmv32.ms b/sim/testsuite/sim/cris/asm/tmvrmv32.ms deleted file mode 100644 index 339ab20..0000000 --- a/sim/testsuite/sim/cris/asm/tmvrmv32.ms +++ /dev/null @@ -1,14 +0,0 @@ -#mach: crisv32 -#output: Basic clock cycles, total @: 14\n -#output: Memory source stall cycles: 0\n -#output: Memory read-after-write stall cycles: 0\n -#output: Movem source stall cycles: 3\n -#output: Movem destination stall cycles: 0\n -#output: Movem address stall cycles: 0\n -#output: Multiplication source stall cycles: 0\n -#output: Jump source stall cycles: 0\n -#output: Branch misprediction stall cycles: 0\n -#output: Jump target stall cycles: 0\n -#sim: --cris-cycles=basic - - .include "tmvrmv10.ms" diff --git a/sim/testsuite/sim/cris/asm/user.ms b/sim/testsuite/sim/cris/asm/user.ms deleted file mode 100644 index f6115bb..0000000 --- a/sim/testsuite/sim/cris/asm/user.ms +++ /dev/null @@ -1,75 +0,0 @@ -# mach: crisv32 -# output: 40\n40\n140\nabadefb0\n6543789c\n0\n0\n0\n0\n0\n0\n0\n0\n - -; Check for protected operations being NOP in user mode, for the -; parts implemented in this simulator. - - .include "testutils.inc" - start - move 0,ccs - move 0,usp - move 0,pid - move 0,srs - move 0,ebp - move 0,spc - setf u - -; Flag settings, besides what's tested in rfn.ms, rfe.ms and -; sfe.ms. - setf i - move ccs,r3 - dumpr3 ; 0x40 - - clearf u - move ccs,r3 - dumpr3 ; 0x40 - - move 0xc0000300,ccs - move ccs,r3 - dumpr3 ; 0x140 - -; R14==USP - move.d 0xabadefb0,r14 - nop - nop - nop - move usp,r3 - dumpr3 ; 0xabadefb0 - move 0x6543789c,usp - nop - nop - nop - move.d r14,r3 - dumpr3 ; 0x6543789c - -; We can't go back to kernel mode, so we can't check that R14 in -; kernel mode wasn't affected. - -; Moves to protected special registers. - .macro testsr reg,val=-1 - move \val,\reg - ; Registers shorter than dword will not affect the rest of the - ; general register when copied using a move insn. - clear.d r3 -; Three cycles are needed between move to protected register and -; read from it, to avoid reading undefined contents due to -; incomplete forwarding. - nop - nop - move \reg,r3 - dumpr3 - moveq \val,r3 - move r3,\reg - clear.d r3 - nop - nop - move \reg,r3 - dumpr3 - .endm - - testsr pid ; 0 0 - testsr srs,3 ; 0 0 - testsr ebp ; 0 0 - testsr spc ; 0 0 - - quit diff --git a/sim/testsuite/sim/cris/asm/x0-v10.ms b/sim/testsuite/sim/cris/asm/x0-v10.ms deleted file mode 100644 index 432819a..0000000 --- a/sim/testsuite/sim/cris/asm/x0-v10.ms +++ /dev/null @@ -1,7 +0,0 @@ -#mach: crisv10 -#ld: --section-start=.text=0 -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 0\n -#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 1\n -#sim: --cris-trace=basic - - .include "break.ms" diff --git a/sim/testsuite/sim/cris/asm/x0-v32.ms b/sim/testsuite/sim/cris/asm/x0-v32.ms deleted file mode 100644 index bbcb0ec..0000000 --- a/sim/testsuite/sim/cris/asm/x0-v32.ms +++ /dev/null @@ -1,7 +0,0 @@ -#mach: crisv32 -#ld: --section-start=.text=0 -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 0 0\n -#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 1 0\n -#sim: --cris-trace=basic - - .include "break.ms" diff --git a/sim/testsuite/sim/cris/asm/x1-v10.ms b/sim/testsuite/sim/cris/asm/x1-v10.ms deleted file mode 100644 index bfc4859..0000000 --- a/sim/testsuite/sim/cris/asm/x1-v10.ms +++ /dev/null @@ -1,10 +0,0 @@ -#mach: crisv10 -#ld: --section-start=.text=0 -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n -#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 2\n -#sim: --cris-trace=basic - -; With a "--cris-trace=all", cycles for the last line would be 3. - - .include "movect10.ms" diff --git a/sim/testsuite/sim/cris/asm/x1-v32.ms b/sim/testsuite/sim/cris/asm/x1-v32.ms deleted file mode 100644 index d37cfdd..0000000 --- a/sim/testsuite/sim/cris/asm/x1-v32.ms +++ /dev/null @@ -1,8 +0,0 @@ -#mach: crisv32 -#ld: --section-start=.text=0 -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n -#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 1 0\n -#sim: --cris-trace=basic - - .include "movect10.ms" diff --git a/sim/testsuite/sim/cris/asm/x10-v10.ms b/sim/testsuite/sim/cris/asm/x10-v10.ms deleted file mode 100644 index 4b7e4aa..0000000 --- a/sim/testsuite/sim/cris/asm/x10-v10.ms +++ /dev/null @@ -1,21 +0,0 @@ -#mach: crisv10 -#ld: --section-start=.text=0 -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n -#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 3\n -#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#sim: --cris-trace=basic - -; Check that "add.d x,pc" gets 3 cycles. - - .include "testutils.inc" - startnostack - nop - nop - add.d 1f-0f,$pc -0: - nop -1: - nop - break 15 diff --git a/sim/testsuite/sim/cris/asm/x2-v10.ms b/sim/testsuite/sim/cris/asm/x2-v10.ms deleted file mode 100644 index e2d5bbf..0000000 --- a/sim/testsuite/sim/cris/asm/x2-v10.ms +++ /dev/null @@ -1,59 +0,0 @@ -#mach: crisv10 -#ld: --section-start=.text=0 -#sim: --cris-trace=basic -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n -#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n -#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n -#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n -#output: 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 16 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 18 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 1a 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 16 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 18 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 1a 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 16 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 18 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 1a 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 18 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 1a 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n -#output: 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n -#output: 1a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n -#output: 1c ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n -#output: 1e ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n -#output: 20 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n -#output: 22 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n -#output: 26 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 2\n -#output: 230 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n -#output: 232 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n -#output: 236 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 2\n -#output: 440 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n -#output: 442 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 446 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: 650 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 654 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: 442 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 446 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: 650 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 654 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: 442 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 446 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: 650 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 654 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: 442 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 446 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: 650 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 654 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: 442 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n -#output: 446 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 2\n -#output: 650 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n -#output: 654 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 2\n -#output: 656 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n -#output: 658 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n -#output: 65a ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n - .include "tb.ms" diff --git a/sim/testsuite/sim/cris/asm/x2-v32.ms b/sim/testsuite/sim/cris/asm/x2-v32.ms deleted file mode 100644 index 0fdfcfd..0000000 --- a/sim/testsuite/sim/cris/asm/x2-v32.ms +++ /dev/null @@ -1,59 +0,0 @@ -#mach: crisv32 -#ld: --section-start=.text=0 -#sim: --cris-trace=basic -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n -#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n -#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n -#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n -#output: 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 16 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 18 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 1a 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 16 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 18 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 1a 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 16 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 18 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 1a 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 18 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 1a 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n -#output: 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n -#output: 1a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n -#output: 1c ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 1e ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 20 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 22 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 26 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 230 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 232 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 236 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 440 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 442 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 446 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 650 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n -#output: 654 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n -#output: 442 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 446 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 650 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 654 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 442 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 446 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 650 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 654 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 442 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 446 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 650 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 654 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 442 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n -#output: 446 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n -#output: 650 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n -#output: 654 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n -#output: 656 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 658 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n -#output: 65a ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n - .include "tb.ms" diff --git a/sim/testsuite/sim/cris/asm/x3-v10.ms b/sim/testsuite/sim/cris/asm/x3-v10.ms deleted file mode 100644 index fc54f3c..0000000 --- a/sim/testsuite/sim/cris/asm/x3-v10.ms +++ /dev/null @@ -1,12 +0,0 @@ -#mach: crisv10 -#ld: --section-start=.text=0 -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n -#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: 12 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 1e 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#sim: --cris-trace=basic - -; With a "--cris-trace=all", cycles for the third line would be 3. - - .include "tjsrcv10.ms" diff --git a/sim/testsuite/sim/cris/asm/x3-v32.ms b/sim/testsuite/sim/cris/asm/x3-v32.ms deleted file mode 100644 index 93a7436..0000000 --- a/sim/testsuite/sim/cris/asm/x3-v32.ms +++ /dev/null @@ -1,10 +0,0 @@ -#mach: crisv32 -#ld: --section-start=.text=0 -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n -#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 12 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 1e 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#sim: --cris-trace=basic - - .include "tjsrcv10.ms" diff --git a/sim/testsuite/sim/cris/asm/x4-v32.ms b/sim/testsuite/sim/cris/asm/x4-v32.ms deleted file mode 100644 index 056c05c..0000000 --- a/sim/testsuite/sim/cris/asm/x4-v32.ms +++ /dev/null @@ -1,23 +0,0 @@ -#mach: crisv32 -#ld: --section-start=.text=0 -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n -#output: 8 0 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 10 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 12 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 14 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 16 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 18 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 1a 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 1e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 24 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 26 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 28 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 2a 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 2e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 34 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 36 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 38 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#sim: --cris-trace=basic - - .include "tjmpsrv32.ms" diff --git a/sim/testsuite/sim/cris/asm/x5-v10.ms b/sim/testsuite/sim/cris/asm/x5-v10.ms deleted file mode 100644 index ec5023e..0000000 --- a/sim/testsuite/sim/cris/asm/x5-v10.ms +++ /dev/null @@ -1,9 +0,0 @@ -#mach: crisv10 -#ld: --section-start=.text=0 -#sim: --cris-trace=basic -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n -#output: 8 0 0 0 0 0 14 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: a 0 0 0 0 1 14 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: c 0 0 0 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: e 0 0 2 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 2\n - .include "tmemv10.ms" diff --git a/sim/testsuite/sim/cris/asm/x5-v32.ms b/sim/testsuite/sim/cris/asm/x5-v32.ms deleted file mode 100644 index 62b3fca..0000000 --- a/sim/testsuite/sim/cris/asm/x5-v32.ms +++ /dev/null @@ -1,9 +0,0 @@ -#mach: crisv32 -#ld: --section-start=.text=0 -#sim: --cris-trace=basic -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n -#output: 8 0 0 0 0 0 14 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: a 0 0 0 0 1 14 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: c 0 0 0 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: e 0 0 2 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n - .include "tmemv10.ms" diff --git a/sim/testsuite/sim/cris/asm/x6-v10.ms b/sim/testsuite/sim/cris/asm/x6-v10.ms deleted file mode 100644 index 910daf8..0000000 --- a/sim/testsuite/sim/cris/asm/x6-v10.ms +++ /dev/null @@ -1,11 +0,0 @@ -#mach: crisv10 -#ld: --section-start=.text=0 -#sim: --cris-trace=basic -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n -#output: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 6 0 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 8 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: a 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: c 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: e 1 2 0 2 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n - .include "tmulv10.ms" diff --git a/sim/testsuite/sim/cris/asm/x6-v32.ms b/sim/testsuite/sim/cris/asm/x6-v32.ms deleted file mode 100644 index 19c5ada..0000000 --- a/sim/testsuite/sim/cris/asm/x6-v32.ms +++ /dev/null @@ -1,11 +0,0 @@ -#mach: crisv32 -#ld: --section-start=.text=0 -#sim: --cris-trace=basic -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n -#output: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 6 0 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: 8 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: a 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: c 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n -#output: e 1 2 0 2 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n - .include "tmulv10.ms" diff --git a/sim/testsuite/sim/cris/asm/x7-v10.ms b/sim/testsuite/sim/cris/asm/x7-v10.ms deleted file mode 100644 index 8b548ff..0000000 --- a/sim/testsuite/sim/cris/asm/x7-v10.ms +++ /dev/null @@ -1,31 +0,0 @@ -#mach: crisv10 -#ld: --section-start=.text=0 -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n -#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: c 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 4\n -#output: e 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#output: 10 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n -#output: 14 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n -#output: 18 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n -#output: 20 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 4\n -#sim: --cris-trace=basic - -; With a "--cris-trace=all", cycles for the third and last line would be 5. - -; Check that prefix+insn are traced as one. - - .include "testutils.inc" - startnostack - nop - move.d [0f],r3 - nop - moveq 0,r4 - move.d [r3+r4.b],r5 - move.d [r3+4],r5 - bdap.d 0,r3 - move.d [r3],r5 - break 15 - .p2align 2 -0: - .dword 0b - .dword 0b diff --git a/sim/testsuite/sim/cris/asm/x7-v32.ms b/sim/testsuite/sim/cris/asm/x7-v32.ms deleted file mode 100644 index ea98ef0..0000000 --- a/sim/testsuite/sim/cris/asm/x7-v32.ms +++ /dev/null @@ -1,19 +0,0 @@ -#mach: crisv32 -#ld: --section-start=.text=0 -#sim: --cris-trace=basic -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n -#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvc 1 aa424243\n -#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 55212121\n -#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 1\n -#output: e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n - -; Check that trace with changing ACR works. - - .include "testutils.inc" - startnostack - move.d 0xaa424243,$acr - lsrq 1,$acr - moveq 1,$acr - clear.d $acr - break 15 - nop diff --git a/sim/testsuite/sim/cris/asm/x8-v10.ms b/sim/testsuite/sim/cris/asm/x8-v10.ms deleted file mode 100644 index 672cc21..0000000 --- a/sim/testsuite/sim/cris/asm/x8-v10.ms +++ /dev/null @@ -1,20 +0,0 @@ -#mach: crisv10 -#ld: --section-start=.text=0 -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n -#output: 8 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: c 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 2\n -#output: e 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 1\n -#sim: --cris-trace=basic - -; Check that "jump [rN]" gets 2 cycles. - - .include "testutils.inc" - startnostack - move.d 0f,r5 - jump [r5] - break 15 -1: - nop - break 15 -0: - .dword 1b diff --git a/sim/testsuite/sim/cris/asm/x9-v10.ms b/sim/testsuite/sim/cris/asm/x9-v10.ms deleted file mode 100644 index 68472be..0000000 --- a/sim/testsuite/sim/cris/asm/x9-v10.ms +++ /dev/null @@ -1,23 +0,0 @@ -#mach: crisv10 -#ld: --section-start=.text=0 -#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n -#output: 4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 1\n -#output: 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 4\n -#output: 12 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 1\n -#sim: --cris-trace=basic - -; Check that "adds.w [$pc+$r9.w],$pc" gets 4 cycles. - - .include "testutils.inc" - startnostack - moveq 1,r9 - adds.w [$pc+$r9.w],$pc -0: - .word 1f-0b - .word 2f-0b - .word 1f-0b -1: - break 15 -2: - nop - break 15 diff --git a/sim/testsuite/sim/cris/asm/xor.ms b/sim/testsuite/sim/cris/asm/xor.ms deleted file mode 100644 index 2095dea..0000000 --- a/sim/testsuite/sim/cris/asm/xor.ms +++ /dev/null @@ -1,47 +0,0 @@ -# mach: crisv0 crisv3 crisv8 crisv10 crisv32 -# output: 3\n3\nff0\n0\n2c21b3db\n0\nffffffff\n - - .include "testutils.inc" - start - moveq 1,r3 - moveq 2,r4 - xor r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - moveq 2,r3 - moveq 1,r4 - xor r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 3 - - move.d 0xff0f,r4 - move.d 0xf0ff,r3 - xor r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; ff0 - - moveq -1,r4 - move.d r4,r3 - xor r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x5432f789,r4 - move.d 0x78134452,r3 - xor r4,r3 - test_move_cc 0 0 0 0 - dumpr3 ; 2c21b3db - - moveq 0,r4 - moveq 0,r3 - xor r4,r3 - test_move_cc 0 1 0 0 - dumpr3 ; 0 - - move.d 0x7fffffff,r3 - move.d 0x80000000,r4 - xor r4,r3 - test_move_cc 1 0 0 0 - dumpr3 ; ffffffff - quit diff --git a/sim/testsuite/sim/cris/c/access1.c b/sim/testsuite/sim/cris/c/access1.c deleted file mode 100644 index ba9be34..0000000 --- a/sim/testsuite/sim/cris/c/access1.c +++ /dev/null @@ -1,16 +0,0 @@ -/* Check access(2) trivially. Newlib doesn't have it. -#notarget: cris*-*-elf -*/ -#include -#include -#include -#include -int main (int argc, char **argv) -{ - if (access (argv[0], R_OK|W_OK|X_OK) == 0 - && access ("/dev/null", R_OK|W_OK) == 0 - && access ("/dev/null", X_OK) == -1 - && errno == EACCES) - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/append1.c b/sim/testsuite/sim/cris/c/append1.c deleted file mode 100644 index 0acd59d..0000000 --- a/sim/testsuite/sim/cris/c/append1.c +++ /dev/null @@ -1,51 +0,0 @@ -/* Check regression of a bug uncovered by the libio tFile test (old - libstdc++, pre-gcc-3.x era), where appending to a file doesn't work. - The default open-flags-mapping does not match Linux/CRIS, so a - specific mapping is necessary. */ - -#include -#include -#include - -int -main (void) -{ - FILE *f; - const char fname[] = "sk1test.dat"; - const char tsttxt1[] - = "This is the first and only line of this file.\n"; - const char tsttxt2[] = "Now there is a second line.\n"; - char buf[sizeof (tsttxt1) + sizeof (tsttxt2) - 1] = ""; - - f = fopen (fname, "w+"); - if (f == NULL - || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1) - || fclose (f) != 0) - { - printf ("fail\n"); - exit (1); - } - - f = fopen (fname, "a+"); - if (f == NULL - || fwrite (tsttxt2, 1, strlen (tsttxt2), f) != strlen (tsttxt2) - || fclose (f) != 0) - { - printf ("fail\n"); - exit (1); - } - - f = fopen (fname, "r"); - if (f == NULL - || fread (buf, 1, sizeof (buf), f) != sizeof (buf) - 1 - || strncmp (buf, tsttxt1, strlen (tsttxt1)) != 0 - || strncmp (buf + strlen (tsttxt1), tsttxt2, strlen (tsttxt2)) != 0 - || fclose (f) != 0) - { - printf ("fail\n"); - exit (1); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/badldso1.c b/sim/testsuite/sim/cris/c/badldso1.c deleted file mode 100644 index 58caa8d..0000000 --- a/sim/testsuite/sim/cris/c/badldso1.c +++ /dev/null @@ -1,7 +0,0 @@ -/* -#notarget: cris*-*-elf -#dynamic: -#xerror: -#output: *: could not load ELF interpreter `*' for program `*'\n - */ -#include "hello.c" diff --git a/sim/testsuite/sim/cris/c/badldso2.c b/sim/testsuite/sim/cris/c/badldso2.c deleted file mode 100644 index db28889..0000000 --- a/sim/testsuite/sim/cris/c/badldso2.c +++ /dev/null @@ -1,8 +0,0 @@ -/* -#notarget: cris*-*-elf -#dynamic: -#xerror: -#cc: additional_flags=-Wl,-dynamic-linker,/dev/null -#output: *: could not load ELF interpreter `*' for program `*'\n - */ -#include "hello.c" diff --git a/sim/testsuite/sim/cris/c/badldso3.c b/sim/testsuite/sim/cris/c/badldso3.c deleted file mode 100644 index 3f9509b..0000000 --- a/sim/testsuite/sim/cris/c/badldso3.c +++ /dev/null @@ -1,9 +0,0 @@ -/* -#notarget: cris*-*-elf -#dynamic: -#xerror: -#cc: additional_flags=-Wl,-dynamic-linker,/compilercheck.x -#sim: --sysroot=@exedir@ -#output: *: could not load ELF interpreter `*' for program `*'\n - */ -#include "hello.c" diff --git a/sim/testsuite/sim/cris/c/c.exp b/sim/testsuite/sim/cris/c/c.exp deleted file mode 100644 index 08ea188..0000000 --- a/sim/testsuite/sim/cris/c/c.exp +++ /dev/null @@ -1,253 +0,0 @@ -# Copyright (C) 2005-2021 Free Software Foundation, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -# Miscellaneous CRIS simulator testcases testing syscall sequences. - -if ![istarget cris*-*-*] { - return -} - -set CFLAGS_FOR_TARGET "-O2" -if [istarget cris-*-*] { - set mach "crisv10" -} { - set mach "crisv32" -} - -if [istarget cris*-*-elf] { - append CFLAGS_FOR_TARGET " -sim" -} - -# Using target_compile, since it is less noisy, -if { [target_compile $srcdir/$subdir/hello.c compilercheck.x \ - "executable" "" ] == "" } { - set has_cc 1 - - # Now check if we can link a program dynamically, and where - # libc.so is located. If it is, we provide a sym link to the - # directory (which must end in /lib) in [pwd], so /lib/ld.so.1 is - # found (which must reside along libc.so). We don't bother - # replacing the board ldflags like below as we don't care about - # detrimental effects on the executable from the specs and - # -static in the board ldflags, we just add -Bdynamic. - if [regexp "(.*/lib)/libc.so" \ - [target_compile $srcdir/$subdir/hello.c compilercheck.x \ - "executable" \ - "ldflags=-print-file-name=libc.so -Wl,-Bdynamic"] \ - xxx libcsodir] { - file delete lib - verbose -log "Creating link to $libcsodir in [pwd]" - file link lib $libcsodir - } -} { - verbose -log "Can't execute C compiler" - set has_cc 0 -} - -# Like istarget, except take a list of targets as a string. -proc anytarget { targets } { - set targetlist [split $targets] - set argc [llength $targetlist] - for { set i 0 } { $i < $argc } { incr i } { - if [istarget [lindex $targetlist $i]] { - return 1 - } - } - return 0 -} - -foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.c]] { - set orig_ldflags "" - - if ![runtest_file_p $runtests $src] { - continue - } - set testname "[file tail $src]" - - set opt_array [slurp_options $src] - if { $opt_array == -1 } { - unresolved $testname - return - } - - # And again, to simplify specifying tests. - if ![runtest_file_p $runtests $src] { - continue - } - - # Note absence of CC in results, but don't make a big fuss over it. - if { $has_cc == 0 } { - untested $testname - continue - } - - # Clear default options - set opts(cc) "" - set opts(sim) "" - set opts(output) "" - set opts(progoptions) "" - set opts(timeout) "" - set opts(mach) "" - set opts(xerror) "no" - set opts(dest) "$testname.x" - set opts(simenv) "" - set opts(kfail) "" - set opts(xfail) "" - set opts(target) "" - set opts(notarget) "" - set opts(dynamic) "" - - # Clear any machine specific options specified in a previous test case - if [info exists opts(sim,$mach)] { - unset opts(sim,$mach) - } - - foreach i $opt_array { - set opt_name [lindex $i 0] - set opt_machs [lindex $i 1] - set opt_val [lindex $i 2] - if ![info exists opts($opt_name)] { - perror "unknown option $opt_name in file $src" - unresolved $testname - return - } - - # Replace specific substitutions: - # @exedir@ is where the test-program is located. - regsub -all "@exedir@" $opt_val "[pwd]" opt_val - # @srcdir@ is where the source of the test-program is located. - regsub -all "@srcdir@" $opt_val "$srcdir/$subdir" opt_val - - # Multiple of these options concatenate, they don't override. - if { $opt_name == "output" || $opt_name == "progoptions" } { - set opt_val "$opts($opt_name)$opt_val" - } - - # Similar with "xfail", "kfail", "target" and "notarget", but - # arguments are space-separated. - if { $opt_name == "xfail" || $opt_name == "kfail" \ - || $opt_name == "target" || $opt_name == "notarget" } { - if { $opts($opt_name) != "" } { - set opt_val "$opts($opt_name) $opt_val" - } - } - - if { $opt_name == "dynamic" \ - && [info exists board_info([target_info name],ldflags)] } { - # Weed out -static from ldflags, but keep the original in - # $orig_ldflags. - set orig_ldflags $board_info([target_info name],ldflags) - set ldflags " $orig_ldflags " - regsub -all " -static " $ldflags " " ldflags - set board_info([target_info name],ldflags) $ldflags - } - - foreach m $opt_machs { - set opts($opt_name,$m) $opt_val - } - if { "$opt_machs" == "" } { - set opts($opt_name) $opt_val - } - } - - if { $opts(output) == "" } { - if { "$opts(xerror)" == "no" } { - set opts(output) "pass\n" - } else { - set opts(output) "fail\n" - } - } - - if { $opts(target) != "" && ![anytarget $opts(target)] } { - continue - } - - if { $opts(notarget) != "" && [anytarget $opts(notarget)] } { - continue - } - - # If no machine specific options, default to the general version. - if ![info exists opts(sim,$mach)] { - set opts(sim,$mach) $opts(sim) - } - - # Change \n sequences to newline chars. - regsub -all "\\\\n" $opts(output) "\n" opts(output) - - verbose -log "Compiling $src with $opts(cc)" - - set dest "$opts(dest)" - if { [sim_compile $src $dest "executable" "$opts(cc)" ] != "" } { - unresolved $testname - continue - } - - if { $orig_ldflags != "" } { - set board_info([target_info name],ldflags) $orig_ldflags - } - - verbose -log "Simulating $src with $opts(sim,$mach)" - - # Time to setup xfailures and kfailures. - if { "$opts(xfail)" != "" } { - verbose -log "xfail: $opts(xfail)" - # Using eval to make $opts(xfail) appear as individual - # arguments. - eval setup_xfail $opts(xfail) - } - if { "$opts(kfail)" != "" } { - verbose -log "kfail: $opts(kfail)" - eval setup_kfail $opts(kfail) - } - - set result [sim_run $dest "$opts(sim,$mach)" "$opts(progoptions)" \ - "" "$opts(simenv)"] - set return_code [lindex $result 0] - set output [lindex $result 1] - - set status fail - if { $return_code == 0 } { - set status pass - } - - if { "$status" == "pass" } { - if { "$opts(xerror)" == "no" } { - if [string match $opts(output) $output] { - pass "$mach $testname" - } else { - verbose -log "output: $output" 3 - verbose -log "pattern: $opts(output)" 3 - fail "$mach $testname (execution)" - } - } else { - verbose -log "`pass' return code when expecting failure" 3 - fail "$mach $testname (execution)" - } - } elseif { "$status" == "fail" } { - if { "$opts(xerror)" == "no" } { - fail "$mach $testname (execution)" - } else { - if [string match $opts(output) $output] { - pass "$mach $testname" - } else { - verbose -log "output: $output" 3 - verbose -log "pattern: $opts(output)" 3 - fail "$mach $testname (execution)" - } - } - } else { - $status "$mach $testname" - } -} diff --git a/sim/testsuite/sim/cris/c/clone1.c b/sim/testsuite/sim/cris/c/clone1.c deleted file mode 100644 index 163b186..0000000 --- a/sim/testsuite/sim/cris/c/clone1.c +++ /dev/null @@ -1,90 +0,0 @@ -/* -#notarget: cris*-*-elf -#output: got: a\nthen: bc\nexit: 0\n -*/ - -/* This is a very limited subset of what ex1.c does; we just check that - thread creation (clone syscall) and pipe writes and reads work. */ - -#include -#include -#include -#include -#include -#include -#include -#include - -int pip[2]; - -int -process (void *arg) -{ - char *s = arg; - if (write (pip[1], s+2, 1) != 1) abort (); - if (write (pip[1], s+1, 1) != 1) abort (); - if (write (pip[1], s, 1) != 1) abort (); - return 0; -} - -int -main (void) -{ - int retcode; - int pid; - int st; - long stack[16384]; - char buf[10] = {0}; - - retcode = pipe (pip); - - if (retcode != 0) - { - fprintf (stderr, "Bad pipe %d\n", retcode); - abort (); - } - - pid = clone (process, (char *) stack + sizeof (stack) - 64, - (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) - | SIGCHLD, "cba"); - if (pid <= 0) - { - fprintf (stderr, "Bad clone %d\n", pid); - abort (); - } - - if ((retcode = read (pip[0], buf, 1)) != 1) - { - fprintf (stderr, "Bad read 1: %d\n", retcode); - abort (); - } - printf ("got: %c\n", buf[0]); - retcode = read (pip[0], buf, 2); - if (retcode == 1) - { - retcode = read (pip[0], buf+1, 1); - if (retcode != 1) - { - fprintf (stderr, "Bad read 1.5: %d\n", retcode); - abort (); - } - retcode = 2; - } - if (retcode != 2) - { - fprintf (stderr, "Bad read 2: %d\n", retcode); - abort (); - } - - printf ("then: %s\n", buf); - retcode = wait4 (-1, &st, WNOHANG | __WCLONE, NULL); - - if (retcode != pid || !WIFEXITED (st)) - { - fprintf (stderr, "Bad wait %d %x\n", retcode, st); - abort (); - } - - printf ("exit: %d\n", WEXITSTATUS (st)); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/clone2.c b/sim/testsuite/sim/cris/c/clone2.c deleted file mode 100644 index e433a77..0000000 --- a/sim/testsuite/sim/cris/c/clone2.c +++ /dev/null @@ -1,6 +0,0 @@ -/* Make sure the thread system trivially works with trace output. -#notarget: cris*-*-elf -#sim: --cris-trace=basic --trace-file=@exedir@/clone2.tmp -#output: got: a\nthen: bc\nexit: 0\n -*/ -#include "clone1.c" diff --git a/sim/testsuite/sim/cris/c/clone3.c b/sim/testsuite/sim/cris/c/clone3.c deleted file mode 100644 index 0a97484..0000000 --- a/sim/testsuite/sim/cris/c/clone3.c +++ /dev/null @@ -1,45 +0,0 @@ -/* Check that exiting from a parent thread does not kill the child. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int -process (void *arg) -{ - int i; - - for (i = 0; i < 50; i++) - if (sched_yield ()) - abort (); - - printf ("pass\n"); - return 0; -} - -int -main (void) -{ - int pid; - long stack[16384]; - - pid = clone (process, (char *) stack + sizeof (stack) - 64, - (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) - | SIGCHLD, "ab"); - if (pid <= 0) - { - fprintf (stderr, "Bad clone %d\n", pid); - abort (); - } - - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/clone4.c b/sim/testsuite/sim/cris/c/clone4.c deleted file mode 100644 index 81489dd..0000000 --- a/sim/testsuite/sim/cris/c/clone4.c +++ /dev/null @@ -1,61 +0,0 @@ -/* Check that TRT happens when we reach the #threads implementation limit. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int -process (void *arg) -{ - int i; - - for (i = 0; i < 500; i++) - if (sched_yield ()) - abort (); - - return 0; -} - -int -main (void) -{ - int pid; - int i; - int stacksize = 16384; - - for (i = 0; i < 1000; i++) - { - char *stack = malloc (stacksize); - if (stack == NULL) - abort (); - - pid = clone (process, (char *) stack + stacksize - 64, - (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) - | SIGCHLD, "ab"); - if (pid <= 0) - { - /* FIXME: Read sysconf instead of magic number. */ - if (i < 60) - { - fprintf (stderr, "Bad clone %d\n", pid); - abort (); - } - - if (errno == EAGAIN) - { - printf ("pass\n"); - exit (0); - } - } - } - - abort (); -} diff --git a/sim/testsuite/sim/cris/c/clone5.c b/sim/testsuite/sim/cris/c/clone5.c deleted file mode 100644 index 9380a1e..0000000 --- a/sim/testsuite/sim/cris/c/clone5.c +++ /dev/null @@ -1,35 +0,0 @@ -/* Check that unimplemented clone syscalls get the right treatment. -#notarget: cris*-*-elf -#xerror: -#output: Unimplemented clone syscall * -#output: program stopped with signal 4 (*).\n -*/ - -#include -#include -#include -#include -#include -#include -#include - -int pip[2]; - -int -process (void *arg) -{ - return 0; -} - -int -main (void) -{ - int retcode; - long stack[16384]; - - retcode = clone (process, (char *) stack + sizeof (stack) - 64, 0, "cba"); - if (retcode == -1 && errno == ENOSYS) - printf ("ENOSYS\n"); - printf ("xyzzy\n"); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/clone6.c b/sim/testsuite/sim/cris/c/clone6.c deleted file mode 100644 index 586b5c6..0000000 --- a/sim/testsuite/sim/cris/c/clone6.c +++ /dev/null @@ -1,8 +0,0 @@ -/* As the included file, but specifying silent ENOSYS. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=enosys-quiet -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "clone5.c" diff --git a/sim/testsuite/sim/cris/c/ex1.c b/sim/testsuite/sim/cris/c/ex1.c deleted file mode 100644 index 2447319..0000000 --- a/sim/testsuite/sim/cris/c/ex1.c +++ /dev/null @@ -1,54 +0,0 @@ -/* Compiler options: -#notarget: cris*-*-elf -#cc: additional_flags=-pthread -#output: Starting process a\naaaaaaaaStarting process b\nababbbbbbbbb - - The output will change depending on the exact syscall sequence per - thread, so will change with glibc versions. Prepare to modify; use - the latest glibc. - - This file is from glibc/linuxthreads, with the difference that the - number is 10, not 10000. */ - -/* Creates two threads, one printing 10000 "a"s, the other printing - 10000 "b"s. - Illustrates: thread creation, thread joining. */ - -#include -#include -#include -#include "pthread.h" - -static void * -process (void *arg) -{ - int i; - fprintf (stderr, "Starting process %s\n", (char *) arg); - for (i = 0; i < 10; i++) - { - write (1, (char *) arg, 1); - } - return NULL; -} - -int -main (void) -{ - int retcode; - pthread_t th_a, th_b; - void *retval; - - retcode = pthread_create (&th_a, NULL, process, (void *) "a"); - if (retcode != 0) - fprintf (stderr, "create a failed %d\n", retcode); - retcode = pthread_create (&th_b, NULL, process, (void *) "b"); - if (retcode != 0) - fprintf (stderr, "create b failed %d\n", retcode); - retcode = pthread_join (th_a, &retval); - if (retcode != 0) - fprintf (stderr, "join a failed %d\n", retcode); - retcode = pthread_join (th_b, &retval); - if (retcode != 0) - fprintf (stderr, "join b failed %d\n", retcode); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/exitg1.c b/sim/testsuite/sim/cris/c/exitg1.c deleted file mode 100644 index 0b4c425..0000000 --- a/sim/testsuite/sim/cris/c/exitg1.c +++ /dev/null @@ -1,20 +0,0 @@ -/* Check exit_group(2) trivially. Newlib doesn't have it and the - pre-v32 glibc requires updated headers we'd have to check or adjust - for. -#notarget: cris-*-* *-*-elf -#output: exit_group\n -*/ -#include -#include -#include -#include -#ifndef EXITVAL -#define EXITVAL 0 -#endif -int main (int argc, char **argv) -{ - printf ("exit_group\n"); - syscall (SYS_exit_group, EXITVAL); - printf ("failed\n"); - abort (); -} diff --git a/sim/testsuite/sim/cris/c/exitg2.c b/sim/testsuite/sim/cris/c/exitg2.c deleted file mode 100644 index e222cc4..0000000 --- a/sim/testsuite/sim/cris/c/exitg2.c +++ /dev/null @@ -1,7 +0,0 @@ -/* Check exit_group(2) trivially with non-zero status. -#notarget: cris-*-* *-*-elf -#output: exit_group\n -#xerror: -*/ -#define EXITVAL 1 -#include "exitg1.c" diff --git a/sim/testsuite/sim/cris/c/fcntl1.c b/sim/testsuite/sim/cris/c/fcntl1.c deleted file mode 100644 index 032f6b5..0000000 --- a/sim/testsuite/sim/cris/c/fcntl1.c +++ /dev/null @@ -1,19 +0,0 @@ -/* Check that we get the expected message for unsupported fcntl calls. -#notarget: cris*-*-elf -#xerror: -#output: Unimplemented fcntl* -#output: program stopped with signal 4 (*).\n -*/ -#include -#include -#include -#include - -int main (void) -{ - int err = fcntl (1, 42); - if (err == -1 && errno == ENOSYS) - printf ("ENOSYS\n"); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/fcntl2.c b/sim/testsuite/sim/cris/c/fcntl2.c deleted file mode 100644 index fc9f95b..0000000 --- a/sim/testsuite/sim/cris/c/fcntl2.c +++ /dev/null @@ -1,8 +0,0 @@ -/* As the included file, but specifying silent ENOSYS. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=enosys-quiet -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "fcntl1.c" diff --git a/sim/testsuite/sim/cris/c/fdopen1.c b/sim/testsuite/sim/cris/c/fdopen1.c deleted file mode 100644 index cdfe19a..0000000 --- a/sim/testsuite/sim/cris/c/fdopen1.c +++ /dev/null @@ -1,54 +0,0 @@ -/* Check that the syscalls implementing fdopen work trivially. */ - -#include -#include -#include -#include -#include - -void -perr (const char *s) -{ - perror (s); - exit (1); -} - -int -main (void) -{ - FILE *f; - int fd; - const char fname[] = "sk1test.dat"; - const char tsttxt1[] - = "This is the first and only line of this file.\n"; - char buf[sizeof (tsttxt1)] = ""; - - fd = open (fname, O_WRONLY|O_TRUNC|O_CREAT, S_IRWXU); - if (fd <= 0) - perr ("open-w"); - - f = fdopen (fd, "w"); - if (f == NULL - || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1)) - perr ("fdopen or fwrite"); - - if (fclose (f) != 0) - perr ("fclose"); - - fd = open (fname, O_RDONLY); - if (fd <= 0) - perr ("open-r"); - - f = fdopen (fd, "r"); - if (f == NULL - || fread (buf, 1, sizeof (buf), f) != strlen (tsttxt1) - || strcmp (buf, tsttxt1) != 0 - || fclose (f) != 0) - { - printf ("fail\n"); - exit (1); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/fdopen2.c b/sim/testsuite/sim/cris/c/fdopen2.c deleted file mode 100644 index 6a59f36..0000000 --- a/sim/testsuite/sim/cris/c/fdopen2.c +++ /dev/null @@ -1,52 +0,0 @@ -/* Check that the syscalls implementing fdopen work trivially. -#output: This is the first line of this test.\npass\n -*/ - -#include -#include -#include -#include -#include - -void -perr (const char *s) -{ - perror (s); - exit (1); -} - -int -main (void) -{ - FILE *f; - int fd; - const char fname[] = "sk1test.dat"; - const char tsttxt1[] - = "This is the first line of this test.\n"; - char buf[sizeof (tsttxt1)] = ""; - - /* Write a line to stdout. */ - f = fdopen (1, "w"); - if (f == NULL - || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1)) - perr ("fdopen or fwrite"); - -#if 0 - /* Unfortunately we can't get < /dev/null to the simulator with - reasonable test-framework surgery. */ - - /* Try to read from stdin. Expect EOF. */ - f = fdopen (0, "r"); - if (f == NULL - || fread (buf, 1, sizeof (buf), f) != 0 - || feof (f) == 0 - || ferror (f) != 0) - { - printf ("fail\n"); - exit (1); - } -#endif - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/freopen1.c b/sim/testsuite/sim/cris/c/freopen1.c deleted file mode 100644 index 0e0f28d..0000000 --- a/sim/testsuite/sim/cris/c/freopen1.c +++ /dev/null @@ -1,49 +0,0 @@ -/* Check that basic freopen functionality works. */ - -#include -#include -#include - -int -main (void) -{ - FILE *old_stderr; - FILE *f; - const char fname[] = "sk1test.dat"; - const char tsttxt[] - = "A random line of text, used to test correct freopen etc.\n"; - char buf[sizeof tsttxt] = ""; - - /* Like the freopen call in flex. */ - old_stderr = freopen (fname, "w+", stderr); - if (old_stderr == NULL - || fwrite (tsttxt, 1, strlen (tsttxt), stderr) != strlen (tsttxt) - || fclose (stderr) != 0) - { - printf ("fail\n"); - exit (1); - } - - /* Using "rb" to make this test similar to the use in genconf.c in - GhostScript. */ - f = fopen (fname, "rb"); - if (f == NULL - || fseek (f, 0L, SEEK_END) != 0 - || ftell (f) != strlen (tsttxt)) - { - printf ("fail\n"); - exit (1); - } - - rewind (f); - if (fread (buf, 1, strlen (tsttxt), f) != strlen (tsttxt) - || strcmp (buf, tsttxt) != 0 - || fclose (f) != 0) - { - printf ("fail\n"); - exit (1); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/freopen2.c b/sim/testsuite/sim/cris/c/freopen2.c deleted file mode 100644 index 3959607..0000000 --- a/sim/testsuite/sim/cris/c/freopen2.c +++ /dev/null @@ -1,40 +0,0 @@ -/* Tests that stdin can be redirected from a normal file. */ -#include -#include -#include - -int -main (void) -{ - const char* fname = "freopen.dat"; - const char tsttxt[] - = "A random line of text, used to test correct freopen etc.\n"; - FILE* instream; - FILE *old_stderr; - char c1; - - /* Like the freopen call in flex. */ - old_stderr = freopen (fname, "w+", stderr); - if (old_stderr == NULL - || fwrite (tsttxt, 1, strlen (tsttxt), stderr) != strlen (tsttxt) - || fclose (stderr) != 0) - { - printf ("fail\n"); - exit (1); - } - - instream = freopen(fname, "r", stdin); - if (instream == NULL) { - printf("fail\n"); - exit(1); - } - - c1 = getc(instream); - if (c1 != 'A') { - printf("fail\n"); - exit(1); - } - - printf ("pass\n"); - exit(0); -} diff --git a/sim/testsuite/sim/cris/c/ftruncate1.c b/sim/testsuite/sim/cris/c/ftruncate1.c deleted file mode 100644 index 46b8756..0000000 --- a/sim/testsuite/sim/cris/c/ftruncate1.c +++ /dev/null @@ -1,52 +0,0 @@ -/* Check that the ftruncate syscall works trivially. -#notarget: cris*-*-elf -*/ - -#include -#include -#include - -void -perr (const char *s) -{ - perror (s); - exit (1); -} - -int -main (void) -{ - FILE *f; - const char fname[] = "sk1test.dat"; - const char tsttxt1[] - = "This is the first and only line of this file.\n"; - const char tsttxt2[] = "Now there is a second line.\n"; - char buf[sizeof (tsttxt1) + sizeof (tsttxt2) - 1] = ""; - - f = fopen (fname, "w+"); - if (f == NULL - || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1)) - perr ("open or fwrite"); - - if (fflush (f) != 0) - perr ("fflush"); - - if (ftruncate (fileno (f), strlen(tsttxt1) - 20) != 0) - perr ("ftruncate"); - - if (fclose (f) != 0) - perr ("fclose"); - - f = fopen (fname, "r"); - if (f == NULL - || fread (buf, 1, sizeof (buf), f) != strlen (tsttxt1) - 20 - || strncmp (buf, tsttxt1, strlen (tsttxt1) - 20) != 0 - || fclose (f) != 0) - { - printf ("fail\n"); - exit (1); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/ftruncate2.c b/sim/testsuite/sim/cris/c/ftruncate2.c deleted file mode 100644 index f1ef18c..0000000 --- a/sim/testsuite/sim/cris/c/ftruncate2.c +++ /dev/null @@ -1,39 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -/* Check that we get a proper error indication if trying ftruncate on a - fd that is a pipe descriptor. */ - -#include -#include -#include -#include -int main (void) -{ - int pip[2]; - - if (pipe (pip) != 0) - { - perror ("pipe"); - abort (); - } - - if (ftruncate (pip[0], 20) == 0 || errno != EINVAL) - { - perror ("ftruncate 1"); - abort (); - } - - errno = 0; - - if (ftruncate (pip[1], 20) == 0 || errno != EINVAL) - { - perror ("ftruncate 2"); - abort (); - } - - printf ("pass\n"); - - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/getcwd1.c b/sim/testsuite/sim/cris/c/getcwd1.c deleted file mode 100644 index 3838916..0000000 --- a/sim/testsuite/sim/cris/c/getcwd1.c +++ /dev/null @@ -1,18 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - if (getcwd ((void *) -1, 4096) != NULL - || errno != EFAULT) - abort (); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/gettod.c b/sim/testsuite/sim/cris/c/gettod.c deleted file mode 100644 index 18a000c..0000000 --- a/sim/testsuite/sim/cris/c/gettod.c +++ /dev/null @@ -1,27 +0,0 @@ -/* Basic time functionality test. */ -#include -#include -#include -#include -int -main (void) -{ - struct timeval t_m = {0, 0}; - time_t t; - - if ((t = time (NULL)) == (time_t) -1 - || gettimeofday (&t_m, NULL) != 0 - || t_m.tv_sec == 0 - - /* We assume there will be no delay between the time and - gettimeofday calls above, but allow a timer-tick to make the - seconds increase by one. */ - || (t != t_m.tv_sec && t+1 != t_m.tv_sec)) - { - printf ("fail\n"); - exit (1); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/hello.c b/sim/testsuite/sim/cris/c/hello.c deleted file mode 100644 index fb403ba..0000000 --- a/sim/testsuite/sim/cris/c/hello.c +++ /dev/null @@ -1,7 +0,0 @@ -#include -#include -int main () -{ - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/helloaout.c b/sim/testsuite/sim/cris/c/helloaout.c deleted file mode 100644 index c71a658..0000000 --- a/sim/testsuite/sim/cris/c/helloaout.c +++ /dev/null @@ -1,14 +0,0 @@ -/* Make sure we don't just assume ELF all over. (We have to jump - through hoops to get runnable a.out out of the ELF setup, and - having problems with a.out and discontinous section arrangements - doesn't help. Adjust as needed to get a.out which says "pass". If - necessary, move to the asm subdir. By design, it doesn't work with - CRIS v32.) - -NB: We'd rely on kfail, but that doesn't skip compilation, and that's where -the crash in ld happens to break the testcase. -#target: disabled-cris-*-elf -#kfail: ld/13900 cris-*-elf -#cc: ldflags=-Wl,-mcrisaout\ -sim\ -Ttext=0 -*/ -#include "hello.c" diff --git a/sim/testsuite/sim/cris/c/hellodyn.c b/sim/testsuite/sim/cris/c/hellodyn.c deleted file mode 100644 index dc8042f..0000000 --- a/sim/testsuite/sim/cris/c/hellodyn.c +++ /dev/null @@ -1,5 +0,0 @@ -/* -#dynamic: -#sim: --sysroot=@exedir@ - */ -#include "hello.c" diff --git a/sim/testsuite/sim/cris/c/hellodyn2.c b/sim/testsuite/sim/cris/c/hellodyn2.c deleted file mode 100644 index 00f5369..0000000 --- a/sim/testsuite/sim/cris/c/hellodyn2.c +++ /dev/null @@ -1,5 +0,0 @@ -/* -#dynamic: -#sim: --sysroot=@exedir@ --load-vma - */ -#include "hello.c" diff --git a/sim/testsuite/sim/cris/c/hellodyn3.c b/sim/testsuite/sim/cris/c/hellodyn3.c deleted file mode 100644 index 8ae3a4f..0000000 --- a/sim/testsuite/sim/cris/c/hellodyn3.c +++ /dev/null @@ -1,9 +0,0 @@ -/* Check that invoking ld.so as a program, invoking the main program, - works. Jump through a few hoops to avoid reading the host - ld.so.cache (having no absolute path specified for the executable - falls back on loading through the same mechanisms as a DSO). -#notarget: *-*-elf -#dynamic: -#sim: --sysroot=@exedir@ @exedir@/lib/ld.so.1 --library-path / - */ -#include "hello.c" diff --git a/sim/testsuite/sim/cris/c/kill1.c b/sim/testsuite/sim/cris/c/kill1.c deleted file mode 100644 index e5c53a0..0000000 --- a/sim/testsuite/sim/cris/c/kill1.c +++ /dev/null @@ -1,30 +0,0 @@ -/* Basic kill functionality test; fail killing init. Don't run as root. */ -#include -#include -#include -#include -#include -int -main (void) -{ - if (kill (1, SIGTERM) != -1 - || errno != EPERM) - { - printf ("fail\n"); - exit (1); - } - - errno = 0; - - if (kill (1, SIGABRT) != -1 - || errno != EPERM) - { - printf ("fail\n"); - exit (1); - } - - errno = 0; - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/kill2.c b/sim/testsuite/sim/cris/c/kill2.c deleted file mode 100644 index 0a79db0..0000000 --- a/sim/testsuite/sim/cris/c/kill2.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Basic kill functionality test; suicide. -#xerror: -#output: program stopped with signal 6 (*).\n -*/ - -#include -#include -#include -#include -#include - -int -main (void) -{ - kill (getpid (), SIGABRT); - printf ("undead\n"); - exit (1); -} diff --git a/sim/testsuite/sim/cris/c/kill3.c b/sim/testsuite/sim/cris/c/kill3.c deleted file mode 100644 index c0e2179..0000000 --- a/sim/testsuite/sim/cris/c/kill3.c +++ /dev/null @@ -1,16 +0,0 @@ -/* Basic kill functionality test; suicide. -#xerror: -#output: program stopped with signal 6 (*).\n -*/ - -#include -#include -#include -#include -int -main (void) -{ - abort (); - printf ("undead\n"); - exit (1); -} diff --git a/sim/testsuite/sim/cris/c/mapbrk.c b/sim/testsuite/sim/cris/c/mapbrk.c deleted file mode 100644 index 1aff762..0000000 --- a/sim/testsuite/sim/cris/c/mapbrk.c +++ /dev/null @@ -1,39 +0,0 @@ -#include -#include - -/* Basic sanity check that syscalls to implement malloc (brk, mmap2, - munmap) are trivially functional. */ - -int main () -{ - void *p1, *p2, *p3, *p4, *p5, *p6; - - if ((p1 = malloc (8100)) == NULL - || (p2 = malloc (16300)) == NULL - || (p3 = malloc (4000)) == NULL - || (p4 = malloc (500)) == NULL - || (p5 = malloc (1023*1024)) == NULL - || (p6 = malloc (8191*1024)) == NULL) - { - printf ("fail\n"); - exit (1); - } - - free (p1); - free (p2); - free (p3); - free (p4); - free (p5); - free (p6); - - p1 = malloc (64000); - if (p1 == NULL) - { - printf ("fail\n"); - exit (1); - } - free (p1); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/mmap1.c b/sim/testsuite/sim/cris/c/mmap1.c deleted file mode 100644 index 9db94c1..0000000 --- a/sim/testsuite/sim/cris/c/mmap1.c +++ /dev/null @@ -1,52 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#define _GNU_SOURCE -#include -#include -#include -#include -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - int fd = open (argv[0], O_RDONLY); - struct stat sb; - int size; - void *a; - const char *str = "a string you'll only find in the program"; - - if (fd == -1) - { - perror ("open"); - abort (); - } - - if (fstat (fd, &sb) < 0) - { - perror ("fstat"); - abort (); - } - - size = sb.st_size; - - /* We want to test mmapping a size that isn't exactly a page. */ - if ((size & 8191) == 0) - size--; - -#ifndef MMAP_FLAGS -#define MMAP_FLAGS MAP_PRIVATE -#endif - - a = mmap (NULL, size, PROT_READ, MMAP_FLAGS, fd, 0); - - if (memmem (a, size, str, strlen (str) + 1) == NULL) - abort (); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/mmap2.c b/sim/testsuite/sim/cris/c/mmap2.c deleted file mode 100644 index 35139a0..0000000 --- a/sim/testsuite/sim/cris/c/mmap2.c +++ /dev/null @@ -1,48 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#define _GNU_SOURCE -#include -#include -#include -#include -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - int fd = open (argv[0], O_RDONLY); - struct stat sb; - int size; - void *a; - const char *str = "a string you'll only find in the program"; - - if (fd == -1) - { - perror ("open"); - abort (); - } - - if (fstat (fd, &sb) < 0) - { - perror ("fstat"); - abort (); - } - - size = sb.st_size; - - /* We want to test mmapping a size that isn't exactly a page. */ - if ((size & 8191) == 0) - size--; - - a = mmap (NULL, size, PROT_READ, MAP_SHARED, fd, 0); - - if (memmem (a, size, str, strlen (str) + 1) == NULL) - abort (); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/mmap3.c b/sim/testsuite/sim/cris/c/mmap3.c deleted file mode 100644 index 34401fa..0000000 --- a/sim/testsuite/sim/cris/c/mmap3.c +++ /dev/null @@ -1,33 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#define _GNU_SOURCE -#include -#include -#include -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - volatile unsigned char *a; - - /* Check that we can map a non-multiple of a page and still get a full page. */ - a = mmap (NULL, 0x4c, PROT_READ | PROT_WRITE | PROT_EXEC, - MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); - if (a == NULL || a == (unsigned char *) -1) - abort (); - - a[0] = 0xbe; - a[8191] = 0xef; - memset ((char *) a + 1, 0, 8190); - - if (a[0] != 0xbe || a[8191] != 0xef) - abort (); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/mmap4.c b/sim/testsuite/sim/cris/c/mmap4.c deleted file mode 100644 index b3a66e4..0000000 --- a/sim/testsuite/sim/cris/c/mmap4.c +++ /dev/null @@ -1,5 +0,0 @@ -/* Just check that MAP_DENYWRITE is "honored" (ignored). -#notarget: cris*-*-elf -*/ -#define MMAP_FLAGS (MAP_PRIVATE|MAP_DENYWRITE) -#include "mmap1.c" diff --git a/sim/testsuite/sim/cris/c/mmap5.c b/sim/testsuite/sim/cris/c/mmap5.c deleted file mode 100644 index 95f00c3..0000000 --- a/sim/testsuite/sim/cris/c/mmap5.c +++ /dev/null @@ -1,91 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#define _GNU_SOURCE -#include -#include -#include -#include -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - int fd = open (argv[0], O_RDONLY); - struct stat sb; - int size; - void *a; - void *b; - const char *str = "a string you'll only find in the program"; - - if (fd == -1) - { - perror ("open"); - abort (); - } - - if (fstat (fd, &sb) < 0) - { - perror ("fstat"); - abort (); - } - - size = 8192; -#ifdef MMAP_SIZE1 - size = MMAP_SIZE1; -#endif - -#ifndef MMAP_PROT1 -#define MMAP_PROT1 PROT_READ | PROT_WRITE | PROT_EXEC -#endif - -#ifndef MMAP_FLAGS1 -#define MMAP_FLAGS1 MAP_PRIVATE | MAP_ANONYMOUS -#endif - - /* Get a page, any page. */ - b = mmap (NULL, size, MMAP_PROT1, MMAP_FLAGS1, -1, 0); - if (b == MAP_FAILED) - abort (); - - /* Remember it, unmap it. */ -#ifndef NO_MUNMAP - if (munmap (b, size) != 0) - abort (); -#endif - -#ifdef MMAP_ADDR2 - b = MMAP_ADDR2; -#endif - -#ifndef MMAP_PROT2 -#define MMAP_PROT2 PROT_READ | PROT_EXEC -#endif - -#ifndef MMAP_FLAGS2 -#define MMAP_FLAGS2 MAP_DENYWRITE | MAP_FIXED | MAP_PRIVATE -#endif - - size = sb.st_size; -#ifdef MMAP_SIZE2 - size = MMAP_SIZE2; -#endif - -#define MMAP_TEST_BAD_ORIG \ - (a == MAP_FAILED || memmem (a, size, str, strlen (str) + 1) == NULL) -#ifndef MMAP_TEST_BAD -#define MMAP_TEST_BAD MMAP_TEST_BAD_ORIG -#endif - - /* Try mapping the now non-mapped page fixed. */ - a = mmap (b, size, MMAP_PROT2, MMAP_FLAGS2, fd, 0); - - if (MMAP_TEST_BAD) - abort (); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/mmap6.c b/sim/testsuite/sim/cris/c/mmap6.c deleted file mode 100644 index 929d9cc..0000000 --- a/sim/testsuite/sim/cris/c/mmap6.c +++ /dev/null @@ -1,8 +0,0 @@ -/* Check that mmapping specifying a previously mmapped address without - MAP_FIXED works; that we just don't get the same address. -#notarget: cris*-*-elf -*/ -#define NO_MUNMAP -#define MMAP_FLAGS2 MAP_PRIVATE -#define MMAP_TEST_BAD (a == b || MMAP_TEST_BAD_ORIG) -#include "mmap5.c" diff --git a/sim/testsuite/sim/cris/c/mmap7.c b/sim/testsuite/sim/cris/c/mmap7.c deleted file mode 100644 index c4b14b0..0000000 --- a/sim/testsuite/sim/cris/c/mmap7.c +++ /dev/null @@ -1,14 +0,0 @@ -/* Check that mmapping a page-aligned size, larger than the file, - works. - -#notarget: cris*-*-elf -*/ - -/* Make sure we get an address where the size fits. */ -#define MMAP_SIZE1 ((sb.st_size + 8192) & ~8191) - -/* If this ever fails because the file is a page-multiple, we'll deal - with that then. We want it larger than the file-size anyway. */ -#define MMAP_SIZE2 ((size + 8192) & ~8191) -#define MMAP_FLAGS2 MAP_DENYWRITE | MAP_PRIVATE | MAP_FIXED -#include "mmap5.c" diff --git a/sim/testsuite/sim/cris/c/mmap8.c b/sim/testsuite/sim/cris/c/mmap8.c deleted file mode 100644 index 0564c79..0000000 --- a/sim/testsuite/sim/cris/c/mmap8.c +++ /dev/null @@ -1,9 +0,0 @@ -/* Check that mmapping 0 using MAP_FIXED works, both with/without - there being previously mmapped contents. -#notarget: cris*-*-elf -*/ -#define MMAP_FLAGS1 MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED -#define NO_MUNMAP -#define MMAP_SIZE2 8192 -#define MMAP_TEST_BAD (a != b || a != 0) -#include "mmap5.c" diff --git a/sim/testsuite/sim/cris/c/mprotect1.c b/sim/testsuite/sim/cris/c/mprotect1.c deleted file mode 100644 index 8dae50b..0000000 --- a/sim/testsuite/sim/cris/c/mprotect1.c +++ /dev/null @@ -1,19 +0,0 @@ -/* Check unimplemented-output for mprotect call. -#notarget: cris*-*-elf -#xerror: -#output: Unimplemented mprotect call (0x0, 0x2001, 0x4)\n -#output: program stopped with signal 4 (*).\n - */ -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - int err = mprotect (0, 8193, PROT_EXEC); - if (err == -1 && errno == ENOSYS) - printf ("ENOSYS\n"); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/mprotect2.c b/sim/testsuite/sim/cris/c/mprotect2.c deleted file mode 100644 index 4d83945..0000000 --- a/sim/testsuite/sim/cris/c/mprotect2.c +++ /dev/null @@ -1,8 +0,0 @@ -/* As the included file, but specifying silent ENOSYS. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=enosys-quiet -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "mprotect1.c" diff --git a/sim/testsuite/sim/cris/c/mremap.c b/sim/testsuite/sim/cris/c/mremap.c deleted file mode 100644 index e78a8a4..0000000 --- a/sim/testsuite/sim/cris/c/mremap.c +++ /dev/null @@ -1,31 +0,0 @@ -#include -#include - -/* Sanity check that system calls for realloc works. Also tests a few - more cases for mmap2 and munmap. */ - -int main () -{ - void *p1, *p2; - - if ((p1 = malloc (8100)) == NULL - || (p1 = realloc (p1, 16300)) == NULL - || (p1 = realloc (p1, 4000)) == NULL - || (p1 = realloc (p1, 500)) == NULL - || (p1 = realloc (p1, 1023*1024)) == NULL - || (p1 = realloc (p1, 8191*1024)) == NULL - || (p1 = realloc (p1, 512*1024)) == NULL - || (p2 = malloc (1023*1024)) == NULL - || (p1 = realloc (p1, 1023*1024)) == NULL - || (p1 = realloc (p1, 8191*1024)) == NULL - || (p1 = realloc (p1, 512*1024)) == NULL) - { - printf ("fail\n"); - exit (1); - } - - free (p1); - free (p2); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/openpf1.c b/sim/testsuite/sim/cris/c/openpf1.c deleted file mode 100644 index e0d8e5c..0000000 --- a/sim/testsuite/sim/cris/c/openpf1.c +++ /dev/null @@ -1,38 +0,0 @@ -/* Check that --sysroot is applied to open(2). -#sim: --sysroot=@exedir@ - - We assume, with EXE being the name of the executable: - - The simulator executes with cwd the same directory where the executable - is located (so argv[0] contains a plain filename without directory - components). - - There's no /EXE on the host file system. */ - -#include -#include -#include -#include -int main (int argc, char *argv[]) -{ - char *fnam = argv[0]; - FILE *f; - if (argv[0][0] != '/') - { - fnam = malloc (strlen (argv[0]) + 2); - if (fnam == NULL) - abort (); - strcpy (fnam, "/"); - strcat (fnam, argv[0]); - } - - f = fopen (fnam, "rb"); - if (f == NULL) - abort (); - fclose (f); - - /* Cover another execution path. */ - if (fopen ("/nonexistent", "rb") != NULL - || errno != ENOENT) - abort (); - printf ("pass\n"); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/openpf2.c b/sim/testsuite/sim/cris/c/openpf2.c deleted file mode 100644 index 50337b1..0000000 --- a/sim/testsuite/sim/cris/c/openpf2.c +++ /dev/null @@ -1,16 +0,0 @@ -/* Check that the simulator has chdir:ed to the --sysroot argument -#sim: --sysroot=@srcdir@ - (or that --sysroot is applied to relative file paths). */ - -#include -#include -#include -int main (int argc, char *argv[]) -{ - FILE *f = fopen ("openpf2.c", "rb"); - if (f == NULL) - abort (); - fclose (f); - printf ("pass\n"); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/openpf3.c b/sim/testsuite/sim/cris/c/openpf3.c deleted file mode 100644 index 557adee..0000000 --- a/sim/testsuite/sim/cris/c/openpf3.c +++ /dev/null @@ -1,49 +0,0 @@ -/* Basic file operations (rename, unlink); once without sysroot. We - also test that the simulator has chdir:ed to PREFIX, when defined. */ - -#include -#include -#include -#include -#include -#include - -#ifndef PREFIX -#define PREFIX -#endif - -void err (const char *s) -{ - perror (s); - abort (); -} - -int main (int argc, char *argv[]) -{ - FILE *f; - struct stat buf; - - unlink (PREFIX "testfoo2.tmp"); - - f = fopen ("testfoo1.tmp", "w"); - if (f == NULL) - err ("open"); - fclose (f); - - if (rename (PREFIX "testfoo1.tmp", PREFIX "testfoo2.tmp") != 0) - err ("rename"); - - if (stat (PREFIX "testfoo2.tmp", &buf) != 0 - || !S_ISREG (buf.st_mode)) - err ("stat 1"); - - if (stat ("testfoo2.tmp", &buf) != 0 - || !S_ISREG (buf.st_mode)) - err ("stat 2"); - - if (unlink (PREFIX "testfoo2.tmp") != 0) - err ("unlink"); - - printf ("pass\n"); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/openpf4.c b/sim/testsuite/sim/cris/c/openpf4.c deleted file mode 100644 index d3fdcfe..0000000 --- a/sim/testsuite/sim/cris/c/openpf4.c +++ /dev/null @@ -1,5 +0,0 @@ -/* Basic file operations, now *with* sysroot. -#sim: --sysroot=@exedir@ -*/ -#define PREFIX "/" -#include "openpf3.c" diff --git a/sim/testsuite/sim/cris/c/openpf5.c b/sim/testsuite/sim/cris/c/openpf5.c deleted file mode 100644 index 1f86ea2..0000000 --- a/sim/testsuite/sim/cris/c/openpf5.c +++ /dev/null @@ -1,56 +0,0 @@ -/* Check that TRT happens when error on too many opened files. -#notarget: cris*-*-elf -#sim: --sysroot=@exedir@ -*/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - int i; - int filemax; - -#ifdef OPEN_MAX - filemax = OPEN_MAX; -#else - filemax = sysconf (_SC_OPEN_MAX); -#endif - - char *fn = malloc (strlen (argv[0]) + 2); - if (fn == NULL) - abort (); - strcpy (fn, "/"); - strcat (fn, argv[0]); - - for (i = 0; i < filemax + 1; i++) - { - if (open (fn, O_RDONLY) < 0) - { - /* Shouldn't happen too early. */ - if (i < filemax - 3 - 1) - { - fprintf (stderr, "i: %d\n", i); - abort (); - } - if (errno != EMFILE) - { - perror ("open"); - abort (); - } - goto ok; - } - } - abort (); - -ok: - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/pipe1.c b/sim/testsuite/sim/cris/c/pipe1.c deleted file mode 100644 index 735974b..0000000 --- a/sim/testsuite/sim/cris/c/pipe1.c +++ /dev/null @@ -1,48 +0,0 @@ -/* Check for proper pipe semantics at corner cases. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int main (void) -{ - int i; - int filemax; - -#ifdef OPEN_MAX - filemax = OPEN_MAX; -#else - filemax = sysconf (_SC_OPEN_MAX); -#endif - - if (filemax < 10) - abort (); - - /* Check that pipes don't leak file descriptors. */ - for (i = 0; i < filemax * 10; i++) - { - int pip[2]; - if (pipe (pip) != 0) - { - perror ("pipe"); - abort (); - } - - if (close (pip[0]) != 0 || close (pip[1]) != 0) - { - perror ("close"); - abort (); - } - } - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/pipe2.c b/sim/testsuite/sim/cris/c/pipe2.c deleted file mode 100644 index 18ccf38..0000000 --- a/sim/testsuite/sim/cris/c/pipe2.c +++ /dev/null @@ -1,143 +0,0 @@ -/* Check that closing a pipe with a nonempty buffer works. -#notarget: cris*-*-elf -#output: got: a\ngot: b\nexit: 0\n -*/ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -int pip[2]; - -int pipemax; - -int -process (void *arg) -{ - char *s = arg; - int lots = pipemax + 256; - char *buf = malloc (lots); - int ret; - - if (buf == NULL) - abort (); - - *buf = *s; - - /* The first write should go straight through. */ - if (write (pip[1], buf, 1) != 1) - abort (); - - *buf = s[1]; - - /* The second write may or may not be successful for the whole - write, but should be successful for at least the pipemax part. - As linux/limits.h clamps PIPE_BUF to 4096, but the page size is - actually 8k, we can get away with that much. There should be no - error, though. Doing this on host shows that for - x86_64-unknown-linux-gnu (2.6.14-1.1656_FC4) pipemax * 10 can be - successfully written, perhaps for similar reasons. */ - ret = write (pip[1], buf, lots); - if (ret < pipemax) - { - fprintf (stderr, "ret: %d, %s, %d\n", ret, strerror (errno), pipemax); - fflush (0); - abort (); - } - - return 0; -} - -int -main (void) -{ - int retcode; - int pid; - int st = 0; - long stack[16384]; - char buf[1]; - - /* We need to turn this off because we don't want (to have to model) a - SIGPIPE resulting from the close. */ - if (signal (SIGPIPE, SIG_IGN) != SIG_DFL) - abort (); - - retcode = pipe (pip); - - if (retcode != 0) - { - fprintf (stderr, "Bad pipe %d\n", retcode); - abort (); - } - -#ifdef PIPE_MAX - pipemax = PIPE_MAX; -#else - pipemax = fpathconf (pip[1], _PC_PIPE_BUF); -#endif - - if (pipemax <= 0) - { - fprintf (stderr, "Bad pipemax %d\n", pipemax); - abort (); - } - - pid = clone (process, (char *) stack + sizeof (stack) - 64, - (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) - | SIGCHLD, "ab"); - if (pid <= 0) - { - fprintf (stderr, "Bad clone %d\n", pid); - abort (); - } - - while ((retcode = read (pip[0], buf, 1)) == 0) - ; - - if (retcode != 1) - { - fprintf (stderr, "Bad read 1: %d\n", retcode); - abort (); - } - - printf ("got: %c\n", buf[0]); - - /* Need to read out something from the second write too before - closing, or the writer can get EPIPE. */ - while ((retcode = read (pip[0], buf, 1)) == 0) - ; - - if (retcode != 1) - { - fprintf (stderr, "Bad read 2: %d\n", retcode); - abort (); - } - - printf ("got: %c\n", buf[0]); - - if (close (pip[0]) != 0) - { - perror ("pip close"); - abort (); - } - - retcode = waitpid (pid, &st, __WALL); - - if (retcode != pid || !WIFEXITED (st)) - { - fprintf (stderr, "Bad wait %d:%d %x\n", pid, retcode, st); - perror ("errno"); - abort (); - } - - printf ("exit: %d\n", WEXITSTATUS (st)); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/pipe3.c b/sim/testsuite/sim/cris/c/pipe3.c deleted file mode 100644 index bf08a38..0000000 --- a/sim/testsuite/sim/cris/c/pipe3.c +++ /dev/null @@ -1,48 +0,0 @@ -/* Check that TRT happens when error on pipe call. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include -#include - -int main (void) -{ - int i; - int filemax; - -#ifdef OPEN_MAX - filemax = OPEN_MAX; -#else - filemax = sysconf (_SC_OPEN_MAX); -#endif - - /* Check that TRT happens when error on pipe call. */ - for (i = 0; i < filemax + 1; i++) - { - int pip[2]; - if (pipe (pip) != 0) - { - /* Shouldn't happen too early. */ - if (i < filemax / 2 - 3 - 1) - { - fprintf (stderr, "i: %d\n", i); - abort (); - } - if (errno != EMFILE) - { - perror ("pipe"); - abort (); - } - goto ok; - } - } - abort (); - -ok: - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/pipe4.c b/sim/testsuite/sim/cris/c/pipe4.c deleted file mode 100644 index 1cb309f..0000000 --- a/sim/testsuite/sim/cris/c/pipe4.c +++ /dev/null @@ -1,66 +0,0 @@ -/* Check that TRT happens for pipe corner cases. -#notarget: cris*-*-elf -*/ -#include -#include -#include -#include -#include -#include -#include - -void err (const char *s) -{ - perror (s); - abort (); -} - -int main (void) -{ - int pip[2]; - char c; - int pipemax; - - if (pipe (pip) != 0) - err ("pipe"); - -#ifdef PIPE_MAX - pipemax = PIPE_MAX; -#else - pipemax = fpathconf (pip[1], _PC_PIPE_BUF); -#endif - - if (pipemax <= 0) - { - fprintf (stderr, "Bad pipemax %d\n", pipemax); - abort (); - } - - /* Writing to wrong end of pipe. */ - if (write (pip[0], "argh", 1) != -1 - || errno != EBADF) - err ("write pipe"); - - errno = 0; - - /* Reading from wrong end of pipe. */ - if (read (pip[1], &c, 1) != -1 - || errno != EBADF) - err ("write pipe"); - - errno = 0; - - if (close (pip[0]) != 0) - err ("close"); - - if (signal (SIGPIPE, SIG_IGN) != SIG_DFL) - err ("signal"); - - /* Writing to pipe with closed read end. */ - if (write (pip[1], "argh", 1) != -1 - || errno != EPIPE) - err ("write closed"); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/pipe5.c b/sim/testsuite/sim/cris/c/pipe5.c deleted file mode 100644 index 2b4d763..0000000 --- a/sim/testsuite/sim/cris/c/pipe5.c +++ /dev/null @@ -1,59 +0,0 @@ -/* Check that TRT happens for pipe corner cases (for our definition of TRT). -#notarget: cris*-*-elf -#xerror: -#output: Terminating simulation due to writing pipe * from one single thread\n -#output: program stopped with signal 4 (*).\n -*/ -#include -#include -#include -#include -#include -#include -#include - -void err (const char *s) -{ - perror (s); - abort (); -} - -int main (void) -{ - int pip[2]; - int pipemax; - char *buf; - - if (pipe (pip) != 0) - err ("pipe"); - -#ifdef PIPE_MAX - pipemax = PIPE_MAX; -#else - pipemax = fpathconf (pip[1], _PC_PIPE_BUF); -#endif - - if (pipemax <= 0) - { - fprintf (stderr, "Bad pipemax %d\n", pipemax); - abort (); - } - - /* Writing an inordinate amount to the pipe. */ - buf = calloc (100 * pipemax, 1); - if (buf == NULL) - err ("calloc"); - - /* The following doesn't trig on host; writing more than PIPE_MAX to a - pipe with no reader makes the program hang. Neither does it trig - on target: we don't want to emulate the "hanging" (which would - happen with *any* amount written to a pipe with no reader if we'd - support it - but we don't). Better to abort the simulation with a - suitable message. */ - if (write (pip[1], buf, 100 * pipemax) != -1 - || errno != EFBIG) - err ("write mucho"); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/pipe6.c b/sim/testsuite/sim/cris/c/pipe6.c deleted file mode 100644 index a8830cc..0000000 --- a/sim/testsuite/sim/cris/c/pipe6.c +++ /dev/null @@ -1,111 +0,0 @@ -/* Check that writing an inordinate amount of data works (somewhat). -#notarget: cris*-*-elf -#output: got: a\nexit: 0\n - This test-case will *not* work on host (or for real): the first - pipemax+1 bytes will be successfully written. It's just for - exercising a rare execution path. */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int pip[2]; - -int pipemax; - -int -process (void *arg) -{ - char *s = arg; - char *buf = calloc (pipemax * 100, 1); - int ret; - - if (buf == NULL) - abort (); - - *buf = *s; - - ret = write (pip[1], buf, pipemax * 100); - if (ret != -1 || errno != EFBIG) - { - perror ("write"); - abort (); - } - - return 0; -} - -int -main (void) -{ - int retcode; - int pid; - int st = 0; - long stack[16384]; - char buf[1]; - - retcode = pipe (pip); - - if (retcode != 0) - { - fprintf (stderr, "Bad pipe %d\n", retcode); - abort (); - } - -#ifdef PIPE_MAX - pipemax = PIPE_MAX; -#else - pipemax = fpathconf (pip[1], _PC_PIPE_BUF); -#endif - - if (pipemax <= 0) - { - fprintf (stderr, "Bad pipemax %d\n", pipemax); - abort (); - } - - pid = clone (process, (char *) stack + sizeof (stack) - 64, - (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) - | SIGCHLD, "ab"); - if (pid <= 0) - { - fprintf (stderr, "Bad clone %d\n", pid); - abort (); - } - - while ((retcode = read (pip[0], buf, 1)) == 0) - ; - - if (retcode != 1) - { - fprintf (stderr, "Bad read 1: %d\n", retcode); - abort (); - } - - printf ("got: %c\n", buf[0]); - - if (close (pip[0]) != 0) - { - perror ("pip close"); - abort (); - } - - retcode = waitpid (pid, &st, __WALL); - - if (retcode != pid || !WIFEXITED (st)) - { - fprintf (stderr, "Bad wait %d:%d %x\n", pid, retcode, st); - perror ("errno"); - abort (); - } - - printf ("exit: %d\n", WEXITSTATUS (st)); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/pipe7.c b/sim/testsuite/sim/cris/c/pipe7.c deleted file mode 100644 index 552ddb8..0000000 --- a/sim/testsuite/sim/cris/c/pipe7.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Check for proper pipe semantics at corner cases. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include - -int main (void) -{ - if (pipe (NULL) != -1 - || errno != EFAULT) - { - perror ("pipe"); - abort (); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/readlink1.c b/sim/testsuite/sim/cris/c/readlink1.c deleted file mode 100644 index 1898e8e..0000000 --- a/sim/testsuite/sim/cris/c/readlink1.c +++ /dev/null @@ -1,20 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - char buf[1024]; - /* This depends on the test-setup, but it's unlikely that the program - is passed as a symlink, so supposedly safe. */ - if (readlink(argv[0], buf, sizeof (buf)) != -1 || errno != EINVAL) - abort (); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/readlink10.c b/sim/testsuite/sim/cris/c/readlink10.c deleted file mode 100644 index 2174408..0000000 --- a/sim/testsuite/sim/cris/c/readlink10.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Check that odd cases of readlink work. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - if (readlink("/proc/42/exe", NULL, 4096) != -1 - || errno != EFAULT) - abort (); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/readlink11.c b/sim/testsuite/sim/cris/c/readlink11.c deleted file mode 100644 index 05a332f..0000000 --- a/sim/testsuite/sim/cris/c/readlink11.c +++ /dev/null @@ -1,9 +0,0 @@ -/* As readlink5.c (sic), but specifying silent ENOSYS. -#notarget: cris*-*-elf -#dest: ./readlink11.c.x -#sim: --cris-unknown-syscall=enosys-quiet -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "readlink2.c" diff --git a/sim/testsuite/sim/cris/c/readlink2.c b/sim/testsuite/sim/cris/c/readlink2.c deleted file mode 100644 index e5e9d94..0000000 --- a/sim/testsuite/sim/cris/c/readlink2.c +++ /dev/null @@ -1,80 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - char buf[1024]; - char buf2[1024]; - int err; - - /* This is a special feature handled in the simulator. The "42" - should be formed from getpid () if this was a real program. */ - err = readlink ("/proc/42/exe", buf, sizeof (buf)); - if (err < 0) - { - if (err == -1 && errno == ENOSYS) - printf ("ENOSYS\n"); - printf ("xyzzy\n"); - exit (0); - } - - /* Don't use an abort in the following; it might cause the printf to - not make it all the way to output and make debugging more - difficult. */ - - /* We assume the program is called with no path, so we might need to - prepend it. */ - if (getcwd (buf2, sizeof (buf2)) != buf2) - { - perror ("getcwd"); - exit (1); - } - - if (argv[0][0] == '/') - { -#ifdef SYSROOTED - if (strchr (argv[0] + 1, '/') != NULL) - { - printf ("%s != %s\n", argv[0], strrchr (argv[0] + 1, '/')); - exit (1); - } -#endif - if (strcmp (argv[0], buf) != 0) - { - printf ("%s != %s\n", buf, argv[0]); - exit (1); - } - } - else if (argv[0][0] != '.') - { - if (buf2[strlen (buf2) - 1] != '/') - strcat (buf2, "/"); - strcat (buf2, argv[0]); - if (strcmp (buf2, buf) != 0) - { - printf ("%s != %s\n", buf, buf2); - exit (1); - } - } - else - { - strcat (buf2, argv[0] + 1); - if (strcmp (buf, buf2) != 0) - { - printf ("%s != %s\n", buf, buf2); - exit (1); - } - } - - printf ("pass\n"); - exit (0); -} - - diff --git a/sim/testsuite/sim/cris/c/readlink3.c b/sim/testsuite/sim/cris/c/readlink3.c deleted file mode 100644 index 94cff72..0000000 --- a/sim/testsuite/sim/cris/c/readlink3.c +++ /dev/null @@ -1,6 +0,0 @@ -/* Simulator options: -#notarget: cris*-*-elf -#sim: --sysroot=@exedir@ -*/ -#define SYSROOTED 1 -#include "readlink2.c" diff --git a/sim/testsuite/sim/cris/c/readlink4.c b/sim/testsuite/sim/cris/c/readlink4.c deleted file mode 100644 index 028f3ee..0000000 --- a/sim/testsuite/sim/cris/c/readlink4.c +++ /dev/null @@ -1,62 +0,0 @@ -/* Check for corner case: readlink of too-long name. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include -#include - -void bye (const char *s, int i) -{ - fprintf (stderr, "%s: %d\n", s, i); - fflush (NULL); - abort (); -} - -int main (int argc, char *argv[]) -{ - char *buf; - char buf2[1024]; - int max, i; - - /* We assume this limit is what we see in the simulator as well. */ -#ifdef PATH_MAX - max = PATH_MAX; -#else - max = pathconf (argv[0], _PC_PATH_MAX); -#endif - - max *= 10; - - if (max <= 0) - bye ("path_max", max); - - if ((buf = malloc (max + 1)) == NULL) - bye ("malloc", 0); - - strcat (buf, argv[0]); - - if (strrchr (buf, '/') == NULL) - strcat (buf, "./"); - - for (i = strrchr (buf, '/') - buf + 1; i < max; i++) - buf[i] = 'a'; - - buf [i] = 0; - - i = readlink (buf, buf2, sizeof (buf2) - 1); - if (i != -1) - bye ("i", i); - - if (errno != ENAMETOOLONG) - { - perror (buf); - bye ("errno", errno); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/readlink5.c b/sim/testsuite/sim/cris/c/readlink5.c deleted file mode 100644 index 80f20da..0000000 --- a/sim/testsuite/sim/cris/c/readlink5.c +++ /dev/null @@ -1,8 +0,0 @@ -/* Check that unsupported readlink calls don't cause the simulator to abort. -#notarget: cris*-*-elf -#dest: ./readlink5.c.x -#xerror: -#output: Unimplemented readlink syscall (*)\n -#output: program stopped with signal 4 (*).\n -*/ -#include "readlink2.c" diff --git a/sim/testsuite/sim/cris/c/readlink6.c b/sim/testsuite/sim/cris/c/readlink6.c deleted file mode 100644 index 4bac20d..0000000 --- a/sim/testsuite/sim/cris/c/readlink6.c +++ /dev/null @@ -1,5 +0,0 @@ -/* Check that rare readlink calls don't cause the simulator to abort. -#notarget: cris*-*-elf -#dest: @exedir@/readlink6.c.x -*/ -#include "readlink2.c" diff --git a/sim/testsuite/sim/cris/c/readlink7.c b/sim/testsuite/sim/cris/c/readlink7.c deleted file mode 100644 index 9c2b3b7..0000000 --- a/sim/testsuite/sim/cris/c/readlink7.c +++ /dev/null @@ -1,6 +0,0 @@ -/* Check that rare readlink calls don't cause the simulator to abort. -#notarget: cris*-*-elf -#simenv: env(-u\ PWD\ foo)=bar - FIXME: Need to unset PWD, but right now I won't bother tweaking the - generic parts of the testsuite machinery and instead abuse a flaw. */ -#include "readlink2.c" diff --git a/sim/testsuite/sim/cris/c/readlink8.c b/sim/testsuite/sim/cris/c/readlink8.c deleted file mode 100644 index 55f6fe8..0000000 --- a/sim/testsuite/sim/cris/c/readlink8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* Check that rare readlink calls don't cause the simulator to abort. -#notarget: cris*-*-elf -#sim: --sysroot=@exedir@ -#simenv: env(-u\ PWD\ foo)=bar - FIXME: Need to unset PWD, but right now I won't bother tweaking the - generic parts of the testsuite machinery and instead abuse a flaw. */ -#define SYSROOTED 1 -#include "readlink2.c" diff --git a/sim/testsuite/sim/cris/c/readlink9.c b/sim/testsuite/sim/cris/c/readlink9.c deleted file mode 100644 index 2788054..0000000 --- a/sim/testsuite/sim/cris/c/readlink9.c +++ /dev/null @@ -1,23 +0,0 @@ -/* Check that odd cases of readlink work. -#notarget: cris*-*-elf -#cc: additional_flags=-DX="@exedir@" -*/ - -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - /* We assume that "sim/testsuite" isn't renamed to anything that - together with "/" is shorter than 7 characters. */ - char buf[7]; - - if (readlink("/proc/42/exe", buf, sizeof (buf)) != sizeof (buf) - || strncmp (buf, X, sizeof (buf)) != 0) - abort (); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/rename2.c b/sim/testsuite/sim/cris/c/rename2.c deleted file mode 100644 index 39387d1..0000000 --- a/sim/testsuite/sim/cris/c/rename2.c +++ /dev/null @@ -1,38 +0,0 @@ -/* Test some execution paths for error cases. -#cc: additional_flags=-Wl,--section-start=.startup=0x8000 - The linker option is for sake of newlib, where the default program - layout starts at address 0. We need to change the layout so - there's no memory at 0, as all sim error checking is "lazy", - depending on lack of memory mapping. */ - -#include -#include -#include - -void err (const char *s) -{ - perror (s); - abort (); -} - -int main (int argc, char *argv[]) -{ - /* Avoid getting files with random characters due to errors - elsewhere. */ - if (argc != 1 - || (argv[0][0] != '.' && argv[0][0] != '/' && argv[0][0] != 'r')) - abort (); - - if (rename (argv[0], NULL) != -1 - || errno != EFAULT) - err ("rename 1 "); - - errno = 0; - - if (rename (NULL, argv[0]) != -1 - || errno != EFAULT) - err ("rename 2"); - - printf ("pass\n"); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/rtsigprocmask1.c b/sim/testsuite/sim/cris/c/rtsigprocmask1.c deleted file mode 100644 index b76c338..0000000 --- a/sim/testsuite/sim/cris/c/rtsigprocmask1.c +++ /dev/null @@ -1,51 +0,0 @@ -/* Compiler options: -#notarget: cris*-*-elf -#cc: additional_flags=-pthread -#xerror: -#output: Unimplemented rt_sigprocmask syscall (0x3, 0x0, 0x3dff*\n -#output: program stopped with signal 4 (*).\n - - Testing a signal handler corner case. */ - -#include -#include -#include -#include -#include -#include -#include - -static void * -process (void *arg) -{ - while (1) - sched_yield (); - return NULL; -} - -int -main (void) -{ - int retcode; - pthread_t th_a; - void *retval; - sigset_t sigs; - - if (sigemptyset (&sigs) != 0) - abort (); - - retcode = pthread_create (&th_a, NULL, process, NULL); - if (retcode != 0) - abort (); - - /* An invalid parameter 1 should cause this to halt the simulator. */ - retcode - = pthread_sigmask (SIG_BLOCK + SIG_UNBLOCK + SIG_SETMASK, NULL, &sigs); - /* Direct return of the error number; i.e. not using -1 and errno, - is the actual documented behavior. */ - if (retcode == ENOSYS) - printf ("ENOSYS\n"); - - printf ("xyzzy\n"); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/rtsigprocmask2.c b/sim/testsuite/sim/cris/c/rtsigprocmask2.c deleted file mode 100644 index 5026908..0000000 --- a/sim/testsuite/sim/cris/c/rtsigprocmask2.c +++ /dev/null @@ -1,9 +0,0 @@ -/* As the included file, but specifying silent ENOSYS. -#notarget: cris*-*-elf -#cc: additional_flags=-pthread -#sim: --cris-unknown-syscall=enosys-quiet -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "rtsigprocmask1.c" diff --git a/sim/testsuite/sim/cris/c/rtsigsuspend1.c b/sim/testsuite/sim/cris/c/rtsigsuspend1.c deleted file mode 100644 index 66ca795..0000000 --- a/sim/testsuite/sim/cris/c/rtsigsuspend1.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Test that TRT happens for invalid rt_sigsuspend calls. Single-thread. -#notarget: cris*-*-elf -#xerror: -#output: Unimplemented rt_sigsuspend syscall arguments (0x1, 0x2)\n -#output: program stopped with signal 4 (*).\n -*/ - -#include -#include -#include -#include -#include - -int main (void) -{ - int err = syscall (SYS_rt_sigsuspend, 1, 2); - if (err == -1 && errno == ENOSYS) - printf ("ENOSYS\n"); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/rtsigsuspend2.c b/sim/testsuite/sim/cris/c/rtsigsuspend2.c deleted file mode 100644 index 9ce165d..0000000 --- a/sim/testsuite/sim/cris/c/rtsigsuspend2.c +++ /dev/null @@ -1,8 +0,0 @@ -/* As the included file, but specifying silent ENOSYS. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=enosys-quiet -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "rtsigsuspend1.c" diff --git a/sim/testsuite/sim/cris/c/sched1.c b/sim/testsuite/sim/cris/c/sched1.c deleted file mode 100644 index 1b778f4..0000000 --- a/sim/testsuite/sim/cris/c/sched1.c +++ /dev/null @@ -1,16 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include - -int main (void) -{ - if (sched_getscheduler (getpid ()) != SCHED_OTHER) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sched2.c b/sim/testsuite/sim/cris/c/sched2.c deleted file mode 100644 index f40a19a..0000000 --- a/sim/testsuite/sim/cris/c/sched2.c +++ /dev/null @@ -1,20 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include - -int main (void) -{ - struct sched_param sb; - memset (&sb, -1, sizeof sb); - if (sched_getparam (getpid (), &sb) != 0 - || sb.sched_priority != 0) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sched3.c b/sim/testsuite/sim/cris/c/sched3.c deleted file mode 100644 index 2909a4b..0000000 --- a/sim/testsuite/sim/cris/c/sched3.c +++ /dev/null @@ -1,25 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include - -int main (void) -{ - struct sched_param sb; - sb.sched_priority = 0; - if (sched_setscheduler (getpid (), SCHED_OTHER, &sb) != 0 - || sb.sched_priority != 0) - abort (); - sb.sched_priority = 5; - if (sched_setscheduler (getpid (), SCHED_OTHER, &sb) != -1 - || errno != EINVAL - || sb.sched_priority != 5) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sched4.c b/sim/testsuite/sim/cris/c/sched4.c deleted file mode 100644 index df372f2..0000000 --- a/sim/testsuite/sim/cris/c/sched4.c +++ /dev/null @@ -1,25 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include - -int main (void) -{ - struct sched_param sb; - sb.sched_priority = 0; - if (sched_setparam (getpid (), &sb) != 0 - || sb.sched_priority != 0) - abort (); - sb.sched_priority = 5; - if (sched_setparam (getpid (), &sb) == 0 - || errno != EINVAL - || sb.sched_priority != 5) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sched5.c b/sim/testsuite/sim/cris/c/sched5.c deleted file mode 100644 index ddfe14d..0000000 --- a/sim/testsuite/sim/cris/c/sched5.c +++ /dev/null @@ -1,19 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include -int main (void) -{ - int Min = sched_get_priority_min (SCHED_OTHER); - int Max = sched_get_priority_max (SCHED_OTHER); - if (Min != 0 || Max != 0) - { - fprintf (stderr, "min: %d, max: %d\n", Min, Max); - abort (); - } - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sched6.c b/sim/testsuite/sim/cris/c/sched6.c deleted file mode 100644 index d5adedc..0000000 --- a/sim/testsuite/sim/cris/c/sched6.c +++ /dev/null @@ -1,15 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include - -int main (void) -{ - if (sched_yield () != 0) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sched7.c b/sim/testsuite/sim/cris/c/sched7.c deleted file mode 100644 index 35d006b..0000000 --- a/sim/testsuite/sim/cris/c/sched7.c +++ /dev/null @@ -1,17 +0,0 @@ -/* Check corner error case: specifying invalid PID. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include - -int main (void) -{ - if (sched_getscheduler (99) != -1 - || errno != ESRCH) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sched8.c b/sim/testsuite/sim/cris/c/sched8.c deleted file mode 100644 index cd3e06e..0000000 --- a/sim/testsuite/sim/cris/c/sched8.c +++ /dev/null @@ -1,19 +0,0 @@ -/* Check corner error case: specifying invalid PID. -#notarget: cris*-*-elf -*/ -#include -#include -#include -#include -#include - -int main (void) -{ - struct sched_param sb; - memset (&sb, -1, sizeof sb); - if (sched_getparam (99, &sb) != -1 - || errno != ESRCH) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sched9.c b/sim/testsuite/sim/cris/c/sched9.c deleted file mode 100644 index 8499e43..0000000 --- a/sim/testsuite/sim/cris/c/sched9.c +++ /dev/null @@ -1,24 +0,0 @@ -/* Check corner error case: specifying invalid scheduling policy. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include - -int main (void) -{ - if (sched_get_priority_min (-1) != -1 - || errno != EINVAL) - abort (); - - errno = 0; - - if (sched_get_priority_max (-1) != -1 - || errno != EINVAL) - abort (); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/seek1.c b/sim/testsuite/sim/cris/c/seek1.c deleted file mode 100644 index b22c8f9..0000000 --- a/sim/testsuite/sim/cris/c/seek1.c +++ /dev/null @@ -1,47 +0,0 @@ -/* Check that basic (ll|f)seek sim functionality works. Also uses basic - file open/write functionality. */ -#include -#include -#include - -int -main (void) -{ - FILE *f; - const char fname[] = "sk1test.dat"; - const char tsttxt[] - = "A random line of text, used to test correct read, write and seek.\n"; - char buf[sizeof tsttxt] = ""; - - f = fopen (fname, "w"); - if (f == NULL - || fwrite (tsttxt, 1, strlen (tsttxt), f) != strlen (tsttxt) - || fclose (f) != 0) - { - printf ("fail\n"); - exit (1); - } - - /* Using "rb" to make this test similar to the use in genconf.c in - GhostScript. */ - f = fopen (fname, "rb"); - if (f == NULL - || fseek (f, 0L, SEEK_END) != 0 - || ftell (f) != strlen (tsttxt)) - { - printf ("fail\n"); - exit (1); - } - - rewind (f); - if (fread (buf, 1, strlen (tsttxt), f) != strlen (tsttxt) - || strcmp (buf, tsttxt) != 0 - || fclose (f) != 0) - { - printf ("fail\n"); - exit (1); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/seek2.c b/sim/testsuite/sim/cris/c/seek2.c deleted file mode 100644 index 9c24dfb..0000000 --- a/sim/testsuite/sim/cris/c/seek2.c +++ /dev/null @@ -1,4 +0,0 @@ -/* Simulator options: -#sim: --sysroot=@exedir@/ -*/ -#include "seek1.c" diff --git a/sim/testsuite/sim/cris/c/seek3.c b/sim/testsuite/sim/cris/c/seek3.c deleted file mode 100644 index 5e7b578..0000000 --- a/sim/testsuite/sim/cris/c/seek3.c +++ /dev/null @@ -1,49 +0,0 @@ -/* Check for a sim bug, whereby the position was always unsigned - (truncation instead of sign-extension for 64-bit hosts). */ -#include -#include -#include -#include -#include -#include -#include - -int -main (void) -{ - FILE *f; - const char fname[] = "sk1test.dat"; - const char tsttxt[] - = "A random line of text, used to test correct read, write and seek.\n"; - char buf[sizeof tsttxt] = ""; - const char correct[] = "correct"; - char buf2[sizeof correct] = {0}; - int fd; - - f = fopen (fname, "wb"); - if (f == NULL - || fwrite (tsttxt, 1, strlen (tsttxt), f) != strlen (tsttxt) - || fclose (f) != 0) - { - printf ("fail\n"); - exit (1); - } - - /* We have to use file-descriptor calls instead of stream calls to - provoke the bug (for stream calls, the lseek call is canonicalized - to use SEEK_SET). */ - fd = open (fname, O_RDONLY); - if (fd < 0 - || read (fd, buf, strlen (tsttxt)) != strlen (tsttxt) - || strcmp (buf, tsttxt) != 0 - || lseek (fd, -30L, SEEK_CUR) != 36 - || read (fd, buf2, strlen (correct)) != strlen (correct) - || strcmp (buf2, correct) != 0) - { - printf ("fail\n"); - exit (1); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/seek4.c b/sim/testsuite/sim/cris/c/seek4.c deleted file mode 100644 index 16f3bb0..0000000 --- a/sim/testsuite/sim/cris/c/seek4.c +++ /dev/null @@ -1,44 +0,0 @@ -/* Check for a sim bug, whereby an invalid seek (to a negative offset) - did not return an error. */ -#include -#include -#include -#include -#include -#include -#include -#include - -int -main (void) -{ - FILE *f; - const char fname[] = "sk1test.dat"; - const char tsttxt[] - = "A random line of text, used to test correct read, write and seek.\n"; - char buf[sizeof tsttxt] = ""; - int fd; - - f = fopen (fname, "wb"); - if (f == NULL - || fwrite (tsttxt, 1, strlen (tsttxt), f) != strlen (tsttxt) - || fclose (f) != 0) - { - printf ("fail\n"); - exit (1); - } - - fd = open (fname, O_RDONLY); - if (fd < 0 - || lseek (fd, -1L, SEEK_CUR) != -1 - || errno != EINVAL - || read (fd, buf, strlen (tsttxt)) != strlen (tsttxt) - || strcmp (buf, tsttxt) != 0) - { - printf ("fail\n"); - exit (1); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/setrlimit1.c b/sim/testsuite/sim/cris/c/setrlimit1.c deleted file mode 100644 index 747f16c..0000000 --- a/sim/testsuite/sim/cris/c/setrlimit1.c +++ /dev/null @@ -1,22 +0,0 @@ -/* Check corner error case: specifying unimplemented resource. -#notarget: cris*-*-elf -*/ -#include -#include -#include -#include -#include -#include -#include - -int main (void) -{ - struct rlimit lim; - memset (&lim, 0, sizeof lim); - - if (setrlimit (RLIMIT_NPROC, &lim) != -1 - || errno != EINVAL) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/settls1.c b/sim/testsuite/sim/cris/c/settls1.c deleted file mode 100644 index bd55aa1..0000000 --- a/sim/testsuite/sim/cris/c/settls1.c +++ /dev/null @@ -1,49 +0,0 @@ -/* Check that the syscall set_thread_area is supported and does the right thing. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include - -#ifndef SYS_set_thread_area -#define SYS_set_thread_area 243 -#endif - -int main (void) -{ - int ret; - - /* Check the error check that the low 8 bits must be 0. */ - ret = syscall (SYS_set_thread_area, 0xfeeb1ff0); - if (ret != -1 || errno != EINVAL) - { - perror ("tls1"); - abort (); - } - - ret = syscall (SYS_set_thread_area, 0xcafebe00); - if (ret != 0) - { - perror ("tls2"); - abort (); - } - - /* Check that we got the right result. */ -#ifdef __arch_v32 - asm ("move $pid,%0\n\tclear.b %0" : "=rm" (ret)); -#else - asm ("move $brp,%0" : "=rm" (ret)); -#endif - - if (ret != 0xcafebe00) - { - perror ("tls2"); - abort (); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sig1.c b/sim/testsuite/sim/cris/c/sig1.c deleted file mode 100644 index 55499b7..0000000 --- a/sim/testsuite/sim/cris/c/sig1.c +++ /dev/null @@ -1,20 +0,0 @@ -#include -#include -#include - -void -leave (int n) -{ - exit (0); -} - -int -main (void) -{ - /* Check that the sigaction syscall (for signal) is interpreted, though - possibly ignored. */ - signal (SIGFPE, leave); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sig10.c b/sim/testsuite/sim/cris/c/sig10.c deleted file mode 100644 index ef54832..0000000 --- a/sim/testsuite/sim/cris/c/sig10.c +++ /dev/null @@ -1,33 +0,0 @@ -/* Check that TRT happens when trying to IGN an non-ignorable signal, more than one thread. -#notarget: cris*-*-elf -#cc: additional_flags=-pthread -#xerror: -#output: Exiting pid 42 due to signal 9\n -#output: program stopped with signal 4 (*).\n -*/ - -#include -#include -#include -#include -#include -#include -#include - -static void * -process (void *arg) -{ - while (1) - sched_yield (); - return NULL; -} - -int main (void) -{ - pthread_t th_a; - signal (SIGKILL, SIG_IGN); - if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) - kill (getpid (), SIGKILL); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sig11.c b/sim/testsuite/sim/cris/c/sig11.c deleted file mode 100644 index 9c8aad7..0000000 --- a/sim/testsuite/sim/cris/c/sig11.c +++ /dev/null @@ -1,32 +0,0 @@ -/* Check that TRT happens when getting a non-standard (realtime) signal, more than one thread. -#notarget: cris*-*-elf -#cc: additional_flags=-pthread -#xerror: -#output: Unimplemented signal: 77\n -#output: program stopped with signal 4 (*).\n -*/ - -#include -#include -#include -#include -#include -#include -#include - -static void * -process (void *arg) -{ - while (1) - sched_yield (); - return NULL; -} - -int main (void) -{ - pthread_t th_a; - if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) - kill (getpid (), 77); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sig12.c b/sim/testsuite/sim/cris/c/sig12.c deleted file mode 100644 index 5a2e65f..0000000 --- a/sim/testsuite/sim/cris/c/sig12.c +++ /dev/null @@ -1,38 +0,0 @@ -/* Check that TRT happens for a signal sent to a non-existent process/thread, more than one thread. -#cc: additional_flags=-pthread -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -static void * -process (void *arg) -{ - int i; - for (i = 0; i < 100; i++) - sched_yield (); - return NULL; -} - -int main (void) -{ - pthread_t th_a; - int retcode; - void *retval; - - if (pthread_create (&th_a, NULL, process, (void *) "a") != 0) - abort (); - if (kill (getpid () - 1, SIGBUS) != -1 - || errno != ESRCH - || pthread_join (th_a, &retval) != 0) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sig13.c b/sim/testsuite/sim/cris/c/sig13.c deleted file mode 100644 index 4d71752..0000000 --- a/sim/testsuite/sim/cris/c/sig13.c +++ /dev/null @@ -1,8 +0,0 @@ -/* As the included file, but specifying silent ENOSYS. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=enosys-quiet -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "sig7.c" diff --git a/sim/testsuite/sim/cris/c/sig2.c b/sim/testsuite/sim/cris/c/sig2.c deleted file mode 100644 index 65596ef..0000000 --- a/sim/testsuite/sim/cris/c/sig2.c +++ /dev/null @@ -1,32 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include - -/* Like sig1.c, but using sigaction. */ - -void -leave (int n, siginfo_t *info, void *x) -{ - abort (); -} - -int -main (void) -{ - struct sigaction sa; - sa.sa_sigaction = leave; - sa.sa_flags = SA_RESTART | SA_SIGINFO; - sigemptyset (&sa.sa_mask); - - /* Check that the sigaction syscall (for signal) is interpreted, though - possibly ignored. */ - if (sigaction (SIGFPE, &sa, NULL) != 0) - abort (); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sig3.c b/sim/testsuite/sim/cris/c/sig3.c deleted file mode 100644 index 91de227..0000000 --- a/sim/testsuite/sim/cris/c/sig3.c +++ /dev/null @@ -1,13 +0,0 @@ -/* Check that TRT happens at an abort (3) call, single thread. -#xerror: -#output: program stopped with signal 6 (*).\n -*/ - -#include -#include -int main (void) -{ - abort (); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sig4.c b/sim/testsuite/sim/cris/c/sig4.c deleted file mode 100644 index 57491f8..0000000 --- a/sim/testsuite/sim/cris/c/sig4.c +++ /dev/null @@ -1,30 +0,0 @@ -/* Check that TRT happens at an abort (3) call, more than one thread. -#notarget: cris*-*-elf -#cc: additional_flags=-pthread -#xerror: -#output: Exiting pid 42 due to signal 6\n -#output: program stopped with signal 6 (*).\n -*/ - -#include -#include -#include -#include -#include - -static void * -process (void *arg) -{ - while (1) - sched_yield (); - return NULL; -} - -int main (void) -{ - pthread_t th_a; - if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) - abort (); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sig5.c b/sim/testsuite/sim/cris/c/sig5.c deleted file mode 100644 index f80da2b..0000000 --- a/sim/testsuite/sim/cris/c/sig5.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Check that TRT happens for an uncaught non-abort signal, single thread. -#xerror: -#output: Unimplemented signal: 7\n -#output: program stopped with signal 4 (*).\n -*/ - -#include -#include -#include -#include -#include - -int main (void) -{ - kill (getpid (), SIGBUS); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sig6.c b/sim/testsuite/sim/cris/c/sig6.c deleted file mode 100644 index a1f5720..0000000 --- a/sim/testsuite/sim/cris/c/sig6.c +++ /dev/null @@ -1,32 +0,0 @@ -/* Check that TRT happens at an non-abort non-caught signal, more than one thread. -#notarget: cris*-*-elf -#cc: additional_flags=-pthread -#xerror: -#output: Exiting pid 42 due to signal 7\n -#output: program stopped with signal 4 (*).\n -*/ - -#include -#include -#include -#include -#include -#include -#include - -static void * -process (void *arg) -{ - while (1) - sched_yield (); - return NULL; -} - -int main (void) -{ - pthread_t th_a; - if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) - kill (getpid (), SIGBUS); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sig7.c b/sim/testsuite/sim/cris/c/sig7.c deleted file mode 100644 index b04f7c8..0000000 --- a/sim/testsuite/sim/cris/c/sig7.c +++ /dev/null @@ -1,27 +0,0 @@ -/* Check unsupported case of sigaction syscall. -#notarget: cris*-*-elf -#xerror: -#output: Unimplemented rt_sigaction syscall (0x8, 0x3df*\n -#output: program stopped with signal 4 (*).\n -*/ -#include -#include -#include -#include - -int -main (void) -{ - struct sigaction sa; - int err; - sa.sa_sigaction = NULL; - sa.sa_flags = SA_RESTART | SA_SIGINFO; - sigemptyset (&sa.sa_mask); - - err = sigaction (SIGFPE, &sa, NULL); - if (err == -1 && errno == ENOSYS) - printf ("ENOSYS\n"); - - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sig8.c b/sim/testsuite/sim/cris/c/sig8.c deleted file mode 100644 index ea2d7f5..0000000 --- a/sim/testsuite/sim/cris/c/sig8.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Check that TRT happens for an ignored catchable signal, single thread. -#xerror: -#output: Unimplemented signal: 14\n -#output: program stopped with signal 4 (*).\n - - Sure, it'd probably be better to support signals in single-thread too, - but that's on an as-need basis, and I don't have a need for it yet. */ - -#include -#include -#include -#include -#include - -int main (void) -{ - signal (SIGALRM, SIG_IGN); - kill (getpid (), SIGALRM); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sig9.c b/sim/testsuite/sim/cris/c/sig9.c deleted file mode 100644 index c86681b..0000000 --- a/sim/testsuite/sim/cris/c/sig9.c +++ /dev/null @@ -1,36 +0,0 @@ -/* Check that TRT happens at an non-abort ignored signal, more than one thread. -#notarget: cris*-*-elf -#cc: additional_flags=-pthread -*/ - -#include -#include -#include -#include -#include -#include -#include - -static void * -process (void *arg) -{ - int i; - for (i = 0; i < 100; i++) - sched_yield (); - return NULL; -} - -int main (void) -{ - pthread_t th_a; - int retcode; - void *retval; - signal (SIGALRM, SIG_IGN); - if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) - kill (getpid (), SIGALRM); - retcode = pthread_join (th_a, &retval); - if (retcode != 0 || retval != NULL) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sigreturn1.c b/sim/testsuite/sim/cris/c/sigreturn1.c deleted file mode 100644 index 40fc852..0000000 --- a/sim/testsuite/sim/cris/c/sigreturn1.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Test that TRT happens for spurious sigreturn calls. Single-thread. -#notarget: cris*-*-elf -#xerror: -#output: Invalid sigreturn syscall: no signal handler active (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n -#output: program stopped with signal 4 (*).\n -*/ - -#include -#include -#include -#include -#include - -int main (void) -{ - int err = syscall (SYS_sigreturn, 1, 2, 3, 4, 5, 6); - if (err == -1 && errno == ENOSYS) - printf ("ENOSYS\n"); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sigreturn2.c b/sim/testsuite/sim/cris/c/sigreturn2.c deleted file mode 100644 index 3848b5f..0000000 --- a/sim/testsuite/sim/cris/c/sigreturn2.c +++ /dev/null @@ -1,38 +0,0 @@ -/* Check that TRT happens for spurious sigreturn calls. Multiple threads. -#notarget: cris*-*-elf -#cc: additional_flags=-pthread -#xerror: -#output: Invalid sigreturn syscall: no signal handler active (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n -#output: program stopped with signal 4 (*).\n -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void * -process (void *arg) -{ - while (1) - sched_yield (); - return NULL; -} - -int main (void) -{ - pthread_t th_a; - if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) - { - int err = syscall (SYS_sigreturn, 1, 2, 3, 4, 5, 6); - if (err == -1 && errno == ENOSYS) - printf ("ENOSYS\n"); - } - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sigreturn3.c b/sim/testsuite/sim/cris/c/sigreturn3.c deleted file mode 100644 index f5ed90f..0000000 --- a/sim/testsuite/sim/cris/c/sigreturn3.c +++ /dev/null @@ -1,8 +0,0 @@ -/* As the included file, but specifying silent ENOSYS. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=enosys-quiet -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "sigreturn1.c" diff --git a/sim/testsuite/sim/cris/c/sigreturn4.c b/sim/testsuite/sim/cris/c/sigreturn4.c deleted file mode 100644 index 456e312..0000000 --- a/sim/testsuite/sim/cris/c/sigreturn4.c +++ /dev/null @@ -1,9 +0,0 @@ -/* As the included file, but specifying silent ENOSYS. -#notarget: cris*-*-elf -#cc: additional_flags=-pthread -#sim: --cris-unknown-syscall=enosys-quiet -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "sigreturn2.c" diff --git a/sim/testsuite/sim/cris/c/sjlj.c b/sim/testsuite/sim/cris/c/sjlj.c deleted file mode 100644 index 141faf6..0000000 --- a/sim/testsuite/sim/cris/c/sjlj.c +++ /dev/null @@ -1,34 +0,0 @@ -/* Check that setjmp and longjmp stand a chance to work; that the used machine - primitives work in the simulator. */ - -#include -#include -#include - -extern void f (void); - -int ok = 0; -jmp_buf b; - -int -main () -{ - int ret = setjmp (b); - - if (ret == 42) - ok = 100; - else if (ret == 0) - f (); - - if (ok == 100) - printf ("pass\n"); - else - printf ("fail\n"); - exit (0); -} - -void -f (void) -{ - longjmp (b, 42); -} diff --git a/sim/testsuite/sim/cris/c/sock1.c b/sim/testsuite/sim/cris/c/sock1.c deleted file mode 100644 index e59f673..0000000 --- a/sim/testsuite/sim/cris/c/sock1.c +++ /dev/null @@ -1,32 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include -#include - -/* Check that socketcall is suitably stubbed. */ - -int main (void) -{ - int ret = socket (PF_INET, SOCK_STREAM, IPPROTO_TCP); - - if (ret != -1) - { - fprintf (stderr, "sock: %d\n", ret); - abort (); - } - - if (errno != ENOSYS) - { - perror ("unexpected"); - abort (); - } - - printf ("pass\n"); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/stat1.c b/sim/testsuite/sim/cris/c/stat1.c deleted file mode 100644 index b5d14a3..0000000 --- a/sim/testsuite/sim/cris/c/stat1.c +++ /dev/null @@ -1,16 +0,0 @@ -#include -#include -#include -#include -#include - -int main (void) -{ - struct stat buf; - - if (stat (".", &buf) != 0 - || !S_ISDIR (buf.st_mode)) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/stat2.c b/sim/testsuite/sim/cris/c/stat2.c deleted file mode 100644 index 78c5c44..0000000 --- a/sim/testsuite/sim/cris/c/stat2.c +++ /dev/null @@ -1,20 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include - -int main (void) -{ - struct stat buf; - - if (lstat (".", &buf) != 0 - || !S_ISDIR (buf.st_mode)) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/stat3.c b/sim/testsuite/sim/cris/c/stat3.c deleted file mode 100644 index a248ec0..0000000 --- a/sim/testsuite/sim/cris/c/stat3.c +++ /dev/null @@ -1,26 +0,0 @@ -/* Simulator options: -#sim: --sysroot=@exedir@ -*/ -#include -#include -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - char path[1024] = "/"; - struct stat buf; - - strcat (path, argv[0]); - if (stat (".", &buf) != 0 - || !S_ISDIR (buf.st_mode)) - abort (); - if (stat (path, &buf) != 0 - || !S_ISREG (buf.st_mode)) - abort (); - printf ("pass\n"); - exit (0); -} - diff --git a/sim/testsuite/sim/cris/c/stat4.c b/sim/testsuite/sim/cris/c/stat4.c deleted file mode 100644 index 62415a3..0000000 --- a/sim/testsuite/sim/cris/c/stat4.c +++ /dev/null @@ -1,28 +0,0 @@ -/* Simulator options: -#notarget: cris*-*-elf -#sim: --sysroot=@exedir@ -*/ - -#include -#include -#include -#include -#include -#include - -int main (int argc, char *argv[]) -{ - char path[1024] = "/"; - struct stat buf; - - strcat (path, argv[0]); - if (lstat (".", &buf) != 0 - || !S_ISDIR (buf.st_mode)) - abort (); - if (lstat (path, &buf) != 0 - || !S_ISREG (buf.st_mode)) - abort (); - printf ("pass\n"); - exit (0); -} - diff --git a/sim/testsuite/sim/cris/c/stat5.c b/sim/testsuite/sim/cris/c/stat5.c deleted file mode 100644 index 41ab493..0000000 --- a/sim/testsuite/sim/cris/c/stat5.c +++ /dev/null @@ -1,20 +0,0 @@ -/* Check that lstat:ing an nonexistent file works as expected. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include -#include - -int main (void) -{ - struct stat buf; - - if (lstat ("nonexistent", &buf) == 0 || errno != ENOENT) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/stat7.c b/sim/testsuite/sim/cris/c/stat7.c deleted file mode 100644 index cbd5282..0000000 --- a/sim/testsuite/sim/cris/c/stat7.c +++ /dev/null @@ -1,26 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include -#include - -int main (void) -{ - struct stat buf; - - /* From Linux, we get EFAULT. The simulator sends us EINVAL. */ - if (lstat (NULL, &buf) != -1 - || (errno != EINVAL && errno != EFAULT)) - { - perror ("lstat 1"); - abort (); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/stat8.c b/sim/testsuite/sim/cris/c/stat8.c deleted file mode 100644 index c7eb49f..0000000 --- a/sim/testsuite/sim/cris/c/stat8.c +++ /dev/null @@ -1,26 +0,0 @@ -/* For this test, we need to do the lstat syscall directly, or else - glibc gets a SEGV. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include - -int main (void) -{ - int ret; - - /* From Linux, we get EFAULT. The simulator sends us EINVAL. */ - ret = syscall (SYS_lstat64, ".", NULL); - if (ret != -1 || (errno != EINVAL && errno != EFAULT)) - { - perror ("lstat"); - abort (); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/syscall1.c b/sim/testsuite/sim/cris/c/syscall1.c deleted file mode 100644 index 84aacb6..0000000 --- a/sim/testsuite/sim/cris/c/syscall1.c +++ /dev/null @@ -1,22 +0,0 @@ -/* Test unknown-syscall output. -#notarget: cris*-*-elf -#xerror: -#output: Unimplemented syscall: 166 (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n -#output: program stopped with signal 4 (*).\n -*/ - -#include -#include -#include -#include - -int main (void) -{ - /* The number 166 is chosen because there's a gap for that number in - the CRIS asm/unistd.h. */ - int err = syscall (166, 1, 2, 3, 4, 5, 6); - if (err == -1 && errno == ENOSYS) - printf ("ENOSYS\n"); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/syscall2.c b/sim/testsuite/sim/cris/c/syscall2.c deleted file mode 100644 index b4dbead..0000000 --- a/sim/testsuite/sim/cris/c/syscall2.c +++ /dev/null @@ -1,23 +0,0 @@ -/* Test unknown-syscall output. -#notarget: cris*-*-elf -#xerror: -#output: Unimplemented syscall: 0 (0x3, 0x2, 0x1, 0x4, 0x6, 0x5)\n -#output: program stopped with signal 4 (*).\n -*/ - -#include -#include -#include -#include - -int main (void) -{ - int err; - - /* Check special case of number 0 syscall. */ - err = syscall (0, 3, 2, 1, 4, 6, 5); - if (err == -1 && errno == ENOSYS) - printf ("ENOSYS\n"); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/syscall3.c b/sim/testsuite/sim/cris/c/syscall3.c deleted file mode 100644 index f4d02eb..0000000 --- a/sim/testsuite/sim/cris/c/syscall3.c +++ /dev/null @@ -1,9 +0,0 @@ -/* As the included file, just actually specifying the default. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=stop -#xerror: -#output: Unimplemented syscall: 166 (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n -#output: program stopped with signal 4 (*).\n -*/ - -#include "syscall1.c" diff --git a/sim/testsuite/sim/cris/c/syscall4.c b/sim/testsuite/sim/cris/c/syscall4.c deleted file mode 100644 index ba01cfd..0000000 --- a/sim/testsuite/sim/cris/c/syscall4.c +++ /dev/null @@ -1,9 +0,0 @@ -/* As the included file, just actually specifying the default. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=stop -#xerror: -#output: Unimplemented syscall: 0 (0x3, 0x2, 0x1, 0x4, 0x6, 0x5)\n -#output: program stopped with signal 4 (*).\n -*/ - -#include "syscall2.c" diff --git a/sim/testsuite/sim/cris/c/syscall5.c b/sim/testsuite/sim/cris/c/syscall5.c deleted file mode 100644 index 2eac900..0000000 --- a/sim/testsuite/sim/cris/c/syscall5.c +++ /dev/null @@ -1,9 +0,0 @@ -/* As the included file, but specifying ENOSYS with message. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=enosys -#output: Unimplemented syscall: 166 (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "syscall1.c" diff --git a/sim/testsuite/sim/cris/c/syscall6.c b/sim/testsuite/sim/cris/c/syscall6.c deleted file mode 100644 index 91375df..0000000 --- a/sim/testsuite/sim/cris/c/syscall6.c +++ /dev/null @@ -1,9 +0,0 @@ -/* As the included file, but specifying ENOSYS with message. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=enosys -#output: Unimplemented syscall: 0 (0x3, 0x2, 0x1, 0x4, 0x6, 0x5)\n -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "syscall2.c" diff --git a/sim/testsuite/sim/cris/c/syscall7.c b/sim/testsuite/sim/cris/c/syscall7.c deleted file mode 100644 index 0f1daf1..0000000 --- a/sim/testsuite/sim/cris/c/syscall7.c +++ /dev/null @@ -1,8 +0,0 @@ -/* As the included file, but specifying silent ENOSYS. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=enosys-quiet -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "syscall1.c" diff --git a/sim/testsuite/sim/cris/c/syscall8.c b/sim/testsuite/sim/cris/c/syscall8.c deleted file mode 100644 index c579436..0000000 --- a/sim/testsuite/sim/cris/c/syscall8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* As the included file, but specifying silent ENOSYS. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=enosys-quiet -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "syscall2.c" diff --git a/sim/testsuite/sim/cris/c/sysctl1.c b/sim/testsuite/sim/cris/c/sysctl1.c deleted file mode 100644 index 6646fac..0000000 --- a/sim/testsuite/sim/cris/c/sysctl1.c +++ /dev/null @@ -1,38 +0,0 @@ -/* -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include - -/* I can't seem to include the right things, so we do it brute force. */ -int main (void) -{ - static int sysctl_args[] = { 1, 4 }; - size_t x = 8; - - struct __sysctl_args { - int *name; - int nlen; - void *oldval; - size_t *oldlenp; - void *newval; - size_t newlen; - unsigned long __unused[4]; - } scargs - = - { - sysctl_args, - sizeof (sysctl_args) / sizeof (sysctl_args[0]), - (void *) -1, &x, NULL, 0 - }; - - if (syscall (SYS__sysctl, &scargs) != -1 - || errno != EFAULT) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sysctl2.c b/sim/testsuite/sim/cris/c/sysctl2.c deleted file mode 100644 index f27c37c..0000000 --- a/sim/testsuite/sim/cris/c/sysctl2.c +++ /dev/null @@ -1,41 +0,0 @@ -/* Check error message for invalid sysctl call. -#xerror: -#output: Unimplemented _sysctl syscall *\n -#output: program stopped with signal 4 (*).\n -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include -#include - -int main (void) -{ - static int sysctl_args[] = { 99, 99 }; - size_t x = 8; - - struct __sysctl_args { - int *name; - int nlen; - void *oldval; - size_t *oldlenp; - void *newval; - size_t newlen; - unsigned long __unused[4]; - } scargs - = - { - sysctl_args, - sizeof (sysctl_args) / sizeof (sysctl_args[0]), - (void *) -1, &x, NULL, 0 - }; - - int err = syscall (SYS__sysctl, &scargs); - if (err == -1 && errno == ENOSYS) - printf ("ENOSYS\n"); - printf ("xyzzy\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/sysctl3.c b/sim/testsuite/sim/cris/c/sysctl3.c deleted file mode 100644 index 747e784..0000000 --- a/sim/testsuite/sim/cris/c/sysctl3.c +++ /dev/null @@ -1,8 +0,0 @@ -/* As the included file, but specifying silent ENOSYS. -#notarget: cris*-*-elf -#sim: --cris-unknown-syscall=enosys-quiet -#output: ENOSYS\n -#output: xyzzy\n -*/ - -#include "sysctl2.c" diff --git a/sim/testsuite/sim/cris/c/thread2.c b/sim/testsuite/sim/cris/c/thread2.c deleted file mode 100644 index c9ad2f9..0000000 --- a/sim/testsuite/sim/cris/c/thread2.c +++ /dev/null @@ -1,28 +0,0 @@ -/* Compiler options: -#cc: additional_flags=-pthread -#notarget: cris*-*-elf - - A sanity check for syscalls resulting from - pthread_getschedparam and pthread_setschedparam. */ - -#include -#include -#include - -int main (void) -{ - struct sched_param param; - int policy; - - if (pthread_getschedparam (pthread_self (), &policy, ¶m) != 0 - || policy != SCHED_OTHER - || param.sched_priority != 0) - abort (); - - if (pthread_setschedparam (pthread_self (), SCHED_OTHER, ¶m) != 0 - || param.sched_priority != 0) - abort (); - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/thread3.c b/sim/testsuite/sim/cris/c/thread3.c deleted file mode 100644 index 3b6945a..0000000 --- a/sim/testsuite/sim/cris/c/thread3.c +++ /dev/null @@ -1,46 +0,0 @@ -/* Compiler options: -#cc: additional_flags=-pthread -#notarget: cris*-*-elf - - To test sched_yield in the presencs of threads. Core from ex1.c. */ - -#include -#include -#include -#include -#include - -static void * -process (void *arg) -{ - int i; - for (i = 0; i < 10; i++) - { - if (sched_yield () != 0) - abort (); - } - return NULL; -} - -int -main (void) -{ - int retcode; - pthread_t th_a, th_b; - void *retval; - - retcode = pthread_create (&th_a, NULL, process, (void *) "a"); - if (retcode != 0) - abort (); - retcode = pthread_create (&th_b, NULL, process, (void *) "b"); - if (retcode != 0) - abort (); - retcode = pthread_join (th_a, &retval); - if (retcode != 0) - abort (); - retcode = pthread_join (th_b, &retval); - if (retcode != 0) - abort (); - printf ("pass\n"); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/thread4.c b/sim/testsuite/sim/cris/c/thread4.c deleted file mode 100644 index cfa2327..0000000 --- a/sim/testsuite/sim/cris/c/thread4.c +++ /dev/null @@ -1,50 +0,0 @@ -/* Compiler options: -#notarget: cris*-*-elf -#cc: additional_flags=-pthread -#output: abb ok\n - - Testing a pthread corner case. Output will change with glibc - releases. */ - -#include -#include -#include -#include -#include - -static void * -process (void *arg) -{ - int i; - - if (pthread_setcancelstate (PTHREAD_CANCEL_ENABLE, NULL) != 0) - abort (); - write (2, "a", 1); - for (i = 0; i < 10; i++) - { - sched_yield (); - pthread_testcancel (); - write (2, "b", 1); - } - return NULL; -} - -int -main (void) -{ - int retcode; - pthread_t th_a; - void *retval; - - retcode = pthread_create (&th_a, NULL, process, NULL); - sched_yield (); - sched_yield (); - sched_yield (); - sched_yield (); - retcode = pthread_cancel (th_a); - retcode = pthread_join (th_a, &retval); - if (retcode != 0) - abort (); - fprintf (stderr, " ok\n"); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/thread5.c b/sim/testsuite/sim/cris/c/thread5.c deleted file mode 100644 index 494251f..0000000 --- a/sim/testsuite/sim/cris/c/thread5.c +++ /dev/null @@ -1,77 +0,0 @@ -/* Compiler options: -#notarget: cris*-*-elf -#cc: additional_flags=-pthread -#output: abbb ok\n - - Testing a signal handler corner case. */ - -#include -#include -#include -#include -#include -#include - -static void * -process (void *arg) -{ - write (2, "a", 1); - write (2, "b", 1); - write (2, "b", 1); - write (2, "b", 1); - return NULL; -} - -int ok = 0; -volatile int done = 0; - -void -sigusr1 (int signum) -{ - if (signum != SIGUSR1 || !ok) - abort (); - done = 1; -} - -int -main (void) -{ - int retcode; - pthread_t th_a; - void *retval; - sigset_t sigs; - - if (sigemptyset (&sigs) != 0) - abort (); - - retcode = pthread_create (&th_a, NULL, process, NULL); - if (retcode != 0) - abort (); - - if (signal (SIGUSR1, sigusr1) != SIG_DFL) - abort (); - if (pthread_sigmask (SIG_BLOCK, NULL, &sigs) != 0 - || sigaddset (&sigs, SIGUSR1) != 0 - || pthread_sigmask (SIG_BLOCK, &sigs, NULL) != 0) - abort (); - if (pthread_kill (pthread_self (), SIGUSR1) != 0 - || sched_yield () != 0 - || sched_yield () != 0 - || sched_yield () != 0) - abort (); - - ok = 1; - if (pthread_sigmask (SIG_UNBLOCK, NULL, &sigs) != 0 - || sigaddset (&sigs, SIGUSR1) != 0 - || pthread_sigmask (SIG_UNBLOCK, &sigs, NULL) != 0) - abort (); - - if (!done) - abort (); - - retcode = pthread_join (th_a, &retval); - if (retcode != 0) - abort (); - fprintf (stderr, " ok\n"); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/time1.c b/sim/testsuite/sim/cris/c/time1.c deleted file mode 100644 index 3fcf0e1..0000000 --- a/sim/testsuite/sim/cris/c/time1.c +++ /dev/null @@ -1,46 +0,0 @@ -/* Basic time functionality test: check that milliseconds are - incremented for each syscall (does not work on host). */ -#include -#include -#include -#include -#include - -void err (const char *s) -{ - perror (s); - abort (); -} - -int -main (void) -{ - struct timeval t_m = {0, 0}; - struct timezone t_z = {0, 0}; - struct timeval t_m1 = {0, 0}; - int i; - - if (gettimeofday (&t_m, &t_z) != 0) - err ("gettimeofday"); - - for (i = 1; i < 10000; i++) - if (gettimeofday (&t_m1, NULL) != 0) - err ("gettimeofday 1"); - else - if (t_m1.tv_sec * 1000000 + t_m1.tv_usec - != (t_m.tv_sec * 1000000 + t_m.tv_usec + i * 1000)) - { - fprintf (stderr, "t0 (%ld, %ld), i %d, t1 (%ld, %ld)\n", - t_m.tv_sec, t_m.tv_usec, i, t_m1.tv_sec, t_m1.tv_usec); - abort (); - } - - if (time (NULL) != t_m1.tv_sec) - { - fprintf (stderr, "time != gettod\n"); - abort (); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/time2.c b/sim/testsuite/sim/cris/c/time2.c deleted file mode 100644 index 20b69b4..0000000 --- a/sim/testsuite/sim/cris/c/time2.c +++ /dev/null @@ -1,18 +0,0 @@ -/* CB_SYS_time doesn't implement the Linux time syscall; the return - value isn't written to the argument. */ - -#include -#include -#include - -int -main (void) -{ - time_t x = (time_t) -1; - time_t t = time (&x); - - if (t == (time_t) -1 || t != x) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/truncate1.c b/sim/testsuite/sim/cris/c/truncate1.c deleted file mode 100644 index 477dc3d..0000000 --- a/sim/testsuite/sim/cris/c/truncate1.c +++ /dev/null @@ -1,49 +0,0 @@ -/* Check that the truncate syscall works trivially. -#notarget: cris*-*-elf -*/ - -#include -#include -#include - -#ifndef PREFIX -#define PREFIX -#endif -int -main (void) -{ - FILE *f; - const char fname[] = PREFIX "sk1test.dat"; - const char tsttxt1[] - = "This is the first and only line of this file.\n"; - const char tsttxt2[] = "Now there is a second line.\n"; - char buf[sizeof (tsttxt1) + sizeof (tsttxt2) - 1] = ""; - - f = fopen (fname, "w+"); - if (f == NULL - || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1) - || fclose (f) != 0) - { - printf ("fail\n"); - exit (1); - } - - if (truncate (fname, strlen(tsttxt1) - 10) != 0) - { - perror ("truncate"); - exit (1); - } - - f = fopen (fname, "r"); - if (f == NULL - || fread (buf, 1, sizeof (buf), f) != strlen (tsttxt1) - 10 - || strncmp (buf, tsttxt1, strlen (tsttxt1) - 10) != 0 - || fclose (f) != 0) - { - printf ("fail\n"); - exit (1); - } - - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/truncate2.c b/sim/testsuite/sim/cris/c/truncate2.c deleted file mode 100644 index a4c6470..0000000 --- a/sim/testsuite/sim/cris/c/truncate2.c +++ /dev/null @@ -1,6 +0,0 @@ -/* -#sim: --sysroot=@exedir@ -#notarget: cris*-*-elf -*/ -#define PREFIX "/" -#include "truncate1.c" diff --git a/sim/testsuite/sim/cris/c/ugetrlimit1.c b/sim/testsuite/sim/cris/c/ugetrlimit1.c deleted file mode 100644 index 2a49b95..0000000 --- a/sim/testsuite/sim/cris/c/ugetrlimit1.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Check corner error case: specifying unimplemented resource. -#notarget: cris*-*-elf -*/ - -#include -#include -#include -#include -#include -#include - -int main (void) -{ - struct rlimit lim; - - if (getrlimit (RLIMIT_NPROC, &lim) != -1 - || errno != EINVAL) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/uname1.c b/sim/testsuite/sim/cris/c/uname1.c deleted file mode 100644 index 83518d6..0000000 --- a/sim/testsuite/sim/cris/c/uname1.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Check that the right machine name appears in the uname result. -#notarget: *-*-elf -*/ -#include -#include -#include -int main (void) -{ - struct utsname buf; - if (uname (&buf) != 0 - || strcmp (buf.machine, -#ifdef __arch_v32 - "crisv32" -#else - "cris" -#endif - ) != 0) - abort (); - printf ("pass\n"); - exit (0); -} diff --git a/sim/testsuite/sim/cris/c/writev1.c b/sim/testsuite/sim/cris/c/writev1.c deleted file mode 100644 index fad5b7f..0000000 --- a/sim/testsuite/sim/cris/c/writev1.c +++ /dev/null @@ -1,25 +0,0 @@ -/* Trivial test of writev. -#notarget: cris*-*-elf -#output: abcdefghijklmn\npass\n -*/ -#include -#include -#include - -#define X(x) {x, sizeof (x) -1} -struct iovec v[] = { - X("a"), - X("bcd"), - X("efghi"), - X("j"), - X("klmn\n"), -}; - -int main (void) -{ - if (writev (1, v, sizeof v / sizeof (v[0])) != 15) - abort (); - - printf ("pass\n"); - return 0; -} diff --git a/sim/testsuite/sim/cris/c/writev2.c b/sim/testsuite/sim/cris/c/writev2.c deleted file mode 100644 index 5cb92b6..0000000 --- a/sim/testsuite/sim/cris/c/writev2.c +++ /dev/null @@ -1,28 +0,0 @@ -/* Trivial test of failing writev: invalid file descriptor. -#notarget: cris*-*-elf -*/ -#include -#include -#include -#include - -#define X(x) {x, sizeof (x) -1} -struct iovec v[] = { - X("a"), - X("bcd"), - X("efghi"), - X("j"), - X("klmn\n"), -}; - -int main (void) -{ - if (writev (99, v, sizeof v / sizeof (v[0])) != -1 - /* The simulator write gives EINVAL instead of EBADF; let's - cope. */ - || (errno != EBADF && errno != EINVAL)) - abort (); - - printf ("pass\n"); - return 0; -} diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/host1.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/host1.ms deleted file mode 100644 index c41f51f..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/host1.ms +++ /dev/null @@ -1,8 +0,0 @@ -#mach: crisv32 -#sim(crisv32): --hw-device "/rv/host localhost" - -# Check that we trivially resolve a hostname. - -#r @,@srcdir@/trivial4.r - - .include "trivial4.ms" diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/irq1.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/irq1.ms deleted file mode 100644 index f3e6f2e..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/irq1.ms +++ /dev/null @@ -1,69 +0,0 @@ -#mach: crisv10 crisv32 -#sim(crisv10): --hw-device "/rv/trace? true" -#sim(crisv32): --hw-device "/rv/trace? true" -#output: /rv: WD\n -#output: /rv: REG R 0xd0000032\n -#output: /rv: := 0xabcdef01\n -#output: /rv: IRQ 0x4\n -#output: /rv: REG R 0xd0000036\n -#output: /rv: := 0x76543210\n -#output: /rv: REG R 0xd0000036\n -#output: /rv: := 0x76543211\n -#output: /rv: REG R 0xd0000030\n -#output: /rv: IRQ 0x0\n -#output: /rv: := 0xeeff4455\n -#output: pass\n - -# Trivial test of interrupts. -# Locations of IRQ notifiers above depend on when the simulator is -# polled; adjustments may be needed (after checking that no poll is -# gone due to a bug!) - -#r W, -#r r,a8832,abcdef01 -#r I,4 -#r r,a8836,76543210 -#r r,a8836,76543211 -#r I,0 -#r r,a8830,eeff4455 - - .lcomm dummy,4 - - .include "testutils.inc" - start - .if ..asm.arch.cris.v32 - move irqvec1,$ebp - .else - move irqvec1,$ibr - .endif - test_h_mem 0xabcdef01 0xd0000032 - nop - nop - test_h_mem 0x76543210 0xd0000036 - ei - test_h_mem 0,dummy -wouldreturnhere: - nop -killme: - fail - -returnhere: - test_h_mem 0x76543211 0xd0000036 - test_h_mem 0xeeff4455 0xd0000030 - pass - -irq0x33: - .if ..asm.arch.cris.v32 - test_h_dr wouldreturnhere,$erp - move returnhere,$erp - rete - rfe - .else - move $dccr,$r0 - test_h_dr wouldreturnhere,$irp - move returnhere,$irp - reti - move $r0,$dccr - .endif - - singlevec irqvec1,0x33,irq0x33 diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/irq2.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/irq2.ms deleted file mode 100644 index 19709e4..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/irq2.ms +++ /dev/null @@ -1,44 +0,0 @@ -#mach: crisv10 crisv32 -#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/rv/intmultiple 0xaa" -#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/rv/intmultiple 0xaa" -#output: /rv: WD\n -#output: /rv: REG R 0xd0000032\n -#output: /rv: := 0xabcdef01\n -#output: /rv: IRQ 0xaa\n -#output: /rv: REG R 0xd0000036\n -#output: /rv: := 0x76543210\n -#output: /rv: REG R 0xd0000030\n -#output: /rv: IRQ 0x0\n -#output: /rv: := 0xeeff4455\n -#output: pass\n - -# Primarily to test multiple-int-bits set in dv-rv.c. - -#r W, -#r r,a8832,abcdef01 -#r I,6 -#r r,a8836,76543210 -#r I,0 -#r r,a8830,eeff4455 - - .lcomm dummy,4 - - .include "testutils.inc" - start - test_h_mem 0xabcdef01 0xd0000032 - .if ..asm.arch.cris.v32 - move irqvec1,$ebp - .else - move irqvec1,$ibr - .endif - ei - test_h_mem 0,dummy -killme: - fail - -irq0xea: - test_h_mem 0x76543210 0xd0000036 - test_h_mem 0xeeff4455 0xd0000030 - pass - - singlevec irqvec1,0xea,irq0xea diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/irq3.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/irq3.ms deleted file mode 100644 index d96b6f5..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/irq3.ms +++ /dev/null @@ -1,46 +0,0 @@ -#mach: crisv10 crisv32 -#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/rv/intmultiple 0xaa" -#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/rv/intmultiple 0xaa" -#output: /rv: WD\n -#output: /rv: REG R 0xd0000032\n -#output: /rv: := 0xabcdef01\n -#output: /rv: IRQ 0xaa\n -#output: /rv: IRQ 0xaa\n -#output: /rv: REG R 0xd0000036\n -#output: /rv: := 0x76543210\n -#output: /rv: REG R 0xd0000030\n -#output: /rv: IRQ 0x0\n -#output: /rv: := 0xeeff4455\n -#output: pass\n - -# Much like irq2.ms, but modified to check same-int-port-value-twice. - -#r W, -#r r,a8832,abcdef01 -#r I,6 -#r I,6 -#r r,a8836,76543210 -#r I,0 -#r r,a8830,eeff4455 - - .lcomm dummy,4 - - .include "testutils.inc" - start - test_h_mem 0xabcdef01 0xd0000032 - .if ..asm.arch.cris.v32 - move irqvec1,$ebp - .else - move irqvec1,$ibr - .endif - ei - test_h_mem 0,dummy -killme: - fail - -irq0xea: - test_h_mem 0x76543210 0xd0000036 - test_h_mem 0xeeff4455 0xd0000030 - pass - - singlevec irqvec1,0xea,irq0xea diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/irq4.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/irq4.ms deleted file mode 100644 index 9e16b5c..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/irq4.ms +++ /dev/null @@ -1,46 +0,0 @@ -#mach: crisv10 crisv32 -#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int ignore_previous" -#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int ignore_previous" -#output: /rv: WD\n -#output: /rv: REG R 0xd0000032\n -#output: /rv: := 0xabcdef01\n -#output: /rv: IRQ 0x4\n -#output: /rv: IRQ 0x8\n -#output: /rv: REG R 0xd0000036\n -#output: /rv: := 0x76543210\n -#output: /rv: REG R 0xd0000030\n -#output: /rv: IRQ 0x0\n -#output: /rv: := 0xeeff4455\n -#output: pass\n - -# Much like irq3.ms, but modified to test multiple-int ignore_previous. - -#r W, -#r r,a8832,abcdef01 -#r I,4 -#r I,8 -#r r,a8836,76543210 -#r I,0 -#r r,a8830,eeff4455 - - .lcomm dummy,4 - - .include "testutils.inc" - start - test_h_mem 0xabcdef01 0xd0000032 - .if ..asm.arch.cris.v32 - move irqvec1,$ebp - .else - move irqvec1,$ibr - .endif - ei - test_h_mem 0,dummy -killme: - fail - -irq0x34: - test_h_mem 0x76543210 0xd0000036 - test_h_mem 0xeeff4455 0xd0000030 - pass - - singlevec irqvec1,0x34,irq0x34 diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/irq5.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/irq5.ms deleted file mode 100644 index 4ecc5a6..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/irq5.ms +++ /dev/null @@ -1,46 +0,0 @@ -#mach: crisv10 crisv32 -#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int 0xae" -#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int 0xae" -#output: /rv: WD\n -#output: /rv: REG R 0xd0000032\n -#output: /rv: := 0xabcdef01\n -#output: /rv: IRQ 0x4\n -#output: /rv: IRQ 0x8\n -#output: /rv: REG R 0xd0000036\n -#output: /rv: := 0x76543210\n -#output: /rv: REG R 0xd0000030\n -#output: /rv: IRQ 0x0\n -#output: /rv: := 0xeeff4455\n -#output: pass\n - -# Much like irq4.ms, but modified to test vector case for multiple-int. - -#r W, -#r r,a8832,abcdef01 -#r I,4 -#r I,8 -#r r,a8836,76543210 -#r I,0 -#r r,a8830,eeff4455 - - .lcomm dummy,4 - - .include "testutils.inc" - start - test_h_mem 0xabcdef01 0xd0000032 - .if ..asm.arch.cris.v32 - move irqvec1,$ebp - .else - move irqvec1,$ibr - .endif - ei - test_h_mem 0,dummy -killme: - fail - -irq0xae: - test_h_mem 0x76543210 0xd0000036 - test_h_mem 0xeeff4455 0xd0000030 - pass - - singlevec irqvec1,0xae,irq0xae diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/irq6.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/irq6.ms deleted file mode 100644 index 9e40f4a..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/irq6.ms +++ /dev/null @@ -1,99 +0,0 @@ -#mach: crisv10 crisv32 -#sim(crisv10): --hw-device "/rv/trace? true" -#sim(crisv32): --hw-device "/rv/trace? true" -#output: /rv: WD\n -#output: /rv: REG R 0xd0000032\n -#output: /rv: := 0xabcdef01\n -#output: /rv: IRQ 0x4\n -#output: /rv: REG R 0xd0000036\n -#output: /rv: := 0x76543210\n -#output: /rv: REG R 0xd0000030\n -#output: /rv: IRQ 0x0\n -#output: /rv: IRQ 0x8\n -#output: /rv: := 0xeeff4455\n -#output: /rv: REG R 0xd0000034\n -#output: /rv: := 0xdd001122\n -#output: /rv: REG R 0xd0000038\n -#output: /rv: := 0xaaeeff44\n -#output: /rv: REG R 0xd000003c\n -#output: /rv: := 0xff445511\n -#output: pass\n - -# Test two successive ints; that flags are disabled when an interrupt -# is taken, and then automatically (or by register restore) enabled at -# return. - -#r W, -#r r,a8832,abcdef01 -#r I,4 -#r r,a8836,76543210 -#r I,0 -#r I,8 -#r r,a8830,eeff4455 -#r r,a8834,dd001122 -#r r,a8838,aaeeff44 -#r r,a883c,ff445511 - - .lcomm dummy,4 - - .include "testutils.inc" - start - test_h_mem 0xabcdef01 0xd0000032 - moveq -1,$r4 - - .if ..asm.arch.cris.v32 - move irqvec1,$ebp - .else - move irqvec1,$ibr - .endif - - ei - test_h_mem 0,dummy - - ; Here after the first interrupt, or perhaps the second interrupt is - ; taken directly; leave it optional. Anyway, the second interrupt - ; should be taken no later than this branch. - test_h_mem 0,dummy - -killme: - fail - -irq0x33: - .if ..asm.arch.cris.v32 - ; Nothing needed to save flags - "shift" should happen, and back at rfe. - .else - ; The missing sim support for interrupt-excluding instructions is matched - ; by the flaw that sim doesn't service interrupts in straight code. - ; So, we can use a sequence that would work on actual hardware. - move $dccr,$r5 - di - .endif - - test_h_mem 0x76543210 0xd0000036 - test_h_mem 0xeeff4455 0xd0000030 - test_h_mem 0xdd001122 0xd0000034 - moveq -22,$r4 - - .if ..asm.arch.cris.v32 - move irqvec2,$ebp - rete - rfe - .else - move irqvec2,$ibr - reti - move $r5,$dccr - .endif - - pass - -irq0x34: - test_h_mem 0xaaeeff44 0xd0000038 - test_h_mem 0xff445511 0xd000003c - cmpq -22,$r4 - bne killme - nop - pass - - singlevec irqvec1,0x33,irq0x33 - - singlevec irqvec2,0x34,irq0x34 diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/mbox1.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/mbox1.ms deleted file mode 100644 index ee0f54c..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/mbox1.ms +++ /dev/null @@ -1,88 +0,0 @@ -#mach: crisv10 crisv32 -#sim(crisv10): --hw-device "/rv/trace? true" -#sim(crisv32): --hw-device "/rv/trace? true" -#output: /rv: WD\n -#output: /rv: MBOX H 0x1001d..0x10037\n -#output: /rv: 0x10020: 12 23 34 56 79 8a bd de\n -#output: /rv: 0x10028: fb ad ba db ad 56 78 9a\n -#output: /rv: 0x10030: fd e1 23 45 66 54 32 1a\n -#output: /rv: -> 0x1001d..0x10027\n -#output: /rv: 0x10020: aa 55 77 88 32 10 ee cc\n -#output: /rv: MBOX P 0xfffd..0x1001f\n -#output: /rv: 0x10000: aa 55 12 23 34 56 79 8a\n -#output: /rv: 0x10008: bd de fb ad ba db ad 56\n -#output: /rv: 0x10010: 78 9a fd e1 23 45 66 54\n -#output: /rv: 0x10018: 32 1a ac cb be ed db ed\n -#output: /rv: -> 0xfffd..0x10017\n -#output: /rv: 0x10000: 11 22 56 78 ee dd 12 ab\n -#output: /rv: 0x10008: 55 aa ee 00 42 12 27 98\n -#output: /rv: 0x10010: 88 55 22 33 66 77 22 45\n -#output: /rv: REG R 0xd0000038\n -#output: /rv: := 0x76543211\n -#output: pass\n - -# Trivial test of mailbox commands. - -#r W, -#r i,1b000512233456798abddefbadbadbad56789afde123456654321a -#r o,0b0005aa5577883210eecc -#r i,230006aa5512233456798abddefbadbadbad56789afde123456654321aaccbbeeddbed -#r o,1b000511225678eedd12ab55aaee00421227988855223366772245 -#r r,a8838,76543211 - - .include "testutils.inc" - start - move.w 0x1b,$r0 - move.d 0x1001d,$r1 - move.w $r0,[$r1+] - moveq 5,$r0 - move.b $r0,[$r1] - mvi_h_mem 0x56342312 0x10020 - mvi_h_mem 0xdebd8a79 0x10024 - mvi_h_mem 0xdbbaadfb 0x10028 - mvi_h_mem 0x9a7856ad 0x1002c - mvi_h_mem 0x4523e1fd 0x10030 - mvi_h_mem 0x1a325466 0x10034 - - mvi_h_mem 0x1001d 0xc000f000 - - move.d 0x1001d,$r0 - movu.w [$r0+],$r1 - test_h_gr 0xb $r1 - movu.b [$r0],$r1 - test_h_gr 0x5 $r1 - test_h_mem 0x887755aa 0x10020 - test_h_mem 0xccee1032 0x10024 - - move.w 0x23,$r0 - move.d 0xfffd,$r1 - move.w $r0,[$r1+] - moveq 6,$r0 - move.b $r0,[$r1] - mvi_h_mem 0x231255aa 0x10000 - mvi_h_mem 0x8a795634 0x10004 - mvi_h_mem 0xadfbdebd 0x10008 - mvi_h_mem 0x56addbba 0x1000c - mvi_h_mem 0xe1fd9a78 0x10010 - mvi_h_mem 0x54664523 0x10014 - mvi_h_mem 0xcbac1a32 0x10018 - mvi_h_mem 0xeddbedbe 0x1001c - - mvi_h_mem 0xfffd 0xc000f000 - - move.d 0xfffd,$r0 - movu.w [$r0+],$r1 - test_h_gr 0x1b $r1 - movu.b [$r0],$r1 - test_h_gr 0x6 $r1 - test_h_mem 0x78562211 0x10000 - test_h_mem 0xab12ddee 0x10004 - test_h_mem 0x00eeaa55 0x10008 - test_h_mem 0x98271242 0x1000c - test_h_mem 0x33225588 0x10010 - test_h_mem 0x45227766 0x10014 - - test_h_mem 0x76543211 0xd0000038 - pass - - .fill 65536*2+128,1,0 diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/mem1.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/mem1.ms deleted file mode 100644 index ee5c4f5..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/mem1.ms +++ /dev/null @@ -1,100 +0,0 @@ -#mach: crisv10 crisv32 -#sim(crisv10): --hw-device "/rv/trace? true" -#sim(crisv32): --hw-device "/rv/trace? true" -#output: /rv: WD\n -#output: /rv: REG R 0xd0000036\n -#output: /rv: := 0x76543210\n -#output: /rv: DMA W 0x20020..0x2003f\n -#output: /rv: 0x20020: 12 23 34 56\n -#output: /rv: 0x20024: 79 8a bd de\n -#output: /rv: 0x20028: fb ad ba db\n -#output: /rv: 0x2002c: ad 56 78 9a\n -#output: /rv: 0x20030: fd e1 23 45\n -#output: /rv: 0x20034: 66 54 32 1a\n -#output: /rv: 0x20038: ac cb be ed\n -#output: /rv: 0x2003c: db ed aa da\n -#output: /rv: REG R 0xd0000038\n -#output: /rv: := 0x76543211\n -#output: /rv: DMA R 0x20000..0x2001f\n -#output: /rv: 0x20000: aa 55 12 23\n -#output: /rv: 0x20004: 34 56 79 8a\n -#output: /rv: 0x20008: bd de fb ad\n -#output: /rv: 0x2000c: ba db ad 56\n -#output: /rv: 0x20010: 78 9a fd e1\n -#output: /rv: 0x20014: 23 45 66 54\n -#output: /rv: 0x20018: 32 1a ac cb\n -#output: /rv: 0x2001c: be ed db ed\n -#output: /rv: IRQ 0x8\n -#output: /rv: REG R 0xd0000038\n -#output: /rv: := 0x76543212\n -#output: pass\n - -# Trivial test of DMA. - -# Locations of IRQ notifiers above depend on when the simulator is -# polled; adjustments may be needed (after checking that no poll is -# gone due to a bug!) - -#r W, -#r r,a8836,76543210 -#r s,e020,12233456798abddefbadbadbad56789afde123456654321aaccbbeeddbedaada -#r r,a8838,76543211 -#r l,e000,aa5512233456798abddefbadbadbad56789afde123456654321aaccbbeeddbed -#r I,8 -#r r,a8838,76543212 - - .include "testutils.inc" - start - test_h_mem 0x76543210 0xd0000036 - - move.d 0x2003f,$r1 - move.d 0x10000,$r3 -0: - test.b [$r1] - bne 1f - subq 1,$r3 - bne 0b - nop - -1: - test_h_mem 0x56342312 0x20020 - test_h_mem 0xdebd8a79 0x20024 - test_h_mem 0xdbbaadfb 0x20028 - test_h_mem 0x9a7856ad 0x2002c - test_h_mem 0x4523e1fd 0x20030 - test_h_mem 0x1a325466 0x20034 - test_h_mem 0xedbecbac 0x20038 - test_h_mem 0xdaaaeddb 0x2003c - - move.d 0x20020,$r0 - move.d 0x20000,$r1 - move.w 0x55aa,$r2 - move.w $r2,[r1+] - .rept 8 - move.d [$r0+],$r2 - move.d $r2,[$r1+] - .endr - - test_h_mem 0x76543211 0xd0000038 - - .if ..asm.arch.cris.v32 - move irqvec1,$ebp - .else - move irqvec1,$ibr - .endif - ei - move.d 0x100000,$r9 -0: - subq 1,$r9 - bne 0b - nop -killme: - fail - -irq0x34: - test_h_mem 0x76543212 0xd0000038 - pass - - .fill 65536*2+128,1,0 - - singlevec irqvec1,0x34,irq0x34 diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/mem2.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/mem2.ms deleted file mode 100644 index b676249..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/mem2.ms +++ /dev/null @@ -1,104 +0,0 @@ -#mach: crisv10 crisv32 -#sim(crisv10): --hw-device "/rv/trace? true" -#sim(crisv32): --hw-device "/rv/trace? true" -#output: /rv: WD\n -#output: /rv: REG R 0xd0000036\n -#output: /rv: := 0x76543210\n -#output: /rv: DMA W 0x20020..0x20043\n -#output: /rv: 0x20020: 12 23 34 56\n -#output: /rv: 0x20024: 79 8a bd de\n -#output: /rv: 0x20028: fb ad ba db\n -#output: /rv: 0x2002c: ad 56 78 9a\n -#output: /rv: 0x20030: fd e1 23 45\n -#output: /rv: 0x20034: 66 54 32 1a\n -#output: /rv: 0x20038: ac cb be ed\n -#output: /rv: 0x2003c: db ed aa da\n -#output: /rv: 0x20040: 00 aa bb cc\n -#output: /rv: REG R 0xd0000038\n -#output: /rv: := 0x76543211\n -#output: /rv: DMA R 0x20000..0x20023\n -#output: /rv: 0x20000: aa 55 12 23\n -#output: /rv: 0x20004: 34 56 79 8a\n -#output: /rv: 0x20008: bd de fb ad\n -#output: /rv: 0x2000c: ba db ad 56\n -#output: /rv: 0x20010: 78 9a fd e1\n -#output: /rv: 0x20014: 23 45 66 54\n -#output: /rv: 0x20018: 32 1a ac cb\n -#output: /rv: 0x2001c: be ed db ed\n -#output: /rv: 0x20020: aa da 00 aa\n -#output: /rv: IRQ 0x8\n -#output: /rv: REG R 0xd0000038\n -#output: /rv: := 0x76543212\n -#output: pass\n - -# This is a slight variation of mem1.ms just to trig the "buffer needs -# to be malloced for large request size" for the DMA request. - -# Locations of IRQ notifiers above depend on when the simulator is -# polled; adjustments may be needed (after checking that no poll is -# gone due to a bug!) - -#r W, -#r r,a8836,76543210 -#r s,e020,12233456798abddefbadbadbad56789afde123456654321aaccbbeeddbedaada00aabbcc -#r r,a8838,76543211 -#r l,e000,aa5512233456798abddefbadbadbad56789afde123456654321aaccbbeeddbedaada00aa -#r I,8 -#r r,a8838,76543212 - - .include "testutils.inc" - start - test_h_mem 0x76543210 0xd0000036 - - move.d 0x2003f,$r1 - move.d 0x10000,$r3 -0: - test.b [$r1] - bne 1f - subq 1,$r3 - bne 0b - nop - -1: - test_h_mem 0x56342312 0x20020 - test_h_mem 0xdebd8a79 0x20024 - test_h_mem 0xdbbaadfb 0x20028 - test_h_mem 0x9a7856ad 0x2002c - test_h_mem 0x4523e1fd 0x20030 - test_h_mem 0x1a325466 0x20034 - test_h_mem 0xedbecbac 0x20038 - test_h_mem 0xdaaaeddb 0x2003c - test_h_mem 0xccbbaa00 0x20040 - - move.d 0x20020,$r0 - move.d 0x20000,$r1 - move.w 0x55aa,$r2 - move.w $r2,[r1+] - .rept 9 - move.d [$r0+],$r2 - move.d $r2,[$r1+] - .endr - - test_h_mem 0x76543211 0xd0000038 - - .if ..asm.arch.cris.v32 - move irqvec1,$ebp - .else - move irqvec1,$ibr - .endif - ei - move.d 0x100000,$r9 -0: - subq 1,$r9 - bne 0b - nop -killme: - fail - -irq0x34: - test_h_mem 0x76543212 0xd0000038 - pass - - .fill 65536*2+128,1,0 - - singlevec irqvec1,0x34,irq0x34 diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/poll1.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/poll1.ms deleted file mode 100644 index baf1ed9..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/poll1.ms +++ /dev/null @@ -1,22 +0,0 @@ -#mach: crisv32 -#sim(crisv32): --hw-device "/rv/dummy 0x12" - -# A variant of trivial2.ms to check that the right thing happens when -# we reach the poll function with a dummy device. - - .include "testutils.inc" - start - move.d 0xd0000000,$r0 - move.d [$r0+],$r3 - cmp.d 0x12121212,$r3 - beq ok - nop -bad: - fail -ok: - move.d 0x10000,$r10 -0: - bne 0b - subq 1,$r10 - - pass diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/quit.s b/sim/testsuite/sim/cris/hw/rv-n-cris/quit.s deleted file mode 100644 index 8c1d239..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/quit.s +++ /dev/null @@ -1,4 +0,0 @@ -; Trivial target simulator program that just exits. - .include "testutils.inc" - startnostack - quit diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp b/sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp deleted file mode 100644 index 0f9ecec..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp +++ /dev/null @@ -1,249 +0,0 @@ -# Copyright (C) 2006-2021 Free Software Foundation, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -# Miscellaneous CRIS simulator testcases in assembly code, testing -# dv-rv.c and dv-cris.c functions. - -# Check whether dv-rv and dv-cris are present. - -proc sim_has_rv_and_cris {} { - global srcdir - global subdir - global SIMFLAGS - global global_as_options - global global_ld_options - global global_sim_options - - # We need to assemble and link a trivial program and pass that, in - # order to test successful exit. - - # A bit of duplication here for the assembling and linking part; - # what we want to do it to run the simulator without affecting the - # PASS/FAIL counters, and we can use e.g. run_sim_test for that. - - if ![info exists global_as_options] { - set global_as_options "" - } - if ![info exists global_ld_options] { - set global_ld_options "" - } - if ![info exists global_sim_options] { - set global_sim_options "" - } - - set comp_output [target_assemble $srcdir/$subdir/quit.s quit.o \ - "-I$srcdir/$subdir $global_as_options"] - - if ![string match "" $comp_output] { - verbose -log "$comp_output" 3 - fail "rv sim test setup (assembling)" - return 0 - } - - set comp_output [target_link quit.o quit.x "$global_ld_options"] - - if ![string match "" $comp_output] { - verbose -log "$comp_output" 3 - fail "rv sim test setup (linking)" - return 0 - } - - set result \ - [sim_run quit.x \ - "$global_sim_options --hw-device rv --hw-device cris --hw-info" \ - "" "" ""] - set return_code [lindex $result 0] - set output [lindex $result 1] - - if { $return_code == 0 } { - return 1 - } - - return 0 -} - -# Similar to slurp_options, but lines are fixed format "^#r ..." (not -# "^#{ws}*r:{ws}+" to avoid intruding on slurp_options syntax). Only -# trailing whitespace of the "..." is trimmed. Beware that lines -# including parameters may not contain ":". - -proc slurp_rv { file } { - if [catch { set f [open $file r] } x] { - #perror "couldn't open `$file': $x" - perror "$x" - return -1 - } - set rv_array {} - # whitespace expression - set ws {[ ]*} - # whitespace is ignored at the end of a line. - set pat "^#r (.*)$ws\$" - # Allow arbitrary lines until the first option is seen. - set seen_opt 0 - while { [gets $f line] != -1 } { - set line [string trim $line] - # Whitespace here is space-tab. - if [regexp $pat $line xxx cmd] { - # match! - lappend rv_array $cmd - set seen_opt 1 - } else { - if { $seen_opt } { - break - } - } - } - close $f - return $rv_array -} - -# The main test loop. - -if [istarget cris*-*-*] { - global ASFLAGS_FOR_TARGET - set has_rv_and_cris [sim_has_rv_and_cris] - global global_as_options - global global_ld_options - global global_sim_options - - set saved_global_sim_options $global_sim_options - set saved_global_ld_options $global_ld_options - - # See the logic in sim-defs.exp for more details. - set sim [board_info target sim] - if [string equal "" $sim] { - global objdir - global arch - set rvdummy "$objdir/../$arch/rvdummy" - } else { - set rvdummy "[file dirname [board_info target sim]]/rvdummy" - } - - # All machines we test and the corresponding assembler option. - # We'll only ever test v10 and higher here. - - set combos {{"crisv10" "--march=v10 --no-mul-bug-abort"} - {"crisv32" "--march=v32"}} - - # We need to pass different assembler flags for each machine. - # Specifying it here rather than adding a specifier to each and every - # test-file is preferrable. - - foreach combo $combos { - set mach [lindex $combo 0] - set ASFLAGS_FOR_TARGET "[lindex $combo 1]" - - # The .ms suffix is for "miscellaneous .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { - - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - # Whoever runs the test should be alerted that not all - # testcases have been checked; that's why we do the loop - # and don't just return at the top. - if !$has_rv_and_cris { - untested $src - continue - } - - set sim_defaults "--hw-file $srcdir/$subdir/std.dev" - set ld_defaults "--section-start=.text=0" - - # We parse options an extra time besides in run_sim_test, - # to determine if our defaults should be overridden. - - set opt_array [slurp_options $src] - foreach i $opt_array { - set opt_name [lindex $i 0] - set opt_machs [lindex $i 1] - set opt_val [lindex $i 2] - - # Allow concatenating to the default options by - # specifying a mach. - if { $opt_name == "sim" && $opt_machs == "" } { - set sim_defaults "" - } - - if { $opt_name == "ld" && $opt_machs == "" } { - set ld_defaults "" - } - } - - set rvdummy_id -1 - set hostcmds [slurp_rv $src] - - if { $hostcmds != "" } { - # I guess we could ask to have rvdummy executed on a - # remote host, but it looks like too much trouble for - # a feature rarely used. - if [is_remote host] { - untested $src - continue - } - - set src_components [file split $src] - set rvfile "[lindex $src_components \ - [expr [llength $src_components] - 1]].r" - - if [catch { set f [open $rvfile w] } x] { - error "$x" - } { - set contents [join $hostcmds "\n"] - - # Make it possible to use files from the test - # source directory; expected with the @-command. - regsub -all "@srcdir@" $contents "$srcdir/$subdir" contents - - verbose "rv: $contents" 2 - puts $f $contents - close $f - } - - spawn -noecho $rvdummy "$rvfile" - if { $spawn_id < 0 } { - error "Couldn't spawn $rvdummy" - continue - } - set rvdummy_id $spawn_id - } - - # Unfortunately this seems like the only way to pass - # additional sim, ld etc. options to run_sim_test. - set global_sim_options "$saved_global_sim_options $sim_defaults" - set global_ld_options "$saved_global_ld_options $ld_defaults" - run_sim_test $src $mach - set global_sim_options $saved_global_sim_options - set global_ld_options $saved_global_ld_options - - # Stop the rvdummy, if it's still running. We need to - # wait on it anyway to avoid it turning into a zombie. - if { $rvdummy_id != -1 } { - close -i $rvdummy_id - wait -i $rvdummy_id - - # Gleaned from framework.exp, this seems an indicator - # to whether the test had expected outcome. If so, we - # want to remove the rv-file. - if { $exit_status == 0 } { - file delete $rvfile - } - } - } - } -} diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/std.dev b/sim/testsuite/sim/cris/hw/rv-n-cris/std.dev deleted file mode 100644 index 9fefcbb..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/std.dev +++ /dev/null @@ -1,8 +0,0 @@ -/rv/reg 0xd0000000 64 -/rv/remote-reg 0xa8800 -/rv/intnum 4 2 -/cris/vec-for-int 4 0x33 8 0x34 0xaa 0xea -/rv/mem 0x20000 0x400 -/rv/remote-mem 0xe000 -/rv/mbox 0xc000f000 -/rv > int int /cris diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/testutils.inc b/sim/testsuite/sim/cris/hw/rv-n-cris/testutils.inc deleted file mode 100644 index e707abf..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/testutils.inc +++ /dev/null @@ -1,22 +0,0 @@ - .include "../../asm/testutils.inc" - -# Define an exception vector table "vecname" with a single -# vector number "n" as "entry", all others "other". -# V32 only needs 1<<10 alignment, earlier versions need 1<<16. - .macro singlevec vecname vecno entry other=killme - .section .text.exvec - .p2align 16 -\vecname: - .if (\vecno) - .rept \vecno - .dword \other - .endr - .endif - .dword \entry - .if (\vecno)-255 - .rept 256-(\vecno)-1 - .dword \other - .endr - .endif - .previous - .endm diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/trivial1.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/trivial1.ms deleted file mode 100644 index a219b04..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/trivial1.ms +++ /dev/null @@ -1,17 +0,0 @@ -#mach: crisv32 -#sim(crisv32): --hw-info -#output: /\n -#output: /rv\n -#output: /rv/reg 0xd0000000 0x40\n -#output: /rv/remote-reg 0xa8800\n -#output: /rv/intnum 0x4 0x2\n -#output: /rv/mem 0x20000 0x400\n -#output: /rv/remote-mem 0xe000\n -#output: /rv/mbox 0xc000f000\n -#output: /rv > int int /cris\n -#output: /cris\n -#output: /cris/vec-for-int 0x4 0x33 0x8 0x34 0xaa 0xea\n - -# Test expected --hw-info output and startup paths of components. - - .include "quit.s" diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/trivial2.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/trivial2.ms deleted file mode 100644 index b633445..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/trivial2.ms +++ /dev/null @@ -1,21 +0,0 @@ -#mach: crisv32 -#sim(crisv32): --hw-device "/rv/dummy 0x12" - -# Test dummy settings: set from value. - - .include "testutils.inc" - start - move.d 0xd0000000,$r0 - move.d [$r0+],$r3 - cmp.d 0x12121212,$r3 - beq ok - nop -bad: - fail -ok: - moveq -1,$r3 - move.d $r3,[$r0] - cmp.d [$r0],$r3 - bne bad - nop - pass diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/trivial3.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/trivial3.ms deleted file mode 100644 index 1f23b49..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/trivial3.ms +++ /dev/null @@ -1,20 +0,0 @@ -#mach: crisv32 -#sim(crisv32): --hw-device "/rv/dummy /dev/zero" - -# Test dummy settings: set from file. - - .include "testutils.inc" - start - move.d 0xd0000000,$r0 - move.d [$r0+],$r3 - beq ok - nop -bad: - fail -ok: - moveq -1,$r3 - move.d $r3,[$r0] - cmp.d [$r0],$r3 - bne bad - nop - pass diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/trivial4.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/trivial4.ms deleted file mode 100644 index 6108160..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/trivial4.ms +++ /dev/null @@ -1,22 +0,0 @@ -#mach: crisv32 -#r @,@srcdir@/trivial4.r - -# Test read and writes. - - .include "testutils.inc" - start - move.d 0xd0000032,$r0 - move.d [$r0+],$r3 - cmp.d 0xabcdef01,$r3 - beq ok - nop -bad: - fail -ok: - move.d 0xaabbccdd,$r3 - move.d $r3,[$r0] - move.d [$r0],$r3 - cmp.d 0x76543210,$r3 - bne bad - nop - pass diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/trivial4.r b/sim/testsuite/sim/cris/hw/rv-n-cris/trivial4.r deleted file mode 100644 index b4896a0..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/trivial4.r +++ /dev/null @@ -1,4 +0,0 @@ -W, -r,a8832,abcdef01 -w,a8836,aabbccdd -r,a8836,76543210 diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/trivial5.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/trivial5.ms deleted file mode 100644 index 849f17e..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/trivial5.ms +++ /dev/null @@ -1,16 +0,0 @@ -#mach: crisv10 crisv32 -#sim(crisv10): --hw-device "/rv/trace? true" -#sim(crisv32): --hw-device "/rv/trace? true" -#output: /rv: WD\n -#output: /rv: REG R 0xd0000032\n -#output: /rv: := 0xabcdef01\n -#output: /rv: REG W 0xd0000036 := 0xaabbccdd\n -#output: /rv: REG R 0xd0000036\n -#output: /rv: := 0x76543210\n -#output: pass\n - -# Test trace output for read and write. - -#r @,@srcdir@/trivial4.r - - .include "trivial4.ms" diff --git a/sim/testsuite/sim/cris/hw/rv-n-cris/wd1.ms b/sim/testsuite/sim/cris/hw/rv-n-cris/wd1.ms deleted file mode 100644 index 91af7fc..0000000 --- a/sim/testsuite/sim/cris/hw/rv-n-cris/wd1.ms +++ /dev/null @@ -1,33 +0,0 @@ -#mach: crisv10 crisv32 -#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/rv/watchdog-interval 1" -#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/rv/watchdog-interval 1" --hw-device "/rv/max-poll-ticks 1000" -#output: /rv: WD\n -#output: /rv: REG R 0xd0000036\n -#output: /rv: := 0x76543210\n -#output: /rv: WD\n -#output: /rv: DMA W 0x20000..0x20003\n -#output: /rv: 0x20000: 01 02 03 04\n -#output: /rv: REG R 0xd0000038\n -#output: /rv: := 0x76543211\n -#output: pass\n - -#r W, -#r r,a8836,76543210 -#r W, -#r s,e000,01020304 -#r r,a8838,76543211 - - .include "testutils.inc" - start - mvi_h_mem 0 0x20000 - test_h_mem 0x76543210 0xd0000036 - - move.d 0x20000,$r1 -0: - test.b [$r1] - beq 0b - nop - test_h_mem 0x76543211 0xd0000038 - pass - - .fill 65536*2+128,1,0 diff --git a/sim/testsuite/sim/d10v/ChangeLog b/sim/testsuite/sim/d10v/ChangeLog deleted file mode 100644 index 5ca8910..0000000 --- a/sim/testsuite/sim/d10v/ChangeLog +++ /dev/null @@ -1,144 +0,0 @@ -2021-01-15 Mike Frysinger - - * allinsn.exp: New file. - * configure, configure.ac, loop.s, Makefile.in: Deleted. - -2020-10-06 Andrew Burgess - - * configure: Regnerate. - * configure.ac (AC_CONFIG_AUX_DIR): Update. - -2015-03-30 Mike Frysinger - - * Makefile.in (RUNFLAGS_FOR_TARGET): Set to --environment operating. - -2009-08-22 Ralf Wildenhues - - * configure: Regenerate. - -2005-01-07 Andrew Cagney - - * configure.ac: Rename configure.in, require autoconf 2.59. - * configure: Re-generate. - -Tue Apr 18 16:32:07 2000 Andrew Cagney - - * t-rie-xx.s (test_rie_xx): New test. - * Makefile.in (TESTS): Update. - -Tue Feb 22 17:36:34 2000 Andrew Cagney - - * Makefile.in: Force d10v into operating mode. - -Mon Jan 3 00:17:28 2000 Andrew Cagney - - * t-ae-ld-d.s, t-ae-ld-i.s, t-ae-ld-id.s, t-ae-ld-im.s , - t-ae-ld-ip.s, t-ae-ld2w-d.s, t-ae-ld2w-i.s, t-ae-ld2w-id.s , - t-ae-ld2w-im.s, t-ae-ld2w-ip.s, t-ae-st-d.s, t-ae-st-i.s , - t-ae-st-id.s, t-ae-st-im.s, t-ae-st-ip.s, t-ae-st-is.s , - t-ae-st2w-d.s, t-ae-st2w-i.s, t-ae-st2w-id.s, t-ae-st2w-im.s , - t-ae-st2w-ip.s, t-ae-st2w-is.s: New tests. Check that an address - exception occures when a word/two-word load/store is not word - aligned. - * Makefile.in (TESTS): Update. - -Fri Oct 29 18:36:34 1999 Andrew Cagney - - * t-mvtc.s: Check that the user can not modify the DM bit in the - BPSW or DPSW. - -Thu Oct 28 01:47:26 1999 Andrew Cagney - - * t-mvtc.s: Update. Check that user can not modify DM bit. - -Wed Sep 8 19:34:55 MDT 1999 Diego Novillo - - * t-ld-st.s: New file. - * t-sac.s: New file. - * t-sachi.s: New file. - * t-slae.s: New file. - -1999-01-13 Jason Molenda (jsm@bugshack.cygnus.com) - - * t-sadd.s: New file. - * Makefile.in (TESTS): Add t-sadd. - -Mon Feb 16 09:20:57 1998 Andrew Cagney - - * t-macros.i (VEC_*): Define. - (DMAP_REG, DMAP_BASE, DMAP_MASK): Define. - (IMAP[01]_REG): Define. - - * t-rdt.s (test_tdt): New file. - - * t-dbt.s (test_dbt): New file. - - * Makefile.in (TESTS): Add t-rdt and t-dbt. - - -Fri Feb 13 16:21:13 1998 Andrew Cagney - - * t-sp.s: New test. - * Makefile.in (TESTS): Update. - -Wed Feb 11 17:58:50 1998 Andrew Cagney - - * t-macros.i: Update trap calls, func in r4, args in - r0... - (start): Force r0 to zero. - - * t-sub2w.s: Ditto. - -Tue Dec 9 10:41:44 1997 Andrew Cagney - - * t-rte.s (success): New file. - * Makefile.in: Update. - - * t-rep.s: Check rep repeats correct number of times. - -Fri Dec 5 10:11:18 1997 Andrew Cagney - - * t-mvtc.s: Check for stuck-zero in MOD_E, MOD_S. - - * t-trap.s: New file. - * Makefile.in (TESTS): Update. - -Thu Dec 4 16:56:55 1997 Andrew Cagney - - * t-macros.i: Add definitions for PSW bits. - - * t-mvtc.s: New file. - * Makefile.in (TESTS): Update. - -Wed Dec 3 16:35:24 1997 Andrew Cagney - - * t-rac.s: New files. - - * t-macros.i: Add macros for checking psw and 2w quantities. - - * Makefile.in (TESTS): Update. - -Tue Dec 2 11:01:36 1997 Andrew Cagney - - * t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s, t-sub.s: New - files. - - * Makefile.in: Update. - -Mon Nov 17 20:14:48 1997 Andrew Cagney - - * t-subi.s (test_subi): New file. - * Makefile.in: Update. - -Fri Nov 14 14:06:06 1997 Andrew Cagney - - * t-rep.s: New file. Test case of branch to RPT_E address. - -Mon Nov 10 19:21:26 1997 Andrew Cagney - - * t-macros.i (_start): New file. - * t-rachi.s: New file. - - * Makefile.in (RUN_FOR_TARGET): Look for simulator in d10v - directory. - diff --git a/sim/testsuite/sim/d10v/allinsn.exp b/sim/testsuite/sim/d10v/allinsn.exp deleted file mode 100644 index 123509a..0000000 --- a/sim/testsuite/sim/d10v/allinsn.exp +++ /dev/null @@ -1,17 +0,0 @@ -# d10v simulator testsuite. - -if [istarget d10v*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "d10v" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/d10v/exit47.s b/sim/testsuite/sim/d10v/exit47.s deleted file mode 100644 index 8f2a6ee..0000000 --- a/sim/testsuite/sim/d10v/exit47.s +++ /dev/null @@ -1,8 +0,0 @@ -# mach: all -# status: 47 -# output: - -.include "t-macros.i" - - start - exit47 diff --git a/sim/testsuite/sim/d10v/hello.s b/sim/testsuite/sim/d10v/hello.s deleted file mode 100644 index 3e3557d..0000000 --- a/sim/testsuite/sim/d10v/hello.s +++ /dev/null @@ -1,8 +0,0 @@ -# mach: all -# output: Hello World!\n - - .include "t-macros.i" - - start - hello - exit0 diff --git a/sim/testsuite/sim/d10v/t-ae-ld-d.s b/sim/testsuite/sim/d10v/t-ae-ld-d.s deleted file mode 100644 index 511fbb0..0000000 --- a/sim/testsuite/sim/d10v/t-ae-ld-d.s +++ /dev/null @@ -1,17 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld - - ld r8,@0x4000 -test_ld: - ld r8,@0x4001 - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld-i.s b/sim/testsuite/sim/d10v/t-ae-ld-i.s deleted file mode 100644 index b9d10d1..0000000 --- a/sim/testsuite/sim/d10v/t-ae-ld-i.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld - - ldi r10, #0x4000 - ld r8, @r10 - - ldi r10, #0x4001 -test_ld: - ld r8,@r10 - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld-id.s b/sim/testsuite/sim/d10v/t-ae-ld-id.s deleted file mode 100644 index ed86525..0000000 --- a/sim/testsuite/sim/d10v/t-ae-ld-id.s +++ /dev/null @@ -1,19 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld - - ldi r10, #0x4001 - ld r8, @(1,r10) - -test_ld: - ld r8,@(2,r10) - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld-im.s b/sim/testsuite/sim/d10v/t-ae-ld-im.s deleted file mode 100644 index 42f8716..0000000 --- a/sim/testsuite/sim/d10v/t-ae-ld-im.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld - - ldi r10, #0x4000 - ld r8, @r10- - - ldi r10, #0x4001 -test_ld: - ld r8,@r10- - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld-ip.s b/sim/testsuite/sim/d10v/t-ae-ld-ip.s deleted file mode 100644 index c163912..0000000 --- a/sim/testsuite/sim/d10v/t-ae-ld-ip.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld - - ldi r10, #0x4000 - ld r8, @r10+ - - ldi r10, #0x4001 -test_ld: - ld r8,@r10+ - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld2w-d.s b/sim/testsuite/sim/d10v/t-ae-ld2w-d.s deleted file mode 100644 index 1c81594..0000000 --- a/sim/testsuite/sim/d10v/t-ae-ld2w-d.s +++ /dev/null @@ -1,17 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w - - ld2w r8,@0x4000 -test_ld2w: - ld2w r8,@0x4001 - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld2w-i.s b/sim/testsuite/sim/d10v/t-ae-ld2w-i.s deleted file mode 100644 index 9547870..0000000 --- a/sim/testsuite/sim/d10v/t-ae-ld2w-i.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w - - ldi r10, #0x4000 - ld2w r8, @r10 - - ldi r10, #0x4001 -test_ld2w: - ld2w r8,@r10 - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld2w-id.s b/sim/testsuite/sim/d10v/t-ae-ld2w-id.s deleted file mode 100644 index 2766388..0000000 --- a/sim/testsuite/sim/d10v/t-ae-ld2w-id.s +++ /dev/null @@ -1,18 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w - - ldi r10, #0x4001 - ld2w r8,@(1,r10) -test_ld2w: - ld2w r8,@(2,r10) - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld2w-im.s b/sim/testsuite/sim/d10v/t-ae-ld2w-im.s deleted file mode 100644 index c6946f3..0000000 --- a/sim/testsuite/sim/d10v/t-ae-ld2w-im.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w - - ldi r10, #0x4000 - ld2w r8, @r10- - - ldi r10, #0x4001 -test_ld2w: - ld2w r8,@r10- - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld2w-ip.s b/sim/testsuite/sim/d10v/t-ae-ld2w-ip.s deleted file mode 100644 index 6214853..0000000 --- a/sim/testsuite/sim/d10v/t-ae-ld2w-ip.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w - - ldi r10, #0x4000 - ld2w r8, @r10+ - - ldi r10, #0x4001 -test_ld2w: - ld2w r8,@r10+ - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st-d.s b/sim/testsuite/sim/d10v/t-ae-st-d.s deleted file mode 100644 index 99bd724..0000000 --- a/sim/testsuite/sim/d10v/t-ae-st-d.s +++ /dev/null @@ -1,17 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st - - st r8,@0x4000 -test_st: - st r8,@0x4001 - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st-i.s b/sim/testsuite/sim/d10v/t-ae-st-i.s deleted file mode 100644 index 5f0f9b4..0000000 --- a/sim/testsuite/sim/d10v/t-ae-st-i.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st - - ldi r10,#0x4000 - st r8, @r10 - - ldi r10,#0x4001 -test_st: - st r8,@r10 - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st-id.s b/sim/testsuite/sim/d10v/t-ae-st-id.s deleted file mode 100644 index 9620fce..0000000 --- a/sim/testsuite/sim/d10v/t-ae-st-id.s +++ /dev/null @@ -1,18 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st - - ldi r10,#0x4001 - st r8, @(1,r10) -test_st: - st r8,@(2,r10) - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st-im.s b/sim/testsuite/sim/d10v/t-ae-st-im.s deleted file mode 100644 index 0318243..0000000 --- a/sim/testsuite/sim/d10v/t-ae-st-im.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st - - ldi r10,#0x4000 - st r8, @r10- - - ldi r10,#0x4001 -test_st: - st r8,@r10- - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st-ip.s b/sim/testsuite/sim/d10v/t-ae-st-ip.s deleted file mode 100644 index 78d9a1d..0000000 --- a/sim/testsuite/sim/d10v/t-ae-st-ip.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st - - ldi r10,#0x4000 - st r8, @r10+ - - ldi r10,#0x4001 -test_st: - st r8,@r10+ - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st-is.s b/sim/testsuite/sim/d10v/t-ae-st-is.s deleted file mode 100644 index 08e1d7e..0000000 --- a/sim/testsuite/sim/d10v/t-ae-st-is.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st - - ldi sp,#0x4000 - st r8, @-SP - - ldi sp,#0x4001 -test_st: - st r8,@-SP - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st2w-d.s b/sim/testsuite/sim/d10v/t-ae-st2w-d.s deleted file mode 100644 index 6f07a99..0000000 --- a/sim/testsuite/sim/d10v/t-ae-st2w-d.s +++ /dev/null @@ -1,17 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w - - st2w r8,@0x4000 -test_st2w: - st2w r8,@0x4001 - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st2w-i.s b/sim/testsuite/sim/d10v/t-ae-st2w-i.s deleted file mode 100644 index a629b75..0000000 --- a/sim/testsuite/sim/d10v/t-ae-st2w-i.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w - - ldi r10, #0x4000 - st2w r8, @r10 - - ldi r10, #0x4001 -test_st2w: - st2w r8,@r10 - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st2w-id.s b/sim/testsuite/sim/d10v/t-ae-st2w-id.s deleted file mode 100644 index 91f2319..0000000 --- a/sim/testsuite/sim/d10v/t-ae-st2w-id.s +++ /dev/null @@ -1,18 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w - - ldi r10, #0x4001 - st2w r8, @(1,r10) -test_st2w: - st2w r8,@(2,r10) - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st2w-im.s b/sim/testsuite/sim/d10v/t-ae-st2w-im.s deleted file mode 100644 index f8cc7fb..0000000 --- a/sim/testsuite/sim/d10v/t-ae-st2w-im.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w - - ldi r10, #0x4000 - st2w r8, @r10- - - ldi r10, #0x4001 -test_st2w: - st2w r8,@r10- - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st2w-ip.s b/sim/testsuite/sim/d10v/t-ae-st2w-ip.s deleted file mode 100644 index 63c5abd..0000000 --- a/sim/testsuite/sim/d10v/t-ae-st2w-ip.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w - - ldi r10, #0x4000 - st2w r8, @r10+ - - ldi r10, #0x4001 -test_st2w: - st2w r8,@r10+ - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st2w-is.s b/sim/testsuite/sim/d10v/t-ae-st2w-is.s deleted file mode 100644 index 190ab42..0000000 --- a/sim/testsuite/sim/d10v/t-ae-st2w-is.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w - - ldi sp, #0x4004 - st2w r8, @-SP - - ldi sp, #0x4005 -test_st2w: - st2w r8,@-SP - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-dbt.s b/sim/testsuite/sim/d10v/t-dbt.s deleted file mode 100644 index 9b405b0..0000000 --- a/sim/testsuite/sim/d10v/t-dbt.s +++ /dev/null @@ -1,38 +0,0 @@ -# mach: all -# output: -# sim: --environment operating -# as: -W - -.include "t-macros.i" - - start - - PSW_BITS = PSW_DM - -;;; Blat our DMAP registers so that they point at on-chip imem - - ldi r2, MAP_INSN | 0xf - st r2, @(DMAP_REG,r0) - ldi r2, MAP_INSN - st r2, @(IMAP1_REG,r0) - -;;; Patch the interrupt vector's dbt entry with a jmp to success - - ldi r4, #trap - ldi r5, (VEC_DBT & DMAP_MASK) + DMAP_BASE - ld2w r2, @(0,r4) - st2w r2, @(0,r5) - ld2w r2, @(4,r4) - st2w r2, @(4,r5) - -test_dbt: - dbt -> nop - exit47 - -success: - checkpsw2 1 PSW_BITS - exit0 - - .data -trap: ldi r1, success@word - jmp r1 diff --git a/sim/testsuite/sim/d10v/t-ld-st.s b/sim/testsuite/sim/d10v/t-ld-st.s deleted file mode 100644 index 4ae4f85..0000000 --- a/sim/testsuite/sim/d10v/t-ld-st.s +++ /dev/null @@ -1,36 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - ; Test ld and st - ld r4, @foo - check 1 r4 0xdead - - ldi r4, #0x2152 - st r4, @foo - ld r4, @foo - check 2 r4 0x2152 - - ; Test ld2w and st2w - ldi r4, #0xdead - st r4, @foo - ld2w r4, @foo - check2w2 3 r4 0xdead 0xf000 - - ldi r4, #0x2112 - ldi r5, #0x1984 - st2w r4, @foo - ld2w r4, @foo - check2w2 4 r4 0x2112 0x1984 - - .data - .align 2 -foo: .short 0xdead -bar: .short 0xf000 - .text - - exit0 diff --git a/sim/testsuite/sim/d10v/t-mac.s b/sim/testsuite/sim/d10v/t-mac.s deleted file mode 100644 index 1b6e660..0000000 --- a/sim/testsuite/sim/d10v/t-mac.s +++ /dev/null @@ -1,75 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - ;; clear FX - loadpsw2 0x8005 - loadacc2 a1 0x7f 0xffff 0xffff - load r8 0xffff - load r9 0x8001 -test_macu1: - MACU a1, r9, r8 - checkacc2 1 a1 0x80 0x8000 0x7FFE - - ;; set FX - loadpsw2 0x8085 - loadacc2 a1 0x7f 0xffff 0xffff - load r8 0xffff - load r9 0x8001 -test_macu2: - MACU a1, r9, r8 - checkacc2 2 a1 0x81 0x0000 0xfffd - - - - - ;; clear FX - ldi r2, #0x8005 - mvtc r2, cr0 - - loadacc2 a1 0x7f 0xffff 0xffff - ldi r8, #0xffff - ldi r9, #0x7FFF -test_macsu1: - MACSU a1, r9, r8 - checkacc2 3 a1 0x80 0x7FFE 0x8000 - - ;; set FX - ldi r2, #0x8085 - mvtc r2, cr0 - - loadacc2 a1 0x7f 0xffff 0xffff - ldi r8, #0xffff - ldi r9, #0x7FFF -test_macsu2: - MACSU a1, r9, r8 - checkacc2 4 a1 0x80 0xfffd 0x0001 - - ;; clear FX - ldi r2, #0x8005 - mvtc r2, cr0 - - loadacc2 a1 0x7f 0xffff 0xffff - ldi r8, 0xffff - ldi r9, 0x8001 -test_macsu3: - MACSU a1, r9, r8 - checkacc2 5 a1 0x7F 0x8001 0x7FFE - - ;; set FX - ldi r2, #0x8085 - mvtc r2, cr0 - - loadacc2 a1 0x7f 0xffff 0xffff - ldi r8, #0xffff - ldi r9, #0x8001 -test_macsu4: - MACSU a1, r9, r8 - checkacc2 6 a1 0x7f 0x0002 0xFFFD - - exit0 - diff --git a/sim/testsuite/sim/d10v/t-macros.i b/sim/testsuite/sim/d10v/t-macros.i deleted file mode 100644 index d6e155c..0000000 --- a/sim/testsuite/sim/d10v/t-macros.i +++ /dev/null @@ -1,235 +0,0 @@ -# mach: d10v -# output: -# sim: --environment operating - - .macro start - .text - .align 2 - .globl _start -_start: - ldi r0, 0 - .endm - - - .macro exit47 - ldi r4, 1 - ldi r0, 47 - trap 15 - .endm - - - .macro exit0 - ldi r4, 1 - ldi r0, 0 - trap 15 - .endm - - - .macro exit1 - ldi r4, 1 - ldi r0, 1 - trap 15 - .endm - - - .macro exit2 - ldi r4, 1 - ldi r0, 2 - trap 15 - .endm - - - .macro load reg val - ldi \reg, #\val - .endm - - - .macro load2w reg hi lo - ld2w \reg, @(1f,r0) - .data - .align 2 -1: .short \hi - .short \lo - .text - .endm - - - .macro check exit reg val - cmpeqi \reg, #\val - brf0t 1f -0: ldi r4, 1 - ldi r0, \exit - trap 15 -1: - .endm - - - .macro check2w2 exit reg hi lo - st2w \reg, @(1f,r0) - ld r2, @(1f, r0) - cmpeqi r2, #\hi - brf0f 0f - ld r2, @(1f + 2, r0) - cmpeqi r2, #\lo - brf0f 0f - bra 2f -0: ldi r4, 1 - ldi r0, \exit - trap 15 - .data - .align 2 -1: .long 0 - .text -2: - .endm - - - .macro loadacc2 acc guard hi lo - ldi r2, #\lo - mvtaclo r2, \acc - ldi r2, #\hi - mvtachi r2, \acc - ldi r2, #\guard - mvtacg r2, \acc - .endm - - - .macro checkacc2 exit acc guard hi lo - ldi r2, #\guard - mvfacg r3, \acc - cmpeq r2, r3 - brf0f 0f - ldi r2, #\hi - mvfachi r3, \acc - cmpeq r2, r3 - brf0f 0f - ldi r2, #\lo - mvfaclo r3, \acc - cmpeq r2, r3 - brf0f 0f - bra 4f -0: ldi r4, 1 - ldi r0, \exit - trap 15 -4: - .endm - - - .macro loadpsw2 val - ldi r2, #\val - mvtc r2, cr0 - .endm - - - .macro checkpsw2 exit val - mvfc r2, cr0 - cmpeqi r2, #\val - brf0t 1f - ldi r4, 1 - ldi r0, \exit - trap 15 -1: - .endm - - - .macro hello - ;; 4:write (1, string, strlen (string)) - ldi r4, 4 - ldi r0, 1 - ldi r1, 1f - ldi r2, 2f-1f-1 - trap 15 - .section .rodata -1: .string "Hello World!\n" -2: .align 2 - .text - .endm - - -;;; Blat our DMAP registers so that they point at on-chip imem - .macro point_dmap_at_imem - .text - ldi r2, MAP_INSN | 0xf - st r2, @(DMAP_REG,r0) - ldi r2, MAP_INSN - st r2, @(IMAP1_REG,r0) - .endm - -;;; Patch VEC so that it jumps back to code that checks PSW -;;; and then exits with success. - .macro check_interrupt vec psw src -;;; Patch the interrupt vector's AE entry with a jmp to success - .text - ldi r4, #1f - ldi r5, \vec - ;; - ld2w r2, @(0,r4) - st2w r2, @(0,r5) - ld2w r2, @(4,r4) - st2w r2, @(4,r5) - ;; - bra 9f - nop -;;; Code that gets patched into the interrupt vector - .data -1: ldi r1, 2f@word - jmp r1 -;;; Successfull trap jumps back to here - .text -;;; Verify the PSW -2: mvfc r2, cr0 - cmpeqi r2, #\psw - brf0t 3f - nop - exit1 -;;; Verify the original addr -3: mvfc r2, bpc - cmpeqi r2, #\src@word - brf0t 4f - exit2 -4: exit0 -;;; continue as normal -9: - .endm - - - PSW_SM = 0x8000 - PSW_01 = 0x4000 - PSW_EA = 0x2000 - PSW_DB = 0x1000 - PSW_DM = 0x0800 - PSW_IE = 0x0400 - PSW_RP = 0x0200 - PSW_MD = 0x0100 - PSW_FX = 0x0080 - PSW_ST = 0x0040 - PSW_10 = 0x0020 - PSW_11 = 0x0010 - PSW_F0 = 0x0008 - PSW_F1 = 0x0004 - PSW_14 = 0x0002 - PSW_C = 0x0001 - - -;;; - - DMAP_MASK = 0x3fff - DMAP_BASE = 0x8000 - DMAP_REG = 0xff04 - - IMAP0_REG = 0xff00 - IMAP1_REG = 0xff02 - - MAP_INSN = 0x1000 - -;;; - - VEC_RI = 0x3ff00 - VEC_BAE = 0x3ff04 - VEC_RIE = 0x3ff08 - VEC_AE = 0x3ff0c - VEC_TRAP = 0x3ff10 - VEC_DBT = 0x3ff50 - VEC_SDBT = 0x3fff4 - VEC_DBI = 0x3ff58 - VEC_EI = 0x3ff5c diff --git a/sim/testsuite/sim/d10v/t-mod-ld-pre.s b/sim/testsuite/sim/d10v/t-mod-ld-pre.s deleted file mode 100644 index 7d75af2..0000000 --- a/sim/testsuite/sim/d10v/t-mod-ld-pre.s +++ /dev/null @@ -1,126 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - mvfc r0, PSW || ldi.s r14, #0 - ldi.l r2, 0x100 ; MOD_E - ldi.l r3, 0x108 ; MOD_S - -test_mod_dec_ld: - mvtc r2, MOD_E || bseti r0, #7 - mvtc r3, MOD_S - mvtc r0, PSW ; modulo mode enable - mv r1,r3 ; r1=0x108 - ld r4, @r1- || nop ; r1=0x106 - ld r4, @r1- || nop ; r1=0x104 - ld r4, @r1- || nop ; r1=0x102 - ld r4, @r1- || nop ; r1=0x100 - ld r4, @r1- || nop ; r1=0x108 - ld r4, @r1- || nop ; r1=0x106 - - cmpeqi r1,#0x106 - brf0f _ERR ; branch to error - -test_mod_inc_ld: - mvtc r2, MOD_S - mvtc r3, MOD_E - mv r1,r2 ; r1=0x100 - ld r4, @r1+ || nop ; r1=0x102 - ld r4, @r1+ || nop ; r1=0x104 - ld r4, @r1+ || nop ; r1=0x106 - ld r4, @r1+ || nop ; r1=0x108 - ld r4, @r1+ || nop ; r1=0x100 - ld r4, @r1+ || nop ; r1=0x102 - - cmpeqi r1,#0x102 - brf0f _ERR - -test_mod_dec_ld2w: - mvtc r2, MOD_E - mvtc r3, MOD_S - mv r1,r3 ; r1=0x108 - ld2W r4, @r1- || nop ; r1=0x104 - ld2W r4, @r1- || nop ; r1=0x100 - ld2W r4, @r1- || nop ; r1=0x108 - ld2W r4, @r1- || nop ; r1=0x104 - - cmpeqi r1,#0x104 - brf0f _ERR ; <= branch to error - -test_mod_inc_ld2w: - mvtc r2, MOD_S - mvtc r3, MOD_E || BCLRI r0, #7 - mv r1,r2 ; r1=0x100 - ld2W r4, @r1+ || nop ; r1=0x104 - ld2W r4, @r1+ || nop ; r1=0x108 - ld2W r4, @r1+ || nop ; r1=0x100 - ld2W r4, @r1+ || nop ; r1=0x104 - - cmpeqi r1,#0x104 - brf0f _ERR - -test_mod_dec_ld_dis: - mvtc r0, PSW ; modulo mode disable - mvtc r2, MOD_E - mvtc r3, MOD_S - mv r1,r3 ; r1=0x108 - ld r4, @r1- || nop ; r1=0x106 - ld r4, @r1- || nop ; r1=0x104 - ld r4, @r1- || nop ; r1=0x102 - ld r4, @r1- || nop ; r1=0x100 - ld r4, @r1- || nop ; r1=0xFE - ld r4, @r1- || nop ; r1=0xFC - - cmpeqi r1,#0xFC - brf0f _ERR - -test_mod_inc_ld_dis: - mvtc r2, MOD_S - mvtc r3, MOD_E - mv r1,r2 ; r1=0x100 - ld r4, @r1+ || nop ; r1=0x102 - ld r4, @r1+ || nop ; r1=0x104 - ld r4, @r1+ || nop ; r1=0x106 - ld r4, @r1+ || nop ; r1=0x108 - ld r4, @r1+ || nop ; r1=0x10A - ld r4, @r1+ || nop ; r1=0x10C - - cmpeqi r1,#0x10C - brf0f _ERR - -test_mod_dec_ld2w_dis: - mvtc r2, MOD_E - mvtc r3, MOD_S - mv r1,r3 ; r1=0x108 - ld2W r4, @r1- || nop ; r1=0x104 - ld2W r4, @r1- || nop ; r1=0x100 - ld2W r4, @r1- || nop ; r1=0xFC - ld2W r4, @r1- || nop ; r1=0xF8 - - cmpeqi r1,#0xF8 - brf0f _ERR - - test_mod_inc_ld2w_dis: - mvtc r2, MOD_S - mvtc r3, MOD_E - mv r1,r2 ; r1=0x100 - ld2W r4, @r1+ || nop ; r1=0x104 - ld2W r4, @r1+ || nop ; r1=0x108 - ld2W r4, @r1+ || nop ; r1=0x10C - ld2W r4, @r1+ || nop ; r1=0x110 - - cmpeqi r1,#0x110 - brf0f _ERR - -_OK: - exit0 - -_ERR: - exit47 - - - diff --git a/sim/testsuite/sim/d10v/t-msbu.s b/sim/testsuite/sim/d10v/t-msbu.s deleted file mode 100644 index 93b65a5..0000000 --- a/sim/testsuite/sim/d10v/t-msbu.s +++ /dev/null @@ -1,32 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - ;; clear FX - ldi r2, #0x8005 - mvtc r2, cr0 - - loadacc2 a1 0x7f 0xffff 0xffff - ldi r8, 0xffff - ldi r9, 0x8001 -test_msbu1: - MSBU a1, r9, r8 - checkacc2 1 a1 0X7F 0x7FFF 0x8000 - - - ;; set FX - ldi r2, #0x8085 - mvtc r2, cr0 - - loadacc2 a1 0x7f 0xffff 0xffff - ldi r8, 0xffff - ldi r9, 0x8001 -test_msbu2: - MSBU a1, r9, r8 - checkacc2 2 a1 0X7E 0xFFFF 0x0001 - - exit0 diff --git a/sim/testsuite/sim/d10v/t-mulxu.s b/sim/testsuite/sim/d10v/t-mulxu.s deleted file mode 100644 index b0c14b6..0000000 --- a/sim/testsuite/sim/d10v/t-mulxu.s +++ /dev/null @@ -1,32 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - ;; clear FX - ldi r2, #0x8005 - mvtc r2, cr0 - - loadacc2 a1 0x7f 0xffff 0xffff - ldi r8, 0xffff - ldi r9, 0x8001 -test_mulxu1: - MULXU a1, r9, r8 - checkacc2 1 a1 0x00 0x8000 0x7FFF - - - ;; set FX - ldi r2, #0x8085 - mvtc r2, cr0 - - loadacc2 a1 0x7f 0xffff 0xffff - ldi r8, 0xffff - ldi r9, 0x8001 -test_mulxu2: - MULXU a1, r9, r8 - checkacc2 2 a1 0x01 0x0000 0xFFFE - - exit0 diff --git a/sim/testsuite/sim/d10v/t-mvtac.s b/sim/testsuite/sim/d10v/t-mvtac.s deleted file mode 100644 index dc73403..0000000 --- a/sim/testsuite/sim/d10v/t-mvtac.s +++ /dev/null @@ -1,23 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - ldi r8, 0xbeef - mvtaclo r8, a0 - checkacc2 1 a0 0xff 0xffff 0xbeef - - mvtacg r0, a0 - checkacc2 2 a0 0x00 0xffff 0xbeef - - ldi r8, 0xdead - mvtachi r8, a0 - checkacc2 3 a0 0xff 0xdead 0xbeef - - loadacc2 a1 0xfe 0xbeef 0xdead - checkacc2 4 a1 0xfe 0xbeef 0xdead - - exit0 diff --git a/sim/testsuite/sim/d10v/t-mvtc.s b/sim/testsuite/sim/d10v/t-mvtc.s deleted file mode 100644 index 0b463ae..0000000 --- a/sim/testsuite/sim/d10v/t-mvtc.s +++ /dev/null @@ -1,134 +0,0 @@ -# mach: all -# output: -# sim: --environment operating -# as: -W - -.include "t-macros.i" - - start - -;;; Try out each bit in the PSW - - loadpsw2 PSW_SM - checkpsw2 1 PSW_SM - - loadpsw2 PSW_01 - checkpsw2 2 0 ;; PSW_01 - - loadpsw2 PSW_EA - checkpsw2 3 PSW_EA - - loadpsw2 PSW_DB - checkpsw2 4 PSW_DB - - loadpsw2 PSW_DM - checkpsw2 5 0 ;; PSW_DM - - loadpsw2 PSW_IE - checkpsw2 6 PSW_IE - - loadpsw2 PSW_RP - checkpsw2 7 PSW_RP - - loadpsw2 PSW_MD - checkpsw2 8 PSW_MD - - loadpsw2 PSW_FX|PSW_ST - checkpsw2 9 PSW_FX|PSW_ST - - ;; loadpsw2 PSW_ST - ;; checkpsw2 10 - - loadpsw2 PSW_10 - checkpsw2 11 0 ;; PSW_10 - - loadpsw2 PSW_11 - checkpsw2 12 0 ;; PSW_11 - - loadpsw2 PSW_F0 - checkpsw2 13 PSW_F0 - - loadpsw2 PSW_F1 - checkpsw2 14 PSW_F1 - - loadpsw2 PSW_14 - checkpsw2 15 0 ;; PSW_14 - - loadpsw2 PSW_C - checkpsw2 16 PSW_C - - -;;; Check that bit 0 (LSB) of the MOD_E & MOD_S registers are stuck at ZERO. - - ldi r6, #0xdead - mvtc r6, cr10 - ldi r6, #0xbeef - mvtc r6, cr11 - - mvfc r7, cr10 - check 17 r7 0xdeac - mvfc r7, cr11 - check 18 r7 0xbeee - -;;; Check that certain bits of the PSW, DPSW and BPSW are hardwired to zero - -psw_ffff: - ldi r6, 0xffff - mvtc r6, psw - mvfc r7, psw - check 18 r7 0xb7cd - -bpsw_ffff: - ldi r6, 0xffff - mvtc r6, bpsw - mvfc r7, bpsw - check 18 r7 0xb7cd - -dpsw_ffff: - ldi r6, 0xffff - mvtc r6, dpsw - mvfc r7, dpsw - check 18 r7 0xb7cd - -;;; Another check. Very similar - -psw_dfff: - ldi r6, 0xdfff - mvtc r6, psw - mvfc r7, psw - check 18 r7 0x97cd - -bpsw_dfff: - ldi r6, 0xdfff - mvtc r6, bpsw - mvfc r7, bpsw - check 18 r7 0x97cd - -dpsw_dfff: - ldi r6, 0xdfff - mvtc r6, dpsw - mvfc r7, dpsw - check 18 r7 0x97cd - -;;; And again. - -psw_8005: - ldi r6, 0x8005 - mvtc r6, psw - mvfc r7, psw - check 18 r7 0x8005 - -bpsw_8005: - ldi r6, 0x8005 - mvtc r6, bpsw - mvfc r7, bpsw - check 18 r7 0x8005 - -dpsw_8005: - ldi r6, 0x8005 - mvtc r6, dpsw - mvfc r7, dpsw - check 18 r7 0x8005 - - - exit0 diff --git a/sim/testsuite/sim/d10v/t-rac.s b/sim/testsuite/sim/d10v/t-rac.s deleted file mode 100644 index a452299..0000000 --- a/sim/testsuite/sim/d10v/t-rac.s +++ /dev/null @@ -1,20 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - ;; clear FX - loadpsw2 0x8004 - loadacc2 a0 0x80 0x0000 0x0000 - loadacc2 a1 0x00 0x0000 0x5000 - load r10 0x0123 - load r11 0x4567 -test_rac1: - RAC r10, a0, #-2 - checkpsw2 1 0x8008 - check2w2 2 r10 0x8000 0x0000 - - exit0 diff --git a/sim/testsuite/sim/d10v/t-rachi.s b/sim/testsuite/sim/d10v/t-rachi.s deleted file mode 100644 index 57589b5..0000000 --- a/sim/testsuite/sim/d10v/t-rachi.s +++ /dev/null @@ -1,32 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - loadacc2 a0 0x00 0x7FFF 0x8000 -test_rachi_1: - rachi r4, a0, 0 - check 1 r4 0x7FFF - - - loadacc2 a0 0xFF 0x8000 0x1000 -test_rachi_2: - rachi r4, a0, 0 - check 2 r4 0x8000 - - - loadacc2 a0 0x00 0x1000 0xA000 -test_rachi_3: - rachi r4, a0, 0 - check 3 r4 0x1001 - - - loadacc2 a0 0xFF 0xA000 0x7FFF -test_rachi_4: - rachi r4, a0, 0 - check 4 r4 0xa000 - - exit0 diff --git a/sim/testsuite/sim/d10v/t-rdt.s b/sim/testsuite/sim/d10v/t-rdt.s deleted file mode 100644 index 947da86..0000000 --- a/sim/testsuite/sim/d10v/t-rdt.s +++ /dev/null @@ -1,23 +0,0 @@ -# mach: all -# output: -# sim: --environment operating -# as: -W - -.include "t-macros.i" - - start - - PSW_BITS = PSW_C|PSW_F0|PSW_F1 - - ldi r6, #success@word - mvtc r6, dpc - ldi r6, #PSW_BITS - mvtc r6, dpsw - -test_rdt: - RTD - exit47 - -success: - checkpsw2 1 PSW_BITS - exit0 diff --git a/sim/testsuite/sim/d10v/t-rep.s b/sim/testsuite/sim/d10v/t-rep.s deleted file mode 100644 index 433aff1..0000000 --- a/sim/testsuite/sim/d10v/t-rep.s +++ /dev/null @@ -1,49 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - - - ;; Check that the instruction @REP_E is executed when it - ;; is reached using a branch instruction - - ldi r2, 1 -test_rep_1: - rep r2, end_rep_1 - nop || nop - nop || nop - nop || nop - nop || nop - ldi r3, 46 - bra end_rep_1 - ldi r3, 42 -end_rep_1: - addi r3, 1 - - check 1 r3 47 - - - ;; Check that the loop is executed the correct number of times - - ldi r2, 10 - ldi r3, 0 - ldi r4, 0 -test_rep_2: - rep r2, end_rep_2 - nop || nop - nop || nop - nop || nop - nop || nop - nop || nop - addi r3, 1 -end_rep_2: - addi r4, 1 - - check 2 r3 10 - check 3 r4 10 - - exit0 diff --git a/sim/testsuite/sim/d10v/t-rie-xx.s b/sim/testsuite/sim/d10v/t-rie-xx.s deleted file mode 100644 index fa6b4fc..0000000 --- a/sim/testsuite/sim/d10v/t-rie-xx.s +++ /dev/null @@ -1,16 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = 0 - point_dmap_at_imem - check_interrupt (VEC_RIE&DMAP_MASK)+DMAP_BASE PSW_BITS test_rie_xx - -test_rie_xx: - .short 0xe120, 0x0000 ;; Example of RIE code - nop - exit47 diff --git a/sim/testsuite/sim/d10v/t-rte.s b/sim/testsuite/sim/d10v/t-rte.s deleted file mode 100644 index 392f118..0000000 --- a/sim/testsuite/sim/d10v/t-rte.s +++ /dev/null @@ -1,22 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = PSW_C|PSW_F0|PSW_F1 - - ldi r6, #success@word - mvtc r6, bpc - ldi r6, #PSW_BITS - mvtc r6, bpsw - -test_rte: - RTE - exit47 - -success: - checkpsw2 1 PSW_BITS - exit0 diff --git a/sim/testsuite/sim/d10v/t-sac.s b/sim/testsuite/sim/d10v/t-sac.s deleted file mode 100644 index 84c31d7..0000000 --- a/sim/testsuite/sim/d10v/t-sac.s +++ /dev/null @@ -1,27 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - -test_sac_1: - loadacc2 a0 0x00 0xAFFF 0x0000 - sac r4, a0 - check 1 r4 0x7FFF - check 2 r5 0xFFFF - -test_sac_2: - loadacc2 a0 0xFF 0x7000 0x0000 - sac r4, a0 - check 3 r4 0x8000 - check 4 r5 0x0000 - -test_sac_3: - loadacc2 a0 0x00 0x1000 0xA000 - sac r4, a0 - check 5 r4 0x1000 - check 6 r5 0xA000 - - exit0 diff --git a/sim/testsuite/sim/d10v/t-sachi.s b/sim/testsuite/sim/d10v/t-sachi.s deleted file mode 100644 index b9ed0e7..0000000 --- a/sim/testsuite/sim/d10v/t-sachi.s +++ /dev/null @@ -1,26 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - -test_sachi_1: - loadacc2 a0 0x00 0xAFFF 0x0000 - sachi r4, a0 - check 1 r4 0x7FFF - - -test_sachi_2: - loadacc2 a0 0xFF 0x8000 0x1000 - sachi r4, a0 - check 2 r4 0x8000 - - -test_sachi_3: - loadacc2 a0 0x00 0x1000 0xA000 - sachi r4, a0 - check 3 r4 0x1000 - - exit0 diff --git a/sim/testsuite/sim/d10v/t-sadd.s b/sim/testsuite/sim/d10v/t-sadd.s deleted file mode 100644 index fb463d9..0000000 --- a/sim/testsuite/sim/d10v/t-sadd.s +++ /dev/null @@ -1,42 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - PSW_BITS = PSW_FX|PSW_ST|PSW_SM - loadpsw2 PSW_BITS - - ;; Test normal sadd - - loadacc2 a0 0x00 0x7fff 0xffff - loadacc2 a1 0xff 0x8000 0x0000 - sadd a1, a0 - checkacc2 1 a0 0x00 0x7fff 0xffff - checkacc2 2 a1 0xff 0x8000 0x7fff - - ;; Test overflow - - loadacc2 a0 0x00 0x0000 0x0000 - loadacc2 a1 0x01 0x8000 0x0000 - sadd a1, a0 - checkacc2 3 a0 0x00 0x0000 0x0000 - checkacc2 4 a1 0x00 0x7fff 0xffff - - loadacc2 a0 0x00 0xffff 0xffff - loadacc2 a1 0x00 0xffff 0xffff - sadd a1, a0 - checkacc2 5 a1 0x00 0x7fff 0xffff - checkacc2 6 a0 0x00 0xffff 0xffff - - ;; Test underflow - - loadacc2 a0 0x00 0x0000 0x0000 - loadacc2 a1 0x80 0x8000 0x0000 - sadd a1, a0 - checkacc2 7 a0 0x00 0x0000 0x0000 - checkacc2 8 a1 0xff 0x8000 0x0000 - - exit0 diff --git a/sim/testsuite/sim/d10v/t-slae.s b/sim/testsuite/sim/d10v/t-slae.s deleted file mode 100644 index 8236fa2..0000000 --- a/sim/testsuite/sim/d10v/t-slae.s +++ /dev/null @@ -1,43 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - -test_slae_1: - loadpsw2 PSW_ST|PSW_FX - loadacc2 a0 0x00 0x0AFF 0xF000 - ldi r0, 4 - slae a0, r0 - checkacc2 1 a0 0x00 0x7FFF 0xFFFF - -test_slae_2: - loadpsw2 PSW_ST|PSW_FX - loadacc2 a0 0xFF 0xF700 0x1000 - ldi r0, 4 - slae a0, r0 - checkacc2 2 a0 0xFF 0x8000 0x0000 - -test_slae_3: - loadpsw2 PSW_ST|PSW_FX - loadacc2 a0 0x00 0x0010 0xA000 - ldi r0, 4 - slae a0, r0 - checkacc2 3 a0 0x00 0x010A 0x0000 - -test_slae_4: - loadpsw2 0 - loadacc2 a0 0x00 0x0010 0xA000 - ldi r0, 4 - slae a0, r0 - checkacc2 4 a0 0x00 0x010A 0x0000 - -test_slae_5: - loadacc2 a0 0x00 0x0010 0xA000 - ldi r0, -4 - slae a0, r0 - checkacc2 4 a0 0x00 0x0001 0x0A00 - - exit0 diff --git a/sim/testsuite/sim/d10v/t-sp.s b/sim/testsuite/sim/d10v/t-sp.s deleted file mode 100644 index df443b9..0000000 --- a/sim/testsuite/sim/d10v/t-sp.s +++ /dev/null @@ -1,21 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - -;;; Read/Write values to SPU/SPI - - loadpsw2 0 - ldi sp, 0xdead - loadpsw2 PSW_SM - ldi sp, 0xbeef - - loadpsw2 0 - check 1 sp 0xdead - loadpsw2 PSW_SM - check 2 sp 0xbeef - - exit0 diff --git a/sim/testsuite/sim/d10v/t-sub.s b/sim/testsuite/sim/d10v/t-sub.s deleted file mode 100644 index 57b99e6..0000000 --- a/sim/testsuite/sim/d10v/t-sub.s +++ /dev/null @@ -1,46 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - -;; The d10v implements negated addition for subtraction - - .macro check_sub s x y r c - ;; clear carry - ldi r6,#0x8004 - mvtc r6,cr0 - ;; subtract - ldi r10,#\x - ldi r11,#\y - sub r10, r11 - ;; verify result - ldi r12, #\r - cmpeq r10, r12 - brf0t 1f - ldi r6, 1 - ldi r2, #\s - trap 15 -1: - ;; verify carry - mvfc r6, cr0 - and3 r6, r6, #1 - cmpeqi r6, #\c - brf0t 1f - ldi r6, 1 - ldi r2, #\s - trap 15 -1: - .endm - -check_sub 1 0x0000 0x0000 0x0000 1 -check_sub 2 0x0000 0x0001 0xffff 0 -check_sub 3 0x0001 0x0000 0x0001 1 -check_sub 4 0x0001 0x0001 0x0000 1 -check_sub 5 0x0000 0x8000 0x8000 0 -check_sub 6 0x8000 0x0001 0x7fff 1 -check_sub 7 0x7fff 0x7fff 0x0000 1 - - exit0 diff --git a/sim/testsuite/sim/d10v/t-sub2w.s b/sim/testsuite/sim/d10v/t-sub2w.s deleted file mode 100644 index 5e8daee..0000000 --- a/sim/testsuite/sim/d10v/t-sub2w.s +++ /dev/null @@ -1,61 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - -;; The d10v implements negated addition for subtraction - - .macro check_sub2w s x y r c v - - ;; clear carry - ldi r6,#0x8004 - mvtc r6,cr0 - - ;; load opnds - ld2w r6, @(1f,r0) - ld2w r8, @(2f,r0) - .data -1: .long \x -2: .long \y - .text - - ;; subtract - SUB2W r6, r8 - - ;; verify result - ld2w r10, @(1f,r0) - .data -1: .long \r - .text - cmpeq r6, r10 - brf0f 2f - cmpeq r7, r11 - brf0t 3f -2: ldi r4, 1 - ldi r0, \s - trap 15 -3: - - ;; verify carry - mvfc r6, cr0 - and3 r6, r6, #1 - cmpeqi r6, #\c - brf0t 1f - ldi r4, 1 - ldi r0, \s - trap 15 -1: - .endm - -check_sub2w 1 0x00000000 0x00000000 0x00000000 1 0 -check_sub2w 2 0x00000000 0x00000001 0xffffffff 0 0 -check_sub2w 3 0x00000001 0x00000000 0x00000001 1 0 -check_sub2w 3 0x00000001 0x00000001 0x00000000 1 0 -check_sub2w 5 0x00000000 0x80000000 0x80000000 0 1 -check_sub2w 6 0x80000000 0x00000001 0x7fffffff 1 1 -check_sub2w 7 0x7fffffff 0x7fffffff 0x00000000 1 0 - - exit0 diff --git a/sim/testsuite/sim/d10v/t-subi.s b/sim/testsuite/sim/d10v/t-subi.s deleted file mode 100644 index dd4b2be..0000000 --- a/sim/testsuite/sim/d10v/t-subi.s +++ /dev/null @@ -1,43 +0,0 @@ -# mach: all -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - -;; The d10v implements negated addition for subtraction - - .macro check_subi s x y r c v - ;; clear carry - ldi r6,#0x8004 - mvtc r6,cr0 - ;; subtract - ldi r10,#\x - SUBI r10,#\y - ;; verify result - ldi r11, #\r - cmpeq r10, r11 - brf0t 1f - ldi r6, 1 - ldi r2, \s - trap 15 -1: - ;; verify carry - mvfc r6, cr0 - and3 r6, r6, #1 - cmpeqi r6, #\c - brf0t 1f - ldi r6, 1 - ldi r2, \s - trap 15 -1: - .endm - - check_subi 1 0000 0x0000 0xfff0 00 ;; 0 - 0x10 - check_subi 2 0x0000 0x0001 0xffff 0 0 - check_subi 3 0x0001 0x0000 0xfff1 0 0 - check_subi 4 0x0001 0x0001 0x0000 1 0 - check_subi 5 0x8000 0x0001 0x7fff 1 1 - - exit0 diff --git a/sim/testsuite/sim/d10v/t-trap.s b/sim/testsuite/sim/d10v/t-trap.s deleted file mode 100644 index 7e5336c..0000000 --- a/sim/testsuite/sim/d10v/t-trap.s +++ /dev/null @@ -1,10 +0,0 @@ -# mach: all -# status: 47 -# output: -# sim: --environment operating - -.include "t-macros.i" - - start - - exit47 diff --git a/sim/testsuite/sim/frv/ChangeLog b/sim/testsuite/sim/frv/ChangeLog deleted file mode 100644 index 66f027e..0000000 --- a/sim/testsuite/sim/frv/ChangeLog +++ /dev/null @@ -1,82 +0,0 @@ -2021-01-15 Mike Frysinger - - * cache.ms: New testcase from ../../frv-elf/. - * exit47.ms, grloop.ms, hello.ms: Likewise. - * misc.exp: New file. - -2004-03-01 Richard Sandiford - - * allinsn.exp (all_machs): Add fr405 and fr450. - * fr400/allinsn.exp (all_machs): Likewise. - * fr400/addss.cgs (mach): Change to "fr405 fr450". - * fr400/scutss.cgs (mach): Likewise. - * fr400/slass.cgs (mach): Likewise. - * fr400/smass.cgs (mach): Likewise. - * fr400/smsss.cgs (mach): Likewise. - * fr400/smu.cgs (mach): Likewise. - * fr400/subss.cgs (mach): Likewise. - * interrupts/fp_exception.cgs: Replace fmadds with .word. - * interrupts/fp_exception-fr550.cgs: Likewise. - * mqlclrhs.cgs: New test. - * mqlmths.cgs: New test. - * mqsllhi.cgs: New test. - * mqsrahi.cgs: New test. - -2004-03-01 Richard Sandiford - - * fr400/scutss.cgs: Fix tests to account for rounding. - Add some new ones. - -2004-03-01 Richard Sandiford - - * {rstb,rsth,rst,rstd,rstq}.cgs: Delete. - * {rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete. - -2003-10-10 Dave Brolley - - * testutils.inc (or_gr_immed): New macro. - * fp_exception-fr550.cgs: Write insns using - unaligned registers into the program in order to - cause the required exceptions. - * fp_exception.cgs: Ditto. - * regalign.cgs: Ditto. - -2003-10-06 Dave Brolley - - * fr550: New subdirectory. - * fr400/*.cgs: Add fr550 as appropriate. - * fr500/*.cgs: Add fr550 as appropriate. - * interrupts/*.cgs: Add fr550 as appropriate. - * interrupts/*-fr550.cgs: New test cases for fr550. - -2003-09-19 Michael Snyder - - * nldqi.cgs: Remove. This insn was never implemented - by Fujitsu. - -2003-09-19 Dave Brolley - - * rstqf.cgs: Use nldq instead of nldqi. - * rstq.cgs: Use nldq instead of nldqi. - -2003-09-11 Michael Snyder - - * movgs.cgs: Change lcr to spr[273], - which according to the comments seems to be the intent. - -2003-09-09 Dave Brolley - - * maddaccs.cgs: move to fr400 subdirectory. - * msubaccs.cgs: move to fr400 subdirectory. - * masaccs.cgs: move to fr400 subdirectory. - -2003-09-03 Michael Snyder - - * fr500/mclracc.cgs: Change mach to 'all', to be - consistent with other tests in the directory. - -2003-09-03 Michael Snyder - - * interrupts/Ipipe-fr400.cgs: New file. - * interrupts/Ipipe-fr500.cgs: New file. - * interrupts/Ipipe.cgs: Remove (replaced by above). diff --git a/sim/testsuite/sim/frv/add.cgs b/sim/testsuite/sim/frv/add.cgs deleted file mode 100644 index 54fdfd5..0000000 --- a/sim/testsuite/sim/frv/add.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for add $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - add gr7,gr8,gr8 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - add gr7,gr8,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - - add gr8,gr8,gr8 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/add.pcgs b/sim/testsuite/sim/frv/add.pcgs deleted file mode 100644 index cf49976..0000000 --- a/sim/testsuite/sim/frv/add.pcgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv parallel testcase for add $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - add.p gr7,gr8,gr8 - add gr7,gr8,gr9 - add.p gr7,gr8,gr10 - add gr7,gr8,gr11 - add.p gr7,gr8,gr12 - add gr7,gr8,gr13 - test_gr_immed 3,gr8 - test_gr_immed 3,gr9 - test_gr_immed 4,gr10 - test_gr_immed 4,gr11 - test_gr_immed 4,gr12 - test_gr_immed 4,gr13 - - pass diff --git a/sim/testsuite/sim/frv/addcc.cgs b/sim/testsuite/sim/frv/addcc.cgs deleted file mode 100644 index d2e33d8..0000000 --- a/sim/testsuite/sim/frv/addcc.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# frv testcase for addcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global addcc -addcc: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - addcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - addcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x08,0 ; Set mask opposite of expected - addcc gr8,gr8,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - addcc gr8,gr8,gr8,icc0; test zero, carry and overflow bits - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - - pass diff --git a/sim/testsuite/sim/frv/addi.cgs b/sim/testsuite/sim/frv/addi.cgs deleted file mode 100644 index 3d60c5d..0000000 --- a/sim/testsuite/sim/frv/addi.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for addi $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global addi -addi: - set_gr_immed 4,gr8 - addi gr8,0,gr8 - test_gr_immed 4,gr8 - addi gr8,1,gr8 - test_gr_immed 5,gr8 - addi gr8,15,gr8 - test_gr_immed 20,gr8 - set_gr_limmed 0x7fff,0xffff,gr8 - addi gr8,1,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - addi gr8,0x7ff,gr8 - test_gr_limmed 0x8000,0x07ff,gr8 - addi gr8,-2048,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - - pass diff --git a/sim/testsuite/sim/frv/addicc.cgs b/sim/testsuite/sim/frv/addicc.cgs deleted file mode 100644 index 6f2a197..0000000 --- a/sim/testsuite/sim/frv/addicc.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for addicc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global addicc -addicc: - ; Test add $u4Ri - set_gr_immed 4,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - addicc gr8,0,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 4,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - addicc gr8,1,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 5,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - addicc gr8,15,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 20,gr8 - set_gr_limmed 0x7fff,0xffff,gr8 ; test neg and overflow bits - set_icc 0x05,0 ; Set mask opposite of expected - addicc gr8,1,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/addx.cgs b/sim/testsuite/sim/frv/addx.cgs deleted file mode 100644 index 259a694..0000000 --- a/sim/testsuite/sim/frv/addx.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for addx $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global addx -addx: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry bit is off - addx gr7,gr8,gr8,icc0 - test_icc 1 1 1 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x04,0 ; Make sure carry bit is off - addx gr7,gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x08,0 ; Make sure carry bit is off - addx gr8,gr8,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Make sure carry bit is on - addx gr7,gr8,gr8,icc0 - test_icc 1 1 1 1 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 0,gr8 - set_icc 0x05,0 ; Make sure carry bit is on - addx gr7,gr8,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_icc 0x0b,0 ; Make sure carry bit is on - addx gr7,gr8,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/addxcc.cgs b/sim/testsuite/sim/frv/addxcc.cgs deleted file mode 100644 index 230c047..0000000 --- a/sim/testsuite/sim/frv/addxcc.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for addxcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global addxcc -addxcc: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry bit is off - addxcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x04,0 ; Make sure carry bit is off - addxcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x08,0 ; Make sure carry bit is off - addxcc gr8,gr8,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Make sure carry bit is on - addxcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 0,gr8 - set_icc 0x05,0 ; Make sure carry bit is on - addxcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_icc 0x0b,0 ; Make sure carry bit is on - addxcc gr7,gr8,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/addxi.cgs b/sim/testsuite/sim/frv/addxi.cgs deleted file mode 100644 index c36272a..0000000 --- a/sim/testsuite/sim/frv/addxi.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# frv testcase for addxi $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global addxi -addxi: - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry bit is off - addxi gr8,1,gr8,icc0 - test_icc 1 1 1 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x04,0 ; Make sure carry bit is off - addxi gr8,1,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xffff,0xff00,gr8 - set_icc 0x08,0 ; Make sure carry bit is off - addxi gr8,0x100,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Make sure carry bit is on - addxi gr8,1,gr8,icc0 - test_icc 1 1 1 1 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x05,0 ; Make sure carry bit is on - addxi gr8,0,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xffff,0xfeff,gr8 - set_icc 0x0b,0 ; Make sure carry bit is on - addxi gr8,0x100,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/addxicc.cgs b/sim/testsuite/sim/frv/addxicc.cgs deleted file mode 100644 index 831fec3..0000000 --- a/sim/testsuite/sim/frv/addxicc.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# frv testcase for addxicc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global addxicc -addxicc: - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry bit is off - addxicc gr8,1,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x04,0 ; Make sure carry bit is off - addxicc gr8,1,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xffff,0xff00,gr8 - set_icc 0x08,0 ; Make sure carry bit is off - addxicc gr8,0x100,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Make sure carry bit is on - addxicc gr8,1,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x05,0 ; Make sure carry bit is on - addxicc gr8,0,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xffff,0xfeff,gr8 - set_icc 0x0b,0 ; Make sure carry bit is on - addxicc gr8,0x100,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/allinsn.exp b/sim/testsuite/sim/frv/allinsn.exp deleted file mode 100644 index b7f9fe2..0000000 --- a/sim/testsuite/sim/frv/allinsn.exp +++ /dev/null @@ -1,19 +0,0 @@ -# FRV simulator testsuite. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "frv fr500 fr550 fr400 fr405 fr450" - set cpu_option -mcpu - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/and.cgs b/sim/testsuite/sim/frv/and.cgs deleted file mode 100644 index a1773f1..0000000 --- a/sim/testsuite/sim/frv/and.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for and $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global and -and: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - and gr7,gr8,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - and gr7,gr8,gr8 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0xaaaa,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - and gr7,gr8,gr8 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x0000,0xaaaa,gr8 - - pass diff --git a/sim/testsuite/sim/frv/andcc.cgs b/sim/testsuite/sim/frv/andcc.cgs deleted file mode 100644 index a2a04d2..0000000 --- a/sim/testsuite/sim/frv/andcc.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for andcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global andcc -andcc: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - andcc gr7,gr8,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - andcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0xaaaa,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - andcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0x0000,0xaaaa,gr8 - - pass diff --git a/sim/testsuite/sim/frv/andcr.cgs b/sim/testsuite/sim/frv/andcr.cgs deleted file mode 100644 index 9fbbaff..0000000 --- a/sim/testsuite/sim/frv/andcr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for andcr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global andcr -andcr: - set_spr_immed 0x1b1b,cccr - andcr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc7,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc7,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc6,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc6,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc5,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc5,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc5,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc5,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc4,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc4,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc4,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - andcr cc4,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/andi.cgs b/sim/testsuite/sim/frv/andi.cgs deleted file mode 100644 index e9fdf75..0000000 --- a/sim/testsuite/sim/frv/andi.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for andi $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global andi -andi: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x0b,0 ; Set mask opposite of expected - andi gr7,0x555,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_icc 0x04,0 ; Set mask opposite of expected - andi gr7,-2048,gr8 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0xaaaa,0xa800,gr8 - - set_icc 0x0d,0 ; Set mask opposite of expected - andi gr7,-1,gr8 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - pass diff --git a/sim/testsuite/sim/frv/andicc.cgs b/sim/testsuite/sim/frv/andicc.cgs deleted file mode 100644 index 6508059..0000000 --- a/sim/testsuite/sim/frv/andicc.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for andicc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global andicc -andicc: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x0b,0 ; Set mask opposite of expected - andicc gr7,0x155,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_icc 0x04,0 ; Set mask opposite of expected - andicc gr7,-512,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0xaaaa,0xaa00,gr8 - - set_icc 0x05,0 ; Set mask opposite of expected - andicc gr7,-1,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - pass diff --git a/sim/testsuite/sim/frv/andncr.cgs b/sim/testsuite/sim/frv/andncr.cgs deleted file mode 100644 index 31fd1f7..0000000 --- a/sim/testsuite/sim/frv/andncr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for andncr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global andncr -andncr: - set_spr_immed 0x1b1b,cccr - andncr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc7,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc7,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc6,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc6,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc5,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc5,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc5,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - andncr cc5,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - andncr cc4,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc4,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc4,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc4,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/bar.cgs b/sim/testsuite/sim/frv/bar.cgs deleted file mode 100644 index df6a9ca..0000000 --- a/sim/testsuite/sim/frv/bar.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# frv testcase for bar -# mach: all - - .include "testutils.inc" - - start - - .global bar -bar: - bar - - pass diff --git a/sim/testsuite/sim/frv/bc.cgs b/sim/testsuite/sim/frv/bc.cgs deleted file mode 100644 index a5c612c..0000000 --- a/sim/testsuite/sim/frv/bc.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bc $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bc -bc: - set_icc 0x0 0 - bc icc0,0,bad - set_icc 0x1 1 - bc icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bc icc2,2,bad - set_icc 0x3 3 - bc icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - bc icc0,0,bad - set_icc 0x5 1 - bc icc1,1,ok6 - fail -ok6: - set_icc 0x6 2 - bc icc2,2,bad - set_icc 0x7 3 - bc icc3,3,ok8 - fail -ok8: - set_icc 0x8 0 - bc icc0,0,bad - set_icc 0x9 1 - bc icc1,1,oka - fail -oka: - set_icc 0xa 2 - bc icc2,2,bad - set_icc 0xb 3 - bc icc3,3,okc - fail -okc: - set_icc 0xc 0 - bc icc0,0,bad - set_icc 0xd 1 - bc icc1,1,oke - fail -oke: - set_icc 0xe 2 - bc icc2,2,bad - set_icc 0xf 3 - bc icc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcclr.cgs b/sim/testsuite/sim/frv/bcclr.cgs deleted file mode 100644 index 248be13..0000000 --- a/sim/testsuite/sim/frv/bcclr.cgs +++ /dev/null @@ -1,293 +0,0 @@ -# frv testcase for bcclr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcclr -bcclr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcclr icc0,0,0 - - set_spr_addr ok2,lr - set_icc 0x1 1 - bcclr icc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bcclr icc2,0,2 - - set_spr_addr ok4,lr - set_icc 0x3 3 - bcclr icc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bcclr icc0,0,0 - - set_spr_addr ok6,lr - set_icc 0x5 1 - bcclr icc1,0,1 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x6 2 - bcclr icc2,0,2 - - set_spr_addr ok8,lr - set_icc 0x7 3 - bcclr icc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bcclr icc0,0,0 - - set_spr_addr oka,lr - set_icc 0x9 1 - bcclr icc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bcclr icc2,0,2 - - set_spr_addr okc,lr - set_icc 0xb 3 - bcclr icc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bcclr icc0,0,0 - - set_spr_addr oke,lr - set_icc 0xd 1 - bcclr icc1,0,1 - fail -oke: - set_spr_addr bad,lr - set_icc 0xe 2 - bcclr icc2,0,2 - - set_spr_addr okg,lr - set_icc 0xf 3 - bcclr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcclr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcclr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bcclr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bcclr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bcclr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bcclr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bcclr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bcclr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bcclr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bcclr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bcclr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcclr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bcclr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bcclr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bcclr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bcclr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcclr icc0,1,0 - - set_icc 0x1 1 - bcclr icc1,1,1 - - set_icc 0x2 2 - bcclr icc2,1,2 - - set_icc 0x3 3 - bcclr icc3,1,3 - - set_icc 0x4 0 - bcclr icc0,1,0 - - set_icc 0x5 1 - bcclr icc1,1,1 - - set_icc 0x6 2 - bcclr icc2,1,2 - - set_icc 0x7 3 - bcclr icc3,1,3 - - set_icc 0x8 0 - bcclr icc0,1,0 - - set_icc 0x9 1 - bcclr icc1,1,1 - - set_icc 0xa 2 - bcclr icc2,1,2 - - set_icc 0xb 3 - bcclr icc3,1,3 - - set_icc 0xc 0 - bcclr icc0,1,0 - - set_icc 0xd 1 - bcclr icc1,1,1 - - set_icc 0xe 2 - bcclr icc2,1,2 - - set_icc 0xf 3 - bcclr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcclr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcclr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcclr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcclr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bceqlr.cgs b/sim/testsuite/sim/frv/bceqlr.cgs deleted file mode 100644 index bacabf4..0000000 --- a/sim/testsuite/sim/frv/bceqlr.cgs +++ /dev/null @@ -1,293 +0,0 @@ -# frv testcase for bceqlr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bceqlr -bceqlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bceqlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bceqlr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0x2 2 - bceqlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bceqlr icc3,0,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bceqlr icc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bceqlr icc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bceqlr icc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bceqlr icc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bceqlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bceqlr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0xa 2 - bceqlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bceqlr icc3,0,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bceqlr icc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bceqlr icc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bceqlr icc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bceqlr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bceqlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bceqlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bceqlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bceqlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bceqlr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bceqlr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bceqlr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bceqlr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bceqlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bceqlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bceqlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bceqlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bceqlr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bceqlr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bceqlr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bceqlr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bceqlr icc0,1,0 - - set_icc 0x1 1 - bceqlr icc1,1,1 - - set_icc 0x2 2 - bceqlr icc2,1,2 - - set_icc 0x3 3 - bceqlr icc3,1,3 - - set_icc 0x4 0 - bceqlr icc0,1,0 - - set_icc 0x5 1 - bceqlr icc1,1,1 - - set_icc 0x6 2 - bceqlr icc2,1,2 - - set_icc 0x7 3 - bceqlr icc3,1,3 - - set_icc 0x8 0 - bceqlr icc0,1,0 - - set_icc 0x9 1 - bceqlr icc1,1,1 - - set_icc 0xa 2 - bceqlr icc2,1,2 - - set_icc 0xb 3 - bceqlr icc3,1,3 - - set_icc 0xc 0 - bceqlr icc0,1,0 - - set_icc 0xd 1 - bceqlr icc1,1,1 - - set_icc 0xe 2 - bceqlr icc2,1,2 - - set_icc 0xf 3 - bceqlr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bceqlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bceqlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bceqlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bceqlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bceqlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bceqlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bceqlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bceqlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bceqlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bceqlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bceqlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bceqlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bceqlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bceqlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bceqlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bceqlr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcgelr.cgs b/sim/testsuite/sim/frv/bcgelr.cgs deleted file mode 100644 index 72bd374..0000000 --- a/sim/testsuite/sim/frv/bcgelr.cgs +++ /dev/null @@ -1,293 +0,0 @@ -# frv testcase for bcgelr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcgelr -bcgelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcgelr icc0,0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bcgelr icc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bcgelr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bcgelr icc3,0,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bcgelr icc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bcgelr icc1,0,1 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x6 2 - bcgelr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bcgelr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0x8 0 - bcgelr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bcgelr icc1,0,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bcgelr icc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bcgelr icc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bcgelr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bcgelr icc1,0,1 - - set_spr_addr okf,lr - set_icc 0xe 2 - bcgelr icc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bcgelr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcgelr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcgelr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bcgelr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bcgelr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bcgelr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bcgelr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bcgelr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bcgelr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bcgelr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bcgelr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcgelr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcgelr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bcgelr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bcgelr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bcgelr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bcgelr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcgelr icc0,1,0 - - set_icc 0x1 1 - bcgelr icc1,1,1 - - set_icc 0x2 2 - bcgelr icc2,1,2 - - set_icc 0x3 3 - bcgelr icc3,1,3 - - set_icc 0x4 0 - bcgelr icc0,1,0 - - set_icc 0x5 1 - bcgelr icc1,1,1 - - set_icc 0x6 2 - bcgelr icc2,1,2 - - set_icc 0x7 3 - bcgelr icc3,1,3 - - set_icc 0x8 0 - bcgelr icc0,1,0 - - set_icc 0x9 1 - bcgelr icc1,1,1 - - set_icc 0xa 2 - bcgelr icc2,1,2 - - set_icc 0xb 3 - bcgelr icc3,1,3 - - set_icc 0xc 0 - bcgelr icc0,1,0 - - set_icc 0xd 1 - bcgelr icc1,1,1 - - set_icc 0xe 2 - bcgelr icc2,1,2 - - set_icc 0xf 3 - bcgelr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcgelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcgelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcgelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcgelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcgelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcgelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcgelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcgelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcgelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcgelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcgelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcgelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcgelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcgelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcgelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcgelr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcgtlr.cgs b/sim/testsuite/sim/frv/bcgtlr.cgs deleted file mode 100644 index edffed8..0000000 --- a/sim/testsuite/sim/frv/bcgtlr.cgs +++ /dev/null @@ -1,284 +0,0 @@ -# frv testcase for bcgtlr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcgtlr -bcgtlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcgtlr icc0,0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bcgtlr icc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bcgtlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bcgtlr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0x4 0 - bcgtlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bcgtlr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bcgtlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bcgtlr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0x8 0 - bcgtlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bcgtlr icc1,0,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bcgtlr icc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bcgtlr icc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bcgtlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bcgtlr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bcgtlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bcgtlr icc3,0,3 - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcgtlr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcgtlr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bcgtlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bcgtlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bcgtlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bcgtlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bcgtlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bcgtlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bcgtlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bcgtlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcgtlr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcgtlr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bcgtlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bcgtlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bcgtlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bcgtlr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcgtlr icc0,1,0 - - set_icc 0x1 1 - bcgtlr icc1,1,1 - - set_icc 0x2 2 - bcgtlr icc2,1,2 - - set_icc 0x3 3 - bcgtlr icc3,1,3 - - set_icc 0x4 0 - bcgtlr icc0,1,0 - - set_icc 0x5 1 - bcgtlr icc1,1,1 - - set_icc 0x6 2 - bcgtlr icc2,1,2 - - set_icc 0x7 3 - bcgtlr icc3,1,3 - - set_icc 0x8 0 - bcgtlr icc0,1,0 - - set_icc 0x9 1 - bcgtlr icc1,1,1 - - set_icc 0xa 2 - bcgtlr icc2,1,2 - - set_icc 0xb 3 - bcgtlr icc3,1,3 - - set_icc 0xc 0 - bcgtlr icc0,1,0 - - set_icc 0xd 1 - bcgtlr icc1,1,1 - - set_icc 0xe 2 - bcgtlr icc2,1,2 - - set_icc 0xf 3 - bcgtlr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcgtlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcgtlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcgtlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcgtlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcgtlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcgtlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcgtlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcgtlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcgtlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcgtlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcgtlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcgtlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcgtlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcgtlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcgtlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcgtlr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bchilr.cgs b/sim/testsuite/sim/frv/bchilr.cgs deleted file mode 100644 index ea7e2f4..0000000 --- a/sim/testsuite/sim/frv/bchilr.cgs +++ /dev/null @@ -1,284 +0,0 @@ -# frv testcase for bchilr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bchilr -bchilr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bchilr icc0,0,0 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x1 1 - bchilr icc1,0,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bchilr icc2,0,2 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x3 3 - bchilr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0x4 0 - bchilr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bchilr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bchilr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bchilr icc3,0,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bchilr icc0,0,0 - fail -ok9: - set_spr_addr bad,lr - set_icc 0x9 1 - bchilr icc1,0,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bchilr icc2,0,2 - fail -okb: - set_spr_addr bad,lr - set_icc 0xb 3 - bchilr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0xc 0 - bchilr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bchilr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bchilr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bchilr icc3,0,3 - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bchilr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bchilr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bchilr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bchilr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bchilr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bchilr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bchilr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bchilr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bchilr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bchilr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bchilr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bchilr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bchilr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bchilr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bchilr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bchilr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bchilr icc0,1,0 - - set_icc 0x1 1 - bchilr icc1,1,1 - - set_icc 0x2 2 - bchilr icc2,1,2 - - set_icc 0x3 3 - bchilr icc3,1,3 - - set_icc 0x4 0 - bchilr icc0,1,0 - - set_icc 0x5 1 - bchilr icc1,1,1 - - set_icc 0x6 2 - bchilr icc2,1,2 - - set_icc 0x7 3 - bchilr icc3,1,3 - - set_icc 0x8 0 - bchilr icc0,1,0 - - set_icc 0x9 1 - bchilr icc1,1,1 - - set_icc 0xa 2 - bchilr icc2,1,2 - - set_icc 0xb 3 - bchilr icc3,1,3 - - set_icc 0xc 0 - bchilr icc0,1,0 - - set_icc 0xd 1 - bchilr icc1,1,1 - - set_icc 0xe 2 - bchilr icc2,1,2 - - set_icc 0xf 3 - bchilr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bchilr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bchilr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bchilr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bchilr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bchilr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bchilr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bchilr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bchilr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bchilr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bchilr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bchilr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bchilr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bchilr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bchilr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bchilr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bchilr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bclelr.cgs b/sim/testsuite/sim/frv/bclelr.cgs deleted file mode 100644 index 6668c77..0000000 --- a/sim/testsuite/sim/frv/bclelr.cgs +++ /dev/null @@ -1,301 +0,0 @@ -# frv testcase for bclelr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bclelr -bclelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclelr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bclelr icc1,0,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bclelr icc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bclelr icc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - bclelr icc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bclelr icc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bclelr icc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bclelr icc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - bclelr icc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bclelr icc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bclelr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bclelr icc3,0,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bclelr icc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bclelr icc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bclelr icc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bclelr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclelr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bclelr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bclelr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bclelr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bclelr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bclelr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bclelr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bclelr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bclelr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bclelr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bclelr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bclelr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bclelr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bclelr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bclelr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bclelr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclelr icc0,1,0 - - set_icc 0x1 1 - bclelr icc1,1,1 - - set_icc 0x2 2 - bclelr icc2,1,2 - - set_icc 0x3 3 - bclelr icc3,1,3 - - set_icc 0x4 0 - bclelr icc0,1,0 - - set_icc 0x5 1 - bclelr icc1,1,1 - - set_icc 0x6 2 - bclelr icc2,1,2 - - set_icc 0x7 3 - bclelr icc3,1,3 - - set_icc 0x8 0 - bclelr icc0,1,0 - - set_icc 0x9 1 - bclelr icc1,1,1 - - set_icc 0xa 2 - bclelr icc2,1,2 - - set_icc 0xb 3 - bclelr icc3,1,3 - - set_icc 0xc 0 - bclelr icc0,1,0 - - set_icc 0xd 1 - bclelr icc1,1,1 - - set_icc 0xe 2 - bclelr icc2,1,2 - - set_icc 0xf 3 - bclelr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bclelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bclelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bclelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bclelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bclelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bclelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bclelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bclelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bclelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bclelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bclelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bclelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bclelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bclelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bclelr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bclr.cgs b/sim/testsuite/sim/frv/bclr.cgs deleted file mode 100644 index d36563b..0000000 --- a/sim/testsuite/sim/frv/bclr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bclr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bclr -bclr: - set_spr_addr bad,lr - set_icc 0x0 0 - bclr icc0,0 - - set_spr_addr ok2,lr - set_icc 0x1 1 - bclr icc1,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bclr icc2,2 - - set_spr_addr ok4,lr - set_icc 0x3 3 - bclr icc3,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bclr icc0,0 - - set_spr_addr ok6,lr - set_icc 0x5 1 - bclr icc1,1 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x6 2 - bclr icc2,2 - - set_spr_addr ok8,lr - set_icc 0x7 3 - bclr icc3,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bclr icc0,0 - - set_spr_addr oka,lr - set_icc 0x9 1 - bclr icc1,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bclr icc2,2 - - set_spr_addr okc,lr - set_icc 0xb 3 - bclr icc3,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bclr icc0,0 - - set_spr_addr oke,lr - set_icc 0xd 1 - bclr icc1,1 - fail -oke: - set_spr_addr bad,lr - set_icc 0xe 2 - bclr icc2,2 - - set_spr_addr okg,lr - set_icc 0xf 3 - bclr icc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bclslr.cgs b/sim/testsuite/sim/frv/bclslr.cgs deleted file mode 100644 index 37b91bc..0000000 --- a/sim/testsuite/sim/frv/bclslr.cgs +++ /dev/null @@ -1,301 +0,0 @@ -# frv testcase for bclslr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bclslr -bclslr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclslr icc0,0,0 - - set_spr_addr ok2,lr - set_icc 0x1 1 - bclslr icc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bclslr icc2,0,2 - - set_spr_addr ok4,lr - set_icc 0x3 3 - bclslr icc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - bclslr icc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bclslr icc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bclslr icc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bclslr icc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bclslr icc0,0,0 - - set_spr_addr oka,lr - set_icc 0x9 1 - bclslr icc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bclslr icc2,0,2 - - set_spr_addr okc,lr - set_icc 0xb 3 - bclslr icc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - bclslr icc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bclslr icc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bclslr icc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bclslr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclslr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bclslr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bclslr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bclslr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bclslr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bclslr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bclslr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bclslr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bclslr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bclslr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bclslr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bclslr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bclslr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bclslr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bclslr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bclslr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclslr icc0,1,0 - - set_icc 0x1 1 - bclslr icc1,1,1 - - set_icc 0x2 2 - bclslr icc2,1,2 - - set_icc 0x3 3 - bclslr icc3,1,3 - - set_icc 0x4 0 - bclslr icc0,1,0 - - set_icc 0x5 1 - bclslr icc1,1,1 - - set_icc 0x6 2 - bclslr icc2,1,2 - - set_icc 0x7 3 - bclslr icc3,1,3 - - set_icc 0x8 0 - bclslr icc0,1,0 - - set_icc 0x9 1 - bclslr icc1,1,1 - - set_icc 0xa 2 - bclslr icc2,1,2 - - set_icc 0xb 3 - bclslr icc3,1,3 - - set_icc 0xc 0 - bclslr icc0,1,0 - - set_icc 0xd 1 - bclslr icc1,1,1 - - set_icc 0xe 2 - bclslr icc2,1,2 - - set_icc 0xf 3 - bclslr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclslr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bclslr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bclslr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bclslr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bclslr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bclslr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bclslr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bclslr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bclslr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bclslr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bclslr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bclslr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bclslr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bclslr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bclslr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bclslr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcltlr.cgs b/sim/testsuite/sim/frv/bcltlr.cgs deleted file mode 100644 index 0ba6bfa..0000000 --- a/sim/testsuite/sim/frv/bcltlr.cgs +++ /dev/null @@ -1,292 +0,0 @@ -# frv testcase for bcltlr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcltlr -bcltlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcltlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bcltlr icc1,0,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bcltlr icc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bcltlr icc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bcltlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bcltlr icc1,0,1 - - set_spr_addr ok7,lr - set_icc 0x6 2 - bcltlr icc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bcltlr icc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - bcltlr icc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bcltlr icc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bcltlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bcltlr icc3,0,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bcltlr icc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bcltlr icc1,0,1 - fail -oke: - set_spr_addr bad,lr - set_icc 0xe 2 - bcltlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bcltlr icc3,0,3 - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcltlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bcltlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bcltlr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bcltlr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bcltlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bcltlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bcltlr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bcltlr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bcltlr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bcltlr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bcltlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bcltlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bcltlr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bcltlr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bcltlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bcltlr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcltlr icc0,1,0 - - set_icc 0x1 1 - bcltlr icc1,1,1 - - set_icc 0x2 2 - bcltlr icc2,1,2 - - set_icc 0x3 3 - bcltlr icc3,1,3 - - set_icc 0x4 0 - bcltlr icc0,1,0 - - set_icc 0x5 1 - bcltlr icc1,1,1 - - set_icc 0x6 2 - bcltlr icc2,1,2 - - set_icc 0x7 3 - bcltlr icc3,1,3 - - set_icc 0x8 0 - bcltlr icc0,1,0 - - set_icc 0x9 1 - bcltlr icc1,1,1 - - set_icc 0xa 2 - bcltlr icc2,1,2 - - set_icc 0xb 3 - bcltlr icc3,1,3 - - set_icc 0xc 0 - bcltlr icc0,1,0 - - set_icc 0xd 1 - bcltlr icc1,1,1 - - set_icc 0xe 2 - bcltlr icc2,1,2 - - set_icc 0xf 3 - bcltlr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcltlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcltlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcltlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcltlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcltlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcltlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcltlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcltlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcltlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcltlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcltlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcltlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcltlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcltlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcltlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcltlr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcnclr.cgs b/sim/testsuite/sim/frv/bcnclr.cgs deleted file mode 100644 index 51824a6..0000000 --- a/sim/testsuite/sim/frv/bcnclr.cgs +++ /dev/null @@ -1,293 +0,0 @@ -# frv testcase for bcnclr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcnclr -bcnclr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcnclr icc0,0,0 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x1 1 - bcnclr icc1,0,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bcnclr icc2,0,2 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x3 3 - bcnclr icc3,0,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bcnclr icc0,0,0 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x5 1 - bcnclr icc1,0,1 - - set_spr_addr ok7,lr - set_icc 0x6 2 - bcnclr icc2,0,2 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x7 3 - bcnclr icc3,0,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bcnclr icc0,0,0 - fail -ok9: - set_spr_addr bad,lr - set_icc 0x9 1 - bcnclr icc1,0,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bcnclr icc2,0,2 - fail -okb: - set_spr_addr bad,lr - set_icc 0xb 3 - bcnclr icc3,0,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bcnclr icc0,0,0 - fail -okd: - set_spr_addr bad,lr - set_icc 0xd 1 - bcnclr icc1,0,1 - - set_spr_addr okf,lr - set_icc 0xe 2 - bcnclr icc2,0,2 - fail -okf: - set_spr_addr bad,lr - set_icc 0xf 3 - bcnclr icc3,0,3 - - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcnclr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bcnclr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bcnclr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bcnclr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bcnclr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bcnclr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bcnclr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bcnclr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bcnclr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bcnclr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcnclr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bcnclr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bcnclr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bcnclr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bcnclr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bcnclr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnclr icc0,1,0 - - set_icc 0x1 1 - bcnclr icc1,1,1 - - set_icc 0x2 2 - bcnclr icc2,1,2 - - set_icc 0x3 3 - bcnclr icc3,1,3 - - set_icc 0x4 0 - bcnclr icc0,1,0 - - set_icc 0x5 1 - bcnclr icc1,1,1 - - set_icc 0x6 2 - bcnclr icc2,1,2 - - set_icc 0x7 3 - bcnclr icc3,1,3 - - set_icc 0x8 0 - bcnclr icc0,1,0 - - set_icc 0x9 1 - bcnclr icc1,1,1 - - set_icc 0xa 2 - bcnclr icc2,1,2 - - set_icc 0xb 3 - bcnclr icc3,1,3 - - set_icc 0xc 0 - bcnclr icc0,1,0 - - set_icc 0xd 1 - bcnclr icc1,1,1 - - set_icc 0xe 2 - bcnclr icc2,1,2 - - set_icc 0xf 3 - bcnclr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcnclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcnclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcnclr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcnclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcnclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcnclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcnclr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcnclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcnclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcnclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcnclr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcnclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcnclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcnclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcnclr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcnelr.cgs b/sim/testsuite/sim/frv/bcnelr.cgs deleted file mode 100644 index 55be2d3..0000000 --- a/sim/testsuite/sim/frv/bcnelr.cgs +++ /dev/null @@ -1,292 +0,0 @@ -# frv testcase for bcnelr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcnelr -bcnelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcnelr icc0,0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bcnelr icc1,0,1 - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - bcnelr icc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bcnelr icc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bcnelr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bcnelr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bcnelr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bcnelr icc3,0,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bcnelr icc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bcnelr icc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - bcnelr icc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bcnelr icc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bcnelr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bcnelr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bcnelr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bcnelr icc3,0,3 - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcnelr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcnelr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bcnelr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bcnelr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bcnelr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bcnelr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bcnelr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bcnelr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bcnelr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bcnelr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcnelr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcnelr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bcnelr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bcnelr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bcnelr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bcnelr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnelr icc0,1,0 - - set_icc 0x1 1 - bcnelr icc1,1,1 - - set_icc 0x2 2 - bcnelr icc2,1,2 - - set_icc 0x3 3 - bcnelr icc3,1,3 - - set_icc 0x4 0 - bcnelr icc0,1,0 - - set_icc 0x5 1 - bcnelr icc1,1,1 - - set_icc 0x6 2 - bcnelr icc2,1,2 - - set_icc 0x7 3 - bcnelr icc3,1,3 - - set_icc 0x8 0 - bcnelr icc0,1,0 - - set_icc 0x9 1 - bcnelr icc1,1,1 - - set_icc 0xa 2 - bcnelr icc2,1,2 - - set_icc 0xb 3 - bcnelr icc3,1,3 - - set_icc 0xc 0 - bcnelr icc0,1,0 - - set_icc 0xd 1 - bcnelr icc1,1,1 - - set_icc 0xe 2 - bcnelr icc2,1,2 - - set_icc 0xf 3 - bcnelr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcnelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcnelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcnelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcnelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcnelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcnelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcnelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcnelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcnelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcnelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcnelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcnelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcnelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcnelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcnelr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcnlr.cgs b/sim/testsuite/sim/frv/bcnlr.cgs deleted file mode 100644 index 8ddfcaa..0000000 --- a/sim/testsuite/sim/frv/bcnlr.cgs +++ /dev/null @@ -1,293 +0,0 @@ -# frv testcase for bcnlr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcnlr -bcnlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bcnlr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0x2 2 - bcnlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bcnlr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0x4 0 - bcnlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bcnlr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bcnlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bcnlr icc3,0,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bcnlr icc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bcnlr icc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - bcnlr icc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bcnlr icc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - bcnlr icc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bcnlr icc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bcnlr icc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bcnlr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bcnlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bcnlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bcnlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bcnlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bcnlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bcnlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bcnlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bcnlr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bcnlr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcnlr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcnlr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bcnlr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bcnlr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bcnlr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bcnlr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnlr icc0,1,0 - - set_icc 0x1 1 - bcnlr icc1,1,1 - - set_icc 0x2 2 - bcnlr icc2,1,2 - - set_icc 0x3 3 - bcnlr icc3,1,3 - - set_icc 0x4 0 - bcnlr icc0,1,0 - - set_icc 0x5 1 - bcnlr icc1,1,1 - - set_icc 0x6 2 - bcnlr icc2,1,2 - - set_icc 0x7 3 - bcnlr icc3,1,3 - - set_icc 0x8 0 - bcnlr icc0,1,0 - - set_icc 0x9 1 - bcnlr icc1,1,1 - - set_icc 0xa 2 - bcnlr icc2,1,2 - - set_icc 0xb 3 - bcnlr icc3,1,3 - - set_icc 0xc 0 - bcnlr icc0,1,0 - - set_icc 0xd 1 - bcnlr icc1,1,1 - - set_icc 0xe 2 - bcnlr icc2,1,2 - - set_icc 0xf 3 - bcnlr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcnlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcnlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcnlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcnlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcnlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcnlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcnlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcnlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcnlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcnlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcnlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcnlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcnlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcnlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcnlr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcnolr.cgs b/sim/testsuite/sim/frv/bcnolr.cgs deleted file mode 100644 index 04f0b8d..0000000 --- a/sim/testsuite/sim/frv/bcnolr.cgs +++ /dev/null @@ -1,246 +0,0 @@ -# frv testcase for bcnolr -# mach: all - - .include "testutils.inc" - - start - - .global bcnolr -bcnolr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnolr - - set_icc 0x1 1 - bcnolr - - set_icc 0x2 2 - bcnolr - - set_icc 0x3 3 - bcnolr - - set_icc 0x4 0 - bcnolr - - set_icc 0x5 1 - bcnolr - - set_icc 0x6 2 - bcnolr - - set_icc 0x7 3 - bcnolr - - set_icc 0x8 0 - bcnolr - - set_icc 0x9 1 - bcnolr - - set_icc 0xa 2 - bcnolr - - set_icc 0xb 3 - bcnolr - - set_icc 0xc 0 - bcnolr - - set_icc 0xd 1 - bcnolr - - set_icc 0xe 2 - bcnolr - - set_icc 0xf 3 - bcnolr - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcnolr - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnolr - - set_icc 0x1 1 - bcnolr - - set_icc 0x2 2 - bcnolr - - set_icc 0x3 3 - bcnolr - - set_icc 0x4 0 - bcnolr - - set_icc 0x5 1 - bcnolr - - set_icc 0x6 2 - bcnolr - - set_icc 0x7 3 - bcnolr - - set_icc 0x8 0 - bcnolr - - set_icc 0x9 1 - bcnolr - - set_icc 0xa 2 - bcnolr - - set_icc 0xb 3 - bcnolr - - set_icc 0xc 0 - bcnolr - - set_icc 0xd 1 - bcnolr - - set_icc 0xe 2 - bcnolr - - set_icc 0xf 3 - bcnolr - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcnolr - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcnvlr.cgs b/sim/testsuite/sim/frv/bcnvlr.cgs deleted file mode 100644 index 2451557..0000000 --- a/sim/testsuite/sim/frv/bcnvlr.cgs +++ /dev/null @@ -1,292 +0,0 @@ -# frv testcase for bcnvlr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcnvlr -bcnvlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcnvlr icc0,0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bcnvlr icc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bcnvlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bcnvlr icc3,0,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bcnvlr icc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bcnvlr icc1,0,1 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x6 2 - bcnvlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bcnvlr icc3,0,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bcnvlr icc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bcnvlr icc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bcnvlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bcnvlr icc3,0,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bcnvlr icc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bcnvlr icc1,0,1 - fail -oke: - set_spr_addr bad,lr - set_icc 0xe 2 - bcnvlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bcnvlr icc3,0,3 - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcnvlr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcnvlr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bcnvlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bcnvlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bcnvlr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bcnvlr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bcnvlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bcnvlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bcnvlr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bcnvlr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bcnvlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bcnvlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bcnvlr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bcnvlr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bcnvlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bcnvlr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnvlr icc0,1,0 - - set_icc 0x1 1 - bcnvlr icc1,1,1 - - set_icc 0x2 2 - bcnvlr icc2,1,2 - - set_icc 0x3 3 - bcnvlr icc3,1,3 - - set_icc 0x4 0 - bcnvlr icc0,1,0 - - set_icc 0x5 1 - bcnvlr icc1,1,1 - - set_icc 0x6 2 - bcnvlr icc2,1,2 - - set_icc 0x7 3 - bcnvlr icc3,1,3 - - set_icc 0x8 0 - bcnvlr icc0,1,0 - - set_icc 0x9 1 - bcnvlr icc1,1,1 - - set_icc 0xa 2 - bcnvlr icc2,1,2 - - set_icc 0xb 3 - bcnvlr icc3,1,3 - - set_icc 0xc 0 - bcnvlr icc0,1,0 - - set_icc 0xd 1 - bcnvlr icc1,1,1 - - set_icc 0xe 2 - bcnvlr icc2,1,2 - - set_icc 0xf 3 - bcnvlr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcnvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcnvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcnvlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcnvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcnvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcnvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcnvlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcnvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcnvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcnvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcnvlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcnvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcnvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcnvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcnvlr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcplr.cgs b/sim/testsuite/sim/frv/bcplr.cgs deleted file mode 100644 index fef3ccb..0000000 --- a/sim/testsuite/sim/frv/bcplr.cgs +++ /dev/null @@ -1,292 +0,0 @@ -# frv testcase for bcplr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcplr -bcplr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcplr icc0,0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bcplr icc1,0,1 - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - bcplr icc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bcplr icc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - bcplr icc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bcplr icc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bcplr icc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bcplr icc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bcplr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bcplr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0xa 2 - bcplr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bcplr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0xc 0 - bcplr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bcplr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bcplr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bcplr icc3,0,3 - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcplr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcplr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bcplr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bcplr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bcplr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bcplr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bcplr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bcplr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bcplr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bcplr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bcplr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bcplr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bcplr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bcplr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bcplr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bcplr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcplr icc0,1,0 - - set_icc 0x1 1 - bcplr icc1,1,1 - - set_icc 0x2 2 - bcplr icc2,1,2 - - set_icc 0x3 3 - bcplr icc3,1,3 - - set_icc 0x4 0 - bcplr icc0,1,0 - - set_icc 0x5 1 - bcplr icc1,1,1 - - set_icc 0x6 2 - bcplr icc2,1,2 - - set_icc 0x7 3 - bcplr icc3,1,3 - - set_icc 0x8 0 - bcplr icc0,1,0 - - set_icc 0x9 1 - bcplr icc1,1,1 - - set_icc 0xa 2 - bcplr icc2,1,2 - - set_icc 0xb 3 - bcplr icc3,1,3 - - set_icc 0xc 0 - bcplr icc0,1,0 - - set_icc 0xd 1 - bcplr icc1,1,1 - - set_icc 0xe 2 - bcplr icc2,1,2 - - set_icc 0xf 3 - bcplr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcplr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcplr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcplr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcplr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcplr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcplr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcplr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcplr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcplr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcplr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcplr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcplr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcplr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcplr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcplr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcplr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcralr.cgs b/sim/testsuite/sim/frv/bcralr.cgs deleted file mode 100644 index 612363d..0000000 --- a/sim/testsuite/sim/frv/bcralr.cgs +++ /dev/null @@ -1,309 +0,0 @@ -# frv testcase for bcralr $ccond -# mach: all - - .include "testutils.inc" - - start - - .global bcralr -bcralr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcralr 0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bcralr 0 - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - bcralr 0 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bcralr 0 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - bcralr 0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bcralr 0 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bcralr 0 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bcralr 0 - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - bcralr 0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bcralr 0 - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - bcralr 0 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bcralr 0 - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - bcralr 0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bcralr 0 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bcralr 0 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bcralr 0 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcralr 1 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcralr 1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bcralr 1 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bcralr 1 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bcralr 1 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bcralr 1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bcralr 1 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bcralr 1 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bcralr 1 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bcralr 1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcralr 1 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcralr 1 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bcralr 1 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bcralr 1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bcralr 1 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bcralr 1 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcralr 1 - - set_icc 0x1 1 - bcralr 1 - - set_icc 0x2 2 - bcralr 1 - - set_icc 0x3 3 - bcralr 1 - - set_icc 0x4 0 - bcralr 1 - - set_icc 0x5 1 - bcralr 1 - - set_icc 0x6 2 - bcralr 1 - - set_icc 0x7 3 - bcralr 1 - - set_icc 0x8 0 - bcralr 1 - - set_icc 0x9 1 - bcralr 1 - - set_icc 0xa 2 - bcralr 1 - - set_icc 0xb 3 - bcralr 1 - - set_icc 0xc 0 - bcralr 1 - - set_icc 0xd 1 - bcralr 1 - - set_icc 0xe 2 - bcralr 1 - - set_icc 0xf 3 - bcralr 1 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcralr 0 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bctrlr.cgs b/sim/testsuite/sim/frv/bctrlr.cgs deleted file mode 100644 index b00cb97..0000000 --- a/sim/testsuite/sim/frv/bctrlr.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for bctrlr $ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bctrlr -bctrlr: - set_spr_addr bad,lr - set_spr_immed 1,lcr - bctrlr 0,0 - - set_spr_addr ok1,lr - set_spr_immed 2,lcr - bctrlr 0,0 - fail -ok1: - set_spr_addr bad,lr - set_spr_immed 2,lcr - bctrlr 1,0 - - set_spr_addr ok2,lr - bctrlr 1,0 - fail -ok2: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcvlr.cgs b/sim/testsuite/sim/frv/bcvlr.cgs deleted file mode 100644 index b25d646..0000000 --- a/sim/testsuite/sim/frv/bcvlr.cgs +++ /dev/null @@ -1,293 +0,0 @@ -# frv testcase for bcvlr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcvlr -bcvlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcvlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bcvlr icc1,0,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bcvlr icc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bcvlr icc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bcvlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bcvlr icc1,0,1 - - set_spr_addr ok7,lr - set_icc 0x6 2 - bcvlr icc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bcvlr icc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bcvlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bcvlr icc1,0,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bcvlr icc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bcvlr icc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bcvlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bcvlr icc1,0,1 - - set_spr_addr okf,lr - set_icc 0xe 2 - bcvlr icc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bcvlr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcvlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bcvlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bcvlr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bcvlr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bcvlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bcvlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bcvlr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bcvlr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bcvlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bcvlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcvlr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcvlr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bcvlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bcvlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bcvlr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bcvlr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcvlr icc0,1,0 - - set_icc 0x1 1 - bcvlr icc1,1,1 - - set_icc 0x2 2 - bcvlr icc2,1,2 - - set_icc 0x3 3 - bcvlr icc3,1,3 - - set_icc 0x4 0 - bcvlr icc0,1,0 - - set_icc 0x5 1 - bcvlr icc1,1,1 - - set_icc 0x6 2 - bcvlr icc2,1,2 - - set_icc 0x7 3 - bcvlr icc3,1,3 - - set_icc 0x8 0 - bcvlr icc0,1,0 - - set_icc 0x9 1 - bcvlr icc1,1,1 - - set_icc 0xa 2 - bcvlr icc2,1,2 - - set_icc 0xb 3 - bcvlr icc3,1,3 - - set_icc 0xc 0 - bcvlr icc0,1,0 - - set_icc 0xd 1 - bcvlr icc1,1,1 - - set_icc 0xe 2 - bcvlr icc2,1,2 - - set_icc 0xf 3 - bcvlr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcvlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcvlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcvlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcvlr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/beq.cgs b/sim/testsuite/sim/frv/beq.cgs deleted file mode 100644 index b3706dc..0000000 --- a/sim/testsuite/sim/frv/beq.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for beq $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global beq -beq: - set_icc 0x0 0 - beq icc0,0,bad - set_icc 0x1 1 - beq icc1,1,bad - set_icc 0x2 2 - beq icc2,2,bad - set_icc 0x3 3 - beq icc3,3,bad - set_icc 0x4 0 - beq icc0,0,ok1 - fail -ok1: - set_icc 0x5 1 - beq icc1,1,ok2 - fail -ok2: - set_icc 0x6 2 - beq icc2,2,ok3 - fail -ok3: - set_icc 0x7 3 - beq icc3,3,ok4 - fail -ok4: - set_icc 0x8 0 - beq icc0,0,bad - set_icc 0x9 1 - beq icc1,1,bad - set_icc 0xa 2 - beq icc2,2,bad - set_icc 0xb 3 - beq icc3,3,bad - set_icc 0xc 0 - beq icc0,0,ok5 - fail -ok5: - set_icc 0xd 1 - beq icc1,1,ok6 - fail -ok6: - set_icc 0xe 2 - beq icc2,2,ok7 - fail -ok7: - set_icc 0xf 3 - beq icc3,3,ok8 - fail -ok8: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/beqlr.cgs b/sim/testsuite/sim/frv/beqlr.cgs deleted file mode 100644 index 772b9fa..0000000 --- a/sim/testsuite/sim/frv/beqlr.cgs +++ /dev/null @@ -1,71 +0,0 @@ -# frv testcase for beqlr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global beqlr -beqlr: - set_spr_addr bad,lr - set_icc 0x0 0 - beqlr icc0,0 - set_icc 0x1 1 - beqlr icc1,1 - set_icc 0x2 2 - beqlr icc2,2 - set_icc 0x3 3 - beqlr icc3,3 - set_spr_addr ok1,lr - set_icc 0x4 0 - beqlr icc0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x5 1 - beqlr icc1,1 - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x6 2 - beqlr icc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x7 3 - beqlr icc3,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x8 0 - beqlr icc0,0 - set_icc 0x9 1 - beqlr icc1,1 - set_icc 0xa 2 - beqlr icc2,2 - set_icc 0xb 3 - beqlr icc3,3 - set_spr_addr ok5,lr - set_icc 0xc 0 - beqlr icc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0xd 1 - beqlr icc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0xe 2 - beqlr icc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0xf 3 - beqlr icc3,3 - fail -ok8: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bge.cgs b/sim/testsuite/sim/frv/bge.cgs deleted file mode 100644 index 7ebead7..0000000 --- a/sim/testsuite/sim/frv/bge.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bge $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bge -bge: - set_icc 0x0 0 - bge icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bge icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bge icc2,2,bad - set_icc 0x3 3 - bge icc3,3,bad - set_icc 0x4 0 - bge icc0,0,ok5 - fail -ok5: - set_icc 0x5 1 - bge icc1,1,ok6 - fail -ok6: - set_icc 0x6 2 - bge icc2,2,bad - set_icc 0x7 3 - bge icc3,3,bad - set_icc 0x8 0 - bge icc0,0,bad - set_icc 0x9 1 - bge icc1,1,bad - set_icc 0xa 2 - bge icc2,2,okb - fail -okb: - set_icc 0xb 3 - bge icc3,3,okc - fail -okc: - set_icc 0xc 0 - bge icc0,0,bad - set_icc 0xd 1 - bge icc1,1,bad - set_icc 0xe 2 - bge icc2,2,okf - fail -okf: - set_icc 0xf 3 - bge icc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bgelr.cgs b/sim/testsuite/sim/frv/bgelr.cgs deleted file mode 100644 index 806770a..0000000 --- a/sim/testsuite/sim/frv/bgelr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bgelr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bgelr -bgelr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bgelr icc0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bgelr icc1,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bgelr icc2,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bgelr icc3,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bgelr icc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bgelr icc1,1 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x6 2 - bgelr icc2,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bgelr icc3,3 - - set_spr_addr bad,lr - set_icc 0x8 0 - bgelr icc0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bgelr icc1,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bgelr icc2,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bgelr icc3,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bgelr icc0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bgelr icc1,1 - - set_spr_addr okf,lr - set_icc 0xe 2 - bgelr icc2,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bgelr icc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bgt.cgs b/sim/testsuite/sim/frv/bgt.cgs deleted file mode 100644 index 98b1b17..0000000 --- a/sim/testsuite/sim/frv/bgt.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for bgt $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bgt -bgt: - set_icc 0x0 0 - bgt icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bgt icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bgt icc2,2,bad - set_icc 0x3 3 - bgt icc3,3,bad - set_icc 0x4 0 - bgt icc0,0,bad - set_icc 0x5 1 - bgt icc1,1,bad - set_icc 0x6 2 - bgt icc2,2,bad - set_icc 0x7 3 - bgt icc3,3,bad - set_icc 0x8 0 - bgt icc0,0,bad - set_icc 0x9 1 - bgt icc1,1,bad - set_icc 0xa 2 - bgt icc2,2,okb - fail -okb: - set_icc 0xb 3 - bgt icc3,3,okc - fail -okc: - set_icc 0xc 0 - bgt icc0,0,bad - set_icc 0xd 1 - bgt icc1,1,bad - set_icc 0xe 2 - bgt icc2,2,bad - set_icc 0xf 3 - bgt icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bgtlr.cgs b/sim/testsuite/sim/frv/bgtlr.cgs deleted file mode 100644 index ad44a2c..0000000 --- a/sim/testsuite/sim/frv/bgtlr.cgs +++ /dev/null @@ -1,80 +0,0 @@ -# frv testcase for bgtlr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bgtlr -bgtlr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bgtlr icc0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bgtlr icc1,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bgtlr icc2,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bgtlr icc3,3 - - set_spr_addr bad,lr - set_icc 0x4 0 - bgtlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bgtlr icc1,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bgtlr icc2,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bgtlr icc3,3 - - set_spr_addr bad,lr - set_icc 0x8 0 - bgtlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bgtlr icc1,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bgtlr icc2,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bgtlr icc3,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bgtlr icc0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bgtlr icc1,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bgtlr icc2,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bgtlr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bhi.cgs b/sim/testsuite/sim/frv/bhi.cgs deleted file mode 100644 index a92c0c0..0000000 --- a/sim/testsuite/sim/frv/bhi.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for bhi $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bhi -bhi: - set_icc 0x0 0 - bhi icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bhi icc1,1,bad - set_icc 0x2 2 - bhi icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - bhi icc3,3,bad - set_icc 0x4 0 - bhi icc0,0,bad - set_icc 0x5 1 - bhi icc1,1,bad - set_icc 0x6 2 - bhi icc2,2,bad - set_icc 0x7 3 - bhi icc3,3,bad - set_icc 0x8 0 - bhi icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - bhi icc1,1,bad - set_icc 0xa 2 - bhi icc2,2,okb - fail -okb: - set_icc 0xb 3 - bhi icc3,3,bad - set_icc 0xc 0 - bhi icc0,0,bad - set_icc 0xd 1 - bhi icc1,1,bad - set_icc 0xe 2 - bhi icc2,2,bad - set_icc 0xf 3 - bhi icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bhilr.cgs b/sim/testsuite/sim/frv/bhilr.cgs deleted file mode 100644 index 927643b..0000000 --- a/sim/testsuite/sim/frv/bhilr.cgs +++ /dev/null @@ -1,80 +0,0 @@ -# frv testcase for bhilr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bhilr -bhilr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bhilr icc0,0 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x1 1 - bhilr icc1,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bhilr icc2,2 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x3 3 - bhilr icc3,3 - - set_spr_addr bad,lr - set_icc 0x4 0 - bhilr icc0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bhilr icc1,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bhilr icc2,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bhilr icc3,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bhilr icc0,0 - fail -ok9: - set_spr_addr bad,lr - set_icc 0x9 1 - bhilr icc1,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bhilr icc2,2 - fail -okb: - set_spr_addr bad,lr - set_icc 0xb 3 - bhilr icc3,3 - - set_spr_addr bad,lr - set_icc 0xc 0 - bhilr icc0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bhilr icc1,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bhilr icc2,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bhilr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ble.cgs b/sim/testsuite/sim/frv/ble.cgs deleted file mode 100644 index c358766..0000000 --- a/sim/testsuite/sim/frv/ble.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for ble $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global ble -ble: - set_icc 0x0 0 - ble icc0,0,bad - set_icc 0x1 1 - ble icc1,1,bad - set_icc 0x2 2 - ble icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - ble icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - ble icc0,0,ok5 - fail -ok5: - set_icc 0x5 1 - ble icc1,1,ok6 - fail -ok6: - set_icc 0x6 2 - ble icc2,2,ok7 - fail -ok7: - set_icc 0x7 3 - ble icc3,3,ok8 - fail -ok8: - set_icc 0x8 0 - ble icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - ble icc1,1,oka - fail -oka: - set_icc 0xa 2 - ble icc2,2,bad - set_icc 0xb 3 - ble icc3,3,bad - set_icc 0xc 0 - ble icc0,0,okd - fail -okd: - set_icc 0xd 1 - ble icc1,1,oke - fail -oke: - set_icc 0xe 2 - ble icc2,2,okf - fail -okf: - set_icc 0xf 3 - ble icc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/blelr.cgs b/sim/testsuite/sim/frv/blelr.cgs deleted file mode 100644 index dbb8e84..0000000 --- a/sim/testsuite/sim/frv/blelr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for blelr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global blelr -blelr: - set_spr_addr bad,lr - set_icc 0x0 0 - blelr icc0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - blelr icc1,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - blelr icc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - blelr icc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - blelr icc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - blelr icc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - blelr icc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - blelr icc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - blelr icc0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - blelr icc1,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - blelr icc2,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - blelr icc3,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - blelr icc0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - blelr icc1,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - blelr icc2,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - blelr icc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bls.cgs b/sim/testsuite/sim/frv/bls.cgs deleted file mode 100644 index e868de6..0000000 --- a/sim/testsuite/sim/frv/bls.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for bls $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bls -bls: - set_icc 0x0 0 - bls icc0,0,bad - set_icc 0x1 1 - bls icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bls icc2,2,bad - set_icc 0x3 3 - bls icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - bls icc0,0,ok5 - fail -ok5: - set_icc 0x5 1 - bls icc1,1,ok6 - fail -ok6: - set_icc 0x6 2 - bls icc2,2,ok7 - fail -ok7: - set_icc 0x7 3 - bls icc3,3,ok8 - fail -ok8: - set_icc 0x8 0 - bls icc0,0,bad - set_icc 0x9 1 - bls icc1,1,oka - fail -oka: - set_icc 0xa 2 - bls icc2,2,bad - set_icc 0xb 3 - bls icc3,3,okc - fail -okc: - set_icc 0xc 0 - bls icc0,0,okd - fail -okd: - set_icc 0xd 1 - bls icc1,1,oke - fail -oke: - set_icc 0xe 2 - bls icc2,2,okf - fail -okf: - set_icc 0xf 3 - bls icc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/blslr.cgs b/sim/testsuite/sim/frv/blslr.cgs deleted file mode 100644 index 5166c52..0000000 --- a/sim/testsuite/sim/frv/blslr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for blslr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global blslr -blslr: - set_spr_addr bad,lr - set_icc 0x0 0 - blslr icc0,0 - - set_spr_addr ok2,lr - set_icc 0x1 1 - blslr icc1,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - blslr icc2,2 - - set_spr_addr ok4,lr - set_icc 0x3 3 - blslr icc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - blslr icc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - blslr icc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - blslr icc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - blslr icc3,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - blslr icc0,0 - - set_spr_addr oka,lr - set_icc 0x9 1 - blslr icc1,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - blslr icc2,2 - - set_spr_addr okc,lr - set_icc 0xb 3 - blslr icc3,3 - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - blslr icc0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - blslr icc1,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - blslr icc2,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - blslr icc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/blt.cgs b/sim/testsuite/sim/frv/blt.cgs deleted file mode 100644 index 639f971..0000000 --- a/sim/testsuite/sim/frv/blt.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for blt $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global blt -blt: - set_icc 0x0 0 - blt icc0,0,bad - set_icc 0x1 1 - blt icc1,1,bad - set_icc 0x2 2 - blt icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - blt icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - blt icc0,0,bad - set_icc 0x5 1 - blt icc1,1,bad - set_icc 0x6 2 - blt icc2,2,ok7 - fail -ok7: - set_icc 0x7 3 - blt icc3,3,ok8 - fail -ok8: - set_icc 0x8 0 - blt icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - blt icc1,1,oka - fail -oka: - set_icc 0xa 2 - blt icc2,2,bad - set_icc 0xb 3 - blt icc3,3,bad - set_icc 0xc 0 - blt icc0,0,okd - fail -okd: - set_icc 0xd 1 - blt icc1,1,oke - fail -oke: - set_icc 0xe 2 - blt icc2,2,bad - set_icc 0xf 3 - blt icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bltlr.cgs b/sim/testsuite/sim/frv/bltlr.cgs deleted file mode 100644 index fcf04b5..0000000 --- a/sim/testsuite/sim/frv/bltlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bltlr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bltlr -bltlr: - set_spr_addr bad,lr - set_icc 0x0 0 - bltlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bltlr icc1,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bltlr icc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bltlr icc3,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bltlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bltlr icc1,1 - - set_spr_addr ok7,lr - set_icc 0x6 2 - bltlr icc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bltlr icc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - bltlr icc0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bltlr icc1,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bltlr icc2,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bltlr icc3,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bltlr icc0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bltlr icc1,1 - fail -oke: - set_spr_addr bad,lr - set_icc 0xe 2 - bltlr icc2,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bltlr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bn.cgs b/sim/testsuite/sim/frv/bn.cgs deleted file mode 100644 index e5ff397..0000000 --- a/sim/testsuite/sim/frv/bn.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bn $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bn -bn: - set_icc 0x0 0 - bn icc0,0,bad - set_icc 0x1 1 - bn icc1,1,bad - set_icc 0x2 2 - bn icc2,2,bad - set_icc 0x3 3 - bn icc3,3,bad - set_icc 0x4 0 - bn icc0,0,bad - set_icc 0x5 1 - bn icc1,1,bad - set_icc 0x6 2 - bn icc2,2,bad - set_icc 0x7 3 - bn icc3,3,bad - set_icc 0x8 0 - bn icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - bn icc1,1,oka - fail -oka: - set_icc 0xa 2 - bn icc2,2,okb - fail -okb: - set_icc 0xb 3 - bn icc3,3,okc - fail -okc: - set_icc 0xc 0 - bn icc0,0,okd - fail -okd: - set_icc 0xd 1 - bn icc1,1,oke - fail -oke: - set_icc 0xe 2 - bn icc2,2,okf - fail -okf: - set_icc 0xf 3 - bn icc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnc.cgs b/sim/testsuite/sim/frv/bnc.cgs deleted file mode 100644 index 6f14e6c..0000000 --- a/sim/testsuite/sim/frv/bnc.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bnc $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bnc -bnc: - set_icc 0x0 0 - bnc icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bnc icc1,1,bad - set_icc 0x2 2 - bnc icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - bnc icc3,3,bad - set_icc 0x4 0 - bnc icc0,0,ok5 - fail -ok5: - set_icc 0x5 1 - bnc icc1,1,bad - set_icc 0x6 2 - bnc icc2,2,ok7 - fail -ok7: - set_icc 0x7 3 - bnc icc3,3,bad - set_icc 0x8 0 - bnc icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - bnc icc1,1,bad - set_icc 0xa 2 - bnc icc2,2,okb - fail -okb: - set_icc 0xb 3 - bnc icc3,3,bad - set_icc 0xc 0 - bnc icc0,0,okd - fail -okd: - set_icc 0xd 1 - bnc icc1,1,bad - set_icc 0xe 2 - bnc icc2,2,okf - fail -okf: - set_icc 0xf 3 - bnc icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnclr.cgs b/sim/testsuite/sim/frv/bnclr.cgs deleted file mode 100644 index d24f8eb..0000000 --- a/sim/testsuite/sim/frv/bnclr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bnclr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bnclr -bnclr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bnclr icc0,0 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x1 1 - bnclr icc1,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bnclr icc2,2 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x3 3 - bnclr icc3,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bnclr icc0,0 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x5 1 - bnclr icc1,1 - - set_spr_addr ok7,lr - set_icc 0x6 2 - bnclr icc2,2 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x7 3 - bnclr icc3,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bnclr icc0,0 - fail -ok9: - set_spr_addr bad,lr - set_icc 0x9 1 - bnclr icc1,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bnclr icc2,2 - fail -okb: - set_spr_addr bad,lr - set_icc 0xb 3 - bnclr icc3,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bnclr icc0,0 - fail -okd: - set_spr_addr bad,lr - set_icc 0xd 1 - bnclr icc1,1 - - set_spr_addr okf,lr - set_icc 0xe 2 - bnclr icc2,2 - fail -okf: - set_spr_addr bad,lr - set_icc 0xf 3 - bnclr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bne.cgs b/sim/testsuite/sim/frv/bne.cgs deleted file mode 100644 index f0f0894..0000000 --- a/sim/testsuite/sim/frv/bne.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bne $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bne -bne: - set_icc 0x0 0 - bne icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bne icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bne icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - bne icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - bne icc0,0,bad - set_icc 0x5 1 - bne icc1,1,bad - set_icc 0x6 2 - bne icc2,2,bad - set_icc 0x7 3 - bne icc3,3,bad - set_icc 0x8 0 - bne icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - bne icc1,1,oka - fail -oka: - set_icc 0xa 2 - bne icc2,2,okb - fail -okb: - set_icc 0xb 3 - bne icc3,3,okc - fail -okc: - set_icc 0xc 0 - bne icc0,0,bad - set_icc 0xd 1 - bne icc1,1,bad - set_icc 0xe 2 - bne icc2,2,bad - set_icc 0xf 3 - bne icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnelr.cgs b/sim/testsuite/sim/frv/bnelr.cgs deleted file mode 100644 index 7a477b8..0000000 --- a/sim/testsuite/sim/frv/bnelr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bnelr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bnelr -bnelr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bnelr icc0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bnelr icc1,1 - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - bnelr icc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bnelr icc3,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bnelr icc0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bnelr icc1,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bnelr icc2,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bnelr icc3,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bnelr icc0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bnelr icc1,1 - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - bnelr icc2,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bnelr icc3,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bnelr icc0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bnelr icc1,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bnelr icc2,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bnelr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnlr.cgs b/sim/testsuite/sim/frv/bnlr.cgs deleted file mode 100644 index de32b05..0000000 --- a/sim/testsuite/sim/frv/bnlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bnlr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bnlr -bnlr: - set_spr_addr bad,lr - set_icc 0x0 0 - bnlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bnlr icc1,1 - - set_spr_addr bad,lr - set_icc 0x2 2 - bnlr icc2,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bnlr icc3,3 - - set_spr_addr bad,lr - set_icc 0x4 0 - bnlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bnlr icc1,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bnlr icc2,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bnlr icc3,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bnlr icc0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bnlr icc1,1 - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - bnlr icc2,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bnlr icc3,3 - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - bnlr icc0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bnlr icc1,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bnlr icc2,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bnlr icc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bno.cgs b/sim/testsuite/sim/frv/bno.cgs deleted file mode 100644 index 005e422..0000000 --- a/sim/testsuite/sim/frv/bno.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for bno $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bno -bno: - set_icc 0x0 0 - bno - set_icc 0x1 1 - bno - set_icc 0x2 2 - bno - set_icc 0x3 3 - bno - set_icc 0x4 0 - bno - set_icc 0x5 1 - bno - set_icc 0x6 2 - bno - set_icc 0x7 3 - bno - set_icc 0x8 0 - bno - set_icc 0x9 1 - bno - set_icc 0xa 2 - bno - set_icc 0xb 3 - bno - set_icc 0xc 0 - bno - set_icc 0xd 1 - bno - set_icc 0xe 2 - bno - set_icc 0xf 3 - bno - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnolr.cgs b/sim/testsuite/sim/frv/bnolr.cgs deleted file mode 100644 index ae69f6f..0000000 --- a/sim/testsuite/sim/frv/bnolr.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bnolr -# mach: all - - .include "testutils.inc" - - start - - .global bnolr -bnolr: - set_spr_addr bad,lr - set_icc 0x0 0 - bnolr - - set_icc 0x1 1 - bnolr - - set_icc 0x2 2 - bnolr - - set_icc 0x3 3 - bnolr - - set_icc 0x4 0 - bnolr - - set_icc 0x5 1 - bnolr - - set_icc 0x6 2 - bnolr - - set_icc 0x7 3 - bnolr - - set_icc 0x8 0 - bnolr - - set_icc 0x9 1 - bnolr - - set_icc 0xa 2 - bnolr - - set_icc 0xb 3 - bnolr - - set_icc 0xc 0 - bnolr - - set_icc 0xd 1 - bnolr - - set_icc 0xe 2 - bnolr - - set_icc 0xf 3 - bnolr - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnv.cgs b/sim/testsuite/sim/frv/bnv.cgs deleted file mode 100644 index 29ec57a..0000000 --- a/sim/testsuite/sim/frv/bnv.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bnv $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bnv -bnv: - set_icc 0x0 0 - bnv icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bnv icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bnv icc2,2,bad - set_icc 0x3 3 - bnv icc3,3,bad - set_icc 0x4 0 - bnv icc0,0,ok5 - fail -ok5: - set_icc 0x5 1 - bnv icc1,1,ok6 - fail -ok6: - set_icc 0x6 2 - bnv icc2,2,bad - set_icc 0x7 3 - bnv icc3,3,bad - set_icc 0x8 0 - bnv icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - bnv icc1,1,oka - fail -oka: - set_icc 0xa 2 - bnv icc2,2,bad - set_icc 0xb 3 - bnv icc3,3,bad - set_icc 0xc 0 - bnv icc0,0,okd - fail -okd: - set_icc 0xd 1 - bnv icc1,1,oke - fail -oke: - set_icc 0xe 2 - bnv icc2,2,bad - set_icc 0xf 3 - bnv icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnvlr.cgs b/sim/testsuite/sim/frv/bnvlr.cgs deleted file mode 100644 index de40f9c..0000000 --- a/sim/testsuite/sim/frv/bnvlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bnvlr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bnvlr -bnvlr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bnvlr icc0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bnvlr icc1,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bnvlr icc2,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bnvlr icc3,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bnvlr icc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bnvlr icc1,1 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x6 2 - bnvlr icc2,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bnvlr icc3,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bnvlr icc0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bnvlr icc1,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bnvlr icc2,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bnvlr icc3,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bnvlr icc0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bnvlr icc1,1 - fail -oke: - set_spr_addr bad,lr - set_icc 0xe 2 - bnvlr icc2,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bnvlr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bp.cgs b/sim/testsuite/sim/frv/bp.cgs deleted file mode 100644 index 0bc1e7f..0000000 --- a/sim/testsuite/sim/frv/bp.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bp $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bp -bp: - set_icc 0x0 0 - bp icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bp icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bp icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - bp icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - bp icc0,0,ok5 - fail -ok5: - set_icc 0x5 1 - bp icc1,1,ok6 - fail -ok6: - set_icc 0x6 2 - bp icc2,2,ok7 - fail -ok7: - set_icc 0x7 3 - bp icc3,3,ok8 - fail -ok8: - set_icc 0x8 0 - bp icc0,0,bad - set_icc 0x9 1 - bp icc1,1,bad - set_icc 0xa 2 - bp icc2,2,bad - set_icc 0xb 3 - bp icc3,3,bad - set_icc 0xc 0 - bp icc0,0,bad - set_icc 0xd 1 - bp icc1,1,bad - set_icc 0xe 2 - bp icc2,2,bad - set_icc 0xf 3 - bp icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bplr.cgs b/sim/testsuite/sim/frv/bplr.cgs deleted file mode 100644 index 2bd9bb6..0000000 --- a/sim/testsuite/sim/frv/bplr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bplr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bplr -bplr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bplr icc0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bplr icc1,1 - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - bplr icc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bplr icc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - bplr icc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bplr icc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bplr icc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bplr icc3,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bplr icc0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bplr icc1,1 - - set_spr_addr bad,lr - set_icc 0xa 2 - bplr icc2,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bplr icc3,3 - - set_spr_addr bad,lr - set_icc 0xc 0 - bplr icc0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bplr icc1,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bplr icc2,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bplr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bra.cgs b/sim/testsuite/sim/frv/bra.cgs deleted file mode 100644 index e6b312b..0000000 --- a/sim/testsuite/sim/frv/bra.cgs +++ /dev/null @@ -1,75 +0,0 @@ -# frv testcase for bra $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bra -bra: - set_icc 0x0 0 - bra ok1 - fail -ok1: - set_icc 0x1 1 - bra ok2 - fail -ok2: - set_icc 0x2 2 - bra ok3 - fail -ok3: - set_icc 0x3 3 - bra ok4 - fail -ok4: - set_icc 0x4 0 - bra ok5 - fail -ok5: - set_icc 0x5 1 - bra ok6 - fail -ok6: - set_icc 0x6 2 - bra ok7 - fail -ok7: - set_icc 0x7 3 - bra ok8 - fail -ok8: - set_icc 0x8 0 - bra ok9 - fail -ok9: - set_icc 0x9 1 - bra oka - fail -oka: - set_icc 0xa 2 - bra okb - fail -okb: - set_icc 0xb 3 - bra okc - fail -okc: - set_icc 0xc 0 - bra okd - fail -okd: - set_icc 0xd 1 - bra oke - fail -oke: - set_icc 0xe 2 - bra okf - fail -okf: - set_icc 0xf 3 - bra okg - fail -okg: - - pass diff --git a/sim/testsuite/sim/frv/bralr.cgs b/sim/testsuite/sim/frv/bralr.cgs deleted file mode 100644 index 3928209..0000000 --- a/sim/testsuite/sim/frv/bralr.cgs +++ /dev/null @@ -1,91 +0,0 @@ -# frv testcase for bralr -# mach: all - - .include "testutils.inc" - - start - - .global bralr -bralr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bralr - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bralr - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - bralr - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bralr - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - bralr - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bralr - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bralr - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bralr - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - bralr - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bralr - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - bralr - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bralr - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - bralr - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bralr - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bralr - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bralr - fail -okg: - - pass diff --git a/sim/testsuite/sim/frv/branch.pcgs b/sim/testsuite/sim/frv/branch.pcgs deleted file mode 100644 index 013b0ba..0000000 --- a/sim/testsuite/sim/frv/branch.pcgs +++ /dev/null @@ -1,63 +0,0 @@ -# frv parallel testcase for branching -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global branch -branch: ; All insns in VLIW execute - setlos.p 1,gr1 - setlos 0,gr2 - setlos.p 0,gr3 - bra ok1 - setlos.p 2,gr2 - setlos 3,gr3 - fail -ok1: - test_gr_immed 1,gr1 - test_gr_immed 0,gr2 - test_gr_immed 0,gr3 - - ; 1st branch is taken - bra.p ok5 - bra ok4 - bra.p ok3 - bra ok2 - fail -ok2: - fail -ok3: - fail -ok4: - fail -ok5: - ; 1st true branch is taken - set_icc 0x4 1 - bne.p icc1,1,ok6 - blt icc1,1,ok7 - beq.p icc1,1,ok9 - ble icc1,1,ok8 - fail -ok6: - fail -ok7: - fail -ok8: - fail -ok9: - ; combination of the above - set_icc 0x4 1 - setlos.p 4,gr4 - setlos.p 0,gr5 - bne.p icc1,1,oka - beq icc1,1,okb - setlos 5,gr5 - fail -oka: - fail -okb: - test_gr_immed 4,gr4 - test_gr_immed 0,gr5 - - pass diff --git a/sim/testsuite/sim/frv/break.cgs b/sim/testsuite/sim/frv/break.cgs deleted file mode 100644 index b2a61a0..0000000 --- a/sim/testsuite/sim/frv/break.cgs +++ /dev/null @@ -1,58 +0,0 @@ -# FRV testcase for break -# mach: all - - .include "testutils.inc" - - start - - .global tra -tra: - ; Can't test break anymore in the user environment because it is the - ; debugger's breakpoint insn. Just pass this test for now. - pass - - - - - - set_gr_spr tbr,gr7 - and_gr_immed -4081,gr7 ; clear tbr.tt - inc_gr_immed 0xff0,gr7 ; break handler - set_bctrlr_0_0 gr7 - set_spr_immed 128,lcr - - test_spr_bits 0x4,2,0x1,psr ; psr.s is set - test_spr_bits 0x1,0,0x0,psr ; psr.et is clear - set_spr_addr ok1,lr - break -ret: - or_spr_immed 0x00000001,psr ; turn on psr.et - and_spr_immed 0xfffffffb,psr ; turn off psr.s - test_spr_bits 0x4,2,0x0,psr ; psr.s is clear - test_spr_bits 0x1,0,0x1,psr ; psr.et is set - set_spr_addr ok0,lr - break -ret1: - test_spr_bits 0x4,2,0x0,psr ; psr.s is clear - test_spr_bits 0x1,0,0x1,psr ; psr.et is set - pass - - ; check interrupt for second break -ok0: test_spr_addr ret1,bpcsr - test_spr_bits 0x1000,12,0x0,bpsr ; bpsr.bs is clear - test_spr_bits 0x0001,0,0x1,bpsr ; bpsr.et is set - test_spr_bits 0x4,2,0x1,psr ; psr.s is set - test_spr_bits 0x1,0,0x0,psr ; psr.et is clear - rett 0 ; nop - rett 1 - - ; check interrupt for first break -ok1: test_spr_addr ret,bpcsr - test_spr_bits 0x1000,12,0x1,bpsr ; bpsr.bs is set - test_spr_bits 0x0001,0,0x0,bpsr ; bpsr.et is clear - test_spr_bits 0x4,2,0x1,psr ; psr.s is set - test_spr_bits 0x1,0,0x0,psr ; psr.et is clear - rett 0 ; nop - rett 1 - - diff --git a/sim/testsuite/sim/frv/bv.cgs b/sim/testsuite/sim/frv/bv.cgs deleted file mode 100644 index e2f8174..0000000 --- a/sim/testsuite/sim/frv/bv.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bv $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bv -bv: - set_icc 0x0 0 - bv icc0,0,bad - set_icc 0x1 1 - bv icc1,1,bad - set_icc 0x2 2 - bv icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - bv icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - bv icc0,0,bad - set_icc 0x5 1 - bv icc1,1,bad - set_icc 0x6 2 - bv icc2,2,ok7 - fail -ok7: - set_icc 0x7 3 - bv icc3,3,ok8 - fail -ok8: - set_icc 0x8 0 - bv icc0,0,bad - set_icc 0x9 1 - bv icc1,1,bad - set_icc 0xa 2 - bv icc2,2,okb - fail -okb: - set_icc 0xb 3 - bv icc3,3,okc - fail -okc: - set_icc 0xc 0 - bv icc0,0,bad - set_icc 0xd 1 - bv icc1,1,bad - set_icc 0xe 2 - bv icc2,2,okf - fail -okf: - set_icc 0xf 3 - bv icc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bvlr.cgs b/sim/testsuite/sim/frv/bvlr.cgs deleted file mode 100644 index b7ba9d8..0000000 --- a/sim/testsuite/sim/frv/bvlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bvlr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bvlr -bvlr: - set_spr_addr bad,lr - set_icc 0x0 0 - bvlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bvlr icc1,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bvlr icc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bvlr icc3,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bvlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bvlr icc1,1 - - set_spr_addr ok7,lr - set_icc 0x6 2 - bvlr icc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bvlr icc3,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bvlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bvlr icc1,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bvlr icc2,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bvlr icc3,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bvlr icc0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bvlr icc1,1 - - set_spr_addr okf,lr - set_icc 0xe 2 - bvlr icc2,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bvlr icc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/cache.ms b/sim/testsuite/sim/frv/cache.ms deleted file mode 100644 index 5b93f01..0000000 --- a/sim/testsuite/sim/frv/cache.ms +++ /dev/null @@ -1,168 +0,0 @@ -# mach: frv fr500 fr550 -# sim: --memory-region 0xff000000,4 --memory-region 0xfe000000,00404000 -# xfail: "crashes with bad write" frv-* - -; Exit with return code - - .macro exit rc - setlos.p #1,gr7 - setlos \rc,gr8 - tira gr0,#0 - .endm - -; Pass the test case - .macro pass -pass: - setlos.p #5,gr10 - setlos #1,gr8 - setlos #5,gr7 - sethi.p %hi(passmsg),gr9 - setlo %lo(passmsg),gr9 - tira gr0,#0 - exit #0 - .endm - -; Fail the testcase - .macro fail -fail\@: - setlos.p #5,gr10 - setlos #1,gr8 - setlos #5,gr7 - sethi.p %hi(failmsg),gr9 - setlo %lo(failmsg),gr9 - tira gr0,#0 - exit #1 - .endm - - .data -failmsg: - .ascii "fail\n" -passmsg: - .ascii "pass\n" - - .text - .global _start -_start: - movsg hsr0,gr10 ; enable insn and data caches - sethi.p 0xc800,gr11 ; in copy-back mode - setlo 0x0000,gr11 - or gr10,gr11,gr10 - movgs gr10,hsr0 - - sethi.p 0x7,sp - setlo 0x0000,sp - - ; fill the cache - sethi.p %hi(done1),gr10 - setlo %lo(done1),gr10 - movgs gr10,lr - setlos.p 0x1000,gr10 - setlos 0x0,gr11 - movgs gr10,lcr -write1: st.p gr11,@(sp,gr11) - addi.p gr11,4,gr11 - bctrlr.p 1,0 - bra write1 -done1: - ; read it back - sethi.p %hi(done2),gr10 - setlo %lo(done2),gr10 - movgs gr10,lr - setlos.p 0x1000,gr10 - setlos 0x0,gr11 - movgs gr10,lcr -read1: ld @(sp,gr11),gr12 - cmp gr11,gr12,icc0 - bne icc0,1,fail - addi.p gr11,4,gr11 - bctrlr.p 1,0 - bra read1 -done2: - - ; fill the cache twice - sethi.p %hi(done3),gr10 - setlo %lo(done3),gr10 - movgs gr10,lr - setlos.p 0x2000,gr10 - setlos 0x0,gr11 - movgs gr10,lcr -write3: st.p gr11,@(sp,gr11) - addi.p gr11,4,gr11 - bctrlr.p 1,0 - bra write3 -done3: - ; read it back - sethi.p %hi(done4),gr10 - setlo %lo(done4),gr10 - movgs gr10,lr - setlos.p 0x2000,gr10 - setlos 0x0,gr11 - movgs gr10,lcr -read4: ld @(sp,gr11),gr12 - cmp gr11,gr12,icc0 - bne icc0,1,fail - addi.p gr11,4,gr11 - bctrlr.p 1,0 - bra read4 -done4: - ; read it back in reverse - sethi.p %hi(done5),gr10 - setlo %lo(done5),gr10 - movgs gr10,lr - setlos.p 0x2000,gr10 - setlos 0x7ffc,gr11 - movgs gr10,lcr -read5: ld @(sp,gr11),gr12 - cmp gr11,gr12,icc0 - bne icc0,1,fail - subi.p gr11,4,gr11 - bctrlr.p 1,0 - bra read5 -done5: - - ; access data and insns in non-cache areas - sethi.p 0x8038,gr11 ; bctrlr 0,0 - setlo 0x2000,gr11 - - sethi.p 0xff00,gr10 ; documented area - setlo 0x0000,gr10 - sti gr11,@(gr10,0) - jmpl @(gr10,gr0) - - ; enable RAM mode - movsg hsr0,gr10 - sethi.p 0x0040,gr12 - setlo 0x0000,gr12 - or gr10,gr12,gr10 - movgs gr10,hsr0 - - sethi.p 0xfe00,gr10 ; documented area - setlo 0x0400,gr10 - sti gr11,@(gr10,0) - jmpl @(gr10,gr0) - - sethi.p 0xfe40,gr10 ; documented area - setlo 0x0400,gr10 - sti gr11,@(gr10,0) - dcf @(gr10,gr0) - jmpl @(gr10,gr0) - - sethi.p 0x0007,gr10 ; non RAM area - setlo 0x0000,gr10 - sti gr11,@(gr10,0) - jmpl @(gr10,gr0) - - sethi.p 0xfe00,gr10 ; insn RAM area - setlo 0x0000,gr10 - sti gr11,@(gr10,0) - jmpl @(gr10,gr0) - - sethi.p 0xfe40,gr10 ; data RAM area - setlo 0x0000,gr10 - sti gr11,@(gr10,0) - dcf @(gr10,gr0) - jmpl @(gr10,gr0) - - pass -fail: - fail diff --git a/sim/testsuite/sim/frv/cadd.cgs b/sim/testsuite/sim/frv/cadd.cgs deleted file mode 100644 index 291b8fb..0000000 --- a/sim/testsuite/sim/frv/cadd.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for cadd $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cadd -cadd: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - cadd gr7,gr8,gr8,cc4,1 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - cadd gr7,gr8,gr8,cc4,1 - test_gr_limmed 0x8000,0x0000,gr8 - - cadd gr8,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - cadd gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - cadd gr7,gr8,gr8,cc4,0 - test_gr_immed 1,gr8 - - cadd gr8,gr8,gr8,cc4,0 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - cadd gr7,gr8,gr8,cc5,0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - cadd gr7,gr8,gr8,cc5,0 - test_gr_limmed 0x8000,0x0000,gr8 - - cadd gr8,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - cadd gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - cadd gr7,gr8,gr8,cc5,1 - test_gr_immed 1,gr8 - - cadd gr8,gr8,gr8,cc5,1 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - cadd gr7,gr8,gr8,cc6,1 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - cadd gr7,gr8,gr8,cc6,0 - test_gr_immed 1,gr8 - - cadd gr8,gr8,gr8,cc6,1 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - cadd gr7,gr8,gr8,cc7,0 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - cadd gr7,gr8,gr8,cc7,1 - test_gr_immed 1,gr8 - - cadd gr8,gr8,gr8,cc7,0 - test_gr_immed 1,gr8 - - pass diff --git a/sim/testsuite/sim/frv/caddcc.cgs b/sim/testsuite/sim/frv/caddcc.cgs deleted file mode 100644 index ddfd41e..0000000 --- a/sim/testsuite/sim/frv/caddcc.cgs +++ /dev/null @@ -1,163 +0,0 @@ -# frv testcase for caddcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global caddcc -caddcc: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x08,0 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc4,1; test zero, carry and overflow bits - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_immed 1,gr8 - - set_icc 0x08,0 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc4,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc4,0; test zero, carry and overflow bits - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x08,1 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc5,0; test zero, carry and overflow bits - test_icc 0 1 1 1 icc1 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_immed 1,gr8 - - set_icc 0x08,1 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc5,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc5,1; test zero, carry and overflow bits - test_icc 1 0 0 0 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_immed 1,gr8 - - set_icc 0x08,2 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc6,1 - test_icc 1 0 0 0 icc2 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc6,1; test zero, carry and overflow bits - test_icc 1 0 0 0 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_immed 1,gr8 - - set_icc 0x08,3 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc7,1 - test_icc 1 0 0 0 icc3 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc7,1; test zero, carry and overflow bits - test_icc 1 0 0 0 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - - pass diff --git a/sim/testsuite/sim/frv/call.cgs b/sim/testsuite/sim/frv/call.cgs deleted file mode 100644 index 5f0d767..0000000 --- a/sim/testsuite/sim/frv/call.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# frv testcase for call $label24 -# mach: all - - .include "testutils.inc" - - start - - .global call -call: - set_spr_immed 0,lr - call ok1 -bad1: - fail -ok1: - test_spr_addr bad1,lr - - pass diff --git a/sim/testsuite/sim/frv/call.pcgs b/sim/testsuite/sim/frv/call.pcgs deleted file mode 100644 index 7f452c6..0000000 --- a/sim/testsuite/sim/frv/call.pcgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv parallel testcase for call $label24 -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global call -call: - set_spr_immed 0,lr - call ok1 -bad1: - fail -ok1: - test_spr_addr bad1,lr - - set_spr_immed 0,lr - setlos.p 0,gr5 - call.p ok2 - bra bad3 -bad2: - setlos 5,gr5 - fail -bad3: - fail -ok2: - test_spr_addr bad2,lr - test_gr_immed 0,gr5 - - pass diff --git a/sim/testsuite/sim/frv/callil.cgs b/sim/testsuite/sim/frv/callil.cgs deleted file mode 100644 index eac63e8..0000000 --- a/sim/testsuite/sim/frv/callil.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for callil @($GRi,$d12),$LI -# mach: all - - .include "testutils.inc" - - start - - .global callil -callil: - set_gr_addr ok2,gr8 - inc_gr_immed -2047,gr8 - callil @(gr8,0x7ff) -bad2: - fail -ok2: - test_spr_addr bad2,lr - - set_gr_addr ok3,gr8 - inc_gr_immed 2048,gr8 - callil @(gr8,-2048) -bad3: - fail -ok3: - test_spr_addr bad3,lr - - pass diff --git a/sim/testsuite/sim/frv/calll.cgs b/sim/testsuite/sim/frv/calll.cgs deleted file mode 100644 index eee73bc..0000000 --- a/sim/testsuite/sim/frv/calll.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# frv testcase for calll @($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global calll -calll: - set_gr_addr ok2,gr8 - inc_gr_immed -4,gr8 - inc_gr_immed 4,gr9 - calll @(gr8,gr9) -bad2: - fail -ok2: - test_spr_addr bad2,lr - - set_gr_addr ok3,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - calll @(gr8,gr9) -bad3: - fail -ok3: - test_spr_addr bad3,lr - - pass diff --git a/sim/testsuite/sim/frv/cand.cgs b/sim/testsuite/sim/frv/cand.cgs deleted file mode 100644 index 6113593..0000000 --- a/sim/testsuite/sim/frv/cand.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for cand $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global cand -cand: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc0,1 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc0,1 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0xaaaa,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc4,1 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x0000,0xaaaa,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc0,0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc4,0 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x0000,0xffff,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc1,0 - test_icc 1 0 1 1 icc1 - test_gr_immed 0,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,1 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc1,0 - test_icc 0 1 0 0 icc1 - test_gr_limmed 0xaaaa,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc5,0 - test_icc 1 1 0 1 icc1 - test_gr_limmed 0x0000,0xaaaa,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc1,1 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,1 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 0 icc1 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc5,1 - test_icc 1 1 0 1 icc1 - test_gr_limmed 0x0000,0xffff,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,2 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc2,0 - test_icc 1 0 1 1 icc2 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,2 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc2,0 - test_icc 0 1 0 0 icc2 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,2 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc6,1 - test_icc 1 1 0 1 icc2 - test_gr_limmed 0x0000,0xffff,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,3 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc3,0 - test_icc 1 0 1 1 icc3 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,3 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc3,0 - test_icc 0 1 0 0 icc3 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,3 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc7,1 - test_icc 1 1 0 1 icc3 - test_gr_limmed 0x0000,0xffff,gr8 - - pass diff --git a/sim/testsuite/sim/frv/candcc.cgs b/sim/testsuite/sim/frv/candcc.cgs deleted file mode 100644 index c16df73..0000000 --- a/sim/testsuite/sim/frv/candcc.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for candcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global candcc -candcc: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc0,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0xaaaa,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0x0000,0xaaaa,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc4,0 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x0000,0xffff,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc1,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,1 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_limmed 0xaaaa,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 0 1 icc1 - test_gr_limmed 0x0000,0xaaaa,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,1 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 0 icc1 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc5,1 - test_icc 1 1 0 1 icc1 - test_gr_limmed 0x0000,0xffff,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,2 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc2,0 - test_icc 1 0 1 1 icc2 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,2 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 0 0 icc2 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,2 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc6,1 - test_icc 1 1 0 1 icc2 - test_gr_limmed 0x0000,0xffff,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,3 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc3,0 - test_icc 1 0 1 1 icc3 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,3 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 0 0 icc3 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,3 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc7,1 - test_icc 1 1 0 1 icc3 - test_gr_limmed 0x0000,0xffff,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ccalll.cgs b/sim/testsuite/sim/frv/ccalll.cgs deleted file mode 100644 index dcfd300..0000000 --- a/sim/testsuite/sim/frv/ccalll.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for ccalll @($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global ccalll -ccalll: - set_spr_immed 0x1b1b,cccr - - set_gr_addr ok2,gr8 - inc_gr_immed -4,gr8 - inc_gr_immed 4,gr9 - ccalll @(gr8,gr9),cc0,1 -bad2: - fail -ok2: - test_spr_addr bad2,lr - - set_gr_addr ok3,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - ccalll @(gr8,gr9),cc4,1 -bad3: - fail -ok3: - test_spr_addr bad3,lr - - set_spr_immed 0,lr - set_gr_addr bad,gr8 - inc_gr_immed -4,gr8 - set_gr_immed 4,gr9 - ccalll @(gr8,gr9),cc0,0 - test_spr_addr 0,lr - - set_gr_addr bad,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - ccalll @(gr8,gr9),cc4,0 - test_spr_addr 0,lr - - set_gr_addr ok5,gr8 - inc_gr_immed -4,gr8 - set_gr_immed 4,gr9 - ccalll @(gr8,gr9),cc1,0 -bad5: - fail -ok5: - test_spr_addr bad5,lr - - set_gr_addr ok6,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - ccalll @(gr8,gr9),cc5,0 -bad6: - fail -ok6: - test_spr_addr bad6,lr - - set_spr_immed 0,lr - set_gr_addr bad,gr8 - inc_gr_immed -4,gr8 - set_gr_immed 4,gr9 - ccalll @(gr8,gr9),cc1,1 - test_spr_addr 0,lr - - set_gr_addr bad,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - ccalll @(gr8,gr9),cc5,1 - test_spr_addr 0,lr - - set_gr_addr bad,gr8 - inc_gr_immed -4,gr8 - set_gr_immed 4,gr9 - ccalll @(gr8,gr9),cc2,1 - test_spr_addr 0,lr - - set_gr_addr bad,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - ccalll @(gr8,gr9),cc6,0 - test_spr_addr 0,lr - - set_gr_addr bad,gr8 - inc_gr_immed -4,gr8 - set_gr_immed 4,gr9 - ccalll @(gr8,gr9),cc3,0 - test_spr_addr 0,lr - - set_gr_addr bad,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - ccalll @(gr8,gr9),cc7,1 - test_spr_addr 0,lr - - pass -bad: - fail - diff --git a/sim/testsuite/sim/frv/cckc.cgs b/sim/testsuite/sim/frv/cckc.cgs deleted file mode 100644 index 70eabee..0000000 --- a/sim/testsuite/sim/frv/cckc.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckc $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckc -cckc: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckeq.cgs b/sim/testsuite/sim/frv/cckeq.cgs deleted file mode 100644 index 2c86f18..0000000 --- a/sim/testsuite/sim/frv/cckeq.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckeq $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckeq -cckeq: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckeq icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckeq icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckeq icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckeq icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckeq icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckeq icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckeq icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckeq icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckeq icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckeq icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckeq icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckeq icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckeq icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckeq icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckeq icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckeq icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckeq icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckeq icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckeq icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckeq icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckeq icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckeq icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckeq icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckeq icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckeq icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckeq icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckeq icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckeq icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckeq icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckeq icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckeq icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckeq icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckge.cgs b/sim/testsuite/sim/frv/cckge.cgs deleted file mode 100644 index 6938f1e..0000000 --- a/sim/testsuite/sim/frv/cckge.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckge $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckge -cckge: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckge icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckge icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckge icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckge icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckge icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckge icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckge icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckge icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckge icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckge icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckge icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckge icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckge icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckge icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckge icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckge icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckge icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckge icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckge icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckge icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckge icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckge icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckge icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckge icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckge icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckge icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckge icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckge icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckge icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckge icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckge icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckge icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckgt.cgs b/sim/testsuite/sim/frv/cckgt.cgs deleted file mode 100644 index e0745dd..0000000 --- a/sim/testsuite/sim/frv/cckgt.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckgt $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckgt -cckgt: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckgt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckgt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckgt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckgt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckgt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckgt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckgt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckgt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckgt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckgt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckgt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckgt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckgt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckgt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckgt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckgt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckgt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckgt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckgt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckgt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckgt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckgt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckgt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckgt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckgt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckgt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckgt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckgt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckgt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckgt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckgt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckgt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckhi.cgs b/sim/testsuite/sim/frv/cckhi.cgs deleted file mode 100644 index 4741f5a..0000000 --- a/sim/testsuite/sim/frv/cckhi.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckhi $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckhi -cckhi: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckhi icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckhi icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckhi icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckhi icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckhi icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckhi icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckhi icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckhi icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckhi icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckhi icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckhi icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckhi icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckhi icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckhi icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckhi icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckhi icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckhi icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckhi icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckhi icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckhi icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckhi icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckhi icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckhi icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckhi icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckhi icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckhi icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckhi icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckhi icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckhi icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckhi icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckhi icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckhi icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckle.cgs b/sim/testsuite/sim/frv/cckle.cgs deleted file mode 100644 index 9d88214..0000000 --- a/sim/testsuite/sim/frv/cckle.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckle $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckle -cckle: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckle icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckle icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckle icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckle icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckle icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckle icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckle icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckle icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckle icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckle icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckle icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckle icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckle icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckle icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckle icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckle icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckle icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckle icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckle icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckle icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckle icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckle icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckle icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckle icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckle icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckle icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckle icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckle icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckle icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckle icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckle icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckle icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckls.cgs b/sim/testsuite/sim/frv/cckls.cgs deleted file mode 100644 index a78b779..0000000 --- a/sim/testsuite/sim/frv/cckls.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckls $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckls -cckls: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ccklt.cgs b/sim/testsuite/sim/frv/ccklt.cgs deleted file mode 100644 index c14c632..0000000 --- a/sim/testsuite/sim/frv/ccklt.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for ccklt $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global ccklt -ccklt: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccklt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccklt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccklt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccklt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccklt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccklt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccklt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccklt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccklt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccklt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccklt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccklt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccklt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccklt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccklt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccklt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccklt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccklt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccklt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccklt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccklt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccklt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccklt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccklt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccklt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccklt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccklt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccklt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccklt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccklt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccklt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccklt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckn.cgs b/sim/testsuite/sim/frv/cckn.cgs deleted file mode 100644 index d423124..0000000 --- a/sim/testsuite/sim/frv/cckn.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckn $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckn -cckn: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckn icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckn icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckn icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckn icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckn icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckn icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckn icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckn icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckn icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckn icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckn icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckn icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckn icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckn icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckn icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckn icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckn icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckn icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckn icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckn icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckn icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckn icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckn icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckn icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckn icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckn icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckn icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckn icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckn icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckn icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckn icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckn icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ccknc.cgs b/sim/testsuite/sim/frv/ccknc.cgs deleted file mode 100644 index 0478f27..0000000 --- a/sim/testsuite/sim/frv/ccknc.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for ccknc $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global ccknc -ccknc: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknc icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknc icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknc icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknc icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknc icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknc icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknc icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknc icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknc icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknc icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknc icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknc icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknc icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknc icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknc icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknc icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckne.cgs b/sim/testsuite/sim/frv/cckne.cgs deleted file mode 100644 index d8af1e3..0000000 --- a/sim/testsuite/sim/frv/cckne.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckne $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckne -cckne: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckne icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckne icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckne icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckne icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckne icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckne icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckne icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckne icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckne icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckne icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckne icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckne icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckne icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckne icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckne icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckne icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckne icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckne icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckne icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckne icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckne icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckne icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckne icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckne icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckne icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckne icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckne icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckne icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckne icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckne icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckne icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckne icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckno.cgs b/sim/testsuite/sim/frv/cckno.cgs deleted file mode 100644 index 8c3c927..0000000 --- a/sim/testsuite/sim/frv/cckno.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckno $CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckno -cckno: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckno cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckno cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckno cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckno cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckno cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckno cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckno cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckno cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckno cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckno cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckno cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckno cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckno cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckno cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckno cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckno cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckno cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckno cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckno cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckno cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckno cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckno cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckno cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckno cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckno cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckno cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckno cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckno cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckno cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckno cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckno cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckno cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ccknv.cgs b/sim/testsuite/sim/frv/ccknv.cgs deleted file mode 100644 index 333edca..0000000 --- a/sim/testsuite/sim/frv/ccknv.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for ccknv $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global ccknv -ccknv: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckp.cgs b/sim/testsuite/sim/frv/cckp.cgs deleted file mode 100644 index 53570d9..0000000 --- a/sim/testsuite/sim/frv/cckp.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckp $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckp -cckp: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckp icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckp icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckp icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckp icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckp icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckp icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckp icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckp icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckp icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckp icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckp icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckp icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckp icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckp icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckp icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckp icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckp icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckp icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckp icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckp icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckp icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckp icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckp icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckp icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckp icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckp icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckp icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckp icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckp icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckp icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckp icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckp icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckra.cgs b/sim/testsuite/sim/frv/cckra.cgs deleted file mode 100644 index c0b27fc..0000000 --- a/sim/testsuite/sim/frv/cckra.cgs +++ /dev/null @@ -1,480 +0,0 @@ -# frv testcase for cckra $CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckra -cckra: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckra cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckra cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckra cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckra cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckra cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckra cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckra cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckra cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckra cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckra cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckra cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckra cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckra cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckra cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckra cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckra cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckra cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckra cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckra cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckra cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckra cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckra cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckra cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckra cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckra cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckra cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckra cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckra cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckra cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckra cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckv.cgs b/sim/testsuite/sim/frv/cckv.cgs deleted file mode 100644 index 9ebb6e3..0000000 --- a/sim/testsuite/sim/frv/cckv.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckv $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckv -cckv: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ccmp.cgs b/sim/testsuite/sim/frv/ccmp.cgs deleted file mode 100644 index 52d5310..0000000 --- a/sim/testsuite/sim/frv/ccmp.cgs +++ /dev/null @@ -1,134 +0,0 @@ -# frv testcase for ccmp $GRi,$GRj,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global ccmp -ccmp: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - ccmp gr8,gr7,cc0,1 - test_icc 0 0 0 0 icc0 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - ccmp gr8,gr7,cc0,1 - test_icc 0 0 1 0 icc0 - - set_icc 0x0b,0 ; Set mask opposite of expected - ccmp gr8,gr8,cc4,1 - test_icc 0 1 0 0 icc0 - - set_gr_immed 0,gr8 - set_icc 0x06,0 ; Set mask opposite of expected - ccmp gr8,gr7,cc4,1 - test_icc 1 0 0 1 icc0 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - ccmp gr8,gr7,cc0,0 - test_icc 1 1 1 1 icc0 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - ccmp gr8,gr7,cc0,0 - test_icc 1 1 0 1 icc0 - - set_icc 0x0b,0 ; Set mask opposite of expected - ccmp gr8,gr8,cc4,0 - test_icc 1 0 1 1 icc0 - - set_icc 0x06,0 ; Set mask opposite of expected - ccmp gr8,gr7,cc4,0 - test_icc 0 1 1 0 icc0 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - ccmp gr8,gr7,cc1,0 - test_icc 0 0 0 0 icc1 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - ccmp gr8,gr7,cc1,0 - test_icc 0 0 1 0 icc1 - - set_icc 0x0b,1 ; Set mask opposite of expected - ccmp gr8,gr8,cc5,0 - test_icc 0 1 0 0 icc1 - - set_gr_immed 0,gr8 - set_icc 0x06,1 ; Set mask opposite of expected - ccmp gr8,gr7,cc5,0 - test_icc 1 0 0 1 icc1 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - ccmp gr8,gr7,cc1,1 - test_icc 1 1 1 1 icc1 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - ccmp gr8,gr7,cc1,1 - test_icc 1 1 0 1 icc1 - - set_icc 0x0b,1 ; Set mask opposite of expected - ccmp gr8,gr8,cc5,1 - test_icc 1 0 1 1 icc1 - - set_icc 0x06,1 ; Set mask opposite of expected - ccmp gr8,gr7,cc5,1 - test_icc 0 1 1 0 icc1 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - ccmp gr8,gr7,cc2,0 - test_icc 1 1 1 1 icc2 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,2 ; Set mask opposite of expected - ccmp gr8,gr7,cc2,0 - test_icc 1 1 0 1 icc2 - - set_icc 0x0b,2 ; Set mask opposite of expected - ccmp gr8,gr8,cc6,1 - test_icc 1 0 1 1 icc2 - - set_icc 0x06,2 ; Set mask opposite of expected - ccmp gr8,gr7,cc6,1 - test_icc 0 1 1 0 icc2 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - ccmp gr8,gr7,cc3,0 - test_icc 1 1 1 1 icc3 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,3 ; Set mask opposite of expected - ccmp gr8,gr7,cc3,0 - test_icc 1 1 0 1 icc3 - - set_icc 0x0b,3 ; Set mask opposite of expected - ccmp gr8,gr8,cc7,1 - test_icc 1 0 1 1 icc3 - - set_icc 0x06,3 ; Set mask opposite of expected - ccmp gr8,gr7,cc7,1 - test_icc 0 1 1 0 icc3 - - pass diff --git a/sim/testsuite/sim/frv/cfabss.cgs b/sim/testsuite/sim/frv/cfabss.cgs deleted file mode 100644 index 752a40b..0000000 --- a/sim/testsuite/sim/frv/cfabss.cgs +++ /dev/null @@ -1,96 +0,0 @@ -# frv testcase for cfabss $FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfabss -cfabss: - set_spr_immed 0x1b1b,cccr - - cfabss fr0,fr1,cc0,1 - test_fr_fr fr1,fr52 - cfabss fr8,fr1,cc0,1 - test_fr_fr fr1,fr28 - cfabss fr12,fr1,cc0,1 - test_fr_fr fr1,fr24 - cfabss fr24,fr1,cc4,1 - test_fr_fr fr1,fr24 - cfabss fr28,fr1,cc4,1 - test_fr_fr fr1,fr28 - cfabss fr52,fr1,cc4,1 - test_fr_fr fr1,fr52 - - cfabss fr0,fr1,cc1,0 - test_fr_fr fr1,fr52 - cfabss fr8,fr1,cc1,0 - test_fr_fr fr1,fr28 - cfabss fr12,fr1,cc1,0 - test_fr_fr fr1,fr24 - cfabss fr24,fr1,cc5,0 - test_fr_fr fr1,fr24 - cfabss fr28,fr1,cc5,0 - test_fr_fr fr1,fr28 - cfabss fr52,fr1,cc5,0 - test_fr_fr fr1,fr52 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfabss fr0,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr24,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfabss fr0,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr24,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfabss fr0,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr8,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr12,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr24,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr28,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr52,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfabss fr0,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr8,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr12,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr24,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr28,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr52,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfadds.cgs b/sim/testsuite/sim/frv/cfadds.cgs deleted file mode 100644 index 158ac93..0000000 --- a/sim/testsuite/sim/frv/cfadds.cgs +++ /dev/null @@ -1,456 +0,0 @@ -# frv testcase for cfadds $FRi,$FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfadds -cfadds: - set_spr_immed 0x1b1b,cccr - - cfadds fr16,fr0,fr1,cc0,1 - test_fr_fr fr1,fr0 - cfadds fr16,fr4,fr1,cc0,1 - test_fr_fr fr1,fr4 - cfadds fr16,fr8,fr1,cc0,1 - test_fr_fr fr1,fr8 - cfadds fr16,fr12,fr1,cc0,1 - test_fr_fr fr1,fr12 - cfadds fr16,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr16,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr16,fr24,fr1,cc0,1 - test_fr_fr fr1,fr24 - cfadds fr16,fr28,fr1,cc0,1 - test_fr_fr fr1,fr28 - cfadds fr16,fr32,fr1,cc0,1 - test_fr_fr fr1,fr32 - cfadds fr16,fr36,fr1,cc0,1 - test_fr_fr fr1,fr36 - cfadds fr16,fr40,fr1,cc0,1 - test_fr_fr fr1,fr40 - cfadds fr16,fr44,fr1,cc0,1 - test_fr_fr fr1,fr44 - cfadds fr16,fr48,fr1,cc0,1 - test_fr_fr fr1,fr48 - cfadds fr16,fr52,fr1,cc0,1 - test_fr_fr fr1,fr52 - - cfadds fr20,fr0,fr1,cc0,1 - test_fr_fr fr1,fr0 - cfadds fr20,fr4,fr1,cc0,1 - test_fr_fr fr1,fr4 - cfadds fr20,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - cfadds fr20,fr12,fr1,cc4,1 - test_fr_fr fr1,fr12 - cfadds fr20,fr16,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr20,fr20,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr20,fr24,fr1,cc4,1 - test_fr_fr fr1,fr24 - cfadds fr20,fr28,fr1,cc4,1 - test_fr_fr fr1,fr28 - cfadds fr20,fr32,fr1,cc4,1 - test_fr_fr fr1,fr32 - cfadds fr20,fr36,fr1,cc4,1 - test_fr_fr fr1,fr36 - cfadds fr20,fr40,fr1,cc4,1 - test_fr_fr fr1,fr40 - cfadds fr20,fr44,fr1,cc4,1 - test_fr_fr fr1,fr44 - cfadds fr20,fr48,fr1,cc4,1 - test_fr_fr fr1,fr48 - cfadds fr20,fr52,fr1,cc4,1 - test_fr_fr fr1,fr52 - - cfadds fr8,fr28,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr12,fr24,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr24,fr12,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfadds fr36,fr40,fr1,cc4,1 - test_fr_fr fr1,fr44 - - cfadds fr16,fr0,fr1,cc1,0 - test_fr_fr fr1,fr0 - cfadds fr16,fr4,fr1,cc1,0 - test_fr_fr fr1,fr4 - cfadds fr16,fr8,fr1,cc1,0 - test_fr_fr fr1,fr8 - cfadds fr16,fr12,fr1,cc1,0 - test_fr_fr fr1,fr12 - cfadds fr16,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr16,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr16,fr24,fr1,cc1,0 - test_fr_fr fr1,fr24 - cfadds fr16,fr28,fr1,cc1,0 - test_fr_fr fr1,fr28 - cfadds fr16,fr32,fr1,cc1,0 - test_fr_fr fr1,fr32 - cfadds fr16,fr36,fr1,cc1,0 - test_fr_fr fr1,fr36 - cfadds fr16,fr40,fr1,cc1,0 - test_fr_fr fr1,fr40 - cfadds fr16,fr44,fr1,cc1,0 - test_fr_fr fr1,fr44 - cfadds fr16,fr48,fr1,cc1,0 - test_fr_fr fr1,fr48 - cfadds fr16,fr52,fr1,cc1,0 - test_fr_fr fr1,fr52 - - cfadds fr20,fr0,fr1,cc1,0 - test_fr_fr fr1,fr0 - cfadds fr20,fr4,fr1,cc1,0 - test_fr_fr fr1,fr4 - cfadds fr20,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - cfadds fr20,fr12,fr1,cc5,0 - test_fr_fr fr1,fr12 - cfadds fr20,fr16,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr20,fr20,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr20,fr24,fr1,cc5,0 - test_fr_fr fr1,fr24 - cfadds fr20,fr28,fr1,cc5,0 - test_fr_fr fr1,fr28 - cfadds fr20,fr32,fr1,cc5,0 - test_fr_fr fr1,fr32 - cfadds fr20,fr36,fr1,cc5,0 - test_fr_fr fr1,fr36 - cfadds fr20,fr40,fr1,cc5,0 - test_fr_fr fr1,fr40 - cfadds fr20,fr44,fr1,cc5,0 - test_fr_fr fr1,fr44 - cfadds fr20,fr48,fr1,cc5,0 - test_fr_fr fr1,fr48 - cfadds fr20,fr52,fr1,cc5,0 - test_fr_fr fr1,fr52 - - cfadds fr8,fr28,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr12,fr24,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr24,fr12,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfadds fr36,fr40,fr1,cc5,0 - test_fr_fr fr1,fr44 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfadds fr16,fr0,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr4,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr20,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr24,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr32,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr36,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr40,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr44,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr48,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr52,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr20,fr0,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr4,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr8,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr12,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr16,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr24,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr44,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr48,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr8,fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr12,fr24,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr24,fr12,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr28,fr8,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr36,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfadds fr16,fr0,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr4,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr20,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr24,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr32,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr36,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr40,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr44,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr48,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr52,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr20,fr0,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr4,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr8,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr12,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr16,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr24,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr44,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr48,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr8,fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr12,fr24,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr24,fr12,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr28,fr8,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr36,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfadds fr16,fr0,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr4,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr8,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr12,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr20,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr24,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr32,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr36,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr40,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr44,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr48,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr52,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr20,fr0,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr4,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr8,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr12,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr16,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr24,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr28,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr32,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr36,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr40,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr44,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr48,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr52,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr8,fr28,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr12,fr24,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr24,fr12,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr28,fr8,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr36,fr40,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfadds fr16,fr0,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr4,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr8,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr12,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr20,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr24,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr32,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr36,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr40,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr44,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr48,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr52,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr20,fr0,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr4,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr8,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr12,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr16,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr24,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr28,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr32,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr36,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr40,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr44,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr48,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr52,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr8,fr28,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr12,fr24,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr24,fr12,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr28,fr8,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr36,fr40,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass - - diff --git a/sim/testsuite/sim/frv/cfckeq.cgs b/sim/testsuite/sim/frv/cfckeq.cgs deleted file mode 100644 index 467568a..0000000 --- a/sim/testsuite/sim/frv/cfckeq.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckeq $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckeq -cfckeq: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckeq fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckeq fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckeq fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckeq fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckeq fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckeq fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckeq fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckeq fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckeq fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckeq fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckeq fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckeq fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckeq fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckeq fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckeq fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckeq fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckeq fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckeq fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckeq fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckeq fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckeq fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckeq fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckeq fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckeq fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckeq fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckeq fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckeq fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckeq fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckeq fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckeq fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckeq fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckeq fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckge.cgs b/sim/testsuite/sim/frv/cfckge.cgs deleted file mode 100644 index ba2de95..0000000 --- a/sim/testsuite/sim/frv/cfckge.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckge $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckge -cfckge: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckgt.cgs b/sim/testsuite/sim/frv/cfckgt.cgs deleted file mode 100644 index 7858c17..0000000 --- a/sim/testsuite/sim/frv/cfckgt.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckgt $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckgt -cfckgt: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckgt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckgt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckgt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckgt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckgt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckgt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckgt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckgt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckgt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckgt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckgt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckgt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckgt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckgt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckgt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckgt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckgt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckgt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckgt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckgt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckgt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckgt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckgt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckgt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckgt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckgt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckgt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckgt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckgt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckgt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckgt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckgt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckle.cgs b/sim/testsuite/sim/frv/cfckle.cgs deleted file mode 100644 index fb2b1b85..0000000 --- a/sim/testsuite/sim/frv/cfckle.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckle $FCCi,$CCj_float$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckle -cfckle: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckle fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckle fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckle fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckle fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckle fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckle fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckle fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckle fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckle fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckle fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckle fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckle fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckle fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckle fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckle fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckle fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckle fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckle fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckle fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckle fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckle fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckle fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckle fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckle fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckle fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckle fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckle fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckle fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckle fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckle fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckle fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckle fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfcklg.cgs b/sim/testsuite/sim/frv/cfcklg.cgs deleted file mode 100644 index 22deb52..0000000 --- a/sim/testsuite/sim/frv/cfcklg.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfcklg $FCCi,$CCj_float$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfcklg -cfcklg: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklg fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklg fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklg fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklg fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklg fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklg fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklg fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklg fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklg fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklg fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklg fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklg fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklg fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklg fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklg fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklg fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklg fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklg fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklg fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklg fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklg fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklg fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklg fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklg fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklg fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklg fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklg fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklg fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklg fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklg fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklg fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklg fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfcklt.cgs b/sim/testsuite/sim/frv/cfcklt.cgs deleted file mode 100644 index ffabcd2..0000000 --- a/sim/testsuite/sim/frv/cfcklt.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfcklt $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfcklt -cfcklt: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckne.cgs b/sim/testsuite/sim/frv/cfckne.cgs deleted file mode 100644 index da6846f..0000000 --- a/sim/testsuite/sim/frv/cfckne.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckne $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckne -cfckne: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckne fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckne fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckne fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckne fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckne fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckne fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckne fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckne fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckne fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckne fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckne fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckne fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckne fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckne fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckne fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckne fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckne fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckne fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckne fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckne fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckne fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckne fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckne fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckne fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckne fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckne fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckne fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckne fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckne fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckne fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckne fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckne fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckno.cgs b/sim/testsuite/sim/frv/cfckno.cgs deleted file mode 100644 index 5681960..0000000 --- a/sim/testsuite/sim/frv/cfckno.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckno $CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckno -cfckno: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckno cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckno cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckno cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckno cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckno cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckno cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckno cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckno cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckno cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckno cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckno cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckno cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckno cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckno cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckno cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckno cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckno cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckno cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckno cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckno cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckno cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckno cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckno cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckno cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckno cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckno cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckno cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckno cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckno cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckno cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckno cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckno cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfcko.cgs b/sim/testsuite/sim/frv/cfcko.cgs deleted file mode 100644 index ac55fc3..0000000 --- a/sim/testsuite/sim/frv/cfcko.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfcko $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfcko -cfcko: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcko fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcko fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcko fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcko fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcko fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcko fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcko fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcko fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcko fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcko fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcko fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcko fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcko fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcko fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcko fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcko fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcko fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcko fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcko fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcko fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcko fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcko fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcko fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcko fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcko fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcko fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcko fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcko fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcko fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcko fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcko fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcko fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckra.cgs b/sim/testsuite/sim/frv/cfckra.cgs deleted file mode 100644 index 0cabd8f..0000000 --- a/sim/testsuite/sim/frv/cfckra.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckra $CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckra -cfckra: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckra cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckra cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckra cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckra cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckra cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckra cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckra cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckra cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckra cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckra cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckra cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckra cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckra cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckra cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckra cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckra cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckra cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckra cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckra cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckra cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckra cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckra cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckra cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckra cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckra cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckra cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckra cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckra cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckra cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckra cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckra cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckra cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfcku.cgs b/sim/testsuite/sim/frv/cfcku.cgs deleted file mode 100644 index 0f56e7e..0000000 --- a/sim/testsuite/sim/frv/cfcku.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfcku $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfcku -cfcku: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcku fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcku fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcku fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcku fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcku fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcku fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcku fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcku fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcku fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcku fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcku fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcku fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcku fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcku fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcku fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcku fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcku fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcku fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcku fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcku fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcku fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcku fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcku fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcku fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcku fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcku fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcku fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcku fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcku fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcku fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcku fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcku fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckue.cgs b/sim/testsuite/sim/frv/cfckue.cgs deleted file mode 100644 index 447c2ba..0000000 --- a/sim/testsuite/sim/frv/cfckue.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckue $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckue -cfckue: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckue fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckue fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckue fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckue fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckue fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckue fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckue fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckue fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckue fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckue fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckue fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckue fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckue fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckue fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckue fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckue fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckue fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckue fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckue fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckue fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckue fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckue fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckue fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckue fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckue fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckue fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckue fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckue fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckue fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckue fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckue fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckue fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckug.cgs b/sim/testsuite/sim/frv/cfckug.cgs deleted file mode 100644 index 7442f84..0000000 --- a/sim/testsuite/sim/frv/cfckug.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckug $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckug -cfckug: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckug fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckug fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckug fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckug fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckug fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckug fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckug fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckug fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckug fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckug fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckug fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckug fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckug fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckug fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckug fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckug fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckug fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckug fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckug fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckug fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckug fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckug fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckug fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckug fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckug fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckug fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckug fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckug fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckug fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckug fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckug fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckug fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckuge.cgs b/sim/testsuite/sim/frv/cfckuge.cgs deleted file mode 100644 index 8eaf92f..0000000 --- a/sim/testsuite/sim/frv/cfckuge.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckuge $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckuge -cfckuge: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckuge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckuge fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckuge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckuge fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckuge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckuge fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckuge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckuge fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckuge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckuge fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckuge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckuge fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckuge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckuge fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckuge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckuge fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckuge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckuge fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckuge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckuge fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckuge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckuge fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckuge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckuge fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckuge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckuge fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckuge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckuge fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckuge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckuge fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckuge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckuge fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckul.cgs b/sim/testsuite/sim/frv/cfckul.cgs deleted file mode 100644 index 5945a8a..0000000 --- a/sim/testsuite/sim/frv/cfckul.cgs +++ /dev/null @@ -1,410 +0,0 @@ -# frv testcase for cfckul $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckul -cfckul: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckule.cgs b/sim/testsuite/sim/frv/cfckule.cgs deleted file mode 100644 index aaf655e..0000000 --- a/sim/testsuite/sim/frv/cfckule.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckule $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckule -cfckule: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckule fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckule fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckule fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckule fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckule fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckule fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckule fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckule fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckule fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckule fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckule fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckule fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckule fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckule fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckule fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckule fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckule fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckule fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckule fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckule fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckule fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckule fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckule fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckule fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckule fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckule fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckule fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckule fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckule fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckule fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckule fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckule fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfcmps.cgs b/sim/testsuite/sim/frv/cfcmps.cgs deleted file mode 100644 index 168e618..0000000 --- a/sim/testsuite/sim/frv/cfcmps.cgs +++ /dev/null @@ -1,3542 +0,0 @@ -# frv testcase for cfcmps $FRi,$FRj,$FCCi,$CCi,$cond_2 -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfcmps -cfcmps: - set_spr_immed 0x1b1b,cccr - - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr0,fr0,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr4,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr8,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr12,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr16,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr20,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr24,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr28,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr32,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr36,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr40,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr44,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr48,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr52,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr56,fcc0,cc0,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr60,fcc0,cc0,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr4,fr0,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr4,fr4,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr8,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr12,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr16,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr20,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr24,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr28,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr32,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr36,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr40,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr44,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr48,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr52,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr56,fcc0,cc0,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr60,fcc0,cc0,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr0,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr4,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr8,fr8,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr12,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr16,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr20,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr24,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr28,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr32,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr36,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr40,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr44,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr48,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr52,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr56,fcc0,cc0,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr60,fcc0,cc0,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr0,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr4,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr8,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr12,fr12,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr16,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr20,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr24,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr28,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr32,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr36,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr40,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr44,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr48,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr52,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr56,fcc0,cc0,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr60,fcc0,cc0,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr0,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr4,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr8,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr12,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr16,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr20,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr24,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr28,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr32,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr36,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr40,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr44,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr48,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr52,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr56,fcc0,cc0,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr60,fcc0,cc0,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr0,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr4,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr8,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr12,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr16,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr20,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr24,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr28,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr32,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr36,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr40,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr44,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr48,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr52,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr56,fcc0,cc0,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr60,fcc0,cc0,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr0,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr4,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr8,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr12,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr16,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr20,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr24,fr24,fcc0,cc4,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr28,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr32,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr36,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr40,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr44,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr48,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr52,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr56,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr60,fcc0,cc4,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr0,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr4,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr8,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr12,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr16,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr20,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr24,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr28,fr28,fcc0,cc4,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr32,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr36,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr40,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr44,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr48,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr52,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr56,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr60,fcc0,cc4,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr0,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr4,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr8,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr12,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr16,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr20,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr24,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr28,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr32,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr36,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr40,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr44,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr48,fr48,fcc0,cc4,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr48,fr52,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr56,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr60,fcc0,cc4,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr0,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr4,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr8,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr12,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr16,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr20,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr24,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr28,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr32,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr36,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr40,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr44,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr48,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr52,fr52,fcc0,cc4,1 - test_fcc 0x8,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr56,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr60,fcc0,cc4,1 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr0,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr4,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr8,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr12,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr16,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr20,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr24,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr28,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr32,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr36,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr40,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr44,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr48,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr52,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr56,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr60,fcc0,cc4,1 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr0,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr4,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr8,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr12,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr16,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr20,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr24,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr28,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr32,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr36,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr40,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr44,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr48,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr52,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr56,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr60,fcc0,cc4,1 - test_fcc 0x1,0 -; - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr0,fr0,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr4,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr8,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr12,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr16,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr20,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr24,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr28,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr32,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr36,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr40,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr44,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr48,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr52,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr56,fcc0,cc1,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr60,fcc0,cc1,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr4,fr0,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr4,fr4,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr8,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr12,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr16,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr20,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr24,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr28,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr32,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr36,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr40,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr44,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr48,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr52,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr56,fcc0,cc1,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr60,fcc0,cc1,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr0,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr4,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr8,fr8,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr12,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr16,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr20,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr24,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr28,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr32,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr36,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr40,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr44,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr48,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr52,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr56,fcc0,cc1,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr60,fcc0,cc1,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr0,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr4,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr8,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr12,fr12,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr16,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr20,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr24,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr28,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr32,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr36,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr40,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr44,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr48,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr52,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr56,fcc0,cc1,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr60,fcc0,cc1,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr0,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr4,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr8,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr12,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr16,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr20,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr24,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr28,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr32,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr36,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr40,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr44,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr48,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr52,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr56,fcc0,cc1,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr60,fcc0,cc1,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr0,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr4,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr8,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr12,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr16,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr20,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr24,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr28,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr32,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr36,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr40,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr44,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr48,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr52,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr56,fcc0,cc1,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr60,fcc0,cc1,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr0,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr4,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr8,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr12,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr16,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr20,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr24,fr24,fcc0,cc5,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr28,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr32,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr36,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr40,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr44,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr48,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr52,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr56,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr60,fcc0,cc5,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr0,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr4,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr8,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr12,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr16,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr20,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr24,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr28,fr28,fcc0,cc5,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr32,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr36,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr40,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr44,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr48,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr52,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr56,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr60,fcc0,cc5,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr0,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr4,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr8,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr12,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr16,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr20,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr24,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr28,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr32,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr36,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr40,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr44,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr48,fr48,fcc0,cc5,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr48,fr52,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr56,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr60,fcc0,cc5,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr0,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr4,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr8,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr12,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr16,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr20,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr24,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr28,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr32,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr36,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr40,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr44,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr48,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr52,fr52,fcc0,cc5,0 - test_fcc 0x8,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr56,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr60,fcc0,cc5,0 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr0,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr4,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr8,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr12,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr16,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr20,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr24,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr28,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr32,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr36,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr40,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr44,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr48,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr52,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr56,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr60,fcc0,cc5,0 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr0,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr4,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr8,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr12,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr16,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr20,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr24,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr28,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr32,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr36,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr40,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr44,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr48,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr52,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr56,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr60,fcc0,cc5,0 - test_fcc 0x1,0 -; - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr0,fr0,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr4,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr8,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr12,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr16,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr20,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr24,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr28,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr32,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr36,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr40,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr44,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr48,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr52,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr56,fcc0,cc0,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr60,fcc0,cc0,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr4,fr0,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr4,fr4,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr8,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr12,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr16,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr20,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr24,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr28,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr32,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr36,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr40,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr44,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr48,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr52,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr56,fcc0,cc0,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr60,fcc0,cc0,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr0,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr4,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr8,fr8,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr12,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr16,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr20,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr24,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr28,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr32,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr36,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr40,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr44,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr48,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr52,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr56,fcc0,cc0,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr60,fcc0,cc0,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr0,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr4,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr8,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr12,fr12,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr16,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr20,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr24,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr28,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr32,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr36,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr40,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr44,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr48,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr52,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr56,fcc0,cc0,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr60,fcc0,cc0,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr0,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr4,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr8,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr12,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr16,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr20,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr24,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr28,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr32,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr36,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr40,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr44,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr48,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr52,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr56,fcc0,cc0,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr60,fcc0,cc0,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr0,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr4,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr8,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr12,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr16,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr20,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr24,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr28,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr32,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr36,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr40,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr44,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr48,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr52,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr56,fcc0,cc0,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr60,fcc0,cc0,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr0,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr4,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr8,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr12,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr16,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr20,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr24,fr24,fcc0,cc4,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr28,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr32,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr36,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr40,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr44,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr48,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr52,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr56,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr60,fcc0,cc4,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr0,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr4,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr8,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr12,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr16,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr20,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr24,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr28,fr28,fcc0,cc4,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr32,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr36,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr40,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr44,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr48,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr52,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr56,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr60,fcc0,cc4,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr0,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr4,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr8,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr12,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr16,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr20,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr24,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr28,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr32,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr36,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr40,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr44,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr48,fr48,fcc0,cc4,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr48,fr52,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr56,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr60,fcc0,cc4,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr0,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr4,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr8,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr12,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr16,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr20,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr24,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr28,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr32,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr36,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr40,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr44,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr48,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr52,fr52,fcc0,cc4,0 - test_fcc 0x7,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr56,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr60,fcc0,cc4,0 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr0,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr4,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr8,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr12,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr16,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr20,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr24,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr28,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr32,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr36,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr40,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr44,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr48,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr52,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr56,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr60,fcc0,cc4,0 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr0,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr4,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr8,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr12,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr16,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr20,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr24,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr28,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr32,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr36,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr40,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr44,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr48,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr52,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr56,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr60,fcc0,cc4,0 - test_fcc 0xe,0 -; - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr0,fr0,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr4,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr8,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr12,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr16,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr20,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr24,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr28,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr32,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr36,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr40,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr44,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr48,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr52,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr56,fcc0,cc1,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr60,fcc0,cc1,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr4,fr0,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr4,fr4,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr8,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr12,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr16,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr20,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr24,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr28,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr32,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr36,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr40,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr44,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr48,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr52,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr56,fcc0,cc1,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr60,fcc0,cc1,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr0,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr4,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr8,fr8,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr12,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr16,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr20,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr24,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr28,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr32,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr36,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr40,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr44,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr48,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr52,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr56,fcc0,cc1,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr60,fcc0,cc1,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr0,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr4,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr8,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr12,fr12,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr16,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr20,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr24,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr28,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr32,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr36,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr40,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr44,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr48,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr52,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr56,fcc0,cc1,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr60,fcc0,cc1,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr0,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr4,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr8,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr12,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr16,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr20,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr24,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr28,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr32,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr36,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr40,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr44,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr48,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr52,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr56,fcc0,cc1,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr60,fcc0,cc1,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr0,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr4,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr8,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr12,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr16,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr20,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr24,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr28,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr32,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr36,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr40,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr44,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr48,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr52,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr56,fcc0,cc1,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr60,fcc0,cc1,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr0,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr4,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr8,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr12,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr16,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr20,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr24,fr24,fcc0,cc5,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr28,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr32,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr36,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr40,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr44,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr48,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr52,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr56,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr60,fcc0,cc5,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr0,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr4,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr8,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr12,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr16,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr20,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr24,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr28,fr28,fcc0,cc5,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr32,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr36,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr40,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr44,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr48,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr52,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr56,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr60,fcc0,cc5,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr0,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr4,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr8,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr12,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr16,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr20,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr24,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr28,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr32,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr36,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr40,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr44,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr48,fr48,fcc0,cc5,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr48,fr52,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr56,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr60,fcc0,cc5,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr0,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr4,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr8,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr12,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr16,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr20,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr24,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr28,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr32,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr36,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr40,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr44,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr48,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr52,fr52,fcc0,cc5,1 - test_fcc 0x7,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr56,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr60,fcc0,cc5,1 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr0,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr4,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr8,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr12,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr16,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr20,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr24,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr28,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr32,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr36,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr40,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr44,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr48,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr52,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr56,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr60,fcc0,cc5,1 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr0,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr4,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr8,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr12,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr16,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr20,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr24,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr28,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr32,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr36,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr40,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr44,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr48,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr52,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr56,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr60,fcc0,cc5,1 - test_fcc 0xe,0 -; - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr0,fr0,fcc0,cc2,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr4,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr8,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr12,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr16,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr20,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr24,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr28,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr32,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr36,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr40,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr44,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr48,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr52,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr56,fcc0,cc2,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr60,fcc0,cc2,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr4,fr0,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr4,fr4,fcc0,cc2,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr8,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr12,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr16,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr20,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr24,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr28,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr32,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr36,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr40,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr44,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr48,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr52,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr56,fcc0,cc2,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr60,fcc0,cc2,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr0,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr4,fcc0,cc2,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr8,fr8,fcc0,cc2,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr12,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr16,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr20,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr24,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr28,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr32,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr36,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr40,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr44,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr48,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr52,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr56,fcc0,cc2,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr60,fcc0,cc2,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr0,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr4,fcc0,cc2,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr8,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr12,fr12,fcc0,cc2,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr16,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr20,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr24,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr28,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr32,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr36,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr40,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr44,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr48,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr52,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr56,fcc0,cc2,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr60,fcc0,cc2,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr0,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr4,fcc0,cc2,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr8,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr12,fcc0,cc2,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr16,fcc0,cc2,1 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr20,fcc0,cc2,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr24,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr28,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr32,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr36,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr40,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr44,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr48,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr52,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr56,fcc0,cc2,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr60,fcc0,cc2,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr0,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr4,fcc0,cc2,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr8,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr12,fcc0,cc2,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr16,fcc0,cc2,1 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr20,fcc0,cc2,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr24,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr28,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr32,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr36,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr40,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr44,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr48,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr52,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr56,fcc0,cc2,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr60,fcc0,cc2,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr0,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr4,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr8,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr12,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr16,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr20,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr24,fr24,fcc0,cc6,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr28,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr32,fcc0,cc6,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr36,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr40,fcc0,cc6,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr44,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr48,fcc0,cc6,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr52,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr56,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr60,fcc0,cc6,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr0,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr4,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr8,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr12,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr16,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr20,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr24,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr28,fr28,fcc0,cc6,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr32,fcc0,cc6,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr36,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr40,fcc0,cc6,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr44,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr48,fcc0,cc6,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr52,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr56,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr60,fcc0,cc6,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr0,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr4,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr8,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr12,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr16,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr20,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr24,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr28,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr32,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr36,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr40,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr44,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr48,fr48,fcc0,cc6,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr48,fr52,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr56,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr60,fcc0,cc6,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr0,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr4,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr8,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr12,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr16,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr20,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr24,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr28,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr32,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr36,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr40,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr44,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr48,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr52,fr52,fcc0,cc6,0 - test_fcc 0x7,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr56,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr60,fcc0,cc6,0 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr0,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr4,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr8,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr12,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr16,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr20,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr24,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr28,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr32,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr36,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr40,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr44,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr48,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr52,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr56,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr60,fcc0,cc6,0 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr0,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr4,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr8,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr12,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr16,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr20,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr24,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr28,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr32,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr36,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr40,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr44,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr48,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr52,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr56,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr60,fcc0,cc6,1 - test_fcc 0xe,0 - - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr0,fr0,fcc0,cc3,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr4,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr8,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr12,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr16,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr20,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr24,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr28,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr32,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr36,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr40,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr44,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr48,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr52,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr56,fcc0,cc3,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr60,fcc0,cc3,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr4,fr0,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr4,fr4,fcc0,cc3,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr8,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr12,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr16,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr20,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr24,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr28,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr32,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr36,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr40,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr44,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr48,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr52,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr56,fcc0,cc3,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr60,fcc0,cc3,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr0,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr4,fcc0,cc3,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr8,fr8,fcc0,cc3,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr12,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr16,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr20,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr24,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr28,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr32,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr36,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr40,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr44,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr48,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr52,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr56,fcc0,cc3,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr60,fcc0,cc3,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr0,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr4,fcc0,cc3,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr8,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr12,fr12,fcc0,cc3,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr16,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr20,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr24,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr28,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr32,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr36,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr40,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr44,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr48,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr52,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr56,fcc0,cc3,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr60,fcc0,cc3,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr0,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr4,fcc0,cc3,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr8,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr12,fcc0,cc3,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr16,fcc0,cc3,1 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr20,fcc0,cc3,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr24,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr28,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr32,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr36,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr40,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr44,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr48,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr52,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr56,fcc0,cc3,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr60,fcc0,cc3,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr0,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr4,fcc0,cc3,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr8,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr12,fcc0,cc3,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr16,fcc0,cc3,1 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr20,fcc0,cc3,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr24,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr28,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr32,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr36,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr40,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr44,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr48,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr52,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr56,fcc0,cc3,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr60,fcc0,cc3,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr0,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr4,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr8,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr12,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr16,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr20,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr24,fr24,fcc0,cc7,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr28,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr32,fcc0,cc7,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr36,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr40,fcc0,cc7,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr44,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr48,fcc0,cc7,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr52,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr56,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr60,fcc0,cc7,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr0,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr4,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr8,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr12,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr16,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr20,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr24,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr28,fr28,fcc0,cc7,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr32,fcc0,cc7,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr36,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr40,fcc0,cc7,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr44,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr48,fcc0,cc7,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr52,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr56,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr60,fcc0,cc7,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr0,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr4,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr8,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr12,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr16,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr20,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr24,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr28,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr32,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr36,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr40,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr44,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr48,fr48,fcc0,cc7,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr48,fr52,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr56,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr60,fcc0,cc7,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr0,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr4,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr8,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr12,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr16,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr20,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr24,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr28,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr32,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr36,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr40,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr44,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr48,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr52,fr52,fcc0,cc7,0 - test_fcc 0x7,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr56,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr60,fcc0,cc7,0 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr0,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr4,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr8,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr12,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr16,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr20,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr24,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr28,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr32,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr36,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr40,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr44,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr48,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr52,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr56,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr60,fcc0,cc7,0 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr0,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr4,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr8,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr12,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr16,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr20,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr24,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr28,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr32,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr36,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr40,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr44,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr48,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr52,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr56,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr60,fcc0,cc7,1 - test_fcc 0xe,0 - - pass diff --git a/sim/testsuite/sim/frv/cfdivs.cgs b/sim/testsuite/sim/frv/cfdivs.cgs deleted file mode 100644 index e776f80..0000000 --- a/sim/testsuite/sim/frv/cfdivs.cgs +++ /dev/null @@ -1,696 +0,0 @@ -# frv testcase for cfdivs $FRi,$FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfdivs -cfdivs: - set_spr_immed 0x1b1b,cccr - - cfdivs fr0,fr28,fr1,cc0,1 - test_fr_fr fr1,fr0 - cfdivs fr4,fr28,fr1,cc0,1 - test_fr_fr fr1,fr4 - cfdivs fr8,fr28,fr1,cc0,1 - test_fr_fr fr1,fr8 - cfdivs fr12,fr28,fr1,cc0,1 - test_fr_fr fr1,fr12 - cfdivs fr16,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr24,fr28,fr1,cc0,1 - test_fr_fr fr1,fr24 - cfdivs fr28,fr28,fr1,cc0,1 - test_fr_fr fr1,fr28 - cfdivs fr32,fr28,fr1,cc0,1 - test_fr_fr fr1,fr32 - cfdivs fr36,fr28,fr1,cc0,1 - test_fr_fr fr1,fr36 - cfdivs fr40,fr28,fr1,cc0,1 - test_fr_fr fr1,fr40 - cfdivs fr44,fr28,fr1,cc0,1 - test_fr_fr fr1,fr44 - cfdivs fr48,fr28,fr1,cc0,1 - test_fr_fr fr1,fr48 - cfdivs fr52,fr28,fr1,cc0,1 - test_fr_fr fr1,fr52 - - cfdivs fr16,fr0,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr32,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr36,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr40,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr44,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr48,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr52,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfdivs fr20,fr0,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr4,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr8,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr12,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr24,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr28,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr32,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr36,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr40,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr44,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr48,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr52,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfdivs fr8,fr28,fr1,cc4,1 - test_fr_fr fr1,fr8 - cfdivs fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - - cfdivs fr40,fr32,fr1,cc4,1 - test_fr_fr fr1,fr36 -; - cfdivs fr0,fr28,fr1,cc1,0 - test_fr_fr fr1,fr0 - cfdivs fr4,fr28,fr1,cc1,0 - test_fr_fr fr1,fr4 - cfdivs fr8,fr28,fr1,cc1,0 - test_fr_fr fr1,fr8 - cfdivs fr12,fr28,fr1,cc1,0 - test_fr_fr fr1,fr12 - cfdivs fr16,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr24,fr28,fr1,cc1,0 - test_fr_fr fr1,fr24 - cfdivs fr28,fr28,fr1,cc1,0 - test_fr_fr fr1,fr28 - cfdivs fr32,fr28,fr1,cc1,0 - test_fr_fr fr1,fr32 - cfdivs fr36,fr28,fr1,cc1,0 - test_fr_fr fr1,fr36 - cfdivs fr40,fr28,fr1,cc1,0 - test_fr_fr fr1,fr40 - cfdivs fr44,fr28,fr1,cc1,0 - test_fr_fr fr1,fr44 - cfdivs fr48,fr28,fr1,cc1,0 - test_fr_fr fr1,fr48 - cfdivs fr52,fr28,fr1,cc1,0 - test_fr_fr fr1,fr52 - - cfdivs fr16,fr0,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr32,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr36,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr40,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr44,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr48,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr52,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfdivs fr20,fr0,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr4,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr8,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr12,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr24,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr28,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr32,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr36,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr40,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr44,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr48,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr52,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfdivs fr8,fr28,fr1,cc5,0 - test_fr_fr fr1,fr8 - cfdivs fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - - cfdivs fr40,fr32,fr1,cc5,0 - test_fr_fr fr1,fr36 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfdivs fr0,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr4,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr8,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr12,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr24,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr32,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr36,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr40,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr44,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr48,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr52,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr16,fr0,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr4,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr24,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr44,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr48,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr20,fr0,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr4,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr8,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr12,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr24,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr44,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr48,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr8,fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr8,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr40,fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfdivs fr0,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr4,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr8,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr12,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr24,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr32,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr36,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr40,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr44,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr48,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr52,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr16,fr0,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr4,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr24,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr44,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr48,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr20,fr0,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr4,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr8,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr12,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr24,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr44,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr48,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr8,fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr8,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr40,fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfdivs fr0,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr4,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr8,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr12,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr24,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr32,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr36,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr40,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr44,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr48,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr52,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr16,fr0,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr4,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr8,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr12,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr24,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr32,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr36,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr40,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr44,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr48,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr52,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr20,fr0,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr4,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr8,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr12,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr24,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr32,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr36,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr40,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr44,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr48,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr52,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr8,fr28,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr8,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr40,fr32,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfdivs fr0,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr4,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr8,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr12,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr24,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr32,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr36,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr40,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr44,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr48,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr52,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr16,fr0,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr4,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr8,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr12,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr24,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr32,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr36,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr40,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr44,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr48,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr52,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr20,fr0,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr4,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr8,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr12,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr24,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr32,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr36,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr40,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr44,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr48,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr52,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr8,fr28,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr8,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr40,fr32,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfitos.cgs b/sim/testsuite/sim/frv/cfitos.cgs deleted file mode 100644 index b24184e..0000000 --- a/sim/testsuite/sim/frv/cfitos.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for cfitos $FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfitos -cfitos: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0,0,fr1 - cfitos fr1,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_iimmed 0x0000,0x0002,fr1 - cfitos fr1,fr1,cc0,1 - test_fr_fr fr1,fr32 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfitos fr1,fr1,cc4,1 - test_fr_iimmed 0xce054904,fr1 - - set_fr_iimmed 0,0,fr1 - cfitos fr1,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_iimmed 0x0000,0x0002,fr1 - cfitos fr1,fr1,cc1,0 - test_fr_fr fr1,fr32 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfitos fr1,fr1,cc5,0 - test_fr_iimmed 0xce054904,fr1 - - set_fr_iimmed 0,0,fr1 - cfitos fr1,fr1,cc0,0 - test_fr_iimmed 0,fr1 - - set_fr_iimmed 0x0000,0x0002,fr1 - cfitos fr1,fr1,cc0,0 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfitos fr1,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0,0,fr1 - cfitos fr1,fr1,cc1,1 - test_fr_iimmed 0,fr1 - - set_fr_iimmed 0x0000,0x0002,fr1 - cfitos fr1,fr1,cc1,1 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfitos fr1,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0,0,fr1 - cfitos fr1,fr1,cc2,1 - test_fr_iimmed 0,fr1 - - set_fr_iimmed 0x0000,0x0002,fr1 - cfitos fr1,fr1,cc2,0 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfitos fr1,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0,0,fr1 - cfitos fr1,fr1,cc3,0 - test_fr_iimmed 0,fr1 - - set_fr_iimmed 0x0000,0x0002,fr1 - cfitos fr1,fr1,cc3,1 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfitos fr1,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfmadds.cgs b/sim/testsuite/sim/frv/cfmadds.cgs deleted file mode 100644 index a30f7bf..0000000 --- a/sim/testsuite/sim/frv/cfmadds.cgs +++ /dev/null @@ -1,627 +0,0 @@ -# frv testcase for cfmadds $GRi,$GRj,$GRk,$CCi,$cond -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfmadds -cfmadds: - set_spr_immed 0x1b1b,cccr - - set_fr_fr fr16,fr1 - cfmadds fr16,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr32,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr36,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr40,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr44,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr48,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmadds fr20,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr32,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr36,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr40,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr44,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr48,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_fr fr16,fr1 - cfmadds fr28,fr0,fr1,cc4,1 - test_fr_fr fr1,fr0 - set_fr_fr fr16,fr1 - cfmadds fr28,fr4,fr1,cc4,1 - test_fr_fr fr1,fr4 - set_fr_fr fr16,fr1 - cfmadds fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - set_fr_fr fr16,fr1 - cfmadds fr28,fr12,fr1,cc4,1 - test_fr_fr fr1,fr12 - set_fr_fr fr16,fr1 - cfmadds fr28,fr16,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmadds fr28,fr20,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmadds fr28,fr24,fr1,cc4,1 - test_fr_fr fr1,fr24 - set_fr_fr fr16,fr1 - cfmadds fr28,fr28,fr1,cc4,1 - test_fr_fr fr1,fr28 - set_fr_fr fr16,fr1 - cfmadds fr28,fr32,fr1,cc4,1 - test_fr_fr fr1,fr32 - set_fr_fr fr16,fr1 - cfmadds fr28,fr36,fr1,cc4,1 - test_fr_fr fr1,fr36 - set_fr_fr fr16,fr1 - cfmadds fr28,fr40,fr1,cc4,1 - test_fr_fr fr1,fr40 - set_fr_fr fr16,fr1 - cfmadds fr28,fr44,fr1,cc4,1 - test_fr_fr fr1,fr44 - set_fr_fr fr16,fr1 - cfmadds fr28,fr48,fr1,cc4,1 - test_fr_fr fr1,fr48 - set_fr_fr fr16,fr1 - cfmadds fr28,fr52,fr1,cc4,1 - test_fr_fr fr1,fr52 - - set_fr_fr fr36,fr1 - cfmadds fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr32 - cfmadds fr8,fr28,fr1,cc4,1 - test_fr_fr fr1,fr28 - - set_fr_fr fr36,fr1 - cfmadds fr32,fr36,fr1,cc4,1 - test_fr_fr fr1,fr44 -; - set_fr_fr fr16,fr1 - cfmadds fr16,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr32,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr36,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr40,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr44,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr48,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmadds fr20,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr32,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr36,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr40,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr44,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr48,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_fr fr16,fr1 - cfmadds fr28,fr0,fr1,cc5,0 - test_fr_fr fr1,fr0 - set_fr_fr fr16,fr1 - cfmadds fr28,fr4,fr1,cc5,0 - test_fr_fr fr1,fr4 - set_fr_fr fr16,fr1 - cfmadds fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - set_fr_fr fr16,fr1 - cfmadds fr28,fr12,fr1,cc5,0 - test_fr_fr fr1,fr12 - set_fr_fr fr16,fr1 - cfmadds fr28,fr16,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmadds fr28,fr20,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmadds fr28,fr24,fr1,cc5,0 - test_fr_fr fr1,fr24 - set_fr_fr fr16,fr1 - cfmadds fr28,fr28,fr1,cc5,0 - test_fr_fr fr1,fr28 - set_fr_fr fr16,fr1 - cfmadds fr28,fr32,fr1,cc5,0 - test_fr_fr fr1,fr32 - set_fr_fr fr16,fr1 - cfmadds fr28,fr36,fr1,cc5,0 - test_fr_fr fr1,fr36 - set_fr_fr fr16,fr1 - cfmadds fr28,fr40,fr1,cc5,0 - test_fr_fr fr1,fr40 - set_fr_fr fr16,fr1 - cfmadds fr28,fr44,fr1,cc5,0 - test_fr_fr fr1,fr44 - set_fr_fr fr16,fr1 - cfmadds fr28,fr48,fr1,cc5,0 - test_fr_fr fr1,fr48 - set_fr_fr fr16,fr1 - cfmadds fr28,fr52,fr1,cc5,0 - test_fr_fr fr1,fr52 - - set_fr_fr fr36,fr1 - cfmadds fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr32 - cfmadds fr8,fr28,fr1,cc5,0 - test_fr_fr fr1,fr28 - - set_fr_fr fr36,fr1 - cfmadds fr32,fr36,fr1,cc5,0 - test_fr_fr fr1,fr44 -; - set_fr_fr fr48,fr1 - cfmadds fr16,fr4,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr8,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr12,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr16,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr20,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr24,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr28,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr32,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr36,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr40,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr44,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr48,fr1,cc0,0 - test_fr_fr fr1,fr48 - - cfmadds fr20,fr4,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr8,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr12,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr16,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr20,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr24,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr28,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr32,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr36,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr40,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr44,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr48,fr1,cc4,0 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr0,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr4,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr8,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr12,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr16,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr20,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr24,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr28,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr32,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr36,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr40,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr44,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr48,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr52,fr1,cc4,0 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr8,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr8,fr28,fr1,cc4,0 - test_fr_fr fr1,fr48 - - cfmadds fr32,fr36,fr1,cc4,0 - test_fr_fr fr1,fr48 -; - set_fr_fr fr48,fr1 - cfmadds fr16,fr4,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr8,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr12,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr16,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr20,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr24,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr28,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr32,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr36,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr40,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr44,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr48,fr1,cc1,1 - test_fr_fr fr1,fr48 - - cfmadds fr20,fr4,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr8,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr12,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr16,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr20,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr24,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr28,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr32,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr36,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr40,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr44,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr48,fr1,cc5,1 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr0,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr4,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr8,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr12,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr16,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr20,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr24,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr28,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr32,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr36,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr40,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr44,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr48,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr52,fr1,cc5,1 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr8,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr8,fr28,fr1,cc5,1 - test_fr_fr fr1,fr48 - - cfmadds fr32,fr36,fr1,cc5,1 - test_fr_fr fr1,fr48 -; - set_fr_fr fr48,fr1 - cfmadds fr16,fr4,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr8,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr12,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr16,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr20,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr24,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr28,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr32,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr36,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr40,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr44,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr48,fr1,cc2,0 - test_fr_fr fr1,fr48 - - cfmadds fr20,fr4,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr8,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr12,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr16,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr20,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr24,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr28,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr32,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr36,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr40,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr44,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr48,fr1,cc6,0 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr0,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr4,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr8,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr12,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr16,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr20,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr24,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr28,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr32,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr36,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr40,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr44,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr48,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr52,fr1,cc6,0 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr8,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr8,fr28,fr1,cc6,0 - test_fr_fr fr1,fr48 - - cfmadds fr32,fr36,fr1,cc6,1 - test_fr_fr fr1,fr48 -; - set_fr_fr fr48,fr1 - cfmadds fr16,fr4,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr8,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr12,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr16,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr20,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr24,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr28,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr32,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr36,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr40,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr44,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr48,fr1,cc3,0 - test_fr_fr fr1,fr48 - - cfmadds fr20,fr4,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr8,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr12,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr16,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr20,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr24,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr28,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr32,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr36,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr40,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr44,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr48,fr1,cc7,0 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr0,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr4,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr8,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr12,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr16,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr20,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr24,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr28,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr32,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr36,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr40,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr44,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr48,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr52,fr1,cc7,0 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr8,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr8,fr28,fr1,cc7,0 - test_fr_fr fr1,fr48 - - cfmadds fr32,fr36,fr1,cc7,1 - test_fr_fr fr1,fr48 -; - pass diff --git a/sim/testsuite/sim/frv/cfmas.cgs b/sim/testsuite/sim/frv/cfmas.cgs deleted file mode 100644 index 8c0dc05..0000000 --- a/sim/testsuite/sim/frv/cfmas.cgs +++ /dev/null @@ -1,775 +0,0 @@ -# frv testcase for cfmas $FRi,$FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global cfmas -cfmas: - set_spr_immed 0x1b1b,cccr - - cfmas fr16,fr4,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - cfmas fr16,fr8,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmas fr16,fr12,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - cfmas fr16,fr16,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr16,fr20,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr16,fr24,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - cfmas fr16,fr28,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmas fr16,fr32,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - cfmas fr16,fr36,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - cfmas fr16,fr40,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - cfmas fr16,fr44,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - cfmas fr16,fr48,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - cfmas fr20,fr4,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - cfmas fr20,fr8,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmas fr20,fr12,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - cfmas fr20,fr16,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr20,fr20,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr20,fr24,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - cfmas fr20,fr28,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmas fr20,fr32,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - cfmas fr20,fr36,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - cfmas fr20,fr40,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - cfmas fr20,fr44,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - cfmas fr20,fr48,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - cfmas fr28,fr0,fr2,cc4,1 - test_fr_fr fr2,fr0 - cfmas fr28,fr4,fr2,cc4,1 - test_fr_fr fr2,fr4 - cfmas fr28,fr8,fr2,cc4,1 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr28,fr12,fr2,cc4,1 - test_fr_fr fr2,fr12 - cfmas fr28,fr16,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmas fr28,fr20,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmas fr28,fr24,fr2,cc4,1 - test_fr_fr fr2,fr24 - cfmas fr28,fr28,fr2,cc4,1 - test_fr_fr fr2,fr28 - cfmas fr28,fr32,fr2,cc4,1 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr36 - cfmas fr28,fr36,fr2,cc4,1 - test_fr_fr fr2,fr36 - cfmas fr28,fr40,fr2,cc4,1 - test_fr_fr fr2,fr40 - cfmas fr28,fr44,fr2,cc4,1 - test_fr_fr fr2,fr44 - cfmas fr28,fr48,fr2,cc4,1 - test_fr_fr fr2,fr48 - cfmas fr28,fr52,fr2,cc4,1 - test_fr_fr fr2,fr52 - - cfmas fr28,fr8,fr2,cc4,1 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr8,fr28,fr2,cc4,1 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - cfmas fr32,fr36,fr2,cc4,1 - test_fr_fr fr2,fr40 -; - cfmas fr16,fr4,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - cfmas fr16,fr8,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmas fr16,fr12,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - cfmas fr16,fr16,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr16,fr20,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr16,fr24,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - cfmas fr16,fr28,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmas fr16,fr32,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - cfmas fr16,fr36,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - cfmas fr16,fr40,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - cfmas fr16,fr44,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - cfmas fr16,fr48,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - cfmas fr20,fr4,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - cfmas fr20,fr8,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmas fr20,fr12,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - cfmas fr20,fr16,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr20,fr20,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr20,fr24,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - cfmas fr20,fr28,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmas fr20,fr32,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - cfmas fr20,fr36,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - cfmas fr20,fr40,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - cfmas fr20,fr44,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - cfmas fr20,fr48,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - cfmas fr28,fr0,fr2,cc5,0 - test_fr_fr fr2,fr0 - cfmas fr28,fr4,fr2,cc5,0 - test_fr_fr fr2,fr4 - cfmas fr28,fr8,fr2,cc5,0 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr28,fr12,fr2,cc5,0 - test_fr_fr fr2,fr12 - cfmas fr28,fr16,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmas fr28,fr20,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmas fr28,fr24,fr2,cc5,0 - test_fr_fr fr2,fr24 - cfmas fr28,fr28,fr2,cc5,0 - test_fr_fr fr2,fr28 - cfmas fr28,fr32,fr2,cc5,0 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr36 - cfmas fr28,fr36,fr2,cc5,0 - test_fr_fr fr2,fr36 - cfmas fr28,fr40,fr2,cc5,0 - test_fr_fr fr2,fr40 - cfmas fr28,fr44,fr2,cc5,0 - test_fr_fr fr2,fr44 - cfmas fr28,fr48,fr2,cc5,0 - test_fr_fr fr2,fr48 - cfmas fr28,fr52,fr2,cc5,0 - test_fr_fr fr2,fr52 - - cfmas fr28,fr8,fr2,cc5,0 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr8,fr28,fr2,cc5,0 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - cfmas fr32,fr36,fr2,cc5,0 - test_fr_fr fr2,fr40 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmas fr16,fr4,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr8,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr12,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr16,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr20,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr24,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr28,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr32,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr36,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr40,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr44,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr48,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr20,fr4,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr8,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr12,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr16,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr20,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr24,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr20,fr28,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr32,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr36,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr40,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr44,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr48,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr28,fr0,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr4,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr8,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr12,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr16,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr20,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr24,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr28,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr32,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr36,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr40,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr44,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr48,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr52,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - - cfmas fr28,fr8,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr8,fr28,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr32,fr36,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmas fr16,fr4,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr8,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr12,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr16,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr20,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr24,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr28,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr32,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr36,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr40,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr44,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr48,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr20,fr4,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr8,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr12,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr16,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr20,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr24,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr20,fr28,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr32,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr36,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr40,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr44,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr48,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr28,fr0,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr4,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr8,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr12,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr16,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr20,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr24,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr28,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr32,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr36,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr40,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr44,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr48,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr52,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - - cfmas fr28,fr8,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr8,fr28,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr32,fr36,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmas fr16,fr4,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr8,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr12,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr16,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr20,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr24,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr28,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr32,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr36,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr40,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr44,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr48,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr20,fr4,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr8,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr12,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr16,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr20,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr24,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr20,fr28,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr32,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr36,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr40,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr44,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr48,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr28,fr0,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr4,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr8,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr12,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr16,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr20,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr24,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr28,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr32,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr36,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr40,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr44,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr48,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr52,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - - cfmas fr28,fr8,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr8,fr28,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr32,fr36,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmas fr16,fr4,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr8,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr12,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr16,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr20,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr24,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr28,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr32,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr36,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr40,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr44,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr48,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr20,fr4,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr8,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr12,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr16,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr20,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr24,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr20,fr28,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr32,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr36,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr40,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr44,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr48,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr28,fr0,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr4,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr8,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr12,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr16,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr20,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr24,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr28,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr32,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr36,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr40,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr44,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr48,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr52,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - - cfmas fr28,fr8,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr8,fr28,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr32,fr36,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - - pass diff --git a/sim/testsuite/sim/frv/cfmovs.cgs b/sim/testsuite/sim/frv/cfmovs.cgs deleted file mode 100644 index 310bac3..0000000 --- a/sim/testsuite/sim/frv/cfmovs.cgs +++ /dev/null @@ -1,216 +0,0 @@ -# frv testcase for cfmovs $FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfmovs -cfmovs: - set_spr_immed 0x1b1b,cccr - - cfmovs fr0,fr1,cc0,1 - test_fr_fr fr0,fr1 - cfmovs fr4,fr1,cc0,1 - test_fr_fr fr4,fr1 - cfmovs fr8,fr1,cc0,1 - test_fr_fr fr8,fr1 - cfmovs fr12,fr1,cc0,1 - test_fr_fr fr12,fr1 - cfmovs fr16,fr1,cc0,1 - test_fr_fr fr16,fr1 - cfmovs fr20,fr1,cc0,1 - test_fr_fr fr20,fr1 - cfmovs fr24,fr1,cc0,1 - test_fr_fr fr24,fr1 - cfmovs fr28,fr1,cc0,1 - test_fr_fr fr28,fr1 - cfmovs fr32,fr1,cc4,1 - test_fr_fr fr32,fr1 - cfmovs fr36,fr1,cc4,1 - test_fr_fr fr36,fr1 - cfmovs fr40,fr1,cc4,1 - test_fr_fr fr40,fr1 - cfmovs fr44,fr1,cc4,1 - test_fr_fr fr44,fr1 - cfmovs fr48,fr1,cc4,1 - test_fr_fr fr48,fr1 - cfmovs fr52,fr1,cc4,1 - test_fr_fr fr52,fr1 - cfmovs fr56,fr1,cc4,1 - test_fr_iimmed 0x7fc00000,fr1 - cfmovs fr60,fr1,cc4,1 - test_fr_iimmed 0x7f800001,fr1 - - cfmovs fr0,fr1,cc1,0 - test_fr_fr fr0,fr1 - cfmovs fr4,fr1,cc1,0 - test_fr_fr fr4,fr1 - cfmovs fr8,fr1,cc1,0 - test_fr_fr fr8,fr1 - cfmovs fr12,fr1,cc1,0 - test_fr_fr fr12,fr1 - cfmovs fr16,fr1,cc1,0 - test_fr_fr fr16,fr1 - cfmovs fr20,fr1,cc1,0 - test_fr_fr fr20,fr1 - cfmovs fr24,fr1,cc1,0 - test_fr_fr fr24,fr1 - cfmovs fr28,fr1,cc1,0 - test_fr_fr fr28,fr1 - cfmovs fr32,fr1,cc5,0 - test_fr_fr fr32,fr1 - cfmovs fr36,fr1,cc5,0 - test_fr_fr fr36,fr1 - cfmovs fr40,fr1,cc5,0 - test_fr_fr fr40,fr1 - cfmovs fr44,fr1,cc5,0 - test_fr_fr fr44,fr1 - cfmovs fr48,fr1,cc5,0 - test_fr_fr fr48,fr1 - cfmovs fr52,fr1,cc5,0 - test_fr_fr fr52,fr1 - cfmovs fr56,fr1,cc5,0 - test_fr_iimmed 0x7fc00000,fr1 - cfmovs fr60,fr1,cc5,0 - test_fr_iimmed 0x7f800001,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmovs fr0,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr4,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr20,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr24,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr44,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr48,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr56,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr60,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmovs fr0,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr4,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr20,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr24,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr44,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr48,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr56,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr60,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmovs fr0,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr4,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr8,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr12,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr20,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr24,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr32,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr36,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr40,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr44,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr48,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr52,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr56,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr60,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmovs fr0,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr4,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr8,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr12,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr20,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr24,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr32,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr36,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr40,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr44,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr48,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr52,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr56,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr60,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfmss.cgs b/sim/testsuite/sim/frv/cfmss.cgs deleted file mode 100644 index c31fba3..0000000 --- a/sim/testsuite/sim/frv/cfmss.cgs +++ /dev/null @@ -1,697 +0,0 @@ -# frv testcase for cfmss $FRi,$FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global cfmss -cfmss: - set_spr_immed 0x1b1b,cccr - - cfmss fr16,fr4,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr8,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr16,fr12,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr16,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr16,fr20,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr16,fr24,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr28,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmss fr16,fr32,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr36,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr40,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr44,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr48,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - cfmss fr20,fr4,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr8,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr20,fr12,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr16,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr20,fr20,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr20,fr24,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr28,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmss fr20,fr32,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr36,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr40,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr44,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr48,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - cfmss fr28,fr0,fr2,cc4,1 - test_fr_fr fr2,fr0 - cfmss fr28,fr4,fr2,cc4,1 - test_fr_fr fr2,fr4 - cfmss fr28,fr8,fr2,cc4,1 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - cfmss fr28,fr12,fr2,cc4,1 - test_fr_fr fr2,fr12 - cfmss fr28,fr16,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr28,fr20,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr28,fr24,fr2,cc4,1 - test_fr_fr fr2,fr24 - cfmss fr28,fr28,fr2,cc4,1 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - cfmss fr28,fr32,fr2,cc4,1 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr8 - cfmss fr28,fr36,fr2,cc4,1 - test_fr_fr fr2,fr36 - cfmss fr28,fr40,fr2,cc4,1 - test_fr_fr fr2,fr40 - cfmss fr28,fr44,fr2,cc4,1 - test_fr_fr fr2,fr44 - cfmss fr28,fr48,fr2,cc4,1 - test_fr_fr fr2,fr48 - cfmss fr28,fr52,fr2,cc4,1 - test_fr_fr fr2,fr52 - - cfmss fr28,fr8,fr2,cc4,1 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - cfmss fr8,fr28,fr2,cc4,1 - test_fr_fr fr2,fr8 - - cfmss fr32,fr36,fr2,cc4,1 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr8 -; - cfmss fr16,fr4,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr8,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr16,fr12,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr16,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr16,fr20,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr16,fr24,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr28,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmss fr16,fr32,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr36,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr40,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr44,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr48,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - cfmss fr20,fr4,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr8,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr20,fr12,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr16,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr20,fr20,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr20,fr24,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr28,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmss fr20,fr32,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr36,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr40,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr44,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr48,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - cfmss fr28,fr0,fr2,cc5,0 - test_fr_fr fr2,fr0 - cfmss fr28,fr4,fr2,cc5,0 - test_fr_fr fr2,fr4 - cfmss fr28,fr8,fr2,cc5,0 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - cfmss fr28,fr12,fr2,cc5,0 - test_fr_fr fr2,fr12 - cfmss fr28,fr16,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr28,fr20,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr28,fr24,fr2,cc5,0 - test_fr_fr fr2,fr24 - cfmss fr28,fr28,fr2,cc5,0 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - cfmss fr28,fr32,fr2,cc5,0 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr8 - cfmss fr28,fr36,fr2,cc5,0 - test_fr_fr fr2,fr36 - cfmss fr28,fr40,fr2,cc5,0 - test_fr_fr fr2,fr40 - cfmss fr28,fr44,fr2,cc5,0 - test_fr_fr fr2,fr44 - cfmss fr28,fr48,fr2,cc5,0 - test_fr_fr fr2,fr48 - cfmss fr28,fr52,fr2,cc5,0 - test_fr_fr fr2,fr52 - - cfmss fr28,fr8,fr2,cc5,0 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - cfmss fr8,fr28,fr2,cc5,0 - test_fr_fr fr2,fr8 - - cfmss fr32,fr36,fr2,cc5,0 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr8 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmss fr16,fr4,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr8,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr12,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr16,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr20,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr24,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr28,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr32,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr36,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr40,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr44,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr48,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr20,fr4,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr8,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr12,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr16,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr20,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr24,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr28,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr32,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr36,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr40,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr44,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr48,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr0,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr4,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr8,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr12,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr16,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr20,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr24,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr28,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr32,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr36,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr40,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr44,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr48,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr52,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr8,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr8,fr28,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr32,fr36,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmss fr16,fr4,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr8,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr12,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr16,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr20,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr24,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr28,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr32,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr36,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr40,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr44,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr48,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr20,fr4,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr8,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr12,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr16,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr20,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr24,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr28,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr32,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr36,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr40,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr44,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr48,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr0,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr4,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr8,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr12,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr16,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr20,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr24,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr28,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr32,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr36,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr40,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr44,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr48,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr52,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr8,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr8,fr28,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr32,fr36,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmss fr16,fr4,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr8,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr12,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr16,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr20,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr24,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr28,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr32,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr36,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr40,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr44,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr48,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr20,fr4,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr8,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr12,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr16,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr20,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr24,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr28,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr32,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr36,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr40,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr44,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr48,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr0,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr4,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr8,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr12,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr16,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr20,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr24,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr28,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr32,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr36,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr40,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr44,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr48,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr52,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr8,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr8,fr28,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr32,fr36,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmss fr16,fr4,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr8,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr12,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr16,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr20,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr24,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr28,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr32,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr36,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr40,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr44,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr48,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr20,fr4,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr8,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr12,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr16,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr20,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr24,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr28,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr32,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr36,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr40,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr44,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr48,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr0,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr4,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr8,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr12,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr16,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr20,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr24,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr28,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr32,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr36,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr40,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr44,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr48,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr52,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr8,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr8,fr28,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr32,fr36,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - pass diff --git a/sim/testsuite/sim/frv/cfmsubs.cgs b/sim/testsuite/sim/frv/cfmsubs.cgs deleted file mode 100644 index bc74da4..0000000 --- a/sim/testsuite/sim/frv/cfmsubs.cgs +++ /dev/null @@ -1,629 +0,0 @@ -# frv testcase for cfmsubs $GRi,$GRj,$GRk,$CCi,$cond -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfmsubs -cfmsubs: - set_spr_immed 0x1b1b,cccr - - set_fr_fr fr16,fr1 - cfmsubs fr16,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr32,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr36,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr40,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr44,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr48,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmsubs fr20,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr32,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr36,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr40,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr44,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr48,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_fr fr16,fr1 - cfmsubs fr28,fr0,fr1,cc4,1 - test_fr_fr fr1,fr0 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr4,fr1,cc4,1 - test_fr_fr fr1,fr4 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr12,fr1,cc4,1 - test_fr_fr fr1,fr12 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr16,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr20,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr24,fr1,cc4,1 - test_fr_fr fr1,fr24 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr28,fr1,cc4,1 - test_fr_fr fr1,fr28 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr32,fr1,cc4,1 - test_fr_fr fr1,fr32 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr36,fr1,cc4,1 - test_fr_fr fr1,fr36 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr40,fr1,cc4,1 - test_fr_fr fr1,fr40 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr44,fr1,cc4,1 - test_fr_fr fr1,fr44 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr48,fr1,cc4,1 - test_fr_fr fr1,fr48 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr52,fr1,cc4,1 - test_fr_fr fr1,fr52 - - set_fr_fr fr32,fr1 - cfmsubs fr8,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - set_fr_fr fr36,fr1 - cfmsubs fr36,fr36,fr1,cc4,1 - test_fr_fr fr1,fr40 - - cfmsubs fr32,fr36,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 -; - set_fr_fr fr16,fr1 - cfmsubs fr16,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr32,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr36,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr40,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr44,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr48,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmsubs fr20,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr32,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr36,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr40,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr44,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr48,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_fr fr16,fr1 - cfmsubs fr28,fr0,fr1,cc5,0 - test_fr_fr fr1,fr0 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr4,fr1,cc5,0 - test_fr_fr fr1,fr4 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr12,fr1,cc5,0 - test_fr_fr fr1,fr12 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr16,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr20,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr24,fr1,cc5,0 - test_fr_fr fr1,fr24 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr28,fr1,cc5,0 - test_fr_fr fr1,fr28 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr32,fr1,cc5,0 - test_fr_fr fr1,fr32 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr36,fr1,cc5,0 - test_fr_fr fr1,fr36 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr40,fr1,cc5,0 - test_fr_fr fr1,fr40 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr44,fr1,cc5,0 - test_fr_fr fr1,fr44 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr48,fr1,cc5,0 - test_fr_fr fr1,fr48 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr52,fr1,cc5,0 - test_fr_fr fr1,fr52 - - set_fr_fr fr32,fr1 - cfmsubs fr8,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - set_fr_fr fr36,fr1 - cfmsubs fr36,fr36,fr1,cc5,0 - test_fr_fr fr1,fr40 - - cfmsubs fr32,fr36,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 -; - set_fr_fr fr48,fr1 - cfmsubs fr16,fr4,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr8,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr12,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr16,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr20,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr24,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr28,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr32,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr36,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr40,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr44,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr48,fr1,cc0,0 - test_fr_fr fr1,fr48 - - cfmsubs fr20,fr4,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr8,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr12,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr16,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr20,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr24,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr28,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr32,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr36,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr40,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr44,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr48,fr1,cc4,0 - test_fr_fr fr1,fr48 - - cfmsubs fr28,fr0,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr4,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr8,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr12,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr16,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr20,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr24,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr28,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr32,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr36,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr40,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr44,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr48,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr52,fr1,cc4,0 - test_fr_fr fr1,fr48 - - cfmsubs fr8,fr8,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr36,fr36,fr1,cc4,0 - test_fr_fr fr1,fr48 - - cfmsubs fr32,fr36,fr1,cc4,0 - test_fr_fr fr1,fr48 -; - set_fr_fr fr48,fr1 - cfmsubs fr16,fr4,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr8,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr12,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr16,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr20,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr24,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr28,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr32,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr36,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr40,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr44,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr48,fr1,cc1,1 - test_fr_fr fr1,fr48 - - cfmsubs fr20,fr4,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr8,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr12,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr16,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr20,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr24,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr28,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr32,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr36,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr40,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr44,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr48,fr1,cc5,1 - test_fr_fr fr1,fr48 - - cfmsubs fr28,fr0,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr4,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr8,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr12,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr16,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr20,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr24,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr28,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr32,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr36,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr40,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr44,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr48,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr52,fr1,cc5,1 - test_fr_fr fr1,fr48 - - cfmsubs fr8,fr8,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr36,fr36,fr1,cc5,1 - test_fr_fr fr1,fr48 - - cfmsubs fr32,fr36,fr1,cc5,1 - test_fr_fr fr1,fr48 -; - set_fr_fr fr48,fr1 - cfmsubs fr16,fr4,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr8,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr12,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr16,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr20,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr24,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr28,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr32,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr36,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr40,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr44,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr48,fr1,cc2,1 - test_fr_fr fr1,fr48 - - cfmsubs fr20,fr4,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr8,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr12,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr16,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr20,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr24,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr28,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr32,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr36,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr40,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr44,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr48,fr1,cc6,1 - test_fr_fr fr1,fr48 - - cfmsubs fr28,fr0,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr4,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr8,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr12,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr16,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr20,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr24,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr28,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr32,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr36,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr40,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr44,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr48,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr52,fr1,cc6,1 - test_fr_fr fr1,fr48 - - cfmsubs fr8,fr8,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr36,fr36,fr1,cc6,1 - test_fr_fr fr1,fr48 - - cfmsubs fr32,fr36,fr1,cc6,0 - test_fr_fr fr1,fr48 -; - set_fr_fr fr48,fr1 - cfmsubs fr16,fr4,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr8,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr12,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr16,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr20,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr24,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr28,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr32,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr36,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr40,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr44,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr48,fr1,cc3,1 - test_fr_fr fr1,fr48 - - cfmsubs fr20,fr4,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr8,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr12,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr16,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr20,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr24,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr28,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr32,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr36,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr40,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr44,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr48,fr1,cc7,1 - test_fr_fr fr1,fr48 - - cfmsubs fr28,fr0,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr4,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr8,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr12,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr16,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr20,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr24,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr28,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr32,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr36,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr40,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr44,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr48,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr52,fr1,cc7,1 - test_fr_fr fr1,fr48 - - cfmsubs fr8,fr8,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr36,fr36,fr1,cc7,1 - test_fr_fr fr1,fr48 - - cfmsubs fr32,fr36,fr1,cc7,0 - test_fr_fr fr1,fr48 -; - pass diff --git a/sim/testsuite/sim/frv/cfmuls.cgs b/sim/testsuite/sim/frv/cfmuls.cgs deleted file mode 100644 index 773c95a..0000000 --- a/sim/testsuite/sim/frv/cfmuls.cgs +++ /dev/null @@ -1,696 +0,0 @@ -# frv testcase for cfmuls $FRi,$FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfmuls -cfmuls: - set_spr_immed 0x1b1b,cccr - - cfmuls fr16,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr32,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr36,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr40,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr44,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr48,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmuls fr20,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr32,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr36,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr40,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr44,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr48,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmuls fr28,fr0,fr1,cc4,1 - test_fr_fr fr1,fr0 - cfmuls fr28,fr4,fr1,cc4,1 - test_fr_fr fr1,fr4 - cfmuls fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - cfmuls fr28,fr12,fr1,cc4,1 - test_fr_fr fr1,fr12 - cfmuls fr28,fr16,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr28,fr20,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr28,fr24,fr1,cc4,1 - test_fr_fr fr1,fr24 - cfmuls fr28,fr28,fr1,cc4,1 - test_fr_fr fr1,fr28 - cfmuls fr28,fr32,fr1,cc4,1 - test_fr_fr fr1,fr32 - cfmuls fr28,fr36,fr1,cc4,1 - test_fr_fr fr1,fr36 - cfmuls fr28,fr40,fr1,cc4,1 - test_fr_fr fr1,fr40 - cfmuls fr28,fr44,fr1,cc4,1 - test_fr_fr fr1,fr44 - cfmuls fr28,fr48,fr1,cc4,1 - test_fr_fr fr1,fr48 - cfmuls fr28,fr52,fr1,cc4,1 - test_fr_fr fr1,fr52 - - cfmuls fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - cfmuls fr8,fr28,fr1,cc4,1 - test_fr_fr fr1,fr8 - - cfmuls fr32,fr36,fr1,cc4,1 - test_fr_fr fr1,fr40 -; - cfmuls fr16,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr32,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr36,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr40,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr44,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr48,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmuls fr20,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr32,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr36,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr40,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr44,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr48,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmuls fr28,fr0,fr1,cc5,0 - test_fr_fr fr1,fr0 - cfmuls fr28,fr4,fr1,cc5,0 - test_fr_fr fr1,fr4 - cfmuls fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - cfmuls fr28,fr12,fr1,cc5,0 - test_fr_fr fr1,fr12 - cfmuls fr28,fr16,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr28,fr20,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr28,fr24,fr1,cc5,0 - test_fr_fr fr1,fr24 - cfmuls fr28,fr28,fr1,cc5,0 - test_fr_fr fr1,fr28 - cfmuls fr28,fr32,fr1,cc5,0 - test_fr_fr fr1,fr32 - cfmuls fr28,fr36,fr1,cc5,0 - test_fr_fr fr1,fr36 - cfmuls fr28,fr40,fr1,cc5,0 - test_fr_fr fr1,fr40 - cfmuls fr28,fr44,fr1,cc5,0 - test_fr_fr fr1,fr44 - cfmuls fr28,fr48,fr1,cc5,0 - test_fr_fr fr1,fr48 - cfmuls fr28,fr52,fr1,cc5,0 - test_fr_fr fr1,fr52 - - cfmuls fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - cfmuls fr8,fr28,fr1,cc5,0 - test_fr_fr fr1,fr8 - - cfmuls fr32,fr36,fr1,cc5,0 - test_fr_fr fr1,fr40 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmuls fr16,fr4,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr20,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr24,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr32,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr36,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr40,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr44,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr48,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr20,fr4,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr20,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr24,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr32,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr44,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr48,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr0,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr4,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr8,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr12,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr16,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr24,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr44,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr48,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr8,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr8,fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr32,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmuls fr16,fr4,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr20,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr24,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr32,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr36,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr40,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr44,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr48,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr20,fr4,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr20,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr24,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr32,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr44,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr48,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr0,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr4,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr8,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr12,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr16,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr24,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr44,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr48,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr8,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr8,fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr32,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmuls fr16,fr4,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr8,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr12,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr20,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr24,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr32,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr36,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr40,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr44,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr48,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr20,fr4,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr8,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr12,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr20,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr24,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr32,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr36,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr40,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr44,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr48,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr0,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr4,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr8,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr12,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr16,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr24,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr28,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr32,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr36,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr40,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr44,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr48,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr52,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr8,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr8,fr28,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr32,fr36,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmuls fr16,fr4,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr8,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr12,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr20,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr24,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr32,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr36,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr40,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr44,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr48,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr20,fr4,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr8,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr12,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr20,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr24,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr32,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr36,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr40,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr44,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr48,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr0,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr4,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr8,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr12,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr16,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr24,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr28,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr32,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr36,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr40,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr44,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr48,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr52,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr8,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr8,fr28,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr32,fr36,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfnegs.cgs b/sim/testsuite/sim/frv/cfnegs.cgs deleted file mode 100644 index c1f2b25..0000000 --- a/sim/testsuite/sim/frv/cfnegs.cgs +++ /dev/null @@ -1,96 +0,0 @@ -# frv testcase for cfnegs $FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfnegs -cfnegs: - set_spr_immed 0x1b1b,cccr - - cfnegs fr0,fr1,cc0,1 - test_fr_fr fr1,fr52 - cfnegs fr8,fr1,cc0,1 - test_fr_fr fr1,fr28 - cfnegs fr12,fr1,cc0,1 - test_fr_fr fr1,fr24 - cfnegs fr24,fr1,cc4,1 - test_fr_fr fr1,fr12 - cfnegs fr28,fr1,cc4,1 - test_fr_fr fr1,fr8 - cfnegs fr52,fr1,cc4,1 - test_fr_fr fr1,fr0 - - cfnegs fr0,fr1,cc1,0 - test_fr_fr fr1,fr52 - cfnegs fr8,fr1,cc1,0 - test_fr_fr fr1,fr28 - cfnegs fr12,fr1,cc1,0 - test_fr_fr fr1,fr24 - cfnegs fr24,fr1,cc5,0 - test_fr_fr fr1,fr12 - cfnegs fr28,fr1,cc5,0 - test_fr_fr fr1,fr8 - cfnegs fr52,fr1,cc5,0 - test_fr_fr fr1,fr0 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfnegs fr0,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr24,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfnegs fr0,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr24,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfnegs fr0,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr8,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr12,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr24,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr28,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr52,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfnegs fr0,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr8,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr12,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr24,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr28,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr52,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfsqrts.cgs b/sim/testsuite/sim/frv/cfsqrts.cgs deleted file mode 100644 index ee7a9a5..0000000 --- a/sim/testsuite/sim/frv/cfsqrts.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for cfsqrts $FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfsqrts -cfsqrts: - set_spr_immed 0x1b1b,cccr - - cfsqrts fr44,fr1,cc0,1 ; 9.0 - test_fr_fr fr1,fr36 ; 3.0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - cfsqrts fr10,fr10,cc4,1 - test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 - - cfsqrts fr44,fr1,cc1,0 ; 9.0 - test_fr_fr fr1,fr36 ; 3.0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - cfsqrts fr10,fr10,cc5,0 - test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 - - set_fr_fr fr0,fr1 - cfsqrts fr44,fr1,cc0,0 ; 9.0 - test_fr_fr fr1,fr0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - cfsqrts fr10,fr10,cc4,0 - test_fr_iimmed 0x40490fdb,fr10 - - set_fr_fr fr0,fr1 - cfsqrts fr44,fr1,cc1,1 ; 9.0 - test_fr_fr fr1,fr0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - cfsqrts fr10,fr10,cc5,1 - test_fr_iimmed 0x40490fdb,fr10 - - set_fr_fr fr0,fr1 - cfsqrts fr44,fr1,cc2,0 ; 9.0 - test_fr_fr fr1,fr0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - cfsqrts fr10,fr10,cc6,1 - test_fr_iimmed 0x40490fdb,fr10 - - set_fr_fr fr0,fr1 - cfsqrts fr44,fr1,cc3,1 ; 9.0 - test_fr_fr fr1,fr0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - cfsqrts fr10,fr10,cc7,0 - test_fr_iimmed 0x40490fdb,fr10 - - pass diff --git a/sim/testsuite/sim/frv/cfstoi.cgs b/sim/testsuite/sim/frv/cfstoi.cgs deleted file mode 100644 index 9ba8d12..0000000 --- a/sim/testsuite/sim/frv/cfstoi.cgs +++ /dev/null @@ -1,83 +0,0 @@ -# frv testcase for cfstoi $FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfstoi -cfstoi: - set_spr_immed 0x1b1b,cccr - - cfstoi fr16,fr1,cc0,1 - test_fr_iimmed 0,fr1 - cfstoi fr20,fr1,cc0,1 - test_fr_iimmed 0,fr1 - - cfstoi fr32,fr1,cc4,1 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xce05,0x4904,fr1 - cfstoi fr1,fr1,cc4,1 - test_fr_iimmed 0xdeadbf00,fr1 - - cfstoi fr16,fr1,cc1,0 - test_fr_iimmed 0,fr1 - cfstoi fr20,fr1,cc1,0 - test_fr_iimmed 0,fr1 - - cfstoi fr32,fr1,cc5,0 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xce05,0x4904,fr1 - cfstoi fr1,fr1,cc5,0 - test_fr_iimmed 0xdeadbf00,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfstoi fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfstoi fr20,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr1,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfstoi fr20,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr1,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfstoi fr20,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr32,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr1,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfstoi fr20,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr32,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr1,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfsubs.cgs b/sim/testsuite/sim/frv/cfsubs.cgs deleted file mode 100644 index 3bc7db1..0000000 --- a/sim/testsuite/sim/frv/cfsubs.cgs +++ /dev/null @@ -1,412 +0,0 @@ -# frv testcase for cfsubs $FRi,$FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfsubs -cfsubs: - set_spr_immed 0x1b1b,cccr - - cfsubs fr0,fr16,fr1,cc0,1 - test_fr_fr fr1,fr0 - cfsubs fr4,fr16,fr1,cc0,1 - test_fr_fr fr1,fr4 - cfsubs fr8,fr16,fr1,cc0,1 - test_fr_fr fr1,fr8 - cfsubs fr12,fr16,fr1,cc0,1 - test_fr_fr fr1,fr12 - cfsubs fr16,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr20,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr24,fr16,fr1,cc0,1 - test_fr_fr fr1,fr24 - cfsubs fr28,fr16,fr1,cc0,1 - test_fr_fr fr1,fr28 - cfsubs fr32,fr16,fr1,cc0,1 - test_fr_fr fr1,fr32 - cfsubs fr36,fr16,fr1,cc0,1 - test_fr_fr fr1,fr36 - cfsubs fr40,fr16,fr1,cc0,1 - test_fr_fr fr1,fr40 - cfsubs fr44,fr16,fr1,cc0,1 - test_fr_fr fr1,fr44 - cfsubs fr48,fr16,fr1,cc0,1 - test_fr_fr fr1,fr48 - cfsubs fr52,fr16,fr1,cc0,1 - test_fr_fr fr1,fr52 - - cfsubs fr0,fr20,fr1,cc0,1 - test_fr_fr fr1,fr0 - cfsubs fr4,fr20,fr1,cc4,1 - test_fr_fr fr1,fr4 - cfsubs fr8,fr20,fr1,cc4,1 - test_fr_fr fr1,fr8 - cfsubs fr12,fr20,fr1,cc4,1 - test_fr_fr fr1,fr12 - cfsubs fr16,fr20,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr20,fr20,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr24,fr20,fr1,cc4,1 - test_fr_fr fr1,fr24 - cfsubs fr28,fr20,fr1,cc4,1 - test_fr_fr fr1,fr28 - cfsubs fr32,fr20,fr1,cc4,1 - test_fr_fr fr1,fr32 - cfsubs fr36,fr20,fr1,cc4,1 - test_fr_fr fr1,fr36 - cfsubs fr40,fr20,fr1,cc4,1 - test_fr_fr fr1,fr40 - cfsubs fr44,fr20,fr1,cc4,1 - test_fr_fr fr1,fr44 - cfsubs fr48,fr20,fr1,cc4,1 - test_fr_fr fr1,fr48 - cfsubs fr52,fr20,fr1,cc4,1 - test_fr_fr fr1,fr52 - - cfsubs fr32,fr36,fr1,cc4,1 - test_fr_fr fr1,fr8 - - cfsubs fr44,fr40,fr1,cc4,1 - test_fr_fr fr1,fr36 -; - cfsubs fr0,fr16,fr1,cc1,0 - test_fr_fr fr1,fr0 - cfsubs fr4,fr16,fr1,cc1,0 - test_fr_fr fr1,fr4 - cfsubs fr8,fr16,fr1,cc1,0 - test_fr_fr fr1,fr8 - cfsubs fr12,fr16,fr1,cc1,0 - test_fr_fr fr1,fr12 - cfsubs fr16,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr20,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr24,fr16,fr1,cc1,0 - test_fr_fr fr1,fr24 - cfsubs fr28,fr16,fr1,cc1,0 - test_fr_fr fr1,fr28 - cfsubs fr32,fr16,fr1,cc1,0 - test_fr_fr fr1,fr32 - cfsubs fr36,fr16,fr1,cc1,0 - test_fr_fr fr1,fr36 - cfsubs fr40,fr16,fr1,cc1,0 - test_fr_fr fr1,fr40 - cfsubs fr44,fr16,fr1,cc1,0 - test_fr_fr fr1,fr44 - cfsubs fr48,fr16,fr1,cc1,0 - test_fr_fr fr1,fr48 - cfsubs fr52,fr16,fr1,cc1,0 - test_fr_fr fr1,fr52 - - cfsubs fr0,fr20,fr1,cc1,0 - test_fr_fr fr1,fr0 - cfsubs fr4,fr20,fr1,cc5,0 - test_fr_fr fr1,fr4 - cfsubs fr8,fr20,fr1,cc5,0 - test_fr_fr fr1,fr8 - cfsubs fr12,fr20,fr1,cc5,0 - test_fr_fr fr1,fr12 - cfsubs fr16,fr20,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr20,fr20,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr24,fr20,fr1,cc5,0 - test_fr_fr fr1,fr24 - cfsubs fr28,fr20,fr1,cc5,0 - test_fr_fr fr1,fr28 - cfsubs fr32,fr20,fr1,cc5,0 - test_fr_fr fr1,fr32 - cfsubs fr36,fr20,fr1,cc5,0 - test_fr_fr fr1,fr36 - cfsubs fr40,fr20,fr1,cc5,0 - test_fr_fr fr1,fr40 - cfsubs fr44,fr20,fr1,cc5,0 - test_fr_fr fr1,fr44 - cfsubs fr48,fr20,fr1,cc5,0 - test_fr_fr fr1,fr48 - cfsubs fr52,fr20,fr1,cc5,0 - test_fr_fr fr1,fr52 - - cfsubs fr32,fr36,fr1,cc5,0 - test_fr_fr fr1,fr8 - - cfsubs fr44,fr40,fr1,cc5,0 - test_fr_fr fr1,fr36 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfsubs fr0,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr0,fr20,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr32,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr44,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfsubs fr0,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr0,fr20,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr32,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr44,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfsubs fr0,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr0,fr20,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr32,fr36,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr44,fr40,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfsubs fr0,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr0,fr20,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr32,fr36,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr44,fr40,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - pass - - diff --git a/sim/testsuite/sim/frv/cjmpl.cgs b/sim/testsuite/sim/frv/cjmpl.cgs deleted file mode 100644 index df7be86..0000000 --- a/sim/testsuite/sim/frv/cjmpl.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for cjmpl @($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cjmpl -cjmpl: - set_spr_immed 0x1b1b,cccr - - set_spr_immed 0,lr - set_gr_addr ok1,gr8 - set_gr_immed 0,gr9 - cjmpl @(gr8,gr9),cc0,1 - fail -ok1: - test_spr_immed 0,lr - - set_spr_immed 0,lr - set_gr_addr bad,gr8 - set_gr_immed 0,gr9 - cjmpl @(gr8,gr9),cc0,0 - test_spr_immed 0,lr - - set_spr_immed 0,lr - set_gr_addr ok4,gr8 - set_gr_immed 3,gr9 ; target gets aligned down - cjmpl @(gr8,gr9),cc1,0 - fail -ok4: - test_spr_immed 0,lr - - set_spr_immed 0,lr - set_gr_addr bad,gr8 - set_gr_immed 0,gr9 - cjmpl @(gr8,gr9),cc1,1 - test_spr_immed 0,lr - - set_spr_immed 0,lr - set_gr_addr bad,gr8 - set_gr_immed 0,gr9 - cjmpl @(gr8,gr9),cc2,0 - test_spr_immed 0,lr - - set_spr_immed 0,lr - set_gr_addr bad,gr8 - set_gr_immed 0,gr9 - cjmpl @(gr8,gr9),cc3,1 - test_spr_immed 0,lr - - pass -bad: - fail - diff --git a/sim/testsuite/sim/frv/ckc.cgs b/sim/testsuite/sim/frv/ckc.cgs deleted file mode 100644 index a849dd4..0000000 --- a/sim/testsuite/sim/frv/ckc.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckc $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckc -ckc: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckeq.cgs b/sim/testsuite/sim/frv/ckeq.cgs deleted file mode 100644 index 241dc9d..0000000 --- a/sim/testsuite/sim/frv/ckeq.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckeq $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckeq -ckeq: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckge.cgs b/sim/testsuite/sim/frv/ckge.cgs deleted file mode 100644 index 58eefd3..0000000 --- a/sim/testsuite/sim/frv/ckge.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckge $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckge -ckge: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckgt.cgs b/sim/testsuite/sim/frv/ckgt.cgs deleted file mode 100644 index 7d4b6a8..0000000 --- a/sim/testsuite/sim/frv/ckgt.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckgt $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckgt -ckgt: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckgt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckgt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckgt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckgt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckhi.cgs b/sim/testsuite/sim/frv/ckhi.cgs deleted file mode 100644 index 5c55937..0000000 --- a/sim/testsuite/sim/frv/ckhi.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckhi $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckhi -ckhi: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckhi icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckhi icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckhi icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckhi icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckle.cgs b/sim/testsuite/sim/frv/ckle.cgs deleted file mode 100644 index 8a6f445..0000000 --- a/sim/testsuite/sim/frv/ckle.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckle $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckle -ckle: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckle icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckle icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckle icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckle icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckls.cgs b/sim/testsuite/sim/frv/ckls.cgs deleted file mode 100644 index ca5822f..0000000 --- a/sim/testsuite/sim/frv/ckls.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckls $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckls -ckls: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckls icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckls icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckls icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckls icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cklt.cgs b/sim/testsuite/sim/frv/cklt.cgs deleted file mode 100644 index f5848af..0000000 --- a/sim/testsuite/sim/frv/cklt.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for cklt $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global cklt -cklt: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckn.cgs b/sim/testsuite/sim/frv/ckn.cgs deleted file mode 100644 index 073a2f1..0000000 --- a/sim/testsuite/sim/frv/ckn.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckn $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckn -ckn: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cknc.cgs b/sim/testsuite/sim/frv/cknc.cgs deleted file mode 100644 index a1359a9..0000000 --- a/sim/testsuite/sim/frv/cknc.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for cknc $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global cknc -cknc: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckne.cgs b/sim/testsuite/sim/frv/ckne.cgs deleted file mode 100644 index b9c2935..0000000 --- a/sim/testsuite/sim/frv/ckne.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckne $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckne -ckne: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckno.cgs b/sim/testsuite/sim/frv/ckno.cgs deleted file mode 100644 index e387b46..0000000 --- a/sim/testsuite/sim/frv/ckno.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckno $CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckno -ckno: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cknv.cgs b/sim/testsuite/sim/frv/cknv.cgs deleted file mode 100644 index 039eb7d..0000000 --- a/sim/testsuite/sim/frv/cknv.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for cknv $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global cknv -cknv: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckp.cgs b/sim/testsuite/sim/frv/ckp.cgs deleted file mode 100644 index 49129ec..0000000 --- a/sim/testsuite/sim/frv/ckp.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckp $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckp -ckp: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckra.cgs b/sim/testsuite/sim/frv/ckra.cgs deleted file mode 100644 index b542b10..0000000 --- a/sim/testsuite/sim/frv/ckra.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckra $CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckra -ckra: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckv.cgs b/sim/testsuite/sim/frv/ckv.cgs deleted file mode 100644 index 338c286..0000000 --- a/sim/testsuite/sim/frv/ckv.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckv $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckv -ckv: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cld.cgs b/sim/testsuite/sim/frv/cld.cgs deleted file mode 100644 index 62e1324..0000000 --- a/sim/testsuite/sim/frv/cld.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for cld @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cld -cld: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cld @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cld @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cld @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cld @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cld @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cld @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cld @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cld @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cld @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cld @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cld @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cld @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cld @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cld @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cld @(sp,gr7),gr8,cc6,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cld @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cld @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cld @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cldbf.cgs b/sim/testsuite/sim/frv/cldbf.cgs deleted file mode 100644 index 46d65ea..0000000 --- a/sim/testsuite/sim/frv/cldbf.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for cldbf @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldbf -cldbf: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0x00de,fr8 - - set_gr_immed 1,gr7 - cldbf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0x00ad,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbf @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0x0000,0x0000,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 1,gr7 - cldbf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbf @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0x00de,fr8 - - set_gr_immed 1,gr7 - cldbf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0x00ad,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbf @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0x0000,0x0000,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 1,gr7 - cldbf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbf @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbf @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 1,gr7 - cldbf @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbf @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbf @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 1,gr7 - cldbf @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbf @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - pass diff --git a/sim/testsuite/sim/frv/cldbfu.cgs b/sim/testsuite/sim/frv/cldbfu.cgs deleted file mode 100644 index bde4ff1..0000000 --- a/sim/testsuite/sim/frv/cldbfu.cgs +++ /dev/null @@ -1,154 +0,0 @@ -# frv testcase for cldbfu @($GRi,$GRj),$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldbfu -cldbfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0x00de,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - cldbfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0x00ad,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbfu @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 1,gr7 - cldbfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbfu @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0x00de,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - cldbfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0x00ad,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbfu @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 1,gr7 - cldbfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbfu @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbfu @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 1,gr7 - cldbfu @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbfu @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbfu @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 1,gr7 - cldbfu @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbfu @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cldd.cgs b/sim/testsuite/sim/frv/cldd.cgs deleted file mode 100644 index 709eba1..0000000 --- a/sim/testsuite/sim/frv/cldd.cgs +++ /dev/null @@ -1,168 +0,0 @@ -# frv testcase for cldd @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldd -cldd: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - cldd @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - cldd @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - cldd @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - cldd @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - cldd @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - cldd @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - cldd @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - cldd @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - cldd @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - cldd @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - cldd @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - cldd @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - cldd @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - cldd @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - cldd @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - cldd @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - cldd @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - cldd @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - pass diff --git a/sim/testsuite/sim/frv/clddf.cgs b/sim/testsuite/sim/frv/clddf.cgs deleted file mode 100644 index c5416ed..0000000 --- a/sim/testsuite/sim/frv/clddf.cgs +++ /dev/null @@ -1,174 +0,0 @@ -# frv testcase for clddf @($GRi,$GRj),$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global clddf -clddf: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddf @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddf @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddf @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddf @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddf @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddf @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddf @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddf @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddf @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddf @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - pass diff --git a/sim/testsuite/sim/frv/clddfu.cgs b/sim/testsuite/sim/frv/clddfu.cgs deleted file mode 100644 index ab981aa..0000000 --- a/sim/testsuite/sim/frv/clddfu.cgs +++ /dev/null @@ -1,212 +0,0 @@ -# frv testcase for clddfu @($GRi,$GRj),$FRk,$CCi,$ccond -# mach: all - - .include "testutils.inc" - - start - - .global clddfu -clddfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - clddfu @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddfu @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - clddfu @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddfu @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddfu @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddfu @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddfu @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddfu @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddfu @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddfu @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/clddu.cgs b/sim/testsuite/sim/frv/clddu.cgs deleted file mode 100644 index 91df6d8..0000000 --- a/sim/testsuite/sim/frv/clddu.cgs +++ /dev/null @@ -1,219 +0,0 @@ -# frv testcase for clddu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global clddu -clddu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - clddu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - clddu @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - clddu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - clddu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - clddu @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - clddu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - clddu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - clddu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_gr gr21,gr8 - inc_gr_immed -12,gr8 - set_gr_immed 8,gr7 - clddu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - pass diff --git a/sim/testsuite/sim/frv/cldf.cgs b/sim/testsuite/sim/frv/cldf.cgs deleted file mode 100644 index 011a02a..0000000 --- a/sim/testsuite/sim/frv/cldf.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for cldf @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldf -cldf: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldf @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldf @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldf @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldf @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldf @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldf @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldf @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldf @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldf @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldf @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - pass diff --git a/sim/testsuite/sim/frv/cldfu.cgs b/sim/testsuite/sim/frv/cldfu.cgs deleted file mode 100644 index d4abef0..0000000 --- a/sim/testsuite/sim/frv/cldfu.cgs +++ /dev/null @@ -1,164 +0,0 @@ -# frv testcase for cldfu @($GRi,$GRj),$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldfu -cldfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - cldfu @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,gr20 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldfu @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - cldfu @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,gr20 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldfu @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldfu @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldfu @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,gr20 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldfu @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldfu @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldfu @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,gr20 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldfu @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cldhf.cgs b/sim/testsuite/sim/frv/cldhf.cgs deleted file mode 100644 index 26972ed..0000000 --- a/sim/testsuite/sim/frv/cldhf.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for cldhf @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldhf -cldhf: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0xdead,fr8 - - set_gr_immed 2,gr7 - cldhf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0xbeef,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhf @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0x0000,0x0000,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 2,gr7 - cldhf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhf @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0xdead,fr8 - - set_gr_immed 2,gr7 - cldhf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0xbeef,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhf @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0x0000,0x0000,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 2,gr7 - cldhf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhf @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhf @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 2,gr7 - cldhf @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhf @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhf @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 2,gr7 - cldhf @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhf @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - pass diff --git a/sim/testsuite/sim/frv/cldhfu.cgs b/sim/testsuite/sim/frv/cldhfu.cgs deleted file mode 100644 index 062e398..0000000 --- a/sim/testsuite/sim/frv/cldhfu.cgs +++ /dev/null @@ -1,152 +0,0 @@ -# frv testcase for cldhfu @($GRi,$GRj),$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldhfu -cldhfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - cldhfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0xbeef,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhfu @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - cldhfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhfu @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - cldhfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0xbeef,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhfu @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - cldhfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhfu @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhfu @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - cldhfu @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhfu @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhfu @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - cldhfu @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhfu @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cldq.cgs b/sim/testsuite/sim/frv/cldq.cgs deleted file mode 100644 index bfb433b..0000000 --- a/sim/testsuite/sim/frv/cldq.cgs +++ /dev/null @@ -1,276 +0,0 @@ -# frv testcase for cldq @($GRi,$GRj),$GRk,$CCi,$cond -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global cldq -cldq: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldq @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldq @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldq @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldq @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldq @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldq @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldq @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldq @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldq @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldq @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldq @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldq @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldq @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldq @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldq @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldq @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldq @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldq @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - pass diff --git a/sim/testsuite/sim/frv/cldqu.cgs b/sim/testsuite/sim/frv/cldqu.cgs deleted file mode 100644 index fa0949a..0000000 --- a/sim/testsuite/sim/frv/cldqu.cgs +++ /dev/null @@ -1,318 +0,0 @@ -# frv testcase for cldqu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global cldqu -cldqu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldqu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldqu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - cldqu @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldqu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,gr20 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldqu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,gr20 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldqu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldqu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldqu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - cldqu @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldqu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,gr20 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldqu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,gr20 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldqu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldqu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,gr20 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldqu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,gr20 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldqu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldqu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,gr20 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldqu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,gr20 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldqu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_gr gr21,gr8 - inc_gr_immed -28,gr8 - set_gr_immed 16,gr7 - cldqu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - pass diff --git a/sim/testsuite/sim/frv/cldsb.cgs b/sim/testsuite/sim/frv/cldsb.cgs deleted file mode 100644 index ea8dd94..0000000 --- a/sim/testsuite/sim/frv/cldsb.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for cldsb @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldsb -cldsb: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsb @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xffde,gr8 - - set_gr_immed 1,gr7 - cldsb @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xffad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsb @(sp,gr7),gr8,cc4,1 - test_gr_immed 0,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsb @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldsb @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsb @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsb @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xffde,gr8 - - set_gr_immed 1,gr7 - cldsb @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xffad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsb @(sp,gr7),gr8,cc5,0 - test_gr_immed 0,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsb @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldsb @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsb @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsb @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldsb @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsb @(sp,gr7),gr8,cc6,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsb @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldsb @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsb @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cldsbu.cgs b/sim/testsuite/sim/frv/cldsbu.cgs deleted file mode 100644 index a4057f1..0000000 --- a/sim/testsuite/sim/frv/cldsbu.cgs +++ /dev/null @@ -1,162 +0,0 @@ -# frv testcase for cldsbu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldsbu -cldsbu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldsbu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xffde,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - cldsbu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xffad,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsbu @(sp,gr7),gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldsbu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldsbu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - inc_gr_immed 4,gr9 - set_gr_immed -1,gr7 - cldsbu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldsbu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xffde,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - cldsbu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xffad,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsbu @(sp,gr7),gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldsbu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldsbu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - inc_gr_immed 4,gr9 - set_gr_immed -1,gr7 - cldsbu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldsbu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldsbu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - inc_gr_immed 4,gr9 - set_gr_immed -1,gr7 - cldsbu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldsbu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldsbu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - inc_gr_immed 4,gr9 - set_gr_immed -1,gr7 - cldsbu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr8 - set_gr_immed 1,gr7 - cldsbu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xffad,gr8 - - pass - diff --git a/sim/testsuite/sim/frv/cldsh.cgs b/sim/testsuite/sim/frv/cldsh.cgs deleted file mode 100644 index 091d720..0000000 --- a/sim/testsuite/sim/frv/cldsh.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for cldsh @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global cldsh -cldsh: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsh @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xdead,gr8 - - set_gr_immed 2,gr7 - cldsh @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldsh @(sp,gr7),gr8,cc4,1 - test_gr_immed 0,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsh @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - cldsh @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldsh @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsh @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xdead,gr8 - - set_gr_immed 2,gr7 - cldsh @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldsh @(sp,gr7),gr8,cc5,0 - test_gr_immed 0,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsh @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - cldsh @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldsh @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsh @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - cldsh @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldsh @(sp,gr7),gr8,cc6,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsh @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - cldsh @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldsh @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cldshu.cgs b/sim/testsuite/sim/frv/cldshu.cgs deleted file mode 100644 index 491352e..0000000 --- a/sim/testsuite/sim/frv/cldshu.cgs +++ /dev/null @@ -1,159 +0,0 @@ -# frv testcase for cldshu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldshu -cldshu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldshu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - cldshu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xbeef,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldshu @(sp,gr7),gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldshu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - cldshu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldshu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldshu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - cldshu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xbeef,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldshu @(sp,gr7),gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldshu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - cldshu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldshu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldshu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - cldshu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldshu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldshu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - cldshu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldshu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr8 - set_gr_immed 2,gr7 - cldshu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cldu.cgs b/sim/testsuite/sim/frv/cldu.cgs deleted file mode 100644 index 61cf606..0000000 --- a/sim/testsuite/sim/frv/cldu.cgs +++ /dev/null @@ -1,172 +0,0 @@ -# frv testcase for cldu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldu -cldu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - cldu @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,gr9 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,gr9 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - cldu @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,gr9 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,gr9 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,gr9 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,gr9 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,gr9 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,gr9 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr8 - inc_gr_immed -4,gr8 - set_gr_immed 4,gr7 - cldu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cldub.cgs b/sim/testsuite/sim/frv/cldub.cgs deleted file mode 100644 index b1f0776..0000000 --- a/sim/testsuite/sim/frv/cldub.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for cldub @($GRi,$GRj),$GRk,$cci,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldub -cldub: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldub @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0x00de,gr8 - - set_gr_immed 1,gr7 - cldub @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0x00ad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldub @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0x0000,0x0000,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldub @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldub @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldub @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldub @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0x00de,gr8 - - set_gr_immed 1,gr7 - cldub @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0x00ad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldub @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0x0000,0x0000,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldub @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldub @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldub @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldub @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldub @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldub @(sp,gr7),gr8,cc6,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldub @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldub @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldub @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cldubu.cgs b/sim/testsuite/sim/frv/cldubu.cgs deleted file mode 100644 index c9f9579..0000000 --- a/sim/testsuite/sim/frv/cldubu.cgs +++ /dev/null @@ -1,155 +0,0 @@ -# frv testcase for cldubu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldubu -cldubu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldubu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0x00de,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - cldubu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0x00ad,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldubu @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0x0000,0x0000,gr8 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldubu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldubu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldubu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldubu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0x00de,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - cldubu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0x00ad,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldubu @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0x0000,0x0000,gr8 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldubu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldubu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldubu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldubu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldubu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldubu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldubu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldubu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldubu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr8 - set_gr_immed 1,gr7 - cldubu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0x00ad,gr8 - - pass diff --git a/sim/testsuite/sim/frv/clduh.cgs b/sim/testsuite/sim/frv/clduh.cgs deleted file mode 100644 index a9e505c..0000000 --- a/sim/testsuite/sim/frv/clduh.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for clduh @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global clduh -clduh: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - clduh @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0xdead,gr8 - - set_gr_immed 2,gr7 - clduh @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduh @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0x0000,0x0000,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - clduh @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - clduh @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduh @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - clduh @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0xdead,gr8 - - set_gr_immed 2,gr7 - clduh @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduh @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0x0000,0x0000,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - clduh @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - clduh @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduh @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - clduh @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - clduh @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduh @(sp,gr7),gr8,cc6,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - clduh @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - clduh @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduh @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/clduhu.cgs b/sim/testsuite/sim/frv/clduhu.cgs deleted file mode 100644 index 80eb381..0000000 --- a/sim/testsuite/sim/frv/clduhu.cgs +++ /dev/null @@ -1,159 +0,0 @@ -# frv testcase for clduhu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global clduhu -clduhu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - clduhu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - clduhu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0xbeef,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduhu @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0x0000,0x0000,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - clduhu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - clduhu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduhu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - clduhu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - clduhu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0xbeef,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduhu @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0x0000,0x0000,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - clduhu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - clduhu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduhu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - clduhu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - clduhu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduhu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - clduhu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - clduhu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduhu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr8 - set_gr_immed 2,gr7 - clduhu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/clrfa.cgs b/sim/testsuite/sim/frv/clrfa.cgs deleted file mode 100644 index 8bba605..0000000 --- a/sim/testsuite/sim/frv/clrfa.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for clrfa -# mach: frv - - .include "testutils.inc" - - start - - .global clrfa -clrfa: - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - or_spr_immed 0x00100000,fner1 - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - or_spr_immed 0x00200000,fner1 - nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 - or_spr_immed 0x00100000,fner0 - - clrfa - test_spr_immed 0x00000000,fner1 - test_spr_immed 0x00000000,fner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0x94800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0,nesr2 - test_spr_immed 0,neear2 - - pass diff --git a/sim/testsuite/sim/frv/clrfr.cgs b/sim/testsuite/sim/frv/clrfr.cgs deleted file mode 100644 index 9112815..0000000 --- a/sim/testsuite/sim/frv/clrfr.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for clrfr $FRk -# mach: frv - - .include "testutils.inc" - - start - - .global clrfr -clrfr: - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - or_spr_immed 0x00100000,fner1 - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - or_spr_immed 0x00200000,fner1 - nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 - or_spr_immed 0x00100000,fner0 - - clrfr fr20 - test_spr_immed 0x00200000,fner1 - test_spr_immed 0x00100000,fner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0x94800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xf4800801,nesr2 - test_spr_gr neear2,sp - - pass diff --git a/sim/testsuite/sim/frv/clrga.cgs b/sim/testsuite/sim/frv/clrga.cgs deleted file mode 100644 index 9e9a9a9..0000000 --- a/sim/testsuite/sim/frv/clrga.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for clrga -# mach: frv - - .include "testutils.inc" - - start - - .global clrga -clrga: - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - or_spr_immed 0x00100000,gner1 - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - or_spr_immed 0x00200000,gner1 - nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 - or_spr_immed 0x00100000,gner0 - - clrga - test_spr_immed 0x00000000,gner1 - test_spr_immed 0x00000000,gner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0xd4800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0,nesr2 - test_spr_immed 0,neear2 - - pass diff --git a/sim/testsuite/sim/frv/clrgr.cgs b/sim/testsuite/sim/frv/clrgr.cgs deleted file mode 100644 index 049b9e3..0000000 --- a/sim/testsuite/sim/frv/clrgr.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for clrgr $GRk -# mach: frv - - .include "testutils.inc" - - start - - .global clrgr -clrgr: - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - or_spr_immed 0x00100000,gner1 - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - or_spr_immed 0x00200000,gner1 - nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 - or_spr_immed 0x00100000,gner0 - - clrgr gr20 - test_spr_immed 0x00200000,gner1 - test_spr_immed 0x00100000,gner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0xd4800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xb4800801,nesr2 - test_spr_gr neear2,sp - - pass diff --git a/sim/testsuite/sim/frv/cmaddhss.cgs b/sim/testsuite/sim/frv/cmaddhss.cgs deleted file mode 100644 index 1f04e67..0000000 --- a/sim/testsuite/sim/frv/cmaddhss.cgs +++ /dev/null @@ -1,562 +0,0 @@ -# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global maddhss -maddhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,1 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc4,1 - cmaddhss fr11,fr11,fr13,cc4,1 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc5,0 - cmaddhss fr11,fr11,fr13,cc5,0 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc4,0 - cmaddhss fr11,fr11,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc5,1 - cmaddhss fr11,fr11,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc6,1 - cmaddhss fr11,fr11,fr13,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set -; - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc7,1 - cmaddhss fr11,fr11,fr13,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/cmaddhus.cgs b/sim/testsuite/sim/frv/cmaddhus.cgs deleted file mode 100644 index 76da81d..0000000 --- a/sim/testsuite/sim/frv/cmaddhus.cgs +++ /dev/null @@ -1,496 +0,0 @@ -# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmaddhus -cmaddhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x7fff,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc4,1 - cmaddhus fr11,fr11,fr13,cc4,1 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0xffff,0xffff,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x7fff,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc5,0 - cmaddhus fr11,fr11,fr13,cc5,0 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0xffff,0xffff,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc4,0 - cmaddhus fr11,fr11,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc5,1 - cmaddhus fr11,fr11,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc6,0 - cmaddhus fr11,fr11,fr13,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc7,0 - cmaddhus fr11,fr11,fr13,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/cmand.cgs b/sim/testsuite/sim/frv/cmand.cgs deleted file mode 100644 index 7ed9e4d..0000000 --- a/sim/testsuite/sim/frv/cmand.cgs +++ /dev/null @@ -1,89 +0,0 @@ -# frv testcase for cmand $FRinti,$FRintj,$FRintk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmand -cmand: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmand fr7,fr8,fr8,cc0,1 - test_fr_iimmed 0,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - cmand fr7,fr8,fr8,cc0,1 - test_fr_iimmed 0xaaaa0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - cmand fr7,fr8,fr8,cc4,1 - test_fr_iimmed 0x0000aaaa,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmand fr7,fr8,fr8,cc1,0 - test_fr_iimmed 0,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - cmand fr7,fr8,fr8,cc1,0 - test_fr_iimmed 0xaaaa0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - cmand fr7,fr8,fr8,cc5,0 - test_fr_iimmed 0x0000aaaa,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmand fr7,fr8,fr8,cc0,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - cmand fr7,fr8,fr8,cc0,0 - test_fr_iimmed 0xffff0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - cmand fr7,fr8,fr8,cc4,0 - test_fr_iimmed 0x0000ffff,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmand fr7,fr8,fr8,cc1,1 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - cmand fr7,fr8,fr8,cc1,1 - test_fr_iimmed 0xffff0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - cmand fr7,fr8,fr8,cc5,1 - test_fr_iimmed 0x0000ffff,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmand fr7,fr8,fr8,cc2,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - cmand fr7,fr8,fr8,cc2,1 - test_fr_iimmed 0xffff0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - cmand fr7,fr8,fr8,cc6,0 - test_fr_iimmed 0x0000ffff,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmand fr7,fr8,fr8,cc3,1 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - cmand fr7,fr8,fr8,cc3,0 - test_fr_iimmed 0xffff0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - cmand fr7,fr8,fr8,cc7,1 - test_fr_iimmed 0x0000ffff,fr8 - pass diff --git a/sim/testsuite/sim/frv/cmbtoh.cgs b/sim/testsuite/sim/frv/cmbtoh.cgs deleted file mode 100644 index 5e7c91a..0000000 --- a/sim/testsuite/sim/frv/cmbtoh.cgs +++ /dev/null @@ -1,74 +0,0 @@ -# frv testcase for cmbtoh $FRj,$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmbtoh -cmbtoh: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtoh fr10,fr12,cc0,1 - test_fr_limmed 0x00de,0x00ad,fr12 - test_fr_limmed 0x00be,0x00ef,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtoh fr10,fr12,cc4,1 - test_fr_limmed 0x0012,0x0034,fr12 - test_fr_limmed 0x0056,0x0078,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtoh fr10,fr12,cc1,0 - test_fr_limmed 0x00de,0x00ad,fr12 - test_fr_limmed 0x00be,0x00ef,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtoh fr10,fr12,cc5,0 - test_fr_limmed 0x0012,0x0034,fr12 - test_fr_limmed 0x0056,0x0078,fr13 - - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x2222,0x2222,fr13 - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtoh fr10,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtoh fr10,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtoh fr10,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtoh fr10,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtoh fr10,fr12,cc2,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtoh fr10,fr12,cc6,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtoh fr10,fr12,cc3,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtoh fr10,fr12,cc7,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - pass diff --git a/sim/testsuite/sim/frv/cmbtohe.cgs b/sim/testsuite/sim/frv/cmbtohe.cgs deleted file mode 100644 index eb6b514..0000000 --- a/sim/testsuite/sim/frv/cmbtohe.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for cmbtohe $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - start - - .global cmbtohe -cmbtohe: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtohe fr10,fr12,cc0,1 - test_fr_limmed 0x00de,0x00de,fr12 - test_fr_limmed 0x00ad,0x00ad,fr13 - test_fr_limmed 0x00be,0x00be,fr14 - test_fr_limmed 0x00ef,0x00ef,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtohe fr10,fr12,cc4,1 - test_fr_limmed 0x0012,0x0012,fr12 - test_fr_limmed 0x0034,0x0034,fr13 - test_fr_limmed 0x0056,0x0056,fr14 - test_fr_limmed 0x0078,0x0078,fr15 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtohe fr10,fr12,cc1,0 - test_fr_limmed 0x00de,0x00de,fr12 - test_fr_limmed 0x00ad,0x00ad,fr13 - test_fr_limmed 0x00be,0x00be,fr14 - test_fr_limmed 0x00ef,0x00ef,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtohe fr10,fr12,cc5,0 - test_fr_limmed 0x0012,0x0012,fr12 - test_fr_limmed 0x0034,0x0034,fr13 - test_fr_limmed 0x0056,0x0056,fr14 - test_fr_limmed 0x0078,0x0078,fr15 - - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x2222,0x2222,fr13 - set_fr_iimmed 0x3333,0x3333,fr14 - set_fr_iimmed 0x4444,0x4444,fr15 - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtohe fr10,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtohe fr10,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtohe fr10,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtohe fr10,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtohe fr10,fr12,cc2,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtohe fr10,fr12,cc6,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtohe fr10,fr12,cc3,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtohe fr10,fr12,cc7,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - pass diff --git a/sim/testsuite/sim/frv/cmcpxis.cgs b/sim/testsuite/sim/frv/cmcpxis.cgs deleted file mode 100644 index ded0300..0000000 --- a/sim/testsuite/sim/frv/cmcpxis.cgs +++ /dev/null @@ -1,971 +0,0 @@ -# frv testcase for cmcpxis $GRi,$GRj,$ACCk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmcpxis -cmcpxis: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - - set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xc000,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -9,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - - set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbfff,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0x8001,0x0000,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x8000,0x0000,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - - ; Positive operands - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - - set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xc000,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -9,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - - set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbfff,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0x8001,0x0000,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x8000,0x0000,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 -; - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - pass diff --git a/sim/testsuite/sim/frv/cmcpxiu.cgs b/sim/testsuite/sim/frv/cmcpxiu.cgs deleted file mode 100644 index 90a92bc..0000000 --- a/sim/testsuite/sim/frv/cmcpxiu.cgs +++ /dev/null @@ -1,508 +0,0 @@ -# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmcpxiu -cmcpxiu: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 5,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7fff,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8001,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0x00010001,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 1,accg0 - test_acc_immed 0xfffb0003,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 1,accg0 - test_acc_immed 0xfffc0002,acc0 - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 5,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7fff,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8001,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0x00010001,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 1,accg0 - test_acc_immed 0xfffb0003,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 1,accg0 - test_acc_immed 0xfffc0002,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - pass diff --git a/sim/testsuite/sim/frv/cmcpxrs.cgs b/sim/testsuite/sim/frv/cmcpxrs.cgs deleted file mode 100644 index ea1242c..0000000 --- a/sim/testsuite/sim/frv/cmcpxrs.cgs +++ /dev/null @@ -1,649 +0,0 @@ -# frv testcase for cmcpxrs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmcpxrs -cmcpxrs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ff0,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x4000,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -3,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbff0,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8006,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0x8000,0x8000,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x7fff,0x8000,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ff0,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x4000,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -3,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbff0,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8006,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0x8000,0x8000,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x7fff,0x8000,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 -; - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - pass diff --git a/sim/testsuite/sim/frv/cmcpxru.cgs b/sim/testsuite/sim/frv/cmcpxru.cgs deleted file mode 100644 index f9217b6..0000000 --- a/sim/testsuite/sim/frv/cmcpxru.cgs +++ /dev/null @@ -1,544 +0,0 @@ -# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmcpxru -cmcpxru: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 14,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffd,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xffff,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0x0001ffff,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 14,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffd,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xffff,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0x0001ffff,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 -; - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - pass diff --git a/sim/testsuite/sim/frv/cmexpdhd.cgs b/sim/testsuite/sim/frv/cmexpdhd.cgs deleted file mode 100644 index 33a3c00..0000000 --- a/sim/testsuite/sim/frv/cmexpdhd.cgs +++ /dev/null @@ -1,116 +0,0 @@ -# frv testcase for cmexpdhd $FRi,$s6,$FRj,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmexpdhd -cmexpdhd: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhd fr10,0,fr12,cc0,1 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xdead,0xdead,fr13 - - cmexpdhd fr10,1,fr12,cc0,1 - test_fr_limmed 0xbeef,0xbeef,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - cmexpdhd fr10,62,fr12,cc4,1 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xdead,0xdead,fr13 - - cmexpdhd fr10,63,fr12,cc4,1 - test_fr_limmed 0xbeef,0xbeef,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhd fr10,0,fr12,cc1,0 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xdead,0xdead,fr13 - - cmexpdhd fr10,1,fr12,cc1,0 - test_fr_limmed 0xbeef,0xbeef,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - cmexpdhd fr10,62,fr12,cc5,0 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xdead,0xdead,fr13 - - cmexpdhd fr10,63,fr12,cc5,0 - test_fr_limmed 0xbeef,0xbeef,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x2222,0x2222,fr13 - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhd fr10,0,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,1,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,62,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,63,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhd fr10,0,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,1,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,62,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,63,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhd fr10,0,fr12,cc2,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,1,fr12,cc2,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,62,fr12,cc6,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,63,fr12,cc6,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhd fr10,0,fr12,cc3,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,1,fr12,cc3,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,62,fr12,cc7,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,63,fr12,cc7,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - pass diff --git a/sim/testsuite/sim/frv/cmexpdhw.cgs b/sim/testsuite/sim/frv/cmexpdhw.cgs deleted file mode 100644 index 330d404..0000000 --- a/sim/testsuite/sim/frv/cmexpdhw.cgs +++ /dev/null @@ -1,91 +0,0 @@ -# frv testcase for cmexpdhw $FRi,$s6,$FRj,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmexpdhw -cmexpdhw: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhw fr10,0,fr12,cc0,1 - test_fr_limmed 0xdead,0xdead,fr12 - - cmexpdhw fr10,1,fr12,cc0,1 - test_fr_limmed 0xbeef,0xbeef,fr12 - - cmexpdhw fr10,62,fr12,cc4,1 - test_fr_limmed 0xdead,0xdead,fr12 - - cmexpdhw fr10,63,fr12,cc4,1 - test_fr_limmed 0xbeef,0xbeef,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhw fr10,0,fr12,cc1,0 - test_fr_limmed 0xdead,0xdead,fr12 - - cmexpdhw fr10,1,fr12,cc1,0 - test_fr_limmed 0xbeef,0xbeef,fr12 - - cmexpdhw fr10,62,fr12,cc5,0 - test_fr_limmed 0xdead,0xdead,fr12 - - cmexpdhw fr10,63,fr12,cc5,0 - test_fr_limmed 0xbeef,0xbeef,fr12 - - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhw fr10,0,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,1,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,62,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,63,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhw fr10,0,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,1,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,62,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,63,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhw fr10,0,fr12,cc2,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,1,fr12,cc2,0 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,62,fr12,cc6,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,63,fr12,cc6,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhw fr10,0,fr12,cc3,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,1,fr12,cc3,0 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,62,fr12,cc7,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,63,fr12,cc7,0 - test_fr_limmed 0x1111,0x1111,fr12 - - pass diff --git a/sim/testsuite/sim/frv/cmhtob.cgs b/sim/testsuite/sim/frv/cmhtob.cgs deleted file mode 100644 index a3f00c5..0000000 --- a/sim/testsuite/sim/frv/cmhtob.cgs +++ /dev/null @@ -1,103 +0,0 @@ -# frv testcase for cmhtob $FRj,$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmhtob -cmhtob: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - cmhtob fr10,fr12,cc0,1 - test_fr_limmed 0xadef,0x3478,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - cmhtob fr10,fr12,cc0,1 - test_fr_limmed 0xffff,0xffff,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 - set_fr_iimmed 0x10ad,0x80ef,fr11 - cmhtob fr10,fr12,cc4,1 - test_fr_limmed 0xffff,0xffff,fr12 - - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - cmhtob fr10,fr12,cc1,0 - test_fr_limmed 0xadef,0x3478,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - cmhtob fr10,fr12,cc1,0 - test_fr_limmed 0xffff,0xffff,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 - set_fr_iimmed 0x10ad,0x80ef,fr11 - cmhtob fr10,fr12,cc5,0 - test_fr_limmed 0xffff,0xffff,fr12 - - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - cmhtob fr10,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - cmhtob fr10,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 - set_fr_iimmed 0x10ad,0x80ef,fr11 - cmhtob fr10,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - cmhtob fr10,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - cmhtob fr10,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 - set_fr_iimmed 0x10ad,0x80ef,fr11 - cmhtob fr10,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - cmhtob fr10,fr12,cc2,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - cmhtob fr10,fr12,cc2,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 - set_fr_iimmed 0x10ad,0x80ef,fr11 - cmhtob fr10,fr12,cc6,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - cmhtob fr10,fr12,cc3,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - cmhtob fr10,fr12,cc7,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 - set_fr_iimmed 0x10ad,0x80ef,fr11 - cmhtob fr10,fr12,cc7,1 - test_fr_limmed 0x1111,0x1111,fr12 - - pass diff --git a/sim/testsuite/sim/frv/cmmachs.cgs b/sim/testsuite/sim/frv/cmmachs.cgs deleted file mode 100644 index 2131b7e..0000000 --- a/sim/testsuite/sim/frv/cmmachs.cgs +++ /dev/null @@ -1,1631 +0,0 @@ -# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmmachs -cmmachs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_spr_immed 0x0,msr0 - set_spr_immed 0x0,msr1 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0007,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0001,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xbffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xbffd,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffd,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc003,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc005,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc005,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3ffec006,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x7ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x7ffec006,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc4,1 -;;;;;;;;;;;; - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed -128,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed -128,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_spr_immed 0x0,msr1 - set_accg_immed 0x0,accg0 ; saturation - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0007,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0001,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xbffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xbffd,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffd,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc003,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc005,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc005,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3ffec006,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x7ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x7ffec006,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_spr_immed 0x0,msr1 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_spr_immed 0x0,msr1 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_spr_immed 0x0,msr1 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 -; - ; Positive operands - set_spr_immed 0x0,msr0 - set_spr_immed 0x0,msr1 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass diff --git a/sim/testsuite/sim/frv/cmmachu.cgs b/sim/testsuite/sim/frv/cmmachu.cgs deleted file mode 100644 index 8948f15..0000000 --- a/sim/testsuite/sim/frv/cmmachu.cgs +++ /dev/null @@ -1,864 +0,0 @@ -# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmmachu -cmmachu: - set_spr_immed 0x1b1b,cccr - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x00020006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00020006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x40010007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40010007,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x8001,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x8001,0x0007,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x7fff,0x0008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x7fff,0x0008,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x00020006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00020006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x40010007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40010007,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x8001,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x8001,0x0007,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x7fff,0x0008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x7fff,0x0008,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 -; - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - pass diff --git a/sim/testsuite/sim/frv/cmmulhs.cgs b/sim/testsuite/sim/frv/cmmulhs.cgs deleted file mode 100644 index 01ee598..0000000 --- a/sim/testsuite/sim/frv/cmmulhs.cgs +++ /dev/null @@ -1,814 +0,0 @@ -# frv testcase for cmmulhs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmmulhs -cmmulhs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x0001,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -2,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffe,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffe,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x8000,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40000000,acc1 - - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x0001,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -2,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffe,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffe,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x8000,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40000000,acc1 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmulhs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhs fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmulhs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhs fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmulhs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmulhs fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmulhs fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmulhs fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhs fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmulhs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhs fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmulhs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhs fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmulhs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmulhs fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmulhs fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmulhs fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhs fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - pass diff --git a/sim/testsuite/sim/frv/cmmulhu.cgs b/sim/testsuite/sim/frv/cmmulhu.cgs deleted file mode 100644 index 9e8fbb8..0000000 --- a/sim/testsuite/sim/frv/cmmulhu.cgs +++ /dev/null @@ -1,460 +0,0 @@ -# frv testcase for cmmulhu $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmmulhu -cmmulhu: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmulhu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmulhu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x00010000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00010000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0000,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmulhu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmulhu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmulhu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x00010000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00010000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0000,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmulhu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmulhu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmulhu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmulhu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmulhu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmulhu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmulhu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmulhu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmulhu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmulhu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmulhu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmulhu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmulhu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - pass diff --git a/sim/testsuite/sim/frv/cmnot.cgs b/sim/testsuite/sim/frv/cmnot.cgs deleted file mode 100644 index cc93c01..0000000 --- a/sim/testsuite/sim/frv/cmnot.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for cmnot $FRintj,$FRintk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmnot -cmnot: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - cmnot fr7,fr7,cc0,1 - test_fr_iimmed 0x55555555,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - cmnot fr7,fr7,cc4,1 - test_fr_iimmed 0x21524110,fr7 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - cmnot fr7,fr7,cc1,0 - test_fr_iimmed 0x55555555,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - cmnot fr7,fr7,cc5,0 - test_fr_iimmed 0x21524110,fr7 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - cmnot fr7,fr7,cc0,0 - test_fr_iimmed 0xaaaaaaaa,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - cmnot fr7,fr7,cc4,0 - test_fr_iimmed 0xdeadbeef,fr7 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - cmnot fr7,fr7,cc1,1 - test_fr_iimmed 0xaaaaaaaa,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - cmnot fr7,fr7,cc5,1 - test_fr_iimmed 0xdeadbeef,fr7 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - cmnot fr7,fr7,cc2,0 - test_fr_iimmed 0xaaaaaaaa,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - cmnot fr7,fr7,cc6,1 - test_fr_iimmed 0xdeadbeef,fr7 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - cmnot fr7,fr7,cc3,0 - test_fr_iimmed 0xaaaaaaaa,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - cmnot fr7,fr7,cc7,1 - test_fr_iimmed 0xdeadbeef,fr7 - - pass diff --git a/sim/testsuite/sim/frv/cmor.cgs b/sim/testsuite/sim/frv/cmor.cgs deleted file mode 100644 index ebdc5f2..0000000 --- a/sim/testsuite/sim/frv/cmor.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for cmor $FRinti,$FRintj,$FRintk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmor -cmor: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmor fr7,fr8,fr8,cc0,1 - test_fr_iimmed 0xffffffff,fr8 - - set_fr_iimmed 0x0000,0x0000,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmor fr7,fr8,fr8,cc0,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmor fr7,fr8,fr8,cc4,1 - test_fr_iimmed 0xdeadbeef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmor fr7,fr8,fr8,cc1,0 - test_fr_iimmed 0xffffffff,fr8 - - set_fr_iimmed 0x0000,0x0000,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmor fr7,fr8,fr8,cc1,0 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmor fr7,fr8,fr8,cc5,0 - test_fr_iimmed 0xdeadbeef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmor fr7,fr8,fr8,cc0,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmor fr7,fr8,fr8,cc0,0 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmor fr7,fr8,fr8,cc4,0 - test_fr_iimmed 0x0000beef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmor fr7,fr8,fr8,cc1,1 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmor fr7,fr8,fr8,cc1,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmor fr7,fr8,fr8,cc5,1 - test_fr_iimmed 0x0000beef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmor fr7,fr8,fr8,cc2,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmor fr7,fr8,fr8,cc2,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmor fr7,fr8,fr8,cc6,0 - test_fr_iimmed 0x0000beef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmor fr7,fr8,fr8,cc3,1 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmor fr7,fr8,fr8,cc3,0 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmor fr7,fr8,fr8,cc7,1 - test_fr_iimmed 0x0000beef,fr8 - pass diff --git a/sim/testsuite/sim/frv/cmov.cgs b/sim/testsuite/sim/frv/cmov.cgs deleted file mode 100644 index 236bb20..0000000 --- a/sim/testsuite/sim/frv/cmov.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# frv testcase for cmov $GRi,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmov -cmov: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0xdeadbeef,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cmov gr7,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0xdeadbeef,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0xdeadbeef,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cmov gr7,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00007fff,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0xdeadbeef,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cmov gr7,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00007fff,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0xdeadbeef,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cmov gr7,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 0xdeadbeef,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0xdeadbeef,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - cmov gr7,gr8,cc2,0 - test_icc 1 0 0 0 icc2 - test_gr_immed 0xdeadbeef,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0xdeadbeef,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - cmov gr7,gr8,cc3,0 - test_icc 1 0 0 0 icc3 - test_gr_immed 0xdeadbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cmovfg.cgs b/sim/testsuite/sim/frv/cmovfg.cgs deleted file mode 100644 index 4109842..0000000 --- a/sim/testsuite/sim/frv/cmovfg.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for cmovfg $FRk,$GRj,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmovfg -cmovfg: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc0,0 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc4,0 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc1,1 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc5,1 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc2,0 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc2,1 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc3,1 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc7,0 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/cmovfgd.cgs b/sim/testsuite/sim/frv/cmovfgd.cgs deleted file mode 100644 index 5d1757d..0000000 --- a/sim/testsuite/sim/frv/cmovfgd.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# frv testcase for cmovfgd $FRk,$GRj,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmovfgd -cmovfgd: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc0,0 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc4,0 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc1,1 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc5,1 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc2,0 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc6,1 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc3,1 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc7,0 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - pass diff --git a/sim/testsuite/sim/frv/cmovgf.cgs b/sim/testsuite/sim/frv/cmovgf.cgs deleted file mode 100644 index 58ed1d8..0000000 --- a/sim/testsuite/sim/frv/cmovgf.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for cmovgf $GRj,$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmovgf -cmovgf: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc2,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc6,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc3,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc7,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - pass diff --git a/sim/testsuite/sim/frv/cmovgfd.cgs b/sim/testsuite/sim/frv/cmovgfd.cgs deleted file mode 100644 index 67bb272..0000000 --- a/sim/testsuite/sim/frv/cmovgfd.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# frv testcase for cmovgfd $GRj,$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmovgfd -cmovgfd: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc2,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc6,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc3,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc7,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - pass diff --git a/sim/testsuite/sim/frv/cmp.cgs b/sim/testsuite/sim/frv/cmp.cgs deleted file mode 100644 index e6694c1..0000000 --- a/sim/testsuite/sim/frv/cmp.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase for cmp $GRi,$GRj,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global cmp -cmp: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - cmp gr8,gr7,icc0 - test_icc 0 0 0 0 icc0 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - cmp gr8,gr7,icc0 - test_icc 0 0 1 0 icc0 - - set_icc 0x0b,0 ; Set mask opposite of expected - cmp gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - - set_gr_immed 0,gr8 - set_icc 0x06,0 ; Set mask opposite of expected - cmp gr8,gr7,icc0 - test_icc 1 0 0 1 icc0 - - pass diff --git a/sim/testsuite/sim/frv/cmpb.cgs b/sim/testsuite/sim/frv/cmpb.cgs deleted file mode 100644 index 94b9836..0000000 --- a/sim/testsuite/sim/frv/cmpb.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# frv testcase for cmpb $GRi,$GRj,$ICCi_1 -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global cmpb -cmpb: - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xdead,0xbeef,gr8 - set_icc 0x00,0 ; Set mask opposite of expected - cmpb gr7,gr8,icc0 - test_icc 1 1 1 1 icc0 - - set_gr_limmed 0x21ad,0xbeef,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cmpb gr7,gr8,icc0 - test_icc 0 1 1 1 icc0 - - set_gr_limmed 0xde52,0xbeef,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - cmpb gr7,gr8,icc0 - test_icc 1 0 1 1 icc0 - - set_gr_limmed 0xdead,0x41ef,gr8 - set_icc 0x02,0 ; Set mask opposite of expected - cmpb gr7,gr8,icc0 - test_icc 1 1 0 1 icc0 - - set_gr_limmed 0xdead,0xbe10,gr8 - set_icc 0x01,0 ; Set mask opposite of expected - cmpb gr7,gr8,icc0 - test_icc 1 1 1 0 icc0 - - set_gr_limmed 0xbeef,0xdead,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - cmpb gr7,gr8,icc0 - test_icc 0 0 0 0 icc0 - - pass diff --git a/sim/testsuite/sim/frv/cmpba.cgs b/sim/testsuite/sim/frv/cmpba.cgs deleted file mode 100644 index 160b9ef..0000000 --- a/sim/testsuite/sim/frv/cmpba.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# frv testcase for cmpba $GRi,$GRj,$ICCi_1 -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global cmpba -cmpba: - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xdead,0xbeef,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - cmpba gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - - set_gr_limmed 0x21ad,0xbeef,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - cmpba gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - - set_gr_limmed 0xde52,0xbeef,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - cmpba gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - - set_gr_limmed 0xdead,0x41ef,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - cmpba gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - - set_gr_limmed 0xdead,0xbe10,gr8 - set_icc 0x03,0 ; Set mask opposite of expected - cmpba gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - - set_gr_limmed 0xbeef,0xdead,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - cmpba gr7,gr8,icc0 - test_icc 0 0 0 0 icc0 - - pass diff --git a/sim/testsuite/sim/frv/cmpi.cgs b/sim/testsuite/sim/frv/cmpi.cgs deleted file mode 100644 index a8324db..0000000 --- a/sim/testsuite/sim/frv/cmpi.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for cmpi $GRi,$s12,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global cmpi -cmpi: - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - cmpi gr8,1,icc0 - test_icc 0 0 0 0 icc0 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - cmpi gr8,1,icc0 - test_icc 0 0 1 0 icc0 - - set_gr_immed 0x1ff,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cmpi gr8,0x1ff,icc0 - test_icc 0 1 0 0 icc0 - - set_gr_immed 0,gr8 - set_icc 0x06,0 ; Set mask opposite of expected - cmpi gr8,1,icc0 - test_icc 1 0 0 1 icc0 - - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - cmpi gr8,-1,icc0 - test_icc 0 0 0 1 icc0 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x06,0 ; Set mask opposite of expected - cmpi gr8,-1,icc0 - test_icc 1 0 0 1 icc0 - - set_gr_immed -512,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cmpi gr8,-512,icc0 - test_icc 0 1 0 0 icc0 - - set_gr_immed 0,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - cmpi gr8,-1,icc0 - test_icc 0 0 0 1 icc0 - - pass diff --git a/sim/testsuite/sim/frv/cmqmachs.cgs b/sim/testsuite/sim/frv/cmqmachs.cgs deleted file mode 100644 index 4acd62a..0000000 --- a/sim/testsuite/sim/frv/cmqmachs.cgs +++ /dev/null @@ -1,1268 +0,0 @@ -# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmqmachs -cmqmachs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 -; - ; Positive operands - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - pass - - diff --git a/sim/testsuite/sim/frv/cmqmachu.cgs b/sim/testsuite/sim/frv/cmqmachu.cgs deleted file mode 100644 index 1be1389..0000000 --- a/sim/testsuite/sim/frv/cmqmachu.cgs +++ /dev/null @@ -1,876 +0,0 @@ -# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmqmachu -cmqmachu: - set_spr_immed 0x1b1b,cccr - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8000,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00018000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00018000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff8007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff8007,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4001,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4001,0x8000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x3ffd,0x8008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x3ffd,0x8008,acc1 - test_accg_immed 1,accg2 - test_acc_limmed 0x3fff,0x8001,acc2 - test_accg_immed 1,accg3 - test_acc_limmed 0x3fff,0x8001,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8000,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00018000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00018000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff8007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff8007,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4001,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4001,0x8000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x3ffd,0x8008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x3ffd,0x8008,acc1 - test_accg_immed 1,accg2 - test_acc_limmed 0x3fff,0x8001,acc2 - test_accg_immed 1,accg3 - test_acc_limmed 0x3fff,0x8001,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 -; - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/cmqmulhs.cgs b/sim/testsuite/sim/frv/cmqmulhs.cgs deleted file mode 100644 index b315737..0000000 --- a/sim/testsuite/sim/frv/cmqmulhs.cgs +++ /dev/null @@ -1,734 +0,0 @@ -# frv testcase for cmqmulhs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmqmulhs -cmqmulhs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmulhs fr8,fr10,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhs fr8,fr10,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x0001,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmulhs fr8,fr10,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - test_accg_immed 0xff,accg2 - test_acc_immed -2,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -2,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmulhs fr8,fr10,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffe,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffe,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xc000,0x8000,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xc000,0x8000,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmulhs fr8,fr10,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhs fr8,fr10,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x40000000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x40000000,acc3 - - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmulhs fr8,fr10,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhs fr8,fr10,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x0001,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmulhs fr8,fr10,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - test_accg_immed 0xff,accg2 - test_acc_immed -2,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -2,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmulhs fr8,fr10,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffe,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffe,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xc000,0x8000,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xc000,0x8000,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmulhs fr8,fr10,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhs fr8,fr10,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x40000000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x40000000,acc3 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmulhs fr8,fr10,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhs fr8,fr10,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmulhs fr8,fr10,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmulhs fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmulhs fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhs fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmulhs fr8,fr10,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhs fr8,fr10,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmulhs fr8,fr10,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmulhs fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmulhs fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhs fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmulhs fr8,fr10,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhs fr8,fr10,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmulhs fr8,fr10,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmulhs fr8,fr10,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmulhs fr8,fr10,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhs fr8,fr10,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 -; - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmulhs fr8,fr10,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhs fr8,fr10,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmulhs fr8,fr10,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmulhs fr8,fr10,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmulhs fr8,fr10,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhs fr8,fr10,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - pass diff --git a/sim/testsuite/sim/frv/cmqmulhu.cgs b/sim/testsuite/sim/frv/cmqmulhu.cgs deleted file mode 100644 index 36f0c2f..0000000 --- a/sim/testsuite/sim/frv/cmqmulhu.cgs +++ /dev/null @@ -1,464 +0,0 @@ -# frv testcase for cmqmulhu $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmqmulhu -cmqmulhu: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmulhu fr8,fr10,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhu fr8,fr10,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00010000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00010000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4000,0x0000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmulhu fr8,fr10,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0xfffe,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xfffe,0x0001,acc3 - - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmulhu fr8,fr10,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhu fr8,fr10,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00010000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00010000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4000,0x0000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmulhu fr8,fr10,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0xfffe,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xfffe,0x0001,acc3 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmulhu fr8,fr10,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhu fr8,fr10,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmulhu fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmulhu fr8,fr10,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhu fr8,fr10,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmulhu fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmulhu fr8,fr10,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhu fr8,fr10,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmulhu fr8,fr10,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 -; - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmulhu fr8,fr10,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhu fr8,fr10,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmulhu fr8,fr10,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - pass diff --git a/sim/testsuite/sim/frv/cmsubhss.cgs b/sim/testsuite/sim/frv/cmsubhss.cgs deleted file mode 100644 index 386b27d..0000000 --- a/sim/testsuite/sim/frv/cmsubhss.cgs +++ /dev/null @@ -1,562 +0,0 @@ -# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmsubhss -cmsubhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0x4111,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x4111,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x1235,0x5679,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc4,1 - cmsubhss fr11,fr10,fr13,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x8000,0x8000,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0x4111,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x4111,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x1235,0x5679,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc5,0 - cmsubhss fr11,fr10,fr13,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x8000,0x8000,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc4,0 - cmsubhss fr11,fr10,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc5,1 - cmsubhss fr11,fr10,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc6,1 - cmsubhss fr11,fr10,fr13,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set -; - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc7,1 - cmsubhss fr11,fr10,fr13,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/cmsubhus.cgs b/sim/testsuite/sim/frv/cmsubhus.cgs deleted file mode 100644 index 2a8f343..0000000 --- a/sim/testsuite/sim/frv/cmsubhus.cgs +++ /dev/null @@ -1,442 +0,0 @@ -# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmsubhus -cmsubhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc4,1 - cmsubhus fr10,fr11,fr13,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc5,0 - cmsubhus fr10,fr11,fr13,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc4,0 - cmsubhus fr10,fr11,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc5,1 - cmsubhus fr10,fr11,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc6,0 - cmsubhus fr10,fr11,fr13,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set -; - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc7,0 - cmsubhus fr10,fr11,fr13,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/cmxor.cgs b/sim/testsuite/sim/frv/cmxor.cgs deleted file mode 100644 index 236e2fe..0000000 --- a/sim/testsuite/sim/frv/cmxor.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# frv testcase for cmxor $FRinti,$FRintj,$FRintk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmxor -cmxor: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmxor fr7,fr8,fr8,cc0,1 - test_fr_iimmed 0xffffffff,fr8 - - set_fr_iimmed 0x0000,0x0000,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmxor fr7,fr8,fr8,cc0,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - cmxor fr7,fr8,fr8,cc4,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmxor fr7,fr8,fr8,cc4,1 - test_fr_iimmed 0xdeadbeef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmxor fr7,fr8,fr8,cc1,0 - test_fr_iimmed 0xffffffff,fr8 - - set_fr_iimmed 0x0000,0x0000,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmxor fr7,fr8,fr8,cc1,0 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - cmxor fr7,fr8,fr8,cc5,0 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmxor fr7,fr8,fr8,cc5,0 - test_fr_iimmed 0xdeadbeef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmxor fr7,fr8,fr8,cc0,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmxor fr7,fr8,fr8,cc0,0 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - cmxor fr7,fr8,fr8,cc4,0 - test_fr_iimmed 0xaaaaaaaa,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmxor fr7,fr8,fr8,cc4,0 - test_fr_iimmed 0x0000beef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmxor fr7,fr8,fr8,cc1,1 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmxor fr7,fr8,fr8,cc1,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - cmxor fr7,fr8,fr8,cc5,1 - test_fr_iimmed 0xaaaaaaaa,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmxor fr7,fr8,fr8,cc5,1 - test_fr_iimmed 0x0000beef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmxor fr7,fr8,fr8,cc2,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmxor fr7,fr8,fr8,cc2,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - cmxor fr7,fr8,fr8,cc6,0 - test_fr_iimmed 0xaaaaaaaa,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmxor fr7,fr8,fr8,cc6,1 - test_fr_iimmed 0x0000beef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmxor fr7,fr8,fr8,cc3,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmxor fr7,fr8,fr8,cc3,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - cmxor fr7,fr8,fr8,cc7,0 - test_fr_iimmed 0xaaaaaaaa,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmxor fr7,fr8,fr8,cc7,1 - test_fr_iimmed 0x0000beef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/cnot.cgs b/sim/testsuite/sim/frv/cnot.cgs deleted file mode 100644 index 3169887..0000000 --- a/sim/testsuite/sim/frv/cnot.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for cnot $GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global cnot -cnot: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - cnot gr7,gr7,cc0,1 - test_gr_limmed 0x5555,0x5555,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - cnot gr7,gr7,cc4,1 - test_gr_limmed 0x2152,0x4110,gr7 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - cnot gr7,gr7,cc0,0 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - cnot gr7,gr7,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr7 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - cnot gr7,gr7,cc1,0 - test_gr_limmed 0x5555,0x5555,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - cnot gr7,gr7,cc5,0 - test_gr_limmed 0x2152,0x4110,gr7 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - cnot gr7,gr7,cc1,1 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - cnot gr7,gr7,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr7 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - cnot gr7,gr7,cc2,0 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - cnot gr7,gr7,cc6,1 - test_gr_limmed 0xdead,0xbeef,gr7 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - cnot gr7,gr7,cc3,0 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - cnot gr7,gr7,cc7,1 - test_gr_limmed 0xdead,0xbeef,gr7 - - pass diff --git a/sim/testsuite/sim/frv/commitfa.cgs b/sim/testsuite/sim/frv/commitfa.cgs deleted file mode 100644 index 8208cab..0000000 --- a/sim/testsuite/sim/frv/commitfa.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for commitfa -# mach: frv - - .include "testutils.inc" - - start - - .global commitfa -commitfa: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x190,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - set_gr_immed 0,gr15 - - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 - set_spr_immed 0x00000000,fner1 - set_spr_immed 0x00000000,fner0 - set_spr_addr bad,lr - commitfa ; should be nop - test_spr_immed 0x00000000,fner1 - test_spr_immed 0x00000000,fner0 - test_spr_immed 0xd4800001,nesr0 - test_spr_gr neear0,sp - test_spr_immed 0x94800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xf4800801,nesr2 - test_spr_gr neear2,sp - - or_spr_immed 0x00100000,fner1 - or_spr_immed 0x00200000,fner1 - or_spr_immed 0x00100000,fner0 - set_spr_addr ok,lr - set_gr_addr com1,gr16 -com1: commitfa - test_gr_immed 1,gr15 - - pass - -ok: test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr16 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear - test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear - test_spr_immed 0x00000000,fner1 - test_spr_immed 0x00000000,fner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0x94800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0,nesr2 - test_spr_immed 0,neear2 - inc_gr_immed 1,gr15 - rett 0 - -bad: fail diff --git a/sim/testsuite/sim/frv/commitfr.cgs b/sim/testsuite/sim/frv/commitfr.cgs deleted file mode 100644 index 97491dc..0000000 --- a/sim/testsuite/sim/frv/commitfr.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for commitfr $FRk -# mach: frv - - .include "testutils.inc" - - start - - .global commitfr -commitfr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x190,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - set_gr_immed 0,gr15 - - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 - set_spr_immed 0x00000000,fner1 - set_spr_immed 0x00000000,fner0 - set_spr_addr bad,lr - commitfr fr20 ; should be nop - test_spr_immed 0x00000000,fner1 - test_spr_immed 0x00000000,fner0 - test_spr_immed 0xd4800001,nesr0 - test_spr_gr neear0,sp - test_spr_immed 0x94800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xf4800801,nesr2 - test_spr_gr neear2,sp - - or_spr_immed 0x00100000,fner1 - or_spr_immed 0x00200000,fner1 - or_spr_immed 0x00100000,fner0 - set_spr_addr ok,lr - set_gr_addr com1,gr16 -com1: commitfr fr20 - test_gr_immed 1,gr15 - - pass - -ok: test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr16 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear - test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear - test_spr_immed 0x00200000,fner1 - test_spr_immed 0x00100000,fner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0x94800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xf4800801,nesr2 - test_spr_gr neear2,sp - inc_gr_immed 1,gr15 - rett 0 - -bad: fail diff --git a/sim/testsuite/sim/frv/commitga.cgs b/sim/testsuite/sim/frv/commitga.cgs deleted file mode 100644 index 57100b8..0000000 --- a/sim/testsuite/sim/frv/commitga.cgs +++ /dev/null @@ -1,62 +0,0 @@ -# frv testcase for commitga -# mach: frv - - .include "testutils.inc" - - start - - .global commitga -commitga: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x190,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - set_gr_immed 0,gr15 - - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 - set_spr_immed 0x00000000,gner1 - set_spr_immed 0x00000000,gner0 - set_spr_addr bad,lr - commitga ; should be a nop - test_gr_immed 0,gr15 - test_spr_immed 0x00000000,gner1 - test_spr_immed 0x00000000,gner0 - test_spr_immed 0x94800001,nesr0 - test_spr_gr neear0,sp - test_spr_immed 0xd4800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xb4800801,nesr2 - test_spr_gr neear2,sp - - or_spr_immed 0x00100000,gner1 - or_spr_immed 0x00200000,gner1 - or_spr_immed 0x00100000,gner0 - set_spr_addr ok,lr - set_gr_addr com1,gr16 -com1: commitga - test_gr_immed 1,gr15 - - pass - -ok: test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr16 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear - test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear - test_spr_immed 0x00000000,gner1 - test_spr_immed 0x00000000,gner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0xd4800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0,nesr2 - test_spr_immed 0,neear0 - inc_gr_immed 1,gr15 - rett 0 - -bad: fail diff --git a/sim/testsuite/sim/frv/commitgr.cgs b/sim/testsuite/sim/frv/commitgr.cgs deleted file mode 100644 index 45553da..0000000 --- a/sim/testsuite/sim/frv/commitgr.cgs +++ /dev/null @@ -1,62 +0,0 @@ -# frv testcase for commitgr $GRk -# mach: frv - - .include "testutils.inc" - - start - - .global commitgr -commitgr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x190,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - set_gr_immed 0,gr15 - - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 - set_spr_immed 0x00000000,gner1 - set_spr_immed 0x00000000,gner0 - set_spr_addr bad,lr - commitgr gr20 ; should only clear ne flags - test_gr_immed 0,gr15 - test_spr_immed 0x00000000,gner1 - test_spr_immed 0x00000000,gner0 - test_spr_immed 0x94800001,nesr0 - test_spr_gr neear0,sp - test_spr_immed 0xd4800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xb4800801,nesr2 - test_spr_gr neear2,sp - - or_spr_immed 0x00100000,gner1 - or_spr_immed 0x00200000,gner1 - or_spr_immed 0x00100000,gner0 - set_spr_addr ok,lr - set_gr_addr com1,gr16 -com1: commitgr gr20 - test_gr_immed 1,gr15 - - pass - -ok: test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr16 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear - test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear - test_spr_immed 0x00200000,gner1 - test_spr_immed 0x00100000,gner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0xd4800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xb4800801,nesr2 - test_spr_gr neear2,sp - inc_gr_immed 1,gr15 - rett 0 - -bad: fail diff --git a/sim/testsuite/sim/frv/cop1.cgs b/sim/testsuite/sim/frv/cop1.cgs deleted file mode 100644 index 652e355..0000000 --- a/sim/testsuite/sim/frv/cop1.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# frv testcase for cop1 $s6_1,$CPRi,$CPRj,$CPRk -# mach: frv - - .include "testutils.inc" - - start - - .global cop1 -cop1: - cop1 0,cpr0,cpr15,cpr31 - cop1 31,cpr32,cpr45,cpr63 - cop1 -32,cpr32,cpr45,cpr63 - - pass diff --git a/sim/testsuite/sim/frv/cop2.cgs b/sim/testsuite/sim/frv/cop2.cgs deleted file mode 100644 index 858ed2b..0000000 --- a/sim/testsuite/sim/frv/cop2.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# frv testcase for cop2 $s6_1,$CPRi,$CPRj,$CPRk -# mach: frv - - .include "testutils.inc" - - start - - .global cop2 -cop2: - cop2 0,cpr0,cpr15,cpr31 - cop2 31,cpr32,cpr45,cpr63 - cop2 -32,cpr32,cpr45,cpr63 - - pass diff --git a/sim/testsuite/sim/frv/cor.cgs b/sim/testsuite/sim/frv/cor.cgs deleted file mode 100644 index ef19985..0000000 --- a/sim/testsuite/sim/frv/cor.cgs +++ /dev/null @@ -1,138 +0,0 @@ -# frv testcase for cor $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cor -cor: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc0,1 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc4,1 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc0,0 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc4,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc1,0 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc5,0 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc1,1 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc5,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,2 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc2,0 - test_icc 0 1 1 1 icc2 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc2,0 - test_icc 1 0 0 0 icc2 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc6,1 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,3 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc3,0 - test_icc 0 1 1 1 icc3 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc3,0 - test_icc 1 0 0 0 icc3 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc7,1 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x0000,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/corcc.cgs b/sim/testsuite/sim/frv/corcc.cgs deleted file mode 100644 index 5276658..0000000 --- a/sim/testsuite/sim/frv/corcc.cgs +++ /dev/null @@ -1,138 +0,0 @@ -# frv testcase for corcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global corcc -corcc: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc0,1 - test_icc 0 1 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc4,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc1,0 - test_icc 0 1 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 0 1 icc1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc5,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,2 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 1 1 icc2 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc2,0 - test_icc 1 0 0 0 icc2 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc6,1 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,3 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 1 1 icc3 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc3,0 - test_icc 1 0 0 0 icc3 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc7,1 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x0000,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cscan.cgs b/sim/testsuite/sim/frv/cscan.cgs deleted file mode 100644 index 505bb5a..0000000 --- a/sim/testsuite/sim/frv/cscan.cgs +++ /dev/null @@ -1,394 +0,0 @@ -# frv testcase for cscan $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cscan -cscan: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0x2aaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0x5555,gr8 - cscan gr7,gr8,gr9,cc0,1 - test_gr_immed 0,gr9 - test_gr_limmed 0x2aaa,0xaaaa,gr7 - test_gr_limmed 0xaaaa,0x5555,gr8 - - set_gr_limmed 0x2aaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaab,gr8 - cscan gr7,gr8,gr9,cc0,1 - test_gr_immed 0,gr9 - test_gr_limmed 0x2aaa,0xaaaa,gr7 - test_gr_limmed 0xaaaa,0xaaab,gr8 - - set_gr_limmed 0xd555,0x5555,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - cscan gr7,gr8,gr9,cc0,1 - test_gr_immed 63,gr9 - test_gr_limmed 0xd555,0x5555,gr7 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xd555,0x5555,gr7 - set_gr_limmed 0xaaaa,0xaaab,gr8 - cscan gr7,gr8,gr9,cc0,1 - test_gr_immed 63,gr9 - test_gr_limmed 0xd555,0x5555,gr7 - test_gr_limmed 0xaaaa,0xaaab,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - cscan gr7,gr8,gr9,cc0,1 - test_gr_immed 0,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - cscan gr7,gr8,gr9,cc4,1 - test_gr_immed 2,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - cscan gr7,gr8,gr9,cc4,1 - test_gr_immed 16,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - cscan gr7,gr8,gr9,cc4,1 - test_gr_immed 31,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - cscan gr7,gr8,gr9,cc4,1 - test_gr_immed 7,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0x7fff,gr9 - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc0,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xaaaa,0xaaab,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc0,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaab,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc0,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5554,gr8 - cscan gr7,gr8,gr9,cc0,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5554,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - cscan gr7,gr8,gr9,cc0,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - cscan gr7,gr8,gr9,cc4,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - cscan gr7,gr8,gr9,cc4,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - cscan gr7,gr8,gr9,cc4,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - cscan gr7,gr8,gr9,cc4,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0x2aaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - cscan gr7,gr8,gr9,cc1,0 - test_gr_immed 0,gr9 - test_gr_limmed 0x2aaa,0xaaaa,gr7 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0x2aaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaab,gr8 - cscan gr7,gr8,gr9,cc1,0 - test_gr_immed 0,gr9 - test_gr_limmed 0x2aaa,0xaaaa,gr7 - test_gr_limmed 0xaaaa,0xaaab,gr8 - - set_gr_limmed 0xd555,0x5555,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - cscan gr7,gr8,gr9,cc1,0 - test_gr_immed 63,gr9 - test_gr_limmed 0xd555,0x5555,gr7 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xd555,0x5555,gr7 - set_gr_limmed 0xaaaa,0xaaab,gr8 - cscan gr7,gr8,gr9,cc1,0 - test_gr_immed 63,gr9 - test_gr_limmed 0xd555,0x5555,gr7 - test_gr_limmed 0xaaaa,0xaaab,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - cscan gr7,gr8,gr9,cc1,0 - test_gr_immed 0,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - cscan gr7,gr8,gr9,cc5,0 - test_gr_immed 2,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - cscan gr7,gr8,gr9,cc5,0 - test_gr_immed 16,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - cscan gr7,gr8,gr9,cc5,0 - test_gr_immed 31,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - cscan gr7,gr8,gr9,cc5,0 - test_gr_immed 7,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0x7fff,gr9 - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc1,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xaaaa,0xaaab,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc1,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaab,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc1,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5554,gr8 - cscan gr7,gr8,gr9,cc1,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5554,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - cscan gr7,gr8,gr9,cc1,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - cscan gr7,gr8,gr9,cc5,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - cscan gr7,gr8,gr9,cc5,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - cscan gr7,gr8,gr9,cc5,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - cscan gr7,gr8,gr9,cc5,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0x7fff,gr9 - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc2,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xaaaa,0xaaab,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc2,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaab,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc2,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5554,gr8 - cscan gr7,gr8,gr9,cc2,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5554,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - cscan gr7,gr8,gr9,cc2,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - cscan gr7,gr8,gr9,cc6,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - cscan gr7,gr8,gr9,cc6,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - cscan gr7,gr8,gr9,cc6,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - cscan gr7,gr8,gr9,cc6,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0x7fff,gr9 - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc3,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xaaaa,0xaaab,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc3,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaab,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc3,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5554,gr8 - cscan gr7,gr8,gr9,cc3,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5554,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - cscan gr7,gr8,gr9,cc3,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - cscan gr7,gr8,gr9,cc7,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - cscan gr7,gr8,gr9,cc7,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - cscan gr7,gr8,gr9,cc7,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - cscan gr7,gr8,gr9,cc7,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csdiv.cgs b/sim/testsuite/sim/frv/csdiv.cgs deleted file mode 100644 index c6bfb97..0000000 --- a/sim/testsuite/sim/frv/csdiv.cgs +++ /dev/null @@ -1,190 +0,0 @@ -# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csdiv -csdiv: - set_spr_immed 0x1b1b,cccr - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc4,1 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc4,1 - test_gr_immed -1,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_addr e1,gr17 - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 -e1: csdiv gr1,gr3,gr2,cc4,1 - test_gr_immed 1,gr15 - test_gr_limmed 0x8000,0x0000,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc4,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc5,0 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc5,0 - test_gr_immed -1,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_addr e2,gr17 - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 -e2: csdiv gr1,gr3,gr2,cc5,0 - test_gr_immed 2,gr15 - test_gr_limmed 0x8000,0x0000,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc5,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - pass - -ok1: ; exception handler for overflow - test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/csll.cgs b/sim/testsuite/sim/frv/csll.cgs deleted file mode 100644 index 0186756..0000000 --- a/sim/testsuite/sim/frv/csll.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for csll $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csll -csll: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc0,1 - test_icc 1 1 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc0,1 - test_icc 1 1 1 1 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc4,1 - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc0,0 - test_icc 1 1 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc4,0 - test_icc 0 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc1,0 - test_icc 1 1 0 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc1,0 - test_icc 1 1 1 1 icc1 - test_gr_immed 4,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc5,0 - test_icc 1 0 1 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc1,1 - test_icc 1 1 0 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc5,1 - test_icc 0 1 1 1 icc1 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,2 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc2,0 - test_icc 1 1 0 1 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,2 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc6,1 - test_icc 0 1 1 1 icc2 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,2 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,3 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc3,0 - test_icc 1 1 0 1 icc3 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,3 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc7,1 - test_icc 0 1 1 1 icc3 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,3 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_immed 2,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csllcc.cgs b/sim/testsuite/sim/frv/csllcc.cgs deleted file mode 100644 index 0c5b9af..0000000 --- a/sim/testsuite/sim/frv/csllcc.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for csllcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csllcc -csllcc: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc0,1 - test_icc 0 0 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc0,1 - test_icc 0 0 0 1 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc4,1 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc4,1 - test_icc 0 1 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc0,0 - test_icc 1 1 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc4,0 - test_icc 0 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc1,0 - test_icc 0 0 0 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc1,0 - test_icc 0 0 0 1 icc1 - test_gr_immed 4,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc5,0 - test_icc 1 0 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc5,0 - test_icc 0 1 1 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc1,1 - test_icc 1 1 0 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc5,1 - test_icc 0 1 1 1 icc1 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,2 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc2,0 - test_icc 1 1 0 1 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,2 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc6,1 - test_icc 0 1 1 1 icc2 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,2 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,3 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc3,0 - test_icc 1 1 0 1 icc3 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,3 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc7,1 - test_icc 0 1 1 1 icc3 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,3 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_immed 2,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csmul.cgs b/sim/testsuite/sim/frv/csmul.cgs deleted file mode 100644 index 25346e7..0000000 --- a/sim/testsuite/sim/frv/csmul.cgs +++ /dev/null @@ -1,1044 +0,0 @@ -# frv testcase for csmul $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csmul -csmul: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0xc000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0x00000000,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0xc000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0x00000000,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - pass diff --git a/sim/testsuite/sim/frv/csmulcc.cgs b/sim/testsuite/sim/frv/csmulcc.cgs deleted file mode 100644 index 26c7e66..0000000 --- a/sim/testsuite/sim/frv/csmulcc.cgs +++ /dev/null @@ -1,1380 +0,0 @@ -# frv testcase for csmulcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csmulcc -csmulcc: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0xc,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0xd,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0xe,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0xb,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x8,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0xd,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0xe,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0xf,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 1 icc0 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0xc,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x5,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x6,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x7,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 1 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x4,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0x9,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xa,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x4,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x5,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x6,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x7,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xc,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xd,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0xe,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0xc,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0xd,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xe,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xf,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 1 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0x00000000,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x0,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 0 0 0 icc0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0x1,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 0 0 1 icc0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x2,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 0 1 0 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0x3,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 0 1 1 icc0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x4,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0x5,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0x6,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 1 1 0 icc0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0x7,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 1 1 1 icc0 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x8,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x9,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 1 icc0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xa,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xb,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 1 0 1 1 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0xc,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 1 1 0 0 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0xd,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 1 1 0 1 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xe,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 1 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 1 1 1 1 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x0,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 0 0 0 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x1,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 0 0 1 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x2,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 0 1 0 icc0 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x3,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 0 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x4,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 0 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x5,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0x6,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 1 1 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 1 1 1 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x8,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x9,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 1 icc0 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xa,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xb,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0xc,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0xd,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 1 icc1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0xe,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0xb,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x8,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 1 0 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0xd,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 1 icc1 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0xe,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 0 icc1 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0xf,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 1 icc1 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0xc,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x5,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 1 icc1 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x6,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 1 0 icc1 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x7,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 1 1 icc1 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x4,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0x9,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 1 0 1 icc1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xa,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 1 1 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x4,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x5,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x6,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x7,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0xc000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xc,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xd,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 1 icc1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0xe,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 1 icc1 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0xc,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0xd,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 1 icc1 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xe,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 0 icc1 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xf,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 1 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0x00000000,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x0,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 0 0 0 icc1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0x1,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 0 0 1 icc1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x2,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 0 1 0 icc1 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0x3,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 0 1 1 icc1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x4,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0x5,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0x6,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 1 1 0 icc1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0x7,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 1 1 1 icc1 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x8,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x9,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 1 icc1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xa,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xb,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 1 0 1 1 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0xc,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 1 1 0 0 icc1 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0xd,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 1 1 0 1 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xe,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 1 1 1 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 1 1 1 1 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x0,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 0 0 0 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x1,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 0 0 1 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x2,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 0 1 0 icc1 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x3,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 0 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x4,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 0 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x5,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0x6,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 1 1 0 icc1 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 1 1 1 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x8,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x9,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 1 icc1 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xa,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xb,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x0,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 0 0 0 0 icc2 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0x1,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 0 0 0 1 icc2 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x2,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 0 0 1 0 icc2 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0x3,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 0 0 1 1 icc2 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x4,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 0 0 icc2 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0x5,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 0 1 0 1 icc2 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0x6,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 0 1 1 0 icc2 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0x7,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 0 1 1 1 icc2 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x8,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 1 0 0 0 icc2 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x9,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 1 0 0 1 icc2 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xa,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xb,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 1 0 1 1 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0xc,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 1 1 0 0 icc2 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0xd,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 1 1 0 1 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xe,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 1 1 1 0 icc2 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 1 1 1 1 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x0,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 0 0 0 0 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x1,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 0 0 0 1 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x2,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 0 0 1 0 icc2 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x3,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 0 0 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x4,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 0 1 0 0 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x5,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0x6,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 0 1 1 0 icc2 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 0 1 1 1 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x8,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 1 0 0 0 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x9,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 1 0 0 1 icc2 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xa,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xb,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 1 0 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x0,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 0 0 0 0 icc3 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0x1,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 0 0 0 1 icc3 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x2,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 0 0 1 0 icc3 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0x3,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 0 0 1 1 icc3 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x4,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 0 0 icc3 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0x5,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 0 1 0 1 icc3 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0x6,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 0 1 1 0 icc3 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0x7,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 0 1 1 1 icc3 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x8,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 1 0 0 0 icc3 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x9,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 1 0 0 1 icc3 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xa,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xb,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 1 0 1 1 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0xc,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 1 1 0 0 icc3 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0xd,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 1 1 0 1 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xe,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 1 1 1 0 icc3 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 1 1 1 1 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x0,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 0 0 0 0 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x1,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 0 0 0 1 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x2,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 0 0 1 0 icc3 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x3,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 0 0 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x4,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 0 1 0 0 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x5,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0x6,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 0 1 1 0 icc3 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 0 1 1 1 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x8,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 1 0 0 0 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x9,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 1 0 0 1 icc3 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xa,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xb,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 1 0 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - pass diff --git a/sim/testsuite/sim/frv/csra.cgs b/sim/testsuite/sim/frv/csra.cgs deleted file mode 100644 index f59de05..0000000 --- a/sim/testsuite/sim/frv/csra.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for csra $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csra -csra: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc0,1 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc0,1 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc4,1 - test_icc 1 1 1 1 icc0 - test_gr_immed -1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc4,1 - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc4,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc1,0 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc1,0 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc5,0 - test_icc 1 1 1 1 icc1 - test_gr_immed -1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc5,0 - test_icc 1 0 1 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc5,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc6,1 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,2 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc7,1 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,3 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_limmed 0x4000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csracc.cgs b/sim/testsuite/sim/frv/csracc.cgs deleted file mode 100644 index 64d4cbf..0000000 --- a/sim/testsuite/sim/frv/csracc.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for csracc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csracc -csracc: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc0,1 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc4,1 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc4,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc1,0 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc5,0 - test_icc 1 0 1 0 icc1 - test_gr_immed -1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc5,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc6,1 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,2 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc7,1 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,3 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_limmed 0x4000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csrl.cgs b/sim/testsuite/sim/frv/csrl.cgs deleted file mode 100644 index 7a71db4..0000000 --- a/sim/testsuite/sim/frv/csrl.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for csrl $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csrl -csrl: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc0,1 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc0,1 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc4,1 - test_icc 1 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc4,1 - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc4,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc1,0 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc1,0 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc5,0 - test_icc 1 1 1 1 icc1 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc5,0 - test_icc 1 0 1 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc5,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc6,1 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,2 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc7,1 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,3 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_limmed 0x4000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csrlcc.cgs b/sim/testsuite/sim/frv/csrlcc.cgs deleted file mode 100644 index fb89456..0000000 --- a/sim/testsuite/sim/frv/csrlcc.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for csrlcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csrlcc -csrlcc: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc0,1 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc4,1 - test_icc 0 0 1 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc4,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc1,0 - test_icc 0 0 1 0 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc5,0 - test_icc 0 0 1 0 icc1 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc5,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc6,1 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,2 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc7,1 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,3 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_limmed 0x4000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cst.cgs b/sim/testsuite/sim/frv/cst.cgs deleted file mode 100644 index 8244edf..0000000 --- a/sim/testsuite/sim/frv/cst.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for cst $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global cst -cst: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cst gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xffff,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cst gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xeeee,0xffff,gr21 - - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cst gr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xcccc,0xdddd,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cst gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cst gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cst gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cst gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xffff,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cst gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xeeee,0xffff,gr21 - - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cst gr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xcccc,0xdddd,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cst gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cst gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cst gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cst gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cst gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cst gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cst gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cst gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cst gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr21 - - pass diff --git a/sim/testsuite/sim/frv/cstb.cgs b/sim/testsuite/sim/frv/cstb.cgs deleted file mode 100644 index 7b62558..0000000 --- a/sim/testsuite/sim/frv/cstb.cgs +++ /dev/null @@ -1,120 +0,0 @@ -# frv testcase for cstb $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstb gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstb gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xeeef,sp - - set_gr_immed -1,gr7 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstb gr8,@(sp,gr7),cc4,1 - inc_gr_immed -4,sp - test_mem_limmed 0xffad,0xee00,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstb gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstb gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed -1,gr7 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstb gr8,@(sp,gr7),cc4,0 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstb gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstb gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xeeef,sp - - set_gr_immed -1,gr7 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstb gr8,@(sp,gr7),cc5,0 - inc_gr_immed -4,sp - test_mem_limmed 0xffad,0xee00,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstb gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstb gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed -1,gr7 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstb gr8,@(sp,gr7),cc5,1 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstb gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstb gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed -1,gr7 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstb gr8,@(sp,gr7),cc6,0 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstb gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstb gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed -1,gr7 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstb gr8,@(sp,gr7),cc7,1 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/cstbf.cgs b/sim/testsuite/sim/frv/cstbf.cgs deleted file mode 100644 index 23e1ae4..0000000 --- a/sim/testsuite/sim/frv/cstbf.cgs +++ /dev/null @@ -1,120 +0,0 @@ -# frv testcase for cstbf $FRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstbf -cstbf: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbf fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbf fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xaaef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbf fr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xffad,0xaabb,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbf fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbf fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbf fr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbf fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbf fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xaaef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbf fr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xffad,0xaabb,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbf fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbf fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbf fr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbf fr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbf fr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbf fr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbf fr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbf fr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbf fr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cstbfu.cgs b/sim/testsuite/sim/frv/cstbfu.cgs deleted file mode 100644 index 01943be..0000000 --- a/sim/testsuite/sim/frv/cstbfu.cgs +++ /dev/null @@ -1,152 +0,0 @@ -# frv testcase for cstbfu $FRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstbfu -cstbfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbfu fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 2,gr21 - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbfu fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xaaef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 1,gr21 - inc_gr_immed 2,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbfu fr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xffad,0xaabb,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbfu fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbfu fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbfu fr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbfu fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 2,gr21 - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbfu fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xaaef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 1,gr21 - inc_gr_immed 2,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbfu fr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xffad,0xaabb,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbfu fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbfu fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbfu fr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbfu fr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbfu fr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbfu fr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbfu fr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbfu fr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbfu fr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - pass diff --git a/sim/testsuite/sim/frv/cstbu.cgs b/sim/testsuite/sim/frv/cstbu.cgs deleted file mode 100644 index f8a9d0f..0000000 --- a/sim/testsuite/sim/frv/cstbu.cgs +++ /dev/null @@ -1,152 +0,0 @@ -# frv testcase for cstbu $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstbu -cstbu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstbu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xbeef,sp - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstbu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xeeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 1,gr20 - set_gr_immed -1,gr7 - inc_gr_immed 2,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstbu gr8,@(sp,gr7),cc4,1 - inc_gr_immed -4,sp - test_mem_limmed 0xffad,0xee00,gr21 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstbu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstbu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed -1,gr7 - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstbu gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstbu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xbeef,sp - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstbu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xeeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 1,gr20 - set_gr_immed -1,gr7 - inc_gr_immed 2,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstbu gr8,@(sp,gr7),cc5,0 - inc_gr_immed -4,sp - test_mem_limmed 0xffad,0xee00,gr21 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstbu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstbu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed -1,gr7 - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstbu gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstbu gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstbu gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed -1,gr7 - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstbu gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstbu gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstbu gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed -1,gr7 - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstbu gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cstd.cgs b/sim/testsuite/sim/frv/cstd.cgs deleted file mode 100644 index 6904414..0000000 --- a/sim/testsuite/sim/frv/cstd.cgs +++ /dev/null @@ -1,221 +0,0 @@ -# frv testcase for cstd $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global cstd -cstd: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstd gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xbeef,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstd gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xaaaa,0xaaaa,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbbbb,0xbbbb,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstd gr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xcccc,0xcccc,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdddd,0xdddd,gr21 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstd gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstd gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstd gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstd gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xbeef,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstd gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xaaaa,0xaaaa,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbbbb,0xbbbb,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstd gr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xcccc,0xcccc,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdddd,0xdddd,gr21 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstd gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstd gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstd gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstd gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstd gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstd gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstd gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstd gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstd gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - pass diff --git a/sim/testsuite/sim/frv/cstdf.cgs b/sim/testsuite/sim/frv/cstdf.cgs deleted file mode 100644 index fabbe93..0000000 --- a/sim/testsuite/sim/frv/cstdf.cgs +++ /dev/null @@ -1,222 +0,0 @@ -# frv testcase for cstdf $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstdf -cstdf: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdf fr8,@(sp,gr7),cc0,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdf fr8,@(sp,gr7),cc0,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xaaaa,0xaaaa,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbbbb,0xbbbb,gr22 - - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdf fr8,@(sp,gr7),cc4,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xcccc,0xcccc,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdddd,0xdddd,gr22 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdf fr8,@(sp,gr7),cc0,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdf fr8,@(sp,gr7),cc0,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdf fr8,@(sp,gr7),cc4,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdf fr8,@(sp,gr7),cc1,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdf fr8,@(sp,gr7),cc1,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xaaaa,0xaaaa,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbbbb,0xbbbb,gr22 - - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdf fr8,@(sp,gr7),cc5,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xcccc,0xcccc,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdddd,0xdddd,gr22 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdf fr8,@(sp,gr7),cc1,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdf fr8,@(sp,gr7),cc1,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdf fr8,@(sp,gr7),cc5,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdf fr8,@(sp,gr7),cc2,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdf fr8,@(sp,gr7),cc2,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdf fr8,@(sp,gr7),cc6,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdf fr8,@(sp,gr7),cc3,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdf fr8,@(sp,gr7),cc3,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdf fr8,@(sp,gr7),cc7,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - pass diff --git a/sim/testsuite/sim/frv/cstdfu.cgs b/sim/testsuite/sim/frv/cstdfu.cgs deleted file mode 100644 index b489bc9..0000000 --- a/sim/testsuite/sim/frv/cstdfu.cgs +++ /dev/null @@ -1,248 +0,0 @@ -# frv testcase for cstdfu $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstdfu -cstdfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdfu fr8,@(sp,gr7),cc0,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdfu fr8,@(sp,gr7),cc0,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xaaaa,0xaaaa,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbbbb,0xbbbb,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdfu fr8,@(sp,gr7),cc4,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xcccc,0xcccc,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdddd,0xdddd,gr22 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdfu fr8,@(sp,gr7),cc0,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed -8,sp - set_gr_gr sp,gr23 - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdfu fr8,@(sp,gr7),cc0,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - inc_gr_immed 16,sp - set_gr_gr sp,gr23 - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdfu fr8,@(sp,gr7),cc4,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdfu fr8,@(sp,gr7),cc1,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdfu fr8,@(sp,gr7),cc1,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xaaaa,0xaaaa,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbbbb,0xbbbb,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdfu fr8,@(sp,gr7),cc5,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xcccc,0xcccc,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdddd,0xdddd,gr22 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdfu fr8,@(sp,gr7),cc1,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed -8,sp - set_gr_gr sp,gr23 - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdfu fr8,@(sp,gr7),cc1,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - inc_gr_immed 16,sp - set_gr_gr sp,gr23 - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdfu fr8,@(sp,gr7),cc5,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdfu fr8,@(sp,gr7),cc2,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed -8,sp - set_gr_gr sp,gr23 - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdfu fr8,@(sp,gr7),cc2,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - inc_gr_immed 16,sp - set_gr_gr sp,gr23 - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdfu fr8,@(sp,gr7),cc6,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdfu fr8,@(sp,gr7),cc3,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed -8,sp - set_gr_gr sp,gr23 - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdfu fr8,@(sp,gr7),cc3,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - inc_gr_immed 16,sp - set_gr_gr sp,gr23 - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdfu fr8,@(sp,gr7),cc7,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - pass diff --git a/sim/testsuite/sim/frv/cstdu.cgs b/sim/testsuite/sim/frv/cstdu.cgs deleted file mode 100644 index a996ef6..0000000 --- a/sim/testsuite/sim/frv/cstdu.cgs +++ /dev/null @@ -1,251 +0,0 @@ -# frv testcase for cstdu $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstdu -cstdu: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstdu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xbeef,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstdu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xaaaa,0xaaaa,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbbbb,0xbbbb,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr20,gr21 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstdu gr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xcccc,0xcccc,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdddd,0xdddd,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_gr sp,gr22 - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstdu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_gr sp,gr22 - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstdu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_gr sp,gr22 - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstdu gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstdu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xbeef,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstdu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xaaaa,0xaaaa,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbbbb,0xbbbb,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr20,gr21 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstdu gr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xcccc,0xcccc,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdddd,0xdddd,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_gr sp,gr22 - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstdu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_gr sp,gr22 - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstdu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_gr sp,gr22 - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstdu gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_gr sp,gr22 - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstdu gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_gr sp,gr22 - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstdu gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_gr sp,gr22 - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstdu gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_gr sp,gr22 - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstdu gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_gr sp,gr22 - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstdu gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_gr sp,gr22 - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstdu gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - pass diff --git a/sim/testsuite/sim/frv/cstf.cgs b/sim/testsuite/sim/frv/cstf.cgs deleted file mode 100644 index 94c0f05..0000000 --- a/sim/testsuite/sim/frv/cstf.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for cstf $FRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstf -cstf: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstf fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xffff,gr20 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstf fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xeeee,0xeeee,gr20 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstf fr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xdddd,0xdddd,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstf fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstf fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstf fr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstf fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xffff,gr20 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstf fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xeeee,0xeeee,gr20 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstf fr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xdddd,0xdddd,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstf fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstf fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstf fr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstf fr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstf fr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstf fr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstf fr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstf fr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstf fr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cstfu.cgs b/sim/testsuite/sim/frv/cstfu.cgs deleted file mode 100644 index ee450c8..0000000 --- a/sim/testsuite/sim/frv/cstfu.cgs +++ /dev/null @@ -1,158 +0,0 @@ -# frv testcase for cstfu $FRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstfu -cstfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstfu fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xffff,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstfu fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_gr_gr sp,gr21 - - set_gr_immed -4,gr7 - inc_gr_immed 4,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstfu fr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xdddd,0xdddd,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstfu fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - inc_gr_immed -4,gr21 - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstfu fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - inc_gr_immed 8,gr21 - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstfu fr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstfu fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xffff,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstfu fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_gr_gr sp,gr21 - - set_gr_immed -4,gr7 - inc_gr_immed 4,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstfu fr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xdddd,0xdddd,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstfu fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - inc_gr_immed -4,gr21 - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstfu fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - inc_gr_immed 8,gr21 - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstfu fr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstfu fr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - inc_gr_immed -4,gr21 - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstfu fr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - inc_gr_immed 8,gr21 - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstfu fr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstfu fr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - inc_gr_immed -4,gr21 - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstfu fr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - inc_gr_immed 8,gr21 - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstfu fr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - pass diff --git a/sim/testsuite/sim/frv/csth.cgs b/sim/testsuite/sim/frv/csth.cgs deleted file mode 100644 index b9f743c..0000000 --- a/sim/testsuite/sim/frv/csth.cgs +++ /dev/null @@ -1,120 +0,0 @@ -# frv testcase for csth $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csth -csth: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csth gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csth gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xeeee,sp - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csth gr8,@(sp,gr7),cc4,1 - inc_gr_immed -4,sp - test_mem_limmed 0xffff,0xdddd,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csth gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csth gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,sp - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csth gr8,@(sp,gr7),cc4,0 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csth gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csth gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xeeee,sp - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csth gr8,@(sp,gr7),cc5,0 - inc_gr_immed -4,sp - test_mem_limmed 0xffff,0xdddd,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csth gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csth gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,sp - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csth gr8,@(sp,gr7),cc5,1 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csth gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csth gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,sp - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csth gr8,@(sp,gr7),cc6,0 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csth gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csth gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,sp - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csth gr8,@(sp,gr7),cc7,1 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/csthf.cgs b/sim/testsuite/sim/frv/csthf.cgs deleted file mode 100644 index 21a64c8..0000000 --- a/sim/testsuite/sim/frv/csthf.cgs +++ /dev/null @@ -1,120 +0,0 @@ -# frv testcase for csthf $FRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csthf -csthf: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthf fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthf fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xaaaa,gr20 - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthf fr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xffff,0xbbbb,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthf fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthf fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthf fr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthf fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthf fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xaaaa,gr20 - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthf fr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xffff,0xbbbb,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthf fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthf fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthf fr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthf fr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthf fr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthf fr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthf fr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthf fr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthf fr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/csthfu.cgs b/sim/testsuite/sim/frv/csthfu.cgs deleted file mode 100644 index 252ae7d..0000000 --- a/sim/testsuite/sim/frv/csthfu.cgs +++ /dev/null @@ -1,150 +0,0 @@ -# frv testcase for csthfu $FRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csthfu -csthfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthfu fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 2,gr21 - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthfu fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xaaaa,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 2,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthfu fr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xffff,0xbbbb,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthfu fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthfu fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthfu fr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthfu fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 2,gr21 - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthfu fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xaaaa,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 2,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthfu fr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xffff,0xbbbb,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthfu fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthfu fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthfu fr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthfu fr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthfu fr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthfu fr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthfu fr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthfu fr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthfu fr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - pass diff --git a/sim/testsuite/sim/frv/csthu.cgs b/sim/testsuite/sim/frv/csthu.cgs deleted file mode 100644 index c7e2255..0000000 --- a/sim/testsuite/sim/frv/csthu.cgs +++ /dev/null @@ -1,150 +0,0 @@ -# frv testcase for csthu $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csthu -csthu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csthu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - set_gr_limmed 0xdead,0xeeee,gr8 - csthu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xeeee,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 2,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csthu gr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xffff,0xdddd,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csthu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csthu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csthu gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,gr20 - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csthu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - set_gr_limmed 0xdead,0xeeee,gr8 - csthu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xeeee,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 2,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csthu gr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xffff,0xdddd,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csthu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csthu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csthu gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csthu gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csthu gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csthu gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csthu gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csthu gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csthu gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cstq.cgs b/sim/testsuite/sim/frv/cstq.cgs deleted file mode 100644 index 6f18332..0000000 --- a/sim/testsuite/sim/frv/cstq.cgs +++ /dev/null @@ -1,355 +0,0 @@ -# frv testcase for cstq $GRk,@($GRi,$GRj),$CCi,$cond -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global cstq -cstq: - set_spr_immed 0x1b1b,cccr - - set_gr_gr sp,gr22 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - cstq gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xbeef,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xbeef,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - set_gr_limmed 0xcccc,0xcccc,gr10 - set_gr_limmed 0xdddd,0xdddd,gr11 - cstq gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xaaaa,0xaaaa,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbbbb,0xbbbb,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xcccc,0xcccc,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdddd,0xdddd,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - set_gr_limmed 0x1111,0x1111,gr8 - set_gr_limmed 0x2222,0x2222,gr9 - set_gr_limmed 0x3333,0x3333,gr10 - set_gr_limmed 0x4444,0x4444,gr11 - cstq gr8,@(sp,gr7),cc4,1 - test_mem_limmed 0x1111,0x1111,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0x2222,0x2222,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0x3333,0x3333,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0x4444,0x4444,gr21 - - set_gr_gr gr22,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - cstq gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - set_gr_limmed 0xcccc,0xcccc,gr10 - set_gr_limmed 0xdddd,0xdddd,gr11 - cstq gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - set_gr_limmed 0x1111,0x1111,gr8 - set_gr_limmed 0x2222,0x2222,gr9 - set_gr_limmed 0x3333,0x3333,gr10 - set_gr_limmed 0x4444,0x4444,gr11 - cstq gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr22,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - cstq gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xbeef,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xbeef,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - set_gr_limmed 0xcccc,0xcccc,gr10 - set_gr_limmed 0xdddd,0xdddd,gr11 - cstq gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xaaaa,0xaaaa,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbbbb,0xbbbb,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xcccc,0xcccc,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdddd,0xdddd,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - set_gr_limmed 0x1111,0x1111,gr8 - set_gr_limmed 0x2222,0x2222,gr9 - set_gr_limmed 0x3333,0x3333,gr10 - set_gr_limmed 0x4444,0x4444,gr11 - cstq gr8,@(sp,gr7),cc5,0 - test_mem_limmed 0x1111,0x1111,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0x2222,0x2222,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0x3333,0x3333,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0x4444,0x4444,gr21 - - set_gr_gr gr22,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - cstq gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - set_gr_limmed 0xcccc,0xcccc,gr10 - set_gr_limmed 0xdddd,0xdddd,gr11 - cstq gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - set_gr_limmed 0x1111,0x1111,gr8 - set_gr_limmed 0x2222,0x2222,gr9 - set_gr_limmed 0x3333,0x3333,gr10 - set_gr_limmed 0x4444,0x4444,gr11 - cstq gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr22,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - cstq gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - set_gr_limmed 0xcccc,0xcccc,gr10 - set_gr_limmed 0xdddd,0xdddd,gr11 - cstq gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - set_gr_limmed 0x1111,0x1111,gr8 - set_gr_limmed 0x2222,0x2222,gr9 - set_gr_limmed 0x3333,0x3333,gr10 - set_gr_limmed 0x4444,0x4444,gr11 - cstq gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr22,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - cstq gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - set_gr_limmed 0xcccc,0xcccc,gr10 - set_gr_limmed 0xdddd,0xdddd,gr11 - cstq gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - set_gr_limmed 0x1111,0x1111,gr8 - set_gr_limmed 0x2222,0x2222,gr9 - set_gr_limmed 0x3333,0x3333,gr10 - set_gr_limmed 0x4444,0x4444,gr11 - cstq gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - pass diff --git a/sim/testsuite/sim/frv/cstu.cgs b/sim/testsuite/sim/frv/cstu.cgs deleted file mode 100644 index 81a5b82..0000000 --- a/sim/testsuite/sim/frv/cstu.cgs +++ /dev/null @@ -1,152 +0,0 @@ -# frv testcase for cstu $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstu -cstu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xffff,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cstu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xeeee,0xffff,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cstu gr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xcccc,0xdddd,gr21 - test_gr_gr sp,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed -4,sp - set_gr_gr sp,gr20 - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cstu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 8,sp - set_gr_gr sp,gr20 - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cstu gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xffff,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cstu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xeeee,0xffff,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cstu gr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xcccc,0xdddd,gr21 - test_gr_gr sp,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed -4,sp - set_gr_gr sp,gr20 - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cstu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 8,sp - set_gr_gr sp,gr20 - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cstu gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstu gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed -4,sp - set_gr_gr sp,gr20 - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cstu gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 8,sp - set_gr_gr sp,gr20 - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cstu gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstu gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed -4,sp - set_gr_gr sp,gr20 - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cstu gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 8,sp - set_gr_gr sp,gr20 - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cstu gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/csub.cgs b/sim/testsuite/sim/frv/csub.cgs deleted file mode 100644 index 7d07c14..0000000 --- a/sim/testsuite/sim/frv/csub.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for csub $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csub -csub: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - csub gr8,gr7,gr8,cc4,1 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - csub gr8,gr7,gr8,cc4,1 - test_gr_limmed 0x7fff,0xffff,gr8 - - csub gr8,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - - csub gr8,gr7,gr8,cc4,1 - test_gr_immed -1,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - csub gr8,gr7,gr8,cc4,0 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - csub gr8,gr7,gr8,cc4,0 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr8,gr8,cc4,0 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr7,gr8,cc4,0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - csub gr8,gr7,gr8,cc5,0 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - csub gr8,gr7,gr8,cc5,0 - test_gr_limmed 0x7fff,0xffff,gr8 - - csub gr8,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - - csub gr8,gr7,gr8,cc5,0 - test_gr_immed -1,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - csub gr8,gr7,gr8,cc5,1 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - csub gr8,gr7,gr8,cc5,1 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr8,gr8,cc5,1 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr7,gr8,cc5,1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - csub gr8,gr7,gr8,cc6,1 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - csub gr8,gr7,gr8,cc6,0 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr8,gr8,cc6,1 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr7,gr8,cc6,0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - csub gr8,gr7,gr8,cc7,0 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - csub gr8,gr7,gr8,cc7,1 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr8,gr8,cc7,0 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr7,gr8,cc7,1 - test_gr_limmed 0x8000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csubcc.cgs b/sim/testsuite/sim/frv/csubcc.cgs deleted file mode 100644 index 64cd93b..0000000 --- a/sim/testsuite/sim/frv/csubcc.cgs +++ /dev/null @@ -1,156 +0,0 @@ -# frv testcase for csubcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csubcc -csubcc: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc0,1 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_icc 0x0b,0 ; Set mask opposite of expected - csubcc gr8,gr8,gr8,cc4,1 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc4,1 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc0,0 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x0b,0 ; Set mask opposite of expected - csubcc gr8,gr8,gr8,cc4,0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x06,0 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc4,0 - test_icc 0 1 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc1,0 - test_icc 0 0 1 0 icc1 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_icc 0x0b,1 ; Set mask opposite of expected - csubcc gr8,gr8,gr8,cc5,0 - test_icc 0 1 0 0 icc1 - test_gr_immed 0,gr8 - - set_icc 0x06,1 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc5,0 - test_icc 1 0 0 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc1,1 - test_icc 1 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x0b,1 ; Set mask opposite of expected - csubcc gr8,gr8,gr8,cc5,1 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x06,1 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc5,1 - test_icc 0 1 1 0 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,2 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc2,0 - test_icc 1 1 0 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x0b,2 ; Set mask opposite of expected - csubcc gr8,gr8,gr8,cc6,1 - test_icc 1 0 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x06,2 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc6,1 - test_icc 0 1 1 0 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,3 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc3,0 - test_icc 1 1 0 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x0b,3 ; Set mask opposite of expected - csubcc gr8,gr8,gr8,cc7,1 - test_icc 1 0 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x06,3 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc7,1 - test_icc 0 1 1 0 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cswap.cgs b/sim/testsuite/sim/frv/cswap.cgs deleted file mode 100644 index 19a51d5..0000000 --- a/sim/testsuite/sim/frv/cswap.cgs +++ /dev/null @@ -1,212 +0,0 @@ -# frv testcase for cswap @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cswap -cswap: - set_spr_immed 0x1b1b,cccr - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - cswap @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 0,gr7 - cswap @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - cswap @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xbeef,0xdead,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - cswap @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_immed 0,gr7 - cswap @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed 4,gr7 - cswap @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - cswap @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 0,gr7 - cswap @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - cswap @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xbeef,0xdead,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - cswap @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_immed 0,gr7 - cswap @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed 4,gr7 - cswap @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - cswap @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_immed 0,gr7 - cswap @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed 4,gr7 - cswap @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - cswap @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_immed 0,gr7 - cswap @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed 4,gr7 - cswap @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cudiv.cgs b/sim/testsuite/sim/frv/cudiv.cgs deleted file mode 100644 index 78f44ae..0000000 --- a/sim/testsuite/sim/frv/cudiv.cgs +++ /dev/null @@ -1,96 +0,0 @@ -# frv testcase for cudiv $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cudiv -cudiv: - set_spr_immed 0x1b1b,cccr - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - cudiv gr3,gr2,gr3,cc0,1 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x00000004,gr3 - - ; example 1 from division in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - cudiv gr3,gr2,gr3,cc4,1 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_immed 0x000000e0,gr3 - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - cudiv gr3,gr2,gr3,cc0,0 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x0000000c,gr3 - - ; example 1 from division in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - cudiv gr3,gr2,gr3,cc4,0 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_limmed 0xfedc,0xba98,gr3 - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - cudiv gr3,gr2,gr3,cc1,0 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x00000004,gr3 - - ; example 1 from division in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - cudiv gr3,gr2,gr3,cc5,0 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_immed 0x000000e0,gr3 - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - cudiv gr3,gr2,gr3,cc1,1 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x0000000c,gr3 - - ; example 1 from division in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - cudiv gr3,gr2,gr3,cc5,1 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_limmed 0xfedc,0xba98,gr3 - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - cudiv gr3,gr2,gr3,cc2,0 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x0000000c,gr3 - - ; example 1 from division in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - cudiv gr3,gr2,gr3,cc6,1 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_limmed 0xfedc,0xba98,gr3 - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - cudiv gr3,gr2,gr3,cc3,0 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x0000000c,gr3 - - ; example 1 from division in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - cudiv gr3,gr2,gr3,cc7,1 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_limmed 0xfedc,0xba98,gr3 - - pass diff --git a/sim/testsuite/sim/frv/cxor.cgs b/sim/testsuite/sim/frv/cxor.cgs deleted file mode 100644 index 54a672d..0000000 --- a/sim/testsuite/sim/frv/cxor.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for cxor $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cxor -cxor: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc0,1 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc4,1 - test_icc 1 0 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc4,1 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc0,0 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc4,0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc4,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc1,0 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc5,0 - test_icc 1 0 1 1 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc5,0 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc1,1 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc5,1 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc5,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,2 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc2,0 - test_icc 0 1 1 1 icc2 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc2,0 - test_icc 1 0 0 0 icc2 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,2 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc6,1 - test_icc 1 0 1 1 icc2 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc6,1 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,3 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc3,0 - test_icc 0 1 1 1 icc3 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc3,0 - test_icc 1 0 0 0 icc3 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,3 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc7,1 - test_icc 1 0 1 1 icc3 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc7,1 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x0000,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cxorcc.cgs b/sim/testsuite/sim/frv/cxorcc.cgs deleted file mode 100644 index 86d917d..0000000 --- a/sim/testsuite/sim/frv/cxorcc.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for cxorcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cxorcc -cxorcc: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc0,1 - test_icc 0 1 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc4,0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc4,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc1,0 - test_icc 0 1 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 0 1 icc1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc5,1 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc5,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,2 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 1 1 icc2 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc2,0 - test_icc 1 0 0 0 icc2 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,2 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc6,1 - test_icc 1 0 1 1 icc2 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc6,1 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,3 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 1 1 icc3 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc3,0 - test_icc 1 0 0 0 icc3 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,3 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc7,1 - test_icc 1 0 1 1 icc3 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc7,1 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x0000,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/dcef.cgs b/sim/testsuite/sim/frv/dcef.cgs deleted file mode 100644 index 74475ef..0000000 --- a/sim/testsuite/sim/frv/dcef.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for dcef @(GRi,GRj),a -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global dcef -dcef: - and_spr_immed 0x7fffffff,hsr0 ; data cache only: copy-back mode - set_gr_addr doit,gr10 - set_gr_immed 0,gr11 - set_gr_immed 1,gr12 - set_gr_immed 2,gr13 - set_gr_immed 3,gr14 - - set_spr_addr ok1,lr - bra doit -ok1: test_gr_immed 1,gr11 - - set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache - set_spr_addr ok2,lr - bra doit -ok2: test_gr_immed 2,gr11 ; still only added 1 - - set_gr_addr doit1,gr10 - set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache - dcef @(gr10,gr0),1 ; flush data cache - set_spr_addr ok3,lr - bra doit1 -ok3: test_gr_immed 4,gr11 ; added 2 this time - - set_gr_addr doit2,gr10 - set_mem_immed 0x9600b00e,gr10 ; change to add gr11,gr14,gr11 in cache - dcef @(gr0,gr0),1 ; flush data cache - set_spr_addr ok4,lr - bra doit2 -ok4: test_gr_immed 7,gr11 ; added 3 this time - - pass - -doit: add gr11,gr12,gr11 - bralr - -doit1: add gr11,gr12,gr11 - bralr - -doit2: add gr11,gr12,gr11 - bralr - diff --git a/sim/testsuite/sim/frv/dcei.cgs b/sim/testsuite/sim/frv/dcei.cgs deleted file mode 100644 index 6254c06..0000000 --- a/sim/testsuite/sim/frv/dcei.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for dcei @(GRi,GRj),a -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global dcei -dcei: - or_spr_immed 0x08000000,hsr0 ; data cache: copy-back mode - - set_mem_immed 0xdeadbeef,sp - test_mem_immed 0xdeadbeef,sp - - flush_data_cache sp - set_mem_immed 0xbeefdead,sp - test_mem_immed 0xbeefdead,sp - - dcei @(sp,gr0),1 - test_mem_immed 0xdeadbeef,sp - - set_mem_immed 0xbeefdead,sp - test_mem_immed 0xbeefdead,sp - dcei @(gr0,gr0),1 - test_mem_immed 0xdeadbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/dcf.cgs b/sim/testsuite/sim/frv/dcf.cgs deleted file mode 100644 index f6e670e..0000000 --- a/sim/testsuite/sim/frv/dcf.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# FRV testcase for dcf @(GRi,GRj) -# mach: all - - .include "testutils.inc" - - start - - .global dcf -dcf: - and_spr_immed 0x7fffffff,hsr0 ; data cache only: copy-back mode - set_gr_addr doit,gr10 - set_gr_immed 0,gr11 - set_gr_immed 1,gr12 - set_gr_immed 2,gr13 - - set_spr_addr ok1,lr - bra doit -ok1: test_gr_immed 1,gr11 - - set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache - set_spr_addr ok2,lr - bra doit -ok2: test_gr_immed 2,gr11 ; still only added 1 - - set_gr_addr doit1,gr10 - set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache - dcf @(gr10,gr0) ; flush data cache - set_spr_addr ok3,lr - bra doit1 -ok3: test_gr_immed 4,gr11 ; added 2 this time - - pass - -doit: add gr11,gr12,gr11 - bralr - -doit1: add gr11,gr12,gr11 - bralr - diff --git a/sim/testsuite/sim/frv/dci.cgs b/sim/testsuite/sim/frv/dci.cgs deleted file mode 100644 index de481c3..0000000 --- a/sim/testsuite/sim/frv/dci.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# FRV testcase for dci @(GRi,GRj) -# mach: all - - .include "testutils.inc" - - start - - .global dci -dci: - or_spr_immed 0x08000000,hsr0 ; data cache: copy-back mode - - set_mem_immed 0xdeadbeef,sp - test_mem_immed 0xdeadbeef,sp - - flush_data_cache sp - set_mem_immed 0xbeefdead,sp - test_mem_immed 0xbeefdead,sp - - dci @(sp,gr0) - test_mem_immed 0xdeadbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/exit47.ms b/sim/testsuite/sim/frv/exit47.ms deleted file mode 100644 index 53306e5..0000000 --- a/sim/testsuite/sim/frv/exit47.ms +++ /dev/null @@ -1,11 +0,0 @@ -# mach: all -# status: 47 -# output: - - ;; Return with exit code 47. - - .global _start -_start: - setlos #47,gr8 - setlos #1,gr7 - tira gr0,#0 diff --git a/sim/testsuite/sim/frv/fabsd.cgs b/sim/testsuite/sim/frv/fabsd.cgs deleted file mode 100644 index 41a485e..0000000 --- a/sim/testsuite/sim/frv/fabsd.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for fabsd $FRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fabsd -fabsd: - fabsd fr0,fr2 - test_dfr_dfr fr2,fr52 - fabsd fr8,fr2 - test_dfr_dfr fr2,fr28 - fabsd fr12,fr2 - test_dfr_dfr fr2,fr24 - fabsd fr24,fr2 - test_dfr_dfr fr2,fr24 - fabsd fr28,fr2 - test_dfr_dfr fr2,fr28 - fabsd fr52,fr2 - test_dfr_dfr fr2,fr52 - - pass diff --git a/sim/testsuite/sim/frv/fabss.cgs b/sim/testsuite/sim/frv/fabss.cgs deleted file mode 100644 index f48514a..0000000 --- a/sim/testsuite/sim/frv/fabss.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for fabss $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fabss -fabss: - fabss fr0,fr1 - test_fr_fr fr1,fr52 - fabss fr8,fr1 - test_fr_fr fr1,fr28 - fabss fr12,fr1 - test_fr_fr fr1,fr24 - fabss fr24,fr1 - test_fr_fr fr1,fr24 - fabss fr28,fr1 - test_fr_fr fr1,fr28 - fabss fr52,fr1 - test_fr_fr fr1,fr52 - - pass diff --git a/sim/testsuite/sim/frv/faddd.cgs b/sim/testsuite/sim/frv/faddd.cgs deleted file mode 100644 index dbb6373..0000000 --- a/sim/testsuite/sim/frv/faddd.cgs +++ /dev/null @@ -1,93 +0,0 @@ -# frv testcase for faddd $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global faddd -faddd: - faddd fr16,fr0,fr2 - test_dfr_dfr fr2,fr0 - faddd fr16,fr4,fr2 - test_dfr_dfr fr2,fr4 - faddd fr16,fr8,fr2 - test_dfr_dfr fr2,fr8 - faddd fr16,fr12,fr2 - test_dfr_dfr fr2,fr12 - faddd fr16,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - faddd fr16,fr20,fr2 - test_dfr_dfr fr2,fr26 - test_dfr_dfr fr2,fr20 - faddd fr16,fr24,fr2 - test_dfr_dfr fr2,fr24 - faddd fr16,fr28,fr2 - test_dfr_dfr fr2,fr28 - faddd fr16,fr32,fr2 - test_dfr_dfr fr2,fr32 - faddd fr16,fr36,fr2 - test_dfr_dfr fr2,fr36 - faddd fr16,fr40,fr2 - test_dfr_dfr fr2,fr40 - faddd fr16,fr44,fr2 - test_dfr_dfr fr2,fr44 - faddd fr16,fr48,fr2 - test_dfr_dfr fr2,fr48 - faddd fr16,fr52,fr2 - test_dfr_dfr fr2,fr52 - - faddd fr20,fr0,fr2 - test_dfr_dfr fr2,fr0 - faddd fr20,fr4,fr2 - test_dfr_dfr fr2,fr4 - faddd fr20,fr8,fr2 - test_dfr_dfr fr2,fr8 - faddd fr20,fr12,fr2 - test_dfr_dfr fr2,fr12 - faddd fr20,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - faddd fr20,fr20,fr2 - test_dfr_dfr fr2,fr26 - test_dfr_dfr fr2,fr20 - faddd fr20,fr24,fr2 - test_dfr_dfr fr2,fr24 - faddd fr20,fr28,fr2 - test_dfr_dfr fr2,fr28 - faddd fr20,fr32,fr2 - test_dfr_dfr fr2,fr32 - faddd fr20,fr36,fr2 - test_dfr_dfr fr2,fr36 - faddd fr20,fr40,fr2 - test_dfr_dfr fr2,fr40 - faddd fr20,fr44,fr2 - test_dfr_dfr fr2,fr44 - faddd fr20,fr48,fr2 - test_dfr_dfr fr2,fr48 - faddd fr20,fr52,fr2 - test_dfr_dfr fr2,fr52 - - faddd fr8,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - faddd fr12,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - faddd fr24,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - faddd fr28,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - faddd fr36,fr40,fr2 - test_dfr_dfr fr2,fr44 - - pass - - diff --git a/sim/testsuite/sim/frv/fadds.cgs b/sim/testsuite/sim/frv/fadds.cgs deleted file mode 100644 index d741ac9..0000000 --- a/sim/testsuite/sim/frv/fadds.cgs +++ /dev/null @@ -1,92 +0,0 @@ -# frv testcase for fadds $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fadds -fadds: - fadds fr16,fr0,fr1 - test_fr_fr fr1,fr0 - fadds fr16,fr4,fr1 - test_fr_fr fr1,fr4 - fadds fr16,fr8,fr1 - test_fr_fr fr1,fr8 - fadds fr16,fr12,fr1 - test_fr_fr fr1,fr12 - fadds fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr16,fr24,fr1 - test_fr_fr fr1,fr24 - fadds fr16,fr28,fr1 - test_fr_fr fr1,fr28 - fadds fr16,fr32,fr1 - test_fr_fr fr1,fr32 - fadds fr16,fr36,fr1 - test_fr_fr fr1,fr36 - fadds fr16,fr40,fr1 - test_fr_fr fr1,fr40 - fadds fr16,fr44,fr1 - test_fr_fr fr1,fr44 - fadds fr16,fr48,fr1 - test_fr_fr fr1,fr48 - fadds fr16,fr52,fr1 - test_fr_fr fr1,fr52 - - fadds fr20,fr0,fr1 - test_fr_fr fr1,fr0 - fadds fr20,fr4,fr1 - test_fr_fr fr1,fr4 - fadds fr20,fr8,fr1 - test_fr_fr fr1,fr8 - fadds fr20,fr12,fr1 - test_fr_fr fr1,fr12 - fadds fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr20,fr24,fr1 - test_fr_fr fr1,fr24 - fadds fr20,fr28,fr1 - test_fr_fr fr1,fr28 - fadds fr20,fr32,fr1 - test_fr_fr fr1,fr32 - fadds fr20,fr36,fr1 - test_fr_fr fr1,fr36 - fadds fr20,fr40,fr1 - test_fr_fr fr1,fr40 - fadds fr20,fr44,fr1 - test_fr_fr fr1,fr44 - fadds fr20,fr48,fr1 - test_fr_fr fr1,fr48 - fadds fr20,fr52,fr1 - test_fr_fr fr1,fr52 - - fadds fr8,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr12,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr24,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr28,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fadds fr36,fr40,fr1 - test_fr_fr fr1,fr44 - - pass - - diff --git a/sim/testsuite/sim/frv/fbeq.cgs b/sim/testsuite/sim/frv/fbeq.cgs deleted file mode 100644 index e51b2c9..0000000 --- a/sim/testsuite/sim/frv/fbeq.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for fbeq $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbeq -fbeq: - set_fcc 0x0 0 - fbeq fcc0,0,bad - set_fcc 0x1 1 - fbeq fcc1,1,bad - set_fcc 0x2 2 - fbeq fcc2,2,bad - set_fcc 0x3 3 - fbeq fcc3,3,bad - set_fcc 0x4 0 - fbeq fcc0,0,bad - set_fcc 0x5 1 - fbeq fcc1,1,bad - set_fcc 0x6 2 - fbeq fcc2,2,bad - set_fcc 0x7 3 - fbeq fcc3,3,bad - set_fcc 0x8 0 - fbeq fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fbeq fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbeq fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbeq fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbeq fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbeq fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbeq fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbeq fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbeqlr.cgs b/sim/testsuite/sim/frv/fbeqlr.cgs deleted file mode 100644 index af29cb9..0000000 --- a/sim/testsuite/sim/frv/fbeqlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for fbeqlr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbeqlr -fbeqlr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbeqlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fbeqlr fcc1,1 - - set_spr_addr bad,lr - set_fcc 0x2 2 - fbeqlr fcc2,2 - - set_spr_addr bad,lr - set_fcc 0x3 3 - fbeqlr fcc3,3 - - set_spr_addr bad,lr - set_fcc 0x4 0 - fbeqlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x5 1 - fbeqlr fcc1,1 - - set_spr_addr bad,lr - set_fcc 0x6 2 - fbeqlr fcc2,2 - - set_spr_addr bad,lr - set_fcc 0x7 3 - fbeqlr fcc3,3 - - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbeqlr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbeqlr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbeqlr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbeqlr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbeqlr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbeqlr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbeqlr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbeqlr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbge.cgs b/sim/testsuite/sim/frv/fbge.cgs deleted file mode 100644 index a20029e..0000000 --- a/sim/testsuite/sim/frv/fbge.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for fbge $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbge -fbge: - set_fcc 0x0 0 - fbge fcc0,0,bad - set_fcc 0x1 1 - fbge fcc1,1,bad - set_fcc 0x2 2 - fbge fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fbge fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbge fcc0,0,bad - set_fcc 0x5 1 - fbge fcc1,1,bad - set_fcc 0x6 2 - fbge fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbge fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbge fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fbge fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbge fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbge fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbge fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbge fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbge fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbge fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbgelr.cgs b/sim/testsuite/sim/frv/fbgelr.cgs deleted file mode 100644 index 59e9410..0000000 --- a/sim/testsuite/sim/frv/fbgelr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for fbgelr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbgelr -fbgelr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbgelr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fbgelr fcc1,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbgelr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbgelr fcc3,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fbgelr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x5 1 - fbgelr fcc1,1 - - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbgelr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbgelr fcc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbgelr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbgelr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbgelr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbgelr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbgelr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbgelr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbgelr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbgelr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbgt.cgs b/sim/testsuite/sim/frv/fbgt.cgs deleted file mode 100644 index 7cc4ea7..0000000 --- a/sim/testsuite/sim/frv/fbgt.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for fbgt $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbgt -fbgt: - set_fcc 0x0 0 - fbgt fcc0,0,bad - set_fcc 0x1 1 - fbgt fcc1,1,bad - set_fcc 0x2 2 - fbgt fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fbgt fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbgt fcc0,0,bad - set_fcc 0x5 1 - fbgt fcc1,1,bad - set_fcc 0x6 2 - fbgt fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbgt fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbgt fcc0,0,bad - set_fcc 0x9 1 - fbgt fcc1,1,bad - set_fcc 0xa 2 - fbgt fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbgt fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbgt fcc0,0,bad - set_fcc 0xd 1 - fbgt fcc1,1,bad - set_fcc 0xe 2 - fbgt fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbgt fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbgtlr.cgs b/sim/testsuite/sim/frv/fbgtlr.cgs deleted file mode 100644 index 7e4a7a5..0000000 --- a/sim/testsuite/sim/frv/fbgtlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for fbgtlr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbgtlr -fbgtlr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbgtlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fbgtlr fcc1,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbgtlr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbgtlr fcc3,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fbgtlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x5 1 - fbgtlr fcc1,1 - - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbgtlr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbgtlr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fbgtlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x9 1 - fbgtlr fcc1,1 - - set_spr_addr okb,lr - set_fcc 0xa 2 - fbgtlr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbgtlr fcc3,3 - fail -okc: - set_spr_addr bad,lr - set_fcc 0xc 0 - fbgtlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0xd 1 - fbgtlr fcc1,1 - - set_spr_addr okf,lr - set_fcc 0xe 2 - fbgtlr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbgtlr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fble.cgs b/sim/testsuite/sim/frv/fble.cgs deleted file mode 100644 index e52936a..0000000 --- a/sim/testsuite/sim/frv/fble.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for fble $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fble -fble: - set_fcc 0x0 0 - fble fcc0,0,bad - set_fcc 0x1 1 - fble fcc1,1,bad - set_fcc 0x2 2 - fble fcc2,2,bad - set_fcc 0x3 3 - fble fcc3,3,bad - set_fcc 0x4 0 - fble fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fble fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fble fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fble fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fble fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fble fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fble fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fble fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fble fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fble fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fble fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fble fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fblelr.cgs b/sim/testsuite/sim/frv/fblelr.cgs deleted file mode 100644 index 92a47bc..0000000 --- a/sim/testsuite/sim/frv/fblelr.cgs +++ /dev/null @@ -1,89 +0,0 @@ -# frv testcase for fblelr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fblelr -fblelr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fblelr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fblelr fcc1,1 - - set_spr_addr bad,lr - set_fcc 0x2 2 - fblelr fcc2,2 - - set_spr_addr bad,lr - set_fcc 0x3 3 - fblelr fcc3,3 - - set_spr_addr ok5,lr - set_fcc 0x4 0 - fblelr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fblelr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fblelr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fblelr fcc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fblelr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fblelr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fblelr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fblelr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fblelr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fblelr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fblelr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fblelr fcc3,3 - fail -okg: - pass -bad: - fail - diff --git a/sim/testsuite/sim/frv/fblg.cgs b/sim/testsuite/sim/frv/fblg.cgs deleted file mode 100644 index a16f802..0000000 --- a/sim/testsuite/sim/frv/fblg.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for fblg $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fblg -fblg: - set_fcc 0x0 0 - fblg fcc0,0,bad - set_fcc 0x1 1 - fblg fcc1,1,bad - set_fcc 0x2 2 - fblg fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fblg fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fblg fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fblg fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fblg fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fblg fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fblg fcc0,0,bad - set_fcc 0x9 1 - fblg fcc1,1,bad - set_fcc 0xa 2 - fblg fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fblg fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fblg fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fblg fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fblg fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fblg fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fblglr.cgs b/sim/testsuite/sim/frv/fblglr.cgs deleted file mode 100644 index e7a32b0..0000000 --- a/sim/testsuite/sim/frv/fblglr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for fblglr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fblglr -fblglr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fblglr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fblglr fcc1,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fblglr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fblglr fcc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fblglr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fblglr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fblglr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fblglr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fblglr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x9 1 - fblglr fcc1,1 - - set_spr_addr okb,lr - set_fcc 0xa 2 - fblglr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fblglr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fblglr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fblglr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fblglr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fblglr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fblt.cgs b/sim/testsuite/sim/frv/fblt.cgs deleted file mode 100644 index ef7e5c7..0000000 --- a/sim/testsuite/sim/frv/fblt.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for fblt $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fblt -fblt: - set_fcc 0x0 0 - fblt fcc0,0,bad - set_fcc 0x1 1 - fblt fcc1,1,bad - set_fcc 0x2 2 - fblt fcc2,2,bad - set_fcc 0x3 3 - fblt fcc3,3,bad - set_fcc 0x4 0 - fblt fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fblt fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fblt fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fblt fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fblt fcc0,0,bad - set_fcc 0x9 1 - fblt fcc1,1,bad - set_fcc 0xa 2 - fblt fcc2,2,bad - set_fcc 0xb 3 - fblt fcc3,3,bad - set_fcc 0xc 0 - fblt fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fblt fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fblt fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fblt fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbltlr.cgs b/sim/testsuite/sim/frv/fbltlr.cgs deleted file mode 100644 index 0a2c436..0000000 --- a/sim/testsuite/sim/frv/fbltlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for fbltlr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbltlr -fbltlr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbltlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fbltlr fcc1,1 - - set_spr_addr bad,lr - set_fcc 0x2 2 - fbltlr fcc2,2 - - set_spr_addr bad,lr - set_fcc 0x3 3 - fbltlr fcc3,3 - - set_spr_addr ok5,lr - set_fcc 0x4 0 - fbltlr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbltlr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbltlr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbltlr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fbltlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x9 1 - fbltlr fcc1,1 - - set_spr_addr bad,lr - set_fcc 0xa 2 - fbltlr fcc2,2 - - set_spr_addr bad,lr - set_fcc 0xb 3 - fbltlr fcc3,3 - - set_spr_addr okd,lr - set_fcc 0xc 0 - fbltlr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbltlr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbltlr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbltlr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbne.cgs b/sim/testsuite/sim/frv/fbne.cgs deleted file mode 100644 index f376eea..0000000 --- a/sim/testsuite/sim/frv/fbne.cgs +++ /dev/null @@ -1,73 +0,0 @@ -# frv testcase for fbne $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbne -fbne: - set_fcc 0x0 0 - fbne fcc0,0,bad - set_fcc 0x1 1 - fbne fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbne fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fbne fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbne fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fbne fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbne fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbne fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbne fcc0,0,bad - set_fcc 0x9 1 - fbne fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbne fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbne fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbne fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbne fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbne fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbne fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbnelr.cgs b/sim/testsuite/sim/frv/fbnelr.cgs deleted file mode 100644 index 334d185..0000000 --- a/sim/testsuite/sim/frv/fbnelr.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fbnelr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbnelr -fbnelr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbnelr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbnelr fcc1,1 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbnelr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbnelr fcc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fbnelr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbnelr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbnelr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbnelr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fbnelr fcc0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fbnelr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbnelr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbnelr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbnelr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbnelr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbnelr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbnelr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbno.cgs b/sim/testsuite/sim/frv/fbno.cgs deleted file mode 100644 index a3dc587..0000000 --- a/sim/testsuite/sim/frv/fbno.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for fbno $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbno -fbno: - set_fcc 0x0 0 - fbno - set_fcc 0x1 1 - fbno - set_fcc 0x2 2 - fbno - set_fcc 0x3 3 - fbno - set_fcc 0x4 0 - fbno - set_fcc 0x5 1 - fbno - set_fcc 0x6 2 - fbno - set_fcc 0x7 3 - fbno - set_fcc 0x8 0 - fbno - set_fcc 0x9 1 - fbno - set_fcc 0xa 2 - fbno - set_fcc 0xb 3 - fbno - set_fcc 0xc 0 - fbno - set_fcc 0xd 1 - fbno - set_fcc 0xe 2 - fbno - set_fcc 0xf 3 - fbno - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbnolr.cgs b/sim/testsuite/sim/frv/fbnolr.cgs deleted file mode 100644 index be5a0ef..0000000 --- a/sim/testsuite/sim/frv/fbnolr.cgs +++ /dev/null @@ -1,47 +0,0 @@ -# frv testcase for fbnolr -# mach: all - - .include "testutils.inc" - - start - - .global fbnolr -fbnolr: - set_spr_addr bad,lr - - set_fcc 0x0 0 - fbnolr - set_fcc 0x1 1 - fbnolr - set_fcc 0x2 2 - fbnolr - set_fcc 0x3 3 - fbnolr - set_fcc 0x4 0 - fbnolr - set_fcc 0x5 1 - fbnolr - set_fcc 0x6 2 - fbnolr - set_fcc 0x7 3 - fbnolr - set_fcc 0x8 0 - fbnolr - set_fcc 0x9 1 - fbnolr - set_fcc 0xa 2 - fbnolr - set_fcc 0xb 3 - fbnolr - set_fcc 0xc 0 - fbnolr - set_fcc 0xd 1 - fbnolr - set_fcc 0xe 2 - fbnolr - set_fcc 0xf 3 - fbnolr - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbo.cgs b/sim/testsuite/sim/frv/fbo.cgs deleted file mode 100644 index 42062c9..0000000 --- a/sim/testsuite/sim/frv/fbo.cgs +++ /dev/null @@ -1,73 +0,0 @@ -# frv testcase for fbo $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbo -fbo: - set_fcc 0x0 0 - fbo fcc0,0,bad - set_fcc 0x1 1 - fbo fcc1,1,bad - set_fcc 0x2 2 - fbo fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fbo fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbo fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fbo fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbo fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbo fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbo fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fbo fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbo fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbo fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbo fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbo fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbo fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbo fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbolr.cgs b/sim/testsuite/sim/frv/fbolr.cgs deleted file mode 100644 index 2f9bfb3..0000000 --- a/sim/testsuite/sim/frv/fbolr.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fbolr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbolr -fbolr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbolr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fbolr fcc1,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbolr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbolr fcc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fbolr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbolr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbolr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbolr fcc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbolr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbolr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbolr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbolr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbolr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbolr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbolr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbolr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbra.cgs b/sim/testsuite/sim/frv/fbra.cgs deleted file mode 100644 index 2f29308..0000000 --- a/sim/testsuite/sim/frv/fbra.cgs +++ /dev/null @@ -1,75 +0,0 @@ -# frv testcase for fbra $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbra -fbra: - set_fcc 0x0 0 - fbra ok1 - fail -ok1: - set_fcc 0x1 1 - fbra ok2 - fail -ok2: - set_fcc 0x2 2 - fbra ok3 - fail -ok3: - set_fcc 0x3 3 - fbra ok4 - fail -ok4: - set_fcc 0x4 0 - fbra ok5 - fail -ok5: - set_fcc 0x5 1 - fbra ok6 - fail -ok6: - set_fcc 0x6 2 - fbra ok7 - fail -ok7: - set_fcc 0x7 3 - fbra ok8 - fail -ok8: - set_fcc 0x8 0 - fbra ok9 - fail -ok9: - set_fcc 0x9 1 - fbra oka - fail -oka: - set_fcc 0xa 2 - fbra okb - fail -okb: - set_fcc 0xb 3 - fbra okc - fail -okc: - set_fcc 0xc 0 - fbra okd - fail -okd: - set_fcc 0xd 1 - fbra oke - fail -oke: - set_fcc 0xe 2 - fbra okf - fail -okf: - set_fcc 0xf 3 - fbra okg - fail -okg: - - pass diff --git a/sim/testsuite/sim/frv/fbralr.cgs b/sim/testsuite/sim/frv/fbralr.cgs deleted file mode 100644 index d57afc9..0000000 --- a/sim/testsuite/sim/frv/fbralr.cgs +++ /dev/null @@ -1,91 +0,0 @@ -# frv testcase for fbralr -# mach: all - - .include "testutils.inc" - - start - - .global fbralr -fbralr: - set_spr_addr ok1,lr - set_fcc 0x0 0 - fbralr - fail -ok1: - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbralr - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbralr - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbralr - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fbralr - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbralr - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbralr - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbralr - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbralr - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbralr - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbralr - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbralr - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbralr - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbralr - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbralr - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbralr - fail -okg: - - pass diff --git a/sim/testsuite/sim/frv/fbu.cgs b/sim/testsuite/sim/frv/fbu.cgs deleted file mode 100644 index f397001..0000000 --- a/sim/testsuite/sim/frv/fbu.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for fbu $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbu -fbu: - set_fcc 0x0 0 - fbu fcc0,0,bad - set_fcc 0x1 1 - fbu fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbu fcc2,2,bad - set_fcc 0x3 3 - fbu fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbu fcc0,0,bad - set_fcc 0x5 1 - fbu fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbu fcc2,2,bad - set_fcc 0x7 3 - fbu fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbu fcc0,0,bad - set_fcc 0x9 1 - fbu fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbu fcc2,2,bad - set_fcc 0xb 3 - fbu fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbu fcc0,0,bad - set_fcc 0xd 1 - fbu fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbu fcc2,2,bad - set_fcc 0xf 3 - fbu fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbue.cgs b/sim/testsuite/sim/frv/fbue.cgs deleted file mode 100644 index dd1d636..0000000 --- a/sim/testsuite/sim/frv/fbue.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for fbue $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbue -fbue: - set_fcc 0x0 0 - fbue fcc0,0,bad - set_fcc 0x1 1 - fbue fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbue fcc2,2,bad - set_fcc 0x3 3 - fbue fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbue fcc0,0,bad - set_fcc 0x5 1 - fbue fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbue fcc2,2,bad - set_fcc 0x7 3 - fbue fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbue fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fbue fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbue fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbue fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbue fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbue fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbue fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbue fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbuelr.cgs b/sim/testsuite/sim/frv/fbuelr.cgs deleted file mode 100644 index 62ca6aa..0000000 --- a/sim/testsuite/sim/frv/fbuelr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for fbuelr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbuelr -fbuelr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbuelr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbuelr fcc1,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fbuelr fcc2,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbuelr fcc3,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fbuelr fcc0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbuelr fcc1,1 - fail -ok6: - set_spr_addr bad,lr - set_fcc 0x6 2 - fbuelr fcc2,2 - - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbuelr fcc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbuelr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbuelr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbuelr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbuelr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbuelr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbuelr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbuelr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbuelr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbug.cgs b/sim/testsuite/sim/frv/fbug.cgs deleted file mode 100644 index 3a5ee01..0000000 --- a/sim/testsuite/sim/frv/fbug.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for fbug $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbug -fbug: - set_fcc 0x0 0 - fbug fcc0,0,bad - set_fcc 0x1 1 - fbug fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbug fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fbug fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbug fcc0,0,bad - set_fcc 0x5 1 - fbug fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbug fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbug fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbug fcc0,0,bad - set_fcc 0x9 1 - fbug fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbug fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbug fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbug fcc0,0,bad - set_fcc 0xd 1 - fbug fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbug fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbug fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbuge.cgs b/sim/testsuite/sim/frv/fbuge.cgs deleted file mode 100644 index edbf7f8..0000000 --- a/sim/testsuite/sim/frv/fbuge.cgs +++ /dev/null @@ -1,73 +0,0 @@ -# frv testcase for fbuge $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbuge -fbuge: - set_fcc 0x0 0 - fbuge fcc0,0,bad - set_fcc 0x1 1 - fbuge fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbuge fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fbuge fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbuge fcc0,0,bad - set_fcc 0x5 1 - fbuge fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbuge fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbuge fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbuge fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fbuge fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbuge fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbuge fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbuge fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbuge fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbuge fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbuge fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbugelr.cgs b/sim/testsuite/sim/frv/fbugelr.cgs deleted file mode 100644 index b1799c5..0000000 --- a/sim/testsuite/sim/frv/fbugelr.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fbugelr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbugelr -fbugelr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbugelr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbugelr fcc1,1 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbugelr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbugelr fcc3,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fbugelr fcc0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbugelr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbugelr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbugelr fcc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbugelr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbugelr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbugelr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbugelr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbugelr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbugelr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbugelr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbugelr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbuglr.cgs b/sim/testsuite/sim/frv/fbuglr.cgs deleted file mode 100644 index d660a95..0000000 --- a/sim/testsuite/sim/frv/fbuglr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for fbuglr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbuglr -fbuglr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbuglr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbuglr fcc1,1 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbuglr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbuglr fcc3,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fbuglr fcc0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbuglr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbuglr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbuglr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fbuglr fcc0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fbuglr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbuglr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbuglr fcc3,3 - fail -okc: - set_spr_addr bad,lr - set_fcc 0xc 0 - fbuglr fcc0,0 - - set_spr_addr oke,lr - set_fcc 0xd 1 - fbuglr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbuglr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbuglr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbul.cgs b/sim/testsuite/sim/frv/fbul.cgs deleted file mode 100644 index 47b689d..0000000 --- a/sim/testsuite/sim/frv/fbul.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for fbul $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbul -fbul: - set_fcc 0x0 0 - fbul fcc0,0,bad - set_fcc 0x1 1 - fbul fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbul fcc2,2,bad - set_fcc 0x3 3 - fbul fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbul fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fbul fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbul fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbul fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbul fcc0,0,bad - set_fcc 0x9 1 - fbul fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbul fcc2,2,bad - set_fcc 0xb 3 - fbul fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbul fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbul fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbul fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbul fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbule.cgs b/sim/testsuite/sim/frv/fbule.cgs deleted file mode 100644 index ad5f4e9..0000000 --- a/sim/testsuite/sim/frv/fbule.cgs +++ /dev/null @@ -1,73 +0,0 @@ -# frv testcase for fbule $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbule -fbule: - set_fcc 0x0 0 - fbule fcc0,0,bad - set_fcc 0x1 1 - fbule fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbule fcc2,2,bad - set_fcc 0x3 3 - fbule fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbule fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fbule fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbule fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbule fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbule fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fbule fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbule fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbule fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbule fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbule fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbule fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbule fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbulelr.cgs b/sim/testsuite/sim/frv/fbulelr.cgs deleted file mode 100644 index f34d58c..0000000 --- a/sim/testsuite/sim/frv/fbulelr.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fbulelr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbulelr -fbulelr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbulelr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbulelr fcc1,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fbulelr fcc2,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbulelr fcc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fbulelr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbulelr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbulelr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbulelr fcc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbulelr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbulelr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbulelr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbulelr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbulelr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbulelr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbulelr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbulelr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbullr.cgs b/sim/testsuite/sim/frv/fbullr.cgs deleted file mode 100644 index 2d5b251..0000000 --- a/sim/testsuite/sim/frv/fbullr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for fbullr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbullr -fbullr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbullr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbullr fcc1,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fbullr fcc2,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbullr fcc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fbullr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbullr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbullr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbullr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fbullr fcc0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fbullr fcc1,1 - fail -oka: - set_spr_addr bad,lr - set_fcc 0xa 2 - fbullr fcc2,2 - - set_spr_addr okc,lr - set_fcc 0xb 3 - fbullr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbullr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbullr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbullr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbullr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbulr.cgs b/sim/testsuite/sim/frv/fbulr.cgs deleted file mode 100644 index d8594bc..0000000 --- a/sim/testsuite/sim/frv/fbulr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for fbulr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbulr -fbulr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbulr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbulr fcc1,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fbulr fcc2,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbulr fcc3,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fbulr fcc0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbulr fcc1,1 - fail -ok6: - set_spr_addr bad,lr - set_fcc 0x6 2 - fbulr fcc2,2 - - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbulr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fbulr fcc0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fbulr fcc1,1 - fail -oka: - set_spr_addr bad,lr - set_fcc 0xa 2 - fbulr fcc2,2 - - set_spr_addr okc,lr - set_fcc 0xb 3 - fbulr fcc3,3 - fail -okc: - set_spr_addr bad,lr - set_fcc 0xc 0 - fbulr fcc0,0 - - set_spr_addr oke,lr - set_fcc 0xd 1 - fbulr fcc1,1 - fail -oke: - set_spr_addr bad,lr - set_fcc 0xe 2 - fbulr fcc2,2 - - set_spr_addr okg,lr - set_fcc 0xf 3 - fbulr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbeqlr.cgs b/sim/testsuite/sim/frv/fcbeqlr.cgs deleted file mode 100644 index b87e77f..0000000 --- a/sim/testsuite/sim/frv/fcbeqlr.cgs +++ /dev/null @@ -1,262 +0,0 @@ -# frv testcase for fcbeqlr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbeqlr -fcbeqlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbeqlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbeqlr fcc1,0,1 - - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbeqlr fcc2,0,2 - - set_spr_addr bad,lr - set_fcc 0x3 3 - fcbeqlr fcc3,0,3 - - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbeqlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x5 1 - fcbeqlr fcc1,0,1 - - set_spr_addr bad,lr - set_fcc 0x6 2 - fcbeqlr fcc2,0,2 - - set_spr_addr bad,lr - set_fcc 0x7 3 - fcbeqlr fcc3,0,3 - - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbeqlr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbeqlr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbeqlr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbeqlr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbeqlr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbeqlr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbeqlr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbeqlr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbeqlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbeqlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbeqlr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x3 3 - fcbeqlr fcc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbeqlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x5 1 - fcbeqlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x6 2 - fcbeqlr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x7 3 - fcbeqlr fcc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbeqlr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbeqlr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbeqlr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbeqlr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbeqlr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbeqlr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbeqlr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbeqlr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbeqlr fcc0,1,0 - set_fcc 0x1 1 - fcbeqlr fcc1,1,1 - set_fcc 0x2 2 - fcbeqlr fcc2,1,2 - set_fcc 0x3 3 - fcbeqlr fcc3,1,3 - set_fcc 0x4 0 - fcbeqlr fcc0,1,0 - set_fcc 0x5 1 - fcbeqlr fcc1,1,1 - set_fcc 0x6 2 - fcbeqlr fcc2,1,2 - set_fcc 0x7 3 - fcbeqlr fcc3,1,3 - set_fcc 0x8 0 - fcbeqlr fcc0,1,0 - set_fcc 0x9 1 - fcbeqlr fcc1,1,1 - set_fcc 0xa 2 - fcbeqlr fcc2,1,2 - set_fcc 0xb 3 - fcbeqlr fcc3,1,3 - set_fcc 0xc 0 - fcbeqlr fcc0,1,0 - set_fcc 0xd 1 - fcbeqlr fcc1,1,1 - set_fcc 0xe 2 - fcbeqlr fcc2,1,2 - set_fcc 0xf 3 - fcbeqlr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbeqlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbeqlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbeqlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbeqlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbeqlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbeqlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbeqlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbeqlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbeqlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbeqlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbeqlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbeqlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbeqlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbeqlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbeqlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbeqlr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbgelr.cgs b/sim/testsuite/sim/frv/fcbgelr.cgs deleted file mode 100644 index cc1b9d7..0000000 --- a/sim/testsuite/sim/frv/fcbgelr.cgs +++ /dev/null @@ -1,270 +0,0 @@ -# frv testcase for fcbgelr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbgelr -fcbgelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbgelr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbgelr fcc1,0,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbgelr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbgelr fcc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbgelr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x5 1 - fcbgelr fcc1,0,1 - - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbgelr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbgelr fcc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbgelr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbgelr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbgelr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbgelr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbgelr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbgelr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbgelr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbgelr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbgelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbgelr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbgelr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbgelr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbgelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x5 1 - fcbgelr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbgelr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbgelr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbgelr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbgelr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbgelr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbgelr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbgelr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbgelr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbgelr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbgelr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbgelr fcc0,1,0 - set_fcc 0x1 1 - fcbgelr fcc1,1,1 - set_fcc 0x2 2 - fcbgelr fcc2,1,2 - set_fcc 0x3 3 - fcbgelr fcc3,1,3 - set_fcc 0x4 0 - fcbgelr fcc0,1,0 - set_fcc 0x5 1 - fcbgelr fcc1,1,1 - set_fcc 0x6 2 - fcbgelr fcc2,1,2 - set_fcc 0x7 3 - fcbgelr fcc3,1,3 - set_fcc 0x8 0 - fcbgelr fcc0,1,0 - set_fcc 0x9 1 - fcbgelr fcc1,1,1 - set_fcc 0xa 2 - fcbgelr fcc2,1,2 - set_fcc 0xb 3 - fcbgelr fcc3,1,3 - set_fcc 0xc 0 - fcbgelr fcc0,1,0 - set_fcc 0xd 1 - fcbgelr fcc1,1,1 - set_fcc 0xe 2 - fcbgelr fcc2,1,2 - set_fcc 0xf 3 - fcbgelr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbgelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbgelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbgelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbgelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbgelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbgelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbgelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbgelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbgelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbgelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbgelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbgelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbgelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbgelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbgelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbgelr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbgtlr.cgs b/sim/testsuite/sim/frv/fcbgtlr.cgs deleted file mode 100644 index 76204e2..0000000 --- a/sim/testsuite/sim/frv/fcbgtlr.cgs +++ /dev/null @@ -1,262 +0,0 @@ -# frv testcase for fcbgtlr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbgtlr -fcbgtlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbgtlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbgtlr fcc1,0,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbgtlr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbgtlr fcc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbgtlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x5 1 - fcbgtlr fcc1,0,1 - - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbgtlr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbgtlr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbgtlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x9 1 - fcbgtlr fcc1,0,1 - - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbgtlr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbgtlr fcc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_fcc 0xc 0 - fcbgtlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0xd 1 - fcbgtlr fcc1,0,1 - - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbgtlr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbgtlr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbgtlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbgtlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbgtlr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbgtlr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbgtlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x5 1 - fcbgtlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbgtlr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbgtlr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbgtlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x9 1 - fcbgtlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbgtlr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbgtlr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xc 0 - fcbgtlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xd 1 - fcbgtlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbgtlr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbgtlr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbgtlr fcc0,1,0 - set_fcc 0x1 1 - fcbgtlr fcc1,1,1 - set_fcc 0x2 2 - fcbgtlr fcc2,1,2 - set_fcc 0x3 3 - fcbgtlr fcc3,1,3 - set_fcc 0x4 0 - fcbgtlr fcc0,1,0 - set_fcc 0x5 1 - fcbgtlr fcc1,1,1 - set_fcc 0x6 2 - fcbgtlr fcc2,1,2 - set_fcc 0x7 3 - fcbgtlr fcc3,1,3 - set_fcc 0x8 0 - fcbgtlr fcc0,1,0 - set_fcc 0x9 1 - fcbgtlr fcc1,1,1 - set_fcc 0xa 2 - fcbgtlr fcc2,1,2 - set_fcc 0xb 3 - fcbgtlr fcc3,1,3 - set_fcc 0xc 0 - fcbgtlr fcc0,1,0 - set_fcc 0xd 1 - fcbgtlr fcc1,1,1 - set_fcc 0xe 2 - fcbgtlr fcc2,1,2 - set_fcc 0xf 3 - fcbgtlr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbgtlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbgtlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbgtlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbgtlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbgtlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbgtlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbgtlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbgtlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbgtlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbgtlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbgtlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbgtlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbgtlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbgtlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbgtlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbgtlr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcblelr.cgs b/sim/testsuite/sim/frv/fcblelr.cgs deleted file mode 100644 index b9850d6..0000000 --- a/sim/testsuite/sim/frv/fcblelr.cgs +++ /dev/null @@ -1,270 +0,0 @@ -# frv testcase for fcblelr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcblelr -fcblelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcblelr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcblelr fcc1,0,1 - - set_spr_addr bad,lr - set_fcc 0x2 2 - fcblelr fcc2,0,2 - - set_spr_addr bad,lr - set_fcc 0x3 3 - fcblelr fcc3,0,3 - - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcblelr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcblelr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcblelr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcblelr fcc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcblelr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcblelr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcblelr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcblelr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcblelr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcblelr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcblelr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcblelr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcblelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcblelr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcblelr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x3 3 - fcblelr fcc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcblelr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcblelr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcblelr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcblelr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcblelr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcblelr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcblelr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcblelr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcblelr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcblelr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcblelr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcblelr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcblelr fcc0,1,0 - set_fcc 0x1 1 - fcblelr fcc1,1,1 - set_fcc 0x2 2 - fcblelr fcc2,1,2 - set_fcc 0x3 3 - fcblelr fcc3,1,3 - set_fcc 0x4 0 - fcblelr fcc0,1,0 - set_fcc 0x5 1 - fcblelr fcc1,1,1 - set_fcc 0x6 2 - fcblelr fcc2,1,2 - set_fcc 0x7 3 - fcblelr fcc3,1,3 - set_fcc 0x8 0 - fcblelr fcc0,1,0 - set_fcc 0x9 1 - fcblelr fcc1,1,1 - set_fcc 0xa 2 - fcblelr fcc2,1,2 - set_fcc 0xb 3 - fcblelr fcc3,1,3 - set_fcc 0xc 0 - fcblelr fcc0,1,0 - set_fcc 0xd 1 - fcblelr fcc1,1,1 - set_fcc 0xe 2 - fcblelr fcc2,1,2 - set_fcc 0xf 3 - fcblelr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcblelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcblelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcblelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcblelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcblelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcblelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcblelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcblelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcblelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcblelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcblelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcblelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcblelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcblelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcblelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcblelr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcblglr.cgs b/sim/testsuite/sim/frv/fcblglr.cgs deleted file mode 100644 index e875d40..0000000 --- a/sim/testsuite/sim/frv/fcblglr.cgs +++ /dev/null @@ -1,270 +0,0 @@ -# frv testcase for fcblglr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcblglr -fcblglr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcblglr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcblglr fcc1,0,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcblglr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcblglr fcc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcblglr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcblglr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcblglr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcblglr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcblglr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x9 1 - fcblglr fcc1,0,1 - - set_spr_addr okb,lr - set_fcc 0xa 2 - fcblglr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcblglr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcblglr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcblglr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcblglr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcblglr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcblglr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcblglr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcblglr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcblglr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcblglr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcblglr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcblglr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcblglr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcblglr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x9 1 - fcblglr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcblglr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcblglr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcblglr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcblglr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcblglr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcblglr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcblglr fcc0,1,0 - set_fcc 0x1 1 - fcblglr fcc1,1,1 - set_fcc 0x2 2 - fcblglr fcc2,1,2 - set_fcc 0x3 3 - fcblglr fcc3,1,3 - set_fcc 0x4 0 - fcblglr fcc0,1,0 - set_fcc 0x5 1 - fcblglr fcc1,1,1 - set_fcc 0x6 2 - fcblglr fcc2,1,2 - set_fcc 0x7 3 - fcblglr fcc3,1,3 - set_fcc 0x8 0 - fcblglr fcc0,1,0 - set_fcc 0x9 1 - fcblglr fcc1,1,1 - set_fcc 0xa 2 - fcblglr fcc2,1,2 - set_fcc 0xb 3 - fcblglr fcc3,1,3 - set_fcc 0xc 0 - fcblglr fcc0,1,0 - set_fcc 0xd 1 - fcblglr fcc1,1,1 - set_fcc 0xe 2 - fcblglr fcc2,1,2 - set_fcc 0xf 3 - fcblglr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcblglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcblglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcblglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcblglr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcblglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcblglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcblglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcblglr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcblglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcblglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcblglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcblglr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcblglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcblglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcblglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcblglr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbltlr.cgs b/sim/testsuite/sim/frv/fcbltlr.cgs deleted file mode 100644 index d15dd30..0000000 --- a/sim/testsuite/sim/frv/fcbltlr.cgs +++ /dev/null @@ -1,262 +0,0 @@ -# frv testcase for fcbltlr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbltlr -fcbltlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbltlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbltlr fcc1,0,1 - - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbltlr fcc2,0,2 - - set_spr_addr bad,lr - set_fcc 0x3 3 - fcbltlr fcc3,0,3 - - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcbltlr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbltlr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbltlr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbltlr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbltlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x9 1 - fcbltlr fcc1,0,1 - - set_spr_addr bad,lr - set_fcc 0xa 2 - fcbltlr fcc2,0,2 - - set_spr_addr bad,lr - set_fcc 0xb 3 - fcbltlr fcc3,0,3 - - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbltlr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbltlr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbltlr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbltlr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbltlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbltlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbltlr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x3 3 - fcbltlr fcc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcbltlr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbltlr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbltlr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbltlr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbltlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x9 1 - fcbltlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xa 2 - fcbltlr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xb 3 - fcbltlr fcc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbltlr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbltlr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbltlr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbltlr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbltlr fcc0,1,0 - set_fcc 0x1 1 - fcbltlr fcc1,1,1 - set_fcc 0x2 2 - fcbltlr fcc2,1,2 - set_fcc 0x3 3 - fcbltlr fcc3,1,3 - set_fcc 0x4 0 - fcbltlr fcc0,1,0 - set_fcc 0x5 1 - fcbltlr fcc1,1,1 - set_fcc 0x6 2 - fcbltlr fcc2,1,2 - set_fcc 0x7 3 - fcbltlr fcc3,1,3 - set_fcc 0x8 0 - fcbltlr fcc0,1,0 - set_fcc 0x9 1 - fcbltlr fcc1,1,1 - set_fcc 0xa 2 - fcbltlr fcc2,1,2 - set_fcc 0xb 3 - fcbltlr fcc3,1,3 - set_fcc 0xc 0 - fcbltlr fcc0,1,0 - set_fcc 0xd 1 - fcbltlr fcc1,1,1 - set_fcc 0xe 2 - fcbltlr fcc2,1,2 - set_fcc 0xf 3 - fcbltlr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbltlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbltlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbltlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbltlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbltlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbltlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbltlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbltlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbltlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbltlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbltlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbltlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbltlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbltlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbltlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbltlr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbnelr.cgs b/sim/testsuite/sim/frv/fcbnelr.cgs deleted file mode 100644 index cb0aa26..0000000 --- a/sim/testsuite/sim/frv/fcbnelr.cgs +++ /dev/null @@ -1,274 +0,0 @@ -# frv testcase for fcbnelr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbnelr -fcbnelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbnelr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbnelr fcc1,0,1 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbnelr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbnelr fcc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcbnelr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbnelr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbnelr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbnelr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbnelr fcc0,0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbnelr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbnelr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbnelr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbnelr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbnelr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbnelr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbnelr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbnelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbnelr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbnelr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbnelr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcbnelr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbnelr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbnelr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbnelr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbnelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbnelr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbnelr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbnelr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbnelr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbnelr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbnelr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbnelr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbnelr fcc0,1,0 - set_fcc 0x1 1 - fcbnelr fcc1,1,1 - set_fcc 0x2 2 - fcbnelr fcc2,1,2 - set_fcc 0x3 3 - fcbnelr fcc3,1,3 - set_fcc 0x4 0 - fcbnelr fcc0,1,0 - set_fcc 0x5 1 - fcbnelr fcc1,1,1 - set_fcc 0x6 2 - fcbnelr fcc2,1,2 - set_fcc 0x7 3 - fcbnelr fcc3,1,3 - set_fcc 0x8 0 - fcbnelr fcc0,1,0 - set_fcc 0x9 1 - fcbnelr fcc1,1,1 - set_fcc 0xa 2 - fcbnelr fcc2,1,2 - set_fcc 0xb 3 - fcbnelr fcc3,1,3 - set_fcc 0xc 0 - fcbnelr fcc0,1,0 - set_fcc 0xd 1 - fcbnelr fcc1,1,1 - set_fcc 0xe 2 - fcbnelr fcc2,1,2 - set_fcc 0xf 3 - fcbnelr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbnelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbnelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbnelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbnelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbnelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbnelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbnelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbnelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbnelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbnelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbnelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbnelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbnelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbnelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbnelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbnelr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbnolr.cgs b/sim/testsuite/sim/frv/fcbnolr.cgs deleted file mode 100644 index 3c1b73a..0000000 --- a/sim/testsuite/sim/frv/fcbnolr.cgs +++ /dev/null @@ -1,185 +0,0 @@ -# frv testcase for fcbnolr -# mach: all - - .include "testutils.inc" - - start - - .global fcbnolr -fcbnolr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - - set_fcc 0x0 0 - fcbnolr - set_fcc 0x1 1 - fcbnolr - set_fcc 0x2 2 - fcbnolr - set_fcc 0x3 3 - fcbnolr - set_fcc 0x4 0 - fcbnolr - set_fcc 0x5 1 - fcbnolr - set_fcc 0x6 2 - fcbnolr - set_fcc 0x7 3 - fcbnolr - set_fcc 0x8 0 - fcbnolr - set_fcc 0x9 1 - fcbnolr - set_fcc 0xa 2 - fcbnolr - set_fcc 0xb 3 - fcbnolr - set_fcc 0xc 0 - fcbnolr - set_fcc 0xd 1 - fcbnolr - set_fcc 0xe 2 - fcbnolr - set_fcc 0xf 3 - fcbnolr - - ; ccond is true - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbnolr - - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbnolr - set_fcc 0x1 1 - fcbnolr - set_fcc 0x2 2 - fcbnolr - set_fcc 0x3 3 - fcbnolr - set_fcc 0x4 0 - fcbnolr - set_fcc 0x5 1 - fcbnolr - set_fcc 0x6 2 - fcbnolr - set_fcc 0x7 3 - fcbnolr - set_fcc 0x8 0 - fcbnolr - set_fcc 0x9 1 - fcbnolr - set_fcc 0xa 2 - fcbnolr - set_fcc 0xb 3 - fcbnolr - set_fcc 0xc 0 - fcbnolr - set_fcc 0xd 1 - fcbnolr - set_fcc 0xe 2 - fcbnolr - set_fcc 0xf 3 - fcbnolr - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbnolr - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbolr.cgs b/sim/testsuite/sim/frv/fcbolr.cgs deleted file mode 100644 index 31909f1..0000000 --- a/sim/testsuite/sim/frv/fcbolr.cgs +++ /dev/null @@ -1,274 +0,0 @@ -# frv testcase for fcbolr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbolr -fcbolr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbolr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbolr fcc1,0,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbolr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbolr fcc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcbolr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbolr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbolr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbolr fcc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbolr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbolr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbolr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbolr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbolr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbolr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbolr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbolr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbolr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbolr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbolr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbolr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcbolr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbolr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbolr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbolr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbolr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbolr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbolr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbolr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbolr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbolr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbolr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbolr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbolr fcc0,1,0 - set_fcc 0x1 1 - fcbolr fcc1,1,1 - set_fcc 0x2 2 - fcbolr fcc2,1,2 - set_fcc 0x3 3 - fcbolr fcc3,1,3 - set_fcc 0x4 0 - fcbolr fcc0,1,0 - set_fcc 0x5 1 - fcbolr fcc1,1,1 - set_fcc 0x6 2 - fcbolr fcc2,1,2 - set_fcc 0x7 3 - fcbolr fcc3,1,3 - set_fcc 0x8 0 - fcbolr fcc0,1,0 - set_fcc 0x9 1 - fcbolr fcc1,1,1 - set_fcc 0xa 2 - fcbolr fcc2,1,2 - set_fcc 0xb 3 - fcbolr fcc3,1,3 - set_fcc 0xc 0 - fcbolr fcc0,1,0 - set_fcc 0xd 1 - fcbolr fcc1,1,1 - set_fcc 0xe 2 - fcbolr fcc2,1,2 - set_fcc 0xf 3 - fcbolr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbolr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbolr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbolr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbolr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbolr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbolr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbolr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbolr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbolr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbolr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbolr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbolr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbolr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbolr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbolr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbolr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbralr.cgs b/sim/testsuite/sim/frv/fcbralr.cgs deleted file mode 100644 index 60359d8..0000000 --- a/sim/testsuite/sim/frv/fcbralr.cgs +++ /dev/null @@ -1,276 +0,0 @@ -# frv testcase for fcbralr $ccond -# mach: all - - .include "testutils.inc" - - start - - .global fcbralr -fcbralr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_fcc 0x0 0 - fcbralr 0 - fail -ok1: - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbralr 0 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbralr 0 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbralr 0 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcbralr 0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbralr 0 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbralr 0 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbralr 0 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbralr 0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbralr 0 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbralr 0 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbralr 0 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbralr 0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbralr 0 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbralr 0 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbralr 0 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_fcc 0x0 0 - fcbralr 1 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbralr 1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbralr 1 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbralr 1 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcbralr 1 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbralr 1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbralr 1 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbralr 1 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbralr 1 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbralr 1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbralr 1 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbralr 1 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbralr 1 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbralr 1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbralr 1 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbralr 1 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbralr 1 - set_fcc 0x1 1 - fcbralr 1 - set_fcc 0x2 2 - fcbralr 1 - set_fcc 0x3 3 - fcbralr 1 - set_fcc 0x4 0 - fcbralr 1 - set_fcc 0x5 1 - fcbralr 1 - set_fcc 0x6 2 - fcbralr 1 - set_fcc 0x7 3 - fcbralr 1 - set_fcc 0x8 0 - fcbralr 1 - set_fcc 0x9 1 - fcbralr 1 - set_fcc 0xa 2 - fcbralr 1 - set_fcc 0xb 3 - fcbralr 1 - set_fcc 0xc 0 - fcbralr 1 - set_fcc 0xd 1 - fcbralr 1 - set_fcc 0xe 2 - fcbralr 1 - set_fcc 0xf 3 - fcbralr 1 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbralr 0 - - pass diff --git a/sim/testsuite/sim/frv/fcbuelr.cgs b/sim/testsuite/sim/frv/fcbuelr.cgs deleted file mode 100644 index e102ee3..0000000 --- a/sim/testsuite/sim/frv/fcbuelr.cgs +++ /dev/null @@ -1,270 +0,0 @@ -# frv testcase for fcbuelr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbuelr -fcbuelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbuelr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbuelr fcc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbuelr fcc2,0,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbuelr fcc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbuelr fcc0,0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbuelr fcc1,0,1 - fail -ok6: - set_spr_addr bad,lr - set_fcc 0x6 2 - fcbuelr fcc2,0,2 - - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbuelr fcc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbuelr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbuelr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbuelr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbuelr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbuelr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbuelr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbuelr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbuelr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbuelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbuelr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbuelr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbuelr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbuelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbuelr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x6 2 - fcbuelr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbuelr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbuelr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbuelr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbuelr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbuelr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbuelr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbuelr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbuelr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbuelr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbuelr fcc0,1,0 - set_fcc 0x1 1 - fcbuelr fcc1,1,1 - set_fcc 0x2 2 - fcbuelr fcc2,1,2 - set_fcc 0x3 3 - fcbuelr fcc3,1,3 - set_fcc 0x4 0 - fcbuelr fcc0,1,0 - set_fcc 0x5 1 - fcbuelr fcc1,1,1 - set_fcc 0x6 2 - fcbuelr fcc2,1,2 - set_fcc 0x7 3 - fcbuelr fcc3,1,3 - set_fcc 0x8 0 - fcbuelr fcc0,1,0 - set_fcc 0x9 1 - fcbuelr fcc1,1,1 - set_fcc 0xa 2 - fcbuelr fcc2,1,2 - set_fcc 0xb 3 - fcbuelr fcc3,1,3 - set_fcc 0xc 0 - fcbuelr fcc0,1,0 - set_fcc 0xd 1 - fcbuelr fcc1,1,1 - set_fcc 0xe 2 - fcbuelr fcc2,1,2 - set_fcc 0xf 3 - fcbuelr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbuelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbuelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbuelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbuelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbuelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbuelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbuelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbuelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbuelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbuelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbuelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbuelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbuelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbuelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbuelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbuelr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbugelr.cgs b/sim/testsuite/sim/frv/fcbugelr.cgs deleted file mode 100644 index 8ecd141..0000000 --- a/sim/testsuite/sim/frv/fcbugelr.cgs +++ /dev/null @@ -1,274 +0,0 @@ -# frv testcase for fcbugelr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbugelr -fcbugelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbugelr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbugelr fcc1,0,1 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbugelr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbugelr fcc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbugelr fcc0,0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbugelr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbugelr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbugelr fcc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbugelr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbugelr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbugelr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbugelr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbugelr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbugelr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbugelr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbugelr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbugelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbugelr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbugelr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbugelr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbugelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbugelr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbugelr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbugelr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbugelr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbugelr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbugelr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbugelr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbugelr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbugelr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbugelr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbugelr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbugelr fcc0,1,0 - set_fcc 0x1 1 - fcbugelr fcc1,1,1 - set_fcc 0x2 2 - fcbugelr fcc2,1,2 - set_fcc 0x3 3 - fcbugelr fcc3,1,3 - set_fcc 0x4 0 - fcbugelr fcc0,1,0 - set_fcc 0x5 1 - fcbugelr fcc1,1,1 - set_fcc 0x6 2 - fcbugelr fcc2,1,2 - set_fcc 0x7 3 - fcbugelr fcc3,1,3 - set_fcc 0x8 0 - fcbugelr fcc0,1,0 - set_fcc 0x9 1 - fcbugelr fcc1,1,1 - set_fcc 0xa 2 - fcbugelr fcc2,1,2 - set_fcc 0xb 3 - fcbugelr fcc3,1,3 - set_fcc 0xc 0 - fcbugelr fcc0,1,0 - set_fcc 0xd 1 - fcbugelr fcc1,1,1 - set_fcc 0xe 2 - fcbugelr fcc2,1,2 - set_fcc 0xf 3 - fcbugelr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbugelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbugelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbugelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbugelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbugelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbugelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbugelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbugelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbugelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbugelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbugelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbugelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbugelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbugelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbugelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbugelr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbuglr.cgs b/sim/testsuite/sim/frv/fcbuglr.cgs deleted file mode 100644 index d9470a8..0000000 --- a/sim/testsuite/sim/frv/fcbuglr.cgs +++ /dev/null @@ -1,270 +0,0 @@ -# frv testcase for fcbuglr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbuglr -fcbuglr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbuglr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbuglr fcc1,0,1 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbuglr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbuglr fcc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbuglr fcc0,0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbuglr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbuglr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbuglr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbuglr fcc0,0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbuglr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbuglr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbuglr fcc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_fcc 0xc 0 - fcbuglr fcc0,0,0 - - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbuglr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbuglr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbuglr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbuglr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbuglr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbuglr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbuglr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbuglr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbuglr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbuglr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbuglr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbuglr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbuglr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbuglr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbuglr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xc 0 - fcbuglr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbuglr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbuglr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbuglr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbuglr fcc0,1,0 - set_fcc 0x1 1 - fcbuglr fcc1,1,1 - set_fcc 0x2 2 - fcbuglr fcc2,1,2 - set_fcc 0x3 3 - fcbuglr fcc3,1,3 - set_fcc 0x4 0 - fcbuglr fcc0,1,0 - set_fcc 0x5 1 - fcbuglr fcc1,1,1 - set_fcc 0x6 2 - fcbuglr fcc2,1,2 - set_fcc 0x7 3 - fcbuglr fcc3,1,3 - set_fcc 0x8 0 - fcbuglr fcc0,1,0 - set_fcc 0x9 1 - fcbuglr fcc1,1,1 - set_fcc 0xa 2 - fcbuglr fcc2,1,2 - set_fcc 0xb 3 - fcbuglr fcc3,1,3 - set_fcc 0xc 0 - fcbuglr fcc0,1,0 - set_fcc 0xd 1 - fcbuglr fcc1,1,1 - set_fcc 0xe 2 - fcbuglr fcc2,1,2 - set_fcc 0xf 3 - fcbuglr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbuglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbuglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbuglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbuglr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbuglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbuglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbuglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbuglr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbuglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbuglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbuglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbuglr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbuglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbuglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbuglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbuglr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbulelr.cgs b/sim/testsuite/sim/frv/fcbulelr.cgs deleted file mode 100644 index 3f1da04..0000000 --- a/sim/testsuite/sim/frv/fcbulelr.cgs +++ /dev/null @@ -1,274 +0,0 @@ -# frv testcase for fcbulelr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbulelr -fcbulelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbulelr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbulelr fcc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbulelr fcc2,0,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbulelr fcc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcbulelr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbulelr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbulelr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbulelr fcc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbulelr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbulelr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbulelr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbulelr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbulelr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbulelr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbulelr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbulelr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbulelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbulelr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbulelr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbulelr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcbulelr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbulelr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbulelr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbulelr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbulelr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbulelr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbulelr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbulelr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbulelr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbulelr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbulelr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbulelr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbulelr fcc0,1,0 - set_fcc 0x1 1 - fcbulelr fcc1,1,1 - set_fcc 0x2 2 - fcbulelr fcc2,1,2 - set_fcc 0x3 3 - fcbulelr fcc3,1,3 - set_fcc 0x4 0 - fcbulelr fcc0,1,0 - set_fcc 0x5 1 - fcbulelr fcc1,1,1 - set_fcc 0x6 2 - fcbulelr fcc2,1,2 - set_fcc 0x7 3 - fcbulelr fcc3,1,3 - set_fcc 0x8 0 - fcbulelr fcc0,1,0 - set_fcc 0x9 1 - fcbulelr fcc1,1,1 - set_fcc 0xa 2 - fcbulelr fcc2,1,2 - set_fcc 0xb 3 - fcbulelr fcc3,1,3 - set_fcc 0xc 0 - fcbulelr fcc0,1,0 - set_fcc 0xd 1 - fcbulelr fcc1,1,1 - set_fcc 0xe 2 - fcbulelr fcc2,1,2 - set_fcc 0xf 3 - fcbulelr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbulelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbulelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbulelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbulelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbulelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbulelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbulelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbulelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbulelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbulelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbulelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbulelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbulelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbulelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbulelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbulelr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbullr.cgs b/sim/testsuite/sim/frv/fcbullr.cgs deleted file mode 100644 index 1a87dde..0000000 --- a/sim/testsuite/sim/frv/fcbullr.cgs +++ /dev/null @@ -1,270 +0,0 @@ -# frv testcase for fcbullr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbullr -fcbullr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbullr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbullr fcc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbullr fcc2,0,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbullr fcc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcbullr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbullr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbullr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbullr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbullr fcc0,0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbullr fcc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_fcc 0xa 2 - fcbullr fcc2,0,2 - - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbullr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbullr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbullr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbullr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbullr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbullr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbullr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbullr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbullr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcbullr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbullr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbullr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbullr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbullr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbullr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xa 2 - fcbullr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbullr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbullr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbullr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbullr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbullr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbullr fcc0,1,0 - set_fcc 0x1 1 - fcbullr fcc1,1,1 - set_fcc 0x2 2 - fcbullr fcc2,1,2 - set_fcc 0x3 3 - fcbullr fcc3,1,3 - set_fcc 0x4 0 - fcbullr fcc0,1,0 - set_fcc 0x5 1 - fcbullr fcc1,1,1 - set_fcc 0x6 2 - fcbullr fcc2,1,2 - set_fcc 0x7 3 - fcbullr fcc3,1,3 - set_fcc 0x8 0 - fcbullr fcc0,1,0 - set_fcc 0x9 1 - fcbullr fcc1,1,1 - set_fcc 0xa 2 - fcbullr fcc2,1,2 - set_fcc 0xb 3 - fcbullr fcc3,1,3 - set_fcc 0xc 0 - fcbullr fcc0,1,0 - set_fcc 0xd 1 - fcbullr fcc1,1,1 - set_fcc 0xe 2 - fcbullr fcc2,1,2 - set_fcc 0xf 3 - fcbullr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbullr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbullr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbullr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbullr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbullr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbullr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbullr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbullr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbullr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbullr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbullr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbullr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbullr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbullr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbullr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbullr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbulr.cgs b/sim/testsuite/sim/frv/fcbulr.cgs deleted file mode 100644 index c81dff3..0000000 --- a/sim/testsuite/sim/frv/fcbulr.cgs +++ /dev/null @@ -1,262 +0,0 @@ -# frv testcase for fcbulr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbulr -fcbulr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbulr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbulr fcc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbulr fcc2,0,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbulr fcc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbulr fcc0,0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbulr fcc1,0,1 - fail -ok6: - set_spr_addr bad,lr - set_fcc 0x6 2 - fcbulr fcc2,0,2 - - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbulr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbulr fcc0,0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbulr fcc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_fcc 0xa 2 - fcbulr fcc2,0,2 - - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbulr fcc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_fcc 0xc 0 - fcbulr fcc0,0,0 - - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbulr fcc1,0,1 - fail -oke: - set_spr_addr bad,lr - set_fcc 0xe 2 - fcbulr fcc2,0,2 - - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbulr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbulr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbulr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbulr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbulr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbulr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbulr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x6 2 - fcbulr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbulr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbulr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbulr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xa 2 - fcbulr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbulr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xc 0 - fcbulr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbulr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xe 2 - fcbulr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbulr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbulr fcc0,1,0 - set_fcc 0x1 1 - fcbulr fcc1,1,1 - set_fcc 0x2 2 - fcbulr fcc2,1,2 - set_fcc 0x3 3 - fcbulr fcc3,1,3 - set_fcc 0x4 0 - fcbulr fcc0,1,0 - set_fcc 0x5 1 - fcbulr fcc1,1,1 - set_fcc 0x6 2 - fcbulr fcc2,1,2 - set_fcc 0x7 3 - fcbulr fcc3,1,3 - set_fcc 0x8 0 - fcbulr fcc0,1,0 - set_fcc 0x9 1 - fcbulr fcc1,1,1 - set_fcc 0xa 2 - fcbulr fcc2,1,2 - set_fcc 0xb 3 - fcbulr fcc3,1,3 - set_fcc 0xc 0 - fcbulr fcc0,1,0 - set_fcc 0xd 1 - fcbulr fcc1,1,1 - set_fcc 0xe 2 - fcbulr fcc2,1,2 - set_fcc 0xf 3 - fcbulr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbulr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbulr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbulr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbulr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbulr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbulr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbulr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbulr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbulr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbulr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbulr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbulr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbulr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbulr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbulr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbulr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fckeq.cgs b/sim/testsuite/sim/frv/fckeq.cgs deleted file mode 100644 index 572a86d..0000000 --- a/sim/testsuite/sim/frv/fckeq.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckeq $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckeq -fckeq: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckge.cgs b/sim/testsuite/sim/frv/fckge.cgs deleted file mode 100644 index 91a1efd..0000000 --- a/sim/testsuite/sim/frv/fckge.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckge $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckge -fckge: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckge fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckge fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckge fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckge fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckgt.cgs b/sim/testsuite/sim/frv/fckgt.cgs deleted file mode 100644 index 06715f9..0000000 --- a/sim/testsuite/sim/frv/fckgt.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckgt $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckgt -fckgt: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckle.cgs b/sim/testsuite/sim/frv/fckle.cgs deleted file mode 100644 index 7d5e6da..0000000 --- a/sim/testsuite/sim/frv/fckle.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckle $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckle -fckle: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckle fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckle fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckle fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckle fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fcklg.cgs b/sim/testsuite/sim/frv/fcklg.cgs deleted file mode 100644 index f8df5a1..0000000 --- a/sim/testsuite/sim/frv/fcklg.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fcklg $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fcklg -fcklg: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fcklg fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fcklg fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fcklg fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fcklg fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fcklt.cgs b/sim/testsuite/sim/frv/fcklt.cgs deleted file mode 100644 index 14e5371..0000000 --- a/sim/testsuite/sim/frv/fcklt.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fcklt $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fcklt -fcklt: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckne.cgs b/sim/testsuite/sim/frv/fckne.cgs deleted file mode 100644 index 774f837..0000000 --- a/sim/testsuite/sim/frv/fckne.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckne $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckne -fckne: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckne fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckne fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckno.cgs b/sim/testsuite/sim/frv/fckno.cgs deleted file mode 100644 index 08513a2..0000000 --- a/sim/testsuite/sim/frv/fckno.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckno $CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckno -fckno: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - pass diff --git a/sim/testsuite/sim/frv/fcko.cgs b/sim/testsuite/sim/frv/fcko.cgs deleted file mode 100644 index 06d5640..0000000 --- a/sim/testsuite/sim/frv/fcko.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fcko $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fcko -fcko: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fcko fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fcko fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckra.cgs b/sim/testsuite/sim/frv/fckra.cgs deleted file mode 100644 index a74b9fc..0000000 --- a/sim/testsuite/sim/frv/fckra.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckra $CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckra -fckra: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fcku.cgs b/sim/testsuite/sim/frv/fcku.cgs deleted file mode 100644 index 9aaa635..0000000 --- a/sim/testsuite/sim/frv/fcku.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fcku $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fcku -fcku: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckue.cgs b/sim/testsuite/sim/frv/fckue.cgs deleted file mode 100644 index 0bd7696..0000000 --- a/sim/testsuite/sim/frv/fckue.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckue $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckue -fckue: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckue fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckue fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckue fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckue fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckug.cgs b/sim/testsuite/sim/frv/fckug.cgs deleted file mode 100644 index f810335..0000000 --- a/sim/testsuite/sim/frv/fckug.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckug $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckug -fckug: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckug fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckug fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckug fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckug fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckuge.cgs b/sim/testsuite/sim/frv/fckuge.cgs deleted file mode 100644 index d812638..0000000 --- a/sim/testsuite/sim/frv/fckuge.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckuge $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckuge -fckuge: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckuge fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckuge fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckul.cgs b/sim/testsuite/sim/frv/fckul.cgs deleted file mode 100644 index 2d30d92..0000000 --- a/sim/testsuite/sim/frv/fckul.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckul $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckul -fckul: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckul fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckul fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckul fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckul fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckule.cgs b/sim/testsuite/sim/frv/fckule.cgs deleted file mode 100644 index 9830a66..0000000 --- a/sim/testsuite/sim/frv/fckule.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckule $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckule -fckule: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckule fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckule fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fcmpd.cgs b/sim/testsuite/sim/frv/fcmpd.cgs deleted file mode 100644 index 5c86266..0000000 --- a/sim/testsuite/sim/frv/fcmpd.cgs +++ /dev/null @@ -1,601 +0,0 @@ -# frv testcase for fcmpd $GRi,$GRj,$FCCi_2 -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fcmpd -fcmpd: - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr0,fr0,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr4,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr8,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr12,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr0,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr0,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr4,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr4,fr4,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr8,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr12,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr4,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr4,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr8,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr8,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr8,fr8,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr12,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr8,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr8,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr12,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr12,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr12,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr12,fr12,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr12,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr12,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr16,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr16,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr16,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr16,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr16,fr16,fcc0 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr16,fr20,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr16,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr16,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr20,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr20,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr20,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr20,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr20,fr16,fcc0 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr20,fr20,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr20,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr20,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr24,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr24,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr24,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr24,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr24,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr24,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr24,fr24,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr24,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr24,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr24,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr28,fr28,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr28,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr28,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr28,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr28,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr28,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr28,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr28,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr28,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr24,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr28,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr32,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr36,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr40,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr44,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr48,fr48,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr48,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr48,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr48,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr24,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr28,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr32,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr36,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr40,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr44,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr48,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr52,fr52,fcc0 - test_fcc 0x8,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr52,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr52,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr0,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr4,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr8,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr12,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr16,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr20,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr24,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr28,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr32,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr36,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr40,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr44,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr48,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr52,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr0,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr4,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr8,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr12,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr16,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr20,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr24,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr28,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr32,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr36,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr40,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr44,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr48,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr52,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr60,fcc0 - test_fcc 0x1,0 - - pass diff --git a/sim/testsuite/sim/frv/fcmps.cgs b/sim/testsuite/sim/frv/fcmps.cgs deleted file mode 100644 index ea1ccc0..0000000 --- a/sim/testsuite/sim/frv/fcmps.cgs +++ /dev/null @@ -1,600 +0,0 @@ -# frv testcase for fcmps $GRi,$GRj,$FCCi_2 -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fcmps -fcmps: - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr0,fr0,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr4,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr8,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr12,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr0,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr0,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr4,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr4,fr4,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr8,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr12,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr4,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr4,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr8,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr8,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr8,fr8,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr12,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr8,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr8,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr12,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr12,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr12,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr12,fr12,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr12,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr12,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr16,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr16,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr16,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr16,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr16,fr16,fcc0 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr16,fr20,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr16,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr16,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr20,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr20,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr20,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr20,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr20,fr16,fcc0 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr20,fr20,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr20,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr20,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr24,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr24,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr24,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr24,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr24,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr24,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr24,fr24,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr24,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr24,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr24,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr28,fr28,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr28,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr28,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr28,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr28,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr28,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr28,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr28,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr28,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr24,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr28,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr32,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr36,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr40,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr44,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr48,fr48,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr48,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr48,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr48,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr24,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr28,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr32,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr36,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr40,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr44,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr48,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr52,fr52,fcc0 - test_fcc 0x8,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr52,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr52,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr0,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr4,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr8,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr12,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr16,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr20,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr24,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr28,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr32,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr36,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr40,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr44,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr48,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr52,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr0,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr4,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr8,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr12,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr16,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr20,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr24,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr28,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr32,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr36,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr40,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr44,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr48,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr52,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr60,fcc0 - test_fcc 0x1,0 - - pass diff --git a/sim/testsuite/sim/frv/fdabss.cgs b/sim/testsuite/sim/frv/fdabss.cgs deleted file mode 100644 index 83d3e1c..0000000 --- a/sim/testsuite/sim/frv/fdabss.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for fdabss $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fdabss -fdabss: - set_fr_fr fr8,fr1 - fdabss fr0,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr28 - set_fr_fr fr24,fr13 - fdabss fr12,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - set_fr_fr fr52,fr29 - fdabss fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr52 - - pass diff --git a/sim/testsuite/sim/frv/fdadds.cgs b/sim/testsuite/sim/frv/fdadds.cgs deleted file mode 100644 index ecfa56c..0000000 --- a/sim/testsuite/sim/frv/fdadds.cgs +++ /dev/null @@ -1,134 +0,0 @@ -# frv testcase for fdadds $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdadds -fdadds: - fdadds fr16,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fdadds fr16,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fdadds fr16,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdadds fr16,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fdadds fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr16,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fdadds fr16,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fdadds fr16,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdadds fr16,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fdadds fr16,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fdadds fr16,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fdadds fr16,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fdadds fr16,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fdadds fr20,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fdadds fr20,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fdadds fr20,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdadds fr20,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fdadds fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr20,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fdadds fr20,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fdadds fr20,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdadds fr20,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fdadds fr20,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fdadds fr20,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fdadds fr20,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fdadds fr20,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fdadds fr8,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr12,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr24,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr28,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fdadds fr36,fr40,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - - pass - - diff --git a/sim/testsuite/sim/frv/fdcmps.cgs b/sim/testsuite/sim/frv/fdcmps.cgs deleted file mode 100644 index 397832c..0000000 --- a/sim/testsuite/sim/frv/fdcmps.cgs +++ /dev/null @@ -1,985 +0,0 @@ -# frv testcase for fdcmps $FRi,$FRj,$FCCi_2 -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdcmps -fdcmps: - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr0,fr0,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr4,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr8,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr12,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr0,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr0,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr4,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr4,fr4,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr8,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr12,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr4,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr4,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr8,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr8,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr8,fr8,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr12,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr8,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr8,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr12,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr12,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr12,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr12,fr12,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr12,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr12,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr16,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr16,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr16,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr16,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr16,fr16,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr16,fr20,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr16,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr16,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr20,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr20,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr20,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr20,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr20,fr16,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr20,fr20,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr20,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr20,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr24,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr24,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr24,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr24,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr24,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr24,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr24,fr24,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr24,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr24,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr24,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr28,fr28,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr28,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr28,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr28,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr28,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr28,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr28,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr28,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr28,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr24,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr28,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr32,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr36,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr40,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr44,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr48,fr48,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr48,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr48,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr48,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr24,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr28,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr32,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr36,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr40,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr44,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr48,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr52,fr52,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr52,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr52,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr0,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr4,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr8,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr12,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr16,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr20,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr24,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr28,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr32,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr36,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr40,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr44,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr48,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr52,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr0,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr4,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr8,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr12,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr16,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr20,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr24,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr28,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr32,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr36,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr40,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr44,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr48,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr52,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - pass diff --git a/sim/testsuite/sim/frv/fddivs.cgs b/sim/testsuite/sim/frv/fddivs.cgs deleted file mode 100644 index ac423b2..0000000 --- a/sim/testsuite/sim/frv/fddivs.cgs +++ /dev/null @@ -1,195 +0,0 @@ -# frv testcase for fddivs $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fddivs -fddivs: - fddivs fr0,fr28,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fddivs fr4,fr28,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fddivs fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fddivs fr12,fr28,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fddivs fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr24,fr28,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fddivs fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fddivs fr32,fr28,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fddivs fr36,fr28,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fddivs fr40,fr28,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fddivs fr44,fr28,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fddivs fr48,fr28,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fddivs fr52,fr28,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fddivs fr16,fr0,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr52,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fddivs fr20,fr0,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr52,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fddivs fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fddivs fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - - fddivs fr40,fr32,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - - pass - - diff --git a/sim/testsuite/sim/frv/fditos.cgs b/sim/testsuite/sim/frv/fditos.cgs deleted file mode 100644 index 412e8af..0000000 --- a/sim/testsuite/sim/frv/fditos.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for fditos $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fditos -fditos: - set_fr_iimmed 0,0,fr2 - set_fr_iimmed 0x0000,0x0002,fr3 - fditos fr2,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - - set_fr_iimmed 0xdead,0xbeef,fr2 - set_fr_iimmed 0xdead,0xbeef,fr3 - fditos fr2,fr2 - test_fr_iimmed 0xce054904,fr2 - test_fr_iimmed 0xce054904,fr3 - - pass diff --git a/sim/testsuite/sim/frv/fdivd.cgs b/sim/testsuite/sim/frv/fdivd.cgs deleted file mode 100644 index 65222bb..0000000 --- a/sim/testsuite/sim/frv/fdivd.cgs +++ /dev/null @@ -1,128 +0,0 @@ -# frv testcase for fdivd $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fdivd -fdivd: - fdivd fr0,fr28,fr2 - test_dfr_dfr fr2,fr0 - fdivd fr4,fr28,fr2 - test_dfr_dfr fr2,fr4 - fdivd fr8,fr28,fr2 - test_dfr_dfr fr2,fr8 - fdivd fr12,fr28,fr2 - test_dfr_dfr fr2,fr12 - fdivd fr16,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr24,fr28,fr2 - test_dfr_dfr fr2,fr24 - fdivd fr28,fr28,fr2 - test_dfr_dfr fr2,fr28 - fdivd fr32,fr28,fr2 - test_dfr_dfr fr2,fr32 - fdivd fr36,fr28,fr2 - test_dfr_dfr fr2,fr36 - fdivd fr40,fr28,fr2 - test_dfr_dfr fr2,fr40 - fdivd fr44,fr28,fr2 - test_dfr_dfr fr2,fr44 - fdivd fr48,fr28,fr2 - test_dfr_dfr fr2,fr48 - fdivd fr52,fr28,fr2 - test_dfr_dfr fr2,fr52 - - fdivd fr16,fr0,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr52,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - fdivd fr20,fr0,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr52,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - fdivd fr8,fr28,fr2 - test_dfr_dfr fr2,fr8 - fdivd fr28,fr8,fr2 - test_dfr_dfr fr2,fr8 - - fdivd fr40,fr32,fr2 - test_dfr_dfr fr2,fr36 - - pass - - diff --git a/sim/testsuite/sim/frv/fdivs.cgs b/sim/testsuite/sim/frv/fdivs.cgs deleted file mode 100644 index cf2bd4b..0000000 --- a/sim/testsuite/sim/frv/fdivs.cgs +++ /dev/null @@ -1,127 +0,0 @@ -# frv testcase for fdivs $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fdivs -fdivs: - fdivs fr0,fr28,fr1 - test_fr_fr fr1,fr0 - fdivs fr4,fr28,fr1 - test_fr_fr fr1,fr4 - fdivs fr8,fr28,fr1 - test_fr_fr fr1,fr8 - fdivs fr12,fr28,fr1 - test_fr_fr fr1,fr12 - fdivs fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr24,fr28,fr1 - test_fr_fr fr1,fr24 - fdivs fr28,fr28,fr1 - test_fr_fr fr1,fr28 - fdivs fr32,fr28,fr1 - test_fr_fr fr1,fr32 - fdivs fr36,fr28,fr1 - test_fr_fr fr1,fr36 - fdivs fr40,fr28,fr1 - test_fr_fr fr1,fr40 - fdivs fr44,fr28,fr1 - test_fr_fr fr1,fr44 - fdivs fr48,fr28,fr1 - test_fr_fr fr1,fr48 - fdivs fr52,fr28,fr1 - test_fr_fr fr1,fr52 - - fdivs fr16,fr0,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr52,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fdivs fr20,fr0,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr52,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fdivs fr8,fr28,fr1 - test_fr_fr fr1,fr8 - fdivs fr28,fr8,fr1 - test_fr_fr fr1,fr8 - - fdivs fr40,fr32,fr1 - test_fr_fr fr1,fr36 - - pass - - diff --git a/sim/testsuite/sim/frv/fdmadds.cgs b/sim/testsuite/sim/frv/fdmadds.cgs deleted file mode 100644 index 7035366..0000000 --- a/sim/testsuite/sim/frv/fdmadds.cgs +++ /dev/null @@ -1,226 +0,0 @@ -# frv testcase for fdmadds $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdmadds -fdmadds: - fdmadds fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fdmadds fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - set_fr_fr fr36,fr2 - set_fr_fr fr36,fr3 - fdmadds fr28,fr8,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdmadds fr8,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - - set_fr_fr fr36,fr2 - set_fr_fr fr36,fr3 - fdmadds fr32,fr36,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - - pass diff --git a/sim/testsuite/sim/frv/fdmas.cgs b/sim/testsuite/sim/frv/fdmas.cgs deleted file mode 100644 index a7162db..0000000 --- a/sim/testsuite/sim/frv/fdmas.cgs +++ /dev/null @@ -1,265 +0,0 @@ -# frv testcase for fdmas $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - load_float_constants2 - load_float_constants3 - - .global fdmas -fdmas: - fdmas fr16,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr4 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr4 - fdmas fr16,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - fdmas fr16,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr12 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr12 - fdmas fr16,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmas fr16,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmas fr16,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr24 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr24 - fdmas fr16,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - fdmas fr16,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr32 - fdmas fr16,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr36 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr36 - fdmas fr16,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr40 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr40 - fdmas fr16,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr44 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr44 - fdmas fr16,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr48 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr48 - - fdmas fr20,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr4 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr4 - fdmas fr20,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - fdmas fr20,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr12 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr12 - fdmas fr20,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmas fr20,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmas fr20,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr24 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr24 - fdmas fr20,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - fdmas fr20,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr32 - fdmas fr20,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr36 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr36 - fdmas fr20,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr40 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr40 - fdmas fr20,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr44 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr44 - fdmas fr20,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr48 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr48 - - fdmas fr28,fr0,fr60 - test_fr_fr fr60,fr0 - test_fr_fr fr62,fr0 - fdmas fr28,fr4,fr60 - test_fr_fr fr60,fr4 - test_fr_fr fr62,fr4 - fdmas fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmas fr28,fr12,fr60 - test_fr_fr fr60,fr12 - test_fr_fr fr62,fr12 - fdmas fr28,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmas fr28,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmas fr28,fr24,fr60 - test_fr_fr fr60,fr24 - test_fr_fr fr62,fr24 - fdmas fr28,fr28,fr60 - test_fr_fr fr60,fr28 - test_fr_fr fr62,fr28 - fdmas fr28,fr32,fr60 - test_fr_fr fr60,fr32 - test_fr_fr fr61,fr36 - test_fr_fr fr62,fr32 - test_fr_fr fr63,fr36 - fdmas fr28,fr36,fr60 - test_fr_fr fr60,fr36 - test_fr_fr fr62,fr36 - fdmas fr28,fr40,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr62,fr40 - fdmas fr28,fr44,fr60 - test_fr_fr fr60,fr44 - test_fr_fr fr62,fr44 - fdmas fr28,fr48,fr60 - test_fr_fr fr60,fr48 - test_fr_fr fr62,fr48 - fdmas fr28,fr52,fr60 - test_fr_fr fr60,fr52 - test_fr_fr fr62,fr52 - - fdmas fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmas fr8,fr28,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - - fdmas fr32,fr36,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr62,fr40 - - pass diff --git a/sim/testsuite/sim/frv/fdmovs.cgs b/sim/testsuite/sim/frv/fdmovs.cgs deleted file mode 100644 index 58e9607..0000000 --- a/sim/testsuite/sim/frv/fdmovs.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for fdmovs $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fdmovs -fdmovs: - set_fr_fr fr4,fr1 - fdmovs fr0,fr2 - test_fr_fr fr0,fr2 - test_fr_fr fr4,fr3 - set_fr_fr fr12,fr9 - fdmovs fr8,fr2 - test_fr_fr fr8,fr2 - test_fr_fr fr12,fr3 - set_fr_fr fr20,fr17 - fdmovs fr16,fr2 - test_fr_fr fr16,fr2 - test_fr_fr fr20,fr3 - set_fr_fr fr28,fr25 - fdmovs fr24,fr2 - test_fr_fr fr24,fr2 - test_fr_fr fr28,fr3 - set_fr_fr fr36,fr33 - fdmovs fr32,fr2 - test_fr_fr fr32,fr2 - test_fr_fr fr36,fr3 - set_fr_fr fr44,fr41 - fdmovs fr40,fr2 - test_fr_fr fr40,fr2 - test_fr_fr fr44,fr3 - set_fr_fr fr52,fr49 - fdmovs fr48,fr2 - test_fr_fr fr48,fr2 - test_fr_fr fr52,fr3 - set_fr_fr fr60,fr57 - fdmovs fr56,fr2 - test_fr_iimmed 0x7fc00000,fr2 - test_fr_iimmed 0x7f800001,fr3 - - pass diff --git a/sim/testsuite/sim/frv/fdmss.cgs b/sim/testsuite/sim/frv/fdmss.cgs deleted file mode 100644 index 5457a1e..0000000 --- a/sim/testsuite/sim/frv/fdmss.cgs +++ /dev/null @@ -1,235 +0,0 @@ -# frv testcase for fdmss $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - load_float_constants2 - load_float_constants3 - - .global fdmss -fdmss: - fdmss fr16,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - fdmss fr16,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmss fr16,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmss fr16,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - fdmss fr16,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - - fdmss fr20,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - fdmss fr20,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmss fr20,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmss fr20,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - fdmss fr20,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - - fdmss fr28,fr0,fr60 - test_fr_fr fr60,fr0 - test_fr_fr fr62,fr0 - fdmss fr28,fr4,fr60 - test_fr_fr fr60,fr4 - test_fr_fr fr62,fr4 - fdmss fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr32 - fdmss fr28,fr12,fr60 - test_fr_fr fr60,fr12 - test_fr_fr fr62,fr12 - fdmss fr28,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - fdmss fr28,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - fdmss fr28,fr24,fr60 - test_fr_fr fr60,fr24 - test_fr_fr fr62,fr24 - fdmss fr28,fr28,fr60 - test_fr_fr fr60,fr28 - test_fr_fr fr61,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr62,fr28 - test_fr_fr fr63,fr20 - test_fr_fr fr63,fr16 - fdmss fr28,fr32,fr60 - test_fr_fr fr60,fr32 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr32 - test_fr_fr fr63,fr8 - fdmss fr28,fr36,fr60 - test_fr_fr fr60,fr36 - test_fr_fr fr62,fr36 - fdmss fr28,fr40,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr62,fr40 - fdmss fr28,fr44,fr60 - test_fr_fr fr60,fr44 - test_fr_fr fr62,fr44 - fdmss fr28,fr48,fr60 - test_fr_fr fr60,fr48 - test_fr_fr fr62,fr48 - fdmss fr28,fr52,fr60 - test_fr_fr fr60,fr52 - test_fr_fr fr62,fr52 - - fdmss fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr32 - fdmss fr8,fr28,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr62,fr8 - - fdmss fr32,fr36,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr40 - test_fr_fr fr63,fr8 - - pass diff --git a/sim/testsuite/sim/frv/fdmulcs.cgs b/sim/testsuite/sim/frv/fdmulcs.cgs deleted file mode 100644 index a7cb159..0000000 --- a/sim/testsuite/sim/frv/fdmulcs.cgs +++ /dev/null @@ -1,201 +0,0 @@ -# frv testcase for fdmulcs $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdmulcs -fdmulcs: - fdmulcs fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fdmulcs fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr2,fr20 - fdmulcs fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fdmulcs fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fdmulcs fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fdmulcs fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdmulcs fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fdmulcs fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fdmulcs fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fdmulcs fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdmulcs fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fdmulcs fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fdmulcs fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fdmulcs fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fdmulcs fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fdmulcs fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdmulcs fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - - fdmulcs fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - - set_fr_fr fr32,fr50 ; 2 - set_fr_fr fr28,fr51 ; 1 - set_fr_fr fr44,fr52 ; 9 - set_fr_fr fr36,fr53 ; 3 - fdmulcs fr50,fr52,fr54 ; 2*3, 1*9 - test_fr_fr fr54,fr40 ; 6 - test_fr_fr fr55,fr44 ; 9 - - pass diff --git a/sim/testsuite/sim/frv/fdmuls.cgs b/sim/testsuite/sim/frv/fdmuls.cgs deleted file mode 100644 index 2c2c05a..0000000 --- a/sim/testsuite/sim/frv/fdmuls.cgs +++ /dev/null @@ -1,193 +0,0 @@ -# frv testcase for fdmuls $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdmuls -fdmuls: - fdmuls fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fdmuls fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr2,fr20 - fdmuls fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fdmuls fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fdmuls fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fdmuls fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdmuls fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fdmuls fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fdmuls fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fdmuls fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdmuls fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fdmuls fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fdmuls fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fdmuls fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fdmuls fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fdmuls fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdmuls fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - - fdmuls fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - - pass diff --git a/sim/testsuite/sim/frv/fdnegs.cgs b/sim/testsuite/sim/frv/fdnegs.cgs deleted file mode 100644 index db409cb..0000000 --- a/sim/testsuite/sim/frv/fdnegs.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for fdnegs $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fdnegs -fdnegs: - set_fr_fr fr8,fr1 - fdnegs fr0,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr28 - set_fr_fr fr24,fr13 - fdnegs fr12,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr12 - set_fr_fr fr52,fr29 - fdnegs fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr0 - - pass diff --git a/sim/testsuite/sim/frv/fdsads.cgs b/sim/testsuite/sim/frv/fdsads.cgs deleted file mode 100644 index 123810d..0000000 --- a/sim/testsuite/sim/frv/fdsads.cgs +++ /dev/null @@ -1,119 +0,0 @@ -# frv testcase for fdsads $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdsads -fdsads: - fdsads fr16,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr52 - fdsads fr16,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr48 - fdsads fr16,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr28 - fdsads fr16,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr24 - fdsads fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsads fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsads fr16,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr12 - fdsads fr16,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr8 - fdsads fr16,fr32,fr2 - test_fr_fr fr2,fr32 - fdsads fr16,fr36,fr2 - test_fr_fr fr2,fr36 - fdsads fr16,fr40,fr2 - test_fr_fr fr2,fr40 - fdsads fr16,fr44,fr2 - test_fr_fr fr2,fr44 - fdsads fr16,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr4 - fdsads fr16,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr0 - - fdsads fr20,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr52 - fdsads fr20,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr48 - fdsads fr20,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr28 - fdsads fr20,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr24 - fdsads fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsads fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsads fr20,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr12 - fdsads fr20,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr8 - fdsads fr20,fr32,fr2 - test_fr_fr fr2,fr32 - fdsads fr20,fr36,fr2 - test_fr_fr fr2,fr36 - fdsads fr20,fr40,fr2 - test_fr_fr fr2,fr40 - fdsads fr20,fr44,fr2 - test_fr_fr fr2,fr44 - fdsads fr20,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr4 - fdsads fr20,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr0 - - fdsads fr8,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fdsads fr12,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fdsads fr24,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fdsads fr28,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - test_fr_fr fr3,fr32 - - fdsads fr36,fr40,fr2 - test_fr_fr fr2,fr44 - - pass - - diff --git a/sim/testsuite/sim/frv/fdsqrts.cgs b/sim/testsuite/sim/frv/fdsqrts.cgs deleted file mode 100644 index 6026b93..0000000 --- a/sim/testsuite/sim/frv/fdsqrts.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# frv testcase for fdsqrts $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fdsqrts -fdsqrts: - set_fr_iimmed 0x4049,0x0fdb,fr45 ; 3.141592654 - fdsqrts fr44,fr2 ; 9.0 - test_fr_fr fr2,fr36 ; 3.0 - test_fr_iimmed 0x3fe2dfc5,fr3 ; 1.7724539 - - pass diff --git a/sim/testsuite/sim/frv/fdstoi.cgs b/sim/testsuite/sim/frv/fdstoi.cgs deleted file mode 100644 index 5c79e49..0000000 --- a/sim/testsuite/sim/frv/fdstoi.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for fdstoi $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fdstoi -fdstoi: - set_fr_fr fr20,fr17 - fdstoi fr16,fr2 - test_fr_iimmed 0,fr2 - test_fr_iimmed 0,fr3 - - set_fr_iimmed 0xce05,0x4904,fr2 - set_fr_fr fr32,fr3 - fdstoi fr2,fr2 - test_fr_iimmed 0xdeadbf00,fr2 - test_fr_iimmed 0x00000002,fr3 - - pass diff --git a/sim/testsuite/sim/frv/fdsubs.cgs b/sim/testsuite/sim/frv/fdsubs.cgs deleted file mode 100644 index 93dae46..0000000 --- a/sim/testsuite/sim/frv/fdsubs.cgs +++ /dev/null @@ -1,117 +0,0 @@ -# frv testcase for fdsubs $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdsubs -fdsubs: - fdsubs fr0,fr16,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fdsubs fr4,fr16,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fdsubs fr8,fr16,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdsubs fr12,fr16,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fdsubs fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsubs fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsubs fr24,fr16,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fdsubs fr28,fr16,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fdsubs fr32,fr16,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdsubs fr36,fr16,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fdsubs fr40,fr16,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fdsubs fr44,fr16,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fdsubs fr48,fr16,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fdsubs fr52,fr16,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fdsubs fr0,fr20,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fdsubs fr4,fr20,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fdsubs fr8,fr20,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdsubs fr12,fr20,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fdsubs fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsubs fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsubs fr24,fr20,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fdsubs fr28,fr20,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fdsubs fr32,fr20,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdsubs fr36,fr20,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fdsubs fr40,fr20,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fdsubs fr44,fr20,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fdsubs fr48,fr20,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fdsubs fr52,fr20,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fdsubs fr32,fr36,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - - fdsubs fr44,fr40,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - - pass - - diff --git a/sim/testsuite/sim/frv/fdtoi.cgs b/sim/testsuite/sim/frv/fdtoi.cgs deleted file mode 100644 index 1749852..0000000 --- a/sim/testsuite/sim/frv/fdtoi.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# frv testcase for fdtoi $FRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global fdtoi -fdtoi: - set_fr_iimmed 0,0,fr2 - set_fr_iimmed 0,0,fr3 - fdtoi fr2,fr2 - test_fr_iimmed 0,fr2 - - set_fr_iimmed 0x4000,0x0000,fr2 - set_fr_iimmed 0x0000,0x0000,fr3 - fdtoi fr2,fr2 - test_fr_iimmed 0x00000002,fr2 - - set_fr_iimmed 0xc1c0,0xa920,fr2 - set_fr_iimmed 0x8880,0x0000,fr3 - fdtoi fr2,fr2 - test_fr_iimmed 0xdeadbeef,fr2 - - set_gr_limmed 0x4031,0x0000,gr8 - set_gr_limmed 0x0000,0x0000,gr9 - movgfd gr8,fr0 - fdtoi fr0,fr0 - test_fr_iimmed 17,fr0 - - pass diff --git a/sim/testsuite/sim/frv/fitod.cgs b/sim/testsuite/sim/frv/fitod.cgs deleted file mode 100644 index 62ef1f2..0000000 --- a/sim/testsuite/sim/frv/fitod.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for fitod $FRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global fitod -fitod: - set_fr_iimmed 0,0,fr2 - fitod fr2,fr2 - test_fr_iimmed 0,fr2 - test_fr_iimmed 0,fr3 - - set_fr_iimmed 0x0000,0x0002,fr2 - fitod fr2,fr2 - test_fr_iimmed 0x40000000,fr2 - test_fr_iimmed 0x00000000,fr3 - - set_fr_iimmed 0xdead,0xbeef,fr2 - fitod fr2,fr2 - test_fr_iimmed 0xc1c0a920,fr2 - test_fr_iimmed 0x88800000,fr3 - - pass diff --git a/sim/testsuite/sim/frv/fitos.cgs b/sim/testsuite/sim/frv/fitos.cgs deleted file mode 100644 index 2afe290..0000000 --- a/sim/testsuite/sim/frv/fitos.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for fitos $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fitos -fitos: - set_fr_iimmed 0,0,fr1 - fitos fr1,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_iimmed 0x0000,0x0002,fr1 - fitos fr1,fr1 - test_fr_fr fr1,fr32 - - set_fr_iimmed 0xdead,0xbeef,fr1 - fitos fr1,fr1 - test_fr_iimmed 0xce054904,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fmad.cgs b/sim/testsuite/sim/frv/fmad.cgs deleted file mode 100644 index 64fee9c..0000000 --- a/sim/testsuite/sim/frv/fmad.cgs +++ /dev/null @@ -1,161 +0,0 @@ -# frv testcase for fmad $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fmad -fmad: - fmad fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - fmad fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmad fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - fmad fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmad fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmad fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - fmad fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmad fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - fmad fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - fmad fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - fmad fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - fmad fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - fmad fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - fmad fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmad fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - fmad fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmad fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmad fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - fmad fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmad fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - fmad fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - fmad fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - fmad fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - fmad fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - fmad fr28,fr0,fr2 - test_fr_fr fr2,fr0 - fmad fr28,fr4,fr2 - test_fr_fr fr2,fr4 - fmad fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmad fr28,fr12,fr2 - test_fr_fr fr2,fr12 - fmad fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmad fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmad fr28,fr24,fr2 - test_fr_fr fr2,fr24 - fmad fr28,fr28,fr2 - test_fr_fr fr2,fr28 - fmad fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr36 - fmad fr28,fr36,fr2 - test_fr_fr fr2,fr36 - fmad fr28,fr40,fr2 - test_fr_fr fr2,fr40 - fmad fr28,fr44,fr2 - test_fr_fr fr2,fr44 - fmad fr28,fr48,fr2 - test_fr_fr fr2,fr48 - fmad fr28,fr52,fr2 - test_fr_fr fr2,fr52 - - fmad fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmad fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fmad fr32,fr36,fr2 - test_fr_fr fr2,fr40 - - pass diff --git a/sim/testsuite/sim/frv/fmaddd.cgs b/sim/testsuite/sim/frv/fmaddd.cgs deleted file mode 100644 index bfa816f..0000000 --- a/sim/testsuite/sim/frv/fmaddd.cgs +++ /dev/null @@ -1,143 +0,0 @@ -# frv testcase for fmaddd $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fmaddd -fmaddd: - set_dfr_dfr fr16,fr2 - fmaddd fr16,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - fmaddd fr20,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr0,fr2 - test_dfr_dfr fr2,fr0 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr4,fr2 - test_dfr_dfr fr2,fr4 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr8,fr2 - test_dfr_dfr fr2,fr8 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr12,fr2 - test_dfr_dfr fr2,fr12 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr24,fr2 - test_dfr_dfr fr2,fr24 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr28,fr2 - test_dfr_dfr fr2,fr28 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr32,fr2 - test_dfr_dfr fr2,fr32 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr36,fr2 - test_dfr_dfr fr2,fr36 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr40,fr2 - test_dfr_dfr fr2,fr40 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr44,fr2 - test_dfr_dfr fr2,fr44 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr48,fr2 - test_dfr_dfr fr2,fr48 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr52,fr2 - test_dfr_dfr fr2,fr52 - - set_dfr_dfr fr36,fr2 - fmaddd fr28,fr8,fr2 - test_dfr_dfr fr2,fr32 - fmaddd fr8,fr28,fr2 - test_dfr_dfr fr2,fr28 - - set_dfr_dfr fr36,fr2 - fmaddd fr32,fr36,fr2 - test_dfr_dfr fr2,fr44 - - pass diff --git a/sim/testsuite/sim/frv/fmadds.cgs b/sim/testsuite/sim/frv/fmadds.cgs deleted file mode 100644 index 128c82a..0000000 --- a/sim/testsuite/sim/frv/fmadds.cgs +++ /dev/null @@ -1,143 +0,0 @@ -# frv testcase for fmadds $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fmadds -fmadds: - set_fr_fr fr16,fr1 - fmadds fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fmadds fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_fr fr16,fr1 - fmadds fr28,fr0,fr1 - test_fr_fr fr1,fr0 - set_fr_fr fr16,fr1 - fmadds fr28,fr4,fr1 - test_fr_fr fr1,fr4 - set_fr_fr fr16,fr1 - fmadds fr28,fr8,fr1 - test_fr_fr fr1,fr8 - set_fr_fr fr16,fr1 - fmadds fr28,fr12,fr1 - test_fr_fr fr1,fr12 - set_fr_fr fr16,fr1 - fmadds fr28,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - fmadds fr28,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - fmadds fr28,fr24,fr1 - test_fr_fr fr1,fr24 - set_fr_fr fr16,fr1 - fmadds fr28,fr28,fr1 - test_fr_fr fr1,fr28 - set_fr_fr fr16,fr1 - fmadds fr28,fr32,fr1 - test_fr_fr fr1,fr32 - set_fr_fr fr16,fr1 - fmadds fr28,fr36,fr1 - test_fr_fr fr1,fr36 - set_fr_fr fr16,fr1 - fmadds fr28,fr40,fr1 - test_fr_fr fr1,fr40 - set_fr_fr fr16,fr1 - fmadds fr28,fr44,fr1 - test_fr_fr fr1,fr44 - set_fr_fr fr16,fr1 - fmadds fr28,fr48,fr1 - test_fr_fr fr1,fr48 - set_fr_fr fr16,fr1 - fmadds fr28,fr52,fr1 - test_fr_fr fr1,fr52 - - set_fr_fr fr36,fr1 - fmadds fr28,fr8,fr1 - test_fr_fr fr1,fr32 - fmadds fr8,fr28,fr1 - test_fr_fr fr1,fr28 - - set_fr_fr fr36,fr1 - fmadds fr32,fr36,fr1 - test_fr_fr fr1,fr44 - - pass diff --git a/sim/testsuite/sim/frv/fmas.cgs b/sim/testsuite/sim/frv/fmas.cgs deleted file mode 100644 index 1e7b1df..0000000 --- a/sim/testsuite/sim/frv/fmas.cgs +++ /dev/null @@ -1,161 +0,0 @@ -# frv testcase for fmas $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fmas -fmas: - fmas fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - fmas fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmas fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - fmas fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmas fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmas fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - fmas fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmas fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - fmas fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - fmas fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - fmas fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - fmas fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - fmas fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - fmas fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmas fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - fmas fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmas fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmas fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - fmas fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmas fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - fmas fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - fmas fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - fmas fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - fmas fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - fmas fr28,fr0,fr2 - test_fr_fr fr2,fr0 - fmas fr28,fr4,fr2 - test_fr_fr fr2,fr4 - fmas fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmas fr28,fr12,fr2 - test_fr_fr fr2,fr12 - fmas fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmas fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmas fr28,fr24,fr2 - test_fr_fr fr2,fr24 - fmas fr28,fr28,fr2 - test_fr_fr fr2,fr28 - fmas fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr36 - fmas fr28,fr36,fr2 - test_fr_fr fr2,fr36 - fmas fr28,fr40,fr2 - test_fr_fr fr2,fr40 - fmas fr28,fr44,fr2 - test_fr_fr fr2,fr44 - fmas fr28,fr48,fr2 - test_fr_fr fr2,fr48 - fmas fr28,fr52,fr2 - test_fr_fr fr2,fr52 - - fmas fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmas fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fmas fr32,fr36,fr2 - test_fr_fr fr2,fr40 - - pass diff --git a/sim/testsuite/sim/frv/fmovd.cgs b/sim/testsuite/sim/frv/fmovd.cgs deleted file mode 100644 index 938faa2..0000000 --- a/sim/testsuite/sim/frv/fmovd.cgs +++ /dev/null @@ -1,48 +0,0 @@ -# frv testcase for fmovd $FRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fmovd -fmovd: - fmovd fr0,fr2 - test_dfr_dfr fr0,fr2 - fmovd fr4,fr2 - test_dfr_dfr fr4,fr2 - fmovd fr8,fr2 - test_dfr_dfr fr8,fr2 - fmovd fr12,fr2 - test_dfr_dfr fr12,fr2 - fmovd fr16,fr2 - test_dfr_dfr fr16,fr2 - fmovd fr20,fr2 - test_dfr_dfr fr20,fr2 - fmovd fr24,fr2 - test_dfr_dfr fr24,fr2 - fmovd fr28,fr2 - test_dfr_dfr fr28,fr2 - fmovd fr32,fr2 - test_dfr_dfr fr32,fr2 - fmovd fr36,fr2 - test_dfr_dfr fr36,fr2 - fmovd fr40,fr2 - test_dfr_dfr fr40,fr2 - fmovd fr44,fr2 - test_dfr_dfr fr44,fr2 - fmovd fr48,fr2 - test_dfr_dfr fr48,fr2 - fmovd fr52,fr2 - test_dfr_dfr fr52,fr2 - fmovd fr56,fr2 - test_fr_iimmed 0x7ff80000,fr2 - test_fr_iimmed 0x00000000,fr3 - fmovd fr60,fr2 - test_fr_iimmed 0x7ff00000,fr2 - test_fr_iimmed 0x00000001,fr3 - - pass diff --git a/sim/testsuite/sim/frv/fmovs.cgs b/sim/testsuite/sim/frv/fmovs.cgs deleted file mode 100644 index 2a70277..0000000 --- a/sim/testsuite/sim/frv/fmovs.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for fmovs $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fmovs -fmovs: - fmovs fr0,fr1 - test_fr_fr fr0,fr1 - fmovs fr4,fr1 - test_fr_fr fr4,fr1 - fmovs fr8,fr1 - test_fr_fr fr8,fr1 - fmovs fr12,fr1 - test_fr_fr fr12,fr1 - fmovs fr16,fr1 - test_fr_fr fr16,fr1 - fmovs fr20,fr1 - test_fr_fr fr20,fr1 - fmovs fr24,fr1 - test_fr_fr fr24,fr1 - fmovs fr28,fr1 - test_fr_fr fr28,fr1 - fmovs fr32,fr1 - test_fr_fr fr32,fr1 - fmovs fr36,fr1 - test_fr_fr fr36,fr1 - fmovs fr40,fr1 - test_fr_fr fr40,fr1 - fmovs fr44,fr1 - test_fr_fr fr44,fr1 - fmovs fr48,fr1 - test_fr_fr fr48,fr1 - fmovs fr52,fr1 - test_fr_fr fr52,fr1 - fmovs fr56,fr1 - test_fr_iimmed 0x7fc00000,fr1 - fmovs fr60,fr1 - test_fr_iimmed 0x7f800001,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fmsd.cgs b/sim/testsuite/sim/frv/fmsd.cgs deleted file mode 100644 index cd2efbd..0000000 --- a/sim/testsuite/sim/frv/fmsd.cgs +++ /dev/null @@ -1,146 +0,0 @@ -# frv testcase for fmsd $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fmsd -fmsd: - fmsd fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmsd fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmsd fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmsd fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmsd fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - fmsd fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmsd fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmsd fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmsd fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmsd fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - fmsd fr28,fr0,fr2 - test_fr_fr fr2,fr0 - fmsd fr28,fr4,fr2 - test_fr_fr fr2,fr4 - fmsd fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - fmsd fr28,fr12,fr2 - test_fr_fr fr2,fr12 - fmsd fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmsd fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmsd fr28,fr24,fr2 - test_fr_fr fr2,fr24 - fmsd fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - fmsd fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr8 - fmsd fr28,fr36,fr2 - test_fr_fr fr2,fr36 - fmsd fr28,fr40,fr2 - test_fr_fr fr2,fr40 - fmsd fr28,fr44,fr2 - test_fr_fr fr2,fr44 - fmsd fr28,fr48,fr2 - test_fr_fr fr2,fr48 - fmsd fr28,fr52,fr2 - test_fr_fr fr2,fr52 - - fmsd fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - fmsd fr8,fr28,fr2 - test_fr_fr fr2,fr8 - - fmsd fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr8 - - pass diff --git a/sim/testsuite/sim/frv/fmss.cgs b/sim/testsuite/sim/frv/fmss.cgs deleted file mode 100644 index defe069..0000000 --- a/sim/testsuite/sim/frv/fmss.cgs +++ /dev/null @@ -1,146 +0,0 @@ -# frv testcase for fmss $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fmss -fmss: - fmss fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmss fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmss fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmss fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmss fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - fmss fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmss fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmss fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmss fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmss fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - fmss fr28,fr0,fr2 - test_fr_fr fr2,fr0 - fmss fr28,fr4,fr2 - test_fr_fr fr2,fr4 - fmss fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - fmss fr28,fr12,fr2 - test_fr_fr fr2,fr12 - fmss fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmss fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmss fr28,fr24,fr2 - test_fr_fr fr2,fr24 - fmss fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - fmss fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr8 - fmss fr28,fr36,fr2 - test_fr_fr fr2,fr36 - fmss fr28,fr40,fr2 - test_fr_fr fr2,fr40 - fmss fr28,fr44,fr2 - test_fr_fr fr2,fr44 - fmss fr28,fr48,fr2 - test_fr_fr fr2,fr48 - fmss fr28,fr52,fr2 - test_fr_fr fr2,fr52 - - fmss fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - fmss fr8,fr28,fr2 - test_fr_fr fr2,fr8 - - fmss fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr8 - - pass diff --git a/sim/testsuite/sim/frv/fmsubd.cgs b/sim/testsuite/sim/frv/fmsubd.cgs deleted file mode 100644 index 6b4c943..0000000 --- a/sim/testsuite/sim/frv/fmsubd.cgs +++ /dev/null @@ -1,144 +0,0 @@ -# frv testcase for fmsubd $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fmsubd -fmsubd: - set_dfr_dfr fr16,fr2 - fmsubd fr16,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - fmsubd fr20,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr0,fr2 - test_dfr_dfr fr2,fr0 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr4,fr2 - test_dfr_dfr fr2,fr4 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr8,fr2 - test_dfr_dfr fr2,fr8 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr12,fr2 - test_dfr_dfr fr2,fr12 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr24,fr2 - test_dfr_dfr fr2,fr24 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr28,fr2 - test_dfr_dfr fr2,fr28 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr32,fr2 - test_dfr_dfr fr2,fr32 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr36,fr2 - test_dfr_dfr fr2,fr36 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr40,fr2 - test_dfr_dfr fr2,fr40 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr44,fr2 - test_dfr_dfr fr2,fr44 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr48,fr2 - test_dfr_dfr fr2,fr48 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr52,fr2 - test_dfr_dfr fr2,fr52 - - set_dfr_dfr fr32,fr2 - fmsubd fr8,fr8,fr2 - test_dfr_dfr fr2,fr8 - set_dfr_dfr fr36,fr2 - fmsubd fr36,fr36,fr2 - test_dfr_dfr fr2,fr40 - - fmsubd fr32,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - pass diff --git a/sim/testsuite/sim/frv/fmsubs.cgs b/sim/testsuite/sim/frv/fmsubs.cgs deleted file mode 100644 index 14a5bb3..0000000 --- a/sim/testsuite/sim/frv/fmsubs.cgs +++ /dev/null @@ -1,144 +0,0 @@ -# frv testcase for fmsubs $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fmsubs -fmsubs: - set_fr_fr fr16,fr1 - fmsubs fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fmsubs fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_fr fr16,fr1 - fmsubs fr28,fr0,fr1 - test_fr_fr fr1,fr0 - set_fr_fr fr16,fr1 - fmsubs fr28,fr4,fr1 - test_fr_fr fr1,fr4 - set_fr_fr fr16,fr1 - fmsubs fr28,fr8,fr1 - test_fr_fr fr1,fr8 - set_fr_fr fr16,fr1 - fmsubs fr28,fr12,fr1 - test_fr_fr fr1,fr12 - set_fr_fr fr16,fr1 - fmsubs fr28,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - fmsubs fr28,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - fmsubs fr28,fr24,fr1 - test_fr_fr fr1,fr24 - set_fr_fr fr16,fr1 - fmsubs fr28,fr28,fr1 - test_fr_fr fr1,fr28 - set_fr_fr fr16,fr1 - fmsubs fr28,fr32,fr1 - test_fr_fr fr1,fr32 - set_fr_fr fr16,fr1 - fmsubs fr28,fr36,fr1 - test_fr_fr fr1,fr36 - set_fr_fr fr16,fr1 - fmsubs fr28,fr40,fr1 - test_fr_fr fr1,fr40 - set_fr_fr fr16,fr1 - fmsubs fr28,fr44,fr1 - test_fr_fr fr1,fr44 - set_fr_fr fr16,fr1 - fmsubs fr28,fr48,fr1 - test_fr_fr fr1,fr48 - set_fr_fr fr16,fr1 - fmsubs fr28,fr52,fr1 - test_fr_fr fr1,fr52 - - set_fr_fr fr32,fr1 - fmsubs fr8,fr8,fr1 - test_fr_fr fr1,fr8 - set_fr_fr fr36,fr1 - fmsubs fr36,fr36,fr1 - test_fr_fr fr1,fr40 - - fmsubs fr32,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - pass diff --git a/sim/testsuite/sim/frv/fmuld.cgs b/sim/testsuite/sim/frv/fmuld.cgs deleted file mode 100644 index e06ca07..0000000 --- a/sim/testsuite/sim/frv/fmuld.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for fmuld $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fmuld -fmuld: - fmuld fr16,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - fmuld fr20,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - fmuld fr28,fr0,fr2 - test_dfr_dfr fr2,fr0 - fmuld fr28,fr4,fr2 - test_dfr_dfr fr2,fr4 - fmuld fr28,fr8,fr2 - test_dfr_dfr fr2,fr8 - fmuld fr28,fr12,fr2 - test_dfr_dfr fr2,fr12 - fmuld fr28,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr28,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr28,fr24,fr2 - test_dfr_dfr fr2,fr24 - fmuld fr28,fr28,fr2 - test_dfr_dfr fr2,fr28 - fmuld fr28,fr32,fr2 - test_dfr_dfr fr2,fr32 - fmuld fr28,fr36,fr2 - test_dfr_dfr fr2,fr36 - fmuld fr28,fr40,fr2 - test_dfr_dfr fr2,fr40 - fmuld fr28,fr44,fr2 - test_dfr_dfr fr2,fr44 - fmuld fr28,fr48,fr2 - test_dfr_dfr fr2,fr48 - fmuld fr28,fr52,fr2 - test_dfr_dfr fr2,fr52 - - fmuld fr28,fr8,fr2 - test_dfr_dfr fr2,fr8 - fmuld fr8,fr28,fr2 - test_dfr_dfr fr2,fr8 - - fmuld fr32,fr36,fr2 - test_dfr_dfr fr2,fr40 - - pass diff --git a/sim/testsuite/sim/frv/fmuls.cgs b/sim/testsuite/sim/frv/fmuls.cgs deleted file mode 100644 index a92fa1e..0000000 --- a/sim/testsuite/sim/frv/fmuls.cgs +++ /dev/null @@ -1,125 +0,0 @@ -# frv testcase for fmuls $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fmuls -fmuls: - fmuls fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fmuls fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fmuls fr28,fr0,fr1 - test_fr_fr fr1,fr0 - fmuls fr28,fr4,fr1 - test_fr_fr fr1,fr4 - fmuls fr28,fr8,fr1 - test_fr_fr fr1,fr8 - fmuls fr28,fr12,fr1 - test_fr_fr fr1,fr12 - fmuls fr28,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr28,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr28,fr24,fr1 - test_fr_fr fr1,fr24 - fmuls fr28,fr28,fr1 - test_fr_fr fr1,fr28 - fmuls fr28,fr32,fr1 - test_fr_fr fr1,fr32 - fmuls fr28,fr36,fr1 - test_fr_fr fr1,fr36 - fmuls fr28,fr40,fr1 - test_fr_fr fr1,fr40 - fmuls fr28,fr44,fr1 - test_fr_fr fr1,fr44 - fmuls fr28,fr48,fr1 - test_fr_fr fr1,fr48 - fmuls fr28,fr52,fr1 - test_fr_fr fr1,fr52 - - fmuls fr28,fr8,fr1 - test_fr_fr fr1,fr8 - fmuls fr8,fr28,fr1 - test_fr_fr fr1,fr8 - - fmuls fr32,fr36,fr1 - test_fr_fr fr1,fr40 - - pass diff --git a/sim/testsuite/sim/frv/fnegd.cgs b/sim/testsuite/sim/frv/fnegd.cgs deleted file mode 100644 index c18721b..0000000 --- a/sim/testsuite/sim/frv/fnegd.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for fnegd $FRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fnegd -fnegd: - fnegd fr0,fr2 - test_dfr_dfr fr2,fr52 - fnegd fr8,fr2 - test_dfr_dfr fr2,fr28 - fnegd fr12,fr2 - test_dfr_dfr fr2,fr24 - fnegd fr24,fr2 - test_dfr_dfr fr2,fr12 - fnegd fr28,fr2 - test_dfr_dfr fr2,fr8 - fnegd fr52,fr2 - test_dfr_dfr fr2,fr0 - - pass diff --git a/sim/testsuite/sim/frv/fnegs.cgs b/sim/testsuite/sim/frv/fnegs.cgs deleted file mode 100644 index fdb8770..0000000 --- a/sim/testsuite/sim/frv/fnegs.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for fnegs $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fnegs -fnegs: - fnegs fr0,fr1 - test_fr_fr fr1,fr52 - fnegs fr8,fr1 - test_fr_fr fr1,fr28 - fnegs fr12,fr1 - test_fr_fr fr1,fr24 - fnegs fr24,fr1 - test_fr_fr fr1,fr12 - fnegs fr28,fr1 - test_fr_fr fr1,fr8 - fnegs fr52,fr1 - test_fr_fr fr1,fr0 - - pass diff --git a/sim/testsuite/sim/frv/fnop.cgs b/sim/testsuite/sim/frv/fnop.cgs deleted file mode 100644 index 5e48384..0000000 --- a/sim/testsuite/sim/frv/fnop.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# frv testcase for fnop -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global fnop -fnop: - fnop - - pass diff --git a/sim/testsuite/sim/frv/fr400/addss.cgs b/sim/testsuite/sim/frv/fr400/addss.cgs deleted file mode 100644 index b108f50..0000000 --- a/sim/testsuite/sim/frv/fr400/addss.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# frv testcase for addss $GRi,$GRj,$GRk -# mach: fr405 fr450 - - .include "../testutils.inc" - - start - - .global add -add_nosaturate: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - addss gr7,gr8,gr8 - test_gr_immed 3,gr8 -add_saturate_pos: - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - addss gr7,gr8,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0x4000,0x0000,gr7 - set_gr_limmed 0x4000,0x0000,gr8 - addss gr7,gr8,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - -add_saturate_neg: - set_gr_limmed 0x8000,0x0000,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - addss gr7,gr8,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0001,gr7 - set_gr_limmed 0x8000,0x0001,gr8 - addss gr7,gr8,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/fr400/allinsn.exp b/sim/testsuite/sim/frv/fr400/allinsn.exp deleted file mode 100644 index b169761..0000000 --- a/sim/testsuite/sim/frv/fr400/allinsn.exp +++ /dev/null @@ -1,19 +0,0 @@ -# FRV simulator testsuite. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "fr400 fr405 fr450 fr550" - set cpu_option -mcpu - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/fr400/csdiv.cgs b/sim/testsuite/sim/frv/fr400/csdiv.cgs deleted file mode 100644 index 9fa6d8c..0000000 --- a/sim/testsuite/sim/frv/fr400/csdiv.cgs +++ /dev/null @@ -1,187 +0,0 @@ -# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global csdiv -csdiv: - set_spr_immed 0x1b1b,cccr - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc4,1 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc4,1 - test_gr_immed -1,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 -e1: csdiv gr1,gr3,gr2,cc4,1 - test_gr_immed 1,gr15 - test_gr_limmed 0x8000,0x0000,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc4,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc5,0 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc5,0 - test_gr_immed -1,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 -e2: csdiv gr1,gr3,gr2,cc5,0 - test_gr_immed 2,gr15 - test_gr_limmed 0x8000,0x0000,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc5,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - pass - -ok1: ; exception handler for overflow - test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr400/maddaccs.cgs b/sim/testsuite/sim/frv/fr400/maddaccs.cgs deleted file mode 100644 index 98659c4..0000000 --- a/sim/testsuite/sim/frv/fr400/maddaccs.cgs +++ /dev/null @@ -1,131 +0,0 @@ -# frv testcase for maddaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global maddaccs -maddaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0xdead,0xbeef,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0xbeef,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x2345,0x6789,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - maddaccs.p acc0,acc1 - maddaccs acc2,acc3 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr400/masaccs.cgs b/sim/testsuite/sim/frv/fr400/masaccs.cgs deleted file mode 100644 index 8fbde91..0000000 --- a/sim/testsuite/sim/frv/fr400/masaccs.cgs +++ /dev/null @@ -1,151 +0,0 @@ -# frv testcase for masaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global masaccs -masaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0xdead,0xbeef,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0xbeef,0xdead,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0x4111,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x2345,0x6789,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xfffc,0x7ffd,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0003,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - masaccs.p acc0,acc0 - masaccs acc2,acc2 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr400/maveh.cgs b/sim/testsuite/sim/frv/fr400/maveh.cgs deleted file mode 100644 index 445e121..0000000 --- a/sim/testsuite/sim/frv/fr400/maveh.cgs +++ /dev/null @@ -1,319 +0,0 @@ -# frv testcase for maveh $FRi,$FRj,$FRj on fr400 machines -# mach: all - - .include "../testutils.inc" - - start - - .global maveh -maveh: - ; Test Rounding toward positive infinity via RDAV - or_spr_immed 0x20000000,msr0 - and_spr_immed 0xefffffff,msr0 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x0000,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0002,0x0001,fr12 - - set_fr_iimmed 0x0000,0xffff,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0xffff,fr12 - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xef57,0xdf78,fr12 - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xdf78,0xef57,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x11a3,0x33c5,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x091a,0x2b3c,fr12 - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x4000,0x4000,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xc000,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xc000,fr12 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maveh.p fr10,fr10,fr12 - maveh fr11,fr11,fr13 - test_fr_limmed 0x8000,0x8000,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - - ; Test Rounding toward nearest via RD - or_spr_immed 0x10000000,msr0 - and_spr_immed 0x3fffffff,msr0 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x0000,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0002,0x0001,fr12 - - set_fr_iimmed 0x0000,0xffff,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xffff,0xfffe,fr12 - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xef56,0xdf77,fr12 - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xdf77,0xef56,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x11a3,0x33c5,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x091a,0x2b3c,fr12 - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x4000,0x4000,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xbfff,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xbfff,0xbfff,fr12 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maveh.p fr10,fr10,fr12 - maveh fr11,fr11,fr13 - test_fr_limmed 0x8000,0x8000,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - - ; Test Rounding toward zero via RD - or_spr_immed 0x50000000,msr0 - and_spr_immed 0x7fffffff,msr0 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x0000,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0001,0x0000,fr12 - - set_fr_iimmed 0x0000,0xffff,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0xffff,fr12 - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xef57,0xdf78,fr12 - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xdf78,0xef57,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x11a2,0x33c4,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0919,0x2b3b,fr12 - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x4000,0x3fff,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xc000,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xc000,fr12 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maveh.p fr10,fr10,fr12 - maveh fr11,fr11,fr13 - test_fr_limmed 0x8000,0x8000,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - - ; Test Rounding toward positive infinity via RD - or_spr_immed 0x90000000,msr0 - and_spr_immed 0xbfffffff,msr0 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x0000,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0002,0x0001,fr12 - - set_fr_iimmed 0x0000,0xffff,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0xffff,fr12 - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xef57,0xdf78,fr12 - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xdf78,0xef57,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x11a3,0x33c5,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x091a,0x2b3c,fr12 - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x4000,0x4000,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xc000,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xc000,fr12 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maveh.p fr10,fr10,fr12 - maveh fr11,fr11,fr13 - test_fr_limmed 0x8000,0x8000,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - - ; Test Rounding toward negative infinity via RD - or_spr_immed 0xd0000000,msr0 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x0000,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0001,0x0000,fr12 - - set_fr_iimmed 0x0000,0xffff,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xffff,0xfffe,fr12 - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xef56,0xdf77,fr12 - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xdf77,0xef56,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x11a2,0x33c4,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0919,0x2b3b,fr12 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x4000,0x3fff,fr12 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xbfff,fr12 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xbfff,0xbfff,fr12 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maveh.p fr10,fr10,fr12 - maveh fr11,fr11,fr13 - test_fr_limmed 0x8000,0x8000,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mclracc.cgs b/sim/testsuite/sim/frv/fr400/mclracc.cgs deleted file mode 100644 index 0297544..0000000 --- a/sim/testsuite/sim/frv/fr400/mclracc.cgs +++ /dev/null @@ -1,79 +0,0 @@ -# frv testcase for mclracc $ACC40k,$A -# mach: all - - .include "../testutils.inc" - - start - - .global mclracc -mclracc: - set_accg_immed 0xff,accg0 - set_acc_immed -1,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed -1,acc1 - set_accg_immed 0xff,accg2 - set_acc_immed -1,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed -1,acc3 - - mclracc acc8,0 ; nop - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0xff,accg2 - test_acc_immed -1,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -1,acc3 - - mclracc acc8,1 ; nop - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0xff,accg2 - test_acc_immed -1,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -1,acc3 - - mclracc acc2,0 - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -1,acc3 - - mclracc acc3,1 - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - mclracc acc0,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - mclracc acc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mhdseth.cgs b/sim/testsuite/sim/frv/fr400/mhdseth.cgs deleted file mode 100644 index b99c996..0000000 --- a/sim/testsuite/sim/frv/fr400/mhdseth.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# frv testcase for mhdseth $s12,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mhdseth -mhdseth: - set_fr_immed 0,fr1 - mhdseth 0,fr1 - test_fr_iimmed 0,fr1 - mhdseth 1,fr1 - test_fr_iimmed 0x08000800,fr1 - mhdseth 0xf,fr1 - test_fr_iimmed 0x78007800,fr1 - mhdseth -16,fr1 - test_fr_iimmed 0x80008000,fr1 - mhdseth -1,fr1 - test_fr_iimmed 0xf800f800,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mhdsets.cgs b/sim/testsuite/sim/frv/fr400/mhdsets.cgs deleted file mode 100644 index c495cb7..0000000 --- a/sim/testsuite/sim/frv/fr400/mhdsets.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# frv testcase for mhdsets $s12,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mhdsets -mhdsets: - set_fr_immed 0,fr1 - mhdsets 0,fr1 - test_fr_iimmed 0,fr1 - mhdsets 1,fr1 - test_fr_iimmed 0x00010001,fr1 - mhdsets 0x7ff,fr1 - test_fr_iimmed 0x07ff07ff,fr1 - mhdsets -2048,fr1 - test_fr_iimmed 0xf800f800,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mhsethih.cgs b/sim/testsuite/sim/frv/fr400/mhsethih.cgs deleted file mode 100644 index fed9d23..0000000 --- a/sim/testsuite/sim/frv/fr400/mhsethih.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# frv testcase for mhsethih $s12,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mhsethih -mhsethih: - set_fr_immed 0,fr1 - mhsethih 0,fr1 - test_fr_iimmed 0,fr1 - mhsethih 1,fr1 - test_fr_iimmed 0x08000000,fr1 - mhsethih 0xf,fr1 - test_fr_iimmed 0x78000000,fr1 - mhsethih -16,fr1 - test_fr_iimmed 0x80000000,fr1 - mhsethih -1,fr1 - test_fr_iimmed 0xf8000000,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mhsethis.cgs b/sim/testsuite/sim/frv/fr400/mhsethis.cgs deleted file mode 100644 index ade9102..0000000 --- a/sim/testsuite/sim/frv/fr400/mhsethis.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for mhsethis $s12,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mhsethis -mhsethis: - set_fr_immed 0,fr1 - mhsethis 0,fr1 - test_fr_iimmed 0,fr1 - mhsethis 1,fr1 - test_fr_iimmed 0x00010000,fr1 - mhsethis 0x7ff,fr1 - test_fr_iimmed 0x07ff0000,fr1 - mhsethis -2048,fr1 - test_fr_iimmed 0xf8000000,fr1 - - ; Try parallel set of hi and lo at the same time - mhsethis.p 1,fr1 - mhsetlos 2,fr1 - test_fr_iimmed 0x00010002,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mhsetloh.cgs b/sim/testsuite/sim/frv/fr400/mhsetloh.cgs deleted file mode 100644 index 1dedb83..0000000 --- a/sim/testsuite/sim/frv/fr400/mhsetloh.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for mhsetloh $s12,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mhsetloh -mhsetloh: - set_fr_immed 0,fr1 - mhsetloh 0,fr1 - test_fr_iimmed 0,fr1 - mhsetloh 1,fr1 - test_fr_iimmed 0x0000800,fr1 - mhsetloh 0xf,fr1 - test_fr_iimmed 0x00007800,fr1 - mhsetloh -16,fr1 - test_fr_iimmed 0x00008000,fr1 - mhsetloh -1,fr1 - test_fr_iimmed 0x0000f800,fr1 - - ; Try parallel write to both hi and lo - mhsetloh.p 1,fr1 - mhsethih 0xf,fr1 - test_fr_iimmed 0x78000800,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mhsetlos.cgs b/sim/testsuite/sim/frv/fr400/mhsetlos.cgs deleted file mode 100644 index 8e8839a..0000000 --- a/sim/testsuite/sim/frv/fr400/mhsetlos.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for mhsetlos $s12,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mhsetlos -mhsetlos: - set_fr_immed 0,fr1 - mhsetlos 0,fr1 - test_fr_iimmed 0,fr1 - mhsetlos 1,fr1 - test_fr_iimmed 0x00000001,fr1 - mhsetlos 0x7ff,fr1 - test_fr_iimmed 0x000007ff,fr1 - mhsetlos -2048,fr1 - test_fr_iimmed 0x0000f800,fr1 - - ; Try parallel set of hi and lo at the same time - mhsethis.p 1,fr1 - mhsetlos 2,fr1 - test_fr_iimmed 0x00010002,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fr400/movgs.cgs b/sim/testsuite/sim/frv/fr400/movgs.cgs deleted file mode 100644 index 4e22aab..0000000 --- a/sim/testsuite/sim/frv/fr400/movgs.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for movgs $GRj,iacc0[hl] -# mach: fr400 - - .include "../testutils.inc" - - start - - .global movgs -IACC0H: - set_gr_limmed 0xdead,0xbeef,gr8 - and_spr_immed 0,iacc0h - movgs gr8,iacc0h - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0h -SPR280: - ; try alternate names for iacc0h - and_spr_immed 0,280 - movgs gr8,spr[280] ; iacc0h is spr number 280 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[280] - -IACC0L: - set_gr_limmed 0xdead,0xbeef,gr8 - and_spr_immed 0,iacc0l - movgs gr8,iacc0l - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0l -SPR281: - ; try alternate names for iacc0l - and_spr_immed 0,281 - movgs gr8,spr[281] ; iacc0l is spr number 281 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[281] - -IACC0L_SPR281: - ; try crossing between iacc0l and spr[281] - and_spr_immed 0,281 - and_spr_immed 0,iacc0l - movgs gr8,spr[281] ; iacc0l is spr number 281 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0l - -SPR280_IACC0H: - and_spr_immed 0,280 - and_spr_immed 0,iacc0h - movgs gr8,iacc0h ; iacc0h is spr number 280 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[280] - - pass diff --git a/sim/testsuite/sim/frv/fr400/movsg.cgs b/sim/testsuite/sim/frv/fr400/movsg.cgs deleted file mode 100644 index 3f9df25..0000000 --- a/sim/testsuite/sim/frv/fr400/movsg.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# frv testcase for movsg iacc0[hl],$GRj -# mach: fr400 - - .include "../testutils.inc" - - start - - .global movsg -Iacc0h: - set_spr_limmed 0xdead,0xbeef,iacc0h - set_gr_limmed 0,0,gr8 - movsg iacc0h,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0h -Iacc0l: - set_spr_limmed 0xdead,0xbeef,iacc0l - set_gr_limmed 0,0,gr8 - movsg iacc0l,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0l - -Spr280: - set_spr_limmed 0xdead,0xbeef,spr[280] - set_gr_limmed 0,0,gr8 - movsg spr[280],gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[280] -Spr281: - set_spr_limmed 0xdead,0xbeef,spr[281] - set_gr_limmed 0,0,gr8 - movsg spr[281],gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[281] - -Iacc0h_spr280: - set_spr_limmed 0xdead,0xbeef,spr[280] - set_spr_limmed 0xdead,0xbeef,iacc0h - set_gr_limmed 0,0,gr8 - movsg iacc0h,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[280] -Iacc0l_spr281: - set_spr_limmed 0xdead,0xbeef,spr[281] - set_spr_limmed 0xdead,0xbeef,iacc0l - set_gr_limmed 0,0,gr8 - movsg iacc0l,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[281] - -Spr280_iacc0h: - set_spr_limmed 0xdead,0xbeef,spr[280] - set_spr_limmed 0xdead,0xbeef,iacc0h - set_gr_limmed 0,0,gr8 - movsg spr[280],gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0h -Spr281_iacc0l: - set_spr_limmed 0xdead,0xbeef,spr[281] - set_spr_limmed 0xdead,0xbeef,iacc0l - set_gr_limmed 0,0,gr8 - movsg spr[281],gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0l - - pass diff --git a/sim/testsuite/sim/frv/fr400/msubaccs.cgs b/sim/testsuite/sim/frv/fr400/msubaccs.cgs deleted file mode 100644 index f0aba1d..0000000 --- a/sim/testsuite/sim/frv/fr400/msubaccs.cgs +++ /dev/null @@ -1,131 +0,0 @@ -# frv testcase for msubaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global msubaccs -msubaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg3 - test_acc_limmed 0x4111,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffffffe,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000002,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0x00000000,acc3 - msubaccs.p acc0,acc1 - msubaccs acc2,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x8,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr400/scutss.cgs b/sim/testsuite/sim/frv/fr400/scutss.cgs deleted file mode 100644 index f958de6..0000000 --- a/sim/testsuite/sim/frv/fr400/scutss.cgs +++ /dev/null @@ -1,664 +0,0 @@ -# frv testcase for scutss $FRj,$FRk -# mach: fr405 fr450 - - .include "../testutils.inc" - - start - - .global scutss -scutss: - set_spr_immed 0xffffffe7,iacc0h - set_spr_immed 0x89abcdef,iacc0l - - set_gr_immed 0,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffe8,gr11 - - set_gr_immed 1,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffcf,gr11 - - set_gr_immed 2,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xff9e,gr11 - - set_gr_immed 3,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xff3c,gr11 - - set_gr_immed 4,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfe79,gr11 - - set_gr_immed 5,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfcf1,gr11 - - set_gr_immed 6,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xf9e2,gr11 - - set_gr_immed 7,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xf3c5,gr11 - - set_gr_immed 8,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xe78a,gr11 - - set_gr_immed 9,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xcf13,gr11 - - set_gr_immed 10,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0x9e27,gr11 - - set_gr_immed 11,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0x3c4d,gr11 - - set_gr_immed 12,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfffe,0x789b,gr11 - - set_gr_immed 13,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfffc,0xf135,gr11 - - set_gr_immed 14,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfff9,0xe26b,gr11 - - set_gr_immed 15,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfff3,0xc4d6,gr11 - - set_gr_immed 16,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffe7,0x89ac,gr11 - - set_gr_immed 17,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffcf,0x1358,gr11 - - set_gr_immed 18,gr10 - scutss gr10,gr11 - test_gr_limmed 0xff9e,0x26af,gr11 - - set_gr_immed 19,gr10 - scutss gr10,gr11 - test_gr_limmed 0xff3c,0x4d5e,gr11 - - set_gr_immed 20,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfe78,0x9abd,gr11 - - set_gr_immed 21,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfcf1,0x357a,gr11 - - set_gr_immed 22,gr10 - scutss gr10,gr11 - test_gr_limmed 0xf9e2,0x6af3,gr11 - - set_gr_immed 23,gr10 - scutss gr10,gr11 - test_gr_limmed 0xf3c4,0xd5e7,gr11 - - set_gr_immed 24,gr10 - scutss gr10,gr11 - test_gr_limmed 0xe789,0xabce,gr11 - - set_gr_immed 25,gr10 - scutss gr10,gr11 - test_gr_limmed 0xcf13,0x579c,gr11 - - set_gr_immed 26,gr10 - scutss gr10,gr11 - test_gr_limmed 0x9e26,0xaf38,gr11 - - set_gr_immed 27,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 28,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 29,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 30,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 31,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 32,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 33,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 34,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 35,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 36,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 37,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 38,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 39,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 40,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 41,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 42,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 43,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 44,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 45,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 46,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 47,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 48,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 49,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 50,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 51,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 52,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 53,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 54,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 55,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 56,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 57,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 58,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 59,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 60,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 61,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 62,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 63,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 64,gr10 ; same as -64 - scutss gr10,gr11 - test_gr_immed 0,gr11 - - set_gr_immed 128,gr10 ; same as 0 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffe8,gr11 - - .global scutss2 -scutss2: - set_spr_immed 0xe789abcd,iacc0h - set_spr_immed 0xefa5a5a5,iacc0l - - set_gr_limmed 0xffff,0xffff,gr10 ; -1 - scutss gr10,gr11 - test_gr_limmed 0xf3c4,0xd5e7,gr11 - - set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter) - scutss gr10,gr11 - test_gr_limmed 0xf9e2,0x6af3,gr11 - - set_gr_immed -3,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfcf1,0x357a,gr11 - - set_gr_immed -4,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfe78,0x9abd,gr11 - - set_gr_immed -5,gr10 - scutss gr10,gr11 - test_gr_limmed 0xff3c,0x4d5e,gr11 - - set_gr_immed -6,gr10 - scutss gr10,gr11 - test_gr_limmed 0xff9e,0x26af,gr11 - - set_gr_immed -7,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffcf,0x1358,gr11 - - set_gr_immed -8,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffe7,0x89ac,gr11 - - set_gr_immed -9,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfff3,0xc4d6,gr11 - - set_gr_immed -10,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfff9,0xe26b,gr11 - - set_gr_immed -11,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfffc,0xf135,gr11 - - set_gr_immed -12,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfffe,0x789b,gr11 - - set_gr_immed -13,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0x3c4d,gr11 - - set_gr_immed -14,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0x9e27,gr11 - - set_gr_immed -15,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xcf13,gr11 - - set_gr_immed -16,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xe78a,gr11 - - set_gr_immed -17,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xf3c5,gr11 - - set_gr_immed -18,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xf9e2,gr11 - - set_gr_immed -19,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfcf1,gr11 - - set_gr_immed -20,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfe79,gr11 - - set_gr_immed -21,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xff3c,gr11 - - set_gr_immed -22,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xff9e,gr11 - - set_gr_immed -23,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffcf,gr11 - - set_gr_immed -24,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffe8,gr11 - - set_gr_immed -25,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfff4,gr11 - - set_gr_immed -26,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfffa,gr11 - - set_gr_immed -27,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfffd,gr11 - - set_gr_immed -28,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfffe,gr11 - - set_gr_immed -29,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffff,gr11 - - set_gr_immed -30,gr10 - scutss gr10,gr11 - test_gr_immed 0,gr11 - - set_gr_immed -31,gr10 - scutss gr10,gr11 - test_gr_immed 0,gr11 - - set_gr_immed -32,gr10 - scutss gr10,gr11 - test_gr_immed 0,gr11 - - set_gr_limmed 0,64,gr10 ; same as -32 - scutss gr10,gr11 - test_gr_immed 0,gr11 - - set_spr_immed 0x6789abcd,iacc0h - set_spr_immed 0xefa5a5a5,iacc0l - - set_gr_limmed 0xffff,0xffff,gr10 - scutss gr10,gr11 - test_gr_limmed 0x33c4,0xd5e7,gr11 - - set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter) - scutss gr10,gr11 - test_gr_limmed 0x19e2,0x6af3,gr11 - - set_gr_immed -3,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0cf1,0x357a,gr11 - - set_gr_immed -4,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0678,0x9abd,gr11 - - set_gr_immed -5,gr10 - scutss gr10,gr11 - test_gr_limmed 0x033c,0x4d5e,gr11 - - set_gr_immed -6,gr10 - scutss gr10,gr11 - test_gr_limmed 0x019e,0x26af,gr11 - - set_gr_immed -7,gr10 - scutss gr10,gr11 - test_gr_limmed 0x00cf,0x1358,gr11 - - set_gr_immed -8,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0067,0x89ac,gr11 - - set_gr_immed -9,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0033,0xc4d6,gr11 - - set_gr_immed -10,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0019,0xe26b,gr11 - - set_gr_immed -11,gr10 - scutss gr10,gr11 - test_gr_limmed 0x000c,0xf135,gr11 - - set_gr_immed -12,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0006,0x789b,gr11 - - set_gr_immed -13,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0003,0x3c4d,gr11 - - set_gr_immed -14,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0001,0x9e27,gr11 - - set_gr_immed -15,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0xcf13,gr11 - - set_gr_immed -16,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x678a,gr11 - - set_gr_immed -17,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x33c5,gr11 - - set_gr_immed -18,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x19e2,gr11 - - set_gr_immed -19,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0cf1,gr11 - - set_gr_immed -20,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0679,gr11 - - set_gr_immed -21,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x033c,gr11 - - set_gr_immed -22,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x019e,gr11 - - set_gr_immed -23,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x00cf,gr11 - - set_gr_immed -24,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0068,gr11 - - set_gr_immed -25,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0034,gr11 - - set_gr_immed -26,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x001a,gr11 - - set_gr_immed -27,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x000d,gr11 - - set_gr_immed -28,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0006,gr11 - - set_gr_immed -29,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0003,gr11 - - set_gr_immed -30,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0002,gr11 - - set_gr_immed -31,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0001,gr11 - - set_gr_immed -32,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0000,gr11 - - set_gr_immed 64,gr10 ; same as -32 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0000,gr11 - - ; Examples from the customer (modified for iacc0) - set_spr_immed 0xffffffff,iacc0h - set_spr_immed 0xffe00000,iacc0l - - set_gr_limmed 0,16,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffe0,gr11 - - set_gr_limmed 0,17,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffc0,gr11 - - set_gr_limmed 0,18,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xff80,gr11 - - set_spr_immed 0,iacc0h - set_spr_immed 0x003fffff,iacc0l - - set_gr_limmed 0,40,gr10 - scutss gr10,gr11 - test_gr_limmed 0x3fff,0xff00,gr11 - - set_gr_limmed 0,41,gr10 - scutss gr10,gr11 - test_gr_limmed 0x7fff,0xfe00,gr11 - - set_spr_immed 0x7f,iacc0h - set_spr_immed 0xffe00000,iacc0l - - set_gr_limmed 0,40,gr10 - scutss gr10,gr11 - test_gr_limmed 0x7fff,0xffff,gr11 ; saturated - - set_gr_limmed 0,41,gr10 - scutss gr10,gr11 - test_gr_limmed 0x7fff,0xffff,gr11 ; saturated - - set_gr_limmed 0,42,gr10 - scutss gr10,gr11 - test_gr_limmed 0x7fff,0xffff,gr11 ; saturated - - set_spr_immed 0x08,iacc0h - set_spr_immed 0x003fffff,iacc0l - - set_gr_limmed 0,40,gr10 - scutss gr10,gr11 - test_gr_limmed 0x7fff,0xffff,gr11 ; saturated - - set_gr_limmed 0,41,gr10 - scutss gr10,gr11 - test_gr_limmed 0x7fff,0xffff,gr11 ; saturated - - set_spr_immed 0xffffffff,iacc0h - set_spr_immed 0xefe00000,iacc0l - - set_gr_limmed 0,40,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 ; saturated - - set_gr_limmed 0,41,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 ; saturated - - set_gr_limmed 0,42,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 ; saturated - - set_spr_immed 0x80000000,iacc0h - set_spr_immed 0x003fffff,iacc0l - - set_gr_limmed 0,16,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 ; saturated - - set_gr_limmed 0,17,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 ; saturated - - set_spr_immed 0xaf5a5a5a,iacc0h - set_spr_immed 0x5a5a5a5a,iacc0l - - set_gr_limmed 0xffff,0xfffc,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfaf5,0xa5a6,gr11 - - set_spr_immed 0x2f5a5a5a,iacc0h - set_spr_immed 0x5a5a5a5a,iacc0l - - set_gr_limmed 0xffff,0xfff9,gr10 - scutss gr10,gr11 - test_gr_limmed 0x005e,0xb4b5,gr11 - -# From the manual - .global scutss3 -scutss3: - set_spr_immed 0xfffffedc,iacc0h - set_spr_immed 0xba987654,iacc0l - - set_gr_immed 16,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfedc,0xba98,gr11 - - set_gr_immed 12,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffed,0xcbaa,gr11 - - set_gr_immed -4,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffee,gr11 - - set_gr_immed 24,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - pass diff --git a/sim/testsuite/sim/frv/fr400/sdiv.cgs b/sim/testsuite/sim/frv/fr400/sdiv.cgs deleted file mode 100644 index b9c03cf..0000000 --- a/sim/testsuite/sim/frv/fr400/sdiv.cgs +++ /dev/null @@ -1,71 +0,0 @@ -# frv testcase for sdiv $GRi,$GRj,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global sdiv -sdiv: - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - sdiv gr1,gr3,gr2 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - sdiv gr1,gr3,gr2 - test_gr_immed -1,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - sdiv gr1,gr3,gr2 - test_gr_limmed 0x7fff,0xffff,gr2 - test_spr_bits 0x4,2,1,isr ; isr.aexc is set - - and_spr_immed -33,isr ; turn off isr.edem - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 -e1: sdiv gr1,gr3,gr2 ; overflow - test_gr_immed 1,gr15 - test_gr_limmed 0x8000,0x0000,gr2; gr2 updated - - ; divide by zero - set_spr_addr ok2,lr - set_gr_immed 0xdeadbeef,gr2 -e2: sdiv gr1,gr0,gr2 ; divide by zero - test_gr_immed 2,gr15 ; handler called - test_gr_immed 0xdeadbeef,gr2 ; gr2 not updated. - - pass - -ok1: ; exception handler for overflow - test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail - -ok2: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr400/sdivi.cgs b/sim/testsuite/sim/frv/fr400/sdivi.cgs deleted file mode 100644 index fda573e..0000000 --- a/sim/testsuite/sim/frv/fr400/sdivi.cgs +++ /dev/null @@ -1,70 +0,0 @@ -# frv testcase for sdivi $GRi,$s12,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global sdivi -sdivi: - ; simple division 12 / 3 - set_gr_immed 12,gr1 - sdivi gr1,3,gr2 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0xfedc,0xba98,gr1 - sdivi gr1,0x7ff,gr2 - test_gr_limmed 0xffff,0xdb93,gr2 - - ; Random negative example - set_gr_limmed 0xfedc,0xba98,gr1 - sdivi gr1,-2048,gr2 - test_gr_immed 0x2468,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_limmed 0x8000,0x0000,gr1 - sdivi gr1,-1,gr2 - test_gr_limmed 0x7fff,0xffff,gr2 - test_spr_bits 0x4,2,1,isr ; isr.aexc is set - - and_spr_immed -33,isr ; turn off isr.edem - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_limmed 0x8000,0x0000,gr1 -e1: sdivi gr1,-1,gr2 - test_gr_immed 1,gr15 - test_gr_limmed 0x8000,0x0000,gr2 - - ; divide by zero - set_spr_addr ok2,lr -e2: sdivi gr1,0,gr2 ; divide by zero - test_gr_immed 2,gr15 - - pass - -ok1: ; exception handler for overflow - test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail - -ok2: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr400/slass.cgs b/sim/testsuite/sim/frv/fr400/slass.cgs deleted file mode 100644 index 3e8bcac..0000000 --- a/sim/testsuite/sim/frv/fr400/slass.cgs +++ /dev/null @@ -1,104 +0,0 @@ -# frv testcase for slass $GRi,$GRj,$GRk -# mach: fr405 fr450 - - .include "../testutils.inc" - - start - - .global sll -slass0: - set_gr_immed 0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - slass gr8,gr7,gr6 - test_gr_immed 2,gr8 - test_gr_immed 0,gr7 - test_gr_immed 2,gr6 -slass1: - set_gr_immed 1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - slass gr8,gr7,gr6 - test_gr_immed 2,gr8 - test_gr_immed 1,gr7 - test_gr_immed 4,gr6 - -slass2: - set_gr_immed 31,gr7 ; Shift 1 by 31 - set_gr_immed 1,gr8 - slass gr8,gr7,gr6 - test_gr_immed 1,gr8 - test_gr_immed 31,gr7 - test_gr_limmed 0x7fff,0xffff,gr6 - -slass3: - set_gr_immed 31,gr7 ; Shift -1 by 31 - set_gr_immed -1,gr8 - slass gr8,gr7,gr6 - test_gr_immed -1,gr8 - test_gr_immed 31,gr7 - test_gr_limmed 0x8000,0x0000,gr6 - -slass4: - set_gr_immed 14,gr7 ; Shift 0xffff0000 by 14 - set_gr_limmed 0xffff,0x0000,gr8 - slass gr8,gr7,gr6 - test_gr_limmed 0xffff,0x0000,gr8 - test_gr_immed 14,gr7 - test_gr_limmed 0xc000,0x0000,gr6 - -slass5: - set_gr_immed 15,gr7 ; Shift 0xffff0000 by 15 - set_gr_limmed 0xffff,0x0000,gr8 - slass gr8,gr7,gr6 - test_gr_limmed 0xffff,0x0000,gr8 - test_gr_immed 15,gr7 - test_gr_limmed 0x8000,0x0000,gr6 - -slass6: - set_gr_immed 20,gr7 ; Shift 0xffff0000 by 20 - set_gr_limmed 0xffff,0x0000,gr8 - slass gr8,gr7,gr6 - test_gr_limmed 0xffff,0x0000,gr8 - test_gr_immed 20,gr7 - test_gr_limmed 0x8000,0x0000,gr6 - -slass7: - set_gr_immed 14,gr7 ; Shift 0x0000ffff by 14 - set_gr_limmed 0x0000,0xffff,gr8 - slass gr8,gr7,gr6 - test_gr_limmed 0x0000,0xffff,gr8 - test_gr_immed 14,gr7 - test_gr_limmed 0x3fff,0xc000,gr6 - -slass8: - set_gr_immed 15,gr7 ; Shift 0x0000ffff by 15 - set_gr_limmed 0x0000,0xffff,gr8 - slass gr8,gr7,gr6 - test_gr_limmed 0x0000,0xffff,gr8 - test_gr_immed 15,gr7 - test_gr_limmed 0x7fff,0x8000,gr6 - -slass9: - set_gr_immed 20,gr7 ; Shift 0x0000ffff by 20 - set_gr_limmed 0x0000,0xffff,gr8 - slass gr8,gr7,gr6 - test_gr_limmed 0x0000,0xffff,gr8 - test_gr_immed 20,gr7 - test_gr_limmed 0x7fff,0xffff,gr6 - -slass10: - set_gr_immed 30,gr7 ; Shift 1 by 30 - set_gr_immed 1,gr8 - slass gr8,gr7,gr6 - test_gr_immed 1,gr8 - test_gr_immed 30,gr7 - test_gr_limmed 0x4000,0x0000,gr6 - -slass11: - set_gr_immed 30,gr7 ; Shift -1 by 30 - set_gr_immed -1,gr8 - slass gr8,gr7,gr6 - test_gr_immed -1,gr8 - test_gr_immed 30,gr7 - test_gr_limmed 0xc000,0000,gr6 - - pass diff --git a/sim/testsuite/sim/frv/fr400/smass.cgs b/sim/testsuite/sim/frv/fr400/smass.cgs deleted file mode 100644 index 4594ecd..0000000 --- a/sim/testsuite/sim/frv/fr400/smass.cgs +++ /dev/null @@ -1,359 +0,0 @@ -# frv testcase for smass $GRi,$GRj -# mach: fr405 fr450 - - .include "../testutils.inc" - - start - - .global smass -smass1: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 3,gr7 - test_gr_immed 2,gr8 - test_spr_immed 7,iacc0l ; result 3*2+1 - test_spr_immed 0,iacc0h -smass2: - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 1,gr7 - test_gr_immed 2,gr8 - test_spr_immed 3,iacc0l ; result 1*2+1 - test_spr_immed 0,iacc0h -smass3: - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 1,gr8 - test_gr_immed 2,gr7 - test_spr_immed 3,iacc0l ; result 2*1+1 - test_spr_immed 0,iacc0h -smass4: - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 2,gr8 - test_gr_immed 0,gr7 - test_spr_immed 1,iacc0l ; result 0*2+1 - test_spr_immed 0,iacc0h -smass5: - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr7 - test_spr_immed 1,iacc0l ; result 2*0+1 - test_spr_immed 0,iacc0h -smass6: - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 2,gr8 - test_gr_limmed 0x3fff,0xffff,gr7 - test_spr_limmed 0x7fff,0xffff,iacc0l ; 3fffffff*2+1 - test_spr_immed 0,iacc0h -smass7: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*2+1 - test_spr_immed 0,iacc0h -smass8: - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 4,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_immed 1,iacc0l ; 40000000*4+1 - test_spr_immed 1,iacc0h -smass9: - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_immed 0x00000002,iacc0l ; 7fffffff*7fffffff+1 - test_spr_limmed 0x3fff,0xffff,iacc0h -smass10: - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 2,gr8 - test_gr_immed -3,gr7 - test_spr_immed -5,iacc0l ; -3*2+1 - test_spr_immed -1,iacc0h -smass11: - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 3,gr7 - test_spr_immed -5,iacc0l ; 3*-2+1 - test_spr_immed -1,iacc0h -smass12: - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 1,gr7 - test_spr_immed -1,iacc0l ; 1*-2+1 - test_spr_immed -1,iacc0h -smass13: - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 1,gr8 - test_gr_immed -2,gr7 - test_spr_immed -1,iacc0l ; -2*1+1 - test_spr_immed -1,iacc0h -smass14: - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 0,gr7 - test_spr_immed 1,iacc0l ; 0*-2+1 - test_spr_immed 0,iacc0h -smass15: - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed -2,gr7 - test_spr_immed 1,iacc0l ; -2*0+1 - test_spr_immed 0,iacc0h -smass16: - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x2000,0x0001,gr7 - test_spr_limmed 0xbfff,0xffff,iacc0l ; 20000001*-2+1 - test_spr_limmed 0xffff,0xffff,iacc0h -smass17: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*-2+1 - test_spr_limmed 0xffff,0xffff,iacc0h -smass18: - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x4000,0x0001,gr7 - test_spr_limmed 0x7fff,0xffff,iacc0l ; 40000001*-2+1 - test_spr_limmed 0xffff,0xffff,iacc0h -smass19: - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -4,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x0000,0x0001,iacc0l ; 40000000*-4+1 - test_spr_limmed 0xffff,0xffff,iacc0h -smass20: - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x8000,0x0001,iacc0l ; 7fffffff*80000000+1 - test_spr_limmed 0xc000,0x0000,iacc0h -smass21: - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -3,gr7 - test_spr_immed 7,iacc0l ; -3*-2+1 - test_spr_immed 0,iacc0h -smass22: - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -1,gr7 - test_spr_immed 3,iacc0l ; -1*-2+1 - test_spr_immed 0,iacc0h -smass23: - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -1,gr8 - test_gr_immed -2,gr7 - test_spr_immed 3,iacc0l ; -2*-1+1 - test_spr_immed 0,iacc0h -smass24: - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0xc000,0x0001,gr7 - test_spr_limmed 0x7fff,0xffff,iacc0l ; c0000001*-2+1 - test_spr_immed 0,iacc0h -smass25: - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0xc000,0x0000,gr7 - test_spr_limmed 0x8000,0x0001,iacc0l ; c0000000*-2+1 - test_spr_immed 0,iacc0h -smass26: - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -4,gr8 - test_gr_limmed 0xc000,0x0000,gr7 - test_spr_immed 0x00000001,iacc0l ; c0000000*-4+1 - test_spr_immed 1,iacc0h -smass27: - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_limmed 0x8000,0x0001,gr7 - test_spr_immed 0x00000002,iacc0l ; 80000001*80000001+1 - test_spr_limmed 0x3fff,0xffff,iacc0h -smass28: - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr7 - test_spr_immed 0x00000001,iacc0l ; 80000000*80000000+1 - test_spr_limmed 0x4000,0x0000,iacc0h - -smass29: - set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos) - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_limmed 0xffff,0xfffe,iacc0l - set_spr_limmed 0x4000,0x0000,iacc0h - smass gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000fffffffe - -smass30: - set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos) - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_limmed 0xffff,0xffff,iacc0l - set_spr_limmed 0x4000,0x0000,iacc0h - smass gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000ffffffff - -smass31: - set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos) - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_limmed 0xffff,0xffff,iacc0l - set_spr_limmed 0x7fff,0xffff,iacc0h - smass gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x7fff,0xffff,iacc0h ; 7fffffffffffffff - -smass32: - set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg) - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_limmed 0x8000,0x0000,iacc0l - set_spr_limmed 0xbfff,0xffff,iacc0h - smass gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff80000000 - -smass33: - set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg) - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_limmed 0x7fff,0xffff,iacc0l - set_spr_limmed 0xbfff,0xffff,iacc0h - smass gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff - -smass34: - set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg) - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_limmed 0x0000,0x0000,iacc0l - set_spr_limmed 0x8000,0x0000,iacc0h - smass gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x8000,0x0000,iacc0h ; 8000000000000000 - - pass diff --git a/sim/testsuite/sim/frv/fr400/smsss.cgs b/sim/testsuite/sim/frv/fr400/smsss.cgs deleted file mode 100644 index 50876d8..0000000 --- a/sim/testsuite/sim/frv/fr400/smsss.cgs +++ /dev/null @@ -1,354 +0,0 @@ -# frv testcase for smsss $GRi,$GRj -# mach: fr405 fr450 - - .include "../testutils.inc" - - start - - .global smsss -smsss1: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 7,iacc0l - smsss gr7,gr8 - test_gr_immed 3,gr7 - test_gr_immed 2,gr8 - test_spr_immed 1,iacc0l ; result 7-3*2 - test_spr_immed 0,iacc0h -smsss2: - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 3,iacc0l - smsss gr7,gr8 - test_gr_immed 1,gr7 - test_gr_immed 2,gr8 - test_spr_immed 1,iacc0l ; result 3-1*2 - test_spr_immed 0,iacc0h -smsss3: - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 3,iacc0l - smsss gr7,gr8 - test_gr_immed 1,gr8 - test_gr_immed 2,gr7 - test_spr_immed 1,iacc0l ; result 3-2*1 - test_spr_immed 0,iacc0h -smsss4: - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed 2,gr8 - test_gr_immed 0,gr7 - test_spr_immed 1,iacc0l ; result 1-0*2 - test_spr_immed 0,iacc0h -smsss5: - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr7 - test_spr_immed 1,iacc0l ; result 1-2*0 - test_spr_immed 0,iacc0h -smsss6: - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_spr_immed -1,iacc0h - set_spr_immed -1,iacc0l - smsss gr7,gr8 - test_gr_immed 2,gr8 - test_gr_limmed 0x3fff,0xffff,gr7 - test_spr_limmed 0x8000,0x0001,iacc0l ; -1-3fffffff*2 - test_spr_immed -1,iacc0h -smsss7: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_spr_immed -1,iacc0h - set_spr_limmed 0x8000,0x0001,iacc0l - smsss gr7,gr8 - test_gr_immed 2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_immed 1,iacc0l ; ffffffff80000001-40000000*2 - test_spr_immed -1,iacc0h -smsss8: - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_spr_immed -1,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed 4,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_immed 1,iacc0l ; ffffffff00000001-40000000*4 - test_spr_immed -2,iacc0h -smsss9: - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_limmed 0x7fff,0xffff,iacc0h - set_spr_immed -1,iacc0l - smsss gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xfffe,iacc0l ; 7fffffffffffffff-7fffffff*7fffffff - test_spr_limmed 0x4000,0x0000,iacc0h -smsss10: - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_spr_immed -1,iacc0h - set_spr_immed -5,iacc0l - smsss gr7,gr8 - test_gr_immed 2,gr8 - test_gr_immed -3,gr7 - test_spr_immed 1,iacc0l ; -5-(-3*2) - test_spr_immed 0,iacc0h -smsss11: - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_spr_immed -1,iacc0h - set_spr_immed -5,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 3,gr7 - test_spr_immed 1,iacc0l ; -5-(3*-2) - test_spr_immed 0,iacc0h -smsss12: - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_spr_immed -1,iacc0h - set_spr_immed -1,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 1,gr7 - test_spr_immed 1,iacc0l ; -1-(1*-2) - test_spr_immed 0,iacc0h -smsss13: - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_spr_immed -1,iacc0h - set_spr_immed -1,iacc0l - smsss gr7,gr8 - test_gr_immed 1,gr8 - test_gr_immed -2,gr7 - test_spr_immed 1,iacc0l ; -1-(-2*1) - test_spr_immed 0,iacc0h -smsss14: - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 0,gr7 - test_spr_immed 1,iacc0l ; 1-(0*-2) - test_spr_immed 0,iacc0h -smsss15: - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed -2,gr7 - test_spr_immed 1,iacc0l ; 1-(-2*0) - test_spr_immed 0,iacc0h -smsss16: - set_gr_limmed 0x2000,0x0000,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_limmed 0x3fff,0xffff,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x2000,0x0000,gr7 - test_spr_limmed 0x7fff,0xffff,iacc0l - test_spr_immed 0,iacc0h ; 3fffffff-20000001*-2 -smsss17: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x8000,0x0001,iacc0l ; 1-40000000*-2 - test_spr_immed 0,iacc0h -smsss18: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_spr_immed -1,iacc0h - set_spr_immed -1,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x7fff,0xffff,iacc0l - test_spr_immed 0,iacc0h ; -1-40000000*-2 -smsss19: - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed -4,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_immed 1,iacc0l ; 200000001-(40000000*-4) - test_spr_immed 1,iacc0h -smsss20: - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_limmed 0xbfff,0xffff,iacc0h - set_spr_limmed 0x0000,0x0001,iacc0l - smsss gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_immed 0,iacc0l ; bfffffff00000001-(7fffffff*7fffffff) - test_spr_limmed 0x8000,0x0000,iacc0h -smsss21: - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 7,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -3,gr7 - test_spr_immed 1,iacc0l ; 7-(-3*-2) - test_spr_immed 0,iacc0h -smsss22: - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 3,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -1,gr7 - test_spr_immed 1,iacc0l ; 3-(-1*-2) - test_spr_immed 0,iacc0h -smsss23: - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 3,iacc0l - smsss gr7,gr8 - test_gr_immed -1,gr8 - test_gr_immed -2,gr7 - test_spr_immed 1,iacc0l ; 3-(-2*-1) - test_spr_immed 0,iacc0h -smsss24: - set_gr_immed -32768,gr7 ; 31 bit result - set_gr_immed -32768,gr8 - set_spr_immed 0,iacc0h - set_spr_limmed 0xbfff,0xffff,iacc0l - smsss gr7,gr8 - test_gr_immed -32768,gr8 - test_gr_immed -32768,gr7 - test_spr_limmed 0x7fff,0xffff,iacc0l ; 7ffffffb-(-2*-2) - test_spr_immed 0,iacc0h -smsss25: - set_gr_immed 0xffff,gr7 ; 32 bit result - set_gr_immed 0xffff,gr8 - set_spr_immed 1,iacc0h - set_spr_limmed 0xfffe,0x0000,iacc0l - smsss gr7,gr8 - test_gr_immed 0xffff,gr8 - test_gr_immed 0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 1fffe0000-ffff*ffff - test_spr_immed 0,iacc0h -smsss26: - set_gr_limmed 0x0001,0x0000,gr7 ; 33 bit result - set_gr_limmed 0x0001,0x0000,gr8 - set_spr_immed 2,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_limmed 0x0001,0x0000,gr8 - test_gr_limmed 0x0001,0x0000,gr7 - test_spr_immed 1,iacc0l ; 0x200000001-0x10000*0x10000 - test_spr_immed 1,iacc0h -smsss27: - set_gr_immed -2,gr7 ; almost max positive result - set_gr_immed -2,gr8 - set_spr_limmed 0x7fff,0xffff,iacc0h - set_spr_limmed 0xffff,0xffff,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -2,gr7 - test_spr_limmed 0xffff,0xfffb,iacc0l ; maxpos - (-2*-2) - test_spr_limmed 0x7fff,0xffff,iacc0h -smsss28: - set_gr_immed 0,gr7 ; max positive result - set_gr_immed 0,gr8 - set_spr_limmed 0x7fff,0xffff,iacc0h - set_spr_limmed 0xffff,0xffff,iacc0l - smsss gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; maxpos-(0*0) - test_spr_limmed 0x7fff,0xffff,iacc0h -smsss29: - set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos) - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_limmed 0x4000,0x0000,iacc0h - set_spr_limmed 0x7fff,0xffff,iacc0l - smsss gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 400000007fffffff - - test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff -smsss30: - set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos) - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_limmed 0x4000,0x0000,iacc0h - set_spr_limmed 0x8000,0x0000,iacc0l - smsss gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 4000000080000000 - - test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff - -smsss31: - set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos) - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_limmed 0xffff,0xffff,iacc0l - set_spr_limmed 0x7fff,0xffff,iacc0h - smsss gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffffffffffff - - test_spr_limmed 0x7fff,0xffff,iacc0h ; 80000000*80000000 -smsss32: - set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg) - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_immed 1,iacc0l - set_spr_limmed 0xbfff,0xffff,iacc0h - smsss gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l ; bfffffff00000001 - - test_spr_limmed 0x8000,0x0000,iacc0h ; 0x7fffffff*0x7fffffff -smsss33: - set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg) - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_immed 0,iacc0l - set_spr_limmed 0xbfff,0xffff,iacc0h - smsss gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff -smsss34: - set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg) - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_limmed 0x0000,0x0000,iacc0l - set_spr_limmed 0x8000,0x0000,iacc0h - smsss gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l ; 8000000000000000- - test_spr_limmed 0x8000,0x0000,iacc0h ; 7fffffff*7fffffff+ - - pass diff --git a/sim/testsuite/sim/frv/fr400/smu.cgs b/sim/testsuite/sim/frv/fr400/smu.cgs deleted file mode 100644 index eae788e..0000000 --- a/sim/testsuite/sim/frv/fr400/smu.cgs +++ /dev/null @@ -1,237 +0,0 @@ -# frv testcase for smu $GRi,$GRj -# mach: fr405 fr450 - - .include "../testutils.inc" - - start - - .global smu -smu1: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - smu gr7,gr8 - test_gr_immed 3,gr7 - test_gr_immed 2,gr8 - test_spr_immed 6,iacc0l - test_spr_immed 0,iacc0h -smu2: - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - smu gr7,gr8 - test_gr_immed 1,gr7 - test_gr_immed 2,gr8 - test_spr_immed 2,iacc0l - test_spr_immed 0,iacc0h -smu3: - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - smu gr7,gr8 - test_gr_immed 1,gr8 - test_gr_immed 2,gr7 - test_spr_immed 2,iacc0l - test_spr_immed 0,iacc0h -smu4: - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - smu gr7,gr8 - test_gr_immed 2,gr8 - test_gr_immed 0,gr7 - test_spr_immed 0,iacc0l - test_spr_immed 0,iacc0h -smu5: - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - smu gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr7 - test_spr_immed 0,iacc0l - test_spr_immed 0,iacc0h -smu6: - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - smu gr7,gr8 - test_gr_immed 2,gr8 - test_gr_limmed 0x3fff,0xffff,gr7 - test_spr_limmed 0x7fff,0xfffe,iacc0l - test_spr_immed 0,iacc0h -smu7: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - smu gr7,gr8 - test_gr_immed 2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x8000,0x0000,iacc0l - test_spr_immed 0,iacc0h -smu8: - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - smu gr7,gr8 - test_gr_immed 4,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_immed 0,iacc0l - test_spr_immed 1,iacc0h -smu9: - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - smu gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_immed 0x00000001,iacc0l - test_spr_limmed 0x3fff,0xffff,iacc0h -smu10: - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - smu gr7,gr8 - test_gr_immed 2,gr8 - test_gr_immed -3,gr7 - test_spr_immed -6,iacc0l - test_spr_immed -1,iacc0h -smu11: - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 3,gr7 - test_spr_immed -6,iacc0l - test_spr_immed -1,iacc0h -smu12: - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 1,gr7 - test_spr_immed -2,iacc0l - test_spr_immed -1,iacc0h -smu13: - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - smu gr7,gr8 - test_gr_immed 1,gr8 - test_gr_immed -2,gr7 - test_spr_immed -2,iacc0l - test_spr_immed -1,iacc0h -smu14: - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 0,gr7 - test_spr_immed 0,iacc0l - test_spr_immed 0,iacc0h -smu15: - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - smu gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed -2,gr7 - test_spr_immed 0,iacc0l - test_spr_immed 0,iacc0h -smu16: - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x2000,0x0001,gr7 - test_spr_limmed 0xbfff,0xfffe,iacc0l - test_spr_limmed 0xffff,0xffff,iacc0h -smu17: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x8000,0x0000,iacc0l - test_spr_limmed 0xffff,0xffff,iacc0h -smu18: - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x4000,0x0001,gr7 - test_spr_limmed 0x7fff,0xfffe,iacc0l - test_spr_limmed 0xffff,0xffff,iacc0h -smu19: - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - smu gr7,gr8 - test_gr_immed -4,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l - test_spr_limmed 0xffff,0xffff,iacc0h -smu20: - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - smu gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x8000,0x0000,iacc0l - test_spr_limmed 0xc000,0x0000,iacc0h -smu21: - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -3,gr7 - test_spr_immed 6,iacc0l - test_spr_immed 0,iacc0h -smu22: - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -1,gr7 - test_spr_immed 2,iacc0l - test_spr_immed 0,iacc0h -smu23: - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - smu gr7,gr8 - test_gr_immed -1,gr8 - test_gr_immed -2,gr7 - test_spr_immed 2,iacc0l - test_spr_immed 0,iacc0h -smu24: - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0xc000,0x0001,gr7 - test_spr_limmed 0x7fff,0xfffe,iacc0l - test_spr_immed 0,iacc0h -smu25: - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0xc000,0x0000,gr7 - test_spr_limmed 0x8000,0x0000,iacc0l - test_spr_immed 0,iacc0h -smu26: - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - smu gr7,gr8 - test_gr_immed -4,gr8 - test_gr_limmed 0xc000,0x0000,gr7 - test_spr_immed 0x00000000,iacc0l - test_spr_immed 1,iacc0h -smu27: - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - smu gr7,gr8 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_limmed 0x8000,0x0001,gr7 - test_spr_immed 0x00000001,iacc0l - test_spr_limmed 0x3fff,0xffff,iacc0h -smu28: - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - smu gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr7 - test_spr_immed 0x00000000,iacc0l - test_spr_limmed 0x4000,0x0000,iacc0h - - pass diff --git a/sim/testsuite/sim/frv/fr400/subss.cgs b/sim/testsuite/sim/frv/fr400/subss.cgs deleted file mode 100644 index fcda589..0000000 --- a/sim/testsuite/sim/frv/fr400/subss.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# frv testcase for subss $GRi,$GRj,$GRk -# mach: fr405 fr450 - - .include "../testutils.inc" - - start - - .global sub -sub_no_saturate: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - subss gr8,gr7,gr8 - test_gr_immed 1,gr8 - - set_gr_immed 2,gr7 - set_gr_immed 1,gr8 - subss gr8,gr7,gr8 - test_gr_limmed 0xffff,0xffff,gr8 - -sub_saturate_neg: - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - subss gr8,gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_limmed 0xffff,0xfff0,gr8 - subss gr8,gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - -sub_saturate_pos: - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - subss gr8,gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x0010,gr8 - set_gr_limmed 0x8000,0x0000,gr7 - subss gr8,gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - - - pass diff --git a/sim/testsuite/sim/frv/fr400/udiv.cgs b/sim/testsuite/sim/frv/fr400/udiv.cgs deleted file mode 100644 index dd92bcd..0000000 --- a/sim/testsuite/sim/frv/fr400/udiv.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# frv testcase for udiv $GRi,$GRj,$GRk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global udiv -udiv: - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - udiv gr3,gr2,gr3 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x00000004,gr3 - - ; example 1 from udiv in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - udiv gr3,gr2,gr3 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_immed 0x000000e0,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr -e1: udiv gr1,gr0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr400/udivi.cgs b/sim/testsuite/sim/frv/fr400/udivi.cgs deleted file mode 100644 index 69a7937..0000000 --- a/sim/testsuite/sim/frv/fr400/udivi.cgs +++ /dev/null @@ -1,47 +0,0 @@ -# frv testcase for udivi $GRi,$s12,$GRk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global udivi -udivi: - ; simple division 12 / 3 - set_gr_immed 0x0000000c,gr3 - udivi gr3,3,gr3 - test_gr_immed 0x00000004,gr3 - - ; random example - set_gr_limmed 0xfedc,0xba98,gr3 - udivi gr3,0x7ff,gr3 - test_gr_limmed 0x001f,0xdf93,gr3 - - ; random example - set_gr_limmed 0xffff,0xffff,gr3 - udivi gr3,-2048,gr3 - test_gr_immed 1,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr -e1: udivi gr1,0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr500/allinsn.exp b/sim/testsuite/sim/frv/fr500/allinsn.exp deleted file mode 100644 index 7d19259..0000000 --- a/sim/testsuite/sim/frv/fr500/allinsn.exp +++ /dev/null @@ -1,19 +0,0 @@ -# FRV simulator testsuite. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "frv fr500 fr550" - set cpu_option -mcpu - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs b/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs deleted file mode 100644 index 9c88620..0000000 --- a/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs +++ /dev/null @@ -1,444 +0,0 @@ -# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global cmqaddhss -cmqaddhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc4,1 - cmqaddhss fr12,fr12,fr16,cc4,1 - test_fr_limmed 0x0002,0x0002,fr14 - test_fr_limmed 0xfffe,0xfffe,fr15 - test_fr_limmed 0x7fff,0x0000,fr16 - test_fr_limmed 0x0000,0x8000,fr17 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc5,0 - cmqaddhss fr12,fr12,fr16,cc5,0 - test_fr_limmed 0x0002,0x0002,fr14 - test_fr_limmed 0xfffe,0xfffe,fr15 - test_fr_limmed 0x7fff,0x0000,fr16 - test_fr_limmed 0x0000,0x8000,fr17 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc4,0 - cmqaddhss fr12,fr12,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc5,1 - cmqaddhss fr12,fr12,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc6,1 - cmqaddhss fr12,fr12,fr16,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set -; - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc7,1 - cmqaddhss fr12,fr12,fr16,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs b/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs deleted file mode 100644 index 5b29c9a..0000000 --- a/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs +++ /dev/null @@ -1,360 +0,0 @@ -# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global cmqaddhus -cmqaddhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x8000,0x7fff,fr14 - test_fr_limmed 0xffff,0xffff,fr15 - test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc4,1 - cmqaddhus fr12,fr12,fr16,cc4,1 - test_fr_limmed 0x0004,0x0002,fr14 - test_fr_limmed 0x0002,0x0002,fr15 - test_fr_limmed 0xffff,0xffff,fr16 - test_fr_limmed 0xffff,0xffff,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x8000,0x7fff,fr14 - test_fr_limmed 0xffff,0xffff,fr15 - test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc5,0 - cmqaddhus fr12,fr12,fr16,cc5,0 - test_fr_limmed 0x0004,0x0002,fr14 - test_fr_limmed 0x0002,0x0002,fr15 - test_fr_limmed 0xffff,0xffff,fr16 - test_fr_limmed 0xffff,0xffff,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc4,0 - cmqaddhus fr12,fr12,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc5,1 - cmqaddhus fr12,fr12,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc6,0 - cmqaddhus fr12,fr12,fr16,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc7,0 - cmqaddhus fr12,fr12,fr16,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs b/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs deleted file mode 100644 index 4dbee66..0000000 --- a/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs +++ /dev/null @@ -1,448 +0,0 @@ -# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global msubhss -msubhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0x4111,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x4111,0xdead,fr14 - test_fr_limmed 0x0123,0x4567,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x1235,0x5679,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc4,1 - cmqsubhss fr12,fr10,fr16,cc4,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x8000,0x8000,fr16 - test_fr_limmed 0x8001,0x8001,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0x4111,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x4111,0xdead,fr14 - test_fr_limmed 0x0123,0x4567,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x1235,0x5679,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc5,0 - cmqsubhss fr12,fr10,fr16,cc5,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x8000,0x8000,fr16 - test_fr_limmed 0x8001,0x8001,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc4,0 - cmqsubhss fr12,fr10,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc5,1 - cmqsubhss fr12,fr10,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc6,1 - cmqsubhss fr12,fr10,fr16,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc7,1 - cmqsubhss fr12,fr10,fr16,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs b/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs deleted file mode 100644 index f60ae98..0000000 --- a/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs +++ /dev/null @@ -1,370 +0,0 @@ -# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global cmqsubhus -cmqsubhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0123,0x4567,fr14 - test_fr_limmed 0x7ffc,0x7ffd,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc4,1 - cmqsubhus fr10,fr12,fr16,cc4,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x0001,0x0000,fr16 - test_fr_limmed 0x0000,0x0000,fr17 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0123,0x4567,fr14 - test_fr_limmed 0x7ffc,0x7ffd,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc5,0 - cmqsubhus fr10,fr12,fr16,cc5,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x0001,0x0000,fr16 - test_fr_limmed 0x0000,0x0000,fr17 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc4,0 - cmqsubhus fr10,fr12,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_fr_limmed 0x4444,0x4444,fr17 - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc5,1 - cmqsubhus fr10,fr12,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_fr_limmed 0x4444,0x4444,fr17 - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc6,0 - cmqsubhus fr10,fr12,fr16,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_fr_limmed 0x4444,0x4444,fr17 -; - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc7,0 - cmqsubhus fr10,fr12,fr16,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_fr_limmed 0x4444,0x4444,fr17 - - pass diff --git a/sim/testsuite/sim/frv/fr500/dcpl.cgs b/sim/testsuite/sim/frv/fr500/dcpl.cgs deleted file mode 100644 index c0c904c..0000000 --- a/sim/testsuite/sim/frv/fr500/dcpl.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# FRV testcase for dcpl GRi,GRj,lock -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global dcpl -dcpl: - or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode - - ; preload and lock all the lines in set 0 of the data cache - set_gr_immed 0x70000,gr10 - dcpl gr10,gr0,1 - set_mem_immed 0x11111111,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 1,gr11 - dcpl gr10,gr11,1 - set_mem_immed 0x22222222,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 63,gr11 - dcpl gr10,gr11,1 - set_mem_immed 0x33333333,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 64,gr11 - dcpl gr10,gr11,1 - set_mem_immed 0x44444444,gr10 - test_mem_immed 0x44444444,gr10 - - ; Now write to another address which should be in the same set - ; the write should go through to memory, since all the lines in the - ; set are locked - inc_gr_immed 0x1000,gr10 - set_mem_immed 0xdeadbeef,gr10 - test_mem_immed 0xdeadbeef,gr10 - - ; Invalidate the data cache. Only the last value stored should have made - ; it through to memory - set_gr_immed 0x70000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0xdeadbeef,gr10 - - pass diff --git a/sim/testsuite/sim/frv/fr500/dcul.cgs b/sim/testsuite/sim/frv/fr500/dcul.cgs deleted file mode 100644 index 1c5bd93..0000000 --- a/sim/testsuite/sim/frv/fr500/dcul.cgs +++ /dev/null @@ -1,118 +0,0 @@ -# FRV testcase for dcul GRi -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global dcul -dcul: - or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode - - ; preload and lock all the lines in set 0 of the data cache - set_gr_immed 0x70000,gr10 - lock_data_cache gr10 - set_mem_immed 0x11111111,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 1,gr11 - lock_data_cache gr10 - set_mem_immed 0x22222222,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 63,gr11 - lock_data_cache gr10 - set_mem_immed 0x33333333,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 64,gr11 - lock_data_cache gr10 - set_mem_immed 0x44444444,gr10 - test_mem_immed 0x44444444,gr10 - - ; Now write to another address which should be in the same set - ; the write should go through to memory, since all the lines in the - ; set are locked - inc_gr_immed 0x1000,gr10 - set_mem_immed 0xdeadbeef,gr10 - test_mem_immed 0xdeadbeef,gr10 - - ; Invalidate the data cache. Only the last value stored should have made - ; it through to memory - set_gr_immed 0x70000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0xdeadbeef,gr10 - - ; Now preload load and lock all the lines in set 0 of the data cache - ; again - set_gr_immed 0x70000,gr10 - lock_data_cache gr10 - set_mem_immed 0x11111111,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 1,gr11 - lock_data_cache gr10 - set_mem_immed 0x22222222,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 63,gr11 - lock_data_cache gr10 - set_mem_immed 0x33333333,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 64,gr11 - lock_data_cache gr10 - set_mem_immed 0x44444444,gr10 - test_mem_immed 0x44444444,gr10 - - ; unlock one line - set_gr_immed 0x72000,gr10 - dcul gr10 - - ; Now write to another address which should be in the same set. - set_gr_immed 0x75000,gr10 - set_mem_immed 0xbeefdead,gr10 - - ; All of the stored values should be retrievable - - set_gr_immed 0x70000,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x1000,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x1000,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x1000,gr10 - test_mem_immed 0x44444444,gr10 - - inc_gr_immed 0x1000,gr10 - test_mem_immed 0xdeadbeef,gr10 - - inc_gr_immed 0x1000,gr10 - test_mem_immed 0xbeefdead,gr10 - - pass diff --git a/sim/testsuite/sim/frv/fr500/mclracc.cgs b/sim/testsuite/sim/frv/fr500/mclracc.cgs deleted file mode 100644 index 43fcf75..0000000 --- a/sim/testsuite/sim/frv/fr500/mclracc.cgs +++ /dev/null @@ -1,79 +0,0 @@ -# frv testcase for mclracc $ACC40k,$A -# mach: all - - .include "../testutils.inc" - - start - - .global mclracc -mclracc: - set_accg_immed 0xff,accg0 - set_acc_immed -1,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed -1,acc1 - set_accg_immed 0xff,accg3 - set_acc_immed -1,acc3 - set_accg_immed 0xff,accg7 - set_acc_immed -1,acc7 - - mclracc acc8,0 ; nop - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0xff,accg3 - test_acc_immed -1,acc3 - test_accg_immed 0xff,accg7 - test_acc_immed -1,acc7 - - mclracc acc8,1 ; nop - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0xff,accg3 - test_acc_immed -1,acc3 - test_accg_immed 0xff,accg7 - test_acc_immed -1,acc7 - - mclracc acc3,0 - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0xff,accg7 - test_acc_immed -1,acc7 - - mclracc acc7,1 - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0,accg7 - test_acc_immed 0,acc7 - - mclracc acc0,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0,accg7 - test_acc_immed 0,acc7 - - mclracc acc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0,accg7 - test_acc_immed 0,acc7 - - pass diff --git a/sim/testsuite/sim/frv/fr500/mqaddhss.cgs b/sim/testsuite/sim/frv/fr500/mqaddhss.cgs deleted file mode 100644 index 7183a3f..0000000 --- a/sim/testsuite/sim/frv/fr500/mqaddhss.cgs +++ /dev/null @@ -1,79 +0,0 @@ -# frv testcase for mqaddhss $FRi,$FRj,$FRj -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global mqaddhss -mqaddhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - mqaddhss.p fr10,fr10,fr14 - mqaddhss fr12,fr12,fr16 - test_fr_limmed 0x0002,0x0002,fr14 - test_fr_limmed 0xfffe,0xfffe,fr15 - test_fr_limmed 0x7fff,0x0000,fr16 - test_fr_limmed 0x0000,0x8000,fr17 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr500/mqaddhus.cgs b/sim/testsuite/sim/frv/fr500/mqaddhus.cgs deleted file mode 100644 index 9faa109..0000000 --- a/sim/testsuite/sim/frv/fr500/mqaddhus.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# frv testcase for mqaddhus $FRi,$FRj,$FRj -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global mqaddhus -mqaddhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - mqaddhus fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - mqaddhus fr10,fr12,fr14 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - mqaddhus fr10,fr12,fr14 - test_fr_limmed 0x8000,0x7fff,fr14 - test_fr_limmed 0xffff,0xffff,fr15 - test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - mqaddhus.p fr10,fr10,fr14 - mqaddhus fr12,fr12,fr16 - test_fr_limmed 0x0004,0x0002,fr14 - test_fr_limmed 0x0002,0x0002,fr15 - test_fr_limmed 0xffff,0xffff,fr16 - test_fr_limmed 0xffff,0xffff,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr500/mqsubhss.cgs b/sim/testsuite/sim/frv/fr500/mqsubhss.cgs deleted file mode 100644 index 74d5a87..0000000 --- a/sim/testsuite/sim/frv/fr500/mqsubhss.cgs +++ /dev/null @@ -1,79 +0,0 @@ -# frv testcase for mqsubhss $FRi,$FRj,$FRj -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global msubhss -msubhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0x4111,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x4111,0xdead,fr14 - test_fr_limmed 0x0123,0x4567,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x1235,0x5679,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - mqsubhss.p fr10,fr10,fr14 - mqsubhss fr12,fr10,fr16 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x8000,0x8000,fr16 - test_fr_limmed 0x8001,0x8001,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr500/mqsubhus.cgs b/sim/testsuite/sim/frv/fr500/mqsubhus.cgs deleted file mode 100644 index 44aa7a9..0000000 --- a/sim/testsuite/sim/frv/fr500/mqsubhus.cgs +++ /dev/null @@ -1,66 +0,0 @@ -# frv testcase for msubhus $FRi,$FRj,$FRj -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global msubhus -msubhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - mqsubhus fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqsubhus fr10,fr12,fr14 - test_fr_limmed 0x0123,0x4567,fr14 - test_fr_limmed 0x7ffc,0x7ffd,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqsubhus fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - mqsubhus.p fr10,fr10,fr14 - mqsubhus fr10,fr12,fr16 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x0001,0x0000,fr16 - test_fr_limmed 0x0000,0x0000,fr17 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/allinsn.exp b/sim/testsuite/sim/frv/fr550/allinsn.exp deleted file mode 100644 index 1fe1795..0000000 --- a/sim/testsuite/sim/frv/fr550/allinsn.exp +++ /dev/null @@ -1,19 +0,0 @@ -# FRV simulator testsuite. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "fr550" - set cpu_option -mcpu - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/fr550/cmaddhss.cgs b/sim/testsuite/sim/frv/fr550/cmaddhss.cgs deleted file mode 100644 index 174a3dc..0000000 --- a/sim/testsuite/sim/frv/fr550/cmaddhss.cgs +++ /dev/null @@ -1,547 +0,0 @@ -# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global maddhss -maddhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,1 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc4,1 - cmaddhss fr11,fr11,fr13,cc4,1 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc5,0 - cmaddhss fr11,fr11,fr13,cc5,0 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc4,0 - cmaddhss fr11,fr11,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc5,1 - cmaddhss fr11,fr11,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc6,1 - cmaddhss fr11,fr11,fr13,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set -; - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc7,1 - cmaddhss fr11,fr11,fr13,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmaddhus.cgs b/sim/testsuite/sim/frv/fr550/cmaddhus.cgs deleted file mode 100644 index 40e1152..0000000 --- a/sim/testsuite/sim/frv/fr550/cmaddhus.cgs +++ /dev/null @@ -1,481 +0,0 @@ -# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmaddhus -cmaddhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x7fff,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc4,1 - cmaddhus fr11,fr11,fr13,cc4,1 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0xffff,0xffff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x7fff,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc5,0 - cmaddhus fr11,fr11,fr13,cc5,0 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0xffff,0xffff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc4,0 - cmaddhus fr11,fr11,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc5,1 - cmaddhus fr11,fr11,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc6,0 - cmaddhus fr11,fr11,fr13,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc7,0 - cmaddhus fr11,fr11,fr13,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs b/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs deleted file mode 100644 index 341949b..0000000 --- a/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs +++ /dev/null @@ -1,492 +0,0 @@ -# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmcpxiu -cmcpxiu: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 5,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7fff,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8001,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0x00010001,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 1,accg0 - test_acc_immed 0xfffb0003,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 1,accg0 - test_acc_immed 0xfffc0002,acc0 - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 5,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7fff,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8001,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0x00010001,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 1,accg0 - test_acc_immed 0xfffb0003,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 1,accg0 - test_acc_immed 0xfffc0002,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmcpxru.cgs b/sim/testsuite/sim/frv/fr550/cmcpxru.cgs deleted file mode 100644 index 3eeb0a0..0000000 --- a/sim/testsuite/sim/frv/fr550/cmcpxru.cgs +++ /dev/null @@ -1,528 +0,0 @@ -# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmcpxru -cmcpxru: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 14,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffd,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xffff,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0x0001ffff,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 14,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffd,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xffff,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0x0001ffff,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 -; - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmmachs.cgs b/sim/testsuite/sim/frv/fr550/cmmachs.cgs deleted file mode 100644 index f716867..0000000 --- a/sim/testsuite/sim/frv/fr550/cmmachs.cgs +++ /dev/null @@ -1,1545 +0,0 @@ -# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmmachs -cmmachs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_spr_immed 0x0,msr0 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0007,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0001,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xbffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xbffd,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffd,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc003,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc005,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc005,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3ffec006,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x7ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x7ffec006,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc4,1 -;;;;;;;;;;;; - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed -128,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed -128,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_accg_immed 0x0,accg0 ; saturation - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0007,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0001,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xbffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xbffd,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffd,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc003,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc005,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc005,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3ffec006,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x7ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x7ffec006,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 -; - ; Positive operands - set_spr_immed 0x0,msr0 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmmachu.cgs b/sim/testsuite/sim/frv/fr550/cmmachu.cgs deleted file mode 100644 index 176d1b1..0000000 --- a/sim/testsuite/sim/frv/fr550/cmmachu.cgs +++ /dev/null @@ -1,858 +0,0 @@ -# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmmachu -cmmachu: - set_spr_immed 0x1b1b,cccr - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x00020006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00020006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x40010007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40010007,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x8001,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x8001,0x0007,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x7fff,0x0008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x7fff,0x0008,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x00020006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00020006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x40010007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40010007,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x8001,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x8001,0x0007,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x7fff,0x0008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x7fff,0x0008,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 -; - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs b/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs deleted file mode 100644 index 3d32bec..0000000 --- a/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs +++ /dev/null @@ -1,429 +0,0 @@ -# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmqaddhss -cmqaddhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc4,1 - cmqaddhss fr12,fr12,fr16,cc4,1 - test_fr_limmed 0x0002,0x0002,fr14 - test_fr_limmed 0xfffe,0xfffe,fr15 - test_fr_limmed 0x7fff,0x0000,fr16 - test_fr_limmed 0x0000,0x8000,fr17 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc5,0 - cmqaddhss fr12,fr12,fr16,cc5,0 - test_fr_limmed 0x0002,0x0002,fr14 - test_fr_limmed 0xfffe,0xfffe,fr15 - test_fr_limmed 0x7fff,0x0000,fr16 - test_fr_limmed 0x0000,0x8000,fr17 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc4,0 - cmqaddhss fr12,fr12,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc5,1 - cmqaddhss fr12,fr12,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc6,1 - cmqaddhss fr12,fr12,fr16,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set -; - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc7,1 - cmqaddhss fr12,fr12,fr16,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs b/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs deleted file mode 100644 index 4e25ba4..0000000 --- a/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs +++ /dev/null @@ -1,345 +0,0 @@ -# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmqaddhus -cmqaddhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x8000,0x7fff,fr14 - test_fr_limmed 0xffff,0xffff,fr15 - test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc4,1 - cmqaddhus fr12,fr12,fr16,cc4,1 - test_fr_limmed 0x0004,0x0002,fr14 - test_fr_limmed 0x0002,0x0002,fr15 - test_fr_limmed 0xffff,0xffff,fr16 - test_fr_limmed 0xffff,0xffff,fr17 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x8000,0x7fff,fr14 - test_fr_limmed 0xffff,0xffff,fr15 - test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc5,0 - cmqaddhus fr12,fr12,fr16,cc5,0 - test_fr_limmed 0x0004,0x0002,fr14 - test_fr_limmed 0x0002,0x0002,fr15 - test_fr_limmed 0xffff,0xffff,fr16 - test_fr_limmed 0xffff,0xffff,fr17 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc4,0 - cmqaddhus fr12,fr12,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc5,1 - cmqaddhus fr12,fr12,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc6,0 - cmqaddhus fr12,fr12,fr16,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc7,0 - cmqaddhus fr12,fr12,fr16,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmqmachs.cgs b/sim/testsuite/sim/frv/fr550/cmqmachs.cgs deleted file mode 100644 index 0aee4f0..0000000 --- a/sim/testsuite/sim/frv/fr550/cmqmachs.cgs +++ /dev/null @@ -1,1262 +0,0 @@ -# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmqmachs -cmqmachs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 -; - ; Positive operands - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/cmqmachu.cgs b/sim/testsuite/sim/frv/fr550/cmqmachu.cgs deleted file mode 100644 index 8b880f8..0000000 --- a/sim/testsuite/sim/frv/fr550/cmqmachu.cgs +++ /dev/null @@ -1,870 +0,0 @@ -# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmqmachu -cmqmachu: - set_spr_immed 0x1b1b,cccr - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8000,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00018000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00018000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff8007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff8007,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4001,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4001,0x8000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x3ffd,0x8008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x3ffd,0x8008,acc1 - test_accg_immed 1,accg2 - test_acc_limmed 0x3fff,0x8001,acc2 - test_accg_immed 1,accg3 - test_acc_limmed 0x3fff,0x8001,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8000,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00018000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00018000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff8007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff8007,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4001,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4001,0x8000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x3ffd,0x8008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x3ffd,0x8008,acc1 - test_accg_immed 1,accg2 - test_acc_limmed 0x3fff,0x8001,acc2 - test_accg_immed 1,accg3 - test_acc_limmed 0x3fff,0x8001,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 -; - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs b/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs deleted file mode 100644 index 490b449..0000000 --- a/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs +++ /dev/null @@ -1,429 +0,0 @@ -# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global msubhss -msubhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0x4111,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x4111,0xdead,fr14 - test_fr_limmed 0x0123,0x4567,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x1235,0x5679,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc4,1 - cmqsubhss fr12,fr10,fr16,cc4,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x8000,0x8000,fr16 - test_fr_limmed 0x8001,0x8001,fr17 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0x4111,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x4111,0xdead,fr14 - test_fr_limmed 0x0123,0x4567,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x1235,0x5679,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc5,0 - cmqsubhss fr12,fr10,fr16,cc5,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x8000,0x8000,fr16 - test_fr_limmed 0x8001,0x8001,fr17 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf not set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc4,0 - cmqsubhss fr12,fr10,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc5,1 - cmqsubhss fr12,fr10,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc6,1 - cmqsubhss fr12,fr10,fr16,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc7,1 - cmqsubhss fr12,fr10,fr16,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs b/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs deleted file mode 100644 index 90bd89a..0000000 --- a/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs +++ /dev/null @@ -1,351 +0,0 @@ -# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmqsubhus -cmqsubhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0123,0x4567,fr14 - test_fr_limmed 0x7ffc,0x7ffd,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc4,1 - cmqsubhus fr10,fr12,fr16,cc4,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x0001,0x0000,fr16 - test_fr_limmed 0x0000,0x0000,fr17 - test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0123,0x4567,fr14 - test_fr_limmed 0x7ffc,0x7ffd,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc5,0 - cmqsubhus fr10,fr12,fr16,cc5,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x0001,0x0000,fr16 - test_fr_limmed 0x0000,0x0000,fr17 - test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc4,0 - cmqsubhus fr10,fr12,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_fr_limmed 0x4444,0x4444,fr17 - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc5,1 - cmqsubhus fr10,fr12,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_fr_limmed 0x4444,0x4444,fr17 - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc6,0 - cmqsubhus fr10,fr12,fr16,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_fr_limmed 0x4444,0x4444,fr17 -; - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc7,0 - cmqsubhus fr10,fr12,fr16,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_fr_limmed 0x4444,0x4444,fr17 - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmsubhss.cgs b/sim/testsuite/sim/frv/fr550/cmsubhss.cgs deleted file mode 100644 index 9370d54..0000000 --- a/sim/testsuite/sim/frv/fr550/cmsubhss.cgs +++ /dev/null @@ -1,547 +0,0 @@ -# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmsubhss -cmsubhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0x4111,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x4111,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x1235,0x5679,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc4,1 - cmsubhss fr11,fr10,fr13,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x8000,0x8000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0x4111,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x4111,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x1235,0x5679,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc5,0 - cmsubhss fr11,fr10,fr13,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x8000,0x8000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc4,0 - cmsubhss fr11,fr10,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc5,1 - cmsubhss fr11,fr10,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc6,1 - cmsubhss fr11,fr10,fr13,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set -; - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc7,1 - cmsubhss fr11,fr10,fr13,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmsubhus.cgs b/sim/testsuite/sim/frv/fr550/cmsubhus.cgs deleted file mode 100644 index 5cf676b..0000000 --- a/sim/testsuite/sim/frv/fr550/cmsubhus.cgs +++ /dev/null @@ -1,427 +0,0 @@ -# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmsubhus -cmsubhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc4,1 - cmsubhus fr10,fr11,fr13,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc5,0 - cmsubhus fr10,fr11,fr13,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc4,0 - cmsubhus fr10,fr11,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc5,1 - cmsubhus fr10,fr11,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc6,0 - cmsubhus fr10,fr11,fr13,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set -; - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc7,0 - cmsubhus fr10,fr11,fr13,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/dcpl.cgs b/sim/testsuite/sim/frv/fr550/dcpl.cgs deleted file mode 100644 index 93c659a..0000000 --- a/sim/testsuite/sim/frv/fr550/dcpl.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# FRV testcase for dcpl GRi,GRj,lock -# mach: all - - .include "../testutils.inc" - - start - - .global dcpl -dcpl: - or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode - - ; preload and lock all the lines in set 0 of the data cache - set_gr_immed 0x70000,gr10 - dcpl gr10,gr0,1 - set_mem_immed 0x11111111,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 1,gr11 - dcpl gr10,gr11,1 - set_mem_immed 0x22222222,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 63,gr11 - dcpl gr10,gr11,1 - set_mem_immed 0x33333333,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 64,gr11 - dcpl gr10,gr11,1 - set_mem_immed 0x44444444,gr10 - test_mem_immed 0x44444444,gr10 - - ; Now write to another address which should be in the same set - ; the write should go through to memory, since all the lines in the - ; set are locked - inc_gr_immed 0x2000,gr10 - set_mem_immed 0xdeadbeef,gr10 - test_mem_immed 0xdeadbeef,gr10 - - ; Invalidate the data cache. Only the last value stored should have made - ; it through to memory - set_gr_immed 0x70000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0xdeadbeef,gr10 - - pass diff --git a/sim/testsuite/sim/frv/fr550/dcul.cgs b/sim/testsuite/sim/frv/fr550/dcul.cgs deleted file mode 100644 index a3bd4be..0000000 --- a/sim/testsuite/sim/frv/fr550/dcul.cgs +++ /dev/null @@ -1,118 +0,0 @@ -# FRV testcase for dcul GRi -# mach: all - - .include "../testutils.inc" - - start - - .global dcul -dcul: - or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode - - ; preload and lock all the lines in set 0 of the data cache - set_gr_immed 0x70000,gr10 - lock_data_cache gr10 - set_mem_immed 0x11111111,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 1,gr11 - lock_data_cache gr10 - set_mem_immed 0x22222222,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 63,gr11 - lock_data_cache gr10 - set_mem_immed 0x33333333,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 64,gr11 - lock_data_cache gr10 - set_mem_immed 0x44444444,gr10 - test_mem_immed 0x44444444,gr10 - - ; Now write to another address which should be in the same set - ; the write should go through to memory, since all the lines in the - ; set are locked - inc_gr_immed 0x2000,gr10 - set_mem_immed 0xdeadbeef,gr10 - test_mem_immed 0xdeadbeef,gr10 - - ; Invalidate the data cache. Only the last value stored should have made - ; it through to memory - set_gr_immed 0x70000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0xdeadbeef,gr10 - - ; Now preload load and lock all the lines in set 0 of the data cache - ; again - set_gr_immed 0x70000,gr10 - lock_data_cache gr10 - set_mem_immed 0x11111111,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 1,gr11 - lock_data_cache gr10 - set_mem_immed 0x22222222,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 63,gr11 - lock_data_cache gr10 - set_mem_immed 0x33333333,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 64,gr11 - lock_data_cache gr10 - set_mem_immed 0x44444444,gr10 - test_mem_immed 0x44444444,gr10 - - ; unlock one line - set_gr_immed 0x78000,gr10 - dcul gr10 - - ; Now write to another address which should be in the same set. - set_gr_immed 0x7a000,gr10 - set_mem_immed 0xbeefdead,gr10 - - ; All of the stored values should be retrievable - - set_gr_immed 0x70000,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x2000,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x2000,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x2000,gr10 - test_mem_immed 0x44444444,gr10 - - inc_gr_immed 0x2000,gr10 - test_mem_immed 0xdeadbeef,gr10 - - inc_gr_immed 0x2000,gr10 - test_mem_immed 0xbeefdead,gr10 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mabshs.cgs b/sim/testsuite/sim/frv/fr550/mabshs.cgs deleted file mode 100644 index 9168df8..0000000 --- a/sim/testsuite/sim/frv/fr550/mabshs.cgs +++ /dev/null @@ -1,64 +0,0 @@ -# frv testcase for mabshs $FRj,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mabshs -mabshs: - set_fr_iimmed 0x0000,0x0000,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x0000,0x0000,fr11 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0xffff,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x0001,0x0001,fr11 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7fff,0x8001,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x7fff,0x7fff,fr11 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7fff,0x8000,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x7fff,0x7fff,fr11 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8000,0x7fff,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x7fff,0x7fff,fr11 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - mabshs.p fr10,fr12 - mabshs fr11,fr13 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/maddaccs.cgs b/sim/testsuite/sim/frv/fr550/maddaccs.cgs deleted file mode 100644 index 262a148..0000000 --- a/sim/testsuite/sim/frv/fr550/maddaccs.cgs +++ /dev/null @@ -1,128 +0,0 @@ -# frv testcase for maddaccs $ACC40Si,$ACC40Sk -# mach: all - - .include "../testutils.inc" - - start - - .global maddaccs -maddaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0xdead,0xbeef,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0xbeef,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0x2345,0x6789,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg4 - set_acc_immed 0x00000001,acc4 - set_accg_immed 0x7f,accg5 - set_acc_immed 0xffffffff,acc5 - maddaccs.p acc0,acc1 - maddaccs acc4,acc5 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0x7f,accg5 - test_acc_limmed 0xffff,0xffff,acc5 - - pass diff --git a/sim/testsuite/sim/frv/fr550/maddhss.cgs b/sim/testsuite/sim/frv/fr550/maddhss.cgs deleted file mode 100644 index 8c5c714..0000000 --- a/sim/testsuite/sim/frv/fr550/maddhss.cgs +++ /dev/null @@ -1,97 +0,0 @@ -# frv testcase for maddhss $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global maddhss -maddhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maddhss fr10,fr11,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maddhss.p fr10,fr10,fr12 - maddhss fr11,fr11,fr13 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/maddhus.cgs b/sim/testsuite/sim/frv/fr550/maddhus.cgs deleted file mode 100644 index 93d06bd..0000000 --- a/sim/testsuite/sim/frv/fr550/maddhus.cgs +++ /dev/null @@ -1,86 +0,0 @@ -# frv testcase for maddhus $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global maddhus -maddhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0x8000,0x7fff,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - maddhus.p fr10,fr10,fr12 - maddhus fr11,fr11,fr13 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0xffff,0xffff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/masaccs.cgs b/sim/testsuite/sim/frv/fr550/masaccs.cgs deleted file mode 100644 index 9595d16..0000000 --- a/sim/testsuite/sim/frv/fr550/masaccs.cgs +++ /dev/null @@ -1,148 +0,0 @@ -# frv testcase for masaccs $ACC40Si,$ACC40Sk -# mach: all - - .include "../testutils.inc" - - start - - .global masaccs -masaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0xdead,0xbeef,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0xbeef,0xdead,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0x4111,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x2345,0x6789,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set - test_accg_immed 1,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xfffc,0x7ffd,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0003,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg4 - set_acc_immed 0x00000001,acc4 - set_accg_immed 0x7f,accg5 - set_acc_immed 0xffffffff,acc5 - masaccs.p acc0,acc0 - masaccs acc4,acc4 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg4 - test_acc_limmed 0xffff,0xffff,acc4 - test_accg_immed 0x80,accg5 - test_acc_limmed 0x0000,0x0002,acc5 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs b/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs deleted file mode 100644 index 92d23d0..0000000 --- a/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs +++ /dev/null @@ -1,102 +0,0 @@ -# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk -# mach: all - - .include "../testutils.inc" - - start - - .global mdaddaccs -mdaddaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0xdead0000,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x0000beef,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdead,0xbeef,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x11111111,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0xbeef,0xdead,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x2345,0x6789,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - set_accg_immed 0x80,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xfffffffe,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0002,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mdasaccs.cgs b/sim/testsuite/sim/frv/fr550/mdasaccs.cgs deleted file mode 100644 index 8821621..0000000 --- a/sim/testsuite/sim/frv/fr550/mdasaccs.cgs +++ /dev/null @@ -1,122 +0,0 @@ -# frv testcase for mdasaccs $ACC40Si,$ACC40Sk -# mach: all - - .include "../testutils.inc" - - start - - .global mdasaccs -mdasaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0xdead0000,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x0000beef,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0xdead,0xbeef,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x11111111,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0xbeef,0xdead,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0x4111,0xdead,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x2345,0x6789,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x1234,0x5677,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0x1234,0x5679,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - set_accg_immed 0x80,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xfffffffe,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0xa,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xfffc,0x7ffd,acc1 - test_accg_immed 0x80,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0003,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs b/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs deleted file mode 100644 index 1fe7498..0000000 --- a/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs +++ /dev/null @@ -1,102 +0,0 @@ -# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk -# mach: all - - .include "../testutils.inc" - - start - - .global mdsubaccs -mdsubaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0xdead0000,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x0000beef,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x11111111,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg2 - test_acc_limmed 0x4111,0xdead,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg2 - test_acc_limmed 0x1234,0x5679,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffffffe,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - set_accg_immed 0x80,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x00000002,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0x00000000,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mmachs.cgs b/sim/testsuite/sim/frv/fr550/mmachs.cgs deleted file mode 100644 index 9014076..0000000 --- a/sim/testsuite/sim/frv/fr550/mmachs.cgs +++ /dev/null @@ -1,259 +0,0 @@ -# frv testcase for mmachs $GRi,$GRj,$ACCk -# mach: all - - .include "../testutils.inc" - - start - - .global mmachs -mmachs: - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0007,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0001,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xbffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xbffd,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffd,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc003,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc005,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc005,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3ffec006,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x7ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x7ffec006,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - mmachs fr7,fr8,acc0 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/mmachu.cgs b/sim/testsuite/sim/frv/fr550/mmachu.cgs deleted file mode 100644 index cd5c03c..0000000 --- a/sim/testsuite/sim/frv/fr550/mmachu.cgs +++ /dev/null @@ -1,146 +0,0 @@ -# frv testcase for mmachu $GRi,$GRj,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global mmachu -mmachu: - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x00020006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00020006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x40010007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40010007,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x8001,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x8001,0x0007,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x7fff,0x0008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x7fff,0x0008,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mmrdhs.cgs b/sim/testsuite/sim/frv/fr550/mmrdhs.cgs deleted file mode 100644 index 1aeb1b5..0000000 --- a/sim/testsuite/sim/frv/fr550/mmrdhs.cgs +++ /dev/null @@ -1,263 +0,0 @@ -# frv testcase for mmrdhs $GRi,$GRj,$ACCk -# mach: all - - .include "../testutils.inc" - - start - - .global mmrdhs -mmrdhs: - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_immed -8,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x7ffa,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xfffe,0xfffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xfffe,0xfffa,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xbfff,0xfff9,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xbfff,0xfff9,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xbfff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xbfff,0xffff,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x0001,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x0001,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x0001,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x0001,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x4003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x4003,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0xc003,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x4003,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x4003,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x3ffd,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x3ffb,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x3ffb,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_immed 0xc0013ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xc0013ffa,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_immed 0x80013ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0x80013ffa,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 0xffff,1,fr7 - set_fr_iimmed 1,0xffff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x8000,0x0000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0,1,fr7 - set_fr_iimmed 1,1,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/mmrdhu.cgs b/sim/testsuite/sim/frv/fr550/mmrdhu.cgs deleted file mode 100644 index 99378bc..0000000 --- a/sim/testsuite/sim/frv/fr550/mmrdhu.cgs +++ /dev/null @@ -1,151 +0,0 @@ -# frv testcase for mmrdhu $GRi,$GRj,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global mmrdhu -mmrdhu: - set_accg_immed 0x80,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_immed 0xfffffffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xfffffffa,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_immed 0xfffffff8,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xfffffff8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_immed 0xfffffff8,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xfffffff8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0x7ffa,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xfffe,0xfffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xfffe,0xfffa,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xfffd,0xfffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xfffd,0xfffa,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xbffe,0xfff9,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xbffe,0xfff9,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0x7ffe,0xfff9,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0x7ffe,0xfff9,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7e,accg0 - test_acc_limmed 0x8000,0xfff8,acc0 - test_accg_immed 0x7e,accg1 - test_acc_limmed 0x8000,0xfff8,acc1 - - set_accg_immed 0,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0xffff,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mqaddhss.cgs b/sim/testsuite/sim/frv/fr550/mqaddhss.cgs deleted file mode 100644 index b0c7853..0000000 --- a/sim/testsuite/sim/frv/fr550/mqaddhss.cgs +++ /dev/null @@ -1,76 +0,0 @@ -# frv testcase for mqaddhss $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global mqaddhss -mqaddhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - mqaddhss.p fr10,fr10,fr14 - mqaddhss fr12,fr12,fr16 - test_fr_limmed 0x0002,0x0002,fr14 - test_fr_limmed 0xfffe,0xfffe,fr15 - test_fr_limmed 0x7fff,0x0000,fr16 - test_fr_limmed 0x0000,0x8000,fr17 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/mqaddhus.cgs b/sim/testsuite/sim/frv/fr550/mqaddhus.cgs deleted file mode 100644 index 7f8b755..0000000 --- a/sim/testsuite/sim/frv/fr550/mqaddhus.cgs +++ /dev/null @@ -1,62 +0,0 @@ -# frv testcase for mqaddhus $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global mqaddhus -mqaddhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - mqaddhus fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - mqaddhus fr10,fr12,fr14 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - mqaddhus fr10,fr12,fr14 - test_fr_limmed 0x8000,0x7fff,fr14 - test_fr_limmed 0xffff,0xffff,fr15 - test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - mqaddhus.p fr10,fr10,fr14 - mqaddhus fr12,fr12,fr16 - test_fr_limmed 0x0004,0x0002,fr14 - test_fr_limmed 0x0002,0x0002,fr15 - test_fr_limmed 0xffff,0xffff,fr16 - test_fr_limmed 0xffff,0xffff,fr17 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/mqmachs.cgs b/sim/testsuite/sim/frv/fr550/mqmachs.cgs deleted file mode 100644 index 2f18620..0000000 --- a/sim/testsuite/sim/frv/fr550/mqmachs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqmachs $GRi,$GRj,$ACCk -# mach: all - - .include "../testutils.inc" - - start - - .global mqmachs -mqmachs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/mqmachu.cgs b/sim/testsuite/sim/frv/fr550/mqmachu.cgs deleted file mode 100644 index 71cba98..0000000 --- a/sim/testsuite/sim/frv/fr550/mqmachu.cgs +++ /dev/null @@ -1,144 +0,0 @@ -# frv testcase for mqmachu $GRi,$GRj,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global mqmachu -mqmachu: - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8000,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00018000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00018000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff8007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff8007,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4001,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4001,0x8000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x3ffd,0x8008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x3ffd,0x8008,acc1 - test_accg_immed 1,accg2 - test_acc_limmed 0x3fff,0x8001,acc2 - test_accg_immed 1,accg3 - test_acc_limmed 0x3fff,0x8001,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs b/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs deleted file mode 100644 index aded33e..0000000 --- a/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqmacxhs $GRi,$GRj,$ACCk -# mach: all - - .include "../testutils.inc" - - start - - .global mqmacxhs -mqmacxhs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 0,2,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 2,1,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x4000,2,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 2,0xfffd,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0xfffe,0,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0x2001,0xfffe,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0x4000,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x7fff,0x8000,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffe,0xfffd,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 0xffff,1,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/mqsubhss.cgs b/sim/testsuite/sim/frv/fr550/mqsubhss.cgs deleted file mode 100644 index a8936e9..0000000 --- a/sim/testsuite/sim/frv/fr550/mqsubhss.cgs +++ /dev/null @@ -1,76 +0,0 @@ -# frv testcase for mqsubhss $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global msubhss -msubhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0x4111,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x4111,0xdead,fr14 - test_fr_limmed 0x0123,0x4567,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x1235,0x5679,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - mqsubhss.p fr10,fr10,fr14 - mqsubhss fr12,fr10,fr16 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x8000,0x8000,fr16 - test_fr_limmed 0x8001,0x8001,fr17 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/mqsubhus.cgs b/sim/testsuite/sim/frv/fr550/mqsubhus.cgs deleted file mode 100644 index fc92eb5..0000000 --- a/sim/testsuite/sim/frv/fr550/mqsubhus.cgs +++ /dev/null @@ -1,63 +0,0 @@ -# frv testcase for msubhus $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global msubhus -msubhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - mqsubhus fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqsubhus fr10,fr12,fr14 - test_fr_limmed 0x0123,0x4567,fr14 - test_fr_limmed 0x7ffc,0x7ffd,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqsubhus fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - mqsubhus.p fr10,fr10,fr14 - mqsubhus fr10,fr12,fr16 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x0001,0x0000,fr16 - test_fr_limmed 0x0000,0x0000,fr17 - test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/mqxmachs.cgs b/sim/testsuite/sim/frv/fr550/mqxmachs.cgs deleted file mode 100644 index 3c08e41..0000000 --- a/sim/testsuite/sim/frv/fr550/mqxmachs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqxmachs $GRi,$GRj,$ACCk -# mach: all - - .include "../testutils.inc" - - start - - .global mqxmachs -mqxmachs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_immed 6,acc2 - test_accg_immed 0,accg3 - test_acc_immed 6,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_immed 8,acc2 - test_accg_immed 0,accg3 - test_acc_immed 8,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8008,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7fff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7fff,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7ffd,acc1 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffb,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffb,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffb,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffb,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0008,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_immed 0x3fff0009,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fff0009,acc3 - test_accg_immed 0,accg0 - test_acc_immed 0x3fffbffd,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fffbffd,acc1 - - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs b/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs deleted file mode 100644 index 32b043b..0000000 --- a/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk -# mach: all - - .include "../testutils.inc" - - start - - .global mqxmacxhs -mqxmacxhs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 0,2,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_immed 6,acc2 - test_accg_immed 0,accg3 - test_acc_immed 6,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 2,1,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_immed 8,acc2 - test_accg_immed 0,accg3 - test_acc_immed 8,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x4000,2,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8008,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7fff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7fff,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 2,0xfffd,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7ffd,acc1 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0xfffe,0,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0x2001,0xfffe,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffb,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffb,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0x4000,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x7fff,0x8000,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffb,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffb,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffe,0xfffd,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0008,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_immed 0x3fff0009,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fff0009,acc3 - test_accg_immed 0,accg0 - test_acc_immed 0x3fffbffd,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fffbffd,acc1 - - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 0xffff,1,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/msubaccs.cgs b/sim/testsuite/sim/frv/fr550/msubaccs.cgs deleted file mode 100644 index eeaf4a6..0000000 --- a/sim/testsuite/sim/frv/fr550/msubaccs.cgs +++ /dev/null @@ -1,128 +0,0 @@ -# frv testcase for msubaccs $ACC40Si,$ACC40Sk -# mach: all - - .include "../testutils.inc" - - start - - .global msubaccs -msubaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg3 - test_acc_limmed 0x4111,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffffffe,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000002,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg4 - set_acc_immed 0x00000001,acc4 - set_accg_immed 0x80,accg5 - set_acc_immed 0x00000000,acc5 - msubaccs.p acc0,acc1 - msubaccs acc4,acc5 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg5 - test_acc_limmed 0xffff,0xffff,acc5 - - pass diff --git a/sim/testsuite/sim/frv/fr550/msubhss.cgs b/sim/testsuite/sim/frv/fr550/msubhss.cgs deleted file mode 100644 index 6beb676..0000000 --- a/sim/testsuite/sim/frv/fr550/msubhss.cgs +++ /dev/null @@ -1,97 +0,0 @@ -# frv testcase for msubhss $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global msubhss -msubhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0xdead,0x4111,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x4111,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x1235,0x5679,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - msubhss.p fr10,fr10,fr12 - msubhss fr11,fr10,fr13 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x8000,0x8000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/msubhus.cgs b/sim/testsuite/sim/frv/fr550/msubhus.cgs deleted file mode 100644 index 5a3cd26..0000000 --- a/sim/testsuite/sim/frv/fr550/msubhus.cgs +++ /dev/null @@ -1,77 +0,0 @@ -# frv testcase for msubhus $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global msubhus -msubhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - msubhus.p fr10,fr10,fr12 - msubhus fr10,fr11,fr13 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/mtrap.cgs b/sim/testsuite/sim/frv/fr550/mtrap.cgs deleted file mode 100644 index 83dca7b..0000000 --- a/sim/testsuite/sim/frv/fr550/mtrap.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for mp_exception -# mach: all - - .include "../testutils.inc" - - start - - .global mp_exception -mpx: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 0x0e0,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_psr_et 1 - set_gr_immed 0,gr5 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - mtrap ; generate interrupt - test_gr_immed 1,gr5 - - and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields - mcmpsh fr10,fr11,fcc0 ; no exception - test_spr_bits 0x7000,12,1,msr0; msr0.mtt is always set - mtrap ; nop - test_gr_immed 1,gr5 - - pass - -; exception handler -ok1: - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - inc_gr_immed 1,gr5 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr550/udiv.cgs b/sim/testsuite/sim/frv/fr550/udiv.cgs deleted file mode 100644 index 05cbde4..0000000 --- a/sim/testsuite/sim/frv/fr550/udiv.cgs +++ /dev/null @@ -1,48 +0,0 @@ -# frv testcase for udiv $GRi,$GRj,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global udiv -udiv: - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - udiv gr3,gr2,gr3 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x00000004,gr3 - - ; example 1 from udiv in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - udiv gr3,gr2,gr3 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_immed 0x000000e0,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr - set_gr_addr e1,gr17 -e1: udiv gr1,gr0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr550/udivi.cgs b/sim/testsuite/sim/frv/fr550/udivi.cgs deleted file mode 100644 index d5ee1c4..0000000 --- a/sim/testsuite/sim/frv/fr550/udivi.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for udivi $GRi,$s12,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global udivi -udivi: - ; simple division 12 / 3 - set_gr_immed 0x0000000c,gr3 - udivi gr3,3,gr3 - test_gr_immed 0x00000004,gr3 - - ; random example - set_gr_limmed 0xfedc,0xba98,gr3 - udivi gr3,0x7ff,gr3 - test_gr_limmed 0x001f,0xdf93,gr3 - - ; random example - set_gr_limmed 0xffff,0xffff,gr3 - udivi gr3,-2048,gr3 - test_gr_immed 1,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr - set_gr_addr e1,gr17 -e1: udivi gr1,0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fsqrtd.cgs b/sim/testsuite/sim/frv/fsqrtd.cgs deleted file mode 100644 index a428b01..0000000 --- a/sim/testsuite/sim/frv/fsqrtd.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# frv testcase for fsqrtd $FRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fsqrtd -fsqrtd: - fsqrtd fr44,fr2 ; 9.0 - test_dfr_dfr fr2,fr36 ; 3.0 - - set_fr_iimmed 0x4009,0x21fb,fr10 ; 3.141592654 - set_fr_iimmed 0x6000,0x0000,fr11 - fsqrtd fr10,fr10 - test_fr_iimmed 0x3ffc5bf8,fr10 ; 1.7724539 - test_fr_iimmed 0x9853a94d,fr11 - - pass diff --git a/sim/testsuite/sim/frv/fsqrts.cgs b/sim/testsuite/sim/frv/fsqrts.cgs deleted file mode 100644 index e771c40..0000000 --- a/sim/testsuite/sim/frv/fsqrts.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for fsqrts $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fsqrts -fsqrts: - fsqrts fr44,fr1 ; 9.0 - test_fr_fr fr1,fr36 ; 3.0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - fsqrts fr10,fr10 - test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 - - pass diff --git a/sim/testsuite/sim/frv/fstoi.cgs b/sim/testsuite/sim/frv/fstoi.cgs deleted file mode 100644 index 0a90a2a..0000000 --- a/sim/testsuite/sim/frv/fstoi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for fstoi $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fstoi -fstoi: - fstoi fr16,fr1 - test_fr_iimmed 0,fr1 - fstoi fr20,fr1 - test_fr_iimmed 0,fr1 - - fstoi fr32,fr1 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xce05,0x4904,fr1 - fstoi fr1,fr1 - test_fr_iimmed 0xdeadbf00,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fsubd.cgs b/sim/testsuite/sim/frv/fsubd.cgs deleted file mode 100644 index fed2d04..0000000 --- a/sim/testsuite/sim/frv/fsubd.cgs +++ /dev/null @@ -1,83 +0,0 @@ -# frv testcase for fsubd $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fsubd -fsubd: - fsubd fr0,fr16,fr2 - test_dfr_dfr fr2,fr0 - fsubd fr4,fr16,fr2 - test_dfr_dfr fr2,fr4 - fsubd fr8,fr16,fr2 - test_dfr_dfr fr2,fr8 - fsubd fr12,fr16,fr2 - test_dfr_dfr fr2,fr12 - fsubd fr16,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fsubd fr20,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fsubd fr24,fr16,fr2 - test_dfr_dfr fr2,fr24 - fsubd fr28,fr16,fr2 - test_dfr_dfr fr2,fr28 - fsubd fr32,fr16,fr2 - test_dfr_dfr fr2,fr32 - fsubd fr36,fr16,fr2 - test_dfr_dfr fr2,fr36 - fsubd fr40,fr16,fr2 - test_dfr_dfr fr2,fr40 - fsubd fr44,fr16,fr2 - test_dfr_dfr fr2,fr44 - fsubd fr48,fr16,fr2 - test_dfr_dfr fr2,fr48 - fsubd fr52,fr16,fr2 - test_dfr_dfr fr2,fr52 - - fsubd fr0,fr20,fr2 - test_dfr_dfr fr2,fr0 - fsubd fr4,fr20,fr2 - test_dfr_dfr fr2,fr4 - fsubd fr8,fr20,fr2 - test_dfr_dfr fr2,fr8 - fsubd fr12,fr20,fr2 - test_dfr_dfr fr2,fr12 - fsubd fr16,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fsubd fr20,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fsubd fr24,fr20,fr2 - test_dfr_dfr fr2,fr24 - fsubd fr28,fr20,fr2 - test_dfr_dfr fr2,fr28 - fsubd fr32,fr20,fr2 - test_dfr_dfr fr2,fr32 - fsubd fr36,fr20,fr2 - test_dfr_dfr fr2,fr36 - fsubd fr40,fr20,fr2 - test_dfr_dfr fr2,fr40 - fsubd fr44,fr20,fr2 - test_dfr_dfr fr2,fr44 - fsubd fr48,fr20,fr2 - test_dfr_dfr fr2,fr48 - fsubd fr52,fr20,fr2 - test_dfr_dfr fr2,fr52 - - fsubd fr32,fr36,fr2 - test_dfr_dfr fr2,fr8 - - fsubd fr44,fr40,fr2 - test_dfr_dfr fr2,fr36 - - pass - - diff --git a/sim/testsuite/sim/frv/fsubs.cgs b/sim/testsuite/sim/frv/fsubs.cgs deleted file mode 100644 index c1143ad..0000000 --- a/sim/testsuite/sim/frv/fsubs.cgs +++ /dev/null @@ -1,82 +0,0 @@ -# frv testcase for fsubs $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fsubs -fsubs: - fsubs fr0,fr16,fr1 - test_fr_fr fr1,fr0 - fsubs fr4,fr16,fr1 - test_fr_fr fr1,fr4 - fsubs fr8,fr16,fr1 - test_fr_fr fr1,fr8 - fsubs fr12,fr16,fr1 - test_fr_fr fr1,fr12 - fsubs fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fsubs fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fsubs fr24,fr16,fr1 - test_fr_fr fr1,fr24 - fsubs fr28,fr16,fr1 - test_fr_fr fr1,fr28 - fsubs fr32,fr16,fr1 - test_fr_fr fr1,fr32 - fsubs fr36,fr16,fr1 - test_fr_fr fr1,fr36 - fsubs fr40,fr16,fr1 - test_fr_fr fr1,fr40 - fsubs fr44,fr16,fr1 - test_fr_fr fr1,fr44 - fsubs fr48,fr16,fr1 - test_fr_fr fr1,fr48 - fsubs fr52,fr16,fr1 - test_fr_fr fr1,fr52 - - fsubs fr0,fr20,fr1 - test_fr_fr fr1,fr0 - fsubs fr4,fr20,fr1 - test_fr_fr fr1,fr4 - fsubs fr8,fr20,fr1 - test_fr_fr fr1,fr8 - fsubs fr12,fr20,fr1 - test_fr_fr fr1,fr12 - fsubs fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fsubs fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fsubs fr24,fr20,fr1 - test_fr_fr fr1,fr24 - fsubs fr28,fr20,fr1 - test_fr_fr fr1,fr28 - fsubs fr32,fr20,fr1 - test_fr_fr fr1,fr32 - fsubs fr36,fr20,fr1 - test_fr_fr fr1,fr36 - fsubs fr40,fr20,fr1 - test_fr_fr fr1,fr40 - fsubs fr44,fr20,fr1 - test_fr_fr fr1,fr44 - fsubs fr48,fr20,fr1 - test_fr_fr fr1,fr48 - fsubs fr52,fr20,fr1 - test_fr_fr fr1,fr52 - - fsubs fr32,fr36,fr1 - test_fr_fr fr1,fr8 - - fsubs fr44,fr40,fr1 - test_fr_fr fr1,fr36 - - pass - - diff --git a/sim/testsuite/sim/frv/fteq.cgs b/sim/testsuite/sim/frv/fteq.cgs deleted file mode 100644 index 020a887..0000000 --- a/sim/testsuite/sim/frv/fteq.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for fteq $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global fteq -fteq: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x2 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x3 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x4 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x5 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x6 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x7 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftge.cgs b/sim/testsuite/sim/frv/ftge.cgs deleted file mode 100644 index eab7a06..0000000 --- a/sim/testsuite/sim/frv/ftge.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for ftge $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftge -ftge: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x5 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftgt.cgs b/sim/testsuite/sim/frv/ftgt.cgs deleted file mode 100644 index 9035fbc..0000000 --- a/sim/testsuite/sim/frv/ftgt.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for ftgt $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftgt -ftgt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x5 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x9 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_fcc 0xc 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0xd 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftieq.cgs b/sim/testsuite/sim/frv/ftieq.cgs deleted file mode 100644 index a5710ad..0000000 --- a/sim/testsuite/sim/frv/ftieq.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for ftieq $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftieq -ftieq: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x2 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x3 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x4 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x5 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x6 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x7 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftige.cgs b/sim/testsuite/sim/frv/ftige.cgs deleted file mode 100644 index 5b58ce0..0000000 --- a/sim/testsuite/sim/frv/ftige.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for ftige $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftige -ftige: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x5 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftigt.cgs b/sim/testsuite/sim/frv/ftigt.cgs deleted file mode 100644 index e31ead4..0000000 --- a/sim/testsuite/sim/frv/ftigt.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for ftigt $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftigt -ftigt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x5 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x9 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_fcc 0xc 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0xd 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftile.cgs b/sim/testsuite/sim/frv/ftile.cgs deleted file mode 100644 index d13eeee..0000000 --- a/sim/testsuite/sim/frv/ftile.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for ftile $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftile -ftile: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x2 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x3 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftilg.cgs b/sim/testsuite/sim/frv/ftilg.cgs deleted file mode 100644 index 26127d2..0000000 --- a/sim/testsuite/sim/frv/ftilg.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for ftilg $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftilg -ftilg: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x9 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftilt.cgs b/sim/testsuite/sim/frv/ftilt.cgs deleted file mode 100644 index 7a74d5b..0000000 --- a/sim/testsuite/sim/frv/ftilt.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for ftilt $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftilt -ftilt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x2 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x3 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x9 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0xa 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0xb 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftine.cgs b/sim/testsuite/sim/frv/ftine.cgs deleted file mode 100644 index 89aa5a6..0000000 --- a/sim/testsuite/sim/frv/ftine.cgs +++ /dev/null @@ -1,112 +0,0 @@ -# frv testcase for ftine $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftine -ftine: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftino.cgs b/sim/testsuite/sim/frv/ftino.cgs deleted file mode 100644 index b08a571..0000000 --- a/sim/testsuite/sim/frv/ftino.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for ftino -# mach: all - - .include "testutils.inc" - - start - - .global ftinev -ftinev: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_gr_immed 0,gr7 - - set_fcc 0x0 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x1 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x2 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x3 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x4 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x5 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x6 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x7 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x8 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x9 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0xa 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0xb 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0xc 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0xd 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0xe 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0xf 0 - ftino ; should branch to tbr + (128 + 4)*16 - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftio.cgs b/sim/testsuite/sim/frv/ftio.cgs deleted file mode 100644 index 083c170..0000000 --- a/sim/testsuite/sim/frv/ftio.cgs +++ /dev/null @@ -1,112 +0,0 @@ -# frv testcase for ftio $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftio -ftio: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftira.cgs b/sim/testsuite/sim/frv/ftira.cgs deleted file mode 100644 index 9382b2b..0000000 --- a/sim/testsuite/sim/frv/ftira.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for ftira $GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftira -ftira: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_fcc 0x0 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass diff --git a/sim/testsuite/sim/frv/ftiu.cgs b/sim/testsuite/sim/frv/ftiu.cgs deleted file mode 100644 index adc40be..0000000 --- a/sim/testsuite/sim/frv/ftiu.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for ftiu $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftiu -ftiu: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_fcc 0x6 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_fcc 0xa 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_fcc 0xc 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_fcc 0xe 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftiue.cgs b/sim/testsuite/sim/frv/ftiue.cgs deleted file mode 100644 index 3111434..0000000 --- a/sim/testsuite/sim/frv/ftiue.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for ftiue $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftiue -ftiue: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_fcc 0x6 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftiug.cgs b/sim/testsuite/sim/frv/ftiug.cgs deleted file mode 100644 index 9e16f89..0000000 --- a/sim/testsuite/sim/frv/ftiug.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for ftiug $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftiug -ftiug: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_fcc 0xc 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftiuge.cgs b/sim/testsuite/sim/frv/ftiuge.cgs deleted file mode 100644 index bda587e..0000000 --- a/sim/testsuite/sim/frv/ftiuge.cgs +++ /dev/null @@ -1,112 +0,0 @@ -# frv testcase for ftiuge $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftiuge -ftiuge: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftiul.cgs b/sim/testsuite/sim/frv/ftiul.cgs deleted file mode 100644 index ee5e2ba..0000000 --- a/sim/testsuite/sim/frv/ftiul.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for ftiul $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftiul -ftiul: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_fcc 0xa 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftle.cgs b/sim/testsuite/sim/frv/ftle.cgs deleted file mode 100644 index 4ffa760..0000000 --- a/sim/testsuite/sim/frv/ftle.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for ftle $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftle -ftle: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x2 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x3 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftlg.cgs b/sim/testsuite/sim/frv/ftlg.cgs deleted file mode 100644 index a72f502..0000000 --- a/sim/testsuite/sim/frv/ftlg.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for ftlg $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftlg -ftlg: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x9 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftlt.cgs b/sim/testsuite/sim/frv/ftlt.cgs deleted file mode 100644 index c934313..0000000 --- a/sim/testsuite/sim/frv/ftlt.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for ftlt $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftlt -ftlt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x2 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x3 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x9 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0xa 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0xb 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftne.cgs b/sim/testsuite/sim/frv/ftne.cgs deleted file mode 100644 index 03b9857..0000000 --- a/sim/testsuite/sim/frv/ftne.cgs +++ /dev/null @@ -1,113 +0,0 @@ -# frv testcase for ftne $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftne -ftne: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftno.cgs b/sim/testsuite/sim/frv/ftno.cgs deleted file mode 100644 index bada522..0000000 --- a/sim/testsuite/sim/frv/ftno.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# frv testcase for ftno -# mach: all - - .include "testutils.inc" - - start - - .global ftnev -ftnev: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_fcc 0x0 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x1 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x2 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x3 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x4 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x5 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x6 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x7 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x8 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x9 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0xa 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0xb 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0xc 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0xd 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0xe 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0xf 0 - ftno ; should branch to tbr + (128 + 4)*16 - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fto.cgs b/sim/testsuite/sim/frv/fto.cgs deleted file mode 100644 index 82035f4..0000000 --- a/sim/testsuite/sim/frv/fto.cgs +++ /dev/null @@ -1,113 +0,0 @@ -# frv testcase for fto $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global fto -fto: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftra.cgs b/sim/testsuite/sim/frv/ftra.cgs deleted file mode 100644 index 7754f69..0000000 --- a/sim/testsuite/sim/frv/ftra.cgs +++ /dev/null @@ -1,115 +0,0 @@ -# frv testcase for ftra $GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftra -ftra: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_fcc 0x0 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass diff --git a/sim/testsuite/sim/frv/ftu.cgs b/sim/testsuite/sim/frv/ftu.cgs deleted file mode 100644 index 354423b..0000000 --- a/sim/testsuite/sim/frv/ftu.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for ftu $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftu -ftu: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_fcc 0x6 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_fcc 0xa 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_fcc 0xc 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_fcc 0xe 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftue.cgs b/sim/testsuite/sim/frv/ftue.cgs deleted file mode 100644 index 564bb30..0000000 --- a/sim/testsuite/sim/frv/ftue.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for ftue $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftue -ftue: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_fcc 0x6 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftug.cgs b/sim/testsuite/sim/frv/ftug.cgs deleted file mode 100644 index cc6a405..0000000 --- a/sim/testsuite/sim/frv/ftug.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for ftug $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftug -ftug: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_fcc 0xc 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftuge.cgs b/sim/testsuite/sim/frv/ftuge.cgs deleted file mode 100644 index 7c04eaf..0000000 --- a/sim/testsuite/sim/frv/ftuge.cgs +++ /dev/null @@ -1,113 +0,0 @@ -# frv testcase for ftuge $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftuge -ftuge: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftul.cgs b/sim/testsuite/sim/frv/ftul.cgs deleted file mode 100644 index b45ebb3..0000000 --- a/sim/testsuite/sim/frv/ftul.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for ftul $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftul -ftul: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_fcc 0xa 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftule.cgs b/sim/testsuite/sim/frv/ftule.cgs deleted file mode 100644 index 4a93260..0000000 --- a/sim/testsuite/sim/frv/ftule.cgs +++ /dev/null @@ -1,113 +0,0 @@ -# frv testcase for ftule $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftule -ftule: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/grloop.ms b/sim/testsuite/sim/frv/grloop.ms deleted file mode 100644 index 0060963..0000000 --- a/sim/testsuite/sim/frv/grloop.ms +++ /dev/null @@ -1,13 +0,0 @@ -# mach: all -# output: - - .global _start -_start: - setlo 0x0400,gr10 -loop: - addicc gr10,-1,gr10,icc0 - bne icc0,0,loop -; exit (0) - setlos #0,gr8 - setlos #1,gr7 - tira gr0,#0 diff --git a/sim/testsuite/sim/frv/hello.ms b/sim/testsuite/sim/frv/hello.ms deleted file mode 100644 index 117e4a6..0000000 --- a/sim/testsuite/sim/frv/hello.ms +++ /dev/null @@ -1,19 +0,0 @@ -# mach: all -# output: Hello World!\n - - .global _start -_start: - -; write (hello world) - setlos #14,gr10 - sethi %hi(hello),gr9 - setlo %lo(hello),gr9 - setlos #1,gr8 - setlos #5,gr7 - tira gr0,#0 -; exit (0) - setlos #0,gr8 - setlos #1,gr7 - tira gr0,#0 - -hello: .ascii "Hello World!\r\n" diff --git a/sim/testsuite/sim/frv/icei.cgs b/sim/testsuite/sim/frv/icei.cgs deleted file mode 100644 index aac925b..0000000 --- a/sim/testsuite/sim/frv/icei.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# frv testcase for icei @(GRi,GRj),a -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global icei -icei: - ; Can't really test this because of SCACHE implementation - set_gr_addr icei,gr10 - icei @(gr10,gr0),1 - icei @(gr10,gr0),1 - - pass diff --git a/sim/testsuite/sim/frv/ici.cgs b/sim/testsuite/sim/frv/ici.cgs deleted file mode 100644 index 8aeacae..0000000 --- a/sim/testsuite/sim/frv/ici.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# FRV testcase for ici @(GRi,GRj) -# mach: all - - .include "testutils.inc" - - start - - .global ici -ici: - set_gr_immed 1234,gr2 - set_spr_addr ok1,lr - bra testit - -ok1: - ; Change the first insn to set gr1 to 1235 - ; but don't invalidate the insn cache - ; should have no effect - set_gr_mem testit,gr10 - ori gr10,1,gr10 - set_mem_gr gr10,testit - set_gr_addr testit,gr10 - dcf @(gr10,gr0) ; flush data cache - set_spr_addr ok2,lr - bra testit - -ok2: ; Now invalidate the insn cache. The new insn should take effect - ici @(gr10,gr0) - set_gr_immed 1235,gr2 - set_spr_addr ok3,lr - bra testit - -ok3: - pass - -testit: - setlos 1234,gr1 - test_gr_gr gr1,gr2 - bralr - fail diff --git a/sim/testsuite/sim/frv/icpl.cgs b/sim/testsuite/sim/frv/icpl.cgs deleted file mode 100644 index b86ba35..0000000 --- a/sim/testsuite/sim/frv/icpl.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# FRV testcase for icpl GRi,GRj,lock -# mach: all - - .include "testutils.inc" - - start - - .global icpl - ; keep this at least 64 bytes away from doit2 - bra icpl -doit1: add gr11,gr12,gr11 - bralr - -icpl: - or_spr_immed 0x80000000,hsr0 ; insn cache: enable - and_spr_immed 0xbfffffff,hsr0 ; data cache: disable - set_gr_immed 0,gr11 - set_gr_immed 1,gr12 - set_gr_immed 2,gr13 - - set_gr_addr doit1,gr10 - icpl gr10,gr0,0 ; preload insns at doit1 - set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 - - set_gr_addr doit2,gr10 - set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 - - set_spr_addr ok1,lr - bra doit1 -ok1: test_gr_immed 1,gr11 ; used preloaded add of 1 - - set_spr_addr ok2,lr - bra doit2 -ok2: test_gr_immed 3,gr11 ; used changed add of 2 - - pass - -doit2: add gr11,gr12,gr11 - bralr diff --git a/sim/testsuite/sim/frv/icul.cgs b/sim/testsuite/sim/frv/icul.cgs deleted file mode 100644 index b112f41..0000000 --- a/sim/testsuite/sim/frv/icul.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# FRV testcase for icul $GRi -# mach: all - - .include "testutils.inc" - - start - - .global icul -icul: - or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode - - ; preload and lock all the lines in set 0 of the insn cache - set_gr_immed 0x70000,gr10 - set_bctrlr_0_0 gr10 - lock_insn_cache gr10 - - inc_gr_immed 0x1000,gr10 - set_bctrlr_0_0 gr10 - lock_insn_cache gr10 - - inc_gr_immed 0x1000,gr10 - set_bctrlr_0_0 gr10 - lock_insn_cache gr10 - - inc_gr_immed 0x1000,gr10 - set_bctrlr_0_0 gr10 - lock_insn_cache gr10 - - ; execute the pre-loaded insn - set_gr_immed 0x70000,gr10 - calll @(gr10,gr0) ; should come right back - inc_gr_immed 0x1000,gr10 - calll @(gr10,gr0) ; should come right back - inc_gr_immed 0x1000,gr10 - calll @(gr10,gr0) ; should come right back - inc_gr_immed 0x1000,gr10 - calll @(gr10,gr0) ; should come right back - - ; Now execute another insn which would have gone into set 0. - inc_gr_immed 0x1000,gr10 - set_bctrlr_0_0 gr10 - set_spr_immed 128,lcr - calll @(gr10,gr0) ; should come right back - - ; Now unlock one of the lines and do it again - set_gr_immed 0x71000,gr10 - icul gr10 - calll @(gr10,gr0) ; should come right back - - inc_gr_immed 0x3000,gr10 - calll @(gr10,gr0) ; should come right back - - pass diff --git a/sim/testsuite/sim/frv/interrupts.exp b/sim/testsuite/sim/frv/interrupts.exp deleted file mode 100644 index e31533e..0000000 --- a/sim/testsuite/sim/frv/interrupts.exp +++ /dev/null @@ -1,19 +0,0 @@ -# FRV simulator testsuite. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "frv fr500 fr550 fr400" - set cpu_option -mcpu - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/interrupts/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs b/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs deleted file mode 100644 index dad9f0e..0000000 --- a/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# frv testcase -# mach: fr400 - - .include "testutils.inc" - - start - - .global Ipipe -Ipipe: - ; Clear the packing bit of the insn at 'pack:'. We can't - ; simply use '.p' because the assembler will catch the error. - set_gr_mem pack,gr10 - and_gr_immed 0x7fffffff,gr10 - set_mem_gr gr10,pack - set_gr_addr pack,gr10 - flush_data_cache gr10 - - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 0x070,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - set_spr_immed 128,lcr - set_spr_addr ok0,lr - set_psr_et 1 - -bundle: add.p gr1,gr1,gr1 -pack: add gr2,gr2,gr2 -bad: add gr3,gr3,gr3 - fail -ok0: - test_spr_immed 1,esfr1 - test_spr_bits 0x3f,0,0xb,esr0 - test_spr_addr bundle,epcr0 - - pass diff --git a/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs b/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs deleted file mode 100644 index b4dd770..0000000 --- a/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# frv testcase -# mach: fr500 - - .include "testutils.inc" - - start - - .global Ipipe -Ipipe: - ; Clear the packing bit of the insn at 'pack:'. We can't - ; simply use '.p' because the assembler will catch the error. - set_gr_mem pack,gr10 - and_gr_immed 0x7fffffff,gr10 - set_mem_gr gr10,pack - set_gr_addr pack,gr10 - flush_data_cache gr10 - - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 0x070,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - set_spr_immed 128,lcr - set_spr_addr ok0,lr - set_psr_et 1 - - add.p gr1,gr1,gr1 -pack: add gr2,gr2,gr2 -bad: add gr3,gr3,gr3 - fail -ok0: - test_spr_immed 1,esfr1 - test_spr_bits 0x3f,0,0xb,esr0 - test_spr_addr bad,epcr0 - - pass diff --git a/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs b/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs deleted file mode 100644 index 6c0369b..0000000 --- a/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) -# mach: fr550 - .include "testutils.inc" - - start - - .global align -align: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x100,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - set_gr_immed 0xdeadbeef,gr17 - set_gr_immed 0,gr15 - inc_gr_immed 2,sp ; out of alignment - - test_spr_bits 1,0,0,isr ; ISR.EMAM always clear (not used) - sti gr17,@(sp,0) ; no exception - sti gr17,@(sp,4) ; no exception - ldi @(sp,0),gr18 ; stored at unaligned address - test_gr_immed 0xdeadbeef,gr18 - ldi @(sp,0),gr19 ; no exception - test_gr_immed 0xdeadbeef,gr19 - - and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM - sti gr17,@(sp,0) ; misaligned -- no exception - test_gr_immed 0,gr15 - - set_gr_gr sp,gr20 - set_gr_immed 1,gr21 - set_gr_immed 0x10101010,gr10 - nop.p - ldu @(sp,gr21),gr10 ; misaligned read no exception - test_gr_immed 0,gr15 ; handler was not called - test_gr_immed 0xadbeefde,gr10 ; gr10 updated - test_gr_immed 1,gr21 ; gr21 not updated - inc_gr_immed 1,gr20 - test_gr_gr gr20,sp ; sp updated - - pass diff --git a/sim/testsuite/sim/frv/interrupts/badalign.cgs b/sim/testsuite/sim/frv/interrupts/badalign.cgs deleted file mode 100644 index b866021..0000000 --- a/sim/testsuite/sim/frv/interrupts/badalign.cgs +++ /dev/null @@ -1,73 +0,0 @@ -# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) -# mach: fr500 frv - .include "testutils.inc" - - start - - .global align -align: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x100,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_psr_et 1 - set_gr_immed 0xdeadbeef,gr17 - set_gr_immed 0,gr15 - inc_gr_immed 2,sp ; out of alignment - - test_spr_bits 1,0,1,isr ; mem_address_not_aligned is masked - sti gr17,@(sp,0) ; no exception - ldi @(sp,-2),gr18 ; stored at aligned address - test_gr_immed 0xdeadbeef,gr18 - ldi @(sp,0),gr19 ; no exception - test_gr_immed 0xdeadbeef,gr19 - - and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM - set_gr_addr bad1,gr16 -bad1: sti gr17,@(sp,0) ; misaligned write in slot I1 - test_gr_immed 1,gr15 - - set_gr_addr bad3,gr16 - set_gr_gr sp,gr20 - set_gr_immed 1,gr21 - set_gr_immed 0x10101010,gr10 -bad2: nop.p -bad3: ldu @(sp,gr21),gr10 ; misaligned read in slot I2 - test_gr_immed 2,gr15 ; handler was called - test_gr_immed 0x10101010,gr10 ; gr10 not updated - test_gr_immed 1,gr21 ; gr21 not updated - inc_gr_immed 1,gr20 - test_gr_gr gr20,sp ; sp updated - - pass - -; exception handler -ok1: - cmpi gr15,0,icc0 - bne icc0,0,load - ; handle interrupt on store - test_spr_immed 0x100,esfr1 ; esr8 is active - test_spr_gr epcr8,gr16 - test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid - test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set - test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set - test_spr_gr ear8,sp - test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set - test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3 - test_spr_gr edr3,gr17 ; edr3 is set - bra ret -load: - ; handle interrupt on load - test_spr_immed 0x200,esfr1 ; esr9 is active - test_spr_gr epcr9,gr16 - test_spr_bits 0x0001,0,0x1,esr9 ; esr9 is valid - test_spr_bits 0x003e,1,0xb,esr9 ; esr9.ec is set - test_spr_bits 0x0800,11,0x1,esr9 ; esr9.eav is set - test_spr_gr ear9,sp - test_spr_bits 0x1000,12,0x0,esr9 ; esr9.edv is not set -ret: - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs b/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs deleted file mode 100644 index 7cd2278..0000000 --- a/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# frv testcase to generate compound exception -# mach: fr550 - .include "testutils.inc" - - start - - .global align -align: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x200,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception - set_psr_et 1 - - set_gr_immed 0,gr15 - set_fr_iimmed 0x7f7f,0xffff,fr0 - set_fr_iimmed 0x0000,0x0000,fr1 - - and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned - set_gr_addr dividef,gr16 - set_gr_addr dividei,gr17 - set_gr_immed 0xdeadbeef,gr8 - inc_gr_immed 2,sp ; misalign -store: sti.p gr8,@(sp,0) ; misaligned - no exception -dividef:fdivs.p fr0,fr1,fr2 ; fp_exception -dividei:sdiv gr1,gr0,gr1 ; division exception - test_gr_immed 1,gr15 - - pass - -; exception handler -ok1: - ; check fp_exception - test_spr_immed 0x5,esfr1 ; esr2 and esr0 are active - test_spr_gr epcr2,gr16 - test_spr_bits 0x0001,0,0x1,esr2 ; esr2 is valid - test_spr_bits 0x003e,1,0xd,esr2 ; esr2.ec is set - test_spr_bits 0x0800,11,0x0,esr2 ; esr2.eav is clear - - ; check on fp_exception - test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear - - ; check interrupt on dividei - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/compound.cgs b/sim/testsuite/sim/frv/interrupts/compound.cgs deleted file mode 100644 index 2fd928e..0000000 --- a/sim/testsuite/sim/frv/interrupts/compound.cgs +++ /dev/null @@ -1,66 +0,0 @@ -# frv testcase to generate compound exception -# mach: fr500 frv - .include "testutils.inc" - - start - - .global align -align: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x200,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception - set_psr_et 1 - - set_gr_immed 0,gr15 - set_fr_iimmed 0x7f7f,0xffff,fr0 - set_fr_iimmed 0x0000,0x0000,fr1 - - and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned - set_gr_addr store,gr16 - set_gr_addr dividei,gr17 - set_gr_immed 0xdeadbeef,gr8 - inc_gr_immed 2,sp ; misalign -store: sti.p gr8,@(sp,0) ; misaligned write -dividef:fdivs.p fr0,fr1,fr2 ; fp_exception -dividei:sdiv gr1,gr0,gr1 ; division exception - test_gr_immed 1,gr15 - - pass - -; exception handler -ok1: - ; check interrupt on store - test_spr_immed 0x102,esfr1 ; esr8 and esr1 are active - test_spr_gr epcr8,gr16 - test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid - test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set - test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set - test_spr_gr ear8,sp - test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set - test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3 - test_spr_gr edr3,gr8 ; edr3 is set - - ; check on fp_exception - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear - - test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set - test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set - test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set - test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set - test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set - test_spr_immed 0x05e40241,fqop2 ; fq2.opc - - ; check interrupt on dividei - test_spr_gr epcr1,gr17 - test_spr_bits 0x0001,0,0x1,esr1 ; esr1 is valid - test_spr_bits 0x003e,1,0x13,esr1 ; esr1.ec is set - - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs b/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs deleted file mode 100644 index 3924adc..0000000 --- a/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) -# mach: fr550 -# sim(fr550): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010 - .include "testutils.inc" - - start - - .global dsr -dsr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x140,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - - set_spr_addr ok0,lr - set_gr_immed 0,gr16 - - set_gr_immed 0xdeadbeef,gr15 - set_gr_addr 0xfeff0600,gr17 -bad1: sti gr15,@(gr17,0) ; no interrupt - test_gr_immed 0,gr16 - - set_gr_immed 0xbeefdead,gr15 - set_gr_addr 0xfeff7ffc,gr17 -bad2: sti gr15,@(gr17,0) ; no interrupt - test_gr_immed 0,gr16 - - set_gr_immed 0xbeefbeef,gr15 - set_gr_addr 0xfe800000,gr17 -bad3: sti gr15,@(gr17,0) ; cause interrupt - test_gr_immed 1,gr16 - - set_gr_immed 0xdeaddead,gr15 - set_gr_addr 0xfefefffc,gr17 -bad4: sti gr15,@(gr17,0) ; cause interrupt - test_gr_immed 2,gr16 - - sti gr0,@(sp,0) ; no interrupt - test_gr_immed 2,gr16 - - pass -ok0: - ; check interrupts - test_spr_immed 0x4000,esfr1 ; esr14 is active - test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid - test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set - test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set - - addi gr16,1,gr16 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/data_store_error.cgs b/sim/testsuite/sim/frv/interrupts/data_store_error.cgs deleted file mode 100644 index b967d0a..0000000 --- a/sim/testsuite/sim/frv/interrupts/data_store_error.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) -# mach: fr500 -# sim(fr500): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010 - .include "testutils.inc" - - start - - .global dsr -dsr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x140,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - - set_spr_addr ok0,lr - set_gr_immed 0,gr16 - - set_gr_immed 0xdeadbeef,gr15 - set_gr_addr 0xfeff0600,gr17 -bad1: sti gr15,@(gr17,0) ; cause interrupt - test_gr_immed 1,gr16 - - set_gr_immed 0xbeefdead,gr15 - set_gr_addr 0xfeff7ffc,gr17 -bad2: sti gr15,@(gr17,0) ; cause interrupt - test_gr_immed 2,gr16 - - set_gr_immed 0xbeefbeef,gr15 - set_gr_addr 0xfe800000,gr17 -bad3: sti gr15,@(gr17,0) ; cause interrupt - test_gr_immed 3,gr16 - - set_gr_immed 0xdeaddead,gr15 - set_gr_addr 0xfefefffc,gr17 -bad4: sti gr15,@(gr17,0) ; cause interrupt - test_gr_immed 4,gr16 - - sti gr0,@(sp,0) ; no interrupt - test_gr_immed 4,gr16 - - pass -ok0: - ; check interrupts - test_spr_immed 0x4000,esfr1 ; esr14 is active - test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid - test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set - test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set - - addi gr16,1,gr16 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs deleted file mode 100644 index 5d1c3f5..0000000 --- a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs +++ /dev/null @@ -1,185 +0,0 @@ -# frv testcase to generate fp_exception -# mach: fr550 - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global align -align: - ; clear the packing bit if the insn at 'pack:'. We can't simply use - ; '.p' because the assembler will catch the error. - set_gr_mem pack,gr10 - and_gr_immed 0x7fffffff,gr10 - set_mem_gr gr10,pack - set_gr_addr pack,gr10 - flush_data_cache gr10 - - ; Make the the source register number odd at badst. We can't simply - ; code an odd register number because the assembler will catch the - ; error. - set_gr_mem badst,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,badst - set_gr_addr badst,gr10 - flush_data_cache gr10 - - ; Make the the dest register number odd at badld. We can't simply - ; code an odd register number because the assembler will catch the - ; error. - set_gr_mem badld,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,badld - set_gr_addr badld,gr10 - flush_data_cache gr10 - - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x070,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - inc_gr_immed 0x060,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_psr_et 1 - inc_gr_immed -4,sp ; for alignment - - set_gr_immed 0,gr20 ; PC increment - set_gr_immed 0,gr15 - - set_spr_addr ok3,lr - set_gr_immed 4,gr20 ; PC increment -badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 - test_gr_immed 1,gr15 - - set_spr_addr ok4,lr - set_gr_immed 8,gr20 ; PC increment - nop.p -badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 - test_gr_immed 2,gr15 - - set_spr_addr ok5,lr - set_gr_immed 20,gr20 ; PC increment - fnegs.p fr9,fr9 - fnegs.p fr9,fr10 - fnegs.p fr9,fr11 -pack: fnegs fr10,fr12 - fnegs fr10,fr13 ; packing violation - test_gr_immed 3,gr15 - - set_spr_addr ok1,lr - set_gr_immed 4,gr20 ; PC increment -bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented) - test_gr_immed 4,gr15 - - and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception - set_fr_iimmed 0x7f7f,0xffff,fr0 - set_fr_iimmed 0x0000,0x0000,fr1 - fdivs fr0,fr1,fr2 ; div/0 -- no exception - test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set - test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set - test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear - - set_spr_addr ok2,lr - set_gr_immed 0,gr20 ; PC increment - or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception - set_fr_iimmed 0xdead,0xbeef,fr2 -div0: fdivs fr0,fr1,fr2 ; fp_exception - div/0 - test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated - test_gr_immed 5,gr15 - - and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception - fsqrts fr32,fr2 ; inexact -- no exception - test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set - test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set - test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear - - set_fr_fr fr2,fr3 ; sqrt 2 - set_fr_iimmed 0xdead,0xbeef,fr2 - set_spr_addr ok6,lr - or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception -inxt1: fsqrts fr32,fr2 ; fp_exception - inexact - test_gr_immed 6,gr15 ; handler called - test_fr_fr fr2,fr3 ; fr2 updated - - set_fr_iimmed 0xdead,0xbeef,fr2 - set_spr_addr ok7,lr -inxt2: fsqrts fr32,fr2 ; fp_exception - inexact again - test_gr_immed 7,gr15 ; handler called - test_fr_fr fr2,fr3 ; fr2 updated - - pass - -; exception handler 1 -- illegal_instruction: bad insn -ok1: - test_spr_immed 1,esfr1 ; esr0 active - test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set - test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set - bra ret - -; exception handler 2 - fp_exception: divide by 0 -ok2: - test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set - - test_spr_immed 4,esfr1 ; esr2 active - test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set - test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set - test_spr_addr div0,epcr2 ; epcr2 is set - bra ret - -; exception handler 3 - illegal_instruction: register exception -ok3: - test_spr_immed 1,esfr1 ; esr0 active - test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set - test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set - bra ret - -; exception handler 4 - illegal_instruction: register exception -ok4: - test_spr_immed 1,esfr1 ; esr0 active - test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set - test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set - bra ret - -; exception handler 5 - illegal_instruction: sequence violation -ok5: - test_spr_immed 1,esfr1 ; esr0 active - test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set - test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set - bra ret - -; exception handler 6 - fp_exception: inexact -ok6: - test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set - - test_spr_immed 4,esfr1 ; esr2 active - test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set - test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set - test_spr_addr inxt1,epcr2 ; epcr2 is set - bra ret - -; exception handler 7 - fp_exception: inexact again -ok7: - test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set - - test_spr_immed 4,esfr1 ; esr2 active - test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set - test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set - test_spr_addr inxt2,epcr2 ; epcr2 is set - bra ret - -ret: - inc_gr_immed 1,gr15 - movsg pcsr,gr60 - add gr60,gr20,gr60 - movgs gr60,pcsr - rett 0 - fail - diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs deleted file mode 100644 index 0109b53..0000000 --- a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs +++ /dev/null @@ -1,209 +0,0 @@ -# frv testcase to generate fp_exception -# mach: fr500 - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global align -align: - ; clear the packing bit if the insn at 'pack:'. We can't simply use - ; '.p' because the assembler will catch the error. - set_gr_mem pack,gr10 - and_gr_immed 0x7fffffff,gr10 - set_mem_gr gr10,pack - set_gr_addr pack,gr10 - flush_data_cache gr10 - - ; Make the the source register number odd at badst. We can't simply - ; code an odd register number because the assembler will catch the - ; error. - set_gr_mem badst,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,badst - set_gr_addr badst,gr10 - flush_data_cache gr10 - - ; Make the the dest register number odd at ld. We can't simply - ; code an odd register number because the assembler will catch the - ; error. - set_gr_mem badld,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,badld - set_gr_addr badld,gr10 - flush_data_cache gr10 - - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x070,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - inc_gr_immed 0x060,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_psr_et 1 - inc_gr_immed -4,sp ; for alignment - - set_gr_immed 0,gr20 ; PC increment - set_gr_immed 0,gr15 - - set_spr_addr ok3,lr -badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 - test_gr_immed 1,gr15 - - set_spr_addr ok4,lr - nop.p -badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 - test_gr_immed 2,gr15 - - set_spr_addr ok5,lr - fnegs.p fr9,fr9 -pack: fnegs fr10,fr10 - fnegs fr10,fr11 ; packing violation - test_gr_immed 3,gr15 - - set_spr_addr ok1,lr - set_gr_immed 4,gr20 ; PC increment -bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented) - test_gr_immed 4,gr15 - - and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception - set_fr_iimmed 0x7f7f,0xffff,fr0 - set_fr_iimmed 0x0000,0x0000,fr1 - fdivs fr0,fr1,fr2 ; div/0 -- no exception - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set - test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set - test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear - and_spr_immed 0xffefffff,fsr0 ; Clear fsr0.qne - - set_spr_addr ok2,lr - set_gr_immed 0,gr20 ; PC increment - or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception - set_fr_iimmed 0xdead,0xbeef,fr2 - fdivs fr0,fr1,fr2 ; fp_exception - div/0 - test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated - test_gr_immed 5,gr15 - - and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception - fsqrts fr32,fr2 ; inexact -- no exception - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set - test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set - test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear - - set_fr_fr fr2,fr3 ; sqrt 2 - set_fr_iimmed 0xdead,0xbeef,fr2 - set_spr_addr ok6,lr - or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception - fsqrts fr32,fr2 ; fp_exception - inexact - test_gr_immed 6,gr15 ; handler called - test_fr_fr fr2,fr3 ; fr2 updated - - set_fr_iimmed 0xdead,0xbeef,fr2 - set_spr_addr ok7,lr - fsqrts fr32,fr2 ; fp_exception - inexact again - test_gr_immed 7,gr15 ; handler called - test_fr_fr fr2,fr3 ; fr2 updated - - pass - -; exception handler 1 -- bad insn -ok1: - test_spr_immed 1,esfr1 ; esr0 active - test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set - test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set - test_spr_addr bad,epcr0 - bra ret - -; exception handler 2 - fp_exception: divide by 0 -ok2: - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set - - test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set - test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set - test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set - test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set - test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set - test_spr_immed 0x85e40241,fqop2 ; fq2.opc - bra ret - -; exception handler 3 - fp_exception: register exception -ok3: - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear - - test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set - test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set - test_spr_bits 0x380,7,0x6,fqst2 ; fq2.ftt is set - test_spr_bits 0x7e,1,0x0,fqst2 ; fq2.cexc is set - test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set - test_spr_immed 0x83581000,fqop2 ; fq2.opc - bra ret - -; exception handler 4 - fp_exception: another register exception -ok4: - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear - - test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set - test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set - test_spr_bits 0x380,7,0x6,fqst3 ; fq3.ftt is set - test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set - test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set - test_spr_immed 0x92ec1000,fqop3 ; fq3.opc - bra ret - -; exception handler 5 - fp_exception: sequence violation -ok5: - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x4,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear - - test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set - test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set - test_spr_bits 0x380,7,0x4,fqst3 ; fq3.ftt is set - test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set - test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set - test_spr_immed 0x97e400ca,fqop3 ; fq3.opc - bra ret - -; exception handler 6 - fp_exception: inexact -ok6: - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set - - test_spr_bits 0x80000000,31,0x0,fqst0 ; fq0.miv is set - test_spr_bits 0x18000,15,0x0,fqst0 ; fq0.sie is set - test_spr_bits 0x380,7,0x1,fqst0 ; fq0.ftt is set - test_spr_bits 0x7e,1,0x2,fqst0 ; fq0.cexc is set - test_spr_bits 0x1,0,0x1,fqst0 ; fq0.valid is set - test_spr_immed 0x85e40160,fqop0 ; fq0.opc - bra ret - -; exception handler 7 - fp_exception: inexact again -ok7: - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set - - test_spr_bits 0x80000000,31,0x0,fqst1 ; fq1.miv is set - test_spr_bits 0x18000,15,0x0,fqst1 ; fq1.sie is set - test_spr_bits 0x380,7,0x1,fqst1 ; fq1.ftt is set - test_spr_bits 0x7e,1,0x2,fqst1 ; fq1.cexc is set - test_spr_bits 0x1,0,0x1,fqst1 ; fq1.valid is set - test_spr_immed 0x85e40160,fqop1 ; fq1.opc - bra ret - -ret: - inc_gr_immed 1,gr15 - movsg pcsr,gr60 - add gr60,gr20,gr60 - movgs gr60,pcsr - rett 0 - fail - diff --git a/sim/testsuite/sim/frv/interrupts/illinsn.cgs b/sim/testsuite/sim/frv/interrupts/illinsn.cgs deleted file mode 100644 index fc44a8f..0000000 --- a/sim/testsuite/sim/frv/interrupts/illinsn.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# FRV testcase -# mach: fr500 fr550 fr400 - - .include "testutils.inc" - - start - - .global tra -tra: - and_spr_immed 0x3fffffff,hsr0 ; no caches enabled - - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 0x070,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - inc_gr_immed 0x790,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - set_spr_immed 128,lcr - set_psr_et 1 - set_spr_addr ok0,lr - - set_gr_addr ill1,gr7 - set_mem_immed 0x81f80000,gr7 ; unknown opcode: 7E -ill1: tira gr0,0 ; should be overridden -ill2: nop ; also illegal, but prev has priority -bad0: fail - - ; check interrupt -ok0: test_spr_addr ill1,pcsr - test_spr_immed 1,esfr1 ; esr0 active - test_spr_bits 0x3f,0,0xb,esr0 - movsg psr,gr28 - srli gr28,28,gr28 - subicc gr28,0x3,gr0,icc3 ; is fr550? - beq icc3,0,no_epcr - test_spr_addr ill1,epcr0 -no_epcr: - pass diff --git a/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs b/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs deleted file mode 100644 index 6c49299..0000000 --- a/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs +++ /dev/null @@ -1,44 +0,0 @@ -# frv testcase to generate insn_access_error interrupt -# mach: fr550 -# sim: --memory-region 0xfe800000,0x7f0500 --memory-region 0xfeff0540,0xfb00 - .include "testutils.inc" - - start - - .global dsr -dsr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x020,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - - set_spr_addr handler,lr - set_gr_immed 0,gr16 - - set_gr_addr ok0,gr8 - set_gr_addr 0xfe800000,gr17 - jmpl @(gr17,gr0) ; cause interrupt -ok0: - test_gr_immed 1,gr16 - - set_gr_addr ok1,gr8 - set_gr_addr 0xfefffffc,gr17 - jmpl @(gr17,gr0) ; cause interrupt -ok1: - test_gr_immed 2,gr16 - - pass -handler: - ; check interrupts - test_spr_immed 0x1,esfr1 ; esr0 is active -; test_spr_gr epcr0,gr17 ; epcr0 is not used - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set - - addi gr16,1,gr16 - movgs gr8,pcsr - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs b/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs deleted file mode 100644 index 11a9eaf..0000000 --- a/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs +++ /dev/null @@ -1,56 +0,0 @@ -# frv testcase to generate insn_access_error interrupt -# mach: fr500 fr400 -# sim: --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0040 - .include "testutils.inc" - - start - - .global dsr -dsr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x020,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - - set_spr_addr handler,lr - set_gr_immed 0,gr16 - - set_gr_addr ok0,gr8 - set_gr_addr 0xfeff0600,gr17 - jmpl @(gr17,gr0) ; cause interrupt -ok0: - test_gr_immed 1,gr16 - - set_gr_addr ok1,gr8 - set_gr_addr 0xfeff7ffc,gr17 - jmpl @(gr17,gr0) ; cause interrupt -ok1: - test_gr_immed 2,gr16 - - set_gr_addr ok2,gr8 - set_gr_addr 0xfe800000,gr17 - jmpl @(gr17,gr0) ; cause interrupt -ok2: - test_gr_immed 3,gr16 - - set_gr_addr ok3,gr8 - set_gr_addr 0xfefefffc,gr17 - jmpl @(gr17,gr0) ; cause interrupt -ok3: - test_gr_immed 4,gr16 - - pass -handler: - ; check interrupts - test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr17 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set - - addi gr16,1,gr16 - movgs gr8,pcsr - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/mp_exception.cgs b/sim/testsuite/sim/frv/interrupts/mp_exception.cgs deleted file mode 100644 index 3203acc..0000000 --- a/sim/testsuite/sim/frv/interrupts/mp_exception.cgs +++ /dev/null @@ -1,289 +0,0 @@ -# frv testcase for mp_exception -# mach: fr500 fr550 frv -# xerror: - -# This program no longer assembles because the assembler -# now detects the unaligned registers. For this reason -# this test is now marked as "xerror" and prints the -# expected message "fail" - - .include "testutils.inc" - - start - - .global mp_exception -mpx: -.if 1 - fail -.else - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mcmpsh fr10,fr11,fcc1 ; mp_exception: cr-not-aligned - test_spr_bits 0x7000,12,3,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf is set - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mcmpsh.p fr10,fr11,fcc0 ; no exception - mcmpsh fr10,fr11,fcc2 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mmulhs.p fr10,fr11,acc3 ; no exception - mmulhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mmulhu fr10,fr11,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mmulxhs.p fr10,fr11,acc3 ; no exception - mmulxhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mmulxhu fr10,fr11,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mmachs.p fr10,fr11,acc3 ; no exception - mmachs fr10,fr11,acc1 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mmachu fr10,fr11,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqaddhss.p fr10,fr12,fr17 ; mp_exception: register-not-aligned - mqaddhss fr10,fr12,fr14 ; no exception - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqaddhss.p fr10,fr12,fr14 ; no exception - mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqaddhss.p fr19,fr12,fr14 ; mp_exception: register-not-aligned - mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqaddhss fr10,fr12,fr14 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqmulhs.p fr10,fr11,acc3 ; no exception - mqmulhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmulhu fr10,fr11,acc0 ; mp_exception: register_not_aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmulhu fr10,fr12,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqmulxhs.p fr10,fr11,acc3 ; no exception - mqmulxhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmulxhu fr10,fr11,acc0 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmulxhu fr10,fr12,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqmachs.p fr10,fr12,acc3 ; no exception - mqmachs fr10,fr12,acc2 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned - mqmachu fr10,fr12,acc0 ; no exception - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmachu.p fr10,fr12,acc0 ; no exception - mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned - mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmachu fr10,fr12,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqcpxrs.p fr10,fr12,acc0 ; no exception - mqcpxrs fr10,fr12,acc1 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned - mqcpxru fr10,fr12,acc0 ; no exception - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqcpxru.p fr10,fr12,acc0 ; no exception - mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned - mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqcpxru fr10,fr12,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - pass -.endif diff --git a/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs b/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs deleted file mode 100644 index 9996236..0000000 --- a/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# frv testcase to generate privileged_instruction interrupt -# mach: frv - - .include "testutils.inc" - - start - - .global dsr -dsr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x060,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - and_spr_immed 0xfffffffb,psr ; clear psr.s - - set_spr_addr handler,lr - set_gr_immed 0,gr16 - - set_gr_addr bad1,gr17 -bad1: rett 0 ; cause interrupt - test_gr_immed 1,gr16 - set_gr_addr bad2,gr17 -bad2: rei 0 ; cause interrupt - test_gr_immed 2,gr16 - set_gr_addr bad3,gr17 -bad3: witlb gr0,@(gr0,gr0) ; cause interrupt - test_gr_immed 3,gr16 - set_gr_addr bad4,gr17 -bad4: wdtlb gr0,@(gr0,gr0) ; cause interrupt - test_gr_immed 4,gr16 - set_gr_addr bad5,gr17 -bad5: itlbi @(gr0,gr0) ; cause interrupt - test_gr_immed 5,gr16 - set_gr_addr bad6,gr17 -bad6: dtlbi @(gr0,gr0) ; cause interrupt - test_gr_immed 6,gr16 - - pass -handler: - ; check interrupts - test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr17 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x4,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set - - addi gr16,1,gr16 - movsg pcsr,gr8 - addi gr8,4,gr8 - movgs gr8,pcsr - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/regalign.cgs b/sim/testsuite/sim/frv/interrupts/regalign.cgs deleted file mode 100644 index afa09b5..0000000 --- a/sim/testsuite/sim/frv/interrupts/regalign.cgs +++ /dev/null @@ -1,130 +0,0 @@ -# frv testcase to generate interrupts for bad register alignment -# mach: frv - .include "testutils.inc" - - start - - .global align -align: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x080,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - inc_gr_immed 0x050,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_psr_et 1 - - ; Make the the register number odd at bad[1-4], bad9 and bada. - ; We can't simply code an odd register number because the assembler - ; will catch the error. - set_gr_mem bad1,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,bad1 - set_gr_addr bad1,gr10 - flush_data_cache gr10 - set_gr_mem bad2,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,bad2 - set_gr_addr bad2,gr10 - flush_data_cache gr10 - set_gr_mem bad3,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,bad3 - set_gr_addr bad3,gr10 - flush_data_cache gr10 - set_gr_mem bad4,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,bad4 - set_gr_addr bad4,gr10 - flush_data_cache gr10 - set_gr_mem bad9,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,bad9 - set_gr_addr bad9,gr10 - flush_data_cache gr10 - set_gr_mem bada,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,bada - set_gr_addr bada,gr10 - flush_data_cache gr10 - - set_gr_immed 4,gr20 ; PC increment - set_gr_immed 0,gr15 - inc_gr_immed -12,sp ; for memory alignment - - set_gr_addr bad1,gr17 -bad1: stdi gr0,@(sp,0) ; misaligned reg - test_gr_immed 1,gr15 - - set_gr_addr bad2,gr17 -bad2: lddi @(sp,0),gr8 ; misaligned reg - test_gr_immed 2,gr15 - - set_gr_addr bad3,gr17 -bad3: stdc cpr0,@(sp,gr0) ; misaligned reg - test_gr_immed 3,gr15 - - set_gr_addr bad4,gr17 -bad4: lddc @(sp,gr0),cpr8 ; misaligned reg - test_gr_immed 4,gr15 - - set_gr_addr bad5,gr17 -bad5: stqi gr2,@(sp,0) ; misaligned reg - test_gr_immed 5,gr15 - - set_gr_addr bad6,gr17 -bad6: ldqi @(sp,0),gr10 ; misaligned reg - test_gr_immed 6,gr15 - - set_gr_addr bad7,gr17 -bad7: stqc cpr2,@(sp,gr0) ; misaligned reg - test_gr_immed 7,gr15 - - set_gr_addr bad8,gr17 -bad8: ldqc @(sp,gr0),cpr10 ; misaligned reg - test_gr_immed 8,gr15 - - set_gr_immed 0,gr20 ; PC increment - set_gr_addr bad9,gr17 -bad9: stdfi fr0,@(sp,0) ; misaligned reg - test_gr_immed 9,gr15 - - set_gr_addr bada,gr17 -bada: lddfi @(sp,0),fr8 ; misaligned reg - test_gr_immed 10,gr15 - - set_gr_addr badb,gr17 -badb: stqfi fr2,@(sp,0) ; misaligned reg - test_gr_immed 11,gr15 - - set_gr_addr badc,gr17 -badc: ldqfi @(sp,0),fr10 ; misaligned reg - test_gr_immed 12,gr15 - - pass - -; exception handler -ok1: - cmpi gr20,0,icc0 - beq icc0,0,float - - ; check register_exception - test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr17 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0xc,esr0 ; esr0.ec is set - test_spr_bits 0x00c0,6,0x1,esr0 ; esr0.rec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set - movsg pcsr,gr60 - add gr60,gr20,gr60 - movgs gr60,pcsr - bra ret -float: - ; check fp_exception - test_spr_immed 0,esfr1 ; no esr's active -ret: - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/reset.cgs b/sim/testsuite/sim/frv/interrupts/reset.cgs deleted file mode 100644 index ff2035c..0000000 --- a/sim/testsuite/sim/frv/interrupts/reset.cgs +++ /dev/null @@ -1,81 +0,0 @@ -# frv testcase to generate reset interrupts -# mach: fr500 fr550 fr400 -# sim: --memory-region 0xff000000,64 - - .include "testutils.inc" - - start - - .global reset -reset: - and_spr_immed 0xfffffffb,psr ; turn off PSR.S - set_gr_immed 0xfeff0500,gr10 ; address of reset register - set_spr_immed 0x7fffffff,lcr - set_bctrlr_0_0 gr0 - -; Can't recover from hardware interrupt with enough state intact to verify it -; set_spr_addr ok1,lr -; set_mem_immed 0x3,gr10 ; cause hardware reset -; dcf @(gr10,gr0) ; Wait for store to happen -; fail -; -;ok1: ; reset should branch to reset address which should then branch here -; test_mem_immed 0x00000200,gr10 -; set_spr_addr ok2,lr -; set_mem_immed 0x2,gr10 ; cause hardware reset -; dcf @(gr10,gr0) ; Wait for store to happen -; fail -; -ok2: ; reset should branch to reset address which should then branch here -; test_mem_immed 0x00000200,gr10 - set_spr_addr ok3,lr - set_mem_immed 0x1,gr10 ; cause software reset - dcf @(gr10,gr0) ; Wait for store to happen - fail - -ok3: ; reset should branch to reset address which should then branch here - test_mem_immed 0x00000100,gr10 - test_spr_bits 0x4,2,1,psr ; psr.s is set - test_spr_bits 0x2,1,0,psr ; psr.ps not set - set_spr_addr bad,lr - set_mem_immed 0x0,gr10 ; no reset - test_mem_immed 0x0,gr10 - - ; now retest with HSR0.SA set - set_mem_immed 0,gr0 - set_gr_addr 0xff000000,gr11 - set_bctrlr_0_0 gr11 - or_spr_immed 0x00001000,hsr0 ; set HSR0.SA - -; Can't recover from hardware interrupt with enough state intact to verify it -; set_spr_addr ok4,lr -; dcf @(gr10,gr0) ; Wait for store to happen -; set_mem_immed 0x3,gr10 ; cause hardware reset -; fail -; -;ok4: ; reset should branch to reset address which should then branch here -; test_mem_immed 0x00000200,gr10 -; set_spr_addr ok5,lr -; set_mem_immed 0x2,gr10 ; cause hardware reset -; dcf @(gr10,gr0) ; Wait for store to happen -; fail -; -ok5: ; reset should branch to reset address which should then branch here -; test_mem_immed 0x00000200,gr10 - set_spr_addr ok6,lr - set_mem_immed 0x1,gr10 ; cause software reset - dcf @(gr10,gr0) ; Wait for store to happen - fail - -ok6: ; reset should branch to reset address which should then branch here - test_mem_immed 0x00000100,gr10 - test_spr_bits 0x4,2,1,psr ; psr.s is set - test_spr_bits 0x2,1,1,psr ; psr.ps is set - set_spr_addr bad,lr - set_mem_immed 0x0,gr10 ; no reset - test_mem_immed 0x0,gr10 - - pass - -bad: ; Should never get here - fail diff --git a/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs b/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs deleted file mode 100644 index ee6bea4..0000000 --- a/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs +++ /dev/null @@ -1,205 +0,0 @@ -# FRV testcase for handling of shadow registers SR0-SR4 -# mach: frv - - .include "testutils.inc" - - start - - .global tra -tra: - test_spr_bits 0x800,11,1,psr ; PSR.ESR set - test_spr_bits 0x4,2,1,psr ; PSR.S set - - ; Set up exception handler for later - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - set_spr_immed 128,lcr - set_psr_et 1 - - set_gr_immed 0x11111111,gr4 ; SGR4-7 - set_gr_immed 0x22222222,gr5 - set_gr_immed 0x33333333,gr6 - set_gr_immed 0x44444444,gr7 - set_spr_immed 0x55555555,sr0 ; UGR4-7 - set_spr_immed 0x66666666,sr1 - set_spr_immed 0x77777777,sr2 - set_spr_immed 0x88888888,sr3 - - and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - - set_spr_immed 0x55555555,sr0 ; SGR4-7 - set_spr_immed 0x66666666,sr1 - set_spr_immed 0x77777777,sr2 - set_spr_immed 0x88888888,sr3 - test_gr_immed 0x55555555,gr4 ; SGR4-7 - test_gr_immed 0x66666666,gr5 - test_gr_immed 0x77777777,gr6 - test_gr_immed 0x88888888,gr7 - test_spr_immed 0x55555555,sr0 ; SGR4-7 - test_spr_immed 0x66666666,sr1 - test_spr_immed 0x77777777,sr2 - test_spr_immed 0x88888888,sr3 - - set_gr_immed 0x11111111,gr4 ; SGR4-7 - set_gr_immed 0x22222222,gr5 - set_gr_immed 0x33333333,gr6 - set_gr_immed 0x44444444,gr7 - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - - or_spr_immed 0x00000800,psr ; turn on PSR.ESR - test_gr_immed 0x11111111,gr4 ; SGR4-7 -- SR0-3 (UGR4-7) are undefined - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - - set_spr_immed 0x55555555,sr0 ; UGR4-7 - set_spr_immed 0x66666666,sr1 - set_spr_immed 0x77777777,sr2 - set_spr_immed 0x88888888,sr3 - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x55555555,sr0 ; UGR4-7 - test_spr_immed 0x66666666,sr1 - test_spr_immed 0x77777777,sr2 - test_spr_immed 0x88888888,sr3 - - and_spr_immed 0xfffffffb,psr ; turn off PSR.S - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - test_gr_immed 0x55555555,gr4 ; UGR4-7 - test_gr_immed 0x66666666,gr5 - test_gr_immed 0x77777777,gr6 - test_gr_immed 0x88888888,gr7 - - ; need to generate a trap to return to supervisor mode - set_spr_addr ok0,lr - tira gr0,4 ; should branch to tbr + (128 + 4)*16 - - test_spr_bits 0x800,11,0,psr ; PSR.ESR clear - test_spr_bits 0x4,2,0,psr ; PSR.S clear - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - - set_gr_immed 0x55555555,gr4 ; SGR4-7 - set_gr_immed 0x66666666,gr5 - set_gr_immed 0x77777777,gr6 - set_gr_immed 0x88888888,gr7 - test_gr_immed 0x55555555,gr4 ; SGR4-7 - test_gr_immed 0x66666666,gr5 - test_gr_immed 0x77777777,gr6 - test_gr_immed 0x88888888,gr7 - test_spr_immed 0x55555555,sr0 ; SGR4-7 - test_spr_immed 0x66666666,sr1 - test_spr_immed 0x77777777,sr2 - test_spr_immed 0x88888888,sr3 - - set_gr_immed 0x11111111,gr4 ; SGR4-7 - set_gr_immed 0x22222222,gr5 - set_gr_immed 0x33333333,gr6 - set_gr_immed 0x44444444,gr7 - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - - ; need to generate a trap to return to supervisor mode - set_spr_addr ok1,lr - tira gr0,4 ; should branch to tbr + (128 + 4)*16 - - pass - -ok0: ; exception handler should branch here the first time - test_spr_bits 0x800,11,1,psr ; PSR.ESR set - test_spr_bits 0x4,2,1,psr ; PSR.S set - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x55555555,sr0 ; UGR4-7 - test_spr_immed 0x66666666,sr1 - test_spr_immed 0x77777777,sr2 - test_spr_immed 0x88888888,sr3 - - and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - rett 0 - fail - -ok1: ; exception handler should branch here the second time - test_spr_bits 0x800,11,0,psr ; PSR.ESR clear - test_spr_bits 0x4,2,1,psr ; PSR.S set - - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - - set_spr_immed 0x55555555,sr0 ; SGR4-7 - set_spr_immed 0x66666666,sr1 - set_spr_immed 0x77777777,sr2 - set_spr_immed 0x88888888,sr3 - test_gr_immed 0x55555555,gr4 ; SGR4-7 - test_gr_immed 0x66666666,gr5 - test_gr_immed 0x77777777,gr6 - test_gr_immed 0x88888888,gr7 - test_spr_immed 0x55555555,sr0 ; SGR4-7 - test_spr_immed 0x66666666,sr1 - test_spr_immed 0x77777777,sr2 - test_spr_immed 0x88888888,sr3 - - set_gr_immed 0x11111111,gr4 ; SGR4-7 - set_gr_immed 0x22222222,gr5 - set_gr_immed 0x33333333,gr6 - set_gr_immed 0x44444444,gr7 - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/timer.cgs b/sim/testsuite/sim/frv/interrupts/timer.cgs deleted file mode 100644 index e9cebc2..0000000 --- a/sim/testsuite/sim/frv/interrupts/timer.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase to generate timer interrupt for st $GRk,@($GRi,$GRj) -# mach: fr500 fr550 fr400 -# sim: --timer 200,14 - .include "testutils.inc" - - start - - .global align -align: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x2e0,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 0x7fffffff,lcr - set_spr_addr ok1,lr - and_spr_immed 0xffffff87,psr ; enable external interrupts - or_spr_immed 0x00000069,psr ; enable external interrupts - - set_gr_immed 10,gr16 - set_gr_immed 0,gr15 - -again: cmp gr15,gr16,icc0 - blt icc0,0,again - - pass - -; exception handler -ok1: - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/jmpil.cgs b/sim/testsuite/sim/frv/jmpil.cgs deleted file mode 100644 index 1d11067..0000000 --- a/sim/testsuite/sim/frv/jmpil.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# frv testcase for jmpil @($GRi,$d12) -# mach: all - - .include "testutils.inc" - - start - - .global jmpil -jmpil: - set_spr_immed 0,lr - set_gr_addr ok1,gr8 - jmpil @(gr8,2) ; target gets aligned down - fail -ok1: - test_spr_immed 0,lr - - pass diff --git a/sim/testsuite/sim/frv/jmpl.cgs b/sim/testsuite/sim/frv/jmpl.cgs deleted file mode 100644 index 9a58e60..0000000 --- a/sim/testsuite/sim/frv/jmpl.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for jmpl @($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global jmpl -jmpl: - set_spr_immed 0,lr - set_gr_addr ok1,gr8 - set_gr_immed 1,gr9 ; target gets aligned down - jmpl @(gr8,gr9) - fail -ok1: - test_spr_immed 0,lr - - pass diff --git a/sim/testsuite/sim/frv/jmpl.pcgs b/sim/testsuite/sim/frv/jmpl.pcgs deleted file mode 100644 index 2126820..0000000 --- a/sim/testsuite/sim/frv/jmpl.pcgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv parallel testcase for jmpl @($GRi,$GRj),$LI -# mach: all - - .include "testutils.inc" - - start - - .global jmpl -jmpl: - set_spr_immed 0,lr - set_gr_addr ok1,gr8 - set_gr_immed 0,gr9 - jmpl.p @(gr8,gr9) - setlos 10,gr10 - fail -ok1: - test_spr_immed 0,lr - test_gr_immed 10,gr10 - - set_gr_addr ok2,gr8 - inc_gr_immed -4,gr8 - inc_gr_immed 4,gr9 - calll.p @(gr8,gr9) - setlos 11,gr11 -bad2: - fail -ok2: - test_spr_addr bad2,lr - test_gr_immed 11,gr11 - - set_gr_addr ok3,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - setlos 12,gr12 - calll @(gr8,gr9) -bad3: - fail -ok3: - test_spr_addr bad3,lr - test_gr_immed 12,gr12 - - pass diff --git a/sim/testsuite/sim/frv/ld.cgs b/sim/testsuite/sim/frv/ld.cgs deleted file mode 100644 index 35206c2..0000000 --- a/sim/testsuite/sim/frv/ld.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for ld @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ld -ld: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - ld @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ld @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - ld @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldbf.cgs b/sim/testsuite/sim/frv/ldbf.cgs deleted file mode 100644 index 52ac077..0000000 --- a/sim/testsuite/sim/frv/ldbf.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for ldbf @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldbf -ldbf: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - ldbf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00de,fr8 - - set_gr_immed 1,gr7 - ldbf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00ad,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - ldbf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - - pass diff --git a/sim/testsuite/sim/frv/ldbfi.cgs b/sim/testsuite/sim/frv/ldbfi.cgs deleted file mode 100644 index 7e91806..0000000 --- a/sim/testsuite/sim/frv/ldbfi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for ldbfi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldbfi -ldbfi: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - ldbfi @(sp,0),fr8 - test_fr_limmed 0x0000,0x00de,fr8 - - ldbfi @(sp,1),fr8 - test_fr_limmed 0x0000,0x00ad,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - ldbfi @(sp,-1),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - - pass diff --git a/sim/testsuite/sim/frv/ldbfu.cgs b/sim/testsuite/sim/frv/ldbfu.cgs deleted file mode 100644 index 3cbfb91..0000000 --- a/sim/testsuite/sim/frv/ldbfu.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for ldbfu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldbfu -ldbfu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - ldbfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00de,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - ldbfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00ad,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - ldbfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/ldc.cgs b/sim/testsuite/sim/frv/ldc.cgs deleted file mode 100644 index 4593c31..0000000 --- a/sim/testsuite/sim/frv/ldc.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for ldc @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldc -ldc: - set_mem_limmed 0xdead,0xbeef,sp - set_cpr_limmed 0xbeef,0xdead,cpr8 - - set_gr_immed 0,gr7 - ldc @(sp,gr7),cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr8 - - set_cpr_limmed 0xbeef,0xdead,cpr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ldc @(sp,gr7),cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr8 - - set_cpr_limmed 0xbeef,0xdead,cpr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - ldc @(sp,gr7),cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr8 - - pass diff --git a/sim/testsuite/sim/frv/ldcu.cgs b/sim/testsuite/sim/frv/ldcu.cgs deleted file mode 100644 index 69890a8..0000000 --- a/sim/testsuite/sim/frv/ldcu.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for ldcu @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldcu -ldcu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_cpr_limmed 0xbeef,0xdead,cpr8 - - set_gr_immed 0,gr7 - ldcu @(sp,gr7),cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr8 - test_gr_gr sp,gr20 - - set_cpr_limmed 0xbeef,0xdead,cpr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ldcu @(sp,gr7),cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr8 - test_gr_gr sp,gr20 - - set_cpr_limmed 0xbeef,0xdead,cpr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - ldcu @(sp,gr7),cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/ldd.cgs b/sim/testsuite/sim/frv/ldd.cgs deleted file mode 100644 index fa09d31..0000000 --- a/sim/testsuite/sim/frv/ldd.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# frv testcase for ldd @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldd -ldd: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - ldd @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - ldd @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - ldd @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - ; loading into gr0 should have no effect - ; gr1 is sp - set_gr_gr gr1,gr8 - ldd @(sp,gr7),gr0 - test_gr_immed 0,gr0 - test_gr_gr gr1,gr8 - pass diff --git a/sim/testsuite/sim/frv/lddc.cgs b/sim/testsuite/sim/frv/lddc.cgs deleted file mode 100644 index e01a214..0000000 --- a/sim/testsuite/sim/frv/lddc.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for lddc @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global lddc -lddc: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - - set_gr_immed 0,gr7 - ; loading into cpr0 is business as usual - set_cpr_limmed 0xdead,0xbeef,cpr0 - set_cpr_limmed 0xbeef,0xdead,cpr1 - lddc @(sp,gr7),cpr0 - test_cpr_limmed 0xbeef,0xdead,cpr0 - test_cpr_limmed 0xdead,0xbeef,cpr1 - - lddc @(sp,gr7),cpr8 - test_cpr_limmed 0xbeef,0xdead,cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr9 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - lddc @(sp,gr7),cpr8 - test_cpr_limmed 0xbeef,0xdead,cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr9 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - lddc @(sp,gr7),cpr8 - test_cpr_limmed 0xbeef,0xdead,cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr9 - - pass diff --git a/sim/testsuite/sim/frv/lddcu.cgs b/sim/testsuite/sim/frv/lddcu.cgs deleted file mode 100644 index b4ed485..0000000 --- a/sim/testsuite/sim/frv/lddcu.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for lddcu @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global lddcu -lddcu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - - set_gr_immed 0,gr7 - lddcu @(sp,gr7),cpr8 - test_cpr_limmed 0xbeef,0xdead,cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr9 - test_gr_gr sp,gr20 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - lddcu @(sp,gr7),cpr8 - test_cpr_limmed 0xbeef,0xdead,cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr9 - test_gr_gr sp,gr20 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - lddcu @(sp,gr7),cpr8 - test_cpr_limmed 0xbeef,0xdead,cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr9 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/lddf.cgs b/sim/testsuite/sim/frv/lddf.cgs deleted file mode 100644 index f7bae78..0000000 --- a/sim/testsuite/sim/frv/lddf.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# frv testcase for lddf @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lddf -lddf: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - ; loading into fr0 is business as usual - set_fr_iimmed 0xdead,0xbeef,fr0 - set_fr_iimmed 0xbeef,0xdead,fr1 - lddf @(sp,gr7),fr0 - test_fr_limmed 0xbeef,0xdead,fr0 - test_fr_limmed 0xdead,0xbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - lddf @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - lddf @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - lddf @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - pass diff --git a/sim/testsuite/sim/frv/lddfi.cgs b/sim/testsuite/sim/frv/lddfi.cgs deleted file mode 100644 index 1eac916..0000000 --- a/sim/testsuite/sim/frv/lddfi.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for lddfi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lddfi -lddfi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - lddfi @(sp,0),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - lddfi @(sp,8),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - lddfi @(sp,-8),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - pass diff --git a/sim/testsuite/sim/frv/lddfu.cgs b/sim/testsuite/sim/frv/lddfu.cgs deleted file mode 100644 index cb4c86e..0000000 --- a/sim/testsuite/sim/frv/lddfu.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# frv testcase for lddfu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lddfu -lddfu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - lddfu @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - lddfu @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - lddfu @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/lddi.cgs b/sim/testsuite/sim/frv/lddi.cgs deleted file mode 100644 index 38ef2b4..0000000 --- a/sim/testsuite/sim/frv/lddi.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for lddi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lddi -lddi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - lddi @(sp,0),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - lddi @(sp,8),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - lddi @(sp,-8),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - pass diff --git a/sim/testsuite/sim/frv/lddu.cgs b/sim/testsuite/sim/frv/lddu.cgs deleted file mode 100644 index 5b2ead1..0000000 --- a/sim/testsuite/sim/frv/lddu.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for lddu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lddu -lddu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - lddu @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - lddu @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - lddu @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - set_gr_gr sp,gr8 - lddu @(gr8,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - pass diff --git a/sim/testsuite/sim/frv/ldf.cgs b/sim/testsuite/sim/frv/ldf.cgs deleted file mode 100644 index 996d72c..0000000 --- a/sim/testsuite/sim/frv/ldf.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for ldf @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldf -ldf: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - ldf @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ldf @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - ldf @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/ldfi.cgs b/sim/testsuite/sim/frv/ldfi.cgs deleted file mode 100644 index e5ea94d..0000000 --- a/sim/testsuite/sim/frv/ldfi.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for ldfi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldfi -ldfi: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - ldfi @(sp,0),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - ldfi @(sp,4),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - ldfi @(sp,-4),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/ldfu.cgs b/sim/testsuite/sim/frv/ldfu.cgs deleted file mode 100644 index 08f67db..0000000 --- a/sim/testsuite/sim/frv/ldfu.cgs +++ /dev/null @@ -1,33 +0,0 @@ -# frv testcase for ldfu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldfu -ldfu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - ldfu @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ldfu @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - ldfu @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/ldhf.cgs b/sim/testsuite/sim/frv/ldhf.cgs deleted file mode 100644 index 8935ac7..0000000 --- a/sim/testsuite/sim/frv/ldhf.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for ldhf @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldhf -ldhf: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - ldhf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xdead,fr8 - - set_gr_immed 2,gr7 - ldhf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xbeef,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - ldhf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - - pass diff --git a/sim/testsuite/sim/frv/ldhfi.cgs b/sim/testsuite/sim/frv/ldhfi.cgs deleted file mode 100644 index 362ec50..0000000 --- a/sim/testsuite/sim/frv/ldhfi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for ldhfi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldhfi -ldhfi: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - ldhfi @(sp,0),fr8 - test_fr_limmed 0x0000,0xdead,fr8 - - ldhfi @(sp,2),fr8 - test_fr_limmed 0x0000,0xbeef,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - ldhfi @(sp,-2),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - - pass diff --git a/sim/testsuite/sim/frv/ldhfu.cgs b/sim/testsuite/sim/frv/ldhfu.cgs deleted file mode 100644 index 0b342e1..0000000 --- a/sim/testsuite/sim/frv/ldhfu.cgs +++ /dev/null @@ -1,33 +0,0 @@ -# frv testcase for ldhfu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldhfu -ldhfu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - ldhfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - ldhfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xbeef,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - ldhfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/ldi.cgs b/sim/testsuite/sim/frv/ldi.cgs deleted file mode 100644 index f36b95d..0000000 --- a/sim/testsuite/sim/frv/ldi.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for ldi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldi -ldi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - ldi @(sp,0),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - ldi @(sp,4),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - ldi @(sp,-4),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldq.cgs b/sim/testsuite/sim/frv/ldq.cgs deleted file mode 100644 index e61f1de..0000000 --- a/sim/testsuite/sim/frv/ldq.cgs +++ /dev/null @@ -1,64 +0,0 @@ -# frv testcase for ldq @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global ldq -ldq: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - ldq @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - ldq @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - ldq @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - ; loading into gr0 has no effect - ; gr1 is sp - set_gr_gr gr1,gr8 - set_gr_limmed 0x1234,0x5678,gr2 - set_gr_limmed 0x9abc,0xdef0,gr3 - ldq @(sp,gr7),gr0 - test_gr_immed 0,gr0 - test_gr_gr gr1,gr8 - set_gr_immed 0x12345678,gr2 - set_gr_immed 0x9abcdef0,gr3 - - pass diff --git a/sim/testsuite/sim/frv/ldqc.cgs b/sim/testsuite/sim/frv/ldqc.cgs deleted file mode 100644 index 64b6a6a..0000000 --- a/sim/testsuite/sim/frv/ldqc.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for ldqc @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global ldqc -ldqc: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - set_cpr_limmed 0x1234,0x5678,cpr10 - set_cpr_limmed 0x9abc,0xdef0,cpr11 - - set_gr_immed 0,gr7 - ;loading into cpr0 is business as usual - ldqc @(sp,gr7),cpr0 - test_cpr_limmed 0x9abc,0xdef0,cpr0 - test_cpr_limmed 0x1234,0x5678,cpr1 - test_cpr_limmed 0xbeef,0xdead,cpr2 - test_cpr_limmed 0xdead,0xbeef,cpr3 - - ldqc @(sp,gr7),cpr8 - test_cpr_limmed 0x9abc,0xdef0,cpr8 - test_cpr_limmed 0x1234,0x5678,cpr9 - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - set_cpr_limmed 0x1234,0x5678,cpr10 - set_cpr_limmed 0x9abc,0xdef0,cpr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - ldqc @(sp,gr7),cpr8 - test_cpr_limmed 0x9abc,0xdef0,cpr8 - test_cpr_limmed 0x1234,0x5678,cpr9 - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - set_cpr_limmed 0x1234,0x5678,cpr10 - set_cpr_limmed 0x9abc,0xdef0,cpr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - ldqc @(sp,gr7),cpr8 - test_cpr_limmed 0x9abc,0xdef0,cpr8 - test_cpr_limmed 0x1234,0x5678,cpr9 - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - - pass diff --git a/sim/testsuite/sim/frv/ldqcu.cgs b/sim/testsuite/sim/frv/ldqcu.cgs deleted file mode 100644 index 18d9246..0000000 --- a/sim/testsuite/sim/frv/ldqcu.cgs +++ /dev/null @@ -1,57 +0,0 @@ -# frv testcase for ldqcu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global ldqcu -ldqcu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - set_cpr_limmed 0x1234,0x5678,cpr10 - set_cpr_limmed 0x9abc,0xdef0,cpr11 - - set_gr_immed 0,gr7 - ldqcu @(sp,gr7),cpr8 - test_cpr_limmed 0x9abc,0xdef0,cpr8 - test_cpr_limmed 0x1234,0x5678,cpr9 - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - test_gr_gr sp,gr20 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - set_cpr_limmed 0x1234,0x5678,cpr10 - set_cpr_limmed 0x9abc,0xdef0,cpr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - ldqcu @(sp,gr7),cpr8 - test_cpr_limmed 0x9abc,0xdef0,cpr8 - test_cpr_limmed 0x1234,0x5678,cpr9 - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - test_gr_gr sp,gr20 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - set_cpr_limmed 0x1234,0x5678,cpr10 - set_cpr_limmed 0x9abc,0xdef0,cpr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - ldqcu @(sp,gr7),cpr8 - test_cpr_limmed 0x9abc,0xdef0,cpr8 - test_cpr_limmed 0x1234,0x5678,cpr9 - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/ldqf.cgs b/sim/testsuite/sim/frv/ldqf.cgs deleted file mode 100644 index 66fb65c..0000000 --- a/sim/testsuite/sim/frv/ldqf.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for ldqf @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldqf -ldqf: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - - set_gr_immed 0,gr7 - ; loading into fr0 is business as usual - ldqf @(sp,gr7),fr0 - test_fr_limmed 0x9abc,0xdef0,fr0 - test_fr_limmed 0x1234,0x5678,fr1 - test_fr_limmed 0xbeef,0xdead,fr2 - test_fr_limmed 0xdead,0xbeef,fr3 - - ldqf @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - ldqf @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - ldqf @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - - pass diff --git a/sim/testsuite/sim/frv/ldqfi.cgs b/sim/testsuite/sim/frv/ldqfi.cgs deleted file mode 100644 index 28c3b1f..0000000 --- a/sim/testsuite/sim/frv/ldqfi.cgs +++ /dev/null @@ -1,51 +0,0 @@ -# frv testcase for ldqfi @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldqfi -ldqfi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - - ldqfi @(sp,0),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed -16,sp - ldqfi @(sp,16),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed 32,sp - ldqfi @(sp,-16),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - - pass diff --git a/sim/testsuite/sim/frv/ldqfu.cgs b/sim/testsuite/sim/frv/ldqfu.cgs deleted file mode 100644 index 7287958..0000000 --- a/sim/testsuite/sim/frv/ldqfu.cgs +++ /dev/null @@ -1,58 +0,0 @@ -# frv testcase for ldqfu @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldqfu -ldqfu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - - set_gr_immed 0,gr7 - ldqfu @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - ldqfu @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - ldqfu @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/ldqi.cgs b/sim/testsuite/sim/frv/ldqi.cgs deleted file mode 100644 index 64d66f2..0000000 --- a/sim/testsuite/sim/frv/ldqi.cgs +++ /dev/null @@ -1,51 +0,0 @@ -# frv testcase for ldqi @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldqi -ldqi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - ldqi @(sp,0),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - ldqi @(sp,16),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - ldqi @(sp,-16),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - pass diff --git a/sim/testsuite/sim/frv/ldqu.cgs b/sim/testsuite/sim/frv/ldqu.cgs deleted file mode 100644 index 263eae1..0000000 --- a/sim/testsuite/sim/frv/ldqu.cgs +++ /dev/null @@ -1,71 +0,0 @@ -# frv testcase for ldqu @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldqu -ldqu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - ldqu @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - ldqu @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - ldqu @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - set_gr_gr sp,gr8 - ldqu @(gr8,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - pass diff --git a/sim/testsuite/sim/frv/ldsb.cgs b/sim/testsuite/sim/frv/ldsb.cgs deleted file mode 100644 index 4b10639..0000000 --- a/sim/testsuite/sim/frv/ldsb.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for ldsb @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldsb -ldsb: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - ldsb @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffde,gr8 - - set_gr_immed 1,gr7 - ldsb @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - ldsb @(sp,gr7),gr8 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldsbi.cgs b/sim/testsuite/sim/frv/ldsbi.cgs deleted file mode 100644 index c90a129..0000000 --- a/sim/testsuite/sim/frv/ldsbi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for ldsbi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldsbi -ldsbi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - ldsbi @(sp,0),gr8 - test_gr_limmed 0xffff,0xffde,gr8 - - ldsbi @(sp,1),gr8 - test_gr_limmed 0xffff,0xffad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - ldsbi @(sp,-1),gr8 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldsbu.cgs b/sim/testsuite/sim/frv/ldsbu.cgs deleted file mode 100644 index 976cee8..0000000 --- a/sim/testsuite/sim/frv/ldsbu.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# frv testcase for ldsbu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldsbu -ldsbu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - ldsbu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffde,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - ldsbu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffad,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - ldsbu @(sp,gr7),gr8 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -3,sp - set_mem_limmed 0x0000,0x00da,sp - set_gr_immed 3,gr7 - ldsbu @(sp,gr7),sp - test_gr_limmed 0xffff,0xffda,sp - - pass diff --git a/sim/testsuite/sim/frv/ldsh.cgs b/sim/testsuite/sim/frv/ldsh.cgs deleted file mode 100644 index c526f39..0000000 --- a/sim/testsuite/sim/frv/ldsh.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for ldsh @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldsh -ldsh: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - ldsh @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xdead,gr8 - - set_gr_immed 2,gr7 - ldsh @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - ldsh @(sp,gr7),gr8 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldshi.cgs b/sim/testsuite/sim/frv/ldshi.cgs deleted file mode 100644 index 69f99f1..0000000 --- a/sim/testsuite/sim/frv/ldshi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for ldshi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldshi -ldshi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - ldshi @(sp,0),gr8 - test_gr_limmed 0xffff,0xdead,gr8 - - ldshi @(sp,2),gr8 - test_gr_limmed 0xffff,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - ldshi @(sp,-2),gr8 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldshu.cgs b/sim/testsuite/sim/frv/ldshu.cgs deleted file mode 100644 index f1b8c23..0000000 --- a/sim/testsuite/sim/frv/ldshu.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for ldshu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldshu -ldshu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - ldshu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - ldshu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xbeef,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - ldshu @(sp,gr7),gr8 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0x0000,0xdead,sp - set_gr_immed 2,gr7 - ldshu @(sp,gr7),sp - test_gr_limmed 0xffff,0xdead,sp - - pass diff --git a/sim/testsuite/sim/frv/ldu.cgs b/sim/testsuite/sim/frv/ldu.cgs deleted file mode 100644 index b7f2e34..0000000 --- a/sim/testsuite/sim/frv/ldu.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for ldu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldu -ldu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - ldu @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ldu @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - ldu @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ldu @(sp,gr7),sp - test_gr_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/ldub.cgs b/sim/testsuite/sim/frv/ldub.cgs deleted file mode 100644 index 1e19254..0000000 --- a/sim/testsuite/sim/frv/ldub.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for ldub @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldub -ldub: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - ldub @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00de,gr8 - - set_gr_immed 1,gr7 - ldub @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00ad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - ldub @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldubi.cgs b/sim/testsuite/sim/frv/ldubi.cgs deleted file mode 100644 index 4c40bee..0000000 --- a/sim/testsuite/sim/frv/ldubi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for ldubi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldubi -ldubi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - ldubi @(sp,0),gr8 - test_gr_limmed 0x0000,0x00de,gr8 - - ldubi @(sp,1),gr8 - test_gr_limmed 0x0000,0x00ad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - ldubi @(sp,-1),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldubu.cgs b/sim/testsuite/sim/frv/ldubu.cgs deleted file mode 100644 index 8c99ab0..0000000 --- a/sim/testsuite/sim/frv/ldubu.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for ldubu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldubu -ldubu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - ldubu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00de,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - ldubu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00ad,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - ldubu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - - inc_gr_immed -3,sp - set_mem_limmed 0xffff,0xffda,sp - set_gr_immed 3,gr7 - ldubu @(sp,gr7),sp - test_gr_limmed 0x0000,0x00da,sp - - pass diff --git a/sim/testsuite/sim/frv/lduh.cgs b/sim/testsuite/sim/frv/lduh.cgs deleted file mode 100644 index 24c3bac..0000000 --- a/sim/testsuite/sim/frv/lduh.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for lduh @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lduh -lduh: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - lduh @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xdead,gr8 - - set_gr_immed 2,gr7 - lduh @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - lduh @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/lduhi.cgs b/sim/testsuite/sim/frv/lduhi.cgs deleted file mode 100644 index b9896d6..0000000 --- a/sim/testsuite/sim/frv/lduhi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for lduhi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lduhi -lduhi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - lduhi @(sp,0),gr8 - test_gr_limmed 0x0000,0xdead,gr8 - - lduhi @(sp,2),gr8 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - lduhi @(sp,-2),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/lduhu.cgs b/sim/testsuite/sim/frv/lduhu.cgs deleted file mode 100644 index 52faecf..0000000 --- a/sim/testsuite/sim/frv/lduhu.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for lduhu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lduhu -lduhu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - lduhu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - lduhu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xbeef,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - lduhu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0xdead,sp - set_gr_immed 2,gr7 - lduhu @(sp,gr7),sp - test_gr_limmed 0x0000,0xdead,sp - - pass diff --git a/sim/testsuite/sim/frv/lrbranch.pcgs b/sim/testsuite/sim/frv/lrbranch.pcgs deleted file mode 100644 index 0ac1a75..0000000 --- a/sim/testsuite/sim/frv/lrbranch.pcgs +++ /dev/null @@ -1,51 +0,0 @@ -# frv parallel testcase for lr branching -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global lrbranch -lrbranch: - ; Both conditions true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x4 0 - bcgelr.p icc0,0,0 - bra ok4 - fail -ok1: - test_spr_immed 127,LCR - - ; Only first condition true - set_spr_immed 128,lcr - set_spr_addr ok2,lr - set_icc 0x0 0 - bcgelr.p icc0,0,0 - bno - fail -ok2: - test_spr_immed 127,LCR - - ; Only second condition true - set_spr_immed 128,lcr - set_spr_addr ok3,lr - set_icc 0x8 0 - bcgelr.p icc0,0,0 - bra ok3 - fail -ok3: - test_spr_immed 127,LCR - - ; Both conditions false - set_spr_immed 128,lcr - set_spr_addr ok4,lr - set_icc 0x0 0 - bceqlr.p icc0,0,0 - bno - test_spr_immed 127,LCR - - pass - -ok4: - fail diff --git a/sim/testsuite/sim/frv/mabshs.cgs b/sim/testsuite/sim/frv/mabshs.cgs deleted file mode 100644 index 29b2532..0000000 --- a/sim/testsuite/sim/frv/mabshs.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# frv testcase for mabshs $FRj,$FRk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mabshs -mabshs: - set_fr_iimmed 0x0000,0x0000,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x0000,0x0000,fr11 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0xffff,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x0001,0x0001,fr11 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7fff,0x8001,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x7fff,0x7fff,fr11 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7fff,0x8000,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x7fff,0x7fff,fr11 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8000,0x7fff,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x7fff,0x7fff,fr11 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - mabshs.p fr10,fr12 - mabshs fr11,fr13 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/maddhss.cgs b/sim/testsuite/sim/frv/maddhss.cgs deleted file mode 100644 index 289ecc77..0000000 --- a/sim/testsuite/sim/frv/maddhss.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for maddhss $FRi,$FRj,$FRj -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global maddhss -maddhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maddhss fr10,fr11,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maddhss.p fr10,fr10,fr12 - maddhss fr11,fr11,fr13 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/maddhus.cgs b/sim/testsuite/sim/frv/maddhus.cgs deleted file mode 100644 index fe96e69..0000000 --- a/sim/testsuite/sim/frv/maddhus.cgs +++ /dev/null @@ -1,89 +0,0 @@ -# frv testcase for maddhus $FRi,$FRj,$FRj -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global maddhus -maddhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0x8000,0x7fff,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - maddhus.p fr10,fr10,fr12 - maddhus fr11,fr11,fr13 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0xffff,0xffff,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/mand.cgs b/sim/testsuite/sim/frv/mand.cgs deleted file mode 100644 index c6aa993..0000000 --- a/sim/testsuite/sim/frv/mand.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for mand $FRinti,$FRintj,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mand -mand: - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - mand fr7,fr8,fr8 - test_fr_iimmed 0,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - mand fr7,fr8,fr8 - test_fr_iimmed 0xaaaa0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - mand fr7,fr8,fr8 - test_fr_iimmed 0x0000aaaa,fr8 - - pass diff --git a/sim/testsuite/sim/frv/maveh.cgs b/sim/testsuite/sim/frv/maveh.cgs deleted file mode 100644 index d48ad72..0000000 --- a/sim/testsuite/sim/frv/maveh.cgs +++ /dev/null @@ -1,72 +0,0 @@ -# frv testcase for maveh $FRi,$FRj,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global maveh -maveh: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x0000,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0001,0x0000,fr12 - - set_fr_iimmed 0x0000,0xffff,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xffff,0xfffe,fr12 - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xef56,0xdf77,fr12 - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xdf77,0xef56,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x11a2,0x33c4,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0919,0x2b3b,fr12 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x4000,0x3fff,fr12 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xbfff,fr12 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xbfff,0xbfff,fr12 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maveh.p fr10,fr10,fr12 - maveh fr11,fr11,fr13 - test_fr_limmed 0x8000,0x8000,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - - pass diff --git a/sim/testsuite/sim/frv/mbtoh.cgs b/sim/testsuite/sim/frv/mbtoh.cgs deleted file mode 100644 index 52895ad..0000000 --- a/sim/testsuite/sim/frv/mbtoh.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# frv testcase for mbtoh $FRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mbtoh -mbtoh: - set_fr_iimmed 0xdead,0xbeef,fr10 - mbtoh fr10,fr12 - test_fr_limmed 0x00de,0x00ad,fr12 - test_fr_limmed 0x00be,0x00ef,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - mbtoh fr10,fr12 - test_fr_limmed 0x0012,0x0034,fr12 - test_fr_limmed 0x0056,0x0078,fr13 - - pass diff --git a/sim/testsuite/sim/frv/mbtohe.cgs b/sim/testsuite/sim/frv/mbtohe.cgs deleted file mode 100644 index 1e978ec..0000000 --- a/sim/testsuite/sim/frv/mbtohe.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for mbtohe $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - start - - .global mbtohe -mbtohe: - set_fr_iimmed 0xdead,0xbeef,fr10 - mbtohe fr10,fr12 - test_fr_limmed 0x00de,0x00de,fr12 - test_fr_limmed 0x00ad,0x00ad,fr13 - test_fr_limmed 0x00be,0x00be,fr14 - test_fr_limmed 0x00ef,0x00ef,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - mbtohe fr10,fr12 - test_fr_limmed 0x0012,0x0012,fr12 - test_fr_limmed 0x0034,0x0034,fr13 - test_fr_limmed 0x0056,0x0056,fr14 - test_fr_limmed 0x0078,0x0078,fr15 - - pass diff --git a/sim/testsuite/sim/frv/mclracc.cgs b/sim/testsuite/sim/frv/mclracc.cgs deleted file mode 100644 index 7972b9a..0000000 --- a/sim/testsuite/sim/frv/mclracc.cgs +++ /dev/null @@ -1,79 +0,0 @@ -# frv testcase for mclracc $ACC40k,$A -# mach: frv - - .include "testutils.inc" - - start - - .global mclracc -mclracc: - set_accg_immed 0xff,accg0 - set_acc_immed -1,acc0 - set_accg_immed 0xff,accg8 - set_acc_immed -1,acc8 - set_accg_immed 0xff,accg31 - set_acc_immed -1,acc31 - set_accg_immed 0xff,accg62 - set_acc_immed -1,acc62 - - mclracc acc63,0 ; nop - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg8 - test_acc_immed -1,acc8 - test_accg_immed 0xff,accg31 - test_acc_immed -1,acc31 - test_accg_immed 0xff,accg62 - test_acc_immed -1,acc62 - - mclracc acc63,1 ; nop - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg8 - test_acc_immed -1,acc8 - test_accg_immed 0xff,accg31 - test_acc_immed -1,acc31 - test_accg_immed 0xff,accg62 - test_acc_immed -1,acc62 - - mclracc acc31,0 - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg8 - test_acc_immed -1,acc8 - test_accg_immed 0,accg31 - test_acc_immed 0,acc31 - test_accg_immed 0xff,accg62 - test_acc_immed -1,acc62 - - mclracc acc62,1 - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg8 - test_acc_immed -1,acc8 - test_accg_immed 0,accg31 - test_acc_immed 0,acc31 - test_accg_immed 0,accg62 - test_acc_immed 0,acc62 - - mclracc acc0,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0xff,accg8 - test_acc_immed -1,acc8 - test_accg_immed 0,accg31 - test_acc_immed 0,acc31 - test_accg_immed 0,accg62 - test_acc_immed 0,acc62 - - mclracc acc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg8 - test_acc_immed 0,acc8 - test_accg_immed 0,accg31 - test_acc_immed 0,acc31 - test_accg_immed 0,accg62 - test_acc_immed 0,acc62 - - pass diff --git a/sim/testsuite/sim/frv/mcmpsh.cgs b/sim/testsuite/sim/frv/mcmpsh.cgs deleted file mode 100644 index 50e986d..0000000 --- a/sim/testsuite/sim/frv/mcmpsh.cgs +++ /dev/null @@ -1,138 +0,0 @@ -# frv testcase for mcmpsh $FRi,$FRj,$FCCk -# mach: all - - .include "testutils.inc" - - start - - .global mcmpsh -mcmpsh: - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - pass diff --git a/sim/testsuite/sim/frv/mcmpuh.cgs b/sim/testsuite/sim/frv/mcmpuh.cgs deleted file mode 100644 index a6670b7..0000000 --- a/sim/testsuite/sim/frv/mcmpuh.cgs +++ /dev/null @@ -1,138 +0,0 @@ -# frv testcase for mcmpuh $FRi,$FRj,$FCCk -# mach: all - - .include "testutils.inc" - - start - - .global mcmpuh -mcmpuh: - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - pass diff --git a/sim/testsuite/sim/frv/mcop1.cgs b/sim/testsuite/sim/frv/mcop1.cgs deleted file mode 100644 index 5405456..0000000 --- a/sim/testsuite/sim/frv/mcop1.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# frv testcase for mcop1 $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - start - - .global mcop1 -mcop1: - mcop1.p fr19,fr12,fr13 ; mp_exception: not-implemented - mcop1 fr20,fr14,fr18 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mcop1.p fr19,fr12,fr13 ; mp_exception: not-implemented - mcop1 fr20,fr14,fr18 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mcop1 fr19,fr12,fr13 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mcop1 fr19,fr12,fr13 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - pass diff --git a/sim/testsuite/sim/frv/mcop2.cgs b/sim/testsuite/sim/frv/mcop2.cgs deleted file mode 100644 index f423a3e..0000000 --- a/sim/testsuite/sim/frv/mcop2.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# frv testcase for mcop2 $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - start - - .global mcop2 -mcop2: - mcop2.p fr19,fr12,fr13 ; mp_exception: not-implemented - mcop2 fr20,fr14,fr18 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mcop2.p fr19,fr12,fr13 ; mp_exception: not-implemented - mcop2 fr20,fr14,fr18 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mcop2 fr19,fr12,fr13 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mcop2 fr19,fr12,fr13 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - pass diff --git a/sim/testsuite/sim/frv/mcplhi.cgs b/sim/testsuite/sim/frv/mcplhi.cgs deleted file mode 100644 index d1a52eb..0000000 --- a/sim/testsuite/sim/frv/mcplhi.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for mcplhi $FRi,$s6,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global mcplhi -mcplhi: - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x0,fr10 ; Shift by 0 - test_fr_iimmed 0xdead5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x1,fr10 ; Shift by 1 - test_fr_iimmed 0xbd5b5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x4,fr10 ; Shift by 4 - test_fr_iimmed 0xeadf5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0xc,fr10 ; Shift by 12 - test_fr_iimmed 0xdeef5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0xf,fr10 ; Shift by 15 - test_fr_iimmed 0xbeef5678,fr10 - - ; test again with truncated shift values - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x10,fr10 ; Shift by 0 - test_fr_iimmed 0xdead5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x21,fr10 ; Shift by 1 - test_fr_iimmed 0xbd5b5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x34,fr10 ; Shift by 4 - test_fr_iimmed 0xeadf5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x1c,fr10 ; Shift by 12 - test_fr_iimmed 0xdeef5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x2f,fr10 ; Shift by 15 - test_fr_iimmed 0xbeef5678,fr10 - - pass diff --git a/sim/testsuite/sim/frv/mcpli.cgs b/sim/testsuite/sim/frv/mcpli.cgs deleted file mode 100644 index b63ec67..0000000 --- a/sim/testsuite/sim/frv/mcpli.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for mcpli $FRi,$s6,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global mcpli -mcpli: - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x0,fr10 ; Shift by 0 - test_fr_iimmed 0xdeadbeef,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x1,fr10 ; Shift by 1 - test_fr_iimmed 0xbd5b7ddf,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x4,fr10 ; Shift by 4 - test_fr_iimmed 0xeadbeefd,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0xc,fr10 ; Shift by 12 - test_fr_iimmed 0xdbeefead,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x1c,fr10 ; Shift by 28 - test_fr_iimmed 0xfeefdead,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x1f,fr10 ; Shift by 31 - test_fr_iimmed 0xbeefdead,fr10 - - ; test again with truncated shift values - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x20,fr10 ; Shift by 0 - test_fr_iimmed 0xdeadbeef,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x21,fr10 ; Shift by 1 - test_fr_iimmed 0xbd5b7ddf,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x24,fr10 ; Shift by 4 - test_fr_iimmed 0xeadbeefd,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x2c,fr10 ; Shift by 12 - test_fr_iimmed 0xdbeefead,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x3c,fr10 ; Shift by 28 - test_fr_iimmed 0xfeefdead,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x3f,fr10 ; Shift by 31 - test_fr_iimmed 0xbeefdead,fr10 - - pass diff --git a/sim/testsuite/sim/frv/mcpxis.cgs b/sim/testsuite/sim/frv/mcpxis.cgs deleted file mode 100644 index c3dad01..0000000 --- a/sim/testsuite/sim/frv/mcpxis.cgs +++ /dev/null @@ -1,115 +0,0 @@ -# frv testcase for mcpxis $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mcpxis -mcpxis: - ; Positive operands - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - - set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xc000,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -9,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - - set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result - set_fr_iimmed 0xffff,0xfffe,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbfff,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0x8001,0x0000,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x8000,0x0000,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - - pass diff --git a/sim/testsuite/sim/frv/mcpxiu.cgs b/sim/testsuite/sim/frv/mcpxiu.cgs deleted file mode 100644 index 198f056..0000000 --- a/sim/testsuite/sim/frv/mcpxiu.cgs +++ /dev/null @@ -1,76 +0,0 @@ -# frv testcase for mcpxiu $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mcpxiu -mcpxiu: - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 5,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7fff,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,2,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8001,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x00010001,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 1,accg0 - test_acc_immed 0xfffb0003,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 1,accg0 - test_acc_immed 0xfffc0002,acc0 - - pass diff --git a/sim/testsuite/sim/frv/mcpxrs.cgs b/sim/testsuite/sim/frv/mcpxrs.cgs deleted file mode 100644 index 1d62a96..0000000 --- a/sim/testsuite/sim/frv/mcpxrs.cgs +++ /dev/null @@ -1,115 +0,0 @@ -# frv testcase for mcpxrs $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mcpxrs -mcpxrs: - ; Positive operands - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ff0,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x4000,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -3,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbff0,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8006,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0x8000,0x8000,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x7fff,0x8000,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - - pass diff --git a/sim/testsuite/sim/frv/mcpxru.cgs b/sim/testsuite/sim/frv/mcpxru.cgs deleted file mode 100644 index 8a54392..0000000 --- a/sim/testsuite/sim/frv/mcpxru.cgs +++ /dev/null @@ -1,94 +0,0 @@ -# frv testcase for mcpxru $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mcpxru -mcpxru: - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 14,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffd,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xffff,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x0001ffff,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - mcpxru fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - mcpxru fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - mcpxru fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - pass diff --git a/sim/testsuite/sim/frv/mcut.cgs b/sim/testsuite/sim/frv/mcut.cgs deleted file mode 100644 index d6211ab..0000000 --- a/sim/testsuite/sim/frv/mcut.cgs +++ /dev/null @@ -1,509 +0,0 @@ -# frv testcase for mcut $ACC40i,$FRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mcut -mcut: - set_accg_immed 0xffffffe7,accg0 - set_acc_immed 0x89abcdef,acc0 - - set_fr_iimmed 0,0,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe789abcd,fr11 - - set_fr_iimmed 0,1,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xcf13579b,fr11 - - set_fr_iimmed 0,2,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x9e26af37,fr11 - - set_fr_iimmed 0,3,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x3c4d5e6f,fr11 - - set_fr_iimmed 0,4,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x789abcde,fr11 - - set_fr_iimmed 0,5,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xf13579bd,fr11 - - set_fr_iimmed 0,6,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe26af37b,fr11 - - set_fr_iimmed 0,7,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xc4d5e6f7,fr11 - - set_fr_iimmed 0,8,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x89abcdef,fr11 - - set_fr_iimmed 0,9,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x13579bde,fr11 - - set_fr_iimmed 0,10,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x26af37bc,fr11 - - set_fr_iimmed 0,11,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x4d5e6f78,fr11 - - set_fr_iimmed 0,12,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x9abcdef0,fr11 - - set_fr_iimmed 0,13,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x3579bde0,fr11 - - set_fr_iimmed 0,14,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x6af37bc0,fr11 - - set_fr_iimmed 0,15,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xd5e6f780,fr11 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xabcdef00,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x579bde00,fr11 - - set_fr_iimmed 0,18,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xaf37bc00,fr11 - - set_fr_iimmed 0,19,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x5e6f7800,fr11 - - set_fr_iimmed 0,20,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xbcdef000,fr11 - - set_fr_iimmed 0,21,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x79bde000,fr11 - - set_fr_iimmed 0,22,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xf37bc000,fr11 - - set_fr_iimmed 0,23,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe6f78000,fr11 - - set_fr_iimmed 0,24,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xcdef0000,fr11 - - set_fr_iimmed 0,25,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x9bde0000,fr11 - - set_fr_iimmed 0,26,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x37bc0000,fr11 - - set_fr_iimmed 0,27,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x6f780000,fr11 - - set_fr_iimmed 0,28,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xdef00000,fr11 - - set_fr_iimmed 0,29,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xbde00000,fr11 - - set_fr_iimmed 0,30,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x7bc00000,fr11 - - set_fr_iimmed 0,31,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xf7800000,fr11 - - set_fr_iimmed 0,31,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xf7800000,fr11 - - set_fr_iimmed 0,64,fr10 ; same as 0 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe789abcd,fr11 - - set_fr_iimmed 0xffff,0xffff,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xf3c4d5e6,fr11 - - set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter - mcut acc0,fr10,fr11 - test_fr_iimmed 0xf9e26af3,fr11 - - set_fr_iimmed 0xffff,0xfffd,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfcf13579,fr11 - - set_fr_iimmed 0xffff,0xfffc,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfe789abc,fr11 - - set_fr_iimmed 0xffff,0xfffb,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xff3c4d5e,fr11 - - set_fr_iimmed 0xffff,0xfffa,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xff9e26af,fr11 - - set_fr_iimmed 0xffff,0xfff9,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffcf1357,fr11 - - set_fr_iimmed 0xffff,0xfff8,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffe789ab,fr11 - - set_fr_iimmed 0xffff,0xfff7,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfff3c4d5,fr11 - - set_fr_iimmed 0xffff,0xfff6,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfff9e26a,fr11 - - set_fr_iimmed 0xffff,0xfff5,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffcf135,fr11 - - set_fr_iimmed 0xffff,0xfff4,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffe789a,fr11 - - set_fr_iimmed 0xffff,0xfff3,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffff3c4d,fr11 - - set_fr_iimmed 0xffff,0xfff2,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffff9e26,fr11 - - set_fr_iimmed 0xffff,0xfff1,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffcf13,fr11 - - set_fr_iimmed 0xffff,0xfff0,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffe789,fr11 - - set_fr_iimmed 0xffff,0xffef,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffff3c4,fr11 - - set_fr_iimmed 0xffff,0xffee,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffff9e2,fr11 - - set_fr_iimmed 0xffff,0xffed,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffffcf1,fr11 - - set_fr_iimmed 0xffff,0xffec,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffffe78,fr11 - - set_fr_iimmed 0xffff,0xffeb,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffff3c,fr11 - - set_fr_iimmed 0xffff,0xffea,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffff9e,fr11 - - set_fr_iimmed 0xffff,0xffe9,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffcf,fr11 - - set_fr_iimmed 0xffff,0xffe8,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffe7,fr11 - - set_fr_iimmed 0xffff,0xffe7,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffffff3,fr11 - - set_fr_iimmed 0xffff,0xffe6,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffffff9,fr11 - - set_fr_iimmed 0xffff,0xffe5,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffffffc,fr11 - - set_fr_iimmed 0xffff,0xffe4,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffffffe,fr11 - - set_fr_iimmed 0xffff,0xffe3,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0xffff,0xffe2,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0xffff,0xffe1,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0xffff,0xffe0,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0,32,fr10 ; same as -32 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_accg_immed 0xffffff67,accg0 - set_acc_immed 0x89abcdef,acc0 - - set_fr_iimmed 0xffff,0xffff,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x33c4d5e6,fr11 - - set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter - mcut acc0,fr10,fr11 - test_fr_iimmed 0x19e26af3,fr11 - - set_fr_iimmed 0xffff,0xfffd,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0cf13579,fr11 - - set_fr_iimmed 0xffff,0xfffc,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x06789abc,fr11 - - set_fr_iimmed 0xffff,0xfffb,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x033c4d5e,fr11 - - set_fr_iimmed 0xffff,0xfffa,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x019e26af,fr11 - - set_fr_iimmed 0xffff,0xfff9,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00cf1357,fr11 - - set_fr_iimmed 0xffff,0xfff8,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x006789ab,fr11 - - set_fr_iimmed 0xffff,0xfff7,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0033c4d5,fr11 - - set_fr_iimmed 0xffff,0xfff6,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0019e26a,fr11 - - set_fr_iimmed 0xffff,0xfff5,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x000cf135,fr11 - - set_fr_iimmed 0xffff,0xfff4,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0006789a,fr11 - - set_fr_iimmed 0xffff,0xfff3,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00033c4d,fr11 - - set_fr_iimmed 0xffff,0xfff2,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00019e26,fr11 - - set_fr_iimmed 0xffff,0xfff1,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0000cf13,fr11 - - set_fr_iimmed 0xffff,0xfff0,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00006789,fr11 - - set_fr_iimmed 0xffff,0xffef,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x000033c4,fr11 - - set_fr_iimmed 0xffff,0xffee,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x000019e2,fr11 - - set_fr_iimmed 0xffff,0xffed,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000cf1,fr11 - - set_fr_iimmed 0xffff,0xffec,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000678,fr11 - - set_fr_iimmed 0xffff,0xffeb,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0000033c,fr11 - - set_fr_iimmed 0xffff,0xffea,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0000019e,fr11 - - set_fr_iimmed 0xffff,0xffe9,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x000000cf,fr11 - - set_fr_iimmed 0xffff,0xffe8,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000067,fr11 - - set_fr_iimmed 0xffff,0xffe7,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000033,fr11 - - set_fr_iimmed 0xffff,0xffe6,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000019,fr11 - - set_fr_iimmed 0xffff,0xffe5,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0000000c,fr11 - - set_fr_iimmed 0xffff,0xffe4,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000006,fr11 - - set_fr_iimmed 0xffff,0xffe3,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000003,fr11 - - set_fr_iimmed 0xffff,0xffe2,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000001,fr11 - - set_fr_iimmed 0xffff,0xffe1,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000000,fr11 - - set_fr_iimmed 0xffff,0xffe0,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000000,fr11 - - set_fr_iimmed 0,32,fr10 ; same as -32 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000000,fr11 - - ; Examples from the customer - set_accg_immed 0xffffffff,accg0 - set_acc_immed 0xffe00000,acc0 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe0000000,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xc0000000,fr11 - - set_fr_iimmed 0,18,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0,accg0 - set_acc_immed 0x003fffff,acc0 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0x7f,accg0 - set_acc_immed 0xffe00000,acc0 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe0000000,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xc0000000,fr11 - - set_fr_iimmed 0,18,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0x08,accg0 - set_acc_immed 0x003fffff,acc0 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0xff,accg0 - set_acc_immed 0xefe00000,acc0 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe0000000,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xc0000000,fr11 - - set_fr_iimmed 0,18,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0x80,accg0 - set_acc_immed 0x003fffff,acc0 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0xffffffaf,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - set_fr_iimmed 0xffff,0xfffc,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfaf5a5a5,fr11 - - set_accg_immed 0x0000002f,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - set_fr_iimmed 0xffff,0xfff9,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x005eb4b4,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mcuti.cgs b/sim/testsuite/sim/frv/mcuti.cgs deleted file mode 100644 index e2e702f..0000000 --- a/sim/testsuite/sim/frv/mcuti.cgs +++ /dev/null @@ -1,381 +0,0 @@ -# frv testcase for mcuti $ACC40i,$s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mcuti -mcuti: - set_accg_immed 0xffffffe7,accg0 - set_acc_immed 0x89abcdef,acc0 - - mcuti acc0,0,fr11 - test_fr_iimmed 0xe789abcd,fr11 - - mcuti acc0,1,fr11 - test_fr_iimmed 0xcf13579b,fr11 - - mcuti acc0,2,fr11 - test_fr_iimmed 0x9e26af37,fr11 - - set_fr_iimmed 0,3,fr10 - mcuti acc0,3,fr11 - test_fr_iimmed 0x3c4d5e6f,fr11 - - mcuti acc0,4,fr11 - test_fr_iimmed 0x789abcde,fr11 - - mcuti acc0,5,fr11 - test_fr_iimmed 0xf13579bd,fr11 - - mcuti acc0,6,fr11 - test_fr_iimmed 0xe26af37b,fr11 - - mcuti acc0,7,fr11 - test_fr_iimmed 0xc4d5e6f7,fr11 - - mcuti acc0,8,fr11 - test_fr_iimmed 0x89abcdef,fr11 - - mcuti acc0,9,fr11 - test_fr_iimmed 0x13579bde,fr11 - - mcuti acc0,10,fr11 - test_fr_iimmed 0x26af37bc,fr11 - - mcuti acc0,11,fr11 - test_fr_iimmed 0x4d5e6f78,fr11 - - mcuti acc0,12,fr11 - test_fr_iimmed 0x9abcdef0,fr11 - - mcuti acc0,13,fr11 - test_fr_iimmed 0x3579bde0,fr11 - - mcuti acc0,14,fr11 - test_fr_iimmed 0x6af37bc0,fr11 - - mcuti acc0,15,fr11 - test_fr_iimmed 0xd5e6f780,fr11 - - mcuti acc0,16,fr11 - test_fr_iimmed 0xabcdef00,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0x579bde00,fr11 - - mcuti acc0,18,fr11 - test_fr_iimmed 0xaf37bc00,fr11 - - mcuti acc0,19,fr11 - test_fr_iimmed 0x5e6f7800,fr11 - - mcuti acc0,20,fr11 - test_fr_iimmed 0xbcdef000,fr11 - - mcuti acc0,21,fr11 - test_fr_iimmed 0x79bde000,fr11 - - mcuti acc0,22,fr11 - test_fr_iimmed 0xf37bc000,fr11 - - mcuti acc0,23,fr11 - test_fr_iimmed 0xe6f78000,fr11 - - mcuti acc0,24,fr11 - test_fr_iimmed 0xcdef0000,fr11 - - mcuti acc0,25,fr11 - test_fr_iimmed 0x9bde0000,fr11 - - mcuti acc0,26,fr11 - test_fr_iimmed 0x37bc0000,fr11 - - mcuti acc0,27,fr11 - test_fr_iimmed 0x6f780000,fr11 - - mcuti acc0,28,fr11 - test_fr_iimmed 0xdef00000,fr11 - - mcuti acc0,29,fr11 - test_fr_iimmed 0xbde00000,fr11 - - mcuti acc0,30,fr11 - test_fr_iimmed 0x7bc00000,fr11 - - mcuti acc0,31,fr11 - test_fr_iimmed 0xf7800000,fr11 - - mcuti acc0,-1,fr11 - test_fr_iimmed 0xf3c4d5e6,fr11 - - mcuti acc0,-2,fr11 - test_fr_iimmed 0xf9e26af3,fr11 - - mcuti acc0,-3,fr11 - test_fr_iimmed 0xfcf13579,fr11 - - mcuti acc0,-4,fr11 - test_fr_iimmed 0xfe789abc,fr11 - - mcuti acc0,-5,fr11 - test_fr_iimmed 0xff3c4d5e,fr11 - - mcuti acc0,-6,fr11 - test_fr_iimmed 0xff9e26af,fr11 - - mcuti acc0,-7,fr11 - test_fr_iimmed 0xffcf1357,fr11 - - mcuti acc0,-8,fr11 - test_fr_iimmed 0xffe789ab,fr11 - - mcuti acc0,-9,fr11 - test_fr_iimmed 0xfff3c4d5,fr11 - - mcuti acc0,-10,fr11 - test_fr_iimmed 0xfff9e26a,fr11 - - mcuti acc0,-11,fr11 - test_fr_iimmed 0xfffcf135,fr11 - - mcuti acc0,-12,fr11 - test_fr_iimmed 0xfffe789a,fr11 - - mcuti acc0,-13,fr11 - test_fr_iimmed 0xffff3c4d,fr11 - - mcuti acc0,-14,fr11 - test_fr_iimmed 0xffff9e26,fr11 - - mcuti acc0,-15,fr11 - test_fr_iimmed 0xffffcf13,fr11 - - mcuti acc0,-16,fr11 - test_fr_iimmed 0xffffe789,fr11 - - mcuti acc0,-17,fr11 - test_fr_iimmed 0xfffff3c4,fr11 - - mcuti acc0,-18,fr11 - test_fr_iimmed 0xfffff9e2,fr11 - - mcuti acc0,-19,fr11 - test_fr_iimmed 0xfffffcf1,fr11 - - mcuti acc0,-20,fr11 - test_fr_iimmed 0xfffffe78,fr11 - - mcuti acc0,-21,fr11 - test_fr_iimmed 0xffffff3c,fr11 - - mcuti acc0,-22,fr11 - test_fr_iimmed 0xffffff9e,fr11 - - mcuti acc0,-23,fr11 - test_fr_iimmed 0xffffffcf,fr11 - - mcuti acc0,-24,fr11 - test_fr_iimmed 0xffffffe7,fr11 - - mcuti acc0,-25,fr11 - test_fr_iimmed 0xfffffff3,fr11 - - mcuti acc0,-26,fr11 - test_fr_iimmed 0xfffffff9,fr11 - - mcuti acc0,-27,fr11 - test_fr_iimmed 0xfffffffc,fr11 - - mcuti acc0,-28,fr11 - test_fr_iimmed 0xfffffffe,fr11 - - mcuti acc0,-29,fr11 - test_fr_iimmed 0xffffffff,fr11 - - mcuti acc0,-30,fr11 - test_fr_iimmed 0xffffffff,fr11 - - mcuti acc0,-31,fr11 - test_fr_iimmed 0xffffffff,fr11 - - mcuti acc0,-32,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_accg_immed 0xffffff67,accg0 - set_acc_immed 0x89abcdef,acc0 - - mcuti acc0,-1,fr11 - test_fr_iimmed 0x33c4d5e6,fr11 - - mcuti acc0,-2,fr11 - test_fr_iimmed 0x19e26af3,fr11 - - mcuti acc0,-3,fr11 - test_fr_iimmed 0x0cf13579,fr11 - - mcuti acc0,-4,fr11 - test_fr_iimmed 0x06789abc,fr11 - - mcuti acc0,-5,fr11 - test_fr_iimmed 0x033c4d5e,fr11 - - mcuti acc0,-6,fr11 - test_fr_iimmed 0x019e26af,fr11 - - mcuti acc0,-7,fr11 - test_fr_iimmed 0x00cf1357,fr11 - - mcuti acc0,-8,fr11 - test_fr_iimmed 0x006789ab,fr11 - - mcuti acc0,-9,fr11 - test_fr_iimmed 0x0033c4d5,fr11 - - mcuti acc0,-10,fr11 - test_fr_iimmed 0x0019e26a,fr11 - - mcuti acc0,-11,fr11 - test_fr_iimmed 0x000cf135,fr11 - - mcuti acc0,-12,fr11 - test_fr_iimmed 0x0006789a,fr11 - - mcuti acc0,-13,fr11 - test_fr_iimmed 0x00033c4d,fr11 - - mcuti acc0,-14,fr11 - test_fr_iimmed 0x00019e26,fr11 - - mcuti acc0,-15,fr11 - test_fr_iimmed 0x0000cf13,fr11 - - mcuti acc0,-16,fr11 - test_fr_iimmed 0x00006789,fr11 - - mcuti acc0,-17,fr11 - test_fr_iimmed 0x000033c4,fr11 - - mcuti acc0,-18,fr11 - test_fr_iimmed 0x000019e2,fr11 - - mcuti acc0,-19,fr11 - test_fr_iimmed 0x00000cf1,fr11 - - mcuti acc0,-20,fr11 - test_fr_iimmed 0x00000678,fr11 - - mcuti acc0,-21,fr11 - test_fr_iimmed 0x0000033c,fr11 - - mcuti acc0,-22,fr11 - test_fr_iimmed 0x0000019e,fr11 - - mcuti acc0,-23,fr11 - test_fr_iimmed 0x000000cf,fr11 - - mcuti acc0,-24,fr11 - test_fr_iimmed 0x00000067,fr11 - - mcuti acc0,-25,fr11 - test_fr_iimmed 0x00000033,fr11 - - mcuti acc0,-26,fr11 - test_fr_iimmed 0x00000019,fr11 - - mcuti acc0,-27,fr11 - test_fr_iimmed 0x0000000c,fr11 - - mcuti acc0,-28,fr11 - test_fr_iimmed 0x00000006,fr11 - - mcuti acc0,-29,fr11 - test_fr_iimmed 0x00000003,fr11 - - mcuti acc0,-30,fr11 - test_fr_iimmed 0x00000001,fr11 - - mcuti acc0,-31,fr11 - test_fr_iimmed 0x00000000,fr11 - - mcuti acc0,-32,fr11 - test_fr_iimmed 0x00000000,fr11 - - ; Examples from the customer - set_accg_immed 0xffffffff,accg0 - set_acc_immed 0xffe00000,acc0 - - mcuti acc0,16,fr11 - test_fr_iimmed 0xe0000000,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0xc0000000,fr11 - - mcuti acc0,18,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0,accg0 - set_acc_immed 0x003fffff,acc0 - - mcuti acc0,16,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0x7f,accg0 - set_acc_immed 0xffe00000,acc0 - - mcuti acc0,16,fr11 - test_fr_iimmed 0xe0000000,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0xc0000000,fr11 - - mcuti acc0,18,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0x08,accg0 - set_acc_immed 0x003fffff,acc0 - - mcuti acc0,16,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0xff,accg0 - set_acc_immed 0xefe00000,acc0 - - mcuti acc0,16,fr11 - test_fr_iimmed 0xe0000000,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0xc0000000,fr11 - - mcuti acc0,18,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0x80,accg0 - set_acc_immed 0x003fffff,acc0 - - mcuti acc0,16,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0xffffffaf,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - mcuti acc0,-4,fr11 - test_fr_iimmed 0xfaf5a5a5,fr11 - - set_accg_immed 0x0000002f,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - mcuti acc0,-7,fr11 - test_fr_iimmed 0x005eb4b4,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mcutss.cgs b/sim/testsuite/sim/frv/mcutss.cgs deleted file mode 100644 index efe3278..0000000 --- a/sim/testsuite/sim/frv/mcutss.cgs +++ /dev/null @@ -1,505 +0,0 @@ -# frv testcase for mcutss $ACC40i,$FRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mcutss -mcutss: - set_accg_immed 0xffffffe7,accg0 - set_acc_immed 0x89abcdef,acc0 - - set_fr_iimmed 0,0,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xe789abcd,fr11 - - set_fr_iimmed 0,1,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xcf13579b,fr11 - - set_fr_iimmed 0,2,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x9e26af37,fr11 - - set_fr_iimmed 0,3,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,4,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,5,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,6,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,7,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,8,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,9,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,10,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,11,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,12,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,13,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,14,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,15,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,18,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,19,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,20,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,21,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,22,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,23,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,24,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,25,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,26,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,27,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,28,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,29,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,30,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,31,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,64,fr10 ; same as 0 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xe789abcd,fr11 - - set_fr_iimmed 0xffff,0xffff,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xf3c4d5e6,fr11 - - set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xf9e26af3,fr11 - - set_fr_iimmed 0xffff,0xfffd,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfcf13579,fr11 - - set_fr_iimmed 0xffff,0xfffc,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfe789abc,fr11 - - set_fr_iimmed 0xffff,0xfffb,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xff3c4d5e,fr11 - - set_fr_iimmed 0xffff,0xfffa,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xff9e26af,fr11 - - set_fr_iimmed 0xffff,0xfff9,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffcf1357,fr11 - - set_fr_iimmed 0xffff,0xfff8,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffe789ab,fr11 - - set_fr_iimmed 0xffff,0xfff7,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfff3c4d5,fr11 - - set_fr_iimmed 0xffff,0xfff6,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfff9e26a,fr11 - - set_fr_iimmed 0xffff,0xfff5,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffcf135,fr11 - - set_fr_iimmed 0xffff,0xfff4,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffe789a,fr11 - - set_fr_iimmed 0xffff,0xfff3,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffff3c4d,fr11 - - set_fr_iimmed 0xffff,0xfff2,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffff9e26,fr11 - - set_fr_iimmed 0xffff,0xfff1,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffcf13,fr11 - - set_fr_iimmed 0xffff,0xfff0,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffe789,fr11 - - set_fr_iimmed 0xffff,0xffef,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffff3c4,fr11 - - set_fr_iimmed 0xffff,0xffee,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffff9e2,fr11 - - set_fr_iimmed 0xffff,0xffed,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffffcf1,fr11 - - set_fr_iimmed 0xffff,0xffec,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffffe78,fr11 - - set_fr_iimmed 0xffff,0xffeb,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffff3c,fr11 - - set_fr_iimmed 0xffff,0xffea,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffff9e,fr11 - - set_fr_iimmed 0xffff,0xffe9,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffcf,fr11 - - set_fr_iimmed 0xffff,0xffe8,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffe7,fr11 - - set_fr_iimmed 0xffff,0xffe7,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffffff3,fr11 - - set_fr_iimmed 0xffff,0xffe6,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffffff9,fr11 - - set_fr_iimmed 0xffff,0xffe5,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffffffc,fr11 - - set_fr_iimmed 0xffff,0xffe4,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffffffe,fr11 - - set_fr_iimmed 0xffff,0xffe3,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0xffff,0xffe2,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0xffff,0xffe1,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0xffff,0xffe0,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0,32,fr10 ; same as -32 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_accg_immed 0xffffff67,accg0 - set_acc_immed 0x89abcdef,acc0 - - set_fr_iimmed 0xffff,0xffff,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x33c4d5e6,fr11 - - set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x19e26af3,fr11 - - set_fr_iimmed 0xffff,0xfffd,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0cf13579,fr11 - - set_fr_iimmed 0xffff,0xfffc,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x06789abc,fr11 - - set_fr_iimmed 0xffff,0xfffb,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x033c4d5e,fr11 - - set_fr_iimmed 0xffff,0xfffa,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x019e26af,fr11 - - set_fr_iimmed 0xffff,0xfff9,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00cf1357,fr11 - - set_fr_iimmed 0xffff,0xfff8,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x006789ab,fr11 - - set_fr_iimmed 0xffff,0xfff7,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0033c4d5,fr11 - - set_fr_iimmed 0xffff,0xfff6,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0019e26a,fr11 - - set_fr_iimmed 0xffff,0xfff5,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x000cf135,fr11 - - set_fr_iimmed 0xffff,0xfff4,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0006789a,fr11 - - set_fr_iimmed 0xffff,0xfff3,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00033c4d,fr11 - - set_fr_iimmed 0xffff,0xfff2,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00019e26,fr11 - - set_fr_iimmed 0xffff,0xfff1,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0000cf13,fr11 - - set_fr_iimmed 0xffff,0xfff0,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00006789,fr11 - - set_fr_iimmed 0xffff,0xffef,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x000033c4,fr11 - - set_fr_iimmed 0xffff,0xffee,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x000019e2,fr11 - - set_fr_iimmed 0xffff,0xffed,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000cf1,fr11 - - set_fr_iimmed 0xffff,0xffec,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000678,fr11 - - set_fr_iimmed 0xffff,0xffeb,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0000033c,fr11 - - set_fr_iimmed 0xffff,0xffea,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0000019e,fr11 - - set_fr_iimmed 0xffff,0xffe9,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x000000cf,fr11 - - set_fr_iimmed 0xffff,0xffe8,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000067,fr11 - - set_fr_iimmed 0xffff,0xffe7,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000033,fr11 - - set_fr_iimmed 0xffff,0xffe6,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000019,fr11 - - set_fr_iimmed 0xffff,0xffe5,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0000000c,fr11 - - set_fr_iimmed 0xffff,0xffe4,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000006,fr11 - - set_fr_iimmed 0xffff,0xffe3,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000003,fr11 - - set_fr_iimmed 0xffff,0xffe2,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000001,fr11 - - set_fr_iimmed 0xffff,0xffe1,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000000,fr11 - - set_fr_iimmed 0xffff,0xffe0,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000000,fr11 - - set_fr_iimmed 0,32,fr10 ; same as -32 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000000,fr11 - - ; Examples from the customer - set_accg_immed 0xffffffff,accg0 - set_acc_immed 0xffe00000,acc0 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xe0000000,fr11 - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xc0000000,fr11 - - set_fr_iimmed 0,18,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0,accg0 - set_acc_immed 0x003fffff,acc0 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0x7f,accg0 - set_acc_immed 0xffe00000,acc0 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_fr_iimmed 0,18,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_accg_immed 0x08,accg0 - set_acc_immed 0x003fffff,acc0 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_accg_immed 0xff,accg0 - set_acc_immed 0xefe00000,acc0 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_fr_iimmed 0,18,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_accg_immed 0x80,accg0 - set_acc_immed 0x003fffff,acc0 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_accg_immed 0xffffffaf,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - set_fr_iimmed 0xffff,0xfffc,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfaf5a5a5,fr11 - - set_accg_immed 0x0000002f,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - set_fr_iimmed 0xffff,0xfff9,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x005eb4b4,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mcutssi.cgs b/sim/testsuite/sim/frv/mcutssi.cgs deleted file mode 100644 index 739912f..0000000 --- a/sim/testsuite/sim/frv/mcutssi.cgs +++ /dev/null @@ -1,380 +0,0 @@ -# frv testcase for mcutssi $ACC40i,$s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mcutssi -mcutssi: - set_accg_immed 0xffffffe7,accg0 - set_acc_immed 0x89abcdef,acc0 - - mcutssi acc0,0,fr11 - test_fr_iimmed 0xe789abcd,fr11 - - mcutssi acc0,1,fr11 - test_fr_iimmed 0xcf13579b,fr11 - - mcutssi acc0,2,fr11 - test_fr_iimmed 0x9e26af37,fr11 - - mcutssi acc0,3,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,4,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,5,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,6,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,7,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,8,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,9,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,10,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,11,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,12,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,13,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,14,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,15,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,17,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,18,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,19,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,20,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,21,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,22,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,23,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,24,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,25,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,26,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,27,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,28,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,29,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,30,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,31,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,-1,fr11 - test_fr_iimmed 0xf3c4d5e6,fr11 - - mcutssi acc0,-2,fr11 - test_fr_iimmed 0xf9e26af3,fr11 - - mcutssi acc0,-3,fr11 - test_fr_iimmed 0xfcf13579,fr11 - - mcutssi acc0,-4,fr11 - test_fr_iimmed 0xfe789abc,fr11 - - mcutssi acc0,-5,fr11 - test_fr_iimmed 0xff3c4d5e,fr11 - - mcutssi acc0,-6,fr11 - test_fr_iimmed 0xff9e26af,fr11 - - mcutssi acc0,-7,fr11 - test_fr_iimmed 0xffcf1357,fr11 - - mcutssi acc0,-8,fr11 - test_fr_iimmed 0xffe789ab,fr11 - - mcutssi acc0,-9,fr11 - test_fr_iimmed 0xfff3c4d5,fr11 - - mcutssi acc0,-10,fr11 - test_fr_iimmed 0xfff9e26a,fr11 - - mcutssi acc0,-11,fr11 - test_fr_iimmed 0xfffcf135,fr11 - - mcutssi acc0,-12,fr11 - test_fr_iimmed 0xfffe789a,fr11 - - mcutssi acc0,-13,fr11 - test_fr_iimmed 0xffff3c4d,fr11 - - mcutssi acc0,-14,fr11 - test_fr_iimmed 0xffff9e26,fr11 - - mcutssi acc0,-15,fr11 - test_fr_iimmed 0xffffcf13,fr11 - - mcutssi acc0,-16,fr11 - test_fr_iimmed 0xffffe789,fr11 - - mcutssi acc0,-17,fr11 - test_fr_iimmed 0xfffff3c4,fr11 - - mcutssi acc0,-18,fr11 - test_fr_iimmed 0xfffff9e2,fr11 - - mcutssi acc0,-19,fr11 - test_fr_iimmed 0xfffffcf1,fr11 - - mcutssi acc0,-20,fr11 - test_fr_iimmed 0xfffffe78,fr11 - - mcutssi acc0,-21,fr11 - test_fr_iimmed 0xffffff3c,fr11 - - mcutssi acc0,-22,fr11 - test_fr_iimmed 0xffffff9e,fr11 - - mcutssi acc0,-23,fr11 - test_fr_iimmed 0xffffffcf,fr11 - - mcutssi acc0,-24,fr11 - test_fr_iimmed 0xffffffe7,fr11 - - mcutssi acc0,-25,fr11 - test_fr_iimmed 0xfffffff3,fr11 - - mcutssi acc0,-26,fr11 - test_fr_iimmed 0xfffffff9,fr11 - - mcutssi acc0,-27,fr11 - test_fr_iimmed 0xfffffffc,fr11 - - mcutssi acc0,-28,fr11 - test_fr_iimmed 0xfffffffe,fr11 - - mcutssi acc0,-29,fr11 - test_fr_iimmed 0xffffffff,fr11 - - mcutssi acc0,-30,fr11 - test_fr_iimmed 0xffffffff,fr11 - - mcutssi acc0,-31,fr11 - test_fr_iimmed 0xffffffff,fr11 - - mcutssi acc0,-32,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_accg_immed 0xffffff67,accg0 - set_acc_immed 0x89abcdef,acc0 - - mcutssi acc0,-1,fr11 - test_fr_iimmed 0x33c4d5e6,fr11 - - mcutssi acc0,-2,fr11 - test_fr_iimmed 0x19e26af3,fr11 - - mcutssi acc0,-3,fr11 - test_fr_iimmed 0x0cf13579,fr11 - - mcutssi acc0,-4,fr11 - test_fr_iimmed 0x06789abc,fr11 - - mcutssi acc0,-5,fr11 - test_fr_iimmed 0x033c4d5e,fr11 - - mcutssi acc0,-6,fr11 - test_fr_iimmed 0x019e26af,fr11 - - mcutssi acc0,-7,fr11 - test_fr_iimmed 0x00cf1357,fr11 - - mcutssi acc0,-8,fr11 - test_fr_iimmed 0x006789ab,fr11 - - mcutssi acc0,-9,fr11 - test_fr_iimmed 0x0033c4d5,fr11 - - mcutssi acc0,-10,fr11 - test_fr_iimmed 0x0019e26a,fr11 - - mcutssi acc0,-11,fr11 - test_fr_iimmed 0x000cf135,fr11 - - mcutssi acc0,-12,fr11 - test_fr_iimmed 0x0006789a,fr11 - - mcutssi acc0,-13,fr11 - test_fr_iimmed 0x00033c4d,fr11 - - mcutssi acc0,-14,fr11 - test_fr_iimmed 0x00019e26,fr11 - - mcutssi acc0,-15,fr11 - test_fr_iimmed 0x0000cf13,fr11 - - mcutssi acc0,-16,fr11 - test_fr_iimmed 0x00006789,fr11 - - mcutssi acc0,-17,fr11 - test_fr_iimmed 0x000033c4,fr11 - - mcutssi acc0,-18,fr11 - test_fr_iimmed 0x000019e2,fr11 - - mcutssi acc0,-19,fr11 - test_fr_iimmed 0x00000cf1,fr11 - - mcutssi acc0,-20,fr11 - test_fr_iimmed 0x00000678,fr11 - - mcutssi acc0,-21,fr11 - test_fr_iimmed 0x0000033c,fr11 - - mcutssi acc0,-22,fr11 - test_fr_iimmed 0x0000019e,fr11 - - mcutssi acc0,-23,fr11 - test_fr_iimmed 0x000000cf,fr11 - - mcutssi acc0,-24,fr11 - test_fr_iimmed 0x00000067,fr11 - - mcutssi acc0,-25,fr11 - test_fr_iimmed 0x00000033,fr11 - - mcutssi acc0,-26,fr11 - test_fr_iimmed 0x00000019,fr11 - - mcutssi acc0,-27,fr11 - test_fr_iimmed 0x0000000c,fr11 - - mcutssi acc0,-28,fr11 - test_fr_iimmed 0x00000006,fr11 - - mcutssi acc0,-29,fr11 - test_fr_iimmed 0x00000003,fr11 - - mcutssi acc0,-30,fr11 - test_fr_iimmed 0x00000001,fr11 - - mcutssi acc0,-31,fr11 - test_fr_iimmed 0x00000000,fr11 - - mcutssi acc0,-32,fr11 - test_fr_iimmed 0x00000000,fr11 - - ; Examples from the customer - set_accg_immed 0xffffffff,accg0 - set_acc_immed 0xffe00000,acc0 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0xe0000000,fr11 - - mcutssi acc0,17,fr11 - test_fr_iimmed 0xc0000000,fr11 - - mcutssi acc0,18,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0,accg0 - set_acc_immed 0x003fffff,acc0 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - mcutssi acc0,17,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0x7f,accg0 - set_acc_immed 0xffe00000,acc0 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - mcutssi acc0,17,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - mcutssi acc0,18,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_accg_immed 0x08,accg0 - set_acc_immed 0x003fffff,acc0 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - mcutssi acc0,17,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_accg_immed 0xff,accg0 - set_acc_immed 0xefe00000,acc0 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - mcutssi acc0,17,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - mcutssi acc0,18,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_accg_immed 0x80,accg0 - set_acc_immed 0x003fffff,acc0 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - mcutssi acc0,17,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_accg_immed 0xffffffaf,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - mcutssi acc0,-4,fr11 - test_fr_iimmed 0xfaf5a5a5,fr11 - - set_accg_immed 0x0000002f,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - mcutssi acc0,-7,fr11 - test_fr_iimmed 0x005eb4b4,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mdaddaccs.cgs b/sim/testsuite/sim/frv/mdaddaccs.cgs deleted file mode 100644 index 553c4a7..0000000 --- a/sim/testsuite/sim/frv/mdaddaccs.cgs +++ /dev/null @@ -1,102 +0,0 @@ -# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mdaddaccs -mdaddaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0xdead0000,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x0000beef,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdead,0xbeef,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x11111111,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0xbeef,0xdead,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x2345,0x6789,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - set_accg_immed 0x80,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xfffffffe,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0002,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mdasaccs.cgs b/sim/testsuite/sim/frv/mdasaccs.cgs deleted file mode 100644 index 0535b62..0000000 --- a/sim/testsuite/sim/frv/mdasaccs.cgs +++ /dev/null @@ -1,122 +0,0 @@ -# frv testcase for mdasaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mdasaccs -mdasaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0xdead0000,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x0000beef,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0xdead,0xbeef,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x11111111,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0xbeef,0xdead,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0x4111,0xdead,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x2345,0x6789,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x1234,0x5677,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0x1234,0x5679,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - set_accg_immed 0x80,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xfffffffe,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0xa,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xfffc,0x7ffd,acc1 - test_accg_immed 0x80,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0003,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mdcutssi.cgs b/sim/testsuite/sim/frv/mdcutssi.cgs deleted file mode 100644 index 8e5216c..0000000 --- a/sim/testsuite/sim/frv/mdcutssi.cgs +++ /dev/null @@ -1,513 +0,0 @@ -# frv testcase for mdcutssi $ACC40i,$s6,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global mdcutssi -mdcutssi: - set_accg_immed 0xffffffe7,accg0 - set_acc_immed 0x89abcdef,acc0 - set_accg_immed 0xffffffe7,accg1 - set_acc_immed 0x89abcdef,acc1 - - mdcutssi acc0,0,fr10 - test_fr_iimmed 0xe789abcd,fr10 - test_fr_iimmed 0xe789abcd,fr11 - - mdcutssi acc0,1,fr10 - test_fr_iimmed 0xcf13579b,fr10 - test_fr_iimmed 0xcf13579b,fr11 - - mdcutssi acc0,2,fr10 - test_fr_iimmed 0x9e26af37,fr10 - test_fr_iimmed 0x9e26af37,fr11 - - mdcutssi acc0,3,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,4,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,5,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,6,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,7,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,8,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,9,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,10,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,11,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,12,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,13,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,14,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,15,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,18,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,19,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,20,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,21,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,22,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,23,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,24,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,25,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,26,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,27,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,28,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,29,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,30,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,31,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,-1,fr10 - test_fr_iimmed 0xf3c4d5e6,fr10 - test_fr_iimmed 0xf3c4d5e6,fr11 - - mdcutssi acc0,-2,fr10 - test_fr_iimmed 0xf9e26af3,fr10 - test_fr_iimmed 0xf9e26af3,fr11 - - mdcutssi acc0,-3,fr10 - test_fr_iimmed 0xfcf13579,fr10 - test_fr_iimmed 0xfcf13579,fr11 - - mdcutssi acc0,-4,fr10 - test_fr_iimmed 0xfe789abc,fr10 - test_fr_iimmed 0xfe789abc,fr11 - - mdcutssi acc0,-5,fr10 - test_fr_iimmed 0xff3c4d5e,fr10 - test_fr_iimmed 0xff3c4d5e,fr11 - - mdcutssi acc0,-6,fr10 - test_fr_iimmed 0xff9e26af,fr10 - test_fr_iimmed 0xff9e26af,fr11 - - mdcutssi acc0,-7,fr10 - test_fr_iimmed 0xffcf1357,fr10 - test_fr_iimmed 0xffcf1357,fr11 - - mdcutssi acc0,-8,fr10 - test_fr_iimmed 0xffe789ab,fr10 - test_fr_iimmed 0xffe789ab,fr11 - - mdcutssi acc0,-9,fr10 - test_fr_iimmed 0xfff3c4d5,fr10 - test_fr_iimmed 0xfff3c4d5,fr11 - - mdcutssi acc0,-10,fr10 - test_fr_iimmed 0xfff9e26a,fr10 - test_fr_iimmed 0xfff9e26a,fr11 - - mdcutssi acc0,-11,fr10 - test_fr_iimmed 0xfffcf135,fr10 - test_fr_iimmed 0xfffcf135,fr11 - - mdcutssi acc0,-12,fr10 - test_fr_iimmed 0xfffe789a,fr10 - test_fr_iimmed 0xfffe789a,fr11 - - mdcutssi acc0,-13,fr10 - test_fr_iimmed 0xffff3c4d,fr10 - test_fr_iimmed 0xffff3c4d,fr11 - - mdcutssi acc0,-14,fr10 - test_fr_iimmed 0xffff9e26,fr10 - test_fr_iimmed 0xffff9e26,fr11 - - mdcutssi acc0,-15,fr10 - test_fr_iimmed 0xffffcf13,fr10 - test_fr_iimmed 0xffffcf13,fr11 - - mdcutssi acc0,-16,fr10 - test_fr_iimmed 0xffffe789,fr10 - test_fr_iimmed 0xffffe789,fr11 - - mdcutssi acc0,-17,fr10 - test_fr_iimmed 0xfffff3c4,fr10 - test_fr_iimmed 0xfffff3c4,fr11 - - mdcutssi acc0,-18,fr10 - test_fr_iimmed 0xfffff9e2,fr10 - test_fr_iimmed 0xfffff9e2,fr11 - - mdcutssi acc0,-19,fr10 - test_fr_iimmed 0xfffffcf1,fr10 - test_fr_iimmed 0xfffffcf1,fr11 - - mdcutssi acc0,-20,fr10 - test_fr_iimmed 0xfffffe78,fr10 - test_fr_iimmed 0xfffffe78,fr11 - - mdcutssi acc0,-21,fr10 - test_fr_iimmed 0xffffff3c,fr10 - test_fr_iimmed 0xffffff3c,fr11 - - mdcutssi acc0,-22,fr10 - test_fr_iimmed 0xffffff9e,fr10 - test_fr_iimmed 0xffffff9e,fr11 - - mdcutssi acc0,-23,fr10 - test_fr_iimmed 0xffffffcf,fr10 - test_fr_iimmed 0xffffffcf,fr11 - - mdcutssi acc0,-24,fr10 - test_fr_iimmed 0xffffffe7,fr10 - test_fr_iimmed 0xffffffe7,fr11 - - mdcutssi acc0,-25,fr10 - test_fr_iimmed 0xfffffff3,fr10 - test_fr_iimmed 0xfffffff3,fr11 - - mdcutssi acc0,-26,fr10 - test_fr_iimmed 0xfffffff9,fr10 - test_fr_iimmed 0xfffffff9,fr11 - - mdcutssi acc0,-27,fr10 - test_fr_iimmed 0xfffffffc,fr10 - test_fr_iimmed 0xfffffffc,fr11 - - mdcutssi acc0,-28,fr10 - test_fr_iimmed 0xfffffffe,fr10 - test_fr_iimmed 0xfffffffe,fr11 - - mdcutssi acc0,-29,fr10 - test_fr_iimmed 0xffffffff,fr10 - test_fr_iimmed 0xffffffff,fr11 - - mdcutssi acc0,-30,fr10 - test_fr_iimmed 0xffffffff,fr10 - test_fr_iimmed 0xffffffff,fr11 - - mdcutssi acc0,-31,fr10 - test_fr_iimmed 0xffffffff,fr10 - test_fr_iimmed 0xffffffff,fr11 - - mdcutssi acc0,-32,fr10 - test_fr_iimmed 0xffffffff,fr10 - test_fr_iimmed 0xffffffff,fr11 - - set_accg_immed 0xffffff67,accg0 - set_acc_immed 0x89abcdef,acc0 - set_accg_immed 0xffffff67,accg1 - set_acc_immed 0x89abcdef,acc1 - - mdcutssi acc0,-1,fr10 - test_fr_iimmed 0x33c4d5e6,fr10 - test_fr_iimmed 0x33c4d5e6,fr11 - - mdcutssi acc0,-2,fr10 - test_fr_iimmed 0x19e26af3,fr10 - test_fr_iimmed 0x19e26af3,fr11 - - mdcutssi acc0,-3,fr10 - test_fr_iimmed 0x0cf13579,fr10 - test_fr_iimmed 0x0cf13579,fr11 - - mdcutssi acc0,-4,fr10 - test_fr_iimmed 0x06789abc,fr10 - test_fr_iimmed 0x06789abc,fr11 - - mdcutssi acc0,-5,fr10 - test_fr_iimmed 0x033c4d5e,fr10 - test_fr_iimmed 0x033c4d5e,fr11 - - mdcutssi acc0,-6,fr10 - test_fr_iimmed 0x019e26af,fr10 - test_fr_iimmed 0x019e26af,fr11 - - mdcutssi acc0,-7,fr10 - test_fr_iimmed 0x00cf1357,fr10 - test_fr_iimmed 0x00cf1357,fr11 - - mdcutssi acc0,-8,fr10 - test_fr_iimmed 0x006789ab,fr10 - test_fr_iimmed 0x006789ab,fr11 - - mdcutssi acc0,-9,fr10 - test_fr_iimmed 0x0033c4d5,fr10 - test_fr_iimmed 0x0033c4d5,fr11 - - mdcutssi acc0,-10,fr10 - test_fr_iimmed 0x0019e26a,fr10 - test_fr_iimmed 0x0019e26a,fr11 - - mdcutssi acc0,-11,fr10 - test_fr_iimmed 0x000cf135,fr10 - test_fr_iimmed 0x000cf135,fr11 - - mdcutssi acc0,-12,fr10 - test_fr_iimmed 0x0006789a,fr10 - test_fr_iimmed 0x0006789a,fr11 - - mdcutssi acc0,-13,fr10 - test_fr_iimmed 0x00033c4d,fr10 - test_fr_iimmed 0x00033c4d,fr11 - - mdcutssi acc0,-14,fr10 - test_fr_iimmed 0x00019e26,fr10 - test_fr_iimmed 0x00019e26,fr11 - - mdcutssi acc0,-15,fr10 - test_fr_iimmed 0x0000cf13,fr10 - test_fr_iimmed 0x0000cf13,fr11 - - mdcutssi acc0,-16,fr10 - test_fr_iimmed 0x00006789,fr10 - test_fr_iimmed 0x00006789,fr11 - - mdcutssi acc0,-17,fr10 - test_fr_iimmed 0x000033c4,fr10 - test_fr_iimmed 0x000033c4,fr11 - - mdcutssi acc0,-18,fr10 - test_fr_iimmed 0x000019e2,fr10 - test_fr_iimmed 0x000019e2,fr11 - - mdcutssi acc0,-19,fr10 - test_fr_iimmed 0x00000cf1,fr10 - test_fr_iimmed 0x00000cf1,fr11 - - mdcutssi acc0,-20,fr10 - test_fr_iimmed 0x00000678,fr10 - test_fr_iimmed 0x00000678,fr11 - - mdcutssi acc0,-21,fr10 - test_fr_iimmed 0x0000033c,fr10 - test_fr_iimmed 0x0000033c,fr11 - - mdcutssi acc0,-22,fr10 - test_fr_iimmed 0x0000019e,fr10 - test_fr_iimmed 0x0000019e,fr11 - - mdcutssi acc0,-23,fr10 - test_fr_iimmed 0x000000cf,fr10 - test_fr_iimmed 0x000000cf,fr11 - - mdcutssi acc0,-24,fr10 - test_fr_iimmed 0x00000067,fr10 - test_fr_iimmed 0x00000067,fr11 - - mdcutssi acc0,-25,fr10 - test_fr_iimmed 0x00000033,fr10 - test_fr_iimmed 0x00000033,fr11 - - mdcutssi acc0,-26,fr10 - test_fr_iimmed 0x00000019,fr10 - test_fr_iimmed 0x00000019,fr11 - - mdcutssi acc0,-27,fr10 - test_fr_iimmed 0x0000000c,fr10 - test_fr_iimmed 0x0000000c,fr11 - - mdcutssi acc0,-28,fr10 - test_fr_iimmed 0x00000006,fr10 - test_fr_iimmed 0x00000006,fr11 - - mdcutssi acc0,-29,fr10 - test_fr_iimmed 0x00000003,fr10 - test_fr_iimmed 0x00000003,fr11 - - mdcutssi acc0,-30,fr10 - test_fr_iimmed 0x00000001,fr10 - test_fr_iimmed 0x00000001,fr11 - - mdcutssi acc0,-31,fr10 - test_fr_iimmed 0x00000000,fr10 - test_fr_iimmed 0x00000000,fr11 - - mdcutssi acc0,-32,fr10 - test_fr_iimmed 0x00000000,fr10 - test_fr_iimmed 0x00000000,fr11 - - ; Examples from the customer - set_accg_immed 0xffffffff,accg0 - set_acc_immed 0xffe00000,acc0 - set_accg_immed 0xffffffff,accg1 - set_acc_immed 0xffe00000,acc1 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0xe0000000,fr10 - test_fr_iimmed 0xe0000000,fr11 - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0xc0000000,fr10 - test_fr_iimmed 0xc0000000,fr11 - - mdcutssi acc0,18,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0,accg0 - set_acc_immed 0x003fffff,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x003fffff,acc1 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0x3fffff00,fr10 - test_fr_iimmed 0x3fffff00,fr11 - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0x7ffffe00,fr10 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0x7f,accg0 - set_acc_immed 0xffe00000,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffe00000,acc1 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0x7fffffff,fr10 ; saturated - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0x7fffffff,fr10 ; saturated - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - mdcutssi acc0,18,fr10 - test_fr_iimmed 0x7fffffff,fr10 ; saturated - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_accg_immed 0x08,accg0 - set_acc_immed 0x003fffff,acc0 - set_accg_immed 0x08,accg1 - set_acc_immed 0x003fffff,acc1 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0x7fffffff,fr10 ; saturated - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0x7fffffff,fr10 ; saturated - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_accg_immed 0xff,accg0 - set_acc_immed 0xefe00000,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xefe00000,acc1 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0x80000000,fr10 ; saturated - test_fr_iimmed 0x80000000,fr11 ; saturated - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0x80000000,fr10 ; saturated - test_fr_iimmed 0x80000000,fr11 ; saturated - - mdcutssi acc0,18,fr10 - test_fr_iimmed 0x80000000,fr10 ; saturated - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_accg_immed 0x80,accg0 - set_acc_immed 0x003fffff,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0x003fffff,acc1 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0x80000000,fr10 ; saturated - test_fr_iimmed 0x80000000,fr11 ; saturated - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0x80000000,fr10 ; saturated - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_accg_immed 0xffffffaf,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - set_accg_immed 0xffffffaf,accg1 - set_acc_immed 0x5a5a5a5a,acc1 - - mdcutssi acc0,-4,fr10 - test_fr_iimmed 0xfaf5a5a5,fr10 - test_fr_iimmed 0xfaf5a5a5,fr11 - - set_accg_immed 0x0000002f,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - set_accg_immed 0x0000002f,accg1 - set_acc_immed 0x5a5a5a5a,acc1 - - mdcutssi acc0,-7,fr10 - test_fr_iimmed 0x005eb4b4,fr10 - test_fr_iimmed 0x005eb4b4,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mdpackh.cgs b/sim/testsuite/sim/frv/mdpackh.cgs deleted file mode 100644 index cbd0bc8..0000000 --- a/sim/testsuite/sim/frv/mdpackh.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for mdpackh $FRi,$FRj,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global mdpackh -mdpackh: - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0xaaaa,0xbbbb,fr11 - set_fr_iimmed 0x1234,0x5678,fr12 - set_fr_iimmed 0xcccc,0xdddd,fr13 - mdpackh fr10,fr12,fr14 - test_fr_limmed 0xbeef,0x5678,fr14 - test_fr_limmed 0xbbbb,0xdddd,fr15 - - pass diff --git a/sim/testsuite/sim/frv/mdrotli.cgs b/sim/testsuite/sim/frv/mdrotli.cgs deleted file mode 100644 index 1d2e183..0000000 --- a/sim/testsuite/sim/frv/mdrotli.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for mdrotli $FRi,$s6,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global mdrotli -mdrotli: - set_fr_iimmed 0,2,fr8 - set_fr_iimmed 0,2,fr9 - mdrotli fr8,-32,fr8 ; Shift by 0 - test_fr_iimmed 2,fr8 - test_fr_iimmed 2,fr9 - - set_fr_iimmed 0,2,fr8 - set_fr_iimmed 0,2,fr9 - mdrotli fr8,1,fr8 ; Shift by 1 - test_fr_iimmed 4,fr8 - test_fr_iimmed 4,fr9 - - set_fr_iimmed 0,1,fr8 - set_fr_iimmed 0,2,fr9 - mdrotli fr8,31,fr8 ; Shift by 31 - test_fr_iimmed 0x80000000,fr8 - test_fr_iimmed 1,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - mdrotli fr8,16,fr8 - test_fr_iimmed 0xbeefdead,fr8 - test_fr_iimmed 0xdeadbeef,fr9 - - pass diff --git a/sim/testsuite/sim/frv/mdsubaccs.cgs b/sim/testsuite/sim/frv/mdsubaccs.cgs deleted file mode 100644 index 73d2e2d..0000000 --- a/sim/testsuite/sim/frv/mdsubaccs.cgs +++ /dev/null @@ -1,102 +0,0 @@ -# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mdsubaccs -mdsubaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0xdead0000,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x0000beef,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x11111111,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg2 - test_acc_limmed 0x4111,0xdead,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg2 - test_acc_limmed 0x1234,0x5679,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffffffe,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - set_accg_immed 0x80,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x00000002,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0x00000000,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mdunpackh.cgs b/sim/testsuite/sim/frv/mdunpackh.cgs deleted file mode 100644 index 02870c8..0000000 --- a/sim/testsuite/sim/frv/mdunpackh.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mdunpackh $FRi,$FRj -# mach: frv - - .include "testutils.inc" - - start - - .global mdunpackh -mdunpackh: - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - mdunpackh fr10,fr12 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - test_fr_limmed 0x1234,0x1234,fr14 - test_fr_limmed 0x5678,0x5678,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - mdunpackh fr10,fr12 - test_fr_limmed 0x1234,0x1234,fr12 - test_fr_limmed 0x5678,0x5678,fr13 - test_fr_limmed 0xdead,0xdead,fr14 - test_fr_limmed 0xbeef,0xbeef,fr15 - - pass diff --git a/sim/testsuite/sim/frv/membar.cgs b/sim/testsuite/sim/frv/membar.cgs deleted file mode 100644 index aae1d1a..0000000 --- a/sim/testsuite/sim/frv/membar.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# frv testcase for membar -# mach: all - - .include "testutils.inc" - - start - - .global membar -membar: - membar - - pass diff --git a/sim/testsuite/sim/frv/mexpdhd.cgs b/sim/testsuite/sim/frv/mexpdhd.cgs deleted file mode 100644 index d5f95ce..0000000 --- a/sim/testsuite/sim/frv/mexpdhd.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for mexpdhd $FRi,$s6,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global mexpdhd -mexpdhd: - set_fr_iimmed 0xdead,0xbeef,fr10 - mexpdhd fr10,0,fr12 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xdead,0xdead,fr13 - - mexpdhd fr10,1,fr12 - test_fr_limmed 0xbeef,0xbeef,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - mexpdhd fr10,62,fr12 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xdead,0xdead,fr13 - - mexpdhd fr10,63,fr12 - test_fr_limmed 0xbeef,0xbeef,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - pass diff --git a/sim/testsuite/sim/frv/mexpdhw.cgs b/sim/testsuite/sim/frv/mexpdhw.cgs deleted file mode 100644 index a13b0f2..0000000 --- a/sim/testsuite/sim/frv/mexpdhw.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for mexpdhw $FRi,$s6,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global mexpdhw -mexpdhw: - set_fr_iimmed 0xdead,0xbeef,fr10 - mexpdhw fr10,0,fr12 - test_fr_limmed 0xdead,0xdead,fr12 - - mexpdhw fr10,1,fr12 - test_fr_limmed 0xbeef,0xbeef,fr12 - - mexpdhw fr10,62,fr12 - test_fr_limmed 0xdead,0xdead,fr12 - - mexpdhw fr10,63,fr12 - test_fr_limmed 0xbeef,0xbeef,fr12 - - pass diff --git a/sim/testsuite/sim/frv/mhdseth.cgs b/sim/testsuite/sim/frv/mhdseth.cgs deleted file mode 100644 index 7c09b2d..0000000 --- a/sim/testsuite/sim/frv/mhdseth.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mhdseth $s5,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_fr_iimmed 0xdead,0xbeef,fr1 - mhdseth 0,fr1 - test_fr_limmed 0x06ad,0x06ef,fr1 - - mhdseth 1,fr1 - test_fr_limmed 0x0ead,0x0eef,fr1 - - mhdseth 0xf,fr1 - test_fr_limmed 0x7ead,0x7eef,fr1 - - mhdseth -16,fr1 - test_fr_limmed 0x86ad,0x86ef,fr1 - - mhdseth -1,fr1 - test_fr_limmed 0xfead,0xfeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/mhdsets.cgs b/sim/testsuite/sim/frv/mhdsets.cgs deleted file mode 100644 index 1f26814..0000000 --- a/sim/testsuite/sim/frv/mhdsets.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mhdsets $u12,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_fr_iimmed 0xdead,0xbeef,fr1 - mhdsets 0,fr1 - test_fr_limmed 0x0000,0x0000,fr1 - - mhdsets 1,fr1 - test_fr_limmed 0x0001,0x0001,fr1 - - mhdsets 0x07ff,fr1 - test_fr_limmed 0x07ff,0x07ff,fr1 - - mhdsets -2048,fr1 - test_fr_limmed 0xf800,0xf800,fr1 - - mhdsets -1,fr1 - test_fr_limmed 0xffff,0xffff,fr1 - - pass diff --git a/sim/testsuite/sim/frv/mhsethih.cgs b/sim/testsuite/sim/frv/mhsethih.cgs deleted file mode 100644 index f05eb77..0000000 --- a/sim/testsuite/sim/frv/mhsethih.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mhsethih $s5,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_fr_iimmed 0xdead,0xbeef,fr1 - mhsethih 0,fr1 - test_fr_limmed 0x06ad,0xbeef,fr1 - - mhsethih 1,fr1 - test_fr_limmed 0x0ead,0xbeef,fr1 - - mhsethih 0xf,fr1 - test_fr_limmed 0x7ead,0xbeef,fr1 - - mhsethih -16,fr1 - test_fr_limmed 0x86ad,0xbeef,fr1 - - mhsethih -1,fr1 - test_fr_limmed 0xfead,0xbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/mhsethis.cgs b/sim/testsuite/sim/frv/mhsethis.cgs deleted file mode 100644 index cf89336..0000000 --- a/sim/testsuite/sim/frv/mhsethis.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mhsethis $u12,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_fr_iimmed 0xdead,0xbeef,fr1 - mhsethis 0,fr1 - test_fr_limmed 0x0000,0xbeef,fr1 - - mhsethis 1,fr1 - test_fr_limmed 0x0001,0xbeef,fr1 - - mhsethis 0x07ff,fr1 - test_fr_limmed 0x07ff,0xbeef,fr1 - - mhsethis -2048,fr1 - test_fr_limmed 0xf800,0xbeef,fr1 - - mhsethis -1,fr1 - test_fr_limmed 0xffff,0xbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/mhsetloh.cgs b/sim/testsuite/sim/frv/mhsetloh.cgs deleted file mode 100644 index 930628d..0000000 --- a/sim/testsuite/sim/frv/mhsetloh.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mhsetloh $s5,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_fr_iimmed 0xdead,0xbeef,fr1 - mhsetloh 0,fr1 - test_fr_limmed 0xdead,0x06ef,fr1 - - mhsetloh 1,fr1 - test_fr_limmed 0xdead,0x0eef,fr1 - - mhsetloh 0xf,fr1 - test_fr_limmed 0xdead,0x7eef,fr1 - - mhsetloh -16,fr1 - test_fr_limmed 0xdead,0x86ef,fr1 - - mhsetloh -1,fr1 - test_fr_limmed 0xdead,0xfeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/mhsetlos.cgs b/sim/testsuite/sim/frv/mhsetlos.cgs deleted file mode 100644 index fb404a2..0000000 --- a/sim/testsuite/sim/frv/mhsetlos.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mhsetlos $u12,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_fr_iimmed 0xdead,0xbeef,fr1 - mhsetlos 0,fr1 - test_fr_limmed 0xdead,0x0000,fr1 - - mhsetlos 1,fr1 - test_fr_limmed 0xdead,0x0001,fr1 - - mhsetlos 0x07ff,fr1 - test_fr_limmed 0xdead,0x07ff,fr1 - - mhsetlos -2048,fr1 - test_fr_limmed 0xdead,0xf800,fr1 - - mhsetlos -1,fr1 - test_fr_limmed 0xdead,0xffff,fr1 - - pass diff --git a/sim/testsuite/sim/frv/mhtob.cgs b/sim/testsuite/sim/frv/mhtob.cgs deleted file mode 100644 index efd83d7..0000000 --- a/sim/testsuite/sim/frv/mhtob.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for mhtob $FRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mhtob -mhtob: - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - mhtob fr10,fr12 - test_fr_limmed 0xadef,0x3478,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 ; saturation - set_fr_iimmed 0x1234,0x5678,fr11 - mhtob fr10,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 ; saturation - set_fr_iimmed 0x10ad,0x80ef,fr11 - mhtob fr10,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - - pass diff --git a/sim/testsuite/sim/frv/misc.exp b/sim/testsuite/sim/frv/misc.exp deleted file mode 100644 index 4245a81..0000000 --- a/sim/testsuite/sim/frv/misc.exp +++ /dev/null @@ -1,19 +0,0 @@ -# Miscellaneous FRV simulator testcases. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "frv fr500 fr550 fr400 fr405 fr450" - set cpu_option -mcpu - - # The .ms suffix is for "miscellaneous .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/mmachs.cgs b/sim/testsuite/sim/frv/mmachs.cgs deleted file mode 100644 index 0292161..0000000 --- a/sim/testsuite/sim/frv/mmachs.cgs +++ /dev/null @@ -1,259 +0,0 @@ -# frv testcase for mmachs $GRi,$GRj,$ACCk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mmachs -mmachs: - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0007,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0001,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xbffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xbffd,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffd,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc003,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc005,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc005,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3ffec006,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x7ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x7ffec006,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - mmachs fr7,fr8,acc0 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/mmachu.cgs b/sim/testsuite/sim/frv/mmachu.cgs deleted file mode 100644 index aad07c7..0000000 --- a/sim/testsuite/sim/frv/mmachu.cgs +++ /dev/null @@ -1,146 +0,0 @@ -# frv testcase for mmachu $GRi,$GRj,$GRk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mmachu -mmachu: - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x00020006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00020006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x40010007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40010007,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x8001,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x8001,0x0007,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x7fff,0x0008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x7fff,0x0008,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mmrdhs.cgs b/sim/testsuite/sim/frv/mmrdhs.cgs deleted file mode 100644 index 6295bc1..0000000 --- a/sim/testsuite/sim/frv/mmrdhs.cgs +++ /dev/null @@ -1,263 +0,0 @@ -# frv testcase for mmrdhs $GRi,$GRj,$ACCk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mmrdhs -mmrdhs: - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_immed -8,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x7ffa,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xfffe,0xfffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xfffe,0xfffa,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xbfff,0xfff9,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xbfff,0xfff9,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xbfff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xbfff,0xffff,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x0001,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x0001,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x0001,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x0001,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x4003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x4003,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0xc003,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x4003,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x4003,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x3ffd,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x3ffb,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x3ffb,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_immed 0xc0013ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xc0013ffa,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_immed 0x80013ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0x80013ffa,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 0xffff,1,fr7 - set_fr_iimmed 1,0xffff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x8000,0x0000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0,1,fr7 - set_fr_iimmed 1,1,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/mmrdhu.cgs b/sim/testsuite/sim/frv/mmrdhu.cgs deleted file mode 100644 index b1c0243..0000000 --- a/sim/testsuite/sim/frv/mmrdhu.cgs +++ /dev/null @@ -1,151 +0,0 @@ -# frv testcase for mmrdhu $GRi,$GRj,$GRk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mmrdhu -mmrdhu: - set_accg_immed 0x80,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_immed 0xfffffffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xfffffffa,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_immed 0xfffffff8,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xfffffff8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_immed 0xfffffff8,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xfffffff8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0x7ffa,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xfffe,0xfffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xfffe,0xfffa,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xfffd,0xfffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xfffd,0xfffa,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xbffe,0xfff9,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xbffe,0xfff9,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0x7ffe,0xfff9,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0x7ffe,0xfff9,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7e,accg0 - test_acc_limmed 0x8000,0xfff8,acc0 - test_accg_immed 0x7e,accg1 - test_acc_limmed 0x8000,0xfff8,acc1 - - set_accg_immed 0,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0xffff,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mmulhs.cgs b/sim/testsuite/sim/frv/mmulhs.cgs deleted file mode 100644 index 2104500..0000000 --- a/sim/testsuite/sim/frv/mmulhs.cgs +++ /dev/null @@ -1,141 +0,0 @@ -# frv testcase for mmulhs $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mmulhs -mmulhs: - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x0001,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -2,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffe,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffe,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x8000,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40000000,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mmulhu.cgs b/sim/testsuite/sim/frv/mmulhu.cgs deleted file mode 100644 index 53e9b70..0000000 --- a/sim/testsuite/sim/frv/mmulhu.cgs +++ /dev/null @@ -1,82 +0,0 @@ -# frv testcase for mmulhu $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mmulhu -mmulhu: - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x00010000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00010000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0000,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mmulxhs.cgs b/sim/testsuite/sim/frv/mmulxhs.cgs deleted file mode 100644 index 449becf..0000000 --- a/sim/testsuite/sim/frv/mmulxhs.cgs +++ /dev/null @@ -1,141 +0,0 @@ -# frv testcase for mmulxhs $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mmulxhs -mmulxhs: - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 4,acc0 - test_accg_immed 0,accg1 - test_acc_immed 9,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x4000,2,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x0001,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 2,0xfffd,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -2,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,0,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0x2001,0xfffe,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffe,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffe,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x4000,0xfffe,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x7fff,0x8000,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x8000,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffe,0xfffd,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40000000,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mmulxhu.cgs b/sim/testsuite/sim/frv/mmulxhu.cgs deleted file mode 100644 index 866b64e..0000000 --- a/sim/testsuite/sim/frv/mmulxhu.cgs +++ /dev/null @@ -1,82 +0,0 @@ -# frv testcase for mmulxhu $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mmulxhu -mmulxhu: - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x4000,2,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 0x8000,2,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x00010000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00010000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0000,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mnop.cgs b/sim/testsuite/sim/frv/mnop.cgs deleted file mode 100644 index 54dda66..0000000 --- a/sim/testsuite/sim/frv/mnop.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# frv testcase for mnop -# mach: all - - .include "testutils.inc" - - start - - .global mnop -mnop: - mnop - - pass diff --git a/sim/testsuite/sim/frv/mnot.cgs b/sim/testsuite/sim/frv/mnot.cgs deleted file mode 100644 index 3a90781..0000000 --- a/sim/testsuite/sim/frv/mnot.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for mnot $FRintj,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mnot -mnot: - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - mnot fr7,fr7 - test_fr_iimmed 0x55555555,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - mnot fr7,fr7 - test_fr_iimmed 0x21524110,fr7 - - pass diff --git a/sim/testsuite/sim/frv/mor.cgs b/sim/testsuite/sim/frv/mor.cgs deleted file mode 100644 index 72feaff..0000000 --- a/sim/testsuite/sim/frv/mor.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for mor $FRinti,$FRintj,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mor -mor: - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - mor fr7,fr8,fr8 - test_fr_iimmed 0xffffffff,fr8 - - set_fr_iimmed 0x0000,0x0000,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - mor fr7,fr8,fr8 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - mor fr7,fr8,fr8 - test_fr_iimmed 0xdeadbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/mov.cgs b/sim/testsuite/sim/frv/mov.cgs deleted file mode 100644 index 8a077eb..0000000 --- a/sim/testsuite/sim/frv/mov.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for mov $GRi,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ori -ori: - set_gr_immed 0xdeadbeef,gr7 - set_gr_immed 0xbeefdead,gr8 - set_icc 0x08,0 - mov gr7,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0xdeadbeef,gr7 - test_gr_immed 0xdeadbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/movfg.cgs b/sim/testsuite/sim/frv/movfg.cgs deleted file mode 100644 index c3da00e..0000000 --- a/sim/testsuite/sim/frv/movfg.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for movfg $FRk,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global movfg -movfg: - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - movfg fr8,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/movfgd.cgs b/sim/testsuite/sim/frv/movfgd.cgs deleted file mode 100644 index cc2d60d..0000000 --- a/sim/testsuite/sim/frv/movfgd.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# frv testcase for movfgd $FRk,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global movfgd -movfgd: - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - movfgd fr8,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - pass diff --git a/sim/testsuite/sim/frv/movfgq.cgs b/sim/testsuite/sim/frv/movfgq.cgs deleted file mode 100644 index b3a90e8..0000000 --- a/sim/testsuite/sim/frv/movfgq.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for movfgq $FRk,$GRj -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global movfgq -movfgq: - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - set_gr_limmed 0,0,gr10 - set_gr_limmed 0,0,gr11 - movfgq fr8,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_fr_limmed 0x1234,0x5678,fr10 - test_fr_limmed 0x9abc,0xdef0,fr11 - - pass diff --git a/sim/testsuite/sim/frv/movgf.cgs b/sim/testsuite/sim/frv/movgf.cgs deleted file mode 100644 index 40fae33..0000000 --- a/sim/testsuite/sim/frv/movgf.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for movgf $GRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global movgf -movgf: - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - movgf gr8,fr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/movgfd.cgs b/sim/testsuite/sim/frv/movgfd.cgs deleted file mode 100644 index df844cc..0000000 --- a/sim/testsuite/sim/frv/movgfd.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# frv testcase for movgfd $GRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global movgfd -movgfd: - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - movgfd gr8,fr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - pass diff --git a/sim/testsuite/sim/frv/movgfq.cgs b/sim/testsuite/sim/frv/movgfq.cgs deleted file mode 100644 index 0196133..0000000 --- a/sim/testsuite/sim/frv/movgfq.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for movgfq $GRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global movgfq -movgfq: - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - set_fr_iimmed 0,0,fr10 - set_fr_iimmed 0,0,fr11 - movgfq gr8,fr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_fr_limmed 0x1234,0x5678,fr10 - test_fr_limmed 0x9abc,0xdef0,fr11 - - pass diff --git a/sim/testsuite/sim/frv/movgs.cgs b/sim/testsuite/sim/frv/movgs.cgs deleted file mode 100644 index f9d2f54..0000000 --- a/sim/testsuite/sim/frv/movgs.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# frv testcase for movgs $GRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global movgs -movgs: - set_gr_limmed 0xdead,0xbeef,gr8 - and_spr_immed 0,lcr - movgs gr8,lcr - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,lcr - - ; try alternate names for lcr - and_spr_immed 0,273 - movgs gr8,spr[273] ; lcr is spr number 273 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[273] - - pass diff --git a/sim/testsuite/sim/frv/movsg.cgs b/sim/testsuite/sim/frv/movsg.cgs deleted file mode 100644 index b26dbc1..0000000 --- a/sim/testsuite/sim/frv/movsg.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for movsg $FRk,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global movsg -movsg: - set_spr_limmed 0xdead,0xbeef,lcr - set_gr_limmed 0,0,gr8 - movsg lcr,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,lcr - - pass diff --git a/sim/testsuite/sim/frv/mpackh.cgs b/sim/testsuite/sim/frv/mpackh.cgs deleted file mode 100644 index 5a87cc6..0000000 --- a/sim/testsuite/sim/frv/mpackh.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# frv testcase for mpackh $FRi,$FRj,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global mpackh -mpackh: - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - mpackh fr10,fr11,fr12 - test_fr_limmed 0xbeef,0x5678,fr12 - - pass diff --git a/sim/testsuite/sim/frv/mqcpxis.cgs b/sim/testsuite/sim/frv/mqcpxis.cgs deleted file mode 100644 index 397f533..0000000 --- a/sim/testsuite/sim/frv/mqcpxis.cgs +++ /dev/null @@ -1,103 +0,0 @@ -# frv testcase for mqcpxis $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mqcpxis -mqcpxis: - ; Positive operands - set_fr_iimmed 2,4,fr8 ; multiply small numbers - set_fr_iimmed 5,3,fr10 - set_fr_iimmed 3,1,fr9 ; multiply by 0 - set_fr_iimmed 0,2,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result - set_fr_iimmed 0x0001,2,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7fff,acc1 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x2000,2,fr10 - set_fr_iimmed 0x7fff,0x0000,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xc000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x0001,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr10 - set_fr_iimmed 0xfffe,2,fr9 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -9,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr10 - set_fr_iimmed 0x2001,0xffff,fr9 ; 15 bit result - set_fr_iimmed 0xffff,0xfffe,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbfff,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0x8001,0x0000,acc1 - - ; Negative operands - set_fr_iimmed 0x8000,0x8000,fr8 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0xfffe,0xfffc,fr9 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0x00,accg0 - test_acc_limmed 0x8000,0x0000,acc0 - test_accg_immed 0x00,accg1 - test_acc_immed 26,acc1 - - set_fr_iimmed 0xffff,0xffff,fr8 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x0000,fr9 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x0000,fr8 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x8000,0x0000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40000000,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mqcpxiu.cgs b/sim/testsuite/sim/frv/mqcpxiu.cgs deleted file mode 100644 index 22d48f6..0000000 --- a/sim/testsuite/sim/frv/mqcpxiu.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for mqcpxiu $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mqcpxiu -mqcpxiu: - set_fr_iimmed 4,2,fr8 ; multiply small numbers - set_fr_iimmed 3,5,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 1,3,fr11 - mqcpxiu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 26,acc0 - test_accg_immed 0,accg1 - test_acc_immed 5,acc1 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 0,2,fr10 - set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result - set_fr_iimmed 0x0001,2,fr11 - mqcpxiu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x7fff,acc1 - - set_fr_iimmed 0x4000,1,fr8 ; 16 bit result - set_fr_iimmed 0x0001,2,fr10 - set_fr_iimmed 0x4000,1,fr9 ; 17 bit result - set_fr_iimmed 0x0001,4,fr11 - mqcpxiu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x0010001,acc1 - - set_fr_iimmed 0x7fff,0x0000,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr11 - mqcpxiu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0000,acc1 - - set_fr_iimmed 0xffff,0x0000,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - mqcpxiu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 1,accg1 - test_acc_immed 0xfffc0002,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mqcpxrs.cgs b/sim/testsuite/sim/frv/mqcpxrs.cgs deleted file mode 100644 index d1d1f48..0000000 --- a/sim/testsuite/sim/frv/mqcpxrs.cgs +++ /dev/null @@ -1,103 +0,0 @@ -# frv testcase for mqcpxrs $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mqcpxrs -mqcpxrs: - ; Positive operands - set_fr_iimmed 2,4,fr8 ; multiply small numbers - set_fr_iimmed 3,5,fr10 - set_fr_iimmed 3,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x0007,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ff0,acc1 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x2000,fr10 - set_fr_iimmed 0x7fff,0x0000,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x4000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x0001,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr10 - set_fr_iimmed 0xfffe,2,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -3,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbff0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8006,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0x8000,0x8000,acc1 - - ; Negative operands - set_fr_iimmed 0x8000,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0xfffe,0xfffc,fr9 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x7fff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -14,acc1 - - set_fr_iimmed 0xffff,0xffff,fr8 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr10 - set_fr_iimmed 0x7fff,0x0000,fr9 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x0000,fr8 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x8000,0x0000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40000000,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mqcpxru.cgs b/sim/testsuite/sim/frv/mqcpxru.cgs deleted file mode 100644 index 45e1b35..0000000 --- a/sim/testsuite/sim/frv/mqcpxru.cgs +++ /dev/null @@ -1,78 +0,0 @@ -# frv testcase for mqcpxru $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mqcpxru -mqcpxru: - set_fr_iimmed 4,2,fr8 ; multiply small numbers - set_fr_iimmed 5,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 3,1,fr11 - mqcpxru fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 14,acc0 - test_accg_immed 0,accg1 - test_acc_immed 1,acc1 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result - set_fr_iimmed 2,0x0001,fr11 - mqcpxru fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x7ffd,acc1 - - set_fr_iimmed 0x4000,1,fr8 ; 16 bit result - set_fr_iimmed 4,0x0001,fr10 - set_fr_iimmed 0x8000,1,fr9 ; 17 bit result - set_fr_iimmed 4,0x0001,fr11 - mqcpxru fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x0001ffff,acc1 - - set_fr_iimmed 0x7fff,0x0000,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr11 - mqcpxru fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0000,acc1 - - set_fr_iimmed 0xffff,0x0000,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0x0001,fr9 ; saturation - set_fr_iimmed 0xffff,0x0001,fr11 - mqcpxru fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0xffff,fr8 ; saturation - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xfffe,0xffff,fr9 ; saturation - set_fr_iimmed 0xffff,0xffff,fr11 - mqcpxru fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mqlclrhs.cgs b/sim/testsuite/sim/frv/mqlclrhs.cgs deleted file mode 100644 index 5e090b0..0000000 --- a/sim/testsuite/sim/frv/mqlclrhs.cgs +++ /dev/null @@ -1,74 +0,0 @@ -# frv testcase for mqlclrhs $FRi,$FRj,$FRj -# mach: fr450 - - .include "testutils.inc" - - start - - .global mqlclrhs -mqlclrhs: - set_fr_iimmed 0x1000,0x2000,fr4 - set_fr_iimmed 0xe800,0xd800,fr5 - set_fr_iimmed 0x0800,0x0800,fr6 - set_fr_iimmed 0x0800,0x0800,fr7 - mqlclrhs fr4,fr6,fr8 - test_fr_limmed 0x1000,0x2000,fr8 - test_fr_limmed 0xe800,0xd800,fr9 - - set_fr_iimmed 0x1000,0x2000,fr4 - set_fr_iimmed 0xe800,0xd800,fr5 - set_fr_iimmed 0xf800,0xf800,fr6 - set_fr_iimmed 0xf800,0xf800,fr7 - mqlclrhs fr4,fr6,fr8 - test_fr_limmed 0xf000,0xe000,fr8 - test_fr_limmed 0x1800,0x2800,fr9 - - set_fr_iimmed 0x1000,0x1000,fr4 - set_fr_iimmed 0x1000,0x1000,fr5 - set_fr_iimmed 0xf000,0xf800,fr6 - set_fr_iimmed 0x0800,0x1000,fr7 - mqlclrhs fr4,fr6,fr8 - test_fr_limmed 0x0000,0xf000,fr8 - test_fr_limmed 0x1000,0x0000,fr9 - - set_fr_iimmed 0xf000,0xf000,fr4 - set_fr_iimmed 0xf000,0xf000,fr5 - set_fr_iimmed 0xf000,0xf800,fr6 - set_fr_iimmed 0x0800,0x1000,fr7 - mqlclrhs fr4,fr6,fr8 - test_fr_limmed 0x0000,0x1000,fr8 - test_fr_limmed 0xf000,0x0000,fr9 - - set_fr_iimmed 0x8000,0x8000,fr4 - set_fr_iimmed 0x8000,0x8000,fr5 - set_fr_iimmed 0x8000,0x7fff,fr6 - set_fr_iimmed 0x8001,0x0000,fr7 - mqlclrhs fr4,fr6,fr8 - test_fr_limmed 0x0000,0x8000,fr8 - test_fr_limmed 0x7fff,0x8000,fr9 - - set_fr_iimmed 0x7fff,0x7fff,fr4 - set_fr_iimmed 0x7fff,0x7fff,fr5 - set_fr_iimmed 0x8000,0x7fff,fr6 - set_fr_iimmed 0x8001,0x0000,fr7 - mqlclrhs fr4,fr6,fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_fr_limmed 0x0000,0x7fff,fr9 - - set_fr_iimmed 0x8001,0x8001,fr4 - set_fr_iimmed 0x8001,0x8001,fr5 - set_fr_iimmed 0x8000,0x7fff,fr6 - set_fr_iimmed 0x8001,0x0000,fr7 - mqlclrhs fr4,fr6,fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_fr_limmed 0x0000,0x8001,fr9 - - set_fr_iimmed 0x8000,0x8000,fr4 - set_fr_iimmed 0x0001,0xffff,fr5 - set_fr_iimmed 0x0001,0xffff,fr6 - set_fr_iimmed 0x8000,0x8000,fr7 - mqlclrhs fr4,fr6,fr8 - test_fr_limmed 0x8000,0x7fff,fr8 - test_fr_limmed 0x0000,0x0000,fr9 - - pass diff --git a/sim/testsuite/sim/frv/mqlmths.cgs b/sim/testsuite/sim/frv/mqlmths.cgs deleted file mode 100644 index d416d65..0000000 --- a/sim/testsuite/sim/frv/mqlmths.cgs +++ /dev/null @@ -1,74 +0,0 @@ -# frv testcase for mqlmths $FRi,$FRj,$FRj -# mach: fr450 - - .include "testutils.inc" - - start - - .global mqlmths -mqlmths: - set_fr_iimmed 0x1000,0x2000,fr4 - set_fr_iimmed 0xe800,0xd800,fr5 - set_fr_iimmed 0x0800,0x0800,fr6 - set_fr_iimmed 0x0800,0x0800,fr7 - mqlmths fr4,fr6,fr8 - test_fr_limmed 0x0800,0x0800,fr8 - test_fr_limmed 0xf800,0xf800,fr9 - - set_fr_iimmed 0x1000,0x2000,fr4 - set_fr_iimmed 0xe800,0xd800,fr5 - set_fr_iimmed 0xf800,0xf800,fr6 - set_fr_iimmed 0xf800,0xf800,fr7 - mqlmths fr4,fr6,fr8 - test_fr_limmed 0xf800,0xf800,fr8 - test_fr_limmed 0x0800,0x0800,fr9 - - set_fr_iimmed 0x1000,0x1000,fr4 - set_fr_iimmed 0x1000,0x1000,fr5 - set_fr_iimmed 0xe800,0xf800,fr6 - set_fr_iimmed 0x0800,0x1800,fr7 - mqlmths fr4,fr6,fr8 - test_fr_limmed 0x1000,0xf800,fr8 - test_fr_limmed 0x0800,0x1000,fr9 - - set_fr_iimmed 0xf000,0xf000,fr4 - set_fr_iimmed 0xf000,0xf000,fr5 - set_fr_iimmed 0xe800,0xf800,fr6 - set_fr_iimmed 0x0800,0x1800,fr7 - mqlmths fr4,fr6,fr8 - test_fr_limmed 0xf000,0x0800,fr8 - test_fr_limmed 0xf800,0xf000,fr9 - - set_fr_iimmed 0x8000,0x8000,fr4 - set_fr_iimmed 0x8000,0x8000,fr5 - set_fr_iimmed 0x8000,0x7fff,fr6 - set_fr_iimmed 0x8001,0x0000,fr7 - mqlmths fr4,fr6,fr8 - test_fr_limmed 0x7fff,0x8001,fr8 - test_fr_limmed 0x7fff,0x0000,fr9 - - set_fr_iimmed 0x7fff,0x7fff,fr4 - set_fr_iimmed 0x7fff,0x7fff,fr5 - set_fr_iimmed 0x8000,0x7fff,fr6 - set_fr_iimmed 0x8001,0x0000,fr7 - mqlmths fr4,fr6,fr8 - test_fr_limmed 0x7fff,0x7fff,fr8 - test_fr_limmed 0x8001,0x0000,fr9 - - set_fr_iimmed 0x8001,0x8001,fr4 - set_fr_iimmed 0x8001,0x8001,fr5 - set_fr_iimmed 0x8000,0x7fff,fr6 - set_fr_iimmed 0x8001,0x0000,fr7 - mqlmths fr4,fr6,fr8 - test_fr_limmed 0x8001,0x8001,fr8 - test_fr_limmed 0x7fff,0x0000,fr9 - - set_fr_iimmed 0x8000,0x8000,fr4 - set_fr_iimmed 0x0001,0xffff,fr5 - set_fr_iimmed 0x0001,0xffff,fr6 - set_fr_iimmed 0x8000,0x8000,fr7 - mqlmths fr4,fr6,fr8 - test_fr_limmed 0xffff,0x0001,fr8 - test_fr_limmed 0x0001,0xffff,fr9 - - pass diff --git a/sim/testsuite/sim/frv/mqmachs.cgs b/sim/testsuite/sim/frv/mqmachs.cgs deleted file mode 100644 index 5608c64..0000000 --- a/sim/testsuite/sim/frv/mqmachs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqmachs $GRi,$GRj,$ACCk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mqmachs -mqmachs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - pass - - diff --git a/sim/testsuite/sim/frv/mqmachu.cgs b/sim/testsuite/sim/frv/mqmachu.cgs deleted file mode 100644 index e16be68..0000000 --- a/sim/testsuite/sim/frv/mqmachu.cgs +++ /dev/null @@ -1,144 +0,0 @@ -# frv testcase for mqmachu $GRi,$GRj,$GRk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mqmachu -mqmachu: - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8000,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00018000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00018000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff8007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff8007,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4001,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4001,0x8000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x3ffd,0x8008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x3ffd,0x8008,acc1 - test_accg_immed 1,accg2 - test_acc_limmed 0x3fff,0x8001,acc2 - test_accg_immed 1,accg3 - test_acc_limmed 0x3fff,0x8001,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mqmacxhs.cgs b/sim/testsuite/sim/frv/mqmacxhs.cgs deleted file mode 100644 index 0be1151..0000000 --- a/sim/testsuite/sim/frv/mqmacxhs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqmacxhs $GRi,$GRj,$ACCk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mqmacxhs -mqmacxhs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 0,2,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 2,1,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x4000,2,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 2,0xfffd,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0xfffe,0,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0x2001,0xfffe,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0x4000,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x7fff,0x8000,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffe,0xfffd,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 0xffff,1,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - pass - - diff --git a/sim/testsuite/sim/frv/mqmulhs.cgs b/sim/testsuite/sim/frv/mqmulhs.cgs deleted file mode 100644 index 0a10c29..0000000 --- a/sim/testsuite/sim/frv/mqmulhs.cgs +++ /dev/null @@ -1,125 +0,0 @@ -# frv testcase for mqmulhs $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mqmulhs -mqmulhs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x0001,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - test_accg_immed 0xff,accg2 - test_acc_immed -2,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -2,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffe,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffe,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xc000,0x8000,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xc000,0x8000,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x40000000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x40000000,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mqmulhu.cgs b/sim/testsuite/sim/frv/mqmulhu.cgs deleted file mode 100644 index e94c09ae9..0000000 --- a/sim/testsuite/sim/frv/mqmulhu.cgs +++ /dev/null @@ -1,80 +0,0 @@ -# frv testcase for mqmulhu $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mqmulhu -mqmulhu: - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - mqmulhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqmulhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - mqmulhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00010000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00010000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmulhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4000,0x0000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - mqmulhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0xfffe,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xfffe,0x0001,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mqmulxhs.cgs b/sim/testsuite/sim/frv/mqmulxhs.cgs deleted file mode 100644 index 7686bc1..0000000 --- a/sim/testsuite/sim/frv/mqmulxhs.cgs +++ /dev/null @@ -1,125 +0,0 @@ -# frv testcase for mqmulxhs $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mqmulxhs -mqmulxhs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 0,2,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 4,acc0 - test_accg_immed 0,accg1 - test_acc_immed 9,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 2,1,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x4000,2,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x0001,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 2,0xfffd,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - test_accg_immed 0xff,accg2 - test_acc_immed -2,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -2,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0xfffe,0,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0x2001,0xfffe,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffe,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffe,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0x4000,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x7fff,0x8000,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xc000,0x8000,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xc000,0x8000,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffe,0xfffd,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x40000000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x40000000,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mqmulxhu.cgs b/sim/testsuite/sim/frv/mqmulxhu.cgs deleted file mode 100644 index b60e421..0000000 --- a/sim/testsuite/sim/frv/mqmulxhu.cgs +++ /dev/null @@ -1,80 +0,0 @@ -# frv testcase for mqmulxhu $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mqmulxhu -mqmulxhu: - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 1,2,fr11 - mqmulxhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 0,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr11 - mqmulxhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x4000,2,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 0x8000,2,fr11 - mqmulxhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00010000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00010000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmulxhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4000,0x0000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - mqmulxhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0xfffe,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xfffe,0x0001,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mqsaths.cgs b/sim/testsuite/sim/frv/mqsaths.cgs deleted file mode 100644 index 61ff112..0000000 --- a/sim/testsuite/sim/frv/mqsaths.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for mqsaths $FRi,$FRj,$FRj -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global mqsaths -mqsaths: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0001,0x7fff,fr11 - set_fr_iimmed 0x0000,0x0000,fr13 - mqsaths fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr11 - set_fr_iimmed 0x0040,0x0040,fr13 - mqsaths fr10,fr12,fr14 - test_fr_limmed 0xffff,0xffff,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x0040,0x0040,fr12 - set_fr_iimmed 0xffff,0x8000,fr11 - set_fr_iimmed 0x0040,0x0040,fr13 - mqsaths fr10,fr12,fr14 - test_fr_limmed 0x0001,0x0040,fr14 - test_fr_limmed 0xffff,0xffbf,fr15 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr12 - set_fr_iimmed 0x0001,0x7fff,fr11 - set_fr_iimmed 0x7fff,0x7fff,fr13 - mqsaths fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0001,0x7fff,fr15 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr12 - set_fr_iimmed 0xffff,0x8000,fr11 - set_fr_iimmed 0x7fff,0x7fff,fr13 - mqsaths fr10,fr12,fr14 - test_fr_limmed 0xffff,0x8000,fr14 - test_fr_limmed 0xffff,0x8000,fr15 - - pass diff --git a/sim/testsuite/sim/frv/mqsllhi.cgs b/sim/testsuite/sim/frv/mqsllhi.cgs deleted file mode 100644 index 21379f2..0000000 --- a/sim/testsuite/sim/frv/mqsllhi.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# frv testcase for mqsllhi $FRi,#u6,$FRj -# mach: fr450 - - .include "testutils.inc" - - start - - .global mqsllhi -mqsllhi: - set_fr_iimmed 0x0001,0x0002,fr4 - set_fr_iimmed 0x0003,0x0004,fr5 - mqsllhi fr4,#1,fr6 - test_fr_limmed 0x0002,0x0004,fr6 - test_fr_limmed 0x0006,0x0008,fr7 - - set_fr_iimmed 0xffff,0xfffe,fr4 - set_fr_iimmed 0xfffc,0xfff8,fr5 - mqsllhi fr4,#1,fr6 - test_fr_limmed 0xfffe,0xfffc,fr6 - test_fr_limmed 0xfff8,0xfff0,fr7 - - set_fr_iimmed 0xffff,0xfffe,fr4 - set_fr_iimmed 0xfffc,0xfff8,fr5 - mqsllhi fr4,#12,fr6 - test_fr_limmed 0xf000,0xe000,fr6 - test_fr_limmed 0xc000,0x8000,fr7 - - set_fr_iimmed 0x1234,0x5678,fr4 - set_fr_iimmed 0x9abc,0xdef0,fr5 - mqsllhi fr4,#12,fr6 - test_fr_limmed 0x4000,0x8000,fr6 - test_fr_limmed 0xc000,0x0000,fr7 - - set_fr_iimmed 0x1234,0x5678,fr4 - set_fr_iimmed 0x9abc,0xdef0,fr5 - mqsllhi fr4,#16,fr6 - test_fr_limmed 0x1234,0x5678,fr6 - test_fr_limmed 0x9abc,0xdef0,fr7 - - pass diff --git a/sim/testsuite/sim/frv/mqsrahi.cgs b/sim/testsuite/sim/frv/mqsrahi.cgs deleted file mode 100644 index 1d30179..0000000 --- a/sim/testsuite/sim/frv/mqsrahi.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# frv testcase for mqsrahi $FRi,#u6,$FRj -# mach: fr450 - - .include "testutils.inc" - - start - - .global mqsrahi -mqsrahi: - set_fr_iimmed 0x0001,0x0002,fr4 - set_fr_iimmed 0x0003,0x0004,fr5 - mqsrahi fr4,#1,fr6 - test_fr_limmed 0x0000,0x0001,fr6 - test_fr_limmed 0x0001,0x0002,fr7 - - set_fr_iimmed 0xffff,0xfffe,fr4 - set_fr_iimmed 0xfffc,0xfff8,fr5 - mqsrahi fr4,#1,fr6 - test_fr_limmed 0xffff,0xffff,fr6 - test_fr_limmed 0xfffe,0xfffc,fr7 - - set_fr_iimmed 0x8000,0xc000,fr4 - set_fr_iimmed 0xe000,0xf000,fr5 - mqsrahi fr4,#12,fr6 - test_fr_limmed 0xfff8,0xfffc,fr6 - test_fr_limmed 0xfffe,0xffff,fr7 - - set_fr_iimmed 0x1234,0x5678,fr4 - set_fr_iimmed 0x9abc,0xdef0,fr5 - mqsrahi fr4,#12,fr6 - test_fr_limmed 0x0001,0x0005,fr6 - test_fr_limmed 0xfff9,0xfffd,fr7 - - set_fr_iimmed 0x1234,0x5678,fr4 - set_fr_iimmed 0x9abc,0xdef0,fr5 - mqsrahi fr4,#16,fr6 - test_fr_limmed 0x1234,0x5678,fr6 - test_fr_limmed 0x9abc,0xdef0,fr7 - - pass diff --git a/sim/testsuite/sim/frv/mqxmachs.cgs b/sim/testsuite/sim/frv/mqxmachs.cgs deleted file mode 100644 index 6791ed3..0000000 --- a/sim/testsuite/sim/frv/mqxmachs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqxmachs $GRi,$GRj,$ACCk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mqxmachs -mqxmachs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_immed 6,acc2 - test_accg_immed 0,accg3 - test_acc_immed 6,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_immed 8,acc2 - test_accg_immed 0,accg3 - test_acc_immed 8,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8008,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7fff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7fff,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7ffd,acc1 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffb,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffb,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffb,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffb,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0008,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_immed 0x3fff0009,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fff0009,acc3 - test_accg_immed 0,accg0 - test_acc_immed 0x3fffbffd,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fffbffd,acc1 - - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/mqxmacxhs.cgs b/sim/testsuite/sim/frv/mqxmacxhs.cgs deleted file mode 100644 index c644eed..0000000 --- a/sim/testsuite/sim/frv/mqxmacxhs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mqxmacxhs -mqxmacxhs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 0,2,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_immed 6,acc2 - test_accg_immed 0,accg3 - test_acc_immed 6,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 2,1,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_immed 8,acc2 - test_accg_immed 0,accg3 - test_acc_immed 8,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x4000,2,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8008,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7fff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7fff,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 2,0xfffd,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7ffd,acc1 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0xfffe,0,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0x2001,0xfffe,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffb,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffb,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0x4000,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x7fff,0x8000,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffb,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffb,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffe,0xfffd,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0008,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_immed 0x3fff0009,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fff0009,acc3 - test_accg_immed 0,accg0 - test_acc_immed 0x3fffbffd,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fffbffd,acc1 - - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 0xffff,1,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/mrdacc.cgs b/sim/testsuite/sim/frv/mrdacc.cgs deleted file mode 100644 index 2178036..0000000 --- a/sim/testsuite/sim/frv/mrdacc.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mrdacc $ACC40i,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mrdacc -mrdacc: - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed -1,accg3 - set_acc_immed -1,acc3 - set_accg_immed 0x12,accg2 - set_acc_immed 0xdeadbeef,acc2 - - mrdacc acc0,fr10 - test_fr_iimmed 0,fr10 - - mrdacc acc3,fr10 - test_fr_iimmed 0xffffffff,fr10 - - mrdacc acc2,fr10 - test_fr_iimmed 0xdeadbeef,fr10 - - pass diff --git a/sim/testsuite/sim/frv/mrdaccg.cgs b/sim/testsuite/sim/frv/mrdaccg.cgs deleted file mode 100644 index 96e9406..0000000 --- a/sim/testsuite/sim/frv/mrdaccg.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mrdaccg $ACC40i,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mrdaccg -mrdaccg: - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed -1,accg3 - set_acc_immed -1,acc3 - set_accg_immed 0x12,accg2 - set_acc_immed 0xdeadbeef,acc2 - - mrdaccg accg0,fr10 - test_fr_iimmed 0,fr10 - - mrdaccg accg3,fr10 - test_fr_iimmed 0x000000ff,fr10 - - mrdaccg accg2,fr10 - test_fr_iimmed 0x00000012,fr10 - - pass diff --git a/sim/testsuite/sim/frv/mrotli.cgs b/sim/testsuite/sim/frv/mrotli.cgs deleted file mode 100644 index 02220ee..0000000 --- a/sim/testsuite/sim/frv/mrotli.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for mrotli $FRi,$s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mrotli -mrotli: - set_fr_iimmed 0,2,fr8 - mrotli fr8,0x20,fr8 ; Shift by 0 - test_fr_iimmed 2,fr8 - - set_fr_iimmed 0,2,fr8 - mrotli fr8,0,fr8 ; Shift by 0 - test_fr_iimmed 2,fr8 - - set_fr_iimmed 0,2,fr8 - mrotli fr8,1,fr8 ; Shift by 1 - test_fr_iimmed 4,fr8 - - set_fr_iimmed 0,1,fr8 - mrotli fr8,31,fr8 ; Shift by 31 - test_fr_iimmed 0x80000000,fr8 - - set_fr_iimmed 0,2,fr8 - mrotli fr8,31,fr8 ; max rotation - test_fr_iimmed 1,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - mrotli fr8,16,fr8 - test_fr_iimmed 0xbeefdead,fr8 - - pass diff --git a/sim/testsuite/sim/frv/mrotri.cgs b/sim/testsuite/sim/frv/mrotri.cgs deleted file mode 100644 index 17a5c74..0000000 --- a/sim/testsuite/sim/frv/mrotri.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for mrotri $FRinti,$s6,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mrotri -mrotri: - set_fr_iimmed 0x8000,0x0000,fr8 - mrotri fr8,0x20,fr8 ; Shift by 0 - test_fr_iimmed 0x80000000,fr8 - - set_fr_iimmed 0x8000,0x0000,fr8 - mrotri fr8,0,fr8 ; Shift by 0 - test_fr_iimmed 0x80000000,fr8 - - set_fr_iimmed 0x8000,0x0000,fr8 - mrotri fr8,1,fr8 ; Shift by 1 - test_fr_iimmed 0x40000000,fr8 - - set_fr_iimmed 0x8000,0x0000,fr8 - mrotri fr8,31,fr8 ; Shift by 31 - test_fr_iimmed 1,fr8 - - set_fr_iimmed 0x4000,0x0000,fr8 - mrotri fr8,31,fr8 ; max shift - test_fr_iimmed 0x80000000,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - mrotri fr8,16,fr8 ; max shift - test_fr_iimmed 0xbeefdead,fr8 - - pass diff --git a/sim/testsuite/sim/frv/msaths.cgs b/sim/testsuite/sim/frv/msaths.cgs deleted file mode 100644 index 513d5d3..0000000 --- a/sim/testsuite/sim/frv/msaths.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for msaths $FRi,$FRj,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global msaths -msaths: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0040,0x0040,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x0040,0x0040,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0x0001,0x0040,fr12 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x0040,0x0040,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0xffff,0xffbf,fr12 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0x0001,0x7fff,fr12 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0xffff,0x8000,fr12 - - pass diff --git a/sim/testsuite/sim/frv/msathu.cgs b/sim/testsuite/sim/frv/msathu.cgs deleted file mode 100644 index 4f376b2..0000000 --- a/sim/testsuite/sim/frv/msathu.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for msathu $FRi,$FRj,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global msathu -msathu: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0040,0x0040,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x0040,0x0040,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0001,0x0040,fr12 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x0040,0x0040,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0040,0x0040,fr12 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0001,0x7fff,fr12 - - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x7fff,0xffff,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x7fff,0xffff,fr12 - - pass diff --git a/sim/testsuite/sim/frv/msllhi.cgs b/sim/testsuite/sim/frv/msllhi.cgs deleted file mode 100644 index 4340b9f..0000000 --- a/sim/testsuite/sim/frv/msllhi.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for msllhi $FRi,$s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global msllhi -msllhi: - set_fr_iimmed 2,2,fr8 - msllhi fr8,0x20,fr8 ; Shift by 0 - test_fr_limmed 2,2,fr8 - - set_fr_iimmed 2,2,fr8 - msllhi fr8,0,fr8 ; Shift by 0 - test_fr_limmed 2,2,fr8 - - set_fr_iimmed 2,2,fr8 - msllhi fr8,1,fr8 ; Shift by 1 - test_fr_limmed 4,4,fr8 - - set_fr_iimmed 1,1,fr8 - msllhi fr8,31,fr8 ; Shift by 15 - test_fr_limmed 0x8000,0x8000,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - msllhi fr8,15,fr8 - test_fr_iimmed 0x80008000,fr8 - - pass diff --git a/sim/testsuite/sim/frv/msrahi.cgs b/sim/testsuite/sim/frv/msrahi.cgs deleted file mode 100644 index 182f84e..0000000 --- a/sim/testsuite/sim/frv/msrahi.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for msrahi $FRi,$s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global msrahi -msrahi: - set_fr_iimmed 2,2,fr8 - msrahi fr8,0x20,fr8 ; Shift by 0 - test_fr_limmed 2,2,fr8 - - set_fr_iimmed 2,2,fr8 - msrahi fr8,0,fr8 ; Shift by 0 - test_fr_limmed 2,2,fr8 - - set_fr_iimmed 3,2,fr8 - msrahi fr8,1,fr8 ; Shift by 1 - test_fr_limmed 1,1,fr8 - - set_fr_iimmed 0x8000,0x7fff,fr8 - msrahi fr8,31,fr8 ; Shift by 15 - test_fr_limmed 0xffff,0x0000,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - msrahi fr8,15,fr8 - test_fr_iimmed 0xffffffff,fr8 - - pass diff --git a/sim/testsuite/sim/frv/msrlhi.cgs b/sim/testsuite/sim/frv/msrlhi.cgs deleted file mode 100644 index c9971a9..0000000 --- a/sim/testsuite/sim/frv/msrlhi.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for msrlhi $FRi,$s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global msrlhi -msrlhi: - set_fr_iimmed 2,2,fr8 - msrlhi fr8,0x20,fr8 ; Shift by 0 - test_fr_limmed 2,2,fr8 - - set_fr_iimmed 2,2,fr8 - msrlhi fr8,0,fr8 ; Shift by 0 - test_fr_limmed 2,2,fr8 - - set_fr_iimmed 3,2,fr8 - msrlhi fr8,1,fr8 ; Shift by 1 - test_fr_limmed 1,1,fr8 - - set_fr_iimmed 0xffff,0x8000,fr8 - msrlhi fr8,31,fr8 ; Shift by 15 - test_fr_limmed 0x0001,0x0001,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - msrlhi fr8,15,fr8 - test_fr_iimmed 0x00010001,fr8 - - pass diff --git a/sim/testsuite/sim/frv/msubhss.cgs b/sim/testsuite/sim/frv/msubhss.cgs deleted file mode 100644 index 1ba3343..0000000 --- a/sim/testsuite/sim/frv/msubhss.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for msubhss $FRi,$FRj,$FRj -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global msubhss -msubhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0xdead,0x4111,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x4111,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x1235,0x5679,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - msubhss.p fr10,fr10,fr12 - msubhss fr11,fr10,fr13 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x8000,0x8000,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/msubhus.cgs b/sim/testsuite/sim/frv/msubhus.cgs deleted file mode 100644 index 1a002da..0000000 --- a/sim/testsuite/sim/frv/msubhus.cgs +++ /dev/null @@ -1,80 +0,0 @@ -# frv testcase for msubhus $FRi,$FRj,$FRj -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global msubhus -msubhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - msubhus.p fr10,fr10,fr12 - msubhus fr10,fr11,fr13 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/mtrap.cgs b/sim/testsuite/sim/frv/mtrap.cgs deleted file mode 100644 index 65b947a..0000000 --- a/sim/testsuite/sim/frv/mtrap.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for mp_exception -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mp_exception -mpx: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 0x0e0,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_psr_et 1 - set_gr_immed 0,gr5 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - mtrap ; generate interrupt - test_gr_immed 1,gr5 - - and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields - mcmpsh fr10,fr11,fcc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - mtrap ; nop - test_gr_immed 1,gr5 - - pass - -; exception handler -ok1: - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - inc_gr_immed 1,gr5 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/munpackh.cgs b/sim/testsuite/sim/frv/munpackh.cgs deleted file mode 100644 index 45b2bd8..0000000 --- a/sim/testsuite/sim/frv/munpackh.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# frv testcase for munpackh $FRi,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global munpackh -munpackh: - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - munpackh fr10,fr12 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - munpackh fr10,fr12 - test_fr_limmed 0x1234,0x1234,fr12 - test_fr_limmed 0x5678,0x5678,fr13 - - pass diff --git a/sim/testsuite/sim/frv/mwcut.cgs b/sim/testsuite/sim/frv/mwcut.cgs deleted file mode 100644 index 0e31b8f..0000000 --- a/sim/testsuite/sim/frv/mwcut.cgs +++ /dev/null @@ -1,269 +0,0 @@ -# frv testcase for mwcut $FRi,FRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mwcut -mwcut: - set_fr_iimmed 0x0123,0x4567,fr8 - set_fr_iimmed 0x89ab,0xcdef,fr9 - - set_fr_iimmed 0,0,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x01234567,fr11 - - set_fr_iimmed 0,1,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x02468acf,fr11 - - set_fr_iimmed 0,2,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x048d159e,fr11 - - set_fr_iimmed 0,3,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x091a2b3c,fr11 - - set_fr_iimmed 0,4,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x12345678,fr11 - - set_fr_iimmed 0,5,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x2468acf1,fr11 - - set_fr_iimmed 0,6,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x48d159e2,fr11 - - set_fr_iimmed 0,7,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x91a2b3c4,fr11 - - set_fr_iimmed 0,8,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x23456789,fr11 - - set_fr_iimmed 0,9,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x468acf13,fr11 - - set_fr_iimmed 0,10,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x8d159e26,fr11 - - set_fr_iimmed 0,11,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x1a2b3c4d,fr11 - - set_fr_iimmed 0,12,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x3456789a,fr11 - - set_fr_iimmed 0,13,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x68acf135,fr11 - - set_fr_iimmed 0,14,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xd159e26a,fr11 - - set_fr_iimmed 0,15,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xa2b3c4d5,fr11 - - set_fr_iimmed 0,16,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x456789ab,fr11 - - set_fr_iimmed 0,17,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x8acf1357,fr11 - - set_fr_iimmed 0,18,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x159e26af,fr11 - - set_fr_iimmed 0,19,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x2b3c4d5e,fr11 - - set_fr_iimmed 0,20,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x56789abc,fr11 - - set_fr_iimmed 0,21,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xacf13579,fr11 - - set_fr_iimmed 0,22,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x59e26af3,fr11 - - set_fr_iimmed 0,23,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xb3c4d5e6,fr11 - - set_fr_iimmed 0,24,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x6789abcd,fr11 - - set_fr_iimmed 0,25,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xcf13579b,fr11 - - set_fr_iimmed 0,26,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x9e26af37,fr11 - - set_fr_iimmed 0,27,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x3c4d5e6f,fr11 - - set_fr_iimmed 0,28,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x789abcde,fr11 - - set_fr_iimmed 0,29,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xf13579bd,fr11 - - set_fr_iimmed 0,30,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xe26af37b,fr11 - - set_fr_iimmed 0,31,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xc4d5e6f7,fr11 - - set_fr_iimmed 0,32,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x89abcdef,fr11 - - set_fr_iimmed 0,33,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x13579bde,fr11 - - set_fr_iimmed 0,34,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x26af37bc,fr11 - - set_fr_iimmed 0,35,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x4d5e6f78,fr11 - - set_fr_iimmed 0,36,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x9abcdef0,fr11 - - set_fr_iimmed 0,37,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x3579bde0,fr11 - - set_fr_iimmed 0,38,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x6af37bc0,fr11 - - set_fr_iimmed 0,39,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xd5e6f780,fr11 - - set_fr_iimmed 0,40,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xabcdef00,fr11 - - set_fr_iimmed 0,41,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x579bde00,fr11 - - set_fr_iimmed 0,42,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xaf37bc00,fr11 - - set_fr_iimmed 0,43,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x5e6f7800,fr11 - - set_fr_iimmed 0,44,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xbcdef000,fr11 - - set_fr_iimmed 0,45,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x79bde000,fr11 - - set_fr_iimmed 0,46,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xf37bc000,fr11 - - set_fr_iimmed 0,47,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xe6f78000,fr11 - - set_fr_iimmed 0,48,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xcdef0000,fr11 - - set_fr_iimmed 0,49,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x9bde0000,fr11 - - set_fr_iimmed 0,50,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x37bc0000,fr11 - - set_fr_iimmed 0,51,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x6f780000,fr11 - - set_fr_iimmed 0,52,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xdef00000,fr11 - - set_fr_iimmed 0,53,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xbde00000,fr11 - - set_fr_iimmed 0,54,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x7bc00000,fr11 - - set_fr_iimmed 0,55,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xf7800000,fr11 - - set_fr_iimmed 0,56,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xef000000,fr11 - - set_fr_iimmed 0,57,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xde000000,fr11 - - set_fr_iimmed 0,58,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xbc000000,fr11 - - set_fr_iimmed 0,59,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x78000000,fr11 - - set_fr_iimmed 0,60,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xf0000000,fr11 - - set_fr_iimmed 0,61,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xe0000000,fr11 - - set_fr_iimmed 0,62,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xc0000000,fr11 - - set_fr_iimmed 0,63,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mwcuti.cgs b/sim/testsuite/sim/frv/mwcuti.cgs deleted file mode 100644 index 338eab8..0000000 --- a/sim/testsuite/sim/frv/mwcuti.cgs +++ /dev/null @@ -1,205 +0,0 @@ -# frv testcase for mwcuti $FRi,s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mwcuti -mwcuti: - set_fr_iimmed 0x0123,0x4567,fr8 - set_fr_iimmed 0x89ab,0xcdef,fr9 - - mwcuti fr8,0,fr11 - test_fr_iimmed 0x01234567,fr11 - - mwcuti fr8,1,fr11 - test_fr_iimmed 0x02468acf,fr11 - - mwcuti fr8,2,fr11 - test_fr_iimmed 0x048d159e,fr11 - - mwcuti fr8,3,fr11 - test_fr_iimmed 0x091a2b3c,fr11 - - mwcuti fr8,4,fr11 - test_fr_iimmed 0x12345678,fr11 - - mwcuti fr8,5,fr11 - test_fr_iimmed 0x2468acf1,fr11 - - mwcuti fr8,6,fr11 - test_fr_iimmed 0x48d159e2,fr11 - - mwcuti fr8,7,fr11 - test_fr_iimmed 0x91a2b3c4,fr11 - - mwcuti fr8,8,fr11 - test_fr_iimmed 0x23456789,fr11 - - mwcuti fr8,9,fr11 - test_fr_iimmed 0x468acf13,fr11 - - mwcuti fr8,10,fr11 - test_fr_iimmed 0x8d159e26,fr11 - - mwcuti fr8,11,fr11 - test_fr_iimmed 0x1a2b3c4d,fr11 - - mwcuti fr8,12,fr11 - test_fr_iimmed 0x3456789a,fr11 - - mwcuti fr8,13,fr11 - test_fr_iimmed 0x68acf135,fr11 - - mwcuti fr8,14,fr11 - test_fr_iimmed 0xd159e26a,fr11 - - mwcuti fr8,15,fr11 - test_fr_iimmed 0xa2b3c4d5,fr11 - - mwcuti fr8,16,fr11 - test_fr_iimmed 0x456789ab,fr11 - - mwcuti fr8,17,fr11 - test_fr_iimmed 0x8acf1357,fr11 - - mwcuti fr8,18,fr11 - test_fr_iimmed 0x159e26af,fr11 - - mwcuti fr8,19,fr11 - test_fr_iimmed 0x2b3c4d5e,fr11 - - mwcuti fr8,20,fr11 - test_fr_iimmed 0x56789abc,fr11 - - mwcuti fr8,21,fr11 - test_fr_iimmed 0xacf13579,fr11 - - mwcuti fr8,22,fr11 - test_fr_iimmed 0x59e26af3,fr11 - - mwcuti fr8,23,fr11 - test_fr_iimmed 0xb3c4d5e6,fr11 - - mwcuti fr8,24,fr11 - test_fr_iimmed 0x6789abcd,fr11 - - mwcuti fr8,25,fr11 - test_fr_iimmed 0xcf13579b,fr11 - - mwcuti fr8,26,fr11 - test_fr_iimmed 0x9e26af37,fr11 - - mwcuti fr8,27,fr11 - test_fr_iimmed 0x3c4d5e6f,fr11 - - mwcuti fr8,28,fr11 - test_fr_iimmed 0x789abcde,fr11 - - mwcuti fr8,29,fr11 - test_fr_iimmed 0xf13579bd,fr11 - - mwcuti fr8,30,fr11 - test_fr_iimmed 0xe26af37b,fr11 - - mwcuti fr8,31,fr11 - test_fr_iimmed 0xc4d5e6f7,fr11 - - mwcuti fr8,32,fr11 - test_fr_iimmed 0x89abcdef,fr11 - - mwcuti fr8,33,fr11 - test_fr_iimmed 0x13579bde,fr11 - - mwcuti fr8,34,fr11 - test_fr_iimmed 0x26af37bc,fr11 - - mwcuti fr8,35,fr11 - test_fr_iimmed 0x4d5e6f78,fr11 - - mwcuti fr8,36,fr11 - test_fr_iimmed 0x9abcdef0,fr11 - - mwcuti fr8,37,fr11 - test_fr_iimmed 0x3579bde0,fr11 - - mwcuti fr8,38,fr11 - test_fr_iimmed 0x6af37bc0,fr11 - - mwcuti fr8,39,fr11 - test_fr_iimmed 0xd5e6f780,fr11 - - mwcuti fr8,40,fr11 - test_fr_iimmed 0xabcdef00,fr11 - - mwcuti fr8,41,fr11 - test_fr_iimmed 0x579bde00,fr11 - - mwcuti fr8,42,fr11 - test_fr_iimmed 0xaf37bc00,fr11 - - mwcuti fr8,43,fr11 - test_fr_iimmed 0x5e6f7800,fr11 - - mwcuti fr8,44,fr11 - test_fr_iimmed 0xbcdef000,fr11 - - mwcuti fr8,45,fr11 - test_fr_iimmed 0x79bde000,fr11 - - mwcuti fr8,46,fr11 - test_fr_iimmed 0xf37bc000,fr11 - - mwcuti fr8,47,fr11 - test_fr_iimmed 0xe6f78000,fr11 - - mwcuti fr8,48,fr11 - test_fr_iimmed 0xcdef0000,fr11 - - mwcuti fr8,49,fr11 - test_fr_iimmed 0x9bde0000,fr11 - - mwcuti fr8,50,fr11 - test_fr_iimmed 0x37bc0000,fr11 - - mwcuti fr8,51,fr11 - test_fr_iimmed 0x6f780000,fr11 - - mwcuti fr8,52,fr11 - test_fr_iimmed 0xdef00000,fr11 - - mwcuti fr8,53,fr11 - test_fr_iimmed 0xbde00000,fr11 - - mwcuti fr8,54,fr11 - test_fr_iimmed 0x7bc00000,fr11 - - mwcuti fr8,55,fr11 - test_fr_iimmed 0xf7800000,fr11 - - mwcuti fr8,56,fr11 - test_fr_iimmed 0xef000000,fr11 - - mwcuti fr8,57,fr11 - test_fr_iimmed 0xde000000,fr11 - - mwcuti fr8,58,fr11 - test_fr_iimmed 0xbc000000,fr11 - - mwcuti fr8,59,fr11 - test_fr_iimmed 0x78000000,fr11 - - mwcuti fr8,60,fr11 - test_fr_iimmed 0xf0000000,fr11 - - mwcuti fr8,61,fr11 - test_fr_iimmed 0xe0000000,fr11 - - mwcuti fr8,62,fr11 - test_fr_iimmed 0xc0000000,fr11 - - mwcuti fr8,63,fr11 - test_fr_iimmed 0x80000000,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mwtacc.cgs b/sim/testsuite/sim/frv/mwtacc.cgs deleted file mode 100644 index 20b4d31..0000000 --- a/sim/testsuite/sim/frv/mwtacc.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for mwtacc $FRinti,$ACC40k -# mach: all - - .include "testutils.inc" - - start - - .global mwtacc -mwtacc: - test_accg_immed 0x00,accg0 - test_acc_immed 0x00000000,acc0 - - set_fr_iimmed 0xdead,0xbeef,fr10 - mwtacc fr10,acc0 - test_accg_immed 0x00,accg0 - test_acc_immed 0xdeadbeef,acc0 - - set_fr_iimmed 0x1234,0x5678,fr10 - mwtacc fr10,acc0 - test_accg_immed 0x00,accg0 - test_acc_immed 0x12345678,acc0 - - pass diff --git a/sim/testsuite/sim/frv/mwtaccg.cgs b/sim/testsuite/sim/frv/mwtaccg.cgs deleted file mode 100644 index 6e26bab..0000000 --- a/sim/testsuite/sim/frv/mwtaccg.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for mwtaccg $FRinti,$ACC40k -# mach: all - - .include "testutils.inc" - - start - - .global mwtaccg -mwtaccg: - test_accg_immed 0x00,accg0 - test_acc_immed 0x00000000,acc0 - - set_fr_iimmed 0xdead,0xbeef,fr10 - mwtaccg fr10,accg0 - test_accg_immed 0xef,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x1234,0x5678,fr10 - mwtaccg fr10,accg0 - test_accg_immed 0x78,accg0 - test_acc_immed 0,acc0 - - pass diff --git a/sim/testsuite/sim/frv/mxor.cgs b/sim/testsuite/sim/frv/mxor.cgs deleted file mode 100644 index 6d1cce1..0000000 --- a/sim/testsuite/sim/frv/mxor.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for mxor $FRinti,$FRintj,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mxor -mxor: - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - mxor fr7,fr8,fr8 - test_fr_iimmed 0xffffffff,fr8 - - set_fr_iimmed 0x0000,0x0000,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - mxor fr7,fr8,fr8 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - mxor fr7,fr8,fr8 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - mxor fr7,fr8,fr8 - test_fr_iimmed 0xdeadbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/nandcr.cgs b/sim/testsuite/sim/frv/nandcr.cgs deleted file mode 100644 index 8d3298f..0000000 --- a/sim/testsuite/sim/frv/nandcr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for nandcr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global nandcr -nandcr: - set_spr_immed 0x1b1b,cccr - nandcr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc7,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc7,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc6,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc6,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc5,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc5,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc5,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc5,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc4,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc4,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc4,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - nandcr cc4,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - pass diff --git a/sim/testsuite/sim/frv/nandncr.cgs b/sim/testsuite/sim/frv/nandncr.cgs deleted file mode 100644 index c761c56..0000000 --- a/sim/testsuite/sim/frv/nandncr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for nandncr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global nandncr -nandncr: - set_spr_immed 0x1b1b,cccr - nandncr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc7,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc7,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc6,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc6,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc5,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc5,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc5,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - nandncr cc5,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - nandncr cc4,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc4,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc4,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc4,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/nfadds.cgs b/sim/testsuite/sim/frv/nfadds.cgs deleted file mode 100644 index bdfa1dc..0000000 --- a/sim/testsuite/sim/frv/nfadds.cgs +++ /dev/null @@ -1,179 +0,0 @@ -# frv testcase for nfadds $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfadds -nfadds: - nfadds fr16,fr0,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr4,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr12,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr24,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr32,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr36,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr40,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr44,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr48,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr52,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfadds fr20,fr0,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr4,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr12,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr24,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr32,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr36,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr40,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr44,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr48,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr52,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfadds fr8,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr12,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr24,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr28,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfadds fr36,fr40,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfadds fr48,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfadds fr52,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfadds fr56,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfadds fr60,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 2,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nfdadds.cgs b/sim/testsuite/sim/frv/nfdadds.cgs deleted file mode 100644 index 0be25e7..0000000 --- a/sim/testsuite/sim/frv/nfdadds.cgs +++ /dev/null @@ -1,225 +0,0 @@ -# frv testcase for nfdadds $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdadds -nfdadds: - nfdadds fr16,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdadds fr20,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdadds fr8,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr12,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr24,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr28,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdadds fr36,fr40,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfdadds fr48,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdadds fr52,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdadds fr56,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdadds fr60,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nfdcmps.cgs b/sim/testsuite/sim/frv/nfdcmps.cgs deleted file mode 100644 index 977805a..0000000 --- a/sim/testsuite/sim/frv/nfdcmps.cgs +++ /dev/null @@ -1,1549 +0,0 @@ -# frv testcase for nfdcmps $FRi,$FRj,$FCCi_2 -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdcmps -nfdcmps: - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr0,fr0,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr4,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr8,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr12,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr0,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr0,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr4,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr4,fr4,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr8,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr12,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr4,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr4,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr8,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr8,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr8,fr8,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr12,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr8,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr8,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr12,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr12,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr12,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr12,fr12,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr12,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr12,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr16,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr16,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr16,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr16,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr16,fr16,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr16,fr20,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr16,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr16,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr20,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr20,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr20,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr20,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr20,fr16,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr20,fr20,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr20,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr20,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr24,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr24,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr24,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr24,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr24,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr24,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr24,fr24,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr24,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr24,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr24,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr28,fr28,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr28,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr28,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr28,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr28,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr28,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr28,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr28,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr28,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr24,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr28,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr32,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr36,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr40,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr44,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr48,fr48,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr48,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr48,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr48,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr24,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr28,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr32,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr36,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr40,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr44,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr48,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr52,fr52,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr52,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr52,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr0,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr4,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr8,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr12,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr16,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr20,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr24,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr28,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr32,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr36,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr40,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr44,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr48,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr52,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr0,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr4,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr8,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr12,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr16,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr20,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr24,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr28,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr32,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr36,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr40,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr44,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr48,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr52,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfddivs.cgs b/sim/testsuite/sim/frv/nfddivs.cgs deleted file mode 100644 index 0b16447..0000000 --- a/sim/testsuite/sim/frv/nfddivs.cgs +++ /dev/null @@ -1,306 +0,0 @@ -# frv testcase for nfddivs $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfddivs -nfddivs: - nfddivs fr0,fr28,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr4,fr28,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr12,fr28,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr24,fr28,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr32,fr28,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr36,fr28,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr40,fr28,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr44,fr28,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr48,fr28,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr52,fr28,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfddivs fr16,fr0,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr52,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfddivs fr20,fr0,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr52,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfddivs fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfddivs fr40,fr32,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfddivs fr48,fr20,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfddivs fr52,fr16,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0x0,fner1 - test_spr_immed 0,fner0 - - nfddivs fr56,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfddivs fr60,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nfditos.cgs b/sim/testsuite/sim/frv/nfditos.cgs deleted file mode 100644 index 1200944..0000000 --- a/sim/testsuite/sim/frv/nfditos.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase for nfditos $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfditos -nfditos: - set_fr_iimmed 0,0,fr2 - set_fr_iimmed 0x0000,0x0002,fr3 - nfditos fr2,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr2 - set_fr_iimmed 0xdead,0xbeef,fr3 - nfditos fr2,fr2 - test_fr_iimmed 0xce054904,fr2 - test_fr_iimmed 0xce054904,fr3 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfdivs.cgs b/sim/testsuite/sim/frv/nfdivs.cgs deleted file mode 100644 index 73e58b8..0000000 --- a/sim/testsuite/sim/frv/nfdivs.cgs +++ /dev/null @@ -1,234 +0,0 @@ -# frv testcase for nfdivs $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfdivs -nfdivs: - nfdivs fr0,fr28,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr4,fr28,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr8,fr28,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr12,fr28,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr24,fr28,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr28,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr32,fr28,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr36,fr28,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr40,fr28,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr44,fr28,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr48,fr28,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr52,fr28,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdivs fr16,fr0,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr52,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdivs fr20,fr0,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr52,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdivs fr8,fr28,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr28,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdivs fr40,fr32,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfdivs fr48,fr20,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 2,fner1 - test_spr_immed 0,fner0 - - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfdivs fr52,fr16,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdivs fr56,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdivs fr60,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 2,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nfdmadds.cgs b/sim/testsuite/sim/frv/nfdmadds.cgs deleted file mode 100644 index 1af110c..0000000 --- a/sim/testsuite/sim/frv/nfdmadds.cgs +++ /dev/null @@ -1,310 +0,0 @@ -# frv testcase for nfdmadds $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdmadds -nfdmadds: - nfdmadds fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmadds fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr36,fr2 - set_fr_fr fr36,fr3 - nfdmadds fr28,fr8,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr8,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr36,fr2 - set_fr_fr fr36,fr3 - nfdmadds fr32,fr36,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO -- test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfdmas.cgs b/sim/testsuite/sim/frv/nfdmas.cgs deleted file mode 100644 index 07f76aa..0000000 --- a/sim/testsuite/sim/frv/nfdmas.cgs +++ /dev/null @@ -1,349 +0,0 @@ -# frv testcase for nfdmas $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - load_float_constants2 - load_float_constants3 - - .global nfdmas -nfdmas: - nfdmas fr16,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr4 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr12 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr24 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr36 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr40 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr44 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr48 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmas fr20,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr4 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr12 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr24 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr36 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr40 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr44 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr48 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmas fr28,fr0,fr60 - test_fr_fr fr60,fr0 - test_fr_fr fr62,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr4,fr60 - test_fr_fr fr60,fr4 - test_fr_fr fr62,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr12,fr60 - test_fr_fr fr60,fr12 - test_fr_fr fr62,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr24,fr60 - test_fr_fr fr60,fr24 - test_fr_fr fr62,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr28,fr60 - test_fr_fr fr60,fr28 - test_fr_fr fr62,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr32,fr60 - test_fr_fr fr60,fr32 - test_fr_fr fr61,fr36 - test_fr_fr fr62,fr32 - test_fr_fr fr63,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr36,fr60 - test_fr_fr fr60,fr36 - test_fr_fr fr62,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr40,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr62,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr44,fr60 - test_fr_fr fr60,fr44 - test_fr_fr fr62,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr48,fr60 - test_fr_fr fr60,fr48 - test_fr_fr fr62,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr52,fr60 - test_fr_fr fr60,fr52 - test_fr_fr fr62,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmas fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr8,fr28,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmas fr32,fr36,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr62,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO -- test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfdmss.cgs b/sim/testsuite/sim/frv/nfdmss.cgs deleted file mode 100644 index 3633d70..0000000 --- a/sim/testsuite/sim/frv/nfdmss.cgs +++ /dev/null @@ -1,319 +0,0 @@ -# frv testcase for nfdmss $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - load_float_constants2 - load_float_constants3 - - .global nfdmss -nfdmss: - nfdmss fr16,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmss fr20,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmss fr28,fr0,fr60 - test_fr_fr fr60,fr0 - test_fr_fr fr62,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr4,fr60 - test_fr_fr fr60,fr4 - test_fr_fr fr62,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr12,fr60 - test_fr_fr fr60,fr12 - test_fr_fr fr62,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr24,fr60 - test_fr_fr fr60,fr24 - test_fr_fr fr62,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr28,fr60 - test_fr_fr fr60,fr28 - test_fr_fr fr61,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr62,fr28 - test_fr_fr fr63,fr20 - test_fr_fr fr63,fr16 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr32,fr60 - test_fr_fr fr60,fr32 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr32 - test_fr_fr fr63,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr36,fr60 - test_fr_fr fr60,fr36 - test_fr_fr fr62,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr40,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr62,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr44,fr60 - test_fr_fr fr60,fr44 - test_fr_fr fr62,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr48,fr60 - test_fr_fr fr60,fr48 - test_fr_fr fr62,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr52,fr60 - test_fr_fr fr60,fr52 - test_fr_fr fr62,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmss fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr8,fr28,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr62,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmss fr32,fr36,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr40 - test_fr_fr fr63,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO -- test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfdmulcs.cgs b/sim/testsuite/sim/frv/nfdmulcs.cgs deleted file mode 100644 index 227ff29..0000000 --- a/sim/testsuite/sim/frv/nfdmulcs.cgs +++ /dev/null @@ -1,313 +0,0 @@ -# frv testcase for nfdmulcs $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdmulcs -nfdmulcs: - nfdmulcs fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfdmulcs fr48,fr32,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr52,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr56,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr60,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - ; test all regs different - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - set_fr_fr fr32,fr50 ; 2 - set_fr_fr fr28,fr51 ; 1 - set_fr_fr fr44,fr52 ; 9 - set_fr_fr fr36,fr53 ; 3 - nfdmulcs fr50,fr52,fr54 ; 2*3, 1*9 - test_fr_fr fr54,fr40 ; 6 - test_fr_fr fr55,fr44 ; 9 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfdmuls.cgs b/sim/testsuite/sim/frv/nfdmuls.cgs deleted file mode 100644 index efe1580..0000000 --- a/sim/testsuite/sim/frv/nfdmuls.cgs +++ /dev/null @@ -1,300 +0,0 @@ -# frv testcase for nfdmuls $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdmuls -nfdmuls: - nfdmuls fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfdmuls fr48,fr32,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr52,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr56,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr60,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfdsads.cgs b/sim/testsuite/sim/frv/nfdsads.cgs deleted file mode 100644 index 6c06f16..0000000 --- a/sim/testsuite/sim/frv/nfdsads.cgs +++ /dev/null @@ -1,212 +0,0 @@ -# frv testcase for nfdsads $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdsads -nfdsads: - nfdsads fr16,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr32,fr2 - test_fr_fr fr2,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr36,fr2 - test_fr_fr fr2,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr40,fr2 - test_fr_fr fr2,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr44,fr2 - test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsads fr20,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr32,fr2 - test_fr_fr fr2,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr36,fr2 - test_fr_fr fr2,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr40,fr2 - test_fr_fr fr2,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr44,fr2 - test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsads fr8,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr12,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr24,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr28,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsads fr36,fr40,fr2 - test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - set_fr_fr fr4,fr49 - nfdsads fr48,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr0,fr53 - nfdsads fr52,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsads fr56,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsads fr60,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nfdsqrts.cgs b/sim/testsuite/sim/frv/nfdsqrts.cgs deleted file mode 100644 index 1a906bb..0000000 --- a/sim/testsuite/sim/frv/nfdsqrts.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# frv testcase for nfdsqrts $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfdsqrts -nfdsqrts: - set_fr_iimmed 0x4049,0x0fdb,fr45 ; 3.141592654 - nfdsqrts fr44,fr2 ; 9.0 - test_fr_fr fr2,fr36 ; 3.0 - test_fr_iimmed 0x3fe2dfc5,fr3 ; 1.7724539 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfdstoi.cgs b/sim/testsuite/sim/frv/nfdstoi.cgs deleted file mode 100644 index 56dc941..0000000 --- a/sim/testsuite/sim/frv/nfdstoi.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for nfdstoi $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfdstoi -nfdstoi: - set_fr_fr fr20,fr17 - nfdstoi fr16,fr2 - test_fr_iimmed 0,fr2 - test_fr_iimmed 0,fr3 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0xce05,0x4904,fr2 - set_fr_fr fr32,fr3 - nfdstoi fr2,fr2 - test_fr_iimmed 0xdeadbf00,fr2 - test_fr_iimmed 0x00000002,fr3 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfdsubs.cgs b/sim/testsuite/sim/frv/nfdsubs.cgs deleted file mode 100644 index c981aab..0000000 --- a/sim/testsuite/sim/frv/nfdsubs.cgs +++ /dev/null @@ -1,202 +0,0 @@ -# frv testcase for nfdsubs $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdsubs -nfdsubs: - nfdsubs fr0,fr16,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr4,fr16,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr8,fr16,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr12,fr16,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr24,fr16,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr28,fr16,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr32,fr16,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr36,fr16,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr40,fr16,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr44,fr16,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr48,fr16,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr52,fr16,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsubs fr0,fr20,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr4,fr20,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr8,fr20,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr12,fr20,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr24,fr20,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr28,fr20,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr32,fr20,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr36,fr20,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr40,fr20,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr44,fr20,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr48,fr20,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr52,fr20,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsubs fr32,fr36,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsubs fr44,fr40,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfdsubs fr4,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsubs fr0,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsubs fr56,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsubs fr60,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nfitos.cgs b/sim/testsuite/sim/frv/nfitos.cgs deleted file mode 100644 index 539f7b2..0000000 --- a/sim/testsuite/sim/frv/nfitos.cgs +++ /dev/null @@ -1,44 +0,0 @@ -# frv testcase for nfitos $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfitos -nfitos: - set_fr_iimmed 0,0,fr1 - nfitos fr1,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0x0000,0x0002,fr1 - nfitos fr1,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr1 - nfitos fr1,fr1 - test_fr_iimmed 0xce054904,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; These were an attempt to cause overflow - set_fr_iimmed 0x7fff,0xffff,fr1 - nfitos fr1,fr1 - test_fr_iimmed 0x4f000000,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0x8000,0x0000,fr1 - nfitos fr1,fr1 - test_fr_iimmed 0xcf000000,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfmadds.cgs b/sim/testsuite/sim/frv/nfmadds.cgs deleted file mode 100644 index 2113cd2..0000000 --- a/sim/testsuite/sim/frv/nfmadds.cgs +++ /dev/null @@ -1,227 +0,0 @@ -# frv testcase for nfmadds $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfmadds -nfmadds: - set_fr_fr fr16,fr1 - nfmadds fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmadds fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr16,fr1 - nfmadds fr28,fr0,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr4,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr12,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr24,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr32,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr36,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr40,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr44,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr48,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr52,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr36,fr1 - nfmadds fr28,fr8,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr8,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr36,fr1 - nfmadds fr32,fr36,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfmas.cgs b/sim/testsuite/sim/frv/nfmas.cgs deleted file mode 100644 index b688dbd..0000000 --- a/sim/testsuite/sim/frv/nfmas.cgs +++ /dev/null @@ -1,297 +0,0 @@ -# frv testcase for nfmas $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfmas -nfmas: - nfmas fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfmas fr48,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr52,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr56,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr60,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 6,fner1 - test_spr_immed 0,fner0 - - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfmas fr48,fr32,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr52,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr56,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr60,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 6,fner1 - test_spr_immed 0,fner0 - - pass - diff --git a/sim/testsuite/sim/frv/nfmss.cgs b/sim/testsuite/sim/frv/nfmss.cgs deleted file mode 100644 index bc7c8ef..0000000 --- a/sim/testsuite/sim/frv/nfmss.cgs +++ /dev/null @@ -1,279 +0,0 @@ -# frv testcase for nfmss $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfmss -nfmss: - nfmss fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfmss fr4,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr0,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr56,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr60,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0x6,fner1 - test_spr_immed 0,fner0 - - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfmss fr48,fr32,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr52,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr56,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr60,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0x6,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfmsubs.cgs b/sim/testsuite/sim/frv/nfmsubs.cgs deleted file mode 100644 index 1ae87e3..0000000 --- a/sim/testsuite/sim/frv/nfmsubs.cgs +++ /dev/null @@ -1,227 +0,0 @@ -# frv testcase for nfmsubs $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfmsubs -nfmsubs: - set_fr_fr fr16,fr1 - nfmsubs fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmsubs fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr16,fr1 - nfmsubs fr28,fr0,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr4,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr12,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr24,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr32,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr36,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr40,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr44,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr48,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr52,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr32,fr1 - nfmsubs fr8,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr36,fr1 - nfmsubs fr36,fr36,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmsubs fr32,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO test cases to set ne flags - pass diff --git a/sim/testsuite/sim/frv/nfmuls.cgs b/sim/testsuite/sim/frv/nfmuls.cgs deleted file mode 100644 index e4b0d2e..0000000 --- a/sim/testsuite/sim/frv/nfmuls.cgs +++ /dev/null @@ -1,228 +0,0 @@ -# frv testcase for nfmuls $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfmuls -nfmuls: - nfmuls fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr28,fr0,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr4,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr12,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr24,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr32,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr36,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr40,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr44,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr48,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr52,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr28,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr8,fr28,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr32,fr36,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfmuls fr48,fr32,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr52,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr56,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr60,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 2,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfsqrts.cgs b/sim/testsuite/sim/frv/nfsqrts.cgs deleted file mode 100644 index 8ada77a..0000000 --- a/sim/testsuite/sim/frv/nfsqrts.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# frv testcase for nfsqrts $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfsqrts -nfsqrts: - nfsqrts fr44,fr1 ; 9.0 - test_fr_fr fr1,fr36 ; 3.0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - nfsqrts fr10,fr10 - test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; fp_exceptions - nfsqrts fr8,fr1 ; -1 -- invalid - test_fr_iimmed 0x7fc00000,fr1 ; nan1 - test_spr_immed 2,fner1 - test_spr_immed 0,fner0 - test_spr_bits 0x80000000,31,0x0,fqst0 ; fq0.miv is clear - test_spr_bits 0x18000,15,0x0,fqst0 ; fq0.sie is clear - test_spr_bits 0x380,7,0x0,fqst0 ; fq0.ftt is clear - test_spr_bits 0x7e,1,0x0,fqst0 ; fq0.cexc is clear - test_spr_bits 0x1,0,0x0,fqst0 ; fq0.valid is clear - test_spr_immed 0,fqop0 ; fq0.opc - - pass diff --git a/sim/testsuite/sim/frv/nfstoi.cgs b/sim/testsuite/sim/frv/nfstoi.cgs deleted file mode 100644 index 2968128..0000000 --- a/sim/testsuite/sim/frv/nfstoi.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for nfstoi $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfstoi -nfstoi: - nfstoi fr16,fr1 - test_fr_iimmed 0,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfstoi fr20,fr1 - test_fr_iimmed 0,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfstoi fr32,fr1 - test_fr_iimmed 0x00000002,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0xce05,0x4904,fr1 - nfstoi fr1,fr1 - test_fr_iimmed 0xdeadbf00,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; These were an attempt to cause overflow and nan exceptions - nfstoi fr48,fr1 - test_fr_iimmed 0x7fffffff,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfstoi fr52,fr1 - test_fr_iimmed 0x7fffffff,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfstoi fr56,fr1 - test_fr_iimmed 0x80000000,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfsubs.cgs b/sim/testsuite/sim/frv/nfsubs.cgs deleted file mode 100644 index 3da08b9..0000000 --- a/sim/testsuite/sim/frv/nfsubs.cgs +++ /dev/null @@ -1,163 +0,0 @@ -# frv testcase for nfsubs $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfsubs -nfsubs: - nfsubs fr0,fr16,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr4,fr16,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr8,fr16,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr12,fr16,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr24,fr16,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr28,fr16,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr32,fr16,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr36,fr16,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr40,fr16,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr44,fr16,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr48,fr16,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr52,fr16,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfsubs fr0,fr20,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr4,fr20,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr8,fr20,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr12,fr20,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr24,fr20,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr28,fr20,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr32,fr20,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr36,fr20,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr40,fr20,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr44,fr20,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr48,fr20,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr52,fr20,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfsubs fr32,fr36,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfsubs fr44,fr40,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfsubs fr4,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfsubs fr0,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfsubs fr56,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfsubs fr60,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 2,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nld.cgs b/sim/testsuite/sim/frv/nld.cgs deleted file mode 100644 index 297468b..0000000 --- a/sim/testsuite/sim/frv/nld.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for nld @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nld -nld: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nld @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0x8880,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - nld @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0x8880,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - nld @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0x8880,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldbf.cgs b/sim/testsuite/sim/frv/nldbf.cgs deleted file mode 100644 index 1a5c25b..0000000 --- a/sim/testsuite/sim/frv/nldbf.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for nldbf @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldbf -nldbf: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldbf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00de,fr8 - test_spr_limmed 0xc800,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - nldbf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00ad,fr8 - test_spr_limmed 0xc800,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 2,gr20 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - nldbf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_spr_limmed 0xc800,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldbfi.cgs b/sim/testsuite/sim/frv/nldbfi.cgs deleted file mode 100644 index aa90bc9..0000000 --- a/sim/testsuite/sim/frv/nldbfi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for nldbfi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldbfi -nldbfi: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_gr sp,gr20 - nldbfi @(sp,0),fr8 - test_fr_limmed 0x0000,0x00de,fr8 - test_spr_limmed 0xc800,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 1,gr20 - nldbfi @(sp,1),fr8 - test_fr_limmed 0x0000,0x00ad,fr8 - test_spr_limmed 0xc800,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 2,gr20 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - nldbfi @(sp,-1),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_spr_limmed 0xc800,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldbfu.cgs b/sim/testsuite/sim/frv/nldbfu.cgs deleted file mode 100644 index 174042b..0000000 --- a/sim/testsuite/sim/frv/nldbfu.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# frv testcase for nldbfu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldbfu -nldbfu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - nldbfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00de,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc800,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - nldbfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00ad,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc800,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 2,gr20 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - nldbfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc800,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldd.cgs b/sim/testsuite/sim/frv/nldd.cgs deleted file mode 100644 index 1f45761..0000000 --- a/sim/testsuite/sim/frv/nldd.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for nldd @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldd -nldd: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldd @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - nldd @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - nldd @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nlddf.cgs b/sim/testsuite/sim/frv/nlddf.cgs deleted file mode 100644 index d30b6dd..0000000 --- a/sim/testsuite/sim/frv/nlddf.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for nlddf @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlddf -nlddf: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nlddf @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_spr_limmed 0xc8a0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - nlddf @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_spr_limmed 0xc8a0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - nlddf @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_spr_limmed 0xc8a0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nlddfi.cgs b/sim/testsuite/sim/frv/nlddfi.cgs deleted file mode 100644 index b58ad6f..0000000 --- a/sim/testsuite/sim/frv/nlddfi.cgs +++ /dev/null @@ -1,47 +0,0 @@ -# frv testcase for nlddfi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlddfi -nlddfi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_gr sp,gr20 - nlddfi @(sp,0),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_spr_limmed 0xc8a0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - nlddfi @(sp,8),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_spr_limmed 0xc8a0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - nlddfi @(sp,-8),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_spr_limmed 0xc8a0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nlddfu.cgs b/sim/testsuite/sim/frv/nlddfu.cgs deleted file mode 100644 index d45c995..0000000 --- a/sim/testsuite/sim/frv/nlddfu.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for nlddfu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlddfu -nlddfu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - nlddfu @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - test_spr_limmed 0xc8a0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - nlddfu @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - test_spr_limmed 0xc8a0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - nlddfu @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - test_spr_limmed 0xc8a0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nlddi.cgs b/sim/testsuite/sim/frv/nlddi.cgs deleted file mode 100644 index 04d2487..0000000 --- a/sim/testsuite/sim/frv/nlddi.cgs +++ /dev/null @@ -1,47 +0,0 @@ -# frv testcase for nlddi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlddi -nlddi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_gr sp,gr20 - nlddi @(sp,0),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - nlddi @(sp,8),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - nlddi @(sp,-8),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nlddu.cgs b/sim/testsuite/sim/frv/nlddu.cgs deleted file mode 100644 index 44565c8..0000000 --- a/sim/testsuite/sim/frv/nlddu.cgs +++ /dev/null @@ -1,66 +0,0 @@ -# frv testcase for nlddu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlddu -nlddu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - nlddu @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - test_spr_limmed 0x88a0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - nlddu @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - test_spr_limmed 0x88a0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - nlddu @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - test_spr_limmed 0x88a0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - set_gr_gr sp,gr8 - nlddu @(gr8,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0c01,nesr3 - test_spr_gr neear3,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldf.cgs b/sim/testsuite/sim/frv/nldf.cgs deleted file mode 100644 index 6aabc67..0000000 --- a/sim/testsuite/sim/frv/nldf.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for nldf @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldf -nldf: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldf @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_spr_limmed 0xc880,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - nldf @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_spr_limmed 0xc880,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - nldf @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_spr_limmed 0xc880,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldfi.cgs b/sim/testsuite/sim/frv/nldfi.cgs deleted file mode 100644 index 20f62df..0000000 --- a/sim/testsuite/sim/frv/nldfi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for nldfi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldfi -nldfi: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_gr sp,gr20 - nldfi @(sp,0),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_spr_limmed 0xc880,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - nldfi @(sp,4),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_spr_limmed 0xc880,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - nldfi @(sp,-4),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_spr_limmed 0xc880,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldfu.cgs b/sim/testsuite/sim/frv/nldfu.cgs deleted file mode 100644 index 8e95016..0000000 --- a/sim/testsuite/sim/frv/nldfu.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for nldfu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldfu -nldfu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - nldfu @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc880,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - nldfu @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc880,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - nldfu @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc880,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldhf.cgs b/sim/testsuite/sim/frv/nldhf.cgs deleted file mode 100644 index b90d8f9..0000000 --- a/sim/testsuite/sim/frv/nldhf.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# frv testcase for nldhf @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldhf -nldhf: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldhf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xdead,fr8 - test_spr_limmed 0xc840,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - nldhf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xbeef,fr8 - test_spr_limmed 0xc840,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - nldhf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_spr_limmed 0xc840,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldhfi.cgs b/sim/testsuite/sim/frv/nldhfi.cgs deleted file mode 100644 index bcd52ed..0000000 --- a/sim/testsuite/sim/frv/nldhfi.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for nldhfi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldhfi -nldhfi: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_gr sp,gr20 - nldhfi @(sp,0),fr8 - test_fr_limmed 0x0000,0xdead,fr8 - test_spr_limmed 0xc840,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 2,gr20 - nldhfi @(sp,2),fr8 - test_fr_limmed 0x0000,0xbeef,fr8 - test_spr_limmed 0xc840,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - nldhfi @(sp,-2),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_spr_limmed 0xc840,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldhfu.cgs b/sim/testsuite/sim/frv/nldhfu.cgs deleted file mode 100644 index 97d1dd9..0000000 --- a/sim/testsuite/sim/frv/nldhfu.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for nldhfu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldhfu -nldhfu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - nldhfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xdead,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc840,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - nldhfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xbeef,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc840,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - nldhfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc840,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldi.cgs b/sim/testsuite/sim/frv/nldi.cgs deleted file mode 100644 index c70f0cb..0000000 --- a/sim/testsuite/sim/frv/nldi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for nldi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldi -nldi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - nldi @(sp,0),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0x8880,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - nldi @(sp,4),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0x8880,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - nldi @(sp,-4),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0x8880,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldq.cgs b/sim/testsuite/sim/frv/nldq.cgs deleted file mode 100644 index 0338e19..0000000 --- a/sim/testsuite/sim/frv/nldq.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# frv testcase for nldq @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global nldq -nldq: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldq @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_spr_limmed 0x88c0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - nldq @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_spr_limmed 0x88c0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - nldq @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_spr_limmed 0x88c0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldqf.cgs b/sim/testsuite/sim/frv/nldqf.cgs deleted file mode 100644 index 8e268ac..0000000 --- a/sim/testsuite/sim/frv/nldqf.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# frv testcase for nldqf @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global nldqf -nldqf: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldqf @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_spr_limmed 0xc8c0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - nldqf @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_spr_limmed 0xc8c0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - nldqf @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_spr_limmed 0xc8c0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldqfi.cgs b/sim/testsuite/sim/frv/nldqfi.cgs deleted file mode 100644 index ff05fae..0000000 --- a/sim/testsuite/sim/frv/nldqfi.cgs +++ /dev/null @@ -1,64 +0,0 @@ -# frv testcase for nldqfi @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global nldqfi -nldqfi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - - set_gr_gr sp,gr20 - nldqfi @(sp,0),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_spr_limmed 0xc8c0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed -16,sp - nldqfi @(sp,16),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_spr_limmed 0xc8c0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed 32,sp - nldqfi @(sp,-16),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_spr_limmed 0xc8c0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldqfu.cgs b/sim/testsuite/sim/frv/nldqfu.cgs deleted file mode 100644 index ffe2990..0000000 --- a/sim/testsuite/sim/frv/nldqfu.cgs +++ /dev/null @@ -1,70 +0,0 @@ -# frv testcase for nldqfu @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global nldqfu -nldqfu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - - set_gr_immed 0,gr7 - nldqfu @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_gr_gr sp,gr20 - test_spr_limmed 0xc8c0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - nldqfu @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_gr_gr sp,gr20 - test_spr_limmed 0xc8c0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - nldqfu @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_gr_gr sp,gr20 - test_spr_limmed 0xc8c0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldqu.cgs b/sim/testsuite/sim/frv/nldqu.cgs deleted file mode 100644 index a7e8b30..0000000 --- a/sim/testsuite/sim/frv/nldqu.cgs +++ /dev/null @@ -1,87 +0,0 @@ -# frv testcase for nldqu @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global nldqu -nldqu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - nldqu @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - test_spr_limmed 0x88c0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - nldqu @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - test_spr_limmed 0x88c0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - nldqu @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - test_spr_limmed 0x88c0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - set_gr_gr sp,gr8 - nldqu @(gr8,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_spr_limmed 0x88c0,0x0c01,nesr3 - test_spr_gr neear3,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldsb.cgs b/sim/testsuite/sim/frv/nldsb.cgs deleted file mode 100644 index 1db547c..0000000 --- a/sim/testsuite/sim/frv/nldsb.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for nldsb @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldsb -nldsb: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldsb @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffde,gr8 - test_spr_limmed 0x8820,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - nldsb @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffad,gr8 - test_spr_limmed 0x8820,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - nldsb @(sp,gr7),gr8 - test_gr_immed 0,gr8 - test_spr_limmed 0x8820,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldsbi.cgs b/sim/testsuite/sim/frv/nldsbi.cgs deleted file mode 100644 index 4b9dcba..0000000 --- a/sim/testsuite/sim/frv/nldsbi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for nldsbi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldsbi -nldsbi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - nldsbi @(sp,0),gr8 - test_gr_limmed 0xffff,0xffde,gr8 - test_spr_limmed 0x8820,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 1,gr20 - nldsbi @(sp,1),gr8 - test_gr_limmed 0xffff,0xffad,gr8 - test_spr_limmed 0x8820,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - nldsbi @(sp,-1),gr8 - test_gr_immed 0,gr8 - test_spr_limmed 0x8820,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldsbu.cgs b/sim/testsuite/sim/frv/nldsbu.cgs deleted file mode 100644 index e60ffc0..0000000 --- a/sim/testsuite/sim/frv/nldsbu.cgs +++ /dev/null @@ -1,56 +0,0 @@ -# frv testcase for nldsbu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldsbu -nldsbu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - nldsbu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffde,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8820,0x0001,nesr0 - test_spr_gr neear0,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - nldsbu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffad,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8820,0x0401,nesr1 - test_spr_gr neear1,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - nldsbu @(sp,gr7),gr8 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8820,0x0801,nesr2 - test_spr_gr neear2,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed -3,sp - set_mem_limmed 0x0000,0x00da,sp - set_gr_immed 3,gr7 - nldsbu @(sp,gr7),sp - test_gr_limmed 0xffff,0xffda,sp - test_spr_limmed 0x8120,0x0c01,nesr3 - test_spr_gr neear3,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldsh.cgs b/sim/testsuite/sim/frv/nldsh.cgs deleted file mode 100644 index afc00c4..0000000 --- a/sim/testsuite/sim/frv/nldsh.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# frv testcase for nldsh @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldsh -nldsh: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldsh @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xdead,gr8 - test_spr_limmed 0x8860,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - nldsh @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xbeef,gr8 - test_spr_limmed 0x8860,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - nldsh @(sp,gr7),gr8 - test_gr_immed 0,gr8 - test_spr_limmed 0x8860,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldshi.cgs b/sim/testsuite/sim/frv/nldshi.cgs deleted file mode 100644 index 60de156..0000000 --- a/sim/testsuite/sim/frv/nldshi.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for nldshi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldshi -nldshi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - nldshi @(sp,0),gr8 - test_gr_limmed 0xffff,0xdead,gr8 - test_spr_limmed 0x8860,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - nldshi @(sp,2),gr8 - test_gr_limmed 0xffff,0xbeef,gr8 - test_spr_limmed 0x8860,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - nldshi @(sp,-2),gr8 - test_gr_immed 0,gr8 - test_spr_limmed 0x8860,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldshu.cgs b/sim/testsuite/sim/frv/nldshu.cgs deleted file mode 100644 index 775b760..0000000 --- a/sim/testsuite/sim/frv/nldshu.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for nldshu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldshu -nldshu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - nldshu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xdead,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8860,0x0001,nesr0 - test_spr_gr neear0,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - nldshu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xbeef,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8860,0x0401,nesr1 - test_spr_gr neear1,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - nldshu @(sp,gr7),gr8 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8860,0x0801,nesr2 - test_spr_gr neear2,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed -2,sp - set_mem_limmed 0x0000,0xdead,sp - set_gr_immed 2,gr7 - nldshu @(sp,gr7),sp - test_gr_limmed 0xffff,0xdead,sp - test_spr_limmed 0x8160,0x0c01,nesr3 - test_spr_gr neear3,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldu.cgs b/sim/testsuite/sim/frv/nldu.cgs deleted file mode 100644 index 0d1735e..0000000 --- a/sim/testsuite/sim/frv/nldu.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for nldu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldu -nldu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - nldu @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8880,0x0001,nesr0 - test_spr_gr neear0,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - nldu @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8880,0x0401,nesr1 - test_spr_gr neear1,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - nldu @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8880,0x0801,nesr2 - test_spr_gr neear2,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - nldu @(sp,gr7),sp - test_gr_limmed 0xdead,0xbeef,sp - test_spr_limmed 0x8180,0x0c01,nesr3 - test_spr_gr neear3,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldub.cgs b/sim/testsuite/sim/frv/nldub.cgs deleted file mode 100644 index 2067bcc..0000000 --- a/sim/testsuite/sim/frv/nldub.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for nldub @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldub -nldub: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldub @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00de,gr8 - test_spr_limmed 0x8800,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - nldub @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00ad,gr8 - test_spr_limmed 0x8800,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - nldub @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_spr_limmed 0x8800,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldubi.cgs b/sim/testsuite/sim/frv/nldubi.cgs deleted file mode 100644 index 8eba516..0000000 --- a/sim/testsuite/sim/frv/nldubi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for nldubi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldubi -nldubi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - nldubi @(sp,0),gr8 - test_gr_limmed 0x0000,0x00de,gr8 - test_spr_limmed 0x8800,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 1,gr20 - nldubi @(sp,1),gr8 - test_gr_limmed 0x0000,0x00ad,gr8 - test_spr_limmed 0x8800,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - nldubi @(sp,-1),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_spr_limmed 0x8800,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldubu.cgs b/sim/testsuite/sim/frv/nldubu.cgs deleted file mode 100644 index acf9d9c..0000000 --- a/sim/testsuite/sim/frv/nldubu.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for nldubu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldubu -nldubu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - nldubu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00de,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8800,0x0001,nesr0 - test_spr_gr neear0,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - nldubu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00ad,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8800,0x0401,nesr1 - test_spr_gr neear1,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - nldubu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_spr_limmed 0x8800,0x0801,nesr2 - test_spr_gr neear2,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed -3,sp - set_mem_limmed 0xffff,0xffda,sp - set_gr_immed 3,gr7 - nldubu @(sp,gr7),sp - test_gr_limmed 0x0000,0x00da,sp - test_spr_limmed 0x8100,0x0c01,nesr3 - test_spr_gr neear3,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nlduh.cgs b/sim/testsuite/sim/frv/nlduh.cgs deleted file mode 100644 index 1871a22..0000000 --- a/sim/testsuite/sim/frv/nlduh.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# frv testcase for nlduh @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlduh -nlduh: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nlduh @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xdead,gr8 - test_spr_limmed 0x8840,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - nlduh @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xbeef,gr8 - test_spr_limmed 0x8840,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - nlduh @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_spr_limmed 0x8840,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nlduhi.cgs b/sim/testsuite/sim/frv/nlduhi.cgs deleted file mode 100644 index ae7171e..0000000 --- a/sim/testsuite/sim/frv/nlduhi.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for nlduhi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlduhi -nlduhi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - nlduhi @(sp,0),gr8 - test_gr_limmed 0x0000,0xdead,gr8 - test_spr_limmed 0x8840,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - nlduhi @(sp,2),gr8 - test_gr_limmed 0x0000,0xbeef,gr8 - test_spr_limmed 0x8840,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - nlduhi @(sp,-2),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_spr_limmed 0x8840,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nlduhu.cgs b/sim/testsuite/sim/frv/nlduhu.cgs deleted file mode 100644 index 8142fc5..0000000 --- a/sim/testsuite/sim/frv/nlduhu.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for nlduhu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlduhu -nlduhu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - nlduhu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xdead,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8840,0x0001,nesr0 - test_spr_gr neear0,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - nlduhu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xbeef,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8840,0x0401,nesr1 - test_spr_gr neear1,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - nlduhu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8840,0x0801,nesr2 - test_spr_gr neear2,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0xdead,sp - set_gr_immed 2,gr7 - nlduhu @(sp,gr7),sp - test_gr_limmed 0x0000,0xdead,sp - test_spr_limmed 0x8140,0x0c01,nesr3 - test_spr_gr neear3,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nop.cgs b/sim/testsuite/sim/frv/nop.cgs deleted file mode 100644 index 7180066..0000000 --- a/sim/testsuite/sim/frv/nop.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# frv testcase for nop -# mach: all - - .include "testutils.inc" - - start - - .global nop -nop: - nop - - pass diff --git a/sim/testsuite/sim/frv/norcr.cgs b/sim/testsuite/sim/frv/norcr.cgs deleted file mode 100644 index e097a1b..0000000 --- a/sim/testsuite/sim/frv/norcr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for norcr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global norcr -norcr: - set_spr_immed 0x1b1b,cccr - norcr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - norcr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - norcr cc7,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - norcr cc7,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - norcr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - norcr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - norcr cc6,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - norcr cc6,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - norcr cc5,cc7,cc3 - test_spr_immed 0x1bdb,cccr - - norcr cc5,cc6,cc3 - test_spr_immed 0x1bdb,cccr - - norcr cc5,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - norcr cc5,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - norcr cc4,cc7,cc3 - test_spr_immed 0x1b9b,cccr - - norcr cc4,cc6,cc3 - test_spr_immed 0x1b9b,cccr - - norcr cc4,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - norcr cc4,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - pass diff --git a/sim/testsuite/sim/frv/norncr.cgs b/sim/testsuite/sim/frv/norncr.cgs deleted file mode 100644 index a7b95da..0000000 --- a/sim/testsuite/sim/frv/norncr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for norncr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global norncr -norncr: - set_spr_immed 0x1b1b,cccr - norncr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - norncr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - norncr cc7,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - norncr cc7,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - norncr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - norncr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - norncr cc6,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - norncr cc6,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - norncr cc5,cc7,cc3 - test_spr_immed 0x1b9b,cccr - - norncr cc5,cc6,cc3 - test_spr_immed 0x1b9b,cccr - - norncr cc5,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - norncr cc5,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - norncr cc4,cc7,cc3 - test_spr_immed 0x1bdb,cccr - - norncr cc4,cc6,cc3 - test_spr_immed 0x1bdb,cccr - - norncr cc4,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - norncr cc4,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - pass diff --git a/sim/testsuite/sim/frv/not.cgs b/sim/testsuite/sim/frv/not.cgs deleted file mode 100644 index e44eabf..0000000 --- a/sim/testsuite/sim/frv/not.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for not $GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global not -not: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - not gr7,gr7 - test_gr_limmed 0x5555,0x5555,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - not gr7,gr7 - test_gr_limmed 0x2152,0x4110,gr7 - - pass diff --git a/sim/testsuite/sim/frv/notcr.cgs b/sim/testsuite/sim/frv/notcr.cgs deleted file mode 100644 index e6c08e0..0000000 --- a/sim/testsuite/sim/frv/notcr.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for notcr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global notcr -notcr: - set_spr_immed 0x1b1b,cccr - notcr cc7,cc3 - test_spr_immed 0x1b5b,cccr - - notcr cc6,cc3 - test_spr_immed 0x1b1b,cccr - - notcr cc5,cc3 - test_spr_immed 0x1bdb,cccr - - notcr cc4,cc3 - test_spr_immed 0x1b9b,cccr - - pass diff --git a/sim/testsuite/sim/frv/nsdiv.cgs b/sim/testsuite/sim/frv/nsdiv.cgs deleted file mode 100644 index 533f2ef..0000000 --- a/sim/testsuite/sim/frv/nsdiv.cgs +++ /dev/null @@ -1,64 +0,0 @@ -# frv testcase for nsdiv $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global nsdiv -nsdiv: - set_spr_immed 0,gner0 - set_spr_immed 0,gner1 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - nsdiv gr1,gr3,gr2 - test_gr_immed 4,gr2 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - nsdiv gr1,gr3,gr2 - test_gr_immed -1,gr2 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - set_spr_immed 4,gner1 ; turn on NE bit for gr2 - nsdiv gr1,gr3,gr2 ; overflow is masked - test_gr_limmed 0x7fff,0xffff,gr2 - test_spr_bits 0x4,2,1,isr ; isr.aexc is set - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - nsdiv gr1,gr0,gr32 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0,gner1 - - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - nsdiv gr1,gr3,gr2 - test_gr_limmed 0x8000,0x0000,gr2 - test_spr_immed 1,gner0 - test_spr_immed 4,gner1 - - nsdiv gr1,gr0,gr10 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0x00000404,gner1 - - ; simple division 12 / 3 -- should turn off ne flag - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - nsdiv gr1,gr3,gr2 - test_gr_immed 4,gr2 - test_spr_immed 1,gner0 - test_spr_immed 0x00000400,gner1 - - pass diff --git a/sim/testsuite/sim/frv/nsdivi.cgs b/sim/testsuite/sim/frv/nsdivi.cgs deleted file mode 100644 index 014fadd..0000000 --- a/sim/testsuite/sim/frv/nsdivi.cgs +++ /dev/null @@ -1,64 +0,0 @@ -# frv testcase for nsdivi $GRi,$s12,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global nsdivi -nsdivi: - set_spr_immed 0,gner0 - set_spr_immed 0,gner1 - - ; simple division 12 / 3 - set_gr_immed 12,gr1 - nsdivi gr1,3,gr2 - test_gr_immed 4,gr2 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; Random example - set_gr_limmed 0xfedc,0xba98,gr1 - nsdivi gr1,0x7ff,gr2 - test_gr_limmed 0xffff,0xdb93,gr2 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; Random negative example - set_gr_limmed 0xfedc,0xba98,gr1 - nsdivi gr1,-2048,gr2 - test_gr_immed 0x2468,gr2 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_limmed 0x8000,0x0000,gr1 - nsdivi gr1,-1,gr2 - test_gr_limmed 0x7fff,0xffff,gr2 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - nsdivi gr1,0,gr32 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0,gner1 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_limmed 0x8000,0x0000,gr1 - nsdivi gr1,-1,gr2 - test_gr_limmed 0x8000,0x0000,gr2 - test_spr_immed 1,gner0 - test_spr_immed 4,gner1 - - nsdivi gr1,0,gr10 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0x00000404,gner1 - - ; simple division 12 / 3 -- should turn off ne flag - set_gr_immed 12,gr1 - nsdivi gr1,3,gr2 - test_gr_immed 4,gr2 - test_spr_immed 1,gner0 - test_spr_immed 0x00000400,gner1 - - pass diff --git a/sim/testsuite/sim/frv/nudiv.cgs b/sim/testsuite/sim/frv/nudiv.cgs deleted file mode 100644 index 58bce82..0000000 --- a/sim/testsuite/sim/frv/nudiv.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for nudiv $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global nudiv -nudiv: - set_spr_immed 0,gner0 - set_spr_immed 0,gner1 - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - nudiv gr3,gr2,gr3 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x00000004,gr3 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; example 1 from the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - nudiv gr3,gr2,gr3 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_immed 0x000000e0,gr3 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - or_spr_immed 0x20,isr ; turn on isr.edem - nudiv gr1,gr0,gr32 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0,gner1 - - and_spr_immed -33,isr ; turn off isr.edem - nudiv gr1,gr0,gr10 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0x00000400,gner1 - - ; simple division 12 / 3 -- should turn off ne flag - set_gr_immed 12,gr1 - set_gr_immed 3,gr3 - nudiv gr1,gr3,gr10 - test_gr_immed 4,gr10 - test_spr_immed 1,gner0 - test_spr_immed 0,gner1 - - pass diff --git a/sim/testsuite/sim/frv/nudivi.cgs b/sim/testsuite/sim/frv/nudivi.cgs deleted file mode 100644 index 2426eb3..0000000 --- a/sim/testsuite/sim/frv/nudivi.cgs +++ /dev/null @@ -1,51 +0,0 @@ -# frv testcase for nudivi $GRi,$s12,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global nudivi -nudivi: - set_spr_immed 0,gner0 - set_spr_immed 0,gner1 - - ; simple division 12 / 3 - set_gr_immed 0x0000000c,gr3 - nudivi gr3,3,gr3 - test_gr_immed 0x00000004,gr3 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; random example - set_gr_limmed 0xfedc,0xba98,gr3 - nudivi gr3,0x7ff,gr3 - test_gr_limmed 0x001f,0xdf93,gr3 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; random example - set_gr_limmed 0xffff,0xffff,gr3 - nudivi gr3,-2048,gr3 - test_gr_immed 1,gr3 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - or_spr_immed 0x20,isr ; turn on isr.edem - nudivi gr1,0,gr32 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0,gner1 - - and_spr_immed -33,isr ; turn off isr.edem - nudivi gr1,0,gr10 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0x00000400,gner1 - - ; simple division 12 / 3 -- should turn off ne flag - set_gr_immed 12,gr1 - nudivi gr1,3,gr10 - test_gr_immed 4,gr10 - test_spr_immed 1,gner0 - test_spr_immed 0,gner1 - - pass diff --git a/sim/testsuite/sim/frv/or.cgs b/sim/testsuite/sim/frv/or.cgs deleted file mode 100644 index b432429..0000000 --- a/sim/testsuite/sim/frv/or.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase for or $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global or -or: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - or gr7,gr8,gr8 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - or gr7,gr8,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - or gr7,gr8,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/orcc.cgs b/sim/testsuite/sim/frv/orcc.cgs deleted file mode 100644 index a0a3e5b..0000000 --- a/sim/testsuite/sim/frv/orcc.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase for orcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global orcc -orcc: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - orcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - orcc gr7,gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - orcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/orcr.cgs b/sim/testsuite/sim/frv/orcr.cgs deleted file mode 100644 index a5114b2..0000000 --- a/sim/testsuite/sim/frv/orcr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for orcr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global orcr -orcr: - set_spr_immed 0x1b1b,cccr - orcr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - orcr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - orcr cc7,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - orcr cc7,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - orcr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - orcr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - orcr cc6,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - orcr cc6,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - orcr cc5,cc7,cc3 - test_spr_immed 0x1b9b,cccr - - orcr cc5,cc6,cc3 - test_spr_immed 0x1b9b,cccr - - orcr cc5,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - orcr cc5,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - orcr cc4,cc7,cc3 - test_spr_immed 0x1bdb,cccr - - orcr cc4,cc6,cc3 - test_spr_immed 0x1bdb,cccr - - orcr cc4,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - orcr cc4,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/ori.cgs b/sim/testsuite/sim/frv/ori.cgs deleted file mode 100644 index aa1d61a..0000000 --- a/sim/testsuite/sim/frv/ori.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for ori $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ori -ori: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x07,0 ; Set mask opposite of expected - ori gr7,0x555,gr8 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xaaaa,0xafff,gr8 - - set_gr_immed 0x00000000,gr7 - set_icc 0x08,0 ; Set mask opposite of expected - ori gr7,0,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xb800,gr7 - set_icc 0x05,0 ; Set mask opposite of expected - ori gr7,0x6ef,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xdead,0xb000,gr7 - set_icc 0x05,0 ; Set mask opposite of expected - ori gr7,-273,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xffff,0xfeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/oricc.cgs b/sim/testsuite/sim/frv/oricc.cgs deleted file mode 100644 index 71e6d53..0000000 --- a/sim/testsuite/sim/frv/oricc.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for oricc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global oricc -oricc: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x07,0 ; Set mask opposite of expected - oricc gr7,0x155,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xaaaa,0xabff,gr8 - - set_gr_immed 0x00000000,gr7 - set_icc 0x08,0 ; Set mask opposite of expected - oricc gr7,0,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbe00,gr7 - set_icc 0x05,0 ; Set mask opposite of expected - oricc gr7,0x0ef,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xdead,0xb000,gr7 - set_icc 0x05,0 ; Set mask opposite of expected - oricc gr7,-273,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xfeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/orncr.cgs b/sim/testsuite/sim/frv/orncr.cgs deleted file mode 100644 index b0e4e59..0000000 --- a/sim/testsuite/sim/frv/orncr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for orncr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global orncr -orncr: - set_spr_immed 0x1b1b,cccr - orncr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - orncr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - orncr cc7,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - orncr cc7,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - orncr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - orncr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - orncr cc6,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - orncr cc6,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - orncr cc5,cc7,cc3 - test_spr_immed 0x1bdb,cccr - - orncr cc5,cc6,cc3 - test_spr_immed 0x1bdb,cccr - - orncr cc5,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - orncr cc5,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - orncr cc4,cc7,cc3 - test_spr_immed 0x1b9b,cccr - - orncr cc4,cc6,cc3 - test_spr_immed 0x1b9b,cccr - - orncr cc4,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - orncr cc4,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/parallel.exp b/sim/testsuite/sim/frv/parallel.exp deleted file mode 100644 index 8101a67a..0000000 --- a/sim/testsuite/sim/frv/parallel.exp +++ /dev/null @@ -1,19 +0,0 @@ -# FRV simulator testsuite. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "frv fr500 fr550 fr400" - set cpu_option -mcpu - - # The .pcgs suffix is for "parallel cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.pcgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/ret.cgs b/sim/testsuite/sim/frv/ret.cgs deleted file mode 100644 index 1447998..0000000 --- a/sim/testsuite/sim/frv/ret.cgs +++ /dev/null @@ -1,91 +0,0 @@ -# frv testcase for ret -# mach: all - - .include "testutils.inc" - - start - - .global ret -ret: - set_spr_addr ok1,lr - set_icc 0x0 0 - ret - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - ret - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - ret - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - ret - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - ret - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - ret - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - ret - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - ret - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - ret - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - ret - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - ret - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - ret - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - ret - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - ret - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - ret - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - ret - fail -okg: - - pass diff --git a/sim/testsuite/sim/frv/rett.cgs b/sim/testsuite/sim/frv/rett.cgs deleted file mode 100644 index f964bae..0000000 --- a/sim/testsuite/sim/frv/rett.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for rett $debug -# mach: all - - .include "testutils.inc" - - start - - .global rett -rett: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x0 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 -ok0: - test_gr_immed 1,gr7 - pass - fail -ok1: - inc_gr_immed 1,gr7 - rett 1 ; should be a nop - rett 0 - fail diff --git a/sim/testsuite/sim/frv/scan.cgs b/sim/testsuite/sim/frv/scan.cgs deleted file mode 100644 index d19107d..0000000 --- a/sim/testsuite/sim/frv/scan.cgs +++ /dev/null @@ -1,73 +0,0 @@ -# frv testcase for scan $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global scan -scan: - set_gr_limmed 0x2aaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - scan gr7,gr8,gr9 - test_gr_immed 0,gr9 - test_gr_limmed 0x2aaa,0xaaaa,gr7 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0x2aaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaab,gr8 - scan gr7,gr8,gr9 - test_gr_immed 0,gr9 - test_gr_limmed 0x2aaa,0xaaaa,gr7 - test_gr_limmed 0xaaaa,0xaaab,gr8 - - set_gr_limmed 0xd555,0x5555,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - scan gr7,gr8,gr9 - test_gr_immed 63,gr9 - test_gr_limmed 0xd555,0x5555,gr7 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xd555,0x5555,gr7 - set_gr_limmed 0xaaaa,0xaaab,gr8 - scan gr7,gr8,gr9 - test_gr_immed 63,gr9 - test_gr_limmed 0xd555,0x5555,gr7 - test_gr_limmed 0xaaaa,0xaaab,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - scan gr7,gr8,gr9 - test_gr_immed 0,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - scan gr7,gr8,gr9 - test_gr_immed 2,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - scan gr7,gr8,gr9 - test_gr_immed 16,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - scan gr7,gr8,gr9 - test_gr_immed 31,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - scan gr7,gr8,gr9 - test_gr_immed 7,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/scani.cgs b/sim/testsuite/sim/frv/scani.cgs deleted file mode 100644 index 97175dc..0000000 --- a/sim/testsuite/sim/frv/scani.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for scani $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global scani -scani: - set_gr_limmed 0xffff,0xfeaa,gr7 - scani gr7,0x2aa,gr9 - test_gr_immed 0,gr9 - test_gr_limmed 0xffff,0xfeaa,gr7 - - set_gr_limmed 0xffff,0xfeaa,gr7 - scani gr7,0x2ab,gr9 - test_gr_immed 0,gr9 - test_gr_limmed 0xffff,0xfeaa,gr7 - - set_gr_limmed 0x0000,0x0155,gr7 - scani gr7,0x2aa,gr9 - test_gr_immed 63,gr9 - test_gr_limmed 0x0000,0x0155,gr7 - - set_gr_limmed 0x0000,0x0155,gr7 - scani gr7,0x2ab,gr9 - test_gr_immed 63,gr9 - test_gr_limmed 0x0000,0x0155,gr7 - - set_gr_limmed 0x7fff,0xffff,gr7 - scani gr7,-1,gr9 - test_gr_immed 0,gr9 - test_gr_limmed 0x7fff,0xffff,gr7 - - set_gr_limmed 0xbfff,0xffff,gr7 - scani gr7,-1,gr9 - test_gr_immed 1,gr9 - test_gr_limmed 0xbfff,0xffff,gr7 - - set_gr_limmed 0xfffe,0xffff,gr7 - scani gr7,-1,gr9 - test_gr_immed 15,gr9 - test_gr_limmed 0xfffe,0xffff,gr7 - - set_gr_limmed 0xffff,0xfffd,gr7 - scani gr7,-1,gr9 - test_gr_immed 30,gr9 - test_gr_limmed 0xffff,0xfffd,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - scani gr7,-2048,gr9 - test_gr_immed 2,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - - pass diff --git a/sim/testsuite/sim/frv/sdiv.cgs b/sim/testsuite/sim/frv/sdiv.cgs deleted file mode 100644 index d193b23..0000000 --- a/sim/testsuite/sim/frv/sdiv.cgs +++ /dev/null @@ -1,75 +0,0 @@ -# frv testcase for sdiv $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sdiv -sdiv: - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - sdiv gr1,gr3,gr2 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - sdiv gr1,gr3,gr2 - test_gr_immed -1,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - sdiv gr1,gr3,gr2 - test_gr_limmed 0x7fff,0xffff,gr2 - test_spr_bits 0x4,2,1,isr ; isr.aexc is set - - and_spr_immed -33,isr ; turn off isr.edem - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_addr e1,gr17 - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 -e1: sdiv gr1,gr3,gr2 ; overflow - test_gr_immed 1,gr15 - test_gr_limmed 0x8000,0x0000,gr2; gr2 updated - - ; divide by zero - set_spr_addr ok2,lr - set_gr_addr e2,gr17 - set_gr_immed 0xdeadbeef,gr2 -e2: sdiv gr1,gr0,gr2 ; divide by zero - test_gr_immed 2,gr15 ; handler called - test_gr_immed 0xdeadbeef,gr2 ; gr2 not updated. - - pass - -ok1: ; exception handler for overflow - test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail - -ok2: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/sdivi.cgs b/sim/testsuite/sim/frv/sdivi.cgs deleted file mode 100644 index eb781e7..0000000 --- a/sim/testsuite/sim/frv/sdivi.cgs +++ /dev/null @@ -1,74 +0,0 @@ -# frv testcase for sdivi $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sdivi -sdivi: - ; simple division 12 / 3 - set_gr_immed 12,gr1 - sdivi gr1,3,gr2 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0xfedc,0xba98,gr1 - sdivi gr1,0x7ff,gr2 - test_gr_limmed 0xffff,0xdb93,gr2 - - ; Random negative example - set_gr_limmed 0xfedc,0xba98,gr1 - sdivi gr1,-2048,gr2 - test_gr_immed 0x2468,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_limmed 0x8000,0x0000,gr1 - sdivi gr1,-1,gr2 - test_gr_limmed 0x7fff,0xffff,gr2 - test_spr_bits 0x4,2,1,isr ; isr.aexc is set - - and_spr_immed -33,isr ; turn off isr.edem - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_addr e1,gr17 - set_gr_limmed 0x8000,0x0000,gr1 -e1: sdivi gr1,-1,gr2 - test_gr_immed 1,gr15 - test_gr_limmed 0x8000,0x0000,gr2 - - ; divide by zero - set_spr_addr ok2,lr - set_gr_addr e2,gr17 -e2: sdivi gr1,0,gr2 ; divide by zero - test_gr_immed 2,gr15 - - pass - -ok1: ; exception handler for overflow - test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail - -ok2: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/sethi.cgs b/sim/testsuite/sim/frv/sethi.cgs deleted file mode 100644 index 00a3bdd..0000000 --- a/sim/testsuite/sim/frv/sethi.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for sethi $s16,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sethi -sethi: - set_gr_immed 0,gr1 - sethi 0,gr1 - test_gr_immed 0,gr1 - sethi 1,gr1 - test_gr_immed 0x00010000,gr1 - sethi 0x7fff,gr1 - test_gr_immed 0x7fff0000,gr1 - - pass diff --git a/sim/testsuite/sim/frv/sethilo.pcgs b/sim/testsuite/sim/frv/sethilo.pcgs deleted file mode 100644 index c8e7b60..0000000 --- a/sim/testsuite/sim/frv/sethilo.pcgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv parallel testcase for sethi $s16,$GRk and setlo $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sethilo -sethilo: - sethi.p 0xdead,gr7 - setlo 0xbeef,gr7 - test_gr_immed 0xdeadbeef,gr7 - - setlo.p 0xdead,gr7 - sethi 0xbeef,gr7 - test_gr_immed 0xbeefdead,gr7 - - pass diff --git a/sim/testsuite/sim/frv/setlo.cgs b/sim/testsuite/sim/frv/setlo.cgs deleted file mode 100644 index 6bdac2e..0000000 --- a/sim/testsuite/sim/frv/setlo.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for setlo $s16,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_gr_immed 0,gr1 - setlo 0,gr1 - test_gr_immed 0,gr1 - setlo 1,gr1 - test_gr_immed 1,gr1 - setlo 0x7fff,gr1 - test_gr_immed 0x7fff,gr1 - - pass diff --git a/sim/testsuite/sim/frv/setlos.cgs b/sim/testsuite/sim/frv/setlos.cgs deleted file mode 100644 index 8979d13..0000000 --- a/sim/testsuite/sim/frv/setlos.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# frv testcase for setlos $s16,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global setlos -setlos: - setlos 0,gr1 - test_gr_immed 0,gr1 - setlos 1,gr1 - test_gr_immed 1,gr1 - setlos 0x7fff,gr1 - test_gr_immed 0x7fff,gr1 - setlos -1,gr1 - test_gr_immed -1,gr1 - setlos -32768,gr1 - test_gr_immed -32768,gr1 - - pass diff --git a/sim/testsuite/sim/frv/sll.cgs b/sim/testsuite/sim/frv/sll.cgs deleted file mode 100644 index 9103cf6..0000000 --- a/sim/testsuite/sim/frv/sll.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for sll $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sll -sll: - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - sll gr8,gr7,gr8 - test_icc 1 1 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sll gr8,gr7,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sll gr8,gr7,gr8 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - sll gr8,gr7,gr8 - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/sllcc.cgs b/sim/testsuite/sim/frv/sllcc.cgs deleted file mode 100644 index 533b504..0000000 --- a/sim/testsuite/sim/frv/sllcc.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for sllcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global sllcc -sllcc: - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sllcc gr8,gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sllcc gr8,gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sllcc gr8,gr7,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - sllcc gr8,gr7,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/slli.cgs b/sim/testsuite/sim/frv/slli.cgs deleted file mode 100644 index 80c25c0..0000000 --- a/sim/testsuite/sim/frv/slli.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for slli $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global slli -slli: - set_gr_immed 2,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - slli gr8,0x7e0,gr8 ; Shift by 0 - test_icc 1 1 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - slli gr8,-31,gr8 ; Shift by 1 - test_icc 1 1 1 1 icc0 - test_gr_immed 4,gr8 - - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - slli gr8,31,gr8 ; Shift by 31 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - slli gr8,31,gr8 ; clear register - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/sllicc.cgs b/sim/testsuite/sim/frv/sllicc.cgs deleted file mode 100644 index b8e4c7d..0000000 --- a/sim/testsuite/sim/frv/sllicc.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for sllicc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global sllicc -sllicc: - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sllicc gr8,0x1e0,gr8,icc0 ; Shift by 0 - test_icc 0 0 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sllicc gr8,-31,gr8,icc0 ; Shift by 1 - test_icc 0 0 0 1 icc0 - test_gr_immed 4,gr8 - - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sllicc gr8,31,gr8,icc0 ; Shift by 31 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 2,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - sllicc gr8,31,gr8,icc0 ; clear register - test_icc 0 1 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/smul.cgs b/sim/testsuite/sim/frv/smul.cgs deleted file mode 100644 index ed065a9..0000000 --- a/sim/testsuite/sim/frv/smul.cgs +++ /dev/null @@ -1,182 +0,0 @@ -# frv testcase for smul $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global smul -smul: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - smul gr7,gr8,gr8 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - smul gr7,gr8,gr8 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - smul gr7,gr8,gr8 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0xc000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - smul gr7,gr8,gr8 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0x00000000,gr9 - - pass diff --git a/sim/testsuite/sim/frv/smulcc.cgs b/sim/testsuite/sim/frv/smulcc.cgs deleted file mode 100644 index 76a009e..0000000 --- a/sim/testsuite/sim/frv/smulcc.cgs +++ /dev/null @@ -1,238 +0,0 @@ -# frv testcase for smulcc $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global smulcc -smulcc: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x0,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0x1,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x2,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0xb,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x8,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0xd,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0xe,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0xf,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0xc,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x5,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x6,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x7,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x4,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0x9,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xa,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x4,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x5,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x6,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x7,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xc,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xd,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0xe,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0xc,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0xd,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xe,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xf,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0x00000000,gr9 - - pass diff --git a/sim/testsuite/sim/frv/smuli.cgs b/sim/testsuite/sim/frv/smuli.cgs deleted file mode 100644 index 19a695c..0000000 --- a/sim/testsuite/sim/frv/smuli.cgs +++ /dev/null @@ -1,210 +0,0 @@ -# frv testcase for smuli $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global smuli -smuli: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_icc 0x0,0 - smuli gr7,2,gr8 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_icc 0x1,0 - smuli gr7,2,gr8 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_icc 0x2,0 - smuli gr7,1,gr8 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_icc 0x3,0 - smuli gr7,2,gr8 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_icc 0x4,0 - smuli gr7,0,gr8 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_icc 0x5,0 - smuli gr7,2,gr8 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_icc 0x6,0 - smuli gr7,2,gr8 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_icc 0x7,0 - smuli gr7,4,gr8 - test_icc 0 1 1 1 icc0 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_icc 0x8,0 - smuli gr7,0x7ff,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x3ff,gr8 - test_gr_limmed 0x7fff,0xf801,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_icc 0x9,0 - smuli gr7,2,gr8 - test_icc 1 0 0 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_icc 0xa,0 - smuli gr7,-2,gr8 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_icc 0xb,0 - smuli gr7,-2,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_icc 0xc,0 - smuli gr7,1,gr8 - test_icc 1 1 0 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_icc 0xd,0 - smuli gr7,-2,gr8 - test_icc 1 1 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_icc 0xe,0 - smuli gr7,0,gr8 - test_icc 1 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_icc 0xf,0 - smuli gr7,-2,gr8 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_icc 0x0,0 - smuli gr7,-2,gr8 - test_icc 0 0 0 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_icc 0x1,0 - smuli gr7,-2,gr8 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_icc 0x2,0 - smuli gr7,-4,gr8 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_icc 0x3,0 - smuli gr7,-2048,gr8 - test_icc 0 0 1 1 icc0 - test_gr_limmed 0xffff,0xfc00,gr8 - test_gr_limmed 0x0000,0x0800,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_icc 0x4,0 - smuli gr7,-2,gr8 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_icc 0x5,0 - smuli gr7,-2,gr8 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_icc 0x6,0 - smuli gr7,-1,gr8 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_icc 0x7,0 - smuli gr7,-2,gr8 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_icc 0x8,0 - smuli gr7,-2,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_icc 0x9,0 - smuli gr7,-4,gr8 - test_icc 1 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_icc 0xa,0 - smuli gr7,-2048,gr8 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x0000,0x03ff,gr8 - test_gr_limmed 0xffff,0xf800,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_icc 0xb,0 - smuli gr7,-2048,gr8 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0x0000,0x0400,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - pass diff --git a/sim/testsuite/sim/frv/smulicc.cgs b/sim/testsuite/sim/frv/smulicc.cgs deleted file mode 100644 index e9aa889..0000000 --- a/sim/testsuite/sim/frv/smulicc.cgs +++ /dev/null @@ -1,210 +0,0 @@ -# frv testcase for smulicc $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global smulicc -smulicc: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_icc 0x0,0 - smulicc gr7,2,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_icc 0x1,0 - smulicc gr7,2,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_icc 0x2,0 - smulicc gr7,1,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_icc 0x3,0 - smulicc gr7,2,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_icc 0x4,0 - smulicc gr7,0,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_icc 0x5,0 - smulicc gr7,2,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_icc 0x6,0 - smulicc gr7,2,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_icc 0x7,0 - smulicc gr7,4,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_icc 0x8,0 - smulicc gr7,0x1ff,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0xff,gr8 - test_gr_limmed 0x7fff,0xfe01,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_icc 0x9,0 - smulicc gr7,2,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_icc 0xa,0 - smulicc gr7,-2,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_icc 0xb,0 - smulicc gr7,-2,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_icc 0xc,0 - smulicc gr7,1,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_icc 0xd,0 - smulicc gr7,-2,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_icc 0xe,0 - smulicc gr7,0,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_icc 0xf,0 - smulicc gr7,-2,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_icc 0x0,0 - smulicc gr7,-2,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_icc 0x1,0 - smulicc gr7,-2,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_icc 0x2,0 - smulicc gr7,-4,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_icc 0x3,0 - smulicc gr7,-512,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xff00,gr8 - test_gr_limmed 0x0000,0x0200,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_icc 0x4,0 - smulicc gr7,-2,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_icc 0x5,0 - smulicc gr7,-2,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_icc 0x6,0 - smulicc gr7,-1,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_icc 0x7,0 - smulicc gr7,-2,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_icc 0x8,0 - smulicc gr7,-2,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_icc 0x9,0 - smulicc gr7,-4,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_icc 0xa,0 - smulicc gr7,-512,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x0000,0x00ff,gr8 - test_gr_limmed 0xffff,0xfe00,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_icc 0xb,0 - smulicc gr7,-512,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_limmed 0x0000,0x0100,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - pass diff --git a/sim/testsuite/sim/frv/sra.cgs b/sim/testsuite/sim/frv/sra.cgs deleted file mode 100644 index 0f0c864..0000000 --- a/sim/testsuite/sim/frv/sra.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for sra $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sra -sra: - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - sra gr8,gr7,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sra gr8,gr7,gr8 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sra gr8,gr7,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed -1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - sra gr8,gr7,gr8 - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/sracc.cgs b/sim/testsuite/sim/frv/sracc.cgs deleted file mode 100644 index 14f4a8b..0000000 --- a/sim/testsuite/sim/frv/sracc.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for sracc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global sracc -sracc: - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - sracc gr8,gr7,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sracc gr8,gr7,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sracc gr8,gr7,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - sracc gr8,gr7,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/srai.cgs b/sim/testsuite/sim/frv/srai.cgs deleted file mode 100644 index 02b9654..0000000 --- a/sim/testsuite/sim/frv/srai.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for srai $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global srai -srai: - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - srai gr8,0x7e0,gr8 ; Shift by 0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srai gr8,-31,gr8 ; Shift by 1 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srai gr8,31,gr8 ; Shift by 31 - test_icc 1 1 1 1 icc0 - test_gr_immed -1,gr8 - - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - srai gr8,31,gr8 ; clear register - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/sraicc.cgs b/sim/testsuite/sim/frv/sraicc.cgs deleted file mode 100644 index 5dbd1e6..0000000 --- a/sim/testsuite/sim/frv/sraicc.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for sraicc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global sraicc -sraicc: - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - sraicc gr8,0x1e0,gr8,icc0 ; Shift by 0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sraicc gr8,-31,gr8,icc0 ; Shift by 1 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sraicc gr8,31,gr8,icc0 ; Shift by 31 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - sraicc gr8,31,gr8,icc0 ; clear register - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/srl.cgs b/sim/testsuite/sim/frv/srl.cgs deleted file mode 100644 index 045e75e..0000000 --- a/sim/testsuite/sim/frv/srl.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for srl $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global srl -srl: - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - srl gr8,gr7,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srl gr8,gr7,gr8 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srl gr8,gr7,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - srl gr8,gr7,gr8 - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/srlcc.cgs b/sim/testsuite/sim/frv/srlcc.cgs deleted file mode 100644 index 1450a4b..0000000 --- a/sim/testsuite/sim/frv/srlcc.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for srlcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global srlcc -srlcc: - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - srlcc gr8,gr7,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srlcc gr8,gr7,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srlcc gr8,gr7,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - srlcc gr8,gr7,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/srli.cgs b/sim/testsuite/sim/frv/srli.cgs deleted file mode 100644 index 72207d3..0000000 --- a/sim/testsuite/sim/frv/srli.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for srli $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global srli -srli: - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - srli gr8,0x7e0,gr8 ; Shift by 0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srli gr8,-31,gr8 ; Shift by 1 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srli gr8,31,gr8 ; Shift by 31 - test_icc 1 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - srli gr8,31,gr8 ; clear register - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/srlicc.cgs b/sim/testsuite/sim/frv/srlicc.cgs deleted file mode 100644 index d232802..0000000 --- a/sim/testsuite/sim/frv/srlicc.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for srlicc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global srlicc -srlicc: - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - srlicc gr8,0x1e0,gr8,icc0 ; Shift by 0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srlicc gr8,-31,gr8,icc0 ; Shift by 1 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srlicc gr8,31,gr8,icc0 ; Shift by 31 - test_icc 0 0 1 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - srlicc gr8,31,gr8,icc0 ; clear register - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/st.cgs b/sim/testsuite/sim/frv/st.cgs deleted file mode 100644 index 557713c..0000000 --- a/sim/testsuite/sim/frv/st.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for st $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - st gr8,@(sp,gr7) - test_mem_limmed 0xffff,0xffff,sp - - pass diff --git a/sim/testsuite/sim/frv/stb.cgs b/sim/testsuite/sim/frv/stb.cgs deleted file mode 100644 index 15fa1e6..0000000 --- a/sim/testsuite/sim/frv/stb.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for stb $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - stb gr8,@(sp,gr7) - test_mem_limmed 0xffad,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stbf.cgs b/sim/testsuite/sim/frv/stbf.cgs deleted file mode 100644 index 741327d..0000000 --- a/sim/testsuite/sim/frv/stbf.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for stbf $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stbf -stbf: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - stbf fr8,@(sp,gr7) - test_mem_limmed 0xffad,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stbfi.cgs b/sim/testsuite/sim/frv/stbfi.cgs deleted file mode 100644 index cfea708..0000000 --- a/sim/testsuite/sim/frv/stbfi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for stbfi $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stbfi -stbfi: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xffff,0xffff,fr8 - stbfi fr8,@(sp,0) - test_mem_limmed 0xffad,0xbeef,sp - - inc_gr_immed 0x801,sp ; 2049 - stbfi fr8,@(sp,-2048) - test_mem_limmed 0xffff,0xbeef,gr20 - - inc_gr_immed -4094,sp - stbfi fr8,@(sp,0x7ff) - test_mem_limmed 0xffff,0xffef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/stbfu.cgs b/sim/testsuite/sim/frv/stbfu.cgs deleted file mode 100644 index 01bbb99..0000000 --- a/sim/testsuite/sim/frv/stbfu.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for stbfu $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stbfu -stbfu: - set_gr_gr sp,gr9 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - stbfu fr8,@(sp,gr7) - test_mem_limmed 0xffad,0xbeef,sp - test_gr_gr sp,gr9 - - pass diff --git a/sim/testsuite/sim/frv/stbi.cgs b/sim/testsuite/sim/frv/stbi.cgs deleted file mode 100644 index f23efc9..0000000 --- a/sim/testsuite/sim/frv/stbi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for stbi $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stbi -stbi: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xffff,0xffff,gr8 - stbi gr8,@(sp,0) - test_mem_limmed 0xffad,0xbeef,sp - - inc_gr_immed 0x801,sp ; 2049 - stbi gr8,@(sp,-2048) - test_mem_limmed 0xffff,0xbeef,gr20 - - inc_gr_immed -4094,sp - stbi gr8,@(sp,0x7ff) - test_mem_limmed 0xffff,0xffef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/stbu.cgs b/sim/testsuite/sim/frv/stbu.cgs deleted file mode 100644 index e56ad11..0000000 --- a/sim/testsuite/sim/frv/stbu.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for stbu $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stbu -stbu: - set_gr_gr sp,gr9 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - stbu gr8,@(sp,gr7) - test_mem_limmed 0xffad,0xbeef,sp - test_gr_gr sp,gr9 - - pass diff --git a/sim/testsuite/sim/frv/stc.cgs b/sim/testsuite/sim/frv/stc.cgs deleted file mode 100644 index 581297c..0000000 --- a/sim/testsuite/sim/frv/stc.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# frv testcase for stc $CPRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stc -stc: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xffff,0xffff,cpr8 - stc cpr8,@(sp,gr7) - test_mem_limmed 0xffff,0xffff,sp - - pass diff --git a/sim/testsuite/sim/frv/stcu.cgs b/sim/testsuite/sim/frv/stcu.cgs deleted file mode 100644 index eb9e6c5..0000000 --- a/sim/testsuite/sim/frv/stcu.cgs +++ /dev/null @@ -1,33 +0,0 @@ -# frv testcase for stcu $CPRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stcu -stcu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xffff,0xffff,cpr8 - stcu cpr8,@(sp,gr7) - test_mem_limmed 0xffff,0xffff,sp - test_gr_gr sp,gr20 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_cpr_limmed 0x1234,0x5678,cpr8 - stcu cpr8,@(sp,gr7) - test_mem_limmed 0x1234,0x5678,sp - test_gr_gr sp,gr20 - - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - set_cpr_limmed 0x9abc,0xdef0,cpr8 - stcu cpr8,@(sp,gr7) - test_mem_limmed 0x9abc,0xdef0,sp - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/std.cgs b/sim/testsuite/sim/frv/std.cgs deleted file mode 100644 index 8a2ed12..0000000 --- a/sim/testsuite/sim/frv/std.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# frv testcase for std $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - std gr8,@(sp,gr7) - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr3 ; sp is gr1 - set_gr_limmed 0xbeef,0xdead,gr0 - set_gr_limmed 0xdead,0xbeef,gr1 - std gr0,@(gr3,gr7) - test_mem_immed 0,gr3 - inc_gr_immed 4,gr3 - test_mem_immed 0,gr3 - - pass diff --git a/sim/testsuite/sim/frv/std.pcgs b/sim/testsuite/sim/frv/std.pcgs deleted file mode 100644 index d518b8b..0000000 --- a/sim/testsuite/sim/frv/std.pcgs +++ /dev/null @@ -1,37 +0,0 @@ -# frv parallel testcase for std $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - std gr8,@(sp,gr7) ; non parallel - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - std.p gr8,@(sp,gr0) ; parallel - setlos 0,gr8 - ld @(sp,gr0),gr10 - ld @(sp,gr7),gr11 - test_mem_limmed 0xbeef,0xdead,sp ; memory is set - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - test_gr_immed 0xbeefdead,gr10 ; regs were pre-loaded - test_gr_immed 0xdeadbeef,gr11 ; not this one - - pass diff --git a/sim/testsuite/sim/frv/stdc.cgs b/sim/testsuite/sim/frv/stdc.cgs deleted file mode 100644 index bdff0ac..0000000 --- a/sim/testsuite/sim/frv/stdc.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# frv testcase for stdc $CPk,@($GRi,$GRj) -# mach: frv - - .include "testutils.inc" - - start - - .global stdc -stdc: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - stdc cpr8,@(sp,gr7) - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stdc.pcgs b/sim/testsuite/sim/frv/stdc.pcgs deleted file mode 100644 index 46c4925..0000000 --- a/sim/testsuite/sim/frv/stdc.pcgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv parallel testcase for stdc $CPk,@($GRi,$GRj) -# mach: frv - - .include "testutils.inc" - - start - - .global stdc -stdc: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - stdc cpr8,@(sp,gr7) ; non parallel - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 4,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - stdc.p cpr8,@(sp,gr0) ; parallel - addi sp,4,sp - subi sp,4,sp - ldc @(sp,gr0),cpr10 - ldc @(sp,gr7),cpr11 - test_mem_limmed 0xbeef,0xdead,sp ; memory is set - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - - pass diff --git a/sim/testsuite/sim/frv/stdcu.cgs b/sim/testsuite/sim/frv/stdcu.cgs deleted file mode 100644 index bbae5ff..0000000 --- a/sim/testsuite/sim/frv/stdcu.cgs +++ /dev/null @@ -1,44 +0,0 @@ -# frv testcase for stdcu $CPk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stdcu -stdcu: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - stdcu cpr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - inc_gr_immed -12,sp - set_gr_immed 8,gr7 - set_cpr_limmed 0x1234,0x5678,cpr8 - set_cpr_limmed 0x9abc,0xdef0,cpr9 - stdcu cpr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0x1234,0x5678,sp - inc_gr_immed 4,sp - test_mem_limmed 0x9abc,0xdef0,sp - - inc_gr_immed 4,sp - set_gr_immed -8,gr7 - set_cpr_limmed 0xfedc,0xba98,cpr8 - set_cpr_limmed 0x7654,0x3210,cpr9 - stdcu cpr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xfedc,0xba98,sp - inc_gr_immed 4,sp - test_mem_limmed 0x7654,0x3210,sp - - pass diff --git a/sim/testsuite/sim/frv/stdf.cgs b/sim/testsuite/sim/frv/stdf.cgs deleted file mode 100644 index 82c1461..0000000 --- a/sim/testsuite/sim/frv/stdf.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# frv testcase for stdf $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stdf -stdf: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - stdf fr8,@(sp,gr7) - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stdf.pcgs b/sim/testsuite/sim/frv/stdf.pcgs deleted file mode 100644 index 7ef991c..0000000 --- a/sim/testsuite/sim/frv/stdf.pcgs +++ /dev/null @@ -1,37 +0,0 @@ -# frv parallel testcase for stdf $GRk,@($GRi,$GRj) -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global stdf -stdf: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - stdf fr8,@(sp,gr7) ; non parallel - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 4,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - stdf.p fr8,@(sp,gr0) ; parallel - fnegs fr8,fr8 - ldf @(sp,gr0),fr10 - ldf @(sp,gr7),fr11 ; memory is set - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - test_fr_iimmed 0xbeefdead,fr10 ; regs were pre-loaded - test_fr_iimmed 0xdeadbeef,fr11 ; not this one - - pass diff --git a/sim/testsuite/sim/frv/stdfi.cgs b/sim/testsuite/sim/frv/stdfi.cgs deleted file mode 100644 index fea9b51..0000000 --- a/sim/testsuite/sim/frv/stdfi.cgs +++ /dev/null @@ -1,56 +0,0 @@ -# frv testcase for stdfi $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stdfi -stdfi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr21 - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - set_gr_gr sp,gr22 - inc_gr_immed -4,sp - set_mem_limmed 0x8765,0x4321,sp - set_gr_gr sp,gr23 - inc_gr_immed -4,sp - set_mem_limmed 0xfedc,0xba98,sp - set_gr_gr sp,gr24 - inc_gr_immed -4,sp - set_mem_limmed 0x89ab,0xcdef,sp - set_gr_gr sp,gr25 - set_fr_iimmed 0xffff,0xffff,fr8 - set_fr_iimmed 0xffff,0xffff,fr9 - - stdfi fr8,@(sp,0) - test_mem_limmed 0xffff,0xffff,gr25 - test_mem_limmed 0xffff,0xffff,gr24 - test_mem_limmed 0x8765,0x4321,gr23 - test_mem_limmed 0x1234,0x5678,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 0x808,sp ; 2056 - stdfi fr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr25 - test_mem_limmed 0xffff,0xffff,gr24 - test_mem_limmed 0xffff,0xffff,gr23 - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed -4080,sp - stdfi fr8,@(sp,0x7f8) - test_mem_limmed 0xffff,0xffff,gr25 - test_mem_limmed 0xffff,0xffff,gr24 - test_mem_limmed 0xffff,0xffff,gr23 - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xffff,0xffff,gr20 - - pass diff --git a/sim/testsuite/sim/frv/stdfu.cgs b/sim/testsuite/sim/frv/stdfu.cgs deleted file mode 100644 index 439cfa0..0000000 --- a/sim/testsuite/sim/frv/stdfu.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for stdfu $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stdfu -stdfu: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - stdfu fr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stdi.cgs b/sim/testsuite/sim/frv/stdi.cgs deleted file mode 100644 index e1a783d..0000000 --- a/sim/testsuite/sim/frv/stdi.cgs +++ /dev/null @@ -1,56 +0,0 @@ -# frv testcase for stdi $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stdi -stdi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr21 - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - set_gr_gr sp,gr22 - inc_gr_immed -4,sp - set_mem_limmed 0x8765,0x4321,sp - set_gr_gr sp,gr23 - inc_gr_immed -4,sp - set_mem_limmed 0xfedc,0xba98,sp - set_gr_gr sp,gr24 - inc_gr_immed -4,sp - set_mem_limmed 0x89ab,0xcdef,sp - set_gr_gr sp,gr25 - set_gr_limmed 0xffff,0xffff,gr8 - set_gr_limmed 0xffff,0xffff,gr9 - - stdi gr8,@(sp,0) - test_mem_limmed 0xffff,0xffff,gr25 - test_mem_limmed 0xffff,0xffff,gr24 - test_mem_limmed 0x8765,0x4321,gr23 - test_mem_limmed 0x1234,0x5678,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 0x808,sp ; 2056 - stdi gr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr25 - test_mem_limmed 0xffff,0xffff,gr24 - test_mem_limmed 0xffff,0xffff,gr23 - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed -4080,sp - stdi gr8,@(sp,0x7f8) - test_mem_limmed 0xffff,0xffff,gr25 - test_mem_limmed 0xffff,0xffff,gr24 - test_mem_limmed 0xffff,0xffff,gr23 - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xffff,0xffff,gr20 - - pass diff --git a/sim/testsuite/sim/frv/stdu.cgs b/sim/testsuite/sim/frv/stdu.cgs deleted file mode 100644 index b5f122f..0000000 --- a/sim/testsuite/sim/frv/stdu.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for stdu $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stdu -stdu: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - stdu gr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stf.cgs b/sim/testsuite/sim/frv/stf.cgs deleted file mode 100644 index 5ebc060..0000000 --- a/sim/testsuite/sim/frv/stf.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for stf $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stf -stf: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - stf fr8,@(sp,gr7) - test_mem_limmed 0xffff,0xffff,sp - - pass diff --git a/sim/testsuite/sim/frv/stfi.cgs b/sim/testsuite/sim/frv/stfi.cgs deleted file mode 100644 index cfce1fd..0000000 --- a/sim/testsuite/sim/frv/stfi.cgs +++ /dev/null @@ -1,37 +0,0 @@ -# frv testcase for stfi $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stfi -stfi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr21 - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - set_gr_gr sp,gr22 - set_fr_iimmed 0xffff,0xffff,fr8 - - stfi fr8,@(sp,0) - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 0x804,sp ; 2052 - stfi fr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed -4088,sp - stfi fr8,@(sp,0x7fc) - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xffff,0xffff,gr20 - - pass diff --git a/sim/testsuite/sim/frv/stfu.cgs b/sim/testsuite/sim/frv/stfu.cgs deleted file mode 100644 index e47e61d..0000000 --- a/sim/testsuite/sim/frv/stfu.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for stfu $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stfu -stfu: - set_gr_gr sp,gr9 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - stfu fr8,@(sp,gr7) - test_mem_limmed 0xffff,0xffff,sp - test_gr_gr sp,gr9 - - pass diff --git a/sim/testsuite/sim/frv/sth.cgs b/sim/testsuite/sim/frv/sth.cgs deleted file mode 100644 index c11ae40..0000000 --- a/sim/testsuite/sim/frv/sth.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for sth $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - sth gr8,@(sp,gr7) - test_mem_limmed 0xffff,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/sthf.cgs b/sim/testsuite/sim/frv/sthf.cgs deleted file mode 100644 index 7310e4e..0000000 --- a/sim/testsuite/sim/frv/sthf.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for sthf $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global sthf -sthf: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - sthf fr8,@(sp,gr7) - test_mem_limmed 0xffff,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/sthfi.cgs b/sim/testsuite/sim/frv/sthfi.cgs deleted file mode 100644 index ae9da97..0000000 --- a/sim/testsuite/sim/frv/sthfi.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase for sthfi $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global sthfi -sthfi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr21 - set_fr_iimmed 0xffff,0xffff,fr8 - - sthfi fr8,@(sp,0) - test_mem_limmed 0xffff,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 0x802,sp ; 2050 - sthfi fr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed -4092,sp - sthfi fr8,@(sp,0x7fe) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xffff,0xbeef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/sthfu.cgs b/sim/testsuite/sim/frv/sthfu.cgs deleted file mode 100644 index df472e7..0000000 --- a/sim/testsuite/sim/frv/sthfu.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for sthfu $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global sthfu -sthfu: - set_gr_gr sp,gr9 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - sthfu fr8,@(sp,gr7) - test_mem_limmed 0xffff,0xbeef,sp - test_gr_gr sp,gr9 - - pass diff --git a/sim/testsuite/sim/frv/sthi.cgs b/sim/testsuite/sim/frv/sthi.cgs deleted file mode 100644 index 93636e9..0000000 --- a/sim/testsuite/sim/frv/sthi.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase for sthi $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global sthi -sthi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr21 - set_gr_limmed 0xffff,0xffff,gr8 - - sthi gr8,@(sp,0) - test_mem_limmed 0xffff,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 0x802,sp ; 2050 - sthi gr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed -4092,sp - sthi gr8,@(sp,0x7fe) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xffff,0xbeef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/sthu.cgs b/sim/testsuite/sim/frv/sthu.cgs deleted file mode 100644 index ab35b30..0000000 --- a/sim/testsuite/sim/frv/sthu.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for sthu $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global sthu -sthu: - set_gr_gr sp,gr9 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - sthu gr8,@(sp,gr7) - test_mem_limmed 0xffff,0xbeef,sp - test_gr_gr sp,gr9 - - pass diff --git a/sim/testsuite/sim/frv/sti.cgs b/sim/testsuite/sim/frv/sti.cgs deleted file mode 100644 index ce05003..0000000 --- a/sim/testsuite/sim/frv/sti.cgs +++ /dev/null @@ -1,37 +0,0 @@ -# frv testcase for sti $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global sti -sti: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr21 - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - set_gr_gr sp,gr22 - set_gr_limmed 0xffff,0xffff,gr8 - - sti gr8,@(sp,0) - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 0x804,sp ; 2052 - sti gr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed -4088,sp - sti gr8,@(sp,0x7fc) - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xffff,0xffff,gr20 - - pass diff --git a/sim/testsuite/sim/frv/stq.cgs b/sim/testsuite/sim/frv/stq.cgs deleted file mode 100644 index 5ec8369..0000000 --- a/sim/testsuite/sim/frv/stq.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for stq $GRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stq -stq: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - stq gr8,@(sp,gr7) - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr4 ; sp is gr1 - set_gr_limmed 0xbeef,0xdead,gr0 - set_gr_limmed 0xdead,0xbeef,gr1 - set_gr_limmed 0xdead,0xdead,gr2 - set_gr_limmed 0xbeef,0xbeef,gr3 - stq gr0,@(gr4,gr7) - test_mem_immed 0,gr4 - inc_gr_immed 4,gr4 - test_mem_immed 0,gr4 - inc_gr_immed 4,gr4 - test_mem_immed 0,gr4 - inc_gr_immed 4,gr4 - test_mem_immed 0,gr4 - - pass diff --git a/sim/testsuite/sim/frv/stq.pcgs b/sim/testsuite/sim/frv/stq.pcgs deleted file mode 100644 index 268dd9e..0000000 --- a/sim/testsuite/sim/frv/stq.pcgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv parallel testcase for stq $GRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stq -stq: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - stq gr8,@(sp,gr7) ; non parallel - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - stq.p gr8,@(sp,gr7) ; parallel - setlos 0,gr8 - ldq @(sp,gr7),gr12 - test_mem_limmed 0xbeef,0xdead,sp ; memory is set - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - test_gr_immed 0xbeefdead,gr12 - test_gr_immed 0xdeadbeef,gr13 - test_gr_immed 0xdeaddead,gr14 - test_gr_immed 0xbeefbeef,gr15 - - pass diff --git a/sim/testsuite/sim/frv/stqc.cgs b/sim/testsuite/sim/frv/stqc.cgs deleted file mode 100644 index 19fc79d..0000000 --- a/sim/testsuite/sim/frv/stqc.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# frv testcase for stqc $CPRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqc -stqc: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - set_cpr_limmed 0xdead,0xdead,cpr10 - set_cpr_limmed 0xbeef,0xbeef,cpr11 - stqc cpr8,@(sp,gr7) - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stqc.pcgs b/sim/testsuite/sim/frv/stqc.pcgs deleted file mode 100644 index bda68ba..0000000 --- a/sim/testsuite/sim/frv/stqc.pcgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv parallel testcase for stqc $CPRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqc -stqc: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - set_cpr_limmed 0xdead,0xdead,cpr10 - set_cpr_limmed 0xbeef,0xbeef,cpr11 - stqc cpr8,@(sp,gr7) ; non parallel - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - set_cpr_limmed 0xdead,0xdead,cpr10 - set_cpr_limmed 0xbeef,0xbeef,cpr11 - stqc.p cpr8,@(sp,gr7) ; parallel - addi sp,4,sp - subi sp,4,sp - ldqc @(sp,gr7),cpr12 - test_mem_limmed 0xbeef,0xdead,sp ; memory is set - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - test_cpr_limmed 0xbeef,0xdead,cpr12 - test_cpr_limmed 0xdead,0xbeef,cpr13 - test_cpr_limmed 0xdead,0xdead,cpr14 - test_cpr_limmed 0xbeef,0xbeef,cpr15 - - pass diff --git a/sim/testsuite/sim/frv/stqcu.cgs b/sim/testsuite/sim/frv/stqcu.cgs deleted file mode 100644 index a7746ca..0000000 --- a/sim/testsuite/sim/frv/stqcu.cgs +++ /dev/null @@ -1,66 +0,0 @@ -# frv testcase for stqcu $CPRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqcu -stqcu: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - set_cpr_limmed 0xdead,0xdead,cpr10 - set_cpr_limmed 0xbeef,0xbeef,cpr11 - stqcu cpr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - inc_gr_immed -28,sp - set_gr_immed 16,gr7 - set_cpr_limmed 0x1111,0x1111,cpr8 - set_cpr_limmed 0x2222,0x2222,cpr9 - set_cpr_limmed 0x3333,0x3333,cpr10 - set_cpr_limmed 0x4444,0x4444,cpr11 - stqcu cpr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0x1111,0x1111,sp - inc_gr_immed 4,sp - test_mem_limmed 0x2222,0x2222,sp - inc_gr_immed 4,sp - test_mem_limmed 0x3333,0x3333,sp - inc_gr_immed 4,sp - test_mem_limmed 0x4444,0x4444,sp - - inc_gr_immed 4,sp - set_gr_immed -16,gr7 - set_cpr_limmed 0x5555,0x5555,cpr8 - set_cpr_limmed 0x6666,0x6666,cpr9 - set_cpr_limmed 0x7777,0x7777,cpr10 - set_cpr_limmed 0x8888,0x8888,cpr11 - stqcu cpr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0x5555,0x5555,sp - inc_gr_immed 4,sp - test_mem_limmed 0x6666,0x6666,sp - inc_gr_immed 4,sp - test_mem_limmed 0x7777,0x7777,sp - inc_gr_immed 4,sp - test_mem_limmed 0x8888,0x8888,sp - - pass diff --git a/sim/testsuite/sim/frv/stqf.cgs b/sim/testsuite/sim/frv/stqf.cgs deleted file mode 100644 index 24dbb42..0000000 --- a/sim/testsuite/sim/frv/stqf.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# frv testcase for stqf $GRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqf -stqf: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - set_fr_iimmed 0xdead,0xdead,fr10 - set_fr_iimmed 0xbeef,0xbeef,fr11 - stqf fr8,@(sp,gr7) - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stqf.pcgs b/sim/testsuite/sim/frv/stqf.pcgs deleted file mode 100644 index 497f5fb..0000000 --- a/sim/testsuite/sim/frv/stqf.pcgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv parallel testcase for stqf $GRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqf -stqf: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - set_fr_iimmed 0xdead,0xdead,fr10 - set_fr_iimmed 0xbeef,0xbeef,fr11 - stqf fr8,@(sp,gr7) ; non-parallel - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - set_fr_iimmed 0xdead,0xdead,fr10 - set_fr_iimmed 0xbeef,0xbeef,fr11 - stqf.p fr8,@(sp,gr7) ; parallel - fnegs fr8,fr8 - ldqf @(sp,gr7),fr12 - test_mem_limmed 0xbeef,0xdead,sp ; memory is set - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - test_fr_iimmed 0xbeefdead,fr12 - test_fr_iimmed 0xdeadbeef,fr13 - test_fr_iimmed 0xdeaddead,fr14 - test_fr_iimmed 0xbeefbeef,fr15 - - pass diff --git a/sim/testsuite/sim/frv/stqfi.cgs b/sim/testsuite/sim/frv/stqfi.cgs deleted file mode 100644 index 6a36a90..0000000 --- a/sim/testsuite/sim/frv/stqfi.cgs +++ /dev/null @@ -1,95 +0,0 @@ -# frv testcase for stqfi $FRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqfi -stqfi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr10 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr11 - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - set_gr_gr sp,gr12 - inc_gr_immed -4,sp - set_mem_limmed 0x8765,0x4321,sp - set_gr_gr sp,gr13 - inc_gr_immed -4,sp - set_mem_limmed 0xfedc,0xba98,sp - set_gr_gr sp,gr14 - inc_gr_immed -4,sp - set_mem_limmed 0x89ab,0xcdef,sp - set_gr_gr sp,gr15 - inc_gr_immed -4,sp - set_mem_limmed 0x2345,0x6789,sp - set_gr_gr sp,gr16 - inc_gr_immed -4,sp - set_mem_limmed 0x9876,0x5432,sp - set_gr_gr sp,gr17 - inc_gr_immed -4,sp - set_mem_limmed 0x3456,0x789a,sp - set_gr_gr sp,gr18 - inc_gr_immed -4,sp - set_mem_limmed 0xa987,0x6543,sp - set_gr_gr sp,gr19 - inc_gr_immed -4,sp - set_mem_limmed 0x4567,0x89ab,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xba98,0x7654,sp - set_gr_gr sp,gr21 - set_fr_iimmed 0xffff,0xffff,fr8 - set_fr_iimmed 0xeeee,0xeeee,fr9 - set_fr_iimmed 0xdddd,0xdddd,fr10 - set_fr_iimmed 0xcccc,0xcccc,fr11 - - stqfi fr8,@(sp,0) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_mem_limmed 0xdddd,0xdddd,gr19 - test_mem_limmed 0xcccc,0xcccc,gr18 - test_mem_limmed 0x9876,0x5432,gr17 - test_mem_limmed 0x2345,0x6789,gr16 - test_mem_limmed 0x89ab,0xcdef,gr15 - test_mem_limmed 0xfedc,0xba98,gr14 - test_mem_limmed 0x8765,0x4321,gr13 - test_mem_limmed 0x1234,0x5678,gr12 - test_mem_limmed 0xbeef,0xdead,gr11 - test_mem_limmed 0xdead,0xbeef,gr10 - - inc_gr_immed 0x810,sp ; 2064 - stqfi fr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_mem_limmed 0xdddd,0xdddd,gr19 - test_mem_limmed 0xcccc,0xcccc,gr18 - test_mem_limmed 0xffff,0xffff,gr17 - test_mem_limmed 0xeeee,0xeeee,gr16 - test_mem_limmed 0xdddd,0xdddd,gr15 - test_mem_limmed 0xcccc,0xcccc,gr14 - test_mem_limmed 0x8765,0x4321,gr13 - test_mem_limmed 0x1234,0x5678,gr12 - test_mem_limmed 0xbeef,0xdead,gr11 - test_mem_limmed 0xdead,0xbeef,gr10 - - inc_gr_immed -4064,sp - stqfi fr8,@(sp,0x7f0) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_mem_limmed 0xdddd,0xdddd,gr19 - test_mem_limmed 0xcccc,0xcccc,gr18 - test_mem_limmed 0xffff,0xffff,gr17 - test_mem_limmed 0xeeee,0xeeee,gr16 - test_mem_limmed 0xdddd,0xdddd,gr15 - test_mem_limmed 0xcccc,0xcccc,gr14 - test_mem_limmed 0xffff,0xffff,gr13 - test_mem_limmed 0xeeee,0xeeee,gr12 - test_mem_limmed 0xdddd,0xdddd,gr11 - test_mem_limmed 0xcccc,0xcccc,gr10 - - pass diff --git a/sim/testsuite/sim/frv/stqfu.cgs b/sim/testsuite/sim/frv/stqfu.cgs deleted file mode 100644 index 80a1494..0000000 --- a/sim/testsuite/sim/frv/stqfu.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# frv testcase for stqfu $FRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqfu -stqfu: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - set_fr_iimmed 0xdead,0xdead,fr10 - set_fr_iimmed 0xbeef,0xbeef,fr11 - stqfu fr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stqi.cgs b/sim/testsuite/sim/frv/stqi.cgs deleted file mode 100644 index 5a3680e..0000000 --- a/sim/testsuite/sim/frv/stqi.cgs +++ /dev/null @@ -1,95 +0,0 @@ -# frv testcase for stqi $GRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqi -stqi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr10 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr11 - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - set_gr_gr sp,gr12 - inc_gr_immed -4,sp - set_mem_limmed 0x8765,0x4321,sp - set_gr_gr sp,gr13 - inc_gr_immed -4,sp - set_mem_limmed 0xfedc,0xba98,sp - set_gr_gr sp,gr14 - inc_gr_immed -4,sp - set_mem_limmed 0x89ab,0xcdef,sp - set_gr_gr sp,gr15 - inc_gr_immed -4,sp - set_mem_limmed 0x2345,0x6789,sp - set_gr_gr sp,gr16 - inc_gr_immed -4,sp - set_mem_limmed 0x9876,0x5432,sp - set_gr_gr sp,gr17 - inc_gr_immed -4,sp - set_mem_limmed 0x3456,0x789a,sp - set_gr_gr sp,gr18 - inc_gr_immed -4,sp - set_mem_limmed 0xa987,0x6543,sp - set_gr_gr sp,gr19 - inc_gr_immed -4,sp - set_mem_limmed 0x4567,0x89ab,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xba98,0x7654,sp - set_gr_gr sp,gr21 - set_gr_limmed 0xffff,0xffff,gr4 - set_gr_limmed 0xeeee,0xeeee,gr5 - set_gr_limmed 0xdddd,0xdddd,gr6 - set_gr_limmed 0xcccc,0xcccc,gr7 - - stqi gr4,@(sp,0) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_mem_limmed 0xdddd,0xdddd,gr19 - test_mem_limmed 0xcccc,0xcccc,gr18 - test_mem_limmed 0x9876,0x5432,gr17 - test_mem_limmed 0x2345,0x6789,gr16 - test_mem_limmed 0x89ab,0xcdef,gr15 - test_mem_limmed 0xfedc,0xba98,gr14 - test_mem_limmed 0x8765,0x4321,gr13 - test_mem_limmed 0x1234,0x5678,gr12 - test_mem_limmed 0xbeef,0xdead,gr11 - test_mem_limmed 0xdead,0xbeef,gr10 - - inc_gr_immed 0x810,sp ; 2064 - stqi gr4,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_mem_limmed 0xdddd,0xdddd,gr19 - test_mem_limmed 0xcccc,0xcccc,gr18 - test_mem_limmed 0xffff,0xffff,gr17 - test_mem_limmed 0xeeee,0xeeee,gr16 - test_mem_limmed 0xdddd,0xdddd,gr15 - test_mem_limmed 0xcccc,0xcccc,gr14 - test_mem_limmed 0x8765,0x4321,gr13 - test_mem_limmed 0x1234,0x5678,gr12 - test_mem_limmed 0xbeef,0xdead,gr11 - test_mem_limmed 0xdead,0xbeef,gr10 - - inc_gr_immed -4064,sp - stqi gr4,@(sp,0x7f0) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_mem_limmed 0xdddd,0xdddd,gr19 - test_mem_limmed 0xcccc,0xcccc,gr18 - test_mem_limmed 0xffff,0xffff,gr17 - test_mem_limmed 0xeeee,0xeeee,gr16 - test_mem_limmed 0xdddd,0xdddd,gr15 - test_mem_limmed 0xcccc,0xcccc,gr14 - test_mem_limmed 0xffff,0xffff,gr13 - test_mem_limmed 0xeeee,0xeeee,gr12 - test_mem_limmed 0xdddd,0xdddd,gr11 - test_mem_limmed 0xcccc,0xcccc,gr10 - - pass diff --git a/sim/testsuite/sim/frv/stqu.cgs b/sim/testsuite/sim/frv/stqu.cgs deleted file mode 100644 index 31e8de5..0000000 --- a/sim/testsuite/sim/frv/stqu.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# frv testcase for stqu $GRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqu -stqu: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - stqu gr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stu.cgs b/sim/testsuite/sim/frv/stu.cgs deleted file mode 100644 index cc48040..0000000 --- a/sim/testsuite/sim/frv/stu.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for stu $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stu -stu: - set_gr_gr sp,gr9 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - stu gr8,@(sp,gr7) - test_mem_limmed 0xffff,0xffff,sp - test_gr_gr sp,gr9 - - pass diff --git a/sim/testsuite/sim/frv/sub.cgs b/sim/testsuite/sim/frv/sub.cgs deleted file mode 100644 index 5a1410c..0000000 --- a/sim/testsuite/sim/frv/sub.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for sub $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sub -sub: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - sub gr8,gr7,gr8 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - sub gr8,gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - - sub gr8,gr8,gr8 - test_gr_immed 0,gr8 - - sub gr8,gr7,gr8 - test_gr_immed -1,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subcc.cgs b/sim/testsuite/sim/frv/subcc.cgs deleted file mode 100644 index 188e0ff..0000000 --- a/sim/testsuite/sim/frv/subcc.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for subcc $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global subcc -subcc: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - subcc gr8,gr7,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - subcc gr8,gr7,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_icc 0x0b,0 ; Set mask opposite of expected - subcc gr8,gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Set mask opposite of expected - subcc gr8,gr7,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subi.cgs b/sim/testsuite/sim/frv/subi.cgs deleted file mode 100644 index c632838..0000000 --- a/sim/testsuite/sim/frv/subi.cgs +++ /dev/null @@ -1,56 +0,0 @@ -# frv testcase for subi $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global subi -subi: - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - subi gr8,1,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - subi gr8,1,gr8 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x7ff,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - subi gr8,0x7ff,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Set mask opposite of expected - subi gr8,1,gr8 - test_icc 0 1 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - subi gr8,-1,gr8 - test_icc 1 1 1 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x06,0 ; Set mask opposite of expected - subi gr8,-1,gr8 - test_icc 0 1 1 0 icc0 - test_gr_limmed 0x8000,0x0001,gr8 - - set_gr_immed -2048,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - subi gr8,-2048,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_icc 0x0e,0 ; Set mask opposite of expected - subi gr8,-1,gr8 - test_icc 1 1 1 0 icc0 - test_gr_immed 1,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subicc.cgs b/sim/testsuite/sim/frv/subicc.cgs deleted file mode 100644 index b2296ee..0000000 --- a/sim/testsuite/sim/frv/subicc.cgs +++ /dev/null @@ -1,56 +0,0 @@ -# frv testcase for subicc $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global subicc -subicc: - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - subicc gr8,1,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - subicc gr8,1,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x1ff,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - subicc gr8,0x1ff,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Set mask opposite of expected - subicc gr8,1,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - subicc gr8,-1,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x06,0 ; Set mask opposite of expected - subicc gr8,-1,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0x8000,0x0001,gr8 - - set_gr_immed -512,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - subicc gr8,-512,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x0e,0 ; Set mask opposite of expected - subicc gr8,-1,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 1,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subx.cgs b/sim/testsuite/sim/frv/subx.cgs deleted file mode 100644 index 4559a52..0000000 --- a/sim/testsuite/sim/frv/subx.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for subx $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global subx -subx: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry is off - subx gr8,gr7,gr8,icc0 - test_icc 1 1 1 0 icc0 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0c,0 ; Make sure carry is off - subx gr8,gr7,gr8,icc0 - test_icc 1 1 0 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_icc 0x0a,0 ; Make sure carry is off - subx gr8,gr8,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Make sure carry is off - subx gr8,gr7,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 3,gr8 - set_icc 0x0f,0 ; Make sure carry is on - subx gr8,gr7,gr8,icc0 - test_icc 1 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_immed 0,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Make sure carry is on - subx gr8,gr7,gr8,icc0 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0x7fff,0xfffe,gr7 - set_icc 0x0b,0 ; Make sure carry is on - subx gr8,gr7,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 0,gr7 - set_icc 0x07,0 ; Make sure carry is on - subx gr8,gr7,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subxcc.cgs b/sim/testsuite/sim/frv/subxcc.cgs deleted file mode 100644 index 713a2a7..0000000 --- a/sim/testsuite/sim/frv/subxcc.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for subxcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global subxcc -subxcc: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry is off - subxcc gr8,gr7,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0c,0 ; Make sure carry is off - subxcc gr8,gr7,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_icc 0x0a,0 ; Make sure carry is off - subxcc gr8,gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Make sure carry is off - subxcc gr8,gr7,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 3,gr8 - set_icc 0x0f,0 ; Make sure carry is on - subxcc gr8,gr7,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_immed 0,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Make sure carry is on - subxcc gr8,gr7,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0x7fff,0xfffe,gr7 - set_icc 0x0b,0 ; Make sure carry is on - subxcc gr8,gr7,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 0,gr7 - set_icc 0x07,0 ; Make sure carry is on - subxcc gr8,gr7,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subxi.cgs b/sim/testsuite/sim/frv/subxi.cgs deleted file mode 100644 index bbe8e4d..0000000 --- a/sim/testsuite/sim/frv/subxi.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for subxi $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global subxi -subxi: - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry is off - subxi gr8,1,gr8,icc0 - test_icc 1 1 1 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0c,0 ; Make sure carry is off - subxi gr8,1,gr8,icc0 - test_icc 1 1 0 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x1ff,gr8 - set_icc 0x0a,0 ; Make sure carry is off - subxi gr8,0x1ff,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Make sure carry is off - subxi gr8,1,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 3,gr8 - set_icc 0x0f,0 ; Make sure carry is on - subxi gr8,1,gr8,icc0 - test_icc 1 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Make sure carry is on - subxi gr8,0,gr8,icc0 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x200,gr8 - set_icc 0x0b,0 ; Make sure carry is on - subxi gr8,0x1ff,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_icc 0x07,0 ; Make sure carry is on - subxi gr8,0,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_icc 0x07,0 ; Make sure carry is on - subxi gr8,-512,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 510,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subxicc.cgs b/sim/testsuite/sim/frv/subxicc.cgs deleted file mode 100644 index 369cab9..0000000 --- a/sim/testsuite/sim/frv/subxicc.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for subxicc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global subxicc -subxicc: - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry is off - subxicc gr8,1,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0c,0 ; Make sure carry is off - subxicc gr8,1,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x1ff,gr8 - set_icc 0x0a,0 ; Make sure carry is off - subxicc gr8,0x1ff,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Make sure carry is off - subxicc gr8,1,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 3,gr8 - set_icc 0x0f,0 ; Make sure carry is on - subxicc gr8,1,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Make sure carry is on - subxicc gr8,0,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x200,gr8 - set_icc 0x0b,0 ; Make sure carry is on - subxicc gr8,0x1ff,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x07,0 ; Make sure carry is on - subxicc gr8,0,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_icc 0x07,0 ; Make sure carry is on - subxicc gr8,-512,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 510,gr8 - - pass diff --git a/sim/testsuite/sim/frv/swap.cgs b/sim/testsuite/sim/frv/swap.cgs deleted file mode 100644 index 1e22903..0000000 --- a/sim/testsuite/sim/frv/swap.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for swap @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global swap -swap: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - swap @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 0,gr7 - swap @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - swap @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xbeef,0xdead,gr20 - - pass diff --git a/sim/testsuite/sim/frv/swapi.cgs b/sim/testsuite/sim/frv/swapi.cgs deleted file mode 100644 index 4951bfa..0000000 --- a/sim/testsuite/sim/frv/swapi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for swapi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global swapi -swapi: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - swapi @(sp,-4),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - swapi @(sp,0),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - swapi @(sp,4),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xbeef,0xdead,gr20 - - pass diff --git a/sim/testsuite/sim/frv/tc.cgs b/sim/testsuite/sim/frv/tc.cgs deleted file mode 100644 index 116190b..0000000 --- a/sim/testsuite/sim/frv/tc.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tc $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tc -tc: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x6 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_icc 0xe 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/teq.cgs b/sim/testsuite/sim/frv/teq.cgs deleted file mode 100644 index 59c6091..0000000 --- a/sim/testsuite/sim/frv/teq.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for teq $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global teq -teq: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x2 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xa 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/testutils.inc b/sim/testsuite/sim/frv/testutils.inc deleted file mode 100644 index 8261b4fa..0000000 --- a/sim/testsuite/sim/frv/testutils.inc +++ /dev/null @@ -1,656 +0,0 @@ -# gr28-gr31, fr31, icc3, fcc3 are used as tmps. -# consider them call clobbered by these macros. - - .macro start - .data -failmsg: - .ascii "fail\n" -passmsg: - .ascii "pass\n" - .text - .global _start -_start: - ; enable data and insn caches in copy-back mode - ; Also enable all registers - or_spr_immed 0xc80003c0,hsr0 - and_spr_immed 0xfffff3ff,hsr0 - - ; turn on psr.nem, psr.cm, psr.ef, psr.em, psr.esr, - ; disable external interrupts - or_spr_immed 0x69f8,psr - - ; If fsr exists, enable all fp_exceptions except inexact - movsg psr,gr28 - srli gr28,28,gr28 - subicc gr28,0x2,gr0,icc3 ; is fr400? - beq icc3,0,nofsr0 - or_spr_immed 0x3d000000,fsr0 -nofsr0: - - ; Set the stack pointer - sethi.p 0x7,sp - setlo 0xfffc,sp ; TODO -- what's a good value for this? - - ; Set the TBR address - sethi.p 0xf,gr28 - setlo 0xf000,gr28 - movgs gr28,tbr ; TODO -- what's a good value for this? - - ; Go to user mode -- causes too many problems - ;and_spr_immed 0xfffffffb,psr - .endm - -; Set GR with another GR - .macro set_gr_gr src targ - addi \src,0,\targ - .endm - -; Set GR with immediate value - .macro set_gr_immed val reg - .if (\val >= -32768) && (\val <= 23767) - setlos \val,\reg - .else - setlo.p %lo(\val),\reg - sethi %hi(\val),\reg - .endif - .endm - - .macro set_gr_limmed valh vall reg - sethi.p \valh,\reg - setlo \vall,\reg - .endm - -; Set GR with address value - .macro set_gr_addr addr reg - sethi.p %hi(\addr),\reg - setlo %lo(\addr),\reg - .endm - -; Set GR with SPR - .macro set_gr_spr src targ - movsg \src,\targ - .endm - -; Set GR with a value from memory - .macro set_gr_mem addr reg - set_gr_addr \addr,gr28 - ldi @(gr28,0),\reg - .endm - -; Increment GR with immediate value - .macro inc_gr_immed val reg - .if (\val >= -2048) && (\val <= 2047) - addi \reg,\val,\reg - .else - set_gr_immed \val,gr28 - add \reg,gr28,\reg - .endif - .endm - -; AND GR with immediate value - .macro and_gr_immed val reg - .if (\val >= -2048) && (\val <= 2047) - andi \reg,\val,\reg - .else - set_gr_immed \val,gr28 - and \reg,gr28,\reg - .endif - .endm - -; OR GR with immediate value - .macro or_gr_immed val reg - .if (\val >= -2048) && (\val <= 2047) - ori \reg,\val,\reg - .else - set_gr_immed \val,gr28 - or \reg,gr28,\reg - .endif - .endm - -; Set FR with another FR - .macro set_fr_fr src targ - fmovs \src,\targ - .endm - -; Set FR with integer immediate value - .macro set_fr_iimmed valh vall reg - set_gr_limmed \valh,\vall,gr28 - movgf gr28,\reg - .endm - -; Set FR with integer immediate value - .macro set_fr_immed val reg - set_gr_immed \val,gr28 - movgf gr28,\reg - .endm - -; Set FR with a value from memory - .macro set_fr_mem addr reg - set_gr_addr \addr,gr28 - ldfi @(gr28,0),\reg - .endm - -; Set double FR with another double FR - .macro set_dfr_dfr src targ - fmovd \src,\targ - .endm - -; Set double FR with a value from memory - .macro set_dfr_mem addr reg - set_gr_addr \addr,gr28 - lddfi @(gr28,0),\reg - .endm - -; Set CPR with immediate value - .macro set_cpr_immed val reg - addi sp,-4,gr28 - set_gr_immed \val,gr29 - st gr29,@(gr28,gr0) - ldc @(gr28,gr0),\reg - .endm - - .macro set_cpr_limmed valh vall reg - addi sp,-4,gr28 - set_gr_limmed \valh,\vall,gr29 - st gr29,@(gr28,gr0) - ldc @(gr28,gr0),\reg - .endm - -; Set SPR with immediate value - .macro set_spr_immed val reg - set_gr_immed \val,gr28 - movgs gr28,\reg - .endm - - .macro set_spr_limmed valh vall reg - set_gr_limmed \valh,\vall,gr28 - movgs gr28,\reg - .endm - - .macro set_spr_addr addr reg - set_gr_addr \addr,gr28 - movgs gr28,\reg - .endm - -; increment SPR with immediate value - .macro inc_spr_immed val reg - movsg \reg,gr28 - inc_gr_immed \val,gr28 - movgs gr28,\reg - .endm - -; OR spr with immediate value - .macro or_spr_immed val reg - movsg \reg,gr28 - set_gr_immed \val,gr29 - or gr28,gr29,gr28 - movgs gr28,\reg - .endm - -; AND spr with immediate value - .macro and_spr_immed val reg - movsg \reg,gr28 - set_gr_immed \val,gr29 - and gr28,gr29,gr28 - movgs gr28,\reg - .endm - -; Set accumulator with immediate value - .macro set_acc_immed val reg - set_fr_immed \val,fr31 - mwtacc fr31,\reg - .endm - -; Set accumulator guard with immediate value - .macro set_accg_immed val reg - set_fr_immed \val,fr31 - mwtaccg fr31,\reg - .endm - -; Set memory with immediate value - .macro set_mem_immed val base - set_gr_immed \val,gr28 - sti gr28,@(\base,0) - .endm - - .macro set_mem_limmed valh vall base - set_gr_limmed \valh,\vall,gr28 - sti gr28,@(\base,0) - .endm - -; Set memory with GR value - .macro set_mem_gr reg addr - set_gr_addr \addr,gr28 - sti \reg,@(gr28,0) - .endm - -; Test the value of a general register against another general register - .macro test_gr_gr reg1 reg2 - subcc \reg1,\reg2,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - -; Test the value of an immediate against a general register - .macro test_gr_immed val reg - .if (\val >= -512) && (\val <= 511) - subicc \reg,\val,gr0,icc3 - .else - set_gr_immed \val,gr28 - subcc \reg,gr28,gr0,icc3 - .endif - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - - .macro test_gr_limmed valh vall reg - set_gr_limmed \valh,\vall,gr28 - subcc \reg,gr28,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - -; Test the value of an floating register against an integer immediate - .macro test_fr_limmed valh vall reg - movfg \reg,gr29 - set_gr_limmed \valh,\vall,gr28 - subcc gr29,gr28,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - - .macro test_fr_iimmed val reg - movfg \reg,gr29 - set_gr_immed \val,gr28 - subcc gr29,gr28,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - -; Test the value of a floating register against another floating point register - .macro test_fr_fr reg1 reg2 - fcmps \reg1,\reg2,fcc3 - fbeq fcc3,0,test_gr\@ - fail -test_gr\@: - .endm - -; Test the value of a double floating register against another -; double floating point register - .macro test_dfr_dfr reg1 reg2 - fcmpd \reg1,\reg2,fcc3 - fbeq fcc3,0,test_gr\@ - fail -test_gr\@: - .endm - -; Test the value of a special purpose register against an integer immediate - .macro test_spr_immed val reg - movsg \reg,gr29 - set_gr_immed \val,gr28 - subcc gr29,gr28,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - - .macro test_spr_limmed valh vall reg - movsg \reg,gr29 - set_gr_limmed \valh,\vall,gr28 - subcc gr29,gr28,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - - .macro test_spr_gr spr gr - movsg \spr,gr28 - test_gr_gr \gr,gr28 - .endm - - .macro test_spr_addr addr reg - movsg \reg,gr29 - set_gr_addr \addr,gr28 - test_gr_gr gr28,gr29 - .endm - -; Test spr bits masked and shifted against the given value - .macro test_spr_bits mask,shift,val,reg - movsg \reg,gr28 - set_gr_immed \mask,gr29 - and gr28,gr29,gr28 - srli gr28,\shift,gr29 - test_gr_immed \val,gr29 - .endm - - -; Test the value of an accumulator against an integer immediate - .macro test_acc_immed val reg - mrdacc \reg,fr31 - test_fr_iimmed \val,fr31 - .endm - -; Test the value of an accumulator against an integer immediate - .macro test_acc_limmed valh vall reg - mrdacc \reg,fr31 - test_fr_limmed \valh,\vall,fr31 - .endm - -; Test the value of an accumulator guard against an integer immediate - .macro test_accg_immed val reg - mrdaccg \reg,fr31 - test_fr_iimmed \val,fr31 - .endm - -; Test CPR agains an immediate value - .macro test_cpr_limmed valh vall reg - addi sp,-4,gr31 - stc \reg,@(gr31,gr0) - test_mem_limmed \valh,\vall,gr31 - .endm - -; Test the value of an immediate against memory - .macro test_mem_immed val base - ldi @(\base,0),gr29 - .if (\val >= -512) && (\val <= 511) - subicc gr29,\val,gr0,icc3 - .else - set_gr_immed \val,gr28 - subcc gr29,gr28,gr0,icc3 - .endif - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - - .macro test_mem_limmed valh vall base - ldi @(\base,0),gr29 - set_gr_limmed \valh,\vall,gr28 - subcc gr29,gr28,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - -; Set an integer condition code - .macro set_icc mask iccno - set_gr_immed 4,gr29 - smuli gr29,\iccno,gr30 - addi gr31,16,gr31 - set_gr_immed 0xf,gr28 - sll gr28,gr31,gr28 - not gr28,gr28 - movsg ccr,gr29 - and gr28,gr29,gr29 - set_gr_immed \mask,gr28 - sll gr28,gr31,gr28 - or gr28,gr29,gr29 - movgs gr29,ccr - .endm -; started here -; Test the condition codes - .macro test_icc N Z V C iccno - .if (\N == 1) - bp \iccno,0,fail\@ - .else - bn \iccno,0,fail\@ - .endif - .if (\Z == 1) - bne \iccno,0,fail\@ - .else - beq \iccno,0,fail\@ - .endif - .if (\V == 1) - bnv \iccno,0,fail\@ - .else - bv \iccno,0,fail\@ - .endif - .if (\C == 1) - bnc \iccno,0,fail\@ - .else - bc \iccno,0,fail\@ - .endif - bra test_cc\@ -fail\@: - fail -test_cc\@: - .endm - -; Set an floating point condition code - .macro set_fcc mask fccno - set_gr_immed 4,gr29 - smuli gr29,\fccno,gr30 - set_gr_immed 0xf,gr28 - sll gr28,gr31,gr28 - not gr28,gr28 - movsg ccr,gr29 - and gr28,gr29,gr29 - set_gr_immed \mask,gr28 - sll gr28,gr31,gr28 - or gr28,gr29,gr29 - movgs gr29,ccr - .endm - -; Test the condition codes - .macro test_fcc val fccno - set_gr_immed 4,gr29 - smuli gr29,\fccno,gr30 - movsg ccr,gr29 - srl gr29,gr31,gr29 - andi gr29,0xf,gr29 - test_gr_immed \val,gr29 - .endm - -; Set PSR.ET - .macro set_psr_et val - movsg psr,gr28 - .if (\val == 1) - ori gr28,1,gr28 ; Turn on SPR.ET - .else - andi gr28,0xfffffffe,gr28 ; Turn off SPR.ET - .endif - movgs gr28,psr - .endm - -; Floating point constants - .macro float_constants -f0: .float 0.0 -f1: .float 1.0 -f2: .float 2.0 -f3: .float 3.0 -f6: .float 6.0 -f9: .float 9.0 -fn0: .float -0.0 -fn1: .float -1.0 -finf: .long 0x7f800000 -fninf: .long 0xff800000 -fmax: .long 0x7f7fffff -fmin: .long 0xff7fffff -feps: .long 0x00400000 -fneps: .long 0x80400000 -fnan1: .long 0x7fc00000 -fnan2: .long 0x7f800001 - .endm - - .macro double_constants -d0: .double 0.0 -d1: .double 1.0 -d2: .double 2.0 -d3: .double 3.0 -d6: .double 6.0 -d9: .double 9.0 -dn0: .double -0.0 -dn1: .double -1.0 -dinf: .long 0x7ff00000 - .long 0x00000000 -dninf: .long 0xfff00000 - .long 0x00000000 -dmax: .long 0x7fefffff - .long 0xffffffff -dmin: .long 0xffefffff - .long 0xffffffff -deps: .long 0x00080000 - .long 0x00000000 -dneps: .long 0x80080000 - .long 0x00000000 -dnan1: .long 0x7ff80000 - .long 0x00000000 -dnan2: .long 0x7ff00000 - .long 0x00000001 - .endm - -; Load floating point constants - .macro load_float_constants - set_fr_mem fninf,fr0 - set_fr_mem fmin,fr4 - set_fr_mem fn1,fr8 - set_fr_mem fneps,fr12 - set_fr_mem fn0,fr16 - set_fr_mem f0,fr20 - set_fr_mem feps,fr24 - set_fr_mem f1,fr28 - set_fr_mem f2,fr32 - set_fr_mem f3,fr36 - set_fr_mem f6,fr40 - set_fr_mem f9,fr44 - set_fr_mem fmax,fr48 - set_fr_mem finf,fr52 - set_fr_mem fnan1,fr56 - set_fr_mem fnan2,fr60 - .endm - - .macro load_float_constants1 - set_fr_mem fninf,fr1 - set_fr_mem fmin,fr5 - set_fr_mem fn1,fr9 - set_fr_mem fneps,fr13 - set_fr_mem fn0,fr17 - set_fr_mem f0,fr21 - set_fr_mem feps,fr25 - set_fr_mem f1,fr29 - set_fr_mem f2,fr33 - set_fr_mem f3,fr37 - set_fr_mem f6,fr41 - set_fr_mem f9,fr45 - set_fr_mem fmax,fr49 - set_fr_mem finf,fr53 - set_fr_mem fnan1,fr57 - set_fr_mem fnan2,fr61 - .endm - - .macro load_float_constants2 - set_fr_mem fninf,fr2 - set_fr_mem fmin,fr6 - set_fr_mem fn1,fr10 - set_fr_mem fneps,fr14 - set_fr_mem fn0,fr18 - set_fr_mem f0,fr22 - set_fr_mem feps,fr26 - set_fr_mem f1,fr30 - set_fr_mem f2,fr34 - set_fr_mem f3,fr38 - set_fr_mem f6,fr42 - set_fr_mem f9,fr46 - set_fr_mem fmax,fr50 - set_fr_mem finf,fr54 - set_fr_mem fnan1,fr58 - set_fr_mem fnan2,fr62 - .endm - - .macro load_float_constants3 - set_fr_mem fninf,fr3 - set_fr_mem fmin,fr7 - set_fr_mem fn1,fr11 - set_fr_mem fneps,fr15 - set_fr_mem fn0,fr19 - set_fr_mem f0,fr23 - set_fr_mem feps,fr27 - set_fr_mem f1,fr31 - set_fr_mem f2,fr35 - set_fr_mem f3,fr39 - set_fr_mem f6,fr43 - set_fr_mem f9,fr47 - set_fr_mem fmax,fr51 - set_fr_mem finf,fr55 - set_fr_mem fnan1,fr59 - set_fr_mem fnan2,fr63 - .endm - - .macro load_double_constants - set_dfr_mem dninf,fr0 - set_dfr_mem dmin,fr4 - set_dfr_mem dn1,fr8 - set_dfr_mem dneps,fr12 - set_dfr_mem dn0,fr16 - set_dfr_mem d0,fr20 - set_dfr_mem deps,fr24 - set_dfr_mem d1,fr28 - set_dfr_mem d2,fr32 - set_dfr_mem d3,fr36 - set_dfr_mem d6,fr40 - set_dfr_mem d9,fr44 - set_dfr_mem dmax,fr48 - set_dfr_mem dinf,fr52 - set_dfr_mem dnan1,fr56 - set_dfr_mem dnan2,fr60 - .endm - -; Lock the insn cache at the given address - .macro lock_insn_cache address - icpl \address,gr0,1 - .endm - -; Lock the data cache at the given address - .macro lock_data_cache address - dcpl \address,gr0,1 - .endm - -; Invalidate the data cache at the given address - .macro invalidate_data_cache address - dci @(\address,gr0) - .endm - -; Flush the data cache at the given address - .macro flush_data_cache address - dcf @(\address,gr0) - .endm - -; Write a bctrlr 0,0 insn at the address contained in the given register - .macro set_bctrlr_0_0 address - set_mem_immed 0x80382000,\address ; bctrlr 0,0 - flush_data_cache \address - .endm - -; Exit with return code - .macro exit rc - setlos #1,gr7 - set_gr_immed \rc,gr8 - tira gr0,#0 - .endm - -; Pass the test case - .macro pass -pass\@: - setlos.p #5,gr10 - setlos #1,gr8 - setlos #5,gr7 - set_gr_addr passmsg,gr9 - tira gr0,#0 - exit #0 - .endm - -; Fail the testcase - .macro fail -fail\@: - setlos.p #5,gr10 - setlos #1,gr8 - setlos #5,gr7 - set_gr_addr failmsg,gr9 - tira gr0,#0 - exit #1 - .endm diff --git a/sim/testsuite/sim/frv/tge.cgs b/sim/testsuite/sim/frv/tge.cgs deleted file mode 100644 index 3e12d92..0000000 --- a/sim/testsuite/sim/frv/tge.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tge $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tge -tge: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x6 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x8 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tgt.cgs b/sim/testsuite/sim/frv/tgt.cgs deleted file mode 100644 index 7e01330..0000000 --- a/sim/testsuite/sim/frv/tgt.cgs +++ /dev/null @@ -1,93 +0,0 @@ -# frv testcase for tgt $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tgt -tgt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x4 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x8 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/thi.cgs b/sim/testsuite/sim/frv/thi.cgs deleted file mode 100644 index 36cc923..0000000 --- a/sim/testsuite/sim/frv/thi.cgs +++ /dev/null @@ -1,93 +0,0 @@ -# frv testcase for thi $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global thi -thi: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_spr_addr bad,lr - set_icc 0x1 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x3 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x4 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x9 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_spr_addr bad,lr - set_icc 0xb 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xc 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tic.cgs b/sim/testsuite/sim/frv/tic.cgs deleted file mode 100644 index 8c746f5..0000000 --- a/sim/testsuite/sim/frv/tic.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tic $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tic -tic: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x6 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_icc 0xe 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tieq.cgs b/sim/testsuite/sim/frv/tieq.cgs deleted file mode 100644 index 5dfc0e6..0000000 --- a/sim/testsuite/sim/frv/tieq.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tieq $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tieq -tieq: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x2 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr bad,lr - set_icc 0x8 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xa 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tige.cgs b/sim/testsuite/sim/frv/tige.cgs deleted file mode 100644 index cde3ac8..0000000 --- a/sim/testsuite/sim/frv/tige.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tige $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tige -tige: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr bad,lr - set_icc 0x6 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x8 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tigt.cgs b/sim/testsuite/sim/frv/tigt.cgs deleted file mode 100644 index 163d92f..0000000 --- a/sim/testsuite/sim/frv/tigt.cgs +++ /dev/null @@ -1,92 +0,0 @@ -# frv testcase for tigt $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tigt -tigt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x4 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x8 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tihi.cgs b/sim/testsuite/sim/frv/tihi.cgs deleted file mode 100644 index e564fc2..0000000 --- a/sim/testsuite/sim/frv/tihi.cgs +++ /dev/null @@ -1,92 +0,0 @@ -# frv testcase for tihi $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tihi -tihi: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_spr_addr bad,lr - set_icc 0x1 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x3 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x4 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x9 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_spr_addr bad,lr - set_icc 0xb 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xc 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tile.cgs b/sim/testsuite/sim/frv/tile.cgs deleted file mode 100644 index 7f5ef2a..0000000 --- a/sim/testsuite/sim/frv/tile.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for tile $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tile -tile: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tils.cgs b/sim/testsuite/sim/frv/tils.cgs deleted file mode 100644 index 5713de5..0000000 --- a/sim/testsuite/sim/frv/tils.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for tils $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tils -tils: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tilt.cgs b/sim/testsuite/sim/frv/tilt.cgs deleted file mode 100644 index 4d596b0..0000000 --- a/sim/testsuite/sim/frv/tilt.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tilt $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tilt -tilt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_icc 0xe 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tin.cgs b/sim/testsuite/sim/frv/tin.cgs deleted file mode 100644 index f55c921..0000000 --- a/sim/testsuite/sim/frv/tin.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tin $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tin -tin: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x2 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x4 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tinc.cgs b/sim/testsuite/sim/frv/tinc.cgs deleted file mode 100644 index 8e99e31..0000000 --- a/sim/testsuite/sim/frv/tinc.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tinc $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tinc -tinc: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_spr_addr bad,lr - set_icc 0x1 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x3 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x5 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x7 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x9 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_spr_addr bad,lr - set_icc 0xb 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_spr_addr bad,lr - set_icc 0xd 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_spr_addr bad,lr - set_icc 0xf 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tine.cgs b/sim/testsuite/sim/frv/tine.cgs deleted file mode 100644 index d7e8b00..0000000 --- a/sim/testsuite/sim/frv/tine.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tine $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tine -tine: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tino.cgs b/sim/testsuite/sim/frv/tino.cgs deleted file mode 100644 index 65a2d6d..0000000 --- a/sim/testsuite/sim/frv/tino.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for tino -# mach: all - - .include "testutils.inc" - - start - - .global tinev -tinev: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_gr_immed 0,gr7 - - set_icc 0x0 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x1 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x2 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x3 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x4 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x5 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x6 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x7 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x8 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x9 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0xa 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0xb 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0xc 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0xd 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0xe 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0xf 0 - tino ; should branch to tbr + (128 + 4)*16 - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tinv.cgs b/sim/testsuite/sim/frv/tinv.cgs deleted file mode 100644 index 7ec34a4..0000000 --- a/sim/testsuite/sim/frv/tinv.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tinv $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tinv -tinv: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x6 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_icc 0xe 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tip.cgs b/sim/testsuite/sim/frv/tip.cgs deleted file mode 100644 index 8353422..0000000 --- a/sim/testsuite/sim/frv/tip.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tip $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tip -tip: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xa 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xc 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tira.cgs b/sim/testsuite/sim/frv/tira.cgs deleted file mode 100644 index bd3139e..0000000 --- a/sim/testsuite/sim/frv/tira.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for tira $GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tira -tira: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass diff --git a/sim/testsuite/sim/frv/tiv.cgs b/sim/testsuite/sim/frv/tiv.cgs deleted file mode 100644 index 84a2576..0000000 --- a/sim/testsuite/sim/frv/tiv.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tiv $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tiv -tiv: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tle.cgs b/sim/testsuite/sim/frv/tle.cgs deleted file mode 100644 index 1322821..0000000 --- a/sim/testsuite/sim/frv/tle.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for tle $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tle -tle: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tls.cgs b/sim/testsuite/sim/frv/tls.cgs deleted file mode 100644 index 708e617..0000000 --- a/sim/testsuite/sim/frv/tls.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for tls $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tls -tls: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tlt.cgs b/sim/testsuite/sim/frv/tlt.cgs deleted file mode 100644 index 12ee05b..0000000 --- a/sim/testsuite/sim/frv/tlt.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tlt $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tlt -tlt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_icc 0xe 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tn.cgs b/sim/testsuite/sim/frv/tn.cgs deleted file mode 100644 index 05b0424..0000000 --- a/sim/testsuite/sim/frv/tn.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tn $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tn -tn: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x2 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x4 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tnc.cgs b/sim/testsuite/sim/frv/tnc.cgs deleted file mode 100644 index 808db3c..0000000 --- a/sim/testsuite/sim/frv/tnc.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tnc $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tnc -tnc: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_spr_addr bad,lr - set_icc 0x1 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x3 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x5 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x7 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x9 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_spr_addr bad,lr - set_icc 0xb 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_spr_addr bad,lr - set_icc 0xd 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_spr_addr bad,lr - set_icc 0xf 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tne.cgs b/sim/testsuite/sim/frv/tne.cgs deleted file mode 100644 index 880188d..0000000 --- a/sim/testsuite/sim/frv/tne.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tne $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tne -tne: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tno.cgs b/sim/testsuite/sim/frv/tno.cgs deleted file mode 100644 index df49969..0000000 --- a/sim/testsuite/sim/frv/tno.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# frv testcase for tno -# mach: all - - .include "testutils.inc" - - start - - .global tno -tno: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_icc 0x0 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x1 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x2 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x3 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x4 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x5 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x6 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x7 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x8 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x9 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0xa 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0xb 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0xc 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0xd 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0xe 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0xf 0 - tno ; should branch to tbr + (128 + 4)*16 - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tnv.cgs b/sim/testsuite/sim/frv/tnv.cgs deleted file mode 100644 index d7f9241..0000000 --- a/sim/testsuite/sim/frv/tnv.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tnv $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tnv -tnv: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x6 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_icc 0xe 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tp.cgs b/sim/testsuite/sim/frv/tp.cgs deleted file mode 100644 index 2709e31..0000000 --- a/sim/testsuite/sim/frv/tp.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tp $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tp -tp: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xa 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xc 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tra.cgs b/sim/testsuite/sim/frv/tra.cgs deleted file mode 100644 index 368c83a..0000000 --- a/sim/testsuite/sim/frv/tra.cgs +++ /dev/null @@ -1,117 +0,0 @@ -# frv testcase for tra $GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tra -tra: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 -bad0: - fail -ok0: - test_spr_addr bad0,pcsr - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass diff --git a/sim/testsuite/sim/frv/tv.cgs b/sim/testsuite/sim/frv/tv.cgs deleted file mode 100644 index d173f29..0000000 --- a/sim/testsuite/sim/frv/tv.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tv $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tv -tv: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/udiv.cgs b/sim/testsuite/sim/frv/udiv.cgs deleted file mode 100644 index 35cfa8c..0000000 --- a/sim/testsuite/sim/frv/udiv.cgs +++ /dev/null @@ -1,48 +0,0 @@ -# frv testcase for udiv $GRi,$GRj,$GRk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global udiv -udiv: - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - udiv gr3,gr2,gr3 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x00000004,gr3 - - ; example 1 from udiv in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - udiv gr3,gr2,gr3 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_immed 0x000000e0,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr - set_gr_addr e1,gr17 -e1: udiv gr1,gr0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/udivi.cgs b/sim/testsuite/sim/frv/udivi.cgs deleted file mode 100644 index 6a50590..0000000 --- a/sim/testsuite/sim/frv/udivi.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for udivi $GRi,$s12,$GRk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global udivi -udivi: - ; simple division 12 / 3 - set_gr_immed 0x0000000c,gr3 - udivi gr3,3,gr3 - test_gr_immed 0x00000004,gr3 - - ; random example - set_gr_limmed 0xfedc,0xba98,gr3 - udivi gr3,0x7ff,gr3 - test_gr_limmed 0x001f,0xdf93,gr3 - - ; random example - set_gr_limmed 0xffff,0xffff,gr3 - udivi gr3,-2048,gr3 - test_gr_immed 1,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr - set_gr_addr e1,gr17 -e1: udivi gr1,0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/umul.cgs b/sim/testsuite/sim/frv/umul.cgs deleted file mode 100644 index 6c61221..0000000 --- a/sim/testsuite/sim/frv/umul.cgs +++ /dev/null @@ -1,76 +0,0 @@ -# frv testcase for umul $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global umul -umul: - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result - set_gr_immed 2,gr8 - umul gr7,gr8,gr8 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - umul gr7,gr8,gr8 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - umul gr7,gr8,gr8 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xffff,0xffff,gr7 ; max positive result - set_gr_limmed 0xffff,0xffff,gr8 - umul gr7,gr8,gr8 - test_gr_limmed 0xffff,0xfffe,gr8 - test_gr_immed 1,gr9 - - pass diff --git a/sim/testsuite/sim/frv/umulcc.cgs b/sim/testsuite/sim/frv/umulcc.cgs deleted file mode 100644 index c2b5cff..0000000 --- a/sim/testsuite/sim/frv/umulcc.cgs +++ /dev/null @@ -1,98 +0,0 @@ -# frv testcase for umulcc $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global umulcc -umulcc: - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result - set_gr_immed 2,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 1,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xffff,0xffff,gr7 ; max positive result - set_gr_limmed 0xffff,0xffff,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xfffe,gr8 - test_gr_immed 1,gr9 - - pass diff --git a/sim/testsuite/sim/frv/umuli.cgs b/sim/testsuite/sim/frv/umuli.cgs deleted file mode 100644 index 6f1b9c1..0000000 --- a/sim/testsuite/sim/frv/umuli.cgs +++ /dev/null @@ -1,87 +0,0 @@ -# frv testcase for umuli $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global umuli -umuli: - set_gr_immed 3,gr7 ; multiply small numbers - set_icc 0x0f,0 ; Set mask opposite of expected - umuli gr7,2,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_icc 0x0e,0 ; Set mask opposite of expected - umuli gr7,2,gr8 - test_icc 1 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_icc 0x0f,0 ; Set mask opposite of expected - umuli gr7,1,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_icc 0x0b,0 ; Set mask opposite of expected - umuli gr7,2,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_icc 0x0a,0 ; Set mask opposite of expected - umuli gr7,0,gr8 - test_icc 1 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_icc 0x0f,0 ; Set mask opposite of expected - umuli gr7,2,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_icc 0x0e,0 ; Set mask opposite of expected - umuli gr7,2,gr8 - test_icc 1 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result - set_icc 0x09,0 ; Set mask opposite of expected - umuli gr7,2,gr8 - test_icc 1 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_icc 0x0d,0 ; Set mask opposite of expected - umuli gr7,0x7ff,gr8 - test_icc 1 1 0 1 icc0 - test_gr_immed 0x3ff,gr8 - test_gr_limmed 0x7fff,0xf801,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_icc 0x09,0 ; Set mask opposite of expected - umuli gr7,-2048,gr8 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0x7fff,0xfc00,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0xffff,0xffff,gr7 ; max positive result - set_icc 0x05,0 ; Set mask opposite of expected - umuli gr7,-1,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xffff,0xfffe,gr8 - test_gr_immed 1,gr9 - - pass diff --git a/sim/testsuite/sim/frv/umulicc.cgs b/sim/testsuite/sim/frv/umulicc.cgs deleted file mode 100644 index 0d0d0c1..0000000 --- a/sim/testsuite/sim/frv/umulicc.cgs +++ /dev/null @@ -1,87 +0,0 @@ -# frv testcase for umulicc $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global umulicc -umulicc: - set_gr_immed 3,gr7 ; multiply small numbers - set_icc 0x0f,0 ; Set mask opposite of expected - umulicc gr7,2,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_icc 0x0e,0 ; Set mask opposite of expected - umulicc gr7,2,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_icc 0x0f,0 ; Set mask opposite of expected - umulicc gr7,1,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_icc 0x0b,0 ; Set mask opposite of expected - umulicc gr7,2,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_icc 0x0a,0 ; Set mask opposite of expected - umulicc gr7,0,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_icc 0x0f,0 ; Set mask opposite of expected - umulicc gr7,2,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_icc 0x0e,0 ; Set mask opposite of expected - umulicc gr7,2,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result - set_icc 0x09,0 ; Set mask opposite of expected - umulicc gr7,2,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_icc 0x0d,0 ; Set mask opposite of expected - umulicc gr7,0x1ff,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0xff,gr8 - test_gr_limmed 0x7fff,0xfe01,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_icc 0x09,0 ; Set mask opposite of expected - umulicc gr7,-512,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0x7fff,0xff00,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0xffff,0xffff,gr7 ; max positive result - set_icc 0x05,0 ; Set mask opposite of expected - umulicc gr7,-1,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xfffe,gr8 - test_gr_immed 1,gr9 - - pass diff --git a/sim/testsuite/sim/frv/xor.cgs b/sim/testsuite/sim/frv/xor.cgs deleted file mode 100644 index 97310e4..0000000 --- a/sim/testsuite/sim/frv/xor.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for xor $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global xor -xor: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - xor gr7,gr8,gr8 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - xor gr7,gr8,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - xor gr7,gr8,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - xor gr7,gr8,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/xorcc.cgs b/sim/testsuite/sim/frv/xorcc.cgs deleted file mode 100644 index 9516b78..0000000 --- a/sim/testsuite/sim/frv/xorcc.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for xorcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global xorcc -xorcc: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - xorcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - xorcc gr7,gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - xorcc gr7,gr8,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - xorcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/xorcr.cgs b/sim/testsuite/sim/frv/xorcr.cgs deleted file mode 100644 index bcb153b..0000000 --- a/sim/testsuite/sim/frv/xorcr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for xorcr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global xorcr -xorcr: - set_spr_immed 0x1b1b,cccr - xorcr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc7,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc7,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc6,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc6,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc5,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc5,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc5,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - xorcr cc5,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - xorcr cc4,cc7,cc3 - test_spr_immed 0x1bdb,cccr - - xorcr cc4,cc6,cc3 - test_spr_immed 0x1bdb,cccr - - xorcr cc4,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - xorcr cc4,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - pass diff --git a/sim/testsuite/sim/frv/xori.cgs b/sim/testsuite/sim/frv/xori.cgs deleted file mode 100644 index ed26660..0000000 --- a/sim/testsuite/sim/frv/xori.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# frv testcase for xori $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global xori -xori: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x07,0 ; Set mask opposite of expected - xori gr7,0x555,gr8 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xaaaa,0xafff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - xori gr7,0,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x0b,0 ; Set mask opposite of expected - xori gr7,0x2aa,gr8 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xaaaa,0xa800,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_icc 0x05,0 ; Set mask opposite of expected - xori gr7,-273,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x2152,0xfeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/xoricc.cgs b/sim/testsuite/sim/frv/xoricc.cgs deleted file mode 100644 index b473620..0000000 --- a/sim/testsuite/sim/frv/xoricc.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# frv testcase for xoricc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global xoricc -xoricc: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x07,0 ; Set mask opposite of expected - xoricc gr7,0x155,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xaaaa,0xabff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - xoricc gr7,0,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - xoricc gr7,0xaa,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xaaaa,0xaa00,gr8 - - set_gr_limmed 0xdead,0xb000,gr7 - set_icc 0x0d,0 ; Set mask opposite of expected - xoricc gr7,-273,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0x2152,0x4eef,gr8 - - pass diff --git a/sim/testsuite/sim/ft32/ChangeLog b/sim/testsuite/sim/ft32/ChangeLog deleted file mode 100644 index cb1d2f4..0000000 --- a/sim/testsuite/sim/ft32/ChangeLog +++ /dev/null @@ -1,8 +0,0 @@ -2015-10-12 James Bowman - - * basic.s: Add test for memory size link parameters. - Add test for program memory write port. - -2015-02-28 James Bowman - - * basic.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/sim/ft32/allinsn.exp b/sim/testsuite/sim/ft32/allinsn.exp deleted file mode 100644 index 730b422..0000000 --- a/sim/testsuite/sim/ft32/allinsn.exp +++ /dev/null @@ -1,15 +0,0 @@ -# ft32 simulator testsuite - -if [istarget ft32-*] { - # all machines - set all_machs "ft32" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/ft32/basic.s b/sim/testsuite/sim/ft32/basic.s deleted file mode 100644 index 62977c8..0000000 --- a/sim/testsuite/sim/ft32/basic.s +++ /dev/null @@ -1,899 +0,0 @@ -# check that basic insns work. -# mach: ft32 - -.include "testutils.inc" - - start - - ldk $r0,__PMSIZE - EXPECT $r0,0x00040000 - ldk $r0,__RAMSIZE - EXPECT $r0,0x00010000 - - ldk $r4,10 - add $r4,$r4,23 - EXPECT $r4,33 - -# lda, sta - .data -tmp: .long 0 - .text - - xor.l $r0,$r0,$r0 - EXPECT $r0,0x00000000 - xor.l $r0,$r0,$r0 - add.l $r0,$r0,1 - EXPECT $r0,0x00000001 - - ldk.l $r0,0x4567 - EXPECT $r0,0x00004567 - - lpm.l $r0,k_12345678 - EXPECT $r0,0x12345678 - - sta.l tmp,$r0 - lda.l $r1,tmp - EXPECT $r1,0x12345678 - - lda.b $r1,tmp - EXPECT $r1,0x00000078 - - lda.b $r1,tmp+1 - EXPECT $r1,0x00000056 - - lda.b $r1,tmp+2 - EXPECT $r1,0x00000034 - - lda.b $r1,tmp+3 - EXPECT $r1,0x00000012 - - sta.b tmp+1,$r0 - lda.l $r1,tmp+0 - EXPECT $r1,0x12347878 - -# immediate - ldk.l $r1,12 - add.l $r1,$r1,4 - EXPECT $r1,0x00000010 - add.l $r1,$r1,0x1ff - EXPECT $r1,0x0000020f - add.l $r1,$r1,-0x200 - EXPECT $r1,0x0000000f - -# addk - xor.l $r1,$r0,$r0 - add.l $r2,$r1,127 - EXPECT $r2,0x0000007f - - add.l $r2,$r2,127 - EXPECT $r2,0x000000fe - - add.l $r2,$r2,-127 - EXPECT $r2,0x0000007f - - add.l $r2,$r2,-128 - EXPECT $r2,0xffffffff - - add.l $r2,$r2,1 - EXPECT $r2,0x00000000 - -# mul - ldk.l $r1,100 - ldk.l $r2,77 - mul.l $r3,$r1,$r2 - EXPECT $r3,0x00001e14 - - # 0x12345678 ** 2 = 0x14b66dc1df4d840L - mul.l $r3,$r0,$r0 - EXPECT $r3,0x1df4d840 - muluh.l $r3,$r0,$r0 - EXPECT $r3,0x014b66dc - -# push and pop - push.l $r0 - EXPECT $sp,0x0000fffc - ldi.l $r3,$sp,0 - EXPECT $r3,0x12345678 - - pop.l $r4 - EXPECT $sp,0x00000000 - EXPECT $r4,0x12345678 - - ldk.l $r1,0x1111 - push.l $r1 - ldk.l $r1,0x2222 - push.l $r1 - ldk.l $r1,0x3333 - push.l $r1 - ldk.l $r1,0x4444 - push.l $r1 - EXPECT $sp,0x0000fff0 - pop.l $r1 - EXPECT $r1,0x00004444 - pop.l $r1 - EXPECT $r1,0x00003333 - pop.l $r1 - EXPECT $r1,0x00002222 - pop.l $r1 - EXPECT $r1,0x00001111 - -# push and pop with $sp changes - ldk.l $r1,0xa111 - push.l $r1 - sub.l $sp,$sp,4 - ldk.l $r1,0xa222 - push.l $r1 - add.l $sp,$sp,-36 - add.l $sp,$sp,36 - pop.l $r1 - EXPECT $r1,0x0000a222 - add.l $sp,$sp,4 - pop.l $r1 - EXPECT $r1,0x0000a111 - -# sti - ldk.l $r2,80 - EXPECT $r2,0x00000050 - sti.l $r2,0,$r0 - lda.l $r1,80 - EXPECT $r1,0x12345678 - - ldk.l $r3,0xF0 - sti.b $r2,0,$r3 - lda.l $r1,80 - EXPECT $r1,0x123456f0 - - add.l $r2,$r2,1 - sti.l $r2,0,$r0 - sti.b $r2,0,$r3 - lda.l $r1,80 - EXPECT $r1,0x1234f078 - - add.l $r2,$r2,1 - sti.l $r2,0,$r0 - sti.b $r2,0,$r3 - lda.l $r1,80 - EXPECT $r1,0x12f05678 - - add.l $r2,$r2,1 - sti.l $r2,0,$r0 - sti.b $r2,0,$r3 - lda.l $r1,80 - EXPECT $r1,0xf0345678 - - ldk.l $r2,80 - sti.l $r2,0,$r0 - ldk.s $r3,0xbeef - sti.s $r2,0,$r3 - lda.l $r1,80 - EXPECT $r1,0x1234beef - add.l $r2,$r2,2 - sti.s $r2,0,$r3 - lda.l $r1,80 - EXPECT $r1,0xbeefbeef - -# lpmi - - ldk.l $r1,k_12345678 - lpmi.l $r2,$r1,0 - EXPECT $r2,0x12345678 - - lpmi.b $r2,$r1,0 - EXPECT $r2,0x00000078 - - add.l $r1,$r1,1 - lpmi.b $r2,$r1,0 - EXPECT $r2,0x00000056 - - add.l $r1,$r1,1 - lpmi.b $r2,$r1,0 - EXPECT $r2,0x00000034 - - add.l $r1,$r1,1 - lpmi.b $r2,$r1,0 - EXPECT $r2,0x00000012 - - lpmi.l $r2,$r1,4 - EXPECT $r2,0xabcdef01 - - lpmi.l $r2,$r1,-4 - EXPECT $r2,0x10111213 - - lpmi.b $r2,$r1,-4 - EXPECT $r2,0x00000010 - - ldk.l $r1,k_12345678 - lpmi.s $r2,$r1,0 - EXPECT $r2,0x00005678 - lpmi.s $r2,$r1,2 - EXPECT $r2,0x00001234 - lpmi.b $r2,$r1,6 - EXPECT $r2,0x000000cd - lpmi.b $r2,$r1,7 - EXPECT $r2,0x000000ab - lpmi.b $r2,$r1,-1 - EXPECT $r2,0x00000010 - lpmi.s $r2,$r1,-2 - EXPECT $r2,0x00001011 - - ldk.l $r1,k_12345678-127 - lpmi.b $r2,$r1,127 - EXPECT $r2,0x00000078 - - ldk.l $r1,k_12345678+128 - lpmi.b $r2,$r1,-128 - EXPECT $r2,0x00000078 - -# shifts - - lpm.l $r0,k_12345678 - ldk.l $r2,4 - ashl.l $r1,$r0,$r2 - EXPECT $r1,0x23456780 - lshr.l $r1,$r0,$r2 - EXPECT $r1,0x01234567 - ashr.l $r1,$r0,$r2 - EXPECT $r1,0x01234567 - - lpm.l $r0,k_abcdef01 - ashl.l $r1,$r0,$r2 - EXPECT $r1,0xbcdef010 - lshr.l $r1,$r0,$r2 - EXPECT $r1,0x0abcdef0 - ashr.l $r1,$r0,$r2 - EXPECT $r1,0xfabcdef0 - -# rotate right - - lpm.l $r0,k_12345678 - ror.l $r1,$r0,0 - EXPECT $r1,0x12345678 - ror.l $r1,$r0,12 - EXPECT $r1,0x67812345 - ror.l $r1,$r0,-4 - EXPECT $r1,0x23456781 - -# jmpx - ldk $r28,0xaaaaa - jmpx 0,$r28,1,failcase - jmpx 1,$r28,0,failcase - jmpx 2,$r28,1,failcase - jmpx 3,$r28,0,failcase - jmpx 4,$r28,1,failcase - jmpx 5,$r28,0,failcase - jmpx 6,$r28,1,failcase - jmpx 7,$r28,0,failcase - jmpx 8,$r28,1,failcase - jmpx 9,$r28,0,failcase - jmpx 10,$r28,1,failcase - jmpx 11,$r28,0,failcase - jmpx 12,$r28,1,failcase - jmpx 13,$r28,0,failcase - jmpx 14,$r28,1,failcase - jmpx 15,$r28,0,failcase - jmpx 16,$r28,1,failcase - jmpx 17,$r28,0,failcase - jmpx 18,$r28,1,failcase - jmpx 19,$r28,0,failcase - - move $r29,$r28 - ldk $r28,0 - jmpx 0,$r29,1,failcase - jmpx 1,$r29,0,failcase - jmpx 2,$r29,1,failcase - jmpx 3,$r29,0,failcase - jmpx 4,$r29,1,failcase - jmpx 5,$r29,0,failcase - jmpx 6,$r29,1,failcase - jmpx 7,$r29,0,failcase - jmpx 8,$r29,1,failcase - jmpx 9,$r29,0,failcase - jmpx 10,$r29,1,failcase - jmpx 11,$r29,0,failcase - jmpx 12,$r29,1,failcase - jmpx 13,$r29,0,failcase - jmpx 14,$r29,1,failcase - jmpx 15,$r29,0,failcase - jmpx 16,$r29,1,failcase - jmpx 17,$r29,0,failcase - jmpx 18,$r29,1,failcase - jmpx 19,$r29,0,failcase - - move $r30,$r29 - ldk $r29,0 - jmpx 0,$r30,1,failcase - jmpx 1,$r30,0,failcase - jmpx 2,$r30,1,failcase - jmpx 3,$r30,0,failcase - jmpx 4,$r30,1,failcase - jmpx 5,$r30,0,failcase - jmpx 6,$r30,1,failcase - jmpx 7,$r30,0,failcase - jmpx 8,$r30,1,failcase - jmpx 9,$r30,0,failcase - jmpx 10,$r30,1,failcase - jmpx 11,$r30,0,failcase - jmpx 12,$r30,1,failcase - jmpx 13,$r30,0,failcase - jmpx 14,$r30,1,failcase - jmpx 15,$r30,0,failcase - jmpx 16,$r30,1,failcase - jmpx 17,$r30,0,failcase - jmpx 18,$r30,1,failcase - jmpx 19,$r30,0,failcase - -# callx - ldk $r30,0xaaaaa - callx 0,$r30,0,skip1 - jmp failcase - callx 1,$r30,1,skip1 - jmp failcase - callx 2,$r30,0,skip1 - jmp failcase - callx 3,$r30,1,skip1 - jmp failcase - - callx 0,$r30,1,skip1 - ldk $r30,0x123 - EXPECT $r30,0x123 - -#define BIT(N,M) ((((N) & 15) << 5) | (M)) -# bextu - bextu.l $r1,$r0,(0<<5)|0 - EXPECT $r1,0x00005678 - bextu.l $r1,$r0,(4<<5)|0 - EXPECT $r1,0x00000008 - bextu.l $r1,$r0,(4<<5)|4 - EXPECT $r1,0x00000007 - bextu.l $r1,$r0,(4<<5)|28 - EXPECT $r1,0x00000001 - bextu.l $r1,$r0,(8<<5)|16 - EXPECT $r1,0x00000034 - ldk.l $r2,-1 - bextu.l $r1,$r2,(6<<5)|(3) - EXPECT $r1,0x0000003f - -# bexts - bexts.l $r1,$r0,(8<<5)|0 - EXPECT $r1,0x00000078 - bexts.l $r1,$r0,(0<<5)|16 - EXPECT $r1,0x00001234 - bexts.l $r1,$r0,(4<<5)|0 - EXPECT $r1,0xfffffff8 - # extract the '5' digit in widths 4-1 - bexts.l $r1,$r0,(4<<5)|12 - EXPECT $r1,0x00000005 - bexts.l $r1,$r0,(3<<5)|12 - EXPECT $r1,0xfffffffd - bexts.l $r1,$r0,(2<<5)|12 - EXPECT $r1,0x00000001 - bexts.l $r1,$r0,(1<<5)|12 - EXPECT $r1,0xffffffff - -# btst - # low four bits should be 0,0,0,1 - btst.l $r0,(1<<5)|0 - jmpc nz,failcase - btst.l $r0,(1<<5)|1 - jmpc nz,failcase - btst.l $r0,(1<<5)|2 - jmpc nz,failcase - btst.l $r0,(1<<5)|3 - jmpc z,failcase - - # the 6 bit field starting at position 24 is positive - btst.l $r0,(6<<5)|24 - jmpc s,failcase - # the 5 bit field starting at position 24 is negative - btst.l $r0,(5<<5)|24 - jmpc ns,failcase - - EXPECT $r0,0x12345678 - -# bins - bins.l $r1,$r0,(8 << 5) | (0) - EXPECT $r1,0x12345600 - - bins.l $r1,$r0,(0 << 5) | (8) - EXPECT $r1,0x12000078 - - ldk.l $r1,(0xff << 10) | (8 << 5) | (8) - bins.l $r1,$r0,$r1 - EXPECT $r1,0x1234ff78 - - call litr1 - .long (0x8dd1 << 10) | (0 << 5) | (0) - bins.l $r1,$r0,$r1 - EXPECT $r1,0x12348dd1 - - call litr1 - .long (0x8dd1 << 10) | (0 << 5) | (16) - bins.l $r1,$r0,$r1 - EXPECT $r1,0x8dd15678 - - ldk.l $r1,(0xde << 10) | (8 << 5) | (0) - bins.l $r1,$r0,$r1 - EXPECT $r1,0x123456de - -# ldl - ldk.l $r0,0 - ldl.l $r3,$r0,0 - EXPECT $r3,0x00000000 - ldk.l $r0,-1 - ldl.l $r3,$r0,-1 - EXPECT $r3,0xffffffff - ldk.l $r0,(0x12345678 >> 10) - ldl.l $r3,$r0,(0x12345678 & 0x3ff) - EXPECT $r3,0x12345678 - ldk.l $r0,(0xe2345678 >> 10) - ldl.l $r3,$r0,(0xe2345678 & 0x3ff) - EXPECT $r3,0xe2345678 - -# flip - ldk.l $r0,0x0000001 - flip.l $r1,$r0,0 - EXPECT $r1,0x00000001 - - lpm.l $r0,k_12345678 - flip.l $r1,$r0,0 - EXPECT $r1,0x12345678 - flip.l $r1,$r0,24 - EXPECT $r1,0x78563412 - flip.l $r1,$r0,31 - EXPECT $r1,0x1e6a2c48 - -# stack push pop - - EXPECT $sp,0x00000000 - ldk.l $r6,0x6666 - push.l $r6 - or.l $r0,$r0,$r0 # xxx - EXPECT $sp,0x0000fffc - ldi.l $r1,$sp,0 - EXPECT $r1,0x00006666 - pop.l $r1 - EXPECT $r1,0x00006666 - EXPECT $sp,0x00000000 - -# call/return - call fowia - push.l $r1 - call fowia - pop.l $r2 - sub.l $r1,$r1,$r2 - EXPECT $r1,0x00000008 - -# add,carry - - ldk.l $r0,0 - ldk.l $r1,0 - call add64 - EXPECT $r1,0x00000000 - EXPECT $r0,0x00000000 - - lpm.l $r0,k_abcdef01 - lpm.l $r1,k_abcdef01 - call add64 - EXPECT $r1,0x00000001 - EXPECT $r0,0x579bde02 - - ldk.l $r0,4 - ldk.l $r1,-5 - call add64 - EXPECT $r1,0x00000000 - EXPECT $r0,0xffffffff - - ldk.l $r0,5 - ldk.l $r1,-5 - call add64 - EXPECT $r1,0x00000001 - EXPECT $r0,0x00000000 - - lpm.l $r0,k_12345678 - ldk.l $r1,-1 - call add64 - EXPECT $r1,0x00000001 - EXPECT $r0,0x12345677 - - ldk.l $r0,-1 - ldk.l $r1,-1 - call add64 - EXPECT $r1,0x00000001 - EXPECT $r0,0xfffffffe - -# inline literal - call lit - .long 0xdecafbad - EXPECT $r0,0xdecafbad - - ldk.l $r1,0xee - call lit - ldk.l $r1,0xfe - EXPECT $r1,0x000000ee - - call lit - .long 0x01020304 - EXPECT $r0,0x01020304 - - call lit - .long lit - calli $r0 - .long 0xffaa55aa - EXPECT $r0,0xffaa55aa - -# comparisons - ldk.l $r0,-100 - ldk.l $r1,100 - cmp.l $r0,$r1 - - ldk.l $r2,0 - jmpc lt,.c1 - ldk.l $r2,1 -.c1: - EXPECT $r2,0x00000000 - - ldk.l $r2,0 - jmpc gt,.c2 - ldk.l $r2,1 -.c2: - EXPECT $r2,0x00000001 - - ldk.l $r2,0 - jmpc a,.c3 - ldk.l $r2,1 -.c3: - EXPECT $r2,0x00000000 - - ldk.l $r2,0 - jmpc b,.c4 - ldk.l $r2,1 -.c4: - EXPECT $r2,0x00000001 - - ldk.l $r2,0 - jmpc be,.c5 - ldk.l $r2,1 -.c5: - EXPECT $r2,0x00000001 - -# 8-bit comparisons - ldk.l $r0,0x8fe - ldk.l $r1,0x708 - cmp.b $r0,$r1 - - ldk.l $r2,0 - jmpc lt,.8c1 - ldk.l $r2,1 -.8c1: - EXPECT $r2,0x00000000 - - ldk.l $r2,0 - jmpc gt,.8c2 - ldk.l $r2,1 -.8c2: - EXPECT $r2,0x00000001 - - ldk.l $r2,0 - jmpc a,.8c3 - ldk.l $r2,1 -.8c3: - EXPECT $r2,0x00000000 - - ldk.l $r2,0 - jmpc b,.8c4 - ldk.l $r2,1 -.8c4: - EXPECT $r2,0x00000001 - - ldk.l $r2,0 - jmpc be,.8c5 - ldk.l $r2,1 -.8c5: - EXPECT $r2,0x00000001 - - ldk.l $r0,0x8aa - ldk.l $r1,0x7aa - cmp.b $r0,$r1 - - ldk.l $r2,0 - jmpc z,.8c6 - ldk.l $r2,1 -.8c6: - EXPECT $r2,0x00000000 - - ldk.b $r0,1 - ldk.b $r2,0xe0 - cmp.b $r2,0x1c0 - jmpc a,.8c7 - ldk.b $r0,0 -.8c7: - EXPECT $r0,0x00000001 - -# conditional call - cmp.l $r0,$r0 - callc z,lit - .long 0xccddeeff - callc nz,zr0 - EXPECT $r0,0xccddeeff - -# modify return address - ldk.l $r0,0x66 - call skip1 - ldk.l $r0,0xAA - EXPECT $r0,0x00000066 - - ldk.l $r0,0x77 - call skip2 - ldk.l $r0,0xBB - EXPECT $r0,0x00000077 - -# simple recursive function - ldk.l $r0,1 - call factorial - EXPECT $r0,0x00000001 - ldk.l $r0,2 - call factorial - EXPECT $r0,0x00000002 - ldk.l $r0,3 - call factorial - EXPECT $r0,0x00000006 - ldk.l $r0,4 - call factorial - EXPECT $r0,0x00000018 - ldk.l $r0,5 - call factorial - EXPECT $r0,0x00000078 - ldk.l $r0,6 - call factorial - EXPECT $r0,0x000002d0 - ldk.l $r0,7 - call factorial - EXPECT $r0,0x000013b0 - ldk.l $r0,12 - call factorial - EXPECT $r0,0x1c8cfc00 - -# read sp after a call - call nullfunc - EXPECT $sp,0x00000000 - -# CALLI->RETURN - ldk.l $r4,nullfunc - calli $r4 - EXPECT $sp,0x00000000 - -# Link/unlink - ldk.l $r14,0x17566 - - link $r14,48 - EXPECT $r14,0x0000fffc - sub.l $sp,$sp,200 - unlink $r14 - EXPECT $r14,0x00017566 - -# LINK->UNLINK - link $r14,48 - unlink $r14 - EXPECT $r14,0x00017566 - -# LINK->JUMPI - ldk.l $r3,.here - link $r14,48 - jmpi $r3 - jmp failcase -.here: - unlink $r14 - EXPECT $r14,0x00017566 - -# LINK->RETURN -# (This is a nonsense combination, but can still exericse it by -# using a negative parameter for the link. "link $r14,-4" leaves -# $sp exactly unchanged.) - ldk.l $r0,.returnhere - push.l $r0 - link $r14,0xfffc - return -.returnhere: - EXPECT $sp,0x00000000 - -# LPMI->CALLI - ldk.l $r0,k_abcdef01 - ldk.l $r1,increment - lpmi.l $r0,$r0,0 - calli $r1 - EXPECT $r0,0xabcdef02 - -# STRLen - lpm.l $r4,str3 - sta.l tmp,$r4 - ldk.l $r0,tmp - strlen.b $r1,$r0 - EXPECT $r1,0x00000003 - strlen.s $r1,$r0 - EXPECT $r1,0x00000003 - strlen.l $r1,$r0 - EXPECT $r1,0x00000003 - - ldk.l $r4,0 - sta.b 4,$r4 - strlen.l $r1,$r0 - EXPECT $r1,0x00000000 - - ldk.l $r4,-1 - sta.l 4,$r4 - lpm.l $r4,str3 - sta.l 8,$r4 - strlen.l $r1,$r0 - EXPECT $r1,0x00000007 - -# MEMSet - ldk.l $r0,4 - ldk.l $r1,0xaa - memset.s $r0,$r1,8 - ldk.l $r1,0x55 - memset.b $r0,$r1,5 - lda.l $r0,4 - EXPECT $r0,0x55555555 - lda.l $r0,8 - EXPECT $r0,0xaaaaaa55 - -# first cycle after mispredict - ldk.l $r0,3 - cmp.l $r0,$r0 - jmpc nz,failcase - add.l $r0,$r0,7 - EXPECT $r0,0x0000000a - jmpc nz,failcase - push.l $r0 - EXPECT $sp,0x0000fffc - pop.l $r0 - -# $sp access after stall - lpm.l $r13,0 - push.l $r0 - EXPECT $sp,0x0000fffc - pop.l $r0 - - push.l $r0 - add.l $sp,$sp,-484 - EXPECT $sp,0x0000fe18 - EXPECT $sp,0x0000fe18 - EXPECT $sp,0x0000fe18 - add.l $sp,$sp,484 - EXPECT $sp,0x0000fffc - pop.l $r0 - -# atomic exchange - lpm.l $r0,k_12345678 - lpm.l $r1,k_abcdef01 - sta.l 100,$r1 - exa.l $r0,100 - EXPECT $r0,0xabcdef01 - lda.l $r0,100 - EXPECT $r0,0x12345678 - - lpm.l $r0,k_12345678 - lpm.l $r1,k_abcdef01 - sta.l 144,$r1 - ldk.l $r7,20 - exi.l $r0,$r7,124 - EXPECT $r0,0xabcdef01 - lda.l $r0,144 - EXPECT $r0,0x12345678 - - lpm.l $r0,k_12345678 - lpm.l $r1,k_abcdef01 - push $r1 - exi.l $r0,$sp,0 - EXPECT $r0,0xabcdef01 - pop.l $r0 - EXPECT $r0,0x12345678 - -# PM write port - .equ PM_UNLOCK, 0x1fc80 - .equ PM_ADDR, 0x1fc84 - .equ PM_DATA, 0x1fc88 - - lpm.l $r0,k_12345678 - lpm.l $r1,k_abcdef01 - EXPECT $r0,0x12345678 - EXPECT $r1,0xabcdef01 - ldk.l $r3,(0x1337f7d1 >> 10) - ldl.l $r3,$r3,(0x1337f7d1 & 0x3ff) - EXPECT $r3,0x1337f7d1 - ldk $r4,k_12345678 - sta.l PM_ADDR,$r4 - - # write while locked does nothing - sta.l PM_DATA,$r1 - sta.l PM_DATA,$r0 - lpm.l $r0,k_12345678 - lpm.l $r1,k_abcdef01 - EXPECT $r0,0x12345678 - EXPECT $r1,0xabcdef01 - - # write while unlocked modifies program memory - sta.l PM_UNLOCK,$r3 - sta.l PM_DATA,$r1 - sta.l PM_DATA,$r0 - lpm.l $r0,k_12345678 - lpm.l $r1,k_abcdef01 - EXPECT $r0,0xabcdef01 - EXPECT $r1,0x12345678 - -# final stack check - EXPECT $sp,0x00000000 - - PASS - -# -------------------------------------------------- - -skip1: # skip the instruction after the call - pop.l $r1 - add.l $r1,$r1,4 - push.l $r1 - return - -skipparent: # skip the instruction after the caller's call - ldi.l $r1,$sp,4 - add.l $r1,$r1,4 - sti.l $sp,4,$r1 - return -skip2: - call skipparent - return - -add64: - addcc.l $r0,$r1 - add.l $r0,$r0,$r1 - ldk.l $r1,0 - jmpc nc,.done - ldk.l $r1,1 -.done: - return - -fowia: # find out where I'm at - ldi.l $r1,$sp,0 - return - -lit: # load literal to $r0 - pop.l $r14 - lpmi.l $r0,$r14,0 - add.l $r14,$r14,4 - jmpi $r14 -zr0: - ldk.l $r0,0 - return -litr1: - ldi.l $r1,$sp,0 - add.l $r1,$r1,4 - sti.l $sp,0,$r1 - lpmi.l $r1,$r1,-4 - return - -factorial: - ldk.l $r1,1 - cmp.l $r0,$r1 - jmpc z,.factdone - push.l $r0 - add.l $r0,$r0,-1 - call factorial - pop.l $r1 - mul.l $r0,$r0,$r1 -.factdone: - return - -nullfunc: - return - -increment: - add.l $r0,$r0,1 - return - - .long 0x10111213 -k_12345678: - .long 0x12345678 -k_abcdef01: - .long 0xabcdef01 -str3: - .string "abc" diff --git a/sim/testsuite/sim/ft32/testutils.inc b/sim/testsuite/sim/ft32/testutils.inc deleted file mode 100644 index c07811f..0000000 --- a/sim/testsuite/sim/ft32/testutils.inc +++ /dev/null @@ -1,65 +0,0 @@ - -# Write ch to the standard output - .macro outch ch - ldk $r0,\ch - sta 0x10000,$r0 - .endm - -# End the test with return code c - .macro exit c - ldk $r0,\c - sta 0x1fffc,$r0 - .endm - -# All assembler tests should start with this macro "start" - .macro start - .text - - jmp __start - jmp __start - reti - - .data -ccsave: .long 0 - .text - -# Fiddling to load $cc from the following word in program memory -loadcc: - exi $r29,$sp,0 - lpmi $cc,$r29,0 - add $r29,$r29,4 - exi $r29,$sp,0 - return - -failcase: - outch 'f' - outch 'a' - outch 'i' - outch 'l' - outch '\n' - exit 1 - -__start: - - .endm - -# At the end of the test, the code should reach this macro PASS - .macro PASS - outch 'p' - outch 'a' - outch 's' - outch 's' - outch '\n' - exit 0 - .endm - -# Confirm that reg has value, and fail immediately if not -# Preserves all registers - .macro EXPECT reg,value - sta ccsave,$cc - call loadcc - .long \value - cmp \reg,$cc - jmpc nz,failcase - lda $cc,ccsave - .endm diff --git a/sim/testsuite/sim/h8300/ChangeLog b/sim/testsuite/sim/h8300/ChangeLog deleted file mode 100644 index 82128cc..0000000 --- a/sim/testsuite/sim/h8300/ChangeLog +++ /dev/null @@ -1,107 +0,0 @@ -2021-01-05 Mike Frysinger - - * rotl.s (mach): Set to "h8300s h8sx". - * rotr.s, rotxl.s, rotxr.s, shal.s, shar.s, shll.s, shlr.s, tas.s: - Likewise. - -2021-01-05 Mike Frysinger - - * allinsn.exp: Rewrite file to use globs. - -2004-06-28 Alexandre Oliva - - 2003-07-22 Michael Snyder - * mul.s: Don't try to use negative immediate (it's always - unsigned). - * div.s: Ditto. - -2004-06-24 Alexandre Oliva - - 2004-06-17 Alexandre Oliva - * band.s, biand.s: imm3_abs16 is not available on h8300h. - * bset.s: Likewise. Ditto for rn_abs32. - -2003-07-22 Michael Snyder - - * cmpw.s: Add test for less-than-zero immediate. - * shll.s: Test for shll reg, reg. - * shlr.s: Test for shlr reg, reg. - * mova.s: Add dozens of new mova tests. - -2003-05-30 Alexandre Oliva - - * allinsn.exp: Fix typos introduced on 2003-05-27. - -2003-05-29 Michael Snyder - - * tas.s: Use er4 for h8h and h8s, er3 for h8sx. - -2003-05-28 Michael Snyder - - * subs.s: New file. - * subx.s: New file. - * allinsn.exp: Add new subs and subx tests. - * testutils.inc: Simplify (and fix) set_carry_flag. - (clear_carry_flag, set_zero_flag, clear_zero_flag...): New macros. - * addx.s: Use simplified set_carry_flag. - -2003-05-27 Michael Snyder - - * tas.s: New file. - * band.s: New file. - * biand.s: New file. - * allinsn.exp: Add tas, band, biand tests. - * brabc.s: Add abs8 test. - * bset.s: Add bset/ne, bclr/ne tests. - -2003-05-23 Michael Snyder - - * and.b.s: Add andc exr. - * or.b.s: Add orc.exr. - * xor.b.s: Add xor exr. - - * jmp.s: Fix 8-bit indirect test. Add 7-bit vector test. - -2003-05-22 Michael Snyder - - * stack.s: Add rte/l and rts/l tests. - * allinsn.exp: Add stack tests. - -2003-05-21 Michael Snyder - - * stack.s: New file: test stack operations. - * stack.s: Add bsr, jsr tests. - * stack.s: Add trapa, rte tests. - - * div.s: Corrections for size of dividend. - -2003-05-20 Michael Snyder - - * mul.s: Corrections for unsigned multiply. - - * div.s: New file, test div instructions. - * allinsn.exp: Add div test. - -2003-05-19 Michael Snyder - - * mul.s: New file, test mul instructions. - * allinsn.exp: Add mul test. - -2003-05-14 Michael Snyder - - * addb.s, addw.s, addl.s, addw.s, addx.s, andb.s, andw.s, andl.s, - bfld.s, brabc.s, bra.s, bset.s, cmpb.s, cmpw.s, cmpl.s, daa.s, - das.s, dec.s, extw.s, extl.s, inc.s, jmp.s, ldc.s, ldm.s, mac.s, - mova.s, movb.s, movw.s, movl.s, movmd.s, movsd.s, neg.s, nop.s, - not.s, orb.s, orw.s, orl.s, rotl.s, rotr.s, rotxl.s, rotxr.s, - shal.s, shar.s, shll.s, shlr.s, stc.s, subb.s, subw.s, subl.s, - xorb.s, xorw.s, xorl.s: New files. - * allinsn.exp: New file. - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -change-log-default-name: "ChangeLog" -End: diff --git a/sim/testsuite/sim/h8300/addb.s b/sim/testsuite/sim/h8300/addb.s deleted file mode 100644 index f1e4ebf..0000000 --- a/sim/testsuite/sim/h8300/addb.s +++ /dev/null @@ -1,778 +0,0 @@ -# Hitachi H8 testcase 'add.b' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # add.b #xx:8, rd ; 8 rd xxxxxxxx - # add.b #xx:8, @erd ; 7 d rd ???? 8 ???? xxxxxxxx - # add.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? 8 ???? xxxxxxxx - # add.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? 8 ???? xxxxxxxx - # add.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? 8 ???? xxxxxxxx - # add.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? 8 ???? xxxxxxxx - # add.b #xx:8, @(d:16, erd) ; 0 1 7 4 6 e b30 | rd, b31, dd:16 8 ???? xxxxxxxx - # add.b #xx:8, @(d:32, erd) ; 7 8 b30 | rd, 4 6 a 2 8 dd:32 8 ???? xxxxxxxx - # add.b #xx:8, @aa:8 ; 7 f aaaaaaaa 8 ???? xxxxxxxx - # add.b #xx:8, @aa:16 ; 6 a 1 1??? aa:16 8 ???? xxxxxxxx - # add.b #xx:8, @aa:32 ; 6 a 3 1??? aa:32 8 ???? xxxxxxxx - # add.b rs, rd ; 0 8 rs rd - # add.b reg8, @erd ; 7 d rd ???? 0 8 rs ???? - # add.b reg8, @erd+ ; 0 1 7 9 8 rd 1 rs - # add.b reg8, @erd- ; 0 1 7 9 a rd 1 rs - # add.b reg8, @+erd ; 0 1 7 9 9 rd 1 rs - # add.b reg8, @-erd ; 0 1 7 9 b rd 1 rs - # add.b reg8, @(d:16, erd) ; 0 1 7 9 c b30 | rd32, 1 rs8 imm16 - # add.b reg8, @(d:32, erd) ; 0 1 7 9 d b31 | rd32, 1 rs8 imm32 - # add.b reg8, @aa:8 ; 7 f aaaaaaaa 0 8 rs ???? - # add.b reg8, @aa:16 ; 6 a 1 1??? aa:16 0 8 rs ???? - # add.b reg8, @aa:32 ; 6 a 3 1??? aa:32 0 8 rs ???? - # - - # Coming soon: - # add.b #xx:8, @(d:2, erd) ; 0 1 7 b30 | b21 | dd:2, 8 ???? xxxxxxxx - # add.b reg8, @(d:2, erd) ; 0 1 7 9 dd:2 rd32 1 rs8 - # ... - -.data -pre_byte: .byte 0 -byte_dest: .byte 0 -post_byte: .byte 0 - - start - -add_b_imm8_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; add.b #xx:8,Rd - add.b #5:8, r0l ; Immediate 8-bit src, reg8 dst - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5aa r0 ; add result: a5 + 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -add_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@eRd - mov #byte_dest, er0 - add.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst -;;; .word 0x7d00 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest, er0 ; er0 still contains address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #5, r0l - beq .L1 - fail -.L1: - -add_b_imm8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@eRd+ - mov #byte_dest, er0 - add.b #5:8, @er0+ ; Immediate 8-bit src, reg post-inc dst -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte, er0 ; er0 contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #10, r0l - beq .L2 - fail -.L2: - -add_b_imm8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@eRd- - mov #byte_dest, er0 - add.b #5:8, @er0- ; Immediate 8-bit src, reg post-dec dst -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte, er0 ; er0 contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #15, r0l - beq .L3 - fail -.L3: - -add_b_imm8_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@+eRd - mov #pre_byte, er0 - add.b #5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest, er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #20, r0l - beq .L4 - fail -.L4: - -add_b_imm8_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@-eRd - mov #post_byte, er0 - add.b #5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest, er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #25, r0l - beq .L5 - fail -.L5: - -add_b_imm8_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@(dd:16, eRd) - mov #post_byte, er0 - add.b #5:8, @(-1:16, er0) ; Immediate 8-bit src, 16-bit reg disp dest. -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 0xffff -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte, er0 ; er0 contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #30, r0l - beq .L6 - fail -.L6: - -add_b_imm8_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@(dd:32, eRd) - mov #pre_byte, er0 - add.b #5:8, @(1:32, er0) ; Immediate 8-bit src, 32-bit reg disp. dest. -;;; .word 0x7804 -;;; .word 0x6a28 -;;; .word 0x0000 -;;; .word 0x0001 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte, er0 ; er0 contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #35, r0l - beq .L7 - fail -.L7: - -add_b_imm8_abs8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b reg8,@aa:8 - ;; NOTE: for abs8, we will use the SBR register as a base, - ;; since otherwise we would have to make sure that the destination - ;; was in the zero page. - ;; - mov #byte_dest-100, er0 - ldc er0, sbr - add.b #5, @100:8 ; 8-bit reg src, 8-bit absolute dest -;;; .word 0x7f64 -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest-100, er0 ; reg 0 has base address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #40, r0l - beq .L8 - fail -.L8: - -add_b_imm8_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@aa:16 - add.b #5:8, @byte_dest:16 ; Immediate 8-bit src, 16-bit absolute dest -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #45, r0l - beq .L9 - fail -.L9: - -add_b_imm8_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b #xx:8,@aa:32 - add.b #5:8, @byte_dest:32 ; Immediate 8-bit src, 32-bit absolute dest -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x8005 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #50, r0l - beq .L10 - fail -.L10: - -.endif - -add_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; add.b Rs,Rd - mov.b #5, r0h - add.b r0h, r0l ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0x05aa r0 ; add result: a5 + 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -add_b_reg8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@eRd ; Add to register indirect - mov #byte_dest, er0 - mov #5, r1l - add.b r1l, @er0 ; reg8 src, reg indirect dest -;;; .word 0x7d00 -;;; .word 0x0890 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #55, r0l - beq .L11 - fail -.L11: - -add_b_reg8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@eRd+ ; Add to register post-increment - mov #byte_dest, er0 - mov #5, r1l - add.b r1l, @er0+ ; reg8 src, reg post-incr dest -;;; .word 0x0179 -;;; .word 0x8019 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #60, r0l - beq .L12 - fail -.L12: - -add_b_reg8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@eRd- ; Add to register post-decrement - mov #byte_dest, er0 - mov #5, r1l - add.b r1l, @er0- ; reg8 src, reg post-decr dest -;;; .word 0x0179 -;;; .word 0xa019 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #65, r0l - beq .L13 - fail -.L13: - -add_b_reg8_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@+eRd ; Add to register pre-increment - mov #pre_byte, er0 - mov #5, r1l - add.b r1l, @+er0 ; reg8 src, reg pre-incr dest -;;; .word 0x0179 -;;; .word 0x9019 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #70, r0l - beq .L14 - fail -.L14: - -add_b_reg8_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@-eRd ; Add to register pre-decrement - mov #post_byte, er0 - mov #5, r1l - add.b r1l, @-er0 ; reg8 src, reg pre-decr dest -;;; .word 0x0179 -;;; .word 0xb019 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #75, r0l - beq .L15 - fail -.L15: - -add_b_reg8_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@(dd:16, eRd) ; Add to register + 16-bit displacement - mov #pre_byte, er0 - mov #5, r1l - add.b r1l, @(1:16, er0) ; reg8 src, 16-bit reg disp dest -;;; .word 0x0179 -;;; .word 0xc019 -;;; .word 0x0001 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #80, r0l - beq .L16 - fail -.L16: - -add_b_reg8_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b rs8,@-eRd ; Add to register plus 32-bit displacement - mov #post_byte, er0 - mov #5, r1l - add.b r1l, @(-1:32, er0) ; reg8 src, 32-bit reg disp dest -;;; .word 0x0179 -;;; .word 0xd819 -;;; .word 0xffff -;;; .word 0xffff - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #85, r0l - beq .L17 - fail -.L17: - -add_b_reg8_abs8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b reg8,@aa:8 - ;; NOTE: for abs8, we will use the SBR register as a base, - ;; since otherwise we would have to make sure that the destination - ;; was in the zero page. - ;; - mov #byte_dest-100, er0 - ldc er0, sbr - mov #5, r1l - add.b r1l, @100:8 ; 8-bit reg src, 8-bit absolute dest -;;; .word 0x7f64 -;;; .word 0x0890 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest-100, er0 ; reg 0 has base address - test_h_gr32 0xa5a5a505 er1 ; reg 1 has test load - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #90, r0l - beq .L18 - fail -.L18: - -add_b_reg8_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b reg8,@aa:16 - mov #5, r0l - add.b r0l, @byte_dest:16 ; 8-bit reg src, 16-bit absolute dest -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x0880 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #95, r0l - beq .L19 - fail -.L19: - -add_b_reg8_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.b reg8,@aa:32 - mov #5, r0l - add.b r0l, @byte_dest:32 ; 8-bit reg src, 32-bit absolute dest -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x0880 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #100, r0l - beq .L20 - fail -.L20: - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/addl.s b/sim/testsuite/sim/h8300/addl.s deleted file mode 100644 index 586fcf6..0000000 --- a/sim/testsuite/sim/h8300/addl.s +++ /dev/null @@ -1,1865 +0,0 @@ -# Hitachi H8 testcase 'add.l' -# mach(): h8300h h8300s h8sx -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # add.l xx:3, erd - # add.l xx:16, erd - # add.l xx:32, erd - # add.l xx:16, @erd - # add.l xx:16, @erd+ - # add.l xx:16, @erd- - # add.l xx:16, @+erd - # add.l xx:16, @-erd - # add.l xx:16, @(dd:2, erd) - # add.l xx:16, @(dd:16, erd) - # add.l xx:16, @(dd:32, erd) - # add.l xx:16, @aa:16 - # add.l xx:16, @aa:32 - # add.l xx:32, @erd+ - # add.l xx:32, @erd- - # add.l xx:32, @+erd - # add.l xx:32, @-erd - # add.l xx:32, @(dd:2, erd) - # add.l xx:32, @(dd:16, erd) - # add.l xx:32, @(dd:32, erd) - # add.l xx:32, @aa:16 - # add.l xx:32, @aa:32 - # add.l ers, erd - # add.l ers, @erd - # add.l ers, @erd+ - # add.l ers, @erd- - # add.l ers, @+erd - # add.l ers, @-erd - # add.l ers, @(dd:2, erd) - # add.l ers, @(dd:16, erd) - # add.l ers, @(dd:32, erd) - # add.l ers, @aa:16 - # add.l ers, @aa:32 - # add.l ers, erd - # add.l @ers, erd - # add.l @ers+, erd - # add.l @ers-, erd - # add.l @+ers, erd - # add.l @-ers, erd - # add.l @(dd:2, ers), erd - # add.l @(dd:16, ers), erd - # add.l @(dd:32, ers), erd - # add.l @aa:16, erd - # add.l @aa:32, erd - # add.l @ers, @erd - # add.l @ers+, @erd+ - # add.l @ers-, @erd- - # add.l @+ers, +@erd - # add.l @-ers, @-erd - # add.l @(dd:2, ers), @(dd:2, erd) - # add.l @(dd:16, ers), @(dd:16, erd) - # add.l @(dd:32, ers), @(dd:32, erd) - # add.l @aa:16, @aa:16 - # add.l @aa:32, @aa:32 - - start - - .data - .align 4 -long_src: - .long 0x12345678 -long_dst: - .long 0x87654321 - - .text - - ;; - ;; Add long from immediate source - ;; - -.if (sim_cpu == h8sx) -add_l_imm3_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:3, erd - add.l #0x3:3, er0 ; Immediate 16-bit operand -;;; .word 0x0ab8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a5a8 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_imm16_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, erd - add.l #0x1234, er0 ; Immediate 16-bit operand -;;; .word 0x7a18 -;;; .word 0x1234 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5b7d9 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -add_l_imm32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, erd - add.l #0x12345678, er0 ; Immediate 32-bit operand -;;; .word 0x7a10 -;;; .long 0x12345678 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -add_l_imm16_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @erd - mov.l #long_dst, er1 - add.l #0xdead:16, @er1 ; Register indirect operand -;;; .word 0x010e -;;; .word 0x0110 -;;; .word 0xdead - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext11 - fail -.Lnext11: - mov.l #0x87654321, @long_dst ; Initialize it again for the next use. - -add_l_imm16_to_postinc: ; post-increment from imm16 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @erd+ - mov.l #long_dst, er1 - add.l #0xdead:16, @er1+ ; Imm16, register post-incr operands. -;;; .word 0x010e -;;; .word 0x8110 -;;; .word 0xdead - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext12 - fail -.Lnext12: - mov.l #0x87654321, @long_dst ; initialize it again for the next use. - -add_l_imm16_to_postdec: ; post-decrement from imm16 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @erd- - mov.l #long_dst, er1 - add.l #0xdead:16, @er1- ; Imm16, register post-decr operands. -;;; .word 0x010e -;;; .word 0xa110 -;;; .word 0xdead - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext13 - fail -.Lnext13: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @+erd - mov.l #long_dst-4, er1 - add.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands -;;; .word 0x010e -;;; .word 0x9110 -;;; .word 0xdead - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext14 - fail -.Lnext14: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @-erd - mov.l #long_dst+4, er1 - add.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands -;;; .word 0x010e -;;; .word 0xb110 -;;; .word 0xdead - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext15 - fail -.Lnext15: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @(dd:2, erd) - mov.l #long_dst-12, er1 - add.l #0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand -;;; .word 0x010e -;;; .word 0x3110 -;;; .word 0xdead - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-12, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext16 - fail -.Lnext16: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @(dd:16, erd) - mov.l #long_dst-4, er1 - add.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x010e -;;; .word 0xc110 -;;; .word 0xdead -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext17 - fail -.Lnext17: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @(dd:32, erd) - mov.l #long_dst-8, er1 - add.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x010e -;;; .word 0xc910 -;;; .word 0xdead -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext18 - fail -.Lnext18: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @aa:16 - add.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x010e -;;; .word 0x4010 -;;; .word 0xdead -;;; .word @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext19 - fail -.Lnext19: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm16_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:16, @aa:32 - add.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x010e -;;; .word 0x4810 -;;; .word 0xdead -;;; .long @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x876621ce, @long_dst - beq .Lnext20 - fail -.Lnext20: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @erd - mov.l #long_dst, er1 - add.l #0xcafedead:32, @er1 ; Register indirect operand -;;; .word 0x010e -;;; .word 0x0118 -;;; .long 0xcafedead - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext21 - fail -.Lnext21: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_postinc: ; post-increment from imm32 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @erd+ - mov.l #long_dst, er1 - add.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands. -;;; .word 0x010e -;;; .word 0x8118 -;;; .long 0xcafedead - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext22 - fail -.Lnext22: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_postdec: ; post-decrement from imm32 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @erd- - mov.l #long_dst, er1 - add.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands. -;;; .word 0x010e -;;; .word 0xa118 -;;; .long 0xcafedead - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext23 - fail -.Lnext23: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @+erd - mov.l #long_dst-4, er1 - add.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands -;;; .word 0x010e -;;; .word 0x9118 -;;; .long 0xcafedead - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext24 - fail -.Lnext24: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @-erd - mov.l #long_dst+4, er1 - add.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands -;;; .word 0x010e -;;; .word 0xb118 -;;; .long 0xcafedead - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext25 - fail -.Lnext25: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @(dd:2, erd) - mov.l #long_dst-12, er1 - add.l #0xcafedead:32, @(12:2, er1) ; Imm32, reg plus 2-bit disp. operand -;;; .word 0x010e -;;; .word 0x3118 -;;; .long 0xcafedead - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-12, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext26 - fail -.Lnext26: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @(dd:16, erd) - mov.l #long_dst-4, er1 - add.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x010e -;;; .word 0xc118 -;;; .long 0xcafedead -;;; .word 0x0004 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext27 - fail -.Lnext27: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @(dd:32, erd) - mov.l #long_dst-8, er1 - add.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x010e -;;; .word 0xc918 -;;; .long 0xcafedead -;;; .long 8 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext28 - fail -.Lnext28: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @aa:16 - add.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x010e -;;; .word 0x4018 -;;; .long 0xcafedead -;;; .word @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext29 - fail -.Lnext29: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_imm32_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l #xx:32, @aa:32 - add.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x010e -;;; .word 0x4818 -;;; .long 0xcafedead -;;; .long @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x526421ce, @long_dst - beq .Lnext30 - fail -.Lnext30: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. -.endif - - ;; - ;; Add long from register source - ;; - -add_l_reg32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, erd - mov.l #0x12345678, er1 - add.l er1, er0 ; Register 32-bit operand -;;; .word 0x0a90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 ; add result - test_h_gr32 0x12345678 er1 ; add src unchanged - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -add_l_reg32_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @erd - mov.l #long_dst, er1 - add.l er0, @er1 ; Register indirect operand -;;; .word 0x0109 -;;; .word 0x0110 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext44 - fail -.Lnext44: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_postinc: ; post-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @erd+ - mov.l #long_dst, er1 - add.l er0, @er1+ ; Register post-incr operand -;;; .word 0x0109 -;;; .word 0x8110 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext49 - fail -.Lnext49: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_postdec: ; post-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @erd- - mov.l #long_dst, er1 - add.l er0, @er1- ; Register post-decr operand -;;; .word 0x0109 -;;; .word 0xa110 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext50 - fail -.Lnext50: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @+erd - mov.l #long_dst-4, er1 - add.l er0, @+er1 ; Register pre-incr operand -;;; .word 0x0109 -;;; .word 0x9110 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext51 - fail -.Lnext51: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @-erd - mov.l #long_dst+4, er1 - add.l er0, @-er1 ; Register pre-decr operand -;;; .word 0x0109 -;;; .word 0xb110 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext48 - fail -.Lnext48: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @(dd:2, erd) - mov.l #long_dst-12, er1 - add.l er0, @(12:2, er1) ; Register plus 2-bit disp. operand -;;; .word 0x0109 -;;; .word 0x3110 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-12, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext52 - fail -.Lnext52: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @(dd:16, erd) - mov.l #long_dst-4, er1 - add.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x0109 -;;; .word 0xc110 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext45 - fail -.Lnext45: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @(dd:32, erd) - mov.l #long_dst-8, er1 - add.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x0109 -;;; .word 0xc910 -;;; .long 8 - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext46 - fail -.Lnext46: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @aa:16 - add.l er0, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x0109 -;;; .word 0x4110 -;;; .word @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext41 - fail -.Lnext41: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - -add_l_reg32_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l ers, @aa:32 - add.l er0, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x0109 -;;; .word 0x4910 -;;; .long @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 - test_neg_clear - test_zero_clear - test_ovf_set - test_carry_set - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x2d0ae8c6, @long_dst - beq .Lnext42 - fail -.Lnext42: - mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. - - ;; - ;; Add long to register destination. - ;; - -add_l_indirect_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @ers, Rd - mov.l #long_src, er1 - add.l @er1, er0 ; Register indirect operand -;;; .word 0x010a -;;; .word 0x0110 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_h_gr32 long_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_postinc_to_reg32: ; post-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @ers+, erd - mov.l #long_src, er1 - add.l @er1+, er0 ; Register post-incr operand -;;; .word 0x010a -;;; .word 0x8110 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_h_gr32 long_src+4, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_postdec_to_reg32: ; post-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @ers-, erd - mov.l #long_src, er1 - add.l @er1-, er0 ; Register post-decr operand -;;; .word 0x010a -;;; .word 0xa110 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_h_gr32 long_src-4, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_preinc_to_reg32: ; pre-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @+ers, erd - mov.l #long_src-4, er1 - add.l @+er1, er0 ; Register pre-incr operand -;;; .word 0x010a -;;; .word 0x9110 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_h_gr32 long_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_predec_to_reg32: ; pre-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @-ers, erd - mov.l #long_src+4, er1 - add.l @-er1, er0 ; Register pre-decr operand -;;; .word 0x010a -;;; .word 0xb110 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_h_gr32 long_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -add_l_disp2_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @(dd:2, ers), erd - mov.l #long_src-4, er1 - add.l @(4:2, er1), er0 ; Register plus 2-bit disp. operand -;;; .word 0x010a -;;; .word 0x1110 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 - - test_h_gr32 long_src-4, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_disp16_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @(dd:16, ers), erd - mov.l #long_src+0x1234, er1 - add.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand -;;; .word 0x010a -;;; .word 0xc110 -;;; .word -0x1234 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 - - test_h_gr32 long_src+0x1234, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_disp32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @(dd:32, ers), erd - mov.l #long_src+65536, er1 - add.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand -;;; .word 0x010a -;;; .word 0xc910 -;;; .long -65536 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 - - test_h_gr32 long_src+65536, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_abs16_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @aa:16, erd - add.l @long_src:16, er0 ; 16-bit address-direct operand -;;; .word 0x010a -;;; .word 0x4010 -;;; .word @long_src - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -add_l_abs32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @aa:32, erd - add.l @long_src:32, er0 ; 32-bit address-direct operand -;;; .word 0x010a -;;; .word 0x4810 -;;; .long @long_src - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xb7d9fc1d er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - - ;; - ;; Add long from memory to memory - ;; - -add_l_indirect_to_indirect: ; reg indirect, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @ers, @erd - mov.l #long_src, er1 - mov.l #long_dst, er0 - add.l @er1, @er0 -;;; .word 0x0104 -;;; .word 0x691c -;;; .word 0x0010 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst er0 - test_h_gr32 long_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst ; FIXME - beq .Lnext55 - fail -.Lnext55: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext56 - fail -.Lnext56: ; OK, pass on. - -add_l_postinc_to_postinc: ; reg post-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @ers+, @erd+ - mov.l #long_src, er1 - mov.l #long_dst, er0 - add.l @er1+, @er0+ -;;; .word 0x0104 -;;; .word 0x6d1c -;;; .word 0x8010 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst+4 er0 - test_h_gr32 long_src+4 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext65 - fail -.Lnext65: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext66 - fail -.Lnext66: ; OK, pass on. - -add_l_postdec_to_postdec: ; reg post-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @ers-, @erd- - mov.l #long_src, er1 - mov.l #long_dst, er0 - add.l @er1-, @er0- -;;; .word 0x0106 -;;; .word 0x6d1c -;;; .word 0xa010 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-4 er0 - test_h_gr32 long_src-4 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext75 - fail -.Lnext75: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext76 - fail -.Lnext76: ; OK, pass on. - -add_l_preinc_to_preinc: ; reg pre-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @+ers, @+erd - mov.l #long_src-4, er1 - mov.l #long_dst-4, er0 - add.l @+er1, @+er0 -;;; .word 0x0105 -;;; .word 0x6d1c -;;; .word 0x9010 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst er0 - test_h_gr32 long_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext85 - fail -.Lnext85: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext86 - fail -.Lnext86: ; OK, pass on. - -add_l_predec_to_predec: ; reg pre-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @-ers, @-erd - mov.l #long_src+4, er1 - mov.l #long_dst+4, er0 - add.l @-er1, @-er0 -;;; .word 0x0107 -;;; .word 0x6d1c -;;; .word 0xb010 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst er0 - test_h_gr32 long_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext95 - fail -.Lnext95: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext96 - fail -.Lnext96: ; OK, pass on. - -add_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @(dd:2, ers), @(dd:2, erd) - mov.l #long_src-4, er1 - mov.l #long_dst-8, er0 - add.l @(4:2, er1), @(8:2, er0) -;;; .word 0x0105 -;;; .word 0x691c -;;; .word 0x2010 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-8 er0 - test_h_gr32 long_src-4 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext105 - fail -.Lnext105: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext106 - fail -.Lnext106: ; OK, pass on. - -add_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @(dd:16, ers), @(dd:16, erd) - mov.l #long_src-1, er1 - mov.l #long_dst-2, er0 - add.l @(1:16, er1), @(2:16, er0) -;;; .word 0x0104 -;;; .word 0x6f1c -;;; .word 0x0001 -;;; .word 0xc010 -;;; .word 0x0002 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-2 er0 - test_h_gr32 long_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext115 - fail -.Lnext115: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext116 - fail -.Lnext116: ; OK, pass on. - -add_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @(dd:32, ers), @(dd:32, erd) - mov.l #long_src-1, er1 - mov.l #long_dst-2, er0 - add.l @(1:32, er1), @(2:32, er0) -;;; .word 0x7894 -;;; .word 0x6b2c -;;; .word 0xc9c8 -;;; .long 1 -;;; .word 0xc810 -;;; .long 2 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-2 er0 - test_h_gr32 long_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext125 - fail -.Lnext125: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext126 - fail -.Lnext126: ; OK, pass on. - -add_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @aa:16, @aa:16 - add.l @long_src:16, @long_dst:16 -;;; .word 0x0104 -;;; .word 0x6b0c -;;; .word @long_src -;;; .word 0x4010 -;;; .word @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext135 - fail -.Lnext135: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext136 - fail -.Lnext136: ; OK, pass on. - -add_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; add.l @aa:32, @aa:32 - add.l @long_src:32, @long_dst:32 -;;; .word 0x0104 -;;; .word 0x6b2c -;;; .long @long_src -;;; .word 0x4810 -;;; .long @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0x99999999, @long_dst - beq .Lnext145 - fail -.Lnext145: - ;; Now clear the destination location, and verify that. - mov.l #0x87654321, @long_dst - cmp.l #0x99999999, @long_dst - bne .Lnext146 - fail -.Lnext146: ; OK, pass on. - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/adds.s b/sim/testsuite/sim/h8300/adds.s deleted file mode 100644 index 9789e87..0000000 --- a/sim/testsuite/sim/h8300/adds.s +++ /dev/null @@ -1,74 +0,0 @@ -# Hitachi H8 testcase 'adds' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # adds #1, erd ; 0 b 0 xerd - # adds #2, erd ; 0 b 8 xerd - # adds #4, erd ; 0 b 9 xerd - # - - start -.if (sim_cpu) ; 32 bit only -adds_1: - set_grs_a5a5 - set_ccr_zero - - adds #1, er0 - - test_cc_clear ; adds should not affect any condition codes - test_h_gr32 0xa5a5a5a6 er0 ; result of adds #1 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -adds_2: - set_grs_a5a5 - set_ccr_zero - - adds #2, er0 - - test_cc_clear ; adds should not affect any condition codes - test_h_gr32 0xa5a5a5a7 er0 ; result of adds #2 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -adds_4: - set_grs_a5a5 - set_ccr_zero - - adds #4, er0 - - test_cc_clear ; adds should not affect any condition codes - test_h_gr32 0xa5a5a5a9 er0 ; result of adds #4 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass -.endif - exit 0 diff --git a/sim/testsuite/sim/h8300/addw.s b/sim/testsuite/sim/h8300/addw.s deleted file mode 100644 index c38bf69..0000000 --- a/sim/testsuite/sim/h8300/addw.s +++ /dev/null @@ -1,87 +0,0 @@ -# Hitachi H8 testcase 'add.w' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # add.w xx:3, rd ; 0 a 0xxx rd (sx only) - # add.w xx:16, rd ; 7 9 1 rd imm16 - # add.w rs, rd ; 0 9 rs rd - # - - start - -.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx -add_w_imm3: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; add.w #xx:3,Rd ; Immediate 3-bit operand - add.w #7, r0 ; FIXME will not assemble yet -; .word 0x0a70 ; Fake it until assembler will take it. - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5ac r0 ; add result: a5a5 + 7 - test_h_gr32 0xa5a5a5ac er0 ; add result: a5a5 + 7 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -add_w_imm16: - ;; add.w immediate not available in h8300 mode. - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; add.w #xx:16,Rd - add.w #0x111, r0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111 - test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -add_w_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; add.w Rs,Rd - mov.w #0x111, r1 - add.w r1, r0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111 - test_h_gr16 0x0111 r1 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111 - test_h_gr32 0xa5a50111 er1 -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/addx.s b/sim/testsuite/sim/h8300/addx.s deleted file mode 100644 index ef4e9d3..0000000 --- a/sim/testsuite/sim/h8300/addx.s +++ /dev/null @@ -1,992 +0,0 @@ -# Hitachi H8 testcase 'addx' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # addx.b #xx:8, rd8 ; 9 rd8 xxxxxxxx - # addx.b #xx:8, @erd ; 7 d erd ???? 9 ???? xxxxxxxx - # addx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? 9 ???? xxxxxxxx - # addx.b rs8, rd8 ; 0 e rs8 rd8 - # addx.b rs8, @erd ; 7 d erd ???? 0 e rs8 ???? - # addx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 0 e rs8 ???? - # addx.b @ers, rd8 ; 7 c ers ???? 0 e ???? rd8 - # addx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 0 e ???? rd8 - # addx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 1 ???? - # addx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 1 ???? - # - # word ops - # long ops - -.data -byte_src: .byte 0x5 -byte_dest: .byte 0 - - .align 2 -word_src: .word 0x505 -word_dest: .word 0 - - .align 4 -long_src: .long 0x50505 -long_dest: .long 0 - - - start - -addx_b_imm8_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b #xx:8,Rd ; Addx with carry initially zero. - addx.b #5, r0l ; Immediate 8-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0xa5aa r0 ; add result: a5 + 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_b_imm8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b #xx:8,Rd ; Addx with carry initially one. - set_carry_flag - addx.b #5, r0l ; Immediate 8-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0xa5ab r0 ; add result: a5 + 5 + 1 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5ab er0 ; add result: a5 + 5 + 1 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -addx_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b #xx:8,@eRd ; Addx to register indirect - mov #byte_dest, er0 - addx.b #5, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.b #5, @byte_dest - beq .Lb1 - fail -.Lb1: - -addx_b_imm8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b #xx:8,@eRd- ; Addx to register post-decrement - mov #byte_dest, er0 - addx.b #5, @er0- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.b #10, @byte_dest - beq .Lb2 - fail -.Lb2: -.endif - -addx_b_reg8_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b Rs,Rd ; addx with carry initially zero - mov.b #5, r0h - addx.b r0h, r0l ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0x05aa r0 ; add result: a5 + 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b Rs,Rd ; addx with carry initially one - mov.b #5, r0h - set_carry_flag - addx.b r0h, r0l ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0x05ab r0 ; add result: a5 + 5 + 1 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a505ab er0 ; add result: a5 + 5 + 1 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -addx_b_reg8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b rs8,@eRd ; Addx to register indirect - mov #byte_dest, er0 - mov.b #5, r1l - addx.b r1l, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.b #15, @byte_dest - beq .Lb3 - fail -.Lb3: - -addx_b_reg8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b rs8,@eRd- ; Addx to register post-decrement - mov #byte_dest, er0 - mov.b #5, r1l - addx.b r1l, @er0- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.b #20, @byte_dest - beq .Lb4 - fail -.Lb4: - -addx_b_rsind_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b @eRs,rd8 ; Addx from reg indirect to reg - mov #byte_src, er0 - addx.b @er0, r1l - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_src er0 ; er0 still contains address - test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_b_rspostdec_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b @eRs-,rd8 ; Addx to register post-decrement - mov #byte_src, er0 - addx.b @er0-, r1l - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_src-1 er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_b_rsind_rsind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b @eRs,rd8 ; Addx from reg indirect to reg - mov #byte_src, er0 - mov #byte_dest, er1 - addx.b @er0, @er1 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_src er0 ; er0 still contains src address - test_h_gr32 byte_dest er1 ; er1 still contains dst address - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the add to memory. - cmp.b #25, @byte_dest - beq .Lb5 - fail -.Lb5: - -addx_b_rspostdec_rspostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.b @eRs-,rd8 ; Addx to register post-decrement - mov #byte_src, er0 - mov #byte_dest, er1 - addx.b @er0-, @er1- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_src-1 er0 ; er0 contains src address minus one - test_h_gr32 byte_dest-1 er1 ; er1 contains dst address minus one - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the add to memory. - cmp.b #30, @byte_dest - beq .Lb6 - fail -.Lb6: - -addx_w_imm16_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w #xx:16,Rd ; Addx with carry initially zero. - addx.w #0x505, r0 ; Immediate 16-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0xaaaa r0 ; add result: 0xa5a5 + 0x505 - test_h_gr32 0xa5a5aaaa er0 ; add result: 0xa5a5 + 0x505 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_w_imm16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w #xx:16,Rd ; Addx with carry initially one. - set_carry_flag - addx.w #0x505, r0 ; Immediate 16-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0xaaab r0 ; add result: 0xa5a5 + 0x505 + 1 - test_h_gr32 0xa5a5aaab er0 ; add result: 0xa5a5 + 0x505 + 1 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_w_imm16_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w #xx:16,@eRd ; Addx to register indirect - mov #word_dest, er0 - addx.w #0x505, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 word_dest er0 ; er0 still contains address - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.w #0x505, @word_dest - beq .Lw1 - fail -.Lw1: - -addx_w_imm16_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w #xx:16,@eRd- ; Addx to register post-decrement - mov #word_dest, er0 - addx.w #0x505, @er0- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 ; er0 contains address minus one - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.w #0xa0a, @word_dest - beq .Lw2 - fail -.Lw2: - -addx_w_reg16_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w Rs,Rd ; addx with carry initially zero - mov.w #0x505, e0 - addx.w e0, r0 ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0x0505aaaa er0 ; add result: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w Rs,Rd ; addx with carry initially one - mov.w #0x505, e0 - set_carry_flag - addx.w e0, r0 ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0x0505aaab er0 ; add result: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_w_reg16_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w rs8,@eRd ; Addx to register indirect - mov #word_dest, er0 - mov.w #0x505, r1 - addx.w r1, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 word_dest er0 ; er0 still contains address - test_h_gr32 0xa5a50505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.w #0xf0f, @word_dest - beq .Lw3 - fail -.Lw3: - -addx_w_reg16_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w rs8,@eRd- ; Addx to register post-decrement - mov #word_dest, er0 - mov.w #0x505, r1 - addx.w r1, @er0- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 ; er0 contains address minus one - test_h_gr32 0xa5a50505 er1 ; er1 contains the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.w #0x1414, @word_dest - beq .Lw4 - fail -.Lw4: - -addx_w_rsind_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w @eRs,rd8 ; Addx from reg indirect to reg - mov #word_src, er0 - addx.w @er0, r1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 word_src er0 ; er0 still contains address - test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_w_rspostdec_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w @eRs-,rd8 ; Addx to register post-decrement - mov #word_src, er0 - addx.w @er0-, r1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 word_src-2 er0 ; er0 contains address minus one - test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_w_rsind_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w @eRs,rd8 ; Addx from reg indirect to reg - mov #word_src, er0 - mov #word_dest, er1 - addx.w @er0, @er1 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 word_src er0 ; er0 still contains src address - test_h_gr32 word_dest er1 ; er1 still contains dst address - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the add to memory. - cmp.w #0x1919, @word_dest - beq .Lw5 - fail -.Lw5: - -addx_w_rspostdec_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.w @eRs-,rd8 ; Addx to register post-decrement - mov #word_src, er0 - mov #word_dest, er1 - addx.w @er0-, @er1- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 word_src-2 er0 ; er0 contains src address minus one - test_h_gr32 word_dest-2 er1 ; er1 contains dst address minus one - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the add to memory. - cmp.w #0x1e1e, @word_dest - beq .Lw6 - fail -.Lw6: - -addx_l_imm32_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l #xx:32,Rd ; Addx with carry initially zero. - addx.l #0x50505, er0 ; Immediate 32-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0xa5aaaaaa er0 ; add result: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_l_imm32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l #xx:32,Rd ; Addx with carry initially one. - set_carry_flag - addx.l #0x50505, er0 ; Immediate 32-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0xa5aaaaab er0 ; add result: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_l_imm32_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l #xx:32,@eRd ; Addx to register indirect - mov #long_dest, er0 - addx.l #0x50505, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 long_dest er0 ; er0 still contains address - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.l #0x50505, @long_dest - beq .Ll1 - fail -.Ll1: - -addx_l_imm32_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l #xx:32,@eRd- ; Addx to register post-decrement - mov #long_dest, er0 - addx.l #0x50505, @er0- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 ; er0 contains address minus one - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.l #0xa0a0a, @long_dest - beq .Ll2 - fail -.Ll2: - -addx_l_reg32_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l Rs,Rd ; addx with carry initially zero - mov.l #0x50505, er0 - addx.l er0, er1 ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0x50505 er0 ; add load - test_h_gr32 0xa5aaaaaa er1 ; add result: - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l Rs,Rd ; addx with carry initially one - mov.l #0x50505, er0 - set_carry_flag - addx.l er0, er1 ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0x50505 er0 ; add result: - test_h_gr32 0xa5aaaaab er1 ; add result: - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_l_reg32_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l rs8,@eRd ; Addx to register indirect - mov #long_dest, er0 - mov.l #0x50505, er1 - addx.l er1, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 long_dest er0 ; er0 still contains address - test_h_gr32 0x50505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.l #0xf0f0f, @long_dest - beq .Ll3 - fail -.Ll3: - -addx_l_reg32_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l rs8,@eRd- ; Addx to register post-decrement - mov #long_dest, er0 - mov.l #0x50505, er1 - addx.l er1, @er0- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 ; er0 contains address minus one - test_h_gr32 0x50505 er1 ; er1 contains the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the add to memory. - cmp.l #0x141414, @long_dest - beq .Ll4 - fail -.Ll4: - -addx_l_rsind_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l @eRs,rd8 ; Addx from reg indirect to reg - mov #long_src, er0 - addx.l @er0, er1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 long_src er0 ; er0 still contains address - test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_l_rspostdec_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l @eRs-,rd8 ; Addx to register post-decrement - mov #long_src, er0 - addx.l @er0-, er1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 long_src-4 er0 ; er0 contains address minus one - test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -addx_l_rsind_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l @eRs,rd8 ; Addx from reg indirect to reg - mov #long_src, er0 - mov #long_dest, er1 - addx.l @er0, @er1 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 long_src er0 ; er0 still contains src address - test_h_gr32 long_dest er1 ; er1 still contains dst address - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the add to memory. - cmp.l #0x191919, @long_dest - beq .Ll5 - fail -.Ll5: - -addx_l_rspostdec_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; addx.l @eRs-,rd8 ; Addx to register post-decrement - mov #long_src, er0 - mov #long_dest, er1 - addx.l @er0-, @er1- - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 long_src-4 er0 ; er0 contains src address minus one - test_h_gr32 long_dest-4 er1 ; er1 contains dst address minus one - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the add to memory. - cmp.l #0x1e1e1e, @long_dest - beq .Ll6 - fail -.Ll6: -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/allinsn.exp b/sim/testsuite/sim/h8300/allinsn.exp deleted file mode 100644 index 68468f6..0000000 --- a/sim/testsuite/sim/h8300/allinsn.exp +++ /dev/null @@ -1,15 +0,0 @@ -# Hitachi H8/300 (h, s, sx) simulator testsuite - -if {[istarget h8300*-*-*] || [istarget h8sx*-*-*]} then { - set all_machs "h8300 h8300h h8300s h8sx" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/h8300/andb.s b/sim/testsuite/sim/h8300/andb.s deleted file mode 100644 index 8f11805..0000000 --- a/sim/testsuite/sim/h8300/andb.s +++ /dev/null @@ -1,527 +0,0 @@ -# Hitachi H8 testcase 'and.b' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # and.b #xx:8, rd ; e rd xxxxxxxx - # and.b #xx:8, @erd ; 7 d rd ???? e ???? xxxxxxxx - # and.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx - # and.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx - # and.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx - # and.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx - # and.b rs, rd ; 1 6 rs rd - # and.b reg8, @erd ; 7 d rd ???? 1 6 rs ???? - # and.b reg8, @erd+ ; 0 1 7 9 8 rd 6 rs - # and.b reg8, @erd- ; 0 1 7 9 a rd 6 rs - # and.b reg8, @+erd ; 0 1 7 9 9 rd 6 rs - # and.b reg8, @-erd ; 0 1 7 9 b rd 6 rs - # - # andc #xx:8, ccr ; 0 6 xxxxxxxx - # andc #xx:8, exr ; 0 1 4 1 0 6 xxxxxxxx - - # Coming soon: - # ... - -.data -pre_byte: .byte 0 -byte_dest: .byte 0xa5 -post_byte: .byte 0 - - start - -and_b_imm8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.b #xx:8,Rd - and.b #0xaa, r0l ; Immediate 8-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a0 r0 ; and result: a5 & aa -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5a0 er0 ; and result: a5 & aa -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -and_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b #xx:8,@eRd - mov #byte_dest, er0 - and.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst -;;; .word 0x7d00 -;;; .word 0xe0aa - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest, er0 ; er0 still contains address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa0, r0l - beq .L1 - fail -.L1: - -and_b_imm8_rdpostinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b #xx:8,@eRd+ - mov #byte_dest, er0 - and.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xe055 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte, er0 ; er0 contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x05, r0l - beq .L2 - fail -.L2: - -and_b_imm8_rdpostdec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b #xx:8,@eRd- - mov #byte_dest, er0 - and.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xe0aa - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 pre_byte, er0 ; er0 contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa0, r0l - beq .L3 - fail -.L3: - -and_b_imm8_rdpreinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b #xx:8,@+eRd - mov #pre_byte, er0 - and.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0xe055 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest, er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x05, r0l - beq .L4 - fail -.L4: - -and_b_imm8_rdpredec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b #xx:8,@-eRd - mov #post_byte, er0 - and.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0xe0aa - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest, er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa0, r0l - beq .L5 - fail -.L5: - -.endif ; h8sx - -and_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.b Rs,Rd - mov.b #0xaa, r0h - and.b r0h, r0l ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xaaa0 r0 ; and result: a5 & aa -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5aaa0 er0 ; and result: a5 & aa -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -and_b_reg8_rdind: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b rs8,@eRd ; And to register indirect - mov #byte_dest, er0 - mov #0x55, r1l - and.b r1l, @er0 ; reg8 src, reg indirect dest -;;; .word 0x7d00 -;;; .word 0x1690 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a555 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x05, r0l - beq .L6 - fail -.L6: - -and_b_reg8_rdpostinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b rs8,@eRd+ ; And to register post-incr - mov #byte_dest, er0 - mov #0xaa, r1l - and.b r1l, @er0+ ; reg8 src, reg post-incr dest -;;; .word 0x0179 -;;; .word 0x8069 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa0, r0l - beq .L7 - fail -.L7: - -and_b_reg8_rdpostdec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b rs8,@eRd- ; And to register post-decr - mov #byte_dest, er0 - mov #0x55, r1l - and.b r1l, @er0- ; reg8 src, reg post-decr dest -;;; .word 0x0179 -;;; .word 0xa069 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a555 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x05, r0l - beq .L8 - fail -.L8: - -and_b_reg8_rdpreinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b rs8,@+eRd ; And to register post-incr - mov #pre_byte, er0 - mov #0xaa, r1l - and.b r1l, @+er0 ; reg8 src, reg post-incr dest -;;; .word 0x0179 -;;; .word 0x9069 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa0, r0l - beq .L9 - fail -.L9: - -and_b_reg8_rdpredec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; and.b rs8,@-eRd ; And to register post-decr - mov #post_byte, er0 - mov #0x55, r1l - and.b r1l, @-er0 ; reg8 src, reg post-decr dest -;;; .word 0x0179 -;;; .word 0xb069 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a555 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the and to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x05, r0l - beq .L10 - fail -.L10: -.endif ; h8sx - -andc_imm8_ccr: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; andc #xx:8,ccr - set_ccr 0xff - - test_neg_set - andc #0xf7, ccr ; Immediate 8-bit operand (neg flag) - test_neg_clear - - test_zero_set - andc #0xfb, ccr ; Immediate 8-bit operand (zero flag) - test_zero_clear - - test_ovf_set - andc #0xfd, ccr ; Immediate 8-bit operand (overflow flag) - test_ovf_clear - - test_carry_set - andc #0xfe, ccr ; Immediate 8-bit operand (carry flag) - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr -andc_imm8_exr: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ldc #0xff, exr - stc exr, r0l - test_h_gr8 0x87, r0l - - ;; andc #xx:8,exr - set_ccr_zero - andc #0x7f, exr - test_cc_clear - stc exr, r0l - test_h_gr8 0x7, r0l - - andc #0x3, exr - stc exr, r0l - test_h_gr8 0x3, r0l - - andc #0x1, exr - stc exr, r0l - test_h_gr8 0x1, r0l - - andc #0x0, exr - stc exr, r0l - test_h_gr8 0x0, r0l - - test_h_gr32 0xa5a5a500 er0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; not h8300 or h8300h - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/andl.s b/sim/testsuite/sim/h8300/andl.s deleted file mode 100644 index ac09edc..0000000 --- a/sim/testsuite/sim/h8300/andl.s +++ /dev/null @@ -1,77 +0,0 @@ -# Hitachi H8 testcase 'and.l' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. -and_l_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.l #xx:16,Rd - and.l #0xaaaa:16, er0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0x0000a0a0 er0 ; and result: a5a5a5a5 & aaaa - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -and_l_imm32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.l #xx:32,Rd - and.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -and_l_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.l Rs,Rd - mov.l #0xaaaaaaaa, er1 - and.l er1, er0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa - test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/andw.s b/sim/testsuite/sim/h8300/andw.s deleted file mode 100644 index 4267179..0000000 --- a/sim/testsuite/sim/h8300/andw.s +++ /dev/null @@ -1,61 +0,0 @@ -# Hitachi H8 testcase 'and.w' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -and_w_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.w #xx:16,Rd - and.w #0xaaaa, r0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -and_w_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; and.w Rs,Rd - mov.w #0xaaaa, r1 - and.w r1, r0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa - test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa - test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/band.s b/sim/testsuite/sim/h8300/band.s deleted file mode 100644 index 3c7e5a3..0000000 --- a/sim/testsuite/sim/h8300/band.s +++ /dev/null @@ -1,525 +0,0 @@ -# Hitachi H8 testcase 'band', 'bor', 'bxor', 'bld', 'bst', 'bstz' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -byte_src: .byte 0xa5 -byte_dst: .byte 0 - - start - -band_imm3_reg8: - set_grs_a5a5 - set_ccr_zero - ;; band xx:3, reg8 - band #7, r0l ; this should NOT set the carry flag. - test_cc_clear - band #6, r0l ; this should NOT set the carry flag. - test_cc_clear - - orc #1, ccr ; set the carry flag - band #7, r0l ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - band #6, r0l ; this should clear the carry flag - test_cc_clear - - test_grs_a5a5 ; general registers should not be changed. - -band_imm3_ind: - set_grs_a5a5 -.if (sim_cpu == h8300) - mov #byte_src, r1 - set_ccr_zero - ;; band xx:3, ind - band #7, @r1 ; this should NOT set the carry flag. - test_cc_clear - band #6, @r1 ; this should NOT set the carry flag. - test_cc_clear - - orc #1, ccr ; set the carry flag - band #7, @r1 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - band #6, @r1 ; this should clear the carry flag - test_cc_clear -;;; test_h_gr16 byte_src r1 ;FIXME -.else - mov #byte_src, er1 - set_ccr_zero - ;; band xx:3, ind - band #7, @er1 ; this should NOT set the carry flag. - test_cc_clear - band #6, @er1 ; this should NOT set the carry flag. - test_cc_clear - - orc #1, ccr ; set the carry flag - band #7, @er1 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - band #6, @er1 ; this should clear the carry flag - test_cc_clear - test_h_gr32 byte_src er1 -.endif ; h8300 - test_gr_a5a5 0 ; general registers should not be changed. - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -band_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; band xx:3, aa:8 - band #7, @0x20:8 ; this should NOT set the carry flag. - test_cc_clear - band #6, @0x20:8 ; this should NOT set the carry flag. - test_cc_clear - - orc #1, ccr ; set the carry flag - band #7, @0x20:8 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - band #6, @0x20:8 ; this should clear the carry flag - test_cc_clear - - test_grs_a5a5 ; general registers should not be changed. - -.if (sim_cpu > h8300h) -band_imm3_abs16: - set_grs_a5a5 - set_ccr_zero - ;; band xx:3, aa:16 - band #7, @byte_src:16 ; this should NOT set the carry flag. - test_cc_clear - band #6, @byte_src:16 ; this should NOT set the carry flag. - test_cc_clear - - orc #1, ccr ; set the carry flag - band #7, @byte_src:16 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - band #6, @byte_src:16 ; this should clear the carry flag - test_cc_clear - - test_grs_a5a5 ; general registers should not be changed. - -band_imm3_abs32: - set_grs_a5a5 - set_ccr_zero - ;; band xx:3, aa:32 - band #7, @byte_src:32 ; this should NOT set the carry flag. - test_cc_clear - band #6, @byte_src:32 ; this should NOT set the carry flag. - test_cc_clear - - orc #1, ccr ; set the carry flag - band #7, @byte_src:32 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - band #6, @byte_src:32 ; this should clear the carry flag - test_cc_clear - - test_grs_a5a5 ; general registers should not be changed. -.endif - -bor_imm3_reg8: - set_grs_a5a5 - set_ccr_zero - ;; bor xx:3, reg8 - bor #6, r0l ; this should NOT set the carry flag. - test_cc_clear - - bor #7, r0l ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - orc #1, ccr ; set the carry flag - bor #7, r0l ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - bor #6, r0l ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - test_grs_a5a5 ; general registers should not be changed. - -bor_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; bor xx:3, aa:8 - bor #6, @0x20:8 ; this should NOT set the carry flag. - test_cc_clear - bor #7, @0x20:8 ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - orc #1, ccr ; set the carry flag - bor #7, @0x20:8 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - bor #6, @0x20:8 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - test_grs_a5a5 ; general registers should not be changed. - -bxor_imm3_reg8: - set_grs_a5a5 - set_ccr_zero - ;; bxor xx:3, reg8 - bxor #6, r0l ; this should NOT set the carry flag. - test_cc_clear - - bxor #7, r0l ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - orc #1, ccr ; set the carry flag - bxor #6, r0l ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - bxor #7, r0l ; this should clear the carry flag - test_cc_clear - - test_grs_a5a5 ; general registers should not be changed. - -bxor_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; bxor xx:3, aa:8 - bxor #6, @0x20:8 ; this should NOT set the carry flag. - test_cc_clear - bxor #7, @0x20:8 ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - orc #1, ccr ; set the carry flag - bxor #6, @0x20:8 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - bxor #7, @0x20:8 ; this should clear the carry flag - test_cc_clear - - test_grs_a5a5 ; general registers should not be changed. - -bld_imm3_reg8: - set_grs_a5a5 - set_ccr_zero - ;; bld xx:3, reg8 - bld #6, r0l ; this should NOT set the carry flag. - test_cc_clear - bld #7, r0l ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - test_grs_a5a5 ; general registers should not be changed. - -bld_imm3_ind: - set_grs_a5a5 -.if (sim_cpu == h8300) - mov #byte_src, r1 - set_ccr_zero - ;; bld xx:3, ind - bld #6, @r1 ; this should NOT set the carry flag. - test_cc_clear - bld #7, @r1 ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear -;;; test_h_gr16 byte_src r1 ;FIXME -.else - mov #byte_src, er1 - set_ccr_zero - ;; bld xx:3, ind - bld #6, @er1 ; this should NOT set the carry flag. - test_cc_clear - bld #7, @er1 ; this should NOT set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - test_h_gr32 byte_src er1 -.endif ; h8300 - test_gr_a5a5 0 ; general registers should not be changed. - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bld_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; bld xx:3, aa:8 - bld #6, @0x20:8 ; this should NOT set the carry flag. - test_cc_clear - bld #7, @0x20:8 ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - test_grs_a5a5 ; general registers should not be changed. - -.if (sim_cpu > h8300h) -bld_imm3_abs16: - set_grs_a5a5 - set_ccr_zero - ;; bld xx:3, aa:16 - bld #6, @byte_src:16 ; this should NOT set the carry flag. - test_cc_clear - bld #7, @byte_src:16 ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - test_grs_a5a5 ; general registers should not be changed. - -bld_imm3_abs32: - set_grs_a5a5 - set_ccr_zero - ;; bld xx:3, aa:32 - bld #6, @byte_src:32 ; this should NOT set the carry flag. - test_cc_clear - bld #7, @byte_src:32 ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - test_grs_a5a5 ; general registers should not be changed. -.endif - -bst_imm3_reg8: - set_grs_a5a5 - set_ccr_zero - ;; bst xx:3, reg8 - bst #7, r0l ; this should clear bit 7 - test_cc_clear - test_h_gr16 0xa525 r0 - - set_ccr_zero - orc #1, ccr ; set the carry flag - bst #6, r0l ; this should set bit 6 - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - test_h_gr16 0xa565 r0 - - test_gr_a5a5 1 ; Rest of general regs should not be changed. - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bst_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; bst xx:3, aa:8 - bst #7, @0x20:8 ; this should clear bit 7 - test_cc_clear - mov.b @0x20, r0l - test_h_gr16 0xa525 r0 - - set_ccr_zero - orc #1, ccr ; set the carry flag - bst #6, @0x20:8 ; this should set bit 6 - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - mov.b @0x20, r0l - test_h_gr16 0xa565 r0 - - test_gr_a5a5 1 ; general registers should not be changed. - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -bstz_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; bstz xx:3, aa:8 - bstz #7, @0x20:8 ; this should clear bit 7 - test_cc_clear - mov.b @0x20, r0l - test_h_gr16 0xa525 r0 - - set_ccr_zero - orc #4, ccr ; set the zero flag - bstz #6, @0x20:8 ; this should set bit 6 - test_carry_clear - test_ovf_clear - test_neg_clear - test_zero_set - mov.b @0x20, r0l - test_h_gr16 0xa565 r0 - - test_gr_a5a5 1 ; general registers should not be changed. - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx - -btst_imm3_reg8: - set_grs_a5a5 - set_ccr_zero - ;; btst xx:3, reg8 - btst #7, r0l ; this should NOT set the zero flag. - test_cc_clear - btst #6, r0l ; this should set the zero flag. - test_carry_clear - test_ovf_clear - test_neg_clear - test_zero_set - - test_grs_a5a5 ; general registers should not be changed. - -btst_imm3_ind: - set_grs_a5a5 -.if (sim_cpu == h8300) - mov #byte_src, r1 - set_ccr_zero - ;; btst xx:3, ind - btst #7, @r1 ; this should NOT set the zero flag. - test_cc_clear - btst #6, @r1 ; this should set the zero flag. - test_carry_clear - test_ovf_clear - test_neg_clear - test_zero_set -;;; test_h_gr16 byte_src r1 ;FIXME -.else - mov #byte_src, er1 - set_ccr_zero - ;; btst xx:3, ind - btst #7, @er1 ; this should NOT set the zero flag. - test_cc_clear - btst #6, @er1 ; this should NOT set the zero flag. - test_carry_clear - test_ovf_clear - test_neg_clear - test_zero_set - test_h_gr32 byte_src er1 -.endif ; h8300 - test_gr_a5a5 0 ; general registers should not be changed. - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -btst_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; btst xx:3, aa:8 - btst #7, @0x20:8 ; this should NOT set the zero flag. - test_cc_clear - btst #6, @0x20:8 ; this should set the zero flag. - test_carry_clear - test_ovf_clear - test_neg_clear - test_zero_set - - test_grs_a5a5 ; general registers should not be changed. - -.if (sim_cpu > h8300h) -btst_imm3_abs16: - set_grs_a5a5 - set_ccr_zero - ;; btst xx:3, aa:16 - btst #7, @byte_src:16 ; this should NOT set the zero flag. - test_cc_clear - btst #6, @byte_src:16 ; this should set the zero flag. - test_carry_clear - test_ovf_clear - test_neg_clear - test_zero_set - - test_grs_a5a5 ; general registers should not be changed. - -btst_imm3_abs32: - set_grs_a5a5 - set_ccr_zero - ;; btst xx:3, aa:32 - btst #7, @byte_src:32 ; this should NOT set the zero flag. - test_cc_clear - btst #6, @byte_src:32 ; this should set the zero flag. - test_carry_clear - test_ovf_clear - test_neg_clear - test_zero_set - - test_grs_a5a5 ; general registers should not be changed. -.endif - - pass - exit 0 diff --git a/sim/testsuite/sim/h8300/bfld.s b/sim/testsuite/sim/h8300/bfld.s deleted file mode 100644 index 7c55007..0000000 --- a/sim/testsuite/sim/h8300/bfld.s +++ /dev/null @@ -1,286 +0,0 @@ -# Hitachi H8 testcase 'bfld', 'bfst' -# mach(): h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -byte_src: .byte 0xa5 -byte_dst: .byte 0 - - start - -.if (sim_cpu == h8sx) -bfld_imm8_ind: - set_grs_a5a5 - mov #byte_src, er2 - - ;; bfld #xx:8, @ers, rd8 - set_ccr_zero - bfld #1, @er2, r1l - test_cc_clear - test_h_gr8 1 r1l - - set_ccr_zero - bfld #2, @er2, r1l - test_cc_clear - test_h_gr8 0 r1l - - set_ccr_zero - bfld #7, @er2, r1l - test_cc_clear - test_h_gr8 5 r1l - - set_ccr_zero - bfld #0x10, @er2, r1l - test_cc_clear - test_h_gr8 0 r1l - - set_ccr_zero - bfld #0x20, @er2, r1l - test_cc_clear - test_h_gr8 1 r1l - - set_ccr_zero - bfld #0xf0, @er2, r1l - test_cc_clear - test_h_gr8 0xa r1l - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 0xa5a5a50a er1 - test_h_gr32 byte_src er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - -bfld_imm8_abs16: - set_grs_a5a5 - - ;; bfld #xx:8, @aa:16, rd8 - set_ccr_zero - bfld #0x80, @byte_src:16, r1l - test_cc_clear - test_h_gr8 1 r1l - - set_ccr_zero - bfld #0x40, @byte_src:16, r1l - test_cc_clear - test_h_gr8 0 r1l - - set_ccr_zero - bfld #0xe0, @byte_src:16, r1l - test_cc_clear - test_h_gr8 0x5 r1l - - set_ccr_zero - bfld #0x3c, @byte_src:16, r1l - test_cc_clear - test_h_gr8 9 r1l - - set_ccr_zero - bfld #0xfe, @byte_src:16, r1l - test_cc_clear - test_h_gr8 0x52 r1l - - set_ccr_zero - bfld #0, @byte_src:16, r1l - test_cc_clear - test_h_gr8 0 r1l - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 0xa5a5a500 er1 - test_h_gr32 0xa5a5a5a5 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - -bfst_imm8_ind: - set_grs_a5a5 - mov #byte_dst, er2 - - ;; bfst rd8, #xx:8, @ers - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #1, @er2 -;;; .word 0x7d20 -;;; .word 0xf901 - - test_cc_clear - cmp.b #1, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #2, @er2 -;;; .word 0x7d20 -;;; .word 0xf902 - - test_cc_clear - cmp.b #2, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #7, @er2 -;;; .word 0x7d20 -;;; .word 0xf907 - - test_cc_clear - cmp.b #5, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0x10, @er2 -;;; .word 0x7d20 -;;; .word 0xf910 - - test_cc_clear - cmp.b #0x10, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0x20, @er2 -;;; .word 0x7d20 -;;; .word 0xf920 - - test_cc_clear - cmp.b #0x20, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0xf0, @er2 -;;; .word 0x7d20 -;;; .word 0xf9f0 - - test_cc_clear - cmp.b #0x50, @byte_dst - bne fail1:16 - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 0xa5a5a5a5 er1 - test_h_gr32 byte_dst er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - -bfst_imm8_abs32: - set_grs_a5a5 - - ;; bfst #xx:8, @aa:32, rd8 - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0x80, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf980 - - test_cc_clear - cmp.b #0x80, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0x40, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf940 - - test_cc_clear - cmp.b #0x40, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0xe0, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf9e0 - - test_cc_clear - cmp.b #0xa0, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0x3c, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf93c - - test_cc_clear - cmp.b #0x14, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0xfe, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf9fe - - test_cc_clear - cmp.b #0x4a, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf900 - - test_cc_clear - cmp.b #0x0, @byte_dst - bne fail1:16 - - mov.b #0, @byte_dst - set_ccr_zero - bfst r1l, #0x38, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf938 - - test_cc_clear - cmp.b #0x28, @byte_dst - bne fail1:16 - - ;; - ;; Now let's do one in which the bits in the destination - ;; are appropriately combined with the bits in the source. - ;; - - mov.b #0xc3, @byte_dst - set_ccr_zero - bfst r1l, #0x3c, @byte_dst:32 -;;; .word 0x6a38 -;;; .long byte_dst -;;; .word 0xf93c - - test_cc_clear - cmp.b #0xd7, @byte_dst - bne fail1:16 - - test_grs_a5a5 - -.endif - pass - - exit 0 - -fail1: fail - diff --git a/sim/testsuite/sim/h8300/biand.s b/sim/testsuite/sim/h8300/biand.s deleted file mode 100644 index c4cf285..0000000 --- a/sim/testsuite/sim/h8300/biand.s +++ /dev/null @@ -1,473 +0,0 @@ -# Hitachi H8 testcase 'biand', 'bior', 'bixor', 'bild', 'bist', 'bistz' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -byte_src: .byte 0xa5 -byte_dst: .byte 0 - - start - -biand_imm3_reg8: - set_grs_a5a5 - set_ccr_zero - ;; biand xx:3, reg8 - biand #6, r0l ; this should NOT set the carry flag. - test_cc_clear - biand #7, r0l ; this should NOT set the carry flag. - test_cc_clear - - orc #1, ccr ; set the carry flag - biand #6, r0l ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - biand #7, r0l ; this should clear the carry flag - test_cc_clear - - test_grs_a5a5 ; general registers should not be changed. - -biand_imm3_ind: - set_grs_a5a5 -.if (sim_cpu == h8300) - mov #byte_src, r1 - set_ccr_zero - ;; biand xx:3, ind - biand #6, @r1 ; this should NOT set the carry flag. - test_cc_clear - biand #7, @r1 ; this should NOT set the carry flag. - test_cc_clear - - orc #1, ccr ; set the carry flag - biand #6, @r1 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - biand #7, @r1 ; this should clear the carry flag - test_cc_clear -;;; test_h_gr16 byte_src r1 ;FIXME -.else - mov #byte_src, er1 - set_ccr_zero - ;; biand xx:3, ind - biand #6, @er1 ; this should NOT set the carry flag. - test_cc_clear - biand #7, @er1 ; this should NOT set the carry flag. - test_cc_clear - - orc #1, ccr ; set the carry flag - biand #6, @er1 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - biand #7, @er1 ; this should clear the carry flag - test_cc_clear - test_h_gr32 byte_src er1 -.endif ; h8300 - test_gr_a5a5 0 ; general registers should not be changed. - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -biand_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; biand xx:3, aa:8 - biand #6, @0x20:8 ; this should NOT set the carry flag. - test_cc_clear - biand #7, @0x20:8 ; this should NOT set the carry flag. - test_cc_clear - - orc #1, ccr ; set the carry flag - biand #6, @0x20:8 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - biand #7, @0x20:8 ; this should clear the carry flag - test_cc_clear - - test_grs_a5a5 ; general registers should not be changed. - -.if (sim_cpu > h8300h) -biand_imm3_abs16: - set_grs_a5a5 - set_ccr_zero - ;; biand xx:3, aa:16 - biand #6, @byte_src:16 ; this should NOT set the carry flag. - test_cc_clear - biand #7, @byte_src:16 ; this should NOT set the carry flag. - test_cc_clear - - orc #1, ccr ; set the carry flag - biand #6, @byte_src:16 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - biand #7, @byte_src:16 ; this should clear the carry flag - test_cc_clear - - test_grs_a5a5 ; general registers should not be changed. - -biand_imm3_abs32: - set_grs_a5a5 - set_ccr_zero - ;; biand xx:3, aa:32 - biand #6, @byte_src:32 ; this should NOT set the carry flag. - test_cc_clear - biand #7, @byte_src:32 ; this should NOT set the carry flag. - test_cc_clear - - orc #1, ccr ; set the carry flag - biand #6, @byte_src:32 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - biand #7, @byte_src:32 ; this should clear the carry flag - test_cc_clear - - test_grs_a5a5 ; general registers should not be changed. -.endif - -bior_imm3_reg8: - set_grs_a5a5 - set_ccr_zero - ;; bior xx:3, reg8 - bior #7, r0l ; this should NOT set the carry flag. - test_cc_clear - - bior #6, r0l ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - orc #1, ccr ; set the carry flag - bior #6, r0l ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - bior #7, r0l ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - test_grs_a5a5 ; general registers should not be changed. - -bior_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; bior xx:3, aa:8 - bior #7, @0x20:8 ; this should NOT set the carry flag. - test_cc_clear - bior #6, @0x20:8 ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - orc #1, ccr ; set the carry flag - bior #6, @0x20:8 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - bior #7, @0x20:8 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - test_grs_a5a5 ; general registers should not be changed. - -bixor_imm3_reg8: - set_grs_a5a5 - set_ccr_zero - ;; bixor xx:3, reg8 - bixor #7, r0l ; this should NOT set the carry flag. - test_cc_clear - - bixor #6, r0l ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - orc #1, ccr ; set the carry flag - bixor #7, r0l ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - bixor #6, r0l ; this should clear the carry flag - test_cc_clear - - test_grs_a5a5 ; general registers should not be changed. - -bixor_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; bixor xx:3, aa:8 - bixor #7, @0x20:8 ; this should NOT set the carry flag. - test_cc_clear - bixor #6, @0x20:8 ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - orc #1, ccr ; set the carry flag - bixor #7, @0x20:8 ; this should NOT clear the carry flag - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - bixor #6, @0x20:8 ; this should clear the carry flag - test_cc_clear - - test_grs_a5a5 ; general registers should not be changed. - -bild_imm3_reg8: - set_grs_a5a5 - set_ccr_zero - ;; bild xx:3, reg8 - bild #7, r0l ; this should NOT set the carry flag. - test_cc_clear - bild #6, r0l ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - test_grs_a5a5 ; general registers should not be changed. - -bild_imm3_ind: - set_grs_a5a5 -.if (sim_cpu == h8300) - mov #byte_src, r1 - set_ccr_zero - ;; bild xx:3, ind - bild #7, @r1 ; this should NOT set the carry flag. - test_cc_clear - bild #6, @r1 ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear -;;; test_h_gr16 byte_src r1 ;FIXME -.else - mov #byte_src, er1 - set_ccr_zero - ;; bild xx:3, ind - bild #7, @er1 ; this should NOT set the carry flag. - test_cc_clear - bild #6, @er1 ; this should NOT set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - test_h_gr32 byte_src er1 -.endif ; h8300 - test_gr_a5a5 0 ; general registers should not be changed. - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bild_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; bild xx:3, aa:8 - bild #7, @0x20:8 ; this should NOT set the carry flag. - test_cc_clear - bild #6, @0x20:8 ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - test_grs_a5a5 ; general registers should not be changed. - -.if (sim_cpu > h8300h) -bild_imm3_abs16: - set_grs_a5a5 - set_ccr_zero - ;; bild xx:3, aa:16 - bild #7, @byte_src:16 ; this should NOT set the carry flag. - test_cc_clear - bild #6, @byte_src:16 ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - test_grs_a5a5 ; general registers should not be changed. - -bild_imm3_abs32: - set_grs_a5a5 - set_ccr_zero - ;; bild xx:3, aa:32 - bild #7, @byte_src:32 ; this should NOT set the carry flag. - test_cc_clear - bild #6, @byte_src:32 ; this should set the carry flag. - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - - test_grs_a5a5 ; general registers should not be changed. -.endif - -bist_imm3_reg8: - set_grs_a5a5 - set_ccr_zero - ;; bist xx:3, reg8 - bist #6, r0l ; this should set bit 6 - test_cc_clear - test_h_gr16 0xa5e5 r0 - - set_ccr_zero - orc #1, ccr ; set the carry flag - bist #7, r0l ; this should clear bit 7 - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - test_h_gr16 0xa565 r0 - - test_gr_a5a5 1 ; Rest of general regs should not be changed. - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bist_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; bist xx:3, aa:8 - bist #6, @0x20:8 ; this should set bit 6 - test_cc_clear - mov.b @0x20, r0l - test_h_gr16 0xa5e5 r0 - - set_ccr_zero - orc #1, ccr ; set the carry flag - bist #7, @0x20:8 ; this should clear bit 7 - test_carry_set - test_ovf_clear - test_neg_clear - test_zero_clear - mov.b @0x20, r0l - test_h_gr16 0xa565 r0 - - test_gr_a5a5 1 ; general registers should not be changed. - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -bistz_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; bistz xx:3, aa:8 - bistz #6, @0x20:8 ; this should set bit 6 - test_cc_clear - mov.b @0x20, r0l - test_h_gr16 0xa5e5 r0 - - set_ccr_zero - orc #4, ccr ; set the zero flag - bistz #7, @0x20:8 ; this should clear bit 7 - test_carry_clear - test_ovf_clear - test_neg_clear - test_zero_set - mov.b @0x20, r0l - test_h_gr16 0xa565 r0 - - test_gr_a5a5 1 ; general registers should not be changed. - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx - -bnot_imm3_reg8: - set_grs_a5a5 - set_ccr_zero - ;; bnot xx:3, reg8 - bnot #7, r0l - test_cc_clear - test_h_gr16 0xa525 r0 - set_ccr_zero - bnot #6, r0l - test_cc_clear - test_h_gr16 0xa565 r0 - set_ccr_zero - bnot #5, r0l - test_cc_clear - test_h_gr16 0xa545 r0 - set_ccr_zero - bnot #4, r0l - test_cc_clear - test_h_gr16 0xa555 r0 - set_ccr_zero - - bnot #4, r0l - bnot #5, r0l - bnot #6, r0l - bnot #7, r0l - test_cc_clear - test_grs_a5a5 ; general registers should not be changed. - -bnot_imm3_abs8: - set_grs_a5a5 - mov.b r1l, @0x20 - set_ccr_zero - ;; bnot xx:3, aa:8 - bnot #7, @0x20:8 - bnot #6, @0x20:8 - bnot #5, @0x20:8 - bnot #4, @0x20:8 - test_cc_clear - test_grs_a5a5 - mov @0x20, r0l - test_h_gr16 0xa555 r0 - - pass - exit 0 diff --git a/sim/testsuite/sim/h8300/bra.s b/sim/testsuite/sim/h8300/bra.s deleted file mode 100644 index 2ec10dc..0000000 --- a/sim/testsuite/sim/h8300/bra.s +++ /dev/null @@ -1,165 +0,0 @@ -# Hitachi H8 testcase 'bra' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start -.if (sim_cpu == h8sx) - .data - .align 4 -disp8: .long tgt_reg8 -disp16: .long tgt_reg16 -disp32: .long tgt_reg32 -dslot: .byte 0 - .text -.endif - -bra_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; bra dd:8 ; 8-bit displacement - bra tgt_8:8 -;;; .word 0x40xx ; where "xx" is tgt_8 - '.'. - fail - -tgt_8: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; not available in h8/300 mode -bra_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; bra dd:16 ; 16-bit displacement - bra tgt_24:16 ; NOTE: hard-coded to avoid relaxing. -;;; .word 0x5800 -;;; .word tgt_24 - . - fail - -tgt_24: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu == h8sx) -bra_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; bra rn.b ; 8-bit register indirect - sub.l #src8, @disp8 - mov.l @disp8, er5 - bra r5l.b -;;; .word 0x5955 -src8: fail - -tgt_reg8: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 -;;; test_h_gr32 tgt_reg8 er5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bra_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; bra rn.w ; 16-bit register indirect - sub.l #src16, @disp16 - mov.l @disp16, er5 - bra r5.w -;;; .word 0x5956 -src16: fail - -tgt_reg16: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 -;;; test_h_gr32 tgt_reg16 er5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bra_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; bra ern ; 32-bit register indirect - sub.l #src32, @disp32 - mov.l @disp32, er5 - bra er5.l -;;; .word 0x5957 -src32: fail - -tgt_reg32: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 -;;; test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bra_s: set_grs_a5a5 - set_ccr_zero - - bra/s tgt_post_delay -;;; .word 0x4017 - ;; The following instruction is in the delay slot, and should execute. - mov.b #1, @dslot - ;; After this, the next instructions should not execute. - fail - -tgt_post_delay: - test_cc_clear - cmp.b #0, @dslot ; Should be non-zero if delay slot executed. - bne dslot_ok - fail - -dslot_ok: - test_gr_a5a5 0 ; Make sure all general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - - pass - exit 0 - - \ No newline at end of file diff --git a/sim/testsuite/sim/h8300/brabc.s b/sim/testsuite/sim/h8300/brabc.s deleted file mode 100644 index b9a08ea..0000000 --- a/sim/testsuite/sim/h8300/brabc.s +++ /dev/null @@ -1,116 +0,0 @@ -# Hitachi H8 testcase 'bra/bc' -# mach(): h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -byte_src: .byte 0xa5 - - start - -.if (sim_cpu == h8sx) -brabc_ind_disp8: - set_grs_a5a5 - mov #byte_src, er1 - set_ccr_zero - ;; bra/bc xx:3, @erd, disp8 - bra/bc #1, @er1, .Lpass1:8 -;;; .word 0x7c10 -;;; .word 0x4110 - fail -.Lpass1: - bra/bc #2, @er1, .Lfail1:8 -;;; .word 0x7c10 -;;; .word 0x4202 - bra .Lpass2 -.Lfail1: - fail -.Lpass2: - test_cc_clear - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 byte_src er1 - test_h_gr32 0xa5a5a5a5 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - -brabc_abs8_disp16: - set_grs_a5a5 - mov.b #0xa5, @0x20:32 - set_ccr_zero - ;; bra/bc xx:3, @aa:8, disp16 - bra/bc #1, @0x20:8, .Lpass3:16 - fail -.Lpass3: - bra/bc #2, @0x20:8, Lfail:16 - - test_cc_clear - test_grs_a5a5 - -brabc_abs16_disp16: - set_grs_a5a5 - set_ccr_zero - ;; bra/bc xx:3, @aa:16, disp16 - bra/bc #1, @byte_src:16, .Lpass5:16 - fail -.Lpass5: - bra/bc #2, @byte_src:16, Lfail:16 - - test_cc_clear - test_grs_a5a5 - -brabs_ind_disp8: - set_grs_a5a5 - mov #byte_src, er1 - set_ccr_zero - ;; bra/bs xx:3, @erd, disp8 - bra/bs #2, @er1, .Lpass7:8 -;;; .word 0x7c10 -;;; .word 0x4a10 - fail -.Lpass7: - bra/bs #1, @er1, .Lfail3:8 -;;; .word 0x7c10 -;;; .word 0x4902 - bra .Lpass8 -.Lfail3: - fail -.Lpass8: - test_cc_clear - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 byte_src er1 - test_h_gr32 0xa5a5a5a5 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - -brabs_abs32_disp16: - set_grs_a5a5 - set_ccr_zero - ;; bra/bs xx:3, @aa:32, disp16 - bra/bs #2, @byte_src:32, .Lpass9:16 - fail -.Lpass9: - bra/bs #1, @byte_src:32, Lfail:16 - - test_cc_clear - test_grs_a5a5 - -.endif - - pass - - exit 0 - -Lfail: fail diff --git a/sim/testsuite/sim/h8300/bset.s b/sim/testsuite/sim/h8300/bset.s deleted file mode 100644 index 0e16fc1..0000000 --- a/sim/testsuite/sim/h8300/bset.s +++ /dev/null @@ -1,890 +0,0 @@ -# Hitachi H8 testcase 'bset', 'bclr' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # - # bset xx:3, rd8 ; 7 0 ?xxx rd8 - # bclr xx:3, rd8 ; 7 2 ?xxx rd8 - # bset xx:3, @erd ; 7 d 0rd ???? 7 0 ?xxx ???? - # bclr xx:3, @erd ; 7 d 0rd ???? 7 2 ?xxx ???? - # bset xx:3, @abs16 ; 6 a 1 1??? aa:16 7 0 ?xxx ???? - # bclr xx:3, @abs16 ; 6 a 1 1??? aa:16 7 2 ?xxx ???? - # bset reg8, rd8 ; 6 0 rs8 rd8 - # bclr reg8, rd8 ; 6 2 rs8 rd8 - # bset reg8, @erd ; 7 d 0rd ???? 6 0 rs8 ???? - # bclr reg8, @erd ; 7 d 0rd ???? 6 2 rs8 ???? - # bset reg8, @abs32 ; 6 a 3 1??? aa:32 6 0 rs8 ???? - # bclr reg8, @abs32 ; 6 a 3 1??? aa:32 6 2 rs8 ???? - # - # bset/eq xx:3, rd8 - # bclr/eq xx:3, rd8 - # bset/ne xx:3, rd8 - # bclr/ne xx:3, rd8 - - .data -byte_dst: .byte 0 - - start - -bset_imm3_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset xx:3, rd8 - mov #0, r1l - set_ccr_zero - bset #0, r1l - test_cc_clear - test_h_gr8 1 r1l - - set_ccr_zero - bset #1, r1l - test_cc_clear - test_h_gr8 3 r1l - - set_ccr_zero - bset #2, r1l - test_cc_clear - test_h_gr8 7 r1l - - set_ccr_zero - bset #3, r1l - test_cc_clear - test_h_gr8 15 r1l - - set_ccr_zero - bset #4, r1l - test_cc_clear - test_h_gr8 31 r1l - - set_ccr_zero - bset #5, r1l - test_cc_clear - test_h_gr8 63 r1l - - set_ccr_zero - bset #6, r1l - test_cc_clear - test_h_gr8 127 r1l - - set_ccr_zero - bset #7, r1l - test_cc_clear - test_h_gr8 255 r1l - -.if (sim_cpu == h8300) - test_h_gr16 0xa5ff, r1 -.else - test_h_gr32 0xa5a5a5ff er1 -.endif - -bclr_imm3_reg8: - set_ccr_zero - bclr #7, r1l - test_cc_clear - test_h_gr8 127 r1l - - set_ccr_zero - bclr #6, r1l - test_cc_clear - test_h_gr8 63 r1l - - set_ccr_zero - bclr #5, r1l - test_cc_clear - test_h_gr8 31 r1l - - set_ccr_zero - bclr #4, r1l - test_cc_clear - test_h_gr8 15 r1l - - set_ccr_zero - bclr #3, r1l - test_cc_clear - test_h_gr8 7 r1l - - set_ccr_zero - bclr #2, r1l - test_cc_clear - test_h_gr8 3 r1l - - set_ccr_zero - bclr #1, r1l - test_cc_clear - test_h_gr8 1 r1l - - set_ccr_zero - bclr #0, r1l - test_cc_clear - test_h_gr8 0 r1l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed -.if (sim_cpu == h8300) - test_h_gr16 0xa500 r1 -.else - test_h_gr32 0xa5a5a500 er1 -.endif - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) -bset_imm3_ind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset xx:3, @erd - mov #byte_dst, er1 - set_ccr_zero - bset #0, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 1 r2l - - set_ccr_zero - bset #1, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 3 r2l - - set_ccr_zero - bset #2, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 7 r2l - - set_ccr_zero - bset #3, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 15 r2l - - set_ccr_zero - bset #4, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 31 r2l - - set_ccr_zero - bset #5, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 63 r2l - - set_ccr_zero - bset #6, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 127 r2l - - set_ccr_zero - bset #7, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 255 r2l - -.if (sim_cpu == h8300) - test_h_gr16 0xa5ff r2 -.else - test_h_gr32 0xa5a5a5ff er2 -.endif - -bclr_imm3_ind: - set_ccr_zero - bclr #7, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 127 r2l - - set_ccr_zero - bclr #6, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 63 r2l - - set_ccr_zero - bclr #5, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 31 r2l - - set_ccr_zero - bclr #4, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 15 r2l - - set_ccr_zero - bclr #3, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 7 r2l - - set_ccr_zero - bclr #2, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 3 r2l - - set_ccr_zero - bclr #1, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 1 r2l - - set_ccr_zero - bclr #0, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 0 r2l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed -.if (sim_cpu == h8300) - test_h_gr16 byte_dst r1 - test_h_gr16 0xa500 r2 -.else - test_h_gr32 byte_dst er1 - test_h_gr32 0xa5a5a500 er2 -.endif - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu > h8300h) -bset_imm3_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset xx:3, @aa:16 - set_ccr_zero - bset #0, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 1 r2l - - set_ccr_zero - bset #1, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 3 r2l - - set_ccr_zero - bset #2, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 7 r2l - - set_ccr_zero - bset #3, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 15 r2l - - set_ccr_zero - bset #4, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 31 r2l - - set_ccr_zero - bset #5, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 63 r2l - - set_ccr_zero - bset #6, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 127 r2l - - set_ccr_zero - bset #7, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 255 r2l - -.if (sim_cpu == h8300) - test_h_gr16 0xa5ff r2 -.else - test_h_gr32 0xa5a5a5ff er2 -.endif - -bclr_imm3_abs16: - set_ccr_zero - bclr #7, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 127 r2l - - set_ccr_zero - bclr #6, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 63 r2l - - set_ccr_zero - bclr #5, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 31 r2l - - set_ccr_zero - bclr #4, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 15 r2l - - set_ccr_zero - bclr #3, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 7 r2l - - set_ccr_zero - bclr #2, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 3 r2l - - set_ccr_zero - bclr #1, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 1 r2l - - set_ccr_zero - bclr #0, @byte_dst:16 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 0 r2l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 -.if (sim_cpu == h8300) - test_h_gr16 0xa500 r2 -.else - test_h_gr32 0xa5a5a500 er2 -.endif - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif -.endif - -bset_rs8_rd8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset rs8, rd8 - mov #0, r1h - mov #0, r1l - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 1 r1l - - mov #1, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 3 r1l - - mov #2, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 7 r1l - - mov #3, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 15 r1l - - mov #4, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 31 r1l - - mov #5, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 63 r1l - - mov #6, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 127 r1l - - mov #7, r1h - set_ccr_zero - bset r1h, r1l - test_cc_clear - test_h_gr8 255 r1l - -.if (sim_cpu == h8300) - test_h_gr16 0x07ff, r1 -.else - test_h_gr32 0xa5a507ff er1 -.endif - -bclr_rs8_rd8: - mov #7, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 127 r1l - - mov #6, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 63 r1l - - mov #5, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 31 r1l - - mov #4, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 15 r1l - - mov #3, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 7 r1l - - mov #2, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 3 r1l - - mov #1, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 1 r1l - - mov #0, r1h - set_ccr_zero - bclr r1h, r1l - test_cc_clear - test_h_gr8 0 r1l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed -.if (sim_cpu == h8300) - test_h_gr16 0x0000 r1 -.else - test_h_gr32 0xa5a50000 er1 -.endif - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) -bset_rs8_ind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset rs8, @erd - mov #byte_dst, er1 - mov #0, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 1 r2l - - mov #1, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 3 r2l - - mov #2, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 7 r2l - - mov #3, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 15 r2l - - mov #4, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 31 r2l - - mov #5, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 63 r2l - - mov #6, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 127 r2l - - mov #7, r2h - set_ccr_zero - bset r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 255 r2l - -.if (sim_cpu == h8300) - test_h_gr16 0x07ff r2 -.else - test_h_gr32 0xa5a507ff er2 -.endif - -bclr_rs8_ind: - mov #7, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 127 r2l - - mov #6, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 63 r2l - - mov #5, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 31 r2l - - mov #4, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 15 r2l - - mov #3, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 7 r2l - - mov #2, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 3 r2l - - mov #1, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 1 r2l - - mov #0, r2h - set_ccr_zero - bclr r2h, @er1 - test_cc_clear - mov @er1, r2l - test_h_gr8 0 r2l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed -.if (sim_cpu == h8300) - test_h_gr16 byte_dst r1 - test_h_gr16 0x0000 r2 -.else - test_h_gr32 byte_dst er1 - test_h_gr32 0xa5a50000 er2 -.endif - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu > h8300h) -bset_rs8_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset rs8, @aa:32 - mov #0, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 1 r2l - - mov #1, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 3 r2l - - mov #2, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 7 r2l - - mov #3, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 15 r2l - - mov #4, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 31 r2l - - mov #5, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 63 r2l - - mov #6, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 127 r2l - - mov #7, r2h - set_ccr_zero - bset r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 255 r2l - -.if (sim_cpu == h8300) - test_h_gr16 0x07ff r2 -.else - test_h_gr32 0xa5a507ff er2 -.endif - -bclr_rs8_abs32: - mov #7, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 127 r2l - - mov #6, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 63 r2l - - mov #5, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 31 r2l - - mov #4, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 15 r2l - - mov #3, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 7 r2l - - mov #2, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 3 r2l - - mov #1, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 1 r2l - - mov #0, r2h - set_ccr_zero - bclr r2h, @byte_dst:32 - test_cc_clear - mov @byte_dst, r2l - test_h_gr8 0 r2l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 -.if (sim_cpu == h8300) - test_h_gr16 0x0000 r2 -.else - test_h_gr32 0xa5a50000 er2 -.endif - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif -.endif - -.if (sim_cpu == h8sx) -bset_eq_imm3_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset/eq xx:3, rd8 - mov #0, @byte_dst - set_ccr_zero - bset/eq #0, @byte_dst:16 ; Zero is clear, should have no effect. - test_cc_clear - mov @byte_dst, r1l - test_h_gr8 0 r1l - - set_ccr_zero - orc #4, ccr ; Set zero flag - bset/eq #0, @byte_dst:16 ; Zero is set: operation should succeed. - - test_neg_clear - test_zero_set - test_ovf_clear - test_carry_clear - - mov @byte_dst, r1l - test_h_gr8 1 r1l - -bclr_eq_imm3_abs32: - mov #1, @byte_dst - set_ccr_zero - bclr/eq #0, @byte_dst:32 ; Zero is clear, should have no effect. - test_cc_clear - mov @byte_dst, r1l - test_h_gr8 1 r1l - - set_ccr_zero - orc #4, ccr ; Set zero flag - bclr/eq #0, @byte_dst:32 ; Zero is set: operation should succeed. - test_neg_clear - test_zero_set - test_ovf_clear - test_carry_clear - mov @byte_dst, r1l - test_h_gr8 0 r1l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 0xa5a5a500 er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -bset_ne_imm3_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; bset/ne xx:3, aa:16 - mov #0, @byte_dst - set_ccr_zero - orc #4, ccr ; Set zero flag - bset/ne #0, @byte_dst:16 ; Zero is set; should have no effect. - test_zero_set - test_neg_clear - test_ovf_clear - test_carry_clear - mov @byte_dst, r1l - test_h_gr8 0 r1l - - set_ccr_zero - bset/ne #0, @byte_dst:16 ; Zero is clear: operation should succeed. - test_cc_clear - mov @byte_dst, r1l - test_h_gr8 1 r1l - -bclr_ne_imm3_abs32: - mov #1, @byte_dst - set_ccr_zero - orc #4, ccr ; Set zero flag - ;; bclr/ne xx:3, aa:16 - bclr/ne #0, @byte_dst:32 ; Zero is set, should have no effect. - test_neg_clear - test_zero_set - test_ovf_clear - test_carry_clear - mov @byte_dst, r1l - test_h_gr8 1 r1l - - set_ccr_zero - bclr/ne #0, @byte_dst:32 ; Zero is clear: operation should succeed. - test_cc_clear - mov @byte_dst, r1l - test_h_gr8 0 r1l - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 0xa5a5a500 er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - - pass - exit 0 diff --git a/sim/testsuite/sim/h8300/cmpb.s b/sim/testsuite/sim/h8300/cmpb.s deleted file mode 100644 index 1a4f23c..0000000 --- a/sim/testsuite/sim/h8300/cmpb.s +++ /dev/null @@ -1,1086 +0,0 @@ -# Hitachi H8 testcase 'cmp.b' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # cmp.b #xx:8, rd ; a rd xxxxxxxx - # cmp.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx - # cmp.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx - # cmp.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx - # cmp.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx - # cmp.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx - # cmp.b rs, rd ; 1 c rs rd - # cmp.b reg8, @erd ; 7 d rd ???? 1 c rs ???? - # cmp.b reg8, @erd+ ; 0 1 7 9 8 rd 2 rs - # cmp.b reg8, @erd- ; 0 1 7 9 a rd 2 rs - # cmp.b reg8, @+erd ; 0 1 7 9 9 rd 2 rs - # cmp.b reg8, @-erd ; 0 1 7 9 b rd 2 rs - # cmp.b rsind, rdind ; 7 c 0rs 5 0 ?rd 2 ???? - # cmp.b rspostinc, rdpostinc ; 0 1 7 4 6 c 0rs c 8 ?rd 2 ???? - # cmp.b rspostdec, rdpostdec ; 0 1 7 6 6 c 0rs c a ?rd 2 ???? - # cmp.b rspreinc, rdpreinc ; 0 1 7 5 6 c 0rs c 9 ?rd 2 ???? - # cmp.b rspredec, rdpredec ; 0 1 7 7 6 c 0rs c b ?rd 2 ???? - # cmp.b disp2, disp2 ; 0 1 7 01dd:2 6 8 0rs c 00dd:2 ?rd 2 ???? - # cmp.b disp16, disp16 ; 0 1 7 4 6 e 0rs c dd:16 c 0rd 2 ???? dd:16 - # cmp.b disp32, disp32 ; 7 8 0rs 4 6 a 2 c dd:32 c 1rd 2 ???? dd:32 - # cmp.b indexb16, indexb16 ; 0 1 7 5 6 e 0rs c dd:16 d 0rd 2 ???? dd:16 - # cmp.b indexw16, indexw16 ; 0 1 7 6 6 e 0rs c dd:16 e 0rd 2 ???? dd:16 - # cmp.b indexl16, indexl16 ; 0 1 7 7 6 e 0rs c dd:16 f 0rd 2 ???? dd:16 - # cmp.b indexb32, indexb32 ; 7 8 0rs 5 6 a 2 c dd:32 d 1rd 2 ???? dd:32 - # cmp.b indexw32, indexw32 ; 7 8 0rs 6 6 a 2 c dd:32 e 1rd 2 ???? dd:32 - # cmp.b indexl32, indexl32 ; 7 8 0rs 7 6 a 2 c dd:32 f 1rd 2 ???? dd:32 - # cmp.b abs16, abs16 ; 6 a 1 5 aa:16 4 0??? 2 ???? aa:16 - # cmp.b abs32, abs32 ; 6 a 3 5 aa:32 4 1??? 2 ???? aa:32 - # - - # Coming soon: - - # ... - -.data -byte_src: .byte 0x5a -pre_byte: .byte 0 -byte_dst: .byte 0xa5 -post_byte: .byte 0 - - start - -cmp_b_imm8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.b #xx:8,Rd - cmp.b #0xa5, r0l ; Immediate 8-bit src, reg8 dest - beq .Leq1 - fail -.Leq1: cmp.b #0xa6, r0l - blt .Llt1 - fail -.Llt1: cmp.b #0xa4, r0l - bgt .Lgt1 - fail -.Lgt1: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a5 r0 ; r0 unchanged -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -cmp_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b #xx:8,@eRd - mov #byte_dst, er0 - cmp.b #0xa5:8, @er0 ; Immediate 8-bit src, reg indirect dst -;;; .word 0x7d00 -;;; .word 0xa0a5 - beq .Leq2 - fail -.Leq2: set_ccr_zero - cmp.b #0xa6, @er0 -;;; .word 0x7d00 -;;; .word 0xa0a6 - blt .Llt2 - fail -.Llt2: set_ccr_zero - cmp.b #0xa4, @er0 -;;; .word 0x7d00 -;;; .word 0xa0a4 - bgt .Lgt2 - fail -.Lgt2: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dst er0 ; er0 still contains address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dst, r0l - cmp.b #0xa5, r0l - beq .L2 - fail -.L2: - -cmp_b_imm8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b #xx:8,@eRd+ - mov #byte_dst, er0 - cmp.b #0xa5:8, @er0+ ; Immediate 8-bit src, reg postinc dst -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xa0a5 - beq .Leq3 - fail -.Leq3: test_h_gr32 post_byte er0 ; er0 contains address plus one - mov #byte_dst, er0 - set_ccr_zero - cmp.b #0xa6, @er0+ -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xa0a6 - blt .Llt3 - fail -.Llt3: test_h_gr32 post_byte er0 ; er0 contains address plus one - mov #byte_dst, er0 - set_ccr_zero - cmp.b #0xa4, @er0+ -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xa0a4 - bgt .Lgt3 - fail -.Lgt3: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dst, r0l - cmp.b #0xa5, r0l - beq .L3 - fail -.L3: - -cmp_b_imm8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b #xx:8,@eRd- - mov #byte_dst, er0 - cmp.b #0xa5:8, @er0- ; Immediate 8-bit src, reg postdec dst -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xa0a5 - beq .Leq4 - fail -.Leq4: test_h_gr32 pre_byte er0 ; er0 contains address minus one - mov #byte_dst, er0 - set_ccr_zero - cmp.b #0xa6, @er0- -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xa0a6 - blt .Llt4 - fail -.Llt4: test_h_gr32 pre_byte er0 ; er0 contains address minus one - mov #byte_dst, er0 - set_ccr_zero - cmp.b #0xa4, @er0- -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xa0a4 - bgt .Lgt4 - fail -.Lgt4: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dst, r0l - cmp.b #0xa5, r0l - beq .L4 - fail -.L4: - -cmp_b_imm8_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b #xx:8,@+eRd - mov #pre_byte, er0 - cmp.b #0xa5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0xa0a5 - beq .Leq5 - fail -.Leq5: test_h_gr32 byte_dst er0 ; er0 contains destination address - mov #pre_byte, er0 - set_ccr_zero - cmp.b #0xa6, @+er0 -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0xa0a6 - blt .Llt5 - fail -.Llt5: test_h_gr32 byte_dst er0 ; er0 contains destination address - mov #pre_byte, er0 - set_ccr_zero - cmp.b #0xa4, @+er0 -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0xa0a4 - bgt .Lgt5 - fail -.Lgt5: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dst er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dst, r0l - cmp.b #0xa5, r0l - beq .L5 - fail -.L5: - -cmp_b_imm8_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b #xx:8,@-eRd - mov #post_byte, er0 - cmp.b #0xa5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0xa0a5 - beq .Leq6 - fail -.Leq6: test_h_gr32 byte_dst er0 ; er0 contains destination address - mov #post_byte, er0 - set_ccr_zero - cmp.b #0xa6, @-er0 -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0xa0a6 - blt .Llt6 - fail -.Llt6: test_h_gr32 byte_dst er0 ; er0 contains destination address - mov #post_byte, er0 - set_ccr_zero - cmp.b #0xa4, @-er0 -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0xa0a4 - bgt .Lgt6 - fail -.Lgt6: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dst er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dst, r0l - cmp.b #0xa5, r0l - beq .L6 - fail -.L6: - - -.endif - -cmp_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.b Rs,Rd - mov.b #0xa5, r0h - cmp.b r0h, r0l ; Reg8 src, reg8 dst - beq .Leq7 - fail -.Leq7: mov.b #0xa6, r0h - cmp.b r0h, r0l - blt .Llt7 - fail -.Llt7: mov.b #0xa4, r0h - cmp.b r0h, r0l - bgt .Lgt7 - fail -.Lgt7: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa4a5 r0 ; r0l unchanged. -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a4a5 er0 ; r0l unchanged -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -cmp_b_reg8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b rs8,@eRd ; cmp reg8 to register indirect - mov #byte_dst, er0 - mov #0xa5, r1l - cmp.b r1l, @er0 ; reg8 src, reg indirect dest -;;; .word 0x7d00 -;;; .word 0x1c90 - beq .Leq8 - fail -.Leq8: set_ccr_zero - mov #0xa6, r1l - cmp.b r1l, @er0 -;;; .word 0x7d00 -;;; .word 0x1c90 - blt .Llt8 - fail -.Llt8: set_ccr_zero - mov #0xa4, r1l - cmp.b r1l, @er0 -;;; .word 0x7d00 -;;; .word 0x1c90 - bgt .Lgt8 - fail -.Lgt8: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dst er0 ; er0 still contains address - test_h_gr32 0xa5a5a5a4 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (no change). - sub.b r0l, r0l - mov.b @byte_dst, r0l - cmp.b #0xa5, r0l - beq .L8 - fail -.L8: - -cmp_b_reg8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b reg8,@eRd+ - mov #byte_dst, er0 - mov #0xa5, r1l - cmp.b r1l, @er0+ ; Immediate 8-bit src, reg post-incr dst -;;; .word 0x0179 -;;; .word 0x8029 - beq .Leq9 - fail -.Leq9: test_h_gr32 post_byte er0 ; er0 contains address plus one - mov #byte_dst er0 - mov #0xa6, r1l - set_ccr_zero - cmp.b r1l, @er0+ -;;; .word 0x0179 -;;; .word 0x8029 - blt .Llt9 - fail -.Llt9: test_h_gr32 post_byte er0 ; er0 contains address plus one - mov #byte_dst er0 - mov #0xa4, r1l - set_ccr_zero - cmp.b r1l, @er0+ -;;; .word 0x0179 -;;; .word 0x8029 - bgt .Lgt9 - fail -.Lgt9: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dst, r0l - cmp.b #0xa5, r0l - beq .L9 - fail -.L9: - -cmp_b_reg8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b reg8,@eRd- - mov #byte_dst, er0 - mov #0xa5, r1l - cmp.b r1l, @er0- ; Immediate 8-bit src, reg postdec dst -;;; .word 0x0179 -;;; .word 0xa029 - beq .Leq10 - fail -.Leq10: test_h_gr32 pre_byte er0 ; er0 contains address minus one - mov #byte_dst er0 - mov #0xa6, r1l - set_ccr_zero - cmp.b r1l, @er0- -;;; .word 0x0179 -;;; .word 0xa029 - blt .Llt10 - fail -.Llt10: test_h_gr32 pre_byte er0 ; er0 contains address minus one - mov #byte_dst er0 - mov #0xa4, r1l - set_ccr_zero - cmp.b r1l, @er0- -;;; .word 0x0179 -;;; .word 0xa029 - bgt .Lgt10 - fail -.Lgt10: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dst, r0l - cmp.b #0xa5, r0l - beq .L10 - fail -.L10: - -cmp_b_reg8_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b reg8,@+eRd - mov #pre_byte, er0 - mov #0xa5, r1l - cmp.b r1l, @+er0 ; Immediate 8-bit src, reg post-incr dst -;;; .word 0x0179 -;;; .word 0x9029 - beq .Leq11 - fail -.Leq11: test_h_gr32 byte_dst er0 ; er0 contains destination address - mov #pre_byte er0 - mov #0xa6, r1l - set_ccr_zero - cmp.b r1l, @+er0 -;;; .word 0x0179 -;;; .word 0x9029 - blt .Llt11 - fail -.Llt11: test_h_gr32 byte_dst er0 ; er0 contains destination address - mov #pre_byte er0 - mov #0xa4, r1l - set_ccr_zero - cmp.b r1l, @+er0 -;;; .word 0x0179 -;;; .word 0x9029 - bgt .Lgt11 - fail -.Lgt11: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dst er0 ; er0 contains destination address - test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dst, r0l - cmp.b #0xa5, r0l - beq .L11 - fail -.L11: - -cmp_b_reg8_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; cmp.b reg8,@-eRd - mov #post_byte, er0 - mov #0xa5, r1l - cmp.b r1l, @-er0 ; Immediate 8-bit src, reg postdec dst -;;; .word 0x0179 -;;; .word 0xb029 - beq .Leq12 - fail -.Leq12: test_h_gr32 byte_dst er0 ; er0 contains destination address - mov #post_byte er0 - mov #0xa6, r1l - set_ccr_zero - cmp.b r1l, @-er0 -;;; .word 0x0179 -;;; .word 0xb029 - blt .Llt12 - fail -.Llt12: test_h_gr32 byte_dst er0 ; er0 contains destination address - mov #post_byte er0 - mov #0xa4, r1l - set_ccr_zero - cmp.b r1l, @-er0 -;;; .word 0x0179 -;;; .word 0xb029 - bgt .Lgt12 - fail -.Lgt12: - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dst er0 ; er0 contains destination address - test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the cmp to memory (memory unchanged). - sub.b r0l, r0l - mov.b @byte_dst, r0l - cmp.b #0xa5, r0l - beq .L12 - fail -.L12: - -cmp_b_rsind_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #byte_src, er1 - mov #byte_dst, er2 - set_ccr_zero - cmp.b @er1, @er2 - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 byte_src er1 - test_h_gr32 byte_dst er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 -.if 1 ; ambiguous -cmp_b_rspostinc_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #byte_src, er1 - mov #byte_dst, er2 - set_ccr_zero - cmp.b @er1+, @er2+ -;;; .word 0x0174 -;;; .word 0x6c1c -;;; .word 0x8220 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 byte_src+1 er1 - test_h_gr32 byte_dst+1 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 -.endif -.if 1 ; ambiguous -cmp_b_rspostdec_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #byte_src, er1 - mov #byte_dst, er2 - set_ccr_zero - cmp.b @er1-, @er2- -;;; .word 0x0176 -;;; .word 0x6c1c -;;; .word 0xa220 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 byte_src-1 er1 - test_h_gr32 byte_dst-1 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 -.endif - -cmp_b_rspreinc_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #byte_src-1, er1 - mov #byte_dst-1, er2 - set_ccr_zero - cmp.b @+er1, @+er2 -;;; .word 0x0175 -;;; .word 0x6c1c -;;; .word 0x9220 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 byte_src er1 - test_h_gr32 byte_dst er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 - -cmp_b_rspredec_predec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #byte_src+1, er1 - mov #byte_dst+1, er2 - set_ccr_zero - cmp.b @-er1, @-er2 -;;; .word 0x0177 -;;; .word 0x6c1c -;;; .word 0xb220 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 byte_src er1 - test_h_gr32 byte_dst er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 - -cmp_b_disp2_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #byte_src-1, er1 - mov #byte_dst-2, er2 - set_ccr_zero - cmp.b @(1:2, er1), @(2:2, er2) -;;; .word 0x0175 -;;; .word 0x681c -;;; .word 0x2220 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 byte_src-1 er1 - test_h_gr32 byte_dst-2 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 - -cmp_b_disp16_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #byte_src-3, er1 - mov #byte_dst-4, er2 - set_ccr_zero - cmp.b @(3:16, er1), @(4:16, er2) -;;; .word 0x0174 -;;; .word 0x6e1c -;;; .word 3 -;;; .word 0xc220 -;;; .word 4 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 byte_src-3 er1 - test_h_gr32 byte_dst-4 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 - -cmp_b_disp32_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #byte_src+5, er1 - mov #byte_dst+6, er2 - set_ccr_zero - cmp.b @(-5:32, er1), @(-6:32, er2) -;;; .word 0x7814 -;;; .word 0x6a2c -;;; .long -5 -;;; .word 0xca20 -;;; .long -6 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 byte_src+5 er1 - test_h_gr32 byte_dst+6 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 - -cmp_b_indexb16_indexb16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #0xffffff01, er1 - mov #0xffffff02, er2 - set_ccr_zero - cmp.b @(byte_src-1:16, r1.b), @(byte_dst-2:16, r2.b) -;;; .word 0x0175 -;;; .word 0x6e1c -;;; .word byte_src-1 -;;; .word 0xd220 -;;; .word byte_dst-2 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 0xffffff01 er1 - test_h_gr32 0xffffff02 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 -.if 1 ; ambiguous -cmp_b_indexw16_indexw16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #0xffff0003, er1 - mov #0xffff0004, er2 - set_ccr_zero - cmp.b @(byte_src-3:16, r1.w), @(byte_dst-4:16, r2.w) -;;; .word 0x0176 -;;; .word 0x6e1c -;;; .word byte_src-3 -;;; .word 0xe220 -;;; .word byte_dst-4 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 0xffff0003 er1 - test_h_gr32 0xffff0004 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 -.endif - -cmp_b_indexl16_indexl16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #0x00000005, er1 - mov #0x00000006, er2 - set_ccr_zero - cmp.b @(byte_src-5:16, er1.l), @(byte_dst-6:16, er2.l) -;;; .word 0x0177 -;;; .word 0x6e1c -;;; .word byte_src-5 -;;; .word 0xf220 -;;; .word byte_dst-6 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 0x00000005 er1 - test_h_gr32 0x00000006 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 - -cmp_b_indexb32_indexb32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #0xffffff01, er1 - mov #0xffffff02, er2 - set_ccr_zero - cmp.b @(byte_src-1:32, r1.b), @(byte_dst-2:32, r2.b) -;;; .word 0x7815 -;;; .word 0x6a2c -;;; .long byte_src-1 -;;; .word 0xda20 -;;; .long byte_dst-2 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 0xffffff01 er1 - test_h_gr32 0xffffff02 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 - -.if 1 ; ambiguous -cmp_b_indexw32_indexw32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #0xffff0003, er1 - mov #0xffff0004, er2 - set_ccr_zero - cmp.b @(byte_src-3:32, r1.w), @(byte_dst-4:32, r2.w) -;;; .word 0x7816 -;;; .word 0x6a2c -;;; .long byte_src-3 -;;; .word 0xea20 -;;; .long byte_dst-4 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 0xffff0003 er1 - test_h_gr32 0xffff0004 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 -.endif - -cmp_b_indexl32_indexl32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov #0x00000005, er1 - mov #0x00000006, er2 - set_ccr_zero - cmp.b @(byte_src-5:32, er1.l), @(byte_dst-6:32, er2.l) -;;; .word 0x7817 -;;; .word 0x6a2c -;;; .long byte_src-5 -;;; .word 0xfa20 -;;; .long byte_dst-6 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_gr_a5a5 0 - test_h_gr32 0x00000005 er1 - test_h_gr32 0x00000006 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 - -cmp_b_abs16_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - cmp.b @byte_src:16, @byte_dst:16 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_grs_a5a5 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 - -cmp_b_abs32_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - cmp.b @byte_src:32, @byte_dst:32 - - test_neg_clear ; N=0, Z=0, V=1, C=0 - test_zero_clear - test_ovf_set - test_carry_clear - - test_grs_a5a5 - cmp.b #0x5a, @byte_src:16 - bne fail1 - cmp.b #0xa5, @byte_dst:16 - bne fail1 - -.endif - pass - - exit 0 - -fail1: fail diff --git a/sim/testsuite/sim/h8300/cmpl.s b/sim/testsuite/sim/h8300/cmpl.s deleted file mode 100644 index 55f235a..0000000 --- a/sim/testsuite/sim/h8300/cmpl.s +++ /dev/null @@ -1,106 +0,0 @@ -# Hitachi H8 testcase 'cmp.w' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx -cmp_l_imm3: ; - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.l #xx:3,eRd ; Immediate 3-bit operand - mov.l #5, er0 - cmp.l #5, er0 - beq eq3 - fail -eq3: - cmp.l #6, er0 - blt lt3 - fail -lt3: - cmp.l #4, er0 - bgt gt3 - fail -gt3: - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0x00000005 er0 ; er0 unchanged - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -cmp_l_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.l #xx:8,Rd - cmp.l #0xa5a5a5a5, er0 ; Immediate 16-bit operand - beq eqi - fail -eqi: cmp.l #0xa5a5a5a6, er0 - blt lti - fail -lti: cmp.l #0xa5a5a5a4, er0 - bgt gti - fail -gti: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -cmp_w_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.l Rs,Rd - mov.l #0xa5a5a5a5, er1 - cmp.l er1, er0 ; Register operand - beq eqr - fail -eqr: mov.l #0xa5a5a5a6, er1 - cmp.l er1, er0 - blt ltr - fail -ltr: mov.l #0xa5a5a5a4, er1 - cmp.l er1, er0 - bgt gtr - fail -gtr: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged - test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/cmpw.s b/sim/testsuite/sim/h8300/cmpw.s deleted file mode 100644 index 872c56c..0000000 --- a/sim/testsuite/sim/h8300/cmpw.s +++ /dev/null @@ -1,126 +0,0 @@ -# Hitachi H8 testcase 'cmp.w' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx -cmp_w_imm3: ; - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.w #xx:3,Rd ; Immediate 3-bit operand - mov.w #5, r0 - cmp.w #5, r0 - beq eq3 - fail -eq3: - cmp.w #6, r0 - blt lt3 - fail -lt3: - cmp.w #4, r0 - bgt gt3 - fail -gt3: - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr32 0xa5a50005 er0 ; er0 unchanged - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -cmp_w_imm16: ; cmp.w immediate not available in h8300 mode. - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.w #xx:16,Rd - cmp.w #0xa5a5, r0 ; Immediate 16-bit operand - beq eqi - fail -eqi: cmp.w #0xa5a6, r0 - blt lti - fail -lti: cmp.w #0xa5a4, r0 - bgt gti - fail -gti: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a5 r0 ; r0 unchanged -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -cmp_w_imm16_less_than_zero: ; Test for less-than-zero immediate - set_grs_a5a5 - ;; cmp.w #xx:16, Rd, where #xx < 0 (ie. #xx > 0x7fff). - sub.w r0, r0 - cmp.w #0x8001, r0 - bls ltz - fail -ltz: test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - -cmp_w_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; cmp.w Rs,Rd - mov.w #0xa5a5, r1 - cmp.w r1, r0 ; Register operand - beq eqr - fail -eqr: mov.w #0xa5a6, r1 - cmp.w r1, r0 - blt ltr - fail -ltr: mov.w #0xa5a4, r1 - cmp.w r1, r0 - bgt gtr - fail -gtr: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a5 r0 ; r0 unchanged. - test_h_gr16 0xa5a4 r1 ; r1 unchanged. -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged - test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/daa.s b/sim/testsuite/sim/h8300/daa.s deleted file mode 100644 index 5f81eba..0000000 --- a/sim/testsuite/sim/h8300/daa.s +++ /dev/null @@ -1,36 +0,0 @@ -# Hitachi H8 testcase 'daa' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -daa_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; daa Rd - daa r0l ; register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr8 5 r0l - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/das.s b/sim/testsuite/sim/h8300/das.s deleted file mode 100644 index 9317f19..0000000 --- a/sim/testsuite/sim/h8300/das.s +++ /dev/null @@ -1,36 +0,0 @@ -# Hitachi H8 testcase 'das' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -das_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; das Rd - das r0l ; register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/dec.s b/sim/testsuite/sim/h8300/dec.s deleted file mode 100644 index 122f311..0000000 --- a/sim/testsuite/sim/h8300/dec.s +++ /dev/null @@ -1,117 +0,0 @@ -# Hitachi H8 testcase 'dec.b, dec.w, dec.l' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -dec_b: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; dec.b Rd - dec.b r0h ; Decrement 8-bit reg by one - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa4a5 r0 ; dec result: a4|a5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a4a5 er0 ; dec result: a5|a5|a4|a5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -dec_w_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; dec.w #1, Rd - dec.w #1, r0 ; Decrement 16-bit reg by one - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a4 r0 ; dec result: a5|a4 - - test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -dec_w_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; dec.w #2, Rd - dec.w #2, r0 ; Decrement 16-bit reg by two - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a3 r0 ; dec result: a5|a3 - - test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -dec_l_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; dec.l #1, eRd - dec.l #1, er0 ; Decrement 32-bit reg by one - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -dec_l_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; dec.l #2, eRd - dec.l #2, er0 ; Decrement 32-bit reg by two - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/div.s b/sim/testsuite/sim/h8300/div.s deleted file mode 100644 index fd53baf..0000000 --- a/sim/testsuite/sim/h8300/div.s +++ /dev/null @@ -1,387 +0,0 @@ -# Hitachi H8 testcase 'divs', 'divu', 'divxs', 'divxu' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) -divs_w_reg_reg: - set_grs_a5a5 - - ;; divs.w rs, rd - mov.w #32, r1 - mov.w #-2, r2 - set_ccr_zero - divs.w r2, r1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr16 0xfff0 r1 - test_h_gr32 0xa5a5fffe er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -divs_w_imm4_reg: - set_grs_a5a5 - - ;; divs.w xx:4, rd - mov.w #-32, r1 - set_ccr_zero - divs.w #2:4, r1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr16 -16 r1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -divs_l_reg_reg: - set_grs_a5a5 - - ;; divs.l ers, erd - mov.l #320000, er1 - mov.l #-2, er2 - set_ccr_zero - divs.l er2, er1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr32 -160000 er1 - test_h_gr32 -2 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -divs_l_imm4_reg: - set_grs_a5a5 - - ;; divs.l xx:4, rd - mov.l #-320000, er1 - set_ccr_zero - divs.l #2:4, er1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr32 -160000 er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -divu_w_reg_reg: - set_grs_a5a5 - - ;; divu.w rs, rd - mov.w #32, r1 - mov.w #2, r2 - set_ccr_zero - divu.w r2, r1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr16 16 r1 - test_h_gr32 0xa5a50002 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -divu_w_imm4_reg: - set_grs_a5a5 - - ;; divu.w xx:4, rd - mov.w #32, r1 - set_ccr_zero - divu.w #2:4, r1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr16 16 r1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -divu_l_reg_reg: - set_grs_a5a5 - - ;; divu.l ers, erd - mov.l #320000, er1 - mov.l #2, er2 - set_ccr_zero - divu.l er2, er1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr32 160000 er1 - test_h_gr32 2 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -divu_l_imm4_reg: - set_grs_a5a5 - - ;; divu.l xx:4, rd - mov.l #320000, er1 - set_ccr_zero - divu.l #2:4, er1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr32 160000 er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - -.if (sim_cpu) ; not equal to zero ie. not h8 -divxs_b_reg_reg: - set_grs_a5a5 - - ;; divxs.b rs, rd - mov.w #32, r1 - mov.b #-2, r2l - set_ccr_zero - divxs.b r2l, r1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr16 0x00f0 r1 - test_h_gr32 0xa5a5a5fe er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -divxs_b_imm4_reg: - set_grs_a5a5 - - ;; divxs.b xx:4, rd - mov.w #-32, r1 - set_ccr_zero - divxs.b #2:4, r1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr16 0x00f0 r1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx - -divxs_w_reg_reg: - set_grs_a5a5 - - ;; divxs.w ers, erd - mov.l #0x1000, er1 - mov.w #-0x1000, r2 - set_ccr_zero - divxs.w r2, er1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr32 0x0000ffff er1 - test_h_gr32 0xa5a5f000 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -divxs_w_imm4_reg: - set_grs_a5a5 - - ;; divxs.w xx:4, rd - mov.l #-4, er1 - set_ccr_zero - divxs.w #2:4, er1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr32 0x0000fffe er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx -.endif ; not h8 - -divxu_b_reg_reg: - set_grs_a5a5 - - ;; divxu.b rs, rd - mov.w #32, r1 - mov.b #2, r2l - set_ccr_zero - divxu.b r2l, r1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr16 0x0010 r1 - test_h_gr16 0xa502 r2 -.if (sim_cpu) - test_h_gr32 0xa5a5a502 er2 -.endif - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; not h8 -.if (sim_cpu == h8sx) -divxu_b_imm4_reg: - set_grs_a5a5 - - ;; divxu.b xx:4, rd - mov.w #32, r1 - set_ccr_zero - divxu.b #2:4, r1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr16 0x0010 r1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx - -divxu_w_reg_reg: - set_grs_a5a5 - - ;; divxu.w ers, erd - mov.l #0x1000, er1 - mov.w #0x1000, r2 - set_ccr_zero - divxu.w r2, er1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr32 0x00000001 er1 - test_h_gr32 0xa5a51000 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -divxu_w_imm4_reg: - set_grs_a5a5 - - ;; divxu.w xx:4, rd - mov.l #0xffff, er1 - set_ccr_zero - divxu.w #2:4, er1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr32 0x00017fff er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx -.endif ; not h8 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/extl.s b/sim/testsuite/sim/h8300/extl.s deleted file mode 100644 index 001f6d3..0000000 --- a/sim/testsuite/sim/h8300/extl.s +++ /dev/null @@ -1,1146 +0,0 @@ -# Hitachi H8 testcase 'exts.l, extu.l' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data - .align 4 -pos: .long 0xffff0001 -neg: .long 0x00008000 - -pos2: .long 0xffffff01 -neg2: .long 0x00000080 - - .text - -exts_l_reg32_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l ern32 - mov.w #1, r0 - exts.l er0 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 0x00000001 er0 ; result of sign extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -exts_l_reg32_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l ern32 - mov.w #0xffff, r0 - exts.l er0 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xffffffff er0 ; result of sign extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -extu_l_reg32_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l ern32 - mov.w #0xffff, r0 - extu.l er0 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 0x0000ffff er0 ; result of zero extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -exts_l_ind_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @ern32 - mov.l #pos, er1 - exts.l @er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos - beq .Lslindp - fail -.Lslindp: - mov.l #0xffff0001, @pos ; Restore initial value - -exts_l_ind_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @ern32 - mov.l #neg, er1 - exts.l @er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffff8000, @neg - beq .Lslindn - fail -.Lslindn: -;;; Note: leave the value as 0xffff8000, so that extu has work to do. - -extu_l_ind_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @ern32 - mov.l #neg, er1 - extu.l @er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulindn - fail -.Lulindn: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -exts_l_postinc_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @ern32+ - mov.l #pos, er1 - exts.l @er1+ - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos+4 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos - beq .Lslpostincp - fail -.Lslpostincp: - mov.l #0xffff0001, @pos ; Restore initial value - -exts_l_postinc_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @ern32+ - mov.l #neg, er1 - exts.l @er1+ - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg+4 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffff8000, @neg - beq .Lslpostincn - fail -.Lslpostincn: -;;; Note: leave the value as 0xffff8000, so that extu has work to do. - -extu_l_postinc_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @ern32+ - mov.l #neg, er1 - extu.l @er1+ - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg+4 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulpostincn - fail -.Lulpostincn: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -exts_l_postdec_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @ern32- - mov.l #pos, er1 - exts.l @er1- - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos-4 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos - beq .Lslpostdecp - fail -.Lslpostdecp: - mov.l #0xffff0001, @pos ; Restore initial value - -exts_l_postdec_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @ern32- - mov.l #neg, er1 - exts.l @er1- - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg-4 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffff8000, @neg - beq .Lslpostdecn - fail -.Lslpostdecn: -;;; Note: leave the value as 0xffff8000, so that extu has work to do. - -extu_l_postdec_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @ern32- - mov.l #neg, er1 - extu.l @er1- - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg-4 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulpostdecn - fail -.Lulpostdecn: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -exts_l_preinc_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @+ern32 - mov.l #pos-4, er1 - exts.l @+er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos - beq .Lslpreincp - fail -.Lslpreincp: - mov.l #0xffff0001, @pos ; Restore initial value - -exts_l_preinc_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @+ern32 - mov.l #neg-4, er1 - exts.l @+er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffff8000, @neg - beq .Lslpreincn - fail -.Lslpreincn: -;;; Note: leave the value as 0xffff8000, so that extu has work to do. - -extu_l_preinc_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @+ern32 - mov.l #neg-4, er1 - extu.l @+er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulpreincn - fail -.Lulpreincn: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -exts_l_predec_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @-ern32 - mov.l #pos+4, er1 - exts.l @-er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos - beq .Lslpredecp - fail -.Lslpredecp: - mov.l #0xffff0001, @pos ; Restore initial value - -exts_l_predec_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l @-ern32 - mov.l #neg+4, er1 - exts.l @-er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffff8000, @neg - beq .Lslpredecn - fail -.Lslpredecn: -;;; Note: leave the value as 0xffff8000, so that extu has work to do. - -extu_l_predec_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @-ern32 - mov.l #neg+4, er1 - extu.l @-er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulpredecn - fail -.Lulpredecn: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -extu_l_disp2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @(dd:2, ern32) - mov.l #neg-8, er1 - extu.l @(8:2, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg-8 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Luldisp2n - fail -.Luldisp2n: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -extu_l_disp16_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @(dd:16, ern32) - mov.l #neg-44, er1 - extu.l @(44:16, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg-44 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Luldisp16n - fail -.Luldisp16n: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -extu_l_disp32_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @(dd:32, ern32) - mov.l #neg+444, er1 - extu.l @(-444:32, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg+444 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Luldisp32n - fail -.Luldisp32n: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -extu_l_abs16_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @aa:16 - extu.l @neg:16 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulabs16n - fail -.Lulabs16n: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - -extu_l_abs32_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l @aa:32 - extu.l @neg:32 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00008000, @neg - beq .Lulabs32n - fail -.Lulabs32n: -;;; Note: leave the value as 0x00008000, so that extu has work to do. - - - - # - # exts #2, nn - # - -exts_l_reg32_2_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, ern32 - mov.b #1, r0l - exts.l #2, er0 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 0x00000001 er0 ; result of sign extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -exts_l_reg32_2_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, ern32 - mov.b #0xff, r0l - exts.l #2, er0 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_ovf_clear - test_zero_clear - test_carry_clear - - test_h_gr32 0xffffffff er0 ; result of sign extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -extu_l_reg32_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, ern32 - mov.b #0xff, r0l - extu.l #2, er0 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 0x000000ff er0 ; result of zero extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -exts_l_ind_2_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @ern32 - mov.l #pos2, er1 - exts.l #2, @er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos2 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos2 - beq .Lslindp2 - fail -.Lslindp2: - mov.l #0xffffff01, @pos2 ; Restore initial value - -exts_l_ind_2_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @ern32 - mov.l #neg2, er1 - exts.l #2, @er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_ovf_clear - test_zero_clear - test_carry_clear - - test_h_gr32 neg2 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffffff80, @neg2 - beq .Lslindn2 - fail -.Lslindn2: -;;; Note: leave the value as 0xffffff80, so that extu has work to do. - -extu_l_ind_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @ern32 - mov.l #neg2, er1 - extu.l #2, @er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulindn2 - fail -.Lulindn2: -;;; Note: leave the value as 0x00000080, like it started out. - -exts_l_postinc_2_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @ern32+ - mov.l #pos2, er1 - exts.l #2, @er1+ - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos2+4 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos2 - beq .Lslpostincp2 - fail -.Lslpostincp2: - mov.l #0xffffff01, @pos2 ; Restore initial value - -exts_l_postinc_2_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @ern32+ - mov.l #neg2, er1 - exts.l #2, @er1+ - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_ovf_clear - test_zero_clear - test_carry_clear - - test_h_gr32 neg2+4 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffffff80, @neg2 - beq .Lslpostincn2 - fail -.Lslpostincn2: -;;; Note: leave the value as 0xffffff80, so that extu has work to do. - -extu_l_postinc_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @ern32+ - mov.l #neg2, er1 - extu.l #2, @er1+ - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2+4 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulpostincn2 - fail -.Lulpostincn2: -;;; Note: leave the value as 0x00000080, like it started out. - -exts_l_postdec_2_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @ern32- - mov.l #pos2, er1 - exts.l #2, @er1- - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos2-4 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos2 - beq .Lslpostdecp2 - fail -.Lslpostdecp2: - mov.l #0xffffff01, @pos2 ; Restore initial value - -exts_l_postdec_2_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @ern32- - mov.l #neg2, er1 - exts.l #2, @er1- - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_ovf_clear - test_zero_clear - test_carry_clear - - test_h_gr32 neg2-4 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffffff80, @neg2 - beq .Lslpostdecn2 - fail -.Lslpostdecn2: -;;; Note: leave the value as 0xffffff80, so that extu has work to do. - -extu_l_postdec_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @ern32- - mov.l #neg2, er1 - extu.l #2, @er1- - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2-4 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulpostdecn2 - fail -.Lulpostdecn2: -;;; Note: leave the value as 0x00000080, like it started out. - -exts_l_preinc_2_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @+ern32 - mov.l #pos2-4, er1 - exts.l #2, @+er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos2 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos2 - beq .Lslpreincp2 - fail -.Lslpreincp2: - mov.l #0xffffff01, @pos2 ; Restore initial value - -exts_l_preinc_2_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @+ern32 - mov.l #neg2-4, er1 - exts.l #2, @+er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_ovf_clear - test_zero_clear - test_carry_clear - - test_h_gr32 neg2 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffffff80, @neg2 - beq .Lslpreincn2 - fail -.Lslpreincn2: -;;; Note: leave the value as 0xffffff80, so that extu has work to do. - -extu_l_preinc_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @+ern32 - mov.l #neg2-4, er1 - extu.l #2, @+er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulpreincn2 - fail -.Lulpreincn2: -;;; Note: leave the value as 0x00000080, like it started out. - -exts_l_predec_2_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @-ern32 - mov.l #pos2+4, er1 - exts.l #2, @-er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos2 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000001, @pos2 - beq .Lslpredecp2 - fail -.Lslpredecp2: - mov.l #0xffffff01, @pos2 ; Restore initial value - -exts_l_predec_2_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.l #2, @-ern32 - mov.l #neg2+4, er1 - exts.l #2, @-er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_ovf_clear - test_zero_clear - test_carry_clear - - test_h_gr32 neg2 er1 ; result of sign extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0xffffff80, @neg2 - beq .Lslpredecn2 - fail -.Lslpredecn2: -;;; Note: leave the value as 0xffffff80, so that extu has work to do. - -extu_l_predec_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @-ern32 - mov.l #neg2+4, er1 - extu.l #2, @-er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulpredecn2 - fail -.Lulpredecn2: -;;; Note: leave the value as 0x00000080, like it started out. - -extu_l_disp2_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @(dd:2, ern32) - mov.l #neg2-8, er1 - extu.l #2, @(8:2, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2-8 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Luldisp2n2 - fail -.Luldisp2n2: -;;; Note: leave the value as 0x00000080, like it started out. - -extu_l_disp16_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @(dd:16, ern32) - mov.l #neg2-44, er1 - extu.l #2, @(44:16, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2-44 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Luldisp16n2 - fail -.Luldisp16n2: -;;; Note: leave the value as 0x00000080, like it started out. - -extu_l_disp32_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @(dd:32, ern32) - mov.l #neg2+444, er1 - extu.l #2, @(-444:32, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg2+444 er1 ; result of zero extend - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Luldisp32n2 - fail -.Luldisp32n2: -;;; Note: leave the value as 0x00000080, like it started out. - -extu_l_abs16_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @aa:16 - extu.l #2, @neg2:16 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulabs16n2 - fail -.Lulabs16n2: -;;; Note: leave the value as 0x00000080, like it started out. - -extu_l_abs32_2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.l #2, @aa:32 - extu.l #2, @neg2:32 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.l #0x00000080, @neg2 - beq .Lulabs32n2 - fail -.Lulabs32n2: -;;; Note: leave the value as 0x00000080, like it started out. - -.endif - - pass - - exit 0 - - - - diff --git a/sim/testsuite/sim/h8300/extw.s b/sim/testsuite/sim/h8300/extw.s deleted file mode 100644 index b1eb491..0000000 --- a/sim/testsuite/sim/h8300/extw.s +++ /dev/null @@ -1,580 +0,0 @@ -# Hitachi H8 testcase 'exts.w, extu.w' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data - .align 2 -pos: .word 0xff01 -neg: .word 0x0080 - - .text - -exts_w_reg16_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.w rn16 - mov.b #1, r0l - exts.w r0 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 0xa5a50001 er0 ; result of sign extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -exts_w_reg16_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.w rn16 - mov.b #0xff, r0l - exts.w r0 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5ffff er0 ; result of sign extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -extu_w_reg16_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w rn16 - mov.b #0xff, r0l - extu.w r0 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 0xa5a500ff er0 ; result of zero extend - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -exts_w_ind_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @ern - mov.l #pos, er1 - exts.w @er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0001, @pos - beq .Lswindp - fail -.Lswindp: - mov.w #0xff01, @pos ; Restore initial value - -exts_w_ind_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @ern - mov.l #neg, er1 - exts.w @er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0xff80, @neg - beq .Lswindn - fail -.Lswindn: - ;; Note: leave the value as 0xff80, so that extu has work to do. - -extu_w_ind_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @ern - mov.l #neg, er1 - extu.w @er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwindn - fail -.Luwindn: - ;; Note: leave the value as 0x0080, like it started out. - -exts_w_postinc_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @ern+ - mov.l #pos, er1 - exts.w @er1+ - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos+2 er1 ; er1 still contains target address plus 2 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0001, @pos - beq .Lswpostincp - fail -.Lswpostincp: - mov.w #0xff01, @pos ; Restore initial value - -exts_w_postinc_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @ern+ - mov.l #neg, er1 - exts.w @er1+ - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg+2 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0xff80, @neg - beq .Lswpostincn - fail -.Lswpostincn: - ;; Note: leave the value as 0xff80, so that extu has work to do. - -extu_w_postinc_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @ern+ - mov.l #neg, er1 - extu.w @er1+ - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg+2 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwpostincn - fail -.Luwpostincn: - ;; Note: leave the value as 0x0080, like it started out. - -exts_w_postdec_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @ern- - mov.l #pos, er1 - exts.w @er1- - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos-2 er1 ; er1 still contains target address plus 2 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0001, @pos - beq .Lswpostdecp - fail -.Lswpostdecp: - mov.w #0xff01, @pos ; Restore initial value - -exts_w_postdec_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @ern- - mov.l #neg, er1 - exts.w @er1- - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg-2 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0xff80, @neg - beq .Lswpostdecn - fail -.Lswpostdecn: - ;; Note: leave the value as 0xff80, so that extu has work to do. - -extu_w_postdec_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @ern- - mov.l #neg, er1 - extu.w @er1- - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg-2 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwpostdecn - fail -.Luwpostdecn: - ;; Note: leave the value as 0x0080, like it started out. - -exts_w_preinc_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @+ern - mov.l #pos-2, er1 - exts.w @+er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos er1 ; er1 still contains target address plus 2 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0001, @pos - beq .Lswpreincp - fail -.Lswpreincp: - mov.w #0xff01, @pos ; Restore initial value - -exts_w_preinc_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @+ern - mov.l #neg-2, er1 - exts.w @+er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0xff80, @neg - beq .Lswpreincn - fail -.Lswpreincn: - ;; Note: leave the value as 0xff80, so that extu has work to do. - -extu_w_preinc_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @+ern - mov.l #neg-2, er1 - extu.w @+er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwpreincn - fail -.Luwpreincn: - ;; Note: leave the value as 0x0080, like it started out. - -exts_w_predec_p: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @-ern - mov.l #pos+2, er1 - exts.w @-er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 pos er1 ; er1 still contains target address plus 2 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0001, @pos - beq .Lswpredecp - fail -.Lswpredecp: - mov.w #0xff01, @pos ; Restore initial value - -exts_w_predec_n: - set_grs_a5a5 - set_ccr_zero - ;; exts.w @-ern - mov.l #neg+2, er1 - exts.w @-er1 - - ;; Test ccr H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0xff80, @neg - beq .Lswpredecn - fail -.Lswpredecn: - ;; Note: leave the value as 0xff80, so that extu has work to do. - -extu_w_predec_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @-ern - mov.l #neg+2, er1 - extu.w @-er1 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwpredecn - fail -.Luwpredecn: - ;; Note: leave the value as 0x0080, like it started out. - -extu_w_disp2_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @(dd:2, ern) - mov.l #neg-2, er1 - extu.w @(2:2, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg-2 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwdisp2n - fail -.Luwdisp2n: - ;; Note: leave the value as 0x0080, like it started out. - -extu_w_disp16_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @(dd:16, ern) - mov.l #neg-44, er1 - extu.w @(44:16, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg-44 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwdisp16n - fail -.Luwdisp16n: - ;; Note: leave the value as 0x0080, like it started out. - -extu_w_disp32_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @(dd:32, ern) - mov.l #neg+444, er1 - extu.w @(-444:32, er1) - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_h_gr32 neg+444 er1 ; er1 still contains target address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwdisp32n - fail -.Luwdisp32n: - ;; Note: leave the value as 0x0080, like it started out. - -extu_w_abs16_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @aa:16 - extu.w @neg:16 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwabs16n - fail -.Luwabs16n: - ;; Note: leave the value as 0x0080, like it started out. - -extu_w_abs32_n: - set_grs_a5a5 - set_ccr_zero - ;; extu.w @aa:32 - extu.w @neg:32 - - ;; Test ccr H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - cmp.w #0x0080, @neg - beq .Luwabs32n - fail -.Luwabs32n: - ;; Note: leave the value as 0x0080, like it started out. - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/inc.s b/sim/testsuite/sim/h8300/inc.s deleted file mode 100644 index 69d2c3b..0000000 --- a/sim/testsuite/sim/h8300/inc.s +++ /dev/null @@ -1,117 +0,0 @@ -# Hitachi H8 testcase 'inc, inc.w, inc.l' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -inc_b: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; inc.b Rd - inc.b r0h ; Increment 8-bit reg by one - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa6a5 r0 ; inc result: a6|a5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a6a5 er0 ; inc result: a5|a5|a6|a5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -inc_w_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; inc.w #1, Rd - inc.w #1, r0 ; Increment 16-bit reg by one - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a6 r0 ; inc result: a5|a6 - - test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -inc_w_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; inc.w #2, Rd - inc.w #2, r0 ; Increment 16-bit reg by two - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a7 r0 ; inc result: a5|a7 - - test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -inc_l_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; inc.l #1, eRd - inc.l #1, er0 ; Increment 32-bit reg by one - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -inc_l_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; inc.l #2, eRd - inc.l #2, er0 ; Increment 32-bit reg by two - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/jmp.s b/sim/testsuite/sim/h8300/jmp.s deleted file mode 100644 index 30a4b28..0000000 --- a/sim/testsuite/sim/h8300/jmp.s +++ /dev/null @@ -1,123 +0,0 @@ -# Hitachi H8 testcase 'jmp' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -vector_area: - .fill 0x400, 1, 0 - - start - -.if (sim_cpu == h8sx) -jmp_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #.Ltgt_8:32, @0x20 - set_ccr_zero - ;; jmp @@aa:8 ; 8-bit displacement - jmp @@0x20 - fail - -.Ltgt_8: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -jmp_7: ; vector jump - mov.l #vector_area, er0 - ldc.l er0, vbr - set_grs_a5a5 - mov.l #.Ltgt_7:32, @vector_area+0x300 - set_ccr_zero - - jmp @@0x300 - fail -.Ltgt_7: - test_cc_clear - test_grs_a5a5 - stc.l vbr, er0 - test_h_gr32 vector_area, er0 - -.endif ; h8sx - -jmp_24: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; jmp @aa:24 ; 24-bit address - jmp @.Ltgt_24:24 - fail - -.Ltgt_24: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; Non-zero means h8300h, h8300s, or h8sx -jmp_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; jmp @ern ; register indirect - mov.l #.Ltgt_reg, er5 - jmp @er5 - fail - -.Ltgt_reg: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_h_gr32 .Ltgt_reg er5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; not h8300 - -.if (sim_cpu == h8sx) -jmp_32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; jmp @aa:32 ; 32-bit address -; jmp @.Ltgt_32:32 ; NOTE: hard-coded to avoid relaxing - .word 0x5908 - .long .Ltgt_32 - fail - -.Ltgt_32: - test_cc_clear - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx - - pass - exit 0 - - \ No newline at end of file diff --git a/sim/testsuite/sim/h8300/ldc.s b/sim/testsuite/sim/h8300/ldc.s deleted file mode 100644 index 3712a6c..0000000 --- a/sim/testsuite/sim/h8300/ldc.s +++ /dev/null @@ -1,375 +0,0 @@ -# Hitachi H8 testcase 'ldc' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - .data -byte_pre: - .byte 0 -byte_src: - .byte 0xff -byte_post: - .byte 0 - - start - -ldc_imm8_ccr: - set_grs_a5a5 - set_ccr_zero - - ldc #0xff, ccr ; set all ccr flags high, immediate operand - bcs .L1 ; carry flag set? - fail -.L1: bvs .L2 ; overflow flag set? - fail -.L2: beq .L3 ; zero flag set? - fail -.L3: bmi .L4 ; neg flag set? - fail -.L4: - ldc #0, ccr ; set all ccr flags low, immediate operand - bcc .L5 ; carry flag clear? - fail -.L5: bvc .L6 ; overflow flag clear? - fail -.L6: bne .L7 ; zero flag clear? - fail -.L7: bpl .L8 ; neg flag clear? - fail -.L8: - test_cc_clear - test_grs_a5a5 - -ldc_reg8_ccr: - set_grs_a5a5 - set_ccr_zero - - mov #0xff, r0h - ldc r0h, ccr ; set all ccr flags high, reg operand - bcs .L11 ; carry flag set? - fail -.L11: bvs .L12 ; overflow flag set? - fail -.L12: beq .L13 ; zero flag set? - fail -.L13: bmi .L14 ; neg flag set? - fail -.L14: - mov #0, r0h - ldc r0h, ccr ; set all ccr flags low, reg operand - bcc .L15 ; carry flag clear? - fail -.L15: bvc .L16 ; overflow flag clear? - fail -.L16: bne .L17 ; zero flag clear? - fail -.L17: bpl .L18 ; neg flag clear? - fail -.L18: - test_cc_clear - test_h_gr16 0x00a5 r0 ; Register 0 modified by test procedure. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr -ldc_imm8_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - ldc #0x87, exr ; set exr to 0x87 - - stc exr, r0l ; retrieve and check exr value - cmp.b #0x87, r0l - beq .L19 - fail -.L19: - test_h_gr16 0xa587 r0 ; Register 0 modified by test procedure. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_reg8_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - mov #0x87, r0h - ldc r0h, exr ; set exr to 0x87 - - stc exr, r0l ; retrieve and check exr value - cmp.b #0x87, r0l - beq .L21 - fail -.L21: - test_h_gr16 0x8787 r0 ; Register 0 modified by test procedure. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_abs16_ccr: - set_grs_a5a5 - set_ccr_zero - - ldc @byte_src:16, ccr ; abs16 src - stc ccr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_abs16_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - ldc @byte_src:16, exr ; abs16 src - stc exr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_abs32_ccr: - set_grs_a5a5 - set_ccr_zero - - ldc @byte_src:32, ccr ; abs32 src - stc ccr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_abs32_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - ldc @byte_src:32, exr ; abs32 src - stc exr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_disp16_ccr: - set_grs_a5a5 - set_ccr_zero - - mov #byte_pre, er1 - ldc @(1:16, er1), ccr ; disp16 src - stc ccr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_h_gr32 byte_pre, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_disp16_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - mov #byte_post, er1 - ldc @(-1:16, er1), exr ; disp16 src - stc exr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_h_gr32 byte_post, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_disp32_ccr: - set_grs_a5a5 - set_ccr_zero - - mov #byte_pre, er1 - ldc @(1:32, er1), ccr ; disp32 src - stc ccr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_h_gr32 byte_pre, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_disp32_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - mov #byte_post, er1 - ldc @(-1:32, er1), exr ; disp16 src - stc exr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_h_gr32 byte_post, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_postinc_ccr: - set_grs_a5a5 - set_ccr_zero - - mov #byte_src, er1 - ldc @er1+, ccr ; postinc src - stc ccr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_h_gr32 byte_src+2, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_postinc_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - mov #byte_src, er1 - ldc @er1+, exr ; postinc src - stc exr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_h_gr32 byte_src+2, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_ind_ccr: - set_grs_a5a5 - set_ccr_zero - - mov #byte_src, er1 - ldc @er1, ccr ; postinc src - stc ccr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_h_gr32 byte_src, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_ind_exr: - set_grs_a5a5 - set_ccr_zero - - ldc #0, exr - mov #byte_src, er1 - ldc @er1, exr ; postinc src - stc exr, r0l ; copy into general reg - - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_h_gr32 byte_src, er1 ; er1 still contains address - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - -.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx -ldc_reg_sbr: - set_grs_a5a5 - set_ccr_zero - - mov #0xaaaaaaaa, er0 - ldc er0, sbr ; set sbr to 0xaaaaaaaa - stc sbr, er1 ; retreive and check sbr value - - test_h_gr32 0xaaaaaaaa er1 - test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -ldc_reg_vbr: - set_grs_a5a5 - set_ccr_zero - - mov #0xaaaaaaaa, er0 - ldc er0, vbr ; set sbr to 0xaaaaaaaa - stc vbr, er1 ; retreive and check sbr value - - test_h_gr32 0xaaaaaaaa er1 - test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/ldm.s b/sim/testsuite/sim/h8300/ldm.s deleted file mode 100644 index c816221..0000000 --- a/sim/testsuite/sim/h8300/ldm.s +++ /dev/null @@ -1,233 +0,0 @@ -# Hitachi H8 testcase 'ldm', 'stm' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - .data - .align 4 -_stack: .long 0,1,2,3,4,5,6,7,8,9,0,0,0,0,0,0 - .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -_stack_top: - - start - -.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr -stm_2reg: - set_grs_a5a5 - mov #_stack_top, er7 - mov #2, er2 - mov #3, er3 - - set_ccr_zero - stm er2-er3, @-sp - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_h_gr32 2 er2 - test_h_gr32 3 er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_h_gr32 _stack_top-8, er7 - - mov @_stack_top-4, er0 - cmp #2, er0 - bne fail1 - - mov @_stack_top-8, er0 - cmp #3, er0 - bne fail1 - - mov @_stack_top-12, er0 - cmp #0, er0 - bne fail1 - -stm_3reg: - set_grs_a5a5 - mov #_stack_top, er7 - mov #4, er4 - mov #5, er5 - mov #6, er6 - - set_ccr_zero - stm er4-er6, @-sp - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 4 er4 - test_h_gr32 5 er5 - test_h_gr32 6 er6 - test_h_gr32 _stack_top-12, er7 - - mov @_stack_top-4, er0 - cmp #4, er0 - bne fail1 - - mov @_stack_top-8, er0 - cmp #5, er0 - bne fail1 - - mov @_stack_top-12, er0 - cmp #6, er0 - bne fail1 - - mov @_stack_top-16, er0 - cmp #0, er0 - bne fail1 - -stm_4reg: - set_grs_a5a5 - mov #_stack_top, er7 - mov #1, er0 - mov #2, er1 - mov #3, er2 - mov #4, er3 - - set_ccr_zero - stm er0-er3, @-sp - test_cc_clear - - test_h_gr32 1 er0 - test_h_gr32 2 er1 - test_h_gr32 3 er2 - test_h_gr32 4 er3 - test_gr_a5a5 4 ; Make sure other general regs not disturbed - test_gr_a5a5 5 - test_gr_a5a5 6 - test_h_gr32 _stack_top-16, er7 - - mov @_stack_top-4, er0 - cmp #1, er0 - bne fail1 - - mov @_stack_top-8, er0 - cmp #2, er0 - bne fail1 - - mov @_stack_top-12, er0 - cmp #3, er0 - bne fail1 - - mov @_stack_top-16, er0 - cmp #4, er0 - bne fail1 - - mov @_stack_top-20, er0 - cmp #0, er0 - bne fail1 - -ldm_2reg: - set_grs_a5a5 - mov #_stack, er7 - - set_ccr_zero - ldm @sp+, er2-er3 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_h_gr32 1 er2 - test_h_gr32 0 er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_h_gr32 _stack+8, er7 - -ldm_3reg: - set_grs_a5a5 - mov #_stack+4, er7 - - set_ccr_zero - ldm @sp+, er4-er6 - test_cc_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 3 er4 - test_h_gr32 2 er5 - test_h_gr32 1 er6 - test_h_gr32 _stack+16, er7 - -ldm_4reg: - set_grs_a5a5 - mov #_stack+4, er7 - - set_ccr_zero - ldm @sp+, er0-er3 - test_cc_clear - - test_h_gr32 4 er0 - test_h_gr32 3 er1 - test_h_gr32 2 er2 - test_h_gr32 1 er3 - test_gr_a5a5 4 ; Make sure other general regs not disturbed - test_gr_a5a5 5 - test_gr_a5a5 6 - test_h_gr32 _stack+20, er7 -.endif - -pushpop: - set_grs_a5a5 -.if (sim_cpu == h8300) - mov #_stack_top, r7 - mov #12, r1 - mov #34, r2 - mov #56, r3 - push r1 - push r2 - push r3 - pop r4 - pop r5 - pop r6 - - test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed - test_h_gr16 12 r1 - test_h_gr16 34 r2 - test_h_gr16 56 r3 - test_h_gr16 56 r4 - test_h_gr16 34 r5 - test_h_gr16 12 r6 - mov #_stack_top, r0 - cmp.w r0, r7 - bne fail1 -.else - mov #_stack_top, er7 - mov #12, er1 - mov #34, er2 - mov #56, er3 - push er1 - push er2 - push er3 - pop er4 - pop er5 - pop er6 - - test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed - test_h_gr32 12 er1 - test_h_gr32 34 er2 - test_h_gr32 56 er3 - test_h_gr32 56 er4 - test_h_gr32 34 er5 - test_h_gr32 12 er6 - test_h_gr32 _stack_top, er7 -.endif - - pass - - exit 0 - -fail1: fail diff --git a/sim/testsuite/sim/h8300/mac.s b/sim/testsuite/sim/h8300/mac.s deleted file mode 100644 index d60fe30..0000000 --- a/sim/testsuite/sim/h8300/mac.s +++ /dev/null @@ -1,263 +0,0 @@ -# Hitachi H8 testcase 'mac' -# mach(): h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -src1: .word 0 -src2: .word 0 - -array: .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - .word 0x7fff - - start - -.if (sim_cpu) -_clrmac: - set_grs_a5a5 - set_ccr_zero - clrmac - test_cc_clear - test_grs_a5a5 - ;; Now see if the mac is actually clear... - stmac mach, er0 - test_zero_set - test_neg_clear - test_ovf_clear - test_h_gr32 0 er0 - stmac macl, er1 - test_zero_set - test_neg_clear - test_ovf_clear - test_h_gr32 0 er1 - -ld_stmac: - set_grs_a5a5 - sub.l er2, er2 - set_ccr_zero - ldmac er1, macl - stmac macl, er2 - test_ovf_clear - test_carry_clear - ;; neg and zero are undefined - test_h_gr32 0xa5a5a5a5 er2 - - sub.l er2, er2 - set_ccr_zero - ldmac er1, mach - stmac mach, er2 - test_ovf_clear - test_carry_clear - ;; neg and zero are undefined - test_h_gr32 0x0001a5 er2 - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mac_2x2: - set_grs_a5a5 - mov.w #2, r1 - mov.w r1, @src1 - mov.w #2, r2 - mov.w r2, @src2 - mov #src1, er1 - mov #src2, er2 - set_ccr_zero - clrmac - mac @er1+, @er2+ - test_cc_clear - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 src1+2 er1 - test_h_gr32 src2+2 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - - stmac macl, er0 - test_zero_clear - test_neg_clear - test_ovf_clear - test_h_gr32 4 er0 - - stmac mach, er0 - test_zero_clear - test_neg_clear - test_ovf_clear - test_h_gr32 0 er0 - -mac_same_reg_2x4: - ;; Use same reg for src and dst. Should be incremented twice, - ;; and fetch values from consecutive locations. - set_grs_a5a5 - mov.w #2, r1 - mov.w r1, @src1 - mov.w #4, r2 - mov.w r2, @src2 - mov #src1, er1 - - set_ccr_zero - clrmac - mac @er1+, @er1+ ; same register for src and dst - test_cc_clear - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 src1+4 er1 - test_h_gr32 0xa5a50004 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - - stmac macl, er0 - test_zero_clear - test_neg_clear - test_ovf_clear - test_h_gr32 8 er0 - - stmac mach, er0 - test_zero_clear - test_neg_clear - test_ovf_clear - test_h_gr32 0 er0 - -mac_0x0: - set_grs_a5a5 - mov.w #0, r1 - mov.w r1, @src1 - mov.w #0, r2 - mov.w r2, @src2 - mov #src1, er1 - mov #src2, er2 - set_ccr_zero - clrmac - mac @er1+, @er2+ - test_cc_clear - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 src1+2 er1 - test_h_gr32 src2+2 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - - stmac macl, er0 - test_zero_set ; zero flag is set - test_neg_clear - test_ovf_clear - test_h_gr32 0 er0 ; result is zero - - stmac mach, er0 - test_zero_set - test_neg_clear - test_ovf_clear - test_h_gr32 0 er0 - -mac_neg2x2: - set_grs_a5a5 - mov.w #-2, r1 - mov.w r1, @src1 - mov.w #2, r2 - mov.w r2, @src2 - mov #src1, er1 - mov #src2, er2 - set_ccr_zero - clrmac - mac @er1+, @er2+ - test_cc_clear - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 src1+2 er1 - test_h_gr32 src2+2 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - - stmac macl, er0 - test_zero_clear - test_neg_set ; neg flag is set - test_ovf_clear - test_h_gr32 -4 er0 ; result is negative - - stmac mach, er0 - test_zero_clear - test_neg_set - test_ovf_clear - test_h_gr32 -1 er0 ; negative sign extend - -mac_array: - ;; Use same reg for src and dst, pointing to an array of shorts - set_grs_a5a5 - mov #array, er1 - - set_ccr_zero - clrmac - mac @er1+, @er1+ ; same register for src and dst - mac @er1+, @er1+ ; repeat 8 times - mac @er1+, @er1+ - mac @er1+, @er1+ - mac @er1+, @er1+ - mac @er1+, @er1+ - mac @er1+, @er1+ - mac @er1+, @er1+ - test_cc_clear - - test_h_gr32 0xa5a5a5a5 er0 - test_h_gr32 array+32 er1 - test_h_gr32 0xa5a5a5a5 er2 - test_h_gr32 0xa5a5a5a5 er3 - test_h_gr32 0xa5a5a5a5 er4 - test_h_gr32 0xa5a5a5a5 er5 - test_h_gr32 0xa5a5a5a5 er6 - test_h_gr32 0xa5a5a5a5 er7 - - stmac macl, er0 - test_zero_clear - test_neg_clear - test_ovf_clear - test_h_gr32 0xfff80008 er0 - - stmac mach, er0 - test_zero_clear - test_neg_clear - test_ovf_clear - test_h_gr32 1 er0 ; result is greater than 32 bits - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/mova.s b/sim/testsuite/sim/h8300/mova.s deleted file mode 100644 index a4bcfd6..0000000 --- a/sim/testsuite/sim/h8300/mova.s +++ /dev/null @@ -1,838 +0,0 @@ -# Hitachi H8 testcase 'mova' -# mach(): h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -foo: .long 0x01010101 - .long 0x10101010 - .long 0x11111111 - - start - -movabl16_reg8: - set_grs_a5a5 - set_ccr_zero - - mova/b.l @(1:16, r2l.b), er3 - - test_cc_clear - test_gr_a5a5 0 ; Make sure other regs not affected - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 0xa6 er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -movabl16_reg16: - set_grs_a5a5 - set_ccr_zero - - mova/b.l @(1:16, r2.w), er3 - - test_cc_clear - test_gr_a5a5 0 ; Make sure other regs not affected - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 0xa5a6 er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -movabl32_reg8: - set_grs_a5a5 - set_ccr_zero - - mova/b.l @(1:32, r2l.b), er3 - - test_cc_clear - test_gr_a5a5 0 ; Make sure other regs not affected - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 0xa6 er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -movabl32_reg16: - set_grs_a5a5 - set_ccr_zero - - mova/b.l @(1:32, r2.w), er3 - - test_cc_clear - test_gr_a5a5 0 ; Make sure other regs not affected - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 0xa5a6 er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -movawl16_reg8: - set_grs_a5a5 - set_ccr_zero - - mova/w.l @(1:16, r2l.b), er3 - - test_cc_clear - test_gr_a5a5 0 ; Make sure other regs not affected - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 0x14b er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -movawl16_reg16: - set_grs_a5a5 - set_ccr_zero - - mova/w.l @(1:16, r2.w), er3 - - test_cc_clear - test_gr_a5a5 0 ; Make sure other regs not affected - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 0x14b4b er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -movawl32_reg8: - set_grs_a5a5 - set_ccr_zero - - mova/w.l @(1:32, r2l.b), er3 - - test_cc_clear - test_gr_a5a5 0 ; Make sure other regs not affected - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 0x14b er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -movawl32_reg16: - set_grs_a5a5 - set_ccr_zero - - mova/w.l @(1:32, r2.w), er3 - - test_cc_clear - test_gr_a5a5 0 ; Make sure other regs not affected - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 0x14b4b er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -movall16_reg8: - set_grs_a5a5 - set_ccr_zero - - mova/l.l @(1:16, r2l.b), er3 - - test_cc_clear - test_gr_a5a5 0 ; Make sure other regs not affected - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 0x295 er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -movall16_reg16: - set_grs_a5a5 - set_ccr_zero - - mova/l.l @(1:16, r2.w), er3 - - test_cc_clear - test_gr_a5a5 0 ; Make sure other regs not affected - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 0x29695 er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -movall32_reg8: - set_grs_a5a5 - set_ccr_zero - - mova/l.l @(1:32, r2l.b), er3 - - test_cc_clear - test_gr_a5a5 0 ; Make sure other regs not affected - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 0x295 er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -movall32_reg16: - set_grs_a5a5 - set_ccr_zero - - mova/l.l @(1:32, r2.w), er3 - - test_cc_clear - test_gr_a5a5 0 ; Make sure other regs not affected - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 0x29695 er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -t02_mova: - set_grs_a5a5 - set_ccr_zero - - mov.l #0x01010101, er1 - mova/b.c @(0x1234:16,r1l.b),er1 ; 7A891234 - test_h_gr32 0x1235, er1 ; 1s - mov.l #0x01010101, er1 - mova/b.c @(0x1234:16,r1.w),er1 ; 7A991234 - test_h_gr32 0x1335, er1 ; 2s - mov.l #0x01010101, er1 - mova/w.c @(0x1234:16,r1l.b),er1 ; 7AA91234 - test_h_gr32 0x1236, er1 ; 3s - mov.l #0x01010101, er1 - mova/w.c @(0x1234:16,r1.w),er1 ; 7AB91234 - test_h_gr32 0x1436, er1 ; 4s - mov.l #0x01010101, er1 - mova/l.c @(0x1234:16,r1l.b),er1 ; 7AC91234 - test_h_gr32 0x1238, er1 ; 5s - mov.l #0x01010101, er1 - mova/l.c @(0x1234:16,r1.w),er1 ; 7AD91234 - test_h_gr32 0x1638, er1 ; 6s - mov.l #0x01010101, er1 - mova/b.c @(0x12345678:32,r1l.b),er1 ; 7A8112345678 - test_h_gr32 0x12345679, er1 ; 7s - mov.l #0x01010101, er1 - mova/b.c @(0x12345678:32,r1.w),er1 ; 7A9112345678 - test_h_gr32 0x12345779, er1 ; 8s - mov.l #0x01010101, er1 - mova/w.c @(0x12345678:32,r1l.b),er1 ; 7AA112345678 - test_h_gr32 0x1234567a, er1 ; 9s - mov.l #0x01010101, er1 - mova/w.c @(0x12345678:32,r1.w),er1 ; 7AB112345678 - test_h_gr32 0x1234587a, er1 ; 10s - mov.l #0x01010101, er1 - mova/l.c @(0x12345678:32,r1l.b),er1 ; 7AC112345678 - test_h_gr32 0x1234567c, er1 ; 11s - mov.l #0x01010101, er1 - mova/l.c @(0x12345678:32,r1.w),er1 ; 7AD112345678 - test_h_gr32 0x12345a7c, er1 ; 12s - -t02b: - mov.l #0x01010101, er3 - mova/b.l @(0x1234:16,r3l.b),er1 ; 78B87A891234 - test_h_gr32 0x1235, er1 ; 1 - mova/b.l @(0x1234:16,r3.w),er1 ; 78397A991234 - test_h_gr32 0x1335, er1 ; 2 - mova/w.l @(0x1234:16,r3l.b),er1 ; 78B87AA91234 - test_h_gr32 0x1236, er1 ; 3 - mova/w.l @(0x1234:16,r3.w),er1 ; 78397AB91234 - test_h_gr32 0x1436, er1 ; 4 - mova/l.l @(0x1234:16,r3l.b),er1 ; 78B87AC91234 - test_h_gr32 0x1238, er1 ; 5 - mova/l.l @(0x1234:16,r3.w),er1 ; 78397AD91234 - test_h_gr32 0x1638, er1 ; 6 - mova/b.l @(0x12345678:32,r3l.b),er1 ; 78B87A8112345678 - test_h_gr32 0x12345679, er1 ; 7 - mova/b.l @(0x12345678:32,r3.w),er1 ; 78397A9112345678 - test_h_gr32 0x12345779, er1 ; 8 - mova/w.l @(0x12345678:32,r3l.b),er1 ; 78B87AA112345678 - test_h_gr32 0x1234567a, er1 ; 9 - mova/w.l @(0x12345678:32,r3.w),er1 ; 78397AB112345678 - test_h_gr32 0x1234587a, er1 ; 10 - mova/l.l @(0x12345678:32,r3l.b),er1 ; 78B87AC112345678 - test_h_gr32 0x1234567c, er1 ; 11 - mova/l.l @(0x12345678:32,r3.w),er1 ; 78397AD112345678 - test_h_gr32 0x12345a7c, er1 ; 12 - test_h_gr32 0x01010101, er3 -t02c: - mov.l #foo, er2 - mova/b.l @(0x1234:16,@er2.b),er1 ;017F02811234 - test_h_gr32 0x1235, er1 ; 13 - test_h_gr32 foo, er2 - mova/b.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12811234 - test_h_gr32 0x1235, er1 ; 18 - test_h_gr32 foo, er2 - mova/b.l @(0x1234:16,@er2+.b),er1 ;017F82811234 - test_h_gr32 0x1235, er1 ; 14 - test_h_gr32 foo+1, er2 - mova/b.l @(0x1234:16,@-er2.b),er1 ;017FB2811234 - test_h_gr32 0x1235, er1 ; 17 - test_h_gr32 foo, er2 - mova/b.l @(0x1234:16,@+er2.b),er1 ;017F92811234 - test_h_gr32 0x1235, er1 ; 16 - test_h_gr32 foo+1, er2 - mova/b.l @(0x1234:16,@er2-.b),er1 ;017FA2811234 - test_h_gr32 0x1235, er1 ; 15 - test_h_gr32 foo, er2 -t02d: - mov.l #4, er2 - mova/b.l @(0x1234:16, @(foo:16, er2).b), er1 - test_h_gr32 0x1244, er1 ; 19 - mova/b.l @(0x1234:16, @(foo:16, r2L.b).b), er1 - test_h_gr32 0x1244, er1 ; 21 - mova/b.l @(0x1234:16, @(foo:16, r2.w).b), er1 - test_h_gr32 0x1244, er1 ; 22 - mova/b.l @(0x1234:16, @(foo:16, er2.l).b), er1 - test_h_gr32 0x1244, er1 ; 23 - - mov.l #4, er2 - mova/b.l @(0x1234:16, @(foo:32, er2).b), er1 - test_h_gr32 0x1244, er1 ; 20 - mova/b.l @(0x1234:16, @(foo:32, r2L.b).b), er1 - test_h_gr32 0x1244, er1 ; 24 - mova/b.l @(0x1234:16, @(foo:32, r2.w).b), er1 - test_h_gr32 0x1244, er1 ; 25 - mova/b.l @(0x1234:16, @(foo:32, er2.l).b), er1 - test_h_gr32 0x1244, er1 ; 26 - - mova/b.l @(0x1234:16,@foo:16.b),er1 - test_h_gr32 0x1235, er1 ; 27 - mova/b.l @(0x1234:16,@foo:32.b),er1 - test_h_gr32 0x1235, er1 ; 28 - -t02e: - mov.l #foo, er2 - mova/b.l @(0x1234:16,@er2.w),er1 ;015F02911234 - test_h_gr32 0x1335, er1 ; 29 - test_h_gr32 foo, er2 - mova/b.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12911234 - test_h_gr32 0x1335, er1 ; 34 - test_h_gr32 foo, er2 - mova/b.l @(0x1234:16,@er2+.w),er1 ;015F82911234 - test_h_gr32 0x1335, er1 ; 30 - test_h_gr32 foo+2, er2 - mova/b.l @(0x1234:16,@-er2.w),er1 ;015FB2911234 - test_h_gr32 0x1335, er1 ; 33 - test_h_gr32 foo, er2 - mova/b.l @(0x1234:16,@+er2.w),er1 ;015F92911234 - test_h_gr32 0x1335, er1 ; 32 - test_h_gr32 foo+2, er2 - mova/b.l @(0x1234:16,@er2-.w),er1 ;015FA2911234 - test_h_gr32 0x1335, er1 ; 31 - test_h_gr32 foo, er2 - - mov.l #4, er2 - mova/b.l @(0x1234:16, @(foo:16, er2).w), er1 - test_h_gr32 0x2244, er1 ; 35 - shar.l er2 - mova/b.l @(0x1234:16, @(foo:16, r2L.b).w), er1 - test_h_gr32 0x2244, er1 ; 37 - mova/b.l @(0x1234:16, @(foo:16, r2.w).w), er1 - test_h_gr32 0x2244, er1 ; 38 - mova/b.l @(0x1234:16, @(foo:16, er2.l).w), er1 - test_h_gr32 0x2244, er1 ; 39 - - mov.l #4, er2 - mova/b.l @(0x1234:16, @(foo:32, er2).w), er1 - test_h_gr32 0x2244, er1 ; 36 - shar.l er2 - mova/b.l @(0x1234:16, @(foo:32, r2L.b).w), er1 - test_h_gr32 0x2244, er1 ; 40 - mova/b.l @(0x1234:16, @(foo:32, r2.w).w), er1 - test_h_gr32 0x2244, er1 ; 41 - mova/b.l @(0x1234:16, @(foo:32, er2.l).w), er1 - test_h_gr32 0x2244, er1 ; 42 - - mova/b.l @(0x1234:16,@foo:16.w),er1 ;015F40919ABC1234 - test_h_gr32 0x1335, er1 ; 43 - mova/b.l @(0x1234:16,@foo:32.w),er1 ;015F48919ABCDEF01234 - test_h_gr32 0x1335, er1 ; 44 - -t02f: - mov.l #foo, er2 - mova/w.l @(0x1234:16,@er2.b),er1 ;017F02A11234 - test_h_gr32 0x1236, er1 ; 45 - mova/w.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12A11234 - test_h_gr32 0x1236, er1 ; 50 - mova/w.l @(0x1234:16,@er2+.b),er1 ;017F82A11234 - test_h_gr32 0x1236, er1 ; 46 - test_h_gr32 foo+1, er2 - mova/w.l @(0x1234:16,@-er2.b),er1 ;017FB2A11234 - test_h_gr32 0x1236, er1 ; 49 - test_h_gr32 foo, er2 - mova/w.l @(0x1234:16,@+er2.b),er1 ;017F92A11234 - test_h_gr32 0x1236, er1 ; 48 - test_h_gr32 foo+1, er2 - mova/w.l @(0x1234:16,@er2-.b),er1 ;017FA2A11234 - test_h_gr32 0x1236, er1 ; 47 - test_h_gr32 foo, er2 - -t02g: - mov.l #4, er2 - mova/w.l @(0x1234:16, @(foo:16, er2).b), er1 - test_h_gr32 0x1254, er1 ; 51 - mova/w.l @(0x1234:16, @(foo:16, r2L.b).b), er1 - test_h_gr32 0x1254, er1 ; 53 - mova/w.l @(0x1234:16, @(foo:16, r2.w).b), er1 - test_h_gr32 0x1254, er1 ; 54 - mova/w.l @(0x1234:16, @(foo:16, er2.l).b), er1 - test_h_gr32 0x1254, er1 ; 55 - - mov.l #4, er2 - mova/w.l @(0x1234:16, @(foo:32, er2).b), er1 - test_h_gr32 0x1254, er1 ; 52 - mova/w.l @(0x1234:16, @(foo:32, r2L.b).b), er1 - test_h_gr32 0x1254, er1 ; 56 - mova/w.l @(0x1234:16, @(foo:32, r2.w).b), er1 - test_h_gr32 0x1254, er1 ; 57 - mova/w.l @(0x1234:16, @(foo:32, er2.l).b), er1 - test_h_gr32 0x1254, er1 ; 58 - - mova/w.l @(0x1234:16,@foo:16.b),er1 ;017F40A19ABC1234 - test_h_gr32 0x1236, er1 ; 59 (can't test -- points into the woods) - mova/w.l @(0x1234:16,@foo:32.b),er1 ;017F48A19ABCDEF01234 - test_h_gr32 0x1236, er1 ; 60 (can't test -- points into the woods) - -t02h: - mov.l #foo, er2 - mova/w.l @(0x1234:16,@er2.w),er1 ;015F02B11234 - test_h_gr32 0x1436, er1 ; 61 - mova/w.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12B11234 - test_h_gr32 0x1436, er1 ; 66, 0x1234 + (@(4+foo).w << 1 - mova/w.l @(0x1234:16,@er2+.w),er1 ;015F82B11234 - test_h_gr32 0x1436, er1 ; 62 - test_h_gr32 foo+2, er2 - mova/w.l @(0x1234:16,@-er2.w),er1 ;015FB2B11234 - test_h_gr32 0x1436, er1 ; 63 - test_h_gr32 foo, er2 - mova/w.l @(0x1234:16,@+er2.w),er1 ;015F92B11234 - test_h_gr32 0x1436, er1 ; 64 - test_h_gr32 foo+2, er2 - mova/w.l @(0x1234:16,@er2-.w),er1 ;015FA2B11234 - test_h_gr32 0x1436, er1 ; 65 - test_h_gr32 foo, er2 -t02i: - mov.l #4, er2 - mova/w.l @(0x1234:16, @(foo:16, er2).w), er1 - test_h_gr32 0x3254, er1 ; 67 - shar.l er2 - mova/w.l @(0x1234:16, @(foo:16, r2L.b).w), er1 - test_h_gr32 0x3254, er1 ; 69 - mova/w.l @(0x1234:16, @(foo:16, r2.w).w), er1 - test_h_gr32 0x3254, er1 ; 70 - mova/w.l @(0x1234:16, @(foo:16, er2.l).w), er1 - test_h_gr32 0x3254, er1 ; 71 - - mov.l #4, er2 - mova/w.l @(0x1234:16, @(foo:32, er2).w), er1 - test_h_gr32 0x3254, er1 ; 68 - shar.l er2 - mova/w.l @(0x1234:16, @(foo:32, r2L.b).w), er1 - test_h_gr32 0x3254, er1 ; 72 - mova/w.l @(0x1234:16, @(foo:32, r2.w).w), er1 - test_h_gr32 0x3254, er1 ; 73 - mova/w.l @(0x1234:16, @(foo:32, er2.l).w), er1 - test_h_gr32 0x3254, er1 ; 74 - - mova/w.l @(0x1234:16,@foo:16.w),er1 ;015F40B19ABC1234 - test_h_gr32 0x1436, er1 ; 75 (can't test -- points into the woods) - mova/w.l @(0x1234:16,@foo:32.w),er1 ;015F48B19ABCDEF01234 - test_h_gr32 0x1436, er1 ; 76 (can't test -- points into the woods) - -t02j: - mov.l #foo, er2 - mova/l.l @(0x1234:16,@er2.b),er1 ;017F02C11234 - test_h_gr32 0x1238, er1 ; 77 - mova/l.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12C11234 - test_h_gr32 0x1238, er1 ; 82 - mova/l.l @(0x1234:16,@er2+.b),er1 ;017F82C11234 - test_h_gr32 0x1238, er1 ; 78 - test_h_gr32 foo+1, er2 - mova/l.l @(0x1234:16,@-er2.b),er1 ;017FB2C11234 - test_h_gr32 0x1238, er1 ; 79 - test_h_gr32 foo, er2 - mova/l.l @(0x1234:16,@+er2.b),er1 ;017F92C11234 - test_h_gr32 0x1238, er1 ; 80 - test_h_gr32 foo+1, er2 - mova/l.l @(0x1234:16,@er2-.b),er1 ;017FA2C11234 - test_h_gr32 0x1238, er1 ; 81 - test_h_gr32 foo, er2 - -t02k: - mov.l #4, er2 - mova/l.l @(0x1234:16, @(foo:16, er2).b), er1 - test_h_gr32 0x1274, er1 ; 83 - mova/l.l @(0x1234:16, @(foo:16, r2L.b).b), er1 - test_h_gr32 0x1274, er1 ; 85 - mova/l.l @(0x1234:16, @(foo:16, r2.w).b), er1 - test_h_gr32 0x1274, er1 ; 86 - mova/l.l @(0x1234:16, @(foo:16, er2.l).b), er1 - test_h_gr32 0x1274, er1 ; 87 - - mov.l #4, er2 - mova/l.l @(0x1234:16, @(foo:32, er2).b), er1 - test_h_gr32 0x1274, er1 ; 84 - mova/l.l @(0x1234:16, @(foo:32, r2L.b).b), er1 - test_h_gr32 0x1274, er1 ; 88 - mova/l.l @(0x1234:16, @(foo:32, r2.w).b), er1 - test_h_gr32 0x1274, er1 ; 89 - mova/l.l @(0x1234:16, @(foo:32, er2.l).b), er1 - test_h_gr32 0x1274, er1 ; 90 - - mova/l.l @(0x1234:16,@foo:16.b),er1 ;017F40C19ABC1234 - test_h_gr32 0x1238, er1 ; 91 (can't test -- points into the woods) - mova/l.l @(0x1234:16,@foo:32.b),er1 ;017F48C19ABCDEF01234 - test_h_gr32 0x1238, er1 ; 92 (can't test -- points into the woods) - -t02l: - mov.l #foo, er2 - mova/l.l @(0x1234:16,@er2.w),er1 ;015F02D11234 - test_h_gr32 0x1638, er1 ; 93 - mova/l.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12D11234 - test_h_gr32 0x1638, er1 ; 98 - mova/l.l @(0x1234:16,@er2+.w),er1 ;015F82D11234 - test_h_gr32 0x1638, er1 ; 94 - test_h_gr32 foo+2, er2 - mova/l.l @(0x1234:16,@-er2.w),er1 ;015FB2D11234 - test_h_gr32 0x1638, er1 ; 97 - test_h_gr32 foo, er2 - mova/l.l @(0x1234:16,@+er2.w),er1 ;015F92D11234 - test_h_gr32 0x1638, er1 ; 96 - test_h_gr32 foo+2, er2 - mova/l.l @(0x1234:16,@er2-.w),er1 ;015FA2D11234 - test_h_gr32 0x1638, er1 ; 95 - test_h_gr32 foo, er2 - -t02o: - mov.l #4, er2 - mova/l.l @(0x1234:16, @(foo:16, er2).w), er1 - test_h_gr32 0x5274, er1 ; 99 - shar.l er2 - mova/l.l @(0x1234:16, @(foo:16, r2L.b).w), er1 - test_h_gr32 0x5274, er1 ; 101 - mova/l.l @(0x1234:16, @(foo:16, r2.w).w), er1 - test_h_gr32 0x5274, er1 ; 102 - mova/l.l @(0x1234:16, @(foo:16, er2.l).w), er1 - test_h_gr32 0x5274, er1 ; 103 - - mov.l #4, er2 - mova/l.l @(0x1234:16, @(foo:32, er2).w), er1 - test_h_gr32 0x5274, er1 ; 100 - shar.l er2 - mova/l.l @(0x1234:16, @(foo:32, r2L.b).w), er1 - test_h_gr32 0x5274, er1 ; 104 - mova/l.l @(0x1234:16, @(foo:32, r2.w).w), er1 - test_h_gr32 0x5274, er1 ; 105 - mova/l.l @(0x1234:16, @(foo:32, er2.l).w), er1 - test_h_gr32 0x5274, er1 ; 106 - - mova/l.l @(0x1234:16,@foo:16.w),er1 ;015F40D19ABC1234 - test_h_gr32 0x1638, er1 ; 107 (can't test -- points into the woods) - mova/l.l @(0x1234:16,@foo:32.w),er1 ;015F48D19ABCDEF01234 - test_h_gr32 0x1638, er1 ; 108 (can't test -- points into the woods) - -t02p: - mov.l #foo, er2 - mova/b.l @(0x12345678:32,@er2.b),er1 ;017F028912345678 - test_h_gr32 0x12345679, er1 ; 109 - mova/b.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F128912345678 - test_h_gr32 0x12345679, er1 ; 114 - mova/b.l @(0x12345678:32,@er2+.b),er1 ;017F828912345678 - test_h_gr32 0x12345679, er1 ; 110 - test_h_gr32 foo+1, er2 - mova/b.l @(0x12345678:32,@-er2.b),er1 ;017FB28912345678 - test_h_gr32 0x12345679, er1 ; 113 - test_h_gr32 foo, er2 - mova/b.l @(0x12345678:32,@+er2.b),er1 ;017F928912345678 - test_h_gr32 0x12345679, er1 ; 112 - test_h_gr32 foo+1, er2 - mova/b.l @(0x12345678:32,@er2-.b),er1 ;017FA28912345678 - test_h_gr32 0x12345679, er1 ; 111 - test_h_gr32 foo, er2 - -t02q: - mov.l #4, er2 - mova/b.l @(0x12345678:32, @(foo:16, er2).b), er1 - test_h_gr32 0x12345688, er1 ; 115 - mova/b.l @(0x12345678:32, @(foo:16, r2L.b).b), er1 - test_h_gr32 0x12345688, er1 ; 117 - mova/b.l @(0x12345678:32, @(foo:16, r2.w).b), er1 - test_h_gr32 0x12345688, er1 ; 118 - mova/b.l @(0x12345678:32, @(foo:16, er2.l).b), er1 - test_h_gr32 0x12345688, er1 ; 119 - - mov.l #4, er2 - mova/b.l @(0x12345678:32, @(foo:32, er2).b), er1 - test_h_gr32 0x12345688, er1 ; 116 - mova/b.l @(0x12345678:32, @(foo:32, r2L.b).b), er1 - test_h_gr32 0x12345688, er1 ; 120 - mova/b.l @(0x12345678:32, @(foo:32, r2.w).b), er1 - test_h_gr32 0x12345688, er1 ; 121 - mova/b.l @(0x12345678:32, @(foo:32, er2.l).b), er1 - test_h_gr32 0x12345688, er1 ; 122 - - mova/b.l @(0x12345678:32,@foo:16.b),er1 - test_h_gr32 0x12345679, er1 ; 123 - mova/b.l @(0x12345678:32,@foo:32.b),er1 - test_h_gr32 0x12345679, er1 ; 124 - -t02r: - mov.l #foo, er2 - mova/b.l @(0x12345678:32,@er2.w),er1 ;015F029912345678 - test_h_gr32 0x12345779, er1 ; 125 - mova/b.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F129912345678 - test_h_gr32 0x12345779, er1 ; 130 - mova/b.l @(0x12345678:32,@er2+.w),er1 ;015F829912345678 - test_h_gr32 0x12345779, er1 ; 126 - test_h_gr32 foo+2, er2 - mova/b.l @(0x12345678:32,@-er2.w),er1 ;015FB29912345678 - test_h_gr32 0x12345779, er1 ; 129 - test_h_gr32 foo, er2 - mova/b.l @(0x12345678:32,@+er2.w),er1 ;015F929912345678 - test_h_gr32 0x12345779, er1 ; 128 - test_h_gr32 foo+2, er2 - mova/b.l @(0x12345678:32,@er2-.w),er1 ;015FA29912345678 - test_h_gr32 0x12345779, er1 ; 127 - test_h_gr32 foo, er2 - - mov.l #4, er2 - mova/b.l @(0x12345678:32, @(foo:16, er2).w), er1 - test_h_gr32 0x12346688, er1 ; 131 - shar.l er2 - mova/b.l @(0x12345678:32, @(foo:16, r2L.b).w), er1 - test_h_gr32 0x12346688, er1 ; 133 - mova/b.l @(0x12345678:32, @(foo:16, r2.w).w), er1 - test_h_gr32 0x12346688, er1 ; 134 - mova/b.l @(0x12345678:32, @(foo:16, er2.l).w), er1 - test_h_gr32 0x12346688, er1 ; 135 - - mov.l #4, er2 - mova/b.l @(0x12345678:32, @(foo:32, er2).w), er1 - test_h_gr32 0x12346688, er1 ; 132 - shar.l er2 - mova/b.l @(0x12345678:32, @(foo:32, r2L.b).w), er1 - test_h_gr32 0x12346688, er1 ; 136 - mova/b.l @(0x12345678:32, @(foo:32, r2.w).w), er1 - test_h_gr32 0x12346688, er1 ; 137 - mova/b.l @(0x12345678:32, @(foo:32, er2.l).w), er1 - test_h_gr32 0x12346688, er1 ; 138 - - mova/b.l @(0x12345678:32,@foo:16.w),er1 - test_h_gr32 0x12345779, er1 ; 139 - mova/b.l @(0x12345678:32,@foo:32.w),er1 - test_h_gr32 0x12345779, er1 ; 140 - -t02s: - mov.l #foo, er2 - mova/w.l @(0x12345678:32,@er2.b),er1 ;017F02A912345678 - test_h_gr32 0x1234567a, er1 ; 141 - mova/w.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12A912345678 - test_h_gr32 0x1234567a, er1 ; 146 - mova/w.l @(0x12345678:32,@er2+.b),er1 ;017F82A912345678 - test_h_gr32 0x1234567a, er1 ; 142 - test_h_gr32 foo+1, er2 - mova/w.l @(0x12345678:32,@-er2.b),er1 ;017FB2A912345678 - test_h_gr32 0x1234567a, er1 ; 145 - test_h_gr32 foo, er2 - mova/w.l @(0x12345678:32,@+er2.b),er1 ;017F92A912345678 - test_h_gr32 0x1234567a, er1 ; 144 - test_h_gr32 foo+1, er2 - mova/w.l @(0x12345678:32,@er2-.b),er1 ;017FA2A912345678 - test_h_gr32 0x1234567a, er1 ; 143 - test_h_gr32 foo, er2 - - mov.l #4, er2 - mova/w.l @(0x12345678:32, @(foo:16, er2).b), er1 - test_h_gr32 0x12345698, er1 ; 147 - mova/w.l @(0x12345678:32, @(foo:16, r2L.b).b), er1 - test_h_gr32 0x12345698, er1 ; 149 - mova/w.l @(0x12345678:32, @(foo:16, r2.w).b), er1 - test_h_gr32 0x12345698, er1 ; 150 - mova/w.l @(0x12345678:32, @(foo:16, er2.l).b), er1 - test_h_gr32 0x12345698, er1 ; 151 - - mov.l #4, er2 - mova/w.l @(0x12345678:32, @(foo:32, er2).b), er1 - test_h_gr32 0x12345698, er1 ; 148 - mova/w.l @(0x12345678:32, @(foo:32, r2L.b).b), er1 - test_h_gr32 0x12345698, er1 ; 152 - mova/w.l @(0x12345678:32, @(foo:32, r2.w).b), er1 - test_h_gr32 0x12345698, er1 ; 153 - mova/w.l @(0x12345678:32, @(foo:32, er2.l).b), er1 - test_h_gr32 0x12345698, er1 ; 154 - - mova/w.l @(0x12345678:32,@foo:16.b),er1 - test_h_gr32 0x1234567a, er1 ; 155 - mova/w.l @(0x12345678:32,@foo:32.b),er1 - test_h_gr32 0x1234567a, er1 ; 156 - -t02t: - mov.l #foo, er2 - mova/w.l @(0x12345678:32,@er2.w),er1 ;015F02B912345678 - test_h_gr32 0x1234587a, er1 ; 157 - mova/w.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12B912345678 - test_h_gr32 0x1234587a, er1 ; 162 - mova/w.l @(0x12345678:32,@er2+.w),er1 ;015F82B912345678 - test_h_gr32 0x1234587a, er1 ; 158 - test_h_gr32 foo+2, er2 - mova/w.l @(0x12345678:32,@-er2.w),er1 ;015FB2B912345678 - test_h_gr32 0x1234587a, er1 ; 161 - test_h_gr32 foo, er2 - mova/w.l @(0x12345678:32,@+er2.w),er1 ;015F92B912345678 - test_h_gr32 0x1234587a, er1 ; 160 - test_h_gr32 foo+2, er2 - mova/w.l @(0x12345678:32,@er2-.w),er1 ;015FA2B912345678 - test_h_gr32 0x1234587a, er1 ; 159 - test_h_gr32 foo, er2 - - mov.l #4, er2 - mova/w.l @(0x12345678:32, @(foo:16, er2).w), er1 - test_h_gr32 0x12347698, er1 ; 163 - shar.l er2 - mova/w.l @(0x12345678:32, @(foo:16, r2L.b).w), er1 - test_h_gr32 0x12347698, er1 ; 165 - mova/w.l @(0x12345678:32, @(foo:16, r2.w).w), er1 - test_h_gr32 0x12347698, er1 ; 166 - mova/w.l @(0x12345678:32, @(foo:16, er2.l).w), er1 - test_h_gr32 0x12347698, er1 ; 167 - - mov.l #4, er2 - mova/w.l @(0x12345678:32, @(foo:32, er2).w), er1 - test_h_gr32 0x12347698, er1 ; 164 - shar.l er2 - mova/w.l @(0x12345678:32, @(foo:32, r2L.b).w), er1 - test_h_gr32 0x12347698, er1 ; 168 - mova/w.l @(0x12345678:32, @(foo:32, r2.w).w), er1 - test_h_gr32 0x12347698, er1 ; 169 - mova/w.l @(0x12345678:32, @(foo:32, er2.l).w), er1 - test_h_gr32 0x12347698, er1 ; 170 - - mova/w.l @(0x12345678:32,@foo:16.w),er1 - test_h_gr32 0x1234587a, er1 ; 171 - mova/w.l @(0x12345678:32,@foo:32.w),er1 - test_h_gr32 0x1234587a, er1 ; 172 - -t02u: - mov.l #foo, er2 - mova/l.l @(0x12345678:32,@er2.b),er1 ;017F02C912345678 - test_h_gr32 0x1234567c, er1 ; 173 - mova/l.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12C912345678 - test_h_gr32 0x1234567c, er1 ; 178 - mova/l.l @(0x12345678:32,@er2+.b),er1 ;017F82C912345678 - test_h_gr32 0x1234567c, er1 ; 174 - test_h_gr32 foo+1, er2 - mova/l.l @(0x12345678:32,@-er2.b),er1 ;017FB2C912345678 - test_h_gr32 0x1234567c, er1 ; 177 - test_h_gr32 foo, er2 - mova/l.l @(0x12345678:32,@+er2.b),er1 ;017F92C912345678 - test_h_gr32 0x1234567c, er1 ; 176 - test_h_gr32 foo+1, er2 - mova/l.l @(0x12345678:32,@er2-.b),er1 ;017FA2C912345678 - test_h_gr32 0x1234567c, er1 ; 175 - test_h_gr32 foo, er2 - - mov.l #4, er2 - mova/l.l @(0x12345678:32, @(foo:16, er2).b), er1 - test_h_gr32 0x123456b8, er1 ; 179 - mova/l.l @(0x12345678:32, @(foo:16, r2L.b).b), er1 - test_h_gr32 0x123456b8, er1 ; 181 - mova/l.l @(0x12345678:32, @(foo:16, r2.w).b), er1 - test_h_gr32 0x123456b8, er1 ; 182 - mova/l.l @(0x12345678:32, @(foo:16, er2.l).b), er1 - test_h_gr32 0x123456b8, er1 ; 183 - - mov.l #4, er2 - mova/l.l @(0x12345678:32, @(foo:32, er2).b), er1 - test_h_gr32 0x123456b8, er1 ; 180 - mova/l.l @(0x12345678:32, @(foo:32, r2L.b).b), er1 - test_h_gr32 0x123456b8, er1 ; 184 - mova/l.l @(0x12345678:32, @(foo:32, r2.w).b), er1 - test_h_gr32 0x123456b8, er1 ; 185 - mova/l.l @(0x12345678:32, @(foo:32, er2.l).b), er1 - test_h_gr32 0x123456b8, er1 ; 186 - - mova/l.l @(0x12345678:32,@foo:16.b),er1 - test_h_gr32 0x1234567c, er1 ; 187 - mova/l.l @(0x12345678:32,@foo:32.b),er1 - test_h_gr32 0x1234567c, er1 ; 188 - -t02v: - mov.l #foo, er2 - mova/l.l @(0x12345678:32,@er2.w),er1 ;015F02D912345678 - test_h_gr32 0x12345a7c, er1 ; 189 - mova/l.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12D912345678 - test_h_gr32 0x12345a7c, er1 ; 194 - mova/l.l @(0x12345678:32,@er2+.w),er1 ;015F82D912345678 - test_h_gr32 0x12345a7c, er1 ; 190 - test_h_gr32 foo+2, er2 - mova/l.l @(0x12345678:32,@-er2.w),er1 ;015FB2D912345678 - test_h_gr32 0x12345a7c, er1 ; 193 - test_h_gr32 foo, er2 - mova/l.l @(0x12345678:32,@+er2.w),er1 ;015F92D912345678 - test_h_gr32 0x12345a7c, er1 ; 192 - test_h_gr32 foo+2, er2 - mova/l.l @(0x12345678:32,@er2-.w),er1 ;015FA2D912345678 - test_h_gr32 0x12345a7c, er1 ; 191 - test_h_gr32 foo, er2 - - mov.l #4, er2 - mova/l.l @(0x12345678:32, @(foo:16, er2).w), er1 - test_h_gr32 0x123496b8, er1 ; 195 - shar.l er2 - mova/l.l @(0x12345678:32, @(foo:16, r2L.b).w), er1 - test_h_gr32 0x123496b8, er1 ; 197 - mova/l.l @(0x12345678:32, @(foo:16, r2.w).w), er1 - test_h_gr32 0x123496b8, er1 ; 198 - mova/l.l @(0x12345678:32, @(foo:16, er2.l).w), er1 - test_h_gr32 0x123496b8, er1 ; 199 - - mov.l #4, er2 - mova/l.l @(0x12345678:32, @(foo:32, er2).w), er1 - test_h_gr32 0x123496b8, er1 ; 195 - shar.l er2 - mova/l.l @(0x12345678:32, @(foo:32, r2L.b).w), er1 - test_h_gr32 0x123496b8, er1 ; 197 - mova/l.l @(0x12345678:32, @(foo:32, r2.w).w), er1 - test_h_gr32 0x123496b8, er1 ; 198 - mova/l.l @(0x12345678:32, @(foo:32, er2.l).w), er1 - test_h_gr32 0x123496b8, er1 ; 199 - - mova/l.l @(0x12345678:32,@foo:16.w),er1 - test_h_gr32 0x12345a7c, er1 ; 203 - mova/l.l @(0x12345678:32,@foo:32.w),er1 - test_h_gr32 0x12345a7c, er1 ; 204 - - test_gr_a5a5 0 - test_h_gr32 2, er2 - test_h_gr32 0x01010101, er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/movb.s b/sim/testsuite/sim/h8300/movb.s deleted file mode 100644 index 87dcdf3..0000000 --- a/sim/testsuite/sim/h8300/movb.s +++ /dev/null @@ -1,2221 +0,0 @@ -# Hitachi H8 testcase 'mov.w' -# mach(): h8300h h8300s h8sx -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data - .align 4 -byte_src: - .byte 0x77 -byte_dst: - .byte 0 - - .text - - ;; - ;; Move byte from immediate source - ;; - -.if (sim_cpu == h8sx) -mov_b_imm8_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, rd - mov.b #0x77:8, r0l ; Immediate 3-bit operand -;;; .word 0xf877 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu == h8sx) -mov_b_imm4_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:4, @aa:16 - mov.b #0xf:4, @byte_dst:16 ; 16-bit address-direct operand -;;; .word 0x6adf -;;; .word @byte_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xf, @byte_dst - beq .Lnext21 - fail -.Lnext21: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm4_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:4, @aa:32 - mov.b #0xf:4, @byte_dst:32 ; 32-bit address-direct operand -;;; .word 0x6aff -;;; .long @byte_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xf, @byte_dst - beq .Lnext22 - fail -.Lnext22: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @erd - mov.l #byte_dst, er1 - mov.b #0xa5:8, @er1 ; Register indirect operand -;;; .word 0x017d -;;; .word 0x01a5 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext1 - fail -.Lnext1: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_postinc: ; post-increment from imm8 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @erd+ - mov.l #byte_dst, er1 - mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands. -;;; .word 0x017d -;;; .word 0x81a5 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst+1, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext2 - fail -.Lnext2: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_postdec: ; post-decrement from imm8 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @erd- - mov.l #byte_dst, er1 - mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands. -;;; .word 0x017d -;;; .word 0xa1a5 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst-1, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext3 - fail -.Lnext3: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @+erd - mov.l #byte_dst-1, er1 - mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands -;;; .word 0x017d -;;; .word 0x91a5 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext4 - fail -.Lnext4: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @-erd - mov.l #byte_dst+1, er1 - mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands -;;; .word 0x017d -;;; .word 0xb1a5 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext5 - fail -.Lnext5: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @(dd:2, erd) - mov.l #byte_dst-3, er1 - mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand -;;; .word 0x017d -;;; .word 0x31a5 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext6 - fail -.Lnext6: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @(dd:16, erd) - mov.l #byte_dst-4, er1 - mov.b #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x017d -;;; .word 0x6f90 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext7 - fail -.Lnext7: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @(dd:32, erd) - mov.l #byte_dst-8, er1 - mov.b #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x017d -;;; .word 0xc9a5 -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext8 - fail -.Lnext8: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_indexb16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffffff01, er1 - set_ccr_zero - ;; mov.b #xx:8, @(dd:16, rd.b) - mov.b #0xa5:8, @(byte_dst-1:16, r1.b) ; byte indexed operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 0xffffff01, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_indexw16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffff0002, er1 - set_ccr_zero - ;; mov.b #xx:8, @(dd:16, rd.w) - mov.b #0xa5:8, @(byte_dst-2:16, r1.w) ; byte indexed operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 0xffff0002, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_indexl16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0x00000003, er1 - set_ccr_zero - ;; mov.b #xx:8, @(dd:16, erd.l) - mov.b #0xa5:8, @(byte_dst-3:16, er1.l) ; byte indexed operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 0x00000003, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_indexb32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffffff04, er1 - set_ccr_zero - ;; mov.b #xx:8, @(dd:32, rd.b) - mov.b #0xa5:8, @(byte_dst-4:32, r1.b) ; byte indexed operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 0xffffff04 er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_indexw32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffff0005, er1 - set_ccr_zero - ;; mov.b #xx:8, @(dd:32, rd.w) - mov.b #0xa5:8, @(byte_dst-5:32, r1.w) ; byte indexed operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 0xffff0005 er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_indexl32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0x00000006, er1 - set_ccr_zero - ;; mov.b #xx:8, @(dd:32, erd.l) - mov.b #0xa5:8, @(byte_dst-6:32, er1.l) ; byte indexed operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 0x00000006 er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @aa:16 - mov.b #0xa5:8, @byte_dst:16 ; 16-bit address-direct operand -;;; .word 0x017d -;;; .word 0x40a5 -;;; .word @byte_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext9 - fail -.Lnext9: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_imm8_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b #xx:8, @aa:32 - mov.b #0xa5:8, @byte_dst:32 ; 32-bit address-direct operand -;;; .word 0x017d -;;; .word 0x48a5 -;;; .long @byte_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b #0xa5, @byte_dst - beq .Lnext10 - fail -.Lnext10: - mov.b #0, @byte_dst ; zero it again for the next use. - -.endif - - ;; - ;; Move byte from register source - ;; - -mov_b_reg8_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, erd - mov.b #0x12, r1l - mov.b r1l, r0l ; Register 8-bit operand -;;; .word 0x0c98 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - test_h_gr16 0xa512 r0 - test_h_gr16 0xa512 r1 ; mov src unchanged -.if (sim_cpu) - test_h_gr32 0xa5a5a512 er0 - test_h_gr32 0xa5a5a512 er1 ; mov src unchanged -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -mov_b_reg8_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @erd - mov.l #byte_dst, er1 - mov.b r0l, @er1 ; Register indirect operand -;;; .word 0x6898 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.b @byte_dst, r0l - cmp.b r2l, r0l - beq .Lnext44 - fail -.Lnext44: - mov.b #0, r0l - mov.b r0l, @byte_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_b_reg8_to_postinc: ; post-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @erd+ - mov.l #byte_dst, er1 - mov.b r0l, @er1+ ; Register post-incr operand -;;; .word 0x0173 -;;; .word 0x6c98 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst+1, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b r2l, @byte_dst - beq .Lnext49 - fail -.Lnext49: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_postdec: ; post-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @erd- - mov.l #byte_dst, er1 - mov.b r0l, @er1- ; Register post-decr operand -;;; .word 0x0171 -;;; .word 0x6c98 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst-1, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b r2l, @byte_dst - beq .Lnext50 - fail -.Lnext50: - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @+erd - mov.l #byte_dst-1, er1 - mov.b r0l, @+er1 ; Register pre-incr operand -;;; .word 0x0172 -;;; .word 0x6c98 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b r2l, @byte_dst - beq .Lnext51 - fail -.Lnext51: - mov.b #0, @byte_dst ; zero it again for the next use. -.endif - -mov_b_reg8_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @-erd - mov.l #byte_dst+1, er1 - mov.b r0l, @-er1 ; Register pre-decr operand -;;; .word 0x6c98 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.b @byte_dst, r0l - cmp.b r2l, r0l - beq .Lnext48 - fail -.Lnext48: - mov.b #0, r0l - mov.b r0l, @byte_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_b_reg8_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @(dd:2, erd) - mov.l #byte_dst-3, er1 - mov.b r0l, @(3:2, er1) ; Register plus 2-bit disp. operand -;;; .word 0x0173 -;;; .word 0x6898 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 byte_dst-3, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b r2l, @byte_dst - beq .Lnext52 - fail -.Lnext52: - mov.b #0, @byte_dst ; zero it again for the next use. -.endif - -mov_b_reg8_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @(dd:16, erd) - mov.l #byte_dst-4, er1 - mov.b r0l, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x6e98 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 byte_dst-4, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.b @byte_dst, r0l - cmp.b r2l, r0l - beq .Lnext45 - fail -.Lnext45: - mov.b #0, r0l - mov.b r0l, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @(dd:32, erd) - mov.l #byte_dst-8, er1 - mov.b r0l, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x7810 -;;; .word 0x6aa8 -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 byte_dst-8, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.b @byte_dst, r0l - cmp.b r2l, r0l - beq .Lnext46 - fail -.Lnext46: - mov.b #0, r0l - mov.b r0l, @byte_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_b_reg8_to_indexb16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffffff01, er1 - set_ccr_zero - ;; mov.b ers, @(dd:16, rd.b) - mov.b r0l, @(byte_dst-1:16, r1.b) ; byte indexed operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xffffff01 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_dst, r0l - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_indexw16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffff0002, er1 - set_ccr_zero - ;; mov.b ers, @(dd:16, rd.w) - mov.b r0l, @(byte_dst-2:16, r1.w) ; byte indexed operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xffff0002 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_dst, r0l - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_indexl16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0x00000003, er1 - set_ccr_zero - ;; mov.b ers, @(dd:16, erd.l) - mov.b r0l, @(byte_dst-3:16, er1.l) ; byte indexed operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x00000003 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_dst, r0l - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_indexb32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffffff04 er1 - set_ccr_zero - ;; mov.b ers, @(dd:32, rd.b) - mov.b r0l, @(byte_dst-4:32, r1.b) ; byte indexed operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xffffff04, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_dst, r0l - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_indexw32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffff0005 er1 - set_ccr_zero - ;; mov.b ers, @(dd:32, rd.w) - mov.b r0l, @(byte_dst-5:32, r1.w) ; byte indexed operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xffff0005, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_dst, r0l - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_indexl32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0x00000006 er1 - set_ccr_zero - ;; mov.b ers, @(dd:32, erd.l) - mov.b r0l, @(byte_dst-6:32, er1.l) ; byte indexed operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x00000006, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_dst, r0l - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. -.endif - -.if (sim_cpu == h8sx) -mov_b_reg8_to_abs8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - mov.l #byte_dst-20, er0 - ldc er0, sbr - set_ccr_zero - ;; mov.b ers, @aa:8 - mov.b r1l, @20:8 ; 8-bit address-direct (sbr-relative) operand - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 byte_dst-20, er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_dst, r1l - bne fail1 - mov.b #0, @byte_dst ; zero it again for the next use. -.endif - -mov_b_reg8_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @aa:16 - mov.b r0l, @byte_dst:16 ; 16-bit address-direct operand -;;; .word 0x6a88 -;;; .word @byte_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.b @byte_dst, r0l - cmp.b r0l, r1l - beq .Lnext41 - fail -.Lnext41: - mov.b #0, r0l - mov.b r0l, @byte_dst ; zero it again for the next use. - -mov_b_reg8_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b ers, @aa:32 - mov.b r0l, @byte_dst:32 ; 32-bit address-direct operand -;;; .word 0x6aa8 -;;; .long @byte_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.b @byte_dst, r0l - cmp.b r0l, r1l - beq .Lnext42 - fail -.Lnext42: - mov.b #0, r0l - mov.b r0l, @byte_dst ; zero it again for the next use. - - ;; - ;; Move byte to register destination. - ;; - -mov_b_indirect_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @ers, rd - mov.l #byte_src, er1 - mov.b @er1, r0l ; Register indirect operand -;;; .word 0x6818 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_h_gr32 byte_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_postinc_to_reg8: ; post-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @ers+, rd - - mov.l #byte_src, er1 - mov.b @er1+, r0l ; Register post-incr operand -;;; .word 0x6c18 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_h_gr32 byte_src+1, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mov_b_postdec_to_reg8: ; post-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @ers-, rd - - mov.l #byte_src, er1 - mov.b @er1-, r0l ; Register post-decr operand -;;; .word 0x0172 -;;; .word 0x6c18 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_h_gr32 byte_src-1, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_preinc_to_reg8: ; pre-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @+ers, rd - - mov.l #byte_src-1, er1 - mov.b @+er1, r0l ; Register pre-incr operand -;;; .word 0x0171 -;;; .word 0x6c18 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_h_gr32 byte_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_predec_to_reg8: ; pre-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @-ers, rd - - mov.l #byte_src+1, er1 - mov.b @-er1, r0l ; Register pre-decr operand -;;; .word 0x0173 -;;; .word 0x6c18 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_h_gr32 byte_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -mov_b_disp2_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @(dd:2, ers), rd - mov.l #byte_src-1, er1 - mov.b @(1:2, er1), r0l ; Register plus 2-bit disp. operand -;;; .word 0x0171 -;;; .word 0x6818 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 byte_src-1, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -mov_b_disp16_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @(dd:16, ers), rd - mov.l #byte_src+0x1234, er1 - mov.b @(-0x1234:16, er1), r0l ; Register plus 16-bit disp. operand -;;; .word 0x6e18 -;;; .word -0x1234 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 byte_src+0x1234, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_disp32_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @(dd:32, ers), rd - mov.l #byte_src+65536, er1 - mov.b @(-65536:32, er1), r0l ; Register plus 32-bit disp. operand -;;; .word 0x7810 -;;; .word 0x6a28 -;;; .long -65536 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 byte_src+65536, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mov_b_indexb16_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffffff01, er1 - set_ccr_zero - ;; mov.b @(dd:16, rs.b), rd - mov.b @(byte_src-1:16, r1.b), r0l ; indexed byte operand - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 - - test_h_gr32 0xffffff01, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_indexw16_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffff0002, er1 - set_ccr_zero - ;; mov.b @(dd:16, rs.w), rd - mov.b @(byte_src-2:16, r1.w), r0l ; indexed byte operand - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 - - test_h_gr32 0xffff0002, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_indexl16_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0x00000003, er1 - set_ccr_zero - ;; mov.b @(dd:16, ers.l), rd - mov.b @(byte_src-3:16, er1.l), r0l ; indexed byte operand - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 - - test_h_gr32 0x00000003, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_indexb32_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffffff04, er1 - set_ccr_zero - ;; mov.b @(dd:32, rs.b), rd - mov.b @(byte_src-4:32, r1.b), r0l ; indexed byte operand - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 0xffffff04 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_indexw32_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffff0005, er1 - set_ccr_zero - ;; mov.b @(dd:32, rs.w), rd - mov.b @(byte_src-5:32, r1.w), r0l ; indexed byte operand - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 0xffff0005 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_indexl32_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0x00000006, er1 - set_ccr_zero - ;; mov.b @(dd:32, ers.l), rd - mov.b @(byte_src-6:32, er1.l), r0l ; indexed byte operand - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 0x00000006 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - -.if (sim_cpu == h8sx) -mov_b_abs8_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #byte_src-255, er1 - ldc er1, sbr - set_ccr_zero - ;; mov.b @aa:8, rd - mov.b @0xff:8, r0l ; 8-bit (sbr relative) address-direct operand - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_h_gr32 byte_src-255, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -mov_b_abs16_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @aa:16, rd - mov.b @byte_src:16, r0l ; 16-bit address-direct operand -;;; .word 0x6a08 -;;; .word @byte_src - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_b_abs32_to_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @aa:32, rd - mov.b @byte_src:32, r0l ; 32-bit address-direct operand -;;; .word 0x6a28 -;;; .long @byte_src - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a5a577 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) - - ;; - ;; Move byte from memory to memory - ;; - -mov_b_indirect_to_indirect: ; reg indirect, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @ers, @erd - - mov.l #byte_src, er1 - mov.l #byte_dst, er0 - mov.b @er1, @er0 -;;; .word 0x0178 -;;; .word 0x0100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst er0 - test_h_gr32 byte_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext55 - fail -.Lnext55: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext56 - fail -.Lnext56: ; OK, pass on. - -mov_b_postinc_to_postinc: ; reg post-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @ers+, @erd+ - - mov.l #byte_src, er1 - mov.l #byte_dst, er0 - mov.b @er1+, @er0+ -;;; .word 0x0178 -;;; .word 0x8180 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst+1 er0 - test_h_gr32 byte_src+1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext65 - fail -.Lnext65: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext66 - fail -.Lnext66: ; OK, pass on. - -mov_b_postdec_to_postdec: ; reg post-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @ers-, @erd- - - mov.l #byte_src, er1 - mov.l #byte_dst, er0 - mov.b @er1-, @er0- -;;; .word 0x0178 -;;; .word 0xa1a0 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst-1 er0 - test_h_gr32 byte_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext75 - fail -.Lnext75: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext76 - fail -.Lnext76: ; OK, pass on. - -mov_b_preinc_to_preinc: ; reg pre-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @+ers, @+erd - - mov.l #byte_src-1, er1 - mov.l #byte_dst-1, er0 - mov.b @+er1, @+er0 -;;; .word 0x0178 -;;; .word 0x9190 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst er0 - test_h_gr32 byte_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext85 - fail -.Lnext85: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext86 - fail -.Lnext86: ; OK, pass on. - -mov_b_predec_to_predec: ; reg pre-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @-ers, @-erd - - mov.l #byte_src+1, er1 - mov.l #byte_dst+1, er0 - mov.b @-er1, @-er0 -;;; .word 0x0178 -;;; .word 0xb1b0 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst er0 - test_h_gr32 byte_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext95 - fail -.Lnext95: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext96 - fail -.Lnext96: ; OK, pass on. - -mov_b_disp2_to_disp2: ; reg 2-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @(dd:2, ers), @(dd:2, erd) - - mov.l #byte_src-1, er1 - mov.l #byte_dst-2, er0 - mov.b @(1:2, er1), @(2:2, er0) -;;; .word 0x0178 -;;; .word 0x1120 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst-2 er0 - test_h_gr32 byte_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext105 - fail -.Lnext105: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext106 - fail -.Lnext106: ; OK, pass on. - -mov_b_disp16_to_disp16: ; reg 16-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @(dd:16, ers), @(dd:16, erd) - - mov.l #byte_src-1, er1 - mov.l #byte_dst-2, er0 - mov.b @(1:16, er1), @(2:16, er0) -;;; .word 0x0178 -;;; .word 0xc1c0 -;;; .word 0x0001 -;;; .word 0x0002 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst-2 er0 - test_h_gr32 byte_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext115 - fail -.Lnext115: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext116 - fail -.Lnext116: ; OK, pass on. - -mov_b_disp32_to_disp32: ; reg 32-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @(dd:32, ers), @(dd:32, erd) - - mov.l #byte_src-1, er1 - mov.l #byte_dst-2, er0 - mov.b @(1:32, er1), @(2:32, er0) -;;; .word 0x0178 -;;; .word 0xc9c8 -;;; .long 1 -;;; .long 2 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 byte_dst-2 er0 - test_h_gr32 byte_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext125 - fail -.Lnext125: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext126 - fail -.Lnext126: ; OK, pass on. - -mov_b_indexb16_to_indexb16: ; reg 16-bit indexed, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffffff01, er1 - mov.l #0xffffff02, er0 - ;; mov.b @(dd:16, rs.b), @(dd:16, rd.b) - set_ccr_zero - mov.b @(byte_src-1:16, r1.b), @(byte_dst-2:16, r0.b) - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 0xffffff02 er0 - test_h_gr32 0xffffff01 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - bne fail1 - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - beq fail1 - -mov_b_indexw16_to_indewb16: ; reg 16-bit indexed, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffff0003, er1 - mov.l #0xffff0004, er0 - ;; mov.b @(dd:16, rs.w), @(dd:16, rd.w) - set_ccr_zero - mov.b @(byte_src-3:16, r1.w), @(byte_dst-4:16, r0.w) - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 0xffff0004 er0 - test_h_gr32 0xffff0003 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - bne fail1 - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - beq fail1 - -mov_b_indexl16_to_indexl16: ; reg 16-bit indexed, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0x00000005, er1 - mov.l #0x00000006, er0 - ;; mov.b @(dd:16, ers.l), @(dd:16, erd.l) - set_ccr_zero - mov.b @(byte_src-5:16, er1.l), @(byte_dst-6:16, er0.l) - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 0x00000006 er0 - test_h_gr32 0x00000005 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - bne fail1 - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - beq fail1 - -mov_b_indexb32_to_indexb32: ; reg 32-bit indexed, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffffff01, er1 - mov.l #0xffffff02, er0 - set_ccr_zero - ;; mov.b @(dd:32, rs.b), @(dd:32, rd.b) - mov.b @(byte_src-1:32, r1.b), @(byte_dst-2:32, r0.b) - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 0xffffff02 er0 - test_h_gr32 0xffffff01 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - bne fail1 - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - beq fail1 - -mov_b_indexw32_to_indexw32: ; reg 32-bit indexed, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0xffff0003, er1 - mov.l #0xffff0004, er0 - set_ccr_zero - ;; mov.b @(dd:32, rs.w), @(dd:32, rd.w) - mov.b @(byte_src-3:32, r1.w), @(byte_dst-4:32, r0.w) - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 0xffff0004 er0 - test_h_gr32 0xffff0003 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - bne fail1 - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - beq fail1 - -mov_b_indexl32_to_indexl32: ; reg 32-bit indexed, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - mov.l #0x00000005, er1 - mov.l #0x00000006, er0 - set_ccr_zero - ;; mov.b @(dd:32, rs.w), @(dd:32, rd.w) - mov.b @(byte_src-5:32, er1.l), @(byte_dst-6:32, er0.l) - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 0x00000006 er0 - test_h_gr32 0x00000005 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - bne fail1 - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - beq fail1 - -mov_b_abs16_to_abs16: ; 16-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @aa:16, @aa:16 - - mov.b @byte_src:16, @byte_dst:16 -;;; .word 0x0178 -;;; .word 0x4040 -;;; .word @byte_src -;;; .word @byte_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext135 - fail -.Lnext135: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext136 - fail -.Lnext136: ; OK, pass on. - -mov_b_abs32_to_abs32: ; 32-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.b @aa:32, @aa:32 - - mov.b @byte_src:32, @byte_dst:32 -;;; .word 0x0178 -;;; .word 0x4848 -;;; .long @byte_src -;;; .long @byte_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.b @byte_src, @byte_dst - beq .Lnext145 - fail -.Lnext145: - ;; Now clear the destination location, and verify that. - mov.b #0, @byte_dst - cmp.b @byte_src, @byte_dst - bne .Lnext146 - fail -.Lnext146: ; OK, pass on. - - -.endif - - pass - - exit 0 - -fail1: - fail - \ No newline at end of file diff --git a/sim/testsuite/sim/h8300/movl.s b/sim/testsuite/sim/h8300/movl.s deleted file mode 100644 index dcc3922..0000000 --- a/sim/testsuite/sim/h8300/movl.s +++ /dev/null @@ -1,2160 +0,0 @@ -# Hitachi H8 testcase 'mov.l' -# mach(): h8300h h8300s h8sx -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data - .align 4 -long_src: - .long 0x77777777 -long_dst: - .long 0 - - .text - - ;; - ;; Move long from immediate source - ;; - -.if (sim_cpu == h8sx) -mov_l_imm3_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:3, erd - mov.l #0x3:3, er0 ; Immediate 3-bit operand -;;; .word 0x0fb8 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x3 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_imm16_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, erd - mov.l #0x1234, er0 ; Immediate 16-bit operand -;;; .word 0x7a08 -;;; .word 0x1234 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x1234 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -mov_l_imm32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, erd - mov.l #0x12345678, er0 ; Immediate 32-bit operand -;;; .word 0x7a00 -;;; .long 0x12345678 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x12345678 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mov_l_imm8_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @erd - mov.l #long_dst, er1 - mov.l #0xa5:8, @er1 ; Register indirect operand -;;; .word 0x010d -;;; .word 0x01a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext1 - fail -.Lnext1: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_postinc: ; post-increment from imm8 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @erd+ - mov.l #long_dst, er1 - mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands. -;;; .word 0x010d -;;; .word 0x81a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext2 - fail -.Lnext2: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_postdec: ; post-decrement from imm8 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @erd- - mov.l #long_dst, er1 - mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands. -;;; .word 0x010d -;;; .word 0xa1a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext3 - fail -.Lnext3: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @+erd - mov.l #long_dst-4, er1 - mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands -;;; .word 0x010d -;;; .word 0x91a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext4 - fail -.Lnext4: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @-erd - mov.l #long_dst+4, er1 - mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands -;;; .word 0x010d -;;; .word 0xb1a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext5 - fail -.Lnext5: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @(dd:2, erd) - mov.l #long_dst-12, er1 - mov.l #0xa5:8, @(12:2, er1) ; Imm8, reg plus 2-bit disp. operand -;;; .word 0x010d -;;; .word 0x31a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-12, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext6 - fail -.Lnext6: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @(dd:16, erd) - mov.l #long_dst-4, er1 - mov.l #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x010d -;;; .word 0x6f90 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext7 - fail -.Lnext7: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @(dd:32, erd) - mov.l #long_dst-8, er1 - mov.l #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x010d -;;; .word 0xc9a5 -;;; .long 8 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext8 - fail -.Lnext8: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @aa:16 - mov.l #0xa5:8, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x010d -;;; .word 0x40a5 -;;; .word @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext9 - fail -.Lnext9: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm8_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:8, @aa:32 - mov.l #0xa5:8, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x010d -;;; .word 0x48a5 -;;; .long @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xa5, @long_dst - beq .Lnext10 - fail -.Lnext10: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @erd - mov.l #long_dst, er1 - mov.l #0xdead:16, @er1 ; Register indirect operand -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0x0100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext11 - fail -.Lnext11: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_postinc: ; post-increment from imm16 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @erd+ - mov.l #long_dst, er1 - mov.l #0xdead:16, @er1+ ; Imm16, register post-incr operands. -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0x8100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext12 - fail -.Lnext12: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_postdec: ; post-decrement from imm16 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @erd- - mov.l #long_dst, er1 - mov.l #0xdead:16, @er1- ; Imm16, register post-decr operands. -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0xa100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext13 - fail -.Lnext13: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @+erd - mov.l #long_dst-4, er1 - mov.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0x9100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext14 - fail -.Lnext14: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @-erd - mov.l #long_dst+4, er1 - mov.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0xb100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext15 - fail -.Lnext15: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @(dd:2, erd) - mov.l #long_dst-12, er1 - mov.l #0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0x3100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-12, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext16 - fail -.Lnext16: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @(dd:16, erd) - mov.l #long_dst-4, er1 - mov.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0xc100 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext17 - fail -.Lnext17: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @(dd:32, erd) - mov.l #long_dst-8, er1 - mov.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0xc900 -;;; .long 8 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext18 - fail -.Lnext18: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @aa:16 - mov.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0x4000 -;;; .word @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext19 - fail -.Lnext19: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm16_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:16, @aa:32 - mov.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x7a7c -;;; .word 0xdead -;;; .word 0x4800 -;;; .long @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xdead, @long_dst - beq .Lnext20 - fail -.Lnext20: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @erd - mov.l #long_dst, er1 - mov.l #0xcafedead:32, @er1 ; Register indirect operand -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0x0100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext21 - fail -.Lnext21: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_postinc: ; post-increment from imm32 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @erd+ - mov.l #long_dst, er1 - mov.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands. -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0x8100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext22 - fail -.Lnext22: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_postdec: ; post-decrement from imm32 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @erd- - mov.l #long_dst, er1 - mov.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands. -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0xa100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext23 - fail -.Lnext23: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @+erd - mov.l #long_dst-4, er1 - mov.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0x9100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext24 - fail -.Lnext24: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @-erd - mov.l #long_dst+4, er1 - mov.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0xb100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext25 - fail -.Lnext25: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @(dd:2, erd) - mov.l #long_dst-12, er1 - mov.l #0xcafedead:32, @(12:2, er1) ; Imm32, reg plus 2-bit disp. operand -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0x3100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-12, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext26 - fail -.Lnext26: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @(dd:16, erd) - mov.l #long_dst-4, er1 - mov.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0xc100 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext27 - fail -.Lnext27: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @(dd:32, erd) - mov.l #long_dst-8, er1 - mov.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0xc900 -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext28 - fail -.Lnext28: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @aa:16 - mov.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0x4000 -;;; .word @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext29 - fail -.Lnext29: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_imm32_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l #xx:32, @aa:32 - mov.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x7a74 -;;; .long 0xcafedead -;;; .word 0x4800 -;;; .long @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l #0xcafedead, @long_dst - beq .Lnext30 - fail -.Lnext30: - mov.l #0, @long_dst ; zero it again for the next use. - -.endif - - ;; - ;; Move long from register source - ;; - -mov_l_reg32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, erd - mov.l #0x12345678, er1 - mov.l er1, er0 ; Register 32-bit operand -;;; .word 0x0f90 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - test_h_gr32 0x12345678 er0 - test_h_gr32 0x12345678 er1 ; mov src unchanged - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_reg32_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @erd - mov.l #long_dst, er1 - mov.l er0, @er1 ; Register indirect operand -;;; .word 0x0100 -;;; .word 0x6990 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.l #0, er0 - mov.l @long_dst, er0 - cmp.l er2, er0 - beq .Lnext44 - fail -.Lnext44: - mov.l #0, er0 - mov.l er0, @long_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_l_reg32_to_postinc: ; post-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @erd+ - mov.l #long_dst, er1 - mov.l er0, @er1+ ; Register post-incr operand -;;; .word 0x0103 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst+4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l er2, @long_dst - beq .Lnext49 - fail -.Lnext49: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_reg32_to_postdec: ; post-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @erd- - mov.l #long_dst, er1 - mov.l er0, @er1- ; Register post-decr operand -;;; .word 0x0101 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l er2, @long_dst - beq .Lnext50 - fail -.Lnext50: - mov.l #0, @long_dst ; zero it again for the next use. - -mov_l_reg32_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @+erd - mov.l #long_dst-4, er1 - mov.l er0, @+er1 ; Register pre-incr operand -;;; .word 0x0102 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l er2, @long_dst - beq .Lnext51 - fail -.Lnext51: - mov.l #0, @long_dst ; zero it again for the next use. -.endif ; h8sx - -mov_l_reg32_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @-erd - mov.l #long_dst+4, er1 - mov.l er0, @-er1 ; Register pre-decr operand -;;; .word 0x0100 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.l #0, er0 - mov.l @long_dst, er0 - cmp.l er2, er0 - beq .Lnext48 - fail -.Lnext48: - mov.l #0, er0 - mov.l er0, @long_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_l_reg32_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @(dd:2, erd) - mov.l #long_dst-12, er1 - mov.l er0, @(12:2, er1) ; Register plus 2-bit disp. operand -;;; .word 0x0103 -;;; .word 0x6990 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 long_dst-12, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l er2, @long_dst - beq .Lnext52 - fail -.Lnext52: - mov.l #0, @long_dst ; zero it again for the next use. -.endif ; h8sx - -mov_l_reg32_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @(dd:16, erd) - mov.l #long_dst-4, er1 - mov.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x0100 -;;; .word 0x6f90 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 long_dst-4, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.l #0, er0 - mov.l @long_dst, er0 - cmp.l er2, er0 - beq .Lnext45 - fail -.Lnext45: - mov.l #0, er0 - mov.l er0, @long_dst ; zero it again for the next use. - -mov_l_reg32_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @(dd:32, erd) - mov.l #long_dst-8, er1 - mov.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x7890 -;;; .word 0x6ba0 -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 long_dst-8, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.l #0, er0 - mov.l @long_dst, er0 - cmp.l er2, er0 - beq .Lnext46 - fail -.Lnext46: - mov.l #0, er0 - mov.l er0, @long_dst ; zero it again for the next use. - -mov_l_reg32_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @aa:16 - mov.l er0, @long_dst:16 ; 16-bit address-direct operand -;;; .word 0x0100 -;;; .word 0x6b80 -;;; .word @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.l #0, er0 - mov.l @long_dst, er0 - cmp.l er0, er1 - beq .Lnext41 - fail -.Lnext41: - mov.l #0, er0 - mov.l er0, @long_dst ; zero it again for the next use. - -mov_l_reg32_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l ers, @aa:32 - mov.l er0, @long_dst:32 ; 32-bit address-direct operand -;;; .word 0x0100 -;;; .word 0x6ba0 -;;; .long @long_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.l #0, er0 - mov.l @long_dst, er0 - cmp.l er0, er1 - beq .Lnext42 - fail -.Lnext42: - mov.l #0, er0 - mov.l er0, @long_dst ; zero it again for the next use. - - ;; - ;; Move long to register destination. - ;; - -mov_l_indirect_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @ers, erd - mov.l #long_src, er1 - mov.l @er1, er0 ; Register indirect operand -;;; .word 0x0100 -;;; .word 0x6910 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_h_gr32 long_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_postinc_to_reg32: ; post-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @ers+, erd - - mov.l #long_src, er1 - mov.l @er1+, er0 ; Register post-incr operand -;;; .word 0x0100 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_h_gr32 long_src+4, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mov_l_postdec_to_reg32: ; post-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @ers-, erd - - mov.l #long_src, er1 - mov.l @er1-, er0 ; Register post-decr operand -;;; .word 0x0102 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_h_gr32 long_src-4, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_preinc_to_reg32: ; pre-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @+ers, erd - - mov.l #long_src-4, er1 - mov.l @+er1, er0 ; Register pre-incr operand -;;; .word 0x0101 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_h_gr32 long_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_predec_to_reg32: ; pre-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @-ers, erd - - mov.l #long_src+4, er1 - mov.l @-er1, er0 ; Register pre-decr operand -;;; .word 0x0103 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_h_gr32 long_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -mov_l_disp2_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @(dd:2, ers), erd - mov.l #long_src-4, er1 - mov.l @(4:2, er1), er0 ; Register plus 2-bit disp. operand -;;; .word 0x0101 -;;; .word 0x6910 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 long_src-4, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx - -mov_l_disp16_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @(dd:16, ers), erd - mov.l #long_src+0x1234, er1 - mov.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand -;;; .word 0x0100 -;;; .word 0x6f10 -;;; .word -0x1234 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 long_src+0x1234, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_disp32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @(dd:32, ers), erd - mov.l #long_src+65536, er1 - mov.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand -;;; .word 0x7890 -;;; .word 0x6b20 -;;; .long -65536 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 long_src+65536, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_abs16_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @aa:16, erd - mov.l @long_src:16, er0 ; 16-bit address-direct operand -;;; .word 0x0100 -;;; .word 0x6b00 -;;; .word @long_src - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_l_abs32_to_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @aa:32, erd - mov.l @long_src:32, er0 ; 32-bit address-direct operand -;;; .word 0x0100 -;;; .word 0x6b20 -;;; .long @long_src - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0x77777777 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -.if (sim_cpu == h8sx) - - ;; - ;; Move long from memory to memory - ;; - -mov_l_indirect_to_indirect: ; reg indirect, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @ers, @erd - - mov.l #long_src, er1 - mov.l #long_dst, er0 - mov.l @er1, @er0 -;;; .word 0x0108 -;;; .word 0x0100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst er0 - test_h_gr32 long_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext55 - fail -.Lnext55: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext56 - fail -.Lnext56: ; OK, pass on. - -mov_l_postinc_to_postinc: ; reg post-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @ers+, @erd+ - - mov.l #long_src, er1 - mov.l #long_dst, er0 - mov.l @er1+, @er0+ -;;; .word 0x0108 -;;; .word 0x8180 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst+4 er0 - test_h_gr32 long_src+4 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext65 - fail -.Lnext65: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext66 - fail -.Lnext66: ; OK, pass on. - -mov_l_postdec_to_postdec: ; reg post-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @ers-, @erd- - - mov.l #long_src, er1 - mov.l #long_dst, er0 - mov.l @er1-, @er0- -;;; .word 0x0108 -;;; .word 0xa1a0 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-4 er0 - test_h_gr32 long_src-4 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext75 - fail -.Lnext75: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext76 - fail -.Lnext76: ; OK, pass on. - -mov_l_preinc_to_preinc: ; reg pre-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @+ers, @+erd - - mov.l #long_src-4, er1 - mov.l #long_dst-4, er0 - mov.l @+er1, @+er0 -;;; .word 0x0108 -;;; .word 0x9190 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst er0 - test_h_gr32 long_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext85 - fail -.Lnext85: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext86 - fail -.Lnext86: ; OK, pass on. - -mov_l_predec_to_predec: ; reg pre-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @-ers, @-erd - - mov.l #long_src+4, er1 - mov.l #long_dst+4, er0 - mov.l @-er1, @-er0 -;;; .word 0x0108 -;;; .word 0xb1b0 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst er0 - test_h_gr32 long_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext95 - fail -.Lnext95: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext96 - fail -.Lnext96: ; OK, pass on. - -mov_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @(dd:2, ers), @(dd:2, erd) - - mov.l #long_src-4, er1 - mov.l #long_dst-8, er0 - mov.l @(4:2, er1), @(8:2, er0) -;;; .word 0x0108 -;;; .word 0x1120 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-8 er0 - test_h_gr32 long_src-4 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext105 - fail -.Lnext105: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext106 - fail -.Lnext106: ; OK, pass on. - -mov_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @(dd:16, ers), @(dd:16, erd) - - mov.l #long_src-1, er1 - mov.l #long_dst-2, er0 - mov.l @(1:16, er1), @(2:16, er0) -;;; .word 0x0108 -;;; .word 0xc1c0 -;;; .word 0x0001 -;;; .word 0x0002 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-2 er0 - test_h_gr32 long_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext115 - fail -.Lnext115: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext116 - fail -.Lnext116: ; OK, pass on. - -mov_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @(dd:32, ers), @(dd:32, erd) - - mov.l #long_src-1, er1 - mov.l #long_dst-2, er0 - mov.l @(1:32, er1), @(2:32, er0) -;;; .word 0x0108 -;;; .word 0xc9c8 -;;; .long 1 -;;; .long 2 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 long_dst-2 er0 - test_h_gr32 long_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext125 - fail -.Lnext125: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext126 - fail -.Lnext126: ; OK, pass on. - -mov_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @aa:16, @aa:16 - - mov.l @long_src:16, @long_dst:16 -;;; .word 0x0108 -;;; .word 0x4040 -;;; .word @long_src -;;; .word @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext135 - fail -.Lnext135: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext136 - fail -.Lnext136: ; OK, pass on. - -mov_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.l @aa:32, @aa:32 - - mov.l @long_src:32, @long_dst:32 -;;; .word 0x0108 -;;; .word 0x4848 -;;; .long @long_src -;;; .long @long_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.l @long_src, @long_dst - beq .Lnext145 - fail -.Lnext145: - ;; Now clear the destination location, and verify that. - mov.l #0, @long_dst - cmp.l @long_src, @long_dst - bne .Lnext146 - fail -.Lnext146: ; OK, pass on. - - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/movmd.s b/sim/testsuite/sim/h8300/movmd.s deleted file mode 100644 index fefdc33..0000000 --- a/sim/testsuite/sim/h8300/movmd.s +++ /dev/null @@ -1,129 +0,0 @@ -# Hitachi H8 testcase 'movmd' -# mach(): h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -byte_src: - .byte 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -byte_dst: - .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - - .align 2 -word_src: - .word 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -word_dst: - .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - - .align 4 -long_src: - .long 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -long_dst: - .long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - - start -.if (sim_cpu == h8sx) -movmd_b:# - # Byte block transfer - # - set_grs_a5a5 - - mov #byte_src, er5 - mov #byte_dst, er6 - mov #10, r4 - set_ccr_zero - ;; movmd.b - movmd.b -;;; .word 0x7b94 - - test_cc_clear - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 0xa5a50000 er4 - test_h_gr32 byte_src+10 er5 - test_h_gr32 byte_dst+10 er6 - test_gr_a5a5 7 - - # - # Now make sure exactly 10 bytes were transferred. - memcmp byte_src byte_dst 10 - cmp.b #0, @byte_dst+10 - beq .L0 - fail -.L0: - -movmd_w:# - # Word block transfer - # - set_grs_a5a5 - - mov #word_src, er5 - mov #word_dst, er6 - mov #10, r4 - set_ccr_zero - ;; movmd.w - movmd.w -;;; .word 0x7ba4 - - test_cc_clear - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 0xa5a50000 er4 - test_h_gr32 word_src+20 er5 - test_h_gr32 word_dst+20 er6 - test_gr_a5a5 7 - - # - # Now make sure exactly 20 bytes were transferred. - memcmp word_src word_dst 20 - cmp.w #0, @word_dst+20 - beq .L1 - fail -.L1: - -movmd_l:# - # Long block transfer - # - set_grs_a5a5 - - mov #long_src, er5 - mov #long_dst, er6 - mov #10, r4 - set_ccr_zero - ;; movmd.b - movmd.l -;;; .word 0x7bb4 - - test_cc_clear - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 0xa5a50000 er4 - test_h_gr32 long_src+40 er5 - test_h_gr32 long_dst+40 er6 - test_gr_a5a5 7 - - # - # Now make sure exactly 40 bytes were transferred. - memcmp long_src long_dst 40 - cmp.l #0, @long_dst+40 - beq .L2 - fail -.L2: - -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/movsd.s b/sim/testsuite/sim/h8300/movsd.s deleted file mode 100644 index 2689c53..0000000 --- a/sim/testsuite/sim/h8300/movsd.s +++ /dev/null @@ -1,100 +0,0 @@ -# Hitachi H8 testcase 'movsd' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -src: .byte 'h', 'e', 'l', 'l', 'o', 0 -dst1: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -dst2: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - - start -.if (sim_cpu == h8sx) -movsd_n:# - # In this test, the transfer will stop after n bytes. - # - set_grs_a5a5 - - mov #src, er5 - mov #dst1, er6 - mov #4, r4 - set_ccr_zero - ;; movsd.b disp:16 - movsd.b fail1:16 -;;; .word 0x7b84 -;;; .word 0x02 - - bra pass1 -fail1: fail -pass1: test_cc_clear - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 0xa5a50000 er4 - test_h_gr32 src+4 er5 - test_h_gr32 dst1+4 er6 - test_gr_a5a5 7 - - # - # Now make sure exactly 4 bytes were transferred. - cmp.b @src, @dst1 - bne fail1:16 - cmp.b @src+1, @dst1+1 - bne fail1:16 - cmp.b @src+2, @dst1+2 - bne fail1:16 - cmp.b @src+3, @dst1+3 - bne fail1:16 - cmp.b @src+4, @dst1+4 - beq fail1:16 - -movsd_s:# - # In this test, the entire null-terminated string is transferred. - # - set_grs_a5a5 - - mov #src, er5 - mov #dst2, er6 - mov #8, r4 - set_ccr_zero - ;; movsd.b disp:16 - movsd.b pass2:16 -;;; .word 0x7b84 -;;; .word 0x10 - -fail2: fail -pass2: test_cc_clear - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 0xa5a50002 er4 - test_h_gr32 src+6 er5 - test_h_gr32 dst2+6 er6 - test_gr_a5a5 7 - # - # Now make sure 5 bytes were transferred, and the 6th is zero. - cmp.b @src, @dst2 - bne fail2:16 - cmp.b @src+1, @dst2+1 - bne fail2:16 - cmp.b @src+2, @dst2+2 - bne fail2:16 - cmp.b @src+3, @dst2+3 - bne fail2:16 - cmp.b @src+4, @dst2+4 - bne fail2:16 - cmp.b #0, @dst2+5 - bne fail2:16 -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/movw.s b/sim/testsuite/sim/h8300/movw.s deleted file mode 100644 index b8b09ea..0000000 --- a/sim/testsuite/sim/h8300/movw.s +++ /dev/null @@ -1,1857 +0,0 @@ -# Hitachi H8 testcase 'mov.w' -# mach(): h8300h h8300s h8sx -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data - .align 2 -word_src: - .word 0x7777 -word_dst: - .word 0 - - .text - - ;; - ;; Move word from immediate source - ;; - -.if (sim_cpu == h8sx) -mov_w_imm3_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:3, rd - mov.w #0x3:3, r0 ; Immediate 3-bit operand -;;; .word 0x0f30 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a50003 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -mov_w_imm16_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, rd - mov.w #0x1234, r0 ; Immediate 16-bit operand -;;; .word 0x7900 -;;; .word 0x1234 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a51234 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mov_w_imm4_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:4, @aa:16 - mov.w #0xf:4, @word_dst:16 ; 4-bit imm to 16-bit address-direct -;;; .word 0x6bdf -;;; .word @word_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xf, @word_dst - beq .Lnext21 - fail -.Lnext21: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm4_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:4, @aa:32 - mov.w #0xf:4, @word_dst:32 ; 4-bit imm to 32-bit address-direct -;;; .word 0x6bff -;;; .long @word_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xf, @word_dst - beq .Lnext22 - fail -.Lnext22: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @erd - mov.l #word_dst, er1 - mov.w #0xa5:8, @er1 ; Register indirect operand -;;; .word 0x015d -;;; .word 0x01a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext1 - fail -.Lnext1: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_postinc: ; post-increment from imm8 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @erd+ - mov.l #word_dst, er1 - mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands. -;;; .word 0x015d -;;; .word 0x81a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst+2, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext2 - fail -.Lnext2: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_postdec: ; post-decrement from imm8 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @erd- - mov.l #word_dst, er1 - mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands. -;;; .word 0x015d -;;; .word 0xa1a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-2, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext3 - fail -.Lnext3: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @+erd - mov.l #word_dst-2, er1 - mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands -;;; .word 0x015d -;;; .word 0x91a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext4 - fail -.Lnext4: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @-erd - mov.l #word_dst+2, er1 - mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands -;;; .word 0x015d -;;; .word 0xb1a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext5 - fail -.Lnext5: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @(dd:2, erd) - mov.l #word_dst-6, er1 - mov.w #0xa5:8, @(6:2, er1) ; Imm8, reg plus 2-bit disp. operand -;;; .word 0x015d -;;; .word 0x31a5 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-6, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext6 - fail -.Lnext6: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @(dd:16, erd) - mov.l #word_dst-4, er1 - mov.w #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x015d -;;; .word 0x6f90 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext7 - fail -.Lnext7: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @(dd:32, erd) - mov.l #word_dst-8, er1 - mov.w #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x015d -;;; .word 0xc9a5 -;;; .long 8 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext8 - fail -.Lnext8: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @aa:16 - mov.w #0xa5:8, @word_dst:16 ; 16-bit address-direct operand -;;; .word 0x015d -;;; .word 0x40a5 -;;; .word @word_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext9 - fail -.Lnext9: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm8_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:8, @aa:32 - mov.w #0xa5:8, @word_dst:32 ; 32-bit address-direct operand -;;; .word 0x015d -;;; .word 0x48a5 -;;; .long @word_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xa5, @word_dst - beq .Lnext10 - fail -.Lnext10: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @erd - mov.l #word_dst, er1 - mov.w #0xdead:16, @er1 ; Register indirect operand -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0x0100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext11 - fail -.Lnext11: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_postinc: ; post-increment from imm16 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @erd+ - mov.l #word_dst, er1 - mov.w #0xdead:16, @er1+ ; Imm16, register post-incr operands. -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0x8100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst+2, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext12 - fail -.Lnext12: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_postdec: ; post-decrement from imm16 to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @erd- - mov.l #word_dst, er1 - mov.w #0xdead:16, @er1- ; Imm16, register post-decr operands. -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0xa100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-2, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext13 - fail -.Lnext13: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @+erd - mov.l #word_dst-2, er1 - mov.w #0xdead:16, @+er1 ; Imm16, register pre-incr operands -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0x9100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext14 - fail -.Lnext14: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @-erd - mov.l #word_dst+2, er1 - mov.w #0xdead:16, @-er1 ; Imm16, register pre-decr operands -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0xb100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext15 - fail -.Lnext15: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @(dd:2, erd) - mov.l #word_dst-6, er1 - mov.w #0xdead:16, @(6:2, er1) ; Imm16, reg plus 2-bit disp. operand -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0x3100 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-6, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext16 - fail -.Lnext16: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @(dd:16, erd) - mov.l #word_dst-4, er1 - mov.w #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0xc100 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-4, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext17 - fail -.Lnext17: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @(dd:32, erd) - mov.l #word_dst-8, er1 - mov.w #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0xc900 -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-8, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext18 - fail -.Lnext18: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @aa:16 - mov.w #0xdead:16, @word_dst:16 ; 16-bit address-direct operand -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0x4000 -;;; .word @word_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext19 - fail -.Lnext19: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_imm16_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w #xx:16, @aa:32 - mov.w #0xdead:16, @word_dst:32 ; 32-bit address-direct operand -;;; .word 0x7974 -;;; .word 0xdead -;;; .word 0x4800 -;;; .long @word_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w #0xdead, @word_dst - beq .Lnext20 - fail -.Lnext20: - mov.w #0, @word_dst ; zero it again for the next use. -.endif - - ;; - ;; Move word from register source - ;; - -mov_w_reg16_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, erd - mov.w #0x1234, r1 - mov.w r1, r0 ; Register 16-bit operand -;;; .word 0x0d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - test_h_gr16 0x1234 r0 - test_h_gr16 0x1234 r1 ; mov src unchanged -.if (sim_cpu) - test_h_gr32 0xa5a51234 er0 - test_h_gr32 0xa5a51234 er1 ; mov src unchanged -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -mov_w_reg16_to_indirect: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @erd - mov.l #word_dst, er1 - mov.w r0, @er1 ; Register indirect operand -;;; .word 0x6990 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.w #0, r0 - mov.w @word_dst, r0 - cmp.w r2, r0 - beq .Lnext44 - fail -.Lnext44: - mov.w #0, r0 - mov.w r0, @word_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_w_reg16_to_postinc: ; post-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @erd+ - mov.l #word_dst, er1 - mov.w r0, @er1+ ; Register post-incr operand -;;; .word 0x0153 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst+2, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w r2, @word_dst - beq .Lnext49 - fail -.Lnext49: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_reg16_to_postdec: ; post-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @erd- - mov.l #word_dst, er1 - mov.w r0, @er1- ; Register post-decr operand -;;; .word 0x0151 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-2, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w r2, @word_dst - beq .Lnext50 - fail -.Lnext50: - mov.w #0, @word_dst ; zero it again for the next use. - -mov_w_reg16_to_preinc: ; pre-increment from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @+erd - mov.l #word_dst-2, er1 - mov.w r0, @+er1 ; Register pre-incr operand -;;; .word 0x0152 -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w r2, @word_dst - beq .Lnext51 - fail -.Lnext51: - mov.w #0, @word_dst ; zero it again for the next use. -.endif - -mov_w_reg16_to_predec: ; pre-decrement from register to mem - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @-erd - mov.l #word_dst+2, er1 - mov.w r0, @-er1 ; Register pre-decr operand -;;; .word 0x6d90 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.w #0, r0 - mov.w @word_dst, r0 - cmp.w r2, r0 - beq .Lnext48 - fail -.Lnext48: - mov.w #0, r0 - mov.w r0, @word_dst ; zero it again for the next use. - -.if (sim_cpu == h8sx) -mov_w_reg16_to_disp2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @(dd:2, erd) - mov.l #word_dst-6, er1 - mov.w r0, @(6:2, er1) ; Register plus 2-bit disp. operand -;;; .word 0x0153 -;;; .word 0x6990 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_h_gr32 word_dst-6, er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w r2, @word_dst - beq .Lnext52 - fail -.Lnext52: - mov.w #0, @word_dst ; zero it again for the next use. -.endif - -mov_w_reg16_to_disp16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @(dd:16, erd) - mov.l #word_dst-4, er1 - mov.w r0, @(4:16, er1) ; Register plus 16-bit disp. operand -;;; .word 0x6f90 -;;; .word 0x0004 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 word_dst-4, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.w #0, r0 - mov.w @word_dst, r0 - cmp.w r2, r0 - beq .Lnext45 - fail -.Lnext45: - mov.w #0, r0 - mov.w r0, @word_dst ; zero it again for the next use. - -mov_w_reg16_to_disp32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @(dd:32, erd) - mov.l #word_dst-8, er1 - mov.w r0, @(8:32, er1) ; Register plus 32-bit disp. operand -;;; .word 0x7810 -;;; .word 0x6ba0 -;;; .long 8 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 word_dst-8, er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.w #0, r0 - mov.w @word_dst, r0 - cmp.w r2, r0 - beq .Lnext46 - fail -.Lnext46: - mov.w #0, r0 - mov.w r0, @word_dst ; zero it again for the next use. - -mov_w_reg16_to_abs16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @aa:16 - mov.w r0, @word_dst:16 ; 16-bit address-direct operand -;;; .word 0x6b80 -;;; .word @word_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.w #0, r0 - mov.w @word_dst, r0 - cmp.w r0, r1 - beq .Lnext41 - fail -.Lnext41: - mov.w #0, r0 - mov.w r0, @word_dst ; zero it again for the next use. - -mov_w_reg16_to_abs32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w ers, @aa:32 - mov.w r0, @word_dst:32 ; 32-bit address-direct operand -;;; .word 0x6ba0 -;;; .long @word_dst - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed - test_gr_a5a5 1 ; (first, because on h8/300 we must use one - test_gr_a5a5 2 ; to examine the destination memory). - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - mov.w #0, r0 - mov.w @word_dst, r0 - cmp.w r0, r1 - beq .Lnext42 - fail -.Lnext42: - mov.w #0, r0 - mov.w r0, @word_dst ; zero it again for the next use. - - ;; - ;; Move word to register destination. - ;; - -mov_w_indirect_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @ers, rd - mov.l #word_src, er1 - mov.w @er1, r0 ; Register indirect operand -;;; .word 0x6910 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_h_gr32 word_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_w_postinc_to_reg16: ; post-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @ers+, rd - - mov.l #word_src, er1 - mov.w @er1+, r0 ; Register post-incr operand -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_h_gr32 word_src+2, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mov_w_postdec_to_reg16: ; post-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @ers-, rd - - mov.l #word_src, er1 - mov.w @er1-, r0 ; Register post-decr operand -;;; .word 0x0152 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_h_gr32 word_src-2, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_w_preinc_to_reg16: ; pre-increment from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @+ers, rd - - mov.l #word_src-2, er1 - mov.w @+er1, r0 ; Register pre-incr operand -;;; .word 0x0151 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_h_gr32 word_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_w_predec_to_reg16: ; pre-decrement from mem to register - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @-ers, rd - - mov.l #word_src+2, er1 - mov.w @-er1, r0 ; Register pre-decr operand -;;; .word 0x0153 -;;; .word 0x6d10 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_h_gr32 word_src, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - -mov_w_disp2_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @(dd:2, ers), rd - mov.l #word_src-2, er1 - mov.w @(2:2, er1), r0 ; Register plus 2-bit disp. operand -;;; .word 0x0151 -;;; .word 0x6910 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 word_src-2, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -mov_w_disp16_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @(dd:16, ers), rd - mov.l #word_src+0x1234, er1 - mov.w @(-0x1234:16, er1), r0 ; Register plus 16-bit disp. operand -;;; .word 0x6f10 -;;; .word -0x1234 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 word_src+0x1234, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_w_disp32_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @(dd:32, ers), rd - mov.l #word_src+65536, er1 - mov.w @(-65536:32, er1), r0 ; Register plus 32-bit disp. operand -;;; .word 0x7810 -;;; .word 0x6b20 -;;; .long -65536 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 - - test_h_gr32 word_src+65536, er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_w_abs16_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @aa:16, rd - mov.w @word_src:16, r0 ; 16-bit address-direct operand -;;; .word 0x6b00 -;;; .word @word_src - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mov_w_abs32_to_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @aa:32, rd - mov.w @word_src:32, r0 ; 32-bit address-direct operand -;;; .word 0x6b20 -;;; .long @word_src - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_h_gr32 0xa5a57777 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) - - ;; - ;; Move word from memory to memory - ;; - -mov_w_indirect_to_indirect: ; reg indirect, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @ers, @erd - - mov.l #word_src, er1 - mov.l #word_dst, er0 - mov.w @er1, @er0 -;;; .word 0x0158 -;;; .word 0x0100 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst er0 - test_h_gr32 word_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext55 - fail -.Lnext55: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext56 - fail -.Lnext56: ; OK, pass on. - -mov_w_postinc_to_postinc: ; reg post-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @ers+, @erd+ - - mov.l #word_src, er1 - mov.l #word_dst, er0 - mov.w @er1+, @er0+ -;;; .word 0x0158 -;;; .word 0x8180 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst+2 er0 - test_h_gr32 word_src+2 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext65 - fail -.Lnext65: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext66 - fail -.Lnext66: ; OK, pass on. - -mov_w_postdec_to_postdec: ; reg post-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @ers-, @erd- - - mov.l #word_src, er1 - mov.l #word_dst, er0 - mov.w @er1-, @er0- -;;; .word 0x0158 -;;; .word 0xa1a0 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst-2 er0 - test_h_gr32 word_src-2 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext75 - fail -.Lnext75: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext76 - fail -.Lnext76: ; OK, pass on. - -mov_w_preinc_to_preinc: ; reg pre-increment, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @+ers, @+erd - - mov.l #word_src-2, er1 - mov.l #word_dst-2, er0 - mov.w @+er1, @+er0 -;;; .word 0x0158 -;;; .word 0x9190 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst er0 - test_h_gr32 word_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext85 - fail -.Lnext85: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext86 - fail -.Lnext86: ; OK, pass on. - -mov_w_predec_to_predec: ; reg pre-decrement, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @-ers, @-erd - - mov.l #word_src+2, er1 - mov.l #word_dst+2, er0 - mov.w @-er1, @-er0 -;;; .word 0x0158 -;;; .word 0xb1b0 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst er0 - test_h_gr32 word_src er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext95 - fail -.Lnext95: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext96 - fail -.Lnext96: ; OK, pass on. - -mov_w_disp2_to_disp2: ; reg 2-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @(dd:2, ers), @(dd:2, erd) - - mov.l #word_src-2, er1 - mov.l #word_dst-4, er0 - mov.w @(2:2, er1), @(4:2, er0) -;;; .word 0x0158 -;;; .word 0x1120 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst-4 er0 - test_h_gr32 word_src-2 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext105 - fail -.Lnext105: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext106 - fail -.Lnext106: ; OK, pass on. - -mov_w_disp16_to_disp16: ; reg 16-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @(dd:16, ers), @(dd:16, erd) - - mov.l #word_src-1, er1 - mov.l #word_dst-2, er0 - mov.w @(1:16, er1), @(2:16, er0) -;;; .word 0x0158 -;;; .word 0xc1c0 -;;; .word 0x0001 -;;; .word 0x0002 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst-2 er0 - test_h_gr32 word_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext115 - fail -.Lnext115: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext116 - fail -.Lnext116: ; OK, pass on. - -mov_w_disp32_to_disp32: ; reg 32-bit disp, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @(dd:32, ers), @(dd:32, erd) - - mov.l #word_src-1, er1 - mov.l #word_dst-2, er0 - mov.w @(1:32, er1), @(2:32, er0) -;;; .word 0x0158 -;;; .word 0xc9c8 -;;; .long 1 -;;; .long 2 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - ;; Verify the affected registers. - - test_h_gr32 word_dst-2 er0 - test_h_gr32 word_src-1 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext125 - fail -.Lnext125: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext126 - fail -.Lnext126: ; OK, pass on. - -mov_w_abs16_to_abs16: ; 16-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @aa:16, @aa:16 - - mov.w @word_src:16, @word_dst:16 -;;; .word 0x0158 -;;; .word 0x4040 -;;; .word @word_src -;;; .word @word_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext135 - fail -.Lnext135: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext136 - fail -.Lnext136: ; OK, pass on. - -mov_w_abs32_to_abs32: ; 32-bit absolute addr, memory to memory - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; mov.w @aa:32, @aa:32 - - mov.w @word_src:32, @word_dst:32 -;;; .word 0x0158 -;;; .word 0x4848 -;;; .long @word_src -;;; .long @word_dst - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_neg_clear - test_zero_clear - test_ovf_clear - test_carry_clear - - test_gr_a5a5 0 ; Make sure *NO* general registers are changed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the move to memory. - cmp.w @word_src, @word_dst - beq .Lnext145 - fail -.Lnext145: - ;; Now clear the destination location, and verify that. - mov.w #0, @word_dst - cmp.w @word_src, @word_dst - bne .Lnext146 - fail -.Lnext146: ; OK, pass on. - - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/mul.s b/sim/testsuite/sim/h8300/mul.s deleted file mode 100644 index 02b9e9f..0000000 --- a/sim/testsuite/sim/h8300/mul.s +++ /dev/null @@ -1,474 +0,0 @@ -# Hitachi H8 testcase 'muls', 'muls/u', mulu', 'mulu/u', 'mulxs', 'mulxu' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) -muls_w_reg_reg: - set_grs_a5a5 - - ;; muls.w rs, rd - mov.w #32, r1 - mov.w #-2, r2 - set_ccr_zero - muls.w r2, r1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr16 -64 r1 - test_h_gr32 0xa5a5fffe er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -muls_w_imm4_reg: - set_grs_a5a5 - - ;; muls.w xx:4, rd - mov.w #-32, r1 - set_ccr_zero - muls.w #2:4, r1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr16 -64 r1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -muls_l_reg_reg: - set_grs_a5a5 - - ;; muls.l ers, erd - mov.l #320000, er1 - mov.l #-2, er2 - set_ccr_zero - muls.l er2, er1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr32 -640000 er1 - test_h_gr32 -2 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -muls_l_imm4_reg: - set_grs_a5a5 - - ;; muls.l xx:4, rd - mov.l #-320000, er1 - set_ccr_zero - muls.l #2:4, er1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr32 -640000 er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -muls_u_l_reg_reg: - set_grs_a5a5 - - ;; muls/u.l ers, erd - mov.l #0x10000000, er1 - mov.l #-16, er2 - set_ccr_zero - muls/u.l er2, er1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr32 -1 er1 - test_h_gr32 -16 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -muls_u_l_imm4_reg: - set_grs_a5a5 - - ;; muls/u.l xx:4, rd - mov.l #0xffffffff, er1 - set_ccr_zero - muls/u.l #2:4, er1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr32 -1 er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mulu_w_reg_reg: - set_grs_a5a5 - - ;; mulu.w rs, rd - mov.w #32, r1 - mov.w #-2, r2 - set_ccr_zero - mulu.w r2, r1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr16 -64 r1 - test_h_gr32 0xa5a5fffe er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mulu_w_imm4_reg: - set_grs_a5a5 - - ;; mulu.w xx:4, rd - mov.w #32, r1 - set_ccr_zero - mulu.w #-2:4, r1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr16 0x1c0 r1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mulu_l_reg_reg: - set_grs_a5a5 - - ;; mulu.l ers, erd - mov.l #320000, er1 - mov.l #-2, er2 - set_ccr_zero - mulu.l er2, er1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr32 -640000 er1 - test_h_gr32 -2 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mulu_l_imm4_reg: - set_grs_a5a5 - - ;; mulu.l xx:4, rd - mov.l #320000, er1 - set_ccr_zero - mulu.l #-2:4, er1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr32 0x445c00 er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mulu_u_l_reg_reg: - set_grs_a5a5 - - ;; mulu/u.l ers, erd - mov.l #0x10000000, er1 - mov.l #16, er2 - set_ccr_zero - mulu/u.l er2, er1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr32 1 er1 - test_h_gr32 16 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -mulu_u_l_imm4_reg: - set_grs_a5a5 - - ;; mulu/u.l xx:4, rd - mov.l #0xffffffff, er1 - set_ccr_zero - mulu/u.l #2:4, er1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr32 0x1 er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu) ; not equal to zero ie. not h8 -mulxs_b_reg_reg: - set_grs_a5a5 - - ;; mulxs.b rs, rd - mov.b #32, r1l - mov.b #-2, r2l - set_ccr_zero - mulxs.b r2l, r1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr16 -64 r1 - test_h_gr32 0xa5a5a5fe er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mulxs_b_imm4_reg: - set_grs_a5a5 - - ;; mulxs.b xx:4, rd - mov.w #-32, r1 - set_ccr_zero - mulxs.b #2:4, r1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr16 -64 r1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx - -mulxs_w_reg_reg: - set_grs_a5a5 - - ;; mulxs.w ers, erd - mov.w #0x1000, r1 - mov.w #-0x1000, r2 - set_ccr_zero - mulxs.w r2, er1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr32 0xff000000 er1 - test_h_gr32 0xa5a5f000 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mulxs_w_imm4_reg: - set_grs_a5a5 - - ;; mulxs.w xx:4, rd - mov.w #-1, r1 - set_ccr_zero - mulxs.w #2:4, er1 - - ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_h_gr32 -2 er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx -.endif ; not h8 - -mulxu_b_reg_reg: - set_grs_a5a5 - - ;; mulxu.b rs, rd - mov.b #32, r1l - mov.b #-2, r2l - set_ccr_zero - mulxu.b r2l, r1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr16 0x1fc0 r1 - test_h_gr16 0xa5fe r2 -.if (sim_cpu) - test_h_gr32 0xa5a5a5fe er2 -.endif - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; not h8 -.if (sim_cpu == h8sx) -mulxu_b_imm4_reg: - set_grs_a5a5 - - ;; mulxu.b xx:4, rd - mov.b #-32, r1l - set_ccr_zero - mulxu.b #2:4, r1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr16 0x1c0 r1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx - -mulxu_w_reg_reg: - set_grs_a5a5 - - ;; mulxu.w ers, erd - mov.w #0x1000, r1 - mov.w #-0x1000, r2 - set_ccr_zero - mulxu.w r2, er1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr32 0x0f000000 er1 - test_h_gr32 0xa5a5f000 er2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -mulxu_w_imm4_reg: - set_grs_a5a5 - - ;; mulxu.w xx:4, rd - mov.w #-1, r1 - set_ccr_zero - mulxu.w #2:4, er1 - - ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 - test_cc_clear - - test_gr_a5a5 0 - test_h_gr32 0x1fffe er1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; h8sx -.endif ; not h8 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/neg.s b/sim/testsuite/sim/h8300/neg.s deleted file mode 100644 index de82476..0000000 --- a/sim/testsuite/sim/h8300/neg.s +++ /dev/null @@ -1,1022 +0,0 @@ -# Hitachi H8 testcase 'neg.b, neg.w, neg.l' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # neg.b rd ; 1 7 8 rd - # neg.b @erd ; 7 d rd ???? 1 7 8 ignore - # neg.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 8 ignore - # neg.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 8 ignore - # neg.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 8 ignore - # neg.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 8 ignore - # neg.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 8 ignore - # neg.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 8 ignore - # neg.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 8 ignore - # neg.b @aa:16 ; 6 a 1 1??? aa:16 1 7 8 ignore - # neg.b @aa:32 ; 6 a 3 1??? aa:32 1 7 8 ignore - # word operations - # long operations - # - # Coming soon: - # neg.b @aa:8 ; 7 f aaaaaaaa 1 7 8 ignore - # - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - start - - # - # Note: apparently carry is set for neg of anything except zero. - # - - # - # 8-bit byte operations - # - -neg_b_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b Rd - neg r0l ; 8-bit register -;;; .word 0x1788 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5b, r0l ; result of "neg 0xa5" - beq .Lbrd - fail -.Lbrd: - test_h_gr16 0xa55b r0 ; r0 changed by 'neg' -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a55b er0 ; er0 changed by 'neg' -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -neg_b_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @eRd - mov #byte_dest, er0 - neg.b @er0 ; register indirect operand -;;; .word 0x7d00 -;;; .word 0x1780 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - cmp.b #0x5b, @er0 ; memory contents changed - beq .Lbind - fail -.Lbind: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @eRd+ - mov #byte_dest, er0 ; register post-increment operand - neg.b @er0+ -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1780 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one - cmp.b #0xa5, @-er0 - beq .Lbpostinc - fail -.Lbpostinc: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @eRd- - mov #byte_dest, er0 ; register post-decrement operand - neg.b @er0- -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1780 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one - cmp.b #0x5b, @+er0 - beq .Lbpostdec - fail -.Lbpostdec: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @+eRd - mov #byte_dest-1, er0 - neg.b @+er0 ; reg pre-increment operand -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1780 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5, @er0 - beq .Lbpreinc - fail -.Lbpreinc: - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @-eRd - mov #byte_dest+1, er0 - neg.b @-er0 ; reg pre-decr operand -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1780 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5b, @er0 - beq .Lbpredec - fail -.Lbpredec: - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_disp2dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @(dd:2, erd) - mov #byte_dest-1, er0 - neg.b @(1:2, er0) ; reg plus 2-bit displacement -;;; .word 0x0175 -;;; .word 0x6808 -;;; .word 0x1780 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5, @+er0 - beq .Lbdisp2 - fail -.Lbdisp2: - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_disp16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @(dd:16, erd) - mov #byte_dest+100, er0 - neg.b @(-100:16, er0) ; reg plus 16-bit displacement -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word -100 -;;; .word 0x1780 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5b, @byte_dest - beq .Lbdisp16 - fail -.Lbdisp16: - test_h_gr32 byte_dest+100 er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_disp32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @(dd:32, erd) - mov #byte_dest-0xfffff, er0 - neg.b @(0xfffff:32, er0) ; reg plus 32-bit displacement -;;; .word 0x7804 -;;; .word 0x6a28 -;;; .long 0xfffff -;;; .word 0x1780 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5, @byte_dest - beq .Lbdisp32 - fail -.Lbdisp32: - test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_abs16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @aa:16 - neg.b @byte_dest:16 ; 16-bit absolute address -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1780 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5b, @byte_dest - beq .Lbabs16 - fail -.Lbabs16: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_b_abs32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.b @aa:32 - neg.b @byte_dest:32 ; 32-bit absolute address -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1780 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5, @byte_dest - beq .Lbabs32 - fail -.Lbabs32: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - - # - # 16-bit word operations - # - -.if (sim_cpu) ; any except plain-vanilla h8/300 -neg_w_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w Rd - neg r1 ; 16-bit register operand -;;; .word 0x1791 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5b, r1 ; result of "neg 0xa5a5" - beq .Lwrd - fail -.Lwrd: - test_h_gr32 0xa5a55a5b er1 ; er1 changed by 'neg' - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -neg_w_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @eRd - mov #word_dest, er1 - neg.w @er1 ; register indirect operand -;;; .word 0x0154 -;;; .word 0x6d18 -;;; .word 0x1790 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5b, @word_dest ; memory contents changed - beq .Lwind - fail -.Lwind: - test_h_gr32 word_dest er1 ; er1 still contains address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @eRd+ - mov #word_dest, er1 ; register post-increment operand - neg.w @er1+ -;;; .word 0x0154 -;;; .word 0x6d18 -;;; .word 0x1790 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwpostinc - fail -.Lwpostinc: - test_h_gr32 word_dest+2 er1 ; er1 contains address plus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @eRd- - mov #word_dest, er1 - neg.w @er1- -;;; .word 0x0156 -;;; .word 0x6d18 -;;; .word 0x1790 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5b, @word_dest - beq .Lwpostdec - fail -.Lwpostdec: - test_h_gr32 word_dest-2 er1 ; er1 contains address minus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @+eRd - mov #word_dest-2, er1 - neg.w @+er1 ; reg pre-increment operand -;;; .word 0x0155 -;;; .word 0x6d18 -;;; .word 0x1790 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwpreinc - fail -.Lwpreinc: - test_h_gr32 word_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @-eRd - mov #word_dest+2, er1 - neg.w @-er1 ; reg pre-decr operand -;;; .word 0x0157 -;;; .word 0x6d18 -;;; .word 0x1790 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5b, @word_dest - beq .Lwpredec - fail -.Lwpredec: - test_h_gr32 word_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_disp2dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @(dd:2, erd) - mov #word_dest-2, er1 - neg.w @(2:2, er1) ; reg plus 2-bit displacement -;;; .word 0x0155 -;;; .word 0x6918 -;;; .word 0x1790 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwdisp2 - fail -.Lwdisp2: - test_h_gr32 word_dest-2 er1 ; er1 contains address minus one - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_disp16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @(dd:16, erd) - mov #word_dest+100, er1 - neg.w @(-100:16, er1) ; reg plus 16-bit displacement -;;; .word 0x0154 -;;; .word 0x6f18 -;;; .word -100 -;;; .word 0x1790 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5b, @word_dest - beq .Lwdisp16 - fail -.Lwdisp16: - test_h_gr32 word_dest+100 er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_disp32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @(dd:32, erd) - mov #word_dest-0xfffff, er1 - neg.w @(0xfffff:32, er1) ; reg plus 32-bit displacement -;;; .word 0x7814 -;;; .word 0x6b28 -;;; .long 0xfffff -;;; .word 0x1790 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwdisp32 - fail -.Lwdisp32: - test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_abs16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @aa:16 - neg.w @word_dest:16 ; 16-bit absolute address -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1790 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5b, @word_dest - beq .Lwabs16 - fail -.Lwabs16: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_w_abs32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.w @aa:32 - neg.w @word_dest:32 ; 32-bit absolute address -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1790 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwabs32 - fail -.Lwabs32: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif ; h8sx -.endif ; h8/300 - - # - # 32-bit word operations - # - -.if (sim_cpu) ; any except plain-vanilla h8/300 -neg_l_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l eRd - neg er1 ; 32-bit register operand -;;; .word 0x17b1 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5b, er1 ; result of "neg 0xa5a5a5a5" - beq .Llrd - fail -.Llrd: - test_h_gr32 0x5a5a5a5b er1 ; er1 changed by 'neg' - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -neg_l_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @eRd - mov #long_dest, er1 - neg.l @er1 ; register indirect operand -;;; .word 0x0104 -;;; .word 0x6d18 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5b, @long_dest ; memory contents changed - beq .Llind - fail -.Llind: - test_h_gr32 long_dest er1 ; er1 still contains address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @eRd+ - mov #long_dest, er1 ; register post-increment operand - neg.l @er1+ -;;; .word 0x0104 -;;; .word 0x6d18 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Llpostinc - fail -.Llpostinc: - test_h_gr32 long_dest+4 er1 ; er1 contains address plus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @eRd- - mov #long_dest, er1 - neg.l @er1- -;;; .word 0x0106 -;;; .word 0x6d18 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5b, @long_dest - beq .Llpostdec - fail -.Llpostdec: - test_h_gr32 long_dest-4 er1 ; er1 contains address minus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @+eRd - mov #long_dest-4, er1 - neg.l @+er1 ; reg pre-increment operand -;;; .word 0x0105 -;;; .word 0x6d18 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Llpreinc - fail -.Llpreinc: - test_h_gr32 long_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @-eRd - mov #long_dest+4, er1 - neg.l @-er1 ; reg pre-decr operand -;;; .word 0x0107 -;;; .word 0x6d18 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5b, @long_dest - beq .Llpredec - fail -.Llpredec: - test_h_gr32 long_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_disp2dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @(dd:2, erd) - mov #long_dest-4, er1 - neg.l @(4:2, er1) ; reg plus 2-bit displacement -;;; .word 0x0105 -;;; .word 0x6918 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Lldisp2 - fail -.Lldisp2: - test_h_gr32 long_dest-4 er1 ; er1 contains address minus one - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_disp16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @(dd:16, erd) - mov #long_dest+100, er1 - neg.l @(-100:16, er1) ; reg plus 16-bit displacement -;;; .word 0x0104 -;;; .word 0x6f18 -;;; .word -100 -;;; .word 0x17b0 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5b, @long_dest - beq .Lldisp16 - fail -.Lldisp16: - test_h_gr32 long_dest+100 er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_disp32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @(dd:32, erd) - mov #long_dest-0xfffff, er1 - neg.l @(0xfffff:32, er1) ; reg plus 32-bit displacement -;;; .word 0x7894 -;;; .word 0x6b28 -;;; .long 0xfffff -;;; .word 0x17b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Lldisp32 - fail -.Lldisp32: - test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_abs16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @aa:16 - neg.l @long_dest:16 ; 16-bit absolute address -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x17b0 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5b, @long_dest - beq .Llabs16 - fail -.Llabs16: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -neg_l_abs32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; neg.l @aa:32 - neg.l @long_dest:32 ; 32-bit absolute address -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x17b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Llabs32 - fail -.Llabs32: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif ; h8sx -.endif ; h8/300 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/nop.s b/sim/testsuite/sim/h8300/nop.s deleted file mode 100644 index 1d63b67..0000000 --- a/sim/testsuite/sim/h8300/nop.s +++ /dev/null @@ -1,26 +0,0 @@ -# Hitachi H8 testcase 'nop' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -nop: set_grs_a5a5 - set_ccr_zero - - nop - - test_cc_clear - test_grs_a5a5 - - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/not.s b/sim/testsuite/sim/h8300/not.s deleted file mode 100644 index 862c2b2..0000000 --- a/sim/testsuite/sim/h8300/not.s +++ /dev/null @@ -1,1009 +0,0 @@ -# Hitachi H8 testcase 'not.b, not.w, not.l' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # not.b rd ; 1 7 0 rd - # not.b @erd ; 7 d rd ???? 1 7 0 ignore - # not.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 0 ignore - # not.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 0 ignore - # not.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 0 ignore - # not.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 0 ignore - # not.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 0 ignore - # not.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 0 ignore - # not.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 0 ignore - # not.b @aa:16 ; 6 a 1 1??? aa:16 1 7 0 ignore - # not.b @aa:32 ; 6 a 3 1??? aa:32 1 7 0 ignore - # word operations - # long operations - # - # Coming soon: - # not.b @aa:8 ; 7 f aaaaaaaa 1 7 0 ignore - # - -.data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - start - - # - # 8-bit byte operations - # - -not_b_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; not.b Rd - not r0l ; 8-bit register -;;; .word 0x1708 - - cmp.b #0x5a, r0l ; result of "not 0xa5" - beq .Lbrd - fail -.Lbrd: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa55a r0 ; r0 changed by 'not' -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a55a er0 ; er0 changed by 'not' -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -not_b_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @eRd - mov #byte_dest, er0 - not.b @er0 ; register indirect operand -;;; .word 0x7d00 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest er0 ; er0 still contains address - cmp.b #0x5a:8, @er0 ; memory contents changed - beq .Lbind - fail -.Lbind: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @eRd+ - mov #byte_dest, er0 ; register post-increment operand - not.b @er0+ -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one - cmp.b #0xa5:8, @-er0 - beq .Lbpostinc - fail -.Lbpostinc: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @eRd- - mov #byte_dest, er0 ; register post-decrement operand - not.b @er0- -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one - cmp.b #0x5a:8, @+er0 -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0xa05a - beq .Lbpostdec - fail -.Lbpostdec: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @+eRd - mov #byte_dest-1, er0 - not.b @+er0 ; reg pre-increment operand -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5:8, @er0 - beq .Lbpreinc - fail -.Lbpreinc: - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @-eRd - mov #byte_dest+1, er0 - not.b @-er0 ; reg pre-decr operand -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5a:8, @er0 - beq .Lbpredec - fail -.Lbpredec: - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_disp2dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @(dd:2, erd) - mov #byte_dest-1, er0 - not.b @(1:2, er0) ; reg plus 2-bit displacement -;;; .word 0x0175 -;;; .word 0x6808 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5:8, @+er0 - beq .Lbdisp2 - fail -.Lbdisp2: - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_disp16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @(dd:16, erd) - mov #byte_dest+100, er0 - not.b @(-100:16, er0) ; reg plus 16-bit displacement -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word -100 -;;; .word 0x1700 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5a:8, @byte_dest - beq .Lbdisp16 - fail -.Lbdisp16: - test_h_gr32 byte_dest+100 er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_disp32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @(dd:32, erd) - mov #byte_dest-0xfffff, er0 - not.b @(0xfffff:32, er0) ; reg plus 32-bit displacement -;;; .word 0x7804 -;;; .word 0x6a28 -;;; .long 0xfffff -;;; .word 0x1700 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5:8, @byte_dest - beq .Lbdisp32 - fail -.Lbdisp32: - test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_abs16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @aa:16 - not.b @byte_dest:16 ; 16-bit absolute address -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1700 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.b #0x5a:8, @byte_dest - beq .Lbabs16 - fail -.Lbabs16: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_b_abs32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.b @aa:32 - not.b @byte_dest:32 ; 32-bit absolute address -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1700 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.b #0xa5:8, @byte_dest - beq .Lbabs32 - fail -.Lbabs32: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - - # - # 16-bit word operations - # - -.if (sim_cpu) ; any except plain-vanilla h8/300 -not_w_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; not.w Rd - not r1 ; 16-bit register operand -;;; .word 0x1711 - - cmp.w #0x5a5a, r1 ; result of "not 0xa5a5" - beq .Lwrd - fail -.Lwrd: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr32 0xa5a55a5a er1 ; er1 changed by 'not' - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -not_w_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @eRd - mov #word_dest, er1 - not.w @er1 ; register indirect operand -;;; .word 0x0154 -;;; .word 0x6d18 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5a, @word_dest ; memory contents changed - beq .Lwind - fail -.Lwind: - test_h_gr32 word_dest er1 ; er1 still contains address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @eRd+ - mov #word_dest, er1 ; register post-increment operand - not.w @er1+ -;;; .word 0x0154 -;;; .word 0x6d18 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwpostinc - fail -.Lwpostinc: - test_h_gr32 word_dest+2 er1 ; er1 contains address plus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @eRd- - mov #word_dest, er1 - not.w @er1- -;;; .word 0x0156 -;;; .word 0x6d18 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5a, @word_dest - beq .Lwpostdec - fail -.Lwpostdec: - test_h_gr32 word_dest-2 er1 ; er1 contains address minus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @+eRd - mov #word_dest-2, er1 - not.w @+er1 ; reg pre-increment operand -;;; .word 0x0155 -;;; .word 0x6d18 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwpreinc - fail -.Lwpreinc: - test_h_gr32 word_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @-eRd - mov #word_dest+2, er1 - not.w @-er1 ; reg pre-decr operand -;;; .word 0x0157 -;;; .word 0x6d18 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5a, @word_dest - beq .Lwpredec - fail -.Lwpredec: - test_h_gr32 word_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_disp2dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @(dd:2, erd) - mov #word_dest-2, er1 - not.w @(2:2, er1) ; reg plus 2-bit displacement -;;; .word 0x0155 -;;; .word 0x6918 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwdisp2 - fail -.Lwdisp2: - test_h_gr32 word_dest-2 er1 ; er1 contains address minus one - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_disp16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @(dd:16, erd) - mov #word_dest+100, er1 - not.w @(-100:16, er1) ; reg plus 16-bit displacement -;;; .word 0x0154 -;;; .word 0x6f18 -;;; .word -100 -;;; .word 0x1710 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5a, @word_dest - beq .Lwdisp16 - fail -.Lwdisp16: - test_h_gr32 word_dest+100 er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_disp32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @(dd:32, erd) - mov #word_dest-0xfffff, er1 - not.w @(0xfffff:32, er1) ; reg plus 32-bit displacement -;;; .word 0x7814 -;;; .word 0x6b28 -;;; .long 0xfffff -;;; .word 0x1710 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwdisp32 - fail -.Lwdisp32: - test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_abs16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @aa:16 - not.w @word_dest:16 ; 16-bit absolute address -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1710 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.w #0x5a5a, @word_dest - beq .Lwabs16 - fail -.Lwabs16: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_w_abs32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.w @aa:32 - not.w @word_dest:32 ; 32-bit absolute address -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1710 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.w #0xa5a5, @word_dest - beq .Lwabs32 - fail -.Lwabs32: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif ; h8sx -.endif ; h8/300 - - # - # 32-bit word operations - # - -.if (sim_cpu) ; any except plain-vanilla h8/300 -not_l_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; not.l eRd - not er1 ; 32-bit register operand -;;; .word 0x1731 - - cmp.l #0x5a5a5a5a, er1 ; result of "not 0xa5a5a5a5" - beq .Llrd - fail -.Llrd: - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr32 0x5a5a5a5a er1 ; er1 changed by 'not' - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -not_l_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @eRd - mov #long_dest, er1 - not.l @er1 ; register indirect operand -;;; .word 0x0104 -;;; .word 0x6d18 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5a, @long_dest ; memory contents changed - beq .Llind - fail -.Llind: - test_h_gr32 long_dest er1 ; er1 still contains address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @eRd+ - mov #long_dest, er1 ; register post-increment operand - not.l @er1+ -;;; .word 0x0104 -;;; .word 0x6d18 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Llpostinc - fail -.Llpostinc: - test_h_gr32 long_dest+4 er1 ; er1 contains address plus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @eRd- - mov #long_dest, er1 - not.l @er1- -;;; .word 0x0106 -;;; .word 0x6d18 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5a, @long_dest - beq .Llpostdec - fail -.Llpostdec: - test_h_gr32 long_dest-4 er1 ; er1 contains address minus two - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_rdpreinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @+eRd - mov #long_dest-4, er1 - not.l @+er1 ; reg pre-increment operand -;;; .word 0x0105 -;;; .word 0x6d18 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Llpreinc - fail -.Llpreinc: - test_h_gr32 long_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_rdpredec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @-eRd - mov #long_dest+4, er1 - not.l @-er1 ; reg pre-decr operand -;;; .word 0x0107 -;;; .word 0x6d18 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5a, @long_dest - beq .Llpredec - fail -.Llpredec: - test_h_gr32 long_dest er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_disp2dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @(dd:2, erd) - mov #long_dest-4, er1 - not.l @(4:2, er1) ; reg plus 2-bit displacement -;;; .word 0x0105 -;;; .word 0x6918 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Lldisp2 - fail -.Lldisp2: - test_h_gr32 long_dest-4 er1 ; er1 contains address minus one - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_disp16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @(dd:16, erd) - mov #long_dest+100, er1 - not.l @(-100:16, er1) ; reg plus 16-bit displacement -;;; .word 0x0104 -;;; .word 0x6f18 -;;; .word -100 -;;; .word 0x1730 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5a, @long_dest - beq .Lldisp16 - fail -.Lldisp16: - test_h_gr32 long_dest+100 er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_disp32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @(dd:32, erd) - mov #long_dest-0xfffff, er1 - not.l @(0xfffff:32, er1) ; reg plus 32-bit displacement -;;; .word 0x7894 -;;; .word 0x6b28 -;;; .long 0xfffff -;;; .word 0x1730 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Lldisp32 - fail -.Lldisp32: - test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_abs16dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @aa:16 - not.l @long_dest:16 ; 16-bit absolute address -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1730 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - cmp.l #0x5a5a5a5a, @long_dest - beq .Llabs16 - fail -.Llabs16: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -not_l_abs32dst: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; not.l @aa:32 - not.l @long_dest:32 ; 32-bit absolute address -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1730 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - cmp.l #0xa5a5a5a5, @long_dest - beq .Llabs32 - fail -.Llabs32: - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif ; h8sx -.endif ; h8/300 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/orb.s b/sim/testsuite/sim/h8300/orb.s deleted file mode 100644 index 72da8e6..0000000 --- a/sim/testsuite/sim/h8300/orb.s +++ /dev/null @@ -1,532 +0,0 @@ -# Hitachi H8 testcase 'or.b' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # or.b #xx:8, rd ; c rd xxxxxxxx - # or.b #xx:8, @erd ; 7 d rd ???? c ???? xxxxxxxx - # or.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx - # or.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx - # or.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx - # or.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx - # or.b rs, rd ; 1 4 rs rd - # or.b reg8, @erd ; 7 d rd ???? 1 4 rs ???? - # or.b reg8, @erd+ ; 0 1 7 9 8 rd 4 rs - # or.b reg8, @erd- ; 0 1 7 9 a rd 4 rs - # or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs - # or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs - # - # orc #xx:8, ccr - # orc #xx:8, exr - - - # Coming soon: - # ... - -.data -pre_byte: .byte 0 -byte_dest: .byte 0xa5 -post_byte: .byte 0 - - start - -or_b_imm8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.b #xx:8,Rd - or.b #0xaa, r0l ; Immediate 8-bit src, reg8 dest - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5af r0 ; or result: a5 | aa -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5af er0 ; or result: a5 | aa -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -or_b_imm8_rdind: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b #xx:8,@eRd - mov #byte_dest, er0 - or.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst -;;; .word 0x7d00 -;;; .word 0xc0aa - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest, er0 ; er0 still contains address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xaf, r0l - beq .L1 - fail -.L1: - -or_b_imm8_rdpostinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b #xx:8,@eRd+ - mov #byte_dest, er0 - or.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xc055 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 post_byte, er0 ; er0 contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xf5, r0l - beq .L2 - fail -.L2: - -or_b_imm8_rdpostdec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b #xx:8,@eRd- - mov #byte_dest, er0 - or.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xc0aa - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 pre_byte, er0 ; er0 contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xaf, r0l - beq .L3 - fail -.L3: - -or_b_imm8_rdpreinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b #xx:8,@+eRd - mov #pre_byte, er0 - or.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0xc055 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest, er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xf5, r0l - beq .L4 - fail -.L4: - -or_b_imm8_rdpredec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b #xx:8,@-eRd - mov #post_byte, er0 - or.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0xc0aa - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest, er0 ; er0 contains destination address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xaf, r0l - beq .L5 - fail -.L5: - - -.endif - -or_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.b Rs,Rd - mov.b #0xaa, r0h - or.b r0h, r0l ; Reg8 src, reg8 dest - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xaaaf r0 ; or result: a5 | aa -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5aaaf er0 ; or result: a5 | aa -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -or_b_reg8_rdind: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b rs8,@eRd ; or reg8 to register indirect - mov #byte_dest, er0 - mov #0xaa, r1l - or.b r1l, @er0 ; reg8 src, reg indirect dest -;;; .word 0x7d00 -;;; .word 0x1490 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xaf, r0l - beq .L6 - fail -.L6: - -or_b_reg8_rdpostinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b rs8,@eRd+ ; or reg8 to register indirect post-increment - mov #byte_dest, er0 - mov #0x55, r1l - or.b r1l, @er0+ ; reg8 src, reg post-incr dest -;;; .word 0x0179 -;;; .word 0x8049 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_h_gr32 0xa5a5a555 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xf5, r0l - beq .L7 - fail -.L7: - -or_b_reg8_rdpostdec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b rs8,@eRd- ; or reg8 to register indirect post-decrement - mov #byte_dest, er0 - mov #0xaa, r1l - or.b r1l, @er0- ; reg8 src, reg post-decr dest -;;; .word 0x0179 -;;; .word 0xa049 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xaf, r0l - beq .L8 - fail -.L8: - -or_b_reg8_rdpreinc: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b rs8,@+eRd ; or reg8 to register indirect pre-increment - mov #pre_byte, er0 - mov #0x55, r1l - or.b r1l, @+er0 ; reg8 src, reg pre-incr dest -;;; .word 0x0179 -;;; .word 0x9049 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a555 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xf5, r0l - beq .L9 - fail -.L9: - -or_b_reg8_rdpredec: - mov #byte_dest, er0 - mov.b #0xa5, r1l - mov.b r1l, @er0 - - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; or.b rs8,@-eRd ; or reg8 to register indirect pre-decrement - mov #post_byte, er0 - mov #0xaa, r1l - or.b r1l, @-er0 ; reg8 src, reg pre-decr dest -;;; .word 0x0179 -;;; .word 0xb049 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 contains destination address - test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xaf, r0l - beq .L10 - fail -.L10: - -.endif - -orc_imm8_ccr: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; orc #xx:8,ccr - - test_neg_clear - orc #0x8, ccr ; Immediate 8-bit operand (neg flag) - test_neg_set - - test_zero_clear - orc #0x4, ccr ; Immediate 8-bit operand (zero flag) - test_zero_set - - test_ovf_clear - orc #0x2, ccr ; Immediate 8-bit operand (overflow flag) - test_ovf_set - - test_carry_clear - orc #0x1, ccr ; Immediate 8-bit operand (carry flag) - test_carry_set - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr -orc_imm8_exr: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ldc #0, exr - stc exr, r0l - test_h_gr8 0, r0l - - ;; orc #xx:8,exr - - orc #0x1, exr - stc exr,r0l - test_h_gr8 1, r0l - - orc #0x2, exr - stc exr,r0l - test_h_gr8 3, r0l - - orc #0x4, exr - stc exr,r0l - test_h_gr8 7, r0l - - orc #0x80, exr - stc exr,r0l - test_h_gr8 0x87, r0l - - test_h_gr32 0xa5a5a587 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; not h8300 or h8300h - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/orl.s b/sim/testsuite/sim/h8300/orl.s deleted file mode 100644 index 03c3f22..0000000 --- a/sim/testsuite/sim/h8300/orl.s +++ /dev/null @@ -1,77 +0,0 @@ -# Hitachi H8 testcase 'or.l' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. -or_l_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.l #xx:16,Rd - or.l #0xaaaa, er0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a5afaf er0 ; or result: a5a5a5a5 | aaaa - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -or_l_imm32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.l #xx:32,Rd - or.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -or_l_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.l Rs,Rd - mov.l #0xaaaaaaaa, er1 - or.l er1, er0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa - test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/orw.s b/sim/testsuite/sim/h8300/orw.s deleted file mode 100644 index 32eef45..0000000 --- a/sim/testsuite/sim/h8300/orw.s +++ /dev/null @@ -1,61 +0,0 @@ -# Hitachi H8 testcase 'or.w' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -or_w_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.w #xx:16,Rd - or.w #0xaaaa, r0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -or_w_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; or.w Rs,Rd - mov.w #0xaaaa, r1 - or.w r1, r0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa - test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa - test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/rotl.s b/sim/testsuite/sim/h8300/rotl.s deleted file mode 100644 index 1978c2d..0000000 --- a/sim/testsuite/sim/h8300/rotl.s +++ /dev/null @@ -1,1212 +0,0 @@ -# Hitachi H8 testcase 'rotl' -# mach(): h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -rotl_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotl.b r0l ; shift left arithmetic by one - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0xa54b r0 ; 1010 0101 -> 0100 1011 -.if (sim_cpu) - test_h_gr32 0xa5a5a54b er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotl_b_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotl.b @er0 ; shift right arithmetic by one, indirect - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbind1 - fail -.Lbind1: - mov.b #0xa5, @byte_dest - -rotl_b_indexb16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r0l - rotl.b @(byte_dest-5:16, r0.b) ; indexed byte/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbindexb161 - fail -.Lbindexb161: - mov.b #0xa5, @byte_dest - -rotl_b_indexw16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r0 - rotl.b @(byte_dest-256:16, r0.w) ; indexed byte/word - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a50100 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbindexw161 - fail -.Lbindexw161: - mov.b #0xa5, @byte_dest - -rotl_b_indexl16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er0 - rotl.b @(byte_dest+1:16, er0.l) ; indexed byte/long - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xffffffff er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbindexl161 - fail -.Lbindexl161: - mov.b #0xa5, @byte_dest - -rotl_b_indexb32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r1l - rotl.b @(byte_dest-5:32, r1.b) ; indexed byte/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbindexb321 - fail -.Lbindexb321: - mov.b #0xa5, @byte_dest - -rotl_b_indexw32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r1 - rotl.b @(byte_dest-256:32, r1.w) ; indexed byte/word - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a50100 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbindexw321 - fail -.Lbindexw321: - mov.b #0xa5, @byte_dest - -rotl_b_indexl32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er1 - rotl.b @(byte_dest+1:32, er1.l) ; indexed byte/long - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xffffffff er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0100 1011 - cmp.b #0x4b, @byte_dest - beq .Lbindexl321 - fail -.Lbindexl321: - mov.b #0xa5, @byte_dest - -.endif - -rotl_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotl.b #2, r0l ; shift left arithmetic by two - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa596 r0 ; 1010 0101 -> 1001 0110 -.if (sim_cpu) - test_h_gr32 0xa5a5a596 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotl_b_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotl.b #2, @er0 ; shift right arithmetic by one, indirect - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbind2 - fail -.Lbind2: - mov.b #0xa5, @byte_dest - -rotl_b_indexb16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r0l - rotl.b #2, @(byte_dest-5:16, r0.b) ; indexed byte/byte - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a5a505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbindexb162 - fail -.Lbindexb162: - mov.b #0xa5, @byte_dest - -rotl_b_indexw16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r0 - rotl.b #2, @(byte_dest-256:16, r0.w) ; indexed byte/word - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a50100 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbindexw162 - fail -.Lbindexw162: - mov.b #0xa5, @byte_dest - -rotl_b_indexl16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er0 - rotl.b #2, @(byte_dest+1:16, er0.l) ; indexed byte/long - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xffffffff er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbindexl162 - fail -.Lbindexl162: - mov.b #0xa5, @byte_dest - -rotl_b_indexb32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r1l - rotl.b #2, @(byte_dest-5:32, r1.b) ; indexed byte/byte - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbindexb322 - fail -.Lbindexb322: - mov.b #0xa5, @byte_dest - -rotl_b_indexw32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r1 - rotl.b #2, @(byte_dest-256:32, r1.w) ; indexed byte/word - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a50100 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbindexw322 - fail -.Lbindexw322: - mov.b #0xa5, @byte_dest - -rotl_b_indexl32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er1 - rotl.b #2, @(byte_dest+1:32, er1.l) ; indexed byte/long - - test_carry_clear ; H=0 N=1 Z=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xffffffff er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1001 0110 - cmp.b #0x96, @byte_dest - beq .Lbindexl322 - fail -.Lbindexl322: - mov.b #0xa5, @byte_dest - -.endif - -.if (sim_cpu) ; Not available in h8300 mode -rotl_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotl.w r0 ; shift left arithmetic by one - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0x4b4b r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - test_h_gr32 0xa5a54b4b er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotl_w_indexb16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r0l - rotl.w @(word_dest-10:16, r0.b) ; indexed word/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - cmp.w #0x4b4b, @word_dest - beq .Lwindexb161 - fail -.Lwindexb161: - mov.w #0xa5a5, @word_dest - -rotl_w_indexw16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r0 - rotl.w @(word_dest-512:16, r0.w) ; indexed word/word - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a50100 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - cmp.w #0x4b4b, @word_dest - beq .Lwindexw161 - fail -.Lwindexw161: - mov.w #0xa5a5, @word_dest - -rotl_w_indexl16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er0 - rotl.w @(word_dest+2:16, er0.l) ; indexed word/long - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xffffffff er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - cmp.w #0x4b4b, @word_dest - beq .Lwindexl161 - fail -.Lwindexl161: - mov.w #0xa5a5, @word_dest - -rotl_w_indexb32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r1l - rotl.w @(word_dest-10:32, r1.b) ; indexed word/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - cmp.w #0x4b4b, @word_dest - beq .Lwindexb321 - fail -.Lwindexb321: - mov.w #0xa5a5, @word_dest - -rotl_w_indexw32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r1 - rotl.w @(word_dest-512:32, r1.w) ; indexed word/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a50100 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - cmp.w #0x4b4b, @word_dest - beq .Lwindexw321 - fail -.Lwindexw321: - mov.w #0xa5a5, @word_dest - -rotl_w_indexl32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er1 - rotl.w @(word_dest+2:32, er1.l) ; indexed word/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xffffffff er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 - cmp.w #0x4b4b, @word_dest - beq .Lwindexl321 - fail -.Lwindexl321: - mov.w #0xa5a5, @word_dest -.endif - -rotl_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotl.w #2, r0 ; shift left arithmetic by two - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0x9696 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - test_h_gr32 0xa5a59696 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotl_w_indexb16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r0l - rotl.w #2, @(word_dest-10:16, r0.b) ; indexed word/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a5a505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - cmp.w #0x9696, @word_dest - beq .Lwindexb162 - fail -.Lwindexb162: - mov.w #0xa5a5, @word_dest - -rotl_w_indexw16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r0 - rotl.w #2, @(word_dest-512:16, r0.w) ; indexed word/word - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a50100 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - cmp.w #0x9696, @word_dest - beq .Lwindexw162 - fail -.Lwindexw162: - mov.w #0xa5a5, @word_dest - -rotl_w_indexl16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er0 - rotl.w #2, @(word_dest+2:16, er0.l) ; indexed word/long - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xffffffff er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - cmp.w #0x9696, @word_dest - beq .Lwindexl162 - fail -.Lwindexl162: - mov.w #0xa5a5, @word_dest - -rotl_w_indexb32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r1l - rotl.w #2, @(word_dest-10:32, r1.b) ; indexed word/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - cmp.w #0x9696, @word_dest - beq .Lwindexb322 - fail -.Lwindexb322: - mov.w #0xa5a5, @word_dest - -rotl_w_indexw32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r1 - rotl.w #2, @(word_dest-512:32, r1.w) ; indexed word/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a50100 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - cmp.w #0x9696, @word_dest - beq .Lwindexw322 - fail -.Lwindexw322: - mov.w #0xa5a5, @word_dest - -rotl_w_indexl32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er1 - rotl.w #2, @(word_dest+2:32, er1.l) ; indexed word/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xffffffff er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 - cmp.w #0x9696, @word_dest - beq .Lwindexl322 - fail -.Lwindexl322: - mov.w #0xa5a5, @word_dest -.endif - -rotl_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotl.l er0 ; shift left arithmetic by one - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - test_h_gr32 0x4b4b4b4b er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotl_l_indexb16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r0l - rotl.l @(long_dest-20:16, er0.b) ; indexed long/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - cmp.l #0x4b4b4b4b, @long_dest - beq .Llindexb161 - fail -.Llindexb161: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexw16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r0 - rotl.l @(long_dest-1024:16, er0.w) ; indexed long/word - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a50100 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - cmp.l #0x4b4b4b4b, @long_dest - beq .Llindexw161 - fail -.Llindexw161: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexl16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er0 - rotl.l @(long_dest+4:16, er0.l) ; indexed long/long - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xffffffff er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - cmp.l #0x4b4b4b4b, @long_dest - beq .Llindexl161 - fail -.Llindexl161: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexb32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r1l - rotl.l @(long_dest-20:32, er1.b) ; indexed long/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - cmp.l #0x4b4b4b4b, @long_dest - beq .Llindexb321 - fail -.Llindexb321: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexw32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r1 - rotl.l @(long_dest-1024:32, er1.w) ; indexed long/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xa5a50100 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - cmp.l #0x4b4b4b4b, @long_dest - beq .Llindexw321 - fail -.Llindexw321: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexl32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er1 - rotl.l @(long_dest+4:32, er1.l) ; indexed long/byte - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 0xffffffff er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1011 - cmp.l #0x4b4b4b4b, @long_dest - beq .Llindexl321 - fail -.Llindexl321: - mov.l #0xa5a5a5a5, @long_dest -.endif - -rotl_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotl.l #2, er0 ; shift left arithmetic by two - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - test_h_gr32 0x96969696 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotl_l_indexb16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r0l - rotl.l #2, @(long_dest-20:16, er0.b) ; indexed long/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a5a505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - cmp.l #0x96969696, @long_dest - beq .Llindexb162 - fail -.Llindexb162: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexw16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r0 - rotl.l #2, @(long_dest-1024:16, er0.w) ; indexed long/word - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a50100 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - cmp.l #0x96969696, @long_dest - beq .Llindexw162 - fail -.Llindexw162: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexl16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er0 - rotl.l #2, @(long_dest+4:16, er0.l) ; indexed long/long - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xffffffff er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - cmp.l #0x96969696, @long_dest - beq .Llindexl162 - fail -.Llindexl162: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexb32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.b #5, r1l - rotl.l #2, @(long_dest-20:32, er1.b) ; indexed long/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - cmp.l #0x96969696, @long_dest - beq .Llindexb322 - fail -.Llindexb322: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexw32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.w #256, r1 - rotl.l #2, @(long_dest-1024:32, er1.w) ; indexed long/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xa5a50100 er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - cmp.l #0x96969696, @long_dest - beq .Llindexw322 - fail -.Llindexw322: - mov.l #0xa5a5a5a5, @long_dest - -rotl_l_indexl32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov.l #0xffffffff, er1 - rotl.l #2, @(long_dest+4:32, er1.l) ; indexed long/byte - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 0xffffffff er1 - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0110 - cmp.l #0x96969696, @long_dest - beq .Llindexl322 - fail -.Llindexl322: - mov.l #0xa5a5a5a5, @long_dest -.endif -.endif - - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/rotr.s b/sim/testsuite/sim/h8300/rotr.s deleted file mode 100644 index 658ef82..0000000 --- a/sim/testsuite/sim/h8300/rotr.s +++ /dev/null @@ -1,1802 +0,0 @@ -# Hitachi H8 testcase 'rotr' -# mach(): h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -rotr_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.b r0l ; shift right arithmetic by one - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010 -.if (sim_cpu) - test_h_gr32 0xa5a5a5d2 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotr_b_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotr.b @er0 ; shift right arithmetic by one, indirect - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbind1 - fail -.Lbind1: - mov.b #0xa5, @byte_dest - -rotr_b_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotr.b @er0+ ; shift right arithmetic by one, postinc - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpostinc1 - fail -.Lbpostinc1: - mov.b #0xa5, @byte_dest - -rotr_b_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotr.b @er0- ; shift right arithmetic by one, postdec - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpostdec1 - fail -.Lbpostdec1: - mov.b #0xa5, @byte_dest - -rotr_b_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - rotr.b @+er0 ; shift right arithmetic by one, preinc - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpreinc1 - fail -.Lbpreinc1: - mov.b #0xa5, @byte_dest - -rotr_b_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - rotr.b @-er0 ; shift right arithmetic by one, predec - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpredec1 - fail -.Lbpredec1: - mov.b #0xa5, @byte_dest - -rotr_b_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - rotr.b @(2:2, er0) ; shift right arithmetic by one, disp2 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbdisp21 - fail -.Lbdisp21: - mov.b #0xa5, @byte_dest - -rotr_b_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - rotr.b @(44:16, er0) ; shift right arithmetic by one, disp16 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbdisp161 - fail -.Lbdisp161: - mov.b #0xa5, @byte_dest - -rotr_b_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - rotr.b @(666:32, er0) ; shift right arithmetic by one, disp32 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbdisp321 - fail -.Lbdisp321: - mov.b #0xa5, @byte_dest - -rotr_b_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.b @byte_dest:16 ; shift right arithmetic by one, abs16 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbabs161 - fail -.Lbabs161: - mov.b #0xa5, @byte_dest - -rotr_b_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.b @byte_dest:32 ; shift right arithmetic by one, abs32 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbabs321 - fail -.Lbabs321: - mov.b #0xa5, @byte_dest -.endif - -rotr_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.b #2, r0l ; shift right arithmetic by two - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0xa569 r0 ; 1010 0101 -> 0110 1001 -.if (sim_cpu) - test_h_gr32 0xa5a5a569 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotr_b_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotr.b #2, @er0 ; shift right arithmetic by two, indirect - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbind2 - fail -.Lbind2: - mov.b #0xa5, @byte_dest - -rotr_b_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotr.b #2, @er0+ ; shift right arithmetic by two, postinc - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbpostinc2 - fail -.Lbpostinc2: - mov.b #0xa5, @byte_dest - -rotr_b_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotr.b #2, @er0- ; shift right arithmetic by two, postdec - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbpostdec2 - fail -.Lbpostdec2: - mov.b #0xa5, @byte_dest - -rotr_b_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - rotr.b #2, @+er0 ; shift right arithmetic by two, preinc - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbpreinc2 - fail -.Lbpreinc2: - mov.b #0xa5, @byte_dest - -rotr_b_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - rotr.b #2, @-er0 ; shift right arithmetic by two, predec - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbpredec2 - fail -.Lbpredec2: - mov.b #0xa5, @byte_dest - -rotr_b_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - rotr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbdisp22 - fail -.Lbdisp22: - mov.b #0xa5, @byte_dest - -rotr_b_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - rotr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbdisp162 - fail -.Lbdisp162: - mov.b #0xa5, @byte_dest - -rotr_b_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - rotr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbdisp322 - fail -.Lbdisp322: - mov.b #0xa5, @byte_dest - -rotr_b_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbabs162 - fail -.Lbabs162: - mov.b #0xa5, @byte_dest - -rotr_b_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0110 1001 - cmp.b #0x69, @byte_dest - beq .Lbabs322 - fail -.Lbabs322: - mov.b #0xa5, @byte_dest -.endif - -.if (sim_cpu) ; Not available in h8300 mode -rotr_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.w r0 ; shift right arithmetic by one - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - test_h_gr32 0xa5a5d2d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotr_w_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotr.w @er0 ; shift right arithmetic by one, indirect - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwind1 - fail -.Lwind1: - mov.w #0xa5a5, @word_dest - -rotr_w_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotr.w @er0+ ; shift right arithmetic by one, postinc - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpostinc1 - fail -.Lwpostinc1: - mov.w #0xa5a5, @word_dest - -rotr_w_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotr.w @er0- ; shift right arithmetic by one, postdec - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpostdec1 - fail -.Lwpostdec1: - mov.w #0xa5a5, @word_dest - -rotr_w_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - rotr.w @+er0 ; shift right arithmetic by one, preinc - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpreinc1 - fail -.Lwpreinc1: - mov.w #0xa5a5, @word_dest - -rotr_w_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - rotr.w @-er0 ; shift right arithmetic by one, predec - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpredec1 - fail -.Lwpredec1: - mov.w #0xa5a5, @word_dest - -rotr_w_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-4, er0 - rotr.w @(4:2, er0) ; shift right arithmetic by one, disp2 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwdisp21 - fail -.Lwdisp21: - mov.w #0xa5a5, @word_dest - -rotr_w_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - rotr.w @(44:16, er0) ; shift right arithmetic by one, disp16 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwdisp161 - fail -.Lwdisp161: - mov.w #0xa5a5, @word_dest - -rotr_w_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - rotr.w @(666:32, er0) ; shift right arithmetic by one, disp32 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwdisp321 - fail -.Lwdisp321: - mov.w #0xa5a5, @word_dest - -rotr_w_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.w @word_dest:16 ; shift right arithmetic by one, abs16 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwabs161 - fail -.Lwabs161: - mov.w #0xa5a5, @word_dest - -rotr_w_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.w @word_dest:32 ; shift right arithmetic by one, abs32 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwabs321 - fail -.Lwabs321: - mov.w #0xa5a5, @word_dest -.endif - -rotr_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.w #2, r0 ; shift right arithmetic by two - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0x6969 r0 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - test_h_gr32 0xa5a56969 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotr_w_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotr.w #2, @er0 ; shift right arithmetic by two, indirect - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwind2 - fail -.Lwind2: - mov.w #0xa5a5, @word_dest - -rotr_w_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotr.w #2, @er0+ ; shift right arithmetic by two, postinc - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwpostinc2 - fail -.Lwpostinc2: - mov.w #0xa5a5, @word_dest - -rotr_w_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotr.w #2, @er0- ; shift right arithmetic by two, postdec - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwpostdec2 - fail -.Lwpostdec2: - mov.w #0xa5a5, @word_dest - -rotr_w_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - rotr.w #2, @+er0 ; shift right arithmetic by two, preinc - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwpreinc2 - fail -.Lwpreinc2: - mov.w #0xa5a5, @word_dest - -rotr_w_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - rotr.w #2, @-er0 ; shift right arithmetic by two, predec - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwpredec2 - fail -.Lwpredec2: - mov.w #0xa5a5, @word_dest - -rotr_w_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-4, er0 - rotr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwdisp22 - fail -.Lwdisp22: - mov.w #0xa5a5, @word_dest - -rotr_w_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - rotr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwdisp162 - fail -.Lwdisp162: - mov.w #0xa5a5, @word_dest - -rotr_w_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - rotr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwdisp322 - fail -.Lwdisp322: - mov.w #0xa5a5, @word_dest - -rotr_w_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwabs162 - fail -.Lwabs162: - mov.w #0xa5a5, @word_dest - -rotr_w_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 - cmp.w #0x6969, @word_dest - beq .Lwabs322 - fail -.Lwabs322: - mov.w #0xa5a5, @word_dest -.endif - -rotr_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.l er0 ; shift right arithmetic by one, register - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1101 0010 1101 0010 1101 0010 1101 0010 - test_h_gr32 0xd2d2d2d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotr_l_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotr.l @er0 ; shift right arithmetic by one, indirect - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llind1 - fail -.Llind1: - mov #0xa5a5a5a5, @long_dest - -rotr_l_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotr.l @er0+ ; shift right arithmetic by one, postinc - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpostinc1 - fail -.Llpostinc1: - mov #0xa5a5a5a5, @long_dest - -rotr_l_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotr.l @er0- ; shift right arithmetic by one, postdec - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpostdec1 - fail -.Llpostdec1: - mov #0xa5a5a5a5, @long_dest - -rotr_l_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - rotr.l @+er0 ; shift right arithmetic by one, preinc - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpreinc1 - fail -.Llpreinc1: - mov #0xa5a5a5a5, @long_dest - -rotr_l_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - rotr.l @-er0 ; shift right arithmetic by one, predec - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpredec1 - fail -.Llpredec1: - mov #0xa5a5a5a5, @long_dest - -rotr_l_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-8, er0 - rotr.l @(8:2, er0) ; shift right arithmetic by one, disp2 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-8 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Lldisp21 - fail -.Lldisp21: - mov #0xa5a5a5a5, @long_dest - -rotr_l_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - rotr.l @(44:16, er0) ; shift right arithmetic by one, disp16 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Lldisp161 - fail -.Lldisp161: - mov #0xa5a5a5a5, @long_dest - -rotr_l_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - rotr.l @(666:32, er0) ; shift right arithmetic by one, disp32 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Lldisp321 - fail -.Lldisp321: - mov #0xa5a5a5a5, @long_dest - -rotr_l_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.l @long_dest:16 ; shift right arithmetic by one, abs16 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llabs161 - fail -.Llabs161: - mov #0xa5a5a5a5, @long_dest - -rotr_l_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.l @long_dest:32 ; shift right arithmetic by one, abs32 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llabs321 - fail -.Llabs321: - mov #0xa5a5a5a5, @long_dest -.endif - -rotr_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.l #2, er0 ; shift right arithmetic by two, register - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0110 1001 0110 1001 0110 1001 0110 1001 - test_h_gr32 0x69696969 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) - -rotr_l_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotr.l #2, @er0 ; shift right arithmetic by two, indirect - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llind2 - fail -.Llind2: - mov #0xa5a5a5a5, @long_dest - -rotr_l_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotr.l #2, @er0+ ; shift right arithmetic by two, postinc - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llpostinc2 - fail -.Llpostinc2: - mov #0xa5a5a5a5, @long_dest - -rotr_l_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotr.l #2, @er0- ; shift right arithmetic by two, postdec - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llpostdec2 - fail -.Llpostdec2: - mov #0xa5a5a5a5, @long_dest - -rotr_l_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - rotr.l #2, @+er0 ; shift right arithmetic by two, preinc - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llpreinc2 - fail -.Llpreinc2: - mov #0xa5a5a5a5, @long_dest - -rotr_l_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - rotr.l #2, @-er0 ; shift right arithmetic by two, predec - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llpredec2 - fail -.Llpredec2: - mov #0xa5a5a5a5, @long_dest - -rotr_l_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-8, er0 - rotr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-8 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Lldisp22 - fail -.Lldisp22: - mov #0xa5a5a5a5, @long_dest - -rotr_l_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - rotr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Lldisp162 - fail -.Lldisp162: - mov #0xa5a5a5a5, @long_dest - -rotr_l_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - rotr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Lldisp322 - fail -.Lldisp322: - mov #0xa5a5a5a5, @long_dest - -rotr_l_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llabs162 - fail -.Llabs162: - mov #0xa5a5a5a5, @long_dest - -rotr_l_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x69696969, @long_dest - beq .Llabs322 - fail -.Llabs322: - mov #0xa5a5a5a5, @long_dest - -.endif -.endif - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/rotxl.s b/sim/testsuite/sim/h8300/rotxl.s deleted file mode 100644 index d0ff4a3..0000000 --- a/sim/testsuite/sim/h8300/rotxl.s +++ /dev/null @@ -1,167 +0,0 @@ -# Hitachi H8 testcase 'rotxl' -# mach(): h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -rotxl_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxl.b r0l ; shift left arithmetic by one -;;; .word 0x1208 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 -.if (sim_cpu) - test_h_gr32 0xa5a5a54a er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -rotxl_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxl.b #2, r0l ; shift left arithmetic by two -;;; .word 0x1248 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa595 r0 ; 1010 0101 -> 1001 0101 -.if (sim_cpu) - test_h_gr32 0xa5a5a595 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; Not available in h8300 mode -rotxl_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxl.w r0 ; shift left arithmetic by one -;;; .word 0x1210 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 - test_h_gr32 0xa5a54b4a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -rotxl_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxl.w #2, r0 ; shift left arithmetic by two -;;; .word 0x1250 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0x9695 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0101 - test_h_gr32 0xa5a59695 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -rotxl_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxl.l er0 ; shift left arithmetic by one -;;; .word 1030 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1010 - test_h_gr32 0x4b4b4b4a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -rotxl_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxl.l #2, er0 ; shift left arithmetic by two -;;; .word 0x1270 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0101 - test_h_gr32 0x96969695 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/rotxr.s b/sim/testsuite/sim/h8300/rotxr.s deleted file mode 100644 index 31a351f..0000000 --- a/sim/testsuite/sim/h8300/rotxr.s +++ /dev/null @@ -1,2002 +0,0 @@ -# Hitachi H8 testcase 'rotxr' -# mach(): h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -rotxr_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.b r0l ; shift right arithmetic by one -;;; .word 0x1308 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010 -.if (sim_cpu) - test_h_gr32 0xa5a5a552 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotxr_b_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotxr.b @er0 ; shift right arithmetic by one, indirect -;;; .word 0x7d00 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbind1 - fail -.Lbind1: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotxr.b @er0+ ; shift right arithmetic by one, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpostinc1 - fail -.Lbpostinc1: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotxr.b @er0- ; shift right arithmetic by one, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpostdec1 - fail -.Lbpostdec1: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - rotxr.b @+er0 ; shift right arithmetic by one, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpreinc1 - fail -.Lbpreinc1: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - rotxr.b @-er0 ; shift right arithmetic by one, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpredec1 - fail -.Lbpredec1: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - rotxr.b @(2:2, er0) ; shift right arithmetic by one, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbdisp21 - fail -.Lbdisp21: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - rotxr.b @(44:16, er0) ; shift right arithmetic by one, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbdisp161 - fail -.Lbdisp161: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - rotxr.b @(666:32, er0) ; shift right arithmetic by one, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbdisp321 - fail -.Lbdisp321: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.b @byte_dest:16 ; shift right arithmetic by one, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbabs161 - fail -.Lbabs161: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.b @byte_dest:32 ; shift right arithmetic by one, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1300 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbabs321 - fail -.Lbabs321: - mov #0xa5a5a5a5, @byte_dest -.endif - -rotxr_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.b #2, r0l ; shift right arithmetic by two -;;; .word 0x1348 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa5a9 r0 ; 1010 0101 -> 1010 1001 -.if (sim_cpu) - test_h_gr32 0xa5a5a5a9 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotxr_b_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotxr.b #2, @er0 ; shift right arithmetic by two, indirect -;;; .word 0x7d00 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbind2 - fail -.Lbind2: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotxr.b #2, @er0+ ; shift right arithmetic by two, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbpostinc2 - fail -.Lbpostinc2: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - rotxr.b #2, @er0- ; shift right arithmetic by two, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbpostdec2 - fail -.Lbpostdec2: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - rotxr.b #2, @+er0 ; shift right arithmetic by two, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbpreinc2 - fail -.Lbpreinc2: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - rotxr.b #2, @-er0 ; shift right arithmetic by two, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbpredec2 - fail -.Lbpredec2: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - rotxr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbdisp22 - fail -.Lbdisp22: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - rotxr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbdisp162 - fail -.Lbdisp162: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - rotxr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbdisp322 - fail -.Lbdisp322: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbabs162 - fail -.Lbabs162: - mov #0xa5a5a5a5, @byte_dest - -rotxr_b_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1340 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1010 1001 - cmp.b #0xa9, @byte_dest - beq .Lbabs322 - fail -.Lbabs322: - mov #0xa5a5a5a5, @byte_dest -.endif - -.if (sim_cpu) ; Not available in h8300 mode -rotxr_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.w r0 ; shift right arithmetic by one -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - test_h_gr32 0xa5a552d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotxr_w_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotxr.w @er0 ; shift right arithmetic by one, indirect -;;; .word 0x7d80 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwind1 - fail -.Lwind1: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotxr.w @er0+ ; shift right arithmetic by one, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpostinc1 - fail -.Lwpostinc1: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotxr.w @er0- ; shift right arithmetic by one, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpostdec1 - fail -.Lwpostdec1: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - rotxr.w @+er0 ; shift right arithmetic by one, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpreinc1 - fail -.Lwpreinc1: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - rotxr.w @-er0 ; shift right arithmetic by one, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpredec1 - fail -.Lwpredec1: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-4, er0 - rotxr.w @(4:2, er0) ; shift right arithmetic by one, disp2 -;;; .word 0x0156 -;;; .word 0xa908 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwdisp21 - fail -.Lwdisp21: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - rotxr.w @(44:16, er0) ; shift right arithmetic by one, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwdisp161 - fail -.Lwdisp161: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - rotxr.w @(666:32, er0) ; shift right arithmetic by one, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwdisp321 - fail -.Lwdisp321: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.w @word_dest:16 ; shift right arithmetic by one, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwabs161 - fail -.Lwabs161: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.w @word_dest:32 ; shift right arithmetic by one, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1310 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwabs321 - fail -.Lwabs321: - mov #0xa5a5a5a5, @word_dest -.endif - -rotxr_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.w #2, r0 ; shift right arithmetic by two -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa969 r0 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - test_h_gr32 0xa5a5a969 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotxr_w_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotxr.w #2, @er0 ; shift right arithmetic by two, indirect -;;; .word 0x7d80 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwind2 - fail -.Lwind2: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotxr.w #2, @er0+ ; shift right arithmetic by two, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwpostinc2 - fail -.Lwpostinc2: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - rotxr.w #2, @er0- ; shift right arithmetic by two, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwpostdec2 - fail -.Lwpostdec2: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - rotxr.w #2, @+er0 ; shift right arithmetic by two, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwpreinc2 - fail -.Lwpreinc2: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - rotxr.w #2, @-er0 ; shift right arithmetic by two, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwpredec2 - fail -.Lwpredec2: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-4, er0 - rotxr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 -;;; .word 0x0156 -;;; .word 0xa908 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwdisp22 - fail -.Lwdisp22: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - rotxr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwdisp162 - fail -.Lwdisp162: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - rotxr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwdisp322 - fail -.Lwdisp322: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwabs162 - fail -.Lwabs162: - mov #0xa5a5a5a5, @word_dest - -rotxr_w_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1350 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 - cmp.w #0xa969, @word_dest - beq .Lwabs322 - fail -.Lwabs322: - mov #0xa5a5a5a5, @word_dest -.endif - -rotxr_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.l er0 ; shift right arithmetic by one, register -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0101 0010 1101 0010 1101 0010 1101 0010 - test_h_gr32 0x52d2d2d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -rotxr_l_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotxr.l @er0 ; shift right arithmetic by one, indirect -;;; .word 0x0104 -;;; .word 0xa908 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llind1 - fail -.Llind1: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotxr.l @er0+ ; shift right arithmetic by one, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpostinc1 - fail -.Llpostinc1: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotxr.l @er0- ; shift right arithmetic by one, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpostdec1 - fail -.Llpostdec1: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - rotxr.l @+er0 ; shift right arithmetic by one, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpreinc1 - fail -.Llpreinc1: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - rotxr.l @-er0 ; shift right arithmetic by one, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpredec1 - fail -.Llpredec1: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-8, er0 - rotxr.l @(8:2, er0) ; shift right arithmetic by one, disp2 -;;; .word 0x0106 -;;; .word 0xa908 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-8 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Lldisp21 - fail -.Lldisp21: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - rotxr.l @(44:16, er0) ; shift right arithmetic by one, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Lldisp161 - fail -.Lldisp161: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - rotxr.l @(666:32, er0) ; shift right arithmetic by one, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Lldisp321 - fail -.Lldisp321: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.l @long_dest:16 ; shift right arithmetic by one, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llabs161 - fail -.Llabs161: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.l @long_dest:32 ; shift right arithmetic by one, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1330 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llabs321 - fail -.Llabs321: - mov #0xa5a5a5a5, @long_dest -.endif - -rotxr_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.l #2, er0 ; shift right arithmetic by two, register -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1010 1001 0110 1001 0110 1001 0110 1001 - test_h_gr32 0xa9696969 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) - -rotxr_l_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotxr.l #2, @er0 ; shift right arithmetic by two, indirect -;;; .word 0x0104 -;;; .word 0xa908 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llind2 - fail -.Llind2: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotxr.l #2, @er0+ ; shift right arithmetic by two, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llpostinc2 - fail -.Llpostinc2: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - rotxr.l #2, @er0- ; shift right arithmetic by two, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llpostdec2 - fail -.Llpostdec2: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - rotxr.l #2, @+er0 ; shift right arithmetic by two, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llpreinc2 - fail -.Llpreinc2: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - rotxr.l #2, @-er0 ; shift right arithmetic by two, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llpredec2 - fail -.Llpredec2: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-8, er0 - rotxr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 -;;; .word 0x0106 -;;; .word 0xa908 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-8 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Lldisp22 - fail -.Lldisp22: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - rotxr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Lldisp162 - fail -.Lldisp162: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - rotxr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Lldisp322 - fail -.Lldisp322: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llabs162 - fail -.Llabs162: - mov #0xa5a5a5a5, @long_dest - -rotxr_l_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - rotxr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1370 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xa9696969, @long_dest - beq .Llabs322 - fail -.Llabs322: - mov #0xa5a5a5a5, @long_dest - -.endif -.endif - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/shal.s b/sim/testsuite/sim/h8300/shal.s deleted file mode 100644 index 5d930d9..0000000 --- a/sim/testsuite/sim/h8300/shal.s +++ /dev/null @@ -1,167 +0,0 @@ -# Hitachi H8 testcase 'shal' -# mach(): h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -shal_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shal.b r0l ; shift left arithmetic by one -;;; .word 0x1088 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear -; test_ovf_clear ; FIXME - test_neg_clear - test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 -.if (sim_cpu) - test_h_gr32 0xa5a5a54a er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shal_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shal.b #2, r0l ; shift left arithmetic by two -;;; .word 0x10c8 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear -; test_ovf_clear ; FIXME - test_neg_set - - test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100 -.if (sim_cpu) - test_h_gr32 0xa5a5a594 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu) ; Not available in h8300 mode -shal_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shal.w r0 ; shift left arithmetic by one -;;; .word 0x1090 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear -; test_ovf_clear ; FIXME - test_neg_clear - test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 - test_h_gr32 0xa5a54b4a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shal_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shal.w #2, r0 ; shift left arithmetic by two -;;; .word 0x10d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear -; test_ovf_clear ; FIXME - test_neg_set - test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100 - test_h_gr32 0xa5a59694 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shal_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shal.l er0 ; shift left arithmetic by one -;;; .word 10b0 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear -; test_ovf_clear ; FIXME - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1010 - test_h_gr32 0x4b4b4b4a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shal_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shal.l #2, er0 ; shift left arithmetic by two -;;; .word 0x10f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear -; test_ovf_clear ; FIXME - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0100 - test_h_gr32 0x96969694 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/shar.s b/sim/testsuite/sim/h8300/shar.s deleted file mode 100644 index 6b182aa..0000000 --- a/sim/testsuite/sim/h8300/shar.s +++ /dev/null @@ -1,2000 +0,0 @@ -# Hitachi H8 testcase 'shar' -# mach(): h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -shar_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.b r0l ; shift right arithmetic by one -;;; .word 0x1188 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010 -.if (sim_cpu) - test_h_gr32 0xa5a5a5d2 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shar_b_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shar.b @er0 ; shift right arithmetic by one, indirect -;;; .word 0x7d00 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbind1 - fail -.Lbind1: - mov.b #0xa5, @byte_dest - -shar_b_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shar.b @er0+ ; shift right arithmetic by one, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpostinc1 - fail -.Lbpostinc1: - mov.b #0xa5, @byte_dest - -shar_b_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shar.b @er0- ; shift right arithmetic by one, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpostdec1 - fail -.Lbpostdec1: - mov.b #0xa5, @byte_dest - -shar_b_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - shar.b @+er0 ; shift right arithmetic by one, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpreinc1 - fail -.Lbpreinc1: - mov.b #0xa5, @byte_dest - -shar_b_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - shar.b @-er0 ; shift right arithmetic by one, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbpredec1 - fail -.Lbpredec1: - mov.b #0xa5, @byte_dest - -shar_b_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - shar.b @(2:2, er0) ; shift right arithmetic by one, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbdisp21 - fail -.Lbdisp21: - mov.b #0xa5, @byte_dest - -shar_b_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - shar.b @(44:16, er0) ; shift right arithmetic by one, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbdisp161 - fail -.Lbdisp161: - mov.b #0xa5, @byte_dest - -shar_b_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - shar.b @(666:32, er0) ; shift right arithmetic by one, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbdisp321 - fail -.Lbdisp321: - mov.b #0xa5, @byte_dest - -shar_b_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.b @byte_dest:16 ; shift right arithmetic by one, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbabs161 - fail -.Lbabs161: - mov.b #0xa5, @byte_dest - -shar_b_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.b @byte_dest:32 ; shift right arithmetic by one, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1180 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1101 0010 - cmp.b #0xd2, @byte_dest - beq .Lbabs321 - fail -.Lbabs321: - mov.b #0xa5, @byte_dest -.endif - -shar_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.b #2, r0l ; shift right arithmetic by two -;;; .word 0x11c8 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0xa5e9 r0 ; 1010 0101 -> 1110 1001 -.if (sim_cpu) - test_h_gr32 0xa5a5a5e9 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shar_b_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shar.b #2, @er0 ; shift right arithmetic by two, indirect -;;; .word 0x7d00 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbind2 - fail -.Lbind2: - mov.b #0xa5, @byte_dest - -shar_b_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shar.b #2, @er0+ ; shift right arithmetic by two, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbpostinc2 - fail -.Lbpostinc2: - mov.b #0xa5, @byte_dest - -shar_b_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shar.b #2, @er0- ; shift right arithmetic by two, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbpostdec2 - fail -.Lbpostdec2: - mov.b #0xa5, @byte_dest - -shar_b_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - shar.b #2, @+er0 ; shift right arithmetic by two, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbpreinc2 - fail -.Lbpreinc2: - mov.b #0xa5, @byte_dest - -shar_b_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - shar.b #2, @-er0 ; shift right arithmetic by two, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbpredec2 - fail -.Lbpredec2: - mov.b #0xa5, @byte_dest - -shar_b_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - shar.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbdisp22 - fail -.Lbdisp22: - mov.b #0xa5, @byte_dest - -shar_b_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - shar.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbdisp162 - fail -.Lbdisp162: - mov.b #0xa5, @byte_dest - -shar_b_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - shar.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbdisp322 - fail -.Lbdisp322: - mov.b #0xa5, @byte_dest - -shar_b_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbabs162 - fail -.Lbabs162: - mov.b #0xa5, @byte_dest - -shar_b_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x11c0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 1110 1001 - cmp.b #0xe9, @byte_dest - beq .Lbabs322 - fail -.Lbabs322: - mov.b #0xa5, @byte_dest -.endif - -.if (sim_cpu) ; Not available in h8300 mode -shar_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.w r0 ; shift right arithmetic by one -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - test_h_gr32 0xa5a5d2d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shar_w_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shar.w @er0 ; shift right arithmetic by one, indirect -;;; .word 0x7d80 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwind1 - fail -.Lwind1: - mov.w #0xa5a5, @word_dest - -shar_w_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shar.w @er0+ ; shift right arithmetic by one, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpostinc1 - fail -.Lwpostinc1: - mov.w #0xa5a5, @word_dest - -shar_w_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shar.w @er0- ; shift right arithmetic by one, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpostdec1 - fail -.Lwpostdec1: - mov.w #0xa5a5, @word_dest - -shar_w_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shar.w @+er0 ; shift right arithmetic by one, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpreinc1 - fail -.Lwpreinc1: - mov.w #0xa5a5, @word_dest - -shar_w_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - shar.w @-er0 ; shift right arithmetic by one, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwpredec1 - fail -.Lwpredec1: - mov.w #0xa5a5, @word_dest - -shar_w_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-4, er0 - shar.w @(4:2, er0) ; shift right arithmetic by one, disp2 -;;; .word 0x0156 -;;; .word 0x6908 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwdisp21 - fail -.Lwdisp21: - mov.w #0xa5a5, @word_dest - -shar_w_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - shar.w @(44:16, er0) ; shift right arithmetic by one, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwdisp161 - fail -.Lwdisp161: - mov.w #0xa5a5, @word_dest - -shar_w_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - shar.w @(666:32, er0) ; shift right arithmetic by one, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwdisp321 - fail -.Lwdisp321: - mov.w #0xa5a5, @word_dest - -shar_w_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.w @word_dest:16 ; shift right arithmetic by one, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwabs161 - fail -.Lwabs161: - mov.w #0xa5a5, @word_dest - -shar_w_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.w @word_dest:32 ; shift right arithmetic by one, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1190 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 - cmp.w #0xd2d2, @word_dest - beq .Lwabs321 - fail -.Lwabs321: - mov.w #0xa5a5, @word_dest -.endif - -shar_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.w #2, r0 ; shift right arithmetic by two -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xe969 r0 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - test_h_gr32 0xa5a5e969 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shar_w_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shar.w #2, @er0 ; shift right arithmetic by two, indirect -;;; .word 0x7d80 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwind2 - fail -.Lwind2: - mov.w #0xa5a5, @word_dest - -shar_w_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shar.w #2, @er0+ ; shift right arithmetic by two, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwpostinc2 - fail -.Lwpostinc2: - mov.w #0xa5a5, @word_dest - -shar_w_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shar.w #2, @er0- ; shift right arithmetic by two, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwpostdec2 - fail -.Lwpostdec2: - mov.w #0xa5a5, @word_dest - -shar_w_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shar.w #2, @+er0 ; shift right arithmetic by two, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwpreinc2 - fail -.Lwpreinc2: - mov.w #0xa5a5, @word_dest - -shar_w_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - shar.w #2, @-er0 ; shift right arithmetic by two, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwpredec2 - fail -.Lwpredec2: - mov.w #0xa5a5, @word_dest - -shar_w_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-4, er0 - shar.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 -;;; .word 0x0156 -;;; .word 0x6908 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwdisp22 - fail -.Lwdisp22: - mov.w #0xa5a5, @word_dest - -shar_w_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - shar.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwdisp162 - fail -.Lwdisp162: - mov.w #0xa5a5, @word_dest - -shar_w_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - shar.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwdisp322 - fail -.Lwdisp322: - mov.w #0xa5a5, @word_dest - -shar_w_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwabs162 - fail -.Lwabs162: - mov.w #0xa5a5, @word_dest - -shar_w_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x11d0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 - cmp.w #0xe969, @word_dest - beq .Lwabs322 - fail -.Lwabs322: - mov.w #0xa5a5, @word_dest -.endif - -shar_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.l er0 ; shift right arithmetic by one, register -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1101 0010 1101 0010 1101 0010 1101 0010 - test_h_gr32 0xd2d2d2d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shar_l_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shar.l @er0 ; shift right arithmetic by one, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llind1 - fail -.Llind1: - mov #0xa5a5a5a5, @long_dest - -shar_l_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shar.l @er0+ ; shift right arithmetic by one, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpostinc1 - fail -.Llpostinc1: - mov #0xa5a5a5a5, @long_dest - -shar_l_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shar.l @er0- ; shift right arithmetic by one, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpostdec1 - fail -.Llpostdec1: - mov #0xa5a5a5a5, @long_dest - -shar_l_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shar.l @+er0 ; shift right arithmetic by one, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpreinc1 - fail -.Llpreinc1: - mov #0xa5a5a5a5, @long_dest - -shar_l_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shar.l @-er0 ; shift right arithmetic by one, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llpredec1 - fail -.Llpredec1: - mov #0xa5a5a5a5, @long_dest - -shar_l_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-8, er0 - shar.l @(8:2, er0) ; shift right arithmetic by one, disp2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-8 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Lldisp21 - fail -.Lldisp21: - mov #0xa5a5a5a5, @long_dest - -shar_l_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shar.l @(44:16, er0) ; shift right arithmetic by one, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Lldisp161 - fail -.Lldisp161: - mov #0xa5a5a5a5, @long_dest - -shar_l_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shar.l @(666:32, er0) ; shift right arithmetic by one, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Lldisp321 - fail -.Lldisp321: - mov #0xa5a5a5a5, @long_dest - -shar_l_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.l @long_dest:16 ; shift right arithmetic by one, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llabs161 - fail -.Llabs161: - mov #0xa5a5a5a5, @long_dest - -shar_l_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.l @long_dest:32 ; shift right arithmetic by one, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x11b0 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0xd2d2d2d2, @long_dest - beq .Llabs321 - fail -.Llabs321: - mov #0xa5a5a5a5, @long_dest -.endif - -shar_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.l #2, er0 ; shift right arithmetic by two, register -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1110 1001 0110 1001 0110 1001 0110 1001 - test_h_gr32 0xe9696969 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) - -shar_l_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shar.l #2, @er0 ; shift right arithmetic by two, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llind2 - fail -.Llind2: - mov #0xa5a5a5a5, @long_dest - -shar_l_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shar.l #2, @er0+ ; shift right arithmetic by two, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llpostinc2 - fail -.Llpostinc2: - mov #0xa5a5a5a5, @long_dest - -shar_l_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shar.l #2, @er0- ; shift right arithmetic by two, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llpostdec2 - fail -.Llpostdec2: - mov #0xa5a5a5a5, @long_dest - -shar_l_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shar.l #2, @+er0 ; shift right arithmetic by two, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llpreinc2 - fail -.Llpreinc2: - mov #0xa5a5a5a5, @long_dest - -shar_l_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shar.l #2, @-er0 ; shift right arithmetic by two, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llpredec2 - fail -.Llpredec2: - mov #0xa5a5a5a5, @long_dest - -shar_l_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-8, er0 - shar.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-8 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Lldisp22 - fail -.Lldisp22: - mov #0xa5a5a5a5, @long_dest - -shar_l_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shar.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Lldisp162 - fail -.Lldisp162: - mov #0xa5a5a5a5, @long_dest - -shar_l_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shar.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Lldisp322 - fail -.Lldisp322: - mov #0xa5a5a5a5, @long_dest - -shar_l_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llabs162 - fail -.Llabs162: - mov #0xa5a5a5a5, @long_dest - -shar_l_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shar.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x11f0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0xe9696969, @long_dest - beq .Llabs322 - fail -.Llabs322: - mov #0xa5a5a5a5, @long_dest - -.endif -.endif - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/shll.s b/sim/testsuite/sim/h8300/shll.s deleted file mode 100644 index f21a60b..0000000 --- a/sim/testsuite/sim/h8300/shll.s +++ /dev/null @@ -1,375 +0,0 @@ -# Hitachi H8 testcase 'shll' -# mach(): h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -shll_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.b r0l ; shift left logical by one -;;; .word 0x1008 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 -.if (sim_cpu) - test_h_gr32 0xa5a5a54a er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.b #2, r0l ; shift left logical by two -;;; .word 0x1048 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - - test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100 -.if (sim_cpu) - test_h_gr32 0xa5a5a594 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shll_b_reg8_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.b #4, r0l ; shift left logical by four -;;; .word 0x10a8 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0xa550 r0 ; 1010 0101 -> 0101 0000 - test_h_gr32 0xa5a5a550 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #5, r0h - shll.b r0h, r0l ; shift left logical by register value - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0x05a0 r0 ; 1010 0101 -> 1010 0000 - test_h_gr32 0xa5a505a0 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu) ; Not available in h8300 mode -shll_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.w r0 ; shift left logical by one -;;; .word 0x1010 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 - test_h_gr32 0xa5a54b4a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.w #2, r0 ; shift left logical by two -;;; .word 0x1050 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100 - test_h_gr32 0xa5a59694 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shll_w_reg16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.w #4, r0 ; shift left logical by four -;;; .word 0x1020 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0x5a50 r0 ; 1010 0101 1010 0101 -> 0101 1010 0101 0000 - test_h_gr32 0xa5a55a50 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_w_reg16_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.w #8, r0 ; shift left logical by eight -;;; .word 0x1060 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0xa500 r0 ; 1010 0101 1010 0101 -> 1010 0101 0000 0000 - test_h_gr32 0xa5a5a500 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_w_reg16_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #5, r0h - shll.w r0h, r0 ; shift left logical by register value - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0xb4a0 r0 ; 1010 0101 1010 0101 -> 1011 0100 1010 0000 - test_h_gr32 0xa5a5b4a0 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -shll_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.l er0 ; shift left logical by one -;;; .word 1030 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0100 1011 0100 1011 0100 1011 0100 1010 - test_h_gr32 0x4b4b4b4a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.l #2, er0 ; shift left logical by two -;;; .word 0x1070 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1001 0110 1001 0110 1001 0110 1001 0100 - test_h_gr32 0x96969694 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shll_l_reg32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.l #4, er0 ; shift left logical by four -;;; .word 0x1038 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0101 1010 0101 1010 0101 1010 0101 0000 - test_h_gr32 0x5a5a5a50 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_l_reg32_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.l #8, er0 ; shift left logical by eight -;;; .word 0x1078 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - test_h_gr16 0xa500 r0 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1010 0101 1010 0101 1010 0101 0000 0000 - test_h_gr32 0xa5a5a500 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_l_reg32_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shll.l #16, er0 ; shift left logical by sixteen -;;; .word 0x10f8 - - test_carry_set ; H=0 N=1 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 1010 0101 1010 0101 0000 0000 0000 0000 - test_h_gr32 0xa5a50000 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shll_l_reg32_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #5, r1l - shll.l r1l, er0 ; shift left logical by register value - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_set - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 1011 0100 1011 0100 1011 0100 1010 0000 - test_h_gr32 0xb4b4b4a0 er0 - - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif -.endif - - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/shlr.s b/sim/testsuite/sim/h8300/shlr.s deleted file mode 100644 index c9f6a08..0000000 --- a/sim/testsuite/sim/h8300/shlr.s +++ /dev/null @@ -1,4085 +0,0 @@ -# Hitachi H8 testcase 'shlr' -# mach(): h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - - .data -byte_dest: .byte 0xa5 - .align 2 -word_dest: .word 0xa5a5 - .align 4 -long_dest: .long 0xa5a5a5a5 - - .text - -shlr_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b r0l ; shift right logical by one -;;; .word 0x1108 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010 -.if (sim_cpu) - test_h_gr32 0xa5a5a552 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shlr_b_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b @er0 ; shift right logical by one, indirect -;;; .word 0x7d00 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbind1 - fail -.Lbind1: - mov.b #0xa5, @byte_dest - -shlr_b_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b @er0+ ; shift right logical by one, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpostinc1 - fail -.Lbpostinc1: - mov.b #0xa5, @byte_dest - -shlr_b_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b @er0- ; shift right logical by one, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpostdec1 - fail -.Lbpostdec1: - mov.b #0xa5, @byte_dest - -shlr_b_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - shlr.b @+er0 ; shift right logical by one, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpreinc1 - fail -.Lbpreinc1: - mov.b #0xa5, @byte_dest - -shlr_b_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - shlr.b @-er0 ; shift right logical by one, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbpredec1 - fail -.Lbpredec1: - mov.b #0xa5, @byte_dest - -shlr_b_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - shlr.b @(2:2, er0) ; shift right logical by one, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbdisp21 - fail -.Lbdisp21: - mov.b #0xa5, @byte_dest - -shlr_b_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - shlr.b @(44:16, er0) ; shift right logical by one, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbdisp161 - fail -.Lbdisp161: - mov.b #0xa5, @byte_dest - -shlr_b_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - shlr.b @(666:32, er0) ; shift right logical by one, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbdisp321 - fail -.Lbdisp321: - mov.b #0xa5, @byte_dest - -shlr_b_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b @byte_dest:16 ; shift right logical by one, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbabs161 - fail -.Lbabs161: - mov.b #0xa5, @byte_dest - -shlr_b_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b @byte_dest:32 ; shift right logical by one, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1100 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0101 0010 - cmp.b #0x52, @byte_dest - beq .Lbabs321 - fail -.Lbabs321: - mov.b #0xa5, @byte_dest -.endif - -shlr_b_reg8_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b #2, r0l ; shift right logical by two -;;; .word 0x1148 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0xa529 r0 ; 1010 0101 -> 0010 1001 -.if (sim_cpu) - test_h_gr32 0xa5a5a529 er0 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shlr_b_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b #2, @er0 ; shift right logical by two, indirect -;;; .word 0x7d00 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbind2 - fail -.Lbind2: - mov.b #0xa5, @byte_dest - -shlr_b_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b #2, @er0+ ; shift right logical by two, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbpostinc2 - fail -.Lbpostinc2: - mov.b #0xa5, @byte_dest - -shlr_b_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b #2, @er0- ; shift right logical by two, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbpostdec2 - fail -.Lbpostdec2: - mov.b #0xa5, @byte_dest - -shlr_b_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - shlr.b #2, @+er0 ; shift right logical by two, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbpreinc2 - fail -.Lbpreinc2: - mov.b #0xa5, @byte_dest - -shlr_b_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - shlr.b #2, @-er0 ; shift right logical by two, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbpredec2 - fail -.Lbpredec2: - mov.b #0xa5, @byte_dest - -shlr_b_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - shlr.b #2, @(2:2, er0) ; shift right logical by two, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbdisp22 - fail -.Lbdisp22: - mov.b #0xa5, @byte_dest - -shlr_b_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - shlr.b #2, @(44:16, er0) ; shift right logical by two, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbdisp162 - fail -.Lbdisp162: - mov.b #0xa5, @byte_dest - -shlr_b_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - shlr.b #2, @(666:32, er0) ; shift right logical by two, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbdisp322 - fail -.Lbdisp322: - mov.b #0xa5, @byte_dest - -shlr_b_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b #2, @byte_dest:16 ; shift right logical by two, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbabs162 - fail -.Lbabs162: - mov.b #0xa5, @byte_dest - -shlr_b_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b #2, @byte_dest:32 ; shift right logical by two, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x1140 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0010 1001 - cmp.b #0x29, @byte_dest - beq .Lbabs322 - fail -.Lbabs322: - mov.b #0xa5, @byte_dest - -shlr_b_reg8_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b #4, r0l ; shift right logical by four -;;; .word 0x11a8 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0xa50a r0 ; 1010 0101 -> 0000 1010 - test_h_gr32 0xa5a5a50a er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #5, r0h - shlr.b r0h, r0l ; shift right logical by register value - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0x0505 r0 ; 1010 0101 -> 0000 0101 - test_h_gr32 0xa5a50505 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_b_ind_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b #4, @er0 ; shift right logical by four, indirect -;;; .word 0x7d00 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbind4 - fail -.Lbind4: - mov.b #0xa5, @byte_dest - -shlr_b_postinc_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b #4, @er0+ ; shift right logical by four, postinc -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest+1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbpostinc4 - fail -.Lbpostinc4: - mov.b #0xa5, @byte_dest - -shlr_b_postdec_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest, er0 - shlr.b #4, @er0- ; shift right logical by four, postdec -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-1 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbpostdec4 - fail -.Lbpostdec4: - mov.b #0xa5, @byte_dest - -shlr_b_preinc_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-1, er0 - shlr.b #4, @+er0 ; shift right logical by four, preinc -;;; .word 0x0175 -;;; .word 0x6c08 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbpreinc4 - fail -.Lbpreinc4: - mov.b #0xa5, @byte_dest - -shlr_b_predec_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest+1, er0 - shlr.b #4, @-er0 ; shift right logical by four, predec -;;; .word 0x0177 -;;; .word 0x6c08 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbpredec4 - fail -.Lbpredec4: - mov.b #0xa5, @byte_dest - -shlr_b_disp2_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-2, er0 - shlr.b #4, @(2:2, er0) ; shift right logical by four, disp2 -;;; .word 0x0176 -;;; .word 0x6808 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbdisp24 - fail -.Lbdisp24: - mov.b #0xa5, @byte_dest - -shlr_b_disp16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-44, er0 - shlr.b #4, @(44:16, er0) ; shift right logical by four, disp16 -;;; .word 0x0174 -;;; .word 0x6e08 -;;; .word 44 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbdisp164 - fail -.Lbdisp164: - mov.b #0xa5, @byte_dest - -shlr_b_disp32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #byte_dest-666, er0 - shlr.b #4, @(666:32, er0) ; shift right logical by four, disp32 -;;; .word 0x7884 -;;; .word 0x6a28 -;;; .long 666 -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 byte_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbdisp324 - fail -.Lbdisp324: - mov.b #0xa5, @byte_dest - -shlr_b_abs16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b #4, @byte_dest:16 ; shift right logical by four, abs16 -;;; .word 0x6a18 -;;; .word byte_dest -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbabs164 - fail -.Lbabs164: - mov.b #0xa5, @byte_dest - -shlr_b_abs32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.b #4, @byte_dest:32 ; shift right logical by four, abs32 -;;; .word 0x6a38 -;;; .long byte_dest -;;; .word 0x11a0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 -> 0000 1010 - cmp.b #0x0a, @byte_dest - beq .Lbabs324 - fail -.Lbabs324: - mov.b #0xa5, @byte_dest -.endif - -.if (sim_cpu == h8sx) -shlr_w_imm5_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #15:5, r0 ; shift right logical by 5-bit immediate -;;; .word 0x038f -;;; .word 0x1110 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - ; 1010 0101 1010 0101 -> 0000 0000 0000 0001 - test_h_gr32 0xa5a50001 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu) ; Not available in h8300 mode -shlr_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w r0 ; shift right logical by one -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - test_h_gr32 0xa5a552d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shlr_w_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w @er0 ; shift right logical by one, indirect -;;; .word 0x7d80 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwind1 - fail -.Lwind1: - mov.w #0xa5a5, @word_dest - -shlr_w_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w @er0+ ; shift right logical by one, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpostinc1 - fail -.Lwpostinc1: - mov.w #0xa5a5, @word_dest - -shlr_w_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w @er0- ; shift right logical by one, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpostdec1 - fail -.Lwpostdec1: - mov.w #0xa5a5, @word_dest - -shlr_w_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shlr.w @+er0 ; shift right logical by one, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpreinc1 - fail -.Lwpreinc1: - mov.w #0xa5a5, @word_dest - -shlr_w_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - shlr.w @-er0 ; shift right logical by one, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwpredec1 - fail -.Lwpredec1: - mov.w #0xa5a5, @word_dest - -shlr_w_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-4, er0 - shlr.w @(4:2, er0) ; shift right logical by one, disp2 -;;; .word 0x0156 -;;; .word 0x6908 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwdisp21 - fail -.Lwdisp21: - mov.w #0xa5a5, @word_dest - -shlr_w_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - shlr.w @(44:16, er0) ; shift right logical by one, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwdisp161 - fail -.Lwdisp161: - mov.w #0xa5a5, @word_dest - -shlr_w_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - shlr.w @(666:32, er0) ; shift right logical by one, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwdisp321 - fail -.Lwdisp321: - mov.w #0xa5a5, @word_dest - -shlr_w_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w @word_dest:16 ; shift right logical by one, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwabs161 - fail -.Lwabs161: - mov.w #0xa5a5, @word_dest - -shlr_w_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w @word_dest:32 ; shift right logical by one, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1110 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 - cmp.w #0x52d2, @word_dest - beq .Lwabs321 - fail -.Lwabs321: - mov.w #0xa5a5, @word_dest -.endif - -shlr_w_reg16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #2, r0 ; shift right logical by two -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0x2969 r0 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - test_h_gr32 0xa5a52969 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shlr_w_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #2, @er0 ; shift right logical by two, indirect -;;; .word 0x7d80 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwind2 - fail -.Lwind2: - mov.w #0xa5a5, @word_dest - -shlr_w_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #2, @er0+ ; shift right logical by two, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwpostinc2 - fail -.Lwpostinc2: - mov.w #0xa5a5, @word_dest - -shlr_w_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #2, @er0- ; shift right logical by two, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwpostdec2 - fail -.Lwpostdec2: - mov.w #0xa5a5, @word_dest - -shlr_w_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shlr.w #2, @+er0 ; shift right logical by two, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwpreinc2 - fail -.Lwpreinc2: - mov.w #0xa5a5, @word_dest - -shlr_w_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - shlr.w #2, @-er0 ; shift right logical by two, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwpredec2 - fail -.Lwpredec2: - mov.w #0xa5a5, @word_dest - -shlr_w_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-4, er0 - shlr.w #2, @(4:2, er0) ; shift right logical by two, disp2 -;;; .word 0x0156 -;;; .word 0x6908 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwdisp22 - fail -.Lwdisp22: - mov.w #0xa5a5, @word_dest - -shlr_w_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - shlr.w #2, @(44:16, er0) ; shift right logical by two, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwdisp162 - fail -.Lwdisp162: - mov.w #0xa5a5, @word_dest - -shlr_w_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - shlr.w #2, @(666:32, er0) ; shift right logical by two, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwdisp322 - fail -.Lwdisp322: - mov.w #0xa5a5, @word_dest - -shlr_w_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #2, @word_dest:16 ; shift right logical by two, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwabs162 - fail -.Lwabs162: - mov.w #0xa5a5, @word_dest - -shlr_w_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #2, @word_dest:32 ; shift right logical by two, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1150 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 - cmp.w #0x2969, @word_dest - beq .Lwabs322 - fail -.Lwabs322: - mov.w #0xa5a5, @word_dest - -shlr_w_reg16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #4, r0 ; shift right logical by four -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0x0a5a r0 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - test_h_gr32 0xa5a50a5a er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_w_reg16_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #5, r1l - shlr.w r1l, r0 ; shift right logical by register value - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0x052d r0 ; 1010 0101 1010 0101 -> 0000 0101 0010 1101 - test_h_gr32 0xa5a5052d er0 - test_h_gr32 0xa5a5a505 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_w_ind_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #4, @er0 ; shift right logical by four, indirect -;;; .word 0x7d80 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwind4 - fail -.Lwind4: - mov.w #0xa5a5, @word_dest - -shlr_w_postinc_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #4, @er0+ ; shift right logical by four, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwpostinc4 - fail -.Lwpostinc4: - mov.w #0xa5a5, @word_dest - -shlr_w_postdec_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #4, @er0- ; shift right logical by four, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwpostdec4 - fail -.Lwpostdec4: - mov.w #0xa5a5, @word_dest - -shlr_w_preinc_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shlr.w #4, @+er0 ; shift right logical by four, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwpreinc4 - fail -.Lwpreinc4: - mov.w #0xa5a5, @word_dest - -shlr_w_predec_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - shlr.w #4, @-er0 ; shift right logical by four, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwpredec4 - fail -.Lwpredec4: - mov.w #0xa5a5, @word_dest - -shlr_w_disp2_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-4, er0 - shlr.w #4, @(4:2, er0) ; shift right logical by four, disp2 -;;; .word 0x0156 -;;; .word 0x6908 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwdisp24 - fail -.Lwdisp24: - mov.w #0xa5a5, @word_dest - -shlr_w_disp16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - shlr.w #4, @(44:16, er0) ; shift right logical by four, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwdisp164 - fail -.Lwdisp164: - mov.w #0xa5a5, @word_dest - -shlr_w_disp32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - shlr.w #4, @(666:32, er0) ; shift right logical by four, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwdisp324 - fail -.Lwdisp324: - mov.w #0xa5a5, @word_dest - -shlr_w_abs16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #4, @word_dest:16 ; shift right logical by four, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwabs164 - fail -.Lwabs164: - mov.w #0xa5a5, @word_dest - -shlr_w_abs32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #4, @word_dest:32 ; shift right logical by four, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1120 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 - cmp.w #0x0a5a, @word_dest - beq .Lwabs324 - fail -.Lwabs324: - mov.w #0xa5a5, @word_dest - -shlr_w_reg16_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #8, r0 ; shift right logical by eight -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr16 0x00a5 r0 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - test_h_gr32 0xa5a500a5 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_w_ind_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #8, @er0 ; shift right logical by eight, indirect -;;; .word 0x7d80 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwind8 - fail -.Lwind8: - mov.w #0xa5a5, @word_dest - -shlr_w_postinc_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #8, @er0+ ; shift right logical by eight, postinc -;;; .word 0x0154 -;;; .word 0x6d08 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest+2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwpostinc8 - fail -.Lwpostinc8: - mov.w #0xa5a5, @word_dest - -shlr_w_postdec_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest, er0 - shlr.w #8, @er0- ; shift right logical by eight, postdec -;;; .word 0x0156 -;;; .word 0x6d08 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-2 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwpostdec8 - fail -.Lwpostdec8: - mov.w #0xa5a5, @word_dest - -shlr_w_preinc_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-2, er0 - shlr.w #8, @+er0 ; shift right logical by eight, preinc -;;; .word 0x0155 -;;; .word 0x6d08 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwpreinc8 - fail -.Lwpreinc8: - mov.w #0xa5a5, @word_dest - -shlr_w_predec_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest+2, er0 - shlr.w #8, @-er0 ; shift right logical by eight, predec -;;; .word 0x0157 -;;; .word 0x6d08 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwpredec8 - fail -.Lwpredec8: - mov.w #0xa5a5, @word_dest - -shlr_w_disp2_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-4, er0 - shlr.w #8, @(4:2, er0) ; shift right logical by eight, disp2 -;;; .word 0x0156 -;;; .word 0x6908 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwdisp28 - fail -.Lwdisp28: - mov.w #0xa5a5, @word_dest - -shlr_w_disp16_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-44, er0 - shlr.w #8, @(44:16, er0) ; shift right logical by eight, disp16 -;;; .word 0x0154 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwdisp168 - fail -.Lwdisp168: - mov.w #0xa5a5, @word_dest - -shlr_w_disp32_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #word_dest-666, er0 - shlr.w #8, @(666:32, er0) ; shift right logical by eight, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 word_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwdisp328 - fail -.Lwdisp328: - mov.w #0xa5a5, @word_dest - -shlr_w_abs16_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #8, @word_dest:16 ; shift right logical by eight, abs16 -;;; .word 0x6b18 -;;; .word word_dest -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwabs168 - fail -.Lwabs168: - mov.w #0xa5a5, @word_dest - -shlr_w_abs32_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.w #8, @word_dest:32 ; shift right logical by eight, abs32 -;;; .word 0x6b38 -;;; .long word_dest -;;; .word 0x1160 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 - cmp.w #0x00a5, @word_dest - beq .Lwabs328 - fail -.Lwabs328: - mov.w #0xa5a5, @word_dest - -shlr_l_imm5_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #31:5, er0 ; shift right logical by 5-bit immediate -;;; .word 0x0399 -;;; .word 0x1130 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0000 0000 0000 0000 0000 0000 0000 0001 - test_h_gr32 0x1 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -shlr_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l er0 ; shift right logical by one, register -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0101 0010 1101 0010 1101 0010 1101 0010 - test_h_gr32 0x52d2d2d2 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -shlr_l_ind_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l @er0 ; shift right logical by one, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llind1 - fail -.Llind1: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l @er0+ ; shift right logical by one, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpostinc1 - fail -.Llpostinc1: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postdec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l @er0- ; shift right logical by one, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpostdec1 - fail -.Llpostdec1: - mov #0xa5a5a5a5, @long_dest - -shlr_l_preinc_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shlr.l @+er0 ; shift right logical by one, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpreinc1 - fail -.Llpreinc1: - mov #0xa5a5a5a5, @long_dest - -shlr_l_predec_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shlr.l @-er0 ; shift right logical by one, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llpredec1 - fail -.Llpredec1: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp2_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-8, er0 - shlr.l @(8:2, er0) ; shift right logical by one, disp2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-8 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Lldisp21 - fail -.Lldisp21: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shlr.l @(44:16, er0) ; shift right logical by one, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Lldisp161 - fail -.Lldisp161: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shlr.l @(666:32, er0) ; shift right logical by one, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Lldisp321 - fail -.Lldisp321: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l @long_dest:16 ; shift right logical by one, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llabs161 - fail -.Llabs161: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l @long_dest:32 ; shift right logical by one, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1130 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 - cmp.l #0x52d2d2d2, @long_dest - beq .Llabs321 - fail -.Llabs321: - mov #0xa5a5a5a5, @long_dest -.endif - -shlr_l_reg32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #2, er0 ; shift right logical by two, register -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0010 1001 0110 1001 0110 1001 0110 1001 - test_h_gr32 0x29696969 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) - -shlr_l_ind_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #2, @er0 ; shift right logical by two, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llind2 - fail -.Llind2: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #2, @er0+ ; shift right logical by two, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llpostinc2 - fail -.Llpostinc2: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postdec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #2, @er0- ; shift right logical by two, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llpostdec2 - fail -.Llpostdec2: - mov #0xa5a5a5a5, @long_dest - -shlr_l_preinc_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shlr.l #2, @+er0 ; shift right logical by two, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llpreinc2 - fail -.Llpreinc2: - mov #0xa5a5a5a5, @long_dest - -shlr_l_predec_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shlr.l #2, @-er0 ; shift right logical by two, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llpredec2 - fail -.Llpredec2: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp2_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-8, er0 - shlr.l #2, @(8:2, er0) ; shift right logical by two, disp2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-8 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Lldisp22 - fail -.Lldisp22: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shlr.l #2, @(44:16, er0) ; shift right logical by two, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Lldisp162 - fail -.Lldisp162: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shlr.l #2, @(666:32, er0) ; shift right logical by two, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Lldisp322 - fail -.Lldisp322: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs16_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #2, @long_dest:16 ; shift right logical by two, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llabs162 - fail -.Llabs162: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs32_2: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #2, @long_dest:32 ; shift right logical by two, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1170 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 - cmp.l #0x29696969, @long_dest - beq .Llabs322 - fail -.Llabs322: - mov #0xa5a5a5a5, @long_dest - -shlr_l_reg32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #4, er0 ; shift right logical by four, register -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0000 1010 0101 1010 0101 1010 0101 1010 - test_h_gr32 0x0a5a5a5a er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_l_reg32_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #5, r1l - shlr.l r1l, er0 ; shift right logical by value of register - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0000 0101 0010 1101 0010 1101 0010 1101 - test_h_gr32 0x052d2d2d er0 - test_h_gr32 0xa5a5a505 er1 - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_l_ind_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #4, @er0 ; shift right logical by four, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llind4 - fail -.Llind4: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postinc_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #4, @er0+ ; shift right logical by four, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llpostinc4 - fail -.Llpostinc4: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postdec_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #4, @er0- ; shift right logical by four, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llpostdec4 - fail -.Llpostdec4: - mov #0xa5a5a5a5, @long_dest - -shlr_l_preinc_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shlr.l #4, @+er0 ; shift right logical by four, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llpreinc4 - fail -.Llpreinc4: - mov #0xa5a5a5a5, @long_dest - -shlr_l_predec_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shlr.l #4, @-er0 ; shift right logical by four, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llpredec4 - fail -.Llpredec4: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp2_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-8, er0 - shlr.l #4, @(8:2, er0) ; shift right logical by four, disp2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-8 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Lldisp24 - fail -.Lldisp24: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shlr.l #4, @(44:16, er0) ; shift right logical by four, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Lldisp164 - fail -.Lldisp164: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shlr.l #4, @(666:32, er0) ; shift right logical by four, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Lldisp324 - fail -.Lldisp324: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs16_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #4, @long_dest:16 ; shift right logical by four, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llabs164 - fail -.Llabs164: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs32_4: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #4, @long_dest:32 ; shift right logical by four, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1138 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 - cmp.l #0x0a5a5a5a, @long_dest - beq .Llabs324 - fail -.Llabs324: - mov #0xa5a5a5a5, @long_dest - -shlr_l_reg32_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #8, er0 ; shift right logical by eight, register -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ; -> 0000 0000 1010 0101 1010 0101 1010 0101 - test_h_gr32 0x00a5a5a5 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_l_ind_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #8, @er0 ; shift right logical by eight, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llind8 - fail -.Llind8: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postinc_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #8, @er0+ ; shift right logical by eight, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llpostinc8 - fail -.Llpostinc8: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postdec_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #8, @er0- ; shift right logical by eight, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llpostdec8 - fail -.Llpostdec8: - mov #0xa5a5a5a5, @long_dest - -shlr_l_preinc_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shlr.l #8, @+er0 ; shift right logical by eight, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llpreinc8 - fail -.Llpreinc8: - mov #0xa5a5a5a5, @long_dest - -shlr_l_predec_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shlr.l #8, @-er0 ; shift right logical by eight, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llpredec8 - fail -.Llpredec8: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp2_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-8, er0 - shlr.l #8, @(8:2, er0) ; shift right logical by eight, disp2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-8 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Lldisp28 - fail -.Lldisp28: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp16_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shlr.l #8, @(44:16, er0) ; shift right logical by eight, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Lldisp168 - fail -.Lldisp168: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp32_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shlr.l #8, @(666:32, er0) ; shift right logical by eight, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Lldisp328 - fail -.Lldisp328: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs16_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #8, @long_dest:16 ; shift right logical by eight, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llabs168 - fail -.Llabs168: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs32_8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #8, @long_dest:32 ; shift right logical by eight, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x1178 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 - cmp.l #0x00a5a5a5, @long_dest - beq .Llabs328 - fail -.Llabs328: - mov #0xa5a5a5a5, @long_dest - -shlr_l_reg32_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #16, er0 ; shift right logical by sixteen, register -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - test_h_gr32 0x0000a5a5 er0 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -shlr_l_ind_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #16, @er0 ; shift right logical by sixteen, indirect -;;; .word 0x0104 -;;; .word 0x6908 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llind16 - fail -.Llind16: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postinc_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #16, @er0+ ; shift right logical by sixteen, postinc -;;; .word 0x0104 -;;; .word 0x6d08 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest+4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llpostinc16 - fail -.Llpostinc16: - mov #0xa5a5a5a5, @long_dest - -shlr_l_postdec_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest, er0 - shlr.l #16, @er0- ; shift right logical by sixteen, postdec -;;; .word 0x0106 -;;; .word 0x6d08 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-4 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llpostdec16 - fail -.Llpostdec16: - mov #0xa5a5a5a5, @long_dest - -shlr_l_preinc_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-4, er0 - shlr.l #16, @+er0 ; shift right logical by sixteen, preinc -;;; .word 0x0105 -;;; .word 0x6d08 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llpreinc16 - fail -.Llpreinc16: - mov #0xa5a5a5a5, @long_dest - -shlr_l_predec_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest+4, er0 - shlr.l #16, @-er0 ; shift right logical by sixteen, predec -;;; .word 0x0107 -;;; .word 0x6d08 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llpredec16 - fail -.Llpredec16: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp2_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-8, er0 - shlr.l #16, @(8:2, er0) ; shift right logical by 16, dest2 -;;; .word 0x0106 -;;; .word 0x6908 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-8 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Lldisp216 - fail -.Lldisp216: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp16_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-44, er0 - shlr.l #16, @(44:16, er0) ; shift right logical by 16, disp16 -;;; .word 0x0104 -;;; .word 0x6f08 -;;; .word 44 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-44 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Lldisp1616 - fail -.Lldisp1616: - mov #0xa5a5a5a5, @long_dest - -shlr_l_disp32_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - mov #long_dest-666, er0 - shlr.l #16, @(666:32, er0) ; shift right logical by 16, disp32 -;;; .word 0x7884 -;;; .word 0x6b28 -;;; .long 666 -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_h_gr32 long_dest-666 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Lldisp3216 - fail -.Lldisp3216: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs16_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #16, @long_dest:16 ; shift right logical by 16, abs16 -;;; .word 0x0104 -;;; .word 0x6b08 -;;; .word long_dest -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llabs1616 - fail -.Llabs1616: - mov #0xa5a5a5a5, @long_dest - -shlr_l_abs32_16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - shlr.l #16, @long_dest:32 ; shift right logical by 16, abs32 -;;; .word 0x0104 -;;; .word 0x6b28 -;;; .long long_dest -;;; .word 0x11f8 - - test_carry_set ; H=0 N=0 Z=0 V=0 C=1 - test_zero_clear - test_ovf_clear - test_neg_clear - - test_gr_a5a5 0 ; Make sure ALL general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ; 1010 0101 1010 0101 1010 0101 1010 0101 - ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 - cmp.l #0x0000a5a5, @long_dest - beq .Llabs3216 - fail -.Llabs3216: - mov #0xa5a5a5a5, @long_dest -.endif -.endif - pass - - exit 0 - diff --git a/sim/testsuite/sim/h8300/stack.s b/sim/testsuite/sim/h8300/stack.s deleted file mode 100644 index dd53445..0000000 --- a/sim/testsuite/sim/h8300/stack.s +++ /dev/null @@ -1,445 +0,0 @@ -# Hitachi H8 testcase 'ldc' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.data - .align 4 -stack: -.if (sim_cpu == h8300) - .fill 128, 2, 0 -.else - .fill 128, 4, 0 -.endif -stacktop: - - .text - -push_w: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero -.if (sim_cpu == h8300) - mov.w #stacktop, r7 -.else - mov.l #stacktop, er7 -.endif - push.w r0 ; a5a5 is negative - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - push.w r1 - push.w r2 - push.w r3 - - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - - mov @stacktop-2, r0 - test_gr_a5a5 0 - mov @stacktop-4, r0 - test_gr_a5a5 0 - mov @stacktop-6, r0 - test_gr_a5a5 0 - mov @stacktop-8, r0 - test_gr_a5a5 0 - - mov.w #1, r1 - mov.w #2, r2 - mov.w #3, r3 - mov.w #4, r4 - - push.w r1 ; #1 is non-negative, non-zero - test_cc_clear - - push.w r2 - push.w r3 - push.w r4 - - test_h_gr16 1 r1 - test_h_gr16 2 r2 - test_h_gr16 3 r3 - test_h_gr16 4 r4 - - mov @stacktop-10, r0 - test_h_gr16 1 r0 - mov @stacktop-12, r0 - test_h_gr16 2 r0 - mov @stacktop-14, r0 - test_h_gr16 3 r0 - mov @stacktop-16, r0 - test_h_gr16 4 r0 - -.if (sim_cpu == h8300) - test_h_gr16 4 r0 - test_h_gr16 1 r1 - test_h_gr16 2 r2 - test_h_gr16 3 r3 - test_h_gr16 4 r4 -;;; test_h_gr16 stacktop-16 r7 ; FIXME -.else - test_h_gr32 0xa5a50004 er0 - test_h_gr32 0xa5a50001 er1 - test_h_gr32 0xa5a50002 er2 - test_h_gr32 0xa5a50003 er3 - test_h_gr32 0xa5a50004 er4 - test_h_gr32 stacktop-16 er7 -.endif - test_gr_a5a5 5 - test_gr_a5a5 6 - -pop_w: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero -.if (sim_cpu == h8300) - mov.w #stacktop-16, r7 -.else - mov.l #stacktop-16, er7 -.endif - pop.w r4 - pop.w r3 - pop.w r2 - pop.w r1 ; Should set all flags zero - test_cc_clear - - test_h_gr16 1 r1 - test_h_gr16 2 r2 - test_h_gr16 3 r3 - test_h_gr16 4 r4 - - pop.w r4 - pop.w r3 - pop.w r2 - pop.w r1 ; a5a5 is negative - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 -.if (sim_cpu == h8300) -;;; test_h_gr16 stacktop r7 ; FIXME -.else - test_h_gr32 stacktop er7 -.endif - -.if (sim_cpu) ; non-zero means not h8300 -push_l: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - mov.l #stacktop, er7 - push.l er0 ; a5a5 is negative - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - push.l er1 - push.l er2 - push.l er3 - - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - - mov @stacktop-4, er0 - test_gr_a5a5 0 - mov @stacktop-8, er0 - test_gr_a5a5 0 - mov @stacktop-12, er0 - test_gr_a5a5 0 - mov @stacktop-16, er0 - test_gr_a5a5 0 - - mov #1, er1 - mov #2, er2 - mov #3, er3 - mov #4, er4 - - push.l er1 ; #1 is non-negative, non-zero - test_cc_clear - - push.l er2 - push.l er3 - push.l er4 - - test_h_gr32 1 er1 - test_h_gr32 2 er2 - test_h_gr32 3 er3 - test_h_gr32 4 er4 - - mov @stacktop-20, er0 - test_h_gr32 1 er0 - mov @stacktop-24, er0 - test_h_gr32 2 er0 - mov @stacktop-28, er0 - test_h_gr32 3 er0 - mov @stacktop-32, er0 - test_h_gr32 4 er0 - - test_h_gr32 4 er0 - test_h_gr32 1 er1 - test_h_gr32 2 er2 - test_h_gr32 3 er3 - test_h_gr32 4 er4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_h_gr32 stacktop-32 er7 - -pop_l: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - mov.l #stacktop-32, er7 - pop.l er4 - pop.l er3 - pop.l er2 - pop.l er1 ; Should set all flags zero - test_cc_clear - - test_h_gr32 1 er1 - test_h_gr32 2 er2 - test_h_gr32 3 er3 - test_h_gr32 4 er4 - - pop.l er4 - pop.l er3 - pop.l er2 - pop.l er1 ; a5a5 is negative - test_neg_set - test_carry_clear - test_zero_clear - test_ovf_clear - - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_h_gr32 stacktop er7 -.endif - - ;; Jump over subroutine - jmp _bsr - -bsr_jsr_func: - test_ccr 0 ; call should not affect ccr - mov.w #0, r0 - mov.w #1, r1 - mov.w #2, r2 - mov.w #3, r3 - mov.w #4, r4 - mov.w #5, r5 - mov.w #6, r6 - rts - -_bsr: set_grs_a5a5 -.if (sim_cpu == h8300) - mov.w #stacktop, r7 -.else - mov.l #stacktop, er7 -.endif - set_ccr_zero - bsr bsr_jsr_func - - test_h_gr16 0 r0 - test_h_gr16 1 r1 - test_h_gr16 2 r2 - test_h_gr16 3 r3 - test_h_gr16 4 r4 - test_h_gr16 5 r5 - test_h_gr16 6 r6 -.if (sim_cpu == h8300) -;;; test_h_gr16 stacktop, r7 ; FIXME -.else - test_h_gr32 stacktop, er7 -.endif - -_jsr: set_grs_a5a5 -.if (sim_cpu == h8300) - mov.w #stacktop, r7 -.else - mov.l #stacktop, er7 -.endif - set_ccr_zero - jsr bsr_jsr_func - - test_h_gr16 0 r0 - test_h_gr16 1 r1 - test_h_gr16 2 r2 - test_h_gr16 3 r3 - test_h_gr16 4 r4 - test_h_gr16 5 r5 - test_h_gr16 6 r6 -.if (sim_cpu == h8300) -;;; test_h_gr16 stacktop, r7 ; FIXME -.else - test_h_gr32 stacktop, er7 -.endif - -.if (sim_cpu) ; not zero ie. not h8300 -_trapa: - set_grs_a5a5 - mov.l #trap_handler, er7 ; trap vector - mov.l er7, @0x2c - mov.l #stacktop, er7 - set_ccr_zero - trapa #3 - - test_cc_clear ; ccr should be restored by rte - test_h_gr16 0x10 r0 - test_h_gr16 0x11 r1 - test_h_gr16 0x12 r2 - test_h_gr16 0x13 r3 - test_h_gr16 0x14 r4 - test_h_gr16 0x15 r5 - test_h_gr16 0x16 r6 - test_h_gr32 stacktop er7 -.endif - -.if (sim_cpu == h8sx) -_rtsl: ; Test rts/l insn. - set_grs_a5a5 - mov #0,r0l - mov #1,r1l - mov #2,r2l - mov #3,r3l - mov #4,r4l - mov #5,r5l - mov #6,r6l - mov #stacktop, er7 - - jsr rtsl1_func - test_h_gr32 0xa5a5a500 er0 - test_h_gr32 0xa5a5a501 er1 - test_h_gr32 0xa5a5a502 er2 - test_h_gr32 0xa5a5a503 er3 - test_h_gr32 0xa5a5a504 er4 - test_h_gr32 0xa5a5a505 er5 - test_h_gr32 0xa5a5a506 er6 - test_h_gr32 stacktop er7 - - jsr rtsl2_func - test_h_gr32 0xa5a5a500 er0 - test_h_gr32 0xa5a5a501 er1 - test_h_gr32 0xa5a5a502 er2 - test_h_gr32 0xa5a5a503 er3 - test_h_gr32 0xa5a5a504 er4 - test_h_gr32 0xa5a5a505 er5 - test_h_gr32 0xa5a5a506 er6 - test_h_gr32 stacktop er7 - - jsr rtsl3_func - test_h_gr32 0xa5a5a500 er0 - test_h_gr32 0xa5a5a501 er1 - test_h_gr32 0xa5a5a502 er2 - test_h_gr32 0xa5a5a503 er3 - test_h_gr32 0xa5a5a504 er4 - test_h_gr32 0xa5a5a505 er5 - test_h_gr32 0xa5a5a506 er6 - test_h_gr32 stacktop er7 - - jsr rtsl4_func - test_h_gr32 0xa5a5a500 er0 - test_h_gr32 0xa5a5a501 er1 - test_h_gr32 0xa5a5a502 er2 - test_h_gr32 0xa5a5a503 er3 - test_h_gr32 0xa5a5a504 er4 - test_h_gr32 0xa5a5a505 er5 - test_h_gr32 0xa5a5a506 er6 - test_h_gr32 stacktop er7 -.endif ; h8sx - - pass - - exit 0 - - ;; Handler for a software exception (trap). -trap_handler: - ;; Test the 'i' interrupt mask flag. - stc ccr, r0l - test_h_gr8 0x80, r0l - ;; Change the registers (so we know we've been here) - mov.w #0x10, r0 - mov.w #0x11, r1 - mov.w #0x12, r2 - mov.w #0x13, r3 - mov.w #0x14, r4 - mov.w #0x15, r5 - mov.w #0x16, r6 - ;; Change the ccr (which will be restored by RTE) - orc #0xff, ccr - rte - -.if (sim_cpu == h8sx) - ;; Functions for testing rts/l -rtsl1_func: ; Save and restore R0 - push.l er0 - ;; Now modify it, and verify the modification. - mov #0xfeedface, er0 - test_h_gr32 0xfeedface, er0 - ;; Then use rts/l to restore them and return. - rts/l er0 - -rtsl2_func: ; Save and restore R5 and R6 - push.l er5 - push.l er6 - ;; Now modify them, and verify the modification. - mov #0xdeadbeef, er5 - mov #0xfeedface, er6 - test_h_gr32 0xdeadbeef, er5 - test_h_gr32 0xfeedface, er6 - ;; Then use rts/l to restore them and return. - rts/l (er5-er6) - -rtsl3_func: ; Save and restore R4, R5, and R6 - push.l er4 - push.l er5 - push.l er6 - ;; Now modify them, and verify the modification. - mov #0xdeafcafe, er4 - mov #0xdeadbeef, er5 - mov #0xfeedface, er6 - test_h_gr32 0xdeafcafe, er4 - test_h_gr32 0xdeadbeef, er5 - test_h_gr32 0xfeedface, er6 - ;; Then use rts/l to restore them and return. - rts/l (er4-er6) - -rtsl4_func: ; Save and restore R0 - R3 - push.l er0 - push.l er1 - push.l er2 - push.l er3 - ;; Now modify them, and verify the modification. - mov #0xdadacafe, er0 - mov #0xfeedbeef, er1 - mov #0xdeadface, er2 - mov #0xf00dd00d, er3 - test_h_gr32 0xdadacafe, er0 - test_h_gr32 0xfeedbeef, er1 - test_h_gr32 0xdeadface, er2 - test_h_gr32 0xf00dd00d, er3 - ;; Then use rts/l to restore them and return. - rts/l (er0-er3) -.endif ; h8sx diff --git a/sim/testsuite/sim/h8300/stc.s b/sim/testsuite/sim/h8300/stc.s deleted file mode 100644 index 232bd5a..0000000 --- a/sim/testsuite/sim/h8300/stc.s +++ /dev/null @@ -1,401 +0,0 @@ -# Hitachi H8 testcase 'stc' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - .data -byte_dest1: - .byte 0 - .byte 0 -byte_dest2: - .byte 0 - .byte 0 -byte_dest3: - .byte 0 - .byte 0 -byte_dest4: - .byte 0 - .byte 0 -byte_dest5: - .byte 0 - .byte 0 -byte_dest6: - .byte 0 - .byte 0 -byte_dest7: - .byte 0 - .byte 0 -byte_dest8: - .byte 0 - .byte 0 -byte_dest9: - .byte 0 - .byte 0 -byte_dest10: - .byte 0 - .byte 0 -byte_dest11: - .byte 0 - .byte 0 -byte_dest12: - .byte 0 - .byte 0 - - start - -stc_ccr_reg8: - set_grs_a5a5 - set_ccr_zero - - ldc #0xff, ccr ; test value - stc ccr, r0h ; copy test value to r0h - - test_h_gr16 0xffa5 r0 ; ff in r0h, a5 in r0l -.if (sim_cpu) ; h/s/sx - test_h_gr32 0xa5a5ffa5 er0 ; ff in r0h, a5 everywhere else -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr -stc_exr_reg8: - set_grs_a5a5 - set_ccr_zero - - ldc #0x87, exr ; set exr to 0x87 - stc exr, r0l ; retrieve and check exr value - cmp.b #0x87, r0l - beq .L21 - fail -.L21: - test_h_gr32 0xa5a5a587 er0 ; Register 0 modified by test procedure. - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_ccr_abs16: - set_grs_a5a5 - set_ccr_zero - - ldc #0xff, ccr - stc ccr, @byte_dest1:16 ; abs16 dest - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_exr_abs16: - set_grs_a5a5 - set_ccr_zero - - ldc #0x87, exr - stc exr, @byte_dest2:16 ; abs16 dest - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_ccr_abs32: - set_grs_a5a5 - set_ccr_zero - - ldc #0xff, ccr - stc ccr, @byte_dest3:32 ; abs32 dest - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_exr_abs32: - set_grs_a5a5 - set_ccr_zero - - ldc #0x87, exr - stc exr, @byte_dest4:32 ; abs32 dest - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_ccr_disp16: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest5-1, er1 - ldc #0xff, ccr - stc ccr, @(1:16,er1) ; disp16 dest (5) - - test_h_gr32 byte_dest5-1, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_exr_disp16: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest6+1, er1 - ldc #0x87, exr - stc exr, @(-1:16,er1) ; disp16 dest (6) - - test_h_gr32 byte_dest6+1, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_ccr_disp32: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest7-1, er1 - ldc #0xff, ccr - stc ccr, @(1:32,er1) ; disp32 dest (7) - - test_h_gr32 byte_dest7-1, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_exr_disp32: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest8+1, er1 - ldc #0x87, exr - stc exr, @(-1:32,er1) ; disp16 dest (8) - - test_h_gr32 byte_dest8+1, er1 ; er1 still contains address - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_ccr_predecr: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest9+2, er1 - ldc #0xff, ccr - stc ccr, @-er1 ; predecr dest (9) - - test_h_gr32 byte_dest9 er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_exr_predecr: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest10+2, er1 - ldc #0x87, exr - stc exr, @-er1 ; predecr dest (10) - - test_h_gr32 byte_dest10, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_ccr_ind: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest11, er1 - ldc #0xff, ccr - stc ccr, @er1 ; postinc dest (11) - - test_h_gr32 byte_dest11, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_exr_ind: - set_grs_a5a5 - set_ccr_zero - - mov #byte_dest12, er1 - ldc #0x87, exr - stc exr, @er1, exr ; postinc dest (12) - - test_h_gr32 byte_dest12, er1 ; er1 still contains address - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - -.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx -stc_sbr_reg: - set_grs_a5a5 - set_ccr_zero - - mov #0xaaaaaaaa, er0 - ldc er0, sbr ; set sbr to 0xaaaaaaaa - stc sbr, er1 ; retreive and check sbr value - - test_h_gr32 0xaaaaaaaa er1 - test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -stc_vbr_reg: - set_grs_a5a5 - set_ccr_zero - - mov #0xaaaaaaaa, er0 - ldc er0, vbr ; set sbr to 0xaaaaaaaa - stc vbr, er1 ; retreive and check sbr value - - test_h_gr32 0xaaaaaaaa er1 - test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -check_results: - ;; Now check results - mov @byte_dest1, r0h - cmp.b #0xff, r0h - beq .L1 - fail - -.L1: mov @byte_dest2, r0h - cmp.b #0x87, r0h - beq .L2 - fail - -.L2: mov @byte_dest3, r0h - cmp.b #0xff, r0h - beq .L3 - fail - -.L3: mov @byte_dest4, r0h - cmp.b #0x87, r0h - beq .L4 - fail - -.L4: mov @byte_dest5, r0h - cmp.b #0xff, r0h - beq .L5 - fail - -.L5: mov @byte_dest6, r0h - cmp.b #0x87, r0h - beq .L6 - fail - -.L6: mov @byte_dest7, r0h - cmp.b #0xff, r0h - beq .L7 - fail - -.L7: mov @byte_dest8, r0h - cmp.b #0x87, r0h - beq .L8 - fail - -.L8: mov @byte_dest9, r0h - cmp.b #0xff, r0h - beq .L9 - fail - -.L9: mov @byte_dest10, r0h - cmp.b #0x87, r0h - beq .L10 - fail - -.L10: mov @byte_dest11, r0h - cmp.b #0xff, r0h - beq .L11 - fail - -.L11: mov @byte_dest12, r0h - cmp.b #0x87, r0h - beq .L12 - fail - -.L12: -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/subb.s b/sim/testsuite/sim/h8300/subb.s deleted file mode 100644 index 0183294..0000000 --- a/sim/testsuite/sim/h8300/subb.s +++ /dev/null @@ -1,289 +0,0 @@ -# Hitachi H8 testcase 'sub.b' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # sub.b #xx:8, rd ; - # sub.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx - # sub.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx - # sub.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx - # sub.b rs, rd ; 1 8 rs rd - # sub.b reg8, @erd ; 7 d rd ???? 1 8 rs ???? - # sub.b reg8, @erd+ ; 0 1 7 9 8 rd 3 rs - # sub.b reg8, @erd- ; 0 1 7 9 a rd 3 rs - # - - # Coming soon: - # sub.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx - # sub.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx - # sub.b reg8, @+erd ; 0 1 7 9 9 rd 3 rs - # sub.b reg8, @-erd ; 0 1 7 9 b rd 3 rs - # ... - -.data -pre_byte: .byte 0 -byte_dest: .byte 0xa5 -post_byte: .byte 0 - - start - -.if (0) ; Guess what? Sub.b immediate reg8 is illegal! -sub_b_imm8_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.b #xx:8,Rd - sub.b #5, r0l ; Immediate 8-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu == h8sx) -sub_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; sub.b #xx:8,@eRd - mov #byte_dest, er0 - sub.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst -;;; .word 0x7d00 -;;; .word 0xa105 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest, er0 ; er0 still contains address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa0, r0l - beq .L1 - fail -.L1: - -sub_b_imm8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; sub.b #xx:8,@eRd+ - mov #byte_dest, er0 - sub.b #5:8, @er0+ ; Immediate 8-bit src, reg post-incr dest -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xa105 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 post_byte, er0 ; er0 still contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x9b, r0l - beq .L2 - fail -.L2: - -sub_b_imm8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; sub.b #xx:8,@eRd- - mov #byte_dest, er0 - sub.b #5:8, @er0- ; Immediate 8-bit src, reg post-decr dest -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xa105 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 pre_byte, er0 ; er0 still contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x96, r0l - beq .L3 - fail -.L3: - -.endif - -sub_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.b Rs,Rd - mov.b #5, r0h - sub.b r0h, r0l ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0x05a0 r0 ; sub result: a5 - 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -sub_b_reg8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; sub.b rs8,@eRd ; Subx to register indirect - mov #byte_dest, er0 - mov #5, r1l - sub.b r1l, @er0 ; reg8 src, reg indirect dest -;;; .word 0x7d00 -;;; .word 0x1890 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x91, r0l - beq .L4 - fail -.L4: - -sub_b_reg8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; sub.b rs8,@eRd+ ; Subx to register indirect - mov #byte_dest, er0 - mov #5, r1l - sub.b r1l, @er0+ ; reg8 src, reg indirect dest -;;; .word 0x0179 -;;; .word 0x8039 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 post_byte er0 ; er0 still contains address plus one - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x8c, r0l - beq .L5 - fail -.L5: - -sub_b_reg8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; sub.b rs8,@eRd- ; Subx to register indirect - mov #byte_dest, er0 - mov #5, r1l - sub.b r1l, @er0- ; reg8 src, reg indirect dest -;;; .word 0x0179 -;;; .word 0xa039 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 pre_byte er0 ; er0 still contains address minus one - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x87, r0l - beq .L6 - fail -.L6: - -.endif - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/subl.s b/sim/testsuite/sim/h8300/subl.s deleted file mode 100644 index 7f62f11..0000000 --- a/sim/testsuite/sim/h8300/subl.s +++ /dev/null @@ -1,91 +0,0 @@ -# Hitachi H8 testcase 'sub.l' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) ; -sub_l_imm3: ; 3-bit immediate mode only for h8sx - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.l #xx:3,eRd ; Immediate 3-bit operand - sub.l #7:3, er0 - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -sub_l_imm16: ; sub immediate 16-bit value - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.l #xx:16,eRd ; Immediate 16-bit operand - sub.l #0x1111:16, er0 - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111 - test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.endif - -sub_l_imm32: - ;; sub.l immediate not available in h8300 mode. - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.l #xx:32,Rd - sub.l #0x11111111, er0 ; Immediate 32-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -sub.l.reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; add.l Rs,Rd - mov.l #0x11111111, er1 - sub.l er1, er0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111 - test_h_gr32 0x11111111 er1 - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/subs.s b/sim/testsuite/sim/h8300/subs.s deleted file mode 100644 index 1bb5eea..0000000 --- a/sim/testsuite/sim/h8300/subs.s +++ /dev/null @@ -1,74 +0,0 @@ -# Hitachi H8 testcase 'subs' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # subs #1, erd ; 1 b 0 0erd - # subs #2, erd ; 1 b 8 0erd - # subs #4, erd ; 1 b 9 0erd - # - - start -.if (sim_cpu) ; 32 bit only -subs_1: - set_grs_a5a5 - set_ccr_zero - - subs #1, er0 - - test_cc_clear ; subs should not affect any condition codes - test_h_gr32 0xa5a5a5a4 er0 ; result of subs #1 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subs_2: - set_grs_a5a5 - set_ccr_zero - - subs #2, er0 - - test_cc_clear ; subs should not affect any condition codes - test_h_gr32 0xa5a5a5a3 er0 ; result of subs #2 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subs_4: - set_grs_a5a5 - set_ccr_zero - - subs #4, er0 - - test_cc_clear ; subs should not affect any condition codes - test_h_gr32 0xa5a5a5a1 er0 ; result of subs #4 - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass -.endif - exit 0 diff --git a/sim/testsuite/sim/h8300/subw.s b/sim/testsuite/sim/h8300/subw.s deleted file mode 100644 index 2370250..0000000 --- a/sim/testsuite/sim/h8300/subw.s +++ /dev/null @@ -1,78 +0,0 @@ -# Hitachi H8 testcase 'sub.w' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start -.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx -sub_w_imm3: ; sub.w immediate not available in h8300 mode. - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.w #xx:3,Rd ; Immediate 3-bit operand - sub.w #7:3, r0 - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa59e r0 ; sub result: a5a5 - 7 - test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -sub_w_imm16: ; sub.w immediate not available in h8300 mode. - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.w #xx:16,Rd - sub.w #0x111, r0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111 - test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -sub.w.reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; sub.w Rs,Rd - mov.w #0x111, r1 - sub.w r1, r0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111 - test_h_gr16 0x0111 r1 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111 - test_h_gr32 0xa5a50111 er1 -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/subx.s b/sim/testsuite/sim/h8300/subx.s deleted file mode 100644 index 78656bc..0000000 --- a/sim/testsuite/sim/h8300/subx.s +++ /dev/null @@ -1,1010 +0,0 @@ -# Hitachi H8 testcase 'subx' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # subx.b #xx:8, rd8 ; b rd8 xxxxxxxx - # subx.b #xx:8, @erd ; 7 d erd ???? b ???? xxxxxxxx - # subx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? b ???? xxxxxxxx - # subx.b rs8, rd8 ; 1 e rs8 rd8 - # subx.b rs8, @erd ; 7 d erd ???? 1 e rs8 ???? - # subx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 1 e rs8 ???? - # subx.b @ers, rd8 ; 7 c ers ???? 1 e ???? rd8 - # subx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 1 e ???? rd8 - # subx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 3 ???? - # subx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 3 ???? - # - # word ops - # long ops - -.data -byte_src: .byte 0x5 -byte_dest: .byte 0 - - .align 2 -word_src: .word 0x505 -word_dest: .word 0 - - .align 4 -long_src: .long 0x50505 -long_dest: .long 0 - - - start - -subx_b_imm8_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; subx.b #xx:8,Rd ; Subx with carry initially zero. - subx.b #5, r0l ; Immediate 8-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_b_imm8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; subx.b #xx:8,Rd ; Subx with carry initially one. - set_carry_flag - subx.b #4, r0l ; Immediate 8-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0xa5a0 r0 ; sub result: a5 - (4 + 1) -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - (4 + 1) -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -subx_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.b #xx:8,@eRd ; Subx to register indirect - mov #byte_dest, er0 - mov.b #0xa5, @er0 - set_ccr_zero - subx.b #5, @er0 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 still contains subress - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - cmp.b #0xa0, @byte_dest - beq .Lb1 - fail -.Lb1: - -subx_b_imm8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.b #xx:8,@eRd- ; Subx to register post-decrement - mov #byte_dest, er0 - mov.b #0xa5, @er0 - set_ccr_zero - subx.b #5, @er0- - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest-1 er0 ; er0 contains subress minus one - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - cmp.b #0xa0, @byte_dest - beq .Lb2 - fail -.Lb2: -.endif - -subx_b_reg8_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.b Rs,Rd ; subx with carry initially zero - mov.b #5, r0h - set_ccr_zero - subx.b r0h, r0l ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0x05a0 r0 ; sub result: a5 - 5 -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5 -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_b_reg8_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.b Rs,Rd ; subx with carry initially one - mov.b #4, r0h - set_ccr_zero - set_carry_flag - subx.b r0h, r0l ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0x04a0 r0 ; sub result: a5 - (4 + 1) -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a504a0 er0 ; sub result: a5 - (4 + 1) -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -subx_b_reg8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.b rs8,@eRd ; Subx to register indirect - mov #byte_dest, er0 - mov.b #0xa5, @er0 - mov.b #5, r1l - set_ccr_zero - subx.b r1l, @er0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 still contains subress - test_h_gr32 0xa5a5a505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - cmp.b #0xa0, @byte_dest - beq .Lb3 - fail -.Lb3: - -subx_b_reg8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.b rs8,@eRd- ; Subx to register post-decrement - mov #byte_dest, er0 - mov.b #0xa5, @er0 - mov.b #5, r1l - set_ccr_zero - subx.b r1l, @er0- - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest-1 er0 ; er0 contains subress minus one - test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - cmp.b #0xa0, @byte_dest - beq .Lb4 - fail -.Lb4: - -subx_b_rsind_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.b @eRs,rd8 ; Subx from reg indirect to reg - mov #byte_src, er0 - set_ccr_zero - subx.b @er0, r1l - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_src er0 ; er0 still contains subress - test_h_gr32 0xa5a5a5a0 er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_b_rspostdec_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.b @eRs-,rd8 ; Subx to register post-decrement - mov #byte_src, er0 - set_ccr_zero - subx.b @er0-, r1l - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_src-1 er0 ; er0 contains subress minus one - test_h_gr32 0xa5a5a5a0 er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_b_rsind_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.b @eRs,rd8 ; Subx from reg indirect to reg - mov #byte_src, er0 - mov #byte_dest, er1 - mov.b #0xa5, @er1 - set_ccr_zero - subx.b @er0, @er1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_src er0 ; er0 still contains src subress - test_h_gr32 byte_dest er1 ; er1 still contains dst subress - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the sub to memory. - cmp.b #0xa0, @byte_dest - beq .Lb5 - fail -.Lb5: - -subx_b_rspostdec_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - mov #byte_src, er0 - mov #byte_dest, er1 - mov.b #0xa5, @er1 - set_ccr_zero - ;; subx.b @eRs-,@erd- ; Subx post-decrement to post-decrement - subx.b @er0-, @er1- - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_src-1 er0 ; er0 contains src subress minus one - test_h_gr32 byte_dest-1 er1 ; er1 contains dst subress minus one - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the sub to memory. - cmp.b #0xa0, @byte_dest - beq .Lb6 - fail -.Lb6: - -subx_w_imm16_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; subx.w #xx:16,Rd ; Subx with carry initially zero. - subx.w #0x505, r0 ; Immediate 16-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0xa0a0 r0 ; sub result: 0xa5a5 + 0x505 - test_h_gr32 0xa5a5a0a0 er0 ; sub result: 0xa5a5 + 0x505 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_w_imm16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; subx.w #xx:16,Rd ; Subx with carry initially one. - set_carry_flag - subx.w #0x504, r0 ; Immediate 16-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr16 0xa0a0 r0 ; sub result: 0xa5a5 + 0x505 + 1 - test_h_gr32 0xa5a5a0a0 er0 ; sub result: 0xa5a5 + 0x505 + 1 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_w_imm16_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.w #xx:16,@eRd ; Subx to register indirect - mov #word_dest, er0 - mov.w #0xa5a5, @er0 - set_ccr_zero - subx.w #0x505, @er0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 word_dest er0 ; er0 still contains subress - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - cmp.w #0xa0a0, @word_dest - beq .Lw1 - fail -.Lw1: - -subx_w_imm16_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.w #xx:16,@eRd- ; Subx to register post-decrement - mov #word_dest, er0 - mov.w #0xa5a5, @er0 - set_ccr_zero - subx.w #0x505, @er0- - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 ; er0 contains subress minus one - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - cmp.w #0xa0a0, @word_dest - beq .Lw2 - fail -.Lw2: - -subx_w_reg16_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.w Rs,Rd ; subx with carry initially zero - mov.w #0x505, e0 - set_ccr_zero - subx.w e0, r0 ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0x0505a0a0 er0 ; sub result: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_w_reg16_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.w Rs,Rd ; subx with carry initially one - mov.w #0x504, e0 - set_ccr_zero - set_carry_flag - subx.w e0, r0 ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0x0504a0a0 er0 ; sub result: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_w_reg16_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.w rs8,@eRd ; Subx to register indirect - mov #word_dest, er0 - mov.w #0xa5a5, @er0 - mov.w #0x505, r1 - set_ccr_zero - subx.w r1, @er0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 word_dest er0 ; er0 still contains subress - test_h_gr32 0xa5a50505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - cmp.w #0xa0a0, @word_dest - beq .Lw3 - fail -.Lw3: - -subx_w_reg16_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.w rs8,@eRd- ; Subx to register post-decrement - mov #word_dest, er0 - mov.w #0xa5a5, @er0 - mov.w #0x505, r1 - set_ccr_zero - subx.w r1, @er0- - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 word_dest-2 er0 ; er0 contains subress minus one - test_h_gr32 0xa5a50505 er1 ; er1 contains the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - cmp.w #0xa0a0, @word_dest - beq .Lw4 - fail -.Lw4: - -subx_w_rsind_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.w @eRs,rd8 ; Subx from reg indirect to reg - mov #word_src, er0 - set_ccr_zero - subx.w @er0, r1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 word_src er0 ; er0 still contains subress - test_h_gr32 0xa5a5a0a0 er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_w_rspostdec_reg16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.w @eRs-,rd8 ; Subx to register post-decrement - mov #word_src, er0 - set_ccr_zero - subx.w @er0-, r1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 word_src-2 er0 ; er0 contains subress minus one - test_h_gr32 0xa5a5a0a0 er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_w_rsind_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.w @eRs,rd8 ; Subx from reg indirect to reg - mov #word_src, er0 - mov #word_dest, er1 - mov.w #0xa5a5, @er1 - set_ccr_zero - subx.w @er0, @er1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 word_src er0 ; er0 still contains src subress - test_h_gr32 word_dest er1 ; er1 still contains dst subress - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the sub to memory. - cmp.w #0xa0a0, @word_dest - beq .Lw5 - fail -.Lw5: - -subx_w_rspostdec_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.w @eRs-,rd8 ; Subx to register post-decrement - mov #word_src, er0 - mov #word_dest, er1 - mov.w #0xa5a5, @er1 - set_ccr_zero - subx.w @er0-, @er1- - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 word_src-2 er0 ; er0 contains src subress minus one - test_h_gr32 word_dest-2 er1 ; er1 contains dst subress minus one - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the sub to memory. - cmp.w #0xa0a0, @word_dest - beq .Lw6 - fail -.Lw6: - -subx_l_imm32_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; subx.l #xx:32,Rd ; Subx with carry initially zero. - subx.l #0x50505, er0 ; Immediate 32-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0xa5a0a0a0 er0 ; sub result: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_l_imm32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; subx.l #xx:32,Rd ; Subx with carry initially one. - set_carry_flag - subx.l #0x50504, er0 ; Immediate 32-bit operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0xa5a0a0a0 er0 ; sub result: - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_l_imm32_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.l #xx:32,@eRd ; Subx to register indirect - mov #long_dest, er0 - mov.l #0xa5a5a5a5, @er0 - set_ccr_zero - subx.l #0x50505, @er0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 long_dest er0 ; er0 still contains subress - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - cmp.l #0xa5a0a0a0, @long_dest - beq .Ll1 - fail -.Ll1: - -subx_l_imm32_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.l #xx:32,@eRd- ; Subx to register post-decrement - mov #long_dest, er0 - mov.l #0xa5a5a5a5, @er0 - set_ccr_zero - subx.l #0x50505, @er0- - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 long_dest-4 er0 ; er0 contains subress minus one - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - cmp.l #0xa5a0a0a0, @long_dest - beq .Ll2 - fail -.Ll2: - -subx_l_reg32_0: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.l Rs,Rd ; subx with carry initially zero - mov.l #0x50505, er0 - set_ccr_zero - subx.l er0, er1 ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0x50505 er0 ; sub load - test_h_gr32 0xa5a0a0a0 er1 ; sub result: - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_l_reg32_1: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.l Rs,Rd ; subx with carry initially one - mov.l #0x50504, er0 - set_ccr_zero - set_carry_flag - subx.l er0, er1 ; Register operand - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 0x50504 er0 ; sub result: - test_h_gr32 0xa5a0a0a0 er1 ; sub result: - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_l_reg32_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.l rs8,@eRd ; Subx to register indirect - mov #long_dest, er0 - mov.l er1, @er0 - mov.l #0x50505, er1 - set_ccr_zero - subx.l er1, @er0 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 long_dest er0 ; er0 still contains subress - test_h_gr32 0x50505 er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - cmp.l #0xa5a0a0a0, @long_dest - beq .Ll3 - fail -.Ll3: - -subx_l_reg32_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.l rs8,@eRd- ; Subx to register post-decrement - mov #long_dest, er0 - mov.l er1, @er0 - mov.l #0x50505, er1 - set_ccr_zero - subx.l er1, @er0- - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 long_dest-4 er0 ; er0 contains subress minus one - test_h_gr32 0x50505 er1 ; er1 contains the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the sub to memory. - cmp.l #0xa5a0a0a0, @long_dest - beq .Ll4 - fail -.Ll4: - -subx_l_rsind_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.l @eRs,rd8 ; Subx from reg indirect to reg - mov #long_src, er0 - set_ccr_zero - subx.l @er0, er1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 long_src er0 ; er0 still contains subress - test_h_gr32 0xa5a0a0a0 er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_l_rspostdec_reg32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.l @eRs-,rd8 ; Subx to register post-decrement - mov #long_src, er0 - set_ccr_zero - subx.l @er0-, er1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 long_src-4 er0 ; er0 contains subress minus one - test_h_gr32 0xa5a0a0a0 er1 ; er1 contains the sum - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -subx_l_rsind_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.l @eRs,rd8 ; Subx from reg indirect to reg - mov #long_src, er0 - mov #long_dest, er1 - mov.l er2, @er1 - set_ccr_zero - subx.l @er0, @er1 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 long_src er0 ; er0 still contains src subress - test_h_gr32 long_dest er1 ; er1 still contains dst subress - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the sub to memory. - cmp.l #0xa5a0a0a0, @long_dest - beq .Ll5 - fail -.Ll5: - -subx_l_rspostdec_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - - ;; subx.l @eRs-,rd8 ; Subx to register post-decrement - mov #long_src, er0 - mov #long_dest, er1 - mov.l er2, @er1 - set_ccr_zero - subx.l @er0-, @er1- - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 long_src-4 er0 ; er0 contains src subress minus one - test_h_gr32 long_dest-4 er1 ; er1 contains dst subress minus one - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - ;; Now check the result of the sub to memory. - cmp.l #0xa5a0a0a0, @long_dest - beq .Ll6 - fail -.Ll6: -.endif - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/tas.s b/sim/testsuite/sim/h8300/tas.s deleted file mode 100644 index 60bea92..0000000 --- a/sim/testsuite/sim/h8300/tas.s +++ /dev/null @@ -1,80 +0,0 @@ -# Hitachi H8 testcase 'tas' -# mach(): h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - .data -byte_dst: .byte 0 - - start - -tas_ind: ; test and set instruction - set_grs_a5a5 - mov #byte_dst, er4 - set_ccr_zero - ;; tas @erd - tas @er4 ; should set zero flag - test_carry_clear - test_neg_clear - test_ovf_clear - test_zero_set - - tas @er4 ; should clear zero, set neg - test_carry_clear - test_neg_set - test_ovf_clear - test_zero_clear - - test_gr_a5a5 0 ; general regs have not been modified - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_h_gr32 byte_dst, er4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - mov.b @byte_dst, r0l ; test variable has MSB set? - test_h_gr8 0x80 r0l - -.if (sim_cpu == h8sx) ; h8sx can use any register for tas -tas_h8sx: ; test and set instruction - mov.b #0, @byte_dst - set_grs_a5a5 - mov #byte_dst, er3 - set_ccr_zero - ;; tas @erd - tas @er3 ; should set zero flag - test_carry_clear - test_neg_clear - test_ovf_clear - test_zero_set - - tas @er3 ; should clear zero, set neg - test_carry_clear - test_neg_set - test_ovf_clear - test_zero_clear - - test_gr_a5a5 0 ; general regs have not been modified - test_gr_a5a5 1 - test_gr_a5a5 2 - test_h_gr32 byte_dst, er3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - mov.b @byte_dst, r0l ; test variable has MSB set? - test_h_gr8 0x80 r0l -.endif ; h8sx - - pass - exit 0 diff --git a/sim/testsuite/sim/h8300/testutils.inc b/sim/testsuite/sim/h8300/testutils.inc deleted file mode 100644 index 9c2c27a..0000000 --- a/sim/testsuite/sim/h8300/testutils.inc +++ /dev/null @@ -1,351 +0,0 @@ -# Support macros for the Hitachi H8 assembly test cases. - -; Set up a minimal machine state - .macro start - .equ h8300, 0 - .equ h8300h, 1 - .equ h8300s, 2 - .equ h8sx, 3 - .if (sim_cpu == h8300s) - .h8300s - .else - .if (sim_cpu == h8300h) - .h8300h - .else - .if (sim_cpu == h8sx) - .h8300sx - .endif - .endif - .endif - - .text - .align 2 - .global _start -_start: - jmp _main - - .data - .align 2 - .global pass_str - .global fail_str - .global ok_str - .global pass_loc - .global fail_loc - .global ok_loc -pass_str: - .ascii "pass\n" -fail_str: - .ascii "fail\n" -ok_str: - .ascii "ok\n" -pass_loc16: - .word pass_str -pass_loc32: - .long pass_str -fail_loc16: - .word fail_str -fail_loc32: - .long fail_str -ok_loc16: - .word ok_str -ok_loc32: - .long ok_str - .text - - .global _write_and_exit -_write_and_exit: -;ssize_t write(int fd, const void *buf, size_t count); -;Integer arguments have to be zero extended. -.if (sim_cpu) -#if __INT_MAX__ == 32767 - extu.l er0 -#endif -.endif - jsr @@0xc7 - mov #0, r0 - jmp _exit - - .global _exit -_exit: - mov.b r0l, r0h - mov.w #0xdead, r1 - mov.w #0xbeef, r2 - sleep - - .global _main -_main: - .endm - - -; Exit with an exit code - .macro exit code - mov.w #\code, r0 - jmp _exit - .endm - -; Output "pass\n" - .macro pass - mov.w #0, r0 ; fd == stdout -.if (sim_cpu == h8300) - mov.w #pass_str, r1 ; buf == "pass\n" - mov.w #5, r2 ; len == 5 -.else - mov.l #pass_str, er1 ; buf == "pass\n" - mov.l #5, er2 ; len == 5 -.endif - jmp _write_and_exit - .endm - -; Output "fail\n" - .macro fail - mov.w #0, r0 ; fd == stdout -.if (sim_cpu == h8300) - mov.w #fail_str, r1 ; buf == "fail\n" - mov.w #5, r2 ; len == 5 -.else - mov.l #fail_str, er1 ; buf == "fail\n" - mov.l #5, er2 ; len == 5 -.endif - jmp _write_and_exit - .endm - - -; Load an 8-bit immediate value into a general register -; (reg must be r0l - r7l or r0h - r7h) - .macro mvi_h_gr8 val reg - mov.b #\val, \reg - .endm - -; Load a 16-bit immediate value into a general register -; (reg must be r0 - r7) - .macro mvi_h_gr16 val reg - mov.w #\val, \reg - .endm - -; Load a 32-bit immediate value into a general register -; (reg must be er0 - er7) - .macro mvi_h_gr32 val reg - mov.l #\val, \reg - .endm - -; Test the value of an 8-bit immediate against a general register -; (reg must be r0l - r7l or r0h - r7h) - .macro test_h_gr8 val reg - cmp.b #\val, \reg - beq .Ltest_gr8\@ - fail -.Ltest_gr8\@: - .endm - -; Test the value of a 16-bit immediate against a general register -; (reg must be r0 - r7) - .macro test_h_gr16 val reg h=h l=l - .if (sim_cpu == h8300) - test_h_gr8 (\val >> 8) \reg\h - test_h_gr8 (\val & 0xff) \reg\l - .else - cmp.w #\val, \reg - beq .Ltest_gr16\@ - fail -.Ltest_gr16\@: - .endif - .endm - -; Test the value of a 32-bit immediate against a general register -; (reg must be er0 - er7) - .macro test_h_gr32 val reg - cmp.l #\val, \reg - beq .Ltest_gr32\@ - fail -.Ltest_gr32\@: - .endm - -; Set a general register to the fixed pattern 'a5a5a5a5' - .macro set_gr_a5a5 reg - .if (sim_cpu == 0) - ; h8300 - mov.w #0xa5a5, r\reg - .else - mov.l #0xa5a5a5a5, er\reg - .endif - .endm - -; Set all general registers to the fixed pattern 'a5a5a5a5' - .macro set_grs_a5a5 - .if (sim_cpu == 0) - ; h8300 - mov.w #0xa5a5, r0 - mov.w #0xa5a5, r1 - mov.w #0xa5a5, r2 - mov.w #0xa5a5, r3 - mov.w #0xa5a5, r4 - mov.w #0xa5a5, r5 - mov.w #0xa5a5, r6 - mov.w #0xa5a5, r7 - .else - mov.l #0xa5a5a5a5, er0 - mov.l #0xa5a5a5a5, er1 - mov.l #0xa5a5a5a5, er2 - mov.l #0xa5a5a5a5, er3 - mov.l #0xa5a5a5a5, er4 - mov.l #0xa5a5a5a5, er5 - mov.l #0xa5a5a5a5, er6 - mov.l #0xa5a5a5a5, er7 - .endif - .endm - -; Test that a general register contains the fixed pattern 'a5a5a5a5' - .macro test_gr_a5a5 reg - .if (sim_cpu == 0) - ; h8300 - test_h_gr16 0xa5a5 r\reg - .else - test_h_gr32 0xa5a5a5a5 er\reg - .endif - .endm - -; Test that all general regs contain the fixed pattern 'a5a5a5a5' - .macro test_grs_a5a5 - test_gr_a5a5 0 - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - .endm - -; Set condition code register to an explicit value - .macro set_ccr val - ldc #\val, ccr - .endm - -; Set all condition code flags to zero - .macro set_ccr_zero - ldc #0, ccr - .endm - -; Set carry flag true - .macro set_carry_flag - orc #1, ccr - .endm - -; Clear carry flag - .macro clear_carry_flag - andc 0xfe, ccr - .endm - -; Set zero flag true - .macro set_zero_flag - orc #4, ccr - .endm - -; Clear zero flag - .macro clear_zero_flag - andc 0xfb, ccr - .endm - -; Set neg flag true - .macro set_neg_flag - orc #8, ccr - .endm - -; Clear neg flag - .macro clear_neg_flag - andc 0xf7, ccr - .endm - -; Test that carry flag is clear - .macro test_carry_clear - bcc .Lcc\@ - fail ; carry flag not clear -.Lcc\@: - .endm - -; Test that carry flag is set - .macro test_carry_set - bcs .Lcs\@ - fail ; carry flag not clear -.Lcs\@: - .endm - -; Test that overflow flag is clear - .macro test_ovf_clear - bvc .Lvc\@ - fail ; overflow flag not clear -.Lvc\@: - .endm - -; Test that overflow flag is set - .macro test_ovf_set - bvs .Lvs\@ - fail ; overflow flag not clear -.Lvs\@: - .endm - -; Test that zero flag is clear - .macro test_zero_clear - bne .Lne\@ - fail ; zero flag not clear -.Lne\@: - .endm - -; Test that zero flag is set - .macro test_zero_set - beq .Leq\@ - fail ; zero flag not clear -.Leq\@: - .endm - -; Test that neg flag is clear - .macro test_neg_clear - bpl .Lneg\@ - fail ; negative flag not clear -.Lneg\@: - .endm - -; Test that neg flag is set - .macro test_neg_set - bmi .Lneg\@ - fail ; negative flag not clear -.Lneg\@: - .endm - -; Test ccr against an explicit value - .macro test_ccr val - .data -tccr\@: .byte 0 - .text - mov.b r0l, @tccr\@ - stc ccr, r0l - cmp.b #\val, r0l - bne .Ltcc\@ - fail -.Ltcc\@: - mov.b @tccr\@, r0l - .endm - -; Test that all (accessable) condition codes are clear - .macro test_cc_clear - test_carry_clear - test_ovf_clear - test_zero_clear - test_neg_clear - ; leaves H, I, U, and UI untested - .endm - -; Compare memory, fail if not equal (h8sx only, len > 0). - .macro memcmp src dst len - mov.l #\src, er5 - mov.l #\dst, er6 - mov.l #\len, er4 -.Lmemcmp_\@: - cmp.b @er5+, @er6+ - beq .Lmemcmp2_\@ - fail -.Lmemcmp2_\@: - dec.l #1, er4 - bne .Lmemcmp_\@ - .endm - diff --git a/sim/testsuite/sim/h8300/xorb.s b/sim/testsuite/sim/h8300/xorb.s deleted file mode 100644 index 337c396..0000000 --- a/sim/testsuite/sim/h8300/xorb.s +++ /dev/null @@ -1,378 +0,0 @@ -# Hitachi H8 testcase 'xor.b' -# mach(): all -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - # Instructions tested: - # xor.b #xx:8, rd ; d rd xxxxxxxx - # xor.b #xx:8, @erd ; 7 d rd ???? d ???? xxxxxxxx - # xor.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx - # xor.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx - # xor.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx - # xor.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx - # xor.b rs, rd ; 1 5 rs rd - # xor.b reg8, @erd ; 7 d rd ???? 1 5 rs ???? - # xor.b reg8, @erd+ ; 0 1 7 9 8 rd 5 rs - # xor.b reg8, @erd- ; 0 1 7 9 a rd 5 rs - # xor.b reg8, @+erd ; 0 1 7 9 9 rd 5 rs - # xor.b reg8, @-erd ; 0 1 7 9 b rd 5 rs - # - # xorc #xx:8, ccr ; - # xorc #xx:8, exr ; - - # Coming soon: - # ... - -.data -pre_byte: .byte 0 -byte_dest: .byte 0xa5 -post_byte: .byte 0 - - start - -xor_b_imm8_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.b #xx:8,Rd - xor.b #0xff, r0l ; Immediate 8-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xa55a r0 ; xor result: a5 ^ ff -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5a55a er0 ; xor result: a5 ^ ff -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -xor_b_imm8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xor.b #xx:8,@eRd - mov #byte_dest, er0 - xor.b #0xff:8, @er0 ; Immediate 8-bit src, reg indirect dst -;;; .word 0x7d00 -;;; .word 0xd0ff - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 byte_dest, er0 ; er0 still contains address - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the xor to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x5a, r0l - beq .L1 - fail -.L1: - -xor_b_imm8_postinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xor.b #xx:8,@eRd+ - mov #byte_dest, er0 - xor.b #0xff:8, @er0+ ; Immediate 8-bit src, reg indirect dst -;;; .word 0x0174 -;;; .word 0x6c08 -;;; .word 0xd0ff - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 post_byte, er0 ; er0 contains address plus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the xor to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L2 - fail -.L2: - -xor_b_imm8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xor.b #xx:8,@eRd- - mov #byte_dest, er0 - xor.b #0xff:8, @er0- ; Immediate 8-bit src, reg indirect dst -;;; .word 0x0176 -;;; .word 0x6c08 -;;; .word 0xd0ff - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 pre_byte, er0 ; er0 contains address minus one - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the xor to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x5a, r0l - beq .L3 - fail -.L3: - - -.endif - -xor_b_reg8_reg8: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.b Rs,Rd - mov.b #0xff, r0h - xor.b r0h, r0l ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0xff5a r0 ; xor result: a5 ^ ff -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a5ff5a er0 ; xor result: a5 ^ ff -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8sx) -xor_b_reg8_rdind: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xor.b rs8,@eRd ; xor reg8 to register indirect - mov #byte_dest, er0 - mov #0xff, r1l - xor.b r1l, @er0 ; reg8 src, reg indirect dest -;;; .word 0x7d00 -;;; .word 0x1590 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 byte_dest er0 ; er0 still contains address - test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L4 - fail -.L4: - -xor_b_reg8_rdpostinc: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xor.b rs8,@eRd+ ; xor reg8 to register post-increment - mov #byte_dest, er0 - mov #0xff, r1l - xor.b r1l, @er0+ ; reg8 src, reg post-increment dest -;;; .word 0x0179 -;;; .word 0x8059 - - test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_clear - - test_h_gr32 post_byte er0 ; er0 contains address plus one - test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0x5a, r0l - beq .L5 - fail -.L5: - -xor_b_reg8_rdpostdec: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xor.b rs8,@eRd- ; xor reg8 to register post-decrement - mov #byte_dest, er0 - mov #0xff, r1l - xor.b r1l, @er0- ; reg8 src, reg indirect dest -;;; .word 0x0179 -;;; .word 0xa059 - - test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 - test_ovf_clear - test_zero_clear - test_neg_set - - test_h_gr32 pre_byte er0 ; er0 contains address minus one - test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - ;; Now check the result of the or to memory. - sub.b r0l, r0l - mov.b @byte_dest, r0l - cmp.b #0xa5, r0l - beq .L6 - fail -.L6: - -.endif ; h8sx - -xorc_imm8_ccr: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - set_ccr_zero - - ;; xorc #xx:8,ccr - - test_neg_clear - xorc #0x8, ccr ; Immediate 8-bit operand (neg flag) - test_neg_set - xorc #0x8, ccr - test_neg_clear - - test_zero_clear - xorc #0x4, ccr ; Immediate 8-bit operand (zero flag) - test_zero_set - xorc #0x4, ccr - test_zero_clear - - test_ovf_clear - xorc #0x2, ccr ; Immediate 8-bit operand (overflow flag) - test_ovf_set - xorc #0x2, ccr - test_ovf_clear - - test_carry_clear - xorc #0x1, ccr ; Immediate 8-bit operand (carry flag) - test_carry_set - xorc #0x1, ccr - test_carry_clear - - test_gr_a5a5 0 ; Make sure other general regs not disturbed - test_gr_a5a5 1 - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr -xorc_imm8_exr: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ldc #0, exr - stc exr, r0l - test_h_gr8 0, r0l - - set_ccr_zero - ;; xorc #xx:8,exr - - xorc #0x80, exr - test_cc_clear - stc exr, r0l - test_h_gr8 0x80, r0l - xorc #0x80, exr - stc exr, r0l - test_h_gr8 0, r0l - - xorc #0x4, exr - stc exr, r0l - test_h_gr8 4, r0l - xorc #0x4, exr - stc exr, r0l - test_h_gr8 0, r0l - - xorc #0x2, exr ; Immediate 8-bit operand (overflow flag) - stc exr, r0l - test_h_gr8 2, r0l - xorc #0x2, exr - stc exr, r0l - test_h_gr8 0, r0l - - xorc #0x1, exr ; Immediate 8-bit operand (carry flag) - stc exr, r0l - test_h_gr8 1, r0l - xorc #0x1, exr - stc exr, r0l - test_h_gr8 0, r0l - - test_h_gr32 0xa5a5a500 er0 - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif ; not h8300 or h8300h - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/xorl.s b/sim/testsuite/sim/h8300/xorl.s deleted file mode 100644 index 67b2e49..0000000 --- a/sim/testsuite/sim/h8300/xorl.s +++ /dev/null @@ -1,77 +0,0 @@ -# Hitachi H8 testcase 'xor.l' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. -xor_l_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.l #xx:16,Rd - xor.l #0xffff:16, er0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5a5a5 | ffff - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -xor_l_imm32: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.l #xx:32,Rd - xor.l #0xffffffff, er0 ; Immediate 32-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff - - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - -xor_l_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.l Rs,Rd - mov.l #0xffffffff, er1 - xor.l er1, er0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - - test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff - test_h_gr32 0xffffffff er1 ; Make sure er1 is unchanged - - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/h8300/xorw.s b/sim/testsuite/sim/h8300/xorw.s deleted file mode 100644 index 3c5e5b8..0000000 --- a/sim/testsuite/sim/h8300/xorw.s +++ /dev/null @@ -1,61 +0,0 @@ -# Hitachi H8 testcase 'xor.w' -# mach(): h8300h h8300s h8sx -# as(h8300): --defsym sim_cpu=0 -# as(h8300h): --defsym sim_cpu=1 -# as(h8300s): --defsym sim_cpu=2 -# as(h8sx): --defsym sim_cpu=3 -# ld(h8300h): -m h8300helf -# ld(h8300s): -m h8300self -# ld(h8sx): -m h8300sxelf - - .include "testutils.inc" - - start - -.if (sim_cpu) ; non-zero means h8300h, s, or sx -xor_w_imm16: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.w #xx:16,Rd - xor.w #0xffff, r0 ; Immediate 16-bit operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff -.endif - test_gr_a5a5 1 ; Make sure other general regs not disturbed - test_gr_a5a5 2 - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 -.endif - -xor_w_reg: - set_grs_a5a5 ; Fill all general regs with a fixed pattern - ;; fixme set ccr - - ;; xor.w Rs,Rd - mov.w #0xffff, r1 - xor.w r1, r0 ; Register operand - - ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 - test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff - test_h_gr16 0xffff r1 ; Make sure r1 is unchanged -.if (sim_cpu) ; non-zero means h8300h, s, or sx - test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff - test_h_gr32 0xa5a5ffff er1 ; Make sure er1 is unchanged -.endif - test_gr_a5a5 2 ; Make sure other general regs not disturbed - test_gr_a5a5 3 - test_gr_a5a5 4 - test_gr_a5a5 5 - test_gr_a5a5 6 - test_gr_a5a5 7 - - pass - - exit 0 diff --git a/sim/testsuite/sim/iq2000/ChangeLog b/sim/testsuite/sim/iq2000/ChangeLog deleted file mode 100644 index d3f8b9d..0000000 --- a/sim/testsuite/sim/iq2000/ChangeLog +++ /dev/null @@ -1,3 +0,0 @@ -2015-04-05 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/sim/iq2000/allinsn.exp b/sim/testsuite/sim/iq2000/allinsn.exp deleted file mode 100644 index 38eee9b..0000000 --- a/sim/testsuite/sim/iq2000/allinsn.exp +++ /dev/null @@ -1,15 +0,0 @@ -# iq2000 simulator testsuite - -if [istarget iq2000-*] { - # all machines - set all_machs "iq2000" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/iq2000/pass.s b/sim/testsuite/sim/iq2000/pass.s deleted file mode 100644 index 4bb07cb..0000000 --- a/sim/testsuite/sim/iq2000/pass.s +++ /dev/null @@ -1,7 +0,0 @@ -# check that the sim doesn't die immediately. -# mach: iq2000 - -.include "testutils.inc" - - start - pass diff --git a/sim/testsuite/sim/iq2000/testutils.inc b/sim/testsuite/sim/iq2000/testutils.inc deleted file mode 100644 index 0e0dabd..0000000 --- a/sim/testsuite/sim/iq2000/testutils.inc +++ /dev/null @@ -1,53 +0,0 @@ -# MACRO: exit - .macro exit nr - ori r5, r0, \nr; - # Trap function 1: exit(). - ori r4, r0, 1; - syscall; - .endm - -# MACRO: pass -# Write 'pass' to stdout and quit - .macro pass - # Trap function 5: write(). - ori r4, r0, 5; - # Use stdout. - ori r5, r0, 1; - # Point to the string. - lui r6, %hi(1f); - ori r6, r6, %lo(1f); - # Number of bytes to write. - ori r7, r0, 5; - # Trigger OS trap. - syscall; - exit 0 - .data - 1: .asciz "pass\n" - .endm - -# MACRO: fail -# Write 'fail' to stdout and quit - .macro fail - # Trap function 5: write(). - ori r4, r0, 5; - # Use stdout. - ori r5, r0, 1; - # Point to the string. - lui r6, %hi(1f); - ori r6, r6, %lo(1f); - # Number of bytes to write. - ori r7, r0, 5; - # Trigger OS trap. - syscall; - exit 0 - .data - 1: .asciz "fail\n" - .endm - -# MACRO: start -# All assembler tests should start with a call to "start" - .macro start - .text -.global _start -_start: - .endm diff --git a/sim/testsuite/sim/lm32/ChangeLog b/sim/testsuite/sim/lm32/ChangeLog deleted file mode 100644 index d3f8b9d..0000000 --- a/sim/testsuite/sim/lm32/ChangeLog +++ /dev/null @@ -1,3 +0,0 @@ -2015-04-05 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/sim/lm32/allinsn.exp b/sim/testsuite/sim/lm32/allinsn.exp deleted file mode 100644 index 6174498..0000000 --- a/sim/testsuite/sim/lm32/allinsn.exp +++ /dev/null @@ -1,15 +0,0 @@ -# lm32 simulator testsuite - -if [istarget lm32-*] { - # all machines - set all_machs "lm32" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/lm32/pass.s b/sim/testsuite/sim/lm32/pass.s deleted file mode 100644 index 3154b2b..0000000 --- a/sim/testsuite/sim/lm32/pass.s +++ /dev/null @@ -1,7 +0,0 @@ -# check that the sim doesn't die immediately. -# mach: lm32 - -.include "testutils.inc" - - start - pass diff --git a/sim/testsuite/sim/lm32/testutils.inc b/sim/testsuite/sim/lm32/testutils.inc deleted file mode 100644 index 0f62e3a..0000000 --- a/sim/testsuite/sim/lm32/testutils.inc +++ /dev/null @@ -1,59 +0,0 @@ -# MACRO: exit - .macro exit nr - mvi r1, \nr; - # Trap function 1: exit(). - mvi r8, 1; - scall; - .endm - -# MACRO: pass -# Write 'pass' to stdout and quit - .macro pass - # Trap function 5: write(). - mvi r8, 5; - # Use stdout. - mvi r1, 1; - # Point to the string. - mvhi r2, hi(1f) - ori r2, r2, lo(1f) - # Number of bytes to write. - mvi r3, 5; - # Trigger OS trap. - scall; - exit 0 - .data - 1: .asciz "pass\n" - .endm - -# MACRO: fail -# Write 'fail' to stdout and quit - .macro fail - # Trap function 5: write(). - mvi r8, 5; - # Use stdout. - mvi r1, 1; - # Point to the string. - mvhi r2, hi(1f) - ori r2, r2, lo(1f) - # Number of bytes to write. - mvi r3, 5; - # Trigger OS trap. - scall; - exit 0 - .data - 1: .asciz "fail\n" - .endm - -# MACRO: start -# All assembler tests should start with a call to "start" - .macro start - .data -.global _fstack -_fstack: - .rept 0x1024 - .byte 00 - .endr - .text -.global _start -_start: - .endm diff --git a/sim/testsuite/sim/m32c/ChangeLog b/sim/testsuite/sim/m32c/ChangeLog deleted file mode 100644 index 8437919..0000000 --- a/sim/testsuite/sim/m32c/ChangeLog +++ /dev/null @@ -1,10 +0,0 @@ -2015-11-14 Mike Frysinger - - * allinsn.exp: New file. - * fail.s, pass.s: New tests. - * testutils.inc: New test helper logic. - -2015-11-09 Mike Frysinger - - * blinky.s: Moved from ../../../m32c/. - * gloss.s, sample.ld, sample.s, sample2.c: Likewise. diff --git a/sim/testsuite/sim/m32c/allinsn.exp b/sim/testsuite/sim/m32c/allinsn.exp deleted file mode 100644 index fb5ccca..0000000 --- a/sim/testsuite/sim/m32c/allinsn.exp +++ /dev/null @@ -1,16 +0,0 @@ -# M32C simulator testsuite. -# TODO: Add support for .c tests. - -if [istarget m32c*-*-*] { - # all machines - set all_machs "m32c" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/m32c/blinky.s b/sim/testsuite/sim/m32c/blinky.s deleted file mode 100644 index 1dbad97..0000000 --- a/sim/testsuite/sim/m32c/blinky.s +++ /dev/null @@ -1,34 +0,0 @@ -;;; blinky.s --- sample program to blink LED's on M32C simulator -;;; -;;; Copyright (C) 2005-2021 Free Software Foundation, Inc. -;;; Contributed by Red Hat, Inc. -;;; -;;; This file is part of the GNU simulators. -;;; -;;; This program is free software; you can redistribute it and/or modify -;;; it under the terms of the GNU General Public License as published by -;;; the Free Software Foundation; either version 3 of the License, or -;;; (at your option) any later version. -;;; -;;; This program is distributed in the hope that it will be useful, -;;; but WITHOUT ANY WARRANTY; without even the implied warranty of -;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -;;; GNU General Public License for more details. -;;; -;;; You should have received a copy of the GNU General Public License -;;; along with this program. If not, see . - - .text - - .global _start -_start: - mov.w #0xe1,a0 -top: - sub.w #1,r0 - mov.b r0h,[a0] - - mov.w #1000,r1 -loop: - adjnz.w #-1,r1,loop - - jmp.w top diff --git a/sim/testsuite/sim/m32c/fail.s b/sim/testsuite/sim/m32c/fail.s deleted file mode 100644 index 5066bce..0000000 --- a/sim/testsuite/sim/m32c/fail.s +++ /dev/null @@ -1,9 +0,0 @@ -# check that the sim doesn't die immediately. -# mach: m32c -# ld: -T$srcdir/$subdir/sample.ld -# xerror: - -.include "testutils.inc" - - start - fail diff --git a/sim/testsuite/sim/m32c/gloss.s b/sim/testsuite/sim/m32c/gloss.s deleted file mode 100644 index ce03774..0000000 --- a/sim/testsuite/sim/m32c/gloss.s +++ /dev/null @@ -1,32 +0,0 @@ -;;; gloss.s --- system calls for sample2.x -;;; -;;; Copyright (C) 2005-2021 Free Software Foundation, Inc. -;;; Contributed by Red Hat, Inc. -;;; -;;; This file is part of the GNU simulators. -;;; -;;; This program is free software; you can redistribute it and/or modify -;;; it under the terms of the GNU General Public License as published by -;;; the Free Software Foundation; either version 3 of the License, or -;;; (at your option) any later version. -;;; -;;; This program is distributed in the hope that it will be useful, -;;; but WITHOUT ANY WARRANTY; without even the implied warranty of -;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -;;; GNU General Public License for more details. -;;; -;;; You should have received a copy of the GNU General Public License -;;; along with this program. If not, see . - -;;; See the 'sample2.x' target in Makefile.in. - .global _exit -_exit: - mov.b #1,r0l - ste.b r0l,0xe0000 - rts - - .global _foo -_foo: - mov.b #2,r0l - ste.b r0l,0xe0000 - rts diff --git a/sim/testsuite/sim/m32c/pass.s b/sim/testsuite/sim/m32c/pass.s deleted file mode 100644 index 9f39ac0..0000000 --- a/sim/testsuite/sim/m32c/pass.s +++ /dev/null @@ -1,8 +0,0 @@ -# check that the sim doesn't die immediately. -# mach: m32c -# ld: -T$srcdir/$subdir/sample.ld - -.include "testutils.inc" - - start - pass diff --git a/sim/testsuite/sim/m32c/sample.ld b/sim/testsuite/sim/m32c/sample.ld deleted file mode 100644 index 112012a..0000000 --- a/sim/testsuite/sim/m32c/sample.ld +++ /dev/null @@ -1,41 +0,0 @@ -/* sample2.ld --- linker script for sample2.x - -Copyright (C) 2005-2021 Free Software Foundation, Inc. -Contributed by Red Hat, Inc. - -This file is part of the GNU simulators. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program. If not, see . */ - -/* See the 'sample2.x' target in Makefile.in. */ - -ENTRY(_start) - -MEMORY { - RAM1 (w) : ORIGIN = 0xc800, LENGTH = 0x0200 - RAM2 (w) : ORIGIN = 0xca56, LENGTH = 0x1000 - ROM (w) : ORIGIN = 0x30000, LENGTH = 0x1000 -} - -SECTIONS { - .data : { - *(.data*) - } > RAM1 - .text : { - *(.text*) - } > RAM2 - .fardata : { - *(.fardata*) - } > ROM -} diff --git a/sim/testsuite/sim/m32c/sample.s b/sim/testsuite/sim/m32c/sample.s deleted file mode 100644 index 14b0548..0000000 --- a/sim/testsuite/sim/m32c/sample.s +++ /dev/null @@ -1,27 +0,0 @@ -;;; sample.s --- simple test program for M32C simulator -;;; -;;; Copyright (C) 2005-2021 Free Software Foundation, Inc. -;;; Contributed by Red Hat, Inc. -;;; -;;; This file is part of the GNU simulators. -;;; -;;; This program is free software; you can redistribute it and/or modify -;;; it under the terms of the GNU General Public License as published by -;;; the Free Software Foundation; either version 3 of the License, or -;;; (at your option) any later version. -;;; -;;; This program is distributed in the hope that it will be useful, -;;; but WITHOUT ANY WARRANTY; without even the implied warranty of -;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -;;; GNU General Public License for more details. -;;; -;;; You should have received a copy of the GNU General Public License -;;; along with this program. If not, see . - - .text - - .global _start -_start: - mov.w #0x1234,r1 - mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3 - brk diff --git a/sim/testsuite/sim/m32c/sample2.c b/sim/testsuite/sim/m32c/sample2.c deleted file mode 100644 index 3b8f055..0000000 --- a/sim/testsuite/sim/m32c/sample2.c +++ /dev/null @@ -1,29 +0,0 @@ -/* sample2.c --- main source for sample2.x test program for M32C simulator - -Copyright (C) 2005-2021 Free Software Foundation, Inc. -Contributed by Red Hat, Inc. - -This file is part of the GNU simulators. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program. If not, see . */ - -/* See the 'sample2.x' target in Makefile.in. */ -void exit (int); - -void -start (void) -{ - foo (1, 2, 3, 4); - exit (5); -} diff --git a/sim/testsuite/sim/m32c/testutils.inc b/sim/testsuite/sim/m32c/testutils.inc deleted file mode 100644 index fa6f5a9..0000000 --- a/sim/testsuite/sim/m32c/testutils.inc +++ /dev/null @@ -1,53 +0,0 @@ -# MACRO: exit - .macro exit nr - mov.w \nr, r1; - # Trap function 1: exit(). - mov.b #1, r0l; - ste.b r0l, 0x400; - .endm - -# MACRO: pass -# Write 'pass' to stdout and quit - .macro pass - # Use stdout. - mov.w #1, r1; - # Point to the string. - mov.w #1f, r2; - # Number of bytes to write; push onto stack. - push.w #5; - # Adjust as the sim expects 3 byte offset. (!?) - add.w #-3, sp; - # Trap function 5: write(). - mov.b #5, r0l; - ste.b r0l, 0x400; - exit #0 - .data - 1: .asciz "pass\n" - .endm - -# MACRO: fail -# Write 'fail' to stdout and quit - .macro fail - # Use stdout. - mov.w #1, r1; - # Point to the string. - mov.w #1f, r2; - # Number of bytes to write; push onto stack. - push.w #5; - # Adjust as the sim expects 3 byte offset. (!?) - add.w #-3, sp; - # Trap function 5: write(). - mov.b #5, r0l; - ste.b r0l, 0x400; - exit #1 - .data - 1: .asciz "fail\n" - .endm - -# MACRO: start -# All assembler tests should start with a call to "start" - .macro start - .text -.global _start -_start: - .endm diff --git a/sim/testsuite/sim/m32r/ChangeLog b/sim/testsuite/sim/m32r/ChangeLog deleted file mode 100644 index 3e6dbf7..0000000 --- a/sim/testsuite/sim/m32r/ChangeLog +++ /dev/null @@ -1,126 +0,0 @@ -2021-01-15 Mike Frysinger - - * exit47.ms: New testcase from ../../m32r-elf/. - -1999-04-21 Doug Evans - - * nop.cgs: Add missing nop insn. - -1999-01-05 Doug Evans - - * allinsn.exp: Set all_machs. - * misc.exp: Likewise. - -1998-12-14 Doug Evans - - * hello.ms: Add trailing \n to expected output. - * hw-trap.ms: Ditto. - - * trap.cgs: Properly align trap2_handler. - - * uread16.ms: New testcase. - * uread32.ms: New testcase. - * uwrite16.ms: New testcase. - * uwrite32.ms: New testcase. - -Tue Sep 15 14:56:22 1998 Doug Evans - - * testutils.inc (test_h_gr): Use mvaddr_h_gr. - * rte.cgs: Test bbpc,bbpsw. - * trap.cgs: Test bbpc,bbpsw. - -Wed Jul 1 15:57:54 1998 Doug Evans - - * hw-trap.ms: New testcase. - -Wed Jun 10 10:53:20 1998 Doug Evans - - * addx.cgs: Add another test. - * jmp.cgs: Add another test. - -Mon Jun 8 16:08:27 1998 Doug Evans - - * trap.cgs: Test trap 2. - -Tue Apr 21 10:49:03 1998 Doug Evans - - * addx.cgs: Test (-1)+(-1)+1. - -Fri Apr 17 16:00:52 1998 Doug Evans - - * mv[ft]achi.cgs: Fix expected result - (sign extension of top 8 bits). - -Fri Feb 20 11:00:02 1998 Nick Clifton - - * unlock.cgs: Fixed test. - * mvfc.cgs: Fixed test. - * remu.cgs: Fixed test. - * bnc24.cgs: Test long BNC instruction. - * bnc8.cgs: Test short BNC instruction. - * ld-plus.cgs: Test LD instruction. - * macwhi.cgs: Test MACWHI instruction. - * macwlo.cgs: Test MACWLO instruction. - * mulwhi.cgs: Test MULWHI instruction. - * mulwlo.cgs: Test MULWLO instruction. - * mvfachi.cgs: Test MVFACHI instruction. - * mvfaclo.cgs: Test MVFACLO instruction. - * mvtaclo.cgs: Test MVTACLO instruction. - * addv.cgs: Test ADDV instruction. - * addv3.cgs: Test ADDV3 instruction. - * addx.cgs: Test ADDX instruction. - * lock.cgs: Test LOCK instruction. - * neg.cgs: Test NEG instruction. - * not.cgs: Test NOT instruction. - * unlock.cgs: Test UNLOCK instruction. - -Thu Feb 19 11:15:45 1998 Nick Clifton - - * testutils.inc (mvaddr_h_gr): new macro to load an - address into a general register. - - * or3.cgs: Test OR3 instruction. - * rach.cgs: Test RACH instruction. - * rem.cgs: Test REM instruction. - * sub.cgs: Test SUB instruction. - * mv.cgs: Test MV instruction. - * mul.cgs: Test MUL instruction. - * bl24.cgs: Test long BL instruction. - * bl8.cgs: Test short BL instruction. - * blez.cgs: Test BLEZ instruction. - * bltz.cgs: Test BLTZ instruction. - * bne.cgs: Test BNE instruction. - * bnez.cgs: Test BNEZ instruction. - * bra24.cgs: Test long BRA instruction. - * bra8.cgs: Test short BRA instruction. - * jl.cgs: Test JL instruction. - * or.cgs: Test OR instruction. - * jmp.cgs: Test JMP instruction. - * and.cgs: Test AND instruction. - * and3.cgs: Test AND3 instruction. - * beq.cgs: Test BEQ instruction. - * beqz.cgs: Test BEQZ instruction. - * bgez.cgs: Test BGEZ instruction. - * bgtz.cgs: Test BGTZ instruction. - * cmp.cgs: Test CMP instruction. - * cmpi.cgs: Test CMPI instruction. - * cmpu.cgs: Test CMPU instruction. - * cmpui.cgs: Test CMPUI instruction. - * div.cgs: Test DIV instruction. - * divu.cgs: Test DIVU instruction. - * cmpeq.cgs: Test CMPEQ instruction. - * sll.cgs: Test SLL instruction. - * sll3.cgs: Test SLL3 instruction. - * slli.cgs: Test SLLI instruction. - * sra.cgs: Test SRA instruction. - * sra3.cgs: Test SRA3 instruction. - * srai.cgs: Test SRAI instruction. - * srl.cgs: Test SRL instruction. - * srl3.cgs: Test SRL3 instruction. - * srli.cgs: Test SRLI instruction. - * xor3.cgs: Test XOR3 instruction. - * xor.cgs: Test XOR instruction. - -Tue Feb 17 12:46:05 1998 Doug Evans - - * *: m32r dejagnu simulator testsuite. diff --git a/sim/testsuite/sim/m32r/add.cgs b/sim/testsuite/sim/m32r/add.cgs deleted file mode 100644 index 8ed2b3a..0000000 --- a/sim/testsuite/sim/m32r/add.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# m32r testcase for add $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global add -add: - - mvi_h_gr r4, 1 - mvi_h_gr r5, 2 - add r4, r5 - test_h_gr r4, 3 - - pass diff --git a/sim/testsuite/sim/m32r/add3.cgs b/sim/testsuite/sim/m32r/add3.cgs deleted file mode 100644 index d1cc848..0000000 --- a/sim/testsuite/sim/m32r/add3.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# m32r testcase for add3 $dr,$sr,#$slo16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global add3 -add3: - - mvi_h_gr r5, 1 - add3 r4, r5, 2 - test_h_gr r4, 3 - - pass diff --git a/sim/testsuite/sim/m32r/addi.cgs b/sim/testsuite/sim/m32r/addi.cgs deleted file mode 100644 index 1448d0d..0000000 --- a/sim/testsuite/sim/m32r/addi.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# m32r testcase for addi $dr,#$simm8 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global addi -addi: - - mvi_h_gr r5, 1 - addi r5, 2 - test_h_gr r5, 3 - - pass - diff --git a/sim/testsuite/sim/m32r/addv.cgs b/sim/testsuite/sim/m32r/addv.cgs deleted file mode 100644 index 704be83..0000000 --- a/sim/testsuite/sim/m32r/addv.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# m32r testcase for addv $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global addv -addv: - mvi_h_condbit 0 - mvi_h_gr r4, 0x80000000 - mvi_h_gr r5, 0x80000000 - - addv r4, r5 - - bnc not_ok - test_h_gr r4, 0 - - pass -not_ok: - fail diff --git a/sim/testsuite/sim/m32r/addv3.cgs b/sim/testsuite/sim/m32r/addv3.cgs deleted file mode 100644 index a8c0a10..0000000 --- a/sim/testsuite/sim/m32r/addv3.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# m32r testcase for addv3 $dr,$sr,#$simm16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global addv3 -addv3: - mvi_h_condbit 0 - mvi_h_gr r4, 1 - mvi_h_gr r5, 1 - - addv3 r4, r5, #2 - - bc not_ok - - test_h_gr r4, 3 - - mvi_h_gr r5, 0x7fff8001 - - addv3 r4, r5, #0x7fff - - bnc not_ok - - pass -not_ok: - fail diff --git a/sim/testsuite/sim/m32r/addx.cgs b/sim/testsuite/sim/m32r/addx.cgs deleted file mode 100644 index 630e3db..0000000 --- a/sim/testsuite/sim/m32r/addx.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# m32r testcase for addx $dr,$sr -# mach(): m32r m32rx -# timeout(): 42 - -# timeout is set to test it - - .include "testutils.inc" - - start - - .global addx -addx: - mvi_h_condbit 1 - mvi_h_gr r4, 1 - mvi_h_gr r5, 2 - addx r4, r5 - bc not_ok - test_h_gr r4, 4 - - mvi_h_gr r4, 0xfffffffe - addx r4, r5 - bnc not_ok - test_h_gr r4, 0 - - mvi_h_gr r4, -1 - mvi_h_gr r5, -1 - mvi_h_condbit 1 - addx r4,r5 - bnc not_ok - test_h_gr r4, -1 - - mvi_h_gr r4,-1 - mvi_h_gr r5,0x7fffffff - mvi_h_condbit 1 - addx r5,r4 - bnc not_ok - test_h_gr r5,0x7fffffff - - pass - -not_ok: - fail diff --git a/sim/testsuite/sim/m32r/allinsn.exp b/sim/testsuite/sim/m32r/allinsn.exp deleted file mode 100644 index 8eed80f..0000000 --- a/sim/testsuite/sim/m32r/allinsn.exp +++ /dev/null @@ -1,21 +0,0 @@ -# M32R simulator testsuite. - -if [istarget m32r*-*-*] { - # load support procs - # load_lib cgen.exp - - # all machines - set all_machs "m32r" - - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/m32r/and.cgs b/sim/testsuite/sim/m32r/and.cgs deleted file mode 100644 index 1c26885..0000000 --- a/sim/testsuite/sim/m32r/and.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for and $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global and -and: - mvi_h_gr r4, 3 - mvi_h_gr r5, 6 - - and r4, r5 - - test_h_gr r4, 2 - - pass diff --git a/sim/testsuite/sim/m32r/and3.cgs b/sim/testsuite/sim/m32r/and3.cgs deleted file mode 100644 index 395de30..0000000 --- a/sim/testsuite/sim/m32r/and3.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for and3 $dr,$sr,#$uimm16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global and3 -and3: - mvi_h_gr r4, 0 - mvi_h_gr r5, 6 - - and3 r4, r5, #3 - - test_h_gr r4, 2 - - pass diff --git a/sim/testsuite/sim/m32r/bc24.cgs b/sim/testsuite/sim/m32r/bc24.cgs deleted file mode 100644 index 6bb4333..0000000 --- a/sim/testsuite/sim/m32r/bc24.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# m32r testcase for bc $disp24 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bc24 -bc24: - - mvi_h_condbit 0 - bc.l test0fail - bra test0pass -test0fail: - fail -test0pass: - - mvi_h_condbit 1 - bc.l test1pass - fail -test1pass: - - pass - diff --git a/sim/testsuite/sim/m32r/bc8.cgs b/sim/testsuite/sim/m32r/bc8.cgs deleted file mode 100644 index ceb622c..0000000 --- a/sim/testsuite/sim/m32r/bc8.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# m32r testcase for bc $disp8 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bc8 -bc8: - - mvi_h_condbit 0 - bc.s test0fail - bra test0pass -test0fail: - fail -test0pass: - - mvi_h_condbit 1 - bc.s test1pass - fail -test1pass: - - pass diff --git a/sim/testsuite/sim/m32r/beq.cgs b/sim/testsuite/sim/m32r/beq.cgs deleted file mode 100644 index c4d6d8b..0000000 --- a/sim/testsuite/sim/m32r/beq.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# m32r testcase for beq $src1,$src2,$disp16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global beq -beq: - mvi_h_condbit 0 - mvi_h_gr r4, 12 - mvi_h_gr r5, 12 - beq r4, r5, ok -not_ok: - fail -ok: - mvi_h_gr r5, 11 - beq r4, r5, not_ok - - pass diff --git a/sim/testsuite/sim/m32r/beqz.cgs b/sim/testsuite/sim/m32r/beqz.cgs deleted file mode 100644 index 654737d..0000000 --- a/sim/testsuite/sim/m32r/beqz.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# m32r testcase for beqz $src2,$disp16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global beqz -beqz: - mvi_h_gr r4, 0 - beqz r4, ok -not_ok: - fail -ok: - mvi_h_gr r4, 1 - beqz r4, not_ok - - pass diff --git a/sim/testsuite/sim/m32r/bgez.cgs b/sim/testsuite/sim/m32r/bgez.cgs deleted file mode 100644 index f7031f0..0000000 --- a/sim/testsuite/sim/m32r/bgez.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# m32r testcase for bgez $src2,$disp16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bgez -bgez: - mvi_h_gr r4, 1 - bgez r4, ok -not_ok: - fail -ok: - mvi_h_gr r4, -1 - bgez r4, not_ok - - pass diff --git a/sim/testsuite/sim/m32r/bgtz.cgs b/sim/testsuite/sim/m32r/bgtz.cgs deleted file mode 100644 index 6ab8989..0000000 --- a/sim/testsuite/sim/m32r/bgtz.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# m32r testcase for bgtz $src2,$disp16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bgtz -bgtz: - mvi_h_gr r4, 1 - bgtz r4, ok -not_ok: - fail -ok: - mvi_h_gr r4, 0 - bgtz r4, not_ok - - pass diff --git a/sim/testsuite/sim/m32r/bl24.cgs b/sim/testsuite/sim/m32r/bl24.cgs deleted file mode 100644 index fd6f0dd..0000000 --- a/sim/testsuite/sim/m32r/bl24.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# m32r testcase for bl $disp24 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bl24 -bl24: - bl.l test0pass -test1fail: - fail - -test0pass: - mvaddr_h_gr r4, test1fail - bne r4, r14, test1fail - - pass diff --git a/sim/testsuite/sim/m32r/bl8.cgs b/sim/testsuite/sim/m32r/bl8.cgs deleted file mode 100644 index d263698..0000000 --- a/sim/testsuite/sim/m32r/bl8.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# m32r testcase for bl $disp8 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bl8 -bl8: - bl.s test0pass -test1fail: - fail - -test0pass: - mvaddr_h_gr r4, test1fail - bne r4, r14, test1fail - - pass diff --git a/sim/testsuite/sim/m32r/blez.cgs b/sim/testsuite/sim/m32r/blez.cgs deleted file mode 100644 index e3d198d..0000000 --- a/sim/testsuite/sim/m32r/blez.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# m32r testcase for blez $src2,$disp16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global blez -blez: - mvi_h_gr r4, 0 - blez r4, test0pass -test1fail: - fail - -test0pass: - mvi_h_gr r4, 1 - blez r4, test1fail - - pass diff --git a/sim/testsuite/sim/m32r/bltz.cgs b/sim/testsuite/sim/m32r/bltz.cgs deleted file mode 100644 index c9377fc..0000000 --- a/sim/testsuite/sim/m32r/bltz.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# m32r testcase for bltz $src2,$disp16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bltz -bltz: - mvi_h_gr r4, -1 - bltz r4, test0pass -test1fail: - fail - -test0pass: - mvi_h_gr r4, 0 - bltz r4, test1fail - - pass diff --git a/sim/testsuite/sim/m32r/bnc24.cgs b/sim/testsuite/sim/m32r/bnc24.cgs deleted file mode 100644 index 692d2d5..0000000 --- a/sim/testsuite/sim/m32r/bnc24.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# m32r testcase for bnc $disp24 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bnc24 -bnc24: - mvi_h_condbit 0 - bnc.l test0pass - -test1fail: - fail -test0pass: - - mvi_h_condbit 1 - bnc.l test1fail - - pass diff --git a/sim/testsuite/sim/m32r/bnc8.cgs b/sim/testsuite/sim/m32r/bnc8.cgs deleted file mode 100644 index dae2613..0000000 --- a/sim/testsuite/sim/m32r/bnc8.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# m32r testcase for bnc $disp8 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bnc8 -bnc8: - mvi_h_condbit 0 - bnc.s test0pass - -test1fail: - fail - -test0pass: - mvi_h_condbit 1 - bnc.s test1fail - - pass diff --git a/sim/testsuite/sim/m32r/bne.cgs b/sim/testsuite/sim/m32r/bne.cgs deleted file mode 100644 index 5e1d7a6..0000000 --- a/sim/testsuite/sim/m32r/bne.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# m32r testcase for bne $src1,$src2,$disp16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bne -bne: - mvi_h_gr r4, 1 - mvi_h_gr r5, 2 - bne r4, r5, test0pass -test1fail: - fail - -test0pass: - mvi_h_gr r4, 2 - bne r4, r5, test1fail - - pass diff --git a/sim/testsuite/sim/m32r/bnez.cgs b/sim/testsuite/sim/m32r/bnez.cgs deleted file mode 100644 index 9f10289..0000000 --- a/sim/testsuite/sim/m32r/bnez.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# m32r testcase for bnez $src2,$disp16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bnez -bnez: - mvi_h_gr r4, 1 - bnez r4, test0pass -test1fail: - fail - -test0pass: - mvi_h_gr r4, 0 - bnez r4, test1fail - - pass diff --git a/sim/testsuite/sim/m32r/bra24.cgs b/sim/testsuite/sim/m32r/bra24.cgs deleted file mode 100644 index d62d2bf..0000000 --- a/sim/testsuite/sim/m32r/bra24.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# m32r testcase for bra $disp24 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bra24 -bra24: - bra.l ok - - fail - -ok: - pass diff --git a/sim/testsuite/sim/m32r/bra8.cgs b/sim/testsuite/sim/m32r/bra8.cgs deleted file mode 100644 index f5f50ad..0000000 --- a/sim/testsuite/sim/m32r/bra8.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# m32r testcase for bra $disp8 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global bra8 -bra8: - bra.s ok - - fail -ok: - pass diff --git a/sim/testsuite/sim/m32r/cmp.cgs b/sim/testsuite/sim/m32r/cmp.cgs deleted file mode 100644 index 6ea6720..0000000 --- a/sim/testsuite/sim/m32r/cmp.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# m32r testcase for cmp $src1,$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global cmp -cmp: - mvi_h_condbit 0 - mvi_h_gr r4, 1 - mvi_h_gr r5, 2 - cmp r4, r5 - bc ok -not_ok: - fail -ok: - mvi_h_condbit 1 - mvi_h_gr r4, 2 - cmp r4, r5 - bc not_ok - - pass diff --git a/sim/testsuite/sim/m32r/cmpi.cgs b/sim/testsuite/sim/m32r/cmpi.cgs deleted file mode 100644 index af11283..0000000 --- a/sim/testsuite/sim/m32r/cmpi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# m32r testcase for cmpi $src2,#$simm16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global cmpi -cmpi: - mvi_h_condbit 0 - mvi_h_gr r4, 1 - - cmpi r4, #2 - bc ok -not_ok: - fail -ok: - mvi_h_condbit 1 - mvi_h_gr r4, 2 - cmpi r4, #2 - bc not_ok - - - pass diff --git a/sim/testsuite/sim/m32r/cmpu.cgs b/sim/testsuite/sim/m32r/cmpu.cgs deleted file mode 100644 index e0b4ef1..0000000 --- a/sim/testsuite/sim/m32r/cmpu.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# m32r testcase for cmpu $src1,$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global cmpu -cmpu: - mvi_h_condbit 0 - mvi_h_gr r4, 1 - mvi_h_gr r5, -2 - cmpu r4, r5 - bc ok -not_ok: - fail -ok: - mvi_h_condbit 1 - mvi_h_gr r4, -1 - cmpu r4, r5 - bc not_ok - - pass diff --git a/sim/testsuite/sim/m32r/cmpui.cgs b/sim/testsuite/sim/m32r/cmpui.cgs deleted file mode 100644 index aa30207..0000000 --- a/sim/testsuite/sim/m32r/cmpui.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# m32r testcase for cmpui $src2,#$simm16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global cmpui -cmpui: - mvi_h_condbit 0 - mvi_h_gr r4, 1 - cmpui r4, #2 - bc ok -not_ok: - fail -ok: - mvi_h_condbit 1 - mvi_h_gr r4, -1 - cmpui r4, #2 - bc not_ok - - pass diff --git a/sim/testsuite/sim/m32r/div.cgs b/sim/testsuite/sim/m32r/div.cgs deleted file mode 100644 index 733f362..0000000 --- a/sim/testsuite/sim/m32r/div.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for div $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global div -div: - mvi_h_gr r4, 0x18000 - mvi_h_gr r5, 8 - - div r4, r5 - - test_h_gr r4, 0x3000 - - pass diff --git a/sim/testsuite/sim/m32r/divu.cgs b/sim/testsuite/sim/m32r/divu.cgs deleted file mode 100644 index 25342d5..0000000 --- a/sim/testsuite/sim/m32r/divu.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for divu $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global divu -divu: - mvi_h_gr r4, 0x18000 - mvi_h_gr r5, 8 - - divu r4, r5 - - test_h_gr r4, 0x3000 - - pass diff --git a/sim/testsuite/sim/m32r/exit47.ms b/sim/testsuite/sim/m32r/exit47.ms deleted file mode 100644 index 20074f6..0000000 --- a/sim/testsuite/sim/m32r/exit47.ms +++ /dev/null @@ -1,11 +0,0 @@ -# mach(): m32r m32rx -# status: 47 -# output: - - ;; Return with exit code 47. - - .globl _start -_start: - ldi8 r1,#47 - ldi8 r0,#1 - trap #0 diff --git a/sim/testsuite/sim/m32r/hello.ms b/sim/testsuite/sim/m32r/hello.ms deleted file mode 100644 index 7ae2277..0000000 --- a/sim/testsuite/sim/m32r/hello.ms +++ /dev/null @@ -1,19 +0,0 @@ -# output(): Hello world!\n -# mach(): m32r m32rx - - .globl _start -_start: - -; write (hello world) - ldi8 r3,#14 - ld24 r2,#hello - ldi8 r1,#1 - ldi8 r0,#5 - trap #0 -; exit (0) - ldi8 r1,#0 - ldi8 r0,#1 - trap #0 - -length: .long 14 -hello: .ascii "Hello world!\r\n" diff --git a/sim/testsuite/sim/m32r/hw-trap.ms b/sim/testsuite/sim/m32r/hw-trap.ms deleted file mode 100644 index 2aa200b..0000000 --- a/sim/testsuite/sim/m32r/hw-trap.ms +++ /dev/null @@ -1,31 +0,0 @@ -# mach(): m32r m32rx -# output(): pass\n - - .include "testutils.inc" - - start - -; construct bra trap2_handler in trap 2 slot - ld24 r0,#bra_insn - ld r0,@r0 - ld24 r1,#trap2_handler - addi r1,#-0x48 ; pc relative address from trap 2 slot to handler - srai r1,#2 - or r0,r1 - ld24 r2,#0x48 ; address of trap 2 slot - st r0,@r2 - -; perform trap - ldi r4,#0 - trap #2 - test_h_gr r4,42 - - pass - -; trap 2 handler -trap2_handler: - ldi r4,#42 - rte - -bra_insn: - bra.l 0 diff --git a/sim/testsuite/sim/m32r/jl.cgs b/sim/testsuite/sim/m32r/jl.cgs deleted file mode 100644 index a89c26a..0000000 --- a/sim/testsuite/sim/m32r/jl.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# m32r testcase for jl $sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global jl -jl: - mvaddr_h_gr r4, ok - jl r4 -not_ok: - fail -ok: - mvaddr_h_gr r4, not_ok - bne r4, r14, not_ok - - pass diff --git a/sim/testsuite/sim/m32r/jmp.cgs b/sim/testsuite/sim/m32r/jmp.cgs deleted file mode 100644 index ba0864a..0000000 --- a/sim/testsuite/sim/m32r/jmp.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# m32r testcase for jmp $sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global jmp -jmp: - mvaddr_h_gr r4, ok1 - jmp r4 - fail -ok1: - mvaddr_h_gr r4, ok2 - addi r4,#1 - jmp r4 - fail -ok2: - pass diff --git a/sim/testsuite/sim/m32r/ld-d.cgs b/sim/testsuite/sim/m32r/ld-d.cgs deleted file mode 100644 index 1517436..0000000 --- a/sim/testsuite/sim/m32r/ld-d.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# m32r testcase for ld $dr,@($slo16,$sr) -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global ld_d -ld_d: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0 - - ld r5, @(#4, r4) - - test_h_gr r5, 0x12345678 - - pass - -data_loc: - .word 0x11223344 - .word 0x12345678 - diff --git a/sim/testsuite/sim/m32r/ld-plus.cgs b/sim/testsuite/sim/m32r/ld-plus.cgs deleted file mode 100644 index 5feaf62..0000000 --- a/sim/testsuite/sim/m32r/ld-plus.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# m32r testcase for ld $dr,@$sr+ -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global ld_plus -ld_plus: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0 - - ld r5, @r4+ - - test_h_gr r5, 0x12345678 - - mvaddr_h_gr r5, data_loc2 - bne r4, r5, not_ok - - pass -not_ok: - fail - -data_loc: - .word 0x12345678 -data_loc2: - .word 0x11223344 - diff --git a/sim/testsuite/sim/m32r/ld.cgs b/sim/testsuite/sim/m32r/ld.cgs deleted file mode 100644 index ad0b86f..0000000 --- a/sim/testsuite/sim/m32r/ld.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# m32r testcase for ld $dr,@$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global ld -ld: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0 - - ld r5, @r4 - - test_h_gr r5, 0x12345678 - - pass - -data_loc: - .word 0x12345678 - diff --git a/sim/testsuite/sim/m32r/ld24.cgs b/sim/testsuite/sim/m32r/ld24.cgs deleted file mode 100644 index 74b1555..0000000 --- a/sim/testsuite/sim/m32r/ld24.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# m32r testcase for ld24 $dr,#$uimm24 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global ld24 -ld24: - ld24 r4, #0x123456 - - test_h_gr r4, 0x123456 - - pass diff --git a/sim/testsuite/sim/m32r/ldb-d.cgs b/sim/testsuite/sim/m32r/ldb-d.cgs deleted file mode 100644 index 4a1cebb..0000000 --- a/sim/testsuite/sim/m32r/ldb-d.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# m32r testcase for ldb $dr,@($slo16,$sr) -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global ldb_d -ldb_d: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0 - - ldb r5, @(#2, r4) - - test_h_gr r5, 0x56 ; big endian processor - - pass - -data_loc: - .word 0x12345678 diff --git a/sim/testsuite/sim/m32r/ldb.cgs b/sim/testsuite/sim/m32r/ldb.cgs deleted file mode 100644 index 9b89545..0000000 --- a/sim/testsuite/sim/m32r/ldb.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# m32r testcase for ldb $dr,@$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global ldb -ldb: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0 - - ldb r5, @r4 - - test_h_gr r5, 0x12 ; big endian processor - - pass - -data_loc: - .word 0x12345678 - diff --git a/sim/testsuite/sim/m32r/ldh-d.cgs b/sim/testsuite/sim/m32r/ldh-d.cgs deleted file mode 100644 index 0be0309..0000000 --- a/sim/testsuite/sim/m32r/ldh-d.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# m32r testcase for ldh $dr,@($slo16,$sr) -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global ldh_d -ldh_d: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0 - - ldh r5, @(#2, r4) - - test_h_gr r5, 0x5678 ; big endian processor - - pass - -data_loc: - .word 0x12345678 - diff --git a/sim/testsuite/sim/m32r/ldh.cgs b/sim/testsuite/sim/m32r/ldh.cgs deleted file mode 100644 index 3d8db95..0000000 --- a/sim/testsuite/sim/m32r/ldh.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# m32r testcase for ldh $dr,@$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global ldh -ldh: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0 - - ldh r5, @r4 - - test_h_gr r5, 0x1234 ; big endian processor - - pass - -data_loc: - .word 0x12345678 - - pass diff --git a/sim/testsuite/sim/m32r/ldi16.cgs b/sim/testsuite/sim/m32r/ldi16.cgs deleted file mode 100644 index 478df1c..0000000 --- a/sim/testsuite/sim/m32r/ldi16.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# m32r testcase for ldi $dr,$slo16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global ldi16 -ldi16: - ldi r4, #0x1234 - - test_h_gr r4, 0x1234 - - pass diff --git a/sim/testsuite/sim/m32r/ldi8.cgs b/sim/testsuite/sim/m32r/ldi8.cgs deleted file mode 100644 index 081e7a8..0000000 --- a/sim/testsuite/sim/m32r/ldi8.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# m32r testcase for ldi $dr,#$simm8 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global ldi8 -ldi8: - ldi r4, #0x78 - - test_h_gr r4, 0x78 - - pass diff --git a/sim/testsuite/sim/m32r/ldub-d.cgs b/sim/testsuite/sim/m32r/ldub-d.cgs deleted file mode 100644 index 7661071..0000000 --- a/sim/testsuite/sim/m32r/ldub-d.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# m32r testcase for ldub $dr,@($slo16,$sr) -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global ldub_d -ldub_d: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0 - - ldub r5, @(#2, r4) - - test_h_gr r5, 0xa0 ; big endian processor - - pass - -data_loc: - .word 0x8090a0b0 - diff --git a/sim/testsuite/sim/m32r/ldub.cgs b/sim/testsuite/sim/m32r/ldub.cgs deleted file mode 100644 index 27913b5..0000000 --- a/sim/testsuite/sim/m32r/ldub.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# m32r testcase for ldub $dr,@$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global ldub -ldub: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0 - - ldub r5, @r4 - - test_h_gr r5, 0x80 ; big endian processor - - pass - -data_loc: - .word 0x800000f0 - diff --git a/sim/testsuite/sim/m32r/lduh-d.cgs b/sim/testsuite/sim/m32r/lduh-d.cgs deleted file mode 100644 index 96e294f..0000000 --- a/sim/testsuite/sim/m32r/lduh-d.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# m32r testcase for lduh $dr,@($slo16,$sr) -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global lduh_d -lduh_d: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0 - - lduh r5, @(#2, r4) - - test_h_gr r5, 0xf000 ; big endian processor - - pass - -data_loc: - .word 0x8000f000 diff --git a/sim/testsuite/sim/m32r/lduh.cgs b/sim/testsuite/sim/m32r/lduh.cgs deleted file mode 100644 index a03bbee..0000000 --- a/sim/testsuite/sim/m32r/lduh.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# m32r testcase for lduh $dr,@$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global lduh -lduh: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0 - - lduh r5, @r4 - - test_h_gr r5, 0x8010 ; big endian processor - - pass - -data_loc: - .word 0x8010f020 - - pass diff --git a/sim/testsuite/sim/m32r/lock.cgs b/sim/testsuite/sim/m32r/lock.cgs deleted file mode 100644 index 631525e..0000000 --- a/sim/testsuite/sim/m32r/lock.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# m32r testcase for lock $dr,@$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global lock -lock: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0 - - lock r5, @r4 - - test_h_gr r5, 0x12345678 - - ; There is no way to test the lock bit - - unlock r5, @r4 ; Unlock the processor - - pass - -data_loc: - .word 0x12345678 - diff --git a/sim/testsuite/sim/m32r/machi.cgs b/sim/testsuite/sim/m32r/machi.cgs deleted file mode 100644 index 2e2ef00..0000000 --- a/sim/testsuite/sim/m32r/machi.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for machi $src1,$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global machi -machi: - - mvi_h_accum0 0, 1 - mvi_h_gr r4, 0x10123 - mvi_h_gr r5, 0x20456 - machi r4, r5 - test_h_accum0 0, 0x20001 - - pass diff --git a/sim/testsuite/sim/m32r/maclo.cgs b/sim/testsuite/sim/m32r/maclo.cgs deleted file mode 100644 index 5d03539..0000000 --- a/sim/testsuite/sim/m32r/maclo.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for maclo $src1,$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global maclo -maclo: - - mvi_h_accum0 0, 1 - mvi_h_gr r4, 0x1230001 - mvi_h_gr r5, 0x4560002 - maclo r4, r5 - test_h_accum0 0, 0x20001 - - pass diff --git a/sim/testsuite/sim/m32r/macwhi.cgs b/sim/testsuite/sim/m32r/macwhi.cgs deleted file mode 100644 index 9ee7a5b..0000000 --- a/sim/testsuite/sim/m32r/macwhi.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# m32r testcase for macwhi $src1,$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global macwhi -macwhi: - mvi_h_accum0 0, 1 - mvi_h_gr r4, 0x10123 - mvi_h_gr r5, 0x20456 - - macwhi r4, r5 - - test_h_accum0 0, 0x20247 - - pass diff --git a/sim/testsuite/sim/m32r/macwlo.cgs b/sim/testsuite/sim/m32r/macwlo.cgs deleted file mode 100644 index a7ce4ed..0000000 --- a/sim/testsuite/sim/m32r/macwlo.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# m32r testcase for macwlo $src1,$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global macwlo -macwlo: - mvi_h_accum0 0, 1 - mvi_h_gr r4, 0x10123 - mvi_h_gr r5, 0x40002 - - macwlo r4, r5 - - test_h_accum0 0, 0x20247 - - pass diff --git a/sim/testsuite/sim/m32r/misc.exp b/sim/testsuite/sim/m32r/misc.exp deleted file mode 100644 index 6ed5638..0000000 --- a/sim/testsuite/sim/m32r/misc.exp +++ /dev/null @@ -1,21 +0,0 @@ -# Miscellaneous M32R simulator testcases - -if [istarget m32r*-*-*] { - # load support procs - # load_lib cgen.exp - - # all machines - set all_machs "m32r" - - - # The .ms suffix is for "miscellaneous .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/m32r/mul.cgs b/sim/testsuite/sim/m32r/mul.cgs deleted file mode 100644 index c78f24b..0000000 --- a/sim/testsuite/sim/m32r/mul.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for mul $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mul -mul: - mvi_h_gr r4, 3 - mvi_h_gr r5, 7 - - mul r5, r4 - - test_h_gr r5, 21 - - pass diff --git a/sim/testsuite/sim/m32r/mulhi.cgs b/sim/testsuite/sim/m32r/mulhi.cgs deleted file mode 100644 index 77c103d..0000000 --- a/sim/testsuite/sim/m32r/mulhi.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# m32r testcase for mulhi $src1,$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mulhi -mulhi: - - mvi_h_gr r4, 0x40000 - mvi_h_gr r5, 0x50000 - mulhi r4, r5 - test_h_accum0 0, 0x140000 - - pass diff --git a/sim/testsuite/sim/m32r/mullo.cgs b/sim/testsuite/sim/m32r/mullo.cgs deleted file mode 100644 index 11aadff..0000000 --- a/sim/testsuite/sim/m32r/mullo.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# m32r testcase for mullo $src1,$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mullo -mullo: - - mvi_h_gr r4, 4 - mvi_h_gr r5, 5 - mullo r4, r5 - test_h_accum0 0, 0x140000 - - pass diff --git a/sim/testsuite/sim/m32r/mulwhi.cgs b/sim/testsuite/sim/m32r/mulwhi.cgs deleted file mode 100644 index eb18562..0000000 --- a/sim/testsuite/sim/m32r/mulwhi.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# m32r testcase for mulwhi $src1,$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mulwhi -mulwhi: - mvi_h_accum0 0, 1 - mvi_h_gr r4, 0x10123 - mvi_h_gr r5, 0x20456 - - mulwhi r4, r5 - - test_h_accum0 0, 0x20246 - - pass diff --git a/sim/testsuite/sim/m32r/mulwlo.cgs b/sim/testsuite/sim/m32r/mulwlo.cgs deleted file mode 100644 index d22c268..0000000 --- a/sim/testsuite/sim/m32r/mulwlo.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# m32r testcase for mulwlo $src1,$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mulwlo -mulwlo: - mvi_h_accum0 0, 1 - mvi_h_gr r4, 0x10123 - mvi_h_gr r5, 0x40002 - - mulwlo r4, r5 - - test_h_accum0 0, 0x20246 - - pass diff --git a/sim/testsuite/sim/m32r/mv.cgs b/sim/testsuite/sim/m32r/mv.cgs deleted file mode 100644 index 6945695..0000000 --- a/sim/testsuite/sim/m32r/mv.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for mv $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mv -mv: - mvi_h_gr r4, 1 - mvi_h_gr r5, 0 - - mv r5, r4 - - test_h_gr r5, 1 - - pass diff --git a/sim/testsuite/sim/m32r/mvfachi.cgs b/sim/testsuite/sim/m32r/mvfachi.cgs deleted file mode 100644 index 0222e1b..0000000 --- a/sim/testsuite/sim/m32r/mvfachi.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# m32r testcase for mvfachi $dr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mvfachi -mvfachi: - mvi_h_accum0 0x11223344, 0x55667788 - mvi_h_gr r4, 0 - - mvfachi r4 - test_h_gr r4, 0x223344 - - mvi_h_accum0 0x99aabbcc, 0x55667788 - mvi_h_gr r4, 0 - - mvfachi r4 - test_h_gr r4, 0xffaabbcc - - pass diff --git a/sim/testsuite/sim/m32r/mvfaclo.cgs b/sim/testsuite/sim/m32r/mvfaclo.cgs deleted file mode 100644 index 0a88d84..0000000 --- a/sim/testsuite/sim/m32r/mvfaclo.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for mvfaclo $dr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mvfaclo -mvfaclo: - mvi_h_accum0 0x11223344, 0x55667788 - mvi_h_gr r4, 0 - - mvfaclo r4 - - test_h_gr r4, 0x55667788 - - pass diff --git a/sim/testsuite/sim/m32r/mvfacmi.cgs b/sim/testsuite/sim/m32r/mvfacmi.cgs deleted file mode 100644 index 580bcae..0000000 --- a/sim/testsuite/sim/m32r/mvfacmi.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# m32r testcase for mvfacmi $dr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mvfacmi -mvfacmi: - - mvi_h_accum0 0x12345678, 0x87654321 - mvfacmi r4 - test_h_gr r4, 0x56788765 - - pass diff --git a/sim/testsuite/sim/m32r/mvfc.cgs b/sim/testsuite/sim/m32r/mvfc.cgs deleted file mode 100644 index ca2470e..0000000 --- a/sim/testsuite/sim/m32r/mvfc.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# m32r testcase for mvfc $dr,$scr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mvfc -mvfc: - mvi_h_condbit 0 - mvi_h_gr r4, 1 - - mvfc r4, cr1 - - test_h_gr r4, 0 - - mvi_h_condbit 1 - - mvfc r4, cr1 - - test_h_gr r4, 1 - - pass diff --git a/sim/testsuite/sim/m32r/mvtachi.cgs b/sim/testsuite/sim/m32r/mvtachi.cgs deleted file mode 100644 index 6d59616..0000000 --- a/sim/testsuite/sim/m32r/mvtachi.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# m32r testcase for mvtachi $src1 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mvtachi -mvtachi: - mvi_h_accum0 0, 0 - - mvi_h_gr r4, 0x11223344 - mvtachi r4 - test_h_accum0 0x223344, 0x0 - - mvi_h_gr r4, 0x99aabbcc - mvtachi r4 - test_h_accum0 0xffaabbcc, 0x0 - - pass diff --git a/sim/testsuite/sim/m32r/mvtaclo.cgs b/sim/testsuite/sim/m32r/mvtaclo.cgs deleted file mode 100644 index baafd83..0000000 --- a/sim/testsuite/sim/m32r/mvtaclo.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for mvtaclo $src1 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mvtaclo -mvtaclo: - mvi_h_accum0 0, 0 - mvi_h_gr r4, 0x11223344 - - mvtaclo r4 - - test_h_accum0 0, 0x11223344 - - pass diff --git a/sim/testsuite/sim/m32r/mvtc.cgs b/sim/testsuite/sim/m32r/mvtc.cgs deleted file mode 100644 index 94780df..0000000 --- a/sim/testsuite/sim/m32r/mvtc.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# m32r testcase for mvtc $sr,$dcr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global mvtc -mvtc: - mvi_h_condbit 0 - mvi_h_gr r4, 1 - - mvtc r4, cr1 - bc ok - - fail -ok: - pass diff --git a/sim/testsuite/sim/m32r/neg.cgs b/sim/testsuite/sim/m32r/neg.cgs deleted file mode 100644 index 6051efa..0000000 --- a/sim/testsuite/sim/m32r/neg.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for neg $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global neg -neg: - mvi_h_gr r4, 1 - mvi_h_gr r5, 2 - - neg r4, r5 - - test_h_gr r4, -2 - - pass diff --git a/sim/testsuite/sim/m32r/nop.cgs b/sim/testsuite/sim/m32r/nop.cgs deleted file mode 100644 index e06d656..0000000 --- a/sim/testsuite/sim/m32r/nop.cgs +++ /dev/null @@ -1,11 +0,0 @@ -# m32r testcase for nop -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global nop -nop: - nop - pass diff --git a/sim/testsuite/sim/m32r/not.cgs b/sim/testsuite/sim/m32r/not.cgs deleted file mode 100644 index e6ceb64..0000000 --- a/sim/testsuite/sim/m32r/not.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for not $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global not -not: - mvi_h_gr r4, 1 - mvi_h_gr r5, 2 - - not r4, r5 - - test_h_gr r4, 0xfffffffd - - pass diff --git a/sim/testsuite/sim/m32r/or.cgs b/sim/testsuite/sim/m32r/or.cgs deleted file mode 100644 index 1b08bd0..0000000 --- a/sim/testsuite/sim/m32r/or.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for or $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global or -or: - mvi_h_gr r4, 3 - mvi_h_gr r5, 6 - - or r4, r5 - - test_h_gr r4, 7 - - pass diff --git a/sim/testsuite/sim/m32r/or3.cgs b/sim/testsuite/sim/m32r/or3.cgs deleted file mode 100644 index dc76ada..0000000 --- a/sim/testsuite/sim/m32r/or3.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for or3 $dr,$sr,#$ulo16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global or3 -or3: - mvi_h_gr r4, 0 - mvi_h_gr r5, 6 - - or3 r4, r5, #3 - - test_h_gr r4, 7 - - pass diff --git a/sim/testsuite/sim/m32r/rac.cgs b/sim/testsuite/sim/m32r/rac.cgs deleted file mode 100644 index 35b9ae3..0000000 --- a/sim/testsuite/sim/m32r/rac.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# m32r testcase for rac -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global rac -rac: - - mvi_h_accum0 1, 0x4001 - rac - test_h_accum0 2, 0x10000 - - mvi_h_accum0 0x3fff, 0xffff4000 - rac - test_h_accum0 0x7fff, 0xffff0000 - - mvi_h_accum0 0xffff8000, 0 - rac - test_h_accum0 0xffff8000, 0 - - pass diff --git a/sim/testsuite/sim/m32r/rach.cgs b/sim/testsuite/sim/m32r/rach.cgs deleted file mode 100644 index c224698..0000000 --- a/sim/testsuite/sim/m32r/rach.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# m32r testcase for rach -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global rach -rach: - mvi_h_accum0 1, 0x40004001 - rach - test_h_accum0 3, 0 - - mvi_h_accum0 0x3fff, 0xc0000000 - rach - test_h_accum0 0x7fff, 0 - - mvi_h_accum0 0xffff8000, 0 - rach - test_h_accum0 0xffff8000, 0 - - pass diff --git a/sim/testsuite/sim/m32r/rem.cgs b/sim/testsuite/sim/m32r/rem.cgs deleted file mode 100644 index 78c11cb..0000000 --- a/sim/testsuite/sim/m32r/rem.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# m32r testcase for rem $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global rem -rem: - mvi_h_gr r4, 12345678 - mvi_h_gr r5, 7 - - rem r4, r5 - - test_h_gr r4, 2 - - pass diff --git a/sim/testsuite/sim/m32r/remu.cgs b/sim/testsuite/sim/m32r/remu.cgs deleted file mode 100644 index 3633630..0000000 --- a/sim/testsuite/sim/m32r/remu.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# m32r testcase for remu $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global remu -remu: - mvi_h_gr r4, 17 - mvi_h_gr r5, 7 - - remu r4, r5 - - test_h_gr r4, 3 - - mvi_h_gr r4, -17 - - remu r4, r5 - - test_h_gr r4, 1 - - pass diff --git a/sim/testsuite/sim/m32r/rte.cgs b/sim/testsuite/sim/m32r/rte.cgs deleted file mode 100644 index b389fe1..0000000 --- a/sim/testsuite/sim/m32r/rte.cgs +++ /dev/null @@ -1,87 +0,0 @@ -# m32r testcase for rte -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global rte -rte: - -; Test 1: bbpsw = 0, bpsw = 1, psw = 0 - - ; bbsm = 0, bie = 0, bbcond = 0 - mvi_h_gr r4, 0 - mvtc r4, cr8 - - ; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 - mvi_h_gr r4, 0xc100 - mvtc r4, cr0 - - ; bbpc = 0 - mvaddr_h_gr r4, 0 - mvtc r4, bbpc - - ; bpc = ret1 - mvaddr_h_gr r4, ret1 - mvtc r4, bpc - - rte - fail - -ret1: - ; test bbsm = 0, bbie = 0, bbcond = 0 - mvfc r4, cr8 - test_h_gr r4, 0 - - ; test bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 - mvfc r4, cr0 - test_h_gr r4, 0xc1 - - ; test bbpc = 0 - mvfc r4, bbpc - test_h_gr r4, 0 - - ; test bpc = 0 - mvfc r4, bpc - test_h_gr r4, 0 - -; Test 2: bbpsw = 1, bpsw = 0, psw = 1 - - ; bbsm = 1, bie = 1, bbcond = 1 - mvi_h_gr r4, 0xc1 - mvtc r4, cr8 - - ; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 - mvi_h_gr r4, 0xc1 - mvtc r4, cr0 - - ; bbpc = 42 - mvaddr_h_gr r4, 42 - mvtc r4, bbpc - - ; bpc = ret2 + 2 - mvaddr_h_gr r4, ret2 + 2 - mvtc r4, bpc - - rte - fail - -ret2: - ; test bbsm = 1, bbie = 1, bbcond = 1 - mvfc r4, cr8 - test_h_gr r4, 0xc1 - - ; test bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 - mvfc r4, cr0 - test_h_gr r4, 0xc100 - - ; test bbpc = 42 - mvfc r4, bbpc - test_h_gr r4, 42 - - ; test bpc = 42 - mvfc r4, bpc - test_h_gr r4, 42 - - pass diff --git a/sim/testsuite/sim/m32r/seth.cgs b/sim/testsuite/sim/m32r/seth.cgs deleted file mode 100644 index aec3230..0000000 --- a/sim/testsuite/sim/m32r/seth.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# m32r testcase for seth $dr,#$hi16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global seth -seth: - seth r4, #0x1234 - - ; do not use test_h_gr macro since this uses seth - - srli r4, #16 - ld24 r5, #0x1234 - beq r4, r5, ok - - fail -ok: - pass diff --git a/sim/testsuite/sim/m32r/sll.cgs b/sim/testsuite/sim/m32r/sll.cgs deleted file mode 100644 index fa3cfed..0000000 --- a/sim/testsuite/sim/m32r/sll.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# m32r testcase for sll $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global sll -sll: - mvi_h_gr r4, 6 - mvi_h_gr r5, 1 - sll r4, r5 - test_h_gr r4, 12 - - pass diff --git a/sim/testsuite/sim/m32r/sll3.cgs b/sim/testsuite/sim/m32r/sll3.cgs deleted file mode 100644 index ddd360c..0000000 --- a/sim/testsuite/sim/m32r/sll3.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# m32r testcase for sll3 $dr,$sr,#$simm16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global sll3 -sll3: - mvi_h_gr r4, 1 - mvi_h_gr r5, 6 - sll3 r4, r5, #1 - test_h_gr r4, 12 - - pass diff --git a/sim/testsuite/sim/m32r/slli.cgs b/sim/testsuite/sim/m32r/slli.cgs deleted file mode 100644 index eab77da..0000000 --- a/sim/testsuite/sim/m32r/slli.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# m32r testcase for slli $dr,#$uimm5 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global slli -slli: - mvi_h_gr r4, 6 - slli r4, #1 - test_h_gr r4, 12 - - pass diff --git a/sim/testsuite/sim/m32r/sra.cgs b/sim/testsuite/sim/m32r/sra.cgs deleted file mode 100644 index 11671ed..0000000 --- a/sim/testsuite/sim/m32r/sra.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# m32r testcase for sra $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global sra -sra: - - mvi_h_gr r4, 0xf0f0f0ff - mvi_h_gr r5, 4 - sra r4, r5 - test_h_gr r4, 0xff0f0f0f - - pass diff --git a/sim/testsuite/sim/m32r/sra3.cgs b/sim/testsuite/sim/m32r/sra3.cgs deleted file mode 100644 index 0dd387a..0000000 --- a/sim/testsuite/sim/m32r/sra3.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# m32r testcase for sra3 $dr,$sr,#$simm16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global sra3 -sra3: - - mvi_h_gr r4, 0 - mvi_h_gr r5, 0xf0f0f0ff - sra3 r4, r5, #4 - test_h_gr r4, 0xff0f0f0f - - pass diff --git a/sim/testsuite/sim/m32r/srai.cgs b/sim/testsuite/sim/m32r/srai.cgs deleted file mode 100644 index 2a15694..0000000 --- a/sim/testsuite/sim/m32r/srai.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# m32r testcase for srai $dr,#$uimm5 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global srai -srai: - mvi_h_gr r5, 0xf0f0f0ff - srai r5, #4 - test_h_gr r5, 0xff0f0f0f - - pass diff --git a/sim/testsuite/sim/m32r/srl.cgs b/sim/testsuite/sim/m32r/srl.cgs deleted file mode 100644 index 8838c2f..0000000 --- a/sim/testsuite/sim/m32r/srl.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# m32r testcase for srl $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global srl -srl: - mvi_h_gr r4, 6 - mvi_h_gr r5, 1 - srl r4, r5 - test_h_gr r4, 3 - - pass diff --git a/sim/testsuite/sim/m32r/srl3.cgs b/sim/testsuite/sim/m32r/srl3.cgs deleted file mode 100644 index a1dc484..0000000 --- a/sim/testsuite/sim/m32r/srl3.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# m32r testcase for srl3 $dr,$sr,#$simm16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global srl3 -srl3: - mvi_h_gr r4, 0 - mvi_h_gr r5, 6 - srl3 r4, r5, #1 - test_h_gr r4, 3 - - pass diff --git a/sim/testsuite/sim/m32r/srli.cgs b/sim/testsuite/sim/m32r/srli.cgs deleted file mode 100644 index f358a76..0000000 --- a/sim/testsuite/sim/m32r/srli.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# m32r testcase for srli $dr,#$uimm5 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global srli -srli: - mvi_h_gr r5, 6 - srli r5, #1 - test_h_gr r5, 3 - - - pass diff --git a/sim/testsuite/sim/m32r/st-d.cgs b/sim/testsuite/sim/m32r/st-d.cgs deleted file mode 100644 index e2668a0..0000000 --- a/sim/testsuite/sim/m32r/st-d.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# m32r testcase for st $src1,@($slo16,$src2) -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global st_d -st_d: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 1 - - st r5, @(#8,r4) - - mvaddr_h_gr r4, data_loc2 - ld r4, @r4 - test_h_gr r4, 1 - - pass - -data_loc: - .word 0 - .word 0 -data_loc2: - .word 0 - diff --git a/sim/testsuite/sim/m32r/st-minus.cgs b/sim/testsuite/sim/m32r/st-minus.cgs deleted file mode 100644 index fc90351..0000000 --- a/sim/testsuite/sim/m32r/st-minus.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# m32r testcase for st $src1,@-$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global st_minus -st_minus: - mvaddr_h_gr r4, data_loc2 - mvi_h_gr r5, 1 - - st r5, @-r4 - - mvaddr_h_gr r5, data_loc - - bne r4, r5, not_ok - ld r4, @r4 - test_h_gr r4, 1 - - pass -not_ok: - fail - -data_loc: - .word 0 -data_loc2: - .word 0 - diff --git a/sim/testsuite/sim/m32r/st-plus.cgs b/sim/testsuite/sim/m32r/st-plus.cgs deleted file mode 100644 index 7bb4dd1..0000000 --- a/sim/testsuite/sim/m32r/st-plus.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# m32r testcase for st $src1,@+$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global st_plus -st_plus: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 1 - - st r5, @+r4 - - mvaddr_h_gr r5, data_loc2 - - bne r4, r5, not_ok - ld r4, @r4 - test_h_gr r4, 1 - - pass -not_ok: - fail - -data_loc: - .word 0 -data_loc2: - .word 0 diff --git a/sim/testsuite/sim/m32r/st.cgs b/sim/testsuite/sim/m32r/st.cgs deleted file mode 100644 index 9588b8c..0000000 --- a/sim/testsuite/sim/m32r/st.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# m32r testcase for st $src1,@$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global st -st: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 1 - - st r5, @r4 - - ld r4, @r4 - test_h_gr r4, 1 - - pass - -data_loc: - .word 0 diff --git a/sim/testsuite/sim/m32r/stb-d.cgs b/sim/testsuite/sim/m32r/stb-d.cgs deleted file mode 100644 index 37c2d73..0000000 --- a/sim/testsuite/sim/m32r/stb-d.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# m32r testcase for stb $src1,@($slo16,$src2) -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global stb_d -stb_d: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0x1234 - - stb r5, @(#8,r4) - - mvaddr_h_gr r4, data_loc2 - ld r4, @r4 - test_h_gr r4, 0x34000000 ; big endian processor - - pass - -data_loc: - .word 0 - .word 0 -data_loc2: - .word 0 diff --git a/sim/testsuite/sim/m32r/stb.cgs b/sim/testsuite/sim/m32r/stb.cgs deleted file mode 100644 index 0128316..0000000 --- a/sim/testsuite/sim/m32r/stb.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# m32r testcase for stb $src1,@$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global stb -stb: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0x1234 - - stb r5, @r4 - - ld r4, @r4 - test_h_gr r4, 0x34000000 ; big endian processor - - pass - -data_loc: - .word 0 diff --git a/sim/testsuite/sim/m32r/sth-d.cgs b/sim/testsuite/sim/m32r/sth-d.cgs deleted file mode 100644 index 11aaa6d..0000000 --- a/sim/testsuite/sim/m32r/sth-d.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# m32r testcase for sth $src1,@($slo16,$src2) -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global sth_d -sth_d: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0x123456 - - sth r5, @(#8,r4) - - mvaddr_h_gr r4, data_loc2 - ld r4, @r4 - test_h_gr r4, 0x34560000 ; big endian processor - - pass - -data_loc: - .word 0 - .word 0 -data_loc2: - .word 0 diff --git a/sim/testsuite/sim/m32r/sth.cgs b/sim/testsuite/sim/m32r/sth.cgs deleted file mode 100644 index 1a10fde..0000000 --- a/sim/testsuite/sim/m32r/sth.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# m32r testcase for sth $src1,@$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global sth -sth: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 0x123456 - - sth r5, @r4 - - ld r4, @r4 - test_h_gr r4, 0x34560000 ; big endian processor - - pass - -data_loc: - .word 0 diff --git a/sim/testsuite/sim/m32r/sub.cgs b/sim/testsuite/sim/m32r/sub.cgs deleted file mode 100644 index 4d676e5..0000000 --- a/sim/testsuite/sim/m32r/sub.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# m32r testcase for sub $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global sub -sub: - - mvi_h_gr r4, 7 - mvi_h_gr r5, 3 - - sub r4, r5 - - test_h_gr r4, 4 - - pass diff --git a/sim/testsuite/sim/m32r/subv.cgs b/sim/testsuite/sim/m32r/subv.cgs deleted file mode 100644 index 9474766..0000000 --- a/sim/testsuite/sim/m32r/subv.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# m32r testcase for subv $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global subv -subv: - mvi_h_condbit 0 - mvi_h_gr r4, 0x80000000 - mvi_h_gr r5, 3 - - subv r4, r5 - - bc ok - - fail -ok: - pass diff --git a/sim/testsuite/sim/m32r/subx.cgs b/sim/testsuite/sim/m32r/subx.cgs deleted file mode 100644 index e890fcf..0000000 --- a/sim/testsuite/sim/m32r/subx.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# m32r testcase for subx $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global subx -subx: - mvi_h_condbit 1 - mvi_h_gr r4, 6 - mvi_h_gr r5, 4 - subx r4, r5 - bc not_ok - test_h_gr r4, 1 - - mvi_h_condbit 1 - mvi_h_gr r4, 4 - mvi_h_gr r5, 4 - subx r4, r5 - bnc not_ok - test_h_gr r4, 0xffffffff - - pass -not_ok: - fail diff --git a/sim/testsuite/sim/m32r/testutils.inc b/sim/testsuite/sim/m32r/testutils.inc deleted file mode 100644 index 1d8822a..0000000 --- a/sim/testsuite/sim/m32r/testutils.inc +++ /dev/null @@ -1,95 +0,0 @@ -# r0-r3 are used as tmps, consider them call clobbered by these macros. - - .macro start - .data -failmsg: - .ascii "fail\n" -passmsg: - .ascii "pass\n" - .text - .global _start -_start: - .endm - - .macro exit rc - ldi8 r1, \rc - ldi8 r0, #1 - trap #0 - .endm - - .macro pass - ldi8 r3, 5 - ld24 r2, passmsg - ldi8 r1, 1 - ldi8 r0, 5 - trap #0 - exit 0 - .endm - - .macro fail - ldi8 r3, 5 - ld24 r2, failmsg - ldi8 r1, 1 - ldi8 r0, 5 - trap #0 - exit 1 - .endm - - .macro mvi_h_gr reg, val - .if (\val >= -128) && (\val <= 127) - ldi8 \reg, \val - .else - seth \reg, high(\val) - or3 \reg, \reg, low(\val) - .endif - .endm - - .macro mvaddr_h_gr reg, addr - seth \reg, high(\addr) - or3 \reg, \reg, low(\addr) - .endm - -# Other macros know this only clobbers r0. - .macro test_h_gr reg, val - mvaddr_h_gr r0, \val - beq \reg, r0, test_gr\@ - fail -test_gr\@: - .endm - - .macro mvi_h_condbit val - ldi8 r0, 0 - ldi8 r1, 1 - .if \val - cmp r0, r1 - .else - cmp r1, r0 - .endif - .endm - - .macro test_h_condbit val - .if \val - bc test_c1\@ - fail -test_c1\@: - .else - bnc test_c0\@ - fail -test_c0\@: - .endif - .endm - - .macro mvi_h_accum0 hi, lo - mvi_h_gr r0, \hi - mvtachi r0 - mvi_h_gr r0, \lo - mvtaclo r0 - .endm - - .macro test_h_accum0 hi, lo - mvfachi r1 - test_h_gr r1, \hi - mvfaclo r1 - test_h_gr r1, \lo - .endm - diff --git a/sim/testsuite/sim/m32r/trap.cgs b/sim/testsuite/sim/m32r/trap.cgs deleted file mode 100644 index 59e136a..0000000 --- a/sim/testsuite/sim/m32r/trap.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# m32r testcase for trap #$uimm4 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global trap -trap: - -; Test 1: bbpsw = 0, bpsw = 1, psw = 0 - - ; bbsm = 0, bie = 0, bbcond = 0 - mvi_h_gr r4, 0 - mvtc r4, cr8 - - ; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 - mvi_h_gr r4, 0xc100 - mvtc r4, cr0 - - ; bbpc = 0 - mvaddr_h_gr r4, 0 - mvtc r4, bbpc - - ; bpc = 42 - mvaddr_h_gr r4, 42 - mvtc r4, bpc - - ; Copy trap2_handler to trap area of memory. - ld24 r0,#0x48 ; address of trap 2 handler - ld24 r1,#trap2_handler - ld r2,@r1 - st r2,@r0 - ; Set up return address. - ld24 r5,#trap2_ret1 - -trap_insn1: - trap #2 - fail - -trap2_ret1: - ; test bbsm = 1, bbie = 1, bbcond = 1 - mvfc r4, cr8 - test_h_gr r4, 0xc1 - - ; test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0 - mvfc r4, cr0 - test_h_gr r4, 0 - - ; test bbpc = 42 - mvfc r4, bbpc - test_h_gr r4, 42 - - ; test bpc = proper return address - mvfc r4, bpc - test_h_gr r4, trap_insn1 + 4 - -; Test 2: bbpsw = 1, bpsw = 0, psw = 1 - - ; bbsm = 1, bie = 1, bbcond = 1 - mvi_h_gr r4, 0xc1 - mvtc r4, cr8 - - ; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 - mvi_h_gr r4, 0xc1 - mvtc r4, cr0 - - ; bbpc = 42 - mvaddr_h_gr r4, 42 - mvtc r4, bbpc - - ; bpc = 0 - mvaddr_h_gr r4, 0 - mvtc r4, bpc - - ; Set up return address. - ld24 r5,#trap2_ret2 - -trap_insn2: - trap #2 - fail - -trap2_ret2: - ; test bbsm = 0, bbie = 0, bbcond = 0 - mvfc r4, cr8 - test_h_gr r4, 0 - - ; test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0 - mvfc r4, cr0 - test_h_gr r4, 0xc180 - - ; test bbpc = 0 - mvfc r4, bbpc - test_h_gr r4, 0 - - ; test bpc = proper return address - mvfc r4, bpc - test_h_gr r4, trap_insn2 + 4 - - pass - - .data - -; Don't use rte as it will undo the effects of trap we're testing. - - .p2align 2 -trap2_handler: - jmp r5 - nop diff --git a/sim/testsuite/sim/m32r/unlock.cgs b/sim/testsuite/sim/m32r/unlock.cgs deleted file mode 100644 index 1a51b7a..0000000 --- a/sim/testsuite/sim/m32r/unlock.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# m32r testcase for unlock $src1,@$src2 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global unlock -unlock: - mvaddr_h_gr r4, data_loc - mvi_h_gr r5, 1 - - lock r5, @r4 - - mvi_h_gr r5, 2 - unlock r5, @r4 - - ld r6, @r4 - test_h_gr r6, 2 - - mvi_h_gr r5, 0 - unlock r5, @r4 ; This should be a nop since the processor should be unlocked. - - ld r6, @r4 - test_h_gr r6, 2 - - pass - -data_loc: - .word 0 diff --git a/sim/testsuite/sim/m32r/uread16.ms b/sim/testsuite/sim/m32r/uread16.ms deleted file mode 100644 index 550e99a..0000000 --- a/sim/testsuite/sim/m32r/uread16.ms +++ /dev/null @@ -1,18 +0,0 @@ -# mach: m32r m32rx -# xerror: -# output: *misaligned read* - - .include "testutils.inc" - - start - -; construct bra trap2_handler in trap 2 slot - ld24 r0,#foo+1 - ldh r0,@r0 - fail - exit 0 - -.data - .p2align 2 -foo: - .short 42 diff --git a/sim/testsuite/sim/m32r/uread32.ms b/sim/testsuite/sim/m32r/uread32.ms deleted file mode 100644 index 935c716..0000000 --- a/sim/testsuite/sim/m32r/uread32.ms +++ /dev/null @@ -1,18 +0,0 @@ -# mach: m32r m32rx -# xerror: -# output: *misaligned read* - - .include "testutils.inc" - - start - -; construct bra trap2_handler in trap 2 slot - ld24 r0,#foo+1 - ld r0,@r0 - fail - exit 0 - -.data - .p2align 2 -foo: - .word 42 diff --git a/sim/testsuite/sim/m32r/uwrite16.ms b/sim/testsuite/sim/m32r/uwrite16.ms deleted file mode 100644 index 11bfd6e..0000000 --- a/sim/testsuite/sim/m32r/uwrite16.ms +++ /dev/null @@ -1,18 +0,0 @@ -# mach: m32r m32rx -# xerror: -# output: *misaligned write* - - .include "testutils.inc" - - start - -; construct bra trap2_handler in trap 2 slot - ld24 r0,#foo+1 - sth r0,@r0 - fail - exit 0 - -.data - .p2align 2 -foo: - .short 42 diff --git a/sim/testsuite/sim/m32r/uwrite32.ms b/sim/testsuite/sim/m32r/uwrite32.ms deleted file mode 100644 index 495a123..0000000 --- a/sim/testsuite/sim/m32r/uwrite32.ms +++ /dev/null @@ -1,18 +0,0 @@ -# mach: m32r m32rx -# xerror: -# output: *misaligned write* - - .include "testutils.inc" - - start - -; construct bra trap2_handler in trap 2 slot - ld24 r0,#foo+1 - st r0,@r0 - fail - exit 0 - -.data - .p2align 2 -foo: - .word 42 diff --git a/sim/testsuite/sim/m32r/xor.cgs b/sim/testsuite/sim/m32r/xor.cgs deleted file mode 100644 index 254da79..0000000 --- a/sim/testsuite/sim/m32r/xor.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# m32r testcase for xor $dr,$sr -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global xor -xor: - - mvi_h_gr r4, 3 - mvi_h_gr r5, 6 - xor r4, r5 - test_h_gr r4, 5 - - pass diff --git a/sim/testsuite/sim/m32r/xor3.cgs b/sim/testsuite/sim/m32r/xor3.cgs deleted file mode 100644 index eee7269..0000000 --- a/sim/testsuite/sim/m32r/xor3.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# m32r testcase for xor3 $dr,$sr,#$uimm16 -# mach(): m32r m32rx - - .include "testutils.inc" - - start - - .global xor3 -xor3: - - mvi_h_gr r5, 0 - mvi_h_gr r4, 3 - xor3 r5, r4, #6 - test_h_gr r5, 5 - - pass diff --git a/sim/testsuite/sim/m68hc11/ChangeLog b/sim/testsuite/sim/m68hc11/ChangeLog deleted file mode 100644 index d3f8b9d..0000000 --- a/sim/testsuite/sim/m68hc11/ChangeLog +++ /dev/null @@ -1,3 +0,0 @@ -2015-04-05 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/sim/m68hc11/allinsn.exp b/sim/testsuite/sim/m68hc11/allinsn.exp deleted file mode 100644 index db0cbd5..0000000 --- a/sim/testsuite/sim/m68hc11/allinsn.exp +++ /dev/null @@ -1,15 +0,0 @@ -# m68hc11 simulator testsuite - -if [istarget m68hc11-*] { - # all machines - set all_machs "m68hc11" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/m68hc11/pass.s b/sim/testsuite/sim/m68hc11/pass.s deleted file mode 100644 index 302a7fb..0000000 --- a/sim/testsuite/sim/m68hc11/pass.s +++ /dev/null @@ -1,7 +0,0 @@ -# check that the sim doesn't die immediately. -# mach: m68hc11 - -.include "testutils.inc" - - start - pass diff --git a/sim/testsuite/sim/m68hc11/testutils.inc b/sim/testsuite/sim/m68hc11/testutils.inc deleted file mode 100644 index 3d30de2..0000000 --- a/sim/testsuite/sim/m68hc11/testutils.inc +++ /dev/null @@ -1,53 +0,0 @@ -# MACRO: exit - .macro exit nr - ldd # \nr - # The debug insn class. - .byte 0xcd - # The exit utility function. - .byte 0x03 - .endm - -# MACRO: pass -# Write 'pass' to stdout and quit - .macro pass - # Point to the string. - # NB: See comment above _pass below. - ldx #0x8000 - # Number of bytes to write. - ldd #5 - # The debug insn class. - .byte 0xcd - # The write utility function. - .byte 0x01 - exit 0 - .endm - -# MACRO: ffail -# Write 'ffail' to stdout and quit -# Normally this would be 'fail', but m68k has a pseudo "fail" op. - .macro ffail - # Point to the string. - ldx #0x8006 - # Number of bytes to write. - ldd #5 - # The debug insn class. - .byte 0xcd - # The write utility function. - .byte 0x01 - exit 0 - .endm - -# MACRO: start -# All assembler tests should start with a call to "start" - .macro start - .text -# These need to be at the start of text as it's the only stable address. -# The sim will load all sections starting at the .text address and ignore -# the addresses for the other sections. -_pass: - .asciz "pass\n" -_fail: - .asciz "fail\n" -.global _start -_start: - .endm diff --git a/sim/testsuite/sim/mcore/ChangeLog b/sim/testsuite/sim/mcore/ChangeLog deleted file mode 100644 index b0e7908..0000000 --- a/sim/testsuite/sim/mcore/ChangeLog +++ /dev/null @@ -1,8 +0,0 @@ -2015-11-15 Mike Frysinger - - * fail.s: New test. - * testutils.inc (fail): Fix exit code. - -2015-03-29 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/sim/mcore/allinsn.exp b/sim/testsuite/sim/mcore/allinsn.exp deleted file mode 100644 index 5921cfc..0000000 --- a/sim/testsuite/sim/mcore/allinsn.exp +++ /dev/null @@ -1,15 +0,0 @@ -# mcore simulator testsuite - -if [istarget mcore-*] { - # all machines - set all_machs "mcore" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/mcore/fail.s b/sim/testsuite/sim/mcore/fail.s deleted file mode 100644 index 10e3b23..0000000 --- a/sim/testsuite/sim/mcore/fail.s +++ /dev/null @@ -1,8 +0,0 @@ -# check that the sim doesn't die immediately. -# mach: mcore -# xerror: - -.include "testutils.inc" - - start - fail diff --git a/sim/testsuite/sim/mcore/pass.s b/sim/testsuite/sim/mcore/pass.s deleted file mode 100644 index 92fada0..0000000 --- a/sim/testsuite/sim/mcore/pass.s +++ /dev/null @@ -1,7 +0,0 @@ -# check that the sim doesn't die immediately. -# mach: mcore - -.include "testutils.inc" - - start - pass diff --git a/sim/testsuite/sim/mcore/testutils.inc b/sim/testsuite/sim/mcore/testutils.inc deleted file mode 100644 index f5be06d..0000000 --- a/sim/testsuite/sim/mcore/testutils.inc +++ /dev/null @@ -1,52 +0,0 @@ -# MACRO: exit - .macro exit nr - movi r2, \nr - # The exit utility function. - .byte 0x00 - # The debug insn class. - .byte 0x50 - .endm - -# MACRO: pass -# Write 'pass' to stdout and quit - .macro pass - # Trap function 4: write(). - movi r1, 4; - # Use stdout. - movi r2, 1; - # Point to the string. - lrw r3, 1f; - # Number of bytes to write. - movi r4, 5; - # Trigger OS trap. - trap 1; - exit 0 - .data - 1: .asciz "pass\n" - .endm - -# MACRO: fail -# Write 'fail' to stdout and quit - .macro fail - # Trap function 4: write(). - movi r1, 4; - # Use stdout. - movi r2, 1; - # Point to the string. - lrw r3, 1f; - # Number of bytes to write. - movi r4, 5; - # Trigger OS trap. - trap 1; - exit 1 - .data - 1: .asciz "fail\n" - .endm - -# MACRO: start -# All assembler tests should start with a call to "start" - .macro start - .text -.global _start -_start: - .endm diff --git a/sim/testsuite/sim/microblaze/ChangeLog b/sim/testsuite/sim/microblaze/ChangeLog deleted file mode 100644 index 2aa1f2c..0000000 --- a/sim/testsuite/sim/microblaze/ChangeLog +++ /dev/null @@ -1,3 +0,0 @@ -2015-03-29 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/sim/microblaze/allinsn.exp b/sim/testsuite/sim/microblaze/allinsn.exp deleted file mode 100644 index f756914..0000000 --- a/sim/testsuite/sim/microblaze/allinsn.exp +++ /dev/null @@ -1,15 +0,0 @@ -# microblaze simulator testsuite - -if [istarget microblaze-*] { - # all machines - set all_machs "microblaze" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/microblaze/pass.s b/sim/testsuite/sim/microblaze/pass.s deleted file mode 100644 index 93ed924..0000000 --- a/sim/testsuite/sim/microblaze/pass.s +++ /dev/null @@ -1,8 +0,0 @@ -# check that the sim doesn't die immediately. -# mach: microblaze -# output: - -.include "testutils.inc" - - start - pass diff --git a/sim/testsuite/sim/microblaze/testutils.inc b/sim/testsuite/sim/microblaze/testutils.inc deleted file mode 100644 index 158a3c5..0000000 --- a/sim/testsuite/sim/microblaze/testutils.inc +++ /dev/null @@ -1,29 +0,0 @@ -# MACRO: exit - .macro exit nr - addi r3, r0, \nr; - bri 0; - .endm - -# MACRO: pass -# Write 'pass' to stdout and quit - .macro pass - exit 0 - .data - 1: .asciz "pass\n" - .endm - -# MACRO: fail -# Write 'fail' to stdout and quit - .macro fail - exit 1 - .data - 1: .asciz "fail\n" - .endm - -# MACRO: start -# All assembler tests should start with a call to "start" - .macro start - .text -.global _start -_start: - .endm diff --git a/sim/testsuite/sim/mips/ChangeLog b/sim/testsuite/sim/mips/ChangeLog deleted file mode 100644 index ea95441..0000000 --- a/sim/testsuite/sim/mips/ChangeLog +++ /dev/null @@ -1,118 +0,0 @@ -2016-01-06 Joel Brobecker - - * hilo-hazard-4.s: Change copyright ownder to FSF. - -2015-09-25 Andrew Bennett - Ali Lown - - * basic.exp (run_micromips_test, run_sim_tests): New functions - Add support for micromips tests. - * hilo-hazard-4.s: New file. - * testutils.inc (_dowrite): Changed reserved instruction encoding. - (writemsg): Moved the la and li instructions before the data they are - assigned to, which prevents a bug where MIPS32 relocations are used - instead of micromips relocations when building for micromips. - -2015-04-13 Hans-Peter Nilsson - - * basic.exp: Don't unset target ldscript here. - -2011-01-06 Hans-Peter Nilsson - - * testutils.inc: Correct comment syntax fallout from - copyright update. - * utils-dsp.inc, utils-fpu.inc, utils-mdmx.inc: Ditto. - - * mips32-dsp.s: Update copyright year. - -2010-04-26 Mike Frysinger - - * basic.exp: Delete sim target check. - -2007-08-27 Joel Brobecker - - * testutils.inc: Change license to GPL version 3. - * utils-dsp.inc: Change license to GPL version 3. - * utils-fpu.inc: Change license to GPL version 3. - * utils-mdmx.inc: Change license to GPL version 3. - -2007-02-20 Thiemo Seufer - Chao-Ying Fu - * basic.exp: Run the dsp2 test. - * utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro. - * mips32-dsp2.s: New test. - -2007-02-17 Thiemo Seufer - - * basic.exp: Add case for mips*-sde-elf*. - (mdmxmodels): Run mdmx tests only on mdmx capable configurations. - -2007-02-13 Thiemo Seufer - - * mips32-dsp.s: Run DSP testcase only for release 2 architecture. - -2007-02-13 Thiemo Seufer - - * mdmx-ob.s: Delete extraneous include. - -2006-11-08 Thiemo Seufer - - * basic.exp: Fix spelling in comment. Use canonical form of target - patterns. Run DSP test only for DSP-capable ISAs. Check also mips32r2 - and mips64r2 if supported by the target. - -2006-08-08 Chris Dearman - - * testutils.inc (setup): __start is also a valid start symbol. - -2006-05-15 Chao-ying Fu - - * mips32-dsp.s: Add some tests for shra_r.ph, shrav_r.ph, shra_r.w, - shrav_r.w. - -2005-12-14 Chao-ying Fu - - * basic.exp: Run the dsp test. - * utils-dsp.inc: New file. - * mips32-dsp.s: New test. - -2004-04-11 Chris Demetriou - - * utils-fpu.inc (enable_fpu, ckm_fp_cc): New macros. - (clrset_fp_cc): Fix mask used for upper 7 condition codes. - * utils-mdmx.inc: Include utils-fpu.inc. - (enable_mdmx): Use enable_fpu. - -2004-04-10 Chris Demetriou - - * utils-fpu.inc: New file. - * utils-mdmx.inc: New file. - * mdmx-ob.s: New file. - * mdmx-ob-sb1.s: New file. - * basic.exp: Run new mdmx-ob and mdmx-ob-sb1 tests. - -2004-04-10 Chris Demetriou - - * fpu64-ps-sb1.s: New file. - * basic.exp: Recognize mipsisa64sb1 targets, and run fpu64-ps-sb1.s - if appropriate. - -2004-04-10 Chris Demetriou - - * fpu64-ps.s: New file. - * basic.exp: Run fpu64-ps.s. - -2004-03-29 Richard Sandiford - - * hilo-hazard-[123].s: New files. - * basic.exp (run_hilo_test): New procedure. - (models): Only list models that are included in the configuration. - (submodels): New variable, set to submodels of the above. - (mips64vr-*-elf, mips64vrel-*-elf): New configuration stanza. - Run hilo-hazard-[123].s. - -2004-01-26 Chris Demetriou - - * basic.exp: New file. - * testutils.inc: New file. - * sanity.s: New file. diff --git a/sim/testsuite/sim/mips/basic.exp b/sim/testsuite/sim/mips/basic.exp deleted file mode 100644 index f810741..0000000 --- a/sim/testsuite/sim/mips/basic.exp +++ /dev/null @@ -1,106 +0,0 @@ -# MIPS simulator instruction tests - -# Do "run_sim_test TESTFILE MODELS" for each combination of the -# mf{lo,hi} -> mult/div/mt{lo,hi} hazard described in mips.igen. -# Insert NOPS nops after the mflo or mfhi. -proc run_hilo_test {testfile models nops} { - foreach reg {lo hi} { - foreach insn "{mult\t\$4,\$4} {div\t\$0,\$4,\$4} {mt$reg\t\$4}" { - set contents "" - append contents "\t.macro hilo\n" - append contents "\tmf$reg\t\$4\n" - append contents "\t.rept\t$nops\n" - append contents "\tnop\n" - append contents "\t.endr\n" - append contents "\t$insn\n" - append contents "\t.endm" - - verbose -log "HILO test:\n$contents" - set file [open hilo-hazard.inc w] - puts $file $contents - close $file - - run_sim_test $testfile $models - } - } -} - -# Runs micromips tests by adding -mmicromips to as options -proc run_micromips_test { name requested_machs } { - global global_as_options; - set gas_old $global_as_options; - append global_as_options " -mmicromips " - run_sim_test $name $requested_machs - set global_as_options $gas_old -} - -# Runs all specified tests -proc run_sim_tests { name requested_machs { requested_micromips_machs "" } } { - run_sim_test $name $requested_machs - run_micromips_test $name $requested_micromips_machs -} - -# Only test mips*-*-elf (e.g., no mips*-*-linux) -if {[istarget mips*-*-elf]} { - - set dspmodels "" - set mdmxmodels "" - set micromipsmodels "" - set micromipsdspmodels "" - - if {[istarget mipsisa64sb1*-*-elf]} { - set models "sb1" - set submodels "mips1 mips2 mips3 mips4 mips32 mips64" - append mdmxmodels " mips64" - } elseif {[istarget mipsisa64*-*-elf]} { - set models "mips32 mips64 mips32r2 mips64r2" - set submodels "mips1 mips2 mips3 mips4" - append dspmodels " mips32r2 mips64r2" - append mdmxmodels " mips64 mips32r2 mips64r2" - } elseif {[istarget mips*-sde-elf*] || [istarget mips*-mti-elf*]} { - set models "mips32 mips64 mips32r2 mips64r2" - set submodels "" - append dspmodels " mips32r2 mips64r2" - append mdmxmodels " mips64 mips32r2 mips64r2" - append micromipsmodels " mips32r2" - append micromipsdspmodels " mips32r2 mips64r2" - } elseif {[istarget mipsisa32*-*-elf]} { - set models "mips32 mips32r2" - set submodels "mips1 mips2" - append dspmodels " mips32r2" - append mdmxmodels " mips32r2" - append micromipsmodels " mips32r2" - append micromipsdspmodels " mips32r2" - } elseif {[istarget mips64vr*-*-elf]} { - set models "vr4100 vr4111 vr4120 vr5000 vr5400 vr5500" - set submodels "mips1 mips2 mips3 mips4" - } elseif {[istarget mips64*-*-elf]} { - set models "mips3" - set submodels "mips1 mips2" - } else { - # fall back to just testing mips1 code. - set models "mips1" - set submodels "" - } - append submodels " " $models - set cpu_option -march - - run_sim_tests sanity.s $submodels $micromipsmodels - - foreach nops {0 1} { - run_hilo_test hilo-hazard-1.s $models $nops - run_hilo_test hilo-hazard-2.s $models $nops - } - run_hilo_test hilo-hazard-3.s $models 2 - run_hilo_test hilo-hazard-4.s $micromipsmodels 2 - - run_sim_test fpu64-ps.s $submodels - run_sim_test fpu64-ps-sb1.s $submodels - - run_sim_test mdmx-ob.s $mdmxmodels - run_sim_test mdmx-ob-sb1.s $mdmxmodels - - run_sim_tests mips32-dsp.s $dspmodels $micromipsdspmodels - run_sim_tests mips32-dsp2.s $dspmodels $micromipsdspmodels - -} diff --git a/sim/testsuite/sim/mips/fpu64-ps-sb1.s b/sim/testsuite/sim/mips/fpu64-ps-sb1.s deleted file mode 100644 index a39d079..0000000 --- a/sim/testsuite/sim/mips/fpu64-ps-sb1.s +++ /dev/null @@ -1,72 +0,0 @@ -# mips test sanity, expected to pass. -# mach: sb1 -# as: -mabi=eabi -# ld: -N -Ttext=0x80010000 -# output: *\\npass\\n - - .include "testutils.inc" - - .macro check_ps psval, upperval, lowerval - .set push - .set noreorder - cvt.s.pu $f0, \psval # upper - cvt.s.pl $f2, \psval # lower - li.s $f4, \upperval - li.s $f6, \lowerval - c.eq.s $fcc0, $f0, $f4 - bc1f $fcc0, _fail - c.eq.s $fcc0, $f2, $f6 - bc1f $fcc0, _fail - nop - .set pop - .endm - - setup - - .set noreorder - - .ent DIAG -DIAG: - - # make sure that Status.FR, .CU1, and .SBX are set. - mfc0 $2, $12 - or $2, $2, (1 << 26) | (1 << 29) | (1 << 16) - mtc0 $2, $12 - - - li.s $f10, 4.0 - li.s $f12, 16.0 - cvt.ps.s $f20, $f10, $f12 # $f20: u=4.0, l=16.0 - - li.s $f10, -1.0 - li.s $f12, 2.0 - cvt.ps.s $f22, $f10, $f12 # $f22: u=-1.0, l=2.0 - - - writemsg "div.ps" - - div.ps $f8, $f20, $f22 - check_ps $f8, -4.0, 8.0 - - - writemsg "recip.ps" - - recip.ps $f8, $f20 - check_ps $f8, 0.25, 0.0625 - - - writemsg "rsqrt.ps" - - rsqrt.ps $f8, $f20 - check_ps $f8, 0.5, 0.25 - - - writemsg "sqrt.ps" - - sqrt.ps $f8, $f20 - check_ps $f8, 2.0, 4.0 - - - pass - - .end DIAG diff --git a/sim/testsuite/sim/mips/fpu64-ps.s b/sim/testsuite/sim/mips/fpu64-ps.s deleted file mode 100644 index ad493b8..0000000 --- a/sim/testsuite/sim/mips/fpu64-ps.s +++ /dev/null @@ -1,367 +0,0 @@ -# mips test sanity, expected to pass. -# mach: mips64 sb1 -# as: -mabi=eabi -# ld: -N -Ttext=0x80010000 -# output: *\\npass\\n - - .include "testutils.inc" - - .macro check_ps psval, upperval, lowerval - .set push - .set noreorder - cvt.s.pu $f0, \psval # upper - cvt.s.pl $f2, \psval # lower - li.s $f4, \upperval - li.s $f6, \lowerval - c.eq.s $fcc0, $f0, $f4 - bc1f $fcc0, _fail - c.eq.s $fcc0, $f2, $f6 - bc1f $fcc0, _fail - nop - .set pop - .endm - - setup - - .set noreorder - - .ent DIAG -DIAG: - - # make sure that Status.FR and .CU1 are set. - mfc0 $2, $12 - or $2, $2, (1 << 26) | (1 << 29) - mtc0 $2, $12 - - - writemsg "ldc1" - - .data -1: .dword 0xc1a8000042200000 # -21.0, 40.0 - .text - la $2, 1b - ldc1 $f8, 0($2) - check_ps $f8, -21.0, 40.0 - - - writemsg "cvt.ps.s" - - li.s $f10, 1.0 - li.s $f12, 3.0 - cvt.ps.s $f8, $f10, $f12 # upper, lower - check_ps $f8, 1.0, 3.0 - - - writemsg "cvt.ps.s, sdc1, copy, ldc1" - - .data -1: .dword 0 - .dword 0 - .text - la $2, 1b - li.s $f12, -4.0 - li.s $f14, 32.0 - cvt.ps.s $f10, $f12, $f14 # upper, lower - sdc1 $f10, 8($2) - lw $3, 8($2) - lw $4, 12($2) - sw $3, 0($2) - sw $4, 4($2) - ldc1 $f8, 0($2) - check_ps $f8, -4.0, 32.0 - - - # Load some constants for later use - - li.s $f10, 4.0 - li.s $f12, 16.0 - cvt.ps.s $f20, $f10, $f12 # $f20: u=4.0, l=16.0 - - li.s $f10, -1.0 - li.s $f12, 2.0 - cvt.ps.s $f22, $f10, $f12 # $f22: u=-1.0, l=2.0 - - li.s $f10, 17.0 - li.s $f12, -8.0 - cvt.ps.s $f24, $f10, $f12 # $f24: u=17.0, l=-8.0 - - - writemsg "pll.ps" - - pll.ps $f8, $f20, $f22 - check_ps $f8, 16.0, 2.0 - - - writemsg "plu.ps" - - plu.ps $f8, $f20, $f22 - check_ps $f8, 16.0, -1.0 - - - writemsg "pul.ps" - - pul.ps $f8, $f20, $f22 - check_ps $f8, 4.0, 2.0 - - - writemsg "puu.ps" - - puu.ps $f8, $f20, $f22 - check_ps $f8, 4.0, -1.0 - - - writemsg "abs.ps" - - abs.ps $f8, $f22 - check_ps $f8, 1.0, 2.0 - - - writemsg "mov.ps" - - mov.ps $f8, $f22 - check_ps $f8, -1.0, 2.0 - - - writemsg "neg.ps" - - neg.ps $f8, $f22 - check_ps $f8, 1.0, -2.0 - - - writemsg "add.ps" - - add.ps $f8, $f20, $f22 - check_ps $f8, 3.0, 18.0 - - - writemsg "mul.ps" - - mul.ps $f8, $f20, $f22 - check_ps $f8, -4.0, 32.0 - - - writemsg "sub.ps" - - sub.ps $f8, $f20, $f22 - check_ps $f8, 5.0, 14.0 - - - writemsg "madd.ps" - - madd.ps $f8, $f24, $f20, $f22 - check_ps $f8, 13.0, 24.0 - - - writemsg "msub.ps" - - msub.ps $f8, $f24, $f20, $f22 - check_ps $f8, -21.0, 40.0 - - - writemsg "nmadd.ps" - - nmadd.ps $f8, $f24, $f20, $f22 - check_ps $f8, -13.0, -24.0 - - - writemsg "nmsub.ps" - - nmsub.ps $f8, $f24, $f20, $f22 - check_ps $f8, 21.0, -40.0 - - - writemsg "movn.ps (n)" - - li $2, 0 - mov.ps $f8, $f20 - movn.ps $f8, $f22, $2 # doesn't move - check_ps $f8, 4.0, 16.0 - - - writemsg "movn.ps (y)" - - li $2, 1 - mov.ps $f8, $f20 - movn.ps $f8, $f22, $2 # does move - check_ps $f8, -1.0, 2.0 - - - writemsg "movz.ps (y)" - - li $2, 0 - mov.ps $f8, $f20 - movz.ps $f8, $f22, $2 # does move - check_ps $f8, -1.0, 2.0 - - - writemsg "movz.ps (n)" - - li $2, 1 - mov.ps $f8, $f20 - movz.ps $f8, $f22, $2 # doesn't move - check_ps $f8, 4.0, 16.0 - - - writemsg "movf.ps (y,y)" - - cfc1 $2, $31 - or $2, $2, (1 << 23) | (1 << 25) - xor $2, $2, (1 << 23) | (1 << 25) - ctc1 $2, $31 # clear fcc0, clear fcc1 - mov.ps $f8, $f20 - movf.ps $f8, $f22, $fcc0 # moves both halves - check_ps $f8, -1.0, 2.0 - - - writemsg "movf.ps (y,n)" - - cfc1 $2, $31 - or $2, $2, (1 << 23) | (1 << 25) - xor $2, $2, (0 << 23) | (1 << 25) - ctc1 $2, $31 # set fcc0, clear fcc1 - mov.ps $f8, $f20 - movf.ps $f8, $f22, $fcc0 # moves upper half only - check_ps $f8, -1.0, 16.0 - - - writemsg "movf.ps (n,y)" - - cfc1 $2, $31 - or $2, $2, (1 << 23) | (1 << 25) - xor $2, $2, (1 << 23) | (0 << 25) - ctc1 $2, $31 # clear fcc0, set fcc1 - mov.ps $f8, $f20 - movf.ps $f8, $f22, $fcc0 # moves lower half only - check_ps $f8, 4.0, 2.0 - - - writemsg "movf.ps (n,n)" - - cfc1 $2, $31 - or $2, $2, (1 << 23) | (1 << 25) - xor $2, $2, (0 << 23) | (0 << 25) - ctc1 $2, $31 # set fcc0, set fcc1 - mov.ps $f8, $f20 - movf.ps $f8, $f22, $fcc0 # doesn't move either half - check_ps $f8, 4.0, 16.0 - - - writemsg "movt.ps (n,n)" - - cfc1 $2, $31 - or $2, $2, (1 << 23) | (1 << 25) - xor $2, $2, (1 << 23) | (1 << 25) - ctc1 $2, $31 # clear fcc0, clear fcc1 - mov.ps $f8, $f20 - movt.ps $f8, $f22, $fcc0 # doesn't move either half - check_ps $f8, 4.0, 16.0 - - - writemsg "movt.ps (n,y)" - - cfc1 $2, $31 - or $2, $2, (1 << 23) | (1 << 25) - xor $2, $2, (0 << 23) | (1 << 25) - ctc1 $2, $31 # set fcc0, clear fcc1 - mov.ps $f8, $f20 - movt.ps $f8, $f22, $fcc0 # moves lower half only - check_ps $f8, 4.0, 2.0 - - - writemsg "movt.ps (y,n)" - - cfc1 $2, $31 - or $2, $2, (1 << 23) | (1 << 25) - xor $2, $2, (1 << 23) | (0 << 25) - ctc1 $2, $31 # clear fcc0, set fcc1 - mov.ps $f8, $f20 - movt.ps $f8, $f22, $fcc0 # moves upper half only - check_ps $f8, -1.0, 16.0 - - - writemsg "movt.ps (y,y)" - - cfc1 $2, $31 - or $2, $2, (1 << 23) | (1 << 25) - xor $2, $2, (0 << 23) | (0 << 25) - ctc1 $2, $31 # set fcc0, set fcc1 - mov.ps $f8, $f20 - movt.ps $f8, $f22, $fcc0 # moves both halves - check_ps $f8, -1.0, 2.0 - - - writemsg "alnv.ps (aligned)" - - .data -1: .dword 0xc1a8000042200000 # -21.0, 40.0 - .dword 0xc228000041a00000 # -42.0, 20.0 - .text - la $2, 1b - li $3, 0 - addu $4, $3, 8 - luxc1 $f10, $3($2) - luxc1 $f12, $4($2) - alnv.ps $f8, $f10, $f12, $3 - check_ps $f8, -21.0, 40.0 - - - writemsg "alnv.ps (unaligned)" - - .data -1: .dword 0xc1a8000042200000 # -21.0, 40.0 - .dword 0xc228000041a00000 # -42.0, 20.0 - .hword 0x0001 - .text - la $2, 1b - li $3, 4 - addu $4, $3, 8 - luxc1 $f10, $3($2) - luxc1 $f12, $4($2) - alnv.ps $f8, $f10, $f12, $3 - - lb $5, 16($2) - bnez $5, 2f # little endian - nop - - # big endian - check_ps $f8, 40.0, -42.0 - b 3f - nop -2: - # little endian - check_ps $f8, 20.0, -21.0 -3: - - - # We test c.cond.ps only lightly, just to make sure it modifies - # two bits and compares the halves separately. Perhaps it should - # be tested more thoroughly. - - writemsg "c.f.ps" - - cfc1 $2, $31 - or $2, $2, (1 << 23) | (0x7f << 25) - ctc1 $2, $31 # set all fcc bits - c.f.ps $fcc0, $f8, $f8 # -> f, f - bc1t $fcc0, _fail - nop - bc1t $fcc1, _fail - nop - - - writemsg "c.olt.ps" - - cfc1 $2, $31 - or $2, $2, (1 << 23) | (0x7f << 25) - xor $2, $2, (1 << 23) | (0x7f << 25) - ctc1 $2, $31 # clear all fcc bits - c.lt.ps $fcc0, $f22, $f24 # -> f, t - bc1t $fcc0, _fail - nop - bc1f $fcc1, _fail - nop - - - pass - - .end DIAG diff --git a/sim/testsuite/sim/mips/hilo-hazard-1.s b/sim/testsuite/sim/mips/hilo-hazard-1.s deleted file mode 100644 index f20c939..0000000 --- a/sim/testsuite/sim/mips/hilo-hazard-1.s +++ /dev/null @@ -1,19 +0,0 @@ -# Test for architectures with mf{hi,lo} -> mult/div/mt{hi,lo} hazards. -# -# mach: mips1 mips2 mips3 mips4 vr4100 vr4111 vr4120 vr5000 vr5400 -# as: -mabi=eabi -# ld: -N -Ttext=0x80010000 -# output: HILO: * too close to MF at *\\n\\nprogram stopped*\\n -# xerror: - - .include "hilo-hazard.inc" - .include "testutils.inc" - - setup - - .set noreorder - .ent DIAG -DIAG: - hilo - pass - .end DIAG diff --git a/sim/testsuite/sim/mips/hilo-hazard-2.s b/sim/testsuite/sim/mips/hilo-hazard-2.s deleted file mode 100644 index 07b84d2..0000000 --- a/sim/testsuite/sim/mips/hilo-hazard-2.s +++ /dev/null @@ -1,18 +0,0 @@ -# Test for architectures without mf{hi,lo} -> mult/div/mt{hi,lo} hazards. -# -# mach: vr5500 mips32 mips64 -# as: -mabi=eabi -# ld: -N -Ttext=0x80010000 -# output: pass\\n - - .include "hilo-hazard.inc" - .include "testutils.inc" - - setup - - .set noreorder - .ent DIAG -DIAG: - hilo - pass - .end DIAG diff --git a/sim/testsuite/sim/mips/hilo-hazard-3.s b/sim/testsuite/sim/mips/hilo-hazard-3.s deleted file mode 100644 index 1a0949d..0000000 --- a/sim/testsuite/sim/mips/hilo-hazard-3.s +++ /dev/null @@ -1,18 +0,0 @@ -# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween. -# -# mach: all -# as: -mabi=eabi -# ld: -N -Ttext=0x80010000 -# output: pass\\n - - .include "hilo-hazard.inc" - .include "testutils.inc" - - setup - - .set noreorder - .ent DIAG -DIAG: - hilo - pass - .end DIAG diff --git a/sim/testsuite/sim/mips/hilo-hazard-4.s b/sim/testsuite/sim/mips/hilo-hazard-4.s deleted file mode 100644 index fc010f8..0000000 --- a/sim/testsuite/sim/mips/hilo-hazard-4.s +++ /dev/null @@ -1,36 +0,0 @@ -# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween. -# -# mach: all -# as: -mabi=eabi -mmicromips -# ld: -N -Ttext=0x80010000 -# output: pass\\n - -# Copyright (C) 2013-2021 Free Software Foundation, Inc. -# Contributed by Andrew Bennett (andrew.bennett@imgtec.com) -# -# This file is part of the MIPS sim. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, see . - - .include "hilo-hazard.inc" - .include "testutils.inc" - - setup - - .set noreorder - .ent DIAG -DIAG: - hilo - pass - .end DIAG diff --git a/sim/testsuite/sim/mips/mdmx-ob-sb1.s b/sim/testsuite/sim/mips/mdmx-ob-sb1.s deleted file mode 100644 index c8409fc..0000000 --- a/sim/testsuite/sim/mips/mdmx-ob-sb1.s +++ /dev/null @@ -1,102 +0,0 @@ -# MDMX .OB op tests. -# mach: sb1 -# as: -mabi=eabi -# ld: -N -Ttext=0x80010000 -# output: *\\npass\\n - - .include "testutils.inc" - .include "utils-mdmx.inc" - - setup - - .set noreorder - - .ent DIAG -DIAG: - - enable_mdmx - - # set Status.SBX to enable SB-1 extensions. - mfc0 $2, $12 - or $2, $2, (1 << 16) - mtc0 $2, $12 - - - ### - ### SB-1 Non-accumulator .ob format ops. - ### - ### Key: v = vector - ### ev = vector of single element - ### cv = vector of constant. - ### - - - writemsg "pavg.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - pavg.ob $f10, $f8, $f9 - ck_ob $f10, 0x3c4d5e6f8091a2b3 - - writemsg "pavg.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - pavg.ob $f10, $f8, $f9[6] - ck_ob $f10, 0x444d555e666f7780 - - writemsg "pavg.ob (cv)" - ld_ob $f8, 0x1122334455667788 - pavg.ob $f10, $f8, 0x10 - ck_ob $f10, 0x1119222a333b444c - - - writemsg "pabsdiff.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - pabsdiff.ob $f10, $f8, $f9 - ck_ob $f10, 0x5555555555555555 - - writemsg "pabsdiff.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - pabsdiff.ob $f10, $f8, $f9[7] - ck_ob $f10, 0x5544332211001122 - - writemsg "pabsdiff.ob (cv)" - ld_ob $f8, 0x0001020304050607 - pabsdiff.ob $f10, $f8, 0x04 - ck_ob $f10, 0x0403020100010203 - - - ### - ### SB-1 Accumulator .ob format ops - ### - ### Key: v = vector - ### ev = vector of single element - ### cv = vector of constant. - ### - - - writemsg "pabsdiffc.ob (v)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - pabsdiffc.ob $f8, $f9 - ck_acc_ob 0x0001020304050607, 0x0000000000000000, 0x5555555555555555 - - writemsg "pabsdiffc.ob (ev)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - pabsdiffc.ob $f8, $f9[7] - ck_acc_ob 0x0001020304050607, 0x0000000000000000, 0x5544332211001122 - - writemsg "pabsdiffc.ob (cv)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x0001020304050607 - pabsdiffc.ob $f8, 0x04 - ck_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0403020100010203 - - - pass - - .end DIAG diff --git a/sim/testsuite/sim/mips/mdmx-ob.s b/sim/testsuite/sim/mips/mdmx-ob.s deleted file mode 100644 index 23759ae..0000000 --- a/sim/testsuite/sim/mips/mdmx-ob.s +++ /dev/null @@ -1,630 +0,0 @@ -# MDMX .OB op tests. -# mach: mips64 sb1 -# as: -mabi=eabi -# as(mips64): -mabi=eabi -mdmx -# ld: -N -Ttext=0x80010000 -# output: *\\npass\\n - - .include "testutils.inc" - .include "utils-mdmx.inc" - - setup - - .set noreorder - - .ent DIAG -DIAG: - - enable_mdmx - - - ### - ### Non-accumulator, non-CC-using .ob format ops. - ### - ### Key: v = vector - ### ev = vector of single element - ### cv = vector of constant. - ### - - - writemsg "add.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - add.ob $f10, $f8, $f9 - ck_ob $f10, 0x7799bbddffffffff - - writemsg "add.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - add.ob $f10, $f8, $f9[6] - ck_ob $f10, 0x8899aabbccddeeff - - writemsg "add.ob (cv)" - ld_ob $f8, 0x1122334455667788 - add.ob $f10, $f8, 0x10 - ck_ob $f10, 0x2132435465768798 - - - writemsg "alni.ob" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - alni.ob $f10, $f8, $f9, 3 - ck_ob $f10, 0x4455667788667788 - - - writemsg "alnv.ob" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - li $4, 5 - alnv.ob $f10, $f8, $f9, $4 - ck_ob $f10, 0x66778866778899aa - - - writemsg "and.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - and.ob $f10, $f8, $f9 - ck_ob $f10, 0x0022000000224488 - - writemsg "and.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - and.ob $f10, $f8, $f9[4] - ck_ob $f10, 0x1100110011001188 - - writemsg "and.ob (cv)" - ld_ob $f8, 0x1122334455667788 - and.ob $f10, $f8, 0x1e - ck_ob $f10, 0x1002120414061608 - - - writemsg "max.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - max.ob $f10, $f8, $f9 - ck_ob $f10, 0x66778899aabbccdd - - writemsg "max.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - max.ob $f10, $f8, $f9[7] - ck_ob $f10, 0x6666666666667788 - - writemsg "max.ob (cv)" - ld_ob $f8, 0x1122334455667788 - max.ob $f10, $f8, 0x15 - ck_ob $f10, 0x1522334455667788 - - - writemsg "min.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - min.ob $f10, $f8, $f9 - ck_ob $f10, 0x1122334455667788 - - writemsg "min.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - min.ob $f10, $f8, $f9[7] - ck_ob $f10, 0x1122334455666666 - - writemsg "min.ob (cv)" - ld_ob $f8, 0x1122334455667788 - min.ob $f10, $f8, 0x15 - ck_ob $f10, 0x1115151515151515 - - - writemsg "mul.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x0001020304050607 - mul.ob $f10, $f8, $f9 - ck_ob $f10, 0x002266ccffffffff - - writemsg "mul.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x0001020304050607 - mul.ob $f10, $f8, $f9[4] - ck_ob $f10, 0x336699ccffffffff - - writemsg "mul.ob (cv)" - ld_ob $f8, 0x1122334455667788 - mul.ob $f10, $f8, 2 - ck_ob $f10, 0x22446688aacceeff - - - writemsg "nor.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - nor.ob $f10, $f8, $f9 - ck_ob $f10, 0x8888442200000022 - - writemsg "nor.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - nor.ob $f10, $f8, $f9[6] - ck_ob $f10, 0x8888888888888800 - - writemsg "nor.ob (cv)" - ld_ob $f8, 0x1122334455667788 - nor.ob $f10, $f8, 0x08 - ck_ob $f10, 0xe6d5c4b3a2918077 - - - writemsg "or.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - or.ob $f10, $f8, $f9 - ck_ob $f10, 0x7777bbddffffffdd - - writemsg "or.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - or.ob $f10, $f8, $f9[6] - ck_ob $f10, 0x77777777777777ff - - writemsg "or.ob (cv)" - ld_ob $f8, 0x1122334455667788 - or.ob $f10, $f8, 0x08 - ck_ob $f10, 0x192a3b4c5d6e7f88 - - - writemsg "shfl.mixh.ob" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - shfl.mixh.ob $f10, $f8, $f9 - ck_ob $f10, 0x1166227733884499 - - - writemsg "shfl.mixl.ob" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - shfl.mixl.ob $f10, $f8, $f9 - ck_ob $f10, 0x55aa66bb77cc88dd - - - writemsg "shfl.pach.ob" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - shfl.pach.ob $f10, $f8, $f9 - ck_ob $f10, 0x113355776688aacc - - - writemsg "shfl.upsl.ob" - ld_ob $f8, 0x1122334455667788 - shfl.upsl.ob $f10, $f8, $f8 - ck_ob $f10, 0x005500660077ff88 - - - writemsg "sll.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x0001020304050607 - sll.ob $f10, $f8, $f9 - ck_ob $f10, 0x1144cc2050c0c000 - - writemsg "sll.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x0001020304050607 - sll.ob $f10, $f8, $f9[3] - ck_ob $f10, 0x1020304050607080 - - writemsg "sll.ob (cv)" - ld_ob $f8, 0x1122334455667788 - sll.ob $f10, $f8, 1 - ck_ob $f10, 0x22446688aaccee10 - - - writemsg "srl.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x0001020304050607 - srl.ob $f10, $f8, $f9 - ck_ob $f10, 0x11110c0805030101 - - writemsg "srl.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x0001020304050607 - srl.ob $f10, $f8, $f9[3] - ck_ob $f10, 0x0102030405060708 - - writemsg "srl.ob (cv)" - ld_ob $f8, 0x1122334455667788 - srl.ob $f10, $f8, 1 - ck_ob $f10, 0x081119222a333b44 - - - writemsg "sub.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x0001020304050607 - sub.ob $f10, $f8, $f9 - ck_ob $f10, 0x1121314151617181 - - writemsg "sub.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - sub.ob $f10, $f8, $f9[7] - ck_ob $f10, 0x0000000000001122 - - writemsg "sub.ob (cv)" - ld_ob $f8, 0x1122334455667788 - sub.ob $f10, $f8, 0x10 - ck_ob $f10, 0x0112233445566778 - - - writemsg "xor.ob (v)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - xor.ob $f10, $f8, $f9 - ck_ob $f10, 0x7755bbddffddbb55 - - writemsg "xor.ob (ev)" - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - xor.ob $f10, $f8, $f9[6] - ck_ob $f10, 0x66554433221100ff - - writemsg "xor.ob (cv)" - ld_ob $f8, 0x1122334455667788 - xor.ob $f10, $f8, 0x08 - ck_ob $f10, 0x192a3b4c5d6e7f80 - - - ### - ### Accumulator .ob format ops (in order: rd/wr, math, scale/round) - ### - ### Key: v = vector - ### ev = vector of single element - ### cv = vector of constant. - ### - - - writemsg "wacl.ob / rac[hml].ob" - ld_ob $f8, 0x8001028304850687 - ld_ob $f9, 0x1011121314151617 - wacl.ob $f8, $f9 - ck_acc_ob 0xff0000ff00ff00ff, 0x8001028304850687, 0x1011121314151617 - - # Note: relies on data left in accumulator by previous test. - writemsg "wach.ob / rac[hml].ob" - ld_ob $f8, 0x2021222324252627 - wach.ob $f8 - ck_acc_ob 0x2021222324252627, 0x8001028304850687, 0x1011121314151617 - - - writemsg "adda.ob (v)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - adda.ob $f8, $f9 - ck_acc_ob 0x0001020304050607, 0x0000000000010101, 0x7799bbddff214365 - - writemsg "adda.ob (ev)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - adda.ob $f8, $f9[2] - ck_acc_ob 0x0001020304050607, 0x0000000001010101, 0xccddeeff10213243 - - writemsg "adda.ob (cv)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - adda.ob $f8, 0x1f - ck_acc_ob 0x0001020304050607, 0x0000000000000000, 0x30415263748596a7 - - - writemsg "addl.ob (v)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - addl.ob $f8, $f9 - ck_acc_ob 0x0000000000000000, 0x0000000000010101, 0x7799bbddff214365 - - writemsg "addl.ob (ev)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - addl.ob $f8, $f9[2] - ck_acc_ob 0x0000000000000000, 0x0000000001010101, 0xccddeeff10213243 - - writemsg "addl.ob (cv)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - addl.ob $f8, 0x1f - ck_acc_ob 0x0000000000000000, 0x0000000000000000, 0x30415263748596a7 - - - writemsg "mula.ob (v)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - mula.ob $f8, $f9 - ck_acc_ob 0x0001020304050607, 0x060f1b28384a5e75, 0xc6ce18a47282d468 - - writemsg "mula.ob (ev)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - mula.ob $f8, $f9[2] - ck_acc_ob 0x0001020304050607, 0x0c1825313e4a5663, 0x6bd641ac1782ed58 - - writemsg "mula.ob (cv)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - mula.ob $f8, 0x1f - ck_acc_ob 0x0001020304050607, 0x020406080a0c0e10, 0x0f1e2d3c4b5a6978 - - - writemsg "mull.ob (v)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - mull.ob $f8, $f9 - ck_acc_ob 0x0000000000000000, 0x060f1b28384a5e75, 0xc6ce18a47282d468 - - writemsg "mull.ob (ev)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - mull.ob $f8, $f9[2] - ck_acc_ob 0x0000000000000000, 0x0c1825313e4a5663, 0x6bd641ac1782ed58 - - writemsg "mull.ob (cv)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - mull.ob $f8, 0x1f - ck_acc_ob 0x0000000000000000, 0x020406080a0c0e10, 0x0f1e2d3c4b5a6978 - - - writemsg "muls.ob (v)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - muls.ob $f8, $f9 - ck_acc_ob 0xff00010203040506, 0xf9f0e4d7c7b5a18a, 0x3a32e85c8e7e2c98 - - writemsg "muls.ob (ev)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - muls.ob $f8, $f9[2] - ck_acc_ob 0xff00010203040506, 0xf3e7dacec1b5a99c, 0x952abf54e97e13a8 - - writemsg "muls.ob (cv)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - muls.ob $f8, 0x1f - ck_acc_ob 0xff00010203040506, 0xfdfbf9f7f5f3f1ef, 0xf1e2d3c4b5a69788 - - - writemsg "mulsl.ob (v)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - mulsl.ob $f8, $f9 - ck_acc_ob 0xffffffffffffffff, 0xf9f0e4d7c7b5a18a, 0x3a32e85c8e7e2c98 - - writemsg "mulsl.ob (ev)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - mulsl.ob $f8, $f9[2] - ck_acc_ob 0xffffffffffffffff, 0xf3e7dacec1b5a99c, 0x952abf54e97e13a8 - - writemsg "mulsl.ob (cv)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - mulsl.ob $f8, 0x1f - ck_acc_ob 0xffffffffffffffff, 0xfdfbf9f7f5f3f1ef, 0xf1e2d3c4b5a69788 - - - writemsg "suba.ob (v)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - suba.ob $f8, $f9 - ck_acc_ob 0xff00010203040506, 0xffffffffffffffff, 0xabababababababab - - writemsg "suba.ob (ev)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - suba.ob $f8, $f9[2] - ck_acc_ob 0xff00010203040506, 0xffffffffffffffff, 0x566778899aabbccd - - writemsg "suba.ob (cv)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - suba.ob $f8, 0x1f - ck_acc_ob 0xff01020304050607, 0xff00000000000000, 0xf203142536475869 - - - writemsg "subl.ob (v)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - subl.ob $f8, $f9 - ck_acc_ob 0xffffffffffffffff, 0xffffffffffffffff, 0xabababababababab - - writemsg "subl.ob (ev)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - ld_ob $f9, 0x66778899aabbccdd - subl.ob $f8, $f9[2] - ck_acc_ob 0xffffffffffffffff, 0xffffffffffffffff, 0x566778899aabbccd - - writemsg "subl.ob (cv)" - ld_acc_ob 0x0001020304050607, 0x0000000000000000, 0x0000000000000000 - ld_ob $f8, 0x1122334455667788 - subl.ob $f8, 0x1f - ck_acc_ob 0xff00000000000000, 0xff00000000000000, 0xf203142536475869 - - - writemsg "rnau.ob (v)" - ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe - ld_ob $f8, 0x0001020304050607 - rnau.ob $f9, $f8 - ck_ob $f9, 0x4021110940201008 - - writemsg "rnau.ob (ev)" - ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe - ld_ob $f8, 0x0001020304050607 - rnau.ob $f9, $f8[4] - ck_ob $f9, 0x080809097f7f8080 - - writemsg "rnau.ob (cv)" - ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe - rnau.ob $f9, 2 - ck_ob $f9, 0x10111112feffffff - - - writemsg "rneu.ob (v)" - ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe - ld_ob $f8, 0x0001020304050607 - rneu.ob $f9, $f8 - ck_ob $f9, 0x4021110940201008 - - writemsg "rneu.ob (ev)" - ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe - ld_ob $f8, 0x0001020304050607 - rneu.ob $f9, $f8[4] - ck_ob $f9, 0x080808097f7f8080 - - writemsg "rneu.ob (cv)" - ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe - rneu.ob $f9, 2 - ck_ob $f9, 0x10101112fefeffff - - - writemsg "rzu.ob (v)" - ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe - ld_ob $f8, 0x0001020304050607 - rzu.ob $f9, $f8 - ck_ob $f9, 0x402111083f1f0f07 - - writemsg "rzu.ob (ev)" - ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe - ld_ob $f8, 0x0001020304050607 - rzu.ob $f9, $f8[4] - ck_ob $f9, 0x080808087f7f7f7f - - writemsg "rzu.ob (cv)" - ld_acc_ob 0x0000000000000000, 0x0000000003030303, 0x40424446f8fafcfe - rzu.ob $f9, 2 - ck_ob $f9, 0x10101111fefeffff - - - ### - ### CC-using .ob format ops. - ### - ### Key: v = vector - ### ev = vector of single element - ### cv = vector of constant. - ### - - - writemsg "c.eq.ob (v)" - ld_ob $f8, 0x0001010202030304 - ld_ob $f9, 0x0101020203030404 - clr_fp_cc 0xff - c.eq.ob $f8, $f9 - ck_fp_cc 0x55 - - writemsg "c.eq.ob (ev)" - ld_ob $f8, 0x0001010202030304 - ld_ob $f9, 0x0101020203030404 - clr_fp_cc 0xff - c.eq.ob $f8, $f9[5] - ck_fp_cc 0x18 - - writemsg "c.eq.ob (cv)" - ld_ob $f8, 0x0001010202030304 - clr_fp_cc 0xff - c.eq.ob $f8, 0x03 - ck_fp_cc 0x06 - - - writemsg "c.le.ob (v)" - ld_ob $f8, 0x0001010202030304 - ld_ob $f9, 0x0101020203030404 - clr_fp_cc 0xff - c.le.ob $f8, $f9 - ck_fp_cc 0xff - - writemsg "c.le.ob (ev)" - ld_ob $f8, 0x0001010202030304 - ld_ob $f9, 0x0101020203030404 - clr_fp_cc 0xff - c.le.ob $f8, $f9[5] - ck_fp_cc 0xf8 - - writemsg "c.le.ob (cv)" - ld_ob $f8, 0x0001010202030304 - clr_fp_cc 0xff - c.le.ob $f8, 0x03 - ck_fp_cc 0xfe - - - writemsg "c.lt.ob (v)" - ld_ob $f8, 0x0001010202030304 - ld_ob $f9, 0x0101020203030404 - clr_fp_cc 0xff - c.lt.ob $f8, $f9 - ck_fp_cc 0xaa - - writemsg "c.lt.ob (ev)" - ld_ob $f8, 0x0001010202030304 - ld_ob $f9, 0x0101020203030404 - clr_fp_cc 0xff - c.lt.ob $f8, $f9[5] - ck_fp_cc 0xe0 - - writemsg "c.lt.ob (cv)" - ld_ob $f8, 0x0001010202030304 - clr_fp_cc 0xff - c.lt.ob $f8, 0x03 - ck_fp_cc 0xf8 - - - writemsg "pickf.ob (v)" - ld_ob $f8, 0x0001020304050607 - ld_ob $f9, 0x08090a0b0c0d0e0f - clrset_fp_cc 0xff, 0xaa - pickf.ob $f10, $f8, $f9 - ck_ob $f10, 0x08010a030c050e07 - - writemsg "pickf.ob (ev)" - ld_ob $f8, 0x0001020304050607 - ld_ob $f9, 0x08090a0b0c0d0e0f - clrset_fp_cc 0xff, 0xaa - pickf.ob $f10, $f8, $f9[4] - ck_ob $f10, 0x0b010b030b050b07 - - writemsg "pickf.ob (cv)" - ld_ob $f8, 0x0001020304050607 - clrset_fp_cc 0xff, 0xaa - pickf.ob $f10, $f8, 0x10 - ck_ob $f10, 0x1001100310051007 - - - writemsg "pickt.ob (v)" - ld_ob $f8, 0x0001020304050607 - ld_ob $f9, 0x08090a0b0c0d0e0f - clrset_fp_cc 0xff, 0xaa - pickt.ob $f10, $f8, $f9 - ck_ob $f10, 0x0009020b040d060f - - writemsg "pickt.ob (ev)" - ld_ob $f8, 0x0001020304050607 - ld_ob $f9, 0x08090a0b0c0d0e0f - clrset_fp_cc 0xff, 0xaa - pickt.ob $f10, $f8, $f9[5] - ck_ob $f10, 0x000a020a040a060a - - writemsg "pickt.ob (cv)" - ld_ob $f8, 0x0001020304050607 - clrset_fp_cc 0xff, 0xaa - pickt.ob $f10, $f8, 0x10 - ck_ob $f10, 0x0010021004100610 - - - pass - - .end DIAG diff --git a/sim/testsuite/sim/mips/mips32-dsp.s b/sim/testsuite/sim/mips/mips32-dsp.s deleted file mode 100644 index ade6bcf..0000000 --- a/sim/testsuite/sim/mips/mips32-dsp.s +++ /dev/null @@ -1,787 +0,0 @@ -# MIPS32 DSP ASE test -# mach: mips32r2 mips64r2 -#as: -mdsp -#ld: -N -Ttext=0x80010000 -#output: *\\npass\\n - -# Copyright (C) 2005-2021 Free Software Foundation, Inc. -# Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu. -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - - .include "testutils.inc" - .include "utils-dsp.inc" - - setup - - .set noreorder - - .ent DIAG -DIAG: - - writemsg "[1] Test addq.ph" - dspck_dstio addq.ph, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio addq.ph, 0x20002, 0x10001, 0x10001, 0x0, 0x0 - dspck_dstio addq.ph, 0xfffefffe, 0xffffffff, 0xffffffff, 0x0, 0x0 - dspck_dstio addq.ph, 0xffff0000, 0xffffffff, 0x1, 0x0, 0x0 - dspck_dstio addq.ph, 0x0, 0xffffffff, 0x10001, 0x0, 0x0 - - writemsg "[2] Test addq_s.ph" - dspck_dstio addq_s.ph, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio addq_s.ph, 0x20002, 0x10001, 0x10001, 0x0, 0x0 - dspck_dstio addq_s.ph, 0xfffefffe, 0xffffffff, 0xffffffff, 0x0, 0x0 - dspck_dstio addq_s.ph, 0xffff0000, 0xffffffff, 0x1, 0x0, 0x0 - dspck_dstio addq_s.ph, 0xffff0000, 0x1, 0xffffffff, 0x0, 0x0 - - writemsg "[3] Test addq_s.w" - dspck_dsti addq_s.w, 0x0, 0x0, 0x0, 0x0 - dspck_dstio addq_s.w, 0x2, 0x1, 0x1, 0x0, 0x0 - dspck_dstio addq_s.w, 0xfffffffe, 0xffffffff, 0xffffffff, 0x0, 0x0 - dspck_dstio addq_s.w, 0x0, 0xffffffff, 0x1, 0x0, 0x0 - dspck_dstio addq_s.w, 0xffff, 0xffffffff, 0x10000, 0x0, 0x0 - - writemsg "[4] Test addu.qb" - dspck_dstio addu.qb, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio addu.qb, 0x2040000, 0x102ff01, 0x10201ff, 0x0, 0x100000 - dspck_dstio addu.qb, 0xfe0001fe, 0x7f80ffff, 0x7f8002ff, 0x0, 0x100000 - dspck_dstio addu.qb, 0xffffffff, 0x10203, 0xfffefdfc, 0x0, 0x0 - dspck_dstio addu.qb, 0xffffffff, 0xfbfaf9f8, 0x4050607, 0x0, 0x0 - - writemsg "[5] Test addu_s.qb" - dspck_dstio addu_s.qb, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio addu_s.qb, 0x204ffff, 0x102ff01, 0x10201ff, 0x0, 0x100000 - dspck_dstio addu_s.qb, 0xfeffffff, 0x7f80ffff, 0x7f8002ff, 0x0, 0x100000 - dspck_dstio addu_s.qb, 0xffffffff, 0x10203, 0xfffefdfc, 0x0, 0x0 - dspck_dstio addu_s.qb, 0xffffffff, 0xfbfaf9f8, 0x4050607, 0x0, 0x0 - - writemsg "[6] Test subq.ph" - dspck_dstio subq.ph, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio subq.ph, 0x10001, 0x20002, 0x10001, 0x0, 0x0 - dspck_dstio subq.ph, 0x1ffff, 0x2fffe, 0x1ffff, 0x0, 0x0 - dspck_dstio subq.ph, 0x7fff0000, 0xfffe8000, 0x7fff8000, 0x0, 0x100000 - dspck_dstio subq.ph, 0x1ffff, 0x7fff8000, 0x7ffe8001, 0x0, 0x0 - - writemsg "[7] Test subq_s.ph" - dspck_dstio subq_s.ph, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio subq_s.ph, 0x10001, 0x20002, 0x10001, 0x0, 0x0 - dspck_dstio subq_s.ph, 0x1ffff, 0x2fffe, 0x1ffff, 0x0, 0x0 - dspck_dstio subq_s.ph, 0x0, 0x7fff8000, 0x7fff8000, 0x0, 0x0 - dspck_dstio subq_s.ph, 0x1ffff, 0x7fff8000, 0x7ffe8001, 0x0, 0x0 - - writemsg "[8] Test subq_s.w" - dspck_dsti subq_s.w, 0x0, 0x0, 0x0, 0x0 - dspck_dsti subq_s.w, 0x0, 0x7fffffff, 0x7fffffff, 0x0 - dspck_dstio subq_s.w, 0x7fffffff, 0x0, 0x80000000, 0x0, 0x100000 - dspck_dstio subq_s.w, 0x1, 0x2, 0x1, 0x0, 0x0 - dspck_dstio subq_s.w, 0xffffffff, 0xfffffffe, 0xffffffff, 0x0, 0x0 - - writemsg "[9] Test subu.qb" - dspck_dstio subu.qb, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio subu.qb, 0x4030201, 0x8060402, 0x4030201, 0x0, 0x0 - dspck_dstio subu.qb, 0xfcfdfeff, 0x4030201, 0x8060402, 0x0, 0x100000 - dspck_dstio subu.qb, 0x102ff01, 0x2040000, 0x10201ff, 0x0, 0x100000 - dspck_dstio subu.qb, 0x7f80ffff, 0xfe0001fe, 0x7f8002ff, 0x0, 0x100000 - - writemsg "[10] Test subu_s.qb" - dspck_dstio subu_s.qb, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio subu_s.qb, 0x4030201, 0x8060402, 0x4030201, 0x0, 0x0 - dspck_dstio subu_s.qb, 0x0, 0x4030201, 0x8060402, 0x0, 0x100000 - dspck_dstio subu_s.qb, 0x1020000, 0x2040000, 0x10201ff, 0x0, 0x100000 - dspck_dstio subu_s.qb, 0x7f000000, 0xfe0001fe, 0x7f8002ff, 0x0, 0x100000 - - writemsg "[11] Test addsc" - dspck_dstio addsc, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio addsc, 0x1000000, 0x84000000, 0x7d000000, 0x0, 0x2000 - dspck_dstio addsc, 0xf1000000, 0x74000000, 0x7d000000, 0x0, 0x0 - dspck_dstio addsc, 0x2, 0x1, 0x1, 0x0, 0x0 - dspck_dstio addsc, 0xffffffff, 0xfffffffe, 0x1, 0x0, 0x0 - - writemsg "[12] Test addwc" - dspck_dstio addwc, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio addwc, 0x2, 0x1, 0x1, 0x0, 0x0 - dspck_dstio addwc, 0x3, 0x1, 0x1, 0x2000, 0x2000 - dspck_dsti addwc, 0x1, 0xffffffff, 0x1, 0x2000 - dspck_dsti addwc, 0x11, 0xa, 0x6, 0x2000 - - writemsg "[13] Test modsub" - dspck_dstio modsub, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio modsub, 0x76, 0x78, 0x7802, 0x0, 0x0 - dspck_dstio modsub, 0x74, 0x76, 0x7802, 0x0, 0x0 - dspck_dstio modsub, 0x78, 0x0, 0x7802, 0x0, 0x0 - dspck_dstio modsub, 0xf9, 0xfc, 0xfe03, 0x0, 0x0 - - writemsg "[14] Test raddu.w.qb" - dspck_dsio raddu.w.qb, 0x0, 0x0, 0x0, 0x0 - dspck_dsio raddu.w.qb, 0x2, 0x1000100, 0x0, 0x0 - dspck_dsio raddu.w.qb, 0x4, 0x1010101, 0x0, 0x0 - dspck_dsio raddu.w.qb, 0x200, 0xff01ff01, 0x0, 0x0 - dspck_dsio raddu.w.qb, 0x3fc, 0xffffffff, 0x0, 0x0 - - writemsg "[15] Test absq_s.ph" - dspck_dsio absq_s.ph, 0x0, 0x0, 0x0, 0x0 - dspck_dsio absq_s.ph, 0x10001, 0xffffffff, 0x0, 0x0 - dspck_dsio absq_s.ph, 0x7fff7fff, 0x80008000, 0x0, 0x100000 - dspck_dsio absq_s.ph, 0x60000002, 0xa000fffe, 0x0, 0x0 - dspck_dsio absq_s.ph, 0x70000004, 0x9000fffc, 0x0, 0x0 - - writemsg "[16] Test absq_s.w" - dspck_dsio absq_s.w, 0x0, 0x0, 0x0, 0x0 - dspck_dsio absq_s.w, 0x1, 0xffffffff, 0x0, 0x0 - dspck_dsio absq_s.w, 0x7fffffff, 0x80000000, 0x0, 0x100000 - dspck_dsio absq_s.w, 0x40000001, 0xbfffffff, 0x0, 0x0 - dspck_dsio absq_s.w, 0x8000001, 0xf7ffffff, 0x0, 0x0 - - writemsg "[17] Test precrq.qb.ph" - dspck_dstio precrq.qb.ph, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio precrq.qb.ph, 0xff7f4020, 0xffff7fff, 0x40002000, 0x0, 0x0 - dspck_dstio precrq.qb.ph, 0xfeba7632, 0xfedcba98, 0x76543210, 0x0, 0x0 - dspck_dstio precrq.qb.ph, 0x7632feba, 0x76543210, 0xfedcba98, 0x0, 0x0 - dspck_dstio precrq.qb.ph, 0x14589cd, 0x1234567, 0x89abcdef, 0x0, 0x0 - - writemsg "[18] Test precrq.ph.w" - dspck_dstio precrq.ph.w, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio precrq.ph.w, 0xffff4000, 0xffff7fff, 0x40002000, 0x0, 0x0 - dspck_dstio precrq.ph.w, 0xfedc7654, 0xfedcba98, 0x76543210, 0x0, 0x0 - dspck_dstio precrq.ph.w, 0x7654fedc, 0x76543210, 0xfedcba98, 0x0, 0x0 - dspck_dstio precrq.ph.w, 0x12389ab, 0x1234567, 0x89abcdef, 0x0, 0x0 - - writemsg "[19] Test precrq_rs.ph.w" - dspck_dstio precrq_rs.ph.w, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio precrq_rs.ph.w, 0x7fff0000, 0x7fffffff, 0xffffffff, 0x0, 0x400000 - dspck_dstio precrq_rs.ph.w, 0x80008001, 0x80007fff, 0x8000ffff, 0x0, 0x0 - dspck_dstio precrq_rs.ph.w, 0xfedd7654, 0xfedcba98, 0x76543210, 0x0, 0x0 - dspck_dstio precrq_rs.ph.w, 0x7654fedd, 0x76543210, 0xfedcba98, 0x0, 0x0 - - writemsg "[20] Test precrqu_s.qb.ph" - dspck_dstio precrqu_s.qb.ph, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio precrqu_s.qb.ph, 0xff8040, 0xffff7fff, 0x40002000, 0x0, 0x400000 - dspck_dstio precrqu_s.qb.ph, 0xec64, 0xfedcba98, 0x76543210, 0x0, 0x400000 - dspck_dstio precrqu_s.qb.ph, 0xec640000, 0x76543210, 0xfedcba98, 0x0, 0x400000 - dspck_dstio precrqu_s.qb.ph, 0x28a0000, 0x1234567, 0x89abcdef, 0x0, 0x400000 - - writemsg "[21] Test preceq.w.phl" - dspck_dsio preceq.w.phl, 0x0, 0x0, 0x0, 0x0 - dspck_dsio preceq.w.phl, 0xffff0000, 0xffffffff, 0x0, 0x0 - dspck_dsio preceq.w.phl, 0x80000000, 0x80004000, 0x0, 0x0 - dspck_dsio preceq.w.phl, 0xc0010000, 0xc0012001, 0x0, 0x0 - dspck_dsio preceq.w.phl, 0x76540000, 0x76543210, 0x0, 0x0 - - writemsg "[22] Test preceq.w.phr" - dspck_dsio preceq.w.phr, 0x0, 0x0, 0x0, 0x0 - dspck_dsio preceq.w.phr, 0xffff0000, 0xffffffff, 0x0, 0x0 - dspck_dsio preceq.w.phr, 0x40000000, 0x80004000, 0x0, 0x0 - dspck_dsio preceq.w.phr, 0x20010000, 0xc0012001, 0x0, 0x0 - dspck_dsio preceq.w.phr, 0x32100000, 0x76543210, 0x0, 0x0 - - writemsg "[23] Test precequ.ph.qbl" - dspck_dsio precequ.ph.qbl, 0x0, 0x0, 0x0, 0x0 - dspck_dsio precequ.ph.qbl, 0x7f807f80, 0xffffffff, 0x0, 0x0 - dspck_dsio precequ.ph.qbl, 0x40000000, 0x80004000, 0x0, 0x0 - dspck_dsio precequ.ph.qbl, 0x60000080, 0xc0012001, 0x0, 0x0 - dspck_dsio precequ.ph.qbl, 0x3b002a00, 0x76543210, 0x0, 0x0 - - writemsg "[24] Test precequ.ph.qbr" - dspck_dsio precequ.ph.qbr, 0x0, 0x0, 0x0, 0x0 - dspck_dsio precequ.ph.qbr, 0x7f807f80, 0xffffffff, 0x0, 0x0 - dspck_dsio precequ.ph.qbr, 0x20000000, 0x80004000, 0x0, 0x0 - dspck_dsio precequ.ph.qbr, 0x10000080, 0xc0012001, 0x0, 0x0 - dspck_dsio precequ.ph.qbr, 0x19000800, 0x76543210, 0x0, 0x0 - - writemsg "[25] Test precequ.ph.qbla" - dspck_dsio precequ.ph.qbla, 0x0, 0x0, 0x0, 0x0 - dspck_dsio precequ.ph.qbla, 0x7f807f80, 0xffffffff, 0x0, 0x0 - dspck_dsio precequ.ph.qbla, 0x40002000, 0x80004000, 0x0, 0x0 - dspck_dsio precequ.ph.qbla, 0x60001000, 0xc0012001, 0x0, 0x0 - dspck_dsio precequ.ph.qbla, 0x3b001900, 0x76543210, 0x0, 0x0 - - writemsg "[26] Test precequ.ph.qbra" - dspck_dsio precequ.ph.qbra, 0x0, 0x0, 0x0, 0x0 - dspck_dsio precequ.ph.qbra, 0x7f807f80, 0xffffffff, 0x0, 0x0 - dspck_dsio precequ.ph.qbra, 0x0, 0x80004000, 0x0, 0x0 - dspck_dsio precequ.ph.qbra, 0x800080, 0xc0012001, 0x0, 0x0 - dspck_dsio precequ.ph.qbra, 0x2a000800, 0x76543210, 0x0, 0x0 - - writemsg "[27] Test preceu.ph.qbl" - dspck_dsio preceu.ph.qbl, 0x0, 0x0, 0x0, 0x0 - dspck_dsio preceu.ph.qbl, 0xff00ff, 0xffffffff, 0x0, 0x0 - dspck_dsio preceu.ph.qbl, 0x800000, 0x80004000, 0x0, 0x0 - dspck_dsio preceu.ph.qbl, 0xc00001, 0xc0012001, 0x0, 0x0 - dspck_dsio preceu.ph.qbl, 0x760054, 0x76543210, 0x0, 0x0 - - writemsg "[28] Test preceu.ph.qbr" - dspck_dsio preceu.ph.qbr, 0x0, 0x0, 0x0, 0x0 - dspck_dsio preceu.ph.qbr, 0xff00ff, 0xffffffff, 0x0, 0x0 - dspck_dsio preceu.ph.qbr, 0x400000, 0x80004000, 0x0, 0x0 - dspck_dsio preceu.ph.qbr, 0x200001, 0xc0012001, 0x0, 0x0 - dspck_dsio preceu.ph.qbr, 0x320010, 0x76543210, 0x0, 0x0 - - writemsg "[29] Test preceu.ph.qbla" - dspck_dsio preceu.ph.qbla, 0x0, 0x0, 0x0, 0x0 - dspck_dsio preceu.ph.qbla, 0xff00ff, 0xffffffff, 0x0, 0x0 - dspck_dsio preceu.ph.qbla, 0x800040, 0x80004000, 0x0, 0x0 - dspck_dsio preceu.ph.qbla, 0xc00020, 0xc0012001, 0x0, 0x0 - dspck_dsio preceu.ph.qbla, 0x760032, 0x76543210, 0x0, 0x0 - - writemsg "[30] Test preceu.ph.qbra" - dspck_dsio preceu.ph.qbra, 0x0, 0x0, 0x0, 0x0 - dspck_dsio preceu.ph.qbra, 0xff00ff, 0xffffffff, 0x0, 0x0 - dspck_dsio preceu.ph.qbra, 0x0, 0x80004000, 0x0, 0x0 - dspck_dsio preceu.ph.qbra, 0x10001, 0xc0012001, 0x0, 0x0 - dspck_dsio preceu.ph.qbra, 0x540010, 0x76543210, 0x0, 0x0 - - writemsg "[31] Test shll.qb" - dspck_dtsaio shll.qb, 0x0, 0x0, 0, 0x0, 0x0 - dspck_dtsai shll.qb, 0x202fefe, 0x101ffff, 1, 0x0 - dspck_dtsai shll.qb, 0xfefe0002, 0x7fff8081, 1, 0x0 - dspck_dtsai shll.qb, 0xfcfc0020, 0x7fff8008, 2, 0x0 - dspck_dtsai shll.qb, 0x68b0d868, 0x6db6db6d, 3, 0x0 - - writemsg "[32] Test shllv.qb" - dspck_dstio shllv.qb, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dsti shllv.qb, 0x202fefe, 0x101ffff, 0x1, 0x0 - dspck_dsti shllv.qb, 0xfefe0002, 0x7fff8081, 0x1, 0x0 - dspck_dsti shllv.qb, 0xfcfc0020, 0x7fff8008, 0x2, 0x0 - dspck_dsti shllv.qb, 0x68b0d868, 0x6db6db6d, 0x3, 0x0 - - writemsg "[33] Test shll.ph" - dspck_dtsaio shll.ph, 0x0, 0x0, 0, 0x0, 0x0 - dspck_dtsaio shll.ph, 0x2fffe, 0x1ffff, 1, 0x0, 0x0 - dspck_dtsaio shll.ph, 0xfffe0000, 0x7fff8000, 1, 0x0, 0x400000 - dspck_dtsaio shll.ph, 0xfffc0020, 0x7fff8008, 2, 0x0, 0x400000 - dspck_dtsaio shll.ph, 0x6db0db68, 0x6db6db6d, 3, 0x0, 0x400000 - - writemsg "[34] Test shllv.ph" - dspck_dstio shllv.ph, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio shllv.ph, 0x2fffe, 0x1ffff, 0x1, 0x0, 0x0 - dspck_dstio shllv.ph, 0xfffe0000, 0x7fff8000, 0x1, 0x0, 0x400000 - dspck_dstio shllv.ph, 0xfffc0020, 0x7fff8008, 0x2, 0x0, 0x400000 - dspck_dstio shllv.ph, 0x6db0db68, 0x6db6db6d, 0x3, 0x0, 0x400000 - - writemsg "[35] Test shll_s.ph" - dspck_dtsaio shll_s.ph, 0x0, 0x0, 0, 0x0, 0x0 - dspck_dtsaio shll_s.ph, 0x2fffe, 0x1ffff, 1, 0x0, 0x0 - dspck_dtsaio shll_s.ph, 0x7fff8000, 0x7fff8000, 1, 0x0, 0x400000 - dspck_dtsaio shll_s.ph, 0x7fff8000, 0x7fff8008, 2, 0x0, 0x400000 - dspck_dtsaio shll_s.ph, 0x7fff8000, 0x6db6db6d, 3, 0x0, 0x400000 - - writemsg "[36] Test shllv_s.ph" - dspck_dstio shllv_s.ph, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio shllv_s.ph, 0x2fffe, 0x1ffff, 0x1, 0x0, 0x0 - dspck_dstio shllv_s.ph, 0x7fff8000, 0x7fff8000, 0x1, 0x0, 0x400000 - dspck_dstio shllv_s.ph, 0x7fff8000, 0x7fff8008, 0x2, 0x0, 0x400000 - dspck_dstio shllv_s.ph, 0x7fff8000, 0x6db6db6d, 0x3, 0x0, 0x400000 - - writemsg "[37] Test shll_s.w" - dspck_dtsaio shll_s.w, 0x0, 0x0, 0, 0x0, 0x0 - dspck_dtsaio shll_s.w, 0x3fffe, 0x1ffff, 1, 0x0, 0x0 - dspck_dtsaio shll_s.w, 0x7fffffff, 0x7fff8000, 1, 0x0, 0x400000 - dspck_dtsaio shll_s.w, 0x80000000, 0x80000000, 1, 0x0, 0x400000 - dspck_dtsaio shll_s.w, 0x7fffffff, 0x7fff8008, 2, 0x0, 0x400000 - - writemsg "[38] Test shllv_s.w" - dspck_dstio shllv_s.w, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio shllv_s.w, 0x3fffe, 0x1ffff, 0x1, 0x0, 0x0 - dspck_dstio shllv_s.w, 0x7fffffff, 0x7fff8000, 0x1, 0x0, 0x400000 - dspck_dstio shllv_s.w, 0x80000000, 0x80000000, 0x1, 0x0, 0x400000 - dspck_dstio shllv_s.w, 0x7fffffff, 0x7fff8008, 0x2, 0x0, 0x400000 - - writemsg "[39] Test shrl.qb" - dspck_dtsaio shrl.qb, 0x0, 0x0, 0, 0x0, 0x0 - dspck_dtsai shrl.qb, 0x7f7f, 0x101ffff, 1, 0x0 - dspck_dtsai shrl.qb, 0x3f7f4040, 0x7fff8081, 1, 0x0 - dspck_dtsai shrl.qb, 0x1f3f2002, 0x7fff8008, 2, 0x0 - dspck_dtsai shrl.qb, 0xd161b0d, 0x6db6db6d, 3, 0x0 - - writemsg "[40] Test shrlv.qb" - dspck_dstio shrlv.qb, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dsti shrlv.qb, 0x7f7f, 0x101ffff, 0x1, 0x0 - dspck_dsti shrlv.qb, 0x3f7f4040, 0x7fff8081, 0x1, 0x0 - dspck_dsti shrlv.qb, 0x1f3f2002, 0x7fff8008, 0x2, 0x0 - dspck_dsti shrlv.qb, 0xd161b0d, 0x6db6db6d, 0x3, 0x0 - - writemsg "[41] Test shra.ph" - dspck_dtsaio shra.ph, 0x10001, 0x20002, 1, 0x0, 0x0 - dspck_dtsaio shra.ph, 0x10006, 0x10106f6f, 12, 0x0, 0x0 - dspck_dtsaio shra.ph, 0x1c000, 0x28000, 1, 0x0, 0x0 - dspck_dtsaio shra.ph, 0x2f800, 0x208000, 4, 0x0, 0x0 - dspck_dtsaio shra.ph, 0xfc01fc00, 0x80208000, 5, 0x0, 0x0 - - writemsg "[42] Test shrav.ph" - dspck_dstio shrav.ph, 0x10001, 0x20002, 0x1, 0x0, 0x0 - dspck_dstio shrav.ph, 0x10006, 0x10106f6f, 0xc, 0x0, 0x0 - dspck_dstio shrav.ph, 0x1c000, 0x28000, 0x1, 0x0, 0x0 - dspck_dstio shrav.ph, 0x2f800, 0x208000, 0x4, 0x0, 0x0 - dspck_dstio shrav.ph, 0xfc01fc00, 0x80208000, 0x5, 0x0, 0x0 - - writemsg "[43] Test shra_r.ph" - dspck_dtsaio shra_r.ph, 0x20001, 0x30002, 1, 0x0, 0x0 - dspck_dtsaio shra_r.ph, 0x10001, 0x20001, 1, 0x0, 0x0 - dspck_dtsaio shra_r.ph, 0x10001, 0x10001, 1, 0x0, 0x0 - dspck_dtsaio shra_r.ph, 0x0, 0x10001, 2, 0x0, 0x0 - dspck_dtsaio shra_r.ph, 0x7fff8000, 0x7fff8000, 0, 0x0, 0x0 - dspck_dtsaio shra_r.ph, 0x4000c000, 0x7fff8000, 1, 0x0, 0x0 - dspck_dtsaio shra_r.ph, 0x2000e000, 0x7ffe8000, 2, 0x0, 0x0 - - writemsg "[44] Test shrav_r.ph" - dspck_dstio shrav_r.ph, 0x20001, 0x30002, 0x1, 0x0, 0x0 - dspck_dstio shrav_r.ph, 0x10001, 0x20001, 0x1, 0x0, 0x0 - dspck_dstio shrav_r.ph, 0x10001, 0x10001, 0x1, 0x0, 0x0 - dspck_dstio shrav_r.ph, 0x0, 0x10001, 0x2, 0x0, 0x0 - dspck_dstio shrav_r.ph, 0x7fff8000, 0x7fff8000, 0, 0x0, 0x0 - dspck_dstio shrav_r.ph, 0x2000e000, 0x7fff8000, 2, 0x0, 0x0 - - writemsg "[45] Test shra_r.w" - dspck_dtsaio shra_r.w, 0x1, 0x2, 1, 0x0, 0x0 - dspck_dtsaio shra_r.w, 0xffff8000, 0x80000000, 16, 0x0, 0x0 - dspck_dtsaio shra_r.w, 0x8001, 0x10001, 1, 0x0, 0x0 - dspck_dtsaio shra_r.w, 0x1, 0x10001, 17, 0x0, 0x0 - dspck_dtsaio shra_r.w, 0xffffc001, 0x80010001, 17, 0x0, 0x0 - dspck_dtsaio shra_r.w, 0x7fffffff, 0x7fffffff, 0, 0x0, 0x0 - dspck_dtsaio shra_r.w, 0x40000000, 0x7fffffff, 1, 0x0, 0x0 - dspck_dtsaio shra_r.w, 0x20000000, 0x7ffffffe, 2, 0x0, 0x0 - - writemsg "[46] Test shrav_r.w" - dspck_dstio shrav_r.w, 0x1, 0x2, 0x1, 0x0, 0x0 - dspck_dstio shrav_r.w, 0xffff8000, 0x80000000, 0x10, 0x0, 0x0 - dspck_dstio shrav_r.w, 0x8001, 0x10001, 0x1, 0x0, 0x0 - dspck_dstio shrav_r.w, 0x8001, 0x10001, 0x21, 0x0, 0x0 - dspck_dstio shrav_r.w, 0x4000, 0x10001, 0x2, 0x0, 0x0 - dspck_dstio shrav_r.w, 0x7fffffff, 0x7fffffff, 0x0, 0x0, 0x0 - dspck_dstio shrav_r.w, 0x10000000, 0x7ffffffc, 0x3, 0x0, 0x0 - dspck_dstio shrav_r.w, 0x08000000, 0x7ffffff8, 0x4, 0x0, 0x0 - - writemsg "[47] Test muleu_s.ph.qbl" - dspck_dstio muleu_s.ph.qbl, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio muleu_s.ph.qbl, 0x0, 0x0, 0x40004000, 0x0, 0x0 - dspck_dstio muleu_s.ph.qbl, 0x0, 0xffffffff, 0x0, 0x0, 0x0 - dspck_dstio muleu_s.ph.qbl, 0x10001, 0x1010101, 0x10001, 0x0, 0x0 - dspck_dstio muleu_s.ph.qbl, 0x10000, 0x1000001, 0x10001, 0x0, 0x0 - - writemsg "[48] Test muleu_s.ph.qbr" - dspck_dstio muleu_s.ph.qbr, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio muleu_s.ph.qbr, 0x0, 0x0, 0x40004000, 0x0, 0x0 - dspck_dstio muleu_s.ph.qbr, 0x0, 0xffffffff, 0x0, 0x0, 0x0 - dspck_dstio muleu_s.ph.qbr, 0x10001, 0x1010101, 0x10001, 0x0, 0x0 - dspck_dstio muleu_s.ph.qbr, 0x1, 0x1000001, 0x10001, 0x0, 0x0 - - writemsg "[49] Test mulq_rs.ph" - dspck_dstio mulq_rs.ph, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio mulq_rs.ph, 0x0, 0x1, 0x1, 0x0, 0x0 - dspck_dstio mulq_rs.ph, 0x20000000, 0x40007fff, 0x40000000, 0x0, 0x0 - dspck_dstio mulq_rs.ph, 0x33330000, 0x66660000, 0x40007fff, 0x0, 0x0 - dspck_dstio mulq_rs.ph, 0xccd3332, 0x66666666, 0x10003fff, 0x0, 0x0 - - writemsg "[50] Test muleq_s.w.phl" - dspck_dstio muleq_s.w.phl, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio muleq_s.w.phl, 0x0, 0x0, 0x40004000, 0x0, 0x0 - dspck_dstio muleq_s.w.phl, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0 - dspck_dstio muleq_s.w.phl, 0x0, 0x0, 0xc000c000, 0x0, 0x0 - dspck_dstio muleq_s.w.phl, 0x0, 0x80008000, 0x0, 0x0, 0x0 - - writemsg "[51] Test muleq_s.w.phr" - dspck_dstio muleq_s.w.phr, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio muleq_s.w.phr, 0x0, 0x0, 0x40004000, 0x0, 0x0 - dspck_dstio muleq_s.w.phr, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0 - dspck_dstio muleq_s.w.phr, 0x0, 0x0, 0xc000c000, 0x0, 0x0 - dspck_dstio muleq_s.w.phr, 0x0, 0x80008000, 0x0, 0x0, 0x0 - - writemsg "[52] Test dpau.h.qbl" - dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0x1, 0x1010101, 0x1000001, 0x0, 0x0 - dspck_astio dpau.h.qbl, 0xffffffff, 0xffffffff, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0 - dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0 - dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0xff, 0xffff0001, 0x1ffff, 0x0, 0x0 - - writemsg "[53] Test dpau.h.qbr" - dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0x1, 0x1010101, 0x1000001, 0x0, 0x0 - dspck_astio dpau.h.qbr, 0xffffffff, 0xffffffff, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0 - dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0 - dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0xff, 0xffff0001, 0x1ffff, 0x0, 0x0 - - writemsg "[54] Test dpsu.h.qbl" - dspck_astio dpsu.h.qbl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio dpsu.h.qbl, 0x0, 0x1, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0 - dspck_astio dpsu.h.qbl, 0x0, 0x0, 0xffffffff, 0xffffffff, 0x1010101, 0x1000001, 0x0, 0x0 - dspck_astio dpsu.h.qbl, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0 - dspck_astio dpsu.h.qbl, 0x0, 0xff, 0x0, 0x0, 0xffff0001, 0x1ffff, 0x0, 0x0 - - writemsg "[55] Test dpsu.h.qbr" - dspck_astio dpsu.h.qbr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio dpsu.h.qbr, 0x0, 0x1, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0 - dspck_astio dpsu.h.qbr, 0x0, 0x0, 0xffffffff, 0xffffffff, 0x1010101, 0x1000001, 0x0, 0x0 - dspck_astio dpsu.h.qbr, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0 - dspck_astio dpsu.h.qbr, 0x0, 0xff, 0x0, 0x0, 0xffff0001, 0x1ffff, 0x0, 0x0 - - writemsg "[56] Test dpaq_s.w.ph" - dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0x0, 0xfffc0004, 0x7fff7fff, 0x7fff7fff, 0x0, 0x0 - dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0x0, 0xfffffffe, 0x80008000, 0x80008000, 0x0, 0xf0000 - dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0xffffffff, 0xa0000000, 0x40002000, 0x80008000, 0x0, 0x0 - dspck_astio dpaq_s.w.ph, 0xffffffff, 0xa0000000, 0xffffffff, 0x88000000, 0x10000800, 0x80008000, 0x0, 0x0 - - writemsg "[57] Test dpsq_s.w.ph" - dspck_astio dpsq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio dpsq_s.w.ph, 0x0, 0xfffc0004, 0x0, 0x0, 0x7fff7fff, 0x7fff7fff, 0x0, 0x0 - dspck_astio dpsq_s.w.ph, 0x0, 0xfffffffe, 0x0, 0x0, 0x80008000, 0x80008000, 0x0, 0xf0000 - dspck_astio dpsq_s.w.ph, 0xffffffff, 0xa0000000, 0x0, 0x0, 0x40002000, 0x80008000, 0x0, 0x0 - dspck_astio dpsq_s.w.ph, 0xffffffff, 0x88000000, 0xffffffff, 0xa0000000, 0x10000800, 0x80008000, 0x0, 0x0 - - writemsg "[58] Test mulsaq_s.w.ph" - dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x4000, 0xc0000000, 0x0, 0x0 - dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0xffffffff, 0x60010000, 0x80004000, 0x7fff4000, 0x0, 0x0 - dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0x0, 0x5fffffff, 0x80004000, 0x80004000, 0x0, 0xf0000 - dspck_astio mulsaq_s.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0xfffc0003, 0x7fff8001, 0x7fff7fff, 0x0, 0x0 - - writemsg "[59] Test dpaq_sa.l.w" - dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0x7ffffffe, 0x2, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0x7fffffff, 0xffffffff, 0x80000000, 0x80000000, 0x0, 0xf0000 - dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0xc0000000, 0x80000000, 0xc0000000, 0x7fffffff, 0x0, 0x0 - dspck_astio dpaq_sa.l.w, 0x20000000, 0x0, 0x0, 0x40000000, 0xe0000000, 0x7fffffff, 0x0, 0x0 - - writemsg "[60] Test dpsq_sa.l.w" - dspck_astio dpsq_sa.l.w, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio dpsq_sa.l.w, 0x7fffffff, 0xffffffff, 0x0, 0x0, 0x80000000, 0x80000000, 0x0, 0xf0000 - dspck_astio dpsq_sa.l.w, 0x80000000, 0x0, 0x80000000, 0x0, 0x80000000, 0x80000000, 0x0, 0xf0000 - dspck_astio dpsq_sa.l.w, 0x0, 0x0, 0x80000000, 0x1, 0x80000000, 0x80000000, 0x0, 0xf0000 - dspck_astio dpsq_sa.l.w, 0x0, 0x0, 0x3fffffff, 0x80000000, 0xc0000000, 0x7fffffff, 0x0, 0x0 - - writemsg "[61] Test maq_s.w.phl" - dspck_astio maq_s.w.phl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio maq_s.w.phl, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x0, 0x40004000, 0x0, 0x0 - dspck_astio maq_s.w.phl, 0x0, 0xffffffff, 0x0, 0xffffffff, 0x7fff7fff, 0x0, 0x0, 0x0 - dspck_astio maq_s.w.phl, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0 - dspck_astio maq_s.w.phl, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000, 0x0, 0x0 - - writemsg "[62] Test maq_s.w.phr" - dspck_astio maq_s.w.phr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio maq_s.w.phr, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x0, 0x40004000, 0x0, 0x0 - dspck_astio maq_s.w.phr, 0x0, 0xffffffff, 0x0, 0xffffffff, 0x7fff7fff, 0x0, 0x0, 0x0 - dspck_astio maq_s.w.phr, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0 - dspck_astio maq_s.w.phr, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000, 0x0, 0x0 - - writemsg "[63] Test maq_sa.w.phl" - dspck_astio maq_sa.w.phl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio maq_sa.w.phl, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0, 0x40004000, 0x0, 0x0 - dspck_astio maq_sa.w.phl, 0x0, 0x7fffffff, 0x0, 0x7fffffff, 0x7fff7fff, 0x0, 0x0, 0x0 - dspck_astio maq_sa.w.phl, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7fff7fff, 0x0, 0x0, 0x0 - dspck_astio maq_sa.w.phl, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000, 0x0, 0x0 - - writemsg "[64] Test maq_sa.w.phr" - dspck_astio maq_sa.w.phr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_astio maq_sa.w.phr, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0, 0x40004000, 0x0, 0x0 - dspck_astio maq_sa.w.phr, 0x0, 0x7fffffff, 0x0, 0x7fffffff, 0x7fff7fff, 0x0, 0x0, 0x0 - dspck_astio maq_sa.w.phr, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7fff7fff, 0x0, 0x0, 0x0 - dspck_astio maq_sa.w.phr, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000, 0x0, 0x0 - - writemsg "[65] Test bitrev" - dspck_dsio bitrev, 0x0, 0x0, 0x0, 0x0 - dspck_dsio bitrev, 0x1, 0x8000, 0x0, 0x0 - dspck_dsio bitrev, 0x8000, 0x1, 0x0, 0x0 - dspck_dsio bitrev, 0xc0c0, 0x1010303, 0x0, 0x0 - dspck_dsio bitrev, 0x1, 0xffff8000, 0x0, 0x0 - - writemsg "[66] Test insv" - dspck_tsi insv, 0xf0caf0f0, 0xf0f0f0f0, 0xa5a5a5a5, 0x311 - dspck_tsi insv, 0x7fffffe, 0x0, 0x7ffffff, 0xd01 - dspck_tsi insv, 0x3fff, 0x0, 0x3fff, 0x700 - dspck_tsi insv, 0xf0f2f0f0, 0xf0f0f0f0, 0xa5a5a5a5, 0x28f - dspck_tsi insv, 0x3fc, 0x0, 0x3ff, 0x402 - - writemsg "[67] Test repl.qb" - dspck_dIio repl.qb, 0x0, 0, 0x0, 0x0 - dspck_dIio repl.qb, 0x1010101, 1, 0x0, 0x0 - dspck_dIio repl.qb, 0xffffffff, 255, 0x0, 0x0 - dspck_dIio repl.qb, 0x7f7f7f7f, 127, 0x0, 0x0 - dspck_dIio repl.qb, 0xfefefefe, 254, 0x0, 0x0 - - writemsg "[68] Test replv.qb" - dspck_dsio replv.qb, 0x0, 0x0, 0x0, 0x0 - dspck_dsio replv.qb, 0x1010101, 0x1, 0x0, 0x0 - dspck_dsio replv.qb, 0xffffffff, 0xff, 0x0, 0x0 - dspck_dsio replv.qb, 0x7f7f7f7f, 0x37f, 0x0, 0x0 - dspck_dsio replv.qb, 0xfefefefe, 0xfffffffe, 0x0, 0x0 - - writemsg "[69] Test repl.ph" - dspck_dIio repl.ph, 0x0, 0, 0x0, 0x0 - dspck_dIio repl.ph, 0x10001, 1, 0x0, 0x0 - dspck_dIio repl.ph, 0xffffffff, -1, 0x0, 0x0 - dspck_dIio repl.ph, 0xff7fff7f, -129, 0x0, 0x0 - dspck_dIio repl.ph, 0xfffefffe, -2, 0x0, 0x0 - - writemsg "[70] Test replv.ph" - dspck_dsio replv.ph, 0x0, 0x0, 0x0, 0x0 - dspck_dsio replv.ph, 0x10001, 0x1, 0x0, 0x0 - dspck_dsio replv.ph, 0xffffffff, 0x5555ffff, 0x0, 0x0 - dspck_dsio replv.ph, 0x37f037f, 0x37f, 0x0, 0x0 - dspck_dsio replv.ph, 0xfffefffe, 0xfffffffe, 0x0, 0x0 - - writemsg "[71] Test cmpu.eq.qb" - dspck_stio cmpu.eq.qb, 0x0, 0x0, 0x0, 0xf000000 - dspck_stio cmpu.eq.qb, 0xffffffff, 0x0, 0x0, 0x0 - dspck_stio cmpu.eq.qb, 0x0, 0xffffffff, 0x0, 0x0 - dspck_stio cmpu.eq.qb, 0x10203, 0x4050607, 0x0, 0x0 - dspck_stio cmpu.eq.qb, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0 - - writemsg "[72] Test cmpu.lt.qb" - dspck_stio cmpu.lt.qb, 0x0, 0x0, 0x0, 0x0 - dspck_stio cmpu.lt.qb, 0xffffffff, 0x0, 0x0, 0x0 - dspck_stio cmpu.lt.qb, 0x0, 0xffffffff, 0x0, 0xf000000 - dspck_stio cmpu.lt.qb, 0x10203, 0x4050607, 0x0, 0xf000000 - dspck_stio cmpu.lt.qb, 0x8090a0b, 0xc0d0e0f, 0x0, 0xf000000 - - writemsg "[73] Test cmpu.le.qb" - dspck_stio cmpu.le.qb, 0x0, 0x0, 0x0, 0xf000000 - dspck_stio cmpu.le.qb, 0xffffffff, 0x0, 0x0, 0x0 - dspck_stio cmpu.le.qb, 0x0, 0xffffffff, 0x0, 0xf000000 - dspck_stio cmpu.le.qb, 0x10203, 0x4050607, 0x0, 0xf000000 - dspck_stio cmpu.le.qb, 0x8090a0b, 0xc0d0e0f, 0x0, 0xf000000 - - writemsg "[74] Test cmpgu.eq.qb" - dspck_dstio cmpgu.eq.qb, 0xf, 0x0, 0x0, 0x0, 0x0 - dspck_dstio cmpgu.eq.qb, 0x0, 0xffffffff, 0x0, 0x0, 0x0 - dspck_dstio cmpgu.eq.qb, 0x0, 0x0, 0xffffffff, 0x0, 0x0 - dspck_dstio cmpgu.eq.qb, 0x0, 0x10203, 0x4050607, 0x0, 0x0 - dspck_dstio cmpgu.eq.qb, 0x0, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0 - - writemsg "[75] Test cmpgu.lt.qb" - dspck_dstio cmpgu.lt.qb, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_dstio cmpgu.lt.qb, 0x0, 0xffffffff, 0x0, 0x0, 0x0 - dspck_dstio cmpgu.lt.qb, 0xf, 0x0, 0xffffffff, 0x0, 0x0 - dspck_dstio cmpgu.lt.qb, 0xf, 0x10203, 0x4050607, 0x0, 0x0 - dspck_dstio cmpgu.lt.qb, 0xf, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0 - - writemsg "[76] Test cmpgu.le.qb" - dspck_dstio cmpgu.le.qb, 0xf, 0x0, 0x0, 0x0, 0x0 - dspck_dstio cmpgu.le.qb, 0x0, 0xffffffff, 0x0, 0x0, 0x0 - dspck_dstio cmpgu.le.qb, 0xf, 0x0, 0xffffffff, 0x0, 0x0 - dspck_dstio cmpgu.le.qb, 0xf, 0x10203, 0x4050607, 0x0, 0x0 - dspck_dstio cmpgu.le.qb, 0xf, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0 - - writemsg "[77] Test cmp.eq.ph" - dspck_stio cmp.eq.ph, 0x0, 0x0, 0x0, 0x3000000 - dspck_stio cmp.eq.ph, 0x0, 0xffffffff, 0x0, 0x0 - dspck_stio cmp.eq.ph, 0xffffffff, 0x0, 0x0, 0x0 - dspck_stio cmp.eq.ph, 0x7fff7fff, 0xffffffff, 0x0, 0x0 - dspck_stio cmp.eq.ph, 0x11112222, 0x33334444, 0x0, 0x0 - - writemsg "[78] Test cmp.lt.ph" - dspck_stio cmp.lt.ph, 0x0, 0x0, 0x0, 0x0 - dspck_stio cmp.lt.ph, 0x0, 0xffffffff, 0x0, 0x0 - dspck_stio cmp.lt.ph, 0xffffffff, 0x0, 0x0, 0x3000000 - dspck_stio cmp.lt.ph, 0x7fff7fff, 0xffffffff, 0x0, 0x0 - dspck_stio cmp.lt.ph, 0x11112222, 0x33334444, 0x0, 0x3000000 - - writemsg "[79] Test cmp.le.ph" - dspck_stio cmp.le.ph, 0x0, 0x0, 0x0, 0x3000000 - dspck_stio cmp.le.ph, 0x0, 0xffffffff, 0x0, 0x0 - dspck_stio cmp.le.ph, 0xffffffff, 0x0, 0x0, 0x3000000 - dspck_stio cmp.le.ph, 0x7fff7fff, 0xffffffff, 0x0, 0x0 - dspck_stio cmp.le.ph, 0x11112222, 0x33334444, 0x0, 0x3000000 - - writemsg "[80] Test pick.qb" - dspck_dsti pick.qb, 0x0, 0x0, 0x0, 0x0 - dspck_dsti pick.qb, 0x0, 0xffffffff, 0x0, 0x0 - dspck_dsti pick.qb, 0xffffffff, 0xffffffff, 0x0, 0xf000000 - dspck_dsti pick.qb, 0xff, 0xffffffff, 0x0, 0x1000000 - dspck_dsti pick.qb, 0xff00, 0xffffffff, 0x0, 0x2000000 - - writemsg "[81] Test pick.ph" - dspck_dsti pick.ph, 0x0, 0x0, 0x0, 0x0 - dspck_dsti pick.ph, 0x0, 0xffffffff, 0x0, 0x0 - dspck_dsti pick.ph, 0xffffffff, 0xffffffff, 0x0, 0x3000000 - dspck_dsti pick.ph, 0xffff, 0xffffffff, 0x0, 0x1000000 - dspck_dsti pick.ph, 0xffff0000, 0xffffffff, 0x0, 0x2000000 - - writemsg "[82] Test packrl.ph" - dspck_dstio packrl.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio packrl.ph, 0x0000ffff, 0x00000000, 0xffff0000, 0x0, 0x0 - dspck_dstio packrl.ph, 0x00000000, 0x00000000, 0x0000ffff, 0x0, 0x0 - dspck_dstio packrl.ph, 0x00005555, 0x00000000, 0x5555aaaa, 0x0, 0x0 - dspck_dstio packrl.ph, 0x0000aaaa, 0x00000000, 0xaaaa5555, 0x0, 0x0 - - writemsg "[83] Test extr.w" - dspck_atsaio extr.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 - dspck_atsaio extr.w, 0x7fffffff, 0xcbcdef01 0xffffffff, 0x1f, 0x0, 0x800000 - dspck_atsaio extr.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0 - dspck_atsaio extr.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 - dspck_atsaio extr.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0 - - writemsg "[84] Test extr_r.w" - dspck_atsaio extr_r.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 - dspck_atsaio extr_r.w, 0x7fffffff, 0xcbcdef01 0x0, 0x1f, 0x0, 0x800000 - dspck_atsaio extr_r.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0 - dspck_atsaio extr_r.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 - dspck_atsaio extr_r.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0 - - writemsg "[85] Test extr_rs.w" - dspck_atsaio extr_rs.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 - dspck_atsaio extr_rs.w, 0x7fffffff, 0xcbcdef01 0x7fffffff, 0x1f, 0x0, 0x800000 - dspck_atsaio extr_rs.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0 - dspck_atsaio extr_rs.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 - dspck_atsaio extr_rs.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0 - - writemsg "[86] Test extr_s.h" - dspck_atsaio extr_s.h, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 - dspck_atsaio extr_s.h, 0x7fffffff, 0xcbcdef01 0x7fff, 0x1f, 0x0, 0x800000 - dspck_atsaio extr_s.h, 0x3fffffff, 0x2bcdef01 0x7fff, 0x1f, 0x0, 0x800000 - dspck_atsaio extr_s.h, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 - dspck_atsaio extr_s.h, 0x0, 0xfffffffe 0x7fff, 0x1, 0x0, 0x800000 - - writemsg "[87] Test extrv_s.h" - dspck_atsio extrv_s.h, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 - dspck_atsio extrv_s.h, 0x7fffffff, 0xcbcdef01 0x7fff, 0x1f, 0x0, 0x800000 - dspck_atsio extrv_s.h, 0x3fffffff, 0x2bcdef01 0x7fff, 0x1f, 0x0, 0x800000 - dspck_atsio extrv_s.h, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 - dspck_atsio extrv_s.h, 0x0, 0xfffffffe 0x7fff, 0x1, 0x0, 0x800000 - - writemsg "[88] Test extrv.w" - dspck_atsio extrv.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 - dspck_atsio extrv.w, 0x7fffffff, 0xcbcdef01 0xffffffff, 0x1f, 0x0, 0x800000 - dspck_atsio extrv.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0 - dspck_atsio extrv.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 - dspck_atsio extrv.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0 - - writemsg "[89] Test extrv_r.w" - dspck_atsio extrv_r.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 - dspck_atsio extrv_r.w, 0x7fffffff, 0xcbcdef01 0x0, 0x1f, 0x0, 0x800000 - dspck_atsio extrv_r.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0 - dspck_atsio extrv_r.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 - dspck_atsio extrv_r.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0 - - writemsg "[90] Test extrv_rs.w" - dspck_atsio extrv_rs.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0 - dspck_atsio extrv_rs.w, 0x7fffffff, 0xcbcdef01 0x7fffffff, 0x1f, 0x0, 0x800000 - dspck_atsio extrv_rs.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0 - dspck_atsio extrv_rs.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0 - dspck_atsio extrv_rs.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0 - - writemsg "[91] Test extp" - dspck_tasiimom extp, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x0, 0x403f - dspck_tasiimom extp, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x4000 - dspck_tasiim extp, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f - dspck_tasiim extp, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f - - writemsg "[92] Test extpv" - dspck_tasimom extpv, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x0, 0x403f - dspck_tasimom extpv, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x4000 - dspck_tasim extpv, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f - dspck_tasim extpv, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f - - writemsg "[93] Test extpdp" - dspck_tasiimom extpdp, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x3f, 0x403f - dspck_tasiimom extpdp, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x4000 - dspck_tasiim extpdp, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f - dspck_tasiim extpdp, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f - - writemsg "[94] Test extpdpv" - dspck_tasimom extpdpv, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x3f, 0x403f - dspck_tasimom extpdpv, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x4000 - dspck_tasim extpdpv, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f - dspck_tasim extpdpv, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f - - writemsg "[95] Test shilo" - dspck_asaio shilo, 0x0, 0x0, 0x0, 0x0, 0, 0x0, 0x0 - dspck_asaio shilo, 0x1, 0x80000000, 0x1, 0x80000000, 0, 0x0, 0x0 - dspck_asaio shilo, 0x1, 0x80000000, 0x3, 0x0, -1, 0x0, 0x0 - dspck_asaio shilo, 0x1, 0x80000000, 0x6, 0x0, -2, 0x0, 0x0 - dspck_asaio shilo, 0x1, 0x80000000, 0x18, 0x0, -4, 0x0, 0x0 - - writemsg "[96] Test shilov" - dspck_asio shilov, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 - dspck_asio shilov, 0x1, 0x80000000, 0x1, 0x80000000, 0x0, 0x0, 0x0 - dspck_asio shilov, 0x1, 0x80000000, 0x3, 0x0, 0xffffffff, 0x0, 0x0 - dspck_asio shilov, 0x1, 0x80000000, 0x6, 0x0, 0xfffffffe, 0x0, 0x0 - dspck_asio shilov, 0x1, 0x80000000, 0x18, 0x0, 0xfffffffc, 0x0, 0x0 - - writemsg "[97] Test mthlip" - dspck_saio mthlip, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20 - dspck_saio mthlip, 0x0, 0x1, 0x1, 0x2, 0x2, 0x8, 0x28 - dspck_saio mthlip, 0xffffffff, 0xffff1234, 0xffff1234, 0xfffffffe, 0xfffffffe, 0x10, 0x30 - dspck_saio mthlip, 0xdeadbeef, 0x1234, 0x1234, 0xbeefdead, 0xbeefdead, 0x18, 0x38 - - writemsg "[98] Test wrdsp" - dspck_wrdsp 0x0, 0x0, 0x0, 0x0 - dspck_wrdsp 0x4000, 0x20, 0x0, 0x4000 - dspck_wrdsp 0xffffffff, 0x3f, 0x0, 0x0fff7fbf - dspck_wrdsp 0x3f, 0x1, 0x0, 0x3f - dspck_wrdsp 0x1f80, 0x2, 0x0, 0x1f80 - - writemsg "[99] Test rddsp" - dspck_rddsp 0x0, 0x0, 0x0 - dspck_rddsp 0x0, 0x0, 0xffffffff - dspck_rddsp 0x3f, 0x1, 0xffffffff - dspck_rddsp 0x1f80, 0x2, 0x0fff7fbf - dspck_rddsp 0x2000, 0x4, 0x0fff7fbf - - writemsg "[100] Test lbux" - .data -mydata: - .byte 0x12 - .byte 0x34 - .byte 0x56 - .byte 0x78 - .byte 0x9a - .byte 0xbc - .byte 0xde - .byte 0xf0 - .previous - dspck_load lbux, 0x12, 0x0, mydata - dspck_load lbux, 0x34, 0x1, mydata - dspck_load lbux, 0x56, 0x2, mydata - dspck_load lbux, 0x78, 0x3, mydata - dspck_load lbux, 0x9a, 0x4, mydata - dspck_load lbux, 0xbc, 0x5, mydata - dspck_load lbux, 0xde, 0x6, mydata - dspck_load lbux, 0xf0, 0x7, mydata - - writemsg "[101] Test lhx" - .data -myhdata: - .hword 0x1234 - .hword 0x5678 - .hword 0x9abc - .hword 0xdef0 - .previous - dspck_load lhx, 0x1234, 0x0, myhdata - dspck_load lhx, 0x5678, 0x2, myhdata - dspck_load lhx, 0xffff9abc, 0x4, myhdata - dspck_load lhx, 0xffffdef0, 0x6, myhdata - - writemsg "[102] Test lwx" - .data -mywdata: - .word 0x12345678 - .word 0x9abcdef0 - .word 0x13579abc - .word 0xffff0001 - .previous - dspck_load lwx, 0x12345678, 0x0, mywdata - dspck_load lwx, 0x9abcdef0, 0x4, mywdata - dspck_load lwx, 0x13579abc, 0x8, mywdata - dspck_load lwx, 0xffff0001, 0xc, mywdata - - writemsg "[103] Test bposge32" - dspck_bposge32 0x0, 0 - dspck_bposge32 0x1f, 0 - dspck_bposge32 0x20, 1 - dspck_bposge32 0x3f, 1 - - pass - .end DIAG - diff --git a/sim/testsuite/sim/mips/mips32-dsp2.s b/sim/testsuite/sim/mips/mips32-dsp2.s deleted file mode 100644 index 8c8384e..0000000 --- a/sim/testsuite/sim/mips/mips32-dsp2.s +++ /dev/null @@ -1,12360 +0,0 @@ -# MIPS32 DSP REV 2 ASE test -# mach: mips32r2 mips64r2 -#as: -mdspr2 -#ld: -N -Ttext=0x80010000 -#output: *\\npass\\n - -# Copyright (C) 2006 MIPS Technologies, Inc. -# All rights reserved. -# Contributed by Chao-ying Fu (fu@mips.com). -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, see . - - .include "testutils.inc" - .include "utils-dsp.inc" - - setup - - .set noreorder - - .ent DIAG -DIAG: - - writemsg "[1] Test absq_s.qb" - dspck_dsio absq_s.qb, 0x40670106, 0xc099ff06, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x001c0205, 0x001c0205, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x000e0001, 0x000e00ff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01000101, 0x0100ff01, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x03000204, 0x030002fc, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x1d060400, 0xe3060400, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0019017f, 0x0019ff81, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00716e1d, 0x007192e3, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x77060003, 0x77060003, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x6100011a, 0x9f00ff1a, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x06017d00, 0x06ff8300, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x54010601, 0x54ff0601, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x10000101, 0xf000ffff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x6b7d0001, 0x6b8300ff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01550101, 0x0155ffff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x20014900, 0xe0ff4900, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00086000, 0x00f86000, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x72030102, 0x8efdff02, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00720079, 0x008e0087, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x1f496115, 0x1f499f15, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x10010000, 0x10ff0000, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x7f010700, 0x8001f900, 0x00000000, 0x00100000 - dspck_dsio absq_s.qb, 0x4141017e, 0x41bfff7e, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x6d3f0156, 0x6d3fffaa, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0103091f, 0x010309e1, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x010e400d, 0xff0e40f3, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01060101, 0xff06ff01, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x047f0240, 0xfc81fec0, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x78141d01, 0x7814e3ff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x25000000, 0xdb000000, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00040200, 0x00fc0200, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x003f0207, 0x003f0207, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x000d0140, 0x000dffc0, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x7100001e, 0x7100001e, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0101401a, 0xffffc01a, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x660e0025, 0x660e00db, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x021b0100, 0x021b0100, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00000f09, 0x00000f09, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x0100081c, 0xff00f81c, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x05000000, 0x05000000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x21661801, 0xdf661801, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x3f013c01, 0x3fff3cff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01010101, 0xffffff01, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00000103, 0x00000103, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01340004, 0xffcc0004, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01000104, 0x0100ff04, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x011f1011, 0xffe11011, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x08000001, 0x080000ff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x057f0200, 0x05810200, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0c660001, 0x0c660001, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x72011c20, 0x8eff1ce0, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x0d007803, 0x0d007803, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x4a020070, 0xb6020070, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x21083c0e, 0xdf083c0e, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x563e0105, 0xaa3eff05, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x013c000d, 0xff3c00f3, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01380104, 0xff380104, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x08006e35, 0x08009235, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x121b0100, 0x121bff00, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x79000301, 0x870003ff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x0512616b, 0x05129f6b, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x0c010700, 0x0cff0700, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x6e0e0016, 0x920e0016, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x4a011901, 0xb6ffe7ff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x02010902, 0x02fff702, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x393d0800, 0xc7c3f800, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00070000, 0x00070000, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00003400, 0x0000cc00, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x003c0000, 0x003c0000, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00000900, 0x0000f700, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01397f01, 0xffc780ff, 0x00000000, 0x00100000 - dspck_dsio absq_s.qb, 0x01000146, 0xff00ff46, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01030000, 0xff030000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x7f010119, 0x80ffffe7, 0x00000000, 0x00100000 - dspck_dsio absq_s.qb, 0x0f011c00, 0x0fff1c00, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01491f0e, 0xff491f0e, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00013e03, 0x00013e03, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x24000101, 0x2400ffff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x000e3d00, 0x000e3d00, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00003d01, 0x00003d01, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x4a031100, 0xb603ef00, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x0104026e, 0xfffc0292, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00200d01, 0x0020f3ff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01133001, 0x011330ff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x21710261, 0x218f029f, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x7b030300, 0x7b030300, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x30007801, 0x30007801, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x016e0104, 0xff92fffc, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x31014024, 0xcfff4024, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x03790457, 0x03870457, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00010200, 0x00ff0200, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00081c01, 0x00081cff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x40011d61, 0x40ffe39f, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x7f406e41, 0x80c092bf, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x003d0001, 0x00c300ff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x031c0701, 0x031c07ff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0f1e0145, 0x0f1eff45, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x3d1f1307, 0xc31f1307, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x26010003, 0x26ff0003, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x003d5501, 0x00c35501, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x02707f04, 0x02708004, 0x00000000, 0x00100000 - dspck_dsio absq_s.qb, 0x35190139, 0x35e7ffc7, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x007e0101, 0x007eff01, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x7f33013e, 0x7f33ff3e, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x40004006, 0x4000c006, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00110100, 0x0011ff00, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x11300d0d, 0xef30f30d, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x15007f66, 0x15008066, 0x00000000, 0x00100000 - dspck_dsio absq_s.qb, 0x0c01041c, 0x0cff041c, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x02071800, 0x02071800, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x010b0100, 0xff0bff00, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01010201, 0x01ff0201, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00007f1f, 0x00007f1f, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x71011c00, 0x8f011c00, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01071667, 0xff071699, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00003f00, 0x0000c100, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x18010000, 0x18ff0000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x40013701, 0xc0ff37ff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x007f3e00, 0x00813e00, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x05000000, 0x05000000, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x0100215a, 0xff00df5a, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00010101, 0x000101ff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x0100046d, 0x0100046d, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00180604, 0x00180604, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x1a01070f, 0x1aff070f, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0205011e, 0x0205ff1e, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01000255, 0xff000255, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x66030030, 0x66030030, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x3e3f2406, 0x3e3f2406, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00330000, 0x00330000, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x100f0003, 0x10f10003, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x3f010119, 0xc10101e7, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0e010000, 0x0eff0000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x1c2b0107, 0x1c2b0107, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x7201081a, 0x8eff081a, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x71000303, 0x8f000303, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x04010102, 0x04ff0102, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x030d0c7d, 0x030d0c83, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0001017c, 0x00ffff7c, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x017f5500, 0xff7f5500, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00020101, 0x0002ff01, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01010000, 0x01010000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x08011720, 0xf8ff1720, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00240120, 0x0024ffe0, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0156210b, 0xffaadf0b, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0f0e0101, 0xf10effff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00190067, 0x00e70099, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x10010107, 0xf0ff0107, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01557e03, 0x01557e03, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01017101, 0xffff7101, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01003c56, 0xff003caa, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x05007001, 0x05007001, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x02021f08, 0x02021ff8, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x0033043f, 0x0033043f, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00020101, 0x0002ff01, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x07150440, 0x071504c0, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x513f0024, 0x513f0024, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x71016101, 0x8f019fff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x031e0e01, 0x031e0e01, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x7700060d, 0x770006f3, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01033c06, 0x01033c06, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0838061e, 0x0838061e, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0300001d, 0x030000e3, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00003d1f, 0x0000c3e1, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00005649, 0x0000aa49, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x013f010a, 0xffc1ff0a, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01030101, 0xff03ffff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x30000001, 0x300000ff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x010d4a02, 0xfff3b602, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x32020000, 0x32020000, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x31000407, 0xcf000407, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x1f010c00, 0xe1ff0c00, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x71037d00, 0x71038300, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x671c0004, 0x991c0004, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00010001, 0x00ff00ff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00000f00, 0x00000f00, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x38400101, 0x384001ff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x010e7002, 0xff0e7002, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x79000000, 0x87000000, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x18016e00, 0x18ff9200, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x003c1d7f, 0x003ce380, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x0001010d, 0x0001010d, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x1b30047f, 0x1b300480, 0x00000000, 0x00100000 - dspck_dsio absq_s.qb, 0x33370001, 0x333700ff, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x71003000, 0x8f003000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x013f070e, 0xff3f070e, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x0101210d, 0xffffdff3, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01020171, 0xff02ff8f, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x7d017200, 0x83ff8e00, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x10000401, 0x1000fc01, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x000d7e02, 0x00f37e02, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00010101, 0x0001ffff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x20000161, 0x2000019f, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00030501, 0x000305ff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01010118, 0xffff0118, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x09000436, 0x09000436, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x21010100, 0xdfffff00, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x181e0100, 0x181eff00, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x09020911, 0x09fef7ef, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x05010100, 0x05ffff00, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x61137201, 0x9f138e01, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x003f2400, 0x003f2400, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x7d3d0110, 0x833d01f0, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x700e1938, 0x700ee738, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x08011d01, 0xf801e3ff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01097f03, 0x01097f03, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x05070a3f, 0x05070a3f, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01260600, 0x01260600, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x0d000200, 0xf3000200, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x02010939, 0x02ff09c7, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x070a0101, 0xf90a0101, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x2c000100, 0x2c00ff00, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00010126, 0x00ffff26, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x01010172, 0xff01ff8e, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01550f01, 0x01550fff, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0f01003e, 0x0f01003e, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x1c010140, 0x1cff0140, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00113f05, 0x00ef3f05, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x01303619, 0xff303619, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00011c60, 0x00ff1c60, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x66010100, 0x66ffff00, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x1f00404b, 0x1f00c04b, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0310016e, 0x03f00192, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x2e310125, 0x2ecf01db, 0x00000000, 0x00000000 - dspck_dsio absq_s.qb, 0x0007007f, 0x00070080, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x30790a00, 0x30870a00, 0x00100000, 0x00100000 - dspck_dsio absq_s.qb, 0x00007806, 0x00007806, 0x00100000, 0x00100000 - - writemsg "[2] Test addu.ph" - dspck_dstio addu.ph, 0x7b52f3d9, 0x800ffffa, 0xfb43f3df, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xedb67ff9, 0x80000000, 0x6db67ff9, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x8000f7fc, 0x8000fff9, 0x0000f803, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x9a51405f, 0x9999007f, 0x00b83fe0, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xc71cb3bd, 0xc71cb6db, 0x0000fce2, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x371a7fe0, 0xffe08000, 0x373affe0, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x807fc96a, 0x80002fd1, 0x007f9999, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x01bbca9a, 0xfff0c007, 0x01cb0a93, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xdd03ff12, 0x00000005, 0xdd03ff0d, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x1e35ffff, 0x1c717fff, 0x01c48000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xff350ff8, 0xff35fffa, 0x00000ffe, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x3fc0fff0, 0x3fc07ff0, 0x00008000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xfb96fc96, 0xfbc8fc6f, 0xffce0027, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7fe07fff, 0x00000000, 0x7fe07fff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x800f82c5, 0x800f02c5, 0x00008000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xc0070000, 0xc0070000, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x8000781b, 0x7ffff81b, 0x00018000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x4977ffff, 0x4924fffe, 0x00530001, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xe02afffe, 0x000b7fff, 0xe01f7fff, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x1c61e392, 0xfff0e38e, 0x1c710004, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfffb8012, 0x7fff7fff, 0x7ffc0013, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xc003c002, 0x0000c001, 0xc0030001, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x0e377f19, 0x7fff7fff, 0x8e38ff1a, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xf8020006, 0xfc018003, 0xfc018003, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x1fe3fffe, 0x1fe07ffe, 0x00038000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfb5d007e, 0xdb6d807f, 0x1ff07fff, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xfffb000a, 0xfffb000a, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfac1ff80, 0x003f7f80, 0xfa828000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x00007ffd, 0x00000000, 0x00007ffd, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7ff2400e, 0xfff33ff8, 0x7fff0016, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x009efff2, 0x801f0001, 0x807ffff1, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xff040000, 0x107e0000, 0xee860000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xf003fffe, 0x00007fff, 0xf0037fff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x80007ff9, 0x7fff7fff, 0x0001fffa, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xb8e39fdf, 0x80007fff, 0x38e31fe0, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfffffff0, 0x80000000, 0x7ffffff0, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x803f0000, 0x00000000, 0x803f0000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x6ea58000, 0x00ef0000, 0x6db68000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xfffa8004, 0xfffa7fff, 0x00000005, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x4007ffe4, 0x8000ffe4, 0xc0070000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xbfefe453, 0x3ff0e3d7, 0x7fff007c, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x07187ffd, 0xf3e07fff, 0x1338fffe, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xff36fffd, 0x00007ffd, 0xff368000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xf7fdffff, 0xf001ffff, 0x07fc0000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xffe20f1d, 0xffe2000e, 0x00000f0f, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfffcfffe, 0x00007fff, 0xfffc7fff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7ffd83a0, 0x00007fff, 0x7ffd03a1, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x7ffe8000, 0x80000000, 0xfffe8000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x00fffffe, 0x00007fff, 0x00ff7fff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xbffb7fff, 0x7fff7fff, 0x3ffc0000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfff9400a, 0x0000c003, 0xfff98007, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x800300ee, 0x8003ffeb, 0x00000103, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7fa6fffd, 0xffa60002, 0x8000fffb, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x7fff19c1, 0x7fff19c1, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfff3ffff, 0x00017fff, 0xfff28000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xc00ffffe, 0x00007fff, 0xc00f7fff, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x09050000, 0x09050000, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x003b003f, 0x002f8000, 0x000c803f, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x80008000, 0x00000000, 0x80008000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x07fdffff, 0x07fc0000, 0x0001ffff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xffc13ffe, 0x00000000, 0xffc13ffe, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x7ff7524a, 0xfff89249, 0x7fffc001, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x7ff8ffff, 0xfff97fff, 0x7fff8000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xffc0ffe8, 0x00000000, 0xffc0ffe8, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x5cfcf0ff, 0x1ff0000f, 0x3d0cf0f0, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x800c79bf, 0x7fff8000, 0x000df9bf, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xfff303fc, 0x3ff00000, 0xc00303fc, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfb2eff54, 0x1b27ffc7, 0xe007ff8d, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xbffe7fff, 0x3ffe0000, 0x80007fff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x217d601f, 0x1fe0e01f, 0x019d8000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x80007ffe, 0x7fff8000, 0x0001fffe, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xbfbd8000, 0x3fc08000, 0x7ffd0000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x80000007, 0x80000007, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xffffffff, 0x80008000, 0x7fff7fff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x33330001, 0x33330002, 0x0000ffff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x03f77fff, 0xfff90000, 0x03fe7fff, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x1fa1c71c, 0x1fa10000, 0x0000c71c, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x80007ff7, 0x00007fff, 0x8000fff8, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x5552fff0, 0x55550000, 0xfffdfff0, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xfe5b8039, 0x044b8000, 0xfa100039, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x0000dfff, 0x0000e001, 0x0000fffe, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xff781062, 0x7f800ffe, 0x7ff80064, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x04fdfffe, 0x00ff7fff, 0x03fe7fff, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x0e3e835f, 0x8e388000, 0x8006035f, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xff803ffd, 0x7f803ffe, 0x8000ffff, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xfffc7ffd, 0x0001fffd, 0xfffb8000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x7f7e7fff, 0x7ffeffff, 0xff808000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xb8e38008, 0x80007fff, 0x38e30009, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x807f0084, 0x807f007f, 0x00000005, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x000500fa, 0x0000fffb, 0x000500ff, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xfffcc00f, 0x7fffc00f, 0x7ffd0000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x5fe03fb5, 0x1ff0ffb7, 0x3ff03ffe, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xfffafff9, 0xfffb8000, 0xffff7ff9, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x9026fc12, 0x807f0000, 0x0fa7fc12, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xa0080717, 0xc0070717, 0xe0010000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x7fe0f803, 0xffe0f801, 0x80000002, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x1ffcfff8, 0x1ffc7ff9, 0x00007fff, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xfe703fff, 0xffff3ffe, 0xfe710001, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x000f001f, 0x800f0000, 0x8000001f, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x4051fac5, 0x3ff8fd71, 0x0059fd54, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x7ff6ffc0, 0x7ff9ffc0, 0xfffd0000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x474280b4, 0xfe1e8000, 0x492400b4, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x0562089a, 0x0598ff63, 0xffca0937, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xf42c7fc1, 0x00007fc0, 0xf42c0001, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x8cc70602, 0x800007fe, 0x0cc7fe04, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x7ff07ffa, 0x7ff0fffa, 0x00008000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xd59400cc, 0x803f00ca, 0x55550002, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x80008e38, 0x80008e38, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x000d8000, 0x00020000, 0x000b8000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xff0e7dc5, 0xfffffdc6, 0xff0f7fff, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x7ffaff74, 0xfffbff81, 0x7ffffff3, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x7fffffd0, 0x7fffffd0, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x0000a00d, 0x0000800f, 0x00001ffe, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x92477ff8, 0xfffe7ff8, 0x92490000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x8ff8fffc, 0x0ffe0000, 0x7ffafffc, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x001e4924, 0x002c0000, 0xfff24924, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfffe001e, 0xffff000f, 0xffff000f, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7f7e0187, 0x7f800000, 0xfffe0187, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x0002400f, 0x0000c00f, 0x00028000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x003ffff8, 0x00008000, 0x003f7ff8, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xfff8807f, 0x00000000, 0xfff8807f, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7ffffff2, 0x00000000, 0x7ffffff2, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x0002e401, 0x0000e003, 0x000203fe, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xc924009d, 0x8000009c, 0x49240001, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfb3d8129, 0xfb380129, 0x00058000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xf1301fb3, 0x00d2ffd3, 0xf05e1fe0, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7ff57fbc, 0x80007f80, 0xfff5003c, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x06a880dd, 0x06a100de, 0x00077fff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xffdf38e6, 0x7fe00003, 0x7fff38e3, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x80008003, 0x80007fff, 0x00000004, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x8003fd4e, 0x0004fce2, 0x7fff006c, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x099e0ffd, 0x07fef001, 0x01a01ffc, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xc00f7fff, 0xc00f0000, 0x00007fff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x00077ff6, 0x0000fff6, 0x00078000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x3ff01082, 0x00000084, 0x3ff00ffe, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x00eb007e, 0x00ac807f, 0x003f7fff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xc9230041, 0x7fff803f, 0x49248002, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x8006d804, 0x8000e001, 0x0006f803, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x38e3fb2c, 0x38e30004, 0x0000fb28, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x0f0fc718, 0x0f0ffffc, 0x0000c71c, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xffff7ff7, 0x8000fff8, 0x7fff7fff, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x8097c01b, 0x00880014, 0x800fc007, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x1249004a, 0x92490000, 0x8000004a, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xfff90001, 0xfff87fff, 0x00018002, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x2842bfe0, 0xe8468000, 0x3ffc3fe0, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x1591bff8, 0xffeb8000, 0x15a63ff8, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x003e08b2, 0x7fff094d, 0x803fff65, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xd01d9c49, 0xc01f7fff, 0x0ffe1c4a, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xffe72810, 0xffe9ef2d, 0xfffe38e3, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x0000b8ea, 0x000038e3, 0x00008007, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x0f1e2ea6, 0x078f1753, 0x078f1753, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x80048000, 0x00000000, 0x80048000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x803ff003, 0x003f0000, 0x8000f003, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xff00db6b, 0xff00fffe, 0x0000db6d, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x80007ffe, 0x00007fff, 0x8000ffff, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x003ffcbc, 0x8000fcbf, 0x803ffffd, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x7fffe01f, 0x7fffe01f, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x00018000, 0x00018000, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x0001469d, 0x8000069f, 0x80013ffe, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x0002d959, 0x00009999, 0x00023fc0, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfffefffa, 0x7fff7fff, 0x7fff7ffb, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7f5eff70, 0x80000070, 0xff5eff00, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7fc0fcdb, 0x8000fc9f, 0xffc0003c, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xc0128000, 0xc00f0000, 0x00038000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x00320000, 0x00320000, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xeeb5f9dc, 0xeeb5f9dc, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xffe8ff35, 0xffe90000, 0xffffff35, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xfeff7fff, 0x0e7d7fff, 0xf0820000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x192cf0f0, 0x2b380000, 0xedf4f0f0, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x100cbc25, 0x0ffc3c25, 0x00108000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x00247ff0, 0x001f0000, 0x00057ff0, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xe666c91e, 0x66664924, 0x80007ffa, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x99997ffe, 0x00008000, 0x9999fffe, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x8002ffe6, 0x00010000, 0x8001ffe6, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xff4d006c, 0x00000000, 0xff4d006c, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x7fffffff, 0x00007fff, 0x7fff8000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x70f00000, 0xf0f0fffa, 0x80000006, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xffff1c71, 0x80001c71, 0x7fff0000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x00000051, 0x80000051, 0x80000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xf7fd800e, 0xf801000f, 0xfffc7fff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xffff0003, 0x7fff0000, 0x80000003, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x7ffdffff, 0x80007fff, 0xfffd8000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x0405ccdb, 0x0007cccc, 0x03fe000f, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x07ee8000, 0x00000000, 0x07ee8000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xfe7506d9, 0x000007fe, 0xfe75fedb, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x80068000, 0x80000000, 0x00068000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x7fa0f342, 0x3fc0f1c8, 0x3fe0017a, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x4fdc6000, 0x3fe0e001, 0x0ffc7fff, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x80000002, 0x80000002, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7ffc7fd0, 0x80007fe0, 0xfffcfff0, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xe86683ca, 0xc86803cb, 0x1ffe7fff, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xffffebf1, 0x8000f0b6, 0x7ffffb3b, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xffc0b6db, 0xffc0b6db, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x80003ffe, 0x00000000, 0x80003ffe, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x803f7fa5, 0x80008000, 0x003fffa5, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x27f67fe5, 0x07fe7fff, 0x1ff8ffe6, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x87fed555, 0x80005555, 0x07fe8000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x00000ffe, 0x00000000, 0x00000ffe, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7fa5c0f9, 0x7fffc003, 0xffa600f6, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xbff32062, 0x3ff01ff0, 0x80030072, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x00000060, 0x00000000, 0x00000060, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfedc0000, 0xff6e8000, 0xff6e8000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xd9ffffff, 0x03fe0000, 0xd601ffff, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x21398005, 0x168b8007, 0x0aaefffe, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x00010004, 0x00000004, 0x00010000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xc001ffff, 0xc0017fff, 0x00008000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xffff8007, 0x7fff8000, 0x80000007, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7ff00fbe, 0x00000fb7, 0x7ff00007, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x1ffcffc0, 0x00000000, 0x1ffcffc0, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0x803f0000, 0x803f8000, 0x00008000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xb0f171b8, 0xc00171c7, 0xf0f0fff1, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x0405801e, 0x00078000, 0x03fe001e, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x7fe47fff, 0xffe4ffff, 0x80008000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x8127fffd, 0x01270001, 0x8000fffc, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xffeea4fa, 0xfffe71c7, 0xfff03333, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x60020106, 0x7ffffffd, 0xe0030109, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xfffe7ffe, 0x7ffffffe, 0x7fff8000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xff368390, 0x00000390, 0xff368000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xb6db3ffd, 0x00003ffe, 0xb6dbffff, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xc01cfffe, 0xc01ffffd, 0xfffd0001, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x0f0f8000, 0x0f0f8000, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0x70c77e01, 0x71c77fff, 0xff00fe02, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x021b8000, 0x00000000, 0x021b8000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xe01ffb12, 0xe01fffff, 0x0000fb13, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xc9260138, 0x4924ffb6, 0x80020182, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x85c47fff, 0x7ff97fff, 0x05cb0000, 0x00000000, 0x00000000 - dspck_dstio addu.ph, 0xfaba2aae, 0xfab9aaaa, 0x00018004, 0x00100000, 0x00100000 - dspck_dstio addu.ph, 0xbf32807f, 0xc001007f, 0xff318000, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x00070006, 0x80070000, 0x80000006, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x8002e38b, 0x0003e38e, 0x7ffffffd, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0xffdf7fff, 0x7fe08000, 0x7fffffff, 0x00000000, 0x00100000 - dspck_dstio addu.ph, 0x04e4b8dd, 0xffc938e3, 0x051b7ffa, 0x00000000, 0x00100000 - - writemsg "[3] Test addu_s.ph" - dspck_dstio addu_s.ph, 0x8007804c, 0x80007fff, 0x0007004d, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffff8005, 0xf2d97fff, 0xffec0006, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x0000fe78, 0x00000d88, 0x0000f0f0, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffa001, 0xfffc8003, 0x07fe1ffe, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xfffafbb5, 0x8000febc, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffffffe, 0x7fff0000, 0x8000fffe, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0x3fc08000, 0xfff8807f, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x28695555, 0x00040000, 0x28655555, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x80f1a195, 0x00f207fc, 0x7fff9999, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffe801e, 0x7fff001f, 0x7fff7fff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x00017fff, 0x00017fff, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x8000807d, 0x7fff007f, 0x00017ffe, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffff007f, 0x80000000, 0x8e38007f, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffe68ff5, 0x00000ffc, 0xffe67ff9, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x84647fff, 0x04657fff, 0x7fff0000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffb9fef, 0xfff81ff0, 0x00037fff, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0xfff87fff, 0x7ffc8006, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfff87fff, 0xfff87fff, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x81eaffff, 0x7fffcccc, 0x01eb807f, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff0005, 0x7fff0005, 0xfffd0000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xbff81029, 0x3ff80031, 0x80000ff8, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffff0008, 0x80000004, 0x80000004, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xc0e4ffff, 0xc0078000, 0x00dd8000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x85e97fcf, 0x8000000f, 0x05e97fc0, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfff3f003, 0x0003f003, 0xfff00000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffffdd1, 0xfffc0000, 0x0007fdd1, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xa491e01b, 0x24921ffc, 0x7fffc01f, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xa0770025, 0x807f0000, 0x1ff80025, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x0008ff2d, 0x0008ff2d, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xfffffffe, 0x80007fff, 0x7fff7fff, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x0006000d, 0x00060007, 0x00000006, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xdcf3ffff, 0x1ce4f801, 0xc00fffff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x8000e03d, 0x00061ffe, 0x7ffac03f, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x2017b6db, 0x1fe00000, 0x0037b6db, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff738e, 0xfff101c7, 0x7fff71c7, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xfff5ffff, 0xfff2f80a, 0x00037fff, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff0014, 0xc71c0000, 0x7fff0014, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffaffff, 0x0000ff07, 0xfffa0e69, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xff67b332, 0xff673333, 0x00007fff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xe003ebdd, 0xf0e5fc3a, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xfc017fff, 0xfffd8000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x00010000, 0x00000000, 0x00010000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0xc0077fff, 0x8000ffbb, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfff00005, 0xfff00005, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x000fffff, 0x0000ff03, 0x000fffff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x0086ffff, 0x007ffebd, 0x0007aaaa, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xbffdf92c, 0x3ffe000c, 0x7ffff920, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xfff90004, 0x00000002, 0xfff90002, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x0015bffe, 0x00033ffe, 0x00128000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xbfbf80b1, 0x3fc000b2, 0x7fff7fff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x0000000f, 0x0000000f, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xfffffffe, 0x000f0000, 0xfff9fffe, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffeffff, 0x0000f889, 0xfffefffe, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x800df007, 0x8000f007, 0x000d0000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0xf001ffff, 0x80008000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x3ffef93e, 0x3ffef93e, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xff7fffff, 0x7f807fff, 0x7fffc01f, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xf50cfc94, 0xfec87f80, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x0000ffff, 0x00008000, 0x0000aaaa, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff8004, 0x7ffc0001, 0xffff8003, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x804307c7, 0x800007c7, 0x00430000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x8012ffff, 0x00127ff8, 0x8000c001, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff07fe, 0xfe1107fe, 0xff790000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x808d0ffe, 0x008d0002, 0x80000ffc, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff8062, 0xfffe8000, 0xfff90062, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0x8000f801, 0xffe97fff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x00420689, 0x00000000, 0x00420689, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xe003fffd, 0x7ffff003, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x7fff0004, 0x00000004, 0x7fff0000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0x7fffc007, 0x80007fff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x223fff18, 0x05ce0001, 0x1c71ff17, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x27eeffff, 0x1ff07fff, 0x07fedb6d, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x8000f977, 0x80000023, 0x0000f954, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffa492, 0x80008000, 0xffe72492, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x801cffff, 0x001cffff, 0x80000000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff7fff, 0x99990000, 0x92497fff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfff81d5c, 0xfff81d5c, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0xfffe8000, 0x000ffffe, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x0002fffe, 0x00020000, 0x0000fffe, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff8000, 0x80000000, 0xfff48000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xfc01ffff, 0x0000fff1, 0xfc01cd65, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x00210000, 0x001f0000, 0x00020000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xbfc0ffff, 0x3fc07fff, 0x80008000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffe08e, 0xffcee00f, 0x1ff0007f, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfff90000, 0x7ffa0000, 0x7fff0000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffeffff, 0xfffef95b, 0x00008000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0x7fffe007, 0xfff98000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffffffe, 0x7fff0000, 0x8006fffe, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffa0000, 0x7ffd0000, 0x7ffd0000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x6db7ffff, 0x6db60675, 0x0001f98d, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff07fc, 0x7fff0000, 0x800007fc, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0xfff9ff5c, 0x807f8000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0x07fcf001, 0xfffe8000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xff82ffff, 0xff827fff, 0x00008002, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfca6ffff, 0xfc01c01f, 0x00a5cab9, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xea55ffdf, 0x0ee80000, 0xdb6dffdf, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x83fe0dbb, 0x03fe0710, 0x800006ab, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0x8002c71c, 0xfff9ffff, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffc00f, 0xfffd0000, 0x00a0c00f, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff000c, 0xfffa0004, 0xff7a0008, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff8014, 0x80000014, 0xfffa8000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffc71c, 0xffff0000, 0x8000c71c, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x3fccffff, 0x3fc0801f, 0x000c8000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffd34c, 0xffff1c71, 0xfffab6db, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xff80ffff, 0x80001ce2, 0x7f80ffff, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff107d, 0x7fff0ffe, 0xff9a007f, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff0005, 0x80000000, 0xfa280005, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x8013cccd, 0x7fffcccc, 0x00140001, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffff80, 0x80000000, 0x8001ff80, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x8ff8f49f, 0x0ff8f499, 0x80000006, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xfc38ffff, 0x00007fff, 0xfc38ffec, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffe0, 0xaaaa8000, 0x80007fe0, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffeffff, 0x7ffffff9, 0x7fff8000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xfc56ff89, 0x003f0018, 0xfc17ff71, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x81407fc0, 0x80007fc0, 0x01400000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffff07fc, 0x800f0000, 0x800007fc, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xc0038003, 0x00000000, 0xc0038003, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0xf0037fff, 0xfffdfff9, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffffff3, 0xc03f0003, 0x6666fff0, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffffffe, 0x80007fff, 0xff547fff, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x04d88000, 0x00520000, 0x04868000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x78dfaaaa, 0x38e3aaaa, 0x3ffc0000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffff2f11, 0xffc62f11, 0xc00f0000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x0071ffff, 0x006af001, 0x00071c71, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0x80008000, 0x8000ffc0, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x555f0001, 0x55550001, 0x000a0000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x405d7fff, 0x3ffc7fff, 0x00610000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x00018000, 0x00018000, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xc007c01f, 0x7fffaaaa, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff0000, 0x80000000, 0x80000000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x80000000, 0x80000000, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff0ff8, 0xfffd0ff8, 0xffce0000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x0001f003, 0x0001f003, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x000500ff, 0x000500ff, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff0009, 0xfffd0009, 0xff410000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xe001fe20, 0xe001fe20, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xfffc7fff, 0x000d8000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff0014, 0x1ff80005, 0xfff9000f, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffcfff, 0x80070ffc, 0xfe29c003, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0x7fffffd1, 0x8000fcc2, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffffff9, 0xfffc7fff, 0x3fe07ffa, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xfffdf003, 0xfffec01f, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xf3ce8050, 0xaaaa7fff, 0x49240051, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x08198000, 0x00000000, 0x08198000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x8622ffff, 0x06228002, 0x8000f803, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x8007aab9, 0x0000000f, 0x8007aaaa, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x01b9f9cd, 0x0000f9be, 0x01b9000f, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xbfe0ff8c, 0x3fe000c2, 0x8000feca, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff3ff8, 0xffff3ff8, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x00ad0002, 0x007e0001, 0x002f0001, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffcd46, 0xf262cccc, 0x8000007a, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff800c, 0xfffd000d, 0x00a97fff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0x80008000, 0xff95f003, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x87fc0003, 0x07fc0003, 0x80000000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffff0004, 0x80000002, 0x80000002, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xdb6fffff, 0xdb6dfffb, 0x00027fff, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x3ffb8000, 0x00030000, 0x3ff88000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff87fe, 0x800007fe, 0x801f8000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff9156, 0x800f1156, 0x803f8000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x08020007, 0x00060007, 0x07fc0000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xe003f410, 0xe003f409, 0x00000007, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x800e9ffc, 0x7fff8000, 0x000f1ffc, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0xb6db7fff, 0xe01f8000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffa1ff0, 0xfffa1ff0, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0xffb67fff, 0xfff68001, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffe8002, 0xfffe7fff, 0x00000003, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x0099ffff, 0x00990004, 0x0000fffe, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffd1, 0xfff9ffd1, 0xff800000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x03adffff, 0x0003fffe, 0x03aa7fff, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xfffeb8e2, 0x7fff7fff, 0x7fff38e3, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x8004fffe, 0x80047fff, 0x00007fff, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xfff98e59, 0x00008e38, 0xfff90021, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xff068000, 0xff008000, 0x00060000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0x8000ff47, 0xfff4f001, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffdb6d, 0x9999db6d, 0x80000000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x8a67ffff, 0x0a68f003, 0x7fff1ff8, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x3b4a00de, 0x00000001, 0x3b4a00dd, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff1fe0, 0x11900000, 0xf8011fe0, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x80008000, 0x80008000, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x81e61555, 0x01e70005, 0x7fff1550, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x0ffd0000, 0x00050000, 0x0ff80000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xfffc001f, 0xfff3001e, 0x00090001, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x80000801, 0x000107fe, 0x7fff0003, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x4bd80002, 0x25ec0001, 0x25ec0001, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0xc00ff754, 0xfefb7fff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x00498ff6, 0x000a0ff8, 0x003f7ffe, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x0000f003, 0x00000000, 0x0000f003, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0x8000fff9, 0xffff800f, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x0000faa5, 0x0000faa5, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xe0078000, 0xf8497fff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff100d, 0xfff90015, 0x80000ff8, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xfffd8000, 0x8000fffc, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x001280f2, 0x00008000, 0x001200f2, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff02c4, 0x80000162, 0x80000162, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x0065ffff, 0x0065fff0, 0x0000ffd4, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xffc07fff, 0xfffaffff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x07ffffff, 0x0003ff92, 0x07fcfffa, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0x7ffff801, 0x80005555, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xfcf3ffff, 0xfcb4ef00, 0x003f8000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xfb0e0016, 0xf0010016, 0x0b0d0000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x000fffcf, 0x00000000, 0x000fffcf, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff00ef, 0xfeef00e8, 0x7ff80007, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x02f97fc0, 0x02f97fc0, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffff0025, 0xfffc0006, 0x0094001f, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xfffd7fff, 0x24928000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffff53, 0xff90ff48, 0x06c1000b, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x7fffbff8, 0x7fff8000, 0x00003ff8, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0x8000e003, 0x80008000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x7fffffff, 0x00007fff, 0x7ffff3b3, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff4001, 0xfffc3ffe, 0x7fff0003, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x8019ffff, 0x8000ffef, 0x0019f2cb, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x00007fff, 0x00000000, 0x00007fff, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x00008000, 0x00000000, 0x00008000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xfffcc71c, 0x9999fffa, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff800e, 0x71c7000f, 0xfe127fff, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x000dffff, 0x000d8000, 0x00007fff, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x3ffc001b, 0x3ffc001b, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0xffff8000, 0x0f0f8000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x7ff8ffff, 0x3ffcffc0, 0x3ffcffc0, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xff36fe6c, 0x8e387fc0, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0xc00fff4c, 0x80007ff9, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffc0, 0xff000000, 0xfffeffc0, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x8000ffff, 0x8000e74a, 0x0000f007, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x07fcffff, 0x0000ffb9, 0x07fcfffe, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x8000fe8a, 0x8000fe8a, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffffff, 0x7ffcf001, 0xffff8000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x80e783fe, 0x00c88000, 0x801f03fe, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffffbde1, 0xb6db0706, 0x8000b6db, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0x7ffe9999, 0xfffffff0, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff8000, 0x7ffb0000, 0xf1a08000, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0x81e5018e, 0x7ff000be, 0x01f500d0, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x8000fffe, 0x80007fff, 0x00007fff, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xffff7fff, 0xc01f7fff, 0xffd20000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0x3ffeffff, 0x3ffeff42, 0x00005555, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffb6dd, 0x7fff0002, 0x807fb6db, 0x00100000, 0x00100000 - dspck_dstio addu_s.ph, 0xe38e0054, 0x00000000, 0xe38e0054, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0xf0f0eaa6, 0x00003ffc, 0xf0f0aaaa, 0x00000000, 0x00000000 - dspck_dstio addu_s.ph, 0x8000ffff, 0x0000ffd0, 0x8000e001, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffff5555, 0xc00f5555, 0xc03f0000, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xffffffff, 0x7ffffffc, 0xdb6d807f, 0x00000000, 0x00100000 - dspck_dstio addu_s.ph, 0xea6821cc, 0x0a651ff0, 0xe00301dc, 0x00000000, 0x00000000 - - writemsg "[4] Test adduh.qb" - dspck_dstio adduh.qb, 0x8da5b67e, 0x1c7e6f00, 0xffccfefc, 0x0, 0x0 - dspck_dstio adduh.qb, 0x001f005b, 0x01000000, 0x003e00b6, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00b2386a, 0x006600c7, 0x00ff700e, 0x0, 0x0 - dspck_dstio adduh.qb, 0x3ebe7905, 0x7c7e000b, 0x00fff300, 0x0, 0x0 - dspck_dstio adduh.qb, 0xe766078e, 0xf00006ff, 0xdfcc091e, 0x0, 0x0 - dspck_dstio adduh.qb, 0x810e0182, 0x03000005, 0xff1d03ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x070257a4, 0x0f047f92, 0x000030b6, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0086aa55, 0x00e35501, 0x0029ffaa, 0x0, 0x0 - dspck_dstio adduh.qb, 0xa800279d, 0xff003cff, 0x5200123c, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f4702ad, 0xf90000db, 0x068e057f, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0f5c6034, 0x1eaa002a, 0x010ec03e, 0x0, 0x0 - dspck_dstio adduh.qb, 0xa16f8054, 0x83db0125, 0xc003ff83, 0x0, 0x0 - dspck_dstio adduh.qb, 0x8bff3738, 0xffff6600, 0x17ff0971, 0x0, 0x0 - dspck_dstio adduh.qb, 0x3638797f, 0x6d71c000, 0x000032ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f1f9d00, 0xff3f3c00, 0x0000ff00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x8a4c3700, 0x15996400, 0xff000a00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x8100000f, 0x03000002, 0xff00001d, 0x0, 0x0 - dspck_dstio adduh.qb, 0x680d79c1, 0xcf0302b6, 0x0218f1cc, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00004300, 0x00000000, 0x00008700, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f190a09, 0x00300f13, 0xff030600, 0x0, 0x0 - dspck_dstio adduh.qb, 0x6fff0c09, 0x83ff0305, 0x5cff160e, 0x0, 0x0 - dspck_dstio adduh.qb, 0x067f1d57, 0x0600033f, 0x06ff3870, 0x0, 0x0 - dspck_dstio adduh.qb, 0x8507bfd4, 0xef0f80aa, 0x1c00fffe, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7e03027f, 0xfd0705ff, 0x00000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0xd74ee096, 0xbf0ac366, 0xef92fdc7, 0x0, 0x0 - dspck_dstio adduh.qb, 0x479c8089, 0x003a8014, 0x8eff80ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x38088540, 0x66000c81, 0x0a11ff00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00bd22e3, 0x00ff01ff, 0x007c44c7, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7e997f42, 0x00330060, 0xfcffff24, 0x0, 0x0 - dspck_dstio adduh.qb, 0xff9907be, 0xffff0eff, 0xff33007e, 0x0, 0x0 - dspck_dstio adduh.qb, 0xef004f80, 0xdf001f01, 0xff0080ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x157e0049, 0x2afd0000, 0x00000092, 0x0, 0x0 - dspck_dstio adduh.qb, 0x21033b66, 0x03004400, 0x400633cc, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0b6ac342, 0x0f54ff05, 0x0781877f, 0x0, 0x0 - dspck_dstio adduh.qb, 0x4aed7e7a, 0x8fe3f778, 0x06f8067c, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f06807f, 0x000cff00, 0xff0001ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x83bbff01, 0x08f8ff02, 0xff7eff01, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7d387fb8, 0xf37000ff, 0x0700ff71, 0x0, 0x0 - dspck_dstio adduh.qb, 0x06030066, 0x040600cc, 0x09000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0c160400, 0x00030100, 0x18290800, 0x0, 0x0 - dspck_dstio adduh.qb, 0x12000c85, 0x23000e3e, 0x02010bcc, 0x0, 0x0 - dspck_dstio adduh.qb, 0x04aa0800, 0x04aa0800, 0x04aa0800, 0x0, 0x0 - dspck_dstio adduh.qb, 0x89fb0001, 0x92ff0103, 0x81f80000, 0x0, 0x0 - dspck_dstio adduh.qb, 0xa97f2212, 0xc1ff3800, 0x92000c24, 0x0, 0x0 - dspck_dstio adduh.qb, 0x051c7e02, 0x0038f704, 0x0b000600, 0x0, 0x0 - dspck_dstio adduh.qb, 0x91f30f06, 0xffe70001, 0x24ff1f0c, 0x0, 0x0 - dspck_dstio adduh.qb, 0x02f6118d, 0x02f1051b, 0x02fc1eff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x839d4462, 0x08ff71c3, 0xff3c1801, 0x0, 0x0 - dspck_dstio adduh.qb, 0x41c28381, 0x83c3fff3, 0x00c10710, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00034c4d, 0x0007920c, 0x0000078e, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0d037f7f, 0x0006ffff, 0x1a010000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x1f037418, 0x0000e130, 0x3e060700, 0x0, 0x0 - dspck_dstio adduh.qb, 0x2a77bc80, 0x55009902, 0x00efdfff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x003f9700, 0x007e3000, 0x0100ff00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x3dff010f, 0x4aff0300, 0x31ff001f, 0x0, 0x0 - dspck_dstio adduh.qb, 0x003c9988, 0x0079ffff, 0x00003411, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f86e102, 0x00ffc305, 0xff0eff00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x183f0303, 0x12010406, 0x1e7e0201, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0d210d07, 0x0c3f0000, 0x0e031b0f, 0x0, 0x0 - dspck_dstio adduh.qb, 0x006a1e3e, 0x010e3c01, 0x00c7017c, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0239b91f, 0x0005ff30, 0x046d730f, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f003382, 0x0001000c, 0xff0066f9, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7a87c1f8, 0xe7f1ffff, 0x0e1e83f1, 0x0, 0x0 - dspck_dstio adduh.qb, 0x147c7d40, 0x00002b01, 0x28f9cf80, 0x0, 0x0 - dspck_dstio adduh.qb, 0x20050701, 0x20050701, 0x20050701, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7a7ff77f, 0x0effffff, 0xe700f000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x16007f00, 0x1e00ff00, 0x0f000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f7f6f07, 0x00007f0f, 0xffff6000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x8387817f, 0x080fffff, 0xffff0300, 0x0, 0x0 - dspck_dstio adduh.qb, 0x693c077f, 0xbf780e00, 0x130001ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0xff5b207d, 0xff3e3ebf, 0xff78033c, 0x0, 0x0 - dspck_dstio adduh.qb, 0x1fb60071, 0x006d0000, 0x3eff00e3, 0x0, 0x0 - dspck_dstio adduh.qb, 0x4a8effa8, 0x921dffc3, 0x03ffff8e, 0x0, 0x0 - dspck_dstio adduh.qb, 0xcf017814, 0xcf017814, 0xcf017814, 0x0, 0x0 - dspck_dstio adduh.qb, 0xa3077007, 0x550f0100, 0xf100e00e, 0x0, 0x0 - dspck_dstio adduh.qb, 0xbe427c80, 0x7e810201, 0xff03f7ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x86510485, 0x0d9f00ff, 0xff04090c, 0x0, 0x0 - dspck_dstio adduh.qb, 0xb51c487f, 0xfe008eff, 0x6d380200, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0e007f07, 0x0000000e, 0x1d00ff00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0940007b, 0x00000000, 0x128000f7, 0x0, 0x0 - dspck_dstio adduh.qb, 0x19432c06, 0x0087290b, 0x32003002, 0x0, 0x0 - dspck_dstio adduh.qb, 0x77f7878f, 0xeff0ffff, 0x00ff0f1f, 0x0, 0x0 - dspck_dstio adduh.qb, 0x77435378, 0xef0087f1, 0x00871f00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x81fbf8e3, 0x03f7ffc7, 0xfffff1ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f007f00, 0x0000ff00, 0xff000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x83603318, 0xffc10b30, 0x07005c00, 0x0, 0x0 - dspck_dstio adduh.qb, 0xff3301f1, 0xff3301f1, 0xff3301f1, 0x0, 0x0 - dspck_dstio adduh.qb, 0x4c361bf9, 0x000034f9, 0x996d02f9, 0x0, 0x0 - dspck_dstio adduh.qb, 0x1f00885d, 0x3e01ff87, 0x00001233, 0x0, 0x0 - dspck_dstio adduh.qb, 0x6438ff91, 0x011cff24, 0xc755ffff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x108a367f, 0x001617ff, 0x21ff5500, 0x0, 0x0 - dspck_dstio adduh.qb, 0x817f4f09, 0xff000012, 0x04ff9f00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f0c9d83, 0x00183cff, 0xfe00ff07, 0x0, 0x0 - dspck_dstio adduh.qb, 0x024080c0, 0x008001ff, 0x0500ff81, 0x0, 0x0 - dspck_dstio adduh.qb, 0x857f4d7f, 0x0b0099ff, 0xffff0100, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7ff37f3a, 0x00e7ff04, 0xffff0071, 0x0, 0x0 - dspck_dstio adduh.qb, 0xb70c580b, 0x7019aa15, 0xff000601, 0x0, 0x0 - dspck_dstio adduh.qb, 0x04b18063, 0x06e02560, 0x0283db66, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0780498a, 0x0eff9216, 0x000100ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x03872a85, 0x000f3f0c, 0x07ff16ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0c60031e, 0x13c10600, 0x0600013c, 0x0, 0x0 - dspck_dstio adduh.qb, 0x000b0003, 0x00000000, 0x00170006, 0x0, 0x0 - dspck_dstio adduh.qb, 0x3b102a4f, 0x071e0000, 0x7002559f, 0x0, 0x0 - dspck_dstio adduh.qb, 0x37227020, 0x013a0000, 0x6d0be040, 0x0, 0x0 - dspck_dstio adduh.qb, 0x737fbba4, 0xe7ff78ff, 0x0000ff49, 0x0, 0x0 - dspck_dstio adduh.qb, 0x3cd5fc36, 0x00e3f907, 0x78c7ff66, 0x0, 0x0 - dspck_dstio adduh.qb, 0x1b7f80cc, 0x180001ff, 0x1effff99, 0x0, 0x0 - dspck_dstio adduh.qb, 0x01797f60, 0x00000000, 0x03f3ffc0, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f06cc81, 0x000cffff, 0xff019904, 0x0, 0x0 - dspck_dstio adduh.qb, 0x55183c52, 0x01307866, 0xaa01003e, 0x0, 0x0 - dspck_dstio adduh.qb, 0x8d748120, 0x1c2aff1c, 0xffbf0324, 0x0, 0x0 - dspck_dstio adduh.qb, 0x31018408, 0x34020a00, 0x2e01ff11, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7a483f55, 0x04357e00, 0xf05c00aa, 0x0, 0x0 - dspck_dstio adduh.qb, 0x73800660, 0xe7010dc1, 0x00ff0000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x80557f7f, 0x010000ff, 0xffaaff00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x1f7700ff, 0x000000ff, 0x3fef00ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x55afda00, 0x0c5fff00, 0x9fffb600, 0x0, 0x0 - dspck_dstio adduh.qb, 0x387f8200, 0x00ffff00, 0x71000600, 0x0, 0x0 - dspck_dstio adduh.qb, 0x03ff6381, 0x00ff0303, 0x07ffc3ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x05012a00, 0x0b025500, 0x00000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x117f810d, 0x14ef7f17, 0x0f0f8304, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0300d043, 0x0500f708, 0x0101aa7f, 0x0, 0x0 - dspck_dstio adduh.qb, 0x01603f00, 0x00000000, 0x03c17f00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7b00c300, 0x06008700, 0xf000ff00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0013077f, 0x00000dff, 0x00270100, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00470001, 0x008e0002, 0x00000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x2a00010f, 0x5500031e, 0x00000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0f085f21, 0x1f10bf43, 0x00000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00010574, 0x00020701, 0x010004e7, 0x0, 0x0 - dspck_dstio adduh.qb, 0x1f058063, 0x3f0aff00, 0x000101c7, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f710681, 0x00750703, 0xff6d05ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x66488000, 0x6081ff00, 0x6d0f0200, 0x0, 0x0 - dspck_dstio adduh.qb, 0xa0360e00, 0x423c1800, 0xff300400, 0x0, 0x0 - dspck_dstio adduh.qb, 0x417f420d, 0x7cff8017, 0x07000404, 0x0, 0x0 - dspck_dstio adduh.qb, 0x9a879f08, 0xf90fff10, 0x3cff4000, 0x0, 0x0 - dspck_dstio adduh.qb, 0xe1006600, 0xff00cc01, 0xc3000100, 0x0, 0x0 - dspck_dstio adduh.qb, 0x08ff837f, 0x01ffccff, 0x0fff3a00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0086ff01, 0x0015ff00, 0x00f8ff03, 0x0, 0x0 - dspck_dstio adduh.qb, 0x449ebf02, 0x01ffff00, 0x873e8004, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00ff38bb, 0x00ff71ff, 0x00ff0078, 0x0, 0x0 - dspck_dstio adduh.qb, 0x4c7f0603, 0x99000d07, 0x00ff0000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x782f9c02, 0xc1403a00, 0x301eff04, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00ed1200, 0x00e71200, 0x01f31301, 0x0, 0x0 - dspck_dstio adduh.qb, 0x478381bd, 0x00ffff7c, 0x8e0703ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x09857307, 0x00ff0b00, 0x120cdb0f, 0x0, 0x0 - dspck_dstio adduh.qb, 0x85032667, 0xff070c00, 0x0c0040cf, 0x0, 0x0 - dspck_dstio adduh.qb, 0x01051e49, 0x02003792, 0x000b0600, 0x0, 0x0 - dspck_dstio adduh.qb, 0xf39f157f, 0xf7df1d00, 0xef600eff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x12150019, 0x002b0020, 0x24000112, 0x0, 0x0 - dspck_dstio adduh.qb, 0x8118710b, 0x0400e300, 0xff300017, 0x0, 0x0 - dspck_dstio adduh.qb, 0x8bae4f14, 0xff607f20, 0x18fc2008, 0x0, 0x0 - dspck_dstio adduh.qb, 0x04ff0804, 0x02ff0200, 0x07ff0f08, 0x0, 0x0 - dspck_dstio adduh.qb, 0x057f7e82, 0x03fffd05, 0x070000ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00b8df16, 0x01ffff1e, 0x0071c00e, 0x0, 0x0 - dspck_dstio adduh.qb, 0xa88f008f, 0x713e0120, 0xe0e000ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0b053b7d, 0x160570f9, 0x00050601, 0x0, 0x0 - dspck_dstio adduh.qb, 0x02959a05, 0x0481ff0b, 0x00aa3500, 0x0, 0x0 - dspck_dstio adduh.qb, 0x159e0678, 0x1c3e0c09, 0x0fff00e7, 0x0, 0x0 - dspck_dstio adduh.qb, 0x667f0300, 0xccff0700, 0x00000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0015bb00, 0x002b7800, 0x0100ff00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x40141067, 0x802820cf, 0x00000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x85031f83, 0xff013e08, 0x0c0601ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x1439488d, 0x0703011c, 0x22708fff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x000f007f, 0x00000000, 0x011f00ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f06037f, 0x00000000, 0xff0c07ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x1c630d77, 0x00000000, 0x38c71bef, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0b5ea17e, 0x166943f7, 0x0053ff06, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0f100004, 0x05200009, 0x19010100, 0x0, 0x0 - dspck_dstio adduh.qb, 0xd3368f70, 0xc7051fe1, 0xdf67ff00, 0x0, 0x0 - dspck_dstio adduh.qb, 0xc700b608, 0xc700b608, 0xc700b608, 0x0, 0x0 - dspck_dstio adduh.qb, 0x48010506, 0x0201020d, 0x8e010800, 0x0, 0x0 - dspck_dstio adduh.qb, 0x017f0300, 0x00000000, 0x03ff0600, 0x0, 0x0 - dspck_dstio adduh.qb, 0x89800100, 0xf77f0100, 0x1c810100, 0x0, 0x0 - dspck_dstio adduh.qb, 0x051fda0b, 0x0a3eff08, 0x0000b60e, 0x0, 0x0 - dspck_dstio adduh.qb, 0x85102702, 0x0c1f4f04, 0xff020000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0602f1ff, 0x0001f1ff, 0x0d03f1ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x107f44be, 0x01ff057f, 0x200083fd, 0x0, 0x0 - dspck_dstio adduh.qb, 0x780006d8, 0x000000f1, 0xf0000cc0, 0x0, 0x0 - dspck_dstio adduh.qb, 0x07124444, 0x01000105, 0x0d248783, 0x0, 0x0 - dspck_dstio adduh.qb, 0x04005f08, 0x04000000, 0x0501bf11, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00007f0b, 0x0000ff07, 0x01010010, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0bba7338, 0x00ffdf01, 0x17750770, 0x0, 0x0 - dspck_dstio adduh.qb, 0x34ff4600, 0x49ff0d01, 0x20ff7f00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x443d1440, 0x7e0d2400, 0x0a6d0581, 0x0, 0x0 - dspck_dstio adduh.qb, 0x784a485b, 0x003d55b6, 0xf0573c01, 0x0, 0x0 - dspck_dstio adduh.qb, 0x38c3407f, 0x6d8780ff, 0x04ff0000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x1f0b6045, 0x3f00bf7f, 0x0016010c, 0x0, 0x0 - dspck_dstio adduh.qb, 0xdb2200fe, 0xf00700fd, 0xc73e00ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f010f30, 0xff000b60, 0x00021300, 0x0, 0x0 - dspck_dstio adduh.qb, 0x8f037f04, 0xff060009, 0x1f00ff00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0b7f0997, 0x00000b30, 0x16ff07ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f818800, 0xff248100, 0x00df8f00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x011a047e, 0x00290100, 0x020c07fd, 0x0, 0x0 - dspck_dstio adduh.qb, 0x034e8e81, 0x040e55ff, 0x028fc704, 0x0, 0x0 - dspck_dstio adduh.qb, 0x01000b03, 0x00000000, 0x02001607, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f181404, 0x00302808, 0xff000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00000604, 0x00010c09, 0x00000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0c9e23ff, 0x09ff3fff, 0x0f3e07ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00501a0c, 0x0099340b, 0x0008000e, 0x0, 0x0 - dspck_dstio adduh.qb, 0xcc9f1802, 0xffff0101, 0x993f3004, 0x0, 0x0 - dspck_dstio adduh.qb, 0xff9f057f, 0xff400aff, 0xffff0000, 0x0, 0x0 - dspck_dstio adduh.qb, 0xe1814707, 0xffff0105, 0xc3048e0a, 0x0, 0x0 - dspck_dstio adduh.qb, 0x88136d64, 0x6627001f, 0xaa00dbaa, 0x0, 0x0 - dspck_dstio adduh.qb, 0x46201976, 0x060100e0, 0x8740330c, 0x0, 0x0 - dspck_dstio adduh.qb, 0x9b1f034c, 0xff010015, 0x373e0783, 0x0, 0x0 - dspck_dstio adduh.qb, 0x03010aaf, 0x000007ff, 0x07030d60, 0x0, 0x0 - dspck_dstio adduh.qb, 0xff00780e, 0xff00780e, 0xff00780e, 0x0, 0x0 - dspck_dstio adduh.qb, 0x3c50f37f, 0x661ee700, 0x1283ffff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x6f06075b, 0x000804b6, 0xdf050a00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x18f8df71, 0x00ffff03, 0x31f1bfdf, 0x0, 0x0 - dspck_dstio adduh.qb, 0xb2ff3260, 0xffff4900, 0x66ff1cc1, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f01af10, 0xff03ff09, 0x00006018, 0x0, 0x0 - dspck_dstio adduh.qb, 0xf6803502, 0xfeff6a01, 0xef020003, 0x0, 0x0 - dspck_dstio adduh.qb, 0x803e1f20, 0x0101003f, 0xff7c3f01, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0903b67f, 0x0001ffff, 0x13056d00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x3219a481, 0x0000ff03, 0x653349ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x2600783e, 0x4d00f17c, 0x00000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x00aa7d03, 0x00fff902, 0x00550205, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0900ff73, 0x1100ff00, 0x0100ffe7, 0x0, 0x0 - dspck_dstio adduh.qb, 0x8bd883d4, 0xffc108fe, 0x18f0ffaa, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f887f05, 0xfff9030a, 0x0018fc00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x04804970, 0x00ff0002, 0x090192df, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0a006000, 0x0000c000, 0x15010100, 0x0, 0x0 - dspck_dstio adduh.qb, 0x477f067f, 0x00000000, 0x8eff0cff, 0x0, 0x0 - dspck_dstio adduh.qb, 0xbf8f7b7c, 0xff1ff700, 0x80ff00f9, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7222978a, 0x050dff55, 0xe03830c0, 0x0, 0x0 - dspck_dstio adduh.qb, 0x5838067f, 0x06000c00, 0xaa7000ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7e007f7f, 0xfd00ffff, 0x00000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0xff046e11, 0xff05db07, 0xff04011c, 0x0, 0x0 - dspck_dstio adduh.qb, 0x21a82b1c, 0x2d583e00, 0x15f91838, 0x0, 0x0 - dspck_dstio adduh.qb, 0x2ab61f00, 0x54ff3e00, 0x006d0000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x677f0051, 0xaaff009f, 0x24000003, 0x0, 0x0 - dspck_dstio adduh.qb, 0x82d24585, 0x06c16daa, 0xffe31e60, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0008407f, 0x001180ff, 0x00000000, 0x0, 0x0 - dspck_dstio adduh.qb, 0x099ec87f, 0x12409200, 0x00fdffff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f813301, 0xfeff4700, 0x00031f03, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0000f96d, 0x0000f96d, 0x0000f96d, 0x0, 0x0 - dspck_dstio adduh.qb, 0x10aa02ff, 0x205502ff, 0x00ff02ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x6d06127f, 0x1c002400, 0xbf0d00ff, 0x0, 0x0 - dspck_dstio adduh.qb, 0x81038b7e, 0x0305180b, 0xff01fff1, 0x0, 0x0 - dspck_dstio adduh.qb, 0x0600001d, 0x00000000, 0x0d00003b, 0x0, 0x0 - dspck_dstio adduh.qb, 0x31016600, 0x61010000, 0x0101cc00, 0x0, 0x0 - dspck_dstio adduh.qb, 0x7f5c7f05, 0x00b6ff00, 0xff03000b, 0x0, 0x0 - dspck_dstio adduh.qb, 0x000461cc, 0x00065599, 0x00036dff, 0x0, 0x0 - - writemsg "[5] Test adduh_r.qb" - dspck_dstio adduh_r.qb, 0x857e6272, 0x0a00c300, 0xfffc01e3, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x07ff1fd5, 0x0eff3daa, 0x00ff00ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0f4d4d94, 0x1c99998f, 0x01000099, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x80cc5601, 0xff990201, 0x00ffaa00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x72298019, 0xdf3f0013, 0x0412ff1f, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x80800727, 0x03ff0e3e, 0xfd00000f, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x24144b19, 0x3000872b, 0x18270e06, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xd7aaa680, 0xf7e17c00, 0xb673cfff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x4810c930, 0x80189206, 0x0f07ff5a, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x7744ff75, 0xcc00ff03, 0x2187ffe7, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8005f880, 0x0002f100, 0xff08ffff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x070202ff, 0x0e0003ff, 0x000300ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xcc9f8180, 0xffffffff, 0x993e0200, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0400c03f, 0x0400ff60, 0x0300801d, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x63119474, 0x1c1c99c3, 0xaa058f25, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x451304a4, 0x0c1201db, 0x7e14076d, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x198bf898, 0x0024f1ff, 0x32f1ff30, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x3f093000, 0x01100000, 0x7c016000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x06612ba4, 0x000155e7, 0x0cc00160, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xa43b624b, 0x49210330, 0xff55c066, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x048008ff, 0x000000ff, 0x07ff0fff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x4b9a8c00, 0x60341800, 0x36ffff00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x00098102, 0x000c8104, 0x00068000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x9e628534, 0x3cbf0a01, 0xff04ff66, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x03186066, 0x062fbfcc, 0x00000000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x38602c1a, 0x0ac00f33, 0x66004900, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0482bb10, 0x0007831f, 0x07fdf301, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x7fff0500, 0x7fff0500, 0x7fff0500, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x68ff3e82, 0xcfff7c04, 0x00ff00ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xb686cc0b, 0x6d0cff13, 0xffff9902, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x1fb81570, 0x3aff10c0, 0x03711a1f, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x72618a20, 0x08c1ff40, 0xdb001400, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8330bc72, 0x075f7863, 0xff00ff80, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x87ff2f80, 0x0fff3e01, 0xffff1fff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xe3ffa6ff, 0xffff4dff, 0xc7ffffff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x00ff0002, 0x00ff0000, 0x00ff0003, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x95110cb8, 0x2b000cff, 0xfe220c71, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0a0080c3, 0x0800ff87, 0x0c0000ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0380f79f, 0x00ffeffe, 0x0500ff40, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x4976e104, 0x00e3ff03, 0x9208c305, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x7d10312f, 0x01160208, 0xf9096055, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x1e800116, 0x00000000, 0x3cff012b, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x421a3f80, 0x00337eff, 0x83010000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8243a41f, 0x047f813e, 0xff07c700, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x01803971, 0x00000000, 0x01ff71e1, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x001ec707, 0x001ec707, 0x001ec707, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x3c101ef7, 0x781f39ff, 0x000003ef, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x3c1e8a80, 0x60033000, 0x1738e3ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x87118204, 0xff020401, 0x0f1fff06, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x20002055, 0x3f0040aa, 0x00000000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x04804a00, 0x017f0c00, 0x06808700, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x613e50f0, 0x007c00e0, 0xc1009fff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0800818e, 0x000003ff, 0x0f00ff1d, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x346a037a, 0x49cf05f3, 0x1e040001, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x808221d5, 0x000504ff, 0xffff3eaa, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x19ff0200, 0x19ff0200, 0x19ff0200, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xc909988d, 0x920e301b, 0xff03ffff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x81680256, 0x02cf023e, 0xff00016d, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x06b57b82, 0x00dbefc7, 0x0b8f073c, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x011a0000, 0x01330000, 0x00000000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x7f800478, 0xfdff07ef, 0x00000000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x41826201, 0x03040200, 0x7effc102, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x80710068, 0x00000000, 0xffe100cf, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xfff9ff00, 0xfff9ff00, 0xfff9ff00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x017a060b, 0x01700015, 0x01830c00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x70419937, 0xdf7c3200, 0x0006ff6d, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x39000280, 0x3e0002ff, 0x33000201, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x1a6e4780, 0x00000000, 0x33db8eff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0005184f, 0x00081099, 0x00011f04, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xff458097, 0xff0eaa31, 0xff7c55fd, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x6e087001, 0x0000df01, 0xdb100000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x060380c3, 0x05050187, 0x0601ffff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xff68ffa4, 0xff00ff49, 0xffcfffff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x6338f018, 0xaa0fe100, 0x1b60fe30, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x19000437, 0x00000000, 0x3200086d, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x02407d82, 0x0078f8ff, 0x04070205, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x20809700, 0x33ff2e00, 0x0d00ff00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x03808080, 0x00000000, 0x06ffffff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x06020001, 0x00040000, 0x0c000001, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x66025af9, 0xc70099ff, 0x04041bf3, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x10031f0d, 0x00000000, 0x1f063e19, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x01800f20, 0x00ff1c3e, 0x01000102, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x834a26fc, 0x0f9202ff, 0xf70149f8, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x7e228301, 0xc103ff00, 0x3b400702, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x38686cf8, 0x00cf3fff, 0x700099f0, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x9f500890, 0xff240e81, 0x3f7c019f, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x77ff0005, 0x07ff0009, 0xe7ff0000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8000ff01, 0xff00ff00, 0x0000ff02, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0c2e7c42, 0x00550017, 0x1707f76d, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x09820473, 0x0f0506df, 0x03ff0107, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x011a020f, 0x0000001c, 0x01330302, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xcc977a1b, 0xffc70333, 0x9966f003, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x032b7800, 0x0555f000, 0x00000000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x7a118001, 0xf11fff00, 0x03020002, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xdb110d14, 0xff1d1626, 0xb6040401, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x7e800700, 0xfc010000, 0x00ff0e00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x47309703, 0x00002e00, 0x8e60ff05, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xb9503808, 0xff9f700f, 0x72010000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xd38c7211, 0xef30e022, 0xb6e70400, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8480e004, 0x0800df00, 0xffffe108, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xa0803e80, 0x4fff0e00, 0xf0006dff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8b808013, 0x17ffff1e, 0xff000008, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x02808289, 0x0000ff12, 0x04ff05ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x081072f7, 0x1020e3ef, 0x000000ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x10362c04, 0x10220601, 0x10495206, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x4e2bff0e, 0x4e2bff0e, 0x4e2bff0e, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xff38921f, 0xff38921f, 0xff38921f, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0b02011a, 0x04030110, 0x12000024, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x067a92e7, 0x0cef24ff, 0x0004ffcf, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x07012102, 0x0c000403, 0x01013d00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x72804880, 0x030102ff, 0xe0ff8e00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0029713c, 0x0029713c, 0x0029713c, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x01012b39, 0x02010000, 0x00005571, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0e640000, 0x01000000, 0x1bc70000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x4d030084, 0x0a0000ff, 0x8f060009, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0b191de3, 0x000101c7, 0x163039ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x92ff6a00, 0x92ff6a00, 0x92ff6a00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x9e80ffff, 0xff00fffe, 0x3dffffff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x80146725, 0x00038f00, 0xff243e49, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x08098806, 0x10111000, 0x0000ff0c, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x99046100, 0x4007c100, 0xf1000000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x800e8002, 0xff0c0100, 0x0010ff03, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x4f7d0010, 0x1ecc001d, 0x7f2e0003, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x55803302, 0x1bff3804, 0x8e002d00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0e0cda80, 0x0018c300, 0x1c00f0ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x60e64808, 0x00ff0000, 0xc0cc8f10, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x80002103, 0x00003f06, 0xff000200, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xa2010026, 0x6801000f, 0xdb00003c, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0380ed18, 0x0000db0f, 0x06ffff21, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x14a53780, 0x00ff6dff, 0x274b0000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x579c0168, 0x0ff800cf, 0x9f3f0100, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x044e002d, 0x0599005a, 0x02020000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8b3f9f4d, 0x16183e12, 0xff66ff87, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x1f6e0300, 0x02db0000, 0x3c000500, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x4a838001, 0x14ff0000, 0x7f06ff01, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x000000ff, 0x000000ff, 0x000000ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x367a0d00, 0x00001300, 0x6cf30700, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xf6034518, 0xf9057000, 0xf3001a30, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8c037705, 0xff010d01, 0x1804e108, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x3810dc04, 0x6d01bf00, 0x021ef907, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0051bc02, 0x000f8700, 0x0092f003, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xb0065e80, 0x60002cff, 0xff0b8f00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0470a501, 0x04dfcc01, 0x04007e00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x20013008, 0x40016003, 0x0000000d, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x67010004, 0xc7000007, 0x07020000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x41868080, 0x71ff00ff, 0x110cff01, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x70931e50, 0x00ff009f, 0xe0263c01, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x2380020d, 0x46000413, 0x00ff0006, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x67080000, 0x01000000, 0xcc0f0000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x95824283, 0x2aff83e3, 0xff050122, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x039b037f, 0x02ff0500, 0x033701fd, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x68440005, 0xcc690007, 0x031f0002, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x01fb2bc3, 0x02fd00ff, 0x00f95587, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x3c500180, 0x71920100, 0x070e00ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x80000600, 0x00000000, 0xff000c00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x790380a1, 0xcc00ffc3, 0x2605017e, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xe4d92110, 0xf8b60300, 0xcffc3f1f, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0e07048e, 0x0e07048e, 0x0e07048e, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x46077c13, 0x83000025, 0x080ef700, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x7378a285, 0xdff08e0a, 0x0600b6ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0260ff17, 0x01bfff28, 0x0200ff05, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x86ff0001, 0xccff0000, 0x3fff0002, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0fde807f, 0x1ec3ffe0, 0x00f8001e, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x093c0c0a, 0x0f000c0f, 0x03780b05, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x31db780c, 0x00e7ef00, 0x61cf0018, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8af1b62b, 0x33ffff00, 0xe0e36d55, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xbf015202, 0xff008704, 0x7f011d00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xf5177e70, 0xf32a00cf, 0xf703fc10, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x00003705, 0x00006d0a, 0x00000000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x80fb071e, 0xffff0d3c, 0x00f70100, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x46101b3a, 0x1c013306, 0x701f026d, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x87802080, 0xff0300e7, 0x0ffc3f18, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x1020019f, 0x1e3200ff, 0x010d013e, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x80001852, 0xff000038, 0x0000306b, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x00841b83, 0x00083607, 0x00ff00ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x6e1a863e, 0x0003fc7c, 0xdb300f00, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x740efcbc, 0xe718f8f9, 0x0104ff7e, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x6ee08783, 0x0dcf0f06, 0xcff0ffff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x88f60c74, 0xfff00000, 0x10fc18e7, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0f9bffc3, 0x09ffff87, 0x1437ffff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x01cb8080, 0x02993900, 0x00fdc7ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8000822d, 0xff00ff01, 0x00000558, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x43760a2c, 0x81df0030, 0x050d1327, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x03191013, 0x05010020, 0x00301f05, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x3e810003, 0x7bff0000, 0x00030005, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x1800000f, 0x3000001e, 0x00000000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xfe80aab3, 0xfdff7166, 0xff00e3ff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x39ff1a9f, 0x01ff15b6, 0x70fe1e87, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xf307141e, 0xe70c0c05, 0xff011b37, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x80801a37, 0xff01106d, 0x00ff2400, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x01009488, 0x0000fd8f, 0x01002b81, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x711f025c, 0x020001b6, 0xdf3e0301, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x03789804, 0x03003003, 0x03efff04, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x6e000061, 0xdb0000c1, 0x00000000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x82ffb82e, 0x04ffff0a, 0xffff7051, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x288cff3b, 0x4918ff74, 0x06ffff02, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x00f7ff18, 0x00f7ff18, 0x00f7ff18, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x12550c04, 0x00000007, 0x23aa1800, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x1e3e0350, 0x007c049f, 0x3b000100, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0b54ab1b, 0x0e0fff30, 0x07995606, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x3987c706, 0x721c8e0a, 0x00f1ff01, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x80108b17, 0xff203624, 0x0000df09, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x60038016, 0xbf050008, 0x0001ff24, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xffff8301, 0xffffff00, 0xffff0701, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x2b060d80, 0x00000000, 0x550c1aff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x84ff003a, 0x08ff006d, 0xffff0006, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x450d0026, 0x450d0026, 0x450d0026, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x19018304, 0x3001ff07, 0x01000600, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x3f640980, 0x7cc70401, 0x02010eff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x80788084, 0x000000ff, 0xfff0ff08, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x47ff3880, 0x7fff00ff, 0x0eff7001, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x403b920a, 0x0249ff00, 0x7e2d2414, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x4881823b, 0x02030504, 0x8effff71, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x44648141, 0x0000027e, 0x87c7ff03, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x08842113, 0x0ccc041e, 0x033c3e07, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xbf6bc74c, 0x7ec08e18, 0xff16ff7f, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x0180010f, 0x00000000, 0x02ff011d, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x805b3c00, 0x00000000, 0xffb67800, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8d66480e, 0xff3e8f00, 0x1b8e001b, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x00ff8513, 0x00ff0a0b, 0x00ffff1a, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8080fffe, 0x0000fffd, 0xffffffff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0xfc860f34, 0xff0c1859, 0xf9ff060e, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x00000680, 0x00000bff, 0x00000000, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x80c3dba8, 0xff87b68f, 0x00ffffc0, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x10ff37c5, 0x1fff00f0, 0x00ff6d99, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x01017f1c, 0x0201fd30, 0x00010007, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x7100170f, 0xe100261d, 0x00000801, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x84800587, 0x090008ff, 0xffff010f, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x4d41ff93, 0x997eff26, 0x0103ffff, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8c7c0878, 0x18f70000, 0xff000fef, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x8148060e, 0xff8f0500, 0x0200071c, 0x0, 0x0 - dspck_dstio adduh_r.qb, 0x9f8c8005, 0xffffff09, 0x3e180000, 0x0, 0x0 - - writemsg "[6] Test append" - dspck_tsimm append, 0x00000090, 0x00000000, 0x079f2390, 8 - dspck_tsimm append, 0x00000001, 0x00000000, 0x008a1001, 1 - dspck_tsimm append, 0x09f0acd0, 0x09f0acd0, 0xf8000003, 0 - dspck_tsimm append, 0x80000019, 0x00000019, 0x00000019, 31 - dspck_tsimm append, 0xfffffff0, 0x00000003, 0x7ffffff0, 31 - dspck_tsimm append, 0x3b92e92e, 0x0073b92e, 0x0073b92e, 12 - dspck_tsimm append, 0x4000001f, 0x80000000, 0xc000001f, 31 - dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0x7fffffff, 0 - dspck_tsimm append, 0x40000001, 0x3ffffff0, 0xc0000001, 31 - dspck_tsimm append, 0xdff59020, 0xeffac810, 0x80000000, 1 - dspck_tsimm append, 0x0dbb0000, 0x00000dbb, 0x00000000, 16 - dspck_tsimm append, 0x000f0084, 0x0000000f, 0x00000084, 16 - dspck_tsimm append, 0x00000007, 0x00000000, 0xe0000007, 5 - dspck_tsimm append, 0x00000003, 0x80000000, 0x00003423, 3 - dspck_tsimm append, 0x00165235, 0x00165235, 0x00000007, 0 - dspck_tsimm append, 0xfdd29c98, 0xfdd29c98, 0xffffbef0, 0 - dspck_tsimm append, 0xff00ff00, 0xff00ff00, 0xfffd7cd8, 0 - dspck_tsimm append, 0xf8071c71, 0xff00ff00, 0x71c71c71, 19 - dspck_tsimm append, 0xfec36c54, 0xffd86d8a, 0xcccccccc, 3 - dspck_tsimm append, 0xffffdffe, 0x07fffffe, 0x07fffffe, 13 - dspck_tsimm append, 0xffffffec, 0xfffffffe, 0x3ffffffc, 4 - dspck_tsimm append, 0x80000000, 0x80000000, 0x7ffffff9, 0 - dspck_tsimm append, 0xfffffff0, 0xfffffff0, 0x3ffffffc, 0 - dspck_tsimm append, 0xffc3d805, 0xfffff87b, 0x00000005, 11 - dspck_tsimm append, 0x00000003, 0x80000000, 0xfffffffb, 2 - dspck_tsimm append, 0xffffffff, 0x7fffffff, 0x7fffffff, 31 - dspck_tsimm append, 0x80000000, 0xff36a999, 0x80000000, 31 - dspck_tsimm append, 0x80000000, 0x80000000, 0xf8000003, 0 - dspck_tsimm append, 0xe000000e, 0xfc000001, 0xb6db6db6, 3 - dspck_tsimm append, 0xffffffff, 0x7fffffff, 0x0000ffff, 1 - dspck_tsimm append, 0x00000006, 0xc0000001, 0x00000002, 2 - dspck_tsimm append, 0x000001bd, 0x00000000, 0x000001bd, 31 - dspck_tsimm append, 0xf8000001, 0xf8000001, 0x80000000, 0 - dspck_tsimm append, 0x07e0001b, 0x0000003f, 0x0000001b, 21 - dspck_tsimm append, 0x8ffffffe, 0x7fffffff, 0x0ffffffe, 31 - dspck_tsimm append, 0x0000006f, 0x0000006f, 0xffffff80, 0 - dspck_tsimm append, 0xffca4380, 0xffff290e, 0x7fffffc0, 6 - dspck_tsimm append, 0x00000000, 0x80000000, 0x80000000, 16 - dspck_tsimm append, 0x3ffffffd, 0x1ffffffe, 0x7fffffff, 1 - dspck_tsimm append, 0x00000005, 0x00000000, 0xfffffc5d, 3 - dspck_tsimm append, 0x8000001f, 0x8000001f, 0x00000000, 0 - dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0xfffffffc, 0 - dspck_tsimm append, 0x08f97af2, 0xffe09f08, 0xfff97af2, 24 - dspck_tsimm append, 0x00000000, 0x00000000, 0x80000000, 0 - dspck_tsimm append, 0x80000002, 0x80000002, 0xffffffe3, 0 - dspck_tsimm append, 0x000011f9, 0x0ffffffe, 0x000011f9, 31 - dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0xffdf9521, 0 - dspck_tsimm append, 0x0000002d, 0x80000000, 0xfff9cbad, 7 - dspck_tsimm append, 0x24924924, 0xb6db6db6, 0x24924924, 31 - dspck_tsimm append, 0xfe000001, 0x0000007f, 0x00000001, 25 - dspck_tsimm append, 0x7ffffff9, 0x00000000, 0xfffffff9, 31 - dspck_tsimm append, 0x80000000, 0x80000000, 0x71c71c71, 0 - dspck_tsimm append, 0xb6dbffff, 0x6db6db6d, 0x7fffffff, 17 - dspck_tsimm append, 0x000000b3, 0x80000000, 0x00f042b3, 8 - dspck_tsimm append, 0xb0000000, 0x0a72ad2b, 0x00000000, 28 - dspck_tsimm append, 0x00000000, 0x00000000, 0x3ffffff8, 3 - dspck_tsimm append, 0xc71c71c7, 0xc71c71c7, 0x007ec075, 0 - dspck_tsimm append, 0xfff3ff87, 0xfffffffc, 0xffffff87, 18 - dspck_tsimm append, 0x029129e0, 0x0052253c, 0x00000000, 3 - dspck_tsimm append, 0x7fffffc4, 0x0ffffff8, 0x0003a09c, 3 - dspck_tsimm append, 0xfffffe02, 0xffffff80, 0xffe06586, 2 - dspck_tsimm append, 0x80000006, 0x7fffffff, 0x80000006, 31 - dspck_tsimm append, 0x80000000, 0x80000000, 0x0000ffff, 0 - dspck_tsimm append, 0xf9820006, 0xfffff982, 0x80000006, 16 - dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0x7ffffffc, 0 - dspck_tsimm append, 0xfffffff9, 0x7fffffff, 0xfffffff9, 7 - dspck_tsimm append, 0x8000000f, 0x8000000f, 0x00000000, 0 - dspck_tsimm append, 0x00000000, 0x00000000, 0x80000000, 31 - dspck_tsimm append, 0x00000000, 0x80000000, 0x00000000, 31 - dspck_tsimm append, 0x92492492, 0x49249249, 0x00000000, 1 - dspck_tsimm append, 0xfffffffc, 0x7fffffff, 0x00000000, 2 - dspck_tsimm append, 0x80000000, 0x00ff00ff, 0x00000000, 31 - dspck_tsimm append, 0xfffffffc, 0x7fffffff, 0x0ffffffc, 28 - dspck_tsimm append, 0x0000198c, 0x00000006, 0x0000198c, 31 - dspck_tsimm append, 0x80000000, 0x80000000, 0x80000000, 0 - dspck_tsimm append, 0xe0c44a9f, 0xfc188953, 0x80000007, 3 - dspck_tsimm append, 0xffffffe7, 0xffffffe7, 0x0000001f, 0 - dspck_tsimm append, 0xfffe0000, 0x7fffffff, 0x80000000, 17 - dspck_tsimm append, 0x7ffffffc, 0x7ffffffc, 0x000b2d36, 0 - dspck_tsimm append, 0xe0000000, 0x80000007, 0x80000000, 29 - dspck_tsimm append, 0x8000003f, 0x8000003f, 0x00000000, 0 - dspck_tsimm append, 0x00f73453, 0xfffd9cce, 0x00f73453, 31 - dspck_tsimm append, 0x00000003, 0x00000000, 0xc0000003, 2 - dspck_tsimm append, 0xf0000001, 0xf0000001, 0x80000000, 0 - dspck_tsimm append, 0x0004000f, 0xf0000001, 0x8000000f, 18 - dspck_tsimm append, 0x00003800, 0x00000007, 0x00000000, 11 - dspck_tsimm append, 0x00000000, 0x00000000, 0x80000000, 0 - dspck_tsimm append, 0xbb4000ff, 0x001745da, 0x000000ff, 21 - dspck_tsimm append, 0x00000002, 0x00000001, 0x38e38e38, 1 - dspck_tsimm append, 0x7ffff89a, 0xfffffffa, 0xfffff89a, 31 - dspck_tsimm append, 0x00000000, 0x7fffff80, 0x00000000, 31 - dspck_tsimm append, 0x80000007, 0x80000007, 0x80000007, 0 - dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0xfffff895, 0 - dspck_tsimm append, 0xfbd4ecf0, 0xfef53b3c, 0x3ffffff8, 2 - dspck_tsimm append, 0xffe00000, 0xfffffff0, 0x80000000, 17 - dspck_tsimm append, 0x0000007f, 0x80000000, 0x7fffffff, 7 - dspck_tsimm append, 0x40000007, 0x80000000, 0xc0000007, 31 - dspck_tsimm append, 0x0000007a, 0xc000000f, 0x92492492, 3 - dspck_tsimm append, 0x0000000f, 0x00000007, 0x71c71c71, 1 - dspck_tsimm append, 0xfffffec4, 0xfffffec4, 0xfffffec4, 0 - dspck_tsimm append, 0x80000000, 0x80000000, 0xff6693b4, 0 - dspck_tsimm append, 0x0ffffff8, 0x80000000, 0x0ffffff8, 31 - dspck_tsimm append, 0xfffffffe, 0x7fffffff, 0xf320ad72, 1 - dspck_tsimm append, 0x0000000a, 0x00000000, 0x0000000a, 13 - dspck_tsimm append, 0xffffffff, 0x7fffffff, 0xffffffe5, 1 - dspck_tsimm append, 0xfffffe38, 0x7fffffff, 0x38e38e38, 9 - dspck_tsimm append, 0xfffffffe, 0x7fffffff, 0xfffffffe, 10 - dspck_tsimm append, 0x0000000e, 0x00000000, 0x8e38e38e, 7 - dspck_tsimm append, 0x001b738b, 0x00000db9, 0xfff9d38b, 9 - dspck_tsimm append, 0x24924924, 0xffd5e328, 0x24924924, 31 - dspck_tsimm append, 0x00037864, 0x00037864, 0xffff0000, 0 - dspck_tsimm append, 0xfd43c708, 0xff50f1c2, 0x80000000, 2 - dspck_tsimm append, 0x80000000, 0x80000000, 0x80000000, 0 - dspck_tsimm append, 0xfffffffe, 0x7fffffff, 0x80000000, 1 - dspck_tsimm append, 0x00180007, 0x00000006, 0x00000007, 18 - dspck_tsimm append, 0xffffff0c, 0xffffff0c, 0x7fffffff, 0 - dspck_tsimm append, 0xfffec000, 0xffffffec, 0x80000000, 12 - dspck_tsimm append, 0x0000003f, 0x80000003, 0x0000000f, 4 - dspck_tsimm append, 0xe46796e9, 0xff849723, 0x000796e9, 21 - dspck_tsimm append, 0xffffffff, 0x7fffffff, 0xc71c71c7, 2 - dspck_tsimm append, 0xfffffff0, 0xfffffff0, 0x80000006, 0 - dspck_tsimm append, 0x000007f8, 0x000000ff, 0x00000000, 3 - dspck_tsimm append, 0x05900000, 0xfffa4164, 0x00000000, 18 - dspck_tsimm append, 0x000003ff, 0x0000003f, 0x7fffffff, 4 - dspck_tsimm append, 0x78000001, 0x0004372e, 0xf8000001, 31 - dspck_tsimm append, 0xfefffffb, 0xfffffffb, 0xfffffffb, 22 - dspck_tsimm append, 0x020f6aac, 0x0000107b, 0x006feaac, 13 - dspck_tsimm append, 0x0000003c, 0x0000000f, 0x3fffffe0, 2 - dspck_tsimm append, 0xf50dfa1d, 0xfea1bf43, 0xfffffffd, 3 - dspck_tsimm append, 0xb512a800, 0xfff6a255, 0x00000000, 11 - dspck_tsimm append, 0x80023a3b, 0x0ad67261, 0x00023a3b, 31 - dspck_tsimm append, 0xf9999999, 0x0000001f, 0x99999999, 29 - dspck_tsimm append, 0x00026381, 0x000004c7, 0x00000001, 7 - dspck_tsimm append, 0x80000000, 0x00000007, 0x00000000, 31 - dspck_tsimm append, 0xffff7bfc, 0xffff7bfc, 0xffffd30b, 0 - dspck_tsimm append, 0x000005f8, 0x80000002, 0x3ffffff8, 9 - dspck_tsimm append, 0x7ffffffe, 0x00000000, 0xfffffffe, 31 - dspck_tsimm append, 0x029735d1, 0x029735d1, 0xffffe9b6, 0 - dspck_tsimm append, 0x80002246, 0xffffffff, 0x00002246, 31 - dspck_tsimm append, 0xfffffe7b, 0xfffffe7b, 0x00006e8f, 0 - dspck_tsimm append, 0x000009c8, 0x00000139, 0xff00ff00, 3 - dspck_tsimm append, 0xe0000007, 0x7ffffffb, 0xe0000007, 31 - dspck_tsimm append, 0xffffffff, 0x7fffffff, 0x00000017, 3 - dspck_tsimm append, 0x0000001f, 0x0000000f, 0x7fffffff, 1 - dspck_tsimm append, 0x000076aa, 0x00000000, 0xf03a76aa, 17 - dspck_tsimm append, 0xfffffff0, 0x7fffffff, 0x80000000, 4 - dspck_tsimm append, 0x0000003e, 0x00000007, 0xfb1e10f6, 3 - dspck_tsimm append, 0x0000ffff, 0x0000ffff, 0x92492492, 0 - dspck_tsimm append, 0x0000001f, 0x80000000, 0x0000001f, 31 - dspck_tsimm append, 0xffff81dc, 0xfffff03b, 0xffffc1bc, 3 - dspck_tsimm append, 0x00001e3d, 0x00000000, 0x00001e3d, 28 - dspck_tsimm append, 0xffb26ef1, 0xfff64dde, 0x00000001, 3 - dspck_tsimm append, 0x0ffffff8, 0x00000001, 0xfffffff8, 27 - dspck_tsimm append, 0x00001c46, 0x00000e23, 0x80000000, 1 - dspck_tsimm append, 0xfffe03fe, 0xffffff01, 0xfffffffe, 9 - dspck_tsimm append, 0x8410795a, 0x7fffffff, 0x0410795a, 31 - dspck_tsimm append, 0xffffc223, 0xffffff84, 0xffff81a3, 7 - dspck_tsimm append, 0x00000000, 0x00000000, 0xfbd3119d, 0 - dspck_tsimm append, 0x00000000, 0x00000000, 0xfff4148a, 1 - dspck_tsimm append, 0xffff8a84, 0xfffff150, 0xe468dc34, 3 - dspck_tsimm append, 0x00000000, 0x00000000, 0x00000000, 0 - dspck_tsimm append, 0x00003ffe, 0x80000000, 0xfffffffe, 14 - dspck_tsimm append, 0x00000000, 0x80000000, 0xfe261ae0, 3 - dspck_tsimm append, 0x0000003e, 0x0000003e, 0x0000006d, 0 - dspck_tsimm append, 0x00000000, 0x07fffffe, 0x80000000, 31 - dspck_tsimm append, 0x00e4fe00, 0x0001c9fc, 0x80000000, 7 - dspck_tsimm append, 0x7f00ff00, 0xff804b6c, 0xff00ff00, 31 - dspck_tsimm append, 0xfffff000, 0x7ffffffc, 0x80000000, 10 - dspck_tsimm append, 0x00000002, 0x00000001, 0x1ffffffe, 1 - dspck_tsimm append, 0xf072726f, 0x7fffffff, 0x0072726f, 28 - dspck_tsimm append, 0x80000002, 0x80000002, 0x7fffffff, 0 - dspck_tsimm append, 0x00013d29, 0x000027a5, 0xff4cd0b9, 3 - dspck_tsimm append, 0x20000000, 0x2b1945c4, 0x00000000, 27 - dspck_tsimm append, 0xfffff000, 0x7fffffff, 0x00000000, 12 - dspck_tsimm append, 0xf5b64a46, 0xf5b64a46, 0x8000001f, 0 - dspck_tsimm append, 0xe0000007, 0xe0000007, 0x80000000, 0 - dspck_tsimm append, 0x00000017, 0x80000001, 0x00009bc7, 4 - dspck_tsimm append, 0x0000003f, 0xf0000003, 0x7fffffff, 4 - dspck_tsimm append, 0x80000000, 0xf8000003, 0x00000000, 31 - dspck_tsimm append, 0xfffffb48, 0x7fffffff, 0xfffffb48, 31 - dspck_tsimm append, 0x00000004, 0x00000004, 0x80000000, 0 - dspck_tsimm append, 0xa5800000, 0x00007296, 0x80000000, 22 - dspck_tsimm append, 0xc71c401f, 0x71c71c71, 0x8000001f, 14 - dspck_tsimm append, 0x8000001f, 0x8000001f, 0x000000f2, 0 - dspck_tsimm append, 0x08dacc7f, 0x00a411b5, 0xffbe4c7f, 15 - dspck_tsimm append, 0x00003fe0, 0x000000ff, 0xffffffe0, 6 - dspck_tsimm append, 0x07305dfd, 0xffdc1cc1, 0x037a5dfd, 14 - dspck_tsimm append, 0xcccccccc, 0xcccccccc, 0x00066420, 0 - dspck_tsimm append, 0xfffffff6, 0x7ffffffb, 0x00000000, 1 - dspck_tsimm append, 0x00000007, 0x80000000, 0xf0000007, 3 - dspck_tsimm append, 0xff000001, 0x7fffffff, 0xf8000001, 24 - dspck_tsimm append, 0xffffffff, 0x7fffffff, 0x7fffffff, 28 - dspck_tsimm append, 0x8c7ffff9, 0xfffffa31, 0x7ffffff9, 22 - dspck_tsimm append, 0x8000003f, 0xffffffff, 0x8000003f, 31 - dspck_tsimm append, 0x0000000f, 0x0000000f, 0xffffffc0, 0 - dspck_tsimm append, 0xf0000003, 0xf0000003, 0x80000000, 0 - dspck_tsimm append, 0x00002b44, 0x80000000, 0x00042b44, 14 - dspck_tsimm append, 0x76680c00, 0xed1d9a03, 0x80000000, 10 - dspck_tsimm append, 0x000d3ca7, 0x000d3ca7, 0x7fffffff, 0 - dspck_tsimm append, 0xffffb15c, 0x7fffffff, 0x0029b15c, 15 - dspck_tsimm append, 0xfffffffb, 0x7fffffff, 0xff80a663, 3 - dspck_tsimm append, 0x000018b3, 0x00000c59, 0x000944f9, 1 - dspck_tsimm append, 0x80000000, 0x80000000, 0x80000000, 0 - dspck_tsimm append, 0xfffffa00, 0xfffffffd, 0x00000000, 9 - dspck_tsimm append, 0x38e38e38, 0x1c71c71c, 0xf0f0f0f0, 1 - dspck_tsimm append, 0x00000b58, 0x00000b58, 0xffe0425f, 0 - dspck_tsimm append, 0x0000001c, 0x00000007, 0x80000000, 2 - dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0x0545da72, 0 - dspck_tsimm append, 0x2bffffff, 0x001bef2b, 0x7fffffff, 24 - dspck_tsimm append, 0x000000c7, 0x00000000, 0xc71c71c7, 8 - dspck_tsimm append, 0xffff5ffe, 0xffffffd7, 0xfffffffe, 10 - dspck_tsimm append, 0xffffff80, 0xffffffe0, 0x00000000, 2 - dspck_tsimm append, 0xffffffcc, 0x0ffffffc, 0xfffceb9c, 4 - dspck_tsimm append, 0x036d1448, 0x00036d14, 0xffff2348, 8 - dspck_tsimm append, 0xcb0fffff, 0xffff5961, 0x7fffffff, 19 - dspck_tsimm append, 0x00000000, 0x00000000, 0x00000000, 0 - dspck_tsimm append, 0xfffffffe, 0x7fffffff, 0x80000000, 1 - dspck_tsimm append, 0xffffffff, 0xffffffff, 0x7fffffff, 1 - dspck_tsimm append, 0xfffffffd, 0x7fffffff, 0x00000225, 3 - dspck_tsimm append, 0xe0000000, 0x00ff00ff, 0x80000000, 29 - dspck_tsimm append, 0xfffffff7, 0xfffffff7, 0x71c71c71, 0 - dspck_tsimm append, 0xffc00002, 0xfffffffe, 0x80000002, 21 - dspck_tsimm append, 0x00000003, 0x00000000, 0x00000027, 2 - dspck_tsimm append, 0xfffffff8, 0x7fffffff, 0x0ffffff8, 9 - dspck_tsimm append, 0x51a45fff, 0x00328d22, 0x7fffffff, 13 - dspck_tsimm append, 0x00003f00, 0x00000000, 0xffffff00, 14 - dspck_tsimm append, 0x00000004, 0x00000004, 0x00000000, 0 - dspck_tsimm append, 0x7fffffff, 0x7fffffff, 0xfeec3b3a, 0 - dspck_tsimm append, 0x80000000, 0x80000000, 0xfc07f8c2, 0 - dspck_tsimm append, 0x8000006b, 0xfc000001, 0x0000006b, 31 - dspck_tsimm append, 0xffff9db6, 0x7fffffff, 0xffff9db6, 18 - dspck_tsimm append, 0x00000000, 0x00000000, 0xe38e38e3, 0 - dspck_tsimm append, 0xffffffff, 0x7fffffff, 0xffffffff, 14 - dspck_tsimm append, 0x05ec1bfc, 0x00017b06, 0x07fffffc, 10 - dspck_tsimm append, 0xff800000, 0xffffffe0, 0x80000000, 18 - dspck_tsimm append, 0xffffffff, 0x7fffffff, 0x7fffffff, 19 - dspck_tsimm append, 0x8f0f0f0f, 0x7fffffff, 0x0f0f0f0f, 31 - dspck_tsimm append, 0x38e38e39, 0x1c71c71c, 0xfffffffb, 1 - dspck_tsimm append, 0x1c71c71c, 0x1c71c71c, 0xffffc119, 0 - dspck_tsimm append, 0x00000004, 0x00000004, 0x80000000, 0 - dspck_tsimm append, 0x00000005, 0x80000000, 0x00000005, 27 - dspck_tsimm append, 0xfffffe00, 0xfffffffe, 0x00000000, 8 - - writemsg "[7] Test balign" - dspck_tsimm balign, 0x1f01fd01, 0x001f01fd, 0x015ca9c0, 1 - dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000000, 3 - dspck_tsimm balign, 0x710000f7, 0x71c71c71, 0x0000f73c, 3 - dspck_tsimm balign, 0x1b000000, 0x0000001b, 0x0000001b, 3 - dspck_tsimm balign, 0xf900248f, 0x7ffffff9, 0x00248f28, 3 - dspck_tsimm balign, 0x00003d00, 0x0000003d, 0x00000001, 1 - dspck_tsimm balign, 0xffff807f, 0x7fffff80, 0x7fffffff, 1 - dspck_tsimm balign, 0x4b000000, 0x0000004b, 0x00000000, 3 - dspck_tsimm balign, 0xffff8000, 0xffffff80, 0x002fdb08, 1 - dspck_tsimm balign, 0x0ab8dd00, 0x000ab8dd, 0x000064a2, 1 - dspck_tsimm balign, 0xffffffe2, 0x7fffffff, 0xe29d63ad, 1 - dspck_tsimm balign, 0xf803ffff, 0x3ffffff8, 0x03fffffe, 3 - dspck_tsimm balign, 0x3d800000, 0xfffe6a3d, 0x80000000, 3 - dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000000, 3 - dspck_tsimm balign, 0xffe96d00, 0xffffe96d, 0x00000000, 1 - dspck_tsimm balign, 0x000000c7, 0x80000000, 0xc71c71c7, 1 - dspck_tsimm balign, 0x3e8aac80, 0x003e8aac, 0x80000000, 1 - dspck_tsimm balign, 0x00000000, 0x80000000, 0x0000000f, 3 - dspck_tsimm balign, 0xfca3d07f, 0xfffca3d0, 0x7fffffff, 1 - dspck_tsimm balign, 0xffff8055, 0xffffff80, 0x55555555, 1 - dspck_tsimm balign, 0xffffffff, 0x7fffffff, 0xfffffff8, 1 - dspck_tsimm balign, 0x80ffffff, 0xffffff80, 0xffffff80, 3 - dspck_tsimm balign, 0x91000000, 0x0cf0c191, 0x00000000, 3 - dspck_tsimm balign, 0xffff5503, 0xffffff55, 0x0374dc74, 1 - dspck_tsimm balign, 0x000000c0, 0x80000000, 0xc0000001, 1 - dspck_tsimm balign, 0x0000087f, 0x00000008, 0x7fffffff, 1 - dspck_tsimm balign, 0xe7050500, 0xffe70505, 0x00000069, 1 - dspck_tsimm balign, 0x007fffff, 0x00000000, 0x7fffffff, 3 - dspck_tsimm balign, 0xffffe0ff, 0xffffffe0, 0xffffffe0, 1 - dspck_tsimm balign, 0xfffffe00, 0x3ffffffe, 0x00000000, 1 - dspck_tsimm balign, 0xffff80ff, 0xffffff80, 0xffe4aca7, 1 - dspck_tsimm balign, 0x01800000, 0x00000001, 0x80000005, 3 - dspck_tsimm balign, 0x0fffffff, 0x0000000f, 0xffffff39, 3 - dspck_tsimm balign, 0xd05dfc00, 0x1bd05dfc, 0x004e7d52, 1 - dspck_tsimm balign, 0xf8fffa05, 0x0ffffff8, 0xfffa0520, 3 - dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000000, 1 - dspck_tsimm balign, 0xffffeeff, 0xffffffee, 0xff7ccdf7, 1 - dspck_tsimm balign, 0x00000180, 0x80000001, 0x80000001, 1 - dspck_tsimm balign, 0xfc7fffff, 0x3ffffffc, 0x7fffffc0, 3 - dspck_tsimm balign, 0xc71c7100, 0x71c71c71, 0x00000000, 1 - dspck_tsimm balign, 0x555555ff, 0x55555555, 0xffff0000, 1 - dspck_tsimm balign, 0x33f80000, 0x02f67833, 0xf8000001, 3 - dspck_tsimm balign, 0x03029747, 0xf0000003, 0x029747e5, 3 - dspck_tsimm balign, 0x00516bff, 0x0000516b, 0xfffffd33, 1 - dspck_tsimm balign, 0xf86db6db, 0x7ffffff8, 0x6db6db6d, 3 - dspck_tsimm balign, 0xf87fffff, 0x0ffffff8, 0x7fffffff, 3 - dspck_tsimm balign, 0x107fffff, 0x00018c10, 0x7fffffff, 3 - dspck_tsimm balign, 0xf2a6e180, 0xfff2a6e1, 0x80000000, 1 - dspck_tsimm balign, 0x0000000f, 0x80000000, 0x0ffffffe, 1 - dspck_tsimm balign, 0x000000e0, 0x00000000, 0xe0000001, 1 - dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000000, 1 - dspck_tsimm balign, 0x5b00193c, 0xffff9e5b, 0x00193cb0, 3 - dspck_tsimm balign, 0x0000007f, 0x80000000, 0x7fffffff, 1 - dspck_tsimm balign, 0x0000070f, 0x80000007, 0x0ffffffc, 1 - dspck_tsimm balign, 0xff0f0f0f, 0x7fffffff, 0x0f0f0f0f, 3 - dspck_tsimm balign, 0xefc00000, 0xffffffef, 0xc0000001, 3 - dspck_tsimm balign, 0x00000c0f, 0x0000000c, 0x0ffffffc, 1 - dspck_tsimm balign, 0x05000000, 0x00000005, 0x00000001, 3 - dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000007, 1 - dspck_tsimm balign, 0x0effffff, 0xffff300e, 0xfffffffe, 3 - dspck_tsimm balign, 0x1fffeb60, 0x8000001f, 0xffeb607e, 3 - dspck_tsimm balign, 0x10bbe280, 0x0110bbe2, 0x80000004, 1 - dspck_tsimm balign, 0xffe25c1f, 0xffffe25c, 0x1ffffffc, 1 - dspck_tsimm balign, 0xffffffff, 0x00ff00ff, 0xfffffffb, 3 - dspck_tsimm balign, 0x00000000, 0x00000000, 0x00f2f43d, 1 - dspck_tsimm balign, 0xffb97400, 0xffffb974, 0x00000000, 1 - dspck_tsimm balign, 0xfffa5400, 0xfffffa54, 0x00000000, 1 - dspck_tsimm balign, 0x4d000543, 0x0005434d, 0x0005434d, 3 - dspck_tsimm balign, 0x00000080, 0x80000000, 0x80000000, 1 - dspck_tsimm balign, 0xfffe1fff, 0xfffffe1f, 0xfffffffe, 1 - dspck_tsimm balign, 0x000000aa, 0x80000000, 0xaaaaaaaa, 1 - dspck_tsimm balign, 0xfffff6c0, 0xfffffff6, 0xc000001f, 1 - dspck_tsimm balign, 0xffffff00, 0x7fffffff, 0x00000000, 1 - dspck_tsimm balign, 0xff800000, 0x7fffffff, 0x80000000, 3 - dspck_tsimm balign, 0x00800000, 0x80000000, 0x80000000, 3 - dspck_tsimm balign, 0xffffffff, 0x7fffffff, 0xffffff00, 3 - dspck_tsimm balign, 0x00000380, 0x80000003, 0x80000000, 1 - dspck_tsimm balign, 0xf08e38e3, 0x1ffffff0, 0x8e38e38e, 3 - dspck_tsimm balign, 0xfffff800, 0xfffffff8, 0x00005016, 1 - dspck_tsimm balign, 0xff000000, 0x7fffffff, 0x00000000, 3 - dspck_tsimm balign, 0x00000700, 0x00000007, 0x00002153, 1 - dspck_tsimm balign, 0xff800000, 0xffffffff, 0x80000000, 3 - dspck_tsimm balign, 0xffffff80, 0x7fffffff, 0x80000000, 1 - dspck_tsimm balign, 0xfe000000, 0x0ffffffe, 0x00000000, 3 - dspck_tsimm balign, 0xfffffde7, 0xfffffffd, 0xe75d405c, 1 - dspck_tsimm balign, 0xfd982d7f, 0xfffd982d, 0x7fffffff, 1 - dspck_tsimm balign, 0xff7fffff, 0x7fffffff, 0x7ffffffe, 3 - dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000002, 3 - dspck_tsimm balign, 0x5e7fffff, 0xff8bdc5e, 0x7fffffff, 3 - dspck_tsimm balign, 0xffffffff, 0x7fffffff, 0xffffffe6, 1 - dspck_tsimm balign, 0x00007f00, 0x8000007f, 0x00001059, 1 - dspck_tsimm balign, 0x0000007f, 0x00000000, 0x7fffffff, 1 - dspck_tsimm balign, 0x51800000, 0x32b3c151, 0x80000006, 3 - dspck_tsimm balign, 0x000000c0, 0x00000000, 0xc000001f, 1 - dspck_tsimm balign, 0x00fff286, 0x80000000, 0xfff2864d, 3 - dspck_tsimm balign, 0x00001ae4, 0x00000000, 0x001ae4b6, 3 - dspck_tsimm balign, 0x00000300, 0xf8000003, 0x00000000, 1 - dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000000, 1 - dspck_tsimm balign, 0x06f655e9, 0x80000006, 0xf655e94f, 3 - dspck_tsimm balign, 0xff000000, 0x7fffffff, 0x000000a9, 3 - dspck_tsimm balign, 0x00000780, 0xc0000007, 0x80000001, 1 - dspck_tsimm balign, 0x60ffffff, 0xffff8860, 0xffffffc8, 3 - dspck_tsimm balign, 0xfffffef8, 0xfffffffe, 0xf8000001, 1 - dspck_tsimm balign, 0x000000db, 0x00000000, 0xdb6db6db, 1 - dspck_tsimm balign, 0xfd800000, 0xfffffffd, 0x80000001, 3 - dspck_tsimm balign, 0xf1800000, 0x0002e7f1, 0x80000000, 3 - dspck_tsimm balign, 0x0d000002, 0x0000000d, 0x000002f2, 3 - dspck_tsimm balign, 0xffffffff, 0x7fffffff, 0xfffffffd, 1 - dspck_tsimm balign, 0x00000000, 0x00000000, 0x0000001c, 1 - dspck_tsimm balign, 0xfffffa00, 0xfffffffa, 0x00000000, 1 - dspck_tsimm balign, 0xffffffff, 0x7fffffff, 0xffffe59b, 1 - dspck_tsimm balign, 0x00ffffff, 0x00000000, 0xfffffff9, 3 - dspck_tsimm balign, 0xffffff7f, 0x7fffffff, 0x7fffffff, 1 - dspck_tsimm balign, 0xfffffff9, 0xffffffff, 0xfffff92d, 3 - dspck_tsimm balign, 0xaaaaaaff, 0xaaaaaaaa, 0xffffedc7, 1 - dspck_tsimm balign, 0xffffff7f, 0x7fffffff, 0x7ffffff9, 1 - dspck_tsimm balign, 0x800e0ff8, 0xffffff80, 0x0e0ff8b5, 3 - dspck_tsimm balign, 0xfff36500, 0xfffff365, 0x00000005, 1 - dspck_tsimm balign, 0x00000000, 0x00000000, 0x00000001, 1 - - writemsg "[8] Test cmpgdu.eq.qb" - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1ef101ff, 0x07270316, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x06cc0001, 0x24000102, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1f8fc0ff, 0x28001e24, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x03ff0001, 0x37ff0405, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0083ffdf, 0xfe000007, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x001000ff, 0x3fff0a12, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0xbfff0008, 0xc7000002, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x091c038e, 0x02600600, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff0801ff, 0xff00cc08, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x06ffc700, 0x0300830d, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x021f1e01, 0x3c000100, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0cff0a3e, 0xf73ee700, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1e00ff04, 0x00ff0fdf, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x01ff0106, 0x001d49ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x7f000000, 0x088100cc, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff3e3e01, 0xff010700, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x3800e3ff, 0x00000000, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x02fffe33, 0xf00b32ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xef1ff81e, 0x000e0f8e, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x04c02400, 0xff9f1355, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000009, 0x00000000, 0x0004ff00, 0x0, 0x09000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x00000000, 0x00021a3a, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x05000001, 0x0f0002f7, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x49aa3101, 0x00008fef, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x6bc30000, 0xf0ff01ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x13c10138, 0x3a380eff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x3c1f0000, 0xe000ff16, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x05efff26, 0xff001f03, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x0000000f, 0xff495500, 0xff495500, 0x0, 0x0f000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00e7ff2b, 0x4bff1eff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x33ffff78, 0x306d0018, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x17207c00, 0x021b006c, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0xff008003, 0x0200ff0f, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffe71605, 0xf30703ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x0e031e01, 0x3801aa01, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xfff939df, 0x2f001f00, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x70240080, 0x00000066, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x720aff00, 0x0033ff3f, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x21007219, 0x19ffff00, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x7f004508, 0x0000ff49, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x0000000f, 0x510000ff, 0x510000ff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff180000, 0xc0ffdf33, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x3e013603, 0x07ff4d3c, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x00f106ff, 0x9900ffff, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xffff0754, 0xff0117ff, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x0000000f, 0x1c0c0008, 0x1c0c0008, 0x0, 0x0f000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0808ccff, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff020012, 0x00f001ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x03ff0027, 0xf1014005, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xbf3312ff, 0x18ffff06, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00073004, 0x7eb60799, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x03feff00, 0x021cfcff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0xfeff0203, 0x00ff0409, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0xfdff7638, 0x000e0138, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x031effff, 0xc131077d, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x09c3c7ff, 0xdb000700, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x120c0055, 0x1133ff06, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x20ff0336, 0x0904403f, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1a007e00, 0x8301c0ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0b00ffc3, 0x00c018e3, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0000000e, 0xff05db6d, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xc3340000, 0x83ffff01, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x01e10078, 0x090caa0e, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0xff01ef00, 0x00000000, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x3bdf081e, 0x658eff71, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x0000000f, 0x0020dfff, 0x0020dfff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00ff0cb6, 0xf801db00, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00381a66, 0x01017501, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x01006600, 0x2d0006ff, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x00000000, 0x663300ff, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x001e00e7, 0x01064905, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0b26ffc0, 0x51160001, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x252f0300, 0x26004f0e, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00000000, 0x830a4a03, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x7b2b0200, 0x07aa0600, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x070000ff, 0xfff900f9, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff706dff, 0x24ff01df, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x3c050071, 0x10003eff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x703f0018, 0xe0003500, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff0ff803, 0x0b008335, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffff08aa, 0x063003f0, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0xef008e10, 0x00000000, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x09ff0000, 0x003f11ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x00000033, 0x04020000, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x05000114, 0x55ff070c, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff3d3870, 0xff007840, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x8055ff6d, 0x0cff38f3, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x00010024, 0x007999ff, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0200ff01, 0x7d380002, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0a062702, 0x00650bff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0xf9160002, 0xff8700ff, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x00000000, 0x1f293800, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x13000700, 0x01ffaa3d, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0101ff14, 0x00497102, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff7066ff, 0xc100db24, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x6a787000, 0x00247c6f, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x210000ff, 0x01ff1e1c, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x06ff7703, 0xff00f90e, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x27fc39ff, 0x00053e00, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffff3023, 0x65009f30, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xc78e0ccf, 0x003048ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0xe7920000, 0x00007f00, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff1ae1f8, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0049ff87, 0x01ff8f00, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00ff3855, 0xc30619ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x0400ffff, 0x0000030e, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x02300100, 0xfffddb00, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x0000000f, 0xfc000eff, 0xfc000eff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x2605032f, 0xff3381ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00ff11f9, 0xaa0e01ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1fff0a01, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x2a000201, 0x49ff0600, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0007ff3c, 0xffe70107, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00000000, 0x7c0c18db, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xc71d01ff, 0x00004900, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x8700e71f, 0x2500f739, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x83060570, 0xf9ff2002, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff003c00, 0xffffff02, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x2d09ffff, 0x020006ff, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00380c1c, 0x3800f9ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x000f04e3, 0x7f11382f, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x001eff00, 0xcc01ff04, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00107f00, 0x7f01048f, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x00000000, 0x00ffdbff, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0e30c107, 0x03ff1200, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0xc157ff00, 0x1c08ff03, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x4100ff00, 0x0804c070, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x01ff03ff, 0x00f800c0, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x00000a3d, 0x0c0000cc, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x60ff3801, 0xff0099e7, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x000500fc, 0x0100133c, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00b60113, 0x1eff0400, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0xff06ffff, 0x01ffff02, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x26000500, 0xffc3ff03, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00183e01, 0xff1ef0ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff00ffff, 0xff05251a, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x300000ff, 0x00000e04, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x001ec700, 0xff0303e7, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x000a16ff, 0x01001fff, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff550703, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x55010602, 0x1a208787, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x00ff02ff, 0xff026dff, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000005, 0x3effffff, 0x0eff20ff, 0x0, 0x05000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x49fd0004, 0xcf00fe66, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00064000, 0xf920ffff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0000fff9, 0xff1f00ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x008700ff, 0x00ff4000, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00ff87e0, 0x0e00ffff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x04ff0900, 0x3192ff06, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00000b06, 0xffff0104, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00ff1800, 0x8ec3f3f8, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xc18155e7, 0x0007130c, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0f1e0f08, 0xff3e0700, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x00ff8706, 0xb6ffffff, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x00000000, 0x2401ff00, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x010a0c18, 0x1c010000, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0b00f110, 0x320304aa, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x03ff0000, 0x13ffffc1, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1203fffd, 0x002e0180, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff0130e7, 0x01c0fff1, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x60001f1d, 0xfd04ff01, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0xe7093f00, 0x00000000, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x01df0c18, 0x00f9feff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x000060df, 0x0008ff00, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x80ff0400, 0x002403c7, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xe71e1f00, 0x02ff1cff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x8f9260ff, 0x9200c302, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x0000000f, 0x55117cff, 0x55117cff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffff01ff, 0x012c0078, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffe30702, 0x0c000083, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0371c092, 0xffe08f60, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00000000, 0x38ff0301, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xff017c03, 0x8edf02ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff000000, 0xffb60c92, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x8100ff38, 0xff8f4aff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x000340ff, 0x02002002, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x00000000, 0x008f1c01, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x33183b51, 0x0a0afecc, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000005, 0x00000000, 0x06003000, 0x0, 0x05000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffff6020, 0x0008570f, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x6f71ffff, 0xffcf00ff, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x40aa3000, 0xff009202, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x8e03fee7, 0x132d0001, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0c71109f, 0xc0f9ffff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x0103009f, 0x01021f00, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0e0ac7c7, 0x06fd0bfe, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x000aff66, 0x040002c0, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xffff01ff, 0x1109fd00, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x013a1c0f, 0x04010003, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x0009f1ff, 0x0000783e, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xf81e01ff, 0x0001837f, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0xffff0160, 0xaafffffc, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x001eff1f, 0x9f0a0301, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0xf9ffffc7, 0x00ff0200, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff030092, 0xffff0133, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1b00001e, 0x6f07ff14, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x3c000fff, 0x00ff0201, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1ff03f60, 0x01b6fe00, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x03062003, 0x87df80ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0a240104, 0x33010242, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x3200039f, 0x00ff0003, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0xcf00ff00, 0x0006ff03, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1f044401, 0x00008f2c, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0301ff03, 0x7c0001ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x8307c100, 0x00000000, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x0300e7ff, 0x52004902, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x1f0f07c7, 0xff010100, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000009, 0x00ff0000, 0x0000ff00, 0x0, 0x09000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xf806c1ff, 0xffff06df, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x66383f0a, 0xaa07ff03, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x60db1e0a, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000004, 0x01000cff, 0x00000000, 0x0, 0x04000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x002b71c0, 0xcf12ff0a, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x68098102, 0xfc788e00, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x24543c00, 0x7fbfff01, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x01ff8ff7, 0x24000033, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0101b670, 0xdf02ff05, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x60050000, 0xff040001, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0xff1f0c00, 0xff02ff06, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xf9fff834, 0xdf06c102, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000006, 0xc1000301, 0x4200030a, 0x0, 0x06000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x00ff0200, 0x601c001f, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000009, 0x003e04ff, 0x001800ff, 0x0, 0x09000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0aff1a00, 0x3ec0000d, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000009, 0x0137fc71, 0x0102ff71, 0x0, 0x09000000 - dspck_dstio cmpgdu.eq.qb, 0x00000008, 0x0055000e, 0x00e3dbff, 0x0, 0x08000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0xe7e0ff1f, 0xff050701, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x813400ff, 0x666a0d01, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x1b73ffc0, 0x002dff78, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x251f0340, 0x2300ffff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x02ff3f00, 0x0001ff1d, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x0002ff80, 0xf88300ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x01092400, 0x3e07cf00, 0x0, 0x01000000 - dspck_dstio cmpgdu.eq.qb, 0x00000002, 0x050aff00, 0xff7cffff, 0x0, 0x02000000 - dspck_dstio cmpgdu.eq.qb, 0x00000000, 0x2b00ffff, 0x020178fc, 0x0, 0x00000000 - dspck_dstio cmpgdu.eq.qb, 0x00000001, 0x02ff8f00, 0x00c70300, 0x0, 0x01000000 - - writemsg "[9] Test cmpgdu.lt.qb" - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff0000ff, 0x3a0cffff, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x1b0c03f8, 0x178f2d0d, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x0a02ff7f, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000e, 0x18003cff, 0xff0b7e00, 0x0, 0x0e000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x03300018, 0x0200df06, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xdfdbe7ff, 0x00ffffbf, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0xfd026046, 0xff1e1a07, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x00ffff0d, 0x1dffe300, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x00009f00, 0xff002b06, 0x0, 0x09000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x0201007f, 0x8e007f10, 0x0, 0x0a000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x3666c1aa, 0xff060000, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000d, 0x00001a02, 0xffff006d, 0x0, 0x0d000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xb6df10e3, 0xb6df10e3, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000e, 0x0e1e027c, 0xef492d00, 0x0, 0x0e000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x03ff031c, 0x00010001, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x03ffff6c, 0x1604df00, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xf8fc02fd, 0x00240030, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000007, 0x0f000300, 0x00030f18, 0x0, 0x07000000 - dspck_dstio cmpgdu.lt.qb, 0x00000001, 0xf1ffff06, 0x9200f114, 0x0, 0x01000000 - dspck_dstio cmpgdu.lt.qb, 0x00000007, 0xff310800, 0x005cff0c, 0x0, 0x07000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff0008ff, 0x0107c70b, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff71003e, 0xff71003e, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xffff0000, 0x1f00ffc3, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x0e0108ff, 0x00ff051c, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x6d01ffe1, 0x0bff017f, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x038e02ff, 0x038e02ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000e, 0x180c1dff, 0xf31ec1ff, 0x0, 0x0e000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xffff0209, 0x0000ff8f, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x01390035, 0x000eff01, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x00ff06ff, 0x30030cff, 0x0, 0x0a000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x022c496d, 0xff0bf3ff, 0x0, 0x0b000000 - dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x0d00e701, 0x061a0b2a, 0x0, 0x05000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x0000ff18, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x009f010e, 0x33070100, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000007, 0xf1ef0001, 0x03ff0105, 0x0, 0x07000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x2c0e138e, 0x00f70000, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x1e077e18, 0x0500010b, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x00ff0310, 0x3f0300ff, 0x0, 0x09000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x00ffff76, 0x001ff303, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000001, 0xff0aff0e, 0x030000ff, 0x0, 0x01000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x1e0002ff, 0x12cf3802, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x018000fd, 0x018000fd, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x0fffaa01, 0xf1383981, 0x0, 0x09000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xffef0003, 0x0700ff40, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff02c167, 0x04cfff01, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x79030300, 0x00e10106, 0x0, 0x05000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x000104ff, 0xffff0110, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000d, 0x0d0100cc, 0x0fff00df, 0x0, 0x0d000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x0004ff3d, 0x0466ff03, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x78002c07, 0x2400f9f3, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xff4000ff, 0x008100fe, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x81c1014b, 0x1038c0ff, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x020254ff, 0xffff0eff, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x0210ffcf, 0x00ff8019, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x7100ff80, 0x01db557c, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000007, 0x3b17095e, 0x00db41b6, 0x0, 0x07000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x40440500, 0x05016d00, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff0000ff, 0x010201fe, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x07000000, 0x00004000, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x00000000, 0x09f06699, 0x0, 0x0f000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x60090b04, 0xffff1011, 0x0, 0x0f000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x10cf00ff, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xf8040024, 0xf8040024, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xffc0e7e3, 0x7c000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x0721f104, 0x0501ff64, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x55100000, 0x000f1a03, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x20fff90f, 0x01aacc0a, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x2603aa00, 0x0718aa00, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xaa87f13c, 0x0003f003, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x02ff0d0e, 0x000c20c3, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xbf012492, 0xbf012492, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xffff02fe, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x030001f7, 0x00ff1d02, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xe326bfdf, 0x00f1010c, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x0300ff00, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xc3090081, 0x000392ff, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xc30200ff, 0xc30200ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x1e101603, 0x02f90103, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x16ffff8e, 0x307eff00, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x870100ff, 0x3f000e00, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x00000000, 0x001b00e3, 0x0, 0x05000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x1e01ff24, 0xc3ff0000, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000e, 0x00070040, 0x7f130227, 0x0, 0x0e000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x00004902, 0x01f90400, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x00000eff, 0x02002408, 0x0, 0x0a000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0xf0f800ff, 0x01080c70, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x01ff4700, 0x44003c00, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x06f93fff, 0xff6d00ff, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x0f030007, 0x00003449, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xf91d3c00, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x00036d02, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x03200078, 0x02780002, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x0206ff92, 0x0206ff92, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000e, 0x1f000000, 0x2ef83500, 0x0, 0x0e000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x30010b16, 0x00021800, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x66074600, 0xf06dff02, 0x0, 0x0f000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x6ef1ff60, 0x00707102, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff001b7c, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x20fe3200, 0x00497c8f, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000007, 0xff371000, 0x383cff04, 0x0, 0x07000000 - dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x8380f038, 0x00ff03ff, 0x0, 0x05000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x13000132, 0x13000132, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x0300c30f, 0x00b683fc, 0x0, 0x05000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x28007000, 0xdf8effff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000d, 0x00057e08, 0x07db011e, 0x0, 0x0d000000 - dspck_dstio cmpgdu.lt.qb, 0x00000005, 0xff030e02, 0xffc30caa, 0x0, 0x05000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x7e0000aa, 0x0000ff01, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x00ff00ff, 0xcf1b0001, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000001, 0xff8e000b, 0x060c00fc, 0x0, 0x01000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x590f00ff, 0xff0000e0, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x00004000, 0x7a003c00, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x020f01ff, 0x7c0aff01, 0x0, 0x0a000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x1d000040, 0x001fff00, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000d, 0x37000110, 0xaae1003e, 0x0, 0x0d000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000d, 0x001d00cc, 0xc7ff00ff, 0x0, 0x0d000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x0e1d12ff, 0x3c620100, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x87ff0080, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x3300df87, 0x00df8300, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x200431ff, 0xef240580, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff0002bf, 0xff027e33, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xf9db08ff, 0xcf030519, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x38001849, 0xff360000, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000007, 0xb6007300, 0x0007f709, 0x0, 0x07000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x01ff0000, 0xffaaf300, 0x0, 0x0a000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xffbfffb6, 0xffbfffb6, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x00ff01b6, 0x00ff01b6, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x0001e101, 0x01ff0000, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x013e3038, 0x02003300, 0x0, 0x0a000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x00ff01e1, 0x0100ff00, 0x0, 0x0a000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff240080, 0xff00006a, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xccffff0a, 0xccffff0a, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x3f0078ff, 0x0f171b10, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xff010740, 0xffff0004, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff7dffff, 0x00001c19, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x0307ff07, 0xff789f00, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x01e04900, 0x06023800, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xc7020066, 0x0c0034ff, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xfffc003c, 0x1f0010ff, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x80000107, 0xff240000, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x80f9343f, 0x80f9343f, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x006001fe, 0x0000027e, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x01ff0499, 0x36ff0200, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0xe1fd3070, 0x0100ff01, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x0fe3ccff, 0x1faacfaa, 0x0, 0x0a000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x6f03e31a, 0xffff0800, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x0703f9ff, 0x00e7ff30, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000001, 0x00ffff0f, 0x0000c0ff, 0x0, 0x01000000 - dspck_dstio cmpgdu.lt.qb, 0x00000001, 0x7cc7fe55, 0x070000ff, 0x0, 0x01000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0xcfff0302, 0xff013c09, 0x0, 0x0b000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x07000039, 0xff020002, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x330adbff, 0xff001501, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000e, 0x3c2800ff, 0xcc3b151e, 0x0, 0x0e000000 - dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x0380ff00, 0xbf000024, 0x0, 0x09000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x9f700001, 0xff075520, 0x0, 0x0b000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xffff78e0, 0x04000183, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x0100063f, 0xc3001e00, 0x0, 0x0a000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x00ff0502, 0xff08e1f8, 0x0, 0x0b000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x3e380300, 0x24030f03, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x7f1f0010, 0x01071800, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x00000007, 0x30000100, 0x01ffffff, 0x0, 0x07000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x00010201, 0x0d00ff83, 0x0, 0x0b000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xf901c783, 0x92030500, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xaa03f080, 0x0d000800, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0xff0037f3, 0xff00fe7f, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x00010c03, 0x01006500, 0x0, 0x0a000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xffff3800, 0xff00ff01, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x012b0460, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000007, 0x08000bf9, 0x010b16ff, 0x0, 0x07000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff0070ff, 0x00000071, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x077100ff, 0xff8100f9, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x2bff0000, 0x023f0401, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0xfffe0003, 0x15000100, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff1607ff, 0xff1607ff, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x100b0b03, 0x01ff6600, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x05007f01, 0x00ff04f0, 0x0, 0x05000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x008f0200, 0x190c3ef8, 0x0, 0x0b000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xff0060ff, 0x00ff0400, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xe008ff38, 0x00ffff00, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x0f000000, 0x03001578, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x5901f9ff, 0x00ff028e, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000d, 0x00000000, 0xffff00ff, 0x0, 0x0d000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x0001339f, 0x00f11e07, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0xff0038f0, 0x08000004, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x031006c0, 0xe0ff6dff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x8e00001c, 0x03010d02, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0xcfb63103, 0xf9ffff92, 0x0, 0x0f000000 - dspck_dstio cmpgdu.lt.qb, 0x00000001, 0xff99ef01, 0xc37b0713, 0x0, 0x01000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x00700e08, 0xffff3887, 0x0, 0x0f000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0xf80c0002, 0x0f009902, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff3c050e, 0x38ffff03, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000005, 0xff00b600, 0xff7c3299, 0x0, 0x05000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x0000002e, 0x080013ff, 0x0, 0x0b000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xff24dfff, 0xffff36ff, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x1b000c00, 0x1a83f900, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x02ffff1b, 0xffff010e, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x03fe0206, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x0000711d, 0x0000711d, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x01000f00, 0xffff4081, 0x0, 0x0f000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xff80fdff, 0x9fff0887, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x008efff8, 0xf981033f, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0xff722fff, 0x0178008f, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x00000000, 0x07000000, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x00100626, 0x01e11830, 0x0, 0x0f000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x00e00708, 0x00007e00, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x00000000, 0x00003813, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x0333dbf9, 0x0333dbf9, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000f, 0x00000000, 0x24830e06, 0x0, 0x0f000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0x170106cf, 0x047fff1e, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xff0a0002, 0x3b00ff2c, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x3c83fff9, 0x02fcc1ff, 0x0, 0x05000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x71dbff30, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000001, 0xff13ff0d, 0x400400b6, 0x0, 0x01000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x01ff0200, 0xff00e72d, 0x0, 0x0b000000 - dspck_dstio cmpgdu.lt.qb, 0x00000002, 0x01ff0155, 0x01000240, 0x0, 0x02000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x00cf0100, 0x24000408, 0x0, 0x0b000000 - dspck_dstio cmpgdu.lt.qb, 0x00000001, 0x00001800, 0x00000004, 0x0, 0x01000000 - dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x011effe3, 0x11001eff, 0x0, 0x09000000 - dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x00ff0a00, 0xff00007c, 0x0, 0x09000000 - dspck_dstio cmpgdu.lt.qb, 0x00000001, 0x338fff66, 0x0004f983, 0x0, 0x01000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff870010, 0x00f03800, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x70019200, 0x00006000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x00000001, 0xcf01ff36, 0x0001ffff, 0x0, 0x01000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000b, 0x003e8700, 0x1800ffff, 0x0, 0x0b000000 - dspck_dstio cmpgdu.lt.qb, 0x00000004, 0x220102ff, 0x012c0040, 0x0, 0x04000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x034402e7, 0x7100c303, 0x0, 0x0a000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0x000f3017, 0x00015555, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x0700ff07, 0x03ffe1ff, 0x0, 0x05000000 - dspck_dstio cmpgdu.lt.qb, 0x00000009, 0xe1002678, 0xff0008ff, 0x0, 0x09000000 - dspck_dstio cmpgdu.lt.qb, 0x00000008, 0x0106ffe3, 0x0d0007c3, 0x0, 0x08000000 - dspck_dstio cmpgdu.lt.qb, 0x00000003, 0xffdb07aa, 0x0e03c7c0, 0x0, 0x03000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x2f01081e, 0xe0020100, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000006, 0xff33006d, 0x8f38ff20, 0x0, 0x06000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000a, 0x00090010, 0x1a008004, 0x0, 0x0a000000 - dspck_dstio cmpgdu.lt.qb, 0x00000000, 0x003a7f18, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.lt.qb, 0x0000000c, 0x031affff, 0xffff03ff, 0x0, 0x0c000000 - dspck_dstio cmpgdu.lt.qb, 0x00000005, 0x7805001f, 0x065600f3, 0x0, 0x05000000 - dspck_dstio cmpgdu.lt.qb, 0x00000009, 0x0049ff99, 0xf80e00f8, 0x0, 0x09000000 - - writemsg "[10] Test cmpgdu.le.qb" - dspck_dstio cmpgdu.le.qb, 0x00000003, 0xe0870000, 0x3718fd30, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0xff001e7e, 0xef7cc338, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x000200aa, 0xc100ffff, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x0218ff01, 0xdfc13c00, 0x0, 0x0c000000 - dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0008f8ff, 0x003f00ff, 0x0, 0x0d000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x007e0828, 0x002c7f3c, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x29071000, 0x6d3c0102, 0x0, 0x0d000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0x8f1fffc0, 0x0000c301, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0xff780000, 0x00fff01e, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x0c1c00ff, 0xff339200, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x00005640, 0xff3e0d0b, 0x0, 0x0c000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00ffff02, 0x00ffff02, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0000cc38, 0xff0000ff, 0x0, 0x0d000000 - dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x7800b6ff, 0xffff9902, 0x0, 0x0c000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x200b01e0, 0xffff0700, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0x2003ff31, 0x18008f1e, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x0520c001, 0x3e01df06, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x19004600, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000004, 0xffff0cff, 0x8fff0501, 0x0, 0x04000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0xfffffd3e, 0x0023cc53, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x00000009, 0x4c7e6300, 0x601b0000, 0x0, 0x09000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0xfffe007f, 0x00000000, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0xff2017ef, 0x92000703, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0x2cc05a55, 0x17000306, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0xff011ae7, 0x0000ff01, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x00000009, 0x8302780e, 0xff010e7f, 0x0, 0x09000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0x08060007, 0x021755ff, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0x92040001, 0x00f1ff00, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0x7f800000, 0x07007ecf, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x380000ef, 0xffff10df, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x183e001f, 0x32060200, 0x0, 0x0a000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0x01cf0883, 0x0030006d, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0x3f3a1200, 0x0c000024, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x1400e000, 0xfe0c00aa, 0x0, 0x0d000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0xff0002ff, 0x00fc3ee1, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x8708c300, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0x64ff0308, 0x1eff34ff, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x00ff0002, 0xfff9df00, 0x0, 0x0a000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0x7c07300c, 0x0bffff55, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0x780e0f00, 0x0305ff00, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x0300c0ff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x100f003c, 0x100f003c, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000004, 0x3c00ff38, 0x10020806, 0x0, 0x04000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0x01ff9f1b, 0x00330401, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0x0b1c1c00, 0x030200ff, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x00000009, 0x000d0c80, 0x170102ff, 0x0, 0x09000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0xffff000e, 0x0505f86d, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x067f49aa, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x000100fc, 0x1f26024f, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x0000000d, 0xcf00ff00, 0xfffd00ff, 0x0, 0x0d000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x55033600, 0xff07f900, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0x007899ff, 0xfd003500, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x039900ff, 0x10f70400, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0x7c200007, 0x00830036, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x001eff05, 0x3affff00, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0xff3e0309, 0x0000f301, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0xf7000042, 0xdfff0692, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0x1c78ffff, 0x000029ff, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x00000005, 0x0100ffb6, 0x00000eff, 0x0, 0x05000000 - dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x000e0c83, 0x0706c004, 0x0, 0x0a000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x037e0100, 0x78f30e00, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x01007101, 0x03380715, 0x0, 0x0d000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0xc1ffff03, 0x0018008f, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0xf8ff0600, 0xffbf81ff, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0xfce0600e, 0xbf7e408e, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0xc0db5f3f, 0x0003ff3f, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0x81ffe718, 0x33c7006b, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0x35ff0006, 0x03010e10, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x1c07e0ff, 0x83ffe31f, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0x14518308, 0xff0c3f02, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0xff2e0000, 0x8e0224ff, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0xff2c00f9, 0x6aff0e7e, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0x04000370, 0x01ff800e, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0xefe10700, 0x3e024b99, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0x3c02e018, 0x0070f300, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x00000004, 0xff00c03a, 0x00050f01, 0x0, 0x04000000 - dspck_dstio cmpgdu.le.qb, 0x0000000c, 0xff00fff8, 0xff000309, 0x0, 0x0c000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0x0036ff01, 0x66055f00, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0xffff010e, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00ff0700, 0x02ffffff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xe0ff1400, 0xe0ff1400, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000005, 0x9f48870f, 0x00ff08ff, 0x0, 0x05000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x008e0137, 0x01014978, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0xff000003, 0x7f0f803f, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0xc30200ff, 0x00000000, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x03ff3001, 0xff008e9f, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0x83000d00, 0x550c2900, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x0000000a, 0xffff0473, 0xff06c324, 0x0, 0x0a000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0xb6f13eff, 0x01030805, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x380000f7, 0xe7ff0351, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0x380030b6, 0x050087ff, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0x02ccffff, 0xff130000, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0x0700023f, 0x00008762, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x00017e3f, 0x00ff0600, 0x0, 0x0c000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0xfccf01ff, 0x717187ff, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x00000009, 0x65ff0f00, 0xff080004, 0x0, 0x09000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0xf3808f17, 0x00000000, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0xb667ff07, 0x001ce7db, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x010f6dff, 0x010f6dff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xff000000, 0xff000000, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000005, 0x2302ff00, 0x011100e0, 0x0, 0x05000000 - dspck_dstio cmpgdu.le.qb, 0x00000005, 0x06000100, 0x0000008e, 0x0, 0x05000000 - dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x01ff03ff, 0x05119238, 0x0, 0x0a000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x00ff0000, 0x178700ff, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x00000009, 0x00df8110, 0x000d0078, 0x0, 0x09000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x60c3c305, 0x60c3c305, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x0022f940, 0x8703ff00, 0x0, 0x0a000000 - dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0230f324, 0x1881f17c, 0x0, 0x0d000000 - dspck_dstio cmpgdu.le.qb, 0x00000005, 0x20002c00, 0x008300ff, 0x0, 0x05000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0xcc4900ff, 0x086d1e00, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0x83ff001f, 0x3800021e, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xffff0000, 0xffff1100, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x01200216, 0x01200216, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0x1e241e92, 0x000005ff, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x0000e306, 0x3333fff3, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0xfe0307ff, 0xff000003, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x00ff04ff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x07030e00, 0xc724ff00, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0001170f, 0x7e2a0099, 0x0, 0x0d000000 - dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0000ff33, 0x023f81aa, 0x0, 0x0d000000 - dspck_dstio cmpgdu.le.qb, 0x00000005, 0x0800ff00, 0x04cc8eff, 0x0, 0x05000000 - dspck_dstio cmpgdu.le.qb, 0x00000005, 0xf1067800, 0x00f13d07, 0x0, 0x05000000 - dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0300ff00, 0xffaa6d40, 0x0, 0x0d000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0xf9000628, 0x051c0803, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x046c9f00, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x8f1c17ef, 0xb6ffff19, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0x0660df18, 0x0002ff00, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000202, 0xf0ff1602, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xff043e00, 0xff043e00, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0x04010110, 0x000000ff, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x00000009, 0x28aab600, 0xff02001b, 0x0, 0x09000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x38380501, 0xff0171ff, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0xff200ce1, 0x0010ff71, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0xff1b012d, 0x1e04ffe0, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x00000009, 0x1010240c, 0xff001f18, 0x0, 0x09000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0x4cffff15, 0x060049ff, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0xffff2639, 0x0000fef1, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x05000087, 0x0a1e00c3, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000009, 0x00f1201e, 0x08f000ff, 0x0, 0x09000000 - dspck_dstio cmpgdu.le.qb, 0x00000004, 0xe000ff0b, 0x0087db00, 0x0, 0x04000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xf9000002, 0xf9000002, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0xf8ffff00, 0x923f2df7, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x01ff1700, 0x0140ff00, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x92007edf, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0xffff0000, 0x008eef00, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x00000009, 0x012c1f00, 0x34180000, 0x0, 0x09000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0xf312ff06, 0x2300cfff, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0xff6e007f, 0x00000000, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x07000000, 0xff00021b, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x03032401, 0x03032401, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00240006, 0x30ff1cff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x7f0034ff, 0xff05ff03, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0x920d6e78, 0xfd000b60, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x009f0102, 0x3efe08ff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x0000b6ff, 0x00fc3403, 0x0, 0x0c000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x7b180000, 0x87efc303, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000004, 0xff00031c, 0x01180000, 0x0, 0x04000000 - dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x008f001c, 0x660b6c00, 0x0, 0x0a000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0x1f9900ff, 0x00010507, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x000300ff, 0x000e0300, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0x02479266, 0x18000007, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0x1537c3e1, 0x000c0100, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0x7e060200, 0x171b0b00, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0xff00026d, 0xeff935ff, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x0000013e, 0x180316ff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x0600660e, 0xff000001, 0x0, 0x0c000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x009200f3, 0x000300ff, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0xff000018, 0x2a0104c1, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x000000ef, 0xdf00001f, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x03020000, 0x4320fd00, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0x03bf3c02, 0x05aa0000, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0x03f8fff0, 0xff99c06d, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0xfcff0cff, 0x000300fc, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x00000004, 0x0d00f3ff, 0x02db1e08, 0x0, 0x04000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0x7803ffe7, 0x00000038, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x00000004, 0xff00ff0c, 0x00ff0a00, 0x0, 0x04000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0x1f710000, 0x0fff0000, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x02110049, 0x0e000083, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x0000000c, 0xfe7d0214, 0xffff0000, 0x0, 0x0c000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x01240000, 0x0fff0105, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000009, 0x080c1c03, 0xe009017e, 0x0, 0x09000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0xfcff03ff, 0x02000001, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x19ff01ff, 0xe700213c, 0x0, 0x0a000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0xe7000000, 0x00cc0c00, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x78ffefc0, 0x78ffefc0, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x043e3300, 0x1e07f97f, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00010101, 0x03ff0281, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0xf8000237, 0x003f5bff, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0x017c0100, 0x000003ff, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0xff713e00, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0x3c0006ff, 0x00007e00, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0x33000000, 0x008f02ff, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0x04e700ff, 0x02cff100, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00070000, 0x013601aa, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x00c03bff, 0x03ffff00, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x0000000c, 0x2300ff07, 0xcf780100, 0x0, 0x0c000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0xc17104ff, 0x34fde034, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x7f070000, 0x7f0f0100, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0x0e000003, 0x00ff0601, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0xffffffff, 0x710000ff, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0x00ffffff, 0x8000004f, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0xf71c9918, 0x0014aa00, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x0000007e, 0x00ff004b, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0x0a360303, 0x0000e7ff, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x00000004, 0x7effe13c, 0x03ff0700, 0x0, 0x04000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0x7efcff1c, 0x9201040d, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x00000009, 0xffff1800, 0xff0c0117, 0x0, 0x09000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x83446d02, 0x83446d02, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x137e0101, 0x99ff7e9f, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0xff000d02, 0xcf020f00, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x01600107, 0xffff4f04, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x318e00ff, 0xffffff2e, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xff000000, 0xff0666cf, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0x9f242470, 0xff00000f, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x00000c0b, 0xff0ef102, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0x00000000, 0x3f872c0d, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000007, 0x0f1913ff, 0x001e7cff, 0x0, 0x07000000 - dspck_dstio cmpgdu.le.qb, 0x00000001, 0xff8f7e66, 0x2c0626ff, 0x0, 0x01000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0x07ffaa07, 0x03040001, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x0000000d, 0x0f008300, 0xdf290ef7, 0x0, 0x0d000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0x0aff1701, 0x00fffc00, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0xff007cff, 0x03ffff80, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0xf90003ff, 0xff7ffe13, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x02fd0100, 0xdb03aa01, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xff000003, 0xff7effff, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x1602001c, 0x99220302, 0x0, 0x0e000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0xf3ff0000, 0x006000ff, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0xff8f001c, 0x092f0100, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x00000008, 0x00e7077e, 0x0020002f, 0x0, 0x08000000 - dspck_dstio cmpgdu.le.qb, 0x00000002, 0xaa0100ff, 0x0800ff06, 0x0, 0x02000000 - dspck_dstio cmpgdu.le.qb, 0x0000000f, 0xff000001, 0xff18f906, 0x0, 0x0f000000 - dspck_dstio cmpgdu.le.qb, 0x00000009, 0x00ffff05, 0x00718107, 0x0, 0x09000000 - dspck_dstio cmpgdu.le.qb, 0x00000003, 0x71193401, 0x6000ffdb, 0x0, 0x03000000 - dspck_dstio cmpgdu.le.qb, 0x0000000b, 0x008e0111, 0x0000992b, 0x0, 0x0b000000 - dspck_dstio cmpgdu.le.qb, 0x00000000, 0x71ff5508, 0x0d060003, 0x0, 0x00000000 - dspck_dstio cmpgdu.le.qb, 0x00000005, 0x81ff3600, 0x5bff03ff, 0x0, 0x05000000 - dspck_dstio cmpgdu.le.qb, 0x0000000a, 0x078700ff, 0xff0383cf, 0x0, 0x0a000000 - dspck_dstio cmpgdu.le.qb, 0x0000000c, 0xff00ff04, 0xffff8101, 0x0, 0x0c000000 - dspck_dstio cmpgdu.le.qb, 0x00000006, 0xff00008f, 0x19ff3a00, 0x0, 0x06000000 - dspck_dstio cmpgdu.le.qb, 0x0000000e, 0x00c00020, 0x0fe00000, 0x0, 0x0e000000 - - writemsg "[11] Test dpa.w.ph" - dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xfea8b6db, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xf0017fff, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x0005b1d8, 0x6e41ec9a, 0x0005b1d8, 0x81590494, 0x80007ffa, 0xd5d3fc01, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x0327f3a3, 0x96512bf6, 0x0327f3a3, 0x5682ab94, 0x00628000, 0x7fff7fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xc71b8002, 0xfffe71c7, 0x7fff8000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xfffec14f, 0x38e18814, 0xfffec14f, 0x638c8814, 0x0000aaaa, 0x80058000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x3ffc0006, 0x00007ff9, 0xfff67fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0xffffffff, 0xffffffe0, 0x00000000, 0x3ffc7fe7, 0x8000fff9, 0x80007fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0e3536, 0x001f0000, 0xf8f90007, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x2aab0000, 0x0000aaaa, 0x09558000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x003b4563, 0x02d52d0c, 0x003b4563, 0x03832a54, 0x015c0000, 0x7ffe8000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xfffffffe, 0xffffffff, 0xc0037ffe, 0xffc07ff9, 0x00008000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x0000ffff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x7fffffff, 0xffffff80, 0x7fffffff, 0x8002ff7c, 0x80007fff, 0x7fff8004, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000001, 0x7fffffff, 0xf1c770f2, 0x1c710f0f, 0x8000ffff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0xc71bf1c8, 0xffff3fc0, 0x7fff0000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0xfffef965, 0x04b726aa, 0xfffef965, 0x44ae23d7, 0x800fff00, 0x80030003, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x00000000, 0x02857fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000002, 0x00000000, 0x00048ec7, 0xffb70002, 0xf003ffd0, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xc0020000, 0x7fff7ffc, 0x00008000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x0ff061e0, 0x80000002, 0xe01ff0f0, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xfff5c2de, 0xffffffff, 0xe7f502dd, 0x7ffff003, 0xc0018000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xc0597f4e, 0x7fff7fff, 0x800600ac, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff69fff2, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0xe0000000, 0x00000003, 0xdfffffff, 0xfffd0083, 0xffff8000, 0x7f800005, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xffffffff, 0x00000000, 0x01b6077b, 0xf8848000, 0xfffffc94, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xf873d01e, 0x7ffffc01, 0xf0f00110, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0xc0000000, 0x00000007, 0xc0000000, 0x00000007, 0x3ec40000, 0x00007fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x2622e9f3, 0x17799bff, 0x2622e9f2, 0xecfa45f0, 0xfe5d807f, 0xff7e5555, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x000aedee, 0x0002fc01, 0x0055fd44, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000004, 0x80000000, 0x00bef99e, 0xe007f14d, 0x0000f302, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x741b9c5f, 0x00000000, 0xb41a9c60, 0x7fff7fff, 0x7fff0000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffff8001, 0x7fff0000, 0xffff8000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0xffffffff, 0xfffeaa5a, 0xffffffff, 0xfffebef1, 0x00000003, 0x000506dd, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000035, 0xffffffff, 0xfe814613, 0x8002e00f, 0x02fefffe, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xe013ffe0, 0x7fff3ff8, 0x00208000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000007, 0xffffffff, 0xffff8009, 0x00000001, 0xc01f8002, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0xdb6db6db, 0x6db6db6d, 0xdb6db6db, 0x2db75b6d, 0x80000000, 0x7fffff80, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0xffffffff, 0xfffffff8, 0xffffffff, 0xcce10557, 0x6666f007, 0x803f0053, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x013720ed, 0x00000000, 0x413620ee, 0x00007fff, 0xe0077fff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0xffffa810, 0x9221fb51, 0xffffa810, 0x677750a7, 0x00007fff, 0x03ecaaaa, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000003, 0xffffffff, 0xfffffdbd, 0x000000c2, 0x8000fffd, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xff4cd7de, 0xffffffff, 0xff4cb0c4, 0x00000596, 0x7ffdfff9, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0x7ffffffc, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0xf8000000, 0x00000001, 0xf8000000, 0x0325b84d, 0xf9b5fffa, 0x8000f69e, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x66666666, 0x66666666, 0x66666666, 0x66666666, 0x00000000, 0x1ffe800f, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fff2401, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000002, 0x00000000, 0x00018002, 0x80000000, 0xfffdffff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x0000003f, 0x00000000, 0x0001003d, 0x00007fff, 0x19090002, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x0000003c, 0x81f26808, 0x0000003c, 0xc1e2e808, 0x00008000, 0x1c6e801f, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaa47e2, 0xf9580007, 0xfffff0f0, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xfd35146e, 0xffffffff, 0xfd35146e, 0x00008000, 0x7fff0000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0xfff110c9, 0x419edfd7, 0xfff110c9, 0x3a3bee9d, 0x00007fff, 0xfff7f13a, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x00076db4, 0xbdf3e757, 0x00076db4, 0xc151e09b, 0x7fff7fff, 0x07acff10, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x06e3f0e2, 0x3fc0e38e, 0xff20c007, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x00197fca, 0x7fff8000, 0x00350002, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x0000063c, 0xffffffff, 0xf878154c, 0xf801f0f0, 0x00007fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x1fffffff, 0xfffffffc, 0x1fffffff, 0xffff7d40, 0x0002ffeb, 0x0003063a, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfffeb9ae, 0xffa40001, 0x038cfffe, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000165, 0xffffffff, 0xdb6d74b1, 0x8000000a, 0x4924f1ee, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000004, 0x80000000, 0x00000004, 0xfffefff6, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0xf8000000, 0x00000001, 0xf8000000, 0x003cc37b, 0x0000807f, 0x8000ff86, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000004, 0x00000000, 0x03fdfa30, 0x7fff0008, 0x07fc0045, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0xaaaaf1c7, 0x80007ffc, 0x38e30000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xafcb206b, 0xc5fc7fff, 0x7fff9999, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffff4b80, 0xffed0006, 0xff66e003, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0xffffe808, 0xd9a80061, 0xffffe808, 0x99a88061, 0x7fff0000, 0x80000b22, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x07ffffff, 0xfffffffc, 0x07ffffff, 0xfffffffc, 0x00000000, 0xfffa0f9e, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x00347c63, 0xc0077fff, 0xff82002a, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x56606095, 0x00000000, 0x36812046, 0xfff07fff, 0xf001c03f, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x003cf1c6, 0x00018000, 0x71c7ff87, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x3fffffff, 0xfffffff8, 0x40000000, 0x3fb06f1b, 0xfc978000, 0x17558000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0xffffe8a9, 0x744ad39c, 0xffffe8a9, 0x74192138, 0xf0550000, 0x032ce007, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xfffeb769, 0x00000000, 0x002ab769, 0x8000ffa8, 0x00008000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0xffffffff, 0xfb19fa7e, 0x00000000, 0x3b15fa85, 0x7fff7fff, 0x7ffffffa, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0xffffffff, 0xfffffcd4, 0x00000000, 0x000f4b54, 0x8000e163, 0x0000ff80, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x02d5b67b, 0x00000000, 0x3569507f, 0x8e380132, 0x8e380132, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffff8fc5, 0x7fff07e2, 0xffff0002, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x000000fc, 0x00000000, 0x1f400ba0, 0x7ffffb32, 0x3fe02492, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000004, 0xffffffff, 0xff8ddae8, 0x0772fff9, 0xf0f04924, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000006, 0x00000000, 0x3ffa802c, 0x7fff7ffb, 0x00027ff8, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0xffff476a, 0xccd415fe, 0xffff476a, 0xb052960e, 0x8000ffd8, 0x38e36666, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x7fff0010, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x0fffffff, 0xfffffffe, 0x0fffffff, 0xffff9cbe, 0x0000ffc0, 0x5555018d, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x0000ffff, 0x0000ffff, 0x0000fffe, 0xfffd03ef, 0xc03f0000, 0x00107fff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xdb6fb668, 0x00078006, 0xfff04924, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x00000007, 0x00000000, 0x0035128a, 0x8000ed7d, 0xff96ffff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x0000e9ce, 0x507e3769, 0x0000e9ce, 0x340c704d, 0x00007fff, 0x257ac71c, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0xc71c71c7, 0xfffdffff, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x0000fff3, 0xfffe01d3, 0x80060000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000611, 0x0ecd277d, 0x00000610, 0xdd4598c5, 0x71c77fff, 0x80000eb8, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffffe978, 0x0780fffc, 0xfffd0002, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0xfffc06ca, 0x9100de16, 0xfffc06ca, 0x91009566, 0xffffb6db, 0xff8b0001, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x06729d6e, 0x2f7fe3e8, 0x06729d6e, 0x2f803306, 0x0ff8001f, 0x0005fffa, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x0000000f, 0x00000000, 0x00030003, 0x00008002, 0xcbb4fffa, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xe0057ad6, 0x7ff0fffe, 0xc003027d, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000ff8, 0x1b440000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00327ee6, 0xa703c34a, 0x00327ee6, 0xa6e88491, 0x0000c003, 0x0000006d, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x0008f375, 0x3ff0120b, 0x0000007f, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x00800000, 0x0000ff00, 0x1ffc8000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0xffffffe3, 0xe65d492d, 0xffffffe3, 0xcd70897d, 0x7ffb71c7, 0x3ff08000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0xfff08000, 0x00008000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000002, 0x80000000, 0x1248db70, 0x00002492, 0x80007fff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0xfffd6e60, 0x3316951d, 0xfffd6e5f, 0xf318951a, 0xf9d98003, 0x00007fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x7fffffff, 0xfffffffc, 0x7fffffff, 0xffe1404a, 0xffc4e003, 0x7fff0006, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000006, 0x00000000, 0x00000006, 0x800ffffa, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000007, 0x7fffffff, 0xffffee07, 0xff000001, 0x00120000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x02001147, 0xffffffff, 0xc220904e, 0x8000001f, 0x7fc00419, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0xffffffff, 0xffffffc7, 0x00000000, 0x000eb887, 0xc71c3fe0, 0xffc00002, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xfc01f95e, 0xfffe1ffc, 0x3333e00f, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x7fffffff, 0xfffffffc, 0x7fffffff, 0xe007fffc, 0x80000000, 0x3ff0ff2a, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000001, 0x1f1b24b5, 0x00000001, 0x1f1a8022, 0x0001db6d, 0x80000001, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xffffff8d, 0x00000000, 0x003fff0e, 0xffff007f, 0x80007fff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffe8002, 0xfffd8000, 0x7fff0000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0xf8000000, 0x00000001, 0xf8000000, 0x00000001, 0xf3a4ff26, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xffff8000, 0x00018000, 0x80000000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfff8000f, 0xfffe7fff, 0x0000fff0, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xffd105f4, 0x0000fb1c, 0x7fff099b, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xfffffff0, 0x80000000, 0x000042ad, 0x000000ff, 0xf8010043, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x40003f01, 0x007f8000, 0x007f8000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xfffffffb, 0x7fffffff, 0xfffffffb, 0x00000000, 0x0ffc7fff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xc00fffe1, 0x0000801f, 0xff7d7fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xffffb6da, 0xccccdb6d, 0x00000002, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x80008000, 0x80000000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xfa667d3a, 0x7ffaf655, 0xeb218000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xfffffff0, 0x00000000, 0x03c3a1d2, 0x00003ffe, 0x80000f0f, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffe8, 0x38706230, 0xffffffe8, 0x38706230, 0x00000000, 0x0000f9c2, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x000000e3, 0x9d3c57e4, 0x000000e3, 0x9dda56a8, 0x00007fff, 0x17c7013c, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x000000ff, 0xffffffff, 0xfffec914, 0x00120003, 0xf001f801, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0xf66afd8a, 0xf6925efe, 0xf66afd8a, 0xf6935f02, 0x0002ff00, 0x0002ff00, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xffffff80, 0xffffffff, 0xfff8ab72, 0x002bfffc, 0xd2e2f001, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x0000003f, 0x7fffffff, 0xffc000bf, 0x00007fff, 0x0000ff80, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xffffffff, 0x00000000, 0x402d0000, 0x7fff8000, 0x7fffffa4, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000d70, 0xffffffff, 0xfff68d70, 0x06548000, 0x00000013, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0xfffffff8, 0xc5d3660c, 0xfffffff8, 0xc5d32d23, 0x38e3fffd, 0xffff0002, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfc19edf3, 0x003c0ff8, 0x5555c03f, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xfffffff8, 0xffffffff, 0xfe9500f6, 0x80028000, 0x007f0257, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0xffff0000, 0xffff0000, 0xffff0000, 0xc000c012, 0xe0018000, 0x00127ff8, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00778b21, 0x00000000, 0x00778b21, 0x0037ffc3, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x0031c77c, 0x00000000, 0x005c477c, 0x00008000, 0x0001ffab, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xbffd8000, 0x80000006, 0x7fff8000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xffffffbe, 0xfffe0006, 0x0000fff5, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x7fffffff, 0xfffffffa, 0x7fffffff, 0xfc827fb8, 0xfc01c821, 0x00000ffe, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfd5b467a, 0x7fff2d18, 0x0005f0f0, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000e01f, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x0fffffff, 0xfffffffe, 0x10000000, 0x0ab3301e, 0x38e30f0f, 0x0e457fff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000003, 0x80000000, 0x00000003, 0x000003fe, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xffffffeb, 0xffffffff, 0xffffffeb, 0xf0078000, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x009b60e1, 0x00140c77, 0x00140c77, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0xfffffffd, 0x7aed58f9, 0xfffffffd, 0x88bfbd54, 0x1ba50000, 0x7ffffffe, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x0000000a, 0xc9d0d535, 0x0000000a, 0xd158d535, 0x00008000, 0x0000f0f0, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xe0000000, 0x00000003, 0xdfffffff, 0xfffd0003, 0xf0010006, 0x00008000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0xf0000000, 0x00000003, 0xefffffff, 0xc0075d1e, 0xff458000, 0x00df7ff0, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0xe38e38e3, 0x8e38e38e, 0xe38e38e3, 0x8e3cdf96, 0xfffafffe, 0x807f807f, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0xe0000000, 0x00000003, 0xdfffffff, 0xc0005a83, 0x8000ffc0, 0x7fff0096, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xc0007ec0, 0x8000fff8, 0x7fff0028, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0xfffffffc, 0xa1321610, 0xfffffffc, 0xa13a9487, 0x0009ff80, 0x7ffff803, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000b0c, 0xdf2900d5, 0x00000b0d, 0x1f280c3a, 0xfffa7fff, 0xfe1a7fff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf68b7b4f, 0x00001546, 0x80028e38, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x1bab38e8, 0x01897ff8, 0x800038e3, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xff916db6, 0xffffffff, 0xff9f2e07, 0xfff9001f, 0x3ff07fff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0xfffffffd, 0x1bb2d7a6, 0xfffffffc, 0xfdfa1318, 0xc71c7fff, 0x7ffffd72, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x000004d5, 0xafe0f76c, 0x000004d5, 0xafe1776b, 0x7fff0000, 0x0001ffff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0xfe090217, 0xbea0acbe, 0xfe090217, 0xbe01216e, 0x80007ff8, 0x02a9016a, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000003, 0x7fffffff, 0xfc8cdbb2, 0x803f0f0f, 0x0035c71c, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x1006a030, 0x1ff08000, 0x7ffdffe2, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x49249249, 0x24924924, 0x49249249, 0x41044924, 0x00008000, 0xff80c71c, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xc0000000, 0x00000007, 0xbfffffff, 0xff9b00d1, 0xf95005e6, 0x7fff7fff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x0002b5a3, 0xffffffff, 0xfffd35a3, 0x000bfffe, 0x80000000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0xfe5c9ac4, 0x23718f95, 0xfe5c9ac4, 0x43614fb5, 0x80007fff, 0x00003fe0, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0xb6db6db6, 0xdb6db6db, 0xb6db6db6, 0xdb6db6db, 0x07fc0006, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xffffffc0, 0xffffffff, 0xfffffddd, 0x0063000c, 0xffffffe0, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x0000a7cc, 0xffffffff, 0xe2e9bf23, 0x3a310000, 0x8007ffd2, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0xffffffff, 0xfffffff9, 0x00000000, 0x0000005e, 0xfff6ffff, 0xfff6ffff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0000800f, 0x00070000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x000000ff, 0xffffffff, 0xfff7837c, 0x0003ffec, 0x7fff7fe0, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00007fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x03fe3739, 0x00000000, 0x03fe3739, 0x00000000, 0x8000fff8, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0xfffffff8, 0xae7abf0a, 0xfffffff8, 0xaeca3e6b, 0x0000009f, 0x00007fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0xfffffcbe, 0xdc7790df, 0xfffffcbe, 0xebc796d1, 0x23bb0000, 0x6db6000b, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xdb6db6db, 0x6db6db6d, 0xdb6db6db, 0x74d2e9a5, 0xc0038e38, 0x0000f001, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x003ff001, 0xfffff801, 0xfffff801, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000001, 0x7fffffff, 0xff9a1a00, 0x66660001, 0xff007fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x00207fbe, 0x7ffffffc, 0x00410000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x00efff27, 0xf0f00002, 0xf020f094, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xfffffee6, 0x00000000, 0x3ffffee6, 0x80000000, 0x80007ffc, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000006, 0xffffffff, 0xffdf8047, 0x7fff8000, 0xffbf0000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x07ffffff, 0xfffffffc, 0x07ffffff, 0xf22c8a44, 0xff371c71, 0x80058005, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x000000a8, 0x9e0579ec, 0x000000a8, 0x94aa7e8c, 0x8000b6db, 0x007f1fe0, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x64ef51b8, 0x00000000, 0x64e751c8, 0x0000fff0, 0x7fff7fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x40006dc5, 0xfece7fff, 0xfece7fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0xf0000000, 0x00000003, 0xf0000000, 0x30059ff7, 0x7ffd7fff, 0x7fffe00f, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000001, 0x00000000, 0x040d865d, 0x800f0000, 0xf7e48000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0xc0000000, 0x00000001, 0xc0000000, 0x00000001, 0x00006db6, 0xfffe0000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xc62f7393, 0x7fff800f, 0x0c4e7ffe, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x00c48b94, 0x7666df7e, 0x00c48b94, 0x7649dfb8, 0x00007fff, 0xffc1ffc6, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0xffffffff, 0xfffbe8e0, 0x00000000, 0x18aaea4e, 0x7ff938e3, 0x03dc6666, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0xffff92e3, 0x3fa343fb, 0xffff92e3, 0x877827bc, 0xe01f8000, 0xc01f803f, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x07109f0c, 0xc00f7fff, 0x0000f003, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xe67fd9c0, 0x38e39999, 0x00003fc0, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0xffffffff, 0xffffff89, 0x00000000, 0x22a6597a, 0x7fff803f, 0x7f803a4f, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0xffffffff, 0xfffd5bb6, 0xffffffff, 0xfd56c572, 0xed937fff, 0x24d40000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x349b6162, 0x00000000, 0x349b5ed4, 0x0000006d, 0x803ffffa, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xfff1ea15, 0x85bc6da8, 0xfff1ea15, 0x85bc6daa, 0x0001c01f, 0x00020000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xfef18cd1, 0x7fff055a, 0xfde30002, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0eef430a, 0xff800bfb, 0x8000f801, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x001ef9b3, 0x000707fe, 0x003503e0, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x05da3d3b, 0x00000000, 0x09fac5da, 0x099c068f, 0x6db60059, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffc0, 0x80000000, 0x1ff681bc, 0xc00f0004, 0x8000807f, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x0000007f, 0x80000000, 0x00022188, 0xffcb000f, 0x00112492, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x00000758, 0x6666fffc, 0x0000fe2a, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f1, 0x29d3ff29, 0x7fff0000, 0x71c70000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0xffffffff, 0xfffffffa, 0x00000000, 0x1b52c21f, 0x0002c03f, 0x01179249, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000f0f, 0x716bbd7a, 0x00000f0f, 0x6d6c4579, 0xc03ff801, 0x00007fff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0xfe678323, 0x8000fcd5, 0x00067fff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0xffffffff, 0xfe7b529d, 0xffffffff, 0xfe7a7ccd, 0xfff50ffc, 0x11fcffff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0x00000000, 0x00000004, 0x00000000, 0x00008004, 0x80001c71, 0xffff0000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xfffffefb, 0x9999fefb, 0x00000001, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xfffffffb, 0x7fffffff, 0xfe207fbc, 0x03fe7fff, 0x8000003f, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x0000400a, 0x00010006, 0x3ff80003, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x0000003f, 0xffffffff, 0xfc713b43, 0x9999f87c, 0xff807fff, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000e4c, 0xf60a9f91, 0x00000e4d, 0x6eee9f91, 0x8e388000, 0x80008000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0xc0000000, 0x00000001, 0xc0000000, 0x3fe08041, 0xfffe7fff, 0x80007fc0, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0xfefccbd4, 0x00017fff, 0xccccfff8, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffff75f, 0x0001ffe9, 0xf6bffff9, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x30c1fe84, 0x71c7fffb, 0x6db61ffe, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0xfd9e612d, 0x27f639e9, 0xfd9e612d, 0x681b685a, 0x80000619, 0x80000619, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000004, 0x80000000, 0x00000004, 0x7fe0fe15, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xffffffff, 0x00000000, 0x000017b4, 0x000f05f1, 0xffff0004, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x71c71c71, 0xc71c71c7, 0x71c71c72, 0x070cefdb, 0x0052801f, 0xfffa8000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80003333, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x0049ffd8, 0xff6cffff, 0x80000028, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x00000000, 0x001fc0e8, 0x00000000, 0x0017e2a1, 0xe0070000, 0x003f8000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x012bfff0, 0xb6db801f, 0xff05fe37, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0xffcf2742, 0xf03b2b2a, 0xffcf2742, 0xf03b2b2a, 0x0004fffe, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffec23, 0x46cbc035, 0xffffec23, 0x46cb4035, 0x00008000, 0x80000001, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x1fffffff, 0xfffffff8, 0x1fffffff, 0xfe6afff8, 0x032a0f0f, 0x80000000, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac3, 0x00000000, 0x00000034, 0x00000000, 0x0001381d, 0xf8030002, 0xfff97fff, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000005, 0x7fffffff, 0xffb1efe1, 0xffec0218, 0x803fd5f3, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xff8cfada, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0xffff0000, 0xffff0000, 0xffff0001, 0x00949c5a, 0x8000ec5a, 0x000ff801, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x00d6ffff, 0x000a8000, 0x8000fe48, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00005fa3, 0xe01f7fff, 0xfffd0000, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000007, 0xc4ab6b32, 0x00000007, 0xc49beb32, 0x3fc08000, 0x0000001f, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac2, 0xffffffff, 0xfffffff8, 0x00000000, 0x0001cdc2, 0x6666fff8, 0x00071fe0, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x00000000, 0x00000002, 0xffffffff, 0xff970002, 0x00d20000, 0x8000fffe, 0x00010000, 0x00010000 - dspckacc_astio dpa.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xff910bc3, 0x0000f90f, 0x7fff0ffc, 0x00000000, 0x00000000 - dspckacc_astio dpa.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xf2080040, 0x1bec7ff0, 0x8000fffc, 0x00000000, 0x00000000 - - writemsg "[12] Test dps.w.ph" - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000006, 0x00000000, 0x031d1f69, 0x24920059, 0xea34fffd, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xffd46ab9, 0xffffffff, 0xe7e05a7a, 0xe00ff001, 0x8000803f, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffc605c, 0x0000054d, 0x077200af, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffeef54, 0x02500035, 0x0076ffff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000011, 0xd9821737, 0x00000011, 0xd9821ce5, 0xffff0024, 0xffeaffd7, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfff5a297, 0xfc010000, 0xfd68fffd, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xdffe8000, 0xc0018000, 0x8000fffc, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfffc8007, 0x7fff0000, 0x00070000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xf62487d3, 0x0ff8801f, 0x1ffef043, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xfefffffc, 0x0ffeff80, 0x0ffeff80, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0xffb4d691, 0x925251d6, 0xffb4d691, 0x125851bc, 0x7ffb7fff, 0x7ffb7fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0xffffffff, 0xfffa95a7, 0x00000000, 0x0007559f, 0x3ffc7fff, 0x80063fe0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x3fff8000, 0x80008000, 0x00007fff, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x0000d78e, 0xffffffff, 0xc0005796, 0x00037fff, 0x7ffd7fff, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xfeb5447c, 0xf98cfffb, 0xccccf003, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xffffff61, 0x00000000, 0x03591d89, 0xe8480000, 0x24238000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x0001ffeb, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0xffff0000, 0xffff0000, 0xffff0001, 0x020e6b68, 0xfabdf001, 0x6666ff4a, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x5874e925, 0x00000000, 0x5870e925, 0xf8038000, 0x0000fff8, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x0002dd5b, 0xffffffff, 0xfff80bd9, 0xfffefc9e, 0x08f7fcc8, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0xffffb42d, 0xf197cd6f, 0xffffb42d, 0xf1982d0f, 0x1fe0ffff, 0xfffe1fe0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xfffffffe, 0xffffffff, 0xffff800d, 0xfff07fff, 0xf001ffff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x92492492, 0x49249249, 0x92492492, 0x49249249, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x00001d14, 0x83abf203, 0x00001d14, 0x9d391ce9, 0xffe9c01f, 0x00c06666, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xc3fef807, 0x8007f809, 0x80007fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xfedc7fdb, 0xffdb8000, 0x7ffffd94, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffffffb, 0xffffffff, 0xfffffe07, 0xfff8fffd, 0xffedff8c, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x0000fae6, 0x07d70002, 0xffe0fffd, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0xc0000000, 0x0000001f, 0xbfffffff, 0xc007801f, 0x80000000, 0x800f0000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x1242ffff, 0xfff48000, 0x80002492, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0xfffff85b, 0x0e81b11b, 0xfffff85b, 0x4e7abf64, 0x7fff001d, 0x800038e3, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x800fc001, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xffffe536, 0x55eaa9bd, 0xffffe536, 0x574b935b, 0x1b478000, 0xe38efcb2, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffffec3, 0x00000000, 0x40102c07, 0x7fff3fc0, 0x8004ffb5, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x1fefffff, 0x80008000, 0x00003fe0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xff9e18fc, 0x7fc0ff2c, 0x005ac003, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xf80c0fe8, 0x7fff0ff8, 0xfff07fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x0000007f, 0x00000000, 0x004c5144, 0xff590099, 0xffd4801f, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x0fffffff, 0xfffffffc, 0x10000000, 0x01ff7bb5, 0x00187fff, 0x0003fc01, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0xe0000000, 0x00000003, 0xe0000000, 0x00000003, 0x3ff8ff84, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xfffffff9, 0x00000000, 0x0001c713, 0x00027fff, 0x1c71fffc, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x0177ccbc, 0xcbfb5c14, 0x0177ccbc, 0x8bfb5c14, 0x80000000, 0x80000000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xfdd9de19, 0x48ff2817, 0xfdd9de19, 0x48ffba61, 0xb6db0000, 0x00023fe0, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x1def42f5, 0x00000000, 0x5dc67abc, 0x02e8807f, 0xf8037fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0xffffffff, 0xffed319b, 0xffffffff, 0x7fee319a, 0x80007fff, 0x80007fff, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xffff8e7d, 0x45453af3, 0xffff8e7d, 0x354dd35b, 0xfff87fff, 0x0f0f1ff0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0003edfe, 0xdb6d8000, 0x0065ffe9, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xffff568a, 0xffffffff, 0xffff568a, 0x00000000, 0x8000ff6b, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x0002e38e, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xffdd0046, 0x00468000, 0x7fff0000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x24924924, 0x92492492, 0x24924924, 0x92491b5e, 0x09340000, 0x0001ffe4, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xffffff80, 0x00000000, 0x001f7ee1, 0x0006003f, 0xfd85803f, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x0005a068, 0x000fe007, 0x8000fff1, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xfffffff9, 0x7fffffff, 0xbf504bb8, 0x801f7f80, 0x801f019f, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xbaec1244, 0x7ffff491, 0x7fff8e38, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xfffffffd, 0x00000000, 0x0026dc42, 0x7fffdb6d, 0x00060125, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xc0000000, 0x00008000, 0x00008000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xffff6db8, 0x000236e3, 0x49240000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xe38efff7, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xee497f93, 0xffffffff, 0xefc014a3, 0xc003fb49, 0xff915555, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xfffc0000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000024, 0xffffffff, 0xf0037ff3, 0x0000c007, 0x0000c007, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00001455, 0xf149a2cb, 0x00001455, 0xb15122cb, 0x8000005b, 0x800f0000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x0011fe1d, 0x0024ffff, 0x800f003a, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfc0ee2b9, 0x0ffef803, 0x3ff801bd, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x0002e003, 0x00061ffc, 0x80000001, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffffff0, 0xffffffff, 0xfffffff0, 0x0040e774, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0xfffff967, 0x9b888bb0, 0xfffff967, 0x7d9789b0, 0x80003ff0, 0x03fe7fe0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xfe7627ab, 0xffffffff, 0xbe29a78b, 0xff467fe0, 0x80007fff, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000006, 0xffffffff, 0xbffb800f, 0x80000009, 0x80007fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x1fde46df, 0xfffd807f, 0x01a13ffc, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x3fffffff, 0xfffffff0, 0x3fffffff, 0xfffffff0, 0x00000000, 0x00003ffe, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x01e66d68, 0x80008005, 0x001503b8, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000007, 0x80000000, 0x3fff8007, 0x00007fff, 0x71c78000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000034, 0x00000000, 0x0003fffc, 0x7ff9fffe, 0xfff80000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x0000007f, 0x00000000, 0x000266a7, 0xffc0fffd, 0x0999fff8, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000009, 0xffffffff, 0xfffc7c5f, 0x003f7fff, 0x000f0007, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0xfffffe55, 0x7b4d9ef3, 0xfffffe55, 0x7b3778fe, 0x00ca0003, 0x1d05c001, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0xb348e486, 0x00000000, 0xb349a429, 0x00030000, 0xc01fe7de, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x0009f1bc, 0x4768935b, 0x0009f1bc, 0x59bbd016, 0x04117fff, 0xfd92db6d, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0xf8000000, 0x00000001, 0xf7ffffff, 0xffb2f4ce, 0x0181ffc0, 0x3333ffd2, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0xf8008007, 0x0003f001, 0xfffb8000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0xc0000000, 0x0000000f, 0xc0000000, 0x0000604d, 0xff460002, 0x007ffe04, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00030001, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x38e38e38, 0xe38e38e3, 0x38e38e38, 0xe18c3ce1, 0x7ffffffa, 0x03fe8000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xf84cad82, 0x198c7566, 0xf84cad82, 0x2569485b, 0xee79e001, 0x38e33fc0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000005, 0xffffffff, 0xc03ec8a1, 0xdb6d7fff, 0xfff47f80, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfe067001, 0xfc0df003, 0x8000ffff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x7fff0000, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x00038e1c, 0xdaf28bc2, 0x00038e1c, 0xfaf14bc4, 0x7fff7fff, 0xc003ffff, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x0000006f, 0x00000000, 0x1974006f, 0x80000000, 0x32e83fe0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000302, 0x00000000, 0x1f96026e, 0xaaaa8000, 0xff223fc0, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xe3f868fb, 0x1ff8c71c, 0xfd1c803f, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00d4e530, 0xfffd7ff0, 0x8000fe53, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0xffffff8e, 0xe33f475b, 0xffffff8e, 0xe33f475b, 0xfdb2e007, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x0000007f, 0xffffffff, 0xffd23219, 0x00a0000e, 0x492401b5, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xfff29624, 0x3f07165b, 0xfff29624, 0x3f59bda8, 0x00f5ce18, 0xc03f006f, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xe38e8000, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xe0000000, 0x00000003, 0xe0000000, 0x4034fd16, 0x8000006b, 0x7fff8007, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x0000001c, 0x61d58d9d, 0x0000001c, 0x69d48d9d, 0x8000c01f, 0x0ffe0000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xe221254c, 0x39a33aaf, 0xe221254c, 0x00c02bc7, 0xfff97fff, 0xffe771c7, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000005, 0x7fffffff, 0xfc03ff05, 0x00001ff0, 0x00001ff0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x24924924, 0x92492492, 0x24924924, 0x91b5a5e8, 0x024efffe, 0x3ffefe5d, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xfffffffd, 0x00000000, 0xff803fc0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x0398379a, 0x00000000, 0x4397b86c, 0x000f7fff, 0xfff28000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0xffff0000, 0xffff0000, 0xffff0001, 0x303158c1, 0x71c70ff8, 0x92490910, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0xffffed68, 0x8d8942da, 0xffffed68, 0x8d8aac1a, 0xffc00000, 0x05a50000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xf62cae7c, 0x00000000, 0x364aaa7f, 0x7ff07fff, 0xffc08003, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xfffffff0, 0xffffffff, 0xfd8dfff0, 0xfb158000, 0x80000007, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xfffffff5, 0x5e8df3c0, 0xfffffff5, 0x5e8df3c0, 0x7ff001e6, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x00ff00ff, 0x00ff00ff, 0x00ff00fe, 0xc10080fd, 0x00007fff, 0x7fff7ffe, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x0fffffff, 0xfffffffc, 0x0fffffff, 0xc9247fed, 0xfffb9249, 0xfffd8000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x0357b2bf, 0x0a07ffcd, 0xaaaa0007, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x3fff8000, 0x7fff0000, 0x80008007, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x0000003f, 0x00000000, 0x000d473e, 0x800038e3, 0x0003ffcb, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x03ceffff, 0x80008000, 0xfff907a5, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffff80, 0x7fffffff, 0xffffffa8, 0xfff80000, 0x0005e003, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffe9fc01, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xffffffff, 0xffffffff, 0xf9e87fff, 0xffc2f40f, 0x80008000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffdb, 0xe2a6bef0, 0xffffffdc, 0x1be2734c, 0xfa768e38, 0x0fea7fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff80005, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffff80, 0x80000000, 0x00007f7f, 0x80007fff, 0x7fff7fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xfffffda8, 0x00000000, 0x0004294a, 0x00040052, 0xfffef2fb, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xffffe010, 0xffe00001, 0x00001ff0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0x5170d173, 0xffffffff, 0x509943d5, 0x8000fe0e, 0xfe51fff9, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x0fffffff, 0xfffffff8, 0x10000000, 0x10f77036, 0xd8690007, 0x6db60004, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0xc0000000, 0x00000001, 0xc0000000, 0x00000001, 0x00000000, 0x8000003f, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xffffff80, 0x80000000, 0x00007efd, 0x807f0001, 0x00010004, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0xff12c914, 0x4706b369, 0xff12c914, 0x71b03367, 0x7ffd8000, 0xaaaaffff, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x0000ffff, 0x0000ffff, 0x0000fffe, 0xfed1ce7f, 0x00ff019a, 0x7ffc6db6, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0xfffffc15, 0x279f88fc, 0xfffffc14, 0xd7af08fc, 0x80008000, 0x8000e01f, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x0000000f, 0x6ea838f3, 0x0000000f, 0x4e0a48e4, 0x7ff907fc, 0x39477fc0, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x3ffc8000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00006950, 0x00000000, 0x00008750, 0x000f003c, 0x0000ff80, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0xffed0000, 0x0000fffd, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x3fffffff, 0xffffffe0, 0x3fffffff, 0xffffffe0, 0xfffd7fff, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xfffa17ca, 0xffffffff, 0xffbb9847, 0x00007fff, 0xb6db007d, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x0001113d, 0x8e3b5ea2, 0x0001113d, 0x73031513, 0x00003671, 0x11317fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x0363d379, 0x00000000, 0x0302d379, 0x80000000, 0xff3effff, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xffffff4c, 0xfffa7fff, 0xffe20000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xcb29ffff, 0x7fff8000, 0x7fff1652, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x0517ffff, 0x00000a30, 0x7fff8000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x0000003f, 0xffffffff, 0xffea3c92, 0xd1cbff41, 0xfffde38e, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x0022cfdc, 0xc92af564, 0x0022cfdc, 0xc93dd308, 0x0ffe0000, 0xfed28005, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffcc86a7, 0x7ff0fff9, 0x006e7ff8, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x8000e007, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00038000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00000006, 0xffffffff, 0xfff650a1, 0x0000ff65, 0xe007f001, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xeffad4a8, 0x8000039c, 0xe01f05ba, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xe0000000, 0x00000007, 0xe0000000, 0x0011ff48, 0x7fff001f, 0xffdc0005, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfff8fc05, 0xffffffff, 0xf50e7c05, 0x8000f432, 0xf5f98000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x3fff8000, 0x8000c001, 0x7fff0000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffff47f7, 0x038a1c71, 0x00340000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000004, 0xffffffff, 0xfafb0509, 0x5555b6db, 0x0f0f0000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x000000ff, 0xffffffff, 0xfce5bd96, 0xe00f7fff, 0x072907fe, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0xffffe980, 0xe7bdf8a9, 0xffffe980, 0xe7b95573, 0xfffed57b, 0x01abffe4, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00000003, 0xffffffff, 0xc048d5cb, 0xc71c8000, 0x0102801f, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xffffd806, 0x7a69a0e1, 0xffffd806, 0x93b24539, 0x8e3803fe, 0x38e30000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x1fffffff, 0xfffffff8, 0x1fffffff, 0xfff88007, 0x7fff0000, 0x000f8000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x3ff80004, 0xffff8000, 0x00057ff0, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000004, 0x00000000, 0x00270004, 0x004efffa, 0x80000000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x7fff0000, 0x7fff7fff, 0x80008000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x0000038e, 0xffffffff, 0xe4927401, 0xfffe9249, 0xe15ec001, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x000002a3, 0xfffeffd3, 0x0000000f, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x3fffffff, 0xfffffffe, 0x3fffffff, 0xff133892, 0x7fff801f, 0x0007fe2d, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffff80, 0x80000000, 0x0ffbff80, 0x80008000, 0x1ff80000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xc0802392, 0xfc7f8000, 0x24928000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1bd048c9, 0x01ad8000, 0x7fff006a, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x0005b6e2, 0x00010ea1, 0x0002ff9c, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x0000007f, 0x80000000, 0x01604a6a, 0x0f0f8006, 0xe89b0000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffdac984, 0x0000fe0f, 0x001fecd5, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0xfe8f757d, 0xbc23c059, 0xfe8f757d, 0xbc99405d, 0x00ef7fff, 0x80000004, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0xc0000000, 0x00000003, 0xc0000000, 0x00000003, 0x00000000, 0xffff803f, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0xfffff842, 0x21f53073, 0xfffff842, 0x21f53043, 0x0008ffd8, 0x00060000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xcf3d0f96, 0xffffffff, 0xcec97333, 0xe001fffd, 0xfc630000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x0000002f, 0x6519b10d, 0x0000002f, 0x617c5534, 0x073b0000, 0x7ffb08a9, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xe38e03fe, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x03ffffff, 0xfffffffe, 0x04000000, 0x0ff7810e, 0xfff97ffd, 0xe945e00f, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x0007fff0, 0x7fff0000, 0xfff00ffe, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x2492b6da, 0x7fffb6db, 0xffff7fff, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x00088eaa, 0x00000000, 0x016c39e1, 0xfff10590, 0xffe9c00f, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xffc379d5, 0xffffffff, 0xfac623b0, 0x7fffffff, 0x09fb1fe0, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0xfffffb14, 0xe7dadbeb, 0xfffffb14, 0xe7d5943a, 0x00068003, 0xf6a3fff5, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x00007fff, 0xfffffff9, 0x7fff0000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x3fffffff, 0xffffffe0, 0x40000000, 0x0002ffe0, 0x8000fff2, 0x00060000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0xc0000000, 0x0000000f, 0xbfffffff, 0xc0010c0b, 0x00037fff, 0xfc017fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x000079c9, 0xa8334575, 0x000079c9, 0xa83346e9, 0x0006fffd, 0xffc20000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x000c811b, 0x0911974d, 0x000c811b, 0x0911976b, 0xffee0006, 0x0000fffb, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xfffffffc, 0x7fffffff, 0xfffffffc, 0x00038007, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xfffffff6, 0xf53bffff, 0x0000fff6, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xffffff00, 0x00000000, 0x0001bef2, 0xe0010000, 0x000e0ffe, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x3fffffff, 0xfffffff0, 0x3fffffff, 0xffffc80c, 0xeed00007, 0x000007fc, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf0041ff7, 0x7fffc001, 0x1ff80000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xfffc19dd, 0xffffffff, 0xd0f6c108, 0xfffe9249, 0xfffe9249, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x0034c062, 0x9999da9a, 0xfff8017f, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x01d0ebf0, 0x00000000, 0x01ba6ca4, 0x8000002d, 0x00007ffc, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xd639d38d, 0x138f3ffe, 0x7fff7fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0xf0000000, 0x00000003, 0xf0000000, 0x00000003, 0x7f808001, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0xb470ac84, 0x00007ffb, 0xfca72559, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffd559, 0x80001c71, 0x00010006, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0xf8000000, 0x00000003, 0xf7ffffff, 0xfffd6dbf, 0x00000009, 0x80004924, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0xffffffff, 0xfe026710, 0xffffffff, 0xfe026710, 0x00000000, 0x001f07fc, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0xffffffff, 0xfffffffd, 0x00000000, 0x0006968d, 0xff220f0f, 0x0000ff90, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0xffff83a9, 0x59b3a217, 0xffff83a9, 0x59b3a217, 0x00010000, 0x00008000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0xf0000000, 0x00000007, 0xf0000000, 0x000013dd, 0x7ffff615, 0x00000002, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x00000007, 0x09568d12, 0x00000007, 0x3c8a0c93, 0x00016666, 0x807f8000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x000003d4, 0xebe18f2f, 0x000003d4, 0xebdd0fc9, 0x00000125, 0x800003ee, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x0000003f, 0x80000000, 0x31c71cb0, 0x80001c71, 0x7fff7fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0xfffa4621, 0xbeeb1105, 0xfffa4621, 0xbeeb0f90, 0x0007ffee, 0x0007ffee, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x3fffffff, 0xffffffe0, 0x3fffffff, 0xc0017edf, 0x007f7fff, 0xff007fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x002c2f59, 0x00000000, 0x002b3b45, 0xfffcffff, 0xc2fb0000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xfffffc92, 0x522e8973, 0xfffffc92, 0x521e9b71, 0x0ffeffc0, 0x00ff0000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x00000000, 0x1b037b3e, 0x00000000, 0x1b037b3e, 0x00000000, 0x7fff7fff, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffffff0, 0xffffffff, 0xfffc10a4, 0x003f0006, 0x0ffefff7, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x000014dc, 0x582af822, 0x000014dc, 0x5815f837, 0xffe65555, 0x0000003f, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfdf2fbe5, 0xfffff9d9, 0x0000aaaa, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf8007fff, 0x0000f001, 0xc0038000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x0be5e487, 0x6003ca86, 0x0be5e487, 0x6003ca86, 0x00000000, 0xaaaafffe, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xffffc1bc, 0xfffb0000, 0xf38c8000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfebd83bf, 0x050f0000, 0x3fc0004c, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xfff101be, 0x7fffc007, 0xfffeffc0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x000006ff, 0xe1cf2bdc, 0x000006ff, 0xe1cf64c7, 0x0007e38e, 0xffff0002, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xffce0ff8, 0xfffe8000, 0x07fcff9c, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0xffffffff, 0xfffd9364, 0xffffffff, 0xfffd7e9a, 0x0000f912, 0x8000fffd, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0xffffffff, 0xffdab1fd, 0xffffffff, 0xdffb11a5, 0x00047fff, 0xf8063fc0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xe0000000, 0x00000007, 0xdfffffff, 0xf3d2e6a5, 0xfff0aaaa, 0x3ff0db6d, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x000000ff, 0x00000000, 0x01bc7e46, 0x80010004, 0x0379ffd0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xf0000000, 0x00000007, 0xf0000000, 0x07fe732b, 0x0321f003, 0xffff7fff, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x8e38e38e, 0x38e38e38, 0x8e38e38e, 0x38eb0dfc, 0x80040000, 0x000fff62, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0xe0000000, 0x0000000f, 0xe0000000, 0x099b4cdb, 0x7fff8000, 0xcccce003, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0x1fffffff, 0xfffffff8, 0x1fffffff, 0xfffffff8, 0x0040ffff, 0x00000000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac0, 0xffffffff, 0xfffbba3f, 0x00000000, 0x0238a350, 0x0531c9ec, 0xffff0a98, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xe38e9999, 0xc71ccccc, 0x80000003, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x0000003f, 0xffffffff, 0xc004002c, 0xfffd7ff9, 0xfffc7fff, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0xffffffff, 0xfffff197, 0xffffffff, 0xffd5f1eb, 0x00540000, 0x7fffe38e, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fff9999, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac1, 0xfffff32e, 0x7a61c863, 0xfffff32e, 0x7a61c863, 0x8000fff8, 0x00000000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac0, 0x55555555, 0x55555555, 0x55555555, 0x94e35557, 0x8002ff1f, 0x7fff8000, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfc003ffe, 0x0000e001, 0x0000e001, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000006, 0x80000000, 0x0603e106, 0x66660005, 0xf0f07fe0, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x000044ed, 0x000f0005, 0x001ff1da, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x800007fc, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xc000ffff, 0x7fff0000, 0x7fff8000, 0x00010000, 0x00010000 - dspckacc_astio dps.w.ph, $ac3, 0x00003469, 0x77af6dfb, 0x00003469, 0x491f8dd3, 0x80001ff8, 0xc2d77ffb, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0xffff2669, 0x49620ddd, 0xffff2669, 0x62fbdaa9, 0xc03fcccc, 0x00007fff, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x01283b98, 0x00000ff8, 0xfff3ed73, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac2, 0x00000000, 0x000de46e, 0x00000000, 0x000e5072, 0x0000001f, 0xfffcfc84, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x80000000, 0x00000005, 0x7fffffff, 0xf00b1997, 0xe007ffda, 0x80003333, 0x00000000, 0x00000000 - dspckacc_astio dps.w.ph, $ac1, 0x0fffffff, 0xfffffffe, 0x10000000, 0x004d6101, 0xf6d10000, 0x086d0014, 0x00010000, 0x00010000 - - writemsg "[13] Test madd" - dspck_astio madd, 0x000007ea, 0x1c572c4f, 0xffb0dd02, 0x1884e628, 0x0d3bfa1b, 0xfa049b1b, 0x0, 0x0 - dspck_astio madd, 0xe0000000, 0x00000001, 0xe0000000, 0x00000001, 0x00000000, 0x011bc658, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xffff323b, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x8000113a, 0xb14ea013, 0x00114bec, 0x00ff00ff, 0x0, 0x0 - dspck_astio madd, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1c71c71c, 0xffffff80, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000033, 0xff8cd5d2, 0x55c87fb6, 0xfea68177, 0x55555555, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffa807, 0x8000aff0, 0xffff500f, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x81c38c39, 0x64a2da2d, 0x33333333, 0x08d1bd1f, 0x0, 0x0 - dspck_astio madd, 0x55555555, 0x55555555, 0x5555558e, 0x65554e33, 0xfffff8de, 0xf8000001, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xffff6498, 0xffffffff, 0xffff6498, 0x00000000, 0x3ffffff0, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffe, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x6db6db6d, 0xb6db6db6, 0x6db6db6d, 0xb6db6db6, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0xffffffff, 0xfffffe1f, 0x0000000d, 0xffffffdb, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x7fffffae, 0x580ad64b, 0xfffffc9f, 0x182a9ad5, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0xfffffff5, 0x800000a8, 0x7ffffff8, 0xffffffeb, 0x0, 0x0 - dspck_astio madd, 0xe38e38e3, 0x8e38e38e, 0xe38e38e3, 0x8e38e38e, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xffdc7f4b, 0x15144627, 0xfaa30721, 0x4e8c6ff3, 0xdb6db6db, 0x24924924, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x0000003b, 0x00000000, 0x0000003b, 0x00000000, 0x1ffffffe, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xfffffffa, 0x40000000, 0x7ffffffa, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7c066337, 0x7fffffff, 0x80000000, 0x07f33991, 0x0, 0x0 - dspck_astio madd, 0x6db6db6d, 0xb6db6db6, 0x6db6db6a, 0xb6db6db6, 0x00000006, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x60000007, 0xbffffff1, 0x7fffffff, 0xc000000f, 0x0, 0x0 - dspck_astio madd, 0x1c71c71c, 0x71c71c71, 0x1c71c74a, 0x71c71c15, 0x7fffffff, 0x0000005c, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffff9, 0x00000000, 0x000675b9, 0xffffb140, 0xffffffeb, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0xc0000000, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x07ffffff, 0xfffffffe, 0x071ac183, 0x81ca7cf7, 0xfe358307, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x000017d3, 0x9e7cda6b, 0x000017d3, 0x9e760aca, 0xffffffff, 0x0006cfa1, 0x0, 0x0 - dspck_astio madd, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0x00000006, 0xfffffffe, 0x7ffffff9, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x7f1072c1, 0x1df1a7e0, 0xfe20e582, 0x7ffffff0, 0x0, 0x0 - dspck_astio madd, 0xfc000000, 0x00000001, 0xfc000000, 0x0002c99f, 0x000032f9, 0x0000000e, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffffc, 0x00000320, 0xfffff9ba, 0x00000642, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x0000007f, 0x33333333, 0x8000007f, 0x99999999, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffff80, 0x8000003f, 0xfffffc00, 0xffffff80, 0x80000007, 0x0, 0x0 - dspck_astio madd, 0x06508b03, 0xae37a5e3, 0x06508b03, 0xae37a529, 0x0000001f, 0xfffffffa, 0x0, 0x0 - dspck_astio madd, 0x00125566, 0xabd5de14, 0x00f907a0, 0x65656278, 0xfcd89036, 0xb6db6db6, 0x0, 0x0 - dspck_astio madd, 0xf8000000, 0x00000001, 0xf6000000, 0x97fffffb, 0x7ffffffa, 0xfc000001, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fa40281, 0x044fe1f3, 0x016ff5fc, 0xc0000003, 0x0, 0x0 - dspck_astio madd, 0x66666666, 0x66666666, 0x5e666667, 0x66666666, 0x80000000, 0x0ffffffe, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80000016, 0x7fffe980, 0x7fffff80, 0x0000002d, 0x0, 0x0 - dspck_astio madd, 0x38e38e38, 0xe38e38e3, 0x38e38e38, 0xe38e38e3, 0x00ff00ff, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x99999999, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xfffffb7b, 0x75082318, 0x0002e5d8, 0x74fc79a4, 0x24924924, 0x0014688b, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7ffd7ffd, 0x009b00b9, 0x8000001f, 0x00050006, 0x0, 0x0 - dspck_astio madd, 0xe072cc5d, 0xb8b90a85, 0xe072cc5d, 0xb8b9ba03, 0xffffa841, 0xfffffffe, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x000000d7, 0x3fc4c79c, 0xfffb83d7, 0xffd001c4, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x0000003a, 0xffffbc43, 0x8000003a, 0x00008779, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x92492492, 0x49249249, 0xd2492492, 0x49249249, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000007, 0x00000000, 0x00000007, 0x00000000, 0x1c71c71c, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xffffe6ab, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x0000004f, 0xaaaaaa5b, 0x000000ef, 0x55555555, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x33053ce3, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x92492492, 0x49249249, 0x92492482, 0xa36ac2e2, 0x000d1d3d, 0xfffece8d, 0x0, 0x0 - dspck_astio madd, 0xe0000000, 0x00000003, 0xdfffffff, 0xfffe0005, 0x0000ffff, 0xfffffffe, 0x0, 0x0 - dspck_astio madd, 0x1c71c71c, 0x71c71c71, 0xdc71c71f, 0x71c71c6c, 0x7fffffff, 0x80000005, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfe46c589, 0x1ffffff7, 0x3e46c5b9, 0x3ffffff0, 0x7ffffffd, 0x0, 0x0 - dspck_astio madd, 0x07ffffff, 0xfffffffe, 0x07fffb9d, 0x800008c3, 0x80000001, 0x000008c5, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x0001e522, 0xfffffec4, 0x8001e799, 0x7fffffff, 0xfffffd89, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x70000000, 0xffffffff, 0x1ffffffe, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0xcccccccc, 0xcccccccc, 0xcccd8069, 0xedb78d54, 0xff81eaa8, 0xfe934fcd, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffffc, 0xf0000000, 0xfffffffc, 0x1ffffffe, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x6d097b42, 0x684bda12, 0x55555555, 0xc71c71c7, 0x0, 0x0 - dspck_astio madd, 0x1fffffff, 0xfffffffe, 0x1fffffff, 0xfffffffe, 0x00000000, 0xfffff8a8, 0x0, 0x0 - dspck_astio madd, 0x00000003, 0xbb182077, 0x00000003, 0x9b18207b, 0xfffffffe, 0x0ffffffe, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0xf0000001, 0x00000000, 0x1ffffffe, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0xfffff0b5, 0xb030a647, 0xfffff0bd, 0x77696d78, 0x00ff00ff, 0x000007cf, 0x0, 0x0 - dspck_astio madd, 0x000b43e4, 0xbf1579a0, 0x000b43e4, 0xbf1579a0, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xf7e01642, 0xc0000007, 0xf7e01633, 0x8000000f, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000004, 0x00000000, 0x00000004, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00000377, 0xfffffe44, 0x49249249, 0x00000c24, 0x0, 0x0 - dspck_astio madd, 0x00000510, 0xd61702cf, 0x40000510, 0xd61702cf, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xff0f4741, 0xffffffff, 0xff0f4741, 0xc0000007, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x55555555, 0x55555555, 0x555555ab, 0xe2bc4ce3, 0xffff5393, 0xff7f7efa, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xc0000003, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x0000000f, 0xfffffc40, 0xc000000f, 0xffffffc0, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x55555555, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0xbfffffdf, 0x8000003f, 0x7fffffff, 0x7fffffc0, 0x0, 0x0 - dspck_astio madd, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xfffffff0, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x3ffffff8, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00d979c9, 0x0000000e, 0x80d97972, 0xffffffe3, 0x80000003, 0x0, 0x0 - dspck_astio madd, 0x66666666, 0x66666666, 0x66666666, 0x25c416af, 0xfffd7135, 0x00001945, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000de7, 0x00000000, 0x00000de7, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffe0, 0x40000000, 0x7fffffe0, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00b2f56e, 0x74d0a918, 0x0165eadd, 0x7ffffff8, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffffe, 0xff86e7b4, 0xfffffffe, 0x80000000, 0x00f23096, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffcc, 0x00000067, 0x7fffffff, 0xffffff98, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xe000000f, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xffffffc0, 0x00000000, 0x000264d6, 0xfffffff6, 0xffffc2b1, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000006, 0x80000000, 0x7fffff87, 0x8000007f, 0xffffffff, 0x0, 0x0 - dspck_astio madd, 0xe0000000, 0x00000003, 0xe0000000, 0x00000003, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfff9dd70, 0x000013e3, 0x6db097b8, 0x00002e68, 0x6db6db6d, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffc337e0, 0x0, 0x0 - dspck_astio madd, 0xffffff8a, 0xb1dbee92, 0x14e5e031, 0xcbfb4763, 0x49249249, 0x49249249, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80189cfa, 0x00000000, 0x80000000, 0xffcec60c, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x0000001f, 0xfffff1d0, 0x9001c60d, 0x0001c5ee, 0xf8000001, 0x0, 0x0 - dspck_astio madd, 0x3fffffff, 0xfffffff8, 0x31c71c72, 0x51c71c69, 0x71c71c71, 0xe0000001, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xf0000001, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x66666666, 0x66666666, 0x6665175d, 0xa7037280, 0xe000000f, 0x000a7846, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffff80, 0x40000000, 0x7fffff80, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0xffed92d5, 0x26c0d3b4, 0xffed92d7, 0x26c0d3a4, 0xfffffffc, 0x80000004, 0x0, 0x0 - dspck_astio madd, 0xb6db6db6, 0xdb6db6db, 0xb5fd1671, 0x56ce710c, 0xf8000003, 0x1bcae8bb, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7ffd67f5, 0x20914260, 0x0014c057, 0xe0000007, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xfffffff0, 0x80000000, 0x00000ef4, 0xffffffc2, 0xffffffc2, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xffffd836, 0xffffffff, 0xffffd836, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffffb, 0xffffffff, 0xfffffffb, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000b35, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x10495344, 0x00004092, 0x00004092, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x0dea8be3, 0xf64221a7, 0x485dc1f9, 0x80000003, 0x137bbcb2, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x0003b4f0, 0xfffc4b10, 0xffffffff, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xfffffffb, 0x7fffffff, 0xfffffffb, 0x7ffffff0, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7ffffff9, 0x9999999f, 0x66666666, 0xfffffff0, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffe35, 0xffffffff, 0xfffffe35, 0x0000000f, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x40000002, 0xfffffffa, 0x80000005, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x20131c81, 0xf0000007, 0xc0131c72, 0x7fffffff, 0xe000000f, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x7fffffc0, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xfffffffe, 0xb91de955, 0xfda564af, 0xd55d3109, 0x04b5369e, 0x80000006, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0000007, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x0000000f, 0x00000000, 0x0000000f, 0x80000006, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x83c3c3c3, 0x9696968f, 0xc0000007, 0xf0f0f0f0, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000002, 0x80000000, 0x00000002, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0xfffba51e, 0xa536ddaa, 0xfffba51e, 0xa536ddaa, 0x00000000, 0x0001fe81, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x7122641e, 0xe0000009, 0xf12263a6, 0x7ffffff8, 0xc000000f, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffffc0, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x0000000f, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffd2, 0x800001c6, 0xffffffa5, 0x7ffffffb, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x7fee5e4e, 0x15fdf021, 0xf85292d9, 0x024bea89, 0x0, 0x0 - dspck_astio madd, 0x000413bb, 0xafb8c6ab, 0xfc0413bd, 0x2fb8c68b, 0xf8000001, 0x7fffffe0, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xffffffe0, 0xffa48a28, 0x48038e52, 0xf0000007, 0x05b75d7e, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x03fffffe, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00082bdd, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x80000000, 0x7fffffff, 0xffffffff, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x000495dd, 0xff33514e, 0xaa48e92f, 0x01cc890f, 0x8e38e38e, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x027ea0a2, 0x40000000, 0x027ea0a2, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x80000002, 0x7ffffffa, 0x00000005, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0xbfffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x000346f7, 0xfffffffb, 0xffff5835, 0x0, 0x0 - dspck_astio madd, 0x0001d19f, 0x20a5fa03, 0x0001bb81, 0xa0a5fa03, 0x80000000, 0x00002c3b, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00075530, 0x3fffffff, 0x00075531, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0xffff1b9a, 0xdbaf3253, 0x0786a322, 0xdbaf3253, 0x80000000, 0xf0f0f0f0, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000007, 0x3fffff80, 0x00004007, 0x7fffff80, 0x7fffff80, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xff594f8c, 0xffffffff, 0xff595772, 0x00000006, 0x00000151, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7e000000, 0x83fffffe, 0x7fffffff, 0xfc000001, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000001, 0x00000000, 0x003aeaea, 0x000007ad, 0x000007ad, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffffb, 0xfd3751a3, 0x05915cb5, 0x7fffffff, 0xfa6ea346, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffede, 0xffffffda, 0x7ffffede, 0x0000004b, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0xfffffffd, 0xf69575c2, 0xfffffffe, 0x674ff42a, 0x00000007, 0x101aa458, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x0014939f, 0x00000000, 0x0014939f, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xfffffffd, 0x9e51cf8b, 0xffffffff, 0x9e51cf87, 0x00000004, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0xc0000000, 0x00000003, 0xc0000000, 0x00000003, 0x00000000, 0xffffd631, 0x0, 0x0 - dspck_astio madd, 0xf0000000, 0x00000001, 0xe8000000, 0x90000000, 0xf0000001, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000003, 0x80000000, 0x00000003, 0x00000000, 0x3fffffe0, 0x0, 0x0 - dspck_astio madd, 0x0003252e, 0xb69f700c, 0xffcf1701, 0x369f700c, 0x80000000, 0x00681c5b, 0x0, 0x0 - dspck_astio madd, 0xfc000000, 0x00000001, 0xfc000000, 0x03a4590f, 0x00001086, 0x0000386d, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfff9d117, 0xfffff3d2, 0xfff9d117, 0x80000000, 0x0000185a, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x000c90be, 0x03fffffe, 0x800c90be, 0xf8000003, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1c71c71c, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x1fffffff, 0xfffffffe, 0x2ffffff7, 0xe0000049, 0x80000005, 0xe000000f, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xffffff7a, 0x00000000, 0x0147c9ba, 0xffeb835c, 0xfffffff0, 0x0, 0x0 - dspck_astio madd, 0x07ffffff, 0xfffffffc, 0xc8000000, 0x7ffffffc, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xfffffffc, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x00000022, 0xfb3ca75c, 0x00000022, 0xfb3ca76c, 0xfffffffc, 0xfffffffc, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xfee5d86b, 0x0, 0x0 - dspck_astio madd, 0xdb6db6db, 0x6db6db6d, 0xdb6db6dd, 0x6db6db69, 0x7fffffff, 0x00000004, 0x0, 0x0 - dspck_astio madd, 0x0000d2c7, 0x86b4a129, 0x0400d2c5, 0x96b4a13e, 0xc0000003, 0xf0000007, 0x0, 0x0 - dspck_astio madd, 0x0c51f874, 0xb4db6b7a, 0x0c51f874, 0xb4db6b7a, 0x00000000, 0xffffffe7, 0x0, 0x0 - dspck_astio madd, 0xffff0000, 0xffff0000, 0xffff0000, 0xffff0000, 0x07fffffc, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x3fffffe0, 0x0, 0x0 - dspck_astio madd, 0x8e38e38e, 0x38e38e38, 0x8e38e38e, 0x38e38e38, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xffffffe0, 0xffffffff, 0xff45a550, 0x00000008, 0xffe8b4ae, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xffffffea, 0xf73d2fb4, 0xffffffea, 0xf73d1bcc, 0xffffffc8, 0x0000005b, 0x0, 0x0 - dspck_astio madd, 0xffffffeb, 0x762f3464, 0xffffffec, 0xf62f3464, 0xfffffffd, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x0000ffff, 0x0000ffff, 0xe001000f, 0x0000ffff, 0x3fffffe0, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0xff00ff00, 0xff00ff00, 0xff026364, 0xff00ff00, 0x80000000, 0xfffd3738, 0x0, 0x0 - dspck_astio madd, 0xffffffce, 0xc7ddbb22, 0xffffffce, 0xc7ddbb46, 0x00000003, 0x0000000c, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x000006ca, 0x00000000, 0x000006ca, 0xfda11f82, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x80001003, 0xffffffff, 0x80000000, 0xffffdff8, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x001379ca, 0xfffffff0, 0x001379ea, 0x7fffffff, 0xffffffe0, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000005, 0x3fffffff, 0x00000006, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0xcccccccc, 0xcccccccc, 0xcccccd3b, 0x4ccccccc, 0xffffff23, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffffb, 0x00000000, 0x17fffff5, 0x07fffffe, 0x00000003, 0x0, 0x0 - dspck_astio madd, 0x0020d5bf, 0xfe09927b, 0x001d41ff, 0xbf72ee88, 0x14f7a245, 0xffd45329, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0xffffffff, 0xfffffa4a, 0x000002db, 0xfffffffe, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffffe, 0xfff00ff0, 0x03fc03fe, 0xff00ff00, 0x0ffffffc, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x82830e7e, 0xaf9e3020, 0x7ffffff0, 0x05061cfe, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000005, 0x7fffffff, 0xfffa1e9d, 0xfffffffc, 0x0001785a, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0xfffdda1c, 0x00000000, 0x80000000, 0x00044bc8, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffea89, 0x26f1b437, 0x0005e9fc, 0xfc5edff2, 0x0, 0x0 - dspck_astio madd, 0x0072e0a3, 0x0d292f53, 0x0072e0a3, 0x0d292f53, 0x80000001, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x8e38e38e, 0x38e38e38, 0x8e386b90, 0xb8ea1e15, 0x80000007, 0x0000effb, 0x0, 0x0 - dspck_astio madd, 0x00000001, 0xc69d20d5, 0xffffffe1, 0xc69d2115, 0x7fffffff, 0xffffffc0, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00000149, 0xffffedf4, 0xfffffd6c, 0x80000007, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffd7f, 0x00000000, 0x03c47df7, 0xfffffffc, 0xff0edfe2, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x0000003f, 0x80000000, 0x0000003f, 0x00000000, 0xb6db6db6, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0xffffffff, 0x37f33ab0, 0x0e4a0e18, 0xfffffff2, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffe9300, 0xffffffff, 0xfffe9300, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x40000000, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xffff6db5, 0x2e962822, 0xffff6db4, 0xe57195d8, 0xdb6db6db, 0x00000002, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x7f5df778, 0x8a5368d4, 0xf65bcb0a, 0x10ce51e2, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffbf0, 0x0000001d, 0x1ffff84c, 0x000000e9, 0x1ffffffc, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x60000001, 0xffffffff, 0x80000000, 0x3ffffffc, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xffff4ba1, 0xffffffff, 0xffff4ba1, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x800038fa, 0xc9810771, 0x0078c699, 0x0078c699, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000003, 0x40000000, 0x80000003, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x0000003f, 0xffc00000, 0x1800003d, 0xf8000001, 0x07fffffe, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffcde4dd, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000001, 0x7fffffff, 0xfffec3a5, 0x00001a5d, 0xfffffff4, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xffe8df2a, 0xffffffff, 0xbfe8df2d, 0xc0000003, 0x00000001, 0x0, 0x0 - dspck_astio madd, 0xffffc084, 0xa9d71250, 0x3fffc083, 0xa9d71251, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x00621952, 0x74f665b4, 0xc0621952, 0xf4f665b4, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0xef52071c, 0xa6229407, 0xef52072b, 0xa6229353, 0x80000006, 0xffffffe2, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7ffca15a, 0xb6e8e84b, 0xffe8697b, 0x24924924, 0x0, 0x0 - dspck_astio madd, 0xe0000000, 0x00000007, 0xe0000000, 0x014d9d93, 0x00000016, 0x000f2a12, 0x0, 0x0 - dspck_astio madd, 0x92492492, 0x49249249, 0x925914a2, 0x3726904b, 0x0ffffffe, 0x00ff00ff, 0x0, 0x0 - dspck_astio madd, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x3ffffffe, 0x00000003, 0x7ffffffd, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x7fff1876, 0x00000000, 0x0001cf14, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x24924924, 0x92492492, 0x24924924, 0x91d7ac8b, 0x0016b19b, 0xfffffffb, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000002, 0x00000000, 0x00000002, 0xffffff80, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffe, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x1c71c71c, 0x71c71c71, 0x1c71c71c, 0x71c71c71, 0x3fffffe0, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x000099f4, 0xffffff59, 0xffffff14, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x000be722, 0xc71c71c7, 0x71d30394, 0x8e38e38e, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xff8507a5, 0x00000005, 0xffe767ee, 0x0, 0x0 - dspck_astio madd, 0x07ffffff, 0xfffffffc, 0x07fffffe, 0x38e38e34, 0x8e38e38e, 0x00000004, 0x0, 0x0 - dspck_astio madd, 0xffffffe4, 0x21d6a4a1, 0xffffffe2, 0x6453f3c1, 0xe24c9ee0, 0x0000000f, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0x8107de84, 0xfffffffe, 0x0107de84, 0x80000000, 0x00000003, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffe, 0x00000000, 0xffa16359, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x15317c20, 0x00000000, 0x15317c20, 0xffffffcc, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xfffffffb, 0xd6451027, 0xfffffffb, 0xd63833bb, 0xfffffeb1, 0x000009d4, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xf0000000, 0x00000007, 0xf3ffffff, 0x80000007, 0xf8000001, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x00000000, 0x00004990, 0xf8e38e3a, 0x871cbb60, 0xe38e38e3, 0x3ffffff0, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xf98ad94d, 0x000002be, 0xf98ad94d, 0xfffffa82, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xfffffffc, 0x80000000, 0x7fffffec, 0x7ffffff0, 0x00000001, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xfffffff8, 0x800033b9, 0xb7f26246, 0x07ec3057, 0x00068762, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0xaaaaaaaa, 0x2aaaaaaa, 0x55555555, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0xbfffffff, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio madd, 0xe38e38e3, 0x8e38e38e, 0xe38e38e3, 0x8e38e38e, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio madd, 0x00000c9f, 0x004e5a07, 0x00000c9f, 0x004e5a07, 0x0000007f, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0xffffffff, 0xffffffc0, 0xffffffff, 0xffffffc0, 0x00000018, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x7fffffff, 0xffffffff, 0x77733209, 0x7fffffff, 0x80000000, 0x11199bed, 0x0, 0x0 - dspck_astio madd, 0x0002cb5c, 0x75ecc27a, 0x0002cb5c, 0x75ecc27a, 0xffff4350, 0x00000000, 0x0, 0x0 - dspck_astio madd, 0x80000000, 0x00000004, 0x80000016, 0xbfffff4e, 0x3ffffffe, 0x0000005b, 0x0, 0x0 - - writemsg "[14] Test maddu" - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x8f0f0f0e, 0xa5a5a5a5, 0xfffffffa, 0x0f0f0f0f, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0xfffffffd, 0x00000000, 0xfffffffa, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000002, 0x00000002, 0x00000001, 0x0, 0x0 - dspck_astio maddu, 0x8e38e38e, 0x38e38e38, 0x8e38e390, 0x78e38e4d, 0xc0000007, 0x00000003, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xf485f7e8, 0x7fffffdf, 0xf485f7e8, 0x80000000, 0xffffffc0, 0x0, 0x0 - dspck_astio maddu, 0xffffc602, 0x0bedd4a3, 0x7ff8ae5c, 0x0bedd4a3, 0x80000000, 0xfff1d0b4, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xffffff80, 0x012825e2, 0xba0c5d48, 0xffff2bfb, 0x012826d8, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x0000384b, 0xffff1ed0, 0xfffffffc, 0x0000384c, 0x0, 0x0 - dspck_astio maddu, 0xfff8169f, 0xd52b1bbf, 0x7ff7c679, 0xd52bbc09, 0xffff5fb6, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x7ffffff9, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000081, 0x6217888b, 0x03903d05, 0x0000244f, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x1c71c71c, 0x00000000, 0x80000000, 0x38e38e38, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xfffffff9, 0xfffffd75, 0x00001431, 0x7ffffffc, 0xfffffaf2, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffc0, 0x7fffffff, 0xffffffc0, 0x00000000, 0x0c36d40c, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfffffff8, 0x3ffffffe, 0xfffffff9, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0xb5a134d9, 0x722c4676, 0xf22c4676, 0xc0000001, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xffc5d149, 0x000c12ec, 0xffa19882, 0xfffffffd, 0x000c12ed, 0x0, 0x0 - dspck_astio maddu, 0x00670513, 0x80ef3917, 0xf7f447fb, 0x27f9179d, 0xf85cca0f, 0xff2a171a, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xffffffff, 0x00000003, 0xfffffde3, 0xffffff79, 0x00000004, 0x0, 0x0 - dspck_astio maddu, 0x000027ee, 0x118f3a31, 0xfffc0af4, 0x119b9116, 0xfffbe309, 0xfffffffd, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0xb165aeb7, 0x0294ce7a, 0x9cb44f99, 0x02e9dd71, 0xe2ce4602, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000006, 0x4000003e, 0xffffff87, 0x8000007f, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000002, 0x80000000, 0x00000002, 0x00000000, 0x00000057, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00053916, 0xffc402d5, 0x01e5222e, 0xfffffff8, 0xffc402dd, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfffffffe, 0x0000001f, 0x24924913, 0x0000006d, 0x49249249, 0x0, 0x0 - dspck_astio maddu, 0xfffffdaf, 0xac101bf3, 0xbffffdad, 0x6c101bde, 0xfffffff9, 0xc0000003, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfffff5d7, 0x67ddd503, 0xb0444bce, 0x7fffffff, 0xcfbbaa09, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0xfe000000, 0x7fffffff, 0xfc000001, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x007cf5fa, 0x1dc4965b, 0x047cf5f9, 0x1dc4966b, 0x1ffffffc, 0x1ffffffc, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x55555555, 0x55555555, 0x55724881, 0x53f9ef45, 0x0039e658, 0x7ffffffa, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x09e7be3a, 0x37ffffe4, 0xc9e7bdda, 0xe0000003, 0x3fffffe0, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffe, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x000001fe, 0xef21c306, 0x800001f6, 0x6f21c30e, 0xffffffff, 0x7ffffff8, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000063, 0x3fffffff, 0x80000063, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x0fffffff, 0xfffffffe, 0x10000000, 0xefffff86, 0x0ffffff8, 0x0000000f, 0x0, 0x0 - dspck_astio maddu, 0x92492492, 0x49249249, 0x92492492, 0x49249249, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x1fffffff, 0xfffffff0, 0x5fffffff, 0xfffffff0, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xfffffffd, 0x00000006, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x0000001f, 0xbffffffe, 0x80000021, 0x7ffffffe, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x999989af, 0x9999a983, 0x99999999, 0xffffe57b, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xfffedf3f, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x800007ff, 0xf7fe0002, 0x0000ffff, 0x07fffffe, 0x0, 0x0 - dspck_astio maddu, 0xfc000000, 0x00000001, 0x7be65c19, 0x003347cd, 0xffccb834, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0xffffff91, 0x4b79b6c1, 0x1fffff8b, 0x2b79b705, 0xffffffef, 0x1ffffffc, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xffffffe0, 0x7ffe4028, 0x800dfe7c, 0xfffc8059, 0x7ffffffc, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x03ab636c, 0x6b5d12dc, 0xf8000003, 0x03c9b0f4, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x001558b0, 0x3fffffff, 0x001558b1, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0xffffc57f, 0x000074ff, 0x7fffffff, 0xffff8b00, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x55555555, 0x55555555, 0x55555555, 0x5555558d, 0x00000002, 0x0000001c, 0x0, 0x0 - dspck_astio maddu, 0xfffffeef, 0x6427edf8, 0xfffffeef, 0x6427edf8, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x0000001f, 0x4fe76e2a, 0x0000001f, 0x4fe76e2a, 0x00001306, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfe171397, 0xffffffff, 0xfe171397, 0xfffffffd, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xffffffe0, 0x07fffffa, 0x000000e0, 0x7fffffe0, 0x0ffffff8, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000005, 0x80000000, 0x00000005, 0x00000000, 0x00d1f23e, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000005, 0x0000007a, 0xfffffc0d, 0x8000007f, 0xfffffff8, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00000243, 0xfffffb78, 0x7fffffff, 0x00000488, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xf7536e34, 0x7fffffa9, 0x775370c8, 0xffffff5b, 0x7ffffffc, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x0019d51c, 0x0, 0x0 - dspck_astio maddu, 0x1fffffff, 0xfffffff8, 0x6000001f, 0x7ffffff8, 0x80000000, 0x8000003f, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x0000007f, 0x80000000, 0x000000d3, 0x00000015, 0x00000004, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0xedb6db6c, 0xa4924925, 0xdb6db6db, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x000000f8, 0x328b14f1, 0x2aaaaba2, 0xb28b14f1, 0x55555555, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x0fffffff, 0xfffffffc, 0x4fffffff, 0x7ffffffc, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80000015, 0x1c71c6c7, 0x38e38e38, 0x0000005f, 0x0, 0x0 - dspck_astio maddu, 0xffff0000, 0xffff0000, 0x3fff0000, 0x7fff0000, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x003eedcb, 0x8399f5aa, 0x003eedcb, 0x8399f5aa, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x0000007f, 0xf8000003, 0x8000007f, 0xf0000007, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000007, 0xff6dd515, 0x812455da, 0xfedbaa2d, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x8f0f0f0b, 0x3c3c3c40, 0x0ffffffc, 0xf0f0f0f0, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000004, 0xb6db6d5a, 0x92492504, 0xffffff80, 0xb6db6db6, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xfffffffc, 0xfffdfcd0, 0x0004065a, 0xfffbf9a2, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x38e38e38, 0xe38e38e3, 0x38e391b4, 0xe388c723, 0xfffffe70, 0x0000037c, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x78100001, 0xf8000000, 0xfc000001, 0xfc000001, 0x0, 0x0 - dspck_astio maddu, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x7ffffffe, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000024, 0xc0000019, 0xbfffff4b, 0xfffffff9, 0xc000001f, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x8000003f, 0x80000000, 0x0000007f, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x1fffffff, 0xfffffff8, 0x256ad256, 0x7ffffff8, 0x80000000, 0x0ad5a4ad, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x38e38e38, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x85a7353d, 0xd2c65610, 0xfffffff8, 0x05a7353e, 0x0, 0x0 - dspck_astio maddu, 0x92492492, 0x49249249, 0x9249249a, 0x09249059, 0x0000001f, 0x3ffffff0, 0x0, 0x0 - dspck_astio maddu, 0xffffac83, 0x13403e4f, 0xffffac83, 0x13403e4f, 0x00000000, 0xfffff96f, 0x0, 0x0 - dspck_astio maddu, 0x00000016, 0x288440c6, 0x40000016, 0x288440c6, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x0000000e, 0xd0ad2f8f, 0x0000000f, 0xfcd85881, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000007, 0x6cb5f2b1, 0x818d590f, 0x8000003f, 0xd96be4f8, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000005, 0x00000000, 0x00000005, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x80000000, 0xfffffffc, 0xfffffffe, 0x80000002, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x0000000b, 0x0007f5dc, 0x8000000b, 0x80000000, 0x000febb9, 0x0, 0x0 - dspck_astio maddu, 0xf0000000, 0x00000003, 0xf0000000, 0x00000003, 0x00000000, 0x80000001, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x8150cfff, 0x1eaa8726, 0xfffffd0d, 0x0150d003, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000299, 0x0, 0x0 - dspck_astio maddu, 0x00000014, 0x9ae8eb85, 0x24924939, 0xf656a260, 0x80000003, 0x49249249, 0x0, 0x0 - dspck_astio maddu, 0xfffe40ab, 0x2cbb3242, 0x0ffe40a3, 0x0cbb3252, 0xfffffffe, 0x0ffffff8, 0x0, 0x0 - dspck_astio maddu, 0xc0000000, 0x00000007, 0xc0000000, 0x00000007, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000001, 0x7fff447e, 0x80000001, 0x80000000, 0xfffe88fd, 0x0, 0x0 - dspck_astio maddu, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1c71c71c, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0002cd56, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80000001, 0xfffffff1, 0x00000002, 0xfffffff9, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xfffffffc, 0x871c71c3, 0x81c71c74, 0x71c71c71, 0x0ffffff8, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000007, 0x7fffffcf, 0x80000066, 0x7fffffff, 0xffffffa1, 0x0, 0x0 - dspck_astio maddu, 0xaaaaaaaa, 0xaaaaaaaa, 0xa6aaa82d, 0xcaaaa822, 0xfc000001, 0xfffffd78, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80000000, 0x13fffff5, 0x00000005, 0x03fffffe, 0x0, 0x0 - dspck_astio maddu, 0xff9edb1e, 0x08c07004, 0x009d8e06, 0xd0f88652, 0xffb19bb2, 0x00ff00ff, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x9ffffff0, 0x000001ff, 0x7fffffe0, 0x3ffffff0, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x818282c8, 0x5d9bac70, 0x03050590, 0x8000001f, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x38e38e38, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000589, 0x00000002, 0x000002c5, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xf2760d6d, 0xc71c7021, 0x643d2a1b, 0xc71c71c7, 0xfffffde2, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfffffff7, 0x3fffffff, 0xfffffff7, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0xfffff4f2, 0xbe4f2c0a, 0x38e3832b, 0x3e4f2c0a, 0x71c71c71, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xffffffff, 0x7fffec1b, 0xffff38e5, 0x80000005, 0xffffd82e, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0xf0000000, 0x00000007, 0xf0000000, 0x00000007, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00010387, 0x7ffdf8f1, 0x0002070f, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000003, 0x00000000, 0x00000003, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00004efc, 0x7ffffff9, 0x80004f07, 0x7fffffff, 0xfffffff5, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x7e000000, 0x80000000, 0xfc000001, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffe0, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00010d4d, 0x01c71c71, 0x4e39f0dd, 0x0ffffffc, 0x1c71c71c, 0x0, 0x0 - dspck_astio maddu, 0x0000064d, 0xc5646196, 0x800004fd, 0x456456f2, 0xfffffd57, 0x80000004, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfffe758e, 0xffffffff, 0xfffe758e, 0x00000000, 0xfffffffb, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x04c74fae, 0x33333331, 0x6b2db616, 0xfffffff8, 0x33333333, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0xe0000001, 0xbfffffd6, 0xfffffffa, 0xe0000007, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1ffffff8, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0xf0000000, 0x00000001, 0x6ffffb95, 0x80000001, 0x80000000, 0xfffff72b, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000002, 0x00000000, 0x00000002, 0x00000000, 0xfffffd32, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x83fffffe, 0xffffffff, 0x07fffffe, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0xf8000000, 0x00000001, 0xe8f0f0b3, 0xc3c3c401, 0xf0f0f0f0, 0xffffffc0, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000001, 0x1c71c718, 0x0000000a, 0x1c71c71c, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x0000000f, 0x80d05620, 0x762e6c85, 0x00d05632, 0xffffea73, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xf01a2f3a, 0x70000007, 0x701a2f3a, 0x80000000, 0xe000000f, 0x0, 0x0 - dspck_astio maddu, 0x0006a63e, 0xec0d609e, 0x0006a63e, 0xec0d609e, 0x00000000, 0x00000006, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x84dba689, 0xf648b2ec, 0x04dba68a, 0xfffffffe, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xffff88cd, 0x3fffffdf, 0xffff88cd, 0x7fffffc0, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x07fffffe, 0x0, 0x0 - dspck_astio maddu, 0xf0000000, 0x00000007, 0x0ffffff4, 0x00000107, 0x7ffffff0, 0x3ffffff0, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0xbfffffff, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x188fc626, 0x7ffe35df, 0x98935a65, 0xfffc6bc1, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x7f83f0b4, 0x02e85ba4, 0xfffffffa, 0xff83f0ba, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x0000000e, 0x00000000, 0x80000000, 0x0000001c, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfffb1ef8, 0xffffffff, 0xfffb2072, 0x0000003f, 0x00000006, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000003, 0xc0000000, 0x00000003, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfffffffe, 0x40000006, 0xffffffef, 0x7fffffff, 0x8000000f, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x0008246c, 0x00000000, 0x0008246c, 0x00000000, 0xfffffff8, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x007f807f, 0x7f00ff01, 0x7fffffff, 0x00ff00ff, 0x0, 0x0 - dspck_astio maddu, 0x71c71c71, 0xc71c71c7, 0xf1c39a3d, 0xc723762d, 0xfff8fb9a, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xfffffffa, 0x80000002, 0x94f8b209, 0x0000003f, 0x0a7dda31, 0x0, 0x0 - dspck_astio maddu, 0x1fffffff, 0xfffffff8, 0x2000002f, 0x400003a9, 0x0000003f, 0xc000000f, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0xff807f80, 0x00000000, 0x80000000, 0xff00ff00, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xfffffffc, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x0000007b, 0x7fffff09, 0x7fffffff, 0x000000f7, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfffc2ba3, 0xffffffff, 0xfffc99a4, 0x0000003f, 0x000001bf, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x5ffffff8, 0xffffff8f, 0xe0000007, 0xfffffff0, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x0000007f, 0x800000ea, 0x4fffc5eb, 0x07fffffe, 0x00001d4a, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000003, 0x26666653, 0x0ccccce3, 0x3fffffe0, 0x99999999, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xc71c71c7, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x0000007f, 0xffffcf89, 0x7ffd59a2, 0xffff9f05, 0x80000007, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80000000, 0x954e660f, 0x00000d84, 0x000b0c04, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00009813, 0x00000000, 0x00009813, 0x00000000, 0x8000000f, 0x0, 0x0 - dspck_astio maddu, 0x1c71c71c, 0x71c71c71, 0x1cf1479b, 0xe9cf1479, 0x7ffffff8, 0x00ff00ff, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x2f91e634, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000131, 0xef746c23, 0xfd53dbd9, 0xef747747, 0xfffff418, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x8000000b, 0x400001d1, 0x0000000f, 0xc000001f, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x013d4de2, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffe0, 0xbfffffff, 0x7fffffe0, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7ffffefc, 0x000003ff, 0xffffff00, 0xfffffffc, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00193438, 0xfd25158b, 0xffffffe3, 0x00193439, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xf8550280, 0x0ffffffb, 0xd8550090, 0x1ffffff0, 0x8000001f, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x89172bed, 0xffffffa0, 0x89172ead, 0xffffffa8, 0xfffffff8, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00ce6f01, 0x00000005, 0x00ce6ef7, 0x7fffffff, 0x0000000a, 0x0, 0x0 - dspck_astio maddu, 0xaaaaaaaa, 0xaaaaaaaa, 0x8aaaaa8f, 0xaaaaaa8a, 0xe0000001, 0xffffffe0, 0x0, 0x0 - dspck_astio maddu, 0x0fffffff, 0xfffffff8, 0x0ffffff8, 0x00000004, 0xfffffffe, 0xfffffffa, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x0000007f, 0x0, 0x0 - dspck_astio maddu, 0x09e9a721, 0x9b487a5c, 0x08eaa620, 0x9c477b5c, 0xff00ff00, 0xffffffff, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xffffff21, 0xffffffff, 0xffffff21, 0xc0000001, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x0000015c, 0xffee2d59, 0x4af0f94b, 0xffffed5b, 0xffee3ffd, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xfffffff8, 0x7fffffff, 0xfffffff8, 0x1ffffffe, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000007, 0x80000000, 0x00000007, 0x00000000, 0x38e38e38, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000005, 0xd42fd82f, 0x00000035, 0x1c278b53, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfff115b6, 0x0059de97, 0x38c7cd47, 0x00738be7, 0xc71c71c7, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x7ffffff9, 0x80000000, 0xfffffff3, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x06cfe542, 0x071c71c5, 0x3fb37382, 0x38e38e38, 0x1ffffff8, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x1b41447d, 0x01d126b3, 0x0000000f, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0xfffffc3e, 0x00000782, 0xfffff87e, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0xfffac4fc, 0x89ac2465, 0x0004c00f, 0xdb90136d, 0xffffd4e8, 0x0009fb15, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000007, 0x00000000, 0x80000000, 0x0000000e, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000007, 0x3be51184, 0x00000024, 0x33710799, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x000078f7, 0x006f346e, 0xe4e72317, 0x09923530, 0x0b9e6896, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x009b80a3, 0x0, 0x0 - dspck_astio maddu, 0x6db6db6d, 0xb6db6db6, 0x34d1da6a, 0x61864d59, 0xfffe2345, 0xc71c71c7, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x3ffffff4, 0x3fffff50, 0xc0000007, 0xffffffe7, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00001c17, 0x00051873, 0xf9619ebb, 0x0241e01a, 0x0241e01a, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x36bd3d24, 0x71c71ba6, 0x8c1293dc, 0xfffffe38, 0x71c71c71, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80000006, 0xf0981053, 0x0091369b, 0x00000c3c, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xffff0767, 0x0000016a, 0x7fff0767, 0x000002d5, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000005, 0x12492491, 0x2492492d, 0x7ffffffa, 0x24924924, 0x0, 0x0 - dspck_astio maddu, 0xffffff2f, 0xfa69e3a1, 0x3fffff2f, 0xfa69e3a1, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x028c52e8, 0x00000000, 0x028c52e8, 0x0007084a, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0xe0000000, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0x80000007, 0x0, 0x0 - dspck_astio maddu, 0x00000046, 0xee62b809, 0x70000047, 0x6e62b809, 0x80000000, 0xe0000001, 0x0, 0x0 - dspck_astio maddu, 0x8e38e38e, 0x38e38e38, 0x8e38e48d, 0x38e2d2f4, 0x000000ff, 0xffffff44, 0x0, 0x0 - dspck_astio maddu, 0x92492492, 0x49249249, 0x92492492, 0x49249249, 0xfffffc15, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x1c71c71c, 0x71c71c71, 0xd849e8ec, 0x2c3c9eda, 0xfa758269, 0xc0000001, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x0000001f, 0xffffff7e, 0x8000019f, 0xfffffffd, 0x7fffff80, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffe0, 0x7fffffff, 0xffffffe0, 0x00000000, 0x000ce333, 0x0, 0x0 - dspck_astio maddu, 0x0d8fbb41, 0x1c73dc5d, 0x8d72bf59, 0x1cadd42b, 0x7fffffff, 0xffc60832, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7ffffffb, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xffdcb2ba, 0x000000a5, 0xfb1f0932, 0xfff8b054, 0x000000a6, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0xfc000001, 0x80000000, 0x80000000, 0xf8000003, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80060038, 0x7ff3ff8e, 0x000c0071, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x3fffffe0, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x800000eb, 0x165494e0, 0x000007fb, 0x1d7533d3, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x87ffffff, 0x00000000, 0x0ffffffe, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x0000185d, 0x77927fa7, 0x0000185d, 0x77927fa7, 0x07fffffe, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000001, 0x80000000, 0x00000001, 0x0000778b, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0xbfffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffff00, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x8000562c, 0x7fffffff, 0x80000000, 0x0000ac59, 0x0, 0x0 - dspck_astio maddu, 0x7fffffff, 0xffffffff, 0x80001e96, 0xffe2f6aa, 0x00001e97, 0xffffff0d, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0xa6666666, 0xd9999999, 0xc0000003, 0x33333333, 0x0, 0x0 - dspck_astio maddu, 0x1fffffff, 0xfffffff8, 0x5fffffff, 0x7ffffff8, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xffffff00, 0x00000098, 0xfffffe67, 0x000000ff, 0x99999999, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0xef1f79f1, 0x49738e4d, 0xff10820b, 0xf0000007, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000000, 0x0001df85, 0x00000000, 0x80000000, 0x0003bf0a, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0xb8e38e38, 0x80000000, 0x80000000, 0x71c71c71, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfffffffe, 0xffe36072, 0x03217076, 0xffe3608e, 0xffffffe4, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000003, 0x80000000, 0x80000002, 0x7fffffff, 0x00000001, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfff91d9f, 0x7ffffffe, 0xfff91d9f, 0xfffffffe, 0x80000000, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x800011db, 0xfae22060, 0x000011dc, 0xffffb6a8, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0x5e860602, 0xffffffff, 0x5e8cc489, 0x000000fd, 0x000006d3, 0x0, 0x0 - dspck_astio maddu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio maddu, 0x00000000, 0x00000155, 0x3ffffffe, 0x80000155, 0x80000000, 0x7ffffffd, 0x0, 0x0 - dspck_astio maddu, 0x0000d6fa, 0x92c7d6ba, 0x002cd92c, 0x1377df80, 0x00580463, 0x80000002, 0x0, 0x0 - dspck_astio maddu, 0xffffca4e, 0xdb17acf9, 0x7fffc9f8, 0x5b17af8d, 0xffffff5b, 0x7ffffffc, 0x0, 0x0 - dspck_astio maddu, 0xffffffff, 0xfffffffd, 0xffffffff, 0xfffffffd, 0x00000000, 0x0ffffffc, 0x0, 0x0 - - writemsg "[15] Test msub" - dspck_astio msub, 0x7fffffff, 0xfffffff9, 0x40000000, 0xfffffff8, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x0fffffff, 0xfffffffc, 0x10001354, 0xffffd952, 0xffffd956, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x7fffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x1fffffff, 0xfffffffe, 0x1fffffff, 0xfffffffe, 0x00000000, 0x8000007f, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0xffffffc0, 0x400003fc, 0x3ffffffc, 0x000000ff, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfffffdc7, 0xfffffffe, 0x7ffffdc7, 0x80000000, 0xfffffffd, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7ffffffb, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0000064f, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x000100e4, 0xfffdfe36, 0xfffdfe36, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xfffffff0, 0x800022b5, 0x7fffba85, 0x7fffffff, 0xffffba95, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfffffff3, 0x0000003a, 0xfffffff3, 0x80000000, 0x00000076, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffffe89, 0x0ba42fce, 0x000007cf, 0x3004a7ff, 0x0, 0x0 - dspck_astio msub, 0xcccccccc, 0xcccccccc, 0xccc85c69, 0x4ccccccc, 0xfff71f39, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffe, 0x0000ffff, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0xffff0000, 0xffff0000, 0xffff0000, 0xffff0000, 0x00000000, 0x0ffffffe, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x0000000f, 0xffffff77, 0x24924799, 0xdb6db6db, 0xfffffc42, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x7fc9d069, 0x7b17cb50, 0x0ffffff8, 0x0362f96a, 0x0, 0x0 - dspck_astio msub, 0x6db6db6d, 0xb6db6db6, 0x6db6db6d, 0xb6db6db6, 0x00000000, 0xffffe47c, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x80000003, 0xfffffff7, 0xfffffff8, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xff78ed21, 0xffffffff, 0xff78ed21, 0x11ff3312, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x87c8a81d, 0x706eafc4, 0x7fffffff, 0xf06eafc5, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xe0000001, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffffcc6, 0x00000673, 0x7fffffff, 0x00000674, 0x0, 0x0 - dspck_astio msub, 0xf0000000, 0x00000007, 0xb000001f, 0x80000007, 0x8000003f, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfffd15b4, 0x00000004, 0xd7fd13e3, 0x0000009b, 0xf8000003, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0x0000000f, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000a66, 0x7ffeb330, 0xffffeb33, 0x7ffffff0, 0x0, 0x0 - dspck_astio msub, 0x000001bc, 0xeb36bc19, 0x000001d2, 0xeb36bab9, 0x7ffffff8, 0xffffffd4, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00003f07, 0xc0000001, 0x00003f06, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x00000024, 0x11b7df27, 0x00000087, 0x11b7df27, 0x000000c6, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffffff0, 0x0000005f, 0x80000003, 0xffffffe0, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000074, 0x000000c7, 0xfffff8a4, 0x00000190, 0x80000005, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000d09, 0x00246ddb, 0x6d253109, 0xff00ff00, 0x24924924, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0xf1c71c71, 0x80000000, 0xe38e38e3, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00000fef, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xffffc89c, 0xffffffc0, 0x3fffe87c, 0x000000ff, 0x3fffffe0, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x0000007f, 0x6db6db6e, 0xdb6db757, 0x7ffffffa, 0x24924924, 0x0, 0x0 - dspck_astio msub, 0x000006d1, 0x2c0ed11c, 0x000013ce, 0x2c0ec41f, 0xffffd909, 0x55555555, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffff80, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xfffffff8, 0x7fffffff, 0xfffffff8, 0xcccccccc, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x801af064, 0x5543e6e9, 0x06bc1917, 0xfc000001, 0x0, 0x0 - dspck_astio msub, 0xe0000000, 0x00000001, 0xe0000000, 0x00000001, 0x0030397d, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x7ffffffe, 0x80000003, 0x00000003, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffe166a, 0x800f4cab, 0x80000004, 0xfffc2cd5, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x871c71c7, 0x071c71c6, 0x3ffffffe, 0xe38e38e3, 0x0, 0x0 - dspck_astio msub, 0xb6db6db6, 0xdb6db6db, 0xd6db6daf, 0x1b6db6ea, 0xc000000f, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0xff00ff00, 0xff00ff00, 0xff011176, 0x7f00ff00, 0x80000000, 0x000024eb, 0x0, 0x0 - dspck_astio msub, 0x000a3ed2, 0xb6e3cbee, 0x000a3ed2, 0xb6e3cbee, 0xfffff9a0, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x000000ff, 0x00000008, 0x000000ef, 0x7fffffff, 0xfffffff0, 0x0, 0x0 - dspck_astio msub, 0xb6db6db6, 0xdb6db6db, 0x76db6db9, 0xdb6db6db, 0x80000000, 0x80000006, 0x0, 0x0 - dspck_astio msub, 0x0316d902, 0xa34af328, 0x0316d902, 0xa34af328, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x000011cd, 0x90eda3a7, 0x000011cd, 0x90eda3a7, 0xffffe886, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00007e56, 0x9ed89c04, 0x40007e56, 0x1ed89c04, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x1fffffff, 0xfffffffe, 0x20000000, 0x0002d92e, 0x0000b64c, 0xfffffffc, 0x0, 0x0 - dspck_astio msub, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xffffb77a, 0x00000212, 0x00000023, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0xbffffffb, 0x00000019, 0x7ffffffb, 0x80000005, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xc000001f, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x005ba7e3, 0x00000000, 0x005ba7e3, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x80000003, 0x4bfa8804, 0xfffd37f2, 0x00012f6e, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x000013fb, 0xfffff795, 0x0000467d, 0x7ffffffd, 0x000010d6, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x81ffffff, 0x7c000001, 0xfc000001, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0xc0000000, 0x0000001f, 0xc0000008, 0x0000000f, 0xfffffff0, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0xffffffff, 0xfff42292, 0x00000075, 0x000019f6, 0x0, 0x0 - dspck_astio msub, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0xfffffff8, 0xffffffe0, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xfffffffc, 0x7f650c32, 0x8135e797, 0x0135e79b, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x0000a325, 0x1b6dbc2b, 0x0000a325, 0x1b6dbc2b, 0x00000000, 0x000002fc, 0x0, 0x0 - dspck_astio msub, 0x0263b7c4, 0x3d87f376, 0x0263b7c4, 0x3d87ffc4, 0xffffffff, 0x00000c4e, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0x3afbdbbb, 0x00000001, 0xbafbdbb6, 0x7fffffff, 0xfffffffb, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000c62, 0xfffffffc, 0x80000c69, 0x7fffffff, 0x00000007, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x7fffffff, 0xfffe147a, 0xfffffffe, 0xffff0a3d, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x70000007, 0x7fffffff, 0x80000000, 0xe000000f, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0xffffffff, 0xffffff0d, 0xffffffff, 0xffffff0d, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x80079013, 0xce94fc48, 0x0079013d, 0xf0000003, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffe0, 0x40000001, 0xffffffdd, 0x7ffffffd, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x0000ffff, 0x0000ffff, 0x00014584, 0x0000ffff, 0x80000000, 0x00008b0a, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x000029cb, 0x8b721de9, 0x00708e73, 0xffa0f0cd, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00016105, 0x98d8ef9e, 0xe0016115, 0xd8d8ef7e, 0x7fffffff, 0x3fffffe0, 0x0, 0x0 - dspck_astio msub, 0x0fffffff, 0xfffffffc, 0x0fffffff, 0xfffffffc, 0xfffffff0, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x001f4978, 0xffc16d0e, 0xffc16d0e, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x005ec8cf, 0xe0000000, 0x805ec8cf, 0x80000000, 0xc0000001, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x007f807f, 0x80000000, 0x80000000, 0x00ff00ff, 0x0, 0x0 - dspck_astio msub, 0x06036d31, 0xd4e8c0c4, 0x06036d31, 0xd4732c00, 0xfffffffc, 0xffe29acf, 0x0, 0x0 - dspck_astio msub, 0x00000001, 0xacf931be, 0x00000000, 0xacf931bb, 0xfffffff9, 0xdb6db6db, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0xffffffe0, 0x8000003f, 0x0000003f, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000007, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7ffffff8, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfff83da3, 0x00000000, 0x0057f2e3, 0xffffffc0, 0x00017ed5, 0x0, 0x0 - dspck_astio msub, 0xc0000000, 0x00000001, 0xc0000000, 0x00000001, 0x00000000, 0xfffffff3, 0x0, 0x0 - dspck_astio msub, 0x00000002, 0xb02b83e8, 0x00000002, 0xb02b83e8, 0x00000000, 0x7fffffe0, 0x0, 0x0 - dspck_astio msub, 0xcccccccc, 0xcccccccc, 0xffffffff, 0xe6666665, 0x99999999, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfffff646, 0x00000000, 0xfffff646, 0x00000002, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000001, 0xfffffff2, 0x38e38e52, 0x71c71c71, 0x0000001f, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0xc71c71c7, 0x7ffffff0, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0xffffd375, 0xe706709a, 0xffffd375, 0x0b98b9c2, 0x24924924, 0x00000006, 0x0, 0x0 - dspck_astio msub, 0xffffffed, 0x0cbdc42f, 0xf6db6da4, 0xa82b7b0d, 0xb6db6db6, 0xe0000003, 0x0, 0x0 - dspck_astio msub, 0x00000033, 0x69c5c9e1, 0x00000033, 0x69c5c9e1, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x0000006e, 0x00037120, 0x5e7e8244, 0xf0000007, 0x00371206, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfffffffe, 0xffffffff, 0xff8c0c02, 0xfffffffc, 0xffe30301, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xffffff92, 0x03fffffd, 0xf7ffff96, 0x80000001, 0x07fffffc, 0x0, 0x0 - dspck_astio msub, 0x00000003, 0xc7a8bdc2, 0x40000003, 0x47a8bdc2, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00105539, 0x7fdf558d, 0xffdf558d, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xfffffffd, 0x7ffffff7, 0xfffffffd, 0xfffffff0, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x00000f18, 0x9ad32c8b, 0x00000f1a, 0x9ad32c8b, 0x00000004, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0xf0000000, 0x00000007, 0xdce455ea, 0xa6375432, 0x2637542b, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x66666666, 0x66666666, 0x62666668, 0x6e666662, 0x7fffffff, 0x07fffffc, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x0002ad3e, 0xc0000002, 0x0002ad3a, 0x7ffffffe, 0x7ffffffe, 0x0, 0x0 - dspck_astio msub, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccae6, 0x00000001, 0x000001e6, 0x0, 0x0 - dspck_astio msub, 0x00000005, 0xe272b611, 0x2492492a, 0x994e23c7, 0xb6db6db6, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0xdb6db6db, 0x6db6db6d, 0xdb6db5ef, 0xedb6db6d, 0x80000000, 0xfffffe29, 0x0, 0x0 - dspck_astio msub, 0xf242cc75, 0x02467cd4, 0xf242cc74, 0x82467cd4, 0x80000000, 0xffffffff, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xefeac421, 0x0084d062, 0x0000001f, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x7ffffffc, 0x4924923e, 0xb6db6db6, 0xfffffff3, 0x0, 0x0 - dspck_astio msub, 0xf0000000, 0x00000003, 0xeb01db92, 0x00000003, 0x80000000, 0xf603b724, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x80012949, 0xffffffff, 0x80000000, 0x00025294, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0xffffffff, 0xffffff1f, 0x0000000f, 0x0000000f, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x0000000f, 0x80043b77, 0xfff7891f, 0x7fffffff, 0xfff78910, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x3c291b99, 0x0000003d, 0x3c291b1f, 0xffffff86, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfffff6c2, 0xffffffff, 0xfffff6c2, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffb, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfee0ff36, 0x00000000, 0x6ee0ff05, 0x00000007, 0xf0000007, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0xffffffff, 0xc538de82, 0x00000007, 0x08659712, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfffe43ab, 0x00000000, 0x0ffe43a4, 0x00000001, 0xf0000007, 0x0, 0x0 - dspck_astio msub, 0xfffffd73, 0x39c3f5aa, 0xfffffd73, 0x39c3f5aa, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x0000364b, 0xffffffff, 0xff0f7a3b, 0x00000f84, 0x00000f84, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x0000001f, 0x80000000, 0x0000001f, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0xfff9873f, 0x244a0fed, 0xfff9873f, 0x24414cfd, 0x00008c2f, 0x00000010, 0x0, 0x0 - dspck_astio msub, 0x039dc6dd, 0x7a4758ed, 0x039dc6bd, 0xfa47592c, 0x7fffffff, 0x0000003f, 0x0, 0x0 - dspck_astio msub, 0xfffffff8, 0x3f5ec4f0, 0x0001cdf0, 0xbf5ec4f0, 0x00039bf1, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x00000001, 0x28e115bc, 0xfffffffe, 0x2d393a9c, 0xe822c127, 0xffffffe0, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fff9d05, 0x0062faff, 0x7fffff80, 0x0000c5f6, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x000002e3, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000004, 0xfffffffe, 0x80000010, 0x3ffffffe, 0x00000006, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x0000003f, 0xfffff39d, 0x0000003f, 0x80000000, 0xffffe73a, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0xbffffffe, 0x80000000, 0x7ffffffd, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0xfffe6dbf, 0x5b9a00bd, 0x008379c9, 0xda8fe8a8, 0x7fffffff, 0xfef5e7eb, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfff77cf1, 0x1bcfcca6, 0x4857e3a4, 0x7fffffff, 0xc86066b3, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xfffffffb, 0x7fffffff, 0xfffffffb, 0x0000b239, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00a38021, 0x4abde701, 0xf0a38021, 0xcabde701, 0x80000000, 0xe0000001, 0x0, 0x0 - dspck_astio msub, 0xc0000000, 0x0000001f, 0xc0000000, 0x0000001f, 0x00000000, 0xfffa9d9f, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0xb6db6db6, 0xdb6db6db, 0xb6db6db6, 0xdb6db6db, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000077, 0xfffffff8, 0x0000000f, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xffffffe0, 0x00000000, 0x02d0b311, 0xfff48f71, 0x0000003f, 0x0, 0x0 - dspck_astio msub, 0x33333333, 0x33333333, 0x00000000, 0x99999999, 0x66666666, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfffffffc, 0x3fffffff, 0x7ffffffc, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x8000000f, 0x80000000, 0x80000000, 0x0000001f, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0xffffffff, 0xffffffe4, 0x0000000e, 0x00000002, 0x0, 0x0 - dspck_astio msub, 0xe0000000, 0x00000007, 0xe0000000, 0x00000007, 0x0005cf66, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffffffc, 0xf0f0f0bf, 0xf0f0f0f0, 0xffffffcc, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x8007494b, 0x1fc5b5a7, 0x003a4a59, 0xe0000001, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x001039ca, 0x00000000, 0x001039ca, 0x3ffffff8, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffffbcf, 0xf0004300, 0xffffbcff, 0xf0000001, 0x0, 0x0 - dspck_astio msub, 0x0001b171, 0x4c2f383a, 0x4001b16c, 0x4c2f384a, 0x7ffffff8, 0x80000002, 0x0, 0x0 - dspck_astio msub, 0x00ff00ff, 0x00ff00ff, 0x00feecde, 0x9a984a17, 0xcccccccc, 0xffff9b5e, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x0000000e, 0x00000000, 0x80000000, 0x0000001c, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000f, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000050, 0x9a998ea7, 0x00000050, 0xda59ce67, 0x00ff00ff, 0xffffffc0, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0x1b1536d5, 0xff807f7f, 0x39f655d5, 0xff00ff00, 0x8000001f, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x7f340f68, 0x8197e12f, 0x7fffffff, 0x0197e12f, 0x0, 0x0 - dspck_astio msub, 0xf2b4a4d7, 0x7964e9af, 0xf2b4a4a9, 0xf964e9af, 0xffffffa5, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x871c71c5, 0x5555555b, 0x1c71c71c, 0xc000000f, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfffffffa, 0x00000000, 0x4ec6b0c5, 0x00821b91, 0xffffff65, 0x0, 0x0 - dspck_astio msub, 0xe38e38e3, 0x8e38e38e, 0xe38e38e3, 0x8e3bbb5d, 0xfffffff9, 0x000067f9, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000006, 0x80000000, 0x0069dcef, 0x0000f427, 0xffffff91, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffe2c94, 0x81cfc4a8, 0xfffc5929, 0x8000007f, 0x0, 0x0 - dspck_astio msub, 0xdd77f580, 0x9331e18a, 0xdd37f580, 0xb331e186, 0x07fffffe, 0x07fffffe, 0x0, 0x0 - dspck_astio msub, 0xe38e38e3, 0x8e38e38e, 0xe38e38e3, 0x8e38e38e, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x00000059, 0x2f248d6e, 0x00000059, 0x2f248d6e, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaca, 0xaaaaaa6a, 0xffffffc0, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000f98, 0xfffed780, 0x329b954b, 0xf6449993, 0xffe1889f, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0000007f, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0xe0000000, 0x00000001, 0xe9249248, 0x00000005, 0xc0000007, 0x24924924, 0x0, 0x0 - dspck_astio msub, 0xe1d4841b, 0x83a41544, 0xe1d4841b, 0x83a41544, 0x00000000, 0xfffffffa, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000007, 0x80000000, 0x000796e1, 0xfffff506, 0x000000b1, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000005, 0x3fffffff, 0x80000005, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xffc8ea08, 0xffca3761, 0x00347b46, 0x7fffffff, 0x006b913e, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x80000004, 0x6db6db7a, 0xdb6db6db, 0x0000001f, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xfffffff9, 0x87fffffb, 0xfffffff9, 0x0ffffff8, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x000002c5, 0x3ef67d53, 0xffff1305, 0xbef85cd2, 0x7fffffff, 0x0001df7f, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x01b5373c, 0xfffffffd, 0x0091bd14, 0x0, 0x0 - dspck_astio msub, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000005, 0x7ffffffd, 0x00000005, 0x80000000, 0xfffffffa, 0x0, 0x0 - dspck_astio msub, 0x3fffffff, 0xfffffff0, 0x00000001, 0x7ffffff0, 0x80000003, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0xc71c71c7, 0x1c71c71c, 0xc31c71c9, 0x2c71c714, 0x7ffffffe, 0x07fffffc, 0x0, 0x0 - dspck_astio msub, 0x00000839, 0x19ba9cf0, 0x00000854, 0x99ba9cf0, 0x00000037, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xfffffffa, 0x7ffffff0, 0x80000019, 0x0000001f, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x0000003f, 0x0003e603, 0xfff83437, 0xfff833f8, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xa8c61add, 0xffe2d17d, 0x290077e2, 0x003a5d05, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x0000003f, 0xffff1124, 0x0000003f, 0x80000000, 0xfffe2248, 0x0, 0x0 - dspck_astio msub, 0xfffff17c, 0xe6b637c5, 0x3ffff17c, 0x66b637c5, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x49249249, 0x24924924, 0x4924cd7d, 0xa491d2bb, 0xffff8997, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0xfffffff8, 0xf2102784, 0xfffffffb, 0xf210261c, 0xe000000f, 0x00000018, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x7fffffe0, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x0ffffffd, 0x4000001c, 0x3ffffffc, 0xc0000007, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0x4b830639, 0x0058a1f8, 0x4ad1c247, 0x7fffffff, 0xff4ebc0e, 0x0, 0x0 - dspck_astio msub, 0x0000484f, 0x8556c9da, 0x0000484f, 0x8556c9da, 0xfe4416d8, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfffc5b3b, 0xffffffff, 0xfffc5b3b, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x9ffffffe, 0x00000000, 0x3ffffffc, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0xc0000000, 0x00000007, 0xf333332d, 0x0000000d, 0x8000000f, 0x66666666, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00001c37, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000003, 0xffcdb199, 0x80649cd0, 0x7fffffff, 0x00649ccd, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x000c297f, 0x00000000, 0x4ef5190e, 0x000035e9, 0xfffe8949, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7f442475, 0x45dedc55, 0x3ffffffe, 0x02ef6e2b, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xfffffffa, 0x7fffffff, 0xfffffffa, 0x00000000, 0x005faa47, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0000001f, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x3fffffff, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfffa8dc5, 0x00000005, 0x7ffa8dc5, 0x0000000b, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0xe0000000, 0x00000001, 0xe0000000, 0x00000001, 0x00000000, 0x00000002, 0x0, 0x0 - dspck_astio msub, 0x0fffffff, 0xfffffffc, 0x00000000, 0x7ffffffc, 0xe0000001, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xfe82a28a, 0x000139ba, 0x7e802f15, 0x7fffffff, 0xfffd8c8b, 0x0, 0x0 - dspck_astio msub, 0xc0000000, 0x00000007, 0xe4924924, 0xb6db6dbd, 0x7fffffff, 0xb6db6db6, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x0000003f, 0xffffffff, 0xfffffc7e, 0xffffffe1, 0xffffffe1, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003817, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0x78000004, 0x0ffffff8, 0x0ffffff8, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0xf0000000, 0x00000003, 0xefffd69d, 0x00000003, 0xffffad3a, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ffffce3, 0x11ce68e0, 0xc93b28a5, 0xfffff173, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0xffffff00, 0x1fffffd8, 0x80000680, 0xc000000f, 0x7fffff80, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x0000003f, 0x800003c1, 0xfffc3e3f, 0xfffff87c, 0x7fffff80, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7ea2fc28, 0xce29d0a3, 0x0368899a, 0x66666666, 0x0, 0x0 - dspck_astio msub, 0x00ff00ff, 0x00ff00ff, 0x20ff00fd, 0x40ff0102, 0x7fffffff, 0xc0000003, 0x0, 0x0 - dspck_astio msub, 0xffffffff, 0x0d11f651, 0x1ffffff7, 0x0d11f651, 0x80000000, 0x3ffffff0, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0xffffffff, 0xe0000006, 0xf0000003, 0xfffffffe, 0x0, 0x0 - dspck_astio msub, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0fa3a01, 0x000000c1, 0xfffff3af, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000005, 0x7fe29a0e, 0xc3acbe2d, 0x007597c5, 0x3ffffff8, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000000, 0xbfffffff, 0x00000001, 0x7fffffff, 0x80000001, 0x0, 0x0 - dspck_astio msub, 0xf0000000, 0x00000001, 0xddb6db6d, 0x80000001, 0xdb6db6db, 0x80000000, 0x0, 0x0 - dspck_astio msub, 0xffffff0a, 0x6e28b447, 0xffffff0a, 0x6e28b447, 0x00000000, 0x3ffffffc, 0x0, 0x0 - dspck_astio msub, 0x00000000, 0x00000000, 0xfe38e38e, 0xf71c71cb, 0xf0000007, 0xe38e38e3, 0x0, 0x0 - dspck_astio msub, 0x00000005, 0xe45a1164, 0x00000005, 0xe45560c2, 0xffffffea, 0xffffc96d, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xfffffffc, 0x7ffffffd, 0x20ef7c00, 0xff3686b6, 0xfffffc5a, 0x0, 0x0 - dspck_astio msub, 0xf0000000, 0x00000001, 0xf0000000, 0x00000001, 0xff350964, 0x00000000, 0x0, 0x0 - dspck_astio msub, 0x80000000, 0x00000006, 0x7912cf83, 0x531e45e2, 0x80000006, 0xf2259f06, 0x0, 0x0 - dspck_astio msub, 0xffffffea, 0x7ebf78ed, 0x00001d61, 0x7eb81b2d, 0xffffc512, 0x7fffffe0, 0x0, 0x0 - dspck_astio msub, 0xe0000000, 0x0000000f, 0x1fffffd0, 0x800007cf, 0x8000001f, 0x7fffffc0, 0x0, 0x0 - dspck_astio msub, 0x7fffffff, 0xffffffff, 0x7fffffe4, 0xc71c7233, 0x000000f5, 0x1c71c71c, 0x0, 0x0 - - writemsg "[16] Test msubu" - dspck_astio msubu, 0xffffffff, 0xfffffffe, 0xfffffffe, 0x5000006a, 0x0000001b, 0x0ffffffc, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x40000000, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x61000007, 0x60000018, 0xf8000003, 0x1ffffff8, 0x0, 0x0 - dspck_astio msubu, 0x3fffffff, 0xfffffff8, 0x4033111f, 0xff66cca1, 0xfffffffd, 0xffcceee3, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffff9, 0xfffffc18, 0xfffe1447, 0x8000003f, 0x000007ce, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000006, 0xfffff8ee, 0x000d887a, 0x00000712, 0xfffffe16, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xffffffff, 0x80000004, 0x3ffffffe, 0x00000002, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x000000ff, 0xfffffa5b, 0x01943a30, 0x000005a5, 0xffffb863, 0x0, 0x0 - dspck_astio msubu, 0x0000002d, 0x47f73d6a, 0xc000002d, 0xc7f73d6a, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000003, 0x10000005, 0x9000000a, 0xf0000001, 0xfffffff9, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0024c573, 0xd82d82d8, 0x5b2a75ce, 0xc71c71c7, 0x33333333, 0x0, 0x0 - dspck_astio msubu, 0xc0000000, 0x0000000f, 0xbffffe96, 0x0000044d, 0xfffffffd, 0x0000016a, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0x999999bb, 0x99999978, 0x66666666, 0xffffffac, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffffffdc, 0xffffffff, 0xffffffdc, 0xfffffff0, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x40000000, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0xff00aefd, 0x73c61dca, 0xff00aefd, 0x73c61dca, 0x00000000, 0x71c71c71, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x1c21e374, 0x00078a61, 0x8f65ee53, 0xffffed27, 0xfff88877, 0x0, 0x0 - dspck_astio msubu, 0x1fffffff, 0xfffffffe, 0x1fffffff, 0xfffffffe, 0x7ffffff9, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xfffffffe, 0x7ffffa63, 0xfffffffe, 0x00000b38, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xc0000000, 0xffffffff, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xfffffffa, 0x00000000, 0x0000000c, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00a864d7, 0xffffffff, 0x80a864d8, 0x7fffffff, 0x00000001, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x80f13ad3, 0xb4c73b6a, 0xff0f082b, 0xffffbcc2, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffff8a, 0xbffffc56, 0xe0000007, 0x00000086, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffffff00, 0xffffffff, 0xffffff00, 0x03428034, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x801a9902, 0x752788a0, 0xffe60a0d, 0xffff5ce0, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00006cd1, 0x5ffffffb, 0xc0006cd7, 0xe0000007, 0xb6db6db6, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffff43b, 0xc0000000, 0xfffff43a, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x014f0848, 0x0, 0x0 - dspck_astio msubu, 0xe0000000, 0x0000000f, 0xe0ff0118, 0xe718e70f, 0xff00ff00, 0xffffffe7, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x01b4db37, 0x86cce935, 0x34cc1f37, 0xf2662e88, 0x7fffff80, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00000001, 0xf4f158d0, 0xffffd3eb, 0xa50763f8, 0x0ffffff8, 0x0002c165, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xf8000004, 0x0ffffff8, 0x7fffffff, 0x0ffffff8, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000004, 0x7ff53653, 0x0015935e, 0x7fffffff, 0x0015935a, 0x0, 0x0 - dspck_astio msubu, 0x1fffffff, 0xfffffff8, 0xa0000003, 0xfffffff2, 0x7fffffff, 0xfffffffa, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7cff3c20, 0x01e07a6b, 0x0360dc5c, 0xe38e38e3, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffffff80, 0xff9efe1f, 0x86ae94ae, 0xfffffbf9, 0x006101e2, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xfeee3cb2, 0xf54e5efe, 0x80000005, 0x0223869a, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000047, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0xc0000000, 0x00000003, 0xbffffab0, 0x3fff95c8, 0x00000715, 0xc000000f, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffcd8, 0xffffffff, 0xfffffcd8, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xfffd88ef, 0x7ff623be, 0x0004ee21, 0x80000002, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xffffff14, 0x00000760, 0xfffffff8, 0x000000ec, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xb6db6db7, 0x92492492, 0x92492492, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfff78198, 0xffffffff, 0xfff78198, 0x00000000, 0xffffffd9, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x40000000, 0xffffffff, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xc0000004, 0x7ffffff8, 0x7fffffff, 0x7ffffff8, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x1acdf530, 0x7fffffff, 0x80000000, 0xca64159f, 0x0, 0x0 - dspck_astio msubu, 0x92492492, 0x49249249, 0x8bb90416, 0x437b1bfc, 0xfffcdb13, 0x0690351f, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffffd, 0x7d6343ec, 0x53978299, 0xb6db6db6, 0xb6db6db6, 0x0, 0x0 - dspck_astio msubu, 0xc0000000, 0x0000001f, 0xc0000000, 0x0000001f, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0xffea00a9, 0xf7eb41a7, 0x7fea00a9, 0x77eb41ad, 0x80000002, 0xfffffffd, 0x0, 0x0 - dspck_astio msubu, 0x0b47cc33, 0x3510a0e5, 0x0b47cbb4, 0x3510b4bd, 0xffffffd8, 0x0000007f, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xfffff680, 0x00000980, 0xcccccccc, 0x00000be0, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x0b2a79ab, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xfffd7998, 0x00000000, 0x00050cd0, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0xdb6db6db, 0x6db6db6d, 0xe8954ab2, 0x2bf0f853, 0xf2d86c2e, 0xfffffffb, 0x0, 0x0 - dspck_astio msubu, 0x1fffffff, 0xfffffff0, 0x1ffffe6b, 0x0000031a, 0x0000032a, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x3fffffe0, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x0000002c, 0x8355afca, 0xecb3afa1, 0x32a2bafe, 0xfffffc14, 0x134c50d7, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000005, 0x80000000, 0x00000005, 0x00000000, 0x00000005, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffffe, 0x90000000, 0x5fffffff, 0x7fffffff, 0xe0000001, 0x0, 0x0 - dspck_astio msubu, 0x0000002e, 0x8910ff07, 0x3e88c452, 0x32ed3447, 0xf8bddf40, 0xc71c71c7, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fff8000, 0x807fff7f, 0x0000ffff, 0x7fffff80, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xe0000003, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0000000f, 0x00000000, 0x0000000f, 0x3ffffffc, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00003c56, 0x66ba1b00, 0xfffeb6c9, 0xe4bbb236, 0x03f623ee, 0x00625583, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xfffffffa, 0x05b47cf7, 0xfffffffa, 0x80000000, 0xf4970610, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x03fffffe, 0x7fffffff, 0xf8000003, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffffff9e, 0xffffffff, 0xffffff9e, 0x00000000, 0x80000001, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7d2dc9b2, 0x85a46c9a, 0x7fffffff, 0x05a46c9b, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xf9d26b9a, 0xffffffff, 0xf9d26b9a, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000021, 0x00000000, 0x00000021, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00000002, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0002eabb, 0x00000000, 0x0002eabb, 0x0000052b, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x78787878, 0x7fffffff, 0x80000000, 0x0f0f0f0f, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0000006a, 0x00000000, 0x0000006a, 0x00000000, 0x020d49cd, 0x0, 0x0 - dspck_astio msubu, 0x00000007, 0xe3d2235c, 0x80037b0a, 0x63cb2d59, 0x7fffffff, 0xfff909fd, 0x0, 0x0 - dspck_astio msubu, 0xf0000000, 0x00000007, 0x7000000d, 0xffffffed, 0x7fffffff, 0xffffffe6, 0x0, 0x0 - dspck_astio msubu, 0xf8fd8899, 0x17f7689f, 0x790b6de2, 0x17db9e0f, 0x7fffffff, 0xffe43570, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffe0, 0x7fffffef, 0x5fffff5b, 0xe0000007, 0x00000013, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0000003f, 0x00000000, 0x0000003f, 0xfffc0247, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x037abdc8, 0xffffffce, 0x037b157a, 0x00000032, 0xfffffe3f, 0x0, 0x0 - dspck_astio msubu, 0xffffffa7, 0xc03cb715, 0xffffffa7, 0xc03cb715, 0x7ffffffb, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x49249249, 0x80000000, 0x6db6db6d, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x0000dfb5, 0x3c0a7bea, 0xc000df95, 0xbc0a7bea, 0x80000000, 0x8000003f, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffffffff, 0x80008be1, 0x7ffee83e, 0xfffee83f, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x1c825747, 0x80000004, 0x1c825741, 0xfffffffe, 0x7ffffffd, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffb021, 0x8009fbcf, 0x7ffffff0, 0x00009fbd, 0x0, 0x0 - dspck_astio msubu, 0xedef3c52, 0x66e53cae, 0xedef3c52, 0x66e53cae, 0xfffffaad, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xcccccccc, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0xf1c71c73, 0xaaaaaaa9, 0xfffffffd, 0x8e38e38e, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffbad6, 0x00008a54, 0x00008a54, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x0fffffff, 0xfffffffe, 0x0fffffff, 0xfffffff5, 0x00000003, 0x00000003, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000002, 0xffffffff, 0xffffff29, 0x00000007, 0x0000001f, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffc37c, 0xfff8e8a6, 0x8000000f, 0x00007906, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000001, 0xbfffffff, 0x00000004, 0x80000003, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0xfffe15e3, 0x7cbb8090, 0xfffe15e3, 0x7cbb8090, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xffffff87, 0x25a94cb1, 0x0000007f, 0xf39be531, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xffff540a, 0x1f38cb1c, 0x00759396, 0x01766916, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xfffffffe, 0x7fffffff, 0xfffffffe, 0x8000001f, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfa217d54, 0xc0000000, 0xfa217d53, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xf419bc42, 0xffffffff, 0xf419bc42, 0x00000000, 0x000002df, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000007, 0x7ffffff2, 0x00000025, 0x8000000f, 0xfffffffe, 0x0, 0x0 - dspck_astio msubu, 0xfbb0eec1, 0x328b488a, 0xfbb0ee7d, 0xb28b488a, 0x00000087, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0x800001c8, 0x80000000, 0xfffffc6f, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x1fffffff, 0xfffffff8, 0x1fffffff, 0xfffffff8, 0xf0f0f0f0, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00008301, 0xc0000011, 0x80008285, 0x3ffffffe, 0xffffffc2, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0000003f, 0x00000000, 0x0000003f, 0xfffffa2e, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffc0, 0x38e38e38, 0xffffffc0, 0x80000000, 0x8e38e38e, 0x0, 0x0 - dspck_astio msubu, 0x0000ffff, 0x0000ffff, 0xfc010000, 0x0800fffd, 0x07fffffe, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffffb, 0xffffffff, 0xfffffffb, 0x00000000, 0x00000291, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00001e54, 0xffffef77, 0x1b663fd4, 0x0072a780, 0x0024eb33, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xffe661c3, 0x00ccf1e8, 0x00199e3d, 0xfffffff8, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x7ffffffa, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xf684bda1, 0x5ed097b4, 0x1c71c71c, 0x55555555, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0xfffffffc, 0x00000018, 0x80000006, 0xfffffffc, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0000000f, 0xfffa81d7, 0x800afc60, 0x7fffffff, 0x000afc51, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0x9ffffff0, 0x80000000, 0xc000001f, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffffff, 0x0000516f, 0x00000001, 0xffffae91, 0x0, 0x0 - dspck_astio msubu, 0x000000f8, 0x56399121, 0xfe526437, 0x2d07f221, 0x3fffffe0, 0x06b67308, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00163269, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffff815, 0x0000002d, 0x0000002d, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x40000000, 0x7fffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0000000b, 0xe6666665, 0x199999a6, 0x80000007, 0x33333333, 0x0, 0x0 - dspck_astio msubu, 0xf0000000, 0x00000001, 0xf0000000, 0x00000001, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0eb04dcd, 0x80000003, 0x0eb04dcd, 0xfffffffa, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0x9ebb1b6a, 0x800007f5, 0x1ebb0b81, 0x7fffffff, 0xfffff017, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000007, 0xfc4309df, 0x9439d5d5, 0xfca63823, 0x03c9a726, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffffffc5, 0xc0000000, 0x7fffffc5, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0xfffffffe, 0x61915789, 0xfffffffd, 0x94c48abd, 0xcccccccc, 0x00000001, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0000007f, 0xc0000001, 0x0000007e, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0x80000004, 0x00000000, 0xfffffff8, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xf8000001, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x03ffffff, 0xfffffffe, 0x03fffee9, 0x00000115, 0x00000117, 0xffffffff, 0x0, 0x0 - dspck_astio msubu, 0xf8000000, 0x00000001, 0x7800052a, 0x00000001, 0x80000000, 0xfffff5ac, 0x0, 0x0 - dspck_astio msubu, 0x3fffffff, 0xfffffffc, 0x3fffffff, 0xfffffffc, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0000007f, 0xffafa9bf, 0x4dec9e1f, 0xff982958, 0x005076e4, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000003, 0xff08f708, 0xf700ff04, 0x00ff00ff, 0xf8000001, 0x0, 0x0 - dspck_astio msubu, 0x71c71c71, 0xc71c71c7, 0xf9c71c54, 0x371c71a8, 0xf0000001, 0x8000001f, 0x0, 0x0 - dspck_astio msubu, 0xfffff80f, 0x720bafb1, 0xbffff7ff, 0xf20bafb1, 0x80000000, 0x8000001f, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffffe, 0xffffffea, 0x80000029, 0x7fffffff, 0x0000002b, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x5b6db6db, 0xc9249249, 0x7fffffff, 0x49249249, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00004c2b, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffff0, 0xbfffffff, 0xfffffff0, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffe88, 0xff807f80, 0x80feff87, 0x00ff00ff, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x69fd40e5, 0x02bf3100, 0x2c057e62, 0x7fffff80, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x40000000, 0xfffffffe, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x3fffffff, 0xffffffff, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x40000000, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0xffff7e92, 0xa1fd60f7, 0xffff7e92, 0xa1fd60f7, 0xfffffd0e, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x0fffffff, 0xfffffff8, 0x901ded6e, 0xfffffff8, 0xffc42522, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xf0000008, 0x1ffffff0, 0x7fffffff, 0x1ffffff0, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000007, 0x80000000, 0x00000007, 0x00000000, 0xc0000007, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000005, 0x00000000, 0x00000005, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffffff00, 0x82d2f0f4, 0xfa5a1d18, 0x7fffffff, 0xfa5a1e18, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffffffe0, 0xffffffff, 0xffffffe0, 0x00000000, 0xc0000003, 0x0, 0x0 - dspck_astio msubu, 0x0000ffff, 0x0000ffff, 0x3c00fff9, 0xc000fff6, 0xe0000003, 0xe0000003, 0x0, 0x0 - dspck_astio msubu, 0x1fffffff, 0xfffffff8, 0x1e000001, 0x03fffff6, 0x7fffffff, 0x03fffffe, 0x0, 0x0 - dspck_astio msubu, 0x07ffffff, 0xfffffffc, 0x0d10b78f, 0x84179a4c, 0xfaef7446, 0xffffd348, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x7ffda82e, 0xaf39f01f, 0x00026b1b, 0xf80644b3, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x1c26803b, 0xfffffff5, 0xe342f214, 0x00000017, 0x71c71c71, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffd1d, 0x00087aa1, 0x52b385fb, 0xffff4463, 0xfff840f6, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00062960, 0x142d3efc, 0x00062783, 0x5f5768c0, 0x0e0fa864, 0x000021e7, 0x0, 0x0 - dspck_astio msubu, 0x2dc9effb, 0x5078e410, 0xedc9effb, 0xd078e410, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x24924924, 0x92492492, 0xa49670c7, 0x12492492, 0x80000000, 0xfff7b0bb, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffffff00, 0xffffb5d7, 0xffffff00, 0x00009450, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x40000000, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x01de74e5, 0xffffff3d, 0x01de75a8, 0xffffffff, 0x000000c3, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffff9, 0xc0000034, 0xbffffe63, 0xffffff35, 0x3ffffffe, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000006, 0x80000000, 0x00000006, 0x00000000, 0x0040f4c3, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffa1f46, 0x00982f95, 0xa16156d4, 0xffffcb29, 0xff680522, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x00000001, 0x7fffffff, 0x7fffffff, 0xffffffff, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffc8ba9c, 0xffffffff, 0xffc8ba9c, 0xffffff80, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0xf8000000, 0x00000003, 0xf7ff872e, 0x48123473, 0x00afde54, 0x00afde54, 0x0, 0x0 - dspck_astio msubu, 0x1fffffff, 0xfffffff8, 0xdffffffe, 0xfffffffb, 0x80000003, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000001, 0x7fffe3d7, 0x00070a41, 0xffffffc0, 0x00001c29, 0x0, 0x0 - dspck_astio msubu, 0xfffe2dd6, 0xf11a0080, 0xffc086f1, 0xf11a0080, 0x007b4dca, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffffff27, 0xffffffff, 0xffffff27, 0x00000000, 0xffffff80, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffcee797, 0x01022826, 0xd8f29997, 0xfffcd5b2, 0xff00ff00, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x60000009, 0x3fffffaf, 0x3ffffff0, 0x7ffffffb, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000001, 0xc0000001, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x7ffffffb, 0x00000140, 0x00000005, 0xffffffc0, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xfffffff8, 0x7fffffe0, 0x80000037, 0x7fffffff, 0x0000003f, 0x0, 0x0 - dspck_astio msubu, 0x00001fa6, 0x773631a4, 0xe0001fb7, 0x77363124, 0xfffffff8, 0x1ffffff0, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x8012ee16, 0x11d80000, 0xffee11d8, 0xffff0000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xc0000002, 0x80000000, 0x80000000, 0x7ffffffb, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffffff, 0xfcb57eb7, 0x00000003, 0x0118d5c3, 0x0, 0x0 - dspck_astio msubu, 0x00000003, 0x351ff10a, 0x00000003, 0x351ff10a, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00001365, 0xffffffba, 0x66667a11, 0x66666666, 0x000000ae, 0x0, 0x0 - dspck_astio msubu, 0x000004b1, 0x69983cd9, 0xe00004b5, 0x69983cd9, 0x3ffffff8, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0000036e, 0x8005a241, 0xffbc689e, 0xfff4bb88, 0x7ffffffa, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xfffffffe, 0x00000000, 0x00000004, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x7ffffff1, 0x00000780, 0x00000078, 0x1ffffff0, 0x0, 0x0 - dspck_astio msubu, 0xc0000000, 0x00000001, 0xbff9dd5f, 0x57ed0020, 0x0006554b, 0xf8000003, 0x0, 0x0 - dspck_astio msubu, 0xfc000000, 0x00000001, 0xfc000000, 0x00000001, 0x00000000, 0x1c71c71c, 0x0, 0x0 - dspck_astio msubu, 0x3fffffff, 0xfffffff8, 0x801f172c, 0x407c5cb5, 0xc0000003, 0xffd68bc1, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffffff, 0xfffd8b22, 0x00000766, 0x00000055, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffffff, 0xff67190d, 0x0000001f, 0x0004eead, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffda51, 0x1ffd7a01, 0x00002b11, 0xe000000f, 0x0, 0x0 - dspck_astio msubu, 0xfd5d4c43, 0xa13b6134, 0xfd5d4c37, 0xa13b60d4, 0x80000004, 0x00000018, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xffffffff, 0xffff1d1f, 0x000000f1, 0x000000f1, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000001, 0xfffb94e3, 0x80000001, 0x80000000, 0x0008d639, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffff0, 0xffffffe2, 0x0000002c, 0x7fffffff, 0x0000003c, 0x0, 0x0 - dspck_astio msubu, 0x00070e03, 0x97f7a85b, 0x00070e03, 0x97f7a85b, 0x00000000, 0xfffffff2, 0x0, 0x0 - dspck_astio msubu, 0xf8000000, 0x00000001, 0xf7ffff44, 0x80000178, 0x00000177, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x0fffffff, 0xfffffff8, 0x0fffffff, 0xfffffff8, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x011306b6, 0xfffffff9, 0x011307dc, 0xffffffd6, 0x00000007, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffb, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0xf8000000, 0x00000003, 0xb8000010, 0x7fffffe3, 0x7fffffff, 0x7fffffe0, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x7fffffff, 0x7fffff81, 0x8000007f, 0x00000001, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x8d897496, 0xbffffffe, 0x0d89749c, 0x7fffffff, 0x80000006, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffffffe4, 0xff4bf0eb, 0xdf3237cd, 0x00cdc817, 0xe0000001, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0x0000e84e, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xffffffec, 0xc0000000, 0x7fffffec, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0xe0000000, 0x0000000f, 0xa0000000, 0x0000000f, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0xfc000000, 0x00000001, 0xfb3ab669, 0xa8bb517e, 0xffff27bf, 0x00c54a3d, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfc2218ff, 0xffffd159, 0x7c22764c, 0x00005d4d, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xfffffff0, 0x00000000, 0x000004f5, 0x0, 0x0 - dspck_astio msubu, 0xffefbf40, 0x178f5a0d, 0xffefbf40, 0x178f5a0d, 0x00000000, 0x0007af70, 0x0, 0x0 - dspck_astio msubu, 0xffffff8e, 0x6d14471f, 0x0000b5d1, 0x6d027d05, 0xffffffe7, 0xffff49d6, 0x0, 0x0 - dspck_astio msubu, 0x0fffffff, 0xfffffffc, 0x0fffffff, 0xfffffffc, 0x00000000, 0x7ffffffa, 0x0, 0x0 - dspck_astio msubu, 0x55555555, 0x55555555, 0xd55eecdd, 0xd089b115, 0x7fffffc0, 0xffecd16f, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000001, 0x0de281a2, 0x80000001, 0xe43afcbb, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0xf0000000, 0x00000003, 0xf0000000, 0x00000003, 0x00000000, 0xffff0000, 0x0, 0x0 - dspck_astio msubu, 0xdb6db6db, 0x6db6db6d, 0xdb6db6db, 0x6db6db6d, 0x00000000, 0xfffc600b, 0x0, 0x0 - dspck_astio msubu, 0x71c71c71, 0xc71c71c7, 0x71c715e5, 0x578ae7e5, 0x068c761e, 0x0000ffff, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0xfffff29a, 0x9fff9bfa, 0xf0000007, 0x00000e4a, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0x029e7524, 0x48ac0b06, 0xfd618b21, 0xffffffba, 0x0, 0x0 - dspck_astio msubu, 0xc0000000, 0x0000000f, 0xc0000000, 0x0000000f, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x00000003, 0xfffffff9, 0xfffffffa, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7fffee3b, 0x00004713, 0xfffffffc, 0x000011c5, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x40000000, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x0000045a, 0xedef9a30, 0xc0000457, 0xedef9a30, 0x80000006, 0x80000000, 0x0, 0x0 - dspck_astio msubu, 0x7fffffff, 0xffffffff, 0x7d39892c, 0x058ceda7, 0x7fffffff, 0x058ceda8, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xff9aa03c, 0xc0000000, 0x7f9aa03c, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0xc71c71c7, 0x1c71c71c, 0xae413bc4, 0x32fef829, 0x18db3689, 0xfffffa9b, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000009, 0x00000000, 0x00000009, 0x000000c1, 0x00000000, 0x0, 0x0 - dspck_astio msubu, 0xffffffff, 0xfffffff0, 0xc0000000, 0x7ffffff0, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x0000003f, 0xc0000000, 0x8000003f, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio msubu, 0x80000000, 0x00000000, 0x00000832, 0x800062a6, 0xffffef8f, 0x80000006, 0x0, 0x0 - dspck_astio msubu, 0x00000000, 0x00000000, 0x000008d4, 0xfff85422, 0xffffff06, 0xfffff825, 0x0, 0x0 - dspck_astio msubu, 0x00447ca7, 0xb87a4605, 0xc0447ca8, 0x387a4605, 0x80000000, 0x7fffffff, 0x0, 0x0 - - writemsg "[17] Test mul.ph" - dspck_dstio mul.ph, 0x00007f5b, 0x000000a5, 0x00007fff, 0x0, 0x00200000 - dspck_dstio mul.ph, 0x00008001, 0x0000ffff, 0x0f0f7fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x3ff90000, 0xffff7fff, 0xc0070000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00007fff, 0x00040001, 0x00007fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00008000, 0x80008000, 0x800000f5, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x7fc1fb98, 0xffff7fff, 0x803f0468, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0xffe00000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000ff60, 0x80000014, 0x0000fff8, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xa9400000, 0xff5b0000, 0x7fc00000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x001028e0, 0x7fff00b9, 0xfff03fe0, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x149c0000, 0xfe340000, 0x00837fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x9ff10000, 0x7fff3fc0, 0xe00f8000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfe80ffc0, 0x7fc0ffc0, 0x80060001, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00108001, 0x7fffffff, 0xfff07fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x7fff000e, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x00000003, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x8000a010, 0x800003fe, 0x083d1ff8, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x8b100001, 0xc71c7fff, 0xc71c7fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x000b0fae, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000016e, 0x8000ffc3, 0x000efffa, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xdda40000, 0x1ffc7fff, 0x00970000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x1e6e0000, 0xfffbf5ae, 0xf9ea8000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000df90, 0x00000ed4, 0x00000ed4, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00040000, 0x80000007, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x7ffecccc, 0x80008000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x7fff0000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xa00c7fe7, 0xfffafffb, 0x0ffe8005, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfffe0000, 0x00010000, 0xfffe0000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x7ffffffe, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00199a8d, 0x0005ffd3, 0x0005e01f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00007ffd, 0xf0f07fff, 0x00000003, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00007fe1, 0x80007fff, 0x0000001f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000ffa0, 0xfc12fffc, 0x00000018, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x5cc0c390, 0x3fc007fc, 0x038dc71c, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00008000, 0x00008000, 0x00003333, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x1d560000, 0xffff8000, 0xe2aafffe, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfd917fdb, 0xffa70025, 0x00077fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x018c7808, 0xff9d00ff, 0xfffc7ff8, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000fe56, 0x000001aa, 0xf2ec7fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x63348000, 0x33338000, 0x0ffc7fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x000e0000, 0x80070efd, 0x00020000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0xc003001f, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0c780000, 0xf3880000, 0x7fff0a2d, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xffe06db4, 0x7ff00005, 0x80024924, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00020000, 0x7fff8000, 0xfffe0000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00006d1c, 0x0000010f, 0x7fff4924, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x8003f002, 0xfffd0ffe, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0xffd61dc4, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x08ae0000, 0xf752b6db, 0x7fff0000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00008000, 0x00000069, 0x09bc8000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80008000, 0x800029b1, 0x33338000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x01007004, 0x7fc007fe, 0x03fc3ffe, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80000000, 0xf3290000, 0x8000ff07, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x3ff64008, 0x00051ffe, 0x3ffe1ffc, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x7fffe200, 0x7ffffe20, 0x00010010, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x6feb8000, 0xfff9ffff, 0xf0038000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xff8007e7, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xd1be042a, 0xfe82ffff, 0x001ffbd6, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x7ff70000, 0xfffd0000, 0x8003c007, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00057fff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00007ff2, 0x00008002, 0x7ffafff9, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00400000, 0x7fff0000, 0xffc01967, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80020000, 0x7ffa0003, 0x55550000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xfba27ffc, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x8000fc00, 0x0003ff00, 0x80000004, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xc9ae0e0e, 0xed290002, 0x03fe0707, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x80000000, 0x00008000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80006170, 0x7ffff75d, 0x80000030, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x33340000, 0x7ffe8000, 0x66660024, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x001affff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80008007, 0xf001fff9, 0x80007fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x6790e21f, 0x1ffc00ff, 0x061cfee1, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00008000, 0x7fff8000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x60ae0000, 0xf0030000, 0x003a8000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00009248, 0x80004924, 0x80008002, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xaa568000, 0x807ffff3, 0xaaaa8000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x55c00001, 0xffa9ffff, 0x3fc0ffff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfe900000, 0x01707ffe, 0x7fff8000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfe707fc1, 0xfe707fff, 0xe001003f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x609f0000, 0x00fffffc, 0x00610000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfe800000, 0x80060000, 0x7fc0ff00, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80001ff9, 0x8000ffff, 0x7fffe007, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000005, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xedc08000, 0x00498000, 0xffc0005d, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x3627b261, 0xf627c001, 0xc001f261, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00007f8d, 0xfda17fff, 0x00000073, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80000000, 0xffff0000, 0x80008000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80007efd, 0x80008007, 0xffc9ffdb, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x80007fe0, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x804b0000, 0x7fff8000, 0xffb50000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x86880000, 0x8e38c001, 0xe8a70000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x000083ff, 0xfffafc01, 0x00007fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x2146fede, 0x7fff0091, 0xdebafffe, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000002, 0x00007fff, 0x0000fffe, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00004009, 0x0000e003, 0x0000e003, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xff100000, 0xfff0eebe, 0x800f0000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x8000fb52, 0x8000ffff, 0x02b104ae, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0xfffb000e, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80068000, 0x80020189, 0x00038000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x8000edb8, 0x7fff7ff8, 0x80009249, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x74272ae8, 0x7fff2aa3, 0x0bd97ff8, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x05ee0000, 0x00010000, 0x05eeffe7, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xffc1b080, 0x803f009f, 0x7fffff80, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x8000e4a0, 0x7ffbb6db, 0x80003fe0, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x81c0fc28, 0xfff97fff, 0x7fc003d8, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80008005, 0x80007fff, 0x8003fffb, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00008000, 0xffff0003, 0x00008000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xe8188000, 0xffe871c7, 0x00ff8000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x5520000a, 0x0357fffe, 0x3fe0fffb, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfcb0fff4, 0x7fff0003, 0x0350fffc, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000ffc7, 0x00020039, 0x0000ffff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00003ffd, 0x0000c003, 0xfff2ffff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x1c720048, 0x7fff0018, 0xe38ec003, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000abc5, 0x8000fe95, 0xfff01c71, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00314000, 0x7ff97f80, 0x7ff97f80, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x2d9a0000, 0x0ffe8006, 0x01338000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x08000000, 0xff000329, 0xfff80000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x7fa0ffa4, 0x8003002e, 0x7fe0fffe, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x11aefed6, 0x001f7fff, 0x0092012a, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xebf37e20, 0xfffde00f, 0x06af7fe0, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x7fdfc01c, 0x0021f007, 0x7fff0004, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xffa050a0, 0x00061fe0, 0xfff0007b, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00008000, 0x7fff8000, 0x0000f803, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xb6d50000, 0x000f000b, 0xb6db0000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xffe07fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xbff10070, 0xc00f03f9, 0x7fff3ff0, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xff6e0000, 0x7ffffcb1, 0x00920000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00008031, 0x8000c007, 0x8000c007, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xdc718000, 0x1c717fff, 0xc0018000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x06e88000, 0x0000fb00, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x7ffd0040, 0x0003ffe0, 0x7fff07fe, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x8000e9e1, 0x00091c71, 0x80001c71, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xf4570000, 0xfdab0000, 0x0005fff9, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80039ffa, 0xfffdf003, 0x7fff7ffe, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xffae7a4f, 0x00521abd, 0xfffffffb, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x40e0b95d, 0xfff9ff95, 0x3fe000a9, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000004, 0x00000004, 0xf0f00001, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000096, 0x0000ffe2, 0xff80fffb, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000f61, 0x7fff807f, 0x0000801f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x0000fff0, 0xfda48000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfe440004, 0xfffeffff, 0x00defffc, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0006139d, 0xffff04c3, 0xfffa801f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x3ff00000, 0x00000f3d, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00008000, 0xdf11fc0f, 0x00008000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00070000, 0x7ff98000, 0x7fff0002, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x7ff70000, 0x7ffd8000, 0x00030000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x38038000, 0xf8037fff, 0xc0018000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x0000f007, 0x00010000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x7fcf7ecf, 0x7ff97fff, 0x00070131, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x006c0000, 0xfffd8000, 0xffdc036c, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xd3540002, 0xe01f0002, 0xf22c0001, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x1f001485, 0xff08eed7, 0x3fe0f803, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x0ffefff8, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x43dc7fdd, 0x1f74fffb, 0x38e38007, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000c84, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x463c0000, 0x02440000, 0x801f0000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00009ff1, 0xffeb7fff, 0x0000e00f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x7ffbc004, 0x7fff0ffe, 0x00050ffe, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00007fe1, 0x00ffffff, 0x0000801f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x9ffdffb2, 0x7fff001a, 0xe003fffd, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00030052, 0xfff9ffae, 0xb6db7fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x5980de10, 0x7fc01ff0, 0x0e9ac01f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xffb20000, 0x004e007f, 0xffff0000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00004030, 0x00003ff0, 0x1af5fffd, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x800052d0, 0x8000f803, 0x7ffff0f0, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x8002800f, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80000000, 0xfffd0000, 0x80000004, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xea9e0000, 0x002e8000, 0xff890000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x7f806666, 0x1fe06666, 0x00040001, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000666c, 0x0000cccc, 0x8000fff9, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x55550000, 0x0000007f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x8004aaaa, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x8000804d, 0x80007fff, 0x7ff9ffb3, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x8000fffe, 0x8000fffe, 0xe0070001, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80800000, 0x3fc00000, 0x07fe0012, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0080d486, 0x3fe0f9ca, 0xfffc8007, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x3f460000, 0xe01fb6db, 0x7ffa0000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x7abf21bc, 0x05411ffc, 0x7fffff91, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x80008000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xf0070000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00060000, 0xfffa0000, 0x7fff06fb, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000802a, 0xfffcfff9, 0x80007ffa, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x45538000, 0x1c718000, 0xf003e007, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x80000000, 0x00f0e003, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00020309, 0xfffeffdb, 0x7fffffeb, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000ffff, 0xffc6ffff, 0x80000001, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x7fff7fff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0014fe04, 0xffecfffc, 0xffff807f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x7fff8000, 0x0000fe48, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x84448000, 0x80040001, 0x01118000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80000000, 0x8000ff24, 0xe0070000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfa6b2578, 0xffff0008, 0x059504af, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xd2b48294, 0x0a2e3ffe, 0x6db6feb6, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x63348000, 0x0ffc7fff, 0x33338000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00002110, 0x0000ffa4, 0x0000ffa4, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0xb6dbc1cc, 0x00008000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xee990000, 0xfe6b1ff8, 0x000b8000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xff802c9e, 0x0002f9b1, 0xffc01ffe, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xbf047f97, 0xf0820015, 0x2f027ffb, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000f388, 0x80000008, 0x8002fe71, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000edd7, 0x8000f007, 0x0000ffb1, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x000031c0, 0x00000039, 0x3ff03fc0, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfffaa718, 0xfffefe74, 0x0003fcfe, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00005ee1, 0x800000ff, 0x011ac01f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x80000000, 0x06805555, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xe41e0000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x0000ffdf, 0x00230000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x00000001, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x8001c925, 0x7fff7fff, 0xffffb6db, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0010cd3e, 0xfff0e00f, 0xffff00e2, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfffc0000, 0xfffc10ab, 0x00010000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x83270000, 0x010d8000, 0x80037fe0, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x1fe47ffb, 0x00720005, 0x0b827fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80030000, 0x7ffffff0, 0xfffd0000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xbebe13c1, 0xe00705dd, 0xffd20135, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x01000199, 0x7f80f803, 0xfffe3333, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x6a5071b8, 0xf0f00011, 0xff0b8e38, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0000fe30, 0x0000fff8, 0x13d2003a, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0xffc77fff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0980c036, 0x0980f33e, 0xfc010005, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80007ffb, 0x7fff8005, 0x8000ffff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00008001, 0x0000ffff, 0x7fff7fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xf003007f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfffe0099, 0x0002ffcd, 0x7ffffffd, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfffa8000, 0x7ffd8000, 0x00021e89, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0001e2c0, 0x7fffefb2, 0x7fff0060, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00108000, 0x3ffe8000, 0x7ff8ff3f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xd4fd0fff, 0xd4fdf001, 0x0001ffff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xfffbffa0, 0x80050008, 0x7ffffff4, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0xc001f83c, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x80007fff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x38e3ffa2, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x80000000, 0x80000000, 0x7fff807f, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0xe0108000, 0xfffe8000, 0x0ff87fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x8b103290, 0xc71cf934, 0xc71cf934, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x7ffff900, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x0a900001, 0x00347fff, 0x00347fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0x8000fffc, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0xfc017fff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00000000, 0xfc110002, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00000000, 0x00008000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00008000, 0xfd7f8000, 0x00007fff, 0x00200000, 0x00200000 - dspck_dstio mul.ph, 0x00bfa4e5, 0x00bffd6f, 0x000100eb, 0x00200000, 0x00200000 - - writemsg "[18] Test mul_s.ph" - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x012a0007, 0x0, 0x00000000 - dspck_dstio mul_s.ph, 0x80000000, 0x7fff0000, 0x80068000, 0x00000000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x00000f0f, 0x00000f0f, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fffff93, 0xf989006d, 0xdb6dffff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0xc00ffd8a, 0x00061ffe, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0x0297fce4, 0xf8037fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008000, 0xf0037fff, 0x0000fffd, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xe0208000, 0xffff7fff, 0x1fe0e001, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x0000f003, 0x0000f003, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x7fc00000, 0xf0160000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x0ffcf400, 0xffc0fa7d, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x7ffff294, 0x38e30000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x8000fff8, 0x0c320001, 0x8000fff8, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0xe01f2492, 0x000b8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008000, 0x00006666, 0xffeb8006, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x00009249, 0x8e38fff7, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008000, 0xfffffedd, 0x000007fc, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x1ff86666, 0x2492f96f, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x8000fb3e, 0x8000ffd6, 0x0ffc001d, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x3fc00000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0xfff7ee64, 0xf00102aa, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x7fff7fff, 0xfffe7fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x7fc05555, 0x7ffffe96, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x0ff97fff, 0xffffffe9, 0xf007e38e, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x00e1ff80, 0xe38e0000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000440, 0x0006ffbc, 0x9999fff0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0xfffd8000, 0x80007fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff153c, 0xfc67f562, 0xff5bfffe, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x1ffec001, 0x001e1ffc, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x00007fff, 0x92497fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x00013ff0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0xffcd807f, 0xfb80129a, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x7ffd05cc, 0xfea90000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00e17fff, 0x000f7fff, 0x000f7fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff807f, 0x7fff807f, 0x3fe00001, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0xfffe7fff, 0x80047fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xf8c78000, 0xf8c7801f, 0x00010ffe, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x7fff0000, 0x8000000e, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0xfffd0000, 0x7fffc03f, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80017fff, 0xfffff232, 0x7fff8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x7ffe7fff, 0xff800010, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008000, 0x7fff0003, 0x00008000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xe91a0000, 0xfc2f0000, 0x0006800f, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x00630000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x1ff8001f, 0x7fff7ff0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x7fff8000, 0x7fff8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x80000000, 0xf9400000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008001, 0x088bffff, 0xfb127fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff2888, 0x00be0004, 0x7fff0a22, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x00000004, 0x800738e3, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x800f0000, 0x0ffc029d, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0x7ff0aaaa, 0xf0010002, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000004, 0x00ca0004, 0xf0030001, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x8000f123, 0xf0017fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0xfffb8000, 0x7fff7fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0xe4ee7fff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0004, 0xff41fffe, 0xff41fffe, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x7fff8000, 0x00008000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x7ffac00f, 0x80078000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x1ff0e11b, 0x80058000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x8000b6db, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x1ff8fffc, 0x71c77f80, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0xff8f0000, 0x800f0000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0x80007fff, 0x3ff0fc01, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x1fe0000f, 0x803f7fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x013dffe0, 0x7ffafa98, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xf8227fff, 0x00138000, 0xff968000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7ffffaa0, 0x8000fffc, 0xffc60158, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008000, 0x80077fe0, 0x0000ff53, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008000, 0x00000004, 0x00798000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x80007fff, 0x7ffb3fc0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x800400ff, 0x7ffe7f80, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0x03ce0180, 0xcccc8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0x800f02e4, 0x7fff8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xff607ffb, 0x000a8005, 0xfff0ffff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x7fff0000, 0x71c77ffe, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x7fff0000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x02258000, 0x00018000, 0x02250001, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0xe007024a, 0xe38e0ce0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0xf803007f, 0xf0f03ff0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x00008000, 0xfd898007, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x00007ffd, 0x00007ff8, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x6666009f, 0x800004de, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0xf7d4febe, 0xfe107fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fffe2cc, 0x7ffffef5, 0x7fff001c, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xfe500000, 0x00010000, 0xfe507fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x80070000, 0xfb560000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x80006db6, 0x00046666, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x80000000, 0x80007fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0xffeb0000, 0x92497fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0xff003333, 0x7fff7fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x7fff0000, 0x80000002, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x7fff0000, 0xfff37fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0xffeccccc, 0x8000b6db, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0xc00f7fff, 0xffe18000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x8000fa18, 0x7fff00bd, 0x8000fff8, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x7fff06eb, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x99990000, 0x0005db6d, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x7ff98000, 0xfffd8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0xf9a37ffb, 0x00000004, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x00220000, 0xdb6d7ffe, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00107fff, 0x0004f803, 0x0004f803, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x00050ff8, 0x1c710ff8, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x8000f75a, 0x9249ffff, 0x1c7108a6, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x7fff00c2, 0x7fff3ff0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xfe300000, 0xfffc8000, 0x00740000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0xfffb0000, 0x7fff7fc0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008000, 0xfffb8000, 0x00007fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x80006db6, 0x00001ff0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008004, 0x00000001, 0x80008004, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x00d10004, 0x02e17fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xccfccccc, 0xfffccccc, 0x0cc10001, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xfe300000, 0x003a0000, 0xfff8ff00, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0xffab0000, 0x924900ff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0x80008000, 0x7fff7fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0xe00f0000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xf0040000, 0x0ffc0006, 0xffff0000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x00007fff, 0x49241ff8, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x007f001f, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x0000fd45, 0x0000fddc, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0xfffafffd, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x800005f4, 0x7fff007f, 0xfe6d000c, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xfa210000, 0x01f58000, 0xfffd0000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x1ff87fff, 0x00d08000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x0000ffee, 0x0000fffd, 0xf0170006, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00058000, 0xffff3ffe, 0xfffb8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fffffd0, 0x803f000c, 0xffb2fffc, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x7fffffe0, 0x7ffc8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0xfff100ff, 0x0fc88000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x7fff0057, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008000, 0x3ff87fff, 0x0000ffc0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x8000fff8, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0xe38e00b0, 0x8007f0f0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x8000f44f, 0x7fff0000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xff608000, 0xffe08000, 0x00057fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x3a708000, 0x00028000, 0x1d380ffe, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x800f8000, 0x001ff001, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x8000016b, 0x014c0003, 0x80030079, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x8000f0f0, 0x24928007, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0xf00305e9, 0xc00ff003, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0xff007fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xaaaa0031, 0x00010007, 0xaaaa0007, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x8000fff8, 0xffff8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x1ffe001c, 0x7fffc00f, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x1b0f0000, 0x7fff8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000100, 0x0000fff0, 0x0000fff0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00097fff, 0x00032492, 0x00032492, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0x7fffb6db, 0xfff07fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x8000fe1c, 0xe00f0016, 0x6666ffea, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fffffe7, 0x80050005, 0xfdbefffb, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x02a47fff, 0x001a8000, 0x001a8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x80028000, 0x801f0000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x80000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0x7fffc01f, 0xfbc57fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x0000026f, 0x7fff7fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x0000d300, 0x7fffffe0, 0x00000168, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x99997fff, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0xfcf67fe0, 0xfeb27fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x80007fff, 0xfffcfff8, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0xfc0afffc, 0xe01f0000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008000, 0xfc9adb6d, 0x00007fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x7fff0000, 0xffe08000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0xfffd0000, 0x00003fe0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x7fff0000, 0x0000c01f, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0xffe07fff, 0x30a7fffe, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7ffff89d, 0x8000ffc3, 0xe3ef001f, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x80047fff, 0xff260000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x7fff0000, 0x0ffe00cb, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008000, 0x0000003f, 0x0df48000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x032a0000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x0c448000, 0x002ff0f0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0xff8c0018, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xa05d7fff, 0x0003800f, 0xe01fece2, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fffc040, 0x1fe0ffff, 0x7ffc3fc0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0xf8108000, 0xf003c007, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x7ffffffd, 0x001c2c39, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x7fff7fff, 0x0048803f, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x7fff0000, 0xfffa8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xfff87fff, 0xfffcc01f, 0x0002801f, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0xffd8263d, 0xf0013ffc, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0xaaaa003f, 0x3fc00000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0xfff6c01f, 0xc01f0000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x0043fbb6, 0x03cc7fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0xf0f0000c, 0x7fff7fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x1e960000, 0xf5ce0000, 0xfffd8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x002a8000, 0x7ffffcf6, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x7fffc00f, 0x8000fffd, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0x800000b1, 0x0ffe8003, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x8000007f, 0x1ff30000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff807f, 0x7ff0807f, 0x00170001, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0xfff10000, 0xf0017fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x00000ff8, 0xfffe7fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0xc0f27fff, 0xffd7803f, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x7fff3333, 0x7fff3333, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x7fff0087, 0x00cc3fc0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x7fffe003, 0x7fff0075, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0x03fe8e38, 0x80007fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x00001ff0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xfea07fff, 0xfffc9999, 0x0058807f, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00009249, 0xffc00000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00008000, 0x00040000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x80008000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008000, 0x02efdb6d, 0x00007fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x80008000, 0xfc95c75c, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x80000000, 0x00008000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00008000, 0x7fff9249, 0x000000ff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xf99a7fff, 0xffd90004, 0x002a7fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00e17fff, 0x000f3333, 0x000f3333, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0x0000fc32, 0x8007f801, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x6db60000, 0x00020000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7ffffed9, 0xff76ffff, 0x80000127, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x0c8a7fff, 0x00037fff, 0x042e0447, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x8005f803, 0xffe28000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x0303800f, 0x7fff7fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x1e2001b0, 0xfffeff94, 0xf0f0fffc, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x000f5555, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x0000ffc3, 0x01c70000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0x003f8000, 0xe38e0006, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00007fff, 0xdb6d7fff, 0x00007fff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x2492e003, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x8000f001, 0x7fff9249, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0xf0038000, 0xe01f7ffc, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00457fff, 0xfffd8000, 0xffe9ffff, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x8000fb8e, 0x7fff8000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x7fffffda, 0x1ffce38e, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00070000, 0xffff0006, 0xfff90000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x8000f002, 0x8000ffff, 0x00150ffe, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x00000006, 0x00000001, 0xf0010006, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0xf0db7fff, 0x7ffffff0, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x7fff8004, 0xfffb0000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0000, 0x3fc0ffd5, 0x7fff0000, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80007fff, 0x807f7fff, 0x00090005, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80008000, 0x00b66666, 0xf003fffa, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x8000d654, 0x8000007f, 0x7fffffac, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0xffcf7fff, 0xec7d8003, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x80001df2, 0xc71cff53, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0xff788000, 0xfffc007f, 0x0022f7fb, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x80000000, 0x3fe00000, 0x80000029, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff8000, 0x7fff000a, 0x003db6db, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff0024, 0x8000fffa, 0x8000fffa, 0x00200000, 0x00200000 - dspck_dstio mul_s.ph, 0x7fff7fff, 0x80007fff, 0xff9f0001, 0x00200000, 0x00200000 - - writemsg "[19] Test mulq_rs.w" - dspck_dstio mulq_rs.w, 0x00000151, 0xfffffeaf, 0x80000000, 0x0, 0x00000000 - dspck_dstio mulq_rs.w, 0x0017fc8f, 0xe0000007, 0xffa00dc2, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0xfe9ce071, 0xc0000001, 0x02c63f1f, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000000, 0xffffffc0, 0x0003065a, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x000a50e9, 0x8000001f, 0xfff5af17, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000006, 0x7fffffff, 0x00000006, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0xff0bda44, 0xff0bda44, 0x7fffffc0, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000001, 0x0000003a, 0x026b670d, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000001, 0xfffffcec, 0xffe29d3a, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0xffffffde, 0x10d559b5, 0xffffff00, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000046, 0x00000046, 0x7fffffff, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x0000ffff, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000080, 0xffffff80, 0x80000006, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000040, 0x7fffffff, 0x00000040, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000000, 0x80000005, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x7ffffff9, 0x7ffffffa, 0x7fffffff, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x7ffffffd, 0x7fffffff, 0x7ffffffe, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000056, 0x7fffff80, 0x00000056, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000234, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x006bfe19, 0x24924924, 0x0179f958, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x12492491, 0x3ffffffe, 0x24924924, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000096, 0xffa6fc9a, 0xffff2867, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x00000006, 0x0f0f0f0f, 0x00000035, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0xffffffe1, 0x7fffffff, 0xffffffe1, 0x00000000, 0x00000000 - dspck_dstio mulq_rs.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00000000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xfffff429, 0xfffff429, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x01000000, 0x0ffffffc, 0x07fffffe, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000001, 0xffffffff, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x66666665, 0x66666666, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x0000001b, 0x80000007, 0xffffffe5, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x80000005, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x3fffffe0, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffffad0b, 0x80000007, 0x000052f5, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xffff0000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000027, 0x80000006, 0xffffffd9, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x07fffffc, 0x7fffffff, 0x07fffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00078e5a, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00a1c74b, 0xffffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x7ffffff4, 0x7ffffffb, 0x7ffffff9, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffffadf4, 0xff3e7557, 0x00364356, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x000000df, 0xe000000f, 0xfffffc82, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000001, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000128, 0x7fffffff, 0x00000128, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x01abeed0, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffff0001, 0x80000000, 0x0000ffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xff58cf32, 0xfffffff8, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000001, 0xff00ff00, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x000b829a, 0x7fffffff, 0x000b829a, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x1ffffff0, 0x7fffffff, 0x1ffffff0, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x80000015, 0x7ffffff0, 0x80000005, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xfffffff8, 0xfffffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x80000002, 0x80000001, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffe1aa82, 0x7fffffff, 0xffe1aa82, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xff9b6f67, 0xfffffffa, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000004, 0x80000000, 0xfffffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000006, 0x7fffffff, 0x00000006, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000007, 0x7ffffffb, 0x00000007, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfff013c6, 0x24924924, 0xffc84534, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffa8d35, 0x002b965b, 0xf0000007, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffe43f8, 0xff411954, 0x0129b9d1, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x8000007f, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xffffcca4, 0xfffffc33, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x7ffffffb, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x7ffffff8, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00001dad, 0xffffe01a, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffffffd, 0x00000007, 0xc0000007, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x01ffffff, 0xf0000003, 0xf0000003, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffffeff, 0x000005c4, 0xe9bfc5a9, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00001742, 0xffffe8be, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x7ffffffb, 0x80000000, 0x80000005, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x1ffffffe, 0x1ffffffe, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xfffffffc, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0xffffff97, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffff6e13, 0x000091ed, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000005, 0xb6db6db6, 0xfffffff8, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000038, 0x7fffffff, 0x00000038, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xf0000003, 0x7fffffff, 0xf0000003, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xf0f0f0f0, 0xf0f0f0f0, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000aee, 0xfffff512, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xf0000002, 0x0ffffffe, 0x80000001, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x000000ff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x0000001c, 0xffffffc0, 0xc71a53fe, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x38e38e1c, 0x71c71c71, 0x3fffffe0, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x80000005, 0x7fffffff, 0x80000004, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x8e38e38f, 0x71c71c71, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0xffff3933, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffff5da6, 0x0000a25a, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000fd3, 0x7fffffff, 0x00000fd3, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffffb9c, 0xffffdcdf, 0x0ffffff8, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x015c1cc7, 0xfea3e339, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0xaaaaaaaa, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x054b7975, 0x00000001, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000003, 0x7fffffff, 0x00000003, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x011434d5, 0x49249249, 0x01e35c75, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00000007, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x7fffffc0, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x353dcce8, 0x7fffffff, 0x353dcce8, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x80000005, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xe683a401, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffffffc, 0xffffffe0, 0x0ed9ff25, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xfffffff9, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x8e38e38e, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xf8000002, 0x07fffffe, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffffffd8, 0xf0000007, 0x00000140, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x0000000f, 0xff67e80c, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x80000001, 0x80000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffde962, 0x0ffffffe, 0xffef4b11, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xffffffff, 0xffffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x80000001, 0x80000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00574a38, 0x7fffffff, 0x00574a38, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffffff1d, 0x000000ff, 0x8e38e38e, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xffed1970, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xf0000009, 0xe0000003, 0x3fffffe0, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xff807f81, 0x00ff00ff, 0xc0000003, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0xf8000001, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffff2ec, 0xffffcbb0, 0x1ffffff8, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000003, 0x00000007, 0x38e38e38, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffffffcb, 0x80000000, 0x00000035, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x7ffffffa, 0x7ffffffd, 0x7ffffffd, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000001, 0xb6db6db6, 0xfffffffe, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x12f684bd, 0x55555555, 0x1c71c71c, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x1249248d, 0x3ffffff0, 0x24924924, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xffffffff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xff81f884, 0x013b12b5, 0xcccccccc, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x0000006f, 0x00000d3b, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x023b15c9, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xfffffffa, 0x0014e498, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000001, 0xf0000007, 0xfffffffa, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x7ffffffd, 0x80000000, 0x80000003, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xfffffc38, 0xfffffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffffff36, 0x7fffff80, 0xffffff36, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00ead470, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000006, 0x80000000, 0xfffffffa, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000066, 0x80000000, 0xffffff9a, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000001, 0x0ffffff8, 0x00000006, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffffffc, 0x1ffffff0, 0xfffffff0, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xfffffbe1, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00034357, 0xfffcbca9, 0x8000000f, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x5e0a72ef, 0x6db6db6d, 0x6db6db6d, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x80000001, 0x80000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xffffffc0, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffffff71, 0xfffff709, 0x07fffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x80000004, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00001e53, 0xffffe1ad, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xffffffff, 0x00000004, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000005, 0x003d27bc, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffffffe3, 0x0000001d, 0x80000005, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xfffffffe, 0xe0000003, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00000003, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffffec3, 0xfffffd86, 0x3ffffff0, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xf8000007, 0x3fffffe0, 0xf0000007, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfff2d687, 0x66666666, 0xffef8c29, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000002, 0x80000000, 0xfffffffe, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x7ffffff8, 0x7ffffff9, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x146725b0, 0xeb98da50, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xfff7f8d8, 0xfffffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x0000049a, 0x00001251, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffff007, 0xc000001f, 0x00001ff2, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00024b75, 0x7fffffff, 0x00024b75, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x000002ad, 0x00128096, 0x00128096, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xf1c71c72, 0x38e38e38, 0xe0000001, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x0006c160, 0x7fffffff, 0x0006c160, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xfffffff8, 0xfffffff0, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xc0000007, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x80000002, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x0ffffffe, 0x0ffffffe, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfc000002, 0x80000000, 0x03fffffe, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0xffffffe3, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x38e38e39, 0x80000000, 0xc71c71c7, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000028, 0xffffffd8, 0x80000005, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x80000001, 0x80000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x0ffffffe, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x0000000f, 0x80000001, 0xfffffff1, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffface56, 0x0005d7df, 0x8e38e38e, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x0000000a, 0x0000000f, 0x55555555, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000002, 0xfffffffe, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x80000004, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x80000004, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffffffe, 0x00000002, 0x8e38e38e, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x3fffffe1, 0xc000001f, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xfffffffa, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000007, 0x00000007, 0x7fffffe0, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00001bc5, 0x00001bc5, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x06e5c118, 0x1db69774, 0x1db69774, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00b25008, 0x80000001, 0xff4daff8, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xf8000003, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x7fffff81, 0x80000000, 0x8000007f, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000001, 0x7fffffff, 0x00000001, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffe01fe0, 0xff00ff00, 0x0ffffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000003, 0x00020e6a, 0x00009c63, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffffff0, 0x7fffffff, 0xfffffff0, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000006, 0xfffffffa, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xc0000001, 0xc0000001, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00001866, 0x00030ccb, 0x03fffffe, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x07fffffe, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffffffff, 0xffffffff, 0x66666666, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffffffff, 0x71c71c71, 0xffffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffff312, 0xffff3f7b, 0x0898d847, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xffffffa7, 0x00573bd0, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffffffe1, 0x80000000, 0x0000001f, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xffffff00, 0xffffff00, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0xfffffff9, 0xfffffff9, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000002, 0x001f3444, 0x00000683, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000001, 0xfffffffd, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffffff7, 0x7fffffff, 0xfffffff7, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0xffffe06d, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffffffe, 0x7ffffff9, 0xfffffffe, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000104, 0x00000289, 0x33333333, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000002, 0xffffff00, 0xff00ff00, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x000003d1, 0x80000000, 0xfffffc2f, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x007dd65e, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000000, 0x0003aa03, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x00000001, 0xff00ff00, 0xffffff99, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0x1c71c71d, 0x80000000, 0xe38e38e3, 0x00200000, 0x00200000 - dspck_dstio mulq_rs.w, 0xfffd5905, 0x03fffffe, 0xffab20ab, 0x00200000, 0x00200000 - - writemsg "[20] Test mulq_s.ph" - dspck_dstio mulq_s.ph, 0x99990000, 0x7ffffffa, 0x9999fb8b, 0x0, 0x00000000 - dspck_dstio mulq_s.ph, 0x00040090, 0xfda10091, 0xff0d7fff, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0xf0040000, 0x80000000, 0x0ffc0000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0xfff70000, 0x800ffffe, 0x0009ffff, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000023, 0x00000023, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0xffff0000, 0xffff0000, 0x7fff1ffc, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00007ff1, 0xfffe8000, 0xff5f800f, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x04540000, 0x7fff0000, 0x04551ff8, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x0001ffff, 0x00a1fdb7, 0x00cd0003, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0xfffa0000, 0x05800000, 0xff8b0000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0xfff80005, 0xffe00006, 0x1fe07fff, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00008003, 0x00008003, 0x7fff7fff, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00000000, 0x7fff0000, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x1fdee004, 0x1fe01ffc, 0x7ffa8000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0xfde20000, 0x043b0000, 0xc003c71c, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00001948, 0xfff338e3, 0xfff338e3, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x0000ff19, 0xfec6ff19, 0x00007fff, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x005b0000, 0x7fff0000, 0x005c0002, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0xffffc71d, 0x00048e38, 0xfb413ffe, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x55558000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x00088000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x8001fffd, 0x80000003, 0x7fff8000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00001fff, 0xfa028000, 0x0000e001, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00000000, 0x1ff838e3, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000002, 0xf0070000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00008000, 0x072f0000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0xffda0000, 0x3ffe0000, 0xffb5ff07, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0xffffff00, 0xfd6e7fff, 0x001fff00, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00551ff7, 0xaaaa1ff8, 0xff807fff, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0xf0d1096f, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x8001c02f, 0x8000801f, 0x7fff3fe0, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x8001fffd, 0x7fffffd4, 0x800007ac, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x0000ffff, 0x7fff0007, 0x0000fddb, 0x00000000, 0x00000000 - dspck_dstio mulq_s.ph, 0x7fff7ffe, 0x80007fff, 0x80007fff, 0x00000000, 0x00200000 - dspck_dstio mulq_s.ph, 0x003be001, 0x7fffe001, 0x003c7fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00008001, 0x00008000, 0x00067fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x665f7fff, 0x66668000, 0x7ff88000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x7ffe8001, 0x7fff8000, 0x7fff7fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffc0ffd, 0xffe00ffe, 0x0fed7fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffd7ff28, 0xf0f0ff28, 0x015b7f80, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x01d80012, 0x01d9002f, 0x7fff3333, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfee37ffe, 0x011d7fff, 0x80007fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000e003, 0x00003ffc, 0x0000c003, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000fff8, 0x0006fff8, 0x0ffe7fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0xff510053, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000fdfc, 0x00000204, 0x006a803f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffe0000, 0x7fff8000, 0xfffe0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff0000, 0x0025e001, 0xff140000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffffffff, 0xfffdffff, 0x00d70016, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x02a30000, 0x02a47fff, 0x7ff90000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffffffe, 0x00107fff, 0xfff9fffe, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x0000003f, 0x000f0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0004ffee, 0xfeb73fe0, 0xfe1bffdd, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000ff80, 0xffd87fff, 0xff1fff80, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x1ffd01ff, 0xc0030ffe, 0xc0030ffe, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000db6f, 0x09c18006, 0x00002492, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x001d1ff8, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x999a0000, 0x66660015, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff0004, 0xff468000, 0x0003fffc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00abffff, 0x7ff90001, 0x00ace007, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00001101, 0x00152ea8, 0x00152ea8, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00016524, 0x00ff8e38, 0x00ff8e38, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x0000c71c, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xf802ffff, 0x80000006, 0x07fef003, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffd0003, 0x7ff00004, 0xfffd7fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffffffa3, 0xfffbcccc, 0x001f00e8, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x8000801f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x8001013d, 0x7ffffec3, 0x80018000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00220175, 0x80008002, 0xffdefe8a, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000ff00, 0x55557fff, 0x0000ff00, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xeb848001, 0x147c8000, 0x80007fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x7ffe0000, 0x7fffe003, 0x7fff0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x7ff9004d, 0x7fff004e, 0x7ffa7fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000e202, 0x7fff807f, 0x00001e1b, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xdb6d0093, 0x7fff0094, 0xdb6d7fc0, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff0000, 0x00010000, 0x8000e007, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x020a0000, 0xefd7ffd9, 0xefd7ffd9, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000fffd, 0x49246666, 0x0000fffd, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfff12493, 0x000fdb6d, 0x80008000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x801f0000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x0068fe27, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xe03f0000, 0x3fc0fff1, 0xc03f0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000001, 0xea200cf7, 0x0000000c, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffc9ffff, 0xffc9fffc, 0x7ffe000e, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xe38f000b, 0xe38e000c, 0x7ffb7fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x55560072, 0xaaaa0073, 0x80007fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00060000, 0x09000001, 0x005a0fb2, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x3ffb3332, 0x80048003, 0xc003cccc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffc10000, 0x80007ff0, 0x003f0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00007ffe, 0x000b7fff, 0x000b7fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff0000, 0xffff0007, 0x7fff0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffe5feb9, 0xffe52e09, 0x7ffafc75, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000fffe, 0xfffb8000, 0xfffd0002, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000ff3f, 0xfffe0302, 0xe38ee003, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x01d00003, 0x7fff0b0a, 0x01d1002e, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff0000, 0x012e7fff, 0xfff70000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000e5e0, 0x00004924, 0x0000d248, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000ffff, 0x3ffc001f, 0x0002ffee, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x03088002, 0x03098000, 0x7fff7ffe, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x0000ff1c, 0x801ffffd, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00001caa, 0x00007fff, 0x7fff1cab, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff7fff, 0x00288000, 0xfefd8000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0e370000, 0x1ffe0000, 0x38e3ffd2, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x017e0000, 0xfe420f0f, 0x92490000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xff1af384, 0x80006666, 0x00e6f066, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xc040f003, 0x8000800f, 0x3fc00ffe, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x7ffe0000, 0x7fff002a, 0x7fff0005, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x3f1e0000, 0x0000c001, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xe008ffff, 0x1ff8fff9, 0x80000004, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffcffff, 0xffe5003f, 0x11cdfffd, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x0194000f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfff20000, 0x7ffffffc, 0xfff20000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0xfe1e3ffe, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xc0070006, 0xc0078000, 0x7ffffffa, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000100, 0x0000ff00, 0x1c718000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xf00a0000, 0x7fc0ffc9, 0xf0030000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffb0000, 0x80030000, 0x0005d28f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfc4d8001, 0xfc4d7fff, 0x7fff8000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00b16666, 0x00000001, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000001, 0x00007fff, 0x7ff80002, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x002c7ff4, 0xfb448006, 0xfb448006, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x001d0001, 0x001e0006, 0x7fff1793, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00ff0000, 0xf803fff8, 0xf0010000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x7fff0000, 0x80000000, 0x8000803f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x49230005, 0x7fff0006, 0x49247fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00017ffe, 0x00027fff, 0x7ffe7fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000fffe, 0x00000002, 0x3fe08000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff0032, 0xffff7fff, 0x1ff80033, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000024, 0xc001007f, 0xffff2492, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x8002fff1, 0x8002000f, 0x7fff8000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00060000, 0xfffa0029, 0x80000002, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xff8bfff5, 0x8000fff5, 0x00757ffa, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x00040014, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000e00b, 0x00011ff8, 0x71c7800f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00050009, 0x000600ff, 0x7fff04f2, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x8003fffd, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x8001fff0, 0x8000fff0, 0x7fff7ffc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000ffff, 0x1fe0f003, 0x00000002, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xf87cfb15, 0x0f0f7f80, 0xc01ffb11, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffaffde, 0x00ff0022, 0xfd0f8000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000006, 0x00008000, 0xfffdfffa, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000ff80, 0xffc07fff, 0xffffff80, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00400000, 0x05b3002e, 0x05b3002e, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff0002, 0x0067fffe, 0xfff68000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00e00000, 0x80007ff8, 0xff200000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffe00000, 0xffe00000, 0x7fff00ba, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffc00000, 0x007fc5c4, 0xc03f0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000033, 0x0000019b, 0xf0030ff8, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xf9e7ff08, 0x71c70648, 0xf924ec4b, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000fffe, 0x0000001f, 0x8000f83e, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xe74dfff9, 0x80008007, 0x18b30007, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00eeffc8, 0xff12ff90, 0x80003ff8, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000001, 0xe7817fff, 0x00000002, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x8040003e, 0x7fc07fff, 0x8000003f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0ff80000, 0xe00f0000, 0xc0017ffc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xff80ffff, 0x7fffffea, 0xff80001f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0xc03fffc0, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00008000, 0x07fc0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xe38f0000, 0xc71c8000, 0x3ffc0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00007fff, 0xe38e0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00008008, 0x00007ff8, 0xffff8000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000f878, 0x00000f0f, 0x0000c003, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x7ff80000, 0x7ffe0000, 0x7ffafff0, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x000d0000, 0xdb6d0000, 0xffd00000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x07a20000, 0x8000fff0, 0xf85efe19, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffd0000, 0x80003ffe, 0x00030000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffdc0000, 0x80000034, 0x00240000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x7ffff007, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x1fed6db7, 0x800f9249, 0xe00f8000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0xfbbb7fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xf8f60004, 0x8006fffb, 0x070a8007, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfff0fae2, 0x00fd148a, 0xf868e01f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff8001, 0x1ffc7fff, 0xfffc8000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0007c002, 0x00083ffe, 0x7ffb8000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000fe38, 0x7fff01c8, 0x00008000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffe0000, 0xfff8ff00, 0x1ff80000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00008005, 0xfff60000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffffffb, 0x0001fffb, 0x80007fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xf15effff, 0x2492ff00, 0xcccc0002, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00010000, 0xfffd0000, 0xc00f0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffffc020, 0x3ffe3fe0, 0xfffe8000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000fffa, 0x00008000, 0x3ff00006, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000ffea, 0x0000ffe0, 0xfffd5555, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0x1fe0003e, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00160000, 0x07fc0000, 0x01708000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfbe6ffff, 0xfbe6fff0, 0x7fff0268, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0048b6db, 0x007f7fff, 0x4924b6db, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000feb7, 0x00077fff, 0x0003feb7, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00018003, 0x00047ffd, 0x3ffc8000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffffd78, 0xff7f7fc0, 0x003ffd77, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x1fff0000, 0x8000ffdc, 0xe001fffd, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xc0100000, 0x80000000, 0x3ff01ffc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0xffe00042, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfff4ffc0, 0x156f0040, 0xffb98000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000014, 0x07fc0015, 0x00007ff9, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x80073332, 0x80003333, 0x7ff97ffe, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x803f0000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0xc0010000, 0x00007ff8, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00007fff, 0x14190000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffa90000, 0x801f000f, 0x00570000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x3ffb0000, 0x3ffcc03f, 0x7fff0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00010008, 0xe001fff8, 0xfff88000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfff50000, 0x000b0003, 0x80070028, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x7fff7fff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x8000e00f, 0x0000ffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000ed2a, 0xfc0112d6, 0x00008005, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0a8e001e, 0xe364003d, 0xd0c63ffe, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfff900c9, 0x7fff8000, 0xfff9ff37, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000ffff, 0x80000001, 0x0000f0f0, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x1fed1ff9, 0xc007e007, 0xc01f8000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff0000, 0x00020003, 0xffff0b25, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000ff01, 0x00028000, 0x249200ff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff0000, 0x0ffc0000, 0xfffff007, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfcb60193, 0x8002f9b2, 0x034ae001, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00008e38, 0xe0017fff, 0x00008e38, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00007ffe, 0xffe07fff, 0xffe07fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffdfff7, 0xffe85555, 0x0fd5fff3, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000fffe, 0xe0407fff, 0xfffcfffe, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff0000, 0xfc91ff94, 0x0007ffde, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x1fff7ffe, 0xc0017fff, 0xc0017fff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xff81e676, 0x007f7fff, 0x8000e676, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x49250000, 0xb6dbfffd, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfff40000, 0xf9170000, 0x00d7370e, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xffff0001, 0xffff8000, 0x066effff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000f008, 0xfe980ff8, 0x00008000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x0000002e, 0x00400000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000288, 0xfffef6ce, 0x0000dcb7, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00070000, 0x0005fff3, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffd2493, 0xe00f8000, 0x0009db6d, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xf0180002, 0xe02e014c, 0x3ff800e3, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00000000, 0x00000000, 0xfffcfdb5, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xf98f0000, 0xf31f1ffc, 0x3ffc0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000ffff, 0x00001ff0, 0x0000fffc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0xfffd0000, 0xfffd0000, 0x7fff0000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x0000ffff, 0x0001003d, 0x0ff8ffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.ph, 0x00008003, 0x00007fff, 0xfffd8003, 0x00200000, 0x00200000 - - writemsg "[21] Test mulq_s.w" - dspck_dstio mulq_s.w, 0xff0c108a, 0x7fffffff, 0xff0c108a, 0x0, 0x00000000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x00000003, 0xe0000003, 0xfffffff0, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x183db574, 0x80000000, 0xe7c24a8c, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x80000001, 0x80000000, 0x7fffffff, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0xffffffff, 0x0000001f, 0xffff35c4, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000001, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x00000014, 0x0002b663, 0x0003c2c1, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x80000040, 0x80000000, 0x7fffffc0, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0xfffffffb, 0x00000009, 0xc0000001, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x00000016, 0x00001668, 0x008359a8, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0xfffffff3, 0x0000000d, 0x80000000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x0db6db67, 0x92492492, 0xf0000007, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0xfffffe9a, 0x7fffffff, 0xfffffe9a, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x00000005, 0x00000016, 0x1ffffff8, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0xc0000002, 0xc0000001, 0x7ffffffd, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0xf8000005, 0x07fffffc, 0x8000001f, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x3fffffe1, 0xc000001f, 0x80000000, 0x00000000, 0x00000000 - dspck_dstio mulq_s.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00000000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000950, 0xf0000001, 0xffffb57e, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfff00096, 0x000fff6a, 0x80000005, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xfffffff9, 0xfffffff9, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffed029, 0x80000004, 0x00012fd7, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x0000010c, 0xfffffef4, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0x00005914, 0xfffffffa, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x0ffffffb, 0x0ffffffc, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000007, 0xfffe016e, 0xfffe016e, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000040, 0xffffffc0, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0xffffffff, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xffffffe7, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffc5c9, 0xffffc5c9, 0x7ffffffd, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000048, 0x0000005b, 0x66666666, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x0001c5fe, 0x1ffffff0, 0x000717fa, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffffffd, 0x00000004, 0xb6db6db6, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000035, 0x07313e72, 0x000003b8, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x07878783, 0x0f0f0f0f, 0x3fffffe0, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffffffc, 0x80000000, 0x00000004, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x92492492, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000004, 0x00000004, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000003, 0x24924924, 0x0000000b, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0xfc000001, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x49249249, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xe0000001, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x000042ba, 0xdb6db6db, 0xffff1672, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffff0001, 0x80000000, 0x0000ffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0x80000000, 0x00000001, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffe0, 0x7fffffff, 0xffffffe0, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffe0898, 0x6db6db6d, 0xfffdb4b2, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0xf8000001, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000004, 0x80000000, 0xfffffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x000018c6, 0x7fffffff, 0x000018c7, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0xfffffe56, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0xffff2078, 0x000020b2, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000547, 0xffe601dc, 0xffe601dc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffd5, 0x0000002b, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xffffffff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xb6db6db7, 0x49249249, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0xf0f8a664, 0x00000001, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x3a4591a6, 0x3a4591a7, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffffffe, 0x0013515a, 0xfffff583, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0xffffffff, 0x0004bf5d, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xffffff00, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00070ab3, 0xf0000003, 0xffc7aa60, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x01eb9ec6, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00001d42, 0xffffe2be, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000d04, 0x000026e8, 0x2ad42035, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000444, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0xfffea52d, 0x0000016c, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0x00076c0f, 0xfffffe7a, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000005, 0x80000003, 0xfffffffa, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xe0000007, 0xe0000007, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x28a9770b, 0xd75688f5, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x007bc9dd, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x0002b243, 0xffea6de7, 0xf0000003, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xaaaaaaaa, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x8000000f, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffef, 0xffffffeb, 0x66666666, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x71c71c72, 0x8e38e38e, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffb2beb4, 0xffb2beb4, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0xfffffffe, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x1ffffff0, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x0000003f, 0x0000007f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x0000007f, 0xffffff80, 0x8000007f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffff873, 0x38e38e38, 0xffffef03, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xff11e299, 0xffffff93, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffe2c0, 0x7fffffff, 0xffffe2c0, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x92492492, 0x7fffffff, 0x92492492, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xb6db6dbf, 0xb6db6db6, 0x7ffffff0, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0x00000007, 0xf0f0f0f0, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffff45ae, 0x03fffffe, 0xffe8b5c2, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffe9, 0xd216970c, 0x0000003f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x000085ee, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xfffffff8, 0xfbf0cdae, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffd5, 0x7fffffff, 0xffffffd5, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x0000000e, 0x000000de, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000007, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x71c71c72, 0x80000000, 0x8e38e38e, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xfffffe9a, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x7fffffff, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xf6ee22d3, 0xf6ee22d3, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x0ffffff8, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x06e0d113, 0x1ffffffe, 0x1b834451, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffffff9, 0x00000007, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x000fedbb, 0xfff01244, 0x8000003f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0xffffffec, 0x000d133d, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x0000770c, 0xeeae9cd4, 0xfffc901a, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffff80, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000016, 0x7fffffff, 0x00000017, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xffb013f5, 0xfffffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7ffffff7, 0x7fffffff, 0x7ffffff8, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffffffc, 0x0000000f, 0xe38e38e3, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xc0000005, 0x80000003, 0x3ffffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfd7927a7, 0x80000000, 0x0286d859, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xfffefd47, 0xfffffffd, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000005, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0xf8000001, 0x00000001, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xff19d329, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x0000001a, 0xffffffe2, 0x8e38e38e, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00008b8d, 0x80000000, 0xffff7473, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x000000ae, 0x00000001, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xfffffff9, 0xffde2edd, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000007, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x0000002c, 0xfffff0a0, 0xfe8d6d48, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7ffffffa, 0x80000006, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffffffa, 0xfffffffa, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x3e66848c, 0x3e66848d, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xff00ff01, 0x80000006, 0x00ff00ff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x1c71c71b, 0x1c71c71c, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xffffff8a, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0xc000000f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x0ffffffb, 0x7fffffff, 0x0ffffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x0000001b, 0x00001eb2, 0x00741f18, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000006, 0x80000000, 0xfffffffa, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfec0fe9f, 0x7fffffff, 0xfec0fe9f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xfffffffb, 0xfffffffa, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x3f336130, 0xc0cc9ece, 0x80000003, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x80000020, 0x7fffffe0, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0x01671684, 0xffffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x1ffffffb, 0x1ffffffc, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xfffffff8, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffe9c39, 0xfffe9c39, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfff26d00, 0x80000000, 0x000d9300, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x0000003f, 0x00462bc5, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffe5, 0xffd4233e, 0x00004d60, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x55555555, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x000000ff, 0x80000007, 0xffffff00, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x80000082, 0x7ffffffc, 0x8000007f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000001, 0x80000000, 0xffffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffa5, 0x03fffffe, 0xfffff4a1, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xf8000001, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x0b1b48af, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfee7cc77, 0xfee7cc77, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffed035, 0x7fffffff, 0xfffed035, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x0ffffffb, 0x7fffffff, 0x0ffffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x7fffffe0, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x24924924, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000665, 0x001c9d40, 0x001c9d40, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfeec5637, 0x80000000, 0x0113a9c9, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x80000001, 0x7fffffff, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x000020f9, 0x00041f3a, 0x03fffffe, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xc0000020, 0x3fffffe0, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffeb505, 0xffd6a0ba, 0x03fffffe, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0xfffffffa, 0x0038e08e, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x000000aa, 0xaaaaaaaa, 0xffffff00, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00009fb6, 0x80000006, 0xffff6049, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7fffffe0, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0x1ffffff8, 0xfffffffe, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xffff5c9e, 0xffff5c9e, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffec, 0x00000027, 0xc0000007, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x000001a7, 0x0000069e, 0x1ffffff8, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000a7d, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x000e65db, 0x80000000, 0xfff19a25, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7fffffff, 0x80000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xffffd56d, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x08d62e22, 0x08d62e23, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x01de3389, 0xfe21cc77, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7fffff7b, 0x7fffff80, 0x7ffffffb, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xf0000002, 0x0ffffffe, 0x80000005, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x7fffffc0, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x06ea08ba, 0x06ea08bb, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x000023a2, 0xf0000001, 0xfffee2e8, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x1fffffef, 0xc0000003, 0xc000001f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x80000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x000741c7, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x99999999, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffff, 0x00000001, 0xffff192b, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffffab1, 0x80000000, 0x0000054f, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffe7, 0xffffe80b, 0x0083b5b6, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x000123c5, 0x7fffffff, 0x000123c6, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00745b2f, 0xc0000001, 0xff1749a1, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x2082081f, 0x49249249, 0x38e38e38, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x99999999, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x03160aab, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xe000000f, 0xfffffffd, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x80000001, 0x80000000, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x80000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xfffffffa, 0x80000001, 0x00000006, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0xfffffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x7ffffffe, 0x7fffffff, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffffca, 0x3ffffff8, 0xffffff95, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x039ef36c, 0xe308649b, 0xf0000001, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000295, 0x80000000, 0xfffffd6b, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xfe0d4e6c, 0xfffffffc, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xffffff82, 0xffffff82, 0x7fffffff, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0xffffff5c, 0xffffe198, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0x00000000, 0x00000000, 0x7ffffff8, 0x00200000, 0x00200000 - dspck_dstio mulq_s.w, 0xff92e452, 0xfe4b9148, 0x1ffffff0, 0x00200000, 0x00200000 - - writemsg "[22] Test mulsa.w.ph" - - writemsg "[23] Test mult" - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffff80, 0x80001ee1, 0x8000001f, 0x000000ff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xfffffc4c, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffff9, 0x24924910, 0x00000030, 0xdb6db6db, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xf999999a, 0x39999999, 0x33333333, 0xe0000003, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xc0000000, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffed55c4, 0x0012aa3c, 0xffc8014c, 0x55555555, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000139c, 0xbffddadb, 0xffffb18d, 0xc0000007, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000600e, 0xdb6c36a0, 0x24924924, 0x0002a068, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffff8ff, 0xd404cc78, 0x00060edd, 0xfed82ad8, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffc0, 0x00000080, 0x7fffffff, 0xffffff80, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xc71c71e3, 0x71c71c80, 0x7fffffc0, 0x8e38e38e, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xf0f0f0f0, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x3fffffbf, 0x80000080, 0x7fffff80, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x002da41f, 0x23dbb8a8, 0x24924924, 0x013f7cda, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffff8bd, 0x80000000, 0x80000000, 0x00000e85, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x02ce79a3, 0xffc8bb91, 0xfffffff3, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x000003aa, 0x00000000, 0xfffff8ac, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x000c9f35, 0xa62ea81a, 0xec8d57a7, 0xff59da56, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000007, 0x00000001, 0x00000007, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfe3b2ec0, 0x0389a280, 0x7fffffff, 0xfc765d80, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000044, 0x7ffffeee, 0x7ffffffe, 0x00000089, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x000000d0, 0xfffffe5e, 0x7fffffff, 0x000001a2, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x07fffffe, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffc0, 0x00000200, 0x7ffffffc, 0xffffff80, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffd3, 0x0000005a, 0x7fffffff, 0xffffffa6, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000003, 0x5b09cf80, 0xf949ec61, 0xffffff80, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0001c000, 0x80000000, 0xfffc7fff, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x33333333, 0x80000000, 0x80000000, 0x99999999, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xffffff00, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000291, 0x00000000, 0xfffffade, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x0ffffff8, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x000001a8, 0x35cbde00, 0xfffe5622, 0xff00ff00, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffff6, 0x8000010a, 0x00000026, 0xc0000007, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xff99c744, 0xfffffffe, 0x00331c5e, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x007f807f, 0x7f00ff01, 0x7fffffff, 0x00ff00ff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x0000001f, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xa000002a, 0xf0000007, 0x00000006, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x7ffffffd, 0xffffffff, 0x80000003, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffeef, 0x66666224, 0xcccccccc, 0x00000553, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffc0, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000001d, 0x29f3de4e, 0x0000007f, 0x3ac97ab2, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x1ffffffd, 0x80000008, 0x7ffffffe, 0x3ffffffc, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xc0000002, 0x00000000, 0x7ffffffc, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x33333333, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffffe, 0x24613100, 0xfe04abf0, 0x000000f0, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x000432ad, 0xfff79aa4, 0x0008655c, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0x88022908, 0xfffffd51, 0x002cb688, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000277b, 0xffffb108, 0x7fffffff, 0x00004ef8, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0x80000040, 0xffffffff, 0x7fffffc0, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x8000007f, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffe0, 0x00000040, 0xffffffc0, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xffef3bc0, 0xffffffc0, 0x00004311, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00021873, 0x80000000, 0x80000000, 0xfffbcf19, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x000001fd, 0xe18d1db0, 0xfe0afcaa, 0xfffefb78, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0ffffff7, 0xe0000010, 0x7fffffff, 0x1ffffff0, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000001b, 0xffffffcf, 0x0000003f, 0x71c71c71, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000007e, 0xd06923d4, 0x00c47864, 0x0000a53d, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffaf6, 0x00002850, 0x80000004, 0x00000a14, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000006, 0x00000000, 0x80000000, 0xfffffff4, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xe0000003, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000003f, 0x7ffffd06, 0x7ffffffa, 0x0000007f, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffe98e, 0x9248e13e, 0x00004e8d, 0xb6db6db6, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x3fffffbf, 0x80000080, 0x7fffffff, 0x7fffff80, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x000fa5ff, 0x80000000, 0x80000000, 0xffe0b401, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfe000001, 0x00000000, 0x03fffffe, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffff25, 0x00000000, 0x80000000, 0x000001b6, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xfffffff9, 0x00000007, 0xffffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000009, 0x80000000, 0x80000000, 0xffffffed, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000a809, 0x5ffabfb5, 0xe0000001, 0xfffabfb5, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfe666667, 0x30ccccce, 0x99999999, 0x03fffffe, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x000051b2, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000006, 0xfffffff2, 0x7fffffff, 0x0000000e, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x007155c7, 0x1caa7200, 0x8e38e38e, 0xff00ff00, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffff80, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000002, 0x7ffffec5, 0x8000003f, 0xfffffffb, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x0ffffff8, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xc0000003, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x07fffffb, 0xf0000008, 0x0ffffff8, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xe0000001, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffffd, 0x6db6db72, 0xfffffffa, 0x6db6db6d, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0ffffffc, 0x20000015, 0x80000003, 0xe0000007, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffe0e21, 0x8003e3bd, 0xfffc1c43, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffff8, 0x00000010, 0xfffffff0, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0x80000001, 0xffffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xc0000001, 0xfffffffd, 0x7fffffff, 0x80000003, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000000f, 0x7fffffe1, 0x0000001f, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffaaffaa, 0xff55ff56, 0xaaaaaaaa, 0x00ff00ff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xc0000003, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x80000000, 0x80000000, 0xffffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xd5555555, 0x80000000, 0x55555555, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xe26e778a, 0x00000000, 0x3b2310ec, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00159f32, 0x00001982, 0x000000d9, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000029, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7ffffff8, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x1ffffffc, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffffd, 0x8000001e, 0x00000005, 0x80000006, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffed, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x1ffffffe, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000111d, 0x4bab939c, 0xfef9f346, 0xffef47da, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xffff9d82, 0xfffffff2, 0x00000709, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xfffb09c5, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xff2d02c3, 0xa97e9e60, 0xf968161a, 0x1ffffff0, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffa5, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x000159d9, 0x00000000, 0x80000000, 0xfffd4c4e, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x3ffffffe, 0x00000003, 0x7fffffff, 0x7ffffffd, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000010, 0xfffffffe, 0xfffffff8, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffa1, 0x999999f8, 0x66666666, 0xffffff14, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x001eebe2, 0x9721b440, 0xfa7075b8, 0xfa7075b8, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffffe, 0x00000004, 0x7fffffff, 0xfffffffc, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x03ffffff, 0x80000004, 0x1ffffffe, 0x1ffffffe, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x80000000, 0xffffffff, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xfffffff4, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffff1, 0xa4223c13, 0x001dbb2f, 0xffff845d, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x28f5c28f, 0x0a3d70a4, 0x66666666, 0x66666666, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffdd95, 0x000044d6, 0xffffbb2a, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xf8e38e3c, 0x4e38e3a0, 0x3fffffe0, 0xe38e38e3, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffd32, 0xf43ba168, 0xfffeef0c, 0x02a0829e, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xff5c6f4b, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xe000000f, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x12492491, 0xdb6db6dc, 0x7fffffff, 0x24924924, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x002ed3b6, 0xfdce136c, 0xff44b124, 0xc0000003, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x02eb78cd, 0xfa290e64, 0x05d6f19c, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0x80000001, 0xffffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffffe, 0x80000030, 0xfffffffa, 0x3ffffff8, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000002, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfff48c2c, 0x916e7a6e, 0xff48c2c9, 0x0ffffffe, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x99999999, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x0187ef00, 0xfffe7811, 0xffffff00, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xc0000000, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfe000000, 0xbffffff0, 0x3ffffff0, 0xf8000001, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0x8000001e, 0x00000002, 0xc000000f, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000007, 0x7ffffff1, 0x0000000f, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xfff81c0c, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xf0000001, 0x3ffffffa, 0x3ffffffe, 0xc0000003, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xc0000000, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffe1, 0x400001ec, 0x1ffffffe, 0xffffff0a, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x38e38e3a, 0xe38e38e3, 0xfffffffe, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000039c, 0x4ffe31d8, 0x0ffffff8, 0x000039c5, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xc71c71c7, 0x80000000, 0x71c71c71, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x35250910, 0x000074a4, 0x000074a4, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x0001cc6c, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00006834, 0xfffffffa, 0xffffeea2, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffff21fd, 0x9a3e884e, 0xff209972, 0x00fe67df, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xff56b900, 0xfff78940, 0x00000014, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xf8000002, 0xffffffff, 0x07fffffe, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xfb83a9f5, 0x0000142f, 0xffffc71b, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000003d, 0x7fffff85, 0x0000007b, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xc0000000, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xc0000000, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xffe0894c, 0x0007ddad, 0xfffffffc, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xf9d62cdf, 0x80000000, 0x80000000, 0x0c53a641, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x1fffffef, 0xc0000020, 0x3fffffe0, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xf5ae1969, 0x94a3cd2d, 0x7fffffff, 0xeb5c32d3, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x7ffffffa, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xffffff46, 0x0000001f, 0xfffffffa, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xf8000002, 0xdfffffc8, 0x1ffffff8, 0xc0000007, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000001, 0x7ffffffd, 0x7fffffff, 0x00000003, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xfffa8ef6, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00ff00ff, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xfffeffce, 0x00005566, 0xfffffffd, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000002, 0x80000000, 0xfffffffb, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x04924924, 0x36db6db8, 0x24924924, 0x1ffffffe, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffe8787e, 0x00eb4b14, 0xffd0f0fc, 0x7ffffffb, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffffe, 0x00000040, 0xfffffffc, 0x7ffffff0, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffffd, 0x00000060, 0x7ffffff0, 0xfffffffa, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000007, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffd0, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x23925630, 0x00000006, 0x05edb908, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xc0000001, 0x7ffffffe, 0x7fffffff, 0x80000002, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffd5ed, 0x8003f1bc, 0xe0000003, 0x00015094, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffc59623, 0x00000000, 0x80000000, 0x0074d3ba, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0x00000000, 0x80000000, 0x00000002, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00090b11, 0x5f6f4eea, 0xff6f4eea, 0xf0000001, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x01fffffe, 0xfc000002, 0x7fffffff, 0x03fffffe, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00001756, 0x7fff73f9, 0x80000003, 0xffffd153, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffd0a, 0x705814cc, 0x000184ba, 0xfe0d199e, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xf0000003, 0x9ffffff9, 0xe0000007, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00016eb5, 0x1cf71a04, 0x00448344, 0x055a36b1, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000072c, 0x80000000, 0xfffff1a7, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xfbc0adf4, 0xfffffffc, 0x010fd483, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x24924924, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffe6, 0x80000000, 0x00000033, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xf9fa3ca4, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x07fffffc, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0028575c, 0x7faf5147, 0x7fffffff, 0x0050aeb9, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000001, 0x80000000, 0xfffffffd, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0020c263, 0x493a6936, 0xffb38fc3, 0x92492492, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x92492492, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7ffffffe, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0000003b, 0x924923a4, 0x24924924, 0x000001a1, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x1ffffff0, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xffffff97, 0xfffffff9, 0x0000000f, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x6614e9cb, 0x00000003, 0x2206f899, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xd5555555, 0x80000000, 0x55555555, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000010, 0xfffff780, 0x3fffffe0, 0x00000044, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffffe, 0x38e38e3c, 0xfffffffc, 0x71c71c71, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000ada, 0xfffd74ac, 0xffffd494, 0xc000000f, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xfffffffe, 0x80000000, 0x00000003, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x000e7bb8, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x06666665, 0x19999994, 0xe0000007, 0xcccccccc, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x40000000, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xfffffe1e, 0xfffffffe, 0x000000f1, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x0ffffff8, 0x80000000, 0x80000000, 0xe000000f, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x3fffffbf, 0x80000080, 0x7fffffff, 0x7fffff80, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000007, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x06666664, 0xc6666668, 0x66666666, 0x0ffffffc, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xfffffe04, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x0005f1dd, 0x00000000, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x3fffffe1, 0x000003c1, 0x8000001f, 0x8000001f, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xfffff12d, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0xffffffff, 0xfe8fe1ac, 0xfffffffe, 0x00b80f2a, 0x0, 0x0 - dspck_astio mult, 0x0, 0x0, 0x00000000, 0x00000000, 0xc000000f, 0x00000000, 0x0, 0x0 - - writemsg "[24] Test multu" - dspck_astio multu, 0x0, 0x0, 0xfe76f09e, 0xc2ab91bb, 0xfe770721, 0xffffe95b, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x000074a2, 0xf426fd5d, 0xffffe5ff, 0x000074a3, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x8e38936d, 0xc71c91d4, 0x8e38e38e, 0xffff6fc6, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7f8a380f, 0x80eb8fdf, 0x7fffffff, 0xff147021, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xcccccccc, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x33333333, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x03fffffe, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x40000006, 0x7fffffe2, 0x7ffffffe, 0x8000000f, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000007, 0x7ffffff1, 0x7fffffff, 0x0000000f, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x02e86b10, 0x80000000, 0x80000000, 0x05d0d621, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x0000019a, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x000006f6, 0x3fff909c, 0x1ffffffe, 0x000037b2, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000008, 0x7fffff89, 0x7ffffff9, 0x00000011, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x92492492, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00018e61, 0xfff9c678, 0xfffffffc, 0x00018e62, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ffffffc, 0x00000006, 0x7fffffff, 0xfffffffa, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0000052b, 0xfffff5a8, 0x7fffffff, 0x00000a58, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7f473cc5, 0x80000000, 0xfe8e798b, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xf0000003, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x07fffffe, 0xf0000002, 0x0ffffffe, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0xdb6cdb6d, 0x49250000, 0xdb6db6db, 0xffff0000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x0000000f, 0x00000003, 0x00000005, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x9225e90d, 0x6dc87930, 0x92492492, 0xffc257d8, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x000a182c, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0630fe6a, 0x00000000, 0x80000000, 0x0c61fcd4, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7ffffff9, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00ff00f6, 0xdd22dd2b, 0xfffff7d5, 0x00ff00ff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xfff85e98, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ffe475d, 0x0006e284, 0xfffc8ebe, 0x7ffffffe, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffff06, 0x00000000, 0x80000000, 0xfffffe0c, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffffff, 0x00000000, 0xfffffffe, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0xe1000005, 0xa0000009, 0xf0000003, 0xf0000003, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ff24291, 0x001b7adc, 0x7fffffff, 0xffe48524, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x80000000, 0x00000001, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fc59261, 0x0074db3c, 0xff8b24c4, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x03fffffe, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x020fc465, 0xfbe07734, 0x7fffffff, 0x041f88cc, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x37fffff2, 0x3ffffff0, 0x3ffffff0, 0xe0000001, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xfffffff9, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x018a5afd, 0x16485b28, 0x38e38e38, 0x06ee9973, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x14b59aac, 0x001069e4, 0x00000143, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffffff, 0x00000000, 0xfffffffe, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xffff0000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000015, 0xfffff584, 0x00000016, 0xffffff86, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x50c299ad, 0x01482b13, 0x0000003f, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x032edfac, 0x4d120538, 0x3ffffffc, 0x0cbb7eb2, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000063, 0x80000000, 0x000000c7, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xe000000f, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x05e1578d, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3fffffdf, 0x80000040, 0x7fffffff, 0x7fffffc0, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x70000001, 0x60000001, 0xe0000001, 0x80000001, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x051c66dc, 0xf5c73246, 0x051c66dd, 0xfffffffe, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ffffff0, 0x80000000, 0xffffffe1, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0ffffffd, 0xa000000c, 0x1ffffffc, 0x7ffffffd, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xfffe8fd3, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3ffffffc, 0x80000000, 0x80000000, 0x7ffffff9, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ffffffe, 0x00000000, 0xfffffffc, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xe38e38e3, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ffffffc, 0x80000005, 0xfffffffb, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x03fffffe, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000112, 0xfffdf3c8, 0xfffffe18, 0x00000113, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x038e38e3, 0x0e38e390, 0x1ffffffc, 0x1c71c71c, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xf0f0f0f0, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x4000001f, 0x80000000, 0x8000003f, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00b125e3, 0x1c9a1dfc, 0x00ec3284, 0xc000001f, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xcccccccc, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ff6577f, 0xffecaefe, 0x80000001, 0xffecaefe, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xdb6db6db, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x0000002a, 0x0000000e, 0x00000003, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000e71, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0xff872168, 0x00f1bd2c, 0xff87216a, 0xfffffffe, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0ffffffc, 0x00000000, 0x1ffffff8, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7e68000b, 0x00000000, 0x80000000, 0xfcd00016, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xffff0000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000003, 0x677d987f, 0x0000ffff, 0x00036781, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffffff, 0x80000000, 0x80000000, 0xffffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x000003c0, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ff831e4, 0x80000000, 0x80000000, 0xfff063c9, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x009abdbd, 0xff654242, 0x00e81c9d, 0xaaaaaaaa, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000942, 0x38e36930, 0x00005354, 0x1c71c71c, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0xfffdaeea, 0x52fcab79, 0xffffd9b5, 0xfffdd535, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x5397829c, 0x687d6344, 0x92492492, 0x92492492, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xc71c71c7, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x6db6ae6e, 0xb6dbb8b4, 0xffff9704, 0x6db6db6d, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x000079c8, 0x00000000, 0x0000f390, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffff89, 0x80000000, 0x80000000, 0xffffff13, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000002, 0x00000000, 0x00000004, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3ffffffc, 0x00000007, 0x7fffffff, 0x7ffffff9, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00085b36, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000015, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x329161f8, 0xfcd6e9e1, 0x71c71c71, 0x71c71c71, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000fff, 0xeffe0002, 0x0000ffff, 0x0ffffffe, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x0000005c, 0x0000002e, 0x00000002, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0xffffb839, 0x0002cd62, 0xffffb843, 0xfffffff6, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffceec, 0x00000000, 0x80000000, 0xffff9dd8, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0xffffcf4a, 0x004def30, 0xfffffe58, 0xffffd0f2, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3ffffffb, 0x80000008, 0x7ffffff8, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffff24, 0x80000000, 0x80000000, 0xfffffe49, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000001, 0xfffffffc, 0x7fffffff, 0x00000004, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x000009ee, 0x5af151c4, 0x001e4dca, 0x0053e53a, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x06f539d5, 0x92a45fc4, 0x08b2884b, 0xcccccccc, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fc9ef10, 0xfd773484, 0xff93de16, 0x80000006, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffffc6, 0x80000000, 0xffffff8d, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ffffffb, 0x00000008, 0x7fffffff, 0xfffffff8, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000003, 0xfc03fc00, 0x00000004, 0xff00ff00, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffff15, 0x00000000, 0x80000000, 0xfffffe2a, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x8000001f, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000074, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x000001a4, 0x00000000, 0x00000348, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0574b162, 0xcaca899b, 0x0574cbe1, 0xfffb24fb, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x40000000, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0efffffe, 0x4ffffffa, 0xf0000003, 0x0ffffffe, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x000000d1, 0x7ffff2e8, 0x00000346, 0x3ffffffc, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x30000000, 0x69999999, 0x33333333, 0xf0000003, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0xffffffff, 0x80000001, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x093a7f8a, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00007735, 0xffff88ca, 0x00007736, 0xffffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x009488a6, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7f057c01, 0x944d7360, 0x8e38e38e, 0xe4a378d0, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0064c309, 0xfcd9e7b0, 0x00c98614, 0x7ffffffc, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0000000f, 0x80000000, 0x80000000, 0x0000001f, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ffffffe, 0x80000000, 0xfffffffd, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000003, 0xdfffffc2, 0x0000001f, 0x1ffffffe, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x0ffffff8, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0dfb8d31, 0x6408e59d, 0x1bf71a63, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xffffffa0, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xc0000003, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x40000003, 0x80000000, 0x80000007, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0xf8000001, 0x0ffffffa, 0xf8000003, 0xfffffffe, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0003f590, 0xfe053780, 0x7fffffc0, 0x0007eb22, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000003, 0xfff80180, 0xfffe0060, 0x00000004, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0000001f, 0x80000000, 0x0000003f, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00041824, 0x00000206, 0x00000206, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x749e996a, 0x96c2cd29, 0xe93d32d7, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0000010f, 0x8fffbc1c, 0x000021f2, 0x07fffffe, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00878b27, 0x000066f7, 0x00000151, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000003, 0x00000000, 0x00000006, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xc000000f, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xfff168d9, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00ff00fe, 0x47b847b9, 0x00ff00ff, 0xffffff47, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7c000007, 0x50000012, 0x80000006, 0xf8000003, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00c11193, 0x0003c921, 0x00000033, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffffeb, 0x00000028, 0x7fffffff, 0xffffffd8, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00003a82, 0x7ffe2bec, 0x00007505, 0x7ffffffc, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xfffffffa, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x01145411, 0xf534b74c, 0x0228a824, 0x7ffffffb, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xffffffdb, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x000001c0, 0x7ffffc7f, 0x00000381, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xf8000001, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x33333333, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000004, 0xfffffff6, 0x0000000a, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x66666666, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x1b27e4eb, 0xa9477b41, 0xdb6db6db, 0x1fae8b13, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x0000be96, 0x0000261e, 0x00000005, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x55555551, 0xaaaaaaae, 0xfffffff6, 0x55555555, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xe000000f, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0003995e, 0xfff8cd42, 0xfffffffe, 0x0003995f, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3ffffffc, 0x80000006, 0x7ffffffa, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000018, 0xdb6db6b2, 0x0000003a, 0x6db6db6d, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ffff9a6, 0x80000000, 0x80000000, 0xfffff34d, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ffffffe, 0x80000001, 0x7fffffff, 0xffffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x0000ffff, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x0000000f, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x5555555e, 0xfffffff6, 0xaaaaaaaa, 0x8000000f, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0000045c, 0x7ffff747, 0x000008b9, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x40000000, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0ffffffd, 0xe0000004, 0x1ffffffc, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x0f47fd80, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x61861860, 0xf3cf3cf4, 0x92492492, 0xaaaaaaaa, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x000b3ecb, 0xbc200518, 0x000b3ede, 0xfffe6034, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x6fffffff, 0x9fffffff, 0xe0000001, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x965ed6bb, 0x9649f1c4, 0xc43375ce, 0xc43375ce, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x01a780d2, 0xfcb0fe5a, 0x034f01a6, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x000147f5, 0xfffeb80a, 0x000147f6, 0xffffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0000001d, 0x1000001f, 0x0000001f, 0xf0000001, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0xff2e87d4, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000001, 0x493e3209, 0x0000001f, 0x0a9ee8d7, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x07cebd1b, 0x00000001, 0x07cebd1b, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0000000c, 0x8787877b, 0x000000d5, 0x0f0f0f0f, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x05d59a7e, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffc139, 0x00007d8c, 0x7fffffff, 0xffff8274, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0xffaa6169, 0xffaa6169, 0x00000001, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000026, 0x00000000, 0x0000004c, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x000021e6, 0xc9462000, 0x0000b200, 0x30c1d990, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x4000000d, 0x7fffff84, 0x8000001f, 0x7ffffffc, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x1999999a, 0x4ccccccc, 0x33333333, 0x80000004, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffffc2, 0xfffffe80, 0xffffff80, 0x80000003, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x1c71c71b, 0xc71c71c8, 0x1c71c71c, 0xfffffffe, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0xeffffffb, 0x7fffffe8, 0xfffffff8, 0xf0000003, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0000001a, 0x00000000, 0x00000034, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x004dffc5, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xb6db6db6, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x80000002, 0x7ffffffd, 0xffffffff, 0x80000003, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xfffffb6c, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3ffffff0, 0x00000000, 0x7fffffe0, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x1fffffff, 0xa4924924, 0xe0000001, 0x24924924, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000007, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x78afbbdb, 0x1d41108c, 0x7ffffffe, 0xf15f77ba, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7f807f80, 0x00000000, 0x80000000, 0xff00ff00, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x01865853, 0x80000000, 0x80000000, 0x030cb0a7, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x276b6547, 0x0d23cc6d, 0x00000003, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7ffffffe, 0x80000001, 0xffffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fff8000, 0x00000000, 0x80000000, 0xffff0000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x3fffffff, 0x00000001, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x7fffffff, 0x00000000, 0xfffffffe, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x000001e3, 0x00004dfc, 0xc000001f, 0x00000284, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0xf9e53251, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x4000003d, 0xfffffe83, 0x8000007f, 0x7ffffffd, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x40000001, 0x00000000, 0x80000002, 0x80000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x0000795a, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x003dbb65, 0x00000000, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x000024fc, 0x0000062a, 0x00000006, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0xb216ed65, 0x736f7568, 0xf9534c5c, 0xb6db6db6, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x0fcf55dc, 0xc0c2a88c, 0x0fcf55dd, 0xfffffffc, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x6db6c500, 0xb6db9316, 0x6db6db6d, 0xffffcbae, 0x0, 0x0 - dspck_astio multu, 0x0, 0x0, 0x00000000, 0x00000000, 0x00000000, 0x00ff00ff, 0x0, 0x0 - - writemsg "[25] Test precr.qb.ph" - dspck_dstio precr.qb.ph, 0x997ce000, 0xfa99ff7c, 0x1fe08000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0008ff00, 0x80000008, 0x7fff8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xbd1e1b49, 0xe1bd001e, 0x001b9249, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf848d166, 0x0ff80448, 0xfdd10a66, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0600feab, 0x00068000, 0xfffe1cab, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xffff023e, 0x7fffffff, 0x0002003e, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfe3300e6, 0xfffe3333, 0x8000fbe6, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xdbffffe9, 0xb6db7fff, 0xffffd3e9, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00000092, 0x00000000, 0x0000f892, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0080ff53, 0x80007f80, 0x7fff0753, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x006e0306, 0x8000ff6e, 0xe0030006, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x88dbf0f7, 0x0088b6db, 0x7ff000f7, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xaae5aac3, 0xaaaaffe5, 0xfcaa07c3, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfdfe5549, 0xfffd3ffe, 0x55559249, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x05e1acff, 0x8005ffe1, 0x09ac7fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x000007fe, 0x00000000, 0xc0071ffe, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xe7fbdfde, 0xfee77ffb, 0xebdf02de, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfe0133ff, 0x1ffe0001, 0xfd337fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfa793f02, 0x7ffa0c79, 0x803f0002, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf9ff0000, 0xfff97fff, 0x00008000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x8eff0122, 0xe38e7fff, 0xf0010022, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00e80000, 0x0000ffe8, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xffffe300, 0x7fff7fff, 0xffe30000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00ff000a, 0x00007fff, 0x0000000a, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x3fff1f00, 0xc03f7fff, 0x801f8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x1300fff8, 0x00130000, 0x7fff3ff8, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0000c366, 0x00000000, 0x00c36666, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfffd0094, 0x7ffffffd, 0x80000094, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0000e3ff, 0x00000000, 0x38e3ffff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfdc3f600, 0xfffdffc3, 0x02f60000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x03f800ff, 0x00031ff8, 0x00007fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xeb00e04a, 0xffeb8000, 0xffe0024a, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfefffd8e, 0x0ffe7fff, 0xfffdf78e, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfff8b901, 0x00fffff8, 0xf3b9c001, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x3a330000, 0x003a3333, 0x00008000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff023ffe, 0x7fff8002, 0xc03f07fe, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xaae0ff02, 0xaaaaffe0, 0x7fff0002, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xffc0ff49, 0x7fff3fc0, 0x7fff3949, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff00af00, 0x7fff8000, 0x0faf0000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff000005, 0x7fff0000, 0x80008005, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x03000000, 0x00030000, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf038fa00, 0x7ff08e38, 0xfffa8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0060036d, 0x00000060, 0x0003ff6d, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00000f5c, 0x00000000, 0xf90fdd5c, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xffff3392, 0x7fffffff, 0x33332492, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x07800001, 0xf007ff80, 0xff008001, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00fcf803, 0x80000ffc, 0x3ff8f003, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x07fffff0, 0xc0077fff, 0x7ffff0f0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0f354101, 0xc00fff35, 0x0441f801, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff02fc03, 0x7fff0002, 0x3ffcf803, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xb1ffb1ff, 0x00b17fff, 0x00b17fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x33f005ff, 0x3333fff0, 0x80057fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x3fffff00, 0xc03f7fff, 0x7fff0000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfc000000, 0x3ffc8000, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x09003855, 0x00098000, 0x8e385555, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xe0fff8fc, 0xffe07fff, 0xfff8fffc, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0000240f, 0x00000000, 0x4924000f, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x07c003f0, 0xf0077fc0, 0xe003f0f0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff000000, 0x7fff0000, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00dd0000, 0x80000cdd, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xe80000f8, 0xffe80000, 0x8000fff8, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x38490c04, 0x8e38f549, 0x000c8004, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf1fef9f9, 0xfff1fffe, 0xfff97ff9, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xffa13f00, 0x7fffffa1, 0xc03f8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00ff00ff, 0x80007fff, 0x80007fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfc000105, 0x7ffc0000, 0xf8010005, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff000000, 0x7fff8000, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0002ff49, 0x80008002, 0xffff9249, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0100fdc8, 0x80018000, 0xfffd02c8, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf001ff00, 0x7ff00001, 0x7fff0000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0005f800, 0x00000005, 0x7ff88000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00fe00fe, 0x8000fffe, 0x8000fffe, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x3fc0ff00, 0xc03f3fc0, 0x7fff0000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf80001fd, 0x3ff88000, 0x00017ffd, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0001ff87, 0x00000001, 0x7ffffe87, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf96600ff, 0xfff9f566, 0x8000ffff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x6d7efef2, 0xdb6d007e, 0x07fefff2, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfffc0000, 0x7fff1ffc, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00e2c7ff, 0x0000ffe2, 0x71c77fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0001fff8, 0x8000fc01, 0x7fff1ff8, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xdb03dfc0, 0xffdb0003, 0xe6dfffc0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf8009200, 0x1ff88000, 0x24920000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00801c00, 0x00007f80, 0xc71c8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00cc0ee4, 0x8000cccc, 0x000effe4, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x15180000, 0xfe150318, 0x80000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf8000000, 0x0ff88000, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xe1001cff, 0xfde10000, 0xc71c7fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00f800f3, 0x80003ff8, 0x000035f3, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfffe0103, 0x7fff7ffe, 0x80010003, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfcf9fcf9, 0xfffc7ff9, 0xfffc7ff9, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0000e300, 0x80008000, 0x38e30000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00fffd08, 0xff007fff, 0xfffd1008, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x015cfc00, 0xfc01fb5c, 0xfffc0000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfe130000, 0x0ffe0113, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x7805f001, 0x00780005, 0xf0f0c001, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x06ffff2f, 0xf0067fff, 0x7fff002f, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x000017e0, 0x80000000, 0x0a173fe0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf7c0061c, 0xfff73fc0, 0x8006fa1c, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfcc400eb, 0x07fce9c4, 0xff00f3eb, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x03808fff, 0xe003ff80, 0x1c8fffff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x3cf0fcf0, 0x003cf0f0, 0xfffcfff0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x01f50800, 0xf001fff5, 0x00088000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfc070f01, 0xfffcc007, 0x800fc001, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x3ff30366, 0x803ffff3, 0x00036666, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x7f5700ff, 0x2b7f0257, 0xec007fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xffd1c07f, 0x7fff26d1, 0x3fc0007f, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0801c747, 0x0008f001, 0x71c7fc47, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xe0994f00, 0x7fe09999, 0x094f8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x3c238e01, 0xff3cef23, 0xe38ec001, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x02fc0462, 0x0002fffc, 0x00040f62, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf8018bf9, 0xfff8e001, 0x018bfff9, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xb6fff001, 0x6db6ffff, 0xfff0e001, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xed000000, 0x02ed8000, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff03ff00, 0xfffff803, 0x7fff8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf805f805, 0xfff88005, 0xfff88005, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xe7ee3f33, 0xe2e731ee, 0x803f3333, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00fe0000, 0x00001ffe, 0x80000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00f91f00, 0x8000fff9, 0xe01f0000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x89fc0000, 0xff890ffc, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfb07e767, 0xfffbc007, 0xffe70167, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x3360fab6, 0x0033fe60, 0xfffa6db6, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfb00fe00, 0x7ffb0000, 0xfffe8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00011c1b, 0x8000c001, 0xc71c001b, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfff8fff8, 0x7fff1ff8, 0x7fff1ff8, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff8f71fe, 0xfffff88f, 0x1c717ffe, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0306fce0, 0x00038006, 0xfffc7fe0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x000000ff, 0x00008000, 0x0000ffff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x4a00ffcb, 0xff4a8000, 0x7ffff8cb, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00ff3300, 0x00007fff, 0x33330000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00e00000, 0x00003fe0, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x9202f8ff, 0x24920002, 0x1ff800ff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00fa1c00, 0x0000fffa, 0xc71c8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x1f3fc03f, 0xc01fc03f, 0xffc0003f, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00f00000, 0x80003ff0, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x24ff1e00, 0x49247fff, 0x0e1e0000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x5dff5dff, 0xfe5dffff, 0xfe5dffff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00c0ffea, 0x00007fc0, 0x7fff00ea, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00000000, 0x00008000, 0x00008000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfffff713, 0x7fff7fff, 0x01f70013, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x01c9b6de, 0x8001ffc9, 0xe4b6fcde, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00000007, 0x00000000, 0x80008007, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xc800d151, 0x00c88000, 0xffd10351, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xeaf80000, 0xffea3ff8, 0x80000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x92fcfc2b, 0x24923ffc, 0xfffcf72b, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfe10a803, 0x03fe0310, 0xffa8c003, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x003f51f2, 0x8000803f, 0xfe51d6f2, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0fbcfcff, 0x800fffbc, 0xfffc7fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x71000ef0, 0x1c718000, 0x0e0ef0f0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00ff0001, 0x80007fff, 0x00000001, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x22f0e005, 0x00221ff0, 0x11e00005, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xffa506ff, 0x7ffff8a5, 0x00067fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00b9faa3, 0x8000ffb9, 0xfffaffa3, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00f0c7fb, 0x00003ff0, 0xf3c77ffb, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfe6dd500, 0xfffedb6d, 0xfed58000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00ff8bf2, 0x00007fff, 0xff8bfff2, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00ff8cf0, 0x00007fff, 0x018cf0f0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x01003f86, 0xf8018000, 0xc03f0086, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff008c07, 0x7fffff00, 0xf18cf007, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfb3f3600, 0xfffb003f, 0xff360000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x000c1f00, 0x0000fc0c, 0x801f0000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x000008b1, 0x00000000, 0x0008fab1, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xaaffaaff, 0xaaaaffff, 0xaaaaffff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00fcfee3, 0x8000fffc, 0x07feffe3, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0000feff, 0x80000000, 0x0ffe7fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00330033, 0x80001e33, 0x80001e33, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfc00fecc, 0x07fc8000, 0xfffecccc, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf904ff02, 0xfff90004, 0x7fff0002, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00fd002b, 0x0000fffd, 0x8000ff2b, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x1c6dfc00, 0xc71cdb6d, 0x1ffc8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf8fe49fc, 0xfff83ffe, 0x92491ffc, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfb3f0480, 0xfffbc03f, 0x0004ff80, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xda1500f0, 0x27da0015, 0x80003ff0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x3f00009a, 0x803f8000, 0x0000fe9a, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xaafff001, 0xaaaa7fff, 0x3ff0fc01, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0004ff71, 0x00000004, 0x7ffff271, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00f80000, 0x80003ff8, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x006a0000, 0x8000016a, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x01a04801, 0xf001f5a0, 0x1f480001, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x05ffffb1, 0x80057fff, 0x00ff00b1, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0000ffff, 0x00000000, 0x7fff7fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x40ff40ff, 0x00407fff, 0x00407fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x07fff538, 0xf007ffff, 0xfff58e38, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0000002e, 0x80008000, 0x8000df2e, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x4800b200, 0xff480000, 0xfcb28000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xc0ff0000, 0x7fc07fff, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x000007fc, 0x00000000, 0x00070ffc, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff3ffffe, 0x7ffffc3f, 0x7ffffffe, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x005f00ff, 0x8000005f, 0x00007fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfeff80aa, 0x07fe7fff, 0x7f80aaaa, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0000250e, 0x00000000, 0xff25000e, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf30100c0, 0xfff30001, 0x8000fbc0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfc00ffc2, 0xfffc8000, 0x7fff00c2, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xf6ff6a05, 0x00f67fff, 0xff6a0005, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x38004100, 0x8e380000, 0x01418000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00000f00, 0x80008000, 0xe00f8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x491cf0ff, 0x0049001c, 0xf0f07fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x051f16f8, 0x0005801f, 0x01161ff8, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xefb6c9f0, 0xffef6db6, 0xdac97ff0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff6fff6f, 0x7fffea6f, 0x7fffea6f, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x019d0000, 0x0001ff9d, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00003b8b, 0x00008000, 0x003b028b, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x1a29ff06, 0x001a0029, 0x7fff8006, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xd3d2fffc, 0x1ad3f3d2, 0x7fff7ffc, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff000000, 0x7fff8000, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x12f07a00, 0x00127ff0, 0xfe7a8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfffffa00, 0x7fff7fff, 0xfffa0000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x007a0000, 0x0000007a, 0x00000000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfffdfffd, 0x7fff7ffd, 0x7fff7ffd, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x000003ff, 0x00000000, 0xe0037fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0f010f01, 0x800ffc01, 0x800ffc01, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0001f1fe, 0x80000001, 0xfff1fffe, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00000003, 0x00008000, 0x00000003, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00fb0f09, 0x80007ffb, 0xc00f0009, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x7f5501ff, 0x807f5555, 0x00017fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfcff00ff, 0x0ffc7fff, 0x80007fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfef8ef00, 0xfffefff8, 0xfeef0000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x03f60083, 0x0003fff6, 0x80000a83, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x1ffe0725, 0x801f1ffe, 0x00070b25, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfffff700, 0x7fff7fff, 0xfff70000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x005c0100, 0x8000025c, 0x00010000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0146ff00, 0x00010046, 0x7fff8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfff9fffe, 0x7ffffff9, 0x7ffffffe, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x1f0266e0, 0x001f0002, 0x66661fe0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfe00031f, 0xfffe0000, 0xc003801f, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0000ff35, 0x00000000, 0x7fff0035, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff00001f, 0x7fff0000, 0x8000011f, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x9c1c010a, 0xd39cc71c, 0x0001000a, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xff070077, 0x7fffc007, 0x0000ff77, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x1efe008f, 0x051efffe, 0x8000ff8f, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xbb03fec0, 0xffbbf803, 0xfffe3fc0, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0002fe00, 0x80000002, 0x3ffe8000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xddffddff, 0xffdd7fff, 0xffdd7fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x00001fff, 0x00008000, 0x801f7fff, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xb6c7fe00, 0x6db6ffc7, 0x3ffe0000, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x0ff800f1, 0x000ffff8, 0x0000fff1, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x1a2c008d, 0x011aff2c, 0x0000ff8d, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x03d00209, 0x0303ffd0, 0x8002d309, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x028bfffd, 0x0002ff8b, 0xffff7ffd, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0x000000fe, 0x00000000, 0x0000fffe, 0x0, 0x0 - dspck_dstio precr.qb.ph, 0xfff90000, 0x7ffffff9, 0x00000000, 0x0, 0x0 - - writemsg "[26] Test precr_sra.ph.w" - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 13 - dspck_tsimm precr_sra.ph.w, 0x00000028, 0x0000ffff, 0x00283a6e, 16 - dspck_tsimm precr_sra.ph.w, 0xffffffc0, 0x7fffffff, 0xffffffc0, 0 - dspck_tsimm precr_sra.ph.w, 0xf0f00000, 0xf0f0f0f0, 0x00000000, 0 - dspck_tsimm precr_sra.ph.w, 0x71c7fffe, 0x38e38e38, 0xfffffff0, 3 - dspck_tsimm precr_sra.ph.w, 0x000fffff, 0x7fffffff, 0xf8000003, 27 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00004aa2, 0x00000010, 31 - dspck_tsimm precr_sra.ph.w, 0x0000fffc, 0x00000004, 0x80000000, 29 - dspck_tsimm precr_sra.ph.w, 0x55558e38, 0x55555555, 0x38e38e38, 0 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffffeb, 0x000019ad, 31 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0xf0000001, 0x00000000, 2 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x0ffffff8, 0x7fffffff, 31 - dspck_tsimm precr_sra.ph.w, 0x1fff1fff, 0x7fffffff, 0x7fffffff, 18 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x7fffffff, 0x00000000, 3 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0xfffffff9, 31 - dspck_tsimm precr_sra.ph.w, 0xdb6d0734, 0xb6db6db6, 0x00073400, 8 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0xfffee2a8, 29 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xfff8c7ef, 0x00000000, 30 - dspck_tsimm precr_sra.ph.w, 0xaa370000, 0xff0daa37, 0x00000000, 0 - dspck_tsimm precr_sra.ph.w, 0x55550000, 0x55555555, 0x80000000, 12 - dspck_tsimm precr_sra.ph.w, 0x92490000, 0x92492492, 0x00000000, 1 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x7fffffff, 0x00000000, 3 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000007, 0x00000000, 30 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x7fffffff, 0x00000000, 31 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0x7fffffff, 0xfffffffd, 6 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xff00ff00, 0x7ffffffb, 31 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffffff, 0x0000245d, 31 - dspck_tsimm precr_sra.ph.w, 0xfffb007f, 0x7ffffffb, 0x8000007f, 0 - dspck_tsimm precr_sra.ph.w, 0xffe5ffff, 0xffffffe5, 0x7fffffff, 0 - dspck_tsimm precr_sra.ph.w, 0x0007ffff, 0x7fffffff, 0xfe942219, 28 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0x7fffffff, 0 - dspck_tsimm precr_sra.ph.w, 0x00ff00ff, 0x000000ff, 0x000000ff, 0 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffff2f, 0x00000000, 31 - dspck_tsimm precr_sra.ph.w, 0x001f0000, 0x8000001f, 0x80000000, 0 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x3ffffffc, 0x7fffffff, 31 - dspck_tsimm precr_sra.ph.w, 0x00002492, 0x80000000, 0x92492492, 0 - dspck_tsimm precr_sra.ph.w, 0xc000f800, 0x80000000, 0xf0000001, 17 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xc71c71c7, 0x07fffffe, 31 - dspck_tsimm precr_sra.ph.w, 0x0000ffa3, 0x80000000, 0xfffffd1d, 3 - dspck_tsimm precr_sra.ph.w, 0xffff0230, 0x7fffffff, 0x00000230, 0 - dspck_tsimm precr_sra.ph.w, 0x0000fffc, 0x00000000, 0x80000000, 29 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000006, 0x7fffffff, 9 - dspck_tsimm precr_sra.ph.w, 0x0002ffff, 0x00000005, 0x7fffffff, 1 - dspck_tsimm precr_sra.ph.w, 0xfffffef5, 0x7fffffff, 0xfffffef5, 0 - dspck_tsimm precr_sra.ph.w, 0x912b5555, 0x0832912b, 0x55555555, 0 - dspck_tsimm precr_sra.ph.w, 0xb4c30002, 0xfd05b4c3, 0x00000002, 0 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x0000000f, 0x7ffffff9, 4 - dspck_tsimm precr_sra.ph.w, 0xff80fff1, 0xffffff80, 0xfffffff1, 0 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x80000000, 0x0000705a, 31 - dspck_tsimm precr_sra.ph.w, 0x0000ff00, 0x00000000, 0xffffff00, 0 - dspck_tsimm precr_sra.ph.w, 0x3af90000, 0xffba75f2, 0x80000000, 1 - dspck_tsimm precr_sra.ph.w, 0x07ffffff, 0x1ffffff0, 0xfffffeae, 18 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xfffffff9, 0x80000000, 10 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000049, 10 - dspck_tsimm precr_sra.ph.w, 0x0000ab83, 0x80000000, 0x000b5706, 1 - dspck_tsimm precr_sra.ph.w, 0xffc0ffc0, 0x80000000, 0x8000007f, 25 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000002, 27 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffffb1, 0x00000015, 31 - dspck_tsimm precr_sra.ph.w, 0xf83d0000, 0x00ddf07a, 0x00000000, 1 - dspck_tsimm precr_sra.ph.w, 0x0000fff8, 0x80000000, 0x3ffffff8, 0 - dspck_tsimm precr_sra.ph.w, 0x0000fffc, 0x00000000, 0x0ffffffc, 0 - dspck_tsimm precr_sra.ph.w, 0x0003ffff, 0xc0000003, 0x7fffffff, 0 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xc0000001, 0x00000000, 31 - dspck_tsimm precr_sra.ph.w, 0xfffc0000, 0xfffffffc, 0x00000000, 0 - dspck_tsimm precr_sra.ph.w, 0xfff9ffff, 0xfffffff9, 0x7fffffff, 0 - dspck_tsimm precr_sra.ph.w, 0xffea3aef, 0xffffffea, 0xffff3aef, 0 - dspck_tsimm precr_sra.ph.w, 0xffff0003, 0xffff4871, 0x19692a52, 27 - dspck_tsimm precr_sra.ph.w, 0xfffe0000, 0xfcb6a83c, 0x00000000, 25 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x3fffffe0, 0x7ffffffc, 31 - dspck_tsimm precr_sra.ph.w, 0xc71caaaa, 0x38e38e38, 0x55555555, 1 - dspck_tsimm precr_sra.ph.w, 0x5e5cfffe, 0x00017971, 0x7ffffffa, 2 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000004, 0x80000000, 6 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x0001114c, 0x000000dd, 27 - dspck_tsimm precr_sra.ph.w, 0x00000001, 0x80000000, 0xf8000003, 1 - dspck_tsimm precr_sra.ph.w, 0xfc6770e9, 0xfffff8cf, 0x3142e1d3, 1 - dspck_tsimm precr_sra.ph.w, 0x9eb0f0f0, 0x00029eb0, 0xf0f0f0f0, 0 - dspck_tsimm precr_sra.ph.w, 0x000bfffe, 0x00000017, 0x7ffffffc, 1 - dspck_tsimm precr_sra.ph.w, 0x78720003, 0xeb027872, 0xf8000003, 0 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffbc1b, 0x33333333, 31 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x0001bfb2, 0x7ffffffa, 31 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x7fffffff, 0x80000000, 2 - dspck_tsimm precr_sra.ph.w, 0xfffffff1, 0x7fffffff, 0xfe67ff8f, 3 - dspck_tsimm precr_sra.ph.w, 0x6666fd7d, 0x66666666, 0xfffffd7d, 0 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000001, 0x0000003f, 6 - dspck_tsimm precr_sra.ph.w, 0xffffb6db, 0x7fffffff, 0xdb6db6db, 0 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x014f24fb, 31 - dspck_tsimm precr_sra.ph.w, 0x6db60000, 0x6db6db6d, 0x80000000, 10 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x0f0f0f0f, 31 - dspck_tsimm precr_sra.ph.w, 0xffc0bb38, 0x7fffffc0, 0x0d50bb38, 0 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xfffffff9, 0x000001ca, 13 - dspck_tsimm precr_sra.ph.w, 0xb152ffff, 0xffff62a4, 0x7fffffff, 1 - dspck_tsimm precr_sra.ph.w, 0x0fffffff, 0x07fffffe, 0x7fffffff, 15 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0x3ffffffe, 0x7ffffffe, 1 - dspck_tsimm precr_sra.ph.w, 0xff920000, 0xffe489b1, 0x0000000b, 14 - dspck_tsimm precr_sra.ph.w, 0x34df7f80, 0x1e9469bf, 0xff00ff00, 1 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x02728de8, 0xffff5c80, 30 - dspck_tsimm precr_sra.ph.w, 0xffff5f0d, 0x7fffffff, 0x00045f0d, 0 - dspck_tsimm precr_sra.ph.w, 0xfffefea8, 0xfffffffe, 0xfffffea8, 0 - dspck_tsimm precr_sra.ph.w, 0x0000fc00, 0x00000000, 0xf0000001, 18 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xff8942a6, 0x7fffffc0, 31 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 31 - dspck_tsimm precr_sra.ph.w, 0x7c470000, 0x0f88e8b9, 0x80000000, 13 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x1ffffffc, 0x00000000, 8 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x7fffffff, 0x7fffffff, 31 - dspck_tsimm precr_sra.ph.w, 0x1249fe20, 0x00001249, 0xfffffe20, 0 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xfffe8e4d, 0x00000007, 29 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xfff8431e, 0xf0000001, 31 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00011d30, 0x000003ea, 30 - dspck_tsimm precr_sra.ph.w, 0xfffefffe, 0x7ffffffa, 0x7ffffff8, 2 - dspck_tsimm precr_sra.ph.w, 0x00003fc0, 0x80000000, 0xff00ff00, 2 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x80000000, 0x7fffffff, 0 - dspck_tsimm precr_sra.ph.w, 0x0028ffe1, 0x0000028e, 0xfffffe18, 4 - dspck_tsimm precr_sra.ph.w, 0x00006b69, 0x80000000, 0x004c6b69, 0 - dspck_tsimm precr_sra.ph.w, 0x00010072, 0xf8000001, 0x00000072, 0 - dspck_tsimm precr_sra.ph.w, 0x5154ffff, 0xfda8aa16, 0xffffff80, 7 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 31 - dspck_tsimm precr_sra.ph.w, 0x003f0001, 0x7fffffff, 0x038f9b87, 25 - dspck_tsimm precr_sra.ph.w, 0x0fff0000, 0x3fffffe0, 0x00000000, 18 - dspck_tsimm precr_sra.ph.w, 0xfffc0000, 0xc000001f, 0x00000000, 28 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xff00ff00, 0x00000006, 31 - dspck_tsimm precr_sra.ph.w, 0xfe40fead, 0xfffffe40, 0xfffffead, 0 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 2 - dspck_tsimm precr_sra.ph.w, 0xfcbc001a, 0xfffff978, 0x00000034, 1 - dspck_tsimm precr_sra.ph.w, 0x2492fffc, 0x24924924, 0x0ffffff8, 1 - dspck_tsimm precr_sra.ph.w, 0x65590000, 0x09f19567, 0xf8000001, 2 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x0004db12, 0x00000000, 31 - dspck_tsimm precr_sra.ph.w, 0x00070007, 0xc0000007, 0xc0000007, 0 - dspck_tsimm precr_sra.ph.w, 0x0000f807, 0x80000000, 0x00ff00ff, 5 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0x7fffffff, 6 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000004, 0x00000004, 3 - dspck_tsimm precr_sra.ph.w, 0x7fff0000, 0x7fffffff, 0x00000003, 16 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xe000000f, 0xe000000f, 31 - dspck_tsimm precr_sra.ph.w, 0xfff0fff0, 0x3ffffff0, 0x3ffffff0, 0 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xffff0000, 0xc0000001, 31 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x0ffffffc, 0x80000000, 31 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x80000000, 0x80000000, 15 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x3ffffffe, 0x00003717, 31 - dspck_tsimm precr_sra.ph.w, 0x00070a24, 0xc0000007, 0x00000a24, 0 - dspck_tsimm precr_sra.ph.w, 0xfffe8529, 0x3ffffffe, 0x019f8529, 0 - dspck_tsimm precr_sra.ph.w, 0xfffbff80, 0xfffffffb, 0x7fffff80, 0 - dspck_tsimm precr_sra.ph.w, 0x38e30000, 0x38e38e38, 0xfc000001, 10 - dspck_tsimm precr_sra.ph.w, 0xfffd3127, 0xfffffffa, 0xd986624f, 1 - dspck_tsimm precr_sra.ph.w, 0xfff3ffff, 0xffffff33, 0x1ffffffe, 4 - dspck_tsimm precr_sra.ph.w, 0xbbf30003, 0x0003bbf3, 0xf8000003, 0 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffffe3, 0x00000000, 12 - dspck_tsimm precr_sra.ph.w, 0x9249ffff, 0x92492492, 0xfffffffd, 7 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0x80000000, 0xfffffffd, 31 - dspck_tsimm precr_sra.ph.w, 0x0000fff9, 0x001540d2, 0x99999999, 28 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0x80000000, 0x8000000f, 31 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xfc889cce, 0x80000000, 31 - dspck_tsimm precr_sra.ph.w, 0xffea0000, 0xffffff52, 0x80000000, 3 - dspck_tsimm precr_sra.ph.w, 0x0f0f0000, 0x0f0f0f0f, 0x80000000, 0 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x7fffffff, 0x00000000, 15 - dspck_tsimm precr_sra.ph.w, 0x38060000, 0xff13806f, 0x80000000, 4 - dspck_tsimm precr_sra.ph.w, 0xffff8d70, 0x0000ffff, 0x00008d70, 0 - dspck_tsimm precr_sra.ph.w, 0x0000fffc, 0x000000c9, 0xe000000f, 27 - dspck_tsimm precr_sra.ph.w, 0x0000f000, 0x00000002, 0x8000001f, 19 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x7fffffff, 31 - dspck_tsimm precr_sra.ph.w, 0x8e38003f, 0x38e38e38, 0x0000003f, 0 - dspck_tsimm precr_sra.ph.w, 0x00b80000, 0x000000b8, 0x00000000, 0 - dspck_tsimm precr_sra.ph.w, 0xffc00000, 0x80000004, 0x00000002, 25 - dspck_tsimm precr_sra.ph.w, 0xfffffd55, 0xfffd47dc, 0xaaaaaaaa, 21 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 4 - dspck_tsimm precr_sra.ph.w, 0x837d0000, 0xfffd06fb, 0x00000000, 1 - dspck_tsimm precr_sra.ph.w, 0x00002d30, 0x00000000, 0x00016985, 3 - dspck_tsimm precr_sra.ph.w, 0x000f0007, 0x0000000f, 0x00000007, 0 - dspck_tsimm precr_sra.ph.w, 0x00010000, 0x00000001, 0x00000000, 0 - dspck_tsimm precr_sra.ph.w, 0xff800000, 0x80000000, 0x0000007f, 24 - dspck_tsimm precr_sra.ph.w, 0x0f0f0000, 0xf0f0f0f0, 0x80000000, 4 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x0000ffff, 0xffe2a7e0, 31 - dspck_tsimm precr_sra.ph.w, 0x00003333, 0x00000000, 0x66666666, 17 - dspck_tsimm precr_sra.ph.w, 0xfbe9fbe9, 0xfffffbe9, 0xfffffbe9, 0 - dspck_tsimm precr_sra.ph.w, 0xffccffde, 0xffffffcc, 0xffffffde, 0 - dspck_tsimm precr_sra.ph.w, 0x0000001f, 0x00000000, 0x8000001f, 0 - dspck_tsimm precr_sra.ph.w, 0x000046ab, 0x80000001, 0x00023559, 3 - dspck_tsimm precr_sra.ph.w, 0xffff0007, 0x7fffffff, 0xe000000f, 1 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x7fffffff, 0xffffffc3, 31 - dspck_tsimm precr_sra.ph.w, 0xffff00ef, 0x7fffffff, 0x000003be, 2 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0x7ffffffe, 0x7fffffff, 1 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000007, 0x00000000, 13 - dspck_tsimm precr_sra.ph.w, 0x0001ffff, 0xf0000001, 0x7fffffff, 0 - dspck_tsimm precr_sra.ph.w, 0x00460046, 0x00000235, 0x00000235, 3 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffffe1, 0x80000003, 9 - dspck_tsimm precr_sra.ph.w, 0xfffffff0, 0xfffffffe, 0xffffffe0, 1 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x7ffffff8, 0x49249249, 31 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x7fffffff, 31 - dspck_tsimm precr_sra.ph.w, 0xfffffff0, 0xffffffe0, 0x80000000, 27 - dspck_tsimm precr_sra.ph.w, 0xff80fff2, 0x7fffff80, 0xfffffff2, 0 - dspck_tsimm precr_sra.ph.w, 0x001fff16, 0x0000001f, 0xffffff16, 0 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0xffffffe0, 17 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0x7fffffff, 3 - dspck_tsimm precr_sra.ph.w, 0xfff8ffff, 0x0ffffff8, 0x7fffffff, 0 - dspck_tsimm precr_sra.ph.w, 0x0000de5a, 0x00000000, 0xff79698f, 10 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xffffffd1, 0xfffffff0, 8 - dspck_tsimm precr_sra.ph.w, 0x00013908, 0x00000001, 0xfee43908, 0 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xfffffff8, 0xfded729c, 31 - dspck_tsimm precr_sra.ph.w, 0x0000fe72, 0x00000000, 0xce5a1cb7, 21 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 0 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffff00, 0x7fffffff, 31 - dspck_tsimm precr_sra.ph.w, 0x72defff8, 0x003a72de, 0x3ffffff8, 0 - dspck_tsimm precr_sra.ph.w, 0x0000dccd, 0x00000000, 0x1bdccd6d, 8 - dspck_tsimm precr_sra.ph.w, 0x98880000, 0x01e13110, 0x80000000, 1 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0x7fffffff, 0x80000000, 0 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000007, 0x80000000, 31 - dspck_tsimm precr_sra.ph.w, 0xfffaffff, 0x7ffffffa, 0x7fffffff, 0 - dspck_tsimm precr_sra.ph.w, 0xffff0001, 0xffffffff, 0x00000006, 2 - dspck_tsimm precr_sra.ph.w, 0x0000099e, 0x00000005, 0xeeb099ef, 4 - dspck_tsimm precr_sra.ph.w, 0xffff0000, 0xffffffff, 0x80000000, 0 - dspck_tsimm precr_sra.ph.w, 0xfffee60a, 0xfffffc46, 0xffcc1534, 9 - dspck_tsimm precr_sra.ph.w, 0xfffeffff, 0x80000000, 0xc000000f, 30 - dspck_tsimm precr_sra.ph.w, 0xff000000, 0xffffff00, 0x00000000, 0 - dspck_tsimm precr_sra.ph.w, 0x00070000, 0x00000007, 0x80000000, 0 - dspck_tsimm precr_sra.ph.w, 0xffef0000, 0xfffffefa, 0x80000000, 4 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x0000081f, 0x00000007, 31 - dspck_tsimm precr_sra.ph.w, 0x486effff, 0x000d21b8, 0x7fffffff, 2 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x7fffffff, 0x99999999, 31 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x00000000, 0x7fffffff, 7 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x80000000, 14 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 0 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x0ffffffe, 0x00000000, 31 - dspck_tsimm precr_sra.ph.w, 0x000000ff, 0x80000000, 0x000000ff, 0 - dspck_tsimm precr_sra.ph.w, 0xff800039, 0x80000000, 0x3939e9c0, 24 - dspck_tsimm precr_sra.ph.w, 0x00000001, 0x1ffffffe, 0x7fffffff, 30 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xffffffff, 0xfffffd61, 31 - dspck_tsimm precr_sra.ph.w, 0x00010001, 0x00000688, 0x00000688, 10 - dspck_tsimm precr_sra.ph.w, 0xb6db1c71, 0xdb6db6db, 0x8e38e38e, 3 - dspck_tsimm precr_sra.ph.w, 0x00679999, 0x000000cf, 0x33333333, 1 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x00000000, 0x00000000, 2 - dspck_tsimm precr_sra.ph.w, 0x0034ffff, 0x000068d6, 0xffffff5d, 9 - dspck_tsimm precr_sra.ph.w, 0x0000fc00, 0x00000000, 0x80000000, 21 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x80000000, 0x00000000, 8 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x7fffffff, 0x7fffffff, 31 - dspck_tsimm precr_sra.ph.w, 0x000001a6, 0x80000000, 0x0034dff6, 13 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xffff389e, 0xffffffff, 31 - dspck_tsimm precr_sra.ph.w, 0x00007b11, 0x00000000, 0xe734f622, 1 - dspck_tsimm precr_sra.ph.w, 0x0000ffff, 0x007c388e, 0xffff2106, 25 - dspck_tsimm precr_sra.ph.w, 0x00000000, 0x80000000, 0x00000000, 0 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0x7fffffff, 0x7fffffc0, 12 - dspck_tsimm precr_sra.ph.w, 0xffff0057, 0x7fffffff, 0x00000057, 0 - dspck_tsimm precr_sra.ph.w, 0x09240000, 0x24924924, 0x00000000, 18 - dspck_tsimm precr_sra.ph.w, 0xffffffff, 0xfffffffe, 0x3ffffff8, 6 - - writemsg "[27] Test precr_sra_r.ph.w" - dspck_tsimm precr_sra_r.ph.w, 0xffe0ffe0, 0x3fffffe0, 0x3fffffe0, 0 - dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0xc0000007, 0x80000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0xfff80001, 0x7fffffc0, 0x00000004, 3 - dspck_tsimm precr_sra_r.ph.w, 0x71c70000, 0xc71c71c7, 0x00000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000001, 0x000000ff, 0x7ffffffe, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00008e89, 0x00000002, 0x0118e88a, 4 - dspck_tsimm precr_sra_r.ph.w, 0xffffffff, 0x80000007, 0x80000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0x0000aaab, 0xfffffffb, 0x55555555, 13 - dspck_tsimm precr_sra_r.ph.w, 0x00020000, 0x0000007f, 0xffffffec, 6 - dspck_tsimm precr_sra_r.ph.w, 0x0000fffe, 0x00000000, 0x7ffffffc, 1 - dspck_tsimm precr_sra_r.ph.w, 0x0000fb86, 0x00000000, 0xfffffb86, 0 - dspck_tsimm precr_sra_r.ph.w, 0x7a02ff61, 0xfffe7a02, 0xffffff61, 0 - dspck_tsimm precr_sra_r.ph.w, 0xff48ff48, 0xffffff48, 0xffffff48, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffcea3, 0x00000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0x9cc70000, 0xffa731b1, 0x1ffffffc, 6 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0xc0000007, 7 - dspck_tsimm precr_sra_r.ph.w, 0xf0000000, 0x80000000, 0x000000ff, 19 - dspck_tsimm precr_sra_r.ph.w, 0xfff00010, 0x80000000, 0x7fffffc0, 27 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0x00000007, 31 - dspck_tsimm precr_sra_r.ph.w, 0x8e390000, 0x38e38e38, 0x7fffffff, 6 - dspck_tsimm precr_sra_r.ph.w, 0xfffffff9, 0x7fffffff, 0xfffffff9, 0 - dspck_tsimm precr_sra_r.ph.w, 0xfffe0000, 0x80000000, 0x0000007f, 30 - dspck_tsimm precr_sra_r.ph.w, 0x714dbe05, 0xffbee29a, 0x067b7c09, 1 - dspck_tsimm precr_sra_r.ph.w, 0xffffffff, 0x7fffffff, 0x7fffffff, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00109996, 0x0000001f, 0xfff1332b, 1 - dspck_tsimm precr_sra_r.ph.w, 0xcccc11ce, 0xcccccccc, 0x000011ce, 0 - dspck_tsimm precr_sra_r.ph.w, 0x645343ef, 0x0000c8a6, 0x27ca87de, 1 - dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0x7fffffff, 0xffffffe5, 5 - dspck_tsimm precr_sra_r.ph.w, 0xe02b0000, 0x00270156, 0x80000000, 3 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7ffffffc, 0x00000000, 8 - dspck_tsimm precr_sra_r.ph.w, 0x80008000, 0x3ffffffc, 0x3ffffff8, 15 - dspck_tsimm precr_sra_r.ph.w, 0xfffe7d97, 0x07fffffe, 0x0fa27d97, 0 - dspck_tsimm precr_sra_r.ph.w, 0xfff00002, 0x7fffffe0, 0xc0000003, 1 - dspck_tsimm precr_sra_r.ph.w, 0x00000001, 0x00000004, 0x71c71c71, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x7ffffff9, 0x00000288, 31 - dspck_tsimm precr_sra_r.ph.w, 0x87881ce0, 0x0f0f0f0f, 0x024839bf, 1 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x80000000, 6 - dspck_tsimm precr_sra_r.ph.w, 0xfffe0001, 0x3ffffffe, 0x80000001, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0xff8e97bb, 31 - dspck_tsimm precr_sra_r.ph.w, 0xffff0001, 0x80000000, 0x7fffffff, 31 - dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000000, 0xfffffeae, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x7fffff80, 13 - dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000000, 0xc720a895, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xfffffffa, 0x7fffffff, 7 - dspck_tsimm precr_sra_r.ph.w, 0x03dcf706, 0x0000f6f9, 0xfffdc18d, 6 - dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x7fffffff, 0x80000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xfffe262b, 0xfffffa76, 24 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x80000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0xffc10000, 0xffffc0e6, 0x0ffffffc, 8 - dspck_tsimm precr_sra_r.ph.w, 0x00040004, 0x00000004, 0x00000004, 0 - dspck_tsimm precr_sra_r.ph.w, 0xfff20000, 0x92492492, 0x000000c9, 27 - dspck_tsimm precr_sra_r.ph.w, 0x0000999a, 0xffffffb7, 0x99999999, 12 - dspck_tsimm precr_sra_r.ph.w, 0x00010002, 0xf0000007, 0xe000000f, 3 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x000016ca, 0x00000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0x096f0000, 0x00004b75, 0x00000001, 3 - dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x7fffffff, 0xc71c71c7, 31 - dspck_tsimm precr_sra_r.ph.w, 0xa80cfe4e, 0xffd4a80c, 0xfffffe4e, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffffff, 0x7fffffff, 8 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000b61, 0xe38e38e3, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x00000003, 3 - dspck_tsimm precr_sra_r.ph.w, 0x00060000, 0x00000059, 0xf8000003, 4 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x8000001f, 0x07fffffc, 10 - dspck_tsimm precr_sra_r.ph.w, 0xb4ef0000, 0x03769de4, 0x00000000, 5 - dspck_tsimm precr_sra_r.ph.w, 0x000001a1, 0x80000000, 0x000001a1, 0 - dspck_tsimm precr_sra_r.ph.w, 0x0000fffd, 0x00000001, 0xffffffe5, 3 - dspck_tsimm precr_sra_r.ph.w, 0xfc000000, 0x80000000, 0x00000000, 21 - dspck_tsimm precr_sra_r.ph.w, 0x00000008, 0x7fffffff, 0x0000001f, 2 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7ffffffa, 0x7ffffffc, 6 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x0f0f0f0f, 0x00000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x00000001, 0x00000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x7fffffff, 0xfffeb397, 31 - dspck_tsimm precr_sra_r.ph.w, 0x66660000, 0x66666666, 0x00000000, 16 - dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x92492492, 0x00000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0xe0000000, 0xffff0000, 0x07fffffe, 3 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xc000000f, 0xdb6db6db, 31 - dspck_tsimm precr_sra_r.ph.w, 0xffe00000, 0xffffffe0, 0x00000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0xfff89999, 0x0ffffff8, 0x99999999, 0 - dspck_tsimm precr_sra_r.ph.w, 0x0000fffd, 0x00000002, 0xffffa3b3, 13 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x3fffffe0, 0x3fffffe0, 31 - dspck_tsimm precr_sra_r.ph.w, 0xf5ec0003, 0xfffff5ec, 0xf0000003, 0 - dspck_tsimm precr_sra_r.ph.w, 0x676d0000, 0x0002676d, 0x00000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00010001, 0x7fffffff, 0x7fffffff, 31 - dspck_tsimm precr_sra_r.ph.w, 0x0000fffb, 0x7fffffff, 0xffffffec, 2 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xf8649518, 0x00000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000004, 0x00000000, 8 - dspck_tsimm precr_sra_r.ph.w, 0xe1e2db6e, 0xf0f0f0f0, 0xdb6db6db, 7 - dspck_tsimm precr_sra_r.ph.w, 0x0003fff8, 0x00000003, 0xfffffff8, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000003, 0x80000000, 0x80000006, 1 - dspck_tsimm precr_sra_r.ph.w, 0x0001fffe, 0x80000002, 0xfffffffb, 1 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x1ffffff8, 0xe000000f, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0xffffffff, 1 - dspck_tsimm precr_sra_r.ph.w, 0xfff80000, 0x3ffffff0, 0x7fffffff, 1 - dspck_tsimm precr_sra_r.ph.w, 0x000038e4, 0x00000000, 0xc71c71c7, 1 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x00000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00002492, 0x00000000, 0x49249249, 5 - dspck_tsimm precr_sra_r.ph.w, 0x002d0000, 0x00005ae8, 0xfffffff0, 9 - dspck_tsimm precr_sra_r.ph.w, 0xffae0000, 0xfffffd6e, 0x00000000, 3 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x7fffffff, 5 - dspck_tsimm precr_sra_r.ph.w, 0x80000000, 0xf0000001, 0x00000273, 13 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0x00000000, 1 - dspck_tsimm precr_sra_r.ph.w, 0x55550a42, 0x55555555, 0x07c29079, 6 - dspck_tsimm precr_sra_r.ph.w, 0xfb93fffc, 0xfffffb93, 0xfffffffc, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xff00ff00, 0xe76358a9, 30 - dspck_tsimm precr_sra_r.ph.w, 0xfffeffff, 0x80000000, 0xc000000f, 30 - dspck_tsimm precr_sra_r.ph.w, 0x00000002, 0xffffffff, 0x8000000f, 3 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7ffffff9, 0x7ffffffa, 8 - dspck_tsimm precr_sra_r.ph.w, 0xe3d1fff8, 0xffdfe3d1, 0x7ffffff8, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffe407, 0xfffffffe, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000320, 0xfffffff8, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000d37, 0xfffffff9, 0x0034dcb6, 10 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x00000000, 8 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000035, 0x00000000, 8 - dspck_tsimm precr_sra_r.ph.w, 0x0000fff8, 0x00000000, 0x3ffffff0, 1 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x3ffffffc, 0x00000000, 10 - dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0xffffebc6, 0x80000000, 12 - dspck_tsimm precr_sra_r.ph.w, 0x000038e3, 0x00000000, 0xe38e38e3, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00010001, 0x7ffffff0, 0x7fffffff, 31 - dspck_tsimm precr_sra_r.ph.w, 0xeb0f8e39, 0x00075875, 0xc71c71c7, 3 - dspck_tsimm precr_sra_r.ph.w, 0x00005ae3, 0x00000000, 0x00005ae3, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x0000774b, 0x0000774b, 19 - dspck_tsimm precr_sra_r.ph.w, 0x0223fffc, 0x00000446, 0x1ffffff8, 1 - dspck_tsimm precr_sra_r.ph.w, 0x00030000, 0x80000003, 0x00000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0x00000000, 6 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffc3b4, 0x00000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xff00ff00, 0x00018f10, 27 - dspck_tsimm precr_sra_r.ph.w, 0x150b1f10, 0x0010a85b, 0x0000f87d, 3 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x0000006d, 0x00033da5, 31 - dspck_tsimm precr_sra_r.ph.w, 0x002cfe00, 0x0ae3bff1, 0x80000000, 22 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffffff, 0x00000000, 24 - dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0xe0000001, 0x00000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0x80000007, 0xffffe93d, 13 - dspck_tsimm precr_sra_r.ph.w, 0x0000fffe, 0xffffffff, 0xffffffe0, 4 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x7fffffff, 2 - dspck_tsimm precr_sra_r.ph.w, 0xf7ebf7eb, 0x0003f7eb, 0x0003f7eb, 0 - dspck_tsimm precr_sra_r.ph.w, 0xe45c003f, 0xffcce45c, 0x0000003f, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000001, 0xfd467217, 0x7fffffff, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00074f22, 0xf0000007, 0xed2e4f22, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x0000005c, 0x7fffffff, 6 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0xf3f39787, 31 - dspck_tsimm precr_sra_r.ph.w, 0xffffffff, 0xfffffffa, 0xfffffffa, 3 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffffc0, 0x80000000, 9 - dspck_tsimm precr_sra_r.ph.w, 0x8a5d0000, 0x007c8a5d, 0x00000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000003, 0xfffea149, 31 - dspck_tsimm precr_sra_r.ph.w, 0xfffffff0, 0x7fffffff, 0xfffffff0, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x00000000, 3 - dspck_tsimm precr_sra_r.ph.w, 0xffffffff, 0x80000000, 0x80000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0xffeb0fdb, 0xffffffeb, 0x01d00fdb, 0 - dspck_tsimm precr_sra_r.ph.w, 0x0000fe1d, 0x00000000, 0xfffff874, 2 - dspck_tsimm precr_sra_r.ph.w, 0xfffed715, 0x1ffffffc, 0xe4c3ae2a, 1 - dspck_tsimm precr_sra_r.ph.w, 0xcc260000, 0x03e61329, 0xc000001f, 7 - dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000000, 0x0001cdbc, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00030000, 0xe0000003, 0x00000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0x0005b8cd, 0x80000005, 0x0014b8cd, 0 - dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0x00000000, 0xf8000003, 27 - dspck_tsimm precr_sra_r.ph.w, 0xfff003d2, 0xfffffff0, 0x000003d2, 0 - dspck_tsimm precr_sra_r.ph.w, 0xffe00000, 0x7fffffc0, 0x00000000, 1 - dspck_tsimm precr_sra_r.ph.w, 0xfffcfffc, 0x7ffffff0, 0x1ffffff0, 2 - dspck_tsimm precr_sra_r.ph.w, 0x00000040, 0xffffffa3, 0x7fffffff, 25 - dspck_tsimm precr_sra_r.ph.w, 0xfab9005a, 0xfffffab9, 0x0000005a, 0 - dspck_tsimm precr_sra_r.ph.w, 0xe0000000, 0x80000001, 0x00000000, 18 - dspck_tsimm precr_sra_r.ph.w, 0x978676f6, 0xffa65e16, 0x0001dbd7, 2 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x02c51b17, 0x02c51b17, 31 - dspck_tsimm precr_sra_r.ph.w, 0x948e0000, 0xff14a470, 0x80000000, 3 - dspck_tsimm precr_sra_r.ph.w, 0xc0000000, 0xe0000007, 0x8000003f, 15 - dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000000, 0x00000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000004, 0x80000000, 0x80000004, 0 - dspck_tsimm precr_sra_r.ph.w, 0x0000fffc, 0x00000000, 0x7ffffffc, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7ffffffb, 0x8000003f, 12 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x0002cce6, 0x07fffffc, 31 - dspck_tsimm precr_sra_r.ph.w, 0xf299aa30, 0xfffff299, 0xfffeaa30, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000002, 0xe0000007, 0x00000060, 6 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x00000000, 3 - dspck_tsimm precr_sra_r.ph.w, 0xfe000000, 0x80000000, 0x0002471b, 22 - dspck_tsimm precr_sra_r.ph.w, 0x24920000, 0x92492492, 0xffffffff, 3 - dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000000, 0x00000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0x2ba5fffc, 0xfff82ba5, 0x07fffffc, 0 - dspck_tsimm precr_sra_r.ph.w, 0xff00356e, 0xffffff00, 0x0121356e, 0 - dspck_tsimm precr_sra_r.ph.w, 0x66663c60, 0x66666666, 0xd0c23c60, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00002492, 0x00000001, 0x92492492, 15 - dspck_tsimm precr_sra_r.ph.w, 0xffbfffff, 0xffffffbf, 0x7fffffff, 0 - dspck_tsimm precr_sra_r.ph.w, 0xc7450008, 0xffde3a28, 0x8000003f, 3 - dspck_tsimm precr_sra_r.ph.w, 0x0000b6db, 0x7fffffff, 0xdb6db6db, 3 - dspck_tsimm precr_sra_r.ph.w, 0xc0000000, 0x80000000, 0x00000000, 17 - dspck_tsimm precr_sra_r.ph.w, 0x00ad0000, 0x000acd12, 0x00000005, 12 - dspck_tsimm precr_sra_r.ph.w, 0xbdee0000, 0xff9d7bdc, 0x00000000, 1 - dspck_tsimm precr_sra_r.ph.w, 0x001b3333, 0x0000006b, 0xcccccccc, 2 - dspck_tsimm precr_sra_r.ph.w, 0x81480000, 0x0140a402, 0xe000000f, 7 - dspck_tsimm precr_sra_r.ph.w, 0x0503ffe0, 0x00a05c2c, 0xfffc0bb1, 13 - dspck_tsimm precr_sra_r.ph.w, 0x830c0001, 0x007c185d, 0xe0000007, 3 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0xfbae5c82, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x7fffffff, 2 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00003423, 0x00007446, 30 - dspck_tsimm precr_sra_r.ph.w, 0x0000001f, 0x00000000, 0x8000001f, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000002, 0x00000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0xffb7664a, 0x0928ffb7, 0xff89664a, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x0ffffffe, 8 - dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x7fffffff, 0x1ffffffc, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00040000, 0x7fffffff, 0xffffffe0, 29 - dspck_tsimm precr_sra_r.ph.w, 0x0000fff7, 0x00000815, 0xf7723f4f, 24 - dspck_tsimm precr_sra_r.ph.w, 0x00fffffe, 0x00ff00ff, 0x7ffffffe, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x80000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000001, 0x00000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x1ffffffe, 6 - dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0xff2e1e63, 0x80000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0x0000fffd, 0x7fffffff, 0xfffffffa, 1 - dspck_tsimm precr_sra_r.ph.w, 0x6db70000, 0xdb6db6db, 0x80000000, 11 - dspck_tsimm precr_sra_r.ph.w, 0x141f0001, 0xff00507d, 0x00000002, 2 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x00000000, 1 - dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0x80000000, 0x7fffffff, 0 - dspck_tsimm precr_sra_r.ph.w, 0x2e9d0000, 0xfff2e9cd, 0x00000000, 4 - dspck_tsimm precr_sra_r.ph.w, 0xffd8fc00, 0xfb087aa5, 0x80000000, 21 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x33333333, 0xffffe715, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x7fffffff, 0x7fffffff, 3 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0xe000000f, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00033c3c, 0x0000000d, 0xf0f0f0f0, 2 - dspck_tsimm precr_sra_r.ph.w, 0xfff8ffff, 0x3ffffff8, 0x7fffffff, 0 - dspck_tsimm precr_sra_r.ph.w, 0xff800000, 0x8000001f, 0xffffff00, 24 - dspck_tsimm precr_sra_r.ph.w, 0x0000ffff, 0x00000000, 0x80000000, 31 - dspck_tsimm precr_sra_r.ph.w, 0x0000ffb7, 0x00000000, 0xffdbb2cf, 15 - dspck_tsimm precr_sra_r.ph.w, 0x2c03d9c7, 0x0002c033, 0xf39d9c77, 4 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffffff, 0xffffff2b, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffffff, 0x07fffffe, 11 - dspck_tsimm precr_sra_r.ph.w, 0x40000000, 0x7fffffe0, 0xffff0000, 17 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x00000003, 13 - dspck_tsimm precr_sra_r.ph.w, 0x00010001, 0x7fffffff, 0x7fffffff, 31 - dspck_tsimm precr_sra_r.ph.w, 0x0000b9b9, 0x00000002, 0xff1dcdc4, 3 - dspck_tsimm precr_sra_r.ph.w, 0x000f0000, 0x0000000f, 0x00000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00010000, 0x0000003f, 0x00000000, 6 - dspck_tsimm precr_sra_r.ph.w, 0xfff801e6, 0x7ffffff8, 0x000001e6, 0 - dspck_tsimm precr_sra_r.ph.w, 0xffff0000, 0x80000000, 0xffffffe4, 31 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x80000000, 0x00000000, 1 - dspck_tsimm precr_sra_r.ph.w, 0x00000013, 0x3ffffff0, 0x000004cf, 6 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0xffffffea, 0xc0000003, 7 - dspck_tsimm precr_sra_r.ph.w, 0x000034c6, 0x80000000, 0xffff34c6, 0 - dspck_tsimm precr_sra_r.ph.w, 0xfffefe02, 0xfffffec1, 0x00ff00ff, 7 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x00000000, 0x80000000, 0 - dspck_tsimm precr_sra_r.ph.w, 0xe000e000, 0x80000000, 0x80000000, 18 - dspck_tsimm precr_sra_r.ph.w, 0x9b7fffff, 0x005c9b7f, 0x7fffffff, 0 - dspck_tsimm precr_sra_r.ph.w, 0x00000000, 0x8000003f, 0x80000003, 14 - dspck_tsimm precr_sra_r.ph.w, 0x0000bd45, 0x80000000, 0x1c7b7a8a, 1 - dspck_tsimm precr_sra_r.ph.w, 0xffd70000, 0xffffffad, 0x00000000, 1 - - writemsg "[28] Test prepend" - dspck_tsimm prepend, 0x5ffff0df, 0xffff86fc, 0xfffffe02, 3 - dspck_tsimm prepend, 0x00000000, 0x00000000, 0xfffffe06, 0 - dspck_tsimm prepend, 0x0fffffff, 0x7fffffff, 0x80000000, 3 - dspck_tsimm prepend, 0x80000000, 0x80000000, 0x00000000, 0 - dspck_tsimm prepend, 0x00000000, 0x00000000, 0xffffff23, 0 - dspck_tsimm prepend, 0x01feed28, 0xff76947a, 0x00000000, 7 - dspck_tsimm prepend, 0x00000035, 0x00000035, 0xffffffc0, 0 - dspck_tsimm prepend, 0x80000000, 0x80000000, 0x01130b02, 0 - dspck_tsimm prepend, 0x7ffffffe, 0x7ffffffe, 0xc0000001, 0 - dspck_tsimm prepend, 0x7fffffff, 0x7fffffff, 0x7fffffff, 0 - dspck_tsimm prepend, 0x1a75980e, 0x1a75980e, 0x1b4c3c1e, 0 - dspck_tsimm prepend, 0x7fffffff, 0xffffffff, 0x7ffffffc, 1 - dspck_tsimm prepend, 0x00060000, 0xc0000003, 0x00000000, 13 - dspck_tsimm prepend, 0x7fffffff, 0xfffffffe, 0x00000000, 1 - dspck_tsimm prepend, 0xfffffffe, 0x1ffffffe, 0x7fffffff, 31 - dspck_tsimm prepend, 0x00000000, 0x00000000, 0x00000000, 0 - dspck_tsimm prepend, 0xfffffb50, 0x7fffffff, 0xfffffda8, 31 - dspck_tsimm prepend, 0x6b2c0000, 0xc0000007, 0xfffff6b2, 12 - dspck_tsimm prepend, 0x0015491f, 0x002a923e, 0x1ffffff8, 1 - dspck_tsimm prepend, 0x00000021, 0xfffffee4, 0x00000010, 31 - dspck_tsimm prepend, 0xf6ecdac9, 0xf8034c6b, 0xfb766d64, 31 - dspck_tsimm prepend, 0xb7ffffff, 0x7ffffffb, 0x0000002b, 4 - dspck_tsimm prepend, 0xfffffffa, 0xfffffffa, 0x7fffffff, 0 - dspck_tsimm prepend, 0xffaaaaaa, 0x55555555, 0x7fffffff, 9 - dspck_tsimm prepend, 0x00016000, 0x80000000, 0x80000005, 18 - dspck_tsimm prepend, 0x7fffffff, 0x7fffffff, 0x000004fc, 0 - dspck_tsimm prepend, 0x00000000, 0x0035d189, 0x80000000, 31 - dspck_tsimm prepend, 0x8000007f, 0x8000007f, 0xff00ff00, 0 - dspck_tsimm prepend, 0xaf600000, 0x00000000, 0x03557af6, 12 - dspck_tsimm prepend, 0x000000e3, 0x000000e3, 0x0008f4ab, 0 - dspck_tsimm prepend, 0x00000000, 0x00000000, 0x00000000, 2 - dspck_tsimm prepend, 0x61e1e1e1, 0x0f0f0f0f, 0x00000003, 3 - dspck_tsimm prepend, 0x002559bf, 0x002559bf, 0xdb6db6db, 0 - dspck_tsimm prepend, 0x19999999, 0x66666666, 0x7fffff80, 2 - dspck_tsimm prepend, 0xe85fb7d6, 0x80000000, 0xfa17edf5, 30 - dspck_tsimm prepend, 0x6b800000, 0xc0000001, 0x00003cb5, 7 - dspck_tsimm prepend, 0xc71c71c7, 0xc71c71c7, 0x00000335, 0 - dspck_tsimm prepend, 0x8000001f, 0x8000001f, 0xfffffef3, 0 - dspck_tsimm prepend, 0x00200000, 0x00000006, 0x80000002, 12 - dspck_tsimm prepend, 0x50c7ffff, 0xffffffd5, 0xf8c02863, 15 - dspck_tsimm prepend, 0x0008fd99, 0x33299df8, 0x000011fb, 25 - dspck_tsimm prepend, 0x00f00000, 0x00000000, 0xc000000f, 12 - dspck_tsimm prepend, 0x00000000, 0x00000001, 0x00000000, 31 - dspck_tsimm prepend, 0xebffffff, 0x7ffffffb, 0x7ffffffd, 5 - dspck_tsimm prepend, 0xffffffc0, 0x80000000, 0x7fffffff, 25 - dspck_tsimm prepend, 0xc0ffffff, 0x0ffffffc, 0x0ffffffc, 4 - dspck_tsimm prepend, 0x8000003f, 0xfffffe6a, 0xc000001f, 31 - dspck_tsimm prepend, 0x7face03a, 0xfeb380e9, 0x7ffffffd, 2 - dspck_tsimm prepend, 0x3ffffffd, 0x7ffffffa, 0x00000000, 1 - dspck_tsimm prepend, 0xe0000003, 0x8000000f, 0xdb6db6db, 2 - dspck_tsimm prepend, 0x001548ff, 0xfffd232e, 0x00001548, 24 - dspck_tsimm prepend, 0x6000000f, 0xc000001f, 0x00000000, 1 - dspck_tsimm prepend, 0x000000cc, 0x33333333, 0x00000000, 22 - dspck_tsimm prepend, 0x00000004, 0x0000db1b, 0xc0000001, 30 - dspck_tsimm prepend, 0x01ffffff, 0xffffffff, 0xe0000007, 10 - dspck_tsimm prepend, 0x80000000, 0x00000000, 0xffffff5f, 1 - dspck_tsimm prepend, 0x0000007e, 0x0d2efcd1, 0x8000003f, 31 - dspck_tsimm prepend, 0xda000000, 0x00000000, 0xffffff6d, 7 - dspck_tsimm prepend, 0x00040d38, 0x00081a70, 0xe4606c5a, 1 - dspck_tsimm prepend, 0xc0000007, 0x80000000, 0xe0000003, 31 - dspck_tsimm prepend, 0x00000000, 0x00000000, 0xfff9ab12, 0 - dspck_tsimm prepend, 0xffffffff, 0x80000000, 0x7fffffff, 31 - dspck_tsimm prepend, 0x00007fff, 0xffffd894, 0x00000000, 17 - dspck_tsimm prepend, 0xffed5610, 0x0ffffffe, 0xfff6ab08, 31 - dspck_tsimm prepend, 0x00000002, 0x80000000, 0x00000000, 30 - dspck_tsimm prepend, 0x0019ffff, 0x7fffffff, 0x00000006, 14 - dspck_tsimm prepend, 0xe0000000, 0x80000000, 0x7fffffff, 2 - dspck_tsimm prepend, 0x003ffffc, 0xfffff23b, 0x00000000, 10 - dspck_tsimm prepend, 0x00000001, 0x80000000, 0x80000000, 31 - dspck_tsimm prepend, 0x00000011, 0x00000011, 0x7fffffff, 0 - dspck_tsimm prepend, 0x7ffffffd, 0xfffffffa, 0x1c71c71c, 1 - dspck_tsimm prepend, 0xe6666666, 0xcccccccc, 0xf8000001, 1 - dspck_tsimm prepend, 0x00000001, 0x80000000, 0x80000000, 31 - dspck_tsimm prepend, 0xfdb739b8, 0xfdb739b8, 0x000000e1, 0 - dspck_tsimm prepend, 0x00000fff, 0x7fffffff, 0x80000000, 19 - dspck_tsimm prepend, 0x7ffff90b, 0xfffff216, 0x80000000, 1 - dspck_tsimm prepend, 0x00000000, 0x3ffffff8, 0x00000000, 31 - dspck_tsimm prepend, 0xfea7a4f9, 0xfea7a4f9, 0xfffffffe, 0 - dspck_tsimm prepend, 0xfffffffe, 0x7fffffff, 0x7fffffff, 31 - dspck_tsimm prepend, 0x0000033f, 0x7fffffff, 0x00000006, 25 - dspck_tsimm prepend, 0x8e7fffff, 0x7fffffff, 0x8e38e38e, 8 - dspck_tsimm prepend, 0xfffffffc, 0x00000000, 0xfffffffe, 31 - dspck_tsimm prepend, 0x7fffffff, 0x7fffffff, 0x00000000, 0 - dspck_tsimm prepend, 0xffffff4e, 0x80000000, 0xffffffd3, 30 - dspck_tsimm prepend, 0xf0000001, 0xf0000001, 0x00000006, 0 - dspck_tsimm prepend, 0x000017ff, 0xfffffff8, 0x00000002, 21 - dspck_tsimm prepend, 0x49666666, 0x66666666, 0x49249249, 8 - dspck_tsimm prepend, 0x000001fe, 0x7fffffff, 0x000000ff, 31 - dspck_tsimm prepend, 0x1ffffff8, 0x1ffffff8, 0x80000001, 0 - dspck_tsimm prepend, 0xffffff97, 0xe0000003, 0xffffffcb, 31 - dspck_tsimm prepend, 0xfffec8d0, 0xfffb2342, 0x0000001f, 2 - dspck_tsimm prepend, 0x40000000, 0x80000000, 0xfffffffe, 1 - dspck_tsimm prepend, 0x03fffffe, 0x03fffffe, 0x00000c17, 0 - dspck_tsimm prepend, 0x80000000, 0x00000000, 0xc0000003, 1 - dspck_tsimm prepend, 0xcea81fff, 0x03fffffe, 0xfffd39d5, 13 - dspck_tsimm prepend, 0xc0000c64, 0x0003192a, 0x0000d270, 6 - dspck_tsimm prepend, 0x000001ff, 0x3ffffffe, 0x00000000, 21 - dspck_tsimm prepend, 0x20000000, 0x80000000, 0x80000000, 2 - dspck_tsimm prepend, 0xfec42a9c, 0x1ffffff0, 0xff62154e, 31 - dspck_tsimm prepend, 0xf973ffff, 0x7fffffff, 0xffffff2e, 13 - dspck_tsimm prepend, 0x7c000000, 0xf8000001, 0x80000000, 1 - dspck_tsimm prepend, 0x0000006f, 0x7fffffff, 0xe0000003, 27 - dspck_tsimm prepend, 0x6d17c000, 0xe000000f, 0x0000368b, 15 - dspck_tsimm prepend, 0x0000003f, 0x7fffffff, 0x80000000, 25 - dspck_tsimm prepend, 0x18000000, 0x0000029c, 0x00001460, 10 - dspck_tsimm prepend, 0x59a85fba, 0xfdd559c5, 0x000acd42, 19 - dspck_tsimm prepend, 0xe7ffffff, 0x3ffffff8, 0x0081575f, 3 - dspck_tsimm prepend, 0xffffed07, 0xffffed07, 0x00000000, 0 - dspck_tsimm prepend, 0x4fffffff, 0x7fffffff, 0x00000002, 3 - dspck_tsimm prepend, 0xf8ffffff, 0x3fffffe0, 0x07fffffe, 6 - dspck_tsimm prepend, 0x000a559a, 0x000a559a, 0x7fffffff, 0 - dspck_tsimm prepend, 0x0f261bcd, 0x1e4c379a, 0x00000ae6, 1 - dspck_tsimm prepend, 0x00000000, 0x00000001, 0xfffffff0, 1 - dspck_tsimm prepend, 0xe0000bcb, 0x0000bcb1, 0xfffffffe, 4 - dspck_tsimm prepend, 0x8010c97e, 0x002192fc, 0x7fffffff, 1 - dspck_tsimm prepend, 0x00000000, 0x00000000, 0xfffff7e4, 1 - dspck_tsimm prepend, 0x7ffffff0, 0x7ffffff0, 0x00000000, 0 - dspck_tsimm prepend, 0xdffffffe, 0x7ffffff8, 0x80000007, 2 - dspck_tsimm prepend, 0xfffffff5, 0xfffffffa, 0xfffffffa, 31 - dspck_tsimm prepend, 0x7ffffffa, 0x7ffffffa, 0x7fffffff, 0 - dspck_tsimm prepend, 0x00000000, 0x00000000, 0x7ffffff0, 0 - dspck_tsimm prepend, 0x000001ff, 0x8000001f, 0x000000ff, 31 - dspck_tsimm prepend, 0x00000000, 0x00000000, 0x00000000, 27 - dspck_tsimm prepend, 0x00083a04, 0x00107408, 0x07fffffc, 1 - dspck_tsimm prepend, 0xfffffffe, 0x7fffffff, 0x7fffffff, 31 - dspck_tsimm prepend, 0xffffc25d, 0xaaaaaaaa, 0xffffe12e, 31 - dspck_tsimm prepend, 0x0003e000, 0xf8000001, 0x00000000, 14 - dspck_tsimm prepend, 0x29fc2bb3, 0x29fc2bb3, 0x80000000, 0 - dspck_tsimm prepend, 0xffffa900, 0x000036c7, 0xfffffd48, 27 - dspck_tsimm prepend, 0xffffffba, 0xffffffba, 0x0f0f0f0f, 0 - dspck_tsimm prepend, 0x00000017, 0xffffc303, 0x80000005, 30 - dspck_tsimm prepend, 0x07fffe00, 0xffff0000, 0x00000003, 7 - dspck_tsimm prepend, 0xfffffff7, 0xf0000003, 0xfffffffe, 29 - dspck_tsimm prepend, 0xffe97f08, 0x00000005, 0xfff4bf84, 31 - dspck_tsimm prepend, 0xfffcc6a5, 0xfffcc6a5, 0x7fffffff, 0 - dspck_tsimm prepend, 0xe0000003, 0xe0000003, 0x66666666, 0 - dspck_tsimm prepend, 0xe0000000, 0x00000000, 0x00000827, 3 - dspck_tsimm prepend, 0xf8000000, 0x80000000, 0x7fffffff, 4 - dspck_tsimm prepend, 0xe0000003, 0xe0000003, 0x80000000, 0 - dspck_tsimm prepend, 0x24924940, 0x80000000, 0x92492492, 25 - dspck_tsimm prepend, 0x000001f9, 0x000001f9, 0x1ce10bb3, 0 - dspck_tsimm prepend, 0xfffe0000, 0x00000000, 0x3ffffffc, 17 - dspck_tsimm prepend, 0x0000728f, 0xfffffffe, 0x00001ca3, 30 - dspck_tsimm prepend, 0xfe1db4e0, 0x00000de7, 0xfff0eda7, 27 - dspck_tsimm prepend, 0x07fffffe, 0x0ffffffc, 0x00000000, 1 - dspck_tsimm prepend, 0x80f31ed7, 0x01e63dae, 0x8000007f, 1 - dspck_tsimm prepend, 0xf0000000, 0x80000000, 0x000072d7, 3 - dspck_tsimm prepend, 0xfffffff4, 0x000d0717, 0xfffffffa, 31 - dspck_tsimm prepend, 0x007fffff, 0xfffffff8, 0x80000000, 9 - dspck_tsimm prepend, 0x00000000, 0x00000000, 0x00000000, 0 - dspck_tsimm prepend, 0xe0000006, 0x00006000, 0xf0000003, 31 - dspck_tsimm prepend, 0xf8ffffff, 0x7fffffff, 0x07fffffc, 7 - dspck_tsimm prepend, 0x001fffff, 0x7fffffff, 0x00000000, 10 - dspck_tsimm prepend, 0xffffffec, 0xffffffd8, 0x00000003, 1 - dspck_tsimm prepend, 0xffdfffff, 0x7fffffff, 0x7fffffff, 10 - dspck_tsimm prepend, 0x0000003f, 0x0000003f, 0x0000003f, 0 - dspck_tsimm prepend, 0x00fe67cb, 0xfe67cb2a, 0x00000000, 8 - dspck_tsimm prepend, 0xffe00014, 0x0000a3af, 0x7fffffff, 11 - dspck_tsimm prepend, 0x80000000, 0x80000000, 0xe0000003, 0 - dspck_tsimm prepend, 0x03999999, 0x33333333, 0x00000007, 9 - dspck_tsimm prepend, 0xffffc400, 0x00000022, 0xfffffff1, 22 - dspck_tsimm prepend, 0xaffffe94, 0xffffe940, 0x00a6984a, 4 - dspck_tsimm prepend, 0x02000000, 0x80000000, 0x00000000, 6 - dspck_tsimm prepend, 0xffffe59b, 0xffffe59b, 0x80000000, 0 - dspck_tsimm prepend, 0x04000000, 0x80000000, 0x80000000, 5 - dspck_tsimm prepend, 0xffff0000, 0x00000000, 0x7fffffc0, 22 - dspck_tsimm prepend, 0x01fc0000, 0x00000334, 0x8000007f, 14 - dspck_tsimm prepend, 0x7ffffff0, 0x7ffffff0, 0xfffffffe, 0 - dspck_tsimm prepend, 0x0ff00ff0, 0xff00ff00, 0x00000000, 4 - dspck_tsimm prepend, 0x00001fff, 0x3ffffffe, 0x80000000, 17 - dspck_tsimm prepend, 0x00000001, 0x80000000, 0x80000000, 31 - dspck_tsimm prepend, 0x012b9440, 0x2b9440fc, 0x00000001, 8 - dspck_tsimm prepend, 0x72000000, 0x00000002, 0xffffd5c8, 10 - dspck_tsimm prepend, 0xfff138af, 0xfff138af, 0x80000000, 0 - dspck_tsimm prepend, 0x00000000, 0x00000000, 0x00000000, 16 - dspck_tsimm prepend, 0xe3000000, 0x00000002, 0xe38e38e3, 8 - dspck_tsimm prepend, 0xf4911d04, 0xf4911d04, 0x8000007f, 0 - dspck_tsimm prepend, 0x7ffffff0, 0x7ffffff0, 0x00000000, 0 - dspck_tsimm prepend, 0x09ffe215, 0xffe21573, 0xffffe109, 8 - dspck_tsimm prepend, 0x7fffffff, 0x7fffffff, 0xc890ef17, 0 - dspck_tsimm prepend, 0x52000000, 0x80000001, 0xfffdb214, 6 - dspck_tsimm prepend, 0x0000000f, 0xfee9b599, 0x00000000, 28 - dspck_tsimm prepend, 0x7ffff4ab, 0xffffe956, 0x0000016c, 1 - dspck_tsimm prepend, 0x007ff716, 0xffee2d5e, 0x00000000, 9 - dspck_tsimm prepend, 0xfffffffe, 0xfffffffe, 0x00000000, 0 - dspck_tsimm prepend, 0xd9ffffec, 0xfffff66c, 0xfffff66c, 7 - dspck_tsimm prepend, 0x00000000, 0x00000fb4, 0x80000000, 15 - dspck_tsimm prepend, 0xe0000000, 0x00000000, 0x7fffffff, 3 - dspck_tsimm prepend, 0x00000735, 0x00000735, 0xffffffff, 0 - dspck_tsimm prepend, 0x90000000, 0x80000000, 0x1ffffffc, 3 - dspck_tsimm prepend, 0x000000ff, 0xffffb926, 0x00000000, 24 - dspck_tsimm prepend, 0x00002b8d, 0x00002b8d, 0x8000007f, 0 - dspck_tsimm prepend, 0xc0000000, 0x00000000, 0x00000017, 2 - dspck_tsimm prepend, 0x80000000, 0x80000000, 0xff9a0952, 0 - dspck_tsimm prepend, 0x0f76e7cf, 0x0f76e7cf, 0x0f76e7cf, 0 - dspck_tsimm prepend, 0x38e38e38, 0x7fffffff, 0x1c71c71c, 31 - dspck_tsimm prepend, 0xea000000, 0x80000001, 0xfffffffa, 6 - dspck_tsimm prepend, 0x03fffffd, 0xfffff747, 0x0000000f, 10 - dspck_tsimm prepend, 0x01f80000, 0xe0000007, 0xe0000007, 10 - dspck_tsimm prepend, 0xfffffdbf, 0xffff6c3a, 0xffffffed, 27 - dspck_tsimm prepend, 0x000464c3, 0x7fffffff, 0x00008c98, 29 - dspck_tsimm prepend, 0x80000004, 0x80000004, 0x00000000, 0 - dspck_tsimm prepend, 0x00000128, 0x00000128, 0x0000003c, 0 - dspck_tsimm prepend, 0x2002c2ed, 0x00161769, 0x00de5fe1, 3 - dspck_tsimm prepend, 0x00001fff, 0xffffff80, 0xf0000007, 22 - dspck_tsimm prepend, 0xfffe0000, 0x00000e92, 0x7fffffff, 15 - dspck_tsimm prepend, 0x0001fffe, 0x00000000, 0x0000ffff, 31 - dspck_tsimm prepend, 0xffffffff, 0xe0000001, 0x7fffffff, 31 - dspck_tsimm prepend, 0x01ffffff, 0x7fffffff, 0x00000000, 6 - dspck_tsimm prepend, 0xfffffc19, 0xfffffe0c, 0xfffffe0c, 31 - dspck_tsimm prepend, 0x40000000, 0x80000000, 0x00084488, 1 - dspck_tsimm prepend, 0xe0000000, 0x80000000, 0x7fffffff, 2 - dspck_tsimm prepend, 0x00000001, 0x80000000, 0x80000000, 31 - dspck_tsimm prepend, 0xfff80000, 0x00000000, 0xfffffffe, 14 - dspck_tsimm prepend, 0x00000001, 0xc71c71c7, 0x00000000, 31 - dspck_tsimm prepend, 0x00010000, 0x80000000, 0x00000000, 15 - dspck_tsimm prepend, 0x83fffffe, 0x07fffffc, 0x0001594b, 1 - dspck_tsimm prepend, 0x00800000, 0x80000000, 0x80000000, 8 - dspck_tsimm prepend, 0x1ffffff0, 0x1ffffff0, 0x8000007f, 0 - dspck_tsimm prepend, 0x3ff28345, 0xffca0d15, 0x7ffffff8, 2 - dspck_tsimm prepend, 0x00000001, 0xfffffffc, 0x00000000, 31 - dspck_tsimm prepend, 0x00000000, 0x00000002, 0x80000000, 4 - dspck_tsimm prepend, 0xa4f1ca00, 0x80000000, 0x00293c72, 22 - dspck_tsimm prepend, 0xe03fffff, 0xffffff58, 0xffffff80, 10 - dspck_tsimm prepend, 0x001fe01f, 0x00ff00ff, 0x80000000, 3 - dspck_tsimm prepend, 0xe1e1e1e1, 0xffffff80, 0xf0f0f0f0, 31 - dspck_tsimm prepend, 0x56c7a000, 0x000037a4, 0x0012b63d, 19 - dspck_tsimm prepend, 0xf07fffff, 0x3ffffff8, 0xfffffff8, 7 - dspck_tsimm prepend, 0xfffa4948, 0x00000000, 0xffff4929, 29 - dspck_tsimm prepend, 0xfffffff8, 0xfffffff0, 0xf8000003, 1 - dspck_tsimm prepend, 0xffffff00, 0x00000000, 0x7fffffff, 24 - dspck_tsimm prepend, 0x00120000, 0x00000007, 0x00000009, 15 - dspck_tsimm prepend, 0xffc1ffff, 0xffffff9d, 0xffffffe0, 15 - dspck_tsimm prepend, 0x0000007f, 0xfffe3d99, 0x80000000, 25 - dspck_tsimm prepend, 0x00000000, 0x00000000, 0x00000000, 7 - dspck_tsimm prepend, 0xfde6992d, 0x80000005, 0xfef34c96, 31 - dspck_tsimm prepend, 0xffffffff, 0xffffffe8, 0x7fffffff, 29 - dspck_tsimm prepend, 0x1ffffff0, 0x00000000, 0x0ffffff8, 31 - dspck_tsimm prepend, 0x7ffffffe, 0x7ffffffe, 0xff0fceda, 0 - dspck_tsimm prepend, 0x00000000, 0x00000000, 0x0002e398, 0 - - writemsg "[29] Test shra.qb" - dspck_dtsaio shra.qb, 0x00ff0000, 0x00ff3f01, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x003fe138, 0x007fc371, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000701, 0x01001d04, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0300fffc, 0x6d18fd87, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0dffc3ff, 0x0dffc3ff, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ff05ff, 0x00ff14ff, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000003ff, 0x000e35f9, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x01ff0000, 0x06ff0000, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xf9f800f5, 0xcfc705aa, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ff0000, 0x02bf0900, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000214, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ffffff, 0x00ffffff, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x87080001, 0x87080001, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xf1000300, 0xe3000701, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x030300ff, 0x7f7000ff, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0000ff, 0xff0100ff, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff05ff07, 0xff59ff78, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ff0000, 0x00ff001c, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff00ff02, 0xff01ff04, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0cfe01, 0xff0cfe01, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0000ff00, 0x0000ff00, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0f0e00, 0xff1e1c00, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff000000, 0x8f070d04, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000003, 0x06000039, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000f00f0, 0x000f00f0, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000100, 0x01010f00, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000004, 0x00000008, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x0d070300, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfafc00ff, 0xaac700ff, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xffff00ff, 0xffff00ff, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0cffff00, 0x66ffff03, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x06e700e6, 0x1b9f0199, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfb040000, 0xdb240000, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0efe0304, 0x38f90f12, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00e00300, 0x00810f00, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xe61f0803, 0x997c200f, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ffff00, 0x72e3ff00, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xf00f0809, 0x807e404d, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0ef3ffed, 0x1ce7ffdb, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00fffff1, 0x04ffff8e, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ff0100, 0x00f91101, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x007f2001, 0x007f2001, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfb0f09ff, 0xef3f27ff, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00023f00, 0x00047e00, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ff0000, 0x1fff0006, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000000ff, 0x020700ff, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff003e03, 0xff007c06, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xf800feff, 0x8100e7ff, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x541ecfbf, 0x541ecfbf, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x1500f701, 0x2a00ef03, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0000ff00, 0x3000f100, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfd0300fe, 0xaa7e00c7, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ff0009, 0x02ff0048, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000000ff, 0x010000ff, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff00fe00, 0xff00aa19, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff000000, 0x9208001c, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000000ff, 0x130003e7, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfffff000, 0xffffc102, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x07000319, 0x0e000733, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff000000, 0xff00011e, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff00f000, 0xff01e000, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0100ffff, 0x7a04ffff, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff000200, 0xff000b01, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xefff0100, 0xbfff0600, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x03ffff00, 0x70f1ff00, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x03f80301, 0x3f8e3019, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00027c03, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xf9003c01, 0xf9003c01, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0000fe, 0xf8112e99, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0006f5, 0xff0030aa, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x0c050204, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ffff00, 0x01ffff00, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xf3000100, 0xcc000400, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x0220077f, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x01000010, 0x03010020, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x01ff0009, 0x07ff0124, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfffc0000, 0xffe10301, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfe0400f8, 0xf02000c1, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff000012, 0xff010024, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x001b0603, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0000ff00, 0x3e1bff02, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfd3301ff, 0xfd3301ff, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfc070000, 0xe33d0000, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0000ff02, 0x0000ff02, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x023706e0, 0x046e0cc0, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xc3ff0700, 0xc3ff0700, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0000f806, 0x00008166, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x60ff0105, 0x60ff0105, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xf3ff0100, 0x99ff0800, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000004, 0x03010046, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000001, 0x0c00102b, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0001ff00, 0x0660f93c, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff000df3, 0xff0036cc, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0000ff03, 0x0102ff3b, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0003ff, 0xff000fff, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00038103, 0x00038103, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x03ff00f6, 0x1cff00b6, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xf600030a, 0xdb010e2b, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x02ff0300, 0x24ff3a00, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000000ff, 0x3f1000ff, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00e00f00, 0x01c11e01, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff00f900, 0xff009900, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfe000000, 0xc31b0400, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x38ff00c3, 0x70ff0087, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0000ff, 0x8e0009f9, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00010001, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0901d500, 0x1303aa00, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0000ff, 0xff0007ff, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x06fff803, 0x6aff8138, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00f30300, 0x019f1c03, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0002ffff, 0x0027fff0, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00fe0000, 0x00f80000, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x021f0049, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000301, 0x061b6f24, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0700016c, 0x0700016c, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfc03ff00, 0x817fff00, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff00ff00, 0x8e00cf00, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfd000000, 0xaa1a0e1f, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ffff01, 0x00ffff01, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x01ffff01, 0x18f0ff1a, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0000ff, 0xff003fcf, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xf00001f9, 0x81000ccf, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff00ff00, 0xff00ff02, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0000ff00, 0x0000ff24, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x129f0908, 0x129f0908, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x1b0000ff, 0x6d0001ff, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0f0007ff, 0x3d001fff, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ffff00, 0x1ee7c700, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff030000, 0xff1d0000, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff000000, 0xf90e0159, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff030200, 0xff332b00, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ffff00, 0x00c7e700, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x1c08ffff, 0x7120ffff, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xffffff00, 0xff99c300, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000000ff, 0x030800aa, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfe000001, 0xdf171c20, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff000000, 0xff08331c, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x02001c00, 0x05003800, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0102ffff, 0x1820f8ff, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000002, 0x0001024d, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ffff01, 0x00ffc160, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000100, 0x06054800, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00010003, 0x0e1a0638, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0000ffff, 0x0000ffff, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x01030700, 0x040e1f01, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfd0000f8, 0xdb00068e, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x05000001, 0x2f000008, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff09ffff, 0xff48ffff, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0002e101, 0x000a8706, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ff0000, 0x0dff001f, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00fe00ff, 0x03cc00ff, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0f0614ff, 0x1f0c29ff, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0000ff, 0xc30f05ff, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x001f1509, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff00ffff, 0xe00affff, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xeaf00006, 0xaac00018, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0000fc02, 0x00009f47, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0006ffff, 0x0118ffff, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xcc090000, 0xcc090000, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000000fc, 0x000700e0, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xe300f13e, 0xc701e37c, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0000ff38, 0x0000ff70, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0600f0, 0xff0600f0, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x60c30dff, 0x60c30dff, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfffc0000, 0xfde70001, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x06c00700, 0x06c00700, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ffff00, 0x00f1ff0c, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xffb61fff, 0xffb61fff, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00010000, 0x01330700, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00fe00ff, 0x018f02ff, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0465cc0e, 0x0465cc0e, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0000ff, 0xff0700ff, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfff600ff, 0xffb600ff, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ff01ff, 0x00ff38e0, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000000ff, 0x000f1eff, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xe3021701, 0xe3021701, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ff0a00, 0x00ff5403, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfc000000, 0x80000100, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0000ff, 0xff000fff, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0f000300, 0x1f000700, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0fff0007, 0x7fff003f, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000100, 0x32287e00, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00020004, 0x00160320, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfefeff00, 0x819ffe10, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ff0300, 0x03ff7f00, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x01ffff00, 0x24ffff00, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000000ff, 0x000000ff, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x06ff6000, 0x06ff6000, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xffffff03, 0xffffff03, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000c0700, 0x00331c00, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xffc79f04, 0xffc79f04, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xe3ffffff, 0xc7ffffff, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ff041c, 0x00ff1371, 2, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000001fe, 0x000038df, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x03000c01, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfff9f101, 0xfccf8e0f, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfffe0000, 0xffe10100, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff0106f6, 0xf90d36b6, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xc75500ff, 0xc75500ff, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x1ee30001, 0x3dc70103, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0000000a, 0x00010755, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x0201003f, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x1f7e0e00, 0x1f7e0e00, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x02003f01, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff000000, 0xc1660d07, 7, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xfffeff00, 0xffc7ff00, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xf206ff00, 0x9231ff01, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000300ff, 0x007f0efc, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0000fc00, 0x0c00c00f, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00ff0100, 0x08ff3c01, 5, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x096071ff, 0x096071ff, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x3f0300ff, 0x7e0600ff, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0630ff30, 0x0c60ff60, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xe3133849, 0xe3133849, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff01ff02, 0xff1efe20, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x05000002, 0x5504002d, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x02000e00, 0x15007102, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x018e030c, 0x018e030c, 0, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000003, 0x0101033e, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000113, 0x00010227, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0001fcf8, 0x070ee1c0, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x000000ff, 0x020000ff, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0cff0fff, 0x60ff78ff, 3, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0001ff00, 0x0103ff01, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0xff010000, 0xff170600, 4, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x010000ff, 0x783a04db, 6, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x0c0e3200, 0x181d6500, 1, 0x0, 0x0 - dspck_dtsaio shra.qb, 0x00000000, 0x00000000, 5, 0x0, 0x0 - - writemsg "[30] Test shra_r.qb" - dspck_dtsaio shra_r.qb, 0x01060078, 0x01060078, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0001fe00, 0x001acc00, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00003100, 0x00003100, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0111e7ff, 0x0111e7ff, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00020400, 0xff080e00, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x0bff0002, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xe0051f1e, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000008, 0x0000001e, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000100, 0x15047cff, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xf9100005, 0xc77e0129, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x10020000, 0x200400ff, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x706d0d09, 0x706d0d09, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0000ff00, 0x0101bf01, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x10100000, 0x1f1fffff, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x3e000000, 0x7cffffff, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x0607ff11, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xff00030f, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xe0f907ff, 0xe0f907ff, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x100fffff, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000200, 0x080b781e, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x20c71c30, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000004, 0x0000ff07, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x009905ff, 0x009905ff, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000001, 0x24010049, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0a000000, 0x26ff0100, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00f01e00, 0x00bf7800, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xdbffe019, 0xdbffe019, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00001007, 0x00ff200e, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x01000000, 0x54c7001e, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0007f500, 0x0038aafd, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000002fd, 0x06033b92, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00040001, 0xff470016, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000e070f, 0x001b0d1e, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00f208e0, 0xffc72080, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00ff0000, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x99180083, 0x99180083, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xdb010300, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0100050f, 0x09012478, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000300, 0xff006d0d, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0c000800, 0x60ff3c01, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x02020000, 0x1b21ff00, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xf2000005, 0xc701ff12, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xff00000b, 0xff00000b, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00f90003, 0xff8fff30, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x04ffe7ff, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0c0005cc, 0x0c0005cc, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00ff0700, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x02000003, 0x0700000c, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00ff0200, 0x00fd03ff, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00010000, 0x00550eff, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x0400ff00, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xff000000, 0xe0ffff01, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x11010c00, 0x220218ff, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x000a00ff, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00060500, 0xff0b0aff, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0000f701, 0x0100db04, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x01010000, 0x3e260101, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000001ff, 0x000001ff, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0001ff00, 0x0838cf00, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000010f0, 0xff0040bf, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0000ff00, 0x0300990f, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x1000f41f, 0x3e00cf7c, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x20793338, 0x20793338, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000000ff, 0x0f00ff87, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x001c011c, 0x00370238, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x03000003, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00070000, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xef00ff03, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x1e13000d, 0x1e13000d, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x080c00ff, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00f90000, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000d0300, 0x001a0600, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x18f7ff01, 0x18f7ff01, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0000fa05, 0x00ffe715, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x04000b00, 0x230055ff, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000108, 0x01ff0420, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000000ff, 0x00f901aa, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000300, 0x07006602, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000100, 0x02ff08fd, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x4002e800, 0x7f03cfff, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000300fe, 0x000bfff7, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000100, 0x02001300, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00c8000c, 0x008fff17, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0a9f000e, 0x0a9f000e, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0000003e, 0x00ff007c, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x020002fe, 0x1dff18e0, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000002fd, 0x00000fe7, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000100fe, 0x032c00c1, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xff080001, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000200fe, 0xff4df9c0, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x06001f00, 0x18ff7c00, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xb601ffff, 0xb601ffff, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x30f40933, 0x60e71166, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xf20003f0, 0x92031b81, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00350037, 0x0069006e, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xfe020000, 0x817303ff, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00020100, 0xff3f19ff, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x25ee3c08, 0x49db780f, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xffff0003, 0xffff0003, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000000fa, 0xffffff9f, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x07ff0000, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00010001, 0x007f0052, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0000fe10, 0x0000ef7e, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xaa0000ff, 0xaa0000ff, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x12070b02, 0x240e1503, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xf0080000, 0xc01e0001, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0000000f, 0x02010075, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xee000c01, 0xb6003003, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xff000905, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xe1000103, 0x8300020c, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xff000000, 0xe3000000, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x10070800, 0x7e383cff, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000008, 0x0000003c, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xff00f700, 0xf900b603, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00ff0100, 0xffcc35ff, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0000fa01, 0x0101e703, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xfa010002, 0xcf0b010e, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x05fa1004, 0x26cc7e21, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x02010303, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xffff00ff, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xff101ce0, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00010001, 0xff2dff18, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x03000002, 0x6000ff35, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000001, 0xe3ff1020, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0eeb0100, 0x36aa0300, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00030000, 0x01300000, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00fd0100, 0xfff30501, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0000fc06, 0x00fff70c, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0001fe01, 0xff409f40, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0408fd08, 0x0e20f31e, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x24ff609f, 0x24ff609f, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x01000000, 0x66ffff2a, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x09fd0e00, 0x12f91c00, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xfff30192, 0xfff30192, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00080000, 0x013f0000, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0c00011f, 0x0c00011f, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00ff0101, 0xfff70709, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x01000101, 0x06fe0408, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00080000, 0x067eff00, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000100, 0x00ff7802, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00020010, 0x0003ff1f, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00010000, 0xff550002, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x2500f001, 0x2500f001, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000110, 0xff00011f, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000000ff, 0x30000083, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000100, 0x15ff7806, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x100b0500, 0x100b0500, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00e40000, 0xff8fffff, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000500f9, 0xfd4eff8f, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000002, 0x00000c30, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00070000, 0xff390000, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x02030003, 0x080cff0c, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00f80005, 0xff83014d, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00010100, 0x007e41f1, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x011b0304, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x02fe0000, 0x30bf0300, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x0100f00c, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xfdfd0000, 0xf3f30101, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x01040000, 0x1f7ffe04, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x1e04010f, 0x3b08021e, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0100fe00, 0x2b00c700, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xffff0000, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0002ffe0, 0xff04fdc0, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00ff0802, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x008e0600, 0x008e0600, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xffccfc3e, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x04010010, 0x04010010, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00030000, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00010000, 0xff7e000f, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0c0000e2, 0x170000c3, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x02ff0400, 0x3fe07f03, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x0112000c, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x7f0000e1, 0x7f0000e1, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000001, 0x0100055d, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x04000100, 0x46000f01, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xe79f0106, 0xe79f0106, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x24618f00, 0x24618f00, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00e74900, 0x00e74900, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000200fe, 0x0c7f0a99, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x090efd07, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000000ff, 0x000001db, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00e00403, 0xff810e0d, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xf3090300, 0x994918ff, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x09000000, 0x49000000, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x79ff3018, 0x79ff3018, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000000ff, 0xff0100f9, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00e1ff03, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x04fe0002, 0x71c1f13a, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x01010001, 0x2416f117, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xff000000, 0xef0c0200, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xc800001c, 0x8fff0038, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x07f200fc, 0x389201e3, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00010000, 0x3f4000ff, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00100100, 0x003f02ff, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00380000, 0x00380000, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x020a0013, 0x0927ff4d, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x18c0e004, 0x18c0e004, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000000ff, 0x3f03ef87, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x001f7cff, 0x001f7cff, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000006ff, 0xff0066f0, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00ff06fc, 0x02f733e0, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00010002, 0x0005010e, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x1c00f700, 0x1c00f700, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x0800fc00, 0x7fffc3f9, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x1fc30fc3, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00f20000, 0xff8e0000, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x0aff0000, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000100, 0x010a551c, 6, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000100, 0x00ff1804, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00010000, 0x001affff, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00020000, 0x0007ff00, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xff0fffff, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00020002, 0x01070006, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x07010003, 0x7213ff2a, 4, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x03000000, 0x0aff0100, 2, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x000000ff, 0xf80003e1, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xc33c3302, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x68ff00ff, 0x68ff00ff, 0, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x040000ff, 0x71fff0df, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0xffff0100, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x00000000, 3, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x003c1fe1, 7, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0xc2d5e600, 0x83aaccff, 1, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x01000000, 0x1400ff00, 5, 0x0, 0x0 - dspck_dtsaio shra_r.qb, 0x00000000, 0x02011cff, 6, 0x0, 0x0 - - writemsg "[31] Test shrav.qb" - dspck_dstio shrav.qb, 0x00000000, 0x02020003, 0xafd3a2af, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x04000101, 0x3fa6c62b, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000ff0e, 0x0100ff1c, 0xc0a75279, 0x0, 0x0 - dspck_dstio shrav.qb, 0xfcfcfc03, 0x9f8f8061, 0x2dd91095, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ff6007, 0x00ff6007, 0x00000000, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x39010030, 0xb35f4bd6, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0100ff00, 0x0c00ff00, 0xb39018b3, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xdd9d8345, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x0009010d, 0x117dc387, 0x0, 0x0 - dspck_dstio shrav.qb, 0x165b1edf, 0x165b1edf, 0x8bdd73b0, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff00ffff, 0xff00ffff, 0xa882ebfc, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x01000b00, 0xa1f78da5, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff0000f8, 0xff0000c1, 0xc240332b, 0x0, 0x0 - dspck_dstio shrav.qb, 0x1f002b00, 0x3f005600, 0x9d77deb9, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff00ff00, 0x87188134, 0x98ddb447, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff00ffff, 0x8204819f, 0x8204819f, 0x0, 0x0 - dspck_dstio shrav.qb, 0xfcfff00e, 0xe1ff8071, 0xe85e9f4b, 0x0, 0x0 - dspck_dstio shrav.qb, 0x01ff0000, 0x36ff0000, 0x63dc6b55, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000100, 0x070e6610, 0x96ce4886, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00021e08, 0x00053c10, 0x061c5191, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0001040f, 0x0306103f, 0x49591efa, 0x0, 0x0 - dspck_dstio shrav.qb, 0xffff019f, 0xffff019f, 0x2e3876b8, 0x0, 0x0 - dspck_dstio shrav.qb, 0x47394dc0, 0x47394dc0, 0x47394dc0, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xf5574786, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00bf8700, 0x00bf8700, 0x42635220, 0x0, 0x0 - dspck_dstio shrav.qb, 0xfe0000ff, 0xb60000ff, 0x15d4257e, 0x0, 0x0 - dspck_dstio shrav.qb, 0x1f00d512, 0x3f00aa24, 0xdf5baef1, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00f90000, 0x06cc0500, 0x06ec25e3, 0x0, 0x0 - dspck_dstio shrav.qb, 0xfeff0000, 0x99e70302, 0xe9b3a706, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00f37c00, 0x00f37c00, 0x0dbd3a00, 0x0, 0x0 - dspck_dstio shrav.qb, 0x01051207, 0x0517491c, 0x0f07fe0a, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0106001f, 0x0106001f, 0x8f132c78, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ffff00, 0x00ffff03, 0x2945c7ed, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0001fd00, 0x062cb11d, 0x062cb11d, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff0000ff, 0xe00c08ff, 0xac63fe5d, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff010000, 0xff3f0203, 0xbe03f215, 0x0, 0x0 - dspck_dstio shrav.qb, 0x02ff0dff, 0x08ff37ff, 0x0b8206a2, 0x0, 0x0 - dspck_dstio shrav.qb, 0x05000000, 0x5b030d01, 0xefe6d0f4, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0x417f4151, 0x0, 0x0 - dspck_dstio shrav.qb, 0x380022ff, 0x380022ff, 0x21b5f3f0, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0d0a1402, 0x352a530a, 0x352a530a, 0x0, 0x0 - dspck_dstio shrav.qb, 0x03ff0000, 0x33ff070c, 0x49b3c244, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff0100ff, 0xff0c00ff, 0xf802e8c3, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000ffff, 0x0006ffff, 0x0e271af5, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0b700000, 0x0b700000, 0x00000000, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000300f8, 0x000600f1, 0xd4bc0121, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000100fe, 0x042001cf, 0x87f2742d, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000ff00, 0x0500ff03, 0x36e58b23, 0x0, 0x0 - dspck_dstio shrav.qb, 0x01000000, 0x06000202, 0x3f6da0fa, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00fb0101, 0x00db0b0a, 0xa68689f3, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000001, 0x00051a27, 0x06d1563d, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000000ff, 0x000300ff, 0x93639cc4, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0f010000, 0x7e080000, 0x859a2a53, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0100ff03, 0x0800ff1f, 0x66c89803, 0x0, 0x0 - dspck_dstio shrav.qb, 0xffff0407, 0xffff111c, 0x173c43e2, 0x0, 0x0 - dspck_dstio shrav.qb, 0x1bff00fb, 0x37ff01f7, 0x60ab3591, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000f0fb, 0x0000c0ef, 0xe332bb62, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x3f060f1f, 0x3695b34f, 0x0, 0x0 - dspck_dstio shrav.qb, 0xfe000700, 0xef037100, 0xa8a15ae4, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0003ff00, 0x1e6dff00, 0xcd7da8bd, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000f707, 0x0000f707, 0x00000000, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000107, 0x00001e71, 0xc58eccb4, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff0000ff, 0xff020bff, 0x86423814, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00f00003, 0x00e10107, 0x4d551709, 0x0, 0x0 - dspck_dstio shrav.qb, 0x05ffff00, 0x29ffff00, 0x32044deb, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff000000, 0xff010202, 0x9c48e7a5, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000000ff, 0x000018c3, 0x315e3446, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ff0000, 0x00ff0004, 0xc41aca7e, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000101ff, 0x050f0eff, 0x94849dbb, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000001fe, 0x001d36c3, 0xc39610f5, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff0001ff, 0xff0309ff, 0x4ed1528b, 0x0, 0x0 - dspck_dstio shrav.qb, 0xe0fd04ff, 0x83f710ff, 0xac920fca, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000f000, 0x0100c103, 0x06a82daa, 0x0, 0x0 - dspck_dstio shrav.qb, 0x02ffff00, 0x24fdff01, 0xf20a70a4, 0x0, 0x0 - dspck_dstio shrav.qb, 0x7840fff7, 0x7840fff7, 0x1924ffd8, 0x0, 0x0 - dspck_dstio shrav.qb, 0x03ff24ff, 0x03ff24ff, 0x0619b520, 0x0, 0x0 - dspck_dstio shrav.qb, 0x04ff098e, 0x04ff098e, 0xe6650048, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0eff0001, 0x1cff0003, 0xea144cb1, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff0100ff, 0xdb7e06ff, 0xdfa828de, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff000100, 0xfc0c3c00, 0x5911f40d, 0x0, 0x0 - dspck_dstio shrav.qb, 0x01e40000, 0x05920300, 0x19d88f1a, 0x0, 0x0 - dspck_dstio shrav.qb, 0xffffffe0, 0xffffffc0, 0x651ab179, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00330016, 0x00330016, 0x86d483b8, 0x0, 0x0 - dspck_dstio shrav.qb, 0x01000008, 0x0f000040, 0xff5594a3, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff010300, 0xff030600, 0x4b9c7bd9, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000000e, 0x0000001c, 0xd4498c01, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000000ff, 0x007102ff, 0xb63d928f, 0x0, 0x0 - dspck_dstio shrav.qb, 0xf0001938, 0xe1013370, 0x501b0be9, 0x0, 0x0 - dspck_dstio shrav.qb, 0xe008ff00, 0xc111ff00, 0x0f48f791, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00010400, 0x01030901, 0x03bec071, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff3e3002, 0xff7c6004, 0x1408a259, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xab16062d, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000000ff, 0x30003efc, 0xd50a4476, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x02010006, 0x19f2191b, 0x0, 0x0 - dspck_dstio shrav.qb, 0x03ff03fd, 0x66f371bd, 0x66f371bd, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0b0bff06, 0x0b0bff06, 0x537ca288, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0ef900ff, 0x3be703ff, 0x0314e022, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000000fe, 0x000803aa, 0x78d420d6, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000600c1, 0x000c0083, 0x2ecd3cc9, 0x0, 0x0 - dspck_dstio shrav.qb, 0xffffffff, 0xffffbf8e, 0x96dd54e7, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00f11f00, 0x00c77c01, 0xd2c78f22, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000006ff, 0x000a60f7, 0x6deed8ac, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00090000, 0x8c623acd, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0001f803, 0x04118133, 0xdfc175a4, 0x0, 0x0 - dspck_dstio shrav.qb, 0x07f3f300, 0x1fcccc00, 0x874135ba, 0x0, 0x0 - dspck_dstio shrav.qb, 0xf9ff10c0, 0xf9ff10c0, 0x00000000, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000000ff, 0x17070c8e, 0x24d2eb27, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ff00ff, 0x00aa00aa, 0xe98fb6c7, 0x0, 0x0 - dspck_dstio shrav.qb, 0x010cff33, 0x010cff33, 0xb92126d0, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0007ffff, 0x003cffff, 0x85da748b, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0100fc00, 0x33008702, 0xa5e7f1e5, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000ff00, 0x0001f100, 0x39b74ddd, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000000f1, 0x000000f1, 0x00000000, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000000c7, 0x0000008f, 0xa5d38501, 0x0, 0x0 - dspck_dstio shrav.qb, 0xd33be338, 0xa676c771, 0xa676c771, 0x0, 0x0 - dspck_dstio shrav.qb, 0xfe000001, 0xe100001f, 0xd257bb44, 0x0, 0x0 - dspck_dstio shrav.qb, 0xfffffc00, 0xffffe000, 0x80856f23, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000033, 0xfca7c1af, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0b000005, 0x1600000a, 0xfcf17749, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0300c300, 0x07008700, 0xf7d6c109, 0x0, 0x0 - dspck_dstio shrav.qb, 0x01fc0000, 0x10cf0001, 0xbdf51434, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000fd00, 0x0300db00, 0xd5835b3c, 0x0, 0x0 - dspck_dstio shrav.qb, 0x2a300707, 0x55610e0f, 0x4a0f2999, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ff0000, 0x00ff0031, 0x542810b7, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00fcff00, 0x07cfff01, 0xd483ba64, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000ff00, 0x0007ff00, 0x939cb144, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0100ff00, 0x6018ff0c, 0xda2ae0a6, 0x0, 0x0 - dspck_dstio shrav.qb, 0x1d000574, 0x1d000574, 0x81c54170, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xd90eac9c, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x02000100, 0x45fa4234, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000000fc, 0x05021692, 0xd2a97325, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ff0000, 0x15c00000, 0x26163786, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000208ff, 0x010510ff, 0x5642cae9, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ffff00, 0x07ffff01, 0x06c6977d, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xcf158188, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0x89751668, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000ffe1, 0x0000ffc3, 0x051fe121, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0f1400f6, 0x3f5200da, 0x3f5200da, 0x0, 0x0 - dspck_dstio shrav.qb, 0x180d0100, 0x311a0200, 0x1fc3d561, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0c00ff01, 0x1900ff02, 0x85158e01, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff0001f8, 0xff0008c0, 0x42ddc17b, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000001ff, 0x00001cff, 0xd8c9f45c, 0x0, 0x0 - dspck_dstio shrav.qb, 0x010000ff, 0x040001ff, 0x3655c3c2, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xea33d1d2, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00070001, 0x58f8fe47, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff041800, 0xff041800, 0xe459f6d8, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ff0000, 0x04e32426, 0x42839a26, 0x0, 0x0 - dspck_dstio shrav.qb, 0x02030000, 0x0b0e0200, 0x3c75a952, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00f8f0ff, 0x00c181ff, 0xafd45b2b, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00301e00, 0xa85dfb5f, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff000000, 0xff006601, 0x7d9c855f, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff06001b, 0xff18006d, 0x1dcd6cf2, 0x0, 0x0 - dspck_dstio shrav.qb, 0x01000003, 0x0b000018, 0x3f66acf3, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff000000, 0xff000204, 0xc90e2906, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00fe00f8, 0x04e00383, 0xeeb69444, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000c00ff, 0x006000ff, 0xe8ac4013, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff02fe01, 0xe155c625, 0xe155c625, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff010000, 0xff180300, 0x00f72d24, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff00ffff, 0x8e48fff1, 0x7b3afccf, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00060416, 0x00060416, 0xde10aa60, 0x0, 0x0 - dspck_dstio shrav.qb, 0x001c1205, 0x00714914, 0xd51c7482, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff020002, 0xff4e005f, 0xe30ca9f5, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff0000ff, 0xfd0100bf, 0x46699ddf, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000ff00, 0x0101ff04, 0x25bb8687, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0x96640109, 0x0, 0x0 - dspck_dstio shrav.qb, 0x36000b00, 0x6d001600, 0xc4451731, 0x0, 0x0 - dspck_dstio shrav.qb, 0xe300ff30, 0xc700ff60, 0x52d5c559, 0x0, 0x0 - dspck_dstio shrav.qb, 0x380f17ff, 0x701e2eff, 0xf200a999, 0x0, 0x0 - dspck_dstio shrav.qb, 0x2e000700, 0x5c000e00, 0xf33d2349, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff000701, 0xff007119, 0xda59fd44, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff01ff00, 0xf710ff01, 0x2ef51474, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ff0107, 0x00ff1d70, 0x4923c7e4, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000100, 0x113a4923, 0x742077fe, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff381800, 0xff703100, 0x3b772a49, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0103ff00, 0x0103ff00, 0x42bfc240, 0x0, 0x0 - dspck_dstio shrav.qb, 0x1a01effd, 0x1a01effd, 0x71d8f2c8, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00010001, 0x00680147, 0x5b418ea6, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff010006, 0xff16076d, 0xf6845a7c, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000302fc, 0x12704b8f, 0x897b354d, 0x0, 0x0 - dspck_dstio shrav.qb, 0xffff0a01, 0xffff2906, 0x91185112, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0x2afc9373, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff030000, 0xff1e0000, 0xc08259b3, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00030f0e, 0x9ed5dad4, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff0000fe, 0xc01c0081, 0xa8c7260e, 0x0, 0x0 - dspck_dstio shrav.qb, 0x020000ea, 0x090001aa, 0x82443f9a, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff000000, 0xff000000, 0xd8801cd3, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x37000001, 0x24480ffe, 0x0, 0x0 - dspck_dstio shrav.qb, 0x03ff3800, 0x06ff7100, 0x5fcde621, 0x0, 0x0 - dspck_dstio shrav.qb, 0xe3cc0fff, 0xe3cc0fff, 0x80546498, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000000ff, 0x060000ff, 0xa63e71eb, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0xef98b601, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0007f800, 0x077e8301, 0x8fd74ca4, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0001f340, 0x0001f340, 0xf9525288, 0x0, 0x0 - dspck_dstio shrav.qb, 0x07000000, 0x7e040000, 0x2b9b0454, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff031d01, 0xff031d01, 0x3723b810, 0x0, 0x0 - dspck_dstio shrav.qb, 0x080c001e, 0x080c001e, 0x27388b78, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00fc0000, 0x00e70002, 0xfd5731ab, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff010001, 0xf37c3066, 0xadf6eeee, 0x0, 0x0 - dspck_dstio shrav.qb, 0x03010000, 0x7c380000, 0x6273b78d, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00030000, 0x16730000, 0x2ff34b55, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ff0303, 0x00ff0606, 0x9e9bf481, 0x0, 0x0 - dspck_dstio shrav.qb, 0x81000003, 0x81000003, 0x877e1140, 0x0, 0x0 - dspck_dstio shrav.qb, 0x03000003, 0x32000c30, 0xcac0f81c, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ff00ff, 0x00ff00ff, 0xf0769d3e, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff0003fb, 0xfe021edb, 0x3fde5653, 0x0, 0x0 - dspck_dstio shrav.qb, 0xfeff00fd, 0xccff00b6, 0xa1455fad, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff0600f8, 0xff3103c7, 0xce48298b, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x00000000, 0x8e94e6c8, 0x0, 0x0 - dspck_dstio shrav.qb, 0xffff02ff, 0xffff17ff, 0xc64cbde3, 0x0, 0x0 - dspck_dstio shrav.qb, 0xf801df00, 0xf103bf00, 0xb7c8b3c1, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff00ff00, 0xff02ff1e, 0xeaff692d, 0x0, 0x0 - dspck_dstio shrav.qb, 0xf9000000, 0x92000108, 0xcd1eda74, 0x0, 0x0 - dspck_dstio shrav.qb, 0x09066699, 0x09066699, 0xba540f48, 0x0, 0x0 - dspck_dstio shrav.qb, 0x3c0000ff, 0x780000ff, 0xbd382b61, 0x0, 0x0 - dspck_dstio shrav.qb, 0xf10700f3, 0xf10700f3, 0x96530318, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00fffe00, 0x1fff9203, 0xf6b888b6, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00010003, 0x0012053f, 0xd4bedd14, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ff0000, 0x03ff0302, 0xe69bf4bc, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0006fcf1, 0x0035e38e, 0xce0b293b, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00fffe00, 0x01e3bf10, 0xb6ff1c56, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000000f1, 0x000103c7, 0xeb1baaa2, 0x0, 0x0 - dspck_dstio shrav.qb, 0x1df00007, 0x3be0000e, 0x13eefe49, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000600ff, 0x0c6000ff, 0x6d6530cc, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ff010d, 0x00ff010d, 0x76c2f0d8, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x0001786d, 0x933f62cf, 0x0, 0x0 - dspck_dstio shrav.qb, 0xff0000fe, 0xff0500f0, 0x0700174b, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00f3f000, 0x009f8301, 0x07c93ba3, 0x0, 0x0 - dspck_dstio shrav.qb, 0xfcff0000, 0x87ff0000, 0xd7adcf45, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0003fb04, 0x0118db22, 0x9edbd473, 0x0, 0x0 - dspck_dstio shrav.qb, 0x000000ff, 0x000e00ff, 0x30b7e6ff, 0x0, 0x0 - dspck_dstio shrav.qb, 0xcc000701, 0xcc000701, 0x00000000, 0x0, 0x0 - dspck_dstio shrav.qb, 0x121aff04, 0x2535ff08, 0x09d93101, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00fff9ff, 0x03ffccff, 0x8388608b, 0x0, 0x0 - dspck_dstio shrav.qb, 0xf804ea1f, 0xe010aa7c, 0xee906422, 0x0, 0x0 - dspck_dstio shrav.qb, 0xf800ff00, 0xf101ff00, 0xbcbb8611, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00ff0400, 0x00f04000, 0xd26579c4, 0x0, 0x0 - dspck_dstio shrav.qb, 0x00000000, 0x60007800, 0xe87d4f0f, 0x0, 0x0 - dspck_dstio shrav.qb, 0x0000ff00, 0x0000b604, 0x08b5b807, 0x0, 0x0 - dspck_dstio shrav.qb, 0x020f031f, 0x041f063e, 0xc1b93021, 0x0, 0x0 - - writemsg "[32] Test shrav_r.qb" - dspck_dstio shrav_r.qb, 0x01000000, 0x3301040f, 0x242d09be, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x08ef04ff, 0x08ef04ff, 0x00000000, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xff000000, 0xefff0300, 0x60471685, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02f81700, 0x09e15c00, 0xb8f4bda2, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x550000f1, 0x550000f1, 0x93bd72c0, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x023a2500, 0x047349ff, 0x1512c6c1, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00f10006, 0xff870031, 0x5a89d3fb, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x0023f800, 0xb60ef5cf, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xff110949, 0xff110949, 0xd2e09ff0, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0000ff00, 0x00009f0f, 0xfe907307, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xf00b0102, 0x81550611, 0xd5b7e94b, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x39e80e01, 0x71cf1c01, 0x28f5f269, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00ef0003, 0x2687028f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000004, 0x0001003e, 0xe45d186c, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x010f01e4, 0x011e01c7, 0xcee65491, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x000001ff, 0x07007e83, 0x17124257, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xffff00fd, 0xd0e0fca5, 0xd0e0fca5, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x000904fe, 0xff4922f3, 0xaa1589b3, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x111fe219, 0x457a8762, 0x457a8762, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000001, 0x18000078, 0xfe0946a7, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01000000, 0x71000fc3, 0xe027864f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x920f055c, 0x920f055c, 0x00000000, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00010002, 0x00050013, 0x46bb17bb, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02000004, 0x3507f878, 0xc84e5045, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00fe1c00, 0xfff77100, 0x96f1736a, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xff000a04, 0xff000a04, 0x00000000, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00ff0000, 0x1081ffff, 0xbbd479f7, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x70562009, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xdb000000, 0xb6ffffff, 0xceeb3209, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xbf5be101, 0xbf5be101, 0x638a5990, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00060000, 0xff300000, 0xc6c80193, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xf8f80600, 0x83876000, 0x16aff16c, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xff0500ff, 0xff0500ff, 0xa37e4968, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000300, 0x00003603, 0x451d55fc, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xf700000a, 0xb6ff0052, 0xc97e86ab, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0d000200, 0x33ff0600, 0x9894bee2, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00ff0000, 0x008e18ff, 0x364d3e67, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x1fffff00, 0xc9033376, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00ff0000, 0x0536ff89, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000001, 0x0fff0579, 0xf61738e7, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x032c0000, 0x2a826707, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x06030115, 0x170b0455, 0xc1ae0e2a, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00ff0000, 0x00aaffff, 0xcbacb87e, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xff02ff01, 0xd46bb34e, 0xd46bb34e, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xe7fe2bff, 0xe7fe2bff, 0x00000000, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x06030300, 0x0008459e, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00001000, 0xff0040ff, 0xb93b915a, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02020100, 0x677f4a06, 0x9f141b8e, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000100, 0xff005500, 0xe4397cfe, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02000000, 0x49000300, 0x17825ba5, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01f100ff, 0x01e100fe, 0x03fc3491, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x0012000f, 0xc931e687, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xfc09000e, 0xdf440171, 0xdfaac933, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x0000ff07, 0x1986bee4, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000001, 0xfff00054, 0xc8d79356, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x09ff0000, 0xbbc8f8f6, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0000ff00, 0x06ffc707, 0xe90b9db6, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x301a0027, 0x6033004e, 0x07dcb981, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x73bef463, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01180002, 0x045e0008, 0x98da93ea, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xfafc0000, 0xe7f00000, 0x54b35ef2, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x1a3efcff, 0x337cf8fd, 0xa36a5c11, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xfe000000, 0x87e00013, 0x4d8800ae, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x06000000, 0x3000fd00, 0xe412b51b, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x4901ff49, 0x4901ff49, 0x00000000, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x010100fe, 0x38200083, 0xf5b9c7e6, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00050000, 0x0049fe00, 0x463b491c, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00ffffff, 0xe53983a5, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00fe0000, 0x1487ff01, 0x682f399e, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00ff01ff, 0x395b152d, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000103, 0x0d001b66, 0x9b1936a5, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0xff00feff, 0x7c8e6786, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x1e000100, 0xc771647f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000200, 0x00ff0400, 0x36e1a469, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xffff1cfc, 0xffff1cfc, 0x877b2530, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0xff260205, 0x9900067f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x2371af46, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xffc75500, 0xffc75500, 0xfb9fb348, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000b00, 0x00005500, 0x38ed940b, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xe8f8f205, 0x9fdfc713, 0xc2cd014a, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01000b01, 0x01001601, 0xa5f80111, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x020c0000, 0x0730ff00, 0x528e8c4a, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000001, 0x0000ff24, 0xd47c0d7e, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01df0000, 0x01df0000, 0x00000000, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x06fe03ff, 0x58df31f4, 0x58df31f4, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xfd000000, 0xe700ff00, 0xc410611b, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x000000ff, 0x00030fdf, 0xd2494f75, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x000000fc, 0x00f9ffc1, 0xd9d062f4, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xffdb3ed0, 0xfeb67c9f, 0x304ab6a9, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01000002, 0x04010007, 0x37ea5b1a, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x49ff6681, 0x49ff6681, 0x0b6ea420, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x010d1504, 0x010d1504, 0x83e09d28, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x020000fe, 0x61ff009f, 0x2f50a106, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00ff03ef, 0x00ff03ef, 0x54d09060, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0d8c5298, 0x0d8c5298, 0x0d8c5298, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000300, 0x000362f3, 0xa5e9ccb5, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x040a201b, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xfc1a0000, 0xf06600ff, 0x6a9c5e7a, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00010000, 0xff08ff00, 0x074eb1a3, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00290000, 0x00290000, 0x93762660, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02000000, 0x3800ff00, 0x48a9cdc5, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0701cd02, 0x0e019904, 0xe4498451, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0a0ef900, 0x0a0ef900, 0x00000000, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00e40208, 0xff8e061e, 0xeeab1a0a, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0xff003e00, 0xa79b2f47, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00020200, 0xff434001, 0xe7617b0d, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000100, 0xff207e00, 0x5af39467, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00010001, 0xc443e76f, 0xc443e76f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01000100, 0x3f00490b, 0xafee0fd6, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00010701, 0x00010e02, 0x7410a9a9, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000002, 0x00000008, 0x30f14b02, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0a008100, 0x0a008100, 0x0dd94070, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xff000200, 0xec0327fc, 0xec0327fc, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00080001, 0x037c0011, 0xadeff08c, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000400, 0x00007eff, 0x5e569c2d, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0008303e, 0x000f607c, 0x9cd3b211, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x010000ff, 0x43ff06cc, 0x78a57306, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00020000, 0x007c05ff, 0xea658946, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0xc03dde95, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01000000, 0x0c0104ff, 0xf68aca14, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x051b0305, 0x051b0305, 0xf1384590, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x81190e00, 0x81190e00, 0xbfd1e558, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00ff0000, 0x206b0a24, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00ff00ff, 0x11990e8f, 0x11990e8f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00020000, 0x00040000, 0x4f7dd351, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0a02f000, 0x2908bf00, 0x0fa650ca, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01010101, 0x13162424, 0xd31bd115, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00030000, 0x00600008, 0x0e771295, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02000000, 0x4d0200f1, 0x8d564cd5, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xff00876d, 0xff00876d, 0xb4f870e0, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x010100fe, 0x403a029f, 0x5ca38336, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02000000, 0x4900ffff, 0x6c565805, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x000000ff, 0xcf020083, 0x407e9f27, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x070600ff, 0x070600ff, 0x0c048ac0, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x05020000, 0x4d1e0000, 0x74d658c4, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x808f85aa, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0014e002, 0x004e8007, 0x4f7e36c2, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00ff00fe, 0x18c30383, 0x6f593c76, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000005, 0xff00000a, 0xd31ffe59, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xdb7e0500, 0xdb7e0500, 0x5a21c1c0, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00f8fd00, 0x0087cf01, 0xab4fe12c, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x920a0325, 0x920a0325, 0xf2b828f0, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xfe000001, 0xe7020712, 0x42284324, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000200, 0x00017109, 0x42efba8e, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02020600, 0x0d0c3303, 0x20ee61db, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0000fe00, 0x0500cf07, 0xd61058bd, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0xf803fff8, 0x22ff6da4, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000004, 0xffff0038, 0xee761a1c, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xf7081eff, 0xf7081eff, 0xeb44b7f8, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0138db00, 0x0138db00, 0x00000000, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00050000, 0x0155ffff, 0x3d63281c, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x04000000, 0x10010000, 0x1385a6e2, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x09000000, 0x490301ff, 0x76f7c833, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0100f300, 0x07019900, 0x308ece2b, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0xf700ff07, 0x3ff4817e, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0xa5fb9a3f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000008, 0x00ff0278, 0xf0f3a2ec, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02000002, 0x3301013e, 0xf7f185cd, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01010000, 0x625e083c, 0xed380d7f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02010002, 0x361b0839, 0xf6d339b5, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x20010502, 0x7f021206, 0x662ff09a, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x003801ff, 0x003801ff, 0x0dff0f30, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00100401, 0x00400e02, 0x1f4f656a, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00040200, 0x000e0700, 0xf27342ba, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xffe3208e, 0xffe3208e, 0x17ba7058, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xeb00e415, 0xaa008f53, 0xfc013b02, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00ff0000, 0x0edb0101, 0x10b7c7d6, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x0003ff01, 0xb799731e, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x07160000, 0x0e2b00ff, 0xc919bf81, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0210006e, 0x0210006e, 0x00000000, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x1f1cf245, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xff150cff, 0xff150cff, 0xf379eda8, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000100, 0xfffd2410, 0x0be3f526, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000002, 0x0408ff6d, 0x0daf8956, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0000fc00, 0xfcff8000, 0xbeed5325, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x07fe01c0, 0xcfed84ff, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x09ffc303, 0x06c567c7, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02020000, 0x493e01ff, 0xcd1f25fd, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00ff0203, 0x03e33955, 0xa367eb2d, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0xc96c5e96, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x78009900, 0x78009900, 0xb3665bb0, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0000c100, 0xff008100, 0x23b16a21, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00400020, 0x007fff3f, 0x4bc39d21, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x71e7df02, 0x71e7df02, 0x00000000, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0xfff00600, 0x9ec54cc6, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00010001, 0x0632ff3f, 0x98ad56be, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01010202, 0x01020403, 0x371bb129, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00ff0000, 0xffaa0000, 0x33c4022f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x000104ff, 0xda281adc, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0401f9e6, 0x0f02e399, 0x4b81eec2, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x000000ff, 0xffff04cf, 0x41c8f006, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000100, 0x000578ff, 0xa7934b3f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xe4000102, 0xc7000104, 0x0f3d95a9, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x06c93e00, 0x0c927c00, 0x00785d99, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00007e00, 0x00007e00, 0x1b2347d0, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02000101, 0x06ff0402, 0xda698eaa, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xf700001f, 0xdbff007c, 0x75cf352a, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0xf700000a, 0xb955a7e6, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0xb46ce47c, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x04000202, 0x1e000f10, 0xed948deb, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x0000ff00, 0x09ef9ffe, 0x5b4e52ef, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00040000, 0xff73ff04, 0xe7a5fc7d, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000100, 0x030049ff, 0xdc2991be, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x0c8e982b, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x07090d00, 0x4ff82c0f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0xfffd0004, 0x12ad99bc, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x04000002, 0x3effff1f, 0x4e8a4e8c, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xff000000, 0xc0021e07, 0x049f2bae, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0xe0e70c02, 0xc38d562f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xff0000ff, 0x8f1c0080, 0xa425a9cf, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0xe81d3790, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00ff0000, 0x00cc0001, 0x9f2d62a6, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x04000003, 0x7101ff67, 0xe22220b5, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x32ab766e, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xf20500f7, 0x922500b6, 0xe9644183, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x1e0035ff, 0x502a8edf, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000004, 0x00ffff0e, 0xc76337ba, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00c1ff07, 0x00c1ff07, 0x6b3899d8, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00000000, 0x66854f6b, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01fd0001, 0x1899ff13, 0xa977a60d, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00fe0000, 0x04b60302, 0xd7d19e45, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01d01c00, 0x029f3700, 0x51bd5929, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x043801db, 0x043801db, 0x1c65f388, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x0000000e, 0x67925dfe, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02000000, 0x30ff00ff, 0x79699c05, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x55ff0104, 0x55ff0104, 0x4a05a198, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0xff000000, 0xf8ff0000, 0x7debe48b, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x1400000f, 0x00be0856, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x010c1892, 0x010c1892, 0x5fb16428, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x01010000, 0x7c781304, 0xdadc334f, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000200, 0xff00600a, 0xb96f1cfe, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0x00ff00ff, 0x8c1d6ddc, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x00000000, 0xf11c0703, 0x3bd612be, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x2d030000, 0x59050000, 0x7b8773e9, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02fcf500, 0x10e1aaff, 0x14b53d2b, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x04040810, 0x1c1c3e7e, 0x7edfdbbb, 0x0, 0x0 - dspck_dstio shrav_r.qb, 0x02fcf800, 0x18c18300, 0xaa7d35d4, 0x0, 0x0 - - writemsg "[33] Test shrl.ph" - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0fff0fc5, 0xfff7fc52, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00010000, 0xfb362492, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00001fff, 0x0000fffb, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x000f000c, 0xfffbc71c, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x7fff7fff, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00200000, 0x807f0000, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00010001, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x07fe07f8, 0xffceff10, 5, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x001c0001, 0x1c7101a9, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00010000, 0x1c7103fe, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00c70000, 0xc71c0006, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x09241ffd, 0x4924ffe8, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00380038, 0xe38ee00f, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x000e0000, 0xe003001f, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x3fc03fe2, 0xff00ff8b, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x03ff0000, 0x7fff0000, 5, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 9, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00010001, 0xfc01b6db, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x007c0040, 0xf9938000, 9, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x000003ff, 0x00007fff, 5, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0007007f, 0x07fc7fff, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x001e0100, 0x0f0f8000, 7, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x01ff0000, 0xffaf001f, 7, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00030000, 0xfffe0000, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00010001, 0xfe3f8000, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00010000, 0x7fff1dbb, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00010001, 0x0b5f0ffc, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00ff007f, 0xfff67fff, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x020001ff, 0x80007fff, 6, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00c000ff, 0xc001fffc, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x07ff3ffd, 0x1ffefff6, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0003001f, 0x007f03fe, 5, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x000001a9, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00070000, 0x7fc004b9, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x1ffe2000, 0x7ff88000, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x1fff1fff, 0x7fff7fff, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x000003c0, 0x0006f001, 6, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0030003f, 0xc003fff4, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x60077fff, 0xc00ffffe, 1, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x001c001f, 0xe001ffef, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x07ff0000, 0x7fff0000, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000004, 0x00018002, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x007f7fff, 0x007f7fff, 0, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00040000, 0x80000000, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x40003fff, 0x80007fff, 1, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x003f0020, 0xffeb8000, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00031ffc, 0x000d7ff0, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x16de0003, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x1c710391, 0x38e30722, 1, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00030000, 0xe38e0000, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x007f0040, 0xffc08000, 9, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x801fcd54, 0x801fcd54, 0, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x7fe07f8b, 0xffc0ff17, 1, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x7ff00000, 0xffe00000, 1, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00070003, 0x39dc1fe0, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x80000002, 0x80000002, 0, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x008000e1, 0x8000e14a, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00060000, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000018, 0x04ccc001, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x1fff0fff, 0xfffd7fff, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000040, 0x000a8000, 9, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x7fff7fff, 0x7fff7fff, 0, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x3ffb3fff, 0xffefffff, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0fff0000, 0x7fff0000, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0080007f, 0x80007ff9, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x000003ff, 0x00011ff8, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000007, 0x0356fe0f, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00080007, 0x80007ffc, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00137fc0, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x007f0100, 0x3fe08000, 7, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 0, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00030000, 0xf00301dc, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x02000000, 0x80030000, 6, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x001f6666, 0x003fcccc, 1, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00030003, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x03fa031b, 0xfe8fc6df, 6, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x001b1000, 0x00dc8000, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000006, 7, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x001f0019, 0x7fff6666, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x007f0000, 0xffe4017a, 9, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000fff, 0x00007fff, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0010001f, 0x8000fff5, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x35f20001, 0xd7ca0005, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x000f0080, 0x0ffc8003, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x08000000, 0x80040000, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x3fff7d81, 0x7ffffb02, 1, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x03ff07c0, 0x7ffff803, 5, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00070000, 0xfc880075, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x1fff3fff, 0x7ffdfffe, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00070006, 0xffffdb6d, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000001, 0x7fff9249, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00020000, 0x80000001, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00002000, 0x00008000, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00e30012, 0xe38e127f, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x3ff00000, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0000007f, 0x00007ffd, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x000301ff, 0x00fb7fff, 6, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x003f001f, 0xfffa7fff, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x03c30ffe, 0x0f0f3ff8, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000003, 7, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00010001, 0xf12e801f, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0000076d, 0x0000edba, 5, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x03ff03fd, 0xffffff5b, 6, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x02490fe9, 0x2492fe9d, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0000003f, 0x00001ffe, 7, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00040000, 0x80000000, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x01ff0043, 0x1ffe0433, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0000000f, 0x0000f003, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00020001, 0x92497fc0, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x01ff03ff, 0x7ffffffe, 6, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x03ff0ffe, 0x3ff8ffec, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00010001, 0xfffd8000, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x1fff01ff, 0xfffd0ff8, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00010000, 0x7ffb0000, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x001f0030, 0x7fffc00f, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00030003, 0x7fff7fff, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00010001, 0x800f803f, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x001f0000, 0x7fff0000, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x7fff07fc, 0x7fff07fc, 0, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x07800666, 0xf001cccc, 5, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x007f0000, 0x7ffa0000, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000125, 0x000024ba, 5, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x040003ff, 0x80007ffc, 5, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0002007f, 0x00b41ffc, 6, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0fff0000, 0x7ffa0000, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00030001, 0xf0037fff, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x000000e0, 0x0000e01f, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x07ff0000, 0xfffc0000, 5, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0001001f, 0x0d0fffa0, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00ff0000, 0xffff0033, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00020000, 0x80001c71, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x100001e1, 0x80000f0f, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00310000, 0xc71c0000, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x040003ff, 0x80007fff, 5, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000002, 0x00008000, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000040, 0x00808005, 9, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000010, 0x00048000, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x04fd07ff, 0x27ec3ffc, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0001000f, 0x0fa67f80, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000002, 0x003f8007, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00070007, 0x7fff7fff, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x01ff01ff, 0xfffdfffe, 7, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x007f0000, 0xffd80000, 9, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0000007f, 0x00007fff, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00ff007f, 0x7fff3fc0, 7, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000003, 0x00d3f801, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x1fff0000, 0x7fff0000, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000007, 0x0143f5ce, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00010001, 0xcbe08003, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x1fff0002, 0xfffb0011, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x03ff0000, 0xffcc0000, 6, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000200, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00100003, 0x80001ff0, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x000000ff, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x007f003f, 0xfe867fff, 9, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000ffc, 0x00000ffc, 0, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x03e00049, 0xf8011252, 6, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00070000, 0xfffd0003, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x07ff0e00, 0x7fffe007, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000007, 0x001b7fff, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x20003ffa, 0x8000ffea, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x8000cd47, 0x8000cd47, 0, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x001b0001, 5, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00030000, 0x0f0f0000, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00030000, 0x7f801ffe, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00070007, 0x1ff01daa, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00100007, 0x80003fc0, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x000d0000, 0x00d00000, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00020003, 0x8000ffff, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0fff0000, 0x7fff0000, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00040006, 0x8000c007, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0c030fff, 0xc03ffffc, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000003, 0x0000ff1b, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x003f0031, 0xfffec71c, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00070004, 0xffd98002, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00fe00ff, 0xfe6eff94, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x020000ff, 0x80043fe0, 6, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 6, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x3fff3fff, 0x7fff7fff, 1, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00003fff, 0x0000ffff, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x38e35b6d, 0x71c7b6db, 1, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x009d0000, 0x09d70004, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0aaa0803, 0xaaaa803f, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00080008, 0x803f8007, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x78137fff, 0xf027fffe, 1, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x40024000, 0x80058000, 1, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00030000, 0x3ffc0000, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x01ff0049, 0xff802492, 7, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x1ff9000b, 0xffc9005b, 3, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00030000, 0xcccc0041, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0000001f, 0x0000fe0a, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00010000, 0x80000000, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0010001f, 0x807ff801, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00008000, 0x00008000, 0, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0008000f, 0x8000fb96, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0000000f, 0x0000fef9, 12, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x007f0040, 0xfef68000, 9, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0fff0001, 0xfffc0013, 4, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00070007, 0xffd9e003, 13, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0000007f, 0x00067fc0, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00010000, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x1fff3fff, 0x7ffffffc, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x002a003f, 0x55557ffc, 9, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x001f0001, 0xff220ffe, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00480000, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x7fffe003, 0x7fffe003, 0, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00030002, 0xfea18e38, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x008000db, 0x8000db6d, 8, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x01ff01ff, 0xfffefffc, 7, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000002, 0x01538002, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x000f0000, 0x3fc00000, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000001, 0x00000005, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 7, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x000001c7, 0x0000e38e, 7, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00030000, 0xc71c0000, 14, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x007f0007, 0xffd80e1d, 9, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x0000002d, 0x03feb6db, 10, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x40000000, 0x80000000, 1, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00000000, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x001c0010, 0xe38e8000, 11, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x00000000, 0x00007fff, 15, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x20003ffd, 0x8002fff4, 2, 0x0, 0x0 - dspck_dtsaio shrl.ph, 0x07ff0003, 0x7fff0033, 4, 0x0, 0x0 - - writemsg "[34] Test shrlv.ph" - dspck_dstio shrlv.ph, 0x80001ffe, 0x80001ffe, 0x00000000, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00070001, 0xfff53333, 0x3815c9ad, 0x0, 0x0 - dspck_dstio shrlv.ph, 0xfffdff23, 0xfffdff23, 0x4e836a20, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x001b001f, 0xdb6dffff, 0x66d24b3b, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000005, 0x2059cb19, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x001f001f, 0xfffcfff9, 0x1138d8db, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00040000, 0x80001ffe, 0x0c5ccedd, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0feb0000, 0xfeb80000, 0xdcdf6034, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000010, 0x00048000, 0x59fd687b, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00030012, 0x06b22492, 0x448c9f49, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x01e00000, 0xf00e0000, 0x31bba6f7, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000007ff, 0x0000fff4, 0x025a9815, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00001ffc, 0x0002ffe5, 0x4ac0b643, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x7e003ff0, 0xfc017fe0, 0x086f9ee1, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x01720150, 0x5ca35416, 0x5ca35416, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x03f303f0, 0xfceefc01, 0xd5e8b646, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0000007f, 0x00187fff, 0x18318df8, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000001, 0x3ffc7fff, 0xaece87fe, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x07f807fe, 0xff0effdd, 0x38b51875, 0x0, 0x0 - dspck_dstio shrlv.ph, 0xfd7f3333, 0xfd7f3333, 0x89feb4d0, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00ff07ff, 0x0ffe7fff, 0x8003d454, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000f0007, 0xfffd7ffa, 0x5b427c2c, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xab0ee5b0, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0008000f, 0x8005ffff, 0x13be73ac, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000001, 0x1ffc7fff, 0xb05e134e, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000020, 0x00008000, 0x51ecdcaa, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00ff0000, 0x7fff0000, 0x58d7fab7, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000f000f, 0xfff6ffff, 0xc4d9c01c, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x0b813c8a, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000078, 0x000bf007, 0x401a8529, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0008000c, 0x8000c853, 0x389594dc, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x07ff0800, 0x7fff8000, 0x13e88bf4, 0x0, 0x0 - dspck_dstio shrlv.ph, 0xfff51fe0, 0xfff51fe0, 0x00000000, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00e00000, 0xe0010000, 0xe9cc1168, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x01000000, 0x80000000, 0x380e6e67, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000f0010, 0x7fff8000, 0x0315280b, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x020003ff, 0x8000fffd, 0x0c532bb6, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x15290b12, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x003300da, 0x066e1b59, 0xb482d2d5, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x003f001f, 0xff897fff, 0x62064a7a, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x03fe0006, 0xfcfd57fe, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000004, 0xd3fe9f73, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x309a1fc6, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0003007d, 0x07fcfb58, 0xcbab8f29, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x001d0011, 0x0758046f, 0xe1bf1846, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000003, 0x3fc0e00f, 0x395a470e, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x03fef007, 0x03fef007, 0x00000000, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xbf14b400, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x11260024, 0x11260024, 0x00000000, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000001, 0x5136fa9f, 0x5136fa9f, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x003f0040, 0x7fff8000, 0xe0e04679, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000100, 0x00018000, 0x6b0ee687, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x007f0000, 0xff8c0004, 0x20a06ac9, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00040000, 0x80000000, 0x90f923bd, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x07ed0000, 0xfdbf0002, 0xf4a97d05, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0ffc3e00, 0x3ff0f801, 0x4844d9e2, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x003f0000, 0x7ffd0000, 0x04ddd8c9, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000001ff, 0x0000ffff, 0xf1dd3c57, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000010, 0x035b801f, 0xa52c2fbb, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xd0be099e, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x07fc0400, 0xff808000, 0x0ddbf085, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000000fc, 0x0000fc36, 0xae6c51c8, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x07ff03ff, 0xfffd7fff, 0x43189025, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x7fff0000, 0xa679b7ff, 0x0, 0x0 - dspck_dstio shrlv.ph, 0xfffcfc09, 0xfffcfc09, 0x00000000, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00010000, 0x3ff01ffc, 0xe10483ad, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0000078e, 0x0002f1de, 0x83c9bed5, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x1fff2000, 0x7fff8000, 0x17e071b2, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000057, 0x0000015d, 0x5b2d1752, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0000e007, 0x0000e007, 0x00000000, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x001f00cc, 0x1fe0cccc, 0x04795338, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00010002, 0x553ab1ae, 0x553ab1ae, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x64484000, 0xc8918000, 0x62fa20e1, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00ff007f, 0xfff07ff9, 0xfc5faa38, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0fff0000, 0xfff10000, 0x1b365e04, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x1fff0fff, 0xfffa7fff, 0xac8b8483, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xb47e2a1a, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00001ff0, 0xd64022ae, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x02000000, 0x80040000, 0x5f307386, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00010000, 0x01880000, 0x4475b3b8, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x001f0000, 0xfffe007f, 0xfc18fe2b, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x07ff0fff, 0x7ffffffc, 0x5944b7c4, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x40003ffd, 0x80007ffb, 0x669ee441, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x3fe91fff, 0xffa47fff, 0x94583a12, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x003f019b, 0x422f026c, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x40007fee, 0x8000ffdc, 0xf91dab61, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000003ff, 0x0001ffe9, 0x554897a6, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x37b91bab, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x012403ff, 0x24927fff, 0xb726d8f5, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00020000, 0x10350763, 0x83b1f64b, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x9487082f, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x01c70003, 0x38e3007f, 0x71bba4b5, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x3fe40090, 0xff910243, 0xbe658982, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0000dde1, 0x0000dde1, 0x00000000, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x7fff0000, 0x55f4898f, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x80000994, 0x80000994, 0x7901da20, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x020001ff, 0x80007fff, 0xc4c25336, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000003ff, 0x0020fffd, 0xa7d861f6, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x4c29ed09, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000004, 0x01e18000, 0x2ce1bb0d, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x4f17250a, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000001fe, 0x0006ff3d, 0x3948b837, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000010, 0x00008003, 0x152f5f7b, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x07ff1fff, 0x1ffe7fff, 0x5fa8e602, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000103ff, 0x00277ff9, 0x4c2af275, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x003f0015, 0xffff5555, 0x3460057a, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000001, 0x00007fff, 0x0e7615de, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x007f0000, 0x7ff80000, 0x2c0f8e08, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000020, 0x00008000, 0x97f23f7a, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00010003, 0x3ffc7fff, 0xedb171cd, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x467096da, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00141f67, 0x00a1fb3a, 0xa78af053, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0e7b0c00, 0xe7b9c003, 0xd30ef944, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00003c01, 0x0000f007, 0x8302e082, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00e00006, 0xe00f06b2, 0xee95bd18, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00ff0000, 0x1ffe0002, 0x13514835, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x1fff0fff, 0xfffd7fff, 0xd54e95d3, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x003f003f, 0xfffefff2, 0xcc87c3fa, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00040295, 0x2c42599b, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00c41fff, 0x03137fff, 0x6104a862, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x6db60000, 0x6db60000, 0x709b11e0, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x003f003f, 0xfff8fff9, 0x545450da, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x007f0002, 0x7fcd7e6d, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00030000, 0x7fff0017, 0x0e08407d, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00030000, 0x33330000, 0xc182ac2c, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00230020, 0x8e388000, 0x30dda44a, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000001, 0x7fffb6db, 0x1b9a83af, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0000000d, 0x0000d967, 0x6d9aaa6c, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x199901e1, 0xcccc0f0f, 0x3a5318a3, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0fe200b6, 0xfe2b0b62, 0xa216cf74, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x001c007f, 0x38e3ff81, 0x4858edf9, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x07fe01cb, 0xc81e90cc, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00010000, 0xfc01014a, 0x30b7f88f, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0003001f, 0x0c887ff8, 0x1f97133a, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x80007fff, 0x80007fff, 0xc9295bb0, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x008000e0, 0x8000e01f, 0xbbbe9e68, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0060007f, 0xc01ffff8, 0xc7cdbda9, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x07fd03ff, 0xffa97fff, 0x3cdb6085, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x007f0000, 0xffc00000, 0xf33401a9, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000001, 0x0000ffef, 0x91a9c83f, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00200000, 0x80000000, 0xcbad4e0a, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x1fff000d, 0x7fff0036, 0x111e2072, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x1c713fee, 0x71c7ffb9, 0x4b998f22, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x020003e0, 0x8000f803, 0xf24f4c36, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000000ff, 0x001fff6b, 0xdaa71b18, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0000003f, 0x0238ffe0, 0x3c15b6fa, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00010001, 0x80008000, 0x7838256f, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000800, 0x00008000, 0xf4ab3504, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x0000004f, 0x6dfdcfbd, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x1ff81ff8, 0x1ff81ff8, 0x74dced40, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00710180, 0x38e3c01f, 0x09804e37, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x05768000, 0x05768000, 0x26707240, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0x49a3e60a, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0000018c, 0x00000632, 0x2fb9cec2, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x2000000d, 0x80030035, 0xabe958c2, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0001001c, 0x0ffee38e, 0xeb2b266b, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000200, 0x00008000, 0xc22b8f96, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00070000, 0xfffc0005, 0x1ae8fc8d, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xf0e98239, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0975000a, 0x0975000a, 0x00000000, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000007, 0x348f0396, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00010003, 0x7fffff7d, 0x198aecce, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0fff0fff, 0x7fff7fff, 0x598e8ed3, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xfdda32a8, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x03f90000, 0xfe6c0002, 0xc8ba2496, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000c07fe, 0x0189ffd2, 0xb6ef89c5, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x1fff2000, 0x7fff8000, 0x52fbcdd2, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x000000f1, 0x77db9978, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x3ff82000, 0xffe08000, 0x142abe02, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x010001ff, 0x8003fffd, 0x8d576df7, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0100001f, 0x80000ffe, 0x5c205077, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x40004000, 0x80008000, 0x6cd7dad1, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00070000, 0xfff8000a, 0x5a20231d, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000007ff, 0x0000fffe, 0x97dc1bc5, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000007ff, 0x0004ffff, 0x5882b3f5, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00ff0000, 0xff80003f, 0x7706d078, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000020, 0x00008000, 0x3db5290a, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000db6, 0x0000db6d, 0xb989b284, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0000001f, 0x0000fff8, 0xa2f67c7b, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x03ff03ff, 0xfffeffff, 0x80fafaf6, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x080007ff, 0x80007fff, 0xeddc0bc4, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0c000f0f, 0xc001f0f0, 0x26fda924, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000001, 0x00008000, 0xfdb7deef, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x040007af, 0x8000f5fd, 0x0c5110f5, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x03e00000, 0xf8010007, 0xdb1bbfa6, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00010002, 0x7fff8000, 0x89b8da4e, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x007f0000, 0xfffe0006, 0xb248ae79, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00030000, 0x7ff800f9, 0xccad0f4d, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00080000, 0x80000000, 0x08bc2f7c, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x001f0010, 0xff008000, 0x0d060f8b, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x008000ff, 0x8000fffd, 0x1101b038, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000001ff, 0x0000ff80, 0x2b8d6dc7, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x007b3ff0, 0x007b3ff0, 0x00000000, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x17f3125e, 0xbf9d92f3, 0xbf9d92f3, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00010001, 0xf803fff4, 0x9347887f, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x07ff0fc2, 0x7ffffc2b, 0x7fd4b604, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x3fff7f9b, 0x7fffff37, 0xd1837a51, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x008c00ce, 0x8c30ce18, 0x8c30ce18, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00010001, 0xffdafdc0, 0x19e15c9f, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x049600fe, 0x92c21fc5, 0x92c21fc5, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000004, 0x00008003, 0x01b37bbd, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000c71, 0x0000c71c, 0x3ab39334, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000f0007, 0xfaff7fff, 0xedf43a8c, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000707ff, 0x00717ffc, 0x1460b684, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00020003, 0x9999c003, 0x2c980d8e, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00001ff4, 0x0000ffa6, 0x7267cb13, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000f0008, 0xf8018005, 0x9ff74a2c, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00010000, 0xf0f07f80, 0x2242505f, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x3fff0003, 0xffff000f, 0xda1c89a2, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000001e0, 0x0008f007, 0x00ae2c77, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x007f01ff, 0x3ffcfff7, 0x8ee68f87, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x08000016, 0x80000166, 0x07499164, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00000000, 0xfc0ee4ec, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0000001f, 0x0000fff0, 0x04b633fb, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000008, 0x00008000, 0x15c0274c, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x7ffd7ffd, 0xfffafffa, 0x7337d061, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00200015, 0x807f5555, 0xdfbea0da, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x400377d2, 0x8006efa4, 0x31220071, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0c710000, 0xc71c000e, 0x9c1ec864, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x001f001f, 0xfca5ffb4, 0x9373ddcb, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x03ff003c, 0xfffe0f36, 0x78d15b96, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00030003, 0xe01ffffe, 0xa4e9f9de, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000000, 0x00007fff, 0xe040783f, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000003, 0x00003ffe, 0xf76b2d5c, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x003f0000, 0xfffe000d, 0x319bb95a, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x000f0008, 0xffff8000, 0xafd2ac4c, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0000007f, 0x00fffffd, 0x9f497189, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00010000, 0x80000000, 0x61e03e6f, 0x0, 0x0 - dspck_dstio shrlv.ph, 0xb6db0000, 0xb6db0000, 0x00000000, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00800000, 0x807f0000, 0x48557c78, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x3fff0000, 0x7fff0000, 0x0e4da731, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00800000, 0x80060001, 0x85f65858, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000f80, 0x0009f801, 0xc3fcd024, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x00000003, 0x0000fffb, 0x5830059e, 0x0, 0x0 - dspck_dstio shrlv.ph, 0x0000000a, 0x00000154, 0xc719a275, 0x0, 0x0 - - writemsg "[35] Test subu.ph" - dspck_dstio subu.ph, 0x0f47f8f0, 0x003700ec, 0xf0f007fc, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x8043fffb, 0x7ffffffb, 0xffbc0000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xff847100, 0xff8b8004, 0x00070f04, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x7f818152, 0x80008000, 0x007ffeae, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x02774000, 0x02753ffe, 0xfffefffe, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x00b6e004, 0x00b50000, 0xffff1ffc, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xffa7f8ee, 0xffe3f8ec, 0x003cfffe, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xffce0ff7, 0xffce0ff8, 0x00000001, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x0003ffc6, 0x0000ffca, 0xfffd0004, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x3fe03ffe, 0x3fe03ffe, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x0076034c, 0x0076034c, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x0001f7c2, 0x8000f801, 0x7fff003f, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x7fff0165, 0x7fff0164, 0x0000ffff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x815d8004, 0x7fff8000, 0xfea2fffc, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xfffc4036, 0x7ff97fc0, 0x7ffd3f8a, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x14dc0001, 0xfffb8000, 0xeb1f7fff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xc0204ccd, 0xc0018000, 0xffe13333, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x3990ce2b, 0x3a89cccc, 0x00f9fea1, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x800301b5, 0x000201b5, 0x7fff0000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x000dfffa, 0xfffefffa, 0xfff10000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x7ff92b49, 0x80000f0f, 0x0007e3c6, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x092b4ccd, 0xcf638000, 0xc6383333, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x8e2f55d5, 0xfff6007f, 0x71c7aaaa, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xffe3ef13, 0xffe3e003, 0x0000f0f0, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x80058000, 0x00000000, 0x7ffb8000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x00000002, 0x00000002, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x08818fff, 0x00010ffe, 0xf7807fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xb33303ae, 0x3333033f, 0x8000ff91, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x00000000, 0x0015c003, 0x0015c003, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x0f7fff00, 0x0ffeff00, 0x007f0000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x87fd0000, 0x07fc0000, 0x7fff0000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x7ff8e869, 0x7ffff003, 0x0007079a, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x0008471d, 0x80078000, 0x7fff38e3, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x800c0003, 0x7ffffffb, 0xfff3fff8, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x8012878e, 0x000c8004, 0x7ffaf876, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x1ffe8000, 0x1ffe8000, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xe38bf6bf, 0xe38efe19, 0x0003075a, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x80017fff, 0x00007fff, 0x7fff0000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xffb1666a, 0xffe70003, 0x00369999, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x0000800f, 0x8000000f, 0x80008000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x106c7fd7, 0x02c97fff, 0xf25d0028, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x7003c004, 0xf0030000, 0x80003ffc, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xfff98000, 0x7ff87fff, 0x7fffffff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x07fe72ff, 0x07fcf33e, 0xfffe803f, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x80018001, 0x00000000, 0x7fff7fff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x0000ff88, 0x7fffff85, 0x7ffffffd, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xc7198021, 0xc71c0020, 0x00037fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xfa9a1c72, 0xfa9ae38e, 0x0000c71c, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00eaffef, 0x0000ffee, 0xff16ffff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x70eb0004, 0x7ffa8004, 0x0f0f8000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0xfff9ff39, 0xfffaff39, 0x00010000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x00000001, 0x00000000, 0x0000ffff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x3ffeffcb, 0x3ffeffcb, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00008001, 0x7fff0000, 0x7fff7fff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x80003f79, 0x7fff3ff8, 0xffff007f, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x3b9dfc01, 0x1bbcfc01, 0xe01f0000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x8038fff5, 0x0037fff1, 0x7ffffffc, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x0046fff3, 0x0000fff6, 0xffba0003, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x7ffffe83, 0xfffffe83, 0x80000000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x7f687ff9, 0xff687fff, 0x80000006, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x10cfafe8, 0x00002fef, 0xef318007, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x8001e38d, 0x0000e38e, 0x7fff0001, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x8075f5ca, 0x00790000, 0x80040a36, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xff55d546, 0xff525555, 0xfffd800f, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x80030fff, 0x7fff0006, 0xfffcf007, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x5b757ffc, 0x80070000, 0x24928004, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xd5508002, 0x55550001, 0x80057fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xfffbfffd, 0x00000000, 0x00050003, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xffff0001, 0xffff8000, 0x00007fff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xc002f839, 0x0000f841, 0x3ffe0008, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xfffc0045, 0x0000003f, 0x0004fffa, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00710001, 0xfffe8000, 0xff8d7fff, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x80088d72, 0x00008e38, 0x7ff800c6, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xfffd0001, 0xfffd8000, 0x00007fff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x0ffb849c, 0x0ffc051b, 0x0001807f, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x80070004, 0x80007fff, 0xfff97ffb, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xfe1e0808, 0xfe1b00c7, 0xfffdf8bf, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xed7cfa6d, 0xedbbfa33, 0x003fffc6, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x00808001, 0x00000000, 0xff807fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xfffd0959, 0x7ffd03fe, 0x8000faa5, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xe0017269, 0xffff9249, 0x1ffe1fe0, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0xb42bffaf, 0xf41bffbd, 0x3ff0000e, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x3fe187af, 0x00007ff0, 0xc01ff841, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x0000ffd8, 0x0000ffd6, 0x0000fffe, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xe0027ff0, 0x0000ffef, 0x1ffe7fff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xf0090000, 0x00050000, 0x0ffc0000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x000d1289, 0x00020359, 0xfff5f0d0, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x80060005, 0x80078004, 0x00017fff, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x00000000, 0x275d7fff, 0x275d7fff, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x7ff5ffc0, 0x80007fff, 0x000b803f, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x7a0b5556, 0xfa0b0000, 0x8000aaaa, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00008002, 0x80008000, 0x8000fffe, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x00000000, 0xc00ffff1, 0xc00ffff1, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x800136db, 0x0000b6db, 0x7fff8000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xfffa0000, 0x1ff88000, 0x1ffe8000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x80010003, 0x00000000, 0x7ffffffd, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x7ffa8002, 0xfff90001, 0x7fff7fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x00000000, 0xffcf0007, 0xffcf0007, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0xffd43fc1, 0x00020000, 0x002ec03f, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x45598000, 0xf0030000, 0xaaaa8000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x8004ff4c, 0x00040000, 0x800000b4, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x36dc8ffc, 0xb6db0ffc, 0x7fff8000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x0000b1a8, 0x00003fe0, 0x00008e38, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xbfc176eb, 0x3fc0b6db, 0x7fff3ff0, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x7ff58e40, 0x80000007, 0x000b71c7, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x00000000, 0x7fff0007, 0x7fff0007, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x8a5d55d5, 0x0a5d007f, 0x8000aaaa, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x80027ff9, 0x00010000, 0x7fff8007, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x7faefffc, 0x80007fff, 0x00528003, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xe0127fff, 0x00028000, 0x1ff00001, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x7ffefef2, 0x7ffe0000, 0x0000010e, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xfc00e980, 0xfc01ffff, 0x0001167f, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00637804, 0x0063f803, 0x00007fff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x554fffe1, 0xfff90000, 0xaaaa001f, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00788008, 0x00000000, 0xff887ff8, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00000000, 0x7fff0000, 0x7fff0000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00087ffb, 0x8000fffa, 0x7ff87fff, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0xfcbe8040, 0x00000045, 0x03428005, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x0006f0f0, 0x0005f0f0, 0xffff0000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x0080e007, 0x0000e007, 0xff800000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x7ffb0406, 0xfffa0007, 0x7ffffc01, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xa4b2ffff, 0x2492ffff, 0x7fe00000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xb8e36010, 0x7fff8000, 0xc71c1ff0, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x005c7fff, 0x03767fff, 0x031a0000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0xfffb2492, 0x00002492, 0x00050000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00000000, 0x71c77fff, 0x71c77fff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x60038000, 0x7fff0000, 0x1ffc8000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x4ac4fe24, 0x0ae3fe25, 0xc01f0001, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x00007ffc, 0x7ffffffc, 0x7fff8000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x80000005, 0x00000007, 0x80000002, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x7ff507fe, 0x7fff0001, 0x000af803, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x7ff9dc91, 0xfff9c01f, 0x8000e38e, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xf73f0082, 0xfa37007d, 0x02f8fffb, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00008381, 0x80008000, 0x8000fc7f, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x03fffff0, 0x0000ffff, 0xfc01000f, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x12518000, 0x92490000, 0x7ff88000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x1fe0ffc9, 0x1fe0ffcc, 0x00000003, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xe0091ffc, 0x00011ffc, 0x1ff80000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x0ff98000, 0xfffc0000, 0xf0038000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x801f4040, 0x800f8000, 0xfff03fc0, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x3fe37fc5, 0x3ff07fff, 0x000d003a, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x7ffb0002, 0xfffb0002, 0x80000000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0xf8fefffa, 0xf8fe7fff, 0x00008005, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x333453d4, 0x0000d3db, 0xcccc8007, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x6658fffe, 0xfff1fffe, 0x99990000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x7ffc8042, 0xfffc0041, 0x80007fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x1f9c81c4, 0xffbb01c3, 0xe01f7fff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x7fa07ff9, 0x7fff8003, 0x005f000a, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x7ffa70f0, 0xfff97fff, 0x7fff0f0f, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x7f4bff03, 0xffcafffa, 0x807f00f7, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00007ffa, 0x00008000, 0x00000006, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x7ffcf884, 0xfffcf884, 0x80000000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x8002fffd, 0x7fff7ffc, 0xfffd7fff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x707203ff, 0xf0720000, 0x8000fc01, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x8000000d, 0x00000000, 0x8000fff3, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x4010f1c5, 0x80007ffd, 0x3ff08e38, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x7ffac003, 0x7ffaffff, 0x00003ffc, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00e0d392, 0x00fff003, 0x001f1c71, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x00008001, 0x80008000, 0x8000ffff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xb6dc8003, 0x00008000, 0x4924fffd, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x800ffff9, 0x000afff9, 0x7ffb0000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xb8e3ffb7, 0x7ffffff6, 0xc71c003f, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x800704de, 0x800704de, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xfff87bd3, 0xfff57fe0, 0xfffd040d, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00018020, 0x8000001f, 0x7fff7fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x7ff9fff8, 0x7ff8fffe, 0xffff0006, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x7fa273cb, 0x7fc0f3cb, 0x001e8000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00000000, 0x15632492, 0x15632492, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x1ff25fc1, 0x1ff83fe0, 0x0006e01f, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x0f13bcf1, 0x00001246, 0xf0ed5555, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x5556fe11, 0x0000fa71, 0xaaaafc60, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xc0070a19, 0xc007006d, 0x0000f654, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x80023fe4, 0x80003fe0, 0xfffefffc, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x7ffd7fae, 0xffffffad, 0x80027fff, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0xfffa7c02, 0xfffa8000, 0x000003fe, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x4dbaffff, 0xe003ffff, 0x92490000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x062effff, 0x00037fff, 0xf9d58000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xa0017c21, 0x1ffcfc01, 0x7ffb7fe0, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x8024ffff, 0x00237fff, 0x7fff8000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x2000f985, 0x3ff0fc01, 0x1ff0027c, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x7d7683ff, 0xfd6f03fe, 0x7ff97fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xd556e351, 0x5555e38e, 0x7fff003d, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x8163cccc, 0x0163cccc, 0x80000000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xff99ffde, 0xff8afffb, 0xfff1001d, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xfdd93ff5, 0x00001ffc, 0x0227e007, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x0000dffa, 0x00001ff8, 0x00003ffe, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x07fba413, 0xfffc7f80, 0xf801db6d, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x8ffcb9ba, 0x8003aaaa, 0xf007f0f0, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x7ff39ffc, 0xfff27fff, 0x7fffe003, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xfffa0f0f, 0xfffa0f0f, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00e6fffe, 0x00000000, 0xff1a0002, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x07ff01c1, 0x07feffe0, 0xfffffe1f, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xf0038006, 0xf0037fff, 0x0000fff9, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xfffce020, 0x00000000, 0x00041fe0, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x00058001, 0x7fff0000, 0x7ffa7fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x3ff1ff83, 0x0000ff82, 0xc00fffff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xff748001, 0xfff30000, 0x007f7fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x0248fffe, 0x0248fffe, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x0f0fdb31, 0xffffdb6d, 0xf0f0003c, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0xc00f8003, 0xc00f8003, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0xe2afc022, 0xfffbc01f, 0x1d4cfffd, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00000000, 0x7ffb8000, 0x7ffb8000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x3ff88005, 0x3ff80000, 0x00007ffb, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x49480ffc, 0x49240ffc, 0xffdc0000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xff817fd2, 0x8000ffd1, 0x807f7fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x796c8086, 0xf96b807f, 0x7ffffff9, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0xf8018001, 0xf8010000, 0x00007fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xdff6fc38, 0xe00f0000, 0x001903c8, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x8020065a, 0x8000ff39, 0xffe0f8df, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x803f0f78, 0x003f07fc, 0x8000f884, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0xdb6e0003, 0x00000000, 0x2492fffd, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x0ff00029, 0x0ff00029, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0xfa747fb8, 0x001cffb7, 0x05a87fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x9ff67ff4, 0x7ff9fff4, 0xe0038000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x7ff30000, 0x7fff7fff, 0x000c7fff, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x1fbd8000, 0xffc08000, 0xe0030000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x00000e12, 0x00000e12, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x7f8a8001, 0x80000000, 0x00767fff, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x80231ffc, 0x00231ffc, 0x80000000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x81bffd18, 0x01bf003f, 0x80000327, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x8f0f333d, 0x7fff0009, 0xf0f0cccc, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x0070802a, 0x00728003, 0x0002ffd9, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x40020001, 0x3ffe8000, 0xfffc7fff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x0000f803, 0x0000f803, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0xffee0001, 0xfffe8000, 0x00107fff, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x9249801b, 0x92490017, 0x00007ffc, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x7ffb0e0f, 0x7fff0000, 0x0004f1f1, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x81210f0f, 0x01210f0f, 0x80000000, 0x00000000, 0x00100000 - dspck_dstio subu.ph, 0x8001f989, 0x8000f989, 0xffff0000, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x87ff7fb3, 0x07fefff2, 0x7fff803f, 0x00100000, 0x00100000 - dspck_dstio subu.ph, 0x60078005, 0xe007fffd, 0x80007ff8, 0x00000000, 0x00000000 - dspck_dstio subu.ph, 0x87fea534, 0x7fff2534, 0xf8018000, 0x00100000, 0x00100000 - - writemsg "[36] Test subu_s.ph" - dspck_dstio subu_s.ph, 0x4008019c, 0x8000019c, 0x3ff80000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00007f50, 0x00008000, 0x000100b0, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x7fedaaaa, 0xffe6ffff, 0x7ff95555, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000981, 0x0019fffa, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x60010000, 0xe003f3f1, 0x8002ffff, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x71330023, 0x7f800023, 0x0e4d0000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x7ffe8000, 0x80008000, 0x00020000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7fabf071, 0x7fffff80, 0x00540f0f, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000010f, 0x0001010f, 0xffe30000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7fff8003, 0x7ffffffd, 0x00007ffa, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x0000403f, 0x7fc0c03f, 0xfffc8000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x1cdf1ff8, 0x7fff7fff, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x471d01fd, 0x8000fffe, 0x38e3fe01, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x3ff00ff8, 0xe0017fc0, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00030031, 0x00050037, 0x00020006, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x0ff90000, 0xfffa0000, 0xf0017ff8, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x807f000f, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000fff7, 0x03fafff9, 0x80030002, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0xda050000, 0xdb6d0000, 0x01680000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x3fff0000, 0x7ffb0103, 0x3ffc9999, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x7c740001, 0x7fff8000, 0x038b7fff, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x1ffe7ffa, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00007fbf, 0x7fc07ffe, 0xf0f0003f, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00007ff9, 0x7ff9fff9, 0x80078000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x7ffd0000, 0x80003ffc, 0x0003fbaa, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xffc70001, 0xffc78000, 0x00007fff, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0xa0030ff8, 0xe0010ff8, 0x3ffe0000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00008b6e, 0x0000fd35, 0x000071c7, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000cde, 0x80018000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000019, 0xff678000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00003ffe, 0x00053ffe, 0xff000000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x3ff90001, 0xfffa8000, 0xc0017fff, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0xdffdd110, 0xfff9e01f, 0x1ffc0f0f, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7ffc0000, 0xfffc0245, 0x8000ffc5, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000008, 0x0000ffe8, 0x3ffeffe0, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000e38e, 0x7ffcffff, 0x807f1c71, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x0000fbdf, 0x8000fffc, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x0006fbc8, 0x8005fffc, 0x7fff0434, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000f801, 0x0000f801, 0x80000000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x06fd18e5, 0x070338e3, 0x00061ffe, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x800001ce, 0x80008000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x000721a9, 0xfed1b6db, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7fff0000, 0x7fff0000, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x49238000, 0x4924ffff, 0x00017fff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00007ffb, 0x66668000, 0xe0070005, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0xffbaf752, 0xfffffffb, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x000000ff, 0xffc08000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x07fc0000, 0x07fc07fc, 0x0000fffe, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00006b3a, 0xf7817fff, 0xfd7a14c5, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00003ff0, 0x07feffff, 0x7fffc00f, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000ffdb, 0x7fffffdb, 0x803f0000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00007fff, 0x0028fe2a, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x2fe40000, 0xf0030005, 0xc01f007f, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xdfa30128, 0xff9b0128, 0x1ff80000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x7ffa0000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x638fc003, 0x8000c003, 0x1c710000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00007fff, 0x00007fff, 0xffc50000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x36dc0000, 0xb6db7fff, 0x7fff7fff, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x00018000, 0x8000fffc, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000ff6b, 0x0000ff6b, 0x80050000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xeeeb0000, 0xeeeb38e3, 0x0000ffdb, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000001, 0x007e8000, 0x1ff87fff, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x0003638e, 0x7fff7fff, 0x7ffc1c71, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x3fe80000, 0xc0070000, 0x801f7fff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x14340000, 0xffff0000, 0xebcbfffe, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xff290000, 0xff2d0000, 0x0004e01f, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x80000005, 0xffff7fff, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x036103fe, 0x03fe03fe, 0x009d0000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x6666f007, 0xfffffffc, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000807f, 0x0000807f, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x00007fff, 0x00008000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x09880000, 0x09888000, 0x00008000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fff0000, 0x80001e0a, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x00050ff8, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00040000, 0x00090000, 0x00058000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x001f0000, 0x801f3ff8, 0x80008000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00001fe0, 0x0ffc8000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xfffc6db6, 0xfffc6db6, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x0001dfe7, 0x8000dfe7, 0x7fff0000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x0e561ffc, 0x0ff8ffff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7fda0000, 0x80000000, 0x002600ad, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00007f00, 0x0000ff00, 0x00008000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00008000, 0x00018000, 0xaaaa0000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x8000c03f, 0x8000f332, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7f840006, 0x80008000, 0x007c7ffa, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xc01f0000, 0xc03f8000, 0x0020f0de, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0xff7a0000, 0xfff8fa66, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xc003002d, 0xc003002d, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x0000ffe8, 0xfffffffe, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x00000ffe, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x6b3d0000, 0x7fff0000, 0x14c20002, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0xffe7003f, 0xffe7003f, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fffe00f, 0xc3dbffff, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x012b0000, 0x012b7fff, 0x0000fff0, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000c76f, 0x8000d504, 0x80000d95, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x744d03b1, 0x7fff03b8, 0x0bb20007, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x7f57e00f, 0x8000e00f, 0x00a90000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x0002002f, 0x001dfffa, 0x001bffcb, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x8e380000, 0x8e388000, 0x0000ffa0, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fff0003, 0x7fff0003, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000001, 0x00000001, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x3dde0000, 0xffff8000, 0xc2218000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00007ff9, 0x007b7fff, 0xdb6d0006, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00008006, 0xffc78006, 0xffff0000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000e7f5, 0x0003e7f6, 0xffd90001, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x19996007, 0x9999e007, 0x80008000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x7ffc8000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x000016c2, 0x0000e38e, 0x7ffbcccc, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7fff0000, 0x7fff0000, 0x00008000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00061a54, 0x00061a54, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000fb7b, 0x07fcfb96, 0x7fff001b, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x03ac003c, 0x1fe00063, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x000036cc, 0x7fc07ff0, 0xfffd4924, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0xff673ffe, 0xffffffff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00007ffd, 0x1e797fff, 0x80000002, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x3f330000, 0xff340004, 0xc001ff80, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x15950000, 0x5555003f, 0x3fc0fc01, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x79dd0000, 0x7ffa03a5, 0x061d2492, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00550000, 0x0e140000, 0x0dbf0000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x00360000, 0x007cfe89, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000000f, 0x0006000f, 0xffc00000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x3ffc0000, 0xff89f003, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0xc0030000, 0xf0077fff, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x7fda7fe4, 0x80007fff, 0x0026001b, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7ffd0000, 0xfffc0000, 0x7fff0000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x000f7ffa, 0x1c71f2c4, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x7fff7fff, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x0ead0000, 0xe38e7fff, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x0000e003, 0x803fffc3, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fff8000, 0xf470ff39, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00017f40, 0x0001ff3f, 0x00007fff, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fff0000, 0xfffef001, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00001fd0, 0x00003fc0, 0x80001ff0, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x03cd0000, 0x03cf003d, 0x0002f001, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7ffd00ff, 0x800000ff, 0x00030000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00024001, 0x8001c001, 0x7fff8000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000006, 0x00008006, 0xffd58000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0xdfe40000, 0xe0030001, 0x001f0380, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fff803f, 0x7fffff76, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00377fff, 0xff007fff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000002, 0x80048002, 0xf0038000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xc001f003, 0xc001f003, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00001963, 0x00003953, 0x80051ff0, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fc027d2, 0x80008005, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fff7fff, 0xff417fff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0xfff8000d, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fe07fff, 0x7ffff803, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0xfcb08004, 0xfcb08004, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x0004fff9, 0xfffefff9, 0xfffa0000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7f1b0000, 0xff1b0007, 0x80008000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x007ffffe, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0xfef8f46d, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00008005, 0x0000fffe, 0xffe07ff9, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x80007ffe, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00001171, 0x0012f172, 0xe003e001, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00006719, 0x00dd7fff, 0x800018e6, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x70018002, 0xf0018002, 0x80000000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xff6a0000, 0xfffb7fff, 0x00918e38, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0xfff9100e, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x08aa0000, 0xe8ad0003, 0xe003ff53, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x7fc00000, 0xffc07fff, 0x80008003, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000789b, 0x00017fff, 0xf49e0764, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x0000fff8, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xfeeb0000, 0xffea8000, 0x00ffe38e, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x80000000, 0x80007fff, 0x00007fff, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0xfffb0000, 0xfffb0ffc, 0x00007fff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xf001efa8, 0xf001efb1, 0x00000009, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x0000003f, 0x00007fff, 0x004f7fc0, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7ffe197a, 0x7ffe7fe0, 0x00006666, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00001ff9, 0x7ffffffc, 0xfffee003, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x000048d1, 0x80004924, 0x80000053, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00090000, 0x8002e01f, 0x7ff9ff80, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xffb9000e, 0xffb9000f, 0x00000001, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x6004df6f, 0xe001e003, 0x7ffd0094, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x70f00000, 0x7fff800f, 0x0f0fffff, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000009, 0x7fff8001, 0xf0037ff8, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7ffd0000, 0x80007ffb, 0x0003803f, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x009403fe, 0x7fff8000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x19000001, 0x19000001, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00006004, 0x00068000, 0x7fc01ffc, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0xfffd8001, 0xfffd8001, 0x00000000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x7ffe7fff, 0x80007fff, 0x00020000, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x3ff60001, 0x3ffc8000, 0x00067fff, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x00030003, 0xfa0d1ff0, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0xc0038000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xfffd0012, 0xfffdfff2, 0x0000ffe0, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xb7240000, 0xf007000d, 0x38e3ffdd, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x124d0000, 0x1ffe8000, 0x0db1aaaa, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x22220000, 0xcccc0000, 0xaaaa0000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fff8000, 0xf30effff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x00548003, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x8000c003, 0x8000c003, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x02a20000, 0xffff8003, 0xfd5dfde3, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x3df40000, 0x3fc0000f, 0x01ccfd82, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x40080000, 0xc0071fe0, 0x7fff8000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00007ff3, 0x2634fff6, 0xffe28003, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00007fff, 0x7ffffff0, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0xfee47f81, 0xff008000, 0x001c007f, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x1ffc0000, 0xf803fff8, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000601f, 0x0ffe7fff, 0xc0071fe0, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x1ffc0002, 0x7ff08000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x80000000, 0x80000000, 0x0000fffe, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x7fff0000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00008000, 0x7fe0ffff, 0xf8037fff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fff38e3, 0x7fff8000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x248c0000, 0xfff98000, 0xdb6d8007, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0xfffe00c2, 0xfffe00c2, 0x00000000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xb6db0000, 0xb6dbe713, 0x0000fffe, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00006008, 0x0000e007, 0x80007fff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x8000c00f, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x8000c007, 0xfffffe44, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x00001ff0, 0x00003ff8, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x1ff082a2, 0x1ff08e38, 0x00000b96, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000eb0f, 0x1ffceb10, 0x1ffc0001, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x0000ffff, 0x0000ffff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00009238, 0x00009249, 0xfe070011, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00007f01, 0x0000ff00, 0x00057fff, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000060, 0x000f007f, 0x8000001f, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x92490000, 0xcafefffc, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x40090003, 0xc0018003, 0x7ff88000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x3ffc7fff, 0xfffbfee3, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fff8000, 0xffeffff1, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x0000f0f0, 0x0000f0f0, 0x00630000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0xc0010004, 0xfe7b8000, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0xdfe2ffcb, 0xe001fff0, 0x001f0025, 0x00000000, 0x00000000 - dspck_dstio subu_s.ph, 0x00000000, 0x00000000, 0x00037ffb, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x7ffa7fff, 0x7ffa7fff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00340000, 0xffeef3a0, 0xffbaffe0, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xfffc7e0f, 0xfffcfd8f, 0x00007f80, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x7fff0000, 0x7fff040e, 0x0000fc42, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x7fff1ff0, 0x7fffdb6d, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0x800fcccc, 0xffd1e007, 0x00000000, 0x00100000 - dspck_dstio subu_s.ph, 0xfde40000, 0xfe1b002d, 0x003707c1, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0xfe100010, 0xffff0010, 0x01ef0000, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00007f18, 0x8000ff17, 0xc00f7fff, 0x00100000, 0x00100000 - dspck_dstio subu_s.ph, 0x00000000, 0xe0018000, 0xffa7fff0, 0x00100000, 0x00100000 - - writemsg "[37] Test subuh.qb" - dspck_dstio subuh.qb, 0x00f97100, 0x012fe3ff, 0x003c00ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x610100a6, 0xc303000c, 0x000000c0, 0x0, 0x0 - dspck_dstio subuh.qb, 0x638b7f01, 0xff15ff03, 0x38ff0000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0081087f, 0x050011ff, 0x05fd0001, 0x0, 0x0 - dspck_dstio subuh.qb, 0x1f7f767f, 0x3effffff, 0x00001200, 0x0, 0x0 - dspck_dstio subuh.qb, 0x810019d5, 0x020237aa, 0xff0205ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0580e57f, 0x0c0002ff, 0x02ff3800, 0x0, 0x0 - dspck_dstio subuh.qb, 0xd9800e03, 0x92001e07, 0xdfff0100, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7f417ffd, 0xfffffff8, 0x007c00fd, 0x0, 0x0 - dspck_dstio subuh.qb, 0x000847fe, 0x00118f14, 0x00010017, 0x0, 0x0 - dspck_dstio subuh.qb, 0xc6f07f1b, 0x0e59ff3c, 0x81790005, 0x0, 0x0 - dspck_dstio subuh.qb, 0x3800c597, 0xefff7e0e, 0x7efff3df, 0x0, 0x0 - dspck_dstio subuh.qb, 0x3ce67f29, 0x7839ff6b, 0x006c0119, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0180f4fe, 0x0200e000, 0x00fff803, 0x0, 0x0 - dspck_dstio subuh.qb, 0x03096182, 0xff20ff04, 0xf80d3cff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7f0dec00, 0xff1a0e00, 0x00003500, 0x0, 0x0 - dspck_dstio subuh.qb, 0x2f2ac993, 0x7e550426, 0x1f0071ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x077f0603, 0x0fff0c06, 0x00000000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x43ff7f00, 0xff00ff00, 0x78010000, 0x0, 0x0 - dspck_dstio subuh.qb, 0xe1ff008e, 0x8f00001b, 0xcc0100fe, 0x0, 0x0 - dspck_dstio subuh.qb, 0x04116af8, 0x0922fff0, 0x00002aff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xe6fc0080, 0x00000000, 0x330700ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x5adf06fe, 0xc71f0c00, 0x13600003, 0x0, 0x0 - dspck_dstio subuh.qb, 0x8310fd11, 0x02ff003d, 0xfcdf051b, 0x0, 0x0 - dspck_dstio subuh.qb, 0xd6fe7500, 0x0500f301, 0x58030901, 0x0, 0x0 - dspck_dstio subuh.qb, 0x054f47c2, 0x0a9fff3b, 0x000170b6, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00185cb9, 0x01ffc300, 0x00cf0b8e, 0x0, 0x0 - dspck_dstio subuh.qb, 0xc1e7dd87, 0x81012b00, 0xff3270f1, 0x0, 0x0 - dspck_dstio subuh.qb, 0x22007fea, 0x5803ff08, 0x13030033, 0x0, 0x0 - dspck_dstio subuh.qb, 0xf4783f8c, 0x01f17f07, 0x180000ef, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7402003f, 0xff050081, 0x17000003, 0x0, 0x0 - dspck_dstio subuh.qb, 0x07fc0400, 0x83011000, 0x75080700, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0080007e, 0xff00fffd, 0xffffff00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7f4f8836, 0xffff0f70, 0x0060ff04, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7fa00019, 0xff3f0033, 0x00ff0000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x78e56400, 0xf003e0ff, 0x003818ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xfe7b6a8e, 0x00fff300, 0x04081fe3, 0x0, 0x0 - dspck_dstio subuh.qb, 0x02fd00ba, 0x7a000074, 0x760600ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x82020b07, 0x0304190e, 0xff000200, 0x0, 0x0 - dspck_dstio subuh.qb, 0x007d5f00, 0x01ffbf01, 0x00040000, 0x0, 0x0 - dspck_dstio subuh.qb, 0xff000011, 0x00000040, 0x0200001d, 0x0, 0x0 - dspck_dstio subuh.qb, 0x37807a82, 0x7300ff03, 0x04ff0aff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x4c06d5fe, 0xf80caa00, 0x5f00ff04, 0x0, 0x0 - dspck_dstio subuh.qb, 0xd13c4181, 0x1e79f301, 0x7c0070ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xd78acdf5, 0x040c0866, 0x55f86d7c, 0x0, 0x0 - dspck_dstio subuh.qb, 0x2c817f82, 0x6601ff03, 0x0eff00fe, 0x0, 0x0 - dspck_dstio subuh.qb, 0x01c70802, 0x03751505, 0x00e70500, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00000000, 0x9fff0000, 0x9fff0000, 0x0, 0x0 - dspck_dstio subuh.qb, 0xc4ff00ff, 0x0f000000, 0x87020002, 0x0, 0x0 - dspck_dstio subuh.qb, 0xe6e307f7, 0x00010e0e, 0x333a001f, 0x0, 0x0 - dspck_dstio subuh.qb, 0x200e90c0, 0x401d0001, 0x0000e080, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7c76071c, 0xf9ff103f, 0x00130106, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00000000, 0x0e0200f1, 0x0e0200f1, 0x0, 0x0 - dspck_dstio subuh.qb, 0xc97db37f, 0x00ff33ff, 0x6d05cc00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x721c7710, 0xff39ff4a, 0x1a01102a, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00000000, 0x080805ff, 0x080805ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x37fc2508, 0x7e00c31f, 0x1007780f, 0x0, 0x0 - dspck_dstio subuh.qb, 0x11803e7d, 0x24007cff, 0x01ff0005, 0x0, 0x0 - dspck_dstio subuh.qb, 0x79f428fc, 0xffcf8103, 0x0ce7300b, 0x0, 0x0 - dspck_dstio subuh.qb, 0xc060c5f7, 0x00c04001, 0x7f00b613, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0002ba00, 0x00050300, 0x00018f00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x3fedca80, 0xff190400, 0x803f70ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x41c1fef9, 0xff0200f1, 0x7c8003ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x9cc4ff80, 0x00000000, 0xc77801ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7f5b607f, 0xffb6c1ff, 0x00000000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x78080002, 0xf1100004, 0x00000000, 0x0, 0x0 - dspck_dstio subuh.qb, 0xc080fe80, 0x00000000, 0x80ff03ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7ef1ebff, 0xfc0b4700, 0x00297002, 0x0, 0x0 - dspck_dstio subuh.qb, 0x9080efab, 0x0000c055, 0xe0ffe1ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0363e603, 0x07c7001c, 0x00003316, 0x0, 0x0 - dspck_dstio subuh.qb, 0x818f0086, 0x01000003, 0xffe100f7, 0x0, 0x0 - dspck_dstio subuh.qb, 0xe64761cc, 0x00ffff01, 0x33713c68, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7ffd4618, 0xff328f30, 0x01370200, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0040efc8, 0xffff148f, 0xff7e35ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xe8607f87, 0xcfc0ff0e, 0xff0000ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xf883e53f, 0x08052a7e, 0x18ff6000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x07bfb583, 0x0e183905, 0x0099cfff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00611f1f, 0x01ff40ff, 0x003c02c1, 0x0, 0x0 - dspck_dstio subuh.qb, 0xa52c00dd, 0x00660007, 0xb60e004d, 0x0, 0x0 - dspck_dstio subuh.qb, 0x3738f5ff, 0x6e7104f0, 0x000019f1, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00f800e6, 0x01000000, 0x000f0033, 0x0, 0x0 - dspck_dstio subuh.qb, 0x9e194f17, 0x2cffff3c, 0xefcc600e, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x86fc8000, 0x00000000, 0xf307ff00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x2da0f1f1, 0x5b1f0000, 0x00df1e1e, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00f07f8d, 0x00e0ff09, 0x00ff01ef, 0x0, 0x0 - dspck_dstio subuh.qb, 0x3ef4ff82, 0x7edffe04, 0x02f7ffff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x96eaf047, 0x2c4d58ff, 0xff787871, 0x0, 0x0 - dspck_dstio subuh.qb, 0xfbfe8182, 0x00010103, 0x0904ffff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0518fee8, 0x0a380f00, 0x00071330, 0x0, 0x0 - dspck_dstio subuh.qb, 0xfb07ffac, 0x00f10018, 0x0ae302bf, 0x0, 0x0 - dspck_dstio subuh.qb, 0x9880c46f, 0x300000e0, 0xffff7801, 0x0, 0x0 - dspck_dstio subuh.qb, 0x5e7f7184, 0xc3fff300, 0x060010f8, 0x0, 0x0 - dspck_dstio subuh.qb, 0xf3803cd5, 0x04007800, 0x1eff0055, 0x0, 0x0 - dspck_dstio subuh.qb, 0x22777921, 0xc1fffd49, 0x7c100a06, 0x0, 0x0 - dspck_dstio subuh.qb, 0x5a01f703, 0xcc033d07, 0x18004f01, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0866f7ff, 0x10ff6d00, 0x00337f02, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00000000, 0xf9030cff, 0xf9030cff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xf0fafa4e, 0xdf0b07fd, 0xff161260, 0x0, 0x0 - dspck_dstio subuh.qb, 0xe5faf003, 0x05f3000e, 0x3aff1f07, 0x0, 0x0 - dspck_dstio subuh.qb, 0xe20080f0, 0x15ff0000, 0x51ffff20, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7f35003e, 0xff710081, 0x00060004, 0x0, 0x0 - dspck_dstio subuh.qb, 0x19901c08, 0x4d003840, 0x1ae0002f, 0x0, 0x0 - dspck_dstio subuh.qb, 0x805b707b, 0x00b6fffc, 0xff001e06, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0c787989, 0x1ef1f302, 0x050000f0, 0x0, 0x0 - dspck_dstio subuh.qb, 0x007f0606, 0x00ff0c0c, 0x00000000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7ff859f7, 0xff00b6cf, 0x000f03e0, 0x0, 0x0 - dspck_dstio subuh.qb, 0x07fd002f, 0x11001f5e, 0x02061f00, 0x0, 0x0 - dspck_dstio subuh.qb, 0xfd8880d0, 0x000f0000, 0x06ffff60, 0x0, 0x0 - dspck_dstio subuh.qb, 0x660100ff, 0xff03ff00, 0x3200ff02, 0x0, 0x0 - dspck_dstio subuh.qb, 0x84cdea80, 0x010b5400, 0xf8717fff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7dbaff81, 0xff35fe02, 0x05c1ffff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00d08f00, 0x00991cff, 0x00f9fdff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xfffb7fff, 0x0005ff00, 0x010e0001, 0x0, 0x0 - dspck_dstio subuh.qb, 0xfc7f3dcc, 0x00fff927, 0x07007f8f, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7ff91d08, 0xff00fd3f, 0x000dc32e, 0x0, 0x0 - dspck_dstio subuh.qb, 0x81af0f8c, 0x01411f18, 0xffe301ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xf2ad0f18, 0xe321554b, 0xffc7371a, 0x0, 0x0 - dspck_dstio subuh.qb, 0xd718fcff, 0x0355f800, 0x5524ff01, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0cdd0341, 0x18040783, 0x00490001, 0x0, 0x0 - dspck_dstio subuh.qb, 0x12004ee1, 0x3c00c001, 0x1800243f, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7e00a633, 0xff0402ff, 0x0203b699, 0x0, 0x0 - dspck_dstio subuh.qb, 0x2c0ff073, 0x991fdfff, 0x4001ff19, 0x0, 0x0 - dspck_dstio subuh.qb, 0x77840073, 0xff00ffe7, 0x10f7ff00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x008000be, 0x00000000, 0x00ff0083, 0x0, 0x0 - dspck_dstio subuh.qb, 0xd5f1f002, 0x00000005, 0x551e2000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x72057b00, 0xfdccf900, 0x18c10300, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7977ff82, 0xf3ff1c03, 0x00101dff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xff7fc8f1, 0x00ff0838, 0x01007855, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0f5f8503, 0x1fc10907, 0x0002ff00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x3c9a00fc, 0x781400f8, 0x00df00ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7c7cfb00, 0xffffc300, 0x0707cc00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7f90c20e, 0xff1f001c, 0x01ff7c00, 0x0, 0x0 - dspck_dstio subuh.qb, 0xd32c00f4, 0x5d780130, 0xb6200047, 0x0, 0x0 - dspck_dstio subuh.qb, 0xe109f05f, 0xc11f60bf, 0xff0c7f00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x38abfe88, 0x71170010, 0x00c103ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7fc635fe, 0xff70bf02, 0x00e35506, 0x0, 0x0 - dspck_dstio subuh.qb, 0xc7ff0ef1, 0x8e02e002, 0xff03c31f, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7847b8fc, 0xf8990038, 0x070b8f3f, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7f004428, 0xffffc055, 0x00ff3805, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0e05e3fe, 0x30110200, 0x13063c03, 0x0, 0x0 - dspck_dstio subuh.qb, 0x1d00f102, 0x78010005, 0x3e001e00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x01ffd780, 0x02020000, 0x000352ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xfe05197d, 0x030a3cff, 0x06000905, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7cc47476, 0xff0cfffc, 0x0783170f, 0x0, 0x0 - dspck_dstio subuh.qb, 0x9f01abdb, 0x01035500, 0xc301ff49, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7a3c4c5f, 0xfff199df, 0x0b790020, 0x0, 0x0 - dspck_dstio subuh.qb, 0x607bf08e, 0xfff90700, 0x3f0226e3, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7c010082, 0xff020003, 0x060000ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x99817f00, 0x0102ff00, 0xcfff0100, 0x0, 0x0 - dspck_dstio subuh.qb, 0x03e8c992, 0xf7cf0224, 0xf0ff70ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xe9798103, 0x02f3013c, 0x3000ff35, 0x0, 0x0 - dspck_dstio subuh.qb, 0xc49aab9e, 0x00000000, 0x78ccaac3, 0x0, 0x0 - dspck_dstio subuh.qb, 0xb2a4804c, 0x584700aa, 0xf3ffff11, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7f803c06, 0xff007c10, 0x00ff0304, 0x0, 0x0 - dspck_dstio subuh.qb, 0x01642d87, 0x03cc5b0e, 0x000401ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x2f7f024c, 0x5fff0699, 0x00010100, 0x0, 0x0 - dspck_dstio subuh.qb, 0x77e200ff, 0xef000101, 0x003c0002, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00000b00, 0x01011700, 0x00000000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7f7ee8c2, 0xffffcf7c, 0x0003fff7, 0x0, 0x0 - dspck_dstio subuh.qb, 0x095f7101, 0x18c0ff03, 0x06011c00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7cf833f4, 0xff0066c7, 0x061000df, 0x0, 0x0 - dspck_dstio subuh.qb, 0xff0f09e2, 0x7f331200, 0x8114003c, 0x0, 0x0 - dspck_dstio subuh.qb, 0x920e77c0, 0x24fff30e, 0xffe3058e, 0x0, 0x0 - dspck_dstio subuh.qb, 0x6f5bfefd, 0xdfb60001, 0x01000406, 0x0, 0x0 - dspck_dstio subuh.qb, 0x8023032c, 0x00b6077e, 0xff700026, 0x0, 0x0 - dspck_dstio subuh.qb, 0x9698009e, 0x2b00ff3c, 0xffcfffff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00e40078, 0x0801fff1, 0x0738ff00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x6dfe0219, 0xfd000432, 0x23030000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x02000678, 0x04ff0cff, 0x00ff000e, 0x0, 0x0 - dspck_dstio subuh.qb, 0x8ff4a2ff, 0x00df0409, 0xe1f7c00b, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00ec00ae, 0x00180040, 0x003f00e3, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0063b8f9, 0x01ff0206, 0x00389213, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00fc809b, 0x00010035, 0x0009ffff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xe6fec900, 0xcc009202, 0xff03ff01, 0x0, 0x0 - dspck_dstio subuh.qb, 0x837f9d78, 0x06ff01ff, 0xff01c70f, 0x0, 0x0 - dspck_dstio subuh.qb, 0xecab0400, 0x15550800, 0x3cff0000, 0x0, 0x0 - dspck_dstio subuh.qb, 0xea810212, 0x10000624, 0x3cfe0100, 0x0, 0x0 - dspck_dstio subuh.qb, 0x1f430769, 0xff878fff, 0xc101812d, 0x0, 0x0 - dspck_dstio subuh.qb, 0x828d7f74, 0x0318ffff, 0xfffe0117, 0x0, 0x0 - dspck_dstio subuh.qb, 0x007bf8ff, 0x01fff003, 0x0109ff04, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00a6fb03, 0x01190608, 0x01cc0f01, 0x0, 0x0 - dspck_dstio subuh.qb, 0x8f8208f3, 0x1e011402, 0xfffc031c, 0x0, 0x0 - dspck_dstio subuh.qb, 0x3efa807f, 0x7e0100ff, 0x010cff01, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00f503f1, 0x000e0fdf, 0x002409fd, 0x0, 0x0 - dspck_dstio subuh.qb, 0x8aed2066, 0x053e41ff, 0xf0630033, 0x0, 0x0 - dspck_dstio subuh.qb, 0x80018100, 0x00030101, 0xff00ff00, 0x0, 0x0 - dspck_dstio subuh.qb, 0xd0490087, 0x1f92000e, 0x7f0000ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x6f7f7f00, 0xdfffff00, 0x01000000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x960000e8, 0x1dff0001, 0xf1ff0030, 0x0, 0x0 - dspck_dstio subuh.qb, 0xffede781, 0x00194c01, 0x023e7eff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00000000, 0x1c0101ff, 0x1c0101ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x61012b49, 0xc30256ff, 0x0000006c, 0x0, 0x0 - dspck_dstio subuh.qb, 0x40247fee, 0x81ffff00, 0x00b60024, 0x0, 0x0 - dspck_dstio subuh.qb, 0xc018a743, 0x07f015ff, 0x87c0c778, 0x0, 0x0 - dspck_dstio subuh.qb, 0x6d08700a, 0xdb10e115, 0x00000000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x54e094fc, 0xfd811c00, 0x55c1f308, 0x0, 0x0 - dspck_dstio subuh.qb, 0xf2ff80fc, 0x00000006, 0x1c01ff0d, 0x0, 0x0 - dspck_dstio subuh.qb, 0x37810001, 0x70010005, 0x01ff0002, 0x0, 0x0 - dspck_dstio subuh.qb, 0x40703cfe, 0x81ff7800, 0x001f0004, 0x0, 0x0 - dspck_dstio subuh.qb, 0x3300ff11, 0xc7ff0060, 0x60ff013e, 0x0, 0x0 - dspck_dstio subuh.qb, 0xa97f0800, 0x51ff1400, 0xff010300, 0x0, 0x0 - dspck_dstio subuh.qb, 0x06908110, 0x0e2002ff, 0x02ffffdf, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0ed5fe81, 0x1c000001, 0x005503ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7d414300, 0xff8effff, 0x050c78ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x079f3337, 0x0e3dff7f, 0x00ff9910, 0x0, 0x0 - dspck_dstio subuh.qb, 0x4701005f, 0x8f0301bf, 0x00000000, 0x0, 0x0 - dspck_dstio subuh.qb, 0xfe4f301f, 0x009f9fff, 0x03003ec1, 0x0, 0x0 - dspck_dstio subuh.qb, 0x369fd185, 0x70022408, 0x03c381fe, 0x0, 0x0 - dspck_dstio subuh.qb, 0x07ff80ff, 0xff070000, 0xf009ff01, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x87f6001e, 0x0e00ffff, 0xff14ffc3, 0x0, 0x0 - dspck_dstio subuh.qb, 0xee8078e4, 0x0c00ff07, 0x2fff0f3f, 0x0, 0x0 - dspck_dstio subuh.qb, 0xb0039a00, 0x002601ff, 0x9f1fccff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x1e7b3682, 0x3df9ff03, 0x010392ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0003c70c, 0x00ff8e18, 0x00f9ff00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0eb3ad1c, 0x1d663cfc, 0x00ffe1c3, 0x0, 0x0 - dspck_dstio subuh.qb, 0xa4818f1e, 0x45011e3c, 0xfcffff00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00001917, 0x00003332, 0x00000004, 0x0, 0x0 - dspck_dstio subuh.qb, 0x161f2c35, 0xf9bfb66b, 0xcc805d00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0cff87ff, 0x99000000, 0x8002f101, 0x0, 0x0 - dspck_dstio subuh.qb, 0x8c60b80b, 0x00c0001c, 0xe7008f06, 0x0, 0x0 - dspck_dstio subuh.qb, 0xf4f1497f, 0x3c7192ff, 0x538f0000, 0x0, 0x0 - dspck_dstio subuh.qb, 0xce1b002e, 0x0c3c006a, 0x7006000e, 0x0, 0x0 - dspck_dstio subuh.qb, 0x81ca0088, 0x01020f04, 0xff6d0ef3, 0x0, 0x0 - dspck_dstio subuh.qb, 0x6e8aac81, 0xff132801, 0x23ffcfff, 0x0, 0x0 - dspck_dstio subuh.qb, 0xf2f0f8e4, 0x00000000, 0x1c200f38, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0700007f, 0x0f0000ff, 0x00000000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00ff8207, 0xff00030f, 0xff01ff00, 0x0, 0x0 - dspck_dstio subuh.qb, 0xfea2825b, 0x010403db, 0x05bfff24, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0a473f87, 0x158e7f0e, 0x000000ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x4370419d, 0x87e0ff02, 0x00007cc7, 0x0, 0x0 - dspck_dstio subuh.qb, 0x7f71e7b0, 0xfffd0460, 0x001a36ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00000000, 0x00ff0099, 0x00ff0099, 0x0, 0x0 - dspck_dstio subuh.qb, 0xac7e1f2c, 0x19fc3f58, 0xc1000000, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00e80fef, 0x00cf2b33, 0x00fe0c55, 0x0, 0x0 - dspck_dstio subuh.qb, 0x00000000, 0x0e3fff00, 0x0e3fff00, 0x0, 0x0 - dspck_dstio subuh.qb, 0x817280fe, 0x01ff0000, 0xff1bff03, 0x0, 0x0 - dspck_dstio subuh.qb, 0xd8638166, 0x8fcc01ff, 0xdf05ff33, 0x0, 0x0 - dspck_dstio subuh.qb, 0xf89acb83, 0x08001d06, 0x18cc87ff, 0x0, 0x0 - dspck_dstio subuh.qb, 0x43c99b83, 0x87921103, 0x00ffdbfc, 0x0, 0x0 - dspck_dstio subuh.qb, 0xfe4b0273, 0x02ff3dff, 0x06683818, 0x0, 0x0 - dspck_dstio subuh.qb, 0x0064814b, 0x71cc0199, 0x7103ff03, 0x0, 0x0 - - writemsg "[38] Test subuh_r.qb" - dspck_dstio subuh_r.qb, 0xffea298d, 0x0004b601, 0x023165e7, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0f007e44, 0x40ffff87, 0x22ff0400, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x3a80387f, 0x7fff70ff, 0x0b000001, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0cb90b0f, 0x1c00251d, 0x058f1000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x4a2557c8, 0xc355bf00, 0x300c1270, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x7eff6a83, 0xff00e305, 0x04030fff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00790004, 0x07ff00ff, 0x080e00f8, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x7f807ff9, 0xffffff00, 0x0100010e, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x32250178, 0x7f4a0ef0, 0x1c010c00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x2e7c5a82, 0x64ffff00, 0x08074bfc, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x003e48fd, 0x007eff05, 0x0003700c, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xe1e719f9, 0x00003100, 0x3e33000f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x1e81fc81, 0x3f00f700, 0x04ffffff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x000c0000, 0xffff00ff, 0xffe701ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0be7157f, 0x16003ffe, 0x01321600, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf1a4002e, 0x000a015b, 0x1fc30100, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xff40920d, 0x018e0419, 0x030ee100, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf9621989, 0x00e03f10, 0x0e1c0eff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00020900, 0x00031200, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xc1952699, 0x70086030, 0xefdf14ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x8133891f, 0x00ff013e, 0xff99ef01, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xd082f89a, 0x8f000003, 0xeffd10cf, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xe2e73fcb, 0x0100ff23, 0x3d33818e, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00fd00b9, 0x00000000, 0x0007008e, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xb90066e0, 0x0000ff09, 0x8f013349, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x780d0003, 0xf0190006, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x66e8cec2, 0xffcf0000, 0x33ff657c, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x397deec3, 0xf0ff1b00, 0x7f06407b, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf0a110d6, 0x00012000, 0x20c00055, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x94050432, 0x270e0767, 0xff040003, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf400cd7c, 0x040099f7, 0x1c00ff00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x81b48102, 0x00670003, 0xffffff00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x806ec2b9, 0xffe10100, 0x00067e8f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x70121801, 0xe7239201, 0x07006200, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x15057cf4, 0x2b1fff00, 0x01160819, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x38f164ff, 0x8f00c700, 0x201e0002, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x7c028500, 0xffff0200, 0x07fcf900, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x016e3e07, 0x01db7fff, 0x000003f1, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xfe027d7f, 0x0705ffff, 0x0c020601, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x10f26433, 0x1f01c77c, 0x001d0017, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x7f8278fc, 0xff02fc02, 0x02ff0c0a, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x60910180, 0xc00001ff, 0x00df0000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x73041c01, 0xffff3b04, 0x19f70303, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x02baf30e, 0x0302e3ff, 0x008efde3, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xb17bfe81, 0x41ff0001, 0xe00904ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf4fe87fc, 0xaa190cc3, 0xc31dffcc, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x02001081, 0x0401ff00, 0x0001dfff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xc0f02539, 0x7e048771, 0xff243d00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x930081b9, 0x00000000, 0xdb00ff8f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0978fc92, 0xf8ff001c, 0xe71009f8, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf881cfef, 0x0e000d01, 0x1fff7024, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xff6d0802, 0x00e0102b, 0x02070027, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00f7cb01, 0x00003f03, 0x0113aa01, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x098100f9, 0x2000ff01, 0x0effff10, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x9d800055, 0x38ffffaa, 0xff00ff00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x847fb068, 0x00ff5dfd, 0xf802fe2d, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x280248ac, 0x710d8f16, 0x220900bf, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0111097e, 0x01257cff, 0x00046b04, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xfff7803c, 0x0000ffff, 0x03130087, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x847c302b, 0x00ff6056, 0xf8080000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xd0148000, 0x1028ffff, 0x710000ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x84cb6e00, 0x070ddb00, 0xff780000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x02003840, 0x04006f80, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x338b81ec, 0x66150000, 0x00ffff28, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xd60480fa, 0x01fffff3, 0x55f800ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xc1f83403, 0x0055e310, 0x7f667c0a, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x4300e380, 0x990000ff, 0x14003b00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf6e479bf, 0x00c7fe04, 0x14ff0c87, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00da0007, 0xff7fff0e, 0xffccff00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0400ff0c, 0x07000078, 0x00010360, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x2e7f9b00, 0xe3ff34ff, 0x8702ffff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x02636efc, 0x03c7e305, 0x0001070d, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x3cfd707a, 0x7d00e0ff, 0x0606000c, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00c702ff, 0xff7e031e, 0xfff10021, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x03401a7f, 0x058033ff, 0x00000002, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf11424b7, 0xe18e556d, 0xff660eff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0500a1fd, 0x100000f7, 0x0700bffd, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x800501fa, 0xff0a0300, 0x0000010c, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00000000, 0x0002782a, 0x0002782a, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0100fe33, 0x01000080, 0x0000051a, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x37ca01e9, 0x7c000204, 0x0e6c0032, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x06fd3a3c, 0x6c007583, 0x6107010c, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x01708a73, 0x01df03f8, 0x0000f013, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x52b8f9d2, 0xbf010002, 0x1c920f5f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xe298f7b1, 0xc30ae060, 0xffdbf3ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x88e58211, 0x002f0083, 0xf066fc62, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x85843fe4, 0x0206f9c7, 0xf8ff7cff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xc1b5ce7d, 0x800300ff, 0xff996405, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00000000, 0x00ff2007, 0x00ff2007, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xd17fa0c8, 0x28ff3e1e, 0x8701ff8f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00000000, 0x0f030100, 0x0f030100, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x81810002, 0x0000fff3, 0xffffffef, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x72de6801, 0xe300ff02, 0x00453000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x9ce82ad0, 0x3730559f, 0xff6001ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x04b91888, 0xff038000, 0xf89250f0, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0400001c, 0x07000037, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x81002d16, 0x00ff923e, 0xffff3812, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x797543c5, 0xf1ffc308, 0x00163e7f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x81710188, 0x00e1010e, 0xff0000ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x81000082, 0x01000000, 0xff0000fd, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00000000, 0x13180833, 0x13180833, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x374100c6, 0xfff7ff0a, 0x9275ff7e, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x1f2790b1, 0x7dcf0000, 0x4081e19f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x04fe1900, 0x07f836ff, 0x00fc04ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xc4fffaac, 0x04000138, 0x7c020de0, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x80000106, 0xff00010b, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0080e889, 0x00ff0f10, 0x000040ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xe0b7c107, 0x3f060028, 0x7f997f1b, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x398d41c1, 0x71188102, 0x00ff0081, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x37018480, 0x6d0206ff, 0x0000ff00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x8f0ae8cc, 0x003a0278, 0xe32733e1, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xc250f1f5, 0x83dfe008, 0xff40ff1f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x84847b10, 0x0707ff33, 0xffff0a14, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x017c80ff, 0x1ff7ff00, 0x1e000002, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x052bec05, 0x0bff000a, 0x01aa2900, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x08648000, 0x10c7ff00, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x91298042, 0x2054ff83, 0xff020000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x42308003, 0x8360ff12, 0x0001000d, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x801f0000, 0xff3d0000, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x01045212, 0x0c08bf23, 0x0b011c00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x03ffc106, 0x0500100e, 0x00038f02, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xecf00005, 0x58df000d, 0x80ff0003, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xfe036af0, 0x1be1ffdf, 0x1fdb2bff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0034fc48, 0xff73008f, 0xff0b0800, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0201a268, 0x0d0124df, 0x0a00e110, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x3e390581, 0x7c780900, 0x000600ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x826c8000, 0x02ffff00, 0xfe270000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x5bd6d380, 0xb60125ff, 0x01558000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x1f02390f, 0xfe03802b, 0xc1000e0e, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x690000e4, 0xffffffc7, 0x2effffff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x78816287, 0xff00ff0c, 0x10ff3cff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x6f3fc111, 0xff7e003f, 0x22017f1e, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x610b0407, 0xc116070e, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x80b2d8ff, 0xff638e00, 0x00ffdf03, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xfe7e88f6, 0x02ff0f0a, 0x0703ff1f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x05e8021f, 0x0a18043d, 0x00480000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x9e7a8100, 0x1fff0101, 0xe30bff01, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xfda0ca88, 0x00000000, 0x06c16df1, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xdc7a8080, 0x00ffffff, 0x490c0000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x7cfb79e8, 0xff00f1c7, 0x080b00f7, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x300f0b5e, 0xe73e16ff, 0x87200044, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x07820c7f, 0x0d02ffff, 0x00ffe701, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x375b8511, 0xffb60322, 0x9200f900, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x11ff3702, 0x2502ff03, 0x03049200, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00000000, 0xff0b011c, 0xff0b011c, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x4281d679, 0xff0178fc, 0x7cffcc0b, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x78800702, 0xf0ff0e03, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x02012180, 0x040141ff, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0001018d, 0x0002ff18, 0x0000feff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x7ac004e7, 0xf301080c, 0x0081013f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xa0009f02, 0x3eff0105, 0xffffc301, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xc47eb97a, 0x87ff00f3, 0xff038f00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x4200fe00, 0xff000e00, 0x7c001300, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00ebff81, 0x00550000, 0x008002ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xa102d362, 0x400499e1, 0xff00f31e, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x1c500304, 0x389f0507, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xff998181, 0x00000000, 0x03cfffff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xa26f8031, 0x04dffff3, 0xc1010092, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xe1fc2b80, 0x000755ff, 0x3e100000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf5777e90, 0x19fffd00, 0x2f1101e0, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x83807c87, 0x04ffff0d, 0xff0007ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x010f0ae7, 0x191e1800, 0x18000433, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x030000e2, 0x0e000003, 0x0900003f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xfb0300ed, 0x0a06ff01, 0x1500ff27, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x05007fe5, 0x0a03ff01, 0x00030238, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xb479ff84, 0x66ff0006, 0xff0e03ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x81f4f9ee, 0x0106022e, 0xff1e1152, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x01ffc300, 0x01010000, 0x00037b00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xff00fdfb, 0x00000000, 0x0300070a, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xeef481f8, 0x00000007, 0x2418ff18, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xfdfc807e, 0x7106ffff, 0x780e0003, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x253a7e62, 0xb673ffc3, 0x6d000400, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x76ff78e5, 0xef06ff03, 0x03090f39, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xff1a0300, 0x013306ff, 0x030000ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x897f8158, 0x0aff00b6, 0xf802ff07, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x7cf68131, 0xf7000076, 0x0015ff14, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xfa06e931, 0x132a0af0, 0x201e398e, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x393cc1b0, 0x717c005e, 0x00047eff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0a07401e, 0x140e7f3c, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x78020100, 0xff060100, 0x0f020000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x819d8000, 0x0039ffff, 0xffff00ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf1fce91e, 0x0107013c, 0x20103000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xa02dfdf1, 0x076092e0, 0xc70799ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00000000, 0xefff7107, 0xefff7107, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x3931ec80, 0x717f01ff, 0x001e2a00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x807fb237, 0xffff3f7e, 0x0001db10, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xc2009078, 0x83001ef7, 0xff01ff07, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x70ebe74c, 0xff4600cf, 0x1f713337, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x5f38fb08, 0xc07104ff, 0x03020ef0, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x5f6f0081, 0xbfe10700, 0x010308ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x807ffb88, 0xffff000e, 0x00010aff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0ccf0191, 0x497e0220, 0x32e100ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf93a07c8, 0x00920e0f, 0x0f1f007f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x6020ef82, 0xc03f1b03, 0x00003eff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00e20f81, 0x01006600, 0x013d49ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0e66ff15, 0xfce1002a, 0xe1150300, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xd7d4307f, 0x1f2460ff, 0x717c0002, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x209a6e81, 0x9f33ff00, 0x60ff24ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x805a807d, 0xffc0ffff, 0x000c0006, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0e7e2d10, 0x1efff32e, 0x0303990e, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x39022a89, 0x80035410, 0x0e0000ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x5c460bc1, 0xbf8f1701, 0x0703017f, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0a183f00, 0x16ff7f00, 0x02cf0200, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x92200efa, 0x223f1c00, 0xff00000c, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xfc01b9c0, 0x00010000, 0x08008f80, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x3933d6ac, 0x7166aa57, 0x0000ffff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0f880540, 0x1e0e0b80, 0x00ff0200, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xe93f08fe, 0x00ff2800, 0x2e811805, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x7318380e, 0xe730701c, 0x01000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x6100007f, 0xc10000fe, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x66088071, 0xcc10ffe1, 0x00000000, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xfdd3ad80, 0xf8240fff, 0xff7fb600, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf8008480, 0x0f0000ff, 0x1f00f900, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0ea87906, 0x1c10ff0f, 0x01c10e03, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00558100, 0x00ff00ff, 0x0055ffff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x400f80e8, 0x80ffffcf, 0x00e100ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x009a20fe, 0xff333f05, 0xffff000a, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x967b483f, 0x0fffff99, 0xe30a701c, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x3ea1424e, 0xff00879f, 0x83bf0403, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00000000, 0xff0106aa, 0xff0106aa, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x190100aa, 0x3301ff14, 0x0200ffc0, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x7fc18d28, 0xff811855, 0x02ffff05, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xc0000100, 0x000002ff, 0x810000ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x7c00d49a, 0xf8001833, 0x000070ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x00000000, 0x00b620ff, 0x00b620ff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x815b3ff1, 0x00ffff00, 0xfe49811e, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xdc504993, 0xb69f9200, 0xff0000db, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x046e3b8b, 0x07e07c05, 0x000507ef, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x24351981, 0xc3fc6000, 0x7c922eff, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0070830f, 0x00df041e, 0x0000ff00, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x0f1e3e98, 0x1e3eff2c, 0x010383fc, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x690000f8, 0xe10002e7, 0x0f0103f8, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x5e70128e, 0xc0e02702, 0x050004e7, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xe6bd7bc3, 0x0a78ff7c, 0x3fff09f7, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf2638104, 0xe0ff000b, 0xfc3aff03, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0xf5001802, 0x01003024, 0x18010020, 0x0, 0x0 - dspck_dstio subuh_r.qb, 0x013300f7, 0x01ffff01, 0x0099ff13, 0x0, 0x0 - - writemsg "[39] Test addqh.ph" - dspck_dstio addqh.ph, 0x24914000, 0x49247ffe, 0xffff0003, 0x0, 0x0 - dspck_dstio addqh.ph, 0x499dfffc, 0x7fff7ff9, 0x133b8000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x21effc3c, 0x03fe315c, 0x3fe0c71c, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3fffbf8f, 0x7fff8000, 0x0000ff1f, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc0420001, 0x00050002, 0x807f0000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x07fd0006, 0x0003000d, 0x0ff80000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x00022db6, 0x0004db6d, 0x00007fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffff00f9, 0x8000fff4, 0x7fff01ff, 0x0, 0x0 - dspck_dstio addqh.ph, 0x0000c001, 0x00000000, 0x00008002, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc0030443, 0x8000088a, 0x0007fffc, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf78015e5, 0xf0010bdb, 0xff001ff0, 0x0, 0x0 - dspck_dstio addqh.ph, 0x00031fea, 0x000dffd8, 0xfffa3ffc, 0x0, 0x0 - dspck_dstio addqh.ph, 0x09190ea3, 0xfffafd4a, 0x12381ffc, 0x0, 0x0 - dspck_dstio addqh.ph, 0xefcf3ff3, 0xe01fffe7, 0xff807fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc32d7fff, 0x065a7fff, 0x80007fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0x30033ffd, 0xe007fffc, 0x7fff7fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc7185c71, 0x8e3838e3, 0xfff87fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc6718000, 0x807f8000, 0x0c648000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfc46fffb, 0xf88d0000, 0x0000fff6, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffffdf7d, 0x7fffdb6d, 0x8000e38e, 0x0, 0x0 - dspck_dstio addqh.ph, 0x1fe0fe02, 0x3fc00003, 0x0000fc01, 0x0, 0x0 - dspck_dstio addqh.ph, 0xce38c000, 0x1c710000, 0x80008000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3fffd555, 0x7fffaaaa, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf0033ffc, 0xe0077ff9, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x7ffebcf7, 0x7fff803f, 0x7ffef9af, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf3c0c3fe, 0xe78007fc, 0x00008000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x0000fffb, 0x0000fff6, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x103dffff, 0x007f8000, 0x1ffc7fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0x401cc006, 0x7ffffffd, 0x003a800f, 0x0, 0x0 - dspck_dstio addqh.ph, 0x021e7fff, 0x021e7fff, 0x021e7fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xa2f0d8e7, 0xc5e0b6db, 0x8000faf4, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfff8ce38, 0x001f8000, 0xffd21c71, 0x0, 0x0 - dspck_dstio addqh.ph, 0x03fedb6d, 0x03fedb6d, 0x03fedb6d, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3ffffff8, 0x7ffffff0, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x17f3c71c, 0x3fe00000, 0xf0078e38, 0x0, 0x0 - dspck_dstio addqh.ph, 0xe00200af, 0xfffefffe, 0xc0070161, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf004401d, 0x00027fff, 0xe007003c, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3f960000, 0x7fff0000, 0xff2e0000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x05cff005, 0x0000e001, 0x0b9e0009, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfdd23ffe, 0xffa07fff, 0xfc04fffe, 0x0, 0x0 - dspck_dstio addqh.ph, 0xcd550000, 0xcd550000, 0xcd550000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x0c21f382, 0x0002ff91, 0x1841e774, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfc010dfe, 0xf8031ffc, 0x0000fc01, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3bf02450, 0xf8017fff, 0x7fe0c8a1, 0x0, 0x0 - dspck_dstio addqh.ph, 0x185affd2, 0xf0bc0181, 0x3ff8fe23, 0x0, 0x0 - dspck_dstio addqh.ph, 0x0785bfff, 0x0f0fffff, 0xfffc8000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xec20be41, 0xe00f8000, 0xf832fc82, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc0025fef, 0x00043fe0, 0x80007fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfff73fff, 0xffe07fff, 0x000e0000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc000c007, 0x00008000, 0x8000000f, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc2020e0a, 0x04041c14, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3fff036b, 0x7fff06d7, 0xffff0000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x4e3800a6, 0x1c7102f9, 0x7ffffe53, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfffdf205, 0x000003fc, 0xfffae00f, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf5c8003c, 0xea5d0005, 0x01330074, 0x0, 0x0 - dspck_dstio addqh.ph, 0xb803c002, 0xf0018006, 0x8005ffff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc003c010, 0x00018000, 0x80050020, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3c561c71, 0x38b538e3, 0x3ff80000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x40950e34, 0x7ffffff7, 0x012c1c71, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc0003fff, 0x80000000, 0x00007fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfc2fd75d, 0x001f1c71, 0xf83f9249, 0x0, 0x0 - dspck_dstio addqh.ph, 0x5999022f, 0x7fff0458, 0x33330007, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf3260006, 0xe0010000, 0x064b000c, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffebb878, 0xffd88000, 0xfffef0f0, 0x0, 0x0 - dspck_dstio addqh.ph, 0x8000cccc, 0x80009999, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3ffff031, 0x0000e003, 0x7fff005f, 0x0, 0x0 - dspck_dstio addqh.ph, 0x47470670, 0x7f800000, 0x0f0f0ce0, 0x0, 0x0 - dspck_dstio addqh.ph, 0x0ffeec4a, 0x1ffed8ab, 0xfffeffe9, 0x0, 0x0 - dspck_dstio addqh.ph, 0x03f9ffec, 0x07fcffd9, 0xfff70000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x38e3c924, 0x00000000, 0x71c79249, 0x0, 0x0 - dspck_dstio addqh.ph, 0xeaed0015, 0xaaaa002b, 0x2b300000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf35a407f, 0xe6b47fff, 0x000100ff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf8763511, 0xf0f0fc6c, 0xfffc6db6, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfe2603ff, 0x00000000, 0xfc4c07fe, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc00013b2, 0x00002747, 0x8000001d, 0x0, 0x0 - dspck_dstio addqh.ph, 0x40013ffe, 0x0003fffd, 0x7fff7fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xa38e0921, 0x80009249, 0xc71c7ff9, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfff8bc03, 0x80008003, 0x7ff0f803, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf8463fff, 0xf08d7fff, 0x0000ffff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffe3d907, 0xffc08000, 0x0007320e, 0x0, 0x0 - dspck_dstio addqh.ph, 0x1b6dffff, 0x7fff8000, 0xb6db7fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0x001f3fff, 0x803f7fff, 0x7fff0000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x01003fff, 0xfe020000, 0x03fe7fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf94ee071, 0x0000fffb, 0xf29cc0e7, 0x0, 0x0 - dspck_dstio addqh.ph, 0xff9ec00a, 0xff3c0005, 0x0000800f, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3003fb87, 0xe007f6c8, 0x7fff0046, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffcffe4c, 0xff9efc99, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x4096199c, 0x01343333, 0x7ff80006, 0x0, 0x0 - dspck_dstio addqh.ph, 0xbfff001b, 0xffff0001, 0x80000035, 0x0, 0x0 - dspck_dstio addqh.ph, 0xbffdff0f, 0xfffbfe1f, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfff83fff, 0x7ff00000, 0x80017fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xca63e002, 0x14c7c001, 0x80000004, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffffc020, 0x00000001, 0xfffe803f, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfffc0000, 0xfff80001, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffff0032, 0x7fff0064, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3ffb0000, 0x7ffa0000, 0xfffd0000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xbeb3af32, 0xfd638000, 0x8003de64, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc039fed1, 0x8000fda2, 0x00730000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfe540000, 0x00000000, 0xfca80000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3ffe78e3, 0xfffd71c7, 0x7fff7fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0x7fff07fc, 0x7fff07fc, 0x7fff07fc, 0x0, 0x0 - dspck_dstio addqh.ph, 0x7ff7c016, 0x7fffffed, 0x7ff0803f, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf0b70ff0, 0x00000000, 0xe16f1fe0, 0x0, 0x0 - dspck_dstio addqh.ph, 0x47fe4001, 0x7fff0003, 0x0ffe7fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0x0f85bff1, 0x1f028000, 0x0009ffe3, 0x0, 0x0 - dspck_dstio addqh.ph, 0xdb6dbf80, 0xb6dbff00, 0x00008000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x003f0006, 0x007f000c, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfffd8000, 0x7ffb8000, 0x80008000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xbfdc3fff, 0xffb87fff, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x00020000, 0x00040000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x2636ffa7, 0x7fff000f, 0xcc6eff40, 0x0, 0x0 - dspck_dstio addqh.ph, 0x7fffe003, 0x7fffe003, 0x7fffe003, 0x0, 0x0 - dspck_dstio addqh.ph, 0x402eeccb, 0x005d3ffe, 0x7fff9999, 0x0, 0x0 - dspck_dstio addqh.ph, 0x4033ccce, 0x7ff80003, 0x006f9999, 0x0, 0x0 - dspck_dstio addqh.ph, 0x201f8000, 0xc03f8000, 0x7fff8000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf800fde6, 0x00000000, 0xf001fbcd, 0x0, 0x0 - dspck_dstio addqh.ph, 0x000f26d6, 0x00700db4, 0xffaf3ff8, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf007ee48, 0xe00fe003, 0xfffffc8e, 0x0, 0x0 - dspck_dstio addqh.ph, 0x33f1fff7, 0x71c70003, 0xf61cffeb, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffff02f6, 0xffff02f6, 0xffff02f6, 0x0, 0x0 - dspck_dstio addqh.ph, 0x80000003, 0x80000007, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x7fffdfe0, 0x7fff8000, 0x7fff3fc0, 0x0, 0x0 - dspck_dstio addqh.ph, 0x4001bffe, 0x00038000, 0x7ffffffc, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfffe7ffc, 0xfffe7ffc, 0xfffe7ffc, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffff3ffc, 0xffff7fff, 0xfffffffa, 0x0, 0x0 - dspck_dstio addqh.ph, 0x404144a2, 0x1a1c0946, 0x66667fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffff1be1, 0x7fff3fc0, 0x8000f803, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc003ffff, 0x00068000, 0x80007fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfff2fffc, 0xffe4fff8, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x05f09b6d, 0xfffd8000, 0x0be4b6db, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3ffd2aaa, 0x7fff5555, 0xfffc0000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x022ec3bb, 0x045d0776, 0x00008000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xcb888e38, 0xcb888e38, 0xcb888e38, 0x0, 0x0 - dspck_dstio addqh.ph, 0xe01bc001, 0xc03f8000, 0xfff70002, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3cff1e30, 0x7fff1ff0, 0xfa001c71, 0x0, 0x0 - dspck_dstio addqh.ph, 0x8000c016, 0x8000002c, 0x80008000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf801ffff, 0xfffcffff, 0xf0070000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x47b88000, 0x0ff08000, 0x7f808000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x0000ffff, 0x00000000, 0x0000ffff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xbfff4001, 0xffff0003, 0x80007fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0x1ff7fff9, 0x3fe00001, 0x000ffff2, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf7d207f9, 0xffa2f003, 0xf0031ff0, 0x0, 0x0 - dspck_dstio addqh.ph, 0x018902df, 0x000705b8, 0x030c0006, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf8033d7a, 0xf0077fff, 0x0000faf6, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffbd3ff5, 0xfffcfff2, 0xff7e7ff9, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc000ecbb, 0x8000f5e9, 0x0000e38e, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfff309d7, 0xffe713b0, 0x0000ffff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfd35e2e9, 0xfaa50000, 0xffc5c5d3, 0x0, 0x0 - dspck_dstio addqh.ph, 0xbe00dff8, 0x80003ff0, 0xfc018000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfd45db6d, 0xfa86b6db, 0x00040000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x8002c001, 0x80008000, 0x80050003, 0x0, 0x0 - dspck_dstio addqh.ph, 0xff42d555, 0x00010000, 0xfe84aaaa, 0x0, 0x0 - dspck_dstio addqh.ph, 0x2b463801, 0x7ffff003, 0xd68e7fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0x01243fff, 0x02467fff, 0x00020000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc007e001, 0x800fc003, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfffc0fc8, 0x80001ff8, 0x7ff9ff99, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc0000ff8, 0x00010000, 0x80001ff0, 0x0, 0x0 - dspck_dstio addqh.ph, 0x000a3fff, 0x00000000, 0x00147fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc3ab8003, 0x07578000, 0x80008006, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffdee007, 0xffc0c00f, 0xfffc0000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x2003fffe, 0x7ffffffd, 0xc0070000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x00297fff, 0x01017fff, 0xff517fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0x80000e3d, 0x80001c71, 0x80000009, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3ff25ffe, 0x7fff3ffe, 0xffe57fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf678dff0, 0xf0f0ffe0, 0xfc01c001, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfffffffd, 0xfffffffd, 0xfffffffd, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf801f1c7, 0xf0030000, 0x0000e38e, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc000fff0, 0x00000000, 0x8000ffe0, 0x0, 0x0 - dspck_dstio addqh.ph, 0x80007fff, 0x80007fff, 0x80007fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfff6200f, 0xffec7fff, 0x0000c01f, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf1c7ffff, 0x00000000, 0xe38efffe, 0x0, 0x0 - dspck_dstio addqh.ph, 0x0517ffaa, 0x0000ff16, 0x0a2e003f, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf00f41bd, 0xe01f037c, 0x00007fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3ffe0000, 0x7ffd0001, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x0225f80e, 0x0002f007, 0x04480016, 0x0, 0x0 - dspck_dstio addqh.ph, 0xcc510003, 0xff090006, 0x99990000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x1c934005, 0x4924000b, 0xf0037fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xbf98c9da, 0xff3113b4, 0x80008000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xa56bc004, 0xcad48000, 0x80020008, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc00236de, 0x80050006, 0x00006db6, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3ffd004c, 0x7ffffffe, 0xfffb009b, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3e8058e2, 0x7ff071c7, 0xfd103ffe, 0x0, 0x0 - dspck_dstio addqh.ph, 0x0eedc110, 0xfddd01a1, 0x1ffe807f, 0x0, 0x0 - dspck_dstio addqh.ph, 0xefd70110, 0xffa80220, 0xe0070000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfc15fffe, 0xf840fffc, 0xffeb0000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf879c47b, 0x0003803f, 0xf0f008b7, 0x0, 0x0 - dspck_dstio addqh.ph, 0x08b0ffe0, 0x0db28000, 0x03ae7fc0, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfae70000, 0xf5ce0000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x2aaaff67, 0x0000fcb3, 0x5555021c, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc71effe8, 0x0005fff9, 0x8e38ffd8, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc3fe8000, 0x07fc8000, 0x80008000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x0001ff7f, 0x0002ff00, 0x0000ffff, 0x0, 0x0 - dspck_dstio addqh.ph, 0x1338ffff, 0x3ffcffff, 0xe674ffff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc001fffc, 0x80000000, 0x0002fff8, 0x0, 0x0 - dspck_dstio addqh.ph, 0x00003ff8, 0x0000fff2, 0x00007fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc0150000, 0x002a3ffe, 0x8000c003, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc71c0000, 0xc71c0000, 0xc71c0000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc89d0800, 0x92490004, 0xfef20ffc, 0x0, 0x0 - dspck_dstio addqh.ph, 0xd657c000, 0x02050000, 0xaaaa8000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xe007a00f, 0x0000c01f, 0xc00f8000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x8000fffc, 0x80000000, 0x8000fff8, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc07fc000, 0x80000000, 0x00ff8000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x014dc002, 0x029c8000, 0xfffe0004, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3ff80111, 0x7ff00222, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfff6005e, 0xfff0ffea, 0xfffc00d2, 0x0, 0x0 - dspck_dstio addqh.ph, 0x8000ce13, 0x8000ce13, 0x8000ce13, 0x0, 0x0 - dspck_dstio addqh.ph, 0xb009fffc, 0xe00f7ff8, 0x80048000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x00019555, 0x00008000, 0x0003aaaa, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfbc0bfff, 0xe003fffd, 0x177d8002, 0x0, 0x0 - dspck_dstio addqh.ph, 0xe00f007e, 0xc01f00fc, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf2f18002, 0x05e18004, 0xe0018000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffff0048, 0x7ffffd97, 0x800002f9, 0x0, 0x0 - dspck_dstio addqh.ph, 0xf0102b8c, 0xe0034924, 0x001d0df4, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfff50036, 0x000a0098, 0xffe0ffd5, 0x0, 0x0 - dspck_dstio addqh.ph, 0xff52c001, 0xfeac8000, 0xfff90003, 0x0, 0x0 - dspck_dstio addqh.ph, 0x05fa26e6, 0xe01f3309, 0x2bd61ac4, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc0003fff, 0x80007fff, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x00003fff, 0x00000000, 0x00007fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffdcfc01, 0xffaa0000, 0x000ff803, 0x0, 0x0 - dspck_dstio addqh.ph, 0xfff919d3, 0x00000000, 0xfff233a6, 0x0, 0x0 - dspck_dstio addqh.ph, 0x000101bf, 0x000203fe, 0x0000ff81, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3f933c28, 0xff2e3852, 0x7ff93ffe, 0x0, 0x0 - dspck_dstio addqh.ph, 0x00004786, 0x00000f0f, 0x00007ffd, 0x0, 0x0 - dspck_dstio addqh.ph, 0x80000ffa, 0x8000fffd, 0x80001ff8, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffff3fff, 0x80000000, 0x7fff7fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc0bb200f, 0x0157c01f, 0x801f7fff, 0x0, 0x0 - dspck_dstio addqh.ph, 0xe79e3fff, 0x24927fff, 0xaaaa0000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x5feff006, 0x3fe0e00f, 0x7ffffffe, 0x0, 0x0 - dspck_dstio addqh.ph, 0xbfff02fd, 0xffffff80, 0x8000067b, 0x0, 0x0 - dspck_dstio addqh.ph, 0x4002fffe, 0x0005fffc, 0x7fff0000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3fa4e081, 0xff49c003, 0x7fff00ff, 0x0, 0x0 - dspck_dstio addqh.ph, 0x3fff0000, 0x7fff0000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc0000002, 0x80000005, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xffeeb88b, 0xffe5e2df, 0xfff88e38, 0x0, 0x0 - dspck_dstio addqh.ph, 0x1f21fffc, 0xfffbfff8, 0x3e480000, 0x0, 0x0 - dspck_dstio addqh.ph, 0xd3d78000, 0x80008000, 0x27af8000, 0x0, 0x0 - dspck_dstio addqh.ph, 0x012cc011, 0x02558000, 0x00030022, 0x0, 0x0 - dspck_dstio addqh.ph, 0x0070c00d, 0x0000fffb, 0x00e0801f, 0x0, 0x0 - dspck_dstio addqh.ph, 0xc0031ffb, 0x00071ffe, 0x80001ff8, 0x0, 0x0 - dspck_dstio addqh.ph, 0x4a96fffe, 0x152d0000, 0x7ffffffc, 0x0, 0x0 - - writemsg "[40] Test addqh_r.ph" - dspck_dstio addqh_r.ph, 0x5feebfff, 0x7ffbfffe, 0x3fe08000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0001060c, 0x00020c18, 0x0000ffff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xf4f5fff9, 0xfffcfff2, 0xe9edffff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xe000391e, 0x80037fc0, 0x3ffcf27b, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3ffcf588, 0x7fffeb10, 0xfff90000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4000f06f, 0x7fff00be, 0x0000e01f, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x40030000, 0x00068000, 0x7fff7fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00a40007, 0x00ff000e, 0x00490000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x135dc000, 0x06c18007, 0x1ff8fff8, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfffd054b, 0xfff90aea, 0x0000ffac, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0004c001, 0x00078002, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xe0020000, 0xc0030000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0005bffa, 0x000f8000, 0xfffbfff4, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3c0040fc, 0xf8017fff, 0x7fff01f9, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x38ed8003, 0x00128000, 0x71c78005, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xffff3fd0, 0xfffd7fc0, 0x0000ffe0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0fedffff, 0xfffe7ffd, 0x1fdc8000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xcb2047fb, 0xc9747ffd, 0xcccc0ff8, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xb0082ffe, 0x8000e001, 0xe00f7ffa, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x088cc526, 0x1117f803, 0x00009249, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc00d4953, 0x80007fff, 0x001a12a6, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x76db3fc0, 0x6db60000, 0x7fff7f80, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xffdfbff3, 0xfffdffe6, 0xffc08000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4ffc000e, 0x7fff001c, 0x1ff80000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xbfe3f7f1, 0xffc6f001, 0x8000ffe0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xffbf1620, 0xfffffdb2, 0xff7e2e8e, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4000bfff, 0x7ffffffe, 0x00008000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3ffefffa, 0xfffde003, 0x7fff1ff0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc0161ff8, 0x80050000, 0x00263ff0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xb333fff4, 0xccccffe9, 0x9999fffe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00002fff, 0xffffe003, 0x00007ffa, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0750400f, 0x0ea37fff, 0xfffc001f, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xffff0000, 0xffff0000, 0xffff0000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x30010c2d, 0xe0031866, 0x7ffffff3, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc000ff4a, 0x8000fe93, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x1f08ffbb, 0x3e140000, 0xfffbff76, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3ffff6d2, 0xffff0000, 0x7fffeda3, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0000eedf, 0x00000000, 0x0000ddbe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x7ff85ffe, 0x7ff07fff, 0x7fff3ffc, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0001000f, 0x0002801f, 0x00007fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc0033d92, 0x8000fb24, 0x00067fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x1ff22ab4, 0x7fe00013, 0xc0035555, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xffff0000, 0xffff0000, 0xffff0000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x078823df, 0x000007fe, 0x0f0f3fc0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x7fff07ff, 0x7fff0ffe, 0x7fff0000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x2691ffff, 0x49248000, 0x03fe7ffd, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x40000007, 0x00000000, 0x7fff000d, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0000c401, 0xffff07fe, 0x00008004, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfcd9ffff, 0xfd46ffff, 0xfc6bffff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xffffff34, 0x3ffcfe69, 0xc001ffff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x7fc00ffe, 0x7fc00ffe, 0x7fc00ffe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x44f338da, 0x7fff6db6, 0x09e603fe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xffafff3a, 0xff5dfe70, 0x00000003, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x1c280ff8, 0xfffd0000, 0x38531ff0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0000c05a, 0x7fff00b3, 0x80008000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0000dff9, 0x7ffffff1, 0x8000c001, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x11c707fe, 0x238d0004, 0x00010ff8, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x2a6b8000, 0xff808000, 0x55558000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xf8e4bfe3, 0x71c7ffc5, 0x80018000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3f4807fb, 0xfe910ff8, 0x7ffffffe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xe279c000, 0xc4f28000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0ffe1fe4, 0x1ffcffd8, 0x00003ff0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0000fffe, 0x80008000, 0x7fff7ffc, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x47ff3ff4, 0x7fff3ff0, 0x0ffe3ff8, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xff310000, 0xff610000, 0xff00ffff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfd700003, 0x00000000, 0xfae00005, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0000fff7, 0x0000ffef, 0x0000ffff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc0010ccc, 0x80009999, 0x00017fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4b5bc08d, 0x16b6803f, 0x7fff00da, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x03a4fff0, 0x03a4fff0, 0x03a4fff0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x1ffc2000, 0x3ff80003, 0x00003ffc, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00203ff0, 0x00000000, 0x003f7fe0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xe00103eb, 0xfffeffff, 0xc00307d6, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x7fff000a, 0x7fff0013, 0x7fff0000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00070032, 0x000a0066, 0x0004fffe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xe008c0be, 0xc00f8000, 0x0000017c, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xffed0a23, 0xffda093f, 0x00000b07, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xffebc000, 0x00000000, 0xffd68000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x400047ee, 0x7fff7fe0, 0x00000ffc, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3fe08000, 0x3fe08000, 0x3fe08000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4000e666, 0x00000000, 0x7fffcccc, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x1d6ffff1, 0xffffffe0, 0x3ade0001, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x1fe0f8e4, 0x3fc08000, 0xffff71c7, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x400cbfd9, 0x7ff9ffaf, 0x001f8003, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x03fde672, 0x07fc0018, 0xfffecccc, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00015ff0, 0x00003fe0, 0x00027fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x000f0001, 0x00060001, 0x00170000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xf1c7407e, 0xe38e7fc0, 0xffff013c, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xf801ffdb, 0x00000000, 0xf001ffb5, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00021ffe, 0x00000000, 0x00033ffc, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0924ffe3, 0x7fffffc0, 0x92490005, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc1bf0000, 0x80007fff, 0x037e8000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x401ac000, 0x7fff8000, 0x00350000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xf800c000, 0xf0010000, 0xfffe8000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x36db3fde, 0x00007fff, 0x6db6ffbd, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xe37dff9c, 0xc00f0000, 0x06ebff38, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x400b0013, 0x00170016, 0x7fff000f, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3ec44ffe, 0xfd8c1ffc, 0x7ffc7fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x07fc0000, 0x0ff80000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xbff80028, 0xffef001c, 0x80000033, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfe5a033c, 0xfcad06b1, 0x0006ffc6, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xffff0003, 0xfffd0000, 0x00000005, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfffe0000, 0xfffc0000, 0x0000ffff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x1fe4c007, 0xffcc8000, 0x3ffc000e, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfffd1d44, 0xffff3fc0, 0xfffafac7, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x7fe0087e, 0x7fc010fc, 0x7fff0000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x02ebffd0, 0x01d8ff9f, 0x03fe0000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00018000, 0x00018000, 0x00008000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x803f004e, 0x803f004e, 0x803f004e, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3ff0bff2, 0x7fe08003, 0x0000ffe1, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x007ffc77, 0x00fff0f0, 0xffff07fe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3ffd4000, 0xfffb0000, 0x7fff7fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x000000fe, 0x000000fe, 0x000000fe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xbfffffd1, 0x8000fff9, 0xfffeffa8, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x40004000, 0x00007fff, 0x7fff0000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc000083f, 0x0000007f, 0x80000ffe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x401f7fff, 0x7fff7fff, 0x003f7fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc0000005, 0x0000ffeb, 0x8000001f, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x001ebf26, 0xfffcfe4c, 0x003f8000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xbfab7fff, 0xff557fff, 0x80007fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3c20c008, 0x7ffa000f, 0xf8458000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x01564ff8, 0x02ad1ff0, 0xffff7fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3ffebfd9, 0xfffd801f, 0x7fffff92, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x47fffffd, 0x0ffefffa, 0x7fff0000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0076bffe, 0x0000fffc, 0x00ec8000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfe8b0000, 0x00000000, 0xfd160000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xffe1c000, 0x00018000, 0xffc0ffff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00003fe0, 0x0000ffc0, 0x00007fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4000ff3a, 0x7fffff73, 0x0000ff00, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3334fff4, 0x0001ffeb, 0x6666fffc, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00914000, 0x031d0000, 0xfe057fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x800001ce, 0x80000000, 0x8000039c, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3ffa4000, 0x7ffc7fff, 0xfff80000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfc01400a, 0xf0030014, 0x07fe7fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4232fce5, 0x7ffff9c9, 0x04650000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0000bffd, 0x8000fffa, 0x7fff8000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xeae70000, 0xd5a90000, 0x00250000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x27df4003, 0x0ffe0006, 0x3fc07fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfffcffae, 0x0000ffff, 0xfff8ff5c, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00031fe0, 0x00050000, 0x00003fc0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfed84000, 0xfdb47fff, 0xfffb0000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x03df0011, 0x07fe0006, 0xffc0001b, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x119afffe, 0x119afffe, 0x119afffe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00002e23, 0x80003333, 0x7fff2913, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xdfe0ffff, 0x3fc0fffe, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xd555c93a, 0x0000002b, 0xaaaa9249, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x73330000, 0x7fff8000, 0x66667fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00002492, 0x00000000, 0x00004924, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3ffd0017, 0x7fff0061, 0xfffaffcd, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfe280000, 0xfc4f8000, 0x00007fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc00c7fff, 0x80027fff, 0x00167fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00008000, 0xffff8000, 0x00018000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x2aa60788, 0x55550000, 0xfff60f0f, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc3fe023c, 0x80000479, 0x07fcffff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4000078b, 0x00000006, 0x7fff0f0f, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xb801402c, 0xf0017fff, 0x80000059, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfffeff7f, 0xfffcfffe, 0x0000ff00, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfe264000, 0x00000000, 0xfc4b7fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0fffbff3, 0x1ffeffe6, 0x00008000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xdfeef01c, 0xff9c0018, 0xc03fe01f, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc000c000, 0x00008000, 0x8000ffff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x7fdc4032, 0x7fc00065, 0x7ff87fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00107fff, 0x00007fff, 0x001f7fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00000004, 0x00050001, 0xfffb0006, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xff7d0032, 0xfeff0006, 0xfffb005d, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x40d1c001, 0x7ff88000, 0x01aa0001, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc000fdf9, 0x0000fc01, 0x8000fff0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x1b9e7fee, 0x375c7fe0, 0xffdf7ffb, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3ff94009, 0x7fff0012, 0xfff27fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x95570814, 0x8004002c, 0xaaaa0ffc, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xbfffee11, 0x8000e001, 0xfffefc21, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xbf0ec1ff, 0xfe1c8000, 0x800003fe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc3923fbb, 0xc0077fff, 0xc71cff77, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x803f7ffa, 0x803f7ffa, 0x803f7ffa, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc0001237, 0x80001c71, 0x000007fc, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xe00441ff, 0x000003fe, 0xc0077fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00003ffc, 0x80007ff8, 0x7fff0000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3fff1fe0, 0xffff0000, 0x7fff3fc0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0000f043, 0x0000007f, 0x0000e007, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00003fc0, 0x00007f80, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x2aa98000, 0xfffd8000, 0x55558000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3ffff860, 0x7fff0000, 0xfffef0bf, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4000c000, 0x7fff8000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xffff0001, 0xfff80001, 0x00060001, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfff91b6b, 0xfff27ffa, 0x0000b6db, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc0000002, 0x00000000, 0x80000004, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xf47af551, 0xf8033ff8, 0xf0f0aaaa, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc925c000, 0x00008000, 0x92490000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xf7f2e561, 0xf00303a6, 0xffe0c71c, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x5c71c000, 0x7fff8000, 0x38e30000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x1fe01265, 0x00000ad3, 0x3fc019f7, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xe7e9c019, 0xc007002b, 0x0fca8006, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4187bea9, 0x7ffffd51, 0x030f8000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x5fe85fff, 0x3fe03ffe, 0x7ff07fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x2491c3fe, 0x492407fc, 0xfffd8000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xf879fff2, 0xf0f00000, 0x0002ffe3, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x40412003, 0x7fffc007, 0x00837fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4003e58a, 0x0006fffe, 0x7fffcb15, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0003fffe, 0x0006fffb, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4fffc36c, 0x7fff803f, 0x1ffe0699, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xcccd0003, 0x99990006, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0002ffff, 0x00000000, 0x0004fffd, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xcccf1d19, 0x00053a31, 0x99990000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xf7ff4007, 0xf0017fff, 0xfffc000f, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xcccd38e4, 0x999971c7, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xb96cefc8, 0xf2d8fc01, 0x8000e38e, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x7fbee008, 0x7ffb0001, 0x7f80c00f, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc0043f90, 0x00087fff, 0x8000ff20, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfb09bfff, 0xf6168002, 0xfffbfffc, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x4003bffd, 0x00078000, 0x7ffffffa, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x43ff0000, 0x07fe7fff, 0x7fff8000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x5ff0fffb, 0x7ffffff9, 0x3fe0fffd, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc002eff9, 0x8000ffeb, 0x0004e007, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc24b8000, 0x80018000, 0x04948000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x76db41ff, 0x6db67fff, 0x7fff03fe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xa0213000, 0x8002e001, 0xc03f7fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x53c05ff8, 0x27817fff, 0x7fff3ff0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xf8041000, 0xf0070001, 0x00001ffe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x020232f3, 0x03feff80, 0x00066666, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xff0efffe, 0xff0efffe, 0xff0efffe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x003efe5f, 0x007f0000, 0xfffcfcbd, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xbff03000, 0xffe07fff, 0x8000e001, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x119d4000, 0x33330000, 0xf0077fff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc0003ff8, 0x80007ff0, 0x0000ffff, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x023102dc, 0x00000000, 0x046205b8, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xfd870924, 0xfff57fff, 0xfb189249, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x07fa000f, 0xfffc001f, 0x0ff8fffe, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xb0ff0000, 0xe1fd0000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x3fff3be1, 0x7ffff801, 0xffff7fc0, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xc007ffe4, 0xc007ffe4, 0xc007ffe4, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xede476db, 0xfbc67fff, 0xe0016db6, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0xbffefe68, 0x8000fffb, 0xfffcfcd5, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0001bffc, 0x00018000, 0x0001fff8, 0x0, 0x0 - dspck_dstio addqh_r.ph, 0x0000ffda, 0xffffffd4, 0x0000ffe0, 0x0, 0x0 - - writemsg "[41] Test subqh.ph" - dspck_dstio subqh.ph, 0xffb9d590, 0xff620075, 0xfff05555, 0x0, 0x0 - dspck_dstio subqh.ph, 0xdb6ec05f, 0xb6db807f, 0xffffffc0, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000000, 0x7fff0000, 0x7fff0000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfc01ffff, 0xf803fffe, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x410507b2, 0x021aff6b, 0x800ff007, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbff9006b, 0x800000d4, 0x000dfffd, 0x0, 0x0 - dspck_dstio subqh.ph, 0xf8040000, 0x00007fff, 0x0ff87fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x1c2cfff8, 0x2db40000, 0xf55b000f, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3ff8a054, 0x7fffc0a8, 0x000f7fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc0003fff, 0x00007fff, 0x7fff0000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfff5eff7, 0xfff1ffec, 0x00061ffe, 0x0, 0x0 - dspck_dstio subqh.ph, 0xff80bff6, 0x0000ffec, 0x00ff7fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfff10000, 0xffe18000, 0xfffe8000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x1000fcb7, 0x3ffeff00, 0x1ffe0591, 0x0, 0x0 - dspck_dstio subqh.ph, 0x002038e4, 0x00000000, 0xffc08e38, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbffd4004, 0xfffa0009, 0x7fff8000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0002ffef, 0x0000ffe0, 0xfffb0001, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0000079a, 0x00000f7d, 0x00000049, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0000c56c, 0x80000ad7, 0x80007fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x07ff3f83, 0x0ffe7fff, 0x000000f9, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbf5f0000, 0x801f0000, 0x01610000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3fb9bbcd, 0xff738000, 0x80000865, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0001f248, 0x0003e487, 0x0000fff7, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc3fffe89, 0x80000000, 0xf80102ed, 0x0, 0x0 - dspck_dstio subqh.ph, 0x7fff31c7, 0x7fffe38e, 0x80008000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x038a01cc, 0x0315ff9a, 0xfc01fc01, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc04643ff, 0x008b07fe, 0x7fff8000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00005ffe, 0x00007fff, 0xffffc003, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3fffc000, 0x7fff8000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x56d70ffe, 0x3ff81ffc, 0x92490000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xffff0001, 0x00000000, 0x0001fffe, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000000, 0xf81f7fff, 0xf81f7fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x35e20000, 0xfe0e0000, 0x92490000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000000, 0x0000fff9, 0x0000fff9, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc000bff9, 0x0000fff1, 0x7fff7fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc001fffa, 0x8002fff4, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x4603fffc, 0x7fff0000, 0xf3f80007, 0x0, 0x0 - dspck_dstio subqh.ph, 0xffff41f5, 0xffff03eb, 0x00008000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x000050ae, 0x80007fff, 0x8000dea2, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfffeff46, 0xfffcfe8d, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x266601ff, 0x7fff0000, 0x3333fc01, 0x0, 0x0 - dspck_dstio subqh.ph, 0xf081c04c, 0x00fa0098, 0x1ff87fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3fe00c4a, 0x7ffffff5, 0x003fe760, 0x0, 0x0 - dspck_dstio subqh.ph, 0x7fffe022, 0x7fffc03f, 0x8000fffa, 0x0, 0x0 - dspck_dstio subqh.ph, 0x47ff3ff8, 0x7fff0000, 0xf001800f, 0x0, 0x0 - dspck_dstio subqh.ph, 0x40d2f007, 0x01a5e00f, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00407fff, 0x00017fff, 0xff808000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x4003ff3a, 0x7fffff1a, 0xfff800a5, 0x0, 0x0 - dspck_dstio subqh.ph, 0xffff0e6f, 0xfffe1cd7, 0x0000fff8, 0x0, 0x0 - dspck_dstio subqh.ph, 0x8002c035, 0x8003006a, 0x7fff7fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x8000bff8, 0x80008000, 0x7fff000f, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbfed0000, 0xffda0000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc0004ffc, 0x80001ff8, 0x00008000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x40030062, 0x7fff00c3, 0xfff9ffff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000010, 0x00000000, 0x0000ffe0, 0x0, 0x0 - dspck_dstio subqh.ph, 0x03fec010, 0x00000000, 0xf8037fe0, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfa8303ff, 0xf5040000, 0xfffef801, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfffdff7c, 0x80000000, 0x80060107, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbf96dc72, 0xff2b8000, 0x7fffc71c, 0x0, 0x0 - dspck_dstio subqh.ph, 0x30070002, 0xe00f0004, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc000e003, 0x8000c007, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0000c925, 0x00000000, 0x00006db6, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000000, 0xfff90000, 0xfff90000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xff15c713, 0xfe378e38, 0x000d0011, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc01fffe0, 0x803f7fc0, 0x00007fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfffefffd, 0xfffd0000, 0x00000006, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3ffbffff, 0xfff7fffe, 0x8000ffff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0ffe00bd, 0x1ffc017a, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0000e669, 0x8000cccc, 0x8000fffa, 0x0, 0x0 - dspck_dstio subqh.ph, 0xffff3fff, 0xfffffffe, 0x00008000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x7ffc39b4, 0x7ff8f369, 0x80008000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xf805c000, 0x00038000, 0x0ff80000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbfff00aa, 0x8000016a, 0x00020015, 0x0, 0x0 - dspck_dstio subqh.ph, 0xebfe0001, 0xdb6d0000, 0x0370fffe, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00002000, 0x00007ff8, 0x00003ff8, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3f7e0040, 0xfefc007f, 0x8000fffe, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3fbf08e1, 0x7f8011c1, 0x0001fffe, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc004dffe, 0x80078000, 0xfffec003, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfe10f010, 0xfc270000, 0x00061fe0, 0x0, 0x0 - dspck_dstio subqh.ph, 0x1ffdfffb, 0xfffe0006, 0xc003000f, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000000, 0xfff60000, 0xfff60000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x40073fff, 0x7fff7fff, 0xfff00000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x07ffc96a, 0x0ffe8001, 0x0000ed2d, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc000f47d, 0x00000000, 0x7fff1706, 0x0, 0x0 - dspck_dstio subqh.ph, 0x005d4000, 0x003b0001, 0xff808000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00cefbfd, 0x005ff803, 0xfec30008, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfffe3fff, 0xfffc7fff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x80000400, 0x800007fe, 0x7ffffffe, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3fffc003, 0x7fff0001, 0x00007ffa, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc0001ff9, 0x00000002, 0x7fffc00f, 0x0, 0x0 - dspck_dstio subqh.ph, 0x407fc002, 0x7fff8000, 0xff00fffc, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000000, 0x001e007f, 0x001e007f, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0e8cc02a, 0x1d1d0045, 0x00057ff0, 0x0, 0x0 - dspck_dstio subqh.ph, 0xffe11213, 0x00042492, 0x0042006b, 0x0, 0x0 - dspck_dstio subqh.ph, 0x8040f02f, 0x807fe01f, 0x7fffffc0, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfef21ff2, 0xffc60024, 0x01e1c03f, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc0033fbf, 0x8000fffe, 0xfffa807f, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0000c000, 0x7fff8000, 0x7fff0000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0801cffe, 0x000a8000, 0xf007e003, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfffcdfd0, 0x3ff0ff80, 0x3ff83fe0, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfff0233b, 0x7fe0e00f, 0x7fff9999, 0x0, 0x0 - dspck_dstio subqh.ph, 0x7fff00b2, 0x7fff016c, 0x80000007, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbfb21ac0, 0x8000f582, 0x009cc001, 0x0, 0x0 - dspck_dstio subqh.ph, 0xddb81066, 0xe0031ffe, 0x2492ff31, 0x0, 0x0 - dspck_dstio subqh.ph, 0x400e2492, 0x7fff4924, 0xffe30000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x8001583e, 0x80017ff8, 0x7fffcf7b, 0x0, 0x0 - dspck_dstio subqh.ph, 0xffee4005, 0x001f000a, 0x00428000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x1ff4c34c, 0x7fe08000, 0x3ff8f967, 0x0, 0x0 - dspck_dstio subqh.ph, 0x1555ffe8, 0x7fffffff, 0x5555002f, 0x0, 0x0 - dspck_dstio subqh.ph, 0x1fdd1ff0, 0x3fc00000, 0x0006c01f, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfbfe8040, 0xfff8807f, 0x07fc7fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc02d7fdf, 0x80007fc0, 0xffa68001, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0139216e, 0x02723fc0, 0x0000fce3, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbfc03eec, 0x80007fff, 0x007f0227, 0x0, 0x0 - dspck_dstio subqh.ph, 0x7fffd556, 0x7fff0002, 0x80005555, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0fa88000, 0x1c718000, 0xfd207fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0xe492c924, 0x8000db6d, 0xb6db4924, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc000c71c, 0x80018e38, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0003300f, 0x00077fff, 0x00001fe0, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3fc0400f, 0xff807fff, 0x8000ffe0, 0x0, 0x0 - dspck_dstio subqh.ph, 0xb005c040, 0xe0030000, 0x7ff87f80, 0x0, 0x0 - dspck_dstio subqh.ph, 0xf165ffdc, 0x000000b6, 0x1d3500fe, 0x0, 0x0 - dspck_dstio subqh.ph, 0xffffd369, 0x00000d39, 0x00016666, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc000401f, 0x0000003f, 0x7fff8000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x38032ff7, 0xf0071ffe, 0x8000c00f, 0x0, 0x0 - dspck_dstio subqh.ph, 0xf1b00074, 0x035e00e8, 0x1ffe0000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xe02004ba, 0x0000097e, 0x3fc00009, 0x0, 0x0 - dspck_dstio subqh.ph, 0x7fffdb6d, 0x7fffb6db, 0x80000001, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfa49ff47, 0x048efe8e, 0x0ffc0000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00038000, 0x7fff8000, 0x7ff87fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0xb1c7e8f3, 0xe38ed1f6, 0x7fff000f, 0x0, 0x0 - dspck_dstio subqh.ph, 0x07883fff, 0x0000fffe, 0xf0f08000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000000, 0xc03f6666, 0xc03f6666, 0x0, 0x0 - dspck_dstio subqh.ph, 0x1d7b0fe7, 0xfffcffd0, 0xc505e001, 0x0, 0x0 - dspck_dstio subqh.ph, 0x39c53ff9, 0x7fff7fff, 0x0c74000d, 0x0, 0x0 - dspck_dstio subqh.ph, 0x36dbff90, 0x6db6ff3f, 0xffff001f, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc71c4000, 0x00000000, 0x71c78000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc000fff0, 0x00008000, 0x7fff801f, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3fc3c7ff, 0x00050ffe, 0x807f7fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0xb002f2d7, 0xe0030001, 0x7fff1a53, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00001800, 0x7fff3ffc, 0x7fff0ffc, 0x0, 0x0 - dspck_dstio subqh.ph, 0x4ff837ae, 0x7fffef5c, 0xe00f8000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xffb2f001, 0xff67fffb, 0x00031ff8, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000001, 0x00000000, 0x0000fffe, 0x0, 0x0 - dspck_dstio subqh.ph, 0x40070000, 0x7ffffffe, 0xfff0fffe, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfffd1fff, 0x00000000, 0x0006c001, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000000, 0x3e278000, 0x3e278000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x401cc001, 0x7ffc0000, 0xffc47ffd, 0x0, 0x0 - dspck_dstio subqh.ph, 0xdd03009b, 0xe01f0143, 0x2619000c, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc0293b91, 0x807ff723, 0x002d8000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x7fffe34e, 0x7fffc71c, 0x8000007f, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc0403fff, 0x80000000, 0xff808001, 0x0, 0x0 - dspck_dstio subqh.ph, 0xf5640921, 0xeac89249, 0x00008006, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3ffe6492, 0xfffd4924, 0x80008000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xdffc0000, 0x3ff80000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3ff7ce39, 0x7fff8000, 0x0011e38e, 0x0, 0x0 - dspck_dstio subqh.ph, 0x4ff0e003, 0x7fffc007, 0xe01f0000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xff1a300d, 0xffff7ffa, 0x01ca1fe0, 0x0, 0x0 - dspck_dstio subqh.ph, 0x8000fc02, 0x80000000, 0x7fff07fc, 0x0, 0x0 - dspck_dstio subqh.ph, 0x004e5fff, 0x009c3ffe, 0x00008000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3ffdbfe2, 0x7ffa8000, 0x0000003b, 0x0, 0x0 - dspck_dstio subqh.ph, 0x4039401c, 0x00727fff, 0x8000ffc7, 0x0, 0x0 - dspck_dstio subqh.ph, 0x5ff80003, 0x7fff0004, 0xc00ffffd, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3fff1ff0, 0xffff3fe0, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00003f61, 0x7ffffec3, 0x7fff8000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0000ffe7, 0x00000000, 0x00000031, 0x0, 0x0 - dspck_dstio subqh.ph, 0xff9b1b6b, 0xff36b6db, 0xffff8004, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfffe4000, 0x00000000, 0x00048000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xffc0fff8, 0x00000000, 0x007f000f, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc001bffb, 0x0001fff5, 0x7fff7fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x004009a1, 0x0001e00f, 0xff80cccc, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbffccffc, 0xfff88000, 0x7fffe007, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0044ff08, 0x0246fe10, 0x01bdffff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x4913f1b5, 0x7ff80000, 0xedd11c95, 0x0, 0x0 - dspck_dstio subqh.ph, 0x07847fff, 0xfff87fff, 0xf0f08000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xf8274000, 0xf0940000, 0x00458000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfe61ddba, 0xfcc0e007, 0xfffe2492, 0x0, 0x0 - dspck_dstio subqh.ph, 0xe6661f87, 0xccccff10, 0xffffc001, 0x0, 0x0 - dspck_dstio subqh.ph, 0x32480394, 0x24920728, 0xc0010000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x04007fff, 0x00017fff, 0xf8018000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfbb8ffff, 0xf5e9fffd, 0xfe79fffe, 0x0, 0x0 - dspck_dstio subqh.ph, 0x1ffec05e, 0x3ffc00bc, 0x00007fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3ffffff3, 0x7fff8006, 0x0000801f, 0x0, 0x0 - dspck_dstio subqh.ph, 0x20070000, 0xc00f0000, 0x8000ffff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x000010fa, 0x000021f5, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000000, 0x8000fe19, 0x8000fe19, 0x0, 0x0 - dspck_dstio subqh.ph, 0x7fff3fff, 0x7fffffff, 0x80008000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x1fab0145, 0x3f57028a, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x20004001, 0x7fff0002, 0x3ffe8000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xff59c000, 0xfeb38001, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbbd31c71, 0x800038e3, 0x085a0000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00013ffd, 0x00000000, 0xfffe8006, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbffa067f, 0xfff4007f, 0x7ffff380, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc0043ffe, 0x0007fffc, 0x7fff8000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfcd9f054, 0xf9badb6d, 0x0008fac4, 0x0, 0x0 - dspck_dstio subqh.ph, 0x4000b008, 0x00008000, 0x80001ff0, 0x0, 0x0 - dspck_dstio subqh.ph, 0xffd40000, 0x00048000, 0x005b8000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x1ff6003d, 0xfff00079, 0xc003fffe, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3fff0000, 0x7fff0000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc00344c6, 0x8000098d, 0xfff98000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xe661c004, 0xcccc0000, 0x000a7ff8, 0x0, 0x0 - dspck_dstio subqh.ph, 0xa02ff4ed, 0xc03fe9db, 0x7fe00000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xf0010000, 0xe0030000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc020b6db, 0x8000db6d, 0xffc06db6, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3feaedb6, 0x7ffadb6d, 0x00260000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00750004, 0x007f0000, 0xff94fff8, 0x0, 0x0 - dspck_dstio subqh.ph, 0x4ffcefbf, 0x7ffffc01, 0xe0071c82, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00003fff, 0x7fff7fff, 0x7fff0000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00000000, 0x01457fff, 0x01457fff, 0x0, 0x0 - dspck_dstio subqh.ph, 0x36b70001, 0xed6f001f, 0x8000001d, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0403c239, 0x07fc8000, 0xfff6fb8d, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfdf9a001, 0xfff08000, 0x03fe3ffe, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbe32d555, 0x8000aaaa, 0x039c0000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3f864008, 0xff0d0010, 0x80008000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00003ffd, 0x00000000, 0x00008006, 0x0, 0x0 - dspck_dstio subqh.ph, 0xe003c000, 0xc0078000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00007fff, 0x7fff7fff, 0x7fff8000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x4fd0f820, 0x7fc0003d, 0xe01f0ffc, 0x0, 0x0 - dspck_dstio subqh.ph, 0x7333fffc, 0x66660000, 0x80000008, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfff7048b, 0xfff50000, 0x0006f6e9, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbf4a4000, 0x80060000, 0x01718000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xbc0301b9, 0x80050006, 0x07fefc93, 0x0, 0x0 - dspck_dstio subqh.ph, 0xff98ffff, 0x00048000, 0x00d38002, 0x0, 0x0 - dspck_dstio subqh.ph, 0x24707fff, 0x0ffc7fff, 0xc71c8001, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc801c001, 0x8004ffff, 0xf0017ffc, 0x0, 0x0 - dspck_dstio subqh.ph, 0xffc4ffbf, 0x0000fffe, 0x0077007f, 0x0, 0x0 - dspck_dstio subqh.ph, 0xc0477fff, 0x007f7fff, 0x7ff08000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x001fb971, 0x803f8000, 0x80000d1d, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0083c011, 0x00098000, 0xff03ffdd, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3ffdf001, 0x7fffe003, 0x00040000, 0x0, 0x0 - dspck_dstio subqh.ph, 0x3ffe1fe0, 0xfffd3fc0, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.ph, 0xfff2d000, 0x00011ffe, 0x001d7ffd, 0x0, 0x0 - dspck_dstio subqh.ph, 0x0e5836e6, 0x003f7fff, 0xe38e1232, 0x0, 0x0 - dspck_dstio subqh.ph, 0x00803330, 0x00ff6666, 0xffff0006, 0x0, 0x0 - - writemsg "[42] Test subqh_r.ph" - dspck_dstio subqh_r.ph, 0xbfe10af9, 0x8000cccc, 0x003fb6db, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc01cffe0, 0x0036ffc0, 0x7fff0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xe01d3010, 0xc03f7fff, 0x00051fe0, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x40002002, 0x0000c003, 0x80008000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xeee1fffe, 0xfdba8000, 0x1ff88005, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x4002c000, 0x00038000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x40004000, 0x7fff7fff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc9250003, 0x0000fff8, 0x6db6fff3, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x43ff1b6e, 0x7fffb6db, 0xf8018000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00010bbb, 0x0000ff00, 0xffffe78a, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00000000, 0xf0030000, 0xf0030000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x4001c004, 0x00028000, 0x8000fff9, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc041feea, 0x807ffdd4, 0xfffd0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf87cfffc, 0x0007fff8, 0x0f0f0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc001003b, 0x80000000, 0xffffff8a, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x4000ffff, 0x7ffffffe, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc0010000, 0x00018000, 0x7fff8000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3ffdc000, 0x00008000, 0x80060001, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfff32b09, 0xffe5d611, 0x00008000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00133fff, 0xfff5fffe, 0xffcf8000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0000ffe1, 0x00008000, 0x0000803f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xd99a3c01, 0x3333f801, 0x7fff8000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0002dfb4, 0x0003c01f, 0x000000b7, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0855c001, 0x07560000, 0xf6ad7fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x4001bff1, 0x7fff8000, 0xfffe001f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0259ffff, 0x2492fffe, 0x1fe00000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x4fffc008, 0x1ffe000e, 0x80007fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc0404080, 0x80007fff, 0xff80ff00, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc008fe03, 0x800ffc01, 0x0000fffb, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x19ae1ff1, 0x33333fe0, 0xffd7fffe, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0001f802, 0x0000fffc, 0xfffe0ff8, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x163ecf4f, 0xfffe8004, 0xd382e167, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x1ff80041, 0x3ff00001, 0x0000ff80, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x11aff017, 0x036ce01f, 0xe00ffff1, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf4fafc17, 0xe9f3fc01, 0x000003d4, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x4000db6d, 0x0000b6db, 0x80000002, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0fac3801, 0x1f557fff, 0xfffe0ffe, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xffff0000, 0xfffc0000, 0xfffe0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x2038bf0f, 0x3ffcfe1c, 0xff8d7fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00012010, 0x0002c01f, 0x00008000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xffc10000, 0xff808000, 0xffff8001, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xbe03fff0, 0xfc01fffb, 0x7ffb001c, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0003011d, 0x0002fc82, 0xfffdfa48, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfb364ffc, 0xf8011ff8, 0x01968000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xbaf74003, 0xf5e57fff, 0x7ff8fffa, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x40001ff1, 0x00000000, 0x8000c01f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0000ebf5, 0x0000fffd, 0x00002813, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xe003f1c7, 0xc007fffe, 0x00021c71, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfc01ffff, 0x0000fffd, 0x07fe0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc2000062, 0x03fefffd, 0x7fffff3a, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xbffd4035, 0xfff8006a, 0x7fff8000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x031f0020, 0x0636ffff, 0xfff9ffc0, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc045bf41, 0x807f8001, 0xfff60180, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0000045a, 0x7fff01f5, 0x7ffff941, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfccef02c, 0x00030050, 0x06671ff8, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x36dccff1, 0x00011fe0, 0x92497fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf009c020, 0x00018000, 0x1ff0ffc0, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xd55900ae, 0x00060004, 0x5555fea8, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xe00a18f7, 0x00043333, 0x3ff00145, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x4040c00f, 0x007f801f, 0x80000002, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x5ffcc018, 0x7fff001f, 0xc0077ff0, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3ffcf018, 0x7fffe01f, 0x0007fff0, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0000f30d, 0x7fffe61a, 0x7fff0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfff90000, 0xfff10000, 0x00000001, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00000000, 0x7fffff71, 0x7fffff71, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x38023fe1, 0x7fff7fc0, 0x0ffcfffe, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xa004f816, 0x80000029, 0x3ff80ffe, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x80010006, 0x8000ffcc, 0x7fffffc0, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xbf4b000b, 0xfe85fffd, 0x7ff0ffe7, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x80010000, 0x80007fff, 0x7fff7fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x7fe00ffd, 0x7fc00ffc, 0x8001f003, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00000000, 0x71c77fff, 0x71c77fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfe33c023, 0xfc6b8000, 0x0005ffbb, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xd812124a, 0xf0030000, 0x3fe0db6d, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfe88b804, 0x00018000, 0x02f10ff8, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc00ec788, 0x80000f0f, 0xffe47fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xcffdbfff, 0x80008001, 0xe0070004, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x31c7407f, 0x7fff7fff, 0x1c71ff02, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfffef1c8, 0xfffb0000, 0xffff1c71, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x08341001, 0x00691ffe, 0xf001fffc, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x436f4000, 0x06de7fff, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x4000fd9b, 0x7fff0000, 0xffff04cb, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00150000, 0x001f7fff, 0xfff57fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x010fc090, 0x02210119, 0x00037ff9, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3fe2f969, 0x7ffff243, 0x003cff71, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xff8dd001, 0x00058003, 0x00ece001, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0071ffc1, 0x00e50001, 0x0004007f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf0100002, 0xe01f0003, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3bfdd03f, 0xf8011ffe, 0x80077f80, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc78b0000, 0x0f0f7ffe, 0x7ff97fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0110c001, 0x00000000, 0xfde17fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xff5f05ff, 0xfbf30ffc, 0xfd3503fe, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x400ff802, 0x0021ffff, 0x80040ffc, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x8003014b, 0x80020064, 0x7ffcfdcf, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3334ffef, 0x0001fffa, 0x9999001d, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0ccda760, 0x9999800f, 0x8000314f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x80000060, 0x7fff003f, 0x8000ff80, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00134000, 0x00057fff, 0xffe00000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x4000c001, 0x00000000, 0x80007fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00000000, 0xfc260a01, 0xfc260a01, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x1ff8a00a, 0xffff800f, 0xc00f3ffc, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x1fe81ff2, 0xffef3fe0, 0xc01ffffc, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x199ad555, 0x0000aaaa, 0xcccc0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf9d878e4, 0x03ac71c7, 0x0ffc8000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc46a0002, 0x08cd8004, 0x7ff98000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xbffe3ffe, 0x80000000, 0x00058005, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc0313ff9, 0x80007fff, 0xff9e000d, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xffefeaab, 0xffdd5555, 0xffff7fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0ec2bfff, 0xfd92fffd, 0xe00f7fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0002fff1, 0xffffffff, 0xfffc001e, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc0038000, 0x80057fff, 0x00008000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc0013ffc, 0x0000fff8, 0x7fff8000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc0234010, 0x0025001f, 0x7fe08000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xbf40bfff, 0x80008000, 0x01800002, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3f800001, 0x7fff0000, 0x00ffffff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0000c001, 0xffff8000, 0x0000ffff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfffcc000, 0x0007ffff, 0x000f7fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfea80000, 0xfd500000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xff802010, 0xff007fff, 0x00003fe0, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xeff5eb71, 0xffe6d6ce, 0x1ffcffec, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x40f2fff9, 0x02230000, 0x803f000f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc0dcf2b3, 0x01b70001, 0x7fff1a9b, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00070000, 0x10090000, 0x0ffc0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf2df8003, 0xe0038000, 0xfa467ffa, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0000f010, 0x7fffe01f, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf8983eb9, 0xf130fd72, 0x00008000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x02b0dffa, 0x0520c003, 0xffc10010, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xdb6e0000, 0x00000000, 0x49240000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3ffc1ef1, 0x7ff03fe0, 0xfff801ff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xff9cc000, 0x00028000, 0x00ca0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc002eda9, 0x8000db6d, 0xfffc001b, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x4788bffd, 0x7fff8000, 0xf0f00007, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf1fbffe1, 0x00660000, 0x1c71003f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3bffdcec, 0x7ffcf2bb, 0x07fe38e3, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x003dfbfd, 0x0003fae4, 0xff8902ea, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x03ff871d, 0x07fe8e38, 0x00007fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x1b6ad805, 0x7ff8c001, 0x49240ff8, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00dd4004, 0x00000007, 0xfe468000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0c5c0200, 0x18b70000, 0x0000fc01, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00004748, 0xffff0f0f, 0x0000807f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0c850000, 0xfc970000, 0xe38e0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0001fff9, 0x00007ff0, 0xfffe7fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0006f001, 0x000ae003, 0xfffe0002, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xe010fe01, 0x00000000, 0x3fe003fe, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x80043fe1, 0x80070000, 0x7fff803f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x1e6ef01d, 0x38e30038, 0xfc081ffe, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xbf81c000, 0xff008000, 0x7fff0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf9013fff, 0xf2017fff, 0x00000002, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00040000, 0x00020000, 0xfffb0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf739c001, 0xfe4a8000, 0x0fd8fffe, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc000ffeb, 0x8000ffd6, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x016fe38f, 0x00000000, 0xfd2338e3, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf5623fed, 0xf36dffe0, 0x08a98007, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0000e390, 0x0000c71c, 0x0000fffc, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0002c000, 0x7fff8000, 0x7ffc0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xb87a1ffb, 0x80033ffe, 0x0f0f0009, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x5ffcff86, 0x3ff80001, 0x800000f6, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfffe47fc, 0x80007fff, 0x8005f007, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00030008, 0x0006000f, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x7ffef7c5, 0x7ffbff80, 0x80000ff7, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf7bc0006, 0x00000000, 0x1089fff5, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x8000ffea, 0x7fffffea, 0x80000016, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xebebc0db, 0xfff901b5, 0x28247fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0000c005, 0x7fff0003, 0x7fff7ff9, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x5fe04000, 0x3fc00000, 0x80008000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf009c002, 0x00010000, 0x1ff07ffc, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0000b39e, 0xffffe73b, 0x00007fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x40004000, 0x7fff7fff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00000000, 0xe01f807f, 0xe01f807f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xbf5c03ff, 0x800007fe, 0x01480000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x871ded35, 0x8e38e01f, 0x7fff05b6, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x01a70033, 0x00d70000, 0xfd89ff9b, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0003c000, 0x0000fffe, 0xfffa7fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xffce3334, 0x00010000, 0x00669999, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfff10020, 0x00007fff, 0x001f7fc0, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x36dfc010, 0x00060000, 0x92497fe0, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00122020, 0x0024c03f, 0x00008000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xff664001, 0xfdcc0001, 0xff008000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0ccdb503, 0x9999ea04, 0x80007fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3ffec012, 0xfffc8007, 0x8000ffe3, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc001bf75, 0x0000807f, 0x7fff0195, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3ffd404d, 0x7ffa0099, 0x00008000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00001009, 0xffff1ff8, 0x0000ffe6, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xbffc3002, 0xfff77fff, 0x7fff1ffc, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xbfc5f003, 0xff88e007, 0x7fff0002, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xb8010000, 0xf001fff8, 0x7ffffff9, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfc0a07bd, 0x0012ff80, 0x07fef007, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xe0001231, 0xc00f0465, 0x000fe003, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xffe3c003, 0xffc48000, 0xfffefffa, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3d660197, 0x7fff0087, 0x0534fd5a, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xbff40820, 0x80000ff8, 0x0019ffb9, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf2b25ffd, 0xe64a7ffd, 0x00e7c003, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x406af00c, 0x00d40008, 0x80001ff0, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00000000, 0x7fff0002, 0x7fff0002, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3f0affec, 0x7fff0001, 0x01ec0029, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x5ffcfffd, 0x3ff80000, 0x80000006, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc0434000, 0x80000000, 0xff7a8000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00003ffe, 0x8000fffb, 0x80008000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0ffbe38e, 0xfff9c71c, 0xe0030000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc1740000, 0x80060000, 0xfd1e0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x46cc1ff7, 0x1fe0fffd, 0x9249c00f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xffe4f164, 0x0000e622, 0x0038035b, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xc00001ff, 0x800003fe, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xdffeff34, 0xc001fff6, 0x0006018e, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x1c72ffb9, 0x0000fff0, 0xc71c007f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x40690fee, 0x7fffffea, 0xff2ee00f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xbfece010, 0xffd7c01f, 0x7fff0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3c021b6e, 0xf803b6db, 0x80008000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00001e31, 0x7ffe1c71, 0x7fffe00f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x40000001, 0x00000000, 0x8000ffff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x01230000, 0x00000000, 0xfdba0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x40004001, 0x7fff0002, 0x00008000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3fe8c402, 0x7fff8004, 0x002ff801, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x80102004, 0x801f7fff, 0x7fff3ff8, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfc27fffe, 0xf853fffc, 0x00060000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x5ffc3ffd, 0x7ffa7fff, 0xc0030006, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf666f327, 0x1ffee64d, 0x33330000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0fc800df, 0xff9701bd, 0xe0070000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00000000, 0x0000ffff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x09234000, 0x92497fff, 0x8003ffff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x40623d6b, 0x7ffffb54, 0xff3c807f, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x0010fbe9, 0x001ff803, 0xffff0032, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x9b6e4000, 0x80000000, 0x49248000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3ffc0000, 0x7ff80000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00770000, 0xfff57fff, 0xff077fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x8002c046, 0x8002000c, 0x7fff7f80, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf61d3f3b, 0x00047fff, 0x13cb018a, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x4fff4017, 0x7fff7fff, 0xe001ffd1, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xffee0000, 0xffd60000, 0xfffa0000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x6a9b0725, 0x7fe00e4c, 0xaaaa0002, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3ffd11ed, 0x7fffff47, 0x0006db6d, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xfffddfff, 0xffffc001, 0x00060004, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xdb6bbfdd, 0xfffa803f, 0x49240086, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf6f3bf06, 0xede6fe0b, 0x00007fff, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x00002d33, 0x00001a66, 0x0000c001, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x2f30c0b2, 0xde608000, 0x8000fe9c, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x1c1f0022, 0x383e0044, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0xf004dc22, 0xe007f83b, 0x00003ff8, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x000000c8, 0x0000007f, 0x0000feef, 0x0, 0x0 - dspck_dstio subqh_r.ph, 0x3940ff95, 0x71c7fffd, 0xff4800d3, 0x0, 0x0 - - writemsg "[43] Test addqh.w" - dspck_dstio addqh.w, 0xff6f3d59, 0x00000000, 0xfede7ab3, 0x0, 0x0 - dspck_dstio addqh.w, 0x0203217d, 0x000642fd, 0x03fffffe, 0x0, 0x0 - dspck_dstio addqh.w, 0x40000001, 0x7fffffff, 0x00000003, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffff48f, 0xffffe920, 0xffffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffffff, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xfff71220, 0xffee1fbf, 0x00000481, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffffffa, 0xfffffffa, 0xfffffffb, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffffffe, 0x00000000, 0xfffffffc, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffffc9d, 0x00000000, 0xfffff93b, 0x0, 0x0 - dspck_dstio addqh.w, 0xbfffffae, 0x80000000, 0xffffff5c, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xbffffdc5, 0x80000000, 0xfffffb8a, 0x0, 0x0 - dspck_dstio addqh.w, 0xfe2cab6a, 0xfc600dbd, 0xfff94917, 0x0, 0x0 - dspck_dstio addqh.w, 0x1ffffff5, 0x3fffffe0, 0x0000000a, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000045, 0x00000082, 0x00000008, 0x0, 0x0 - dspck_dstio addqh.w, 0xf8000001, 0x00000000, 0xf0000003, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x1fffffc7, 0x7fffff80, 0xc000000f, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffffb40, 0x00000000, 0xfffff681, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffffbf, 0x7fffff80, 0xfffffffe, 0x0, 0x0 - dspck_dstio addqh.w, 0xc7ffffff, 0x80000000, 0x0ffffffe, 0x0, 0x0 - dspck_dstio addqh.w, 0x00008065, 0x0000000d, 0x000100be, 0x0, 0x0 - dspck_dstio addqh.w, 0x80000002, 0x80000000, 0x80000004, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000001, 0x0, 0x0 - dspck_dstio addqh.w, 0xf6db6df6, 0x6db6db6d, 0x8000007f, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x0000024e, 0x00000000, 0x0000049d, 0x0, 0x0 - dspck_dstio addqh.w, 0x3ffff2a5, 0x7fffffff, 0xffffe54c, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffffff8, 0x80000000, 0x7ffffff0, 0x0, 0x0 - dspck_dstio addqh.w, 0xc8000002, 0x80000007, 0x0ffffffe, 0x0, 0x0 - dspck_dstio addqh.w, 0x2aaaaaaa, 0x00000000, 0x55555555, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000000, 0x00000001, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xfef8701b, 0x00000000, 0xfdf0e037, 0x0, 0x0 - dspck_dstio addqh.w, 0xbfffde84, 0x8000007f, 0xffffbc89, 0x0, 0x0 - dspck_dstio addqh.w, 0x000001d6, 0x0000068d, 0xfffffd1f, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000003, 0x00000000, 0x00000007, 0x0, 0x0 - dspck_dstio addqh.w, 0x32cb2cb2, 0x1c71c71c, 0x49249249, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000003, 0x00000000, 0x00000007, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffffe0, 0xffffffe0, 0x7fffffe0, 0x0, 0x0 - dspck_dstio addqh.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x3ffffffd, 0xfffffffc, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000002, 0x00000000, 0x00000004, 0x0, 0x0 - dspck_dstio addqh.w, 0x078787a7, 0x0f0f0f0f, 0x0000003f, 0x0, 0x0 - dspck_dstio addqh.w, 0x0009a9ea, 0xffffffff, 0x001353d5, 0x0, 0x0 - dspck_dstio addqh.w, 0x3ffffffc, 0x7fffffff, 0xfffffffa, 0x0, 0x0 - dspck_dstio addqh.w, 0x40000000, 0x7ffffffc, 0x00000004, 0x0, 0x0 - dspck_dstio addqh.w, 0x0a1439fc, 0x009de2c8, 0x138a9131, 0x0, 0x0 - dspck_dstio addqh.w, 0x40000001, 0x00000003, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000004, 0x00000004, 0x00000004, 0x0, 0x0 - dspck_dstio addqh.w, 0x3ffffffc, 0x7ffffffe, 0xfffffffb, 0x0, 0x0 - dspck_dstio addqh.w, 0xedb6db6d, 0xdb6db6db, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xdaee365b, 0xff00ff00, 0xb6db6db6, 0x0, 0x0 - dspck_dstio addqh.w, 0xc00ab1c0, 0x80000007, 0x00156379, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffffff, 0x00000000, 0xffffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xf7fffffe, 0xf0000001, 0xfffffffb, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffffe63, 0x00000000, 0xfffffcc7, 0x0, 0x0 - dspck_dstio addqh.w, 0xf7fffca4, 0xf0000007, 0xfffff942, 0x0, 0x0 - dspck_dstio addqh.w, 0x38e38e38, 0x38e38e38, 0x38e38e38, 0x0, 0x0 - dspck_dstio addqh.w, 0xffeddc38, 0xffdbb57e, 0x000002f2, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffc6eb, 0xffff8dd8, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0x40000003, 0x7fffffff, 0x00000007, 0x0, 0x0 - dspck_dstio addqh.w, 0xdfffffe3, 0xffffffa7, 0xc000001f, 0x0, 0x0 - dspck_dstio addqh.w, 0xbff6e6d6, 0xffedcdac, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x2aaad101, 0x00004cae, 0x55555555, 0x0, 0x0 - dspck_dstio addqh.w, 0xff807fbf, 0xff00ff00, 0x0000007f, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffffe2, 0x80000004, 0x7fffffc0, 0x0, 0x0 - dspck_dstio addqh.w, 0x3ffffffe, 0x7fffffff, 0xfffffffe, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffffff, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xfe000000, 0xfc000001, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x43fffffd, 0x07fffffc, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0x002b158f, 0x00562b46, 0xffffffd8, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000002, 0x00000003, 0x80000001, 0x0, 0x0 - dspck_dstio addqh.w, 0x09fffffd, 0x0ffffffc, 0x03fffffe, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000005, 0x00000005, 0x00000006, 0x0, 0x0 - dspck_dstio addqh.w, 0x087f807e, 0x00ff00ff, 0x0ffffffe, 0x0, 0x0 - dspck_dstio addqh.w, 0x3e8d552c, 0x7fffffff, 0xfd1aaa59, 0x0, 0x0 - dspck_dstio addqh.w, 0x0000006e, 0x0000003f, 0x0000009e, 0x0, 0x0 - dspck_dstio addqh.w, 0x400097ab, 0x00012f58, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffffffe, 0x7ffffffc, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xff774142, 0xfeee8285, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x1000c7c8, 0x00018f95, 0x1ffffffc, 0x0, 0x0 - dspck_dstio addqh.w, 0x40000002, 0x00000005, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0x03ef6066, 0xffdec0cf, 0x07fffffe, 0x0, 0x0 - dspck_dstio addqh.w, 0xffb63183, 0xff6c6306, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xff807f83, 0xff00ff00, 0x00000007, 0x0, 0x0 - dspck_dstio addqh.w, 0x5ffffffd, 0x7fffffff, 0x3ffffffc, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffff00, 0xffffff00, 0xffffff00, 0x0, 0x0 - dspck_dstio addqh.w, 0x000144dc, 0x000289b9, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xbf8d4ed6, 0x80000003, 0xff1a9daa, 0x0, 0x0 - dspck_dstio addqh.w, 0xfe7f4090, 0xfcfe8121, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x03c898ae, 0x0791315c, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xc56173b3, 0x0ac2e760, 0x80000007, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffffff, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffffffb, 0xfffffffe, 0xfffffff8, 0x0, 0x0 - dspck_dstio addqh.w, 0xf800aeb7, 0x00015d68, 0xf0000007, 0x0, 0x0 - dspck_dstio addqh.w, 0x2aaaaaaa, 0x55555555, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x0000f569, 0x0001eb4f, 0xffffff83, 0x0, 0x0 - dspck_dstio addqh.w, 0x0800001d, 0x0ffffffc, 0x0000003f, 0x0, 0x0 - dspck_dstio addqh.w, 0x0005ce3e, 0xffffffdd, 0x000b9ca0, 0x0, 0x0 - dspck_dstio addqh.w, 0xdc71c71c, 0x80000000, 0x38e38e38, 0x0, 0x0 - dspck_dstio addqh.w, 0x1ffffffc, 0x00000018, 0x3fffffe0, 0x0, 0x0 - dspck_dstio addqh.w, 0x43efada4, 0x7fffffff, 0x07df5b49, 0x0, 0x0 - dspck_dstio addqh.w, 0x01b25e99, 0xfffffffd, 0x0364bd35, 0x0, 0x0 - dspck_dstio addqh.w, 0x0000c659, 0x00018cb3, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x38e38e4e, 0x71c71c71, 0x0000002c, 0x0, 0x0 - dspck_dstio addqh.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x000000ff, 0x000000ff, 0x000000ff, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xbffff5bb, 0xffffeb77, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xbfff800f, 0xffff0000, 0x8000001f, 0x0, 0x0 - dspck_dstio addqh.w, 0xd5555555, 0xaaaaaaaa, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xd5555555, 0x00000000, 0xaaaaaaaa, 0x0, 0x0 - dspck_dstio addqh.w, 0xdbb34f6b, 0x008b3121, 0xb6db6db6, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000c75, 0x00000000, 0x000018eb, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffffe0, 0xffffffc0, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0x9555555c, 0xaaaaaaaa, 0x8000000f, 0x0, 0x0 - dspck_dstio addqh.w, 0x4076b0e8, 0x7ffffffc, 0x00ed61d4, 0x0, 0x0 - dspck_dstio addqh.w, 0x2aaaaaaa, 0x55555555, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xfff3652d, 0xffe6c981, 0x000000da, 0x0, 0x0 - dspck_dstio addqh.w, 0x44b02eb9, 0x7ffffff8, 0x09605d7a, 0x0, 0x0 - dspck_dstio addqh.w, 0x0013efed, 0x00209236, 0x00074da5, 0x0, 0x0 - dspck_dstio addqh.w, 0xbffffffd, 0x80000000, 0xfffffffb, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000338, 0x00000671, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x3f6a238c, 0x7ffffff8, 0xfed44720, 0x0, 0x0 - dspck_dstio addqh.w, 0x64924924, 0x7fffffff, 0x49249249, 0x0, 0x0 - dspck_dstio addqh.w, 0x38000000, 0x7fffffff, 0xf0000001, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffffff, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000000, 0x00000000, 0x80000001, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffffffd, 0x00000000, 0xfffffffb, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xe19050bf, 0x00000001, 0xc320a17e, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000006, 0x0000000c, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000002, 0x00000004, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x001ed11f, 0x00000000, 0x003da23f, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xbfffffff, 0x80000000, 0xffffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0x3ffeb2f4, 0xfffd65f8, 0x7ffffff0, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffffff, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xcccc7814, 0x99999999, 0xffff5690, 0x0, 0x0 - dspck_dstio addqh.w, 0xc000000b, 0xc0000007, 0xc000000f, 0x0, 0x0 - dspck_dstio addqh.w, 0xf8000002, 0xf0000007, 0xfffffffe, 0x0, 0x0 - dspck_dstio addqh.w, 0xffff2888, 0xffff2888, 0xffff2888, 0x0, 0x0 - dspck_dstio addqh.w, 0xbfffff80, 0xffffff00, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xdb6db675, 0xffffff35, 0xb6db6db6, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000003, 0x80000000, 0x00000007, 0x0, 0x0 - dspck_dstio addqh.w, 0x3ffffffe, 0xfffffffe, 0x7ffffffe, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffff7f, 0x7fffffff, 0xffffff00, 0x0, 0x0 - dspck_dstio addqh.w, 0x59999989, 0x33333333, 0x7fffffe0, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xf0000007, 0xf0000007, 0xf0000007, 0x0, 0x0 - dspck_dstio addqh.w, 0xc00000d4, 0x80000002, 0x000001a7, 0x0, 0x0 - dspck_dstio addqh.w, 0xdffffffe, 0x80000000, 0x3ffffffc, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0x1ff102a8, 0x3ffffff0, 0xffe20561, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xbff42c92, 0xffe85925, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xf1c71c71, 0xaaaaaaaa, 0x38e38e38, 0x0, 0x0 - dspck_dstio addqh.w, 0x00023367, 0xfffffffc, 0x000466d2, 0x0, 0x0 - dspck_dstio addqh.w, 0xf8000003, 0xf0000007, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xff807f80, 0x00000000, 0xff00ff00, 0x0, 0x0 - dspck_dstio addqh.w, 0x40027c25, 0x7fffffff, 0x0004f84b, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x3f9fcf15, 0xff3f9e2c, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xfff9c870, 0x00000005, 0xfff390dc, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fc25387, 0xff84a710, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xbffffd58, 0xfffffab0, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xb904c03b, 0x80000000, 0xf2098076, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffffff2, 0xffffffe4, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x3f00ae1d, 0xfe015c3c, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xbffffff9, 0xfffffff2, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xbfffff4a, 0x80000000, 0xfffffe94, 0x0, 0x0 - dspck_dstio addqh.w, 0xbfe01fc0, 0xffc03f80, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0008001, 0x80000003, 0x0000ffff, 0x0, 0x0 - dspck_dstio addqh.w, 0x3ffff7d1, 0xffffefa4, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0x40002914, 0x00005249, 0x7fffffe0, 0x0, 0x0 - dspck_dstio addqh.w, 0x221d4ee8, 0x043a9df1, 0x3fffffe0, 0x0, 0x0 - dspck_dstio addqh.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xff020def, 0xfe041bde, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffffffd, 0x7ffffffb, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000000, 0xfffffffb, 0x00000006, 0x0, 0x0 - dspck_dstio addqh.w, 0xc00000cb, 0x80000000, 0x00000196, 0x0, 0x0 - dspck_dstio addqh.w, 0x0cd25a83, 0x0b4505df, 0x0e5faf28, 0x0, 0x0 - dspck_dstio addqh.w, 0x0ffffff6, 0x1ffffff0, 0xfffffffd, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffd176, 0xffffffff, 0xffffa2ed, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000000, 0x00000001, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x4ffffffa, 0x1ffffff8, 0x7ffffffd, 0x0, 0x0 - dspck_dstio addqh.w, 0xd491985f, 0xaaaaaaaa, 0xfe788615, 0x0, 0x0 - dspck_dstio addqh.w, 0x40000036, 0x7ffffffe, 0x0000006f, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffff80, 0xffffff00, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000016, 0x00000023, 0x00000009, 0x0, 0x0 - dspck_dstio addqh.w, 0x3e000000, 0x7fffffff, 0xfc000001, 0x0, 0x0 - dspck_dstio addqh.w, 0x1ffffff8, 0x3ffffff0, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xbfff66e1, 0xfffecdc2, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xf0000000, 0x00000000, 0xe0000001, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffffff, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0xfc000005, 0x00000007, 0xf8000003, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffffda, 0xffffffda, 0xffffffda, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xb0000003, 0x80000000, 0xe0000007, 0x0, 0x0 - dspck_dstio addqh.w, 0xc0000018, 0xfffffff1, 0x8000003f, 0x0, 0x0 - dspck_dstio addqh.w, 0xe000001b, 0x3ffffff8, 0x8000003f, 0x0, 0x0 - dspck_dstio addqh.w, 0x1d986f80, 0x3b6f4028, 0xffc19ed9, 0x0, 0x0 - dspck_dstio addqh.w, 0x0aaaaaae, 0xc0000007, 0x55555555, 0x0, 0x0 - dspck_dstio addqh.w, 0x1248fe2b, 0x24924924, 0xffffb333, 0x0, 0x0 - dspck_dstio addqh.w, 0x0001ca6e, 0x000394cd, 0x0000000f, 0x0, 0x0 - dspck_dstio addqh.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xf7e0ad68, 0xffc15ad0, 0xf0000001, 0x0, 0x0 - dspck_dstio addqh.w, 0x80000002, 0x80000004, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000003, 0x00000000, 0x00000006, 0x0, 0x0 - dspck_dstio addqh.w, 0xfffffff1, 0x00000000, 0xffffffe3, 0x0, 0x0 - dspck_dstio addqh.w, 0x0e38e38e, 0x1c71c71c, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000004, 0x00000008, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0xffffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x52492491, 0x7fffffff, 0x24924924, 0x0, 0x0 - dspck_dstio addqh.w, 0x3e8c09b9, 0x7fffffff, 0xfd181374, 0x0, 0x0 - dspck_dstio addqh.w, 0xbfffffff, 0x8000003f, 0xffffffc0, 0x0, 0x0 - dspck_dstio addqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x000000eb, 0x000001d7, 0x00000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x3fffed54, 0x7fffffe0, 0xffffdac9, 0x0, 0x0 - dspck_dstio addqh.w, 0xfc000000, 0x00000000, 0xf8000001, 0x0, 0x0 - dspck_dstio addqh.w, 0xbf0e62c0, 0x80000000, 0xfe1cc581, 0x0, 0x0 - dspck_dstio addqh.w, 0x3249248a, 0x3ffffff0, 0x24924924, 0x0, 0x0 - dspck_dstio addqh.w, 0xf0000004, 0x00000001, 0xe0000007, 0x0, 0x0 - dspck_dstio addqh.w, 0x7ffffffa, 0x7ffffffa, 0x7ffffffa, 0x0, 0x0 - dspck_dstio addqh.w, 0xe0014d4c, 0x00029a79, 0xc000001f, 0x0, 0x0 - dspck_dstio addqh.w, 0x07878797, 0x0f0f0f0f, 0x0000001f, 0x0, 0x0 - dspck_dstio addqh.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh.w, 0x3ffffffd, 0xfffffffc, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh.w, 0x003d608a, 0x0002bc6f, 0x007804a6, 0x0, 0x0 - - writemsg "[44] Test addqh_r.w" - dspck_dstio addqh_r.w, 0x001c2e53, 0xffffffed, 0x00385cb8, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xd55557da, 0x0000050a, 0xaaaaaaaa, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x07ffffff, 0x00000000, 0x0ffffffe, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc07f8083, 0x00ff00ff, 0x80000007, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3fffff92, 0xffffffa4, 0x7fffff80, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000a36, 0x0000146b, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000003, 0x00000000, 0x80000006, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffce4ead, 0x000021b8, 0xff9c7ba2, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfbff2863, 0xfffe50c3, 0xf8000003, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x006b3544, 0x00d66a89, 0xfffffffe, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfb87c222, 0xc3dc5111, 0x33333333, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000001, 0x00000001, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0737f9f, 0x80000000, 0x00e6ff3d, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0000021b, 0x00000435, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0e4639b4, 0x001aac4b, 0x1c71c71c, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xe0000017, 0xc000000f, 0x0000001f, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xe0000004, 0xe0000001, 0xe0000007, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbfffffff, 0x80000000, 0xfffffffd, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000004, 0x00000007, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x02022147, 0x03fffffe, 0x0004428f, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbfffcea2, 0x80000004, 0xffff9d40, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0000023f, 0x000004a2, 0xffffffdb, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xff4bf5da, 0xfe97eba2, 0x00000012, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfffffff7, 0x00000000, 0xffffffed, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfffffff6, 0xffffffec, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xd8000002, 0xf0000003, 0xc0000001, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfe2b8f23, 0xfe2b8f23, 0xfe2b8f23, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x7ffffff0, 0x7fffffe0, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc2f27694, 0x80000000, 0x05e4ed28, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000001, 0x00000001, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfffff9a5, 0x00000000, 0xfffff349, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x33333333, 0x66666666, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x20000000, 0xc0000001, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfe000001, 0xfc000001, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x36db68c5, 0x6db6db6d, 0xfffff61d, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x000000ee, 0x00000003, 0x000001d9, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc71c71c7, 0x00000000, 0x8e38e38e, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x4000007f, 0x000000ff, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3fffd85e, 0xffffb0bc, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfffffe9b, 0xfffffd36, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbffff359, 0x80000000, 0xffffe6b2, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00079fed, 0x000f3fda, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf8000001, 0x00000000, 0xf0000001, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000002, 0x80000004, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x07bc1ffd, 0xfff8f339, 0x0f7f4cc0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x20000001, 0x7fffffff, 0xc0000003, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfc57b223, 0xffffffc0, 0xf8af6486, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x24924925, 0x49249249, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x47fffffe, 0x7fffffff, 0x0ffffffc, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffffd536, 0xffffaa6c, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000011, 0x0000001f, 0x00000003, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x03979f3a, 0x00000000, 0x072f3e73, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3ff806f1, 0xfff00de3, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x7ffffff0, 0x7fffffe0, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x007e6f6e, 0x00ff00ff, 0xfffddddc, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffcd1c51, 0x0000003f, 0xff9a3862, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbb6a9bf9, 0xf6d537f2, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00008c1a, 0x00011833, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xcccccccd, 0x00000000, 0x99999999, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x78e38e38, 0x71c71c71, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3ffffffe, 0xfffffffd, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x1ffffffe, 0x00000000, 0x3ffffffc, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfffffdfe, 0xfffffdfe, 0xfffffdfe, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffebcf00, 0xffd79eff, 0xffffff00, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x4ffffff7, 0x7ffffffe, 0x1ffffff0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf878787b, 0xf0f0f0f0, 0x00000006, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x2ffffffd, 0x1ffffffc, 0x3ffffffe, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xec9a775a, 0xffff4359, 0xd935ab5b, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xe0000002, 0x00000000, 0xc0000003, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000008, 0x8000000f, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffffffbf, 0xffffff80, 0xfffffffd, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0000000f, 0x00000000, 0x0000001d, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000000, 0xffffffff, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00002f90, 0xfffffffb, 0x00005f25, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xdb6ee8cf, 0xb6db6db6, 0x000263e8, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000003, 0x7fffffff, 0x00000006, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbf030c41, 0x80000000, 0xfe061881, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbf8dec7a, 0x80000001, 0xff1bd8f3, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffcac1e3, 0xfffffff8, 0xff9583ce, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xd5555555, 0xaaaaaaaa, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfffffff8, 0x00000000, 0xfffffff0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0003b152, 0x000af736, 0xfffc6b6e, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xd5555556, 0xaaaaaaaa, 0x00000002, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x1c71c720, 0x38e38e38, 0x00000007, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf9906a36, 0xf378b685, 0xffa81de6, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf8015b6a, 0x0002b6d2, 0xf0000001, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x01d83e62, 0x00000000, 0x03b07cc3, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0005d570, 0x000baadf, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x00000003, 0xfffffffd, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x08000006, 0x0ffffffe, 0x0000000e, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3ffbc0cd, 0x7fffffff, 0xfff7819a, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x07fffffb, 0x0ffffff8, 0xfffffffe, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0000033f, 0x00000681, 0xfffffffc, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00008000, 0x0000ffff, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3ffffff0, 0x00000000, 0x7fffffe0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf7ffffd7, 0xffffffac, 0xf0000001, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xe38e38e6, 0xc71c71c7, 0x00000005, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffd22f1c, 0xfffffff0, 0xffa45e47, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3fffffc0, 0x00000000, 0x7fffff80, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x78e38e19, 0x71c71c71, 0x7fffffc0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x20000000, 0xc0000001, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf1c71c62, 0xe38e38e3, 0xffffffe0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfde8abd7, 0xfbd157ad, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfffffd4e, 0xfffffa9b, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00089cd9, 0xfffffffe, 0x001139b4, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3fffffff, 0xffffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000000, 0x7ffffffb, 0x00000004, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffffffff, 0x00000000, 0xfffffffd, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xd5555558, 0xaaaaaaaa, 0x00000006, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xedb6db6e, 0x00000000, 0xdb6db6db, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf1b6db6d, 0xdb6db6db, 0x07fffffe, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x332937e8, 0x66666666, 0xffec096a, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xe0000004, 0x00000000, 0xc0000007, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000f2d, 0x80000000, 0x00001e59, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfb4d222c, 0xfb4d222c, 0xfb4d222c, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000007, 0x7fffffff, 0x0000000f, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfff2720c, 0xffe4e418, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000001, 0x80000000, 0x00000002, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x02000001, 0x03fffffe, 0x00000004, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000160, 0x000002c0, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x404316be, 0x00862d7d, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x000000d2, 0x00000000, 0x000001a4, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000002, 0x00000005, 0xffffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc00000b7, 0x80000000, 0x0000016d, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3fff1ad6, 0xfffe35cb, 0x7fffffe0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfeca0cca, 0xfd94533c, 0xffffc658, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfd7c9654, 0xfa792698, 0x00800610, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0ffffffc, 0x00000000, 0x1ffffff8, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfffed677, 0x0000029d, 0xfffdaa51, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc00019b9, 0x80000000, 0x00003371, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xeffffff9, 0xe0000001, 0xfffffff0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfc000000, 0xf8000003, 0xfffffffc, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x8ccccccd, 0x99999999, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0fffb73b, 0xffff6e78, 0x1ffffffe, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfff4e911, 0xfffa944b, 0xffef3dd6, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x000734ec, 0x000e69d6, 0x00000002, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffffff72, 0x00000000, 0xfffffee3, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbfcd0886, 0x80000000, 0xff9a110b, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0793bc28, 0x0793bc28, 0x0793bc28, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffffffd6, 0x00000000, 0xffffffab, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x4c294f11, 0x7fffffff, 0x18529e22, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000054, 0x00000000, 0x000000a7, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3fffffc0, 0x7fffffff, 0xffffff80, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf3333333, 0x80000000, 0x66666666, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfffffffe, 0x7ffffffb, 0x80000001, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00002e1a, 0x000070b7, 0xffffeb7c, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffd905d7, 0xffb4030a, 0xfffe08a3, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xedededee, 0x0f0f0f0f, 0xcccccccc, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x5ffffff0, 0x7fffffff, 0x3fffffe0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3b33332f, 0x66666666, 0x0ffffff8, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfffff2ad, 0x00000000, 0xffffe559, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000005, 0x00000009, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000001, 0x00000001, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x36db6db9, 0x6db6db6d, 0x00000005, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000002, 0x7fffffff, 0x80000005, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000001, 0x00000002, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000058, 0x80000000, 0x000000af, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbcccccce, 0xe0000003, 0x99999999, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf7ff8002, 0xffff0000, 0xf0000003, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x1ffffff9, 0x00000002, 0x3ffffff0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000005, 0x80000000, 0x00000009, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000005, 0x00000009, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xe38e38e2, 0xc71c71c7, 0xfffffffd, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00387f01, 0x00711173, 0xffffec8f, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000008, 0x8000000f, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffffffe0, 0x00000000, 0xffffffc0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x80000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbffffffd, 0x80000000, 0xfffffff9, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000002, 0x00000004, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbfffc643, 0xffff8c86, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0000001f, 0xfffffffe, 0x0000003f, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbfff8000, 0x80000000, 0xffff0000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf0000080, 0x000000ff, 0xe0000001, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000017, 0x0000002f, 0xfffffffe, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3ffffff0, 0x7fffffe0, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xe0000004, 0xc0000007, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf8787878, 0x00000000, 0xf0f0f0f0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfffa8163, 0xfffffff8, 0xfff502cd, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x24924925, 0x49249249, 0x00000001, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbfff77a4, 0xfffeef40, 0x80000007, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xbff2bb9c, 0x80000001, 0xffe57736, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc15f7fad, 0x80000000, 0x02beff5a, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfdc65340, 0xfb8ca680, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000690, 0x80000001, 0x00000d1e, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xb290f262, 0xe521e4c3, 0x80000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00003e81, 0x00007cff, 0x00000003, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xb1c71c74, 0xe38e38e3, 0x80000005, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x00000003, 0x00000000, 0x00000006, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x1f807f7c, 0x3ffffff8, 0xff00ff00, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfff7827d, 0xfff7827d, 0xfff7827d, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40088cfb, 0x001119f8, 0x7ffffffe, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xe38e3cb7, 0xc71c71c7, 0x000007a7, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3fffffe3, 0xffffffc9, 0x7ffffffc, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf5c71c70, 0xe38e38e3, 0x07fffffc, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3ffff9e6, 0x7ffffffb, 0xfffff3d0, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x003ed38d, 0x007da71b, 0xfffffffe, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3fffffff, 0x7ffffffa, 0x00000003, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000006, 0x0000000c, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x3fffffff, 0xfffffffe, 0x7fffffff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0003a055, 0x00000000, 0x000740a9, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xc0000003, 0xffffffff, 0x80000007, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x009322ba, 0x00000000, 0x01264574, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0012afc2, 0x00000668, 0x0025591c, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf8000083, 0xf0000007, 0x000000ff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xf1c71c72, 0xe38e38e3, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x400000ce, 0x7fffffff, 0x0000019c, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x0000006b, 0x00000000, 0x000000d5, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xfed45432, 0xfda8a765, 0x000000ff, 0x0, 0x0 - dspck_dstio addqh_r.w, 0xffffffe0, 0xffffffc0, 0x00000000, 0x0, 0x0 - dspck_dstio addqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - - writemsg "[45] Test subqh.w" - dspck_dstio subqh.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000002, 0xfffffffc, 0xfffffff8, 0x0, 0x0 - dspck_dstio subqh.w, 0x000001cf, 0xfffffff9, 0xfffffc5b, 0x0, 0x0 - dspck_dstio subqh.w, 0xffffffff, 0xffffffff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x0ffffffd, 0xfffffffe, 0xe0000003, 0x0, 0x0 - dspck_dstio subqh.w, 0xf1c71c73, 0xe38e38e3, 0xfffffffc, 0x0, 0x0 - dspck_dstio subqh.w, 0x40072e8c, 0x7ffffff8, 0xfff1a2df, 0x0, 0x0 - dspck_dstio subqh.w, 0xffff94d2, 0xffff29a5, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0xef8d03bd, 0xdf1a077b, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xefffffff, 0xfffffffc, 0x1ffffffe, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000010, 0x00000018, 0x7ffffff8, 0x0, 0x0 - dspck_dstio subqh.w, 0x43fffffa, 0x07fffffc, 0x80000007, 0x0, 0x0 - dspck_dstio subqh.w, 0xbfffffcf, 0x80000007, 0x00000069, 0x0, 0x0 - dspck_dstio subqh.w, 0xbf2a3e1a, 0xfe547c33, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000023, 0x80000006, 0xffffffc0, 0x0, 0x0 - dspck_dstio subqh.w, 0x07fffffc, 0x0ffffff8, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x78e38e38, 0x7fffffff, 0x8e38e38e, 0x0, 0x0 - dspck_dstio subqh.w, 0x38e380c1, 0xffffe510, 0x8e38e38e, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0008000, 0x80000000, 0xffff0000, 0x0, 0x0 - dspck_dstio subqh.w, 0x03935765, 0x00000000, 0xf8d95135, 0x0, 0x0 - dspck_dstio subqh.w, 0xffffffff, 0xffffffff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000007, 0x0000000e, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0xffedf426, 0xffdbe85d, 0x00000010, 0x0, 0x0 - dspck_dstio subqh.w, 0x0000011a, 0x0000023a, 0x00000005, 0x0, 0x0 - dspck_dstio subqh.w, 0x41ac198f, 0x7ffffff8, 0xfca7ccd9, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000003, 0x7fffffff, 0x7ffffff9, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000020, 0x00000021, 0x7fffffe0, 0x0, 0x0 - dspck_dstio subqh.w, 0xbffffffd, 0xfffffffa, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0xff1f0938, 0x00000000, 0x01c1ed8f, 0x0, 0x0 - dspck_dstio subqh.w, 0x01f31c43, 0xffe63888, 0xfc000001, 0x0, 0x0 - dspck_dstio subqh.w, 0x7ffffffd, 0x7fffffff, 0x80000005, 0x0, 0x0 - dspck_dstio subqh.w, 0x0ccccccc, 0x7fffffff, 0x66666666, 0x0, 0x0 - dspck_dstio subqh.w, 0x3ffffffc, 0xffffffff, 0x80000007, 0x0, 0x0 - dspck_dstio subqh.w, 0xadb6db6e, 0xdb6db6db, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x1c398ddd, 0x00000000, 0xc78ce445, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xffe4e571, 0xffc9c9e2, 0xffffff00, 0x0, 0x0 - dspck_dstio subqh.w, 0xfffee4e2, 0xfffe5537, 0x00008b73, 0x0, 0x0 - dspck_dstio subqh.w, 0xfffd2c0b, 0xffff0000, 0x0004a7ea, 0x0, 0x0 - dspck_dstio subqh.w, 0x3fd334e4, 0x7ffffffd, 0x00599635, 0x0, 0x0 - dspck_dstio subqh.w, 0x0e38e90e, 0x1c71c71c, 0xfffff500, 0x0, 0x0 - dspck_dstio subqh.w, 0xcffffff8, 0x80000000, 0xe000000f, 0x0, 0x0 - dspck_dstio subqh.w, 0xfffffffe, 0x00000000, 0x00000004, 0x0, 0x0 - dspck_dstio subqh.w, 0x4000000c, 0x00000018, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x00000000, 0xffffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0xffa1a497, 0xffffff80, 0x00bcb652, 0x0, 0x0 - dspck_dstio subqh.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x4000003f, 0x7fffffff, 0xffffff80, 0x0, 0x0 - dspck_dstio subqh.w, 0xbf807f80, 0x80000000, 0x00ff00ff, 0x0, 0x0 - dspck_dstio subqh.w, 0x07576dca, 0x0eaedb95, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xd4cccccc, 0x0ffffffe, 0x66666666, 0x0, 0x0 - dspck_dstio subqh.w, 0x3fffff6d, 0xfffffedb, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000002, 0x00000000, 0xfffffffc, 0x0, 0x0 - dspck_dstio subqh.w, 0x40000002, 0x7fffffff, 0xfffffffa, 0x0, 0x0 - dspck_dstio subqh.w, 0xffffff80, 0xffffff00, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xc9249247, 0xfffffffc, 0x6db6db6d, 0x0, 0x0 - dspck_dstio subqh.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x05e03a4e, 0xfff7f3dd, 0xf4377f41, 0x0, 0x0 - dspck_dstio subqh.w, 0x80000001, 0x80000000, 0x7ffffffd, 0x0, 0x0 - dspck_dstio subqh.w, 0xe66664e6, 0xfffffd00, 0x33333333, 0x0, 0x0 - dspck_dstio subqh.w, 0x0000b407, 0x00016802, 0xfffffff3, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000189, 0x000002f2, 0xffffffe0, 0x0, 0x0 - dspck_dstio subqh.w, 0x3ffc3657, 0xfff86caf, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xdff8bda6, 0xfff17b4a, 0x3ffffffe, 0x0, 0x0 - dspck_dstio subqh.w, 0xc1835749, 0x0306ae91, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x07fffede, 0x0ffffff8, 0x0000023b, 0x0, 0x0 - dspck_dstio subqh.w, 0x3ffffff0, 0x00000000, 0x8000001f, 0x0, 0x0 - dspck_dstio subqh.w, 0xe0000004, 0xc000000f, 0x00000007, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x3ff77753, 0xffeeeea7, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0xcffffffe, 0x80000000, 0xe0000003, 0x0, 0x0 - dspck_dstio subqh.w, 0x0e36c890, 0xfffbca03, 0xe38e38e3, 0x0, 0x0 - dspck_dstio subqh.w, 0xfffffffd, 0xfffffffb, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x3ffffe2c, 0x7fffffff, 0x000003a6, 0x0, 0x0 - dspck_dstio subqh.w, 0xbfff4575, 0x80000000, 0x00017515, 0x0, 0x0 - dspck_dstio subqh.w, 0xc00004b7, 0x80000003, 0xfffff694, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xbffffff8, 0xffffffeb, 0x7ffffffb, 0x0, 0x0 - dspck_dstio subqh.w, 0x3fffffbd, 0x7fffffe0, 0x00000066, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x105324c2, 0x00a6498c, 0xe0000007, 0x0, 0x0 - dspck_dstio subqh.w, 0x2000000f, 0xc000001f, 0x80000001, 0x0, 0x0 - dspck_dstio subqh.w, 0xc000000f, 0x8000001f, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x0001894e, 0x00031261, 0xffffffc5, 0x0, 0x0 - dspck_dstio subqh.w, 0x3ffffffe, 0x7fffffff, 0x00000003, 0x0, 0x0 - dspck_dstio subqh.w, 0xf80b23d0, 0xf0f0f0f0, 0x00daa950, 0x0, 0x0 - dspck_dstio subqh.w, 0x07c00d4c, 0x0ffffffc, 0x007fe564, 0x0, 0x0 - dspck_dstio subqh.w, 0x3fffffbb, 0xfffffff6, 0x8000007f, 0x0, 0x0 - dspck_dstio subqh.w, 0x400075bb, 0x7fffffff, 0xffff1489, 0x0, 0x0 - dspck_dstio subqh.w, 0xbf6334b0, 0x80000000, 0x013996a0, 0x0, 0x0 - dspck_dstio subqh.w, 0xc3fffffe, 0x80000000, 0xf8000003, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x0000021e, 0x0000021e, 0x0, 0x0 - dspck_dstio subqh.w, 0x36db6db7, 0x00000001, 0x92492492, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0434639, 0x8000001f, 0xff7973ad, 0x0, 0x0 - dspck_dstio subqh.w, 0xffffd64d, 0x00000000, 0x00005365, 0x0, 0x0 - dspck_dstio subqh.w, 0xeb20f296, 0xc000000f, 0xe9be1ae2, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000001, 0x80000002, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xbfffffc0, 0xffffff80, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0xeaaaaaab, 0x80000000, 0xaaaaaaaa, 0x0, 0x0 - dspck_dstio subqh.w, 0x18000003, 0xf0000007, 0xc0000001, 0x0, 0x0 - dspck_dstio subqh.w, 0xbea0ad0c, 0x80000005, 0x02bea5ec, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000009, 0x00000012, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x000d812e, 0x001b025c, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xf8787875, 0xfffffff9, 0x0f0f0f0f, 0x0, 0x0 - dspck_dstio subqh.w, 0xf6ce4183, 0xfffde50e, 0x12616208, 0x0, 0x0 - dspck_dstio subqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x36db6db5, 0xfffffffc, 0x92492492, 0x0, 0x0 - dspck_dstio subqh.w, 0xbc000002, 0xf8000003, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xfffffffc, 0x00000000, 0x00000007, 0x0, 0x0 - dspck_dstio subqh.w, 0xdffffffc, 0x3ffffff8, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x00206760, 0x00029488, 0xffc1c5c8, 0x0, 0x0 - dspck_dstio subqh.w, 0xc000000a, 0x80000000, 0xffffffeb, 0x0, 0x0 - dspck_dstio subqh.w, 0x7fffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x76db6db6, 0x6db6db6d, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x10000008, 0x1ffffffe, 0xffffffee, 0x0, 0x0 - dspck_dstio subqh.w, 0x000009b0, 0x00001360, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xbf94ea3f, 0xf0f0f0f0, 0x71c71c71, 0x0, 0x0 - dspck_dstio subqh.w, 0x40000000, 0x7fffffff, 0xffffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x02242312, 0x0448a055, 0x00005a30, 0x0, 0x0 - dspck_dstio subqh.w, 0x3ffff1b4, 0xffffe368, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x7fffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000002, 0x00000004, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x3ffffff8, 0xfffffff0, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x0fffffff, 0x1ffffffc, 0xfffffffe, 0x0, 0x0 - dspck_dstio subqh.w, 0xc71c06f7, 0x8e38e38e, 0x0000d59f, 0x0, 0x0 - dspck_dstio subqh.w, 0xffffcc01, 0xffff9802, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x40000071, 0x7fffffff, 0xffffff1d, 0x0, 0x0 - dspck_dstio subqh.w, 0xbffffd5c, 0x80000000, 0x00000547, 0x0, 0x0 - dspck_dstio subqh.w, 0x400006c3, 0x7fffffff, 0xfffff279, 0x0, 0x0 - dspck_dstio subqh.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x8000000f, 0x8000000f, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000007, 0x0000000f, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xb6e5ed26, 0x80000000, 0x123425b3, 0x0, 0x0 - dspck_dstio subqh.w, 0xbfffff8b, 0xffffff15, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x4000007f, 0x7fffffff, 0xffffff00, 0x0, 0x0 - dspck_dstio subqh.w, 0x0000007f, 0x000000ff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x8ccccccd, 0x80000000, 0x66666666, 0x0, 0x0 - dspck_dstio subqh.w, 0x3fffff9b, 0x7fffffff, 0x000000c8, 0x0, 0x0 - dspck_dstio subqh.w, 0xc9249249, 0x00000000, 0x6db6db6d, 0x0, 0x0 - dspck_dstio subqh.w, 0xfffffd6d, 0xfffffad2, 0xfffffff8, 0x0, 0x0 - dspck_dstio subqh.w, 0xc05a2b05, 0x00b455eb, 0x7fffffe0, 0x0, 0x0 - dspck_dstio subqh.w, 0xf8000002, 0x00000000, 0x0ffffffc, 0x0, 0x0 - dspck_dstio subqh.w, 0xce38e38e, 0x80000000, 0xe38e38e3, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000010, 0x00000000, 0xffffffe0, 0x0, 0x0 - dspck_dstio subqh.w, 0x4000000f, 0x0000001f, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x76db6db6, 0x6db6db6d, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x245f6257, 0x49249249, 0x0065cd9b, 0x0, 0x0 - dspck_dstio subqh.w, 0xfff90c88, 0x00000000, 0x000de6ef, 0x0, 0x0 - dspck_dstio subqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xb0000008, 0x80000000, 0x1ffffff0, 0x0, 0x0 - dspck_dstio subqh.w, 0x3f69acda, 0x7fffffff, 0x012ca64a, 0x0, 0x0 - dspck_dstio subqh.w, 0x0000001c, 0x00000002, 0xffffffca, 0x0, 0x0 - dspck_dstio subqh.w, 0x47ffffff, 0x7fffffff, 0xf0000001, 0x0, 0x0 - dspck_dstio subqh.w, 0x7fffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xbed9f06a, 0x8000000f, 0x024c1f3b, 0x0, 0x0 - dspck_dstio subqh.w, 0xbfffff81, 0xffffff02, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x00007ffc, 0xfffffff8, 0xffff0000, 0x0, 0x0 - dspck_dstio subqh.w, 0xe30e12e7, 0xe28decea, 0x1c71c71c, 0x0, 0x0 - dspck_dstio subqh.w, 0xf1c71c52, 0xffffffc1, 0x1c71c71c, 0x0, 0x0 - dspck_dstio subqh.w, 0x0000d973, 0x0001739e, 0xffffc0b7, 0x0, 0x0 - dspck_dstio subqh.w, 0xe1bd3033, 0x037a605e, 0x3ffffff8, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000003, 0x80000006, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x4000001f, 0x0000003f, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xdb6db6de, 0x00000005, 0x49249249, 0x0, 0x0 - dspck_dstio subqh.w, 0x7fffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0003cd9, 0x8000007f, 0xffff86cc, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000053, 0xfffffff9, 0xffffff53, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000001, 0x00000003, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x0000001e, 0xfffffe63, 0xfffffe27, 0x0, 0x0 - dspck_dstio subqh.w, 0xffffffff, 0x00000000, 0x00000001, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000001, 0x0000000a, 0x00000008, 0x0, 0x0 - dspck_dstio subqh.w, 0xdfffffff, 0x80000000, 0xc0000001, 0x0, 0x0 - dspck_dstio subqh.w, 0xf34e99c0, 0xe784bb19, 0x00e78799, 0x0, 0x0 - dspck_dstio subqh.w, 0x3ffffffc, 0x7ffffff8, 0xffffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x3fffffff, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x0000007f, 0xfffffffe, 0xffffff00, 0x0, 0x0 - dspck_dstio subqh.w, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0xbffc0915, 0xfff81228, 0x7ffffffe, 0x0, 0x0 - dspck_dstio subqh.w, 0x0000049b, 0x000000ff, 0xfffff7c8, 0x0, 0x0 - dspck_dstio subqh.w, 0x000056e0, 0x00015b1a, 0x0000ad5a, 0x0, 0x0 - dspck_dstio subqh.w, 0x4e38e38e, 0x7fffffff, 0xe38e38e3, 0x0, 0x0 - dspck_dstio subqh.w, 0x00029102, 0x000521e5, 0xffffffe0, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x00000010, 0x00000010, 0x0, 0x0 - dspck_dstio subqh.w, 0x52492492, 0x24924924, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xfbffffff, 0xfffffffc, 0x07fffffe, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000002, 0x00000001, 0xfffffffc, 0x0, 0x0 - dspck_dstio subqh.w, 0xbffefb51, 0x80000001, 0x0002095e, 0x0, 0x0 - dspck_dstio subqh.w, 0x12343403, 0xffd61ee2, 0xdb6db6db, 0x0, 0x0 - dspck_dstio subqh.w, 0xc9249251, 0x92492492, 0xfffffff0, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000001, 0x00000002, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x3ffead8b, 0xfffd5b16, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x111a2950, 0x023452a1, 0xe0000001, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xe0001c7d, 0xc0000003, 0xffffc708, 0x0, 0x0 - dspck_dstio subqh.w, 0xfffffff8, 0x00000000, 0x0000000f, 0x0, 0x0 - dspck_dstio subqh.w, 0x12492482, 0x24924924, 0x0000001f, 0x0, 0x0 - dspck_dstio subqh.w, 0x3ffffcaf, 0x7fffffc0, 0x00000662, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xeaaaaaab, 0x55555555, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x80000001, 0x80000000, 0x7ffffffd, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x1db10c4b, 0x1db10c4b, 0x0, 0x0 - dspck_dstio subqh.w, 0xfffffffd, 0x00000000, 0x00000005, 0x0, 0x0 - dspck_dstio subqh.w, 0x3fffffe0, 0x7fffffff, 0x0000003f, 0x0, 0x0 - dspck_dstio subqh.w, 0x3ffffffa, 0xfffffffa, 0x80000005, 0x0, 0x0 - dspck_dstio subqh.w, 0xd8787888, 0xc000001f, 0x0f0f0f0f, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000002, 0x00000000, 0x7ffffffb, 0x0, 0x0 - dspck_dstio subqh.w, 0xffffb823, 0xffff704b, 0x00000005, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0xe0000002, 0xc000000f, 0x0000000b, 0x0, 0x0 - dspck_dstio subqh.w, 0x7fffffff, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_dstio subqh.w, 0x3fc87d59, 0xff90fb32, 0x8000007f, 0x0, 0x0 - dspck_dstio subqh.w, 0xbfffffda, 0x80000006, 0x00000051, 0x0, 0x0 - dspck_dstio subqh.w, 0x0dd0d75a, 0xfc000001, 0xe05e514d, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x403ce94e, 0x7fffffff, 0xff862d63, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0xffffffff, 0xffffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0xc0000000, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x0260df06, 0x03fffffe, 0xff3e41f2, 0x0, 0x0 - dspck_dstio subqh.w, 0xfffffffb, 0x00000000, 0x0000000a, 0x0, 0x0 - dspck_dstio subqh.w, 0x80000000, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh.w, 0x045c6e60, 0x00368e02, 0xf77db141, 0x0, 0x0 - dspck_dstio subqh.w, 0xc1a2e7f1, 0x0345cfdd, 0x7ffffffb, 0x0, 0x0 - dspck_dstio subqh.w, 0xffffffc0, 0x00000000, 0x0000007f, 0x0, 0x0 - dspck_dstio subqh.w, 0xf0000008, 0x0000000f, 0x1ffffffe, 0x0, 0x0 - dspck_dstio subqh.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh.w, 0xbfffffff, 0x80000000, 0x00000001, 0x0, 0x0 - dspck_dstio subqh.w, 0x4ffffffc, 0x1ffffff8, 0x80000000, 0x0, 0x0 - - writemsg "[46] Test subqh_r.w" - dspck_dstio subqh_r.w, 0xffffffff, 0x7ffffffc, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3ffffff3, 0x00000004, 0x8000001f, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3b0ded23, 0x7fffffff, 0x09e425ba, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffff6353, 0x00000000, 0x0001395a, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x00488e7e, 0x00488e7e, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xce38e38f, 0x80000000, 0xe38e38e3, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x31c71c70, 0xe38e38e3, 0x80000003, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00872e0d, 0x010e5c19, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffdde0b5, 0xffbbc97c, 0x00000812, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3fc71e03, 0x7fffffff, 0x0071c3fa, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xff89baf8, 0x0000001d, 0x00ec8a2e, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000002, 0x80000000, 0xfffffffc, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffff93b, 0xfffff276, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000010, 0x00000000, 0x7fffffe0, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffff1fb, 0xffffe3f3, 0xfffffffd, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffff9171, 0x000022e1, 0x0000ffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000002, 0x00000004, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000001, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc00002c5, 0x00000583, 0x7ffffff9, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xde000005, 0xfc000001, 0x3ffffff8, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffffffff, 0x00000000, 0x00000002, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xedb6db6b, 0xdb6db6db, 0x00000005, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3fffff9a, 0x7ffffffa, 0x000000c7, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x000003fe, 0x00000800, 0x00000005, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xa6666667, 0xcccccccc, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3fffb09e, 0xffff613c, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x12492492, 0x24924924, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x1ffffffe, 0x3ffffffe, 0x00000003, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x0000001c, 0x7ffffff8, 0x7fffffc0, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffe2283, 0xfffffed4, 0x0003b9ce, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xf1c64eb3, 0xfffe6481, 0x1c71c71c, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000011, 0x00000020, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000040, 0x00000000, 0x7fffff80, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000003, 0x7fffffff, 0xfffffffa, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xa0000002, 0x80000001, 0x3ffffffe, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x17fffffd, 0x0ffffffc, 0xe0000003, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000019, 0x0000003f, 0x0000000e, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x4000004e, 0x7fffffff, 0xffffff63, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffa5206, 0xfff4bb71, 0x00001766, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000001, 0x00000001, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xd0000000, 0x80000000, 0xe0000001, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000008, 0x0000000f, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffffb5d, 0x00000000, 0x00000947, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x95555556, 0xaaaaaaaa, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xedb6e224, 0x00000d6c, 0x24924924, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000004, 0xffffffff, 0xfffffff8, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x01304bc6, 0x0000000b, 0xfd9f687f, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3c000002, 0x7fffffff, 0x07fffffc, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3ffffff0, 0x7fffffff, 0x0000001f, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3ffffffe, 0x00000000, 0x80000004, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000001, 0x7fffffff, 0x7ffffffe, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffffffe, 0x00000000, 0x00000004, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xbfffffa2, 0x80000004, 0x000000c1, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000010, 0x00000020, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffb06b9, 0xfff60d71, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000005, 0x00000008, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x000001c7, 0xfffffff8, 0xfffffc6b, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc4000000, 0x07fffffe, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x4fffffff, 0x7fffffff, 0xe0000001, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffffe055, 0xfffffffd, 0x00003f53, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x09624045, 0xfffffc0a, 0xed3b7b80, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x36db6db7, 0x00000000, 0x92492492, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000080, 0x000000ff, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x1dee5b50, 0x3be82111, 0x000b6a71, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xa0000001, 0xc0000001, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x36db6df7, 0x0000007f, 0x92492492, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffff24e1, 0xfffe3d5c, 0xfffff39a, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000004, 0x00000000, 0xfffffff9, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc924924a, 0x00000000, 0x6db6db6d, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3f3b9830, 0x7fffffff, 0x0188cf9f, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000eb2, 0x00001d64, 0x80000001, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xf8000001, 0x00000000, 0x0ffffffe, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffff693, 0xfffffff9, 0x000012d4, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xe0000002, 0x3ffffffc, 0x7ffffff8, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffffffd, 0xfffffffa, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x4000791b, 0x0000f236, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffffffe5, 0x00000009, 0x0000003f, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffffffe1, 0x00000000, 0x0000003f, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffffffe, 0x7ffffffb, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000020, 0x0000003f, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x400016d4, 0x00002da7, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xefffa3ce, 0xe000000f, 0x0000b874, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x0000000f, 0x0000001d, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000002, 0x80000000, 0xfffffffd, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xd8000003, 0xf0000001, 0x3ffffffc, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x0000000e, 0xffffff9b, 0xffffff80, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3ff8eab8, 0xfff1d573, 0x80000003, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x4055317a, 0x00aa62f3, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xff688053, 0x0000001f, 0x012eff79, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc000041e, 0x00000838, 0x7ffffffd, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc001e15d, 0x0003c2b8, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3ffffffd, 0x7fffffff, 0x00000006, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc71c718c, 0xffffff89, 0x71c71c71, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x20000000, 0x00000000, 0xc0000001, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x1000017d, 0x1ffffff8, 0xfffffcfe, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfb5dbcbf, 0x00000000, 0x09448683, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffffff1, 0x7fffffe0, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xbffffcaf, 0xfffff95c, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x0000037c, 0x000006f8, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc08c8a8b, 0x01191514, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xff63dc33, 0x00000000, 0x0138479b, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xff523fac, 0x00000000, 0x015b80a8, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000002, 0x7fffffff, 0xfffffffb, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x7fffffff, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xd5555555, 0xaaaaaaaa, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3e000001, 0xfc000001, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000000, 0x7fffffff, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfdfffff3, 0xffffffe4, 0x03fffffe, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000008, 0x8000000f, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000001, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x0200001f, 0x0000003f, 0xfc000001, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x01f2725a, 0x03fffffe, 0x001b1b4a, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xbfea0af9, 0xffd415f1, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffac2a9, 0xfff58552, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000430, 0x00000846, 0xffffffe6, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x4000012a, 0x00000254, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xccccccca, 0x99999999, 0x00000005, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc000386c, 0x00007057, 0x7fffff80, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xf1c71cf2, 0x000000ff, 0x1c71c71c, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffffffc, 0x1ffffff0, 0x1ffffff8, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x95555556, 0x80000000, 0x55555555, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xf1c71c71, 0xfffffffe, 0x1c71c71c, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x4002c377, 0x7fffff80, 0xfffa7893, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfff485a0, 0xffe90b40, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xbfffffb7, 0xffffff6d, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000165, 0xfffffffc, 0xfffffd33, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffffff80, 0xffffff00, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xe4924926, 0x49249249, 0x7ffffffe, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffffe93, 0xfffffd26, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x03878789, 0x0f0f0f0f, 0x07fffffe, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000004, 0x00000000, 0xfffffff8, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xe6666667, 0x00000000, 0x33333333, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0004bdf, 0x80000000, 0xffff6842, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xcd96d052, 0x1b2da0a2, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x07ffffff, 0x0ffffffe, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x80000001, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x80000000, 0x7fffffff, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000001, 0x00000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xf7ffff48, 0xf0000007, 0x00000177, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfbfffc7c, 0xf8000001, 0x00000709, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc000005d, 0x000000b9, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000008, 0x00000000, 0xfffffff0, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffa3bd56, 0xffc442a7, 0x007cc7fc, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00011efa, 0x00000000, 0xfffdc20d, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x402580d4, 0x7fffff80, 0xffb4fdd9, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x0000000f, 0x0000001b, 0xfffffffe, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xe0000001, 0x00000000, 0x3ffffffe, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000ec0, 0x00001d7e, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffff7a5b, 0xfffef4b5, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x80000001, 0x80000000, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x16db6dbb, 0x6db6db6d, 0x3ffffff8, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000052, 0x00000000, 0xffffff5d, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xe0000001, 0xc0000001, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xb1c71c72, 0xe38e38e3, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x051c79f3, 0x0a38f3e5, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0xfffffffe, 0xffffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffffffff, 0x7ffffffd, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xbffffffe, 0x80000000, 0x00000004, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xe9c71c74, 0xe38e38e3, 0x0ffffffc, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffff1e1, 0x0000001f, 0x00001c5d, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3ffffffd, 0xfffffffa, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3f304cb7, 0xfe60996d, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x1ffffffe, 0x1ffffffe, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfddf601d, 0xfffb717e, 0x043cb145, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffffe59, 0xffffffa2, 0x000002f1, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x41ffffff, 0x03fffffe, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffee8aec, 0xffdd15f6, 0x0000001f, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3ffffff9, 0x00000000, 0x8000000f, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfff9b067, 0x000192c2, 0x000e31f5, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x0138583e, 0x0270b07b, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x52492492, 0x24924924, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x0005ef18, 0x000bdd2f, 0xffffff00, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xbffffffe, 0xfffffffa, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000001, 0x7fffffff, 0xfffffffe, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xd5555556, 0x00000000, 0x55555555, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000008, 0x0000000f, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc8000003, 0x0ffffffe, 0x7ffffff9, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xe6666667, 0x33333333, 0x66666666, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xd555553a, 0xaaaaaaaa, 0x00000037, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x43ffffff, 0x7fffffff, 0xf8000001, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xa0000004, 0x80000000, 0x3ffffff8, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x76db6db7, 0x7fffffff, 0x92492492, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3fffffa4, 0xffffff47, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000256, 0x7ffffff0, 0xfffffb44, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x03fccfc0, 0xfff99f81, 0xf8000001, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000169, 0x0000003f, 0xfffffd6d, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x000036cc, 0x00006d99, 0x00000001, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x40000000, 0x00000000, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000001, 0x00000000, 0x7ffffffe, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x07fffffe, 0x0ffffffc, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x01ffffff, 0x03fffffe, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3f769ced, 0xfeed39d9, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc928f7da, 0x92492492, 0xfff734de, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000001, 0x00000001, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc00089a4, 0x80000000, 0xfffeecb9, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x0001e8c1, 0xffffffff, 0xfffc2e7e, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x040001c0, 0x00000383, 0xf8000003, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000000, 0x80000000, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffe677c, 0x00000005, 0x0003310d, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x007f8080, 0x00000000, 0xff00ff00, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xc0000002, 0x00000003, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xa38e38e4, 0xc71c71c7, 0x7fffffff, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000003, 0x00000006, 0x00000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x3fffebd9, 0xffffd7b2, 0x80000000, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x384f2cdc, 0x7ffffffb, 0x0f61a643, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffdc404b, 0xffffff16, 0x00477e80, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x06196184, 0x0c313aef, 0xfffe77e8, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xbfffe9cf, 0x80000003, 0x00002c65, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xff61cc0c, 0xfec39819, 0x00000001, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffffffff, 0xffffffff, 0x00000002, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xffb8e420, 0xfe72c740, 0xff00ff00, 0x0, 0x0 - dspck_dstio subqh_r.w, 0xfffffff9, 0x00000000, 0x0000000f, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000000, 0xffbf1455, 0xffbf1455, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000399, 0x00000000, 0xfffff8cf, 0x0, 0x0 - dspck_dstio subqh_r.w, 0x00000020, 0x7fffffff, 0x7fffffc0, 0x0, 0x0 - - writemsg "[47] Test dpax.w.ph" - dspck_astio dpax.w.ph, 0xffcc0271, 0xca18bc2e, 0xffcc0271, 0xca57d72e, 0xfb808000, 0x0000f1fa, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xfffffffe, 0x23cfbe27, 0xfffffffe, 0x1d2fbe27, 0x0ff80d40, 0x80000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffcca479, 0xd7f08525, 0xffcca479, 0xd7f40525, 0x80000000, 0x7ffffff9, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xfffffffa, 0x80000000, 0x00750010, 0xff00ffea, 0x7fff8000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xe0000000, 0x00000001, 0xdfffffff, 0xffff8003, 0x00008002, 0x00018000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xfff6fe31, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffe83c, 0x7ee98f5a, 0xffffe83c, 0x7ee99763, 0x00010000, 0xfb9a0809, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x0077b797, 0x00000000, 0x0077b797, 0x01aa7ff8, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x0c988000, 0xe6f08000, 0xffdf8000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xff389ae7, 0xffffffff, 0xff389ae7, 0x00000000, 0x00030006, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffff55, 0x4ce6cffe, 0xffffff55, 0x4d31e1e9, 0xfb4ffe59, 0xfffcf001, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xff764a9a, 0xffffffff, 0xbf764aba, 0x7fff3ff0, 0xfffe8000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffed545b, 0xba8b4081, 0xffed545b, 0xba8b4081, 0x00000000, 0x7fff0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x02de41b6, 0x7fff05f4, 0x7fe0ffca, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x8e38e38e, 0x38e38e38, 0x8e38e38e, 0x38f888f8, 0x00007fe0, 0x002a7ffa, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x003959f5, 0xc83b70dd, 0x003959f5, 0xc85db054, 0x0e5ec001, 0xff770000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x0000000c, 0x4b8b9d19, 0x0000000c, 0x4b92db66, 0xc00f8000, 0x0000ffe3, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00006e32, 0x00000000, 0x0001ade7, 0x0000fffb, 0xc00f7fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffffffe1, 0x001f0a00, 0x0000ffff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f3dc7f, 0x000efc7d, 0xff2bfff8, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000005, 0x00000000, 0x3f8d80e9, 0x00e37fff, 0x7fff8001, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x1fffffff, 0xfffffff0, 0x20000000, 0x007f5245, 0x0ee400ff, 0x7ffffffd, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0x80010000, 0x80008000, 0x7fff7fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x0004056c, 0xff00e1aa, 0xffde0002, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x400fffdf, 0x7fff7fff, 0x00227fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x2aaa71cb, 0xaaaa1c71, 0xfffb8000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfff15a90, 0x800000b8, 0x007e001e, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x3fffffff, 0xfffffff8, 0x40000000, 0x010d6008, 0x0ff88000, 0xffe40ffe, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xe0203fbf, 0x00003fc0, 0x80010000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfd466820, 0x00ff3333, 0xf260ffff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x0fffffff, 0xfffffffc, 0x10000000, 0x002dcbf4, 0x0ffcee0b, 0xfd740001, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x24924924, 0x92492492, 0x24924924, 0x524aa490, 0x7fff7fff, 0x80000002, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xe66b6847, 0xffffffff, 0xe658686d, 0xffed7fff, 0xffed7fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfffe148d, 0x07cd0000, 0xfc76ffc1, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x0000007f, 0x00000000, 0x0000007f, 0x0f0f0388, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x000006af, 0xabcceced, 0x000006af, 0x72e894b5, 0xff807fff, 0x8e380194, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfe629883, 0x067c0000, 0x7ff0c03f, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xc0000000, 0x00000003, 0xbfffffff, 0xfff8f032, 0x2585801f, 0xfffeffc9, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x10b8748a, 0x743c61f0, 0x10b8748a, 0x6cb896c3, 0xffde0f0f, 0x803fffff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x008405b0, 0x557c83bc, 0x008405b0, 0x5709a350, 0x00243ff0, 0x06065555, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xffe5a17f, 0x00000000, 0x3fe5a17f, 0x8000ffac, 0x00008000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0ffef098, 0x7fff0587, 0x00031ffc, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000012, 0x00000000, 0x00400012, 0x0000ff80, 0x80000f0f, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00001250, 0x00000000, 0x0003df0a, 0x001effc8, 0x33337fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x66666666, 0x66666666, 0x66666666, 0x76628666, 0x1ff80002, 0x1ffc7fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000004, 0x00000000, 0x3fdfffc5, 0x003f807f, 0x80007fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x170b47a0, 0xe8f48004, 0xe8f48004, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffff3380, 0x001f0199, 0xff800000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xffffffff, 0x00000000, 0x00000095, 0x80000032, 0x00030000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfd8893bc, 0x13bcfffd, 0x0000e001, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x0b4f9e09, 0x00000000, 0x0b211fda, 0x80050000, 0x0ffc005d, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00030100, 0xff808000, 0xfffafffe, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000001, 0x80000000, 0x3fd80011, 0x80007ff0, 0x7fff003f, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xff013549, 0x681031d4, 0xff013549, 0x68130382, 0xf001ffed, 0xffe7ffd3, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xc0000000, 0x00000007, 0xbfffffff, 0xff809ee8, 0x0000801f, 0x00ff0a86, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xbfbf01c0, 0x8000fef9, 0x3fc07fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfffb000a, 0x7ffffffb, 0x7ffffffb, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfb6ff842, 0x0ff8ffff, 0x00e6b6db, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x0000088e, 0xffffffff, 0xffb9b579, 0x1c717ffc, 0xff58007b, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x0000000e, 0x00000000, 0x03fdf812, 0x7fff7fff, 0x07fefffe, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x66666666, 0x66666666, 0x66666666, 0xe6666666, 0x80008000, 0x80008000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xecf94b29, 0x00000000, 0x25df4b25, 0x00048e38, 0x80007fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x04020001, 0x8000fffe, 0x7ffff7fa, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xc0028000, 0x7ffb0000, 0xfffd8000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xf255837f, 0x47886f17, 0xf255837f, 0x0788f7b3, 0x8000ffe3, 0xffb47fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00027ffb, 0x00058000, 0x00007fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x03e1cdf8, 0xa96c16d6, 0x03e1cdf8, 0xe97096d6, 0xfff08000, 0x80078000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xd9e94f4d, 0x9d784e3b, 0xd9e94f4d, 0x3d7a8e38, 0x7fff7fff, 0xc0038000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x3fffffff, 0xfffffff8, 0x40000000, 0x0003fff0, 0x7fff7fff, 0x00080000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x1006fc7a, 0x1fc800ca, 0x2d997ff8, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x154a9560, 0x00003fe0, 0x55558000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffd8, 0x79c870b1, 0xffffffd8, 0x8c1ef049, 0x7ffc8000, 0xdb6d001a, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xffff36bb, 0xe003fffc, 0x2a520001, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x0000f2f5, 0x7c6b1ec2, 0x0000f2f5, 0x3c689ec8, 0x7fff8000, 0x7ffffffa, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xf0037fff, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xffffd533, 0xffffffff, 0xe001152f, 0x3ffc8000, 0x00028001, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xffffffc0, 0xffffffff, 0xfffe904a, 0xf8030017, 0xf8030017, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xfffce093, 0x7f16d58e, 0xfffce093, 0xc3a910fb, 0xdb6d8000, 0x8000e001, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xe0000000, 0x00000007, 0xe0000000, 0x00097ff4, 0x3a807fff, 0x00130000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffe5807f, 0xffff8000, 0x0035ff80, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x01e1c1e2, 0x1ffe0000, 0x03540f0f, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xffffff00, 0x00000000, 0x00150ee6, 0x8000fcd2, 0xfffbffd6, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xf4d6bbe0, 0xd4af2714, 0xf4d6bbe0, 0xd4af0be0, 0xfffe000a, 0xfd2aff6c, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xfffe180f, 0xffffffff, 0xfffe180f, 0x0ff87fff, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000006, 0x00000000, 0x012afdb0, 0xc0037fff, 0x02560000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00064bde, 0x6def2da8, 0x00064bde, 0x6def2da8, 0x00008001, 0x000038e3, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x001f0000, 0xf5fa0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xfffabeee, 0xffffffff, 0xc002beee, 0x80000000, 0x66667ff0, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x000a4200, 0x00000328, 0x03400000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x04877fff, 0x80008000, 0x0000f6f1, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x1fffffff, 0xfffffff8, 0x1fffffff, 0xfe048377, 0x0040fc01, 0x7fff0ffe, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x38e38e38, 0xe38e38e3, 0x38e38e38, 0xe38f38e1, 0x00027fff, 0x00020000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xfdb52b6d, 0xffffffff, 0xddb62b6d, 0xfffc3ffe, 0x80000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xffffff86, 0xffffffff, 0xff5b89a5, 0x052400ff, 0x0005e001, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x3ffe405a, 0x8000e00f, 0x00068002, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffe07fff, 0x00008000, 0x003f001d, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00002dcb, 0xf9bc70cf, 0x00002dcb, 0xe2d9b0df, 0x2dc53ff0, 0xffff8000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x3fffffff, 0xfffffffc, 0x40000000, 0x0001000c, 0xe0018000, 0xfffa0010, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xff4e7ffd, 0x00028000, 0x01657fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x3fffffff, 0xfffffffe, 0x40000000, 0x1c733e1f, 0x38e307fc, 0x003f7fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x00000000, 0xe30bfff4, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x38e38e38, 0xe38e38e3, 0x38e38e38, 0xe38e38e3, 0x00000000, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xf0000000, 0x00000007, 0xefffffff, 0xff92052f, 0x80047ffa, 0xff240000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xf576e81f, 0xffffffff, 0xf576e81f, 0x00000000, 0x01dbff60, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xfc000000, 0x00000001, 0xfc000000, 0x000a8001, 0x00008000, 0xffeb7fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x0011e31c, 0x00000000, 0x000d822a, 0xff00c00f, 0x0012ffe2, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x000068c0, 0x00000000, 0x000ee8a3, 0x7fff0000, 0xfff5001d, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfaa7727f, 0x051b8000, 0x0fc77f80, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xffff8018, 0x80007ff8, 0xfffdfffe, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0x00157fc0, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x0144fd76, 0x0ff87fff, 0x028a0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xf8000000, 0x00000003, 0xf7ffffff, 0xbfd81c3f, 0x07fc7fff, 0x8000faf1, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xfffffffe, 0x00000000, 0x009a9c28, 0x0da2ff80, 0xe2c90a45, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000004, 0x00000000, 0x000015e8, 0x00000579, 0x00048000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x000db8ca, 0xe62a7100, 0x000db8ca, 0xe62be7f4, 0x0007007f, 0x02f10033, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xff6a2e0d, 0x0000e003, 0x04afe001, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00066c49, 0x00000000, 0x377af3dc, 0x7fffc01f, 0xfd976db6, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x0152375f, 0xfffc3cdd, 0x05977fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000002, 0x80000000, 0x071bb8e4, 0xc0070000, 0x8000e38e, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xfffffffb, 0x9491ad9b, 0xfffffffb, 0x9491ad9b, 0xe0010000, 0xe0010000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xfffffe04, 0x00000000, 0x078a7e04, 0xf0ac003f, 0x80008000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffd7c53c, 0x5cd959a6, 0xffd7c53c, 0x5a0cf1f3, 0xfff97fff, 0xfa66eb0b, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf00398e9, 0xe00700e2, 0xfff87fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfffffc02, 0x03fe0000, 0x0000ffff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0x9428d7af, 0x7fff9999, 0x7fff007f, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x66666666, 0x66666666, 0x66666666, 0x60058ba6, 0x0004e66b, 0x3fc08000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x000a003a, 0x00000000, 0x3fe8c312, 0xffa87fc0, 0x7fff0227, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xffff84fb, 0xffffffff, 0xfffc48e3, 0x80060f0f, 0xfffc0006, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x079a525f, 0xf0caffff, 0x7fff8003, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00007ffc, 0x7ffc3fe0, 0x00000001, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x0003000e, 0x5fa455fd, 0x0003000e, 0x200724bd, 0x03148000, 0x7fff1ff0, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x002a020e, 0x00000000, 0x1272dd7c, 0x80007fff, 0x24920000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x1fffffff, 0xfffffffc, 0x20000000, 0x00000ff8, 0xfffc0000, 0xccccfc01, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfffc43b1, 0x0000c03f, 0x000f1c71, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfb0e8930, 0xf62c008e, 0xf2567ffd, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00001534, 0xe6fbfbaf, 0x00001534, 0xe8421aad, 0xe38efffe, 0x0000f489, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x10d7ffff, 0x80008000, 0x0000de50, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffffeec6, 0x000a0000, 0x0000fe47, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xfa24204c, 0x272c952e, 0xfa24204c, 0x2824f0a3, 0x8000ffef, 0xb6dbfe19, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x202eb020, 0x807f7fff, 0x7fff3fe0, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000fffc, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x000d0000, 0x000d0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xfffffffc, 0xe50728f9, 0xfffffffd, 0x49912909, 0x7ff0b6db, 0x80007fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfff95548, 0x7ff0000f, 0x8e380000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0xff00c7f5, 0xfc017fff, 0x00013ffe, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xe0100000, 0x7fff8000, 0x3fe00000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x0000000a, 0xd15c588b, 0x0000000a, 0xd15c588b, 0x0000ff00, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffc813c6, 0xc149c5e6, 0xffc813c7, 0x0149c5e6, 0x80000000, 0xe0078000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x05084908, 0x00017ff8, 0x0a129999, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xf0000000, 0x00000007, 0xf0000000, 0x00000007, 0xffe50000, 0xff270000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xf0000000, 0x00000001, 0xf0000000, 0x08848001, 0x8000edc8, 0x8000012f, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000074, 0x1b0038de, 0x00000074, 0x1b36b871, 0x7fffff94, 0x0000006d, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xf0000000, 0x00000001, 0xefffffff, 0xffff2c61, 0xfff00000, 0x7fff0d3a, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfff91c64, 0xf803003e, 0xe38e0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xfe125772, 0x6b08c6aa, 0xfe125772, 0x6b095ed4, 0x00020006, 0xeeb27fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x1ff88000, 0x00008000, 0xc00ffffd, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffff0000, 0xffff0000, 0xffff0000, 0xf5667ffa, 0x7fff8000, 0x15370006, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf0009fff, 0x00007fff, 0xe0018003, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x0001ffbf, 0x00027ff0, 0x00027ff0, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000229, 0xfffdfff8, 0x0113fc6a, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x0016ab99, 0x4543824b, 0x0016ab99, 0x254b823b, 0x00018000, 0x3ff0fff0, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xe0000000, 0x00000007, 0xdfffffff, 0xfb81bbc9, 0xe01f8000, 0x07fe03fe, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0ffc0000, 0x0ffc0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000006, 0x00000000, 0x00000004, 0xffff0001, 0xffff0001, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xe0000000, 0x0000000f, 0xe0000000, 0x0000000f, 0x00000000, 0x8000803f, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x1fffffff, 0xfffffff8, 0x20000000, 0x00017ff5, 0x7fff0000, 0x00000003, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x1ff67e85, 0x807f3ff0, 0x7ff0fffb, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00007fff, 0x00007fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xfc000000, 0x00000001, 0xfc000000, 0x00000001, 0x000c0000, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xfffffffe, 0x7fffffff, 0xfffa5b77, 0x24927fff, 0xfffbffea, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xffd3e3a7, 0xffffffff, 0xffe36388, 0x001f0000, 0xf0037fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfd0a0000, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xfe687fe0, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xbfc7d4e3, 0x7fffc71c, 0x00ff8000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xfffffff9, 0x7fffffff, 0x8002fff5, 0x80048000, 0x7fff7fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x30039ff8, 0x8000e007, 0x7fff8000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x00077ff0, 0x7fff000f, 0x7fff0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x0148886e, 0xffc07fff, 0x0291ffd4, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x0007ffe0, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xc0000000, 0x00000003, 0xbfffffff, 0xffc82eab, 0xf801000c, 0xeb5106dc, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffffffc8, 0xffc80000, 0x00000001, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x0000003f, 0x00000000, 0x0000003f, 0xfdfffffe, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xf0000000, 0x00000003, 0xefffffff, 0xff43804b, 0x0179ffee, 0xfffc8000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xfe8ad804, 0xffffffff, 0xfe8adde2, 0x02ef0000, 0x7fff0002, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00febe, 0xfffdfff7, 0x00050007, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffc0, 0x7fffffff, 0xc04d7f26, 0x7fff8000, 0x7fff009a, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x92492492, 0x49249249, 0x92492492, 0x49249249, 0xe7848006, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xb6db6db6, 0xdb6db6db, 0xb6db6db6, 0xdb41b6db, 0x80000059, 0x8000ffff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xfffffff8, 0x43399daf, 0xfffffff8, 0x42529daf, 0x00008000, 0x01ce0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xfc4d31dc, 0xffffffff, 0xfc4d31dc, 0x7fff07fc, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x000a806d, 0x80038007, 0x002bffc0, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf8782d2f, 0x0000f0f0, 0x7ffd0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfff40000, 0x00008000, 0x0018ffff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x1fffffff, 0xfffffff8, 0x20000000, 0x004b843b, 0x00970002, 0x026d7fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000004, 0x68c0a988, 0x00000004, 0xb8b82989, 0x80007fff, 0x7fffe00f, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffeb, 0x78c2edb5, 0xffffffeb, 0x78b6b66e, 0x0000057f, 0xfdc77fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xfff0eef5, 0x51889b89, 0xfff0eef5, 0x51889b89, 0x9249c03f, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xf84ab6fc, 0xc09e0f91, 0xc09e0f91, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000004, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x0000006e, 0xffffffff, 0xbfd880be, 0xffb07fff, 0x80007fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x40000000, 0x80000000, 0x00c28000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000187, 0x00000000, 0x00000187, 0x6db63fe0, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x3425d915, 0x16035ef6, 0x3425d915, 0x15836ef6, 0xff807ff0, 0xff807ff0, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000007, 0x00000000, 0x00000007, 0x155a0000, 0x7fff0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x09d149d4, 0x7ffa3fe0, 0x000313a2, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00001b20, 0x00207fff, 0x000000d9, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00008000, 0x00007ff0, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x33333333, 0x33333333, 0x33333333, 0x33333397, 0xffcc0005, 0x00140000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x0fffffff, 0xfffffff8, 0x0fffffff, 0xffec09f8, 0x7fc00003, 0x0000ffd8, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x000106ed, 0x03147fff, 0xffff007f, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x000f7e5b, 0xffffffff, 0xbf12f5dc, 0xe01f8003, 0x7fff07fc, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffffe7dc, 0x0024fff0, 0xfff4ff4f, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x0000007f, 0x00000000, 0x003d3375, 0x00000099, 0x66660000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x000085a0, 0x00000000, 0x000085a0, 0x0000ff91, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000004, 0x00000000, 0x0475c622, 0x800001de, 0xffe1f714, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xfffffe4d, 0xae92c158, 0xfffffe4d, 0xcaf3c158, 0x7ff08000, 0xc73e0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xc0000000, 0x0000000f, 0xbfffffff, 0xfffe7ff3, 0x0007fffc, 0x80078000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffbb1d, 0x43b25b1f, 0xffffbb1d, 0x43b25b1f, 0x00000000, 0xcccce01f, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xe023feff, 0x80008004, 0xffc03ff8, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x1c71c71c, 0x71c71c71, 0x1c71c71c, 0x71c71c71, 0xffe50087, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xe0000000, 0x0000000f, 0xdfffffff, 0xfffff3c7, 0x020cfffd, 0x020cfffd, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xfffffffc, 0x7fffffff, 0xfffffffc, 0x00000000, 0xfb1ef803, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00001313, 0xa71010dc, 0x00001313, 0xa6e69284, 0x7ffffeab, 0x8000fe58, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00020017, 0xfff8ffff, 0xffd1c003, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xffffffc0, 0xffffffff, 0xffffffd0, 0xfffe8006, 0x0000fff8, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x005ac344, 0x00000000, 0x005ac6bf, 0xfed7fff8, 0x0000fffd, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x18931984, 0x9e5fb4f4, 0x18931984, 0x9e5fb4f4, 0x000008e3, 0x000008e3, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x0006aab7, 0xc71c0000, 0x01beffe2, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xf8e2fc4a, 0xccbc94c7, 0xf8e2fc4a, 0xcbfa964b, 0xfe7cff9a, 0x00007fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000ea5, 0xffffffff, 0xfe7150b5, 0x7ff87fc0, 0xfcfbffe6, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x0006b784, 0xffffffff, 0xffa3b698, 0x7fff01b2, 0x800000ec, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xfffffffd, 0xffffffff, 0xe02fba8b, 0x807f000f, 0x00b23fe0, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xfffffffc, 0x00000000, 0x0007c39a, 0xffa50007, 0x7ffff401, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xfffffffd, 0x80000000, 0x00187f9b, 0x7fff8002, 0xffcf0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xffffffff, 0xfffffffa, 0xffffffff, 0xffff01c4, 0xfffe0002, 0x00e47fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffd5af3, 0x7fffdb6d, 0x007f001f, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffff, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0xfffffff8, 0x00017fff, 0x00000000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfd8ea1cf, 0x00ff0801, 0xc0078e38, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x04078000, 0x80008000, 0xf7f10000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000007, 0x7fffffff, 0xfffb0011, 0xfffb7fff, 0xfffb7fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1c61c73c, 0x7fffffe0, 0x7fff0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x8e38e38e, 0x38e38e38, 0x8e38e38d, 0xf903a2d8, 0x7fc00a50, 0x00028000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x1fffffff, 0xfffffff8, 0x1fffffff, 0xdb6f36d6, 0x042db6db, 0x7ffa0000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xe6663334, 0xccccf371, 0x00007fff, 0x0, 0x0 - dspck_astio dpax.w.ph, 0xfffffffb, 0x69d2cb92, 0xfffffffb, 0x6e6ed51c, 0xffffefde, 0xb6dbfd60, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x80000000, 0x0000000f, 0x80000000, 0x3ff6000f, 0x80008000, 0x00148000, 0x0, 0x0 - dspck_astio dpax.w.ph, 0x0fffffff, 0xfffffffe, 0x10000000, 0x4000002e, 0x8000fffa, 0xfff88000, 0x0, 0x0 - - writemsg "[48] Test dpsx.w.ph" - dspck_astio dpsx.w.ph, 0x00000000, 0x00002f6a, 0x00000000, 0x03c83547, 0x92491ff8, 0x000108d3, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xffd31d0f, 0x3fe0ffc7, 0x168700c8, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xc0000000, 0x00000001, 0xbfffffff, 0xc0010000, 0x7fff7fff, 0x00007fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x0000036b, 0x077a03a6, 0x0000036a, 0xc77a03a6, 0x00008000, 0x80007fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00952fec, 0xffffffff, 0xf8b934e7, 0x01c91f5a, 0x38e37fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf1776268, 0xe38ef009, 0xfafe8003, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffff3, 0xffffffff, 0xc0ddf436, 0x7fff01ab, 0x80077ff0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x000b4598, 0x7860d4a7, 0x000b4598, 0x786454a7, 0xffe40007, 0x80000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x0000920f, 0xffffffff, 0xffcf059c, 0x7fff00d1, 0x0ffc0049, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffa4b7b3, 0xffb7f803, 0xf0017fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfc010015, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000002, 0x00000000, 0x00000002, 0x00000000, 0x8000ffd2, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffff873, 0x03c6ffff, 0x00000002, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xe9e8a7d3, 0xffffffff, 0xe9d3297b, 0x7fff3fc0, 0x00060028, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffffb, 0xffffffff, 0xffec0023, 0x7fff0000, 0x00000028, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x002e0000, 0x0000005c, 0x8000e003, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00003d56, 0xd2c15fd1, 0x00003d56, 0xd2c15fd1, 0xfff88000, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xfc000000, 0x00000001, 0xfc000000, 0x00000001, 0x00000000, 0x7fff7fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffff0000, 0xffff0000, 0xffff0000, 0xfffe012a, 0xfed80002, 0x7fff0001, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x3fff8000, 0x002d7fff, 0x80000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xe0000000, 0x00000007, 0xe0000000, 0x3ffe883d, 0x7fff020d, 0xfffc8002, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffff803f, 0x00007fc0, 0x0001fff3, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00037fe4, 0x00007ffc, 0xfff90000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffef0fe, 0x8000fc7b, 0xffb30000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x1fffffff, 0xfffffffe, 0x1fffffff, 0xfffffffe, 0x7fff8000, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xfb365ad0, 0x1ed0b6db, 0x0000aaaa, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffff70ee, 0x0f042e88, 0xffff70ee, 0x0f092e7e, 0x7ffffffb, 0x7ffffffb, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffc0, 0x7fffffff, 0xe666b29f, 0x00077fff, 0x3333000c, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000001, 0x00000000, 0x0003fc01, 0x0000fff8, 0x7f808003, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000fff8, 0x00002492, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x04fd00ff, 0x800003fe, 0x800003fe, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0018b892, 0xff95053b, 0xfb770000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x033172c2, 0x00000000, 0x03358aa2, 0x05fa8001, 0x0008fffc, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x0fffffff, 0xfffffff8, 0x10000000, 0x0000624a, 0x01b3f9ac, 0x000ffffe, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf0038000, 0x7fffe007, 0x80000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x0000007f, 0x80000000, 0x00817f7f, 0xff008000, 0x00037fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x0029da05, 0x03feffec, 0x7f80f803, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000076, 0x22a330e7, 0x00000076, 0x22a03147, 0x0006c001, 0x00007ff0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x08223fc0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x33333333, 0x33333333, 0x33333333, 0x498db953, 0x0c3138e3, 0x80007fe0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffff7, 0xffffffff, 0xfffffff7, 0x00000000, 0xf8010ffc, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000fd1, 0x941a16c2, 0x00000fd1, 0x941a16c2, 0x80000000, 0xfffc0000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x0000003f, 0xffffffff, 0xbf7b003f, 0x80008000, 0xfef68000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000006, 0x00000000, 0x00000006, 0x0001fa45, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xf9f06eaf, 0xffffffff, 0xf9e80851, 0x7ffe6666, 0x00150000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000736, 0x00000000, 0x012c9e61, 0x0259fffe, 0x0f1b8003, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00000000, 0x7ffffe10, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf2bfe482, 0xd6c300fe, 0x8000aaaa, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xdb6db6db, 0x6db6db6d, 0xdb6db6db, 0x6db7db6b, 0xc00ffffe, 0x7fff0000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x0000000a, 0xffffffff, 0xfffa0016, 0x8000000c, 0x7fff0000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffce0064, 0x00000064, 0x7fffc00f, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xff043c0e, 0xffffffff, 0xff5c6eec, 0x0006fe56, 0x33338000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xfffffff0, 0x00000000, 0x0001fffe, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xffff80d4, 0xffffffff, 0xffff80d4, 0x00000000, 0xfffa8000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x18c86851, 0x7ffff30f, 0x0002ce6f, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000024, 0x8f22c155, 0x00000024, 0x8f21c155, 0x80000001, 0x8000fffd, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xfff4005d, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffcd479d, 0x00f47fff, 0xfff938e3, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x0281bf68, 0x0000ebed, 0x1ff8fff9, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000001, 0x7fffffff, 0xffff3333, 0x9999f0f0, 0x0000fffe, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xff6b010f, 0xd0cd0002, 0x02fcfcd8, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x0000001f, 0x80000000, 0x007ff8ef, 0x078dff00, 0x7f80fff0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xe0000000, 0x00000003, 0xdfffffff, 0xfffffffc, 0x00010000, 0x3ffc0007, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfe0103fe, 0x7fff0000, 0x7fff03fe, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffff9, 0xffffffff, 0xfce5253d, 0x00000636, 0x7ffa5555, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000128, 0xffffffff, 0xcccfcdf2, 0x00007ff9, 0x6666ffc0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00e5fe34, 0xff1a7fff, 0xff1a7fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x07ffffff, 0xfffffffe, 0x08000000, 0x0000112c, 0x05ba0000, 0x7ffffffd, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffff2a0f, 0x00d40001, 0x02c500ff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfd1d0b8c, 0xf4740000, 0xe694c001, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x0a6f6607, 0x1efa9e25, 0x0a6f6607, 0x1efb7418, 0x2a01fffe, 0x7ffa0001, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffff7fff, 0xffff0000, 0xffff8000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffffd, 0xffffffff, 0xbffff7bd, 0xfd408000, 0x8000fffd, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x38e3dff4, 0x8000fffd, 0x1ffc71c7, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffff7043, 0xbf88adca, 0xffff7043, 0xbf88adca, 0x8000012f, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000003, 0x00000000, 0x00276083, 0xfa20ffff, 0xff0006b4, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x1812b202, 0x0c346666, 0xc0011ffe, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x800f0004, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x07e413dd, 0x00000000, 0x07e313df, 0x00007fff, 0x00028000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xe0000000, 0x0000000f, 0xdfffffff, 0xf007000f, 0x8000ffef, 0x8000e01f, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xff350b1a, 0xff358007, 0xff358007, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xf0000000, 0x00000001, 0xf0000000, 0x00000001, 0xfe2e0000, 0xfffe0000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffffe, 0x00000000, 0x07363aba, 0xe00f8005, 0x0f0ffd77, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1ff8e007, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xe0037fff, 0x800007fe, 0x0000c007, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00014485, 0xffffffff, 0xfd6f4a89, 0xfff97fff, 0x05240020, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00003ffc, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000014, 0x00000000, 0x001a7294, 0xff288000, 0xffff1ff0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x000005d6, 0xf4ab40d9, 0x000005d6, 0xf4cea0d2, 0xff007fff, 0xfff91fe0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf004fff9, 0x7fff8000, 0xe003fff9, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffaa, 0x29390e59, 0xffffffaa, 0x28b847a8, 0x000fff00, 0x80000d3f, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xf7c80000, 0x80000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x0003b7d7, 0x00000000, 0x10009807, 0x801ffff9, 0x3ffe1ffe, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07fe8006, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000004, 0xffffffff, 0xfa9ca1f8, 0xf8161954, 0x0e778000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfff96dca, 0xffffffff, 0xf801cda9, 0xc001c001, 0xe01f0002, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xfffffffc, 0x80000000, 0x07fea008, 0x1ffc0000, 0x0047c003, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xe38e47f4, 0x80010001, 0xf0f0c71c, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x0dcc0000, 0x00090000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000001, 0xffffffff, 0xe008373f, 0x00073ff0, 0x7fff013e, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xf0000000, 0x00000001, 0xf0000000, 0x00000001, 0x71c7fff4, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x00003ffd, 0xe001fffd, 0x00000002, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xf11dfd4f, 0xffffffff, 0xf0128589, 0x2492ffe0, 0x5555079b, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xd5d529aa, 0xff005555, 0x80007fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xfffe5659, 0xa74f6473, 0xfffe5659, 0xa94d6cef, 0x800507fc, 0xc01f0000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000007, 0x51b5bd6c, 0x00000007, 0x55b03d6c, 0x80000000, 0x000107f5, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x0000001f, 0x80000000, 0x0fee820f, 0x7fffe01f, 0x7ff00000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00007ffa, 0x0000fe64, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x07ffffff, 0xfffffffc, 0x07ffffff, 0xe666e662, 0x7ffe1ffe, 0x00003333, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xffffef5a, 0xffffffff, 0xbffdc558, 0xff127fff, 0x7ff8f8d5, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x132bd9a8, 0x80010000, 0x7fff2658, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x0000ec51, 0xffffffff, 0xe1e2f3d1, 0xc001f0f0, 0x1ff88000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x0fffffff, 0xfffffff8, 0x0fffffff, 0xfffce318, 0xfffd1fe0, 0x00190000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000003, 0x7fffffff, 0xfffe107f, 0x00000ffc, 0x001ffc4b, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x02a294cc, 0x3ffcffe8, 0xfff5f575, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0xbf02ff03, 0x80007fff, 0x00038007, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xe0000000, 0x00000007, 0xdfffffff, 0xfffb802a, 0xfff98000, 0xfff70005, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x0000007f, 0x80000000, 0x26ac5078, 0x8000f007, 0xc0015555, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffe6b82d, 0xec14ffff, 0x6666feb6, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x3fffffff, 0xfffffff0, 0x40000000, 0x000005f0, 0xfffa0006, 0xff000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffff8, 0x00000000, 0x02017f2c, 0x03d03ffe, 0xff9a8000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffec00c8, 0x00008005, 0xffd800ff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffffcf6, 0xfff93581, 0x0000ff91, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xffffffe8, 0xffffffff, 0xbb9f0449, 0x55557fff, 0x7fff0d26, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00bb4976, 0xfe9efeb6, 0x07fc7fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xff0037fd, 0x0000f801, 0xe003ff00, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000003, 0x7fffffff, 0xc0030004, 0x00078000, 0x80009249, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfffa8000, 0x00008000, 0xfff50000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xffbf07f5, 0xffffffff, 0xffbc07db, 0x7fffffe0, 0x8000ffe6, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xff92db59, 0xe0f2153f, 0xff92db59, 0xa0f1fe47, 0x8000008c, 0x002a8000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x0000003f, 0x7fffffff, 0xccd2af81, 0x00ee8000, 0x9999f959, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x07ff0000, 0x00000ffe, 0x80008005, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x0037dc2c, 0x00000000, 0x4ff6dcab, 0x7fff8000, 0x1ffe807f, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x3fe0003e, 0x7fff4924, 0x0000803f, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0xb6db0000, 0xe0070000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffd8, 0xa5e1ab49, 0xffffffd8, 0xe5e12b49, 0xc0018000, 0x7fff0000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffb58e5d, 0x7ffa01d0, 0x80000265, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x07ffffff, 0xfffffffe, 0x07ffffff, 0xc001fffb, 0x7ffd7fff, 0x00007fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x00008bfe, 0xfffc0039, 0xffc91ff0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x000000c5, 0xffdfff60, 0x00000006, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffc0, 0x7fffffff, 0xffffffc0, 0xff6be01f, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x018d0143, 0xb9740aeb, 0x018d0143, 0xb92e55b3, 0x1f1800ee, 0x3fe00055, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffc0, 0x7fffffff, 0xf43f91ad, 0x7ffffffa, 0xff121781, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000048, 0x00000f0f, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x0001397d, 0x8018a206, 0x0001397d, 0x7200903b, 0x7ffb3fc0, 0xff801c71, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xfff48000, 0x0f088000, 0xffe90000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x0000008d, 0xffc0ffff, 0x01cdfffb, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xfffb85ad, 0x0003b6db, 0xfff0f801, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xfffff0e5, 0xdeafdd22, 0xfffff0e5, 0xdebb4c1d, 0x00ff00b7, 0xf007fffc, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffcd5, 0xffffffff, 0xfff8fce3, 0x0000000e, 0x7ffffe35, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000344, 0xc75e94f9, 0x00000344, 0xcf5a6511, 0x00000ff8, 0x8003ff08, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffecccd, 0xedc66666, 0x00030000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x01f1d0d3, 0x00000000, 0x01f1d0d3, 0x000c7fff, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xb6db6db6, 0xdb6db6db, 0xb6db6db6, 0xdb662863, 0xe38efff4, 0xfffcffbc, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x24924924, 0x92492492, 0x24924924, 0x924c2290, 0x80000006, 0xd5ab0004, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xf1ca0491, 0x71c7ffed, 0xf7131ff8, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x0000003e, 0x57f1e1af, 0x0000003e, 0x3d3ff722, 0x7fff7ffe, 0xe00f5555, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x07ffffff, 0xfffffffe, 0x08000000, 0x00037fe9, 0x00000007, 0x80037ffc, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x0000003f, 0x80000000, 0x1000c040, 0xe003c001, 0x7fff8000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xffffa0a8, 0x00000000, 0x00058408, 0x000cf1b0, 0xfffe8000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x55558000, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x8e38e38e, 0x38e38e38, 0x8e38e38e, 0x78a38e38, 0x7f800000, 0x1ffe8000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x0bd37f9c, 0x1743ff9c, 0x7fff8000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xf0000000, 0x00000007, 0xf0000000, 0x002dffab, 0x2492fffa, 0x0000febe, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x0000000f, 0x7fffffff, 0xe0008011, 0xc0030002, 0x7fff8000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xffa00000, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x1fffffff, 0xfffffffe, 0x1fffffff, 0xfffffffe, 0x00000000, 0x00010025, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xdb6db6db, 0x6db6db6d, 0xdb6db6db, 0x6e0f8563, 0x1c717fff, 0xff50fffa, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000e6c, 0x2cf185fa, 0x00000e6b, 0xf9be193c, 0x00059999, 0x8000fc26, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000001, 0x00000000, 0x00000e15, 0x0385e003, 0x0000fffc, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x0000008d, 0x00050001, 0x0004ffe3, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x2007d466, 0xffa3c007, 0x7fff1fe0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfc04feee, 0x00113fc0, 0x0ffc0001, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x3a19a389, 0x00000000, 0x3a21f266, 0x1ffcf007, 0x0005ffc0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffff7f, 0xb24c0ece, 0xffffff7f, 0xb24c0ece, 0x3ff0ffff, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xffe96e44, 0xffffffff, 0xfbe92ea4, 0x1ff08000, 0xf8010006, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffe87, 0xffffffff, 0xd00b7e87, 0x80001ff8, 0x8000801f, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x0fffffff, 0xfffffff8, 0x10000000, 0x1c71c714, 0x003dc71c, 0x7fff0000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x0069a7ce, 0x1c71fff0, 0x8004fc01, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00338000, 0x0067ffff, 0x00008000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffffc, 0x00000000, 0x006901e6, 0xfffefcba, 0x1fe05555, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xfffffffd, 0x00000000, 0x006adb6d, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000102, 0xffffffff, 0xf8dfbebb, 0x7fff07fe, 0xf3570f0b, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf000ffff, 0x0001e001, 0x80008000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffff7fd, 0xffffffff, 0xfffff7fd, 0x00000000, 0x00000623, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x03726678, 0x379f21d3, 0x03726678, 0x379f21d3, 0x00008000, 0x00007fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffff0000, 0xffff0000, 0xffff0000, 0xfffe8000, 0x00008000, 0xfffffff0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xeffd0000, 0x8000fff9, 0x8000e001, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x03329667, 0x00003333, 0xf0038002, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x000f1a6a, 0xc2980006, 0x005d003f, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x8e38e38e, 0x38e38e38, 0x8e38e38e, 0x38e2e692, 0x0000c81e, 0xfffde57d, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x0f0ffffc, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xc000f729, 0x800202f2, 0x00038000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffff0, 0xffffffff, 0xff577ea0, 0xfffffe08, 0xaaaa8000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x99999999, 0x99999999, 0x99999999, 0x99999999, 0x49240000, 0xe1d50000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffff12, 0x1b257b7a, 0xffffff12, 0x1b35fb5a, 0xffe08000, 0x00017fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xfffff8d0, 0x68ef9c7c, 0xfffff8d0, 0x68ef9c7c, 0x80000000, 0x80000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xfffffffb, 0x469d3791, 0xfffffffb, 0x4356b7e2, 0x3fe00e07, 0x3bb90003, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00000252, 0x0000fffa, 0x0063ff80, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x33333333, 0x33333333, 0x33333333, 0x4cd2b327, 0x80007fff, 0xfff43333, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x99999999, 0x99999999, 0x99999999, 0xd97f9819, 0x3ff07fc0, 0x8000ffe8, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xd2e75f8b, 0xffffffff, 0xefb033d6, 0x39cb0000, 0x0079807f, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xff1f0000, 0x00038000, 0xfe3e0000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000002, 0x00000000, 0x0056f258, 0x00020185, 0xc71cc00f, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xffc92498, 0xfff8ff80, 0x92490003, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffffb, 0xffffffff, 0xf80478ac, 0xff95f007, 0x80000253, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000007, 0xffffffff, 0xf0150007, 0x00008000, 0xe02a0194, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x0000006d, 0x3fa9cd30, 0x0000006d, 0x3fadf504, 0xfff10048, 0xfe8e3ffc, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000001, 0x7fffffff, 0xfffe0001, 0x8000fffe, 0x8000fffe, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x0ac9c25a, 0x00000000, 0x0acdfa0d, 0xfb490000, 0x001b00e5, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffff65, 0xd48b4c13, 0xffffff65, 0xd0d74c04, 0xf8897fff, 0xfff18000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x7ffffffd, 0x7fff0003, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xffffffe0, 0xffffffff, 0xfd7e67fc, 0x0000f001, 0xd7e4fffa, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x0000000a, 0xffffffff, 0xffccc1b4, 0xfff83ffe, 0x00cd0002, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xf51683fe, 0xaaaa3ffc, 0x00ffe003, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x07fdffff, 0x0ffc0000, 0xfffd8000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf8055f45, 0xc01ff003, 0xc01ff003, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffe9c56, 0xffffffff, 0xfffe9c56, 0x80000000, 0xf8010000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xff1a3358, 0x0f56f008, 0x00000efc, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x92492492, 0x49249249, 0x92492492, 0x334074ed, 0xdca67fff, 0x3ffc4924, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x0000007f, 0x7fffffff, 0xfff1c0f8, 0xe0010007, 0xc001ff80, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xfffe945c, 0xb2ef1065, 0xfffe945c, 0xb2ef13e5, 0xfc01ff80, 0x00070000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x33333333, 0x33333333, 0x33333333, 0x33346b4b, 0xfffbfff8, 0xff2b3fc0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xfff85a2d, 0x00e23275, 0xfff85a2d, 0x00e23275, 0xe001002e, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0xffffffff, 0xc0004017, 0x3ff87fff, 0x7fff0003, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xfffffffe, 0xb0add741, 0xfffffffe, 0xa54325fb, 0x0eda07fc, 0x7ff87fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffdb, 0xfcbd2611, 0xffffffdb, 0xc98a7e58, 0x7ffffffb, 0xfd2d6666, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x80000000, 0x00007e92, 0xfff50001, 0x8003ffdf, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000006, 0xffffffff, 0xff800506, 0xf8038005, 0xff000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fff3fe0, 0x00000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xc000fffe, 0x7fff0000, 0x00057fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x01df0e8b, 0xff807fff, 0xfc8b4924, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xfff8aae2, 0x83eb47c3, 0xfff8aae2, 0x806ea5f2, 0xf903e01f, 0x000f8000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0x0011373f, 0xffbc3fc0, 0xffff3fe0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xfffffffd, 0xffffffff, 0xffff7e6e, 0xffff0051, 0x00058006, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf8eea9b8, 0xf0013352, 0x00077ffa, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffff, 0xffffffff, 0xffffffff, 0xf99c800b, 0xcccc0000, 0xc01fe00f, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x000000ff, 0x00000000, 0x7fc000ff, 0x80007fc0, 0x80007fc0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffff39ba, 0xe003001b, 0x03cafffd, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00fe65fc, 0x4cf3252d, 0x00fe65fc, 0x6cd36576, 0xc03f000a, 0xffff7fff, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x80000000, 0x00000000, 0x7fffffff, 0xc0000000, 0x80008000, 0x80000000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffff9dad, 0x9b20bcbf, 0xffff9dad, 0xb4b21653, 0x3ff00004, 0x7fff9999, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x000844f6, 0xffc07fff, 0xfff60d14, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffcd70, 0x878ab614, 0xffffcd70, 0xc78cb614, 0x00057fff, 0x80008000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xfffff607, 0x4e30d872, 0xfffff607, 0x4e301834, 0x00ff7fff, 0x0002ffc0, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xffffffbd, 0xc6f0c624, 0xffffffbd, 0xc6ef49a4, 0x00070004, 0x80007f80, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000000, 0x00000000, 0x12380004, 0x1c713ffc, 0xf0018000, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0xfe986b7c, 0xe5856df2, 0xfe986b7c, 0xe18775ee, 0x000007fc, 0x7fff0001, 0x0, 0x0 - dspck_astio dpsx.w.ph, 0x00000000, 0x00000001, 0x00000000, 0x3ffffffd, 0x7ffffffe, 0x3ffe8000, 0x0, 0x0 - - writemsg "[49] Test dpaqx_s.w.ph" - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x05946d31, 0xdb6d8000, 0xfa51005d, 0x00000000, 0x00000000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0xffff2cd6, 0xf91307af, 0xffff2cd6, 0xf8d4c631, 0x8000007f, 0xc03fffff, 0x00000000, 0x00000000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x6db6db6d, 0xb6db6db6, 0x6db6db6d, 0x5f1df8de, 0xdb6d7fff, 0xcccc7fe0, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x7fbc03bf, 0x7ff8ffc5, 0x7ff87fff, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xffffffe8, 0xfffcff1f, 0x00000003, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xffef9dc8, 0xf995fd15, 0x010300d1, 0x00000000, 0x00000000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x24924924, 0x92492492, 0x24924924, 0x92502496, 0x7ffefff8, 0x8000ffff, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xe0000000, 0x00000001, 0xe0000000, 0x000059b9, 0xfff4e00f, 0x0000fc43, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff30fea0, 0x00300000, 0x7fff7fff, 0x00000000, 0x00000000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00994ab2, 0xfe260517, 0x0f0f0000, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x07ffffff, 0xfffffffc, 0x07ffffff, 0xffb4fffc, 0x0007004b, 0x80000000, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf2db9dbb, 0x00007ffa, 0xf2dbfffd, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x6db6db6d, 0xb6db6db6, 0x6db6db6d, 0xb6db6db6, 0x00000000, 0x000f8001, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x7ffe0011, 0x7ffffffe, 0xfffc7fff, 0x00000000, 0x00000000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xfff60014, 0x00007fff, 0xfff60004, 0x00000000, 0x00000000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x8064ff35, 0x00658000, 0x80007fff, 0x00000000, 0x00020000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0xfe5f10c3, 0xe760a390, 0xfe5f10c3, 0xeb23d032, 0xde5f7fff, 0x03bffff0, 0x00020000, 0x00020000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xfffffffe, 0x00000000, 0x6465fffe, 0x80008000, 0xaaaaf0f0, 0x00020000, 0x00020000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x0b951e8a, 0x00db3fe0, 0x157f7fff, 0x00030000, 0x00030000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x36db9249, 0x80007fff, 0xb6db8000, 0x00020000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xff147f80, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4924c71c, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x04684d7d, 0x07fe7fff, 0x0377ff25, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xffd90040, 0x7fff8000, 0x0007ffe0, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x000000cf, 0x9a5c8bed, 0x000000cf, 0x7f3b824f, 0x1ff0003f, 0x7fff9249, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0fffffff, 0xfffffffe, 0x10000000, 0x0001ffbe, 0x00100000, 0xfff80ffe, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x552bffe7, 0xfffdaaaa, 0x803ffff6, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffa300b9, 0x7fff8001, 0x0000ffa3, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xfffa000c, 0x00006db6, 0xfff90000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000004, 0x00000000, 0x003f4342, 0xffffff04, 0xe003db6d, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x0fffffff, 0xfffffff8, 0x10000000, 0x7ffee4c6, 0x80010001, 0xf2678000, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x6304bc88, 0x00000000, 0x62f35b60, 0x8000f007, 0x0234ffcb, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xffffffe8, 0xffffffff, 0xdb75dd20, 0x7fe00006, 0xfa0adb6d, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x000f1c9c, 0xffe0ffda, 0x38e38000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000003, 0xffffffff, 0xa5fadb71, 0x80009249, 0x7fffec4f, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x0000000f, 0xffffffff, 0xfffff905, 0x00000035, 0xffef7fff, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x3fffffff, 0xffffffe0, 0x3fffffff, 0xfffdffe0, 0x01ac0002, 0x80000000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xedb82494, 0x80006db6, 0x7fff7ffd, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xffffffff, 0xfffffffb, 0x00000000, 0x0007fffb, 0x0000fff8, 0x80007fff, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x3fffffff, 0xfffffff8, 0x3fffffff, 0xfffffff8, 0x7fff8000, 0x00000000, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xfc000000, 0x00000001, 0xfc000000, 0x3ff10001, 0x00008000, 0xc00f0005, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xff2a4acf, 0xde8c3ffc, 0x24924924, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x0001ffec, 0x0002fffc, 0x00007ffb, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x000002aa, 0x00000000, 0x000401aa, 0xfffffc01, 0xff800000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x80000000, 0x00000002, 0x80000000, 0x000205b4, 0x0000cc3b, 0xfffb0000, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x00000047, 0x1ff00024, 0x00010000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x0012900a, 0x0e63ded6, 0x0012900a, 0x0e61ded6, 0x00000002, 0x8000001c, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xfff9b250, 0xff80fe1b, 0xfff8066c, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x33333333, 0x33333333, 0x33333332, 0xb3353237, 0x7fffc03f, 0xfffe8000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x0000000f, 0x00007fff, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xf8000000, 0x00000001, 0xf7ffffff, 0x00210001, 0x7fe07fff, 0x80008000, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x38e30006, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000788, 0x9cf9f5fb, 0x00000788, 0x9cf9f5c3, 0x0000fffe, 0x000e8001, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0xf8000000, 0x00000001, 0xf8000000, 0x0046fd3f, 0x00300047, 0x7ff90003, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000e003, 0x00000000, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x801fffc1, 0x7fff0000, 0xcccc801f, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xfffffffe, 0x7fffffff, 0xf883ce44, 0x0ff8ff21, 0xb6dbc003, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xff3dec21, 0x0611807f, 0x0000f001, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xfffffff8, 0x7fffffff, 0xf7d91fde, 0x9249f803, 0x7ffe0031, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xffffff00, 0x00000000, 0x3ff0ff00, 0x00008000, 0xc00fc003, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xffe241e9, 0xffffffff, 0xffe56f15, 0x80000f0f, 0x000afffe, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xffffff88, 0x0000fffc, 0x000f0065, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000004, 0xffffffff, 0x7805bf8c, 0x7fffe00f, 0x1ffc8000, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xc0000000, 0x00000007, 0xbfffffff, 0x70cef337, 0x80007ff8, 0xf0cd7fff, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00000f80, 0xff08fffc, 0x0000fff8, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xffffffff, 0xfffffff7, 0xffffffff, 0xe78c30e3, 0xe78afffe, 0x80007fff, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x24924924, 0x92492492, 0x24924924, 0x1249e496, 0x8000ffff, 0x1ffe7fff, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0x80010000, 0xe0018000, 0x7fff0000, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x7f7e89b7, 0x7ffffea5, 0x002c7f80, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xe0011c71, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xfffffffa, 0x3271a679, 0xfffffff9, 0xb2aea679, 0x80008000, 0x00037fc0, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00084bde, 0xf8019999, 0xffffff88, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xffffff8e, 0xffffffff, 0xf0071f80, 0x056b7fff, 0xf0070000, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x7e333a5f, 0x0ffe7ffa, 0x8000f168, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000001, 0xffffffff, 0xfc41ff01, 0xff808000, 0x03fec001, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000018, 0xffffffff, 0xf6a49bf0, 0x8000fe99, 0xcccc09eb, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0xe0000000, 0x00000007, 0xe0000000, 0x000183b7, 0x00037fff, 0x000115f3, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0fffffff, 0xfffffffc, 0x0fffffff, 0xfffffffc, 0x0000fffd, 0x00000000, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x0000002f, 0xfffc8000, 0x0000fffa, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xffffff32, 0x00000000, 0x00016ed6, 0x00170000, 0xf8e007fe, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0x1585a691, 0xfffffffe, 0x95a72df3, 0x7ffff0f0, 0xfff3801f, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x1fffffff, 0xfffffffc, 0x20000000, 0x000000ac, 0x3ff00058, 0x00010000, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0xdcbc91a8, 0x8b369f8f, 0xdcbc91a8, 0x8b3edd7f, 0xfc010000, 0x2d2cfef8, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xfffa0000, 0x80007fff, 0x00000006, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00003f5b, 0x0f60cd1e, 0x00003f5b, 0x0f60cd1e, 0x00008000, 0x00008000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x000000ba, 0xfffeffe1, 0xfffd0000, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xffffffe0, 0xffffffff, 0xf007ffe0, 0x0ff80006, 0x00008000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000005, 0x00000000, 0x44840005, 0x8000e00f, 0x8000db6d, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000001, 0xd93ec0f4, 0x00000001, 0xd91fc0f4, 0x7ffe8000, 0x001f0000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xc0257fb6, 0x7fff7fff, 0x001ec007, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffb, 0x00000000, 0x0000fff7, 0x8002ff4e, 0x0000ffff, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x0fffffff, 0xfffffffe, 0x10000000, 0x7f69b805, 0x49248000, 0x8000fef9, 0x000a0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xffffffff, 0x4ecd37bf, 0xfffffffe, 0xdd5e386f, 0xff7c8000, 0x71c7aaaa, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x00b1bb1d, 0x07407fff, 0x00b1000d, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xeb1ac922, 0xb6db0005, 0x0fef2492, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xa75e1a0c, 0xfca5ff86, 0xf0f07ffd, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xc0000000, 0x0000000f, 0xc0000000, 0x2493020f, 0x8000fff8, 0xffe0db6d, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000007, 0xffffffff, 0xffe5ff3d, 0xffe57f80, 0x00017fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x1ffbc008, 0x00007fff, 0x1ffcffff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x09f1ffe0, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x0000007f, 0x00000000, 0x000333bf, 0xfff8e001, 0x0000cccc, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x3fffffff, 0xfffffffc, 0x3fffffff, 0xff6b3298, 0xfffffb59, 0x0ffe0000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x0000001f, 0x80000000, 0x3ffb8027, 0x00007fff, 0x3ffc0000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0x83558304, 0xffff6db6, 0x801f0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffbf0e92, 0xd352c2a3, 0xffbf0e92, 0xd34bc2b1, 0x7fff0000, 0x0000fff9, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0xd2690abc, 0x00000000, 0x526a2aba, 0x8000ffff, 0xf0017fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xff71ddae, 0x00000000, 0x32a47700, 0x8006ffff, 0x801fcccc, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x2c2db31a, 0x00000000, 0x1e8f2012, 0x8000e001, 0x367c0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xfffffff8, 0x167a2b30, 0xfffffff8, 0x167b47a4, 0xfffbf001, 0x0000e38e, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaa2, 0x00b60004, 0xffff0000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xfffffffb, 0xffffffff, 0x800ec6f5, 0x001f8000, 0x7fff38e3, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xfffbf808, 0xfffc0004, 0xff007fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffeca179, 0x9c0defe7, 0xffeca179, 0xa328844f, 0xfffd38e3, 0x0ffc00c0, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xfffffffa, 0x7fffffff, 0xfc00dfee, 0x0000e003, 0x0ffe0006, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0xfffffe6e, 0x201ba127, 0xfffffe6d, 0xa014a127, 0x7fff0008, 0x80008000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xfe4f6b2e, 0xb6db0000, 0x999902f5, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x0000007f, 0x00000000, 0x0ffee081, 0x7fff0ffe, 0x7fff0001, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffe, 0xffffffff, 0x8004fff6, 0xc0078004, 0x7fff0000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x0fffffff, 0xfffffff8, 0x10000000, 0x4924fff8, 0x7fc08000, 0xb6db0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x1863fffe, 0x92498003, 0x55558000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x000026ac, 0x00000006, 0x03398000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x1fffffff, 0xfffffffe, 0x20000000, 0x7ffe0120, 0x7ffffffc, 0xffdc7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0xffc07f80, 0x00008000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xf0000000, 0x00000001, 0xefffffff, 0xfff80011, 0x0000fff8, 0x7fff8000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x3fffffff, 0xfffffffc, 0x3fffffff, 0xfffffffc, 0x00000000, 0xfffeffe0, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000007, 0xffffffff, 0xffffffe7, 0x0000fff8, 0x000207a4, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xff7c0000, 0x00840000, 0x00698000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x0000007f, 0x80000000, 0x00000043, 0x031cfffa, 0x00050000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xf8704678, 0xffffffff, 0xf8704678, 0xf058800f, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x80000000, 0x0000007f, 0x7fffffff, 0xfff324df, 0xfffe0026, 0xdb6d7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x58313cef, 0x49241ffc, 0xfffb7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xfffffffc, 0x9321c3c0, 0xfffffffc, 0x92cbc46c, 0x0000ffaa, 0x7ffffffb, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000003, 0x00000000, 0x00015555, 0x000038e3, 0x00037f80, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xfff40401, 0x00000000, 0x0dc7e859, 0xf5177fff, 0x02eb8001, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xffe67a34, 0x001a06ca, 0x00098000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0xe0000000, 0x00000001, 0xe0000000, 0x80000000, 0x80000000, 0x80048000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x0000003f, 0x7fffffff, 0x8009002f, 0x7fff7fff, 0x00088000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x1fff0000, 0x8000fffa, 0x8000e007, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1ce2c63c, 0xffff7fff, 0x00708000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xff2b63f0, 0xff8271c7, 0xff10ff44, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf266fffb, 0x8000fffe, 0x00010d99, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x07c5007f, 0xf7fbffc0, 0x7fff8000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x7ffe0002, 0x00007fff, 0x7fff7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xfffffff2, 0xffffffff, 0xffffff2a, 0x0001fffc, 0x00190000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x33333333, 0x33333333, 0x33333333, 0xb3190b24, 0x8000029b, 0xfafb8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x3fffffff, 0xfffffff0, 0x3fffffff, 0xfffe0004, 0x7fffffff, 0xfff8fffe, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x3fffffff, 0xfffffff0, 0x40000000, 0x0251fb50, 0x80007fff, 0x0250fffe, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00cf4fc0, 0x55a72693, 0x00cf4fc0, 0x55b72613, 0x00100000, 0x00007ffc, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0xc71c0000, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x3fa20000, 0xc01f8000, 0x003f8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0fffffff, 0xfffffff8, 0x10000000, 0x001087b0, 0x02123fc0, 0x000003fe, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xffffffff, 0xfff466a6, 0x00000000, 0x198d19da, 0x00013ffe, 0x33330000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x0000000f, 0xffffffff, 0xffff000f, 0x80007fff, 0x00000001, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0xffffe351, 0x19cff3df, 0xffffe351, 0x1a35d2c3, 0xffe15555, 0x0093f003, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00034480, 0x0000e5dc, 0xfff07fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xfffffc7c, 0x3136be68, 0xfffffc7c, 0x4f2db500, 0xc00f8000, 0x0008c3f4, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x0001e5cd, 0x994d42cb, 0x0001e5cd, 0x994d42cb, 0x80000000, 0x80000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x03ffffff, 0xfffffffe, 0x03ffffff, 0xf7ff0ff8, 0x7fff0004, 0x8000f803, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0xffffffff, 0xfff8ebaa, 0xffffffff, 0x8012dda0, 0x801ff9e6, 0x007f7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x1175dd14, 0x7fff71c7, 0x00001176, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000017, 0xc417ec8c, 0x00000017, 0xc43cec90, 0xfffeffd9, 0x80007fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00014957, 0xb94c731c, 0x00014957, 0xb9501dca, 0x0001e38e, 0xfff47fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x1fffffff, 0xfffffff0, 0x20000000, 0x006122d0, 0xff8f097a, 0x0563059e, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00229851, 0x00000000, 0x00229851, 0x00000e45, 0x00000015, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x6db6db6d, 0xb6db6db6, 0x6db6db6d, 0xb6db6db6, 0x003f000e, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffc0, 0x7fffffff, 0xfff9bfc6, 0xffff9249, 0x00071ffc, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x00077fdf, 0xe0018002, 0x1ff88000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x2aaad1ad, 0x00000000, 0x2983380d, 0x66668000, 0x012e0008, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0070000, 0xe0070000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xfed3701a, 0x7fffdb6d, 0xfffbfed2, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0xffffffff, 0xfffff372, 0xffffffff, 0xbdbd59da, 0x7fff0f0f, 0x8000cccc, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffc, 0xffffffff, 0xe7e90c14, 0xe3e50002, 0x001f6db6, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffff9, 0x7fffffff, 0xf84bacab, 0x71c7ff97, 0x8000f6df, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x000106ee, 0xa5857119, 0x000106ee, 0x8589b0fb, 0xe003fff8, 0x00007ffb, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x3ff70020, 0x80007fff, 0x7ff03ff8, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x03ffffff, 0xfffffffe, 0x03ffffff, 0xfffa282a, 0x001800a9, 0x001ee003, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000013, 0xffffffff, 0xc2f00013, 0x8000fd50, 0x80003fc0, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xc00bfff0, 0x80008001, 0xfff83ffc, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xfffffffd, 0x7fffffff, 0xfffffffd, 0x80007fff, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xe03a3522, 0xe00f002b, 0x7fe07fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x8000003f, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffffe44, 0x00000000, 0x81c1fabe, 0x0ffc7fff, 0x71c77fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x801ffff8, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfff607c0, 0xffe0fff0, 0x000027e1, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xcbec8822, 0x7ffff003, 0xffffcbec, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfffc0000, 0x0004fffe, 0x00008000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000005, 0x00000000, 0x00000005, 0x7fff0000, 0x7fff0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xfffffcec, 0xffffffff, 0xd821fcec, 0x80008000, 0x1fe007fe, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xfc0b2f8e, 0x51a4180a, 0xfc0b2f8e, 0x51a4055a, 0x005cfff3, 0x005cfff3, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffe, 0x01058e38, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x11440c4e, 0x00037ff9, 0x1145ffae, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x1fffffff, 0xfffffff8, 0x20000000, 0x000198d8, 0xfff08000, 0xfffe0339, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xfffff13e, 0x47048cc4, 0xfffff13e, 0x06a28da8, 0x80007fff, 0xff8e3ff0, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffa017, 0xfc010006, 0xfc010006, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x80000000, 0x00000004, 0x7fffffff, 0xfffd000a, 0x7fff0000, 0x8004fffd, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0x80010000, 0x800f8000, 0x7fff0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffff8, 0x80000000, 0x00f8fe06, 0x7fff0000, 0x7fff00f9, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x0006ffe4, 0xfff900ff, 0x00008002, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x666d38ef, 0x8e389999, 0x8000fff9, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xfffffffc, 0x80000000, 0x01cbb22e, 0x03e9807f, 0x00273fc0, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x0031b553, 0xffffffff, 0x8033b551, 0x00008001, 0x7fff0003, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x0000a24f, 0x8215c333, 0x0000a24f, 0xb8654371, 0x80008001, 0xc01f0991, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00d7d86e, 0xc845e3f6, 0x00d7d86e, 0xc845500e, 0xfff6ffff, 0x3ffe00ff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xf0000000, 0x00000007, 0xefffffff, 0xffe40727, 0xff8e8000, 0x001cfff8, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xfffa49e9, 0x7af19a01, 0xfffa49e9, 0x7ae0ff5d, 0xfe867fff, 0xfffe04f2, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x000003fe, 0x00000000, 0x000003fe, 0x00000000, 0xffdf0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x0006ac2f, 0xffffffff, 0xe015aa6f, 0x7fe0ff17, 0x0000e007, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x3fffffff, 0xfffffffc, 0x40000000, 0x7ff9588a, 0x026d8002, 0x80060047, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x80030000, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xffffffe4, 0x00000002, 0xfff97ffb, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x10657ba7, 0xf003068b, 0x07fc8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0xd66fd94c, 0x00000000, 0xd65eec6c, 0xffbcffef, 0x7f80fffc, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0xf0000000, 0x00000007, 0xf0000000, 0x00000007, 0x00007fe0, 0x00007fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x71c71c71, 0xc71c71c7, 0x71c71c71, 0xc73871c7, 0x8000ffe5, 0x8000ffff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xef13ffff, 0x80008000, 0xf0f01ffc, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xfffd8000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0fffffff, 0xfffffffc, 0x0fffffff, 0xfffffffc, 0x80017fff, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00000000, 0x0004fa09, 0x00000000, 0x00d472c5, 0xe00fff40, 0x8000ffc2, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x000019d6, 0x25d2e61a, 0x000019d6, 0x25d2e61a, 0x00000000, 0x007f0001, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffb, 0xffffffff, 0xfffffffb, 0x00000000, 0x00008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xfc004d44, 0xfffde00f, 0x0ffc6db6, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xce3fffff, 0x8000fe8d, 0x80003333, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x00000002, 0x77029de6, 0x00000002, 0x77029de6, 0x0000ffb5, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xfffff9e6, 0xd57b1bc1, 0xfffff9e6, 0xc633f18f, 0x1ff0fd49, 0xe01fc00f, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000007, 0x00000000, 0x00000007, 0x00000000, 0xfd7ef003, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x00001c0d, 0xdcaa4259, 0x00001c0d, 0xdcbc4235, 0x7fff0009, 0x7fff0009, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xffffff80, 0x7fffffff, 0x8000ff80, 0x80000000, 0x7fff7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x80000000, 0x00000002, 0x7fffffff, 0xfa180002, 0x800001d1, 0x000005e8, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffe0, 0x80000000, 0x04def622, 0x7fe07fff, 0x04df0000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffbee6c, 0x00000000, 0x3ff8ee6c, 0x80000000, 0xf001c003, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0x8002b414, 0xffc17fff, 0x8000fc8a, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0xffffffff, 0xff546bd0, 0xffffffff, 0xff586bd0, 0xf003fffc, 0x80000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x24924924, 0x92492492, 0x24924924, 0x92492492, 0xf5e80000, 0x80000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffffb, 0x7fffffff, 0xf5a7ffff, 0x7fff0a56, 0x8000fffe, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000528, 0xffffffff, 0xff72e8f2, 0xf82ff932, 0x7fff9999, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00dae090, 0xf0f0ffff, 0xfff8f8bc, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x0000ffff, 0x0000ffff, 0x0000fffe, 0xffb107ff, 0xffd03ffc, 0xff008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0fffffff, 0xfffffffe, 0x0fffffff, 0x8004fffe, 0x8000fffc, 0x80007fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffd, 0xffffffff, 0xaaaaaaa9, 0x7fff8000, 0x0000aaaa, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x0fffffff, 0xfffffff8, 0x10000000, 0x000dffea, 0x00000015, 0x55553c28, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x24f94f56, 0x8000fd5b, 0xfff1db07, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac3, 0x80000000, 0x0000003f, 0x7fffffff, 0xf9082a17, 0x00027ffd, 0xf9067fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x0a7f4d02, 0xdb6dc03f, 0xffe8db6d, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac0, 0x80000000, 0x0000003f, 0x7fffffff, 0xffc23e3f, 0x000f7f80, 0xffc20000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xf0000000, 0x00000003, 0xefffffff, 0xfff471cd, 0xfff3e186, 0x000071c7, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffc03fe, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffff8, 0x80000000, 0x7f7efdf8, 0x7f80ff80, 0x00037fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0xffffffff, 0xfffe99c9, 0xffffffff, 0xfffe99c9, 0x00000000, 0x0000f801, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x1872bff8, 0xe38e3ffc, 0xf8018000, 0x000f0000, 0x000f0000 - - writemsg "[50] Test dpaqx_sa.w.ph" - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xe0000003, 0xffffffff, 0xa57e0003, 0x80008000, 0xcccc6db6, 0x00000000, 0x00000000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xf88d618b, 0xffffffff, 0xf887a56b, 0xfffcfe2e, 0x007a7fff, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x800f1c6e, 0x000071c7, 0x00118002, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0xbfef8020, 0x00007fff, 0x3ff0ffff, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x000140d3, 0xffffffff, 0xfffe40d9, 0x7fff6666, 0x0000fffd, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xe5e57930, 0xffffffff, 0xe5de793e, 0x00007fff, 0xfff90000, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x07361af3, 0x00000000, 0x07501abf, 0x7fff0018, 0x7fff0002, 0x00010000, 0x00010000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x09fa7ff0, 0x80008006, 0x00010000, 0x00030000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00008010, 0xfff87ff8, 0x000107fe, 0x00030000, 0x00030000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x324df2ec, 0x00000000, 0x3257f2d8, 0x00007fff, 0x000a3ffc, 0x00030000, 0x00030000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffffe, 0x00000000, 0x0001ffe2, 0x0000fffe, 0x80070000, 0x00020000, 0x00020000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x3330666a, 0x7fff3ffe, 0x6666ffff, 0x00020000, 0x00020000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xffffffff, 0xffffffff, 0xc04ef87f, 0xc00ffff1, 0xffc07f80, 0x00020000, 0x00020000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000032, 0x0000fffb, 0xfffb07e8, 0x00020000, 0x00020000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xecf8827c, 0xffffffff, 0xecf87bdc, 0xffc0ffe8, 0xfffe000e, 0x00020000, 0x00020000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x01ccab39, 0x00000000, 0x01cca86d, 0xe38efffe, 0x00b30000, 0x00020000, 0x00020000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80030000, 0x7f800000, 0x00030000, 0x00030000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x38e38e38, 0x00000000, 0x4a5d7e40, 0xf6827fff, 0x07fc8000, 0x00030000, 0x00030000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xffef0770, 0xf0078000, 0x00000088, 0x00030000, 0x00030000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7ffffffa, 0x00000000, 0x7fffffff, 0x33330008, 0x7f80fff9, 0x00030000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xe38ec00f, 0x3ff80007, 0x000a0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x38e38e38, 0x00000000, 0x393a8e38, 0x80008000, 0xffa90000, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffb, 0xffffffff, 0xfffffffb, 0x00390001, 0x00000000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x003fffff, 0x00008000, 0x7fc07fff, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0xc103fd0c, 0xc01f3ff8, 0x7ffbfde2, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0x0000f0f0, 0x00008004, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x0003f46b, 0xffffffff, 0xf0f4e62b, 0xfff47ff8, 0xf0f0fff8, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x02aa0000, 0x0000fd56, 0x80007ffa, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000003, 0xffffffff, 0x80000000, 0x0000003f, 0xfff3e003, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7ffffffb, 0x00000000, 0x7ffd4c1b, 0x0f0f0171, 0xff100000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffff7, 0x00000000, 0x7ffe391f, 0xffc97fff, 0x7fffff7b, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xfffffffe, 0x00000000, 0x69512d5b, 0x8000e951, 0x7fff8000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffc0, 0x00000000, 0x7fffffc0, 0x00000000, 0x000e0007, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffe, 0x00000000, 0x80028004, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000009, 0x00000000, 0x00000009, 0x8000c00f, 0x00000000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000004, 0xffffffff, 0x80000000, 0x8000fff8, 0x000f3ffe, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffff1, 0x00000000, 0x2492fff1, 0x8000c007, 0x0000db6d, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffb, 0x00000000, 0x0005c713, 0x8e380004, 0x7ffffffe, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xc14f86eb, 0xffffffff, 0xc46a80b5, 0x8000031b, 0x7fff0000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x80000005, 0xffffffff, 0x8021db55, 0x7fffb6db, 0xffed0017, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xff6e72de, 0xffffffff, 0xff74f100, 0x7fff000f, 0x3ff0ffff, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7fe0fff2, 0x00000000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xffaff986, 0xffffffff, 0xffb6f978, 0x00000007, 0x7fff0699, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x4001a6a9, 0xfffbc001, 0x7ffffc22, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffff0000, 0x80008000, 0x00010000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000003, 0xffffffff, 0xb3340003, 0x8000fafe, 0x0000cccc, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffff7, 0xffffffff, 0xfc9d31a7, 0xf274fff0, 0x00241ffe, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0882eefa, 0x7fff0087, 0x7fff07fc, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00003cf0, 0x00000000, 0x00003cf0, 0x00000000, 0xfffce007, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x7fa9c8d7, 0xfc7e8000, 0x80000c4a, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffff0, 0x00000000, 0x4920184c, 0x7fffe38e, 0x000f4924, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00004275, 0x00000000, 0x1fde1a81, 0x00051fe0, 0x7fffcf2e, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x935162de, 0xffd81351, 0x7ffffe48, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffffc, 0x00000000, 0x001c9f44, 0x1c71800f, 0xff8afe6e, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xdb6db6db, 0xffffffff, 0xdb7cb6bd, 0xffcf000f, 0x7fff0000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xc00f0005, 0x7fff3fe0, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x003b4548, 0x800001c6, 0x0406ffd3, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xc01f7fba, 0x00047fff, 0xc01fffff, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x3fc00111, 0x80007fff, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffd52, 0x00000000, 0x03fbfe52, 0x00007fc0, 0x03fe1169, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x006f440d, 0xffffffff, 0xf075647f, 0x7ffffffe, 0x3fe0f007, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7ffffffb, 0x00000000, 0x60102a55, 0xff758000, 0x1ff0ffd9, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x80008000, 0xfffbff3f, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x0f0f0f0f, 0x00000000, 0x0f0f0f0f, 0x00000000, 0x1f378000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffe62, 0xffffffff, 0xfffffe62, 0x00000000, 0xff327ff0, 0x000a0000, 0x000a0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x0000014c, 0x00000000, 0x7ffff125, 0x8000000d, 0xff618000, 0x000b0000, 0x000b0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x99999999, 0xffffffff, 0x80000000, 0xfb9f8000, 0x49240020, 0x000b0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xf0017fff, 0x7fffff80, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0021d94c, 0x2d3e005f, 0x07fc004f, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0076af00, 0x00000000, 0x0076af00, 0xfff90000, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7fffffff, 0x7ff98000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0x809bfe92, 0xffe4807f, 0x7fff8002, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xc0000003, 0xffffffff, 0xbfc02003, 0xffe07fc0, 0xffe07fc0, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00000000, 0xff70f25f, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000102, 0x00000000, 0x00d30cde, 0x80000045, 0x0016ff2d, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0xffffffff, 0x80000000, 0x0f0f8000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x80008000, 0x1fe00000, 0x000e0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xfffe0000, 0x005d7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fb6a85b, 0xfefffaa0, 0xfffe2492, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x000676a7, 0x00000000, 0x000676a7, 0xffff0000, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x8000e2a7, 0x80008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00001d74, 0x00000000, 0x00001e28, 0x00020000, 0x1ffc002d, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x8000007f, 0xffffffff, 0x8000007f, 0xfffc5555, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x1ffffff0, 0xffffffff, 0xb999fff0, 0x00ff6666, 0x80000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7ff5806b, 0x1fe0000f, 0xaaaafffe, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x55555555, 0x00000000, 0x7fffffff, 0x2fa80000, 0x80067fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x8000003f, 0x00000000, 0x0000003e, 0x80001ff0, 0x00008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xfbeefffd, 0x03fe8000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00725318, 0xff8cfa0b, 0x00248000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xe99839be, 0x7fffe997, 0x7ff90000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x0000ffe4, 0xffda8004, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x3ffffff8, 0x00000000, 0x3ffffff8, 0xf7a80000, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xfe9512f0, 0x00000000, 0x7f281558, 0x7ffffe84, 0xcccc7ffc, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xf0000003, 0xffffffff, 0xf002fffd, 0x7ffff0f0, 0x00000003, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xff5a604a, 0x00000000, 0x075abf9a, 0xf80316b8, 0x00138000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x0feb0400, 0x00057fc0, 0x0ff88000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00000000, 0x80006666, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0000264c, 0x8000fccf, 0xfffa0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xf9130dda, 0xf9130064, 0x00007fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xffe76797, 0xffffffff, 0xf7d68095, 0x3fe07fff, 0xf801ffdc, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000003, 0x00000000, 0x00125559, 0x3ffcfff9, 0xf9d30024, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xfffc3a24, 0x00000000, 0x0722b9a6, 0xc007f8de, 0x8000fff7, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x49249249, 0x00000000, 0x7fffffff, 0xc0070000, 0x80078000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x333d62fd, 0x00000000, 0x333d62fd, 0x00590000, 0x00590000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x55555555, 0xffffffff, 0xd5555557, 0x8000ffff, 0x7fff7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xe6458001, 0x00008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffe, 0x00000000, 0x073f8006, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0004819e, 0x00000000, 0x0004ba20, 0x1fe00009, 0xff990001, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xf8000003, 0xffffffff, 0xf7ff0007, 0xffffffff, 0x7fffffff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x000179e7, 0xffffffff, 0xf00979e7, 0x00008000, 0x0ff87fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0cbac798, 0x00000000, 0x0ca9c7ba, 0xfcc0ffef, 0x7fff0000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xe00ffff0, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x000053c0, 0x00000000, 0x000053c0, 0x00000000, 0x7ff9e007, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x0013ffd8, 0x7fff000a, 0x7fff000a, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000001, 0x00000000, 0x01320605, 0xffeafece, 0x8000ffdd, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0ffca012, 0xf0038000, 0x00008003, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0xffffffff, 0xffe38475, 0x8005f5f8, 0x01b87fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x03771ff0, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xff719f94, 0xffffffff, 0xffb09dc6, 0x003ffff8, 0x00157fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0000003f, 0x00000000, 0x0000003f, 0x00008000, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000fea, 0xffffffff, 0x80000000, 0x800003fa, 0xdb6d7f80, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x000001ae, 0xffffffff, 0xfffffbd2, 0x000f0000, 0xfff7ffce, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7fff0000, 0x7fff7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00001bec, 0x00000000, 0x003509d2, 0xc2e9fd33, 0xfc01ffc0, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffb6123, 0xffffffff, 0xa4936123, 0x2db48000, 0x2db48000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x80000000, 0x3ff8fc5f, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xffffc18d, 0xffffffff, 0xffffc18d, 0x00000000, 0x00007fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x80008000, 0xfc548000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffc5700, 0x00000000, 0x7fffffff, 0x7ffffa96, 0x80007ff8, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xf7c140e2, 0x00000000, 0x37bdc0ec, 0xc0010000, 0x001c8005, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xdb6db6db, 0xffffffff, 0xd53050eb, 0x0000c618, 0x0dcb7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x8005fff4, 0x7fff0003, 0x7fff0003, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x000001f0, 0xffffffff, 0xffffd108, 0x0c3a0000, 0xd148fffe, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000003, 0x00000000, 0x00000003, 0x00038001, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x6db6db6d, 0x00000000, 0x6db0d0dd, 0x000000ca, 0xfc2c1fe0, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x71132c51, 0xf803c00f, 0x1fe0f003, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff800fb, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xe49376e4, 0x71c77fff, 0x00ffe007, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x00008000, 0x0000f803, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00062f91, 0x00000000, 0x2003ef95, 0x7fff0000, 0x7fff1ffe, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffff0, 0x00000000, 0x01c5ca98, 0xc71cc71c, 0xfc010002, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xfedc1764, 0x00018000, 0x01240bb2, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xffffffff, 0x00000000, 0x0001d303, 0xfffa5555, 0x0000d915, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x0000ffff, 0x00000000, 0x71c61c73, 0x7fff38e3, 0x7fff38e3, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x81e9fc2c, 0x034f7fff, 0xff146db6, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00099362, 0xf626f007, 0xffc7ffe0, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0063eed7, 0x00000000, 0x0063eed7, 0x00000000, 0x7f800016, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xfe9b0f10, 0xffffffff, 0xfe9b7c54, 0x05680006, 0xc01f0051, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x8003ffe0, 0x0000fff0, 0xe0010000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffffc, 0xffffffff, 0xffb82e5c, 0x0000f8d0, 0x04ff0061, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffff883, 0x00000000, 0x7f8bf96a, 0x80007fff, 0xff8c8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000001, 0x00000000, 0x00009bed, 0xfcaa8000, 0xffff000f, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x1f505597, 0xffffffff, 0xbf4215b5, 0x1ff07fff, 0x80017fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0668bf07, 0xffffffff, 0xe670bef3, 0x00028000, 0x1ff8fffb, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xc0000003, 0xffffffff, 0xdff8ffc7, 0x8000fffe, 0x000fe007, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x0000003f, 0xffffffff, 0xfffb003f, 0x00000005, 0x8000fffb, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x046ccb93, 0x00000000, 0x04d4879b, 0xfffb03fe, 0x0cfe0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00ff00ff, 0x00000000, 0x00ff00ff, 0x00000000, 0x7f808003, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xf9bdee71, 0xffffffff, 0xf9bbee75, 0x00007fff, 0xfffecaf1, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00075732, 0x00000000, 0x00075732, 0x2d250000, 0x2d250000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000004, 0x00000000, 0x7fffffff, 0x80008000, 0x80008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x0000599b, 0x00000000, 0x0000599b, 0xfffc0000, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x740f882b, 0xf6468000, 0x02377ff9, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0x80000000, 0x00d37fff, 0x80008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffe0, 0x00000000, 0x7fffffe0, 0x80000000, 0x49240000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xffffffcc, 0xffffffff, 0xfff800cc, 0x8000fff8, 0x1ff00006, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xca06af80, 0x92497f80, 0x00ac3fc0, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xe0000001, 0xffffffff, 0xe0080001, 0xfffbfffd, 0x80008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffc66, 0xffffffff, 0xfffffc64, 0xc71cffff, 0x00010000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x49249249, 0xffffffff, 0xc92a923f, 0x80050000, 0xfffe7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x81fee00a, 0x0ffbfe01, 0x8000ffff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xffffff2c, 0xffffffff, 0xff319e1c, 0x00ce001f, 0xfe4e8005, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xc0000003, 0xffffffff, 0xdacb90c3, 0x80001b7a, 0x7ff000ab, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7fff000b, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xedeb1ff0, 0x00007fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xfff49a0a, 0x00000000, 0x0620a728, 0x0cbb7fff, 0x062c0001, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00140000, 0x000a8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x76b9124f, 0x001f7fff, 0xf69a7ffe, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0ffe8000, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xffece62f, 0xffffffff, 0xffe80297, 0x0011000b, 0xc71c0000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x8007ec08, 0x8000007f, 0x07fc0000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xffc80370, 0xfff8ffc8, 0x7ff80001, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x8001bf44, 0xfffd7fff, 0x0001e01f, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7ffffe5b, 0x0004000f, 0xfff20000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x002a6d51, 0xffffffff, 0xfdf90e8b, 0x078e3363, 0xfa81003b, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x78e463e9, 0xc71c0003, 0x000f0ffe, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x00000000, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0x8000001f, 0xffffffff, 0x8000001f, 0x0005db6d, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xffffff7e, 0xffffffff, 0xff56e35a, 0xc0036db6, 0x000f016c, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x6db6db6d, 0x00000000, 0x6fb5b2dd, 0x6db6012a, 0x6db6012a, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7ffffffe, 0x00000000, 0x7fffffff, 0x8000ff59, 0x06d38000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x1ffffff0, 0x00000000, 0x2c92b712, 0xe6d5f575, 0xfffec00f, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xfc01b6e0, 0x03fcfffc, 0x49248000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x24924924, 0x00000000, 0x24924924, 0x00000000, 0x000e7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7ffd07fc, 0x55551fe0, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00000000, 0x7ffff74a, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xffffcbb8, 0xffffffff, 0xc0eb49e2, 0x7fff0000, 0x006ac0eb, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x037df97e, 0xffffffff, 0x839df940, 0x801f7fff, 0x00007fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000047, 0x00000000, 0x000e002b, 0xfff98001, 0xfff98001, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xc0000003, 0xffffffff, 0xc0000003, 0x6666ffff, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00004b97, 0x00000000, 0x00004b97, 0x00000000, 0x00030111, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x92492492, 0xffffffff, 0x9249648a, 0x00000001, 0x1ffc0004, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xff00ff00, 0xffffffff, 0xff013ec2, 0x3ffcffff, 0xe01f0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xcfdad684, 0xffffffff, 0xcfdad6c0, 0x0000fffa, 0xfffbe493, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xffffe46d, 0xffffffff, 0xffffe44d, 0x00000002, 0xfff80004, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xffffcaaa, 0xffffffff, 0xfff9cbf2, 0xfff5ffc8, 0xff564924, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x0000000f, 0x00000000, 0x00000123, 0x00060000, 0xfe200017, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80010000, 0x80001ff0, 0x0000ffff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00003ff8, 0x0000807f, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xf0635618, 0x0ffeaaaa, 0xff6e8000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x0001d4b0, 0x00000000, 0x7fffffff, 0x7fff8005, 0xffeb7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x1c71c147, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x7ffffffb, 0x00000000, 0x7ffffffb, 0x00000000, 0x0000fffd, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xffffff80, 0x00000000, 0x0014ff56, 0x7fff0015, 0x7fff0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xf8000001, 0xffffffff, 0xc0fd0001, 0x00248000, 0x37030000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xd097284c, 0xffffffff, 0xd099284c, 0x80000000, 0x0000fffe, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7ffffffc, 0x00000000, 0x7fffffff, 0xfffcfff5, 0x0000fff6, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x00ff00ff, 0x00000000, 0x00ff00ff, 0xfc450000, 0xfff00000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x3148d154, 0x7fc07fff, 0x05162c49, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xdb6db6db, 0xffffffff, 0xc9a05e1f, 0x7fffc001, 0x03a9f007, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xc001c01f, 0x00003ffe, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffff251, 0xffffffff, 0xfffdf255, 0xfffe0000, 0xff9e7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0002c020, 0xfffdffff, 0x1ff08000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x0000000c, 0x00000000, 0x7ffeff96, 0x7ffffffc, 0xe00f7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xc000000f, 0xffffffff, 0xbf01000f, 0x00008000, 0x00ffaaaa, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00000509, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xdb6db6db, 0xffffffff, 0xdb611a63, 0x19bcfff4, 0x3fc0ffdf, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7fff8000, 0x00000002, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x6db6db6d, 0x00000000, 0x0002b6fb, 0x9249ffef, 0xf0f07fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffffd, 0xffffffff, 0xff00b9c5, 0x7ffb0003, 0x1d4cff00, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xffffc14b, 0x00000000, 0x38afe0d9, 0x38b4068f, 0x00c97fe0, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fa86da9, 0x004f000f, 0xb6db8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0x00000000, 0x1ffffff8, 0x00000000, 0x6924fdf8, 0x80000004, 0xffc0b6db, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0xc000001f, 0xffffffff, 0xbffe6d3f, 0x1ff80007, 0xfea0fffa, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x1ff8e001, 0x492400ff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0012ffda, 0x7fe07fff, 0x00130000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xffffffff, 0x00000000, 0x01cfffff, 0xff2e8000, 0xff028000, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x000007b4, 0x00000000, 0x30b05b14, 0x7ff93fc0, 0x7ffff0f0, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffe764c8, 0x0064e38e, 0x0000e081, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac3, 0xffffffff, 0xc0000003, 0xffffffff, 0xbf913411, 0xff929999, 0x00017fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0xffffffff, 0xf8000001, 0xffffffff, 0xf8000001, 0x00000000, 0x8005c71c, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xfffffe9f, 0xffb43fe0, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7fff7fff, 0x00000558, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xf82c0000, 0x1fe00000, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffc, 0x00000000, 0x00026ccc, 0x00560000, 0xfff7039c, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffc, 0xffffffff, 0xfe00efe0, 0x07fefe7b, 0x0000e007, 0x000f0000, 0x000f0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xf1ad5eb4, 0xffffffff, 0xf1ad5eb4, 0x00000000, 0x00057fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffff0, 0xffffffff, 0xfffffff8, 0xffff0000, 0x0000fffc, 0x000e0000, 0x000e0000 - dspckacc_astio dpaqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80eb0000, 0xff157fff, 0x00008000, 0x000e0000, 0x000e0000 - - writemsg "[51] Test dpsqx_s.w.ph" - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x2492b6da, 0xdb6d8000, 0x00007fff, 0x00000000, 0x00000000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xffffffc4, 0x00000000, 0x00feff84, 0xffe08000, 0x00ffffff, 0x00010000, 0x00010000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000001, 0x00000000, 0x7fff0001, 0x000b8000, 0x7fff0000, 0x00000000, 0x00000000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000001, 0x00000000, 0x4d748fad, 0x55557fff, 0xdd21c01f, 0x00000000, 0x00000000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00005244, 0x00000db6, 0xfffd0000, 0x00010000, 0x00010000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xffc054e0, 0xfff0c003, 0xff80028f, 0x00000000, 0x00000000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xfffffff8, 0x7fffffff, 0xfffffff8, 0x92490000, 0x80070000, 0x00010000, 0x00010000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00003f63, 0xe876f2fc, 0x00003f63, 0xe876f2fc, 0x00000000, 0x001f3fe0, 0x00000000, 0x00000000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xfffffffc, 0x80000000, 0x0055ffa6, 0xff297fff, 0x00003333, 0x00000000, 0x00000000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000013, 0xffffffff, 0xffc98e23, 0x0006feaf, 0xe95e9249, 0x00000000, 0x00000000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x0208d1d3, 0xddcccf9f, 0x0208d1d3, 0xddcce11b, 0x000201f8, 0xfffcff91, 0x00000000, 0x00000000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffffff, 0x00000000, 0xfffdf0f0, 0x00010000, 0x00010000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xc0000000, 0x00000001, 0xbfffffff, 0xed386571, 0x02d07ffd, 0x0ff87fff, 0x00000000, 0x00000000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xf0000000, 0x00000003, 0xefffffff, 0xfc01fff5, 0xfffffc01, 0x80007ff9, 0x00000000, 0x00000000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xfff660c2, 0xffffffff, 0xfffc06c0, 0xfffb0003, 0xe4547fff, 0x00010000, 0x00010000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x0000001f, 0xffffffff, 0x80000020, 0x80000000, 0xf8038000, 0x00000000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xf8000000, 0x00000003, 0xf7ffffff, 0xcccd6669, 0x7fff01bb, 0x00003333, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xf0000000, 0x00000007, 0xf0000000, 0x0000a105, 0x04c0ffff, 0x7fff000a, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xffd3a2c6, 0xfe9d0000, 0x0000f001, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xfffffffe, 0x6b07649d, 0xfffffffe, 0x6b17647d, 0xfff00000, 0x7fff7fff, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00001915, 0x9091c8b8, 0x00001915, 0x8ff6fb5a, 0xffc6ff87, 0x99998000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x55555555, 0x55555555, 0x55555555, 0xd5545555, 0x8000001b, 0x00007fff, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xfffff945, 0xffffffff, 0xfffcf96f, 0xffe9fffd, 0x80070000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x3fffffff, 0xfffffffc, 0x40000000, 0x8662c002, 0x80007fff, 0xe0036666, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x55555555, 0x55555555, 0x55555555, 0x554e15cd, 0x1ffc000e, 0x3ffc0001, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x0000000f, 0xffffffff, 0xf9f02f83, 0x05b5b6db, 0xff617fff, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x01cd0b40, 0xfc01040a, 0x001039c0, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x01e46e08, 0x00000000, 0x81c46e46, 0x80067fff, 0x801f0000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xfffbff4d, 0x000a549d, 0xfffbff4c, 0xe13f9233, 0x025a7fff, 0x1c717fff, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xb6db6db6, 0xdb6db6db, 0xb6db6db6, 0xdb6db6db, 0x00000000, 0x80000000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x0129823f, 0xffcee007, 0xffe27fff, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffff03, 0x35e13d56, 0xffffff03, 0x35e220e6, 0xc71c3fe0, 0x00000002, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00030006, 0x00017fff, 0xfffdfffa, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfffcf7f3, 0xfffdff32, 0xfffb8000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x0000006b, 0xb4ed34b8, 0x0000006b, 0xb25330b8, 0xff808000, 0xfd66fffc, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xe6377963, 0xffffffff, 0xe6377963, 0x00000000, 0xfffd7fff, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffbc, 0x1d56b826, 0xffffffbc, 0x1d59b826, 0x80008007, 0x80007ffc, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xfffffff0, 0xfffdc8dd, 0x00000000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xfffff704, 0x127e1c68, 0xfffff704, 0x127e1c5c, 0x00060000, 0x00690001, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00001e7a, 0xffffffff, 0xff55727a, 0xff000000, 0x014aaaaa, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x0000018b, 0x00420000, 0xfe66fffd, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x1fffffff, 0xfffffff0, 0x1fffffff, 0xff95fff0, 0xff96f46c, 0x00008000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000004, 0x00000000, 0x0045ff78, 0x00007fff, 0xffbaffe9, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000005, 0x7fffffff, 0xfc040801, 0x7fff8000, 0x000203fe, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xe38e38e3, 0x8e38e38e, 0xe38e38e3, 0x8e38e38e, 0xf0f00000, 0x00000000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x48d1a39a, 0x00000000, 0x48f2a3a0, 0x8000ffff, 0x00030021, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x0000000c, 0x0c497530, 0x0000000c, 0x0c4b7512, 0xfffd8000, 0x0002fffb, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000006, 0xffffffff, 0xc0027d28, 0x3ffe016d, 0x00017fff, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000001, 0x0f639f38, 0x00000000, 0x8f6c9f28, 0x00007fff, 0x7ff88000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x55166513, 0x7fff003f, 0x7fe0aaaa, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x000001b4, 0x00000000, 0x000400ec, 0x0000ff11, 0x02248000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffffff, 0xfffffffd, 0xffffffff, 0xf017387b, 0xfffce00f, 0xc03ffffc, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x0ffe0000, 0x0ffe0000, 0x80008000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xc0000000, 0x00000003, 0xc0000000, 0x2489db43, 0xdb6d803f, 0x00007fe0, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x0004fb27, 0x00140000, 0x0018e01f, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffffff, 0xfff86f81, 0xffffffff, 0xfff86f7d, 0x00000001, 0x00027f80, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x3fffffff, 0xffffffe0, 0x3fffffff, 0xffffffe0, 0x07fe0000, 0x03fe0000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xfffffef0, 0xc81352f5, 0xfffffef0, 0xc7ef93c3, 0x011771c7, 0x00010ffe, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x0061adb8, 0x892ce692, 0x0061adb8, 0x8951e648, 0x7fff0000, 0x0000ffdb, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xc0082497, 0xc0070004, 0xdb6d8000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xfc000000, 0x00000001, 0xfbffffff, 0xf0041ff9, 0x00000ffc, 0x7fff0000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x0033ff98, 0xf003ffcc, 0x7fff0000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x0000495f, 0xaca5aaeb, 0x0000495f, 0xad3e97cb, 0xfecef001, 0x00003ff8, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x0000006b, 0x00000000, 0x0001a08d, 0x014f0000, 0x8000ff61, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x01ebf1a4, 0xfb3cb2c6, 0x01ebf1a4, 0xa5e8b2b2, 0x7ffbaaaa, 0x8000fffe, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x000002dc, 0x9e9a53c7, 0x000002dc, 0x1e9c53c5, 0x02eb7fff, 0x7fff0000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000005, 0x80000000, 0x00000005, 0x00017fff, 0x00000000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x063a150b, 0x5ca2e025, 0x063a150b, 0x5c9ce025, 0x80000000, 0x036cfffa, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0xc0018000, 0x7fff8000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xffffff06, 0x00000000, 0x000eff06, 0x0000000f, 0x80000000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfba50006, 0x00000000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000001, 0xbfa5a453, 0x00000001, 0xbf8cd953, 0xfffa7fff, 0x0016c467, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x2a110863, 0x00000000, 0x2614e781, 0x00070ffc, 0x1ff0f007, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xf0000000, 0x00000003, 0xf0000000, 0x00010c43, 0x01880001, 0x8000fffc, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xfc000000, 0x00000001, 0xfc000000, 0x68e309a7, 0x6db67fff, 0x04d38000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xff626849, 0xa8847aae, 0xff626849, 0xa83c5af4, 0x012fffff, 0x7fff1ee4, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xf0021ffc, 0x7fff0005, 0x00000ffe, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000394, 0xffffffff, 0x924b0394, 0x80008000, 0x92490002, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffffff5f, 0xfff00000, 0xc007fffb, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x76c21a35, 0x00000000, 0x86c01a35, 0x800f8000, 0x0ffe0000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffe162, 0xc09e823b, 0xffffe162, 0xc09e823b, 0x0000e38e, 0x00000000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000007, 0x7fffffff, 0xfeae07f3, 0xf8037ffd, 0x01520000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffdd, 0xd34a8b05, 0xffffffdd, 0x534c8b03, 0x00007fff, 0x7fffe50d, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffc42c, 0x8501eb4b, 0xffffc42c, 0x850122f5, 0xfffa800f, 0xffff04a1, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000005, 0x00000000, 0x00021e89, 0x07a10002, 0x8000fffe, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffffff, 0xfffffbda, 0x00000000, 0x0000ca8e, 0x00010cec, 0xfff80006, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xfffffb03, 0xffffffff, 0x80017ab0, 0xe0078000, 0x80000006, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000eef, 0xa2626579, 0x00000eef, 0x2266db99, 0x8004ff70, 0x00698000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x1fffffff, 0xfffffff8, 0x20000000, 0xfff6fff8, 0x80007ff8, 0x80007fff, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000003, 0x00000000, 0x00257095, 0xc03fffea, 0x7fff001f, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffb, 0x00000000, 0x8000ffef, 0x7fff7ffb, 0x8000fffa, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffff852f, 0x4788b9a2, 0xffff852f, 0x317c3942, 0x3ff08000, 0xe9f2fffd, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xffffff80, 0xffffffff, 0xffffff80, 0xdb6d7fff, 0x00000000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000078, 0x00000000, 0x00002146, 0xffef3ffe, 0x000000f7, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x3ffc0000, 0x3ffc0000, 0x3ffe8000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xfffff783, 0xffffffff, 0x2491f783, 0x80009249, 0x80009249, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x001448fb, 0x7fff6db6, 0xfffbfff0, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xcccc0000, 0xcccc0000, 0x00058000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xffffff00, 0xffffffff, 0xffffff00, 0x00000000, 0xfff03ff0, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x00080def, 0x0007fff8, 0x7fffff00, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x0006ffff, 0x80000000, 0x00000007, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xffffff00, 0x00000000, 0x0347fbb8, 0x55550000, 0x7ffffb14, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00670000, 0x80001437, 0x00000067, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xf6e0123f, 0x0ff87fff, 0x00004924, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x03fb807f, 0x1c71f801, 0x3fc00000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xfffffed5, 0x6eb30c90, 0xfffffed5, 0x8e8c1450, 0x7fe00000, 0xffffe01f, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x03892485, 0xe4c0f937, 0x03892485, 0xe4d7f889, 0x7ffffffc, 0xfff0ffe9, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x03570000, 0x80008000, 0x03550002, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xfffe01fc, 0x07fefffe, 0x807f0000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x07ffffff, 0xfffffffc, 0x08000000, 0x000026ca, 0xffff8000, 0x00001367, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffff9, 0x80000000, 0x1b6ca48d, 0xe0010000, 0x1e426db6, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x3fffffff, 0xfffffffc, 0x40000000, 0x7fed0d10, 0x00ff7fff, 0x800f017b, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x02834930, 0x00000000, 0x02834930, 0xf5f87fff, 0x00000000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xc0000000, 0x00000003, 0xbfffffff, 0xfffe38e3, 0xc71c007f, 0x0000fffc, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xe3da01b6, 0x0986801f, 0xe003cccc, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0001000e, 0x00000000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xfffef704, 0x00000000, 0x03fbf784, 0x7fc0fbc2, 0x0000fc01, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000265, 0x00000000, 0x7fff0265, 0x80000000, 0x000f7fff, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00019da7, 0xd2dfd8fe, 0x00019da7, 0xd333b9ae, 0x80008e38, 0xee630ffc, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x219e0000, 0x80003ffe, 0x8000e1a0, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00051a30, 0x93e3d658, 0x00051a31, 0x93e1d658, 0x80008000, 0x7fff7fff, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffe52dd0, 0xb6a53cf9, 0xffe52dd0, 0xb6a50d05, 0xcccc07fe, 0x00030000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x002f9747, 0x00000000, 0x002fe233, 0x80002576, 0xffff0000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f819c0f, 0x0000ff1a, 0x3fc0cccc, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0xc003f77c, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0x4a719a07, 0xffffffff, 0x7c329a07, 0x31c4fffd, 0x80008000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000005, 0xffffffff, 0xf461af61, 0x7ffff99d, 0xf0f00ade, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x3fffffff, 0xfffffffe, 0x3fffffff, 0xfffffffe, 0x80008000, 0x00000000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x000011ed, 0x00000000, 0x000011ed, 0x3ff80000, 0xffc00000, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000015, 0xffffffff, 0xc2c20015, 0x800002b3, 0x8000c00f, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x0000fffe, 0x7fff7fff, 0x0000ffff, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000003, 0x00000000, 0x0015e35d, 0x800038e3, 0xffd10001, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xffffc2d4, 0x0000020a, 0x000f1ffc, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0x80058000, 0x00000000, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffff0, 0x7fffffff, 0x7ffffff1, 0x80000000, 0x00008000, 0x00020000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00079c4b, 0x00000000, 0x00084f97, 0xffa60143, 0x000000ff, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xf0000000, 0x00000003, 0xf0000000, 0x7ff9ff03, 0x8000ff80, 0xffff7ffa, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x80000000, 0x06120000, 0x06228000, 0xfff08000, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x0fffffff, 0xfffffffc, 0x10000000, 0x0060d9b8, 0x1ffc0f0f, 0xfff2fe83, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xfffb17f0, 0xe3740000, 0x0000ffea, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffff0, 0x7fffffff, 0xff73fff0, 0xff640010, 0x80008000, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xe03e6b1c, 0xffffffff, 0xe03e6a9c, 0xffff0000, 0xf0f0ffc0, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000104, 0xeff86417, 0x00000104, 0xf7f6041d, 0xfffd8000, 0x07fef001, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x80007fff, 0x00000000, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xc0000000, 0x00000003, 0xbfffffff, 0x8004fff7, 0x7fff8002, 0x80030000, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x0000007f, 0x80000000, 0x0000007f, 0x00000000, 0x807f0135, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000005, 0xffffffff, 0xffffff15, 0xc01fffe2, 0xfffc0000, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xfea6d946, 0x00000000, 0x53fbd9a0, 0x55550003, 0xfff18000, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xfffffff0, 0x7fffffff, 0xfffffff0, 0x00000000, 0x00000000, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xffef3e2c, 0xffffffff, 0xffef3e2c, 0x00000000, 0x8000ffde, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfffffffe, 0xffffffff, 0x7fff8000, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x0005fff4, 0x7ffffffd, 0x7ffffffd, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xffea7dbf, 0x00000000, 0x1c5b7cc1, 0x1c71007f, 0x00018000, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffff9c, 0xa2f00fdf, 0xffffff9c, 0xa318a265, 0x00473ff0, 0x0000b6db, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x80000000, 0x000018c7, 0x003d021a, 0x0000ffcc, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xfffffffc, 0x7fffffff, 0xfffffffc, 0x00001ffc, 0x00003fe0, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xffd0ffff, 0x00008000, 0xffd1028d, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x0001ff9e, 0x00000000, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xfff31e51, 0xffffffff, 0xfff32a07, 0xfa257fc0, 0x00000001, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xfffffff8, 0x7fffffff, 0xfffffff8, 0x00000fc1, 0x00000000, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00, 0x8000fff8, 0x00000000, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x0fffffff, 0xfffffffc, 0x0fffffff, 0xf005ff7c, 0xfffc3ff0, 0x1ffc0000, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xf0070000, 0xf0077fff, 0x00008000, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x0057f0ac, 0x00000000, 0x8037f0ac, 0x00008000, 0x7fe07ffa, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x5f724e7f, 0x8000209d, 0x7fc07fff, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00007c33, 0xffffffff, 0xfffc7c3b, 0x00000004, 0x7fff9249, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x003b0adf, 0x88661e68, 0x003b0adf, 0x884ad91c, 0x1ff009ce, 0xfec500ce, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x7ffd0006, 0x00038000, 0x80007fff, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffff2817, 0x84076dc7, 0xffff2817, 0x84326d71, 0xffd50000, 0xfff87fff, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00015b6b, 0xe56bd5cd, 0x00015b6b, 0xe56ad5dd, 0x1ffee007, 0x00000004, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xb6db6db6, 0xdb6db6db, 0xb6db6db6, 0x7168a629, 0x1fe08001, 0x99990e8a, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x0000000a, 0xa1b1b7c6, 0x0000000a, 0xa29ffc86, 0x4924febc, 0x8000fc28, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x000ac690, 0x00000000, 0x0006c9d2, 0x0004fff9, 0x003b7fff, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xfffffffc, 0x00000000, 0x7ff8fffc, 0x80008000, 0x00007ff9, 0x00060000, 0x00060000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000edc, 0xffffffff, 0x40208e9d, 0x80003fe0, 0x7fff8000, 0x00060000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffe8a740, 0x6aed4a59, 0xffe8a740, 0x6aed4a59, 0x00067fff, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00078846, 0x1555102f, 0x00078846, 0x1654783b, 0x0000e003, 0x03feffff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0x80dbfe86, 0x801fff43, 0x7fff8000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xfffffffb, 0x80000000, 0x00000037, 0x0000000f, 0xfffef007, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xfffffffb, 0x00000000, 0x0006cfe5, 0x000d38e3, 0xfff8dfef, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xfffdfff6, 0xdb6d0000, 0x7ffffff9, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x8e38e38e, 0x38e38e38, 0x8e38e38e, 0x3a768b12, 0xff227fff, 0xfe6d0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xfffe3805, 0xffffffff, 0xfffd5875, 0x00250ff8, 0x00070000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x0062b411, 0x30dbf45f, 0x0062b410, 0xbf15d78d, 0xfffc7fff, 0x71c7fff4, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00f3f0be, 0x2efcd0a6, 0x00f3f0be, 0x2f02ce6a, 0x005b7fff, 0xfffbfe9b, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x000000e8, 0x5d89b153, 0x000000e8, 0x47616e13, 0x800015e6, 0x7ff0ffbb, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x03e95ee3, 0xfc01e12a, 0x0f0f0918, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000001, 0x6ea2d64b, 0x00000001, 0x6ef6d64b, 0x0054aaaa, 0x00008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x8f0e0000, 0x7fff8000, 0x0f0f8000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00f8010d, 0x00000007, 0x7fff7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x80000000, 0x00000000, 0x7fffffff, 0xffff8780, 0xf0f08006, 0x0000fffc, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xfffe2a94, 0xffffffff, 0xfffe4a8c, 0x0ffc0001, 0x0000ffff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x7f702cae, 0xfb627ff9, 0x803ff801, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000122, 0x832b01c4, 0x00000122, 0x8316a6d0, 0xb6db004d, 0x1ff0fffe, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x0000b153, 0xa32a28ae, 0x0000b154, 0x230428a4, 0x801ffffa, 0xffdb7ff9, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffffa, 0x80000000, 0x671300fc, 0x00d87fff, 0x99999999, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xf804104c, 0x07fcfff9, 0x00067fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xf8019000, 0x07fee001, 0xfffe7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xf8020fc4, 0xfff907fe, 0x7ffffffc, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000007, 0x7fffffff, 0xeb9cda0d, 0xf46b801f, 0xe0037fe0, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffc0, 0x80000000, 0x0040fcd0, 0x3ffc0012, 0x8000ffa2, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x24706728, 0x0ffc8006, 0x0001c003, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x1fffffff, 0xfffffffc, 0x20000000, 0x0005fffc, 0x80000000, 0x80010006, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x00000000, 0x7ffa7fff, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x010cfde6, 0x7ffffff3, 0x7fffff00, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x80000000, 0x000001b7, 0x00048000, 0x0000ffc9, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffffff, 0xe8486105, 0xffffffff, 0xce18cfb3, 0x0000e5cf, 0x80070006, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x7ff0001e, 0x00007fff, 0x800f02a6, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xfffffef0, 0xffffffff, 0xfc0606e4, 0x7fff03f5, 0x7fff0005, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000064, 0xffffffff, 0xcccd66ca, 0x00003333, 0x7fff8000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffe0740e, 0x3287e00f, 0xff80ffff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x0fffffff, 0xfffffffe, 0x10000000, 0x2aad8000, 0x80005555, 0xc0030005, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x80000000, 0x0eeee002, 0xfef0f001, 0x7fff8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xfe876f58, 0xffffffff, 0xfe391ab2, 0xaaaa0053, 0x7fff0007, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x0000043c, 0x010d0001, 0xfffcfffe, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffffff, 0xfffffff9, 0x00000000, 0x71737f85, 0x8e380ffe, 0x028f7ffd, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffffff, 0xfffe33c5, 0xffffffff, 0xffd533d1, 0x80008006, 0xffffffd8, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00005270, 0x0fa26952, 0x00005270, 0x0f719bc2, 0xfc01cccc, 0xff860000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xfffc0000, 0x80000000, 0x8000fffc, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0xffffffff, 0xfffffe27, 0xffffffff, 0x8800ee2d, 0xf8038000, 0x80047fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xc0000000, 0x00000001, 0xbfffffff, 0xffffff8d, 0x0000ffe3, 0xfffefafe, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000000, 0x7fffffff, 0xffbe11b2, 0x80000003, 0xfd0dffbe, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffffff, 0xfffffffe, 0xffffffff, 0xc0027ffa, 0x00003ffe, 0x7fffff2f, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xffffa9c9, 0x4e755172, 0xffffa9c9, 0x52c649cc, 0x0451ffee, 0x00078001, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffdd803f, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x80000000, 0x00000000, 0x7fffffff, 0xfffe3c20, 0xfff1ff5a, 0x0000f0f0, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffe0, 0x7fffffff, 0xfe2a2708, 0x1ffc807f, 0xfe5c00ce, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xe007d9a7, 0x01141ffe, 0x7fe000ff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xfffffffa, 0x80000000, 0x2a95d530, 0xffffc01f, 0x5555ffe6, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x0000003f, 0x00000000, 0x0f0f003f, 0x0f0f0000, 0x7ffc8000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x00000001, 0x7fffffff, 0xc03f0001, 0x9999c03f, 0x80000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffe87fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xfffffffe, 0x7fffffff, 0xfffffffe, 0x80009249, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x7fffffff, 0xffffffff, 0x80000000, 0x0002feb5, 0x0003ffff, 0xff5b8000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0xf311d96e, 0x00000000, 0xf213db4c, 0x7fff0ffe, 0xfff800ff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x00000000, 0x000003e9, 0x00000000, 0x000003e9, 0x00008000, 0x0000e0d1, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x80000000, 0x0000000f, 0x7fffffff, 0xffe80023, 0x0019800f, 0x00017fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x00000641, 0xb58ec28c, 0x00000641, 0x9ae4e7e2, 0x12ab8000, 0xf8017fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x80000000, 0x7ffbffff, 0x80003ffe, 0x80003ffe, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0xc71c71c7, 0x1c71c71c, 0xc71c71c7, 0x1c71c71c, 0x00000000, 0x00009999, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x7fffffff, 0xffffffff, 0x7fffffff, 0x7ffc0000, 0xfffc8000, 0x80008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0xffffff80, 0xacac92de, 0xffffff80, 0x2ca992e6, 0x7fff0005, 0x7fff7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac0, 0x7fffffff, 0xffffffff, 0x7fffffff, 0xfdcbffff, 0xfdcc0000, 0x80008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0xffffffff, 0xfffffffb, 0xffffffff, 0x7fad01ee, 0xffad8000, 0x80008003, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_s.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xfffff4ce, 0x7fffffff, 0xfa670000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac2, 0x80000000, 0x00000000, 0x7fffffff, 0xfff083e0, 0x1fe0001f, 0x3ff00000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_s.w.ph, $ac1, 0x00000000, 0x000008ee, 0x00000000, 0x00006a26, 0x00cc0001, 0x0000ffc3, 0x000e0000, 0x000e0000 - - writemsg "[52] Test dpsqx_sa.w.ph" - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffffe7, 0x00000000, 0x0050ffe7, 0x8000ffe0, 0x00000051, 0x00000000, 0x00000000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xfffffff8, 0xfe1afff8, 0x00000000, 0x00020000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000001, 0x00000000, 0x0144cbeb, 0x0a07fffc, 0x7ffff001, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x005e8cd9, 0xffffffff, 0x80608cd7, 0x7fff0000, 0xf0017fff, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x99999999, 0xffffffff, 0x99999999, 0x00000006, 0x00000006, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x007cd308, 0x00000000, 0x007b365c, 0x00070ebd, 0x00070ebd, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffffffd4, 0x00000000, 0x7fff00d4, 0x00017fff, 0x8000ff80, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffb, 0x00000000, 0x03c80efb, 0x80001ff8, 0xf0f00005, 0x00020000, 0x00020000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x800b3278, 0x0006fff0, 0x7ffa6666, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xfc000001, 0xffffffff, 0xfbe80031, 0x7ffffffa, 0x7fff001e, 0x00030000, 0x00030000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7ffffffd, 0x00000000, 0x7fffffff, 0x29ac1fe0, 0xffda000b, 0x00030000, 0x00070000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x2472b6da, 0x8000db6d, 0x7fffffe0, 0x00070000, 0x00070000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7ffffffd, 0x00000000, 0x7fffffff, 0xdb6d8000, 0x7ffffffa, 0x00070000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xffffffe2, 0xffffffff, 0x8001def3, 0xfff18000, 0x80000ff8, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x0000835a, 0x03eefffd, 0x1c710005, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7ffffff8, 0x00000000, 0x165faaa2, 0xebb47fff, 0x55558000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x000002e1, 0x00000000, 0x00004af7, 0xfffc0269, 0xfff1fff9, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x8c0c9084, 0x0062f0f0, 0x6666003f, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x92492492, 0xffffffff, 0x924224a0, 0x7fff7fff, 0x00070000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffca267, 0xffffffff, 0xfffd05af, 0x08460000, 0x8006fffa, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x7fffffff, 0x7fff0015, 0x80008000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xaaaaaaaa, 0xffffffff, 0xaaaaaaaa, 0x7ffff0f0, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000b8e, 0xffffffff, 0xe90a7b6e, 0x00027ff8, 0x16f63fe0, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffffff80, 0xffffffff, 0x80000000, 0x80008000, 0x8000aaaa, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x7ffef004, 0xfc018000, 0x7ffffffe, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x0000c90c, 0x7fffdcec, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x0000005a, 0x00000000, 0x0000005a, 0x0ff80006, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffde, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xffffffff, 0x00000000, 0x10e6de3b, 0x00017fff, 0xef187ffa, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x0520cc81, 0x00000000, 0x0520cc81, 0xfffe8000, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00ff00ff, 0x00000000, 0x7fffffff, 0x00057fff, 0x80007fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x80070004, 0xff887ffd, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0xbff019e0, 0x3ff000cf, 0xfff08000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x1ffffffe, 0x00000000, 0x20000fde, 0x0000007f, 0xfff07fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000002, 0xffffffff, 0x80000002, 0x7fffffc0, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x0000003a, 0x00000000, 0x0000003a, 0x001f8000, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x00577fff, 0x80000001, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffff00, 0xffffffff, 0x8020fef0, 0xfff87fe0, 0x7fff0003, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000013, 0x00000000, 0x7c01080f, 0x800003fe, 0x7fff7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffffff, 0x00000000, 0x7fef5577, 0x7fff1c71, 0x0003800f, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00003a28, 0x00000000, 0x7f843c56, 0x00077f80, 0x8003800f, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x1fe3fff9, 0x7ffd1fe0, 0x80007fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffffce35, 0xffffffff, 0x9248ee2d, 0x8000fc01, 0x00049249, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0x8002d5be, 0x7fff0260, 0xffd37fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xffff0002, 0x00007fff, 0x00010c61, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffff8d, 0xffffffff, 0xf0069bc5, 0x8004ffff, 0x8e38f007, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000007, 0xffffffff, 0x80000000, 0xff70ff54, 0xff70ff54, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7fff7fff, 0x7fff7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xff3744f1, 0xffffffff, 0xff28425b, 0x80000329, 0x03530006, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffff7ffd, 0xffffffff, 0x80011223, 0xfe847fff, 0x7fffffdb, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000437, 0xffffffff, 0xf47cd219, 0x7fff136e, 0x49240069, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xf4b2f5c7, 0xffffffff, 0xb551a685, 0xe01fe070, 0x8000803f, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0xffffffff, 0xffff0001, 0x80008000, 0x7fff8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000072, 0x00000000, 0x3fa11ff2, 0x7fc00000, 0xc8f8c03f, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7ffffff9, 0x00000000, 0x4047f7f9, 0x00007f80, 0x3ff8fee5, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x80001ba0, 0xfff0fc9f, 0x000000dd, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x000149e8, 0xffffffff, 0xf89b5920, 0xffff0766, 0x7fff0036, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x60209fb9, 0xf0017fff, 0x1fe00003, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x400877cf, 0x3ff8fff8, 0xff7e7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0000f801, 0xc0012492, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0xc376fd80, 0x8000f8fb, 0x3fc03ff8, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffffc00a, 0xffffffff, 0xdf510168, 0x7fff7fff, 0x00b31ffc, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x0000ffff, 0xffffffff, 0xf8145a0f, 0xfe338005, 0xf8130003, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffd65ca2, 0xffffffff, 0xffd65ca2, 0x00010000, 0x00010000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00017b63, 0xffffffff, 0xc0187b43, 0xc007fff0, 0x7fff8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xfb740918, 0x00007fff, 0x048c7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x0024c304, 0x00000000, 0x0024d04e, 0xff430000, 0x80000009, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x000001bc, 0x0000ff91, 0x0002000f, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffffff, 0xffffffff, 0x8001e809, 0x7fff0003, 0x03fe7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x004281fc, 0x00000000, 0x004281fc, 0x00000000, 0x00001efe, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x03860040, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x60037fe7, 0x7ffa0000, 0x00001ffe, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000006, 0xffffffff, 0x80000000, 0x800500b2, 0x33330000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffbf8006, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7ffffffe, 0x00000000, 0x7fffffff, 0x00003fe0, 0xfffc9249, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xe0000003, 0xffffffff, 0xffe0c041, 0x00047fff, 0xe01f0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xc03f0000, 0x3ffc8001, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7ffeffff, 0x80000000, 0x7fffffff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x1c71c71c, 0x00000000, 0x1c55e79e, 0xc003ffdf, 0x807f000a, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x007c8000, 0xfffae001, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xf8000003, 0xffffffff, 0x80000000, 0x00008000, 0x8000fffe, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x7ffffffb, 0x00000000, 0x7ffffffb, 0x8000f007, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x1ffffff8, 0x00000000, 0x23fdfff8, 0x8000fc2f, 0x000003fe, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x1ffffff8, 0x00000000, 0x2123fb68, 0x00008002, 0x01243ff8, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffff8, 0xffffffff, 0xfffffff8, 0xf7b90000, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffff80, 0x00000000, 0x7ffaaa20, 0xfffcaaaa, 0xfffcaaaa, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x000001ad, 0xffffffff, 0xfc994b21, 0xf0f0fffd, 0x3ffee30c, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0xfff8000e, 0x00078000, 0x7fff7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x02e6cef6, 0x00000000, 0x02e8244e, 0x00000003, 0xc71cfff3, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xffacf75a, 0xffffffff, 0xffacf264, 0x007f0000, 0xc0010005, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000195, 0xffffffff, 0x8400f995, 0x7fff7fff, 0x7ffffc01, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xc000001f, 0x00000000, 0x3f6ee63d, 0xf8037fff, 0x8000f6fb, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffc0, 0x00000000, 0x7fffffff, 0xfffa7fff, 0xc01fdb6d, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x003fff80, 0x7fff0038, 0x0000ffc0, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x01563ffc, 0x80008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000c4a, 0x00000000, 0x00000c4a, 0x00000000, 0xfff6004f, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xffefffca, 0x8000ffff, 0xffe5fff0, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0xee8c0000, 0x0000ee8c, 0x80008000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7f7ff9f3, 0xfff5ff80, 0x8001ffae, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x00780017, 0x00003ffe, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xb6db8000, 0xf77cfdec, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x80000001, 0xffffffff, 0x80000000, 0x80000000, 0x8003800f, 0x000e0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7fff0000, 0x8000aaaa, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffff68f, 0x00000000, 0x0040f487, 0x00410000, 0x00318004, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xffffff00, 0xffffffff, 0xfff8ff0e, 0x7fffc00f, 0x00000007, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x07fffffc, 0x00000000, 0x07fffffc, 0xffc0fec4, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x0f0f0f0f, 0x00000000, 0x0ef00f4d, 0x7ffffffa, 0x0000001f, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffffb, 0xffffffff, 0x8e75fd13, 0x80068e38, 0x8000003e, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xfffffe6f, 0x00000000, 0x0003e1df, 0x1c717ffc, 0xfffdfffc, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xc000000f, 0xffffffff, 0xc13a92c1, 0x92490000, 0x8000016f, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffa79b42, 0xffffffff, 0xffa79b42, 0xf0d9027c, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffc0, 0x00000000, 0x7fffac6e, 0xffd30000, 0x7fffff13, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x00c6f801, 0x7fff8000, 0x000e0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000006, 0xffffffff, 0x8001fffe, 0x00020000, 0x000d8002, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0xff1a274e, 0x0004fffa, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x35e594be, 0x00000000, 0x35e44320, 0xfff9e38e, 0xfffef003, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, 0x03fe0000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0xf1c71c70, 0x8e388000, 0x00007fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x000058b2, 0x00000000, 0x000058b2, 0x00000000, 0x7ffffffc, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xfffffffc, 0x00000000, 0x00012494, 0x00000004, 0xdb6d3ff8, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff33ff8, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xff7b8000, 0x7fffc007, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x99999999, 0xffffffff, 0x98c19e85, 0x8000005a, 0x7ff9ff82, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffffff, 0x00000000, 0x07e3ffff, 0x8000ffe8, 0x800007fc, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xcccccccc, 0xffffffff, 0xc93f8e2c, 0x0ffcfffc, 0xffbb1c71, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x002feb2d, 0x00000000, 0x002feb2d, 0x00000000, 0x0002e003, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xff8d2fc9, 0x00000000, 0x3f91e89f, 0x38e37fff, 0xc001fff2, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7fffffc0, 0xf18c7fc0, 0x000e0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xffa6892b, 0xffffffff, 0x8025892b, 0x807f0000, 0x8e388000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x07fef002, 0xfffa7fff, 0xf8010000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000000, 0x00000000, 0x0046fd8a, 0x8005800f, 0xfffc004b, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000007, 0xffffffff, 0xbffe0007, 0xfff58000, 0x3ffe0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00ff00ff, 0xffffffff, 0xebe2169b, 0xfe877fff, 0x151dfff9, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xf8000003, 0x00000000, 0x3da574b7, 0x7fff7fff, 0x3a5a8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x8000003f, 0xffffffff, 0x80000000, 0x00008000, 0xfe2f1ed8, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xfecda9e4, 0xfd99e01f, 0xfd99e01f, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x001fa337, 0xffffffff, 0x99c43cc5, 0x99993333, 0xffe38000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00002718, 0xfffdf0f0, 0x00000684, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfeaf28c5, 0xffffffff, 0xfeaf29b9, 0x0000003d, 0xfffec040, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x1a6b4c3a, 0x00000000, 0x7fffffff, 0x1ffc7ffc, 0x80008000, 0x000e0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x0000007f, 0xffffffff, 0xff02027b, 0x7fff007f, 0x7fff007f, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x7fffffed, 0xfffec00f, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7ffffffc, 0x00000000, 0x40087fec, 0x10207fff, 0x3ff80000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x800f7fff, 0x7fff0002, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7ffffffb, 0x00017f80, 0x00000002, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000001, 0x00000000, 0x7ffc7c8d, 0x8006fff9, 0x3fc07fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000001, 0x00000000, 0x1ffd8009, 0xc0018000, 0x00003ffc, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x0001bfcf, 0xffffffff, 0xffe25ecd, 0x08f58000, 0x000201dd, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0x80000006, 0x00000000, 0x00257906, 0xff3b8005, 0x7fff1c3f, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x000004d5, 0x00000000, 0x0000052d, 0xfffc0000, 0x8000000b, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000005, 0xffffffff, 0x81873507, 0x99998007, 0x000801df, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfff441cd, 0x00000000, 0x7ff2c24b, 0xffff7fff, 0x8000c03f, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x07fffffc, 0x00000000, 0x07ffe1de, 0x00000f0f, 0x00010000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00bfba7e, 0xffffffff, 0xc0d3399e, 0x00007ff9, 0x3ff08000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xe0000001, 0xffffffff, 0xc0115f81, 0x8001ff9f, 0x12a3e003, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x24924924, 0x00000000, 0x23e14906, 0xff4fffff, 0xfff18000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fb91de1, 0xfff000ff, 0x1c718e38, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffd, 0xffffffff, 0xf80001fd, 0x8000ff00, 0xfc01f808, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffff0, 0xffffffff, 0x807efff0, 0x8001807f, 0x80000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xfffffffa, 0xf7f30001, 0x00030000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x1ffffffe, 0x00000000, 0x3fee352e, 0x7fff1889, 0x0037e007, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffffc, 0xffffffff, 0xfff700fc, 0x7fe0fffb, 0x80000004, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0000fffc, 0xfffc7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000005, 0x00000000, 0x00021f17, 0xfff3f007, 0x00110000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xe885e01f, 0xff007fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffff0, 0xffffffff, 0xf0081fe0, 0xaaaa0ff8, 0x7fff0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x07fffffe, 0x00000000, 0x07fffffe, 0x00000f0f, 0x000000ff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x0000001f, 0xffffffff, 0x8000c865, 0x03b67fff, 0x7fff002a, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffe6838, 0xffffffff, 0xffff6738, 0xffff3fc0, 0xffff3fc0, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000006, 0xffffffff, 0x801a2210, 0xffcf8000, 0x800f1d15, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffe0, 0x00000000, 0x6ffb6e10, 0xedfb00f4, 0x00008e38, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00050765, 0x00000000, 0x0004e76b, 0xffff0000, 0xfd81f003, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x92492492, 0xffffffff, 0x9249248e, 0xfffefe80, 0x0000ffff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x0001554b, 0x00000000, 0x0001554b, 0x00000000, 0x801f8004, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffff80, 0x00000000, 0x7fffffff, 0xfffe7fff, 0x80018000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7ff801a4, 0x0ffe7fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x0000619e, 0xffffffff, 0x80000000, 0x7fff6666, 0x7fff6666, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x0014c26f, 0x00000000, 0x3fd4c26f, 0x00008000, 0x3fc08000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7ffffffd, 0x00000000, 0x7fffffff, 0x8000039d, 0x0ba63ffc, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80027fe2, 0x00050000, 0x0000c003, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffeccf6f, 0x00000000, 0x0384c83f, 0x8000fc68, 0x7fff0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xf0000007, 0xffffffff, 0xf78d038d, 0xef13f803, 0x7ffcfcb3, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00000006, 0x00000000, 0x007ef232, 0xfffa8000, 0x007ffed9, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xffffc64a, 0x00000000, 0x0b605896, 0xffc6e38e, 0x3333ff98, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x7ffd0000, 0x7fff8000, 0xfffe8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffffd, 0x00000000, 0x7ff8000b, 0x8e387fff, 0x80070000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xfffdaaaa, 0x7fff7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000003, 0x00000000, 0x10113daf, 0x7ffa7ff0, 0xffedf001, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffff0, 0xffffffff, 0xff990658, 0xfffcfcc8, 0xf001ffff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000156, 0x00000000, 0x0002ac06, 0x8e380000, 0x7fff0003, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00338e2c, 0x38e371c7, 0xffc60000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xc71c71c7, 0xffffffff, 0xc7e771c7, 0xf00700cb, 0x80000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x000000e2, 0xffffffff, 0xc6b372a8, 0x7fffff96, 0x800038e3, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xffffff9a, 0x00000000, 0x0ffbff9a, 0x00040ffc, 0x80000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffff3bd, 0x00000000, 0x7fe08db3, 0x00037fe0, 0x8000e657, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xffffff28, 0xffffffff, 0xffffff28, 0xffd2ffd9, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x1ee224ec, 0x00000000, 0x1ee224ec, 0x00008000, 0x00007fff, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000005, 0xffffffff, 0x80000000, 0x00000091, 0x018c0000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffffe, 0xffffffff, 0xf99cead0, 0x66660005, 0xfda307fc, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffc072f, 0xffffffff, 0xfffc072f, 0x00000000, 0x3ff8cccc, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xef2025f7, 0x00000000, 0x08bd266b, 0x001d8000, 0x199dfffe, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01267ffe, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x000007fc, 0x000007fc, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xd46c2ef6, 0x00697fff, 0x2b940031, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffffffe, 0xffffffff, 0xf0d9ff06, 0x801f8000, 0xf0d60004, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xc0000007, 0xffffffff, 0x8cceccdf, 0x00038007, 0xcccc0000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7ffce5c9, 0xffff1ff0, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x0007fff1, 0x7ff90000, 0x7ff87fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0x80000000, 0xffffffff, 0xbfe1d34c, 0x021e3fc0, 0x8000f803, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x029b31c9, 0x00000000, 0x069d31c9, 0x03ea0018, 0x80008000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x00000000, 0xffffffff, 0xff680130, 0x0001ff68, 0x80010000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffb77, 0xffffffff, 0xfffffb77, 0xf0030000, 0xff280000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x0018cfeb, 0x00000000, 0x0015d00f, 0x801ffffa, 0xc0030000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00000192, 0x00000000, 0x000b00f8, 0x71c7fff5, 0x7ff90000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x009d026e, 0x00000000, 0x009304c6, 0x0000c00f, 0xffec8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x00029e0d, 0x00000000, 0x018d9e0d, 0x80008000, 0x018b0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xfffffe7c, 0xffffffff, 0xe394a934, 0x0000c00f, 0xc71c0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffffe, 0x00000000, 0x0e27f90a, 0x7fff38e3, 0xe01f0003, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x6db6db6d, 0x00000000, 0x6db6db6d, 0x8000edab, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0x80000000, 0xffffffff, 0x8007c010, 0x0001fff8, 0x7ffd1fe0, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000003, 0x00000000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x0000124e, 0xffffffff, 0xf8042246, 0x07fc6db6, 0x00007fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x1ffec002, 0x7fff0000, 0x7f80e001, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x0080d77c, 0xffffffff, 0x8080d7b9, 0x000f8000, 0x8000fffe, 0x000e0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80370000, 0x00000037, 0x80004924, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x7fffffff, 0x00000000, 0x7c2d07a5, 0x800103d3, 0x7fff0000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0x00000000, 0x7ffff001, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x00000000, 0xffffffff, 0x80000000, 0x80030ff8, 0x7fff801f, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x7ffffffb, 0x00000000, 0x7e640669, 0x0001c001, 0xfcca7fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x07fffffc, 0xffffffff, 0x8801a0b5, 0x8000fff4, 0x115d8000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xe8653084, 0xffffffff, 0xc3d379a8, 0x24920000, 0x04367fff, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0x00000000, 0x0006062c, 0x00000000, 0x0006062c, 0x803f0030, 0x00000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffa83, 0xffffffff, 0x8006fa77, 0x03fe7fff, 0x7ffa0000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0000fff8, 0xfffdff35, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x0000000a, 0xffffffff, 0xfffe000a, 0x0018fffe, 0x80000000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac1, 0xffffffff, 0xffffffe9, 0xffffffff, 0xf2fbffe9, 0xf2fcffe2, 0x00008000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffff0, 0x00000000, 0x08536eec, 0x3ff07fff, 0xf7aefffd, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0xffffffff, 0xfffffffd, 0xffffffff, 0x8e39e38b, 0x7fff0000, 0xcebf71c7, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x001435cb, 0x00000000, 0x001535eb, 0xffff0006, 0xffe87f80, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0xffffffff, 0xfffff76c, 0x00000000, 0x0c1681b0, 0x8000db6d, 0x2d96ff10, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x7fffffff, 0x00000000, 0x7fffffff, 0xfffe0000, 0x7fff7ffd, 0x000e0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0x00000000, 0x7fffffff, 0x00000000, 0x7ffc0007, 0x7fffe2b6, 0x00000004, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac2, 0x00000000, 0x03fffffe, 0x00000000, 0x03f6bb8e, 0x05b4fff7, 0x80000006, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00070000, 0x00070000, 0x000f0000, 0x000f0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x00000000, 0xffffffff, 0xfb8108fe, 0x7fff0000, 0xfffd047f, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac3, 0xffffffff, 0xfffffffb, 0x00000000, 0x7ffe4007, 0x7ffff001, 0xfffa8000, 0x000e0000, 0x000e0000 - dspckacc_astio dpsqx_sa.w.ph, $ac0, 0x00000000, 0x000002f4, 0xffffffff, 0x8676a8d4, 0x80007ff9, 0xf9908007, 0x000f0000, 0x000f0000 - - pass - .end DIAG diff --git a/sim/testsuite/sim/mips/sanity.s b/sim/testsuite/sim/mips/sanity.s deleted file mode 100644 index 74551ed..0000000 --- a/sim/testsuite/sim/mips/sanity.s +++ /dev/null @@ -1,20 +0,0 @@ -# mips test sanity, expected to pass. -# mach: all -# as: -mabi=eabi -# ld: -N -Ttext=0x80010000 -# output: *\\npass\\n - - .include "testutils.inc" - - setup - - .set noreorder - - .ent DIAG -DIAG: - - writemsg "Sanity is good!" - - pass - - .end DIAG diff --git a/sim/testsuite/sim/mips/testutils.inc b/sim/testsuite/sim/mips/testutils.inc deleted file mode 100644 index a0fcd0a..0000000 --- a/sim/testsuite/sim/mips/testutils.inc +++ /dev/null @@ -1,150 +0,0 @@ -# MIPS simulator testsuite utility functions. -# Copyright (C) 2004-2021 Free Software Foundation, Inc. -# Contributed by Chris Demetriou of Broadcom Corporation. -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . */ - - -# $1, $4, $5, %6, are used as temps by the macros defined here. - - .macro writemsg msg - la $5, 901f - li $6, 902f - 901f - .data -901: .ascii "\msg\n" -902: - .previous - .set push - .set noreorder - jal _dowrite - li $4, 0 - .set pop - .endm - - - # The MIPS simulator uses "break 0x3ff" as the code to exit, - # with the return value in $4 (a0). - .macro exit rc - li $4, \rc - break 0x3ff - .endm - - - .macro setup - - .global _start - .global __start - .ent _start -_start: -__start: - .set push - .set noreorder - j DIAG - nop - .set pop - .end _start - - .global _fail - .ent _fail -_fail: - writemsg "fail" - exit 1 - .end _fail - - .global _pass - .ent _pass -_pass: - writemsg "pass" - exit 0 - .end _pass - - # The MIPS simulator can use multiple different monitor types, - # so we hard-code the simulator "write" reserved instruction opcode, - # rather than jumping to a vector that invokes it. The operation - # expects RA to point to the location at which to continue - # after writing. - .global _dowrite - .ent _dowrite -_dowrite: - # Write opcode (reserved instruction). See sim_monitor and its - # callers in sim/mips/interp.c. - .word 0x00000039 | ((8 << 1) << 6) - .end _dowrite - - .endm # setup - - - .macro pass - .set push - .set noreorder - j _pass - nop - .set pop - .endm - - - .macro fail - .set push - .set noreorder - j _fail - nop - .set pop - .endm - - - .macro load32 reg, val - li \reg, \val - .endm - - - .macro load64 reg, val - dli \reg, \val - .endm - - - .macro loadaddr reg, addr - la \reg, \addr - .endm - - - .macro checkreg reg, expreg - .set push - .set noat - .set noreorder - beq \expreg, \reg, 901f - nop - fail -901: - .set pop - .endm - - - .macro check32 reg, val - .set push - .set noat - load32 $1, \val - checkreg \reg, $1 - .set pop - .endm - - - .macro check64 reg, val - .set push - .set noat - load64 $1, \val - checkreg \reg, $1 - .set pop - .endm diff --git a/sim/testsuite/sim/mips/utils-dsp.inc b/sim/testsuite/sim/mips/utils-dsp.inc deleted file mode 100644 index 936f691..0000000 --- a/sim/testsuite/sim/mips/utils-dsp.inc +++ /dev/null @@ -1,443 +0,0 @@ -# MIPS DSP ASE simulator testsuite utility functions. -# Copyright (C) 2005-2021 Free Software Foundation, Inc. -# Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu. -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . */ - -# $4, $5, $6, $7, $ac0, $ac1, $ac2, $ac3 are used as temps by the macros -# defined here. - - # If a != b, jump to _fail. - # Otherwise, fall through. - .macro dsp_assert a, b - beq \a, \b, 1f - nop - j _fail - nop -1: - .endm - - # Set dsp control register <= crin - # Check if d == (inst ?, s, t) - # Check if crout == dsp control register - .macro dspck_dstio inst, d, s, t, crin, crout - li $4, \crin - wrdsp $4 - li $4, \s - li $5, \t - \inst $6, $4, $5 - li $7, \d - dsp_assert $6, $7 - li $4, \crout - rddsp $5 - dsp_assert $4, $5 - .endm - - # Set dsp control register <= crin - # (inst s, t) - # Check if crout == dsp control register - .macro dspck_stio inst, s, t, crin, crout - li $4, \crin - wrdsp $4 - li $4, \s - li $5, \t - \inst $4, $5 - li $4, \crout - rddsp $5 - dsp_assert $4, $5 - .endm - - # Set dsp control register <= crin - # Check if d == (inst ?, s, t) - .macro dspck_dsti inst, d, s, t, crin - li $4, \crin - wrdsp $4 - li $4, \s - li $5, \t - \inst $6, $4, $5 - li $7, \d - dsp_assert $6, $7 - .endm - - # Set dsp control register <= crin - # Check if tou == (inst tin, s) - .macro dspck_tsi inst, tou, tin, s, crin - li $4, \crin - wrdsp $4 - li $4, \s - li $5, \tin - \inst $5, $4 - li $6, \tou - dsp_assert $5, $6 - .endm - - # Set dsp control register <= crin - # Check if d == (inst ?, imm) - # Check if crout == dsp control register - .macro dspck_dIio inst, d, imm, crin, crout - li $4, \crin - wrdsp $4 - \inst $5, \imm - li $6, \d - dsp_assert $5, $6 - li $4, \crout - rddsp $5 - dsp_assert $4, $5 - .endm - - # Set dsp control register <= crin - # Check if d == (inst ?, s) - # Check if crout == dsp control register - .macro dspck_dsio inst, d, s, crin, crout - li $4, \crin - wrdsp $4 - li $4, \s - \inst $6, $4 - li $7, \d - dsp_assert $6, $7 - li $4, \crout - rddsp $5 - dsp_assert $4, $5 - .endm - - # Set dsp control register <= crin - # Check if d == (inst ?, t, sa) - # Check if crout == dsp control register - .macro dspck_dtsaio inst, d, t, sa, crin, crout - li $4, \crin - wrdsp $4 - li $4, \t - \inst $6, $4, \sa - li $7, \d - dsp_assert $6, $7 - li $4, \crout - rddsp $5 - dsp_assert $4, $5 - .endm - - # Set dsp control register <= crin - # Check if d == (inst ?, t, sa) - .macro dspck_dtsai inst, d, t, sa, crin - li $4, \crin - wrdsp $4 - li $4, \t - \inst $6, $4, \sa - li $7, \d - dsp_assert $6, $7 - .endm - - # Set dsp control register <= crin - # Set $ac3 <= {hiin, loin} - # (inst $ac3, s, t) - # Check if {hiou, loou} == $ac3 - # Check if (crout & 0x80000) == (dsp control register & 0x80000) - .macro dspck_astio inst, hiin, loin, hiou, loou, s, t, crin, crout - li $4, \crin - wrdsp $4 - li $4, \hiin - mthi $4, $ac3 - li $4, \loin - mtlo $4, $ac3 - li $4, \s - li $5, \t - \inst $ac3, $4, $5 - li $4, \hiou - mfhi $5, $ac3 - dsp_assert $4, $5 - li $4, \loou - mflo $5, $ac3 - dsp_assert $4, $5 - li $4, \crout - and $4, $4, 0x80000 - rddsp $5 - and $5, $5, 0x80000 - dsp_assert $4, $5 - .endm - - # Set dsp control register <= crin - # Set $ac1 <= {hi, lo} - # Check if t == (inst ? $ac1, sa) - # Check if crout == dsp control register - .macro dspck_atsaio inst, hi, lo, t, sa, crin, crout - li $4, \crin - wrdsp $4 - li $4, \hi - mthi $4, $ac1 - li $4, \lo - mtlo $4, $ac1 - \inst $5, $ac1, \sa - li $6, \t - dsp_assert $5, $6 - li $4, \crout - rddsp $5 - dsp_assert $4, $5 - .endm - - # Set dsp control register <= crin - # Set acc <= {hiin, loin} - # (inst acc, s, t) - # Check if {hiou, loou} == acc - # Check if (crout & 0x80000) == (dsp control register & 0x80000) - .macro dspckacc_astio inst, acc, hiin, loin, hiou, loou, s, t, crin, crout - li $4, \crin - wrdsp $4 - li $4, \hiin - mthi $4, \acc - li $4, \loin - mtlo $4, \acc - li $4, \s - li $5, \t - \inst \acc, $4, $5 - li $4, \hiou - mfhi $5, \acc - dsp_assert $4, $5 - li $4, \loou - mflo $5, \acc - dsp_assert $4, $5 - li $4, \crout - and $4, $4, 0x80000 - rddsp $5 - and $5, $5, 0x80000 - dsp_assert $4, $5 - .endm - - # Set dsp control register <= crin - # Set $ac1 <= {hi, lo} - # Check if t == (inst ? $ac1, s) - # Check if crout == dsp control register - .macro dspck_atsio inst, hi, lo, t, s, crin, crout - li $4, \crin - wrdsp $4 - li $4, \hi - mthi $4, $ac1 - li $4, \lo - mtlo $4, $ac1 - li $4, \s - \inst $5, $ac1, $4 - li $6, \t - dsp_assert $5, $6 - li $4, \crout - rddsp $5 - dsp_assert $4, $5 - .endm - - # Set dsp control register <= (crin & crinmask) - # Set $ac2 <= {hi, lo} - # Check if t == (inst ? $ac2, size) - # Check if (crout & croutmask) == (dsp control register & croutmask) - .macro dspck_tasiimom inst, hi, lo, t, size, crin, crinmask, crout, croutmask - li $4, \crin - and $4, \crinmask - wrdsp $4 - li $4, \hi - mthi $4, $ac2 - li $4, \lo - mtlo $4, $ac2 - \inst $5, $ac2, \size - li $6, \t - dsp_assert $5, $6 - li $4, \crout - and $4, \croutmask - rddsp $5 - and $5, \croutmask - dsp_assert $4, $5 - .endm - - # Set dsp control register <= (crin & crinmask) - # Set $ac2 <= {hi, lo} - # Check if t == (inst ? $ac2, size) - .macro dspck_tasiim inst, hi, lo, t, size, crin, crinmask - li $4, \crin - and $4, \crinmask - wrdsp $4 - li $4, \hi - mthi $4, $ac2 - li $4, \lo - mtlo $4, $ac2 - \inst $5, $ac2, \size - li $6, \t - dsp_assert $5, $6 - .endm - - # Set dsp control register <= (crin & crinmask) - # Set $ac2 <= {hi, lo} - # Check if t == (inst ? $ac2, s) - # Check if (crout & croutmask) == (dsp control register & croutmask) - .macro dspck_tasimom inst, hi, lo, t, s, crin, crinmask, crout, croutmask - li $4, \crin - and $4, \crinmask - wrdsp $4 - li $4, \hi - mthi $4, $ac2 - li $4, \lo - mtlo $4, $ac2 - li $4, \s - \inst $5, $ac2, $4 - li $6, \t - dsp_assert $5, $6 - li $4, \crout - and $4, \croutmask - rddsp $5 - and $5, \croutmask - dsp_assert $4, $5 - .endm - - # Set dsp control register <= (crin & crinmask) - # Set $ac2 <= {hi, lo} - # Check if t == (inst ? $ac2, s) - .macro dspck_tasim inst, hi, lo, t, s, crin, crinmask - li $4, \crin - and $4, \crinmask - wrdsp $4 - li $4, \hi - mthi $4, $ac2 - li $4, \lo - mtlo $4, $ac2 - li $4, \s - \inst $5, $ac2, $4 - li $6, \t - dsp_assert $5, $6 - .endm - - # Set dsp control register <= crin - # Set $ac0 <= {hi, lo} - # (inst $ac0, shift) - # Check if $ac0 == {hio, loo} - # Check if crout == dsp control register - .macro dspck_asaio inst, hi, lo, hio, loo, shift, crin, crout - li $4, \crin - wrdsp $4 - li $4, \hi - mthi $4, $ac0 - li $4, \lo - mtlo $4, $ac0 - \inst $ac0, \shift - mfhi $5, $ac0 - li $6, \hio - dsp_assert $5, $6 - mflo $5, $ac0 - li $6, \loo - dsp_assert $5, $6 - li $4, \crout - rddsp $5 - dsp_assert $4, $5 - .endm - - # Set dsp control register <= crin - # Set $ac0 <= {hi, lo} - # (inst $ac0, s) - # Check if $ac0 == {hio, loo} - # Check if crout == dsp control register - .macro dspck_asio inst, hi, lo, hio, loo, s, crin, crout - li $4, \crin - wrdsp $4 - li $4, \hi - mthi $4, $ac0 - li $4, \lo - mtlo $4, $ac0 - li $4, \s - \inst $ac0, $4 - mfhi $5, $ac0 - li $6, \hio - dsp_assert $5, $6 - mflo $5, $ac0 - li $6, \loo - dsp_assert $5, $6 - li $4, \crout - rddsp $5 - dsp_assert $4, $5 - .endm - - # Set dsp control register <= crin - # Set $ac3 <= {hi, lo} - # Check if s == (inst ? $ac3) - # Check if $ac3 == {hio, loo} - # Check if crout == dsp control register - .macro dspck_saio inst, hi, lo, hio, loo, s, crin, crout - li $4, \crin - wrdsp $4 - li $4, \hi - mthi $4, $ac3 - li $4, \lo - mtlo $4, $ac3 - li $5, \s - \inst $5, $ac3 - mfhi $5, $ac3 - li $6, \hio - dsp_assert $5, $6 - mflo $5, $ac3 - li $6, \loo - dsp_assert $5, $6 - li $4, \crout - rddsp $5 - dsp_assert $4, $5 - .endm - - # Set dsp control register <= crin - # (wrdsp s, m) - # Check if crout == dsp control register - .macro dspck_wrdsp s, m, crin, crout - li $4, \crin - wrdsp $4 - li $5, \s - wrdsp $5, \m - li $6, \crout - rddsp $7 - dsp_assert $6, $7 - .endm - - # Set dsp control register <= crin - # Check if d == (rddsp ?, m) - .macro dspck_rddsp d, m, crin - li $4, \crin - wrdsp $4 - rddsp $5, \m - li $6, \d - dsp_assert $5, $6 - .endm - - # Check if d == (inst i(b)) - .macro dspck_load inst, d, i, b - li $4, \i - la $5, \b - \inst $6, $4($5) - li $7, \d - dsp_assert $6, $7 - .endm - - # Set dsp control register <= crin - # Check if bposge32 is taken or not as expected in r - # (1 => taken, 0 => not taken) - .macro dspck_bposge32 crin, r - li $4, \crin - wrdsp $4 - li $5, 1 - bposge32 1f - nop - li $5, 0 -1: - li $6, \r - dsp_assert $5, $6 - .endm - - # Check if tou == (inst tin, s) - .macro dspck_tsimm inst, tou, tin, s, sa - li $4, \s - li $5, \tin - \inst $5, $4, \sa - li $6, \tou - dsp_assert $5, $6 - .endm diff --git a/sim/testsuite/sim/mips/utils-fpu.inc b/sim/testsuite/sim/mips/utils-fpu.inc deleted file mode 100644 index 1cba87a..0000000 --- a/sim/testsuite/sim/mips/utils-fpu.inc +++ /dev/null @@ -1,104 +0,0 @@ -# MIPS simulator testsuite FPU utility functions. -# Copyright (C) 2004-2021 Free Software Foundation, Inc. -# Contributed by Chris Demetriou of Broadcom Corporation. -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . */ - - .macro enable_fpu fr - mfc0 $20, $12 - or $20, $20, (1 << 29) | (\fr << 26) - mtc0 $20, $20 - .endm - - ### - ### Data movement macros - ### - - .macro ld_fp_df r, v - .data -1: .double \v - .previous - ldc1 \r, 1b - .endm - - .macro ld_fp_di r, v - .data -1: .dword \v - .previous - ldc1 \r, 1b - .endm - - .macro ld_fp_sf r, v - .data -1: .float \v - .previous - lwc1 \r, 1b - .endm - - .macro ld_fp_si r, v - .data -1: .word \v - .previous - lwc1 \r, 1b - .endm - - - ### - ### FP condition code manipulation macros - ### - - .macro clrset_fp_cc clr, set - cfc1 $20, $31 - or $20, $20, (((\clr & 0xfe) << 24) | ((\clr & 0x01) << 23)) - xor $20, $20, (((\clr & 0xfe) << 24) | ((\clr & 0x01) << 23)) - or $20, $20, (((\set & 0xfe) << 24) | ((\set & 0x01) << 23)) - ctc1 $20, $31 - .endm - - .macro clr_fp_cc clr - clrset_fp_cc \clr, 0 - .endm - - .macro set_fp_cc set - clrset_fp_cc 0, \set - .endm - - .macro get_fp_cc r - .set push - .set noat - cfc1 $1, $31 - srl $1, $1, 23 - andi \r, $1, 0x1fc - andi $1, $1, 0x1 - srl \r, \r, 1 - or \r, \r, $1 - .set pop - .endm - - .macro ck_fp_cc v - get_fp_cc $20 - xori $20, $20, \v - bnez $20, _fail - nop - .endm - - .macro ckm_fp_cc v, mask - get_fp_cc $20 - xori $20, $20, \v - andi $20, $20, \mask - bnez $20, _fail - nop - .endm diff --git a/sim/testsuite/sim/mips/utils-mdmx.inc b/sim/testsuite/sim/mips/utils-mdmx.inc deleted file mode 100644 index 62634ef..0000000 --- a/sim/testsuite/sim/mips/utils-mdmx.inc +++ /dev/null @@ -1,71 +0,0 @@ -# MIPS simulator testsuite MDMX utility functions. -# Copyright (C) 2004-2021 Free Software Foundation, Inc. -# Contributed by Chris Demetriou of Broadcom Corporation. -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . */ - - .include "utils-fpu.inc" - - ### - ### Shared macros - ### - - # Enable MDMX: enable the FPU w/ FR=1, then set Status.MX - .macro enable_mdmx - enable_fpu 1 - mfc0 $20, $12 - or $20, $20, (1 << 24) - mtc0 $20, $12 - .endm - - - ### - ### .OB-format macros - ### - - .macro ld_ob r, v - .data -1: .dword \v - .previous - ldc1 \r, 1b - .endm - - .macro ck_ob r, v - .data -1: .dword \v - .previous - dmfc1 $20, \r - ld $21, 1b - bne $20, $21, _fail - nop - .endm - - .macro ld_acc_ob h, m, l - ld_ob $f20, \m - ld_ob $f21, \l - wacl.ob $f20, $f21 - ld_ob $f20, \h - wach.ob $f20 - .endm - - .macro ck_acc_ob h, m, l - rach.ob $f20 - ck_ob $f20, \h - racm.ob $f20 - ck_ob $f20, \m - racl.ob $f20 - ck_ob $f20, \l - .endm diff --git a/sim/testsuite/sim/mn10300/ChangeLog b/sim/testsuite/sim/mn10300/ChangeLog deleted file mode 100644 index d3f8b9d..0000000 --- a/sim/testsuite/sim/mn10300/ChangeLog +++ /dev/null @@ -1,3 +0,0 @@ -2015-04-05 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/sim/mn10300/allinsn.exp b/sim/testsuite/sim/mn10300/allinsn.exp deleted file mode 100644 index f8431e7..0000000 --- a/sim/testsuite/sim/mn10300/allinsn.exp +++ /dev/null @@ -1,15 +0,0 @@ -# mn10300 simulator testsuite - -if [istarget mn10300-*] { - # all machines - set all_machs "mn10300" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/mn10300/pass.s b/sim/testsuite/sim/mn10300/pass.s deleted file mode 100644 index b48fa4c..0000000 --- a/sim/testsuite/sim/mn10300/pass.s +++ /dev/null @@ -1,7 +0,0 @@ -# check that the sim doesn't die immediately. -# mach: mn10300 - -.include "testutils.inc" - - start - pass diff --git a/sim/testsuite/sim/mn10300/testutils.inc b/sim/testsuite/sim/mn10300/testutils.inc deleted file mode 100644 index 6418817..0000000 --- a/sim/testsuite/sim/mn10300/testutils.inc +++ /dev/null @@ -1,63 +0,0 @@ -# MACRO: exit - .macro exit nr - mov \nr, d1; - # Trap function 1: exit(). - mov 1, d0; - syscall; - .endm - -# MACRO: pass -# Write 'pass' to stdout and quit - .macro pass - # Trap function 5: write(). - mov 5, d0; - # Use stdout. - mov 1, d1; - # Point to the string. - mov 1f, a0; - mov a0, (12, sp); - # Number of bytes to write. - mov 5, d3; - mov d3, (16, sp); - # Trigger OS trap. - syscall; - exit 0 - .data - 1: .asciz "pass\n" - .endm - -# MACRO: fail -# Write 'fail' to stdout and quit - .macro fail - # Trap function 5: write(). - mov 5, d0; - # Use stdout. - mov 1, d1; - # Point to the string. - mov 1f, a0; - mov a0, (12, sp); - # Number of bytes to write. - mov 5, d3; - mov d3, (16, sp); - # Trigger OS trap. - syscall; - exit 0 - .data - 1: .asciz "fail\n" - .endm - -# MACRO: start -# All assembler tests should start with a call to "start" - .macro start - .data -.global _stack -_stack: - .rept 8 - .long 0 - .endr - .text -.global _start -_start: - mov _stack, a0; - mov a0, sp; - .endm diff --git a/sim/testsuite/sim/moxie/ChangeLog b/sim/testsuite/sim/moxie/ChangeLog deleted file mode 100644 index d3f8b9d..0000000 --- a/sim/testsuite/sim/moxie/ChangeLog +++ /dev/null @@ -1,3 +0,0 @@ -2015-04-05 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/sim/moxie/allinsn.exp b/sim/testsuite/sim/moxie/allinsn.exp deleted file mode 100644 index 1a6af8b..0000000 --- a/sim/testsuite/sim/moxie/allinsn.exp +++ /dev/null @@ -1,15 +0,0 @@ -# moxie simulator testsuite - -if [istarget moxie-*] { - # all machines - set all_machs "moxie" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/moxie/pass.s b/sim/testsuite/sim/moxie/pass.s deleted file mode 100644 index 4d8e385..0000000 --- a/sim/testsuite/sim/moxie/pass.s +++ /dev/null @@ -1,7 +0,0 @@ -# check that the sim doesn't die immediately. -# mach: moxie - -.include "testutils.inc" - - start - pass diff --git a/sim/testsuite/sim/moxie/testutils.inc b/sim/testsuite/sim/moxie/testutils.inc deleted file mode 100644 index dbdcf7c..0000000 --- a/sim/testsuite/sim/moxie/testutils.inc +++ /dev/null @@ -1,46 +0,0 @@ -# MACRO: exit - .macro exit nr - ldi.l $r0, \nr; - # Trap function 1: exit(). - swi 1; - .endm - -# MACRO: pass -# Write 'pass' to stdout and quit - .macro pass - # Use stdout. - ldi.b $r0, 1; - # Point to the string. - ldi.l $r1, 1f; - # Number of bytes to write. - ldi.s $r2, 5; - # Trap function 5: write(). - swi 5; - exit 0 - .data - 1: .asciz "pass\n" - .endm - -# MACRO: fail -# Write 'fail' to stdout and quit - .macro fail - # Use stdout. - ldi.b $r0, 1; - # Point to the string. - ldi.l $r1, 1f; - # Number of bytes to write. - ldi.s $r2, 5; - # Trap function 5: write(). - swi 5; - exit 0 - .data - 1: .asciz "fail\n" - .endm - -# MACRO: start -# All assembler tests should start with a call to "start" - .macro start - .text -.global _start -_start: - .endm diff --git a/sim/testsuite/sim/msp430/ChangeLog b/sim/testsuite/sim/msp430/ChangeLog deleted file mode 100644 index cd6b195..0000000 --- a/sim/testsuite/sim/msp430/ChangeLog +++ /dev/null @@ -1,17 +0,0 @@ -2020-08-05 Jozef Lawrynowicz - - * mpyull_hwmult.s: New test. - -2020-01-22 Jozef Lawrynowicz - - * rrux.s: New test. - -2016-01-05 Nick Clifton - - * testutils.inc (__pass): Use the LMA addresses of the _passmsg - symbol. - (__fail): Likewise. - -2014-03-10 Mike Frysinger - - * add.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/sim/msp430/add.s b/sim/testsuite/sim/msp430/add.s deleted file mode 100644 index 76247ed..0000000 --- a/sim/testsuite/sim/msp430/add.s +++ /dev/null @@ -1,20 +0,0 @@ -# check that basic add insn works. -# mach: msp430 - -.include "testutils.inc" - - start - - mov #10, r4 - add #23, r4 - cmp #33, r4 - jne 1f - - cmp #32, r4 - jlo 1f - - cmp #34, r4 - jhs 1f - - pass -1: fail diff --git a/sim/testsuite/sim/msp430/allinsn.exp b/sim/testsuite/sim/msp430/allinsn.exp deleted file mode 100644 index affa8ae..0000000 --- a/sim/testsuite/sim/msp430/allinsn.exp +++ /dev/null @@ -1,15 +0,0 @@ -# msp430 simulator testsuite - -if [istarget msp430-*] { - # all machines - set all_machs "msp430" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/msp430/mpyull_hwmult.s b/sim/testsuite/sim/msp430/mpyull_hwmult.s deleted file mode 100644 index 911fa11..0000000 --- a/sim/testsuite/sim/msp430/mpyull_hwmult.s +++ /dev/null @@ -1,55 +0,0 @@ -# Test that unsigned widening multiplication of 32-bit operands to produce a -# 64-bit result is simulated correctly, when using 32-bit or F5series hardware -# multiply functionality. -# 0xffff fffc * 0x2 = 0x1 ffff fff8 -# mach: msp430 - -# 32-bit hwmult register addresses -.set MPY32L, 0x0140 -.set MPY32H, 0x0142 -.set OP2L, 0x0150 -.set OP2H, 0x0152 -.set RES0, 0x0154 -.set RES1, 0x0156 -.set RES2, 0x0158 -.set RES3, 0x015A - -# F5series hwmult register addresses -.set MPY32L_F5, 0x04D0 -.set MPY32H_F5, 0x04D2 -.set OP2L_F5, 0x04E0 -.set OP2H_F5, 0x04E2 -.set RES0_F5, 0x04E4 -.set RES1_F5, 0x04E6 -.set RES2_F5, 0x04E8 -.set RES3_F5, 0x04EA - -.include "testutils.inc" - - start - - ; Test 32bit hwmult - MOV.W #2, &MPY32L ; Load operand 1 Low into multiplier - MOV.W #0, &MPY32H ; Load operand 1 High into multiplier - MOV.W #-4, &OP2L ; Load operand 2 Low into multiplier - MOV.W #-1, &OP2H ; Load operand 2 High, trigger MPY - - CMP.W #-8, &RES0 { JNE .L5 - CMP.W #-1, &RES1 { JNE .L5 - CMP.W #1, &RES2 { JNE .L5 - CMP.W #0, &RES3 { JNE .L5 - - ; Test f5series hwmult - MOV.W #2, &MPY32L_F5 - MOV.W #0, &MPY32H_F5 - MOV.W #-4, &OP2L_F5 - MOV.W #-1, &OP2H_F5 - - CMP.W #-8, &RES0_F5 { JNE .L5 - CMP.W #-1, &RES1_F5 { JNE .L5 - CMP.W #1, &RES2_F5 { JNE .L5 - CMP.W #0, &RES3_F5 { JEQ .L6 -.L5: - fail -.L6: - pass diff --git a/sim/testsuite/sim/msp430/rrux.s b/sim/testsuite/sim/msp430/rrux.s deleted file mode 100644 index 07fc8d5..0000000 --- a/sim/testsuite/sim/msp430/rrux.s +++ /dev/null @@ -1,14 +0,0 @@ -# check that rrux (synthesized as rrc with ZC bit set) works. -# mach: msp430 - -.include "testutils.inc" - - start - - setc ; set the carry bit to ensure ZC bit is obeyed - mov.w #16, r10 - rrux.w r10 - cmp.w #8, r10 - jeq 1f - fail - 1: pass diff --git a/sim/testsuite/sim/msp430/testutils.inc b/sim/testsuite/sim/msp430/testutils.inc deleted file mode 100644 index 1ddef23..0000000 --- a/sim/testsuite/sim/msp430/testutils.inc +++ /dev/null @@ -1,100 +0,0 @@ -# MACRO: start -# All assembler tests should start with a call to "start" - .macro start - .text - - # Skip over these inlined funcs. - jmp __start; - - .global __pass - .type __pass, function -__pass: - # Note - we cannot just invoke: - # - # write 1, _passmsg, 5 - # - # here because _passmsg contains the run-time (VMA) address of - # the pass string (probably 0x500) not the load-time (LMA) - # address (probably 0x804c). Normally using the VMA address - # would be the correct thing to do - *if* there was some start - # up code which copied data from LMA to VMA. But we have no - # start up code, so the data still resides at the LMA - # address. Hence we use __romdatastart instead. - # - # Note - we are cheating because the address that we pass to - # "write" should actually be: - # - # __romdatastart + (_passmsg - __datastart) - # - # but the assembler cannot cope with this expression. So we - # cheat and use the fact that we know that _passmsg is the - # first string in the .data section and so (_passmsg - - # __datastart) evaluates to zero. - - write 1, __romdatastart, 5 - exit 0 - - .global __fail - .type __fail, function -__fail: - # Note - see above. - # - # write 1, _failmsg, 5 - # - # This time we use the fact that _passmsg is aligned to a - # 16 byte boundary to work out that (_failmsg - __datastart) - # evaluates to 0x10. - - write 1, __romdatastart + 0x10, 5 - exit 1 - - .data -_passmsg: - .ascii "pass\n" - .align 4 - -_failmsg: - .ascii "fail\n" - .align 4 - - .text - .global __start - .type __start, function -__start: - .endm - -# MACRO: system_call -# Make a libgloss/Linux system call - .macro system_call nr:req - call #(0x180|\nr); - .endm - -# MACRO: exit -# Quit the current test - .macro exit rc:req - mov #\rc, r12 - system_call 1 - .endm - -# MACRO: pass -# Write 'pass' to stdout via syscalls and quit; -# meant for non-OS operating environments - .macro pass - jmp __pass; - .endm - -# MACRO: fail -# Write 'fail' to stdout via syscalls and quit; -# meant for non-OS operating environments - .macro fail - jmp __fail; - .endm - -# MACRO: write -# Just like the write() C function; uses system calls - .macro write fd:req, buf:req, count:req - mov #\fd, r12; - mov #\buf, r13; - mov #\count, r14; - system_call 5 - .endm diff --git a/sim/testsuite/sim/or1k/ChangeLog b/sim/testsuite/sim/or1k/ChangeLog deleted file mode 100644 index f562380..0000000 --- a/sim/testsuite/sim/or1k/ChangeLog +++ /dev/null @@ -1,46 +0,0 @@ -2019-06-13 Stafford Horne - - * fpu-unordered.S: New file. - * fpu64a32-unordered.S: New file. - -2019-06-13 Stafford Horne - - * adrp.S: New file. - -2019-06-13 Stafford Horne - - * fpu64a32.S: New file. - -2018-10-05 Stafford Horne - - * div.S: Fix tests to match correct overflow/carry semantics. - * mul.S: Likewise. - -2017-12-12 Peter Gavin - Stafford Horne - - * add.S: New file. - * alltests.exp: New file. - * and.S: New file. - * basic.S: New file. - * div.S: New file. - * ext.S: New file. - * find.S: New file. - * flag.S: New file. - * fpu.S: New file. - * jump.S: New file. - * load.S: New file. - * mac.S: New file. - * mfspr.S: New file. - * mul.S: New file. - * or.S: New file. - * or1k-asm-test-env.h: New file. - * or1k-asm-test-helpers.h: New file. - * or1k-asm-test.h: New file. - * or1k-asm.h: New file. - * or1k-test.ld: New file. - * ror.S: New file. - * shift.S: New file. - * spr-defs.h: New file. - * sub.S: New file. - * xor.S: New file. diff --git a/sim/testsuite/sim/or1k/add.S b/sim/testsuite/sim/or1k/add.S deleted file mode 100644 index 2cff73d..0000000 --- a/sim/testsuite/sim/or1k/add.S +++ /dev/null @@ -1,639 +0,0 @@ -/* Tests instructions l.add, l.addc, l.addi and l.addic. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x00000001);\n -# output: report(0x00000002);\n -# output: report(0x00000003);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000001);\n -# output: report(0x00000002);\n -# output: report(0x00000003);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0xfffffffe);\n -# output: report(0xfffffffd);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x40000000);\n -# output: report(0x3fffffff);\n -# output: report(0x7fffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x40000000);\n -# output: report(0x40000000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xc0000000);\n -# output: report(0xc0000000);\n -# output: report(0x80000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xbfffffff);\n -# output: report(0xbfffffff);\n -# output: report(0x7ffffffe);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x40000000);\n -# output: report(0x40000000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0xfffffffe);\n -# output: report(0xfffffffd);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xbfffffff);\n -# output: report(0xbfffffff);\n -# output: report(0x7ffffffe);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x00000001);\n -# output: report(0x00000002);\n -# output: report(0x00000003);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0xfffffffe);\n -# output: report(0xfffffffd);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x40000000);\n -# output: report(0x3fffffff);\n -# output: report(0x7fffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x40000000);\n -# output: report(0x3fffffff);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x40000000);\n -# output: report(0x40000000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xc0000000);\n -# output: report(0xc0000000);\n -# output: report(0x80000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xc0000000);\n -# output: report(0xbfffffff);\n -# output: report(0x80000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xbfffffff);\n -# output: report(0xbfffffff);\n -# output: report(0x7ffffffe);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x40000000);\n -# output: report(0x40000000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x40000000);\n -# output: report(0x3fffffff);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0xfffffffe);\n -# output: report(0xfffffffd);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xbfffffff);\n -# output: report(0xbfffffff);\n -# output: report(0x7ffffffe);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x00000001);\n -# output: report(0x00000002);\n -# output: report(0x00000003);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000001);\n -# output: report(0x00000002);\n -# output: report(0x00000003);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0x0000fffe);\n -# output: report(0xfffffffd);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x7fff8000);\n -# output: report(0x00007fff);\n -# output: report(0x7fffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x7fffc000);\n -# output: report(0x00004000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x80008000);\n -# output: report(0x00008000);\n -# output: report(0x80000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x80007fff);\n -# output: report(0x00008000);\n -# output: report(0x7fffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x7fffc000);\n -# output: report(0x00004000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0x0000fffe);\n -# output: report(0xfffffffd);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x80007fff);\n -# output: report(0x00008000);\n -# output: report(0x7fffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x00000001);\n -# output: report(0x00000002);\n -# output: report(0x00000003);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0x0000fffe);\n -# output: report(0xfffffffd);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x7fff8000);\n -# output: report(0x00007fff);\n -# output: report(0x7fffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x7fff8000);\n -# output: report(0x00007fff);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x7fffc000);\n -# output: report(0x00004000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000000);\n -# output: report(0x0000ffff);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x80008000);\n -# output: report(0x00008000);\n -# output: report(0x80000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x80007fff);\n -# output: report(0x00008000);\n -# output: report(0x80000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x80007fff);\n -# output: report(0x00008000);\n -# output: report(0x7fffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x7fffc000);\n -# output: report(0x00004000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x7fffc000);\n -# output: report(0x00003fff);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0x0000fffe);\n -# output: report(0xfffffffd);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000000);\n -# output: report(0x0000ffff);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x80007fff);\n -# output: report(0x00008000);\n -# output: report(0x7fffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - STANDARD_TEST_ENVIRONMENT - - .section .exception_vectors - - /* Range exception. */ - .org 0xb00 - - /* The handling is a bit dubious at present. We just patch the - instruction with l.nop and restart. This will go wrong in branch - delay slots. But we don't have those in this test. */ - l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE - PUSH r2 - PUSH r3 - /* Save the address of the instruction that caused the problem. */ - MOVE_FROM_SPR r2, SPR_EPCR_BASE - LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */ - l.sw 0(r2), r3 - POP r3 - POP r2 - l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE - l.rfe - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test l.add */ - - /* Add two small positive numbers */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 1, 2 - - /* The carry flag should be ignored. */ - TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.add, 1, 2 - - /* Add two small negative numbers, which should set the carry flag - but not the overflow flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, -1, -2 - - /* Add two quite large positive numbers. Should set neither the - overflow nor the carry flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, \ - 0x3fffffff - - /* Add two large positive numbers. Should set the overflow, but - not the carry flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, \ - 0x40000000 - - /* Add two quite large negative numbers. Should set the carry, but - not the overflow flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, -1073741824, \ - -1073741824 /* -1073741824 = 0xC0000000 */ - - /* Add two large negative numbers. Should set both the overflow - and carry flags. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xbfffffff, \ - 0xbfffffff - - /* Check that range exceptions are triggered. */ - - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Check that an overflow alone causes a RANGE Exception. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, \ - 0x40000000 - - /* Check that a carry alone does not cause a RANGE Exception. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xffffffff, \ - 0xfffffffe - - /* Check that carry and overflow together cause an exception. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xbfffffff, \ - 0xbfffffff - - CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Test l.addc */ - - /* Add two small positive numbers */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 1, 2 - - /* Add two small negative numbers. Sets the carry flag but not the - overflow flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1, -2 - - /* Add two quite large positive numbers. Should set neither the - overflow nor the carry flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, \ - 0x3fffffff - - /* Add two quite large positive numbers with a carry in. Should - set the overflow but not the carry flag. */ - TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x40000000, \ - 0x3fffffff - - /* Add two large positive numbers. Should set the overflow, but - not the carry flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, \ - 0x40000000 - - /* Add the largest unsigned value to zero with a carry. This - potentially can break a simplistic test for carry that does not - consider the carry flag properly. Do it both ways around. */ - TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, -1, 0 - TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0, -1 - - /* Add two quite large negative numbers. Should set the carry, but - not the overflow flag. Here -1073741824 is 0xC0000000. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1073741824, \ - -1073741824 - - /* Add two quite large negative numbers that would overflow, with a - carry that just avoids the overflow. Should set the carry, but - not the overflow flag. Here -1073741824 is 0xC0000000 and - -1073741825 is 0xBFFFFFFF. */ - TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, -1073741824, \ - -1073741825 - - /* Add two large negative numbers. Should set both the overflow - and carry flags. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1073741825, \ - -1073741825 - - /* Check that range exceptions are triggered. */ - - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Check that an overflow alone causes a RANGE Exception, even when - it is the carry that causes the overflow. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, \ - 0x40000000 - TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x40000000, \ - 0x3fffffff - - /* Check that a carry alone does not cause a RANGE Exception, even - when it is the carry that causes the overflow. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0xffffffff, \ - 0xfffffffe - TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x00000000, \ - 0xffffffff - - /* Check that carry and overflow together cause an exception. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0xbfffffff, \ - 0xbfffffff - - CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Test l.addi */ - - /* Add two small positive numbers */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 1, 2 - - /* Check carry in is ignored. */ - TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addi, 1, 2 - - /* Add two small negative numbers. Sets the carry flag but not the - overflow flag. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0xffffffff, \ - 0xfffe - - /* Add two quite large positive numbers. Should set neither the - overflow nor the carry flag. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fff8000, \ - 0x7fff - - /* Add two large positive numbers. Should set the overflow, but - not the carry flag. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fffc000, \ - 0x4000 - - /* Add two quite large negative numbers. Should set the carry, but - not the overflow flag. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80008000, \ - 0x8000 - - /* Add two large negative numbers. Should set both the overflow - and carry flags. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80007fff, \ - 0x8000 - - /* Check that range exceptions are triggered. */ - - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Check that an overflow alone causes a RANGE Exception. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fffc000, \ - 0x4000 - - /* Check that a carry alone does not cause a RANGE Exception. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0xffffffff, \ - 0xfffe - - /* Check that carry and overflow together cause an exception. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80007fff, \ - 0x8000 - - CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Test l.addi */ - - /* Add two small positive numbers */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 1, 2 - - /* Add two small negative numbers. Sets the carry flag but not the - overflow flag. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0xffffffff, \ - 0xfffe - - /* Add two quite large positive numbers. Should set neither the - overflow nor the carry flag. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fff8000, \ - 0x7fff - - /* Add two quite large positive numbers with a carry in. Should - set the overflow but not the carry flag. */ - TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x7fff8000, 0x7fff - - /* Add two large positive numbers. Should set the overflow, but - not the carry flag. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fffc000, \ - 0x4000 - - /* Add the largest unsigned value to zero with a carry. This - potentially can break a simplistic test for carry that does not - consider the carry flag properly. Do it both ways around. */ - TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0xffffffff, 0x0000 - TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x00000000, 0xffff - - /* Add two quite large negative numbers. Should set the carry, but - not the overflow flag. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80008000, \ - 0x8000 - - /* Add two quite large negative numbers that would overflow, with a - carry that just avoids the overflow. This should set the carry, - but not the overflow flag. */ - TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x80007fff, 0x8000 - - /* Add two large negative numbers. Should set both the overflow - and carry flags. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80007fff, \ - 0x8000 - - /* Check that range exceptions are triggered. */ - - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Check that an overflow alone causes a RANGE Exception, even when - it is the carry that causes the overflow. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fffc000, \ - 0x4000 - TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x7fffc000, 0x3fff - - /* Check that a carry alone does not cause a RANGE Exception, even - when it is the carry that causes the overflow. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0xffffffff, \ - 0xfffe - TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x00000000, 0xffff - - /* Check that carry and overflow together cause an exception. */ - TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80007fff, \ - 0x8000 - - CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/adrp.S b/sim/testsuite/sim/or1k/adrp.S deleted file mode 100644 index c0883b6..0000000 --- a/sim/testsuite/sim/or1k/adrp.S +++ /dev/null @@ -1,73 +0,0 @@ -/* Tests the load page address instruction. - - Copyright (C) 2019-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x00002064);\n -# output: report(0x00012138);\n -# output: report(0x00002000);\n -# output: report(0x00012000);\n -# output: report(0x00002000);\n -# output: report(0x00014000);\n -# output: report(0x00000000);\n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - STANDARD_TEST_ENVIRONMENT - - .section .data - .org 0x10000 - .align 4 - .type pi, @object - .size pi, 4 -pi: - .float 3.14159 - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Print out the PC. To compare with that loaded by l.adrp. */ - l.jal capture_pc - l.nop -capture_pc: - REPORT_REG_TO_CONSOLE r9 - - /* Print out our data address to compared with l.adrp offset. */ - l.movhi r11, ha(pi) - l.addi r11, r11, lo(pi) - REPORT_REG_TO_CONSOLE r11 - - /* Test l.adrp with symbols, loads page of symbol to register. */ - l.adrp r4, start_tests - REPORT_REG_TO_CONSOLE r4 - - l.adrp r4, pi - REPORT_REG_TO_CONSOLE r4 - - /* Test l.adrp with immediate, immediate is the page offset. */ - l.adrp r4, 0x0 - REPORT_REG_TO_CONSOLE r4 - - l.adrp r4, 0x12000 - REPORT_REG_TO_CONSOLE r4 - - l.adrp r4, -0x2000 - REPORT_REG_TO_CONSOLE r4 - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/alltests.exp b/sim/testsuite/sim/or1k/alltests.exp deleted file mode 100644 index dd08fbc..0000000 --- a/sim/testsuite/sim/or1k/alltests.exp +++ /dev/null @@ -1,34 +0,0 @@ -# OR1K simulator testsuite. -# -# Copyright 2017-2021 Free Software Foundation, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -if [istarget or1k*-*-*] { - - set all_machs "or1k" - - global global_ld_options - set global_ld_options "-T $srcdir/$subdir/or1k-test.ld" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.S]] { - - if ![runtest_file_p $runtests $src] { - continue - } - - run_sim_test $src $all_machs - } - -} diff --git a/sim/testsuite/sim/or1k/and.S b/sim/testsuite/sim/or1k/and.S deleted file mode 100644 index 8003d38..0000000 --- a/sim/testsuite/sim/or1k/and.S +++ /dev/null @@ -1,198 +0,0 @@ -/* Tests instructions l.and, l.andi. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0xffffffff);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0xaaaaaaaa);\n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x55555555);\n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0xb38f0f83);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0xc4c70f07);\n -# output: report(0x44400004);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x38f0f83b);\n -# output: report(0x30800803);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0x0000ffff);\n -# output: report(0x0000ffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x0000aaaa);\n -# output: report(0x0000aaaa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x00005555);\n -# output: report(0x00005555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x00005555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000f83);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000f07);\n -# output: report(0x00000004);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000f83b);\n -# output: report(0x00000803);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - STANDARD_TEST_ENVIRONMENT - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Always set OVE. We should never trigger an exception, even if - this bit is set. */ - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Test the l.and instruction with a range of operands. */ - TEST_INST_I32_I32 l.and, 0x00000000, 0x00000000 - TEST_INST_I32_I32 l.and, 0xffffffff, 0xffffffff - TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0x00000000 - TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0xaaaaaaaa - TEST_INST_I32_I32 l.and, 0x55555555, 0x00000000 - TEST_INST_I32_I32 l.and, 0x55555555, 0x55555555 - TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0x55555555 - TEST_INST_I32_I32 l.and, 0x4c70f07c, 0xb38f0f83 - TEST_INST_I32_I32 l.and, 0x4c70f07c, 0xc4c70f07 - TEST_INST_I32_I32 l.and, 0xb38f0f83, 0x38f0f83b - - /* Test the l.andi instruction with a range of operands. */ - TEST_INST_I32_I16 l.andi, 0x00000000, 0x0000 - TEST_INST_I32_I16 l.andi, 0xffffffff, 0xffff - TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0x0000 - TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0xaaaa - TEST_INST_I32_I16 l.andi, 0x55555555, 0x0000 - TEST_INST_I32_I16 l.andi, 0x55555555, 0x5555 - TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0x5555 - TEST_INST_I32_I16 l.andi, 0x4c70f07c, 0x0f83 - TEST_INST_I32_I16 l.andi, 0x4c70f07c, 0x0f07 - TEST_INST_I32_I16 l.andi, 0xb38f0f83, 0xf83b - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/basic.S b/sim/testsuite/sim/or1k/basic.S deleted file mode 100644 index 02faebb..0000000 --- a/sim/testsuite/sim/or1k/basic.S +++ /dev/null @@ -1,522 +0,0 @@ -/* Tests some basic CPU instructions. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0xffff0012);\n -# output: report(0x12352af7);\n -# output: report(0x7ffffffe);\n -# output: report(0xffffa5a7);\n -# output: report(0x000fffff);\n -# output: report(0x00002800);\n -# output: report(0x00000009);\n -# output: report(0xdeaddead);\n -# output: report(0xffff0000);\n -# output: report(0x12345678);\n -# output: report(0xabcdf0bd);\n -# output: exit(0)\n - -#include "or1k-asm-test-env.h" - -#define FIRST_RAM_ADDR 0x00000000 - - STANDARD_TEST_HEADER - - /* Early test begin. */ - - /* Do this test upfront, as it modifies STACK_POINTER_R1. */ - - l.addi r1 , r0 , 0x1 - l.addi r2 , r1 , 0x2 - l.addi r3 , r2 , 0x4 - l.addi r4 , r3 , 0x8 - l.addi r5 , r4 , 0x10 - l.addi r6 , r5 , 0x20 - l.addi r7 , r6 , 0x40 - l.addi r8 , r7 , 0x80 - l.addi r9 , r8 , 0x100 - l.addi r10, r9 , 0x200 - l.addi r11, r10, 0x400 - l.addi r12, r11, 0x800 - l.addi r13, r12, 0x1000 - l.addi r14, r13, 0x2000 - l.addi r15, r14, 0x4000 - l.addi r16, r15, 0x8000 - - l.sub r31, r0 , r1 - l.sub r30, r31, r2 - l.sub r29, r30, r3 - l.sub r28, r29, r4 - l.sub r27, r28, r5 - l.sub r26, r27, r6 - l.sub r25, r26, r7 - l.sub r24, r25, r8 - l.sub r23, r24, r9 - l.sub r22, r23, r10 - l.sub r21, r22, r11 - l.sub r20, r21, r12 - l.sub r19, r20, r13 - l.sub r18, r19, r14 - l.sub r17, r18, r15 - l.sub r16, r17, r16 - - /* We cannot use REPORT_REG_TO_CONSOLE here, as the stack is not - set up yet. */ - MOVE_REG NOP_REPORT_R3, r16 - REPORT_TO_CONSOLE /* Should be 0xffff0012 */ - - /* Early test end. */ - - STANDARD_TEST_BODY - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Read and write from RAM. */ - - LOAD_IMMEDIATE r31, FIRST_RAM_ADDR - l.sw 0(r31), r16 - - l.movhi r3,0x1234 - l.ori r3,r3,0x5678 - - l.sw 4(r31),r3 - - l.lbz r4,4(r31) - l.add r8,r8,r4 - l.sb 11(r31),r4 - l.lbz r4,5(r31) - l.add r8,r8,r4 - l.sb 10(r31),r4 - l.lbz r4,6(r31) - l.add r8,r8,r4 - l.sb 9(r31),r4 - l.lbz r4,7(r31) - l.add r8,r8,r4 - l.sb 8(r31),r4 - - l.lbs r4,8(r31) - l.add r8,r8,r4 - l.sb 7(r31),r4 - l.lbs r4,9(r31) - l.add r8,r8,r4 - l.sb 6(r31),r4 - l.lbs r4,10(r31) - l.add r8,r8,r4 - l.sb 5(r31),r4 - l.lbs r4,11(r31) - l.add r8,r8,r4 - l.sb 4(r31),r4 - - l.lhz r4,4(r31) - l.add r8,r8,r4 - l.sh 10(r31),r4 - l.lhz r4,6(r31) - l.add r8,r8,r4 - l.sh 8(r31),r4 - - l.lhs r4,8(r31) - l.add r8,r8,r4 - l.sh 6(r31),r4 - l.lhs r4,10(r31) - l.add r8,r8,r4 - l.sh 4(r31),r4 - - l.lwz r4,4(r31) - l.add r8,r8,r4 - - REPORT_REG_TO_CONSOLE r8 /* Should be 0x12352af7 */ - - l.lwz r9,0(r31) - l.add r8,r9,r8 - l.sw 0(r31),r8 - - /* Test arithmetic operations. */ - - l.addi r3,r0,1 - l.addi r4,r0,2 - l.addi r5,r0,-1 - l.addi r6,r0,-1 - l.addi r8,r0,0 - - l.sub r7,r5,r3 - l.sub r8,r3,r5 - l.add r8,r8,r7 - - l.div r7,r7,r4 - l.add r9,r3,r4 - l.mul r7,r9,r7 - l.divu r7,r7,r4 - l.add r8,r8,r7 - - REPORT_REG_TO_CONSOLE r8 /* Should be 0x7ffffffe */ - - l.lwz r9,0(r31) - l.add r8,r9,r8 - l.sw 0(r31),r8 - - /* Test logical operations. */ - - l.addi r3,r0,1 - l.addi r4,r0,2 - l.addi r5,r0,-1 - l.addi r6,r0,-1 - l.addi r8,r0,0 - - l.andi r8,r8,1 - l.and r8,r8,r3 - - l.xori r8,r5,0xa5a5 - l.xor r8,r8,r5 - - l.ori r8,r8,2 - l.or r8,r8,r4 - - REPORT_REG_TO_CONSOLE r8 /* Should be 0xffffa5a7 */ - - l.lwz r9,0(r31) - l.add r8,r9,r8 - l.sw 0(r31),r8 - - /* Test shifting operations. */ - - l.addi r3,r0,1 - l.addi r4,r0,2 - l.addi r5,r0,-1 - l.addi r6,r0,-1 - l.addi r8,r0,0 - - l.slli r8,r5,6 - l.sll r8,r8,r4 - - l.srli r8,r8,6 - l.srl r8,r8,r4 - - l.srai r8,r8,2 - l.sra r8,r8,r4 - - REPORT_REG_TO_CONSOLE r8 /* Should be 0x000fffff */ - - l.lwz r9,0(r31) - l.add r8,r9,r8 - l.sw 0(r31),r8 - - /* Test the CPU flag. */ - - l.addi r3,r0,1 - l.addi r4,r0,-2 - l.addi r8,r0,0 - - l.sfeq r3,r3 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfeq r3,r4 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfeqi r3,1 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfeqi r3,-2 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfne r3,r3 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfne r3,r4 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfnei r3,1 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfnei r3,-2 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgtu r3,r3 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgtu r3,r4 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgtui r3,1 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgtui r3,-2 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgeu r3,r3 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgeu r3,r4 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgeui r3,1 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgeui r3,-2 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfltu r3,r3 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfltu r3,r4 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfltui r3,1 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfltui r3,-2 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfleu r3,r3 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfleu r3,r4 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfleui r3,1 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfleui r3,-2 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgts r3,r3 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgts r3,r4 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgtsi r3,1 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgtsi r3,-2 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfges r3,r3 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfges r3,r4 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgesi r3,1 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfgesi r3,-2 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sflts r3,r3 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sflts r3,r4 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfltsi r3,1 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfltsi r3,-2 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfles r3,r3 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sfles r3,r4 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sflesi r3,1 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - l.sflesi r3,-2 - l.mfspr r5,r0,17 - l.andi r4,r5,0x200 - l.add r8,r8,r4 - - REPORT_REG_TO_CONSOLE r8 /* Should be 0x00002800 */ - - l.lwz r9,0(r31) - l.add r8,r9,r8 - l.sw 0(r31),r8 - - /* Test the jump instructions. */ - - l.addi r8,r0,0 - - OR1K_DELAYED ( - OR1K_INST (l.addi r8,r8,1), - OR1K_INST (l.j _T1) - ) - -_T2: OR1K_DELAYED ( - OR1K_INST (l.addi r8,r8,1), - OR1K_INST (l.jr r9) - ) - -_T1: OR1K_DELAYED ( - OR1K_INST (l.addi r8,r8,1), - OR1K_INST (l.jal _T2) - ) - - l.sfeqi r0,0 - OR1K_DELAYED ( - OR1K_INST (l.addi r8,r8,1), - OR1K_INST (l.bf _T3) - ) - -_T3: l.sfeqi r0,1 - OR1K_DELAYED ( - OR1K_INST (l.addi r8,r8,1), - OR1K_INST (l.bf _T4) - ) - - l.addi r8,r8,1 - -_T4: l.sfeqi r0,0 - OR1K_DELAYED ( - OR1K_INST (l.addi r8,r8,1), - OR1K_INST (l.bnf _T5) - ) - - l.addi r8,r8,1 - -_T5: l.sfeqi r0,1 - OR1K_DELAYED ( - OR1K_INST (l.addi r8,r8,1), - OR1K_INST (l.bnf _T6) - ) - - l.addi r8,r8,1 - -_T6: l.movhi r3,hi (_T7) - l.ori r3,r3,lo (_T7) - l.mtspr r0,r3,32 - l.mfspr r5,r0,17 - l.mtspr r0,r5,64 - l.rfe - l.addi r8,r8,1 /* l.rfe should not have a delay slot */ - - l.addi r8,r8,1 - -_T7: REPORT_REG_TO_CONSOLE r8 /* Should be 0x000000009 */ - - l.lwz r9,0(r31) - l.add r8,r9,r8 - l.sw 0(r31),r8 - - l.lwz r9,0(r31) - l.movhi r3,0x4c69 - l.ori r3,r3,0xe5f7 - l.add r8,r8,r3 - - REPORT_REG_TO_CONSOLE r8 /* Should be 0xdeaddead */ - - /* Test l.movhi, on 32-bit implementations it should not - sign-extend anything. */ - - l.movhi r3, -1 - REPORT_REG_TO_CONSOLE r3 - - /* Test l.cmov */ - - LOAD_IMMEDIATE r14, 0x12345678 - LOAD_IMMEDIATE r15, 0xABCDF0BD - - SET_SPR_SR_FLAGS SPR_SR_F, r6, r7 - l.cmov r10, r14, r15 - CLEAR_SPR_SR_FLAGS SPR_SR_F, r6, r7 - l.cmov r11, r14, r15 - - REPORT_REG_TO_CONSOLE r10 - REPORT_REG_TO_CONSOLE r11 - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/div.S b/sim/testsuite/sim/or1k/div.S deleted file mode 100644 index dc73d73..0000000 --- a/sim/testsuite/sim/or1k/div.S +++ /dev/null @@ -1,291 +0,0 @@ -/* Tests the divide instructions. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x0000000c);\n -# output: report(0x00000003);\n -# output: report(0x00000004);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x0000000b);\n -# output: report(0x00000003);\n -# output: report(0x00000003);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffff4);\n -# output: report(0xfffffffd);\n -# output: report(0x00000004);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffff5);\n -# output: report(0xfffffffd);\n -# output: report(0x00000003);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffff4);\n -# output: report(0x00000003);\n -# output: report(0xfffffffc);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffff5);\n -# output: report(0x00000003);\n -# output: report(0xfffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x0000000c);\n -# output: report(0xfffffffd);\n -# output: report(0xfffffffc);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x0000000b);\n -# output: report(0xfffffffd);\n -# output: report(0xfffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x0000000c);\n -# output: report(0x00000000);\n -# output: report(0xfffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffff4);\n -# output: report(0x00000000);\n -# output: report(0xfffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x0000000c);\n -# output: report(0x00000000);\n -# output: report(0xfffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0xfffffff4);\n -# output: report(0x00000000);\n -# output: report(0xfffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x0000000c);\n -# output: report(0x00000003);\n -# output: report(0x00000004);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x0000000b);\n -# output: report(0x00000003);\n -# output: report(0x00000003);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffff4);\n -# output: report(0xfffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffff5);\n -# output: report(0xfffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffff4);\n -# output: report(0x00000003);\n -# output: report(0x55555551);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffff5);\n -# output: report(0x00000003);\n -# output: report(0x55555551);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x0000000c);\n -# output: report(0xfffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x0000000b);\n -# output: report(0xfffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x0000000c);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffff4);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x0000000c);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0xfffffff4);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - STANDARD_TEST_ENVIRONMENT - - .section .exception_vectors - - /* Range exception. */ - .org 0xb00 - - l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE - PUSH r2 - PUSH r3 - /* Save the address of the instruction that caused the problem. */ - MOVE_FROM_SPR r2, SPR_EPCR_BASE - LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */ - l.sw 0(r2), r3 - POP r3 - POP r2 - l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE - l.rfe - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test l.div */ - - /* Divide two positive numbers and check rounding. Should set no - flags. */ - TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000003 /* 12 / 3 = 4 */ - TEST_INST_I32_I32 l.div, 0x0000000b, 0x00000003 /* 11 / 3 = 3 */ - - /* Divide two negative numbers and check rounding. Should set no - flags. */ - TEST_INST_I32_I32 l.div, 0xfffffff4, 0xfffffffd - TEST_INST_I32_I32 l.div, 0xfffffff5, 0xfffffffd - - /* Divide a negative number by a positive number and check - rounding. Should set no flags. */ - TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000003 - TEST_INST_I32_I32 l.div, 0xfffffff5, 0x00000003 - - /* Divide a positive number by a negative number and check - rounding. Should set no flags. */ - TEST_INST_I32_I32 l.div, 0x0000000c, 0xfffffffd - TEST_INST_I32_I32 l.div, 0x0000000b, 0xfffffffd - - /* Divide by zero. This will set the overflow flag. */ - TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000000 - TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000000 - - /* Check that range exceptions are triggered. */ - - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Divide by zero. This will set the overflow flag and trigger an - exception. */ - TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000000 - TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000000 - - CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Test l.divu */ - - /* Divide two positive numbers and check rounding. Should set no - flags. */ - TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000003 - TEST_INST_I32_I32 l.divu, 0x0000000b, 0x00000003 - - /* Divide two numbers that would be negative under 2's complement - and check rounding. Should set no flags. */ - TEST_INST_I32_I32 l.divu, 0xfffffff4, 0xfffffffd - TEST_INST_I32_I32 l.divu, 0xfffffff5, 0xfffffffd - - /* Divide a number that would be negative under 2's complement by a - number that would be positive under 2's complement and check - rounding. This should set no flags. */ - TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000003 - TEST_INST_I32_I32 l.divu, 0xfffffff5, 0x00000003 - - /* Divide a number that would be positive under 2's complement by a - number that would be negative under 2's complement and check - rounding. This should set no flags. */ - TEST_INST_I32_I32 l.divu, 0x0000000c, 0xfffffffd - TEST_INST_I32_I32 l.divu, 0x0000000b, 0xfffffffd - - /* Divide by zero. This will set the carry flag. */ - TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000000 - TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000000 - - /* Check that range exceptions are triggered. */ - - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Divide by zero. This will set the carry flag and trigger an - exception. */ - TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000000 - TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000000 - - CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/ext.S b/sim/testsuite/sim/or1k/ext.S deleted file mode 100644 index e7e68f0..0000000 --- a/sim/testsuite/sim/or1k/ext.S +++ /dev/null @@ -1,236 +0,0 @@ -/* Tests the l.ext{b,h}{s,z} instructions. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x0000007f);\n -# output: report(0x0000007f);\n -# output: report(0x00000053);\n -# output: report(0x00000053);\n -# output: report(0x0000ff53);\n -# output: report(0x00000053);\n -# output: report(0x00001234);\n -# output: report(0x00000034);\n -# output: report(0x000000ff);\n -# output: report(0xffffffff);\n -# output: report(0x00000080);\n -# output: report(0xffffff80);\n -# output: report(0x0000ff80);\n -# output: report(0xffffff80);\n -# output: report(0x00007f80);\n -# output: report(0xffffff80);\n -# output: report(0x00007fff);\n -# output: report(0xffffffff);\n -# output: report(0x0000007f);\n -# output: report(0x0000007f);\n -# output: report(0x00000053);\n -# output: report(0x00000053);\n -# output: report(0x0000ff53);\n -# output: report(0x00000053);\n -# output: report(0x00001234);\n -# output: report(0x00000034);\n -# output: report(0x000000ff);\n -# output: report(0x000000ff);\n -# output: report(0x00000080);\n -# output: report(0x00000080);\n -# output: report(0x0000ff80);\n -# output: report(0x00000080);\n -# output: report(0x00007f80);\n -# output: report(0x00000080);\n -# output: report(0x00007fff);\n -# output: report(0x000000ff);\n -# output: report(0x00007fff);\n -# output: report(0x00007fff);\n -# output: report(0x00005233);\n -# output: report(0x00005233);\n -# output: report(0xffff2f53);\n -# output: report(0x00002f53);\n -# output: report(0x12345678);\n -# output: report(0x00005678);\n -# output: report(0x0000ffff);\n -# output: report(0xffffffff);\n -# output: report(0x00008000);\n -# output: report(0xffff8000);\n -# output: report(0x0000ff80);\n -# output: report(0xffffff80);\n -# output: report(0x80008000);\n -# output: report(0xffff8000);\n -# output: report(0x7fffffff);\n -# output: report(0xffffffff);\n -# output: report(0x00007fff);\n -# output: report(0x00007fff);\n -# output: report(0x00005233);\n -# output: report(0x00005233);\n -# output: report(0xffff2f53);\n -# output: report(0x00002f53);\n -# output: report(0x12345678);\n -# output: report(0x00005678);\n -# output: report(0x0000ffff);\n -# output: report(0x0000ffff);\n -# output: report(0x00008000);\n -# output: report(0x00008000);\n -# output: report(0x0000ff80);\n -# output: report(0x0000ff80);\n -# output: report(0x80008000);\n -# output: report(0x00008000);\n -# output: report(0x7fffffff);\n -# output: report(0x0000ffff);\n -# output: report(0xffffffff);\n -# output: report(0xffffffff);\n -# output: report(0x7fffffff);\n -# output: report(0x7fffffff);\n -# output: report(0x7fff7fff);\n -# output: report(0x7fff7fff);\n -# output: report(0xffff7f7f);\n -# output: report(0xffff7f7f);\n -# output: report(0xffffff7f);\n -# output: report(0xffffff7f);\n -# output: report(0xffff7fff);\n -# output: report(0xffff7fff);\n -# output: report(0x7fff7f7f);\n -# output: report(0x7fff7f7f);\n -# output: report(0x12345678);\n -# output: report(0x12345678);\n -# output: report(0xffffffff);\n -# output: report(0xffffffff);\n -# output: report(0x7fffffff);\n -# output: report(0x7fffffff);\n -# output: report(0x7fff7fff);\n -# output: report(0x7fff7fff);\n -# output: report(0xffff7f7f);\n -# output: report(0xffff7f7f);\n -# output: report(0xffffff7f);\n -# output: report(0xffffff7f);\n -# output: report(0xffff7fff);\n -# output: report(0xffff7fff);\n -# output: report(0x7fff7f7f);\n -# output: report(0x7fff7f7f);\n -# output: report(0x12345678);\n -# output: report(0x12345678);\n -# output: exit(0)\n - -#include "or1k-asm-test-env.h" - - .macro CHECK_EXT insn, val, mask, high_mask - LOAD_IMMEDIATE r4, \val - REPORT_REG_TO_CONSOLE r4 - \insn r5, r4 - REPORT_REG_TO_CONSOLE r5 - LOAD_IMMEDIATE r6, \mask - l.xori r7, r6, -1 - l.and r8, r4, r6 - l.and r9, r5, r6 - l.sfne r8, r9 - OR1K_DELAYED_NOP (l.bf ext_fail) - l.and r8, r5, r7 - LOAD_IMMEDIATE r7, \high_mask - l.sfne r8, r7 - OR1K_DELAYED_NOP (l.bf ext_fail) - .endm - -#define CHECK_HIGH3_CLEAR(insn, val) CHECK_EXT insn, val, 0x000000ff, 0 -#define CHECK_HIGH3_SET(val) CHECK_EXT l.extbs, val, 0x000000ff, 0xffffff00 -#define CHECK_HIGH2_CLEAR(insn, val) CHECK_EXT insn, val, 0x0000ffff, 0 -#define CHECK_HIGH2_SET(val) CHECK_EXT l.exths, val, 0x0000ffff, 0xffff0000 - - .macro CHECK_MOVE insn, val - LOAD_IMMEDIATE r4, \val - REPORT_REG_TO_CONSOLE r4 - \insn r5, r4 - REPORT_REG_TO_CONSOLE r5 - l.sfne r5, r4 - OR1K_DELAYED_NOP (l.bf ext_fail) - .endm - - STANDARD_TEST_ENVIRONMENT - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test l.extbs */ - CHECK_HIGH3_CLEAR ( l.extbs, 0x7f ) - CHECK_HIGH3_CLEAR ( l.extbs, 0x53 ) - CHECK_HIGH3_CLEAR ( l.extbs, 0xff53 ) - CHECK_HIGH3_CLEAR ( l.extbs, 0x1234 ) - - CHECK_HIGH3_SET (0xff) - CHECK_HIGH3_SET (0x80) - CHECK_HIGH3_SET (0xff80) - CHECK_HIGH3_SET (0x7f80) - CHECK_HIGH3_SET (0x7fff) - - /* Test l.extbz */ - CHECK_HIGH3_CLEAR (l.extbz, 0x7f) - CHECK_HIGH3_CLEAR (l.extbz, 0x53) - CHECK_HIGH3_CLEAR (l.extbz, 0xff53) - CHECK_HIGH3_CLEAR (l.extbz, 0x1234) - - CHECK_HIGH3_CLEAR (l.extbz, 0xff) - CHECK_HIGH3_CLEAR (l.extbz, 0x80) - CHECK_HIGH3_CLEAR (l.extbz, 0xff80) - CHECK_HIGH3_CLEAR (l.extbz, 0x7f80) - CHECK_HIGH3_CLEAR (l.extbz, 0x7fff) - - /* Test l.exths */ - CHECK_HIGH2_CLEAR (l.exths, 0x7fff) - CHECK_HIGH2_CLEAR (l.exths, 0x5233) - CHECK_HIGH2_CLEAR (l.exths, 0xffff2f53) - CHECK_HIGH2_CLEAR (l.exths, 0x12345678) - - CHECK_HIGH2_SET (0xffff) - CHECK_HIGH2_SET (0x8000) - CHECK_HIGH2_SET (0xff80) - CHECK_HIGH2_SET (0x80008000) - CHECK_HIGH2_SET (0x7fffffff) - - /* Test l.exthz */ - CHECK_HIGH2_CLEAR (l.exthz, 0x7fff) - CHECK_HIGH2_CLEAR (l.exthz, 0x5233) - CHECK_HIGH2_CLEAR (l.exthz, 0xffff2f53) - CHECK_HIGH2_CLEAR (l.exthz, 0x12345678) - - CHECK_HIGH2_CLEAR (l.exthz, 0xffff) - CHECK_HIGH2_CLEAR (l.exthz, 0x8000) - CHECK_HIGH2_CLEAR (l.exthz, 0xff80) - CHECK_HIGH2_CLEAR (l.exthz, 0x80008000) - CHECK_HIGH2_CLEAR (l.exthz, 0x7fffffff) - - /* Test l.extws */ - CHECK_MOVE l.extws, 0xffffffff - CHECK_MOVE l.extws, 0x7fffffff - CHECK_MOVE l.extws, 0x7fff7fff - CHECK_MOVE l.extws, 0xffff7f7f - CHECK_MOVE l.extws, 0xffffff7f - CHECK_MOVE l.extws, 0xffff7fff - CHECK_MOVE l.extws, 0x7fff7f7f - CHECK_MOVE l.extws, 0x12345678 - - /* Test l.extwz */ - CHECK_MOVE l.extwz, 0xffffffff - CHECK_MOVE l.extwz, 0x7fffffff - CHECK_MOVE l.extwz, 0x7fff7fff - CHECK_MOVE l.extwz, 0xffff7f7f - CHECK_MOVE l.extwz, 0xffffff7f - CHECK_MOVE l.extwz, 0xffff7fff - CHECK_MOVE l.extwz, 0x7fff7f7f - CHECK_MOVE l.extwz, 0x12345678 - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 - -ext_fail: - EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR diff --git a/sim/testsuite/sim/or1k/find.S b/sim/testsuite/sim/or1k/find.S deleted file mode 100644 index 7713c17..0000000 --- a/sim/testsuite/sim/or1k/find.S +++ /dev/null @@ -1,100 +0,0 @@ -/* Tests the find instructions. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x80000000);\n -# output: report(0x00000020);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000002);\n -# output: \n -# output: report(0x00018000);\n -# output: report(0x00000010);\n -# output: \n -# output: report(0xc0000000);\n -# output: report(0x0000001f);\n -# output: \n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x80000000);\n -# output: report(0x00000020);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x0000001f);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000020);\n -# output: \n -# output: report(0x00018000);\n -# output: report(0x00000011);\n -# output: \n -# output: report(0xc0000000);\n -# output: report(0x00000020);\n -# output: \n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - .macro TEST_FIND opcode, operand - LOAD_IMMEDIATE r5, \operand - REPORT_REG_TO_CONSOLE r5 - \opcode r4, r5 - REPORT_REG_TO_CONSOLE r4 - PRINT_NEWLINE_TO_CONSOLE - .endm - - STANDARD_TEST_ENVIRONMENT - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test l.ff1 */ - - TEST_FIND l.ff1, 0x00000001 - TEST_FIND l.ff1, 0x80000000 - TEST_FIND l.ff1, 0x55555555 - TEST_FIND l.ff1, 0xaaaaaaaa - TEST_FIND l.ff1, 0x00018000 - TEST_FIND l.ff1, 0xc0000000 - TEST_FIND l.ff1, 0x00000000 - - /* Test l.fl1 */ - - TEST_FIND l.fl1, 0x00000001 - TEST_FIND l.fl1, 0x80000000 - TEST_FIND l.fl1, 0x55555555 - TEST_FIND l.fl1, 0xaaaaaaaa - TEST_FIND l.fl1, 0x00018000 - TEST_FIND l.fl1, 0xc0000000 - TEST_FIND l.fl1, 0x00000000 - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/flag.S b/sim/testsuite/sim/or1k/flag.S deleted file mode 100644 index b614c1a..0000000 --- a/sim/testsuite/sim/or1k/flag.S +++ /dev/null @@ -1,386 +0,0 @@ -/* Tests the set flag (l.sf*) instructions. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - -#define INT_MAX 2147483647 /* 0x7fffffff */ -#define INT_MAX_MIN1 2147483646 /* 0x7ffffffe */ -#define NEG_INT_MAX -2147483648 /* 0x80000000 */ -#define NEG_INT_MAX_PL1 -2147483647 /* 0x80000001 */ -#define MIN1 -1 /* 0xffffffff */ - -#define SHRT_MIN (-32768) -#define SHRT_MAX 32767 - -#define UINT_MAX 4294967295 /* 0xffffffff */ -#define UINT_MAX_MIN1 4294967294 /* 0xfffffffe */ - -#define USHRT_MAX 65535 - - .macro MOVE_TO_R4_R5_AND_REPORT a, b - LOAD_IMMEDIATE r4, \a - LOAD_IMMEDIATE r5, \b - - /* During development, add REPORT_xxx statements here to see the - operands. */ - .endm - - .macro MOVE_TO_R4_AND_REPORT_I a, b - LOAD_IMMEDIATE r4, \a - - /* During development, add REPORT_xxx statements here to see the - operands. */ - .endm - - .macro SHOULD_BE_SET - OR1K_DELAYED_NOP (l.bnf failed) - .endm - - .macro SHOULDNT_BE_SET - OR1K_DELAYED_NOP (l.bf failed) - .endm - - .macro SHOULD_BE_LESS_THAN_SIGNED a, b - MOVE_TO_R4_R5_AND_REPORT \a , \b - - l.sfeq r4, r5 - SHOULDNT_BE_SET - l.sfne r4, r5 - SHOULD_BE_SET - l.sfgts r4, r5 - SHOULDNT_BE_SET - l.sfges r4, r5 - SHOULDNT_BE_SET - l.sfles r4, r5 - SHOULD_BE_SET - l.sflts r4, r5 - SHOULD_BE_SET - .endm - - .macro SHOULD_BE_GREATER_THAN_SIGNED a, b - MOVE_TO_R4_R5_AND_REPORT \a , \b - - l.sfeq r4, r5 - SHOULDNT_BE_SET - l.sfne r4, r5 - SHOULD_BE_SET - l.sfgts r4, r5 - SHOULD_BE_SET - l.sfges r4, r5 - SHOULD_BE_SET - l.sfles r4, r5 - SHOULDNT_BE_SET - l.sflts r4, r5 - SHOULDNT_BE_SET - .endm - - .macro SHOULD_BE_LESS_THAN_UNSIGNED a, b - MOVE_TO_R4_R5_AND_REPORT \a , \b - - l.sfeq r4, r5 - SHOULDNT_BE_SET - l.sfne r4, r5 - SHOULD_BE_SET - l.sfgtu r4, r5 - SHOULDNT_BE_SET - l.sfgeu r4, r5 - SHOULDNT_BE_SET - l.sfleu r4, r5 - SHOULD_BE_SET - l.sfltu r4, r5 - SHOULD_BE_SET - .endm - - .macro SHOULD_BE_GREATER_THAN_UNSIGNED a, b - MOVE_TO_R4_R5_AND_REPORT \a , \b - - l.sfeq r4, r5 - SHOULDNT_BE_SET - l.sfne r4, r5 - SHOULD_BE_SET - l.sfgtu r4, r5 - SHOULD_BE_SET - l.sfgeu r4, r5 - SHOULD_BE_SET - l.sfleu r4, r5 - SHOULDNT_BE_SET - l.sfltu r4, r5 - SHOULDNT_BE_SET - .endm - - .macro SHOULD_BE_EQUAL a, b - MOVE_TO_R4_R5_AND_REPORT \a , \b - - l.sfeq r4, r5 - SHOULD_BE_SET - l.sfne r4, r5 - SHOULDNT_BE_SET - - /* Signed tests. */ - l.sfgts r4, r5 - SHOULDNT_BE_SET - l.sfges r4, r5 - SHOULD_BE_SET - l.sfles r4, r5 - SHOULD_BE_SET - l.sflts r4, r5 - SHOULDNT_BE_SET - - /* Unsigned tests. */ - l.sfgtu r4, r5 - SHOULDNT_BE_SET - l.sfgeu r4, r5 - SHOULD_BE_SET - l.sfleu r4, r5 - SHOULD_BE_SET - l.sfltu r4, r5 - SHOULDNT_BE_SET - .endm - - .macro SHOULDNT_BE_EQUAL a, b - MOVE_TO_R4_R5_AND_REPORT \a , \b - - l.sfeq r4, r5 - SHOULDNT_BE_SET - l.sfne r4, r5 - SHOULD_BE_SET - .endm - - .macro SHOULD_BE_EQUAL_I a, b - MOVE_TO_R4_AND_REPORT_I \a, \b - - l.sfeqi r4, \b - SHOULD_BE_SET - l.sfnei r4, \b - SHOULDNT_BE_SET - - /* Signed tests. */ - l.sfgtsi r4, \b - SHOULDNT_BE_SET - l.sfgesi r4, \b - SHOULD_BE_SET - l.sflesi r4, \b - SHOULD_BE_SET - l.sfltsi r4, \b - SHOULDNT_BE_SET - - /* Unsigned tests. */ - l.sfgtui r4, \b - SHOULDNT_BE_SET - l.sfgeui r4, \b - SHOULD_BE_SET - l.sfleui r4, \b - SHOULD_BE_SET - l.sfltui r4, \b - SHOULDNT_BE_SET - .endm - - .macro SHOULDNT_BE_EQUAL_I a, b - MOVE_TO_R4_AND_REPORT_I \a, \b - - l.sfeqi r4, \b - SHOULDNT_BE_SET - l.sfnei r4, \b - SHOULD_BE_SET - .endm - - .macro SHOULD_BE_LESS_THAN_SIGNED_I a, b - MOVE_TO_R4_AND_REPORT_I \a, \b - - l.sfeqi r4, \b - SHOULDNT_BE_SET - l.sfnei r4, \b - SHOULD_BE_SET - l.sfgtsi r4, \b - SHOULDNT_BE_SET - l.sfgesi r4, \b - SHOULDNT_BE_SET - l.sflesi r4, \b - SHOULD_BE_SET - l.sfltsi r4, \b - SHOULD_BE_SET - .endm - - .macro SHOULD_BE_GREATER_THAN_SIGNED_I a, b - MOVE_TO_R4_AND_REPORT_I \a, \b - - l.sfeqi r4, \b - SHOULDNT_BE_SET - l.sfnei r4, \b - SHOULD_BE_SET - l.sfgtsi r4, \b - SHOULD_BE_SET - l.sfgesi r4, \b - SHOULD_BE_SET - l.sflesi r4, \b - SHOULDNT_BE_SET - l.sfltsi r4, \b - SHOULDNT_BE_SET - .endm - - .macro SHOULD_BE_LESS_THAN_UNSIGNED_I a, b - MOVE_TO_R4_AND_REPORT_I \a, \b - - l.sfeqi r4, \b - SHOULDNT_BE_SET - l.sfnei r4, \b - SHOULD_BE_SET - l.sfgtui r4, \b - SHOULDNT_BE_SET - l.sfgeui r4, \b - SHOULDNT_BE_SET - l.sfleui r4, \b - SHOULD_BE_SET - l.sfltui r4, \b - SHOULD_BE_SET - .endm - - .macro SHOULD_BE_GREATER_THAN_UNSIGNED_I a, b - MOVE_TO_R4_AND_REPORT_I \a, \b - - l.sfeqi r4, \b - SHOULDNT_BE_SET - l.sfnei r4, \b - SHOULD_BE_SET - l.sfgtui r4, \b - SHOULD_BE_SET - l.sfgeui r4, \b - SHOULD_BE_SET - l.sfleui r4, \b - SHOULDNT_BE_SET - l.sfltui r4, \b - SHOULDNT_BE_SET - .endm - - STANDARD_TEST_ENVIRONMENT - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Signed tests */ - - SHOULD_BE_LESS_THAN_SIGNED 0, 1 - SHOULD_BE_LESS_THAN_SIGNED MIN1, 0 - SHOULD_BE_LESS_THAN_SIGNED INT_MAX_MIN1, INT_MAX - SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, INT_MAX - SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, INT_MAX_MIN1 - SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX_PL1, INT_MAX - SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX_PL1, INT_MAX_MIN1 - SHOULD_BE_LESS_THAN_SIGNED -7, -6 - SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, NEG_INT_MAX_PL1 - SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, MIN1 - SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, 0 - - SHOULD_BE_GREATER_THAN_SIGNED 1, 0 - SHOULD_BE_GREATER_THAN_SIGNED 0, MIN1 - SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, INT_MAX_MIN1 - SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, NEG_INT_MAX - SHOULD_BE_GREATER_THAN_SIGNED INT_MAX_MIN1, NEG_INT_MAX - SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, NEG_INT_MAX_PL1 - SHOULD_BE_GREATER_THAN_SIGNED INT_MAX_MIN1, NEG_INT_MAX_PL1 - SHOULD_BE_GREATER_THAN_SIGNED -6, -7 - SHOULD_BE_GREATER_THAN_SIGNED NEG_INT_MAX_PL1, NEG_INT_MAX - SHOULD_BE_GREATER_THAN_SIGNED MIN1, NEG_INT_MAX - SHOULD_BE_GREATER_THAN_SIGNED 0, NEG_INT_MAX - - /* See the immediate tests below. */ - SHOULD_BE_LESS_THAN_SIGNED 0xFFFF7FFF, 0xFFFF8000 - /* See the immediate tests below. */ - SHOULD_BE_GREATER_THAN_SIGNED 0xFFFF8001, 0xFFFF8000 - - /* Signed tests, immediate */ - - SHOULD_BE_LESS_THAN_SIGNED_I 0, 1 - SHOULD_BE_LESS_THAN_SIGNED_I -1, 0 - SHOULD_BE_LESS_THAN_SIGNED_I -7, -6 - - SHOULD_BE_GREATER_THAN_SIGNED_I 0x00008000, 0x7FFF - SHOULD_BE_LESS_THAN_SIGNED_I 0xFFFFFFFF, 0x7FFF - /* 0x8000 gets sign-extended to 0xFFFF8000. */ - SHOULD_BE_LESS_THAN_SIGNED_I 0xFFFF7FFF, 0x8000 - /* 0x8000 gets sign-extended to 0xFFFF8000. */ - SHOULD_BE_GREATER_THAN_SIGNED_I 0xFFFF8001, 0x8000 - /* 0x8000 gets sign-extended to 0xFFFF8000. */ - SHOULD_BE_GREATER_THAN_SIGNED_I 0x00008000, 0x8000 - - /* Unsigned tests */ - - SHOULD_BE_LESS_THAN_UNSIGNED 0, 1 - SHOULD_BE_LESS_THAN_UNSIGNED UINT_MAX_MIN1, UINT_MAX - SHOULD_BE_GREATER_THAN_UNSIGNED 1, 0 - SHOULD_BE_GREATER_THAN_UNSIGNED UINT_MAX, UINT_MAX_MIN1 - SHOULD_BE_GREATER_THAN_UNSIGNED UINT_MAX, 0 - SHOULD_BE_GREATER_THAN_UNSIGNED 0x80000001, 0x80000000 - SHOULD_BE_LESS_THAN_UNSIGNED 0x80000000, 0x80000001 - SHOULD_BE_GREATER_THAN_UNSIGNED 0x80000000, 0x7fffffff - SHOULD_BE_LESS_THAN_UNSIGNED 0x7fffffff, 0x80000000 - SHOULD_BE_GREATER_THAN_UNSIGNED 0x7fffffff, 0x7ffffffe - SHOULD_BE_LESS_THAN_UNSIGNED 0x7ffffffe, 0x7fffffff - SHOULD_BE_LESS_THAN_UNSIGNED 0x2024fae0, 0xfef03220 - - /* Unsigned tests, immediate */ - - SHOULD_BE_LESS_THAN_UNSIGNED_I 0, 1 - SHOULD_BE_GREATER_THAN_UNSIGNED_I 1, 0 - SHOULD_BE_LESS_THAN_UNSIGNED_I SHRT_MAX - 1, SHRT_MAX - SHOULD_BE_GREATER_THAN_UNSIGNED_I SHRT_MAX , SHRT_MAX - 1 - - /* The sign extension produces unexpected results here. */ - - /* 0xFFFF gets sign-extended to 0xFFFFFFFF. */ - SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFFFFFF - 1, 0xFFFF - /* 0x8000 gets sign-extended to 0xFFFF8000. */ - SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFF7FFF, 0x8000 - - /* Equal tests. */ - - SHOULD_BE_EQUAL 0, 0 - SHOULD_BE_EQUAL UINT_MAX, UINT_MAX - SHOULD_BE_EQUAL MIN1, UINT_MAX - SHOULD_BE_EQUAL INT_MAX, INT_MAX - SHOULD_BE_EQUAL NEG_INT_MAX, NEG_INT_MAX - - /* Equal tests, immediate. Test the 16-to-32-bit sign extension. */ - - SHOULD_BE_EQUAL_I 0, 0 - SHOULD_BE_EQUAL_I 0x00007FFF, 0x7FFF - SHOULD_BE_EQUAL_I 0xFFFF8000, 0x8000 - SHOULD_BE_EQUAL_I 0xFFFFFFFF, 0xFFFF - - /* Non-equal tests. */ - - SHOULDNT_BE_EQUAL 0, 1 - SHOULDNT_BE_EQUAL UINT_MAX, INT_MAX - SHOULDNT_BE_EQUAL UINT_MAX, NEG_INT_MAX - SHOULDNT_BE_EQUAL MIN1, NEG_INT_MAX_PL1 - SHOULDNT_BE_EQUAL INT_MAX, NEG_INT_MAX - SHOULDNT_BE_EQUAL NEG_INT_MAX_PL1, UINT_MAX_MIN1 - - /* Non-equal tests, immediate. Test the 16-to-32-bit sign - extension. */ - - SHOULDNT_BE_EQUAL_I 0x00008000, 0x8000 - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 - -failed: - EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR diff --git a/sim/testsuite/sim/or1k/fpu-unordered.S b/sim/testsuite/sim/or1k/fpu-unordered.S deleted file mode 100644 index a4e6556..0000000 --- a/sim/testsuite/sim/or1k/fpu-unordered.S +++ /dev/null @@ -1,97 +0,0 @@ -/* Tests some basic unordered fpu compare instructions. - - Copyright (C) 2019-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x40490fd0);\n -# output: report(0x402df84d);\n -# output: report(0x7fc00000);\n -# output: \n -# output: report(0x00000001);\n -# output: \n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000001);\n -# output: \n -# output: report(0x00000001);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - STANDARD_TEST_ENVIRONMENT - - .section .data - .align 4 - .type pi, @object - .size pi, 4 -anchor: -pi: - .float 3.14159 - - .type e, @object - .size e, 4 -e: - .float 2.71828 - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test unordered float comparisons. Setting up: - * r11 pointer to data - * r12 pi as float - * r13 e as float - * r16 nan as float - */ - l.ori r11, r0, ha(anchor) - l.addi r11, r11, lo(anchor) - l.lwz r12, 0(r11) - - l.lwz r13, 4(r11) - - /* Make a NaN. */ - lf.sub.s r16, r13, r13 - lf.div.s r16, r16, r16 - - /* Output to ensure we loaded it correctly. */ - REPORT_REG_TO_CONSOLE r12 - REPORT_REG_TO_CONSOLE r13 - REPORT_REG_TO_CONSOLE r16 - PRINT_NEWLINE_TO_CONSOLE - - lf.sfuge.s r12, r13 - MOVE_FROM_SPR r2, SPR_SR - REPORT_BIT_TO_CONSOLE r2, SPR_SR_F - PRINT_NEWLINE_TO_CONSOLE - - lf.sfun.s r12, r13 - MOVE_FROM_SPR r2, SPR_SR - REPORT_BIT_TO_CONSOLE r2, SPR_SR_F - PRINT_NEWLINE_TO_CONSOLE - - lf.sfun.s r12, r16 - MOVE_FROM_SPR r2, SPR_SR - REPORT_BIT_TO_CONSOLE r2, SPR_SR_F - PRINT_NEWLINE_TO_CONSOLE - - lf.sfueq.s r12, r12 - MOVE_FROM_SPR r2, SPR_SR - REPORT_BIT_TO_CONSOLE r2, SPR_SR_F - PRINT_NEWLINE_TO_CONSOLE - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/fpu.S b/sim/testsuite/sim/or1k/fpu.S deleted file mode 100644 index 9a164b1..0000000 --- a/sim/testsuite/sim/or1k/fpu.S +++ /dev/null @@ -1,129 +0,0 @@ -/* Tests some basic fpu instructions. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x00007ab7);\n -# output: report(0xffffd8f0);\n -# output: report(0x46f56e00);\n -# output: report(0xc61c4000);\n -# output: report(0x00007ab7);\n -# output: report(0xffffd8f0);\n -# output: \n -# output: report(0xc0490e56);\n -# output: report(0xfffffffd);\n -# output: \n -# output: report(0x4e6b4bbb);\n -# output: \n -# output: report(0xbdc0be40);\n -# output: \n -# output: report(0x00000001);\n -# output: \n -# output: WARNING: ignoring fpu error caught in fast mode.\n -# output: report(0x00000000);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - STANDARD_TEST_ENVIRONMENT - - .section .exception_vectors - - /* Floating point exception. */ - .org 0xd00 - - /* The handling is a bit dubious at present. We just patch the - instruction with l.nop and restart. This will go wrong in branch - delay slots. But we don't have those in this test. */ - l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE - PUSH r2 - PUSH r3 - /* Save the address of the instruction that caused the problem. */ - MOVE_FROM_SPR r2, SPR_EPCR_BASE - LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */ - l.sw -4(r2), r3 - POP r3 - POP r2 - l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE - l.rfe - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test lf.itof.s int to float conversion. Setting up: - * r10 31415.0f - * r12 -10000.0f - */ - l.ori r11, r0, 31415 - l.ori r13, r0, -10000 - l.movhi r15, 0xffff - l.or r13, r13, r15 - - REPORT_REG_TO_CONSOLE r11 - REPORT_REG_TO_CONSOLE r13 - lf.itof.s r10, r11 - lf.itof.s r12, r13 - REPORT_REG_TO_CONSOLE r10 - REPORT_REG_TO_CONSOLE r12 - - /* Test lf.ftoi.s float to int conversion. */ - lf.ftoi.s r11, r10 - lf.ftoi.s r13, r12 - REPORT_REG_TO_CONSOLE r11 - REPORT_REG_TO_CONSOLE r13 - PRINT_NEWLINE_TO_CONSOLE - - /* Test lf.div.s divide 31415 by -1000 to get -pi. Setting up: - * r8 -3.1415f - */ - lf.div.s r8, r10, r12 - REPORT_REG_TO_CONSOLE r8 - - lf.ftoi.s r11, r8 - REPORT_REG_TO_CONSOLE r11 - PRINT_NEWLINE_TO_CONSOLE - - /* Test lf.mul.s multiply -pi x -10000 x 31415. Setting up: - * r6 986902225 - */ - lf.mul.s r6, r8, r12 - lf.mul.s r6, r6, r10 - REPORT_REG_TO_CONSOLE r6 - PRINT_NEWLINE_TO_CONSOLE - - /* Test lf.rem.s remainder of 986902225 / -pi. */ - lf.rem.s r2, r6, r8 - REPORT_REG_TO_CONSOLE r2 - PRINT_NEWLINE_TO_CONSOLE - - /* Test lf.sfge.s set flag if r6 >= r10. */ - lf.sfge.s r6, r10 - MOVE_FROM_SPR r2, SPR_SR - REPORT_BIT_TO_CONSOLE r2, SPR_SR_F - PRINT_NEWLINE_TO_CONSOLE - - /* Test raising an exception by dividing by 0. */ - MOVE_FROM_SPR r2, SPR_FPCSR - l.ori r2, r2, 0x1 - MOVE_TO_SPR SPR_FPCSR, r2 -div0: lf.div.s r2, r8, r0 - REPORT_EXCEPTION div0 - PRINT_NEWLINE_TO_CONSOLE - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/fpu64a32-unordered.S b/sim/testsuite/sim/or1k/fpu64a32-unordered.S deleted file mode 100644 index 1966916..0000000 --- a/sim/testsuite/sim/or1k/fpu64a32-unordered.S +++ /dev/null @@ -1,100 +0,0 @@ -/* Tests some basic unordered fpu compare instructions. - - Copyright (C) 2019-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x400921f9);\n -# output: report(0xf01b866e);\n -# output: report(0x4005bf09);\n -# output: report(0x95aaf790);\n -# output: report(0x7ff80000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000001);\n -# output: \n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000001);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - STANDARD_TEST_ENVIRONMENT - - .section .data - .align 4 - .type pi, @object - .size pi, 8 -anchor: -pi: - .double 3.14159 - - .type e, @object - .size e, 8 -e: - .double 2.71828 - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test unordered double comparisons. Setting up: - * r11 pointer to data - * r12,r13 pi as double - * r14,r15 e as double - * r16,r17 nan as double - */ - l.ori r11, r0, ha(anchor) - l.addi r11, r11, lo(anchor) - l.lwz r12, 0(r11) - l.lwz r13, 4(r11) - - l.lwz r14, 8(r11) - l.lwz r15, 12(r11) - - /* Make a NaN. */ - lf.sub.d r16,r18, r12,r13, r12,r13 - lf.div.d r16,r18, r16,r18, r16,r18 - - /* Output to ensure we loaded it correctly. */ - REPORT_REG_TO_CONSOLE r12 - REPORT_REG_TO_CONSOLE r13 - - REPORT_REG_TO_CONSOLE r14 - REPORT_REG_TO_CONSOLE r15 - - REPORT_REG_TO_CONSOLE r16 - REPORT_REG_TO_CONSOLE r18 - PRINT_NEWLINE_TO_CONSOLE - - lf.sfuge.d r12,r13, r14,r15 - MOVE_FROM_SPR r2, SPR_SR - REPORT_BIT_TO_CONSOLE r2, SPR_SR_F - PRINT_NEWLINE_TO_CONSOLE - - lf.sfun.d r12,r13, r14,r15 - MOVE_FROM_SPR r2, SPR_SR - REPORT_BIT_TO_CONSOLE r2, SPR_SR_F - PRINT_NEWLINE_TO_CONSOLE - - lf.sfun.d r12,r13, r16,r18 - MOVE_FROM_SPR r2, SPR_SR - REPORT_BIT_TO_CONSOLE r2, SPR_SR_F - PRINT_NEWLINE_TO_CONSOLE - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/fpu64a32.S b/sim/testsuite/sim/or1k/fpu64a32.S deleted file mode 100644 index 319af48..0000000 --- a/sim/testsuite/sim/or1k/fpu64a32.S +++ /dev/null @@ -1,172 +0,0 @@ -/* Tests some basic fpu instructions. - - Copyright (C) 2019-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x400921f9);\n -# output: report(0xf01b866e);\n -# output: report(0x4005bf09);\n -# output: report(0x95aaf790);\n -# output: report(0x00000000);\n -# output: report(0x00001234);\n -# output: \n -# output: report(0x40b23400);\n -# output: report(0x00000000);\n -# output: report(0x40b23400);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x40177081);\n -# output: report(0xc2e33eff);\n -# output: report(0x400921f9);\n -# output: report(0xf01b866e);\n -# output: \n -# output: report(0x40211456);\n -# output: report(0x587dfabf);\n -# output: report(0x400921f9);\n -# output: report(0xf01b866d);\n -# output: \n -# output: report(0x00000001);\n -# output: \n -# output: WARNING: ignoring fpu error caught in fast mode.\n -# output: report(0x00000000);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - STANDARD_TEST_ENVIRONMENT - - .section .exception_vectors - - /* Floating point exception. */ - .org 0xd00 - - /* The handling is a bit dubious at present. We just patch the - instruction with l.nop and restart. This will go wrong in branch - delay slots. But we don't have those in this test. */ - l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE - PUSH r2 - PUSH r3 - /* Save the address of the instruction that caused the problem. */ - MOVE_FROM_SPR r2, SPR_EPCR_BASE - LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */ - l.sw -4(r2), r3 - POP r3 - POP r2 - l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE - l.rfe - - .section .data - .align 4 - .type pi, @object - .size pi, 8 -anchor: -pi: - .double 3.14159 - - .type e, @object - .size e, 8 -e: - .double 2.71828 - - .type large, @object - .size large, 8 -large: - .long 0 - .long 0x1234 - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test lf.itof.d int to double conversion. Setting up: - * r11 pointer to data - * r12,r13 pi as double - * r14,r15 e as double - * r16,r17 a long long - */ - l.ori r11, r0, ha(anchor) - l.addi r11, r11, lo(anchor) - l.lwz r12, 0(r11) - l.lwz r13, 4(r11) - - l.lwz r14, 8(r11) - l.lwz r15, 12(r11) - - l.lwz r16, 16(r11) - l.lwz r18, 20(r11) - - /* Output to ensure we loaded it correctly. */ - REPORT_REG_TO_CONSOLE r12 - REPORT_REG_TO_CONSOLE r13 - - REPORT_REG_TO_CONSOLE r14 - REPORT_REG_TO_CONSOLE r15 - - REPORT_REG_TO_CONSOLE r16 - REPORT_REG_TO_CONSOLE r18 - PRINT_NEWLINE_TO_CONSOLE - - /* Convert the big long to a double. */ - lf.itof.d r16,r18, r16,r18 - REPORT_REG_TO_CONSOLE r16 - REPORT_REG_TO_CONSOLE r18 - - /* Convert the double back to a long, it should match before. */ - lf.ftoi.d r16,r18, r16,r18 - lf.itof.d r16,r18, r16,r18 - - REPORT_REG_TO_CONSOLE r16 - REPORT_REG_TO_CONSOLE r18 - - PRINT_NEWLINE_TO_CONSOLE - - /* Add and subtract some double values. */ - lf.add.d r12,r13, r12,r13, r14,r15 - REPORT_REG_TO_CONSOLE r12 - REPORT_REG_TO_CONSOLE r13 - - lf.sub.d r12,r13, r12,r13, r14,r15 - REPORT_REG_TO_CONSOLE r12 - REPORT_REG_TO_CONSOLE r13 - PRINT_NEWLINE_TO_CONSOLE - - /* Multiply and divide double values. */ - lf.mul.d r12,r13, r12,r13, r14,r15 - REPORT_REG_TO_CONSOLE r12 - REPORT_REG_TO_CONSOLE r13 - - lf.div.d r12,r13, r12,r13, r14,r15 - REPORT_REG_TO_CONSOLE r12 - REPORT_REG_TO_CONSOLE r13 - PRINT_NEWLINE_TO_CONSOLE - - /* Test lf.sfge.s set flag if r6 >= r10. */ - lf.sfge.d r12,r13, r14,r15 - MOVE_FROM_SPR r2, SPR_SR - REPORT_BIT_TO_CONSOLE r2, SPR_SR_F - PRINT_NEWLINE_TO_CONSOLE - - /* Test raising an exception by dividing by 0. */ - MOVE_FROM_SPR r2, SPR_FPCSR - l.ori r2, r2, 0x1 - MOVE_TO_SPR SPR_FPCSR, r2 -div0: lf.div.d r2,r3, r12,r13, r0,r1 - REPORT_EXCEPTION div0 - PRINT_NEWLINE_TO_CONSOLE - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/jump.S b/sim/testsuite/sim/or1k/jump.S deleted file mode 100644 index 8181886..0000000 --- a/sim/testsuite/sim/or1k/jump.S +++ /dev/null @@ -1,105 +0,0 @@ -/* Tests the jump instructions. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x48000000);\n -# output: report(0x00000005);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x48000000);\n -# output: report(0x00000009);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x44000000);\n -# output: report(0x00000005);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x44000000);\n -# output: report(0x00000009);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - -/* Tests a jump instruction using a register destination. - Checks whether the jump succeeds, or whether an exception is triggered - (but not if the right exception was triggered yet). - - We manually construct the opcode, to allow us to force R9 into the - destination field, to test exception handling. Usually the assembler - would prevent this. - - Do not specify R31 as the register to use for the jump, as it's used - internally. */ - - .macro TEST_JUMP opcode_value dest_register_number alignment_offset - REPORT_IMMEDIATE_TO_CONSOLE \opcode_value - REPORT_IMMEDIATE_TO_CONSOLE \dest_register_number - REPORT_IMMEDIATE_TO_CONSOLE \alignment_offset - LOAD_IMMEDIATE r\dest_register_number, 51f + \alignment_offset - /* Generate the jump opcode. */ -\@1$: OR1K_DELAYED_NOP \ - (.word ( \opcode_value | (\dest_register_number << 11) )) - /* If the jump failed, we land here. */ - REPORT_IMMEDIATE_TO_CONSOLE 1 - OR1K_DELAYED_NOP (l.j 52f) - /* If the jump succeeds, we land here. */ -51: REPORT_IMMEDIATE_TO_CONSOLE 0 -52: REPORT_EXCEPTION \@1$ - PRINT_NEWLINE_TO_CONSOLE - .endm - - STANDARD_TEST_ENVIRONMENT - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test l.jalr (jump and link register) */ - TEST_JUMP 0x48000000, 5, 0 - /* TODO: The sim does not support unaligned memory access yet. - TEST_JUMP 0x48000000, 5, 1 - TEST_JUMP 0x48000000, 5, 2 - TEST_JUMP 0x48000000, 5, 3 - */ - - /* Test with link register as the destination. This is not - allowed. */ - TEST_JUMP 0x48000000, 9, 0 - - /* Test l.jr (jump register) */ - TEST_JUMP 0x44000000, 5, 0 - /* TODO: The sim does not support unaligned memory access yet. - TEST_JUMP 0x44000000, 5, 1 - TEST_JUMP 0x44000000, 5, 2 - TEST_JUMP 0x44000000, 5, 3 - */ - - /* Test with link register as the destination. */ - TEST_JUMP 0x44000000, 9, 0 - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/load.S b/sim/testsuite/sim/or1k/load.S deleted file mode 100644 index 3644a87..0000000 --- a/sim/testsuite/sim/or1k/load.S +++ /dev/null @@ -1,358 +0,0 @@ -/* Tests the load and store instructions. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0xdeadbeef);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0x80000000);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0x80000000);\n -# output: report(0xffffffff);\n -# output: report(0xdeadbeef);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0x80000000);\n -# output: report(0xdeadbeef);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0x80000000);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0x80000000);\n -# output: report(0xffffffff);\n -# output: report(0xdeadbeef);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0x80000000);\n -# output: report(0x000000de);\n -# output: report(0x000000ad);\n -# output: report(0x000000be);\n -# output: report(0x000000ef);\n -# output: report(0x000000ef);\n -# output: report(0x000000be);\n -# output: report(0x000000ad);\n -# output: report(0x000000de);\n -# output: report(0xffffffde);\n -# output: report(0xffffffad);\n -# output: report(0xffffffbe);\n -# output: report(0xffffffef);\n -# output: report(0xffffffef);\n -# output: report(0xffffffbe);\n -# output: report(0xffffffad);\n -# output: report(0xffffffde);\n -# output: report(0x0000dead);\n -# output: report(0x0000beef);\n -# output: report(0x0000beef);\n -# output: report(0x0000dead);\n -# output: report(0xffffdead);\n -# output: report(0xffffbeef);\n -# output: report(0xffffbeef);\n -# output: report(0xffffdead);\n -# output: report(0xa1a2a3a4);\n -# output: report(0xb4b3b2b1);\n -# output: report(0x81828384);\n -# output: report(0x53545152);\n -# output: report(0xa0b0c0d0);\n -# output: report(0xa1b1c1d1);\n -# output: report(0xa3b3c3d3);\n -# output: report(0xa2b2c2d2);\n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - .macro TEST_LW opcode, label, offset - LOAD_IMMEDIATE r5, \label - \opcode r4, \offset(r5) - REPORT_REG_TO_CONSOLE r4 - .endm - - STANDARD_TEST_ENVIRONMENT - - .section .rodata - .balign 4 - -50: .word 0xdeadbeef -51: .word 0x00000000 -52: .word 0x7fffffff -53: .word 0x80000000 -54: .word 0xffffffff - - .section .data - .balign 4 - -buffer1: .word 0x00000000 -buffer2: .word 0x00000000 -buffer3: .word 0x00000000 -buffer4: .word 0x00000000 -buffer5: - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test instruction l.lws */ - - /* Load with zero offset. */ - TEST_LW l.lws 50b, 0 - TEST_LW l.lws 51b, 0 - TEST_LW l.lws 52b, 0 - TEST_LW l.lws 53b, 0 - TEST_LW l.lws 54b, 0 - - /* Load with positive offset. */ - TEST_LW l.lws 50b, 4 - TEST_LW l.lws 50b, 8 - TEST_LW l.lws 50b, 12 - TEST_LW l.lws 50b, 16 - - /* Load with negative offset. */ - TEST_LW l.lws 54b, -16 - TEST_LW l.lws 54b, -12 - TEST_LW l.lws 54b, -8 - TEST_LW l.lws 54b, -4 - - /* TODO: add here test cases to cover unaligned memory accesses - with l.lws. */ - - /* Test instruction l.lwz */ - - /* Load with zero offset. */ - TEST_LW l.lwz 50b, 0 - TEST_LW l.lwz 51b, 0 - TEST_LW l.lwz 52b, 0 - TEST_LW l.lwz 53b, 0 - TEST_LW l.lwz 54b, 0 - - /* Load with positive offset. */ - TEST_LW l.lwz 50b, 4 - TEST_LW l.lwz 50b, 8 - TEST_LW l.lwz 50b, 12 - TEST_LW l.lwz 50b, 16 - - /* Load with negative offset. */ - TEST_LW l.lwz 54b, -16 - TEST_LW l.lwz 54b, -12 - TEST_LW l.lwz 54b, -8 - TEST_LW l.lwz 54b, -4 - - /* TODO: add here test cases to cover unaligned memory accesses - with l.lwz. */ - - /* Test instruction l.lbz */ - - /* Read data at label 50, forwards, byte by byte. */ - LOAD_IMMEDIATE r5, 50b - - l.lbz r4, 0(r5) - REPORT_REG_TO_CONSOLE r4 - - l.lbz r4, 1(r5) - REPORT_REG_TO_CONSOLE r4 - - l.lbz r4, 2(r5) - REPORT_REG_TO_CONSOLE r4 - - l.lbz r4, 3(r5) - REPORT_REG_TO_CONSOLE r4 - - /* Read data at label 50, backwards, byte by byte. */ - LOAD_IMMEDIATE r31, 51b - - l.lbz r3, -1(r31) - REPORT_REG_TO_CONSOLE r3 - - l.lbz r3, -2(r31) - REPORT_REG_TO_CONSOLE r3 - - l.lbz r3, -3(r31) - REPORT_REG_TO_CONSOLE r3 - - l.lbz r3, -4(r31) - REPORT_REG_TO_CONSOLE r3 - - /* Test instruction l.lbs */ - - /* Read data at label 50, forwards, byte by byte. */ - LOAD_IMMEDIATE r5, 50b - - l.lbs r4, 0(r5) - REPORT_REG_TO_CONSOLE r4 - - l.lbs r4, 1(r5) - REPORT_REG_TO_CONSOLE r4 - - l.lbs r4, 2(r5) - REPORT_REG_TO_CONSOLE r4 - - l.lbs r4, 3(r5) - REPORT_REG_TO_CONSOLE r4 - - /* Read data at label 50, backwards, byte by byte. */ - LOAD_IMMEDIATE r31, 51b - - l.lbs r3, -1(r31) - REPORT_REG_TO_CONSOLE r3 - - l.lbs r3, -2(r31) - REPORT_REG_TO_CONSOLE r3 - - l.lbs r3, -3(r31) - REPORT_REG_TO_CONSOLE r3 - - l.lbs r3, -4(r31) - REPORT_REG_TO_CONSOLE r3 - - /* Test instruction l.lhz */ - - /* Read data at label 50, forwards, half-word by half-word. */ - LOAD_IMMEDIATE r5, 50b - - l.lhz r4, 0(r5) - REPORT_REG_TO_CONSOLE r4 - - l.lhz r4, 2(r5) - REPORT_REG_TO_CONSOLE r4 - - /* Read data at label 50, backwards, half-word by half-word. */ - LOAD_IMMEDIATE r31, 51b - - l.lhz r3, -2(r31) - REPORT_REG_TO_CONSOLE r3 - - l.lhz r3, -4(r31) - REPORT_REG_TO_CONSOLE r3 - - /* TODO: add here test cases to cover unaligned memory accesses - with l.lhz. */ - - /* Test instruction l.lhs */ - - /* Read data at label 50, forwards, half-word by half-word. */ - LOAD_IMMEDIATE r5, 50b - - l.lhs r4, 0(r5) - REPORT_REG_TO_CONSOLE r4 - - l.lhs r4, 2(r5) - REPORT_REG_TO_CONSOLE r4 - - /* Read data at label 50, backwards, half-word by half-word. */ - LOAD_IMMEDIATE r31, 51b - - l.lhs r3, -2(r31) - REPORT_REG_TO_CONSOLE r3 - - l.lhs r3, -4(r31) - REPORT_REG_TO_CONSOLE r3 - - /* TODO: add here test cases to cover unaligned memory accesses - with l.lhs. */ - - /* Test instruction l.sb */ - - /* Write 32-bits forwards, byte-to-byte. */ - LOAD_IMMEDIATE r5, buffer1 - - LOAD_IMMEDIATE r10, 0xA1 - LOAD_IMMEDIATE r11, 0xA2 - LOAD_IMMEDIATE r12, 0xA3 - LOAD_IMMEDIATE r13, 0xA4 - - l.sb 0(r5), r10 - l.sb 1(r5), r11 - l.sb 2(r5), r12 - l.sb 3(r5), r13 - - l.lwz r3, 0(r5) - REPORT_REG_TO_CONSOLE r3 - - /* Write 32-bits backwards, byte-to-byte. */ - LOAD_IMMEDIATE r6, buffer2 - - LOAD_IMMEDIATE r10, 0xB1 - LOAD_IMMEDIATE r11, 0xB2 - LOAD_IMMEDIATE r12, 0xB3 - LOAD_IMMEDIATE r13, 0xB4 - - l.sb -1(r6), r10 - l.sb -2(r6), r11 - l.sb -3(r6), r12 - l.sb -4(r6), r13 - - l.lwz r3, 0(r5) - REPORT_REG_TO_CONSOLE r3 - - /* TODO: add here test cases to cover unaligned memory accesses - with l.sb. */ - - /* Test instruction l.sh */ - - /* Write 32-bits forwards, one half-word at a time. */ - LOAD_IMMEDIATE r5, buffer1 - - LOAD_IMMEDIATE r10, 0x8182 - LOAD_IMMEDIATE r11, 0x8384 - - l.sh 0(r5), r10 - l.sh 2(r5), r11 - - l.lwz r3, 0(r5) - REPORT_REG_TO_CONSOLE r3 - - /* Write 32-bits backwards, one half-word at a time. */ - LOAD_IMMEDIATE r6, buffer2 - - LOAD_IMMEDIATE r10, 0x5152 - LOAD_IMMEDIATE r11, 0x5354 - - l.sh -2(r6), r10 - l.sh -4(r6), r11 - - l.lwz r3, 0(r5) - REPORT_REG_TO_CONSOLE r3 - - /* TODO: add here test cases to cover unaligned memory accesses - with l.sh. */ - - /* Test instruction l.sw */ - LOAD_IMMEDIATE r5, buffer1 - LOAD_IMMEDIATE r6, buffer5 - - LOAD_IMMEDIATE r10, 0xA0B0C0D0 - LOAD_IMMEDIATE r11, 0xA1B1C1D1 - LOAD_IMMEDIATE r12, 0xA2B2C2D2 - LOAD_IMMEDIATE r13, 0xA3B3C3D3 - - l.sw 0(r5), r10 - l.sw 4(r5), r11 - l.sw -4(r6), r12 - l.sw -8(r6), r13 - - TEST_LW l.lwz buffer1, 0 - TEST_LW l.lwz buffer2, 0 - TEST_LW l.lwz buffer3, 0 - TEST_LW l.lwz buffer4, 0 - - /* TODO: add here test cases to cover unaligned memory accesses - with l.sw. */ - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/mac.S b/sim/testsuite/sim/or1k/mac.S deleted file mode 100644 index c57a78f..0000000 --- a/sim/testsuite/sim/or1k/mac.S +++ /dev/null @@ -1,778 +0,0 @@ -/* Tests the MAC instructions. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x00000000);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x0000000c);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x40000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0x00000006);\n -# output: report(0x80000000);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x7ffffffe);\n -# output: report(0x00000000);\n -# output: report(0x80000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x7ffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x0000000c);\n -# output: report(0x00000000);\n -# output: report(0x00000005);\n -# output: report(0xffffffff);\n -# output: report(0xfffffffa);\n -# output: report(0x00000000);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0x7fffffff);\n -# output: report(0xfffffff9);\n -# output: report(0xffffffff);\n -# output: report(0xfffffff9);\n -# output: report(0xfffffffe);\n -# output: report(0xffffffff);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0x80000000);\n -# output: report(0xffffffff);\n -# output: report(0x80000006);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0x7fffffff);\n -# output: report(0xffffffff);\n -# output: report(0x7fffffff);\n -# output: report(0xfffffffe);\n -# output: report(0xffffffff);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x0000000c);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x40000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0x00000006);\n -# output: report(0x80000000);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x7ffffffe);\n -# output: report(0x00000000);\n -# output: report(0x80000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x7ffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x0000000c);\n -# output: report(0x00000000);\n -# output: report(0x00000005);\n -# output: report(0xffffffff);\n -# output: report(0xfffffffa);\n -# output: report(0x00000000);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0x7fffffff);\n -# output: report(0xfffffff9);\n -# output: report(0xffffffff);\n -# output: report(0xfffffff9);\n -# output: report(0xfffffffe);\n -# output: report(0xffffffff);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0x80000000);\n -# output: report(0xffffffff);\n -# output: report(0x80000006);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0x7fffffff);\n -# output: report(0xffffffff);\n -# output: report(0x7fffffff);\n -# output: report(0xfffffffe);\n -# output: report(0xffffffff);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000006);\n -# output: report(0x0000000c);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000006);\n -# output: report(0x00000006);\n -# output: report(0x7ffffffe);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0x7ffffffd);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000006);\n -# output: report(0x0000000c);\n -# output: report(0x00000005);\n -# output: report(0xfffffffa);\n -# output: report(0x00000006);\n -# output: report(0xffffffff);\n -# output: report(0xfffffff9);\n -# output: report(0xfffffff9);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x80000000);\n -# output: report(0x80000006);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0x7fffffff);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0xfffffffa);\n -# output: report(0x00000000);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0xfffffffa);\n -# output: report(0x3fffffff);\n -# output: report(0xfffffffa);\n -# output: report(0xffffffff);\n -# output: report(0xfffffff4);\n -# output: report(0xfffffffe);\n -# output: report(0xffffffff);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0xffffffff);\n -# output: report(0x80000002);\n -# output: report(0xffffffff);\n -# output: report(0x80000004);\n -# output: report(0x00000000);\n -# output: report(0x00000004);\n -# output: report(0x7ffffffe);\n -# output: report(0xffffffff);\n -# output: report(0xffffffff);\n -# output: report(0x80000001);\n -# output: report(0xffffffff);\n -# output: report(0x00000004);\n -# output: report(0xfffffffe);\n -# output: report(0x00000004);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000006);\n -# output: report(0xffffffff);\n -# output: report(0xfffffff9);\n -# output: report(0x00000000);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x0000000c);\n -# output: report(0x00000001);\n -# output: report(0x00000005);\n -# output: report(0x7fffffff);\n -# output: report(0xffffffff);\n -# output: report(0xffffffff);\n -# output: report(0xffffffff);\n -# output: report(0xffffffff);\n -# output: report(0x00000005);\n -# output: report(0x80000000);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x80000006);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x7fffffff);\n -# output: report(0xffffffff);\n -# output: report(0x7fffffff);\n -# output: report(0x80000000);\n -# output: report(0x80000000);\n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - .macro TEST_MACRC mac_hi, mac_lo, op1, op2 - LOAD_IMMEDIATE r2, \mac_hi - MOVE_TO_SPR SPR_MACHI, r2 - LOAD_IMMEDIATE r2, \mac_lo - MOVE_TO_SPR SPR_MACLO, r2 - LOAD_IMMEDIATE r5, \op1 - LOAD_IMMEDIATE r6, \op2 - l.mac r5, r6 - l.macrc r3 - REPORT_REG_TO_CONSOLE r3 - .endm - - .macro TEST_MAC mac_hi, mac_lo, op1, op2 - LOAD_IMMEDIATE r2, \mac_hi - MOVE_TO_SPR SPR_MACHI, r2 - LOAD_IMMEDIATE r2, \mac_lo - MOVE_TO_SPR SPR_MACLO, r2 - LOAD_IMMEDIATE r5, \op1 - LOAD_IMMEDIATE r6, \op2 - l.mac r5, r6 - MOVE_FROM_SPR r3, SPR_MACHI - REPORT_REG_TO_CONSOLE r3 - MOVE_FROM_SPR r3, SPR_MACLO - REPORT_REG_TO_CONSOLE r3 - .endm - - .macro TEST_MACI mac_hi, mac_lo, op1, op2_immediate - LOAD_IMMEDIATE r2, \mac_hi - MOVE_TO_SPR SPR_MACHI, r2 - LOAD_IMMEDIATE r2, \mac_lo - MOVE_TO_SPR SPR_MACLO, r2 - LOAD_IMMEDIATE r5, \op1 - l.maci r5, \op2_immediate - MOVE_FROM_SPR r3, SPR_MACHI - REPORT_REG_TO_CONSOLE r3 - MOVE_FROM_SPR r3, SPR_MACLO - REPORT_REG_TO_CONSOLE r3 - .endm - - .macro TEST_MSB mac_hi, mac_lo, op1, op2 - LOAD_IMMEDIATE r2, \mac_hi - MOVE_TO_SPR SPR_MACHI, r2 - LOAD_IMMEDIATE r2, \mac_lo - MOVE_TO_SPR SPR_MACLO, r2 - LOAD_IMMEDIATE r5, \op1 - LOAD_IMMEDIATE r6, \op2 - l.msb r5, r6 - MOVE_FROM_SPR r3, SPR_MACHI - REPORT_REG_TO_CONSOLE r3 - MOVE_FROM_SPR r3, SPR_MACLO - REPORT_REG_TO_CONSOLE r3 - .endm - - STANDARD_TEST_ENVIRONMENT - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test the l.mac instruction. */ - - /* two small positive numbers */ - - /* MAC two small positive numbers on a zero total */ - TEST_MAC 0x00000000, 0x00000000, 0x00000002, 0x00000003 - - /* MAC two small positive numbers on a small positive total */ - TEST_MAC 0x00000000, 0x00000006, 0x00000002, 0x00000003, - - /* MAC two small positive numbers on a moderate positive total */ - TEST_MAC 0x00000000, 0xfffffffa, 0x00000002, 0x00000003 - - /* MAC two small positive numbers on a large positive total */ - TEST_MAC 0x3fffffff, 0xfffffffa, 0x00000002, 0x00000003 - - /* MAC two small positive numbers on a small negative total */ - TEST_MAC 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003 - - /* MAC two small positive numbers on a moderate negative total */ - TEST_MAC 0xffffffff, 0x00000000, 0x00000002, 0x00000003 - - /* MAC two small positive numbers on a large negative total */ - TEST_MAC 0x80000000, 0x00000000, 0x00000002, 0x00000003 - - /* two moderate positive numbers */ - - /* MAC two moderate positive numbers on a zero total */ - TEST_MAC 0x00000000, 0x00000000, 0x00008001, 0x0000fffe - - /* MAC two moderate positive numbers on a small positive total */ - TEST_MAC 0x00000000, 0x00000002, 0x00008001, 0x0000fffe - - /* MAC two moderate positive numbers on a moderate positive total */ - TEST_MAC 0x00000000, 0x80000002, 0x00008001, 0x0000fffe - - /* MAC two moderate positive numbers on a large positive total */ - TEST_MAC 0x7fffffff, 0x80000001, 0x00008001, 0x0000fffe - - /* MAC two moderate positive numbers on a small negative total */ - TEST_MAC 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe - - /* MAC two moderate positive numbers on a moderate negative total */ - TEST_MAC 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe - - /* MAC two moderate positive numbers on a large negative total */ - TEST_MAC 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe - - /* two small negative numbers */ - - /* MAC two small negative numbers on a zero total */ - TEST_MAC 0x00000000, 0x00000000, 0xfffffffe, 0xfffffffd - - /* MAC two small negative numbers on a small positive total */ - TEST_MAC 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd - - /* MAC two small negative numbers on a small negative total */ - TEST_MAC 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd - - /* one small positive and one small negative */ - - /* MAC one small positive and one small negative number on a zero - total */ - TEST_MAC 0x00000000, 0x00000000, 0x00000002, 0xfffffffd - - /* MAC one small positive and one small negative number on a small - positive total */ - TEST_MAC 0x00000000, 0x0000000c, 0x00000002, 0xfffffffd - - /* MAC one small positive and one small negative number on a - moderate positive total */ - TEST_MAC 0x00000001, 0x00000005, 0x00000002, 0xfffffffd - - /* MAC one small positive and one small negative number on a large - positive total */ - TEST_MAC 0x7fffffff, 0xffffffff, 0x00000002, 0xfffffffd - - /* MAC one small positive and one small negative number on a small - negative total */ - TEST_MAC 0xffffffff, 0xffffffff, 0x00000002, 0xfffffffd - - /* MAC one small positive and one small negative number on a - moderate negative total */ - TEST_MAC 0xffffffff, 0x00000005, 0x00000002, 0xfffffffd - - /* MAC one small positive and one small negative number on a large - negative total */ - TEST_MAC 0x80000000, 0x00000006, 0x00000002, 0xfffffffd - - /* one moderate positive and one moderate negative number */ - - /* MAC one moderate positive and one moderate negative number on a - zero total */ - TEST_MAC 0x00000000, 0x00000000, 0x00008000, 0xffff0000 - - /* MAC one moderate positive and one moderate negative number on a - small positive total */ - TEST_MAC 0x00000000, 0x00000006, 0x00008000, 0xffff0000 - - /* MAC one moderate positive and one moderate negative number on a - moderate positive total */ - TEST_MAC 0x00000000, 0x80000000, 0x00008000, 0xffff0000 - - /* MAC one moderate positive and one moderate negative number on a - large positive total */ - TEST_MAC 0x7fffffff, 0xffffffff, 0x00008000, 0xffff0000 - - /* MAC one moderate positive and one moderate negative number on a - small negative total */ - TEST_MAC 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000 - - /* MAC one moderate positive and one moderate negative number on a - moderate negative total */ - TEST_MAC 0xffffffff, 0x7fffffff, 0x00008000, 0xffff0000 - - /* MAC one moderate positive and one moderate negative number on a - large negative total */ - TEST_MAC 0x80000000, 0x80000000, 0x00008000, 0xffff0000 - - /* Test the l.maci instruction. */ - - /* two small positive numbers */ - - /* MAC two small positive numbers on a zero total */ - TEST_MACI 0x00000000, 0x00000000, 0x00000002, 0x0003 - - /* MAC two small positive numbers on a small positive total */ - TEST_MACI 0x00000000, 0x00000006, 0x00000002, 0x0003 - - /* MAC two small positive numbers on a moderate positive total */ - TEST_MACI 0x00000000, 0xfffffffa, 0x00000002, 0x0003 - - /* MAC two small positive numbers on a large positive total */ - TEST_MACI 0x3fffffff, 0xfffffffa, 0x00000002, 0x0003 - - /* MAC two small positive numbers on a small negative total */ - TEST_MACI 0xffffffff, 0xfffffffa, 0x00000002, 0x0003 - - /* MAC two small positive numbers on a moderate negative total */ - TEST_MACI 0xffffffff, 0x00000000, 0x00000002, 0x0003 - - /* MAC two small positive numbers on a large negative total */ - TEST_MACI 0x80000000, 0x00000000, 0x00000002, 0x0003 - - /* two moderate positive numbers */ - - /* MAC two moderate positive numbers on a zero total */ - TEST_MACI 0x00000000, 0x00000000, 0x00010002, 0x7fff - - /* MAC two moderate positive numbers on a small positive total */ - TEST_MACI 0x00000000, 0x00000002, 0x00010002, 0x7fff - - /* MAC two moderate positive numbers on a moderate positive total */ - TEST_MACI 0x00000000, 0x80000002, 0x00010002, 0x7fff - - /* MAC two moderate positive numbers on a large positive total */ - TEST_MACI 0x7fffffff, 0x80000001, 0x00010002, 0x7fff - - /* MAC two moderate positive numbers on a small negative total */ - TEST_MACI 0xffffffff, 0xffffffff, 0x00010002, 0x7fff - - /* MAC two moderate positive numbers on a moderate negative total */ - TEST_MACI 0xffffffff, 0x80000002, 0x00010002, 0x7fff - - /* MAC two moderate positive numbers on a large negative total */ - TEST_MACI 0xfffffffe, 0x80000002, 0x00010002, 0x7fff - - /* two small negative numbers */ - - /* MAC two small negative numbers on a zero total */ - TEST_MACI 0x00000000, 0x00000000, 0xfffffffe, 0xfffd - - /* MAC two small negative numbers on a small positive total */ - TEST_MACI 0x00000000, 0x00000006, 0xfffffffe, 0xfffd - - /* MAC two small negative numbers on a small negative total */ - TEST_MACI 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffd - - /* one small positive and one small negative */ - - /* MAC one small positive and one small negative number on a zero - total */ - TEST_MACI 0x00000000, 0x00000000, 0x00000002, 0xfffd - - /* MAC one small positive and one small negative number on a small - positive total */ - TEST_MACI 0x00000000, 0x0000000c, 0x00000002, 0xfffd - - /* MAC one small positive and one small negative number on a - moderate positive total */ - TEST_MACI 0x00000001, 0x00000005, 0x00000002, 0xfffd - - /* MAC one small positive and one small negative number on a large - positive total */ - TEST_MACI 0x7fffffff, 0xffffffff, 0x00000002, 0xfffd - - /* MAC one small positive and one small negative number on a small - negative total */ - TEST_MACI 0xffffffff, 0xffffffff, 0x00000002, 0xfffd - - /* MAC one small positive and one small negative number on a - moderate negative total */ - TEST_MACI 0xffffffff, 0x00000005, 0x00000002, 0xfffd - - /* MAC one small positive and one small negative number on a large - negative total */ - TEST_MACI 0x80000000, 0x00000006, 0x00000002, 0xfffd - - /* one moderate positive and one moderate negative */ - - /* MAC one moderate positive and one moderate negative number on a - zero total */ - TEST_MACI 0x00000000, 0x00000000, 0x00010000, 0x8000 - - /* MAC one moderate positive and one moderate negative number on a - small positive total */ - TEST_MACI 0x00000000, 0x00000006, 0x00010000, 0x8000 - - /* MAC one moderate positive and one moderate negative number on a - moderate positive total */ - TEST_MACI 0x00000000, 0x80000000, 0x00010000, 0x8000 - - /* MAC one moderate positive and one moderate negative number on a - large positive total */ - TEST_MACI 0x7fffffff, 0xffffffff, 0x00010000, 0x8000 - - /* MAC one moderate positive and one moderate negative number on a - small negative total */ - TEST_MACI 0xffffffff, 0xffffffff, 0x00010000, 0x8000 - - /* MAC one moderate positive and one moderate negative number on a - moderate negative total */ - TEST_MACI 0xffffffff, 0x7fffffff, 0x00010000, 0x8000 - - /* MAC one moderate positive and one moderate negative number on a - large negative total */ - TEST_MACI 0x80000000, 0x80000000, 0x00010000, 0x8000 - - /* Test the l.macrc instruction. - - Note that these tests use the same input data as the ones for - l.mac above. The results are the same, but only the low 32-bits - are compared. */ - - /* two small positive numbers */ - - /* MAC two small positive numbers on a zero total */ - TEST_MACRC 0x00000000, 0x00000000, 0x00000002, 0x00000003 - - /* MAC two small positive numbers on a small positive total */ - TEST_MACRC 0x00000000, 0x00000006, 0x00000002, 0x00000003 - - /* MAC two small positive numbers on a moderate positive total */ - TEST_MACRC 0x00000000, 0xfffffffa, 0x00000002, 0x00000003 - - /* MAC two small positive numbers on a large positive total */ - TEST_MACRC 0x3fffffff, 0xfffffffa, 0x00000002, 0x00000003 - - /* MAC two small positive numbers on a small negative total */ - TEST_MACRC 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003 - - /* MAC two small positive numbers on a moderate negative total */ - TEST_MACRC 0xffffffff, 0x00000000, 0x00000002, 0x00000003 - - /* MAC two small positive numbers on a large negative total */ - TEST_MACRC 0x80000000, 0x00000000, 0x00000002, 0x00000003 - - /* two moderate positive numbers */ - - /* MAC two moderate positive numbers on a zero total */ - TEST_MACRC 0x00000000, 0x00000000, 0x00008001, 0x0000fffe - - /* MAC two moderate positive numbers on a small positive total */ - TEST_MACRC 0x00000000, 0x00000002, 0x00008001, 0x0000fffe - - /* MAC two moderate positive numbers on a moderate positive total */ - TEST_MACRC 0x00000000, 0x80000002, 0x00008001, 0x0000fffe - - /* MAC two moderate positive numbers on a large positive total */ - TEST_MACRC 0x7fffffff, 0x80000001, 0x00008001, 0x0000fffe - - /* MAC two moderate positive numbers on a small negative total */ - TEST_MACRC 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe - - /* MAC two moderate positive numbers on a moderate negative total */ - TEST_MACRC 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe - - /* MAC two moderate positive numbers on a large negative total */ - TEST_MACRC 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe - - /* two small negative numbers */ - - /* MAC two small negative numbers on a zero total */ - TEST_MACRC 0x00000000, 0x00000000, 0xfffffffe, 0xfffffffd - - /* MAC two small negative numbers on a small positive total */ - TEST_MACRC 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd - - /* MAC two small negative numbers on a small negative total */ - TEST_MACRC 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd - - /* one small positive and one small negative number */ - - /* MAC one small positive and one small negative number on a zero - total */ - TEST_MACRC 0x00000000, 0x00000000, 0x00000002, 0xfffffffd - - /* MAC one small positive and one small negative number on a small - positive total */ - TEST_MACRC 0x00000000, 0x0000000c, 0x00000002, 0xfffffffd - - /* MAC one small positive and one small negative number on a - moderate positive total */ - TEST_MACRC 0x00000001, 0x00000005, 0x00000002, 0xfffffffd - - /* MAC one small positive and one small negative number on a large - positive total */ - TEST_MACRC 0x7fffffff, 0xffffffff, 0x00000002, 0xfffffffd - - /* MAC one small positive and one small negative number on a small - negative total */ - TEST_MACRC 0xffffffff, 0xffffffff, 0x00000002, 0xfffffffd - - /* MAC one small positive and one small negative number on a - moderate negative total */ - TEST_MACRC 0xffffffff, 0x00000005, 0x00000002, 0xfffffffd - - /* MAC one small positive and one small negative number on a large - negative total */ - TEST_MACRC 0x80000000, 0x00000006, 0x00000002, 0xfffffffd - - /* one moderate positive and one moderate negative */ - - /* MAC one moderate positive and one moderate negative number on a - zero total */ - TEST_MACRC 0x00000000, 0x00000000, 0x00008000, 0xffff0000 - - /* MAC one moderate positive and one moderate negative number on a - small positive total */ - TEST_MACRC 0x00000000, 0x00000006, 0x00008000, 0xffff0000 - - /* MAC one moderate positive and one moderate negative number on a - moderate positive total */ - TEST_MACRC 0x00000000, 0x80000000, 0x00008000, 0xffff0000 - - /* MAC one moderate positive and one moderate negative number on a - large positive total */ - TEST_MACRC 0x7fffffff, 0xffffffff, 0x00008000, 0xffff0000 - - /* MAC one moderate positive and one moderate negative number on a - small negative total */ - TEST_MACRC 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000 - - /* MAC one moderate positive and one moderate negative number on a - moderate negative total */ - TEST_MACRC 0xffffffff, 0x7fffffff, 0x00008000, 0xffff0000 - - /* MAC one moderate positive and one moderate negative number on a - large negative total */ - TEST_MACRC 0x80000000, 0x80000000, 0x00008000, 0xffff0000 - - /* Test the l.msb instruction. */ - - /* MSB two small positive numbers on a zero total */ - TEST_MSB 0x00000000, 0x00000000, 0x00000002, 0x00000003 - - /* MSB two small positive numbers on a small positive total */ - TEST_MSB 0x00000000, 0x0000000c, 0x00000002, 0x00000003 - - /* MSB two small positive numbers on a moderate positive total */ - TEST_MSB 0x00000001, 0x00000000, 0x00000002, 0x00000003 - - /* MSB two small positive numbers on a large positive total */ - TEST_MSB 0x40000000, 0x00000000, 0x00000002, 0x00000003 - - /* MSB two small positive numbers on a small negative total */ - TEST_MSB 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003 - - /* MSB two small positive numbers on a moderate negative total */ - TEST_MSB 0xffffffff, 0x00000005, 0x00000002, 0x00000003 - - /* MSB two small positive numbers on a large negative total */ - TEST_MSB 0x80000000, 0x00000006, 0x00000002, 0x00000003 - - /* two moderate positive numbers */ - - /* MSB two moderate positive numbers on a zero total */ - TEST_MSB 0x00000000, 0x00000000, 0x00008001, 0x0000fffe - - /* MSB two moderate positive numbers on a small positive total */ - TEST_MSB 0x00000000, 0x00000002, 0x00008001, 0x0000fffe - - /* MSB two moderate positive numbers on a moderate positive total */ - TEST_MSB 0x00000000, 0x80000002, 0x00008001, 0x0000fffe - - /* MSB two moderate positive numbers on a large positive total */ - TEST_MSB 0x7fffffff, 0x7ffffffd, 0x00008001, 0x0000fffe - - /* MSB two moderate positive numbers on a small negative total */ - TEST_MSB 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe - - /* MSB two moderate positive numbers on a moderate negative total */ - TEST_MSB 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe - - /* MSB two moderate positive numbers on a large negative total */ - TEST_MSB 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe - - /* two small negative numbers */ - - /* MSB two small negative numbers on a zero total */ - TEST_MSB 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd - - /* MSB two small negative numbers on a small positive total */ - TEST_MSB 0x00000000, 0x0000000c, 0xfffffffe, 0xfffffffd - - /* MSB two small negative numbers on a small negative total */ - TEST_MSB 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd - - /* one small positive and one small negative number */ - - /* MSB one small positive and one small negative number on a zero - total */ - TEST_MSB 0x00000000, 0x00000000, 0x00000002, 0xfffffffd - - /* MSB one small positive and one small negative number on a small - positive total */ - TEST_MSB 0x00000000, 0x00000006, 0x00000002, 0xfffffffd - - /* MSB one small positive and one small negative number on a - moderate positive total */ - TEST_MSB 0x00000000, 0xffffffff, 0x00000002, 0xfffffffd - - /* MSB one small positive and one small negative number on a large - positive total */ - TEST_MSB 0x7fffffff, 0xfffffff9, 0x00000002, 0xfffffffd - - /* MSB one small positive and one small negative number on a small - negative total */ - TEST_MSB 0xffffffff, 0xfffffff9, 0x00000002, 0xfffffffd - - /* MSB one small positive and one small negative number on a - moderate negative total */ - TEST_MSB 0xfffffffe, 0xffffffff, 0x00000002, 0xfffffffd - - /* MSB one small positive and one small negative number on a large - negative total */ - TEST_MSB 0x80000000, 0x00000000, 0x00000002, 0xfffffffd - - /* one moderate positive and one moderate negative number */ - - /* MSB one moderate positive and one moderate negative number on a - zero total */ - TEST_MSB 0x00000000, 0x00000000, 0x00008000, 0xffff0000 - - /* MSB one moderate positive and one moderate negative number on a - small positive total */ - TEST_MSB 0x00000000, 0x00000006, 0x00008000, 0xffff0000 - - /* MSB one moderate positive and one moderate negative number on a - moderate positive total */ - TEST_MSB 0x00000000, 0x80000000, 0x00008000, 0xffff0000 - - /* MSB one moderate positive and one moderate negative number on a - large positive total */ - TEST_MSB 0x7fffffff, 0x7fffffff, 0x00008000, 0xffff0000 - - /* MSB one moderate positive and one moderate negative number on a - small negative total */ - TEST_MSB 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000 - - /* MSB one moderate positive and one moderate negative number on a - moderate negative total */ - TEST_MSB 0xfffffffe, 0xffffffff, 0x00008000, 0xffff0000 - - /* MSB one moderate positive and one moderate negative number on a - large negative total */ - TEST_MSB 0x80000000, 0x00000000, 0x00008000, 0xffff0000 - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/mfspr.S b/sim/testsuite/sim/or1k/mfspr.S deleted file mode 100644 index 1aa74e1..0000000 --- a/sim/testsuite/sim/or1k/mfspr.S +++ /dev/null @@ -1,171 +0,0 @@ -/* Tests instructions l.mfspr and l.mtspr. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x00000000);\n -# output: report(0x00002801);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00002801);\n -# output: report(0x00000000);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00002801);\n -# output: report(0x00002801);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00000801);\n -# output: report(0x00002000);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00002000);\n -# output: report(0x00000801);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00002801);\n -# output: report(0x00000001);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00000800);\n -# output: report(0x00002801);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00000000);\n -# output: report(0x00002801);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00002801);\n -# output: report(0x00000000);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00002801);\n -# output: report(0x00002801);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00000801);\n -# output: report(0x00002000);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00002000);\n -# output: report(0x00000801);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00002801);\n -# output: report(0x00000001);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: report(0x00000800);\n -# output: report(0x00002801);\n -# output: report(0xdeadbeef);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-env.h" - -#define MACLO_VAL 0xdeadbeef - - /* A macro to carry out a test of l.mfspr. - - MACLO (0x2801) is used as the SPR, since it can be read and - cleared using l.macrc and can be set using l.maci. spr_number - and immediate_val_to_or should be chosen to address this - register. - - The value placed in the register is entirely arbitrary - we use - 0xdeadbeef. */ - - .macro TEST_MFSPR spr_number, immediate_val_to_or - REPORT_IMMEDIATE_TO_CONSOLE \spr_number - REPORT_IMMEDIATE_TO_CONSOLE \immediate_val_to_or - /* Write MACLO_VAL to MACLO. */ - l.macrc r2 - LOAD_IMMEDIATE r2, MACLO_VAL - l.maci r2, 1 - LOAD_IMMEDIATE r5, \spr_number - l.mfspr r4, r5, \immediate_val_to_or - REPORT_REG_TO_CONSOLE r4 - PRINT_NEWLINE_TO_CONSOLE - .endm - - /* A macro to carry out a test of l.mtspr - - MACLO (0x2801) is used as the SPR, since it can be read and - cleared using l.macrc and can be set using l.maci. The - arguments spr_number and immediate_val_to_or should be chosen - to address this register. - - The value placed in the register is entirely arbitrary - we use - 0xdeadbeef. */ - - .macro TEST_MTSPR spr_number, immediate_val_to_or - REPORT_IMMEDIATE_TO_CONSOLE \spr_number - REPORT_IMMEDIATE_TO_CONSOLE \immediate_val_to_or - /* Clear MACLO */ - l.macrc r2 - LOAD_IMMEDIATE r4, MACLO_VAL - LOAD_IMMEDIATE r5, \spr_number - l.mtspr r5, r4, \immediate_val_to_or - /* Retrieve MACLO. */ - l.macrc r4 - REPORT_REG_TO_CONSOLE r4 - PRINT_NEWLINE_TO_CONSOLE - .endm - - STANDARD_TEST_ENVIRONMENT - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test the l.mfspr instruction with a range of operands. */ - - /* Move a test value using zero in the register. */ - TEST_MFSPR SPR_VR, SPR_MACLO /* 0x0000, 0x2801 */ - - /* Move a test value using zero as the constant. */ - TEST_MFSPR SPR_MACLO, SPR_VR /* 0x2801, 0x0000 */ - - /* Move a test value using non-zero in both register and constant. */ - - /* Some of these values will not give the correct result if OR - rather than ADD is used to determine the SPR address. */ - TEST_MFSPR SPR_MACLO, SPR_MACLO /* 0x2801, 0x2801 */ - TEST_MFSPR SPR_DMMUPR, SPR_ICCR /* 0x0801, 0x2000 */ - TEST_MFSPR SPR_ICCR, SPR_DMMUPR /* 0x2000, 0x0801 */ - TEST_MFSPR SPR_MACLO, SPR_UPR /* 0x2801, 0x0001 */ - TEST_MFSPR SPR_DMMUCR, SPR_MACLO /* 0x0800, 0x2801 */ - - /* Test the l.mtspr instruction with a range of operands. */ - - /* Move a test value using zero in the register. */ - TEST_MTSPR SPR_VR, SPR_MACLO /* 0x0000, 0x2801 */ - - /* Move a test value using zero as the constant. */ - TEST_MTSPR SPR_MACLO, SPR_VR /* 0x2801, 0x0000 */ - - /* Move a test value using non-zero in both register and constant. */ - - /* Some of these values will not give the correct result if or - rather than add is used to determine the SPR address. */ - TEST_MTSPR SPR_MACLO, SPR_MACLO /* 0x2801, 0x2801 */ - TEST_MTSPR SPR_DMMUPR, SPR_ICCR /* 0x0801, 0x2000 */ - TEST_MTSPR SPR_ICCR, SPR_DMMUPR /* 0x2000, 0x0801 */ - TEST_MTSPR SPR_MACLO, SPR_UPR /* 0x2801, 0x0001 */ - TEST_MTSPR SPR_DMMUCR, SPR_MACLO /* 0x0800, 0x2801 */ - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/mul.S b/sim/testsuite/sim/or1k/mul.S deleted file mode 100644 index e126be8..0000000 --- a/sim/testsuite/sim/or1k/mul.S +++ /dev/null @@ -1,565 +0,0 @@ -/* Tests the multiply instructions. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x00000002);\n -# output: report(0x00000003);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00008001);\n -# output: report(0x0000fffe);\n -# output: report(0x7ffffffe);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00008000);\n -# output: report(0x00010000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00010000);\n -# output: report(0x00010000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffffe);\n -# output: report(0xfffffffd);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffff7fff);\n -# output: report(0xffff0002);\n -# output: report(0x7ffffffe);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffff7fff);\n -# output: report(0xffff0000);\n -# output: report(0x80010000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffff0000);\n -# output: report(0xfffeffff);\n -# output: report(0x00010000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000002);\n -# output: report(0xfffffffd);\n -# output: report(0xfffffffa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffff8000);\n -# output: report(0x00010000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffff7fff);\n -# output: report(0x00010000);\n -# output: report(0x7fff0000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x80000000);\n -# output: report(0x00000001);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00008000);\n -# output: report(0x00010000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x00000002);\n -# output: report(0xfffffffd);\n -# output: report(0xfffffffa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffff7fff);\n -# output: report(0xffff0000);\n -# output: report(0x80010000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x00000002);\n -# output: report(0x00000003);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00010002);\n -# output: report(0x00007fff);\n -# output: report(0x7ffffffe);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00020000);\n -# output: report(0x00004000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00040000);\n -# output: report(0x00004000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffffe);\n -# output: report(0x0000fffd);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffefffe);\n -# output: report(0x00008001);\n -# output: report(0x7ffffffe);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffe0000);\n -# output: report(0x0000bfff);\n -# output: report(0x80020000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffdfffe);\n -# output: report(0x00008000);\n -# output: report(0x00010000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000002);\n -# output: report(0x0000fffd);\n -# output: report(0xfffffffa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00010000);\n -# output: report(0x00008000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffdfffc);\n -# output: report(0x00004000);\n -# output: report(0x7fff0000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x80000000);\n -# output: report(0x00000001);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00020000);\n -# output: report(0x00004000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0xfffffffe);\n -# output: report(0x0000fffd);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffdfffe);\n -# output: report(0x00008000);\n -# output: report(0x00010000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x00000002);\n -# output: report(0x00000003);\n -# output: report(0x00000006);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00008001);\n -# output: report(0x0000fffe);\n -# output: report(0x7ffffffe);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00008000);\n -# output: report(0x00010000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00010000);\n -# output: report(0x00010000);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffffe);\n -# output: report(0xfffffffd);\n -# output: report(0x00000006);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffff7fff);\n -# output: report(0xffff0002);\n -# output: report(0x7ffffffe);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffff7fff);\n -# output: report(0xffff0000);\n -# output: report(0x80010000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffff0000);\n -# output: report(0xfffeffff);\n -# output: report(0x00010000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000002);\n -# output: report(0xfffffffd);\n -# output: report(0xfffffffa);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffff8000);\n -# output: report(0x00010000);\n -# output: report(0x80000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffff7fff);\n -# output: report(0x00010000);\n -# output: report(0x7fff0000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x80000000);\n -# output: report(0x00000001);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00008000);\n -# output: report(0x00010000);\n -# output: report(0x80000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000002);\n -# output: report(0xfffffffd);\n -# output: report(0xfffffffa);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0xffff7fff);\n -# output: report(0xffff0000);\n -# output: report(0x80010000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - STANDARD_TEST_ENVIRONMENT - - .section .exception_vectors - - /* Range exception. */ - .org 0xb00 - - /* The handling is a bit dubious at present. We just patch the - instruction with l.nop and restart. This will go wrong in branch - delay slots, but we are not testing that here. */ - l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE - PUSH r2 - PUSH r3 - /* Save the address of the instruction that caused the problem. */ - MOVE_FROM_SPR r2, SPR_EPCR_BASE - LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */ - l.sw 0(r2), r3 - POP r3 - POP r2 - l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE - l.rfe - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test l.mul */ - - /* Multiply two small positive numbers. This should set no flags. - */ - TEST_INST_I32_I32 l.mul, 0x00000002, 0x00000003 - - /* Multiply two quite large positive numbers. This should set no - flags */ - TEST_INST_I32_I32 l.mul, 0x00008001, 0x0000fffe - - /* Multiply two slightly too large positive numbers. This should - set the overflow, but not the carry flag . */ - TEST_INST_I32_I32 l.mul, 0x00008000, 0x00010000 - - /* Multiply two large positive numbers. This should set the - overflow flags (even though the result is not a negative - number. */ - TEST_INST_I32_I32 l.mul, 0x00010000, 0x00010000 - - /* Multiply two small negative numbers. This will set no flags. */ - TEST_INST_I32_I32 l.mul, 0xfffffffe, 0xfffffffd - - /* Multiply two quite large negative numbers. This will no flags. */ - TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0002 - - /* Multiply two slightly too large negative numbers. This should - set the overflow flag. */ - TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0000 - - /* Multiply two large negative numbers. This should set the - both the carry and overflow flags (even though the result is a - positive number. */ - TEST_INST_I32_I32 l.mul, 0xffff0000, 0xfffeffff - - /* Multiply one small negative number and one small positive - number. This will set the no flags. */ - TEST_INST_I32_I32 l.mul, 0x00000002, 0xfffffffd - - /* Multiply one quite large negative number and one quite large - positive number. This will set no flags. */ - TEST_INST_I32_I32 l.mul, 0xffff8000, 0x00010000 - - /* Multiply one slightly too large negative number and one slightly - too large positive number. This should set the overflow flag. */ - TEST_INST_I32_I32 l.mul, 0xffff7fff, 0x00010000 - - /* Multiply the largest negative number by positive unity. This - should set neither carry, nor overflow flag. */ - TEST_INST_I32_I32 l.mul, 0x80000000, 0x00000001 - - /* Check that range exceptions are triggered. */ - - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Check that an overflow alone causes a RANGE Exception. */ - TEST_INST_I32_I32 l.mul, 0x00008000, 0x00010000 - - /* Check multiply of a negative and positive does not cause a RANGE - Exception. */ - TEST_INST_I32_I32 l.mul, 0x00000002, 0xfffffffd - - /* Check that negative overflow causes a RANGE exception. */ - TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0000 - - CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - - /* Test l.muli */ - - /* Multiply two small positive numbers. This should set no flags. */ - TEST_INST_I32_I16 l.muli, 0x00000002, 0x0003 - - /* Multiply two quite large positive numbers. This should set no - flags */ - TEST_INST_I32_I16 l.muli, 0x00010002, 0x7fff - - /* Multiply two slightly too large positive numbers. This should - set the overflow, but not the carry flag. */ - TEST_INST_I32_I16 l.muli, 0x00020000, 0x4000 - - /* Multiply two large positive numbers. This should set the - overflow flag, even though the result is not a negative number. */ - TEST_INST_I32_I16 l.muli, 0x00040000, 0x4000 - - /* Multiply two small negative numbers. This should set no flags. */ - TEST_INST_I32_I16 l.muli, 0xfffffffe, 0xfffd - - /* Multiply two quite large negative numbers. This will set no - flags. */ - TEST_INST_I32_I16 l.muli, 0xfffefffe, 0x8001 - - /* Multiply two slightly too large negative numbers. This should - set the overflow flag. */ - TEST_INST_I32_I16 l.muli, 0xfffe0000, 0xbfff - - /* Multiply two large negative numbers. This should set the - overflow flag, even though the result is a positive number. */ - TEST_INST_I32_I16 l.muli, 0xfffdfffe, 0x8000 - - /* Multiply one small negative number and one small positive - number. This will set no flags. */ - TEST_INST_I32_I16 l.muli, 0x00000002, 0xfffd - - /* Multiply one quite large negative number and one quite large - positive number. This will set no flags. */ - TEST_INST_I32_I16 l.muli, 0x00010000, 0x8000 - - /* Multiply one slightly too large negative number and one slightly - too large positive number. This will set the overflow flag. */ - TEST_INST_I32_I16 l.muli, 0xfffdfffc, 0x4000 - - /* Multiply the largest negative number by positive unity. Should - set neither carry, nor overflow flag. */ - TEST_INST_I32_I16 l.muli, 0x80000000, 0x0001 - - /* Check that range exceptions are triggered. */ - - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Check that an overflow alone causes a RANGE Exception. */ - TEST_INST_I32_I16 l.muli, 0x00020000, 0x4000 - - /* Check that two negatives will not cause a RANGE Exception. */ - TEST_INST_I32_I16 l.muli, 0xfffffffe, 0xfffd - - /* Check that multiply of larget negative and positive numbers causes - a RANGE exception and overflow. */ - TEST_INST_I32_I16 l.muli, 0xfffdfffe, 0x8000 - - CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Test l.mulu */ - - /* Multiply two small positive numbers. This should set no flags. */ - TEST_INST_I32_I32 l.mulu, 0x00000002, 0x00000003 - - /* Multiply two quite large positive numbers. This should set no - flags. */ - TEST_INST_I32_I32 l.mulu, 0x00008001, 0x0000fffe - - /* Multiply two slightly too large positive numbers. This will set - no flags. */ - TEST_INST_I32_I32 l.mulu, 0x00008000, 0x00010000 - - /* Multiply two large positive numbers. This will set the overflow - flag. */ - TEST_INST_I32_I32 l.mulu, 0x00010000, 0x00010000 - - /* Multiply two small negative numbers. This will set the - carry flag, but not the overflow flag. */ - TEST_INST_I32_I32 l.mulu, 0xfffffffe, 0xfffffffd - - /* Multiply two quite large negative numbers. This will set the - carry flag, but not the overflow flag. */ - TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0002 - - /* Multiply two slightly too large negative numbers. This will set - the carry flag, and not the overflow flag */ - TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0000 - - /* Multiply two large negative numbers. This will set the both the - carry flag (even though the result is a positive number.) */ - TEST_INST_I32_I32 l.mulu, 0xffff0000, 0xfffeffff - - /* Multiply one small negative number and one small positive - number. This will set the carry flag, but not the overflow - flag. */ - TEST_INST_I32_I32 l.mulu, 0x00000002, 0xfffffffd - - /* Multiply one quite large negative number and one quite large - positive number. This will set the carry flag, but not the - overflow flag. */ - TEST_INST_I32_I32 l.mulu, 0xffff8000, 0x00010000 - - /* Multiply one slightly too large negative number and one slightly - too large positive number. This will set the carry flag, but - not the overflow flag. */ - TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0x00010000 - - /* Multiply the largest negative number by positive unity. Should - set neither carry, nor overflow flag. */ - TEST_INST_I32_I32 l.mulu, 0x80000000, 0x00000001 - - /* Check that range exceptions are never triggered. */ - - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Check that what would cause an overflow alone in 2's complement - does not cause a RANGE Exception. */ - TEST_INST_I32_I32 l.mulu, 0x00008000, 0x00010000 - - /* Check that a carry causes a RANGE Exception. */ - TEST_INST_I32_I32 l.mulu, 0x00000002, 0xfffffffd - - /* Check that what would cause an overflow and carry in 2's - complement causes a RANGE Exception. */ - TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0000 - - CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/or.S b/sim/testsuite/sim/or1k/or.S deleted file mode 100644 index b20bec8..0000000 --- a/sim/testsuite/sim/or1k/or.S +++ /dev/null @@ -1,199 +0,0 @@ -/* Tests instructions l.or, l.ori. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0xffffffff);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0xaaaaaaaa);\n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x55555555);\n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x55555555);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0xb38f0f83);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0xc4c70f07);\n -# output: report(0xccf7ff7f);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x38f0f83b);\n -# output: report(0xbbffffbb);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0x0000ffff);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x0000aaaa);\n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x00005555);\n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x00005555);\n -# output: report(0xaaaaffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000f83);\n -# output: report(0x4c70ffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000f07);\n -# output: report(0x4c70ff7f);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000f83b);\n -# output: report(0xb38fffbb);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - STANDARD_TEST_ENVIRONMENT - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Always set OVE. We should never trigger an exception, even if - this bit is set. */ - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Test the l.or instruction with a range of operands. */ - - TEST_INST_I32_I32 l.or, 0x00000000, 0x00000000 - TEST_INST_I32_I32 l.or, 0xffffffff, 0xffffffff - TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0x00000000 - TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0xaaaaaaaa - TEST_INST_I32_I32 l.or, 0x55555555, 0x00000000 - TEST_INST_I32_I32 l.or, 0x55555555, 0x55555555 - TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0x55555555 - TEST_INST_I32_I32 l.or, 0x4c70f07c, 0xb38f0f83 - TEST_INST_I32_I32 l.or, 0x4c70f07c, 0xc4c70f07 - TEST_INST_I32_I32 l.or, 0xb38f0f83, 0x38f0f83b - - /* Test the l.ori instruction with a range of operands. */ - TEST_INST_I32_I16 l.ori, 0x00000000, 0x0000 - TEST_INST_I32_I16 l.ori, 0xffffffff, 0xffff - TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0x0000 - TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0xaaaa - TEST_INST_I32_I16 l.ori, 0x55555555, 0x0000 - TEST_INST_I32_I16 l.ori, 0x55555555, 0x5555 - TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0x5555 - TEST_INST_I32_I16 l.ori, 0x4c70f07c, 0x0f83 - TEST_INST_I32_I16 l.ori, 0x4c70f07c, 0x0f07 - TEST_INST_I32_I16 l.ori, 0xb38f0f83, 0xf83b - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/or1k-asm-test-env.h b/sim/testsuite/sim/or1k/or1k-asm-test-env.h deleted file mode 100644 index bbaeeeb..0000000 --- a/sim/testsuite/sim/or1k/or1k-asm-test-env.h +++ /dev/null @@ -1,59 +0,0 @@ -/* Testsuite macros for OpenRISC. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -#ifndef OR1K_ASM_TEST_ENV_H -#define OR1K_ASM_TEST_ENV_H - -#include "or1k-asm.h" -#include "or1k-asm-test.h" - - .macro STANDARD_TEST_HEADER - /* Without the "a" (allocatable) flag, this section gets some - default flags and is discarded by objcopy when flattening to - the binary file. */ - .section .exception_vectors, "ax" - .org 0x100 - .global _start -_start: - /* Clear R0 on start-up. There is no guarantee that R0 is hardwired - to zero and indeed it is not when simulating. */ - CLEAR_REG r0 - OR1K_DELAYED_NOP(l.j test_startup) - .section .text -test_startup: - .endm - - .macro STANDARD_TEST_BODY - LOAD_IMMEDIATE STACK_POINTER_R1, stack_begin - CLEAR_BSS r3, r4 - CALL r3, start_tests - EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_SUCCESS - .section .stack - .space 4096 /* We need more than EXCEPTION_STACK_SKIP_SIZE bytes. */ -stack_begin: - .endm - - .macro STANDARD_TEST_ENVIRONMENT - /* One of the test cases needs to do some tests before setting up - the stack and so on. That's the reason this macro is split into - 2 parts allowing the caller to inject code between the 2 - initialisation phases. */ - STANDARD_TEST_HEADER - STANDARD_TEST_BODY - .endm - -#endif /* OR1K_ASM_TEST_ENV_H */ diff --git a/sim/testsuite/sim/or1k/or1k-asm-test-helpers.h b/sim/testsuite/sim/or1k/or1k-asm-test-helpers.h deleted file mode 100644 index 699479c..0000000 --- a/sim/testsuite/sim/or1k/or1k-asm-test-helpers.h +++ /dev/null @@ -1,121 +0,0 @@ -/* Testsuite helpers for OpenRISC. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -#ifndef OR1K_ASM_TEST_HELPERS_H -#define OR1K_ASM_TEST_HELPERS_H - -#include "spr-defs.h" -#include "or1k-asm-test-env.h" - - /* During exception handling the instruction under test is - overwritten with a nop. Here we check if that is the case and - report. */ - - .macro REPORT_EXCEPTION instruction_addr - PUSH r2 - PUSH r3 - LOAD_IMMEDIATE r3, \instruction_addr - l.lws r2, 0(r3) - LOAD_IMMEDIATE r3, 0x15000000 /* l.nop */ - l.sfeq r2, r3 - OR1K_DELAYED_NOP (l.bnf 1f) - REPORT_IMMEDIATE_TO_CONSOLE 0x00000001 - OR1K_DELAYED_NOP (l.j 2f) -1: - REPORT_IMMEDIATE_TO_CONSOLE 0x00000000 -2: - POP r3 - POP r2 - .endm - - /* Test that will set and clear sr flags, run instruction report - the result and whether or not there was an exception. - - Arguments: - flags_to_set - sr flags to set - flags_to_clear - sr flags to clear - opcode - the instruction to execute - op1 - first argument to the instruction - op2 - second argument to the function - - Reports: - report(0x00000001);\n op1 - report(0x00000002);\n op1 - report(0x00000003);\n result - report(0x00000000);\n 1 if carry - report(0x00000000);\n 1 if overflow - report(0x00000000);\n 1 if exception - \n */ - - .macro TEST_INST_FF_I32_I32 flags_to_set, flags_to_clear, opcode, op1, op2 - LOAD_IMMEDIATE r5, \op1 - LOAD_IMMEDIATE r6, \op2 - REPORT_REG_TO_CONSOLE r5 - REPORT_REG_TO_CONSOLE r6 - /* Clear the last exception address. */ - MOVE_TO_SPR SPR_EPCR_BASE, ZERO_R0 - SET_SPR_SR_FLAGS \flags_to_set , r2, r3 - CLEAR_SPR_SR_FLAGS \flags_to_clear, r2, r3 -\@1$: \opcode r4, r5, r6 - MOVE_FROM_SPR r2, SPR_SR /* Save the flags. */ - REPORT_REG_TO_CONSOLE r4 - - REPORT_BIT_TO_CONSOLE r2, SPR_SR_CY - REPORT_BIT_TO_CONSOLE r2, SPR_SR_OV - REPORT_EXCEPTION \@1$ - PRINT_NEWLINE_TO_CONSOLE - .endm - - .macro TEST_INST_FF_I32_I16 flags_to_set, flags_to_clear, opcode, op1, op2 - LOAD_IMMEDIATE r5, \op1 - REPORT_REG_TO_CONSOLE r5 - REPORT_IMMEDIATE_TO_CONSOLE \op2 - SET_SPR_SR_FLAGS \flags_to_set , r2, r3 - CLEAR_SPR_SR_FLAGS \flags_to_clear, r2, r3 - /* Clear the last exception address. */ - MOVE_TO_SPR SPR_EPCR_BASE, ZERO_R0 -\@1$: \opcode r4, r5, \op2 - MOVE_FROM_SPR r2, SPR_SR /* Save the flags. */ - REPORT_REG_TO_CONSOLE r4 - REPORT_BIT_TO_CONSOLE r2, SPR_SR_CY - REPORT_BIT_TO_CONSOLE r2, SPR_SR_OV - REPORT_EXCEPTION \@1$ - PRINT_NEWLINE_TO_CONSOLE - .endm - - .macro TEST_INST_I32_I32 opcode, op1, op2 - TEST_INST_FF_I32_I32 0, 0, \opcode, \op1, \op2 - .endm - - .macro TEST_INST_I32_I16 opcode, op1, op2 - TEST_INST_FF_I32_I16 0, 0, \opcode, \op1, \op2 - .endm - - .macro CHECK_CARRY_AND_OVERFLOW_NOT_SET overwritten_reg1, overwritten_reg2 - MOVE_FROM_SPR \overwritten_reg1, SPR_SR - - LOAD_IMMEDIATE \overwritten_reg2, SPR_SR_CY + SPR_SR_OV - l.and \overwritten_reg1, \overwritten_reg1, \overwritten_reg2 - l.sfne \overwritten_reg1, ZERO_R0 - - OR1K_DELAYED_NOP (l.bnf \@2$) - - EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR -\@2$: - .endm - -#endif /* OR1K_ASM_TEST_HELPERS_H */ diff --git a/sim/testsuite/sim/or1k/or1k-asm-test.h b/sim/testsuite/sim/or1k/or1k-asm-test.h deleted file mode 100644 index 3525673..0000000 --- a/sim/testsuite/sim/or1k/or1k-asm-test.h +++ /dev/null @@ -1,226 +0,0 @@ -/* Testsuite architecture macros for OpenRISC. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -#ifndef OR1K_ASM_TEST_H -#define OR1K_ASM_TEST_H - -#include "spr-defs.h" - -/* Register definitions */ - -/* The "jump and link" instructions store the return address in R9. */ -#define LINK_REGISTER_R9 r9 - -/* These register definitions match the ABI. */ -#define ZERO_R0 r0 -#define STACK_POINTER_R1 r1 -#define FRAME_POINTER_R2 r2 -#define RETURN_VALUE_R11 r11 - - /* Load/move/clear helpers */ - - .macro LOAD_IMMEDIATE reg, val - l.movhi \reg, hi ( \val ) - l.ori \reg, \reg, lo ( \val ) - .endm - - .macro MOVE_REG dest_reg, src_reg - .ifnes "\dest_reg","\src_reg" - l.ori \dest_reg, \src_reg, 0 - .endif - .endm - - .macro CLEAR_REG reg - l.movhi \reg, 0 - .endm - - .macro MOVE_FROM_SPR reg, spr_reg - l.mfspr \reg, ZERO_R0, \spr_reg - .endm - - .macro MOVE_TO_SPR spr_reg, reg - l.mtspr ZERO_R0, \reg, \spr_reg - .endm - - .macro SET_SPR_SR_FLAGS flag_mask, scratch_reg_1, scratch_reg_2 - /* We cannot use PUSH and POP here because some flags like Carry - would get overwritten. */ - - /* We could optimise this routine, as instruction l.mtspr already - does a logical OR. */ - MOVE_FROM_SPR \scratch_reg_2, SPR_SR - LOAD_IMMEDIATE \scratch_reg_1, \flag_mask - l.or \scratch_reg_2, \scratch_reg_2, \scratch_reg_1 - MOVE_TO_SPR SPR_SR, \scratch_reg_2 - .endm - - .macro CLEAR_SPR_SR_FLAGS flag_mask, scratch_reg_1, scratch_reg_2 - /* We cannot use PUSH and POP here because some flags like Carry - would get overwritten. */ - - MOVE_FROM_SPR \scratch_reg_2, SPR_SR - LOAD_IMMEDIATE \scratch_reg_1, ~\flag_mask - l.and \scratch_reg_2, \scratch_reg_2, \scratch_reg_1 - MOVE_TO_SPR SPR_SR, \scratch_reg_2 - - .endm - - /* Stack helpers */ - -/* This value is defined in the OpenRISC 1000 specification. */ -#define EXCEPTION_STACK_SKIP_SIZE 128 - - /* WARNING: Functions without prolog cannot use these PUSH or POP - macros. - - PERFORMANCE WARNING: These PUSH/POP macros are convenient, but - can lead to slow code. If you need to PUSH or POP several - registers, it's faster to use non-zero offsets when - loading/storing and then increment/decrement the stack pointer - just once. */ - - .macro PUSH reg - l.addi STACK_POINTER_R1, STACK_POINTER_R1, -4 - l.sw 0(STACK_POINTER_R1), \reg - .endm - - /* WARNING: see the warnings for PUSH. */ - .macro POP reg - l.lwz \reg, 0(STACK_POINTER_R1) - l.addi STACK_POINTER_R1, STACK_POINTER_R1, 4 - .endm - -/* l.nop definitions for simulation control and console output. */ - -/* Register definitions for the simulation l.nop codes. */ -#define NOP_REPORT_R3 r3 -#define NOP_EXIT_R3 r3 - -/* SEC = Simulation Exit Code */ -#define SEC_SUCCESS 0 -#define SEC_RETURNED_FROM_MAIN 1 -#define SEC_GENERIC_ERROR 2 - - /* When running under the simulator, this l.nop code terminates the - simulation. */ - .macro EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE immediate_value - LOAD_IMMEDIATE NOP_EXIT_R3, \immediate_value - l.nop 1 - .endm - - .macro EXIT_SIMULATION_WITH_REG_EXIT_CODE reg - MOVE_REG NOP_EXIT_R3, \reg - l.nop 1 - .endm - - /* When running under the simulator, this l.nop code prints the - value of R3 to the console. */ - .macro REPORT_TO_CONSOLE - l.nop 2 - .endm - - /* NOTE: The stack must be set up, as this macro uses PUSH and POP. */ - .macro REPORT_REG_TO_CONSOLE reg - .ifeqs "\reg","r3" - /* Nothing more to do here, R3 is the register that gets printed. */ - REPORT_TO_CONSOLE - .else - PUSH NOP_REPORT_R3 - MOVE_REG NOP_REPORT_R3, \reg - REPORT_TO_CONSOLE - POP NOP_REPORT_R3 - .endif - .endm - - /* NOTE: The stack must be set up, as this macro uses PUSH and POP. */ - .macro REPORT_IMMEDIATE_TO_CONSOLE val - PUSH NOP_REPORT_R3 - LOAD_IMMEDIATE NOP_REPORT_R3, \val - REPORT_TO_CONSOLE - POP NOP_REPORT_R3 - .endm - - .macro PRINT_NEWLINE_TO_CONSOLE - PUSH r3 - LOAD_IMMEDIATE r3, 0x0A - l.nop 4 - POP r3 - .endm - - /* If SR[F] is set, writes 0x00000001 to the console, otherwise it - writes 0x00000000. */ - .macro REPORT_SRF_TO_CONSOLE - OR1K_DELAYED_NOP (l.bnf \@1$) - REPORT_IMMEDIATE_TO_CONSOLE 0x00000001 - OR1K_DELAYED_NOP (l.j \@2$) -\@1$: - REPORT_IMMEDIATE_TO_CONSOLE 0x00000000 -\@2$: - .endm - - /* If the given register is 0, writes 0x00000000 to the console, - otherwise it writes 0x00000001. */ - .macro REPORT_BOOL_TO_CONSOLE reg - l.sfne \reg, ZERO_R0 - REPORT_SRF_TO_CONSOLE - .endm - - /* Writes to the console the value of the given register bit. */ - .macro REPORT_BIT_TO_CONSOLE reg, single_bit_mask - PUSH r2 - PUSH r3 - PUSH r4 - MOVE_REG r2, \reg - LOAD_IMMEDIATE r4, \single_bit_mask - l.and r3, r2, r4 - REPORT_BOOL_TO_CONSOLE r3 - POP r4 - POP r3 - POP r2 - .endm - - /* Jump helpers */ - - .macro CALL overwritten_reg, subroutine_name - LOAD_IMMEDIATE \overwritten_reg, \subroutine_name - OR1K_DELAYED_NOP (l.jalr \overwritten_reg) - .endm - - .macro RETURN_TO_LINK_REGISTER_R9 - OR1K_DELAYED_NOP (l.jr LINK_REGISTER_R9) - .endm - - /* Clear the BSS section on start-up */ - - .macro CLEAR_BSS overwritten_reg1, overwritten_reg2 - LOAD_IMMEDIATE \overwritten_reg1, _bss_begin - LOAD_IMMEDIATE \overwritten_reg2, _bss_end - l.sfgeu \overwritten_reg1, \overwritten_reg2 - OR1K_DELAYED_NOP (l.bf bss_is_empty) -bss_clear_loop: - /* Possible optimisation to investigate: - move "l.sw 0(\overwritten_reg1), r0" to the jump delay slot as - "l.sw -4(\overwritten_reg1), r0" or similar. But keep in mind that - there are plans to remove the jump delay slot. */ - l.sw 0(\overwritten_reg1), r0 - l.addi \overwritten_reg1, \overwritten_reg1, 4 - l.sfgtu \overwritten_reg2, \overwritten_reg1 - OR1K_DELAYED_NOP (l.bf bss_clear_loop) -bss_is_empty: - .endm - -#endif /* OR1K_ASM_TEST_H */ diff --git a/sim/testsuite/sim/or1k/or1k-asm.h b/sim/testsuite/sim/or1k/or1k-asm.h deleted file mode 100644 index 37f4461..0000000 --- a/sim/testsuite/sim/or1k/or1k-asm.h +++ /dev/null @@ -1,37 +0,0 @@ -/* Testsuite assembly helpers for OpenRISC. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -#ifndef OR1K_ASM_H -#define OR1K_ASM_H - -#define OR1K_INST(...) __VA_ARGS__ - -#if defined(__OR1K_NODELAY__) -#define OR1K_DELAYED(a, b) a; b -#define OR1K_DELAYED_NOP(a) a -.nodelay -#elif defined(__OR1K_DELAY__) -#define OR1K_DELAYED(a, b) b; a -#define OR1K_DELAYED_NOP(a) a; l.nop -#elif defined(__OR1K_DELAY_COMPAT__) -#define OR1K_DELAYED(a, b) a; b; l.nop -#define OR1K_DELAYED_NOP(a) a; l.nop -#else -#error One of __OR1K_NODELAY__, __OR1K_DELAY__, or __OR1K_DELAY_COMPAT__ must be defined -#endif - -#endif /* OR1K_ASM_H */ diff --git a/sim/testsuite/sim/or1k/or1k-test.ld b/sim/testsuite/sim/or1k/or1k-test.ld deleted file mode 100644 index fe6fd73..0000000 --- a/sim/testsuite/sim/or1k/or1k-test.ld +++ /dev/null @@ -1,75 +0,0 @@ -/* Test linker script for OpenRISC. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -MEMORY -{ - /* The exception vectors actually start at 0x100, but if you specify - that address here, the "--output-target binary" step will start from - address 0 with the contents meant for address 0x100. */ - exception_vectors : ORIGIN = 0 , LENGTH = 8K - ram : ORIGIN = 8K, LENGTH = 2M - 8K -} - -SECTIONS -{ - .exception_vectors : - { - KEEP(*(.exception_vectors)) - } > exception_vectors - - .text : - { - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - } > ram - - .data : - { - *(.data) - *(.data.*) - } > ram - - .bss : - { - *(.bss) - *(.bss.*) - - /* WARNING about section size alignment: - The start-up assembly code can only clear BSS section sizes - which are aligned to 4 bytes. However, the size of the BSS - section may not be aligned, therefore up to 3 bytes more could - be zeroed on start-up. This is normally not an issue, as the - start of the next section is usually aligned too, so those extra - bytes should be just padding. I did try the following trick to - align the BSS section size, to no avail: - - . = ALIGN(., 4); - */ - } > ram - - _bss_begin = ADDR(.bss); - _bss_end = _bss_begin + SIZEOF(.bss); - - .stack ALIGN(16) (NOLOAD): - { - *(.stack) - } > ram -} - -ENTRY(_start) /* Otherwise, --gc-sections would throw everything away. */ diff --git a/sim/testsuite/sim/or1k/ror.S b/sim/testsuite/sim/or1k/ror.S deleted file mode 100644 index ce47c12..0000000 --- a/sim/testsuite/sim/or1k/ror.S +++ /dev/null @@ -1,159 +0,0 @@ -/* Tests instructions l.ror and l.rori. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0xb38f0f83);\n -# output: report(0x00000000);\n -# output: report(0xb38f0f83);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000001);\n -# output: report(0xd9c787c1);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000004);\n -# output: report(0x3b38f0f8);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000010);\n -# output: report(0x0f83b38f);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000001f);\n -# output: report(0x671e1f07);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000021);\n -# output: report(0xd9c787c1);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00002224);\n -# output: report(0x3b38f0f8);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00f789f0);\n -# output: report(0x0f83b38f);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0xffffffff);\n -# output: report(0x671e1f07);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000000);\n -# output: report(0xb38f0f83);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000001);\n -# output: report(0xd9c787c1);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000004);\n -# output: report(0x3b38f0f8);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000010);\n -# output: report(0x0f83b38f);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000001f);\n -# output: report(0x671e1f07);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000021);\n -# output: report(0xd9c787c1);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000024);\n -# output: report(0x3b38f0f8);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000030);\n -# output: report(0x0f83b38f);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000003f);\n -# output: report(0x671e1f07);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-env.h" - - .macro TEST_ROR op1, op2, res - /* Note that 'res' is not used here. We could stop using the - .TestResults file and use 'res' here instead. */ - LOAD_IMMEDIATE r5, \op1 - LOAD_IMMEDIATE r6, \op2 - REPORT_REG_TO_CONSOLE r5 - REPORT_REG_TO_CONSOLE r6 - l.ror r4, r5, r6 - REPORT_REG_TO_CONSOLE r4 - PRINT_NEWLINE_TO_CONSOLE - .endm - - .macro TEST_RORI op1, op2, res - /* Note that 'res' is not used here. We could stop using the - .TestResults file and use 'res' here instead. */ - LOAD_IMMEDIATE r5, \op1 - REPORT_REG_TO_CONSOLE r5 - REPORT_IMMEDIATE_TO_CONSOLE \op2 - l.rori r4, r5, \op2 - REPORT_REG_TO_CONSOLE r4 - PRINT_NEWLINE_TO_CONSOLE - .endm - - STANDARD_TEST_ENVIRONMENT - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test the l.ror instruction. */ - - /* Rotate by zero */ - TEST_ROR 0xb38f0f83, 0x00000000, 0xb38f0f83 - - /* Rotate by amounts in the 1 - 31 range. */ - TEST_ROR 0xb38f0f83, 0x00000001, 0xd9c787c1 - TEST_ROR 0xb38f0f83, 0x00000004, 0x3b38f0f8 - TEST_ROR 0xb38f0f83, 0x00000010, 0x0f83b38f - TEST_ROR 0xb38f0f83, 0x0000001f, 0x671e1f07 - - /* Rotate by larger amounts - should be masked. */ - TEST_ROR 0xb38f0f83, 0x00000021, 0xd9c787c1 - TEST_ROR 0xb38f0f83, 0x00002224, 0x3b38f0f8 - TEST_ROR 0xb38f0f83, 0x00f789f0, 0x0f83b38f - TEST_ROR 0xb38f0f83, 0xffffffff, 0x671e1f07 - - /* Test the l.rori instruction. */ - - /* Rotate by zero */ - TEST_RORI 0xb38f0f83, 0x00000000, 0xb38f0f83 - - /* Rotate by amounts in the 1 - 31 range. */ - TEST_RORI 0xb38f0f83, 0x01, 0xd9c787c1 - TEST_RORI 0xb38f0f83, 0x04, 0x3b38f0f8 - TEST_RORI 0xb38f0f83, 0x10, 0x0f83b38f - TEST_RORI 0xb38f0f83, 0x1f, 0x671e1f07 - - /* Rotate by larger amounts (32 - 63) - should be masked. */ - TEST_RORI 0xb38f0f83, 0x21, 0xd9c787c1 - TEST_RORI 0xb38f0f83, 0x24, 0x3b38f0f8 - TEST_RORI 0xb38f0f83, 0x30, 0x0f83b38f - TEST_RORI 0xb38f0f83, 0x3f, 0x671e1f07 - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/shift.S b/sim/testsuite/sim/or1k/shift.S deleted file mode 100644 index a98da29..0000000 --- a/sim/testsuite/sim/or1k/shift.S +++ /dev/null @@ -1,541 +0,0 @@ -/* Tests the shift instructions. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0xb38f0f83);\n -# output: report(0x00000000);\n -# output: report(0xb38f0f83);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000001);\n -# output: report(0x671e1f06);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000004);\n -# output: report(0x38f0f830);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000010);\n -# output: report(0x0f830000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000001f);\n -# output: report(0x80000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000021);\n -# output: report(0x671e1f06);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00002224);\n -# output: report(0x38f0f830);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00f789f0);\n -# output: report(0x0f830000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0xffffffff);\n -# output: report(0x80000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000000);\n -# output: report(0xb38f0f83);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000001);\n -# output: report(0x671e1f06);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000004);\n -# output: report(0x38f0f830);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000010);\n -# output: report(0x0f830000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000001f);\n -# output: report(0x80000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000021);\n -# output: report(0x671e1f06);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000024);\n -# output: report(0x38f0f830);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000030);\n -# output: report(0x0f830000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000003f);\n -# output: report(0x80000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000000);\n -# output: report(0xb38f0f83);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000001);\n -# output: report(0xd9c787c1);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000004);\n -# output: report(0xfb38f0f8);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000010);\n -# output: report(0xffffb38f);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000001f);\n -# output: report(0xffffffff);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000001);\n -# output: report(0x2638783e);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000004);\n -# output: report(0x04c70f07);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000010);\n -# output: report(0x00004c70);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x0000001f);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000021);\n -# output: report(0xd9c787c1);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00002224);\n -# output: report(0xfb38f0f8);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00f789f0);\n -# output: report(0xffffb38f);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0xffffffff);\n -# output: report(0xffffffff);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000021);\n -# output: report(0x2638783e);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00002224);\n -# output: report(0x04c70f07);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00f789f0);\n -# output: report(0x00004c70);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000000);\n -# output: report(0xb38f0f83);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000001);\n -# output: report(0xd9c787c1);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000004);\n -# output: report(0xfb38f0f8);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000010);\n -# output: report(0xffffb38f);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000001f);\n -# output: report(0xffffffff);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000001);\n -# output: report(0x2638783e);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000004);\n -# output: report(0x04c70f07);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000010);\n -# output: report(0x00004c70);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x0000001f);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000021);\n -# output: report(0xd9c787c1);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000024);\n -# output: report(0xfb38f0f8);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000030);\n -# output: report(0xffffb38f);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000003f);\n -# output: report(0xffffffff);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000021);\n -# output: report(0x2638783e);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000024);\n -# output: report(0x04c70f07);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000030);\n -# output: report(0x00004c70);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x0000003f);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000000);\n -# output: report(0xb38f0f83);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000001);\n -# output: report(0x59c787c1);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000004);\n -# output: report(0x0b38f0f8);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000010);\n -# output: report(0x0000b38f);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000001f);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000001);\n -# output: report(0x2638783e);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000004);\n -# output: report(0x04c70f07);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000010);\n -# output: report(0x00004c70);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x0000001f);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000021);\n -# output: report(0x59c787c1);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00002224);\n -# output: report(0x0b38f0f8);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00f789f0);\n -# output: report(0x0000b38f);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0xffffffff);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000021);\n -# output: report(0x2638783e);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00002224);\n -# output: report(0x04c70f07);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00f789f0);\n -# output: report(0x00004c70);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000000);\n -# output: report(0xb38f0f83);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000001);\n -# output: report(0x59c787c1);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000004);\n -# output: report(0x0b38f0f8);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000010);\n -# output: report(0x0000b38f);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000001f);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000001);\n -# output: report(0x2638783e);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000004);\n -# output: report(0x04c70f07);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000010);\n -# output: report(0x00004c70);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x0000001f);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000021);\n -# output: report(0x59c787c1);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000024);\n -# output: report(0x0b38f0f8);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x00000030);\n -# output: report(0x0000b38f);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000003f);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000021);\n -# output: report(0x2638783e);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000024);\n -# output: report(0x04c70f07);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000030);\n -# output: report(0x00004c70);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x0000003f);\n -# output: report(0x00000000);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - .macro TEST_SHIFT opcode, op1, op2 - LOAD_IMMEDIATE r5, \op1 - LOAD_IMMEDIATE r6, \op2 - REPORT_REG_TO_CONSOLE r5 - REPORT_REG_TO_CONSOLE r6 - \opcode r4, r5, r6 - CHECK_CARRY_AND_OVERFLOW_NOT_SET r2, r3 - REPORT_REG_TO_CONSOLE r4 - PRINT_NEWLINE_TO_CONSOLE - .endm - - .macro TEST_SHIFT_I opcode, op1, op2 - LOAD_IMMEDIATE r5, \op1 - REPORT_REG_TO_CONSOLE r5 - REPORT_IMMEDIATE_TO_CONSOLE \op2 - \opcode r4, r5, \op2 - CHECK_CARRY_AND_OVERFLOW_NOT_SET r2, r3 - REPORT_REG_TO_CONSOLE r4 - PRINT_NEWLINE_TO_CONSOLE - .endm - - STANDARD_TEST_ENVIRONMENT - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Always set OVE. We should never trigger an exception, even if - this bit is set. */ - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Test l.sll */ - - /* Shift left by zero. */ - TEST_SHIFT l.sll, 0xb38f0f83, 0x00000000 - - /* Shift left by amounts in the 1-31 range. */ - TEST_SHIFT l.sll, 0xb38f0f83, 0x00000001 - TEST_SHIFT l.sll, 0xb38f0f83, 0x00000004 - TEST_SHIFT l.sll, 0xb38f0f83, 0x00000010 - TEST_SHIFT l.sll, 0xb38f0f83, 0x0000001f - - /* Shift left by larger amounts - should be masked. */ - TEST_SHIFT l.sll, 0xb38f0f83, 0x00000021 - TEST_SHIFT l.sll, 0xb38f0f83, 0x00002224 - TEST_SHIFT l.sll, 0xb38f0f83, 0x00f789f0 - TEST_SHIFT l.sll, 0xb38f0f83, 0xffffffff - - /* Test l.slli */ - - /* Shift left by zero. */ - TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0000 - - /* Shift left by amounts in the 1-31 range. */ - TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0001 - TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0004 - TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0010 - TEST_SHIFT_I l.slli, 0xb38f0f83, 0x001f - - /* Shift left by larger amounts - should be masked. */ - TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0021 - TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0024 - TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0030 - TEST_SHIFT_I l.slli, 0xb38f0f83, 0x003f - - /* Test l.sra */ - - /* Shift right by zero. */ - TEST_SHIFT l.sra, 0xb38f0f83, 0x00000000 - - /* Shift right by amounts in the 1-31 range. */ - TEST_SHIFT l.sra, 0xb38f0f83, 0x00000001 - TEST_SHIFT l.sra, 0xb38f0f83, 0x00000004 - TEST_SHIFT l.sra, 0xb38f0f83, 0x00000010 - TEST_SHIFT l.sra, 0xb38f0f83, 0x0000001f - - TEST_SHIFT l.sra, 0x4c70f07c, 0x00000001 - TEST_SHIFT l.sra, 0x4c70f07c, 0x00000004 - TEST_SHIFT l.sra, 0x4c70f07c, 0x00000010 - TEST_SHIFT l.sra, 0x4c70f07c, 0x0000001f - - /* Shift right by larger amounts - should be masked. */ - TEST_SHIFT l.sra, 0xb38f0f83, 0x00000021 - TEST_SHIFT l.sra, 0xb38f0f83, 0x00002224 - TEST_SHIFT l.sra, 0xb38f0f83, 0x00f789f0 - TEST_SHIFT l.sra, 0xb38f0f83, 0xffffffff - - TEST_SHIFT l.sra, 0x4c70f07c, 0x00000021 - TEST_SHIFT l.sra, 0x4c70f07c, 0x00002224 - TEST_SHIFT l.sra, 0x4c70f07c, 0x00f789f0 - TEST_SHIFT l.sra, 0x4c70f07c, 0xffffffff - - /* Test l.srai */ - - /* Shift right by zero. */ - TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0000 - - /* Shift right by amounts in the 1-31 range. */ - TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0001 - TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0004 - TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0010 - TEST_SHIFT_I l.srai, 0xb38f0f83, 0x001f - - TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0001 - TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0004 - TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0010 - TEST_SHIFT_I l.srai, 0x4c70f07c, 0x001f - - /* Shift right by larger amounts - should be masked. */ - TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0021 - TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0024 - TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0030 - TEST_SHIFT_I l.srai, 0xb38f0f83, 0x003f - - TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0021 - TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0024 - TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0030 - TEST_SHIFT_I l.srai, 0x4c70f07c, 0x003f - - /* Test l.srl */ - - /* Shift right by zero. */ - TEST_SHIFT l.srl, 0xb38f0f83, 0x00000000 - - /* Shift right by amounts in the 1-31 range. */ - TEST_SHIFT l.srl, 0xb38f0f83, 0x00000001 - TEST_SHIFT l.srl, 0xb38f0f83, 0x00000004 - TEST_SHIFT l.srl, 0xb38f0f83, 0x00000010 - TEST_SHIFT l.srl, 0xb38f0f83, 0x0000001f - - TEST_SHIFT l.srl, 0x4c70f07c, 0x00000001 - TEST_SHIFT l.srl, 0x4c70f07c, 0x00000004 - TEST_SHIFT l.srl, 0x4c70f07c, 0x00000010 - TEST_SHIFT l.srl, 0x4c70f07c, 0x0000001f - - /* Shift right by larger amounts - should be masked. */ - TEST_SHIFT l.srl, 0xb38f0f83, 0x00000021 - TEST_SHIFT l.srl, 0xb38f0f83, 0x00002224 - TEST_SHIFT l.srl, 0xb38f0f83, 0x00f789f0 - TEST_SHIFT l.srl, 0xb38f0f83, 0xffffffff - - TEST_SHIFT l.srl, 0x4c70f07c, 0x00000021 - TEST_SHIFT l.srl, 0x4c70f07c, 0x00002224 - TEST_SHIFT l.srl, 0x4c70f07c, 0x00f789f0 - TEST_SHIFT l.srl, 0x4c70f07c, 0xffffffff - - /* Test l.srli */ - - /* Shift right by zero. */ - TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0000 - - /* Shift right by amounts in the 1-31 range. */ - TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0001 - TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0004 - TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0010 - TEST_SHIFT_I l.srli, 0xb38f0f83, 0x001f - - TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0001 - TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0004 - TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0010 - TEST_SHIFT_I l.srli, 0x4c70f07c, 0x001f - - /* Shift right by larger amounts - should be masked. */ - TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0021 - TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0024 - TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0030 - TEST_SHIFT_I l.srli, 0xb38f0f83, 0x003f - - TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0021 - TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0024 - TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0030 - TEST_SHIFT_I l.srli, 0x4c70f07c, 0x003f - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/spr-defs.h b/sim/testsuite/sim/or1k/spr-defs.h deleted file mode 100644 index f0ec5e7..0000000 --- a/sim/testsuite/sim/or1k/spr-defs.h +++ /dev/null @@ -1,120 +0,0 @@ -/* Special Purpose Registers definitions - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -#ifndef SPR_DEFS_H -#define SPR_DEFS_H - -#define MAX_GRPS 32 -#define MAX_SPRS_PER_GRP_BITS 11 - -/* Base addresses for the groups */ -#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) -#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS) -#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS) -#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS) -#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS) -#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS) -#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS) -#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) -#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS) -#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS) -#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) -#define SPRGROUP_FP (11<< MAX_SPRS_PER_GRP_BITS) - -/* System control and status group */ -#define SPR_VR (SPRGROUP_SYS + 0) -#define SPR_UPR (SPRGROUP_SYS + 1) -#define SPR_CPUCFGR (SPRGROUP_SYS + 2) -#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) -#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) -#define SPR_DCCFGR (SPRGROUP_SYS + 5) -#define SPR_ICCFGR (SPRGROUP_SYS + 6) -#define SPR_DCFGR (SPRGROUP_SYS + 7) -#define SPR_PCCFGR (SPRGROUP_SYS + 8) -#define SPR_NPC (SPRGROUP_SYS + 16) -#define SPR_SR (SPRGROUP_SYS + 17) -#define SPR_PPC (SPRGROUP_SYS + 18) -#define SPR_FPCSR (SPRGROUP_SYS + 20) -#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) -#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) -#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) -#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) -#define SPR_ESR_BASE (SPRGROUP_SYS + 64) -#define SPR_ESR_LAST (SPRGROUP_SYS + 79) -#define SPR_GPR_BASE (SPRGROUP_SYS + 1024) - -/* Data MMU group */ -#define SPR_DMMUCR (SPRGROUP_DMMU + 0) -#define SPR_DMMUPR (SPRGROUP_DMMU + 1) -#define SPR_DTLBEIR (SPRGROUP_DMMU + 2) -#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) -#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) -#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) -#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) - -/* Instruction MMU group */ -#define SPR_IMMUCR (SPRGROUP_IMMU + 0) -#define SPR_ITLBEIR (SPRGROUP_IMMU + 2) -#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) -#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) -#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) -#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) - -/* Data cache group */ -#define SPR_DCCR (SPRGROUP_DC + 0) -#define SPR_DCBPR (SPRGROUP_DC + 1) -#define SPR_DCBFR (SPRGROUP_DC + 2) -#define SPR_DCBIR (SPRGROUP_DC + 3) -#define SPR_DCBWR (SPRGROUP_DC + 4) -#define SPR_DCBLR (SPRGROUP_DC + 5) -#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) -#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) - -/* Instruction cache group */ -#define SPR_ICCR (SPRGROUP_IC + 0) -#define SPR_ICBPR (SPRGROUP_IC + 1) -#define SPR_ICBIR (SPRGROUP_IC + 2) -#define SPR_ICBLR (SPRGROUP_IC + 3) -#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) -#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) - -/* MAC group */ -#define SPR_MACLO (SPRGROUP_MAC + 1) -#define SPR_MACHI (SPRGROUP_MAC + 2) - -/* Bit definitions for the Supervision Register. */ -#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ -#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ -#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ -#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ -#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ -#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ -#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ -#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ -#define SPR_SR_CE 0x00000100 /* CID Enable */ -#define SPR_SR_F 0x00000200 /* Condition Flag */ -#define SPR_SR_CY 0x00000400 /* Carry flag */ -#define SPR_SR_OV 0x00000800 /* Overflow flag */ -#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ -#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ -#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */ -#define SPR_SR_FO 0x00008000 /* Fixed one */ -#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */ -#define SPR_SR_RES 0x0ffe0000 /* Reserved */ -#define SPR_SR_CID 0xf0000000 /* Context ID */ - -#endif /* SPR_DEFS_H */ diff --git a/sim/testsuite/sim/or1k/sub.S b/sim/testsuite/sim/or1k/sub.S deleted file mode 100644 index 3886145..0000000 --- a/sim/testsuite/sim/or1k/sub.S +++ /dev/null @@ -1,215 +0,0 @@ -/* Tests instruction l.sub. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x00000003);\n -# output: report(0x00000002);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000001);\n -# output: report(0x00000002);\n -# output: report(0xffffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000003);\n -# output: report(0x00000002);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xfffffffd);\n -# output: report(0xfffffffe);\n -# output: report(0xffffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0xfffffffe);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x7fffffff);\n -# output: report(0x3fffffff);\n -# output: report(0x40000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x40000000);\n -# output: report(0x40000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x3fffffff);\n -# output: report(0x40000000);\n -# output: report(0xffffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x40000000);\n -# output: report(0x3fffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x80000000);\n -# output: report(0x7fffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x7fffffff);\n -# output: report(0x80000000);\n -# output: report(0xffffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x80000000);\n -# output: report(0x7fffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: report(0x3fffffff);\n -# output: report(0x40000000);\n -# output: report(0xffffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x7fffffff);\n -# output: report(0x80000000);\n -# output: report(0xffffffff);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: report(0x00000001);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - STANDARD_TEST_ENVIRONMENT - - .section .exception_vectors - - /* Range exception. */ - .org 0xb00 - - /* The handling is a bit dubious at present. We just patch the - instruction with l.nop and restart. This will go wrong in branch - delay slots. But we don't have those in this test. */ - l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE - PUSH r2 - PUSH r3 - /* Save the address of the instruction that caused the problem. */ - MOVE_FROM_SPR r2, SPR_EPCR_BASE - LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */ - l.sw 0(r2), r3 - POP r3 - POP r2 - l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE - l.rfe - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Test l.sub */ - - /* Subtract two small positive numbers. Sets the carry, but never - the overflow if the result is negative. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x00000003, \ - 0x00000002 - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x00000001, \ - 0x00000002 - - /* Check carry in is ignored. */ - TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.sub, 0x00000003, 0x00000002 - - /* Subtract two small negative numbers. Sets the carry flag if - the result is negative, but never the overflow flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0xfffffffd, \ - 0xfffffffe - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0xffffffff, \ - 0xfffffffe - - /* Subtract two quite large positive numbers. Should set neither - the overflow nor the carry flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, \ - 0x3fffffff - - /* Subtract two quite large negative numbers. Should set neither - the overflow nor the carry flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x40000000, \ - 0x40000000 - - /* Subtract two large positive numbers with a negative result. - Should set the carry, but not the overflow flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x3fffffff, \ - 0x40000000 - - /* Subtract two large negative numbers with a positive result. - Should set neither the carry nor the overflow flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x40000000, \ - 0x3fffffff - - /* Subtract a large positive from a large negative number. Should - set overflow but not the carry flag. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x80000000, \ - 0x7fffffff - - /* Subtract a large negative from a large positive number. Should - set both the overflow and carry flags. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, \ - 0x80000000 - - /* Check that range exceptions are triggered. */ - - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Check that an overflow alone causes a RANGE Exception. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x80000000, \ - 0x7fffffff - - /* Check that a carry alone does not cause a RANGE Exception. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x3fffffff, \ - 0x40000000 - - /* Check that carry and overflow together cause an exception. */ - TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, \ - 0x80000000 - - CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/or1k/xor.S b/sim/testsuite/sim/or1k/xor.S deleted file mode 100644 index 2dc0ad8..0000000 --- a/sim/testsuite/sim/or1k/xor.S +++ /dev/null @@ -1,200 +0,0 @@ -/* Tests instructions l.xor, l.xori. - - Copyright (C) 2017-2021 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -# mach: or1k -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x55555555);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0xb38f0f83);\n -# output: report(0xffffffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0xc4c70f07);\n -# output: report(0x88b7ff7b);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x38f0f83b);\n -# output: report(0x8b7ff7b8);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xffffffff);\n -# output: report(0x0000ffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0xaaaaaaaa);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x0000aaaa);\n -# output: report(0x55550000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x55555555);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x55555555);\n -# output: report(0x00005555);\n -# output: report(0x55550000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xaaaaaaaa);\n -# output: report(0x00005555);\n -# output: report(0xaaaaffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000f83);\n -# output: report(0x4c70ffff);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0x4c70f07c);\n -# output: report(0x00000f07);\n -# output: report(0x4c70ff7b);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: report(0xb38f0f83);\n -# output: report(0x0000f83b);\n -# output: report(0x4c70f7b8);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: report(0x00000000);\n -# output: \n -# output: exit(0)\n - -#include "or1k-asm-test-helpers.h" - - STANDARD_TEST_ENVIRONMENT - - .section .text -start_tests: - PUSH LINK_REGISTER_R9 - - /* Always set OVE. We should never trigger an exception, even if - this bit is set. */ - SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3 - - /* Test the l.xor instruction with a range of operands. */ - - TEST_INST_I32_I32 l.xor, 0x00000000, 0x00000000 - TEST_INST_I32_I32 l.xor, 0xffffffff, 0xffffffff - TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0x00000000 - TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0xaaaaaaaa - TEST_INST_I32_I32 l.xor, 0x55555555, 0x00000000 - TEST_INST_I32_I32 l.xor, 0x55555555, 0x55555555 - TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0x55555555 - TEST_INST_I32_I32 l.xor, 0x4c70f07c, 0xb38f0f83 - TEST_INST_I32_I32 l.xor, 0x4c70f07c, 0xc4c70f07 - TEST_INST_I32_I32 l.xor, 0xb38f0f83, 0x38f0f83b - - /* Test the l.xori instruction with a range of operands. */ - - TEST_INST_I32_I16 l.xori, 0x00000000, 0x0000 - TEST_INST_I32_I16 l.xori, 0xffffffff, 0xffff - TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0x0000 - TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0xaaaa - TEST_INST_I32_I16 l.xori, 0x55555555, 0x0000 - TEST_INST_I32_I16 l.xori, 0x55555555, 0x5555 - TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0x5555 - TEST_INST_I32_I16 l.xori, 0x4c70f07c, 0x0f83 - TEST_INST_I32_I16 l.xori, 0x4c70f07c, 0x0f07 - TEST_INST_I32_I16 l.xori, 0xb38f0f83, 0xf83b - - POP LINK_REGISTER_R9 - RETURN_TO_LINK_REGISTER_R9 diff --git a/sim/testsuite/sim/pru/ChangeLog b/sim/testsuite/sim/pru/ChangeLog deleted file mode 100644 index 3d862d1..0000000 --- a/sim/testsuite/sim/pru/ChangeLog +++ /dev/null @@ -1,17 +0,0 @@ -2020-11-12 Dimitar Dimitrov - - * lmbd.s: New test. - -2019-09-23 Dimitar Dimitrov - - * add.s: New test. - * allinsn.exp: New file. - * dmem-zero-pass.s: New test. - * dmem-zero-trap.s: New test. - * dram.s: New test. - * jmp.s: New test. - * loop-imm.s: New test. - * loop-reg.s: New test. - * mul.s: New test. - * subreg.s: New test. - * testutils.inc: New file. diff --git a/sim/testsuite/sim/pru/add.s b/sim/testsuite/sim/pru/add.s deleted file mode 100644 index 89e6f13..0000000 --- a/sim/testsuite/sim/pru/add.s +++ /dev/null @@ -1,40 +0,0 @@ -# Check that basic add insn works. -# mach: pru - -# Copyright (C) 2016-2021 Free Software Foundation, Inc. -# Contributed by Dimitar Dimitrov -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -.include "testutils.inc" - - start - - ldi r4, 10 - add r4, r4, 23 - qbne 2f, r4, 33 - - qblt 2f, r4, 33 - - qbgt 2f, r4, 33 - - jmp 1f - - fail - -1: - pass -2: fail diff --git a/sim/testsuite/sim/pru/allinsn.exp b/sim/testsuite/sim/pru/allinsn.exp deleted file mode 100644 index d147f73..0000000 --- a/sim/testsuite/sim/pru/allinsn.exp +++ /dev/null @@ -1,33 +0,0 @@ -# PRU simulator testsuite. - -# Copyright (C) 2016-2021 Free Software Foundation, Inc. -# Contributed by Dimitar Dimitrov -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -if [istarget pru-*] { - # all machines - set all_machs "pru" - - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/pru/dmem-zero-pass.s b/sim/testsuite/sim/pru/dmem-zero-pass.s deleted file mode 100644 index 7206d2f..0000000 --- a/sim/testsuite/sim/pru/dmem-zero-pass.s +++ /dev/null @@ -1,29 +0,0 @@ -# Check that DMEM zero address access works by default. -# mach: pru - -# Copyright (C) 2016-2021 Free Software Foundation, Inc. -# Contributed by Dimitar Dimitrov -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -.include "testutils.inc" - - start - - ldi r1, 0 - lbbo &r2, r1, 0, 4 - - pass diff --git a/sim/testsuite/sim/pru/dmem-zero-trap.s b/sim/testsuite/sim/pru/dmem-zero-trap.s deleted file mode 100644 index 58febb7..0000000 --- a/sim/testsuite/sim/pru/dmem-zero-trap.s +++ /dev/null @@ -1,32 +0,0 @@ -# Check that DMEM zero address access can be trapped. -# mach: pru -# sim: --error-null-deref -# xerror: -# output: core: 4 byte read to unmapped address 0x0 at *\n - -# Copyright (C) 2016-2021 Free Software Foundation, Inc. -# Contributed by Dimitar Dimitrov -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -.include "testutils.inc" - - start - - ldi r1, 0 - lbbo &r2, r1, 0, 4 - - pass diff --git a/sim/testsuite/sim/pru/dram.s b/sim/testsuite/sim/pru/dram.s deleted file mode 100644 index 5f35633..0000000 --- a/sim/testsuite/sim/pru/dram.s +++ /dev/null @@ -1,72 +0,0 @@ -# Check that DRAM memory access works. -# mach: pru - -# Copyright (C) 2016-2021 Free Software Foundation, Inc. -# Contributed by Dimitar Dimitrov -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -.include "testutils.inc" - - start - - fill r20, 16 - ldi r10, 0 - not r10, r10 - qbne F, r20, r10 - qbne F, r21, r10 - qbne F, r22, r10 - qbne F, r23, r10 - - zero r20, 16 - qbne F, r20, 0 - qbne F, r21, 0 - qbne F, r22, 0 - qbne F, r23, 0 - - ldi r0, testarray - lbbo &r20, r0, 0, 7 - qbne F, r20.b0, 0x01 - qbne F, r20.b1, 0x23 - qbne F, r20.b2, 0x45 - qbne F, r20.b3, 0x67 - qbne F, r21.b0, 0x89 - qbne F, r21.b1, 0xab - qbne F, r21.b2, 0xcd - qbne F, r21.b3, 0x00 ; Should not have been loaded! - qbne F, r22, 0 - qbne F, r23, 0 - - ldi r1, 0x11 - sbbo &r1, r0, 9, 1 - ldi r1, 0x11 - sbbo &r1, r0, 12, 4 - - lbbo &r20, r0, 0, 16 - qbne F, r21.b3, 0xef - qbne F, r22.b0, 0xff - qbne F, r22.b1, 0x11 - qbne F, r22.b2, 0xff - qbne F, r22.b3, 0xff - qbne F, r23, 0x11 - - pass -F: fail - - .data -testarray: - .byte 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef - .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff diff --git a/sim/testsuite/sim/pru/jmp.s b/sim/testsuite/sim/pru/jmp.s deleted file mode 100644 index 9b2ec10..0000000 --- a/sim/testsuite/sim/pru/jmp.s +++ /dev/null @@ -1,40 +0,0 @@ -# Check that jump and branch insns work. -# mach: pru - -# Copyright (C) 2016-2021 Free Software Foundation, Inc. -# Contributed by Dimitar Dimitrov -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -.include "testutils.inc" - - start - - ldi r10, 10 - call func1 - qbne F, r10, 11 - - ldi r0, %pmem(1f) - jmp r0 - fail -1: - pass -F: fail - - -func1: - add r10, r10, 1 - ret diff --git a/sim/testsuite/sim/pru/lmbd.s b/sim/testsuite/sim/pru/lmbd.s deleted file mode 100644 index 36e3086..0000000 --- a/sim/testsuite/sim/pru/lmbd.s +++ /dev/null @@ -1,61 +0,0 @@ -# Check that lmbd insn works. -# mach: pru - -# Copyright (C) 2020-2021 Free Software Foundation, Inc. -# Contributed by Dimitar Dimitrov -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -.include "testutils.inc" - - start - - ldi32 r14, 0xffffffff - ldi32 r15, 0x0 - ldi32 r16, 0x40000000 - ldi32 r17, 8 - - lmbd r0, r14, 0 - qbne 2f, r0, 32 - - lmbd r0, r14, 1 - qbne 2f, r0, 31 - - lmbd r0, r15, 1 - qbne 2f, r0, 32 - - lmbd r0, r15, 0 - qbne 2f, r0, 31 - - lmbd r0, r16, r15 - qbne 2f, r0, 31 - - lmbd r0, r16, 1 - qbne 2f, r0, 30 - - lmbd r0, r14.w1, 1 - qbne 2f, r0, 15 - - lmbd r0, r17.b0, 1 - qbne 2f, r0, 3 - - lmbd r0, r17.b0, r15 - qbne 2f, r0, 7 - - -1: - pass -2: fail diff --git a/sim/testsuite/sim/pru/loop-imm.s b/sim/testsuite/sim/pru/loop-imm.s deleted file mode 100644 index 4de04fa..0000000 --- a/sim/testsuite/sim/pru/loop-imm.s +++ /dev/null @@ -1,43 +0,0 @@ -# Check that loop insn works. -# mach: pru - -# Copyright (C) 2016-2021 Free Software Foundation, Inc. -# Contributed by Dimitar Dimitrov -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -.include "testutils.inc" - - start - - ldi r25, 0 - ldi r26, 0 - ldi r27, 0 - - add r27, r27, 1 - loop 1f, 10 - add r25, r25, 1 - add r26, r26, 2 -1: - add r27, r27, 1 - - qbne F, r25, 10 - qbne F, r26, 20 - qbne F, r27, 2 - - pass - -F: fail diff --git a/sim/testsuite/sim/pru/loop-reg.s b/sim/testsuite/sim/pru/loop-reg.s deleted file mode 100644 index 3fe6654..0000000 --- a/sim/testsuite/sim/pru/loop-reg.s +++ /dev/null @@ -1,44 +0,0 @@ -# Check that loop insn works. -# mach: pru - -# Copyright (C) 2016-2021 Free Software Foundation, Inc. -# Contributed by Dimitar Dimitrov -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -.include "testutils.inc" - - start - - ldi r25, 0 - ldi r26, 0 - ldi r27, 0 - ldi r28, 10 - - add r27, r27, 1 - loop 1f, r28 - add r25, r25, 1 - add r26, r26, 2 -1: - add r27, r27, 1 - - qbne F, r25, 10 - qbne F, r26, 20 - qbne F, r27, 2 - - pass - -F: fail diff --git a/sim/testsuite/sim/pru/mul.s b/sim/testsuite/sim/pru/mul.s deleted file mode 100644 index 7aacc41..0000000 --- a/sim/testsuite/sim/pru/mul.s +++ /dev/null @@ -1,89 +0,0 @@ -# Check that multiplication works. -# mach: pru - -# Copyright (C) 2016-2021 Free Software Foundation, Inc. -# Contributed by Dimitar Dimitrov -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -.include "testutils.inc" - - start - - # MUL: Test regular case - ldi r28, 1001 - ldi r29, 4567 - nop - xin 0, r26, 4 - qbne32 2f, r26, 1001 * 4567 - - # MUL: Test the pipeline emulation - ldi r28, 1002 - ldi r29, 1003 - ldi r29, 4004 - xin 0, r26, 4 - qbne32 2f, r26, 1002 * 1003 - xin 0, r26, 4 - qbne32 2f, r26, 1002 * 4004 - - # MUL: Test 64-bit result - ldi32 r28, 0x12345678 - ldi32 r29, 0xaabbccdd - nop - xin 0, r26, 8 - qbne32 2f, r26, 0x45BE4598 - qbne32 2f, r27, 0xC241C38 - - # MAC: Test regular case - ldi r25, 1 - xout 0, r25, 1 - ldi r25, 3 - xout 0, r25, 1 - - ldi r25, 1 - ldi r28, 1001 - ldi r29, 2002 - xout 0, r25, 1 - ldi r28, 3003 - ldi r29, 4004 - xout 0, r25, 1 - - xin 0, r26, 4 - qbne32 2f, r26, (1001 * 2002) + (3003 * 4004) - - # MAC: Test 64-bit result - ldi r25, 3 - xout 0, r25, 1 - - ldi r25, 1 - ldi32 r28, 0x10203040 - ldi32 r29, 0x50607080 - xout 0, r25, 1 - ldi32 r28, 0xa0b0c0d0 - ldi32 r29, 0x11223344 - xout 0, r25, 1 - - xin 0, r26, 8 - qbne32 2f, r26, 0x8E30C740 - qbne32 2f, r27, 0xFD156B1 - - jmp 1f - - fail - -1: - pass -2: fail diff --git a/sim/testsuite/sim/pru/subreg.s b/sim/testsuite/sim/pru/subreg.s deleted file mode 100644 index 372f700..0000000 --- a/sim/testsuite/sim/pru/subreg.s +++ /dev/null @@ -1,40 +0,0 @@ -# Check that subregister addressing works. -# mach: pru - -# Copyright (C) 2016-2021 Free Software Foundation, Inc. -# Contributed by Dimitar Dimitrov -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -.include "testutils.inc" - - start - - ldi r0, 0x01ff - add r0, r0.b0, r0.b1 - qbne F, r0.b0, 0x00 - qbne F, r0.b1, 0x01 - qbne F, r0.w2, 0x00 - - ldi r0, 0x01ff - add r0.b0, r0.b0, r0.b1 - adc r0, r0.b1, r0.b3 - qbne F, r0.b0, 0x02 - qbne F, r0.b1, 0x00 - qbne F, r0.w2, 0x00 - - pass -F: fail diff --git a/sim/testsuite/sim/pru/testutils.inc b/sim/testsuite/sim/pru/testutils.inc deleted file mode 100644 index dfe63f3..0000000 --- a/sim/testsuite/sim/pru/testutils.inc +++ /dev/null @@ -1,100 +0,0 @@ -# Copyright (C) 2016-2021 Free Software Foundation, Inc. -# Contributed by Dimitar Dimitrov -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . - -# MACRO: start -# All assembler tests should start with a call to "main_test" - .macro start - .text - - .global _start -_start: - - # Skip over these inlined funcs. - jmp __main_test; - - .global __pass - .type __pass, function -__pass: - # Note - DRAM LMA and VMA are equal for PRU, so - # we can afford to pass DRAM pointer directly. - write 1, _passmsg, 5 - exit 0 - - .global __fail - .type __fail, function -__fail: - write 1, _failmsg, 5 - exit 1 - - .data -_passmsg: - .ascii "pass\n" - -_failmsg: - .ascii "fail\n" - - .text - .global __main_test - .type __main_test, function -__main_test: - .endm - -# MACRO: system_call -# Make a libgloss system call - .macro system_call nr:req, arg1=0, arg2=0, arg3=0 - ldi r1, \nr - ldi r14, \arg1 - ldi r15, \arg2 - ldi r16, \arg3 - halt - .endm - -# MACRO: exit -# Quit the current test - .macro exit rc:req - system_call 1, \rc - .endm - -# MACRO: pass -# Write 'pass' to stdout via syscalls and quit; -# meant for non-OS operating environments - .macro pass - jmp __pass; - .endm - -# MACRO: fail -# Write 'fail' to stdout via syscalls and quit; -# meant for non-OS operating environments - .macro fail - jmp __fail; - .endm - -# MACRO: write -# Just like the write() C function; uses system calls - .macro write fd:req, str:req, len:req - system_call 5, \fd, \str, \len - .endm - -# MACRO: qbne32 -# Like qbne instruction, but check a 32-bit constant value. - .macro qbne32 label:req, op0:req, C0:req - qbne \label, \op0\().b0, ((\C0) >> 0) & 0xff - qbne \label, \op0\().b1, ((\C0) >> 8) & 0xff - qbne \label, \op0\().b2, ((\C0) >> 16) & 0xff - qbne \label, \op0\().b3, ((\C0) >> 24) & 0xff - .endm diff --git a/sim/testsuite/sim/sh/ChangeLog b/sim/testsuite/sim/sh/ChangeLog deleted file mode 100644 index e3852f9..0000000 --- a/sim/testsuite/sim/sh/ChangeLog +++ /dev/null @@ -1,77 +0,0 @@ -2004-09-13 DJ Delorie - - * sim/sh/allinsn.exp: Set global_as_options and - global_ld_options appropriately for little endian builds. - * sim/sh/movua.s: Support little endian. - -2004-09-08 Michael Snyder - - Commited by Corinna Vinschen - * allinsn.exp: Add new tests. - * bandor.s: New file. - * bandornot.s: New file. - * bclr.s: New file. - * bld.s: New file. - * bldnot.s: New file. - * bset.s: New file. - * bst.s: New file. - * bxor.s: New file. - * clip.s: New file. - * div.s: New file. - * fail.s: New file, make sure fail works. - * fsca.s: New file. - * fsrra.s: New file. - * mov.s: New file. - * mulr.s: New file. - * pass.s: New file, make sure pass works. - * pushpop.s: New file. - * resbank.s: New file. - * testutils.inc (bf8k, bt8k, assertmem): New macros. - -2004-02-12 Michael Snyder - - * and.s, movi.s, sett.s: New files. - * allinsn.exp: Add new tests. - * testutils.inc (set_sr_bit): Fix macro labels. - -2004-01-07 Michael Snyder - - * dmxy.s, fipr.s, fpchg.s, ldrc.s, loop.s, movli.s, movua.s, - movxy.s, pabs.s, pclr.s, prnd.s, psub.s, pswap.s: New files. - * allinsn.exp: Add new tests. - * testutils.inc (set_sr_bit): Add argument. - (set_greg): Add .align directives. - -2003-08-11 Michael Snyder - - * macl.s: New file. - * macw.s: New file. - * allinsn.exp: Add new tests for mac.w and mac.l. - -2003-07-25 Michael Snyder - - * pshai.s, pshar.s, pshli.s, pshlr.s: New files. - * allinsn.exp: Add psha, pshl tests. - * pdec.s, pinc.s, padd.s, paddc.s: New files. - * allinsn.exp: Add pdec, pinc, padd, paddc tests. - * pand.s, pdmsb.s: New files. - * allinsn.exp: Add pand, pdmsb tests. - -2003-07-23 Michael Snyder - - * pmuls.s: New file. - -2003-07-08 Michael Snyder - - * allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s, - fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s, - float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s, - fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s, - shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files. - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -End: diff --git a/sim/testsuite/sim/sh/add.s b/sim/testsuite/sim/sh/add.s deleted file mode 100644 index 9519251..0000000 --- a/sim/testsuite/sim/sh/add.s +++ /dev/null @@ -1,86 +0,0 @@ -# sh testcase for add -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -_x: .long 1 -_y: .long 1 - - start - -add_reg_reg_direct: - set_grs_a5a5 - mov.l i, r1 - mov.l j, r2 - add r1, r2 - test_gr0_a5a5 - assertreg 2 r1 - assertreg 4 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -add_reg_reg_indirect: - set_grs_a5a5 - mov.l x, r1 - mov.l y, r2 - mov.l @r1, r1 - mov.l @r2, r2 - add r1, r2 - test_gr0_a5a5 - assertreg 1 r1 - assertreg 2 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -add_imm_reg: - set_grs_a5a5 - add #0x16, r1 - test_gr0_a5a5 - assertreg 0xa5a5a5bb r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - - .align 2 -x: .long _x -y: .long _y -i: .long 2 -j: .long 2 - diff --git a/sim/testsuite/sim/sh/allinsn.exp b/sim/testsuite/sim/sh/allinsn.exp deleted file mode 100644 index 40d1392..0000000 --- a/sim/testsuite/sim/sh/allinsn.exp +++ /dev/null @@ -1,89 +0,0 @@ -# sh tests - -set all "sh shdsp" - -set global_as_options "" -set global_ld_options "" - -foreach opt $board_variant_list { - switch "x$opt" { - x-ml { set global_as_options "-little --defsym LITTLE=1" - set global_ld_options "-EL" } - } -} - -if [istarget sh-*elf] { - run_sim_test add.s $all - run_sim_test and.s $all - run_sim_test bandor.s sh - run_sim_test bandornot.s sh - run_sim_test bclr.s sh - run_sim_test bld.s sh - run_sim_test bldnot.s sh - run_sim_test bset.s sh - run_sim_test bst.s sh - run_sim_test bxor.s sh - run_sim_test clip.s sh - run_sim_test div.s sh - run_sim_test dmxy.s shdsp - run_sim_test fabs.s sh - run_sim_test fadd.s sh - run_sim_test fcmpeq.s sh - run_sim_test fcmpgt.s sh - run_sim_test fcnvds.s sh - run_sim_test fcnvsd.s sh - run_sim_test fdiv.s sh - run_sim_test fipr.s sh - run_sim_test fldi0.s sh - run_sim_test fldi1.s sh - run_sim_test flds.s sh - run_sim_test float.s sh - run_sim_test fmac.s sh - run_sim_test fmov.s sh - run_sim_test fmul.s sh - run_sim_test fneg.s sh - run_sim_test fpchg.s sh - run_sim_test frchg.s sh - run_sim_test fschg.s sh - run_sim_test fsqrt.s sh - run_sim_test fsub.s sh - run_sim_test ftrc.s sh - run_sim_test ldrc.s shdsp - run_sim_test loop.s shdsp - run_sim_test macl.s sh - run_sim_test macw.s sh - run_sim_test mov.s $all - run_sim_test movi.s $all - run_sim_test movli.s $all - run_sim_test movua.s $all - run_sim_test movxy.s shdsp - run_sim_test mulr.s sh - run_sim_test pabs.s shdsp - run_sim_test paddc.s shdsp - run_sim_test padd.s shdsp - run_sim_test pand.s shdsp - run_sim_test pclr.s shdsp - run_sim_test pdec.s shdsp - run_sim_test pdmsb.s shdsp - run_sim_test pinc.s shdsp - run_sim_test pmuls.s shdsp - run_sim_test prnd.s shdsp - run_sim_test pshai.s shdsp - run_sim_test pshar.s shdsp - run_sim_test pshli.s shdsp - run_sim_test pshlr.s shdsp - run_sim_test psub.s shdsp - run_sim_test pswap.s shdsp - run_sim_test pushpop.s sh - run_sim_test resbank.s sh - run_sim_test sett.s sh - run_sim_test shll.s $all - run_sim_test shll2.s $all - run_sim_test shll8.s $all - run_sim_test shll16.s $all - run_sim_test shlr.s $all - run_sim_test shlr2.s $all - run_sim_test shlr8.s $all - run_sim_test shlr16.s $all - run_sim_test swap.s $all -} diff --git a/sim/testsuite/sim/sh/and.s b/sim/testsuite/sim/sh/and.s deleted file mode 100644 index 0093447..0000000 --- a/sim/testsuite/sim/sh/and.s +++ /dev/null @@ -1,89 +0,0 @@ -# sh testcase for and -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -_x: .long 0xa5a5a5a5 -_y: .long 0x55555555 - - start - -and_reg_reg_direct: - set_grs_a5a5 - mov.l i, r1 - mov.l j, r2 - and r1, r2 - test_gr0_a5a5 - assertreg 0xa5a5a5a5 r1 - assertreg 0xa0a0a0a0 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - bra and_imm_reg - nop - - .align 2 -i: .long 0xa5a5a5a5 -j: .long 0xaaaaaaaa - -and_imm_reg: - set_grs_a5a5 - and #0xff, r0 - assertreg 0xa5, r0 - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -and_b_imm_ind: - set_grs_a5a5 - mov.l x, r0 - and.b #0x55, @(r0, GBR) - mov.l @r0, r0 - - assertreg 0xa5a5a505, r0 - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - - .align 2 -x: .long _x -y: .long _y - diff --git a/sim/testsuite/sim/sh/bandor.s b/sim/testsuite/sim/sh/bandor.s deleted file mode 100644 index 9ada485..0000000 --- a/sim/testsuite/sim/sh/bandor.s +++ /dev/null @@ -1,120 +0,0 @@ -# sh testcase for band, bor -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -_x: .long 0xa5a5a5a5 - - start - -bandor_b_imm_disp12_reg: - set_grs_a5a5 - # Make sure T is true to start. - sett - - mov.l x, r1 - - band.b #0, @(3, r1) - bf8k mfail - bor.b #1, @(3, r1) - bf8k mfail - band.b #2, @(3, r1) - bf8k mfail - bor.b #3, @(3, r1) - bf8k mfail - - bor.b #4, @(3, r1) - bf8k mfail - band.b #5, @(3, r1) - bf8k mfail - bor.b #6, @(3, r1) - bf8k mfail - band.b #7, @(3, r1) - bf8k mfail - - band.b #0, @(2, r1) - bf8k mfail - bor.b #1, @(2, r1) - bf8k mfail - band.b #2, @(2, r1) - bf8k mfail - bor.b #3, @(2, r1) - bf8k mfail - - bra .L2 - nop - - .align 2 -x: .long _x - -.L2: - bor.b #4, @(2, r1) - bf8k mfail - band.b #5, @(2, r1) - bf8k mfail - bor.b #6, @(2, r1) - bf8k mfail - band.b #7, @(2, r1) - bf8k mfail - - band.b #0, @(1, r1) - bf8k mfail - bor.b #1, @(1, r1) - bf8k mfail - band.b #2, @(1, r1) - bf8k mfail - bor.b #3, @(1, r1) - bf8k mfail - - bor.b #4, @(1, r1) - bf8k mfail - band.b #5, @(1, r1) - bf8k mfail - bor.b #6, @(1, r1) - bf8k mfail - band.b #7, @(1, r1) - bf8k mfail - - band.b #0, @(0, r1) - bf8k mfail - bor.b #1, @(0, r1) - bf8k mfail - band.b #2, @(0, r1) - bf8k mfail - bor.b #3, @(0, r1) - bf8k mfail - - bor.b #4, @(0, r1) - bf8k mfail - band.b #5, @(0, r1) - bf8k mfail - bor.b #6, @(0, r1) - bf8k mfail - band.b #7, @(0, r1) - bf8k mfail - - assertreg _x, r1 - - test_gr_a5a5 r0 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - - diff --git a/sim/testsuite/sim/sh/bandornot.s b/sim/testsuite/sim/sh/bandornot.s deleted file mode 100644 index 1787d0d..0000000 --- a/sim/testsuite/sim/sh/bandornot.s +++ /dev/null @@ -1,120 +0,0 @@ -# sh testcase for bandnot, bornot -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -_x: .long 0xa5a5a5a5 - - start - -bandor_b_imm_disp12_reg: - set_grs_a5a5 - # Make sure T is true to start. - sett - - mov.l x, r1 - - bandnot.b #0, @(3, r1) - bt8k mfail - bornot.b #1, @(3, r1) - bf8k mfail - bandnot.b #2, @(3, r1) - bt8k mfail - bornot.b #3, @(3, r1) - bf8k mfail - - bornot.b #4, @(3, r1) - bf8k mfail - bandnot.b #5, @(3, r1) - bt8k mfail - bornot.b #6, @(3, r1) - bf8k mfail - bandnot.b #7, @(3, r1) - bt8k mfail - - bandnot.b #0, @(2, r1) - bt8k mfail - bornot.b #1, @(2, r1) - bf8k mfail - bandnot.b #2, @(2, r1) - bt8k mfail - bornot.b #3, @(2, r1) - bf8k mfail - - bra .L2 - nop - - .align 2 -x: .long _x - -.L2: - bornot.b #4, @(2, r1) - bf8k mfail - bandnot.b #5, @(2, r1) - bt8k mfail - bornot.b #6, @(2, r1) - bf8k mfail - bandnot.b #7, @(2, r1) - bt8k mfail - - bandnot.b #0, @(1, r1) - bt8k mfail - bornot.b #1, @(1, r1) - bf8k mfail - bandnot.b #2, @(1, r1) - bt8k mfail - bornot.b #3, @(1, r1) - bf8k mfail - - bornot.b #4, @(1, r1) - bf8k mfail - bandnot.b #5, @(1, r1) - bt8k mfail - bornot.b #6, @(1, r1) - bf8k mfail - bandnot.b #7, @(1, r1) - bt8k mfail - - bandnot.b #0, @(0, r1) - bt8k mfail - bornot.b #1, @(0, r1) - bf8k mfail - bandnot.b #2, @(0, r1) - bt8k mfail - bornot.b #3, @(0, r1) - bf8k mfail - - bornot.b #4, @(0, r1) - bf8k mfail - bandnot.b #5, @(0, r1) - bt8k mfail - bornot.b #6, @(0, r1) - bf8k mfail - bandnot.b #7, @(0, r1) - bt8k mfail - - assertreg _x, r1 - - test_gr_a5a5 r0 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - - diff --git a/sim/testsuite/sim/sh/bclr.s b/sim/testsuite/sim/sh/bclr.s deleted file mode 100644 index cbe1c7e..0000000 --- a/sim/testsuite/sim/sh/bclr.s +++ /dev/null @@ -1,139 +0,0 @@ -# sh testcase for bclr -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -_x: .long 0xffffffff -_y: .long 0x55555555 - - start - -bclr_b_imm_disp12_reg: - set_grs_a5a5 - mov.l x, r1 - - bclr.b #0, @(3, r1) - assertmem _x, 0xfffffffe - bclr.b #1, @(3, r1) - assertmem _x, 0xfffffffc - bclr.b #2, @(3, r1) - assertmem _x, 0xfffffff8 - bclr.b #3, @(3, r1) - assertmem _x, 0xfffffff0 - - bclr.b #4, @(3, r1) - assertmem _x, 0xffffffe0 - bclr.b #5, @(3, r1) - assertmem _x, 0xffffffc0 - bclr.b #6, @(3, r1) - assertmem _x, 0xffffff80 - bclr.b #7, @(3, r1) - assertmem _x, 0xffffff00 - - bclr.b #0, @(2, r1) - assertmem _x, 0xfffffe00 - bclr.b #1, @(2, r1) - assertmem _x, 0xfffffc00 - bclr.b #2, @(2, r1) - assertmem _x, 0xfffff800 - bclr.b #3, @(2, r1) - assertmem _x, 0xfffff000 - - bra .L2 - nop - - .align 2 -x: .long _x -y: .long _y - -.L2: - bclr.b #4, @(2, r1) - assertmem _x, 0xffffe000 - bclr.b #5, @(2, r1) - assertmem _x, 0xffffc000 - bclr.b #6, @(2, r1) - assertmem _x, 0xffff8000 - bclr.b #7, @(2, r1) - assertmem _x, 0xffff0000 - - bclr.b #0, @(1, r1) - assertmem _x, 0xfffe0000 - bclr.b #1, @(1, r1) - assertmem _x, 0xfffc0000 - bclr.b #2, @(1, r1) - assertmem _x, 0xfff80000 - bclr.b #3, @(1, r1) - assertmem _x, 0xfff00000 - - bclr.b #4, @(1, r1) - assertmem _x, 0xffe00000 - bclr.b #5, @(1, r1) - assertmem _x, 0xffc00000 - bclr.b #6, @(1, r1) - assertmem _x, 0xff800000 - bclr.b #7, @(1, r1) - assertmem _x, 0xff000000 - - bclr.b #0, @(0, r1) - assertmem _x, 0xfe000000 - bclr.b #1, @(0, r1) - assertmem _x, 0xfc000000 - bclr.b #2, @(0, r1) - assertmem _x, 0xf8000000 - bclr.b #3, @(0, r1) - assertmem _x, 0xf0000000 - - bclr.b #4, @(0, r1) - assertmem _x, 0xe0000000 - bclr.b #5, @(0, r1) - assertmem _x, 0xc0000000 - bclr.b #6, @(0, r1) - assertmem _x, 0x80000000 - bclr.b #7, @(0, r1) - assertmem _x, 0x00000000 - - assertreg _x, r1 - -bclr_imm_reg: - set_greg 0xff, r1 - bclr #0, r1 - assertreg 0xfe, r1 - bclr #1, r1 - assertreg 0xfc, r1 - bclr #2, r1 - assertreg 0xf8, r1 - bclr #3, r1 - assertreg 0xf0, r1 - - bclr #4, r1 - assertreg 0xe0, r1 - bclr #5, r1 - assertreg 0xc0, r1 - bclr #6, r1 - assertreg 0x80, r1 - bclr #7, r1 - assertreg 0x00, r1 - - test_gr_a5a5 r0 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - - diff --git a/sim/testsuite/sim/sh/bld.s b/sim/testsuite/sim/sh/bld.s deleted file mode 100644 index 172718d..0000000 --- a/sim/testsuite/sim/sh/bld.s +++ /dev/null @@ -1,121 +0,0 @@ -# sh testcase for bld -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -_x: .long 0xa5a5a5a5 -_y: .long 0x55555555 - - start - -bld_b_imm_disp12_reg: - set_grs_a5a5 - mov.l x, r1 - - bld.b #0, @(0, r1) - bf8k mfail - bld.b #1, @(0, r1) - bt8k mfail - bld.b #2, @(0, r1) - bf8k mfail - bld.b #3, @(0, r1) - bt8k mfail - - bld.b #4, @(0, r1) - bt8k mfail - bld.b #5, @(0, r1) - bf8k mfail - bld.b #6, @(0, r1) - bt8k mfail - bld.b #7, @(0, r1) - bf8k mfail - - bld.b #0, @(1, r1) - bf8k mfail - bld.b #1, @(1, r1) - bt8k mfail - bld.b #2, @(1, r1) - bf8k mfail - bld.b #3, @(1, r1) - bt8k mfail - - bld.b #4, @(1, r1) - bt8k mfail - bld.b #5, @(1, r1) - bf8k mfail - bld.b #6, @(1, r1) - bt8k mfail - bld.b #7, @(1, r1) - bf8k mfail - - bld.b #0, @(2, r1) - bf8k mfail - bld.b #1, @(2, r1) - bt8k mfail - bld.b #2, @(2, r1) - bf8k mfail - bld.b #3, @(2, r1) - bt8k mfail - - bld.b #4, @(2, r1) - bt8k mfail - bld.b #5, @(2, r1) - bf8k mfail - bld.b #6, @(2, r1) - bt8k mfail - bld.b #7, @(2, r1) - bf8k mfail - - bld.b #0, @(3, r1) - bf8k mfail - bld.b #1, @(3, r1) - bt8k mfail - bld.b #2, @(3, r1) - bf8k mfail - bld.b #3, @(3, r1) - bt8k mfail - - bld.b #4, @(3, r1) - bt8k mfail - bld.b #5, @(3, r1) - bf8k mfail - bld.b #6, @(3, r1) - bt8k mfail - bld.b #7, @(3, r1) - bf8k mfail - - assertreg _x, r1 - -bld_imm_reg: - set_greg 0xa5a5a5a5, r1 - bld #0, r1 - bf8k mfail - bld #1, r1 - bt8k mfail - bld #2, r1 - bf8k mfail - bld #3, r1 - bt8k mfail - - bld #4, r1 - bt8k mfail - bld #5, r1 - bf8k mfail - bld #6, r1 - bt8k mfail - bld #7, r1 - bf8k mfail - - test_grs_a5a5 - - pass - - exit 0 - - .align 2 -x: .long _x -y: .long _y - diff --git a/sim/testsuite/sim/sh/bldnot.s b/sim/testsuite/sim/sh/bldnot.s deleted file mode 100644 index eda87de..0000000 --- a/sim/testsuite/sim/sh/bldnot.s +++ /dev/null @@ -1,102 +0,0 @@ -# sh testcase for bldnot -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -_x: .long 0xa5a5a5a5 -_y: .long 0x55555555 - - start - -bldnot_b_imm_disp12_reg: - set_grs_a5a5 - mov.l x, r1 - - bldnot.b #0, @(0, r1) - bt8k mfail - bldnot.b #1, @(0, r1) - bf8k mfail - bldnot.b #2, @(0, r1) - bt8k mfail - bldnot.b #3, @(0, r1) - bf8k mfail - - bldnot.b #4, @(0, r1) - bf8k mfail - bldnot.b #5, @(0, r1) - bt8k mfail - bldnot.b #6, @(0, r1) - bf8k mfail - bldnot.b #7, @(0, r1) - bt8k mfail - - bldnot.b #0, @(1, r1) - bt8k mfail - bldnot.b #1, @(1, r1) - bf8k mfail - bldnot.b #2, @(1, r1) - bt8k mfail - bldnot.b #3, @(1, r1) - bf8k mfail - - bldnot.b #4, @(1, r1) - bf8k mfail - bldnot.b #5, @(1, r1) - bt8k mfail - bldnot.b #6, @(1, r1) - bf8k mfail - bldnot.b #7, @(1, r1) - bt8k mfail - - bldnot.b #0, @(2, r1) - bt8k mfail - bldnot.b #1, @(2, r1) - bf8k mfail - bldnot.b #2, @(2, r1) - bt8k mfail - bldnot.b #3, @(2, r1) - bf8k mfail - - bldnot.b #4, @(2, r1) - bf8k mfail - bldnot.b #5, @(2, r1) - bt8k mfail - bldnot.b #6, @(2, r1) - bf8k mfail - bldnot.b #7, @(2, r1) - bt8k mfail - - bldnot.b #0, @(3, r1) - bt8k mfail - bldnot.b #1, @(3, r1) - bf8k mfail - bldnot.b #2, @(3, r1) - bt8k mfail - bldnot.b #3, @(3, r1) - bf8k mfail - - bldnot.b #4, @(3, r1) - bf8k mfail - bldnot.b #5, @(3, r1) - bt8k mfail - bldnot.b #6, @(3, r1) - bf8k mfail - bldnot.b #7, @(3, r1) - bt8k mfail - - assertreg _x, r1 - set_greg 0xa5a5a5a5, r1 - - test_grs_a5a5 - - pass - - exit 0 - - .align 2 -x: .long _x -y: .long _y - diff --git a/sim/testsuite/sim/sh/bset.s b/sim/testsuite/sim/sh/bset.s deleted file mode 100644 index 13ae246..0000000 --- a/sim/testsuite/sim/sh/bset.s +++ /dev/null @@ -1,139 +0,0 @@ -# sh testcase for bset -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -_x: .long 0 -_y: .long 0x55555555 - - start - -bset_b_imm_disp12_reg: - set_grs_a5a5 - mov.l x, r1 - - bset.b #0, @(3, r1) - assertmem _x, 0x1 - bset.b #1, @(3, r1) - assertmem _x, 0x3 - bset.b #2, @(3, r1) - assertmem _x, 0x7 - bset.b #3, @(3, r1) - assertmem _x, 0xf - - bset.b #4, @(3, r1) - assertmem _x, 0x1f - bset.b #5, @(3, r1) - assertmem _x, 0x3f - bset.b #6, @(3, r1) - assertmem _x, 0x7f - bset.b #7, @(3, r1) - assertmem _x, 0xff - - bset.b #0, @(2, r1) - assertmem _x, 0x1ff - bset.b #1, @(2, r1) - assertmem _x, 0x3ff - bset.b #2, @(2, r1) - assertmem _x, 0x7ff - bset.b #3, @(2, r1) - assertmem _x, 0xfff - - bra .L2 - nop - - .align 2 -x: .long _x -y: .long _y - -.L2: - bset.b #4, @(2, r1) - assertmem _x, 0x1fff - bset.b #5, @(2, r1) - assertmem _x, 0x3fff - bset.b #6, @(2, r1) - assertmem _x, 0x7fff - bset.b #7, @(2, r1) - assertmem _x, 0xffff - - bset.b #0, @(1, r1) - assertmem _x, 0x1ffff - bset.b #1, @(1, r1) - assertmem _x, 0x3ffff - bset.b #2, @(1, r1) - assertmem _x, 0x7ffff - bset.b #3, @(1, r1) - assertmem _x, 0xfffff - - bset.b #4, @(1, r1) - assertmem _x, 0x1fffff - bset.b #5, @(1, r1) - assertmem _x, 0x3fffff - bset.b #6, @(1, r1) - assertmem _x, 0x7fffff - bset.b #7, @(1, r1) - assertmem _x, 0xffffff - - bset.b #0, @(0, r1) - assertmem _x, 0x1ffffff - bset.b #1, @(0, r1) - assertmem _x, 0x3ffffff - bset.b #2, @(0, r1) - assertmem _x, 0x7ffffff - bset.b #3, @(0, r1) - assertmem _x, 0xfffffff - - bset.b #4, @(0, r1) - assertmem _x, 0x1fffffff - bset.b #5, @(0, r1) - assertmem _x, 0x3fffffff - bset.b #6, @(0, r1) - assertmem _x, 0x7fffffff - bset.b #7, @(0, r1) - assertmem _x, 0xffffffff - - assertreg _x, r1 - -bset_imm_reg: - set_greg 0, r1 - bset #0, r1 - assertreg 0x1, r1 - bset #1, r1 - assertreg 0x3, r1 - bset #2, r1 - assertreg 0x7, r1 - bset #3, r1 - assertreg 0xf, r1 - - bset #4, r1 - assertreg 0x1f, r1 - bset #5, r1 - assertreg 0x3f, r1 - bset #6, r1 - assertreg 0x7f, r1 - bset #7, r1 - assertreg 0xff, r1 - - test_gr_a5a5 r0 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - - diff --git a/sim/testsuite/sim/sh/bst.s b/sim/testsuite/sim/sh/bst.s deleted file mode 100644 index e8b6d65..0000000 --- a/sim/testsuite/sim/sh/bst.s +++ /dev/null @@ -1,142 +0,0 @@ -# sh testcase for bst -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -_x: .long 0 -_y: .long 0x55555555 - - start - -bst_b_imm_disp12_reg: - set_grs_a5a5 - # Make sure T is true to start. - sett - - mov.l x, r1 - - bst.b #0, @(3, r1) - assertmem _x, 0x1 - bst.b #1, @(3, r1) - assertmem _x, 0x3 - bst.b #2, @(3, r1) - assertmem _x, 0x7 - bst.b #3, @(3, r1) - assertmem _x, 0xf - - bst.b #4, @(3, r1) - assertmem _x, 0x1f - bst.b #5, @(3, r1) - assertmem _x, 0x3f - bst.b #6, @(3, r1) - assertmem _x, 0x7f - bst.b #7, @(3, r1) - assertmem _x, 0xff - - bst.b #0, @(2, r1) - assertmem _x, 0x1ff - bst.b #1, @(2, r1) - assertmem _x, 0x3ff - bst.b #2, @(2, r1) - assertmem _x, 0x7ff - bst.b #3, @(2, r1) - assertmem _x, 0xfff - - bra .L2 - nop - - .align 2 -x: .long _x -y: .long _y - -.L2: - bst.b #4, @(2, r1) - assertmem _x, 0x1fff - bst.b #5, @(2, r1) - assertmem _x, 0x3fff - bst.b #6, @(2, r1) - assertmem _x, 0x7fff - bst.b #7, @(2, r1) - assertmem _x, 0xffff - - bst.b #0, @(1, r1) - assertmem _x, 0x1ffff - bst.b #1, @(1, r1) - assertmem _x, 0x3ffff - bst.b #2, @(1, r1) - assertmem _x, 0x7ffff - bst.b #3, @(1, r1) - assertmem _x, 0xfffff - - bst.b #4, @(1, r1) - assertmem _x, 0x1fffff - bst.b #5, @(1, r1) - assertmem _x, 0x3fffff - bst.b #6, @(1, r1) - assertmem _x, 0x7fffff - bst.b #7, @(1, r1) - assertmem _x, 0xffffff - - bst.b #0, @(0, r1) - assertmem _x, 0x1ffffff - bst.b #1, @(0, r1) - assertmem _x, 0x3ffffff - bst.b #2, @(0, r1) - assertmem _x, 0x7ffffff - bst.b #3, @(0, r1) - assertmem _x, 0xfffffff - - bst.b #4, @(0, r1) - assertmem _x, 0x1fffffff - bst.b #5, @(0, r1) - assertmem _x, 0x3fffffff - bst.b #6, @(0, r1) - assertmem _x, 0x7fffffff - bst.b #7, @(0, r1) - assertmem _x, 0xffffffff - - assertreg _x, r1 - -bst_imm_reg: - set_greg 0, r1 - bst #0, r1 - assertreg 0x1, r1 - bst #1, r1 - assertreg 0x3, r1 - bst #2, r1 - assertreg 0x7, r1 - bst #3, r1 - assertreg 0xf, r1 - - bst #4, r1 - assertreg 0x1f, r1 - bst #5, r1 - assertreg 0x3f, r1 - bst #6, r1 - assertreg 0x7f, r1 - bst #7, r1 - assertreg 0xff, r1 - - test_gr_a5a5 r0 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - - diff --git a/sim/testsuite/sim/sh/bxor.s b/sim/testsuite/sim/sh/bxor.s deleted file mode 100644 index abedd38..0000000 --- a/sim/testsuite/sim/sh/bxor.s +++ /dev/null @@ -1,120 +0,0 @@ -# sh testcase for bxor -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -_x: .long 0xa5a5a5a5 - - start - -bxor_b_imm_disp12_reg: - set_grs_a5a5 - # Make sure T is true to start. - sett - - mov.l x, r1 - - bxor.b #0, @(3, r1) - bt8k mfail - bxor.b #1, @(3, r1) - bt8k mfail - bxor.b #2, @(3, r1) - bf8k mfail - bxor.b #3, @(3, r1) - bf8k mfail - - bxor.b #4, @(3, r1) - bf8k mfail - bxor.b #5, @(3, r1) - bt8k mfail - bxor.b #6, @(3, r1) - bt8k mfail - bxor.b #7, @(3, r1) - bf8k mfail - - bxor.b #0, @(2, r1) - bt8k mfail - bxor.b #1, @(2, r1) - bt8k mfail - bxor.b #2, @(2, r1) - bf8k mfail - bxor.b #3, @(2, r1) - bf8k mfail - - bra .L2 - nop - - .align 2 -x: .long _x - -.L2: - bxor.b #4, @(2, r1) - bf8k mfail - bxor.b #5, @(2, r1) - bt8k mfail - bxor.b #6, @(2, r1) - bt8k mfail - bxor.b #7, @(2, r1) - bf8k mfail - - bxor.b #0, @(1, r1) - bt8k mfail - bxor.b #1, @(1, r1) - bt8k mfail - bxor.b #2, @(1, r1) - bf8k mfail - bxor.b #3, @(1, r1) - bf8k mfail - - bxor.b #4, @(1, r1) - bf8k mfail - bxor.b #5, @(1, r1) - bt8k mfail - bxor.b #6, @(1, r1) - bt8k mfail - bxor.b #7, @(1, r1) - bf8k mfail - - bxor.b #0, @(0, r1) - bt8k mfail - bxor.b #1, @(0, r1) - bt8k mfail - bxor.b #2, @(0, r1) - bf8k mfail - bxor.b #3, @(0, r1) - bf8k mfail - - bxor.b #4, @(0, r1) - bf8k mfail - bxor.b #5, @(0, r1) - bt8k mfail - bxor.b #6, @(0, r1) - bt8k mfail - bxor.b #7, @(0, r1) - bf8k mfail - - assertreg _x, r1 - - test_gr_a5a5 r0 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - - diff --git a/sim/testsuite/sim/sh/clip.s b/sim/testsuite/sim/sh/clip.s deleted file mode 100644 index 12770c381..0000000 --- a/sim/testsuite/sim/sh/clip.s +++ /dev/null @@ -1,89 +0,0 @@ -# sh testcase for clips, clipu -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -clips_b: - set_grs_a5a5 - clips.b r1 - test_gr0_a5a5 - assertreg 0xffffff80 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -clipu_b: - set_grs_a5a5 - clipu.b r1 - test_gr0_a5a5 - assertreg 0xff r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -clips_w: - set_grs_a5a5 - clips.w r1 - test_gr0_a5a5 - assertreg 0xffff8000 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -clipu_w: - set_grs_a5a5 - clipu.w r1 - test_gr0_a5a5 - assertreg 0xffff r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - diff --git a/sim/testsuite/sim/sh/div.s b/sim/testsuite/sim/sh/div.s deleted file mode 100644 index 8293c21..0000000 --- a/sim/testsuite/sim/sh/div.s +++ /dev/null @@ -1,199 +0,0 @@ -# sh testcase for divs and divu -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -divs_1: ! divide by one - set_grs_a5a5 - mov #1, r0 - divs r0, r1 - assertreg0 1 - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -divs_2: ! divide by two - set_grs_a5a5 - mov #2, r0 - divs r0, r1 - assertreg0 2 - assertreg 0xd2d2d2d3, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -divs_3: ! divide by three - set_grs_a5a5 - mov #3, r0 - divs r0, r1 - assertreg0 3 - assertreg 0xe1e1e1e2, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -divs_0: ! divide by zero - set_grs_a5a5 - mov #0, r0 - divs r0, r1 - assertreg0 0 - assertreg 0x7fffffff, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -divs_o: ! divide signed overflow - set_grs_a5a5 - mov #16, r0 - movi20 #0x8000, r1 - shad r0, r1 ! r1 == 0x80000000 - mov #-1, r0 - divs r0, r1 - assertreg0 -1 - assertreg 0x7fffffff, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - -divu_1: ! divide by one, unsigned - set_grs_a5a5 - mov #1, r0 - divu r0, r1 - assertreg0 1 - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -divu_2: ! divide by two, unsigned - set_grs_a5a5 - mov #2, r0 - divu r0, r1 - assertreg0 2 - assertreg 0x52d2d2d2, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -divu_3: ! divide by three, unsigned - set_grs_a5a5 - mov #3, r0 - divu r0, r1 - assertreg0 3 - assertreg 0x37373737, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -divu_0: ! divide by zero, unsigned - set_grs_a5a5 - mov #0, r0 - divu r0, r1 - assertreg0 0 - assertreg 0xffffffff, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - - pass - - exit 0 - - \ No newline at end of file diff --git a/sim/testsuite/sim/sh/dmxy.s b/sim/testsuite/sim/sh/dmxy.s deleted file mode 100644 index 0e96963..0000000 --- a/sim/testsuite/sim/sh/dmxy.s +++ /dev/null @@ -1,21 +0,0 @@ -# sh testcase for setdmx, setdmy, clrdmxy -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - setdmx - test_sr_bit_set 0x400 - test_sr_bit_clear 0x800 - setdmy - test_sr_bit_clear 0x400 - test_sr_bit_set 0x800 - clrdmxy - test_sr_bit_clear 0x400 - test_sr_bit_clear 0x800 - - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fabs.s b/sim/testsuite/sim/sh/fabs.s deleted file mode 100644 index 1fb354e..0000000 --- a/sim/testsuite/sim/sh/fabs.s +++ /dev/null @@ -1,115 +0,0 @@ -# sh testcase for fabs -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fabs_freg_b0: - single_prec - bank0 - set_grs_a5a5 - set_fprs_a5a5 - # fabs(0.0) = 0.0. - fldi0 fr0 - fabs fr0 - fldi0 fr1 - fcmp/eq fr0, fr1 - bt .L1 - fail -.L1: - # fabs(1.0) = 1.0. - fldi1 fr0 - fabs fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bt .L2 - fail -.L2: - # fabs(-1.0) = 1.0. - fldi1 fr0 - fneg fr0 - fabs fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bt .L3 - fail -.L3: - test_grs_a5a5 - test_fpr_a5a5 fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fabs_dreg_b0: - # double precision tests. - set_grs_a5a5 - set_fprs_a5a5 - double_prec - # fabs(0.0) = 0.0. - fldi0 fr0 - flds fr0, fpul - fcnvsd fpul, dr0 - fabs dr0 - assert_dpreg_i 0 dr0 - - # fabs(1.0) = 1.0. - fldi1 fr0 - flds fr0, fpul - fcnvsd fpul, dr0 - fabs dr0 - assert_dpreg_i 1 dr0 - - # check. - fldi1 fr2 - flds fr2, fpul - fcnvsd fpul, dr2 - fcmp/eq dr0, dr2 - bt .L4 - fail - -.L4: - # fabs(-1.0) = 1.0. - fldi1 fr0 - fneg fr0 - flds fr0, fpul - fcnvsd fpul, dr0 - fabs dr0 - assert_dpreg_i 1 dr0 - - # check. - fldi1 fr2 - flds fr2, fpul - fcnvsd fpul, dr2 - fcmp/eq dr0, dr2 - bt .L5 - fail -.L5: - test_grs_a5a5 - assert_dpreg_i 1 dr0 - assert_dpreg_i 1 dr2 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fadd.s b/sim/testsuite/sim/sh/fadd.s deleted file mode 100644 index 72431f0..0000000 --- a/sim/testsuite/sim/sh/fadd.s +++ /dev/null @@ -1,75 +0,0 @@ -# sh testcase for fadd -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fadd_freg_freg_b0: - set_grs_a5a5 - set_fprs_a5a5 - bank0 - - fldi1 fr0 - fldi1 fr1 - fadd fr0, fr1 - assert_fpreg_i 2 fr1 - - fldi0 fr0 - fldi1 fr1 - fadd fr0, fr1 - assert_fpreg_i 1 fr1 - - fldi1 fr0 - fldi0 fr1 - fadd fr0, fr1 - assert_fpreg_i 1 fr1 - test_grs_a5a5 - assert_fpreg_i 1 fr0 - test_fpr_a5a5 fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fadd_dreg_dreg_b0: - set_grs_a5a5 - set_fprs_a5a5 - double_prec - fldi1 fr0 - fldi1 fr2 - flds fr0, fpul - fcnvsd fpul, dr0 - flds fr2, fpul - fcnvsd fpul, dr2 - fadd dr0, dr2 - fcnvds dr2, fpul - fsts fpul, fr0 - - test_grs_a5a5 - assert_fpreg_i 2, fr0 - assert_dpreg_i 2, dr2 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fail.s b/sim/testsuite/sim/sh/fail.s deleted file mode 100644 index 0ffb0b2..0000000 --- a/sim/testsuite/sim/sh/fail.s +++ /dev/null @@ -1,13 +0,0 @@ -# sh testcase, fail -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - - fail - - exit 0 - diff --git a/sim/testsuite/sim/sh/fcmpeq.s b/sim/testsuite/sim/sh/fcmpeq.s deleted file mode 100644 index 9c0ef57..0000000 --- a/sim/testsuite/sim/sh/fcmpeq.s +++ /dev/null @@ -1,119 +0,0 @@ -# sh testcase for fcmpeq -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fcmpeq_single: - set_grs_a5a5 - set_fprs_a5a5 - # 1.0 == 1.0. - fldi1 fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bt .L0 - fail -.L0: - # 0.0 != 1.0. - fldi0 fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bf .L1 - fail -.L1: - # 1.0 != 0.0. - fldi1 fr0 - fldi0 fr1 - fcmp/eq fr0, fr1 - bf .L2 - fail -.L2: - # 2.0 != 1.0 - fldi1 fr0 - fadd fr0, fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bf .L3 - fail -.L3: - test_grs_a5a5 - assert_fpreg_i 2, fr0 - assert_fpreg_i 1, fr1 - test_fpr_a5a5 fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fcmpeq_double: - # 1.0 == 1.0 - set_grs_a5a5 - set_fprs_a5a5 - double_prec - fldi1 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bt .L10 - fail -.L10: - # 0.0 != 1.0 - fldi0 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bf .L11 - fail -.L11: - # 1.0 != 0.0 - fldi1 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bf .L12 - fail -.L12: - # 2.0 != 1.0 - fldi1 fr0 - single_prec - fadd fr0, fr0 - double_prec - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bf .L13 - fail -.L13: - test_grs_a5a5 - assert_dpreg_i 2, dr0 - assert_dpreg_i 1, dr2 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/fcmpgt.s b/sim/testsuite/sim/sh/fcmpgt.s deleted file mode 100644 index c6945ba..0000000 --- a/sim/testsuite/sim/sh/fcmpgt.s +++ /dev/null @@ -1,119 +0,0 @@ -# sh testcase for fcmpgt -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fcmpgt_single: - set_grs_a5a5 - set_fprs_a5a5 - # 1.0 !> 1.0. - fldi1 fr0 - fldi1 fr1 - fcmp/gt fr0, fr1 - bf .L0 - fail -.L0: - # 0.0 !> 1.0. - fldi0 fr0 - fldi1 fr1 - fcmp/gt fr0, fr1 - bt .L1 - fail -.L1: - # 1.0 > 0.0. - fldi1 fr0 - fldi0 fr1 - fcmp/gt fr0, fr1 - bf .L2 - fail -.L2: - # 2.0 > 1.0 - fldi1 fr0 - fadd fr0, fr0 - fldi1 fr1 - fcmp/gt fr0, fr1 - bf .L3 - fail -.L3: - test_grs_a5a5 - assert_fpreg_i 2, fr0 - assert_fpreg_i 1, fr1 - test_fpr_a5a5 fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fcmpgt_double: - # double precision tests. - set_grs_a5a5 - set_fprs_a5a5 - double_prec - # 1.0 !> 1.0. - fldi1 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/gt dr0, dr2 - bf .L10 - fail -.L10: - # 0.0 !> 1.0. - fldi0 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/gt dr0, dr2 - bt .L11 - fail -.L11: - # 1.0 > 0.0. - fldi1 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/gt dr0, dr2 - bf .L12 - fail -.L12: - # 2.0 > 1.0. - fldi1 fr0 - single_prec - fadd fr0, fr0 - double_prec - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/gt dr0, dr2 - bf .L13 - fail -.L13: - test_grs_a5a5 - assert_dpreg_i 2, dr0 - assert_dpreg_i 1, dr2 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fcnvds.s b/sim/testsuite/sim/sh/fcnvds.s deleted file mode 100644 index cffcb49..0000000 --- a/sim/testsuite/sim/sh/fcnvds.s +++ /dev/null @@ -1,56 +0,0 @@ -# sh testcase for fcnvds -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - double_prec - sz_64 - set_grs_a5a5 - set_fprs_a5a5 - mov.l ax, r0 - fmov @r0, dr0 - fcnvds dr0, fpul - fsts fpul, fr2 - - assert_dpreg_i 5, dr0 - single_prec - assert_fpreg_i 5, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - assertreg0 x - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - exit 0 - - .align 2 -x: .double 5.0 -ax: .long x - diff --git a/sim/testsuite/sim/sh/fcnvsd.s b/sim/testsuite/sim/sh/fcnvsd.s deleted file mode 100644 index 6592540..0000000 --- a/sim/testsuite/sim/sh/fcnvsd.s +++ /dev/null @@ -1,40 +0,0 @@ -# sh testcase for fcnvsd -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - set_grs_a5a5 - set_fprs_a5a5 - double_prec - fldi1 fr0 - flds fr0, fpul - fcnvsd fpul, dr2 - assert_dpreg_i 1, dr2 - - # Convert back. - fcnvds dr2, fpul - fsts fpul, fr1 - single_prec - assert_fpreg_i 1, fr1 - fcmp/eq fr0, fr1 - bt .L0 - fail -.L0: - test_grs_a5a5 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/fdiv.s b/sim/testsuite/sim/sh/fdiv.s deleted file mode 100644 index 629e774..0000000 --- a/sim/testsuite/sim/sh/fdiv.s +++ /dev/null @@ -1,91 +0,0 @@ -# sh testcase for fdiv -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fdiv_single: - # Single test - set_grs_a5a5 - set_fprs_a5a5 - single_prec - # 1.0 / 0.0 should be INF - # (and not crash the sim). - fldi0 fr0 - fldi1 fr1 - fdiv fr0, fr1 - assert_fpreg_x 0x7f800000, fr1 - - # 0.0 / 1.0 == 0.0. - fldi0 fr0 - fldi1 fr1 - fdiv fr1, fr0 - assert_fpreg_x 0, fr0 - - # 2.0 / 1.0 == 2.0. - fldi1 fr1 - fldi1 fr2 - fadd fr2, fr2 - fdiv fr1, fr2 - assert_fpreg_i 2, fr2 - - # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. - fldi1 fr1 - fldi1 fr2 - fadd fr2, fr2 - fdiv fr2, fr1 - # fr1 should contain 0.5. - fadd fr1, fr1 - assert_fpreg_i 1, fr1 - test_grs_a5a5 - assert_fpreg_i 2, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fdiv_double: - # Double test - set_grs_a5a5 - set_fprs_a5a5 - # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. - fldi1 fr1 - fldi1 fr2 - # This add must be in single precision. The rest must be in double. - fadd fr2, fr2 - double_prec - _s2d fr1, dr0 - _s2d fr2, dr2 - fdiv dr2, dr0 - # dr0 should contain 0.5. - # double it, expect 1.0. - fadd dr0, dr0 - assert_dpreg_i 1, dr0 - assert_dpreg_i 2, dr2 - test_grs_a5a5 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/fipr.s b/sim/testsuite/sim/sh/fipr.s deleted file mode 100644 index 6a949aa..0000000 --- a/sim/testsuite/sim/sh/fipr.s +++ /dev/null @@ -1,137 +0,0 @@ -# sh testcase for fipr $fvm, $fvn -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -initv0: - set_grs_a5a5 - set_fprs_a5a5 - # Load 1 into fr0. - fldi1 fr0 - # Load 2 into fr1. - fldi1 fr1 - fadd fr1, fr1 - # Load 4 into fr2. - fldi1 fr2 - fadd fr2, fr2 - fadd fr2, fr2 - # Load 8 into fr3. - fmov fr2, fr3 - fadd fr2, fr3 - -initv8: - fldi1 fr8 - fldi0 fr9 - fldi1 fr10 - fldi0 fr11 - - fipr fv0, fv8 -test1: - # Result will be in fr11. - assert_fpreg_i 1, fr0 - assert_fpreg_i 2, fr1 - assert_fpreg_i 4, fr2 - assert_fpreg_i 8, fr3 - assert_fpreg_x 0xa5a5a5a5, fr4 - assert_fpreg_x 0xa5a5a5a5, fr5 - assert_fpreg_x 0xa5a5a5a5, fr6 - assert_fpreg_x 0xa5a5a5a5, fr7 - assert_fpreg_i 1, fr8 - assert_fpreg_i 0, fr9 - assert_fpreg_i 1, fr10 - assert_fpreg_i 5, fr11 - assert_fpreg_x 0xa5a5a5a5, fr12 - assert_fpreg_x 0xa5a5a5a5, fr13 - assert_fpreg_x 0xa5a5a5a5, fr14 - assert_fpreg_x 0xa5a5a5a5, fr15 - - test_grs_a5a5 -test_infp: - # Test positive infinity - fldi0 fr11 - mov.l infp, r0 - lds r0, fpul - fsts fpul, fr0 - fipr fv0, fv8 - # fr11 should be plus infinity - assert_fpreg_x 0x7f800000, fr11 -test_infm: - # Test negitive infinity - fldi0 fr11 - mov.l infm, r0 - lds r0, fpul - fsts fpul, fr0 - fipr fv0, fv8 - # fr11 should be plus infinity - assert_fpreg_x 0xff800000, fr11 -test_qnanp: - # Test positive qnan - fldi0 fr11 - mov.l qnanp, r0 - lds r0, fpul - fsts fpul, fr0 - fipr fv0, fv8 - # fr11 should be plus qnan (or greater) - flds fr11, fpul - sts fpul, r1 - cmp/ge r0, r1 - bt .L0 - fail -.L0: -test_snanp: - # Test positive snan - fldi0 fr11 - mov.l snanp, r0 - lds r0, fpul - fsts fpul, fr0 - fipr fv0, fv8 - # fr11 should be plus snan (or greater) - flds fr11, fpul - sts fpul, r1 - cmp/ge r0, r1 - bt .L1 - fail -.L1: -.if 0 - # Handling of nan and inf not implemented yet. -test_qnanm: - # Test negantive qnan - fldi0 fr11 - mov.l qnanm, r0 - lds r0, fpul - fsts fpul, fr0 - fipr fv0, fv8 - # fr11 should be minus qnan (or less) - flds fr11, fpul - sts fpul, r1 - cmp/ge r1, r0 - bt .L2 - fail -.L2: -test_snanm: - # Test negative snan - fldi0 fr11 - mov.l snanm, r0 - lds r0, fpul - fsts fpul, fr0 - fipr fv0, fv8 - # fr11 should be minus snan (or less) - flds fr11, fpul - sts fpul, r1 - cmp/ge r1, r0 - bt .L3 - fail -.L3: -.endif - pass - exit 0 - - .align 2 -qnanp: .long 0x7f800001 -qnanm: .long 0xff800001 -snanp: .long 0x7fc00000 -snanm: .long 0xffc00000 -infp: .long 0x7f800000 -infm: .long 0xff800000 diff --git a/sim/testsuite/sim/sh/fldi0.s b/sim/testsuite/sim/sh/fldi0.s deleted file mode 100644 index 1e20058..0000000 --- a/sim/testsuite/sim/sh/fldi0.s +++ /dev/null @@ -1,37 +0,0 @@ -# sh testcase for fldi0 $frn -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fldi0_single: - set_grs_a5a5 - set_fprs_a5a5 - fldi0 fr0 - fldi0 fr2 - fldi0 fr4 - fldi0 fr6 - fldi0 fr8 - fldi0 fr10 - fldi0 fr12 - fldi0 fr14 - test_grs_a5a5 - assert_fpreg_i 0 fr0 - assert_fpreg_i 0 fr2 - assert_fpreg_i 0 fr4 - assert_fpreg_i 0 fr6 - assert_fpreg_i 0 fr8 - assert_fpreg_i 0 fr10 - assert_fpreg_i 0 fr12 - assert_fpreg_i 0 fr14 - assert_fpreg_x 0xa5a5a5a5 fr1 - assert_fpreg_x 0xa5a5a5a5 fr3 - assert_fpreg_x 0xa5a5a5a5 fr5 - assert_fpreg_x 0xa5a5a5a5 fr7 - assert_fpreg_x 0xa5a5a5a5 fr9 - assert_fpreg_x 0xa5a5a5a5 fr11 - assert_fpreg_x 0xa5a5a5a5 fr13 - assert_fpreg_x 0xa5a5a5a5 fr15 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fldi1.s b/sim/testsuite/sim/sh/fldi1.s deleted file mode 100644 index 1b7c170..0000000 --- a/sim/testsuite/sim/sh/fldi1.s +++ /dev/null @@ -1,38 +0,0 @@ -# sh testcase for fldi1 $frn -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fldi1_single: - set_grs_a5a5 - set_fprs_a5a5 - fldi1 fr1 - fldi1 fr3 - fldi1 fr5 - fldi1 fr7 - fldi1 fr9 - fldi1 fr11 - fldi1 fr13 - fldi1 fr15 - test_grs_a5a5 - assert_fpreg_x 0xa5a5a5a5 fr0 - assert_fpreg_x 0xa5a5a5a5 fr2 - assert_fpreg_x 0xa5a5a5a5 fr4 - assert_fpreg_x 0xa5a5a5a5 fr6 - assert_fpreg_x 0xa5a5a5a5 fr8 - assert_fpreg_x 0xa5a5a5a5 fr10 - assert_fpreg_x 0xa5a5a5a5 fr12 - assert_fpreg_x 0xa5a5a5a5 fr14 - assert_fpreg_i 1 fr1 - assert_fpreg_i 1 fr3 - assert_fpreg_i 1 fr5 - assert_fpreg_i 1 fr7 - assert_fpreg_i 1 fr9 - assert_fpreg_i 1 fr11 - assert_fpreg_i 1 fr13 - assert_fpreg_i 1 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/flds.s b/sim/testsuite/sim/sh/flds.s deleted file mode 100644 index 086b4ed..0000000 --- a/sim/testsuite/sim/sh/flds.s +++ /dev/null @@ -1,43 +0,0 @@ -# sh testcase for flds -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -flds_zero: - set_grs_a5a5 - set_fprs_a5a5 - fldi0 fr0 - flds fr0, fpul - fsts fpul, fr1 - fcmp/eq fr0, fr1 - bt flds_one - fail -flds_one: - fldi1 fr0 - flds fr0, fpul - fsts fpul, fr1 - fcmp/eq fr0, fr1 - bt .L0 - fail -.L0: - test_grs_a5a5 - assert_fpreg_i 1, fr0 - assert_fpreg_i 1, fr1 - test_fpr_a5a5 fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/float.s b/sim/testsuite/sim/sh/float.s deleted file mode 100644 index e5a3bc6..0000000 --- a/sim/testsuite/sim/sh/float.s +++ /dev/null @@ -1,149 +0,0 @@ -# sh testcase for float -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - -float_pos: - set_grs_a5a5 - set_fprs_a5a5 - single_prec - mov #3, r0 - lds r0, fpul - float fpul, fr2 - - # Check the result. - fldi1 fr0 - fldi1 fr1 - fadd fr0, fr1 - fadd fr0, fr1 - fcmp/eq fr1, fr2 - bt float_neg - fail - -float_neg: - mov #3, r0 - neg r0, r0 - lds r0, fpul - float fpul, fr2 - - # Check the result. - fldi1 fr0 - fldi1 fr1 - fadd fr0, fr1 - fadd fr0, fr1 - fneg fr1 - fcmp/eq fr1, fr2 - bt .L0 - fail -.L0: - assertreg0 -3 - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - assert_fpreg_i 1, fr0 - assert_fpreg_i -3, fr1 - assert_fpreg_i -3, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -double_pos: - set_grs_a5a5 - set_fprs_a5a5 - double_prec - mov #3, r0 - lds r0, fpul - float fpul, dr4 - - # check the result. - fldi1 fr0 - fldi1 fr1 - single_prec - fadd fr0, fr1 - fadd fr0, fr1 - double_prec - _s2d fr1, dr2 - fcmp/eq dr2, dr4 - bt double_neg - fail - -double_neg: - double_prec - mov #3, r0 - neg r0, r0 - lds r0, fpul - float fpul, dr4 - - # check the result. - fldi1 fr0 - fldi1 fr1 - single_prec - fadd fr0, fr1 - fadd fr0, fr1 - fneg fr1 - double_prec - _s2d fr1, dr2 - fcmp/eq dr2, dr4 - bt .L2 - fail -.L2: - assertreg0 -3 - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - single_prec - assert_fpreg_i 1, fr0 - assert_fpreg_i -3, fr1 - double_prec - assert_dpreg_i -3, dr2 - assert_dpreg_i -3, dr4 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fmac.s b/sim/testsuite/sim/sh/fmac.s deleted file mode 100644 index eba1da5..0000000 --- a/sim/testsuite/sim/sh/fmac.s +++ /dev/null @@ -1,98 +0,0 @@ -# sh testcase for fmac -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fmac_: - set_grs_a5a5 - set_fprs_a5a5 - # 0.0 * x + y = y. - - fldi0 fr0 - fldi1 fr1 - fldi1 fr2 - fmac fr0, fr1, fr2 - # check result. - fldi1 fr0 - fcmp/eq fr0, fr2 - bt .L0 - fail -.L0: - # x * y + 0.0 = x * y. - - fldi1 fr0 - fldi1 fr1 - fldi0 fr2 - # double it. - fadd fr1, fr2 - fmac fr0, fr1, fr2 - # check result. - fldi1 fr0 - fadd fr0, fr0 - fcmp/eq fr0, fr2 - bt .L1 - fail -.L1: - # x * 0.0 + y = y. - - fldi1 fr0 - fldi0 fr1 - fldi1 fr2 - fadd fr2, fr2 - fmac fr0, fr1, fr2 - # check result. - fldi1 fr0 - # double fr0. - fadd fr0, fr0 - fcmp/eq fr0, fr2 - bt .L2 - fail -.L2: - # x * 0.0 + 0.0 = 0.0 - - fldi1 fr0 - fadd fr0, fr0 - fldi0 fr1 - fldi0 fr2 - fmac fr0, fr1, fr2 - # check result. - fldi0 fr0 - fcmp/eq fr0, fr2 - bt .L3 - fail -.L3: - # 0.0 * x + 0.0 = 0.0. - - fldi0 fr0 - fldi1 fr1 - # double it. - fadd fr1, fr1 - fldi0 fr2 - fmac fr0, fr1, fr2 - # check result. - fldi0 fr0 - fcmp/eq fr0, fr2 - bt .L4 - fail -.L4: - test_grs_a5a5 - assert_fpreg_i 0, fr0 - assert_fpreg_i 2, fr1 - assert_fpreg_i 0, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fmov.s b/sim/testsuite/sim/sh/fmov.s deleted file mode 100644 index 29c51b5..0000000 --- a/sim/testsuite/sim/sh/fmov.s +++ /dev/null @@ -1,322 +0,0 @@ -# sh testcase for all fmov instructions -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - .macro init - fldi0 fr0 - fldi1 fr1 - fldi1 fr2 - fldi1 fr3 - .endm - - start - -fmov1: # Test fr -> fr. - set_grs_a5a5 - set_fprs_a5a5 - init - single_prec - sz_32 - fmov fr0, fr1 - # Ensure fr0 and fr1 are now equal. - fcmp/eq fr0, fr1 - bt fmov2 - fail - -fmov2: # Test dr -> dr. - init - double_prec - sz_64 - fmov dr0, dr2 - # Ensure dr0 and dr2 are now equal. - fcmp/eq dr0, dr2 - bt fmov3 - fail - -fmov3: # Test dr -> xd and xd -> dr. - init - sz_64 - fmov dr0, xd0 - # Ensure dr0 and xd0 are now equal. - fmov xd0, dr2 - fcmp/eq dr0, dr2 - bt fmov4 - fail - -fmov4: # Test xd -> xd. - init - sz_64 - double_prec - fmov dr0, xd0 - fmov xd0, xd2 - fmov xd2, dr2 - # Ensure dr0 and dr2 are now equal. - fcmp/eq dr0, dr2 - bt .L0 - fail - - # FIXME: test fmov.s fr -> @gr, fmov dr -> @gr - # FIXME: test fmov.s @gr -> fr, fmov @gr -> dr - # FIXME: test fmov.s @gr+ -> fr, fmov @gr+ -> dr - # FIXME: test fmov.s fr -> @-gr, fmov dr -> @-gr - # FIXME: test fmov.s @(r0,gr) -> fr, fmov @(r0,gr) -> dr - # FIXME: test fmov.s fr -> @(r0,gr), fmov dr -> @(r0,gr) - -.L0: - test_grs_a5a5 - sz_32 - single_prec - assert_fpreg_i 0, fr0 - assert_fpreg_i 1, fr1 - assert_fpreg_i 0, fr2 - assert_fpreg_i 1, fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fmov5: # Test fr -> @rn and @rn -> fr. - init - sz_32 - single_prec - # FIXME! Use a reserved memory location! - mov #40, r0 - shll8 r0 - fmov fr0, @r0 - fmov @r0, fr1 - fcmp/eq fr0, fr1 - bt fmov6 - fail - -fmov6: # Test dr -> @rn and @rn -> dr. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - fmov dr0, @r0 - fmov @r0, dr2 - fcmp/eq dr0, dr2 - bt fmov7 - fail - -fmov7: # Test xd -> @rn and @rn -> xd. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - fmov dr0, xd0 - fmov xd0, @r0 - fmov @r0, xd2 - fmov xd2, dr2 - fcmp/eq dr0, dr2 - bt fmov8 - fail - -fmov8: # Test fr -> @-rn. - init - sz_32 - single_prec - mov #40, r0 - shll8 r0 - # Preserve. - mov r0, r1 - fmov fr0, @-r0 - fmov @r0, fr2 - fcmp/eq fr0, fr2 - bt f8b - fail -f8b: # check pre-dec. - add #4, r0 - cmp/eq r0, r1 - bt fmov9 - fail - -fmov9: # Test dr -> @-rn. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r1 - fmov dr0, @-r0 - fmov @r0, dr2 - fcmp/eq dr0, dr2 - bt f9b - fail -f9b: # check pre-dec. - add #8, r0 - cmp/eq r0, r1 - bt fmov10 - fail - -fmov10: # Test xd -> @-rn. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r1 - fmov dr0, xd0 - fmov xd0, @-r0 - fmov @r0, xd2 - fmov xd2, dr2 - fcmp/eq dr0, dr2 - bt f10b - fail -f10b: # check pre-dec. - add #8, r0 - cmp/eq r0, r1 - bt fmov11 - fail - -fmov11: # Test @rn+ -> fr. - init - sz_32 - single_prec - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r1 - fmov fr0, @r0 - fmov @r0+, fr2 - fcmp/eq fr0, fr2 - bt f11b - fail -f11b: # check post-inc. - add #4, r1 - cmp/eq r0, r1 - bt fmov12 - fail - -fmov12: # Test @rn+ -> dr. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - # preserve r0. - mov r0, r1 - fmov dr0, @r0 - fmov @r0+, dr2 - fcmp/eq dr0, dr2 - bt f12b - fail -f12b: # check post-inc. - add #8, r1 - cmp/eq r0, r1 - bt fmov13 - fail - -fmov13: # Test @rn -> xd. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r1 - fmov dr0, xd0 - fmov xd0, @r0 - fmov @r0+, xd2 - fmov xd2, dr2 - fcmp/eq dr0, dr2 - bt f13b - fail -f13b: - add #8, r1 - cmp/eq r0, r1 - bt fmov14 - fail - -fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr. - init - sz_32 - single_prec - mov #40, r0 - shll8 r0 - mov #0, r1 - fmov fr0, @(r0, r1) - fmov @(r0, r1), fr1 - fcmp/eq fr0, fr1 - bt fmov15 - fail - -fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - mov #0, r1 - fmov dr0, @(r0, r1) - fmov @(r0, r1), dr2 - fcmp/eq dr0, dr2 - bt fmov16 - fail - -fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - mov #0, r1 - fmov dr0, xd0 - fmov xd0, @(r0, r1) - fmov @(r0, r1), xd2 - fmov xd2, dr2 - fcmp/eq dr0, dr2 - bt .L1 - fail -.L1: - assertreg0 0x2800 - assertreg 0, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - sz_32 - single_prec - assert_fpreg_i 0, fr0 - assert_fpreg_i 1, fr1 - assert_fpreg_i 0, fr2 - assert_fpreg_i 1, fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fmul.s b/sim/testsuite/sim/sh/fmul.s deleted file mode 100644 index 81a2545..0000000 --- a/sim/testsuite/sim/sh/fmul.s +++ /dev/null @@ -1,116 +0,0 @@ -# sh testcase for fmul -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - .macro init - fldi0 fr0 - fldi1 fr1 - fldi1 fr2 - fadd fr2, fr2 - .endm - - start -fmul_single: - set_grs_a5a5 - set_fprs_a5a5 - # 0.0 * 0.0 = 0.0. - init - fmul fr0, fr0 - assert_fpreg_i 0, fr0 - - # 0.0 * 1.0 = 0.0. - init - fmul fr1, fr0 - assert_fpreg_i 0, fr0 - - # 1.0 * 0.0 = 0.0. - init - fmul fr0, fr1 - assert_fpreg_i 0, fr1 - - # 1.0 * 1.0 = 1.0. - init - fmul fr1, fr1 - assert_fpreg_i 1, fr1 - - # 2.0 * 1.0 = 2.0. - init - fmul fr2, fr1 - assert_fpreg_i 2, fr1 - - test_grs_a5a5 - assert_fpreg_i 0, fr0 - assert_fpreg_i 2, fr1 - assert_fpreg_i 2, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - .macro dinit - fldi0 fr0 - fldi1 fr2 - fldi1 fr4 - single_prec - fadd fr4, fr4 - double_prec - _s2d fr0, dr0 - _s2d fr2, dr2 - _s2d fr4, dr4 - .endm - -fmul_double: - double_prec - # 0.0 * 0.0 = 0.0. - dinit - fmul dr0, dr0 - assert_dpreg_i 0, dr0 - - # 0.0 * 1.0 = 0.0. - dinit - fmul dr2, dr0 - assert_dpreg_i 0, dr0 - - # 1.0 * 0.0 = 0.0. - dinit - fmul dr0, dr2 - assert_dpreg_i 0, dr2 - - # 1.0 * 1.0 = 1.0. - dinit - fmul dr2, dr2 - assert_dpreg_i 1, dr2 - - # 2.0 * 1.0 = 2.0. - dinit - fmul dr4, dr2 - assert_dpreg_i 2, dr2 - - test_grs_a5a5 - assert_dpreg_i 0, dr0 - assert_dpreg_i 2, dr2 - assert_dpreg_i 2, dr4 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fneg.s b/sim/testsuite/sim/sh/fneg.s deleted file mode 100644 index dd5fe5d..0000000 --- a/sim/testsuite/sim/sh/fneg.s +++ /dev/null @@ -1,112 +0,0 @@ -# sh testcase for fneg -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fneg_single: - set_grs_a5a5 - set_fprs_a5a5 - # neg(0.0) = 0.0. - fldi0 fr0 - fldi0 fr1 - fneg fr0 - fcmp/eq fr0, fr1 - bt .L0 - fail -.L0: - # neg(1.0) = fsub(0,1) - fldi1 fr0 - fneg fr0 - fldi0 fr1 - fldi1 fr2 - fsub fr2, fr1 - fcmp/eq fr0, fr1 - bt .L1 - fail -.L1: - # neg(neg(1.0)) = 1.0. - fldi1 fr0 - fldi1 fr1 - fneg fr0 - fneg fr0 - fcmp/eq fr0, fr1 - bt .L2 - fail -.L2: - test_grs_a5a5 - assert_fpreg_i 1, fr0 - assert_fpreg_i 1, fr1 - assert_fpreg_i 1, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fneg_double: - set_grs_a5a5 - set_fprs_a5a5 - double_prec - # neg(0.0) = 0.0. - fldi0 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fneg dr0 - fcmp/eq dr0, dr2 - bt .L10 - fail -.L10: - # neg(1.0) = fsub(0,1) - fldi1 fr0 - _s2d fr0, dr0 - fneg dr0 - fldi0 fr2 - fldi1 fr3 - single_prec - fsub fr3, fr2 - double_prec - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bt .L11 - fail -.L11: - # neg(neg(1.0)) = 1.0. - fldi1 fr0 - _s2d fr0, dr0 - fldi1 fr2 - _s2d fr2, dr2 - fneg dr2 - fneg dr2 - fcmp/eq dr0, dr2 - bt .L12 - fail -.L12: - test_grs_a5a5 - assert_dpreg_i 1, dr0 - assert_dpreg_i 1, dr2 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fpchg.s b/sim/testsuite/sim/sh/fpchg.s deleted file mode 100644 index 47ba03b..0000000 --- a/sim/testsuite/sim/sh/fpchg.s +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for fpchg -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - set_grs_a5a5 - set_fprs_a5a5 - sts fpscr, r0 - assertreg0 0 - fpchg - sts fpscr, r0 - assertreg0 0x80000 - fpchg - sts fpscr, r0 - assertreg0 0 - fpchg - sts fpscr, r0 - assertreg0 0x80000 - fpchg - sts fpscr, r0 - assertreg0 0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - test_fprs_a5a5 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/frchg.s b/sim/testsuite/sim/sh/frchg.s deleted file mode 100644 index c5dc099..0000000 --- a/sim/testsuite/sim/sh/frchg.s +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for frchg -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - set_grs_a5a5 - set_fprs_a5a5 - sts fpscr, r0 - assertreg0 0 - frchg - sts fpscr, r0 - assertreg0 0x200000 - frchg - sts fpscr, r0 - assertreg0 0 - frchg - sts fpscr, r0 - assertreg0 0x200000 - frchg - sts fpscr, r0 - assertreg0 0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - test_fprs_a5a5 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fsca.s b/sim/testsuite/sim/sh/fsca.s deleted file mode 100644 index 90df6c9..0000000 --- a/sim/testsuite/sim/sh/fsca.s +++ /dev/null @@ -1,97 +0,0 @@ -# sh testcase for fsca -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fsca: - set_grs_a5a5 - set_fprs_a5a5 - # Start with angle zero - mov.l zero, r0 - lds r0, fpul - fsca fpul, dr2 - assert_fpreg_i 0, fr2 - assert_fpreg_i 1, fr3 - - mov.l plus_90, r0 - lds r0, fpul - fsca fpul, dr2 - assert_fpreg_i 1, fr2 - assert_fpreg_i 0, fr3 - - mov.l plus_180, r0 - lds r0, fpul - fsca fpul, dr2 - assert_fpreg_i 0, fr2 - assert_fpreg_i -1, fr3 - - mov.l plus_270, r0 - lds r0, fpul - fsca fpul, dr2 - assert_fpreg_i -1, fr2 - assert_fpreg_i 0, fr3 - - mov.l plus_360, r0 - lds r0, fpul - fsca fpul, dr2 - assert_fpreg_i 0, fr2 - assert_fpreg_i 1, fr3 - - mov.l minus_90, r0 - lds r0, fpul - fsca fpul, dr2 - assert_fpreg_i -1, fr2 - assert_fpreg_i 0, fr3 - - mov.l minus_180, r0 - lds r0, fpul - fsca fpul, dr2 - assert_fpreg_i 0, fr2 - assert_fpreg_i -1, fr3 - - mov.l minus_270, r0 - lds r0, fpul - fsca fpul, dr2 - assert_fpreg_i 1, fr2 - assert_fpreg_i 0, fr3 - - mov.l minus_360, r0 - lds r0, fpul - fsca fpul, dr2 - assert_fpreg_i 0, fr2 - assert_fpreg_i 1, fr3 - - assertreg0 0xffff0000 - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - test_fpr_a5a5 fr0 - test_fpr_a5a5 fr1 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - pass - exit 0 - - .align 2 -zero: .long 0 -one_bitty: .long 1 -plus_90: .long 0x04000 -plus_180: .long 0x08000 -plus_270: .long 0x0c000 -plus_360: .long 0x10000 -minus_90: .long 0xffffc000 -minus_180: .long 0xffff8000 -minus_270: .long 0xffff4000 -minus_360: .long 0xffff0000 -minus_1_bitty: .long 0xffffffff diff --git a/sim/testsuite/sim/sh/fschg.s b/sim/testsuite/sim/sh/fschg.s deleted file mode 100644 index 7454787..0000000 --- a/sim/testsuite/sim/sh/fschg.s +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for fschg -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - set_grs_a5a5 - set_fprs_a5a5 - sts fpscr, r0 - assertreg0 0 - fschg - sts fpscr, r0 - assertreg0 0x100000 - fschg - sts fpscr, r0 - assertreg0 0 - fschg - sts fpscr, r0 - assertreg0 0x100000 - fschg - sts fpscr, r0 - assertreg0 0 - - set_greg 0xa5a5a5a5 r0 - test_grs_a5a5 - test_fprs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fsqrt.s b/sim/testsuite/sim/sh/fsqrt.s deleted file mode 100644 index cb61bcf..0000000 --- a/sim/testsuite/sim/sh/fsqrt.s +++ /dev/null @@ -1,120 +0,0 @@ -# sh testcase for fsqrt -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fsqrt_single: - set_grs_a5a5 - set_fprs_a5a5 - # sqrt(0.0) = 0.0. - fldi0 fr0 - fsqrt fr0 - fldi0 fr1 - fcmp/eq fr0, fr1 - bt .L0 - fail -.L0: - # sqrt(1.0) = 1.0. - fldi1 fr0 - fsqrt fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bt .L1 - fail -.L1: - # sqrt(4.0) = 2.0 - fldi1 fr0 - # Double it. - fadd fr0, fr0 - # Double it again. - fadd fr0, fr0 - fsqrt fr0 - fldi1 fr1 - # Double it. - fadd fr1, fr1 - fcmp/eq fr0, fr1 - bt .L2 - fail -.L2: - test_grs_a5a5 - assert_fpreg_i 2, fr0 - assert_fpreg_i 2, fr1 - test_fpr_a5a5 fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fsqrt_double: - double_prec - set_grs_a5a5 - set_fprs_a5a5 - # sqrt(0.0) = 0.0. - fldi0 fr0 - _s2d fr0, dr0 - fsqrt dr0 - fldi0 fr2 - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bt .L10 - fail -.L10: - # sqrt(1.0) = 1.0. - fldi1 fr0 - _s2d fr0, dr0 - fsqrt dr0 - fldi1 fr2 - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bt .L11 - fail -.L11: - # sqrt(4.0) = 2.0. - fldi1 fr0 - # Double it. - single_prec - fadd fr0, fr0 - # Double it again. - fadd fr0, fr0 - double_prec - _s2d fr0, dr0 - fsqrt dr0 - fldi1 fr2 - # Double it. - single_prec - fadd fr2, fr2 - double_prec - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bt .L12 - fail -.L12: - test_grs_a5a5 - assert_dpreg_i 2, dr0 - assert_dpreg_i 2, dr2 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fsrra.s b/sim/testsuite/sim/sh/fsrra.s deleted file mode 100644 index fdd2235..0000000 --- a/sim/testsuite/sim/sh/fsrra.s +++ /dev/null @@ -1,62 +0,0 @@ -# sh testcase for fsrra -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fsrra_single: - set_grs_a5a5 - set_fprs_a5a5 - # 1/sqrt(0.0) = +infinity. - fldi0 fr0 - fsrra fr0 - assert_fpreg_x 0x7f800000, fr0 - - # 1/sqrt(1.0) = 1.0. - fldi1 fr0 - fsrra fr0 - assert_fpreg_i 1, fr0 - - # 1/sqrt(4.0) = 1/2.0 - fldi1 fr0 - # Double it. - fadd fr0, fr0 - # Double it again. - fadd fr0, fr0 - fsrra fr0 - fldi1 fr2 - # Double it. - fadd fr2, fr2 - fldi1 fr1 - # Divide - fdiv fr2, fr1 - fcmp/eq fr0, fr1 - bt .L2 - fail -.L2: - # Double-check (pun intended) - fadd fr0, fr0 - assert_fpreg_i 1, fr0 - fadd fr1, fr1 - assert_fpreg_i 1, fr1 - - # And make sure the rest of the regs are un-affected. - assert_fpreg_i 2, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - test_grs_a5a5 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fsub.s b/sim/testsuite/sim/sh/fsub.s deleted file mode 100644 index dfe9172..0000000 --- a/sim/testsuite/sim/sh/fsub.s +++ /dev/null @@ -1,136 +0,0 @@ -# sh testcase for fsub -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fsub_single: - set_grs_a5a5 - set_fprs_a5a5 - # 0.0 - 0.0 = 0.0. - fldi0 fr0 - fldi0 fr1 - fsub fr0, fr1 - fldi0 fr2 - fcmp/eq fr1, fr2 - bt .L0 - fail -.L0: - # 1.0 - 0.0 = 1.0. - fldi0 fr0 - fldi1 fr1 - fsub fr0, fr1 - fldi1 fr2 - fcmp/eq fr1, fr2 - bt .L1 - fail -.L1: - # 1.0 - 1.0 = 0.0. - fldi1 fr0 - fldi1 fr1 - fsub fr0, fr1 - fldi0 fr2 - fcmp/eq fr1, fr2 - bt .L2 - fail -.L2: - # 0.0 - 1.0 = -1.0. - fldi1 fr0 - fldi0 fr1 - fsub fr0, fr1 - fldi1 fr2 - fneg fr2 - fcmp/eq fr1, fr2 - bt .L3 - fail -.L3: - test_grs_a5a5 - assert_fpreg_i 1, fr0 - assert_fpreg_i -1, fr1 - assert_fpreg_i -1, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fsub_double: - set_grs_a5a5 - set_fprs_a5a5 - double_prec - # 0.0 - 0.0 = 0.0. - fldi0 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fsub dr0, dr2 - fldi0 fr4 - _s2d fr4, dr4 - fcmp/eq dr2, dr4 - bt .L10 - fail -.L10: - # 1.0 - 0.0 = 1.0. - fldi0 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fsub dr0, dr2 - fldi1 fr4 - _s2d fr4, dr4 - fcmp/eq dr2, dr4 - bt .L11 - fail -.L11: - # 1.0 - 1.0 = 0.0. - fldi1 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fsub dr0, dr2 - fldi0 fr4 - _s2d fr4, dr4 - fcmp/eq dr2, dr4 - bt .L12 - fail -.L12: - # 0.0 - 1.0 = -1.0. - fldi1 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fsub dr0, dr2 - fldi1 fr4 - single_prec - fneg fr4 - double_prec - _s2d fr4, dr4 - fcmp/eq dr2, dr4 - bt .L13 - fail -.L13: - test_grs_a5a5 - assert_dpreg_i 1, dr0 - assert_dpreg_i -1, dr2 - assert_dpreg_i -1, dr4 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/ftrc.s b/sim/testsuite/sim/sh/ftrc.s deleted file mode 100644 index 25e33be..0000000 --- a/sim/testsuite/sim/sh/ftrc.s +++ /dev/null @@ -1,156 +0,0 @@ -# sh testcase for ftrc -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -ftrc_single: - set_grs_a5a5 - set_fprs_a5a5 - # ftrc(0.0) = 0. - fldi0 fr0 - ftrc fr0, fpul - # check results. - mov #0, r0 - sts fpul, r1 - cmp/eq r0, r1 - bt .L0 - fail -.L0: - # ftrc(1.5) = 1. - fldi1 fr0 - fldi1 fr1 - fldi1 fr2 - # double it. - fadd fr2, fr2 - # form the fraction. - fdiv fr2, fr1 - fadd fr1, fr0 - # now we've got 1.5 in fr0. - ftrc fr0, fpul - # check results. - mov #1, r0 - sts fpul, r1 - cmp/eq r0, r1 - bt .L1 - fail -.L1: - # ftrc(-1.5) = -1. - fldi1 fr0 - fneg fr0 - fldi1 fr1 - fldi1 fr2 - # double it. - fadd fr2, fr2 - # form the fraction. - fdiv fr2, fr1 - fneg fr1 - # -1 + -0.5 = -1.5. - fadd fr1, fr0 - # now we've got 1.5 in fr0. - ftrc fr0, fpul - # check results. - mov #1, r0 - neg r0, r0 - sts fpul, r1 - cmp/eq r0, r1 - bt ftrc_double - fail - -ftrc_double: - double_prec - # ftrc(0.0) = 0. - fldi0 fr0 - _s2d fr0, dr0 - ftrc dr0, fpul - # check results. - mov #0, r0 - sts fpul, r1 - cmp/eq r0, r1 - bt .L10 - fail -.L10: - # ftrc(1.5) = 1. - fldi1 fr0 - fldi1 fr2 - fldi1 fr4 - # double it. - single_prec - fadd fr4, fr4 - # form 0.5. - fdiv fr4, fr2 - fadd fr2, fr0 - double_prec - # now we've got 1.5 in fr0, so do some single->double - # conversions and perform the ftrc. - _s2d fr0, dr0 - _s2d fr2, dr2 - _s2d fr4, dr4 - ftrc dr0, fpul - - # check results. - mov #1, r0 - sts fpul, r1 - cmp/eq r0, r1 - bt .L11 - fail -.L11: - # ftrc(-1.5) = -1. - fldi1 fr0 - fneg fr0 - fldi1 fr2 - fldi1 fr4 - single_prec - # double it. - fadd fr4, fr4 - # form the fraction. - fdiv fr4, fr2 - fneg fr2 - # -1 + -0.5 = -1.5. - fadd fr2, fr0 - double_prec - # now we've got 1.5 in fr0, so do some single->double - # conversions and perform the ftrc. - _s2d fr0, dr0 - _s2d fr2, dr2 - _s2d fr4, dr4 - ftrc dr0, fpul - - # check results. - mov #1, r0 - neg r0, r0 - sts fpul, r1 - cmp/eq r0, r1 - bt .L12 - fail -.L12: - assertreg0 -1 - assertreg -1, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - assert_dpreg_i 2, dr4 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/ldrc.s b/sim/testsuite/sim/sh/ldrc.s deleted file mode 100644 index 4441313..0000000 --- a/sim/testsuite/sim/sh/ldrc.s +++ /dev/null @@ -1,118 +0,0 @@ -# sh testcase for ldrc, strc -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -setrc_imm: - set_grs_a5a5 - # Test setrc - # - ldrs lstart - ldre lend - setrc #0xff - get_sr r1 - shlr16 r1 - set_greg 0xfff, r0 - and r0, r1 - assertreg 0xff, r1 - - stc rs, r0 ! rs unchanged - assertreg0 lstart - stc re, r0 ! re unchanged - assertreg0 lend - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - - test_grs_a5a5 - -setrc_reg: - set_grs_a5a5 - # Test setrc - # - ldrs lstart - ldre lend - set_greg 0xfff, r0 - setrc r0 - get_sr r1 - shlr16 r1 - set_greg 0xfff, r0 - and r0, r1 - assertreg 0xfff, r1 - - stc rs, r0 ! rs unchanged - assertreg0 lstart - stc re, r0 ! re unchanged - assertreg0 lend - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - - test_grs_a5a5 - - bra ldrc_imm - - .global lstart - .align 2 -lstart: nop - nop - nop - nop - .global lend - .align 2 -lend: nop - nop - nop - nop - -ldrc_imm: - set_grs_a5a5 - # Test ldrc - setrc #0x0 ! zero rc - ldrc #0xa5 - get_sr r1 - shlr16 r1 - set_greg 0xfff, r0 - and r0, r1 - assertreg 0xa5, r1 - stc rs, r0 ! rs unchanged - assertreg0 lstart - stc re, r0 - assertreg0 lend+1 ! bit 0 set in re - - # fix up re for next test - dt r0 ! Ugh! No DEC insn! - ldc r0, re - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - - test_grs_a5a5 - -ldrc_reg: - set_grs_a5a5 - # Test ldrc - setrc #0x0 ! zero rc - set_greg 0xa5a, r0 - ldrc r0 - get_sr r1 - shlr16 r1 - set_greg 0xfff, r0 - and r0, r1 - assertreg 0xa5a, r1 - stc rs, r0 ! rs unchanged - assertreg0 lstart - stc re, r0 - assertreg0 lend+1 ! bit 0 set in re - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - - test_grs_a5a5 - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/loop.s b/sim/testsuite/sim/sh/loop.s deleted file mode 100644 index 6040519..0000000 --- a/sim/testsuite/sim/sh/loop.s +++ /dev/null @@ -1,311 +0,0 @@ -# sh testcase for loop control -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start -loop1: - set_grs_a5a5 - - ldrs Loop1_start0+8 - ldre Loop1_start0+4 - setrc #5 -Loop1_start0: - add #1, r1 ! Before loop - # Loop should execute one instruction five times. -Loop1_begin: - add #1, r1 ! Within loop -Loop1_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before) - assertreg 0xa5a5a5a5+8, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop2: - set_grs_a5a5 - - ldrs Loop2_start0+6 - ldre Loop2_start0+4 - setrc #5 -Loop2_start0: - add #1, r1 ! Before loop - # Loop should execute two instructions five times. -Loop2_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loop2_end: - add #3, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 14 (ten in loop, three after, one before) - assertreg 0xa5a5a5a5+14, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop3: - set_grs_a5a5 - - ldrs Loop3_start0+4 - ldre Loop3_start0+4 - setrc #5 -Loop3_start0: - add #1, r1 ! Before loop - # Loop should execute three instructions five times. -Loop3_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loop3_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before) - assertreg 0xa5a5a5a5+18, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop4: - set_grs_a5a5 - - ldrs Loop4_begin - ldre Loop4_last3+4 - setrc #5 - add #1, r1 ! Before loop - # Loop should execute four instructions five times. -Loop4_begin: -Loop4_last3: - add #1, r1 ! Within loop -Loop4_last2: - add #1, r1 ! Within loop -Loop4_last1: - add #1, r1 ! Within loop -Loop4_last: - add #1, r1 ! Within loop -Loop4_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 23 (20 in loop, two after, one before) - assertreg 0xa5a5a5a5+23, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop5: - set_grs_a5a5 - - ldrs Loop5_begin - ldre Loop5_last3+4 - setrc #5 - add #1, r1 ! Before loop - # Loop should execute five instructions five times. -Loop5_begin: - add #1, r1 ! Within loop -Loop5_last3: - add #1, r1 ! Within loop -Loop5_last2: - add #1, r1 ! Within loop -Loop5_last1: - add #1, r1 ! Within loop -Loop5_last: - add #1, r1 ! Within loop -Loop5_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 28 (25 in loop, two after, one before) - assertreg 0xa5a5a5a5+28, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loopn: - set_grs_a5a5 - - ldrs Loopn_begin - ldre Loopn_last3+4 - setrc #5 - add #1, r1 ! Before loop - # Loop should execute n instructions five times. -Loopn_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loopn_last3: - add #1, r1 ! Within loop -Loopn_last2: - add #1, r1 ! Within loop -Loopn_last1: - add #1, r1 ! Within loop -Loopn_last: - add #1, r1 ! Within loop -Loopn_end: - add #3, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 64 (60 in loop, three after, one before) - assertreg 0xa5a5a5a5+64, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop1e: - set_grs_a5a5 - - ldrs Loop1e_begin - ldre Loop1e_last - ldrc #5 - add #1, r1 ! Before loop - # Loop should execute one instruction five times. -Loop1e_begin: -Loop1e_last: - add #1, r1 ! Within loop -Loop1e_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before) - assertreg 0xa5a5a5a5+8, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop2e: - set_grs_a5a5 - - ldrs Loop2e_begin - ldre Loop2e_last - ldrc #5 - add #1, r1 ! Before loop - # Loop should execute two instructions five times. -Loop2e_begin: - add #1, r1 ! Within loop -Loop2e_last: - add #1, r1 ! Within loop -Loop2e_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 13 (ten in loop, two after, one before) - assertreg 0xa5a5a5a5+13, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop3e: - set_grs_a5a5 - - ldrs Loop3e_begin - ldre Loop3e_last - ldrc #5 - add #1, r1 ! Before loop - # Loop should execute three instructions five times. -Loop3e_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loop3e_last: - add #1, r1 ! Within loop -Loop3e_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before) - assertreg 0xa5a5a5a5+18, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop4e: - set_grs_a5a5 - - ldrs Loop4e_begin - ldre Loop4e_last - ldrc #5 - add #1, r1 ! Before loop - # Loop should execute four instructions five times. -Loop4e_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loop4e_last: - add #1, r1 ! Within loop -Loop4e_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 23 (twenty in loop, two after, one before) - assertreg 0xa5a5a5a5+23, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop5e: - set_grs_a5a5 - - ldrs Loop5e_begin - ldre Loop5e_last - ldrc #5 - add #1, r1 ! Before loop - # Loop should execute five instructions five times. -Loop5e_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loop5e_last: - add #1, r1 ! Within loop -Loop5e_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 28 (twenty five in loop, two after, one before) - assertreg 0xa5a5a5a5+28, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop_n_e: - set_grs_a5a5 - - ldrs Loop_n_e_begin - ldre Loop_n_e_last - ldrc #5 - add #1, r1 ! Before loop - # Loop should execute n instructions five times. -Loop_n_e_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loop_n_e_last: - add #1, r1 ! Within loop -Loop_n_e_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 48 (forty five in loop, two after, one before) - assertreg 0xa5a5a5a5+48, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - - pass - - exit 0 - diff --git a/sim/testsuite/sim/sh/macl.s b/sim/testsuite/sim/sh/macl.s deleted file mode 100644 index 39b3b7d..0000000 --- a/sim/testsuite/sim/sh/macl.s +++ /dev/null @@ -1,54 +0,0 @@ -# sh testcase for mac.l -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - # force S-bit clear - clrs - -init: - # Prime {MACL, MACH} to #1. - mov #1, r0 - dmulu.l r0, r0 - - # Set up addresses. - mov.l pfour00, r0 ! 85 - mov.l pfour12, r1 ! 17 - -test: - mac.l @r0+, @r1+ - -check: - # Check result. - assert_sreg 0, mach - assert_sreg 85*17+1, macl - - # Ensure post-increment occurred. - assertreg0 four00+4 - assertreg four12+4, r1 - -doubleinc: - mov.l pfour00, r0 - mac.l @r0+, @r0+ - assertreg0 four00+8 - - - pass - exit 0 - - .align 1 -four00: - .long 85 - .long 2 -four12: - .long 17 - .long 3 - - .align 2 -pfour00: - .long four00 -pfour12: - .long four12 diff --git a/sim/testsuite/sim/sh/macw.s b/sim/testsuite/sim/sh/macw.s deleted file mode 100644 index 7e3ebc0..0000000 --- a/sim/testsuite/sim/sh/macw.s +++ /dev/null @@ -1,56 +0,0 @@ -# sh testcase for mac.w -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - - # Prime {MACL, MACH} to #1. - mov #1, r0 - dmulu.l r0, r0 - - # Set up addresses. - mov.l pfour00, r0 ! 85 - mov.l pfour12, r1 ! 17 - -test: - mac.w @r0+, @r1+ ! MAC = 85 * 17 + 1 - -check: - # Check result. - assert_sreg 0, mach - assert_sreg 85*17+1, macl - - # Ensure post-increment occurred. - assertreg0 four00+2 - assertreg four12+2, r1 - -doubleinc: - mov.l pfour00, r0 - mac.w @r0+, @r0+ - assertreg0 four00+4 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - - test_grs_a5a5 - - pass - exit 0 - - .align 2 -four00: - .word 85 - .word 2 -four12: - .word 17 - .word 3 - - -pfour00: - .long four00 -pfour12: - .long four12 diff --git a/sim/testsuite/sim/sh/mov.s b/sim/testsuite/sim/sh/mov.s deleted file mode 100644 index 37fef51..0000000 --- a/sim/testsuite/sim/sh/mov.s +++ /dev/null @@ -1,118 +0,0 @@ -# sh testcase for all mov.[bwl] instructions -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - .align 2 -_lsrc: .long 0x55555555 -_wsrc: .long 0x55550000 -_bsrc: .long 0x55000000 - - .align 2 -_ldst: .long 0 -_wdst: .long 0 -_bdst: .long 0 - - - start - -movb_disp12_reg: # Test 8-bit @(disp12,gr) -> gr - set_grs_a5a5 - mov.l bsrc, r1 - add #-111, r1 - add #-111, r1 - add #-111, r1 - add #-111, r1 - mov.b @(444,r1), r2 - - assertreg _bsrc-444, r1 - assertreg 0x55, r2 - -movb_reg_disp12: # Test 8-bit gr -> @(disp12,gr) - set_grs_a5a5 - mov.l bdst, r1 - add #-111, r1 - add #-111, r1 - add #-111, r1 - add #-111, r1 - mov.b r2, @(444,r1) - - assertreg _bdst-444, r1 - assertmem _bdst, 0xa5000000 - -movw_disp12_reg: # Test 16-bit @(disp12,gr) -> gr - set_grs_a5a5 - mov.l wsrc, r1 - add #-111, r1 - add #-111, r1 - add #-111, r1 - add #-111, r1 - mov.w @(444,r1), r2 - - assertreg _wsrc-444, r1 - assertreg 0x5555, r2 - -movw_reg_disp12: # Test 16-bit gr -> @(disp12,gr) - set_grs_a5a5 - mov.l wdst, r1 - add #-111, r1 - add #-111, r1 - add #-111, r1 - add #-111, r1 - mov.w r2, @(444,r1) - - assertreg _wdst-444, r1 - assertmem _wdst, 0xa5a50000 - -movl_disp12_reg: # Test 32-bit @(disp12,gr) -> gr - set_grs_a5a5 - mov.l lsrc, r1 - add #-111, r1 - add #-111, r1 - add #-111, r1 - add #-111, r1 - mov.l @(444,r1), r2 - - assertreg _lsrc-444, r1 - assertreg 0x55555555, r2 - -movl_reg_disp12: # Test 32-bit gr -> @(disp12,gr) - set_grs_a5a5 - mov.l ldst, r1 - add #-111, r1 - add #-111, r1 - add #-111, r1 - add #-111, r1 - mov.l r2, @(444,r1) - - assertreg _ldst-444, r1 - assertmem _ldst, 0xa5a5a5a5 - - test_gr_a5a5 r0 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - -lsrc: .long _lsrc -wsrc: .long _wsrc -bsrc: .long _bsrc - -ldst: .long _ldst -wdst: .long _wdst -bdst: .long _bdst - diff --git a/sim/testsuite/sim/sh/movi.s b/sim/testsuite/sim/sh/movi.s deleted file mode 100644 index e54f4f6..0000000 --- a/sim/testsuite/sim/sh/movi.s +++ /dev/null @@ -1,76 +0,0 @@ -# sh testcase for all mov <#imm> instructions -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - -mov_i_reg: # Test - set_grs_a5a5 - mov #-0x55, r1 - - assertreg 0xffffffab, r1 - - test_gr_a5a5 r0 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -movi20_reg: # Test - set_grs_a5a5 - movi20 #-0x55555,r1 - - assertreg 0xfffaaaab, r1 - - test_gr_a5a5 r0 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -movi20s_reg: # Test << 8 - set_grs_a5a5 - movi20s #-0x5555500,r1 - - assertreg 0xfaaaab00, r1 - - test_gr_a5a5 r0 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - - diff --git a/sim/testsuite/sim/sh/movli.s b/sim/testsuite/sim/sh/movli.s deleted file mode 100644 index eacd103..0000000 --- a/sim/testsuite/sim/sh/movli.s +++ /dev/null @@ -1,55 +0,0 @@ -# sh testcase for movli -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -x: .long 1 -y: .long 2 -z: .long 3 - - start - set_grs_a5a5 - mov.l xptr, r1 - mov.l yptr, r2 - # Move linked/conditional, x to y - movli.l @r1, r0 - movco.l r0, @r2 - - # Check result. - assertreg0 1 - mov.l yptr, r1 - mov.l @r1, r2 - assertreg 1, r2 - - # Now attempt an unlinked move of r0 to z - mov.l zptr, r1 - movco.l r0, @r1 - - # Check that z is unchanged. - mov.l zptr, r1 - mov.l @r1, r2 - assertreg 3, r2 - - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - exit 0 - - .align 2 -xptr: .long x -yptr: .long y -zptr: .long z diff --git a/sim/testsuite/sim/sh/movua.s b/sim/testsuite/sim/sh/movua.s deleted file mode 100644 index fa12fe5..0000000 --- a/sim/testsuite/sim/sh/movua.s +++ /dev/null @@ -1,197 +0,0 @@ -# sh testcase for movua -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start -movua_1: - set_grs_a5a5 - mov.l srcp, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x03020100 -.else - assertreg0 0x00010203 -.endif - - add #1, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x04030201 -.else - assertreg0 0x01020304 -.endif - - add #1, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x05040302 -.else - assertreg0 0x02030405 -.endif - - add #1, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x06050403 -.else - assertreg0 0x03040506 -.endif - - add #1, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x07060504 -.else - assertreg0 0x04050607 -.endif - - add #1, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x08070605 -.else - assertreg0 0x05060708 -.endif - - add #1, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x09080706 -.else - assertreg0 0x06070809 -.endif - - add #1, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x0a090807 -.else - assertreg0 0x0708090a -.endif - - add #1, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x0b0a0908 -.else - assertreg0 0x08090a0b -.endif - - add #1, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x0c0b0a09 -.else - assertreg0 0x090a0b0c -.endif - - add #1, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x0d0c0b0a -.else - assertreg0 0x0a0b0c0d -.endif - - add #1, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x0e0d0c0b -.else - assertreg0 0x0b0c0d0e -.endif - - add #1, r1 - movua.l @r1, r0 -.ifdef LITTLE - assertreg0 0x0f0e0d0c -.else - assertreg0 0x0c0d0e0f -.endif - - assertreg src+12, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - bra movua_4: - nop - - .align 0 -src: .byte 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - .align 2 -srcp: .long src - -movua_4: - set_grs_a5a5 - mov.l srcp2, r1 - movua.l @r1+, r0 -.ifdef LITTLE - assertreg0 0x03020100 -.else - assertreg0 0x00010203 -.endif - assertreg src+4, r1 - - mov.l srcp2, r1 - add #1, r1 - movua.l @r1+, r0 -.ifdef LITTLE - assertreg0 0x04030201 -.else - assertreg0 0x01020304 -.endif - assertreg src+5, r1 - - mov.l srcp2, r1 - add #2, r1 - movua.l @r1+, r0 -.ifdef LITTLE - assertreg0 0x05040302 -.else - assertreg0 0x02030405 -.endif - assertreg src+6, r1 - - mov.l srcp2, r1 - add #3, r1 - movua.l @r1+, r0 -.ifdef LITTLE - assertreg0 0x06050403 -.else - assertreg0 0x03040506 -.endif - assertreg src+7, r1 - - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - exit 0 - -srcp2: .long src - diff --git a/sim/testsuite/sim/sh/movxy.s b/sim/testsuite/sim/sh/movxy.s deleted file mode 100644 index 7768ef9..0000000 --- a/sim/testsuite/sim/sh/movxy.s +++ /dev/null @@ -1,1186 +0,0 @@ -# sh testcase for movxy -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -src1: .word 1 -src2: .word 2 -src3: .word 3 -src4: .word 4 -src5: .word 5 -src6: .word 6 -src7: .word 7 -src8: .word 8 -src9: .word 9 - .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - -dst1: .word 0 -dst2: .word 0 -dst3: .word 0 -dst4: .word 0 -dst5: .word 0 -dst6: .word 0 -dst7: .word 0 -dst8: .word 0 -dst9: .word 0 - .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - - start -movxw_nopy: - set_grs_a5a5 - # load up pointers - mov.l srcp1, r4 - mov.l dstp1, r5 - - # perform moves - movx.w @r4, x0 - pcopy x0, a0 - movx.w a0, @r5 - - # verify pointers unchanged - mov.l srcp1, r0 - cmp/eq r0, r4 - bt .L0 - fail -.L0: - mov.l dstp1, r1 - cmp/eq r1, r5 - bt .L1 - fail -.L1: - # verify copied values - mov.w @r0, r0 - mov.w @r1, r1 - cmp/eq r0, r1 - bt .L2 - fail -.L2: - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -movyw_nopx: - set_grs_a5a5 - # load up pointers - mov.l srcp2, r6 - mov.l dstp2, r7 - - # perform moves - movy.w @r6, y0 - pcopy y0, a0 - movy.w a0, @r7 - - # verify pointers unchanged - mov.l srcp2, r2 - cmp/eq r2, r6 - bt .L3 - fail -.L3: - mov.l dstp2, r3 - cmp/eq r3, r7 - bt .L4 - fail -.L4: - # verify copied values - mov.w @r2, r2 - mov.w @r3, r3 - cmp/eq r2, r3 - bt .L5 - fail -.L5: - test_gr_a5a5 r0 - test_gr_a5a5 r1 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -movxw_movyw: - set_grs_a5a5 - # load up pointers - mov.l srcp3, r4 - mov.l dstp3, r5 - mov.l srcp4, r6 - mov.l dstp4, r7 - - # perform moves - movx.w @r4, x1 movy.w @r6, y1 - pcopy x1, a0 - pcopy y1, a1 - movx.w a0, @r5 movy.w a1, @r7 - - # verify pointers unchanged - mov.l srcp3, r0 - cmp/eq r0, r4 - bt .L6 - fail -.L6: - mov.l dstp3, r1 - cmp/eq r1, r5 - bt .L7 - fail -.L7: - mov.l srcp4, r2 - cmp/eq r2, r6 - bt .L8 - fail -.L8: - mov.l dstp4, r3 - cmp/eq r3, r7 - bt .L9 - fail -.L9: - # verify copied values - mov.w @r0, r0 - mov.w @r1, r1 - cmp/eq r0, r1 - bt .L10 - fail -.L10: - mov.w @r2, r2 - mov.w @r3, r3 - cmp/eq r2, r3 - bt .L11 - fail -.L11: - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - bra movxw_movyw_new - nop - - .align 2 -srcp1: .long src1 -srcp2: .long src2 -srcp3: .long src3 -srcp4: .long src4 -srcp5: .long src5 -srcp6: .long src6 -srcp7: .long src7 -srcp8: .long src8 -srcp9: .long src9 - -dstp1: .long dst1 -dstp2: .long dst2 -dstp3: .long dst3 -dstp4: .long dst4 -dstp5: .long dst5 -dstp6: .long dst6 -dstp7: .long dst7 -dstp8: .long dst8 -dstp9: .long dst9 - -movxw_movyw_new: - set_grs_a5a5 - # load up pointers - mov.l srcp5b, r0 - mov.l dstp5b, r1 - mov.l srcp6b, r2 - mov.l dstp6b, r3 - - # perform moves - movx.w @r0, x1 - movy.w @r2, y1 - movx.w x1, @r1 - movy.w y1, @r3 - - # verify pointers unchanged - mov.l srcp5b, r4 - cmp/eq r0, r4 - bt .L12 - fail - -.L12: - mov.l dstp5b, r5 - cmp/eq r1, r5 - bt .L13 - fail -.L13: - mov.l srcp6b, r6 - cmp/eq r2, r6 - bt .L14 - fail -.L14: - mov.l dstp6b, r7 - cmp/eq r3, r7 - bt .L15 - fail -.L15: - # verify copied values - mov.w @r0, r0 - mov.w @r1, r1 - cmp/eq r0, r1 - bt .L16 - fail -.L16: - mov.w @r2, r2 - mov.w @r3, r3 - cmp/eq r2, r3 - bt .L17 - fail -.L17: - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - mov.l srcp1b, r0 - mov.l dstp1b, r1 - mov.l srcp2b, r2 - mov.l dstp2b, r3 - mov.l srcp1b, r4 - mov.l dstp1b, r5 - mov.l srcp2b, r6 - mov.l dstp2b, r7 - mov #4, r8 - mov #4, r9 - bra .L18 - nop - - .align 2 -srcp1b: .long src1 -srcp2b: .long src2 -srcp3b: .long src3 -srcp4b: .long src4 -srcp5b: .long src5 -srcp6b: .long src6 -srcp7b: .long src7 -srcp8b: .long src8 -srcp9b: .long src9 - -dstp1b: .long dst1 -dstp2b: .long dst2 -dstp3b: .long dst3 -dstp4b: .long dst4 -dstp5b: .long dst5 -dstp6b: .long dst6 -dstp7b: .long dst7 -dstp8b: .long dst8 -dstp9b: .long dst9 - -.L18: - - # movx.w @Ax{}, Dx | nopy -movxwaxdx_nopy: - movx.w @r4,x0 ! .word 0xf004 - movx.w @r4,x1 ! .word 0xf084 - movx.w @r5,x0 ! .word 0xf204 - movx.w @r5,x1 ! .word 0xf284 - movx.w @r4+,x0 ! .word 0xf008 - movx.w @r4+,x1 ! .word 0xf088 - movx.w @r5+,x0 ! .word 0xf208 - movx.w @r5+,x1 ! .word 0xf288 - movx.w @r4+r8,x0 ! .word 0xf00c - movx.w @r4+r8,x1 ! .word 0xf08c - movx.w @r5+r8,x0 ! .word 0xf20c - movx.w @r5+r8,x1 ! .word 0xf28c - # movx.w Da, @Ax{} | nopy -movxwdaax_nopy: - movx.w a0,@r4 ! .word 0xf024 - movx.w a1,@r4 ! .word 0xf0a4 - movx.w a0,@r5 ! .word 0xf224 - movx.w a1,@r5 ! .word 0xf2a4 - movx.w a0,@r4+ ! .word 0xf028 - movx.w a1,@r4+ ! .word 0xf0a8 - movx.w a0,@r5+ ! .word 0xf228 - movx.w a1,@r5+ ! .word 0xf2a8 - movx.w a0,@r4+r8 ! .word 0xf02c - movx.w a1,@r4+r8 ! .word 0xf0ac - movx.w a0,@r5+r8 ! .word 0xf22c - movx.w a1,@r5+r8 ! .word 0xf2ac - # movy.w @Ay{}, Dy | nopx -movywaydy_nopx: - movy.w @r6,y0 ! .word 0xf001 - movy.w @r6,y1 ! .word 0xf041 - movy.w @r7,y0 ! .word 0xf101 - movy.w @r7,y1 ! .word 0xf141 - movy.w @r6+,y0 ! .word 0xf002 - movy.w @r6+,y1 ! .word 0xf042 - movy.w @r7+,y0 ! .word 0xf102 - movy.w @r7+,y1 ! .word 0xf142 - movy.w @r6+r9,y0 ! .word 0xf003 - movy.w @r6+r9,y1 ! .word 0xf043 - movy.w @r7+r9,y0 ! .word 0xf103 - movy.w @r7+r9,y1 ! .word 0xf143 - # movy.w Da, @Ay{} | nopx -movywdaay_nopx: - movy.w a0,@r6 ! .word 0xf011 - movy.w a1,@r6 ! .word 0xf051 - movy.w a0,@r7 ! .word 0xf111 - movy.w a1,@r7 ! .word 0xf151 - movy.w a0,@r6+ ! .word 0xf012 - movy.w a1,@r6+ ! .word 0xf052 - movy.w a0,@r7+ ! .word 0xf112 - movy.w a1,@r7+ ! .word 0xf152 - movy.w a0,@r6+r9 ! .word 0xf013 - movy.w a1,@r6+r9 ! .word 0xf053 - movy.w a0,@r7+r9 ! .word 0xf113 - movy.w a1,@r7+r9 ! .word 0xf153 - # movx {} || movy {} -movx_movy: - movx.w @r4,x0 movy.w @r6,y0 ! .word 0xf005 - movx.w @r4,x0 movy.w @r6,y1 ! .word 0xf045 - movx.w @r4,x1 movy.w @r6,y0 ! .word 0xf085 - movx.w @r4,x1 movy.w @r6,y1 ! .word 0xf0c5 - movx.w @r4,x0 movy.w @r7,y0 ! .word 0xf105 - movx.w @r4,x0 movy.w @r7,y1 ! .word 0xf145 - movx.w @r4,x1 movy.w @r7,y0 ! .word 0xf185 - movx.w @r4,x1 movy.w @r7,y1 ! .word 0xf1c5 - movx.w @r5,x0 movy.w @r6,y0 ! .word 0xf205 - movx.w @r5,x0 movy.w @r6,y1 ! .word 0xf245 - movx.w @r5,x1 movy.w @r6,y0 ! .word 0xf285 - movx.w @r5,x1 movy.w @r6,y1 ! .word 0xf2c5 - movx.w @r5,x0 movy.w @r7,y0 ! .word 0xf305 - movx.w @r5,x0 movy.w @r7,y1 ! .word 0xf345 - movx.w @r5,x1 movy.w @r7,y0 ! .word 0xf385 - movx.w @r5,x1 movy.w @r7,y1 ! .word 0xf3c5 - movx.w @r4,x0 movy.w @r6+,y0 ! .word 0xf006 - movx.w @r4,x0 movy.w @r6+,y1 ! .word 0xf046 - movx.w @r4,x1 movy.w @r6+,y0 ! .word 0xf086 - movx.w @r4,x1 movy.w @r6+,y1 ! .word 0xf0c6 - movx.w @r4,x0 movy.w @r7+,y0 ! .word 0xf106 - movx.w @r4,x0 movy.w @r7+,y1 ! .word 0xf146 - movx.w @r4,x1 movy.w @r7+,y0 ! .word 0xf186 - movx.w @r4,x1 movy.w @r7+,y1 ! .word 0xf1c6 - movx.w @r5,x0 movy.w @r6+,y0 ! .word 0xf206 - movx.w @r5,x0 movy.w @r6+,y1 ! .word 0xf246 - movx.w @r5,x1 movy.w @r6+,y0 ! .word 0xf286 - movx.w @r5,x1 movy.w @r6+,y1 ! .word 0xf2c6 - movx.w @r5,x0 movy.w @r7+,y0 ! .word 0xf306 - movx.w @r5,x0 movy.w @r7+,y1 ! .word 0xf346 - movx.w @r5,x1 movy.w @r7+,y0 ! .word 0xf386 - movx.w @r5,x1 movy.w @r7+,y1 ! .word 0xf3c6 - movx.w @r4,x0 movy.w @r6+r9,y0 ! .word 0xf007 - movx.w @r4,x0 movy.w @r6+r9,y1 ! .word 0xf047 - movx.w @r4,x1 movy.w @r6+r9,y0 ! .word 0xf087 - movx.w @r4,x1 movy.w @r6+r9,y1 ! .word 0xf0c7 - movx.w @r4,x0 movy.w @r7+r9,y0 ! .word 0xf107 - movx.w @r4,x0 movy.w @r7+r9,y1 ! .word 0xf147 - movx.w @r4,x1 movy.w @r7+r9,y0 ! .word 0xf187 - movx.w @r4,x1 movy.w @r7+r9,y1 ! .word 0xf1c7 - movx.w @r5,x0 movy.w @r6+r9,y0 ! .word 0xf207 - movx.w @r5,x0 movy.w @r6+r9,y1 ! .word 0xf247 - movx.w @r5,x1 movy.w @r6+r9,y0 ! .word 0xf287 - movx.w @r5,x1 movy.w @r6+r9,y1 ! .word 0xf2c7 - movx.w @r5,x0 movy.w @r7+r9,y0 ! .word 0xf307 - movx.w @r5,x0 movy.w @r7+r9,y1 ! .word 0xf347 - movx.w @r5,x1 movy.w @r7+r9,y0 ! .word 0xf387 - movx.w @r5,x1 movy.w @r7+r9,y1 ! .word 0xf3c7 - movx.w @r4+,x0 movy.w @r6,y0 ! .word 0xf009 - movx.w @r4+,x0 movy.w @r6,y1 ! .word 0xf049 - movx.w @r4+,x1 movy.w @r6,y0 ! .word 0xf089 - movx.w @r4+,x1 movy.w @r6,y1 ! .word 0xf0c9 - movx.w @r4+,x0 movy.w @r7,y0 ! .word 0xf109 - movx.w @r4+,x0 movy.w @r7,y1 ! .word 0xf149 - movx.w @r4+,x1 movy.w @r7,y0 ! .word 0xf189 - movx.w @r4+,x1 movy.w @r7,y1 ! .word 0xf1c9 - movx.w @r5+,x0 movy.w @r6,y0 ! .word 0xf209 - movx.w @r5+,x0 movy.w @r6,y1 ! .word 0xf249 - movx.w @r5+,x1 movy.w @r6,y0 ! .word 0xf289 - movx.w @r5+,x1 movy.w @r6,y1 ! .word 0xf2c9 - movx.w @r5+,x0 movy.w @r7,y0 ! .word 0xf309 - movx.w @r5+,x0 movy.w @r7,y1 ! .word 0xf349 - movx.w @r5+,x1 movy.w @r7,y0 ! .word 0xf389 - movx.w @r5+,x1 movy.w @r7,y1 ! .word 0xf3c9 - movx.w @r4+,x0 movy.w @r6+,y0 ! .word 0xf00a - movx.w @r4+,x0 movy.w @r6+,y1 ! .word 0xf04a - movx.w @r4+,x1 movy.w @r6+,y0 ! .word 0xf08a - movx.w @r4+,x1 movy.w @r6+,y1 ! .word 0xf0ca - movx.w @r4+,x0 movy.w @r7+,y0 ! .word 0xf10a - movx.w @r4+,x0 movy.w @r7+,y1 ! .word 0xf14a - movx.w @r4+,x1 movy.w @r7+,y0 ! .word 0xf18a - movx.w @r4+,x1 movy.w @r7+,y1 ! .word 0xf1ca - movx.w @r5+,x0 movy.w @r6+,y0 ! .word 0xf20a - movx.w @r5+,x0 movy.w @r6+,y1 ! .word 0xf24a - movx.w @r5+,x1 movy.w @r6+,y0 ! .word 0xf28a - movx.w @r5+,x1 movy.w @r6+,y1 ! .word 0xf2ca - movx.w @r5+,x0 movy.w @r7+,y0 ! .word 0xf30a - movx.w @r5+,x0 movy.w @r7+,y1 ! .word 0xf34a - movx.w @r5+,x1 movy.w @r7+,y0 ! .word 0xf38a - movx.w @r5+,x1 movy.w @r7+,y1 ! .word 0xf3ca - movx.w @r4+,x0 movy.w @r6+r9,y0 ! .word 0xf00b - movx.w @r4+,x0 movy.w @r6+r9,y1 ! .word 0xf04b - movx.w @r4+,x1 movy.w @r6+r9,y0 ! .word 0xf08b - movx.w @r4+,x1 movy.w @r6+r9,y1 ! .word 0xf0cb - movx.w @r4+,x0 movy.w @r7+r9,y0 ! .word 0xf10b - movx.w @r4+,x0 movy.w @r7+r9,y1 ! .word 0xf14b - movx.w @r4+,x1 movy.w @r7+r9,y0 ! .word 0xf18b - movx.w @r4+,x1 movy.w @r7+r9,y1 ! .word 0xf1cb - movx.w @r5+,x0 movy.w @r6+r9,y0 ! .word 0xf20b - movx.w @r5+,x0 movy.w @r6+r9,y1 ! .word 0xf24b - movx.w @r5+,x1 movy.w @r6+r9,y0 ! .word 0xf28b - movx.w @r5+,x1 movy.w @r6+r9,y1 ! .word 0xf2cb - movx.w @r5+,x0 movy.w @r7+r9,y0 ! .word 0xf30b - movx.w @r5+,x0 movy.w @r7+r9,y1 ! .word 0xf34b - movx.w @r5+,x1 movy.w @r7+r9,y0 ! .word 0xf38b - movx.w @r5+,x1 movy.w @r7+r9,y1 ! .word 0xf3cb - movx.w @r4+r8,x0 movy.w @r6,y0 ! .word 0xf00d - movx.w @r4+r8,x0 movy.w @r6,y1 ! .word 0xf04d - movx.w @r4+r8,x1 movy.w @r6,y0 ! .word 0xf08d - movx.w @r4+r8,x1 movy.w @r6,y1 ! .word 0xf0cd - movx.w @r4+r8,x0 movy.w @r7,y0 ! .word 0xf10d - movx.w @r4+r8,x0 movy.w @r7,y1 ! .word 0xf14d - movx.w @r4+r8,x1 movy.w @r7,y0 ! .word 0xf18d - movx.w @r4+r8,x1 movy.w @r7,y1 ! .word 0xf1cd - movx.w @r5+r8,x0 movy.w @r6,y0 ! .word 0xf20d - movx.w @r5+r8,x0 movy.w @r6,y1 ! .word 0xf24d - movx.w @r5+r8,x1 movy.w @r6,y0 ! .word 0xf28d - movx.w @r5+r8,x1 movy.w @r6,y1 ! .word 0xf2cd - movx.w @r5+r8,x0 movy.w @r7,y0 ! .word 0xf30d - movx.w @r5+r8,x0 movy.w @r7,y1 ! .word 0xf34d - movx.w @r5+r8,x1 movy.w @r7,y0 ! .word 0xf38d - movx.w @r5+r8,x1 movy.w @r7,y1 ! .word 0xf3cd - movx.w @r4+r8,x0 movy.w @r6+,y0 ! .word 0xf00e - movx.w @r4+r8,x0 movy.w @r6+,y1 ! .word 0xf04e - movx.w @r4+r8,x1 movy.w @r6+,y0 ! .word 0xf08e - movx.w @r4+r8,x1 movy.w @r6+,y1 ! .word 0xf0ce - movx.w @r4+r8,x0 movy.w @r7+,y0 ! .word 0xf10e - movx.w @r4+r8,x0 movy.w @r7+,y1 ! .word 0xf14e - movx.w @r4+r8,x1 movy.w @r7+,y0 ! .word 0xf18e - movx.w @r4+r8,x1 movy.w @r7+,y1 ! .word 0xf1ce - movx.w @r5+r8,x0 movy.w @r6+,y0 ! .word 0xf20e - movx.w @r5+r8,x0 movy.w @r6+,y1 ! .word 0xf24e - movx.w @r5+r8,x1 movy.w @r6+,y0 ! .word 0xf28e - movx.w @r5+r8,x1 movy.w @r6+,y1 ! .word 0xf2ce - movx.w @r5+r8,x0 movy.w @r7+,y0 ! .word 0xf30e - movx.w @r5+r8,x0 movy.w @r7+,y1 ! .word 0xf34e - movx.w @r5+r8,x1 movy.w @r7+,y0 ! .word 0xf38e - movx.w @r5+r8,x1 movy.w @r7+,y1 ! .word 0xf3ce - movx.w @r4+r8,x0 movy.w @r6+r9,y0 ! .word 0xf00f - movx.w @r4+r8,x0 movy.w @r6+r9,y1 ! .word 0xf04f - movx.w @r4+r8,x1 movy.w @r6+r9,y0 ! .word 0xf08f - movx.w @r4+r8,x1 movy.w @r6+r9,y1 ! .word 0xf0cf - movx.w @r4+r8,x0 movy.w @r7+r9,y0 ! .word 0xf10f - movx.w @r4+r8,x0 movy.w @r7+r9,y1 ! .word 0xf14f - movx.w @r4+r8,x1 movy.w @r7+r9,y0 ! .word 0xf18f - movx.w @r4+r8,x1 movy.w @r7+r9,y1 ! .word 0xf1cf - movx.w @r5+r8,x0 movy.w @r6+r9,y0 ! .word 0xf20f - movx.w @r5+r8,x0 movy.w @r6+r9,y1 ! .word 0xf24f - movx.w @r5+r8,x1 movy.w @r6+r9,y0 ! .word 0xf28f - movx.w @r5+r8,x1 movy.w @r6+r9,y1 ! .word 0xf2cf - movx.w @r5+r8,x0 movy.w @r7+r9,y0 ! .word 0xf30f - movx.w @r5+r8,x0 movy.w @r7+r9,y1 ! .word 0xf34f - movx.w @r5+r8,x1 movy.w @r7+r9,y0 ! .word 0xf38f - movx.w @r5+r8,x1 movy.w @r7+r9,y1 ! .word 0xf3cf - movx.w @r4,x0 movy.w a0,@r6 ! .word 0xf015 - movx.w @r4,x0 movy.w a1,@r6 ! .word 0xf055 - movx.w @r4,x1 movy.w a0,@r6 ! .word 0xf095 - movx.w @r4,x1 movy.w a1,@r6 ! .word 0xf0d5 - movx.w @r4,x0 movy.w a0,@r7 ! .word 0xf115 - movx.w @r4,x0 movy.w a1,@r7 ! .word 0xf155 - movx.w @r4,x1 movy.w a0,@r7 ! .word 0xf195 - movx.w @r4,x1 movy.w a1,@r7 ! .word 0xf1d5 - movx.w @r5,x0 movy.w a0,@r6 ! .word 0xf215 - movx.w @r5,x0 movy.w a1,@r6 ! .word 0xf255 - movx.w @r5,x1 movy.w a0,@r6 ! .word 0xf295 - movx.w @r5,x1 movy.w a1,@r6 ! .word 0xf2d5 - movx.w @r5,x0 movy.w a0,@r7 ! .word 0xf315 - movx.w @r5,x0 movy.w a1,@r7 ! .word 0xf355 - movx.w @r5,x1 movy.w a0,@r7 ! .word 0xf395 - movx.w @r5,x1 movy.w a1,@r7 ! .word 0xf3d5 - movx.w @r4,x0 movy.w a0,@r6+ ! .word 0xf016 - movx.w @r4,x0 movy.w a1,@r6+ ! .word 0xf056 - movx.w @r4,x1 movy.w a0,@r6+ ! .word 0xf096 - movx.w @r4,x1 movy.w a1,@r6+ ! .word 0xf0d6 - movx.w @r4,x0 movy.w a0,@r7+ ! .word 0xf116 - movx.w @r4,x0 movy.w a1,@r7+ ! .word 0xf156 - movx.w @r4,x1 movy.w a0,@r7+ ! .word 0xf196 - movx.w @r4,x1 movy.w a1,@r7+ ! .word 0xf1d6 - movx.w @r5,x0 movy.w a0,@r6+ ! .word 0xf216 - movx.w @r5,x0 movy.w a1,@r6+ ! .word 0xf256 - movx.w @r5,x1 movy.w a0,@r6+ ! .word 0xf296 - movx.w @r5,x1 movy.w a1,@r6+ ! .word 0xf2d6 - movx.w @r5,x0 movy.w a0,@r7+ ! .word 0xf316 - movx.w @r5,x0 movy.w a1,@r7+ ! .word 0xf356 - movx.w @r5,x1 movy.w a0,@r7+ ! .word 0xf396 - movx.w @r5,x1 movy.w a1,@r7+ ! .word 0xf3d6 - movx.w @r4,x0 movy.w a0,@r6+r9 ! .word 0xf017 - movx.w @r4,x0 movy.w a1,@r6+r9 ! .word 0xf057 - movx.w @r4,x1 movy.w a0,@r6+r9 ! .word 0xf097 - movx.w @r4,x1 movy.w a1,@r6+r9 ! .word 0xf0d7 - movx.w @r4,x0 movy.w a0,@r7+r9 ! .word 0xf117 - movx.w @r4,x0 movy.w a1,@r7+r9 ! .word 0xf157 - movx.w @r4,x1 movy.w a0,@r7+r9 ! .word 0xf197 - movx.w @r4,x1 movy.w a1,@r7+r9 ! .word 0xf1d7 - movx.w @r5,x0 movy.w a0,@r6+r9 ! .word 0xf217 - movx.w @r5,x0 movy.w a1,@r6+r9 ! .word 0xf257 - movx.w @r5,x1 movy.w a0,@r6+r9 ! .word 0xf297 - movx.w @r5,x1 movy.w a1,@r6+r9 ! .word 0xf2d7 - movx.w @r5,x0 movy.w a0,@r7+r9 ! .word 0xf317 - movx.w @r5,x0 movy.w a1,@r7+r9 ! .word 0xf357 - movx.w @r5,x1 movy.w a0,@r7+r9 ! .word 0xf397 - movx.w @r5,x1 movy.w a1,@r7+r9 ! .word 0xf3d7 - movx.w @r4+,x0 movy.w a0,@r6 ! .word 0xf019 - movx.w @r4+,x0 movy.w a1,@r6 ! .word 0xf059 - movx.w @r4+,x1 movy.w a0,@r6 ! .word 0xf099 - movx.w @r4+,x1 movy.w a1,@r6 ! .word 0xf0d9 - movx.w @r4+,x0 movy.w a0,@r7 ! .word 0xf119 - movx.w @r4+,x0 movy.w a1,@r7 ! .word 0xf159 - movx.w @r4+,x1 movy.w a0,@r7 ! .word 0xf199 - movx.w @r4+,x1 movy.w a1,@r7 ! .word 0xf1d9 - movx.w @r5+,x0 movy.w a0,@r6 ! .word 0xf219 - movx.w @r5+,x0 movy.w a1,@r6 ! .word 0xf259 - movx.w @r5+,x1 movy.w a0,@r6 ! .word 0xf299 - movx.w @r5+,x1 movy.w a1,@r6 ! .word 0xf2d9 - movx.w @r5+,x0 movy.w a0,@r7 ! .word 0xf319 - movx.w @r5+,x0 movy.w a1,@r7 ! .word 0xf359 - movx.w @r5+,x1 movy.w a0,@r7 ! .word 0xf399 - movx.w @r5+,x1 movy.w a1,@r7 ! .word 0xf3d9 - movx.w @r4+,x0 movy.w a0,@r6+ ! .word 0xf01a - movx.w @r4+,x0 movy.w a1,@r6+ ! .word 0xf05a - movx.w @r4+,x1 movy.w a0,@r6+ ! .word 0xf09a - movx.w @r4+,x1 movy.w a1,@r6+ ! .word 0xf0da - movx.w @r4+,x0 movy.w a0,@r7+ ! .word 0xf11a - movx.w @r4+,x0 movy.w a1,@r7+ ! .word 0xf15a - movx.w @r4+,x1 movy.w a0,@r7+ ! .word 0xf19a - movx.w @r4+,x1 movy.w a1,@r7+ ! .word 0xf1da - movx.w @r5+,x0 movy.w a0,@r6+ ! .word 0xf21a - movx.w @r5+,x0 movy.w a1,@r6+ ! .word 0xf25a - movx.w @r5+,x1 movy.w a0,@r6+ ! .word 0xf29a - movx.w @r5+,x1 movy.w a1,@r6+ ! .word 0xf2da - movx.w @r5+,x0 movy.w a0,@r7+ ! .word 0xf31a - movx.w @r5+,x0 movy.w a1,@r7+ ! .word 0xf35a - movx.w @r5+,x1 movy.w a0,@r7+ ! .word 0xf39a - movx.w @r5+,x1 movy.w a1,@r7+ ! .word 0xf3da - movx.w @r4+,x0 movy.w a0,@r6+r9 ! .word 0xf01b - movx.w @r4+,x0 movy.w a1,@r6+r9 ! .word 0xf05b - movx.w @r4+,x1 movy.w a0,@r6+r9 ! .word 0xf09b - movx.w @r4+,x1 movy.w a1,@r6+r9 ! .word 0xf0db - movx.w @r4+,x0 movy.w a0,@r7+r9 ! .word 0xf11b - movx.w @r4+,x0 movy.w a1,@r7+r9 ! .word 0xf15b - movx.w @r4+,x1 movy.w a0,@r7+r9 ! .word 0xf19b - movx.w @r4+,x1 movy.w a1,@r7+r9 ! .word 0xf1db - movx.w @r5+,x0 movy.w a0,@r6+r9 ! .word 0xf21b - movx.w @r5+,x0 movy.w a1,@r6+r9 ! .word 0xf25b - movx.w @r5+,x1 movy.w a0,@r6+r9 ! .word 0xf29b - movx.w @r5+,x1 movy.w a1,@r6+r9 ! .word 0xf2db - movx.w @r5+,x0 movy.w a0,@r7+r9 ! .word 0xf31b - movx.w @r5+,x0 movy.w a1,@r7+r9 ! .word 0xf35b - movx.w @r5+,x1 movy.w a0,@r7+r9 ! .word 0xf39b - movx.w @r5+,x1 movy.w a1,@r7+r9 ! .word 0xf3db - movx.w @r4+r8,x0 movy.w a0,@r6 ! .word 0xf01d - movx.w @r4+r8,x0 movy.w a1,@r6 ! .word 0xf05d - movx.w @r4+r8,x1 movy.w a0,@r6 ! .word 0xf09d - movx.w @r4+r8,x1 movy.w a1,@r6 ! .word 0xf0dd - movx.w @r4+r8,x0 movy.w a0,@r7 ! .word 0xf11d - movx.w @r4+r8,x0 movy.w a1,@r7 ! .word 0xf15d - movx.w @r4+r8,x1 movy.w a0,@r7 ! .word 0xf19d - movx.w @r4+r8,x1 movy.w a1,@r7 ! .word 0xf1dd - movx.w @r5+r8,x0 movy.w a0,@r6 ! .word 0xf21d - movx.w @r5+r8,x0 movy.w a1,@r6 ! .word 0xf25d - movx.w @r5+r8,x1 movy.w a0,@r6 ! .word 0xf29d - movx.w @r5+r8,x1 movy.w a1,@r6 ! .word 0xf2dd - movx.w @r5+r8,x0 movy.w a0,@r7 ! .word 0xf31d - movx.w @r5+r8,x0 movy.w a1,@r7 ! .word 0xf35d - movx.w @r5+r8,x1 movy.w a0,@r7 ! .word 0xf39d - movx.w @r5+r8,x1 movy.w a1,@r7 ! .word 0xf3dd - movx.w @r4+r8,x0 movy.w a0,@r6+ ! .word 0xf01e - movx.w @r4+r8,x0 movy.w a1,@r6+ ! .word 0xf05e - movx.w @r4+r8,x1 movy.w a0,@r6+ ! .word 0xf09e - movx.w @r4+r8,x1 movy.w a1,@r6+ ! .word 0xf0de - movx.w @r4+r8,x0 movy.w a0,@r7+ ! .word 0xf11e - movx.w @r4+r8,x0 movy.w a1,@r7+ ! .word 0xf15e - movx.w @r4+r8,x1 movy.w a0,@r7+ ! .word 0xf19e - movx.w @r4+r8,x1 movy.w a1,@r7+ ! .word 0xf1de - movx.w @r5+r8,x0 movy.w a0,@r6+ ! .word 0xf21e - movx.w @r5+r8,x0 movy.w a1,@r6+ ! .word 0xf25e - movx.w @r5+r8,x1 movy.w a0,@r6+ ! .word 0xf29e - movx.w @r5+r8,x1 movy.w a1,@r6+ ! .word 0xf2de - movx.w @r5+r8,x0 movy.w a0,@r7+ ! .word 0xf31e - movx.w @r5+r8,x0 movy.w a1,@r7+ ! .word 0xf35e - movx.w @r5+r8,x1 movy.w a0,@r7+ ! .word 0xf39e - movx.w @r5+r8,x1 movy.w a1,@r7+ ! .word 0xf3de - movx.w @r4+r8,x0 movy.w a0,@r6+r9 ! .word 0xf01f - movx.w @r4+r8,x0 movy.w a1,@r6+r9 ! .word 0xf05f - movx.w @r4+r8,x1 movy.w a0,@r6+r9 ! .word 0xf09f - movx.w @r4+r8,x1 movy.w a1,@r6+r9 ! .word 0xf0df - movx.w @r4+r8,x0 movy.w a0,@r7+r9 ! .word 0xf11f - movx.w @r4+r8,x0 movy.w a1,@r7+r9 ! .word 0xf15f - movx.w @r4+r8,x1 movy.w a0,@r7+r9 ! .word 0xf19f - movx.w @r4+r8,x1 movy.w a1,@r7+r9 ! .word 0xf1df - movx.w @r5+r8,x0 movy.w a0,@r6+r9 ! .word 0xf21f - movx.w @r5+r8,x0 movy.w a1,@r6+r9 ! .word 0xf25f - movx.w @r5+r8,x1 movy.w a0,@r6+r9 ! .word 0xf29f - movx.w @r5+r8,x1 movy.w a1,@r6+r9 ! .word 0xf2df - movx.w @r5+r8,x0 movy.w a0,@r7+r9 ! .word 0xf31f - movx.w @r5+r8,x0 movy.w a1,@r7+r9 ! .word 0xf35f - movx.w @r5+r8,x1 movy.w a0,@r7+r9 ! .word 0xf39f - movx.w @r5+r8,x1 movy.w a1,@r7+r9 ! .word 0xf3df - movx.w a0,@r4 movy.w @r6,y0 ! .word 0xf025 - movx.w a0,@r4 movy.w @r6,y1 ! .word 0xf065 - movx.w a1,@r4 movy.w @r6,y0 ! .word 0xf0a5 - movx.w a1,@r4 movy.w @r6,y1 ! .word 0xf0e5 - movx.w a0,@r4 movy.w @r7,y0 ! .word 0xf125 - movx.w a0,@r4 movy.w @r7,y1 ! .word 0xf165 - movx.w a1,@r4 movy.w @r7,y0 ! .word 0xf1a5 - movx.w a1,@r4 movy.w @r7,y1 ! .word 0xf1e5 - movx.w a0,@r5 movy.w @r6,y0 ! .word 0xf225 - movx.w a0,@r5 movy.w @r6,y1 ! .word 0xf265 - movx.w a1,@r5 movy.w @r6,y0 ! .word 0xf2a5 - movx.w a1,@r5 movy.w @r6,y1 ! .word 0xf2e5 - movx.w a0,@r5 movy.w @r7,y0 ! .word 0xf325 - movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf365 - movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf3a5 - movx.w a1,@r5 movy.w @r7,y1 ! .word 0xf3e5 - movx.w a0,@r4 movy.w @r6+,y0 ! .word 0xf026 - movx.w a0,@r4 movy.w @r6+,y1 ! .word 0xf066 - movx.w a1,@r4 movy.w @r6+,y0 ! .word 0xf0a6 - movx.w a1,@r4 movy.w @r6+,y1 ! .word 0xf0e6 - movx.w a0,@r4 movy.w @r7+,y0 ! .word 0xf126 - movx.w a0,@r4 movy.w @r7+,y1 ! .word 0xf166 - movx.w a1,@r4 movy.w @r7+,y0 ! .word 0xf1a6 - movx.w a1,@r4 movy.w @r7+,y1 ! .word 0xf1e6 - movx.w a0,@r5 movy.w @r6+,y0 ! .word 0xf226 - movx.w a0,@r5 movy.w @r6+,y1 ! .word 0xf266 - movx.w a1,@r5 movy.w @r6+,y0 ! .word 0xf2a6 - movx.w a1,@r5 movy.w @r6+,y1 ! .word 0xf2e6 - movx.w a0,@r5 movy.w @r7+,y0 ! .word 0xf326 - movx.w a0,@r5 movy.w @r7+,y1 ! .word 0xf366 - movx.w a1,@r5 movy.w @r7+,y0 ! .word 0xf3a6 - movx.w a1,@r5 movy.w @r7+,y1 ! .word 0xf3e6 - movx.w a0,@r4 movy.w @r6+r9,y0 ! .word 0xf027 - movx.w a0,@r4 movy.w @r6+r9,y1 ! .word 0xf067 - movx.w a1,@r4 movy.w @r6+r9,y0 ! .word 0xf0a7 - movx.w a1,@r4 movy.w @r6+r9,y1 ! .word 0xf0e7 - movx.w a0,@r4 movy.w @r7+r9,y0 ! .word 0xf127 - movx.w a0,@r4 movy.w @r7+r9,y1 ! .word 0xf167 - movx.w a1,@r4 movy.w @r7+r9,y0 ! .word 0xf1a7 - movx.w a1,@r4 movy.w @r7+r9,y1 ! .word 0xf1e7 - movx.w a0,@r5 movy.w @r6+r9,y0 ! .word 0xf227 - movx.w a0,@r5 movy.w @r6+r9,y1 ! .word 0xf267 - movx.w a1,@r5 movy.w @r6+r9,y0 ! .word 0xf2a7 - movx.w a1,@r5 movy.w @r6+r9,y1 ! .word 0xf2e7 - movx.w a0,@r5 movy.w @r7+r9,y0 ! .word 0xf327 - movx.w a0,@r5 movy.w @r7+r9,y1 ! .word 0xf367 - movx.w a1,@r5 movy.w @r7+r9,y0 ! .word 0xf3a7 - movx.w a1,@r5 movy.w @r7+r9,y1 ! .word 0xf3e7 - movx.w a0,@r4+ movy.w @r6,y0 ! .word 0xf029 - movx.w a0,@r4+ movy.w @r6,y1 ! .word 0xf069 - movx.w a1,@r4+ movy.w @r6,y0 ! .word 0xf0a9 - movx.w a1,@r4+ movy.w @r6,y1 ! .word 0xf0e9 - movx.w a0,@r4+ movy.w @r7,y0 ! .word 0xf129 - movx.w a0,@r4+ movy.w @r7,y1 ! .word 0xf169 - movx.w a1,@r4+ movy.w @r7,y0 ! .word 0xf1a9 - movx.w a1,@r4+ movy.w @r7,y1 ! .word 0xf1e9 - movx.w a0,@r5+ movy.w @r6,y0 ! .word 0xf229 - movx.w a0,@r5+ movy.w @r6,y1 ! .word 0xf269 - movx.w a1,@r5+ movy.w @r6,y0 ! .word 0xf2a9 - movx.w a1,@r5+ movy.w @r6,y1 ! .word 0xf2e9 - movx.w a0,@r5+ movy.w @r7,y0 ! .word 0xf329 - movx.w a0,@r5+ movy.w @r7,y1 ! .word 0xf369 - movx.w a1,@r5+ movy.w @r7,y0 ! .word 0xf3a9 - movx.w a1,@r5+ movy.w @r7,y1 ! .word 0xf3e9 - movx.w a0,@r4+ movy.w @r6+,y0 ! .word 0xf02a - movx.w a0,@r4+ movy.w @r6+,y1 ! .word 0xf06a - movx.w a1,@r4+ movy.w @r6+,y0 ! .word 0xf0aa - movx.w a1,@r4+ movy.w @r6+,y1 ! .word 0xf0ea - movx.w a0,@r4+ movy.w @r7+,y0 ! .word 0xf12a - movx.w a0,@r4+ movy.w @r7+,y1 ! .word 0xf16a - movx.w a1,@r4+ movy.w @r7+,y0 ! .word 0xf1aa - movx.w a1,@r4+ movy.w @r7+,y1 ! .word 0xf1ea - movx.w a0,@r5+ movy.w @r6+,y0 ! .word 0xf22a - movx.w a0,@r5+ movy.w @r6+,y1 ! .word 0xf26a - movx.w a1,@r5+ movy.w @r6+,y0 ! .word 0xf2aa - movx.w a1,@r5+ movy.w @r6+,y1 ! .word 0xf2ea - movx.w a0,@r5+ movy.w @r7+,y0 ! .word 0xf32a - movx.w a0,@r5+ movy.w @r7+,y1 ! .word 0xf36a - movx.w a1,@r5+ movy.w @r7+,y0 ! .word 0xf3aa - movx.w a1,@r5+ movy.w @r7+,y1 ! .word 0xf3ea - movx.w a0,@r4+ movy.w @r6+r9,y0 ! .word 0xf02b - movx.w a0,@r4+ movy.w @r6+r9,y1 ! .word 0xf06b - movx.w a1,@r4+ movy.w @r6+r9,y0 ! .word 0xf0ab - movx.w a1,@r4+ movy.w @r6+r9,y1 ! .word 0xf0eb - movx.w a0,@r4+ movy.w @r7+r9,y0 ! .word 0xf12b - movx.w a0,@r4+ movy.w @r7+r9,y1 ! .word 0xf16b - movx.w a1,@r4+ movy.w @r7+r9,y0 ! .word 0xf1ab - movx.w a1,@r4+ movy.w @r7+r9,y1 ! .word 0xf1eb - movx.w a0,@r5+ movy.w @r6+r9,y0 ! .word 0xf22b - movx.w a0,@r5+ movy.w @r6+r9,y1 ! .word 0xf26b - movx.w a1,@r5+ movy.w @r6+r9,y0 ! .word 0xf2ab - movx.w a1,@r5+ movy.w @r6+r9,y1 ! .word 0xf2eb - movx.w a0,@r5+ movy.w @r7+r9,y0 ! .word 0xf32b - movx.w a0,@r5+ movy.w @r7+r9,y1 ! .word 0xf36b - movx.w a1,@r5+ movy.w @r7+r9,y0 ! .word 0xf3ab - movx.w a1,@r5+ movy.w @r7+r9,y1 ! .word 0xf3eb - movx.w a0,@r4+r8 movy.w @r6,y0 ! .word 0xf02d - movx.w a0,@r4+r8 movy.w @r6,y1 ! .word 0xf06d - movx.w a1,@r4+r8 movy.w @r6,y0 ! .word 0xf0ad - movx.w a1,@r4+r8 movy.w @r6,y1 ! .word 0xf0ed - movx.w a0,@r4+r8 movy.w @r7,y0 ! .word 0xf12d - movx.w a0,@r4+r8 movy.w @r7,y1 ! .word 0xf16d - movx.w a1,@r4+r8 movy.w @r7,y0 ! .word 0xf1ad - movx.w a1,@r4+r8 movy.w @r7,y1 ! .word 0xf1ed - movx.w a0,@r5+r8 movy.w @r6,y0 ! .word 0xf22d - movx.w a0,@r5+r8 movy.w @r6,y1 ! .word 0xf26d - movx.w a1,@r5+r8 movy.w @r6,y0 ! .word 0xf2ad - movx.w a1,@r5+r8 movy.w @r6,y1 ! .word 0xf2ed - movx.w a0,@r5+r8 movy.w @r7,y0 ! .word 0xf32d - movx.w a0,@r5+r8 movy.w @r7,y1 ! .word 0xf36d - movx.w a1,@r5+r8 movy.w @r7,y0 ! .word 0xf3ad - movx.w a1,@r5+r8 movy.w @r7,y1 ! .word 0xf3ed - movx.w a0,@r4+r8 movy.w @r6+,y0 ! .word 0xf02e - movx.w a0,@r4+r8 movy.w @r6+,y1 ! .word 0xf06e - movx.w a1,@r4+r8 movy.w @r6+,y0 ! .word 0xf0ae - movx.w a1,@r4+r8 movy.w @r6+,y1 ! .word 0xf0ee - movx.w a0,@r4+r8 movy.w @r7+,y0 ! .word 0xf12e - movx.w a0,@r4+r8 movy.w @r7+,y1 ! .word 0xf16e - movx.w a1,@r4+r8 movy.w @r7+,y0 ! .word 0xf1ae - movx.w a1,@r4+r8 movy.w @r7+,y1 ! .word 0xf1ee - movx.w a0,@r5+r8 movy.w @r6+,y0 ! .word 0xf22e - movx.w a0,@r5+r8 movy.w @r6+,y1 ! .word 0xf26e - movx.w a1,@r5+r8 movy.w @r6+,y0 ! .word 0xf2ae - movx.w a1,@r5+r8 movy.w @r6+,y1 ! .word 0xf2ee - movx.w a0,@r5+r8 movy.w @r7+,y0 ! .word 0xf32e - movx.w a0,@r5+r8 movy.w @r7+,y1 ! .word 0xf36e - movx.w a1,@r5+r8 movy.w @r7+,y0 ! .word 0xf3ae - movx.w a1,@r5+r8 movy.w @r7+,y1 ! .word 0xf3ee - movx.w a0,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf02f - movx.w a0,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf06f - movx.w a1,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf0af - movx.w a1,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf0ef - movx.w a0,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf12f - movx.w a0,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf16f - movx.w a1,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf1af - movx.w a1,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf1ef - movx.w a0,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf22f - movx.w a0,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf26f - movx.w a1,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf2af - movx.w a1,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf2ef - movx.w a0,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf32f - movx.w a0,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf36f - movx.w a1,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf3af - movx.w a1,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf3ef - -movxwaxydxy: - movx.w @r4,x0 ! - movx.w @r4,y0 ! - movx.w @r4,x1 ! - movx.w @r4,y1 ! - movx.w @r0,x0 ! - movx.w @r0,y0 ! - movx.w @r0,x1 ! - movx.w @r0,y1 ! - movx.w @r5,x0 ! - movx.w @r5,y0 ! - movx.w @r5,x1 ! - movx.w @r5,y1 ! - movx.w @r1,x0 ! - movx.w @r1,y0 ! - movx.w @r1,x1 ! - movx.w @r1,y1 ! - movx.w @r4+,x0 ! - movx.w @r4+,y0 ! - movx.w @r4+,x1 ! - movx.w @r4+,y1 ! - movx.w @r0+,x0 ! - movx.w @r0+,y0 ! - movx.w @r0+,x1 ! - movx.w @r0+,y1 ! - movx.w @r5+,x0 ! - movx.w @r5+,y0 ! - movx.w @r5+,x1 ! - movx.w @r5+,y1 ! - movx.w @r1+,x0 ! - movx.w @r1+,y0 ! - movx.w @r1+,x1 ! - movx.w @r1+,y1 ! - movx.w @r4+r8,x0 ! - movx.w @r4+r8,y0 ! - movx.w @r4+r8,x1 ! - movx.w @r4+r8,y1 ! - movx.w @r0+r8,x0 ! - movx.w @r0+r8,y0 ! - movx.w @r0+r8,x1 ! - movx.w @r0+r8,y1 ! - movx.w @r5+r8,x0 ! - movx.w @r5+r8,y0 ! - movx.w @r5+r8,x1 ! - movx.w @r5+r8,y1 ! - movx.w @r1+r8,x0 ! - movx.w @r1+r8,y0 ! - movx.w @r1+r8,x1 ! - movx.w @r1+r8,y1 ! - -movxwdaxaxy: ! - movx.w a0,@r4 ! - movx.w x0,@r4 ! - movx.w a1,@r4 ! - movx.w x1,@r4 ! - movx.w a0,@r0 ! - movx.w x0,@r0 ! - movx.w a1,@r0 ! - movx.w x1,@r0 ! - movx.w a0,@r5 ! - movx.w x0,@r5 ! - movx.w a1,@r5 ! - movx.w x1,@r5 ! - movx.w a0,@r1 ! - movx.w x0,@r1 ! - movx.w a1,@r1 ! - movx.w x1,@r1 ! - movx.w a0,@r4+ ! - movx.w x0,@r4+ ! - movx.w a1,@r4+ ! - movx.w x1,@r4+ ! - movx.w a0,@r0+ ! - movx.w x0,@r0+ ! - movx.w a1,@r0+ ! - movx.w x1,@r0+ ! - movx.w a0,@r5+ ! - movx.w x0,@r5+ ! - movx.w a1,@r5+ ! - movx.w x1,@r5+ ! - movx.w a0,@r1+ ! - movx.w x0,@r1+ ! - movx.w a1,@r1+ ! - movx.w x1,@r1+ ! - movx.w a0,@r4+r8 ! - movx.w x0,@r4+r8 ! - movx.w a1,@r4+r8 ! - movx.w x1,@r4+r8 ! - movx.w a0,@r0+r8 ! - movx.w x0,@r0+r8 ! - movx.w a1,@r0+r8 ! - movx.w x1,@r0+r8 ! - movx.w a0,@r5+r8 ! - movx.w x0,@r5+r8 ! - movx.w a1,@r5+r8 ! - movx.w x1,@r5+r8 ! - movx.w a0,@r1+r8 ! - movx.w x0,@r1+r8 ! - movx.w a1,@r1+r8 ! - movx.w x1,@r1+r8 ! - -movywayxdyx: ! - movy.w @r6,y0 ! - movy.w @r6,y1 ! - movy.w @r6,x0 ! - movy.w @r6,x1 ! - movy.w @r7,y0 ! - movy.w @r7,y1 ! - movy.w @r7,x0 ! - movy.w @r7,x1 ! - movy.w @r2,y0 ! - movy.w @r2,y1 ! - movy.w @r2,x0 ! - movy.w @r2,x1 ! - movy.w @r3,y0 ! - movy.w @r3,y1 ! - movy.w @r3,x0 ! - movy.w @r3,x1 ! - movy.w @r6+,y0 ! - movy.w @r6+,y1 ! - movy.w @r6+,x0 ! - movy.w @r6+,x1 ! - movy.w @r7+,y0 ! - movy.w @r7+,y1 ! - movy.w @r7+,x0 ! - movy.w @r7+,x1 ! - movy.w @r2+,y0 ! - movy.w @r2+,y1 ! - movy.w @r2+,x0 ! - movy.w @r2+,x1 ! - movy.w @r3+,y0 ! - movy.w @r3+,y1 ! - movy.w @r3+,x0 ! - movy.w @r3+,x1 ! - movy.w @r6+r9,y0 ! - movy.w @r6+r9,y1 ! - movy.w @r6+r9,x0 ! - movy.w @r6+r9,x1 ! - movy.w @r7+r9,y0 ! - movy.w @r7+r9,y1 ! - movy.w @r7+r9,x0 ! - movy.w @r7+r9,x1 ! - movy.w @r2+r9,y0 ! - movy.w @r2+r9,y1 ! - movy.w @r2+r9,x0 ! - movy.w @r2+r9,x1 ! - movy.w @r3+r9,y0 ! - movy.w @r3+r9,y1 ! - movy.w @r3+r9,x0 ! - movy.w @r3+r9,x1 ! - -movywdayayx: - movy.w a0,@r6 - movy.w a1,@r6 - movy.w y0,@r6 - movy.w y1,@r6 - movy.w a0,@r7 - movy.w a1,@r7 - movy.w y0,@r7 - movy.w y1,@r7 - movy.w a0,@r2 - movy.w a1,@r2 - movy.w y0,@r2 - movy.w y1,@r2 - movy.w a0,@r3 - movy.w a1,@r3 - movy.w y0,@r3 - movy.w y1,@r3 - movy.w a0,@r6+ - movy.w a1,@r6+ - movy.w y0,@r6+ - movy.w y1,@r6+ - movy.w a0,@r7+ - movy.w a1,@r7+ - movy.w y0,@r7+ - movy.w y1,@r7+ - movy.w a0,@r2+ - movy.w a1,@r2+ - movy.w y0,@r2+ - movy.w y1,@r2+ - movy.w a0,@r3+ - movy.w a1,@r3+ - movy.w y0,@r3+ - movy.w y1,@r3+ - movy.w a0,@r6+r9 - movy.w a1,@r6+r9 - movy.w y0,@r6+r9 - movy.w y1,@r6+r9 - movy.w a0,@r7+r9 - movy.w a1,@r7+r9 - movy.w y0,@r7+r9 - movy.w y1,@r7+r9 - movy.w a0,@r2+r9 - movy.w a1,@r2+r9 - movy.w y0,@r2+r9 - movy.w y1,@r2+r9 - movy.w a0,@r3+r9 - movy.w a1,@r3+r9 - movy.w y0,@r3+r9 - movy.w y1,@r3+r9 - - mov r4, r0 - mov r4, r1 - mov r4, r2 - mov r4, r3 - mov r4, r5 - mov r4, r6 - mov r5, r7 - -movxlaxydxy: - movx.l @r4,x0 - movx.l @r4,y0 - movx.l @r4,x1 - movx.l @r4,y1 - movx.l @r0,x0 - movx.l @r0,y0 - movx.l @r0,x1 - movx.l @r0,y1 - movx.l @r5,x0 - movx.l @r5,y0 - movx.l @r5,x1 - movx.l @r5,y1 - movx.l @r1,x0 - movx.l @r1,y0 - movx.l @r1,x1 - movx.l @r1,y1 - movx.l @r4+,x0 - movx.l @r4+,y0 - movx.l @r4+,x1 - movx.l @r4+,y1 - movx.l @r0+,x0 - movx.l @r0+,y0 - movx.l @r0+,x1 - movx.l @r0+,y1 - movx.l @r5+,x0 - movx.l @r5+,y0 - movx.l @r5+,x1 - movx.l @r5+,y1 - movx.l @r1+,x0 - movx.l @r1+,y0 - movx.l @r1+,x1 - movx.l @r1+,y1 - movx.l @r4+r8,x0 - movx.l @r4+r8,y0 - movx.l @r4+r8,x1 - movx.l @r4+r8,y1 - movx.l @r0+r8,x0 - movx.l @r0+r8,y0 - movx.l @r0+r8,x1 - movx.l @r0+r8,y1 - movx.l @r5+r8,x0 - movx.l @r5+r8,y0 - movx.l @r5+r8,x1 - movx.l @r5+r8,y1 - movx.l @r1+r8,x0 - movx.l @r1+r8,y0 - movx.l @r1+r8,x1 - movx.l @r1+r8,y1 - -movxldaxaxy: - movx.l a0,@r4 - movx.l x0,@r4 - movx.l a1,@r4 - movx.l x1,@r4 - movx.l a0,@r0 - movx.l x0,@r0 - movx.l a1,@r0 - movx.l x1,@r0 - movx.l a0,@r5 - movx.l x0,@r5 - movx.l a1,@r5 - movx.l x1,@r5 - movx.l a0,@r1 - movx.l x0,@r1 - movx.l a1,@r1 - movx.l x1,@r1 - movx.l a0,@r4+ - movx.l x0,@r4+ - movx.l a1,@r4+ - movx.l x1,@r4+ - movx.l a0,@r0+ - movx.l x0,@r0+ - movx.l a1,@r0+ - movx.l x1,@r0+ - movx.l a0,@r5+ - movx.l x0,@r5+ - movx.l a1,@r5+ - movx.l x1,@r5+ - movx.l a0,@r1+ - movx.l x0,@r1+ - movx.l a1,@r1+ - movx.l x1,@r1+ - movx.l a0,@r4+r8 - movx.l x0,@r4+r8 - movx.l a1,@r4+r8 - movx.l x1,@r4+r8 - movx.l a0,@r0+r8 - movx.l x0,@r0+r8 - movx.l a1,@r0+r8 - movx.l x1,@r0+r8 - movx.l a0,@r5+r8 - movx.l x0,@r5+r8 - movx.l a1,@r5+r8 - movx.l x1,@r5+r8 - movx.l a0,@r1+r8 - movx.l x0,@r1+r8 - movx.l a1,@r1+r8 - movx.l x1,@r1+r8 - -movylayxdyx: - movy.l @r6,y0 - movy.l @r6,y1 - movy.l @r6,x0 - movy.l @r6,x1 - movy.l @r7,y0 - movy.l @r7,y1 - movy.l @r7,x0 - movy.l @r7,x1 - movy.l @r2,y0 - movy.l @r2,y1 - movy.l @r2,x0 - movy.l @r2,x1 - movy.l @r3,y0 - movy.l @r3,y1 - movy.l @r3,x0 - movy.l @r3,x1 - movy.l @r6+,y0 - movy.l @r6+,y1 - movy.l @r6+,x0 - movy.l @r6+,x1 - movy.l @r7+,y0 - movy.l @r7+,y1 - movy.l @r7+,x0 - movy.l @r7+,x1 - movy.l @r2+,y0 - movy.l @r2+,y1 - movy.l @r2+,x0 - movy.l @r2+,x1 - movy.l @r3+,y0 - movy.l @r3+,y1 - movy.l @r3+,x0 - movy.l @r3+,x1 - movy.l @r6+r9,y0 - movy.l @r6+r9,y1 - movy.l @r6+r9,x0 - movy.l @r6+r9,x1 - movy.l @r7+r9,y0 - movy.l @r7+r9,y1 - movy.l @r7+r9,x0 - movy.l @r7+r9,x1 - movy.l @r2+r9,y0 - movy.l @r2+r9,y1 - movy.l @r2+r9,x0 - movy.l @r2+r9,x1 - movy.l @r3+r9,y0 - movy.l @r3+r9,y1 - movy.l @r3+r9,x0 - movy.l @r3+r9,x1 - -movyldayayx: - movy.l a0,@r6 - movy.l a1,@r6 - movy.l y0,@r6 - movy.l y1,@r6 - movy.l a0,@r7 - movy.l a1,@r7 - movy.l y0,@r7 - movy.l y1,@r7 - movy.l a0,@r2 - movy.l a1,@r2 - movy.l y0,@r2 - movy.l y1,@r2 - movy.l a0,@r3 - movy.l a1,@r3 - movy.l y0,@r3 - movy.l y1,@r3 - movy.l a0,@r6+ - movy.l a1,@r6+ - movy.l y0,@r6+ - movy.l y1,@r6+ - movy.l a0,@r7+ - movy.l a1,@r7+ - movy.l y0,@r7+ - movy.l y1,@r7+ - movy.l a0,@r2+ - movy.l a1,@r2+ - movy.l y0,@r2+ - movy.l y1,@r2+ - movy.l a0,@r3+ - movy.l a1,@r3+ - movy.l y0,@r3+ - movy.l y1,@r3+ - movy.l a0,@r6+r9 - movy.l a1,@r6+r9 - movy.l y0,@r6+r9 - movy.l y1,@r6+r9 - movy.l a0,@r7+r9 - movy.l a1,@r7+r9 - movy.l y0,@r7+r9 - movy.l y1,@r7+r9 - movy.l a0,@r2+r9 - movy.l a1,@r2+r9 - movy.l y0,@r2+r9 - movy.l y1,@r2+r9 - movy.l a0,@r3+r9 - movy.l a1,@r3+r9 - movy.l y0,@r3+r9 - movy.l y1,@r3+r9 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/mulr.s b/sim/testsuite/sim/sh/mulr.s deleted file mode 100644 index 1e755ab..0000000 --- a/sim/testsuite/sim/sh/mulr.s +++ /dev/null @@ -1,162 +0,0 @@ -# sh testcase for mulr -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -mulr_1: ! multiply by one - set_grs_a5a5 - mov #1, r0 - mulr r0, r1 - assertreg0 1 - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -mulr_2: ! multiply by two - set_grs_a5a5 - mov #2, r0 - mov #12, r1 - mulr r0, r1 - assertreg0 2 - assertreg 24, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -mulr_3: ! multiply five by five - set_grs_a5a5 - mov #5, r0 - mov #5, r1 - mulr r0, r1 - assertreg0 5 - assertreg 25, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - -mulr_4: ! multiply 127 by 127 - set_grs_a5a5 - mov #127, r0 - mov #127, r1 - mulr r0, r1 - assertreg0 127 - assertreg 0x3f01, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -mulr_5: ! multiply -1 by -1 - set_grs_a5a5 - mov #-1, r0 - mov #-1, r1 - mulr r0, r1 - assertreg0 -1 - assertreg 1, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -mulr_6: ! multiply 46340 by 46340 - set_grs_a5a5 - movi20 #46340, r0 - movi20 #46340, r1 - mulr r0, r1 - assertreg0 46340 - assertreg 0x7ffea810, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -mulr_7: ! multiply 7ffff by 7ffff (overflow) - set_grs_a5a5 - movi20 #0x7ffff, r0 - movi20 #0x7ffff, r1 - mulr r0, r1 - assertreg0 0x7ffff - assertreg 0xfff00001, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - - pass - - exit 0 - - \ No newline at end of file diff --git a/sim/testsuite/sim/sh/pabs.s b/sim/testsuite/sim/sh/pabs.s deleted file mode 100644 index 6a9e4f2..0000000 --- a/sim/testsuite/sim/sh/pabs.s +++ /dev/null @@ -1,54 +0,0 @@ -# sh testcase for pabs -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - # FIXME: opcode table ambiguity in ignored bits 4-7. - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pabs x0, x1 - pabs y0, y1 - assert_sreg 0x5a5a5a5b, x1 - assert_sreg 0x5a5a5a5b, y1 - pabs x1, x0 - pabs y1, y0 - assert_sreg 0x5a5a5a5b, x0 - assert_sreg 0x5a5a5a5b, y0 - - set_dcfalse - dct pabs a0, a0 - dct pabs m0, m0 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, m0 - set_dctrue - dct pabs a0, a0 - dct pabs m0, m0 - assert_sreg 0x5a5a5a5b, a0 - assert_sreg2 0x5a5a5a5b, m0 - - set_dctrue - dcf pabs a1, a1 - dcf pabs m1, m1 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m1 - set_dcfalse - dcf pabs a1, a1 - dcf pabs m1, m1 - assert_sreg2 0x5a5a5a5b, a1 - assert_sreg2 0x5a5a5a5b, m1 - - test_grs_a5a5 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/padd.s b/sim/testsuite/sim/sh/padd.s deleted file mode 100644 index 072935d..0000000 --- a/sim/testsuite/sim/sh/padd.s +++ /dev/null @@ -1,54 +0,0 @@ -# sh testcase for padd -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - padd x0, y0, a0 - assert_sreg 0x4b4b4b4a, a0 - - # 2 + 2 = 4 - mov #2, r0 - lds r0, x0 - lds r0, y0 - padd x0, y0, a0 - assert_sreg 4, a0 - - set_dcfalse - dct padd x0, y0, a1 - assert_sreg2 0xa5a5a5a5, a1 - set_dctrue - dct padd x0, y0, a1 - assert_sreg2 4, a1 - - set_dctrue - dcf padd x0, y0, m1 - assert_sreg2 0xa5a5a5a5, m1 - set_dcfalse - dcf padd x0, y0, m1 - assert_sreg2 4, m1 - - # padd / pmuls - - padd x0, y0, y0 pmuls x1, y1, m1 - assert_sreg 4, y0 - assert_sreg2 0x3fc838b2, m1 ! (int) 0xa5a5 x (int) 0xa5a5 x 2 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/paddc.s b/sim/testsuite/sim/sh/paddc.s deleted file mode 100644 index 0dd3b67..0000000 --- a/sim/testsuite/sim/sh/paddc.s +++ /dev/null @@ -1,39 +0,0 @@ -# sh testcase for paddc -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - # 2 + 2 = 4 - set_dcfalse - mov #2, r0 - lds r0, x0 - lds r0, y0 - paddc x0, y0, a0 - assert_sreg 4, a0 - - # 2 + 2 + carry = 5 - set_dctrue - paddc x0, y0, a1 - assert_sreg2 5, a1 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pand.s b/sim/testsuite/sim/sh/pand.s deleted file mode 100644 index cddf058..0000000 --- a/sim/testsuite/sim/sh/pand.s +++ /dev/null @@ -1,48 +0,0 @@ -# sh testcase for pand -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pand x0, y0, a0 - assert_sreg 0xa5a50000, a0 - - # 0xa5a5a5a5 & 0x5a5a5a5a == 0 - set_greg 0x5a5a5a5a r0 - lds r0, x0 - pand x0, y0, a0 - assert_sreg 0, a0 - - set_dcfalse - dct pand x0, y0, m0 - assert_sreg2 0xa5a5a5a5, m0 - set_dctrue - dct pand x0, y0, m0 - assert_sreg2 0, m0 - - set_dctrue - dcf pand x0, y0, m1 - assert_sreg2 0xa5a5a5a5, m1 - set_dcfalse - dcf pand x0, y0, m1 - assert_sreg2 0, m1 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, a1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pass.s b/sim/testsuite/sim/sh/pass.s deleted file mode 100644 index cc3bbcc..0000000 --- a/sim/testsuite/sim/sh/pass.s +++ /dev/null @@ -1,14 +0,0 @@ -# sh testcase, pass -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - test_grs_a5a5 - pass - - exit 0 - diff --git a/sim/testsuite/sim/sh/pclr.s b/sim/testsuite/sim/sh/pclr.s deleted file mode 100644 index c396f83..0000000 --- a/sim/testsuite/sim/sh/pclr.s +++ /dev/null @@ -1,65 +0,0 @@ -# sh testcase for pclr -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - # FIXME: opcode table ambiguity in ignored bits 4-7. - - .include "testutils.inc" - - start -pclr_cc: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - assert_sreg 0xa5a5a5a5, x0 - pclr x0 - assert_sreg 0, x0 - - set_dcfalse - dct pclr x1 - assert_sreg 0xa5a5a5a5, x1 - set_dctrue - dct pclr x1 - assert_sreg 0, x1 - - set_dctrue - dcf pclr y0 - assert_sreg 0xa5a5a5a5, y0 - set_dcfalse - dcf pclr y0 - assert_sreg 0, y0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -pclr_pmuls: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pclr x0 pmuls y0, y1, a0 - - assert_sreg 0, x0 - assert_sreg 0x3fc838b2, a0 ! 0xa5a5 x 0xa5a5 - - test_grs_a5a5 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pdec.s b/sim/testsuite/sim/sh/pdec.s deleted file mode 100644 index fa4b6a5..0000000 --- a/sim/testsuite/sim/sh/pdec.s +++ /dev/null @@ -1,110 +0,0 @@ -# sh testcase for pdec -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -pdecx: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pdec x0, y0 - assert_sreg 0xa5a40000, y0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -pdecy: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pdec y0, x0 - assert_sreg 0xa5a40000, x0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -dct_pdecx: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_dcfalse - dct pdec x0, y0 - assert_sreg 0xa5a5a5a5, y0 - set_dctrue - dct pdec x0, y0 - assert_sreg 0xa5a40000, y0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -dcf_pdecy: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_dctrue - dcf pdec y0, x0 - assert_sreg 0xa5a5a5a5, x0 - set_dcfalse - dcf pdec y0, x0 - assert_sreg 0xa5a40000, x0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pdmsb.s b/sim/testsuite/sim/sh/pdmsb.s deleted file mode 100644 index 0cb7829..0000000 --- a/sim/testsuite/sim/sh/pdmsb.s +++ /dev/null @@ -1,230 +0,0 @@ -# sh testcase for pdmsb -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_sreg 0x0, x0 -L0: pdmsb x0, x1 -# assert_sreg 31<<16, x1 - set_sreg 0x1, x0 -L1: pdmsb x0, x1 - assert_sreg 30<<16, x1 - set_sreg 0x3, x0 -L2: pdmsb x0, x1 - assert_sreg 29<<16, x1 - set_sreg 0x7, x0 -L3: pdmsb x0, x1 - assert_sreg 28<<16, x1 - set_sreg 0xf, x0 -L4: pdmsb x0, x1 - assert_sreg 27<<16, x1 - set_sreg 0x1f, x0 -L5: pdmsb x0, x1 - assert_sreg 26<<16, x1 - set_sreg 0x3f, x0 -L6: pdmsb x0, x1 - assert_sreg 25<<16, x1 - set_sreg 0x7f, x0 -L7: pdmsb x0, x1 - assert_sreg 24<<16, x1 - set_sreg 0xff, x0 -L8: pdmsb x0, x1 - assert_sreg 23<<16, x1 - - set_sreg 0x1ff, x0 -L9: pdmsb x0, x1 - assert_sreg 22<<16, x1 - set_sreg 0x3ff, x0 -L10: pdmsb x0, x1 - assert_sreg 21<<16, x1 - set_sreg 0x7ff, x0 -L11: pdmsb x0, x1 - assert_sreg 20<<16, x1 - set_sreg 0xfff, x0 -L12: pdmsb x0, x1 - assert_sreg 19<<16, x1 - set_sreg 0x1fff, x0 -L13: pdmsb x0, x1 - assert_sreg 18<<16, x1 - set_sreg 0x3fff, x0 -L14: pdmsb x0, x1 - assert_sreg 17<<16, x1 - set_sreg 0x7fff, x0 -L15: pdmsb x0, x1 - assert_sreg 16<<16, x1 - set_sreg 0xffff, x0 -L16: pdmsb x0, x1 - assert_sreg 15<<16, x1 - - set_sreg 0x1ffff, x0 -L17: pdmsb x0, x1 - assert_sreg 14<<16, x1 - set_sreg 0x3ffff, x0 -L18: pdmsb x0, x1 - assert_sreg 13<<16, x1 - set_sreg 0x7ffff, x0 -L19: pdmsb x0, x1 - assert_sreg 12<<16, x1 - set_sreg 0xfffff, x0 -L20: pdmsb x0, x1 - assert_sreg 11<<16, x1 - set_sreg 0x1fffff, x0 -L21: pdmsb x0, x1 - assert_sreg 10<<16, x1 - set_sreg 0x3fffff, x0 -L22: pdmsb x0, x1 - assert_sreg 9<<16, x1 - set_sreg 0x7fffff, x0 -L23: pdmsb x0, x1 - assert_sreg 8<<16, x1 - set_sreg 0xffffff, x0 -L24: pdmsb x0, x1 - assert_sreg 7<<16, x1 - - set_sreg 0x1ffffff, x0 -L25: pdmsb x0, x1 - assert_sreg 6<<16, x1 - set_sreg 0x3ffffff, x0 -L26: pdmsb x0, x1 - assert_sreg 5<<16, x1 - set_sreg 0x7ffffff, x0 -L27: pdmsb x0, x1 - assert_sreg 4<<16, x1 - set_sreg 0xfffffff, x0 -L28: pdmsb x0, x1 - assert_sreg 3<<16, x1 - set_sreg 0x1fffffff, x0 -L29: pdmsb x0, x1 - assert_sreg 2<<16, x1 - set_sreg 0x3fffffff, x0 -L30: pdmsb x0, x1 - assert_sreg 1<<16, x1 - set_sreg 0x7fffffff, x0 -L31: pdmsb x0, x1 - assert_sreg 0<<16, x1 - set_sreg 0xffffffff, x0 -L32: pdmsb x0, x1 -# assert_sreg 31<<16, x1 - - set_sreg 0xfffffffe, x0 -L33: pdmsb x0, x1 - assert_sreg 30<<16, x1 - set_sreg 0xfffffffc, x0 -L34: pdmsb x0, x1 - assert_sreg 29<<16, x1 - set_sreg 0xfffffff8, x0 -L35: pdmsb x0, x1 - assert_sreg 28<<16, x1 - set_sreg 0xfffffff0, x0 -L36: pdmsb x0, x1 - assert_sreg 27<<16, x1 - set_sreg 0xffffffe0, x0 -L37: pdmsb x0, x1 - assert_sreg 26<<16, x1 - set_sreg 0xffffffc0, x0 -L38: pdmsb x0, x1 - assert_sreg 25<<16, x1 - set_sreg 0xffffff80, x0 -L39: pdmsb x0, x1 - assert_sreg 24<<16, x1 - set_sreg 0xffffff00, x0 -L40: pdmsb x0, x1 - assert_sreg 23<<16, x1 - - set_sreg 0xfffffe00, x0 -L41: pdmsb x0, x1 - assert_sreg 22<<16, x1 - set_sreg 0xfffffc00, x0 -L42: pdmsb x0, x1 - assert_sreg 21<<16, x1 - set_sreg 0xfffff800, x0 -L43: pdmsb x0, x1 - assert_sreg 20<<16, x1 - set_sreg 0xfffff000, x0 -L44: pdmsb x0, x1 - assert_sreg 19<<16, x1 - set_sreg 0xffffe000, x0 -L45: pdmsb x0, x1 - assert_sreg 18<<16, x1 - set_sreg 0xffffc000, x0 -L46: pdmsb x0, x1 - assert_sreg 17<<16, x1 - set_sreg 0xffff8000, x0 -L47: pdmsb x0, x1 - assert_sreg 16<<16, x1 - set_sreg 0xffff0000, x0 -L48: pdmsb x0, x1 - assert_sreg 15<<16, x1 - - set_sreg 0xfffe0000, x0 -L49: pdmsb x0, x1 - assert_sreg 14<<16, x1 - set_sreg 0xfffc0000, x0 -L50: pdmsb x0, x1 - assert_sreg 13<<16, x1 - set_sreg 0xfff80000, x0 -L51: pdmsb x0, x1 - assert_sreg 12<<16, x1 - set_sreg 0xfff00000, x0 -L52: pdmsb x0, x1 - assert_sreg 11<<16, x1 - set_sreg 0xffe00000, x0 -L53: pdmsb x0, x1 - assert_sreg 10<<16, x1 - set_sreg 0xffc00000, x0 -L54: pdmsb x0, x1 - assert_sreg 9<<16, x1 - set_sreg 0xff800000, x0 -L55: pdmsb x0, x1 - assert_sreg 8<<16, x1 - set_sreg 0xff000000, x0 -L56: pdmsb x0, x1 - assert_sreg 7<<16, x1 - - set_sreg 0xfe000000, x0 -L57: pdmsb x0, x1 - assert_sreg 6<<16, x1 - set_sreg 0xfc000000, x0 -L58: pdmsb x0, x1 - assert_sreg 5<<16, x1 - set_sreg 0xf8000000, x0 -L59: pdmsb x0, x1 - assert_sreg 4<<16, x1 - set_sreg 0xf0000000, x0 -L60: pdmsb x0, x1 - assert_sreg 3<<16, x1 - set_sreg 0xe0000000, x0 -L61: pdmsb x0, x1 - assert_sreg 2<<16, x1 - set_sreg 0xc0000000, x0 -L62: pdmsb x0, x1 - assert_sreg 1<<16, x1 - set_sreg 0x80000000, x0 -L63: pdmsb x0, x1 - assert_sreg 0<<16, x1 - set_sreg 0x00000000, x0 -L64: pdmsb x0, x1 -# assert_sreg 31<<16, x1 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pinc.s b/sim/testsuite/sim/sh/pinc.s deleted file mode 100644 index 0067bc0..0000000 --- a/sim/testsuite/sim/sh/pinc.s +++ /dev/null @@ -1,110 +0,0 @@ -# sh testcase for pinc -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -pincx: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pinc x0, y0 - assert_sreg 0xa5a60000, y0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -pincy: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pinc y0, x0 - assert_sreg 0xa5a60000, x0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -dct_pincx: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_dcfalse - dct pinc x0, y0 - assert_sreg 0xa5a5a5a5, y0 - set_dctrue - dct pinc x0, y0 - assert_sreg 0xa5a60000, y0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -dcf_pincy: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_dctrue - dcf pinc y0, x0 - assert_sreg 0xa5a5a5a5, x0 - set_dcfalse - dcf pinc y0, x0 - assert_sreg 0xa5a60000, x0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pmuls.s b/sim/testsuite/sim/sh/pmuls.s deleted file mode 100644 index 4cff878..0000000 --- a/sim/testsuite/sim/sh/pmuls.s +++ /dev/null @@ -1,33 +0,0 @@ -# sh testcase for pmuls -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - # 2 x 2 = 8 (?) - # (I don't understand why the result is x2, - # but that's what it says in the manual...) - mov #2, r0 - shll16 r0 - lds r0, y0 - lds r0, y1 - pmuls y0, y1, a0 - - assert_sreg 8, a0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/prnd.s b/sim/testsuite/sim/sh/prnd.s deleted file mode 100644 index 897d5b9..0000000 --- a/sim/testsuite/sim/sh/prnd.s +++ /dev/null @@ -1,90 +0,0 @@ -# sh testcase for prnd -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - # FIXME: opcode table ambiguity in ignored bits 4-7. - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - # prnd(0xa5a5a5a5) = 0xa5a60000 - prnd x0, x0 - prnd y0, y0 - assert_sreg 0xa5a60000, x0 - assert_sreg 0xa5a60000, y0 - - # prnd(1) = 1 - mov #1, r0 - shll16 r0 - lds r0, x0 - pcopy x0, y0 - prnd x0, x0 - prnd y0, y0 - assert_sreg 0x10000, x0 - assert_sreg 0x10000, y0 - - # prnd(1.4999999) = 1 - mov #1, r0 - shll8 r0 - or #0x7f, r0 - shll8 r0 - or #0xff, r0 - lds r0, x0 - pcopy x0, y0 - prnd x0, x0 - prnd y0, y0 - assert_sreg 0x10000, x0 - assert_sreg 0x10000, y0 - - # prnd(1.5) = 2 - mov #1, r0 - shll8 r0 - or #0x80, r0 - shll8 r0 - lds r0, x0 - pcopy x0, y0 - prnd x0, x0 - prnd y0, y0 - assert_sreg 0x20000, x0 - assert_sreg 0x20000, y0 - - # dct prnd - set_dcfalse - dct prnd x0, x1 - dct prnd y0, y1 - assert_sreg2 0xa5a5a5a5, x1 - assert_sreg2 0xa5a5a5a5, y1 - set_dctrue - dct prnd x0, x1 - dct prnd y0, y1 - assert_sreg2 0x20000, x1 - assert_sreg2 0x20000, y1 - - # dcf prnd - set_dctrue - dcf prnd x0, m0 - dcf prnd y0, m1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - set_dcfalse - dcf prnd x0, m0 - dcf prnd y0, m1 - assert_sreg2 0x20000, m0 - assert_sreg2 0x20000, m1 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pshai.s b/sim/testsuite/sim/sh/pshai.s deleted file mode 100644 index b2cdbbc..0000000 --- a/sim/testsuite/sim/sh/pshai.s +++ /dev/null @@ -1,200 +0,0 @@ -# sh testcase for psha -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -psha_imm: ! shift arithmetic, immediate operand - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_sreg 0x1, a0 - psha #0, a0 - assert_sreg 0x1, a0 - psha #-0, a0 - assert_sreg 0x1, a0 - - psha #1, a0 - assert_sreg 0x2, a0 - psha #-1, a0 - assert_sreg 0x1, a0 - - psha #2, a0 - assert_sreg 0x4, a0 - psha #-2, a0 - assert_sreg 0x1, a0 - - psha #3, a0 - assert_sreg 0x8, a0 - psha #-3, a0 - assert_sreg 0x1, a0 - - psha #4, a0 - assert_sreg 0x10, a0 - psha #-4, a0 - assert_sreg 0x1, a0 - - psha #5, a0 - assert_sreg 0x20, a0 - psha #-5, a0 - assert_sreg 0x1, a0 - - psha #6, a0 - assert_sreg 0x40, a0 - psha #-6, a0 - assert_sreg 0x1, a0 - - psha #7, a0 - assert_sreg 0x80, a0 - psha #-7, a0 - assert_sreg 0x1, a0 - - psha #8, a0 - assert_sreg 0x100, a0 - psha #-8, a0 - assert_sreg 0x1, a0 - - psha #9, a0 - assert_sreg 0x200, a0 - psha #-9, a0 - assert_sreg 0x1, a0 - - psha #10, a0 - assert_sreg 0x400, a0 - psha #-10, a0 - assert_sreg 0x1, a0 - - psha #11, a0 - assert_sreg 0x800, a0 - psha #-11, a0 - assert_sreg 0x1, a0 - - psha #12, a0 - assert_sreg 0x1000, a0 - psha #-12, a0 - assert_sreg 0x1, a0 - - psha #13, a0 - assert_sreg 0x2000, a0 - psha #-13, a0 - assert_sreg 0x1, a0 - - psha #14, a0 - assert_sreg 0x4000, a0 - psha #-14, a0 - assert_sreg 0x1, a0 - - psha #15, a0 - assert_sreg 0x8000, a0 - psha #-15, a0 - assert_sreg 0x1, a0 - - psha #16, a0 - assert_sreg 0x10000, a0 - psha #-16, a0 - assert_sreg 0x1, a0 - - psha #17, a0 - assert_sreg 0x20000, a0 - psha #-17, a0 - assert_sreg 0x1, a0 - - psha #18, a0 - assert_sreg 0x40000, a0 - psha #-18, a0 - assert_sreg 0x1, a0 - - psha #19, a0 - assert_sreg 0x80000, a0 - psha #-19, a0 - assert_sreg 0x1, a0 - - psha #20, a0 - assert_sreg 0x100000, a0 - psha #-20, a0 - assert_sreg 0x1, a0 - - psha #21, a0 - assert_sreg 0x200000, a0 - psha #-21, a0 - assert_sreg 0x1, a0 - - psha #22, a0 - assert_sreg 0x400000, a0 - psha #-22, a0 - assert_sreg 0x1, a0 - - psha #23, a0 - assert_sreg 0x800000, a0 - psha #-23, a0 - assert_sreg 0x1, a0 - - psha #24, a0 - assert_sreg 0x1000000, a0 - psha #-24, a0 - assert_sreg 0x1, a0 - - psha #25, a0 - assert_sreg 0x2000000, a0 - psha #-25, a0 - assert_sreg 0x1, a0 - - psha #26, a0 - assert_sreg 0x4000000, a0 - psha #-26, a0 - assert_sreg 0x1, a0 - - psha #27, a0 - assert_sreg 0x8000000, a0 - psha #-27, a0 - assert_sreg 0x1, a0 - - psha #28, a0 - assert_sreg 0x10000000, a0 - psha #-28, a0 - assert_sreg 0x1, a0 - - psha #29, a0 - assert_sreg 0x20000000, a0 - psha #-29, a0 - assert_sreg 0x1, a0 - - psha #30, a0 - assert_sreg 0x40000000, a0 - psha #-30, a0 - assert_sreg 0x1, a0 - - psha #31, a0 - assert_sreg 0x80000000, a0 - psha #-31, a0 - assert_sreg 0xffffffff, a0 - - psha #32, a0 - assert_sreg 0x00000000, a0 -# I don't grok what should happen here... -# psha #-32, a0 -# assert_sreg 0x0, a0 - - test_grs_a5a5 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/pshar.s b/sim/testsuite/sim/sh/pshar.s deleted file mode 100644 index 01c4b5f..0000000 --- a/sim/testsuite/sim/sh/pshar.s +++ /dev/null @@ -1,265 +0,0 @@ -# sh testcase for psha -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -psha_reg: ! shift arithmetic, register operand - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_sreg 0x1, x0 - set_sreg 0x0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x10000, y0 - psha x0, y0, x0 - assert_sreg 0x2, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x20000, y0 - psha x0, y0, x0 - assert_sreg 0x4, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x30000, y0 - psha x0, y0, x0 - assert_sreg 0x8, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x40000, y0 - psha x0, y0, x0 - assert_sreg 0x10, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x50000, y0 - psha x0, y0, x0 - assert_sreg 0x20, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x60000, y0 - psha x0, y0, x0 - assert_sreg 0x40, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x70000, y0 - psha x0, y0, x0 - assert_sreg 0x80, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x80000, y0 - psha x0, y0, x0 - assert_sreg 0x100, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x90000, y0 - psha x0, y0, x0 - assert_sreg 0x200, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0xa0000, y0 - psha x0, y0, x0 - assert_sreg 0x400, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0xb0000, y0 - psha x0, y0, x0 - assert_sreg 0x800, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0xc0000, y0 - psha x0, y0, x0 - assert_sreg 0x1000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0xd0000, y0 - psha x0, y0, x0 - assert_sreg 0x2000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0xe0000, y0 - psha x0, y0, x0 - assert_sreg 0x4000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0xf0000, y0 - psha x0, y0, x0 - assert_sreg 0x8000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x100000, y0 - psha x0, y0, x0 - assert_sreg 0x10000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x110000, y0 - psha x0, y0, x0 - assert_sreg 0x20000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x120000, y0 - psha x0, y0, x0 - assert_sreg 0x40000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x130000, y0 - psha x0, y0, x0 - assert_sreg 0x80000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x140000, y0 - psha x0, y0, x0 - assert_sreg 0x100000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x150000, y0 - psha x0, y0, x0 - assert_sreg 0x200000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x160000, y0 - psha x0, y0, x0 - assert_sreg 0x400000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x170000, y0 - psha x0, y0, x0 - assert_sreg 0x800000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x180000, y0 - psha x0, y0, x0 - assert_sreg 0x1000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x190000, y0 - psha x0, y0, x0 - assert_sreg 0x2000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x1a0000, y0 - psha x0, y0, x0 - assert_sreg 0x4000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x1b0000, y0 - psha x0, y0, x0 - assert_sreg 0x8000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x1c0000, y0 - psha x0, y0, x0 - assert_sreg 0x10000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x1d0000, y0 - psha x0, y0, x0 - assert_sreg 0x20000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x1e0000, y0 - psha x0, y0, x0 - assert_sreg 0x40000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x1f0000, y0 - psha x0, y0, x0 - assert_sreg 0x80000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0xffffffff, x0 - - set_sreg 0x200000, y0 - psha x0, y0, x0 - assert_sreg 0x00000000, x0 -# I don't grok what should happen here... -# pneg y0, y0 -# psha x0, y0, x0 -# assert_sreg 0x0, x0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/pshli.s b/sim/testsuite/sim/sh/pshli.s deleted file mode 100644 index a6616e8..0000000 --- a/sim/testsuite/sim/sh/pshli.s +++ /dev/null @@ -1,119 +0,0 @@ -# sh testcase for pshl -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -pshl_imm: ! shift logical, immediate operand - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_sreg 0x10000, a0 - pshl #0, a0 - assert_sreg 0x10000, a0 - pshl #-0, a0 - assert_sreg 0x10000, a0 - - pshl #1, a0 - assert_sreg 0x20000, a0 - pshl #-1, a0 - assert_sreg 0x10000, a0 - - pshl #2, a0 - assert_sreg 0x40000, a0 - pshl #-2, a0 - assert_sreg 0x10000, a0 - - pshl #3, a0 - assert_sreg 0x80000, a0 - pshl #-3, a0 - assert_sreg 0x10000, a0 - - pshl #4, a0 - assert_sreg 0x100000, a0 - pshl #-4, a0 - assert_sreg 0x10000, a0 - - pshl #5, a0 - assert_sreg 0x200000, a0 - pshl #-5, a0 - assert_sreg 0x10000, a0 - - pshl #6, a0 - assert_sreg 0x400000, a0 - pshl #-6, a0 - assert_sreg 0x10000, a0 - - pshl #7, a0 - assert_sreg 0x800000, a0 - pshl #-7, a0 - assert_sreg 0x10000, a0 - - pshl #8, a0 - assert_sreg 0x1000000, a0 - pshl #-8, a0 - assert_sreg 0x10000, a0 - - pshl #9, a0 - assert_sreg 0x2000000, a0 - pshl #-9, a0 - assert_sreg 0x10000, a0 - - pshl #10, a0 - assert_sreg 0x4000000, a0 - pshl #-10, a0 - assert_sreg 0x10000, a0 - - pshl #11, a0 - assert_sreg 0x8000000, a0 - pshl #-11, a0 - assert_sreg 0x10000, a0 - - pshl #12, a0 - assert_sreg 0x10000000, a0 - pshl #-12, a0 - assert_sreg 0x10000, a0 - - pshl #13, a0 - assert_sreg 0x20000000, a0 - pshl #-13, a0 - assert_sreg 0x10000, a0 - - pshl #14, a0 - assert_sreg 0x40000000, a0 - pshl #-14, a0 - assert_sreg 0x10000, a0 - - pshl #15, a0 - assert_sreg 0x80000000, a0 - pshl #-15, a0 - assert_sreg 0x10000, a0 - - pshl #16, a0 - assert_sreg 0x00000000, a0 - pshl #-16, a0 - assert_sreg 0x0, a0 - - test_grs_a5a5 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/pshlr.s b/sim/testsuite/sim/sh/pshlr.s deleted file mode 100644 index 36cb47f..0000000 --- a/sim/testsuite/sim/sh/pshlr.s +++ /dev/null @@ -1,152 +0,0 @@ -# sh testcase for pshl -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -pshl_reg: ! shift arithmetic, register operand - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_sreg 0x10000, x0 - set_sreg 0x0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x10000, y0 - pshl x0, y0, x0 - assert_sreg 0x20000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x20000, y0 - pshl x0, y0, x0 - assert_sreg 0x40000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x30000, y0 - pshl x0, y0, x0 - assert_sreg 0x80000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x40000, y0 - pshl x0, y0, x0 - assert_sreg 0x100000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x50000, y0 - pshl x0, y0, x0 - assert_sreg 0x200000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x60000, y0 - pshl x0, y0, x0 - assert_sreg 0x400000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x70000, y0 - pshl x0, y0, x0 - assert_sreg 0x800000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x80000, y0 - pshl x0, y0, x0 - assert_sreg 0x1000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x90000, y0 - pshl x0, y0, x0 - assert_sreg 0x2000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0xa0000, y0 - pshl x0, y0, x0 - assert_sreg 0x4000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0xb0000, y0 - pshl x0, y0, x0 - assert_sreg 0x8000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0xc0000, y0 - pshl x0, y0, x0 - assert_sreg 0x10000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0xd0000, y0 - pshl x0, y0, x0 - assert_sreg 0x20000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0xe0000, y0 - pshl x0, y0, x0 - assert_sreg 0x40000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0xf0000, y0 - pshl x0, y0, x0 - assert_sreg 0x80000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x100000, y0 - pshl x0, y0, x0 - assert_sreg 0x00000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x0, x0 - - test_grs_a5a5 - assert_sreg2 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/psub.s b/sim/testsuite/sim/sh/psub.s deleted file mode 100644 index bcfd26e..0000000 --- a/sim/testsuite/sim/sh/psub.s +++ /dev/null @@ -1,64 +0,0 @@ -# sh testcase for psub -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - -psub_sx_sy: - # 0xa5a5a5a5 minus 0xa5a5a5a5 equals zero - psub x0, y0, a0 - assert_sreg 0, a0 - -psub_sy_sx: - # 100 - 25 = 75 - mov #100, r0 - mov #25, r1 - lds r0, y1 - lds r1, x1 - psub y1, x1, a0 - assert_sreg 75, a0 - -dct_psub: - # 100 - 25 = 75 - set_dcfalse - dct psub y1, x1, a1 - assert_sreg2 0xa5a5a5a5, a1 - set_dctrue - dct psub y1, x1, a1 - assert_sreg2 75, a1 - -dcf_psub: - # 25 - 100 = -75 - set_dctrue - dcf psub x1, y1, m1 - assert_sreg2 0xa5a5a5a5, m1 - set_dcfalse - dcf psub x1, y1, m1 - assert_sreg2 -75, m1 - -psub_pmuls: - # 25 - 100 = -75, and 2 x 2 = 8 (yes, eight, not four) - mov #2, r0 - shll16 r0 - lds r0, x0 - lds r0, y0 - psub x1, y1, a1 pmuls x0, y0, a0 - assert_sreg 8, a0 - assert_sreg2 -75, a1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pswap.s b/sim/testsuite/sim/sh/pswap.s deleted file mode 100644 index 5bd6a59..0000000 --- a/sim/testsuite/sim/sh/pswap.s +++ /dev/null @@ -1,177 +0,0 @@ -# sh testcase for pswap -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -pswapx: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_greg 0xa5a57777, r0 - lds r0, x0 - pswap x0, y0 - assert_sreg 0x7777a5a5, y0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a57777, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -pswapy: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_greg 0xa5a57777, r0 - lds r0, y0 - pswap y0, x0 - assert_sreg 0x7777a5a5, x0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a57777, y0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -pswapa: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_greg 0xa5a57777, r0 - lds r0, a0 - pcopy a0, a1 - pswap a1, y0 - assert_sreg 0x7777a5a5, y0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a57777, a0 - assert_sreg2 0xa5a57777, a1 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -pswapm: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_greg 0xa5a57777, r0 - lds r0, a0 - pcopy a0, m1 - pswap m1, y0 - assert_sreg 0x7777a5a5, y0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a57777, a0 - assert_sreg2 0xa5a57777, m1 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - - -dct_pswapx: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_greg 0xa5a57777, r0 - lds r0, x0 - set_dcfalse - dct pswap x0, y0 - assert_sreg 0xa5a5a5a5, y0 - set_dctrue - dct pswap x0, y0 - assert_sreg 0x7777a5a5, y0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a57777, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -dcf_pswapy: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_greg 0xa5a57777, r0 - lds r0, x0 - set_dctrue - dcf pswap x0, y0 - assert_sreg 0xa5a5a5a5, y0 - set_dcfalse - dcf pswap x0, y0 - assert_sreg 0x7777a5a5, y0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a57777, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pushpop.s b/sim/testsuite/sim/sh/pushpop.s deleted file mode 100644 index 9ee5bfd..0000000 --- a/sim/testsuite/sim/sh/pushpop.s +++ /dev/null @@ -1,146 +0,0 @@ -# sh testcase for push/pop (mov,movml,movmu...) insns. -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start -movml_1: - set_greg 0, r0 - set_greg 1, r1 - set_greg 2, r2 - set_greg 3, r3 - set_greg 4, r4 - set_greg 5, r5 - set_greg 6, r6 - set_greg 7, r7 - set_greg 8, r8 - set_greg 9, r9 - set_greg 10, r10 - set_greg 11, r11 - set_greg 12, r12 - set_greg 13, r13 - set_greg 14, r14 - set_sreg 15, pr - - movml.l r15,@-r15 - - assertmem stackt-4, 15 - assertmem stackt-8, 14 - assertmem stackt-12, 13 - assertmem stackt-16, 12 - assertmem stackt-20, 11 - assertmem stackt-24, 10 - assertmem stackt-28, 9 - assertmem stackt-32, 8 - assertmem stackt-36, 7 - assertmem stackt-40, 6 - assertmem stackt-44, 5 - assertmem stackt-48, 4 - assertmem stackt-52, 3 - assertmem stackt-56, 2 - assertmem stackt-60, 1 - assertmem stackt-64, 0 - - assertreg0 0 - assertreg 1, r1 - assertreg 2, r2 - assertreg 3, r3 - assertreg 4, r4 - assertreg 5, r5 - assertreg 6, r6 - assertreg 7, r7 - assertreg 8, r8 - assertreg 9, r9 - assertreg 10, r10 - assertreg 11, r11 - assertreg 12, r12 - assertreg 13, r13 - assertreg 14, r14 - mov r15, r0 - assertreg0 stackt-64 - -movml_2: - set_grs_a5a5 - movml.l @r15+, r15 - assert_sreg 15, pr - assertreg0 0 - assertreg 1, r1 - assertreg 2, r2 - assertreg 3, r3 - assertreg 4, r4 - assertreg 5, r5 - assertreg 6, r6 - assertreg 7, r7 - assertreg 8, r8 - assertreg 9, r9 - assertreg 10, r10 - assertreg 11, r11 - assertreg 12, r12 - assertreg 13, r13 - assertreg 14, r14 - mov r15, r0 - assertreg0 stackt - -movmu_1: - set_grs_a5a5 - add #1,r14 - add #2,r13 - add #3,r12 - set_sreg 0xa5a5,pr - - movmu.l r12,@-r15 - - assert_sreg 0xa5a5,pr - assertreg 0xa5a5a5a6, r14 - assertreg 0xa5a5a5a7, r13 - assertreg 0xa5a5a5a8, r12 - test_gr_a5a5 r11 - test_gr_a5a5 r10 - test_gr_a5a5 r9 - test_gr_a5a5 r8 - test_gr_a5a5 r7 - test_gr_a5a5 r6 - test_gr_a5a5 r5 - test_gr_a5a5 r4 - test_gr_a5a5 r3 - test_gr_a5a5 r2 - test_gr_a5a5 r1 - test_gr_a5a5 r0 - mov r15, r0 - assertreg stackt-16, r0 - - assertmem stackt-4, 0xa5a5 - assertmem stackt-8, 0xa5a5a5a6 - assertmem stackt-12, 0xa5a5a5a7 - assertmem stackt-16, 0xa5a5a5a8 - -movmu_2: - set_grs_a5a5 - movmu.l @r15+,r12 - - assert_sreg 0xa5a5, pr - assertreg 0xa5a5a5a6, r14 - assertreg 0xa5a5a5a7, r13 - assertreg 0xa5a5a5a8, r12 - test_gr_a5a5 r11 - test_gr_a5a5 r10 - test_gr_a5a5 r9 - test_gr_a5a5 r8 - test_gr_a5a5 r7 - test_gr_a5a5 r6 - test_gr_a5a5 r5 - test_gr_a5a5 r4 - test_gr_a5a5 r3 - test_gr_a5a5 r2 - test_gr_a5a5 r1 - test_gr_a5a5 r0 - mov r15, r0 - assertreg stackt, r0 - - pass - - exit 0 - - \ No newline at end of file diff --git a/sim/testsuite/sim/sh/resbank.s b/sim/testsuite/sim/sh/resbank.s deleted file mode 100644 index 33801b8..0000000 --- a/sim/testsuite/sim/sh/resbank.s +++ /dev/null @@ -1,268 +0,0 @@ -# sh testcase for ldbank stbank resbank -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .macro SEND reg bankno regno - set_greg ((\bankno << 7) + (\regno << 2)), \reg - .endm - - start - -stbank_1: - set_grs_a5a5 - mov #0, r0 - SEND r1, 0, 0 - stbank r0, @r1 - mov #1, r0 - SEND r1, 0, 1 - stbank r0, @r1 - mov #2, r0 - SEND r1, 0, 2 - stbank r0, @r1 - mov #3, r0 - SEND r1, 0, 3 - stbank r0, @r1 - mov #4, r0 - SEND r1, 0, 4 - stbank r0, @r1 - mov #5, r0 - SEND r1, 0, 5 - stbank r0, @r1 - mov #6, r0 - SEND r1, 0, 6 - stbank r0, @r1 - mov #7, r0 - SEND r1, 0, 7 - stbank r0, @r1 - mov #8, r0 - SEND r1, 0, 8 - stbank r0, @r1 - mov #9, r0 - SEND r1, 0, 9 - stbank r0, @r1 - mov #10, r0 - SEND r1, 0, 10 - stbank r0, @r1 - mov #11, r0 - SEND r1, 0, 11 - stbank r0, @r1 - mov #12, r0 - SEND r1, 0, 12 - stbank r0, @r1 - mov #13, r0 - SEND r1, 0, 13 - stbank r0, @r1 - mov #14, r0 - SEND r1, 0, 14 - stbank r0, @r1 - mov #15, r0 - SEND r1, 0, 15 - stbank r0, @r1 - mov #16, r0 - SEND r1, 0, 16 - stbank r0, @r1 - mov #17, r0 - SEND r1, 0, 17 - stbank r0, @r1 - mov #18, r0 - SEND r1, 0, 18 - stbank r0, @r1 - mov #19, r0 - SEND r1, 0, 19 - stbank r0, @r1 - - assertreg0 19 - assertreg 19 << 2, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -ldbank_1: - set_grs_a5a5 - SEND r1, 0, 0 - ldbank @r1, r0 - assertreg0 0 - SEND r1, 0, 1 - ldbank @r1, r0 - assertreg0 1 - SEND r1, 0, 2 - ldbank @r1, r0 - assertreg0 2 - SEND r1, 0, 3 - ldbank @r1, r0 - assertreg0 3 - SEND r1, 0, 4 - ldbank @r1, r0 - assertreg0 4 - SEND r1, 0, 5 - ldbank @r1, r0 - assertreg0 5 - SEND r1, 0, 6 - ldbank @r1, r0 - assertreg0 6 - SEND r1, 0, 7 - ldbank @r1, r0 - assertreg0 7 - SEND r1, 0, 8 - ldbank @r1, r0 - assertreg0 8 - SEND r1, 0, 9 - ldbank @r1, r0 - assertreg0 9 - SEND r1, 0, 10 - ldbank @r1, r0 - assertreg0 10 - SEND r1, 0, 11 - ldbank @r1, r0 - assertreg0 11 - SEND r1, 0, 12 - ldbank @r1, r0 - assertreg0 12 - SEND r1, 0, 13 - ldbank @r1, r0 - assertreg0 13 - SEND r1, 0, 14 - ldbank @r1, r0 - assertreg0 14 - SEND r1, 0, 15 - ldbank @r1, r0 - assertreg0 15 - SEND r1, 0, 16 - ldbank @r1, r0 - assertreg0 16 - SEND r1, 0, 17 - ldbank @r1, r0 - assertreg0 17 - SEND r1, 0, 18 - ldbank @r1, r0 - assertreg0 18 - SEND r1, 0, 19 - ldbank @r1, r0 - assertreg0 19 - - assertreg (19 << 2), r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -resbank_1: - set_grs_a5a5 - mov #1, r0 - trapa #13 ! magic trap, sets ibnr - - resbank - - assertreg0 0 - assertreg 1, r1 - assertreg 2, r2 - assertreg 3, r3 - assertreg 4, r4 - assertreg 5, r5 - assertreg 6, r6 - assertreg 7, r7 - assertreg 8, r8 - assertreg 9, r9 - assertreg 10, r10 - assertreg 11, r11 - assertreg 12, r12 - assertreg 13, r13 - assertreg 14, r14 - assert_sreg 15, mach - assert_sreg 17, pr - assert_creg 18, gbr - assert_sreg 19, macl - -resbank_2: - set_grs_a5a5 - movi20 #555, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - add #-1, r0 - mov.l r0, @-r15 - - set_sr_bit (1 << 14) ! set BO - - resbank - - assert_sreg 555, macl - assert_sreg 554, mach - assert_creg 553, gbr - assert_sreg 552, pr - assertreg 551, r14 - assertreg 550, r13 - assertreg 549, r12 - assertreg 548, r11 - assertreg 547, r10 - assertreg 546, r9 - assertreg 545, r8 - assertreg 544, r7 - assertreg 543, r6 - assertreg 542, r5 - assertreg 541, r4 - assertreg 540, r3 - assertreg 539, r2 - assertreg 538, r1 - assertreg0 537 - - mov r15, r0 - assertreg0 stackt - - pass - - exit 0 diff --git a/sim/testsuite/sim/sh/sett.s b/sim/testsuite/sim/sh/sett.s deleted file mode 100644 index fff2d2d..0000000 --- a/sim/testsuite/sim/sh/sett.s +++ /dev/null @@ -1,65 +0,0 @@ -# sh testcase for sett, clrt, movt -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start -sett_1: set_grs_a5a5 - sett - bt .Lsett - nop - fail -.Lsett: - test_grs_a5a5 - -clrt_1: set_grs_a5a5 - clrt - bf .Lclrt - nop - fail -.Lclrt: - test_grs_a5a5 - -movt_1: set_grs_a5a5 - sett - movt r1 - test_gr_a5a5 r0 - assertreg 1, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -movt_2: set_grs_a5a5 - clrt - movt r1 - test_gr_a5a5 r0 - assertreg 0, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 diff --git a/sim/testsuite/sim/sh/shll.s b/sim/testsuite/sim/sh/shll.s deleted file mode 100644 index ec2ea12..0000000 --- a/sim/testsuite/sim/sh/shll.s +++ /dev/null @@ -1,91 +0,0 @@ -# sh testcase for shll -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shll: - set_grs_a5a5 - mov #1, r1 - shll r1 - assertreg 2, r1 - shll r1 - assertreg 4, r1 - shll r1 - assertreg 8, r1 - shll r1 - assertreg 16, r1 - shll r1 - assertreg 32, r1 - shll r1 - assertreg 64, r1 - shll r1 - assertreg 0x80, r1 - shll r1 - assertreg 0x100, r1 - shll r1 - assertreg 0x200, r1 - shll r1 - assertreg 0x400, r1 - shll r1 - assertreg 0x800, r1 - shll r1 - assertreg 0x1000, r1 - shll r1 - assertreg 0x2000, r1 - shll r1 - assertreg 0x4000, r1 - shll r1 - assertreg 0x8000, r1 - shll r1 - assertreg 0x10000, r1 - shll r1 - assertreg 0x20000, r1 - shll r1 - assertreg 0x40000, r1 - shll r1 - assertreg 0x80000, r1 - shll r1 - assertreg 0x100000, r1 - shll r1 - assertreg 0x200000, r1 - shll r1 - assertreg 0x400000, r1 - shll r1 - assertreg 0x800000, r1 - shll r1 - assertreg 0x1000000, r1 - shll r1 - assertreg 0x2000000, r1 - shll r1 - assertreg 0x4000000, r1 - shll r1 - assertreg 0x8000000, r1 - shll r1 - assertreg 0x10000000, r1 - shll r1 - assertreg 0x20000000, r1 - shll r1 - assertreg 0x40000000, r1 - shll r1 - assertreg 0x80000000, r1 - shll r1 - assertreg 0, r1 - shll r1 - assertreg 0, r1 - - # another: - mov #1, r1 - shll r1 - shll r1 - shll r1 - assertreg 8, r1 - - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/shll16.s b/sim/testsuite/sim/sh/shll16.s deleted file mode 100644 index 4574835..0000000 --- a/sim/testsuite/sim/sh/shll16.s +++ /dev/null @@ -1,46 +0,0 @@ -# sh testcase for shll16 -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shll16: - set_grs_a5a5 - mov #0x18, r1 - shll16 r1 - assertreg 0x180000, r1 - shll16 r1 - assertreg 0, r1 - - # another: - mov #1, r1 - shll16 r1 - mov #1, r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - cmp/eq r1, r7 - bt okay - fail -okay: - set_greg 0xa5a5a5a5, r1 - set_greg 0xa5a5a5a5, r7 - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/shll2.s b/sim/testsuite/sim/sh/shll2.s deleted file mode 100644 index 01a784c..0000000 --- a/sim/testsuite/sim/sh/shll2.s +++ /dev/null @@ -1,51 +0,0 @@ -# sh testcase for shll2 -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shll2: - set_grs_a5a5 - mov #1, r1 - shll2 r1 - assertreg 4, r1 - shll2 r1 - assertreg 16, r1 - shll2 r1 - assertreg 64, r1 - shll2 r1 - assertreg 0x100, r1 - shll2 r1 - assertreg 0x400, r1 - shll2 r1 - assertreg 0x1000, r1 - shll2 r1 - assertreg 0x4000, r1 - shll2 r1 - assertreg 0x10000, r1 - shll2 r1 - assertreg 0x40000, r1 - shll2 r1 - assertreg 0x100000, r1 - shll2 r1 - assertreg 0x400000, r1 - shll2 r1 - assertreg 0x1000000, r1 - shll2 r1 - assertreg 0x4000000, r1 - shll2 r1 - assertreg 0x10000000, r1 - shll2 r1 - assertreg 0x40000000, r1 - shll2 r1 - assertreg 0, r1 - - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/shll8.s b/sim/testsuite/sim/sh/shll8.s deleted file mode 100644 index 71e241d..0000000 --- a/sim/testsuite/sim/sh/shll8.s +++ /dev/null @@ -1,42 +0,0 @@ -# sh testcase for shll8 -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shll8: - set_grs_a5a5 - mov #1, r1 - shll8 r1 - assertreg 0x100, r1 - shll8 r1 - assertreg 0x10000, r1 - shll8 r1 - assertreg 0x1000000, r1 - shll8 r1 - assertreg 0, r1 - - # another: - mov #1, r1 - shll8 r1 - mov #1, r2 - shll r2 - shll r2 - shll r2 - shll r2 - shll r2 - shll r2 - shll r2 - shll r2 - cmp/eq r1, r2 - bt okay - fail -okay: - set_greg 0xa5a5a5a5, r1 - set_greg 0xa5a5a5a5, r2 - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/shlr.s b/sim/testsuite/sim/sh/shlr.s deleted file mode 100644 index 8755afb..0000000 --- a/sim/testsuite/sim/sh/shlr.s +++ /dev/null @@ -1,42 +0,0 @@ -# sh testcase for shlr -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shlr: - set_grs_a5a5 - mov #0, r0 - or #192, r0 - shlr r0 - assertreg0 96 - shlr r0 - assertreg0 48 - shlr r0 - assertreg0 24 - shlr r0 - assertreg0 12 - shlr r0 - assertreg0 6 - shlr r0 - assertreg0 3 - - # Make sure a bit is shifted into T. - shlr r0 - bf wrong - assertreg0 1 - # Ditto. - shlr r0 - bf wrong - assertreg0 0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - pass - exit 0 - -wrong: - fail diff --git a/sim/testsuite/sim/sh/shlr16.s b/sim/testsuite/sim/sh/shlr16.s deleted file mode 100644 index 1161c66..0000000 --- a/sim/testsuite/sim/sh/shlr16.s +++ /dev/null @@ -1,20 +0,0 @@ -# sh testcase for shlr16 -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shrl16: - set_grs_a5a5 - shlr16 r0 - assertreg0 0xa5a5 - shlr16 r0 - assertreg0 0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/shlr2.s b/sim/testsuite/sim/sh/shlr2.s deleted file mode 100644 index ce554dd..0000000 --- a/sim/testsuite/sim/sh/shlr2.s +++ /dev/null @@ -1,48 +0,0 @@ -# sh testcase for shlr2 -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shrl2: - set_grs_a5a5 - shlr2 r0 - assertreg0 0x29696969 - shlr2 r0 - assertreg0 0x0a5a5a5a - shlr2 r0 - assertreg0 0x02969696 - shlr2 r0 - assertreg0 0x00a5a5a5 - shlr2 r0 - assertreg0 0x00296969 - shlr2 r0 - assertreg0 0x000a5a5a - shlr2 r0 - assertreg0 0x00029696 - shlr2 r0 - assertreg0 0x0000a5a5 - shlr2 r0 - assertreg0 0x00002969 - shlr2 r0 - assertreg0 0x00000a5a - shlr2 r0 - assertreg0 0x00000296 - shlr2 r0 - assertreg0 0x000000a5 - shlr2 r0 - assertreg0 0x00000029 - shlr2 r0 - assertreg0 0x0000000a - shlr2 r0 - assertreg0 0x00000002 - shlr2 r0 - assertreg0 0 - - set_greg 0xa5a5a5a5 r0 - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/shlr8.s b/sim/testsuite/sim/sh/shlr8.s deleted file mode 100644 index d609af1..0000000 --- a/sim/testsuite/sim/sh/shlr8.s +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for shlr8 -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shrl8: - set_grs_a5a5 - shlr8 r0 - assertreg0 0xa5a5a5 - shlr8 r0 - assertreg0 0xa5a5 - shlr8 r0 - assertreg0 0xa5 - shlr8 r0 - assertreg0 0x0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/swap.s b/sim/testsuite/sim/sh/swap.s deleted file mode 100644 index 4dd6572..0000000 --- a/sim/testsuite/sim/sh/swap.s +++ /dev/null @@ -1,59 +0,0 @@ -# sh testcase for swap -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -swapb: - set_grs_a5a5 - mov #0x5a, r0 - shll8 r0 - or #0xa5, r0 - assertreg0 0x5aa5 - - swap.b r0, r1 - assertreg 0xa55a, r1 - - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -swapw: - set_grs_a5a5 - mov #0x5a, r0 - shll16 r0 - or #0xa5, r0 - assertreg0 0x5a00a5 - - swap.w r0, r1 - assertreg 0xa5005a, r1 - - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/testutils.inc b/sim/testsuite/sim/sh/testutils.inc deleted file mode 100644 index c9644b4..0000000 --- a/sim/testsuite/sim/sh/testutils.inc +++ /dev/null @@ -1,617 +0,0 @@ -# Support macros for the sh assembly test cases. - - .equ no_dsp, 0 - .equ yes_dsp, 1 - - .section .rodata - .align 2 -_pass: .string "pass\n" -_fail: .string "fail\n" -_stack: .fill 128, 4, 0 -stackt: - - .macro push reg - mov.l \reg, @-r15 - .endm - - .macro pop reg - mov.l @r15+, \reg - .endm - - .macro start - .text - .align 1 - .global start -start: mov.l stackp, r15 - bra main - nop - .align 2 -stackp: .long stackt -mpass: - mov #4, r4 - mov #1, r5 - mov.l ppass, r6 - mov #5, r7 - trapa #34 - rts - nop -mfail: - mov #4, r4 - mov #1, r5 - mov.l pfail, r6 - mov #5, r7 - trapa #34 - mov #1, r5 -mexit: - mov #1, r4 - mov #0, r6 - mov #0, r7 - trapa #34 - .align 2 -ppass: .long _pass -pfail: .long _fail - -mtesta5: - push r0 - mov.l a5a5, r0 - cmp/eq r1, r0 - bf mfail - cmp/eq r2, r0 - bf mfail - cmp/eq r3, r0 - bf mfail - cmp/eq r4, r0 - bf mfail - cmp/eq r5, r0 - bf mfail - cmp/eq r6, r0 - bf mfail - cmp/eq r7, r0 - bf mfail - cmp/eq r8, r0 - bf mfail - cmp/eq r9, r0 - bf mfail - cmp/eq r10, r0 - bf mfail - cmp/eq r11, r0 - bf mfail - cmp/eq r12, r0 - bf mfail - cmp/eq r13, r0 - bf mfail - cmp/eq r14, r0 - bf mfail - # restore and check r0 - pop r0 - cmp/eq r0, r1 - bf mfail - # pass - rts - nop -.if (sim_cpu == no_dsp) -mtesta5_fp: - push r0 - flds fr0, fpul - sts fpul, r0 - push r0 - mov.l a5a5, r0 - lds r0, fpul - fsts fpul, fr0 - fcmp/eq fr1, fr0 - bf mfail - fcmp/eq fr2, fr0 - bf mfail - fcmp/eq fr3, fr0 - bf mfail - fcmp/eq fr4, fr0 - bf mfail - fcmp/eq fr5, fr0 - bf mfail - fcmp/eq fr6, fr0 - bf mfail - fcmp/eq fr7, fr0 - bf mfail - fcmp/eq fr8, fr0 - bf mfail - fcmp/eq fr9, fr0 - bf mfail - fcmp/eq fr10, fr0 - bf mfail - fcmp/eq fr11, fr0 - bf mfail - fcmp/eq fr12, fr0 - bf mfail - fcmp/eq fr13, fr0 - bf mfail - fcmp/eq fr14, fr0 - bf mfail - fcmp/eq fr15, fr0 - bf mfail - # restore and check fr0 - pop r0 - lds r0, fpul - fsts fpul, fr0 - fcmp/eq fr0, fr1 - bf mfail - # restore r0 and pass - pop r0 - rts - nop -.endif - -mseta5: - mov.l a5a5, r0 - mov.l a5a5, r1 - mov.l a5a5, r2 - mov.l a5a5, r3 - mov.l a5a5, r4 - mov.l a5a5, r5 - mov.l a5a5, r6 - mov.l a5a5, r7 - mov.l a5a5, r8 - mov.l a5a5, r9 - mov.l a5a5, r10 - mov.l a5a5, r11 - mov.l a5a5, r12 - mov.l a5a5, r13 - mov.l a5a5, r14 - rts - nop - -.if (sim_cpu == no_dsp) -mseta5_fp: - push r0 - mov.l a5a5, r0 - lds r0, fpul - fsts fpul, fr0 - fsts fpul, fr1 - fsts fpul, fr2 - fsts fpul, fr3 - fsts fpul, fr4 - fsts fpul, fr5 - fsts fpul, fr6 - fsts fpul, fr7 - fsts fpul, fr8 - fsts fpul, fr9 - fsts fpul, fr10 - fsts fpul, fr11 - fsts fpul, fr12 - fsts fpul, fr13 - fsts fpul, fr14 - fsts fpul, fr15 - pop r0 - rts - nop -.endif - - .align 2 -a5a5: .long 0xa5a5a5a5 -main: - .endm - - .macro exit val - mov #\val, r5 - bra mexit - nop - .endm - - .macro pass - bsr mpass - nop - .endm - - .macro fail - bra mfail - nop - .endm - # Branch if false -- 8k range - .macro bf8k label - bt .Lbf8k\@ - bra \label -.Lbf8k\@: - .endm - - # Branch if true -- 8k range - .macro bt8k label - bf .Lbt8k\@ - bra \label -.Lbt8k\@: - .endm - - # Assert value of register (any general register but r0) - # Preserves r0 on stack, restores it on success. - .macro assertreg val reg - push r0 - mov.l .Larval\@, r0 - cmp/eq r0, \reg - bt .Lar\@ - fail - .align 2 -.Larval\@: - .long \val -.Lar\@: pop r0 - .endm - - # Assert value of register zero - # Preserves r1 on stack, restores it on success. - .macro assertreg0 val - push r1 - mov.l .Lazval\@, r1 - cmp/eq r1, r0 - bt .Laz\@ - fail - .align 2 -.Lazval\@: - .long \val -.Laz\@: pop r1 - .endm - - # Assert value of system register - # [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...] - .macro assert_sreg val reg - push r0 - sts \reg, r0 - assertreg0 \val - pop r0 - .endm - - # Assert value of system register that isn't directly stc-able - # [a1, m0, m1, ...] - .macro assert_sreg2 val reg - push r0 - sts a0, r0 - push r0 - pcopy \reg, a0 - sts a0, r0 - assertreg0 \val - pop r0 - lds r0, a0 - pop r0 - .endm - - # Assert value of control register - # [gbr, vbr, ssr, spc, sgr, dbr, r[0-7]_bank, sr, mod, re, rs, ...] - .macro assert_creg val reg - push r0 - stc \reg, r0 - assertreg0 \val - pop r0 - .endm - - # Assert integer value of fp register - # Preserves r0 on stack, restores it on success - # Assumes single-precision fp mode - .macro assert_fpreg_i val freg - push r0 - ftrc \freg, fpul - sts fpul, r0 - assertreg0 \val - pop r0 - .endm - - # Assert integer value of dp register - # Preserves r0 on stack, restores it on success - # Assumes double-precision fp mode - .macro assert_dpreg_i val dreg - push r0 - ftrc \dreg, fpul - sts fpul, r0 - assertreg0 \val - pop r0 - .endm - - # Assert hex value of fp register - # Preserves r0 on stack, restores it on success - # Assumes single-precision fp mode - .macro assert_fpreg_x val freg - push r0 - flds \freg, fpul - sts fpul, r0 - assertreg0 \val - pop r0 - .endm - - # Set FP bank 0 - # Saves and restores r0 and r1 - .macro bank0 - push r0 - push r1 - mov #32, r1 - shll16 r1 - not r1, r1 - sts fpscr, r0 - and r1, r0 - lds r0, fpscr - pop r1 - pop r0 - .endm - - # Set FP bank 1 - .macro bank1 - push r0 - push r1 - mov #32, r1 - shll16 r1 - sts fpscr, r0 - or r1, r0 - lds r0, fpscr - pop r1 - pop r0 - .endm - - # Set FP 32-bit xfer - .macro sz_32 - push r0 - push r1 - mov #16, r1 - shll16 r1 - not r1, r1 - sts fpscr, r0 - and r1, r0 - lds r0, fpscr - pop r1 - pop r0 - .endm - - # Set FP 64-bit xfer - .macro sz_64 - push r0 - push r1 - mov #16, r1 - shll16 r1 - sts fpscr, r0 - or r1, r0 - lds r0, fpscr - pop r1 - pop r0 - .endm - - # Set FP single precision - .macro single_prec - push r0 - push r1 - mov #8, r1 - shll16 r1 - not r1, r1 - sts fpscr, r0 - and r1, r0 - lds r0, fpscr - pop r1 - pop r0 - .endm - - # Set FP double precision - .macro double_prec - push r0 - push r1 - mov #8, r1 - shll16 r1 - sts fpscr, r0 - or r1, r0 - lds r0, fpscr - pop r1 - pop r0 - .endm - - .macro set_carry - sett - .endm - - .macro set_ovf - sett - .endm - - .macro clear_carry - clrt - .endm - - .macro clear_ovf - clrt - .endm - - # sets, clrs - - - .macro set_grs_a5a5 - bsr mseta5 - nop - .endm - - .macro set_greg val greg - mov.l gregval\@, \greg - bra set_greg\@ - nop - .align 2 -gregval\@: .long \val -set_greg\@: - .endm - - .macro set_fprs_a5a5 - bsr mseta5_fp - nop - .endm - - .macro test_grs_a5a5 - bsr mtesta5 - nop - .endm - - .macro test_fprs_a5a5 - bsr mtesta5_fp - nop - .endm - - .macro test_gr_a5a5 reg - assertreg 0xa5a5a5a5 \reg - .endm - - .macro test_fpr_a5a5 reg - assert_fpreg_x 0xa5a5a5a5 \reg - .endm - - .macro test_gr0_a5a5 - assertreg0 0xa5a5a5a5 - .endm - - # Perform a single to double precision floating point conversion. - # Assumes correct settings of fpscr. - .macro _s2d fpr dpr - flds \fpr, fpul - fcnvsd fpul, \dpr - .endm - - # Manipulate the status register - .macro set_sr val - push r0 - mov.l .Lsrval\@, r0 - ldc r0, sr - pop r0 - bra .Lsetsr\@ - nop - .align 2 -.Lsrval\@: - .long \val -.Lsetsr\@: - .endm - - .macro get_sr reg - stc sr, \reg - .endm - - .macro test_sr val - push r0 - get_sr r0 - assertreg0 \val - pop r0 - .endm - - .macro set_sr_bit val - push r0 - push r1 - get_sr r0 - mov.l .Lsrbitval\@, r1 - or r1, r0 - ldc r0, sr - pop r1 - pop r0 - bra .Lsrbit\@ - nop - .align 2 -.Lsrbitval\@: - .long \val -.Lsrbit\@: - .endm - - .macro test_sr_bit_set val - push r0 - push r1 - get_sr r0 - mov.l .Ltsbsval\@, r1 - tst r1, r0 - bf .Ltsbs\@ - fail - .align 2 -.Ltsbsval\@: - .long \val -.Ltsbs\@: - pop r1 - pop r0 - .endm - - .macro test_sr_bit_clear val - push r0 - push r1 - get_sr r0 - mov.l .Ltsbcval\@, r1 - not r0, r0 - tst r1, r0 - bf .Ltsbc\@ - fail - .align 2 -.Ltsbcval\@: - .long \val -.Ltsbc\@: - pop r1 - pop r0 - .endm - - # Set system registers - .macro set_sreg val reg - # [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...] - push r0 - mov.l .Lssrval\@, r0 - lds r0, \reg - pop r0 - bra .Lssr\@ - nop - .align 2 -.Lssrval\@: - .long \val -.Lssr\@: - .endm - - .macro set_sreg2 val reg - # [a1, m0, m1, ...] - push r0 - sts a0, r0 - push r0 - mov.l .Lssr2val\@, r0 - lds r0, a0 - pcopy a0, \reg - pop r0 - lds r0, a0 - pop r0 - bra .Lssr2_\@ - nop - .align 2 -.Lssr2val\@: - .long \val -.Lssr2_\@: - .endm - - - .macro set_creg val reg - # [gbr, vbr, ssr, spc, sgr, dbr... ] - push r0 - mov.l .Lscrval\@, r0 - ldc r0, \reg - pop r0 - bra .Lscr\@ - nop - .align 2 -.Lscrval\@: - .long \val -.Lscr\@: - .endm - - .macro set_dctrue - push r0 - sts dsr, r0 - or #1, r0 - lds r0, dsr - pop r0 - .endm - - .macro set_dcfalse - push r0 - sts dsr, r0 - not r0, r0 - or #1, r0 - not r0, r0 - lds r0, dsr - pop r0 - .endm - - .macro assertmem addr val - push r0 - mov.l .Laddr\@, r0 - mov.l @r0, r0 - assertreg0 \val - bra .Lam\@ - nop - .align 2 -.Laddr\@: - .long \addr -.Lam\@: pop r0 - .endm diff --git a/sim/testsuite/sim/v850/ChangeLog b/sim/testsuite/sim/v850/ChangeLog deleted file mode 100644 index 2508dfd..0000000 --- a/sim/testsuite/sim/v850/ChangeLog +++ /dev/null @@ -1,19 +0,0 @@ -2008-02-05 DJ Delorie - - * .: New directory. - * allinsns.exp: New. - * bsh.cgs: New. - * div.cgs: New. - * divh.cgs: New. - * divh_3.cgs: New. - * divhu.cgs: New. - * divu.cgs: New. - * sar.cgs: New. - * satadd.cgs: New. - * satsub.cgs: New. - * satsubi.cgs: New. - * satsubr.cgs: New. - * shl.cgs: New. - * shr.cgs: New. - * testutils.cgs: New. - * testutils.inc: New. diff --git a/sim/testsuite/sim/v850/allinsns.exp b/sim/testsuite/sim/v850/allinsns.exp deleted file mode 100644 index f60c3d6..0000000 --- a/sim/testsuite/sim/v850/allinsns.exp +++ /dev/null @@ -1,39 +0,0 @@ -# v850 simulator testsuite. - -if [istarget v850*-*] { - global opt - - # load support procs (none yet) - # load_lib cgen.exp - # all machines - - switch -regexp -- $opt { - .*v850e.* { - set all_machs "v850e" - } - default { - set all_machs "v850" - } - } - # gas doesn't support any '=' option for v850. - #set cpu_option -m - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} - -#foreach var [lsort [info globals]] { -# if [array exists ::$var] { -# puts [format "%-27s %s" $var Array:] -# continue -# } -# puts [format "%-30s %s" $var "[set ::$var]"] -#} - \ No newline at end of file diff --git a/sim/testsuite/sim/v850/bsh.cgs b/sim/testsuite/sim/v850/bsh.cgs deleted file mode 100644 index e9d216e..0000000 --- a/sim/testsuite/sim/v850/bsh.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# v850 bsh -# mach: v850e -# as(v850e): -mv850e - - .include "testutils.inc" - - seti 0x12345678, r1 - bsh r1, r2 - - flags 0 - reg r2, 0x34127856 - -# CY is 1 if one or more bytes in the result half-word is zero, else 0 - - seti 0x12345600, r1 - bsh r1, r2 - flags c - reg r2, 0x34120056 - - seti 0x12340078, r1 - bsh r1, r2 - flags c - reg r2, 0x34127800 - - seti 0x12005678, r1 - bsh r1, r2 - flags 0 - reg r2, 0x00127856 - - seti 0x00345678, r1 - bsh r1, r2 - flags 0 - reg r2, 0x34007856 - -# S is set if the result is negative - - seti 0x00800000, r1 - bsh r1, r2 - flags s + c + z - reg r2, 0x80000000 - -# Z is set if the result is zero -# According to NEC, the Z flag depends on only the lower half-word - - seti 0x00000000, r1 - bsh r1, r2 - flags c + z - reg r2, 0x00000000 - - seti 0xffff0000, r1 - bsh r1, r2 - flags c + s + z - reg r2, 0xffff0000 - - pass diff --git a/sim/testsuite/sim/v850/div.cgs b/sim/testsuite/sim/v850/div.cgs deleted file mode 100644 index 16683f1..0000000 --- a/sim/testsuite/sim/v850/div.cgs +++ /dev/null @@ -1,118 +0,0 @@ -# v850 div -# mach: v850e -# as(v850e): -mv850e - - .include "testutils.inc" - -# Regular division - check signs -# The S flag is based on the quotient, not the remainder - - seti 6, r1 - seti 45, r2 - div r1, r2, r3 - - flags 0 - reg r1, 6 - reg r2, 7 - reg r3, 3 - - seti -6, r1 - seti 45, r2 - div r1, r2, r3 - - flags s - reg r1, -6 - reg r2, -7 - reg r3, 3 - - seti 6, r1 - seti -45, r2 - div r1, r2, r3 - - flags s - reg r1, 6 - reg r2, -7 - reg r3, -3 - - seti -6, r1 - seti -45, r2 - div r1, r2, r3 - - flags 0 - reg r1, -6 - reg r2, 7 - reg r3, -3 - -# If the data is divided by zero, OV=1 and the quotient is undefined. -# According to NEC, the S and Z flags, and the output registers, are -# unchanged. - - noflags - seti 0, r1 - seti 45, r2 - seti 67, r3 - div r1, r2, r3 - - flags v - reg r2, 45 - reg r3, 67 - - allflags - seti 0, r1 - seti 45, r2 - seti 67, r3 - div r1, r2, r3 - - flags sat + c + v + s + z - reg r2, 45 - reg r3, 67 - -# Zero / (N!=0) => normal - - noflags - seti 45, r1 - seti 0, r2 - seti 67, r3 - div r1, r2, r3 - - flags z - reg r1, 45 - reg r2, 0 - reg r3, 0 - -# Test for regular overflow - - noflags - seti -1, r1 - seti 0x80000000, r2 - seti 67, r3 - div r1, r2, r3 - - flags v + s - reg r1, -1 - reg r2, 0x80000000 - reg r3, 0 - -# The Z flag is based on the quotient, not the remainder - - noflags - seti 45, r1 - seti 16, r2 - div r1, r2, r3 - - flags z - reg r2, 0 - reg r3, 16 - -# If the quot and rem registers are the same, the remainder is stored. - - seti 6, r1 - seti 45, r2 - div r1, r2, r2 - - flags 0 - reg r1, 6 - reg r2, 3 - - - pass diff --git a/sim/testsuite/sim/v850/divh.cgs b/sim/testsuite/sim/v850/divh.cgs deleted file mode 100644 index 1cef7f9..0000000 --- a/sim/testsuite/sim/v850/divh.cgs +++ /dev/null @@ -1,96 +0,0 @@ -# v850 divh -# mach: all - - .include "testutils.inc" - -# Regular division - check signs - - seti 6, r1 - seti 45, r2 - divh r1, r2 - - flags 0 - reg r1, 6 - reg r2, 7 - - seti -6, r1 - seti 45, r2 - divh r1, r2 - - flags s - reg r1, -6 - reg r2, -7 - - seti 6, r1 - seti -45, r2 - divh r1, r2 - - flags s - reg r1, 6 - reg r2, -7 - - seti -6, r1 - seti -45, r2 - divh r1, r2 - - flags 0 - reg r1, -6 - reg r2, 7 - -# Only the lower half of the dividend is used - - seti 0x0000fffa, r1 - seti -45, r2 - divh r1, r2 - - flags 0 - reg r1, 0x0000fffa - reg r2, 7 - -# If the data is divhided by zero, OV=1 and the quotient is undefined. -# According to NEC, the S and Z flags, and the output registers, are -# unchanged. - - noflags - seti 0, r1 - seti 45, r2 - seti 67, r3 - divh r1, r2 - - flags v - reg r2, 45 - - allflags - seti 0, r1 - seti 45, r2 - seti 67, r3 - divh r1, r2 - - flags sat + c + v + s + z - reg r2, 45 - -# Zero / (N!=0) => normal - - noflags - seti 45, r1 - seti 0, r2 - seti 67, r3 - divh r1, r2 - - flags z - reg r1, 45 - reg r2, 0 - -# Test for regular overflow - - noflags - seti -1, r1 - seti 0x80000000, r2 - divh r1, r2 - - flags v + s - reg r1, -1 - reg r2, 0x80000000 - - - pass diff --git a/sim/testsuite/sim/v850/divh_3.cgs b/sim/testsuite/sim/v850/divh_3.cgs deleted file mode 100644 index 77d14af..0000000 --- a/sim/testsuite/sim/v850/divh_3.cgs +++ /dev/null @@ -1,130 +0,0 @@ -# v850 divh_3 -# mach: v850e -# as(v850e): -mv850e - - .include "testutils.inc" - -# Regular divhision - check signs -# The S flag is based on the quotient, not the remainder - - seti 6, r1 - seti 45, r2 - divh r1, r2, r3 - - flags 0 - reg r1, 6 - reg r2, 7 - reg r3, 3 - - seti -6, r1 - seti 45, r2 - divh r1, r2, r3 - - flags s - reg r1, -6 - reg r2, -7 - reg r3, 3 - - seti 6, r1 - seti -45, r2 - divh r1, r2, r3 - - flags s - reg r1, 6 - reg r2, -7 - reg r3, -3 - - seti -6, r1 - seti -45, r2 - divh r1, r2, r3 - - flags 0 - reg r1, -6 - reg r2, 7 - reg r3, -3 - -# Only the lower half of the dividend is used - - seti 0x0000fffa, r1 - seti -45, r2 - divh r1, r2, r3 - - flags 0 - reg r1, 0x0000fffa - reg r2, 7 - reg r3, -3 - - -# If the data is divhided by zero, OV=1 and the quotient is undefined. -# According to NEC, the S and Z flags, and the output registers, are -# unchanged. - - noflags - seti 0, r1 - seti 45, r2 - seti 67, r3 - divh r1, r2, r3 - - flags v - reg r2, 45 - reg r3, 67 - - allflags - seti 0, r1 - seti 45, r2 - seti 67, r3 - divh r1, r2, r3 - - flags sat + c + v + s + z - reg r2, 45 - reg r3, 67 - -# Zero / (N!=0) => normal - - noflags - seti 45, r1 - seti 0, r2 - seti 67, r3 - divh r1, r2, r3 - - flags z - reg r1, 45 - reg r2, 0 - reg r3, 0 - -# Test for regular overflow - - noflags - seti -1, r1 - seti 0x80000000, r2 - seti 67, r3 - divh r1, r2, r3 - - flags v + s - reg r1, -1 - reg r2, 0x80000000 - reg r3, 0 - -# The Z flag is based on the quotient, not the remainder - - noflags - seti 45, r1 - seti 16, r2 - divh r1, r2, r3 - - flags z - reg r2, 0 - reg r3, 16 - -# If the quot and rem registers are the same, the remainder is stored. - - seti 6, r1 - seti 45, r2 - divh r1, r2, r2 - - flags 0 - reg r1, 6 - reg r2, 3 - - - pass diff --git a/sim/testsuite/sim/v850/divhu.cgs b/sim/testsuite/sim/v850/divhu.cgs deleted file mode 100644 index 911e96e..0000000 --- a/sim/testsuite/sim/v850/divhu.cgs +++ /dev/null @@ -1,94 +0,0 @@ -# v850 divu -# mach: v850e -# as(v850e): -mv850e - - .include "testutils.inc" - - seti 6, r1 - seti 45, r2 - divu r1, r2, r3 - - flags 0 - reg r1, 6 - reg r2, 7 - reg r3, 3 - - seti 4, r1 - seti 0x40000000, r2 - divu r1, r2, r3 - - flags 0 - reg r1, 4 - reg r2, 0x10000000 - reg r3, 0 - -# Only the lower half of the dividend is used - - seti 0x00010006, r1 - seti 45, r2 - divhu r1, r2, r3 - - flags 0 - reg r1, 0x00010006 - reg r2, 7 - reg r3, 3 - -# If the data is divided by zero, OV=1 and the quotient is undefined. -# According to NEC, the S and Z flags, and the output registers, are -# unchanged. - - noflags - seti 0, r1 - seti 45, r2 - seti 67, r3 - divu r1, r2, r3 - - flags v - reg r2, 45 - reg r3, 67 - - allflags - seti 0, r1 - seti 45, r2 - seti 67, r3 - divu r1, r2, r3 - - flags sat + c + v + s + z - reg r2, 45 - reg r3, 67 - -# Zero / (N!=0) => normal - - noflags - seti 45, r1 - seti 0, r2 - seti 67, r3 - divu r1, r2, r3 - - flags z - reg r1, 45 - reg r2, 0 - reg r3, 0 - -# The Z flag is based on the quotient, not the remainder - - noflags - seti 45, r1 - seti 16, r2 - divu r1, r2, r3 - - flags z - reg r2, 0 - reg r3, 16 - -# If the quot and rem registers are the same, the remainder is stored. - - seti 6, r1 - seti 45, r2 - divu r1, r2, r2 - - flags 0 - reg r1, 6 - reg r2, 3 - - pass diff --git a/sim/testsuite/sim/v850/divu.cgs b/sim/testsuite/sim/v850/divu.cgs deleted file mode 100644 index fb44185..0000000 --- a/sim/testsuite/sim/v850/divu.cgs +++ /dev/null @@ -1,83 +0,0 @@ -# v850 divu -# mach: v850e -# as(v850e): -mv850e - - .include "testutils.inc" - - seti 6, r1 - seti 45, r2 - divu r1, r2, r3 - - flags 0 - reg r1, 6 - reg r2, 7 - reg r3, 3 - - seti 4, r1 - seti 0x40000000, r2 - divu r1, r2, r3 - - flags 0 - reg r1, 4 - reg r2, 0x10000000 - reg r3, 0 - -# If the data is divided by zero, OV=1 and the quotient is undefined. -# According to NEC, the S and Z flags, and the output registers, are -# unchanged. - - noflags - seti 0, r1 - seti 45, r2 - seti 67, r3 - divu r1, r2, r3 - - flags v - reg r2, 45 - reg r3, 67 - - allflags - seti 0, r1 - seti 45, r2 - seti 67, r3 - divu r1, r2, r3 - - flags sat + c + v + s + z - reg r2, 45 - reg r3, 67 - -# Zero / (N!=0) => normal - - noflags - seti 45, r1 - seti 0, r2 - seti 67, r3 - divu r1, r2, r3 - - flags z - reg r1, 45 - reg r2, 0 - reg r3, 0 - -# The Z flag is based on the quotient, not the remainder - - noflags - seti 45, r1 - seti 16, r2 - divu r1, r2, r3 - - flags z - reg r2, 0 - reg r3, 16 - -# If the quot and rem registers are the same, the remainder is stored. - - seti 6, r1 - seti 45, r2 - divu r1, r2, r2 - - flags 0 - reg r1, 6 - reg r2, 3 - - pass diff --git a/sim/testsuite/sim/v850/sar.cgs b/sim/testsuite/sim/v850/sar.cgs deleted file mode 100644 index 4372e6c..0000000 --- a/sim/testsuite/sim/v850/sar.cgs +++ /dev/null @@ -1,91 +0,0 @@ -# v850 sar -# mach: all - - .include "testutils.inc" - -# CY is set to 1 if the bit shifted out last is 1, else 0 -# OV is set to zero. -# Z is set if the result is 0, else 0 - - noflags - seti 4, r1 - seti 0x00000000, r2 - sar r1, r2 - - flags z - reg r2, 0 - - noflags - seti 4, r1 - seti 0x00000001, r2 - sar r1, r2 - - flags z - reg r2, 0 - - noflags - seti 4, r1 - seti 0x00000008, r2 - sar r1, r2 - - flags c + z - reg r2, 0 - - noflags - seti 0x00000000, r2 - sar 4, r2 - - flags z - reg r2, 0 - - noflags - seti 0x00000001, r2 - sar 4, r2 - - flags z - reg r2, 0 - - noflags - seti 0x00000008, r2 - sar 4, r2 - - flags c + z - reg r2, 0 - -# However, if the number of shifts is 0, CY is 0. - - noflags - seti 0, r1 - seti 0xffffffff, r2 - sar r1, r2 - - flags s - reg r2, 0xffffffff - - noflags - seti 0xffffffff, r2 - sar 0, r2 - - flags s - reg r2, 0xffffffff - -# Old MSB is copied as new MSB after shift -# S is 1 if the result is negative, else 0 - - noflags - seti 1, r1 - seti 0x80000000, r2 - sar r1, r2 - - flags s - reg r2, 0xc0000000 - - noflags - seti 1, r1 - seti 0x40000000, r2 - sar r1, r2 - - flags 0 - reg r2, 0x20000000 - - pass diff --git a/sim/testsuite/sim/v850/satadd.cgs b/sim/testsuite/sim/v850/satadd.cgs deleted file mode 100644 index 60ac654..0000000 --- a/sim/testsuite/sim/v850/satadd.cgs +++ /dev/null @@ -1,79 +0,0 @@ -# v850 satadd -# mach: all - - .include "testutils.inc" - -# If the result of the add is "negative", that means we went too -# positive. The result should be the most positive number. - - noflags - seti 0x70000000, r1 - seti 0x70000000, r2 - satadd r1, r2 - - flags sat + nc + v + ns + nz - reg r2, 0x7fffffff - - noflags - seti 0x7ffffffe, r1 - satadd 10, r1 - - flags sat + nc + v + ns + nz - reg r1, 0x7fffffff - -# Similarly, if the result of the add is "positive", that means we -# went too negative. The result should be the most negative number. - - noflags - seti 0x90000000, r1 - seti 0x90000000, r2 - satadd r1, r2 - - flags sat + c + v + s + nz - reg r2, 0x80000000 - - noflags - seti 0x80000001, r1 - satadd -10, r1 - - flags sat + c + v + s + nz - reg r1, 0x80000000 - -# Check that the SAT flag remains set until reset - - seti 1, r1 - seti 2, r2 - satadd r1,r2 - - flags sat + nc + nv + ns + nz - reg r2, 3 - - noflags - seti 1, r1 - seti 2, r2 - satadd r1,r2 - - flags nsat + nc + nv + ns + nz - reg r2, 3 - -# Check that results exactly equal to min/max don't saturate - - noflags - seti 0x70000000, r1 - seti 0x0fffffff, r2 - satadd r1,r2 - - flags nsat + nc + nv + ns + nz - reg r2, 0x7fffffff - - - noflags - seti 0x90000000, r1 - seti 0xf0000000, r2 - satadd r1,r2 - - flags nsat + c + nv + s + nz - reg r2, 0x80000000 - - - pass diff --git a/sim/testsuite/sim/v850/satsub.cgs b/sim/testsuite/sim/v850/satsub.cgs deleted file mode 100644 index b7085e7..0000000 --- a/sim/testsuite/sim/v850/satsub.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# v850 satsub -# mach: all - - .include "testutils.inc" - -# If the result of the add is "negative", that means we went too -# positive. The result should be the most positive number. - - noflags - seti 0x90000000, r1 - seti 0x70000000, r2 - satsub r1, r2 - - flags sat + c + v + ns + nz - reg r2, 0x7fffffff - -# Similarly, if the result of the add is "positive", that means we -# went too negative. The result should be the most negative number. - - noflags - seti 0x70000000, r1 - seti 0x90000000, r2 - satsub r1, r2 - - flags sat + nc + v + s + nz - reg r2, 0x80000000 - -# Check that the SAT flag remains set until reset - - seti 1, r1 - seti 2, r2 - satsub r1,r2 - - flags sat + nc + nv + ns + nz - reg r2, 1 - - noflags - seti 1, r1 - seti 2, r2 - satsub r1,r2 - - flags nsat + nc + nv + ns + nz - reg r2, 1 - -# Check that results exactly equal to min/max don't saturate - - noflags - seti 0x90000000, r1 - seti 0x0fffffff, r2 - satsub r1,r2 - - flags nsat + c + nv + ns + nz - reg r2, 0x7fffffff - - - noflags - seti 0x70000000, r1 - seti 0xf0000000, r2 - satsub r1,r2 - - flags nsat + nc + nv + s + nz - reg r2, 0x80000000 - - - pass diff --git a/sim/testsuite/sim/v850/satsubi.cgs b/sim/testsuite/sim/v850/satsubi.cgs deleted file mode 100644 index b86b26d..0000000 --- a/sim/testsuite/sim/v850/satsubi.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# v850 satsubi -# mach: all - - .include "testutils.inc" - -# If the result of the add is "negative", that means we went too -# positive. The result should be the most positive number. - - noflags - seti 0x7ffffffe, r1 - satsubi -10, r1, r2 - - flags sat + c + v + ns + nz - reg r2, 0x7fffffff - -# Similarly, if the result of the add is "positive", that means we -# went too negative. The result should be the most negative number. - - noflags - seti 0x80000001, r1 - satsubi 10, r1, r2 - - flags sat + nc + v + s + nz - reg r2, 0x80000000 - -# Check that the SAT flag remains set until reset - - seti 2, r1 - satsubi 1, r1, r2 - - flags sat + nc + nv + ns + nz - reg r2, 1 - - noflags - seti 2, r1 - satsubi 1, r1, r2 - - flags nsat + nc + nv + ns + nz - reg r2, 1 - -# Check that results exactly equal to min/max don't saturate - - noflags - seti 0x7ffffffe, r1 - satsubi -1, r1, r2 - - flags nsat + c + nv + ns + nz - reg r2, 0x7fffffff - - - noflags - seti 0x80000001, r1 - satsubi 1, r1, r2 - - flags nsat + nc + nv + s + nz - reg r2, 0x80000000 - - - pass diff --git a/sim/testsuite/sim/v850/satsubr.cgs b/sim/testsuite/sim/v850/satsubr.cgs deleted file mode 100644 index 7e91e0c..0000000 --- a/sim/testsuite/sim/v850/satsubr.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# v850 satsub -# mach: all - - .include "testutils.inc" - -# If the result of the add is "negative", that means we went too -# positive. The result should be the most positive number. - - noflags - seti 0x90000000, r1 - seti 0x70000000, r2 - satsubr r2, r1 - - flags sat + c + v + ns + nz - reg r1, 0x7fffffff - -# Similarly, if the result of the add is "positive", that means we -# went too negative. The result should be the most negative number. - - noflags - seti 0x70000000, r1 - seti 0x90000000, r2 - satsubr r2, r1 - - flags sat + nc + v + s + nz - reg r1, 0x80000000 - -# Check that the SAT flag remains set until reset - - seti 1, r1 - seti 2, r2 - satsubr r2, r1 - - flags sat + nc + nv + ns + nz - reg r1, 1 - - noflags - seti 1, r1 - seti 2, r2 - satsubr r2, r1 - - flags nsat + nc + nv + ns + nz - reg r1, 1 - -# Check that results exactly equal to min/max don't saturate - - noflags - seti 0x90000000, r1 - seti 0x0fffffff, r2 - satsubr r2, r1 - - flags nsat + c + nv + ns + nz - reg r1, 0x7fffffff - - - noflags - seti 0x70000000, r1 - seti 0xf0000000, r2 - satsubr r2, r1 - - flags nsat + nc + nv + s + nz - reg r1, 0x80000000 - - - pass diff --git a/sim/testsuite/sim/v850/shl.cgs b/sim/testsuite/sim/v850/shl.cgs deleted file mode 100644 index 6ad8213..0000000 --- a/sim/testsuite/sim/v850/shl.cgs +++ /dev/null @@ -1,75 +0,0 @@ -# v850 shl -# mach: all - - .include "testutils.inc" - -# CY is set to 1 if the bit shifted out last is 1, else 0 -# OV is set to zero. -# Z is set if the result is 0, else 0 - - noflags - seti 1, r1 - seti 0x00000000, r2 - shl r1, r2 - - flags z - reg r2, 0 - - noflags - seti 1, r1 - seti 0x80000000, r2 - shl r1, r2 - - flags c + z - reg r2, 0 - - noflags - seti 0x00000000, r2 - shl 1, r2 - - flags z - reg r2, 0 - - noflags - seti 0x80000000, r2 - shl 1, r2 - - flags c + z - reg r2, 0 - -# However, if the number of shifts is 0, CY is 0. - - noflags - seti 0, r1 - seti 0xffffffff, r2 - shl r1, r2 - - flags s - reg r2, 0xffffffff - - noflags - seti 0xffffffff, r2 - shl 0, r2 - - flags s - reg r2, 0xffffffff - -# Zero is shifted into the LSB -# S is 1 if the result is negative, else 0 - - noflags - seti 1, r1 - seti 0x4000000f, r2 - shl r1, r2 - - flags s - reg r2, 0x8000001e - - noflags - seti 0x4000000f, r2 - shl 1, r2 - - flags s - reg r2, 0x8000001e - - pass diff --git a/sim/testsuite/sim/v850/shr.cgs b/sim/testsuite/sim/v850/shr.cgs deleted file mode 100644 index e4fdc38..0000000 --- a/sim/testsuite/sim/v850/shr.cgs +++ /dev/null @@ -1,91 +0,0 @@ -# v850 shr -# mach: all - - .include "testutils.inc" - -# CY is set to 1 if the bit shifted out last is 1, else 0 -# OV is set to zero. -# Z is set if the result is 0, else 0 - - noflags - seti 4, r1 - seti 0x00000000, r2 - shr r1, r2 - - flags z - reg r2, 0 - - noflags - seti 4, r1 - seti 0x00000001, r2 - shr r1, r2 - - flags z - reg r2, 0 - - noflags - seti 4, r1 - seti 0x00000008, r2 - shr r1, r2 - - flags c + z - reg r2, 0 - - noflags - seti 0x00000000, r2 - shr 4, r2 - - flags z - reg r2, 0 - - noflags - seti 0x00000001, r2 - shr 4, r2 - - flags z - reg r2, 0 - - noflags - seti 0x00000008, r2 - shr 4, r2 - - flags c + z - reg r2, 0 - -# However, if the number of shifts is 0, CY is 0. - - noflags - seti 0, r1 - seti 0xffffffff, r2 - shr r1, r2 - - flags s - reg r2, 0xffffffff - - noflags - seti 0xffffffff, r2 - shr 0, r2 - - flags s - reg r2, 0xffffffff - -# Zere is shifted into the MSB -# S is 1 if the result is negative, else 0 - - noflags - seti 1, r1 - seti 0x80000000, r2 - shr r1, r2 - - flags 0 - reg r2, 0x40000000 - - noflags - seti 1, r1 - seti 0x40000000, r2 - shr r1, r2 - - flags 0 - reg r2, 0x20000000 - - pass diff --git a/sim/testsuite/sim/v850/testutils.cgs b/sim/testsuite/sim/v850/testutils.cgs deleted file mode 100644 index 12b5611..0000000 --- a/sim/testsuite/sim/v850/testutils.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# v850 test framework -# mach: all - - .include "testutils.inc" - -# This just makes sure that a passing test will pass. - - seti 0x12345678, r1 - - reg r1, 0x12345678 - - pass diff --git a/sim/testsuite/sim/v850/testutils.inc b/sim/testsuite/sim/v850/testutils.inc deleted file mode 100644 index e496698..0000000 --- a/sim/testsuite/sim/v850/testutils.inc +++ /dev/null @@ -1,205 +0,0 @@ -SYS_exit = 1 -SYS_write = 4 - - .bss - .space 64 -_stack: - - .data -pass_text: - .string "pass\n" -fail_text: - .string "fail\n" - - .text - .global _start -_start: - movhi hi(_stack), r0, sp - movea lo(_stack), sp, sp - jr start_test - - .macro seti val reg - movhi hi(\val),r0,\reg - movea lo(\val),\reg,\reg - .endm - -_pass_1: - mov SYS_write,r6 - mov 1,r7 - seti pass_text,r8 - mov 5,r9 - trap 31 - - mov 0, r7 - jr _exit - -_fail_1: - mov SYS_write,r6 - mov 1,r7 - seti fail_text,r8 - mov 5,r9 - trap 31 - - mov 1, r7 - jr _exit - -_exit: - mov SYS_exit, r6 - mov 0, r8 - mov 0, r9 - trap 31 - -_pass: - jr _pass_1 - -_fail: - jr _fail_1 - - .macro pass - jr _pass - .endm - .macro fail - jr _fail - .endm - - # These pass or fail if the given flag is set or not set - # Currently, it assumed that the code of any test is going to - # be less than 256 bytes. Else, we'll have to use a - # branch-around-jump design instead. - - .macro pass_c - bc _pass - .endm - .macro fail_c - bc _fail - .endm - .macro pass_nc - bnc _pass - .endm - .macro fail_nc - bnc _fail - .endm - - .macro pass_z - bz _pass - .endm - .macro fail_z - bz _fail - .endm - .macro pass_nz - bnz _pass - .endm - .macro fail_nz - bnz _fail - .endm - - .macro pass_v - bv _pass - .endm - .macro fail_v - bv _fail - .endm - .macro pass_nv - bnv _pass - .endm - .macro fail_nv - bnv _fail - .endm - - .macro pass_s - bn _pass - .endm - .macro fail_s - bn _fail - .endm - .macro pass_ns - bp _pass - .endm - .macro fail_ns - bp _fail - .endm - - .macro pass_sat - bsa _pass - .endm - .macro fail_sat - bsa _fail - .endm - .macro pass_nsat - bsa 1f - br _pass -1: - .endm - .macro fail_nsat - bsa 1f - br _fail -1: - .endm - - # These pass/fail if the given register has/hasn't the specified value in it. - - .macro pass_req reg val - seti \val,r10 - cmp r10,\reg - be _pass - .endm - - .macro pass_rne reg val - seti \val,r10 - cmp r10,\reg - bne _pass - .endm - - .macro fail_req reg val - seti \val,r10 - cmp r10,\reg - be _fail - .endm - - .macro fail_rne reg val - seti \val,r10 - cmp r10,\reg - bne _fail - .endm - -# convenience version - .macro reg reg val - seti \val,r10 - cmp r10,\reg - bne _fail - .endm - -z = 1 -nz = 0 -s = 2 -ns = 0 -v = 4 -nv = 0 -c = 8 -nc = 0 -sat = 16 -nsat = 0 - -# sat c v s z - - .macro flags fval - stsr psw, r10 - movea +(\fval), r0, r9 - andi 31, r10, r10 - cmp r9, r10 - bne _fail - .endm - - .macro noflags - stsr psw, r10 - andi ~0x1f, r10, r10 - ldsr r10, psw - .endm - - .macro allflags - stsr psw, r10 - ori 0x1f, r10, r10 - ldsr r10, psw - .endm - -start_test: diff --git a/sim/testsuite/v850/ChangeLog b/sim/testsuite/v850/ChangeLog new file mode 100644 index 0000000..2508dfd --- /dev/null +++ b/sim/testsuite/v850/ChangeLog @@ -0,0 +1,19 @@ +2008-02-05 DJ Delorie + + * .: New directory. + * allinsns.exp: New. + * bsh.cgs: New. + * div.cgs: New. + * divh.cgs: New. + * divh_3.cgs: New. + * divhu.cgs: New. + * divu.cgs: New. + * sar.cgs: New. + * satadd.cgs: New. + * satsub.cgs: New. + * satsubi.cgs: New. + * satsubr.cgs: New. + * shl.cgs: New. + * shr.cgs: New. + * testutils.cgs: New. + * testutils.inc: New. diff --git a/sim/testsuite/v850/allinsns.exp b/sim/testsuite/v850/allinsns.exp new file mode 100644 index 0000000..f60c3d6 --- /dev/null +++ b/sim/testsuite/v850/allinsns.exp @@ -0,0 +1,39 @@ +# v850 simulator testsuite. + +if [istarget v850*-*] { + global opt + + # load support procs (none yet) + # load_lib cgen.exp + # all machines + + switch -regexp -- $opt { + .*v850e.* { + set all_machs "v850e" + } + default { + set all_machs "v850" + } + } + # gas doesn't support any '=' option for v850. + #set cpu_option -m + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} + +#foreach var [lsort [info globals]] { +# if [array exists ::$var] { +# puts [format "%-27s %s" $var Array:] +# continue +# } +# puts [format "%-30s %s" $var "[set ::$var]"] +#} + \ No newline at end of file diff --git a/sim/testsuite/v850/bsh.cgs b/sim/testsuite/v850/bsh.cgs new file mode 100644 index 0000000..e9d216e --- /dev/null +++ b/sim/testsuite/v850/bsh.cgs @@ -0,0 +1,55 @@ +# v850 bsh +# mach: v850e +# as(v850e): -mv850e + + .include "testutils.inc" + + seti 0x12345678, r1 + bsh r1, r2 + + flags 0 + reg r2, 0x34127856 + +# CY is 1 if one or more bytes in the result half-word is zero, else 0 + + seti 0x12345600, r1 + bsh r1, r2 + flags c + reg r2, 0x34120056 + + seti 0x12340078, r1 + bsh r1, r2 + flags c + reg r2, 0x34127800 + + seti 0x12005678, r1 + bsh r1, r2 + flags 0 + reg r2, 0x00127856 + + seti 0x00345678, r1 + bsh r1, r2 + flags 0 + reg r2, 0x34007856 + +# S is set if the result is negative + + seti 0x00800000, r1 + bsh r1, r2 + flags s + c + z + reg r2, 0x80000000 + +# Z is set if the result is zero +# According to NEC, the Z flag depends on only the lower half-word + + seti 0x00000000, r1 + bsh r1, r2 + flags c + z + reg r2, 0x00000000 + + seti 0xffff0000, r1 + bsh r1, r2 + flags c + s + z + reg r2, 0xffff0000 + + pass diff --git a/sim/testsuite/v850/div.cgs b/sim/testsuite/v850/div.cgs new file mode 100644 index 0000000..16683f1 --- /dev/null +++ b/sim/testsuite/v850/div.cgs @@ -0,0 +1,118 @@ +# v850 div +# mach: v850e +# as(v850e): -mv850e + + .include "testutils.inc" + +# Regular division - check signs +# The S flag is based on the quotient, not the remainder + + seti 6, r1 + seti 45, r2 + div r1, r2, r3 + + flags 0 + reg r1, 6 + reg r2, 7 + reg r3, 3 + + seti -6, r1 + seti 45, r2 + div r1, r2, r3 + + flags s + reg r1, -6 + reg r2, -7 + reg r3, 3 + + seti 6, r1 + seti -45, r2 + div r1, r2, r3 + + flags s + reg r1, 6 + reg r2, -7 + reg r3, -3 + + seti -6, r1 + seti -45, r2 + div r1, r2, r3 + + flags 0 + reg r1, -6 + reg r2, 7 + reg r3, -3 + +# If the data is divided by zero, OV=1 and the quotient is undefined. +# According to NEC, the S and Z flags, and the output registers, are +# unchanged. + + noflags + seti 0, r1 + seti 45, r2 + seti 67, r3 + div r1, r2, r3 + + flags v + reg r2, 45 + reg r3, 67 + + allflags + seti 0, r1 + seti 45, r2 + seti 67, r3 + div r1, r2, r3 + + flags sat + c + v + s + z + reg r2, 45 + reg r3, 67 + +# Zero / (N!=0) => normal + + noflags + seti 45, r1 + seti 0, r2 + seti 67, r3 + div r1, r2, r3 + + flags z + reg r1, 45 + reg r2, 0 + reg r3, 0 + +# Test for regular overflow + + noflags + seti -1, r1 + seti 0x80000000, r2 + seti 67, r3 + div r1, r2, r3 + + flags v + s + reg r1, -1 + reg r2, 0x80000000 + reg r3, 0 + +# The Z flag is based on the quotient, not the remainder + + noflags + seti 45, r1 + seti 16, r2 + div r1, r2, r3 + + flags z + reg r2, 0 + reg r3, 16 + +# If the quot and rem registers are the same, the remainder is stored. + + seti 6, r1 + seti 45, r2 + div r1, r2, r2 + + flags 0 + reg r1, 6 + reg r2, 3 + + + pass diff --git a/sim/testsuite/v850/divh.cgs b/sim/testsuite/v850/divh.cgs new file mode 100644 index 0000000..1cef7f9 --- /dev/null +++ b/sim/testsuite/v850/divh.cgs @@ -0,0 +1,96 @@ +# v850 divh +# mach: all + + .include "testutils.inc" + +# Regular division - check signs + + seti 6, r1 + seti 45, r2 + divh r1, r2 + + flags 0 + reg r1, 6 + reg r2, 7 + + seti -6, r1 + seti 45, r2 + divh r1, r2 + + flags s + reg r1, -6 + reg r2, -7 + + seti 6, r1 + seti -45, r2 + divh r1, r2 + + flags s + reg r1, 6 + reg r2, -7 + + seti -6, r1 + seti -45, r2 + divh r1, r2 + + flags 0 + reg r1, -6 + reg r2, 7 + +# Only the lower half of the dividend is used + + seti 0x0000fffa, r1 + seti -45, r2 + divh r1, r2 + + flags 0 + reg r1, 0x0000fffa + reg r2, 7 + +# If the data is divhided by zero, OV=1 and the quotient is undefined. +# According to NEC, the S and Z flags, and the output registers, are +# unchanged. + + noflags + seti 0, r1 + seti 45, r2 + seti 67, r3 + divh r1, r2 + + flags v + reg r2, 45 + + allflags + seti 0, r1 + seti 45, r2 + seti 67, r3 + divh r1, r2 + + flags sat + c + v + s + z + reg r2, 45 + +# Zero / (N!=0) => normal + + noflags + seti 45, r1 + seti 0, r2 + seti 67, r3 + divh r1, r2 + + flags z + reg r1, 45 + reg r2, 0 + +# Test for regular overflow + + noflags + seti -1, r1 + seti 0x80000000, r2 + divh r1, r2 + + flags v + s + reg r1, -1 + reg r2, 0x80000000 + + + pass diff --git a/sim/testsuite/v850/divh_3.cgs b/sim/testsuite/v850/divh_3.cgs new file mode 100644 index 0000000..77d14af --- /dev/null +++ b/sim/testsuite/v850/divh_3.cgs @@ -0,0 +1,130 @@ +# v850 divh_3 +# mach: v850e +# as(v850e): -mv850e + + .include "testutils.inc" + +# Regular divhision - check signs +# The S flag is based on the quotient, not the remainder + + seti 6, r1 + seti 45, r2 + divh r1, r2, r3 + + flags 0 + reg r1, 6 + reg r2, 7 + reg r3, 3 + + seti -6, r1 + seti 45, r2 + divh r1, r2, r3 + + flags s + reg r1, -6 + reg r2, -7 + reg r3, 3 + + seti 6, r1 + seti -45, r2 + divh r1, r2, r3 + + flags s + reg r1, 6 + reg r2, -7 + reg r3, -3 + + seti -6, r1 + seti -45, r2 + divh r1, r2, r3 + + flags 0 + reg r1, -6 + reg r2, 7 + reg r3, -3 + +# Only the lower half of the dividend is used + + seti 0x0000fffa, r1 + seti -45, r2 + divh r1, r2, r3 + + flags 0 + reg r1, 0x0000fffa + reg r2, 7 + reg r3, -3 + + +# If the data is divhided by zero, OV=1 and the quotient is undefined. +# According to NEC, the S and Z flags, and the output registers, are +# unchanged. + + noflags + seti 0, r1 + seti 45, r2 + seti 67, r3 + divh r1, r2, r3 + + flags v + reg r2, 45 + reg r3, 67 + + allflags + seti 0, r1 + seti 45, r2 + seti 67, r3 + divh r1, r2, r3 + + flags sat + c + v + s + z + reg r2, 45 + reg r3, 67 + +# Zero / (N!=0) => normal + + noflags + seti 45, r1 + seti 0, r2 + seti 67, r3 + divh r1, r2, r3 + + flags z + reg r1, 45 + reg r2, 0 + reg r3, 0 + +# Test for regular overflow + + noflags + seti -1, r1 + seti 0x80000000, r2 + seti 67, r3 + divh r1, r2, r3 + + flags v + s + reg r1, -1 + reg r2, 0x80000000 + reg r3, 0 + +# The Z flag is based on the quotient, not the remainder + + noflags + seti 45, r1 + seti 16, r2 + divh r1, r2, r3 + + flags z + reg r2, 0 + reg r3, 16 + +# If the quot and rem registers are the same, the remainder is stored. + + seti 6, r1 + seti 45, r2 + divh r1, r2, r2 + + flags 0 + reg r1, 6 + reg r2, 3 + + + pass diff --git a/sim/testsuite/v850/divhu.cgs b/sim/testsuite/v850/divhu.cgs new file mode 100644 index 0000000..911e96e --- /dev/null +++ b/sim/testsuite/v850/divhu.cgs @@ -0,0 +1,94 @@ +# v850 divu +# mach: v850e +# as(v850e): -mv850e + + .include "testutils.inc" + + seti 6, r1 + seti 45, r2 + divu r1, r2, r3 + + flags 0 + reg r1, 6 + reg r2, 7 + reg r3, 3 + + seti 4, r1 + seti 0x40000000, r2 + divu r1, r2, r3 + + flags 0 + reg r1, 4 + reg r2, 0x10000000 + reg r3, 0 + +# Only the lower half of the dividend is used + + seti 0x00010006, r1 + seti 45, r2 + divhu r1, r2, r3 + + flags 0 + reg r1, 0x00010006 + reg r2, 7 + reg r3, 3 + +# If the data is divided by zero, OV=1 and the quotient is undefined. +# According to NEC, the S and Z flags, and the output registers, are +# unchanged. + + noflags + seti 0, r1 + seti 45, r2 + seti 67, r3 + divu r1, r2, r3 + + flags v + reg r2, 45 + reg r3, 67 + + allflags + seti 0, r1 + seti 45, r2 + seti 67, r3 + divu r1, r2, r3 + + flags sat + c + v + s + z + reg r2, 45 + reg r3, 67 + +# Zero / (N!=0) => normal + + noflags + seti 45, r1 + seti 0, r2 + seti 67, r3 + divu r1, r2, r3 + + flags z + reg r1, 45 + reg r2, 0 + reg r3, 0 + +# The Z flag is based on the quotient, not the remainder + + noflags + seti 45, r1 + seti 16, r2 + divu r1, r2, r3 + + flags z + reg r2, 0 + reg r3, 16 + +# If the quot and rem registers are the same, the remainder is stored. + + seti 6, r1 + seti 45, r2 + divu r1, r2, r2 + + flags 0 + reg r1, 6 + reg r2, 3 + + pass diff --git a/sim/testsuite/v850/divu.cgs b/sim/testsuite/v850/divu.cgs new file mode 100644 index 0000000..fb44185 --- /dev/null +++ b/sim/testsuite/v850/divu.cgs @@ -0,0 +1,83 @@ +# v850 divu +# mach: v850e +# as(v850e): -mv850e + + .include "testutils.inc" + + seti 6, r1 + seti 45, r2 + divu r1, r2, r3 + + flags 0 + reg r1, 6 + reg r2, 7 + reg r3, 3 + + seti 4, r1 + seti 0x40000000, r2 + divu r1, r2, r3 + + flags 0 + reg r1, 4 + reg r2, 0x10000000 + reg r3, 0 + +# If the data is divided by zero, OV=1 and the quotient is undefined. +# According to NEC, the S and Z flags, and the output registers, are +# unchanged. + + noflags + seti 0, r1 + seti 45, r2 + seti 67, r3 + divu r1, r2, r3 + + flags v + reg r2, 45 + reg r3, 67 + + allflags + seti 0, r1 + seti 45, r2 + seti 67, r3 + divu r1, r2, r3 + + flags sat + c + v + s + z + reg r2, 45 + reg r3, 67 + +# Zero / (N!=0) => normal + + noflags + seti 45, r1 + seti 0, r2 + seti 67, r3 + divu r1, r2, r3 + + flags z + reg r1, 45 + reg r2, 0 + reg r3, 0 + +# The Z flag is based on the quotient, not the remainder + + noflags + seti 45, r1 + seti 16, r2 + divu r1, r2, r3 + + flags z + reg r2, 0 + reg r3, 16 + +# If the quot and rem registers are the same, the remainder is stored. + + seti 6, r1 + seti 45, r2 + divu r1, r2, r2 + + flags 0 + reg r1, 6 + reg r2, 3 + + pass diff --git a/sim/testsuite/v850/sar.cgs b/sim/testsuite/v850/sar.cgs new file mode 100644 index 0000000..4372e6c --- /dev/null +++ b/sim/testsuite/v850/sar.cgs @@ -0,0 +1,91 @@ +# v850 sar +# mach: all + + .include "testutils.inc" + +# CY is set to 1 if the bit shifted out last is 1, else 0 +# OV is set to zero. +# Z is set if the result is 0, else 0 + + noflags + seti 4, r1 + seti 0x00000000, r2 + sar r1, r2 + + flags z + reg r2, 0 + + noflags + seti 4, r1 + seti 0x00000001, r2 + sar r1, r2 + + flags z + reg r2, 0 + + noflags + seti 4, r1 + seti 0x00000008, r2 + sar r1, r2 + + flags c + z + reg r2, 0 + + noflags + seti 0x00000000, r2 + sar 4, r2 + + flags z + reg r2, 0 + + noflags + seti 0x00000001, r2 + sar 4, r2 + + flags z + reg r2, 0 + + noflags + seti 0x00000008, r2 + sar 4, r2 + + flags c + z + reg r2, 0 + +# However, if the number of shifts is 0, CY is 0. + + noflags + seti 0, r1 + seti 0xffffffff, r2 + sar r1, r2 + + flags s + reg r2, 0xffffffff + + noflags + seti 0xffffffff, r2 + sar 0, r2 + + flags s + reg r2, 0xffffffff + +# Old MSB is copied as new MSB after shift +# S is 1 if the result is negative, else 0 + + noflags + seti 1, r1 + seti 0x80000000, r2 + sar r1, r2 + + flags s + reg r2, 0xc0000000 + + noflags + seti 1, r1 + seti 0x40000000, r2 + sar r1, r2 + + flags 0 + reg r2, 0x20000000 + + pass diff --git a/sim/testsuite/v850/satadd.cgs b/sim/testsuite/v850/satadd.cgs new file mode 100644 index 0000000..60ac654 --- /dev/null +++ b/sim/testsuite/v850/satadd.cgs @@ -0,0 +1,79 @@ +# v850 satadd +# mach: all + + .include "testutils.inc" + +# If the result of the add is "negative", that means we went too +# positive. The result should be the most positive number. + + noflags + seti 0x70000000, r1 + seti 0x70000000, r2 + satadd r1, r2 + + flags sat + nc + v + ns + nz + reg r2, 0x7fffffff + + noflags + seti 0x7ffffffe, r1 + satadd 10, r1 + + flags sat + nc + v + ns + nz + reg r1, 0x7fffffff + +# Similarly, if the result of the add is "positive", that means we +# went too negative. The result should be the most negative number. + + noflags + seti 0x90000000, r1 + seti 0x90000000, r2 + satadd r1, r2 + + flags sat + c + v + s + nz + reg r2, 0x80000000 + + noflags + seti 0x80000001, r1 + satadd -10, r1 + + flags sat + c + v + s + nz + reg r1, 0x80000000 + +# Check that the SAT flag remains set until reset + + seti 1, r1 + seti 2, r2 + satadd r1,r2 + + flags sat + nc + nv + ns + nz + reg r2, 3 + + noflags + seti 1, r1 + seti 2, r2 + satadd r1,r2 + + flags nsat + nc + nv + ns + nz + reg r2, 3 + +# Check that results exactly equal to min/max don't saturate + + noflags + seti 0x70000000, r1 + seti 0x0fffffff, r2 + satadd r1,r2 + + flags nsat + nc + nv + ns + nz + reg r2, 0x7fffffff + + + noflags + seti 0x90000000, r1 + seti 0xf0000000, r2 + satadd r1,r2 + + flags nsat + c + nv + s + nz + reg r2, 0x80000000 + + + pass diff --git a/sim/testsuite/v850/satsub.cgs b/sim/testsuite/v850/satsub.cgs new file mode 100644 index 0000000..b7085e7 --- /dev/null +++ b/sim/testsuite/v850/satsub.cgs @@ -0,0 +1,65 @@ +# v850 satsub +# mach: all + + .include "testutils.inc" + +# If the result of the add is "negative", that means we went too +# positive. The result should be the most positive number. + + noflags + seti 0x90000000, r1 + seti 0x70000000, r2 + satsub r1, r2 + + flags sat + c + v + ns + nz + reg r2, 0x7fffffff + +# Similarly, if the result of the add is "positive", that means we +# went too negative. The result should be the most negative number. + + noflags + seti 0x70000000, r1 + seti 0x90000000, r2 + satsub r1, r2 + + flags sat + nc + v + s + nz + reg r2, 0x80000000 + +# Check that the SAT flag remains set until reset + + seti 1, r1 + seti 2, r2 + satsub r1,r2 + + flags sat + nc + nv + ns + nz + reg r2, 1 + + noflags + seti 1, r1 + seti 2, r2 + satsub r1,r2 + + flags nsat + nc + nv + ns + nz + reg r2, 1 + +# Check that results exactly equal to min/max don't saturate + + noflags + seti 0x90000000, r1 + seti 0x0fffffff, r2 + satsub r1,r2 + + flags nsat + c + nv + ns + nz + reg r2, 0x7fffffff + + + noflags + seti 0x70000000, r1 + seti 0xf0000000, r2 + satsub r1,r2 + + flags nsat + nc + nv + s + nz + reg r2, 0x80000000 + + + pass diff --git a/sim/testsuite/v850/satsubi.cgs b/sim/testsuite/v850/satsubi.cgs new file mode 100644 index 0000000..b86b26d --- /dev/null +++ b/sim/testsuite/v850/satsubi.cgs @@ -0,0 +1,59 @@ +# v850 satsubi +# mach: all + + .include "testutils.inc" + +# If the result of the add is "negative", that means we went too +# positive. The result should be the most positive number. + + noflags + seti 0x7ffffffe, r1 + satsubi -10, r1, r2 + + flags sat + c + v + ns + nz + reg r2, 0x7fffffff + +# Similarly, if the result of the add is "positive", that means we +# went too negative. The result should be the most negative number. + + noflags + seti 0x80000001, r1 + satsubi 10, r1, r2 + + flags sat + nc + v + s + nz + reg r2, 0x80000000 + +# Check that the SAT flag remains set until reset + + seti 2, r1 + satsubi 1, r1, r2 + + flags sat + nc + nv + ns + nz + reg r2, 1 + + noflags + seti 2, r1 + satsubi 1, r1, r2 + + flags nsat + nc + nv + ns + nz + reg r2, 1 + +# Check that results exactly equal to min/max don't saturate + + noflags + seti 0x7ffffffe, r1 + satsubi -1, r1, r2 + + flags nsat + c + nv + ns + nz + reg r2, 0x7fffffff + + + noflags + seti 0x80000001, r1 + satsubi 1, r1, r2 + + flags nsat + nc + nv + s + nz + reg r2, 0x80000000 + + + pass diff --git a/sim/testsuite/v850/satsubr.cgs b/sim/testsuite/v850/satsubr.cgs new file mode 100644 index 0000000..7e91e0c --- /dev/null +++ b/sim/testsuite/v850/satsubr.cgs @@ -0,0 +1,65 @@ +# v850 satsub +# mach: all + + .include "testutils.inc" + +# If the result of the add is "negative", that means we went too +# positive. The result should be the most positive number. + + noflags + seti 0x90000000, r1 + seti 0x70000000, r2 + satsubr r2, r1 + + flags sat + c + v + ns + nz + reg r1, 0x7fffffff + +# Similarly, if the result of the add is "positive", that means we +# went too negative. The result should be the most negative number. + + noflags + seti 0x70000000, r1 + seti 0x90000000, r2 + satsubr r2, r1 + + flags sat + nc + v + s + nz + reg r1, 0x80000000 + +# Check that the SAT flag remains set until reset + + seti 1, r1 + seti 2, r2 + satsubr r2, r1 + + flags sat + nc + nv + ns + nz + reg r1, 1 + + noflags + seti 1, r1 + seti 2, r2 + satsubr r2, r1 + + flags nsat + nc + nv + ns + nz + reg r1, 1 + +# Check that results exactly equal to min/max don't saturate + + noflags + seti 0x90000000, r1 + seti 0x0fffffff, r2 + satsubr r2, r1 + + flags nsat + c + nv + ns + nz + reg r1, 0x7fffffff + + + noflags + seti 0x70000000, r1 + seti 0xf0000000, r2 + satsubr r2, r1 + + flags nsat + nc + nv + s + nz + reg r1, 0x80000000 + + + pass diff --git a/sim/testsuite/v850/shl.cgs b/sim/testsuite/v850/shl.cgs new file mode 100644 index 0000000..6ad8213 --- /dev/null +++ b/sim/testsuite/v850/shl.cgs @@ -0,0 +1,75 @@ +# v850 shl +# mach: all + + .include "testutils.inc" + +# CY is set to 1 if the bit shifted out last is 1, else 0 +# OV is set to zero. +# Z is set if the result is 0, else 0 + + noflags + seti 1, r1 + seti 0x00000000, r2 + shl r1, r2 + + flags z + reg r2, 0 + + noflags + seti 1, r1 + seti 0x80000000, r2 + shl r1, r2 + + flags c + z + reg r2, 0 + + noflags + seti 0x00000000, r2 + shl 1, r2 + + flags z + reg r2, 0 + + noflags + seti 0x80000000, r2 + shl 1, r2 + + flags c + z + reg r2, 0 + +# However, if the number of shifts is 0, CY is 0. + + noflags + seti 0, r1 + seti 0xffffffff, r2 + shl r1, r2 + + flags s + reg r2, 0xffffffff + + noflags + seti 0xffffffff, r2 + shl 0, r2 + + flags s + reg r2, 0xffffffff + +# Zero is shifted into the LSB +# S is 1 if the result is negative, else 0 + + noflags + seti 1, r1 + seti 0x4000000f, r2 + shl r1, r2 + + flags s + reg r2, 0x8000001e + + noflags + seti 0x4000000f, r2 + shl 1, r2 + + flags s + reg r2, 0x8000001e + + pass diff --git a/sim/testsuite/v850/shr.cgs b/sim/testsuite/v850/shr.cgs new file mode 100644 index 0000000..e4fdc38 --- /dev/null +++ b/sim/testsuite/v850/shr.cgs @@ -0,0 +1,91 @@ +# v850 shr +# mach: all + + .include "testutils.inc" + +# CY is set to 1 if the bit shifted out last is 1, else 0 +# OV is set to zero. +# Z is set if the result is 0, else 0 + + noflags + seti 4, r1 + seti 0x00000000, r2 + shr r1, r2 + + flags z + reg r2, 0 + + noflags + seti 4, r1 + seti 0x00000001, r2 + shr r1, r2 + + flags z + reg r2, 0 + + noflags + seti 4, r1 + seti 0x00000008, r2 + shr r1, r2 + + flags c + z + reg r2, 0 + + noflags + seti 0x00000000, r2 + shr 4, r2 + + flags z + reg r2, 0 + + noflags + seti 0x00000001, r2 + shr 4, r2 + + flags z + reg r2, 0 + + noflags + seti 0x00000008, r2 + shr 4, r2 + + flags c + z + reg r2, 0 + +# However, if the number of shifts is 0, CY is 0. + + noflags + seti 0, r1 + seti 0xffffffff, r2 + shr r1, r2 + + flags s + reg r2, 0xffffffff + + noflags + seti 0xffffffff, r2 + shr 0, r2 + + flags s + reg r2, 0xffffffff + +# Zere is shifted into the MSB +# S is 1 if the result is negative, else 0 + + noflags + seti 1, r1 + seti 0x80000000, r2 + shr r1, r2 + + flags 0 + reg r2, 0x40000000 + + noflags + seti 1, r1 + seti 0x40000000, r2 + shr r1, r2 + + flags 0 + reg r2, 0x20000000 + + pass diff --git a/sim/testsuite/v850/testutils.cgs b/sim/testsuite/v850/testutils.cgs new file mode 100644 index 0000000..12b5611 --- /dev/null +++ b/sim/testsuite/v850/testutils.cgs @@ -0,0 +1,12 @@ +# v850 test framework +# mach: all + + .include "testutils.inc" + +# This just makes sure that a passing test will pass. + + seti 0x12345678, r1 + + reg r1, 0x12345678 + + pass diff --git a/sim/testsuite/v850/testutils.inc b/sim/testsuite/v850/testutils.inc new file mode 100644 index 0000000..e496698 --- /dev/null +++ b/sim/testsuite/v850/testutils.inc @@ -0,0 +1,205 @@ +SYS_exit = 1 +SYS_write = 4 + + .bss + .space 64 +_stack: + + .data +pass_text: + .string "pass\n" +fail_text: + .string "fail\n" + + .text + .global _start +_start: + movhi hi(_stack), r0, sp + movea lo(_stack), sp, sp + jr start_test + + .macro seti val reg + movhi hi(\val),r0,\reg + movea lo(\val),\reg,\reg + .endm + +_pass_1: + mov SYS_write,r6 + mov 1,r7 + seti pass_text,r8 + mov 5,r9 + trap 31 + + mov 0, r7 + jr _exit + +_fail_1: + mov SYS_write,r6 + mov 1,r7 + seti fail_text,r8 + mov 5,r9 + trap 31 + + mov 1, r7 + jr _exit + +_exit: + mov SYS_exit, r6 + mov 0, r8 + mov 0, r9 + trap 31 + +_pass: + jr _pass_1 + +_fail: + jr _fail_1 + + .macro pass + jr _pass + .endm + .macro fail + jr _fail + .endm + + # These pass or fail if the given flag is set or not set + # Currently, it assumed that the code of any test is going to + # be less than 256 bytes. Else, we'll have to use a + # branch-around-jump design instead. + + .macro pass_c + bc _pass + .endm + .macro fail_c + bc _fail + .endm + .macro pass_nc + bnc _pass + .endm + .macro fail_nc + bnc _fail + .endm + + .macro pass_z + bz _pass + .endm + .macro fail_z + bz _fail + .endm + .macro pass_nz + bnz _pass + .endm + .macro fail_nz + bnz _fail + .endm + + .macro pass_v + bv _pass + .endm + .macro fail_v + bv _fail + .endm + .macro pass_nv + bnv _pass + .endm + .macro fail_nv + bnv _fail + .endm + + .macro pass_s + bn _pass + .endm + .macro fail_s + bn _fail + .endm + .macro pass_ns + bp _pass + .endm + .macro fail_ns + bp _fail + .endm + + .macro pass_sat + bsa _pass + .endm + .macro fail_sat + bsa _fail + .endm + .macro pass_nsat + bsa 1f + br _pass +1: + .endm + .macro fail_nsat + bsa 1f + br _fail +1: + .endm + + # These pass/fail if the given register has/hasn't the specified value in it. + + .macro pass_req reg val + seti \val,r10 + cmp r10,\reg + be _pass + .endm + + .macro pass_rne reg val + seti \val,r10 + cmp r10,\reg + bne _pass + .endm + + .macro fail_req reg val + seti \val,r10 + cmp r10,\reg + be _fail + .endm + + .macro fail_rne reg val + seti \val,r10 + cmp r10,\reg + bne _fail + .endm + +# convenience version + .macro reg reg val + seti \val,r10 + cmp r10,\reg + bne _fail + .endm + +z = 1 +nz = 0 +s = 2 +ns = 0 +v = 4 +nv = 0 +c = 8 +nc = 0 +sat = 16 +nsat = 0 + +# sat c v s z + + .macro flags fval + stsr psw, r10 + movea +(\fval), r0, r9 + andi 31, r10, r10 + cmp r9, r10 + bne _fail + .endm + + .macro noflags + stsr psw, r10 + andi ~0x1f, r10, r10 + ldsr r10, psw + .endm + + .macro allflags + stsr psw, r10 + ori 0x1f, r10, r10 + ldsr r10, psw + .endm + +start_test: -- cgit v1.1